Vendor import of llvm trunk r238337:vendor/llvm/llvm-trunk-r238337

https://llvm.org/svn/llvm-project/llvm/trunk@238337

7356 files changed, 270580 insertions, 111691 deletions

diff --git a/test/Analysis/AssumptionCache/basic.ll b/test/Analysis/AssumptionCache/basic.ll
new file mode 100644
index 000000000000..bd4e7b6449fb
--- /dev/null
+++ b/test/Analysis/AssumptionCache/basic.ll
@@ -0,0 +1,22 @@
+; RUN: opt < %s -disable-output -passes='print<assumptions>' 2>&1 | FileCheck %s
+
+target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
+
+declare void @llvm.assume(i1)
+
+define void @test1(i32 %a) {
+; CHECK-LABEL: Cached assumptions for function: test1
+; CHECK-NEXT: icmp ne i32 %{{.*}}, 0
+; CHECK-NEXT: icmp slt i32 %{{.*}}, 0
+; CHECK-NEXT: icmp sgt i32 %{{.*}}, 0
+
+entry:
+  %cond1 = icmp ne i32 %a, 0
+  call void @llvm.assume(i1 %cond1)
+  %cond2 = icmp slt i32 %a, 0
+  call void @llvm.assume(i1 %cond2)
+  %cond3 = icmp sgt i32 %a, 0
+  call void @llvm.assume(i1 %cond3)
+
+  ret void
+}
diff --git a/test/Analysis/BasicAA/2003-02-26-AccessSizeTest.ll b/test/Analysis/BasicAA/2003-02-26-AccessSizeTest.ll
index 45f6088eaf0c..d712e33b8c0a 100644
--- a/test/Analysis/BasicAA/2003-02-26-AccessSizeTest.ll
+++ b/test/Analysis/BasicAA/2003-02-26-AccessSizeTest.ll
@@ -5,15 +5,15 @@
 ; RUN: opt < %s -basicaa -gvn -instcombine -S | FileCheck %s
 
 define i32 @test() {
-; CHECK: %Y.DONOTREMOVE = load i32* %A
+; CHECK: %Y.DONOTREMOVE = load i32, i32* %A
 ; CHECK: %Z = sub i32 0, %Y.DONOTREMOVE
   %A = alloca i32
   store i32 0, i32* %A
-  %X = load i32* %A
+  %X = load i32, i32* %A
   %B = bitcast i32* %A to i8*
-  %C = getelementptr i8* %B, i64 1
+  %C = getelementptr i8, i8* %B, i64 1
   store i8 1, i8* %C    ; Aliases %A
-  %Y.DONOTREMOVE = load i32* %A
+  %Y.DONOTREMOVE = load i32, i32* %A
   %Z = sub i32 %X, %Y.DONOTREMOVE
   ret i32 %Z
 }
diff --git a/test/Analysis/BasicAA/2003-03-04-GEPCrash.ll b/test/Analysis/BasicAA/2003-03-04-GEPCrash.ll
index 4f8eabb79308..5a93b3da054e 100644
--- a/test/Analysis/BasicAA/2003-03-04-GEPCrash.ll
+++ b/test/Analysis/BasicAA/2003-03-04-GEPCrash.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -basicaa -aa-eval -disable-output 2>/dev/null
 ; Test for a bug in BasicAA which caused a crash when querying equality of P1&P2
 define void @test({[2 x i32],[2 x i32]}* %A, i64 %X, i64 %Y) {
-	%P1 = getelementptr {[2 x i32],[2 x i32]}* %A, i64 0, i32 0, i64 %X
-	%P2 = getelementptr {[2 x i32],[2 x i32]}* %A, i64 0, i32 1, i64 %Y
+	%P1 = getelementptr {[2 x i32],[2 x i32]}, {[2 x i32],[2 x i32]}* %A, i64 0, i32 0, i64 %X
+	%P2 = getelementptr {[2 x i32],[2 x i32]}, {[2 x i32],[2 x i32]}* %A, i64 0, i32 1, i64 %Y
 	ret void
 }
diff --git a/test/Analysis/BasicAA/2003-04-22-GEPProblem.ll b/test/Analysis/BasicAA/2003-04-22-GEPProblem.ll
index 78f74a0abe56..96ca071587e6 100644
--- a/test/Analysis/BasicAA/2003-04-22-GEPProblem.ll
+++ b/test/Analysis/BasicAA/2003-04-22-GEPProblem.ll
@@ -4,11 +4,11 @@
 
 define i32 @test(i32 *%Ptr, i64 %V) {
 ; CHECK: sub i32 %X, %Y
-  %P2 = getelementptr i32* %Ptr, i64 1
-  %P1 = getelementptr i32* %Ptr, i64 %V
-  %X = load i32* %P1
+  %P2 = getelementptr i32, i32* %Ptr, i64 1
+  %P1 = getelementptr i32, i32* %Ptr, i64 %V
+  %X = load i32, i32* %P1
   store i32 5, i32* %P2
-  %Y = load i32* %P1
+  %Y = load i32, i32* %P1
   %Z = sub i32 %X, %Y
   ret i32 %Z
 }
diff --git a/test/Analysis/BasicAA/2003-04-25-GEPCrash.ll b/test/Analysis/BasicAA/2003-04-25-GEPCrash.ll
index 97bc38eb69bf..ea26c2200726 100644
--- a/test/Analysis/BasicAA/2003-04-25-GEPCrash.ll
+++ b/test/Analysis/BasicAA/2003-04-25-GEPCrash.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -basicaa -aa-eval -disable-output 2>/dev/null
 ; Test for a bug in BasicAA which caused a crash when querying equality of P1&P2
 define void @test([17 x i16]* %mask_bits) {
-	%P1 = getelementptr [17 x i16]* %mask_bits, i64 0, i64 0
-	%P2 = getelementptr [17 x i16]* %mask_bits, i64 252645134, i64 0
+	%P1 = getelementptr [17 x i16], [17 x i16]* %mask_bits, i64 0, i64 0
+	%P2 = getelementptr [17 x i16], [17 x i16]* %mask_bits, i64 252645134, i64 0
 	ret void
 }
diff --git a/test/Analysis/BasicAA/2003-05-21-GEP-Problem.ll b/test/Analysis/BasicAA/2003-05-21-GEP-Problem.ll
index 8ca346985593..fb5b3bb4618e 100644
--- a/test/Analysis/BasicAA/2003-05-21-GEP-Problem.ll
+++ b/test/Analysis/BasicAA/2003-05-21-GEP-Problem.ll
@@ -6,13 +6,13 @@ define void @table_reindex(%struct..apr_table_t* %t.1) {		; No predecessors!
 	br label %loopentry
 
 loopentry:		; preds = %0, %no_exit
-	%tmp.101 = getelementptr %struct..apr_table_t* %t.1, i64 0, i32 0, i32 2
-	%tmp.11 = load i32* %tmp.101		; <i32> [#uses=0]
+	%tmp.101 = getelementptr %struct..apr_table_t, %struct..apr_table_t* %t.1, i64 0, i32 0, i32 2
+	%tmp.11 = load i32, i32* %tmp.101		; <i32> [#uses=0]
 	br i1 false, label %no_exit, label %UnifiedExitNode
 
 no_exit:		; preds = %loopentry
 	%tmp.25 = sext i32 0 to i64		; <i64> [#uses=1]
-	%tmp.261 = getelementptr %struct..apr_table_t* %t.1, i64 0, i32 3, i64 %tmp.25		; <i32*> [#uses=1]
+	%tmp.261 = getelementptr %struct..apr_table_t, %struct..apr_table_t* %t.1, i64 0, i32 3, i64 %tmp.25		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp.261
 	br label %loopentry
 
diff --git a/test/Analysis/BasicAA/2003-06-01-AliasCrash.ll b/test/Analysis/BasicAA/2003-06-01-AliasCrash.ll
index 0abd3847836c..ace5982afaab 100644
--- a/test/Analysis/BasicAA/2003-06-01-AliasCrash.ll
+++ b/test/Analysis/BasicAA/2003-06-01-AliasCrash.ll
@@ -1,11 +1,11 @@
 ; RUN: opt < %s -basicaa -aa-eval -disable-output 2>/dev/null
 
 define i32 @MTConcat([3 x i32]* %a.1) {
-	%tmp.961 = getelementptr [3 x i32]* %a.1, i64 0, i64 4
-	%tmp.97 = load i32* %tmp.961
-	%tmp.119 = getelementptr [3 x i32]* %a.1, i64 1, i64 0
-	%tmp.120 = load i32* %tmp.119
-	%tmp.1541 = getelementptr [3 x i32]* %a.1, i64 0, i64 4
-	%tmp.155 = load i32* %tmp.1541
+	%tmp.961 = getelementptr [3 x i32], [3 x i32]* %a.1, i64 0, i64 4
+	%tmp.97 = load i32, i32* %tmp.961
+	%tmp.119 = getelementptr [3 x i32], [3 x i32]* %a.1, i64 1, i64 0
+	%tmp.120 = load i32, i32* %tmp.119
+	%tmp.1541 = getelementptr [3 x i32], [3 x i32]* %a.1, i64 0, i64 4
+	%tmp.155 = load i32, i32* %tmp.1541
 	ret i32 0
 }
diff --git a/test/Analysis/BasicAA/2003-07-03-BasicAACrash.ll b/test/Analysis/BasicAA/2003-07-03-BasicAACrash.ll
index 3e813fa2ca18..7aaae2a1927b 100644
--- a/test/Analysis/BasicAA/2003-07-03-BasicAACrash.ll
+++ b/test/Analysis/BasicAA/2003-07-03-BasicAACrash.ll
@@ -4,7 +4,7 @@
 %struct..RefRect = type { %struct..RefPoint, %struct..RefPoint }
 
 define i32 @BMT_CommitPartDrawObj() {
-	%tmp.19111 = getelementptr %struct..RefRect* null, i64 0, i32 0, i32 1, i32 2
-	%tmp.20311 = getelementptr %struct..RefRect* null, i64 0, i32 1, i32 1, i32 2
+	%tmp.19111 = getelementptr %struct..RefRect, %struct..RefRect* null, i64 0, i32 0, i32 1, i32 2
+	%tmp.20311 = getelementptr %struct..RefRect, %struct..RefRect* null, i64 0, i32 1, i32 1, i32 2
 	ret i32 0
 }
diff --git a/test/Analysis/BasicAA/2003-09-19-LocalArgument.ll b/test/Analysis/BasicAA/2003-09-19-LocalArgument.ll
index fd4c239bbbee..1e75d6461d6f 100644
--- a/test/Analysis/BasicAA/2003-09-19-LocalArgument.ll
+++ b/test/Analysis/BasicAA/2003-09-19-LocalArgument.ll
@@ -7,9 +7,9 @@
 
 define i32 @test(i32* %P) {
 	%X = alloca i32
-	%V1 = load i32* %P
+	%V1 = load i32, i32* %P
 	store i32 0, i32* %X
-	%V2 = load i32* %P
+	%V2 = load i32, i32* %P
 	%Diff = sub i32 %V1, %V2
 	ret i32 %Diff
 }
diff --git a/test/Analysis/BasicAA/2003-11-04-SimpleCases.ll b/test/Analysis/BasicAA/2003-11-04-SimpleCases.ll
index 768411e9d35f..f8d4195c46c6 100644
--- a/test/Analysis/BasicAA/2003-11-04-SimpleCases.ll
+++ b/test/Analysis/BasicAA/2003-11-04-SimpleCases.ll
@@ -3,16 +3,18 @@
 
 ; RUN: opt < %s -basicaa -aa-eval -print-may-aliases -disable-output 2>&1 | FileCheck %s
 
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
 %T = type { i32, [10 x i8] }
 
 ; CHECK:     Function: test
-; CHECK-NOT:   May:
+; CHECK-NOT:   MayAlias:
 
 define void @test(%T* %P) {
-  %A = getelementptr %T* %P, i64 0
-  %B = getelementptr %T* %P, i64 0, i32 0
-  %C = getelementptr %T* %P, i64 0, i32 1
-  %D = getelementptr %T* %P, i64 0, i32 1, i64 0
-  %E = getelementptr %T* %P, i64 0, i32 1, i64 5
+  %A = getelementptr %T, %T* %P, i64 0
+  %B = getelementptr %T, %T* %P, i64 0, i32 0
+  %C = getelementptr %T, %T* %P, i64 0, i32 1
+  %D = getelementptr %T, %T* %P, i64 0, i32 1, i64 0
+  %E = getelementptr %T, %T* %P, i64 0, i32 1, i64 5
   ret void
 }
diff --git a/test/Analysis/BasicAA/2003-12-11-ConstExprGEP.ll b/test/Analysis/BasicAA/2003-12-11-ConstExprGEP.ll
index b7bbf7732f95..957502f2d99c 100644
--- a/test/Analysis/BasicAA/2003-12-11-ConstExprGEP.ll
+++ b/test/Analysis/BasicAA/2003-12-11-ConstExprGEP.ll
@@ -3,18 +3,20 @@
 
 ; RUN: opt < %s -basicaa -aa-eval -print-may-aliases -disable-output 2>&1 | FileCheck %s
 
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
 %T = type { i32, [10 x i8] }
 
 @G = external global %T
 
 ; CHECK:     Function: test
-; CHECK-NOT:   May:
+; CHECK-NOT:   MayAlias:
 
 define void @test() {
-  %D = getelementptr %T* @G, i64 0, i32 0
-  %E = getelementptr %T* @G, i64 0, i32 1, i64 5
-  %F = getelementptr i32* getelementptr (%T* @G, i64 0, i32 0), i64 0
-  %X = getelementptr [10 x i8]* getelementptr (%T* @G, i64 0, i32 1), i64 0, i64 5
+  %D = getelementptr %T, %T* @G, i64 0, i32 0
+  %E = getelementptr %T, %T* @G, i64 0, i32 1, i64 5
+  %F = getelementptr i32, i32* getelementptr (%T, %T* @G, i64 0, i32 0), i64 0
+  %X = getelementptr [10 x i8], [10 x i8]* getelementptr (%T, %T* @G, i64 0, i32 1), i64 0, i64 5
 
   ret void
 }
diff --git a/test/Analysis/BasicAA/2004-07-28-MustAliasbug.ll b/test/Analysis/BasicAA/2004-07-28-MustAliasbug.ll
index 578aa5943cbc..16573a7f9af5 100644
--- a/test/Analysis/BasicAA/2004-07-28-MustAliasbug.ll
+++ b/test/Analysis/BasicAA/2004-07-28-MustAliasbug.ll
@@ -2,9 +2,9 @@
 
 define void @test({i32,i32 }* %P) {
 ; CHECK: store i32 0, i32* %X
-  %Q = getelementptr {i32,i32}* %P, i32 1
-  %X = getelementptr {i32,i32}* %Q, i32 0, i32 1
-  %Y = getelementptr {i32,i32}* %Q, i32 1, i32 1
+  %Q = getelementptr {i32,i32}, {i32,i32}* %P, i32 1
+  %X = getelementptr {i32,i32}, {i32,i32}* %Q, i32 0, i32 1
+  %Y = getelementptr {i32,i32}, {i32,i32}* %Q, i32 1, i32 1
   store i32 0, i32* %X
   store i32 1, i32* %Y
   ret void
diff --git a/test/Analysis/BasicAA/2006-03-03-BadArraySubscript.ll b/test/Analysis/BasicAA/2006-03-03-BadArraySubscript.ll
index 06a804c392f8..98161bff9273 100644
--- a/test/Analysis/BasicAA/2006-03-03-BadArraySubscript.ll
+++ b/test/Analysis/BasicAA/2006-03-03-BadArraySubscript.ll
@@ -12,12 +12,12 @@ entry:
 
 no_exit:		; preds = %no_exit, %entry
 	%i.0.0 = phi i32 [ 0, %entry ], [ %inc, %no_exit ]		; <i32> [#uses=2]
-	%tmp.6 = getelementptr [3 x [3 x i32]]* %X, i32 0, i32 0, i32 %i.0.0		; <i32*> [#uses=1]
+	%tmp.6 = getelementptr [3 x [3 x i32]], [3 x [3 x i32]]* %X, i32 0, i32 0, i32 %i.0.0		; <i32*> [#uses=1]
 	store i32 1, i32* %tmp.6
-	%tmp.8 = getelementptr [3 x [3 x i32]]* %X, i32 0, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp.9 = load i32* %tmp.8		; <i32> [#uses=1]
-	%tmp.11 = getelementptr [3 x [3 x i32]]* %X, i32 0, i32 1, i32 0		; <i32*> [#uses=1]
-	%tmp.12 = load i32* %tmp.11		; <i32> [#uses=1]
+	%tmp.8 = getelementptr [3 x [3 x i32]], [3 x [3 x i32]]* %X, i32 0, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp.9 = load i32, i32* %tmp.8		; <i32> [#uses=1]
+	%tmp.11 = getelementptr [3 x [3 x i32]], [3 x [3 x i32]]* %X, i32 0, i32 1, i32 0		; <i32*> [#uses=1]
+	%tmp.12 = load i32, i32* %tmp.11		; <i32> [#uses=1]
 	%tmp.13 = add i32 %tmp.12, %tmp.9		; <i32> [#uses=1]
 	%inc = add i32 %i.0.0, 1		; <i32> [#uses=2]
 	%tmp.2 = icmp slt i32 %inc, %N		; <i1> [#uses=1]
@@ -25,8 +25,8 @@ no_exit:		; preds = %no_exit, %entry
 
 loopexit:		; preds = %no_exit, %entry
 	%Y.0.1 = phi i32 [ 0, %entry ], [ %tmp.13, %no_exit ]		; <i32> [#uses=1]
-	%tmp.4 = getelementptr [3 x [3 x i32]]* %X, i32 0, i32 0		; <[3 x i32]*> [#uses=1]
-	%tmp.15 = call i32 (...)* @foo( [3 x i32]* %tmp.4, i32 %Y.0.1 )		; <i32> [#uses=0]
+	%tmp.4 = getelementptr [3 x [3 x i32]], [3 x [3 x i32]]* %X, i32 0, i32 0		; <[3 x i32]*> [#uses=1]
+	%tmp.15 = call i32 (...) @foo( [3 x i32]* %tmp.4, i32 %Y.0.1 )		; <i32> [#uses=0]
 	ret void
 }
 
diff --git a/test/Analysis/BasicAA/2006-11-03-BasicAAVectorCrash.ll b/test/Analysis/BasicAA/2006-11-03-BasicAAVectorCrash.ll
index 0db58156547a..a331f7e49557 100644
--- a/test/Analysis/BasicAA/2006-11-03-BasicAAVectorCrash.ll
+++ b/test/Analysis/BasicAA/2006-11-03-BasicAAVectorCrash.ll
@@ -22,7 +22,7 @@ cond_true264.i:		; preds = %bb239.i
 	ret void
 
 cond_false277.i:		; preds = %bb239.i
-	%tmp1062.i = getelementptr [2 x <4 x i32>]* null, i32 0, i32 1		; <<4 x i32>*> [#uses=1]
+	%tmp1062.i = getelementptr [2 x <4 x i32>], [2 x <4 x i32>]* null, i32 0, i32 1		; <<4 x i32>*> [#uses=1]
 	store <4 x i32> zeroinitializer, <4 x i32>* %tmp1062.i
 	br i1 false, label %cond_true1032.i, label %cond_false1063.i85
 
@@ -33,7 +33,7 @@ bb1013.i:		; preds = %bb205.i
 	ret void
 
 cond_true1032.i:		; preds = %cond_false277.i
-	%tmp1187.i = getelementptr [2 x <4 x i32>]* null, i32 0, i32 0, i32 7		; <i32*> [#uses=1]
+	%tmp1187.i = getelementptr [2 x <4 x i32>], [2 x <4 x i32>]* null, i32 0, i32 0, i32 7		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp1187.i
 	br label %bb2037.i
 
diff --git a/test/Analysis/BasicAA/2007-01-13-BasePointerBadNoAlias.ll b/test/Analysis/BasicAA/2007-01-13-BasePointerBadNoAlias.ll
index 46b6aaf91ac9..86bbd44c6448 100644
--- a/test/Analysis/BasicAA/2007-01-13-BasePointerBadNoAlias.ll
+++ b/test/Analysis/BasicAA/2007-01-13-BasePointerBadNoAlias.ll
@@ -21,14 +21,14 @@ target triple = "i686-apple-darwin8"
 ; CHECK:   ret i32 %Z
 
 define i32 @test(%struct.closure_type* %tmp18169) {
-	%tmp18174 = getelementptr %struct.closure_type* %tmp18169, i32 0, i32 4, i32 0, i32 0		; <i32*> [#uses=2]
+	%tmp18174 = getelementptr %struct.closure_type, %struct.closure_type* %tmp18169, i32 0, i32 4, i32 0, i32 0		; <i32*> [#uses=2]
 	%tmp18269 = bitcast i32* %tmp18174  to %struct.STYLE*		; <%struct.STYLE*> [#uses=1]
-	%A = load i32* %tmp18174		; <i32> [#uses=1]
+	%A = load i32, i32* %tmp18174		; <i32> [#uses=1]
 
-        %tmp18272 = getelementptr %struct.STYLE* %tmp18269, i32 0, i32 0, i32 0, i32 2          ; <i16*> [#uses=1]
+        %tmp18272 = getelementptr %struct.STYLE, %struct.STYLE* %tmp18269, i32 0, i32 0, i32 0, i32 2          ; <i16*> [#uses=1]
         store i16 123, i16* %tmp18272
 
-	%Q = load i32* %tmp18174		; <i32> [#uses=1]
+	%Q = load i32, i32* %tmp18174		; <i32> [#uses=1]
 	%Z = sub i32 %A, %Q		; <i32> [#uses=1]
 	ret i32 %Z
 }
diff --git a/test/Analysis/BasicAA/2007-08-01-NoAliasAndGEP.ll b/test/Analysis/BasicAA/2007-08-01-NoAliasAndGEP.ll
index 4be793ec416a..8388d6c97adf 100644
--- a/test/Analysis/BasicAA/2007-08-01-NoAliasAndGEP.ll
+++ b/test/Analysis/BasicAA/2007-08-01-NoAliasAndGEP.ll
@@ -1,15 +1,17 @@
 ; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output 2>&1 | FileCheck %s
 
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
 ; CHECK: Function: foo
-; CHECK:   MayAlias: i32* %Ipointer, i32* %Jpointer
+; CHECK:   PartialAlias: i32* %Ipointer, i32* %Jpointer
 ; CHECK: 9 no alias responses
-; CHECK: 6 may alias responses
+; CHECK: 6 partial alias responses
 
 define void @foo(i32* noalias %p, i32* noalias %q, i32 %i, i32 %j) {
-  %Ipointer = getelementptr i32* %p, i32 %i
-  %qi = getelementptr i32* %q, i32 %i
-  %Jpointer = getelementptr i32* %p, i32 %j
-  %qj = getelementptr i32* %q, i32 %j
+  %Ipointer = getelementptr i32, i32* %p, i32 %i
+  %qi = getelementptr i32, i32* %q, i32 %i
+  %Jpointer = getelementptr i32, i32* %p, i32 %j
+  %qj = getelementptr i32, i32* %q, i32 %j
   store i32 0, i32* %p
   store i32 0, i32* %Ipointer
   store i32 0, i32* %Jpointer
diff --git a/test/Analysis/BasicAA/2007-08-05-GetOverloadedModRef.ll b/test/Analysis/BasicAA/2007-08-05-GetOverloadedModRef.ll
index ec0e2bd91413..5f0e1170f044 100644
--- a/test/Analysis/BasicAA/2007-08-05-GetOverloadedModRef.ll
+++ b/test/Analysis/BasicAA/2007-08-05-GetOverloadedModRef.ll
@@ -5,10 +5,10 @@ declare i16 @llvm.cttz.i16(i16, i1)
 
 define i32 @test(i32* %P, i16* %Q) {
 ; CHECK: ret i32 0
-        %A = load i16* %Q               ; <i16> [#uses=1]
-        %x = load i32* %P               ; <i32> [#uses=1]
+        %A = load i16, i16* %Q               ; <i16> [#uses=1]
+        %x = load i32, i32* %P               ; <i32> [#uses=1]
         %B = call i16 @llvm.cttz.i16( i16 %A, i1 true )          ; <i16> [#uses=1]
-        %y = load i32* %P               ; <i32> [#uses=1]
+        %y = load i32, i32* %P               ; <i32> [#uses=1]
         store i16 %B, i16* %Q
         %z = sub i32 %x, %y             ; <i32> [#uses=1]
         ret i32 %z
diff --git a/test/Analysis/BasicAA/2007-10-24-ArgumentsGlobals.ll b/test/Analysis/BasicAA/2007-10-24-ArgumentsGlobals.ll
index 429160ef6d5e..2d33e9439376 100644
--- a/test/Analysis/BasicAA/2007-10-24-ArgumentsGlobals.ll
+++ b/test/Analysis/BasicAA/2007-10-24-ArgumentsGlobals.ll
@@ -8,9 +8,9 @@ define i32 @_Z3fooP1A(%struct.A* %b) {
 ; CHECK: %tmp7 = load
 ; CHECK: ret i32 %tmp7
 entry:
-        store i32 1, i32* getelementptr (%struct.B* @a, i32 0, i32 0, i32 0), align 8
-        %tmp4 = getelementptr %struct.A* %b, i32 0, i32 0               ;<i32*> [#uses=1]
+        store i32 1, i32* getelementptr (%struct.B, %struct.B* @a, i32 0, i32 0, i32 0), align 8
+        %tmp4 = getelementptr %struct.A, %struct.A* %b, i32 0, i32 0               ;<i32*> [#uses=1]
         store i32 0, i32* %tmp4, align 4
-        %tmp7 = load i32* getelementptr (%struct.B* @a, i32 0, i32 0, i32 0), align 8           ; <i32> [#uses=1]
+        %tmp7 = load i32, i32* getelementptr (%struct.B, %struct.B* @a, i32 0, i32 0, i32 0), align 8           ; <i32> [#uses=1]
         ret i32 %tmp7
 }
diff --git a/test/Analysis/BasicAA/2007-11-05-SizeCrash.ll b/test/Analysis/BasicAA/2007-11-05-SizeCrash.ll
index 32d9930f4270..069bd0bcfd8f 100644
--- a/test/Analysis/BasicAA/2007-11-05-SizeCrash.ll
+++ b/test/Analysis/BasicAA/2007-11-05-SizeCrash.ll
@@ -14,18 +14,18 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @uhci_suspend(%struct.usb_hcd* %hcd) {
 entry:
-        %tmp17 = getelementptr %struct.usb_hcd* %hcd, i32 0, i32 2, i64 1      
+        %tmp17 = getelementptr %struct.usb_hcd, %struct.usb_hcd* %hcd, i32 0, i32 2, i64 1      
         ; <i64*> [#uses=1]
         %tmp1718 = bitcast i64* %tmp17 to i32*          ; <i32*> [#uses=1]
-        %tmp19 = load i32* %tmp1718, align 4            ; <i32> [#uses=0]
+        %tmp19 = load i32, i32* %tmp1718, align 4            ; <i32> [#uses=0]
         br i1 false, label %cond_true34, label %done_okay
 
 cond_true34:            ; preds = %entry
-        %tmp631 = getelementptr %struct.usb_hcd* %hcd, i32 0, i32 2, i64
+        %tmp631 = getelementptr %struct.usb_hcd, %struct.usb_hcd* %hcd, i32 0, i32 2, i64
 2305843009213693950            ; <i64*> [#uses=1]
         %tmp70 = bitcast i64* %tmp631 to %struct.device**
 
-        %tmp71 = load %struct.device** %tmp70, align 8
+        %tmp71 = load %struct.device*, %struct.device** %tmp70, align 8
 
         ret i32 undef
 
diff --git a/test/Analysis/BasicAA/2007-12-08-OutOfBoundsCrash.ll b/test/Analysis/BasicAA/2007-12-08-OutOfBoundsCrash.ll
index cd997ea52513..20be13d153bb 100644
--- a/test/Analysis/BasicAA/2007-12-08-OutOfBoundsCrash.ll
+++ b/test/Analysis/BasicAA/2007-12-08-OutOfBoundsCrash.ll
@@ -13,17 +13,17 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @ehci_pci_setup(%struct.usb_hcd* %hcd) {
 entry:
-	%tmp14 = getelementptr %struct.usb_hcd* %hcd, i32 0, i32 0, i32 0		; <%struct.device**> [#uses=1]
-	%tmp15 = load %struct.device** %tmp14, align 8		; <%struct.device*> [#uses=0]
+	%tmp14 = getelementptr %struct.usb_hcd, %struct.usb_hcd* %hcd, i32 0, i32 0, i32 0		; <%struct.device**> [#uses=1]
+	%tmp15 = load %struct.device*, %struct.device** %tmp14, align 8		; <%struct.device*> [#uses=0]
 	br i1 false, label %bb25, label %return
 
 bb25:		; preds = %entry
 	br i1 false, label %cond_true, label %return
 
 cond_true:		; preds = %bb25
-	%tmp601 = getelementptr %struct.usb_hcd* %hcd, i32 0, i32 1, i64 2305843009213693951		; <i64*> [#uses=1]
+	%tmp601 = getelementptr %struct.usb_hcd, %struct.usb_hcd* %hcd, i32 0, i32 1, i64 2305843009213693951		; <i64*> [#uses=1]
 	%tmp67 = bitcast i64* %tmp601 to %struct.device**		; <%struct.device**> [#uses=1]
-	%tmp68 = load %struct.device** %tmp67, align 8		; <%struct.device*> [#uses=0]
+	%tmp68 = load %struct.device*, %struct.device** %tmp67, align 8		; <%struct.device*> [#uses=0]
 	ret i32 undef
 
 return:		; preds = %bb25, %entry
diff --git a/test/Analysis/BasicAA/2008-04-15-Byval.ll b/test/Analysis/BasicAA/2008-04-15-Byval.ll
index 2ea0314d5b60..9d4fd1483185 100644
--- a/test/Analysis/BasicAA/2008-04-15-Byval.ll
+++ b/test/Analysis/BasicAA/2008-04-15-Byval.ll
@@ -7,10 +7,10 @@ target triple = "i386-apple-darwin8"
 define void @foo(%struct.x* byval align 4  %X) nounwind  {
 ; CHECK: store i32 2, i32* %tmp1
 entry:
-	%tmp = getelementptr %struct.x* %X, i32 0, i32 0		; <[4 x i32]*> [#uses=1]
-	%tmp1 = getelementptr [4 x i32]* %tmp, i32 0, i32 3		; <i32*> [#uses=1]
+	%tmp = getelementptr %struct.x, %struct.x* %X, i32 0, i32 0		; <[4 x i32]*> [#uses=1]
+	%tmp1 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 3		; <i32*> [#uses=1]
 	store i32 2, i32* %tmp1, align 4
-	%tmp2 = call i32 (...)* @bar( %struct.x* byval align 4  %X ) nounwind 		; <i32> [#uses=0]
+	%tmp2 = call i32 (...) @bar( %struct.x* byval align 4  %X ) nounwind 		; <i32> [#uses=0]
 	br label %return
 return:		; preds = %entry
 	ret void
diff --git a/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll b/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll
index 170914447644..7d2cde4864a3 100644
--- a/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll
+++ b/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll
@@ -9,7 +9,7 @@ target triple = "i686-pc-linux-gnu"
 
 define void @test291() nounwind  {
 entry:
-	store i32 1138410269, i32* getelementptr ([5 x %struct.S291]* @a291, i32 0, i32 2, i32 1)
-	%tmp54 = load i32* bitcast (%struct.S291* getelementptr ([5 x %struct.S291]* @a291, i32 0, i32 2) to i32*), align 4		; <i32> [#uses=0]
+	store i32 1138410269, i32* getelementptr ([5 x %struct.S291], [5 x %struct.S291]* @a291, i32 0, i32 2, i32 1)
+	%tmp54 = load i32, i32* bitcast (%struct.S291* getelementptr ([5 x %struct.S291], [5 x %struct.S291]* @a291, i32 0, i32 2) to i32*), align 4		; <i32> [#uses=0]
 	unreachable
 }
diff --git a/test/Analysis/BasicAA/2008-11-23-NoaliasRet.ll b/test/Analysis/BasicAA/2008-11-23-NoaliasRet.ll
index 3db9a3fbcdc9..49a742c31f58 100644
--- a/test/Analysis/BasicAA/2008-11-23-NoaliasRet.ll
+++ b/test/Analysis/BasicAA/2008-11-23-NoaliasRet.ll
@@ -9,6 +9,6 @@ define i32 @foo() {
   %B = call i32* @_Znwj(i32 4)
   store i32 1, i32* %A
   store i32 2, i32* %B
-  %C = load i32* %A
+  %C = load i32, i32* %A
   ret i32 %C
 }
diff --git a/test/Analysis/BasicAA/2009-03-04-GEPNoalias.ll b/test/Analysis/BasicAA/2009-03-04-GEPNoalias.ll
index add7dee0fe10..65dcf5ceab36 100644
--- a/test/Analysis/BasicAA/2009-03-04-GEPNoalias.ll
+++ b/test/Analysis/BasicAA/2009-03-04-GEPNoalias.ll
@@ -3,12 +3,12 @@
 declare noalias i32* @noalias()
 
 define i32 @test(i32 %x) {
-; CHECK: load i32* %a
+; CHECK: load i32, i32* %a
   %a = call i32* @noalias()
   store i32 1, i32* %a
-  %b = getelementptr i32* %a, i32 %x
+  %b = getelementptr i32, i32* %a, i32 %x
   store i32 2, i32* %b
 
-  %c = load i32* %a
+  %c = load i32, i32* %a
   ret i32 %c
 }
diff --git a/test/Analysis/BasicAA/2009-10-13-AtomicModRef.ll b/test/Analysis/BasicAA/2009-10-13-AtomicModRef.ll
index 4b6a12e821e1..97a92517dca8 100644
--- a/test/Analysis/BasicAA/2009-10-13-AtomicModRef.ll
+++ b/test/Analysis/BasicAA/2009-10-13-AtomicModRef.ll
@@ -2,12 +2,12 @@
 target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
 
 define i8 @foo(i8* %ptr) {
-  %P = getelementptr i8* %ptr, i32 0
-  %Q = getelementptr i8* %ptr, i32 1
+  %P = getelementptr i8, i8* %ptr, i32 0
+  %Q = getelementptr i8, i8* %ptr, i32 1
 ; CHECK: getelementptr
-  %X = load i8* %P
+  %X = load i8, i8* %P
   %Y = atomicrmw add i8* %Q, i8 1 monotonic
-  %Z = load i8* %P
+  %Z = load i8, i8* %P
 ; CHECK-NOT: = load
   %A = sub i8 %X, %Z
   ret i8 %A
diff --git a/test/Analysis/BasicAA/2009-10-13-GEP-BaseNoAlias.ll b/test/Analysis/BasicAA/2009-10-13-GEP-BaseNoAlias.ll
index c546d68f425b..43ee96ce9b3d 100644
--- a/test/Analysis/BasicAA/2009-10-13-GEP-BaseNoAlias.ll
+++ b/test/Analysis/BasicAA/2009-10-13-GEP-BaseNoAlias.ll
@@ -15,7 +15,7 @@ entry:
   br i1 %tmp, label %bb, label %bb1
 
 bb:
-  %b = getelementptr i32* %a, i32 0
+  %b = getelementptr i32, i32* %a, i32 0
   br label %bb2
 
 bb1:
@@ -23,9 +23,9 @@ bb1:
 
 bb2:
   %P = phi i32* [ %b, %bb ], [ @Y, %bb1 ]
-  %tmp1 = load i32* @Z, align 4
+  %tmp1 = load i32, i32* @Z, align 4
   store i32 123, i32* %P, align 4
-  %tmp2 = load i32* @Z, align 4
+  %tmp2 = load i32, i32* @Z, align 4
   br label %return
 
 return:
diff --git a/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll b/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll
index 66569808fb66..b2e7a60047bd 100644
--- a/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll
+++ b/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll
@@ -8,10 +8,10 @@ target datalayout = "e-p:32:32:32"
 define i32 @test(i32* %tab, i32 %indvar) nounwind {
   %tmp31 = mul i32 %indvar, -2
   %tmp32 = add i32 %tmp31, 30
-  %t.5 = getelementptr i32* %tab, i32 %tmp32
-  %loada = load i32* %tab
+  %t.5 = getelementptr i32, i32* %tab, i32 %tmp32
+  %loada = load i32, i32* %tab
   store i32 0, i32* %t.5
-  %loadb = load i32* %tab
+  %loadb = load i32, i32* %tab
   %rval = add i32 %loada, %loadb
   ret i32 %rval
 }
diff --git a/test/Analysis/BasicAA/2014-03-18-Maxlookup-reached.ll b/test/Analysis/BasicAA/2014-03-18-Maxlookup-reached.ll
index bc2512eca0c9..08db5ec4d1d9 100644
--- a/test/Analysis/BasicAA/2014-03-18-Maxlookup-reached.ll
+++ b/test/Analysis/BasicAA/2014-03-18-Maxlookup-reached.ll
@@ -10,27 +10,27 @@ target datalayout = "e"
 
 define i32 @main() {
   %t = alloca %struct.foo, align 4
-  %1 = getelementptr inbounds %struct.foo* %t, i32 0, i32 0
+  %1 = getelementptr inbounds %struct.foo, %struct.foo* %t, i32 0, i32 0
   store i32 1, i32* %1, align 4
-  %2 = getelementptr inbounds %struct.foo* %t, i64 1
+  %2 = getelementptr inbounds %struct.foo, %struct.foo* %t, i64 1
   %3 = bitcast %struct.foo* %2 to i8*
-  %4 = getelementptr inbounds i8* %3, i32 -1
+  %4 = getelementptr inbounds i8, i8* %3, i32 -1
   store i8 0, i8* %4
-  %5 = getelementptr inbounds i8* %4, i32 -1
+  %5 = getelementptr inbounds i8, i8* %4, i32 -1
   store i8 0, i8* %5
-  %6 = getelementptr inbounds i8* %5, i32 -1
+  %6 = getelementptr inbounds i8, i8* %5, i32 -1
   store i8 0, i8* %6
-  %7 = getelementptr inbounds i8* %6, i32 -1
+  %7 = getelementptr inbounds i8, i8* %6, i32 -1
   store i8 0, i8* %7
-  %8 = getelementptr inbounds i8* %7, i32 -1
+  %8 = getelementptr inbounds i8, i8* %7, i32 -1
   store i8 0, i8* %8
-  %9 = getelementptr inbounds i8* %8, i32 -1
+  %9 = getelementptr inbounds i8, i8* %8, i32 -1
   store i8 0, i8* %9
-  %10 = getelementptr inbounds i8* %9, i32 -1
+  %10 = getelementptr inbounds i8, i8* %9, i32 -1
   store i8 0, i8* %10
-  %11 = getelementptr inbounds i8* %10, i32 -1
+  %11 = getelementptr inbounds i8, i8* %10, i32 -1
   store i8 0, i8* %11
-  %12 = load i32* %1, align 4
+  %12 = load i32, i32* %1, align 4
   ret i32 %12
 ; CHECK: ret i32 %12
 }
diff --git a/test/Analysis/BasicAA/aligned-overread.ll b/test/Analysis/BasicAA/aligned-overread.ll
index b05f8eb69483..aa0a83e66975 100644
--- a/test/Analysis/BasicAA/aligned-overread.ll
+++ b/test/Analysis/BasicAA/aligned-overread.ll
@@ -9,11 +9,11 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 define i32 @main() nounwind uwtable ssp {
 entry:
-  %tmp = load i8* getelementptr inbounds ({ i8, i8, i8, i8, i8 }* @a, i64 0, i32 4), align 4
+  %tmp = load i8, i8* getelementptr inbounds ({ i8, i8, i8, i8, i8 }, { i8, i8, i8, i8, i8 }* @a, i64 0, i32 4), align 4
   %tmp1 = or i8 %tmp, -128
-  store i8 %tmp1, i8* getelementptr inbounds ({ i8, i8, i8, i8, i8 }* @a, i64 0, i32 4), align 4
-  %tmp2 = load i64* bitcast ({ i8, i8, i8, i8, i8 }* @a to i64*), align 8
-  store i8 11, i8* getelementptr inbounds ({ i8, i8, i8, i8, i8 }* @a, i64 0, i32 4), align 4
+  store i8 %tmp1, i8* getelementptr inbounds ({ i8, i8, i8, i8, i8 }, { i8, i8, i8, i8, i8 }* @a, i64 0, i32 4), align 4
+  %tmp2 = load i64, i64* bitcast ({ i8, i8, i8, i8, i8 }* @a to i64*), align 8
+  store i8 11, i8* getelementptr inbounds ({ i8, i8, i8, i8, i8 }, { i8, i8, i8, i8, i8 }* @a, i64 0, i32 4), align 4
   %tmp3 = trunc i64 %tmp2 to i32
   ret i32 %tmp3
 
diff --git a/test/Analysis/BasicAA/args-rets-allocas-loads.ll b/test/Analysis/BasicAA/args-rets-allocas-loads.ll
index 066f46b16c01..05b56a07e44b 100644
--- a/test/Analysis/BasicAA/args-rets-allocas-loads.ll
+++ b/test/Analysis/BasicAA/args-rets-allocas-loads.ll
@@ -22,8 +22,8 @@ define void @caller_a(double* %arg_a0,
   %noalias_ret_a0 = call double* @noalias_returner()
   %noalias_ret_a1 = call double* @noalias_returner()
 
-  %loaded_a0 = load double** %indirect_a0
-  %loaded_a1 = load double** %indirect_a1
+  %loaded_a0 = load double*, double** %indirect_a0
+  %loaded_a1 = load double*, double** %indirect_a1
 
   call void @callee(double* %escape_alloca_a0)
   call void @callee(double* %escape_alloca_a1)
diff --git a/test/Analysis/BasicAA/byval.ll b/test/Analysis/BasicAA/byval.ll
index 673fee01cc8d..4f90c3f4d26e 100644
--- a/test/Analysis/BasicAA/byval.ll
+++ b/test/Analysis/BasicAA/byval.ll
@@ -6,11 +6,11 @@ target triple = "i686-apple-darwin8"
 
 define i32 @foo(%struct.x* byval  %a) nounwind  {
 ; CHECK: ret i32 1
-  %tmp1 = tail call i32 (...)* @bar( %struct.x* %a ) nounwind 		; <i32> [#uses=0]
-  %tmp2 = getelementptr %struct.x* %a, i32 0, i32 0		; <i32*> [#uses=2]
+  %tmp1 = tail call i32 (...) @bar( %struct.x* %a ) nounwind 		; <i32> [#uses=0]
+  %tmp2 = getelementptr %struct.x, %struct.x* %a, i32 0, i32 0		; <i32*> [#uses=2]
   store i32 1, i32* %tmp2, align 4
   store i32 2, i32* @g, align 4
-  %tmp4 = load i32* %tmp2, align 4		; <i32> [#uses=1]
+  %tmp4 = load i32, i32* %tmp2, align 4		; <i32> [#uses=1]
   ret i32 %tmp4
 }
 
diff --git a/test/Analysis/BasicAA/cas.ll b/test/Analysis/BasicAA/cas.ll
index d0cd9f40ccc2..b770cb73381a 100644
--- a/test/Analysis/BasicAA/cas.ll
+++ b/test/Analysis/BasicAA/cas.ll
@@ -6,9 +6,9 @@
 ; CHECK: ret i32 0
 
 define i32 @main() {
-  %a = load i32* @flag0
+  %a = load i32, i32* @flag0
   %b = atomicrmw xchg i32* @turn, i32 1 monotonic
-  %c = load i32* @flag0
+  %c = load i32, i32* @flag0
   %d = sub i32 %a, %c
   ret i32 %d
 }
diff --git a/test/Analysis/BasicAA/constant-over-index.ll b/test/Analysis/BasicAA/constant-over-index.ll
index 232533cc73e1..f5e2c7c13617 100644
--- a/test/Analysis/BasicAA/constant-over-index.ll
+++ b/test/Analysis/BasicAA/constant-over-index.ll
@@ -1,20 +1,23 @@
 ; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info 2>&1 | FileCheck %s
 ; PR4267
 
-; CHECK: MayAlias: double* %p.0.i.0, double* %p3
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+; CHECK: PartialAlias: double* %p.0.i.0, double* %p3
 
 ; %p3 is equal to %p.0.i.0 on the second iteration of the loop,
-; so MayAlias is needed.
+; so MayAlias is needed.  In practice, basicaa returns PartialAlias
+; for GEPs to ignore TBAA.
 
 define void @foo([3 x [3 x double]]* noalias %p) {
 entry:
-  %p3 = getelementptr [3 x [3 x double]]* %p, i64 0, i64 0, i64 3
+  %p3 = getelementptr [3 x [3 x double]], [3 x [3 x double]]* %p, i64 0, i64 0, i64 3
   br label %loop
 
 loop:
   %i = phi i64 [ 0, %entry ], [ %i.next, %loop ]
 
-  %p.0.i.0 = getelementptr [3 x [3 x double]]* %p, i64 0, i64 %i, i64 0
+  %p.0.i.0 = getelementptr [3 x [3 x double]], [3 x [3 x double]]* %p, i64 0, i64 %i, i64 0
 
   store volatile double 0.0, double* %p3
   store volatile double 0.1, double* %p.0.i.0
diff --git a/test/Analysis/BasicAA/cs-cs.ll b/test/Analysis/BasicAA/cs-cs.ll
index 693634c0414d..78670b61ca1c 100644
--- a/test/Analysis/BasicAA/cs-cs.ll
+++ b/test/Analysis/BasicAA/cs-cs.ll
@@ -12,7 +12,7 @@ declare void @a_readonly_func(i8 *) noinline nounwind readonly
 
 define <8 x i16> @test1(i8* %p, <8 x i16> %y) {
 entry:
-  %q = getelementptr i8* %p, i64 16
+  %q = getelementptr i8, i8* %p, i64 16
   %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind
   call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16)
   %b = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind
@@ -70,7 +70,7 @@ define void @test2a(i8* noalias %P, i8* noalias %Q) nounwind ssp {
 
 define void @test2b(i8* noalias %P, i8* noalias %Q) nounwind ssp {
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %P, i8* %Q, i64 12, i32 1, i1 false)
-  %R = getelementptr i8* %P, i64 12
+  %R = getelementptr i8, i8* %P, i64 12
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %R, i8* %Q, i64 12, i32 1, i1 false)
   ret void
 
@@ -91,7 +91,7 @@ define void @test2b(i8* noalias %P, i8* noalias %Q) nounwind ssp {
 
 define void @test2c(i8* noalias %P, i8* noalias %Q) nounwind ssp {
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %P, i8* %Q, i64 12, i32 1, i1 false)
-  %R = getelementptr i8* %P, i64 11
+  %R = getelementptr i8, i8* %P, i64 11
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %R, i8* %Q, i64 12, i32 1, i1 false)
   ret void
 
@@ -112,7 +112,7 @@ define void @test2c(i8* noalias %P, i8* noalias %Q) nounwind ssp {
 
 define void @test2d(i8* noalias %P, i8* noalias %Q) nounwind ssp {
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %P, i8* %Q, i64 12, i32 1, i1 false)
-  %R = getelementptr i8* %P, i64 -12
+  %R = getelementptr i8, i8* %P, i64 -12
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %R, i8* %Q, i64 12, i32 1, i1 false)
   ret void
 
@@ -133,7 +133,7 @@ define void @test2d(i8* noalias %P, i8* noalias %Q) nounwind ssp {
 
 define void @test2e(i8* noalias %P, i8* noalias %Q) nounwind ssp {
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %P, i8* %Q, i64 12, i32 1, i1 false)
-  %R = getelementptr i8* %P, i64 -11
+  %R = getelementptr i8, i8* %P, i64 -11
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %R, i8* %Q, i64 12, i32 1, i1 false)
   ret void
 
diff --git a/test/Analysis/BasicAA/dag.ll b/test/Analysis/BasicAA/dag.ll
index 1d2f6f1a76dd..63e2c1a8c09f 100644
--- a/test/Analysis/BasicAA/dag.ll
+++ b/test/Analysis/BasicAA/dag.ll
@@ -36,6 +36,6 @@ xc:
   %bigbase = bitcast i8* %base to i16*
   store i16 -1, i16* %bigbase
 
-  %loaded = load i8* %phi
+  %loaded = load i8, i8* %phi
   ret i8 %loaded
 }
diff --git a/test/Analysis/BasicAA/featuretest.ll b/test/Analysis/BasicAA/featuretest.ll
index 47d278fab1c2..c621d0e3e849 100644
--- a/test/Analysis/BasicAA/featuretest.ll
+++ b/test/Analysis/BasicAA/featuretest.ll
@@ -18,13 +18,13 @@ define i32 @different_array_test(i64 %A, i64 %B) {
         call void @external(i32* %Array1)
         call void @external(i32* %Array2)
 
-	%pointer = getelementptr i32* %Array1, i64 %A
-	%val = load i32* %pointer
+	%pointer = getelementptr i32, i32* %Array1, i64 %A
+	%val = load i32, i32* %pointer
 
-	%pointer2 = getelementptr i32* %Array2, i64 %B
+	%pointer2 = getelementptr i32, i32* %Array2, i64 %B
 	store i32 7, i32* %pointer2
 
-	%REMOVE = load i32* %pointer ; redundant with above load
+	%REMOVE = load i32, i32* %pointer ; redundant with above load
 	%retval = sub i32 %REMOVE, %val
 	ret i32 %retval
 ; CHECK: @different_array_test
@@ -38,12 +38,12 @@ define i32 @constant_array_index_test() {
 	%Array = alloca i32, i32 100
         call void @external(i32* %Array)
 
-	%P1 = getelementptr i32* %Array, i64 7
-	%P2 = getelementptr i32* %Array, i64 6
+	%P1 = getelementptr i32, i32* %Array, i64 7
+	%P2 = getelementptr i32, i32* %Array, i64 6
 	
-	%A = load i32* %P1
+	%A = load i32, i32* %P1
 	store i32 1, i32* %P2   ; Should not invalidate load
-	%BREMOVE = load i32* %P1
+	%BREMOVE = load i32, i32* %P1
 	%Val = sub i32 %A, %BREMOVE
 	ret i32 %Val
 ; CHECK: @constant_array_index_test
@@ -53,10 +53,10 @@ define i32 @constant_array_index_test() {
 ; Test that if two pointers are spaced out by a constant getelementptr, that 
 ; they cannot alias.
 define i32 @gep_distance_test(i32* %A) {
-        %REMOVEu = load i32* %A
-        %B = getelementptr i32* %A, i64 2  ; Cannot alias A
+        %REMOVEu = load i32, i32* %A
+        %B = getelementptr i32, i32* %A, i64 2  ; Cannot alias A
         store i32 7, i32* %B
-        %REMOVEv = load i32* %A
+        %REMOVEv = load i32, i32* %A
         %r = sub i32 %REMOVEu, %REMOVEv
         ret i32 %r
 ; CHECK: @gep_distance_test
@@ -66,11 +66,11 @@ define i32 @gep_distance_test(i32* %A) {
 ; Test that if two pointers are spaced out by a constant offset, that they
 ; cannot alias, even if there is a variable offset between them...
 define i32 @gep_distance_test2({i32,i32}* %A, i64 %distance) {
-	%A1 = getelementptr {i32,i32}* %A, i64 0, i32 0
-	%REMOVEu = load i32* %A1
-	%B = getelementptr {i32,i32}* %A, i64 %distance, i32 1
+	%A1 = getelementptr {i32,i32}, {i32,i32}* %A, i64 0, i32 0
+	%REMOVEu = load i32, i32* %A1
+	%B = getelementptr {i32,i32}, {i32,i32}* %A, i64 %distance, i32 1
 	store i32 7, i32* %B    ; B cannot alias A, it's at least 4 bytes away
-	%REMOVEv = load i32* %A1
+	%REMOVEv = load i32, i32* %A1
         %r = sub i32 %REMOVEu, %REMOVEv
         ret i32 %r
 ; CHECK: @gep_distance_test2
@@ -80,11 +80,11 @@ define i32 @gep_distance_test2({i32,i32}* %A, i64 %distance) {
 ; Test that we can do funny pointer things and that distance calc will still 
 ; work.
 define i32 @gep_distance_test3(i32 * %A) {
-	%X = load i32* %A
+	%X = load i32, i32* %A
 	%B = bitcast i32* %A to i8*
-	%C = getelementptr i8* %B, i64 4
+	%C = getelementptr i8, i8* %B, i64 4
         store i8 42, i8* %C
-	%Y = load i32* %A
+	%Y = load i32, i32* %A
         %R = sub i32 %X, %Y
 	ret i32 %R
 ; CHECK: @gep_distance_test3
@@ -96,9 +96,9 @@ define i32 @constexpr_test() {
    %X = alloca i32
    call void @external(i32* %X)
 
-   %Y = load i32* %X
-   store i32 5, i32* getelementptr ({ i32 }* @Global, i64 0, i32 0)
-   %REMOVE = load i32* %X
+   %Y = load i32, i32* %X
+   store i32 5, i32* getelementptr ({ i32 }, { i32 }* @Global, i64 0, i32 0)
+   %REMOVE = load i32, i32* %X
    %retval = sub i32 %Y, %REMOVE
    ret i32 %retval
 ; CHECK: @constexpr_test
@@ -112,13 +112,13 @@ define i32 @constexpr_test() {
 define i16 @zext_sext_confusion(i16* %row2col, i5 %j) nounwind{
 entry:
   %sum5.cast = zext i5 %j to i64             ; <i64> [#uses=1]
-  %P1 = getelementptr i16* %row2col, i64 %sum5.cast
-  %row2col.load.1.2 = load i16* %P1, align 1 ; <i16> [#uses=1]
+  %P1 = getelementptr i16, i16* %row2col, i64 %sum5.cast
+  %row2col.load.1.2 = load i16, i16* %P1, align 1 ; <i16> [#uses=1]
   
   %sum13.cast31 = sext i5 %j to i6          ; <i6> [#uses=1]
   %sum13.cast = zext i6 %sum13.cast31 to i64      ; <i64> [#uses=1]
-  %P2 = getelementptr i16* %row2col, i64 %sum13.cast
-  %row2col.load.1.6 = load i16* %P2, align 1 ; <i16> [#uses=1]
+  %P2 = getelementptr i16, i16* %row2col, i64 %sum13.cast
+  %row2col.load.1.6 = load i16, i16* %P2, align 1 ; <i16> [#uses=1]
   
   %.ret = sub i16 %row2col.load.1.6, %row2col.load.1.2 ; <i16> [#uses=1]
   ret i16 %.ret
diff --git a/test/Analysis/BasicAA/full-store-partial-alias.ll b/test/Analysis/BasicAA/full-store-partial-alias.ll
index 9699d92ea83f..341f6ba23b3a 100644
--- a/test/Analysis/BasicAA/full-store-partial-alias.ll
+++ b/test/Analysis/BasicAA/full-store-partial-alias.ll
@@ -18,13 +18,13 @@ define i32 @signbit(double %x) nounwind {
 ; CHECK:   ret i32 0
 entry:
   %u = alloca %union.anon, align 8
-  %tmp9 = getelementptr inbounds %union.anon* %u, i64 0, i32 0
+  %tmp9 = getelementptr inbounds %union.anon, %union.anon* %u, i64 0, i32 0
   store double %x, double* %tmp9, align 8, !tbaa !0
-  %tmp2 = load i32* bitcast (i64* @endianness_test to i32*), align 8, !tbaa !3
+  %tmp2 = load i32, i32* bitcast (i64* @endianness_test to i32*), align 8, !tbaa !3
   %idxprom = sext i32 %tmp2 to i64
   %tmp4 = bitcast %union.anon* %u to [2 x i32]*
-  %arrayidx = getelementptr inbounds [2 x i32]* %tmp4, i64 0, i64 %idxprom
-  %tmp5 = load i32* %arrayidx, align 4, !tbaa !3
+  %arrayidx = getelementptr inbounds [2 x i32], [2 x i32]* %tmp4, i64 0, i64 %idxprom
+  %tmp5 = load i32, i32* %arrayidx, align 4, !tbaa !3
   %tmp5.lobit = lshr i32 %tmp5, 31
   ret i32 %tmp5.lobit
 }
diff --git a/test/Analysis/BasicAA/gcsetest.ll b/test/Analysis/BasicAA/gcsetest.ll
index 64792eb00a2f..cf6ab710bf2f 100644
--- a/test/Analysis/BasicAA/gcsetest.ll
+++ b/test/Analysis/BasicAA/gcsetest.ll
@@ -12,11 +12,11 @@
 ; CHECK-NEXT:   ret i32 0
 
 define i32 @test() {
-	%A1 = load i32* @A
+	%A1 = load i32, i32* @A
 
 	store i32 123, i32* @B  ; Store cannot alias @A
 
-	%A2 = load i32* @A
+	%A2 = load i32, i32* @A
 	%X = sub i32 %A1, %A2
 	ret i32 %X
 }
@@ -30,13 +30,13 @@ define i32 @test() {
 ; CHECK-NEXT:   ret i32 0
 
 define i32 @test2() {
-        %A1 = load i32* @A
+        %A1 = load i32, i32* @A
         br label %Loop
 Loop:
         %AP = phi i32 [0, %0], [%X, %Loop]
         store i32 %AP, i32* @B  ; Store cannot alias @A
 
-        %A2 = load i32* @A
+        %A2 = load i32, i32* @A
         %X = sub i32 %A1, %A2
         %c = icmp eq i32 %X, 0
         br i1 %c, label %out, label %Loop
@@ -55,7 +55,7 @@ define i32 @test3() {
 	%X = alloca i32
 	store i32 7, i32* %X
 	call void @external()
-	%V = load i32* %X
+	%V = load i32, i32* %X
 	ret i32 %V
 }
 
diff --git a/test/Analysis/BasicAA/gep-alias.ll b/test/Analysis/BasicAA/gep-alias.ll
index 2c0d467003f2..f686010f9ead 100644
--- a/test/Analysis/BasicAA/gep-alias.ll
+++ b/test/Analysis/BasicAA/gep-alias.ll
@@ -6,12 +6,12 @@ target datalayout = "e-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-
 define i32 @test1(i8 * %P) {
 entry:
 	%Q = bitcast i8* %P to {i32, i32}*
-	%R = getelementptr {i32, i32}* %Q, i32 0, i32 1
-	%S = load i32* %R
+	%R = getelementptr {i32, i32}, {i32, i32}* %Q, i32 0, i32 1
+	%S = load i32, i32* %R
 
 	%q = bitcast i8* %P to {i32, i32}*
-	%r = getelementptr {i32, i32}* %q, i32 0, i32 1
-	%s = load i32* %r
+	%r = getelementptr {i32, i32}, {i32, i32}* %q, i32 0, i32 1
+	%s = load i32, i32* %r
 
 	%t = sub i32 %S, %s
 	ret i32 %t
@@ -22,13 +22,13 @@ entry:
 define i32 @test2(i8 * %P) {
 entry:
 	%Q = bitcast i8* %P to {i32, i32, i32}*
-	%R = getelementptr {i32, i32, i32}* %Q, i32 0, i32 1
-	%S = load i32* %R
+	%R = getelementptr {i32, i32, i32}, {i32, i32, i32}* %Q, i32 0, i32 1
+	%S = load i32, i32* %R
 
-	%r = getelementptr {i32, i32, i32}* %Q, i32 0, i32 2
+	%r = getelementptr {i32, i32, i32}, {i32, i32, i32}* %Q, i32 0, i32 2
   store i32 42, i32* %r
 
-	%s = load i32* %R
+	%s = load i32, i32* %R
 
 	%t = sub i32 %S, %s
 	ret i32 %t
@@ -40,14 +40,14 @@ entry:
 ; This was a miscompilation.
 define i32 @test3({float, {i32, i32, i32}}* %P) {
 entry:
-  %P2 = getelementptr {float, {i32, i32, i32}}* %P, i32 0, i32 1
-	%R = getelementptr {i32, i32, i32}* %P2, i32 0, i32 1
-	%S = load i32* %R
+  %P2 = getelementptr {float, {i32, i32, i32}}, {float, {i32, i32, i32}}* %P, i32 0, i32 1
+	%R = getelementptr {i32, i32, i32}, {i32, i32, i32}* %P2, i32 0, i32 1
+	%S = load i32, i32* %R
 
-	%r = getelementptr {i32, i32, i32}* %P2, i32 0, i32 2
+	%r = getelementptr {i32, i32, i32}, {i32, i32, i32}* %P2, i32 0, i32 2
   store i32 42, i32* %r
 
-	%s = load i32* %R
+	%s = load i32, i32* %R
 
 	%t = sub i32 %S, %s
 	ret i32 %t
@@ -62,11 +62,11 @@ entry:
 
 define i32 @test4(%SmallPtrSet64* %P) {
 entry:
-  %tmp2 = getelementptr inbounds %SmallPtrSet64* %P, i64 0, i32 0, i32 1
+  %tmp2 = getelementptr inbounds %SmallPtrSet64, %SmallPtrSet64* %P, i64 0, i32 0, i32 1
   store i32 64, i32* %tmp2, align 8
-  %tmp3 = getelementptr inbounds %SmallPtrSet64* %P, i64 0, i32 0, i32 4, i64 64
+  %tmp3 = getelementptr inbounds %SmallPtrSet64, %SmallPtrSet64* %P, i64 0, i32 0, i32 4, i64 64
   store i8* null, i8** %tmp3, align 8
-  %tmp4 = load i32* %tmp2, align 8
+  %tmp4 = load i32, i32* %tmp2, align 8
 	ret i32 %tmp4
 ; CHECK-LABEL: @test4(
 ; CHECK: ret i32 64
@@ -74,12 +74,12 @@ entry:
 
 ; P[i] != p[i+1]
 define i32 @test5(i32* %p, i64 %i) {
-  %pi = getelementptr i32* %p, i64 %i
+  %pi = getelementptr i32, i32* %p, i64 %i
   %i.next = add i64 %i, 1
-  %pi.next = getelementptr i32* %p, i64 %i.next
-  %x = load i32* %pi
+  %pi.next = getelementptr i32, i32* %p, i64 %i.next
+  %x = load i32, i32* %pi
   store i32 42, i32* %pi.next
-  %y = load i32* %pi
+  %y = load i32, i32* %pi
   %z = sub i32 %x, %y
   ret i32 %z
 ; CHECK-LABEL: @test5(
@@ -87,12 +87,12 @@ define i32 @test5(i32* %p, i64 %i) {
 }
 
 define i32 @test5_as1_smaller_size(i32 addrspace(1)* %p, i8 %i) {
-  %pi = getelementptr i32 addrspace(1)* %p, i8 %i
+  %pi = getelementptr i32, i32 addrspace(1)* %p, i8 %i
   %i.next = add i8 %i, 1
-  %pi.next = getelementptr i32 addrspace(1)* %p, i8 %i.next
-  %x = load i32 addrspace(1)* %pi
+  %pi.next = getelementptr i32, i32 addrspace(1)* %p, i8 %i.next
+  %x = load i32, i32 addrspace(1)* %pi
   store i32 42, i32 addrspace(1)* %pi.next
-  %y = load i32 addrspace(1)* %pi
+  %y = load i32, i32 addrspace(1)* %pi
   %z = sub i32 %x, %y
   ret i32 %z
 ; CHECK-LABEL: @test5_as1_smaller_size(
@@ -101,12 +101,12 @@ define i32 @test5_as1_smaller_size(i32 addrspace(1)* %p, i8 %i) {
 }
 
 define i32 @test5_as1_same_size(i32 addrspace(1)* %p, i16 %i) {
-  %pi = getelementptr i32 addrspace(1)* %p, i16 %i
+  %pi = getelementptr i32, i32 addrspace(1)* %p, i16 %i
   %i.next = add i16 %i, 1
-  %pi.next = getelementptr i32 addrspace(1)* %p, i16 %i.next
-  %x = load i32 addrspace(1)* %pi
+  %pi.next = getelementptr i32, i32 addrspace(1)* %p, i16 %i.next
+  %x = load i32, i32 addrspace(1)* %pi
   store i32 42, i32 addrspace(1)* %pi.next
-  %y = load i32 addrspace(1)* %pi
+  %y = load i32, i32 addrspace(1)* %pi
   %z = sub i32 %x, %y
   ret i32 %z
 ; CHECK-LABEL: @test5_as1_same_size(
@@ -116,12 +116,12 @@ define i32 @test5_as1_same_size(i32 addrspace(1)* %p, i16 %i) {
 ; P[i] != p[(i*4)|1]
 define i32 @test6(i32* %p, i64 %i1) {
   %i = shl i64 %i1, 2
-  %pi = getelementptr i32* %p, i64 %i
+  %pi = getelementptr i32, i32* %p, i64 %i
   %i.next = or i64 %i, 1
-  %pi.next = getelementptr i32* %p, i64 %i.next
-  %x = load i32* %pi
+  %pi.next = getelementptr i32, i32* %p, i64 %i.next
+  %x = load i32, i32* %pi
   store i32 42, i32* %pi.next
-  %y = load i32* %pi
+  %y = load i32, i32* %pi
   %z = sub i32 %x, %y
   ret i32 %z
 ; CHECK-LABEL: @test6(
@@ -130,12 +130,12 @@ define i32 @test6(i32* %p, i64 %i1) {
 
 ; P[1] != P[i*4]
 define i32 @test7(i32* %p, i64 %i) {
-  %pi = getelementptr i32* %p, i64 1
+  %pi = getelementptr i32, i32* %p, i64 1
   %i.next = shl i64 %i, 2
-  %pi.next = getelementptr i32* %p, i64 %i.next
-  %x = load i32* %pi
+  %pi.next = getelementptr i32, i32* %p, i64 %i.next
+  %x = load i32, i32* %pi
   store i32 42, i32* %pi.next
-  %y = load i32* %pi
+  %y = load i32, i32* %pi
   %z = sub i32 %x, %y
   ret i32 %z
 ; CHECK-LABEL: @test7(
@@ -146,13 +146,13 @@ define i32 @test7(i32* %p, i64 %i) {
 ; PR1143
 define i32 @test8(i32* %p, i16 %i) {
   %i1 = zext i16 %i to i32
-  %pi = getelementptr i32* %p, i32 %i1
+  %pi = getelementptr i32, i32* %p, i32 %i1
   %i.next = add i16 %i, 1
   %i.next2 = zext i16 %i.next to i32
-  %pi.next = getelementptr i32* %p, i32 %i.next2
-  %x = load i32* %pi
+  %pi.next = getelementptr i32, i32* %p, i32 %i.next2
+  %x = load i32, i32* %pi
   store i32 42, i32* %pi.next
-  %y = load i32* %pi
+  %y = load i32, i32* %pi
   %z = sub i32 %x, %y
   ret i32 %z
 ; CHECK-LABEL: @test8(
@@ -163,16 +163,16 @@ define i8 @test9([4 x i8] *%P, i32 %i, i32 %j) {
   %i2 = shl i32 %i, 2
   %i3 = add i32 %i2, 1
   ; P2 = P + 1 + 4*i
-  %P2 = getelementptr [4 x i8] *%P, i32 0, i32 %i3
+  %P2 = getelementptr [4 x i8], [4 x i8] *%P, i32 0, i32 %i3
 
   %j2 = shl i32 %j, 2
 
   ; P4 = P + 4*j
-  %P4 = getelementptr [4 x i8]* %P, i32 0, i32 %j2
+  %P4 = getelementptr [4 x i8], [4 x i8]* %P, i32 0, i32 %j2
 
-  %x = load i8* %P2
+  %x = load i8, i8* %P2
   store i8 42, i8* %P4
-  %y = load i8* %P2
+  %y = load i8, i8* %P2
   %z = sub i8 %x, %y
   ret i8 %z
 ; CHECK-LABEL: @test9(
@@ -183,14 +183,14 @@ define i8 @test10([4 x i8] *%P, i32 %i) {
   %i2 = shl i32 %i, 2
   %i3 = add i32 %i2, 4
   ; P2 = P + 4 + 4*i
-  %P2 = getelementptr [4 x i8] *%P, i32 0, i32 %i3
+  %P2 = getelementptr [4 x i8], [4 x i8] *%P, i32 0, i32 %i3
 
   ; P4 = P + 4*i
-  %P4 = getelementptr [4 x i8]* %P, i32 0, i32 %i2
+  %P4 = getelementptr [4 x i8], [4 x i8]* %P, i32 0, i32 %i2
 
-  %x = load i8* %P2
+  %x = load i8, i8* %P2
   store i8 42, i8* %P4
-  %y = load i8* %P2
+  %y = load i8, i8* %P2
   %z = sub i8 %x, %y
   ret i8 %z
 ; CHECK-LABEL: @test10(
@@ -201,13 +201,13 @@ define i8 @test10([4 x i8] *%P, i32 %i) {
 define float @test11(i32 %indvar, [4 x [2 x float]]* %q) nounwind ssp {
   %tmp = mul i32 %indvar, -1
   %dec = add i32 %tmp, 3
-  %scevgep = getelementptr [4 x [2 x float]]* %q, i32 0, i32 %dec
+  %scevgep = getelementptr [4 x [2 x float]], [4 x [2 x float]]* %q, i32 0, i32 %dec
   %scevgep35 = bitcast [2 x float]* %scevgep to i64*
-  %arrayidx28 = getelementptr inbounds [4 x [2 x float]]* %q, i32 0, i32 0
-  %y29 = getelementptr inbounds [2 x float]* %arrayidx28, i32 0, i32 1
+  %arrayidx28 = getelementptr inbounds [4 x [2 x float]], [4 x [2 x float]]* %q, i32 0, i32 0
+  %y29 = getelementptr inbounds [2 x float], [2 x float]* %arrayidx28, i32 0, i32 1
   store float 1.0, float* %y29, align 4
   store i64 0, i64* %scevgep35, align 4
-  %tmp30 = load float* %y29, align 4
+  %tmp30 = load float, float* %y29, align 4
   ret float %tmp30
 ; CHECK-LABEL: @test11(
 ; CHECK: ret float %tmp30
@@ -216,14 +216,14 @@ define float @test11(i32 %indvar, [4 x [2 x float]]* %q) nounwind ssp {
 ; (This was a miscompilation.)
 define i32 @test12(i32 %x, i32 %y, i8* %p) nounwind {
   %a = bitcast i8* %p to [13 x i8]*
-  %b = getelementptr [13 x i8]* %a, i32 %x
+  %b = getelementptr [13 x i8], [13 x i8]* %a, i32 %x
   %c = bitcast [13 x i8]* %b to [15 x i8]*
-  %d = getelementptr [15 x i8]* %c, i32 %y, i32 8
+  %d = getelementptr [15 x i8], [15 x i8]* %c, i32 %y, i32 8
   %castd = bitcast i8* %d to i32*
   %castp = bitcast i8* %p to i32*
   store i32 1, i32* %castp
   store i32 0, i32* %castd
-  %r = load i32* %castp
+  %r = load i32, i32* %castp
   ret i32 %r
 ; CHECK-LABEL: @test12(
 ; CHECK: ret i32 %r
diff --git a/test/Analysis/BasicAA/global-size.ll b/test/Analysis/BasicAA/global-size.ll
index f081cb1e0724..bacf3bc9c1b9 100644
--- a/test/Analysis/BasicAA/global-size.ll
+++ b/test/Analysis/BasicAA/global-size.ll
@@ -8,9 +8,9 @@ target datalayout = "E-p:64:64:64-p1:16:16:16-a0:0:8-f32:32:32-f64:64:64-i1:8:8-
 
 ; CHECK-LABEL: @test1(
 define i16 @test1(i32* %P) {
-        %X = load i16* @B
+        %X = load i16, i16* @B
         store i32 7, i32* %P
-        %Y = load i16* @B
+        %Y = load i16, i16* @B
         %Z = sub i16 %Y, %X
         ret i16 %Z
 ; CHECK: ret i16 0
@@ -21,9 +21,9 @@ define i16 @test1(i32* %P) {
 define i16 @test1_as1(i32 addrspace(1)* %P) {
 ; CHECK-LABEL: @test1_as1(
 ; CHECK: ret i16 0
-  %X = load i16 addrspace(1)* @B_as1
+  %X = load i16, i16 addrspace(1)* @B_as1
   store i32 7, i32 addrspace(1)* %P
-  %Y = load i16 addrspace(1)* @B_as1
+  %Y = load i16, i16 addrspace(1)* @B_as1
   %Z = sub i16 %Y, %X
   ret i16 %Z
 }
@@ -35,14 +35,14 @@ define i16 @test1_as1(i32 addrspace(1)* %P) {
 ; CHECK-LABEL: @test2(
 define i8 @test2(i32 %tmp79, i32 %w.2, i32 %indvar89) nounwind {
   %tmp92 = add i32 %tmp79, %indvar89
-  %arrayidx412 = getelementptr [0 x i8]* @window, i32 0, i32 %tmp92
+  %arrayidx412 = getelementptr [0 x i8], [0 x i8]* @window, i32 0, i32 %tmp92
   %tmp93 = add i32 %w.2, %indvar89
-  %arrayidx416 = getelementptr [0 x i8]* @window, i32 0, i32 %tmp93
+  %arrayidx416 = getelementptr [0 x i8], [0 x i8]* @window, i32 0, i32 %tmp93
 
-  %A = load i8* %arrayidx412, align 1
+  %A = load i8, i8* %arrayidx412, align 1
   store i8 4, i8* %arrayidx416, align 1
 
-  %B = load i8* %arrayidx412, align 1
+  %B = load i8, i8* %arrayidx412, align 1
   %C = sub i8 %A, %B
   ret i8 %C
 
diff --git a/test/Analysis/BasicAA/intrinsics.ll b/test/Analysis/BasicAA/intrinsics.ll
index c1cf587204cf..8c05587ce233 100644
--- a/test/Analysis/BasicAA/intrinsics.ll
+++ b/test/Analysis/BasicAA/intrinsics.ll
@@ -21,13 +21,13 @@ entry:
 
 ; CHECK:      define <8 x i16> @test1(i8* %p, <8 x i16> %y) {
 ; CHECK-NEXT: entry:
-; CHECK-NEXT:   %q = getelementptr i8* %p, i64 16
+; CHECK-NEXT:   %q = getelementptr i8, i8* %p, i64 16
 ; CHECK-NEXT:   %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) [[ATTR]]
 ; CHECK-NEXT:   call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16)
 ; CHECK-NEXT:   %c = add <8 x i16> %a, %a
 define <8 x i16> @test1(i8* %p, <8 x i16> %y) {
 entry:
-  %q = getelementptr i8* %p, i64 16
+  %q = getelementptr i8, i8* %p, i64 16
   %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind
   call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16)
   %b = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind
diff --git a/test/Analysis/BasicAA/invariant_load.ll b/test/Analysis/BasicAA/invariant_load.ll
index bc629cdfe9ea..722fb5b47650 100644
--- a/test/Analysis/BasicAA/invariant_load.ll
+++ b/test/Analysis/BasicAA/invariant_load.ll
@@ -10,15 +10,15 @@
 
 define i32 @foo(i32* nocapture %p, i8* nocapture %q) {
 entry:
-  %0 = load i32* %p, align 4, !invariant.load !3
+  %0 = load i32, i32* %p, align 4, !invariant.load !3
   %conv = trunc i32 %0 to i8
   store i8 %conv, i8* %q, align 1
-  %1 = load i32* %p, align 4, !invariant.load !3
+  %1 = load i32, i32* %p, align 4, !invariant.load !3
   %add = add nsw i32 %1, 1
   ret i32 %add
 
 ; CHECK: foo
-; CHECK: %0 = load i32* %p
+; CHECK: %0 = load i32, i32* %p
 ; CHECK: store i8 %conv, i8* %q,
 ; CHECK: %add = add nsw i32 %0, 1
 }
diff --git a/test/Analysis/BasicAA/memset_pattern.ll b/test/Analysis/BasicAA/memset_pattern.ll
index 590664c5084e..25bdb2e202fb 100644
--- a/test/Analysis/BasicAA/memset_pattern.ll
+++ b/test/Analysis/BasicAA/memset_pattern.ll
@@ -13,7 +13,7 @@ entry:
   store i32 1, i32* @z
   tail call void @memset_pattern16(i8* bitcast (i32* @y to i8*), i8* bitcast (i32* @x to i8*), i64 4) nounwind
 ; CHECK-NOT: load
-  %l = load i32* @z
+  %l = load i32, i32* @z
 ; CHECK: ret i32 1
   ret i32 %l
 }
diff --git a/test/Analysis/BasicAA/modref.ll b/test/Analysis/BasicAA/modref.ll
index 0d8bf71d42fe..e124d6cbe20f 100644
--- a/test/Analysis/BasicAA/modref.ll
+++ b/test/Analysis/BasicAA/modref.ll
@@ -13,7 +13,7 @@ define i32 @test0(i8* %P) {
 
   call void @llvm.memset.p0i8.i32(i8* %P, i8 0, i32 42, i32 1, i1 false)
 
-  %B = load i32* %A
+  %B = load i32, i32* %A
   ret i32 %B
 
 ; CHECK-LABEL: @test0
@@ -29,30 +29,30 @@ define i8 @test1() {
 
   call void @llvm.memcpy.p0i8.p0i8.i8(i8* %A, i8* %B, i8 -1, i32 0, i1 false)
 
-  %C = load i8* %B
+  %C = load i8, i8* %B
   ret i8 %C
 ; CHECK: ret i8 2
 }
 
 define i8 @test2(i8* %P) {
 ; CHECK-LABEL: @test2
-  %P2 = getelementptr i8* %P, i32 127
+  %P2 = getelementptr i8, i8* %P, i32 127
   store i8 1, i8* %P2  ;; Not dead across memset
   call void @llvm.memset.p0i8.i8(i8* %P, i8 2, i8 127, i32 0, i1 false)
-  %A = load i8* %P2
+  %A = load i8, i8* %P2
   ret i8 %A
 ; CHECK: ret i8 1
 }
 
 define i8 @test2a(i8* %P) {
 ; CHECK-LABEL: @test2
-  %P2 = getelementptr i8* %P, i32 126
+  %P2 = getelementptr i8, i8* %P, i32 126
 
   ;; FIXME: DSE isn't zapping this dead store.
   store i8 1, i8* %P2  ;; Dead, clobbered by memset.
 
   call void @llvm.memset.p0i8.i8(i8* %P, i8 2, i8 127, i32 0, i1 false)
-  %A = load i8* %P2
+  %A = load i8, i8* %P2
   ret i8 %A
 ; CHECK-NOT: load
 ; CHECK: ret i8 2
@@ -64,7 +64,7 @@ define void @test3(i8* %P, i8 %X) {
 ; CHECK-NOT: %Y
   %Y = add i8 %X, 1     ;; Dead, because the only use (the store) is dead.
 
-  %P2 = getelementptr i8* %P, i32 2
+  %P2 = getelementptr i8, i8* %P, i32 2
   store i8 %Y, i8* %P2  ;; Not read by lifetime.end, should be removed.
 ; CHECK: store i8 2, i8* %P2
   call void @llvm.lifetime.end(i64 1, i8* %P)
@@ -78,7 +78,7 @@ define void @test3a(i8* %P, i8 %X) {
 ; CHECK-LABEL: @test3a
   %Y = add i8 %X, 1     ;; Dead, because the only use (the store) is dead.
 
-  %P2 = getelementptr i8* %P, i32 2
+  %P2 = getelementptr i8, i8* %P, i32 2
   store i8 %Y, i8* %P2
 ; CHECK-NEXT: call void @llvm.lifetime.end
   call void @llvm.lifetime.end(i64 10, i8* %P)
@@ -90,9 +90,9 @@ define void @test3a(i8* %P, i8 %X) {
 @G2 = external global [4000 x i32]
 
 define i32 @test4(i8* %P) {
-  %tmp = load i32* @G1
+  %tmp = load i32, i32* @G1
   call void @llvm.memset.p0i8.i32(i8* bitcast ([4000 x i32]* @G2 to i8*), i8 0, i32 4000, i32 1, i1 false)
-  %tmp2 = load i32* @G1
+  %tmp2 = load i32, i32* @G1
   %sub = sub i32 %tmp2, %tmp
   ret i32 %sub
 ; CHECK-LABEL: @test4
@@ -105,9 +105,9 @@ define i32 @test4(i8* %P) {
 ; Verify that basicaa is handling variable length memcpy, knowing it doesn't
 ; write to G1.
 define i32 @test5(i8* %P, i32 %Len) {
-  %tmp = load i32* @G1
+  %tmp = load i32, i32* @G1
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* bitcast ([4000 x i32]* @G2 to i8*), i8* bitcast (i32* @G1 to i8*), i32 %Len, i32 1, i1 false)
-  %tmp2 = load i32* @G1
+  %tmp2 = load i32, i32* @G1
   %sub = sub i32 %tmp2, %tmp
   ret i32 %sub
 ; CHECK: @test5
@@ -118,13 +118,13 @@ define i32 @test5(i8* %P, i32 %Len) {
 }
 
 define i8 @test6(i8* %p, i8* noalias %a) {
-  %x = load i8* %a
+  %x = load i8, i8* %a
   %t = va_arg i8* %p, float
-  %y = load i8* %a
+  %y = load i8, i8* %a
   %z = add i8 %x, %y
   ret i8 %z
 ; CHECK-LABEL: @test6
-; CHECK: load i8* %a
+; CHECK: load i8, i8* %a
 ; CHECK-NOT: load
 ; CHECK: ret
 }
@@ -135,14 +135,14 @@ define i32 @test7() nounwind uwtable ssp {
 entry:
   %x = alloca i32, align 4
   store i32 0, i32* %x, align 4
-  %add.ptr = getelementptr inbounds i32* %x, i64 1
+  %add.ptr = getelementptr inbounds i32, i32* %x, i64 1
   call void @test7decl(i32* %add.ptr)
-  %tmp = load i32* %x, align 4
+  %tmp = load i32, i32* %x, align 4
   ret i32 %tmp
 ; CHECK-LABEL: @test7(
 ; CHECK: store i32 0
 ; CHECK: call void @test7decl
-; CHECK: load i32*
+; CHECK: load i32, i32*
 }
 
 declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
diff --git a/test/Analysis/BasicAA/must-and-partial.ll b/test/Analysis/BasicAA/must-and-partial.ll
index 58139ff30eca..3b4c84a2f81b 100644
--- a/test/Analysis/BasicAA/must-and-partial.ll
+++ b/test/Analysis/BasicAA/must-and-partial.ll
@@ -9,7 +9,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; CHECK: PartialAlias:  i16* %bigbase0, i8* %phi
 define i8 @test0(i8* %base, i1 %x) {
 entry:
-  %baseplusone = getelementptr i8* %base, i64 1
+  %baseplusone = getelementptr i8, i8* %base, i64 1
   br i1 %x, label %red, label %green
 red:
   br label %green
@@ -20,20 +20,20 @@ green:
   %bigbase0 = bitcast i8* %base to i16*
   store i16 -1, i16* %bigbase0
 
-  %loaded = load i8* %phi
+  %loaded = load i8, i8* %phi
   ret i8 %loaded
 }
 
 ; CHECK: PartialAlias:  i16* %bigbase1, i8* %sel
 define i8 @test1(i8* %base, i1 %x) {
 entry:
-  %baseplusone = getelementptr i8* %base, i64 1
+  %baseplusone = getelementptr i8, i8* %base, i64 1
   %sel = select i1 %x, i8* %baseplusone, i8* %base
   store i8 0, i8* %sel
 
   %bigbase1 = bitcast i8* %base to i16*
   store i16 -1, i16* %bigbase1
 
-  %loaded = load i8* %sel
+  %loaded = load i8, i8* %sel
   ret i8 %loaded
 }
diff --git a/test/Analysis/BasicAA/no-escape-call.ll b/test/Analysis/BasicAA/no-escape-call.ll
index b93db6e0ee7c..ea335325170a 100644
--- a/test/Analysis/BasicAA/no-escape-call.ll
+++ b/test/Analysis/BasicAA/no-escape-call.ll
@@ -8,13 +8,13 @@ define i1 @foo(i32 %i) nounwind  {
 entry:
 	%arr = alloca [10 x i8*]		; <[10 x i8*]*> [#uses=1]
 	%tmp2 = call i8* @getPtr( ) nounwind 		; <i8*> [#uses=2]
-	%tmp4 = getelementptr [10 x i8*]* %arr, i32 0, i32 %i		; <i8**> [#uses=2]
+	%tmp4 = getelementptr [10 x i8*], [10 x i8*]* %arr, i32 0, i32 %i		; <i8**> [#uses=2]
 	store i8* %tmp2, i8** %tmp4, align 4
-	%tmp10 = getelementptr i8* %tmp2, i32 10		; <i8*> [#uses=1]
+	%tmp10 = getelementptr i8, i8* %tmp2, i32 10		; <i8*> [#uses=1]
 	store i8 42, i8* %tmp10, align 1
-	%tmp14 = load i8** %tmp4, align 4		; <i8*> [#uses=1]
-	%tmp16 = getelementptr i8* %tmp14, i32 10		; <i8*> [#uses=1]
-	%tmp17 = load i8* %tmp16, align 1		; <i8> [#uses=1]
+	%tmp14 = load i8*, i8** %tmp4, align 4		; <i8*> [#uses=1]
+	%tmp16 = getelementptr i8, i8* %tmp14, i32 10		; <i8*> [#uses=1]
+	%tmp17 = load i8, i8* %tmp16, align 1		; <i8> [#uses=1]
 	%tmp19 = icmp eq i8 %tmp17, 42		; <i1> [#uses=1]
 	ret i1 %tmp19
 }
diff --git a/test/Analysis/BasicAA/noalias-bugs.ll b/test/Analysis/BasicAA/noalias-bugs.ll
index 2bcc14fd9397..acb230c45de4 100644
--- a/test/Analysis/BasicAA/noalias-bugs.ll
+++ b/test/Analysis/BasicAA/noalias-bugs.ll
@@ -12,12 +12,12 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define i64 @testcase(%nested * noalias %p1, %nested * noalias %p2,
                      i32 %a, i32 %b) {
-  %ptr = getelementptr inbounds %nested* %p1, i64 -1, i32 0
-  %ptr.64 = getelementptr inbounds %nested.i64* %ptr, i64 0, i32 0
-  %ptr2= getelementptr inbounds %nested* %p2, i64 0, i32 0
+  %ptr = getelementptr inbounds %nested, %nested* %p1, i64 -1, i32 0
+  %ptr.64 = getelementptr inbounds %nested.i64, %nested.i64* %ptr, i64 0, i32 0
+  %ptr2= getelementptr inbounds %nested, %nested* %p2, i64 0, i32 0
   %cmp = icmp ult i32 %a, %b
   %either_ptr = select i1 %cmp, %nested.i64* %ptr2, %nested.i64* %ptr
-  %either_ptr.64 = getelementptr inbounds %nested.i64* %either_ptr, i64 0, i32 0
+  %either_ptr.64 = getelementptr inbounds %nested.i64, %nested.i64* %either_ptr, i64 0, i32 0
 
 ; Because either_ptr.64 and ptr.64 can alias (we used to return noalias)
 ; elimination of the first store is not valid.
@@ -27,7 +27,7 @@ define i64 @testcase(%nested * noalias %p1, %nested * noalias %p2,
 ; CHECK; store i64 1
 
   store i64 2, i64* %ptr.64, align 8
-  %r = load i64* %either_ptr.64, align 8
+  %r = load i64, i64* %either_ptr.64, align 8
   store i64 1, i64* %ptr.64, align 8
   ret i64 %r
 }
diff --git a/test/Analysis/BasicAA/noalias-geps.ll b/test/Analysis/BasicAA/noalias-geps.ll
index f9ec71345739..cdec9889ca88 100644
--- a/test/Analysis/BasicAA/noalias-geps.ll
+++ b/test/Analysis/BasicAA/noalias-geps.ll
@@ -5,26 +5,26 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 ; Check that geps with equal base offsets of noalias base pointers stay noalias.
 define i32 @test(i32* %p, i16 %i) {
 ; CHECK-LABEL: Function: test:
-  %pi = getelementptr i32* %p, i32 0
-  %pi.next = getelementptr i32* %p, i32 1
+  %pi = getelementptr i32, i32* %p, i32 0
+  %pi.next = getelementptr i32, i32* %p, i32 1
   %b = icmp eq i16 %i, 0
   br i1 %b, label %bb1, label %bb2
 
 bb1:
-  %f = getelementptr i32* %pi, i32 1
-  %g = getelementptr i32* %pi.next, i32 1
+  %f = getelementptr i32, i32* %pi, i32 1
+  %g = getelementptr i32, i32* %pi.next, i32 1
   br label %bb3
 bb2:
-  %f2 = getelementptr i32* %pi, i32 1
-  %g2 = getelementptr i32* %pi.next, i32 1
+  %f2 = getelementptr i32, i32* %pi, i32 1
+  %g2 = getelementptr i32, i32* %pi.next, i32 1
   br label %bb3
 
 bb3:
   %ptr_phi = phi i32* [ %f, %bb1 ], [ %f2, %bb2 ]
   %ptr_phi2 = phi i32* [ %g, %bb1 ], [ %g2, %bb2 ]
 ; CHECK: NoAlias: i32* %f1, i32* %g1
-  %f1 = getelementptr i32* %ptr_phi , i32 1
-  %g1 = getelementptr i32* %ptr_phi2 , i32 1
+  %f1 = getelementptr i32, i32* %ptr_phi , i32 1
+  %g1 = getelementptr i32, i32* %ptr_phi2 , i32 1
 
 ret i32 0
 }
@@ -32,25 +32,25 @@ ret i32 0
 ; Check that geps with equal indices of noalias base pointers stay noalias.
 define i32 @test2([2 x i32]* %p, i32 %i) {
 ; CHECK-LABEL: Function: test2:
-  %pi = getelementptr [2 x i32]* %p, i32 0
-  %pi.next = getelementptr [2 x i32]* %p, i32 1
+  %pi = getelementptr [2 x i32], [2 x i32]* %p, i32 0
+  %pi.next = getelementptr [2 x i32], [2 x i32]* %p, i32 1
   %b = icmp eq i32 %i, 0
   br i1 %b, label %bb1, label %bb2
 
 bb1:
-  %f = getelementptr [2 x i32]* %pi, i32 1
-  %g = getelementptr [2 x i32]* %pi.next, i32 1
+  %f = getelementptr [2 x i32], [2 x i32]* %pi, i32 1
+  %g = getelementptr [2 x i32], [2 x i32]* %pi.next, i32 1
   br label %bb3
 bb2:
-  %f2 = getelementptr [2 x i32]* %pi, i32 1
-  %g2 = getelementptr [2 x i32]* %pi.next, i32 1
+  %f2 = getelementptr [2 x i32], [2 x i32]* %pi, i32 1
+  %g2 = getelementptr [2 x i32], [2 x i32]* %pi.next, i32 1
   br label %bb3
 bb3:
   %ptr_phi = phi [2 x i32]* [ %f, %bb1 ], [ %f2, %bb2 ]
   %ptr_phi2 = phi [2 x i32]* [ %g, %bb1 ], [ %g2, %bb2 ]
 ; CHECK: NoAlias: i32* %f1, i32* %g1
-  %f1 = getelementptr [2 x i32]* %ptr_phi , i32 1, i32 %i
-  %g1 = getelementptr [2 x i32]* %ptr_phi2 , i32 1, i32 %i
+  %f1 = getelementptr [2 x i32], [2 x i32]* %ptr_phi , i32 1, i32 %i
+  %g1 = getelementptr [2 x i32], [2 x i32]* %ptr_phi2 , i32 1, i32 %i
 
 ret i32 0
 }
diff --git a/test/Analysis/BasicAA/noalias-param.ll b/test/Analysis/BasicAA/noalias-param.ll
index 6494771fc59f..c5b1ebf1a1d2 100644
--- a/test/Analysis/BasicAA/noalias-param.ll
+++ b/test/Analysis/BasicAA/noalias-param.ll
@@ -6,7 +6,7 @@ define void @no(i32* noalias %a, i32* %b) nounwind {
 entry:
   store i32 1, i32* %a 
   %cap = call i32* @captures(i32* %a) nounwind readonly
-  %l = load i32* %b
+  %l = load i32, i32* %b
   ret void
 }
 
@@ -16,7 +16,7 @@ define void @yes(i32* %c, i32* %d) nounwind {
 entry:
   store i32 1, i32* %c 
   %cap = call i32* @captures(i32* %c) nounwind readonly
-  %l = load i32* %d
+  %l = load i32, i32* %d
   ret void
 }
 
diff --git a/test/Analysis/BasicAA/nocapture.ll b/test/Analysis/BasicAA/nocapture.ll
index ffc0a09a078d..26cb69bffcc0 100644
--- a/test/Analysis/BasicAA/nocapture.ll
+++ b/test/Analysis/BasicAA/nocapture.ll
@@ -6,9 +6,9 @@ define i32 @test2() {
 ; CHECK: ret i32 0
        %P = alloca i32
        %Q = call i32* @test(i32* %P)
-       %a = load i32* %P
+       %a = load i32, i32* %P
        store i32 4, i32* %Q   ;; cannot clobber P since it is nocapture.
-       %b = load i32* %P
+       %b = load i32, i32* %P
        %c = sub i32 %a, %b
        ret i32 %c
 }
@@ -19,7 +19,7 @@ define i32 @test4(i32* noalias nocapture %p) nounwind {
 ; CHECK: call void @test3
 ; CHECK: store i32 0, i32* %p
 ; CHECK: store i32 1, i32* %x
-; CHECK: %y = load i32* %p
+; CHECK: %y = load i32, i32* %p
 ; CHECK: ret i32 %y
 entry:
        %q = alloca i32*
@@ -27,10 +27,10 @@ entry:
        ; attribute since the copy doesn't outlive the function.
        call void @test3(i32** %q, i32* %p) nounwind
        store i32 0, i32* %p
-       %x = load i32** %q
+       %x = load i32*, i32** %q
        ; This store might write to %p and so we can't eliminate the subsequent
        ; load
        store i32 1, i32* %x
-       %y = load i32* %p
+       %y = load i32, i32* %p
        ret i32 %y
 }
diff --git a/test/Analysis/BasicAA/phi-aa.ll b/test/Analysis/BasicAA/phi-aa.ll
index c1100f1d36fc..3944e9e43566 100644
--- a/test/Analysis/BasicAA/phi-aa.ll
+++ b/test/Analysis/BasicAA/phi-aa.ll
@@ -25,9 +25,9 @@ bb1:
 
 bb2:
   %P = phi i32* [ @X, %bb ], [ @Y, %bb1 ]
-  %tmp1 = load i32* @Z, align 4
+  %tmp1 = load i32, i32* @Z, align 4
   store i32 123, i32* %P, align 4
-  %tmp2 = load i32* @Z, align 4
+  %tmp2 = load i32, i32* @Z, align 4
   br label %return
 
 return:
@@ -52,23 +52,23 @@ codeRepl:
   br i1 %targetBlock, label %for.body, label %bye
 
 for.body:
-  %1 = load i32* %jj7, align 4
+  %1 = load i32, i32* %jj7, align 4
   %idxprom4 = zext i32 %1 to i64
-  %arrayidx5 = getelementptr inbounds [100 x i32]* %oa5, i64 0, i64 %idxprom4
-  %2 = load i32* %arrayidx5, align 4
+  %arrayidx5 = getelementptr inbounds [100 x i32], [100 x i32]* %oa5, i64 0, i64 %idxprom4
+  %2 = load i32, i32* %arrayidx5, align 4
   %sub6 = sub i32 %2, 6
   store i32 %sub6, i32* %arrayidx5, align 4
   ; %0 and %arrayidx5 can alias! It is not safe to DSE the above store.
-  %3 = load i32* %0, align 4
+  %3 = load i32, i32* %0, align 4
   store i32 %3, i32* %arrayidx5, align 4
   %sub11 = add i32 %1, -1
   %idxprom12 = zext i32 %sub11 to i64
-  %arrayidx13 = getelementptr inbounds [100 x i32]* %oa5, i64 0, i64 %idxprom12
+  %arrayidx13 = getelementptr inbounds [100 x i32], [100 x i32]* %oa5, i64 0, i64 %idxprom12
   call void @inc(i32* %jj7)
   br label %codeRepl
 
 bye:
-  %.reload = load i32* %jj7, align 4
+  %.reload = load i32, i32* %jj7, align 4
   ret i32 %.reload
 }
 
diff --git a/test/Analysis/BasicAA/phi-spec-order.ll b/test/Analysis/BasicAA/phi-spec-order.ll
index 4172d0963f34..b326dc360060 100644
--- a/test/Analysis/BasicAA/phi-spec-order.ll
+++ b/test/Analysis/BasicAA/phi-spec-order.ll
@@ -14,7 +14,7 @@ for.cond2.preheader:                              ; preds = %for.end, %entry
   br label %for.body4
 
 for.body4:                                        ; preds = %for.body4, %for.cond2.preheader
-  %lsr.iv4 = phi [16000 x double]* [ %i11, %for.body4 ], [ bitcast (double* getelementptr inbounds ([16000 x double]* @Y, i64 0, i64 8)
+  %lsr.iv4 = phi [16000 x double]* [ %i11, %for.body4 ], [ bitcast (double* getelementptr inbounds ([16000 x double], [16000 x double]* @Y, i64 0, i64 8)
  to [16000 x double]*), %for.cond2.preheader ]
   %lsr.iv1 = phi [16000 x double]* [ %i10, %for.body4 ], [ @X, %for.cond2.preheader ]
 
@@ -23,23 +23,23 @@ for.body4:                                        ; preds = %for.body4, %for.con
   %lsr.iv = phi i32 [ %lsr.iv.next, %for.body4 ], [ 16000, %for.cond2.preheader ]
   %lsr.iv46 = bitcast [16000 x double]* %lsr.iv4 to <4 x double>*
   %lsr.iv12 = bitcast [16000 x double]* %lsr.iv1 to <4 x double>*
-  %scevgep11 = getelementptr <4 x double>* %lsr.iv46, i64 -2
-  %i6 = load <4 x double>* %scevgep11, align 32
+  %scevgep11 = getelementptr <4 x double>, <4 x double>* %lsr.iv46, i64 -2
+  %i6 = load <4 x double>, <4 x double>* %scevgep11, align 32
   %add = fadd <4 x double> %i6, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>
   store <4 x double> %add, <4 x double>* %lsr.iv12, align 32
-  %scevgep10 = getelementptr <4 x double>* %lsr.iv46, i64 -1
-  %i7 = load <4 x double>* %scevgep10, align 32
+  %scevgep10 = getelementptr <4 x double>, <4 x double>* %lsr.iv46, i64 -1
+  %i7 = load <4 x double>, <4 x double>* %scevgep10, align 32
   %add.4 = fadd <4 x double> %i7, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>
-  %scevgep9 = getelementptr <4 x double>* %lsr.iv12, i64 1
+  %scevgep9 = getelementptr <4 x double>, <4 x double>* %lsr.iv12, i64 1
   store <4 x double> %add.4, <4 x double>* %scevgep9, align 32
-  %i8 = load <4 x double>* %lsr.iv46, align 32
+  %i8 = load <4 x double>, <4 x double>* %lsr.iv46, align 32
   %add.8 = fadd <4 x double> %i8, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>
-  %scevgep8 = getelementptr <4 x double>* %lsr.iv12, i64 2
+  %scevgep8 = getelementptr <4 x double>, <4 x double>* %lsr.iv12, i64 2
   store <4 x double> %add.8, <4 x double>* %scevgep8, align 32
-  %scevgep7 = getelementptr <4 x double>* %lsr.iv46, i64 1
-  %i9 = load <4 x double>* %scevgep7, align 32
+  %scevgep7 = getelementptr <4 x double>, <4 x double>* %lsr.iv46, i64 1
+  %i9 = load <4 x double>, <4 x double>* %scevgep7, align 32
   %add.12 = fadd <4 x double> %i9, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>
-  %scevgep3 = getelementptr <4 x double>* %lsr.iv12, i64 3
+  %scevgep3 = getelementptr <4 x double>, <4 x double>* %lsr.iv12, i64 3
   store <4 x double> %add.12, <4 x double>* %scevgep3, align 32
 
 ; CHECK: NoAlias:{{[ \t]+}}<4 x double>* %scevgep11, <4 x double>* %scevgep7
@@ -50,9 +50,9 @@ for.body4:                                        ; preds = %for.body4, %for.con
 ; CHECK: NoAlias:{{[ \t]+}}<4 x double>* %scevgep3, <4 x double>* %scevgep9
 
   %lsr.iv.next = add i32 %lsr.iv, -16
-  %scevgep = getelementptr [16000 x double]* %lsr.iv1, i64 0, i64 16
+  %scevgep = getelementptr [16000 x double], [16000 x double]* %lsr.iv1, i64 0, i64 16
   %i10 = bitcast double* %scevgep to [16000 x double]*
-  %scevgep5 = getelementptr [16000 x double]* %lsr.iv4, i64 0, i64 16
+  %scevgep5 = getelementptr [16000 x double], [16000 x double]* %lsr.iv4, i64 0, i64 16
   %i11 = bitcast double* %scevgep5 to [16000 x double]*
   %exitcond.15 = icmp eq i32 %lsr.iv.next, 0
   br i1 %exitcond.15, label %for.end, label %for.body4
diff --git a/test/Analysis/BasicAA/phi-speculation.ll b/test/Analysis/BasicAA/phi-speculation.ll
index 5e1e118d9855..ed0d49bc0994 100644
--- a/test/Analysis/BasicAA/phi-speculation.ll
+++ b/test/Analysis/BasicAA/phi-speculation.ll
@@ -8,7 +8,7 @@ target datalayout =
 ; CHECK: NoAlias: i32* %ptr2_phi, i32* %ptr_phi
 define i32 @test_noalias_1(i32* %ptr2, i32 %count, i32* %coeff) {
 entry:
-  %ptr = getelementptr inbounds i32* %ptr2, i64 1
+  %ptr = getelementptr inbounds i32, i32* %ptr2, i64 1
   br label %while.body
 
 while.body:
@@ -17,15 +17,15 @@ while.body:
   %ptr2_phi = phi i32* [ %ptr2, %entry ], [ %ptr2_inc, %while.body ]
   %result.09 = phi i32 [ 0 , %entry ], [ %add, %while.body ]
   %dec = add nsw i32 %num, -1
-  %0 = load i32* %ptr_phi, align 4
+  %0 = load i32, i32* %ptr_phi, align 4
   store i32 %0, i32* %ptr2_phi, align 4
-  %1 = load i32* %coeff, align 4
-  %2 = load i32* %ptr_phi, align 4
+  %1 = load i32, i32* %coeff, align 4
+  %2 = load i32, i32* %ptr_phi, align 4
   %mul = mul nsw i32 %1, %2
   %add = add nsw i32 %mul, %result.09
   %tobool = icmp eq i32 %dec, 0
-  %ptr_inc = getelementptr inbounds i32* %ptr_phi, i64 1
-  %ptr2_inc = getelementptr inbounds i32* %ptr2_phi, i64 1
+  %ptr_inc = getelementptr inbounds i32, i32* %ptr_phi, i64 1
+  %ptr2_inc = getelementptr inbounds i32, i32* %ptr2_phi, i64 1
   br i1 %tobool, label %the_exit, label %while.body
 
 the_exit:
@@ -37,7 +37,7 @@ the_exit:
 ; CHECK: NoAlias: i32* %ptr2_phi, i32* %ptr_phi
 define i32 @test_noalias_2(i32* %ptr2, i32 %count, i32* %coeff) {
 entry:
-  %ptr = getelementptr inbounds i32* %ptr2, i64 1
+  %ptr = getelementptr inbounds i32, i32* %ptr2, i64 1
   br label %outer.while.header
 
 outer.while.header:
@@ -52,20 +52,20 @@ while.body:
   %ptr2_phi = phi i32* [ %ptr_outer_phi2, %outer.while.header ], [ %ptr2_inc, %while.body ]
   %result.09 = phi i32 [ 0 , %outer.while.header ], [ %add, %while.body ]
   %dec = add nsw i32 %num, -1
-  %0 = load i32* %ptr_phi, align 4
+  %0 = load i32, i32* %ptr_phi, align 4
   store i32 %0, i32* %ptr2_phi, align 4
-  %1 = load i32* %coeff, align 4
-  %2 = load i32* %ptr_phi, align 4
+  %1 = load i32, i32* %coeff, align 4
+  %2 = load i32, i32* %ptr_phi, align 4
   %mul = mul nsw i32 %1, %2
   %add = add nsw i32 %mul, %result.09
   %tobool = icmp eq i32 %dec, 0
-  %ptr_inc = getelementptr inbounds i32* %ptr_phi, i64 1
-  %ptr2_inc = getelementptr inbounds i32* %ptr2_phi, i64 1
+  %ptr_inc = getelementptr inbounds i32, i32* %ptr_phi, i64 1
+  %ptr2_inc = getelementptr inbounds i32, i32* %ptr2_phi, i64 1
   br i1 %tobool, label %outer.while.backedge, label %while.body
 
 outer.while.backedge:
-  %ptr_inc_outer = getelementptr inbounds i32* %ptr_phi, i64 1
-  %ptr2_inc_outer = getelementptr inbounds i32* %ptr2_phi, i64 1
+  %ptr_inc_outer = getelementptr inbounds i32, i32* %ptr_phi, i64 1
+  %ptr2_inc_outer = getelementptr inbounds i32, i32* %ptr2_phi, i64 1
   %dec.outer = add nsw i32 %num.outer, -1
   %br.cond = icmp eq i32 %dec.outer, 0
   br i1 %br.cond, label %the_exit, label %outer.while.header
diff --git a/test/Analysis/BasicAA/pr18573.ll b/test/Analysis/BasicAA/pr18573.ll
index 1d2a316b6ffe..ea5e4a2082f3 100644
--- a/test/Analysis/BasicAA/pr18573.ll
+++ b/test/Analysis/BasicAA/pr18573.ll
@@ -10,8 +10,8 @@ declare <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float>, i8*, <8 x i32>,
 ; Function Attrs: nounwind
 define <8 x float> @foo1(i8* noalias readonly %arr.ptr, <8 x i32>* noalias readonly %vix.ptr, i8* noalias %t2.ptr) #1 {
 allocas:
-  %vix = load <8 x i32>* %vix.ptr, align 4
-  %t1.ptr = getelementptr i8* %arr.ptr, i8 4
+  %vix = load <8 x i32>, <8 x i32>* %vix.ptr, align 4
+  %t1.ptr = getelementptr i8, i8* %arr.ptr, i8 4
   
   %v1 = tail call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, i8* %arr.ptr, <8 x i32> %vix, <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, i8 1) #2
   store i8 1, i8* %t1.ptr, align 4
@@ -31,8 +31,8 @@ allocas:
 ; Function Attrs: nounwind
 define <8 x float> @foo2(i8* noalias readonly %arr.ptr, <8 x i32>* noalias readonly %vix.ptr, i8* noalias %t2.ptr) #1 {
 allocas:
-  %vix = load <8 x i32>* %vix.ptr, align 4
-  %t1.ptr = getelementptr i8* %arr.ptr, i8 4
+  %vix = load <8 x i32>, <8 x i32>* %vix.ptr, align 4
+  %t1.ptr = getelementptr i8, i8* %arr.ptr, i8 4
   
   %v1 = tail call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, i8* %arr.ptr, <8 x i32> %vix, <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, i8 1) #2
   store i8 1, i8* %t2.ptr, align 4
diff --git a/test/Analysis/BasicAA/store-promote.ll b/test/Analysis/BasicAA/store-promote.ll
index 0db805c3e21e..afe11c2a1488 100644
--- a/test/Analysis/BasicAA/store-promote.ll
+++ b/test/Analysis/BasicAA/store-promote.ll
@@ -10,11 +10,11 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1
 @C = global [2 x i32] [ i32 4, i32 8 ]          ; <[2 x i32]*> [#uses=2]
 
 define i32 @test1(i1 %c) {
-        %Atmp = load i32* @A            ; <i32> [#uses=2]
+        %Atmp = load i32, i32* @A            ; <i32> [#uses=2]
         br label %Loop
 
 Loop:           ; preds = %Loop, %0
-        %ToRemove = load i32* @A                ; <i32> [#uses=1]
+        %ToRemove = load i32, i32* @A                ; <i32> [#uses=1]
         store i32 %Atmp, i32* @B
         br i1 %c, label %Out, label %Loop
 
@@ -24,7 +24,7 @@ Out:            ; preds = %Loop
         
 ; The Loop block should be empty after the load/store are promoted.
 ; CHECK:     @test1
-; CHECK:        load i32* @A
+; CHECK:        load i32, i32* @A
 ; CHECK:      Loop:
 ; CHECK-NEXT:   br i1 %c, label %Out, label %Loop
 ; CHECK:      Out:
@@ -35,11 +35,11 @@ define i32 @test2(i1 %c) {
         br label %Loop
 
 Loop:           ; preds = %Loop, %0
-        %AVal = load i32* @A            ; <i32> [#uses=2]
-        %C0 = getelementptr [2 x i32]* @C, i64 0, i64 0         ; <i32*> [#uses=1]
+        %AVal = load i32, i32* @A            ; <i32> [#uses=2]
+        %C0 = getelementptr [2 x i32], [2 x i32]* @C, i64 0, i64 0         ; <i32*> [#uses=1]
         store i32 %AVal, i32* %C0
-        %BVal = load i32* @B            ; <i32> [#uses=2]
-        %C1 = getelementptr [2 x i32]* @C, i64 0, i64 1         ; <i32*> [#uses=1]
+        %BVal = load i32, i32* @B            ; <i32> [#uses=2]
+        %C1 = getelementptr [2 x i32], [2 x i32]* @C, i64 0, i64 1         ; <i32*> [#uses=1]
         store i32 %BVal, i32* %C1
         br i1 %c, label %Out, label %Loop
 
diff --git a/test/Analysis/BasicAA/struct-geps.ll b/test/Analysis/BasicAA/struct-geps.ll
new file mode 100644
index 000000000000..d63c71a3278b
--- /dev/null
+++ b/test/Analysis/BasicAA/struct-geps.ll
@@ -0,0 +1,164 @@
+; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output 2>&1 | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+%struct = type { i32, i32, i32 }
+
+; CHECK-LABEL: test_simple
+
+; CHECK-DAG: PartialAlias: %struct* %st, i32* %x
+; CHECK-DAG: PartialAlias: %struct* %st, i32* %y
+; CHECK-DAG: PartialAlias: %struct* %st, i32* %z
+
+; CHECK-DAG: NoAlias: i32* %x, i32* %y
+; CHECK-DAG: NoAlias: i32* %x, i32* %z
+; CHECK-DAG: NoAlias: i32* %y, i32* %z
+
+; CHECK-DAG: PartialAlias: %struct* %st, %struct* %y_12
+; CHECK-DAG: PartialAlias: %struct* %y_12, i32* %x
+; CHECK-DAG: PartialAlias: i32* %x, i80* %y_10
+
+; CHECK-DAG: PartialAlias: %struct* %st, i64* %y_8
+; CHECK-DAG: PartialAlias: i32* %z, i64* %y_8
+; CHECK-DAG: NoAlias: i32* %x, i64* %y_8
+
+; CHECK-DAG: MustAlias: %struct* %y_12, i32* %y
+; CHECK-DAG: MustAlias: i32* %y, i64* %y_8
+; CHECK-DAG: MustAlias: i32* %y, i80* %y_10
+
+define void @test_simple(%struct* %st, i64 %i, i64 %j, i64 %k) {
+  %x = getelementptr %struct, %struct* %st, i64 %i, i32 0
+  %y = getelementptr %struct, %struct* %st, i64 %j, i32 1
+  %z = getelementptr %struct, %struct* %st, i64 %k, i32 2
+  %y_12 = bitcast i32* %y to %struct*
+  %y_10 = bitcast i32* %y to i80*
+  %y_8 = bitcast i32* %y to i64*
+  ret void
+}
+
+; CHECK-LABEL: test_in_array
+
+; CHECK-DAG: PartialAlias: [1 x %struct]* %st, i32* %x
+; CHECK-DAG: PartialAlias: [1 x %struct]* %st, i32* %y
+; CHECK-DAG: PartialAlias: [1 x %struct]* %st, i32* %z
+
+; CHECK-DAG: NoAlias: i32* %x, i32* %y
+; CHECK-DAG: NoAlias: i32* %x, i32* %z
+; CHECK-DAG: NoAlias: i32* %y, i32* %z
+
+; CHECK-DAG: PartialAlias: %struct* %y_12, [1 x %struct]* %st
+; CHECK-DAG: PartialAlias: %struct* %y_12, i32* %x
+; CHECK-DAG: PartialAlias: i32* %x, i80* %y_10
+
+; CHECK-DAG: PartialAlias: [1 x %struct]* %st, i64* %y_8
+; CHECK-DAG: PartialAlias: i32* %z, i64* %y_8
+; CHECK-DAG: NoAlias: i32* %x, i64* %y_8
+
+; CHECK-DAG: MustAlias: %struct* %y_12, i32* %y
+; CHECK-DAG: MustAlias: i32* %y, i64* %y_8
+; CHECK-DAG: MustAlias: i32* %y, i80* %y_10
+
+define void @test_in_array([1 x %struct]* %st, i64 %i, i64 %j, i64 %k, i64 %i1, i64 %j1, i64 %k1) {
+  %x = getelementptr [1 x %struct], [1 x %struct]* %st, i64 %i, i64 %i1, i32 0
+  %y = getelementptr [1 x %struct], [1 x %struct]* %st, i64 %j, i64 %j1, i32 1
+  %z = getelementptr [1 x %struct], [1 x %struct]* %st, i64 %k, i64 %k1, i32 2
+  %y_12 = bitcast i32* %y to %struct*
+  %y_10 = bitcast i32* %y to i80*
+  %y_8 = bitcast i32* %y to i64*
+  ret void
+}
+
+; CHECK-LABEL: test_in_3d_array
+
+; CHECK-DAG: PartialAlias: [1 x [1 x [1 x %struct]]]* %st, i32* %x
+; CHECK-DAG: PartialAlias: [1 x [1 x [1 x %struct]]]* %st, i32* %y
+; CHECK-DAG: PartialAlias: [1 x [1 x [1 x %struct]]]* %st, i32* %z
+
+; CHECK-DAG: NoAlias: i32* %x, i32* %y
+; CHECK-DAG: NoAlias: i32* %x, i32* %z
+; CHECK-DAG: NoAlias: i32* %y, i32* %z
+
+; CHECK-DAG: PartialAlias: %struct* %y_12, [1 x [1 x [1 x %struct]]]* %st
+; CHECK-DAG: PartialAlias: %struct* %y_12, i32* %x
+; CHECK-DAG: PartialAlias: i32* %x, i80* %y_10
+
+; CHECK-DAG: PartialAlias: [1 x [1 x [1 x %struct]]]* %st, i64* %y_8
+; CHECK-DAG: PartialAlias: i32* %z, i64* %y_8
+; CHECK-DAG: NoAlias: i32* %x, i64* %y_8
+
+; CHECK-DAG: MustAlias: %struct* %y_12, i32* %y
+; CHECK-DAG: MustAlias: i32* %y, i64* %y_8
+; CHECK-DAG: MustAlias: i32* %y, i80* %y_10
+
+define void @test_in_3d_array([1 x [1 x [1 x %struct]]]* %st, i64 %i, i64 %j, i64 %k, i64 %i1, i64 %j1, i64 %k1, i64 %i2, i64 %j2, i64 %k2, i64 %i3, i64 %j3, i64 %k3) {
+  %x = getelementptr [1 x [1 x [1 x %struct]]], [1 x [1 x [1 x %struct]]]* %st, i64 %i, i64 %i1, i64 %i2, i64 %i3, i32 0
+  %y = getelementptr [1 x [1 x [1 x %struct]]], [1 x [1 x [1 x %struct]]]* %st, i64 %j, i64 %j1, i64 %j2, i64 %j3, i32 1
+  %z = getelementptr [1 x [1 x [1 x %struct]]], [1 x [1 x [1 x %struct]]]* %st, i64 %k, i64 %k1, i64 %k2, i64 %k3, i32 2
+  %y_12 = bitcast i32* %y to %struct*
+  %y_10 = bitcast i32* %y to i80*
+  %y_8 = bitcast i32* %y to i64*
+  ret void
+}
+
+; CHECK-LABEL: test_same_underlying_object_same_indices
+
+; CHECK-DAG: NoAlias: i32* %x, i32* %x2
+; CHECK-DAG: NoAlias: i32* %y, i32* %y2
+; CHECK-DAG: NoAlias: i32* %z, i32* %z2
+
+; CHECK-DAG: PartialAlias: i32* %x, i32* %y2
+; CHECK-DAG: PartialAlias: i32* %x, i32* %z2
+
+; CHECK-DAG: PartialAlias: i32* %x2, i32* %y
+; CHECK-DAG: PartialAlias: i32* %y, i32* %z2
+
+; CHECK-DAG: PartialAlias: i32* %x2, i32* %z
+; CHECK-DAG: PartialAlias: i32* %y2, i32* %z
+
+define void @test_same_underlying_object_same_indices(%struct* %st, i64 %i, i64 %j, i64 %k) {
+  %st2 = getelementptr %struct, %struct* %st, i32 10
+  %x2 = getelementptr %struct, %struct* %st2, i64 %i, i32 0
+  %y2 = getelementptr %struct, %struct* %st2, i64 %j, i32 1
+  %z2 = getelementptr %struct, %struct* %st2, i64 %k, i32 2
+  %x = getelementptr %struct, %struct* %st, i64 %i, i32 0
+  %y = getelementptr %struct, %struct* %st, i64 %j, i32 1
+  %z = getelementptr %struct, %struct* %st, i64 %k, i32 2
+  ret void
+}
+
+; CHECK-LABEL: test_same_underlying_object_different_indices
+
+; CHECK-DAG: PartialAlias: i32* %x, i32* %x2
+; CHECK-DAG: PartialAlias: i32* %y, i32* %y2
+; CHECK-DAG: PartialAlias: i32* %z, i32* %z2
+
+; CHECK-DAG: PartialAlias: i32* %x, i32* %y2
+; CHECK-DAG: PartialAlias: i32* %x, i32* %z2
+
+; CHECK-DAG: PartialAlias: i32* %x2, i32* %y
+; CHECK-DAG: PartialAlias: i32* %y, i32* %z2
+
+; CHECK-DAG: PartialAlias: i32* %x2, i32* %z
+; CHECK-DAG: PartialAlias: i32* %y2, i32* %z
+
+define void @test_same_underlying_object_different_indices(%struct* %st, i64 %i1, i64 %j1, i64 %k1, i64 %i2, i64 %k2, i64 %j2) {
+  %st2 = getelementptr %struct, %struct* %st, i32 10
+  %x2 = getelementptr %struct, %struct* %st2, i64 %i2, i32 0
+  %y2 = getelementptr %struct, %struct* %st2, i64 %j2, i32 1
+  %z2 = getelementptr %struct, %struct* %st2, i64 %k2, i32 2
+  %x = getelementptr %struct, %struct* %st, i64 %i1, i32 0
+  %y = getelementptr %struct, %struct* %st, i64 %j1, i32 1
+  %z = getelementptr %struct, %struct* %st, i64 %k1, i32 2
+  ret void
+}
+
+
+%struct2 = type { [1 x { i32, i32 }], [2 x { i32 }] }
+
+; CHECK-LABEL: test_struct_in_array
+; CHECK-DAG: MustAlias: i32* %x, i32* %y
+define void @test_struct_in_array(%struct2* %st, i64 %i, i64 %j, i64 %k) {
+  %x = getelementptr %struct2, %struct2* %st, i32 0, i32 1, i32 1, i32 0
+  %y = getelementptr %struct2, %struct2* %st, i32 0, i32 0, i32 1, i32 1
+  ret void
+}
diff --git a/test/Analysis/BasicAA/tailcall-modref.ll b/test/Analysis/BasicAA/tailcall-modref.ll
index ebeb28c11310..5857e684bc57 100644
--- a/test/Analysis/BasicAA/tailcall-modref.ll
+++ b/test/Analysis/BasicAA/tailcall-modref.ll
@@ -4,9 +4,9 @@ define i32 @test() {
 ; CHECK: ret i32 0
         %A = alloca i32         ; <i32*> [#uses=3]
         call void @foo( i32* %A )
-        %X = load i32* %A               ; <i32> [#uses=1]
+        %X = load i32, i32* %A               ; <i32> [#uses=1]
         tail call void @bar( )
-        %Y = load i32* %A               ; <i32> [#uses=1]
+        %Y = load i32, i32* %A               ; <i32> [#uses=1]
         %Z = sub i32 %X, %Y             ; <i32> [#uses=1]
         ret i32 %Z
 }
diff --git a/test/Analysis/BasicAA/underlying-value.ll b/test/Analysis/BasicAA/underlying-value.ll
index 0671c8250681..0cfbdb893b30 100644
--- a/test/Analysis/BasicAA/underlying-value.ll
+++ b/test/Analysis/BasicAA/underlying-value.ll
@@ -14,10 +14,10 @@ for.cond2:                                        ; preds = %for.body5, %for.con
   br i1 false, label %for.body5, label %for.cond
 
 for.body5:                                        ; preds = %for.cond2
-  %arrayidx = getelementptr inbounds [2 x i64]* undef, i32 0, i64 0
-  %tmp7 = load i64* %arrayidx, align 8
-  %arrayidx9 = getelementptr inbounds [2 x i64]* undef, i32 0, i64 undef
-  %tmp10 = load i64* %arrayidx9, align 8
+  %arrayidx = getelementptr inbounds [2 x i64], [2 x i64]* undef, i32 0, i64 0
+  %tmp7 = load i64, i64* %arrayidx, align 8
+  %arrayidx9 = getelementptr inbounds [2 x i64], [2 x i64]* undef, i32 0, i64 undef
+  %tmp10 = load i64, i64* %arrayidx9, align 8
   br label %for.cond2
 
 for.end22:                                        ; preds = %for.cond
diff --git a/test/Analysis/BasicAA/unreachable-block.ll b/test/Analysis/BasicAA/unreachable-block.ll
index 1ca1e66f8947..551d18e3e0fb 100644
--- a/test/Analysis/BasicAA/unreachable-block.ll
+++ b/test/Analysis/BasicAA/unreachable-block.ll
@@ -11,6 +11,6 @@ bb:
   %t = select i1 undef, i32* %t, i32* undef
   %p = select i1 undef, i32* %p, i32* %p
   %q = select i1 undef, i32* undef, i32* %p
-  %a = getelementptr i8* %a, i32 0
+  %a = getelementptr i8, i8* %a, i32 0
   unreachable
 }
diff --git a/test/Analysis/BasicAA/zext.ll b/test/Analysis/BasicAA/zext.ll
index b59d16cc5f51..ed3565640251 100644
--- a/test/Analysis/BasicAA/zext.ll
+++ b/test/Analysis/BasicAA/zext.ll
@@ -7,10 +7,10 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define void @test_with_zext() {
   %1 = tail call i8* @malloc(i64 120)
-  %a = getelementptr inbounds i8* %1, i64 8
-  %2 = getelementptr inbounds i8* %1, i64 16
+  %a = getelementptr inbounds i8, i8* %1, i64 8
+  %2 = getelementptr inbounds i8, i8* %1, i64 16
   %3 = zext i32 3 to i64
-  %b = getelementptr inbounds i8* %2, i64 %3
+  %b = getelementptr inbounds i8, i8* %2, i64 %3
   ret void
 }
 
@@ -19,10 +19,10 @@ define void @test_with_zext() {
 
 define void @test_with_lshr(i64 %i) {
   %1 = tail call i8* @malloc(i64 120)
-  %a = getelementptr inbounds i8* %1, i64 8
-  %2 = getelementptr inbounds i8* %1, i64 16
+  %a = getelementptr inbounds i8, i8* %1, i64 8
+  %2 = getelementptr inbounds i8, i8* %1, i64 16
   %3 = lshr i64 %i, 2
-  %b = getelementptr inbounds i8* %2, i64 %3
+  %b = getelementptr inbounds i8, i8* %2, i64 %3
   ret void
 }
 
@@ -34,10 +34,10 @@ define void @test_with_a_loop(i8* %mem) {
 
 for.loop:
   %i = phi i32 [ 0, %0 ], [ %i.plus1, %for.loop ]
-  %a = getelementptr inbounds i8* %mem, i64 8
-  %a.plus1 = getelementptr inbounds i8* %mem, i64 16
+  %a = getelementptr inbounds i8, i8* %mem, i64 8
+  %a.plus1 = getelementptr inbounds i8, i8* %mem, i64 16
   %i.64 = zext i32 %i to i64
-  %b = getelementptr inbounds i8* %a.plus1, i64 %i.64
+  %b = getelementptr inbounds i8, i8* %a.plus1, i64 %i.64
   %i.plus1 = add nuw nsw i32 %i, 1
   %cmp = icmp eq i32 %i.plus1, 10
   br i1 %cmp, label %for.loop.exit, label %for.loop
@@ -55,12 +55,12 @@ define void @test_with_varying_base_pointer_in_loop(i8* %mem.orig) {
 for.loop:
   %mem = phi i8* [ %mem.orig, %0 ], [ %mem.plus1, %for.loop ]
   %i = phi i32 [ 0, %0 ], [ %i.plus1, %for.loop ]
-  %a = getelementptr inbounds i8* %mem, i64 8
-  %a.plus1 = getelementptr inbounds i8* %mem, i64 16
+  %a = getelementptr inbounds i8, i8* %mem, i64 8
+  %a.plus1 = getelementptr inbounds i8, i8* %mem, i64 16
   %i.64 = zext i32 %i to i64
-  %b = getelementptr inbounds i8* %a.plus1, i64 %i.64
+  %b = getelementptr inbounds i8, i8* %a.plus1, i64 %i.64
   %i.plus1 = add nuw nsw i32 %i, 1
-  %mem.plus1 = getelementptr inbounds i8* %mem, i64 8
+  %mem.plus1 = getelementptr inbounds i8, i8* %mem, i64 8
   %cmp = icmp eq i32 %i.plus1, 10
   br i1 %cmp, label %for.loop.exit, label %for.loop
 
@@ -74,10 +74,10 @@ for.loop.exit:
 define void @test_sign_extension(i32 %p) {
   %1 = tail call i8* @malloc(i64 120)
   %p.64 = zext i32 %p to i64
-  %a = getelementptr inbounds i8* %1, i64 %p.64
+  %a = getelementptr inbounds i8, i8* %1, i64 %p.64
   %p.minus1 = add i32 %p, -1
   %p.minus1.64 = zext i32 %p.minus1 to i64
-  %b.i8 = getelementptr inbounds i8* %1, i64 %p.minus1.64
+  %b.i8 = getelementptr inbounds i8, i8* %1, i64 %p.minus1.64
   %b.i64 = bitcast i8* %b.i8 to i64*
   ret void
 }
@@ -91,13 +91,13 @@ define void @test_fe_tools([8 x i32]* %values) {
 for.loop:
   %i = phi i32 [ 0, %reorder ], [ %i.next, %for.loop ]
   %idxprom = zext i32 %i to i64
-  %b = getelementptr inbounds [8 x i32]* %values, i64 0, i64 %idxprom
+  %b = getelementptr inbounds [8 x i32], [8 x i32]* %values, i64 0, i64 %idxprom
   %i.next = add nuw nsw i32 %i, 1
   %1 = icmp eq i32 %i.next, 10
   br i1 %1, label %for.loop.exit, label %for.loop
 
 reorder:
-  %a = getelementptr inbounds [8 x i32]* %values, i64 0, i64 1
+  %a = getelementptr inbounds [8 x i32], [8 x i32]* %values, i64 0, i64 1
   br label %for.loop
 
 for.loop.exit:
@@ -112,7 +112,7 @@ for.loop.exit:
 
 define void @test_spec2006() {
   %h = alloca [1 x [2 x i32*]], align 16
-  %d.val = load i32* @d, align 4
+  %d.val = load i32, i32* @d, align 4
   %d.promoted = sext i32 %d.val to i64
   %1 = icmp slt i32 %d.val, 2
   br i1 %1, label %.lr.ph, label %3
@@ -123,13 +123,13 @@ define void @test_spec2006() {
 ; <label>:2                                       ; preds = %.lr.ph, %2
   %i = phi i32 [ %d.val, %.lr.ph ], [ %i.plus1, %2 ]
   %i.promoted = sext i32 %i to i64
-  %x = getelementptr inbounds [1 x [2 x i32*]]* %h, i64 0, i64 %d.promoted, i64 %i.promoted
+  %x = getelementptr inbounds [1 x [2 x i32*]], [1 x [2 x i32*]]* %h, i64 0, i64 %d.promoted, i64 %i.promoted
   %i.plus1 = add nsw i32 %i, 1
   %cmp = icmp slt i32 %i.plus1, 2
   br i1 %cmp, label %2, label %3
 
 ; <label>:3                                      ; preds = %._crit_edge, %0
-  %y = getelementptr inbounds [1 x [2 x i32*]]* %h, i64 0, i64 0, i64 1
+  %y = getelementptr inbounds [1 x [2 x i32*]], [1 x [2 x i32*]]* %h, i64 0, i64 0, i64 1
   ret void
 }
 
@@ -138,8 +138,8 @@ define void @test_spec2006() {
 
 define void @test_modulo_analysis_easy_case(i64 %i) {
   %h = alloca [1 x [2 x i32*]], align 16
-  %x = getelementptr inbounds [1 x [2 x i32*]]* %h, i64 0, i64 %i, i64 0
-  %y = getelementptr inbounds [1 x [2 x i32*]]* %h, i64 0, i64 0, i64 1
+  %x = getelementptr inbounds [1 x [2 x i32*]], [1 x [2 x i32*]]* %h, i64 0, i64 %i, i64 0
+  %y = getelementptr inbounds [1 x [2 x i32*]], [1 x [2 x i32*]]* %h, i64 0, i64 0, i64 1
   ret void
 }
 
@@ -153,8 +153,8 @@ define void @test_modulo_analysis_in_loop() {
 for.loop:
   %i = phi i32 [ 0, %0 ], [ %i.plus1, %for.loop ]
   %i.promoted = sext i32 %i to i64
-  %x = getelementptr inbounds [1 x [2 x i32*]]* %h, i64 0, i64 %i.promoted, i64 0
-  %y = getelementptr inbounds [1 x [2 x i32*]]* %h, i64 0, i64 0, i64 1
+  %x = getelementptr inbounds [1 x [2 x i32*]], [1 x [2 x i32*]]* %h, i64 0, i64 %i.promoted, i64 0
+  %y = getelementptr inbounds [1 x [2 x i32*]], [1 x [2 x i32*]]* %h, i64 0, i64 0, i64 1
   %i.plus1 = add nsw i32 %i, 1
   %cmp = icmp slt i32 %i.plus1, 2
   br i1 %cmp, label %for.loop, label %for.loop.exit
@@ -168,15 +168,15 @@ for.loop.exit:
 
 define void @test_modulo_analysis_with_global() {
   %h = alloca [1 x [2 x i32*]], align 16
-  %b = load i32* @b, align 4
+  %b = load i32, i32* @b, align 4
   %b.promoted = sext i32 %b to i64
   br label %for.loop
 
 for.loop:
   %i = phi i32 [ 0, %0 ], [ %i.plus1, %for.loop ]
   %i.promoted = sext i32 %i to i64
-  %x = getelementptr inbounds [1 x [2 x i32*]]* %h, i64 0, i64 %i.promoted, i64 %b.promoted
-  %y = getelementptr inbounds [1 x [2 x i32*]]* %h, i64 0, i64 0, i64 1
+  %x = getelementptr inbounds [1 x [2 x i32*]], [1 x [2 x i32*]]* %h, i64 0, i64 %i.promoted, i64 %b.promoted
+  %y = getelementptr inbounds [1 x [2 x i32*]], [1 x [2 x i32*]]* %h, i64 0, i64 0, i64 1
   %i.plus1 = add nsw i32 %i, 1
   %cmp = icmp slt i32 %i.plus1, 2
   br i1 %cmp, label %for.loop, label %for.loop.exit
@@ -188,10 +188,10 @@ for.loop.exit:
 ; CHECK-LABEL: test_const_eval
 ; CHECK: NoAlias: i8* %a, i8* %b
 define void @test_const_eval(i8* %ptr, i64 %offset) {
-  %a = getelementptr inbounds i8* %ptr, i64 %offset
-  %a.dup = getelementptr inbounds i8* %ptr, i64 %offset
+  %a = getelementptr inbounds i8, i8* %ptr, i64 %offset
+  %a.dup = getelementptr inbounds i8, i8* %ptr, i64 %offset
   %three = zext i32 3 to i64
-  %b = getelementptr inbounds i8* %a.dup, i64 %three
+  %b = getelementptr inbounds i8, i8* %a.dup, i64 %three
   ret void
 }
 
@@ -200,8 +200,8 @@ define void @test_const_eval(i8* %ptr, i64 %offset) {
 define void @test_const_eval_scaled(i8* %ptr) {
   %three = zext i32 3 to i64
   %six = mul i64 %three, 2
-  %a = getelementptr inbounds i8* %ptr, i64 %six
-  %b = getelementptr inbounds i8* %ptr, i64 6
+  %a = getelementptr inbounds i8, i8* %ptr, i64 %six
+  %b = getelementptr inbounds i8, i8* %ptr, i64 6
   ret void
 }
 
diff --git a/test/Analysis/BlockFrequencyInfo/bad_input.ll b/test/Analysis/BlockFrequencyInfo/bad_input.ll
index da62dca67a8b..e5b1f500e1e6 100644
--- a/test/Analysis/BlockFrequencyInfo/bad_input.ll
+++ b/test/Analysis/BlockFrequencyInfo/bad_input.ll
@@ -32,7 +32,8 @@ define void @infinite_loop(i1 %x) {
 entry:
   br i1 %x, label %for.body, label %for.end, !prof !1
 
-; Check that the loop scale maxes out at 4096, giving 2048 here.
+; Check that the infinite loop is arbitrarily scaled to max out at 4096,
+; giving 2048 here.
 ; CHECK-NEXT: for.body: float = 2048.0,
 for.body:
   %i = phi i32 [ 0, %entry ], [ %inc, %for.body ]
diff --git a/test/Analysis/BlockFrequencyInfo/basic.ll b/test/Analysis/BlockFrequencyInfo/basic.ll
index 1c24176d6153..728adf007f42 100644
--- a/test/Analysis/BlockFrequencyInfo/basic.ll
+++ b/test/Analysis/BlockFrequencyInfo/basic.ll
@@ -12,8 +12,8 @@ entry:
 body:
   %iv = phi i32 [ 0, %entry ], [ %next, %body ]
   %base = phi i32 [ 0, %entry ], [ %sum, %body ]
-  %arrayidx = getelementptr inbounds i32* %a, i32 %iv
-  %0 = load i32* %arrayidx
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %iv
+  %0 = load i32, i32* %arrayidx
   %sum = add nsw i32 %0, %base
   %next = add i32 %iv, 1
   %exitcond = icmp eq i32 %next, %i
diff --git a/test/Analysis/BlockFrequencyInfo/loops_with_profile_info.ll b/test/Analysis/BlockFrequencyInfo/loops_with_profile_info.ll
new file mode 100644
index 000000000000..534c4ad0e94f
--- /dev/null
+++ b/test/Analysis/BlockFrequencyInfo/loops_with_profile_info.ll
@@ -0,0 +1,204 @@
+; RUN: opt < %s -analyze -block-freq | FileCheck %s
+
+; This code contains three loops. One is triple-nested, the
+; second is double nested and the third is a single loop. At
+; runtime, all three loops execute 1,000,000 times each. We use to
+; give different frequencies to each of the loops because loop
+; scales were limited to no more than 4,096.
+;
+; This was penalizing the hotness of the second and third loops
+; because BFI was reducing the loop scale for for.cond16 and
+; for.cond26 to a max of 4,096.
+;
+; Without this restriction, all loops are now correctly given the same
+; frequency values.
+;
+; Original C code:
+;
+;
+; int g;
+; __attribute__((noinline)) void bar() {
+;  g++;
+; }
+;
+; extern int printf(const char*, ...);
+;
+; int main()
+; {
+;   int i, j, k;
+;
+;   g = 0;
+;   for (i = 0; i < 100; i++)
+;     for (j = 0; j < 100; j++)
+;        for (k = 0; k < 100; k++)
+;            bar();
+;
+;   printf ("g = %d\n", g);
+;   g = 0;
+;
+;   for (i = 0; i < 100; i++)
+;     for (j = 0; j < 10000; j++)
+;         bar();
+;
+;   printf ("g = %d\n", g);
+;   g = 0;
+;
+;
+;   for (i = 0; i < 1000000; i++)
+;     bar();
+;
+;   printf ("g = %d\n", g);
+;   g = 0;
+; }
+
+@g = common global i32 0, align 4
+@.str = private unnamed_addr constant [8 x i8] c"g = %d\0A\00", align 1
+
+declare void @bar()
+declare i32 @printf(i8*, ...)
+
+; CHECK: Printing analysis {{.*}} for function 'main':
+; CHECK-NEXT: block-frequency-info: main
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %i = alloca i32, align 4
+  %j = alloca i32, align 4
+  %k = alloca i32, align 4
+  store i32 0, i32* %retval
+  store i32 0, i32* @g, align 4
+  store i32 0, i32* %i, align 4
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc10, %entry
+  %0 = load i32, i32* %i, align 4
+  %cmp = icmp slt i32 %0, 100
+  br i1 %cmp, label %for.body, label %for.end12, !prof !1
+
+for.body:                                         ; preds = %for.cond
+  store i32 0, i32* %j, align 4
+  br label %for.cond1
+
+for.cond1:                                        ; preds = %for.inc7, %for.body
+  %1 = load i32, i32* %j, align 4
+  %cmp2 = icmp slt i32 %1, 100
+  br i1 %cmp2, label %for.body3, label %for.end9, !prof !2
+
+for.body3:                                        ; preds = %for.cond1
+  store i32 0, i32* %k, align 4
+  br label %for.cond4
+
+for.cond4:                                        ; preds = %for.inc, %for.body3
+  %2 = load i32, i32* %k, align 4
+  %cmp5 = icmp slt i32 %2, 100
+  br i1 %cmp5, label %for.body6, label %for.end, !prof !3
+
+; CHECK: - for.body6: float = 500000.5, int = 4000003
+for.body6:                                        ; preds = %for.cond4
+  call void @bar()
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body6
+  %3 = load i32, i32* %k, align 4
+  %inc = add nsw i32 %3, 1
+  store i32 %inc, i32* %k, align 4
+  br label %for.cond4
+
+for.end:                                          ; preds = %for.cond4
+  br label %for.inc7
+
+for.inc7:                                         ; preds = %for.end
+  %4 = load i32, i32* %j, align 4
+  %inc8 = add nsw i32 %4, 1
+  store i32 %inc8, i32* %j, align 4
+  br label %for.cond1
+
+for.end9:                                         ; preds = %for.cond1
+  br label %for.inc10
+
+for.inc10:                                        ; preds = %for.end9
+  %5 = load i32, i32* %i, align 4
+  %inc11 = add nsw i32 %5, 1
+  store i32 %inc11, i32* %i, align 4
+  br label %for.cond
+
+for.end12:                                        ; preds = %for.cond
+  %6 = load i32, i32* @g, align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0), i32 %6)
+  store i32 0, i32* @g, align 4
+  store i32 0, i32* %i, align 4
+  br label %for.cond13
+
+for.cond13:                                       ; preds = %for.inc22, %for.end12
+  %7 = load i32, i32* %i, align 4
+  %cmp14 = icmp slt i32 %7, 100
+  br i1 %cmp14, label %for.body15, label %for.end24, !prof !1
+
+for.body15:                                       ; preds = %for.cond13
+  store i32 0, i32* %j, align 4
+  br label %for.cond16
+
+for.cond16:                                       ; preds = %for.inc19, %for.body15
+  %8 = load i32, i32* %j, align 4
+  %cmp17 = icmp slt i32 %8, 10000
+  br i1 %cmp17, label %for.body18, label %for.end21, !prof !4
+
+; CHECK: - for.body18: float = 500000.5, int = 4000003
+for.body18:                                       ; preds = %for.cond16
+  call void @bar()
+  br label %for.inc19
+
+for.inc19:                                        ; preds = %for.body18
+  %9 = load i32, i32* %j, align 4
+  %inc20 = add nsw i32 %9, 1
+  store i32 %inc20, i32* %j, align 4
+  br label %for.cond16
+
+for.end21:                                        ; preds = %for.cond16
+  br label %for.inc22
+
+for.inc22:                                        ; preds = %for.end21
+  %10 = load i32, i32* %i, align 4
+  %inc23 = add nsw i32 %10, 1
+  store i32 %inc23, i32* %i, align 4
+  br label %for.cond13
+
+for.end24:                                        ; preds = %for.cond13
+  %11 = load i32, i32* @g, align 4
+  %call25 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0), i32 %11)
+  store i32 0, i32* @g, align 4
+  store i32 0, i32* %i, align 4
+  br label %for.cond26
+
+for.cond26:                                       ; preds = %for.inc29, %for.end24
+  %12 = load i32, i32* %i, align 4
+  %cmp27 = icmp slt i32 %12, 1000000
+  br i1 %cmp27, label %for.body28, label %for.end31, !prof !5
+
+; CHECK: - for.body28: float = 500000.5, int = 4000003
+for.body28:                                       ; preds = %for.cond26
+  call void @bar()
+  br label %for.inc29
+
+for.inc29:                                        ; preds = %for.body28
+  %13 = load i32, i32* %i, align 4
+  %inc30 = add nsw i32 %13, 1
+  store i32 %inc30, i32* %i, align 4
+  br label %for.cond26
+
+for.end31:                                        ; preds = %for.cond26
+  %14 = load i32, i32* @g, align 4
+  %call32 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0), i32 %14)
+  store i32 0, i32* @g, align 4
+  %15 = load i32, i32* %retval
+  ret i32 %15
+}
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 232635) (llvm/trunk 232636)"}
+!1 = !{!"branch_weights", i32 101, i32 2}
+!2 = !{!"branch_weights", i32 10001, i32 101}
+!3 = !{!"branch_weights", i32 1000001, i32 10001}
+!4 = !{!"branch_weights", i32 1000001, i32 101}
+!5 = !{!"branch_weights", i32 1000001, i32 2}
diff --git a/test/Analysis/BranchProbabilityInfo/basic.ll b/test/Analysis/BranchProbabilityInfo/basic.ll
index 5915ed152b06..2c9c15618682 100644
--- a/test/Analysis/BranchProbabilityInfo/basic.ll
+++ b/test/Analysis/BranchProbabilityInfo/basic.ll
@@ -9,8 +9,8 @@ entry:
 body:
   %iv = phi i32 [ 0, %entry ], [ %next, %body ]
   %base = phi i32 [ 0, %entry ], [ %sum, %body ]
-  %arrayidx = getelementptr inbounds i32* %a, i32 %iv
-  %0 = load i32* %arrayidx
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %iv
+  %0 = load i32, i32* %arrayidx
   %sum = add nsw i32 %0, %base
   %next = add i32 %iv, 1
   %exitcond = icmp eq i32 %next, %i
@@ -153,8 +153,8 @@ define i32 @test_cold_call_sites(i32* %a) {
 ; CHECK: edge entry -> else probability is 64 / 68 = 94.1176% [HOT edge]
 
 entry:
-  %gep1 = getelementptr i32* %a, i32 1
-  %val1 = load i32* %gep1
+  %gep1 = getelementptr i32, i32* %a, i32 1
+  %val1 = load i32, i32* %gep1
   %cond1 = icmp ugt i32 %val1, 1
   br i1 %cond1, label %then, label %else
 
@@ -164,8 +164,8 @@ then:
   br label %exit
 
 else:
-  %gep2 = getelementptr i32* %a, i32 2
-  %val2 = load i32* %gep2
+  %gep2 = getelementptr i32, i32* %a, i32 2
+  %val2 = load i32, i32* %gep2
   %val3 = call i32 @regular_function(i32 %val2)
   br label %exit
 
@@ -212,3 +212,31 @@ exit:
   ret i32 %result
 }
 
+define i32 @zero3(i32 %i, i32 %a, i32 %b) {
+; CHECK: Printing analysis {{.*}} for function 'zero3'
+entry:
+; AND'ing with a single bit bitmask essentially leads to a bool comparison,
+; meaning we don't have probability information.
+  %and = and i32 %i, 2
+  %tobool = icmp eq i32 %and, 0
+  br i1 %tobool, label %then, label %else
+; CHECK: edge entry -> then probability is 16 / 32
+; CHECK: edge entry -> else probability is 16 / 32
+
+then:
+; AND'ing with other bitmask might be something else, so we still assume the
+; usual probabilities.
+  %and2 = and i32 %i, 5
+  %tobool2 = icmp eq i32 %and2, 0
+  br i1 %tobool2, label %else, label %exit
+; CHECK: edge then -> else probability is 12 / 32
+; CHECK: edge then -> exit probability is 20 / 32
+
+else:
+  br label %exit
+
+exit:
+  %result = phi i32 [ %a, %then ], [ %b, %else ]
+  ret i32 %result
+}
+
diff --git a/test/Analysis/BranchProbabilityInfo/loop.ll b/test/Analysis/BranchProbabilityInfo/loop.ll
index 40f1111c6b03..e792790f84f8 100644
--- a/test/Analysis/BranchProbabilityInfo/loop.ll
+++ b/test/Analysis/BranchProbabilityInfo/loop.ll
@@ -88,7 +88,7 @@ entry:
 do.body:
   %i.0 = phi i32 [ 0, %entry ], [ %inc4, %if.end ]
   call void @g1()
-  %0 = load i32* %c, align 4
+  %0 = load i32, i32* %c, align 4
   %cmp = icmp slt i32 %0, 42
   br i1 %cmp, label %do.body1, label %if.end
 ; CHECK: edge do.body -> do.body1 probability is 16 / 32 = 50%
@@ -124,7 +124,7 @@ entry:
 do.body:
   %i.0 = phi i32 [ 0, %entry ], [ %inc4, %do.end ]
   call void @g1()
-  %0 = load i32* %c, align 4
+  %0 = load i32, i32* %c, align 4
   %cmp = icmp slt i32 %0, 42
   br i1 %cmp, label %return, label %do.body1
 ; CHECK: edge do.body -> return probability is 4 / 128
@@ -169,7 +169,7 @@ do.body:
 
 do.body1:
   %j.0 = phi i32 [ 0, %do.body ], [ %inc, %if.end ]
-  %0 = load i32* %c, align 4
+  %0 = load i32, i32* %c, align 4
   %cmp = icmp slt i32 %0, 42
   br i1 %cmp, label %return, label %if.end
 ; CHECK: edge do.body1 -> return probability is 4 / 128
@@ -214,7 +214,7 @@ do.body:
 do.body1:
   %j.0 = phi i32 [ 0, %do.body ], [ %inc, %do.cond ]
   call void @g2()
-  %0 = load i32* %c, align 4
+  %0 = load i32, i32* %c, align 4
   %cmp = icmp slt i32 %0, 42
   br i1 %cmp, label %return, label %do.cond
 ; CHECK: edge do.body1 -> return probability is 4 / 128
@@ -258,7 +258,7 @@ for.body.lr.ph:
 
 for.body:
   %i.011 = phi i32 [ 0, %for.body.lr.ph ], [ %inc6, %for.inc5 ]
-  %0 = load i32* %c, align 4
+  %0 = load i32, i32* %c, align 4
   %cmp1 = icmp eq i32 %0, %i.011
   br i1 %cmp1, label %for.inc5, label %if.end
 ; CHECK: edge for.body -> for.inc5 probability is 16 / 32 = 50%
@@ -305,8 +305,8 @@ entry:
 
 for.body.lr.ph:
   %cmp216 = icmp sgt i32 %b, 0
-  %arrayidx5 = getelementptr inbounds i32* %c, i64 1
-  %arrayidx9 = getelementptr inbounds i32* %c, i64 2
+  %arrayidx5 = getelementptr inbounds i32, i32* %c, i64 1
+  %arrayidx9 = getelementptr inbounds i32, i32* %c, i64 2
   br label %for.body
 ; CHECK: edge for.body.lr.ph -> for.body probability is 16 / 16 = 100%
 
@@ -319,21 +319,21 @@ for.body:
 
 for.body3:
   %j.017 = phi i32 [ 0, %for.body ], [ %inc, %for.inc ]
-  %0 = load i32* %c, align 4
+  %0 = load i32, i32* %c, align 4
   %cmp4 = icmp eq i32 %0, %j.017
   br i1 %cmp4, label %for.inc, label %if.end
 ; CHECK: edge for.body3 -> for.inc probability is 16 / 32 = 50%
 ; CHECK: edge for.body3 -> if.end probability is 16 / 32 = 50%
 
 if.end:
-  %1 = load i32* %arrayidx5, align 4
+  %1 = load i32, i32* %arrayidx5, align 4
   %cmp6 = icmp eq i32 %1, %j.017
   br i1 %cmp6, label %for.inc, label %if.end8
 ; CHECK: edge if.end -> for.inc probability is 16 / 32 = 50%
 ; CHECK: edge if.end -> if.end8 probability is 16 / 32 = 50%
 
 if.end8:
-  %2 = load i32* %arrayidx9, align 4
+  %2 = load i32, i32* %arrayidx9, align 4
   %cmp10 = icmp eq i32 %2, %j.017
   br i1 %cmp10, label %for.inc, label %if.end12
 ; CHECK: edge if.end8 -> for.inc probability is 16 / 32 = 50%
diff --git a/test/Analysis/BranchProbabilityInfo/pr18705.ll b/test/Analysis/BranchProbabilityInfo/pr18705.ll
index 9f239b46058d..aff08a63d506 100644
--- a/test/Analysis/BranchProbabilityInfo/pr18705.ll
+++ b/test/Analysis/BranchProbabilityInfo/pr18705.ll
@@ -22,23 +22,23 @@ while.body:
   %d.addr.010 = phi i32* [ %d, %while.body.lr.ph ], [ %incdec.ptr4, %if.end ]
   %c.addr.09 = phi i32* [ %c, %while.body.lr.ph ], [ %c.addr.1, %if.end ]
   %indvars.iv.next = add nsw i64 %indvars.iv, -1
-  %arrayidx = getelementptr inbounds float* %f0, i64 %indvars.iv.next
-  %1 = load float* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds float* %f1, i64 %indvars.iv.next
-  %2 = load float* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds float, float* %f0, i64 %indvars.iv.next
+  %1 = load float, float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %f1, i64 %indvars.iv.next
+  %2 = load float, float* %arrayidx2, align 4
   %cmp = fcmp une float %1, %2
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:
-  %incdec.ptr = getelementptr inbounds i32* %b.addr.011, i64 1
-  %3 = load i32* %b.addr.011, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %b.addr.011, i64 1
+  %3 = load i32, i32* %b.addr.011, align 4
   %add = add nsw i32 %3, 12
   store i32 %add, i32* %b.addr.011, align 4
   br label %if.end
 
 if.else:
-  %incdec.ptr3 = getelementptr inbounds i32* %c.addr.09, i64 1
-  %4 = load i32* %c.addr.09, align 4
+  %incdec.ptr3 = getelementptr inbounds i32, i32* %c.addr.09, i64 1
+  %4 = load i32, i32* %c.addr.09, align 4
   %sub = add nsw i32 %4, -13
   store i32 %sub, i32* %c.addr.09, align 4
   br label %if.end
@@ -46,7 +46,7 @@ if.else:
 if.end:
   %c.addr.1 = phi i32* [ %c.addr.09, %if.then ], [ %incdec.ptr3, %if.else ]
   %b.addr.1 = phi i32* [ %incdec.ptr, %if.then ], [ %b.addr.011, %if.else ]
-  %incdec.ptr4 = getelementptr inbounds i32* %d.addr.010, i64 1
+  %incdec.ptr4 = getelementptr inbounds i32, i32* %d.addr.010, i64 1
   store i32 14, i32* %d.addr.010, align 4
   %5 = trunc i64 %indvars.iv.next to i32
   %tobool = icmp eq i32 %5, 0
diff --git a/test/Analysis/BranchProbabilityInfo/pr22718.ll b/test/Analysis/BranchProbabilityInfo/pr22718.ll
new file mode 100644
index 000000000000..0de4d643c9c9
--- /dev/null
+++ b/test/Analysis/BranchProbabilityInfo/pr22718.ll
@@ -0,0 +1,84 @@
+; RUN: opt < %s -analyze -branch-prob | FileCheck %s
+
+; In this test, the else clause is taken about 90% of the time. This was not
+; reflected in the probability computation because the weight is larger than
+; the branch weight cap (about 2 billion).
+;
+; CHECK: edge for.body -> if.then probability is 216661881 / 2166666667 = 9.9
+; CHECK: edge for.body -> if.else probability is 1950004786 / 2166666667 = 90.0
+
+@y = common global i64 0, align 8
+@x = common global i64 0, align 8
+@.str = private unnamed_addr constant [17 x i8] c"x = %lu\0Ay = %lu\0A\00", align 1
+
+; Function Attrs: inlinehint nounwind uwtable
+define i32 @main() #0 {
+entry:
+  %retval = alloca i32, align 4
+  %i = alloca i64, align 8
+  store i32 0, i32* %retval
+  store i64 0, i64* @y, align 8
+  store i64 0, i64* @x, align 8
+  call void @srand(i32 422304) #3
+  store i64 0, i64* %i, align 8
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %entry
+  %0 = load i64, i64* %i, align 8
+  %cmp = icmp ult i64 %0, 13000000000
+  br i1 %cmp, label %for.body, label %for.end, !prof !1
+
+for.body:                                         ; preds = %for.cond
+  %call = call i32 @rand() #3
+  %conv = sitofp i32 %call to double
+  %mul = fmul double %conv, 1.000000e+02
+  %div = fdiv double %mul, 0x41E0000000000000
+  %cmp1 = fcmp ogt double %div, 9.000000e+01
+  br i1 %cmp1, label %if.then, label %if.else, !prof !2
+
+if.then:                                          ; preds = %for.body
+  %1 = load i64, i64* @x, align 8
+  %inc = add i64 %1, 1
+  store i64 %inc, i64* @x, align 8
+  br label %if.end
+
+if.else:                                          ; preds = %for.body
+  %2 = load i64, i64* @y, align 8
+  %inc3 = add i64 %2, 1
+  store i64 %inc3, i64* @y, align 8
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  br label %for.inc
+
+for.inc:                                          ; preds = %if.end
+  %3 = load i64, i64* %i, align 8
+  %inc4 = add i64 %3, 1
+  store i64 %inc4, i64* %i, align 8
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  %4 = load i64, i64* @x, align 8
+  %5 = load i64, i64* @y, align 8
+  %call5 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str, i32 0, i32 0), i64 %4, i64 %5)
+  ret i32 0
+}
+
+; Function Attrs: nounwind
+declare void @srand(i32) #1
+
+; Function Attrs: nounwind
+declare i32 @rand() #1
+
+declare i32 @printf(i8*, ...) #2
+
+attributes #0 = { inlinehint nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 236218) (llvm/trunk 236235)"}
+!1 = !{!"branch_weights", i32 -1044967295, i32 1}
+!2 = !{!"branch_weights", i32 433323762, i32 -394957723}
diff --git a/test/Analysis/CFLAliasAnalysis/asm-global-bugfix.ll b/test/Analysis/CFLAliasAnalysis/asm-global-bugfix.ll
new file mode 100644
index 000000000000..ec2de54e3eee
--- /dev/null
+++ b/test/Analysis/CFLAliasAnalysis/asm-global-bugfix.ll
@@ -0,0 +1,16 @@
+; Test case for a bug where we would crash when we were requested to report
+; whether two values that didn't belong to a function (i.e. two globals, etc)
+; aliased.
+
+; RUN: opt < %s -cfl-aa -aa-eval -print-may-aliases -disable-output 2>&1 | FileCheck %s
+
+@G = private unnamed_addr constant [1 x i8] c"\00", align 1
+
+; CHECK: Function: test_no_crash
+; CHECK: 0 no alias responses
+define void @test_no_crash() #0 {
+entry:
+  call i8* asm "nop", "=r,r"(
+       i8* getelementptr inbounds ([1 x i8], [1 x i8]* @G, i64 0, i64 0))
+  ret void
+}
diff --git a/test/Analysis/CFLAliasAnalysis/branch-alias.ll b/test/Analysis/CFLAliasAnalysis/branch-alias.ll
new file mode 100644
index 000000000000..8307462928e7
--- /dev/null
+++ b/test/Analysis/CFLAliasAnalysis/branch-alias.ll
@@ -0,0 +1,73 @@
+; Makes sure that we give up on some pathological cases with inttoptr/ptrtoint
+;
+; @ptr_test was generated from the following C code:
+;  void ptr_test() {
+;    int* A;
+;    unsigned long RefCopy = 0;
+;    for (int i = 0; i < 8*sizeof(&A); ++i) {
+;      if ((unsigned long)&A & (1UL << i))
+;        RefCopy |= 1UL << i;
+;    }
+;
+;    int** AliasA1 = (int**)RefCopy;
+;    int* ShouldAliasA = *AliasA1;
+;  }
+
+; RUN: opt < %s -cfl-aa -aa-eval -print-may-aliases -disable-output 2>&1 | FileCheck %s
+
+; CHECK: Function: ptr_test
+define void @ptr_test() #0 {
+  ; CHECK: MayAlias: i32** %A, i32** %ShouldAliasA
+  ; CHECK-NOT: %AliasA1
+entry:
+  %A = alloca i32*, align 8
+  %RefCopy = alloca i64, align 8
+  %i = alloca i32, align 4
+  %AliasA1 = alloca i32**, align 8
+  %ShouldAliasA = alloca i32*, align 8
+  store i64 0, i64* %RefCopy, align 8
+  store i32 0, i32* %i, align 4
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %entry
+  %0 = load i32, i32* %i, align 4
+  %conv = sext i32 %0 to i64
+  %cmp = icmp ult i64 %conv, 64
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %1 = ptrtoint i32** %A to i64
+  %2 = load i32, i32* %i, align 4
+  %sh_prom = zext i32 %2 to i64
+  %shl = shl i64 1, %sh_prom
+  %and = and i64 %1, %shl
+  %tobool = icmp ne i64 %and, 0
+  br i1 %tobool, label %if.then, label %if.end
+
+if.then:                                          ; preds = %for.body
+  %3 = load i32, i32* %i, align 4
+  %sh_prom2 = zext i32 %3 to i64
+  %shl3 = shl i64 1, %sh_prom2
+  %4 = load i64, i64* %RefCopy, align 8
+  %or = or i64 %4, %shl3
+  store i64 %or, i64* %RefCopy, align 8
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %for.body
+  br label %for.inc
+
+for.inc:                                          ; preds = %if.end
+  %5 = load i32, i32* %i, align 4
+  %inc = add nsw i32 %5, 1
+  store i32 %inc, i32* %i, align 4
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  %6 = load i64, i64* %RefCopy, align 8
+  %7 = inttoptr i64 %6 to i32**
+  store i32** %7, i32*** %AliasA1, align 8
+  %8 = load i32**, i32*** %AliasA1, align 8
+  %9 = load i32*, i32** %8, align 8
+  store i32* %9, i32** %ShouldAliasA, align 8
+  ret void
+}
diff --git a/test/Analysis/CFLAliasAnalysis/const-expr-gep.ll b/test/Analysis/CFLAliasAnalysis/const-expr-gep.ll
index 9ae200bc5701..c7ff407db2f6 100644
--- a/test/Analysis/CFLAliasAnalysis/const-expr-gep.ll
+++ b/test/Analysis/CFLAliasAnalysis/const-expr-gep.ll
@@ -7,15 +7,51 @@
 %T = type { i32, [10 x i8] }
 
 @G = external global %T
+@G2 = external global %T
 
-; CHECK:     Function: test
-; CHECK-NOT:   May:
+; TODO: Quite a few of these are MayAlias because we don't yet consider
+; constant offsets in CFLAA. If we start doing so, then we'll need to
+; change these test cases
 
+; CHECK:     Function: test
+; CHECK:     MayAlias: i32* %D, i32* %F
+; CHECK:     MayAlias: i32* %D, i8* %X
+; CHECK:     MayAlias: i32* %F, i8* %X
 define void @test() {
-  %D = getelementptr %T* @G, i64 0, i32 0
-  %E = getelementptr %T* @G, i64 0, i32 1, i64 5
-  %F = getelementptr i32* getelementptr (%T* @G, i64 0, i32 0), i64 0
-  %X = getelementptr [10 x i8]* getelementptr (%T* @G, i64 0, i32 1), i64 0, i64 5
+  %D = getelementptr %T, %T* @G, i64 0, i32 0
+  %F = getelementptr i32, i32* getelementptr (%T, %T* @G, i64 0, i32 0), i64 0
+  %X = getelementptr [10 x i8], [10 x i8]* getelementptr (%T, %T* @G, i64 0, i32 1), i64 0, i64 5
+
+  ret void
+}
+
+; CHECK:     Function: simplecheck
+; CHECK:     MayAlias: i32* %F, i32* %arg0
+; CHECK:     MayAlias: i32* %H, i32* %arg0
+; CHECK:     MayAlias: i32* %F, i32* %H
+define void @simplecheck(i32* %arg0) {
+  %F = getelementptr i32, i32* getelementptr (%T, %T* @G, i64 0, i32 0), i64 0
+  %H = getelementptr %T, %T* @G2, i64 0, i32 0
+
+  ret void
+}
+
+; Ensure that CFLAA properly identifies and handles escaping variables (i.e.
+; globals) in nested ConstantExprs
+
+; CHECK:      Function: checkNesting
+; CHECK:      MayAlias: i32* %A, i32* %arg0
+
+%NestedT = type { [1 x [1 x i32]] }
+@NT = external global %NestedT
 
+define void @checkNesting(i32* %arg0) {
+  %A = getelementptr [1 x i32],
+         [1 x i32]* getelementptr
+           ([1 x [1 x i32]], [1 x [1 x i32]]* getelementptr (%NestedT, %NestedT* @NT, i64 0, i32 0),
+           i64 0,
+           i32 0),
+         i64 0,
+         i32 0
   ret void
 }
diff --git a/test/Analysis/CFLAliasAnalysis/constant-over-index.ll b/test/Analysis/CFLAliasAnalysis/constant-over-index.ll
index fb44b95d134f..a8e00aaed378 100644
--- a/test/Analysis/CFLAliasAnalysis/constant-over-index.ll
+++ b/test/Analysis/CFLAliasAnalysis/constant-over-index.ll
@@ -10,13 +10,13 @@
 
 define void @foo([3 x [3 x double]]* noalias %p) {
 entry:
-  %p3 = getelementptr [3 x [3 x double]]* %p, i64 0, i64 0, i64 3
+  %p3 = getelementptr [3 x [3 x double]], [3 x [3 x double]]* %p, i64 0, i64 0, i64 3
   br label %loop
 
 loop:
   %i = phi i64 [ 0, %entry ], [ %i.next, %loop ]
 
-  %p.0.i.0 = getelementptr [3 x [3 x double]]* %p, i64 0, i64 %i, i64 0
+  %p.0.i.0 = getelementptr [3 x [3 x double]], [3 x [3 x double]]* %p, i64 0, i64 %i, i64 0
 
   store volatile double 0.0, double* %p3
   store volatile double 0.1, double* %p.0.i.0
diff --git a/test/Analysis/CFLAliasAnalysis/full-store-partial-alias.ll b/test/Analysis/CFLAliasAnalysis/full-store-partial-alias.ll
index 664ea9eb1180..adacf048d678 100644
--- a/test/Analysis/CFLAliasAnalysis/full-store-partial-alias.ll
+++ b/test/Analysis/CFLAliasAnalysis/full-store-partial-alias.ll
@@ -2,8 +2,9 @@
 ; RUN: opt -S -tbaa -gvn < %s | FileCheck %s
 ; Adapted from the BasicAA full-store-partial-alias.ll test.
 
-; CFL AA should notice that the store stores to the entire %u object,
+; CFL AA could notice that the store stores to the entire %u object,
 ; so the %tmp5 load is PartialAlias with the store and suppress TBAA.
+; FIXME: However, right now, CFLAA cannot prove PartialAlias here
 ; Without CFL AA, TBAA should say that %tmp5 is NoAlias with the store.
 
 target datalayout = "e-p:64:64:64"
@@ -14,17 +15,18 @@ target datalayout = "e-p:64:64:64"
 @endianness_test = global i64 1, align 8
 
 define i32 @signbit(double %x) nounwind {
-; CFLAA: ret i32 %tmp5.lobit
-; CHECK:   ret i32 0
+; FIXME: This would be ret i32 %tmp5.lobit if CFLAA could prove PartialAlias
+; CFLAA: ret i32 0
+; CHECK: ret i32 0
 entry:
   %u = alloca %union.anon, align 8
-  %tmp9 = getelementptr inbounds %union.anon* %u, i64 0, i32 0
+  %tmp9 = getelementptr inbounds %union.anon, %union.anon* %u, i64 0, i32 0
   store double %x, double* %tmp9, align 8, !tbaa !0
-  %tmp2 = load i32* bitcast (i64* @endianness_test to i32*), align 8, !tbaa !3
+  %tmp2 = load i32, i32* bitcast (i64* @endianness_test to i32*), align 8, !tbaa !3
   %idxprom = sext i32 %tmp2 to i64
   %tmp4 = bitcast %union.anon* %u to [2 x i32]*
-  %arrayidx = getelementptr inbounds [2 x i32]* %tmp4, i64 0, i64 %idxprom
-  %tmp5 = load i32* %arrayidx, align 4, !tbaa !3
+  %arrayidx = getelementptr inbounds [2 x i32], [2 x i32]* %tmp4, i64 0, i64 %idxprom
+  %tmp5 = load i32, i32* %arrayidx, align 4, !tbaa !3
   %tmp5.lobit = lshr i32 %tmp5, 31
   ret i32 %tmp5.lobit
 }
diff --git a/test/Analysis/CFLAliasAnalysis/gep-signed-arithmetic.ll b/test/Analysis/CFLAliasAnalysis/gep-signed-arithmetic.ll
index a0195d7f8d6a..c2fcf32ce06b 100644
--- a/test/Analysis/CFLAliasAnalysis/gep-signed-arithmetic.ll
+++ b/test/Analysis/CFLAliasAnalysis/gep-signed-arithmetic.ll
@@ -3,15 +3,17 @@
 
 target datalayout = "e-p:32:32:32"
 
-; CHECK: 1 partial alias response
+; FIXME: This could be PartialAlias but CFLAA can't currently prove it
+; CHECK: 1 may alias response
 
-define i32 @test(i32* %tab, i32 %indvar) nounwind {
+define i32 @test(i32 %indvar) nounwind {
+  %tab = alloca i32, align 4
   %tmp31 = mul i32 %indvar, -2
   %tmp32 = add i32 %tmp31, 30
-  %t.5 = getelementptr i32* %tab, i32 %tmp32
-  %loada = load i32* %tab
+  %t.5 = getelementptr i32, i32* %tab, i32 %tmp32
+  %loada = load i32, i32* %tab
   store i32 0, i32* %t.5
-  %loadb = load i32* %tab
+  %loadb = load i32, i32* %tab
   %rval = add i32 %loada, %loadb
   ret i32 %rval
 }
diff --git a/test/Analysis/CFLAliasAnalysis/multilevel-combine.ll b/test/Analysis/CFLAliasAnalysis/multilevel-combine.ll
index 9bbc721a7b16..e997374e92d9 100644
--- a/test/Analysis/CFLAliasAnalysis/multilevel-combine.ll
+++ b/test/Analysis/CFLAliasAnalysis/multilevel-combine.ll
@@ -25,7 +25,7 @@ define void @test(i1 %C) {
 
   store %T* %MS, %T** %M
 
-  %AP = load %T** %M ; PartialAlias with %A, %B
+  %AP = load %T*, %T** %M ; PartialAlias with %A, %B
 
   ret void
 }
diff --git a/test/Analysis/CFLAliasAnalysis/multilevel.ll b/test/Analysis/CFLAliasAnalysis/multilevel.ll
index 9c9eb9a49779..d42dca442eab 100644
--- a/test/Analysis/CFLAliasAnalysis/multilevel.ll
+++ b/test/Analysis/CFLAliasAnalysis/multilevel.ll
@@ -23,8 +23,8 @@ define void @test() {
   store %T* %A, %T** %M
   store %T* %B, %T** %N
 
-  %AP = load %T** %M ; PartialAlias with %A
-  %BP = load %T** %N ; PartialAlias with %B
+  %AP = load %T*, %T** %M ; PartialAlias with %A
+  %BP = load %T*, %T** %N ; PartialAlias with %B
 
   ret void
 }
diff --git a/test/Analysis/CFLAliasAnalysis/must-and-partial.ll b/test/Analysis/CFLAliasAnalysis/must-and-partial.ll
index df7de38ebd73..9deacf860ed8 100644
--- a/test/Analysis/CFLAliasAnalysis/must-and-partial.ll
+++ b/test/Analysis/CFLAliasAnalysis/must-and-partial.ll
@@ -1,15 +1,16 @@
 ; RUN: opt < %s -cfl-aa -aa-eval -print-all-alias-modref-info 2>&1 | FileCheck %s
-
 ; When merging MustAlias and PartialAlias, merge to PartialAlias
 ; instead of MayAlias.
 
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 
-; CHECK: PartialAlias:  i16* %bigbase0, i8* %phi
-define i8 @test0(i8* %base, i1 %x) {
+; FIXME: This could be PartialAlias but CFLAA can't currently prove it
+; CHECK: MayAlias:  i16* %bigbase0, i8* %phi
+define i8 @test0(i1 %x) {
 entry:
-  %baseplusone = getelementptr i8* %base, i64 1
+  %base = alloca i8, align 4
+  %baseplusone = getelementptr i8, i8* %base, i64 1
   br i1 %x, label %red, label %green
 red:
   br label %green
@@ -20,20 +21,34 @@ green:
   %bigbase0 = bitcast i8* %base to i16*
   store i16 -1, i16* %bigbase0
 
-  %loaded = load i8* %phi
+  %loaded = load i8, i8* %phi
   ret i8 %loaded
 }
 
-; CHECK: PartialAlias:  i16* %bigbase1, i8* %sel
-define i8 @test1(i8* %base, i1 %x) {
+; FIXME: This could be PartialAlias but CFLAA can't currently prove it
+; CHECK: MayAlias:  i16* %bigbase1, i8* %sel
+define i8 @test1(i1 %x) {
 entry:
-  %baseplusone = getelementptr i8* %base, i64 1
+  %base = alloca i8, align 4
+  %baseplusone = getelementptr i8, i8* %base, i64 1
   %sel = select i1 %x, i8* %baseplusone, i8* %base
   store i8 0, i8* %sel
 
   %bigbase1 = bitcast i8* %base to i16*
   store i16 -1, i16* %bigbase1
 
-  %loaded = load i8* %sel
+  %loaded = load i8, i8* %sel
   ret i8 %loaded
 }
+
+; Incoming pointer arguments should not be PartialAlias because we do not know their initial state
+; even if they are nocapture
+; CHECK: MayAlias:  double* %A, double* %Index
+define void @testr2(double* nocapture readonly %A, double* nocapture readonly %Index) {
+  %arrayidx22 = getelementptr inbounds double, double* %Index, i64 2
+  %1 = load double, double* %arrayidx22
+  %arrayidx25 = getelementptr inbounds double, double* %A, i64 2
+  %2 = load double, double* %arrayidx25
+  %mul26 = fmul double %1, %2
+  ret void
+}
diff --git a/test/Analysis/CFLAliasAnalysis/simple.ll b/test/Analysis/CFLAliasAnalysis/simple.ll
index 7bc455ae7a2d..adc71867bfc1 100644
--- a/test/Analysis/CFLAliasAnalysis/simple.ll
+++ b/test/Analysis/CFLAliasAnalysis/simple.ll
@@ -9,10 +9,10 @@
 ; CHECK-NOT:   May:
 
 define void @test(%T* %P) {
-  %A = getelementptr %T* %P, i64 0
-  %B = getelementptr %T* %P, i64 0, i32 0
-  %C = getelementptr %T* %P, i64 0, i32 1
-  %D = getelementptr %T* %P, i64 0, i32 1, i64 0
-  %E = getelementptr %T* %P, i64 0, i32 1, i64 5
+  %A = getelementptr %T, %T* %P, i64 0
+  %B = getelementptr %T, %T* %P, i64 0, i32 0
+  %C = getelementptr %T, %T* %P, i64 0, i32 1
+  %D = getelementptr %T, %T* %P, i64 0, i32 1, i64 0
+  %E = getelementptr %T, %T* %P, i64 0, i32 1, i64 5
   ret void
 }
diff --git a/test/Analysis/CFLAliasAnalysis/stratified-attrs-indexing.ll b/test/Analysis/CFLAliasAnalysis/stratified-attrs-indexing.ll
new file mode 100644
index 000000000000..347528583a61
--- /dev/null
+++ b/test/Analysis/CFLAliasAnalysis/stratified-attrs-indexing.ll
@@ -0,0 +1,33 @@
+; This testcase ensures that CFLAA doesn't try to access out of bounds indices
+; when given functions with large amounts of arguments (specifically, more
+; arguments than the StratifiedAttrs bitset can handle)
+;
+; Because the result on failure is effectively crashing the compiler, output
+; checking is minimal.
+
+; RUN: opt < %s -cfl-aa -aa-eval -print-may-aliases -disable-output 2>&1 | FileCheck %s
+
+; CHECK: Function: test
+define void @test(i1 %cond,
+                  i32* %arg1, i32* %arg2, i32* %arg3, i32* %arg4, i32* %arg5,
+                  i32* %arg6, i32* %arg7, i32* %arg8, i32* %arg9, i32* %arg10,
+                  i32* %arg11, i32* %arg12, i32* %arg13, i32* %arg14, i32* %arg15,
+                  i32* %arg16, i32* %arg17, i32* %arg18, i32* %arg19, i32* %arg20,
+                  i32* %arg21, i32* %arg22, i32* %arg23, i32* %arg24, i32* %arg25,
+                  i32* %arg26, i32* %arg27, i32* %arg28, i32* %arg29, i32* %arg30,
+                  i32* %arg31, i32* %arg32, i32* %arg33, i32* %arg34, i32* %arg35) {
+
+  ; CHECK: 946 Total Alias Queries Performed
+  ; CHECK: 43 no alias responses (4.5%)
+  %a = alloca i32, align 4
+  %b = select i1 %cond, i32* %arg35, i32* %arg34
+  %c = select i1 %cond, i32* %arg34, i32* %arg33
+  %d = select i1 %cond, i32* %arg33, i32* %arg32
+  %e = select i1 %cond, i32* %arg32, i32* %arg31
+  %f = select i1 %cond, i32* %arg31, i32* %arg30
+  %g = select i1 %cond, i32* %arg30, i32* %arg29
+  %h = select i1 %cond, i32* %arg29, i32* %arg28
+  %i = select i1 %cond, i32* %arg28, i32* %arg27
+
+  ret void
+}
diff --git a/test/Analysis/CallGraph/2008-09-09-DirectCall.ll b/test/Analysis/CallGraph/2008-09-09-DirectCall.ll
index 595cc427c452..56eac49c1684 100644
--- a/test/Analysis/CallGraph/2008-09-09-DirectCall.ll
+++ b/test/Analysis/CallGraph/2008-09-09-DirectCall.ll
@@ -12,6 +12,6 @@ entry:
 
 define void @caller() {
 entry:
-	call void (...)* @callee( void (...)* @callee )
+	call void (...) @callee( void (...)* @callee )
 	unreachable
 }
diff --git a/test/Analysis/CostModel/AArch64/store.ll b/test/Analysis/CostModel/AArch64/store.ll
index 0c9883cf2a2f..307f8f8ee974 100644
--- a/test/Analysis/CostModel/AArch64/store.ll
+++ b/test/Analysis/CostModel/AArch64/store.ll
@@ -14,9 +14,9 @@ define void @store() {
     ; CHECK: cost of 64 {{.*}} store
     store <4 x i8> undef, <4 x i8> * undef
     ; CHECK: cost of 16 {{.*}} load
-    load <2 x i8> * undef
+    load <2 x i8> , <2 x i8> * undef
     ; CHECK: cost of 64 {{.*}} load
-    load <4 x i8> * undef
+    load <4 x i8> , <4 x i8> * undef
 
     ret void
 }
diff --git a/test/Analysis/CostModel/ARM/gep.ll b/test/Analysis/CostModel/ARM/gep.ll
index a63b87d2ad11..624ca113a302 100644
--- a/test/Analysis/CostModel/ARM/gep.ll
+++ b/test/Analysis/CostModel/ARM/gep.ll
@@ -6,37 +6,37 @@ target triple = "thumbv7-apple-ios6.0.0"
 define void @test_geps() {
   ; Cost of scalar integer geps should be one. We can't always expect it to be
   ; folded into the instruction addressing mode.
-;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i8*
-  %a0 = getelementptr inbounds i8* undef, i32 0
-;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i16*
-  %a1 = getelementptr inbounds i16* undef, i32 0
-;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i32*
-  %a2 = getelementptr inbounds i32* undef, i32 0
+;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i8, i8*
+  %a0 = getelementptr inbounds i8, i8* undef, i32 0
+;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i16, i16*
+  %a1 = getelementptr inbounds i16, i16* undef, i32 0
+;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i32, i32*
+  %a2 = getelementptr inbounds i32, i32* undef, i32 0
 
-;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i64*
-  %a3 = getelementptr inbounds i64* undef, i32 0
+;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i64, i64*
+  %a3 = getelementptr inbounds i64, i64* undef, i32 0
 
   ; Cost of scalar floating point geps should be one. We cannot fold the address
   ; computation.
-;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds float*
-  %a4 = getelementptr inbounds float* undef, i32 0
-;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds double*
-  %a5 = getelementptr inbounds double* undef, i32 0
+;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds float, float*
+  %a4 = getelementptr inbounds float, float* undef, i32 0
+;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds double, double*
+  %a5 = getelementptr inbounds double, double* undef, i32 0
 
 
   ; Cost of vector geps should be one. We cannot fold the address computation.
-;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i8>*
-  %a7 = getelementptr inbounds <4 x i8>* undef, i32 0
-;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i16>*
-  %a8 = getelementptr inbounds <4 x i16>* undef, i32 0
-;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i32>*
-  %a9 = getelementptr inbounds <4 x i32>* undef, i32 0
-;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i64>*
-  %a10 = getelementptr inbounds <4 x i64>* undef, i32 0
-;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x float>*
-  %a11 = getelementptr inbounds <4 x float>* undef, i32 0
-;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x double>*
-  %a12 = getelementptr inbounds <4 x double>* undef, i32 0
+;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i8>, <4 x i8>*
+  %a7 = getelementptr inbounds <4 x i8>, <4 x i8>* undef, i32 0
+;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i16>, <4 x i16>*
+  %a8 = getelementptr inbounds <4 x i16>, <4 x i16>* undef, i32 0
+;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i32>, <4 x i32>*
+  %a9 = getelementptr inbounds <4 x i32>, <4 x i32>* undef, i32 0
+;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i64>, <4 x i64>*
+  %a10 = getelementptr inbounds <4 x i64>, <4 x i64>* undef, i32 0
+;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x float>, <4 x float>*
+  %a11 = getelementptr inbounds <4 x float>, <4 x float>* undef, i32 0
+;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x double>, <4 x double>*
+  %a12 = getelementptr inbounds <4 x double>, <4 x double>* undef, i32 0
 
 
   ret void
diff --git a/test/Analysis/CostModel/ARM/insertelement.ll b/test/Analysis/CostModel/ARM/insertelement.ll
index f951b08f9baa..bd1467ef4a56 100644
--- a/test/Analysis/CostModel/ARM/insertelement.ll
+++ b/test/Analysis/CostModel/ARM/insertelement.ll
@@ -10,8 +10,8 @@ target triple = "thumbv7-apple-ios6.0.0"
 ; CHECK: insertelement_i8
 define void @insertelement_i8(%T_i8* %saddr,
                            %T_i8v* %vaddr) {
-  %v0 = load %T_i8v* %vaddr
-  %v1 = load %T_i8* %saddr
+  %v0 = load %T_i8v, %T_i8v* %vaddr
+  %v1 = load %T_i8, %T_i8* %saddr
 ;CHECK: estimated cost of 3 for {{.*}} insertelement <8 x i8>
   %v2 = insertelement %T_i8v %v0, %T_i8 %v1, i32 1
   store %T_i8v %v2, %T_i8v* %vaddr
@@ -24,8 +24,8 @@ define void @insertelement_i8(%T_i8* %saddr,
 ; CHECK: insertelement_i16
 define void @insertelement_i16(%T_i16* %saddr,
                            %T_i16v* %vaddr) {
-  %v0 = load %T_i16v* %vaddr
-  %v1 = load %T_i16* %saddr
+  %v0 = load %T_i16v, %T_i16v* %vaddr
+  %v1 = load %T_i16, %T_i16* %saddr
 ;CHECK: estimated cost of 3 for {{.*}} insertelement <4 x i16>
   %v2 = insertelement %T_i16v %v0, %T_i16 %v1, i32 1
   store %T_i16v %v2, %T_i16v* %vaddr
@@ -37,8 +37,8 @@ define void @insertelement_i16(%T_i16* %saddr,
 ; CHECK: insertelement_i32
 define void @insertelement_i32(%T_i32* %saddr,
                            %T_i32v* %vaddr) {
-  %v0 = load %T_i32v* %vaddr
-  %v1 = load %T_i32* %saddr
+  %v0 = load %T_i32v, %T_i32v* %vaddr
+  %v1 = load %T_i32, %T_i32* %saddr
 ;CHECK: estimated cost of 3 for {{.*}} insertelement <2 x i32>
   %v2 = insertelement %T_i32v %v0, %T_i32 %v1, i32 1
   store %T_i32v %v2, %T_i32v* %vaddr
diff --git a/test/Analysis/CostModel/PowerPC/load_store.ll b/test/Analysis/CostModel/PowerPC/load_store.ll
index 368f0a73489b..1e50f1651e0a 100644
--- a/test/Analysis/CostModel/PowerPC/load_store.ll
+++ b/test/Analysis/CostModel/PowerPC/load_store.ll
@@ -19,26 +19,26 @@ define i32 @stores(i32 %arg) {
 }
 define i32 @loads(i32 %arg) {
   ; CHECK: cost of 1 {{.*}} load
-  load i8* undef, align 4
+  load i8, i8* undef, align 4
   ; CHECK: cost of 1 {{.*}} load
-  load i16* undef, align 4
+  load i16, i16* undef, align 4
   ; CHECK: cost of 1 {{.*}} load
-  load i32* undef, align 4
+  load i32, i32* undef, align 4
   ; CHECK: cost of 2 {{.*}} load
-  load i64* undef, align 4
+  load i64, i64* undef, align 4
   ; CHECK: cost of 4 {{.*}} load
-  load i128* undef, align 4
+  load i128, i128* undef, align 4
 
   ; FIXME: There actually are sub-vector Altivec loads, and so we could handle
   ; this with a small expense, but we don't currently.
   ; CHECK: cost of 48 {{.*}} load
-  load <4 x i16>* undef, align 2
+  load <4 x i16>, <4 x i16>* undef, align 2
 
   ; CHECK: cost of 1 {{.*}} load
-  load <4 x i32>* undef, align 4
+  load <4 x i32>, <4 x i32>* undef, align 4
 
   ; CHECK: cost of 46 {{.*}} load
-  load <3 x float>* undef, align 1
+  load <3 x float>, <3 x float>* undef, align 1
 
   ret i32 undef
 }
diff --git a/test/Analysis/CostModel/X86/gep.ll b/test/Analysis/CostModel/X86/gep.ll
index 877184a3eaa8..a4488ba422b8 100644
--- a/test/Analysis/CostModel/X86/gep.ll
+++ b/test/Analysis/CostModel/X86/gep.ll
@@ -7,33 +7,33 @@ target triple = "x86_64-apple-macosx10.8.0"
 define void @test_geps() {
   ; Cost of should be zero. We expect it to be folded into
   ; the instruction addressing mode.
-;CHECK:  cost of 0 for instruction: {{.*}} getelementptr inbounds i8*
-  %a0 = getelementptr inbounds i8* undef, i32 0
-;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i16*
-  %a1 = getelementptr inbounds i16* undef, i32 0
-;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i32*
-  %a2 = getelementptr inbounds i32* undef, i32 0
-;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i64*
-  %a3 = getelementptr inbounds i64* undef, i32 0
+;CHECK:  cost of 0 for instruction: {{.*}} getelementptr inbounds i8, i8*
+  %a0 = getelementptr inbounds i8, i8* undef, i32 0
+;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i16, i16*
+  %a1 = getelementptr inbounds i16, i16* undef, i32 0
+;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i32, i32*
+  %a2 = getelementptr inbounds i32, i32* undef, i32 0
+;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i64, i64*
+  %a3 = getelementptr inbounds i64, i64* undef, i32 0
 
-;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds float*
-  %a4 = getelementptr inbounds float* undef, i32 0
-;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds double*
-  %a5 = getelementptr inbounds double* undef, i32 0
+;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds float, float*
+  %a4 = getelementptr inbounds float, float* undef, i32 0
+;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds double, double*
+  %a5 = getelementptr inbounds double, double* undef, i32 0
 
  ; Vector geps should also have zero cost.
-;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i8>*
-  %a7 = getelementptr inbounds <4 x i8>* undef, i32 0
-;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i16>*
-  %a8 = getelementptr inbounds <4 x i16>* undef, i32 0
-;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i32>*
-  %a9 = getelementptr inbounds <4 x i32>* undef, i32 0
-;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i64>*
-  %a10 = getelementptr inbounds <4 x i64>* undef, i32 0
-;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x float>*
-  %a11 = getelementptr inbounds <4 x float>* undef, i32 0
-;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x double>*
-  %a12 = getelementptr inbounds <4 x double>* undef, i32 0
+;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i8>, <4 x i8>*
+  %a7 = getelementptr inbounds <4 x i8>, <4 x i8>* undef, i32 0
+;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i16>, <4 x i16>*
+  %a8 = getelementptr inbounds <4 x i16>, <4 x i16>* undef, i32 0
+;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i32>, <4 x i32>*
+  %a9 = getelementptr inbounds <4 x i32>, <4 x i32>* undef, i32 0
+;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i64>, <4 x i64>*
+  %a10 = getelementptr inbounds <4 x i64>, <4 x i64>* undef, i32 0
+;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x float>, <4 x float>*
+  %a11 = getelementptr inbounds <4 x float>, <4 x float>* undef, i32 0
+;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x double>, <4 x double>*
+  %a12 = getelementptr inbounds <4 x double>, <4 x double>* undef, i32 0
 
 
   ret void
diff --git a/test/Analysis/CostModel/X86/intrinsic-cost.ll b/test/Analysis/CostModel/X86/intrinsic-cost.ll
index 3b27b52f7654..efc1263373e5 100644
--- a/test/Analysis/CostModel/X86/intrinsic-cost.ll
+++ b/test/Analysis/CostModel/X86/intrinsic-cost.ll
@@ -9,9 +9,9 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %0 = getelementptr inbounds float* %f, i64 %index
+  %0 = getelementptr inbounds float, float* %f, i64 %index
   %1 = bitcast float* %0 to <4 x float>*
-  %wide.load = load <4 x float>* %1, align 4
+  %wide.load = load <4 x float>, <4 x float>* %1, align 4
   %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.load)
   store <4 x float> %2, <4 x float>* %1, align 4
   %index.next = add i64 %index, 4
@@ -22,7 +22,7 @@ for.end:                                          ; preds = %vector.body
   ret void
 
 ; CORE2: Printing analysis 'Cost Model Analysis' for function 'test1':
-; CORE2: Cost Model: Found an estimated cost of 400 for instruction:   %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.load)
+; CORE2: Cost Model: Found an estimated cost of 46 for instruction:   %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.load)
 
 ; COREI7: Printing analysis 'Cost Model Analysis' for function 'test1':
 ; COREI7: Cost Model: Found an estimated cost of 1 for instruction:   %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.load)
@@ -37,9 +37,9 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %0 = getelementptr inbounds float* %f, i64 %index
+  %0 = getelementptr inbounds float, float* %f, i64 %index
   %1 = bitcast float* %0 to <4 x float>*
-  %wide.load = load <4 x float>* %1, align 4
+  %wide.load = load <4 x float>, <4 x float>* %1, align 4
   %2 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %wide.load)
   store <4 x float> %2, <4 x float>* %1, align 4
   %index.next = add i64 %index, 4
@@ -50,7 +50,7 @@ for.end:                                          ; preds = %vector.body
   ret void
 
 ; CORE2: Printing analysis 'Cost Model Analysis' for function 'test2':
-; CORE2: Cost Model: Found an estimated cost of 400 for instruction:   %2 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %wide.load)
+; CORE2: Cost Model: Found an estimated cost of 46 for instruction:   %2 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %wide.load)
 
 ; COREI7: Printing analysis 'Cost Model Analysis' for function 'test2':
 ; COREI7: Cost Model: Found an estimated cost of 1 for instruction:   %2 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %wide.load)
@@ -65,9 +65,9 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %0 = getelementptr inbounds float* %f, i64 %index
+  %0 = getelementptr inbounds float, float* %f, i64 %index
   %1 = bitcast float* %0 to <4 x float>*
-  %wide.load = load <4 x float>* %1, align 4
+  %wide.load = load <4 x float>, <4 x float>* %1, align 4
   %2 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %wide.load, <4 x float> %b, <4 x float> %c)
   store <4 x float> %2, <4 x float>* %1, align 4
   %index.next = add i64 %index, 4
diff --git a/test/Analysis/CostModel/X86/load_store.ll b/test/Analysis/CostModel/X86/load_store.ll
index a53d0bd4e993..ccf110a3a371 100644
--- a/test/Analysis/CostModel/X86/load_store.ll
+++ b/test/Analysis/CostModel/X86/load_store.ll
@@ -34,49 +34,49 @@ define i32 @stores(i32 %arg) {
 }
 define i32 @loads(i32 %arg) {
   ;CHECK: cost of 1 {{.*}} load
-  load i8* undef, align 4
+  load i8, i8* undef, align 4
   ;CHECK: cost of 1 {{.*}} load
-  load i16* undef, align 4
+  load i16, i16* undef, align 4
   ;CHECK: cost of 1 {{.*}} load
-  load i32* undef, align 4
+  load i32, i32* undef, align 4
   ;CHECK: cost of 1 {{.*}} load
-  load i64* undef, align 4
+  load i64, i64* undef, align 4
   ;CHECK: cost of 2 {{.*}} load
-  load i128* undef, align 4
+  load i128, i128* undef, align 4
 
   ;CHECK: cost of 1 {{.*}} load
-  load <2 x i32>* undef, align 4
+  load <2 x i32>, <2 x i32>* undef, align 4
   ;CHECK: cost of 1 {{.*}} load
-  load <4 x i32>* undef, align 4
+  load <4 x i32>, <4 x i32>* undef, align 4
   ;CHECK: cost of 2 {{.*}} load
-  load <8 x i32>* undef, align 4
+  load <8 x i32>, <8 x i32>* undef, align 4
 
 
   ;CHECK: cost of 1 {{.*}} load
-  load <2 x i64>* undef, align 4
+  load <2 x i64>, <2 x i64>* undef, align 4
   ;CHECK: cost of 2 {{.*}} load
-  load <4 x i64>* undef, align 4
+  load <4 x i64>, <4 x i64>* undef, align 4
   ;CHECK: cost of 4 {{.*}} load
-  load <8 x i64>* undef, align 4
+  load <8 x i64>, <8 x i64>* undef, align 4
 
 
   ;CHECK: cost of 3 {{.*}} load
-  load <3 x float>* undef, align 4
+  load <3 x float>, <3 x float>* undef, align 4
 
   ;CHECK: cost of 3 {{.*}} load
-  load <3 x double>* undef, align 4
+  load <3 x double>, <3 x double>* undef, align 4
 
   ;CHECK: cost of 3 {{.*}} load
-  load <3 x i32>* undef, align 4
+  load <3 x i32>, <3 x i32>* undef, align 4
 
   ;CHECK: cost of 3 {{.*}} load
-  load <3 x i64>* undef, align 4
+  load <3 x i64>, <3 x i64>* undef, align 4
 
   ;CHECK: cost of 10 {{.*}} load
-  load <5 x i32>* undef, align 4
+  load <5 x i32>, <5 x i32>* undef, align 4
 
   ;CHECK: cost of 10 {{.*}} load
-  load <5 x i64>* undef, align 4
+  load <5 x i64>, <5 x i64>* undef, align 4
 
   ret i32 undef
 }
diff --git a/test/Analysis/CostModel/X86/loop_v2.ll b/test/Analysis/CostModel/X86/loop_v2.ll
index 348444eb0833..9283310e6003 100644
--- a/test/Analysis/CostModel/X86/loop_v2.ll
+++ b/test/Analysis/CostModel/X86/loop_v2.ll
@@ -10,20 +10,20 @@ vector.ph:
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
   %vec.phi = phi <2 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]
-  %0 = getelementptr inbounds i32* %A, i64 %index
+  %0 = getelementptr inbounds i32, i32* %A, i64 %index
   %1 = bitcast i32* %0 to <2 x i32>*
-  %2 = load <2 x i32>* %1, align 4
+  %2 = load <2 x i32>, <2 x i32>* %1, align 4
   %3 = sext <2 x i32> %2 to <2 x i64>
   ;CHECK: cost of 1 {{.*}} extract
   %4 = extractelement <2 x i64> %3, i32 0
-  %5 = getelementptr inbounds i32* %A, i64 %4
+  %5 = getelementptr inbounds i32, i32* %A, i64 %4
   ;CHECK: cost of 1 {{.*}} extract
   %6 = extractelement <2 x i64> %3, i32 1
-  %7 = getelementptr inbounds i32* %A, i64 %6
-  %8 = load i32* %5, align 4
+  %7 = getelementptr inbounds i32, i32* %A, i64 %6
+  %8 = load i32, i32* %5, align 4
   ;CHECK: cost of 1 {{.*}} insert
   %9 = insertelement <2 x i32> undef, i32 %8, i32 0
-  %10 = load i32* %7, align 4
+  %10 = load i32, i32* %7, align 4
   ;CHECK: cost of 1 {{.*}} insert
   %11 = insertelement <2 x i32> %9, i32 %10, i32 1
   %12 = add nsw <2 x i32> %11, %vec.phi
diff --git a/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll b/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
new file mode 100644
index 000000000000..4683c432c559
--- /dev/null
+++ b/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
@@ -0,0 +1,89 @@
+; RUN: opt -S -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -cost-model -analyze < %s | FileCheck %s -check-prefix=AVX2
+
+
+; AVX2-LABEL: test1
+; AVX2: Found an estimated cost of 4 {{.*}}.masked
+define <2 x double> @test1(<2 x i64> %trigger, <2 x double>* %addr, <2 x double> %dst) {
+  %mask = icmp eq <2 x i64> %trigger, zeroinitializer
+  %res = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %addr, i32 4, <2 x i1>%mask, <2 x double>%dst)
+  ret <2 x double> %res
+}
+
+; AVX2-LABEL: test2
+; AVX2: Found an estimated cost of 4 {{.*}}.masked
+define <4 x i32> @test2(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %dst) {
+  %mask = icmp eq <4 x i32> %trigger, zeroinitializer
+  %res = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %addr, i32 4, <4 x i1>%mask, <4 x i32>%dst)
+  ret <4 x i32> %res
+}
+
+; AVX2-LABEL: test3
+; AVX2: Found an estimated cost of 4 {{.*}}.masked
+define void @test3(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %val) {
+  %mask = icmp eq <4 x i32> %trigger, zeroinitializer
+  call void @llvm.masked.store.v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1>%mask)
+  ret void
+}
+
+; AVX2-LABEL: test4
+; AVX2: Found an estimated cost of 4 {{.*}}.masked
+define <8 x float> @test4(<8 x i32> %trigger, <8 x float>* %addr, <8 x float> %dst) {
+  %mask = icmp eq <8 x i32> %trigger, zeroinitializer
+  %res = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 4, <8 x i1>%mask, <8 x float>%dst)
+  ret <8 x float> %res
+}
+
+; AVX2-LABEL: test5
+; AVX2: Found an estimated cost of 5 {{.*}}.masked
+define void @test5(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %val) {
+  %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+  call void @llvm.masked.store.v2f32(<2 x float>%val, <2 x float>* %addr, i32 4, <2 x i1>%mask)
+  ret void
+}
+
+; AVX2-LABEL: test6
+; AVX2: Found an estimated cost of 6 {{.*}}.masked
+define void @test6(<2 x i32> %trigger, <2 x i32>* %addr, <2 x i32> %val) {
+  %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+  call void @llvm.masked.store.v2i32(<2 x i32>%val, <2 x i32>* %addr, i32 4, <2 x i1>%mask)
+  ret void
+}
+
+; AVX2-LABEL: test7
+; AVX2: Found an estimated cost of 5 {{.*}}.masked
+define <2 x float> @test7(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %dst) {
+  %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+  %res = call <2 x float> @llvm.masked.load.v2f32(<2 x float>* %addr, i32 4, <2 x i1>%mask, <2 x float>%dst)
+  ret <2 x float> %res
+}
+
+; AVX2-LABEL: test8
+; AVX2: Found an estimated cost of 6 {{.*}}.masked
+define <2 x i32> @test8(<2 x i32> %trigger, <2 x i32>* %addr, <2 x i32> %dst) {
+  %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+  %res = call <2 x i32> @llvm.masked.load.v2i32(<2 x i32>* %addr, i32 4, <2 x i1>%mask, <2 x i32>%dst)
+  ret <2 x i32> %res
+}
+
+
+declare <16 x i32> @llvm.masked.load.v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>)
+declare <4 x i32> @llvm.masked.load.v4i32(<4 x i32>*, i32, <4 x i1>, <4 x i32>)
+declare <2 x i32> @llvm.masked.load.v2i32(<2 x i32>*, i32, <2 x i1>, <2 x i32>)
+declare void @llvm.masked.store.v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)
+declare void @llvm.masked.store.v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>)
+declare void @llvm.masked.store.v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>)
+declare void @llvm.masked.store.v2f32(<2 x float>, <2 x float>*, i32, <2 x i1>)
+declare void @llvm.masked.store.v2i32(<2 x i32>, <2 x i32>*, i32, <2 x i1>)
+declare void @llvm.masked.store.v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)
+declare void @llvm.masked.store.v16f32p(<16 x float>*, <16 x float>**, i32, <16 x i1>)
+declare <16 x float> @llvm.masked.load.v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)
+declare <8 x float> @llvm.masked.load.v8f32(<8 x float>*, i32, <8 x i1>, <8 x float>)
+declare <4 x float> @llvm.masked.load.v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>)
+declare <2 x float> @llvm.masked.load.v2f32(<2 x float>*, i32, <2 x i1>, <2 x float>)
+declare <8 x double> @llvm.masked.load.v8f64(<8 x double>*, i32, <8 x i1>, <8 x double>)
+declare <4 x double> @llvm.masked.load.v4f64(<4 x double>*, i32, <4 x i1>, <4 x double>)
+declare <2 x double> @llvm.masked.load.v2f64(<2 x double>*, i32, <2 x i1>, <2 x double>)
+declare void @llvm.masked.store.v8f64(<8 x double>, <8 x double>*, i32, <8 x i1>)
+declare void @llvm.masked.store.v2f64(<2 x double>, <2 x double>*, i32, <2 x i1>)
+declare void @llvm.masked.store.v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>)
+
diff --git a/test/Analysis/CostModel/X86/testshiftlshr.ll b/test/Analysis/CostModel/X86/testshiftlshr.ll
index 7bc8d89e4ad8..78bf0a608307 100644
--- a/test/Analysis/CostModel/X86/testshiftlshr.ll
+++ b/test/Analysis/CostModel/X86/testshiftlshr.ll
@@ -7,7 +7,7 @@ entry:
   ; SSE2: shift2i16
   ; SSE2: cost of 20 {{.*}} lshr
   ; SSE2-CODEGEN: shift2i16
-  ; SSE2-CODEGEN: shrq %cl
+  ; SSE2-CODEGEN: psrlq
 
   %0 = lshr %shifttype %a , %b
   ret %shifttype %0
@@ -67,7 +67,7 @@ entry:
   ; SSE2: shift2i32
   ; SSE2: cost of 20 {{.*}} lshr
   ; SSE2-CODEGEN: shift2i32
-  ; SSE2-CODEGEN: shrq %cl
+  ; SSE2-CODEGEN: psrlq
 
   %0 = lshr %shifttype2i32 %a , %b
   ret %shifttype2i32 %0
@@ -127,7 +127,7 @@ entry:
   ; SSE2: shift2i64
   ; SSE2: cost of 20 {{.*}} lshr
   ; SSE2-CODEGEN: shift2i64
-  ; SSE2-CODEGEN: shrq %cl
+  ; SSE2-CODEGEN: psrlq
 
   %0 = lshr %shifttype2i64 %a , %b
   ret %shifttype2i64 %0
@@ -139,7 +139,7 @@ entry:
   ; SSE2: shift4i64
   ; SSE2: cost of 40 {{.*}} lshr
   ; SSE2-CODEGEN: shift4i64
-  ; SSE2-CODEGEN: shrq %cl
+  ; SSE2-CODEGEN: psrlq
 
   %0 = lshr %shifttype4i64 %a , %b
   ret %shifttype4i64 %0
@@ -151,7 +151,7 @@ entry:
   ; SSE2: shift8i64
   ; SSE2: cost of 80 {{.*}} lshr
   ; SSE2-CODEGEN: shift8i64
-  ; SSE2-CODEGEN: shrq %cl
+  ; SSE2-CODEGEN: psrlq
 
   %0 = lshr %shifttype8i64 %a , %b
   ret %shifttype8i64 %0
@@ -163,7 +163,7 @@ entry:
   ; SSE2: shift16i64
   ; SSE2: cost of 160 {{.*}} lshr
   ; SSE2-CODEGEN: shift16i64
-  ; SSE2-CODEGEN: shrq %cl
+  ; SSE2-CODEGEN: psrlq
 
   %0 = lshr %shifttype16i64 %a , %b
   ret %shifttype16i64 %0
@@ -175,7 +175,7 @@ entry:
   ; SSE2: shift32i64
   ; SSE2: cost of 320 {{.*}} lshr
   ; SSE2-CODEGEN: shift32i64
-  ; SSE2-CODEGEN: shrq %cl
+  ; SSE2-CODEGEN: psrlq
 
   %0 = lshr %shifttype32i64 %a , %b
   ret %shifttype32i64 %0
@@ -187,7 +187,7 @@ entry:
   ; SSE2: shift2i8
   ; SSE2: cost of 20 {{.*}} lshr
   ; SSE2-CODEGEN: shift2i8
-  ; SSE2-CODEGEN: shrq %cl
+  ; SSE2-CODEGEN: psrlq
 
   %0 = lshr %shifttype2i8 %a , %b
   ret %shifttype2i8 %0
diff --git a/test/Analysis/CostModel/X86/testshiftshl.ll b/test/Analysis/CostModel/X86/testshiftshl.ll
index 40effd02922c..c36e0f5dfdfe 100644
--- a/test/Analysis/CostModel/X86/testshiftshl.ll
+++ b/test/Analysis/CostModel/X86/testshiftshl.ll
@@ -7,7 +7,7 @@ entry:
   ; SSE2: shift2i16
   ; SSE2: cost of 20 {{.*}} shl
   ; SSE2-CODEGEN: shift2i16
-  ; SSE2-CODEGEN: shlq %cl
+  ; SSE2-CODEGEN: psllq
 
   %0 = shl %shifttype %a , %b
   ret %shifttype %0
@@ -67,7 +67,7 @@ entry:
   ; SSE2: shift2i32
   ; SSE2: cost of 20 {{.*}} shl
   ; SSE2-CODEGEN: shift2i32
-  ; SSE2-CODEGEN: shlq %cl
+  ; SSE2-CODEGEN: psllq
 
   %0 = shl %shifttype2i32 %a , %b
   ret %shifttype2i32 %0
@@ -127,7 +127,7 @@ entry:
   ; SSE2: shift2i64
   ; SSE2: cost of 20 {{.*}} shl
   ; SSE2-CODEGEN: shift2i64
-  ; SSE2-CODEGEN: shlq %cl
+  ; SSE2-CODEGEN: psllq
 
   %0 = shl %shifttype2i64 %a , %b
   ret %shifttype2i64 %0
@@ -139,7 +139,7 @@ entry:
   ; SSE2: shift4i64
   ; SSE2: cost of 40 {{.*}} shl
   ; SSE2-CODEGEN: shift4i64
-  ; SSE2-CODEGEN: shlq %cl
+  ; SSE2-CODEGEN: psllq
 
   %0 = shl %shifttype4i64 %a , %b
   ret %shifttype4i64 %0
@@ -151,7 +151,7 @@ entry:
   ; SSE2: shift8i64
   ; SSE2: cost of 80 {{.*}} shl
   ; SSE2-CODEGEN: shift8i64
-  ; SSE2-CODEGEN: shlq %cl
+  ; SSE2-CODEGEN: psllq
 
   %0 = shl %shifttype8i64 %a , %b
   ret %shifttype8i64 %0
@@ -163,7 +163,7 @@ entry:
   ; SSE2: shift16i64
   ; SSE2: cost of 160 {{.*}} shl
   ; SSE2-CODEGEN: shift16i64
-  ; SSE2-CODEGEN: shlq %cl
+  ; SSE2-CODEGEN: psllq
 
   %0 = shl %shifttype16i64 %a , %b
   ret %shifttype16i64 %0
@@ -175,7 +175,7 @@ entry:
   ; SSE2: shift32i64
   ; SSE2: cost of 320 {{.*}} shl
   ; SSE2-CODEGEN: shift32i64
-  ; SSE2-CODEGEN: shlq %cl
+  ; SSE2-CODEGEN: psllq
 
   %0 = shl %shifttype32i64 %a , %b
   ret %shifttype32i64 %0
@@ -187,7 +187,7 @@ entry:
   ; SSE2: shift2i8
   ; SSE2: cost of 20 {{.*}} shl
   ; SSE2-CODEGEN: shift2i8
-  ; SSE2-CODEGEN: shlq %cl
+  ; SSE2-CODEGEN: psllq
 
   %0 = shl %shifttype2i8 %a , %b
   ret %shifttype2i8 %0
diff --git a/test/Analysis/CostModel/X86/vectorized-loop.ll b/test/Analysis/CostModel/X86/vectorized-loop.ll
index af7d1df8a570..2dd52a00782e 100644
--- a/test/Analysis/CostModel/X86/vectorized-loop.ll
+++ b/test/Analysis/CostModel/X86/vectorized-loop.ll
@@ -25,17 +25,17 @@ for.body.lr.ph:                                   ; preds = %entry
 vector.body:                                      ; preds = %for.body.lr.ph, %vector.body
   %index = phi i64 [ %index.next, %vector.body ], [ %0, %for.body.lr.ph ]
   %3 = add i64 %index, 2
-  %4 = getelementptr inbounds i32* %B, i64 %3
+  %4 = getelementptr inbounds i32, i32* %B, i64 %3
   ;CHECK: cost of 0 {{.*}} bitcast
   %5 = bitcast i32* %4 to <8 x i32>*
   ;CHECK: cost of 2 {{.*}} load
-  %6 = load <8 x i32>* %5, align 4
+  %6 = load <8 x i32>, <8 x i32>* %5, align 4
   ;CHECK: cost of 4 {{.*}} mul
   %7 = mul nsw <8 x i32> %6, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
-  %8 = getelementptr inbounds i32* %A, i64 %index
+  %8 = getelementptr inbounds i32, i32* %A, i64 %index
   %9 = bitcast i32* %8 to <8 x i32>*
   ;CHECK: cost of 2 {{.*}} load
-  %10 = load <8 x i32>* %9, align 4
+  %10 = load <8 x i32>, <8 x i32>* %9, align 4
   ;CHECK: cost of 4 {{.*}} add
   %11 = add nsw <8 x i32> %10, %7
   ;CHECK: cost of 2 {{.*}} store
@@ -52,14 +52,14 @@ middle.block:                                     ; preds = %vector.body, %for.b
 for.body:                                         ; preds = %middle.block, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ %end.idx.rnd.down, %middle.block ]
   %13 = add nsw i64 %indvars.iv, 2
-  %arrayidx = getelementptr inbounds i32* %B, i64 %13
+  %arrayidx = getelementptr inbounds i32, i32* %B, i64 %13
   ;CHECK: cost of 1 {{.*}} load
-  %14 = load i32* %arrayidx, align 4
+  %14 = load i32, i32* %arrayidx, align 4
   ;CHECK: cost of 1 {{.*}} mul
   %mul = mul nsw i32 %14, 5
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
   ;CHECK: cost of 1 {{.*}} load
-  %15 = load i32* %arrayidx2, align 4
+  %15 = load i32, i32* %arrayidx2, align 4
   %add3 = add nsw i32 %15, %mul
   store i32 %add3, i32* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Analysis/CostModel/X86/vselect-cost.ll b/test/Analysis/CostModel/X86/vselect-cost.ll
index 2416777506df..b7e56ef52a40 100644
--- a/test/Analysis/CostModel/X86/vselect-cost.ll
+++ b/test/Analysis/CostModel/X86/vselect-cost.ll
@@ -11,7 +11,7 @@
 
 define <2 x i64> @test_2i64(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'test_2i64':
-; SSE2: Cost Model: {{.*}} 4 for instruction:   %sel = select <2 x i1>
+; SSE2: Cost Model: {{.*}} 1 for instruction:   %sel = select <2 x i1>
 ; SSE41: Cost Model: {{.*}} 1 for instruction:   %sel = select <2 x i1>
 ; AVX: Cost Model: {{.*}} 1 for instruction:   %sel = select <2 x i1>
 ; AVX2: Cost Model: {{.*}} 1 for instruction:   %sel = select <2 x i1>
@@ -21,7 +21,7 @@ define <2 x i64> @test_2i64(<2 x i64> %a, <2 x i64> %b) {
 
 define <2 x double> @test_2double(<2 x double> %a, <2 x double> %b) {
 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'test_2double':
-; SSE2: Cost Model: {{.*}} 3 for instruction:   %sel = select <2 x i1>
+; SSE2: Cost Model: {{.*}} 1 for instruction:   %sel = select <2 x i1>
 ; SSE41: Cost Model: {{.*}} 1 for instruction:   %sel = select <2 x i1>
 ; AVX: Cost Model: {{.*}} 1 for instruction:   %sel = select <2 x i1>
 ; AVX2: Cost Model: {{.*}} 1 for instruction:   %sel = select <2 x i1>
@@ -31,7 +31,7 @@ define <2 x double> @test_2double(<2 x double> %a, <2 x double> %b) {
 
 define <4 x i32> @test_4i32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'test_4i32':
-; SSE2: Cost Model: {{.*}} 8 for instruction:   %sel = select <4 x i1>
+; SSE2: Cost Model: {{.*}} 1 for instruction:   %sel = select <4 x i1>
 ; SSE41: Cost Model: {{.*}} 1 for instruction:   %sel = select <4 x i1>
 ; AVX: Cost Model: {{.*}} 1 for instruction:   %sel = select <4 x i1>
 ; AVX2: Cost Model: {{.*}} 1 for instruction:   %sel = select <4 x i1>
@@ -41,7 +41,7 @@ define <4 x i32> @test_4i32(<4 x i32> %a, <4 x i32> %b) {
 
 define <4 x float> @test_4float(<4 x float> %a, <4 x float> %b) {
 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'test_4float':
-; SSE2: Cost Model: {{.*}} 7 for instruction:   %sel = select <4 x i1>
+; SSE2: Cost Model: {{.*}} 1 for instruction:   %sel = select <4 x i1>
 ; SSE41: Cost Model: {{.*}} 1 for instruction:   %sel = select <4 x i1>
 ; AVX: Cost Model: {{.*}} 1 for instruction:   %sel = select <4 x i1>
 ; AVX2: Cost Model: {{.*}} 1 for instruction:   %sel = select <4 x i1>
@@ -51,7 +51,7 @@ define <4 x float> @test_4float(<4 x float> %a, <4 x float> %b) {
 
 define <16 x i8> @test_16i8(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'test_16i8':
-; SSE2: Cost Model: {{.*}} 32 for instruction:   %sel = select <16 x i1>
+; SSE2: Cost Model: {{.*}} 1 for instruction:   %sel = select <16 x i1>
 ; SSE41: Cost Model: {{.*}} 1 for instruction:   %sel = select <16 x i1>
 ; AVX: Cost Model: {{.*}} 1 for instruction:   %sel = select <16 x i1>
 ; AVX2: Cost Model: {{.*}} 1 for instruction:   %sel = select <16 x i1>
@@ -63,7 +63,7 @@ define <16 x i8> @test_16i8(<16 x i8> %a, <16 x i8> %b) {
 ; <8 x float>. Integers of the same size should also use those instructions.
 define <4 x i64> @test_4i64(<4 x i64> %a, <4 x i64> %b) {
 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'test_4i64':
-; SSE2: Cost Model: {{.*}} 8 for instruction:   %sel = select <4 x i1>
+; SSE2: Cost Model: {{.*}} 2 for instruction:   %sel = select <4 x i1>
 ; SSE41: Cost Model: {{.*}} 2 for instruction:   %sel = select <4 x i1>
 ; AVX: Cost Model: {{.*}} 1 for instruction:   %sel = select <4 x i1>
 ; AVX2: Cost Model: {{.*}} 1 for instruction:   %sel = select <4 x i1>
@@ -73,7 +73,7 @@ define <4 x i64> @test_4i64(<4 x i64> %a, <4 x i64> %b) {
 
 define <4 x double> @test_4double(<4 x double> %a, <4 x double> %b) {
 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'test_4double':
-; SSE2: Cost Model: {{.*}} 6 for instruction:   %sel = select <4 x i1>
+; SSE2: Cost Model: {{.*}} 2 for instruction:   %sel = select <4 x i1>
 ; SSE41: Cost Model: {{.*}} 2 for instruction:   %sel = select <4 x i1>
 ; AVX: Cost Model: {{.*}} 1 for instruction:   %sel = select <4 x i1>
 ; AVX2: Cost Model: {{.*}} 1 for instruction:   %sel = select <4 x i1>
@@ -83,7 +83,7 @@ define <4 x double> @test_4double(<4 x double> %a, <4 x double> %b) {
 
 define <8 x i32> @test_8i32(<8 x i32> %a, <8 x i32> %b) {
 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'test_8i32':
-; SSE2: Cost Model: {{.*}} 16 for instruction:   %sel = select <8 x i1>
+; SSE2: Cost Model: {{.*}} 2 for instruction:   %sel = select <8 x i1>
 ; SSE41: Cost Model: {{.*}} 2 for instruction:   %sel = select <8 x i1>
 ; AVX: Cost Model: {{.*}} 1 for instruction:   %sel = select <8 x i1>
 ; AVX2: Cost Model: {{.*}} 1 for instruction:   %sel = select <8 x i1>
@@ -93,7 +93,7 @@ define <8 x i32> @test_8i32(<8 x i32> %a, <8 x i32> %b) {
 
 define <8 x float> @test_8float(<8 x float> %a, <8 x float> %b) {
 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'test_8float':
-; SSE2: Cost Model: {{.*}} 14 for instruction:   %sel = select <8 x i1>
+; SSE2: Cost Model: {{.*}} 2 for instruction:   %sel = select <8 x i1>
 ; SSE41: Cost Model: {{.*}} 2 for instruction:   %sel = select <8 x i1>
 ; AVX: Cost Model: {{.*}} 1 for instruction:   %sel = select <8 x i1>
 ; AVX2: Cost Model: {{.*}} 1 for instruction:   %sel = select <8 x i1>
@@ -104,10 +104,9 @@ define <8 x float> @test_8float(<8 x float> %a, <8 x float> %b) {
 ; AVX2
 define <16 x i16> @test_16i16(<16 x i16> %a, <16 x i16> %b) {
 ; CHECK:Printing analysis 'Cost Model Analysis' for function 'test_16i16':
-; SSE2: Cost Model: {{.*}} 32 for instruction:   %sel = select <16 x i1>
+; SSE2: Cost Model: {{.*}} 2 for instruction:   %sel = select <16 x i1>
 ; SSE41: Cost Model: {{.*}} 2 for instruction:   %sel = select <16 x i1>
-;;; FIXME: This AVX cost is obviously wrong. We shouldn't be scalarizing.
-; AVX: Cost Model: {{.*}} 32 for instruction:   %sel = select <16 x i1>
+; AVX: Cost Model: {{.*}} 1 for instruction:   %sel = select <16 x i1>
 ; AVX2: Cost Model: {{.*}} 1 for instruction:   %sel = select <16 x i1>
   %sel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i16> %a, <16 x i16> %b
   ret <16 x i16> %sel
@@ -115,10 +114,9 @@ define <16 x i16> @test_16i16(<16 x i16> %a, <16 x i16> %b) {
 
 define <32 x i8> @test_32i8(<32 x i8> %a, <32 x i8> %b) {
 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'test_32i8':
-; SSE2: Cost Model: {{.*}} 64 for instruction:   %sel = select <32 x i1>
+; SSE2: Cost Model: {{.*}} 2 for instruction:   %sel = select <32 x i1>
 ; SSE41: Cost Model: {{.*}} 2 for instruction:   %sel = select <32 x i1>
-;;; FIXME: This AVX cost is obviously wrong. We shouldn't be scalarizing.
-; AVX: Cost Model: {{.*}} 64 for instruction:   %sel = select <32 x i1>
+; AVX: Cost Model: {{.*}} 1 for instruction:   %sel = select <32 x i1>
 ; AVX2: Cost Model: {{.*}} 1 for instruction:   %sel = select <32 x i1>
   %sel = select <32 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true>, <32 x i8> %a, <32 x i8> %b
   ret <32 x i8> %sel
diff --git a/test/Analysis/CostModel/no_info.ll b/test/Analysis/CostModel/no_info.ll
index f3f165b1b52a..5f3b56ad9cf8 100644
--- a/test/Analysis/CostModel/no_info.ll
+++ b/test/Analysis/CostModel/no_info.ll
@@ -1,11 +1,12 @@
 ; RUN: opt < %s -cost-model -analyze | FileCheck %s
 
-; The cost model does not have any target information so it can't make a decision.
+; The cost model does not have any target information so it just makes boring
+; assumptions.
 
 ; -- No triple in this module --
 
-;CHECK: Unknown cost {{.*}} add
-;CHECK: Unknown cost {{.*}} ret
+;CHECK: cost of 1 {{.*}} add
+;CHECK: cost of 1 {{.*}} ret
 define i32 @no_info(i32 %arg) {
   %e = add i32 %arg, %arg
   ret i32 %e
diff --git a/test/Analysis/Delinearization/a.ll b/test/Analysis/Delinearization/a.ll
index efebcc42ea27..78bbfcf7de6e 100644
--- a/test/Analysis/Delinearization/a.ll
+++ b/test/Analysis/Delinearization/a.ll
@@ -9,7 +9,7 @@
 
 ; AddRec: {{{(28 + (4 * (-4 + (3 * %m)) * %o) + %A),+,(8 * %m * %o)}<%for.i>,+,(12 * %o)}<%for.j>,+,20}<%for.k>
 ; CHECK: Base offset: %A
-; CHECK: ArrayDecl[UnknownSize][%m][%o] with elements of sizeof(i32) bytes.
+; CHECK: ArrayDecl[UnknownSize][%m][%o] with elements of 4 bytes.
 ; CHECK: ArrayRef[{3,+,2}<%for.i>][{-4,+,3}<%for.j>][{7,+,5}<%for.k>]
 
 define void @foo(i64 %n, i64 %m, i64 %o, i32* nocapture %A) #0 {
@@ -52,7 +52,7 @@ for.k:                                  ; preds = %for.k, %for.j
   %mul.us.us = mul nsw i64 %k.029.us.us, 5
   %arrayidx.sum.us.us = add i64 %mul.us.us, 7
   %arrayidx10.sum.us.us = add i64 %arrayidx.sum.us.us, %tmp27.us.us
-  %arrayidx11.us.us = getelementptr inbounds i32* %A, i64 %arrayidx10.sum.us.us
+  %arrayidx11.us.us = getelementptr inbounds i32, i32* %A, i64 %arrayidx10.sum.us.us
   store i32 1, i32* %arrayidx11.us.us, align 4
   %inc.us.us = add nsw i64 %k.029.us.us, 1
   %exitcond = icmp eq i64 %inc.us.us, %o
diff --git a/test/Analysis/Delinearization/divide_by_one.ll b/test/Analysis/Delinearization/divide_by_one.ll
new file mode 100644
index 000000000000..c6e0b134e045
--- /dev/null
+++ b/test/Analysis/Delinearization/divide_by_one.ll
@@ -0,0 +1,70 @@
+; RUN: opt < %s -analyze -delinearize | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"
+
+; Check that division by 1 can be delinearized.
+;
+; void test1(unsigned char *dst, int stride, int bs) {
+;   for (int r = bs; r >= 0; --r)
+;     for (int c = 0; c < bs; ++c)
+;       dst[r * stride + c] = dst[(r + 1) * stride + c - 1];
+; }
+
+; AddRec: {{(-1 + ((1 + %bs) * %stride)),+,(-1 * %stride)}<%for.cond1.preheader>,+,1}<nw><%for.body3>
+; CHECK: Inst:  %0 = load i8, i8* %arrayidx, align 1
+; CHECK: Base offset: %dst
+; CHECK: ArrayDecl[UnknownSize][%stride] with elements of 1 bytes.
+; CHECK: ArrayRef[{(1 + %bs),+,-1}<nw><%for.cond1.preheader>][{-1,+,1}<nw><%for.body3>]
+
+; AddRec: {{(%stride * %bs),+,(-1 * %stride)}<%for.cond1.preheader>,+,1}<nw><%for.body3>
+; CHECK: Inst:  store i8 %0, i8* %arrayidx7, align 1
+; CHECK: Base offset: %dst
+; CHECK: ArrayDecl[UnknownSize][%stride] with elements of 1 bytes.
+; CHECK: ArrayRef[{%bs,+,-1}<nsw><%for.cond1.preheader>][{0,+,1}<nuw><nsw><%for.body3>]
+
+define void @test(i8* nocapture %dst, i32 %stride, i32 %bs) {
+entry:
+  %cmp20 = icmp sgt i32 %bs, -1
+  br i1 %cmp20, label %for.cond1.preheader.lr.ph, label %for.end9
+
+for.cond1.preheader.lr.ph:
+  %cmp218 = icmp slt i32 0, %bs
+  br label %for.cond1.preheader
+
+for.cond1.preheader:
+  %r.021 = phi i32 [ %bs, %for.cond1.preheader.lr.ph ], [ %dec, %for.inc8 ]
+  br i1 %cmp218, label %for.body3.lr.ph, label %for.inc8
+
+for.body3.lr.ph:
+  %add = add nsw i32 %r.021, 1
+  %mul = mul nsw i32 %add, %stride
+  %add4 = add i32 %mul, -1
+  %mul5 = mul nsw i32 %r.021, %stride
+  br label %for.body3
+
+for.body3:
+  %c.019 = phi i32 [ 0, %for.body3.lr.ph ], [ %inc, %for.body3 ]
+  %sub = add i32 %add4, %c.019
+  %arrayidx = getelementptr inbounds i8, i8* %dst, i32 %sub
+  %0 = load i8, i8* %arrayidx, align 1
+  %add6 = add nsw i32 %c.019, %mul5
+  %arrayidx7 = getelementptr inbounds i8, i8* %dst, i32 %add6
+  store i8 %0, i8* %arrayidx7, align 1
+  %inc = add nsw i32 %c.019, 1
+  %cmp2 = icmp slt i32 %inc, %bs
+  br i1 %cmp2, label %for.body3, label %for.cond1.for.inc8_crit_edge
+
+for.cond1.for.inc8_crit_edge:
+  br label %for.inc8
+
+for.inc8:
+  %dec = add nsw i32 %r.021, -1
+  %cmp = icmp sgt i32 %dec, -1
+  br i1 %cmp, label %for.cond1.preheader, label %for.cond.for.end9_crit_edge
+
+for.cond.for.end9_crit_edge:
+  br label %for.end9
+
+for.end9:
+  ret void
+}
diff --git a/test/Analysis/Delinearization/gcd_multiply_expr.ll b/test/Analysis/Delinearization/gcd_multiply_expr.ll
index f962f6db7f2b..c30a672b840b 100644
--- a/test/Analysis/Delinearization/gcd_multiply_expr.ll
+++ b/test/Analysis/Delinearization/gcd_multiply_expr.ll
@@ -27,7 +27,7 @@
 
 define i32 @fn2() {
 entry:
-  %.pr = load i32* @d, align 4
+  %.pr = load i32, i32* @d, align 4
   %phitmp = icmp eq i32 %.pr, 0
   br label %for.cond
 
@@ -36,11 +36,11 @@ for.cond:
   br i1 %0, label %for.cond, label %for.cond2thread-pre-split.preheader.i
 
 for.cond2thread-pre-split.preheader.i:
-  %1 = load i32* @g, align 4
-  %2 = load i32* @h, align 4
+  %1 = load i32, i32* @g, align 4
+  %2 = load i32, i32* @h, align 4
   %mul = mul nsw i32 %2, %1
-  %3 = load i8** @f, align 4
-  %.pr.pre.i = load i32* @b, align 4
+  %3 = load i8*, i8** @f, align 4
+  %.pr.pre.i = load i32, i32* @b, align 4
   br label %for.cond2thread-pre-split.i
 
 for.cond2thread-pre-split.i:
@@ -64,57 +64,57 @@ for.body4.i.preheader:
 for.body4.i:
   %8 = phi i32 [ %inc.7.i, %for.body4.i ], [ %.pr.i, %for.body4.i.preheader ]
   %arrayidx.sum1 = add i32 %add.i, %8
-  %arrayidx.i = getelementptr inbounds i8* %3, i32 %arrayidx.sum1
-  %9 = load i8* %arrayidx.i, align 1
+  %arrayidx.i = getelementptr inbounds i8, i8* %3, i32 %arrayidx.sum1
+  %9 = load i8, i8* %arrayidx.i, align 1
   %conv.i = sext i8 %9 to i32
   store i32 %conv.i, i32* @c, align 4
   %inc.i = add nsw i32 %8, 1
   store i32 %inc.i, i32* @b, align 4
   %arrayidx.sum2 = add i32 %add.i, %inc.i
-  %arrayidx.1.i = getelementptr inbounds i8* %3, i32 %arrayidx.sum2
-  %10 = load i8* %arrayidx.1.i, align 1
+  %arrayidx.1.i = getelementptr inbounds i8, i8* %3, i32 %arrayidx.sum2
+  %10 = load i8, i8* %arrayidx.1.i, align 1
   %conv.1.i = sext i8 %10 to i32
   store i32 %conv.1.i, i32* @c, align 4
   %inc.1.i = add nsw i32 %8, 2
   store i32 %inc.1.i, i32* @b, align 4
   %arrayidx.sum3 = add i32 %add.i, %inc.1.i
-  %arrayidx.2.i = getelementptr inbounds i8* %3, i32 %arrayidx.sum3
-  %11 = load i8* %arrayidx.2.i, align 1
+  %arrayidx.2.i = getelementptr inbounds i8, i8* %3, i32 %arrayidx.sum3
+  %11 = load i8, i8* %arrayidx.2.i, align 1
   %conv.2.i = sext i8 %11 to i32
   store i32 %conv.2.i, i32* @c, align 4
   %inc.2.i = add nsw i32 %8, 3
   store i32 %inc.2.i, i32* @b, align 4
   %arrayidx.sum4 = add i32 %add.i, %inc.2.i
-  %arrayidx.3.i = getelementptr inbounds i8* %3, i32 %arrayidx.sum4
-  %12 = load i8* %arrayidx.3.i, align 1
+  %arrayidx.3.i = getelementptr inbounds i8, i8* %3, i32 %arrayidx.sum4
+  %12 = load i8, i8* %arrayidx.3.i, align 1
   %conv.3.i = sext i8 %12 to i32
   store i32 %conv.3.i, i32* @c, align 4
   %inc.3.i = add nsw i32 %8, 4
   store i32 %inc.3.i, i32* @b, align 4
   %arrayidx.sum5 = add i32 %add.i, %inc.3.i
-  %arrayidx.4.i = getelementptr inbounds i8* %3, i32 %arrayidx.sum5
-  %13 = load i8* %arrayidx.4.i, align 1
+  %arrayidx.4.i = getelementptr inbounds i8, i8* %3, i32 %arrayidx.sum5
+  %13 = load i8, i8* %arrayidx.4.i, align 1
   %conv.4.i = sext i8 %13 to i32
   store i32 %conv.4.i, i32* @c, align 4
   %inc.4.i = add nsw i32 %8, 5
   store i32 %inc.4.i, i32* @b, align 4
   %arrayidx.sum6 = add i32 %add.i, %inc.4.i
-  %arrayidx.5.i = getelementptr inbounds i8* %3, i32 %arrayidx.sum6
-  %14 = load i8* %arrayidx.5.i, align 1
+  %arrayidx.5.i = getelementptr inbounds i8, i8* %3, i32 %arrayidx.sum6
+  %14 = load i8, i8* %arrayidx.5.i, align 1
   %conv.5.i = sext i8 %14 to i32
   store i32 %conv.5.i, i32* @c, align 4
   %inc.5.i = add nsw i32 %8, 6
   store i32 %inc.5.i, i32* @b, align 4
   %arrayidx.sum7 = add i32 %add.i, %inc.5.i
-  %arrayidx.6.i = getelementptr inbounds i8* %3, i32 %arrayidx.sum7
-  %15 = load i8* %arrayidx.6.i, align 1
+  %arrayidx.6.i = getelementptr inbounds i8, i8* %3, i32 %arrayidx.sum7
+  %15 = load i8, i8* %arrayidx.6.i, align 1
   %conv.6.i = sext i8 %15 to i32
   store i32 %conv.6.i, i32* @c, align 4
   %inc.6.i = add nsw i32 %8, 7
   store i32 %inc.6.i, i32* @b, align 4
   %arrayidx.sum8 = add i32 %add.i, %inc.6.i
-  %arrayidx.7.i = getelementptr inbounds i8* %3, i32 %arrayidx.sum8
-  %16 = load i8* %arrayidx.7.i, align 1
+  %arrayidx.7.i = getelementptr inbounds i8, i8* %3, i32 %arrayidx.sum8
+  %16 = load i8, i8* %arrayidx.7.i, align 1
   %conv.7.i = sext i8 %16 to i32
   store i32 %conv.7.i, i32* @c, align 4
   %inc.7.i = add nsw i32 %8, 8
@@ -135,8 +135,8 @@ for.body4.ur.i.preheader:
 for.body4.ur.i:
   %20 = phi i32 [ %inc.ur.i, %for.body4.ur.i ], [ %.ph, %for.body4.ur.i.preheader ]
   %arrayidx.sum = add i32 %add.i, %20
-  %arrayidx.ur.i = getelementptr inbounds i8* %3, i32 %arrayidx.sum
-  %21 = load i8* %arrayidx.ur.i, align 1
+  %arrayidx.ur.i = getelementptr inbounds i8, i8* %3, i32 %arrayidx.sum
+  %21 = load i8, i8* %arrayidx.ur.i, align 1
   %conv.ur.i = sext i8 %21 to i32
   store i32 %conv.ur.i, i32* @c, align 4
   %inc.ur.i = add nsw i32 %20, 1
diff --git a/test/Analysis/Delinearization/himeno_1.ll b/test/Analysis/Delinearization/himeno_1.ll
index c94ca7aff759..5c86f57f7791 100644
--- a/test/Analysis/Delinearization/himeno_1.ll
+++ b/test/Analysis/Delinearization/himeno_1.ll
@@ -28,31 +28,31 @@
 
 ; AddRec: {{{(4 + (4 * (sext i32 %a.deps to i64) * (1 + (sext i32 %a.cols to i64))) + %a.base),+,(4 * (sext i32 %a.deps to i64) * (sext i32 %a.cols to i64))}<%for.i>,+,(4 * (sext i32 %a.deps to i64))}<%for.j>,+,4}<%for.k>
 ; CHECK: Base offset: %a.base
-; CHECK: ArrayDecl[UnknownSize][(sext i32 %a.cols to i64)][(sext i32 %a.deps to i64)] with elements of sizeof(float) bytes.
+; CHECK: ArrayDecl[UnknownSize][(sext i32 %a.cols to i64)][(sext i32 %a.deps to i64)] with elements of 4 bytes.
 ; CHECK: ArrayRef[{1,+,1}<nuw><nsw><%for.i>][{1,+,1}<nuw><nsw><%for.j>][{1,+,1}<nuw><nsw><%for.k>]
 
 %struct.Mat = type { float*, i32, i32, i32, i32 }
 
 define void @jacobi(i32 %nn, %struct.Mat* nocapture %a, %struct.Mat* nocapture %p) nounwind uwtable {
 entry:
-  %p.rows.ptr = getelementptr inbounds %struct.Mat* %p, i64 0, i32 2
-  %p.rows = load i32* %p.rows.ptr
+  %p.rows.ptr = getelementptr inbounds %struct.Mat, %struct.Mat* %p, i64 0, i32 2
+  %p.rows = load i32, i32* %p.rows.ptr
   %p.rows.sub = add i32 %p.rows, -1
   %p.rows.sext = sext i32 %p.rows.sub to i64
-  %p.cols.ptr = getelementptr inbounds %struct.Mat* %p, i64 0, i32 3
-  %p.cols = load i32* %p.cols.ptr
+  %p.cols.ptr = getelementptr inbounds %struct.Mat, %struct.Mat* %p, i64 0, i32 3
+  %p.cols = load i32, i32* %p.cols.ptr
   %p.cols.sub = add i32 %p.cols, -1
   %p.cols.sext = sext i32 %p.cols.sub to i64
-  %p.deps.ptr = getelementptr inbounds %struct.Mat* %p, i64 0, i32 4
-  %p.deps = load i32* %p.deps.ptr
+  %p.deps.ptr = getelementptr inbounds %struct.Mat, %struct.Mat* %p, i64 0, i32 4
+  %p.deps = load i32, i32* %p.deps.ptr
   %p.deps.sub = add i32 %p.deps, -1
   %p.deps.sext = sext i32 %p.deps.sub to i64
-  %a.cols.ptr = getelementptr inbounds %struct.Mat* %a, i64 0, i32 3
-  %a.cols = load i32* %a.cols.ptr
-  %a.deps.ptr = getelementptr inbounds %struct.Mat* %a, i64 0, i32 4
-  %a.deps = load i32* %a.deps.ptr
-  %a.base.ptr = getelementptr inbounds %struct.Mat* %a, i64 0, i32 0
-  %a.base = load float** %a.base.ptr, align 8
+  %a.cols.ptr = getelementptr inbounds %struct.Mat, %struct.Mat* %a, i64 0, i32 3
+  %a.cols = load i32, i32* %a.cols.ptr
+  %a.deps.ptr = getelementptr inbounds %struct.Mat, %struct.Mat* %a, i64 0, i32 4
+  %a.deps = load i32, i32* %a.deps.ptr
+  %a.base.ptr = getelementptr inbounds %struct.Mat, %struct.Mat* %a, i64 0, i32 0
+  %a.base = load float*, float** %a.base.ptr, align 8
   br label %for.i
 
 for.i:                                            ; preds = %for.i.inc, %entry
@@ -71,7 +71,7 @@ for.k:                                            ; preds = %for.k, %for.j
   %tmp2 = add i64 %tmp1, %j
   %tmp3 = mul i64 %tmp2, %a.deps.sext
   %tmp4 = add nsw i64 %k, %tmp3
-  %arrayidx = getelementptr inbounds float* %a.base, i64 %tmp4
+  %arrayidx = getelementptr inbounds float, float* %a.base, i64 %tmp4
   store float 1.000000e+00, float* %arrayidx
   %k.inc = add nsw i64 %k, 1
   %k.exitcond = icmp eq i64 %k.inc, %p.deps.sext
diff --git a/test/Analysis/Delinearization/himeno_2.ll b/test/Analysis/Delinearization/himeno_2.ll
index c256384f201e..e1e756095022 100644
--- a/test/Analysis/Delinearization/himeno_2.ll
+++ b/test/Analysis/Delinearization/himeno_2.ll
@@ -28,33 +28,33 @@
 
 ; AddRec: {{{(4 + (4 * (sext i32 %a.deps to i64) * (1 + (sext i32 %a.cols to i64))) + %a.base),+,(4 * (sext i32 %a.deps to i64) * (sext i32 %a.cols to i64))}<%for.i>,+,(4 * (sext i32 %a.deps to i64))}<%for.j>,+,4}<%for.k>
 ; CHECK: Base offset: %a.base
-; CHECK: ArrayDecl[UnknownSize][(sext i32 %a.cols to i64)][(sext i32 %a.deps to i64)] with elements of sizeof(float) bytes.
+; CHECK: ArrayDecl[UnknownSize][(sext i32 %a.cols to i64)][(sext i32 %a.deps to i64)] with elements of 4 bytes.
 ; CHECK: ArrayRef[{1,+,1}<nuw><nsw><%for.i>][{1,+,1}<nuw><nsw><%for.j>][{1,+,1}<nuw><nsw><%for.k>]
 
 %struct.Mat = type { float*, i32, i32, i32, i32 }
 
 define void @jacobi(i32 %nn, %struct.Mat* nocapture %a, %struct.Mat* nocapture %p) nounwind uwtable {
 entry:
-  %p.rows.ptr = getelementptr inbounds %struct.Mat* %p, i64 0, i32 2
-  %p.rows = load i32* %p.rows.ptr
+  %p.rows.ptr = getelementptr inbounds %struct.Mat, %struct.Mat* %p, i64 0, i32 2
+  %p.rows = load i32, i32* %p.rows.ptr
   %p.rows.sub = add i32 %p.rows, -1
   %p.rows.sext = sext i32 %p.rows.sub to i64
-  %p.cols.ptr = getelementptr inbounds %struct.Mat* %p, i64 0, i32 3
-  %p.cols = load i32* %p.cols.ptr
+  %p.cols.ptr = getelementptr inbounds %struct.Mat, %struct.Mat* %p, i64 0, i32 3
+  %p.cols = load i32, i32* %p.cols.ptr
   %p.cols.sub = add i32 %p.cols, -1
   %p.cols.sext = sext i32 %p.cols.sub to i64
-  %p.deps.ptr = getelementptr inbounds %struct.Mat* %p, i64 0, i32 4
-  %p.deps = load i32* %p.deps.ptr
+  %p.deps.ptr = getelementptr inbounds %struct.Mat, %struct.Mat* %p, i64 0, i32 4
+  %p.deps = load i32, i32* %p.deps.ptr
   %p.deps.sub = add i32 %p.deps, -1
   %p.deps.sext = sext i32 %p.deps.sub to i64
-  %a.cols.ptr = getelementptr inbounds %struct.Mat* %a, i64 0, i32 3
-  %a.cols = load i32* %a.cols.ptr
+  %a.cols.ptr = getelementptr inbounds %struct.Mat, %struct.Mat* %a, i64 0, i32 3
+  %a.cols = load i32, i32* %a.cols.ptr
   %a.cols.sext = sext i32 %a.cols to i64
-  %a.deps.ptr = getelementptr inbounds %struct.Mat* %a, i64 0, i32 4
-  %a.deps = load i32* %a.deps.ptr
+  %a.deps.ptr = getelementptr inbounds %struct.Mat, %struct.Mat* %a, i64 0, i32 4
+  %a.deps = load i32, i32* %a.deps.ptr
   %a.deps.sext = sext i32 %a.deps to i64
-  %a.base.ptr = getelementptr inbounds %struct.Mat* %a, i64 0, i32 0
-  %a.base = load float** %a.base.ptr, align 8
+  %a.base.ptr = getelementptr inbounds %struct.Mat, %struct.Mat* %a, i64 0, i32 0
+  %a.base = load float*, float** %a.base.ptr, align 8
   br label %for.i
 
 for.i:                                            ; preds = %for.i.inc, %entry
@@ -71,7 +71,7 @@ for.k:                                            ; preds = %for.k, %for.j
   %tmp2 = add i64 %tmp1, %j
   %tmp3 = mul i64 %tmp2, %a.deps.sext
   %tmp4 = add nsw i64 %k, %tmp3
-  %arrayidx = getelementptr inbounds float* %a.base, i64 %tmp4
+  %arrayidx = getelementptr inbounds float, float* %a.base, i64 %tmp4
   store float 1.000000e+00, float* %arrayidx
   %k.inc = add nsw i64 %k, 1
   %k.exitcond = icmp eq i64 %k.inc, %p.deps.sext
diff --git a/test/Analysis/Delinearization/iv_times_constant_in_subscript.ll b/test/Analysis/Delinearization/iv_times_constant_in_subscript.ll
index 01a4b96b11a0..0c893bf11379 100644
--- a/test/Analysis/Delinearization/iv_times_constant_in_subscript.ll
+++ b/test/Analysis/Delinearization/iv_times_constant_in_subscript.ll
@@ -8,9 +8,9 @@
 ;       A[2i+b][2j] = 1.0;
 ; }
 
-; AddRec: {{((%m * %b * sizeof(double)) + %A),+,(2 * %m * sizeof(double))}<%for.i>,+,(2 * sizeof(double))}<%for.j>
+; AddRec: {{((%m * %b * 8) + %A),+,(2 * %m * 8)}<%for.i>,+,(2 * 8)}<%for.j>
 ; CHECK: Base offset: %A
-; CHECK: ArrayDecl[UnknownSize][%m] with elements of sizeof(double) bytes.
+; CHECK: ArrayDecl[UnknownSize][%m] with elements of 8 bytes.
 ; CHECK: ArrayRef[{%b,+,2}<%for.i>][{0,+,2}<%for.j>]
 
 
@@ -29,7 +29,7 @@ for.j:
   %j = phi i64 [ 0, %for.i ], [ %j.inc, %for.j ]
   %prodj = mul i64 %j, 2
   %vlaarrayidx.sum = add i64 %prodj, %tmp
-  %arrayidx = getelementptr inbounds double* %A, i64 %vlaarrayidx.sum
+  %arrayidx = getelementptr inbounds double, double* %A, i64 %vlaarrayidx.sum
   store double 1.0, double* %arrayidx
   %j.inc = add nsw i64 %j, 1
   %j.exitcond = icmp eq i64 %j.inc, %m
diff --git a/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_3d.ll b/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_3d.ll
index ae80ebc52271..317e62c8ef90 100644
--- a/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_3d.ll
+++ b/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_3d.ll
@@ -10,7 +10,7 @@
 
 ; AddRec: {{{(56 + (8 * (-4 + (3 * %m)) * %o) + %A),+,(8 * %m * %o)}<%for.i>,+,(8 * %o)}<%for.j>,+,8}<%for.k>
 ; CHECK: Base offset: %A
-; CHECK: ArrayDecl[UnknownSize][%m][%o] with elements of sizeof(double) bytes.
+; CHECK: ArrayDecl[UnknownSize][%m][%o] with elements of 8 bytes.
 ; CHECK: ArrayRef[{3,+,1}<nw><%for.i>][{-4,+,1}<nw><%for.j>][{7,+,1}<nw><%for.k>]
 
 define void @foo(i64 %n, i64 %m, i64 %o, double* %A) {
@@ -34,7 +34,7 @@ for.k:
   %subscript2 = mul i64 %subscript1, %o
   %offset2 = add nsw i64 %k, 7
   %subscript = add i64 %subscript2, %offset2
-  %idx = getelementptr inbounds double* %A, i64 %subscript
+  %idx = getelementptr inbounds double, double* %A, i64 %subscript
   store double 1.0, double* %idx
   br label %for.k.inc
 
diff --git a/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_nts_3d.ll b/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_nts_3d.ll
index 75080dad3af7..ada7758b21ba 100644
--- a/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_nts_3d.ll
+++ b/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_nts_3d.ll
@@ -10,7 +10,7 @@
 
 ; AddRec: {{{(56 + (8 * (-4 + (3 * %m)) * (%o + %p)) + %A),+,(8 * (%o + %p) * %m)}<%for.cond4.preheader.lr.ph.us>,+,(8 * (%o + %p))}<%for.body6.lr.ph.us.us>,+,8}<%for.body6.us.us>
 ; CHECK: Base offset: %A
-; CHECK: ArrayDecl[UnknownSize][%m][(%o + %p)] with elements of sizeof(double) bytes.
+; CHECK: ArrayDecl[UnknownSize][%m][(%o + %p)] with elements of 8 bytes.
 ; CHECK: ArrayRef[{3,+,1}<nw><%for.cond4.preheader.lr.ph.us>][{-4,+,1}<nw><%for.body6.lr.ph.us.us>][{7,+,1}<nw><%for.body6.us.us>]
 
 define void @foo(i64 %n, i64 %m, i64 %o, i64 %p, double* nocapture %A) nounwind uwtable {
@@ -51,7 +51,7 @@ for.body6.us.us:                                  ; preds = %for.body6.us.us, %f
   %k.019.us.us = phi i64 [ 0, %for.body6.lr.ph.us.us ], [ %inc.us.us, %for.body6.us.us ]
   %arrayidx.sum.us.us = add i64 %k.019.us.us, 7
   %arrayidx9.sum.us.us = add i64 %arrayidx.sum.us.us, %tmp17.us.us
-  %arrayidx10.us.us = getelementptr inbounds double* %A, i64 %arrayidx9.sum.us.us
+  %arrayidx10.us.us = getelementptr inbounds double, double* %A, i64 %arrayidx9.sum.us.us
   store double 1.000000e+00, double* %arrayidx10.us.us, align 8
   %inc.us.us = add nsw i64 %k.019.us.us, 1
   %exitcond = icmp eq i64 %inc.us.us, %o
diff --git a/test/Analysis/Delinearization/multidim_ivs_and_parameteric_offsets_3d.ll b/test/Analysis/Delinearization/multidim_ivs_and_parameteric_offsets_3d.ll
index e921444668d0..9e37b76e59b9 100644
--- a/test/Analysis/Delinearization/multidim_ivs_and_parameteric_offsets_3d.ll
+++ b/test/Analysis/Delinearization/multidim_ivs_and_parameteric_offsets_3d.ll
@@ -10,7 +10,7 @@
 
 ; AddRec: {{{((8 * ((((%m * %p) + %q) * %o) + %r)) + %A),+,(8 * %m * %o)}<%for.i>,+,(8 * %o)}<%for.j>,+,8}<%for.k>
 ; CHECK: Base offset: %A
-; CHECK: ArrayDecl[UnknownSize][%m][%o] with elements of sizeof(double) bytes.
+; CHECK: ArrayDecl[UnknownSize][%m][%o] with elements of 8 bytes.
 ; CHECK: ArrayRef[{%p,+,1}<nw><%for.i>][{%q,+,1}<nw><%for.j>][{%r,+,1}<nw><%for.k>]
 
 define void @foo(i64 %n, i64 %m, i64 %o, double* %A, i64 %p, i64 %q, i64 %r) {
@@ -34,7 +34,7 @@ for.k:
   %subscript2 = mul i64 %subscript1, %o
   %offset2 = add nsw i64 %k, %r
   %subscript = add i64 %subscript2, %offset2
-  %idx = getelementptr inbounds double* %A, i64 %subscript
+  %idx = getelementptr inbounds double, double* %A, i64 %subscript
   store double 1.0, double* %idx
   br label %for.k.inc
 
diff --git a/test/Analysis/Delinearization/multidim_only_ivs_2d.ll b/test/Analysis/Delinearization/multidim_only_ivs_2d.ll
index 5a88c4ce4eb1..66e2348a9275 100644
--- a/test/Analysis/Delinearization/multidim_only_ivs_2d.ll
+++ b/test/Analysis/Delinearization/multidim_only_ivs_2d.ll
@@ -8,18 +8,18 @@
 ;       A[i][j] = 1.0;
 ; }
 
-; Inst:  %val = load double* %arrayidx
+; Inst:  %val = load double, double* %arrayidx
 ; In Loop with Header: for.j
-; AddRec: {{0,+,(%m * sizeof(double))}<%for.i>,+,sizeof(double)}<%for.j>
+; AddRec: {{0,+,(%m * 8)}<%for.i>,+,8}<%for.j>
 ; Base offset: %A
-; ArrayDecl[UnknownSize][%m] with elements of sizeof(double) bytes.
+; ArrayDecl[UnknownSize][%m] with elements of 8 bytes.
 ; ArrayRef[{0,+,1}<nuw><nsw><%for.i>][{0,+,1}<nuw><nsw><%for.j>]
 
 ; Inst:  store double %val, double* %arrayidx
 ; In Loop with Header: for.j
 ; AddRec: {{%A,+,(8 * %m)}<%for.i>,+,8}<%for.j>
 ; CHECK: Base offset: %A
-; CHECK: ArrayDecl[UnknownSize][%m] with elements of sizeof(double) bytes.
+; CHECK: ArrayDecl[UnknownSize][%m] with elements of 8 bytes.
 ; CHECK: ArrayRef[{0,+,1}<nuw><nsw><%for.i>][{0,+,1}<nuw><nsw><%for.j>]
 
 define void @foo(i64 %n, i64 %m, double* %A) {
@@ -34,8 +34,8 @@ for.i:
 for.j:
   %j = phi i64 [ 0, %for.i ], [ %j.inc, %for.j ]
   %vlaarrayidx.sum = add i64 %j, %tmp
-  %arrayidx = getelementptr inbounds double* %A, i64 %vlaarrayidx.sum
-  %val = load double* %arrayidx
+  %arrayidx = getelementptr inbounds double, double* %A, i64 %vlaarrayidx.sum
+  %val = load double, double* %arrayidx
   store double %val, double* %arrayidx
   %j.inc = add nsw i64 %j, 1
   %j.exitcond = icmp eq i64 %j.inc, %m
diff --git a/test/Analysis/Delinearization/multidim_only_ivs_2d_nested.ll b/test/Analysis/Delinearization/multidim_only_ivs_2d_nested.ll
index 810188f7d552..1ca18c1013a5 100644
--- a/test/Analysis/Delinearization/multidim_only_ivs_2d_nested.ll
+++ b/test/Analysis/Delinearization/multidim_only_ivs_2d_nested.ll
@@ -53,7 +53,7 @@ for.body9.lr.ph.us.us:                            ; preds = %for.cond7.preheader
 for.body9.us.us:                                  ; preds = %for.body9.us.us, %for.body9.lr.ph.us.us
   %j.021.us.us = phi i64 [ 0, %for.body9.lr.ph.us.us ], [ %inc.us.us, %for.body9.us.us ]
   %arrayidx.sum.us.us = add i64 %j.021.us.us, %0
-  %arrayidx10.us.us = getelementptr inbounds double* %vla.us, i64 %arrayidx.sum.us.us
+  %arrayidx10.us.us = getelementptr inbounds double, double* %vla.us, i64 %arrayidx.sum.us.us
   store double 1.000000e+00, double* %arrayidx10.us.us, align 8
   %inc.us.us = add nsw i64 %j.021.us.us, 1
   %exitcond50 = icmp eq i64 %inc.us.us, %indvars.iv48
diff --git a/test/Analysis/Delinearization/multidim_only_ivs_3d.ll b/test/Analysis/Delinearization/multidim_only_ivs_3d.ll
index aad0f0940840..8cb7ad56749f 100644
--- a/test/Analysis/Delinearization/multidim_only_ivs_3d.ll
+++ b/test/Analysis/Delinearization/multidim_only_ivs_3d.ll
@@ -10,7 +10,7 @@
 
 ; AddRec: {{{%A,+,(8 * %m * %o)}<%for.i>,+,(8 * %o)}<%for.j>,+,8}<%for.k>
 ; CHECK: Base offset: %A
-; CHECK: ArrayDecl[UnknownSize][%m][%o] with elements of sizeof(double) bytes.
+; CHECK: ArrayDecl[UnknownSize][%m][%o] with elements of 8 bytes.
 ; CHECK: ArrayRef[{0,+,1}<nuw><nsw><%for.i>][{0,+,1}<nuw><nsw><%for.j>][{0,+,1}<nuw><nsw><%for.k>]
 
 define void @foo(i64 %n, i64 %m, i64 %o, double* %A) {
@@ -31,7 +31,7 @@ for.k:
   %subscript1 = add i64 %j, %subscript0
   %subscript2 = mul i64 %subscript1, %o
   %subscript = add i64 %subscript2, %k
-  %idx = getelementptr inbounds double* %A, i64 %subscript
+  %idx = getelementptr inbounds double, double* %A, i64 %subscript
   store double 1.0, double* %idx
   br label %for.k.inc
 
diff --git a/test/Analysis/Delinearization/multidim_only_ivs_3d_cast.ll b/test/Analysis/Delinearization/multidim_only_ivs_3d_cast.ll
index 9e406d125f44..e08d1b900957 100644
--- a/test/Analysis/Delinearization/multidim_only_ivs_3d_cast.ll
+++ b/test/Analysis/Delinearization/multidim_only_ivs_3d_cast.ll
@@ -38,7 +38,7 @@ for.k:
   %tmp.us.us = add i64 %j, %tmp
   %tmp17.us.us = mul i64 %tmp.us.us, %n_zext
   %subscript = add i64 %tmp17.us.us, %k
-  %idx = getelementptr inbounds double* %A, i64 %subscript
+  %idx = getelementptr inbounds double, double* %A, i64 %subscript
   store double 1.0, double* %idx
   br label %for.k.inc
 
diff --git a/test/Analysis/Delinearization/multidim_two_accesses_different_delinearization.ll b/test/Analysis/Delinearization/multidim_two_accesses_different_delinearization.ll
index 6a98507340ac..6775bba88d02 100644
--- a/test/Analysis/Delinearization/multidim_two_accesses_different_delinearization.ll
+++ b/test/Analysis/Delinearization/multidim_two_accesses_different_delinearization.ll
@@ -23,11 +23,11 @@ for.j:
   %j = phi i64 [ 0, %for.i ], [ %j.inc, %for.j ]
   %tmp = mul nsw i64 %i, %m
   %vlaarrayidx.sum = add i64 %j, %tmp
-  %arrayidx = getelementptr inbounds double* %A, i64 %vlaarrayidx.sum
+  %arrayidx = getelementptr inbounds double, double* %A, i64 %vlaarrayidx.sum
   store double 1.0, double* %arrayidx
   %tmp1 = mul nsw i64 %j, %n
   %vlaarrayidx.sum1 = add i64 %i, %tmp1
-  %arrayidx1 = getelementptr inbounds double* %A, i64 %vlaarrayidx.sum1
+  %arrayidx1 = getelementptr inbounds double, double* %A, i64 %vlaarrayidx.sum1
   store double 1.0, double* %arrayidx1
   %j.inc = add nsw i64 %j, 1
   %j.exitcond = icmp eq i64 %j.inc, %m
diff --git a/test/Analysis/Delinearization/type_mismatch.ll b/test/Analysis/Delinearization/type_mismatch.ll
new file mode 100644
index 000000000000..0aa9a96cb1f2
--- /dev/null
+++ b/test/Analysis/Delinearization/type_mismatch.ll
@@ -0,0 +1,29 @@
+; RUN: opt < %s -analyze -delinearize
+; REQUIRES: asserts
+
+; Test that SCEV divide code doesn't crash when attempting to create a SCEV
+; with operands of different types. In this case, the visitAddRecExpr
+; function tries to create an AddRec where the start and step are different
+; types.
+
+target datalayout = "e-m:e-p:32:32-i64:64-a:0-v32:32-n16:32"
+
+define fastcc void @test() {
+entry:
+  %0 = load i16, i16* undef, align 2
+  %conv21 = zext i16 %0 to i32
+  br label %for.cond7.preheader
+
+for.cond7.preheader:
+  %p1.022 = phi i8* [ undef, %entry ], [ %add.ptr, %for.end ]
+  br label %for.body11
+
+for.body11:
+  %arrayidx.phi = phi i8* [ %p1.022, %for.cond7.preheader ], [ undef, %for.body11 ]
+  store i8 undef, i8* %arrayidx.phi, align 1
+  br i1 undef, label %for.body11, label %for.end
+
+for.end:
+  %add.ptr = getelementptr inbounds i8, i8* %p1.022, i32 %conv21
+  br label %for.cond7.preheader
+}
diff --git a/test/Analysis/Delinearization/undef.ll b/test/Analysis/Delinearization/undef.ll
index 8ee64e3a2f40..399ff2782aa4 100644
--- a/test/Analysis/Delinearization/undef.ll
+++ b/test/Analysis/Delinearization/undef.ll
@@ -20,8 +20,8 @@ for.body60:
   %tmp5 = add i64 %iy.067, %0
   %tmp6 = mul i64 %tmp5, undef
   %arrayidx69.sum = add i64 undef, %tmp6
-  %arrayidx70 = getelementptr inbounds double* %Ey, i64 %arrayidx69.sum
-  %1 = load double* %arrayidx70, align 8
+  %arrayidx70 = getelementptr inbounds double, double* %Ey, i64 %arrayidx69.sum
+  %1 = load double, double* %arrayidx70, align 8
   %inc = add nsw i64 %ix.062, 1
   br i1 false, label %for.body60, label %for.end
 
diff --git a/test/Analysis/DependenceAnalysis/Banerjee.ll b/test/Analysis/DependenceAnalysis/Banerjee.ll
index 883a06d0bed5..84459b26aa56 100644
--- a/test/Analysis/DependenceAnalysis/Banerjee.ll
+++ b/test/Analysis/DependenceAnalysis/Banerjee.ll
@@ -40,21 +40,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %B.addr.11 = phi i64* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ]
   %mul = mul nsw i64 %i.03, 10
   %add = add nsw i64 %mul, %j.02
-  %arrayidx = getelementptr inbounds i64* %A, i64 %add
+  %arrayidx = getelementptr inbounds i64, i64* %A, i64 %add
   store i64 0, i64* %arrayidx, align 8
   %mul4 = mul nsw i64 %i.03, 10
   %add5 = add nsw i64 %mul4, %j.02
   %sub = add nsw i64 %add5, -1
-  %arrayidx6 = getelementptr inbounds i64* %A, i64 %sub
-  %0 = load i64* %arrayidx6, align 8
-  %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1
+  %arrayidx6 = getelementptr inbounds i64, i64* %A, i64 %sub
+  %0 = load i64, i64* %arrayidx6, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %B.addr.11, i64 1
   store i64 %0, i64* %B.addr.11, align 8
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 11
   br i1 %exitcond, label %for.body3, label %for.inc7
 
 for.inc7:                                         ; preds = %for.body3
-  %scevgep = getelementptr i64* %B.addr.04, i64 10
+  %scevgep = getelementptr i64, i64* %B.addr.04, i64 10
   %inc8 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc8, 11
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end9
@@ -109,21 +109,21 @@ for.body3:                                        ; preds = %for.body3.preheader
   %B.addr.12 = phi i64* [ %incdec.ptr, %for.body3 ], [ %B.addr.06, %for.body3.preheader ]
   %mul = mul nsw i64 %i.05, 10
   %add = add nsw i64 %mul, %j.03
-  %arrayidx = getelementptr inbounds i64* %A, i64 %add
+  %arrayidx = getelementptr inbounds i64, i64* %A, i64 %add
   store i64 0, i64* %arrayidx, align 8
   %mul4 = mul nsw i64 %i.05, 10
   %add5 = add nsw i64 %mul4, %j.03
   %sub = add nsw i64 %add5, -1
-  %arrayidx6 = getelementptr inbounds i64* %A, i64 %sub
-  %2 = load i64* %arrayidx6, align 8
-  %incdec.ptr = getelementptr inbounds i64* %B.addr.12, i64 1
+  %arrayidx6 = getelementptr inbounds i64, i64* %A, i64 %sub
+  %2 = load i64, i64* %arrayidx6, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %B.addr.12, i64 1
   store i64 %2, i64* %B.addr.12, align 8
   %inc = add nsw i64 %j.03, 1
   %exitcond = icmp eq i64 %inc, %1
   br i1 %exitcond, label %for.inc7.loopexit, label %for.body3
 
 for.inc7.loopexit:                                ; preds = %for.body3
-  %scevgep = getelementptr i64* %B.addr.06, i64 %m
+  %scevgep = getelementptr i64, i64* %B.addr.06, i64 %m
   br label %for.inc7
 
 for.inc7:                                         ; preds = %for.inc7.loopexit, %for.cond1.preheader
@@ -175,21 +175,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %B.addr.11 = phi i64* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ]
   %mul = mul nsw i64 %i.03, 10
   %add = add nsw i64 %mul, %j.02
-  %arrayidx = getelementptr inbounds i64* %A, i64 %add
+  %arrayidx = getelementptr inbounds i64, i64* %A, i64 %add
   store i64 0, i64* %arrayidx, align 8
   %mul4 = mul nsw i64 %i.03, 10
   %add5 = add nsw i64 %mul4, %j.02
   %add6 = add nsw i64 %add5, 100
-  %arrayidx7 = getelementptr inbounds i64* %A, i64 %add6
-  %0 = load i64* %arrayidx7, align 8
-  %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1
+  %arrayidx7 = getelementptr inbounds i64, i64* %A, i64 %add6
+  %0 = load i64, i64* %arrayidx7, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %B.addr.11, i64 1
   store i64 %0, i64* %B.addr.11, align 8
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 10
   br i1 %exitcond, label %for.body3, label %for.inc8
 
 for.inc8:                                         ; preds = %for.body3
-  %scevgep = getelementptr i64* %B.addr.04, i64 10
+  %scevgep = getelementptr i64, i64* %B.addr.04, i64 10
   %inc9 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc9, 10
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end10
@@ -234,21 +234,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %B.addr.11 = phi i64* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ]
   %mul = mul nsw i64 %i.03, 10
   %add = add nsw i64 %mul, %j.02
-  %arrayidx = getelementptr inbounds i64* %A, i64 %add
+  %arrayidx = getelementptr inbounds i64, i64* %A, i64 %add
   store i64 0, i64* %arrayidx, align 8
   %mul4 = mul nsw i64 %i.03, 10
   %add5 = add nsw i64 %mul4, %j.02
   %add6 = add nsw i64 %add5, 99
-  %arrayidx7 = getelementptr inbounds i64* %A, i64 %add6
-  %0 = load i64* %arrayidx7, align 8
-  %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1
+  %arrayidx7 = getelementptr inbounds i64, i64* %A, i64 %add6
+  %0 = load i64, i64* %arrayidx7, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %B.addr.11, i64 1
   store i64 %0, i64* %B.addr.11, align 8
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 10
   br i1 %exitcond, label %for.body3, label %for.inc8
 
 for.inc8:                                         ; preds = %for.body3
-  %scevgep = getelementptr i64* %B.addr.04, i64 10
+  %scevgep = getelementptr i64, i64* %B.addr.04, i64 10
   %inc9 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc9, 10
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end10
@@ -293,21 +293,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %B.addr.11 = phi i64* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ]
   %mul = mul nsw i64 %i.03, 10
   %add = add nsw i64 %mul, %j.02
-  %arrayidx = getelementptr inbounds i64* %A, i64 %add
+  %arrayidx = getelementptr inbounds i64, i64* %A, i64 %add
   store i64 0, i64* %arrayidx, align 8
   %mul4 = mul nsw i64 %i.03, 10
   %add5 = add nsw i64 %mul4, %j.02
   %sub = add nsw i64 %add5, -100
-  %arrayidx6 = getelementptr inbounds i64* %A, i64 %sub
-  %0 = load i64* %arrayidx6, align 8
-  %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1
+  %arrayidx6 = getelementptr inbounds i64, i64* %A, i64 %sub
+  %0 = load i64, i64* %arrayidx6, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %B.addr.11, i64 1
   store i64 %0, i64* %B.addr.11, align 8
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 10
   br i1 %exitcond, label %for.body3, label %for.inc7
 
 for.inc7:                                         ; preds = %for.body3
-  %scevgep = getelementptr i64* %B.addr.04, i64 10
+  %scevgep = getelementptr i64, i64* %B.addr.04, i64 10
   %inc8 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc8, 10
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end9
@@ -352,21 +352,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %B.addr.11 = phi i64* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ]
   %mul = mul nsw i64 %i.03, 10
   %add = add nsw i64 %mul, %j.02
-  %arrayidx = getelementptr inbounds i64* %A, i64 %add
+  %arrayidx = getelementptr inbounds i64, i64* %A, i64 %add
   store i64 0, i64* %arrayidx, align 8
   %mul4 = mul nsw i64 %i.03, 10
   %add5 = add nsw i64 %mul4, %j.02
   %sub = add nsw i64 %add5, -99
-  %arrayidx6 = getelementptr inbounds i64* %A, i64 %sub
-  %0 = load i64* %arrayidx6, align 8
-  %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1
+  %arrayidx6 = getelementptr inbounds i64, i64* %A, i64 %sub
+  %0 = load i64, i64* %arrayidx6, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %B.addr.11, i64 1
   store i64 %0, i64* %B.addr.11, align 8
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 10
   br i1 %exitcond, label %for.body3, label %for.inc7
 
 for.inc7:                                         ; preds = %for.body3
-  %scevgep = getelementptr i64* %B.addr.04, i64 10
+  %scevgep = getelementptr i64, i64* %B.addr.04, i64 10
   %inc8 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc8, 10
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end9
@@ -411,21 +411,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %B.addr.11 = phi i64* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ]
   %mul = mul nsw i64 %i.03, 10
   %add = add nsw i64 %mul, %j.02
-  %arrayidx = getelementptr inbounds i64* %A, i64 %add
+  %arrayidx = getelementptr inbounds i64, i64* %A, i64 %add
   store i64 0, i64* %arrayidx, align 8
   %mul4 = mul nsw i64 %i.03, 10
   %add5 = add nsw i64 %mul4, %j.02
   %add6 = add nsw i64 %add5, 9
-  %arrayidx7 = getelementptr inbounds i64* %A, i64 %add6
-  %0 = load i64* %arrayidx7, align 8
-  %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1
+  %arrayidx7 = getelementptr inbounds i64, i64* %A, i64 %add6
+  %0 = load i64, i64* %arrayidx7, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %B.addr.11, i64 1
   store i64 %0, i64* %B.addr.11, align 8
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 10
   br i1 %exitcond, label %for.body3, label %for.inc8
 
 for.inc8:                                         ; preds = %for.body3
-  %scevgep = getelementptr i64* %B.addr.04, i64 10
+  %scevgep = getelementptr i64, i64* %B.addr.04, i64 10
   %inc9 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc9, 10
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end10
@@ -470,21 +470,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %B.addr.11 = phi i64* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ]
   %mul = mul nsw i64 %i.03, 10
   %add = add nsw i64 %mul, %j.02
-  %arrayidx = getelementptr inbounds i64* %A, i64 %add
+  %arrayidx = getelementptr inbounds i64, i64* %A, i64 %add
   store i64 0, i64* %arrayidx, align 8
   %mul4 = mul nsw i64 %i.03, 10
   %add5 = add nsw i64 %mul4, %j.02
   %add6 = add nsw i64 %add5, 10
-  %arrayidx7 = getelementptr inbounds i64* %A, i64 %add6
-  %0 = load i64* %arrayidx7, align 8
-  %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1
+  %arrayidx7 = getelementptr inbounds i64, i64* %A, i64 %add6
+  %0 = load i64, i64* %arrayidx7, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %B.addr.11, i64 1
   store i64 %0, i64* %B.addr.11, align 8
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 10
   br i1 %exitcond, label %for.body3, label %for.inc8
 
 for.inc8:                                         ; preds = %for.body3
-  %scevgep = getelementptr i64* %B.addr.04, i64 10
+  %scevgep = getelementptr i64, i64* %B.addr.04, i64 10
   %inc9 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc9, 10
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end10
@@ -529,21 +529,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %B.addr.11 = phi i64* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ]
   %mul = mul nsw i64 %i.03, 10
   %add = add nsw i64 %mul, %j.02
-  %arrayidx = getelementptr inbounds i64* %A, i64 %add
+  %arrayidx = getelementptr inbounds i64, i64* %A, i64 %add
   store i64 0, i64* %arrayidx, align 8
   %mul4 = mul nsw i64 %i.03, 10
   %add5 = add nsw i64 %mul4, %j.02
   %add6 = add nsw i64 %add5, 11
-  %arrayidx7 = getelementptr inbounds i64* %A, i64 %add6
-  %0 = load i64* %arrayidx7, align 8
-  %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1
+  %arrayidx7 = getelementptr inbounds i64, i64* %A, i64 %add6
+  %0 = load i64, i64* %arrayidx7, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %B.addr.11, i64 1
   store i64 %0, i64* %B.addr.11, align 8
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 10
   br i1 %exitcond, label %for.body3, label %for.inc8
 
 for.inc8:                                         ; preds = %for.body3
-  %scevgep = getelementptr i64* %B.addr.04, i64 10
+  %scevgep = getelementptr i64, i64* %B.addr.04, i64 10
   %inc9 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc9, 10
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end10
@@ -589,21 +589,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %mul = mul nsw i64 %i.03, 30
   %mul4 = mul nsw i64 %j.02, 500
   %add = add nsw i64 %mul, %mul4
-  %arrayidx = getelementptr inbounds i64* %A, i64 %add
+  %arrayidx = getelementptr inbounds i64, i64* %A, i64 %add
   store i64 0, i64* %arrayidx, align 8
   %0 = mul i64 %j.02, -500
   %sub = add i64 %i.03, %0
   %add6 = add nsw i64 %sub, 11
-  %arrayidx7 = getelementptr inbounds i64* %A, i64 %add6
-  %1 = load i64* %arrayidx7, align 8
-  %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1
+  %arrayidx7 = getelementptr inbounds i64, i64* %A, i64 %add6
+  %1 = load i64, i64* %arrayidx7, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %B.addr.11, i64 1
   store i64 %1, i64* %B.addr.11, align 8
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 20
   br i1 %exitcond, label %for.body3, label %for.inc8
 
 for.inc8:                                         ; preds = %for.body3
-  %scevgep = getelementptr i64* %B.addr.04, i64 20
+  %scevgep = getelementptr i64, i64* %B.addr.04, i64 20
   %inc9 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc9, 20
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end10
@@ -648,21 +648,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %B.addr.11 = phi i64* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ]
   %mul = mul nsw i64 %j.02, 500
   %add = add nsw i64 %i.03, %mul
-  %arrayidx = getelementptr inbounds i64* %A, i64 %add
+  %arrayidx = getelementptr inbounds i64, i64* %A, i64 %add
   store i64 0, i64* %arrayidx, align 8
   %0 = mul i64 %j.02, -500
   %sub = add i64 %i.03, %0
   %add5 = add nsw i64 %sub, 11
-  %arrayidx6 = getelementptr inbounds i64* %A, i64 %add5
-  %1 = load i64* %arrayidx6, align 8
-  %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1
+  %arrayidx6 = getelementptr inbounds i64, i64* %A, i64 %add5
+  %1 = load i64, i64* %arrayidx6, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %B.addr.11, i64 1
   store i64 %1, i64* %B.addr.11, align 8
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 20
   br i1 %exitcond, label %for.body3, label %for.inc7
 
 for.inc7:                                         ; preds = %for.body3
-  %scevgep = getelementptr i64* %B.addr.04, i64 20
+  %scevgep = getelementptr i64, i64* %B.addr.04, i64 20
   %inc8 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc8, 20
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end9
@@ -707,21 +707,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %B.addr.11 = phi i64* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ]
   %mul = mul nsw i64 %i.03, 300
   %add = add nsw i64 %mul, %j.02
-  %arrayidx = getelementptr inbounds i64* %A, i64 %add
+  %arrayidx = getelementptr inbounds i64, i64* %A, i64 %add
   store i64 0, i64* %arrayidx, align 8
   %mul4 = mul nsw i64 %i.03, 250
   %sub = sub nsw i64 %mul4, %j.02
   %add5 = add nsw i64 %sub, 11
-  %arrayidx6 = getelementptr inbounds i64* %A, i64 %add5
-  %0 = load i64* %arrayidx6, align 8
-  %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1
+  %arrayidx6 = getelementptr inbounds i64, i64* %A, i64 %add5
+  %0 = load i64, i64* %arrayidx6, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %B.addr.11, i64 1
   store i64 %0, i64* %B.addr.11, align 8
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 20
   br i1 %exitcond, label %for.body3, label %for.inc7
 
 for.inc7:                                         ; preds = %for.body3
-  %scevgep = getelementptr i64* %B.addr.04, i64 20
+  %scevgep = getelementptr i64, i64* %B.addr.04, i64 20
   %inc8 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc8, 20
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end9
@@ -766,21 +766,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %B.addr.11 = phi i64* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ]
   %mul = mul nsw i64 %i.03, 100
   %add = add nsw i64 %mul, %j.02
-  %arrayidx = getelementptr inbounds i64* %A, i64 %add
+  %arrayidx = getelementptr inbounds i64, i64* %A, i64 %add
   store i64 0, i64* %arrayidx, align 8
   %mul4 = mul nsw i64 %i.03, 100
   %sub = sub nsw i64 %mul4, %j.02
   %add5 = add nsw i64 %sub, 11
-  %arrayidx6 = getelementptr inbounds i64* %A, i64 %add5
-  %0 = load i64* %arrayidx6, align 8
-  %incdec.ptr = getelementptr inbounds i64* %B.addr.11, i64 1
+  %arrayidx6 = getelementptr inbounds i64, i64* %A, i64 %add5
+  %0 = load i64, i64* %arrayidx6, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %B.addr.11, i64 1
   store i64 %0, i64* %B.addr.11, align 8
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 20
   br i1 %exitcond, label %for.body3, label %for.inc7
 
 for.inc7:                                         ; preds = %for.body3
-  %scevgep = getelementptr i64* %B.addr.04, i64 20
+  %scevgep = getelementptr i64, i64* %B.addr.04, i64 20
   %inc8 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc8, 20
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end9
diff --git a/test/Analysis/DependenceAnalysis/Constraints.ll b/test/Analysis/DependenceAnalysis/Constraints.ll
new file mode 100644
index 000000000000..42dfac767a73
--- /dev/null
+++ b/test/Analysis/DependenceAnalysis/Constraints.ll
@@ -0,0 +1,103 @@
+; RUN: opt < %s -analyze -basicaa -da
+;; Check that this code doesn't abort. Test case is reduced version of lnt Polybench benchmark test case dynprog.
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+@sum_c = common global [10 x [10 x [10 x i32]]] zeroinitializer
+@c = common global [10 x [10 x i32]] zeroinitializer
+@W = common global [10 x [10 x i32]] zeroinitializer
+@out_l = common global i32 0
+
+; Function Attrs: nounwind uwtable
+define void @dep_constraint_crash_test(i32 %M, i32 %N) {
+  %1 = icmp sgt i32 %N, 0
+  br i1 %1, label %.preheader.lr.ph, label %35
+
+.preheader.lr.ph:                                 ; preds = %0
+  %2 = add nsw i32 %M, -2
+  %3 = icmp slt i32 %M, 2
+  %4 = add nsw i32 %M, -1
+  %5 = sext i32 %4 to i64
+  %6 = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* @c, i64 0, i64 0, i64 %5
+  %7 = add nsw i32 %M, -1
+  %out_l.promoted = load i32, i32* @out_l
+  %8 = sext i32 %7 to i64
+  %9 = sext i32 %2 to i64
+  br label %.preheader
+
+.preheader:                                       ; preds = %._crit_edge7, %.preheader.lr.ph
+  %10 = phi i32 [ %out_l.promoted, %.preheader.lr.ph ], [ %33, %._crit_edge7 ]
+  %iter.08 = phi i32 [ 0, %.preheader.lr.ph ], [ %34, %._crit_edge7 ]
+  br i1 %3, label %._crit_edge7, label %.lr.ph6
+
+.loopexit:                                        ; preds = %._crit_edge, %.lr.ph6
+  %11 = icmp slt i64 %indvars.iv23, %9
+  %indvars.iv.next18 = add nuw nsw i64 %indvars.iv17, 1
+  %indvars.iv.next14 = add nuw i32 %indvars.iv13, 1
+  br i1 %11, label %.lr.ph6, label %._crit_edge7
+
+.lr.ph6:                                          ; preds = %.preheader, %.loopexit
+  %indvars.iv23 = phi i64 [ %indvars.iv.next24, %.loopexit ], [ 0, %.preheader ]
+  %indvars.iv17 = phi i64 [ %indvars.iv.next18, %.loopexit ], [ 1, %.preheader ]
+  %indvars.iv13 = phi i32 [ %indvars.iv.next14, %.loopexit ], [ 1, %.preheader ]
+  %indvars.iv.next24 = add nuw nsw i64 %indvars.iv23, 1
+  %12 = icmp slt i64 %indvars.iv23, %8
+  br i1 %12, label %.lr.ph4, label %.loopexit
+
+.lr.ph4:                                          ; preds = %.lr.ph6, %._crit_edge
+  %indvars.iv19 = phi i64 [ %indvars.iv.next20, %._crit_edge ], [ %indvars.iv17, %.lr.ph6 ]
+  %indvars.iv15 = phi i32 [ %indvars.iv.next16, %._crit_edge ], [ %indvars.iv13, %.lr.ph6 ]
+  %13 = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* @sum_c, i64 0, i64 %indvars.iv23, i64 %indvars.iv19, i64 %indvars.iv23
+  store i32 0, i32* %13
+  %14 = add nsw i64 %indvars.iv19, -1
+  %15 = icmp slt i64 %indvars.iv23, %14
+  br i1 %15, label %.lr.ph, label %._crit_edge
+
+.lr.ph:                                           ; preds = %.lr.ph4, %.lr.ph
+  %indvars.iv11 = phi i64 [ %indvars.iv.next12, %.lr.ph ], [ %indvars.iv17, %.lr.ph4 ]
+  %16 = add nsw i64 %indvars.iv11, -1
+  %17 = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* @sum_c, i64 0, i64 %indvars.iv23, i64 %indvars.iv19, i64 %16
+  %18 = load i32, i32* %17
+  %19 = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* @c, i64 0, i64 %indvars.iv23, i64 %indvars.iv11
+  %20 = load i32, i32* %19
+  %21 = add nsw i32 %20, %18
+  %22 = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* @c, i64 0, i64 %indvars.iv11, i64 %indvars.iv19
+  %23 = load i32, i32* %22
+  %24 = add nsw i32 %21, %23
+  %25 = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* @sum_c, i64 0, i64 %indvars.iv23, i64 %indvars.iv19, i64 %indvars.iv11
+  store i32 %24, i32* %25
+  %indvars.iv.next12 = add nuw nsw i64 %indvars.iv11, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next12 to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %indvars.iv15
+  br i1 %exitcond, label %._crit_edge, label %.lr.ph
+
+._crit_edge:                                      ; preds = %.lr.ph, %.lr.ph4
+  %26 = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* @sum_c, i64 0, i64 %indvars.iv23, i64 %indvars.iv19, i64 %14
+  %27 = load i32, i32* %26
+  %28 = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* @W, i64 0, i64 %indvars.iv23, i64 %indvars.iv19
+  %29 = load i32, i32* %28
+  %30 = add nsw i32 %29, %27
+  %31 = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* @c, i64 0, i64 %indvars.iv23, i64 %indvars.iv19
+  store i32 %30, i32* %31
+  %indvars.iv.next16 = add nuw i32 %indvars.iv15, 1
+  %indvars.iv.next20 = add nuw nsw i64 %indvars.iv19, 1
+  %lftr.wideiv21 = trunc i64 %indvars.iv.next20 to i32
+  %exitcond22 = icmp eq i32 %lftr.wideiv21, %M
+  br i1 %exitcond22, label %.loopexit, label %.lr.ph4
+
+._crit_edge7:                                     ; preds = %.loopexit, %.preheader
+  %32 = load i32, i32* %6
+  %33 = add nsw i32 %10, %32
+  %34 = add nuw nsw i32 %iter.08, 1
+  %exitcond25 = icmp eq i32 %34, %N
+  br i1 %exitcond25, label %._crit_edge9, label %.preheader
+
+._crit_edge9:                                     ; preds = %._crit_edge7
+  store i32 %33, i32* @out_l
+  br label %35
+
+; <label>:35                                      ; preds = %._crit_edge9, %0
+  ret void
+}
+
diff --git a/test/Analysis/DependenceAnalysis/Coupled.ll b/test/Analysis/DependenceAnalysis/Coupled.ll
index 8c77849ae847..096add6e80be 100644
--- a/test/Analysis/DependenceAnalysis/Coupled.ll
+++ b/test/Analysis/DependenceAnalysis/Coupled.ll
@@ -24,13 +24,13 @@ for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
-  %arrayidx1 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02
+  %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %i.02
   store i32 %conv, i32* %arrayidx1, align 4
   %add = add nsw i64 %i.02, 9
   %add2 = add nsw i64 %i.02, 10
-  %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %add2, i64 %add
-  %0 = load i32* %arrayidx4, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %add2, i64 %add
+  %0 = load i32, i32* %arrayidx4, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 50
@@ -60,13 +60,13 @@ for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
-  %arrayidx1 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02
+  %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %i.02
   store i32 %conv, i32* %arrayidx1, align 4
   %add = add nsw i64 %i.02, 9
   %add2 = add nsw i64 %i.02, 9
-  %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %add2, i64 %add
-  %0 = load i32* %arrayidx4, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %add2, i64 %add
+  %0 = load i32, i32* %arrayidx4, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 50
@@ -100,11 +100,11 @@ for.body:                                         ; preds = %entry, %for.body
   %sub = add nsw i64 %mul, -6
   %mul1 = mul nsw i64 %i.02, 3
   %sub2 = add nsw i64 %mul1, -6
-  %arrayidx3 = getelementptr inbounds [100 x i32]* %A, i64 %sub2, i64 %sub
+  %arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %sub2, i64 %sub
   store i32 %conv, i32* %arrayidx3, align 4
-  %arrayidx5 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02
-  %0 = load i32* %arrayidx5, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx5 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %i.02
+  %0 = load i32, i32* %arrayidx5, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 50
@@ -138,11 +138,11 @@ for.body:                                         ; preds = %entry, %for.body
   %sub = add nsw i64 %mul, -5
   %mul1 = mul nsw i64 %i.02, 3
   %sub2 = add nsw i64 %mul1, -6
-  %arrayidx3 = getelementptr inbounds [100 x i32]* %A, i64 %sub2, i64 %sub
+  %arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %sub2, i64 %sub
   store i32 %conv, i32* %arrayidx3, align 4
-  %arrayidx5 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02
-  %0 = load i32* %arrayidx5, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx5 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %i.02
+  %0 = load i32, i32* %arrayidx5, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 50
@@ -177,11 +177,11 @@ for.body:                                         ; preds = %entry, %for.body
   %sub = sub nsw i64 %mul, %conv1
   %mul2 = mul nsw i64 %i.02, 3
   %sub3 = add nsw i64 %mul2, -6
-  %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %sub3, i64 %sub
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %sub3, i64 %sub
   store i32 %conv, i32* %arrayidx4, align 4
-  %arrayidx6 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02
-  %0 = load i32* %arrayidx6, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx6 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %i.02
+  %0 = load i32, i32* %arrayidx6, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 50
@@ -218,11 +218,11 @@ for.body:                                         ; preds = %entry, %for.body
   %conv3 = sext i32 %n to i64
   %sub4 = sub nsw i64 %mul2, %conv3
   %add = add nsw i64 %sub4, 1
-  %arrayidx5 = getelementptr inbounds [100 x i32]* %A, i64 %add, i64 %sub
+  %arrayidx5 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %add, i64 %sub
   store i32 %conv, i32* %arrayidx5, align 4
-  %arrayidx7 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02
-  %0 = load i32* %arrayidx7, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx7 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %i.02
+  %0 = load i32, i32* %arrayidx7, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 50
@@ -254,11 +254,11 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.02 to i32
   %mul = mul nsw i64 %i.02, 3
   %sub = add nsw i64 %mul, -6
-  %arrayidx1 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %sub
+  %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %sub
   store i32 %conv, i32* %arrayidx1, align 4
-  %arrayidx3 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02
-  %0 = load i32* %arrayidx3, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %i.02
+  %0 = load i32, i32* %arrayidx3, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 50
@@ -290,11 +290,11 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.02 to i32
   %mul = mul nsw i64 %i.02, 3
   %sub = add nsw i64 %mul, -5
-  %arrayidx1 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %sub
+  %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %sub
   store i32 %conv, i32* %arrayidx1, align 4
-  %arrayidx3 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02
-  %0 = load i32* %arrayidx3, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %i.02
+  %0 = load i32, i32* %arrayidx3, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 50
@@ -327,11 +327,11 @@ for.body:                                         ; preds = %entry, %for.body
   %sub = sub nsw i64 3, %i.02
   %mul = mul nsw i64 %i.02, 3
   %sub1 = add nsw i64 %mul, -18
-  %arrayidx2 = getelementptr inbounds [100 x i32]* %A, i64 %sub1, i64 %sub
+  %arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %sub1, i64 %sub
   store i32 %conv, i32* %arrayidx2, align 4
-  %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02
-  %0 = load i32* %arrayidx4, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %i.02
+  %0 = load i32, i32* %arrayidx4, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 16
@@ -364,11 +364,11 @@ for.body:                                         ; preds = %entry, %for.body
   %sub = sub nsw i64 2, %i.02
   %mul = mul nsw i64 %i.02, 3
   %sub1 = add nsw i64 %mul, -18
-  %arrayidx2 = getelementptr inbounds [100 x i32]* %A, i64 %sub1, i64 %sub
+  %arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %sub1, i64 %sub
   store i32 %conv, i32* %arrayidx2, align 4
-  %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02
-  %0 = load i32* %arrayidx4, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %i.02
+  %0 = load i32, i32* %arrayidx4, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 16
@@ -402,11 +402,11 @@ for.body:                                         ; preds = %entry, %for.body
   %sub = sub nsw i64 6, %i.02
   %mul = mul nsw i64 %i.02, 3
   %sub1 = add nsw i64 %mul, -18
-  %arrayidx2 = getelementptr inbounds [100 x i32]* %A, i64 %sub1, i64 %sub
+  %arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %sub1, i64 %sub
   store i32 %conv, i32* %arrayidx2, align 4
-  %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02
-  %0 = load i32* %arrayidx4, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %i.02
+  %0 = load i32, i32* %arrayidx4, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 16
@@ -440,11 +440,11 @@ for.body:                                         ; preds = %entry, %for.body
   %sub = sub nsw i64 18, %i.02
   %mul = mul nsw i64 %i.02, 3
   %sub1 = add nsw i64 %mul, -18
-  %arrayidx2 = getelementptr inbounds [100 x i32]* %A, i64 %sub1, i64 %sub
+  %arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %sub1, i64 %sub
   store i32 %conv, i32* %arrayidx2, align 4
-  %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02
-  %0 = load i32* %arrayidx4, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %i.02
+  %0 = load i32, i32* %arrayidx4, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 16
@@ -478,11 +478,11 @@ for.body:                                         ; preds = %entry, %for.body
   %sub = sub nsw i64 22, %i.02
   %mul = mul nsw i64 %i.02, 3
   %sub1 = add nsw i64 %mul, -18
-  %arrayidx2 = getelementptr inbounds [100 x i32]* %A, i64 %sub1, i64 %sub
+  %arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %sub1, i64 %sub
   store i32 %conv, i32* %arrayidx2, align 4
-  %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02
-  %0 = load i32* %arrayidx4, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %i.02
+  %0 = load i32, i32* %arrayidx4, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 13
@@ -515,11 +515,11 @@ for.body:                                         ; preds = %entry, %for.body
   %sub = sub nsw i64 22, %i.02
   %mul = mul nsw i64 %i.02, 3
   %sub1 = add nsw i64 %mul, -18
-  %arrayidx2 = getelementptr inbounds [100 x i32]* %A, i64 %sub1, i64 %sub
+  %arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %sub1, i64 %sub
   store i32 %conv, i32* %arrayidx2, align 4
-  %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %i.02, i64 %i.02
-  %0 = load i32* %arrayidx4, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.02, i64 %i.02
+  %0 = load i32, i32* %arrayidx4, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 12
@@ -552,11 +552,11 @@ for.body:                                         ; preds = %entry, %for.body
   %sub = sub nsw i64 18, %i.02
   %mul = mul nsw i64 %i.02, 3
   %sub1 = add nsw i64 %mul, -18
-  %arrayidx3 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 %sub1, i64 %sub, i64 %i.02
+  %arrayidx3 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %A, i64 %sub1, i64 %sub, i64 %i.02
   store i32 %conv, i32* %arrayidx3, align 4
-  %arrayidx6 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 %i.02, i64 %i.02, i64 %i.02
-  %0 = load i32* %arrayidx6, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx6 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %A, i64 %i.02, i64 %i.02, i64 %i.02
+  %0 = load i32, i32* %arrayidx6, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 100
@@ -589,11 +589,11 @@ for.body:                                         ; preds = %entry, %for.body
   %sub = sub nsw i64 22, %i.02
   %mul = mul nsw i64 %i.02, 3
   %sub1 = add nsw i64 %mul, -18
-  %arrayidx3 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 %sub1, i64 %sub, i64 %i.02
+  %arrayidx3 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %A, i64 %sub1, i64 %sub, i64 %i.02
   store i32 %conv, i32* %arrayidx3, align 4
-  %arrayidx6 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 %i.02, i64 %i.02, i64 %i.02
-  %0 = load i32* %arrayidx6, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx6 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %A, i64 %i.02, i64 %i.02, i64 %i.02
+  %0 = load i32, i32* %arrayidx6, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add nsw i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 100
diff --git a/test/Analysis/DependenceAnalysis/ExactRDIV.ll b/test/Analysis/DependenceAnalysis/ExactRDIV.ll
index 81f55161c0df..5b2488c1bc8e 100644
--- a/test/Analysis/DependenceAnalysis/ExactRDIV.ll
+++ b/test/Analysis/DependenceAnalysis/ExactRDIV.ll
@@ -26,7 +26,7 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.03 to i32
   %mul = shl nsw i64 %i.03, 2
   %add = add nsw i64 %mul, 10
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc, 10
@@ -40,9 +40,9 @@ for.body4:                                        ; preds = %for.body4.preheader
   %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ]
   %mul5 = shl nsw i64 %j.02, 1
   %add64 = or i64 %mul5, 1
-  %arrayidx7 = getelementptr inbounds i32* %A, i64 %add64
-  %0 = load i32* %arrayidx7, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx7 = getelementptr inbounds i32, i32* %A, i64 %add64
+  %0 = load i32, i32* %arrayidx7, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc9 = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc9, 10
@@ -74,7 +74,7 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.03 to i32
   %mul = mul nsw i64 %i.03, 11
   %sub = add nsw i64 %mul, -45
-  %arrayidx = getelementptr inbounds i32* %A, i64 %sub
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %sub
   store i32 %conv, i32* %arrayidx, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond4 = icmp ne i64 %inc, 5
@@ -86,9 +86,9 @@ for.body4.preheader:                              ; preds = %for.body
 for.body4:                                        ; preds = %for.body4.preheader, %for.body4
   %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ]
   %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ]
-  %arrayidx5 = getelementptr inbounds i32* %A, i64 %j.02
-  %0 = load i32* %arrayidx5, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx5 = getelementptr inbounds i32, i32* %A, i64 %j.02
+  %0 = load i32, i32* %arrayidx5, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc7 = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc7, 10
@@ -120,7 +120,7 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.03 to i32
   %mul = mul nsw i64 %i.03, 11
   %sub = add nsw i64 %mul, -45
-  %arrayidx = getelementptr inbounds i32* %A, i64 %sub
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %sub
   store i32 %conv, i32* %arrayidx, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond4 = icmp ne i64 %inc, 6
@@ -132,9 +132,9 @@ for.body4.preheader:                              ; preds = %for.body
 for.body4:                                        ; preds = %for.body4.preheader, %for.body4
   %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ]
   %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ]
-  %arrayidx5 = getelementptr inbounds i32* %A, i64 %j.02
-  %0 = load i32* %arrayidx5, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx5 = getelementptr inbounds i32, i32* %A, i64 %j.02
+  %0 = load i32, i32* %arrayidx5, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc7 = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc7, 10
@@ -166,7 +166,7 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.03 to i32
   %mul = mul nsw i64 %i.03, 11
   %sub = add nsw i64 %mul, -45
-  %arrayidx = getelementptr inbounds i32* %A, i64 %sub
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %sub
   store i32 %conv, i32* %arrayidx, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond4 = icmp ne i64 %inc, 5
@@ -178,9 +178,9 @@ for.body4.preheader:                              ; preds = %for.body
 for.body4:                                        ; preds = %for.body4.preheader, %for.body4
   %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ]
   %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ]
-  %arrayidx5 = getelementptr inbounds i32* %A, i64 %j.02
-  %0 = load i32* %arrayidx5, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx5 = getelementptr inbounds i32, i32* %A, i64 %j.02
+  %0 = load i32, i32* %arrayidx5, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc7 = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc7, 11
@@ -212,7 +212,7 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.03 to i32
   %mul = mul nsw i64 %i.03, 11
   %sub = add nsw i64 %mul, -45
-  %arrayidx = getelementptr inbounds i32* %A, i64 %sub
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %sub
   store i32 %conv, i32* %arrayidx, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond4 = icmp ne i64 %inc, 6
@@ -224,9 +224,9 @@ for.body4.preheader:                              ; preds = %for.body
 for.body4:                                        ; preds = %for.body4.preheader, %for.body4
   %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ]
   %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ]
-  %arrayidx5 = getelementptr inbounds i32* %A, i64 %j.02
-  %0 = load i32* %arrayidx5, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx5 = getelementptr inbounds i32, i32* %A, i64 %j.02
+  %0 = load i32, i32* %arrayidx5, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc7 = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc7, 11
@@ -258,7 +258,7 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.03 to i32
   %mul = mul nsw i64 %i.03, -11
   %add = add nsw i64 %mul, 45
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond4 = icmp ne i64 %inc, 5
@@ -271,9 +271,9 @@ for.body4:                                        ; preds = %for.body4.preheader
   %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ]
   %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ]
   %sub = sub nsw i64 0, %j.02
-  %arrayidx5 = getelementptr inbounds i32* %A, i64 %sub
-  %0 = load i32* %arrayidx5, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx5 = getelementptr inbounds i32, i32* %A, i64 %sub
+  %0 = load i32, i32* %arrayidx5, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc7 = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc7, 10
@@ -305,7 +305,7 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.03 to i32
   %mul = mul nsw i64 %i.03, -11
   %add = add nsw i64 %mul, 45
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond4 = icmp ne i64 %inc, 6
@@ -318,9 +318,9 @@ for.body4:                                        ; preds = %for.body4.preheader
   %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ]
   %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ]
   %sub = sub nsw i64 0, %j.02
-  %arrayidx5 = getelementptr inbounds i32* %A, i64 %sub
-  %0 = load i32* %arrayidx5, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx5 = getelementptr inbounds i32, i32* %A, i64 %sub
+  %0 = load i32, i32* %arrayidx5, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc7 = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc7, 10
@@ -352,7 +352,7 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.03 to i32
   %mul = mul nsw i64 %i.03, -11
   %add = add nsw i64 %mul, 45
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond4 = icmp ne i64 %inc, 5
@@ -365,9 +365,9 @@ for.body4:                                        ; preds = %for.body4.preheader
   %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ]
   %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ]
   %sub = sub nsw i64 0, %j.02
-  %arrayidx5 = getelementptr inbounds i32* %A, i64 %sub
-  %0 = load i32* %arrayidx5, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx5 = getelementptr inbounds i32, i32* %A, i64 %sub
+  %0 = load i32, i32* %arrayidx5, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc7 = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc7, 11
@@ -399,7 +399,7 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.03 to i32
   %mul = mul nsw i64 %i.03, -11
   %add = add nsw i64 %mul, 45
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond4 = icmp ne i64 %inc, 6
@@ -412,9 +412,9 @@ for.body4:                                        ; preds = %for.body4.preheader
   %j.02 = phi i64 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ]
   %B.addr.01 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ]
   %sub = sub nsw i64 0, %j.02
-  %arrayidx5 = getelementptr inbounds i32* %A, i64 %sub
-  %0 = load i32* %arrayidx5, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx5 = getelementptr inbounds i32, i32* %A, i64 %sub
+  %0 = load i32, i32* %arrayidx5, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc7 = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc7, 11
@@ -452,18 +452,18 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %conv = trunc i64 %i.03 to i32
   %mul = mul nsw i64 %i.03, 11
   %sub = sub nsw i64 %mul, %j.02
-  %arrayidx = getelementptr inbounds i32* %A, i64 %sub
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %sub
   store i32 %conv, i32* %arrayidx, align 4
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 45
-  %0 = load i32* %arrayidx4, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 45
+  %0 = load i32, i32* %arrayidx4, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 10
   br i1 %exitcond, label %for.body3, label %for.inc5
 
 for.inc5:                                         ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 10
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 10
   %inc6 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc6, 5
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end7
@@ -501,18 +501,18 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %conv = trunc i64 %i.03 to i32
   %mul = mul nsw i64 %i.03, 11
   %sub = sub nsw i64 %mul, %j.02
-  %arrayidx = getelementptr inbounds i32* %A, i64 %sub
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %sub
   store i32 %conv, i32* %arrayidx, align 4
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 45
-  %0 = load i32* %arrayidx4, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 45
+  %0 = load i32, i32* %arrayidx4, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 10
   br i1 %exitcond, label %for.body3, label %for.inc5
 
 for.inc5:                                         ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 10
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 10
   %inc6 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc6, 6
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end7
@@ -549,18 +549,18 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %conv = trunc i64 %i.03 to i32
   %mul = mul nsw i64 %i.03, 11
   %sub = sub nsw i64 %mul, %j.02
-  %arrayidx = getelementptr inbounds i32* %A, i64 %sub
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %sub
   store i32 %conv, i32* %arrayidx, align 4
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 45
-  %0 = load i32* %arrayidx4, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 45
+  %0 = load i32, i32* %arrayidx4, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 11
   br i1 %exitcond, label %for.body3, label %for.inc5
 
 for.inc5:                                         ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 11
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 11
   %inc6 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc6, 5
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end7
@@ -597,18 +597,18 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %conv = trunc i64 %i.03 to i32
   %mul = mul nsw i64 %i.03, 11
   %sub = sub nsw i64 %mul, %j.02
-  %arrayidx = getelementptr inbounds i32* %A, i64 %sub
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %sub
   store i32 %conv, i32* %arrayidx, align 4
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 45
-  %0 = load i32* %arrayidx4, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 45
+  %0 = load i32, i32* %arrayidx4, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 11
   br i1 %exitcond, label %for.body3, label %for.inc5
 
 for.inc5:                                         ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 11
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 11
   %inc6 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc6, 6
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end7
diff --git a/test/Analysis/DependenceAnalysis/ExactSIV.ll b/test/Analysis/DependenceAnalysis/ExactSIV.ll
index 586bbe5096d6..d84cd058718a 100644
--- a/test/Analysis/DependenceAnalysis/ExactSIV.ll
+++ b/test/Analysis/DependenceAnalysis/ExactSIV.ll
@@ -25,13 +25,13 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %add = add i64 %i.02, 10
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %mul = shl i64 %i.02, 1
   %add13 = or i64 %mul, 1
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %add13
-  %0 = load i32* %arrayidx2, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %add13
+  %0 = load i32, i32* %arrayidx2, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 10
@@ -63,13 +63,13 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.02 to i32
   %mul = shl i64 %i.02, 2
   %add = add i64 %mul, 10
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %mul1 = shl i64 %i.02, 1
   %add23 = or i64 %mul1, 1
-  %arrayidx3 = getelementptr inbounds i32* %A, i64 %add23
-  %0 = load i32* %arrayidx3, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx3 = getelementptr inbounds i32, i32* %A, i64 %add23
+  %0 = load i32, i32* %arrayidx3, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 10
@@ -100,12 +100,12 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = mul i64 %i.02, 6
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
   %add = add i64 %i.02, 60
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %add
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %add
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 10
@@ -136,12 +136,12 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = mul i64 %i.02, 6
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
   %add = add i64 %i.02, 60
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %add
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %add
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 11
@@ -172,12 +172,12 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = mul i64 %i.02, 6
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
   %add = add i64 %i.02, 60
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %add
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %add
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 12
@@ -208,12 +208,12 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = mul i64 %i.02, 6
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
   %add = add i64 %i.02, 60
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %add
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %add
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 13
@@ -244,12 +244,12 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = mul i64 %i.02, 6
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
   %add = add i64 %i.02, 60
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %add
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %add
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 18
@@ -280,12 +280,12 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = mul i64 %i.02, 6
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
   %add = add i64 %i.02, 60
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %add
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %add
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 19
@@ -316,12 +316,12 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = mul i64 %i.02, -6
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
   %sub1 = sub i64 -60, %i.02
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub1
-  %0 = load i32* %arrayidx2, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %sub1
+  %0 = load i32, i32* %arrayidx2, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 10
@@ -352,12 +352,12 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = mul i64 %i.02, -6
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
   %sub1 = sub i64 -60, %i.02
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub1
-  %0 = load i32* %arrayidx2, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %sub1
+  %0 = load i32, i32* %arrayidx2, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 11
@@ -388,12 +388,12 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = mul i64 %i.02, -6
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
   %sub1 = sub i64 -60, %i.02
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub1
-  %0 = load i32* %arrayidx2, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %sub1
+  %0 = load i32, i32* %arrayidx2, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 12
@@ -424,12 +424,12 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = mul i64 %i.02, -6
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
   %sub1 = sub i64 -60, %i.02
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub1
-  %0 = load i32* %arrayidx2, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %sub1
+  %0 = load i32, i32* %arrayidx2, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 13
@@ -460,12 +460,12 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = mul i64 %i.02, -6
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
   %sub1 = sub i64 -60, %i.02
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub1
-  %0 = load i32* %arrayidx2, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %sub1
+  %0 = load i32, i32* %arrayidx2, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 18
@@ -496,12 +496,12 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = mul i64 %i.02, -6
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
   %sub1 = sub i64 -60, %i.02
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub1
-  %0 = load i32* %arrayidx2, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %sub1
+  %0 = load i32, i32* %arrayidx2, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 19
diff --git a/test/Analysis/DependenceAnalysis/GCD.ll b/test/Analysis/DependenceAnalysis/GCD.ll
index 7eca18ed262c..81d05a10cf1c 100644
--- a/test/Analysis/DependenceAnalysis/GCD.ll
+++ b/test/Analysis/DependenceAnalysis/GCD.ll
@@ -43,21 +43,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %mul = shl nsw i64 %i.03, 1
   %mul4 = shl nsw i64 %j.02, 2
   %sub = sub nsw i64 %mul, %mul4
-  %arrayidx = getelementptr inbounds i32* %A, i64 %sub
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %sub
   store i32 %conv, i32* %arrayidx, align 4
   %mul5 = mul nsw i64 %i.03, 6
   %mul6 = shl nsw i64 %j.02, 3
   %add = add nsw i64 %mul5, %mul6
-  %arrayidx7 = getelementptr inbounds i32* %A, i64 %add
-  %0 = load i32* %arrayidx7, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx7 = getelementptr inbounds i32, i32* %A, i64 %add
+  %0 = load i32, i32* %arrayidx7, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body3, label %for.inc8
 
 for.inc8:                                         ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 100
   %inc9 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc9, 100
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end10
@@ -104,22 +104,22 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %mul = shl nsw i64 %i.03, 1
   %mul4 = shl nsw i64 %j.02, 2
   %sub = sub nsw i64 %mul, %mul4
-  %arrayidx = getelementptr inbounds i32* %A, i64 %sub
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %sub
   store i32 %conv, i32* %arrayidx, align 4
   %mul5 = mul nsw i64 %i.03, 6
   %mul6 = shl nsw i64 %j.02, 3
   %add = add nsw i64 %mul5, %mul6
   %add7 = or i64 %add, 1
-  %arrayidx8 = getelementptr inbounds i32* %A, i64 %add7
-  %0 = load i32* %arrayidx8, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx8 = getelementptr inbounds i32, i32* %A, i64 %add7
+  %0 = load i32, i32* %arrayidx8, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body3, label %for.inc9
 
 for.inc9:                                         ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 100
   %inc10 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc10, 100
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end11
@@ -167,21 +167,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %mul4 = shl nsw i64 %j.02, 2
   %sub = sub nsw i64 %mul, %mul4
   %add5 = or i64 %sub, 1
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add5
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add5
   store i32 %conv, i32* %arrayidx, align 4
   %mul5 = mul nsw i64 %i.03, 6
   %mul6 = shl nsw i64 %j.02, 3
   %add7 = add nsw i64 %mul5, %mul6
-  %arrayidx8 = getelementptr inbounds i32* %A, i64 %add7
-  %0 = load i32* %arrayidx8, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx8 = getelementptr inbounds i32, i32* %A, i64 %add7
+  %0 = load i32, i32* %arrayidx8, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body3, label %for.inc9
 
 for.inc9:                                         ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 100
   %inc10 = add nsw i64 %i.03, 1
   %exitcond6 = icmp ne i64 %inc10, 100
   br i1 %exitcond6, label %for.cond1.preheader, label %for.end11
@@ -227,21 +227,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %conv = trunc i64 %i.03 to i32
   %mul = shl nsw i64 %j.02, 1
   %add = add nsw i64 %i.03, %mul
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %mul4 = shl nsw i64 %j.02, 1
   %add5 = add nsw i64 %i.03, %mul4
   %sub = add nsw i64 %add5, -1
-  %arrayidx6 = getelementptr inbounds i32* %A, i64 %sub
-  %0 = load i32* %arrayidx6, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx6 = getelementptr inbounds i32, i32* %A, i64 %sub
+  %0 = load i32, i32* %arrayidx6, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body3, label %for.inc7
 
 for.inc7:                                         ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 100
   %inc8 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc8, 100
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end9
@@ -292,7 +292,7 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %mul6 = mul nsw i64 %M, 9
   %mul7 = mul nsw i64 %mul6, %N
   %add8 = add nsw i64 %add, %mul7
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add8
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add8
   store i32 %conv, i32* %arrayidx, align 4
   %mul9 = mul nsw i64 %i.03, 15
   %mul10 = mul nsw i64 %j.02, 20
@@ -302,16 +302,16 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %mul14 = mul nsw i64 %mul13, %M
   %sub = sub nsw i64 %add12, %mul14
   %add15 = add nsw i64 %sub, 4
-  %arrayidx16 = getelementptr inbounds i32* %A, i64 %add15
-  %0 = load i32* %arrayidx16, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx16 = getelementptr inbounds i32, i32* %A, i64 %add15
+  %0 = load i32, i32* %arrayidx16, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body3, label %for.inc17
 
 for.inc17:                                        ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 100
   %inc18 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc18, 100
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end19
@@ -362,7 +362,7 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %mul6 = mul nsw i64 %M, 9
   %mul7 = mul nsw i64 %mul6, %N
   %add8 = add nsw i64 %add, %mul7
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add8
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add8
   store i32 %conv, i32* %arrayidx, align 4
   %mul9 = mul nsw i64 %i.03, 15
   %mul10 = mul nsw i64 %j.02, 20
@@ -372,16 +372,16 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %mul14 = mul nsw i64 %mul13, %M
   %sub = sub nsw i64 %add12, %mul14
   %add15 = add nsw i64 %sub, 5
-  %arrayidx16 = getelementptr inbounds i32* %A, i64 %add15
-  %0 = load i32* %arrayidx16, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx16 = getelementptr inbounds i32, i32* %A, i64 %add15
+  %0 = load i32, i32* %arrayidx16, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body3, label %for.inc17
 
 for.inc17:                                        ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 100
   %inc18 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc18, 100
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end19
@@ -437,23 +437,23 @@ for.body3:                                        ; preds = %for.body3.preheader
   %mul4 = shl nsw i64 %i.06, 1
   %0 = mul nsw i64 %mul4, %n
   %arrayidx.sum = add i64 %0, %mul
-  %arrayidx5 = getelementptr inbounds i32* %A, i64 %arrayidx.sum
+  %arrayidx5 = getelementptr inbounds i32, i32* %A, i64 %arrayidx.sum
   store i32 %conv, i32* %arrayidx5, align 4
   %mul6 = mul nsw i64 %j.03, 6
   %add7 = or i64 %mul6, 1
   %mul7 = shl nsw i64 %i.06, 3
   %1 = mul nsw i64 %mul7, %n
   %arrayidx8.sum = add i64 %1, %add7
-  %arrayidx9 = getelementptr inbounds i32* %A, i64 %arrayidx8.sum
-  %2 = load i32* %arrayidx9, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.12, i64 1
+  %arrayidx9 = getelementptr inbounds i32, i32* %A, i64 %arrayidx8.sum
+  %2 = load i32, i32* %arrayidx9, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.12, i64 1
   store i32 %2, i32* %B.addr.12, align 4
   %inc = add nsw i64 %j.03, 1
   %exitcond = icmp ne i64 %inc, %n
   br i1 %exitcond, label %for.body3, label %for.inc10.loopexit
 
 for.inc10.loopexit:                               ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.05, i64 %n
+  %scevgep = getelementptr i32, i32* %B.addr.05, i64 %n
   br label %for.inc10
 
 for.inc10:                                        ; preds = %for.inc10.loopexit, %for.cond1.preheader
@@ -523,7 +523,7 @@ for.body3:                                        ; preds = %for.body3.preheader
   %idxprom5 = sext i32 %mul4 to i64
   %6 = mul nsw i64 %idxprom5, %0
   %arrayidx.sum = add i64 %6, %idxprom
-  %arrayidx6 = getelementptr inbounds i32* %A, i64 %arrayidx.sum
+  %arrayidx6 = getelementptr inbounds i32, i32* %A, i64 %arrayidx.sum
   %7 = trunc i64 %indvars.iv8 to i32
   store i32 %7, i32* %arrayidx6, align 4
   %8 = trunc i64 %indvars.iv to i32
@@ -535,9 +535,9 @@ for.body3:                                        ; preds = %for.body3.preheader
   %idxprom10 = sext i32 %mul9 to i64
   %10 = mul nsw i64 %idxprom10, %0
   %arrayidx11.sum = add i64 %10, %idxprom8
-  %arrayidx12 = getelementptr inbounds i32* %A, i64 %arrayidx11.sum
-  %11 = load i32* %arrayidx12, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.12, i64 1
+  %arrayidx12 = getelementptr inbounds i32, i32* %A, i64 %arrayidx11.sum
+  %11 = load i32, i32* %arrayidx12, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.12, i64 1
   store i32 %11, i32* %B.addr.12, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -545,7 +545,7 @@ for.body3:                                        ; preds = %for.body3.preheader
   br i1 %exitcond, label %for.body3, label %for.inc13.loopexit
 
 for.inc13.loopexit:                               ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.05, i64 %3
+  %scevgep = getelementptr i32, i32* %B.addr.05, i64 %3
   br label %for.inc13
 
 for.inc13:                                        ; preds = %for.inc13.loopexit, %for.cond1.preheader
@@ -613,7 +613,7 @@ for.body3:                                        ; preds = %for.body3.preheader
   %mul5 = shl nsw i32 %3, 2
   %add = add nsw i32 %mul4, %mul5
   %idxprom = sext i32 %add to i64
-  %arrayidx = getelementptr inbounds i32* %A, i64 %idxprom
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %idxprom
   store i32 %i.06, i32* %arrayidx, align 4
   %mul6 = shl nsw i32 %n, 3
   %mul7 = mul nsw i32 %mul6, %i.06
@@ -622,9 +622,9 @@ for.body3:                                        ; preds = %for.body3.preheader
   %add9 = add nsw i32 %mul7, %mul8
   %add10 = or i32 %add9, 1
   %idxprom11 = sext i32 %add10 to i64
-  %arrayidx12 = getelementptr inbounds i32* %A, i64 %idxprom11
-  %5 = load i32* %arrayidx12, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.12, i64 1
+  %arrayidx12 = getelementptr inbounds i32, i32* %A, i64 %idxprom11
+  %5 = load i32, i32* %arrayidx12, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.12, i64 1
   store i32 %5, i32* %B.addr.12, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -632,7 +632,7 @@ for.body3:                                        ; preds = %for.body3.preheader
   br i1 %exitcond, label %for.body3, label %for.inc13.loopexit
 
 for.inc13.loopexit:                               ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.05, i64 %2
+  %scevgep = getelementptr i32, i32* %B.addr.05, i64 %2
   br label %for.inc13
 
 for.inc13:                                        ; preds = %for.inc13.loopexit, %for.cond1.preheader
@@ -702,7 +702,7 @@ for.body3:                                        ; preds = %for.body3.preheader
   %idxprom5 = zext i32 %mul4 to i64
   %6 = mul nsw i64 %idxprom5, %0
   %arrayidx.sum = add i64 %6, %idxprom
-  %arrayidx6 = getelementptr inbounds i32* %A, i64 %arrayidx.sum
+  %arrayidx6 = getelementptr inbounds i32, i32* %A, i64 %arrayidx.sum
   %7 = trunc i64 %indvars.iv8 to i32
   store i32 %7, i32* %arrayidx6, align 4
   %8 = trunc i64 %indvars.iv to i32
@@ -714,9 +714,9 @@ for.body3:                                        ; preds = %for.body3.preheader
   %idxprom10 = zext i32 %mul9 to i64
   %10 = mul nsw i64 %idxprom10, %0
   %arrayidx11.sum = add i64 %10, %idxprom8
-  %arrayidx12 = getelementptr inbounds i32* %A, i64 %arrayidx11.sum
-  %11 = load i32* %arrayidx12, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.12, i64 1
+  %arrayidx12 = getelementptr inbounds i32, i32* %A, i64 %arrayidx11.sum
+  %11 = load i32, i32* %arrayidx12, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.12, i64 1
   store i32 %11, i32* %B.addr.12, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -724,7 +724,7 @@ for.body3:                                        ; preds = %for.body3.preheader
   br i1 %exitcond, label %for.body3, label %for.inc13.loopexit
 
 for.inc13.loopexit:                               ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.05, i64 %3
+  %scevgep = getelementptr i32, i32* %B.addr.05, i64 %3
   br label %for.inc13
 
 for.inc13:                                        ; preds = %for.inc13.loopexit, %for.cond1.preheader
diff --git a/test/Analysis/DependenceAnalysis/Invariant.ll b/test/Analysis/DependenceAnalysis/Invariant.ll
index 202d8e2d68db..9fdb4d9b0c46 100644
--- a/test/Analysis/DependenceAnalysis/Invariant.ll
+++ b/test/Analysis/DependenceAnalysis/Invariant.ll
@@ -19,10 +19,10 @@ for.cond1.preheader:
 for.body3:
   %j.02 = phi i32 [ 0, %for.cond1.preheader ], [ %add8, %for.body3 ]
   %res.11 = phi float [ %res.03, %for.cond1.preheader ], [ %add.res.1, %for.body3 ]
-  %arrayidx4 = getelementptr inbounds [40 x float]* %rr, i32 %j.02, i32 %j.02
-  %0 = load float* %arrayidx4, align 4
-  %arrayidx6 = getelementptr inbounds [40 x float]* %rr, i32 %i.04, i32 %j.02
-  %1 = load float* %arrayidx6, align 4
+  %arrayidx4 = getelementptr inbounds [40 x float], [40 x float]* %rr, i32 %j.02, i32 %j.02
+  %0 = load float, float* %arrayidx4, align 4
+  %arrayidx6 = getelementptr inbounds [40 x float], [40 x float]* %rr, i32 %i.04, i32 %j.02
+  %1 = load float, float* %arrayidx6, align 4
   %add = fadd float %0, %1
   %cmp7 = fcmp ogt float %add, %g
   %add.res.1 = select i1 %cmp7, float %add, float %res.11
diff --git a/test/Analysis/DependenceAnalysis/NonCanonicalizedSubscript.ll b/test/Analysis/DependenceAnalysis/NonCanonicalizedSubscript.ll
index 95e5e52bc2a7..1b47341ed4d6 100644
--- a/test/Analysis/DependenceAnalysis/NonCanonicalizedSubscript.ll
+++ b/test/Analysis/DependenceAnalysis/NonCanonicalizedSubscript.ll
@@ -26,9 +26,9 @@ for.body:
 ; DELIN: da analyze - anti [=|<]!
 ; DELIN: da analyze - none!
   %i = phi i64 [ 0, %entry ], [ %i.inc, %for.body ]
-  %a.addr = getelementptr [100 x [100 x i32]]* %a, i64 0, i64 %i, i64 %i
-  %a.addr.2 = getelementptr [100 x [100 x i32]]* %a, i64 0, i64 %i, i32 5
-  %0 = load i32* %a.addr, align 4
+  %a.addr = getelementptr [100 x [100 x i32]], [100 x [100 x i32]]* %a, i64 0, i64 %i, i64 %i
+  %a.addr.2 = getelementptr [100 x [100 x i32]], [100 x [100 x i32]]* %a, i64 0, i64 %i, i32 5
+  %0 = load i32, i32* %a.addr, align 4
   %1 = add i32 %0, 1
   store i32 %1, i32* %a.addr.2, align 4
   %i.inc = add nsw i64 %i, 1
diff --git a/test/Analysis/DependenceAnalysis/PR21585.ll b/test/Analysis/DependenceAnalysis/PR21585.ll
new file mode 100644
index 000000000000..bb62c68918f7
--- /dev/null
+++ b/test/Analysis/DependenceAnalysis/PR21585.ll
@@ -0,0 +1,105 @@
+; RUN: opt < %s -analyze -basicaa -globalsmodref-aa -da | FileCheck %s
+define void @i32_subscript(i32* %a) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i32 [ 0, %entry ], [ %i.inc, %for.body ]
+  %a.addr = getelementptr i32, i32* %a, i32 %i
+  %a.addr.2 = getelementptr i32, i32* %a, i32 5
+  %0 = load i32, i32* %a.addr, align 4
+  %1 = add i32 %0, 1
+  store i32 %1, i32* %a.addr.2, align 4
+  %i.inc = add nsw i32 %i, 1
+  %i.inc.ext = sext i32 %i to i64
+  %exitcond = icmp ne i64 %i.inc.ext, 100
+  br i1 %exitcond, label %for.body, label %for.end
+
+for.end:
+  ret void
+}
+; CHECK: none
+; CHECK: anti
+; CHECK: output
+
+
+; Test for a bug, which caused an assert in ScalarEvolution because
+; the Dependence Analyzer attempted to zero extend a type to a smaller
+; type.
+
+; void t(unsigned int *a, unsigned int n) {
+;   for (unsigned int i = 0; i != n; i++) {
+;     a[(unsigned short)i] = g;
+;  }}
+
+@g = common global i32 0, align 4
+
+define void @t(i32* noalias %a, i32 %n) nounwind {
+entry:
+  %cmp1 = icmp eq i32 %n, 0
+  br i1 %cmp1, label %for.end, label %for.body
+
+for.body:
+  %i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
+  %0 = load i32, i32* @g, align 4
+  %idxprom = and i32 %i.02, 65535
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %idxprom
+  store i32 %0, i32* %arrayidx, align 4
+  %inc = add i32 %i.02, 1
+  %cmp = icmp eq i32 %inc, %n
+  br i1 %cmp, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+; CHECK: input
+; CHECK: none
+; CHECK: output
+
+define void @i16_wrap(i64* %a) {
+entry:
+  br label %for.body
+for.body:
+  %i = phi i64 [0, %entry], [%i.inc, %for.inc]
+  %i.tr = trunc i64 %i to i16
+  %idx = getelementptr i64, i64* %a, i16 %i.tr
+  %0 = load i64, i64* %idx
+  %1 = add i64 %0, 1
+store i64 %1, i64* %idx
+  br label %for.inc
+
+for.inc:
+  %i.inc = add nuw i64 %i, 1
+  %cmp = icmp ult i64 %i.inc, 17179869184
+  br i1 %cmp, label %for.body, label %for.end
+for.end:
+  ret void
+}
+; CHECK: input
+; CHECK: anti
+; CHECK: output
+
+define void @i8_stride_wrap(i32* noalias %a, i32* noalias %b) {
+entry:
+  br label %for.body
+for.body:
+  %i = phi i32 [1,%entry], [%i.inc, %for.inc]
+  %i.tr = trunc i32 %i to i8
+  %idx = getelementptr i32, i32* %a, i8 %i.tr
+  %idx.2 = getelementptr i32, i32* %b, i32 %i
+  %0 = load i32, i32* %idx, align 4
+  %1 = add i32 %0, 1
+  store i32 %1, i32* %idx.2, align 4
+  br label %for.inc
+
+for.inc:
+  %i.inc = add nsw i32 %i, 256
+  %exitcond = icmp ult i32 %i, 65536
+  br i1 %exitcond, label %for.body, label %for.end
+
+for.end:
+  ret void
+}
+; CHECK: input
+; CHECK: none
+; CHECK: none
diff --git a/test/Analysis/DependenceAnalysis/Preliminary.ll b/test/Analysis/DependenceAnalysis/Preliminary.ll
index f36b85a5951e..d6500cc03367 100644
--- a/test/Analysis/DependenceAnalysis/Preliminary.ll
+++ b/test/Analysis/DependenceAnalysis/Preliminary.ll
@@ -17,8 +17,8 @@ entry:
 ; CHECK: da analyze - confused!
 ; CHECK: da analyze - none!
 
-  %arrayidx1 = getelementptr inbounds i32* %B, i64 1
-  %0 = load i32* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %B, i64 1
+  %0 = load i32, i32* %arrayidx1, align 4
   ret i32 %0
 }
 
@@ -35,8 +35,8 @@ entry:
 ; CHECK: da analyze - none!
 ; CHECK: da analyze - none!
 
-  %arrayidx1 = getelementptr inbounds i32* %B, i64 1
-  %0 = load i32* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %B, i64 1
+  %0 = load i32, i32* %arrayidx1, align 4
   ret i32 %0
 }
 
@@ -84,7 +84,7 @@ for.body6.preheader:                              ; preds = %for.cond4.preheader
 
 for.body6:                                        ; preds = %for.body6.preheader, %for.body6
   %k.02 = phi i64 [ %inc, %for.body6 ], [ 0, %for.body6.preheader ]
-  %arrayidx8 = getelementptr inbounds [100 x [100 x i64]]* %A, i64 %i.011, i64 %j.07, i64 %k.02
+  %arrayidx8 = getelementptr inbounds [100 x [100 x i64]], [100 x [100 x i64]]* %A, i64 %i.011, i64 %j.07, i64 %k.02
   store i64 %i.011, i64* %arrayidx8, align 8
   %inc = add nsw i64 %k.02, 1
   %exitcond13 = icmp ne i64 %inc, %n
@@ -106,16 +106,16 @@ for.body12:                                       ; preds = %for.body12.preheade
   %add = add nsw i64 %k9.05, 1
   %add13 = add nsw i64 %j.07, 2
   %add14 = add nsw i64 %i.011, 3
-  %arrayidx17 = getelementptr inbounds [100 x [100 x i64]]* %A, i64 %add14, i64 %add13, i64 %add
-  %0 = load i64* %arrayidx17, align 8
-  %incdec.ptr = getelementptr inbounds i64* %B.addr.24, i64 1
+  %arrayidx17 = getelementptr inbounds [100 x [100 x i64]], [100 x [100 x i64]]* %A, i64 %add14, i64 %add13, i64 %add
+  %0 = load i64, i64* %arrayidx17, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %B.addr.24, i64 1
   store i64 %0, i64* %B.addr.24, align 8
   %inc19 = add nsw i64 %k9.05, 1
   %exitcond = icmp ne i64 %inc19, %n
   br i1 %exitcond, label %for.body12, label %for.inc21.loopexit
 
 for.inc21.loopexit:                               ; preds = %for.body12
-  %scevgep = getelementptr i64* %B.addr.18, i64 %n
+  %scevgep = getelementptr i64, i64* %B.addr.18, i64 %n
   br label %for.inc21
 
 for.inc21:                                        ; preds = %for.inc21.loopexit, %for.cond10.loopexit
@@ -281,7 +281,7 @@ for.body33:                                       ; preds = %for.body33.preheade
   %add3547 = or i64 %mul, 1
   %sub = add nsw i64 %k.037, -1
   %sub36 = add nsw i64 %i.045, -3
-  %arrayidx43 = getelementptr inbounds [100 x [100 x [100 x [100 x [100 x [100 x [100 x i64]]]]]]]* %A, i64 %sub36, i64 %j.041, i64 2, i64 %sub, i64 %add3547, i64 %m.029, i64 %add34, i64 %add
+  %arrayidx43 = getelementptr inbounds [100 x [100 x [100 x [100 x [100 x [100 x [100 x i64]]]]]]], [100 x [100 x [100 x [100 x [100 x [100 x [100 x i64]]]]]]]* %A, i64 %sub36, i64 %j.041, i64 2, i64 %sub, i64 %add3547, i64 %m.029, i64 %add34, i64 %add
   store i64 %i.045, i64* %arrayidx43, align 8
   %add44 = add nsw i64 %t.03, 2
   %add45 = add nsw i64 %n, 1
@@ -289,16 +289,16 @@ for.body33:                                       ; preds = %for.body33.preheade
   %sub47 = add nsw i64 %mul46, -1
   %sub48 = sub nsw i64 1, %k.037
   %add49 = add nsw i64 %i.045, 3
-  %arrayidx57 = getelementptr inbounds [100 x [100 x [100 x [100 x [100 x [100 x [100 x i64]]]]]]]* %A, i64 %add49, i64 2, i64 %u.06, i64 %sub48, i64 %sub47, i64 %o.025, i64 %add45, i64 %add44
-  %0 = load i64* %arrayidx57, align 8
-  %incdec.ptr = getelementptr inbounds i64* %B.addr.112, i64 1
+  %arrayidx57 = getelementptr inbounds [100 x [100 x [100 x [100 x [100 x [100 x [100 x i64]]]]]]], [100 x [100 x [100 x [100 x [100 x [100 x [100 x i64]]]]]]]* %A, i64 %add49, i64 2, i64 %u.06, i64 %sub48, i64 %sub47, i64 %o.025, i64 %add45, i64 %add44
+  %0 = load i64, i64* %arrayidx57, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %B.addr.112, i64 1
   store i64 %0, i64* %B.addr.112, align 8
   %inc = add nsw i64 %t.03, 1
   %exitcond = icmp ne i64 %inc, %n
   br i1 %exitcond, label %for.body33, label %for.inc58.loopexit
 
 for.inc58.loopexit:                               ; preds = %for.body33
-  %scevgep = getelementptr i64* %B.addr.105, i64 %n
+  %scevgep = getelementptr i64, i64* %B.addr.105, i64 %n
   br label %for.inc58
 
 for.inc58:                                        ; preds = %for.inc58.loopexit, %for.cond31.preheader
@@ -441,12 +441,12 @@ for.body:                                         ; preds = %for.body.preheader,
   %conv2 = sext i8 %i.03 to i32
   %conv3 = sext i8 %i.03 to i64
   %add = add i64 %conv3, 2
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv2, i32* %arrayidx, align 4
   %idxprom4 = sext i8 %i.03 to i64
-  %arrayidx5 = getelementptr inbounds i32* %A, i64 %idxprom4
-  %0 = load i32* %arrayidx5, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx5 = getelementptr inbounds i32, i32* %A, i64 %idxprom4
+  %0 = load i32, i32* %arrayidx5, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add i8 %i.03, 1
   %conv = sext i8 %inc to i64
@@ -487,12 +487,12 @@ for.body:                                         ; preds = %for.body.preheader,
   %conv2 = sext i16 %i.03 to i32
   %conv3 = sext i16 %i.03 to i64
   %add = add i64 %conv3, 2
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv2, i32* %arrayidx, align 4
   %idxprom4 = sext i16 %i.03 to i64
-  %arrayidx5 = getelementptr inbounds i32* %A, i64 %idxprom4
-  %0 = load i32* %arrayidx5, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx5 = getelementptr inbounds i32, i32* %A, i64 %idxprom4
+  %0 = load i32, i32* %arrayidx5, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add i16 %i.03, 1
   %conv = sext i16 %inc to i64
@@ -531,12 +531,12 @@ for.body:                                         ; preds = %for.body.preheader,
   %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ]
   %0 = add nsw i64 %indvars.iv, 2
-  %arrayidx = getelementptr inbounds i32* %A, i64 %0
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %0
   %1 = trunc i64 %indvars.iv to i32
   store i32 %1, i32* %arrayidx, align 4
-  %arrayidx3 = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %2 = load i32* %arrayidx3, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx3 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %2, i32* %B.addr.02, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %exitcond = icmp ne i64 %indvars.iv.next, %n
@@ -557,7 +557,7 @@ for.end:                                          ; preds = %for.end.loopexit, %
 define void @p7(i32* %A, i32* %B, i8 signext %n) nounwind uwtable ssp {
 entry:
   %idxprom = sext i8 %n to i64
-  %arrayidx = getelementptr inbounds i32* %A, i64 %idxprom
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %idxprom
 
 ; CHECK: da analyze - none!
 ; CHECK: da analyze - none!
@@ -569,8 +569,8 @@ entry:
   store i32 0, i32* %arrayidx, align 4
   %conv = sext i8 %n to i64
   %add = add i64 %conv, 1
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %add
-  %0 = load i32* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %add
+  %0 = load i32, i32* %arrayidx2, align 4
   store i32 %0, i32* %B, align 4
   ret void
 }
@@ -583,7 +583,7 @@ entry:
 define void @p8(i32* %A, i32* %B, i16 signext %n) nounwind uwtable ssp {
 entry:
   %idxprom = sext i16 %n to i64
-  %arrayidx = getelementptr inbounds i32* %A, i64 %idxprom
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %idxprom
   store i32 0, i32* %arrayidx, align 4
 
 ; CHECK: da analyze - none!
@@ -595,8 +595,8 @@ entry:
 
   %conv = sext i16 %n to i64
   %add = add i64 %conv, 1
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %add
-  %0 = load i32* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %add
+  %0 = load i32, i32* %arrayidx2, align 4
   store i32 %0, i32* %B, align 4
   ret void
 }
@@ -609,7 +609,7 @@ entry:
 define void @p9(i32* %A, i32* %B, i32 %n) nounwind uwtable ssp {
 entry:
   %idxprom = sext i32 %n to i64
-  %arrayidx = getelementptr inbounds i32* %A, i64 %idxprom
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %idxprom
   store i32 0, i32* %arrayidx, align 4
 
 ; CHECK: da analyze - none!
@@ -621,8 +621,8 @@ entry:
 
   %add = add nsw i32 %n, 1
   %idxprom1 = sext i32 %add to i64
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %idxprom1
-  %0 = load i32* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %idxprom1
+  %0 = load i32, i32* %arrayidx2, align 4
   store i32 %0, i32* %B, align 4
   ret void
 }
@@ -635,7 +635,7 @@ entry:
 define void @p10(i32* %A, i32* %B, i32 %n) nounwind uwtable ssp {
 entry:
   %idxprom = zext i32 %n to i64
-  %arrayidx = getelementptr inbounds i32* %A, i64 %idxprom
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %idxprom
   store i32 0, i32* %arrayidx, align 4
 
 ; CHECK: da analyze - none!
@@ -647,8 +647,8 @@ entry:
 
   %add = add i32 %n, 1
   %idxprom1 = zext i32 %add to i64
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %idxprom1
-  %0 = load i32* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %idxprom1
+  %0 = load i32, i32* %arrayidx2, align 4
   store i32 %0, i32* %B, align 4
   ret void
 }
@@ -668,7 +668,7 @@ define void @f(%struct.S* %s, i32 %size) nounwind uwtable ssp {
 entry:
   %idx.ext = zext i32 %size to i64
   %add.ptr.sum = add i64 %idx.ext, -1
-  %add.ptr1 = getelementptr inbounds %struct.S* %s, i64 %add.ptr.sum
+  %add.ptr1 = getelementptr inbounds %struct.S, %struct.S* %s, i64 %add.ptr.sum
   %cmp1 = icmp eq i64 %add.ptr.sum, 0
   br i1 %cmp1, label %while.end, label %while.body.preheader
 
@@ -681,11 +681,11 @@ while.body.preheader:                             ; preds = %entry
 
 while.body:                                       ; preds = %while.body.preheader, %while.body
   %i.02 = phi %struct.S* [ %incdec.ptr, %while.body ], [ %s, %while.body.preheader ]
-  %0 = getelementptr inbounds %struct.S* %i.02, i64 1, i32 0
-  %1 = load i32* %0, align 4
-  %2 = getelementptr inbounds %struct.S* %i.02, i64 0, i32 0
+  %0 = getelementptr inbounds %struct.S, %struct.S* %i.02, i64 1, i32 0
+  %1 = load i32, i32* %0, align 4
+  %2 = getelementptr inbounds %struct.S, %struct.S* %i.02, i64 0, i32 0
   store i32 %1, i32* %2, align 4
-  %incdec.ptr = getelementptr inbounds %struct.S* %i.02, i64 1
+  %incdec.ptr = getelementptr inbounds %struct.S, %struct.S* %i.02, i64 1
   %cmp = icmp eq %struct.S* %incdec.ptr, %add.ptr1
   br i1 %cmp, label %while.end.loopexit, label %while.body
 
diff --git a/test/Analysis/DependenceAnalysis/Propagating.ll b/test/Analysis/DependenceAnalysis/Propagating.ll
index f9034ede9d0b..5a97b9929263 100644
--- a/test/Analysis/DependenceAnalysis/Propagating.ll
+++ b/test/Analysis/DependenceAnalysis/Propagating.ll
@@ -32,19 +32,19 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %conv = trunc i64 %i.03 to i32
   %add = add nsw i64 %i.03, %j.02
   %add4 = add nsw i64 %i.03, 1
-  %arrayidx5 = getelementptr inbounds [100 x i32]* %A, i64 %add4, i64 %add
+  %arrayidx5 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %add4, i64 %add
   store i32 %conv, i32* %arrayidx5, align 4
   %add6 = add nsw i64 %i.03, %j.02
-  %arrayidx8 = getelementptr inbounds [100 x i32]* %A, i64 %i.03, i64 %add6
-  %0 = load i32* %arrayidx8, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx8 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.03, i64 %add6
+  %0 = load i32, i32* %arrayidx8, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body3, label %for.inc9
 
 for.inc9:                                         ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 100
   %inc10 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc10, 100
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end11
@@ -88,26 +88,26 @@ for.body6:                                        ; preds = %for.cond4.preheader
   %add = add nsw i64 %j.03, %k.02
   %add7 = add nsw i64 %i.05, 1
   %sub = sub nsw i64 %j.03, %i.05
-  %arrayidx9 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 %sub, i64 %add7, i64 %add
+  %arrayidx9 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %A, i64 %sub, i64 %add7, i64 %add
   store i32 %conv, i32* %arrayidx9, align 4
   %add10 = add nsw i64 %j.03, %k.02
   %sub11 = sub nsw i64 %j.03, %i.05
-  %arrayidx14 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 %sub11, i64 %i.05, i64 %add10
-  %0 = load i32* %arrayidx14, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.21, i64 1
+  %arrayidx14 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %A, i64 %sub11, i64 %i.05, i64 %add10
+  %0 = load i32, i32* %arrayidx14, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.21, i64 1
   store i32 %0, i32* %B.addr.21, align 4
   %inc = add nsw i64 %k.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body6, label %for.inc15
 
 for.inc15:                                        ; preds = %for.body6
-  %scevgep = getelementptr i32* %B.addr.14, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.14, i64 100
   %inc16 = add nsw i64 %j.03, 1
   %exitcond8 = icmp ne i64 %inc16, 100
   br i1 %exitcond8, label %for.cond4.preheader, label %for.inc18
 
 for.inc18:                                        ; preds = %for.inc15
-  %scevgep7 = getelementptr i32* %B.addr.06, i64 10000
+  %scevgep7 = getelementptr i32, i32* %B.addr.06, i64 10000
   %inc19 = add nsw i64 %i.05, 1
   %exitcond9 = icmp ne i64 %inc19, 100
   br i1 %exitcond9, label %for.cond1.preheader, label %for.end20
@@ -144,20 +144,20 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %conv = trunc i64 %i.03 to i32
   %mul = shl nsw i64 %i.03, 1
   %sub = add nsw i64 %i.03, -1
-  %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %sub, i64 %mul
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %sub, i64 %mul
   store i32 %conv, i32* %arrayidx4, align 4
   %add = add nsw i64 %i.03, %j.02
   %add5 = add nsw i64 %add, 110
-  %arrayidx7 = getelementptr inbounds [100 x i32]* %A, i64 %i.03, i64 %add5
-  %0 = load i32* %arrayidx7, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx7 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.03, i64 %add5
+  %0 = load i32, i32* %arrayidx7, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body3, label %for.inc8
 
 for.inc8:                                         ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 100
   %inc9 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc9, 100
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end10
@@ -194,21 +194,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %conv = trunc i64 %i.03 to i32
   %mul = shl nsw i64 %j.02, 1
   %add = add nsw i64 %mul, %i.03
-  %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 %i.03, i64 %add
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.03, i64 %add
   store i32 %conv, i32* %arrayidx4, align 4
   %mul5 = shl nsw i64 %j.02, 1
   %sub = sub nsw i64 %mul5, %i.03
   %add6 = add nsw i64 %sub, 5
-  %arrayidx8 = getelementptr inbounds [100 x i32]* %A, i64 %i.03, i64 %add6
-  %0 = load i32* %arrayidx8, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx8 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.03, i64 %add6
+  %0 = load i32, i32* %arrayidx8, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body3, label %for.inc9
 
 for.inc9:                                         ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 100
   %inc10 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc10, 100
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end11
@@ -247,20 +247,20 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %add = add nsw i64 %mul, %j.02
   %add4 = add nsw i64 %add, 1
   %add5 = add nsw i64 %i.03, 2
-  %arrayidx6 = getelementptr inbounds [100 x i32]* %A, i64 %add5, i64 %add4
+  %arrayidx6 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %add5, i64 %add4
   store i32 %conv, i32* %arrayidx6, align 4
   %mul7 = shl nsw i64 %i.03, 1
   %add8 = add nsw i64 %mul7, %j.02
-  %arrayidx10 = getelementptr inbounds [100 x i32]* %A, i64 %i.03, i64 %add8
-  %0 = load i32* %arrayidx10, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx10 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %i.03, i64 %add8
+  %0 = load i32, i32* %arrayidx10, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body3, label %for.inc11
 
 for.inc11:                                        ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 100
   %inc12 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc12, 100
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end13
@@ -301,20 +301,20 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %sub = sub nsw i64 22, %i.03
   %mul4 = mul nsw i64 %i.03, 3
   %sub5 = add nsw i64 %mul4, -18
-  %arrayidx7 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 %sub5, i64 %sub, i64 %add
+  %arrayidx7 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %A, i64 %sub5, i64 %sub, i64 %add
   store i32 %conv, i32* %arrayidx7, align 4
   %mul8 = mul nsw i64 %i.03, 3
   %add9 = add nsw i64 %mul8, %j.02
-  %arrayidx12 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 %i.03, i64 %i.03, i64 %add9
-  %0 = load i32* %arrayidx12, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx12 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %A, i64 %i.03, i64 %i.03, i64 %add9
+  %0 = load i32, i32* %arrayidx12, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body3, label %for.inc13
 
 for.inc13:                                        ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 100
   %inc14 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc14, 100
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end15
@@ -353,21 +353,21 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %add = add nsw i64 %mul, %j.02
   %add4 = add nsw i64 %add, 2
   %add5 = add nsw i64 %i.03, 1
-  %arrayidx6 = getelementptr inbounds [100 x i32]* %A, i64 %add5, i64 %add4
+  %arrayidx6 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %add5, i64 %add4
   store i32 %conv, i32* %arrayidx6, align 4
   %mul7 = shl nsw i64 %i.03, 3
   %add8 = add nsw i64 %mul7, %j.02
   %mul9 = shl nsw i64 %i.03, 1
-  %arrayidx11 = getelementptr inbounds [100 x i32]* %A, i64 %mul9, i64 %add8
-  %0 = load i32* %arrayidx11, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx11 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %mul9, i64 %add8
+  %0 = load i32, i32* %arrayidx11, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body3, label %for.inc12
 
 for.inc12:                                        ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 100
   %inc13 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc13, 100
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end14
@@ -408,22 +408,22 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %add4 = add nsw i64 %add, 2
   %mul5 = shl nsw i64 %i.03, 1
   %add6 = add nsw i64 %mul5, 4
-  %arrayidx7 = getelementptr inbounds [100 x i32]* %A, i64 %add6, i64 %add4
+  %arrayidx7 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %add6, i64 %add4
   store i32 %conv, i32* %arrayidx7, align 4
   %mul8 = mul nsw i64 %i.03, 5
   %add9 = add nsw i64 %mul8, %j.02
   %mul10 = mul nsw i64 %i.03, -2
   %add11 = add nsw i64 %mul10, 20
-  %arrayidx13 = getelementptr inbounds [100 x i32]* %A, i64 %add11, i64 %add9
-  %0 = load i32* %arrayidx13, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx13 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %add11, i64 %add9
+  %0 = load i32, i32* %arrayidx13, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body3, label %for.inc14
 
 for.inc14:                                        ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 100
   %inc15 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc15, 100
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end16
@@ -459,22 +459,22 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %B.addr.11 = phi i32* [ %B.addr.04, %for.cond1.preheader ], [ %incdec.ptr, %for.body3 ]
   %conv = trunc i64 %i.03 to i32
   %add = add nsw i64 %j.02, 2
-  %arrayidx4 = getelementptr inbounds [100 x i32]* %A, i64 4, i64 %add
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 4, i64 %add
   store i32 %conv, i32* %arrayidx4, align 4
   %mul = mul nsw i64 %i.03, 5
   %add5 = add nsw i64 %mul, %j.02
   %mul6 = mul nsw i64 %i.03, -2
   %add7 = add nsw i64 %mul6, 4
-  %arrayidx9 = getelementptr inbounds [100 x i32]* %A, i64 %add7, i64 %add5
-  %0 = load i32* %arrayidx9, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx9 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %add7, i64 %add5
+  %0 = load i32, i32* %arrayidx9, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body3, label %for.inc10
 
 for.inc10:                                        ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 100
   %inc11 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc11, 100
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end12
@@ -514,18 +514,18 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %add4 = add nsw i64 %add, 2
   %mul5 = shl nsw i64 %i.03, 1
   %add6 = add nsw i64 %mul5, 4
-  %arrayidx7 = getelementptr inbounds [100 x i32]* %A, i64 %add6, i64 %add4
+  %arrayidx7 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 %add6, i64 %add4
   store i32 %conv, i32* %arrayidx7, align 4
-  %arrayidx9 = getelementptr inbounds [100 x i32]* %A, i64 4, i64 %j.02
-  %0 = load i32* %arrayidx9, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.11, i64 1
+  %arrayidx9 = getelementptr inbounds [100 x i32], [100 x i32]* %A, i64 4, i64 %j.02
+  %0 = load i32, i32* %arrayidx9, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.11, i64 1
   store i32 %0, i32* %B.addr.11, align 4
   %inc = add nsw i64 %j.02, 1
   %exitcond = icmp ne i64 %inc, 100
   br i1 %exitcond, label %for.body3, label %for.inc10
 
 for.inc10:                                        ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.04, i64 100
+  %scevgep = getelementptr i32, i32* %B.addr.04, i64 100
   %inc11 = add nsw i64 %i.03, 1
   %exitcond5 = icmp ne i64 %inc11, 100
   br i1 %exitcond5, label %for.cond1.preheader, label %for.end12
diff --git a/test/Analysis/DependenceAnalysis/Separability.ll b/test/Analysis/DependenceAnalysis/Separability.ll
index 3dcaaec2ae85..e56e741295ba 100644
--- a/test/Analysis/DependenceAnalysis/Separability.ll
+++ b/test/Analysis/DependenceAnalysis/Separability.ll
@@ -44,33 +44,33 @@ for.body9:                                        ; preds = %for.cond7.preheader
   %conv = trunc i64 %i.07 to i32
   %add = add nsw i64 %j.05, %k.03
   %idxprom = sext i32 %n to i64
-  %arrayidx11 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 %idxprom, i64 %i.07, i64 %add
+  %arrayidx11 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %A, i64 %idxprom, i64 %i.07, i64 %add
   store i32 %conv, i32* %arrayidx11, align 4
   %mul = shl nsw i64 %j.05, 1
   %sub = sub nsw i64 %mul, %l.02
   %add12 = add nsw i64 %i.07, 10
-  %arrayidx15 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 10, i64 %add12, i64 %sub
-  %0 = load i32* %arrayidx15, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.31, i64 1
+  %arrayidx15 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %A, i64 10, i64 %add12, i64 %sub
+  %0 = load i32, i32* %arrayidx15, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.31, i64 1
   store i32 %0, i32* %B.addr.31, align 4
   %inc = add nsw i64 %l.02, 1
   %exitcond = icmp ne i64 %inc, 50
   br i1 %exitcond, label %for.body9, label %for.inc16
 
 for.inc16:                                        ; preds = %for.body9
-  %scevgep = getelementptr i32* %B.addr.24, i64 50
+  %scevgep = getelementptr i32, i32* %B.addr.24, i64 50
   %inc17 = add nsw i64 %k.03, 1
   %exitcond10 = icmp ne i64 %inc17, 50
   br i1 %exitcond10, label %for.cond7.preheader, label %for.inc19
 
 for.inc19:                                        ; preds = %for.inc16
-  %scevgep9 = getelementptr i32* %B.addr.16, i64 2500
+  %scevgep9 = getelementptr i32, i32* %B.addr.16, i64 2500
   %inc20 = add nsw i64 %j.05, 1
   %exitcond12 = icmp ne i64 %inc20, 50
   br i1 %exitcond12, label %for.cond4.preheader, label %for.inc22
 
 for.inc22:                                        ; preds = %for.inc19
-  %scevgep11 = getelementptr i32* %B.addr.08, i64 125000
+  %scevgep11 = getelementptr i32, i32* %B.addr.08, i64 125000
   %inc23 = add nsw i64 %i.07, 1
   %exitcond13 = icmp ne i64 %inc23, 50
   br i1 %exitcond13, label %for.cond1.preheader, label %for.end24
@@ -118,33 +118,33 @@ for.body9:                                        ; preds = %for.cond7.preheader
   %B.addr.31 = phi i32* [ %B.addr.24, %for.cond7.preheader ], [ %incdec.ptr, %for.body9 ]
   %conv = trunc i64 %i.07 to i32
   %add = add nsw i64 %j.05, %k.03
-  %arrayidx11 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 %i.07, i64 %i.07, i64 %add
+  %arrayidx11 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %A, i64 %i.07, i64 %i.07, i64 %add
   store i32 %conv, i32* %arrayidx11, align 4
   %mul = shl nsw i64 %j.05, 1
   %sub = sub nsw i64 %mul, %l.02
   %add12 = add nsw i64 %i.07, 10
-  %arrayidx15 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 10, i64 %add12, i64 %sub
-  %0 = load i32* %arrayidx15, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.31, i64 1
+  %arrayidx15 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %A, i64 10, i64 %add12, i64 %sub
+  %0 = load i32, i32* %arrayidx15, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.31, i64 1
   store i32 %0, i32* %B.addr.31, align 4
   %inc = add nsw i64 %l.02, 1
   %exitcond = icmp ne i64 %inc, 50
   br i1 %exitcond, label %for.body9, label %for.inc16
 
 for.inc16:                                        ; preds = %for.body9
-  %scevgep = getelementptr i32* %B.addr.24, i64 50
+  %scevgep = getelementptr i32, i32* %B.addr.24, i64 50
   %inc17 = add nsw i64 %k.03, 1
   %exitcond10 = icmp ne i64 %inc17, 50
   br i1 %exitcond10, label %for.cond7.preheader, label %for.inc19
 
 for.inc19:                                        ; preds = %for.inc16
-  %scevgep9 = getelementptr i32* %B.addr.16, i64 2500
+  %scevgep9 = getelementptr i32, i32* %B.addr.16, i64 2500
   %inc20 = add nsw i64 %j.05, 1
   %exitcond12 = icmp ne i64 %inc20, 50
   br i1 %exitcond12, label %for.cond4.preheader, label %for.inc22
 
 for.inc22:                                        ; preds = %for.inc19
-  %scevgep11 = getelementptr i32* %B.addr.08, i64 125000
+  %scevgep11 = getelementptr i32, i32* %B.addr.08, i64 125000
   %inc23 = add nsw i64 %i.07, 1
   %exitcond13 = icmp ne i64 %inc23, 50
   br i1 %exitcond13, label %for.cond1.preheader, label %for.end24
@@ -192,33 +192,33 @@ for.body9:                                        ; preds = %for.cond7.preheader
   %B.addr.31 = phi i32* [ %B.addr.24, %for.cond7.preheader ], [ %incdec.ptr, %for.body9 ]
   %conv = trunc i64 %i.07 to i32
   %add = add nsw i64 %i.07, %k.03
-  %arrayidx12 = getelementptr inbounds [100 x [100 x [100 x i32]]]* %A, i64 %i.07, i64 %i.07, i64 %add, i64 %l.02
+  %arrayidx12 = getelementptr inbounds [100 x [100 x [100 x i32]]], [100 x [100 x [100 x i32]]]* %A, i64 %i.07, i64 %i.07, i64 %add, i64 %l.02
   store i32 %conv, i32* %arrayidx12, align 4
   %add13 = add nsw i64 %l.02, 10
   %add14 = add nsw i64 %j.05, %k.03
   %add15 = add nsw i64 %i.07, 10
-  %arrayidx19 = getelementptr inbounds [100 x [100 x [100 x i32]]]* %A, i64 10, i64 %add15, i64 %add14, i64 %add13
-  %0 = load i32* %arrayidx19, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.31, i64 1
+  %arrayidx19 = getelementptr inbounds [100 x [100 x [100 x i32]]], [100 x [100 x [100 x i32]]]* %A, i64 10, i64 %add15, i64 %add14, i64 %add13
+  %0 = load i32, i32* %arrayidx19, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.31, i64 1
   store i32 %0, i32* %B.addr.31, align 4
   %inc = add nsw i64 %l.02, 1
   %exitcond = icmp ne i64 %inc, 50
   br i1 %exitcond, label %for.body9, label %for.inc20
 
 for.inc20:                                        ; preds = %for.body9
-  %scevgep = getelementptr i32* %B.addr.24, i64 50
+  %scevgep = getelementptr i32, i32* %B.addr.24, i64 50
   %inc21 = add nsw i64 %k.03, 1
   %exitcond10 = icmp ne i64 %inc21, 50
   br i1 %exitcond10, label %for.cond7.preheader, label %for.inc23
 
 for.inc23:                                        ; preds = %for.inc20
-  %scevgep9 = getelementptr i32* %B.addr.16, i64 2500
+  %scevgep9 = getelementptr i32, i32* %B.addr.16, i64 2500
   %inc24 = add nsw i64 %j.05, 1
   %exitcond12 = icmp ne i64 %inc24, 50
   br i1 %exitcond12, label %for.cond4.preheader, label %for.inc26
 
 for.inc26:                                        ; preds = %for.inc23
-  %scevgep11 = getelementptr i32* %B.addr.08, i64 125000
+  %scevgep11 = getelementptr i32, i32* %B.addr.08, i64 125000
   %inc27 = add nsw i64 %i.07, 1
   %exitcond13 = icmp ne i64 %inc27, 50
   br i1 %exitcond13, label %for.cond1.preheader, label %for.end28
@@ -267,33 +267,33 @@ for.body9:                                        ; preds = %for.cond7.preheader
   %conv = trunc i64 %i.07 to i32
   %add = add nsw i64 %l.02, %k.03
   %add10 = add nsw i64 %i.07, %k.03
-  %arrayidx13 = getelementptr inbounds [100 x [100 x [100 x i32]]]* %A, i64 %i.07, i64 %i.07, i64 %add10, i64 %add
+  %arrayidx13 = getelementptr inbounds [100 x [100 x [100 x i32]]], [100 x [100 x [100 x i32]]]* %A, i64 %i.07, i64 %i.07, i64 %add10, i64 %add
   store i32 %conv, i32* %arrayidx13, align 4
   %add14 = add nsw i64 %l.02, 10
   %add15 = add nsw i64 %j.05, %k.03
   %add16 = add nsw i64 %i.07, 10
-  %arrayidx20 = getelementptr inbounds [100 x [100 x [100 x i32]]]* %A, i64 10, i64 %add16, i64 %add15, i64 %add14
-  %0 = load i32* %arrayidx20, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.31, i64 1
+  %arrayidx20 = getelementptr inbounds [100 x [100 x [100 x i32]]], [100 x [100 x [100 x i32]]]* %A, i64 10, i64 %add16, i64 %add15, i64 %add14
+  %0 = load i32, i32* %arrayidx20, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.31, i64 1
   store i32 %0, i32* %B.addr.31, align 4
   %inc = add nsw i64 %l.02, 1
   %exitcond = icmp ne i64 %inc, 50
   br i1 %exitcond, label %for.body9, label %for.inc21
 
 for.inc21:                                        ; preds = %for.body9
-  %scevgep = getelementptr i32* %B.addr.24, i64 50
+  %scevgep = getelementptr i32, i32* %B.addr.24, i64 50
   %inc22 = add nsw i64 %k.03, 1
   %exitcond10 = icmp ne i64 %inc22, 50
   br i1 %exitcond10, label %for.cond7.preheader, label %for.inc24
 
 for.inc24:                                        ; preds = %for.inc21
-  %scevgep9 = getelementptr i32* %B.addr.16, i64 2500
+  %scevgep9 = getelementptr i32, i32* %B.addr.16, i64 2500
   %inc25 = add nsw i64 %j.05, 1
   %exitcond12 = icmp ne i64 %inc25, 50
   br i1 %exitcond12, label %for.cond4.preheader, label %for.inc27
 
 for.inc27:                                        ; preds = %for.inc24
-  %scevgep11 = getelementptr i32* %B.addr.08, i64 125000
+  %scevgep11 = getelementptr i32, i32* %B.addr.08, i64 125000
   %inc28 = add nsw i64 %i.07, 1
   %exitcond13 = icmp ne i64 %inc28, 50
   br i1 %exitcond13, label %for.cond1.preheader, label %for.end29
diff --git a/test/Analysis/DependenceAnalysis/StrongSIV.ll b/test/Analysis/DependenceAnalysis/StrongSIV.ll
index f499e84d4844..78befa5e4707 100644
--- a/test/Analysis/DependenceAnalysis/StrongSIV.ll
+++ b/test/Analysis/DependenceAnalysis/StrongSIV.ll
@@ -28,12 +28,12 @@ for.body:                                         ; preds = %for.body.preheader,
   %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ]
   %0 = add nsw i64 %indvars.iv, 2
-  %arrayidx = getelementptr inbounds i32* %A, i64 %0
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %0
   %1 = trunc i64 %indvars.iv to i32
   store i32 %1, i32* %arrayidx, align 4
-  %arrayidx3 = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %2 = load i32* %arrayidx3, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx3 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %2, i32* %B.addr.02, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %exitcond = icmp ne i64 %indvars.iv.next, %n
@@ -72,11 +72,11 @@ for.body:                                         ; preds = %for.body.preheader,
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ]
   %conv2 = trunc i64 %i.03 to i32
   %add = add nsw i64 %i.03, 2
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv2, i32* %arrayidx, align 4
-  %arrayidx3 = getelementptr inbounds i32* %A, i64 %i.03
-  %1 = load i32* %arrayidx3, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx3 = getelementptr inbounds i32, i32* %A, i64 %i.03
+  %1 = load i32, i32* %arrayidx3, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %1, i32* %B.addr.02, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %0
@@ -114,11 +114,11 @@ for.body:                                         ; preds = %for.body.preheader,
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ]
   %conv = trunc i64 %i.03 to i32
   %add = add i64 %i.03, 2
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %i.03
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %i.03
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
@@ -155,12 +155,12 @@ for.body:                                         ; preds = %for.body.preheader,
   %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ]
   %0 = add nsw i64 %indvars.iv, 2
-  %arrayidx = getelementptr inbounds i32* %A, i64 %0
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %0
   %1 = trunc i64 %indvars.iv to i32
   store i32 %1, i32* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %2 = load i32* %arrayidx2, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx2, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %2, i32* %B.addr.02, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -195,11 +195,11 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %add = add i64 %i.02, 19
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %i.02
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %i.02
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 19
@@ -230,11 +230,11 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %add = add i64 %i.02, 19
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %i.02
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %i.02
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 20
@@ -266,12 +266,12 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.02 to i32
   %mul = shl i64 %i.02, 1
   %add = add i64 %mul, 6
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %mul1 = shl i64 %i.02, 1
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %mul1
-  %0 = load i32* %arrayidx2, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %mul1
+  %0 = load i32, i32* %arrayidx2, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 20
@@ -303,12 +303,12 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.02 to i32
   %mul = shl i64 %i.02, 1
   %add = add i64 %mul, 7
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %mul1 = shl i64 %i.02, 1
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %mul1
-  %0 = load i32* %arrayidx2, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %mul1
+  %0 = load i32, i32* %arrayidx2, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 20
@@ -339,11 +339,11 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %add = add i64 %i.02, %n
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %i.02
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %i.02
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 20
@@ -378,13 +378,13 @@ for.body:                                         ; preds = %for.body.preheader,
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ]
   %conv = trunc i64 %i.03 to i32
   %add = add i64 %i.03, %n
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %mul = shl i64 %n, 1
   %add1 = add i64 %i.03, %mul
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %add1
-  %0 = load i32* %arrayidx2, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %add1
+  %0 = load i32, i32* %arrayidx2, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
@@ -419,13 +419,13 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.02 to i32
   %mul = mul i64 %i.02, %n
   %add = add i64 %mul, 5
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %mul1 = mul i64 %i.02, %n
   %add2 = add i64 %mul1, 5
-  %arrayidx3 = getelementptr inbounds i32* %A, i64 %add2
-  %0 = load i32* %arrayidx3, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx3 = getelementptr inbounds i32, i32* %A, i64 %add2
+  %0 = load i32, i32* %arrayidx3, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 1000
diff --git a/test/Analysis/DependenceAnalysis/SymbolicRDIV.ll b/test/Analysis/DependenceAnalysis/SymbolicRDIV.ll
index 5443909d7ef6..6e8b98ca2643 100644
--- a/test/Analysis/DependenceAnalysis/SymbolicRDIV.ll
+++ b/test/Analysis/DependenceAnalysis/SymbolicRDIV.ll
@@ -41,7 +41,7 @@ for.body:                                         ; preds = %for.body.preheader,
   %conv = trunc i64 %i.05 to i32
   %mul = shl nsw i64 %i.05, 1
   %add = add i64 %mul, %n1
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %inc = add nsw i64 %i.05, 1
   %exitcond = icmp ne i64 %inc, %n1
@@ -52,9 +52,9 @@ for.body4:                                        ; preds = %for.body4.preheader
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ]
   %mul56 = add i64 %j.03, %n1
   %add7 = mul i64 %mul56, 3
-  %arrayidx8 = getelementptr inbounds i32* %A, i64 %add7
-  %0 = load i32* %arrayidx8, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx8 = getelementptr inbounds i32, i32* %A, i64 %add7
+  %0 = load i32, i32* %arrayidx8, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc10 = add nsw i64 %j.03, 1
   %exitcond7 = icmp ne i64 %inc10, %n2
@@ -105,7 +105,7 @@ for.body:                                         ; preds = %for.body.preheader,
   %mul = shl nsw i64 %i.05, 1
   %mul1 = mul i64 %n2, 5
   %add = add i64 %mul, %mul1
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %inc = add nsw i64 %i.05, 1
   %exitcond = icmp ne i64 %inc, %n1
@@ -117,9 +117,9 @@ for.body5:                                        ; preds = %for.body5.preheader
   %mul6 = mul nsw i64 %j.03, 3
   %mul7 = shl i64 %n2, 1
   %add8 = add i64 %mul6, %mul7
-  %arrayidx9 = getelementptr inbounds i32* %A, i64 %add8
-  %0 = load i32* %arrayidx9, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx9 = getelementptr inbounds i32, i32* %A, i64 %add8
+  %0 = load i32, i32* %arrayidx9, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc11 = add nsw i64 %j.03, 1
   %exitcond6 = icmp ne i64 %inc11, %n2
@@ -169,7 +169,7 @@ for.body:                                         ; preds = %for.body.preheader,
   %conv = trunc i64 %i.05 to i32
   %mul = shl nsw i64 %i.05, 1
   %sub = sub i64 %mul, %n2
-  %arrayidx = getelementptr inbounds i32* %A, i64 %sub
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %sub
   store i32 %conv, i32* %arrayidx, align 4
   %inc = add nsw i64 %i.05, 1
   %exitcond = icmp ne i64 %inc, %n1
@@ -180,9 +180,9 @@ for.body4:                                        ; preds = %for.body4.preheader
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ]
   %mul6 = shl i64 %n1, 1
   %add = sub i64 %mul6, %j.03
-  %arrayidx7 = getelementptr inbounds i32* %A, i64 %add
-  %0 = load i32* %arrayidx7, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx7 = getelementptr inbounds i32, i32* %A, i64 %add
+  %0 = load i32, i32* %arrayidx7, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc9 = add nsw i64 %j.03, 1
   %exitcond6 = icmp ne i64 %inc9, %n2
@@ -231,7 +231,7 @@ for.body:                                         ; preds = %for.body.preheader,
   %i.05 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ]
   %conv = trunc i64 %i.05 to i32
   %add = sub i64 %n2, %i.05
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %inc = add nsw i64 %i.05, 1
   %exitcond = icmp ne i64 %inc, %n1
@@ -241,9 +241,9 @@ for.body4:                                        ; preds = %for.body4.preheader
   %j.03 = phi i64 [ %inc8, %for.body4 ], [ 0, %for.body4.preheader ]
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ]
   %sub5 = sub i64 %j.03, %n1
-  %arrayidx6 = getelementptr inbounds i32* %A, i64 %sub5
-  %0 = load i32* %arrayidx6, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx6 = getelementptr inbounds i32, i32* %A, i64 %sub5
+  %0 = load i32, i32* %arrayidx6, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc8 = add nsw i64 %j.03, 1
   %exitcond6 = icmp ne i64 %inc8, %n2
@@ -293,7 +293,7 @@ for.body:                                         ; preds = %for.body.preheader,
   %conv = trunc i64 %i.05 to i32
   %mul = shl i64 %n1, 1
   %add = sub i64 %mul, %i.05
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %inc = add nsw i64 %i.05, 1
   %exitcond = icmp ne i64 %inc, %n1
@@ -303,9 +303,9 @@ for.body4:                                        ; preds = %for.body4.preheader
   %j.03 = phi i64 [ %inc9, %for.body4 ], [ 0, %for.body4.preheader ]
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ]
   %add6 = sub i64 %n1, %j.03
-  %arrayidx7 = getelementptr inbounds i32* %A, i64 %add6
-  %0 = load i32* %arrayidx7, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx7 = getelementptr inbounds i32, i32* %A, i64 %add6
+  %0 = load i32, i32* %arrayidx7, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc9 = add nsw i64 %j.03, 1
   %exitcond6 = icmp ne i64 %inc9, %n2
@@ -354,7 +354,7 @@ for.body:                                         ; preds = %for.body.preheader,
   %i.05 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ]
   %conv = trunc i64 %i.05 to i32
   %add = sub i64 %n2, %i.05
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %inc = add nsw i64 %i.05, 1
   %exitcond = icmp ne i64 %inc, %n1
@@ -365,9 +365,9 @@ for.body4:                                        ; preds = %for.body4.preheader
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ]
   %mul = shl i64 %n2, 1
   %add6 = sub i64 %mul, %j.03
-  %arrayidx7 = getelementptr inbounds i32* %A, i64 %add6
-  %0 = load i32* %arrayidx7, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx7 = getelementptr inbounds i32, i32* %A, i64 %add6
+  %0 = load i32, i32* %arrayidx7, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc9 = add nsw i64 %j.03, 1
   %exitcond6 = icmp ne i64 %inc9, %n2
@@ -417,19 +417,19 @@ for.body3:                                        ; preds = %for.body3.preheader
   %conv = trunc i64 %i.05 to i32
   %sub = sub nsw i64 %j.03, %i.05
   %add = add i64 %sub, %n2
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %mul = shl i64 %n2, 1
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 %mul
-  %0 = load i32* %arrayidx4, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.12, i64 1
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 %mul
+  %0 = load i32, i32* %arrayidx4, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.12, i64 1
   store i32 %0, i32* %B.addr.12, align 4
   %inc = add nsw i64 %j.03, 1
   %exitcond = icmp ne i64 %inc, %n2
   br i1 %exitcond, label %for.body3, label %for.inc5.loopexit
 
 for.inc5.loopexit:                                ; preds = %for.body3
-  %scevgep = getelementptr i32* %B.addr.06, i64 %n2
+  %scevgep = getelementptr i32, i32* %B.addr.06, i64 %n2
   br label %for.inc5
 
 for.inc5:                                         ; preds = %for.inc5.loopexit, %for.cond1.preheader
diff --git a/test/Analysis/DependenceAnalysis/SymbolicSIV.ll b/test/Analysis/DependenceAnalysis/SymbolicSIV.ll
index 297096ce135d..711d0fabf87f 100644
--- a/test/Analysis/DependenceAnalysis/SymbolicSIV.ll
+++ b/test/Analysis/DependenceAnalysis/SymbolicSIV.ll
@@ -30,13 +30,13 @@ for.body:                                         ; preds = %for.body.preheader,
   %conv = trunc i64 %i.03 to i32
   %mul = shl nsw i64 %i.03, 1
   %add = add i64 %mul, %n
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %mul14 = add i64 %i.03, %n
   %add3 = mul i64 %mul14, 3
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 %add3
-  %0 = load i32* %arrayidx4, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 %add3
+  %0 = load i32, i32* %arrayidx4, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
@@ -76,14 +76,14 @@ for.body:                                         ; preds = %for.body.preheader,
   %mul = shl nsw i64 %i.03, 1
   %mul1 = mul i64 %n, 5
   %add = add i64 %mul, %mul1
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %mul2 = mul nsw i64 %i.03, 3
   %mul3 = shl i64 %n, 1
   %add4 = add i64 %mul2, %mul3
-  %arrayidx5 = getelementptr inbounds i32* %A, i64 %add4
-  %0 = load i32* %arrayidx5, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx5 = getelementptr inbounds i32, i32* %A, i64 %add4
+  %0 = load i32, i32* %arrayidx5, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
@@ -122,13 +122,13 @@ for.body:                                         ; preds = %for.body.preheader,
   %conv = trunc i64 %i.03 to i32
   %mul = shl nsw i64 %i.03, 1
   %sub = sub i64 %mul, %n
-  %arrayidx = getelementptr inbounds i32* %A, i64 %sub
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %sub
   store i32 %conv, i32* %arrayidx, align 4
   %mul2 = shl i64 %n, 1
   %add = sub i64 %mul2, %i.03
-  %arrayidx3 = getelementptr inbounds i32* %A, i64 %add
-  %0 = load i32* %arrayidx3, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx3 = getelementptr inbounds i32, i32* %A, i64 %add
+  %0 = load i32, i32* %arrayidx3, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
@@ -168,13 +168,13 @@ for.body:                                         ; preds = %for.body.preheader,
   %mul = mul nsw i64 %i.03, -2
   %add = add i64 %mul, %n
   %add1 = add i64 %add, 1
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add1
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add1
   store i32 %conv, i32* %arrayidx, align 4
   %mul2 = shl i64 %n, 1
   %sub = sub i64 %i.03, %mul2
-  %arrayidx3 = getelementptr inbounds i32* %A, i64 %sub
-  %0 = load i32* %arrayidx3, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx3 = getelementptr inbounds i32, i32* %A, i64 %sub
+  %0 = load i32, i32* %arrayidx3, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
@@ -214,12 +214,12 @@ for.body:                                         ; preds = %for.body.preheader,
   %mul = mul nsw i64 %i.03, -2
   %mul1 = mul i64 %n, 3
   %add = add i64 %mul, %mul1
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %add2 = sub i64 %n, %i.03
-  %arrayidx3 = getelementptr inbounds i32* %A, i64 %add2
-  %0 = load i32* %arrayidx3, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx3 = getelementptr inbounds i32, i32* %A, i64 %add2
+  %0 = load i32, i32* %arrayidx3, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
@@ -259,13 +259,13 @@ for.body:                                         ; preds = %for.body.preheader,
   %mul = mul nsw i64 %i.03, -2
   %mul1 = shl i64 %n, 1
   %sub = sub i64 %mul, %mul1
-  %arrayidx = getelementptr inbounds i32* %A, i64 %sub
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %sub
   store i32 %conv, i32* %arrayidx, align 4
   %sub2 = sub nsw i64 0, %i.03
   %sub3 = sub i64 %sub2, %n
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 %sub3
-  %0 = load i32* %arrayidx4, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 %sub3
+  %0 = load i32, i32* %arrayidx4, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
@@ -306,12 +306,12 @@ for.body:                                         ; preds = %for.body.preheader,
   %conv = trunc i64 %i.03 to i32
   %add = add i64 %i.03, %n
   %add1 = add i64 %add, 1
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add1
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add1
   store i32 %conv, i32* %arrayidx, align 4
   %sub = sub i64 0, %i.03
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub
-  %0 = load i32* %arrayidx2, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %sub
+  %0 = load i32, i32* %arrayidx2, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
@@ -351,16 +351,16 @@ for.body:                                         ; preds = %for.body.preheader,
   %mul = shl i64 %N, 2
   %mul1 = mul i64 %mul, %i.03
   %add = add i64 %mul1, %M
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %mul2 = shl i64 %N, 2
   %mul3 = mul i64 %mul2, %i.03
   %mul4 = mul i64 %M, 3
   %add5 = add i64 %mul3, %mul4
   %add6 = add i64 %add5, 1
-  %arrayidx7 = getelementptr inbounds i32* %A, i64 %add6
-  %0 = load i32* %arrayidx7, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx7 = getelementptr inbounds i32, i32* %A, i64 %add6
+  %0 = load i32, i32* %arrayidx7, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
@@ -400,16 +400,16 @@ for.body:                                         ; preds = %for.body.preheader,
   %mul = shl i64 %N, 1
   %mul1 = mul i64 %mul, %i.03
   %add = add i64 %mul1, %M
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %mul2 = shl i64 %N, 1
   %mul3 = mul i64 %mul2, %i.03
   %0 = mul i64 %M, -3
   %sub = add i64 %mul3, %0
   %add5 = add i64 %sub, 2
-  %arrayidx6 = getelementptr inbounds i32* %A, i64 %add5
-  %1 = load i32* %arrayidx6, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx6 = getelementptr inbounds i32, i32* %A, i64 %add5
+  %1 = load i32, i32* %arrayidx6, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %1, i32* %B.addr.02, align 4
   %inc = add nsw i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
diff --git a/test/Analysis/DependenceAnalysis/UsefulGEP.ll b/test/Analysis/DependenceAnalysis/UsefulGEP.ll
new file mode 100644
index 000000000000..cd46a275034c
--- /dev/null
+++ b/test/Analysis/DependenceAnalysis/UsefulGEP.ll
@@ -0,0 +1,51 @@
+; RUN: opt < %s -analyze -basicaa -da
+;; Check this doesn't crash.
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+;; struct s {
+;;   int A[10][10];
+;;   int C[10][10][10]; 
+;; } S;
+
+;; void dep_constraint_crash_test(int k,int N) {
+;;   for( int i=0;i<N;i++)
+;;     for( int j=0;j<N;j++)
+;;       S.A[0][0] = S.C[0][0][k];
+;; }
+
+
+%struct.s = type { [10 x [10 x i32]], [10 x [10 x [10 x i32]]] }
+
+@S = common global %struct.s zeroinitializer
+
+define void @dep_constraint_crash_test(i32 %k, i32 %N) {
+entry:
+  %cmp12 = icmp sgt i32 %N, 0
+  br i1 %cmp12, label %for.cond1.preheader.lr.ph, label %for.end6
+
+for.cond1.preheader.lr.ph:                        
+  %idxprom = sext i32 %k to i64
+  %arrayidx = getelementptr inbounds %struct.s, %struct.s* @S, i64 0, i32 1, i64 0, i64 0, i64 %idxprom
+  br label %for.body3.preheader
+
+for.body3.preheader:                              
+  %i.013 = phi i32 [ 0, %for.cond1.preheader.lr.ph ], [ %inc5, %for.inc4 ]
+  br label %for.body3
+
+for.body3:                                        
+  %j.011 = phi i32 [ %inc, %for.body3 ], [ 0, %for.body3.preheader ]
+  %0 = load i32, i32* %arrayidx
+  store i32 %0, i32* getelementptr inbounds (%struct.s, %struct.s* @S, i64 0, i32 0, i64 0, i64 0)
+  %inc = add nuw nsw i32 %j.011, 1
+  %exitcond = icmp eq i32 %inc, %N
+  br i1 %exitcond, label %for.inc4, label %for.body3
+
+for.inc4:                                         
+  %inc5 = add nuw nsw i32 %i.013, 1
+  %exitcond14 = icmp eq i32 %inc5, %N
+  br i1 %exitcond14, label %for.end6, label %for.body3.preheader
+
+for.end6:                                         
+  ret void
+}
diff --git a/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll b/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
index 8b2e43f3d868..5b81ec10f9d8 100644
--- a/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
+++ b/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
@@ -30,13 +30,13 @@ for.body:                                         ; preds = %for.body.preheader,
   %conv = trunc i64 %i.03 to i32
   %mul = mul i64 %i.03, %n
   %add = add i64 %mul, 1
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %mul1 = mul i64 %i.03, %n
   %sub = sub i64 1, %mul1
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub
-  %0 = load i32* %arrayidx2, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %sub
+  %0 = load i32, i32* %arrayidx2, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
@@ -75,13 +75,13 @@ for.body:                                         ; preds = %for.body.preheader,
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ]
   %conv = trunc i64 %i.03 to i32
   %add = add i64 %i.03, %n
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
   %add1 = add i64 %n, 1
   %sub = sub i64 %add1, %i.03
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub
-  %0 = load i32* %arrayidx2, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %sub
+  %0 = load i32, i32* %arrayidx2, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
@@ -114,12 +114,12 @@ for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
-  %arrayidx = getelementptr inbounds i32* %A, i64 %i.02
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %i.02
   store i32 %conv, i32* %arrayidx, align 4
   %sub = sub i64 6, %i.02
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %sub
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %sub
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 3
@@ -149,12 +149,12 @@ for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
-  %arrayidx = getelementptr inbounds i32* %A, i64 %i.02
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %i.02
   store i32 %conv, i32* %arrayidx, align 4
   %sub = sub i64 6, %i.02
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %sub
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %sub
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 4
@@ -184,12 +184,12 @@ for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
-  %arrayidx = getelementptr inbounds i32* %A, i64 %i.02
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %i.02
   store i32 %conv, i32* %arrayidx, align 4
   %sub = sub i64 -6, %i.02
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %sub
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %sub
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 10
@@ -224,13 +224,13 @@ for.body:                                         ; preds = %for.body.preheader,
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ]
   %conv = trunc i64 %i.03 to i32
   %mul = mul i64 %i.03, 3
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
   %0 = mul i64 %i.03, -3
   %sub = add i64 %0, 5
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %sub
-  %1 = load i32* %arrayidx2, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %sub
+  %1 = load i32, i32* %arrayidx2, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %1, i32* %B.addr.02, align 4
   %inc = add i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
@@ -264,12 +264,12 @@ for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
-  %arrayidx = getelementptr inbounds i32* %A, i64 %i.02
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %i.02
   store i32 %conv, i32* %arrayidx, align 4
   %sub = sub i64 5, %i.02
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %sub
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %sub
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 4
diff --git a/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll b/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll
index bc85e6c8b690..8adb7f7b32d5 100644
--- a/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll
+++ b/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll
@@ -26,11 +26,11 @@ for.body:                                         ; preds = %entry, %for.body
   %conv = trunc i64 %i.02 to i32
   %mul = shl i64 %i.02, 1
   %add = add i64 %mul, 10
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 10
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 10
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 30
@@ -66,11 +66,11 @@ for.body:                                         ; preds = %for.body.preheader,
   %conv = trunc i64 %i.03 to i32
   %mul = mul i64 %i.03, %n
   %add = add i64 %mul, 10
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 %conv, i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 10
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 10
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
@@ -104,11 +104,11 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = shl i64 %i.02, 1
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 10
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 10
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 5
@@ -139,11 +139,11 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = shl i64 %i.02, 1
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 10
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 10
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 6
@@ -174,11 +174,11 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = shl i64 %i.02, 1
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 10
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 10
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 7
@@ -209,11 +209,11 @@ for.body:                                         ; preds = %entry, %for.body
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
   %mul = shl i64 %i.02, 1
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 -10
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 -10
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 7
@@ -248,11 +248,11 @@ for.body:                                         ; preds = %for.body.preheader,
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ]
   %conv = trunc i64 %i.03 to i32
   %mul = mul i64 %i.03, 3
-  %arrayidx = getelementptr inbounds i32* %A, i64 %mul
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %mul
   store i32 %conv, i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 10
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 10
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
diff --git a/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll b/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll
index 2b3b2d00ecac..ac261b0dcaf5 100644
--- a/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll
+++ b/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll
@@ -24,13 +24,13 @@ for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
-  %arrayidx = getelementptr inbounds i32* %A, i64 10
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 10
   store i32 %conv, i32* %arrayidx, align 4
   %mul = shl i64 %i.02, 1
   %add = add i64 %mul, 10
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %add
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %add
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 30
@@ -64,13 +64,13 @@ for.body:                                         ; preds = %for.body.preheader,
   %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ]
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ]
   %conv = trunc i64 %i.03 to i32
-  %arrayidx = getelementptr inbounds i32* %A, i64 10
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 10
   store i32 %conv, i32* %arrayidx, align 4
   %mul = mul i64 %i.03, %n
   %add = add i64 %mul, 10
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %add
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %add
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
@@ -103,12 +103,12 @@ for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
-  %arrayidx = getelementptr inbounds i32* %A, i64 10
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 10
   store i32 %conv, i32* %arrayidx, align 4
   %mul = shl i64 %i.02, 1
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %mul
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %mul
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 5
@@ -138,12 +138,12 @@ for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
-  %arrayidx = getelementptr inbounds i32* %A, i64 10
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 10
   store i32 %conv, i32* %arrayidx, align 4
   %mul = shl i64 %i.02, 1
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %mul
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %mul
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 6
@@ -173,12 +173,12 @@ for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
-  %arrayidx = getelementptr inbounds i32* %A, i64 10
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 10
   store i32 %conv, i32* %arrayidx, align 4
   %mul = shl i64 %i.02, 1
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %mul
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %mul
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 7
@@ -208,12 +208,12 @@ for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
   %B.addr.01 = phi i32* [ %B, %entry ], [ %incdec.ptr, %for.body ]
   %conv = trunc i64 %i.02 to i32
-  %arrayidx = getelementptr inbounds i32* %A, i64 -10
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 -10
   store i32 %conv, i32* %arrayidx, align 4
   %mul = shl i64 %i.02, 1
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %mul
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.01, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %mul
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.01, i64 1
   store i32 %0, i32* %B.addr.01, align 4
   %inc = add i64 %i.02, 1
   %exitcond = icmp ne i64 %inc, 7
@@ -247,12 +247,12 @@ for.body:                                         ; preds = %for.body.preheader,
   %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ]
   %B.addr.02 = phi i32* [ %incdec.ptr, %for.body ], [ %B, %for.body.preheader ]
   %conv = trunc i64 %i.03 to i32
-  %arrayidx = getelementptr inbounds i32* %A, i64 10
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 10
   store i32 %conv, i32* %arrayidx, align 4
   %mul = mul i64 %i.03, 3
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %mul
-  %0 = load i32* %arrayidx1, align 4
-  %incdec.ptr = getelementptr inbounds i32* %B.addr.02, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %mul
+  %0 = load i32, i32* %arrayidx1, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %B.addr.02, i64 1
   store i32 %0, i32* %B.addr.02, align 4
   %inc = add i64 %i.03, 1
   %exitcond = icmp ne i64 %inc, %n
diff --git a/test/Analysis/DependenceAnalysis/ZIV.ll b/test/Analysis/DependenceAnalysis/ZIV.ll
index 5463c63ba3fb..b3216415c8e8 100644
--- a/test/Analysis/DependenceAnalysis/ZIV.ll
+++ b/test/Analysis/DependenceAnalysis/ZIV.ll
@@ -11,7 +11,7 @@ target triple = "x86_64-apple-macosx10.6.0"
 define void @z0(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp {
 entry:
   %add = add i64 %n, 1
-  %arrayidx = getelementptr inbounds i32* %A, i64 %add
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %add
   store i32 0, i32* %arrayidx, align 4
 
 ; CHECK: da analyze - none!
@@ -22,8 +22,8 @@ entry:
 ; CHECK: da analyze - none!
 
   %add1 = add i64 %n, 1
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %add1
-  %0 = load i32* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %add1
+  %0 = load i32, i32* %arrayidx2, align 4
   store i32 %0, i32* %B, align 4
   ret void
 }
@@ -34,7 +34,7 @@ entry:
 
 define void @z1(i32* %A, i32* %B, i64 %n) nounwind uwtable ssp {
 entry:
-  %arrayidx = getelementptr inbounds i32* %A, i64 %n
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %n
   store i32 0, i32* %arrayidx, align 4
 
 ; CHECK: da analyze - none!
@@ -45,8 +45,8 @@ entry:
 ; CHECK: da analyze - none!
 
   %add = add i64 %n, 1
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %add
-  %0 = load i32* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %add
+  %0 = load i32, i32* %arrayidx1, align 4
   store i32 %0, i32* %B, align 4
   ret void
 }
@@ -57,7 +57,7 @@ entry:
 
 define void @z2(i32* %A, i32* %B, i64 %n, i64 %m) nounwind uwtable ssp {
 entry:
-  %arrayidx = getelementptr inbounds i32* %A, i64 %n
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %n
   store i32 0, i32* %arrayidx, align 4
 
 ; CHECK: da analyze - none!
@@ -67,8 +67,8 @@ entry:
 ; CHECK: da analyze - confused!
 ; CHECK: da analyze - none!
 
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 %m
-  %0 = load i32* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 %m
+  %0 = load i32, i32* %arrayidx1, align 4
   store i32 %0, i32* %B, align 4
   ret void
 }
diff --git a/test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll b/test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll
new file mode 100644
index 000000000000..9dd3d557f8cd
--- /dev/null
+++ b/test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll
@@ -0,0 +1,198 @@
+; RUN: opt %s -analyze -divergence | FileCheck %s
+
+target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
+target triple = "nvptx64-nvidia-cuda"
+
+; return (n < 0 ? a + threadIdx.x : b + threadIdx.x)
+define i32 @no_diverge(i32 %n, i32 %a, i32 %b) {
+; CHECK-LABEL: Printing analysis 'Divergence Analysis' for function 'no_diverge'
+entry:
+  %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
+  %cond = icmp slt i32 %n, 0
+  br i1 %cond, label %then, label %else ; uniform
+; CHECK-NOT: DIVERGENT: br i1 %cond,
+then:
+  %a1 = add i32 %a, %tid
+  br label %merge
+else:
+  %b2 = add i32 %b, %tid
+  br label %merge
+merge:
+  %c = phi i32 [ %a1, %then ], [ %b2, %else ]
+  ret i32 %c
+}
+
+; c = a;
+; if (threadIdx.x < 5)    // divergent: data dependent
+;   c = b;
+; return c;               // c is divergent: sync dependent
+define i32 @sync(i32 %a, i32 %b) {
+; CHECK-LABEL: Printing analysis 'Divergence Analysis' for function 'sync'
+bb1:
+  %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
+  %cond = icmp slt i32 %tid, 5
+  br i1 %cond, label %bb2, label %bb3
+; CHECK: DIVERGENT: br i1 %cond,
+bb2:
+  br label %bb3
+bb3:
+  %c = phi i32 [ %a, %bb1 ], [ %b, %bb2 ] ; sync dependent on tid
+; CHECK: DIVERGENT: %c =
+  ret i32 %c
+}
+
+; c = 0;
+; if (threadIdx.x >= 5) {  // divergent
+;   c = (n < 0 ? a : b);  // c here is uniform because n is uniform
+; }
+; // c here is divergent because it is sync dependent on threadIdx.x >= 5
+; return c;
+define i32 @mixed(i32 %n, i32 %a, i32 %b) {
+; CHECK-LABEL: Printing analysis 'Divergence Analysis' for function 'mixed'
+bb1:
+  %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
+  %cond = icmp slt i32 %tid, 5
+  br i1 %cond, label %bb6, label %bb2
+; CHECK: DIVERGENT: br i1 %cond,
+bb2:
+  %cond2 = icmp slt i32 %n, 0
+  br i1 %cond2, label %bb4, label %bb3
+bb3:
+  br label %bb5
+bb4:
+  br label %bb5
+bb5:
+  %c = phi i32 [ %a, %bb3 ], [ %b, %bb4 ]
+; CHECK-NOT: DIVERGENT: %c =
+  br label %bb6
+bb6:
+  %c2 = phi i32 [ 0, %bb1], [ %c, %bb5 ]
+; CHECK: DIVERGENT: %c2 =
+  ret i32 %c2
+}
+
+; We conservatively treats all parameters of a __device__ function as divergent.
+define i32 @device(i32 %n, i32 %a, i32 %b) {
+; CHECK-LABEL: Printing analysis 'Divergence Analysis' for function 'device'
+; CHECK: DIVERGENT: i32 %n
+; CHECK: DIVERGENT: i32 %a
+; CHECK: DIVERGENT: i32 %b
+entry:
+  %cond = icmp slt i32 %n, 0
+  br i1 %cond, label %then, label %else
+; CHECK: DIVERGENT: br i1 %cond,
+then:
+  br label %merge
+else:
+  br label %merge
+merge:
+  %c = phi i32 [ %a, %then ], [ %b, %else ]
+  ret i32 %c
+}
+
+; int i = 0;
+; do {
+;   i++;                  // i here is uniform
+; } while (i < laneid);
+; return i == 10 ? 0 : 1; // i here is divergent
+;
+; The i defined in the loop is used outside.
+define i32 @loop() {
+; CHECK-LABEL: Printing analysis 'Divergence Analysis' for function 'loop'
+entry:
+  %laneid = call i32 @llvm.ptx.read.laneid()
+  br label %loop
+loop:
+  %i = phi i32 [ 0, %entry ], [ %i1, %loop ]
+; CHECK-NOT: DIVERGENT: %i =
+  %i1 = add i32 %i, 1
+  %exit_cond = icmp sge i32 %i1, %laneid
+  br i1 %exit_cond, label %loop_exit, label %loop
+loop_exit:
+  %cond = icmp eq i32 %i, 10
+  br i1 %cond, label %then, label %else
+; CHECK: DIVERGENT: br i1 %cond,
+then:
+  ret i32 0
+else:
+  ret i32 1
+}
+
+; Same as @loop, but the loop is in the LCSSA form.
+define i32 @lcssa() {
+; CHECK-LABEL: Printing analysis 'Divergence Analysis' for function 'lcssa'
+entry:
+  %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
+  br label %loop
+loop:
+  %i = phi i32 [ 0, %entry ], [ %i1, %loop ]
+; CHECK-NOT: DIVERGENT: %i =
+  %i1 = add i32 %i, 1
+  %exit_cond = icmp sge i32 %i1, %tid
+  br i1 %exit_cond, label %loop_exit, label %loop
+loop_exit:
+  %i.lcssa = phi i32 [ %i, %loop ]
+; CHECK: DIVERGENT: %i.lcssa =
+  %cond = icmp eq i32 %i.lcssa, 10
+  br i1 %cond, label %then, label %else
+; CHECK: DIVERGENT: br i1 %cond,
+then:
+  ret i32 0
+else:
+  ret i32 1
+}
+
+; This test contains an unstructured loop.
+;           +-------------- entry ----------------+
+;           |                                     |
+;           V                                     V
+; i1 = phi(0, i3)                            i2 = phi(0, i3)
+;     j1 = i1 + 1 ---> i3 = phi(j1, j2) <--- j2 = i2 + 2
+;           ^                 |                   ^
+;           |                 V                   |
+;           +-------- switch (tid / i3) ----------+
+;                             |
+;                             V
+;                        if (i3 == 5) // divergent
+; because sync dependent on (tid / i3).
+define i32 @unstructured_loop(i1 %entry_cond) {
+; CHECK-LABEL: Printing analysis 'Divergence Analysis' for function 'unstructured_loop'
+entry:
+  %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
+  br i1 %entry_cond, label %loop_entry_1, label %loop_entry_2
+loop_entry_1:
+  %i1 = phi i32 [ 0, %entry ], [ %i3, %loop_latch ]
+  %j1 = add i32 %i1, 1
+  br label %loop_body
+loop_entry_2:
+  %i2 = phi i32 [ 0, %entry ], [ %i3, %loop_latch ]
+  %j2 = add i32 %i2, 2
+  br label %loop_body
+loop_body:
+  %i3 = phi i32 [ %j1, %loop_entry_1 ], [ %j2, %loop_entry_2 ]
+  br label %loop_latch
+loop_latch:
+  %div = sdiv i32 %tid, %i3
+  switch i32 %div, label %branch [ i32 1, label %loop_entry_1
+                                   i32 2, label %loop_entry_2 ]
+branch:
+  %cmp = icmp eq i32 %i3, 5
+  br i1 %cmp, label %then, label %else
+; CHECK: DIVERGENT: br i1 %cmp,
+then:
+  ret i32 0
+else:
+  ret i32 1
+}
+
+declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
+declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
+declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
+declare i32 @llvm.ptx.read.laneid()
+
+!nvvm.annotations = !{!0, !1, !2, !3, !4}
+!0 = !{i32 (i32, i32, i32)* @no_diverge, !"kernel", i32 1}
+!1 = !{i32 (i32, i32)* @sync, !"kernel", i32 1}
+!2 = !{i32 (i32, i32, i32)* @mixed, !"kernel", i32 1}
+!3 = !{i32 ()* @loop, !"kernel", i32 1}
+!4 = !{i32 (i1)* @unstructured_loop, !"kernel", i32 1}
diff --git a/test/Analysis/DivergenceAnalysis/NVPTX/lit.local.cfg b/test/Analysis/DivergenceAnalysis/NVPTX/lit.local.cfg
new file mode 100644
index 000000000000..2cb98eb371b2
--- /dev/null
+++ b/test/Analysis/DivergenceAnalysis/NVPTX/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'NVPTX' in config.root.targets:
+    config.unsupported = True
diff --git a/test/Analysis/Dominators/invoke.ll b/test/Analysis/Dominators/invoke.ll
index da0b2461656c..ce5f992d8f4e 100644
--- a/test/Analysis/Dominators/invoke.ll
+++ b/test/Analysis/Dominators/invoke.ll
@@ -7,7 +7,7 @@ define void @f() {
   invoke void @__dynamic_cast()
           to label %bb1 unwind label %bb2
 bb1:
-  %Hidden = getelementptr inbounds i32* %v1, i64 1
+  %Hidden = getelementptr inbounds i32, i32* %v1, i64 1
   ret void
 bb2:
   %lpad.loopexit80 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
diff --git a/test/Analysis/GlobalsModRef/2008-09-03-ReadGlobals.ll b/test/Analysis/GlobalsModRef/2008-09-03-ReadGlobals.ll
index d51c159a9117..513ec86ef031 100644
--- a/test/Analysis/GlobalsModRef/2008-09-03-ReadGlobals.ll
+++ b/test/Analysis/GlobalsModRef/2008-09-03-ReadGlobals.ll
@@ -3,7 +3,7 @@
 @g = internal global i32 0		; <i32*> [#uses=2]
 
 define i32 @r() {
-	%tmp = load i32* @g		; <i32> [#uses=1]
+	%tmp = load i32, i32* @g		; <i32> [#uses=1]
 	ret i32 %tmp
 }
 
diff --git a/test/Analysis/GlobalsModRef/aliastest.ll b/test/Analysis/GlobalsModRef/aliastest.ll
index 4cfed71bfb76..3474e130de8c 100644
--- a/test/Analysis/GlobalsModRef/aliastest.ll
+++ b/test/Analysis/GlobalsModRef/aliastest.ll
@@ -9,6 +9,6 @@ define i32 @test(i32* %P) {
 ; CHECK-NEXT: ret i32 7
 	store i32 7, i32* %P
 	store i32 12, i32* @X
-	%V = load i32* %P		; <i32> [#uses=1]
+	%V = load i32, i32* %P		; <i32> [#uses=1]
 	ret i32 %V
 }
diff --git a/test/Analysis/GlobalsModRef/chaining-analysis.ll b/test/Analysis/GlobalsModRef/chaining-analysis.ll
index aeb76e42d295..26671daf3480 100644
--- a/test/Analysis/GlobalsModRef/chaining-analysis.ll
+++ b/test/Analysis/GlobalsModRef/chaining-analysis.ll
@@ -14,7 +14,7 @@ define i32 @test(i32* %P) {
 ; CHECK-NEXT: ret i32 12
 	store i32 12, i32* @X
 	call double @doesnotmodX( double 1.000000e+00 )		; <double>:1 [#uses=0]
-	%V = load i32* @X		; <i32> [#uses=1]
+	%V = load i32, i32* @X		; <i32> [#uses=1]
 	ret i32 %V
 }
 
diff --git a/test/Analysis/GlobalsModRef/indirect-global.ll b/test/Analysis/GlobalsModRef/indirect-global.ll
index 48ac6dd1d167..028132324674 100644
--- a/test/Analysis/GlobalsModRef/indirect-global.ll
+++ b/test/Analysis/GlobalsModRef/indirect-global.ll
@@ -12,11 +12,11 @@ define void @test() {
 
 define i32 @test1(i32* %P) {
 ; CHECK: ret i32 0
-	%g1 = load i32** @G		; <i32*> [#uses=2]
-	%h1 = load i32* %g1		; <i32> [#uses=1]
+	%g1 = load i32*, i32** @G		; <i32*> [#uses=2]
+	%h1 = load i32, i32* %g1		; <i32> [#uses=1]
 	store i32 123, i32* %P
-	%g2 = load i32** @G		; <i32*> [#uses=0]
-	%h2 = load i32* %g1		; <i32> [#uses=1]
+	%g2 = load i32*, i32** @G		; <i32*> [#uses=0]
+	%h2 = load i32, i32* %g1		; <i32> [#uses=1]
 	%X = sub i32 %h1, %h2		; <i32> [#uses=1]
 	ret i32 %X
 }
diff --git a/test/Analysis/GlobalsModRef/modreftest.ll b/test/Analysis/GlobalsModRef/modreftest.ll
index 3eed916e83b4..74101e23bed9 100644
--- a/test/Analysis/GlobalsModRef/modreftest.ll
+++ b/test/Analysis/GlobalsModRef/modreftest.ll
@@ -9,7 +9,7 @@ define i32 @test(i32* %P) {
 ; CHECK-NEXT: ret i32 12
 	store i32 12, i32* @X
 	call void @doesnotmodX( )
-	%V = load i32* @X		; <i32> [#uses=1]
+	%V = load i32, i32* @X		; <i32> [#uses=1]
 	ret i32 %V
 }
 
diff --git a/test/Analysis/GlobalsModRef/pr12351.ll b/test/Analysis/GlobalsModRef/pr12351.ll
index c221f4c087f8..8f922770b306 100644
--- a/test/Analysis/GlobalsModRef/pr12351.ll
+++ b/test/Analysis/GlobalsModRef/pr12351.ll
@@ -9,7 +9,7 @@ define void @foo(i8* %x, i8* %y) {
 define void @bar(i8* %y, i8* %z) {
   %x = alloca i8
   call void @foo(i8* %x, i8* %y)
-  %t = load i8* %x
+  %t = load i8, i8* %x
   store i8 %t, i8* %y
 ; CHECK: store i8 %t, i8* %y
   ret void
@@ -19,8 +19,8 @@ define void @bar(i8* %y, i8* %z) {
 define i32 @foo2() {
   %foo = alloca i32
   call void @bar2(i32* %foo)
-  %t0 = load i32* %foo, align 4
-; CHECK: %t0 = load i32* %foo, align 4
+  %t0 = load i32, i32* %foo, align 4
+; CHECK: %t0 = load i32, i32* %foo, align 4
   ret i32 %t0
 }
 
diff --git a/test/Analysis/GlobalsModRef/volatile-instrs.ll b/test/Analysis/GlobalsModRef/volatile-instrs.ll
index 46d3d768bd07..5dd47bca3a08 100644
--- a/test/Analysis/GlobalsModRef/volatile-instrs.ll
+++ b/test/Analysis/GlobalsModRef/volatile-instrs.ll
@@ -22,9 +22,9 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
 define i32 @main() nounwind uwtable ssp {
 main_entry:
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (%struct.anon* @b to i8*), i8* bitcast (%struct.anon* @a to i8*), i64 12, i32 4, i1 false)
-  %0 = load volatile i32* getelementptr inbounds (%struct.anon* @b, i64 0, i32 0), align 4
+  %0 = load volatile i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @b, i64 0, i32 0), align 4
   store i32 %0, i32* @c, align 4
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (%struct.anon* @b to i8*), i8* bitcast (%struct.anon* @a to i8*), i64 12, i32 4, i1 false) nounwind
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32 %0) nounwind
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %0) nounwind
   ret i32 0
 }
diff --git a/test/Analysis/LazyCallGraph/basic.ll b/test/Analysis/LazyCallGraph/basic.ll
index b8108d99ed6f..7c13d2bef390 100644
--- a/test/Analysis/LazyCallGraph/basic.ll
+++ b/test/Analysis/LazyCallGraph/basic.ll
@@ -90,7 +90,7 @@ next:
   select i1 true, void ()* @f3, void ()* @f4
   store void ()* @f5, void ()** %x
   call void @f6()
-  call void (void ()*, void ()*)* bitcast (void ()* @f7 to void (void ()*, void ()*)*)(void ()* @f8, void ()* @f9)
+  call void (void ()*, void ()*) bitcast (void ()* @f7 to void (void ()*, void ()*)*)(void ()* @f8, void ()* @f9)
   invoke void @f10() to label %exit unwind label %unwind
 
 exit:
@@ -118,10 +118,10 @@ define void @test2() {
 ; CHECK-NEXT: -> f1
 ; CHECK-NOT: ->
 
-  load i8** bitcast (void ()** @g to i8**)
-  load i8** bitcast (void ()** getelementptr ([4 x void ()*]* @g1, i32 0, i32 2) to i8**)
-  load i8** bitcast (void ()** getelementptr ({i8, void ()*, i8}* @g2, i32 0, i32 1) to i8**)
-  load i8** bitcast (void ()** @h to i8**)
+  load i8*, i8** bitcast (void ()** @g to i8**)
+  load i8*, i8** bitcast (void ()** getelementptr ([4 x void ()*], [4 x void ()*]* @g1, i32 0, i32 2) to i8**)
+  load i8*, i8** bitcast (void ()** getelementptr ({i8, void ()*, i8}, {i8, void ()*, i8}* @g2, i32 0, i32 1) to i8**)
+  load i8*, i8** bitcast (void ()** @h to i8**)
   ret void
 }
 
diff --git a/test/Analysis/Lint/cppeh-catch-intrinsics-clean.ll b/test/Analysis/Lint/cppeh-catch-intrinsics-clean.ll
new file mode 100644
index 000000000000..8cd44c86a72a
--- /dev/null
+++ b/test/Analysis/Lint/cppeh-catch-intrinsics-clean.ll
@@ -0,0 +1,109 @@
+; RUN: opt -lint -disable-output < %s
+
+; This test is meant to prove that the verifier does not report errors for correct
+; use of the llvm.eh.begincatch and llvm.eh.endcatch intrinsics.
+
+target triple = "x86_64-pc-windows-msvc"
+
+declare void @llvm.eh.begincatch(i8*, i8*)
+
+declare void @llvm.eh.endcatch()
+
+@_ZTIi = external constant i8*
+
+; Function Attrs: uwtable
+define void @test_ref_clean() {
+entry:
+  invoke void @_Z9may_throwv()
+          to label %try.cont unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %exn = extractvalue { i8*, i32 } %0, 0
+  %sel = extractvalue { i8*, i32 } %0, 1
+  %1 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*))
+  %matches = icmp eq i32 %sel, %1
+  br i1 %matches, label %catch, label %eh.resume
+
+catch:                                            ; preds = %lpad
+  call void @llvm.eh.begincatch(i8* %exn, i8* null)
+  call void @_Z10handle_intv()
+  br label %invoke.cont2
+
+invoke.cont2:                                     ; preds = %catch
+  call void @llvm.eh.endcatch()
+  br label %try.cont
+
+try.cont:                                         ; preds = %invoke.cont2, %entry
+  ret void
+
+eh.resume:                                        ; preds = %catch.dispatch
+  resume { i8*, i32 } %0
+}
+
+; Function Attrs: uwtable
+define void @test_ref_clean_multibranch() {
+entry:
+  invoke void @_Z9may_throwv()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:
+  invoke void @_Z9may_throwv()
+          to label %invoke.cont unwind label %lpad1
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %exn = extractvalue { i8*, i32 } %0, 0
+  %sel = extractvalue { i8*, i32 } %0, 1
+  %1 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*))
+  %matches = icmp eq i32 %sel, %1
+  br i1 %matches, label %catch, label %eh.resume
+
+  invoke void @_Z9may_throwv()
+          to label %try.cont unwind label %lpad
+
+lpad1:                                            ; preds = %entry
+  %l1.0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+		  cleanup
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %exn1 = extractvalue { i8*, i32 } %l1.0, 0
+  %sel1 = extractvalue { i8*, i32 } %l1.0, 1
+  %l1.1 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*))
+  %matchesl1 = icmp eq i32 %sel1, %l1.1
+  br i1 %matchesl1, label %catch, label %eh.resume
+
+catch:                                            ; preds = %lpad, %lpad1
+  %exn2 = phi i8* [%exn, %lpad], [%exn1, %lpad1]
+  %sel2 = phi i32 [%sel, %lpad], [%sel1, %lpad1]
+  call void @llvm.eh.begincatch(i8* %exn2, i8* null)
+  call void @_Z10handle_intv()
+  %matches1 = icmp eq i32 %sel2, 0
+  br i1 %matches1, label %invoke.cont2, label %invoke.cont3
+
+invoke.cont2:                                     ; preds = %catch
+  call void @llvm.eh.endcatch()
+  br label %try.cont
+
+invoke.cont3:                                     ; preds = %catch
+  call void @llvm.eh.endcatch()
+  br label %eh.resume
+
+try.cont:                                         ; preds = %invoke.cont2, %entry
+  ret void
+
+eh.resume:                                        ; preds = %catch.dispatch
+  %lpad.val = insertvalue { i8*, i32 } undef, i32 0, 1
+  resume { i8*, i32 } %lpad.val
+}
+
+declare void @_Z9may_throwv()
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*)
+
+declare void @_Z10handle_intv()
+
diff --git a/test/Analysis/Lint/cppeh-catch-intrinsics.ll b/test/Analysis/Lint/cppeh-catch-intrinsics.ll
new file mode 100644
index 000000000000..3a0c487c290b
--- /dev/null
+++ b/test/Analysis/Lint/cppeh-catch-intrinsics.ll
@@ -0,0 +1,278 @@
+; RUN: opt -lint -disable-output < %s 2>&1 | FileCheck %s
+
+; This test is meant to prove that the Verifier is able to identify a variety
+; of errors with the llvm.eh.begincatch and llvm.eh.endcatch intrinsics.
+; See cppeh-catch-intrinsics-clean for correct uses.
+
+target triple = "x86_64-pc-windows-msvc"
+
+declare void @llvm.eh.begincatch(i8*, i8*)
+
+declare void @llvm.eh.endcatch()
+
+@_ZTIi = external constant i8*
+
+; Function Attrs: uwtable
+define void @test_missing_endcatch() {
+; CHECK: Some paths from llvm.eh.begincatch may not reach llvm.eh.endcatch
+; CHECK-NEXT: call void @llvm.eh.begincatch(i8* %exn, i8* null)
+entry:
+  invoke void @_Z9may_throwv()
+          to label %try.cont unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %exn = extractvalue { i8*, i32 } %0, 0
+  %sel = extractvalue { i8*, i32 } %0, 1
+  %1 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*))
+  %matches = icmp eq i32 %sel, %1
+  br i1 %matches, label %catch, label %eh.resume
+
+catch:                                            ; preds = %lpad
+  call void @llvm.eh.begincatch(i8* %exn, i8* null)
+  call void @_Z10handle_intv()
+  br label %invoke.cont2
+
+invoke.cont2:                                     ; preds = %catch
+  br label %try.cont
+
+try.cont:                                         ; preds = %invoke.cont2, %entry
+  ret void
+
+eh.resume:                                        ; preds = %catch.dispatch
+  resume { i8*, i32 } %0
+}
+
+; Function Attrs: uwtable
+define void @test_missing_begincatch() {
+; CHECK: llvm.eh.endcatch may be reachable without passing llvm.eh.begincatch
+; CHECK-NEXT:  call void @llvm.eh.endcatch()
+entry:
+  invoke void @_Z9may_throwv()
+          to label %try.cont unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %exn = extractvalue { i8*, i32 } %0, 0
+  %sel = extractvalue { i8*, i32 } %0, 1
+  %1 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*))
+  %matches = icmp eq i32 %sel, %1
+  br i1 %matches, label %catch, label %eh.resume
+
+catch:                                            ; preds = %lpad
+  call void @_Z10handle_intv()
+  br label %invoke.cont2
+
+invoke.cont2:                                     ; preds = %catch
+  call void @llvm.eh.endcatch()
+  br label %try.cont
+
+try.cont:                                         ; preds = %invoke.cont2, %entry
+  ret void
+
+eh.resume:                                        ; preds = %catch.dispatch
+  resume { i8*, i32 } %0
+}
+
+; Function Attrs: uwtable
+define void @test_multiple_begin() {
+; CHECK: llvm.eh.begincatch may be called a second time before llvm.eh.endcatch
+; CHECK-NEXT: call void @llvm.eh.begincatch(i8* %exn, i8* null)
+; CHECK-NEXT: call void @llvm.eh.begincatch(i8* %exn, i8* null)
+entry:
+  invoke void @_Z9may_throwv()
+          to label %try.cont unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %exn = extractvalue { i8*, i32 } %0, 0
+  %sel = extractvalue { i8*, i32 } %0, 1
+  %1 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*))
+  %matches = icmp eq i32 %sel, %1
+  br i1 %matches, label %catch, label %eh.resume
+
+catch:                                            ; preds = %lpad
+  call void @llvm.eh.begincatch(i8* %exn, i8* null)
+  call void @_Z10handle_intv()
+  br label %invoke.cont2
+
+invoke.cont2:                                     ; preds = %catch
+  call void @llvm.eh.begincatch(i8* %exn, i8* null)
+  call void @llvm.eh.endcatch()
+  br label %try.cont
+
+try.cont:                                         ; preds = %invoke.cont2, %entry
+  ret void
+
+eh.resume:                                        ; preds = %catch.dispatch
+  resume { i8*, i32 } %0
+}
+
+; Function Attrs: uwtable
+define void @test_multiple_end() {
+; CHECK: llvm.eh.endcatch may be called a second time after llvm.eh.begincatch
+; CHECK-NEXT:  call void @llvm.eh.endcatch()
+; CHECK-NEXT:  call void @llvm.eh.endcatch()
+entry:
+  invoke void @_Z9may_throwv()
+          to label %try.cont unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %exn = extractvalue { i8*, i32 } %0, 0
+  %sel = extractvalue { i8*, i32 } %0, 1
+  %1 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*))
+  %matches = icmp eq i32 %sel, %1
+  br i1 %matches, label %catch, label %eh.resume
+
+catch:                                            ; preds = %lpad
+  call void @llvm.eh.begincatch(i8* %exn, i8* null)
+  call void @_Z10handle_intv()
+  call void @llvm.eh.endcatch()
+  br label %invoke.cont2
+
+invoke.cont2:                                     ; preds = %catch
+  call void @llvm.eh.endcatch()
+  br label %try.cont
+
+try.cont:                                         ; preds = %invoke.cont2, %entry
+  ret void
+
+eh.resume:                                        ; preds = %catch.dispatch
+  resume { i8*, i32 } %0
+}
+
+
+; Function Attrs: uwtable
+define void @test_begincatch_without_lpad() {
+; CHECK: llvm.eh.begincatch may be reachable without passing a landingpad
+; CHECK-NEXT: call void @llvm.eh.begincatch(i8* %exn, i8* null)
+entry:
+  %exn = alloca i8
+  call void @llvm.eh.begincatch(i8* %exn, i8* null)
+  call void @_Z10handle_intv()
+  br label %invoke.cont2
+
+invoke.cont2:                                     ; preds = %catch
+  call void @llvm.eh.endcatch()
+  br label %try.cont
+
+try.cont:                                         ; preds = %invoke.cont2, %entry
+  ret void
+}
+
+; Function Attrs: uwtable
+define void @test_branch_to_begincatch_with_no_lpad(i32 %fake.sel) {
+; CHECK: llvm.eh.begincatch may be reachable without passing a landingpad
+; CHECK-NEXT: call void @llvm.eh.begincatch(i8* %exn2, i8* null)
+entry:
+  %fake.exn = alloca i8
+  invoke void @_Z9may_throwv()
+          to label %catch unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %exn = extractvalue { i8*, i32 } %0, 0
+  %sel = extractvalue { i8*, i32 } %0, 1
+  %1 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*))
+  %matches = icmp eq i32 %sel, %1
+  br i1 %matches, label %catch, label %eh.resume
+
+  invoke void @_Z9may_throwv()
+          to label %try.cont unwind label %lpad
+
+catch:                                            ; preds = %lpad, %entry
+  %exn2 = phi i8* [%exn, %lpad], [%fake.exn, %entry]
+  %sel2 = phi i32 [%sel, %lpad], [%fake.sel, %entry]
+  call void @llvm.eh.begincatch(i8* %exn2, i8* null)
+  call void @_Z10handle_intv()
+  %matches1 = icmp eq i32 %sel2, 0
+  br i1 %matches1, label %invoke.cont2, label %invoke.cont3
+
+invoke.cont2:                                     ; preds = %catch
+  call void @llvm.eh.endcatch()
+  br label %try.cont
+
+invoke.cont3:                                     ; preds = %catch
+  call void @llvm.eh.endcatch()
+  br label %eh.resume
+
+try.cont:                                         ; preds = %invoke.cont2
+  ret void
+
+eh.resume:                                        ; preds = %catch.dispatch
+  %lpad.val = insertvalue { i8*, i32 } undef, i32 0, 1
+  resume { i8*, i32 } %lpad.val
+}
+
+; Function Attrs: uwtable
+define void @test_branch_missing_endcatch() {
+; CHECK: Some paths from llvm.eh.begincatch may not reach llvm.eh.endcatch
+; CHECK-NEXT: call void @llvm.eh.begincatch(i8* %exn2, i8* null)
+entry:
+  invoke void @_Z9may_throwv()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:
+  invoke void @_Z9may_throwv()
+          to label %invoke.cont unwind label %lpad1
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %exn = extractvalue { i8*, i32 } %0, 0
+  %sel = extractvalue { i8*, i32 } %0, 1
+  %1 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*))
+  %matches = icmp eq i32 %sel, %1
+  br i1 %matches, label %catch, label %eh.resume
+
+  invoke void @_Z9may_throwv()
+          to label %try.cont unwind label %lpad
+
+lpad1:                                            ; preds = %entry
+  %l1.0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+		  cleanup
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %exn1 = extractvalue { i8*, i32 } %l1.0, 0
+  %sel1 = extractvalue { i8*, i32 } %l1.0, 1
+  %l1.1 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*))
+  %matchesl1 = icmp eq i32 %sel1, %l1.1
+  br i1 %matchesl1, label %catch, label %eh.resume
+
+catch:                                            ; preds = %lpad, %lpad1
+  %exn2 = phi i8* [%exn, %lpad], [%exn1, %lpad1]
+  %sel2 = phi i32 [%sel, %lpad], [%sel1, %lpad1]
+  call void @llvm.eh.begincatch(i8* %exn2, i8* null)
+  call void @_Z10handle_intv()
+  %matches1 = icmp eq i32 %sel2, 0
+  br i1 %matches1, label %invoke.cont2, label %invoke.cont3
+
+invoke.cont2:                                     ; preds = %catch
+  call void @llvm.eh.endcatch()
+  br label %try.cont
+
+invoke.cont3:                                     ; preds = %catch
+  br label %eh.resume
+
+try.cont:                                         ; preds = %invoke.cont2, %entry
+  ret void
+
+eh.resume:                                        ; preds = %catch.dispatch
+  %lpad.val = insertvalue { i8*, i32 } undef, i32 0, 1
+  resume { i8*, i32 } %lpad.val
+}
+
+declare void @_Z9may_throwv()
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*)
+
+declare void @_Z10handle_intv()
+
diff --git a/test/Analysis/LoopAccessAnalysis/backward-dep-different-types.ll b/test/Analysis/LoopAccessAnalysis/backward-dep-different-types.ll
new file mode 100644
index 000000000000..5d4fb7d3d66c
--- /dev/null
+++ b/test/Analysis/LoopAccessAnalysis/backward-dep-different-types.ll
@@ -0,0 +1,49 @@
+; RUN: opt -loop-accesses -analyze < %s | FileCheck %s
+
+; In this loop just because we access A through different types (int, float)
+; we still have a dependence cycle:
+;
+;   for (i = 0; i < n; i++) {
+;    A_float = (float *) A;
+;    A_float[i + 1] = A[i] * B[i];
+;   }
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+; CHECK: Report: unsafe dependent memory operations in loop
+; CHECK-NOT: Memory dependences are safe
+
+@B = common global i32* null, align 8
+@A = common global i32* null, align 8
+
+define void @f() {
+entry:
+  %a = load i32*, i32** @A, align 8
+  %b = load i32*, i32** @B, align 8
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %storemerge3 = phi i64 [ 0, %entry ], [ %add, %for.body ]
+
+  %arrayidxA = getelementptr inbounds i32, i32* %a, i64 %storemerge3
+  %loadA = load i32, i32* %arrayidxA, align 2
+
+  %arrayidxB = getelementptr inbounds i32, i32* %b, i64 %storemerge3
+  %loadB = load i32, i32* %arrayidxB, align 2
+
+  %mul = mul i32 %loadB, %loadA
+
+  %add = add nuw nsw i64 %storemerge3, 1
+
+  %a_float = bitcast i32* %a to float*
+  %arrayidxA_plus_2 = getelementptr inbounds float, float* %a_float, i64 %add
+  %mul_float = sitofp i32 %mul to float
+  store float %mul_float, float* %arrayidxA_plus_2, align 2
+
+  %exitcond = icmp eq i64 %add, 20
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
diff --git a/test/Analysis/LoopAccessAnalysis/resort-to-memchecks-only.ll b/test/Analysis/LoopAccessAnalysis/resort-to-memchecks-only.ll
new file mode 100644
index 000000000000..64f7729fa18a
--- /dev/null
+++ b/test/Analysis/LoopAccessAnalysis/resort-to-memchecks-only.ll
@@ -0,0 +1,57 @@
+; RUN: opt -loop-accesses -analyze < %s | FileCheck %s
+
+; We give up analyzing the dependences in this loop due to non-constant
+; distance between A[i+offset] and A[i] and add memchecks to prove
+; independence.  Make sure that no interesting dependences are reported in
+; this case.
+;
+;   for (i = 0; i < n; i++)
+;    A[i + offset] = A[i] * B[i] * C[i];
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+; CHECK: Memory dependences are safe with run-time checks
+; CHECK-NEXT: Interesting Dependences:
+; CHECK-NEXT: Run-time memory checks:
+; CHECK-NEXT: 0:
+; CHECK-NEXT:   %arrayidxA2 = getelementptr inbounds i16, i16* %a, i64 %idx
+; CHECK-NEXT:   %arrayidxA = getelementptr inbounds i16, i16* %a, i64 %indvar
+
+@B = common global i16* null, align 8
+@A = common global i16* null, align 8
+@C = common global i16* null, align 8
+
+define void @f(i64 %offset) {
+entry:
+  %a = load i16*, i16** @A, align 8
+  %b = load i16*, i16** @B, align 8
+  %c = load i16*, i16** @C, align 8
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %indvar = phi i64 [ 0, %entry ], [ %add, %for.body ]
+
+  %arrayidxA = getelementptr inbounds i16, i16* %a, i64 %indvar
+  %loadA = load i16, i16* %arrayidxA, align 2
+
+  %arrayidxB = getelementptr inbounds i16, i16* %b, i64 %indvar
+  %loadB = load i16, i16* %arrayidxB, align 2
+
+  %arrayidxC = getelementptr inbounds i16, i16* %c, i64 %indvar
+  %loadC = load i16, i16* %arrayidxC, align 2
+
+  %mul = mul i16 %loadB, %loadA
+  %mul1 = mul i16 %mul, %loadC
+
+  %idx = add i64 %indvar, %offset
+  %arrayidxA2 = getelementptr inbounds i16, i16* %a, i64 %idx
+  store i16 %mul1, i16* %arrayidxA2, align 2
+
+  %add = add nuw nsw i64 %indvar, 1
+  %exitcond = icmp eq i64 %add, 20
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
diff --git a/test/Analysis/LoopAccessAnalysis/safe-no-checks.ll b/test/Analysis/LoopAccessAnalysis/safe-no-checks.ll
new file mode 100644
index 000000000000..fa70c024a9c5
--- /dev/null
+++ b/test/Analysis/LoopAccessAnalysis/safe-no-checks.ll
@@ -0,0 +1,43 @@
+; RUN: opt -basicaa -loop-accesses -analyze < %s | FileCheck %s
+
+; If the arrays don't alias this loop is safe with no memchecks:
+;   for (i = 0; i < n; i++)
+;    A[i] = A[i+1] * B[i] * C[i];
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+; CHECK: Memory dependences are safe{{$}}
+
+define void @f(i16* noalias %a,
+               i16* noalias %b,
+               i16* noalias %c) {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %ind = phi i64 [ 0, %entry ], [ %add, %for.body ]
+
+  %add = add nuw nsw i64 %ind, 1
+
+  %arrayidxA_plus_2 = getelementptr inbounds i16, i16* %a, i64 %add
+  %loadA_plus_2 = load i16, i16* %arrayidxA_plus_2, align 2
+
+  %arrayidxB = getelementptr inbounds i16, i16* %b, i64 %ind
+  %loadB = load i16, i16* %arrayidxB, align 2
+
+  %arrayidxC = getelementptr inbounds i16, i16* %c, i64 %ind
+  %loadC = load i16, i16* %arrayidxC, align 2
+
+  %mul = mul i16 %loadB, %loadA_plus_2
+  %mul1 = mul i16 %mul, %loadC
+
+  %arrayidxA = getelementptr inbounds i16, i16* %a, i64 %ind
+  store i16 %mul1, i16* %arrayidxA, align 2
+
+  %exitcond = icmp eq i64 %add, 20
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
diff --git a/test/Analysis/LoopAccessAnalysis/store-to-invariant-check1.ll b/test/Analysis/LoopAccessAnalysis/store-to-invariant-check1.ll
new file mode 100644
index 000000000000..8ab8ab2a55b6
--- /dev/null
+++ b/test/Analysis/LoopAccessAnalysis/store-to-invariant-check1.ll
@@ -0,0 +1,53 @@
+; RUN: opt < %s -loop-accesses -analyze | FileCheck %s
+
+; Test to confirm LAA will find store to invariant address.
+; Inner loop has a store to invariant address.
+;
+;  for(; i < itr; i++) {
+;    for(; j < itr; j++) {
+;      var1[i] = var2[j] + var1[i];
+;    }
+;  }
+
+; CHECK: Store to invariant address was found in loop.
+; CHECK-NOT: Store to invariant address was not found in loop.
+
+define i32 @foo(i32* nocapture %var1, i32* nocapture readonly %var2, i32 %itr) #0 {
+entry:
+  %cmp20 = icmp eq i32 %itr, 0
+  br i1 %cmp20, label %for.end10, label %for.cond1.preheader
+
+for.cond1.preheader:                              ; preds = %entry, %for.inc8
+  %indvars.iv23 = phi i64 [ %indvars.iv.next24, %for.inc8 ], [ 0, %entry ]
+  %j.022 = phi i32 [ %j.1.lcssa, %for.inc8 ], [ 0, %entry ]
+  %cmp218 = icmp ult i32 %j.022, %itr
+  br i1 %cmp218, label %for.body3.lr.ph, label %for.inc8
+
+for.body3.lr.ph:                                  ; preds = %for.cond1.preheader
+  %arrayidx5 = getelementptr inbounds i32, i32* %var1, i64 %indvars.iv23
+  %0 = zext i32 %j.022 to i64
+  br label %for.body3
+
+for.body3:                                        ; preds = %for.body3, %for.body3.lr.ph
+  %indvars.iv = phi i64 [ %0, %for.body3.lr.ph ], [ %indvars.iv.next, %for.body3 ]
+  %arrayidx = getelementptr inbounds i32, i32* %var2, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx, align 4
+  %2 = load i32, i32* %arrayidx5, align 4
+  %add = add nsw i32 %2, %1
+  store i32 %add, i32* %arrayidx5, align 4
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %itr
+  br i1 %exitcond, label %for.inc8, label %for.body3
+
+for.inc8:                                         ; preds = %for.body3, %for.cond1.preheader
+  %j.1.lcssa = phi i32 [ %j.022, %for.cond1.preheader ], [ %itr, %for.body3 ]
+  %indvars.iv.next24 = add nuw nsw i64 %indvars.iv23, 1
+  %lftr.wideiv25 = trunc i64 %indvars.iv.next24 to i32
+  %exitcond26 = icmp eq i32 %lftr.wideiv25, %itr
+  br i1 %exitcond26, label %for.end10, label %for.cond1.preheader
+
+for.end10:                                        ; preds = %for.inc8, %entry
+  ret i32 undef
+}
+
diff --git a/test/Analysis/LoopAccessAnalysis/store-to-invariant-check2.ll b/test/Analysis/LoopAccessAnalysis/store-to-invariant-check2.ll
new file mode 100644
index 000000000000..4da090689492
--- /dev/null
+++ b/test/Analysis/LoopAccessAnalysis/store-to-invariant-check2.ll
@@ -0,0 +1,54 @@
+; RUN: opt < %s -loop-accesses -analyze  | FileCheck %s
+
+; Test to confirm LAA will not find store to invariant address.
+; Inner loop has no store to invariant address.
+;
+;  for(; i < itr; i++) {
+;    for(; j < itr; j++) {
+;      var2[j] = var2[j] + var1[i];
+;    }
+;  }
+
+; CHECK: Store to invariant address was not found in loop.
+; CHECK-NOT: Store to invariant address was found in loop.
+
+
+define i32 @foo(i32* nocapture readonly %var1, i32* nocapture %var2, i32 %itr) #0 {
+entry:
+  %cmp20 = icmp eq i32 %itr, 0
+  br i1 %cmp20, label %for.end10, label %for.cond1.preheader
+
+for.cond1.preheader:                              ; preds = %entry, %for.inc8
+  %indvars.iv23 = phi i64 [ %indvars.iv.next24, %for.inc8 ], [ 0, %entry ]
+  %j.022 = phi i32 [ %j.1.lcssa, %for.inc8 ], [ 0, %entry ]
+  %cmp218 = icmp ult i32 %j.022, %itr
+  br i1 %cmp218, label %for.body3.lr.ph, label %for.inc8
+
+for.body3.lr.ph:                                  ; preds = %for.cond1.preheader
+  %arrayidx5 = getelementptr inbounds i32, i32* %var1, i64 %indvars.iv23
+  %0 = zext i32 %j.022 to i64
+  br label %for.body3
+
+for.body3:                                        ; preds = %for.body3, %for.body3.lr.ph
+  %indvars.iv = phi i64 [ %0, %for.body3.lr.ph ], [ %indvars.iv.next, %for.body3 ]
+  %arrayidx = getelementptr inbounds i32, i32* %var2, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx, align 4
+  %2 = load i32, i32* %arrayidx5, align 4
+  %add = add nsw i32 %2, %1
+  store i32 %add, i32* %arrayidx, align 4
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %itr
+  br i1 %exitcond, label %for.inc8, label %for.body3
+
+for.inc8:                                         ; preds = %for.body3, %for.cond1.preheader
+  %j.1.lcssa = phi i32 [ %j.022, %for.cond1.preheader ], [ %itr, %for.body3 ]
+  %indvars.iv.next24 = add nuw nsw i64 %indvars.iv23, 1
+  %lftr.wideiv25 = trunc i64 %indvars.iv.next24 to i32
+  %exitcond26 = icmp eq i32 %lftr.wideiv25, %itr
+  br i1 %exitcond26, label %for.end10, label %for.cond1.preheader
+
+for.end10:                                        ; preds = %for.inc8, %entry
+  ret i32 undef
+}
+
diff --git a/test/Analysis/LoopAccessAnalysis/store-to-invariant-check3.ll b/test/Analysis/LoopAccessAnalysis/store-to-invariant-check3.ll
new file mode 100644
index 000000000000..18315a59dc3a
--- /dev/null
+++ b/test/Analysis/LoopAccessAnalysis/store-to-invariant-check3.ll
@@ -0,0 +1,53 @@
+; RUN: opt < %s -loop-accesses -analyze | FileCheck %s
+
+; Test to confirm LAA will find store to invariant address.
+; Inner loop has a store to invariant address.
+;
+;  for(; i < itr; i++) {
+;    for(; j < itr; j++) {
+;      var1[j] = ++var2[i] + var1[j];
+;    }
+;  }
+
+; CHECK: Store to invariant address was found in loop.
+
+define void @foo(i32* nocapture %var1, i32* nocapture %var2, i32 %itr) #0 {
+entry:
+  %cmp20 = icmp sgt i32 %itr, 0
+  br i1 %cmp20, label %for.cond1.preheader, label %for.end11
+
+for.cond1.preheader:                              ; preds = %entry, %for.inc9
+  %indvars.iv23 = phi i64 [ %indvars.iv.next24, %for.inc9 ], [ 0, %entry ]
+  %j.022 = phi i32 [ %j.1.lcssa, %for.inc9 ], [ 0, %entry ]
+  %cmp218 = icmp slt i32 %j.022, %itr
+  br i1 %cmp218, label %for.body3.lr.ph, label %for.inc9
+
+for.body3.lr.ph:                                  ; preds = %for.cond1.preheader
+  %arrayidx = getelementptr inbounds i32, i32* %var2, i64 %indvars.iv23
+  %0 = sext i32 %j.022 to i64
+  br label %for.body3
+
+for.body3:                                        ; preds = %for.body3, %for.body3.lr.ph
+  %indvars.iv = phi i64 [ %0, %for.body3.lr.ph ], [ %indvars.iv.next, %for.body3 ]
+  %1 = load i32, i32* %arrayidx, align 4
+  %inc = add nsw i32 %1, 1
+  store i32 %inc, i32* %arrayidx, align 4
+  %arrayidx5 = getelementptr inbounds i32, i32* %var1, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx5, align 4
+  %add = add nsw i32 %inc, %2
+  store i32 %add, i32* %arrayidx5, align 4
+  %indvars.iv.next = add nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %itr
+  br i1 %exitcond, label %for.inc9, label %for.body3
+
+for.inc9:                                         ; preds = %for.body3, %for.cond1.preheader
+  %j.1.lcssa = phi i32 [ %j.022, %for.cond1.preheader ], [ %itr, %for.body3 ]
+  %indvars.iv.next24 = add nuw nsw i64 %indvars.iv23, 1
+  %lftr.wideiv25 = trunc i64 %indvars.iv.next24 to i32
+  %exitcond26 = icmp eq i32 %lftr.wideiv25, %itr
+  br i1 %exitcond26, label %for.end11, label %for.cond1.preheader
+
+for.end11:                                        ; preds = %for.inc9, %entry
+  ret void
+}
diff --git a/test/Analysis/LoopAccessAnalysis/underlying-objects-1.ll b/test/Analysis/LoopAccessAnalysis/underlying-objects-1.ll
new file mode 100644
index 000000000000..44820ed37222
--- /dev/null
+++ b/test/Analysis/LoopAccessAnalysis/underlying-objects-1.ll
@@ -0,0 +1,47 @@
+; RUN: opt -basicaa -loop-accesses -analyze < %s | FileCheck %s
+
+; In:
+;
+;   store_ptr = A;
+;   load_ptr = &A[2];
+;   for (i = 0; i < n; i++)
+;    *store_ptr++ = *load_ptr++ *10;  // A[i] = A[i+2] * 10
+;
+; make sure, we look through the PHI to conclude that store_ptr and load_ptr
+; both have A as their underlying object.  The dependence is safe for
+; vectorization requiring no memchecks.
+;
+; Otherwise we would try to prove independence with a memcheck that is going
+; to always fail.
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+; CHECK: Memory dependences are safe{{$}}
+
+define void @f(i8* noalias %A, i64 %width) {
+for.body.preheader:
+  %A_ahead = getelementptr inbounds i8, i8* %A, i64 2
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ %i.1, %for.body ], [ 0, %for.body.preheader ]
+  %load_ptr = phi i8* [ %load_ptr.1, %for.body ], [ %A_ahead, %for.body.preheader ]
+  %store_ptr = phi i8* [ %store_ptr.1, %for.body ], [ %A, %for.body.preheader ]
+
+  %loadA = load i8, i8* %load_ptr, align 1
+
+  %mul = mul i8 %loadA, 10
+
+  store i8 %mul, i8* %store_ptr, align 1
+
+  %load_ptr.1 = getelementptr inbounds i8, i8* %load_ptr, i64 1
+  %store_ptr.1 = getelementptr inbounds i8, i8* %store_ptr, i64 1
+  %i.1 = add nuw i64 %i, 1
+
+  %exitcond = icmp eq i64 %i.1, %width
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
diff --git a/test/Analysis/LoopAccessAnalysis/underlying-objects-2.ll b/test/Analysis/LoopAccessAnalysis/underlying-objects-2.ll
new file mode 100644
index 000000000000..d0bed68188db
--- /dev/null
+++ b/test/Analysis/LoopAccessAnalysis/underlying-objects-2.ll
@@ -0,0 +1,90 @@
+; RUN: opt -basicaa -loop-accesses -analyze < %s | FileCheck %s
+
+; This loop:
+;
+;   int **A;
+;   for (i)
+;     for (j) {
+;        A[i][j] = A[i-1][j] * B[j]
+;        B[j+1] = 2       // backward dep between this and the previous
+;     }
+;
+; is transformed by Load-PRE to stash away A[i] for the next iteration of the
+; outer loop:
+;
+;   Curr = A[0];          // Prev_0
+;   for (i: 1..N) {
+;     Prev = Curr;        // Prev = PHI (Prev_0, Curr)
+;     Curr = A[i];
+;     for (j: 0..N) {
+;        Curr[j] = Prev[j] * B[j]
+;        B[j+1] = 2       // backward dep between this and the previous
+;     }
+;   }
+;
+; Since A[i] and A[i-1] are likely to be independent, getUnderlyingObjects
+; should not assume that Curr and Prev share the same underlying object.
+;
+; If it did we would try to dependence-analyze Curr and Prev and the analysis
+; would fail with non-constant distance.
+;
+; To illustrate one of the negative consequences of this, if the loop has a
+; backward dependence we won't detect this but instead fully fall back on
+; memchecks (that is what LAA does after encountering a case of non-constant
+; distance).
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+; CHECK: for_j.body:
+; CHECK-NEXT: Report: unsafe dependent memory operations in loop
+; CHECK-NEXT: Interesting Dependences:
+; CHECK-NEXT: Backward:
+; CHECK-NEXT: %loadB = load i8, i8* %gepB, align 1 ->
+; CHECK-NEXT: store i8 2, i8* %gepB_plus_one, align 1
+
+define void @f(i8** noalias %A, i8* noalias %B, i64 %N) {
+for_i.preheader:
+  %prev_0 = load i8*, i8** %A, align 8
+  br label %for_i.body
+
+for_i.body:
+  %i = phi i64 [1, %for_i.preheader], [%i.1, %for_j.end]
+  %prev = phi i8* [%prev_0, %for_i.preheader], [%curr, %for_j.end]
+  %gep = getelementptr inbounds i8*, i8** %A, i64 %i
+  %curr = load i8*, i8** %gep, align 8
+  br label %for_j.preheader
+
+for_j.preheader:
+  br label %for_j.body
+
+for_j.body:
+  %j = phi i64 [0, %for_j.preheader], [%j.1, %for_j.body]
+
+  %gepPrev = getelementptr inbounds i8, i8* %prev, i64 %j
+  %gepCurr = getelementptr inbounds i8, i8* %curr, i64 %j
+  %gepB = getelementptr inbounds i8, i8* %B, i64 %j
+
+  %loadPrev = load i8, i8* %gepPrev, align 1
+  %loadB = load i8, i8* %gepB, align 1
+
+  %mul = mul i8 %loadPrev, %loadB
+
+  store i8 %mul, i8* %gepCurr, align 1
+
+  %gepB_plus_one = getelementptr inbounds i8, i8* %gepB, i64 1
+  store i8 2, i8* %gepB_plus_one, align 1
+
+  %j.1 = add nuw i64 %j, 1
+  %exitcondj = icmp eq i64 %j.1, %N
+  br i1 %exitcondj, label %for_j.end, label %for_j.body
+
+for_j.end:
+
+  %i.1 = add nuw i64 %i, 1
+  %exitcond = icmp eq i64 %i.1, %N
+  br i1 %exitcond, label %for_i.end, label %for_i.body
+
+for_i.end:
+  ret void
+}
diff --git a/test/Analysis/LoopAccessAnalysis/unsafe-and-rt-checks.ll b/test/Analysis/LoopAccessAnalysis/unsafe-and-rt-checks.ll
new file mode 100644
index 000000000000..ce8b86ba2c51
--- /dev/null
+++ b/test/Analysis/LoopAccessAnalysis/unsafe-and-rt-checks.ll
@@ -0,0 +1,58 @@
+; RUN: opt -loop-accesses -analyze < %s | FileCheck %s
+
+; Analyze this loop:
+;   for (i = 0; i < n; i++)
+;    A[i + 1] = A[i] * B[i] * C[i];
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+; CHECK: Report: unsafe dependent memory operations in loop
+; CHECK-NEXT: Interesting Dependences:
+; CHECK-NEXT:   Backward:
+; CHECK-NEXT:     %loadA = load i16, i16* %arrayidxA, align 2 ->
+; CHECK-NEXT:     store i16 %mul1, i16* %arrayidxA_plus_2, align 2
+; CHECK: Run-time memory checks:
+; CHECK-NEXT: 0:
+; CHECK-NEXT:   %arrayidxA_plus_2 = getelementptr inbounds i16, i16* %a, i64 %add
+; CHECK-NEXT:   %arrayidxB = getelementptr inbounds i16, i16* %b, i64 %storemerge3
+; CHECK-NEXT: 1:
+; CHECK-NEXT:   %arrayidxA_plus_2 = getelementptr inbounds i16, i16* %a, i64 %add
+; CHECK-NEXT:   %arrayidxC = getelementptr inbounds i16, i16* %c, i64 %storemerge3
+
+@B = common global i16* null, align 8
+@A = common global i16* null, align 8
+@C = common global i16* null, align 8
+
+define void @f() {
+entry:
+  %a = load i16*, i16** @A, align 8
+  %b = load i16*, i16** @B, align 8
+  %c = load i16*, i16** @C, align 8
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %storemerge3 = phi i64 [ 0, %entry ], [ %add, %for.body ]
+
+  %arrayidxA = getelementptr inbounds i16, i16* %a, i64 %storemerge3
+  %loadA = load i16, i16* %arrayidxA, align 2
+
+  %arrayidxB = getelementptr inbounds i16, i16* %b, i64 %storemerge3
+  %loadB = load i16, i16* %arrayidxB, align 2
+
+  %arrayidxC = getelementptr inbounds i16, i16* %c, i64 %storemerge3
+  %loadC = load i16, i16* %arrayidxC, align 2
+
+  %mul = mul i16 %loadB, %loadA
+  %mul1 = mul i16 %mul, %loadC
+
+  %add = add nuw nsw i64 %storemerge3, 1
+  %arrayidxA_plus_2 = getelementptr inbounds i16, i16* %a, i64 %add
+  store i16 %mul1, i16* %arrayidxA_plus_2, align 2
+
+  %exitcond = icmp eq i64 %add, 20
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
diff --git a/test/Analysis/LoopInfo/2003-05-15-NestingProblem.ll b/test/Analysis/LoopInfo/2003-05-15-NestingProblem.ll
index a87bab7cabf2..599b3e4b0311 100644
--- a/test/Analysis/LoopInfo/2003-05-15-NestingProblem.ll
+++ b/test/Analysis/LoopInfo/2003-05-15-NestingProblem.ll
@@ -2,6 +2,7 @@
 ; not a child of the loopentry.6 loop.
 ;
 ; RUN: opt < %s -analyze -loops | FileCheck %s
+; RUN: opt < %s -passes='print<loops>' -disable-output 2>&1 | FileCheck %s
 
 ; CHECK: Loop at depth 4 containing: %loopentry.7<header><latch><exiting>
 
diff --git a/test/Analysis/MemoryDependenceAnalysis/memdep_requires_dominator_tree.ll b/test/Analysis/MemoryDependenceAnalysis/memdep_requires_dominator_tree.ll
index 3c957708d705..d472f7c323fb 100644
--- a/test/Analysis/MemoryDependenceAnalysis/memdep_requires_dominator_tree.ll
+++ b/test/Analysis/MemoryDependenceAnalysis/memdep_requires_dominator_tree.ll
@@ -9,9 +9,9 @@ for.exit:                                         ; preds = %for.body
 
 for.body:                                         ; preds = %for.body, %entry
   %i.01 = phi i32 [ 0, %entry ], [ %tmp8.7, %for.body ]
-  %arrayidx = getelementptr i32* %bufUInt, i32 %i.01
-  %arrayidx5 = getelementptr i32* %pattern, i32 %i.01
-  %tmp6 = load i32* %arrayidx5, align 4
+  %arrayidx = getelementptr i32, i32* %bufUInt, i32 %i.01
+  %arrayidx5 = getelementptr i32, i32* %pattern, i32 %i.01
+  %tmp6 = load i32, i32* %arrayidx5, align 4
   store i32 %tmp6, i32* %arrayidx, align 4
   %tmp8.7 = add i32 %i.01, 8
   %cmp.7 = icmp ult i32 %tmp8.7, 1024
diff --git a/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll b/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll
index b5eb9fc4878d..7380da3ae7f8 100644
--- a/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll
+++ b/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll
@@ -11,7 +11,7 @@ entry:
 
 bb:		; preds = %bb, %entry
 	%i.01.0 = phi i32 [ 100, %entry ], [ %tmp4, %bb ]		; <i32> [#uses=2]
-	%tmp1 = getelementptr [101 x i32]* @array, i32 0, i32 %i.01.0		; <i32*> [#uses=1]
+	%tmp1 = getelementptr [101 x i32], [101 x i32]* @array, i32 0, i32 %i.01.0		; <i32*> [#uses=1]
 	store i32 %x, i32* %tmp1
 	%tmp4 = add i32 %i.01.0, -1		; <i32> [#uses=2]
 	%tmp7 = icmp sgt i32 %tmp4, -1		; <i1> [#uses=1]
diff --git a/test/Analysis/ScalarEvolution/2008-07-12-UnneededSelect1.ll b/test/Analysis/ScalarEvolution/2008-07-12-UnneededSelect1.ll
index dcf8fc9dbdb0..7e42530798f6 100644
--- a/test/Analysis/ScalarEvolution/2008-07-12-UnneededSelect1.ll
+++ b/test/Analysis/ScalarEvolution/2008-07-12-UnneededSelect1.ll
@@ -16,11 +16,11 @@ bb.nph:		; preds = %entry
 
 bb:		; preds = %bb1, %bb.nph
 	%j.01 = phi i32 [ %8, %bb1 ], [ 0, %bb.nph ]		; <i32> [#uses=1]
-	load i32* %srcptr, align 4		; <i32>:1 [#uses=2]
+	load i32, i32* %srcptr, align 4		; <i32>:1 [#uses=2]
 	and i32 %1, 255		; <i32>:2 [#uses=1]
 	and i32 %1, -256		; <i32>:3 [#uses=1]
-	getelementptr [256 x i8]* @lut, i32 0, i32 %2		; <i8*>:4 [#uses=1]
-	load i8* %4, align 1		; <i8>:5 [#uses=1]
+	getelementptr [256 x i8], [256 x i8]* @lut, i32 0, i32 %2		; <i8*>:4 [#uses=1]
+	load i8, i8* %4, align 1		; <i8>:5 [#uses=1]
 	zext i8 %5 to i32		; <i32>:6 [#uses=1]
 	or i32 %6, %3		; <i32>:7 [#uses=1]
 	store i32 %7, i32* %dstptr, align 4
diff --git a/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll b/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll
index 46c6c59e92c5..84561c5c6dc9 100644
--- a/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll
+++ b/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll
@@ -13,7 +13,7 @@ bb.nph:		; preds = %entry
 bb:		; preds = %bb.nph, %bb1
 	%indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb1 ]		; <i32> [#uses=2]
 	%argc_addr.04 = add i32 %indvar, %argc		; <i32> [#uses=1]
-	tail call void (...)* @Test() nounwind
+	tail call void (...) @Test() nounwind
 	%1 = add i32 %argc_addr.04, 1		; <i32> [#uses=1]
 	br label %bb1
 
diff --git a/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll b/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll
index 7a7a64001a69..0c24ee4eaff1 100644
--- a/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll
+++ b/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll
@@ -9,9 +9,9 @@ bb1.thread:
 bb1:		; preds = %bb1, %bb1.thread
 	%indvar = phi i32 [ 0, %bb1.thread ], [ %indvar.next, %bb1 ]		; <i32> [#uses=4]
 	%i.0.reg2mem.0 = sub i32 255, %indvar		; <i32> [#uses=2]
-	%0 = getelementptr i32* %alp, i32 %i.0.reg2mem.0		; <i32*> [#uses=1]
-	%1 = load i32* %0, align 4		; <i32> [#uses=1]
-	%2 = getelementptr i32* %lam, i32 %i.0.reg2mem.0		; <i32*> [#uses=1]
+	%0 = getelementptr i32, i32* %alp, i32 %i.0.reg2mem.0		; <i32*> [#uses=1]
+	%1 = load i32, i32* %0, align 4		; <i32> [#uses=1]
+	%2 = getelementptr i32, i32* %lam, i32 %i.0.reg2mem.0		; <i32*> [#uses=1]
 	store i32 %1, i32* %2, align 4
 	%3 = sub i32 254, %indvar		; <i32> [#uses=1]
 	%4 = icmp slt i32 %3, 0		; <i1> [#uses=1]
diff --git a/test/Analysis/ScalarEvolution/2009-01-02-SignedNegativeStride.ll b/test/Analysis/ScalarEvolution/2009-01-02-SignedNegativeStride.ll
index f19d18c72e69..ebcecbf74294 100644
--- a/test/Analysis/ScalarEvolution/2009-01-02-SignedNegativeStride.ll
+++ b/test/Analysis/ScalarEvolution/2009-01-02-SignedNegativeStride.ll
@@ -9,12 +9,12 @@
 
 define void @func_15() nounwind {
 entry:
-	%0 = load i16* @g_16, align 2		; <i16> [#uses=1]
+	%0 = load i16, i16* @g_16, align 2		; <i16> [#uses=1]
 	%1 = icmp sgt i16 %0, 0		; <i1> [#uses=1]
 	br i1 %1, label %bb2, label %bb.nph
 
 bb.nph:		; preds = %entry
-	%g_16.promoted = load i16* @g_16		; <i16> [#uses=1]
+	%g_16.promoted = load i16, i16* @g_16		; <i16> [#uses=1]
 	br label %bb
 
 bb:		; preds = %bb1, %bb.nph
diff --git a/test/Analysis/ScalarEvolution/2009-05-09-PointerEdgeCount.ll b/test/Analysis/ScalarEvolution/2009-05-09-PointerEdgeCount.ll
index 5d1502da179f..4f6b90b39f6f 100644
--- a/test/Analysis/ScalarEvolution/2009-05-09-PointerEdgeCount.ll
+++ b/test/Analysis/ScalarEvolution/2009-05-09-PointerEdgeCount.ll
@@ -11,18 +11,18 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1
 define void @_Z3foov() nounwind {
 entry:
 	%x = alloca %struct.NonPod, align 8		; <%struct.NonPod*> [#uses=2]
-	%0 = getelementptr %struct.NonPod* %x, i32 0, i32 0		; <[2 x %struct.Foo]*> [#uses=1]
-	%1 = getelementptr [2 x %struct.Foo]* %0, i32 1, i32 0		; <%struct.Foo*> [#uses=1]
+	%0 = getelementptr %struct.NonPod, %struct.NonPod* %x, i32 0, i32 0		; <[2 x %struct.Foo]*> [#uses=1]
+	%1 = getelementptr [2 x %struct.Foo], [2 x %struct.Foo]* %0, i32 1, i32 0		; <%struct.Foo*> [#uses=1]
 	br label %bb1.i
 
 bb1.i:		; preds = %bb2.i, %entry
 	%.0.i = phi %struct.Foo* [ %1, %entry ], [ %4, %bb2.i ]		; <%struct.Foo*> [#uses=2]
-	%2 = getelementptr %struct.NonPod* %x, i32 0, i32 0, i32 0		; <%struct.Foo*> [#uses=1]
+	%2 = getelementptr %struct.NonPod, %struct.NonPod* %x, i32 0, i32 0, i32 0		; <%struct.Foo*> [#uses=1]
 	%3 = icmp eq %struct.Foo* %.0.i, %2		; <i1> [#uses=1]
 	br i1 %3, label %_ZN6NonPodD1Ev.exit, label %bb2.i
 
 bb2.i:		; preds = %bb1.i
-	%4 = getelementptr %struct.Foo* %.0.i, i32 -1		; <%struct.Foo*> [#uses=1]
+	%4 = getelementptr %struct.Foo, %struct.Foo* %.0.i, i32 -1		; <%struct.Foo*> [#uses=1]
 	br label %bb1.i
 
 _ZN6NonPodD1Ev.exit:		; preds = %bb1.i
diff --git a/test/Analysis/ScalarEvolution/2009-07-04-GroupConstantsWidthMismatch.ll b/test/Analysis/ScalarEvolution/2009-07-04-GroupConstantsWidthMismatch.ll
index a4358aa63215..d18bdaf7cba7 100644
--- a/test/Analysis/ScalarEvolution/2009-07-04-GroupConstantsWidthMismatch.ll
+++ b/test/Analysis/ScalarEvolution/2009-07-04-GroupConstantsWidthMismatch.ll
@@ -3,11 +3,11 @@
 
 define void @test() {
 entry:
-        %0 = load i16* undef, align 1
+        %0 = load i16, i16* undef, align 1
         %1 = lshr i16 %0, 8
         %2 = and i16 %1, 3
         %3 = zext i16 %2 to i32
-        %4 = load i8* undef, align 1
+        %4 = load i8, i8* undef, align 1
         %5 = lshr i8 %4, 4
         %6 = and i8 %5, 1
         %7 = zext i8 %6 to i32
diff --git a/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll b/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll
index 5746d1c5900c..33fcbab92910 100644
--- a/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll
+++ b/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll
@@ -14,25 +14,25 @@ entry:
   br label %lbl_818
 
 lbl_818:                                          ; preds = %for.end, %entry
-  call void (...)* @func_27()
+  call void (...) @func_27()
   store i32 0, i32* @g_814, align 4
   br label %for.cond
 
 for.cond:                                         ; preds = %for.body, %lbl_818
-  %0 = load i32* @g_814, align 4
+  %0 = load i32, i32* @g_814, align 4
   %cmp = icmp sle i32 %0, 0
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
   %idxprom = sext i32 %0 to i64
-  %arrayidx = getelementptr inbounds [0 x i32]* getelementptr inbounds ([1 x [0 x i32]]* @g_244, i32 0, i64 0), i32 0, i64 %idxprom
-  %1 = load i32* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* getelementptr inbounds ([1 x [0 x i32]], [1 x [0 x i32]]* @g_244, i32 0, i64 0), i32 0, i64 %idxprom
+  %1 = load i32, i32* %arrayidx, align 1
   store i32 %1, i32* @func_21_l_773, align 4
   store i32 1, i32* @g_814, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %2 = load i32* @func_21_l_773, align 4
+  %2 = load i32, i32* @func_21_l_773, align 4
   %tobool = icmp ne i32 %2, 0
   br i1 %tobool, label %lbl_818, label %if.end
 
diff --git a/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll b/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
index 2cb8c5bf46ff..f7ef0ea9e484 100644
--- a/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
+++ b/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
@@ -10,7 +10,7 @@ entry:
         br label %bb3
 
 bb:             ; preds = %bb3
-        %tmp = getelementptr [1000 x i32]* @A, i32 0, i32 %i.0          ; <i32*> [#uses=1]
+        %tmp = getelementptr [1000 x i32], [1000 x i32]* @A, i32 0, i32 %i.0          ; <i32*> [#uses=1]
         store i32 123, i32* %tmp
         %tmp2 = add i32 %i.0, 1         ; <i32> [#uses=1]
         br label %bb3
diff --git a/test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll b/test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll
index 7eeb30849589..0976ef92985c 100644
--- a/test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll
+++ b/test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll
@@ -7,7 +7,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @test() {
 entry:
-	%0 = load i32** undef, align 8		; <i32*> [#uses=1]
+	%0 = load i32*, i32** undef, align 8		; <i32*> [#uses=1]
 	%1 = ptrtoint i32* %0 to i64		; <i64> [#uses=1]
 	%2 = sub i64 undef, %1		; <i64> [#uses=1]
 	%3 = lshr i64 %2, 3		; <i64> [#uses=1]
diff --git a/test/Analysis/ScalarEvolution/avoid-smax-0.ll b/test/Analysis/ScalarEvolution/avoid-smax-0.ll
index 8abb43074c5e..a282ee6993f0 100644
--- a/test/Analysis/ScalarEvolution/avoid-smax-0.ll
+++ b/test/Analysis/ScalarEvolution/avoid-smax-0.ll
@@ -11,7 +11,7 @@ entry:
 	br i1 %0, label %bb, label %return
 
 bb:
-	load i32* %q, align 4
+	load i32, i32* %q, align 4
 	icmp eq i32 %1, 0
 	br i1 %2, label %return, label %bb3.preheader
 
@@ -20,10 +20,10 @@ bb3.preheader:
 
 bb3:
 	%i.0 = phi i32 [ %7, %bb3 ], [ 0, %bb3.preheader ]
-	getelementptr i32* %p, i32 %i.0
-	load i32* %3, align 4
+	getelementptr i32, i32* %p, i32 %i.0
+	load i32, i32* %3, align 4
 	add i32 %4, 1
-	getelementptr i32* %p, i32 %i.0
+	getelementptr i32, i32* %p, i32 %i.0
 	store i32 %5, i32* %6, align 4
 	add i32 %i.0, 1
 	icmp slt i32 %7, %n
diff --git a/test/Analysis/ScalarEvolution/avoid-smax-1.ll b/test/Analysis/ScalarEvolution/avoid-smax-1.ll
index d9b83a929aa7..e6c62ee6b475 100644
--- a/test/Analysis/ScalarEvolution/avoid-smax-1.ll
+++ b/test/Analysis/ScalarEvolution/avoid-smax-1.ll
@@ -35,9 +35,9 @@ bb6:		; preds = %bb7, %bb.nph7
 	%7 = add i32 %x.06, %4		; <i32> [#uses=1]
 	%8 = shl i32 %x.06, 1		; <i32> [#uses=1]
 	%9 = add i32 %6, %8		; <i32> [#uses=1]
-	%10 = getelementptr i8* %r, i32 %9		; <i8*> [#uses=1]
-	%11 = load i8* %10, align 1		; <i8> [#uses=1]
-	%12 = getelementptr i8* %j, i32 %7		; <i8*> [#uses=1]
+	%10 = getelementptr i8, i8* %r, i32 %9		; <i8*> [#uses=1]
+	%11 = load i8, i8* %10, align 1		; <i8> [#uses=1]
+	%12 = getelementptr i8, i8* %j, i32 %7		; <i8*> [#uses=1]
 	store i8 %11, i8* %12, align 1
 	%13 = add i32 %x.06, 1		; <i32> [#uses=2]
 	br label %bb7
@@ -102,18 +102,18 @@ bb14:		; preds = %bb15, %bb.nph3
 	%x.12 = phi i32 [ %40, %bb15 ], [ 0, %bb.nph3 ]		; <i32> [#uses=5]
 	%29 = shl i32 %x.12, 2		; <i32> [#uses=1]
 	%30 = add i32 %29, %25		; <i32> [#uses=1]
-	%31 = getelementptr i8* %r, i32 %30		; <i8*> [#uses=1]
-	%32 = load i8* %31, align 1		; <i8> [#uses=1]
+	%31 = getelementptr i8, i8* %r, i32 %30		; <i8*> [#uses=1]
+	%32 = load i8, i8* %31, align 1		; <i8> [#uses=1]
 	%.sum = add i32 %26, %x.12		; <i32> [#uses=1]
-	%33 = getelementptr i8* %j, i32 %.sum		; <i8*> [#uses=1]
+	%33 = getelementptr i8, i8* %j, i32 %.sum		; <i8*> [#uses=1]
 	store i8 %32, i8* %33, align 1
 	%34 = shl i32 %x.12, 2		; <i32> [#uses=1]
 	%35 = or i32 %34, 2		; <i32> [#uses=1]
 	%36 = add i32 %35, %25		; <i32> [#uses=1]
-	%37 = getelementptr i8* %r, i32 %36		; <i8*> [#uses=1]
-	%38 = load i8* %37, align 1		; <i8> [#uses=1]
+	%37 = getelementptr i8, i8* %r, i32 %36		; <i8*> [#uses=1]
+	%38 = load i8, i8* %37, align 1		; <i8> [#uses=1]
 	%.sum6 = add i32 %27, %x.12		; <i32> [#uses=1]
-	%39 = getelementptr i8* %j, i32 %.sum6		; <i8*> [#uses=1]
+	%39 = getelementptr i8, i8* %j, i32 %.sum6		; <i8*> [#uses=1]
 	store i8 %38, i8* %39, align 1
 	%40 = add i32 %x.12, 1		; <i32> [#uses=2]
 	br label %bb15
@@ -168,10 +168,10 @@ bb23:		; preds = %bb24, %bb.nph
 	%y.21 = phi i32 [ %57, %bb24 ], [ 0, %bb.nph ]		; <i32> [#uses=3]
 	%53 = mul i32 %y.21, %50		; <i32> [#uses=1]
 	%.sum1 = add i32 %53, %51		; <i32> [#uses=1]
-	%54 = getelementptr i8* %r, i32 %.sum1		; <i8*> [#uses=1]
+	%54 = getelementptr i8, i8* %r, i32 %.sum1		; <i8*> [#uses=1]
 	%55 = mul i32 %y.21, %w		; <i32> [#uses=1]
 	%.sum5 = add i32 %55, %.sum3		; <i32> [#uses=1]
-	%56 = getelementptr i8* %j, i32 %.sum5		; <i8*> [#uses=1]
+	%56 = getelementptr i8, i8* %j, i32 %.sum5		; <i8*> [#uses=1]
 	tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %56, i8* %54, i32 %w, i32 1, i1 false)
 	%57 = add i32 %y.21, 1		; <i32> [#uses=2]
 	br label %bb24
@@ -186,7 +186,7 @@ bb24.bb26_crit_edge:		; preds = %bb24
 bb26:		; preds = %bb24.bb26_crit_edge, %bb22
 	%59 = mul i32 %x, %w		; <i32> [#uses=1]
 	%.sum4 = add i32 %.sum3, %59		; <i32> [#uses=1]
-	%60 = getelementptr i8* %j, i32 %.sum4		; <i8*> [#uses=1]
+	%60 = getelementptr i8, i8* %j, i32 %.sum4		; <i8*> [#uses=1]
 	%61 = mul i32 %x, %w		; <i32> [#uses=1]
 	%62 = sdiv i32 %61, 2		; <i32> [#uses=1]
 	tail call void @llvm.memset.p0i8.i32(i8* %60, i8 -128, i32 %62, i32 1, i1 false)
@@ -204,9 +204,9 @@ bb.nph11:		; preds = %bb29
 bb30:		; preds = %bb31, %bb.nph11
 	%y.310 = phi i32 [ %70, %bb31 ], [ 0, %bb.nph11 ]		; <i32> [#uses=3]
 	%66 = mul i32 %y.310, %64		; <i32> [#uses=1]
-	%67 = getelementptr i8* %r, i32 %66		; <i8*> [#uses=1]
+	%67 = getelementptr i8, i8* %r, i32 %66		; <i8*> [#uses=1]
 	%68 = mul i32 %y.310, %w		; <i32> [#uses=1]
-	%69 = getelementptr i8* %j, i32 %68		; <i8*> [#uses=1]
+	%69 = getelementptr i8, i8* %j, i32 %68		; <i8*> [#uses=1]
 	tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %69, i8* %67, i32 %w, i32 1, i1 false)
 	%70 = add i32 %y.310, 1		; <i32> [#uses=2]
 	br label %bb31
@@ -220,7 +220,7 @@ bb31.bb33_crit_edge:		; preds = %bb31
 
 bb33:		; preds = %bb31.bb33_crit_edge, %bb29
 	%72 = mul i32 %x, %w		; <i32> [#uses=1]
-	%73 = getelementptr i8* %j, i32 %72		; <i8*> [#uses=1]
+	%73 = getelementptr i8, i8* %j, i32 %72		; <i8*> [#uses=1]
 	%74 = mul i32 %x, %w		; <i32> [#uses=1]
 	%75 = sdiv i32 %74, 2		; <i32> [#uses=1]
 	tail call void @llvm.memset.p0i8.i32(i8* %73, i8 -128, i32 %75, i32 1, i1 false)
diff --git a/test/Analysis/ScalarEvolution/ext-antecedent.ll b/test/Analysis/ScalarEvolution/ext-antecedent.ll
new file mode 100644
index 000000000000..e8d38133ad30
--- /dev/null
+++ b/test/Analysis/ScalarEvolution/ext-antecedent.ll
@@ -0,0 +1,45 @@
+; RUN: opt -S -indvars < %s | FileCheck %s
+
+declare void @use(i1)
+
+define void @sext_condition(i8 %t) {
+; CHECK-LABEL: sext_condition
+ entry:
+  %st = sext i8 %t to i16
+  %ecmp = icmp slt i16 %st, 42
+  br i1 %ecmp, label %loop, label %exit
+
+ loop:
+; CHECK-LABEL: loop
+  %idx = phi i8 [ %t, %entry ], [ %idx.inc, %loop ]
+  %idx.inc = add i8 %idx, 1
+  %c = icmp slt i8 %idx, 42
+; CHECK: call void @use(i1 true)
+  call void @use(i1 %c)
+  %be = icmp slt i8 %idx.inc, 42
+  br i1 %be, label %loop, label %exit
+
+ exit:
+  ret void
+}
+
+define void @zext_condition(i8 %t) {
+; CHECK-LABEL: zext_condition
+ entry:
+  %st = zext i8 %t to i16
+  %ecmp = icmp ult i16 %st, 42
+  br i1 %ecmp, label %loop, label %exit
+
+ loop:
+; CHECK-LABEL: loop
+  %idx = phi i8 [ %t, %entry ], [ %idx.inc, %loop ]
+  %idx.inc = add i8 %idx, 1
+  %c = icmp ult i8 %idx, 42
+; CHECK: call void @use(i1 true)
+  call void @use(i1 %c)
+  %be = icmp ult i8 %idx.inc, 42
+  br i1 %be, label %loop, label %exit
+
+ exit:
+  ret void
+}
diff --git a/test/Analysis/ScalarEvolution/fold.ll b/test/Analysis/ScalarEvolution/fold.ll
index ab5742557b33..226a24ff9c84 100644
--- a/test/Analysis/ScalarEvolution/fold.ll
+++ b/test/Analysis/ScalarEvolution/fold.ll
@@ -34,7 +34,7 @@ loop:
   %rand2 = icmp ugt i32 %A, %Z1
   %Z2 = select i1 %rand2, i32 %A, i32 %Z1
 ; CHECK: %Z2 =
-; CHECK-NEXT: -->  ([[EXPR:.*]]){{ +}}Exits: 20
+; CHECK-NEXT: -->  ([[EXPR:.*]]){{ U: [^ ]+ S: [^ ]+}}{{ +}}Exits: 20
   %B = trunc i32 %Z2 to i16
   %C = sext i16 %B to i30
 ; CHECK: %C =
@@ -86,3 +86,15 @@ define void @test6(i8 %x) {
 ; CHECK: -->  (2048 * ((zext i8 %x to i16) /u 8))
   ret void
 }
+
+; PR22960
+define void @test7(i32 %A) {
+; CHECK-LABEL: @test7
+  %B = sext i32 %A to i64
+  %C = zext i32 %A to i64
+  %D = sub i64 %B, %C
+  %E = trunc i64 %D to i16
+; CHECK: %E
+; CHECK-NEXT: -->  0
+  ret void
+}
diff --git a/test/Analysis/ScalarEvolution/incorrect-nsw.ll b/test/Analysis/ScalarEvolution/incorrect-nsw.ll
new file mode 100644
index 000000000000..dd981c404ccd
--- /dev/null
+++ b/test/Analysis/ScalarEvolution/incorrect-nsw.ll
@@ -0,0 +1,26 @@
+; RUN: opt -analyze -scalar-evolution -scalar-evolution < %s | FileCheck %s
+
+define void @bad.nsw() {
+; CHECK-LABEL: Classifying expressions for: @bad.nsw
+; CHECK-LABEL: Classifying expressions for: @bad.nsw
+ entry: 
+  br label %loop
+
+ loop:
+  %i = phi i8 [ -1, %entry ], [ %i.inc, %loop ]
+; CHECK:  %i = phi i8 [ -1, %entry ], [ %i.inc, %loop ]
+; CHECK-NEXT: -->  {-1,+,-128}<nw><%loop>
+; CHECK-NOT: -->  {-1,+,-128}<nsw><%loop>
+
+  %counter = phi i8 [ 0, %entry ], [ %counter.inc, %loop ]
+
+  %i.inc = add i8 %i, -128
+  %i.sext = sext i8 %i to i16
+
+  %counter.inc = add i8 %counter, 1
+  %continue = icmp eq i8 %counter, 1
+  br i1 %continue, label %exit, label %loop
+
+ exit:
+  ret void  
+}
diff --git a/test/Analysis/ScalarEvolution/infer-prestart-no-wrap.ll b/test/Analysis/ScalarEvolution/infer-prestart-no-wrap.ll
new file mode 100644
index 000000000000..078ca03ff14e
--- /dev/null
+++ b/test/Analysis/ScalarEvolution/infer-prestart-no-wrap.ll
@@ -0,0 +1,101 @@
+; ; RUN: opt -analyze -scalar-evolution < %s | FileCheck %s
+
+define void @infer.sext.0(i1* %c, i32 %start) {
+; CHECK-LABEL: Classifying expressions for: @infer.sext.0
+ entry:
+  br label %loop
+
+ loop:
+  %counter = phi i32 [ 0, %entry ], [ %counter.inc, %loop ]
+  %idx = phi i32 [ %start, %entry ], [ %idx.inc, %loop ]
+  %idx.inc = add nsw i32 %idx, 1
+  %idx.inc.sext = sext i32 %idx.inc to i64
+; CHECK: %idx.inc.sext = sext i32 %idx.inc to i64
+; CHECK-NEXT: -->  {(1 + (sext i32 %start to i64)),+,1}<nsw><%loop>
+  %condition = icmp eq i32 %counter, 1
+  %counter.inc = add i32 %counter, 1
+  br i1 %condition, label %exit, label %loop
+
+ exit:
+  ret void
+}
+
+define void @infer.zext.0(i1* %c, i32 %start) {
+; CHECK-LABEL: Classifying expressions for: @infer.zext.0
+ entry:
+  br label %loop
+
+ loop:
+  %counter = phi i32 [ 0, %entry ], [ %counter.inc, %loop ]
+  %idx = phi i32 [ %start, %entry ], [ %idx.inc, %loop ]
+  %idx.inc = add nuw i32 %idx, 1
+  %idx.inc.sext = zext i32 %idx.inc to i64
+; CHECK: %idx.inc.sext = zext i32 %idx.inc to i64
+; CHECK-NEXT: -->  {(1 + (zext i32 %start to i64)),+,1}<nuw><%loop>
+  %condition = icmp eq i32 %counter, 1
+  %counter.inc = add i32 %counter, 1
+  br i1 %condition, label %exit, label %loop
+
+ exit:
+  ret void
+}
+
+define void @infer.sext.1(i32 %start, i1* %c) {
+; CHECK-LABEL: Classifying expressions for: @infer.sext.1
+ entry:
+  %start.mul = mul i32 %start, 4
+  %start.real = add i32 %start.mul, 2
+  br label %loop
+
+ loop:
+  %idx = phi i32 [ %start.real, %entry ], [ %idx.inc, %loop ]
+  %idx.sext = sext i32 %idx to i64
+; CHECK: %idx.sext = sext i32 %idx to i64
+; CHECK-NEXT:  -->  {(2 + (sext i32 (4 * %start) to i64)),+,2}<nsw><%loop>
+  %idx.inc = add nsw i32 %idx, 2
+  %condition = load i1, i1* %c
+  br i1 %condition, label %exit, label %loop
+
+ exit:
+  ret void
+}
+
+define void @infer.sext.2(i1* %c, i8 %start) {
+; CHECK-LABEL: Classifying expressions for: @infer.sext.2
+ entry:
+  %start.inc = add i8 %start, 1
+  %entry.condition = icmp slt i8 %start, 127
+  br i1 %entry.condition, label %loop, label %exit
+
+ loop:
+  %idx = phi i8 [ %start.inc, %entry ], [ %idx.inc, %loop ]
+  %idx.sext = sext i8 %idx to i16
+; CHECK: %idx.sext = sext i8 %idx to i16
+; CHECK-NEXT: -->  {(1 + (sext i8 %start to i16)),+,1}<nsw><%loop>
+  %idx.inc = add nsw i8 %idx, 1
+  %condition = load volatile i1, i1* %c
+  br i1 %condition, label %exit, label %loop
+
+ exit:
+  ret void
+}
+
+define void @infer.zext.1(i1* %c, i8 %start) {
+; CHECK-LABEL: Classifying expressions for: @infer.zext.1
+ entry:
+  %start.inc = add i8 %start, 1
+  %entry.condition = icmp ult i8 %start, 255
+  br i1 %entry.condition, label %loop, label %exit
+
+ loop:
+  %idx = phi i8 [ %start.inc, %entry ], [ %idx.inc, %loop ]
+  %idx.zext = zext i8 %idx to i16
+; CHECK: %idx.zext = zext i8 %idx to i16
+; CHECK-NEXT: -->  {(1 + (zext i8 %start to i16)),+,1}<nuw><%loop>
+  %idx.inc = add nuw i8 %idx, 1
+  %condition = load volatile i1, i1* %c
+  br i1 %condition, label %exit, label %loop
+
+ exit:
+  ret void
+}
diff --git a/test/Analysis/ScalarEvolution/infer-via-ranges.ll b/test/Analysis/ScalarEvolution/infer-via-ranges.ll
new file mode 100644
index 000000000000..3627c3ab45d1
--- /dev/null
+++ b/test/Analysis/ScalarEvolution/infer-via-ranges.ll
@@ -0,0 +1,30 @@
+; RUN: opt -indvars -S < %s | FileCheck %s
+
+define void @infer_via_ranges(i32 *%arr, i32 %n) {
+; CHECK-LABEL: @infer_via_ranges
+ entry:
+  %first.itr.check = icmp sgt i32 %n, 0
+  %start = sub i32 %n, 1
+  br i1 %first.itr.check, label %loop, label %exit
+
+ loop:
+; CHECK-LABEL: loop:
+  %idx = phi i32 [ %start, %entry ] , [ %idx.dec, %in.bounds ]
+  %idx.dec = sub i32 %idx, 1
+  %abc = icmp sge i32 %idx, 0
+; CHECK: br i1 true, label %in.bounds, label %out.of.bounds
+  br i1 %abc, label %in.bounds, label %out.of.bounds
+
+ in.bounds:
+; CHECK-LABEL: in.bounds:
+  %addr = getelementptr i32, i32* %arr, i32 %idx
+  store i32 0, i32* %addr
+  %next = icmp sgt i32 %idx.dec, -1
+  br i1 %next, label %loop, label %exit
+
+ out.of.bounds:
+  ret void
+
+ exit:
+  ret void
+}
diff --git a/test/Analysis/ScalarEvolution/latch-dominating-conditions.ll b/test/Analysis/ScalarEvolution/latch-dominating-conditions.ll
new file mode 100644
index 000000000000..3f6f9584cce0
--- /dev/null
+++ b/test/Analysis/ScalarEvolution/latch-dominating-conditions.ll
@@ -0,0 +1,55 @@
+; RUN: opt -S -indvars < %s | FileCheck %s
+
+declare void @side_effect(i1)
+
+define void @latch_dominating_0(i8 %start) {
+; CHECK-LABEL: latch_dominating_0
+ entry:
+  %e = icmp slt i8 %start, 42
+  br i1 %e, label %loop, label %exit
+
+ loop:
+; CHECK-LABEL: loop
+  %idx = phi i8 [ %start, %entry ], [ %idx.inc, %be ]
+  %idx.inc = add i8 %idx, 1
+  %folds.to.true = icmp slt i8 %idx, 42
+; CHECK: call void @side_effect(i1 true)
+  call void @side_effect(i1 %folds.to.true)
+  %c0 = icmp slt i8 %idx.inc, 42
+  br i1 %c0, label %be, label %exit
+
+ be:
+; CHECK: call void @side_effect(i1 true)
+  call void @side_effect(i1 %folds.to.true)
+  %c1 = icmp slt i8 %idx.inc, 100
+  br i1 %c1, label %loop, label %exit
+
+ exit:
+  ret void
+}
+
+define void @latch_dominating_1(i8 %start) {
+; CHECK-LABEL: latch_dominating_1
+ entry:
+  %e = icmp slt i8 %start, 42
+  br i1 %e, label %loop, label %exit
+
+ loop:
+; CHECK-LABEL: loop
+  %idx = phi i8 [ %start, %entry ], [ %idx.inc, %be ]
+  %idx.inc = add i8 %idx, 1
+  %does.not.fold.to.true = icmp slt i8 %idx, 42
+; CHECK: call void @side_effect(i1 %does.not.fold.to.true)
+  call void @side_effect(i1 %does.not.fold.to.true)
+  %c0 = icmp slt i8 %idx.inc, 42
+  br i1 %c0, label %be, label %be
+
+ be:
+; CHECK: call void @side_effect(i1 %does.not.fold.to.true)
+  call void @side_effect(i1 %does.not.fold.to.true)
+  %c1 = icmp slt i8 %idx.inc, 100
+  br i1 %c1, label %loop, label %exit
+
+ exit:
+  ret void
+}
diff --git a/test/Analysis/ScalarEvolution/load-with-range-metadata.ll b/test/Analysis/ScalarEvolution/load-with-range-metadata.ll
index 32c1074b1742..f26c8d56754d 100644
--- a/test/Analysis/ScalarEvolution/load-with-range-metadata.ll
+++ b/test/Analysis/ScalarEvolution/load-with-range-metadata.ll
@@ -3,7 +3,7 @@
 define i32 @slt_trip_count_with_range(i32 *%ptr0, i32 *%ptr1) {
 ; CHECK-LABEL: slt_trip_count_with_range
  entry:
-  %limit = load i32* %ptr0, !range !0
+  %limit = load i32, i32* %ptr0, !range !0
   br label %loop
 
  loop:
@@ -20,7 +20,7 @@ define i32 @slt_trip_count_with_range(i32 *%ptr0, i32 *%ptr1) {
 define i32 @ult_trip_count_with_range(i32 *%ptr0, i32 *%ptr1) {
 ; CHECK-LABEL: ult_trip_count_with_range
  entry:
-  %limit = load i32* %ptr0, !range !0
+  %limit = load i32, i32* %ptr0, !range !0
   br label %loop
 
  loop:
diff --git a/test/Analysis/ScalarEvolution/load.ll b/test/Analysis/ScalarEvolution/load.ll
index 2c753f5befcb..ea79476de6b3 100644
--- a/test/Analysis/ScalarEvolution/load.ll
+++ b/test/Analysis/ScalarEvolution/load.ll
@@ -14,14 +14,14 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %sum.04 = phi i32 [ 0, %entry ], [ %add2, %for.body ]
-; CHECK: -->  %sum.04{{ *}}Exits: 2450
+; CHECK: -->  %sum.04{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: 2450
   %i.03 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds [50 x i32]* @arr1, i32 0, i32 %i.03
-  %0 = load i32* %arrayidx, align 4
-; CHECK: -->  %0{{ *}}Exits: 50
-  %arrayidx1 = getelementptr inbounds [50 x i32]* @arr2, i32 0, i32 %i.03
-  %1 = load i32* %arrayidx1, align 4
-; CHECK: -->  %1{{ *}}Exits: 0
+  %arrayidx = getelementptr inbounds [50 x i32], [50 x i32]* @arr1, i32 0, i32 %i.03
+  %0 = load i32, i32* %arrayidx, align 4
+; CHECK: -->  %0{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: 50
+  %arrayidx1 = getelementptr inbounds [50 x i32], [50 x i32]* @arr2, i32 0, i32 %i.03
+  %1 = load i32, i32* %arrayidx1, align 4
+; CHECK: -->  %1{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: 0
   %add = add i32 %0, %sum.04
   %add2 = add i32 %add, %1
   %inc = add nsw i32 %i.03, 1
@@ -48,15 +48,15 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %sum.02 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-; CHECK: -->  %sum.02{{ *}}Exits: 10
+; CHECK: -->  %sum.02{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: 10
   %n.01 = phi %struct.ListNode* [ bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node5 to %struct.ListNode*), %entry ], [ %1, %for.body ]
-; CHECK: -->  %n.01{{ *}}Exits: @node1
-  %i = getelementptr inbounds %struct.ListNode* %n.01, i64 0, i32 1
-  %0 = load i32* %i, align 4
+; CHECK: -->  %n.01{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: @node1
+  %i = getelementptr inbounds %struct.ListNode, %struct.ListNode* %n.01, i64 0, i32 1
+  %0 = load i32, i32* %i, align 4
   %add = add nsw i32 %0, %sum.02
-  %next = getelementptr inbounds %struct.ListNode* %n.01, i64 0, i32 0
-  %1 = load %struct.ListNode** %next, align 8
-; CHECK: -->  %1{{ *}}Exits: 0
+  %next = getelementptr inbounds %struct.ListNode, %struct.ListNode* %n.01, i64 0, i32 0
+  %1 = load %struct.ListNode*, %struct.ListNode** %next, align 8
+; CHECK: -->  %1{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: 0
   %cmp = icmp eq %struct.ListNode* %1, null
   br i1 %cmp, label %for.end, label %for.body
 
diff --git a/test/Analysis/ScalarEvolution/max-trip-count-address-space.ll b/test/Analysis/ScalarEvolution/max-trip-count-address-space.ll
index aa5254c758bf..8d6cb2fbf63f 100644
--- a/test/Analysis/ScalarEvolution/max-trip-count-address-space.ll
+++ b/test/Analysis/ScalarEvolution/max-trip-count-address-space.ll
@@ -4,7 +4,7 @@
 
 target datalayout = "e-p:32:32:32-p1:16:16:16-p2:8:8:8-p4:64:64:64-n16:32:64"
 
-; CHECK:  {%d,+,4}<%bb>		Exits: ((4 * (trunc i32 (-1 + %n) to i16)) + %d)
+; CHECK:  {%d,+,4}<%bb>{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: ((4 * (trunc i32 (-1 + %n) to i16)) + %d)
 
 
 define void @foo(i32 addrspace(1)* nocapture %d, i32 %n) nounwind {
@@ -21,7 +21,7 @@ bb:		; preds = %bb1, %bb.nph
 	%p.01 = phi i8 [ %4, %bb1 ], [ -1, %bb.nph ]		; <i8> [#uses=2]
 	%1 = sext i8 %p.01 to i32		; <i32> [#uses=1]
 	%2 = sext i32 %i.02 to i64		; <i64> [#uses=1]
-	%3 = getelementptr i32 addrspace(1)* %d, i64 %2		; <i32*> [#uses=1]
+	%3 = getelementptr i32, i32 addrspace(1)* %d, i64 %2		; <i32*> [#uses=1]
 	store i32 %1, i32 addrspace(1)* %3, align 4
 	%4 = add i8 %p.01, 1		; <i8> [#uses=1]
 	%5 = add i32 %i.02, 1		; <i32> [#uses=2]
@@ -50,7 +50,7 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body, %for.body.lr.ph
   %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %for.body.lr.ph ]
-  %arrayidx = getelementptr i8 addrspace(1)* %a, i64 %indvar
+  %arrayidx = getelementptr i8, i8 addrspace(1)* %a, i64 %indvar
   store i8 0, i8 addrspace(1)* %arrayidx, align 1
   %indvar.next = add i64 %indvar, 1
   %exitcond = icmp ne i64 %indvar.next, %tmp
diff --git a/test/Analysis/ScalarEvolution/max-trip-count.ll b/test/Analysis/ScalarEvolution/max-trip-count.ll
index 31f06a46ad00..614e9b265ab0 100644
--- a/test/Analysis/ScalarEvolution/max-trip-count.ll
+++ b/test/Analysis/ScalarEvolution/max-trip-count.ll
@@ -2,7 +2,7 @@
 
 ; ScalarEvolution should be able to understand the loop and eliminate the casts.
 
-; CHECK: {%d,+,sizeof(i32)}
+; CHECK: {%d,+,4}
 
 define void @foo(i32* nocapture %d, i32 %n) nounwind {
 entry:
@@ -17,7 +17,7 @@ bb:		; preds = %bb1, %bb.nph
 	%p.01 = phi i8 [ %4, %bb1 ], [ -1, %bb.nph ]		; <i8> [#uses=2]
 	%1 = sext i8 %p.01 to i32		; <i32> [#uses=1]
 	%2 = sext i32 %i.02 to i64		; <i64> [#uses=1]
-	%3 = getelementptr i32* %d, i64 %2		; <i32*> [#uses=1]
+	%3 = getelementptr i32, i32* %d, i64 %2		; <i32*> [#uses=1]
 	store i32 %1, i32* %3, align 4
 	%4 = add i8 %p.01, 1		; <i8> [#uses=1]
 	%5 = add i32 %i.02, 1		; <i32> [#uses=2]
@@ -39,7 +39,7 @@ return:		; preds = %bb1.return_crit_edge, %entry
 ; count, it should say so.
 
 ; PR7845
-; CHECK: Loop %for.cond: <multiple exits> Unpredictable backedge-taken count. 
+; CHECK: Loop %for.cond: <multiple exits> Unpredictable backedge-taken count.
 ; CHECK: Loop %for.cond: max backedge-taken count is 5
 
 @.str = private constant [4 x i8] c"%d\0A\00"     ; <[4 x i8]*> [#uses=2]
@@ -65,7 +65,7 @@ for.inc:                                          ; preds = %for.body
   br label %for.cond
 
 for.end:                                          ; preds = %for.body, %for.cond
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32 %g_4.0) nounwind ; <i32> [#uses=0]
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %g_4.0) nounwind ; <i32> [#uses=0]
   ret i32 0
 }
 
@@ -82,7 +82,7 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body, %for.body.lr.ph
   %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %for.body.lr.ph ]
-  %arrayidx = getelementptr i8* %a, i64 %indvar
+  %arrayidx = getelementptr i8, i8* %a, i64 %indvar
   store i8 0, i8* %arrayidx, align 1
   %indvar.next = add i64 %indvar, 1
   %exitcond = icmp ne i64 %indvar.next, %tmp
@@ -101,7 +101,7 @@ for.end:                                          ; preds = %for.cond.for.end_cr
 
 ; PR19799: Indvars miscompile due to an incorrect max backedge taken count from SCEV.
 ; CHECK-LABEL: @pr19799
-; CHECK: Loop %for.body.i: <multiple exits> Unpredictable backedge-taken count. 
+; CHECK: Loop %for.body.i: <multiple exits> Unpredictable backedge-taken count.
 ; CHECK: Loop %for.body.i: max backedge-taken count is 1
 @a = common global i32 0, align 4
 
@@ -127,7 +127,7 @@ bar.exit:                                         ; preds = %for.cond.i, %for.bo
 
 ; PR18886: Indvars miscompile due to an incorrect max backedge taken count from SCEV.
 ; CHECK-LABEL: @pr18886
-; CHECK: Loop %for.body: <multiple exits> Unpredictable backedge-taken count. 
+; CHECK: Loop %for.body: <multiple exits> Unpredictable backedge-taken count.
 ; CHECK: Loop %for.body: max backedge-taken count is 3
 @aa = global i64 0, align 8
 
@@ -157,8 +157,8 @@ return:
 ; before the check is forever skipped.
 ;
 ; CHECK-LABEL: @cannot_compute_mustexit
-; CHECK: Loop %for.body.i: <multiple exits> Unpredictable backedge-taken count. 
-; CHECK: Loop %for.body.i: Unpredictable max backedge-taken count. 
+; CHECK: Loop %for.body.i: <multiple exits> Unpredictable backedge-taken count.
+; CHECK: Loop %for.body.i: Unpredictable max backedge-taken count.
 @b = common global i32 0, align 4
 
 define i32 @cannot_compute_mustexit() {
@@ -174,7 +174,7 @@ for.body.i:                                       ; preds = %for.cond.i, %entry
 
 for.cond.i:                                       ; preds = %for.body.i
   store i32 %add.i.i, i32* @a, align 4
-  %ld = load volatile i32* @b
+  %ld = load volatile i32, i32* @b
   %cmp.i = icmp ne i32 %ld, 0
   br i1 %cmp.i, label %for.body.i, label %bar.exit
 
@@ -186,7 +186,7 @@ bar.exit:                                         ; preds = %for.cond.i, %for.bo
 ; MaxBECount should be the minimum of them.
 ;
 ; CHECK-LABEL: @two_mustexit
-; CHECK: Loop %for.body.i: <multiple exits> Unpredictable backedge-taken count. 
+; CHECK: Loop %for.body.i: <multiple exits> Unpredictable backedge-taken count.
 ; CHECK: Loop %for.body.i: max backedge-taken count is 1
 define i32 @two_mustexit() {
 entry:
diff --git a/test/Analysis/ScalarEvolution/min-max-exprs.ll b/test/Analysis/ScalarEvolution/min-max-exprs.ll
new file mode 100644
index 000000000000..892fc23fe6b2
--- /dev/null
+++ b/test/Analysis/ScalarEvolution/min-max-exprs.ll
@@ -0,0 +1,53 @@
+; RUN: opt -scalar-evolution -analyze < %s | FileCheck %s
+;
+; This checks if the min and max expressions are properly recognized by
+; ScalarEvolution even though they the ICmpInst and SelectInst have different
+; types.
+;
+;    #define max(a, b) (a > b ? a : b)
+;    #define min(a, b) (a < b ? a : b)
+;
+;    void f(int *A, int N) {
+;      for (int i = 0; i < N; i++) {
+;        A[max(0, i - 3)] = A[min(N, i + 3)] * 2;
+;      }
+;    }
+;
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+define void @f(i32* %A, i32 %N) {
+bb:
+  br label %bb1
+
+bb1:                                              ; preds = %bb2, %bb
+  %i.0 = phi i32 [ 0, %bb ], [ %tmp23, %bb2 ]
+  %i.0.1 = sext i32 %i.0 to i64
+  %tmp = icmp slt i32 %i.0, %N
+  br i1 %tmp, label %bb2, label %bb24
+
+bb2:                                              ; preds = %bb1
+  %tmp3 = add nuw nsw i32 %i.0, 3
+  %tmp4 = icmp slt i32 %tmp3, %N
+  %tmp5 = sext i32 %tmp3 to i64
+  %tmp6 = sext i32 %N to i64
+  %tmp9 = select i1 %tmp4, i64 %tmp5, i64 %tmp6
+;                  min(N, i+3)
+; CHECK:           select i1 %tmp4, i64 %tmp5, i64 %tmp6
+; CHECK-NEXT:  --> (-1 + (-1 * ((-1 + (-1 * (sext i32 {3,+,1}<nw><%bb1> to i64))) smax (-1 + (-1 * (sext i32 %N to i64))))))
+  %tmp11 = getelementptr inbounds i32, i32* %A, i64 %tmp9
+  %tmp12 = load i32, i32* %tmp11, align 4
+  %tmp13 = shl nsw i32 %tmp12, 1
+  %tmp14 = icmp sge i32 3, %i.0
+  %tmp17 = add nsw i64 %i.0.1, -3
+  %tmp19 = select i1 %tmp14, i64 0, i64 %tmp17
+;                  max(0, i - 3)
+; CHECK:           select i1 %tmp14, i64 0, i64 %tmp17
+; CHECK-NEXT: -->  (-3 + (3 smax {0,+,1}<nuw><nsw><%bb1>))
+  %tmp21 = getelementptr inbounds i32, i32* %A, i64 %tmp19
+  store i32 %tmp13, i32* %tmp21, align 4
+  %tmp23 = add nuw nsw i32 %i.0, 1
+  br label %bb1
+
+bb24:                                             ; preds = %bb1
+  ret void
+}
diff --git a/test/Analysis/ScalarEvolution/nowrap-preinc-limits.ll b/test/Analysis/ScalarEvolution/nowrap-preinc-limits.ll
new file mode 100644
index 000000000000..1a5409d01f64
--- /dev/null
+++ b/test/Analysis/ScalarEvolution/nowrap-preinc-limits.ll
@@ -0,0 +1,44 @@
+; RUN: opt -analyze -scalar-evolution < %s | FileCheck %s
+
+define void @f(i1* %condition) {
+; CHECK-LABEL: Classifying expressions for: @f
+ entry: 
+  br label %loop
+
+ loop:
+  %idx = phi i32 [ 0, %entry ], [ %idx.inc, %loop ]
+  %idx.inc = add nsw i32 %idx, 1
+
+  %idx.inc2 = add i32 %idx.inc, 1
+  %idx.inc2.zext = zext i32 %idx.inc2 to i64
+
+; CHECK: %idx.inc2.zext = zext i32 %idx.inc2 to i64
+; CHECK-NEXT: -->  {2,+,1}<nuw><%loop>
+
+  %c = load volatile i1, i1* %condition
+  br i1 %c, label %loop, label %exit
+
+ exit:
+  ret void
+}
+
+define void @g(i1* %condition) {
+; CHECK-LABEL: Classifying expressions for: @g
+ entry:
+  br label %loop
+
+ loop:
+  %idx = phi i32 [ 0, %entry ], [ %idx.inc, %loop ]
+  %idx.inc = add nsw i32 %idx, 3
+
+  %idx.inc2 = add i32 %idx.inc, -1
+  %idx.inc2.sext = sext i32 %idx.inc2 to i64
+; CHECK: %idx.inc2.sext = sext i32 %idx.inc2 to i64
+; CHECK-NEXT: -->  {2,+,3}<nuw><nsw><%loop>
+
+  %c = load volatile i1, i1* %condition
+  br i1 %c, label %loop, label %exit
+
+ exit:
+  ret void
+}
diff --git a/test/Analysis/ScalarEvolution/nsw-offset-assume.ll b/test/Analysis/ScalarEvolution/nsw-offset-assume.ll
index 29cf65857797..bef1070bbcb0 100644
--- a/test/Analysis/ScalarEvolution/nsw-offset-assume.ll
+++ b/test/Analysis/ScalarEvolution/nsw-offset-assume.ll
@@ -24,23 +24,23 @@ bb:                                               ; preds = %bb.nph, %bb1
 ; CHECK: -->  {0,+,2}<nuw><nsw><%bb>
   %1 = sext i32 %i.01 to i64                      ; <i64> [#uses=1]
 
-; CHECK: %2 = getelementptr inbounds double* %d, i64 %1
+; CHECK: %2 = getelementptr inbounds double, double* %d, i64 %1
 ; CHECK: -->  {%d,+,16}<nsw><%bb>
-  %2 = getelementptr inbounds double* %d, i64 %1  ; <double*> [#uses=1]
+  %2 = getelementptr inbounds double, double* %d, i64 %1  ; <double*> [#uses=1]
 
-  %3 = load double* %2, align 8                   ; <double> [#uses=1]
+  %3 = load double, double* %2, align 8                   ; <double> [#uses=1]
   %4 = sext i32 %i.01 to i64                      ; <i64> [#uses=1]
-  %5 = getelementptr inbounds double* %q, i64 %4  ; <double*> [#uses=1]
-  %6 = load double* %5, align 8                   ; <double> [#uses=1]
+  %5 = getelementptr inbounds double, double* %q, i64 %4  ; <double*> [#uses=1]
+  %6 = load double, double* %5, align 8                   ; <double> [#uses=1]
   %7 = or i32 %i.01, 1                            ; <i32> [#uses=1]
 
 ; CHECK: %8 = sext i32 %7 to i64
 ; CHECK: -->  {1,+,2}<nuw><nsw><%bb>
   %8 = sext i32 %7 to i64                         ; <i64> [#uses=1]
 
-; CHECK: %9 = getelementptr inbounds double* %q, i64 %8
+; CHECK: %9 = getelementptr inbounds double, double* %q, i64 %8
 ; CHECK: {(8 + %q),+,16}<nsw><%bb>
-  %9 = getelementptr inbounds double* %q, i64 %8  ; <double*> [#uses=1]
+  %9 = getelementptr inbounds double, double* %q, i64 %8  ; <double*> [#uses=1]
 
 ; Artificially repeat the above three instructions, this time using
 ; add nsw instead of or.
@@ -50,16 +50,16 @@ bb:                                               ; preds = %bb.nph, %bb1
 ; CHECK: -->  {1,+,2}<nuw><nsw><%bb>
   %t8 = sext i32 %t7 to i64                         ; <i64> [#uses=1]
 
-; CHECK: %t9 = getelementptr inbounds double* %q, i64 %t8
+; CHECK: %t9 = getelementptr inbounds double, double* %q, i64 %t8
 ; CHECK: {(8 + %q),+,16}<nsw><%bb>
-  %t9 = getelementptr inbounds double* %q, i64 %t8  ; <double*> [#uses=1]
+  %t9 = getelementptr inbounds double, double* %q, i64 %t8  ; <double*> [#uses=1]
 
-  %10 = load double* %9, align 8                  ; <double> [#uses=1]
+  %10 = load double, double* %9, align 8                  ; <double> [#uses=1]
   %11 = fadd double %6, %10                       ; <double> [#uses=1]
   %12 = fadd double %11, 3.200000e+00             ; <double> [#uses=1]
   %13 = fmul double %3, %12                       ; <double> [#uses=1]
   %14 = sext i32 %i.01 to i64                     ; <i64> [#uses=1]
-  %15 = getelementptr inbounds double* %d, i64 %14 ; <double*> [#uses=1]
+  %15 = getelementptr inbounds double, double* %d, i64 %14 ; <double*> [#uses=1]
   store double %13, double* %15, align 8
   %16 = add nsw i32 %i.01, 2                      ; <i32> [#uses=2]
   br label %bb1
diff --git a/test/Analysis/ScalarEvolution/nsw-offset.ll b/test/Analysis/ScalarEvolution/nsw-offset.ll
index 88cdcf23d9ed..127bb19bff02 100644
--- a/test/Analysis/ScalarEvolution/nsw-offset.ll
+++ b/test/Analysis/ScalarEvolution/nsw-offset.ll
@@ -22,23 +22,23 @@ bb:                                               ; preds = %bb.nph, %bb1
 ; CHECK: -->  {0,+,2}<nuw><nsw><%bb>
   %1 = sext i32 %i.01 to i64                      ; <i64> [#uses=1]
 
-; CHECK: %2 = getelementptr inbounds double* %d, i64 %1
+; CHECK: %2 = getelementptr inbounds double, double* %d, i64 %1
 ; CHECK: -->  {%d,+,16}<nsw><%bb>
-  %2 = getelementptr inbounds double* %d, i64 %1  ; <double*> [#uses=1]
+  %2 = getelementptr inbounds double, double* %d, i64 %1  ; <double*> [#uses=1]
 
-  %3 = load double* %2, align 8                   ; <double> [#uses=1]
+  %3 = load double, double* %2, align 8                   ; <double> [#uses=1]
   %4 = sext i32 %i.01 to i64                      ; <i64> [#uses=1]
-  %5 = getelementptr inbounds double* %q, i64 %4  ; <double*> [#uses=1]
-  %6 = load double* %5, align 8                   ; <double> [#uses=1]
+  %5 = getelementptr inbounds double, double* %q, i64 %4  ; <double*> [#uses=1]
+  %6 = load double, double* %5, align 8                   ; <double> [#uses=1]
   %7 = or i32 %i.01, 1                            ; <i32> [#uses=1]
 
 ; CHECK: %8 = sext i32 %7 to i64
 ; CHECK: -->  {1,+,2}<nuw><nsw><%bb>
   %8 = sext i32 %7 to i64                         ; <i64> [#uses=1]
 
-; CHECK: %9 = getelementptr inbounds double* %q, i64 %8
+; CHECK: %9 = getelementptr inbounds double, double* %q, i64 %8
 ; CHECK: {(8 + %q),+,16}<nsw><%bb>
-  %9 = getelementptr inbounds double* %q, i64 %8  ; <double*> [#uses=1]
+  %9 = getelementptr inbounds double, double* %q, i64 %8  ; <double*> [#uses=1]
 
 ; Artificially repeat the above three instructions, this time using
 ; add nsw instead of or.
@@ -48,16 +48,16 @@ bb:                                               ; preds = %bb.nph, %bb1
 ; CHECK: -->  {1,+,2}<nuw><nsw><%bb>
   %t8 = sext i32 %t7 to i64                         ; <i64> [#uses=1]
 
-; CHECK: %t9 = getelementptr inbounds double* %q, i64 %t8
+; CHECK: %t9 = getelementptr inbounds double, double* %q, i64 %t8
 ; CHECK: {(8 + %q),+,16}<nsw><%bb>
-  %t9 = getelementptr inbounds double* %q, i64 %t8  ; <double*> [#uses=1]
+  %t9 = getelementptr inbounds double, double* %q, i64 %t8  ; <double*> [#uses=1]
 
-  %10 = load double* %9, align 8                  ; <double> [#uses=1]
+  %10 = load double, double* %9, align 8                  ; <double> [#uses=1]
   %11 = fadd double %6, %10                       ; <double> [#uses=1]
   %12 = fadd double %11, 3.200000e+00             ; <double> [#uses=1]
   %13 = fmul double %3, %12                       ; <double> [#uses=1]
   %14 = sext i32 %i.01 to i64                     ; <i64> [#uses=1]
-  %15 = getelementptr inbounds double* %d, i64 %14 ; <double*> [#uses=1]
+  %15 = getelementptr inbounds double, double* %d, i64 %14 ; <double*> [#uses=1]
   store double %13, double* %15, align 8
   %16 = add nsw i32 %i.01, 2                      ; <i32> [#uses=2]
   br label %bb1
diff --git a/test/Analysis/ScalarEvolution/nsw.ll b/test/Analysis/ScalarEvolution/nsw.ll
index d776a5a5da78..15444e38b83c 100644
--- a/test/Analysis/ScalarEvolution/nsw.ll
+++ b/test/Analysis/ScalarEvolution/nsw.ll
@@ -7,7 +7,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64"
 ; CHECK: Classifying expressions for: @test1
 define void @test1(double* %p) nounwind {
 entry:
-	%tmp = load double* %p, align 8		; <double> [#uses=1]
+	%tmp = load double, double* %p, align 8		; <double> [#uses=1]
 	%tmp1 = fcmp ogt double %tmp, 2.000000e+00		; <i1> [#uses=1]
 	br i1 %tmp1, label %bb.nph, label %return
 
@@ -19,11 +19,11 @@ bb:		; preds = %bb1, %bb.nph
 ; CHECK: %i.01
 ; CHECK-NEXT: -->  {0,+,1}<nuw><nsw><%bb>
 	%tmp2 = sext i32 %i.01 to i64		; <i64> [#uses=1]
-	%tmp3 = getelementptr double* %p, i64 %tmp2		; <double*> [#uses=1]
-	%tmp4 = load double* %tmp3, align 8		; <double> [#uses=1]
+	%tmp3 = getelementptr double, double* %p, i64 %tmp2		; <double*> [#uses=1]
+	%tmp4 = load double, double* %tmp3, align 8		; <double> [#uses=1]
 	%tmp5 = fmul double %tmp4, 9.200000e+00		; <double> [#uses=1]
 	%tmp6 = sext i32 %i.01 to i64		; <i64> [#uses=1]
-	%tmp7 = getelementptr double* %p, i64 %tmp6		; <double*> [#uses=1]
+	%tmp7 = getelementptr double, double* %p, i64 %tmp6		; <double*> [#uses=1]
 ; CHECK: %tmp7
 ; CHECK-NEXT:   -->  {%p,+,8}<%bb>
 	store double %tmp5, double* %tmp7, align 8
@@ -36,10 +36,10 @@ bb1:		; preds = %bb
 	%phitmp = sext i32 %tmp8 to i64		; <i64> [#uses=1]
 ; CHECK: %phitmp
 ; CHECK-NEXT: -->  {1,+,1}<nuw><nsw><%bb>
-	%tmp9 = getelementptr double* %p, i64 %phitmp		; <double*> [#uses=1]
+	%tmp9 = getelementptr double, double* %p, i64 %phitmp		; <double*> [#uses=1]
 ; CHECK: %tmp9
 ; CHECK-NEXT:  -->  {(8 + %p),+,8}<%bb>
-	%tmp10 = load double* %tmp9, align 8		; <double> [#uses=1]
+	%tmp10 = load double, double* %tmp9, align 8		; <double> [#uses=1]
 	%tmp11 = fcmp ogt double %tmp10, 2.000000e+00		; <i1> [#uses=1]
 	br i1 %tmp11, label %bb, label %bb1.return_crit_edge
 
@@ -64,7 +64,7 @@ for.body.i.i:                                     ; preds = %for.body.i.i, %for.
 ; CHECK: %__first.addr.02.i.i
 ; CHECK-NEXT: -->  {%begin,+,4}<nuw><%for.body.i.i>
   store i32 0, i32* %__first.addr.02.i.i, align 4
-  %ptrincdec.i.i = getelementptr inbounds i32* %__first.addr.02.i.i, i64 1
+  %ptrincdec.i.i = getelementptr inbounds i32, i32* %__first.addr.02.i.i, i64 1
 ; CHECK: %ptrincdec.i.i
 ; CHECK-NEXT: -->  {(4 + %begin),+,4}<nuw><%for.body.i.i>
   %cmp.i.i = icmp eq i32* %ptrincdec.i.i, %end
@@ -90,10 +90,10 @@ for.body.i.i:                                     ; preds = %entry, %for.body.i.
   %tmp = add nsw i64 %indvar.i.i, 1
 ; CHECK: %tmp =
 ; CHECK: {1,+,1}<nuw><nsw><%for.body.i.i>
-  %ptrincdec.i.i = getelementptr inbounds i32* %begin, i64 %tmp
+  %ptrincdec.i.i = getelementptr inbounds i32, i32* %begin, i64 %tmp
 ; CHECK: %ptrincdec.i.i =
 ; CHECK: {(4 + %begin),+,4}<nsw><%for.body.i.i>
-  %__first.addr.08.i.i = getelementptr inbounds i32* %begin, i64 %indvar.i.i
+  %__first.addr.08.i.i = getelementptr inbounds i32, i32* %begin, i64 %indvar.i.i
 ; CHECK: %__first.addr.08.i.i
 ; CHECK: {%begin,+,4}<nsw><%for.body.i.i>
   store i32 0, i32* %__first.addr.08.i.i, align 4
@@ -124,17 +124,17 @@ exit:
 }
 
 ; CHECK-LABEL: PR12375
-; CHECK: -->  {(4 + %arg),+,4}<nuw><%bb1>		Exits: (8 + %arg)<nsw>
+; CHECK: -->  {(4 + %arg),+,4}<nuw><%bb1>{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: (8 + %arg)<nsw>
 define i32 @PR12375(i32* readnone %arg) {
 bb:
-  %tmp = getelementptr inbounds i32* %arg, i64 2
+  %tmp = getelementptr inbounds i32, i32* %arg, i64 2
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb
   %tmp2 = phi i32* [ %arg, %bb ], [ %tmp5, %bb1 ]
   %tmp3 = phi i32 [ 0, %bb ], [ %tmp4, %bb1 ]
   %tmp4 = add nsw i32 %tmp3, 1
-  %tmp5 = getelementptr inbounds i32* %tmp2, i64 1
+  %tmp5 = getelementptr inbounds i32, i32* %tmp2, i64 1
   %tmp6 = icmp ult i32* %tmp5, %tmp
   br i1 %tmp6, label %bb1, label %bb7
 
@@ -143,7 +143,7 @@ bb7:                                              ; preds = %bb1
 }
 
 ; CHECK-LABEL: PR12376
-; CHECK: -->  {(4 + %arg),+,4}<nuw><%bb2>		Exits: (4 + (4 * ((3 + (-1 * %arg) + (%arg umax %arg1)) /u 4)) + %arg)
+; CHECK: -->  {(4 + %arg),+,4}<nuw><%bb2>{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: (4 + (4 * ((3 + (-1 * %arg) + (%arg umax %arg1)) /u 4)) + %arg)
 define void @PR12376(i32* nocapture %arg, i32* nocapture %arg1)  {
 bb:
   br label %bb2
@@ -151,7 +151,7 @@ bb:
 bb2:                                              ; preds = %bb2, %bb
   %tmp = phi i32* [ %arg, %bb ], [ %tmp4, %bb2 ]
   %tmp3 = icmp ult i32* %tmp, %arg1
-  %tmp4 = getelementptr inbounds i32* %tmp, i64 1
+  %tmp4 = getelementptr inbounds i32, i32* %tmp, i64 1
   br i1 %tmp3, label %bb2, label %bb5
 
 bb5:                                              ; preds = %bb2
@@ -161,7 +161,7 @@ bb5:                                              ; preds = %bb2
 declare void @f(i32)
 
 ; CHECK-LABEL: nswnowrap
-; CHECK: --> {(1 + %v),+,1}<nsw><%for.body>   Exits: (2 + %v)
+; CHECK: --> {(1 + %v),+,1}<nsw><%for.body>{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: (2 + %v)
 define void @nswnowrap(i32 %v) {
 entry:
   %add = add nsw i32 %v, 1
diff --git a/test/Analysis/ScalarEvolution/pr22179.ll b/test/Analysis/ScalarEvolution/pr22179.ll
index d9fb5104436e..21ed055dc7b2 100644
--- a/test/Analysis/ScalarEvolution/pr22179.ll
+++ b/test/Analysis/ScalarEvolution/pr22179.ll
@@ -9,12 +9,12 @@
 ; Function Attrs: nounwind ssp uwtable
 define i32 @main() {
 ; CHECK-LABEL: Classifying expressions for: @main
-  store i8 0, i8* getelementptr inbounds (%struct.anon* @a, i64 0, i32 0), align 1
+  store i8 0, i8* getelementptr inbounds (%struct.anon, %struct.anon* @a, i64 0, i32 0), align 1
   br label %loop
 
 loop:
   %storemerge1 = phi i8 [ 0, %0 ], [ %inc, %loop ]
-  %m = load volatile i32* getelementptr inbounds (%struct.S* @b, i64 0, i32 0), align 4
+  %m = load volatile i32, i32* getelementptr inbounds (%struct.S, %struct.S* @b, i64 0, i32 0), align 4
   %inc = add nuw i8 %storemerge1, 1
 ; CHECK:   %inc = add nuw i8 %storemerge1, 1
 ; CHECK-NEXT: -->  {1,+,1}<nuw><%loop>
@@ -23,6 +23,6 @@ loop:
   br i1 %exitcond, label %exit, label %loop
 
 exit:
-  store i8 -128, i8* getelementptr inbounds (%struct.anon* @a, i64 0, i32 0), align 1
+  store i8 -128, i8* getelementptr inbounds (%struct.anon, %struct.anon* @a, i64 0, i32 0), align 1
   ret i32 0
 }
diff --git a/test/Analysis/ScalarEvolution/pr22641.ll b/test/Analysis/ScalarEvolution/pr22641.ll
new file mode 100644
index 000000000000..3b55afe08454
--- /dev/null
+++ b/test/Analysis/ScalarEvolution/pr22641.ll
@@ -0,0 +1,25 @@
+; RUN: opt -analyze -scalar-evolution < %s | FileCheck %s
+
+define i1 @main(i16 %a) {
+; CHECK-LABEL: Classifying expressions for: @main
+entry:
+  br label %body
+
+body:
+  %dec2 = phi i16 [ %a, %entry ], [ %dec, %cond ]
+  %dec = add i16 %dec2, -1
+  %conv2 = zext i16 %dec2 to i32
+  %conv = zext i16 %dec to i32
+; CHECK:   %conv = zext i16 %dec to i32
+; CHECK-NEXT: -->  {(zext i16 (-1 + %a) to i32),+,65535}<nuw><%body>
+; CHECK-NOT:  -->  {(65535 + (zext i16 %a to i32)),+,65535}<nuw><%body>
+
+  br label %cond
+
+cond:
+  br i1 false, label %body, label %exit
+
+exit:
+  %ret = icmp ne i32 %conv, 0
+  ret i1 %ret
+}
diff --git a/test/Analysis/ScalarEvolution/pr22674.ll b/test/Analysis/ScalarEvolution/pr22674.ll
new file mode 100644
index 000000000000..1bc7fd327d28
--- /dev/null
+++ b/test/Analysis/ScalarEvolution/pr22674.ll
@@ -0,0 +1,101 @@
+; RUN: opt -loop-reduce -S %s
+
+
+target datalayout = "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnux32"
+
+%"class.llvm::AttributeSetNode.230.2029.3828.6141.6912.7683.8454.9482.9996.10253.18506" = type { %"class.llvm::FoldingSetImpl::Node.1.1801.3600.5913.6684.7455.8226.9254.9768.10025.18505", i32 }
+%"class.llvm::FoldingSetImpl::Node.1.1801.3600.5913.6684.7455.8226.9254.9768.10025.18505" = type { i8* }
+%"struct.std::pair.241.2040.3839.6152.6923.7694.8465.9493.10007.10264.18507" = type { i32, %"class.llvm::AttributeSetNode.230.2029.3828.6141.6912.7683.8454.9482.9996.10253.18506"* }
+%"class.llvm::Attribute.222.2021.3820.6133.6904.7675.8446.9474.9988.10245.18509" = type { %"class.llvm::AttributeImpl.2.1802.3601.5914.6685.7456.8227.9255.9769.10026.18508"* }
+%"class.llvm::AttributeImpl.2.1802.3601.5914.6685.7456.8227.9255.9769.10026.18508" = type <{ i32 (...)**, %"class.llvm::FoldingSetImpl::Node.1.1801.3600.5913.6684.7455.8226.9254.9768.10025.18505", i8, [3 x i8] }>
+
+; Function Attrs: nounwind uwtable
+define void @_ZNK4llvm11AttrBuilder13hasAttributesENS_12AttributeSetEy() #0 align 2 {
+entry:
+  br i1 undef, label %cond.false, label %_ZNK4llvm12AttributeSet11getNumSlotsEv.exit
+
+_ZNK4llvm12AttributeSet11getNumSlotsEv.exit:      ; preds = %entry
+  br i1 undef, label %cond.false, label %for.body.lr.ph.for.body.lr.ph.split_crit_edge
+
+for.body.lr.ph.for.body.lr.ph.split_crit_edge:    ; preds = %_ZNK4llvm12AttributeSet11getNumSlotsEv.exit
+  br label %land.lhs.true.i
+
+land.lhs.true.i:                                  ; preds = %for.inc, %for.body.lr.ph.for.body.lr.ph.split_crit_edge
+  %I.099 = phi i32 [ 0, %for.body.lr.ph.for.body.lr.ph.split_crit_edge ], [ %inc, %for.inc ]
+  %cmp.i = icmp ugt i32 undef, %I.099
+  br i1 %cmp.i, label %_ZNK4llvm12AttributeSet12getSlotIndexEj.exit, label %cond.false.i.split
+
+cond.false.i.split:                               ; preds = %land.lhs.true.i
+  unreachable
+
+_ZNK4llvm12AttributeSet12getSlotIndexEj.exit:     ; preds = %land.lhs.true.i
+  br i1 undef, label %for.end, label %for.inc
+
+for.inc:                                          ; preds = %_ZNK4llvm12AttributeSet12getSlotIndexEj.exit
+  %inc = add i32 %I.099, 1
+  br i1 undef, label %cond.false, label %land.lhs.true.i
+
+for.end:                                          ; preds = %_ZNK4llvm12AttributeSet12getSlotIndexEj.exit
+  %I.099.lcssa129 = phi i32 [ %I.099, %_ZNK4llvm12AttributeSet12getSlotIndexEj.exit ]
+  br i1 undef, label %cond.false, label %_ZNK4llvm12AttributeSet3endEj.exit
+
+cond.false:                                       ; preds = %for.end, %for.inc, %_ZNK4llvm12AttributeSet11getNumSlotsEv.exit, %entry
+  unreachable
+
+_ZNK4llvm12AttributeSet3endEj.exit:               ; preds = %for.end
+  %second.i.i.i = getelementptr inbounds %"struct.std::pair.241.2040.3839.6152.6923.7694.8465.9493.10007.10264.18507", %"struct.std::pair.241.2040.3839.6152.6923.7694.8465.9493.10007.10264.18507"* undef, i32 %I.099.lcssa129, i32 1
+  %0 = load %"class.llvm::AttributeSetNode.230.2029.3828.6141.6912.7683.8454.9482.9996.10253.18506"*, %"class.llvm::AttributeSetNode.230.2029.3828.6141.6912.7683.8454.9482.9996.10253.18506"** %second.i.i.i, align 4, !tbaa !2
+  %NumAttrs.i.i.i = getelementptr inbounds %"class.llvm::AttributeSetNode.230.2029.3828.6141.6912.7683.8454.9482.9996.10253.18506", %"class.llvm::AttributeSetNode.230.2029.3828.6141.6912.7683.8454.9482.9996.10253.18506"* %0, i32 0, i32 1
+  %1 = load i32, i32* %NumAttrs.i.i.i, align 4, !tbaa !8
+  %add.ptr.i.i.i55 = getelementptr inbounds %"class.llvm::Attribute.222.2021.3820.6133.6904.7675.8446.9474.9988.10245.18509", %"class.llvm::Attribute.222.2021.3820.6133.6904.7675.8446.9474.9988.10245.18509"* undef, i32 %1
+  br i1 undef, label %return, label %for.body11
+
+for.cond9:                                        ; preds = %_ZNK4llvm9Attribute13getKindAsEnumEv.exit
+  %cmp10 = icmp eq %"class.llvm::Attribute.222.2021.3820.6133.6904.7675.8446.9474.9988.10245.18509"* %incdec.ptr, %add.ptr.i.i.i55
+  br i1 %cmp10, label %return, label %for.body11
+
+for.body11:                                       ; preds = %for.cond9, %_ZNK4llvm12AttributeSet3endEj.exit
+  %I5.096 = phi %"class.llvm::Attribute.222.2021.3820.6133.6904.7675.8446.9474.9988.10245.18509"* [ %incdec.ptr, %for.cond9 ], [ undef, %_ZNK4llvm12AttributeSet3endEj.exit ]
+  %2 = bitcast %"class.llvm::Attribute.222.2021.3820.6133.6904.7675.8446.9474.9988.10245.18509"* %I5.096 to i32*
+  %3 = load i32, i32* %2, align 4, !tbaa !10
+  %tobool.i59 = icmp eq i32 %3, 0
+  br i1 %tobool.i59, label %cond.false21, label %_ZNK4llvm9Attribute15isEnumAttributeEv.exit
+
+_ZNK4llvm9Attribute15isEnumAttributeEv.exit:      ; preds = %for.body11
+  switch i8 undef, label %cond.false21 [
+    i8 0, label %_ZNK4llvm9Attribute13getKindAsEnumEv.exit
+    i8 1, label %_ZNK4llvm9Attribute13getKindAsEnumEv.exit
+    i8 2, label %_ZNK4llvm9Attribute15getKindAsStringEv.exit
+  ]
+
+_ZNK4llvm9Attribute13getKindAsEnumEv.exit:        ; preds = %_ZNK4llvm9Attribute15isEnumAttributeEv.exit, %_ZNK4llvm9Attribute15isEnumAttributeEv.exit
+  %incdec.ptr = getelementptr inbounds %"class.llvm::Attribute.222.2021.3820.6133.6904.7675.8446.9474.9988.10245.18509", %"class.llvm::Attribute.222.2021.3820.6133.6904.7675.8446.9474.9988.10245.18509"* %I5.096, i32 1
+  br i1 undef, label %for.cond9, label %return
+
+cond.false21:                                     ; preds = %_ZNK4llvm9Attribute15isEnumAttributeEv.exit, %for.body11
+  unreachable
+
+_ZNK4llvm9Attribute15getKindAsStringEv.exit:      ; preds = %_ZNK4llvm9Attribute15isEnumAttributeEv.exit
+  unreachable
+
+return:                                           ; preds = %_ZNK4llvm9Attribute13getKindAsEnumEv.exit, %for.cond9, %_ZNK4llvm12AttributeSet3endEj.exit
+  ret void
+}
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 (ssh://llvm@gnu-4.sc.intel.com/export/server/git/llvm/clang 4c31740d4f81614b6d278c7825cfdae5a1c78799) (llvm/llvm.git b693958bd09144aed90312709a7e2ccf7124eb53)"}
+!2 = !{!3, !7, i64 4}
+!3 = !{!"_ZTSSt4pairIjPN4llvm16AttributeSetNodeEE", !4, i64 0, !7, i64 4}
+!4 = !{!"int", !5, i64 0}
+!5 = !{!"omnipotent char", !6, i64 0}
+!6 = !{!"Simple C/C++ TBAA"}
+!7 = !{!"any pointer", !5, i64 0}
+!8 = !{!9, !4, i64 4}
+!9 = !{!"_ZTSN4llvm16AttributeSetNodeE", !4, i64 4}
+!10 = !{!7, !7, i64 0}
diff --git a/test/Analysis/ScalarEvolution/range-signedness.ll b/test/Analysis/ScalarEvolution/range-signedness.ll
new file mode 100644
index 000000000000..d04fc9eb56ba
--- /dev/null
+++ b/test/Analysis/ScalarEvolution/range-signedness.ll
@@ -0,0 +1,39 @@
+; RUN: opt -analyze -scalar-evolution < %s | FileCheck %s
+
+define void @x(i1* %cond) {
+; CHECK-LABEL: Classifying expressions for: @x
+ entry:
+  br label %loop
+
+ loop:
+  %idx = phi i8 [ 0, %entry ], [ %idx.inc, %loop ]
+; CHECK: %idx = phi i8 [ 0, %entry ], [ %idx.inc, %loop ]
+; CHECK-NEXT:  -->  {0,+,1}<nuw><nsw><%loop> U: [0,-128) S: [0,-128)
+
+  %idx.inc = add nsw i8 %idx, 1
+
+  %c = load volatile i1, i1* %cond
+  br i1 %c, label %loop, label %exit
+
+ exit:
+  ret void
+}
+
+define void @y(i8* %addr) {
+; CHECK-LABEL: Classifying expressions for: @y
+ entry:
+  br label %loop
+
+ loop:
+  %idx = phi i8 [-5, %entry ], [ %idx.inc, %loop ]
+; CHECK:   %idx = phi i8 [ -5, %entry ], [ %idx.inc, %loop ]
+; CHECK-NEXT:  -->  {-5,+,1}<%loop> U: [-5,6) S: [-5,6)
+
+  %idx.inc = add i8 %idx, 1
+
+  %continue = icmp slt i8 %idx.inc, 6
+  br i1 %continue, label %loop, label %exit
+
+ exit:
+  ret void
+}
diff --git a/test/Analysis/ScalarEvolution/scev-aa.ll b/test/Analysis/ScalarEvolution/scev-aa.ll
index a0abbb787b00..e2123f44f167 100644
--- a/test/Analysis/ScalarEvolution/scev-aa.ll
+++ b/test/Analysis/ScalarEvolution/scev-aa.ll
@@ -19,11 +19,11 @@ entry:
 
 bb:
   %i = phi i64 [ 0, %entry ], [ %i.next, %bb ]
-  %pi = getelementptr double* %p, i64 %i
+  %pi = getelementptr double, double* %p, i64 %i
   %i.next = add i64 %i, 1
-  %pi.next = getelementptr double* %p, i64 %i.next
-  %x = load double* %pi
-  %y = load double* %pi.next
+  %pi.next = getelementptr double, double* %p, i64 %i.next
+  %x = load double, double* %pi
+  %y = load double, double* %pi.next
   %z = fmul double %x, %y
   store double %z, double* %pi
   %exitcond = icmp eq i64 %i.next, %n
@@ -58,18 +58,18 @@ bb:
   %i.next = add i64 %i, 1
 
   %e = add i64 %i, %j
-  %pi.j = getelementptr double* %p, i64 %e
+  %pi.j = getelementptr double, double* %p, i64 %e
   %f = add i64 %i.next, %j
-  %pi.next.j = getelementptr double* %p, i64 %f
-  %x = load double* %pi.j
-  %y = load double* %pi.next.j
+  %pi.next.j = getelementptr double, double* %p, i64 %f
+  %x = load double, double* %pi.j
+  %y = load double, double* %pi.next.j
   %z = fmul double %x, %y
   store double %z, double* %pi.j
 
   %o = add i64 %j, 91
   %g = add i64 %i, %o
-  %pi.j.next = getelementptr double* %p, i64 %g
-  %a = load double* %pi.j.next
+  %pi.j.next = getelementptr double, double* %p, i64 %g
+  %a = load double, double* %pi.j.next
   %b = fmul double %x, %a
   store double %b, double* %pi.j.next
 
@@ -115,18 +115,18 @@ bb:
   %i.next = add i64 %i, 1
 
   %e = add i64 %i, %j
-  %pi.j = getelementptr double* %p, i64 %e
+  %pi.j = getelementptr double, double* %p, i64 %e
   %f = add i64 %i.next, %j
-  %pi.next.j = getelementptr double* %p, i64 %f
-  %x = load double* %pi.j
-  %y = load double* %pi.next.j
+  %pi.next.j = getelementptr double, double* %p, i64 %f
+  %x = load double, double* %pi.j
+  %y = load double, double* %pi.next.j
   %z = fmul double %x, %y
   store double %z, double* %pi.j
 
   %o = add i64 %j, %n
   %g = add i64 %i, %o
-  %pi.j.next = getelementptr double* %p, i64 %g
-  %a = load double* %pi.j.next
+  %pi.j.next = getelementptr double, double* %p, i64 %g
+  %a = load double, double* %pi.j.next
   %b = fmul double %x, %a
   store double %b, double* %pi.j.next
 
@@ -161,12 +161,12 @@ return:
 define void @foo() {
 entry:
   %A = alloca %struct.A
-  %B = getelementptr %struct.A* %A, i32 0, i32 0
+  %B = getelementptr %struct.A, %struct.A* %A, i32 0, i32 0
   %Q = bitcast %struct.B* %B to %struct.A*
-  %Z = getelementptr %struct.A* %Q, i32 0, i32 1
-  %C = getelementptr %struct.B* %B, i32 1
+  %Z = getelementptr %struct.A, %struct.A* %Q, i32 0, i32 1
+  %C = getelementptr %struct.B, %struct.B* %B, i32 1
   %X = bitcast %struct.B* %C to i32*
-  %Y = getelementptr %struct.A* %A, i32 0, i32 1
+  %Y = getelementptr %struct.A, %struct.A* %A, i32 0, i32 1
   ret void
 }
 
@@ -181,12 +181,12 @@ entry:
 
 define void @bar() {
   %M = alloca %struct.A
-  %N = getelementptr %struct.A* %M, i32 0, i32 0
+  %N = getelementptr %struct.A, %struct.A* %M, i32 0, i32 0
   %O = bitcast %struct.B* %N to %struct.A*
-  %P = getelementptr %struct.A* %O, i32 0, i32 1
-  %R = getelementptr %struct.B* %N, i32 1
+  %P = getelementptr %struct.A, %struct.A* %O, i32 0, i32 1
+  %R = getelementptr %struct.B, %struct.B* %N, i32 1
   %W = bitcast %struct.B* %R to i32*
-  %V = getelementptr %struct.A* %M, i32 0, i32 1
+  %V = getelementptr %struct.A, %struct.A* %M, i32 0, i32 1
   ret void
 }
 
@@ -200,9 +200,9 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %i = phi i64 [ %inc, %for.body ], [ 0, %entry ] ; <i64> [#uses=2]
   %inc = add nsw i64 %i, 1                         ; <i64> [#uses=2]
-  %arrayidx = getelementptr inbounds i64* %p, i64 %inc
+  %arrayidx = getelementptr inbounds i64, i64* %p, i64 %inc
   store i64 0, i64* %arrayidx
-  %tmp6 = load i64* %p                            ; <i64> [#uses=1]
+  %tmp6 = load i64, i64* %p                            ; <i64> [#uses=1]
   %cmp = icmp slt i64 %inc, %tmp6                 ; <i1> [#uses=1]
   br i1 %cmp, label %for.body, label %for.end
 
diff --git a/test/Analysis/ScalarEvolution/scev-expander-incorrect-nowrap.ll b/test/Analysis/ScalarEvolution/scev-expander-incorrect-nowrap.ll
new file mode 100644
index 000000000000..012cad743dfe
--- /dev/null
+++ b/test/Analysis/ScalarEvolution/scev-expander-incorrect-nowrap.ll
@@ -0,0 +1,30 @@
+; RUN: opt -indvars -S < %s | FileCheck %s
+
+declare void @use(i32)
+declare void @use.i8(i8)
+
+define void @f() {
+; CHECK-LABEL: @f
+ entry:
+  br label %loop
+
+ loop:
+; The only use for idx.mirror is to induce an nuw for %idx.  It does
+; not induce an nuw for %idx.inc
+  %idx.mirror = phi i8 [ -6, %entry ], [ %idx.mirror.inc, %loop ]
+  %idx = phi i8 [ -5, %entry ], [ %idx.inc, %loop ]
+
+  %idx.sext = sext i8 %idx to i32
+  call void @use(i32 %idx.sext)
+
+  %idx.mirror.inc = add nuw i8 %idx.mirror, 1
+  call void @use.i8(i8 %idx.mirror.inc)
+
+  %idx.inc = add i8 %idx, 1
+; CHECK-NOT: %indvars.iv.next = add nuw nsw i32 %indvars.iv, 1
+  %cmp = icmp ugt i8 %idx.inc, 0
+  br i1 %cmp, label %loop, label %exit
+
+ exit:
+  ret void
+}
diff --git a/test/Analysis/ScalarEvolution/scev-prestart-nowrap.ll b/test/Analysis/ScalarEvolution/scev-prestart-nowrap.ll
new file mode 100644
index 000000000000..77f3482f03c0
--- /dev/null
+++ b/test/Analysis/ScalarEvolution/scev-prestart-nowrap.ll
@@ -0,0 +1,82 @@
+; RUN: opt -analyze -scalar-evolution < %s | FileCheck %s
+
+; An example run where SCEV(%postinc)->getStart() may overflow:
+;
+; %start = INT_SMAX
+; %low.limit = INT_SMIN
+; %high.limit = < not used >
+;
+; >> entry:
+;  %postinc.start = INT_SMIN
+;
+; >> loop:
+;  %idx = %start 
+;  %postinc = INT_SMIN
+;  %postinc.inc = INT_SMIN + 1
+;  %postinc.sext = sext(INT_SMIN) = i64 INT32_SMIN
+;  %break.early = INT_SMIN `slt` INT_SMIN = false
+;  br i1 false, ___,  %early.exit
+;
+; >> early.exit:
+;  ret i64 INT32_SMIN
+
+
+define i64 @bad.0(i32 %start, i32 %low.limit, i32 %high.limit) {
+; CHECK-LABEL: Classifying expressions for: @bad.0
+ entry:
+  %postinc.start = add i32 %start, 1
+  br label %loop
+
+ loop:
+  %idx = phi i32 [ %start, %entry ], [ %idx.inc, %continue ]
+  %postinc = phi i32 [ %postinc.start, %entry ], [ %postinc.inc, %continue ]
+  %postinc.inc = add nsw i32 %postinc, 1
+  %postinc.sext = sext i32 %postinc to i64
+; CHECK:  %postinc.sext = sext i32 %postinc to i64
+; CHECK-NEXT:  -->  {(sext i32 (1 + %start) to i64),+,1}<nsw><%loop>
+  %break.early = icmp slt i32 %postinc, %low.limit
+  br i1 %break.early, label %continue, label %early.exit
+
+ continue:
+  %idx.inc = add nsw i32 %idx, 1
+  %cmp = icmp slt i32 %idx.inc, %high.limit
+  br i1 %cmp, label %loop, label %exit
+
+ exit:
+  ret i64 0
+
+ early.exit:
+  ret i64 %postinc.sext
+}
+
+define i64 @bad.1(i32 %start, i32 %low.limit, i32 %high.limit, i1* %unknown) {
+; CHECK-LABEL: Classifying expressions for: @bad.1
+ entry:
+  %postinc.start = add i32 %start, 1
+  br label %loop
+
+ loop:
+  %idx = phi i32 [ %start, %entry ], [ %idx.inc, %continue ], [ %idx.inc, %continue.1 ]
+  %postinc = phi i32 [ %postinc.start, %entry ], [ %postinc.inc, %continue ], [ %postinc.inc, %continue.1 ]
+  %postinc.inc = add nsw i32 %postinc, 1
+  %postinc.sext = sext i32 %postinc to i64
+; CHECK:  %postinc.sext = sext i32 %postinc to i64
+; CHECK-NEXT:  -->  {(sext i32 (1 + %start) to i64),+,1}<nsw><%loop>
+  %break.early = icmp slt i32 %postinc, %low.limit
+  br i1 %break.early, label %continue.1, label %early.exit
+
+ continue.1:
+  %cond = load volatile i1, i1* %unknown
+  %idx.inc = add nsw i32 %idx, 1
+  br i1 %cond, label %loop, label %continue
+
+ continue:
+  %cmp = icmp slt i32 %idx.inc, %high.limit
+  br i1 %cmp, label %loop, label %exit
+
+ exit:
+  ret i64 0
+
+ early.exit:
+  ret i64 %postinc.sext
+}
diff --git a/test/Analysis/ScalarEvolution/sext-inreg.ll b/test/Analysis/ScalarEvolution/sext-inreg.ll
index 8b3d641943db..8f1d5bdbebad 100644
--- a/test/Analysis/ScalarEvolution/sext-inreg.ll
+++ b/test/Analysis/ScalarEvolution/sext-inreg.ll
@@ -16,7 +16,7 @@ bb:		; preds = %bb, %entry
 	%t2 = ashr i64 %t1, 7		; <i32> [#uses=1]
 	%s1 = shl i64 %i.01, 5		; <i32> [#uses=1]
 	%s2 = ashr i64 %s1, 5		; <i32> [#uses=1]
-	%t3 = getelementptr i64* %x, i64 %i.01		; <i64*> [#uses=1]
+	%t3 = getelementptr i64, i64* %x, i64 %i.01		; <i64*> [#uses=1]
 	store i64 0, i64* %t3, align 1
 	%indvar.next = add i64 %i.01, 199		; <i32> [#uses=2]
 	%exitcond = icmp eq i64 %indvar.next, %n		; <i1> [#uses=1]
diff --git a/test/Analysis/ScalarEvolution/sext-iv-0.ll b/test/Analysis/ScalarEvolution/sext-iv-0.ll
index d5d32689e17c..5634078d2b0e 100644
--- a/test/Analysis/ScalarEvolution/sext-iv-0.ll
+++ b/test/Analysis/ScalarEvolution/sext-iv-0.ll
@@ -13,21 +13,21 @@ bb1.thread:
 bb1:		; preds = %bb1, %bb1.thread
 	%i.0.reg2mem.0 = phi i64 [ -128, %bb1.thread ], [ %8, %bb1 ]		; <i64> [#uses=3]
 ; CHECK: %i.0.reg2mem.0
-; CHECK-NEXT: -->  {-128,+,1}<%bb1>		Exits: 127
+; CHECK-NEXT: -->  {-128,+,1}<%bb1>{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: 127
 	%0 = trunc i64 %i.0.reg2mem.0 to i8		; <i8> [#uses=1]
 ; CHECK: %0
-; CHECK-NEXT: -->  {-128,+,1}<%bb1>		Exits: 127
+; CHECK-NEXT: -->  {-128,+,1}<%bb1>{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: 127
 	%1 = trunc i64 %i.0.reg2mem.0 to i9		; <i8> [#uses=1]
 ; CHECK: %1
-; CHECK-NEXT: -->  {-128,+,1}<%bb1>		Exits: 127
+; CHECK-NEXT: -->  {-128,+,1}<%bb1>{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: 127
 	%2 = sext i9 %1 to i64		; <i64> [#uses=1]
 ; CHECK: %2
-; CHECK-NEXT: -->  {-128,+,1}<nsw><%bb1>	Exits: 127
-	%3 = getelementptr double* %x, i64 %2		; <double*> [#uses=1]
-	%4 = load double* %3, align 8		; <double> [#uses=1]
+; CHECK-NEXT: -->  {-128,+,1}<nsw><%bb1>{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: 127
+	%3 = getelementptr double, double* %x, i64 %2		; <double*> [#uses=1]
+	%4 = load double, double* %3, align 8		; <double> [#uses=1]
 	%5 = fmul double %4, 3.900000e+00		; <double> [#uses=1]
 	%6 = sext i8 %0 to i64		; <i64> [#uses=1]
-	%7 = getelementptr double* %x, i64 %6		; <double*> [#uses=1]
+	%7 = getelementptr double, double* %x, i64 %6		; <double*> [#uses=1]
 	store double %5, double* %7, align 8
 	%8 = add i64 %i.0.reg2mem.0, 1		; <i64> [#uses=2]
 	%9 = icmp sgt i64 %8, 127		; <i1> [#uses=1]
diff --git a/test/Analysis/ScalarEvolution/sext-iv-1.ll b/test/Analysis/ScalarEvolution/sext-iv-1.ll
index a6f70dbff9a0..575b744a1a40 100644
--- a/test/Analysis/ScalarEvolution/sext-iv-1.ll
+++ b/test/Analysis/ScalarEvolution/sext-iv-1.ll
@@ -23,11 +23,11 @@ bb1:		; preds = %bb1, %bb1.thread
 	%0 = trunc i64 %i.0.reg2mem.0 to i7		; <i8> [#uses=1]
 	%1 = trunc i64 %i.0.reg2mem.0 to i9		; <i8> [#uses=1]
 	%2 = sext i9 %1 to i64		; <i64> [#uses=1]
-	%3 = getelementptr double* %x, i64 %2		; <double*> [#uses=1]
-	%4 = load double* %3, align 8		; <double> [#uses=1]
+	%3 = getelementptr double, double* %x, i64 %2		; <double*> [#uses=1]
+	%4 = load double, double* %3, align 8		; <double> [#uses=1]
 	%5 = fmul double %4, 3.900000e+00		; <double> [#uses=1]
 	%6 = sext i7 %0 to i64		; <i64> [#uses=1]
-	%7 = getelementptr double* %x, i64 %6		; <double*> [#uses=1]
+	%7 = getelementptr double, double* %x, i64 %6		; <double*> [#uses=1]
 	store double %5, double* %7, align 8
 	%8 = add i64 %i.0.reg2mem.0, 1		; <i64> [#uses=2]
 	%9 = icmp sgt i64 %8, 127		; <i1> [#uses=1]
@@ -46,11 +46,11 @@ bb1:		; preds = %bb1, %bb1.thread
 	%0 = trunc i64 %i.0.reg2mem.0 to i8		; <i8> [#uses=1]
 	%1 = trunc i64 %i.0.reg2mem.0 to i9		; <i8> [#uses=1]
 	%2 = sext i9 %1 to i64		; <i64> [#uses=1]
-	%3 = getelementptr double* %x, i64 %2		; <double*> [#uses=1]
-	%4 = load double* %3, align 8		; <double> [#uses=1]
+	%3 = getelementptr double, double* %x, i64 %2		; <double*> [#uses=1]
+	%4 = load double, double* %3, align 8		; <double> [#uses=1]
 	%5 = fmul double %4, 3.900000e+00		; <double> [#uses=1]
 	%6 = sext i8 %0 to i64		; <i64> [#uses=1]
-	%7 = getelementptr double* %x, i64 %6		; <double*> [#uses=1]
+	%7 = getelementptr double, double* %x, i64 %6		; <double*> [#uses=1]
 	store double %5, double* %7, align 8
 	%8 = add i64 %i.0.reg2mem.0, 1		; <i64> [#uses=2]
 	%9 = icmp sgt i64 %8, 128		; <i1> [#uses=1]
@@ -69,11 +69,11 @@ bb1:		; preds = %bb1, %bb1.thread
 	%0 = trunc i64 %i.0.reg2mem.0 to i8		; <i8> [#uses=1]
 	%1 = trunc i64 %i.0.reg2mem.0 to i9		; <i8> [#uses=1]
 	%2 = sext i9 %1 to i64		; <i64> [#uses=1]
-	%3 = getelementptr double* %x, i64 %2		; <double*> [#uses=1]
-	%4 = load double* %3, align 8		; <double> [#uses=1]
+	%3 = getelementptr double, double* %x, i64 %2		; <double*> [#uses=1]
+	%4 = load double, double* %3, align 8		; <double> [#uses=1]
 	%5 = fmul double %4, 3.900000e+00		; <double> [#uses=1]
 	%6 = sext i8 %0 to i64		; <i64> [#uses=1]
-	%7 = getelementptr double* %x, i64 %6		; <double*> [#uses=1]
+	%7 = getelementptr double, double* %x, i64 %6		; <double*> [#uses=1]
 	store double %5, double* %7, align 8
 	%8 = add i64 %i.0.reg2mem.0, 1		; <i64> [#uses=2]
 	%9 = icmp sgt i64 %8, 127		; <i1> [#uses=1]
@@ -92,11 +92,11 @@ bb1:		; preds = %bb1, %bb1.thread
 	%0 = trunc i64 %i.0.reg2mem.0 to i8		; <i8> [#uses=1]
 	%1 = trunc i64 %i.0.reg2mem.0 to i9		; <i8> [#uses=1]
 	%2 = sext i9 %1 to i64		; <i64> [#uses=1]
-	%3 = getelementptr double* %x, i64 %2		; <double*> [#uses=1]
-	%4 = load double* %3, align 8		; <double> [#uses=1]
+	%3 = getelementptr double, double* %x, i64 %2		; <double*> [#uses=1]
+	%4 = load double, double* %3, align 8		; <double> [#uses=1]
 	%5 = fmul double %4, 3.900000e+00		; <double> [#uses=1]
 	%6 = sext i8 %0 to i64		; <i64> [#uses=1]
-	%7 = getelementptr double* %x, i64 %6		; <double*> [#uses=1]
+	%7 = getelementptr double, double* %x, i64 %6		; <double*> [#uses=1]
 	store double %5, double* %7, align 8
 	%8 = add i64 %i.0.reg2mem.0, -1		; <i64> [#uses=2]
 	%9 = icmp sgt i64 %8, 127		; <i1> [#uses=1]
diff --git a/test/Analysis/ScalarEvolution/sext-iv-2.ll b/test/Analysis/ScalarEvolution/sext-iv-2.ll
index 97e252c1fb3e..8749ff3987fa 100644
--- a/test/Analysis/ScalarEvolution/sext-iv-2.ll
+++ b/test/Analysis/ScalarEvolution/sext-iv-2.ll
@@ -1,9 +1,9 @@
 ; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s
 
 ; CHECK: %tmp3 = sext i8 %tmp2 to i32
-; CHECK: -->  (sext i8 {0,+,1}<%bb1> to i32)   Exits: -1
+; CHECK: -->  (sext i8 {0,+,1}<%bb1> to i32){{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: -1
 ; CHECK: %tmp4 = mul i32 %tmp3, %i.02
-; CHECK: -->  ((sext i8 {0,+,1}<%bb1> to i32) * {0,+,1}<%bb>)   Exits: {0,+,-1}<%bb>
+; CHECK: -->  ((sext i8 {0,+,1}<%bb1> to i32) * {0,+,1}<%bb>){{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: {0,+,-1}<%bb>
 
 ; These sexts are not foldable.
 
@@ -32,7 +32,7 @@ bb1:		; preds = %bb2, %bb.nph
 	%tmp4 = mul i32 %tmp3, %i.02		; <i32> [#uses=1]
 	%tmp5 = sext i32 %i.02 to i64		; <i64> [#uses=1]
 	%tmp6 = sext i32 %j.01 to i64		; <i64> [#uses=1]
-	%tmp7 = getelementptr [32 x [256 x i32]]* @table, i64 0, i64 %tmp5, i64 %tmp6		; <i32*> [#uses=1]
+	%tmp7 = getelementptr [32 x [256 x i32]], [32 x [256 x i32]]* @table, i64 0, i64 %tmp5, i64 %tmp6		; <i32*> [#uses=1]
 	store i32 %tmp4, i32* %tmp7, align 4
 	%tmp8 = add i32 %j.01, 1		; <i32> [#uses=2]
 	br label %bb2
@@ -56,7 +56,7 @@ bb4.bb5_crit_edge:		; preds = %bb4
 	br label %bb5
 
 bb5:		; preds = %bb4.bb5_crit_edge, %entry
-	%tmp12 = load i32* getelementptr ([32 x [256 x i32]]* @table, i64 0, i64 9, i64 132), align 16		; <i32> [#uses=1]
+	%tmp12 = load i32, i32* getelementptr ([32 x [256 x i32]], [32 x [256 x i32]]* @table, i64 0, i64 9, i64 132), align 16		; <i32> [#uses=1]
 	%tmp13 = icmp eq i32 %tmp12, -1116		; <i1> [#uses=1]
 	br i1 %tmp13, label %bb7, label %bb6
 
diff --git a/test/Analysis/ScalarEvolution/sle.ll b/test/Analysis/ScalarEvolution/sle.ll
index f38f6b63dce4..f24c4807114f 100644
--- a/test/Analysis/ScalarEvolution/sle.ll
+++ b/test/Analysis/ScalarEvolution/sle.ll
@@ -14,8 +14,8 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ] ; <i64> [#uses=2]
-  %arrayidx = getelementptr double* %p, i64 %i    ; <double*> [#uses=2]
-  %t4 = load double* %arrayidx                    ; <double> [#uses=1]
+  %arrayidx = getelementptr double, double* %p, i64 %i    ; <double*> [#uses=2]
+  %t4 = load double, double* %arrayidx                    ; <double> [#uses=1]
   %mul = fmul double %t4, 2.200000e+00            ; <double> [#uses=1]
   store double %mul, double* %arrayidx
   %i.next = add nsw i64 %i, 1                     ; <i64> [#uses=2]
diff --git a/test/Analysis/ScalarEvolution/trip-count.ll b/test/Analysis/ScalarEvolution/trip-count.ll
index f89125aeb29b..1b75c88c753c 100644
--- a/test/Analysis/ScalarEvolution/trip-count.ll
+++ b/test/Analysis/ScalarEvolution/trip-count.ll
@@ -1,16 +1,20 @@
 ; RUN: opt < %s -analyze -scalar-evolution -scalar-evolution-max-iterations=0 | FileCheck %s
 ; PR1101
 
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
 @A = weak global [1000 x i32] zeroinitializer, align 32         
 
+; CHECK: Printing analysis 'Scalar Evolution Analysis' for function 'test1':
 ; CHECK: backedge-taken count is 10000
 
-define void @test(i32 %N) {
+define void @test1(i32 %N) {
 entry:
         br label %bb3
 
 bb:             ; preds = %bb3
-        %tmp = getelementptr [1000 x i32]* @A, i32 0, i32 %i.0          ; <i32*> [#uses=1]
+        %tmp = getelementptr [1000 x i32], [1000 x i32]* @A, i32 0, i32 %i.0          ; <i32*> [#uses=1]
         store i32 123, i32* %tmp
         %tmp2 = add i32 %i.0, 1         ; <i32> [#uses=1]
         br label %bb3
@@ -26,3 +30,61 @@ bb5:            ; preds = %bb3
 return:         ; preds = %bb5
         ret void
 }
+
+; PR22795
+; CHECK: Printing analysis 'Scalar Evolution Analysis' for function 'test2':
+; CHECK:   %iv = phi i32 [ -1, %entry ], [ %next.1, %for.inc.1 ]
+; CHECK-NEXT:  -->  {-1,+,2}<%preheader> U: full-set S: full-set             Exits: 13
+
+define i32 @test2() {
+entry:
+  %bins = alloca [16 x i64], align 16
+  %0 = bitcast [16 x i64]* %bins to i8*
+  call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 128, i32 16, i1 false)
+  br label %preheader
+
+preheader:                                        ; preds = %for.inc.1, %entry
+  %v11 = phi i64 [ 0, %entry ], [ %next12.1, %for.inc.1 ]
+  %iv = phi i32 [ -1, %entry ], [ %next.1, %for.inc.1 ]
+  %cmp = icmp sgt i64 %v11, 0
+  br i1 %cmp, label %for.body, label %for.inc
+
+for.body:                                         ; preds = %preheader
+  %zext = zext i32 %iv to i64
+  %arrayidx = getelementptr [16 x i64], [16 x i64]* %bins, i64 0, i64 %v11
+  %loaded = load i64, i64* %arrayidx, align 8
+  %add = add i64 %loaded, 1
+  %add2 = add i64 %add, %zext
+  store i64 %add2, i64* %arrayidx, align 8
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body, %preheader
+  %next12 = add nuw nsw i64 %v11, 1
+  %next = add nsw i32 %iv, 1
+  br i1 true, label %for.body.1, label %for.inc.1
+
+end:                                              ; preds = %for.inc.1
+  %arrayidx8 = getelementptr [16 x i64], [16 x i64]* %bins, i64 0, i64 2
+  %load = load i64, i64* %arrayidx8, align 16
+  %shr4 = lshr i64 %load, 32
+  %conv = trunc i64 %shr4 to i32
+  ret i32 %conv
+
+for.body.1:                                       ; preds = %for.inc
+  %zext.1 = zext i32 %next to i64
+  %arrayidx.1 = getelementptr [16 x i64], [16 x i64]* %bins, i64 0, i64 %next12
+  %loaded.1 = load i64, i64* %arrayidx.1, align 8
+  %add.1 = add i64 %loaded.1, 1
+  %add2.1 = add i64 %add.1, %zext.1
+  store i64 %add2.1, i64* %arrayidx.1, align 8
+  br label %for.inc.1
+
+for.inc.1:                                        ; preds = %for.body.1, %for.inc
+  %next12.1 = add nuw nsw i64 %next12, 1
+  %next.1 = add nuw nsw i32 %next, 1
+  %exitcond.1 = icmp eq i64 %next12.1, 16
+  br i1 %exitcond.1, label %end, label %preheader
+}
+
+; Function Attrs: nounwind
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #0
diff --git a/test/Analysis/ScalarEvolution/trip-count11.ll b/test/Analysis/ScalarEvolution/trip-count11.ll
index e14af08e33f8..819a89efd507 100644
--- a/test/Analysis/ScalarEvolution/trip-count11.ll
+++ b/test/Analysis/ScalarEvolution/trip-count11.ll
@@ -13,15 +13,15 @@ entry:
 
 for.cond:                                         ; preds = %for.inc, %entry
   %sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ]
-; CHECK: --> %sum.0 Exits: 28
+; CHECK: --> %sum.0{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: 28
   %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
   %cmp = icmp ult i32 %i.0, 8
   br i1 %cmp, label %for.inc, label %for.end
 
 for.inc:                                          ; preds = %for.cond
   %idxprom = sext i32 %i.0 to i64
-  %arrayidx = getelementptr inbounds [8 x i32]* @foo.a, i64 0, i64 %idxprom
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [8 x i32], [8 x i32]* @foo.a, i64 0, i64 %idxprom
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %sum.0, %0
   %inc = add nsw i32 %i.0, 1
   br label %for.cond
@@ -36,15 +36,15 @@ entry:
 
 for.cond:                                         ; preds = %for.inc, %entry
   %sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ]
-; CHECK: --> %sum.0 Exits: 28
+; CHECK: --> %sum.0{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: 28
   %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
   %cmp = icmp ult i32 %i.0, 8
   br i1 %cmp, label %for.inc, label %for.end
 
 for.inc:                                          ; preds = %for.cond
   %idxprom = sext i32 %i.0 to i64
-  %arrayidx = getelementptr inbounds [8 x i32] addrspace(1)* @foo.a_as1, i64 0, i64 %idxprom
-  %0 = load i32 addrspace(1)* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [8 x i32], [8 x i32] addrspace(1)* @foo.a_as1, i64 0, i64 %idxprom
+  %0 = load i32, i32 addrspace(1)* %arrayidx, align 4
   %add = add nsw i32 %sum.0, %0
   %inc = add nsw i32 %i.0, 1
   br label %for.cond
diff --git a/test/Analysis/ScalarEvolution/trip-count12.ll b/test/Analysis/ScalarEvolution/trip-count12.ll
index 8f960e1c1c77..d0086ee2e6ac 100644
--- a/test/Analysis/ScalarEvolution/trip-count12.ll
+++ b/test/Analysis/ScalarEvolution/trip-count12.ll
@@ -16,8 +16,8 @@ for.body:                                         ; preds = %for.body, %for.body
   %p.addr.05 = phi i16* [ %incdec.ptr, %for.body ], [ %p, %for.body.preheader ]
   %len.addr.04 = phi i32 [ %sub, %for.body ], [ %len, %for.body.preheader ]
   %res.03 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
-  %incdec.ptr = getelementptr inbounds i16* %p.addr.05, i32 1
-  %0 = load i16* %p.addr.05, align 2
+  %incdec.ptr = getelementptr inbounds i16, i16* %p.addr.05, i32 1
+  %0 = load i16, i16* %p.addr.05, align 2
   %conv = zext i16 %0 to i32
   %add = add i32 %conv, %res.03
   %sub = add nsw i32 %len.addr.04, -2
diff --git a/test/Analysis/ScalarEvolution/trip-count2.ll b/test/Analysis/ScalarEvolution/trip-count2.ll
index e76488abfca5..d988eff7cfa1 100644
--- a/test/Analysis/ScalarEvolution/trip-count2.ll
+++ b/test/Analysis/ScalarEvolution/trip-count2.ll
@@ -10,7 +10,7 @@ entry:
         br label %bb3
 
 bb:             ; preds = %bb3
-        %tmp = getelementptr [1000 x i32]* @A, i32 0, i32 %i.0          ; <i32*> [#uses=1]
+        %tmp = getelementptr [1000 x i32], [1000 x i32]* @A, i32 0, i32 %i.0          ; <i32*> [#uses=1]
         store i32 123, i32* %tmp
         %tmp4 = mul i32 %i.0, 4         ; <i32> [#uses=1]
         %tmp5 = or i32 %tmp4, 1
diff --git a/test/Analysis/ScalarEvolution/trip-count3.ll b/test/Analysis/ScalarEvolution/trip-count3.ll
index 850e035e7c6b..cce0182d6493 100644
--- a/test/Analysis/ScalarEvolution/trip-count3.ll
+++ b/test/Analysis/ScalarEvolution/trip-count3.ll
@@ -48,10 +48,10 @@ sha_update.exit.exitStub:                         ; preds = %bb3.i
   ret void
 
 bb2.i:                                            ; preds = %bb3.i
-  %1 = getelementptr %struct.SHA_INFO* %sha_info, i64 0, i32 3
+  %1 = getelementptr %struct.SHA_INFO, %struct.SHA_INFO* %sha_info, i64 0, i32 3
   %2 = bitcast [16 x i32]* %1 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %buffer_addr.0.i, i64 64, i32 1, i1 false)
-  %3 = getelementptr %struct.SHA_INFO* %sha_info, i64 0, i32 3, i64 0
+  %3 = getelementptr %struct.SHA_INFO, %struct.SHA_INFO* %sha_info, i64 0, i32 3, i64 0
   %4 = bitcast i32* %3 to i8*
   br label %codeRepl
 
@@ -61,7 +61,7 @@ codeRepl:                                         ; preds = %bb2.i
 
 byte_reverse.exit.i:                              ; preds = %codeRepl
   call fastcc void @sha_transform(%struct.SHA_INFO* %sha_info) nounwind
-  %5 = getelementptr i8* %buffer_addr.0.i, i64 64
+  %5 = getelementptr i8, i8* %buffer_addr.0.i, i64 64
   %6 = add i32 %count_addr.0.i, -64
   br label %bb3.i
 
diff --git a/test/Analysis/ScalarEvolution/trip-count4.ll b/test/Analysis/ScalarEvolution/trip-count4.ll
index b7184a48fe85..966ffd26fd28 100644
--- a/test/Analysis/ScalarEvolution/trip-count4.ll
+++ b/test/Analysis/ScalarEvolution/trip-count4.ll
@@ -12,8 +12,8 @@ loop:		; preds = %loop, %entry
 	%indvar = phi i64 [ %n, %entry ], [ %indvar.next, %loop ]		; <i64> [#uses=4]
 	%s0 = shl i64 %indvar, 8		; <i64> [#uses=1]
 	%indvar.i8 = ashr i64 %s0, 8		; <i64> [#uses=1]
-	%t0 = getelementptr double* %d, i64 %indvar.i8		; <double*> [#uses=2]
-	%t1 = load double* %t0		; <double> [#uses=1]
+	%t0 = getelementptr double, double* %d, i64 %indvar.i8		; <double*> [#uses=2]
+	%t1 = load double, double* %t0		; <double> [#uses=1]
 	%t2 = fmul double %t1, 1.000000e-01		; <double> [#uses=1]
 	store double %t2, double* %t0
 	%indvar.next = sub i64 %indvar, 1		; <i64> [#uses=2]
diff --git a/test/Analysis/ScalarEvolution/trip-count5.ll b/test/Analysis/ScalarEvolution/trip-count5.ll
index 68a1ae14a7ab..dc02fedd1342 100644
--- a/test/Analysis/ScalarEvolution/trip-count5.ll
+++ b/test/Analysis/ScalarEvolution/trip-count5.ll
@@ -9,7 +9,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 define float @t(float* %pTmp1, float* %peakWeight, float* %nrgReducePeakrate, i32 %bim) nounwind {
 entry:
-	%tmp3 = load float* %peakWeight, align 4		; <float> [#uses=2]
+	%tmp3 = load float, float* %peakWeight, align 4		; <float> [#uses=2]
 	%tmp2538 = icmp sgt i32 %bim, 0		; <i1> [#uses=1]
 	br i1 %tmp2538, label %bb.nph, label %bb4
 
@@ -21,13 +21,13 @@ bb:		; preds = %bb1, %bb.nph
 	%hiPart.035 = phi i32 [ %tmp12, %bb1 ], [ 0, %bb.nph ]		; <i32> [#uses=2]
 	%peakCount.034 = phi float [ %tmp19, %bb1 ], [ %tmp3, %bb.nph ]		; <float> [#uses=1]
 	%tmp6 = sext i32 %hiPart.035 to i64		; <i64> [#uses=1]
-	%tmp7 = getelementptr float* %pTmp1, i64 %tmp6		; <float*> [#uses=1]
-	%tmp8 = load float* %tmp7, align 4		; <float> [#uses=1]
+	%tmp7 = getelementptr float, float* %pTmp1, i64 %tmp6		; <float*> [#uses=1]
+	%tmp8 = load float, float* %tmp7, align 4		; <float> [#uses=1]
 	%tmp10 = fadd float %tmp8, %distERBhi.036		; <float> [#uses=3]
 	%tmp12 = add i32 %hiPart.035, 1		; <i32> [#uses=3]
 	%tmp15 = sext i32 %tmp12 to i64		; <i64> [#uses=1]
-	%tmp16 = getelementptr float* %peakWeight, i64 %tmp15		; <float*> [#uses=1]
-	%tmp17 = load float* %tmp16, align 4		; <float> [#uses=1]
+	%tmp16 = getelementptr float, float* %peakWeight, i64 %tmp15		; <float*> [#uses=1]
+	%tmp17 = load float, float* %tmp16, align 4		; <float> [#uses=1]
 	%tmp19 = fadd float %tmp17, %peakCount.034		; <float> [#uses=2]
 	br label %bb1
 
diff --git a/test/Analysis/ScalarEvolution/trip-count6.ll b/test/Analysis/ScalarEvolution/trip-count6.ll
index 0f394a09d156..7980bbdcb121 100644
--- a/test/Analysis/ScalarEvolution/trip-count6.ll
+++ b/test/Analysis/ScalarEvolution/trip-count6.ll
@@ -12,8 +12,8 @@ entry:
 bb:             ; preds = %bb4, %entry
   %mode.0 = phi i8 [ 0, %entry ], [ %indvar.next, %bb4 ]                ; <i8> [#uses=4]
   zext i8 %mode.0 to i32                ; <i32>:1 [#uses=1]
-  getelementptr [4 x i32]* @mode_table, i32 0, i32 %1           ; <i32*>:2 [#uses=1]
-  load i32* %2, align 4         ; <i32>:3 [#uses=1]
+  getelementptr [4 x i32], [4 x i32]* @mode_table, i32 0, i32 %1           ; <i32*>:2 [#uses=1]
+  load i32, i32* %2, align 4         ; <i32>:3 [#uses=1]
   icmp eq i32 %3, %0            ; <i1>:4 [#uses=1]
   br i1 %4, label %bb1, label %bb2
 
diff --git a/test/Analysis/ScalarEvolution/trip-count7.ll b/test/Analysis/ScalarEvolution/trip-count7.ll
index d01a18a468f0..bbe76c490cdd 100644
--- a/test/Analysis/ScalarEvolution/trip-count7.ll
+++ b/test/Analysis/ScalarEvolution/trip-count7.ll
@@ -72,57 +72,57 @@ bb.i:		; preds = %bb7.i
 	%tmp = add i32 %j.0.i, 1		; <i32> [#uses=5]
 	store i32 0, i32* %q, align 4
 	%tmp1 = sext i32 %tmp to i64		; <i64> [#uses=1]
-	%tmp2 = getelementptr [9 x i32]* %a, i64 0, i64 %tmp1		; <i32*> [#uses=1]
-	%tmp3 = load i32* %tmp2, align 4		; <i32> [#uses=1]
+	%tmp2 = getelementptr [9 x i32], [9 x i32]* %a, i64 0, i64 %tmp1		; <i32*> [#uses=1]
+	%tmp3 = load i32, i32* %tmp2, align 4		; <i32> [#uses=1]
 	%tmp4 = icmp eq i32 %tmp3, 0		; <i1> [#uses=1]
 	br i1 %tmp4, label %bb.i.bb7.i.backedge_crit_edge, label %bb1.i
 
 bb1.i:		; preds = %bb.i
 	%tmp5 = add i32 %j.0.i, 2		; <i32> [#uses=1]
 	%tmp6 = sext i32 %tmp5 to i64		; <i64> [#uses=1]
-	%tmp7 = getelementptr [17 x i32]* %b, i64 0, i64 %tmp6		; <i32*> [#uses=1]
-	%tmp8 = load i32* %tmp7, align 4		; <i32> [#uses=1]
+	%tmp7 = getelementptr [17 x i32], [17 x i32]* %b, i64 0, i64 %tmp6		; <i32*> [#uses=1]
+	%tmp8 = load i32, i32* %tmp7, align 4		; <i32> [#uses=1]
 	%tmp9 = icmp eq i32 %tmp8, 0		; <i1> [#uses=1]
 	br i1 %tmp9, label %bb1.i.bb7.i.backedge_crit_edge, label %bb2.i
 
 bb2.i:		; preds = %bb1.i
 	%tmp10 = sub i32 7, %j.0.i		; <i32> [#uses=1]
 	%tmp11 = sext i32 %tmp10 to i64		; <i64> [#uses=1]
-	%tmp12 = getelementptr [15 x i32]* %c, i64 0, i64 %tmp11		; <i32*> [#uses=1]
-	%tmp13 = load i32* %tmp12, align 4		; <i32> [#uses=1]
+	%tmp12 = getelementptr [15 x i32], [15 x i32]* %c, i64 0, i64 %tmp11		; <i32*> [#uses=1]
+	%tmp13 = load i32, i32* %tmp12, align 4		; <i32> [#uses=1]
 	%tmp14 = icmp eq i32 %tmp13, 0		; <i1> [#uses=1]
 	br i1 %tmp14, label %bb2.i.bb7.i.backedge_crit_edge, label %bb3.i
 
 bb3.i:		; preds = %bb2.i
-	%tmp15 = getelementptr [9 x i32]* %x1, i64 0, i64 1		; <i32*> [#uses=1]
+	%tmp15 = getelementptr [9 x i32], [9 x i32]* %x1, i64 0, i64 1		; <i32*> [#uses=1]
 	store i32 %tmp, i32* %tmp15, align 4
 	%tmp16 = sext i32 %tmp to i64		; <i64> [#uses=1]
-	%tmp17 = getelementptr [9 x i32]* %a, i64 0, i64 %tmp16		; <i32*> [#uses=1]
+	%tmp17 = getelementptr [9 x i32], [9 x i32]* %a, i64 0, i64 %tmp16		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp17, align 4
 	%tmp18 = add i32 %j.0.i, 2		; <i32> [#uses=1]
 	%tmp19 = sext i32 %tmp18 to i64		; <i64> [#uses=1]
-	%tmp20 = getelementptr [17 x i32]* %b, i64 0, i64 %tmp19		; <i32*> [#uses=1]
+	%tmp20 = getelementptr [17 x i32], [17 x i32]* %b, i64 0, i64 %tmp19		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp20, align 4
 	%tmp21 = sub i32 7, %j.0.i		; <i32> [#uses=1]
 	%tmp22 = sext i32 %tmp21 to i64		; <i64> [#uses=1]
-	%tmp23 = getelementptr [15 x i32]* %c, i64 0, i64 %tmp22		; <i32*> [#uses=1]
+	%tmp23 = getelementptr [15 x i32], [15 x i32]* %c, i64 0, i64 %tmp22		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp23, align 4
 	call void @Try(i32 2, i32* %q, i32* %b9, i32* %a10, i32* %c11, i32* %x1.sub) nounwind
-	%tmp24 = load i32* %q, align 4		; <i32> [#uses=1]
+	%tmp24 = load i32, i32* %q, align 4		; <i32> [#uses=1]
 	%tmp25 = icmp eq i32 %tmp24, 0		; <i1> [#uses=1]
 	br i1 %tmp25, label %bb5.i, label %bb3.i.bb7.i.backedge_crit_edge
 
 bb5.i:		; preds = %bb3.i
 	%tmp26 = sext i32 %tmp to i64		; <i64> [#uses=1]
-	%tmp27 = getelementptr [9 x i32]* %a, i64 0, i64 %tmp26		; <i32*> [#uses=1]
+	%tmp27 = getelementptr [9 x i32], [9 x i32]* %a, i64 0, i64 %tmp26		; <i32*> [#uses=1]
 	store i32 1, i32* %tmp27, align 4
 	%tmp28 = add i32 %j.0.i, 2		; <i32> [#uses=1]
 	%tmp29 = sext i32 %tmp28 to i64		; <i64> [#uses=1]
-	%tmp30 = getelementptr [17 x i32]* %b, i64 0, i64 %tmp29		; <i32*> [#uses=1]
+	%tmp30 = getelementptr [17 x i32], [17 x i32]* %b, i64 0, i64 %tmp29		; <i32*> [#uses=1]
 	store i32 1, i32* %tmp30, align 4
 	%tmp31 = sub i32 7, %j.0.i		; <i32> [#uses=1]
 	%tmp32 = sext i32 %tmp31 to i64		; <i64> [#uses=1]
-	%tmp33 = getelementptr [15 x i32]* %c, i64 0, i64 %tmp32		; <i32*> [#uses=1]
+	%tmp33 = getelementptr [15 x i32], [15 x i32]* %c, i64 0, i64 %tmp32		; <i32*> [#uses=1]
 	store i32 1, i32* %tmp33, align 4
 	br label %bb7.i.backedge
 
@@ -131,7 +131,7 @@ bb7.i.backedge:		; preds = %bb3.i.bb7.i.backedge_crit_edge, %bb2.i.bb7.i.backedg
 
 bb7.i:		; preds = %bb7.i.backedge, %newFuncRoot
 	%j.0.i = phi i32 [ 0, %newFuncRoot ], [ %tmp, %bb7.i.backedge ]		; <i32> [#uses=8]
-	%tmp34 = load i32* %q, align 4		; <i32> [#uses=1]
+	%tmp34 = load i32, i32* %q, align 4		; <i32> [#uses=1]
 	%tmp35 = icmp eq i32 %tmp34, 0		; <i1> [#uses=1]
 	%tmp36 = icmp ne i32 %j.0.i, 8		; <i1> [#uses=1]
 	%tmp37 = and i1 %tmp35, %tmp36		; <i1> [#uses=1]
diff --git a/test/Analysis/ScalarEvolution/zext-signed-addrec.ll b/test/Analysis/ScalarEvolution/zext-signed-addrec.ll
index 27aed3b0da1b..2b12b33158fb 100644
--- a/test/Analysis/ScalarEvolution/zext-signed-addrec.ll
+++ b/test/Analysis/ScalarEvolution/zext-signed-addrec.ll
@@ -15,16 +15,16 @@ target triple = "x86_64-unknown-linux-gnu"
 ; CHECK-LABEL: foo
 define i32 @foo() {
 entry:
-  %.pr = load i32* @b, align 4
+  %.pr = load i32, i32* @b, align 4
   %cmp10 = icmp slt i32 %.pr, 1
   br i1 %cmp10, label %for.cond1.preheader.lr.ph, label %entry.for.end9_crit_edge
 
 entry.for.end9_crit_edge:                         ; preds = %entry
-  %.pre = load i32* @c, align 4
+  %.pre = load i32, i32* @c, align 4
   br label %for.end9
 
 for.cond1.preheader.lr.ph:                        ; preds = %entry
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %for.cond1.preheader.for.cond1.preheader.split_crit_edge, label %return.loopexit.split
 
@@ -43,7 +43,7 @@ if.end:                                           ; preds = %if.end, %for.cond1.
   %shl = and i32 %conv7, 510
   store i32 %shl, i32* @c, align 4
 
-; CHECK: %lsr.iv.next = add i32 %lsr.iv, -258
+; CHECK: %lsr.iv.next = add nsw i32 %lsr.iv, -258
   %dec = add i8 %2, -1
 
   %cmp2 = icmp sgt i8 %dec, -1
@@ -63,7 +63,7 @@ for.cond.for.end9_crit_edge:                      ; preds = %for.inc8
 
 for.end9:                                         ; preds = %entry.for.end9_crit_edge, %for.cond.for.end9_crit_edge
   %3 = phi i32 [ %.pre, %entry.for.end9_crit_edge ], [ %shl, %for.cond.for.end9_crit_edge ]
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32 %3) #2
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %3) #2
   br label %return
 
 return.loopexit.split:                            ; preds = %for.cond1.preheader.lr.ph
diff --git a/test/Analysis/ScalarEvolution/zext-wrap.ll b/test/Analysis/ScalarEvolution/zext-wrap.ll
index 104ed41010af..f56e4556c697 100644
--- a/test/Analysis/ScalarEvolution/zext-wrap.ll
+++ b/test/Analysis/ScalarEvolution/zext-wrap.ll
@@ -10,7 +10,7 @@ bb.i:           ; preds = %bb1.i, %bb.nph
 
 ; This cast shouldn't be folded into the addrec.
 ; CHECK: %tmp = zext i8 %l_95.0.i1 to i16
-; CHECK: -->  (zext i8 {0,+,-1}<%bb.i> to i16)    Exits: 2
+; CHECK: -->  (zext i8 {0,+,-1}<%bb.i> to i16){{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: 2
 
         %tmp = zext i8 %l_95.0.i1 to i16
 
diff --git a/test/Analysis/ScopedNoAliasAA/basic-domains.ll b/test/Analysis/ScopedNoAliasAA/basic-domains.ll
index 7633a6dfcb4c..2fea2ba068a1 100644
--- a/test/Analysis/ScopedNoAliasAA/basic-domains.ll
+++ b/test/Analysis/ScopedNoAliasAA/basic-domains.ll
@@ -5,52 +5,50 @@ target triple = "x86_64-unknown-linux-gnu"
 define void @foo1(float* nocapture %a, float* nocapture readonly %c) #0 {
 entry:
 ; CHECK-LABEL: Function: foo1
-  %0 = load float* %c, align 4, !alias.scope !9
-  %arrayidx.i = getelementptr inbounds float* %a, i64 5
+  %0 = load float, float* %c, align 4, !alias.scope !0
+  %arrayidx.i = getelementptr inbounds float, float* %a, i64 5
   store float %0, float* %arrayidx.i, align 4, !noalias !6
 
-  %1 = load float* %c, align 4, !alias.scope !5
-  %arrayidx.i2 = getelementptr inbounds float* %a, i64 15
+  %1 = load float, float* %c, align 4, !alias.scope !7
+  %arrayidx.i2 = getelementptr inbounds float, float* %a, i64 15
   store float %1, float* %arrayidx.i2, align 4, !noalias !6
 
-  %2 = load float* %c, align 4, !alias.scope !6
-  %arrayidx.i3 = getelementptr inbounds float* %a, i64 16
-  store float %2, float* %arrayidx.i3, align 4, !noalias !5
+  %2 = load float, float* %c, align 4, !alias.scope !6
+  %arrayidx.i3 = getelementptr inbounds float, float* %a, i64 16
+  store float %2, float* %arrayidx.i3, align 4, !noalias !7
 
   ret void
 }
 
 attributes #0 = { nounwind uwtable }
 
-!0 = !{!0, !"some domain"}
-!1 = !{!1, !"some other domain"}
+!2 = !{!2, !"some domain"}
+!5 = !{!5, !"some other domain"}
 
 ; Two scopes (which must be self-referential to avoid being "uniqued"):
-!2 = !{!2, !0, !"a scope in dom0"}
-!3 = !{!2}
+!1 = !{!1, !2, !"a scope in dom0"}
 
-!4 = !{!4, !0, !"another scope in dom0"}
-!5 = !{!4}
+!3 = !{!3, !2, !"another scope in dom0"}
+!7 = !{!3}
 
 ; A list of the two scopes.
-!6 = !{!2, !4}
+!6 = !{!1, !3}
 
 ; Another scope in the second domain
-!7 = !{!7, !1, !"another scope in dom1"}
-!8 = !{!7}
+!4 = !{!4, !5, !"another scope in dom1"}
 
 ; A list of scopes from both domains.
-!9 = !{!2, !4, !7}
-
-; CHECK: NoAlias:   %0 = load float* %c, align 4, !alias.scope !0 <->   store float %0, float* %arrayidx.i, align 4, !noalias !6
-; CHECK: NoAlias:   %0 = load float* %c, align 4, !alias.scope !0 <->   store float %1, float* %arrayidx.i2, align 4, !noalias !6
-; CHECK: MayAlias:   %0 = load float* %c, align 4, !alias.scope !0 <->   store float %2, float* %arrayidx.i3, align 4, !noalias !7
-; CHECK: NoAlias:   %1 = load float* %c, align 4, !alias.scope !7 <->   store float %0, float* %arrayidx.i, align 4, !noalias !6
-; CHECK: NoAlias:   %1 = load float* %c, align 4, !alias.scope !7 <->   store float %1, float* %arrayidx.i2, align 4, !noalias !6
-; CHECK: NoAlias:   %1 = load float* %c, align 4, !alias.scope !7 <->   store float %2, float* %arrayidx.i3, align 4, !noalias !7
-; CHECK: NoAlias:   %2 = load float* %c, align 4, !alias.scope !6 <->   store float %0, float* %arrayidx.i, align 4, !noalias !6
-; CHECK: NoAlias:   %2 = load float* %c, align 4, !alias.scope !6 <->   store float %1, float* %arrayidx.i2, align 4, !noalias !6
-; CHECK: MayAlias:   %2 = load float* %c, align 4, !alias.scope !6 <->   store float %2, float* %arrayidx.i3, align 4, !noalias !7
+!0 = !{!1, !3, !4}
+
+; CHECK: NoAlias:   %0 = load float, float* %c, align 4, !alias.scope !0 <->   store float %0, float* %arrayidx.i, align 4, !noalias !6
+; CHECK: NoAlias:   %0 = load float, float* %c, align 4, !alias.scope !0 <->   store float %1, float* %arrayidx.i2, align 4, !noalias !6
+; CHECK: MayAlias:   %0 = load float, float* %c, align 4, !alias.scope !0 <->   store float %2, float* %arrayidx.i3, align 4, !noalias !7
+; CHECK: NoAlias:   %1 = load float, float* %c, align 4, !alias.scope !7 <->   store float %0, float* %arrayidx.i, align 4, !noalias !6
+; CHECK: NoAlias:   %1 = load float, float* %c, align 4, !alias.scope !7 <->   store float %1, float* %arrayidx.i2, align 4, !noalias !6
+; CHECK: NoAlias:   %1 = load float, float* %c, align 4, !alias.scope !7 <->   store float %2, float* %arrayidx.i3, align 4, !noalias !7
+; CHECK: NoAlias:   %2 = load float, float* %c, align 4, !alias.scope !6 <->   store float %0, float* %arrayidx.i, align 4, !noalias !6
+; CHECK: NoAlias:   %2 = load float, float* %c, align 4, !alias.scope !6 <->   store float %1, float* %arrayidx.i2, align 4, !noalias !6
+; CHECK: MayAlias:   %2 = load float, float* %c, align 4, !alias.scope !6 <->   store float %2, float* %arrayidx.i3, align 4, !noalias !7
 ; CHECK: NoAlias:   store float %1, float* %arrayidx.i2, align 4, !noalias !6 <->   store float %0, float* %arrayidx.i, align 4, !noalias !6
 ; CHECK: NoAlias:   store float %2, float* %arrayidx.i3, align 4, !noalias !7 <->   store float %0, float* %arrayidx.i, align 4, !noalias !6
 ; CHECK: NoAlias:   store float %2, float* %arrayidx.i3, align 4, !noalias !7 <->   store float %1, float* %arrayidx.i2, align 4, !noalias !6
diff --git a/test/Analysis/ScopedNoAliasAA/basic.ll b/test/Analysis/ScopedNoAliasAA/basic.ll
index bb232b5b6cb6..26258341cc14 100644
--- a/test/Analysis/ScopedNoAliasAA/basic.ll
+++ b/test/Analysis/ScopedNoAliasAA/basic.ll
@@ -5,18 +5,18 @@ target triple = "x86_64-unknown-linux-gnu"
 define void @foo1(float* nocapture %a, float* nocapture readonly %c) #0 {
 entry:
 ; CHECK-LABEL: Function: foo1
-  %0 = load float* %c, align 4, !alias.scope !1
-  %arrayidx.i = getelementptr inbounds float* %a, i64 5
+  %0 = load float, float* %c, align 4, !alias.scope !1
+  %arrayidx.i = getelementptr inbounds float, float* %a, i64 5
   store float %0, float* %arrayidx.i, align 4, !noalias !1
-  %1 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 7
+  %1 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 7
   store float %1, float* %arrayidx, align 4
   ret void
 
-; CHECK: NoAlias:   %0 = load float* %c, align 4, !alias.scope !0 <->   store float %0, float* %arrayidx.i, align 4, !noalias !0
-; CHECK: MayAlias:   %0 = load float* %c, align 4, !alias.scope !0 <->   store float %1, float* %arrayidx, align 4
-; CHECK: MayAlias:   %1 = load float* %c, align 4 <->   store float %0, float* %arrayidx.i, align 4, !noalias !0
-; CHECK: MayAlias:   %1 = load float* %c, align 4 <->   store float %1, float* %arrayidx, align 4
+; CHECK: NoAlias:   %0 = load float, float* %c, align 4, !alias.scope !0 <->   store float %0, float* %arrayidx.i, align 4, !noalias !0
+; CHECK: MayAlias:   %0 = load float, float* %c, align 4, !alias.scope !0 <->   store float %1, float* %arrayidx, align 4
+; CHECK: MayAlias:   %1 = load float, float* %c, align 4 <->   store float %0, float* %arrayidx.i, align 4, !noalias !0
+; CHECK: MayAlias:   %1 = load float, float* %c, align 4 <->   store float %1, float* %arrayidx, align 4
 ; CHECK: NoAlias:   store float %1, float* %arrayidx, align 4 <->   store float %0, float* %arrayidx.i, align 4, !noalias !0
 }
 
diff --git a/test/Analysis/ScopedNoAliasAA/basic2.ll b/test/Analysis/ScopedNoAliasAA/basic2.ll
index a154b13d98bf..a8a17e5f90bf 100644
--- a/test/Analysis/ScopedNoAliasAA/basic2.ll
+++ b/test/Analysis/ScopedNoAliasAA/basic2.ll
@@ -5,24 +5,24 @@ target triple = "x86_64-unknown-linux-gnu"
 define void @foo2(float* nocapture %a, float* nocapture %b, float* nocapture readonly %c) #0 {
 entry:
 ; CHECK-LABEL: Function: foo2
-  %0 = load float* %c, align 4, !alias.scope !0
-  %arrayidx.i = getelementptr inbounds float* %a, i64 5
+  %0 = load float, float* %c, align 4, !alias.scope !0
+  %arrayidx.i = getelementptr inbounds float, float* %a, i64 5
   store float %0, float* %arrayidx.i, align 4, !alias.scope !5, !noalias !4
-  %arrayidx1.i = getelementptr inbounds float* %b, i64 8
+  %arrayidx1.i = getelementptr inbounds float, float* %b, i64 8
   store float %0, float* %arrayidx1.i, align 4, !alias.scope !0, !noalias !5
-  %1 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 7
+  %1 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 7
   store float %1, float* %arrayidx, align 4
   ret void
 
-; CHECK: MayAlias:   %0 = load float* %c, align 4, !alias.scope !0 <->   store float %0, float* %arrayidx.i, align 4, !alias.scope !4, !noalia
+; CHECK: MayAlias:   %0 = load float, float* %c, align 4, !alias.scope !0 <->   store float %0, float* %arrayidx.i, align 4, !alias.scope !4, !noalia
 ; CHECK: s !5
-; CHECK: MayAlias:   %0 = load float* %c, align 4, !alias.scope !0 <->   store float %0, float* %arrayidx1.i, align 4, !alias.scope !0, !noali
+; CHECK: MayAlias:   %0 = load float, float* %c, align 4, !alias.scope !0 <->   store float %0, float* %arrayidx1.i, align 4, !alias.scope !0, !noali
 ; CHECK: as !4
-; CHECK: MayAlias:   %0 = load float* %c, align 4, !alias.scope !0 <->   store float %1, float* %arrayidx, align 4
-; CHECK: MayAlias:   %1 = load float* %c, align 4 <->   store float %0, float* %arrayidx.i, align 4, !alias.scope !4, !noalias !5
-; CHECK: MayAlias:   %1 = load float* %c, align 4 <->   store float %0, float* %arrayidx1.i, align 4, !alias.scope !0, !noalias !4
-; CHECK: MayAlias:   %1 = load float* %c, align 4 <->   store float %1, float* %arrayidx, align 4
+; CHECK: MayAlias:   %0 = load float, float* %c, align 4, !alias.scope !0 <->   store float %1, float* %arrayidx, align 4
+; CHECK: MayAlias:   %1 = load float, float* %c, align 4 <->   store float %0, float* %arrayidx.i, align 4, !alias.scope !4, !noalias !5
+; CHECK: MayAlias:   %1 = load float, float* %c, align 4 <->   store float %0, float* %arrayidx1.i, align 4, !alias.scope !0, !noalias !4
+; CHECK: MayAlias:   %1 = load float, float* %c, align 4 <->   store float %1, float* %arrayidx, align 4
 ; CHECK: NoAlias:   store float %0, float* %arrayidx1.i, align 4, !alias.scope !0, !noalias !4 <->   store float %0, float* %arrayidx.i, align
 ; CHECK: 4, !alias.scope !4, !noalias !5
 ; CHECK: NoAlias:   store float %1, float* %arrayidx, align 4 <->   store float %0, float* %arrayidx.i, align 4, !alias.scope !4, !noalias !5
diff --git a/test/Analysis/TypeBasedAliasAnalysis/PR17620.ll b/test/Analysis/TypeBasedAliasAnalysis/PR17620.ll
index 920d6f56d957..e78529c07f5a 100644
--- a/test/Analysis/TypeBasedAliasAnalysis/PR17620.ll
+++ b/test/Analysis/TypeBasedAliasAnalysis/PR17620.ll
@@ -16,11 +16,11 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 define %structA** @test(%classA* %this, i32** %p1) #0 align 2 {
 entry:
 ; CHECK-LABEL: @test
-; CHECK: load i32** %p1, align 8, !tbaa
-; CHECK: load i32** getelementptr (%classC* null, i32 0, i32 1, i32 0, i32 0), align 8, !tbaa
+; CHECK: load i32*, i32** %p1, align 8, !tbaa
+; CHECK: load i32*, i32** getelementptr (%classC, %classC* null, i32 0, i32 1, i32 0, i32 0), align 8, !tbaa
 ; CHECK: call void @callee
-  %0 = load i32** %p1, align 8, !tbaa !1
-  %1 = load i32** getelementptr (%classC* null, i32 0, i32 1, i32 0, i32 0), align 8, !tbaa !5
+  %0 = load i32*, i32** %p1, align 8, !tbaa !1
+  %1 = load i32*, i32** getelementptr (%classC, %classC* null, i32 0, i32 1, i32 0, i32 0), align 8, !tbaa !5
   call void @callee(i32* %0, i32* %1)
   unreachable
 }
diff --git a/test/Analysis/TypeBasedAliasAnalysis/aliastest.ll b/test/Analysis/TypeBasedAliasAnalysis/aliastest.ll
index 10da13a8d460..93c34f9503ce 100644
--- a/test/Analysis/TypeBasedAliasAnalysis/aliastest.ll
+++ b/test/Analysis/TypeBasedAliasAnalysis/aliastest.ll
@@ -5,9 +5,9 @@
 ; CHECK: @test0_yes
 ; CHECK: add i8 %x, %x
 define i8 @test0_yes(i8* %a, i8* %b) nounwind {
-  %x = load i8* %a, !tbaa !1
+  %x = load i8, i8* %a, !tbaa !1
   store i8 0, i8* %b, !tbaa !2
-  %y = load i8* %a, !tbaa !1
+  %y = load i8, i8* %a, !tbaa !1
   %z = add i8 %x, %y
   ret i8 %z
 }
@@ -15,9 +15,9 @@ define i8 @test0_yes(i8* %a, i8* %b) nounwind {
 ; CHECK: @test0_no
 ; CHECK: add i8 %x, %y
 define i8 @test0_no(i8* %a, i8* %b) nounwind {
-  %x = load i8* %a, !tbaa !3
+  %x = load i8, i8* %a, !tbaa !3
   store i8 0, i8* %b, !tbaa !4
-  %y = load i8* %a, !tbaa !3
+  %y = load i8, i8* %a, !tbaa !3
   %z = add i8 %x, %y
   ret i8 %z
 }
@@ -27,9 +27,9 @@ define i8 @test0_no(i8* %a, i8* %b) nounwind {
 ; CHECK: @test1_yes
 ; CHECK: add i8 %x, %x
 define i8 @test1_yes(i8* %a, i8* %b) nounwind {
-  %x = load i8* %a, !tbaa !5
+  %x = load i8, i8* %a, !tbaa !5
   store i8 0, i8* %b
-  %y = load i8* %a, !tbaa !5
+  %y = load i8, i8* %a, !tbaa !5
   %z = add i8 %x, %y
   ret i8 %z
 }
@@ -37,9 +37,9 @@ define i8 @test1_yes(i8* %a, i8* %b) nounwind {
 ; CHECK: @test1_no
 ; CHECK: add i8 %x, %y
 define i8 @test1_no(i8* %a, i8* %b) nounwind {
-  %x = load i8* %a, !tbaa !6
+  %x = load i8, i8* %a, !tbaa !6
   store i8 0, i8* %b
-  %y = load i8* %a, !tbaa !6
+  %y = load i8, i8* %a, !tbaa !6
   %z = add i8 %x, %y
   ret i8 %z
 }
diff --git a/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll b/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll
index 31f775e04665..a7987f7d7f06 100644
--- a/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll
+++ b/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll
@@ -6,8 +6,8 @@ target datalayout = "E-p:64:64:64"
 ; CHECK-NOT: alloca
 define internal i32 @test(i32* %X, i32* %Y, i32* %Q) {
   store i32 77, i32* %Q, !tbaa !2
-  %A = load i32* %X, !tbaa !1
-  %B = load i32* %Y, !tbaa !1
+  %A = load i32, i32* %X, !tbaa !1
+  %B = load i32, i32* %Y, !tbaa !1
   %C = add i32 %A, %B
   ret i32 %C
 }
diff --git a/test/Analysis/TypeBasedAliasAnalysis/cyclic.ll b/test/Analysis/TypeBasedAliasAnalysis/cyclic.ll
new file mode 100644
index 000000000000..a88e26c5cd52
--- /dev/null
+++ b/test/Analysis/TypeBasedAliasAnalysis/cyclic.ll
@@ -0,0 +1,26 @@
+; RUN: not opt -instcombine < %s 2>&1 | FileCheck %s
+; CHECK: Cycle found in TBAA metadata.
+
+define void @test6(i32* %gi) #0 {
+entry:
+  store i32 42, i32* %gi, align 4, !tbaa !0
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.body, %entry
+  br i1 undef, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  store i32 undef, i32* %gi, align 4, !tbaa !2
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  ret void
+}
+
+attributes #0 = { nounwind ssp uwtable }
+
+!0 = !{!1, !1, i64 0}
+!1 = !{!"Simple C/C++ TBAA"}
+!2 = distinct !{!3, !2, i64 0}
+!3 = !{!"int", !4}
+!4 = !{!"omnipotent ", !1}
diff --git a/test/Analysis/TypeBasedAliasAnalysis/dse.ll b/test/Analysis/TypeBasedAliasAnalysis/dse.ll
index 09f8feb610a9..b6dc9b298eb0 100644
--- a/test/Analysis/TypeBasedAliasAnalysis/dse.ll
+++ b/test/Analysis/TypeBasedAliasAnalysis/dse.ll
@@ -4,47 +4,47 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 ; DSE should make use of TBAA.
 
 ; CHECK: @test0_yes
-; CHECK-NEXT: load i8* %b
+; CHECK-NEXT: load i8, i8* %b
 ; CHECK-NEXT: store i8 1, i8* %a
 ; CHECK-NEXT: ret i8 %y
 define i8 @test0_yes(i8* %a, i8* %b) nounwind {
   store i8 0, i8* %a, !tbaa !1
-  %y = load i8* %b, !tbaa !2
+  %y = load i8, i8* %b, !tbaa !2
   store i8 1, i8* %a, !tbaa !1
   ret i8 %y
 }
 
 ; CHECK: @test0_no
 ; CHECK-NEXT: store i8 0, i8* %a
-; CHECK-NEXT: load i8* %b
+; CHECK-NEXT: load i8, i8* %b
 ; CHECK-NEXT: store i8 1, i8* %a
 ; CHECK-NEXT: ret i8 %y
 define i8 @test0_no(i8* %a, i8* %b) nounwind {
   store i8 0, i8* %a, !tbaa !3
-  %y = load i8* %b, !tbaa !4
+  %y = load i8, i8* %b, !tbaa !4
   store i8 1, i8* %a, !tbaa !3
   ret i8 %y
 }
 
 ; CHECK: @test1_yes
-; CHECK-NEXT: load i8* %b
+; CHECK-NEXT: load i8, i8* %b
 ; CHECK-NEXT: store i8 1, i8* %a
 ; CHECK-NEXT: ret i8 %y
 define i8 @test1_yes(i8* %a, i8* %b) nounwind {
   store i8 0, i8* %a
-  %y = load i8* %b, !tbaa !5
+  %y = load i8, i8* %b, !tbaa !5
   store i8 1, i8* %a
   ret i8 %y
 }
 
 ; CHECK: @test1_no
 ; CHECK-NEXT: store i8 0, i8* %a
-; CHECK-NEXT: load i8* %b
+; CHECK-NEXT: load i8, i8* %b
 ; CHECK-NEXT: store i8 1, i8* %a
 ; CHECK-NEXT: ret i8 %y
 define i8 @test1_no(i8* %a, i8* %b) nounwind {
   store i8 0, i8* %a
-  %y = load i8* %b, !tbaa !6
+  %y = load i8, i8* %b, !tbaa !6
   store i8 1, i8* %a
   ret i8 %y
 }
diff --git a/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll b/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll
index 732f5d7cfcbb..afc83c9f4f57 100644
--- a/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll
+++ b/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll
@@ -12,8 +12,8 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; CHECK: define void @vrlh(
 
 ; CHECK: for.end:
-; CHECK:   %arrayidx31 = getelementptr inbounds %union.vector_t* %t, i64 0, i32 0, i64 1
-; CHECK:   %tmp32 = load i64* %arrayidx31, align 8, !tbaa [[TAG:!.*]]
+; CHECK:   %arrayidx31 = getelementptr inbounds %union.vector_t, %union.vector_t* %t, i64 0, i32 0, i64 1
+; CHECK:   %tmp32 = load i64, i64* %arrayidx31, align 8, !tbaa [[TAG:!.*]]
 
 define void @vrlh(%union.vector_t* %va, %union.vector_t* %vb, %union.vector_t* %vd) nounwind {
 entry:
@@ -25,22 +25,22 @@ for.body:                                         ; preds = %entry, %for.body
   %sub = sub nsw i32 7, %i.01
   %idxprom = sext i32 %sub to i64
   %half = bitcast %union.vector_t* %vb to [8 x i16]*
-  %arrayidx = getelementptr inbounds [8 x i16]* %half, i64 0, i64 %idxprom
-  %tmp4 = load i16* %arrayidx, align 2, !tbaa !0
+  %arrayidx = getelementptr inbounds [8 x i16], [8 x i16]* %half, i64 0, i64 %idxprom
+  %tmp4 = load i16, i16* %arrayidx, align 2, !tbaa !0
   %conv = zext i16 %tmp4 to i32
   %and = and i32 %conv, 15
   %sub6 = sub nsw i32 7, %i.01
   %idxprom7 = sext i32 %sub6 to i64
   %half9 = bitcast %union.vector_t* %va to [8 x i16]*
-  %arrayidx10 = getelementptr inbounds [8 x i16]* %half9, i64 0, i64 %idxprom7
-  %tmp11 = load i16* %arrayidx10, align 2, !tbaa !0
+  %arrayidx10 = getelementptr inbounds [8 x i16], [8 x i16]* %half9, i64 0, i64 %idxprom7
+  %tmp11 = load i16, i16* %arrayidx10, align 2, !tbaa !0
   %conv12 = zext i16 %tmp11 to i32
   %shl = shl i32 %conv12, %and
   %sub15 = sub nsw i32 7, %i.01
   %idxprom16 = sext i32 %sub15 to i64
   %half18 = bitcast %union.vector_t* %va to [8 x i16]*
-  %arrayidx19 = getelementptr inbounds [8 x i16]* %half18, i64 0, i64 %idxprom16
-  %tmp20 = load i16* %arrayidx19, align 2, !tbaa !0
+  %arrayidx19 = getelementptr inbounds [8 x i16], [8 x i16]* %half18, i64 0, i64 %idxprom16
+  %tmp20 = load i16, i16* %arrayidx19, align 2, !tbaa !0
   %conv21 = zext i16 %tmp20 to i32
   %sub23 = sub nsw i32 16, %and
   %shr = lshr i32 %conv21, %sub23
@@ -49,20 +49,20 @@ for.body:                                         ; preds = %entry, %for.body
   %sub26 = sub nsw i32 7, %i.01
   %idxprom27 = sext i32 %sub26 to i64
   %half28 = bitcast %union.vector_t* %t to [8 x i16]*
-  %arrayidx29 = getelementptr inbounds [8 x i16]* %half28, i64 0, i64 %idxprom27
+  %arrayidx29 = getelementptr inbounds [8 x i16], [8 x i16]* %half28, i64 0, i64 %idxprom27
   store i16 %conv24, i16* %arrayidx29, align 2, !tbaa !0
   %inc = add nsw i32 %i.01, 1
   %cmp = icmp slt i32 %inc, 8
   br i1 %cmp, label %for.body, label %for.end
 
 for.end:                                          ; preds = %for.body
-  %arrayidx31 = getelementptr inbounds %union.vector_t* %t, i64 0, i32 0, i64 1
-  %tmp32 = load i64* %arrayidx31, align 8, !tbaa !3
-  %arrayidx35 = getelementptr inbounds %union.vector_t* %vd, i64 0, i32 0, i64 1
+  %arrayidx31 = getelementptr inbounds %union.vector_t, %union.vector_t* %t, i64 0, i32 0, i64 1
+  %tmp32 = load i64, i64* %arrayidx31, align 8, !tbaa !3
+  %arrayidx35 = getelementptr inbounds %union.vector_t, %union.vector_t* %vd, i64 0, i32 0, i64 1
   store i64 %tmp32, i64* %arrayidx35, align 8, !tbaa !3
-  %arrayidx37 = getelementptr inbounds %union.vector_t* %t, i64 0, i32 0, i64 0
-  %tmp38 = load i64* %arrayidx37, align 8, !tbaa !3
-  %arrayidx41 = getelementptr inbounds %union.vector_t* %vd, i64 0, i32 0, i64 0
+  %arrayidx37 = getelementptr inbounds %union.vector_t, %union.vector_t* %t, i64 0, i32 0, i64 0
+  %tmp38 = load i64, i64* %arrayidx37, align 8, !tbaa !3
+  %arrayidx41 = getelementptr inbounds %union.vector_t, %union.vector_t* %vd, i64 0, i32 0, i64 0
   store i64 %tmp38, i64* %arrayidx41, align 8, !tbaa !3
   ret void
 }
@@ -75,14 +75,14 @@ for.end:                                          ; preds = %for.body
 
 define i32 @test0(%struct.X* %a) nounwind {
 entry:
-  %i = getelementptr inbounds %struct.X* %a, i64 0, i32 0
+  %i = getelementptr inbounds %struct.X, %struct.X* %a, i64 0, i32 0
   store i32 0, i32* %i, align 4, !tbaa !4
   br label %for.body
 
 for.body:                                         ; preds = %entry, %for.body
   %i2.01 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
-  %f = getelementptr inbounds %struct.X* %a, i64 %i2.01, i32 1
-  %tmp6 = load float* %f, align 4, !tbaa !5
+  %f = getelementptr inbounds %struct.X, %struct.X* %a, i64 %i2.01, i32 1
+  %tmp6 = load float, float* %f, align 4, !tbaa !5
   %mul = fmul float %tmp6, 0x40019999A0000000
   store float %mul, float* %f, align 4, !tbaa !5
   %inc = add nsw i64 %i2.01, 1
@@ -90,8 +90,8 @@ for.body:                                         ; preds = %entry, %for.body
   br i1 %cmp, label %for.body, label %for.end
 
 for.end:                                          ; preds = %for.body
-  %i9 = getelementptr inbounds %struct.X* %a, i64 0, i32 0
-  %tmp10 = load i32* %i9, align 4, !tbaa !4
+  %i9 = getelementptr inbounds %struct.X, %struct.X* %a, i64 0, i32 0
+  %tmp10 = load i32, i32* %i9, align 4, !tbaa !4
   ret i32 %tmp10
 }
 
@@ -103,14 +103,14 @@ for.end:                                          ; preds = %for.body
 
 define float @test1(%struct.X* %a) nounwind {
 entry:
-  %f = getelementptr inbounds %struct.X* %a, i64 0, i32 1
+  %f = getelementptr inbounds %struct.X, %struct.X* %a, i64 0, i32 1
   store float 0x3FD3333340000000, float* %f, align 4, !tbaa !5
   br label %for.body
 
 for.body:                                         ; preds = %entry, %for.body
   %i.01 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
-  %i5 = getelementptr inbounds %struct.X* %a, i64 %i.01, i32 0
-  %tmp6 = load i32* %i5, align 4, !tbaa !4
+  %i5 = getelementptr inbounds %struct.X, %struct.X* %a, i64 %i.01, i32 0
+  %tmp6 = load i32, i32* %i5, align 4, !tbaa !4
   %mul = mul nsw i32 %tmp6, 3
   store i32 %mul, i32* %i5, align 4, !tbaa !4
   %inc = add nsw i64 %i.01, 1
@@ -118,8 +118,8 @@ for.body:                                         ; preds = %entry, %for.body
   br i1 %cmp, label %for.body, label %for.end
 
 for.end:                                          ; preds = %for.body
-  %f9 = getelementptr inbounds %struct.X* %a, i64 0, i32 1
-  %tmp10 = load float* %f9, align 4, !tbaa !5
+  %f9 = getelementptr inbounds %struct.X, %struct.X* %a, i64 0, i32 1
+  %tmp10 = load float, float* %f9, align 4, !tbaa !5
   ret float %tmp10
 }
 
diff --git a/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll b/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll
index edea6d02800d..aaa43a460900 100644
--- a/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll
+++ b/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll
@@ -17,7 +17,7 @@ entry:
   br i1 %c, label %if.else, label %if.then
 
 if.then:
-  %t = load i32* %p, !tbaa !1
+  %t = load i32, i32* %p, !tbaa !1
   store i32 %t, i32* %q
   ret void
 
@@ -32,11 +32,11 @@ if.else:
 
 ; CHECK: @watch_out_for_type_change
 ; CHECK: if.then:
-; CHECK:   %t = load i32* %p
+; CHECK:   %t = load i32, i32* %p
 ; CHECK:   store i32 %t, i32* %q
 ; CHECK:   ret void
 ; CHECK: if.else:
-; CHECK:   %u = load i32* %p
+; CHECK:   %u = load i32, i32* %p
 ; CHECK:   store i32 %u, i32* %q
 
 define void @watch_out_for_type_change(i1 %c, i32* %p, i32* %p1, i32* %q) nounwind {
@@ -46,12 +46,12 @@ entry:
   br i1 %c, label %if.else, label %if.then
 
 if.then:
-  %t = load i32* %p, !tbaa !3
+  %t = load i32, i32* %p, !tbaa !3
   store i32 %t, i32* %q
   ret void
 
 if.else:
-  %u = load i32* %p, !tbaa !4
+  %u = load i32, i32* %p, !tbaa !4
   store i32 %u, i32* %q
   ret void
 }
@@ -64,7 +64,7 @@ if.else:
 ; CHECK:   store i32 0, i32* %q
 ; CHECK:   ret void
 ; CHECK: if.else:
-; CHECK:   %u = load i32* %p
+; CHECK:   %u = load i32, i32* %p
 ; CHECK:   store i32 %u, i32* %q
 
 define void @watch_out_for_another_type_change(i1 %c, i32* %p, i32* %p1, i32* %q) nounwind {
@@ -74,12 +74,12 @@ entry:
   br i1 %c, label %if.else, label %if.then
 
 if.then:
-  %t = load i32* %p, !tbaa !4
+  %t = load i32, i32* %p, !tbaa !4
   store i32 %t, i32* %q
   ret void
 
 if.else:
-  %u = load i32* %p, !tbaa !3
+  %u = load i32, i32* %p, !tbaa !3
   store i32 %u, i32* %q
   ret void
 }
diff --git a/test/Analysis/TypeBasedAliasAnalysis/licm.ll b/test/Analysis/TypeBasedAliasAnalysis/licm.ll
index 0722a2ce86a8..fe07730577e6 100644
--- a/test/Analysis/TypeBasedAliasAnalysis/licm.ll
+++ b/test/Analysis/TypeBasedAliasAnalysis/licm.ll
@@ -5,7 +5,7 @@
 
 ; CHECK: @foo
 ; CHECK:      entry:
-; CHECK-NEXT:   %tmp3 = load double** @P, !tbaa !0
+; CHECK-NEXT:   %tmp3 = load double*, double** @P, !tbaa !0
 ; CHECK-NEXT:   br label %for.body
 
 @P = common global double* null
@@ -16,9 +16,9 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %i.07 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
-  %tmp3 = load double** @P, !tbaa !1
-  %scevgep = getelementptr double* %tmp3, i64 %i.07
-  %tmp4 = load double* %scevgep, !tbaa !2
+  %tmp3 = load double*, double** @P, !tbaa !1
+  %scevgep = getelementptr double, double* %tmp3, i64 %i.07
+  %tmp4 = load double, double* %scevgep, !tbaa !2
   %mul = fmul double %tmp4, 2.300000e+00
   store double %mul, double* %scevgep, !tbaa !2
   %inc = add i64 %i.07, 1
@@ -49,9 +49,9 @@ entry:
   br label %loop
 
 loop:
-  %tmp51 = load i8** %p, !tbaa !4
+  %tmp51 = load i8*, i8** %p, !tbaa !4
   store i8* %tmp51, i8** %p
-  %tmp40 = load i8* %q, !tbaa !5
+  %tmp40 = load i8, i8* %q, !tbaa !5
   store i8 %tmp40, i8* %q
   br label %loop
 }
diff --git a/test/Analysis/TypeBasedAliasAnalysis/placement-tbaa.ll b/test/Analysis/TypeBasedAliasAnalysis/placement-tbaa.ll
index fd05dbea7cba..aa91020f12d6 100644
--- a/test/Analysis/TypeBasedAliasAnalysis/placement-tbaa.ll
+++ b/test/Analysis/TypeBasedAliasAnalysis/placement-tbaa.ll
@@ -33,20 +33,20 @@ entry:
   %call = call noalias i8* @_Znwm(i64 8)
   %0 = bitcast i8* %call to %struct.Foo*
   store %struct.Foo* %0, %struct.Foo** %f, align 8, !tbaa !4
-  %1 = load %struct.Foo** %f, align 8, !tbaa !4
-  %i = getelementptr inbounds %struct.Foo* %1, i32 0, i32 0
+  %1 = load %struct.Foo*, %struct.Foo** %f, align 8, !tbaa !4
+  %i = getelementptr inbounds %struct.Foo, %struct.Foo* %1, i32 0, i32 0
   store i64 1, i64* %i, align 8, !tbaa !6
   store i32 0, i32* %i1, align 4, !tbaa !0
   br label %for.cond
 
 for.cond:
-  %2 = load i32* %i1, align 4, !tbaa !0
-  %3 = load i32* %n.addr, align 4, !tbaa !0
+  %2 = load i32, i32* %i1, align 4, !tbaa !0
+  %3 = load i32, i32* %n.addr, align 4, !tbaa !0
   %cmp = icmp slt i32 %2, %3
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:
-  %4 = load %struct.Foo** %f, align 8, !tbaa !4
+  %4 = load %struct.Foo*, %struct.Foo** %f, align 8, !tbaa !4
   %5 = bitcast %struct.Foo* %4 to i8*
   %new.isnull = icmp eq i8* %5, null
   br i1 %new.isnull, label %new.cont, label %new.notnull
@@ -58,10 +58,10 @@ new.notnull:
 new.cont:
   %7 = phi %struct.Bar* [ %6, %new.notnull ], [ null, %for.body ]
   store %struct.Bar* %7, %struct.Bar** %b, align 8, !tbaa !4
-  %8 = load %struct.Bar** %b, align 8, !tbaa !4
-  %p = getelementptr inbounds %struct.Bar* %8, i32 0, i32 0
+  %8 = load %struct.Bar*, %struct.Bar** %b, align 8, !tbaa !4
+  %p = getelementptr inbounds %struct.Bar, %struct.Bar* %8, i32 0, i32 0
   store i8* null, i8** %p, align 8, !tbaa !9
-  %9 = load %struct.Foo** %f, align 8, !tbaa !4
+  %9 = load %struct.Foo*, %struct.Foo** %f, align 8, !tbaa !4
   %10 = bitcast %struct.Foo* %9 to i8*
   %new.isnull2 = icmp eq i8* %10, null
   br i1 %new.isnull2, label %new.cont4, label %new.notnull3
@@ -73,23 +73,23 @@ new.notnull3:
 new.cont4:
   %12 = phi %struct.Foo* [ %11, %new.notnull3 ], [ null, %new.cont ]
   store %struct.Foo* %12, %struct.Foo** %f, align 8, !tbaa !4
-  %13 = load i32* %i1, align 4, !tbaa !0
+  %13 = load i32, i32* %i1, align 4, !tbaa !0
   %conv = sext i32 %13 to i64
-  %14 = load %struct.Foo** %f, align 8, !tbaa !4
-  %i5 = getelementptr inbounds %struct.Foo* %14, i32 0, i32 0
+  %14 = load %struct.Foo*, %struct.Foo** %f, align 8, !tbaa !4
+  %i5 = getelementptr inbounds %struct.Foo, %struct.Foo* %14, i32 0, i32 0
   store i64 %conv, i64* %i5, align 8, !tbaa !6
   br label %for.inc
 
 for.inc:
-  %15 = load i32* %i1, align 4, !tbaa !0
+  %15 = load i32, i32* %i1, align 4, !tbaa !0
   %inc = add nsw i32 %15, 1
   store i32 %inc, i32* %i1, align 4, !tbaa !0
   br label %for.cond
 
 for.end:
-  %16 = load %struct.Foo** %f, align 8, !tbaa !4
-  %i6 = getelementptr inbounds %struct.Foo* %16, i32 0, i32 0
-  %17 = load i64* %i6, align 8, !tbaa !6
+  %16 = load %struct.Foo*, %struct.Foo** %f, align 8, !tbaa !4
+  %i6 = getelementptr inbounds %struct.Foo, %struct.Foo* %16, i32 0, i32 0
+  %17 = load i64, i64* %i6, align 8, !tbaa !6
   ret i64 %17
 }
 
diff --git a/test/Analysis/TypeBasedAliasAnalysis/precedence.ll b/test/Analysis/TypeBasedAliasAnalysis/precedence.ll
index 0b697b2e8869..b2931cac75c8 100644
--- a/test/Analysis/TypeBasedAliasAnalysis/precedence.ll
+++ b/test/Analysis/TypeBasedAliasAnalysis/precedence.ll
@@ -18,7 +18,7 @@ entry:
   store i32 0, i32* %x, !tbaa !0
   %0 = bitcast i32* %x to float*
   store float 0x4002666660000000, float* %0, !tbaa !3
-  %tmp3 = load i32* %x, !tbaa !0
+  %tmp3 = load i32, i32* %x, !tbaa !0
   ret i32 %tmp3
 }
 
@@ -33,9 +33,9 @@ define i64 @offset(i64* %x) nounwind {
 entry:
   store i64 0, i64* %x, !tbaa !4
   %0 = bitcast i64* %x to i8*
-  %1 = getelementptr i8* %0, i64 1
+  %1 = getelementptr i8, i8* %0, i64 1
   store i8 1, i8* %1, !tbaa !5
-  %tmp3 = load i64* %x, !tbaa !4
+  %tmp3 = load i64, i64* %x, !tbaa !4
   ret i64 %tmp3
 }
 
diff --git a/test/Analysis/TypeBasedAliasAnalysis/sink.ll b/test/Analysis/TypeBasedAliasAnalysis/sink.ll
index 1a124b86083b..c95dc151ed31 100644
--- a/test/Analysis/TypeBasedAliasAnalysis/sink.ll
+++ b/test/Analysis/TypeBasedAliasAnalysis/sink.ll
@@ -1,11 +1,11 @@
 ; RUN: opt -tbaa -sink -S < %s | FileCheck %s
 
 ; CHECK: a:
-; CHECK:   %f = load float* %p, !tbaa [[TAGA:!.*]]
+; CHECK:   %f = load float, float* %p, !tbaa [[TAGA:!.*]]
 ; CHECK:   store float %f, float* %q
 
 define void @foo(float* %p, i1 %c, float* %q, float* %r) {
-  %f = load float* %p, !tbaa !0
+  %f = load float, float* %p, !tbaa !0
   store float 0.0, float* %r, !tbaa !1
   br i1 %c, label %a, label %b
 a:
diff --git a/test/Analysis/TypeBasedAliasAnalysis/tbaa-path.ll b/test/Analysis/TypeBasedAliasAnalysis/tbaa-path.ll
index 3c035af7c529..a2e4dc6ddcf0 100644
--- a/test/Analysis/TypeBasedAliasAnalysis/tbaa-path.ll
+++ b/test/Analysis/TypeBasedAliasAnalysis/tbaa-path.ll
@@ -17,7 +17,7 @@ entry:
 ; OPT: define
 ; OPT: store i32 1
 ; OPT: store i32 4
-; OPT: %[[RET:.*]] = load i32*
+; OPT: %[[RET:.*]] = load i32, i32*
 ; OPT: ret i32 %[[RET]]
   %s.addr = alloca i32*, align 8
   %A.addr = alloca %struct.StructA*, align 8
@@ -25,13 +25,13 @@ entry:
   store i32* %s, i32** %s.addr, align 8, !tbaa !0
   store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0
   store i64 %count, i64* %count.addr, align 8, !tbaa !4
-  %0 = load i32** %s.addr, align 8, !tbaa !0
+  %0 = load i32*, i32** %s.addr, align 8, !tbaa !0
   store i32 1, i32* %0, align 4, !tbaa !6
-  %1 = load %struct.StructA** %A.addr, align 8, !tbaa !0
-  %f32 = getelementptr inbounds %struct.StructA* %1, i32 0, i32 1
+  %1 = load %struct.StructA*, %struct.StructA** %A.addr, align 8, !tbaa !0
+  %f32 = getelementptr inbounds %struct.StructA, %struct.StructA* %1, i32 0, i32 1
   store i32 4, i32* %f32, align 4, !tbaa !8
-  %2 = load i32** %s.addr, align 8, !tbaa !0
-  %3 = load i32* %2, align 4, !tbaa !6
+  %2 = load i32*, i32** %s.addr, align 8, !tbaa !0
+  %3 = load i32, i32* %2, align 4, !tbaa !6
   ret i32 %3
 }
 
@@ -51,13 +51,13 @@ entry:
   store i32* %s, i32** %s.addr, align 8, !tbaa !0
   store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0
   store i64 %count, i64* %count.addr, align 8, !tbaa !4
-  %0 = load i32** %s.addr, align 8, !tbaa !0
+  %0 = load i32*, i32** %s.addr, align 8, !tbaa !0
   store i32 1, i32* %0, align 4, !tbaa !6
-  %1 = load %struct.StructA** %A.addr, align 8, !tbaa !0
-  %f16 = getelementptr inbounds %struct.StructA* %1, i32 0, i32 0
+  %1 = load %struct.StructA*, %struct.StructA** %A.addr, align 8, !tbaa !0
+  %f16 = getelementptr inbounds %struct.StructA, %struct.StructA* %1, i32 0, i32 0
   store i16 4, i16* %f16, align 2, !tbaa !11
-  %2 = load i32** %s.addr, align 8, !tbaa !0
-  %3 = load i32* %2, align 4, !tbaa !6
+  %2 = load i32*, i32** %s.addr, align 8, !tbaa !0
+  %3 = load i32, i32* %2, align 4, !tbaa !6
   ret i32 %3
 }
 
@@ -69,7 +69,7 @@ entry:
 ; OPT: define
 ; OPT: store i32 1
 ; OPT: store i32 4
-; OPT: %[[RET:.*]] = load i32*
+; OPT: %[[RET:.*]] = load i32, i32*
 ; OPT: ret i32 %[[RET]]
   %A.addr = alloca %struct.StructA*, align 8
   %B.addr = alloca %struct.StructB*, align 8
@@ -77,16 +77,16 @@ entry:
   store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0
   store %struct.StructB* %B, %struct.StructB** %B.addr, align 8, !tbaa !0
   store i64 %count, i64* %count.addr, align 8, !tbaa !4
-  %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0
-  %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1
+  %0 = load %struct.StructA*, %struct.StructA** %A.addr, align 8, !tbaa !0
+  %f32 = getelementptr inbounds %struct.StructA, %struct.StructA* %0, i32 0, i32 1
   store i32 1, i32* %f32, align 4, !tbaa !8
-  %1 = load %struct.StructB** %B.addr, align 8, !tbaa !0
-  %a = getelementptr inbounds %struct.StructB* %1, i32 0, i32 1
-  %f321 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 1
+  %1 = load %struct.StructB*, %struct.StructB** %B.addr, align 8, !tbaa !0
+  %a = getelementptr inbounds %struct.StructB, %struct.StructB* %1, i32 0, i32 1
+  %f321 = getelementptr inbounds %struct.StructA, %struct.StructA* %a, i32 0, i32 1
   store i32 4, i32* %f321, align 4, !tbaa !12
-  %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0
-  %f322 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1
-  %3 = load i32* %f322, align 4, !tbaa !8
+  %2 = load %struct.StructA*, %struct.StructA** %A.addr, align 8, !tbaa !0
+  %f322 = getelementptr inbounds %struct.StructA, %struct.StructA* %2, i32 0, i32 1
+  %3 = load i32, i32* %f322, align 4, !tbaa !8
   ret i32 %3
 }
 
@@ -106,16 +106,16 @@ entry:
   store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0
   store %struct.StructB* %B, %struct.StructB** %B.addr, align 8, !tbaa !0
   store i64 %count, i64* %count.addr, align 8, !tbaa !4
-  %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0
-  %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1
+  %0 = load %struct.StructA*, %struct.StructA** %A.addr, align 8, !tbaa !0
+  %f32 = getelementptr inbounds %struct.StructA, %struct.StructA* %0, i32 0, i32 1
   store i32 1, i32* %f32, align 4, !tbaa !8
-  %1 = load %struct.StructB** %B.addr, align 8, !tbaa !0
-  %a = getelementptr inbounds %struct.StructB* %1, i32 0, i32 1
-  %f16 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 0
+  %1 = load %struct.StructB*, %struct.StructB** %B.addr, align 8, !tbaa !0
+  %a = getelementptr inbounds %struct.StructB, %struct.StructB* %1, i32 0, i32 1
+  %f16 = getelementptr inbounds %struct.StructA, %struct.StructA* %a, i32 0, i32 0
   store i16 4, i16* %f16, align 2, !tbaa !14
-  %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0
-  %f321 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1
-  %3 = load i32* %f321, align 4, !tbaa !8
+  %2 = load %struct.StructA*, %struct.StructA** %A.addr, align 8, !tbaa !0
+  %f321 = getelementptr inbounds %struct.StructA, %struct.StructA* %2, i32 0, i32 1
+  %3 = load i32, i32* %f321, align 4, !tbaa !8
   ret i32 %3
 }
 
@@ -135,15 +135,15 @@ entry:
   store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0
   store %struct.StructB* %B, %struct.StructB** %B.addr, align 8, !tbaa !0
   store i64 %count, i64* %count.addr, align 8, !tbaa !4
-  %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0
-  %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1
+  %0 = load %struct.StructA*, %struct.StructA** %A.addr, align 8, !tbaa !0
+  %f32 = getelementptr inbounds %struct.StructA, %struct.StructA* %0, i32 0, i32 1
   store i32 1, i32* %f32, align 4, !tbaa !8
-  %1 = load %struct.StructB** %B.addr, align 8, !tbaa !0
-  %f321 = getelementptr inbounds %struct.StructB* %1, i32 0, i32 2
+  %1 = load %struct.StructB*, %struct.StructB** %B.addr, align 8, !tbaa !0
+  %f321 = getelementptr inbounds %struct.StructB, %struct.StructB* %1, i32 0, i32 2
   store i32 4, i32* %f321, align 4, !tbaa !15
-  %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0
-  %f322 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1
-  %3 = load i32* %f322, align 4, !tbaa !8
+  %2 = load %struct.StructA*, %struct.StructA** %A.addr, align 8, !tbaa !0
+  %f322 = getelementptr inbounds %struct.StructA, %struct.StructA* %2, i32 0, i32 1
+  %3 = load i32, i32* %f322, align 4, !tbaa !8
   ret i32 %3
 }
 
@@ -163,16 +163,16 @@ entry:
   store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0
   store %struct.StructB* %B, %struct.StructB** %B.addr, align 8, !tbaa !0
   store i64 %count, i64* %count.addr, align 8, !tbaa !4
-  %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0
-  %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1
+  %0 = load %struct.StructA*, %struct.StructA** %A.addr, align 8, !tbaa !0
+  %f32 = getelementptr inbounds %struct.StructA, %struct.StructA* %0, i32 0, i32 1
   store i32 1, i32* %f32, align 4, !tbaa !8
-  %1 = load %struct.StructB** %B.addr, align 8, !tbaa !0
-  %a = getelementptr inbounds %struct.StructB* %1, i32 0, i32 1
-  %f32_2 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 3
+  %1 = load %struct.StructB*, %struct.StructB** %B.addr, align 8, !tbaa !0
+  %a = getelementptr inbounds %struct.StructB, %struct.StructB* %1, i32 0, i32 1
+  %f32_2 = getelementptr inbounds %struct.StructA, %struct.StructA* %a, i32 0, i32 3
   store i32 4, i32* %f32_2, align 4, !tbaa !16
-  %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0
-  %f321 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1
-  %3 = load i32* %f321, align 4, !tbaa !8
+  %2 = load %struct.StructA*, %struct.StructA** %A.addr, align 8, !tbaa !0
+  %f321 = getelementptr inbounds %struct.StructA, %struct.StructA* %2, i32 0, i32 1
+  %3 = load i32, i32* %f321, align 4, !tbaa !8
   ret i32 %3
 }
 
@@ -192,15 +192,15 @@ entry:
   store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0
   store %struct.StructS* %S, %struct.StructS** %S.addr, align 8, !tbaa !0
   store i64 %count, i64* %count.addr, align 8, !tbaa !4
-  %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0
-  %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1
+  %0 = load %struct.StructA*, %struct.StructA** %A.addr, align 8, !tbaa !0
+  %f32 = getelementptr inbounds %struct.StructA, %struct.StructA* %0, i32 0, i32 1
   store i32 1, i32* %f32, align 4, !tbaa !8
-  %1 = load %struct.StructS** %S.addr, align 8, !tbaa !0
-  %f321 = getelementptr inbounds %struct.StructS* %1, i32 0, i32 1
+  %1 = load %struct.StructS*, %struct.StructS** %S.addr, align 8, !tbaa !0
+  %f321 = getelementptr inbounds %struct.StructS, %struct.StructS* %1, i32 0, i32 1
   store i32 4, i32* %f321, align 4, !tbaa !17
-  %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0
-  %f322 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1
-  %3 = load i32* %f322, align 4, !tbaa !8
+  %2 = load %struct.StructA*, %struct.StructA** %A.addr, align 8, !tbaa !0
+  %f322 = getelementptr inbounds %struct.StructA, %struct.StructA* %2, i32 0, i32 1
+  %3 = load i32, i32* %f322, align 4, !tbaa !8
   ret i32 %3
 }
 
@@ -220,15 +220,15 @@ entry:
   store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0
   store %struct.StructS* %S, %struct.StructS** %S.addr, align 8, !tbaa !0
   store i64 %count, i64* %count.addr, align 8, !tbaa !4
-  %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0
-  %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1
+  %0 = load %struct.StructA*, %struct.StructA** %A.addr, align 8, !tbaa !0
+  %f32 = getelementptr inbounds %struct.StructA, %struct.StructA* %0, i32 0, i32 1
   store i32 1, i32* %f32, align 4, !tbaa !8
-  %1 = load %struct.StructS** %S.addr, align 8, !tbaa !0
-  %f16 = getelementptr inbounds %struct.StructS* %1, i32 0, i32 0
+  %1 = load %struct.StructS*, %struct.StructS** %S.addr, align 8, !tbaa !0
+  %f16 = getelementptr inbounds %struct.StructS, %struct.StructS* %1, i32 0, i32 0
   store i16 4, i16* %f16, align 2, !tbaa !19
-  %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0
-  %f321 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1
-  %3 = load i32* %f321, align 4, !tbaa !8
+  %2 = load %struct.StructA*, %struct.StructA** %A.addr, align 8, !tbaa !0
+  %f321 = getelementptr inbounds %struct.StructA, %struct.StructA* %2, i32 0, i32 1
+  %3 = load i32, i32* %f321, align 4, !tbaa !8
   ret i32 %3
 }
 
@@ -248,15 +248,15 @@ entry:
   store %struct.StructS* %S, %struct.StructS** %S.addr, align 8, !tbaa !0
   store %struct.StructS2* %S2, %struct.StructS2** %S2.addr, align 8, !tbaa !0
   store i64 %count, i64* %count.addr, align 8, !tbaa !4
-  %0 = load %struct.StructS** %S.addr, align 8, !tbaa !0
-  %f32 = getelementptr inbounds %struct.StructS* %0, i32 0, i32 1
+  %0 = load %struct.StructS*, %struct.StructS** %S.addr, align 8, !tbaa !0
+  %f32 = getelementptr inbounds %struct.StructS, %struct.StructS* %0, i32 0, i32 1
   store i32 1, i32* %f32, align 4, !tbaa !17
-  %1 = load %struct.StructS2** %S2.addr, align 8, !tbaa !0
-  %f321 = getelementptr inbounds %struct.StructS2* %1, i32 0, i32 1
+  %1 = load %struct.StructS2*, %struct.StructS2** %S2.addr, align 8, !tbaa !0
+  %f321 = getelementptr inbounds %struct.StructS2, %struct.StructS2* %1, i32 0, i32 1
   store i32 4, i32* %f321, align 4, !tbaa !20
-  %2 = load %struct.StructS** %S.addr, align 8, !tbaa !0
-  %f322 = getelementptr inbounds %struct.StructS* %2, i32 0, i32 1
-  %3 = load i32* %f322, align 4, !tbaa !17
+  %2 = load %struct.StructS*, %struct.StructS** %S.addr, align 8, !tbaa !0
+  %f322 = getelementptr inbounds %struct.StructS, %struct.StructS* %2, i32 0, i32 1
+  %3 = load i32, i32* %f322, align 4, !tbaa !17
   ret i32 %3
 }
 
@@ -276,15 +276,15 @@ entry:
   store %struct.StructS* %S, %struct.StructS** %S.addr, align 8, !tbaa !0
   store %struct.StructS2* %S2, %struct.StructS2** %S2.addr, align 8, !tbaa !0
   store i64 %count, i64* %count.addr, align 8, !tbaa !4
-  %0 = load %struct.StructS** %S.addr, align 8, !tbaa !0
-  %f32 = getelementptr inbounds %struct.StructS* %0, i32 0, i32 1
+  %0 = load %struct.StructS*, %struct.StructS** %S.addr, align 8, !tbaa !0
+  %f32 = getelementptr inbounds %struct.StructS, %struct.StructS* %0, i32 0, i32 1
   store i32 1, i32* %f32, align 4, !tbaa !17
-  %1 = load %struct.StructS2** %S2.addr, align 8, !tbaa !0
-  %f16 = getelementptr inbounds %struct.StructS2* %1, i32 0, i32 0
+  %1 = load %struct.StructS2*, %struct.StructS2** %S2.addr, align 8, !tbaa !0
+  %f16 = getelementptr inbounds %struct.StructS2, %struct.StructS2* %1, i32 0, i32 0
   store i16 4, i16* %f16, align 2, !tbaa !22
-  %2 = load %struct.StructS** %S.addr, align 8, !tbaa !0
-  %f321 = getelementptr inbounds %struct.StructS* %2, i32 0, i32 1
-  %3 = load i32* %f321, align 4, !tbaa !17
+  %2 = load %struct.StructS*, %struct.StructS** %S.addr, align 8, !tbaa !0
+  %f321 = getelementptr inbounds %struct.StructS, %struct.StructS* %2, i32 0, i32 1
+  %3 = load i32, i32* %f321, align 4, !tbaa !17
   ret i32 %3
 }
 
@@ -304,21 +304,21 @@ entry:
   store %struct.StructC* %C, %struct.StructC** %C.addr, align 8, !tbaa !0
   store %struct.StructD* %D, %struct.StructD** %D.addr, align 8, !tbaa !0
   store i64 %count, i64* %count.addr, align 8, !tbaa !4
-  %0 = load %struct.StructC** %C.addr, align 8, !tbaa !0
-  %b = getelementptr inbounds %struct.StructC* %0, i32 0, i32 1
-  %a = getelementptr inbounds %struct.StructB* %b, i32 0, i32 1
-  %f32 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 1
+  %0 = load %struct.StructC*, %struct.StructC** %C.addr, align 8, !tbaa !0
+  %b = getelementptr inbounds %struct.StructC, %struct.StructC* %0, i32 0, i32 1
+  %a = getelementptr inbounds %struct.StructB, %struct.StructB* %b, i32 0, i32 1
+  %f32 = getelementptr inbounds %struct.StructA, %struct.StructA* %a, i32 0, i32 1
   store i32 1, i32* %f32, align 4, !tbaa !23
-  %1 = load %struct.StructD** %D.addr, align 8, !tbaa !0
-  %b1 = getelementptr inbounds %struct.StructD* %1, i32 0, i32 1
-  %a2 = getelementptr inbounds %struct.StructB* %b1, i32 0, i32 1
-  %f323 = getelementptr inbounds %struct.StructA* %a2, i32 0, i32 1
+  %1 = load %struct.StructD*, %struct.StructD** %D.addr, align 8, !tbaa !0
+  %b1 = getelementptr inbounds %struct.StructD, %struct.StructD* %1, i32 0, i32 1
+  %a2 = getelementptr inbounds %struct.StructB, %struct.StructB* %b1, i32 0, i32 1
+  %f323 = getelementptr inbounds %struct.StructA, %struct.StructA* %a2, i32 0, i32 1
   store i32 4, i32* %f323, align 4, !tbaa !25
-  %2 = load %struct.StructC** %C.addr, align 8, !tbaa !0
-  %b4 = getelementptr inbounds %struct.StructC* %2, i32 0, i32 1
-  %a5 = getelementptr inbounds %struct.StructB* %b4, i32 0, i32 1
-  %f326 = getelementptr inbounds %struct.StructA* %a5, i32 0, i32 1
-  %3 = load i32* %f326, align 4, !tbaa !23
+  %2 = load %struct.StructC*, %struct.StructC** %C.addr, align 8, !tbaa !0
+  %b4 = getelementptr inbounds %struct.StructC, %struct.StructC* %2, i32 0, i32 1
+  %a5 = getelementptr inbounds %struct.StructB, %struct.StructB* %b4, i32 0, i32 1
+  %f326 = getelementptr inbounds %struct.StructA, %struct.StructA* %a5, i32 0, i32 1
+  %3 = load i32, i32* %f326, align 4, !tbaa !23
   ret i32 %3
 }
 
@@ -330,7 +330,7 @@ entry:
 ; OPT: define
 ; OPT: store i32 1
 ; OPT: store i32 4
-; OPT: %[[RET:.*]] = load i32*
+; OPT: %[[RET:.*]] = load i32, i32*
 ; OPT: ret i32 %[[RET]]
   %C.addr = alloca %struct.StructC*, align 8
   %D.addr = alloca %struct.StructD*, align 8
@@ -340,24 +340,24 @@ entry:
   store %struct.StructC* %C, %struct.StructC** %C.addr, align 8, !tbaa !0
   store %struct.StructD* %D, %struct.StructD** %D.addr, align 8, !tbaa !0
   store i64 %count, i64* %count.addr, align 8, !tbaa !4
-  %0 = load %struct.StructC** %C.addr, align 8, !tbaa !0
-  %b = getelementptr inbounds %struct.StructC* %0, i32 0, i32 1
+  %0 = load %struct.StructC*, %struct.StructC** %C.addr, align 8, !tbaa !0
+  %b = getelementptr inbounds %struct.StructC, %struct.StructC* %0, i32 0, i32 1
   store %struct.StructB* %b, %struct.StructB** %b1, align 8, !tbaa !0
-  %1 = load %struct.StructD** %D.addr, align 8, !tbaa !0
-  %b3 = getelementptr inbounds %struct.StructD* %1, i32 0, i32 1
+  %1 = load %struct.StructD*, %struct.StructD** %D.addr, align 8, !tbaa !0
+  %b3 = getelementptr inbounds %struct.StructD, %struct.StructD* %1, i32 0, i32 1
   store %struct.StructB* %b3, %struct.StructB** %b2, align 8, !tbaa !0
-  %2 = load %struct.StructB** %b1, align 8, !tbaa !0
-  %a = getelementptr inbounds %struct.StructB* %2, i32 0, i32 1
-  %f32 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 1
+  %2 = load %struct.StructB*, %struct.StructB** %b1, align 8, !tbaa !0
+  %a = getelementptr inbounds %struct.StructB, %struct.StructB* %2, i32 0, i32 1
+  %f32 = getelementptr inbounds %struct.StructA, %struct.StructA* %a, i32 0, i32 1
   store i32 1, i32* %f32, align 4, !tbaa !12
-  %3 = load %struct.StructB** %b2, align 8, !tbaa !0
-  %a4 = getelementptr inbounds %struct.StructB* %3, i32 0, i32 1
-  %f325 = getelementptr inbounds %struct.StructA* %a4, i32 0, i32 1
+  %3 = load %struct.StructB*, %struct.StructB** %b2, align 8, !tbaa !0
+  %a4 = getelementptr inbounds %struct.StructB, %struct.StructB* %3, i32 0, i32 1
+  %f325 = getelementptr inbounds %struct.StructA, %struct.StructA* %a4, i32 0, i32 1
   store i32 4, i32* %f325, align 4, !tbaa !12
-  %4 = load %struct.StructB** %b1, align 8, !tbaa !0
-  %a6 = getelementptr inbounds %struct.StructB* %4, i32 0, i32 1
-  %f327 = getelementptr inbounds %struct.StructA* %a6, i32 0, i32 1
-  %5 = load i32* %f327, align 4, !tbaa !12
+  %4 = load %struct.StructB*, %struct.StructB** %b1, align 8, !tbaa !0
+  %a6 = getelementptr inbounds %struct.StructB, %struct.StructB* %4, i32 0, i32 1
+  %f327 = getelementptr inbounds %struct.StructA, %struct.StructA* %a6, i32 0, i32 1
+  %5 = load i32, i32* %f327, align 4, !tbaa !12
   ret i32 %5
 }
 
diff --git a/test/Analysis/ValueTracking/memory-dereferenceable.ll b/test/Analysis/ValueTracking/memory-dereferenceable.ll
new file mode 100644
index 000000000000..dae64d7acc22
--- /dev/null
+++ b/test/Analysis/ValueTracking/memory-dereferenceable.ll
@@ -0,0 +1,65 @@
+; RUN: opt -print-memderefs -analyze -S <%s | FileCheck %s
+
+; Uses the print-deref (+ analyze to print) pass to run
+; isDereferenceablePointer() on many load instruction operands
+
+target datalayout = "e"
+
+declare zeroext i1 @return_i1()
+
+@globalstr = global [6 x i8] c"hello\00"
+@globali32ptr = external global i32*
+
+define void @test(i32 addrspace(1)* dereferenceable(8) %dparam) gc "statepoint-example" {
+; CHECK: The following are dereferenceable:
+; CHECK: %globalptr
+; CHECK: %alloca
+; CHECK: %dparam
+; CHECK: %relocate
+; CHECK-NOT: %nparam
+; CHECK-NOT: %nd_load
+; CHECK: %d4_load
+; CHECK-NOT: %d2_load
+; CHECK-NOT: %d_or_null_load
+; CHECK: %d_or_null_non_null_load
+entry:
+    %globalptr = getelementptr inbounds [6 x i8], [6 x i8]* @globalstr, i32 0, i32 0
+    %load1 = load i8, i8* %globalptr
+    %alloca = alloca i1
+    %load2 = load i1, i1* %alloca
+    %load3 = load i32, i32 addrspace(1)* %dparam
+    %tok = tail call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, i32 addrspace(1)* %dparam)
+    %relocate = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %tok, i32 7, i32 7)
+    %load4 = load i32, i32 addrspace(1)* %relocate
+    %nparam = getelementptr i32, i32 addrspace(1)* %dparam, i32 5
+    %load5 = load i32, i32 addrspace(1)* %nparam
+
+    ; Load from a non-dereferenceable load
+    %nd_load = load i32*, i32** @globali32ptr
+    %load6 = load i32, i32* %nd_load
+
+    ; Load from a dereferenceable load
+    %d4_load = load i32*, i32** @globali32ptr, !dereferenceable !0
+    %load7 = load i32, i32* %d4_load
+
+    ; Load from an offset not covered by the dereferenceable portion
+    %d2_load = load i32*, i32** @globali32ptr, !dereferenceable !1
+    %load8 = load i32, i32* %d2_load
+
+    ; Load from a potentially null pointer with dereferenceable_or_null
+    %d_or_null_load = load i32*, i32** @globali32ptr, !dereferenceable_or_null !0
+    %load9 = load i32, i32* %d_or_null_load
+
+    ; Load from a non-null pointer with dereferenceable_or_null
+    %d_or_null_non_null_load = load i32*, i32** @globali32ptr, !nonnull !2, !dereferenceable_or_null !0
+    %load10 = load i32, i32* %d_or_null_non_null_load
+
+    ret void
+}
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i32, ...)
+declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32, i32, i32)
+
+!0 = !{i64 4}
+!1 = !{i64 2}
+!2 = !{}
diff --git a/test/Analysis/ValueTracking/pr23011.ll b/test/Analysis/ValueTracking/pr23011.ll
new file mode 100644
index 000000000000..9edc1c406601
--- /dev/null
+++ b/test/Analysis/ValueTracking/pr23011.ll
@@ -0,0 +1,15 @@
+; RUN: opt -indvars -S < %s | FileCheck %s
+
+declare { i8, i1 } @llvm.smul.with.overflow.i8(i8, i8) nounwind readnone
+
+define i1 @test1(i8 %x) {
+ entry:
+; CHECK-LABEL: @test1
+  %rem = srem i8 %x, 15
+  %t = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %rem, i8 %rem)
+; CHECK: %t = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %rem, i8 %rem)
+; CHECK: %obit = extractvalue { i8, i1 } %t, 1
+; CHECK: ret i1 %obit
+  %obit = extractvalue { i8, i1 } %t, 1
+  ret i1 %obit
+}
diff --git a/test/Assembler/2002-04-29-NameBinding.ll b/test/Assembler/2002-04-29-NameBinding.ll
index 960209bcb5b3..c387c47ef93f 100644
--- a/test/Assembler/2002-04-29-NameBinding.ll
+++ b/test/Assembler/2002-04-29-NameBinding.ll
@@ -13,7 +13,7 @@
 
 define i32 @createtask() {
         %v1 = alloca i32                ;; Alloca should have one use! 
-        %reg112 = load i32* %v1         ;; This load should not use the global!
+        %reg112 = load i32, i32* %v1         ;; This load should not use the global!
         ret i32 %reg112
 }
 
diff --git a/test/Assembler/2002-07-25-ReturnPtrFunction.ll b/test/Assembler/2002-07-25-ReturnPtrFunction.ll
index fdee93c1ca70..0fb9d55faed4 100644
--- a/test/Assembler/2002-07-25-ReturnPtrFunction.ll
+++ b/test/Assembler/2002-07-25-ReturnPtrFunction.ll
@@ -7,7 +7,7 @@
 declare void (i32)* @foo()
 
 define void @test() {
-        call void (i32)* ()* @foo( )           ; <%ty*>:1 [#uses=0]
+        call void (i32)* () @foo( )           ; <%ty*>:1 [#uses=0]
         ret void
 }
 
diff --git a/test/Assembler/2002-08-15-ConstantExprProblem.ll b/test/Assembler/2002-08-15-ConstantExprProblem.ll
index 343a1044b9c9..47a3f9c96c0e 100644
--- a/test/Assembler/2002-08-15-ConstantExprProblem.ll
+++ b/test/Assembler/2002-08-15-ConstantExprProblem.ll
@@ -8,7 +8,7 @@ define i8* @test() {
         br label %BB1
 
 BB1:            ; preds = %BB2, %0
-        %ret = phi i8* [ getelementptr ([12 x i8]* @.LC0, i64 0, i64 0), %0 ], [ null, %BB2 ]          ; <i8*> [#uses=1]
+        %ret = phi i8* [ getelementptr ([12 x i8], [12 x i8]* @.LC0, i64 0, i64 0), %0 ], [ null, %BB2 ]          ; <i8*> [#uses=1]
         ret i8* %ret
 
 BB2:            ; No predecessors!
diff --git a/test/Assembler/2002-08-15-UnresolvedGlobalReference.ll b/test/Assembler/2002-08-15-UnresolvedGlobalReference.ll
index 6bbe0cfe7f6d..cbed33229c4b 100644
--- a/test/Assembler/2002-08-15-UnresolvedGlobalReference.ll
+++ b/test/Assembler/2002-08-15-UnresolvedGlobalReference.ll
@@ -4,6 +4,6 @@
 @.LC0 = internal global [12 x i8] c"hello world\00"             ; <[12 x i8]*> [#uses=1]
 
 define i8* @test() {
-        ret i8* getelementptr ([12 x i8]* @.LC0, i64 0, i64 0)
+        ret i8* getelementptr ([12 x i8], [12 x i8]* @.LC0, i64 0, i64 0)
 }
 
diff --git a/test/Assembler/2002-08-16-ConstExprInlined.ll b/test/Assembler/2002-08-16-ConstExprInlined.ll
index b78d858c8cf9..d43fe9784055 100644
--- a/test/Assembler/2002-08-16-ConstExprInlined.ll
+++ b/test/Assembler/2002-08-16-ConstExprInlined.ll
@@ -18,6 +18,6 @@ declare i32 @puts(i8*)
 
 define void @main() {
 bb1:
-	%reg211 = call i32 @puts( i8* getelementptr ([4 x i8]* @.LC0, i64 0, i64 0) )		; <i32> [#uses=0]
+	%reg211 = call i32 @puts( i8* getelementptr ([4 x i8], [4 x i8]* @.LC0, i64 0, i64 0) )		; <i32> [#uses=0]
 	ret void
 }
diff --git a/test/Assembler/2002-08-19-BytecodeReader.ll b/test/Assembler/2002-08-19-BytecodeReader.ll
index 0722885ea9fa..1fd6bb6f3bee 100644
--- a/test/Assembler/2002-08-19-BytecodeReader.ll
+++ b/test/Assembler/2002-08-19-BytecodeReader.ll
@@ -10,9 +10,9 @@
 @search = external global %CHESS_POSITION		; <%CHESS_POSITION*> [#uses=2]
 
 define void @Evaluate() {
-	%reg1321 = getelementptr %CHESS_POSITION* @search, i64 0, i32 1		; <i32*> [#uses=1]
-	%reg114 = load i32* %reg1321		; <i32> [#uses=0]
-	%reg1801 = getelementptr %CHESS_POSITION* @search, i64 0, i32 0		; <i32*> [#uses=1]
-	%reg182 = load i32* %reg1801		; <i32> [#uses=0]
+	%reg1321 = getelementptr %CHESS_POSITION, %CHESS_POSITION* @search, i64 0, i32 1		; <i32*> [#uses=1]
+	%reg114 = load i32, i32* %reg1321		; <i32> [#uses=0]
+	%reg1801 = getelementptr %CHESS_POSITION, %CHESS_POSITION* @search, i64 0, i32 0		; <i32*> [#uses=1]
+	%reg182 = load i32, i32* %reg1801		; <i32> [#uses=0]
 	ret void
 }
diff --git a/test/Assembler/2003-05-15-AssemblerProblem.ll b/test/Assembler/2003-05-15-AssemblerProblem.ll
index eba26a2093ee..70c9617ef1c0 100644
--- a/test/Assembler/2003-05-15-AssemblerProblem.ll
+++ b/test/Assembler/2003-05-15-AssemblerProblem.ll
@@ -4,12 +4,12 @@
 ; RUN: verify-uselistorder %s
 
 define void @test() {
-        call void (...)* bitcast (void (i16*, i32)* @AddString to void (...)*)( i16* null, i32 0 )
+        call void (...) bitcast (void (i16*, i32)* @AddString to void (...)*)( i16* null, i32 0 )
         ret void
 }
 
 define void @AddString(i16* %tmp.124, i32 %tmp.127) {
-        call void (...)* bitcast (void (i16*, i32)* @AddString to void (...)*)( i16* %tmp.124, i32 %tmp.127 )
+        call void (...) bitcast (void (i16*, i32)* @AddString to void (...)*)( i16* %tmp.124, i32 %tmp.127 )
         ret void
 }
 
diff --git a/test/Assembler/2003-08-20-ConstantExprGEP-Fold.ll b/test/Assembler/2003-08-20-ConstantExprGEP-Fold.ll
index 911f0ff71592..435992c38ad4 100644
--- a/test/Assembler/2003-08-20-ConstantExprGEP-Fold.ll
+++ b/test/Assembler/2003-08-20-ConstantExprGEP-Fold.ll
@@ -4,7 +4,7 @@
 @.str_1 = internal constant [6 x i8] c"_Bool\00"                ; <[6 x i8]*> [#uses=2]
 
 define i32 @test() {
-        %tmp.54 = load i8* getelementptr ([6 x i8]* @.str_1, i64 0, i64 1)            ; <i8> [#uses=1]
+        %tmp.54 = load i8, i8* getelementptr ([6 x i8], [6 x i8]* @.str_1, i64 0, i64 1)            ; <i8> [#uses=1]
         %tmp.55 = icmp ne i8 %tmp.54, 66                ; <i1> [#uses=1]
         br i1 %tmp.55, label %then.7, label %endif.7
 
diff --git a/test/Assembler/2004-01-11-getelementptrfolding.ll b/test/Assembler/2004-01-11-getelementptrfolding.ll
index 188a95fa9505..def8e37c1a6a 100644
--- a/test/Assembler/2004-01-11-getelementptrfolding.ll
+++ b/test/Assembler/2004-01-11-getelementptrfolding.ll
@@ -7,7 +7,7 @@
 @data_triangleItems = internal constant [2908 x %struct.TTriangleItem] zeroinitializer; <[2908 x %struct.TTriangleItem]*> [#uses=2]
 
 define void @foo() {
-        store i16 0, i16* getelementptr ([2908 x %struct.TTriangleItem]* @data_triangleItems, i64 0, i64 0, i32 2, i64 0, i32 0)
+        store i16 0, i16* getelementptr ([2908 x %struct.TTriangleItem], [2908 x %struct.TTriangleItem]* @data_triangleItems, i64 0, i64 0, i32 2, i64 0, i32 0)
         ret void
 }
 
diff --git a/test/Assembler/2004-04-04-GetElementPtrIndexTypes.ll b/test/Assembler/2004-04-04-GetElementPtrIndexTypes.ll
index a86fe63edf75..04d59619bd88 100644
--- a/test/Assembler/2004-04-04-GetElementPtrIndexTypes.ll
+++ b/test/Assembler/2004-04-04-GetElementPtrIndexTypes.ll
@@ -2,10 +2,10 @@
 ; RUN: verify-uselistorder %s
 
 define i32* @t1({ float, i32 }* %X) {
-        %W = getelementptr { float, i32 }* %X, i32 20, i32 1            ; <i32*> [#uses=0]
-        %X.upgrd.1 = getelementptr { float, i32 }* %X, i64 20, i32 1            ; <i32*> [#uses=0]
-        %Y = getelementptr { float, i32 }* %X, i64 20, i32 1            ; <i32*> [#uses=1]
-        %Z = getelementptr { float, i32 }* %X, i64 20, i32 1            ; <i32*> [#uses=0]
+        %W = getelementptr { float, i32 }, { float, i32 }* %X, i32 20, i32 1            ; <i32*> [#uses=0]
+        %X.upgrd.1 = getelementptr { float, i32 }, { float, i32 }* %X, i64 20, i32 1            ; <i32*> [#uses=0]
+        %Y = getelementptr { float, i32 }, { float, i32 }* %X, i64 20, i32 1            ; <i32*> [#uses=1]
+        %Z = getelementptr { float, i32 }, { float, i32 }* %X, i64 20, i32 1            ; <i32*> [#uses=0]
         ret i32* %Y
 }
 
diff --git a/test/Assembler/2004-06-07-VerifierBug.ll b/test/Assembler/2004-06-07-VerifierBug.ll
index 090599a9a855..2fc0ae29ca7b 100644
--- a/test/Assembler/2004-06-07-VerifierBug.ll
+++ b/test/Assembler/2004-06-07-VerifierBug.ll
@@ -6,7 +6,7 @@ entry:
      ret void
 
 loop:           ; preds = %loop
-     %tmp.4.i9 = getelementptr i32* null, i32 %tmp.5.i10             ; <i32*> [#uses=1]
-     %tmp.5.i10 = load i32* %tmp.4.i9                ; <i32> [#uses=1]
+     %tmp.4.i9 = getelementptr i32, i32* null, i32 %tmp.5.i10             ; <i32*> [#uses=1]
+     %tmp.5.i10 = load i32, i32* %tmp.4.i9                ; <i32> [#uses=1]
      br label %loop
 }
diff --git a/test/Assembler/2007-01-05-Cmp-ConstExpr.ll b/test/Assembler/2007-01-05-Cmp-ConstExpr.ll
index 54a4372b977e..81196293a72d 100644
--- a/test/Assembler/2007-01-05-Cmp-ConstExpr.ll
+++ b/test/Assembler/2007-01-05-Cmp-ConstExpr.ll
@@ -6,9 +6,9 @@
 
 define i32 @main(i32 %argc, i8** %argv) {
 entry:
-        %tmp65 = getelementptr i8** %argv, i32 1                ; <i8**> [#uses=1]
-        %tmp66 = load i8** %tmp65               ; <i8*> [#uses=0]
-        br i1 icmp ne (i32 sub (i32 ptrtoint (i8* getelementptr ([4 x i8]* @str, i32 0, i64 1) to i32), i32 ptrtoint ([4 x i8]* @str to i32)), i32 1), label %exit_1, label %exit_2
+        %tmp65 = getelementptr i8*, i8** %argv, i32 1                ; <i8**> [#uses=1]
+        %tmp66 = load i8*, i8** %tmp65               ; <i8*> [#uses=0]
+        br i1 icmp ne (i32 sub (i32 ptrtoint (i8* getelementptr ([4 x i8], [4 x i8]* @str, i32 0, i64 1) to i32), i32 ptrtoint ([4 x i8]* @str to i32)), i32 1), label %exit_1, label %exit_2
 
 exit_1:         ; preds = %entry
         ret i32 0
diff --git a/test/Assembler/2007-04-20-AlignedLoad.ll b/test/Assembler/2007-04-20-AlignedLoad.ll
index bcf65fd6eac7..1e8850a7073e 100644
--- a/test/Assembler/2007-04-20-AlignedLoad.ll
+++ b/test/Assembler/2007-04-20-AlignedLoad.ll
@@ -3,6 +3,6 @@
 
 define i32 @test(i32* %arg) {
 entry:
-        %tmp2 = load i32* %arg, align 1024      ; <i32> [#uses=1]
+        %tmp2 = load i32, i32* %arg, align 1024      ; <i32> [#uses=1]
         ret i32 %tmp2
 }
diff --git a/test/Assembler/2007-12-11-AddressSpaces.ll b/test/Assembler/2007-12-11-AddressSpaces.ll
index f860f57e8ddd..5155c6b8188a 100644
--- a/test/Assembler/2007-12-11-AddressSpaces.ll
+++ b/test/Assembler/2007-12-11-AddressSpaces.ll
@@ -12,15 +12,15 @@
 
 define void @foo() {
 entry:
-	%tmp1 = load i32 addrspace(33)* addrspace(42)* getelementptr (%struct.mystruct addrspace(42)* @input, i32 0, i32 3), align 4		; <i32 addrspace(33)*> [#uses=1]
-	store i32 addrspace(33)* %tmp1, i32 addrspace(33)* addrspace(66)* getelementptr (%struct.mystruct addrspace(66)* @output, i32 0, i32 1), align 4
+	%tmp1 = load i32 addrspace(33)*, i32 addrspace(33)* addrspace(42)* getelementptr (%struct.mystruct, %struct.mystruct addrspace(42)* @input, i32 0, i32 3), align 4		; <i32 addrspace(33)*> [#uses=1]
+	store i32 addrspace(33)* %tmp1, i32 addrspace(33)* addrspace(66)* getelementptr (%struct.mystruct, %struct.mystruct addrspace(66)* @output, i32 0, i32 1), align 4
 	ret void
 }
 
 define i32 addrspace(11)* @bar(i32 addrspace(11)* addrspace(22)* addrspace(33)* %x) {
 entry:
-	%tmp1 = load i32 addrspace(11)* addrspace(22)* addrspace(33)* @y, align 4		; <i32 addrspace(11)* addrspace(22)*> [#uses=2]
+	%tmp1 = load i32 addrspace(11)* addrspace(22)*, i32 addrspace(11)* addrspace(22)* addrspace(33)* @y, align 4		; <i32 addrspace(11)* addrspace(22)*> [#uses=2]
 	store i32 addrspace(11)* addrspace(22)* %tmp1, i32 addrspace(11)* addrspace(22)* addrspace(33)* %x, align 4
-	%tmp5 = load i32 addrspace(11)* addrspace(22)* %tmp1, align 4		; <i32 addrspace(11)*> [#uses=1]
+	%tmp5 = load i32 addrspace(11)*, i32 addrspace(11)* addrspace(22)* %tmp1, align 4		; <i32 addrspace(11)*> [#uses=1]
 	ret i32 addrspace(11)* %tmp5
 }
diff --git a/test/Assembler/2008-01-11-VarargAttrs.ll b/test/Assembler/2008-01-11-VarargAttrs.ll
index 0b6592c69424..3111f2d32165 100644
--- a/test/Assembler/2008-01-11-VarargAttrs.ll
+++ b/test/Assembler/2008-01-11-VarargAttrs.ll
@@ -6,6 +6,6 @@
 declare void @foo(...)
 
 define void @bar() {
-	call void (...)* @foo(%struct* byval null )
+	call void (...) @foo(%struct* byval null )
 	ret void
 }
diff --git a/test/Assembler/2009-07-24-ZeroArgGEP.ll b/test/Assembler/2009-07-24-ZeroArgGEP.ll
index 92f4d59d2f7f..cd8b5d9827cc 100644
--- a/test/Assembler/2009-07-24-ZeroArgGEP.ll
+++ b/test/Assembler/2009-07-24-ZeroArgGEP.ll
@@ -2,5 +2,5 @@
 ; RUN: verify-uselistorder %s
 
 @foo = global i32 0
-@bar = constant i32* getelementptr(i32* @foo)
+@bar = constant i32* getelementptr(i32, i32* @foo)
 
diff --git a/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll b/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll
index 50ad32e1c9ed..8a6735fbca48 100644
--- a/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll
+++ b/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll
@@ -7,15 +7,15 @@ target triple = "x86_64-apple-darwin10.2"
 %struct.anon = type { i32, i32 }
 %struct.test = type { i64, %struct.anon, %struct.test* }
 
-@TestArrayPtr = global %struct.test* getelementptr inbounds ([10 x %struct.test]* @TestArray, i64 0, i64 3) ; <%struct.test**> [#uses=1]
+@TestArrayPtr = global %struct.test* getelementptr inbounds ([10 x %struct.test], [10 x %struct.test]* @TestArray, i64 0, i64 3) ; <%struct.test**> [#uses=1]
 @TestArray = common global [10 x %struct.test] zeroinitializer, align 32 ; <[10 x %struct.test]*> [#uses=2]
 
 define i32 @main() nounwind readonly {
   %diff1 = alloca i64                             ; <i64*> [#uses=2]
 ; CHECK: call void @llvm.dbg.value(metadata i64 72,
-  call void @llvm.dbg.declare(metadata i64* %diff1, metadata !0, metadata !{!"0x102"})
+  call void @llvm.dbg.declare(metadata i64* %diff1, metadata !0, metadata !DIExpression()), !dbg !DILocation(scope: !1)
   store i64 72, i64* %diff1, align 8
-  %v1 = load %struct.test** @TestArrayPtr, align 8 ; <%struct.test*> [#uses=1]
+  %v1 = load %struct.test*, %struct.test** @TestArrayPtr, align 8 ; <%struct.test*> [#uses=1]
   %v2 = ptrtoint %struct.test* %v1 to i64 ; <i64> [#uses=1]
   %v3 = sub i64 %v2, ptrtoint ([10 x %struct.test]* @TestArray to i64) ; <i64> [#uses=1]
   store i64 %v3, i64* %diff1, align 8
@@ -25,15 +25,15 @@ define i32 @main() nounwind readonly {
 declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 
 !7 = !{!1}
-!6 = !{!"0x11\0012\00clang version 3.0 (trunk 131941)\001\00\000\00\000", !8, !9, !9, !7, null, null} ; [ DW_TAG_compile_unit ]
-!0 = !{!"0x100\00c\002\000", !1, !2, !5} ; [ DW_TAG_auto_variable ]
-!1 = !{!"0x2e\00main\00main\00\001\000\001\000\006\00256\000\001", !8, !2, !3, null, i32 ()* @main, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !8} ; [ DW_TAG_file_type ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !8, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 131941)", isOptimized: true, emissionKind: 0, file: !8, enums: !9, retainedTypes: !9, subprograms: !7)
+!0 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "c", line: 2, scope: !1, file: !2, type: !5)
+!1 = !DISubprogram(name: "main", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !8, scope: !2, type: !3, function: i32 ()* @main)
+!2 = !DIFile(filename: "/d/j/debug-test.c", directory: "/Volumes/Data/b")
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !6} ; [ DW_TAG_base_type ]
-!8 = !{!"/d/j/debug-test.c", !"/Volumes/Data/b"}
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DIFile(filename: "/d/j/debug-test.c", directory: "/Volumes/Data/b")
 !9 = !{i32 0}
 
 !llvm.module.flags = !{!10}
-!10 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Assembler/ConstantExprFold.ll b/test/Assembler/ConstantExprFold.ll
index dc4133115135..3314f8c1af88 100644
--- a/test/Assembler/ConstantExprFold.ll
+++ b/test/Assembler/ConstantExprFold.ll
@@ -19,11 +19,11 @@ global i64* inttoptr (i64 xor (i64 ptrtoint (i64* @A to i64), i64 0) to i64*) ;
 %Ty = type { i32, i32 }
 @B = external global %Ty 
 
-global i1 icmp slt (i64* @A, i64* getelementptr (i64* @A, i64 1))        ; true
-global i1 icmp ult (i64* @A, i64* getelementptr (i64* @A, i64 1))        ; true
-global i1 icmp slt (i64* @A, i64* getelementptr (i64* @A, i64 0))        ; false
-global i1 icmp slt (i32* getelementptr (%Ty* @B, i64 0, i32 0), 
-                   i32* getelementptr (%Ty* @B, i64 0, i32 1))            ; true
+global i1 icmp slt (i64* @A, i64* getelementptr (i64, i64* @A, i64 1))        ; true
+global i1 icmp ult (i64* @A, i64* getelementptr (i64, i64* @A, i64 1))        ; true
+global i1 icmp slt (i64* @A, i64* getelementptr (i64, i64* @A, i64 0))        ; false
+global i1 icmp slt (i32* getelementptr (%Ty, %Ty* @B, i64 0, i32 0), 
+                   i32* getelementptr (%Ty, %Ty* @B, i64 0, i32 1))            ; true
 ;global i1 icmp ne (i64* @A, i64* bitcast (%Ty* @B to i64*))                 ; true
 
 ; PR2206
diff --git a/test/Assembler/ConstantExprNoFold.ll b/test/Assembler/ConstantExprNoFold.ll
index 83236d5793b3..38f8cbbc9cd8 100644
--- a/test/Assembler/ConstantExprNoFold.ll
+++ b/test/Assembler/ConstantExprNoFold.ll
@@ -14,21 +14,21 @@ target datalayout = "p:32:32"
 ; icmp should return true. It's not valid to *dereference* in @B from a pointer
 ; based on @A, but icmp isn't a dereference.
 
-; CHECK: @C = global i1 icmp eq (i64* getelementptr inbounds (i64* @A, i64 1), i64* @B)
-@C = global i1 icmp eq (i64* getelementptr inbounds (i64* @A, i64 1), i64* @B)
+; CHECK: @C = global i1 icmp eq (i64* getelementptr inbounds (i64, i64* @A, i64 1), i64* @B)
+@C = global i1 icmp eq (i64* getelementptr inbounds (i64, i64* @A, i64 1), i64* @B)
 
 ; Don't fold this completely away either. In theory this could be simplified
 ; to only use a gep on one side of the icmp though.
 
-; CHECK: @D = global i1 icmp eq (i64* getelementptr inbounds (i64* @A, i64 1), i64* getelementptr inbounds (i64* @B, i64 2))
-@D = global i1 icmp eq (i64* getelementptr inbounds (i64* @A, i64 1), i64* getelementptr inbounds (i64* @B, i64 2))
+; CHECK: @D = global i1 icmp eq (i64* getelementptr inbounds (i64, i64* @A, i64 1), i64* getelementptr inbounds (i64, i64* @B, i64 2))
+@D = global i1 icmp eq (i64* getelementptr inbounds (i64, i64* @A, i64 1), i64* getelementptr inbounds (i64, i64* @B, i64 2))
 
 ; CHECK: @E = global i64 addrspace(1)* addrspacecast (i64* @A to i64 addrspace(1)*)
 @E = global i64 addrspace(1)* addrspacecast(i64* @A to i64 addrspace(1)*)
 
 ; Don't add an inbounds on @weak.gep, since @weak may be null.
-; CHECK: @weak.gep = global i32* getelementptr (i32* @weak, i32 1)
-@weak.gep = global i32* getelementptr (i32* @weak, i32 1)
+; CHECK: @weak.gep = global i32* getelementptr (i32, i32* @weak, i32 1)
+@weak.gep = global i32* getelementptr (i32, i32* @weak, i32 1)
 @weak = extern_weak global i32
 
 ; An object with weak linkage cannot have it's identity determined at compile time.
@@ -43,8 +43,8 @@ target datalayout = "p:32:32"
 @empty.cmp = global i1 icmp eq ([0 x i8]* @empty.1, [0 x i8]* @empty.2)
 
 ; Don't add an inbounds on @glob.a3, since it's not inbounds.
-; CHECK: @glob.a3 = alias getelementptr (i32* @glob.a2, i32 1)
+; CHECK: @glob.a3 = alias getelementptr (i32, i32* @glob.a2, i32 1)
 @glob = global i32 0
-@glob.a3 = alias getelementptr (i32* @glob.a2, i32 1)
-@glob.a2 = alias getelementptr (i32* @glob.a1, i32 1)
+@glob.a3 = alias getelementptr (i32, i32* @glob.a2, i32 1)
+@glob.a2 = alias getelementptr (i32, i32* @glob.a1, i32 1)
 @glob.a1 = alias i32* @glob
diff --git a/test/Assembler/alias-use-list-order.ll b/test/Assembler/alias-use-list-order.ll
index d29fd6e435fe..c72bad28e500 100644
--- a/test/Assembler/alias-use-list-order.ll
+++ b/test/Assembler/alias-use-list-order.ll
@@ -2,10 +2,10 @@
 
 ; Globals.
 @global = global i32 0
-@alias.ref1 = global i32* getelementptr inbounds (i32* @alias, i64 1)
-@alias.ref2 = global i32* getelementptr inbounds (i32* @alias, i64 1)
+@alias.ref1 = global i32* getelementptr inbounds (i32, i32* @alias, i64 1)
+@alias.ref2 = global i32* getelementptr inbounds (i32, i32* @alias, i64 1)
 
 ; Aliases.
 @alias = alias i32* @global
-@alias.ref3 = alias i32* getelementptr inbounds (i32* @alias, i64 1)
-@alias.ref4 = alias i32* getelementptr inbounds (i32* @alias, i64 1)
+@alias.ref3 = alias i32* getelementptr inbounds (i32, i32* @alias, i64 1)
+@alias.ref4 = alias i32* getelementptr inbounds (i32, i32* @alias, i64 1)
diff --git a/test/Assembler/align-inst-load.ll b/test/Assembler/align-inst-load.ll
index 3586be2d6e03..75fcd3e5a028 100644
--- a/test/Assembler/align-inst-load.ll
+++ b/test/Assembler/align-inst-load.ll
@@ -1,6 +1,6 @@
 ; RUN: not llvm-as %s -o /dev/null 2>/dev/null
 
 define void @foo() {
-  load i1* %p, align 1073741824
+  load i1, i1* %p, align 1073741824
   ret void
 }
diff --git a/test/Assembler/align-inst.ll b/test/Assembler/align-inst.ll
index 1952fbc52972..028da396d2fe 100644
--- a/test/Assembler/align-inst.ll
+++ b/test/Assembler/align-inst.ll
@@ -5,7 +5,7 @@
 
 define void @foo() {
   %p = alloca i1, align 536870912
-  load i1* %p, align 536870912
+  load i1, i1* %p, align 536870912
   store i1 false, i1* %p, align 536870912
   ret void
 }
diff --git a/test/Assembler/alloca-invalid-type-2.ll b/test/Assembler/alloca-invalid-type-2.ll
new file mode 100644
index 000000000000..7b1cc6255427
--- /dev/null
+++ b/test/Assembler/alloca-invalid-type-2.ll
@@ -0,0 +1,9 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+; CHECK: invalid type for alloca
+
+define void @test() {
+entry:
+  alloca i32 (i32)
+  ret void
+}
diff --git a/test/Assembler/alloca-invalid-type.ll b/test/Assembler/alloca-invalid-type.ll
new file mode 100644
index 000000000000..413bcbd76ba0
--- /dev/null
+++ b/test/Assembler/alloca-invalid-type.ll
@@ -0,0 +1,9 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+; CHECK: invalid type for alloca
+
+define void @test() {
+entry:
+  alloca metadata !{null}
+  ret void
+}
diff --git a/test/Assembler/alloca-size-one.ll b/test/Assembler/alloca-size-one.ll
new file mode 100644
index 000000000000..fc5ee34254a1
--- /dev/null
+++ b/test/Assembler/alloca-size-one.ll
@@ -0,0 +1,11 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+define void @foo() {
+entry:
+; CHECK: %alloc32 = alloca i1, align 8
+; CHECK: %alloc64 = alloca i1, i64 1, align 8
+  %alloc32 = alloca i1, i32 1, align 8
+  %alloc64 = alloca i1, i64 1, align 8
+  unreachable
+}
diff --git a/test/Assembler/atomic.ll b/test/Assembler/atomic.ll
index 0356f5fc582c..148b95d88e30 100644
--- a/test/Assembler/atomic.ll
+++ b/test/Assembler/atomic.ll
@@ -3,10 +3,10 @@
 ; Basic smoke test for atomic operations.
 
 define void @f(i32* %x) {
-  ; CHECK: load atomic i32* %x unordered, align 4
-  load atomic i32* %x unordered, align 4
-  ; CHECK: load atomic volatile i32* %x singlethread acquire, align 4
-  load atomic volatile i32* %x singlethread acquire, align 4
+  ; CHECK: load atomic i32, i32* %x unordered, align 4
+  load atomic i32, i32* %x unordered, align 4
+  ; CHECK: load atomic volatile i32, i32* %x singlethread acquire, align 4
+  load atomic volatile i32, i32* %x singlethread acquire, align 4
   ; CHECK: store atomic i32 3, i32* %x release, align 4
   store atomic i32 3, i32* %x release, align 4
   ; CHECK: store atomic volatile i32 3, i32* %x singlethread monotonic, align 4
diff --git a/test/Assembler/auto_upgrade_intrinsics.ll b/test/Assembler/auto_upgrade_intrinsics.ll
index f16e5fee6c36..9a66a0defcea 100644
--- a/test/Assembler/auto_upgrade_intrinsics.ll
+++ b/test/Assembler/auto_upgrade_intrinsics.ll
@@ -55,6 +55,6 @@ define i32 @test.objectsize() {
 ; CHECK-LABEL: @test.objectsize(
 ; CHECK: @llvm.objectsize.i32.p0i8
 ; CHECK-DAG: declare i32 @llvm.objectsize.i32.p0i8
-  %s = call i32 @llvm.objectsize.i32(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i1 false)
+  %s = call i32 @llvm.objectsize.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i1 false)
   ret i32 %s
 }
diff --git a/test/Assembler/call-invalid-1.ll b/test/Assembler/call-invalid-1.ll
new file mode 100644
index 000000000000..4a12b14a5edb
--- /dev/null
+++ b/test/Assembler/call-invalid-1.ll
@@ -0,0 +1,9 @@
+; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s
+
+declare void @f()
+
+define void @g() {
+  call void @f() align 8
+; CHECK: error: call instructions may not have an alignment
+  ret void
+}
diff --git a/test/Assembler/debug-info.ll b/test/Assembler/debug-info.ll
new file mode 100644
index 000000000000..91dfe561a2fe
--- /dev/null
+++ b/test/Assembler/debug-info.ll
@@ -0,0 +1,72 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+; CHECK: !named = !{!0, !0, !1, !2, !3, !4, !5, !6, !7, !8, !8, !9, !10, !11, !12, !13, !14, !15, !16, !17, !18, !19, !20, !21, !22, !23, !24, !25, !26, !27, !27}
+!named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15, !16, !17, !18, !19, !20, !21, !22, !23, !24, !25, !26, !27, !28, !29, !30}
+
+; CHECK:      !0 = !DISubrange(count: 3)
+; CHECK-NEXT: !1 = !DISubrange(count: 3, lowerBound: 4)
+; CHECK-NEXT: !2 = !DISubrange(count: 3, lowerBound: -5)
+!0 = !DISubrange(count: 3)
+!1 = !DISubrange(count: 3, lowerBound: 0)
+
+!2 = !DISubrange(count: 3, lowerBound: 4)
+!3 = !DISubrange(count: 3, lowerBound: -5)
+
+; CHECK-NEXT: !3 = !DIEnumerator(name: "seven", value: 7)
+; CHECK-NEXT: !4 = !DIEnumerator(name: "negeight", value: -8)
+; CHECK-NEXT: !5 = !DIEnumerator(name: "", value: 0)
+!4 = !DIEnumerator(name: "seven", value: 7)
+!5 = !DIEnumerator(name: "negeight", value: -8)
+!6 = !DIEnumerator(name: "", value: 0)
+
+; CHECK-NEXT: !6 = !DIBasicType(name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char)
+; CHECK-NEXT: !7 = !DIBasicType(tag: DW_TAG_unspecified_type, name: "decltype(nullptr)")
+; CHECK-NEXT: !8 = !DIBasicType()
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char)
+!8 = !DIBasicType(tag: DW_TAG_unspecified_type, name: "decltype(nullptr)")
+!9 = !DIBasicType()
+!10 = !DIBasicType(tag: DW_TAG_base_type, name: "", size: 0, align: 0, encoding: 0)
+
+; CHECK-NEXT: !9 = !DITemplateTypeParameter(type: !6)
+; CHECK-NEXT: !10 = !DIFile(filename: "path/to/file", directory: "/path/to/dir")
+; CHECK-NEXT: !11 = distinct !{}
+; CHECK-NEXT: !12 = !DIFile(filename: "", directory: "")
+!11 = !DITemplateTypeParameter(type: !7)
+!12 = !DIFile(filename: "path/to/file", directory: "/path/to/dir")
+!13 = distinct !{}
+!14 = !DIFile(filename: "", directory: "")
+
+; CHECK-NEXT: !13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !6, size: 32, align: 32)
+!15 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !7, size: 32, align: 32)
+
+; CHECK-NEXT: !14 = !DICompositeType(tag: DW_TAG_structure_type, name: "MyType", file: !10, line: 2, size: 32, align: 32, identifier: "MangledMyType")
+; CHECK-NEXT: !15 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Base", scope: !14, file: !10, line: 3, size: 128, align: 32, offset: 64, flags: DIFlagPublic, elements: !16, runtimeLang: DW_LANG_C_plus_plus_11, vtableHolder: !15, templateParams: !18, identifier: "MangledBase")
+; CHECK-NEXT: !16 = !{!17}
+; CHECK-NEXT: !17 = !DIDerivedType(tag: DW_TAG_member, name: "field", scope: !15, file: !10, line: 4, baseType: !6, size: 32, align: 32, offset: 32, flags: DIFlagPublic)
+; CHECK-NEXT: !18 = !{!9}
+; CHECK-NEXT: !19 = !DICompositeType(tag: DW_TAG_structure_type, name: "Derived", scope: !14, file: !10, line: 3, baseType: !15, size: 128, align: 32, offset: 64, flags: DIFlagPublic, elements: !20, runtimeLang: DW_LANG_C_plus_plus_11, vtableHolder: !15, templateParams: !18, identifier: "MangledBase")
+; CHECK-NEXT: !20 = !{!21}
+; CHECK-NEXT: !21 = !DIDerivedType(tag: DW_TAG_inheritance, scope: !19, baseType: !15)
+; CHECK-NEXT: !22 = !DIDerivedType(tag: DW_TAG_ptr_to_member_type, baseType: !6, size: 32, align: 32, extraData: !15)
+; CHECK-NEXT: !23 = !DICompositeType(tag: DW_TAG_structure_type)
+; CHECK-NEXT: !24 = !DICompositeType(tag: DW_TAG_structure_type, runtimeLang: DW_LANG_Cobol85)
+!16 = !DICompositeType(tag: DW_TAG_structure_type, name: "MyType", file: !12, line: 2, size: 32, align: 32, identifier: "MangledMyType")
+!17 = !DICompositeType(tag: DW_TAG_structure_type, name: "Base", scope: !16, file: !12, line: 3, size: 128, align: 32, offset: 64, flags: DIFlagPublic, elements: !18, runtimeLang: DW_LANG_C_plus_plus_11, vtableHolder: !17, templateParams: !20, identifier: "MangledBase")
+!18 = !{!19}
+!19 = !DIDerivedType(tag: DW_TAG_member, name: "field", scope: !17, file: !12, line: 4, baseType: !7, size: 32, align: 32, offset: 32, flags: DIFlagPublic)
+!20 = !{!11}
+!21 = !DICompositeType(tag: DW_TAG_structure_type, name: "Derived", scope: !16, file: !12, line: 3, baseType: !17, size: 128, align: 32, offset: 64, flags: DIFlagPublic, elements: !22, runtimeLang: DW_LANG_C_plus_plus_11, vtableHolder: !17, templateParams: !20, identifier: "MangledBase")
+!22 = !{!23}
+!23 = !DIDerivedType(tag: DW_TAG_inheritance, scope: !21, baseType: !17)
+!24 = !DIDerivedType(tag: DW_TAG_ptr_to_member_type, baseType: !7, size: 32, align: 32, extraData: !17)
+!25 = !DICompositeType(tag: DW_TAG_structure_type)
+!26 = !DICompositeType(tag: DW_TAG_structure_type, runtimeLang: 6)
+
+; !25 = !{!7, !7}
+; !26 = !DISubroutineType(flags: DIFlagPublic | DIFlagStaticMember, types: !25)
+; !27 = !DISubroutineType(types: !25)
+!27 = !{!7, !7}
+!28 = !DISubroutineType(flags: DIFlagPublic | DIFlagStaticMember, types: !27)
+!29 = !DISubroutineType(flags: 0, types: !27)
+!30 = !DISubroutineType(types: !27)
diff --git a/test/Assembler/drop-debug-info.ll b/test/Assembler/drop-debug-info.ll
new file mode 100644
index 000000000000..44a7b78b004d
--- /dev/null
+++ b/test/Assembler/drop-debug-info.ll
@@ -0,0 +1,29 @@
+; RUN: llvm-as < %s -o %t.bc 2>&1 >/dev/null | FileCheck -check-prefix=WARN %s
+; RUN: llvm-dis < %t.bc | FileCheck %s
+; RUN: verify-uselistorder < %t.bc
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  ret i32 0, !dbg !12
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!9}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 (trunk 195495) (llvm/trunk 195495:195504M)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "../llvm/tools/clang/test/CodeGen/debug-info-version.c", directory: "/Users/manmanren/llvm_gmail/release")
+!2 = !{i32 0}
+!3 = !{!4}
+!4 = !DISubprogram(name: "main", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !5, type: !6, function: i32 ()* @main, variables: !2)
+!5 = !DIFile(filename: "../llvm/tools/clang/test/CodeGen/debug-info-version.c", directory: "/Users/manmanren/llvm_gmail/release")
+!6 = !DISubroutineType(types: !7)
+!7 = !{!8}
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !{i32 2, !"Dwarf Version", i32 2}
+!12 = !DILocation(line: 4, scope: !4)
+
+; WARN: warning: ignoring debug info with an invalid version (0)
+; CHECK-NOT: !dbg
+; CHECK-NOT: !llvm.dbg.cu
diff --git a/test/Assembler/extractvalue-no-idx.ll b/test/Assembler/extractvalue-no-idx.ll
new file mode 100644
index 000000000000..b3132097eb10
--- /dev/null
+++ b/test/Assembler/extractvalue-no-idx.ll
@@ -0,0 +1,8 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+; CHECK: expected index
+
+define void @f1() {
+  extractvalue <{ i32, i32 }> undef, !dbg !0
+  ret void
+}
diff --git a/test/Assembler/fast-math-flags.ll b/test/Assembler/fast-math-flags.ll
index 8e75bdf0f966..f0d3ecc761d1 100644
--- a/test/Assembler/fast-math-flags.ll
+++ b/test/Assembler/fast-math-flags.ll
@@ -9,12 +9,12 @@
 
 define float @none(float %x, float %y) {
 entry:
-; CHECK:  %vec = load  <3 x float>* @vec
-  %vec    = load  <3 x float>* @vec
-; CHECK:  %select = load i1* @select
-  %select = load i1* @select
-; CHECK:  %arr    = load [3 x float]* @arr
-  %arr    = load [3 x float]* @arr
+; CHECK:  %vec = load  <3 x float>,  <3 x float>* @vec
+  %vec    = load  <3 x float>,  <3 x float>* @vec
+; CHECK:  %select = load i1, i1* @select
+  %select = load i1, i1* @select
+; CHECK:  %arr    = load [3 x float], [3 x float]* @arr
+  %arr    = load [3 x float], [3 x float]* @arr
 
 ; CHECK:  %a = fadd  float %x, %y
   %a = fadd  float %x, %y
@@ -43,12 +43,12 @@ entry:
 ; CHECK: no_nan
 define float @no_nan(float %x, float %y) {
 entry:
-; CHECK:  %vec = load <3 x float>* @vec
-  %vec    = load  <3 x float>* @vec
-; CHECK:  %select = load i1* @select
-  %select = load i1* @select
-; CHECK:  %arr = load  [3 x float]* @arr
-  %arr    = load  [3 x float]* @arr
+; CHECK:  %vec = load <3 x float>, <3 x float>* @vec
+  %vec    = load  <3 x float>,  <3 x float>* @vec
+; CHECK:  %select = load i1, i1* @select
+  %select = load i1, i1* @select
+; CHECK:  %arr = load  [3 x float],  [3 x float]* @arr
+  %arr    = load  [3 x float],  [3 x float]* @arr
 
 ; CHECK:  %a = fadd nnan  float %x, %y
   %a = fadd nnan  float %x, %y
@@ -77,12 +77,12 @@ entry:
 ; CHECK: no_nan_inf
 define float @no_nan_inf(float %x, float %y) {
 entry:
-; CHECK:  %vec = load <3 x float>* @vec
-  %vec    = load <3 x float>* @vec
-; CHECK:  %select = load i1* @select
-  %select = load i1* @select
-; CHECK:  %arr = load [3 x float]* @arr
-  %arr    = load [3 x float]* @arr
+; CHECK:  %vec = load <3 x float>, <3 x float>* @vec
+  %vec    = load <3 x float>, <3 x float>* @vec
+; CHECK:  %select = load i1, i1* @select
+  %select = load i1, i1* @select
+; CHECK:  %arr = load [3 x float], [3 x float]* @arr
+  %arr    = load [3 x float], [3 x float]* @arr
 
 ; CHECK:  %a = fadd nnan ninf  float %x, %y
   %a = fadd ninf nnan  float %x, %y
@@ -111,12 +111,12 @@ entry:
 ; CHECK: mixed_flags
 define float @mixed_flags(float %x, float %y) {
 entry:
-; CHECK:  %vec = load <3 x float>* @vec
-  %vec    = load <3 x float>* @vec
-; CHECK:  %select = load i1* @select
-  %select = load i1* @select
-; CHECK:  %arr    = load [3 x float]* @arr
-  %arr    = load [3 x float]* @arr
+; CHECK:  %vec = load <3 x float>, <3 x float>* @vec
+  %vec    = load <3 x float>, <3 x float>* @vec
+; CHECK:  %select = load i1, i1* @select
+  %select = load i1, i1* @select
+; CHECK:  %arr    = load [3 x float], [3 x float]* @arr
+  %arr    = load [3 x float], [3 x float]* @arr
 
 ; CHECK:  %a = fadd nnan ninf float %x, %y
   %a = fadd ninf nnan float %x, %y
diff --git a/test/Assembler/flags.ll b/test/Assembler/flags.ll
index e74311afd9a6..bcbfb18d65a9 100644
--- a/test/Assembler/flags.ll
+++ b/test/Assembler/flags.ll
@@ -148,14 +148,14 @@ define i64 @lshr_exact(i64 %x, i64 %y) {
 }
 
 define i64* @gep_nw(i64* %p, i64 %x) {
-; CHECK: %z = getelementptr inbounds i64* %p, i64 %x
-	%z = getelementptr inbounds i64* %p, i64 %x
+; CHECK: %z = getelementptr inbounds i64, i64* %p, i64 %x
+	%z = getelementptr inbounds i64, i64* %p, i64 %x
         ret i64* %z
 }
 
 define i64* @gep_plain(i64* %p, i64 %x) {
-; CHECK: %z = getelementptr i64* %p, i64 %x
-	%z = getelementptr i64* %p, i64 %x
+; CHECK: %z = getelementptr i64, i64* %p, i64 %x
+	%z = getelementptr i64, i64* %p, i64 %x
         ret i64* %z
 }
 
@@ -195,8 +195,8 @@ define i64 @lshr_exact_ce() {
 }
 
 define i64* @gep_nw_ce() {
-; CHECK: ret i64* getelementptr inbounds (i64* @addr, i64 171)
-        ret i64* getelementptr inbounds (i64* @addr, i64 171)
+; CHECK: ret i64* getelementptr inbounds (i64, i64* @addr, i64 171)
+        ret i64* getelementptr inbounds (i64, i64* @addr, i64 171)
 }
 
 define i64 @add_plain_ce() {
@@ -220,8 +220,8 @@ define i64 @sdiv_plain_ce() {
 }
 
 define i64* @gep_plain_ce() {
-; CHECK: ret i64* getelementptr (i64* @addr, i64 171)
-        ret i64* getelementptr (i64* @addr, i64 171)
+; CHECK: ret i64* getelementptr (i64, i64* @addr, i64 171)
+        ret i64* getelementptr (i64, i64* @addr, i64 171)
 }
 
 define i64 @add_both_reversed_ce() {
diff --git a/test/Assembler/functionlocal-metadata.ll b/test/Assembler/functionlocal-metadata.ll
deleted file mode 100644
index 517138dba5fa..000000000000
--- a/test/Assembler/functionlocal-metadata.ll
+++ /dev/null
@@ -1,55 +0,0 @@
-; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-; RUN: verify-uselistorder %s
-
-define void @Foo(i32 %a, i32 %b) {
-entry:
-  call void @llvm.dbg.value(metadata i32* %1, i64 16, metadata !2, metadata !{!"0x102"})
-; CHECK: call void @llvm.dbg.value(metadata i32* %1, i64 16, metadata ![[ID2:[0-9]+]], metadata {{.*}})
-  %0 = add i32 %a, 1                              ; <i32> [#uses=1]
-  %two = add i32 %b, %0                           ; <i32> [#uses=0]
-  %1 = alloca i32                                 ; <i32*> [#uses=1]
-
-  call void @llvm.dbg.declare(metadata i32* %1, metadata i32* %1, metadata !{!"0x102"})
-; CHECK: call void @llvm.dbg.declare(metadata i32* %1, metadata i32* %1, metadata {{.*}})
-  call void @llvm.dbg.declare(metadata i32 %two, metadata i32 %0, metadata !{!"0x102"})
-; CHECK: call void @llvm.dbg.declare(metadata i32 %two, metadata i32 %0, metadata {{.*}})
-  call void @llvm.dbg.declare(metadata i32* %1, metadata i32 %b, metadata !{!"0x102"})
-; CHECK: call void @llvm.dbg.declare(metadata i32* %1, metadata i32 %b, metadata {{.*}})
-  call void @llvm.dbg.declare(metadata i32 %a, metadata i32 %a, metadata !{!"0x102"})
-; CHECK: call void @llvm.dbg.declare(metadata i32 %a, metadata i32 %a, metadata {{.*}})
-  call void @llvm.dbg.declare(metadata i32 %b, metadata i32 %two, metadata !{!"0x102"})
-; CHECK: call void @llvm.dbg.declare(metadata i32 %b, metadata i32 %two, metadata {{.*}})
-
-  call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !1, metadata !{!"0x102"})
-; CHECK: call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata ![[ID1:[0-9]+]], metadata {{.*}})
-  call void @llvm.dbg.value(metadata i32 %0, i64 25, metadata !0, metadata !{!"0x102"})
-; CHECK: call void @llvm.dbg.value(metadata i32 %0, i64 25, metadata ![[ID0:[0-9]+]], metadata {{.*}})
-  call void @llvm.dbg.value(metadata i32* %1, i64 16, metadata !3, metadata !{!"0x102"})
-; CHECK: call void @llvm.dbg.value(metadata i32* %1, i64 16, metadata ![[ID3:[0-9]+]], metadata {{.*}})
-  call void @llvm.dbg.value(metadata !3, i64 12, metadata !2, metadata !{!"0x102"})
-; CHECK: call void @llvm.dbg.value(metadata ![[ID3]], i64 12, metadata ![[ID2]], metadata {{.*}})
-
-  ret void, !foo !0, !bar !1
-; CHECK: ret void, !foo ![[FOO:[0-9]+]], !bar ![[BAR:[0-9]+]]
-}
-
-!llvm.module.flags = !{!4}
-
-!0 = !MDLocation(line: 662302, column: 26, scope: !1)
-!1 = !{i32 4, !"foo"}
-!2 = !{!"bar"}
-!3 = !{!"foo"}
-!4 = !{i32 1, !"Debug Info Version", i32 2}
-
-declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
-declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone
-
-!foo = !{ !0 }
-!bar = !{ !1 }
-
-; CHECK: !foo = !{![[FOO]]}
-; CHECK: !bar = !{![[BAR]]}
-; CHECK: ![[ID0]] = !MDLocation(line: 662302, column: 26, scope: ![[ID1]])
-; CHECK: ![[ID1]] = !{i32 4, !"foo"}
-; CHECK: ![[ID2]] = !{!"bar"}
-; CHECK: ![[ID3]] = !{!"foo"}
diff --git a/test/Assembler/generic-debug-node.ll b/test/Assembler/generic-debug-node.ll
new file mode 100644
index 000000000000..5fb72faa18e1
--- /dev/null
+++ b/test/Assembler/generic-debug-node.ll
@@ -0,0 +1,27 @@
+; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+; CHECK: !named = !{!0, !1, !1, !2, !2, !2, !2, !3, !4, !2}
+!named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9}
+
+; CHECK: !0 = !{}
+!0 = !{}
+
+; CHECK-NEXT: !1 = !GenericDINode(tag: DW_TAG_entry_point, header: "some\00header", operands: {!0, !2, !2})
+!1 = !GenericDINode(tag: 3, header: "some\00header", operands: {!0, !3, !4})
+!2 = !GenericDINode(tag: 3, header: "some\00header", operands: {!{}, !3, !4})
+
+; CHECK-NEXT: !2 = !GenericDINode(tag: DW_TAG_entry_point)
+!3 = !GenericDINode(tag: 3)
+!4 = !GenericDINode(tag: 3, header: "")
+!5 = !GenericDINode(tag: 3, operands: {})
+!6 = !GenericDINode(tag: 3, header: "", operands: {})
+
+; CHECK-NEXT: !3 = distinct !GenericDINode(tag: DW_TAG_entry_point)
+!7 = distinct !GenericDINode(tag: 3)
+
+; CHECK-NEXT: !4 = !GenericDINode(tag: 65535)
+!8 = !GenericDINode(tag: 65535)
+
+; CHECK-NOT: !
+!9 = !GenericDINode(tag: DW_TAG_entry_point)
diff --git a/test/Assembler/getelementptr.ll b/test/Assembler/getelementptr.ll
index e938ff4ad8ce..ee88346eb00b 100644
--- a/test/Assembler/getelementptr.ll
+++ b/test/Assembler/getelementptr.ll
@@ -3,36 +3,42 @@
 
 ; Verify that over-indexed getelementptrs are folded.
 @A = external global [2 x [3 x [5 x [7 x i32]]]]
-@B = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 0, i64 0, i64 2, i64 1, i64 7523)
-; CHECK: @B = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 36, i64 0, i64 1, i64 0, i64 5)
-@C = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 3, i64 2, i64 0, i64 0, i64 7523)
-; CHECK: @C = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 39, i64 1, i64 1, i64 4, i64 5)
+@B = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]], [2 x [3 x [5 x [7 x i32]]]]* @A, i64 0, i64 0, i64 2, i64 1, i64 7523)
+; CHECK: @B = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]], [2 x [3 x [5 x [7 x i32]]]]* @A, i64 36, i64 0, i64 1, i64 0, i64 5)
+@C = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]], [2 x [3 x [5 x [7 x i32]]]]* @A, i64 3, i64 2, i64 0, i64 0, i64 7523)
+; CHECK: @C = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]], [2 x [3 x [5 x [7 x i32]]]]* @A, i64 39, i64 1, i64 1, i64 4, i64 5)
+
+; Verify that constant expression GEPs work with i84 indices.
+@D = external global [1 x i32]
+
+@E = global i32* getelementptr inbounds ([1 x i32], [1 x i32]* @D, i84 0, i64 1)
+; CHECK: @E = global i32* getelementptr inbounds ([1 x i32], [1 x i32]* @D, i84 1, i64 0)
 
 ; Verify that i16 indices work.
 @x = external global {i32, i32}
-@y = global i32* getelementptr ({ i32, i32 }* @x, i16 42, i32 0)
-; CHECK: @y = global i32* getelementptr ({ i32, i32 }* @x, i16 42, i32 0)
+@y = global i32* getelementptr ({ i32, i32 }, { i32, i32 }* @x, i16 42, i32 0)
+; CHECK: @y = global i32* getelementptr ({ i32, i32 }, { i32, i32 }* @x, i16 42, i32 0)
 
 ; See if i92 indices work too.
 define i32 *@test({i32, i32}* %t, i92 %n) {
 ; CHECK: @test
-; CHECK: %B = getelementptr { i32, i32 }* %t, i92 %n, i32 0
-  %B = getelementptr {i32, i32}* %t, i92 %n, i32 0
+; CHECK: %B = getelementptr { i32, i32 }, { i32, i32 }* %t, i92 %n, i32 0
+  %B = getelementptr {i32, i32}, {i32, i32}* %t, i92 %n, i32 0
   ret i32* %B
 }
 
 ; Verify that constant expression vector GEPs work.
 
-@z = global <2 x i32*> getelementptr (<2 x [3 x {i32, i32}]*> zeroinitializer, <2 x i32> <i32 1, i32 2>, <2 x i32> <i32 2, i32 3>, <2 x i32> <i32 1, i32 1>)
+@z = global <2 x i32*> getelementptr ([3 x {i32, i32}], <2 x [3 x {i32, i32}]*> zeroinitializer, <2 x i32> <i32 1, i32 2>, <2 x i32> <i32 2, i32 3>, <2 x i32> <i32 1, i32 1>)
 
 ; Verify that struct GEP works with a vector of pointers.
 define <2 x i32*> @test7(<2 x {i32, i32}*> %a) {
-  %w = getelementptr <2 x {i32, i32}*> %a, <2 x i32> <i32 5, i32 9>, <2 x i32> zeroinitializer
+  %w = getelementptr {i32, i32}, <2 x {i32, i32}*> %a, <2 x i32> <i32 5, i32 9>, <2 x i32> zeroinitializer
   ret <2 x i32*> %w
 }
 
 ; Verify that array GEP works with a vector of pointers.
 define <2 x i8*> @test8(<2 x [2 x i8]*> %a) {
-  %w = getelementptr <2 x  [2 x i8]*> %a, <2 x i32> <i32 0, i32 0>, <2 x i8> <i8 0, i8 1>
+  %w = getelementptr  [2 x i8], <2 x  [2 x i8]*> %a, <2 x i32> <i32 0, i32 0>, <2 x i8> <i8 0, i8 1>
   ret <2 x i8*> %w
 }
diff --git a/test/Assembler/getelementptr_invalid_ptr.ll b/test/Assembler/getelementptr_invalid_ptr.ll
new file mode 100644
index 000000000000..892292729a18
--- /dev/null
+++ b/test/Assembler/getelementptr_invalid_ptr.ll
@@ -0,0 +1,10 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+; Test the case of an invalid pointer type on a GEP
+
+; CHECK: base of getelementptr must be a pointer
+
+define i32* @foo(i32 %a) {
+  %gep = getelementptr i32, i32 %a, i32 1
+  return i32* %gep
+}
+
diff --git a/test/Assembler/getelementptr_struct.ll b/test/Assembler/getelementptr_struct.ll
index 029367223395..9ab554656ea5 100644
--- a/test/Assembler/getelementptr_struct.ll
+++ b/test/Assembler/getelementptr_struct.ll
@@ -9,7 +9,7 @@
 
 define i32* @foo(%ST* %s) {
 entry:
-  %reg = getelementptr %ST* %s, i32 1, i64 2, i32 1, i32 5, i32 13
+  %reg = getelementptr %ST, %ST* %s, i32 1, i64 2, i32 1, i32 5, i32 13
   ret i32* %reg
 }
 
diff --git a/test/Assembler/getelementptr_vec_idx1.ll b/test/Assembler/getelementptr_vec_idx1.ll
index d2479f44048a..084a31e7234e 100644
--- a/test/Assembler/getelementptr_vec_idx1.ll
+++ b/test/Assembler/getelementptr_vec_idx1.ll
@@ -5,6 +5,6 @@
 ; CHECK: getelementptr index type missmatch
 
 define i32 @test(i32* %a) {
-  %w = getelementptr i32* %a, <2 x i32> <i32 5, i32 9>
+  %w = getelementptr i32, i32* %a, <2 x i32> <i32 5, i32 9>
   ret i32 %w
 }
diff --git a/test/Assembler/getelementptr_vec_idx2.ll b/test/Assembler/getelementptr_vec_idx2.ll
index 8b71ce3095b1..638fcb8b67dd 100644
--- a/test/Assembler/getelementptr_vec_idx2.ll
+++ b/test/Assembler/getelementptr_vec_idx2.ll
@@ -5,6 +5,6 @@
 ; CHECK: getelementptr index type missmatch
 
 define <2 x i32> @test(<2 x i32*> %a) {
-  %w = getelementptr <2 x i32*> %a, i32 2
+  %w = getelementptr i32, <2 x i32*> %a, i32 2
   ret <2 x i32> %w
 }
diff --git a/test/Assembler/getelementptr_vec_idx3.ll b/test/Assembler/getelementptr_vec_idx3.ll
index 1f6c29b3ccc2..ac94459e23d4 100644
--- a/test/Assembler/getelementptr_vec_idx3.ll
+++ b/test/Assembler/getelementptr_vec_idx3.ll
@@ -5,6 +5,6 @@
 ; CHECK: getelementptr index type missmatch
 
 define <4 x i32> @test(<4 x i32>* %a) {
-  %w = getelementptr <4 x i32>* %a, <2 x i32> <i32 5, i32 9>
+  %w = getelementptr <4 x i32>, <4 x i32>* %a, <2 x i32> <i32 5, i32 9>
   ret i32 %w
 }
diff --git a/test/Assembler/getelementptr_vec_idx4.ll b/test/Assembler/getelementptr_vec_idx4.ll
new file mode 100644
index 000000000000..f270a0c7810c
--- /dev/null
+++ b/test/Assembler/getelementptr_vec_idx4.ll
@@ -0,0 +1,5 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+; CHECK: getelementptr vector index has a wrong number of elements
+
+global <2 x i32*> getelementptr ([3 x {i32, i32}], <4 x [3 x {i32, i32}]*> zeroinitializer, <2 x i32> <i32 1, i32 2>, <2 x i32> <i32 2, i32 3>, <2 x i32> <i32 1, i32 1>)
diff --git a/test/Assembler/getelementptr_vec_struct.ll b/test/Assembler/getelementptr_vec_struct.ll
index ec66836bac19..493da6686a91 100644
--- a/test/Assembler/getelementptr_vec_struct.ll
+++ b/test/Assembler/getelementptr_vec_struct.ll
@@ -5,6 +5,6 @@
 ; CHECK: invalid getelementptr indices
 
 define <2 x i32*> @test7(<2 x {i32, i32}*> %a) {
-  %w = getelementptr <2 x {i32, i32}*> %a, <2 x i32> <i32 5, i32 9>, <2 x i32> <i32 0, i32 1>
+  %w = getelementptr {i32, i32}, <2 x {i32, i32}*> %a, <2 x i32> <i32 5, i32 9>, <2 x i32> <i32 0, i32 1>
   ret <2 x i32*> %w
 }
diff --git a/test/Assembler/gv-invalid-type.ll b/test/Assembler/gv-invalid-type.ll
new file mode 100644
index 000000000000..bde04dab7a20
--- /dev/null
+++ b/test/Assembler/gv-invalid-type.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+@gv = global metadata undef
+; CHECK: invalid type for global variable
diff --git a/test/Assembler/half-constprop.ll b/test/Assembler/half-constprop.ll
index c5ae3bf16abb..7ca876b3c71f 100644
--- a/test/Assembler/half-constprop.ll
+++ b/test/Assembler/half-constprop.ll
@@ -9,8 +9,8 @@ entry:
   %.compoundliteral = alloca float, align 4
   store half 0xH4200, half* %a, align 2
   store half 0xH4B9A, half* %b, align 2
-  %tmp = load half* %a, align 2
-  %tmp1 = load half* %b, align 2
+  %tmp = load half, half* %a, align 2
+  %tmp1 = load half, half* %b, align 2
   %add = fadd half %tmp, %tmp1
 ; CHECK: 0xH4C8D
   ret half %add
diff --git a/test/Assembler/half-conv.ll b/test/Assembler/half-conv.ll
index e6f73cf71ca7..657550154af4 100644
--- a/test/Assembler/half-conv.ll
+++ b/test/Assembler/half-conv.ll
@@ -7,7 +7,7 @@ entry:
   %a = alloca half, align 2
   %.compoundliteral = alloca float, align 4
   store half 0xH4C8D, half* %a, align 2
-  %tmp = load half* %a, align 2
+  %tmp = load half, half* %a, align 2
   %conv = fpext half %tmp to float
 ; CHECK: 0x4032340000000000
   ret float %conv
diff --git a/test/Assembler/insertextractvalue.ll b/test/Assembler/insertextractvalue.ll
index 692843e9910b..71dbba371d4e 100644
--- a/test/Assembler/insertextractvalue.ll
+++ b/test/Assembler/insertextractvalue.ll
@@ -8,7 +8,7 @@
 ; CHECK-NEXT: store
 ; CHECK-NEXT: ret
 define float @foo({{i32},{float, double}}* %p) nounwind {
-  %t = load {{i32},{float, double}}* %p
+  %t = load {{i32},{float, double}}, {{i32},{float, double}}* %p
   %s = extractvalue {{i32},{float, double}} %t, 1, 0
   %r = insertvalue {{i32},{float, double}} %t, double 2.0, 1, 1
   store {{i32},{float, double}} %r, {{i32},{float, double}}* %p
diff --git a/test/Assembler/insertvalue-invalid-type-1.ll b/test/Assembler/insertvalue-invalid-type-1.ll
new file mode 100644
index 000000000000..de9b782874be
--- /dev/null
+++ b/test/Assembler/insertvalue-invalid-type-1.ll
@@ -0,0 +1,7 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+; CHECK: insertvalue operand and field disagree in type: 'i32' instead of 'i64'
+
+define <{ i32 }> @test() {
+  ret <{ i32 }> insertvalue (<{ i64 }> zeroinitializer, i32 4, 0)
+}
diff --git a/test/Assembler/insertvalue-invalid-type.ll b/test/Assembler/insertvalue-invalid-type.ll
new file mode 100644
index 000000000000..6be20e56a4f2
--- /dev/null
+++ b/test/Assembler/insertvalue-invalid-type.ll
@@ -0,0 +1,9 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+; CHECK: insertvalue operand and field disagree in type: 'i8*' instead of 'i32'
+
+define void @test() {
+entry:
+  insertvalue { i32, i32 } undef, i8* null, 0
+  ret void
+}
diff --git a/test/Assembler/invalid-datalayout14.ll b/test/Assembler/invalid-datalayout14.ll
new file mode 100644
index 000000000000..84634b52a146
--- /dev/null
+++ b/test/Assembler/invalid-datalayout14.ll
@@ -0,0 +1,3 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+target datalayout = "i64:64:16"
+; CHECK: Preferred alignment cannot be less than the ABI alignment
diff --git a/test/Assembler/invalid-datalayout15.ll b/test/Assembler/invalid-datalayout15.ll
new file mode 100644
index 000000000000..ea240b73fd25
--- /dev/null
+++ b/test/Assembler/invalid-datalayout15.ll
@@ -0,0 +1,3 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+target datalayout = "i64:16:16777216"
+; CHECK: Invalid preferred alignment, must be a 16bit integer
diff --git a/test/Assembler/invalid-datalayout16.ll b/test/Assembler/invalid-datalayout16.ll
new file mode 100644
index 000000000000..0dd1abb629b6
--- /dev/null
+++ b/test/Assembler/invalid-datalayout16.ll
@@ -0,0 +1,3 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+target datalayout = "i64:16777216:16777216"
+; CHECK: Invalid ABI alignment, must be a 16bit integer
diff --git a/test/Assembler/invalid-datalayout17.ll b/test/Assembler/invalid-datalayout17.ll
new file mode 100644
index 000000000000..519f5c10ab3c
--- /dev/null
+++ b/test/Assembler/invalid-datalayout17.ll
@@ -0,0 +1,3 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+target datalayout = "i16777216:16:16"
+; CHECK: Invalid bit width, must be a 24bit integer
diff --git a/test/Assembler/invalid-datalayout18.ll b/test/Assembler/invalid-datalayout18.ll
new file mode 100644
index 000000000000..b9956f98c9c6
--- /dev/null
+++ b/test/Assembler/invalid-datalayout18.ll
@@ -0,0 +1,3 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+target datalayout = "p:32:32:16"
+; CHECK: Preferred alignment cannot be less than the ABI alignment
diff --git a/test/Assembler/invalid-datalayout19.ll b/test/Assembler/invalid-datalayout19.ll
new file mode 100644
index 000000000000..fc0fc4685209
--- /dev/null
+++ b/test/Assembler/invalid-datalayout19.ll
@@ -0,0 +1,6 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+target datalayout = "p:0:32:32"
+
+; CHECK: Invalid pointer size of 0 bytes
+
diff --git a/test/Assembler/invalid-datalayout20.ll b/test/Assembler/invalid-datalayout20.ll
new file mode 100644
index 000000000000..a9ac1d7fe098
--- /dev/null
+++ b/test/Assembler/invalid-datalayout20.ll
@@ -0,0 +1,6 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+target datalayout = "p:64:24:64"
+
+; CHECK: Pointer ABI alignment must be a power of 2
+
diff --git a/test/Assembler/invalid-datalayout21.ll b/test/Assembler/invalid-datalayout21.ll
new file mode 100644
index 000000000000..a39d1d7a14a8
--- /dev/null
+++ b/test/Assembler/invalid-datalayout21.ll
@@ -0,0 +1,6 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+target datalayout = "p:64:64:24"
+
+; CHECK: Pointer preferred alignment must be a power of 2
+
diff --git a/test/Assembler/invalid-datalayout22.ll b/test/Assembler/invalid-datalayout22.ll
new file mode 100644
index 000000000000..14e4c2822ce4
--- /dev/null
+++ b/test/Assembler/invalid-datalayout22.ll
@@ -0,0 +1,6 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+target datalayout = "v128:0:128"
+
+; CHECK: ABI alignment specification must be >0 for non-aggregate types
+
diff --git a/test/Assembler/invalid-datalayout23.ll b/test/Assembler/invalid-datalayout23.ll
new file mode 100644
index 000000000000..430326327bc1
--- /dev/null
+++ b/test/Assembler/invalid-datalayout23.ll
@@ -0,0 +1,6 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+target datalayout = "i32:24:32"
+
+; CHECK: Invalid ABI alignment, must be a power of 2
+
diff --git a/test/Assembler/invalid-datalayout24.ll b/test/Assembler/invalid-datalayout24.ll
new file mode 100644
index 000000000000..616ec64518a5
--- /dev/null
+++ b/test/Assembler/invalid-datalayout24.ll
@@ -0,0 +1,6 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+target datalayout = "i32:32:24"
+
+; CHECK: Invalid preferred alignment, must be a power of 2
+
diff --git a/test/Assembler/invalid-debug-info-version.ll b/test/Assembler/invalid-debug-info-version.ll
new file mode 100644
index 000000000000..94a81538562d
--- /dev/null
+++ b/test/Assembler/invalid-debug-info-version.ll
@@ -0,0 +1,5 @@
+; RUN: opt < %s -S | FileCheck %s
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"Debug Info Version", !""}
+; CHECK: !{i32 1, !"Debug Info Version", !""}
diff --git a/test/Assembler/invalid-generic-debug-node-tag-bad.ll b/test/Assembler/invalid-generic-debug-node-tag-bad.ll
new file mode 100644
index 000000000000..8da140f33cee
--- /dev/null
+++ b/test/Assembler/invalid-generic-debug-node-tag-bad.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:26: error: invalid DWARF tag 'DW_TAG_badtag'
+!0 = !GenericDINode(tag: DW_TAG_badtag)
diff --git a/test/Assembler/invalid-generic-debug-node-tag-missing.ll b/test/Assembler/invalid-generic-debug-node-tag-missing.ll
new file mode 100644
index 000000000000..0ae2c7194a7a
--- /dev/null
+++ b/test/Assembler/invalid-generic-debug-node-tag-missing.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:44: error: missing required field 'tag'
+!0 = !GenericDINode(header: "some\00header")
diff --git a/test/Assembler/invalid-generic-debug-node-tag-overflow.ll b/test/Assembler/invalid-generic-debug-node-tag-overflow.ll
new file mode 100644
index 000000000000..1349dc0a2e2e
--- /dev/null
+++ b/test/Assembler/invalid-generic-debug-node-tag-overflow.ll
@@ -0,0 +1,7 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK-NOT: error:
+!0 = !GenericDINode(tag: 65535)
+
+; CHECK: <stdin>:[[@LINE+1]]:26: error: value for 'tag' too large, limit is 65535
+!1 = !GenericDINode(tag: 65536)
diff --git a/test/Assembler/invalid-generic-debug-node-tag-wrong-type.ll b/test/Assembler/invalid-generic-debug-node-tag-wrong-type.ll
new file mode 100644
index 000000000000..7d0c04af9148
--- /dev/null
+++ b/test/Assembler/invalid-generic-debug-node-tag-wrong-type.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:26: error: expected DWARF tag
+!0 = !GenericDINode(tag: "string")
diff --git a/test/Assembler/invalid-gep-mismatched-explicit-type.ll b/test/Assembler/invalid-gep-mismatched-explicit-type.ll
new file mode 100644
index 000000000000..1fc88dd43cb3
--- /dev/null
+++ b/test/Assembler/invalid-gep-mismatched-explicit-type.ll
@@ -0,0 +1,6 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+; CHECK: <stdin>:4:22: error: explicit pointee type doesn't match operand's pointee type
+define void @test(i32* %t) {
+  %x = getelementptr i16, i32* %t, i32 0
+  ret void
+}
diff --git a/test/Assembler/invalid-gep-missing-explicit-type.ll b/test/Assembler/invalid-gep-missing-explicit-type.ll
new file mode 100644
index 000000000000..6f7281abb951
--- /dev/null
+++ b/test/Assembler/invalid-gep-missing-explicit-type.ll
@@ -0,0 +1,7 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+; CHECK: <stdin>:4:27: error: expected comma after getelementptr's type
+define void @test(i32* %t) {
+  %x = getelementptr i32* %t, i32 0
+  ret void
+}
+
diff --git a/test/Assembler/invalid-label.ll b/test/Assembler/invalid-label.ll
new file mode 100644
index 000000000000..33dc63610aae
--- /dev/null
+++ b/test/Assembler/invalid-label.ll
@@ -0,0 +1,11 @@
+; RUN: not llvm-as < %s >/dev/null 2> %t
+; RUN: FileCheck %s < %t
+; Test the case where an invalid label name is used
+
+; CHECK: unable to create block named 'bb'
+
+define void @test(label %bb) {
+bb:
+  ret void
+}
+
diff --git a/test/Assembler/invalid-landingpad.ll b/test/Assembler/invalid-landingpad.ll
new file mode 100644
index 000000000000..c8eab4ac6aef
--- /dev/null
+++ b/test/Assembler/invalid-landingpad.ll
@@ -0,0 +1,7 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+; CHECK: clause argument must be a constant
+
+define void @test(i32 %in) {
+  landingpad {} personality void()* null filter i32 %in
+}
diff --git a/test/Assembler/invalid-load-mismatched-explicit-type.ll b/test/Assembler/invalid-load-mismatched-explicit-type.ll
new file mode 100644
index 000000000000..b8422ed730f2
--- /dev/null
+++ b/test/Assembler/invalid-load-mismatched-explicit-type.ll
@@ -0,0 +1,6 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+; CHECK: <stdin>:4:13: error: explicit pointee type doesn't match operand's pointee type
+define void @test(i32* %t) {
+  %x = load i16, i32* %t
+  ret void
+}
diff --git a/test/Assembler/invalid-load-missing-explicit-type.ll b/test/Assembler/invalid-load-missing-explicit-type.ll
new file mode 100644
index 000000000000..455498e3d15d
--- /dev/null
+++ b/test/Assembler/invalid-load-missing-explicit-type.ll
@@ -0,0 +1,6 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+; CHECK: <stdin>:4:18: error: expected comma after load's type
+define void @test(i32* %t) {
+  %x = load i32* %t
+  ret void
+}
diff --git a/test/Assembler/invalid-mdcompileunit-language-bad.ll b/test/Assembler/invalid-mdcompileunit-language-bad.ll
new file mode 100644
index 000000000000..e6f49f3fba47
--- /dev/null
+++ b/test/Assembler/invalid-mdcompileunit-language-bad.ll
@@ -0,0 +1,5 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:31: error: invalid DWARF language 'DW_LANG_NoSuchLanguage'
+!0 = !DICompileUnit(language: DW_LANG_NoSuchLanguage,
+                    file: !DIFile(filename: "a", directory: "b"))
diff --git a/test/Assembler/invalid-mdcompileunit-language-overflow.ll b/test/Assembler/invalid-mdcompileunit-language-overflow.ll
new file mode 100644
index 000000000000..c558f7aaa258
--- /dev/null
+++ b/test/Assembler/invalid-mdcompileunit-language-overflow.ll
@@ -0,0 +1,9 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK-NOT: error:
+!0 = !DICompileUnit(language: 65535,
+                    file: !DIFile(filename: "a", directory: "b"))
+
+; CHECK: <stdin>:[[@LINE+1]]:31: error: value for 'language' too large, limit is 65535
+!1 = !DICompileUnit(language: 65536,
+                    file: !DIFile(filename: "a", directory: "b"))
diff --git a/test/Assembler/invalid-mdcompileunit-missing-language.ll b/test/Assembler/invalid-mdcompileunit-missing-language.ll
new file mode 100644
index 000000000000..15631b7f640b
--- /dev/null
+++ b/test/Assembler/invalid-mdcompileunit-missing-language.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:65: error: missing required field 'language'
+!0 = !DICompileUnit(file: !DIFile(filename: "a", directory: "b"))
diff --git a/test/Assembler/invalid-mdcompileunit-null-file.ll b/test/Assembler/invalid-mdcompileunit-null-file.ll
new file mode 100644
index 000000000000..cc1892e91465
--- /dev/null
+++ b/test/Assembler/invalid-mdcompileunit-null-file.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:27: error: 'file' cannot be null
+!0 = !DICompileUnit(file: null)
diff --git a/test/Assembler/invalid-mdcompositetype-missing-tag.ll b/test/Assembler/invalid-mdcompositetype-missing-tag.ll
new file mode 100644
index 000000000000..e68c01479902
--- /dev/null
+++ b/test/Assembler/invalid-mdcompositetype-missing-tag.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:36: error: missing required field 'tag'
+!25 = !DICompositeType(name: "Type")
diff --git a/test/Assembler/invalid-mdderivedtype-missing-basetype.ll b/test/Assembler/invalid-mdderivedtype-missing-basetype.ll
new file mode 100644
index 000000000000..308c2ea90ef1
--- /dev/null
+++ b/test/Assembler/invalid-mdderivedtype-missing-basetype.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:45: error: missing required field 'baseType'
+!0 = !DIDerivedType(tag: DW_TAG_pointer_type)
diff --git a/test/Assembler/invalid-mdderivedtype-missing-tag.ll b/test/Assembler/invalid-mdderivedtype-missing-tag.ll
new file mode 100644
index 000000000000..fd286f4c2960
--- /dev/null
+++ b/test/Assembler/invalid-mdderivedtype-missing-tag.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:34: error: missing required field 'tag'
+!0 = !DIDerivedType(baseType: !{})
diff --git a/test/Assembler/invalid-mdenumerator-missing-name.ll b/test/Assembler/invalid-mdenumerator-missing-name.ll
new file mode 100644
index 000000000000..656d3439ba22
--- /dev/null
+++ b/test/Assembler/invalid-mdenumerator-missing-name.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:28: error: missing required field 'name'
+!0 = !DIEnumerator(value: 7)
diff --git a/test/Assembler/invalid-mdenumerator-missing-value.ll b/test/Assembler/invalid-mdenumerator-missing-value.ll
new file mode 100644
index 000000000000..0eee3be41b6a
--- /dev/null
+++ b/test/Assembler/invalid-mdenumerator-missing-value.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:32: error: missing required field 'value'
+!0 = !DIEnumerator(name: "name")
diff --git a/test/Assembler/invalid-mdexpression-large.ll b/test/Assembler/invalid-mdexpression-large.ll
new file mode 100644
index 000000000000..32b77ee51387
--- /dev/null
+++ b/test/Assembler/invalid-mdexpression-large.ll
@@ -0,0 +1,7 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK-NOT: error:
+!0 = !DIExpression(18446744073709551615)
+
+; CHECK: <stdin>:[[@LINE+1]]:20: error: element too large, limit is 18446744073709551615
+!1 = !DIExpression(18446744073709551616)
diff --git a/test/Assembler/invalid-mdexpression-verify.ll b/test/Assembler/invalid-mdexpression-verify.ll
new file mode 100644
index 000000000000..50d6943dead8
--- /dev/null
+++ b/test/Assembler/invalid-mdexpression-verify.ll
@@ -0,0 +1,9 @@
+; RUN: not llvm-as -disable-output < %s 2>&1 | FileCheck -check-prefix VERIFY %s
+; RUN: llvm-as -disable-verify < %s | llvm-dis | FileCheck -check-prefix NOVERIFY %s
+
+; NOVERIFY: !named = !{!0}
+!named = !{!0}
+
+; NOVERIFY: !0 = !DIExpression(0, 1, 9, 7, 2)
+; VERIFY: assembly parsed, but does not verify
+!0 = !DIExpression(0, 1, 9, 7, 2)
diff --git a/test/Assembler/invalid-mdfile-missing-directory.ll b/test/Assembler/invalid-mdfile-missing-directory.ll
new file mode 100644
index 000000000000..a54a22f2e189
--- /dev/null
+++ b/test/Assembler/invalid-mdfile-missing-directory.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:30: error: missing required field 'directory'
+!0 = !DIFile(filename: "file")
diff --git a/test/Assembler/invalid-mdfile-missing-filename.ll b/test/Assembler/invalid-mdfile-missing-filename.ll
new file mode 100644
index 000000000000..17bf3da3f7a3
--- /dev/null
+++ b/test/Assembler/invalid-mdfile-missing-filename.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:30: error: missing required field 'filename'
+!0 = !DIFile(directory: "dir")
diff --git a/test/Assembler/invalid-mdglobalvariable-empty-name.ll b/test/Assembler/invalid-mdglobalvariable-empty-name.ll
new file mode 100644
index 000000000000..a4e69f3c8b75
--- /dev/null
+++ b/test/Assembler/invalid-mdglobalvariable-empty-name.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:30: error: 'name' cannot be empty
+!0 = !DIGlobalVariable(name: "")
diff --git a/test/Assembler/invalid-mdglobalvariable-missing-name.ll b/test/Assembler/invalid-mdglobalvariable-missing-name.ll
new file mode 100644
index 000000000000..baf4d73d94f4
--- /dev/null
+++ b/test/Assembler/invalid-mdglobalvariable-missing-name.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:24: error: missing required field 'name'
+!0 = !DIGlobalVariable()
diff --git a/test/Assembler/invalid-mdimportedentity-missing-scope.ll b/test/Assembler/invalid-mdimportedentity-missing-scope.ll
new file mode 100644
index 000000000000..06164e88d9b3
--- /dev/null
+++ b/test/Assembler/invalid-mdimportedentity-missing-scope.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:51: error: missing required field 'scope'
+!3 = !DIImportedEntity(tag: DW_TAG_imported_module)
diff --git a/test/Assembler/invalid-mdimportedentity-missing-tag.ll b/test/Assembler/invalid-mdimportedentity-missing-tag.ll
new file mode 100644
index 000000000000..996b1ffdc9bf
--- /dev/null
+++ b/test/Assembler/invalid-mdimportedentity-missing-tag.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:33: error: missing required field 'tag'
+!3 = !DIImportedEntity(scope: !0)
diff --git a/test/Assembler/invalid-mdlexicalblock-missing-scope.ll b/test/Assembler/invalid-mdlexicalblock-missing-scope.ll
new file mode 100644
index 000000000000..6108e692b21c
--- /dev/null
+++ b/test/Assembler/invalid-mdlexicalblock-missing-scope.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:29: error: missing required field 'scope'
+!0 = !DILexicalBlock(line: 7)
diff --git a/test/Assembler/invalid-mdlexicalblock-null-scope.ll b/test/Assembler/invalid-mdlexicalblock-null-scope.ll
new file mode 100644
index 000000000000..7457b6085d61
--- /dev/null
+++ b/test/Assembler/invalid-mdlexicalblock-null-scope.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:29: error: 'scope' cannot be null
+!0 = !DILexicalBlock(scope: null)
diff --git a/test/Assembler/invalid-mdlexicalblockfile-missing-discriminator.ll b/test/Assembler/invalid-mdlexicalblockfile-missing-discriminator.ll
new file mode 100644
index 000000000000..bd8395ccf4df
--- /dev/null
+++ b/test/Assembler/invalid-mdlexicalblockfile-missing-discriminator.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:36: error: missing required field 'discriminator'
+!0 = !DILexicalBlockFile(scope: !{})
diff --git a/test/Assembler/invalid-mdlexicalblockfile-missing-scope.ll b/test/Assembler/invalid-mdlexicalblockfile-missing-scope.ll
new file mode 100644
index 000000000000..fd037501c40a
--- /dev/null
+++ b/test/Assembler/invalid-mdlexicalblockfile-missing-scope.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:42: error: missing required field 'scope'
+!0 = !DILexicalBlockFile(discriminator: 0)
diff --git a/test/Assembler/invalid-mdlexicalblockfile-null-scope.ll b/test/Assembler/invalid-mdlexicalblockfile-null-scope.ll
new file mode 100644
index 000000000000..ae1a5d432e3d
--- /dev/null
+++ b/test/Assembler/invalid-mdlexicalblockfile-null-scope.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:33: error: 'scope' cannot be null
+!0 = !DILexicalBlockFile(scope: null)
diff --git a/test/Assembler/invalid-mdlocalvariable-missing-scope.ll b/test/Assembler/invalid-mdlocalvariable-missing-scope.ll
new file mode 100644
index 000000000000..45dcad713609
--- /dev/null
+++ b/test/Assembler/invalid-mdlocalvariable-missing-scope.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:48: error: missing required field 'scope'
+!0 = !DILocalVariable(tag: DW_TAG_auto_variable)
diff --git a/test/Assembler/invalid-mdlocalvariable-missing-tag.ll b/test/Assembler/invalid-mdlocalvariable-missing-tag.ll
new file mode 100644
index 000000000000..18062edf75bd
--- /dev/null
+++ b/test/Assembler/invalid-mdlocalvariable-missing-tag.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:45: error: missing required field 'tag'
+!0 = !DILocalVariable(scope: !DISubprogram())
diff --git a/test/Assembler/invalid-mdlocalvariable-null-scope.ll b/test/Assembler/invalid-mdlocalvariable-null-scope.ll
new file mode 100644
index 000000000000..859412a2568c
--- /dev/null
+++ b/test/Assembler/invalid-mdlocalvariable-null-scope.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:30: error: 'scope' cannot be null
+!0 = !DILocalVariable(scope: null)
diff --git a/test/Assembler/invalid-mdlocation-field-bad.ll b/test/Assembler/invalid-mdlocation-field-bad.ll
index 6ec7c64bb4d0..e68aa45b03eb 100644
--- a/test/Assembler/invalid-mdlocation-field-bad.ll
+++ b/test/Assembler/invalid-mdlocation-field-bad.ll
@@ -1,4 +1,4 @@
 ; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
 
 ; CHECK: <stdin>:[[@LINE+1]]:18: error: invalid field 'bad'
-!0 = !MDLocation(bad: 0)
+!0 = !DILocation(bad: 0)
diff --git a/test/Assembler/invalid-mdlocation-field-twice.ll b/test/Assembler/invalid-mdlocation-field-twice.ll
index 2335c935a5f4..d1dab68246c1 100644
--- a/test/Assembler/invalid-mdlocation-field-twice.ll
+++ b/test/Assembler/invalid-mdlocation-field-twice.ll
@@ -3,4 +3,4 @@
 !0 = !{}
 
 ; CHECK: <stdin>:[[@LINE+1]]:38: error: field 'line' cannot be specified more than once
-!1 = !MDLocation(line: 3, scope: !0, line: 3)
+!1 = !DILocation(line: 3, scope: !0, line: 3)
diff --git a/test/Assembler/invalid-mdlocation-missing-scope-2.ll b/test/Assembler/invalid-mdlocation-missing-scope-2.ll
new file mode 100644
index 000000000000..380e3fde94f6
--- /dev/null
+++ b/test/Assembler/invalid-mdlocation-missing-scope-2.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:25: error: missing required field 'scope'
+!0 = !DILocation(line: 7)
diff --git a/test/Assembler/invalid-mdlocation-missing-scope.ll b/test/Assembler/invalid-mdlocation-missing-scope.ll
new file mode 100644
index 000000000000..fb0cd866dc16
--- /dev/null
+++ b/test/Assembler/invalid-mdlocation-missing-scope.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:18: error: missing required field 'scope'
+!0 = !DILocation()
diff --git a/test/Assembler/invalid-mdlocation-null-scope.ll b/test/Assembler/invalid-mdlocation-null-scope.ll
new file mode 100644
index 000000000000..38c59e15d15a
--- /dev/null
+++ b/test/Assembler/invalid-mdlocation-null-scope.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: <stdin>:[[@LINE+1]]:25: error: 'scope' cannot be null
+!0 = !DILocation(scope: null)
diff --git a/test/Assembler/invalid-mdlocation-overflow-column.ll b/test/Assembler/invalid-mdlocation-overflow-column.ll
index d1dbb27173dc..043f84d3ab21 100644
--- a/test/Assembler/invalid-mdlocation-overflow-column.ll
+++ b/test/Assembler/invalid-mdlocation-overflow-column.ll
@@ -2,8 +2,8 @@
 
 !0 = !{}
 
-; CHECK-NOT: error
-!1 = !MDLocation(column: 255, scope: !0)
+; CHECK-NOT: error:
+!1 = !DILocation(column: 65535, scope: !0)
 
-; CHECK: <stdin>:[[@LINE+1]]:26: error: value for 'column' too large, limit is 255
-!2 = !MDLocation(column: 256, scope: !0)
+; CHECK: <stdin>:[[@LINE+1]]:26: error: value for 'column' too large, limit is 65535
+!2 = !DILocation(column: 65536, scope: !0)
diff --git a/test/Assembler/invalid-mdlocation-overflow-line.ll b/test/Assembler/invalid-mdlocation-overflow-line.ll
index 8e19f6919bf9..7a6774231a97 100644
--- a/test/Assembler/invalid-mdlocation-overflow-line.ll
+++ b/test/Assembler/invalid-mdlocation-overflow-line.ll
@@ -2,8 +2,8 @@
 
 !0 = !{}
 
-; CHECK-NOT: error
-!1 = !MDLocation(line: 16777215, scope: !0)
+; CHECK-NOT: error:
+!1 = !DILocation(line: 4294967295, scope: !0)
 
-; CHECK: <stdin>:[[@LINE+1]]:24: error: value for 'line' too large, limit is 16777215
-!2 = !MDLocation(line: 16777216, scope: !0)
+; CHECK: <stdin>:[[@LINE+1]]:24: error: value for 'line' too large, limit is 4294967295
+!2 = !DILocation(line: 4294967296, scope: !0)
diff --git a/test/Assembler/invalid-mdnamespace-missing-namespace.ll b/test/Assembler/invalid-mdnamespace-missing-namespace.ll
new file mode 100644
index 000000000000..c29391b125d7
--- /dev/null
+++ b/test/Assembler/invalid-mdnamespace-missing-namespace.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:36: error: missing required field 'scope'
+!0 = !DINamespace(name: "Namespace")
diff --git a/test/Assembler/invalid-mdnode-badref.ll b/test/Assembler/invalid-mdnode-badref.ll
new file mode 100644
index 000000000000..cfa03e0b3c6a
--- /dev/null
+++ b/test/Assembler/invalid-mdnode-badref.ll
@@ -0,0 +1,5 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+!named = !{!0}
+
+; CHECK: [[@LINE+1]]:14: error: use of undefined metadata '!1'
+!0 = !{!0, !1}
diff --git a/test/Assembler/invalid-mdsubrange-count-large.ll b/test/Assembler/invalid-mdsubrange-count-large.ll
new file mode 100644
index 000000000000..003274f3a072
--- /dev/null
+++ b/test/Assembler/invalid-mdsubrange-count-large.ll
@@ -0,0 +1,7 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK-NOT: error:
+!0 = !DISubrange(count: 9223372036854775807)
+
+; CHECK: <stdin>:[[@LINE+1]]:25: error: value for 'count' too large, limit is 9223372036854775807
+!1 = !DISubrange(count: 9223372036854775808)
diff --git a/test/Assembler/invalid-mdsubrange-count-missing.ll b/test/Assembler/invalid-mdsubrange-count-missing.ll
new file mode 100644
index 000000000000..8fc4487117f6
--- /dev/null
+++ b/test/Assembler/invalid-mdsubrange-count-missing.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:32: error: missing required field 'count'
+!0 = !DISubrange(lowerBound: -3)
diff --git a/test/Assembler/invalid-mdsubrange-count-negative.ll b/test/Assembler/invalid-mdsubrange-count-negative.ll
new file mode 100644
index 000000000000..f2ad4c302cb2
--- /dev/null
+++ b/test/Assembler/invalid-mdsubrange-count-negative.ll
@@ -0,0 +1,7 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK-NOT: error:
+!0 = !DISubrange(count: -1)
+
+; CHECK: <stdin>:[[@LINE+1]]:25: error: value for 'count' too small, limit is -1
+!0 = !DISubrange(count: -2)
diff --git a/test/Assembler/invalid-mdsubrange-lowerBound-max.ll b/test/Assembler/invalid-mdsubrange-lowerBound-max.ll
new file mode 100644
index 000000000000..e163dc47804d
--- /dev/null
+++ b/test/Assembler/invalid-mdsubrange-lowerBound-max.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:41: error: value for 'lowerBound' too large, limit is 9223372036854775807
+!0 = !DISubrange(count: 30, lowerBound: 9223372036854775808)
diff --git a/test/Assembler/invalid-mdsubrange-lowerBound-min.ll b/test/Assembler/invalid-mdsubrange-lowerBound-min.ll
new file mode 100644
index 000000000000..1dc3a141a576
--- /dev/null
+++ b/test/Assembler/invalid-mdsubrange-lowerBound-min.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:41: error: value for 'lowerBound' too small, limit is -9223372036854775808
+!0 = !DISubrange(count: 30, lowerBound: -9223372036854775809)
diff --git a/test/Assembler/invalid-mdsubroutinetype-missing-types.ll b/test/Assembler/invalid-mdsubroutinetype-missing-types.ll
new file mode 100644
index 000000000000..086e5cc593ec
--- /dev/null
+++ b/test/Assembler/invalid-mdsubroutinetype-missing-types.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:65: error: missing required field 'types'
+!29 = !DISubroutineType(flags: DIFlagPublic | DIFlagStaticMember)
diff --git a/test/Assembler/invalid-mdtemplatetypeparameter-missing-type.ll b/test/Assembler/invalid-mdtemplatetypeparameter-missing-type.ll
new file mode 100644
index 000000000000..797abd2c3044
--- /dev/null
+++ b/test/Assembler/invalid-mdtemplatetypeparameter-missing-type.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+1]]:44: error: missing required field 'type'
+!0 = !DITemplateTypeParameter(name: "param")
diff --git a/test/Assembler/invalid-mdtemplatevalueparameter-missing-value.ll b/test/Assembler/invalid-mdtemplatevalueparameter-missing-value.ll
new file mode 100644
index 000000000000..883bea1c9ad2
--- /dev/null
+++ b/test/Assembler/invalid-mdtemplatevalueparameter-missing-value.ll
@@ -0,0 +1,5 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK: [[@LINE+2]]:41: error: missing required field 'value'
+!0 = !DITemplateValueParameter(tag: DW_TAG_template_value_parameter,
+                               type: !{})
diff --git a/test/Assembler/invalid_cast4.ll b/test/Assembler/invalid_cast4.ll
new file mode 100644
index 000000000000..7056f8400350
--- /dev/null
+++ b/test/Assembler/invalid_cast4.ll
@@ -0,0 +1,4 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+; CHECK: invalid cast opcode for cast from 'i64' to 'i64'
+global i64* inttoptr (i64 0 to i64)
diff --git a/test/Assembler/large-comdat.ll b/test/Assembler/large-comdat.ll
new file mode 100644
index 000000000000..cab164f10b07
--- /dev/null
+++ b/test/Assembler/large-comdat.ll
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+
+$_ZSt9make_pairIN4llvm16DenseMapIteratorINS0_14PointerIntPairIPKNS0_5ValueELj1ENS0_21PointerLikeTypeTraitsIS5_EEEENS0_19NonLocalPointerInfoENS0_12DenseMapInfoIS8_EENS0_12DenseMapPairIS9_EEEEbESt4pairINSt17__decay_and_stripIT_E6__typeENSG_IT0_E6__typeEESH_SK_ = comdat any
+
+; CHECK: $_ZSt9make_pairIN4llvm16DenseMapIteratorINS0_14PointerIntPairIPKNS0_5ValueELj1ENS0_21PointerLikeTypeTraitsIS5_EEEENS0_19NonLocalPointerInfoENS0_12DenseMapInfoIS8_EENS0_12DenseMapPairIS9_EEEEbESt4pairINSt17__decay_and_stripIT_E6__typeENSG_IT0_E6__typeEESH_SK_ = comdat any
+
+define void @_ZSt9make_pairIN4llvm16DenseMapIteratorINS0_14PointerIntPairIPKNS0_5ValueELj1ENS0_21PointerLikeTypeTraitsIS5_EEEENS0_19NonLocalPointerInfoENS0_12DenseMapInfoIS8_EENS0_12DenseMapPairIS9_EEEEbESt4pairINSt17__decay_and_stripIT_E6__typeENSG_IT0_E6__typeEESH_SK_() comdat {
+  ret void
+}
diff --git a/test/Assembler/mdcompileunit.ll b/test/Assembler/mdcompileunit.ll
new file mode 100644
index 000000000000..dc136f0b83e9
--- /dev/null
+++ b/test/Assembler/mdcompileunit.ll
@@ -0,0 +1,31 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+; CHECK: !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !7, !8, !8}
+!named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9, !10}
+
+!0 = distinct !{}
+!1 = !DIFile(filename: "path/to/file", directory: "/path/to/dir")
+!2 = distinct !{}
+!3 = distinct !{}
+!4 = distinct !{}
+!5 = distinct !{}
+!6 = distinct !{}
+
+; CHECK: !7 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", isOptimized: true, flags: "-O2", runtimeVersion: 2, splitDebugFilename: "abc.debug", emissionKind: 3, enums: !2, retainedTypes: !3, subprograms: !4, globals: !5, imports: !6, dwoId: 42)
+!7 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang",
+                    isOptimized: true, flags: "-O2", runtimeVersion: 2,
+                    splitDebugFilename: "abc.debug", emissionKind: 3,
+                    enums: !2, retainedTypes: !3, subprograms: !4,
+                    globals: !5, imports: !6, dwoId: 42)
+!8 = !DICompileUnit(language: 12, file: !1, producer: "clang",
+                    isOptimized: true, flags: "-O2", runtimeVersion: 2,
+                    splitDebugFilename: "abc.debug", emissionKind: 3,
+                    enums: !2, retainedTypes: !3, subprograms: !4,
+                    globals: !5, imports: !6, dwoId: 42)
+
+; CHECK: !8 = !DICompileUnit(language: DW_LANG_C99, file: !1, isOptimized: false, runtimeVersion: 0, emissionKind: 0)
+!9 = !DICompileUnit(language: 12, file: !1, producer: "",
+                    isOptimized: false, flags: "", runtimeVersion: 0,
+                    splitDebugFilename: "", emissionKind: 0)
+!10 = !DICompileUnit(language: 12, file: !1)
diff --git a/test/Assembler/mdexpression.ll b/test/Assembler/mdexpression.ll
new file mode 100644
index 000000000000..31be86cef2d4
--- /dev/null
+++ b/test/Assembler/mdexpression.ll
@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+; CHECK: !named = !{!0, !1, !2, !3, !4}
+!named = !{!0, !1, !2, !3, !4}
+
+; CHECK:      !0 = !DIExpression()
+; CHECK-NEXT: !1 = !DIExpression(DW_OP_deref)
+; CHECK-NEXT: !2 = !DIExpression(DW_OP_plus, 3)
+; CHECK-NEXT: !3 = !DIExpression(DW_OP_bit_piece, 3, 7)
+; CHECK-NEXT: !4 = !DIExpression(DW_OP_deref, DW_OP_plus, 3, DW_OP_bit_piece, 3, 7)
+!0 = !DIExpression()
+!1 = !DIExpression(DW_OP_deref)
+!2 = !DIExpression(DW_OP_plus, 3)
+!3 = !DIExpression(DW_OP_bit_piece, 3, 7)
+!4 = !DIExpression(DW_OP_deref, DW_OP_plus, 3, DW_OP_bit_piece, 3, 7)
diff --git a/test/Assembler/mdfile-escaped-chars.ll b/test/Assembler/mdfile-escaped-chars.ll
new file mode 100644
index 000000000000..5900fdca061d
--- /dev/null
+++ b/test/Assembler/mdfile-escaped-chars.ll
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+; Spot-check that metadata string fields are correctly escaped.
+
+!named = !{!0}
+
+; CHECK: !0 = !DIFile(filename: "\00\01\02\80\81\82\FD\FE\FF", directory: "/dir")
+!0 = !DIFile(filename: "\00\01\02\80\81\82\FD\FE\FF", directory: "/dir")
diff --git a/test/Assembler/mdglobalvariable.ll b/test/Assembler/mdglobalvariable.ll
new file mode 100644
index 000000000000..0d027d310f6d
--- /dev/null
+++ b/test/Assembler/mdglobalvariable.ll
@@ -0,0 +1,27 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+@foo = global i32 0
+
+; CHECK: !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9}
+!named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9}
+
+!0 = !DIFile(filename: "scope.h", directory: "/path/to/dir")
+!1 = distinct !{}
+!2 = !DIFile(filename: "path/to/file", directory: "/path/to/dir")
+!3 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!4 = distinct !{}
+
+; CHECK: !5 = !DIGlobalVariable(name: "foo", linkageName: "foo", scope: !0, file: !2, line: 7, type: !3, isLocal: true, isDefinition: false, variable: i32* @foo)
+!5 = !DIGlobalVariable(name: "foo", linkageName: "foo", scope: !0,
+                       file: !2, line: 7, type: !3, isLocal: true,
+                       isDefinition: false, variable: i32* @foo)
+
+; CHECK: !6 = !DIGlobalVariable(name: "foo", scope: !0, isLocal: false, isDefinition: true)
+!6 = !DIGlobalVariable(name: "foo", scope: !0)
+
+!7 = !DICompositeType(tag: DW_TAG_structure_type, name: "Class", size: 8, align: 8)
+!8 = !DIDerivedType(tag: DW_TAG_member, name: "mem", flags: DIFlagStaticMember, scope: !7, baseType: !3)
+
+; CHECK: !9 = !DIGlobalVariable(name: "mem", scope: !0, isLocal: false, isDefinition: true, declaration: !8)
+!9 = !DIGlobalVariable(name: "mem", scope: !0, declaration: !8)
diff --git a/test/Assembler/mdimportedentity.ll b/test/Assembler/mdimportedentity.ll
new file mode 100644
index 000000000000..929267e3b25e
--- /dev/null
+++ b/test/Assembler/mdimportedentity.ll
@@ -0,0 +1,20 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+; CHECK: !named = !{!0, !1, !2, !3, !3}
+!named = !{!0, !1, !2, !3, !4}
+
+; CHECK:      !0 = !DISubprogram({{.*}})
+; CHECK-NEXT: !1 = !DICompositeType({{.*}})
+!0 = !DISubprogram(name: "foo")
+!1 = !DICompositeType(tag: DW_TAG_structure_type, name: "Class", size: 32, align: 32)
+
+; CHECK-NEXT: !2 = !DIImportedEntity(tag: DW_TAG_imported_module, name: "foo", scope: !0, entity: !1, line: 7)
+!2 = !DIImportedEntity(tag: DW_TAG_imported_module, name: "foo", scope: !0,
+                       entity: !1, line: 7)
+
+; CHECK-NEXT: !3 = !DIImportedEntity(tag: DW_TAG_imported_module, scope: !0)
+!3 = !DIImportedEntity(tag: DW_TAG_imported_module, scope: !0)
+!4 = !DIImportedEntity(tag: DW_TAG_imported_module, name: "", scope: !0, entity: null,
+                       line: 0)
+
diff --git a/test/Assembler/mdlexicalblock.ll b/test/Assembler/mdlexicalblock.ll
new file mode 100644
index 000000000000..2cab372384ca
--- /dev/null
+++ b/test/Assembler/mdlexicalblock.ll
@@ -0,0 +1,25 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+; CHECK: !named = !{!0, !1, !2, !3, !4, !4, !5, !6, !7, !7}
+!named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9}
+
+!0 = distinct !{}
+!1 = !DISubprogram(name: "foo", scope: !2)
+!2 = !DIFile(filename: "path/to/file", directory: "/path/to/dir")
+
+; CHECK: !3 = !DILexicalBlock(scope: !1, file: !2, line: 7, column: 35)
+!3 = !DILexicalBlock(scope: !1, file: !2, line: 7, column: 35)
+
+; CHECK: !4 = !DILexicalBlock(scope: !1)
+!4 = !DILexicalBlock(scope: !1)
+!5 = !DILexicalBlock(scope: !1, file: null, line: 0, column: 0)
+
+; CHECK: !5 = !DILexicalBlockFile(scope: !3, file: !2, discriminator: 0)
+; CHECK: !6 = !DILexicalBlockFile(scope: !3, file: !2, discriminator: 1)
+!6 = !DILexicalBlockFile(scope: !3, file: !2, discriminator: 0)
+!7 = !DILexicalBlockFile(scope: !3, file: !2, discriminator: 1)
+
+; CHECK: !7 = !DILexicalBlockFile(scope: !3, discriminator: 7)
+!8 = !DILexicalBlockFile(scope: !3, discriminator: 7)
+!9 = !DILexicalBlockFile(scope: !3, file: null, discriminator: 7)
diff --git a/test/Assembler/mdlocalvariable.ll b/test/Assembler/mdlocalvariable.ll
new file mode 100644
index 000000000000..312373ca8623
--- /dev/null
+++ b/test/Assembler/mdlocalvariable.ll
@@ -0,0 +1,26 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+@foo = global i32 0
+
+; CHECK: !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8}
+!named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8}
+
+!0 = distinct !DISubprogram()
+!1 = distinct !{}
+!2 = !DIFile(filename: "path/to/file", directory: "/path/to/dir")
+!3 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!4 = !DILocation(scope: !0)
+
+; CHECK: !5 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "foo", arg: 3, scope: !0, file: !2, line: 7, type: !3, flags: DIFlagArtificial)
+; CHECK: !6 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "foo", scope: !0, file: !2, line: 7, type: !3, flags: DIFlagArtificial)
+!5 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "foo", arg: 3,
+                      scope: !0, file: !2, line: 7, type: !3,
+                      flags: DIFlagArtificial)
+!6 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "foo", scope: !0,
+                      file: !2, line: 7, type: !3, flags: DIFlagArtificial)
+
+; CHECK: !7 = !DILocalVariable(tag: DW_TAG_arg_variable, arg: 0, scope: !0)
+; CHECK: !8 = !DILocalVariable(tag: DW_TAG_auto_variable, scope: !0)
+!7 = !DILocalVariable(tag: DW_TAG_arg_variable, scope: !0)
+!8 = !DILocalVariable(tag: DW_TAG_auto_variable, scope: !0)
diff --git a/test/Assembler/mdlocation.ll b/test/Assembler/mdlocation.ll
index c1815ff50e09..a468f8abe9c6 100644
--- a/test/Assembler/mdlocation.ll
+++ b/test/Assembler/mdlocation.ll
@@ -1,20 +1,23 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
 ; RUN: verify-uselistorder %s
 
-; CHECK: !named = !{!0, !1, !1, !2, !2, !3, !3}
-!named = !{!0, !1, !2, !3, !4, !5, !6}
+; CHECK: !named = !{!0, !1, !1, !2, !2, !3, !3, !4}
+!named = !{!0, !1, !2, !3, !4, !5, !6, !7}
 
-; CHECK: !0 = !{}
-!0 = !{}
+; CHECK: !0 = !DISubprogram(
+!0 = !DISubprogram()
 
-; CHECK-NEXT: !1 = !MDLocation(line: 3, column: 7, scope: !0)
-!1 = !MDLocation(line: 3, column: 7, scope: !0)
-!2 = !MDLocation(scope: !0, column: 7, line: 3)
+; CHECK-NEXT: !1 = !DILocation(line: 3, column: 7, scope: !0)
+!1 = !DILocation(line: 3, column: 7, scope: !0)
+!2 = !DILocation(scope: !0, column: 7, line: 3)
 
-; CHECK-NEXT: !2 = !MDLocation(line: 3, column: 7, scope: !0, inlinedAt: !1)
-!3 = !MDLocation(scope: !0, inlinedAt: !1, column: 7, line: 3)
-!4 = !MDLocation(column: 7, line: 3, scope: !0, inlinedAt: !1)
+; CHECK-NEXT: !2 = !DILocation(line: 3, column: 7, scope: !0, inlinedAt: !1)
+!3 = !DILocation(scope: !0, inlinedAt: !1, column: 7, line: 3)
+!4 = !DILocation(column: 7, line: 3, scope: !0, inlinedAt: !1)
 
-; CHECK-NEXT: !3 = !MDLocation(line: 0, scope: !0)
-!5 = !MDLocation(scope: !0)
-!6 = !MDLocation(scope: !0, column: 0, line: 0)
+; CHECK-NEXT: !3 = !DILocation(line: 0, scope: !0)
+!5 = !DILocation(scope: !0)
+!6 = !DILocation(scope: !0, column: 0, line: 0)
+
+; CHECK-NEXT: !4 = !DILocation(line: 4294967295, column: 65535, scope: !0)
+!7 = !DILocation(line: 4294967295, column: 65535, scope: !0)
diff --git a/test/Assembler/mdnamespace.ll b/test/Assembler/mdnamespace.ll
new file mode 100644
index 000000000000..5d8b6b3fa7d7
--- /dev/null
+++ b/test/Assembler/mdnamespace.ll
@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+; CHECK: !named = !{!0, !1, !2, !3, !4, !4}
+!named = !{!0, !1, !2, !3, !4, !5}
+
+!0 = !DIFile(filename: "file.cpp", directory: "/path/to/dir")
+!1 = distinct !{}
+!2 = !DIFile(filename: "path/to/file", directory: "/path/to/dir")
+
+; CHECK: !3 = !DINamespace(name: "Namespace", scope: !0, file: !2, line: 7)
+!3 = !DINamespace(name: "Namespace", scope: !0, file: !2, line: 7)
+
+; CHECK: !4 = !DINamespace(scope: !0)
+!4 = !DINamespace(name: "", scope: !0, file: null, line: 0)
+!5 = !DINamespace(scope: !0)
diff --git a/test/Assembler/mdobjcproperty.ll b/test/Assembler/mdobjcproperty.ll
new file mode 100644
index 000000000000..ca13e27662d4
--- /dev/null
+++ b/test/Assembler/mdobjcproperty.ll
@@ -0,0 +1,19 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+; CHECK: !named = !{!0, !1, !2, !3, !4, !4}
+!named = !{!0, !1, !2, !3, !4, !5}
+
+!0 = distinct !{}
+!1 = !DIFile(filename: "path/to/file", directory: "/path/to/dir")
+!2 = !DICompositeType(tag: DW_TAG_structure_type, name: "Object")
+
+; CHECK: !2 = !DICompositeType({{.*}})
+; CHECK-NEXT: !3 = !DIObjCProperty(name: "foo", file: !1, line: 7, setter: "setFoo", getter: "getFoo", attributes: 7, type: !2)
+!3 = !DIObjCProperty(name: "foo", file: !1, line: 7, setter: "setFoo",
+                     getter: "getFoo", attributes: 7, type: !2)
+
+; CHECK-NEXT: !4 = !DIObjCProperty()
+!4 = !DIObjCProperty(name: "", file: null, line: 0, setter: "", getter: "",
+                     attributes: 0, type: null)
+!5 = !DIObjCProperty()
diff --git a/test/Assembler/mdsubprogram.ll b/test/Assembler/mdsubprogram.ll
new file mode 100644
index 000000000000..3fa1081889ff
--- /dev/null
+++ b/test/Assembler/mdsubprogram.ll
@@ -0,0 +1,28 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+declare void @_Z3foov()
+
+; CHECK: !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9}
+!named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9}
+
+!0 = !{null}
+!1 = distinct !DICompositeType(tag: DW_TAG_structure_type)
+!2 = !DIFile(filename: "path/to/file", directory: "/path/to/dir")
+!3 = !DISubroutineType(types: !0)
+!4 = distinct !DICompositeType(tag: DW_TAG_structure_type)
+!5 = distinct !{}
+!6 = distinct !DISubprogram(isDefinition: false)
+!7 = distinct !{}
+
+; CHECK: !8 = !DISubprogram(name: "foo", linkageName: "_Zfoov", scope: !1, file: !2, line: 7, type: !3, isLocal: true, isDefinition: false, scopeLine: 8, containingType: !4, virtuality: DW_VIRTUALITY_pure_virtual, virtualIndex: 10, flags: DIFlagPrototyped, isOptimized: true, function: void ()* @_Z3foov, templateParams: !5, declaration: !6, variables: !7)
+!8 = !DISubprogram(name: "foo", linkageName: "_Zfoov", scope: !1,
+                   file: !2, line: 7, type: !3, isLocal: true,
+                   isDefinition: false, scopeLine: 8, containingType: !4,
+                   virtuality: DW_VIRTUALITY_pure_virtual, virtualIndex: 10,
+                   flags: DIFlagPrototyped, isOptimized: true, function: void ()* @_Z3foov,
+                   templateParams: !5, declaration: !6, variables: !7)
+
+; CHECK: !9 = !DISubprogram(scope: null, isLocal: false, isDefinition: true, isOptimized: false)
+!9 = !DISubprogram()
+
diff --git a/test/Assembler/mdsubrange-empty-array.ll b/test/Assembler/mdsubrange-empty-array.ll
new file mode 100644
index 000000000000..7b5279e3d3c2
--- /dev/null
+++ b/test/Assembler/mdsubrange-empty-array.ll
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+; CHECK: !named = !{!0, !0, !1, !2}
+!named = !{!0, !1, !2, !3}
+
+; CHECK:      !0 = !DISubrange(count: -1)
+; CHECK-NEXT: !1 = !DISubrange(count: -1, lowerBound: 4)
+; CHECK-NEXT: !2 = !DISubrange(count: -1, lowerBound: -5)
+!0 = !DISubrange(count: -1)
+!1 = !DISubrange(count: -1, lowerBound: 0)
+
+!2 = !DISubrange(count: -1, lowerBound: 4)
+!3 = !DISubrange(count: -1, lowerBound: -5)
diff --git a/test/Assembler/mdsubroutinetype.ll b/test/Assembler/mdsubroutinetype.ll
new file mode 100644
index 000000000000..4ec2be7de3b9
--- /dev/null
+++ b/test/Assembler/mdsubroutinetype.ll
@@ -0,0 +1,23 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+; CHECK: !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8}
+!named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8}
+
+!0 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!1 = !{null}
+!2 = !{null, !0}
+!3 = !{!0, !0, !0}
+
+
+; CHECK: !4 = !DISubroutineType(types: !1)
+; CHECK: !5 = !DISubroutineType(types: !2)
+; CHECK: !6 = !DISubroutineType(types: !3)
+; CHECK: !7 = !DISubroutineType(flags: DIFlagLValueReference, types: !3)
+!4 = !DISubroutineType(types: !1)
+!5 = !DISubroutineType(types: !2)
+!6 = !DISubroutineType(types: !3)
+!7 = !DISubroutineType(flags: DIFlagLValueReference, types: !3)
+
+; CHECK: !8 = !DISubroutineType(types: null)
+!8 = !DISubroutineType(types: null)
diff --git a/test/Assembler/mdtemplateparameter.ll b/test/Assembler/mdtemplateparameter.ll
new file mode 100644
index 000000000000..a356ad4e7bc9
--- /dev/null
+++ b/test/Assembler/mdtemplateparameter.ll
@@ -0,0 +1,24 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+; CHECK: !named = !{!0, !1, !2, !3, !3, !4, !5, !5, !6}
+!named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8}
+
+!0 = distinct !{}
+!1 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+; CHECK: !1 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+
+; CHECK-NEXT: !2 = !DITemplateTypeParameter(name: "Ty", type: !1)
+; CHECK-NEXT: !3 = !DITemplateTypeParameter(type: !1)
+!2 = !DITemplateTypeParameter(name: "Ty", type: !1)
+!3 = !DITemplateTypeParameter(type: !1)
+!4 = !DITemplateTypeParameter(name: "", type: !1)
+
+; CHECK-NEXT: !4 = !DITemplateValueParameter(name: "V", type: !1, value: i32 7)
+; CHECK-NEXT: !5 = !DITemplateValueParameter(type: !1, value: i32 7)
+; CHECK-NEXT: !6 = !DITemplateValueParameter(tag: DW_TAG_GNU_template_template_param, name: "param", type: !1, value: !"template")
+!5 = !DITemplateValueParameter(name: "V", type: !1, value: i32 7)
+!6 = !DITemplateValueParameter(type: !1, value: i32 7)
+!7 = !DITemplateValueParameter(tag: DW_TAG_template_value_parameter,
+                               name: "", type: !1, value: i32 7)
+!8 = !DITemplateValueParameter(tag: DW_TAG_GNU_template_template_param, name: "param", type: !1, value: !"template")
diff --git a/test/Assembler/mdtype-large-values.ll b/test/Assembler/mdtype-large-values.ll
new file mode 100644
index 000000000000..a371ac68f90a
--- /dev/null
+++ b/test/Assembler/mdtype-large-values.ll
@@ -0,0 +1,12 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+; CHECK: !named = !{!0, !1, !2}
+!named = !{!0, !1, !2}
+
+; CHECK:      !0 = !DIBasicType(name: "name", size: 18446744073709551615, align: 18446744073709551614, encoding: DW_ATE_unsigned_char)
+; CHECK-NEXT: !1 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !0, size: 18446744073709551615, align: 18446744073709551614, offset: 18446744073709551613)
+; CHECK-NEXT: !2 = !DICompositeType(tag: DW_TAG_array_type, baseType: !0, size: 18446744073709551615, align: 18446744073709551614, offset: 18446744073709551613)
+!0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 18446744073709551615, align: 18446744073709551614, encoding: DW_ATE_unsigned_char)
+!1 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !0, size: 18446744073709551615, align: 18446744073709551614, offset: 18446744073709551613)
+!2 = !DICompositeType(tag: DW_TAG_array_type, baseType: !0, size: 18446744073709551615, align: 18446744073709551614, offset: 18446744073709551613)
diff --git a/test/Assembler/metadata-function-local.ll b/test/Assembler/metadata-function-local.ll
new file mode 100644
index 000000000000..9768e34d786e
--- /dev/null
+++ b/test/Assembler/metadata-function-local.ll
@@ -0,0 +1,20 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+declare void @llvm.metadata(metadata)
+
+define void @foo(i32 %arg) {
+entry:
+  %before = alloca i32
+  call void @llvm.metadata(metadata i32 %arg)
+  call void @llvm.metadata(metadata i32* %after)
+  call void @llvm.metadata(metadata i32* %before)
+  %after = alloca i32
+  ret void
+
+; CHECK: %before = alloca i32
+; CHECK: call void @llvm.metadata(metadata i32 %arg)
+; CHECK: call void @llvm.metadata(metadata i32* %after)
+; CHECK: call void @llvm.metadata(metadata i32* %before)
+; CHECK: %after = alloca i32
+}
diff --git a/test/Assembler/metadata-null-operands.ll b/test/Assembler/metadata-null-operands.ll
new file mode 100644
index 000000000000..2d013d0e912a
--- /dev/null
+++ b/test/Assembler/metadata-null-operands.ll
@@ -0,0 +1,11 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+; Don't crash on null operands.  When we add a verify check for this, also
+; require non-null in the assembler and rework this test to check for that ala
+; test/Assembler/invalid-mdcompileunit-null-file.ll.
+!named = !{!0}
+!0 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: null)
+
+; CHECK: !named = !{!0}
+; CHECK: !0 = !DIDerivedType({{.*}}baseType: null{{.*}})
diff --git a/test/Assembler/metadata.ll b/test/Assembler/metadata.ll
index e2c59237981f..4fb8851a9f40 100644
--- a/test/Assembler/metadata.ll
+++ b/test/Assembler/metadata.ll
@@ -11,8 +11,22 @@ define void @test() {
   ret void, !foo !0, !bar !1
 }
 
-!0 = !MDLocation(line: 662302, column: 26, scope: !1)
-!1 = !{i32 4, !"foo"}
+; CHECK: define void @test2() !foo !2 !baz !3
+define void @test2() !foo !2 !baz !3 {
+  unreachable
+}
+
+; CHECK: define void @test3() !bar !3
+; CHECK: unreachable, !bar !4
+define void @test3() !bar !3 {
+  unreachable, !bar !4
+}
+
+!0 = !DILocation(line: 662302, column: 26, scope: !1)
+!1 = !DISubprogram(name: "foo")
+!2 = distinct !{}
+!3 = distinct !{}
+!4 = distinct !{}
 
 declare void @llvm.dbg.func.start(metadata) nounwind readnone
 
diff --git a/test/Assembler/musttail-invalid-1.ll b/test/Assembler/musttail-invalid-1.ll
index b123a9151d3d..e9141c813dff 100644
--- a/test/Assembler/musttail-invalid-1.ll
+++ b/test/Assembler/musttail-invalid-1.ll
@@ -8,7 +8,7 @@
 declare i8* @f(i8*, ...)
 
 define i8* @f_thunk(i8* %this) {
-  %rv = musttail call i8* (i8*, ...)* @f(i8* %this, ...)
+  %rv = musttail call i8* (i8*, ...) @f(i8* %this, ...)
 ; CHECK: error: unexpected ellipsis in argument list for musttail call in non-varargs function
   ret i8* %rv
 }
diff --git a/test/Assembler/musttail-invalid-2.ll b/test/Assembler/musttail-invalid-2.ll
index 3bcb51fc4851..8602afd3d2cb 100644
--- a/test/Assembler/musttail-invalid-2.ll
+++ b/test/Assembler/musttail-invalid-2.ll
@@ -7,7 +7,7 @@
 declare i8* @f(i8*, ...)
 
 define i8* @f_thunk(i8* %this, ...) {
-  %rv = musttail call i8* (i8*, ...)* @f(i8* %this)
+  %rv = musttail call i8* (i8*, ...) @f(i8* %this)
 ; CHECK: error: expected '...' at end of argument list for musttail call in varargs function
   ret i8* %rv
 }
diff --git a/test/Assembler/musttail.ll b/test/Assembler/musttail.ll
index 6e2a9b2ef327..ac60ba2d02fa 100644
--- a/test/Assembler/musttail.ll
+++ b/test/Assembler/musttail.ll
@@ -7,8 +7,8 @@
 declare i8* @f(i8*, ...)
 
 define i8* @f_thunk(i8* %this, ...) {
-  %rv = musttail call i8* (i8*, ...)* @f(i8* %this, ...)
+  %rv = musttail call i8* (i8*, ...) @f(i8* %this, ...)
   ret i8* %rv
 }
 ; CHECK-LABEL: define i8* @f_thunk(i8* %this, ...)
-; CHECK: %rv = musttail call i8* (i8*, ...)* @f(i8* %this, ...)
+; CHECK: %rv = musttail call i8* (i8*, ...) @f(i8* %this, ...)
diff --git a/test/Assembler/numbered-values.ll b/test/Assembler/numbered-values.ll
index 70b63779ccb6..0b14c6845ab0 100644
--- a/test/Assembler/numbered-values.ll
+++ b/test/Assembler/numbered-values.ll
@@ -9,7 +9,7 @@ entry:
 	%0 = alloca i32		; <i32*>:0 [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store i32 %X, i32* %X_addr
-	%1 = load i32* %X_addr, align 4		; <i32>:1 [#uses=1]
+	%1 = load i32, i32* %X_addr, align 4		; <i32>:1 [#uses=1]
 	mul i32 %1, 4		; <i32>:2 [#uses=1]
 	%3 = add i32 %2, 123		; <i32>:3 [#uses=1]
 	store i32 %3, i32* %0, align 4
diff --git a/test/Assembler/unnamed.ll b/test/Assembler/unnamed.ll
index 099a15a254af..7f79e5c20d74 100644
--- a/test/Assembler/unnamed.ll
+++ b/test/Assembler/unnamed.ll
@@ -16,7 +16,7 @@ module asm "this is another inline asm block"
 @3 = global x86_fp80 0xK4001E000000000000000
 
 define float @foo(%0* %p) nounwind {
-  %t = load %0* %p                                ; <%0> [#uses=2]
+  %t = load %0, %0* %p                                ; <%0> [#uses=2]
   %s = extractvalue %0 %t, 1, 0                   ; <float> [#uses=1]
   %r = insertvalue %0 %t, double 2.000000e+00, 1, 1; <%0> [#uses=1]
   store %0 %r, %0* %p
diff --git a/test/Assembler/unsized-recursive-type.ll b/test/Assembler/unsized-recursive-type.ll
new file mode 100644
index 000000000000..b6d93fa19fe2
--- /dev/null
+++ b/test/Assembler/unsized-recursive-type.ll
@@ -0,0 +1,9 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+; CHECK: base element of getelementptr must be sized
+
+%myTy = type { %myTy }
+define void @foo(%myTy* %p){
+  %0 = getelementptr %myTy, %myTy* %p, i32 0
+  ret void
+}
diff --git a/test/Assembler/upgrade-loop-metadata.ll b/test/Assembler/upgrade-loop-metadata.ll
index 0852469774bf..d88cb3ee2e2c 100644
--- a/test/Assembler/upgrade-loop-metadata.ll
+++ b/test/Assembler/upgrade-loop-metadata.ll
@@ -14,7 +14,7 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 16
   br i1 %cmp, label %for.body, label %for.end, !llvm.loop !1
 
@@ -22,7 +22,7 @@ for.body:                                         ; preds = %for.cond
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %inc = add nsw i32 %1, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
diff --git a/test/Assembler/uselistorder.ll b/test/Assembler/uselistorder.ll
index be5ee7000299..2475fc48caf4 100644
--- a/test/Assembler/uselistorder.ll
+++ b/test/Assembler/uselistorder.ll
@@ -4,7 +4,7 @@
 ; RUN: verify-uselistorder < %s
 
 @a = global [4 x i1] [i1 0, i1 1, i1 0, i1 1]
-@b = alias i1* getelementptr ([4 x i1]* @a, i64 0, i64 2)
+@b = alias i1* getelementptr ([4 x i1], [4 x i1]* @a, i64 0, i64 2)
 
 ; Check use-list order of constants used by globals.
 @glob1 = global i5 7
@@ -48,9 +48,9 @@ first:
 
 define i1 @loada() {
 entry:
-  %a = load i1* getelementptr ([4 x i1]* @a, i64 0, i64 2)
+  %a = load i1, i1* getelementptr ([4 x i1], [4 x i1]* @a, i64 0, i64 2)
   ret i1 %a
 }
 
 uselistorder i5 7, { 1, 0, 2 }
-uselistorder i1* getelementptr ([4 x i1]* @a, i64 0, i64 2), { 1, 0 }
+uselistorder i1* getelementptr ([4 x i1], [4 x i1]* @a, i64 0, i64 2), { 1, 0 }
diff --git a/test/Assembler/uselistorder_bb.ll b/test/Assembler/uselistorder_bb.ll
index 11ae57b299ca..4da85bc3bafe 100644
--- a/test/Assembler/uselistorder_bb.ll
+++ b/test/Assembler/uselistorder_bb.ll
@@ -4,11 +4,11 @@
 ; RUN: verify-uselistorder < %s
 
 @ba1 = constant i8* blockaddress (@bafunc1, %bb)
-@ba2 = constant i8* getelementptr (i8* blockaddress (@bafunc2, %bb), i61 0)
-@ba3 = constant i8* getelementptr (i8* blockaddress (@bafunc2, %bb), i61 0)
+@ba2 = constant i8* getelementptr (i8, i8* blockaddress (@bafunc2, %bb), i61 0)
+@ba3 = constant i8* getelementptr (i8, i8* blockaddress (@bafunc2, %bb), i61 0)
 
 define i8* @babefore() {
-  ret i8* getelementptr (i8* blockaddress (@bafunc2, %bb), i61 0)
+  ret i8* getelementptr (i8, i8* blockaddress (@bafunc2, %bb), i61 0)
 bb1:
   ret i8* blockaddress (@bafunc1, %bb)
 bb2:
diff --git a/test/Bindings/OCaml/core.ml b/test/Bindings/OCaml/core.ml
index 0f3daac5bfd2..3c759af791d0 100644
--- a/test/Bindings/OCaml/core.ml
+++ b/test/Bindings/OCaml/core.ml
@@ -1428,15 +1428,24 @@ let test_builder () =
     add_incoming (p2, b2) phi;
     insist ([(p1, b1); (p2, b2)] = incoming phi);
 
+    (* CHECK: %PhiEmptyNode = phi i8
+     *)
+    let phi_empty = build_empty_phi i8_type "PhiEmptyNode" at_jb in
+    insist ([] = incoming phi_empty);
+
+    (* can't emit an empty phi to bitcode *)
+    add_incoming (const_int i8_type 1, b1) phi_empty;
+    add_incoming (const_int i8_type 2, b2) phi_empty;
+
     ignore (build_unreachable at_jb);
   end
 
 (* End-of-file checks for things like metdata and attributes.
  * CHECK: attributes #0 = {{.*}}uwtable{{.*}}
  * CHECK: !llvm.module.flags = !{!0}
- * CHECK: !0 = !{i32 1, !"Debug Info Version", i32 2}
+ * CHECK: !0 = !{i32 1, !"Debug Info Version", i32 3}
  * CHECK: !1 = !{i32 1, !"metadata test"}
- * CHECK: !2 = !MDLocation(line: 2, column: 3, scope: !3, inlinedAt: !3)
+ * CHECK: !2 = !DILocation(line: 2, column: 3, scope: !3, inlinedAt: !3)
  *)
 
 (*===-- Pass Managers -----------------------------------------------------===*)
diff --git a/test/Bindings/OCaml/linker.ml b/test/Bindings/OCaml/linker.ml
index 0a365ff81487..1ea0be9d3dc3 100644
--- a/test/Bindings/OCaml/linker.ml
+++ b/test/Bindings/OCaml/linker.ml
@@ -45,7 +45,7 @@ let test_linker () =
 
   let m1 = make_module "one"
   and m2 = make_module "two" in
-  link_modules m1 m2 Mode.DestroySource;
+  link_modules m1 m2;
   dispose_module m1;
 
   let m1 = make_module "one"
diff --git a/test/Bitcode/DICompileUnit-no-DWOId.ll b/test/Bitcode/DICompileUnit-no-DWOId.ll
new file mode 100644
index 000000000000..4771c37264f2
--- /dev/null
+++ b/test/Bitcode/DICompileUnit-no-DWOId.ll
@@ -0,0 +1,9 @@
+; The input uses the older (r236428) form without a dwoId field.  This should
+; default to 0, which is not displayed at all in the textual representation.
+;
+; RUN: llvm-dis %s.bc -o - | FileCheck %s
+; CHECK: !DICompileUnit
+; CHECK-NOT: dwoId:
+!named = !{!0}
+!0 = !DICompileUnit(language: 12, file: !1)
+!1 = !DIFile(filename: "path/to/file", directory: "/path/to/dir")
diff --git a/test/Bitcode/DICompileUnit-no-DWOId.ll.bc b/test/Bitcode/DICompileUnit-no-DWOId.ll.bc
new file mode 100644
index 000000000000..1a3c99b5806b
--- /dev/null
+++ b/test/Bitcode/DICompileUnit-no-DWOId.ll.bc
diff --git a/test/Bitcode/Inputs/invalid-GCTable-overflow.bc b/test/Bitcode/Inputs/invalid-GCTable-overflow.bc
new file mode 100644
index 000000000000..a9e9c52e1c04
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-GCTable-overflow.bc
diff --git a/test/Bitcode/Inputs/invalid-abbrev-fixed-size-too-big.bc b/test/Bitcode/Inputs/invalid-abbrev-fixed-size-too-big.bc
new file mode 100644
index 000000000000..8fa28960d727
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-abbrev-fixed-size-too-big.bc
diff --git a/test/Bitcode/Inputs/invalid-abbrev-no-operands.bc b/test/Bitcode/Inputs/invalid-abbrev-no-operands.bc
new file mode 100644
index 000000000000..29af122e94e2
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-abbrev-no-operands.bc
diff --git a/test/Bitcode/Inputs/invalid-abbrev-vbr-size-too-big.bc b/test/Bitcode/Inputs/invalid-abbrev-vbr-size-too-big.bc
new file mode 100644
index 000000000000..35d00ba154b5
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-abbrev-vbr-size-too-big.bc
diff --git a/test/Bitcode/Inputs/invalid-abbrev.bc b/test/Bitcode/Inputs/invalid-abbrev.bc
new file mode 100644
index 000000000000..4e8f3944b84b
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-abbrev.bc
diff --git a/test/Bitcode/Inputs/invalid-align.bc b/test/Bitcode/Inputs/invalid-align.bc
new file mode 100644
index 000000000000..e84fa6cdda5f
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-align.bc
diff --git a/test/Bitcode/Inputs/invalid-array-element-type.bc b/test/Bitcode/Inputs/invalid-array-element-type.bc
new file mode 100644
index 000000000000..3ce4ba2f77d5
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-array-element-type.bc
diff --git a/test/Bitcode/Inputs/invalid-array-op-not-2nd-to-last.bc b/test/Bitcode/Inputs/invalid-array-op-not-2nd-to-last.bc
new file mode 100644
index 000000000000..a4b94f8213df
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-array-op-not-2nd-to-last.bc
diff --git a/test/Bitcode/Inputs/invalid-array-operand-encoding.bc b/test/Bitcode/Inputs/invalid-array-operand-encoding.bc
new file mode 100644
index 000000000000..f7ec2eb700a3
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-array-operand-encoding.bc
diff --git a/test/Bitcode/Inputs/invalid-array-type.bc b/test/Bitcode/Inputs/invalid-array-type.bc
new file mode 100644
index 000000000000..3a4b635dd0ee
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-array-type.bc
diff --git a/test/Bitcode/Inputs/invalid-bad-abbrev-number.bc b/test/Bitcode/Inputs/invalid-bad-abbrev-number.bc
new file mode 100644
index 000000000000..e4e1fb3e4b31
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-bad-abbrev-number.bc
@@ -0,0 +1 @@
+BCÀÞ!0000000000
\ No newline at end of file
diff --git a/test/Bitcode/Inputs/invalid-bitwidth.bc b/test/Bitcode/Inputs/invalid-bitwidth.bc
new file mode 100644
index 000000000000..e9028f71e5fd
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-bitwidth.bc
diff --git a/test/Bitcode/Inputs/invalid-call-mismatched-explicit-type.bc b/test/Bitcode/Inputs/invalid-call-mismatched-explicit-type.bc
new file mode 100644
index 000000000000..802d28edbf44
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-call-mismatched-explicit-type.bc
diff --git a/test/Bitcode/Inputs/invalid-call-non-function-explicit-type.bc b/test/Bitcode/Inputs/invalid-call-non-function-explicit-type.bc
new file mode 100644
index 000000000000..d080689e567f
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-call-non-function-explicit-type.bc
diff --git a/test/Bitcode/Inputs/invalid-code-len-width.bc b/test/Bitcode/Inputs/invalid-code-len-width.bc
new file mode 100644
index 000000000000..c8e8c4f66538
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-code-len-width.bc
diff --git a/test/Bitcode/Inputs/invalid-extract-0-indices.bc b/test/Bitcode/Inputs/invalid-extract-0-indices.bc
new file mode 100644
index 000000000000..bfde5264502a
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-extract-0-indices.bc
diff --git a/test/Bitcode/Inputs/invalid-extractval-array-idx.bc b/test/Bitcode/Inputs/invalid-extractval-array-idx.bc
new file mode 100644
index 000000000000..7465df361c05
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-extractval-array-idx.bc
diff --git a/test/Bitcode/Inputs/invalid-extractval-struct-idx.bc b/test/Bitcode/Inputs/invalid-extractval-struct-idx.bc
new file mode 100644
index 000000000000..ccb40f7ebce9
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-extractval-struct-idx.bc
diff --git a/test/Bitcode/Inputs/invalid-extractval-too-many-idxs.bc b/test/Bitcode/Inputs/invalid-extractval-too-many-idxs.bc
new file mode 100644
index 000000000000..543a3ba7131f
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-extractval-too-many-idxs.bc
diff --git a/test/Bitcode/Inputs/invalid-fixme-streaming-blob.bc b/test/Bitcode/Inputs/invalid-fixme-streaming-blob.bc
new file mode 100644
index 000000000000..7e32f8b0774f
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-fixme-streaming-blob.bc
diff --git a/test/Bitcode/Inputs/invalid-fp-shift.bc b/test/Bitcode/Inputs/invalid-fp-shift.bc
new file mode 100644
index 000000000000..aeba1bff9687
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-fp-shift.bc
diff --git a/test/Bitcode/Inputs/invalid-function-argument-type.bc b/test/Bitcode/Inputs/invalid-function-argument-type.bc
new file mode 100644
index 000000000000..b00fb03cd313
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-function-argument-type.bc
diff --git a/test/Bitcode/Inputs/invalid-function-comdat-id.bc b/test/Bitcode/Inputs/invalid-function-comdat-id.bc
new file mode 100644
index 000000000000..d0ad8234bc86
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-function-comdat-id.bc
diff --git a/test/Bitcode/Inputs/invalid-fwdref-type-mismatch-2.bc b/test/Bitcode/Inputs/invalid-fwdref-type-mismatch-2.bc
new file mode 100644
index 000000000000..8e38340eedea
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-fwdref-type-mismatch-2.bc
diff --git a/test/Bitcode/Inputs/invalid-fwdref-type-mismatch.bc b/test/Bitcode/Inputs/invalid-fwdref-type-mismatch.bc
new file mode 100644
index 000000000000..d1c9560257a7
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-fwdref-type-mismatch.bc
diff --git a/test/Bitcode/Inputs/invalid-gep-mismatched-explicit-type.bc b/test/Bitcode/Inputs/invalid-gep-mismatched-explicit-type.bc
new file mode 100644
index 000000000000..0d828e8c3296
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-gep-mismatched-explicit-type.bc
diff --git a/test/Bitcode/Inputs/invalid-gep-operator-mismatched-explicit-type.bc b/test/Bitcode/Inputs/invalid-gep-operator-mismatched-explicit-type.bc
new file mode 100644
index 000000000000..3af687f056f9
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-gep-operator-mismatched-explicit-type.bc
diff --git a/test/Bitcode/Inputs/invalid-global-var-comdat-id.bc b/test/Bitcode/Inputs/invalid-global-var-comdat-id.bc
new file mode 100644
index 000000000000..93d6ba2169b4
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-global-var-comdat-id.bc
diff --git a/test/Bitcode/Inputs/invalid-insert-0-indices.bc b/test/Bitcode/Inputs/invalid-insert-0-indices.bc
new file mode 100644
index 000000000000..d7a91e1e4488
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-insert-0-indices.bc
diff --git a/test/Bitcode/Inputs/invalid-inserted-value-type-mismatch.bc b/test/Bitcode/Inputs/invalid-inserted-value-type-mismatch.bc
new file mode 100644
index 000000000000..81333cd6be67
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-inserted-value-type-mismatch.bc
diff --git a/test/Bitcode/Inputs/invalid-insertval-array-idx.bc b/test/Bitcode/Inputs/invalid-insertval-array-idx.bc
new file mode 100644
index 000000000000..79c3c038a1cd
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-insertval-array-idx.bc
diff --git a/test/Bitcode/Inputs/invalid-insertval-struct-idx.bc b/test/Bitcode/Inputs/invalid-insertval-struct-idx.bc
new file mode 100644
index 000000000000..ec70384909a6
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-insertval-struct-idx.bc
diff --git a/test/Bitcode/Inputs/invalid-insertval-too-many-idxs.bc b/test/Bitcode/Inputs/invalid-insertval-too-many-idxs.bc
new file mode 100644
index 000000000000..fd21ac24cf45
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-insertval-too-many-idxs.bc
diff --git a/test/Bitcode/Inputs/invalid-invoke-mismatched-explicit-type.bc b/test/Bitcode/Inputs/invalid-invoke-mismatched-explicit-type.bc
new file mode 100644
index 000000000000..bce885295082
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-invoke-mismatched-explicit-type.bc
diff --git a/test/Bitcode/Inputs/invalid-invoke-non-function-explicit-type.bc b/test/Bitcode/Inputs/invalid-invoke-non-function-explicit-type.bc
new file mode 100644
index 000000000000..d7810bb964be
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-invoke-non-function-explicit-type.bc
diff --git a/test/Bitcode/Inputs/invalid-load-mismatched-explicit-type.bc b/test/Bitcode/Inputs/invalid-load-mismatched-explicit-type.bc
new file mode 100644
index 000000000000..1b8cbc751316
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-load-mismatched-explicit-type.bc
diff --git a/test/Bitcode/Inputs/invalid-load-pointer-type.bc b/test/Bitcode/Inputs/invalid-load-pointer-type.bc
new file mode 100644
index 000000000000..b6a56c55b3bf
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-load-pointer-type.bc
diff --git a/test/Bitcode/Inputs/invalid-load-ptr-type.bc b/test/Bitcode/Inputs/invalid-load-ptr-type.bc
new file mode 100644
index 000000000000..5207ed9156e7
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-load-ptr-type.bc
diff --git a/test/Bitcode/Inputs/invalid-no-proper-module.bc b/test/Bitcode/Inputs/invalid-no-proper-module.bc
new file mode 100644
index 000000000000..6d5a291db631
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-no-proper-module.bc
diff --git a/test/Bitcode/Inputs/invalid-non-vector-extractelement.bc b/test/Bitcode/Inputs/invalid-non-vector-extractelement.bc
new file mode 100644
index 000000000000..6fee7edad879
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-non-vector-extractelement.bc
diff --git a/test/Bitcode/Inputs/invalid-non-vector-insertelement.bc b/test/Bitcode/Inputs/invalid-non-vector-insertelement.bc
new file mode 100644
index 000000000000..362716577910
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-non-vector-insertelement.bc
diff --git a/test/Bitcode/Inputs/invalid-non-vector-shufflevector.bc b/test/Bitcode/Inputs/invalid-non-vector-shufflevector.bc
new file mode 100644
index 000000000000..6c83a4dcb767
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-non-vector-shufflevector.bc
diff --git a/test/Bitcode/Inputs/invalid-pointer-element-type.bc b/test/Bitcode/Inputs/invalid-pointer-element-type.bc
new file mode 100644
index 000000000000..f9649e664294
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-pointer-element-type.bc
diff --git a/test/Bitcode/Inputs/invalid-pr20485.bc b/test/Bitcode/Inputs/invalid-pr20485.bc
new file mode 100644
index 000000000000..b6211de88ff9
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-pr20485.bc
diff --git a/test/Bitcode/Inputs/invalid-too-big-fwdref.bc b/test/Bitcode/Inputs/invalid-too-big-fwdref.bc
new file mode 100644
index 000000000000..d1d51a634fc2
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-too-big-fwdref.bc
diff --git a/test/Bitcode/Inputs/invalid-type-table-forward-ref.bc b/test/Bitcode/Inputs/invalid-type-table-forward-ref.bc
new file mode 100644
index 000000000000..4594efefd6c1
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-type-table-forward-ref.bc
diff --git a/test/Bitcode/Inputs/invalid-unexpected-eof.bc b/test/Bitcode/Inputs/invalid-unexpected-eof.bc
new file mode 100644
index 000000000000..a487393d0668
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-unexpected-eof.bc
@@ -0,0 +1 @@
+BCÀÞ!00000000000000000000
\ No newline at end of file
diff --git a/test/Bitcode/Inputs/invalid-vector-element-type.bc b/test/Bitcode/Inputs/invalid-vector-element-type.bc
new file mode 100644
index 000000000000..9c6c625c9181
--- /dev/null
+++ b/test/Bitcode/Inputs/invalid-vector-element-type.bc
diff --git a/test/Bitcode/arm32_neon_vcnt_upgrade.ll b/test/Bitcode/arm32_neon_vcnt_upgrade.ll
index ed3981b465ac..0032c4a9b7a3 100644
--- a/test/Bitcode/arm32_neon_vcnt_upgrade.ll
+++ b/test/Bitcode/arm32_neon_vcnt_upgrade.ll
@@ -4,7 +4,7 @@
 
 define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
 ;CHECK: @vclz16
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
 ;CHECK: {{call.*@llvm.ctlz.v4i16\(<4 x i16>.*, i1 false}}
         ret <4 x i16> %tmp2
@@ -12,7 +12,7 @@ define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
 
 define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
 ;CHECK: @vcnt8
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1)
 ;CHECK: call <8 x i8> @llvm.ctpop.v8i8(<8 x i8>
         ret <8 x i8> %tmp2
diff --git a/test/Bitcode/attributes.ll b/test/Bitcode/attributes.ll
index c75ee80dc661..cae6a2e01e6f 100644
--- a/test/Bitcode/attributes.ll
+++ b/test/Bitcode/attributes.ll
@@ -204,7 +204,7 @@ define void @f34()
 ; CHECK: define void @f34()
 {
         call void @nobuiltin() nobuiltin
-; CHECK: call void @nobuiltin() #25
+; CHECK: call void @nobuiltin() #26
         ret void;
 }
 
@@ -245,6 +245,17 @@ define void @f41(i8* align 32, double* align 64) {
         ret void
 }
 
+; CHECK: define dereferenceable_or_null(8) i8* @f42(i8* dereferenceable_or_null(8) %foo)
+define dereferenceable_or_null(8) i8* @f42(i8* dereferenceable_or_null(8) %foo) {
+ entry:
+  ret i8* %foo
+}
+
+; CHECK: define void @f43() #25
+define void @f43() convergent {
+  ret void
+}
+
 ; CHECK: attributes #0 = { noreturn }
 ; CHECK: attributes #1 = { nounwind }
 ; CHECK: attributes #2 = { readnone }
@@ -270,4 +281,5 @@ define void @f41(i8* align 32, double* align 64) {
 ; CHECK: attributes #22 = { minsize }
 ; CHECK: attributes #23 = { noinline optnone }
 ; CHECK: attributes #24 = { jumptable }
-; CHECK: attributes #25 = { nobuiltin }
+; CHECK: attributes #25 = { convergent }
+; CHECK: attributes #26 = { nobuiltin }
diff --git a/test/Bitcode/case-ranges-3.3.ll b/test/Bitcode/case-ranges-3.3.ll
index 020b37f49db7..eb55ef1ad21e 100644
--- a/test/Bitcode/case-ranges-3.3.ll
+++ b/test/Bitcode/case-ranges-3.3.ll
@@ -10,7 +10,7 @@ define i32 @foo(i32 %x) nounwind ssp uwtable {
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   store i32 %x, i32* %2, align 4
-  %3 = load i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
   switch i32 %3, label %9 [
 ; CHECK: switch i32 %3, label %9
     i32 -3, label %4
@@ -63,6 +63,6 @@ define i32 @foo(i32 %x) nounwind ssp uwtable {
   br label %11
 
 ; <label>:11
-  %12 = load i32* %1
+  %12 = load i32, i32* %1
   ret i32 %12
 }
diff --git a/test/Bitcode/cmpxchg.3.6.ll b/test/Bitcode/cmpxchg.3.6.ll
new file mode 100644
index 000000000000..bec51a128c33
--- /dev/null
+++ b/test/Bitcode/cmpxchg.3.6.ll
@@ -0,0 +1,13 @@
+; RUN: llvm-dis < %s.bc | FileCheck %s
+
+define void @f2(i32* %x, i32 %y.orig, i32 %z) {
+entry:
+  br label %a
+b:
+  cmpxchg i32* %x, i32 %y, i32 %z acquire acquire
+; CHECK: cmpxchg i32* %x, i32 %y, i32 %z acquire acquire
+  ret void
+a:
+  %y = add i32 %y.orig, 1
+  br label %a
+}
diff --git a/test/Bitcode/cmpxchg.3.6.ll.bc b/test/Bitcode/cmpxchg.3.6.ll.bc
new file mode 100644
index 000000000000..1c66f934324a
--- /dev/null
+++ b/test/Bitcode/cmpxchg.3.6.ll.bc
diff --git a/test/Bitcode/constantsTest.3.2.ll b/test/Bitcode/constantsTest.3.2.ll
index b4973cf7a832..3dea935dcf2d 100644
--- a/test/Bitcode/constantsTest.3.2.ll
+++ b/test/Bitcode/constantsTest.3.2.ll
@@ -99,10 +99,10 @@ entry:
   inttoptr i8 1 to i8*
   ; CHECK-NEXT: bitcast i32 1 to <2 x i16>
   bitcast i32 1 to <2 x i16>
-  ; CHECK-NEXT: getelementptr i32* @X, i32 0
-  getelementptr i32* @X, i32 0
-  ; CHECK-NEXT: getelementptr inbounds i32* @X, i32 0
-  getelementptr inbounds i32* @X, i32 0
+  ; CHECK-NEXT: getelementptr i32, i32* @X, i32 0
+  getelementptr i32, i32* @X, i32 0
+  ; CHECK-NEXT: getelementptr inbounds i32, i32* @X, i32 0
+  getelementptr inbounds i32, i32* @X, i32 0
   ; CHECK: select i1 true, i32 1, i32 0
   select i1 true ,i32 1, i32 0
   ; CHECK-NEXT: icmp eq i32 1, 0
diff --git a/test/Bitcode/debug-loc-again.ll b/test/Bitcode/debug-loc-again.ll
new file mode 100644
index 000000000000..6dbea16121aa
--- /dev/null
+++ b/test/Bitcode/debug-loc-again.ll
@@ -0,0 +1,36 @@
+; RUN: llvm-as < %s | llvm-bcanalyzer -dump | FileCheck %s -check-prefix=BC
+; PR23436: Actually emit DEBUG_LOC_AGAIN records.
+
+; BC: <DEBUG_LOC op
+; BC: <DEBUG_LOC_AGAIN/>
+; BC: <DEBUG_LOC op
+; BC: <DEBUG_LOC_AGAIN/>
+
+; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+; Check that this round-trips correctly.
+
+define void @foo() {
+entry:
+  %a = add i32 0, 0, !dbg !3
+  %b = add i32 0, 1, !dbg !3
+  %c = add i32 0, 2, !dbg !4
+  ret void, !dbg !4
+}
+
+; CHECK-LABEL: entry:
+; CHECK-NEXT: %a = add i32 0, 0, !dbg ![[LINE1:[0-9]+]]
+; CHECK-NEXT: %b = add i32 0, 1, !dbg ![[LINE1]]
+; CHECK-NEXT: %c = add i32 0, 2, !dbg ![[LINE2:[0-9]+]]
+; CHECK-NEXT: ret void, !dbg ![[LINE2]]
+; CHECK: ![[LINE1]] = !DILocation(line: 1,
+; CHECK: ![[LINE2]] = !DILocation(line: 2,
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !DICompileUnit(language: DW_LANG_C99, file: !DIFile(filename: "f", directory: "/d"),
+                    subprograms: !{!2})
+!2 = !DISubprogram(name: "foo")
+!3 = !DILocation(line: 1, scope: !2)
+!4 = !DILocation(line: 2, scope: !2)
diff --git a/test/Bitcode/drop-debug-info.3.5.ll b/test/Bitcode/drop-debug-info.3.5.ll
new file mode 100644
index 000000000000..fde136d1c3c8
--- /dev/null
+++ b/test/Bitcode/drop-debug-info.3.5.ll
@@ -0,0 +1,40 @@
+; RUN: llvm-dis < %s.bc -o %t.ll 2>&1 | FileCheck -check-prefix=WARN %s
+; RUN: FileCheck -input-file=%t.ll %s
+
+; The bitcode paired with this test was generated by passing this file to
+; llvm-dis-3.5.  This tests that llvm-dis warns correctly when reading old
+; bitcode.
+
+; CHECK-NOT: !llvm.dbg.cu
+; CHECK-NOT: !dbg
+; WARN: warning: ignoring debug info with an invalid version (1)
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+; Function Attrs: nounwind ssp uwtable
+define i32 @main() #0 {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  ret i32 0, !dbg !12
+}
+
+attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!9, !10}
+!llvm.ident = !{!11}
+
+!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.5.2 (230356)", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !"", i32 1} ; [ DW_TAG_compile_unit ] [/Users/dexonsmith/data/llvm/staging/test/Bitcode/t.c] [DW_LANG_C99]
+!1 = metadata !{metadata !"t.c", metadata !"/Users/dexonsmith/data/llvm/staging/test/Bitcode"}
+!2 = metadata !{}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"main", metadata !"main", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [main]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [/Users/dexonsmith/data/llvm/staging/test/Bitcode/t.c]
+!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{metadata !8}
+!8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = metadata !{i32 2, metadata !"Dwarf Version", i32 2}
+!10 = metadata !{i32 2, metadata !"Debug Info Version", i32 1}
+!11 = metadata !{metadata !"clang version 3.5.2 (230356)"}
+!12 = metadata !{i32 1, i32 14, metadata !4, null}
diff --git a/test/Bitcode/drop-debug-info.3.5.ll.bc b/test/Bitcode/drop-debug-info.3.5.ll.bc
new file mode 100644
index 000000000000..c40198999b27
--- /dev/null
+++ b/test/Bitcode/drop-debug-info.3.5.ll.bc
diff --git a/test/Bitcode/drop-debug-info.ll b/test/Bitcode/drop-debug-info.ll
deleted file mode 100644
index 5109b5e43279..000000000000
--- a/test/Bitcode/drop-debug-info.ll
+++ /dev/null
@@ -1,29 +0,0 @@
-; RUN: llvm-as < %s -o %t.bc 2>&1 >/dev/null | FileCheck -check-prefix=WARN %s
-; RUN: llvm-dis < %t.bc | FileCheck %s
-; RUN: verify-uselistorder < %t.bc
-
-define i32 @main() {
-entry:
-  %retval = alloca i32, align 4
-  store i32 0, i32* %retval
-  ret i32 0, !dbg !12
-}
-
-!llvm.dbg.cu = !{!0}
-!llvm.module.flags = !{!9}
-
-!0 = !{!"0x11\0012\00clang version 3.5 (trunk 195495) (llvm/trunk 195495:195504M)\000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/Users/manmanren/llvm_gmail/release/../llvm/tools/clang/test/CodeGen/debug-info-version.c] [DW_LANG_C99]
-!1 = !{!"../llvm/tools/clang/test/CodeGen/debug-info-version.c", !"/Users/manmanren/llvm_gmail/release"}
-!2 = !{i32 0}
-!3 = !{!4}
-!4 = !{!"0x2e\00main\00main\00\003\000\001\000\006\00256\000\003", !1, !5, !6, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [main]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/Users/manmanren/llvm_gmail/release/../llvm/tools/clang/test/CodeGen/debug-info-version.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{i32 2, !"Dwarf Version", i32 2}
-!12 = !MDLocation(line: 4, scope: !4)
-
-; WARN: warning: ignoring debug info with an invalid version (0)
-; CHECK-NOT: !dbg
-; CHECK-NOT: !llvm.dbg.cu
diff --git a/test/Bitcode/function-encoding-rel-operands.ll b/test/Bitcode/function-encoding-rel-operands.ll
index 24d6d8082861..1307dd483377 100644
--- a/test/Bitcode/function-encoding-rel-operands.ll
+++ b/test/Bitcode/function-encoding-rel-operands.ll
@@ -35,16 +35,16 @@ define double @test_float_binops(i32 %a) nounwind {
 
 
 ; CHECK: FUNCTION_BLOCK
-; skip checking operands of INST_INBOUNDS_GEP since that depends on ordering
+; skip checking operands of INST_GEP since that depends on ordering
 ; between literals and the formal parameters.
-; CHECK: INST_INBOUNDS_GEP {{.*}}
+; CHECK: INST_GEP {{.*}}
 ; CHECK: INST_LOAD {{.*}}op0=1 {{.*}}
 ; CHECK: INST_CMP2 op0=1 {{.*}}
 ; CHECK: INST_RET {{.*}}op0=1
 define i1 @test_load(i32 %a, {i32, i32}* %ptr) nounwind {
 entry:
-  %0 = getelementptr inbounds {i32, i32}* %ptr, i32 %a, i32 0
-  %1 = load i32* %0
+  %0 = getelementptr inbounds {i32, i32}, {i32, i32}* %ptr, i32 %a, i32 0
+  %1 = load i32, i32* %0
   %2 = icmp eq i32 %1, %a
   ret i1 %2
 }
diff --git a/test/Bitcode/highLevelStructure.3.2.ll b/test/Bitcode/highLevelStructure.3.2.ll
index 88fb3406d820..54356b9fb139 100644
--- a/test/Bitcode/highLevelStructure.3.2.ll
+++ b/test/Bitcode/highLevelStructure.3.2.ll
@@ -5,7 +5,7 @@
 ; older bitcode files.
 
 ; Data Layout Test
-; CHECK: target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-f80:32-n8:16:32-S32"
+; CHECK: target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a0:0:64-f80:32:32-n8:16:32-S32"
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a0:0:64-f80:32:32-n8:16:32-S32"
 
 ; Module-Level Inline Assembly Test
diff --git a/test/Bitcode/invalid.ll b/test/Bitcode/invalid.ll
index 8b532d8dadfd..df9fec8772d1 100644
--- a/test/Bitcode/invalid.ll
+++ b/test/Bitcode/invalid.ll
@@ -1,6 +1,6 @@
 ; RUN:  not llvm-dis < %s.bc 2>&1 | FileCheck %s
 
-; CHECK: llvm-dis{{(\.EXE|\.exe)?}}: Unknown attribute kind (48)
+; CHECK: llvm-dis{{(\.EXE|\.exe)?}}: error: Unknown attribute kind (48)
 
 ; invalid.ll.bc has an invalid attribute number.
 ; The test checks that LLVM reports the error and doesn't access freed memory
diff --git a/test/Bitcode/invalid.test b/test/Bitcode/invalid.test
new file mode 100644
index 000000000000..eb7f979d5745
--- /dev/null
+++ b/test/Bitcode/invalid.test
@@ -0,0 +1,189 @@
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-pr20485.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=INVALID-ENCODING %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=BAD-ABBREV %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-unexpected-eof.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=UNEXPECTED-EOF %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-bad-abbrev-number.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=BAD-ABBREV-NUMBER %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-type-table-forward-ref.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=BAD-TYPE-TABLE-FORWARD-REF %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-bitwidth.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=BAD-BITWIDTH %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-align.bc  2>&1 | \
+RUN:   FileCheck --check-prefix=BAD-ALIGN %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-gep-mismatched-explicit-type.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=MISMATCHED-EXPLICIT-GEP %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-load-mismatched-explicit-type.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=MISMATCHED-EXPLICIT-LOAD %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-gep-operator-mismatched-explicit-type.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=MISMATCHED-EXPLICIT-GEP-OPERATOR %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-call-mismatched-explicit-type.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=MISMATCHED-EXPLICIT-CALL %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-call-non-function-explicit-type.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=NON-FUNCTION-EXPLICIT-CALL %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-invoke-mismatched-explicit-type.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=MISMATCHED-EXPLICIT-INVOKE %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-invoke-non-function-explicit-type.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=NON-FUNCTION-EXPLICIT-INVOKE %s
+
+INVALID-ENCODING: Invalid encoding
+BAD-ABBREV: Abbreviation starts with an Array or a Blob
+UNEXPECTED-EOF: Unexpected end of file
+BAD-ABBREV-NUMBER: Invalid abbrev number
+BAD-TYPE-TABLE-FORWARD-REF: Invalid TYPE table: Only named structs can be forward referenced
+BAD-BITWIDTH: Bitwidth for integer type out of range
+BAD-ALIGN: Invalid alignment value
+MISMATCHED-EXPLICIT-GEP: Explicit gep type does not match pointee type of pointer operand
+MISMATCHED-EXPLICIT-LOAD: Explicit load/store type does not match pointee type of pointer operand
+MISMATCHED-EXPLICIT-GEP-OPERATOR: Explicit gep operator type does not match pointee type of pointer operand
+MISMATCHED-EXPLICIT-CALL: Explicit call type does not match pointee type of callee operand
+NON-FUNCTION-EXPLICIT-CALL: Explicit call type is not a function type
+MISMATCHED-EXPLICIT-INVOKE: Explicit invoke type does not match pointee type of callee operand
+NON-FUNCTION-EXPLICIT-INVOKE: Explicit invoke type is not a function type
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-extractval-array-idx.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=EXTRACT-ARRAY %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-extractval-struct-idx.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=EXTRACT-STRUCT %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-extractval-too-many-idxs.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=EXTRACT-IDXS %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-insertval-array-idx.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=INSERT-ARRAY %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-insertval-struct-idx.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=INSERT-STRUCT %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-insertval-too-many-idxs.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=INSERT-IDXS %s
+
+
+EXTRACT-ARRAY: EXTRACTVAL: Invalid array index
+EXTRACT-STRUCT: EXTRACTVAL: Invalid struct index
+EXTRACT-IDXS: EXTRACTVAL: Invalid type
+INSERT-ARRAY: INSERTVAL: Invalid array index
+INSERT-STRUCT: INSERTVAL: Invalid struct index
+INSERT-IDXS: INSERTVAL: Invalid type
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-no-proper-module.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=NO-MODULE %s
+
+NO-MODULE: Malformed IR file
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-fp-shift.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=FP-SHIFT %s
+
+FP-SHIFT: Invalid record
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev-vbr-size-too-big.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=HUGE-ABBREV-OP %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev-fixed-size-too-big.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=HUGE-ABBREV-OP %s
+
+HUGE-ABBREV-OP: Fixed or VBR abbrev record with size > MaxChunkData
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-array-type.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=ARRAY-TYPE %s
+
+ARRAY-TYPE: Array element type can't be an Array or a Blob
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-non-vector-extractelement.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=INVALID-TYPE %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-non-vector-insertelement.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=INVALID-TYPE %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-non-vector-shufflevector.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=INVALID-TYPE %s
+
+INVALID-TYPE: Invalid type for value
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-fwdref-type-mismatch.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=FWDREF-TYPE %s
+
+FWDREF-TYPE: Invalid record
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-fwdref-type-mismatch-2.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=FWDREF-TYPE-MISMATCH %s
+
+FWDREF-TYPE-MISMATCH: Type mismatch in constant table!
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-array-element-type.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=ELEMENT-TYPE %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-vector-element-type.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=ELEMENT-TYPE %s
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-pointer-element-type.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=ELEMENT-TYPE %s
+
+ELEMENT-TYPE: Invalid type
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-array-op-not-2nd-to-last.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=ARRAY-NOT-2LAST %s
+
+ARRAY-NOT-2LAST: Array op not second to last
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-too-big-fwdref.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=HUGE-FWDREF %s
+
+HUGE-FWDREF: Invalid record
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-load-pointer-type.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=LOAD-BAD-TYPE %s
+
+LOAD-BAD-TYPE: Load/Store operand is not a pointer type
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-GCTable-overflow.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=GCTABLE-OFLOW %s
+
+GCTABLE-OFLOW: Invalid ID
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-insert-0-indices.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=INSERT-0-IDXS %s
+
+INSERT-0-IDXS: INSERTVAL: Invalid instruction with 0 indices
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-extract-0-indices.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=EXTRACT-0-IDXS %s
+
+EXTRACT-0-IDXS: EXTRACTVAL: Invalid instruction with 0 indices
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-load-ptr-type.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=BAD-LOAD-PTR-TYPE %s
+
+BAD-LOAD-PTR-TYPE: Cannot load/store from pointer
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-inserted-value-type-mismatch.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=INSERT-TYPE-MISMATCH %s
+
+INSERT-TYPE-MISMATCH: Inserted value type doesn't match aggregate type
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-code-len-width.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=INVALID-CODELENWIDTH %s
+
+INVALID-CODELENWIDTH: Malformed block
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-function-argument-type.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=INVALID-ARGUMENT-TYPE %s
+
+INVALID-ARGUMENT-TYPE: Invalid function argument type
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-fixme-streaming-blob.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=STREAMING-BLOB %s
+
+STREAMING-BLOB: getPointer in streaming memory objects not allowed
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-function-comdat-id.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=INVALID-FCOMDAT-ID %s
+
+INVALID-FCOMDAT-ID: Invalid function comdat ID
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-global-var-comdat-id.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=INVALID-GVCOMDAT-ID %s
+
+INVALID-GVCOMDAT-ID: Invalid global variable comdat ID
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev-no-operands.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=ABBREV-NO-OPS %s
+
+ABBREV-NO-OPS: Abbrev record with no operands
+
+RUN: not llvm-dis -disable-output %p/Inputs/invalid-array-operand-encoding.bc 2>&1 | \
+RUN:   FileCheck --check-prefix=ARRAY-OP-ENC %s
+
+ARRAY-OP-ENC: Array element type has to be an encoding of a type
diff --git a/test/Bitcode/linkage-types-3.2.ll b/test/Bitcode/linkage-types-3.2.ll
index e255b619f41b..fb6cc5745fad 100644
--- a/test/Bitcode/linkage-types-3.2.ll
+++ b/test/Bitcode/linkage-types-3.2.ll
@@ -33,13 +33,13 @@
 ; CHECK: @available_externally.var = available_externally constant i32 0{{$}}
 
 @linkonce.var = linkonce constant i32 0
-; CHECK: @linkonce.var = linkonce constant i32 0{{$}}
+; CHECK: @linkonce.var = linkonce constant i32 0, comdat{{$}}
 
 @weak.var = weak constant i32 0
-; CHECK: @weak.var = weak constant i32 0{{$}}
+; CHECK: @weak.var = weak constant i32 0, comdat{{$}}
 
 @linkonce_odr.var = linkonce_odr constant i32 0
-; CHECK: @linkonce_odr.var = linkonce_odr constant i32 0{{$}}
+; CHECK: @linkonce_odr.var = linkonce_odr constant i32 0, comdat{{$}}
 
 @linkonce_odr_auto_hide.var = linkonce_odr_auto_hide constant i32 0
 ; CHECK: @linkonce_odr_auto_hide.var = constant i32 0{{$}}
@@ -90,19 +90,19 @@ define available_externally void @available_externally()
 }
 
 define linkonce void @linkonce()
-; CHECK: define linkonce void @linkonce() {
+; CHECK: define linkonce void @linkonce() comdat {
 {
   ret void
 }
 
 define weak void @weak()
-; CHECK: define weak void @weak() {
+; CHECK: define weak void @weak() comdat {
 {
   ret void
 }
 
 define linkonce_odr void @linkonce_odr()
-; CHECK: define linkonce_odr void @linkonce_odr() {
+; CHECK: define linkonce_odr void @linkonce_odr() comdat {
 {
   ret void
 }
diff --git a/test/Bitcode/memInstructions.3.2.ll b/test/Bitcode/memInstructions.3.2.ll
index d826dd120621..1ab05b6d1b42 100644
--- a/test/Bitcode/memInstructions.3.2.ll
+++ b/test/Bitcode/memInstructions.3.2.ll
@@ -27,53 +27,53 @@ entry:
   %ptr1 = alloca i8
   store i8 2, i8* %ptr1
 
-; CHECK: %res1 = load i8* %ptr1
-  %res1 = load i8* %ptr1
+; CHECK: %res1 = load i8, i8* %ptr1
+  %res1 = load i8, i8* %ptr1
 
-; CHECK-NEXT: %res2 = load volatile i8* %ptr1
-  %res2 = load volatile i8* %ptr1
+; CHECK-NEXT: %res2 = load volatile i8, i8* %ptr1
+  %res2 = load volatile i8, i8* %ptr1
 
-; CHECK-NEXT: %res3 = load i8* %ptr1, align 1
-  %res3 = load i8* %ptr1, align 1
+; CHECK-NEXT: %res3 = load i8, i8* %ptr1, align 1
+  %res3 = load i8, i8* %ptr1, align 1
 
-; CHECK-NEXT: %res4 = load volatile i8* %ptr1, align 1
-  %res4 = load volatile i8* %ptr1, align 1
+; CHECK-NEXT: %res4 = load volatile i8, i8* %ptr1, align 1
+  %res4 = load volatile i8, i8* %ptr1, align 1
 
-; CHECK-NEXT: %res5 = load i8* %ptr1, !nontemporal !0
-  %res5 = load i8* %ptr1, !nontemporal !0
+; CHECK-NEXT: %res5 = load i8, i8* %ptr1, !nontemporal !0
+  %res5 = load i8, i8* %ptr1, !nontemporal !0
 
-; CHECK-NEXT: %res6 = load volatile i8* %ptr1, !nontemporal !0
-  %res6 = load volatile i8* %ptr1, !nontemporal !0
+; CHECK-NEXT: %res6 = load volatile i8, i8* %ptr1, !nontemporal !0
+  %res6 = load volatile i8, i8* %ptr1, !nontemporal !0
 
-; CHECK-NEXT: %res7 = load i8* %ptr1, align 1, !nontemporal !0
-  %res7 = load i8* %ptr1, align 1, !nontemporal !0
+; CHECK-NEXT: %res7 = load i8, i8* %ptr1, align 1, !nontemporal !0
+  %res7 = load i8, i8* %ptr1, align 1, !nontemporal !0
 
-; CHECK-NEXT: %res8 = load volatile i8* %ptr1, align 1, !nontemporal !0
-  %res8 = load volatile i8* %ptr1, align 1, !nontemporal !0
+; CHECK-NEXT: %res8 = load volatile i8, i8* %ptr1, align 1, !nontemporal !0
+  %res8 = load volatile i8, i8* %ptr1, align 1, !nontemporal !0
 
-; CHECK-NEXT: %res9 = load i8* %ptr1, !invariant.load !1
-  %res9 = load i8* %ptr1, !invariant.load !1
+; CHECK-NEXT: %res9 = load i8, i8* %ptr1, !invariant.load !1
+  %res9 = load i8, i8* %ptr1, !invariant.load !1
 
-; CHECK-NEXT: %res10 = load volatile i8* %ptr1, !invariant.load !1
-  %res10 = load volatile i8* %ptr1, !invariant.load !1
+; CHECK-NEXT: %res10 = load volatile i8, i8* %ptr1, !invariant.load !1
+  %res10 = load volatile i8, i8* %ptr1, !invariant.load !1
 
-; CHECK-NEXT: %res11 = load i8* %ptr1, align 1, !invariant.load !1
-  %res11 = load i8* %ptr1, align 1, !invariant.load !1
+; CHECK-NEXT: %res11 = load i8, i8* %ptr1, align 1, !invariant.load !1
+  %res11 = load i8, i8* %ptr1, align 1, !invariant.load !1
 
-; CHECK-NEXT: %res12 = load volatile i8* %ptr1, align 1, !invariant.load !1
-  %res12 = load volatile i8* %ptr1, align 1, !invariant.load !1
+; CHECK-NEXT: %res12 = load volatile i8, i8* %ptr1, align 1, !invariant.load !1
+  %res12 = load volatile i8, i8* %ptr1, align 1, !invariant.load !1
 
-; CHECK-NEXT: %res13 = load i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
-  %res13 = load i8* %ptr1, !nontemporal !0, !invariant.load !1
+; CHECK-NEXT: %res13 = load i8, i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
+  %res13 = load i8, i8* %ptr1, !nontemporal !0, !invariant.load !1
 
-; CHECK-NEXT: %res14 = load volatile i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
-  %res14 = load volatile i8* %ptr1, !nontemporal !0, !invariant.load !1
+; CHECK-NEXT: %res14 = load volatile i8, i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
+  %res14 = load volatile i8, i8* %ptr1, !nontemporal !0, !invariant.load !1
 
-; CHECK-NEXT: %res15 = load i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
-  %res15 = load i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
+; CHECK-NEXT: %res15 = load i8, i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
+  %res15 = load i8, i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
 
-; CHECK-NEXT: %res16 = load volatile i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
-  %res16 = load volatile i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
+; CHECK-NEXT: %res16 = load volatile i8, i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
+  %res16 = load volatile i8, i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
 
   ret void
 }
@@ -83,53 +83,53 @@ entry:
   %ptr1 = alloca i8
   store i8 2, i8* %ptr1
 
-; CHECK: %res1 = load atomic i8* %ptr1 unordered, align 1
-  %res1 = load atomic i8* %ptr1 unordered, align 1
+; CHECK: %res1 = load atomic i8, i8* %ptr1 unordered, align 1
+  %res1 = load atomic i8, i8* %ptr1 unordered, align 1
 
-; CHECK-NEXT: %res2 = load atomic i8* %ptr1 monotonic, align 1
-  %res2 = load atomic i8* %ptr1 monotonic, align 1
+; CHECK-NEXT: %res2 = load atomic i8, i8* %ptr1 monotonic, align 1
+  %res2 = load atomic i8, i8* %ptr1 monotonic, align 1
 
-; CHECK-NEXT: %res3 = load atomic i8* %ptr1 acquire, align 1
-  %res3 = load atomic i8* %ptr1 acquire, align 1
+; CHECK-NEXT: %res3 = load atomic i8, i8* %ptr1 acquire, align 1
+  %res3 = load atomic i8, i8* %ptr1 acquire, align 1
 
-; CHECK-NEXT: %res4 = load atomic i8* %ptr1 seq_cst, align 1
-  %res4 = load atomic i8* %ptr1 seq_cst, align 1
+; CHECK-NEXT: %res4 = load atomic i8, i8* %ptr1 seq_cst, align 1
+  %res4 = load atomic i8, i8* %ptr1 seq_cst, align 1
 
-; CHECK-NEXT: %res5 = load atomic volatile i8* %ptr1 unordered, align 1
-  %res5 = load atomic volatile i8* %ptr1 unordered, align 1
+; CHECK-NEXT: %res5 = load atomic volatile i8, i8* %ptr1 unordered, align 1
+  %res5 = load atomic volatile i8, i8* %ptr1 unordered, align 1
 
-; CHECK-NEXT: %res6 = load atomic volatile i8* %ptr1 monotonic, align 1
-  %res6 = load atomic volatile i8* %ptr1 monotonic, align 1
+; CHECK-NEXT: %res6 = load atomic volatile i8, i8* %ptr1 monotonic, align 1
+  %res6 = load atomic volatile i8, i8* %ptr1 monotonic, align 1
 
-; CHECK-NEXT: %res7 = load atomic volatile i8* %ptr1 acquire, align 1
-  %res7 = load atomic volatile i8* %ptr1 acquire, align 1
+; CHECK-NEXT: %res7 = load atomic volatile i8, i8* %ptr1 acquire, align 1
+  %res7 = load atomic volatile i8, i8* %ptr1 acquire, align 1
 
-; CHECK-NEXT: %res8 = load atomic volatile i8* %ptr1 seq_cst, align 1
-  %res8 = load atomic volatile i8* %ptr1 seq_cst, align 1
+; CHECK-NEXT: %res8 = load atomic volatile i8, i8* %ptr1 seq_cst, align 1
+  %res8 = load atomic volatile i8, i8* %ptr1 seq_cst, align 1
 
-; CHECK-NEXT: %res9 = load atomic i8* %ptr1 singlethread unordered, align 1
-  %res9 = load atomic i8* %ptr1 singlethread unordered, align 1
+; CHECK-NEXT: %res9 = load atomic i8, i8* %ptr1 singlethread unordered, align 1
+  %res9 = load atomic i8, i8* %ptr1 singlethread unordered, align 1
 
-; CHECK-NEXT: %res10 = load atomic i8* %ptr1 singlethread monotonic, align 1
-  %res10 = load atomic i8* %ptr1 singlethread monotonic, align 1
+; CHECK-NEXT: %res10 = load atomic i8, i8* %ptr1 singlethread monotonic, align 1
+  %res10 = load atomic i8, i8* %ptr1 singlethread monotonic, align 1
 
-; CHECK-NEXT: %res11 = load atomic i8* %ptr1 singlethread acquire, align 1
-  %res11 = load atomic i8* %ptr1 singlethread acquire, align 1
+; CHECK-NEXT: %res11 = load atomic i8, i8* %ptr1 singlethread acquire, align 1
+  %res11 = load atomic i8, i8* %ptr1 singlethread acquire, align 1
 
-; CHECK-NEXT: %res12 = load atomic i8* %ptr1 singlethread seq_cst, align 1
-  %res12 = load atomic i8* %ptr1 singlethread seq_cst, align 1
+; CHECK-NEXT: %res12 = load atomic i8, i8* %ptr1 singlethread seq_cst, align 1
+  %res12 = load atomic i8, i8* %ptr1 singlethread seq_cst, align 1
 
-; CHECK-NEXT: %res13 = load atomic volatile i8* %ptr1 singlethread unordered, align 1
-  %res13 = load atomic volatile i8* %ptr1 singlethread unordered, align 1
+; CHECK-NEXT: %res13 = load atomic volatile i8, i8* %ptr1 singlethread unordered, align 1
+  %res13 = load atomic volatile i8, i8* %ptr1 singlethread unordered, align 1
 
-; CHECK-NEXT: %res14 = load atomic volatile i8* %ptr1 singlethread monotonic, align 1
-  %res14 = load atomic volatile i8* %ptr1 singlethread monotonic, align 1
+; CHECK-NEXT: %res14 = load atomic volatile i8, i8* %ptr1 singlethread monotonic, align 1
+  %res14 = load atomic volatile i8, i8* %ptr1 singlethread monotonic, align 1
 
-; CHECK-NEXT: %res15 = load atomic volatile i8* %ptr1 singlethread acquire, align 1
-  %res15 = load atomic volatile i8* %ptr1 singlethread acquire, align 1
+; CHECK-NEXT: %res15 = load atomic volatile i8, i8* %ptr1 singlethread acquire, align 1
+  %res15 = load atomic volatile i8, i8* %ptr1 singlethread acquire, align 1
 
-; CHECK-NEXT: %res16 = load atomic volatile i8* %ptr1 singlethread seq_cst, align 1
-  %res16 = load atomic volatile i8* %ptr1 singlethread seq_cst, align 1
+; CHECK-NEXT: %res16 = load atomic volatile i8, i8* %ptr1 singlethread seq_cst, align 1
+  %res16 = load atomic volatile i8, i8* %ptr1 singlethread seq_cst, align 1
 
   ret void
 }
@@ -311,16 +311,16 @@ entry:
   ret void
 }
 
-define void @getelementptr({i8, i8}* %s, <4 x i8*> %ptrs, <4 x i64> %offsets ){
+define void @getelementptr({i8, i8}, {i8, i8}* %s, <4 x i8*> %ptrs, <4 x i64> %offsets ){
 entry:
-; CHECK: %res1 = getelementptr { i8, i8 }* %s, i32 1, i32 1
-  %res1 = getelementptr {i8, i8}* %s, i32 1, i32 1
+; CHECK: %res1 = getelementptr { i8, i8 }, { i8, i8 }* %s, i32 1, i32 1
+  %res1 = getelementptr {i8, i8}, {i8, i8}* %s, i32 1, i32 1
 
-; CHECK-NEXT: %res2 = getelementptr inbounds { i8, i8 }* %s, i32 1, i32 1
-  %res2 = getelementptr inbounds {i8, i8}* %s, i32 1, i32 1
+; CHECK-NEXT: %res2 = getelementptr inbounds { i8, i8 }, { i8, i8 }* %s, i32 1, i32 1
+  %res2 = getelementptr inbounds {i8, i8}, {i8, i8}* %s, i32 1, i32 1
 
-; CHECK-NEXT: %res3 = getelementptr <4 x i8*> %ptrs, <4 x i64> %offsets
-  %res3 = getelementptr <4 x i8*> %ptrs, <4 x i64> %offsets
+; CHECK-NEXT: %res3 = getelementptr i8, <4 x i8*> %ptrs, <4 x i64> %offsets
+  %res3 = getelementptr i8, <4 x i8*> %ptrs, <4 x i64> %offsets
 
   ret void
 }
diff --git a/test/Bitcode/metadata-2.ll b/test/Bitcode/metadata-2.ll
index 07371a30d272..e90652610430 100644
--- a/test/Bitcode/metadata-2.ll
+++ b/test/Bitcode/metadata-2.ll
@@ -21,7 +21,7 @@
 	%"void*[]" = type { i64, i8** }
 @_D10ModuleInfo6__vtblZ = external constant %object.ModuleInfo.__vtbl		; <%object.ModuleInfo.__vtbl*> [#uses=1]
 @.str = internal constant [20 x i8] c"tango.core.BitManip\00"		; <[20 x i8]*> [#uses=1]
-@_D5tango4core8BitManip8__ModuleZ = global %0 { %object.ModuleInfo.__vtbl* @_D10ModuleInfo6__vtblZ, i8* null, %"byte[]" { i64 19, i8* getelementptr ([20 x i8]* @.str, i32 0, i32 0) }, %1 zeroinitializer, %"ClassInfo[]" zeroinitializer, i32 4, void ()* null, void ()* null, void ()* null, i8* null, void ()* null }		; <%0*> [#uses=1]
+@_D5tango4core8BitManip8__ModuleZ = global %0 { %object.ModuleInfo.__vtbl* @_D10ModuleInfo6__vtblZ, i8* null, %"byte[]" { i64 19, i8* getelementptr ([20 x i8], [20 x i8]* @.str, i32 0, i32 0) }, %1 zeroinitializer, %"ClassInfo[]" zeroinitializer, i32 4, void ()* null, void ()* null, void ()* null, i8* null, void ()* null }		; <%0*> [#uses=1]
 @_D5tango4core8BitManip11__moduleRefZ = internal global %ModuleReference { %ModuleReference* null, %object.ModuleInfo* bitcast (%0* @_D5tango4core8BitManip8__ModuleZ to %object.ModuleInfo*) }		; <%ModuleReference*> [#uses=2]
 @_Dmodule_ref = external global %ModuleReference*		; <%ModuleReference**> [#uses=2]
 @llvm.global_ctors = appending constant [1 x %2] [%2 { i32 65535, void ()* @_D5tango4core8BitManip16__moduleinfoCtorZ }]		; <[1 x %2]*> [#uses=0]
@@ -77,8 +77,8 @@ entry:
 
 define internal void @_D5tango4core8BitManip16__moduleinfoCtorZ() nounwind {
 moduleinfoCtorEntry:
-	%current = load %ModuleReference** @_Dmodule_ref		; <%ModuleReference*> [#uses=1]
-	store %ModuleReference* %current, %ModuleReference** getelementptr (%ModuleReference* @_D5tango4core8BitManip11__moduleRefZ, i32 0, i32 0)
+	%current = load %ModuleReference*, %ModuleReference** @_Dmodule_ref		; <%ModuleReference*> [#uses=1]
+	store %ModuleReference* %current, %ModuleReference** getelementptr (%ModuleReference, %ModuleReference* @_D5tango4core8BitManip11__moduleRefZ, i32 0, i32 0)
 	store %ModuleReference* @_D5tango4core8BitManip11__moduleRefZ, %ModuleReference** @_Dmodule_ref
 	ret void
 }
diff --git a/test/Bitcode/miscInstructions.3.2.ll b/test/Bitcode/miscInstructions.3.2.ll
index 6a077d5c9fa0..bed26c22147d 100644
--- a/test/Bitcode/miscInstructions.3.2.ll
+++ b/test/Bitcode/miscInstructions.3.2.ll
@@ -173,8 +173,8 @@ entry:
 ; CHECK-NEXT: %res2 = tail call i32 @test(i32 %x)
   %res2 = tail call i32 @test(i32 %x)
   
-; CHECK-NEXT: %res3 = call i32 (i8*, ...)* @printf(i8* %msg, i32 12, i8 42)
-  %res3 = call i32 (i8*, ...)* @printf(i8* %msg, i32 12, i8 42)
+; CHECK-NEXT: %res3 = call i32 (i8*, ...) @printf(i8* %msg, i32 12, i8 42)
+  %res3 = call i32 (i8*, ...) @printf(i8* %msg, i32 12, i8 42)
   
   ret void
 }
diff --git a/test/Bitcode/old-aliases.ll b/test/Bitcode/old-aliases.ll
index b73b1a90afb9..8527f074d04b 100644
--- a/test/Bitcode/old-aliases.ll
+++ b/test/Bitcode/old-aliases.ll
@@ -13,8 +13,8 @@
 @v3 = alias bitcast (i32* @v1 to i16*)
 ; CHECK: @v3 = alias bitcast (i32* @v1 to i16*)
 
-@v4 = alias getelementptr ([1 x i32]* @v2, i32 0, i32 0)
-; CHECK: @v4 = alias getelementptr inbounds ([1 x i32]* @v2, i32 0, i32 0)
+@v4 = alias getelementptr ([1 x i32], [1 x i32]* @v2, i32 0, i32 0)
+; CHECK: @v4 = alias getelementptr inbounds ([1 x i32], [1 x i32]* @v2, i32 0, i32 0)
 
 @v5 = alias i32 addrspace(2)* addrspacecast (i32 addrspace(0)* @v1 to i32 addrspace(2)*)
 ; CHECK: @v5 = alias addrspacecast (i32* @v1 to i32 addrspace(2)*)
diff --git a/test/Bitcode/pr18704.ll b/test/Bitcode/pr18704.ll
index f05fe53259fa..e57ce3cec4c0 100644
--- a/test/Bitcode/pr18704.ll
+++ b/test/Bitcode/pr18704.ll
@@ -1,6 +1,6 @@
 ; RUN:  not llvm-dis < %s.bc 2>&1 | FileCheck %s
 
-; CHECK: llvm-dis{{(\.EXE|\.exe)?}}: Never resolved value found in function
+; CHECK: llvm-dis{{(\.EXE|\.exe)?}}: error: Never resolved value found in function
 
 ; pr18704.ll.bc has an instruction referring to invalid type.
 ; The test checks that LLVM reports the error and doesn't access freed memory
diff --git a/test/Bitcode/upgrade-loop-metadata.ll b/test/Bitcode/upgrade-loop-metadata.ll
index be2a99a47afb..8dee90757876 100644
--- a/test/Bitcode/upgrade-loop-metadata.ll
+++ b/test/Bitcode/upgrade-loop-metadata.ll
@@ -10,7 +10,7 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 16
   br i1 %cmp, label %for.body, label %for.end, !llvm.loop !1
 
@@ -18,7 +18,7 @@ for.body:                                         ; preds = %for.cond
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %inc = add nsw i32 %1, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
diff --git a/test/Bitcode/use-list-order.ll b/test/Bitcode/use-list-order.ll
index 6617b9c5edf8..09ec44897e73 100644
--- a/test/Bitcode/use-list-order.ll
+++ b/test/Bitcode/use-list-order.ll
@@ -1,7 +1,7 @@
 ; RUN: verify-uselistorder < %s
 
 @a = global [4 x i1] [i1 0, i1 1, i1 0, i1 1]
-@b = alias i1* getelementptr ([4 x i1]* @a, i64 0, i64 2)
+@b = alias i1* getelementptr ([4 x i1], [4 x i1]* @a, i64 0, i64 2)
 
 ; Check use-list order of constants used by globals.
 @glob1 = global i5 7
@@ -79,13 +79,13 @@ entry:
 
 define i1 @loadb() {
 entry:
-  %b = load i1* @b
+  %b = load i1, i1* @b
   ret i1 %b
 }
 
 define i1 @loada() {
 entry:
-  %a = load i1* getelementptr ([4 x i1]* @a, i64 0, i64 2)
+  %a = load i1, i1* getelementptr ([4 x i1], [4 x i1]* @a, i64 0, i64 2)
   ret i1 %a
 }
 
@@ -115,7 +115,7 @@ first:
 
 define i4 @globalAndFunctionFunctionUser() {
 entry:
-  %local = load i4* @globalAndFunction
+  %local = load i4, i4* @globalAndFunction
   ret i4 %local
 }
 
@@ -134,11 +134,11 @@ loop2:
 
 ; Check that block addresses work.
 @ba1 = constant i8* blockaddress (@bafunc1, %bb)
-@ba2 = constant i8* getelementptr (i8* blockaddress (@bafunc2, %bb), i61 0)
-@ba3 = constant i8* getelementptr (i8* blockaddress (@bafunc2, %bb), i61 0)
+@ba2 = constant i8* getelementptr (i8, i8* blockaddress (@bafunc2, %bb), i61 0)
+@ba3 = constant i8* getelementptr (i8, i8* blockaddress (@bafunc2, %bb), i61 0)
 
 define i8* @babefore() {
-  ret i8* getelementptr (i8* blockaddress (@bafunc2, %bb), i61 0)
+  ret i8* getelementptr (i8, i8* blockaddress (@bafunc2, %bb), i61 0)
 bb1:
   ret i8* blockaddress (@bafunc1, %bb)
 bb2:
diff --git a/test/Bitcode/weak-macho-3.5.ll b/test/Bitcode/weak-macho-3.5.ll
new file mode 100644
index 000000000000..0c09fe4cd9dc
--- /dev/null
+++ b/test/Bitcode/weak-macho-3.5.ll
@@ -0,0 +1,11 @@
+; RUN:  llvm-dis < %s.bc| FileCheck %s
+
+; weak-macho-3.5.ll.bc was generated by passing this file to llvm-as-3.5
+; The test checks that LLVM does not place weak GlobalVariables into Comdats for
+; macho object files, they don't support it.
+
+target triple = "x86_64-apple-macosx10.9.0"
+; CHECK: target triple = "x86_64-apple-macosx10.9.0"
+
+@x = weak global i32 0
+; CHECK: @x = weak global i32 0{{$}}
diff --git a/test/Bitcode/weak-macho-3.5.ll.bc b/test/Bitcode/weak-macho-3.5.ll.bc
new file mode 100644
index 000000000000..ee6607235774
--- /dev/null
+++ b/test/Bitcode/weak-macho-3.5.ll.bc
diff --git a/test/BugPoint/metadata.ll b/test/BugPoint/metadata.ll
index 00015d1e8713..d8aca524ee28 100644
--- a/test/BugPoint/metadata.ll
+++ b/test/BugPoint/metadata.ll
@@ -5,10 +5,10 @@
 ; Bugpoint should keep the call's metadata attached to the call.
 
 ; CHECK: call void @foo(), !dbg ![[LOC:[0-9]+]], !attach ![[CALL:[0-9]+]]
-; CHECK: ![[LOC]] = !MDLocation(line: 104, column: 105, scope: ![[SCOPE:[0-9]+]], inlinedAt: ![[SCOPE]])
-; CHECK: ![[SCOPE]] = !{!"0x11\000\00me\001\00\000\00\000", ![[FILE:[0-9]+]], ![[LIST:[0-9]+]], ![[LIST]], null, null, null}
-; CHECK: ![[FILE]] = !{!"source.c", !"/dir"}
-; CHECK: ![[LIST]] = !{i32 0}
+; CHECK: ![[LOC]] = !DILocation(line: 104, column: 105, scope: ![[SCOPE:[0-9]+]])
+; CHECK: ![[SCOPE]] = !DISubprogram(name: "test"
+; CHECK-SAME:                       file: ![[FILE:[0-9]+]]
+; CHECK: ![[FILE]] = !DIFile(filename: "source.c", directory: "/dir")
 ; CHECK: ![[CALL]] = !{!"the call to foo"}
 
 %rust_task = type {}
@@ -31,12 +31,12 @@ declare void @foo()
 !3 = !{!"noise"}
 !4 = !{!"filler"}
 
-!9 = !{!"0x11\000\00me\001\00\000\00\000", !15, !16, !16, null, null, null} ; [ DW_TAG_compile_unit ]
-!10 = !MDLocation(line: 100, column: 101, scope: !9, inlinedAt: !9)
-!11 = !MDLocation(line: 102, column: 103, scope: !9, inlinedAt: !9)
-!12 = !MDLocation(line: 104, column: 105, scope: !9, inlinedAt: !9)
-!13 = !MDLocation(line: 106, column: 107, scope: !9, inlinedAt: !9)
-!14 = !MDLocation(line: 108, column: 109, scope: !9, inlinedAt: !9)
-!15 = !{!"source.c", !"/dir"}
-!16 = !{i32 0}
-!17 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DISubprogram(name: "test", file: !15)
+!10 = !DILocation(line: 100, column: 101, scope: !9)
+!11 = !DILocation(line: 102, column: 103, scope: !9)
+!12 = !DILocation(line: 104, column: 105, scope: !9)
+!13 = !DILocation(line: 106, column: 107, scope: !9)
+!14 = !DILocation(line: 108, column: 109, scope: !9)
+!15 = !DIFile(filename: "source.c", directory: "/dir")
+!16 = !{}
+!17 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/BugPoint/replace-funcs-with-null.ll b/test/BugPoint/replace-funcs-with-null.ll
new file mode 100644
index 000000000000..3433c456e90f
--- /dev/null
+++ b/test/BugPoint/replace-funcs-with-null.ll
@@ -0,0 +1,17 @@
+; Test that bugpoint can reduce the set of functions by replacing them with null.
+;
+; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%shlibext %s -output-prefix %t -replace-funcs-with-null -bugpoint-crash-decl-funcs -silence-passes -safe-run-llc
+; REQUIRES: loadable_module
+
+@foo2 = alias i32 ()* @foo
+
+define i32 @foo() { ret i32 1 }
+
+define i32 @test() {
+	call i32 @test()
+	ret i32 %1
+}
+
+define i32 @bar() { ret i32 2 }
+
+@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @foo to i8*)], section "llvm.metadata"
diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt
index f85a1d97e90c..6e7dfd7c5396 100644
--- a/test/CMakeLists.txt
+++ b/test/CMakeLists.txt
@@ -28,6 +28,7 @@ set(LLVM_TEST_DEPENDS
           llvm-bcanalyzer
           llvm-c-test
           llvm-cov
+          llvm-cxxdump
           llvm-diff
           llvm-dis
           llvm-dsymutil
@@ -46,12 +47,12 @@ set(LLVM_TEST_DEPENDS
           llvm-size
           llvm-symbolizer
           llvm-tblgen
-          llvm-vtabledump
           macho-dump
           opt
           FileCheck
           count
           not
+          yaml-bench
           yaml2obj
           obj2yaml
           verify-uselistorder
@@ -70,6 +71,10 @@ if(TARGET llvm-go)
   set(LLVM_TEST_DEPENDS ${LLVM_TEST_DEPENDS} llvm-go)
 endif()
 
+if(APPLE)
+  set(LLVM_TEST_DEPENDS ${LLVM_TEST_DEPENDS} LTO)
+endif()
+
 if(TARGET ocaml_llvm)
   set(LLVM_TEST_DEPENDS ${LLVM_TEST_DEPENDS}
           ocaml_llvm
@@ -97,6 +102,12 @@ add_lit_testsuite(check-llvm "Running the LLVM regression tests"
   )
 set_target_properties(check-llvm PROPERTIES FOLDER "Tests")
 
+add_lit_testsuites(LLVM ${CMAKE_CURRENT_SOURCE_DIR}
+  PARAMS llvm_site_config=${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg
+         llvm_unit_site_config=${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg
+  DEPENDS ${LLVM_TEST_DEPENDS}
+  )
+
 # Setup a legacy alias for 'check-llvm'. This will likely change to be an
 # alias for 'check-all' at some point in the future.
 add_custom_target(check)
diff --git a/test/CodeGen/AArch64/128bit_load_store.ll b/test/CodeGen/AArch64/128bit_load_store.ll
index a6f077698e40..94fd386e0eaf 100644
--- a/test/CodeGen/AArch64/128bit_load_store.ll
+++ b/test/CodeGen/AArch64/128bit_load_store.ll
@@ -12,7 +12,7 @@ define fp128 @test_load_f128(fp128* readonly %ptr) #2 {
 ; CHECK-LABEL: test_load_f128
 ; CHECK: ldr	 {{q[0-9]+}}, [{{x[0-9]+}}]
 entry:
-  %0 = load fp128* %ptr, align 16
+  %0 = load fp128, fp128* %ptr, align 16
   ret fp128 %0
 }
 
@@ -33,7 +33,7 @@ define i128 @test_vldrq_p128(i128* readonly %ptr) #2 {
 
 entry:
   %0 = bitcast i128* %ptr to fp128*
-  %1 = load fp128* %0, align 16
+  %1 = load fp128, fp128* %0, align 16
   %2 = bitcast fp128 %1 to i128
   ret i128 %2
 }
@@ -44,8 +44,8 @@ define void @test_ld_st_p128(i128* nocapture %ptr) #0 {
 ; CHECK-NEXT: str	{{q[0-9]+}}, [{{x[0-9]+}}, #16]
 entry:
   %0 = bitcast i128* %ptr to fp128*
-  %1 = load fp128* %0, align 16
-  %add.ptr = getelementptr inbounds i128* %ptr, i64 1
+  %1 = load fp128, fp128* %0, align 16
+  %add.ptr = getelementptr inbounds i128, i128* %ptr, i64 1
   %2 = bitcast i128* %add.ptr to fp128*
   store fp128 %1, fp128* %2, align 16
   ret void
diff --git a/test/CodeGen/AArch64/PBQP-chain.ll b/test/CodeGen/AArch64/PBQP-chain.ll
index c4ba026ea428..3e5fa741c243 100644
--- a/test/CodeGen/AArch64/PBQP-chain.ll
+++ b/test/CodeGen/AArch64/PBQP-chain.ll
@@ -22,79 +22,79 @@ target triple = "aarch64"
 ; CHECK-ODD: fmadd {{d[0-9]*[13579]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[13579]}}
 define void @fir(double* nocapture %rx, double* nocapture %ry, double* nocapture %c, double* nocapture %x, double* nocapture %y) {
 entry:
-  %0 = load double* %c, align 8
-  %1 = load double* %x, align 8
+  %0 = load double, double* %c, align 8
+  %1 = load double, double* %x, align 8
   %mul = fmul fast double %1, %0
-  %2 = load double* %y, align 8
+  %2 = load double, double* %y, align 8
   %mul7 = fmul fast double %2, %0
-  %arrayidx.1 = getelementptr inbounds double* %c, i64 1
-  %3 = load double* %arrayidx.1, align 8
-  %arrayidx2.1 = getelementptr inbounds double* %x, i64 1
-  %4 = load double* %arrayidx2.1, align 8
+  %arrayidx.1 = getelementptr inbounds double, double* %c, i64 1
+  %3 = load double, double* %arrayidx.1, align 8
+  %arrayidx2.1 = getelementptr inbounds double, double* %x, i64 1
+  %4 = load double, double* %arrayidx2.1, align 8
   %mul.1 = fmul fast double %4, %3
   %add.1 = fadd fast double %mul.1, %mul
-  %arrayidx6.1 = getelementptr inbounds double* %y, i64 1
-  %5 = load double* %arrayidx6.1, align 8
+  %arrayidx6.1 = getelementptr inbounds double, double* %y, i64 1
+  %5 = load double, double* %arrayidx6.1, align 8
   %mul7.1 = fmul fast double %5, %3
   %add8.1 = fadd fast double %mul7.1, %mul7
-  %arrayidx.2 = getelementptr inbounds double* %c, i64 2
-  %6 = load double* %arrayidx.2, align 8
-  %arrayidx2.2 = getelementptr inbounds double* %x, i64 2
-  %7 = load double* %arrayidx2.2, align 8
+  %arrayidx.2 = getelementptr inbounds double, double* %c, i64 2
+  %6 = load double, double* %arrayidx.2, align 8
+  %arrayidx2.2 = getelementptr inbounds double, double* %x, i64 2
+  %7 = load double, double* %arrayidx2.2, align 8
   %mul.2 = fmul fast double %7, %6
   %add.2 = fadd fast double %mul.2, %add.1
-  %arrayidx6.2 = getelementptr inbounds double* %y, i64 2
-  %8 = load double* %arrayidx6.2, align 8
+  %arrayidx6.2 = getelementptr inbounds double, double* %y, i64 2
+  %8 = load double, double* %arrayidx6.2, align 8
   %mul7.2 = fmul fast double %8, %6
   %add8.2 = fadd fast double %mul7.2, %add8.1
-  %arrayidx.3 = getelementptr inbounds double* %c, i64 3
-  %9 = load double* %arrayidx.3, align 8
-  %arrayidx2.3 = getelementptr inbounds double* %x, i64 3
-  %10 = load double* %arrayidx2.3, align 8
+  %arrayidx.3 = getelementptr inbounds double, double* %c, i64 3
+  %9 = load double, double* %arrayidx.3, align 8
+  %arrayidx2.3 = getelementptr inbounds double, double* %x, i64 3
+  %10 = load double, double* %arrayidx2.3, align 8
   %mul.3 = fmul fast double %10, %9
   %add.3 = fadd fast double %mul.3, %add.2
-  %arrayidx6.3 = getelementptr inbounds double* %y, i64 3
-  %11 = load double* %arrayidx6.3, align 8
+  %arrayidx6.3 = getelementptr inbounds double, double* %y, i64 3
+  %11 = load double, double* %arrayidx6.3, align 8
   %mul7.3 = fmul fast double %11, %9
   %add8.3 = fadd fast double %mul7.3, %add8.2
-  %arrayidx.4 = getelementptr inbounds double* %c, i64 4
-  %12 = load double* %arrayidx.4, align 8
-  %arrayidx2.4 = getelementptr inbounds double* %x, i64 4
-  %13 = load double* %arrayidx2.4, align 8
+  %arrayidx.4 = getelementptr inbounds double, double* %c, i64 4
+  %12 = load double, double* %arrayidx.4, align 8
+  %arrayidx2.4 = getelementptr inbounds double, double* %x, i64 4
+  %13 = load double, double* %arrayidx2.4, align 8
   %mul.4 = fmul fast double %13, %12
   %add.4 = fadd fast double %mul.4, %add.3
-  %arrayidx6.4 = getelementptr inbounds double* %y, i64 4
-  %14 = load double* %arrayidx6.4, align 8
+  %arrayidx6.4 = getelementptr inbounds double, double* %y, i64 4
+  %14 = load double, double* %arrayidx6.4, align 8
   %mul7.4 = fmul fast double %14, %12
   %add8.4 = fadd fast double %mul7.4, %add8.3
-  %arrayidx.5 = getelementptr inbounds double* %c, i64 5
-  %15 = load double* %arrayidx.5, align 8
-  %arrayidx2.5 = getelementptr inbounds double* %x, i64 5
-  %16 = load double* %arrayidx2.5, align 8
+  %arrayidx.5 = getelementptr inbounds double, double* %c, i64 5
+  %15 = load double, double* %arrayidx.5, align 8
+  %arrayidx2.5 = getelementptr inbounds double, double* %x, i64 5
+  %16 = load double, double* %arrayidx2.5, align 8
   %mul.5 = fmul fast double %16, %15
   %add.5 = fadd fast double %mul.5, %add.4
-  %arrayidx6.5 = getelementptr inbounds double* %y, i64 5
-  %17 = load double* %arrayidx6.5, align 8
+  %arrayidx6.5 = getelementptr inbounds double, double* %y, i64 5
+  %17 = load double, double* %arrayidx6.5, align 8
   %mul7.5 = fmul fast double %17, %15
   %add8.5 = fadd fast double %mul7.5, %add8.4
-  %arrayidx.6 = getelementptr inbounds double* %c, i64 6
-  %18 = load double* %arrayidx.6, align 8
-  %arrayidx2.6 = getelementptr inbounds double* %x, i64 6
-  %19 = load double* %arrayidx2.6, align 8
+  %arrayidx.6 = getelementptr inbounds double, double* %c, i64 6
+  %18 = load double, double* %arrayidx.6, align 8
+  %arrayidx2.6 = getelementptr inbounds double, double* %x, i64 6
+  %19 = load double, double* %arrayidx2.6, align 8
   %mul.6 = fmul fast double %19, %18
   %add.6 = fadd fast double %mul.6, %add.5
-  %arrayidx6.6 = getelementptr inbounds double* %y, i64 6
-  %20 = load double* %arrayidx6.6, align 8
+  %arrayidx6.6 = getelementptr inbounds double, double* %y, i64 6
+  %20 = load double, double* %arrayidx6.6, align 8
   %mul7.6 = fmul fast double %20, %18
   %add8.6 = fadd fast double %mul7.6, %add8.5
-  %arrayidx.7 = getelementptr inbounds double* %c, i64 7
-  %21 = load double* %arrayidx.7, align 8
-  %arrayidx2.7 = getelementptr inbounds double* %x, i64 7
-  %22 = load double* %arrayidx2.7, align 8
+  %arrayidx.7 = getelementptr inbounds double, double* %c, i64 7
+  %21 = load double, double* %arrayidx.7, align 8
+  %arrayidx2.7 = getelementptr inbounds double, double* %x, i64 7
+  %22 = load double, double* %arrayidx2.7, align 8
   %mul.7 = fmul fast double %22, %21
   %add.7 = fadd fast double %mul.7, %add.6
-  %arrayidx6.7 = getelementptr inbounds double* %y, i64 7
-  %23 = load double* %arrayidx6.7, align 8
+  %arrayidx6.7 = getelementptr inbounds double, double* %y, i64 7
+  %23 = load double, double* %arrayidx6.7, align 8
   %mul7.7 = fmul fast double %23, %21
   %add8.7 = fadd fast double %mul7.7, %add8.6
   store double %add.7, double* %rx, align 8
diff --git a/test/CodeGen/AArch64/PBQP-coalesce-benefit.ll b/test/CodeGen/AArch64/PBQP-coalesce-benefit.ll
index 45ac5e65c002..bd50b2d84b74 100644
--- a/test/CodeGen/AArch64/PBQP-coalesce-benefit.ll
+++ b/test/CodeGen/AArch64/PBQP-coalesce-benefit.ll
@@ -3,11 +3,11 @@
 ; CHECK-LABEL: test:
 define i32 @test(i32 %acc, i32* nocapture readonly %c) {
 entry:
-  %0 = load i32* %c, align 4
+  %0 = load i32, i32* %c, align 4
 ; CHECK-NOT: mov	 w{{[0-9]*}}, w0
   %add = add nsw i32 %0, %acc
-  %arrayidx1 = getelementptr inbounds i32* %c, i64 1
-  %1 = load i32* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %c, i64 1
+  %1 = load i32, i32* %arrayidx1, align 4
   %add2 = add nsw i32 %add, %1
   ret i32 %add2
 }
diff --git a/test/CodeGen/AArch64/PBQP-csr.ll b/test/CodeGen/AArch64/PBQP-csr.ll
index 64335ae353a1..16d7f8cb7a5a 100644
--- a/test/CodeGen/AArch64/PBQP-csr.ll
+++ b/test/CodeGen/AArch64/PBQP-csr.ll
@@ -11,27 +11,27 @@
 define void @test_csr(%pl* nocapture readnone %this, %rs* nocapture %r) align 2 {
 ;CHECK-NOT: stp {{d[0-9]+}}, {{d[0-9]+}}
 entry:
-  %x.i = getelementptr inbounds %rs* %r, i64 0, i32 7, i32 0
-  %y.i = getelementptr inbounds %rs* %r, i64 0, i32 7, i32 1
-  %z.i = getelementptr inbounds %rs* %r, i64 0, i32 7, i32 2
-  %x.i61 = getelementptr inbounds %rs* %r, i64 0, i32 8, i32 0
-  %y.i62 = getelementptr inbounds %rs* %r, i64 0, i32 8, i32 1
-  %z.i63 = getelementptr inbounds %rs* %r, i64 0, i32 8, i32 2
-  %x.i58 = getelementptr inbounds %rs* %r, i64 0, i32 9, i32 0
-  %y.i59 = getelementptr inbounds %rs* %r, i64 0, i32 9, i32 1
-  %z.i60 = getelementptr inbounds %rs* %r, i64 0, i32 9, i32 2
-  %na = getelementptr inbounds %rs* %r, i64 0, i32 0
+  %x.i = getelementptr inbounds %rs, %rs* %r, i64 0, i32 7, i32 0
+  %y.i = getelementptr inbounds %rs, %rs* %r, i64 0, i32 7, i32 1
+  %z.i = getelementptr inbounds %rs, %rs* %r, i64 0, i32 7, i32 2
+  %x.i61 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 8, i32 0
+  %y.i62 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 8, i32 1
+  %z.i63 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 8, i32 2
+  %x.i58 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 9, i32 0
+  %y.i59 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 9, i32 1
+  %z.i60 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 9, i32 2
+  %na = getelementptr inbounds %rs, %rs* %r, i64 0, i32 0
   %0 = bitcast double* %x.i to i8*
   call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 72, i32 8, i1 false)
-  %1 = load i32* %na, align 4
+  %1 = load i32, i32* %na, align 4
   %cmp70 = icmp sgt i32 %1, 0
   br i1 %cmp70, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry
-  %fn = getelementptr inbounds %rs* %r, i64 0, i32 4
-  %2 = load %v** %fn, align 8
-  %fs = getelementptr inbounds %rs* %r, i64 0, i32 5
-  %3 = load %v** %fs, align 8
+  %fn = getelementptr inbounds %rs, %rs* %r, i64 0, i32 4
+  %2 = load %v*, %v** %fn, align 8
+  %fs = getelementptr inbounds %rs, %rs* %r, i64 0, i32 5
+  %3 = load %v*, %v** %fs, align 8
   %4 = sext i32 %1 to i64
   br label %for.body
 
@@ -42,31 +42,31 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %7 = phi <2 x double> [ zeroinitializer, %for.body.lr.ph ], [ %22, %for.body ]
   %8 = phi <2 x double> [ zeroinitializer, %for.body.lr.ph ], [ %26, %for.body ]
   %9 = phi <2 x double> [ zeroinitializer, %for.body.lr.ph ], [ %28, %for.body ]
-  %x.i54 = getelementptr inbounds %v* %2, i64 %indvars.iv, i32 0
-  %x1.i = getelementptr inbounds %v* %3, i64 %indvars.iv, i32 0
-  %y.i56 = getelementptr inbounds %v* %2, i64 %indvars.iv, i32 1
+  %x.i54 = getelementptr inbounds %v, %v* %2, i64 %indvars.iv, i32 0
+  %x1.i = getelementptr inbounds %v, %v* %3, i64 %indvars.iv, i32 0
+  %y.i56 = getelementptr inbounds %v, %v* %2, i64 %indvars.iv, i32 1
   %10 = bitcast double* %x.i54 to <2 x double>*
-  %11 = load <2 x double>* %10, align 8
-  %y2.i = getelementptr inbounds %v* %3, i64 %indvars.iv, i32 1
+  %11 = load <2 x double>, <2 x double>* %10, align 8
+  %y2.i = getelementptr inbounds %v, %v* %3, i64 %indvars.iv, i32 1
   %12 = bitcast double* %x1.i to <2 x double>*
-  %13 = load <2 x double>* %12, align 8
+  %13 = load <2 x double>, <2 x double>* %12, align 8
   %14 = fadd fast <2 x double> %13, %11
-  %z.i57 = getelementptr inbounds %v* %2, i64 %indvars.iv, i32 2
-  %15 = load double* %z.i57, align 8
-  %z4.i = getelementptr inbounds %v* %3, i64 %indvars.iv, i32 2
-  %16 = load double* %z4.i, align 8
+  %z.i57 = getelementptr inbounds %v, %v* %2, i64 %indvars.iv, i32 2
+  %15 = load double, double* %z.i57, align 8
+  %z4.i = getelementptr inbounds %v, %v* %3, i64 %indvars.iv, i32 2
+  %16 = load double, double* %z4.i, align 8
   %add5.i = fadd fast double %16, %15
   %17 = fadd fast <2 x double> %6, %11
   %18 = bitcast double* %x.i to <2 x double>*
   store <2 x double> %17, <2 x double>* %18, align 8
-  %19 = load double* %x1.i, align 8
+  %19 = load double, double* %x1.i, align 8
   %20 = insertelement <2 x double> undef, double %15, i32 0
   %21 = insertelement <2 x double> %20, double %19, i32 1
   %22 = fadd fast <2 x double> %7, %21
   %23 = bitcast double* %z.i to <2 x double>*
   store <2 x double> %22, <2 x double>* %23, align 8
   %24 = bitcast double* %y2.i to <2 x double>*
-  %25 = load <2 x double>* %24, align 8
+  %25 = load <2 x double>, <2 x double>* %24, align 8
   %26 = fadd fast <2 x double> %8, %25
   %27 = bitcast double* %y.i62 to <2 x double>*
   store <2 x double> %26, <2 x double>* %27, align 8
diff --git a/test/CodeGen/AArch64/Redundantstore.ll b/test/CodeGen/AArch64/Redundantstore.ll
index 72f7f4679e6d..b2072682cd91 100644
--- a/test/CodeGen/AArch64/Redundantstore.ll
+++ b/test/CodeGen/AArch64/Redundantstore.ll
@@ -8,16 +8,16 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 ; CHECK-NOT: stur
 define i8* @test(i32 %size) {
 entry:
-  %0 = load i8** @end_of_array, align 8
+  %0 = load i8*, i8** @end_of_array, align 8
   %conv = sext i32 %size to i64
   %and = and i64 %conv, -8
   %conv2 = trunc i64 %and to i32
   %add.ptr.sum = add nsw i64 %and, -4
-  %add.ptr3 = getelementptr inbounds i8* %0, i64 %add.ptr.sum
+  %add.ptr3 = getelementptr inbounds i8, i8* %0, i64 %add.ptr.sum
   %size4 = bitcast i8* %add.ptr3 to i32*
   store i32 %conv2, i32* %size4, align 4
   %add.ptr.sum9 = add nsw i64 %and, -4
-  %add.ptr5 = getelementptr inbounds i8* %0, i64 %add.ptr.sum9
+  %add.ptr5 = getelementptr inbounds i8, i8* %0, i64 %add.ptr.sum9
   %size6 = bitcast i8* %add.ptr5 to i32*
   store i32 %conv2, i32* %size6, align 4
   ret i8* %0
diff --git a/test/CodeGen/AArch64/a57-csel.ll b/test/CodeGen/AArch64/a57-csel.ll
index 9d16d1a0f104..f5496f777765 100644
--- a/test/CodeGen/AArch64/a57-csel.ll
+++ b/test/CodeGen/AArch64/a57-csel.ll
@@ -3,7 +3,7 @@
 ; Check that the select is expanded into a branch sequence.
 define i64 @f(i64 %a, i64 %b, i64* %c, i64 %d, i64 %e) {
   ; CHECK: cbz
-  %x0 = load i64* %c
+  %x0 = load i64, i64* %c
   %x1 = icmp eq i64 %x0, 0
   %x2 = select i1 %x1, i64 %a, i64 %b
   %x3 = add i64 %x2, %d
diff --git a/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll b/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll
index 73ee522cbf55..b075573cc674 100644
--- a/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll
+++ b/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll
@@ -8,15 +8,15 @@ entry:
   br label %for.body, !dbg !39
 
 for.body:                                         ; preds = %for.body, %entry
-  %arrayidx5 = getelementptr inbounds i32* null, i64 1, !dbg !43
-  %0 = load i32* null, align 4, !dbg !45, !tbaa !46
+  %arrayidx5 = getelementptr inbounds i32, i32* null, i64 1, !dbg !43
+  %0 = load i32, i32* null, align 4, !dbg !45, !tbaa !46
   %s1 = sub nsw i32 0, %0, !dbg !50
   %n1 = sext i32 %s1 to i64, !dbg !50
-  %arrayidx21 = getelementptr inbounds i32* null, i64 3, !dbg !51
+  %arrayidx21 = getelementptr inbounds i32, i32* null, i64 3, !dbg !51
   %add53 = add nsw i64 %n1, 0, !dbg !52
   %add55 = add nsw i64 %n1, 0, !dbg !53
   %mul63 = mul nsw i64 %add53, -20995, !dbg !54
-  tail call void @llvm.dbg.value(metadata i64 %mul63, i64 0, metadata !30, metadata !{!"0x102"}), !dbg !55
+  tail call void @llvm.dbg.value(metadata i64 %mul63, i64 0, metadata !30, metadata !DIExpression()), !dbg !55
   %mul65 = mul nsw i64 %add55, -3196, !dbg !56
   %add67 = add nsw i64 0, %mul65, !dbg !57
   %add80 = add i64 0, 1024, !dbg !58
@@ -44,63 +44,60 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!36, !37}
 !llvm.ident = !{!38}
 
-!0 = !{!"0x11\0012\00clang version 3.6.0 \001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [] [] []
-!1 = !{!"test.c", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.6.0 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.c", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00\00\00\00140\000\001\000\006\00256\001\00141", !1, !5, !6, null, void ()* @test, null, null, !12} ; [ DW_TAG_subprogram ] [] [] [def] [scope 141] []
-!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [] []
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [] [] [from ]
+!4 = !DISubprogram(name: "", line: 140, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 141, file: !1, scope: !1, type: !6, function: void ()* @test, variables: !12)
+!6 = !DISubroutineType(types: !7)
 !7 = !{null, !8}
-!8 = !{!"0xf\00\000\0064\0064\000\000", null, null, !9} ; [ DW_TAG_pointer_type ] [] [] []
-!9 = !{!"0x16\00\0030\000\000\000\000", !10, null, !11} ; [ DW_TAG_typedef ] [] [] [] [from int]
-!10 = !{!"", !""}
-!11 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [] [int] []
+!8 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !9)
+!9 = !DIDerivedType(tag: DW_TAG_typedef, line: 30, file: !1, baseType: !11)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !12 = !{!13, !14, !18, !19, !20, !21, !22, !23, !24, !25, !26, !27, !28, !29, !30, !31, !32, !33, !34, !35}
-!13 = !{!"0x101\00\0016777356\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [] [data] []
-!14 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] []
-!15 = !{!"0x16\00\00183\000\000\000\000", !16, null, !17} ; [ DW_TAG_typedef ] [] [INT32] [] [from long int]
-!16 = !{!"", !""}
-!17 = !{!"0x24\00\000\0064\0064\000\000\005", null, null} ; [ DW_TAG_base_type ] [] [long int] []
-!18 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] []
-!19 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] []
-!20 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] []
-!21 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] []
-!22 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] []
-!23 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] []
-!24 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [  ] [] []
-!25 = !{!"0x100\00\00143\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [  ] [] []
-!26 = !{!"0x100\00\00143\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [  ] [] []
-!27 = !{!"0x100\00\00143\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [  ] [] []
-!28 = !{!"0x100\00\00143\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [  ] [] []
-!29 = !{!"0x100\00\00144\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [  ] [] []
-!30 = !{!"0x100\00\00144\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [  ] [] []
-!31 = !{!"0x100\00\00144\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [  ] [] []
-!32 = !{!"0x100\00\00144\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] []
-!33 = !{!"0x100\00\00144\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [  ] [] []
-!34 = !{!"0x100\00\00145\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [  ] [] []
-!35 = !{!"0x100\00\00146\000", !4, !5, !11} ; [ DW_TAG_auto_variable ] [  ] [] []
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "", line: 140, arg: 1, scope: !4, file: !1, type: !8)
+!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15)
+!15 = !DIDerivedType(tag: DW_TAG_typedef, line: 183, file: !1, baseType: !17)
+!17 = !DIBasicType(tag: DW_TAG_base_type, size: 64, align: 64, encoding: DW_ATE_signed)
+!18 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15)
+!19 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15)
+!20 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15)
+!21 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15)
+!22 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15)
+!23 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15)
+!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15)
+!25 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 143, scope: !4, file: !1, type: !15)
+!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 143, scope: !4, file: !1, type: !15)
+!27 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 143, scope: !4, file: !1, type: !15)
+!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 143, scope: !4, file: !1, type: !15)
+!29 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 144, scope: !4, file: !1, type: !15)
+!30 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 144, scope: !4, file: !1, type: !15)
+!31 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 144, scope: !4, file: !1, type: !15)
+!32 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 144, scope: !4, file: !1, type: !15)
+!33 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 144, scope: !4, file: !1, type: !15)
+!34 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 145, scope: !4, file: !1, type: !8)
+!35 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "", line: 146, scope: !4, file: !1, type: !11)
 !36 = !{i32 2, !"Dwarf Version", i32 4}
-!37 = !{i32 2, !"Debug Info Version", i32 2}
+!37 = !{i32 2, !"Debug Info Version", i32 3}
 !38 = !{!"clang version 3.6.0 "}
-!39 = !MDLocation(line: 154, column: 8, scope: !40)
-!40 = !{!"0xb\00154\008\002", !1, !41} ; [ DW_TAG_lexical_block ] [  ] []
-!41 = !{!"0xb\00154\008\001", !1, !42} ; [ DW_TAG_lexical_block ] [  ] []
-!42 = !{!"0xb\00154\003\000", !1, !4} ; [ DW_TAG_lexical_block ] [  ] []
-!43 = !MDLocation(line: 157, column: 5, scope: !44)
-!44 = !{!"0xb\00154\0042\000", !1, !42} ; [ DW_TAG_lexical_block ] [  ] []
-!45 = !MDLocation(line: 159, column: 5, scope: !44)
+!39 = !DILocation(line: 154, column: 8, scope: !40)
+!40 = distinct !DILexicalBlock(line: 154, column: 8, file: !1, scope: !41)
+!41 = distinct !DILexicalBlock(line: 154, column: 8, file: !1, scope: !42)
+!42 = distinct !DILexicalBlock(line: 154, column: 3, file: !1, scope: !4)
+!43 = !DILocation(line: 157, column: 5, scope: !44)
+!44 = distinct !DILexicalBlock(line: 154, column: 42, file: !1, scope: !42)
+!45 = !DILocation(line: 159, column: 5, scope: !44)
 !46 = !{!47, !47, i64 0}
 !47 = !{!"int", !48, i64 0}
 !48 = !{!"omnipotent char", !49, i64 0}
 !49 = !{!"Simple C/C++ TBAA"}
-!50 = !MDLocation(line: 160, column: 5, scope: !44)
-!51 = !MDLocation(line: 161, column: 5, scope: !44)
-!52 = !MDLocation(line: 188, column: 5, scope: !44)
-!53 = !MDLocation(line: 190, column: 5, scope: !44)
-!54 = !MDLocation(line: 198, column: 5, scope: !44)
-!55 = !MDLocation(line: 144, column: 13, scope: !4)
-!56 = !MDLocation(line: 200, column: 5, scope: !44)
-!57 = !MDLocation(line: 203, column: 5, scope: !44)
-!58 = !MDLocation(line: 207, column: 5, scope: !44)
-!59 = !MDLocation(line: 208, column: 5, scope: !44)
+!50 = !DILocation(line: 160, column: 5, scope: !44)
+!51 = !DILocation(line: 161, column: 5, scope: !44)
+!52 = !DILocation(line: 188, column: 5, scope: !44)
+!53 = !DILocation(line: 190, column: 5, scope: !44)
+!54 = !DILocation(line: 198, column: 5, scope: !44)
+!55 = !DILocation(line: 144, column: 13, scope: !4)
+!56 = !DILocation(line: 200, column: 5, scope: !44)
+!57 = !DILocation(line: 203, column: 5, scope: !44)
+!58 = !DILocation(line: 207, column: 5, scope: !44)
+!59 = !DILocation(line: 208, column: 5, scope: !44)
diff --git a/test/CodeGen/AArch64/aarch64-2014-12-02-combine-soften.ll b/test/CodeGen/AArch64/aarch64-2014-12-02-combine-soften.ll
index 455325166505..b2ee517f8868 100644
--- a/test/CodeGen/AArch64/aarch64-2014-12-02-combine-soften.ll
+++ b/test/CodeGen/AArch64/aarch64-2014-12-02-combine-soften.ll
@@ -9,7 +9,7 @@ define void @foo() {
 entry:
 ;CHECK-LABEL: foo:
 ;CHECK: __floatsisf
-  %0 = load i32* @x, align 4
+  %0 = load i32, i32* @x, align 4
   %conv = sitofp i32 %0 to float
   store float %conv, float* bitcast (i32* @t to float*), align 4
   ret void
diff --git a/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll b/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
index 7108bc0e91a9..b0e9d4aa7703 100644
--- a/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
+++ b/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
@@ -29,15 +29,15 @@ target triple = "aarch64"
 
 define void @f1(double* nocapture readonly %p, double* nocapture %q) #0 {
 entry:
-  %0 = load double* %p, align 8
-  %arrayidx1 = getelementptr inbounds double* %p, i64 1
-  %1 = load double* %arrayidx1, align 8
-  %arrayidx2 = getelementptr inbounds double* %p, i64 2
-  %2 = load double* %arrayidx2, align 8
-  %arrayidx3 = getelementptr inbounds double* %p, i64 3
-  %3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %p, i64 4
-  %4 = load double* %arrayidx4, align 8
+  %0 = load double, double* %p, align 8
+  %arrayidx1 = getelementptr inbounds double, double* %p, i64 1
+  %1 = load double, double* %arrayidx1, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %p, i64 2
+  %2 = load double, double* %arrayidx2, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %p, i64 3
+  %3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %p, i64 4
+  %4 = load double, double* %arrayidx4, align 8
   %mul = fmul fast double %0, %1
   %add = fadd fast double %mul, %4
   %mul5 = fmul fast double %1, %2
@@ -47,18 +47,18 @@ entry:
   %mul8 = fmul fast double %2, %3
   %add9 = fadd fast double %mul8, %sub
   store double %add9, double* %q, align 8
-  %arrayidx11 = getelementptr inbounds double* %p, i64 5
-  %5 = load double* %arrayidx11, align 8
-  %arrayidx12 = getelementptr inbounds double* %p, i64 6
-  %6 = load double* %arrayidx12, align 8
-  %arrayidx13 = getelementptr inbounds double* %p, i64 7
-  %7 = load double* %arrayidx13, align 8
+  %arrayidx11 = getelementptr inbounds double, double* %p, i64 5
+  %5 = load double, double* %arrayidx11, align 8
+  %arrayidx12 = getelementptr inbounds double, double* %p, i64 6
+  %6 = load double, double* %arrayidx12, align 8
+  %arrayidx13 = getelementptr inbounds double, double* %p, i64 7
+  %7 = load double, double* %arrayidx13, align 8
   %mul15 = fmul fast double %6, %7
   %mul16 = fmul fast double %0, %5
   %add17 = fadd fast double %mul16, %mul15
   %mul18 = fmul fast double %5, %6
   %add19 = fadd fast double %mul18, %add17
-  %arrayidx20 = getelementptr inbounds double* %q, i64 1
+  %arrayidx20 = getelementptr inbounds double, double* %q, i64 1
   store double %add19, double* %arrayidx20, align 8
   ret void
 }
@@ -81,21 +81,21 @@ entry:
 
 define void @f2(double* nocapture readonly %p, double* nocapture %q) #0 {
 entry:
-  %0 = load double* %p, align 8
-  %arrayidx1 = getelementptr inbounds double* %p, i64 1
-  %1 = load double* %arrayidx1, align 8
-  %arrayidx2 = getelementptr inbounds double* %p, i64 2
-  %2 = load double* %arrayidx2, align 8
-  %arrayidx3 = getelementptr inbounds double* %p, i64 3
-  %3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %p, i64 4
-  %4 = load double* %arrayidx4, align 8
-  %arrayidx5 = getelementptr inbounds double* %p, i64 5
-  %5 = load double* %arrayidx5, align 8
-  %arrayidx6 = getelementptr inbounds double* %p, i64 6
-  %6 = load double* %arrayidx6, align 8
-  %arrayidx7 = getelementptr inbounds double* %p, i64 7
-  %7 = load double* %arrayidx7, align 8
+  %0 = load double, double* %p, align 8
+  %arrayidx1 = getelementptr inbounds double, double* %p, i64 1
+  %1 = load double, double* %arrayidx1, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %p, i64 2
+  %2 = load double, double* %arrayidx2, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %p, i64 3
+  %3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %p, i64 4
+  %4 = load double, double* %arrayidx4, align 8
+  %arrayidx5 = getelementptr inbounds double, double* %p, i64 5
+  %5 = load double, double* %arrayidx5, align 8
+  %arrayidx6 = getelementptr inbounds double, double* %p, i64 6
+  %6 = load double, double* %arrayidx6, align 8
+  %arrayidx7 = getelementptr inbounds double, double* %p, i64 7
+  %7 = load double, double* %arrayidx7, align 8
   %mul = fmul fast double %0, %1
   %add = fadd fast double %mul, %7
   %mul8 = fmul fast double %5, %6
@@ -110,7 +110,7 @@ entry:
   %mul16 = fmul fast double %2, %3
   %add17 = fadd fast double %mul16, %sub
   store double %add17, double* %q, align 8
-  %arrayidx19 = getelementptr inbounds double* %q, i64 1
+  %arrayidx19 = getelementptr inbounds double, double* %q, i64 1
   store double %add15, double* %arrayidx19, align 8
   ret void
 }
@@ -127,15 +127,15 @@ entry:
 
 define void @f3(double* nocapture readonly %p, double* nocapture %q) #0 {
 entry:
-  %0 = load double* %p, align 8
-  %arrayidx1 = getelementptr inbounds double* %p, i64 1
-  %1 = load double* %arrayidx1, align 8
-  %arrayidx2 = getelementptr inbounds double* %p, i64 2
-  %2 = load double* %arrayidx2, align 8
-  %arrayidx3 = getelementptr inbounds double* %p, i64 3
-  %3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %p, i64 4
-  %4 = load double* %arrayidx4, align 8
+  %0 = load double, double* %p, align 8
+  %arrayidx1 = getelementptr inbounds double, double* %p, i64 1
+  %1 = load double, double* %arrayidx1, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %p, i64 2
+  %2 = load double, double* %arrayidx2, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %p, i64 3
+  %3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %p, i64 4
+  %4 = load double, double* %arrayidx4, align 8
   %mul = fmul fast double %0, %1
   %add = fadd fast double %mul, %4
   %mul5 = fmul fast double %1, %2
@@ -176,21 +176,21 @@ declare void @g(...) #1
 
 define void @f4(float* nocapture readonly %p, float* nocapture %q) #0 {
 entry:
-  %0 = load float* %p, align 4
-  %arrayidx1 = getelementptr inbounds float* %p, i64 1
-  %1 = load float* %arrayidx1, align 4
-  %arrayidx2 = getelementptr inbounds float* %p, i64 2
-  %2 = load float* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds float* %p, i64 3
-  %3 = load float* %arrayidx3, align 4
-  %arrayidx4 = getelementptr inbounds float* %p, i64 4
-  %4 = load float* %arrayidx4, align 4
-  %arrayidx5 = getelementptr inbounds float* %p, i64 5
-  %5 = load float* %arrayidx5, align 4
-  %arrayidx6 = getelementptr inbounds float* %p, i64 6
-  %6 = load float* %arrayidx6, align 4
-  %arrayidx7 = getelementptr inbounds float* %p, i64 7
-  %7 = load float* %arrayidx7, align 4
+  %0 = load float, float* %p, align 4
+  %arrayidx1 = getelementptr inbounds float, float* %p, i64 1
+  %1 = load float, float* %arrayidx1, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %p, i64 2
+  %2 = load float, float* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds float, float* %p, i64 3
+  %3 = load float, float* %arrayidx3, align 4
+  %arrayidx4 = getelementptr inbounds float, float* %p, i64 4
+  %4 = load float, float* %arrayidx4, align 4
+  %arrayidx5 = getelementptr inbounds float, float* %p, i64 5
+  %5 = load float, float* %arrayidx5, align 4
+  %arrayidx6 = getelementptr inbounds float, float* %p, i64 6
+  %6 = load float, float* %arrayidx6, align 4
+  %arrayidx7 = getelementptr inbounds float, float* %p, i64 7
+  %7 = load float, float* %arrayidx7, align 4
   %mul = fmul fast float %0, %1
   %add = fadd fast float %mul, %7
   %mul8 = fmul fast float %5, %6
@@ -205,7 +205,7 @@ entry:
   %mul16 = fmul fast float %2, %3
   %add17 = fadd fast float %mul16, %sub
   store float %add17, float* %q, align 4
-  %arrayidx19 = getelementptr inbounds float* %q, i64 1
+  %arrayidx19 = getelementptr inbounds float, float* %q, i64 1
   store float %add15, float* %arrayidx19, align 4
   ret void
 }
@@ -222,15 +222,15 @@ entry:
 
 define void @f5(float* nocapture readonly %p, float* nocapture %q) #0 {
 entry:
-  %0 = load float* %p, align 4
-  %arrayidx1 = getelementptr inbounds float* %p, i64 1
-  %1 = load float* %arrayidx1, align 4
-  %arrayidx2 = getelementptr inbounds float* %p, i64 2
-  %2 = load float* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds float* %p, i64 3
-  %3 = load float* %arrayidx3, align 4
-  %arrayidx4 = getelementptr inbounds float* %p, i64 4
-  %4 = load float* %arrayidx4, align 4
+  %0 = load float, float* %p, align 4
+  %arrayidx1 = getelementptr inbounds float, float* %p, i64 1
+  %1 = load float, float* %arrayidx1, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %p, i64 2
+  %2 = load float, float* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds float, float* %p, i64 3
+  %3 = load float, float* %arrayidx3, align 4
+  %arrayidx4 = getelementptr inbounds float, float* %p, i64 4
+  %4 = load float, float* %arrayidx4, align 4
   %mul = fmul fast float %0, %1
   %add = fadd fast float %mul, %4
   %mul5 = fmul fast float %1, %2
@@ -264,15 +264,15 @@ if.end:                                           ; preds = %if.then, %entry
 
 define void @f6(double* nocapture readonly %p, double* nocapture %q) #0 {
 entry:
-  %0 = load double* %p, align 8
-  %arrayidx1 = getelementptr inbounds double* %p, i64 1
-  %1 = load double* %arrayidx1, align 8
-  %arrayidx2 = getelementptr inbounds double* %p, i64 2
-  %2 = load double* %arrayidx2, align 8
-  %arrayidx3 = getelementptr inbounds double* %p, i64 3
-  %3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %p, i64 4
-  %4 = load double* %arrayidx4, align 8
+  %0 = load double, double* %p, align 8
+  %arrayidx1 = getelementptr inbounds double, double* %p, i64 1
+  %1 = load double, double* %arrayidx1, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %p, i64 2
+  %2 = load double, double* %arrayidx2, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %p, i64 3
+  %3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %p, i64 4
+  %4 = load double, double* %arrayidx4, align 8
   %mul = fmul fast double %0, %1
   %add = fadd fast double %mul, %4
   %mul5 = fmul fast double %1, %2
@@ -299,15 +299,15 @@ declare double @hh(double) #1
 
 define void @f7(double* nocapture readonly %p, double* nocapture %q) #0 {
 entry:
-  %0 = load double* %p, align 8
-  %arrayidx1 = getelementptr inbounds double* %p, i64 1
-  %1 = load double* %arrayidx1, align 8
-  %arrayidx2 = getelementptr inbounds double* %p, i64 2
-  %2 = load double* %arrayidx2, align 8
-  %arrayidx3 = getelementptr inbounds double* %p, i64 3
-  %3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %p, i64 4
-  %4 = load double* %arrayidx4, align 8
+  %0 = load double, double* %p, align 8
+  %arrayidx1 = getelementptr inbounds double, double* %p, i64 1
+  %1 = load double, double* %arrayidx1, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %p, i64 2
+  %2 = load double, double* %arrayidx2, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %p, i64 3
+  %3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %p, i64 4
+  %4 = load double, double* %arrayidx4, align 8
   %mul = fmul fast double %0, %1
   %add = fadd fast double %mul, %4
   %mul5 = fmul fast double %1, %2
diff --git a/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll b/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll
index 2df9c375bdce..0c6be21f8907 100644
--- a/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll
+++ b/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll
@@ -11,14 +11,14 @@ invoke.cont145:
   br i1 %or.cond, label %if.then274, label %invoke.cont145
 
 if.then274:
-  %0 = load i32* null, align 4
+  %0 = load i32, i32* null, align 4
   br i1 undef, label %invoke.cont291, label %if.else313
 
 invoke.cont291:
   %idxprom.i.i.i605 = sext i32 %0 to i64
-  %arrayidx.i.i.i607 = getelementptr inbounds double* undef, i64 %idxprom.i.i.i605
+  %arrayidx.i.i.i607 = getelementptr inbounds double, double* undef, i64 %idxprom.i.i.i605
   %idxprom.i.i.i596 = sext i32 %0 to i64
-  %arrayidx.i.i.i598 = getelementptr inbounds double* undef, i64 %idxprom.i.i.i596
+  %arrayidx.i.i.i598 = getelementptr inbounds double, double* undef, i64 %idxprom.i.i.i596
   br label %if.end356
 
 if.else313:
@@ -30,7 +30,7 @@ invoke.cont317:
 
 invoke.cont326:
   %idxprom.i.i.i587 = sext i32 %0 to i64
-  %arrayidx.i.i.i589 = getelementptr inbounds double* undef, i64 %idxprom.i.i.i587
+  %arrayidx.i.i.i589 = getelementptr inbounds double, double* undef, i64 %idxprom.i.i.i587
   %sub329 = fsub fast double undef, undef
   br label %invoke.cont334
 
@@ -40,12 +40,12 @@ invoke.cont334:
 
 invoke.cont342:
   %idxprom.i.i.i578 = sext i32 %0 to i64
-  %arrayidx.i.i.i580 = getelementptr inbounds double* undef, i64 %idxprom.i.i.i578
+  %arrayidx.i.i.i580 = getelementptr inbounds double, double* undef, i64 %idxprom.i.i.i578
   br label %if.end356
 
 invoke.cont353:
   %idxprom.i.i.i572 = sext i32 %0 to i64
-  %arrayidx.i.i.i574 = getelementptr inbounds double* undef, i64 %idxprom.i.i.i572
+  %arrayidx.i.i.i574 = getelementptr inbounds double, double* undef, i64 %idxprom.i.i.i572
   br label %if.end356
 
 if.end356:
diff --git a/test/CodeGen/AArch64/aarch64-address-type-promotion.ll b/test/CodeGen/AArch64/aarch64-address-type-promotion.ll
index ee90d199b458..07e0ba654d21 100644
--- a/test/CodeGen/AArch64/aarch64-address-type-promotion.ll
+++ b/test/CodeGen/AArch64/aarch64-address-type-promotion.ll
@@ -14,15 +14,15 @@ entry:
 ; CHECK-NEXT: ret
   %add = add nsw i32 %i, 1
   %idxprom = sext i32 %add to i64
-  %arrayidx = getelementptr inbounds i32* %a, i64 %idxprom
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %idxprom
+  %0 = load i32, i32* %arrayidx, align 4
   %add1 = add nsw i32 %i, 2
   %idxprom2 = sext i32 %add1 to i64
-  %arrayidx3 = getelementptr inbounds i32* %a, i64 %idxprom2
-  %1 = load i32* %arrayidx3, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %a, i64 %idxprom2
+  %1 = load i32, i32* %arrayidx3, align 4
   %add4 = add nsw i32 %1, %0
   %idxprom5 = sext i32 %i to i64
-  %arrayidx6 = getelementptr inbounds i32* %a, i64 %idxprom5
+  %arrayidx6 = getelementptr inbounds i32, i32* %a, i64 %idxprom5
   store i32 %add4, i32* %arrayidx6, align 4
   ret void
 }
diff --git a/test/CodeGen/AArch64/aarch64-be-bv.ll b/test/CodeGen/AArch64/aarch64-be-bv.ll
index 01642a4f3bf8..fb41156c09df 100644
--- a/test/CodeGen/AArch64/aarch64-be-bv.ll
+++ b/test/CodeGen/AArch64/aarch64-be-bv.ll
@@ -8,7 +8,7 @@ define i16 @movi_modimm_t1() nounwind {
   ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].4s, #0x1
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -20,7 +20,7 @@ define i16 @movi_modimm_t2() nounwind {
   ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].4s, #0x1, lsl #8
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -32,7 +32,7 @@ define i16 @movi_modimm_t3() nounwind {
   ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].4s, #0x1, lsl #16
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -44,7 +44,7 @@ define i16 @movi_modimm_t4() nounwind {
   ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].4s, #0x1, lsl #24
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -56,7 +56,7 @@ define i16 @movi_modimm_t5() nounwind {
   ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].8h, #0x1
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -68,7 +68,7 @@ define i16 @movi_modimm_t6() nounwind {
   ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].8h, #0x1, lsl #8
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -80,7 +80,7 @@ define i16 @movi_modimm_t7() nounwind {
   ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].4s, #0x1, msl #8
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 511, i16 0, i16 511, i16 0, i16 511, i16 0, i16 511, i16 0>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -92,7 +92,7 @@ define i16 @movi_modimm_t8() nounwind {
   ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].4s, #0x1, msl #16
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 1>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -104,7 +104,7 @@ define i16 @movi_modimm_t9() nounwind {
   ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].16b, #0x1
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -116,7 +116,7 @@ define i16 @movi_modimm_t10() nounwind {
   ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].2d, #0x00ffff0000ffff
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -128,7 +128,7 @@ define i16 @fmov_modimm_t11() nounwind {
   ; CHECK-NEXT:    fmov    v[[REG2:[0-9]+]].4s, #3.00000000
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -140,7 +140,7 @@ define i16 @fmov_modimm_t12() nounwind {
   ; CHECK-NEXT:    fmov    v[[REG2:[0-9]+]].2d, #0.17968750
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 0, i16 0, i16 0, i16 16327, i16 0, i16 0, i16 0, i16 16327>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -152,7 +152,7 @@ define i16 @mvni_modimm_t1() nounwind {
   ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].4s, #0x1
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -164,7 +164,7 @@ define i16 @mvni_modimm_t2() nounwind {
   ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].4s, #0x1, lsl #8
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -176,7 +176,7 @@ define i16 @mvni_modimm_t3() nounwind {
   ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].4s, #0x1, lsl #16
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -188,7 +188,7 @@ define i16 @mvni_modimm_t4() nounwind {
   ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].4s, #0x1, lsl #24
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -200,7 +200,7 @@ define i16 @mvni_modimm_t5() nounwind {
   ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].8h, #0x1
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -212,7 +212,7 @@ define i16 @mvni_modimm_t6() nounwind {
   ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].8h, #0x1, lsl #8
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -224,7 +224,7 @@ define i16 @mvni_modimm_t7() nounwind {
   ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].4s, #0x1, msl #8
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65024, i16 65535, i16 65024, i16 65535, i16 65024, i16 65535, i16 65024, i16 65535>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -236,7 +236,7 @@ define i16 @mvni_modimm_t8() nounwind {
   ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].4s, #0x1, msl #16
   ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 0, i16 65534, i16 0, i16 65534, i16 0, i16 65534, i16 0, i16 65534>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -247,7 +247,7 @@ define i16 @bic_modimm_t1() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    bic	   v[[REG2:[0-9]+]].4s, #0x1
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = and <8 x i16> %in, <i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -258,7 +258,7 @@ define i16 @bic_modimm_t2() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    bic	   v[[REG2:[0-9]+]].4s, #0x1, lsl #8
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = and <8 x i16> %in, <i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -269,7 +269,7 @@ define i16 @bic_modimm_t3() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    bic	   v[[REG2:[0-9]+]].4s, #0x1, lsl #16
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = and <8 x i16> %in, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -280,7 +280,7 @@ define i16 @bic_modimm_t4() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    bic	   v[[REG2:[0-9]+]].4s, #0x1, lsl #24
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = and <8 x i16> %in, <i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -291,7 +291,7 @@ define i16 @bic_modimm_t5() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    bic	   v[[REG2:[0-9]+]].8h, #0x1
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = and <8 x i16> %in, <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -302,7 +302,7 @@ define i16 @bic_modimm_t6() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    bic	   v[[REG2:[0-9]+]].8h, #0x1, lsl #8
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = and <8 x i16> %in, <i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -313,7 +313,7 @@ define i16 @orr_modimm_t1() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    orr	   v[[REG2:[0-9]+]].4s, #0x1
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = or <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -324,7 +324,7 @@ define i16 @orr_modimm_t2() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    orr     v[[REG2:[0-9]+]].4s, #0x1, lsl #8
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = or <8 x i16> %in, <i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -335,7 +335,7 @@ define i16 @orr_modimm_t3() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    orr	   v[[REG2:[0-9]+]].4s, #0x1, lsl #16
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = or <8 x i16> %in, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -346,7 +346,7 @@ define i16 @orr_modimm_t4() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    orr	   v[[REG2:[0-9]+]].4s, #0x1, lsl #24
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = or <8 x i16> %in, <i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -357,7 +357,7 @@ define i16 @orr_modimm_t5() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    orr	   v[[REG2:[0-9]+]].8h, #0x1
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = or <8 x i16> %in, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -368,7 +368,7 @@ define i16 @orr_modimm_t6() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    orr	   v[[REG2:[0-9]+]].8h, #0x1, lsl #8
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = or <8 x i16> %in, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
diff --git a/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll b/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
new file mode 100644
index 000000000000..a31c66bad4be
--- /dev/null
+++ b/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
@@ -0,0 +1,491 @@
+; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
+
+; This test aims to check basic correctness of frame layout &
+; frame access code. There are 8 functions in this test file,
+; each function implements one element in the cartesian product
+; of:
+; . a function having a VLA/noVLA
+; . a function with dynamic stack realignment/no dynamic stack realignment.
+; . a function needing a frame pionter/no frame pointer,
+; since the presence/absence of these has influence on the frame
+; layout and which pointer to use to access various part of the
+; frame (bp,sp,fp).
+;
+; Furthermore: in every test function:
+; . there is always one integer and 1 floating point argument to be able
+;   to check those are accessed correctly.
+; . there is always one local variable to check that is accessed
+;   correctly
+;
+; The LLVM-IR below was produced by clang on the following C++ code:
+;extern "C" int g();
+;extern "C" int novla_nodynamicrealign_call(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10,
+;                                             double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10)
+;{
+;  // use an argument passed on the stack.
+;  volatile int l1;
+;  return i10 + (int)d10 + l1 + g();
+;}
+;extern "C" int novla_nodynamicrealign_nocall(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10,
+;                                             double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10)
+;{
+;  // use an argument passed on the stack.
+;  volatile int l1;
+;  return i10 + (int)d10 + l1;
+;}
+;extern "C" int novla_dynamicrealign_call(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10,
+;                                         double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10)
+;{
+;  // use an argument passed on the stack.
+;  alignas(128) volatile int l1;
+;  return i10 + (int)d10 + l1 + g();
+;}
+;extern "C" int novla_dynamicrealign_nocall(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10,
+;                                           double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10)
+;{
+;  // use an argument passed on the stack.
+;  alignas(128) volatile int l1;
+;  return i10 + (int)d10 + l1;
+;}
+;
+;extern "C" int vla_nodynamicrealign_call(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10,
+;                                         double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10)
+;{
+;  // use an argument passed on the stack.
+;  volatile int l1;
+;  volatile int vla[i1];
+;  return i10 + (int)d10 + l1 + g() + vla[0];
+;}
+;extern "C" int vla_nodynamicrealign_nocall(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10,
+;                                           double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10)
+;{
+;  // use an argument passed on the stack.
+;  volatile int l1;
+;  volatile int vla[i1];
+;  return i10 + (int)d10 + l1 + vla[0];
+;}
+;extern "C" int vla_dynamicrealign_call(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10,
+;                                       double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10)
+;{
+;  // use an argument passed on the stack.
+;  alignas(128) volatile int l1;
+;  volatile int vla[i1];
+;  return i10 + (int)d10 + l1 + g() + vla[0];
+;}
+;extern "C" int vla_dynamicrealign_nocall(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10,
+;                                         double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10)
+;{
+;  // use an argument passed on the stack.
+;  alignas(128) volatile int l1;
+;  volatile int vla[i1];
+;  return i10 + (int)d10 + l1 + vla[0];
+;}
+
+
+
+define i32 @novla_nodynamicrealign_call(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 {
+entry:
+  %l1 = alloca i32, align 4
+  %conv = fptosi double %d10 to i32
+  %add = add nsw i32 %conv, %i10
+  %l1.0.l1.0. = load volatile i32, i32* %l1, align 4
+  %add1 = add nsw i32 %add, %l1.0.l1.0.
+  %call = tail call i32 @g()
+  %add2 = add nsw i32 %add1, %call
+  ret i32 %add2
+}
+; CHECK-LABEL: novla_nodynamicrealign_call
+; CHECK: .cfi_startproc
+;   Check that used callee-saved registers are saved
+; CHECK: stp	x20, x19, [sp, #-32]!
+;   Check that the frame pointer is created:
+; CHECK: stp	x29, x30, [sp, #16]
+; CHECK: add	x29, sp, #16
+;   Check correctness of cfi pseudo-instructions
+; CHECK: .cfi_def_cfa w29, 16
+; CHECK: .cfi_offset w30, -8
+; CHECK: .cfi_offset w29, -16
+; CHECK: .cfi_offset w19, -24
+; CHECK: .cfi_offset w20, -32
+;   Check correct access to arguments passed on the stack, through frame pointer
+; CHECK: ldr	d[[DARG:[0-9]+]], [x29, #40]
+; CHECK: ldr	w[[IARG:[0-9]+]], [x29, #24]
+;   Check correct access to local variable on the stack, through stack pointer
+; CHECK: ldr	w[[ILOC:[0-9]+]], [sp, #12]
+;   Check epilogue:
+; CHECK: ldp	x29, x30, [sp, #16]
+; CHECK: ldp	x20, x19, [sp], #32
+; CHECK: ret
+; CHECK: .cfi_endproc
+
+
+declare i32 @g() #0
+
+; Function Attrs: nounwind
+define i32 @novla_nodynamicrealign_nocall(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #1 {
+entry:
+  %l1 = alloca i32, align 4
+  %conv = fptosi double %d10 to i32
+  %add = add nsw i32 %conv, %i10
+  %l1.0.l1.0. = load volatile i32, i32* %l1, align 4
+  %add1 = add nsw i32 %add, %l1.0.l1.0.
+  ret i32 %add1
+}
+; CHECK-LABEL: novla_nodynamicrealign_nocall
+;   Check that space is reserved for one local variable on the stack.
+; CHECK:	sub	sp, sp, #16             // =16
+;   Check correct access to arguments passed on the stack, through stack pointer
+; CHECK: ldr	d[[DARG:[0-9]+]], [sp, #40]
+; CHECK: ldr	w[[IARG:[0-9]+]], [sp, #24]
+;   Check correct access to local variable on the stack, through stack pointer
+; CHECK: ldr	w[[ILOC:[0-9]+]], [sp, #12]
+;   Check epilogue:
+; CHECK: add	sp, sp, #16             // =16
+; CHECK: ret
+
+
+define i32 @novla_dynamicrealign_call(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 {
+entry:
+  %l1 = alloca i32, align 128
+  %conv = fptosi double %d10 to i32
+  %add = add nsw i32 %conv, %i10
+  %l1.0.l1.0. = load volatile i32, i32* %l1, align 128
+  %add1 = add nsw i32 %add, %l1.0.l1.0.
+  %call = tail call i32 @g()
+  %add2 = add nsw i32 %add1, %call
+  ret i32 %add2
+}
+
+; CHECK-LABEL: novla_dynamicrealign_call
+; CHECK: .cfi_startproc
+;   Check that used callee-saved registers are saved
+; CHECK: stp	x20, x19, [sp, #-32]!
+;   Check that the frame pointer is created:
+; CHECK: stp	x29, x30, [sp, #16]
+; CHECK: add	x29, sp, #16
+;   Check the dynamic realignment of the stack pointer to a 128-byte boundary
+; CHECK: sub	x9, sp, #96
+; CHECK: and	sp, x9, #0xffffffffffffff80
+;   Check correctness of cfi pseudo-instructions
+; CHECK: .cfi_def_cfa w29, 16
+; CHECK: .cfi_offset w30, -8
+; CHECK: .cfi_offset w29, -16
+; CHECK: .cfi_offset w19, -24
+; CHECK: .cfi_offset w20, -32
+;   Check correct access to arguments passed on the stack, through frame pointer
+; CHECK: ldr	d[[DARG:[0-9]+]], [x29, #40]
+; CHECK: ldr	w[[IARG:[0-9]+]], [x29, #24]
+;   Check correct access to local variable on the stack, through re-aligned stack pointer
+; CHECK: ldr	w[[ILOC:[0-9]+]], [sp]
+;   Check epilogue:
+;     Check that stack pointer get restored from frame pointer.
+; CHECK: sub	sp, x29, #16            // =16
+; CHECK: ldp	x29, x30, [sp, #16]
+; CHECK: ldp	x20, x19, [sp], #32
+; CHECK: ret
+; CHECK: .cfi_endproc
+
+
+; Function Attrs: nounwind
+define i32 @novla_dynamicrealign_nocall(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #1 {
+entry:
+  %l1 = alloca i32, align 128
+  %conv = fptosi double %d10 to i32
+  %add = add nsw i32 %conv, %i10
+  %l1.0.l1.0. = load volatile i32, i32* %l1, align 128
+  %add1 = add nsw i32 %add, %l1.0.l1.0.
+  ret i32 %add1
+}
+
+; CHECK-LABEL: novla_dynamicrealign_nocall
+;   Check that the frame pointer is created:
+; CHECK: stp	x29, x30, [sp, #-16]!
+; CHECK: mov	x29, sp
+;   Check the dynamic realignment of the stack pointer to a 128-byte boundary
+; CHECK: sub	x9, sp, #112
+; CHECK: and	sp, x9, #0xffffffffffffff80
+;   Check correct access to arguments passed on the stack, through frame pointer
+; CHECK: ldr	d[[DARG:[0-9]+]], [x29, #40]
+; CHECK: ldr	w[[IARG:[0-9]+]], [x29, #24]
+;   Check correct access to local variable on the stack, through re-aligned stack pointer
+; CHECK: ldr	w[[ILOC:[0-9]+]], [sp]
+;   Check epilogue:
+;     Check that stack pointer get restored from frame pointer.
+; CHECK: mov	sp, x29
+; CHECK: ldp	x29, x30, [sp], #16
+; CHECK: ret
+
+
+define i32 @vla_nodynamicrealign_call(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 {
+entry:
+  %l1 = alloca i32, align 4
+  %0 = zext i32 %i1 to i64
+  %vla = alloca i32, i64 %0, align 4
+  %conv = fptosi double %d10 to i32
+  %add = add nsw i32 %conv, %i10
+  %l1.0.l1.0. = load volatile i32, i32* %l1, align 4
+  %add1 = add nsw i32 %add, %l1.0.l1.0.
+  %call = tail call i32 @g()
+  %add2 = add nsw i32 %add1, %call
+  %1 = load volatile i32, i32* %vla, align 4, !tbaa !1
+  %add3 = add nsw i32 %add2, %1
+  ret i32 %add3
+}
+
+; CHECK-LABEL: vla_nodynamicrealign_call
+; CHECK: .cfi_startproc
+;   Check that used callee-saved registers are saved
+; CHECK: stp	x20, x19, [sp, #-32]!
+;   Check that the frame pointer is created:
+; CHECK: stp	x29, x30, [sp, #16]
+; CHECK: add	x29, sp, #16
+;   Check that space is reserved on the stack for the local variable,
+;   rounded up to a multiple of 16 to keep the stack pointer 16-byte aligned.
+; CHECK: sub	sp, sp, #16
+;   Check correctness of cfi pseudo-instructions
+; CHECK: .cfi_def_cfa w29, 16
+; CHECK: .cfi_offset w30, -8
+; CHECK: .cfi_offset w29, -16
+; CHECK: .cfi_offset w19, -24
+; CHECK: .cfi_offset w20, -32
+;   Check correct access to arguments passed on the stack, through frame pointer
+; CHECK: ldr	w[[IARG:[0-9]+]], [x29, #24]
+; CHECK: ldr	d[[DARG:[0-9]+]], [x29, #40]
+;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
+; CHECK: ubfx	x9, x0, #0, #32
+; CHECK: lsl	x9, x9, #2
+; CHECK: add	x9, x9, #15
+; CHECK: and	x9, x9, #0xfffffffffffffff0
+; CHECK: mov	 x10, sp
+; CHECK: sub	 x[[VLASPTMP:[0-9]+]], x10, x9
+; CHECK: mov	 sp, x[[VLASPTMP]]
+;   Check correct access to local variable, through frame pointer
+; CHECK: ldur	w[[ILOC:[0-9]+]], [x29, #-20]
+;   Check correct accessing of the VLA variable through the base pointer
+; CHECK: ldr	w[[VLA:[0-9]+]], [x[[VLASPTMP]]]
+;   Check epilogue:
+;     Check that stack pointer get restored from frame pointer.
+; CHECK: sub	sp, x29, #16            // =16
+; CHECK: ldp	x29, x30, [sp, #16]
+; CHECK: ldp	x20, x19, [sp], #32
+; CHECK: ret
+; CHECK: .cfi_endproc
+
+
+; Function Attrs: nounwind
+define i32 @vla_nodynamicrealign_nocall(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #1 {
+entry:
+  %l1 = alloca i32, align 4
+  %0 = zext i32 %i1 to i64
+  %vla = alloca i32, i64 %0, align 4
+  %conv = fptosi double %d10 to i32
+  %add = add nsw i32 %conv, %i10
+  %l1.0.l1.0. = load volatile i32, i32* %l1, align 4
+  %add1 = add nsw i32 %add, %l1.0.l1.0.
+  %1 = load volatile i32, i32* %vla, align 4, !tbaa !1
+  %add2 = add nsw i32 %add1, %1
+  ret i32 %add2
+}
+
+; CHECK-LABEL: vla_nodynamicrealign_nocall
+;   Check that the frame pointer is created:
+; CHECK: stp	x29, x30, [sp, #-16]!
+; CHECK: mov	x29, sp
+;   Check that space is reserved on the stack for the local variable,
+;   rounded up to a multiple of 16 to keep the stack pointer 16-byte aligned.
+; CHECK: sub	sp, sp, #16
+;   Check correctness of cfi pseudo-instructions
+;   Check correct access to arguments passed on the stack, through frame pointer
+; CHECK: ldr	w[[IARG:[0-9]+]], [x29, #24]
+; CHECK: ldr	d[[DARG:[0-9]+]], [x29, #40]
+;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
+; CHECK: ubfx	x9, x0, #0, #32
+; CHECK: lsl	x9, x9, #2
+; CHECK: add	x9, x9, #15
+; CHECK: and	x9, x9, #0xfffffffffffffff0
+; CHECK: mov	 x10, sp
+; CHECK: sub	 x[[VLASPTMP:[0-9]+]], x10, x9
+; CHECK: mov	 sp, x[[VLASPTMP]]
+;   Check correct access to local variable, through frame pointer
+; CHECK: ldur	w[[ILOC:[0-9]+]], [x29, #-4]
+;   Check correct accessing of the VLA variable through the base pointer
+; CHECK: ldr	w[[VLA:[0-9]+]], [x[[VLASPTMP]]]
+;   Check epilogue:
+;     Check that stack pointer get restored from frame pointer.
+; CHECK: mov    sp, x29
+; CHECK: ldp	x29, x30, [sp], #16
+; CHECK: ret
+
+
+define i32 @vla_dynamicrealign_call(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 {
+entry:
+  %l1 = alloca i32, align 128
+  %0 = zext i32 %i1 to i64
+  %vla = alloca i32, i64 %0, align 4
+  %conv = fptosi double %d10 to i32
+  %add = add nsw i32 %conv, %i10
+  %l1.0.l1.0. = load volatile i32, i32* %l1, align 128
+  %add1 = add nsw i32 %add, %l1.0.l1.0.
+  %call = tail call i32 @g()
+  %add2 = add nsw i32 %add1, %call
+  %1 = load volatile i32, i32* %vla, align 4, !tbaa !1
+  %add3 = add nsw i32 %add2, %1
+  ret i32 %add3
+}
+
+; CHECK-LABEL: vla_dynamicrealign_call
+; CHECK: .cfi_startproc
+;   Check that used callee-saved registers are saved
+; CHECK: stp	x22, x21, [sp, #-48]!
+; CHECK: stp	x20, x19, [sp, #16]
+;   Check that the frame pointer is created:
+; CHECK: stp	x29, x30, [sp, #32]
+; CHECK: add	x29, sp, #32
+;   Check that the stack pointer gets re-aligned to 128
+;   bytes & the base pointer (x19) gets initialized to
+;   this 128-byte aligned area for local variables &
+;   spill slots
+; CHECK: sub	x9, sp, #80            // =80
+; CHECK: and	sp, x9, #0xffffffffffffff80
+; CHECK: mov    x19, sp
+;   Check correctness of cfi pseudo-instructions
+; CHECK: .cfi_def_cfa w29, 16
+; CHECK: .cfi_offset w30, -8
+; CHECK: .cfi_offset w29, -16
+; CHECK: .cfi_offset w19, -24
+; CHECK: .cfi_offset w20, -32
+; CHECK: .cfi_offset w21, -40
+; CHECK: .cfi_offset w22, -48
+;   Check correct access to arguments passed on the stack, through frame pointer
+; CHECK: ldr	w[[IARG:[0-9]+]], [x29, #24]
+; CHECK: ldr	d[[DARG:[0-9]+]], [x29, #40]
+;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
+;   and set-up of base pointer (x19).
+; CHECK: ubfx	x9, x0, #0, #32
+; CHECK: lsl	x9, x9, #2
+; CHECK: add	x9, x9, #15
+; CHECK: and	x9, x9, #0xfffffffffffffff0
+; CHECK: mov	 x10, sp
+; CHECK: sub	 x[[VLASPTMP:[0-9]+]], x10, x9
+; CHECK: mov	 sp, x[[VLASPTMP]]
+;   Check correct access to local variable, through base pointer
+; CHECK: ldr	w[[ILOC:[0-9]+]], [x19]
+; CHECK: ldr	 w[[VLA:[0-9]+]], [x[[VLASPTMP]]]
+;   Check epilogue:
+;     Check that stack pointer get restored from frame pointer.
+; CHECK: sub	sp, x29, #32
+; CHECK: ldp	x29, x30, [sp, #32]
+; CHECK: ldp	x20, x19, [sp, #16]
+; CHECK: ldp	x22, x21, [sp], #48
+; CHECK: ret
+; CHECK: .cfi_endproc
+
+
+; Function Attrs: nounwind
+define i32 @vla_dynamicrealign_nocall(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #1 {
+entry:
+  %l1 = alloca i32, align 128
+  %0 = zext i32 %i1 to i64
+  %vla = alloca i32, i64 %0, align 4
+  %conv = fptosi double %d10 to i32
+  %add = add nsw i32 %conv, %i10
+  %l1.0.l1.0. = load volatile i32, i32* %l1, align 128
+  %add1 = add nsw i32 %add, %l1.0.l1.0.
+  %1 = load volatile i32, i32* %vla, align 4, !tbaa !1
+  %add2 = add nsw i32 %add1, %1
+  ret i32 %add2
+}
+
+; CHECK-LABEL: vla_dynamicrealign_nocall
+;   Check that used callee-saved registers are saved
+; CHECK: stp	x20, x19, [sp, #-32]!
+;   Check that the frame pointer is created:
+; CHECK: stp	x29, x30, [sp, #16]
+; CHECK: add	x29, sp, #16
+;   Check that the stack pointer gets re-aligned to 128
+;   bytes & the base pointer (x19) gets initialized to
+;   this 128-byte aligned area for local variables &
+;   spill slots
+; CHECK: sub	x9, sp, #96
+; CHECK: and	sp, x9, #0xffffffffffffff80
+; CHECK: mov    x19, sp
+;   Check correct access to arguments passed on the stack, through frame pointer
+; CHECK: ldr	w[[IARG:[0-9]+]], [x29, #24]
+; CHECK: ldr	d[[DARG:[0-9]+]], [x29, #40]
+;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
+;   and set-up of base pointer (x19).
+; CHECK: ubfx	x9, x0, #0, #32
+; CHECK: lsl	x9, x9, #2
+; CHECK: add	x9, x9, #15
+; CHECK: and	x9, x9, #0xfffffffffffffff0
+; CHECK: mov	 x10, sp
+; CHECK: sub	 x[[VLASPTMP:[0-9]+]], x10, x9
+; CHECK: mov	 sp, x[[VLASPTMP]]
+;   Check correct access to local variable, through base pointer
+; CHECK: ldr	w[[ILOC:[0-9]+]], [x19]
+; CHECK: ldr	 w[[VLA:[0-9]+]], [x[[VLASPTMP]]]
+;   Check epilogue:
+;     Check that stack pointer get restored from frame pointer.
+; CHECK: sub	sp, x29, #16
+; CHECK: ldp	x29, x30, [sp, #16]
+; CHECK: ldp	x20, x19, [sp], #32
+; CHECK: ret
+
+
+; Function Attrs: nounwind
+define i32 @vla_dynamicrealign_nocall_large_align(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #1 {
+entry:
+  %l1 = alloca i32, align 32768
+  %0 = zext i32 %i1 to i64
+  %vla = alloca i32, i64 %0, align 4
+  %conv = fptosi double %d10 to i32
+  %add = add nsw i32 %conv, %i10
+  %l1.0.l1.0. = load volatile i32, i32* %l1, align 32768
+  %add1 = add nsw i32 %add, %l1.0.l1.0.
+  %1 = load volatile i32, i32* %vla, align 4, !tbaa !1
+  %add2 = add nsw i32 %add1, %1
+  ret i32 %add2
+}
+
+; CHECK-LABEL: vla_dynamicrealign_nocall_large_align
+;   Check that used callee-saved registers are saved
+; CHECK: stp	x20, x19, [sp, #-32]!
+;   Check that the frame pointer is created:
+; CHECK: stp	x29, x30, [sp, #16]
+; CHECK: add	x29, sp, #16
+;   Check that the stack pointer gets re-aligned to 128
+;   bytes & the base pointer (x19) gets initialized to
+;   this 128-byte aligned area for local variables &
+;   spill slots
+; CHECK: sub	x9, sp, #7, lsl #12
+; CHECK: and	sp, x9, #0xffffffffffff8000
+; CHECK: mov    x19, sp
+;   Check correct access to arguments passed on the stack, through frame pointer
+; CHECK: ldr	w[[IARG:[0-9]+]], [x29, #24]
+; CHECK: ldr	d[[DARG:[0-9]+]], [x29, #40]
+;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
+;   and set-up of base pointer (x19).
+; CHECK: ubfx	x9, x0, #0, #32
+; CHECK: lsl	x9, x9, #2
+; CHECK: add	x9, x9, #15
+; CHECK: and	x9, x9, #0xfffffffffffffff0
+; CHECK: mov	 x10, sp
+; CHECK: sub	 x[[VLASPTMP:[0-9]+]], x10, x9
+; CHECK: mov	 sp, x[[VLASPTMP]]
+;   Check correct access to local variable, through base pointer
+; CHECK: ldr	w[[ILOC:[0-9]+]], [x19]
+; CHECK: ldr	 w[[VLA:[0-9]+]], [x[[VLASPTMP]]]
+;   Check epilogue:
+;     Check that stack pointer get restored from frame pointer.
+; CHECK: sub	sp, x29, #16
+; CHECK: ldp	x29, x30, [sp, #16]
+; CHECK: ldp	x20, x19, [sp], #32
+; CHECK: ret
+
+attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!1 = !{!2, !2, i64 0}
+!2 = !{!"int", !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C/C++ TBAA"}
diff --git a/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll b/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll
index 64d91eea9739..2170e4b902d4 100644
--- a/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll
+++ b/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll
@@ -22,7 +22,7 @@ target triple = "aarch64--linux-gnu"
 
 define i64 @f_load_madd_64(i64 %a, i64 %b, i64* nocapture readonly %c) #0 {
 entry:
-  %0 = load i64* %c, align 8
+  %0 = load i64, i64* %c, align 8
   %mul = mul nsw i64 %0, %b
   %add = add nsw i64 %mul, %a
   ret i64 %add
@@ -41,7 +41,7 @@ entry:
 
 define i32 @f_load_madd_32(i32 %a, i32 %b, i32* nocapture readonly %c) #0 {
 entry:
-  %0 = load i32* %c, align 4
+  %0 = load i32, i32* %c, align 4
   %mul = mul nsw i32 %0, %b
   %add = add nsw i32 %mul, %a
   ret i32 %add
@@ -56,7 +56,7 @@ entry:
 
 define i64 @f_load_msub_64(i64 %a, i64 %b, i64* nocapture readonly %c) #0 {
 entry:
-  %0 = load i64* %c, align 8
+  %0 = load i64, i64* %c, align 8
   %mul = mul nsw i64 %0, %b
   %sub = sub nsw i64 %a, %mul
   ret i64 %sub
@@ -72,7 +72,7 @@ entry:
 
 define i32 @f_load_msub_32(i32 %a, i32 %b, i32* nocapture readonly %c) #0 {
 entry:
-  %0 = load i32* %c, align 4
+  %0 = load i32, i32* %c, align 4
   %mul = mul nsw i32 %0, %b
   %sub = sub nsw i32 %a, %mul
   ret i32 %sub
@@ -87,7 +87,7 @@ entry:
 
 define i64 @f_load_mul_64(i64 %a, i64 %b, i64* nocapture readonly %c) #0 {
 entry:
-  %0 = load i64* %c, align 8
+  %0 = load i64, i64* %c, align 8
   %mul = mul nsw i64 %0, %b
   ret i64 %mul
 }
@@ -101,7 +101,7 @@ entry:
 
 define i32 @f_load_mul_32(i32 %a, i32 %b, i32* nocapture readonly %c) #0 {
 entry:
-  %0 = load i32* %c, align 4
+  %0 = load i32, i32* %c, align 4
   %mul = mul nsw i32 %0, %b
   ret i32 %mul
 }
@@ -115,7 +115,7 @@ entry:
 
 define i64 @f_load_mneg_64(i64 %a, i64 %b, i64* nocapture readonly %c) #0 {
 entry:
-  %0 = load i64* %c, align 8
+  %0 = load i64, i64* %c, align 8
   %mul = sub i64 0, %b
   %sub = mul i64 %0, %mul
   ret i64 %sub
@@ -133,7 +133,7 @@ entry:
 
 define i32 @f_load_mneg_32(i32 %a, i32 %b, i32* nocapture readonly %c) #0 {
 entry:
-  %0 = load i32* %c, align 4
+  %0 = load i32, i32* %c, align 4
   %mul = sub i32 0, %b
   %sub = mul i32 %0, %mul
   ret i32 %sub
@@ -154,7 +154,7 @@ entry:
   %conv1 = sext i32 %c to i64
   %mul = mul nsw i64 %conv1, %conv
   %add = add nsw i64 %mul, %a
-  %0 = load i32* %d, align 4
+  %0 = load i32, i32* %d, align 4
   %conv2 = sext i32 %0 to i64
   %add3 = add nsw i64 %add, %conv2
   ret i64 %add3
@@ -174,7 +174,7 @@ entry:
   %conv1 = sext i32 %c to i64
   %mul = mul nsw i64 %conv1, %conv
   %sub = sub i64 %a, %mul
-  %0 = load i32* %d, align 4
+  %0 = load i32, i32* %d, align 4
   %conv2 = sext i32 %0 to i64
   %add = add nsw i64 %sub, %conv2
   ret i64 %add
@@ -193,7 +193,7 @@ entry:
   %conv = sext i32 %b to i64
   %conv1 = sext i32 %c to i64
   %mul = mul nsw i64 %conv1, %conv
-  %0 = load i32* %d, align 4
+  %0 = load i32, i32* %d, align 4
   %conv2 = sext i32 %0 to i64
   %div = sdiv i64 %mul, %conv2
   ret i64 %div
@@ -212,7 +212,7 @@ entry:
   %conv1 = sext i32 %c to i64
   %mul = sub nsw i64 0, %conv
   %sub = mul i64 %conv1, %mul
-  %0 = load i32* %d, align 4
+  %0 = load i32, i32* %d, align 4
   %conv2 = sext i32 %0 to i64
   %div = sdiv i64 %sub, %conv2
   ret i64 %div
@@ -229,7 +229,7 @@ entry:
   %conv1 = zext i32 %c to i64
   %mul = mul i64 %conv1, %conv
   %add = add i64 %mul, %a
-  %0 = load i32* %d, align 4
+  %0 = load i32, i32* %d, align 4
   %conv2 = zext i32 %0 to i64
   %add3 = add i64 %add, %conv2
   ret i64 %add3
@@ -249,7 +249,7 @@ entry:
   %conv1 = zext i32 %c to i64
   %mul = mul i64 %conv1, %conv
   %sub = sub i64 %a, %mul
-  %0 = load i32* %d, align 4
+  %0 = load i32, i32* %d, align 4
   %conv2 = zext i32 %0 to i64
   %add = add i64 %sub, %conv2
   ret i64 %add
@@ -268,7 +268,7 @@ entry:
   %conv = zext i32 %b to i64
   %conv1 = zext i32 %c to i64
   %mul = mul i64 %conv1, %conv
-  %0 = load i32* %d, align 4
+  %0 = load i32, i32* %d, align 4
   %conv2 = zext i32 %0 to i64
   %div = udiv i64 %mul, %conv2
   ret i64 %div
@@ -287,7 +287,7 @@ entry:
   %conv1 = zext i32 %c to i64
   %mul = sub nsw i64 0, %conv
   %sub = mul i64 %conv1, %mul
-  %0 = load i32* %d, align 4
+  %0 = load i32, i32* %d, align 4
   %conv2 = zext i32 %0 to i64
   %div = udiv i64 %sub, %conv2
   ret i64 %div
@@ -300,7 +300,7 @@ entry:
 
 define i64 @f_store_madd_64(i64 %a, i64 %b, i64* nocapture readonly %cp, i64* nocapture %e) #1 {
 entry:
-  %0 = load i64* %cp, align 8
+  %0 = load i64, i64* %cp, align 8
   store i64 %a, i64* %e, align 8
   %mul = mul nsw i64 %0, %b
   %add = add nsw i64 %mul, %a
@@ -317,7 +317,7 @@ entry:
 
 define i32 @f_store_madd_32(i32 %a, i32 %b, i32* nocapture readonly %cp, i32* nocapture %e) #1 {
 entry:
-  %0 = load i32* %cp, align 4
+  %0 = load i32, i32* %cp, align 4
   store i32 %a, i32* %e, align 4
   %mul = mul nsw i32 %0, %b
   %add = add nsw i32 %mul, %a
@@ -333,7 +333,7 @@ entry:
 
 define i64 @f_store_msub_64(i64 %a, i64 %b, i64* nocapture readonly %cp, i64* nocapture %e) #1 {
 entry:
-  %0 = load i64* %cp, align 8
+  %0 = load i64, i64* %cp, align 8
   store i64 %a, i64* %e, align 8
   %mul = mul nsw i64 %0, %b
   %sub = sub nsw i64 %a, %mul
@@ -350,7 +350,7 @@ entry:
 
 define i32 @f_store_msub_32(i32 %a, i32 %b, i32* nocapture readonly %cp, i32* nocapture %e) #1 {
 entry:
-  %0 = load i32* %cp, align 4
+  %0 = load i32, i32* %cp, align 4
   store i32 %a, i32* %e, align 4
   %mul = mul nsw i32 %0, %b
   %sub = sub nsw i32 %a, %mul
@@ -366,7 +366,7 @@ entry:
 
 define i64 @f_store_mul_64(i64 %a, i64 %b, i64* nocapture readonly %cp, i64* nocapture %e) #1 {
 entry:
-  %0 = load i64* %cp, align 8
+  %0 = load i64, i64* %cp, align 8
   store i64 %a, i64* %e, align 8
   %mul = mul nsw i64 %0, %b
   ret i64 %mul
@@ -381,7 +381,7 @@ entry:
 
 define i32 @f_store_mul_32(i32 %a, i32 %b, i32* nocapture readonly %cp, i32* nocapture %e) #1 {
 entry:
-  %0 = load i32* %cp, align 4
+  %0 = load i32, i32* %cp, align 4
   store i32 %a, i32* %e, align 4
   %mul = mul nsw i32 %0, %b
   ret i32 %mul
@@ -396,7 +396,7 @@ entry:
 
 define i64 @f_prefetch_madd_64(i64 %a, i64 %b, i64* nocapture readonly %cp, i64* nocapture %e) #1 {
 entry:
-  %0 = load i64* %cp, align 8
+  %0 = load i64, i64* %cp, align 8
   %1 = bitcast i64* %e to i8*
   tail call void @llvm.prefetch(i8* %1, i32 0, i32 0, i32 1)
   %mul = mul nsw i64 %0, %b
@@ -415,7 +415,7 @@ declare void @llvm.prefetch(i8* nocapture, i32, i32, i32) #2
 
 define i32 @f_prefetch_madd_32(i32 %a, i32 %b, i32* nocapture readonly %cp, i32* nocapture %e) #1 {
 entry:
-  %0 = load i32* %cp, align 4
+  %0 = load i32, i32* %cp, align 4
   %1 = bitcast i32* %e to i8*
   tail call void @llvm.prefetch(i8* %1, i32 1, i32 0, i32 1)
   %mul = mul nsw i32 %0, %b
@@ -431,7 +431,7 @@ entry:
 
 define i64 @f_prefetch_msub_64(i64 %a, i64 %b, i64* nocapture readonly %cp, i64* nocapture %e) #1 {
 entry:
-  %0 = load i64* %cp, align 8
+  %0 = load i64, i64* %cp, align 8
   %1 = bitcast i64* %e to i8*
   tail call void @llvm.prefetch(i8* %1, i32 0, i32 1, i32 1)
   %mul = mul nsw i64 %0, %b
@@ -448,7 +448,7 @@ entry:
 
 define i32 @f_prefetch_msub_32(i32 %a, i32 %b, i32* nocapture readonly %cp, i32* nocapture %e) #1 {
 entry:
-  %0 = load i32* %cp, align 4
+  %0 = load i32, i32* %cp, align 4
   %1 = bitcast i32* %e to i8*
   tail call void @llvm.prefetch(i8* %1, i32 1, i32 1, i32 1)
   %mul = mul nsw i32 %0, %b
@@ -464,7 +464,7 @@ entry:
 
 define i64 @f_prefetch_mul_64(i64 %a, i64 %b, i64* nocapture readonly %cp, i64* nocapture %e) #1 {
 entry:
-  %0 = load i64* %cp, align 8
+  %0 = load i64, i64* %cp, align 8
   %1 = bitcast i64* %e to i8*
   tail call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1)
   %mul = mul nsw i64 %0, %b
@@ -479,7 +479,7 @@ entry:
 
 define i32 @f_prefetch_mul_32(i32 %a, i32 %b, i32* nocapture readonly %cp, i32* nocapture %e) #1 {
 entry:
-  %0 = load i32* %cp, align 4
+  %0 = load i32, i32* %cp, align 4
   %1 = bitcast i32* %e to i8*
   tail call void @llvm.prefetch(i8* %1, i32 1, i32 3, i32 1)
   %mul = mul nsw i32 %0, %b
@@ -494,7 +494,7 @@ entry:
 
 define i64 @fall_through(i64 %a, i64 %b, i64* nocapture readonly %c) #0 {
 entry:
-  %0 = load i64* %c, align 8
+  %0 = load i64, i64* %c, align 8
   br label %block1
 
 block1:
diff --git a/test/CodeGen/AArch64/aarch64-gep-opt.ll b/test/CodeGen/AArch64/aarch64-gep-opt.ll
index 811eed9d1fbe..93e2ff14ac71 100644
--- a/test/CodeGen/AArch64/aarch64-gep-opt.ll
+++ b/test/CodeGen/AArch64/aarch64-gep-opt.ll
@@ -1,6 +1,6 @@
-; RUN: llc -O3 -verify-machineinstrs %s -o - | FileCheck %s
-; RUN: llc -O3 -print-after=codegenprepare -mcpu=cyclone < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-NoAA <%t %s
-; RUN: llc -O3 -print-after=codegenprepare -mcpu=cortex-a53 < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA <%t %s
+; RUN: llc -O3 -aarch64-gep-opt=true -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -O3 -aarch64-gep-opt=true -print-after=codegenprepare -mcpu=cyclone < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-NoAA <%t %s
+; RUN: llc -O3 -aarch64-gep-opt=true -print-after=codegenprepare -mcpu=cortex-a53 < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA <%t %s
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-linux-gnueabi"
 
@@ -14,14 +14,14 @@ target triple = "aarch64-linux-gnueabi"
 ; Check that when two complex GEPs are used in two basic blocks, LLVM can
 ; elimilate the common subexpression for the second use.
 define void @test_GEP_CSE([240 x %struct]* %string, i32* %adj, i32 %lib, i64 %idxprom) {
-  %liberties = getelementptr [240 x %struct]* %string, i64 1, i64 %idxprom, i32 3
-  %1 = load i32* %liberties, align 4
+  %liberties = getelementptr [240 x %struct], [240 x %struct]* %string, i64 1, i64 %idxprom, i32 3
+  %1 = load i32, i32* %liberties, align 4
   %cmp = icmp eq i32 %1, %lib
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %origin = getelementptr [240 x %struct]* %string, i64 1, i64 %idxprom, i32 2
-  %2 = load i32* %origin, align 4
+  %origin = getelementptr [240 x %struct], [240 x %struct]* %string, i64 1, i64 %idxprom, i32 2
+  %2 = load i32, i32* %origin, align 4
   store i32 %2, i32* %adj, align 4
   br label %if.end
 
@@ -50,11 +50,11 @@ if.end:                                           ; preds = %if.then, %entry
 ; CHECK-UseAA-LABEL: @test_GEP_CSE(
 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = bitcast [240 x %struct]* %string to i8*
 ; CHECK-UseAA: [[IDX:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96
-; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8* [[PTR0]], i64 [[IDX]]
-; CHECK-UseAA: getelementptr i8* [[PTR1]], i64 23052
+; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8, i8* [[PTR0]], i64 [[IDX]]
+; CHECK-UseAA: getelementptr i8, i8* [[PTR1]], i64 23052
 ; CHECK-UseAA: bitcast
 ; CHECK-UseAA: if.then:
-; CHECK-UseAA: getelementptr i8* [[PTR1]], i64 23048
+; CHECK-UseAA: getelementptr i8, i8* [[PTR1]], i64 23048
 ; CHECK-UseAA: bitcast
 
 %class.my = type { i32, [128 x i32], i32, [256 x %struct.pt]}
@@ -65,10 +65,10 @@ if.end:                                           ; preds = %if.then, %entry
 ; calculation and code gen can generate a better addressing mode for the second
 ; use.
 define void @test_GEP_across_BB(%class.my* %this, i64 %idx) {
-  %1 = getelementptr %class.my* %this, i64 0, i32 3, i64 %idx, i32 1
-  %2 = load i32* %1, align 4
-  %3 = getelementptr %class.my* %this, i64 0, i32 3, i64 %idx, i32 2
-  %4 = load i32* %3, align 4
+  %1 = getelementptr %class.my, %class.my* %this, i64 0, i32 3, i64 %idx, i32 1
+  %2 = load i32, i32* %1, align 4
+  %3 = getelementptr %class.my, %class.my* %this, i64 0, i32 3, i64 %idx, i32 2
+  %4 = load i32, i32* %3, align 4
   %5 = icmp eq i32 %2, %4
   br i1 %5, label %if.true, label %exit
 
@@ -99,12 +99,12 @@ exit:
 
 ; CHECK-UseAA-LABEL: test_GEP_across_BB(
 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = getelementptr
-; CHECK-UseAA: getelementptr i8* [[PTR0]], i64 528
-; CHECK-UseAA: getelementptr i8* [[PTR0]], i64 532
+; CHECK-UseAA: getelementptr i8, i8* [[PTR0]], i64 528
+; CHECK-UseAA: getelementptr i8, i8* [[PTR0]], i64 532
 ; CHECK-UseAA: if.true:
-; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8* [[PTR0]], i64 532
+; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, i8* [[PTR0]], i64 532
 ; CHECK-UseAA: exit:
-; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8* [[PTR0]], i64 528
+; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, i8* [[PTR0]], i64 528
 
 %struct.S = type { float, double }
 @struct_array = global [1024 x %struct.S] zeroinitializer, align 16
@@ -118,7 +118,7 @@ define double* @test-struct_1(i32 %i) {
 entry:
   %add = add nsw i32 %i, 5
   %idxprom = sext i32 %add to i64
-  %p = getelementptr [1024 x %struct.S]* @struct_array, i64 0, i64 %idxprom, i32 1
+  %p = getelementptr [1024 x %struct.S], [1024 x %struct.S]* @struct_array, i64 0, i64 %idxprom, i32 1
   ret double* %p
 }
 ; CHECK-NoAA-LABEL: @test-struct_1(
@@ -126,7 +126,7 @@ entry:
 ; CHECK-NoAA: add i64 %{{[a-zA-Z0-9]+}}, 88
 
 ; CHECK-UseAA-LABEL: @test-struct_1(
-; CHECK-UseAA: getelementptr i8* %{{[a-zA-Z0-9]+}}, i64 88
+; CHECK-UseAA: getelementptr i8, i8* %{{[a-zA-Z0-9]+}}, i64 88
 
 %struct3 = type { i64, i32 }
 %struct2 = type { %struct3, i32 }
@@ -140,7 +140,7 @@ entry:
 define %struct2* @test-struct_2(%struct0* %ptr, i64 %idx) {
 entry:
   %arrayidx = add nsw i64 %idx, -2
-  %ptr2 = getelementptr %struct0* %ptr, i64 0, i32 3, i64 %arrayidx, i32 1
+  %ptr2 = getelementptr %struct0, %struct0* %ptr, i64 0, i32 3, i64 %arrayidx, i32 1
   ret %struct2* %ptr2
 }
 ; CHECK-NoAA-LABEL: @test-struct_2(
@@ -148,14 +148,14 @@ entry:
 ; CHECK-NoAA: add i64 %{{[a-zA-Z0-9]+}}, -40
 
 ; CHECK-UseAA-LABEL: @test-struct_2(
-; CHECK-UseAA: getelementptr i8* %{{[a-zA-Z0-9]+}}, i64 -40
+; CHECK-UseAA: getelementptr i8, i8* %{{[a-zA-Z0-9]+}}, i64 -40
 
 ; Test that when a index is added from two constant, SeparateConstOffsetFromGEP
 ; pass does not generate incorrect result.
 define void @test_const_add([3 x i32]* %in) {
   %inc = add nsw i32 2, 1
   %idxprom = sext i32 %inc to i64
-  %arrayidx = getelementptr [3 x i32]* %in, i64 %idxprom, i64 2
+  %arrayidx = getelementptr [3 x i32], [3 x i32]* %in, i64 %idxprom, i64 2
   store i32 0, i32* %arrayidx, align 4
   ret void
 }
diff --git a/test/CodeGen/AArch64/aarch64-smull.ll b/test/CodeGen/AArch64/aarch64-smull.ll
index 92582d7d25e9..ec0e2de92d0d 100644
--- a/test/CodeGen/AArch64/aarch64-smull.ll
+++ b/test/CodeGen/AArch64/aarch64-smull.ll
@@ -3,8 +3,8 @@
 define <8 x i16> @smull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ; CHECK-LABEL: smull_v8i8_v8i16:
 ; CHECK: smull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-  %tmp1 = load <8 x i8>* %A
-  %tmp2 = load <8 x i8>* %B
+  %tmp1 = load <8 x i8>, <8 x i8>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
   %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
   %tmp5 = mul <8 x i16> %tmp3, %tmp4
@@ -14,8 +14,8 @@ define <8 x i16> @smull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @smull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ; CHECK-LABEL: smull_v4i16_v4i32:
 ; CHECK: smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
   %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
   %tmp5 = mul <4 x i32> %tmp3, %tmp4
@@ -25,8 +25,8 @@ define <4 x i32> @smull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @smull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ; CHECK-LABEL: smull_v2i32_v2i64:
 ; CHECK:  smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
   %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
   %tmp5 = mul <2 x i64> %tmp3, %tmp4
@@ -36,8 +36,8 @@ define <2 x i64> @smull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @umull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ; CHECK-LABEL: umull_v8i8_v8i16:
 ; CHECK: umull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-  %tmp1 = load <8 x i8>* %A
-  %tmp2 = load <8 x i8>* %B
+  %tmp1 = load <8 x i8>, <8 x i8>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
   %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
   %tmp5 = mul <8 x i16> %tmp3, %tmp4
@@ -47,8 +47,8 @@ define <8 x i16> @umull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @umull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ; CHECK-LABEL: umull_v4i16_v4i32:
 ; CHECK: umull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
   %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
   %tmp5 = mul <4 x i32> %tmp3, %tmp4
@@ -58,8 +58,8 @@ define <4 x i32> @umull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @umull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ; CHECK-LABEL: umull_v2i32_v2i64:
 ; CHECK:  umull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
   %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
   %tmp5 = mul <2 x i64> %tmp3, %tmp4
@@ -69,9 +69,9 @@ define <2 x i64> @umull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @smlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ; CHECK-LABEL: smlal_v8i8_v8i16:
 ; CHECK:  smlal {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-  %tmp1 = load <8 x i16>* %A
-  %tmp2 = load <8 x i8>* %B
-  %tmp3 = load <8 x i8>* %C
+  %tmp1 = load <8 x i16>, <8 x i16>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
+  %tmp3 = load <8 x i8>, <8 x i8>* %C
   %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
   %tmp5 = sext <8 x i8> %tmp3 to <8 x i16>
   %tmp6 = mul <8 x i16> %tmp4, %tmp5
@@ -82,9 +82,9 @@ define <8 x i16> @smlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) no
 define <4 x i32> @smlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ; CHECK-LABEL: smlal_v4i16_v4i32:
 ; CHECK: smlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
-  %tmp1 = load <4 x i32>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i16>* %C
+  %tmp1 = load <4 x i32>, <4 x i32>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i16>, <4 x i16>* %C
   %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
   %tmp5 = sext <4 x i16> %tmp3 to <4 x i32>
   %tmp6 = mul <4 x i32> %tmp4, %tmp5
@@ -95,9 +95,9 @@ define <4 x i32> @smlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C)
 define <2 x i64> @smlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ; CHECK-LABEL: smlal_v2i32_v2i64:
 ; CHECK: smlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
-  %tmp1 = load <2 x i64>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i32>* %C
+  %tmp1 = load <2 x i64>, <2 x i64>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i32>, <2 x i32>* %C
   %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
   %tmp5 = sext <2 x i32> %tmp3 to <2 x i64>
   %tmp6 = mul <2 x i64> %tmp4, %tmp5
@@ -108,9 +108,9 @@ define <2 x i64> @smlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C)
 define <8 x i16> @umlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ; CHECK-LABEL: umlal_v8i8_v8i16:
 ; CHECK:  umlal {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-  %tmp1 = load <8 x i16>* %A
-  %tmp2 = load <8 x i8>* %B
-  %tmp3 = load <8 x i8>* %C
+  %tmp1 = load <8 x i16>, <8 x i16>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
+  %tmp3 = load <8 x i8>, <8 x i8>* %C
   %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
   %tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
   %tmp6 = mul <8 x i16> %tmp4, %tmp5
@@ -121,9 +121,9 @@ define <8 x i16> @umlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) no
 define <4 x i32> @umlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ; CHECK-LABEL: umlal_v4i16_v4i32:
 ; CHECK: umlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
-  %tmp1 = load <4 x i32>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i16>* %C
+  %tmp1 = load <4 x i32>, <4 x i32>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i16>, <4 x i16>* %C
   %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
   %tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
   %tmp6 = mul <4 x i32> %tmp4, %tmp5
@@ -134,9 +134,9 @@ define <4 x i32> @umlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C)
 define <2 x i64> @umlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ; CHECK-LABEL: umlal_v2i32_v2i64:
 ; CHECK: umlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
-  %tmp1 = load <2 x i64>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i32>* %C
+  %tmp1 = load <2 x i64>, <2 x i64>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i32>, <2 x i32>* %C
   %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
   %tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
   %tmp6 = mul <2 x i64> %tmp4, %tmp5
@@ -147,9 +147,9 @@ define <2 x i64> @umlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C)
 define <8 x i16> @smlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ; CHECK-LABEL: smlsl_v8i8_v8i16:
 ; CHECK:  smlsl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-  %tmp1 = load <8 x i16>* %A
-  %tmp2 = load <8 x i8>* %B
-  %tmp3 = load <8 x i8>* %C
+  %tmp1 = load <8 x i16>, <8 x i16>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
+  %tmp3 = load <8 x i8>, <8 x i8>* %C
   %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
   %tmp5 = sext <8 x i8> %tmp3 to <8 x i16>
   %tmp6 = mul <8 x i16> %tmp4, %tmp5
@@ -160,9 +160,9 @@ define <8 x i16> @smlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) no
 define <4 x i32> @smlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ; CHECK-LABEL: smlsl_v4i16_v4i32:
 ; CHECK: smlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
-  %tmp1 = load <4 x i32>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i16>* %C
+  %tmp1 = load <4 x i32>, <4 x i32>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i16>, <4 x i16>* %C
   %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
   %tmp5 = sext <4 x i16> %tmp3 to <4 x i32>
   %tmp6 = mul <4 x i32> %tmp4, %tmp5
@@ -173,9 +173,9 @@ define <4 x i32> @smlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C)
 define <2 x i64> @smlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ; CHECK-LABEL: smlsl_v2i32_v2i64:
 ; CHECK: smlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
-  %tmp1 = load <2 x i64>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i32>* %C
+  %tmp1 = load <2 x i64>, <2 x i64>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i32>, <2 x i32>* %C
   %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
   %tmp5 = sext <2 x i32> %tmp3 to <2 x i64>
   %tmp6 = mul <2 x i64> %tmp4, %tmp5
@@ -186,9 +186,9 @@ define <2 x i64> @smlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C)
 define <8 x i16> @umlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ; CHECK-LABEL: umlsl_v8i8_v8i16:
 ; CHECK:  umlsl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-  %tmp1 = load <8 x i16>* %A
-  %tmp2 = load <8 x i8>* %B
-  %tmp3 = load <8 x i8>* %C
+  %tmp1 = load <8 x i16>, <8 x i16>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
+  %tmp3 = load <8 x i8>, <8 x i8>* %C
   %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
   %tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
   %tmp6 = mul <8 x i16> %tmp4, %tmp5
@@ -199,9 +199,9 @@ define <8 x i16> @umlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) no
 define <4 x i32> @umlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ; CHECK-LABEL: umlsl_v4i16_v4i32:
 ; CHECK: umlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
-  %tmp1 = load <4 x i32>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i16>* %C
+  %tmp1 = load <4 x i32>, <4 x i32>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i16>, <4 x i16>* %C
   %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
   %tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
   %tmp6 = mul <4 x i32> %tmp4, %tmp5
@@ -212,9 +212,9 @@ define <4 x i32> @umlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C)
 define <2 x i64> @umlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ; CHECK-LABEL: umlsl_v2i32_v2i64:
 ; CHECK: umlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
-  %tmp1 = load <2 x i64>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i32>* %C
+  %tmp1 = load <2 x i64>, <2 x i64>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i32>, <2 x i32>* %C
   %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
   %tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
   %tmp6 = mul <2 x i64> %tmp4, %tmp5
diff --git a/test/CodeGen/AArch64/addsub-shifted.ll b/test/CodeGen/AArch64/addsub-shifted.ll
index 0a93edd8290a..7c7d65459938 100644
--- a/test/CodeGen/AArch64/addsub-shifted.ll
+++ b/test/CodeGen/AArch64/addsub-shifted.ll
@@ -6,63 +6,63 @@
 define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
 ; CHECK-LABEL: test_lsl_arith:
 
-  %rhs1 = load volatile i32* @var32
+  %rhs1 = load volatile i32, i32* @var32
   %shift1 = shl i32 %rhs1, 18
   %val1 = add i32 %lhs32, %shift1
   store volatile i32 %val1, i32* @var32
 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #18
 
-  %rhs2 = load volatile i32* @var32
+  %rhs2 = load volatile i32, i32* @var32
   %shift2 = shl i32 %rhs2, 31
   %val2 = add i32 %shift2, %lhs32
   store volatile i32 %val2, i32* @var32
 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
 
-  %rhs3 = load volatile i32* @var32
+  %rhs3 = load volatile i32, i32* @var32
   %shift3 = shl i32 %rhs3, 5
   %val3 = sub i32 %lhs32, %shift3
   store volatile i32 %val3, i32* @var32
 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #5
 
 ; Subtraction is not commutative!
-  %rhs4 = load volatile i32* @var32
+  %rhs4 = load volatile i32, i32* @var32
   %shift4 = shl i32 %rhs4, 19
   %val4 = sub i32 %shift4, %lhs32
   store volatile i32 %val4, i32* @var32
 ; CHECK-NOT: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #19
 
-  %lhs4a = load volatile i32* @var32
+  %lhs4a = load volatile i32, i32* @var32
   %shift4a = shl i32 %lhs4a, 15
   %val4a = sub i32 0, %shift4a
   store volatile i32 %val4a, i32* @var32
 ; CHECK: neg {{w[0-9]+}}, {{w[0-9]+}}, lsl #15
 
-  %rhs5 = load volatile i64* @var64
+  %rhs5 = load volatile i64, i64* @var64
   %shift5 = shl i64 %rhs5, 18
   %val5 = add i64 %lhs64, %shift5
   store volatile i64 %val5, i64* @var64
 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #18
 
-  %rhs6 = load volatile i64* @var64
+  %rhs6 = load volatile i64, i64* @var64
   %shift6 = shl i64 %rhs6, 31
   %val6 = add i64 %shift6, %lhs64
   store volatile i64 %val6, i64* @var64
 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #31
 
-  %rhs7 = load volatile i64* @var64
+  %rhs7 = load volatile i64, i64* @var64
   %shift7 = shl i64 %rhs7, 5
   %val7 = sub i64 %lhs64, %shift7
   store volatile i64 %val7, i64* @var64
 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #5
 
 ; Subtraction is not commutative!
-  %rhs8 = load volatile i64* @var64
+  %rhs8 = load volatile i64, i64* @var64
   %shift8 = shl i64 %rhs8, 19
   %val8 = sub i64 %shift8, %lhs64
   store volatile i64 %val8, i64* @var64
 ; CHECK-NOT: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #19
 
-  %lhs8a = load volatile i64* @var64
+  %lhs8a = load volatile i64, i64* @var64
   %shift8a = shl i64 %lhs8a, 60
   %val8a = sub i64 0, %shift8a
   store volatile i64 %val8a, i64* @var64
@@ -190,7 +190,7 @@ define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
 ; CHECK: ret
 }
 
-define i32 @test_cmp(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
+define void @test_cmp(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64, i32 %v) {
 ; CHECK-LABEL: test_cmp:
 
   %shift1 = shl i32 %rhs32, 13
@@ -199,40 +199,46 @@ define i32 @test_cmp(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
 ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, lsl #13
 
 t2:
+  store volatile i32 %v, i32* @var32
   %shift2 = lshr i32 %rhs32, 20
   %tst2 = icmp ne i32 %lhs32, %shift2
   br i1 %tst2, label %t3, label %end
 ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, lsr #20
 
 t3:
+  store volatile i32 %v, i32* @var32
   %shift3 = ashr i32 %rhs32, 9
   %tst3 = icmp ne i32 %lhs32, %shift3
   br i1 %tst3, label %t4, label %end
 ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, asr #9
 
 t4:
+  store volatile i32 %v, i32* @var32
   %shift4 = shl i64 %rhs64, 43
   %tst4 = icmp uge i64 %lhs64, %shift4
   br i1 %tst4, label %t5, label %end
 ; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}, lsl #43
 
 t5:
+  store volatile i32 %v, i32* @var32
   %shift5 = lshr i64 %rhs64, 20
   %tst5 = icmp ne i64 %lhs64, %shift5
   br i1 %tst5, label %t6, label %end
 ; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}, lsr #20
 
 t6:
+  store volatile i32 %v, i32* @var32
   %shift6 = ashr i64 %rhs64, 59
   %tst6 = icmp ne i64 %lhs64, %shift6
   br i1 %tst6, label %t7, label %end
 ; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}, asr #59
 
 t7:
-  ret i32 1
-end:
+  store volatile i32 %v, i32* @var32
+  br label %end
 
-  ret i32 0
+end:
+  ret void
 ; CHECK: ret
 }
 
diff --git a/test/CodeGen/AArch64/addsub.ll b/test/CodeGen/AArch64/addsub.ll
index b85fdbb14ce2..d6350a6db0ee 100644
--- a/test/CodeGen/AArch64/addsub.ll
+++ b/test/CodeGen/AArch64/addsub.ll
@@ -12,29 +12,57 @@ define void @add_small() {
 ; CHECK-LABEL: add_small:
 
 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4095
-  %val32 = load i32* @var_i32
+  %val32 = load i32, i32* @var_i32
   %newval32 = add i32 %val32, 4095
   store i32 %newval32, i32* @var_i32
 
 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #52
-  %val64 = load i64* @var_i64
+  %val64 = load i64, i64* @var_i64
   %newval64 = add i64 %val64, 52
   store i64 %newval64, i64* @var_i64
 
   ret void
 }
 
+; Make sure we grab the imm variant when the register operand
+; can be implicitly zero-extend.
+; We used to generate something horrible like this:
+; wA = ldrb
+; xB = ldimm 12
+; xC = add xB, wA, uxtb
+; whereas this can be achieved with:
+; wA = ldrb
+; xC = add xA, #12 ; <- xA implicitly zero extend wA.
+define void @add_small_imm(i8* %p, i64* %q, i32 %b, i32* %addr) {
+; CHECK-LABEL: add_small_imm:
+entry:
+
+; CHECK: ldrb w[[LOAD32:[0-9]+]], [x0]
+  %t = load i8, i8* %p
+  %promoted = zext i8 %t to i64
+  %zextt = zext i8 %t to i32
+  %add = add nuw i32 %zextt, %b
+
+; CHECK: add [[ADD2:x[0-9]+]], x[[LOAD32]], #12
+  %add2 = add nuw i64 %promoted, 12
+  store i32 %add, i32* %addr
+
+; CHECK: str [[ADD2]], [x1]
+  store i64 %add2, i64* %q
+  ret void
+}
+
 ; Add 12-bit immediates, shifted left by 12 bits
 define void @add_med() {
 ; CHECK-LABEL: add_med:
 
 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
-  %val32 = load i32* @var_i32
+  %val32 = load i32, i32* @var_i32
   %newval32 = add i32 %val32, 14610432 ; =0xdef000
   store i32 %newval32, i32* @var_i32
 
 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}}
-  %val64 = load i64* @var_i64
+  %val64 = load i64, i64* @var_i64
   %newval64 = add i64 %val64, 16773120 ; =0xfff000
   store i64 %newval64, i64* @var_i64
 
@@ -46,12 +74,12 @@ define void @sub_small() {
 ; CHECK-LABEL: sub_small:
 
 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4095
-  %val32 = load i32* @var_i32
+  %val32 = load i32, i32* @var_i32
   %newval32 = sub i32 %val32, 4095
   store i32 %newval32, i32* @var_i32
 
 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, #52
-  %val64 = load i64* @var_i64
+  %val64 = load i64, i64* @var_i64
   %newval64 = sub i64 %val64, 52
   store i64 %newval64, i64* @var_i64
 
@@ -63,12 +91,12 @@ define void @sub_med() {
 ; CHECK-LABEL: sub_med:
 
 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
-  %val32 = load i32* @var_i32
+  %val32 = load i32, i32* @var_i32
   %newval32 = sub i32 %val32, 14610432 ; =0xdef000
   store i32 %newval32, i32* @var_i32
 
 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}}
-  %val64 = load i64* @var_i64
+  %val64 = load i64, i64* @var_i64
   %newval64 = sub i64 %val64, 16773120 ; =0xfff000
   store i64 %newval64, i64* @var_i64
 
@@ -77,7 +105,7 @@ define void @sub_med() {
 
 define void @testing() {
 ; CHECK-LABEL: testing:
-  %val = load i32* @var_i32
+  %val = load i32, i32* @var_i32
 
 ; CHECK: cmp {{w[0-9]+}}, #4095
 ; CHECK: b.ne [[RET:.?LBB[0-9]+_[0-9]+]]
diff --git a/test/CodeGen/AArch64/addsub_ext.ll b/test/CodeGen/AArch64/addsub_ext.ll
index ceea8a08ecee..f0c7572ebf13 100644
--- a/test/CodeGen/AArch64/addsub_ext.ll
+++ b/test/CodeGen/AArch64/addsub_ext.ll
@@ -7,9 +7,9 @@
 
 define void @addsub_i8rhs() minsize {
 ; CHECK-LABEL: addsub_i8rhs:
-    %val8_tmp = load i8* @var8
-    %lhs32 = load i32* @var32
-    %lhs64 = load i64* @var64
+    %val8_tmp = load i8, i8* @var8
+    %lhs32 = load i32, i32* @var32
+    %lhs64 = load i64, i64* @var64
 
     ; Need this to prevent extension upon load and give a vanilla i8 operand.
     %val8 = add i8 %val8_tmp, 123
@@ -82,9 +82,9 @@ end:
 
 define void @addsub_i16rhs() minsize {
 ; CHECK-LABEL: addsub_i16rhs:
-    %val16_tmp = load i16* @var16
-    %lhs32 = load i32* @var32
-    %lhs64 = load i64* @var64
+    %val16_tmp = load i16, i16* @var16
+    %lhs32 = load i32, i32* @var32
+    %lhs64 = load i64, i64* @var64
 
     ; Need this to prevent extension upon load and give a vanilla i16 operand.
     %val16 = add i16 %val16_tmp, 123
@@ -160,8 +160,8 @@ end:
 ; in the face of "add/sub (shifted register)" so I don't intend to.
 define void @addsub_i32rhs() minsize {
 ; CHECK-LABEL: addsub_i32rhs:
-    %val32_tmp = load i32* @var32
-    %lhs64 = load i64* @var64
+    %val32_tmp = load i32, i32* @var32
+    %lhs64 = load i64, i64* @var64
 
     %val32 = add i32 %val32_tmp, 123
 
diff --git a/test/CodeGen/AArch64/alloca.ll b/test/CodeGen/AArch64/alloca.ll
index f93efbc42e65..5b2278ce8a35 100644
--- a/test/CodeGen/AArch64/alloca.ll
+++ b/test/CodeGen/AArch64/alloca.ll
@@ -51,7 +51,7 @@ define i64 @test_alloca_with_local(i64 %n) {
   call void @use_addr_loc(i8* %buf, i64* %loc)
 ; CHECK: bl use_addr
 
-  %val = load i64* %loc
+  %val = load i64, i64* %loc
 
 ; CHECK: ldur x0, [x29, #-[[LOC_FROM_FP]]]
 
diff --git a/test/CodeGen/AArch64/analyzecmp.ll b/test/CodeGen/AArch64/analyzecmp.ll
index 8962505cbd15..0b3bcd887b5b 100644
--- a/test/CodeGen/AArch64/analyzecmp.ll
+++ b/test/CodeGen/AArch64/analyzecmp.ll
@@ -1,9 +1,9 @@
 ; RUN: llc -O3 -mcpu=cortex-a57 < %s | FileCheck %s 
 
-; CHECK-LABLE: @test
-; CHECK: tst [[CMP:x[0-9]+]], #0x8000000000000000
-; CHECK: csel [[R0:x[0-9]+]], [[S0:x[0-9]+]], [[S1:x[0-9]+]], eq
-; CHECK: csel [[R1:x[0-9]+]], [[S2:x[0-9]+]], [[S3:x[0-9]+]], eq
+; CHECK-LABEL: @test
+; CHECK: and 
+; CHECK: csel
+; CHECK: csel
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "arm64--linux-gnueabi"
 
diff --git a/test/CodeGen/AArch64/and-mask-removal.ll b/test/CodeGen/AArch64/and-mask-removal.ll
index f803b85f733b..8291516d81ea 100644
--- a/test/CodeGen/AArch64/and-mask-removal.ll
+++ b/test/CodeGen/AArch64/and-mask-removal.ll
@@ -8,15 +8,15 @@
 define void @new_position(i32 %pos) {
 entry:
   %idxprom = sext i32 %pos to i64
-  %arrayidx = getelementptr inbounds [400 x i8]* @board, i64 0, i64 %idxprom
-  %tmp = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds [400 x i8], [400 x i8]* @board, i64 0, i64 %idxprom
+  %tmp = load i8, i8* %arrayidx, align 1
   %.off = add i8 %tmp, -1
   %switch = icmp ult i8 %.off, 2
   br i1 %switch, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %tmp1 = load i32* @next_string, align 4
-  %arrayidx8 = getelementptr inbounds [400 x i32]* @string_number, i64 0, i64 %idxprom
+  %tmp1 = load i32, i32* @next_string, align 4
+  %arrayidx8 = getelementptr inbounds [400 x i32], [400 x i32]* @string_number, i64 0, i64 %idxprom
   store i32 %tmp1, i32* %arrayidx8, align 4
   br label %if.end
 
diff --git a/test/CodeGen/AArch64/argument-blocks.ll b/test/CodeGen/AArch64/argument-blocks.ll
index f1dcfa67d0eb..3169abc2dcb3 100644
--- a/test/CodeGen/AArch64/argument-blocks.ll
+++ b/test/CodeGen/AArch64/argument-blocks.ll
@@ -64,7 +64,7 @@ define void @test_varargs_stackalign() {
 ; CHECK-LABEL: test_varargs_stackalign:
 ; CHECK-DARWINPCS: stp {{w[0-9]+}}, {{w[0-9]+}}, [sp, #16]
 
-  call void(...)* @callee([3 x float] undef, [2 x float] [float 1.0, float 2.0])
+  call void(...) @callee([3 x float] undef, [2 x float] [float 1.0, float 2.0])
   ret void
 }
 
diff --git a/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll b/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll
index 8b88c0b40887..173a440326ac 100644
--- a/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll
+++ b/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll
@@ -11,7 +11,7 @@ if.then24:                                        ; preds = %entry
   unreachable
 
 if.else295:                                       ; preds = %entry
-  call void @llvm.dbg.declare(metadata i32* %do_tab_convert, metadata !16, metadata !{!"0x102"}), !dbg !18
+  call void @llvm.dbg.declare(metadata i32* %do_tab_convert, metadata !16, metadata !DIExpression()), !dbg !18
   store i32 0, i32* %do_tab_convert, align 4, !dbg !19
   unreachable
 }
@@ -21,25 +21,25 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.gv = !{!0}
 !llvm.dbg.sp = !{!1, !7, !10, !11, !12}
 
-!0 = !{!"0x34\00vsplive\00vsplive\00\00617\001\001", !1, !2, !6, null, null} ; [ DW_TAG_variable ]
-!1 = !{!"0x2e\00drt_vsprintf\00drt_vsprintf\00\00616\000\001\000\006\00256\000\000", !20, !2, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !20} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\0012\00clang version 3.0 (http://llvm.org/git/clang.git git:/git/puzzlebox/clang.git/ c4d1aea01c4444eb81bdbf391f1be309127c3cf1)\001\00\000\00\000", !20, !21, !21, null, null, null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !20, !2, null, !5, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = !DIGlobalVariable(name: "vsplive", line: 617, isLocal: true, isDefinition: true, scope: !1, file: !2, type: !6)
+!1 = !DISubprogram(name: "drt_vsprintf", line: 616, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !2, type: !4)
+!2 = !DIFile(filename: "print.i", directory: "/Volumes/Ebi/echeng/radars/r9146594")
+!3 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (http://llvm.org/git/clang.git git:/git/puzzlebox/clang.git/ c4d1aea01c4444eb81bdbf391f1be309127c3cf1)", isOptimized: true, emissionKind: 0, file: !20, enums: !21, retainedTypes: !21)
+!4 = !DISubroutineType(types: !5)
 !5 = !{!6}
-!6 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !3} ; [ DW_TAG_base_type ]
-!7 = !{!"0x2e\00putc_mem\00putc_mem\00\0030\001\001\000\006\00256\000\000", !20, !2, !8, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!8 = !{!"0x15\00\000\000\000\000\000\000", !20, !2, null, !9, i32 0} ; [ DW_TAG_subroutine_type ]
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!7 = !DISubprogram(name: "putc_mem", line: 30, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !2, type: !8)
+!8 = !DISubroutineType(types: !9)
 !9 = !{null}
-!10 = !{!"0x2e\00print_double\00print_double\00\00203\001\001\000\006\00256\000\000", !20, !2, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!11 = !{!"0x2e\00print_number\00print_number\00\0075\001\001\000\006\00256\000\000", !20, !2, !4, i32 0, null, null, null, null} ; [ DW_TAG_subprogram ]
-!12 = !{!"0x2e\00get_flags\00get_flags\00\00508\001\001\000\006\00256\000\000", !20, !2, !8, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!13 = !MDLocation(line: 653, column: 5, scope: !14)
-!14 = !{!"0xb\00652\0035\002", !20, !15} ; [ DW_TAG_lexical_block ]
-!15 = !{!"0xb\00616\001\000", !20, !1} ; [ DW_TAG_lexical_block ]
-!16 = !{!"0x100\00do_tab_convert\00853\000", !17, !2, !6} ; [ DW_TAG_auto_variable ]
-!17 = !{!"0xb\00850\0012\0033", !20, !14} ; [ DW_TAG_lexical_block ]
-!18 = !MDLocation(line: 853, column: 11, scope: !17)
-!19 = !MDLocation(line: 853, column: 29, scope: !17)
-!20 = !{!"print.i", !"/Volumes/Ebi/echeng/radars/r9146594"}
+!10 = !DISubprogram(name: "print_double", line: 203, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !2, type: !4)
+!11 = !DISubprogram(name: "print_number", line: 75, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !2, type: !4)
+!12 = !DISubprogram(name: "get_flags", line: 508, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !2, type: !8)
+!13 = !DILocation(line: 653, column: 5, scope: !14)
+!14 = distinct !DILexicalBlock(line: 652, column: 35, file: !20, scope: !15)
+!15 = distinct !DILexicalBlock(line: 616, column: 1, file: !20, scope: !1)
+!16 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "do_tab_convert", line: 853, scope: !17, file: !2, type: !6)
+!17 = distinct !DILexicalBlock(line: 850, column: 12, file: !20, scope: !14)
+!18 = !DILocation(line: 853, column: 11, scope: !17)
+!19 = !DILocation(line: 853, column: 29, scope: !17)
+!20 = !DIFile(filename: "print.i", directory: "/Volumes/Ebi/echeng/radars/r9146594")
 !21 = !{i32 0}
diff --git a/test/CodeGen/AArch64/arm64-2011-03-21-Unaligned-Frame-Index.ll b/test/CodeGen/AArch64/arm64-2011-03-21-Unaligned-Frame-Index.ll
index 6f0ec34fc1dd..491433ce71f7 100644
--- a/test/CodeGen/AArch64/arm64-2011-03-21-Unaligned-Frame-Index.ll
+++ b/test/CodeGen/AArch64/arm64-2011-03-21-Unaligned-Frame-Index.ll
@@ -5,7 +5,7 @@ define void @foo(i64 %val) {
 ;   instruction that can handle that.
 ; CHECK: stur x0, [sp, #20]
   %a = alloca [49 x i32], align 4
-  %p32 = getelementptr inbounds [49 x i32]* %a, i64 0, i64 2
+  %p32 = getelementptr inbounds [49 x i32], [49 x i32]* %a, i64 0, i64 2
   %p = bitcast i32* %p32 to i64*
   store i64 %val, i64* %p, align 8
   ret void
diff --git a/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll b/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll
index 88232fcc0b4d..e2c39e0b6232 100644
--- a/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll
+++ b/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll
@@ -8,7 +8,7 @@ entry:
   %cmp = icmp eq i32* null, undef
   %frombool = zext i1 %cmp to i8
   store i8 %frombool, i8* undef, align 1
-  %tmp4 = load i8* undef, align 1
+  %tmp4 = load i8, i8* undef, align 1
   %tobool = trunc i8 %tmp4 to i1
   br i1 %tobool, label %land.lhs.true, label %if.end
 
diff --git a/test/CodeGen/AArch64/arm64-2011-10-18-LdStOptBug.ll b/test/CodeGen/AArch64/arm64-2011-10-18-LdStOptBug.ll
index a83f1646ef62..b69cd2421166 100644
--- a/test/CodeGen/AArch64/arm64-2011-10-18-LdStOptBug.ll
+++ b/test/CodeGen/AArch64/arm64-2011-10-18-LdStOptBug.ll
@@ -19,7 +19,7 @@ for.body:
   %0 = shl nsw i64 %indvars.iv, 12
   %add = add nsw i64 %0, 34628173824
   %1 = inttoptr i64 %add to i32*
-  %2 = load volatile i32* %1, align 4096
+  %2 = load volatile i32, i32* %1, align 4096
   store volatile i32 %2, i32* @test_data, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll b/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll
index d47dbb28164c..8d0b1b6f84cc 100644
--- a/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll
+++ b/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll
@@ -13,7 +13,7 @@ lor.lhs.false:
   br i1 undef, label %return, label %if.end
 
 if.end:
-  %tmp.i = load i64* undef, align 8
+  %tmp.i = load i64, i64* undef, align 8
   %and.i.i.i = and i64 %tmp.i, -16
   br i1 %IsArrow, label %if.else_crit_edge, label %if.end32
 
diff --git a/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll b/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll
index b5b1b70975de..ef8d6f3b4ef9 100644
--- a/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll
+++ b/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll
@@ -15,23 +15,23 @@ define hidden %struct.CGRect @t(%0* nocapture %self, i8* nocapture %_cmd) nounwi
 entry:
 ; CHECK-LABEL: t:
 ; CHECK: ldp d{{[0-9]+}}, d{{[0-9]+}}
-  %ivar = load i64* @"OBJC_IVAR_$_UIScreen._bounds", align 8, !invariant.load !4
+  %ivar = load i64, i64* @"OBJC_IVAR_$_UIScreen._bounds", align 8, !invariant.load !4
   %0 = bitcast %0* %self to i8*
-  %add.ptr = getelementptr inbounds i8* %0, i64 %ivar
+  %add.ptr = getelementptr inbounds i8, i8* %0, i64 %ivar
   %add.ptr10.0 = bitcast i8* %add.ptr to double*
-  %tmp11 = load double* %add.ptr10.0, align 8
+  %tmp11 = load double, double* %add.ptr10.0, align 8
   %add.ptr.sum = add i64 %ivar, 8
-  %add.ptr10.1 = getelementptr inbounds i8* %0, i64 %add.ptr.sum
+  %add.ptr10.1 = getelementptr inbounds i8, i8* %0, i64 %add.ptr.sum
   %1 = bitcast i8* %add.ptr10.1 to double*
-  %tmp12 = load double* %1, align 8
+  %tmp12 = load double, double* %1, align 8
   %add.ptr.sum17 = add i64 %ivar, 16
-  %add.ptr4.1 = getelementptr inbounds i8* %0, i64 %add.ptr.sum17
+  %add.ptr4.1 = getelementptr inbounds i8, i8* %0, i64 %add.ptr.sum17
   %add.ptr4.1.0 = bitcast i8* %add.ptr4.1 to double*
-  %tmp = load double* %add.ptr4.1.0, align 8
+  %tmp = load double, double* %add.ptr4.1.0, align 8
   %add.ptr4.1.sum = add i64 %ivar, 24
-  %add.ptr4.1.1 = getelementptr inbounds i8* %0, i64 %add.ptr4.1.sum
+  %add.ptr4.1.1 = getelementptr inbounds i8, i8* %0, i64 %add.ptr4.1.sum
   %2 = bitcast i8* %add.ptr4.1.1 to double*
-  %tmp5 = load double* %2, align 8
+  %tmp5 = load double, double* %2, align 8
   %insert14 = insertvalue %struct.CGPoint undef, double %tmp11, 0
   %insert16 = insertvalue %struct.CGPoint %insert14, double %tmp12, 1
   %insert = insertvalue %struct.CGRect undef, %struct.CGPoint %insert16, 0
diff --git a/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll b/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll
index 4db1f59a2c6c..b760261f7881 100644
--- a/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll
+++ b/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll
@@ -13,14 +13,14 @@ define void @testDouble(double %d) ssp {
 entry:
   %d.addr = alloca double, align 8
   store double %d, double* %d.addr, align 8
-  %0 = load double* %d.addr, align 8
-  %1 = load double* %d.addr, align 8
+  %0 = load double, double* %d.addr, align 8
+  %1 = load double, double* %d.addr, align 8
   %conv = fptoui double %1 to i64
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), double %0, i64 %conv)
-  %2 = load double* %d.addr, align 8
-  %3 = load double* %d.addr, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), double %0, i64 %conv)
+  %2 = load double, double* %d.addr, align 8
+  %3 = load double, double* %d.addr, align 8
   %conv1 = fptoui double %3 to i32
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str1, i32 0, i32 0), double %2, i32 %conv1)
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str1, i32 0, i32 0), double %2, i32 %conv1)
   ret void
 }
 
@@ -33,16 +33,16 @@ define void @testFloat(float %f) ssp {
 entry:
   %f.addr = alloca float, align 4
   store float %f, float* %f.addr, align 4
-  %0 = load float* %f.addr, align 4
+  %0 = load float, float* %f.addr, align 4
   %conv = fpext float %0 to double
-  %1 = load float* %f.addr, align 4
+  %1 = load float, float* %f.addr, align 4
   %conv1 = fptoui float %1 to i64
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str2, i32 0, i32 0), double %conv, i64 %conv1)
-  %2 = load float* %f.addr, align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str2, i32 0, i32 0), double %conv, i64 %conv1)
+  %2 = load float, float* %f.addr, align 4
   %conv2 = fpext float %2 to double
-  %3 = load float* %f.addr, align 4
+  %3 = load float, float* %f.addr, align 4
   %conv3 = fptoui float %3 to i32
-  %call4 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str3, i32 0, i32 0), double %conv2, i32 %conv3)
+  %call4 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str3, i32 0, i32 0), double %conv2, i32 %conv3)
   ret void
 }
 
diff --git a/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll b/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll
index 55ecfb5d2bd6..997431bda560 100644
--- a/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll
+++ b/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll
@@ -44,7 +44,7 @@ cond.true43:                                      ; preds = %for.body14
   unreachable
 
 cond.false45:                                     ; preds = %for.body14
-  %add.ptr = getelementptr inbounds i8* %path, i64 %conv30
+  %add.ptr = getelementptr inbounds i8, i8* %path, i64 %conv30
   unreachable
 
 if.end56:                                         ; preds = %for.cond10, %entry
diff --git a/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll b/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
index 6266d1cc9b33..8784abdadfab 100644
--- a/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
+++ b/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
@@ -7,13 +7,13 @@ define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
 ; CHECK-LABEL: bar:
 ; CHECK: add.2d	v[[REG:[0-9]+]], v0, v1
 ; CHECK: add	d[[REG3:[0-9]+]], d[[REG]], d1
+; CHECK: sub	d[[REG2:[0-9]+]], d[[REG]], d1
 ; Without advanced copy optimization, we end up with cross register
 ; banks copies that cannot be coalesced.
 ; CHECK-NOOPT: fmov [[COPY_REG3:x[0-9]+]], d[[REG3]]
 ; With advanced copy optimization, we end up with just one copy
 ; to insert the computed high part into the V register. 
 ; CHECK-OPT-NOT: fmov
-; CHECK: sub	d[[REG2:[0-9]+]], d[[REG]], d1
 ; CHECK: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]
 ; CHECK-NOOPT: fmov d0, [[COPY_REG3]]
 ; CHECK-OPT-NOT: fmov
@@ -23,9 +23,9 @@ define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
 ; GENERIC-LABEL: bar:
 ; GENERIC: add	v[[REG:[0-9]+]].2d, v0.2d, v1.2d
 ; GENERIC: add	d[[REG3:[0-9]+]], d[[REG]], d1
+; GENERIC: sub	d[[REG2:[0-9]+]], d[[REG]], d1
 ; GENERIC-NOOPT: fmov [[COPY_REG3:x[0-9]+]], d[[REG3]]
 ; GENERIC-OPT-NOT: fmov
-; GENERIC: sub	d[[REG2:[0-9]+]], d[[REG]], d1
 ; GENERIC: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]
 ; GENERIC-NOOPT: fmov d0, [[COPY_REG3]]
 ; GENERIC-OPT-NOT: fmov
diff --git a/test/CodeGen/AArch64/arm64-aapcs.ll b/test/CodeGen/AArch64/arm64-aapcs.ll
index 41c3ad5766c3..d0880cd4f3eb 100644
--- a/test/CodeGen/AArch64/arm64-aapcs.ll
+++ b/test/CodeGen/AArch64/arm64-aapcs.ll
@@ -2,6 +2,7 @@
 
 @var = global i32 0, align 4
 
+; CHECK-LABEL: @test_i128_align
 define i128 @test_i128_align(i32, i128 %arg, i32 %after) {
   store i32 %after, i32* @var, align 4
 ; CHECK: str w4, [{{x[0-9]+}}, :lo12:var]
@@ -11,6 +12,16 @@ define i128 @test_i128_align(i32, i128 %arg, i32 %after) {
 ; CHECK: mov x1, x3
 }
 
+; CHECK-LABEL: @test_i64x2_align
+define [2 x i64] @test_i64x2_align(i32, [2 x i64] %arg, i32 %after) {
+  store i32 %after, i32* @var, align 4
+; CHECK: str w3, [{{x[0-9]+}}, :lo12:var]
+
+  ret [2 x i64] %arg
+; CHECK: mov x0, x1
+; CHECK: mov x1, x2
+}
+
 @var64 = global i64 0, align 8
 
   ; Check stack slots are 64-bit at all times.
@@ -78,7 +89,7 @@ declare void @variadic(i32 %a, ...)
   ; Under AAPCS variadic functions have the same calling convention as
   ; others. The extra arguments should go in registers rather than on the stack.
 define void @test_variadic() {
-  call void(i32, ...)* @variadic(i32 0, i64 1, double 2.0)
+  call void(i32, ...) @variadic(i32 0, i64 1, double 2.0)
 ; CHECK: fmov d0, #2.0
 ; CHECK: orr w1, wzr, #0x1
 ; CHECK: bl variadic
diff --git a/test/CodeGen/AArch64/arm64-abi-varargs.ll b/test/CodeGen/AArch64/arm64-abi-varargs.ll
index 92db392cd041..03414b56144c 100644
--- a/test/CodeGen/AArch64/arm64-abi-varargs.ll
+++ b/test/CodeGen/AArch64/arm64-abi-varargs.ll
@@ -82,19 +82,19 @@ define i32 @main() nounwind ssp {
   store i32 10, i32* %a10, align 4
   store i32 11, i32* %a11, align 4
   store i32 12, i32* %a12, align 4
-  %1 = load i32* %a1, align 4
-  %2 = load i32* %a2, align 4
-  %3 = load i32* %a3, align 4
-  %4 = load i32* %a4, align 4
-  %5 = load i32* %a5, align 4
-  %6 = load i32* %a6, align 4
-  %7 = load i32* %a7, align 4
-  %8 = load i32* %a8, align 4
-  %9 = load i32* %a9, align 4
-  %10 = load i32* %a10, align 4
-  %11 = load i32* %a11, align 4
-  %12 = load i32* %a12, align 4
-  call void (i32, i32, i32, i32, i32, i32, i32, i32, i32, ...)* @fn9(i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12)
+  %1 = load i32, i32* %a1, align 4
+  %2 = load i32, i32* %a2, align 4
+  %3 = load i32, i32* %a3, align 4
+  %4 = load i32, i32* %a4, align 4
+  %5 = load i32, i32* %a5, align 4
+  %6 = load i32, i32* %a6, align 4
+  %7 = load i32, i32* %a7, align 4
+  %8 = load i32, i32* %a8, align 4
+  %9 = load i32, i32* %a9, align 4
+  %10 = load i32, i32* %a10, align 4
+  %11 = load i32, i32* %a11, align 4
+  %12 = load i32, i32* %a12, align 4
+  call void (i32, i32, i32, i32, i32, i32, i32, i32, i32, ...) @fn9(i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12)
   ret i32 0
 }
 
@@ -131,9 +131,9 @@ entry:
   %y.addr = alloca <4 x i32>, align 16
   store i32 %x, i32* %x.addr, align 4
   store <4 x i32> %y, <4 x i32>* %y.addr, align 16
-  %0 = load i32* %x.addr, align 4
-  %1 = load <4 x i32>* %y.addr, align 16
-  call void (i8*, ...)* @foo(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 %0, <4 x i32> %1)
+  %0 = load i32, i32* %x.addr, align 4
+  %1 = load <4 x i32>, <4 x i32>* %y.addr, align 16
+  call void (i8*, ...) @foo(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %0, <4 x i32> %1)
   ret void
 }
 
@@ -158,12 +158,12 @@ entry:
   call void @llvm.va_start(i8* %args1)
   %0 = va_arg i8** %args, i32
   store i32 %0, i32* %vc, align 4
-  %ap.cur = load i8** %args
-  %1 = getelementptr i8* %ap.cur, i32 15
+  %ap.cur = load i8*, i8** %args
+  %1 = getelementptr i8, i8* %ap.cur, i32 15
   %2 = ptrtoint i8* %1 to i64
   %3 = and i64 %2, -16
   %ap.align = inttoptr i64 %3 to i8*
-  %ap.next = getelementptr i8* %ap.align, i32 16
+  %ap.next = getelementptr i8, i8* %ap.align, i32 16
   store i8* %ap.next, i8** %args
   %4 = bitcast i8* %ap.align to %struct.s41*
   %5 = bitcast %struct.s41* %vs to i8*
@@ -183,9 +183,9 @@ entry:
   store i32 %x, i32* %x.addr, align 4
   %0 = bitcast %struct.s41* %s41 to i128*
   store i128 %s41.coerce, i128* %0, align 1
-  %1 = load i32* %x.addr, align 4
+  %1 = load i32, i32* %x.addr, align 4
   %2 = bitcast %struct.s41* %s41 to i128*
-  %3 = load i128* %2, align 1
-  call void (i8*, ...)* @foo2(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 %1, i128 %3)
+  %3 = load i128, i128* %2, align 1
+  call void (i8*, ...) @foo2(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %1, i128 %3)
   ret void
 }
diff --git a/test/CodeGen/AArch64/arm64-abi.ll b/test/CodeGen/AArch64/arm64-abi.ll
index 8a6b64d6ff35..36a682242aaa 100644
--- a/test/CodeGen/AArch64/arm64-abi.ll
+++ b/test/CodeGen/AArch64/arm64-abi.ll
@@ -79,7 +79,7 @@ entry:
 ; FAST: sub sp, sp
 ; FAST: mov x[[ADDR:[0-9]+]], sp
 ; FAST: str [[REG_1:q[0-9]+]], [x[[ADDR]], #16]
-  %0 = load <4 x i32>* %in, align 16
+  %0 = load <4 x i32>, <4 x i32>* %in, align 16
   %call = tail call double @args_vec_4i(double 3.000000e+00, <4 x i32> %0, <4 x i32> %0, <4 x i32> %0, <4 x i32> %0, <4 x i32> %0, <4 x i32> %0, <4 x i32> %0, double 3.000000e+00, <4 x i32> %0, i8 signext 3)
   ret double %call
 }
@@ -133,7 +133,7 @@ entry:
 ; FAST: sub sp, sp, #32
 ; FAST: mov x[[ADDR:[0-9]+]], sp
 ; FAST: str [[REG_1:d[0-9]+]], [x[[ADDR]], #8]
-  %0 = load <2 x i32>* %in, align 8
+  %0 = load <2 x i32>, <2 x i32>* %in, align 8
   %call = tail call double @args_vec_2i(double 3.000000e+00, <2 x i32> %0,
           <2 x i32> %0, <2 x i32> %0, <2 x i32> %0, <2 x i32> %0, <2 x i32> %0,
           <2 x i32> %0, float 3.000000e+00, <2 x i32> %0, i8 signext 3)
@@ -148,7 +148,7 @@ entry:
 ; CHECK: str [[REG_1:d[0-9]+]], [sp, #8]
 ; CHECK: str [[REG_2:w[0-9]+]], [sp]
 ; CHECK: orr w0, wzr, #0x3
-  %0 = load double* %in, align 8
+  %0 = load double, double* %in, align 8
   %call = tail call double @args_f64(double 3.000000e+00, double %0, double %0,
           double %0, double %0, double %0, double %0, double %0,
           float 3.000000e+00, double %0, i8 signext 3)
@@ -163,7 +163,7 @@ entry:
 ; CHECK: strb [[REG_3:w[0-9]+]], [sp, #16]
 ; CHECK: str [[REG_1:x[0-9]+]], [sp, #8]
 ; CHECK: str [[REG_2:w[0-9]+]], [sp]
-  %0 = load i64* %in, align 8
+  %0 = load i64, i64* %in, align 8
   %call = tail call i64 @args_i64(i64 3, i64 %0, i64 %0, i64 %0, i64 %0, i64 %0,
                          i64 %0, i64 %0, i32 3, i64 %0, i8 signext 3)
   ret i64 %call
@@ -177,7 +177,7 @@ entry:
 ; CHECK: strb [[REG_2:w[0-9]+]], [sp, #8]
 ; CHECK: str [[REG_1:s[0-9]+]], [sp, #4]
 ; CHECK: strh [[REG_3:w[0-9]+]], [sp]
-  %0 = load float* %in, align 4
+  %0 = load float, float* %in, align 4
   %call = tail call i32 @args_f32(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6,
           i32 7, i32 8, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0,
           float 6.0, float 7.0, float 8.0, i16 signext 3, float %0,
@@ -194,7 +194,7 @@ entry:
 ; CHECK: strb [[REG_2:w[0-9]+]], [sp, #8]
 ; CHECK: str [[REG_1:w[0-9]+]], [sp, #4]
 ; CHECK: strh [[REG_3:w[0-9]+]], [sp]
-  %0 = load i32* %in, align 4
+  %0 = load i32, i32* %in, align 4
   %call = tail call i32 @args_i32(i32 3, i32 %0, i32 %0, i32 %0, i32 %0, i32 %0,
                          i32 %0, i32 %0, i16 signext 3, i32 %0, i8 signext 4)
   ret i32 %call
diff --git a/test/CodeGen/AArch64/arm64-abi_align.ll b/test/CodeGen/AArch64/arm64-abi_align.ll
index e03d7fadaf44..1c1b58b8b140 100644
--- a/test/CodeGen/AArch64/arm64-abi_align.ll
+++ b/test/CodeGen/AArch64/arm64-abi_align.ll
@@ -59,8 +59,8 @@ entry:
 ; CHECK-LABEL: caller38
 ; CHECK: ldr x1,
 ; CHECK: ldr x2,
-  %0 = load i64* bitcast (%struct.s38* @g38 to i64*), align 4
-  %1 = load i64* bitcast (%struct.s38* @g38_2 to i64*), align 4
+  %0 = load i64, i64* bitcast (%struct.s38* @g38 to i64*), align 4
+  %1 = load i64, i64* bitcast (%struct.s38* @g38_2 to i64*), align 4
   %call = tail call i32 @f38(i32 3, i64 %0, i64 %1) #5
   ret i32 %call
 }
@@ -76,8 +76,8 @@ entry:
 ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8]
 ; CHECK: movz w[[C:[0-9]+]], #0x9
 ; CHECK: str w[[C]], [sp]
-  %0 = load i64* bitcast (%struct.s38* @g38 to i64*), align 4
-  %1 = load i64* bitcast (%struct.s38* @g38_2 to i64*), align 4
+  %0 = load i64, i64* bitcast (%struct.s38* @g38 to i64*), align 4
+  %1 = load i64, i64* bitcast (%struct.s38* @g38_2 to i64*), align 4
   %call = tail call i32 @f38_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6,
                                    i32 7, i32 8, i32 9, i64 %0, i64 %1) #5
   ret i32 %call
@@ -112,8 +112,8 @@ entry:
 ; CHECK-LABEL: caller39
 ; CHECK: ldp x1, x2,
 ; CHECK: ldp x3, x4,
-  %0 = load i128* bitcast (%struct.s39* @g39 to i128*), align 16
-  %1 = load i128* bitcast (%struct.s39* @g39_2 to i128*), align 16
+  %0 = load i128, i128* bitcast (%struct.s39* @g39 to i128*), align 16
+  %1 = load i128, i128* bitcast (%struct.s39* @g39_2 to i128*), align 16
   %call = tail call i32 @f39(i32 3, i128 %0, i128 %1) #5
   ret i32 %call
 }
@@ -130,8 +130,8 @@ entry:
 ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
 ; CHECK: movz w[[C:[0-9]+]], #0x9
 ; CHECK: str w[[C]], [sp]
-  %0 = load i128* bitcast (%struct.s39* @g39 to i128*), align 16
-  %1 = load i128* bitcast (%struct.s39* @g39_2 to i128*), align 16
+  %0 = load i128, i128* bitcast (%struct.s39* @g39 to i128*), align 16
+  %1 = load i128, i128* bitcast (%struct.s39* @g39_2 to i128*), align 16
   %call = tail call i32 @f39_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6,
                                    i32 7, i32 8, i32 9, i128 %0, i128 %1) #5
   ret i32 %call
@@ -168,8 +168,8 @@ entry:
 ; CHECK-LABEL: caller40
 ; CHECK: ldp x1, x2,
 ; CHECK: ldp x3, x4,
-  %0 = load [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4
-  %1 = load [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 4
+  %0 = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4
+  %1 = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 4
   %call = tail call i32 @f40(i32 3, [2 x i64] %0, [2 x i64] %1) #5
   ret i32 %call
 }
@@ -186,8 +186,8 @@ entry:
 ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8]
 ; CHECK: movz w[[C:[0-9]+]], #0x9
 ; CHECK: str w[[C]], [sp]
-  %0 = load [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4
-  %1 = load [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 4
+  %0 = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4
+  %1 = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 4
   %call = tail call i32 @f40_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6,
                          i32 7, i32 8, i32 9, [2 x i64] %0, [2 x i64] %1) #5
   ret i32 %call
@@ -222,8 +222,8 @@ entry:
 ; CHECK-LABEL: caller41
 ; CHECK: ldp x1, x2,
 ; CHECK: ldp x3, x4,
-  %0 = load i128* bitcast (%struct.s41* @g41 to i128*), align 16
-  %1 = load i128* bitcast (%struct.s41* @g41_2 to i128*), align 16
+  %0 = load i128, i128* bitcast (%struct.s41* @g41 to i128*), align 16
+  %1 = load i128, i128* bitcast (%struct.s41* @g41_2 to i128*), align 16
   %call = tail call i32 @f41(i32 3, i128 %0, i128 %1) #5
   ret i32 %call
 }
@@ -240,8 +240,8 @@ entry:
 ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
 ; CHECK: movz w[[C:[0-9]+]], #0x9
 ; CHECK: str w[[C]], [sp]
-  %0 = load i128* bitcast (%struct.s41* @g41 to i128*), align 16
-  %1 = load i128* bitcast (%struct.s41* @g41_2 to i128*), align 16
+  %0 = load i128, i128* bitcast (%struct.s41* @g41 to i128*), align 16
+  %1 = load i128, i128* bitcast (%struct.s41* @g41_2 to i128*), align 16
   %call = tail call i32 @f41_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6,
                             i32 7, i32 8, i32 9, i128 %0, i128 %1) #5
   ret i32 %call
@@ -260,15 +260,15 @@ entry:
 ; FAST: ldr w[[B:[0-9]+]], [x2]
 ; FAST: add w[[C:[0-9]+]], w[[A]], w0
 ; FAST: add {{w[0-9]+}}, w[[C]], w[[B]]
-  %i1 = getelementptr inbounds %struct.s42* %s1, i64 0, i32 0
-  %0 = load i32* %i1, align 4, !tbaa !0
-  %i2 = getelementptr inbounds %struct.s42* %s2, i64 0, i32 0
-  %1 = load i32* %i2, align 4, !tbaa !0
-  %s = getelementptr inbounds %struct.s42* %s1, i64 0, i32 1
-  %2 = load i16* %s, align 2, !tbaa !3
+  %i1 = getelementptr inbounds %struct.s42, %struct.s42* %s1, i64 0, i32 0
+  %0 = load i32, i32* %i1, align 4, !tbaa !0
+  %i2 = getelementptr inbounds %struct.s42, %struct.s42* %s2, i64 0, i32 0
+  %1 = load i32, i32* %i2, align 4, !tbaa !0
+  %s = getelementptr inbounds %struct.s42, %struct.s42* %s1, i64 0, i32 1
+  %2 = load i16, i16* %s, align 2, !tbaa !3
   %conv = sext i16 %2 to i32
-  %s5 = getelementptr inbounds %struct.s42* %s2, i64 0, i32 1
-  %3 = load i16* %s5, align 2, !tbaa !3
+  %s5 = getelementptr inbounds %struct.s42, %struct.s42* %s2, i64 0, i32 1
+  %3 = load i16, i16* %s5, align 2, !tbaa !3
   %conv6 = sext i16 %3 to i32
   %add = add i32 %0, %i
   %add3 = add i32 %add, %1
@@ -369,15 +369,15 @@ entry:
 ; FAST: ldr w[[B:[0-9]+]], [x2]
 ; FAST: add w[[C:[0-9]+]], w[[A]], w0
 ; FAST: add {{w[0-9]+}}, w[[C]], w[[B]]
-  %i1 = getelementptr inbounds %struct.s43* %s1, i64 0, i32 0
-  %0 = load i32* %i1, align 4, !tbaa !0
-  %i2 = getelementptr inbounds %struct.s43* %s2, i64 0, i32 0
-  %1 = load i32* %i2, align 4, !tbaa !0
-  %s = getelementptr inbounds %struct.s43* %s1, i64 0, i32 1
-  %2 = load i16* %s, align 2, !tbaa !3
+  %i1 = getelementptr inbounds %struct.s43, %struct.s43* %s1, i64 0, i32 0
+  %0 = load i32, i32* %i1, align 4, !tbaa !0
+  %i2 = getelementptr inbounds %struct.s43, %struct.s43* %s2, i64 0, i32 0
+  %1 = load i32, i32* %i2, align 4, !tbaa !0
+  %s = getelementptr inbounds %struct.s43, %struct.s43* %s1, i64 0, i32 1
+  %2 = load i16, i16* %s, align 2, !tbaa !3
   %conv = sext i16 %2 to i32
-  %s5 = getelementptr inbounds %struct.s43* %s2, i64 0, i32 1
-  %3 = load i16* %s5, align 2, !tbaa !3
+  %s5 = getelementptr inbounds %struct.s43, %struct.s43* %s2, i64 0, i32 1
+  %3 = load i16, i16* %s5, align 2, !tbaa !3
   %conv6 = sext i16 %3 to i32
   %add = add i32 %0, %i
   %add3 = add i32 %add, %1
@@ -493,7 +493,7 @@ entry:
 ; Load/Store opt is disabled with -O0, so the i128 is split.
 ; FAST: str {{x[0-9]+}}, [x[[ADDR]], #8]
 ; FAST: str {{x[0-9]+}}, [x[[ADDR]]]
-  %0 = load i128* bitcast (%struct.s41* @g41 to i128*), align 16
+  %0 = load i128, i128* bitcast (%struct.s41* @g41 to i128*), align 16
   %call = tail call i32 @callee_i128_split(i32 1, i32 2, i32 3, i32 4, i32 5,
                                            i32 6, i32 7, i128 %0, i32 8) #5
   ret i32 %call
@@ -514,7 +514,7 @@ entry:
 ; FAST: mov x[[R0:[0-9]+]], sp
 ; FAST: orr w[[R1:[0-9]+]], wzr, #0x8
 ; FAST: str w[[R1]], {{\[}}x[[R0]]{{\]}}
-  %0 = load i64* bitcast (%struct.s41* @g41 to i64*), align 16
+  %0 = load i64, i64* bitcast (%struct.s41* @g41 to i64*), align 16
   %call = tail call i32 @callee_i64(i32 1, i32 2, i32 3, i32 4, i32 5,
                                     i32 6, i32 7, i64 %0, i32 8) #5
   ret i32 %call
diff --git a/test/CodeGen/AArch64/arm64-addr-mode-folding.ll b/test/CodeGen/AArch64/arm64-addr-mode-folding.ll
index 74bb3981ba3e..3197f5bd27ec 100644
--- a/test/CodeGen/AArch64/arm64-addr-mode-folding.ll
+++ b/test/CodeGen/AArch64/arm64-addr-mode-folding.ll
@@ -11,12 +11,12 @@ define i32 @fct(i32 %i1, i32 %i2) {
 ; _CHECK-NOT_: , sxtw]
 entry:
   %idxprom = sext i32 %i1 to i64
-  %0 = load i8** @block, align 8
-  %arrayidx = getelementptr inbounds i8* %0, i64 %idxprom
-  %1 = load i8* %arrayidx, align 1
+  %0 = load i8*, i8** @block, align 8
+  %arrayidx = getelementptr inbounds i8, i8* %0, i64 %idxprom
+  %1 = load i8, i8* %arrayidx, align 1
   %idxprom1 = sext i32 %i2 to i64
-  %arrayidx2 = getelementptr inbounds i8* %0, i64 %idxprom1
-  %2 = load i8* %arrayidx2, align 1
+  %arrayidx2 = getelementptr inbounds i8, i8* %0, i64 %idxprom1
+  %2 = load i8, i8* %arrayidx2, align 1
   %cmp = icmp eq i8 %1, %2
   br i1 %cmp, label %if.end, label %if.then
 
@@ -29,11 +29,11 @@ if.end:                                           ; preds = %entry
   %inc = add nsw i32 %i1, 1
   %inc9 = add nsw i32 %i2, 1
   %idxprom10 = sext i32 %inc to i64
-  %arrayidx11 = getelementptr inbounds i8* %0, i64 %idxprom10
-  %3 = load i8* %arrayidx11, align 1
+  %arrayidx11 = getelementptr inbounds i8, i8* %0, i64 %idxprom10
+  %3 = load i8, i8* %arrayidx11, align 1
   %idxprom12 = sext i32 %inc9 to i64
-  %arrayidx13 = getelementptr inbounds i8* %0, i64 %idxprom12
-  %4 = load i8* %arrayidx13, align 1
+  %arrayidx13 = getelementptr inbounds i8, i8* %0, i64 %idxprom12
+  %4 = load i8, i8* %arrayidx13, align 1
   %cmp16 = icmp eq i8 %3, %4
   br i1 %cmp16, label %if.end23, label %if.then18
 
@@ -46,11 +46,11 @@ if.end23:                                         ; preds = %if.end
   %inc24 = add nsw i32 %i1, 2
   %inc25 = add nsw i32 %i2, 2
   %idxprom26 = sext i32 %inc24 to i64
-  %arrayidx27 = getelementptr inbounds i8* %0, i64 %idxprom26
-  %5 = load i8* %arrayidx27, align 1
+  %arrayidx27 = getelementptr inbounds i8, i8* %0, i64 %idxprom26
+  %5 = load i8, i8* %arrayidx27, align 1
   %idxprom28 = sext i32 %inc25 to i64
-  %arrayidx29 = getelementptr inbounds i8* %0, i64 %idxprom28
-  %6 = load i8* %arrayidx29, align 1
+  %arrayidx29 = getelementptr inbounds i8, i8* %0, i64 %idxprom28
+  %6 = load i8, i8* %arrayidx29, align 1
   %cmp32 = icmp eq i8 %5, %6
   br i1 %cmp32, label %return, label %if.then34
 
@@ -71,12 +71,12 @@ define i32 @fct1(i32 %i1, i32 %i2) optsize {
 ; CHECK: , sxtw]
 entry:
   %idxprom = sext i32 %i1 to i64
-  %0 = load i8** @block, align 8
-  %arrayidx = getelementptr inbounds i8* %0, i64 %idxprom
-  %1 = load i8* %arrayidx, align 1
+  %0 = load i8*, i8** @block, align 8
+  %arrayidx = getelementptr inbounds i8, i8* %0, i64 %idxprom
+  %1 = load i8, i8* %arrayidx, align 1
   %idxprom1 = sext i32 %i2 to i64
-  %arrayidx2 = getelementptr inbounds i8* %0, i64 %idxprom1
-  %2 = load i8* %arrayidx2, align 1
+  %arrayidx2 = getelementptr inbounds i8, i8* %0, i64 %idxprom1
+  %2 = load i8, i8* %arrayidx2, align 1
   %cmp = icmp eq i8 %1, %2
   br i1 %cmp, label %if.end, label %if.then
 
@@ -89,11 +89,11 @@ if.end:                                           ; preds = %entry
   %inc = add nsw i32 %i1, 1
   %inc9 = add nsw i32 %i2, 1
   %idxprom10 = sext i32 %inc to i64
-  %arrayidx11 = getelementptr inbounds i8* %0, i64 %idxprom10
-  %3 = load i8* %arrayidx11, align 1
+  %arrayidx11 = getelementptr inbounds i8, i8* %0, i64 %idxprom10
+  %3 = load i8, i8* %arrayidx11, align 1
   %idxprom12 = sext i32 %inc9 to i64
-  %arrayidx13 = getelementptr inbounds i8* %0, i64 %idxprom12
-  %4 = load i8* %arrayidx13, align 1
+  %arrayidx13 = getelementptr inbounds i8, i8* %0, i64 %idxprom12
+  %4 = load i8, i8* %arrayidx13, align 1
   %cmp16 = icmp eq i8 %3, %4
   br i1 %cmp16, label %if.end23, label %if.then18
 
@@ -106,11 +106,11 @@ if.end23:                                         ; preds = %if.end
   %inc24 = add nsw i32 %i1, 2
   %inc25 = add nsw i32 %i2, 2
   %idxprom26 = sext i32 %inc24 to i64
-  %arrayidx27 = getelementptr inbounds i8* %0, i64 %idxprom26
-  %5 = load i8* %arrayidx27, align 1
+  %arrayidx27 = getelementptr inbounds i8, i8* %0, i64 %idxprom26
+  %5 = load i8, i8* %arrayidx27, align 1
   %idxprom28 = sext i32 %inc25 to i64
-  %arrayidx29 = getelementptr inbounds i8* %0, i64 %idxprom28
-  %6 = load i8* %arrayidx29, align 1
+  %arrayidx29 = getelementptr inbounds i8, i8* %0, i64 %idxprom28
+  %6 = load i8, i8* %arrayidx29, align 1
   %cmp32 = icmp eq i8 %5, %6
   br i1 %cmp32, label %return, label %if.then34
 
@@ -135,9 +135,9 @@ entry:
 
 if.then:                                          ; preds = %entry
   %idxprom = zext i8 %c to i64
-  %arrayidx = getelementptr inbounds i32* %array, i64 %idxprom
-  %0 = load volatile i32* %arrayidx, align 4
-  %1 = load volatile i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %array, i64 %idxprom
+  %0 = load volatile i32, i32* %arrayidx, align 4
+  %1 = load volatile i32, i32* %arrayidx, align 4
   %add3 = add nsw i32 %1, %0
   br label %if.end
 
@@ -159,9 +159,9 @@ entry:
 
 if.then:                                          ; preds = %entry
   %idxprom = zext i8 %c to i64
-  %arrayidx = getelementptr inbounds i32* %array, i64 %idxprom
-  %0 = load volatile i32* %arrayidx, align 4
-  %1 = load volatile i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %array, i64 %idxprom
+  %0 = load volatile i32, i32* %arrayidx, align 4
+  %1 = load volatile i32, i32* %arrayidx, align 4
   %add3 = add nsw i32 %1, %0
   br label %if.end
 
diff --git a/test/CodeGen/AArch64/arm64-addr-type-promotion.ll b/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
index 1a3ca8bd5b8c..4703d25a6016 100644
--- a/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
+++ b/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
@@ -28,12 +28,12 @@ define zeroext i8 @fullGtU(i32 %i1, i32 %i2) {
 ; CHECK-NEXT: cmp [[LOADEDVAL3]], [[LOADEDVAL4]]
 entry:
   %idxprom = sext i32 %i1 to i64
-  %tmp = load i8** @block, align 8
-  %arrayidx = getelementptr inbounds i8* %tmp, i64 %idxprom
-  %tmp1 = load i8* %arrayidx, align 1
+  %tmp = load i8*, i8** @block, align 8
+  %arrayidx = getelementptr inbounds i8, i8* %tmp, i64 %idxprom
+  %tmp1 = load i8, i8* %arrayidx, align 1
   %idxprom1 = sext i32 %i2 to i64
-  %arrayidx2 = getelementptr inbounds i8* %tmp, i64 %idxprom1
-  %tmp2 = load i8* %arrayidx2, align 1
+  %arrayidx2 = getelementptr inbounds i8, i8* %tmp, i64 %idxprom1
+  %tmp2 = load i8, i8* %arrayidx2, align 1
   %cmp = icmp eq i8 %tmp1, %tmp2
   br i1 %cmp, label %if.end, label %if.then
 
@@ -46,11 +46,11 @@ if.end:                                           ; preds = %entry
   %inc = add nsw i32 %i1, 1
   %inc10 = add nsw i32 %i2, 1
   %idxprom11 = sext i32 %inc to i64
-  %arrayidx12 = getelementptr inbounds i8* %tmp, i64 %idxprom11
-  %tmp3 = load i8* %arrayidx12, align 1
+  %arrayidx12 = getelementptr inbounds i8, i8* %tmp, i64 %idxprom11
+  %tmp3 = load i8, i8* %arrayidx12, align 1
   %idxprom13 = sext i32 %inc10 to i64
-  %arrayidx14 = getelementptr inbounds i8* %tmp, i64 %idxprom13
-  %tmp4 = load i8* %arrayidx14, align 1
+  %arrayidx14 = getelementptr inbounds i8, i8* %tmp, i64 %idxprom13
+  %tmp4 = load i8, i8* %arrayidx14, align 1
   %cmp17 = icmp eq i8 %tmp3, %tmp4
   br i1 %cmp17, label %if.end25, label %if.then19
 
@@ -63,11 +63,11 @@ if.end25:                                         ; preds = %if.end
   %inc26 = add nsw i32 %i1, 2
   %inc27 = add nsw i32 %i2, 2
   %idxprom28 = sext i32 %inc26 to i64
-  %arrayidx29 = getelementptr inbounds i8* %tmp, i64 %idxprom28
-  %tmp5 = load i8* %arrayidx29, align 1
+  %arrayidx29 = getelementptr inbounds i8, i8* %tmp, i64 %idxprom28
+  %tmp5 = load i8, i8* %arrayidx29, align 1
   %idxprom30 = sext i32 %inc27 to i64
-  %arrayidx31 = getelementptr inbounds i8* %tmp, i64 %idxprom30
-  %tmp6 = load i8* %arrayidx31, align 1
+  %arrayidx31 = getelementptr inbounds i8, i8* %tmp, i64 %idxprom30
+  %tmp6 = load i8, i8* %arrayidx31, align 1
   %cmp34 = icmp eq i8 %tmp5, %tmp6
   br i1 %cmp34, label %return, label %if.then36
 
diff --git a/test/CodeGen/AArch64/arm64-addrmode.ll b/test/CodeGen/AArch64/arm64-addrmode.ll
index 5433a8c312fe..c22d0312b24d 100644
--- a/test/CodeGen/AArch64/arm64-addrmode.ll
+++ b/test/CodeGen/AArch64/arm64-addrmode.ll
@@ -8,8 +8,8 @@
 ; CHECK: ldr xzr, [x{{[0-9]+}}, #8]
 ; CHECK: ret
 define void @t1() {
-  %incdec.ptr = getelementptr inbounds i64* @object, i64 1
-  %tmp = load volatile i64* %incdec.ptr, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 1
+  %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
 
@@ -20,8 +20,8 @@ define void @t1() {
 ; CHECK: [[ADDREG]]]
 ; CHECK: ret
 define void @t2() {
-  %incdec.ptr = getelementptr inbounds i64* @object, i64 -33
-  %tmp = load volatile i64* %incdec.ptr, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 -33
+  %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
 
@@ -30,8 +30,8 @@ define void @t2() {
 ; CHECK: ldr xzr, [x{{[0-9]+}}, #32760]
 ; CHECK: ret
 define void @t3() {
-  %incdec.ptr = getelementptr inbounds i64* @object, i64 4095
-  %tmp = load volatile i64* %incdec.ptr, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 4095
+  %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
 
@@ -41,8 +41,8 @@ define void @t3() {
 ; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
 ; CHECK: ret
 define void @t4() {
-  %incdec.ptr = getelementptr inbounds i64* @object, i64 4096
-  %tmp = load volatile i64* %incdec.ptr, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 4096
+  %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
 
@@ -51,8 +51,8 @@ define void @t4() {
 ; CHECK: ldr xzr, [x{{[0-9]+}}, x{{[0-9]+}}, lsl #3]
 ; CHECK: ret
 define void @t5(i64 %a) {
-  %incdec.ptr = getelementptr inbounds i64* @object, i64 %a
-  %tmp = load volatile i64* %incdec.ptr, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 %a
+  %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
 
@@ -63,9 +63,9 @@ define void @t5(i64 %a) {
 ; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
 ; CHECK: ret
 define void @t6(i64 %a) {
-  %tmp1 = getelementptr inbounds i64* @object, i64 %a
-  %incdec.ptr = getelementptr inbounds i64* %tmp1, i64 4096
-  %tmp = load volatile i64* %incdec.ptr, align 8
+  %tmp1 = getelementptr inbounds i64, i64* @object, i64 %a
+  %incdec.ptr = getelementptr inbounds i64, i64* %tmp1, i64 4096
+  %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
 
@@ -76,7 +76,7 @@ define void @t7(i64 %a) {
 ; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]]
   %1 = add i64 %a, 65535   ;0xffff
   %2 = inttoptr i64 %1 to i64*
-  %3 = load volatile i64* %2, align 8
+  %3 = load volatile i64, i64* %2, align 8
   ret void
 }
 
@@ -86,7 +86,7 @@ define void @t8(i64 %a) {
 ; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
   %1 = sub i64 %a, 4662   ;-4662 is 0xffffffffffffedca
   %2 = inttoptr i64 %1 to i64*
-  %3 = load volatile i64* %2, align 8
+  %3 = load volatile i64, i64* %2, align 8
   ret void
 }
 
@@ -96,7 +96,7 @@ define void @t9(i64 %a) {
 ; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
   %1 = add i64 -305463297, %a   ;-305463297 is 0xffffffffedcaffff
   %2 = inttoptr i64 %1 to i64*
-  %3 = load volatile i64* %2, align 8
+  %3 = load volatile i64, i64* %2, align 8
   ret void
 }
 
@@ -106,7 +106,7 @@ define void @t10(i64 %a) {
 ; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
   %1 = add i64 %a, 81909218222800896   ;0x123000000000000
   %2 = inttoptr i64 %1 to i64*
-  %3 = load volatile i64* %2, align 8
+  %3 = load volatile i64, i64* %2, align 8
   ret void
 }
 
@@ -117,7 +117,7 @@ define void @t11(i64 %a) {
 ; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]]
   %1 = add i64 %a, 19088743   ;0x1234567
   %2 = inttoptr i64 %1 to i64*
-  %3 = load volatile i64* %2, align 8
+  %3 = load volatile i64, i64* %2, align 8
   ret void
 }
 
@@ -128,7 +128,7 @@ define void @t12(i64 %a) {
 ; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]]
   %1 = add i64 %a, 4095   ;0xfff
   %2 = inttoptr i64 %1 to i64*
-  %3 = load volatile i64* %2, align 8
+  %3 = load volatile i64, i64* %2, align 8
   ret void
 }
 
@@ -138,7 +138,7 @@ define void @t13(i64 %a) {
 ; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]]
   %1 = add i64 %a, -4095   ;-0xfff
   %2 = inttoptr i64 %1 to i64*
-  %3 = load volatile i64* %2, align 8
+  %3 = load volatile i64, i64* %2, align 8
   ret void
 }
 
@@ -148,7 +148,7 @@ define void @t14(i64 %a) {
 ; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]]
   %1 = add i64 %a, 1191936   ;0x123000
   %2 = inttoptr i64 %1 to i64*
-  %3 = load volatile i64* %2, align 8
+  %3 = load volatile i64, i64* %2, align 8
   ret void
 }
 
@@ -158,7 +158,7 @@ define void @t15(i64 %a) {
 ; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]]
   %1 = add i64 %a, -1191936   ;0xFFFFFFFFFFEDD000
   %2 = inttoptr i64 %1 to i64*
-  %3 = load volatile i64* %2, align 8
+  %3 = load volatile i64, i64* %2, align 8
   ret void
 }
 
@@ -167,7 +167,7 @@ define void @t16(i64 %a) {
 ; CHECK: ldr xzr, [x0, #28672]
   %1 = add i64 %a, 28672   ;0x7000
   %2 = inttoptr i64 %1 to i64*
-  %3 = load volatile i64* %2, align 8
+  %3 = load volatile i64, i64* %2, align 8
   ret void
 }
 
@@ -176,6 +176,6 @@ define void @t17(i64 %a) {
 ; CHECK: ldur xzr, [x0, #-256]
   %1 = add i64 %a, -256   ;-0x100
   %2 = inttoptr i64 %1 to i64*
-  %3 = load volatile i64* %2, align 8
+  %3 = load volatile i64, i64* %2, align 8
   ret void
 }
diff --git a/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll b/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll
index f396bc991708..bf2d2cfa6066 100644
--- a/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll
+++ b/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll
@@ -13,9 +13,9 @@ entry:
 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE:x[0-9]+]], #32]
 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE]]]
  %retval = alloca <16 x float>, align 16
- %0 = load <16 x float>* @T3_retval, align 16
+ %0 = load <16 x float>, <16 x float>* @T3_retval, align 16
  store <16 x float> %0, <16 x float>* %retval
- %1 = load <16 x float>* %retval
+ %1 = load <16 x float>, <16 x float>* %retval
  store <16 x float> %1, <16 x float>* %agg.result, align 16
  ret void
 }
diff --git a/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll b/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll
index 3750f31b3734..eb0cd3547bda 100644
--- a/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll
+++ b/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll
@@ -13,17 +13,17 @@ define i32 @foo(i32 %a) nounwind {
   %arr2 = alloca [32 x i32], align 4
   %j = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
-  %tmp = load i32* %a.addr, align 4
+  %tmp = load i32, i32* %a.addr, align 4
   %tmp1 = zext i32 %tmp to i64
   %v = mul i64 4, %tmp1
   %vla = alloca i8, i64 %v, align 4
   %tmp2 = bitcast i8* %vla to i32*
-  %tmp3 = load i32* %a.addr, align 4
+  %tmp3 = load i32, i32* %a.addr, align 4
   store i32 %tmp3, i32* %i, align 4
-  %tmp4 = load i32* %a.addr, align 4
+  %tmp4 = load i32, i32* %a.addr, align 4
   store i32 %tmp4, i32* %j, align 4
-  %tmp5 = load i32* %j, align 4
+  %tmp5 = load i32, i32* %j, align 4
   store i32 %tmp5, i32* %retval
-  %x = load i32* %retval
+  %x = load i32, i32* %retval
   ret i32 %x
 }
diff --git a/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll b/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll
index 419497722f4c..71e64807f524 100644
--- a/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll
+++ b/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll
@@ -29,7 +29,7 @@ _ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit: ; preds = %lor.rhs.i.i
   br i1 %cmp.i.i.i.i, label %if.then3, label %if.end5
 
 if.then3:                                         ; preds = %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, %land.rhs.i
-  %tmp11 = load i8* %str14, align 8
+  %tmp11 = load i8, i8* %str14, align 8
   %tmp12 = and i8 %tmp11, 2
   %tmp13 = icmp ne i8 %tmp12, 0
   br label %return
@@ -55,7 +55,7 @@ if.then7:                                         ; preds = %_ZNK7WebCore4Node10
   br i1 %isTextField, label %if.then9, label %if.end12
 
 if.then9:                                         ; preds = %if.then7
-  %tmp23 = load i8* %str5, align 8
+  %tmp23 = load i8, i8* %str5, align 8
   %tmp24 = and i8 %tmp23, 2
   %tmp25 = icmp ne i8 %tmp24, 0
   br label %return
diff --git a/test/CodeGen/AArch64/arm64-anyregcc-crash.ll b/test/CodeGen/AArch64/arm64-anyregcc-crash.ll
index 241cf974c05b..56c62d5fe7db 100644
--- a/test/CodeGen/AArch64/arm64-anyregcc-crash.ll
+++ b/test/CodeGen/AArch64/arm64-anyregcc-crash.ll
@@ -8,7 +8,7 @@ define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i6
                         i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24,
                         i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32) {
 entry:
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 32,
+  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 32,
                 i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
                 i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16,
                 i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24,
diff --git a/test/CodeGen/AArch64/arm64-anyregcc.ll b/test/CodeGen/AArch64/arm64-anyregcc.ll
index e26875d52f99..2a2f45196046 100644
--- a/test/CodeGen/AArch64/arm64-anyregcc.ll
+++ b/test/CodeGen/AArch64/arm64-anyregcc.ll
@@ -55,7 +55,7 @@
 ; CHECK-NEXT:   .long 3
 define i64 @test() nounwind ssp uwtable {
 entry:
-  call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 0, i32 16, i8* null, i32 2, i32 1, i32 2, i64 3)
+  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 16, i8* null, i32 2, i32 1, i32 2, i64 3)
   ret i64 0
 }
 
@@ -77,7 +77,7 @@ entry:
 define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 1, i32 20, i8* %f, i32 1, i8* %obj)
+  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 20, i8* %f, i32 1, i8* %obj)
   ret i64 %ret
 }
 
@@ -100,7 +100,7 @@ define i64 @property_access2() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
   %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %f, i32 1, i64* %obj)
+  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %f, i32 1, i64* %obj)
   ret i64 %ret
 }
 
@@ -123,7 +123,7 @@ define i64 @property_access3() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
   %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 20, i8* %f, i32 0, i64* %obj)
+  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 20, i8* %f, i32 0, i64* %obj)
   ret i64 %ret
 }
 
@@ -205,7 +205,7 @@ entry:
 define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 4, i32 20, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
+  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 20, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
   ret i64 %ret
 }
 
@@ -287,7 +287,7 @@ entry:
 define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
+  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
   ret i64 %ret
 }
 
@@ -315,7 +315,7 @@ entry:
 ; CHECK-NEXT: .long  0
 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
+  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
   tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
   ret i64 %result
 }
@@ -355,7 +355,7 @@ entry:
 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
   tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 13, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
+  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
   ret i64 %result
 }
 
diff --git a/test/CodeGen/AArch64/arm64-atomic-128.ll b/test/CodeGen/AArch64/arm64-atomic-128.ll
index 642d72aac47e..a76cf74a6d0c 100644
--- a/test/CodeGen/AArch64/arm64-atomic-128.ll
+++ b/test/CodeGen/AArch64/arm64-atomic-128.ll
@@ -169,7 +169,7 @@ define i128 @atomic_load_seq_cst(i128* %p) {
 ; CHECK-NOT: dmb
 ; CHECK-LABEL: ldaxp
 ; CHECK-NOT: dmb
-   %r = load atomic i128* %p seq_cst, align 16
+   %r = load atomic i128, i128* %p seq_cst, align 16
    ret i128 %r
 }
 
@@ -178,7 +178,7 @@ define i128 @atomic_load_relaxed(i128* %p) {
 ; CHECK-NOT: dmb
 ; CHECK: ldxp [[LO:x[0-9]+]], [[HI:x[0-9]+]], [x0]
 ; CHECK-NOT: dmb
-   %r = load atomic i128* %p monotonic, align 16
+   %r = load atomic i128, i128* %p monotonic, align 16
    ret i128 %r
 }
 
diff --git a/test/CodeGen/AArch64/arm64-atomic.ll b/test/CodeGen/AArch64/arm64-atomic.ll
index b56f91ddd111..9136fb6271b5 100644
--- a/test/CodeGen/AArch64/arm64-atomic.ll
+++ b/test/CodeGen/AArch64/arm64-atomic.ll
@@ -1,37 +1,49 @@
-; RUN: llc < %s -march=arm64 -verify-machineinstrs -mcpu=cyclone | FileCheck %s
+; RUN: llc < %s -march=arm64 -asm-verbose=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s
 
-define i32 @val_compare_and_swap(i32* %p) {
+define i32 @val_compare_and_swap(i32* %p, i32 %cmp, i32 %new) #0 {
 ; CHECK-LABEL: val_compare_and_swap:
-; CHECK: orr    [[NEWVAL_REG:w[0-9]+]], wzr, #0x4
-; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
-; CHECK: ldaxr   [[RESULT:w[0-9]+]], [x0]
-; CHECK: cmp    [[RESULT]], #7
-; CHECK: b.ne   [[LABEL2:.?LBB[0-9]+_[0-9]+]]
-; CHECK: stxr   [[SCRATCH_REG:w[0-9]+]], [[NEWVAL_REG]], [x0]
-; CHECK: cbnz   [[SCRATCH_REG]], [[LABEL]]
-; CHECK: [[LABEL2]]:
-  %pair = cmpxchg i32* %p, i32 7, i32 4 acquire acquire
+; CHECK-NEXT: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
+; CHECK-NEXT: ldaxr  [[RESULT:w[0-9]+]], [x0]
+; CHECK-NEXT: cmp    [[RESULT]], w1
+; CHECK-NEXT: b.ne   [[LABEL2:.?LBB[0-9]+_[0-9]+]]
+; CHECK-NEXT: stxr   [[SCRATCH_REG:w[0-9]+]], w2, [x0]
+; CHECK-NEXT: cbnz   [[SCRATCH_REG]], [[LABEL]]
+; CHECK-NEXT: [[LABEL2]]:
+  %pair = cmpxchg i32* %p, i32 %cmp, i32 %new acquire acquire
   %val = extractvalue { i32, i1 } %pair, 0
   ret i32 %val
 }
 
-define i64 @val_compare_and_swap_64(i64* %p) {
+define i32 @val_compare_and_swap_rel(i32* %p, i32 %cmp, i32 %new) #0 {
+; CHECK-LABEL: val_compare_and_swap_rel:
+; CHECK-NEXT: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
+; CHECK-NEXT: ldaxr  [[RESULT:w[0-9]+]], [x0]
+; CHECK-NEXT: cmp    [[RESULT]], w1
+; CHECK-NEXT: b.ne   [[LABEL2:.?LBB[0-9]+_[0-9]+]]
+; CHECK-NEXT: stlxr  [[SCRATCH_REG:w[0-9]+]], w2, [x0]
+; CHECK-NEXT: cbnz   [[SCRATCH_REG]], [[LABEL]]
+; CHECK-NEXT: [[LABEL2]]:
+  %pair = cmpxchg i32* %p, i32 %cmp, i32 %new acq_rel monotonic
+  %val = extractvalue { i32, i1 } %pair, 0
+  ret i32 %val
+}
+
+define i64 @val_compare_and_swap_64(i64* %p, i64 %cmp, i64 %new) #0 {
 ; CHECK-LABEL: val_compare_and_swap_64:
-; CHECK: orr    w[[NEWVAL_REG:[0-9]+]], wzr, #0x4
-; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
-; CHECK: ldxr   [[RESULT:x[0-9]+]], [x0]
-; CHECK: cmp    [[RESULT]], #7
-; CHECK: b.ne   [[LABEL2:.?LBB[0-9]+_[0-9]+]]
-; CHECK-NOT: stxr x[[NEWVAL_REG]], x[[NEWVAL_REG]]
-; CHECK: stxr   [[SCRATCH_REG:w[0-9]+]], x[[NEWVAL_REG]], [x0]
-; CHECK: cbnz   [[SCRATCH_REG]], [[LABEL]]
-; CHECK: [[LABEL2]]:
-  %pair = cmpxchg i64* %p, i64 7, i64 4 monotonic monotonic
+; CHECK-NEXT: mov    x[[ADDR:[0-9]+]], x0
+; CHECK-NEXT: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
+; CHECK-NEXT: ldxr   [[RESULT:x[0-9]+]], [x[[ADDR]]]
+; CHECK-NEXT: cmp    [[RESULT]], x1
+; CHECK-NEXT: b.ne   [[LABEL2:.?LBB[0-9]+_[0-9]+]]
+; CHECK-NEXT: stxr   [[SCRATCH_REG:w[0-9]+]], x2, [x[[ADDR]]]
+; CHECK-NEXT: cbnz   [[SCRATCH_REG]], [[LABEL]]
+; CHECK-NEXT: [[LABEL2]]:
+  %pair = cmpxchg i64* %p, i64 %cmp, i64 %new monotonic monotonic
   %val = extractvalue { i64, i1 } %pair, 0
   ret i64 %val
 }
 
-define i32 @fetch_and_nand(i32* %p) {
+define i32 @fetch_and_nand(i32* %p) #0 {
 ; CHECK-LABEL: fetch_and_nand:
 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
 ; CHECK: ldxr   w[[DEST_REG:[0-9]+]], [x0]
@@ -45,7 +57,7 @@ define i32 @fetch_and_nand(i32* %p) {
   ret i32 %val
 }
 
-define i64 @fetch_and_nand_64(i64* %p) {
+define i64 @fetch_and_nand_64(i64* %p) #0 {
 ; CHECK-LABEL: fetch_and_nand_64:
 ; CHECK: mov    x[[ADDR:[0-9]+]], x0
 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
@@ -59,7 +71,7 @@ define i64 @fetch_and_nand_64(i64* %p) {
   ret i64 %val
 }
 
-define i32 @fetch_and_or(i32* %p) {
+define i32 @fetch_and_or(i32* %p) #0 {
 ; CHECK-LABEL: fetch_and_or:
 ; CHECK: movz   [[OLDVAL_REG:w[0-9]+]], #0x5
 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
@@ -73,7 +85,7 @@ define i32 @fetch_and_or(i32* %p) {
   ret i32 %val
 }
 
-define i64 @fetch_and_or_64(i64* %p) {
+define i64 @fetch_and_or_64(i64* %p) #0 {
 ; CHECK: fetch_and_or_64:
 ; CHECK: mov    x[[ADDR:[0-9]+]], x0
 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
@@ -85,52 +97,52 @@ define i64 @fetch_and_or_64(i64* %p) {
   ret i64 %val
 }
 
-define void @acquire_fence() {
+define void @acquire_fence() #0 {
    fence acquire
    ret void
    ; CHECK-LABEL: acquire_fence:
    ; CHECK: dmb ishld
 }
 
-define void @release_fence() {
+define void @release_fence() #0 {
    fence release
    ret void
    ; CHECK-LABEL: release_fence:
    ; CHECK: dmb ish{{$}}
 }
 
-define void @seq_cst_fence() {
+define void @seq_cst_fence() #0 {
    fence seq_cst
    ret void
    ; CHECK-LABEL: seq_cst_fence:
    ; CHECK: dmb ish{{$}}
 }
 
-define i32 @atomic_load(i32* %p) {
-   %r = load atomic i32* %p seq_cst, align 4
+define i32 @atomic_load(i32* %p) #0 {
+   %r = load atomic i32, i32* %p seq_cst, align 4
    ret i32 %r
    ; CHECK-LABEL: atomic_load:
    ; CHECK: ldar
 }
 
-define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) {
+define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) #0 {
 ; CHECK-LABEL: atomic_load_relaxed_8:
-  %ptr_unsigned = getelementptr i8* %p, i32 4095
-  %val_unsigned = load atomic i8* %ptr_unsigned monotonic, align 1
+  %ptr_unsigned = getelementptr i8, i8* %p, i32 4095
+  %val_unsigned = load atomic i8, i8* %ptr_unsigned monotonic, align 1
 ; CHECK: ldrb {{w[0-9]+}}, [x0, #4095]
 
-  %ptr_regoff = getelementptr i8* %p, i32 %off32
-  %val_regoff = load atomic i8* %ptr_regoff unordered, align 1
+  %ptr_regoff = getelementptr i8, i8* %p, i32 %off32
+  %val_regoff = load atomic i8, i8* %ptr_regoff unordered, align 1
   %tot1 = add i8 %val_unsigned, %val_regoff
 ; CHECK: ldrb {{w[0-9]+}}, [x0, w1, sxtw]
 
-  %ptr_unscaled = getelementptr i8* %p, i32 -256
-  %val_unscaled = load atomic i8* %ptr_unscaled monotonic, align 1
+  %ptr_unscaled = getelementptr i8, i8* %p, i32 -256
+  %val_unscaled = load atomic i8, i8* %ptr_unscaled monotonic, align 1
   %tot2 = add i8 %tot1, %val_unscaled
 ; CHECK: ldurb {{w[0-9]+}}, [x0, #-256]
 
-  %ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
-  %val_random = load atomic i8* %ptr_random unordered, align 1
+  %ptr_random = getelementptr i8, i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
+  %val_random = load atomic i8, i8* %ptr_random unordered, align 1
   %tot3 = add i8 %tot2, %val_random
 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: ldrb {{w[0-9]+}}, [x[[ADDR]]]
@@ -138,24 +150,24 @@ define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) {
   ret i8 %tot3
 }
 
-define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) {
+define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) #0 {
 ; CHECK-LABEL: atomic_load_relaxed_16:
-  %ptr_unsigned = getelementptr i16* %p, i32 4095
-  %val_unsigned = load atomic i16* %ptr_unsigned monotonic, align 2
+  %ptr_unsigned = getelementptr i16, i16* %p, i32 4095
+  %val_unsigned = load atomic i16, i16* %ptr_unsigned monotonic, align 2
 ; CHECK: ldrh {{w[0-9]+}}, [x0, #8190]
 
-  %ptr_regoff = getelementptr i16* %p, i32 %off32
-  %val_regoff = load atomic i16* %ptr_regoff unordered, align 2
+  %ptr_regoff = getelementptr i16, i16* %p, i32 %off32
+  %val_regoff = load atomic i16, i16* %ptr_regoff unordered, align 2
   %tot1 = add i16 %val_unsigned, %val_regoff
 ; CHECK: ldrh {{w[0-9]+}}, [x0, w1, sxtw #1]
 
-  %ptr_unscaled = getelementptr i16* %p, i32 -128
-  %val_unscaled = load atomic i16* %ptr_unscaled monotonic, align 2
+  %ptr_unscaled = getelementptr i16, i16* %p, i32 -128
+  %val_unscaled = load atomic i16, i16* %ptr_unscaled monotonic, align 2
   %tot2 = add i16 %tot1, %val_unscaled
 ; CHECK: ldurh {{w[0-9]+}}, [x0, #-256]
 
-  %ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
-  %val_random = load atomic i16* %ptr_random unordered, align 2
+  %ptr_random = getelementptr i16, i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
+  %val_random = load atomic i16, i16* %ptr_random unordered, align 2
   %tot3 = add i16 %tot2, %val_random
 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: ldrh {{w[0-9]+}}, [x[[ADDR]]]
@@ -163,24 +175,24 @@ define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) {
   ret i16 %tot3
 }
 
-define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) {
+define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) #0 {
 ; CHECK-LABEL: atomic_load_relaxed_32:
-  %ptr_unsigned = getelementptr i32* %p, i32 4095
-  %val_unsigned = load atomic i32* %ptr_unsigned monotonic, align 4
+  %ptr_unsigned = getelementptr i32, i32* %p, i32 4095
+  %val_unsigned = load atomic i32, i32* %ptr_unsigned monotonic, align 4
 ; CHECK: ldr {{w[0-9]+}}, [x0, #16380]
 
-  %ptr_regoff = getelementptr i32* %p, i32 %off32
-  %val_regoff = load atomic i32* %ptr_regoff unordered, align 4
+  %ptr_regoff = getelementptr i32, i32* %p, i32 %off32
+  %val_regoff = load atomic i32, i32* %ptr_regoff unordered, align 4
   %tot1 = add i32 %val_unsigned, %val_regoff
 ; CHECK: ldr {{w[0-9]+}}, [x0, w1, sxtw #2]
 
-  %ptr_unscaled = getelementptr i32* %p, i32 -64
-  %val_unscaled = load atomic i32* %ptr_unscaled monotonic, align 4
+  %ptr_unscaled = getelementptr i32, i32* %p, i32 -64
+  %val_unscaled = load atomic i32, i32* %ptr_unscaled monotonic, align 4
   %tot2 = add i32 %tot1, %val_unscaled
 ; CHECK: ldur {{w[0-9]+}}, [x0, #-256]
 
-  %ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
-  %val_random = load atomic i32* %ptr_random unordered, align 4
+  %ptr_random = getelementptr i32, i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
+  %val_random = load atomic i32, i32* %ptr_random unordered, align 4
   %tot3 = add i32 %tot2, %val_random
 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: ldr {{w[0-9]+}}, [x[[ADDR]]]
@@ -188,24 +200,24 @@ define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) {
   ret i32 %tot3
 }
 
-define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) {
+define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) #0 {
 ; CHECK-LABEL: atomic_load_relaxed_64:
-  %ptr_unsigned = getelementptr i64* %p, i32 4095
-  %val_unsigned = load atomic i64* %ptr_unsigned monotonic, align 8
+  %ptr_unsigned = getelementptr i64, i64* %p, i32 4095
+  %val_unsigned = load atomic i64, i64* %ptr_unsigned monotonic, align 8
 ; CHECK: ldr {{x[0-9]+}}, [x0, #32760]
 
-  %ptr_regoff = getelementptr i64* %p, i32 %off32
-  %val_regoff = load atomic i64* %ptr_regoff unordered, align 8
+  %ptr_regoff = getelementptr i64, i64* %p, i32 %off32
+  %val_regoff = load atomic i64, i64* %ptr_regoff unordered, align 8
   %tot1 = add i64 %val_unsigned, %val_regoff
 ; CHECK: ldr {{x[0-9]+}}, [x0, w1, sxtw #3]
 
-  %ptr_unscaled = getelementptr i64* %p, i32 -32
-  %val_unscaled = load atomic i64* %ptr_unscaled monotonic, align 8
+  %ptr_unscaled = getelementptr i64, i64* %p, i32 -32
+  %val_unscaled = load atomic i64, i64* %ptr_unscaled monotonic, align 8
   %tot2 = add i64 %tot1, %val_unscaled
 ; CHECK: ldur {{x[0-9]+}}, [x0, #-256]
 
-  %ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
-  %val_random = load atomic i64* %ptr_random unordered, align 8
+  %ptr_random = getelementptr i64, i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
+  %val_random = load atomic i64, i64* %ptr_random unordered, align 8
   %tot3 = add i64 %tot2, %val_random
 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: ldr {{x[0-9]+}}, [x[[ADDR]]]
@@ -214,28 +226,28 @@ define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) {
 }
 
 
-define void @atomc_store(i32* %p) {
+define void @atomc_store(i32* %p) #0 {
    store atomic i32 4, i32* %p seq_cst, align 4
    ret void
    ; CHECK-LABEL: atomc_store:
    ; CHECK: stlr
 }
 
-define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) {
+define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) #0 {
 ; CHECK-LABEL: atomic_store_relaxed_8:
-  %ptr_unsigned = getelementptr i8* %p, i32 4095
+  %ptr_unsigned = getelementptr i8, i8* %p, i32 4095
   store atomic i8 %val, i8* %ptr_unsigned monotonic, align 1
 ; CHECK: strb {{w[0-9]+}}, [x0, #4095]
 
-  %ptr_regoff = getelementptr i8* %p, i32 %off32
+  %ptr_regoff = getelementptr i8, i8* %p, i32 %off32
   store atomic i8 %val, i8* %ptr_regoff unordered, align 1
 ; CHECK: strb {{w[0-9]+}}, [x0, w1, sxtw]
 
-  %ptr_unscaled = getelementptr i8* %p, i32 -256
+  %ptr_unscaled = getelementptr i8, i8* %p, i32 -256
   store atomic i8 %val, i8* %ptr_unscaled monotonic, align 1
 ; CHECK: sturb {{w[0-9]+}}, [x0, #-256]
 
-  %ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
+  %ptr_random = getelementptr i8, i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
   store atomic i8 %val, i8* %ptr_random unordered, align 1
 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: strb {{w[0-9]+}}, [x[[ADDR]]]
@@ -243,21 +255,21 @@ define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) {
   ret void
 }
 
-define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) {
+define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) #0 {
 ; CHECK-LABEL: atomic_store_relaxed_16:
-  %ptr_unsigned = getelementptr i16* %p, i32 4095
+  %ptr_unsigned = getelementptr i16, i16* %p, i32 4095
   store atomic i16 %val, i16* %ptr_unsigned monotonic, align 2
 ; CHECK: strh {{w[0-9]+}}, [x0, #8190]
 
-  %ptr_regoff = getelementptr i16* %p, i32 %off32
+  %ptr_regoff = getelementptr i16, i16* %p, i32 %off32
   store atomic i16 %val, i16* %ptr_regoff unordered, align 2
 ; CHECK: strh {{w[0-9]+}}, [x0, w1, sxtw #1]
 
-  %ptr_unscaled = getelementptr i16* %p, i32 -128
+  %ptr_unscaled = getelementptr i16, i16* %p, i32 -128
   store atomic i16 %val, i16* %ptr_unscaled monotonic, align 2
 ; CHECK: sturh {{w[0-9]+}}, [x0, #-256]
 
-  %ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
+  %ptr_random = getelementptr i16, i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
   store atomic i16 %val, i16* %ptr_random unordered, align 2
 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: strh {{w[0-9]+}}, [x[[ADDR]]]
@@ -265,21 +277,21 @@ define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) {
   ret void
 }
 
-define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) {
+define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) #0 {
 ; CHECK-LABEL: atomic_store_relaxed_32:
-  %ptr_unsigned = getelementptr i32* %p, i32 4095
+  %ptr_unsigned = getelementptr i32, i32* %p, i32 4095
   store atomic i32 %val, i32* %ptr_unsigned monotonic, align 4
 ; CHECK: str {{w[0-9]+}}, [x0, #16380]
 
-  %ptr_regoff = getelementptr i32* %p, i32 %off32
+  %ptr_regoff = getelementptr i32, i32* %p, i32 %off32
   store atomic i32 %val, i32* %ptr_regoff unordered, align 4
 ; CHECK: str {{w[0-9]+}}, [x0, w1, sxtw #2]
 
-  %ptr_unscaled = getelementptr i32* %p, i32 -64
+  %ptr_unscaled = getelementptr i32, i32* %p, i32 -64
   store atomic i32 %val, i32* %ptr_unscaled monotonic, align 4
 ; CHECK: stur {{w[0-9]+}}, [x0, #-256]
 
-  %ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
+  %ptr_random = getelementptr i32, i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
   store atomic i32 %val, i32* %ptr_random unordered, align 4
 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: str {{w[0-9]+}}, [x[[ADDR]]]
@@ -287,21 +299,21 @@ define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) {
   ret void
 }
 
-define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) {
+define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) #0 {
 ; CHECK-LABEL: atomic_store_relaxed_64:
-  %ptr_unsigned = getelementptr i64* %p, i32 4095
+  %ptr_unsigned = getelementptr i64, i64* %p, i32 4095
   store atomic i64 %val, i64* %ptr_unsigned monotonic, align 8
 ; CHECK: str {{x[0-9]+}}, [x0, #32760]
 
-  %ptr_regoff = getelementptr i64* %p, i32 %off32
+  %ptr_regoff = getelementptr i64, i64* %p, i32 %off32
   store atomic i64 %val, i64* %ptr_regoff unordered, align 8
 ; CHECK: str {{x[0-9]+}}, [x0, w1, sxtw #3]
 
-  %ptr_unscaled = getelementptr i64* %p, i32 -32
+  %ptr_unscaled = getelementptr i64, i64* %p, i32 -32
   store atomic i64 %val, i64* %ptr_unscaled monotonic, align 8
 ; CHECK: stur {{x[0-9]+}}, [x0, #-256]
 
-  %ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
+  %ptr_random = getelementptr i64, i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
   store atomic i64 %val, i64* %ptr_random unordered, align 8
 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: str {{x[0-9]+}}, [x[[ADDR]]]
@@ -319,13 +331,13 @@ define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) {
 
 define i32 @next_id() nounwind optsize ssp align 2 {
 entry:
-  %0 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
+  %0 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic", %"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
   %add.i = add i32 %0, 1
   %tobool = icmp eq i32 %add.i, 0
   br i1 %tobool, label %if.else, label %return
 
 if.else:                                          ; preds = %entry
-  %1 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
+  %1 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic", %"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
   %add.i2 = add i32 %1, 1
   br label %return
 
@@ -333,3 +345,5 @@ return:                                           ; preds = %if.else, %entry
   %retval.0 = phi i32 [ %add.i2, %if.else ], [ %add.i, %entry ]
   ret i32 %retval.0
 }
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/AArch64/arm64-basic-pic.ll b/test/CodeGen/AArch64/arm64-basic-pic.ll
index 9fdb1e91385b..e11274e45ff1 100644
--- a/test/CodeGen/AArch64/arm64-basic-pic.ll
+++ b/test/CodeGen/AArch64/arm64-basic-pic.ll
@@ -5,7 +5,7 @@
 define i32 @get_globalvar() {
 ; CHECK-LABEL: get_globalvar:
 
-  %val = load i32* @var
+  %val = load i32, i32* @var
 ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
 ; CHECK: ldr x[[GOTLOC:[0-9]+]], [x[[GOTHI]], :got_lo12:var]
 ; CHECK: ldr w0, [x[[GOTLOC]]]
@@ -16,7 +16,7 @@ define i32 @get_globalvar() {
 define i32* @get_globalvaraddr() {
 ; CHECK-LABEL: get_globalvaraddr:
 
-  %val = load i32* @var
+  %val = load i32, i32* @var
 ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
 ; CHECK: ldr x0, [x[[GOTHI]], :got_lo12:var]
 
@@ -28,7 +28,7 @@ define i32* @get_globalvaraddr() {
 define i32 @get_hiddenvar() {
 ; CHECK-LABEL: get_hiddenvar:
 
-  %val = load i32* @hiddenvar
+  %val = load i32, i32* @hiddenvar
 ; CHECK: adrp x[[HI:[0-9]+]], hiddenvar
 ; CHECK: ldr w0, [x[[HI]], :lo12:hiddenvar]
 
@@ -38,7 +38,7 @@ define i32 @get_hiddenvar() {
 define i32* @get_hiddenvaraddr() {
 ; CHECK-LABEL: get_hiddenvaraddr:
 
-  %val = load i32* @hiddenvar
+  %val = load i32, i32* @hiddenvar
 ; CHECK: adrp [[HI:x[0-9]+]], hiddenvar
 ; CHECK: add x0, [[HI]], :lo12:hiddenvar
 
diff --git a/test/CodeGen/AArch64/arm64-bcc.ll b/test/CodeGen/AArch64/arm64-bcc.ll
index 138ae9036092..66d2f52ab969 100644
--- a/test/CodeGen/AArch64/arm64-bcc.ll
+++ b/test/CodeGen/AArch64/arm64-bcc.ll
@@ -27,10 +27,10 @@ entry:
 define { i64, i1 } @foo(i64* , %Sstruct* , i1, i64) {
 entry:
   %.sroa.0 = alloca i72, align 16
-  %.count.value = getelementptr inbounds %Sstruct* %1, i64 0, i32 0, i32 0
-  %4 = load i64* %.count.value, align 8
-  %.repeatedValue.value = getelementptr inbounds %Sstruct* %1, i64 0, i32 1, i32 0
-  %5 = load i32* %.repeatedValue.value, align 8
+  %.count.value = getelementptr inbounds %Sstruct, %Sstruct* %1, i64 0, i32 0, i32 0
+  %4 = load i64, i64* %.count.value, align 8
+  %.repeatedValue.value = getelementptr inbounds %Sstruct, %Sstruct* %1, i64 0, i32 1, i32 0
+  %5 = load i32, i32* %.repeatedValue.value, align 8
   %6 = icmp eq i64 %4, 0
   br label %7
 
diff --git a/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll b/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
index d2985f4dd66a..876a69193b47 100644
--- a/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
+++ b/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
@@ -5,7 +5,7 @@
 define void @test_i64_f64(double* %p, i64* %q) {
 ; CHECK: ldr
 ; CHECK: str
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = bitcast double %2 to i64
     %4 = add i64 %3, %3
@@ -17,7 +17,7 @@ define void @test_i64_f64(double* %p, i64* %q) {
 define void @test_i64_v1i64(<1 x i64>* %p, i64* %q) {
 ; CHECK: ldr
 ; CHECK: str
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = bitcast <1 x i64> %2 to i64
     %4 = add i64 %3, %3
@@ -30,7 +30,7 @@ define void @test_i64_v2f32(<2 x float>* %p, i64* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2s }
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: str
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = bitcast <2 x float> %2 to i64
     %4 = add i64 %3, %3
@@ -43,7 +43,7 @@ define void @test_i64_v2i32(<2 x i32>* %p, i64* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2s }
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: str
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = bitcast <2 x i32> %2 to i64
     %4 = add i64 %3, %3
@@ -56,7 +56,7 @@ define void @test_i64_v4i16(<4 x i16>* %p, i64* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.4h }
 ; CHECK: rev64 v{{[0-9]+}}.4h
 ; CHECK: str
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = bitcast <4 x i16> %2 to i64
     %4 = add i64 %3, %3
@@ -69,7 +69,7 @@ define void @test_i64_v8i8(<8 x i8>* %p, i64* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.8b }
 ; CHECK: rev64 v{{[0-9]+}}.8b
 ; CHECK: str
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = bitcast <8 x i8> %2 to i64
     %4 = add i64 %3, %3
@@ -81,7 +81,7 @@ define void @test_i64_v8i8(<8 x i8>* %p, i64* %q) {
 define void @test_f64_i64(i64* %p, double* %q) {
 ; CHECK: ldr
 ; CHECK: str
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = bitcast i64 %2 to double
     %4 = fadd double %3, %3
@@ -93,7 +93,7 @@ define void @test_f64_i64(i64* %p, double* %q) {
 define void @test_f64_v1i64(<1 x i64>* %p, double* %q) {
 ; CHECK: ldr
 ; CHECK: str
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = bitcast <1 x i64> %2 to double
     %4 = fadd double %3, %3
@@ -106,7 +106,7 @@ define void @test_f64_v2f32(<2 x float>* %p, double* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2s }
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: str
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = bitcast <2 x float> %2 to double
     %4 = fadd double %3, %3
@@ -119,7 +119,7 @@ define void @test_f64_v2i32(<2 x i32>* %p, double* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2s }
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: str
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = bitcast <2 x i32> %2 to double
     %4 = fadd double %3, %3
@@ -132,7 +132,7 @@ define void @test_f64_v4i16(<4 x i16>* %p, double* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.4h }
 ; CHECK: rev64 v{{[0-9]+}}.4h
 ; CHECK: str
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = bitcast <4 x i16> %2 to double
     %4 = fadd double %3, %3
@@ -145,7 +145,7 @@ define void @test_f64_v8i8(<8 x i8>* %p, double* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.8b }
 ; CHECK: rev64 v{{[0-9]+}}.8b
 ; CHECK: str
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = bitcast <8 x i8> %2 to double
     %4 = fadd double %3, %3
@@ -157,7 +157,7 @@ define void @test_f64_v8i8(<8 x i8>* %p, double* %q) {
 define void @test_v1i64_i64(i64* %p, <1 x i64>* %q) {
 ; CHECK: ldr
 ; CHECK: str
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = bitcast i64 %2 to <1 x i64>
     %4 = add <1 x i64> %3, %3
@@ -169,7 +169,7 @@ define void @test_v1i64_i64(i64* %p, <1 x i64>* %q) {
 define void @test_v1i64_f64(double* %p, <1 x i64>* %q) {
 ; CHECK: ldr
 ; CHECK: str
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = bitcast double %2 to <1 x i64>
     %4 = add <1 x i64> %3, %3
@@ -182,7 +182,7 @@ define void @test_v1i64_v2f32(<2 x float>* %p, <1 x i64>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2s }
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: str
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = bitcast <2 x float> %2 to <1 x i64>
     %4 = add <1 x i64> %3, %3
@@ -195,7 +195,7 @@ define void @test_v1i64_v2i32(<2 x i32>* %p, <1 x i64>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2s }
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: str
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = bitcast <2 x i32> %2 to <1 x i64>
     %4 = add <1 x i64> %3, %3
@@ -208,7 +208,7 @@ define void @test_v1i64_v4i16(<4 x i16>* %p, <1 x i64>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.4h }
 ; CHECK: rev64 v{{[0-9]+}}.4h
 ; CHECK: str
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = bitcast <4 x i16> %2 to <1 x i64>
     %4 = add <1 x i64> %3, %3
@@ -221,7 +221,7 @@ define void @test_v1i64_v8i8(<8 x i8>* %p, <1 x i64>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.8b }
 ; CHECK: rev64 v{{[0-9]+}}.8b
 ; CHECK: str
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = bitcast <8 x i8> %2 to <1 x i64>
     %4 = add <1 x i64> %3, %3
@@ -234,7 +234,7 @@ define void @test_v2f32_i64(i64* %p, <2 x float>* %q) {
 ; CHECK: ldr
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: st1 { v{{[0-9]+}}.2s }
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = bitcast i64 %2 to <2 x float>
     %4 = fadd <2 x float> %3, %3
@@ -247,7 +247,7 @@ define void @test_v2f32_f64(double* %p, <2 x float>* %q) {
 ; CHECK: ldr
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: st1 { v{{[0-9]+}}.2s }
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = bitcast double %2 to <2 x float>
     %4 = fadd <2 x float> %3, %3
@@ -260,7 +260,7 @@ define void @test_v2f32_v1i64(<1 x i64>* %p, <2 x float>* %q) {
 ; CHECK: ldr
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: st1 { v{{[0-9]+}}.2s }
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = bitcast <1 x i64> %2 to <2 x float>
     %4 = fadd <2 x float> %3, %3
@@ -272,7 +272,7 @@ define void @test_v2f32_v1i64(<1 x i64>* %p, <2 x float>* %q) {
 define void @test_v2f32_v2i32(<2 x i32>* %p, <2 x float>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2s }
 ; CHECK: st1 { v{{[0-9]+}}.2s }
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = bitcast <2 x i32> %2 to <2 x float>
     %4 = fadd <2 x float> %3, %3
@@ -285,7 +285,7 @@ define void @test_v2f32_v4i16(<4 x i16>* %p, <2 x float>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.4h }
 ; CHECK: rev32 v{{[0-9]+}}.4h
 ; CHECK: st1 { v{{[0-9]+}}.2s }
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = bitcast <4 x i16> %2 to <2 x float>
     %4 = fadd <2 x float> %3, %3
@@ -298,7 +298,7 @@ define void @test_v2f32_v8i8(<8 x i8>* %p, <2 x float>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.8b }
 ; CHECK: rev32 v{{[0-9]+}}.8b
 ; CHECK: st1 { v{{[0-9]+}}.2s }
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = bitcast <8 x i8> %2 to <2 x float>
     %4 = fadd <2 x float> %3, %3
@@ -311,7 +311,7 @@ define void @test_v2i32_i64(i64* %p, <2 x i32>* %q) {
 ; CHECK: ldr
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: st1 { v{{[0-9]+}}.2s }
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = bitcast i64 %2 to <2 x i32>
     %4 = add <2 x i32> %3, %3
@@ -324,7 +324,7 @@ define void @test_v2i32_f64(double* %p, <2 x i32>* %q) {
 ; CHECK: ldr
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: st1 { v{{[0-9]+}}.2s }
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = bitcast double %2 to <2 x i32>
     %4 = add <2 x i32> %3, %3
@@ -337,7 +337,7 @@ define void @test_v2i32_v1i64(<1 x i64>* %p, <2 x i32>* %q) {
 ; CHECK: ldr
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: st1 { v{{[0-9]+}}.2s }
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = bitcast <1 x i64> %2 to <2 x i32>
     %4 = add <2 x i32> %3, %3
@@ -349,7 +349,7 @@ define void @test_v2i32_v1i64(<1 x i64>* %p, <2 x i32>* %q) {
 define void @test_v2i32_v2f32(<2 x float>* %p, <2 x i32>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2s }
 ; CHECK: st1 { v{{[0-9]+}}.2s }
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = bitcast <2 x float> %2 to <2 x i32>
     %4 = add <2 x i32> %3, %3
@@ -362,7 +362,7 @@ define void @test_v2i32_v4i16(<4 x i16>* %p, <2 x i32>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.4h }
 ; CHECK: rev32 v{{[0-9]+}}.4h
 ; CHECK: st1 { v{{[0-9]+}}.2s }
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = bitcast <4 x i16> %2 to <2 x i32>
     %4 = add <2 x i32> %3, %3
@@ -375,7 +375,7 @@ define void @test_v2i32_v8i8(<8 x i8>* %p, <2 x i32>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.8b }
 ; CHECK: rev32 v{{[0-9]+}}.8b
 ; CHECK: st1 { v{{[0-9]+}}.2s }
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = bitcast <8 x i8> %2 to <2 x i32>
     %4 = add <2 x i32> %3, %3
@@ -388,7 +388,7 @@ define void @test_v4i16_i64(i64* %p, <4 x i16>* %q) {
 ; CHECK: ldr
 ; CHECK: rev64 v{{[0-9]+}}.4h
 ; CHECK: st1 { v{{[0-9]+}}.4h }
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = bitcast i64 %2 to <4 x i16>
     %4 = add <4 x i16> %3, %3
@@ -401,7 +401,7 @@ define void @test_v4i16_f64(double* %p, <4 x i16>* %q) {
 ; CHECK: ldr
 ; CHECK: rev64 v{{[0-9]+}}.4h
 ; CHECK: st1 { v{{[0-9]+}}.4h }
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = bitcast double %2 to <4 x i16>
     %4 = add <4 x i16> %3, %3
@@ -414,7 +414,7 @@ define void @test_v4i16_v1i64(<1 x i64>* %p, <4 x i16>* %q) {
 ; CHECK: ldr
 ; CHECK: rev64 v{{[0-9]+}}.4h
 ; CHECK: st1 { v{{[0-9]+}}.4h }
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = bitcast <1 x i64> %2 to <4 x i16>
     %4 = add <4 x i16> %3, %3
@@ -427,7 +427,7 @@ define void @test_v4i16_v2f32(<2 x float>* %p, <4 x i16>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2s }
 ; CHECK: rev32 v{{[0-9]+}}.4h
 ; CHECK: st1 { v{{[0-9]+}}.4h }
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = bitcast <2 x float> %2 to <4 x i16>
     %4 = add <4 x i16> %3, %3
@@ -440,7 +440,7 @@ define void @test_v4i16_v2i32(<2 x i32>* %p, <4 x i16>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2s }
 ; CHECK: rev32 v{{[0-9]+}}.4h
 ; CHECK: st1 { v{{[0-9]+}}.4h }
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = bitcast <2 x i32> %2 to <4 x i16>
     %4 = add <4 x i16> %3, %3
@@ -453,7 +453,7 @@ define void @test_v4i16_v8i8(<8 x i8>* %p, <4 x i16>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.8b }
 ; CHECK: rev16 v{{[0-9]+}}.8b
 ; CHECK: st1 { v{{[0-9]+}}.4h }
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = bitcast <8 x i8> %2 to <4 x i16>
     %4 = add <4 x i16> %3, %3
@@ -466,7 +466,7 @@ define void @test_v8i8_i64(i64* %p, <8 x i8>* %q) {
 ; CHECK: ldr
 ; CHECK: rev64 v{{[0-9]+}}.8b
 ; CHECK: st1 { v{{[0-9]+}}.8b }
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = bitcast i64 %2 to <8 x i8>
     %4 = add <8 x i8> %3, %3
@@ -479,7 +479,7 @@ define void @test_v8i8_f64(double* %p, <8 x i8>* %q) {
 ; CHECK: ldr
 ; CHECK: rev64 v{{[0-9]+}}.8b
 ; CHECK: st1 { v{{[0-9]+}}.8b }
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = bitcast double %2 to <8 x i8>
     %4 = add <8 x i8> %3, %3
@@ -492,7 +492,7 @@ define void @test_v8i8_v1i64(<1 x i64>* %p, <8 x i8>* %q) {
 ; CHECK: ldr
 ; CHECK: rev64 v{{[0-9]+}}.8b
 ; CHECK: st1 { v{{[0-9]+}}.8b }
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = bitcast <1 x i64> %2 to <8 x i8>
     %4 = add <8 x i8> %3, %3
@@ -505,7 +505,7 @@ define void @test_v8i8_v2f32(<2 x float>* %p, <8 x i8>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2s }
 ; CHECK: rev32 v{{[0-9]+}}.8b
 ; CHECK: st1 { v{{[0-9]+}}.8b }
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = bitcast <2 x float> %2 to <8 x i8>
     %4 = add <8 x i8> %3, %3
@@ -518,7 +518,7 @@ define void @test_v8i8_v2i32(<2 x i32>* %p, <8 x i8>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2s }
 ; CHECK: rev32 v{{[0-9]+}}.8b
 ; CHECK: st1 { v{{[0-9]+}}.8b }
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = bitcast <2 x i32> %2 to <8 x i8>
     %4 = add <8 x i8> %3, %3
@@ -531,7 +531,7 @@ define void @test_v8i8_v4i16(<4 x i16>* %p, <8 x i8>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.4h }
 ; CHECK: rev16 v{{[0-9]+}}.8b
 ; CHECK: st1 { v{{[0-9]+}}.8b }
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = bitcast <4 x i16> %2 to <8 x i8>
     %4 = add <8 x i8> %3, %3
@@ -544,7 +544,7 @@ define void @test_f128_v2f64(<2 x double>* %p, fp128* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2d }
 ; CHECK: ext
 ; CHECK: str
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = bitcast <2 x double> %2 to fp128
     %4 = fadd fp128 %3, %3
@@ -557,7 +557,7 @@ define void @test_f128_v2i64(<2 x i64>* %p, fp128* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2d }
 ; CHECK: ext
 ; CHECK: str
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = bitcast <2 x i64> %2 to fp128
     %4 = fadd fp128 %3, %3
@@ -572,7 +572,7 @@ define void @test_f128_v4f32(<4 x float>* %p, fp128* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
 ; CHECK: str q
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = bitcast <4 x float> %2 to fp128
     %4 = fadd fp128 %3, %3
@@ -586,7 +586,7 @@ define void @test_f128_v4i32(<4 x i32>* %p, fp128* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
 ; CHECK: str
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = bitcast <4 x i32> %2 to fp128
     %4 = fadd fp128 %3, %3
@@ -600,7 +600,7 @@ define void @test_f128_v8i16(<8 x i16>* %p, fp128* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.8h
 ; CHECK: ext
 ; CHECK: str
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = bitcast <8 x i16> %2 to fp128
     %4 = fadd fp128 %3, %3
@@ -613,7 +613,7 @@ define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.16b }
 ; CHECK: ext
 ; CHECK: str q
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = bitcast <16 x i8> %2 to fp128
     %4 = fadd fp128 %3, %3
@@ -626,7 +626,7 @@ define void @test_v2f64_f128(fp128* %p, <2 x double>* %q) {
 ; CHECK: ldr
 ; CHECK: ext
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = bitcast fp128 %2 to <2 x double>
     %4 = fadd <2 x double> %3, %3
@@ -638,7 +638,7 @@ define void @test_v2f64_f128(fp128* %p, <2 x double>* %q) {
 define void @test_v2f64_v2i64(<2 x i64>* %p, <2 x double>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2d }
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = bitcast <2 x i64> %2 to <2 x double>
     %4 = fadd <2 x double> %3, %3
@@ -652,7 +652,7 @@ define void @test_v2f64_v4f32(<4 x float>* %p, <2 x double>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = bitcast <4 x float> %2 to <2 x double>
     %4 = fadd <2 x double> %3, %3
@@ -665,7 +665,7 @@ define void @test_v2f64_v4i32(<4 x i32>* %p, <2 x double>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.4s }
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = bitcast <4 x i32> %2 to <2 x double>
     %4 = fadd <2 x double> %3, %3
@@ -678,7 +678,7 @@ define void @test_v2f64_v8i16(<8 x i16>* %p, <2 x double>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.8h }
 ; CHECK: rev64 v{{[0-9]+}}.8h
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = bitcast <8 x i16> %2 to <2 x double>
     %4 = fadd <2 x double> %3, %3
@@ -691,7 +691,7 @@ define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.16b }
 ; CHECK: rev64 v{{[0-9]+}}.16b
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = bitcast <16 x i8> %2 to <2 x double>
     %4 = fadd <2 x double> %3, %3
@@ -704,7 +704,7 @@ define void @test_v2i64_f128(fp128* %p, <2 x i64>* %q) {
 ; CHECK: ldr
 ; CHECK: ext
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = bitcast fp128 %2 to <2 x i64>
     %4 = add <2 x i64> %3, %3
@@ -716,7 +716,7 @@ define void @test_v2i64_f128(fp128* %p, <2 x i64>* %q) {
 define void @test_v2i64_v2f64(<2 x double>* %p, <2 x i64>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2d }
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = bitcast <2 x double> %2 to <2 x i64>
     %4 = add <2 x i64> %3, %3
@@ -730,7 +730,7 @@ define void @test_v2i64_v4f32(<4 x float>* %p, <2 x i64>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = bitcast <4 x float> %2 to <2 x i64>
     %4 = add <2 x i64> %3, %3
@@ -743,7 +743,7 @@ define void @test_v2i64_v4i32(<4 x i32>* %p, <2 x i64>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.4s }
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = bitcast <4 x i32> %2 to <2 x i64>
     %4 = add <2 x i64> %3, %3
@@ -756,7 +756,7 @@ define void @test_v2i64_v8i16(<8 x i16>* %p, <2 x i64>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.8h }
 ; CHECK: rev64 v{{[0-9]+}}.8h
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = bitcast <8 x i16> %2 to <2 x i64>
     %4 = add <2 x i64> %3, %3
@@ -769,7 +769,7 @@ define void @test_v2i64_v16i8(<16 x i8>* %p, <2 x i64>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.16b }
 ; CHECK: rev64 v{{[0-9]+}}.16b
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = bitcast <16 x i8> %2 to <2 x i64>
     %4 = add <2 x i64> %3, %3
@@ -784,7 +784,7 @@ define void @test_v4f32_f128(fp128* %p, <4 x float>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = bitcast fp128 %2 to <4 x float>
     %4 = fadd <4 x float> %3, %3
@@ -798,7 +798,7 @@ define void @test_v4f32_v2f64(<2 x double>* %p, <4 x float>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = bitcast <2 x double> %2 to <4 x float>
     %4 = fadd <4 x float> %3, %3
@@ -812,7 +812,7 @@ define void @test_v4f32_v2i64(<2 x i64>* %p, <4 x float>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = bitcast <2 x i64> %2 to <4 x float>
     %4 = fadd <4 x float> %3, %3
@@ -825,7 +825,7 @@ define void @test_v4f32_v4i32(<4 x i32>* %p, <4 x float>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.4s }
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = bitcast <4 x i32> %2 to <4 x float>
     %4 = fadd <4 x float> %3, %3
@@ -839,7 +839,7 @@ define void @test_v4f32_v8i16(<8 x i16>* %p, <4 x float>* %q) {
 ; CHECK: rev32 v{{[0-9]+}}.8h
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = bitcast <8 x i16> %2 to <4 x float>
     %4 = fadd <4 x float> %3, %3
@@ -853,7 +853,7 @@ define void @test_v4f32_v16i8(<16 x i8>* %p, <4 x float>* %q) {
 ; CHECK: rev32 v{{[0-9]+}}.16b
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: st1 { v{{[0-9]+}}.2d }
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = bitcast <16 x i8> %2 to <4 x float>
     %4 = fadd <4 x float> %3, %3
@@ -867,7 +867,7 @@ define void @test_v4i32_f128(fp128* %p, <4 x i32>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
 ; CHECK: st1 { v{{[0-9]+}}.4s }
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = bitcast fp128 %2 to <4 x i32>
     %4 = add <4 x i32> %3, %3
@@ -880,7 +880,7 @@ define void @test_v4i32_v2f64(<2 x double>* %p, <4 x i32>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2d }
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: st1 { v{{[0-9]+}}.4s }
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = bitcast <2 x double> %2 to <4 x i32>
     %4 = add <4 x i32> %3, %3
@@ -893,7 +893,7 @@ define void @test_v4i32_v2i64(<2 x i64>* %p, <4 x i32>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2d }
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: st1 { v{{[0-9]+}}.4s }
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = bitcast <2 x i64> %2 to <4 x i32>
     %4 = add <4 x i32> %3, %3
@@ -906,7 +906,7 @@ define void @test_v4i32_v4f32(<4 x float>* %p, <4 x i32>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2d }
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: st1 { v{{[0-9]+}}.4s }
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = bitcast <4 x float> %2 to <4 x i32>
     %4 = add <4 x i32> %3, %3
@@ -919,7 +919,7 @@ define void @test_v4i32_v8i16(<8 x i16>* %p, <4 x i32>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.8h }
 ; CHECK: rev32 v{{[0-9]+}}.8h
 ; CHECK: st1 { v{{[0-9]+}}.4s }
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = bitcast <8 x i16> %2 to <4 x i32>
     %4 = add <4 x i32> %3, %3
@@ -932,7 +932,7 @@ define void @test_v4i32_v16i8(<16 x i8>* %p, <4 x i32>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.16b }
 ; CHECK: rev32 v{{[0-9]+}}.16b
 ; CHECK: st1 { v{{[0-9]+}}.4s }
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = bitcast <16 x i8> %2 to <4 x i32>
     %4 = add <4 x i32> %3, %3
@@ -946,7 +946,7 @@ define void @test_v8i16_f128(fp128* %p, <8 x i16>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.8h
 ; CHECK: ext
 ; CHECK: st1 { v{{[0-9]+}}.8h }
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = bitcast fp128 %2 to <8 x i16>
     %4 = add <8 x i16> %3, %3
@@ -959,7 +959,7 @@ define void @test_v8i16_v2f64(<2 x double>* %p, <8 x i16>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2d }
 ; CHECK: rev64 v{{[0-9]+}}.8h
 ; CHECK: st1 { v{{[0-9]+}}.8h }
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = bitcast <2 x double> %2 to <8 x i16>
     %4 = add <8 x i16> %3, %3
@@ -972,7 +972,7 @@ define void @test_v8i16_v2i64(<2 x i64>* %p, <8 x i16>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2d }
 ; CHECK: rev64 v{{[0-9]+}}.8h
 ; CHECK: st1 { v{{[0-9]+}}.8h }
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = bitcast <2 x i64> %2 to <8 x i16>
     %4 = add <8 x i16> %3, %3
@@ -986,7 +986,7 @@ define void @test_v8i16_v4f32(<4 x float>* %p, <8 x i16>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: rev32 v{{[0-9]+}}.8h
 ; CHECK: st1 { v{{[0-9]+}}.8h }
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = bitcast <4 x float> %2 to <8 x i16>
     %4 = add <8 x i16> %3, %3
@@ -999,7 +999,7 @@ define void @test_v8i16_v4i32(<4 x i32>* %p, <8 x i16>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.4s }
 ; CHECK: rev32 v{{[0-9]+}}.8h
 ; CHECK: st1 { v{{[0-9]+}}.8h }
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = bitcast <4 x i32> %2 to <8 x i16>
     %4 = add <8 x i16> %3, %3
@@ -1012,7 +1012,7 @@ define void @test_v8i16_v16i8(<16 x i8>* %p, <8 x i16>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.16b }
 ; CHECK: rev16 v{{[0-9]+}}.16b
 ; CHECK: st1 { v{{[0-9]+}}.8h }
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = bitcast <16 x i8> %2 to <8 x i16>
     %4 = add <8 x i16> %3, %3
@@ -1026,7 +1026,7 @@ define void @test_v16i8_f128(fp128* %p, <16 x i8>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.16b
 ; CHECK: ext
 ; CHECK: st1 { v{{[0-9]+}}.16b }
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = bitcast fp128 %2 to <16 x i8>
     %4 = add <16 x i8> %3, %3
@@ -1039,7 +1039,7 @@ define void @test_v16i8_v2f64(<2 x double>* %p, <16 x i8>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2d }
 ; CHECK: rev64 v{{[0-9]+}}.16b
 ; CHECK: st1 { v{{[0-9]+}}.16b }
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = bitcast <2 x double> %2 to <16 x i8>
     %4 = add <16 x i8> %3, %3
@@ -1052,7 +1052,7 @@ define void @test_v16i8_v2i64(<2 x i64>* %p, <16 x i8>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.2d }
 ; CHECK: rev64 v{{[0-9]+}}.16b
 ; CHECK: st1 { v{{[0-9]+}}.16b }
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = bitcast <2 x i64> %2 to <16 x i8>
     %4 = add <16 x i8> %3, %3
@@ -1066,7 +1066,7 @@ define void @test_v16i8_v4f32(<4 x float>* %p, <16 x i8>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: rev32 v{{[0-9]+}}.16b
 ; CHECK: st1 { v{{[0-9]+}}.16b }
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = bitcast <4 x float> %2 to <16 x i8>
     %4 = add <16 x i8> %3, %3
@@ -1079,7 +1079,7 @@ define void @test_v16i8_v4i32(<4 x i32>* %p, <16 x i8>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.4s }
 ; CHECK: rev32 v{{[0-9]+}}.16b
 ; CHECK: st1 { v{{[0-9]+}}.16b }
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = bitcast <4 x i32> %2 to <16 x i8>
     %4 = add <16 x i8> %3, %3
@@ -1092,7 +1092,7 @@ define void @test_v16i8_v8i16(<8 x i16>* %p, <16 x i8>* %q) {
 ; CHECK: ld1 { v{{[0-9]+}}.8h }
 ; CHECK: rev16 v{{[0-9]+}}.16b
 ; CHECK: st1 { v{{[0-9]+}}.16b }
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = bitcast <8 x i16> %2 to <16 x i8>
     %4 = add <16 x i8> %3, %3
diff --git a/test/CodeGen/AArch64/arm64-big-endian-varargs.ll b/test/CodeGen/AArch64/arm64-big-endian-varargs.ll
index db1f48c6fd5e..e5e16848a4b0 100644
--- a/test/CodeGen/AArch64/arm64-big-endian-varargs.ll
+++ b/test/CodeGen/AArch64/arm64-big-endian-varargs.ll
@@ -21,8 +21,8 @@ entry:
   %vl = alloca %struct.__va_list, align 8
   %vl1 = bitcast %struct.__va_list* %vl to i8*
   call void @llvm.va_start(i8* %vl1)
-  %vr_offs_p = getelementptr inbounds %struct.__va_list* %vl, i64 0, i32 4
-  %vr_offs = load i32* %vr_offs_p, align 4
+  %vr_offs_p = getelementptr inbounds %struct.__va_list, %struct.__va_list* %vl, i64 0, i32 4
+  %vr_offs = load i32, i32* %vr_offs_p, align 4
   %0 = icmp sgt i32 %vr_offs, -1
   br i1 %0, label %vaarg.on_stack, label %vaarg.maybe_reg
 
@@ -33,26 +33,26 @@ vaarg.maybe_reg:                                  ; preds = %entry
   br i1 %inreg, label %vaarg.in_reg, label %vaarg.on_stack
 
 vaarg.in_reg:                                     ; preds = %vaarg.maybe_reg
-  %reg_top_p = getelementptr inbounds %struct.__va_list* %vl, i64 0, i32 2
-  %reg_top = load i8** %reg_top_p, align 8
+  %reg_top_p = getelementptr inbounds %struct.__va_list, %struct.__va_list* %vl, i64 0, i32 2
+  %reg_top = load i8*, i8** %reg_top_p, align 8
   %1 = sext i32 %vr_offs to i64
-  %2 = getelementptr i8* %reg_top, i64 %1
+  %2 = getelementptr i8, i8* %reg_top, i64 %1
   %3 = ptrtoint i8* %2 to i64
   %align_be = add i64 %3, 8
   %4 = inttoptr i64 %align_be to i8*
   br label %vaarg.end
 
 vaarg.on_stack:                                   ; preds = %vaarg.maybe_reg, %entry
-  %stack_p = getelementptr inbounds %struct.__va_list* %vl, i64 0, i32 0
-  %stack = load i8** %stack_p, align 8
-  %new_stack = getelementptr i8* %stack, i64 8
+  %stack_p = getelementptr inbounds %struct.__va_list, %struct.__va_list* %vl, i64 0, i32 0
+  %stack = load i8*, i8** %stack_p, align 8
+  %new_stack = getelementptr i8, i8* %stack, i64 8
   store i8* %new_stack, i8** %stack_p, align 8
   br label %vaarg.end
 
 vaarg.end:                                        ; preds = %vaarg.on_stack, %vaarg.in_reg
   %.sink = phi i8* [ %4, %vaarg.in_reg ], [ %stack, %vaarg.on_stack ]
   %5 = bitcast i8* %.sink to double*
-  %6 = load double* %5, align 8
+  %6 = load double, double* %5, align 8
   call void @llvm.va_end(i8* %vl1)
   ret double %6
 }
diff --git a/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll b/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll
index d72d0a5db41e..d08976788e91 100644
--- a/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll
+++ b/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll
@@ -1,13 +1,19 @@
 ; RUN: llc -mtriple aarch64_be < %s -aarch64-load-store-opt=false -o - | FileCheck %s
 ; RUN: llc -mtriple aarch64_be < %s -aarch64-load-store-opt=false -fast-isel=true -O0 -o - | FileCheck %s
 
+; Note, we split the functions in to multiple BBs below to isolate the call
+; instruction we want to test, from fast-isel failing to select instructions
+; after it.
+
 ; CHECK-LABEL: test_i64_f64:
 declare i64 @test_i64_f64_helper(double %p)
 define void @test_i64_f64(double* %p, i64* %q) {
 ; CHECK-NOT: rev
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = call i64 @test_i64_f64_helper(double %2)
+    br label %return_bb
+return_bb:
     %4 = add i64 %3, %3
     store i64 %4, i64* %q
     ret void
@@ -17,9 +23,11 @@ define void @test_i64_f64(double* %p, i64* %q) {
 declare i64 @test_i64_v1i64_helper(<1 x i64> %p)
 define void @test_i64_v1i64(<1 x i64>* %p, i64* %q) {
 ; CHECK-NOT: rev
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = call i64 @test_i64_v1i64_helper(<1 x i64> %2)
+    br label %return_bb
+return_bb:
     %4 = add i64 %3, %3
     store i64 %4, i64* %q
     ret void
@@ -29,9 +37,11 @@ define void @test_i64_v1i64(<1 x i64>* %p, i64* %q) {
 declare i64 @test_i64_v2f32_helper(<2 x float> %p)
 define void @test_i64_v2f32(<2 x float>* %p, i64* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = call i64 @test_i64_v2f32_helper(<2 x float> %2)
+    br label %return_bb
+return_bb:
     %4 = add i64 %3, %3
     store i64 %4, i64* %q
     ret void
@@ -41,9 +51,11 @@ define void @test_i64_v2f32(<2 x float>* %p, i64* %q) {
 declare i64 @test_i64_v2i32_helper(<2 x i32> %p)
 define void @test_i64_v2i32(<2 x i32>* %p, i64* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = call i64 @test_i64_v2i32_helper(<2 x i32> %2)
+    br label %return_bb
+return_bb:
     %4 = add i64 %3, %3
     store i64 %4, i64* %q
     ret void
@@ -53,9 +65,11 @@ define void @test_i64_v2i32(<2 x i32>* %p, i64* %q) {
 declare i64 @test_i64_v4i16_helper(<4 x i16> %p)
 define void @test_i64_v4i16(<4 x i16>* %p, i64* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4h
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = call i64 @test_i64_v4i16_helper(<4 x i16> %2)
+    br label %return_bb
+return_bb:
     %4 = add i64 %3, %3
     store i64 %4, i64* %q
     ret void
@@ -65,9 +79,11 @@ define void @test_i64_v4i16(<4 x i16>* %p, i64* %q) {
 declare i64 @test_i64_v8i8_helper(<8 x i8> %p)
 define void @test_i64_v8i8(<8 x i8>* %p, i64* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.8b
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = call i64 @test_i64_v8i8_helper(<8 x i8> %2)
+    br label %return_bb
+return_bb:
     %4 = add i64 %3, %3
     store i64 %4, i64* %q
     ret void
@@ -77,9 +93,11 @@ define void @test_i64_v8i8(<8 x i8>* %p, i64* %q) {
 declare double @test_f64_i64_helper(i64 %p)
 define void @test_f64_i64(i64* %p, double* %q) {
 ; CHECK-NOT: rev
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = call double @test_f64_i64_helper(i64 %2)
+    br label %return_bb
+return_bb:
     %4 = fadd double %3, %3
     store double %4, double* %q
     ret void
@@ -89,9 +107,11 @@ define void @test_f64_i64(i64* %p, double* %q) {
 declare double @test_f64_v1i64_helper(<1 x i64> %p)
 define void @test_f64_v1i64(<1 x i64>* %p, double* %q) {
 ; CHECK-NOT: rev
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = call double @test_f64_v1i64_helper(<1 x i64> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd double %3, %3
     store double %4, double* %q
     ret void
@@ -101,9 +121,11 @@ define void @test_f64_v1i64(<1 x i64>* %p, double* %q) {
 declare double @test_f64_v2f32_helper(<2 x float> %p)
 define void @test_f64_v2f32(<2 x float>* %p, double* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = call double @test_f64_v2f32_helper(<2 x float> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd double %3, %3
     store double %4, double* %q
     ret void
@@ -113,9 +135,11 @@ define void @test_f64_v2f32(<2 x float>* %p, double* %q) {
 declare double @test_f64_v2i32_helper(<2 x i32> %p)
 define void @test_f64_v2i32(<2 x i32>* %p, double* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = call double @test_f64_v2i32_helper(<2 x i32> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd double %3, %3
     store double %4, double* %q
     ret void
@@ -125,9 +149,11 @@ define void @test_f64_v2i32(<2 x i32>* %p, double* %q) {
 declare double @test_f64_v4i16_helper(<4 x i16> %p)
 define void @test_f64_v4i16(<4 x i16>* %p, double* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4h
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = call double @test_f64_v4i16_helper(<4 x i16> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd double %3, %3
     store double %4, double* %q
     ret void
@@ -137,9 +163,11 @@ define void @test_f64_v4i16(<4 x i16>* %p, double* %q) {
 declare double @test_f64_v8i8_helper(<8 x i8> %p)
 define void @test_f64_v8i8(<8 x i8>* %p, double* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.8b
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = call double @test_f64_v8i8_helper(<8 x i8> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd double %3, %3
     store double %4, double* %q
     ret void
@@ -149,9 +177,11 @@ define void @test_f64_v8i8(<8 x i8>* %p, double* %q) {
 declare <1 x i64> @test_v1i64_i64_helper(i64 %p)
 define void @test_v1i64_i64(i64* %p, <1 x i64>* %q) {
 ; CHECK-NOT: rev
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = call <1 x i64> @test_v1i64_i64_helper(i64 %2)
+    br label %return_bb
+return_bb:
     %4 = add <1 x i64> %3, %3
     store <1 x i64> %4, <1 x i64>* %q
     ret void
@@ -161,9 +191,11 @@ define void @test_v1i64_i64(i64* %p, <1 x i64>* %q) {
 declare <1 x i64> @test_v1i64_f64_helper(double %p)
 define void @test_v1i64_f64(double* %p, <1 x i64>* %q) {
 ; CHECK-NOT: rev
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = call <1 x i64> @test_v1i64_f64_helper(double %2)
+    br label %return_bb
+return_bb:
     %4 = add <1 x i64> %3, %3
     store <1 x i64> %4, <1 x i64>* %q
     ret void
@@ -173,9 +205,11 @@ define void @test_v1i64_f64(double* %p, <1 x i64>* %q) {
 declare <1 x i64> @test_v1i64_v2f32_helper(<2 x float> %p)
 define void @test_v1i64_v2f32(<2 x float>* %p, <1 x i64>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = call <1 x i64> @test_v1i64_v2f32_helper(<2 x float> %2)
+    br label %return_bb
+return_bb:
     %4 = add <1 x i64> %3, %3
     store <1 x i64> %4, <1 x i64>* %q
     ret void
@@ -185,9 +219,11 @@ define void @test_v1i64_v2f32(<2 x float>* %p, <1 x i64>* %q) {
 declare <1 x i64> @test_v1i64_v2i32_helper(<2 x i32> %p)
 define void @test_v1i64_v2i32(<2 x i32>* %p, <1 x i64>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = call <1 x i64> @test_v1i64_v2i32_helper(<2 x i32> %2)
+    br label %return_bb
+return_bb:
     %4 = add <1 x i64> %3, %3
     store <1 x i64> %4, <1 x i64>* %q
     ret void
@@ -197,9 +233,11 @@ define void @test_v1i64_v2i32(<2 x i32>* %p, <1 x i64>* %q) {
 declare <1 x i64> @test_v1i64_v4i16_helper(<4 x i16> %p)
 define void @test_v1i64_v4i16(<4 x i16>* %p, <1 x i64>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4h
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = call <1 x i64> @test_v1i64_v4i16_helper(<4 x i16> %2)
+    br label %return_bb
+return_bb:
     %4 = add <1 x i64> %3, %3
     store <1 x i64> %4, <1 x i64>* %q
     ret void
@@ -209,9 +247,11 @@ define void @test_v1i64_v4i16(<4 x i16>* %p, <1 x i64>* %q) {
 declare <1 x i64> @test_v1i64_v8i8_helper(<8 x i8> %p)
 define void @test_v1i64_v8i8(<8 x i8>* %p, <1 x i64>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.8b
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = call <1 x i64> @test_v1i64_v8i8_helper(<8 x i8> %2)
+    br label %return_bb
+return_bb:
     %4 = add <1 x i64> %3, %3
     store <1 x i64> %4, <1 x i64>* %q
     ret void
@@ -221,9 +261,11 @@ define void @test_v1i64_v8i8(<8 x i8>* %p, <1 x i64>* %q) {
 declare <2 x float> @test_v2f32_i64_helper(i64 %p)
 define void @test_v2f32_i64(i64* %p, <2 x float>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = call <2 x float> @test_v2f32_i64_helper(i64 %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <2 x float> %3, %3
     store <2 x float> %4, <2 x float>* %q
     ret void
@@ -233,9 +275,11 @@ define void @test_v2f32_i64(i64* %p, <2 x float>* %q) {
 declare <2 x float> @test_v2f32_f64_helper(double %p)
 define void @test_v2f32_f64(double* %p, <2 x float>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = call <2 x float> @test_v2f32_f64_helper(double %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <2 x float> %3, %3
     store <2 x float> %4, <2 x float>* %q
     ret void
@@ -245,9 +289,11 @@ define void @test_v2f32_f64(double* %p, <2 x float>* %q) {
 declare <2 x float> @test_v2f32_v1i64_helper(<1 x i64> %p)
 define void @test_v2f32_v1i64(<1 x i64>* %p, <2 x float>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = call <2 x float> @test_v2f32_v1i64_helper(<1 x i64> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <2 x float> %3, %3
     store <2 x float> %4, <2 x float>* %q
     ret void
@@ -258,9 +304,11 @@ declare <2 x float> @test_v2f32_v2i32_helper(<2 x i32> %p)
 define void @test_v2f32_v2i32(<2 x i32>* %p, <2 x float>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = call <2 x float> @test_v2f32_v2i32_helper(<2 x i32> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <2 x float> %3, %3
     store <2 x float> %4, <2 x float>* %q
     ret void
@@ -271,9 +319,11 @@ declare <2 x float> @test_v2f32_v4i16_helper(<4 x i16> %p)
 define void @test_v2f32_v4i16(<4 x i16>* %p, <2 x float>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4h
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = call <2 x float> @test_v2f32_v4i16_helper(<4 x i16> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <2 x float> %3, %3
     store <2 x float> %4, <2 x float>* %q
     ret void
@@ -284,9 +334,11 @@ declare <2 x float> @test_v2f32_v8i8_helper(<8 x i8> %p)
 define void @test_v2f32_v8i8(<8 x i8>* %p, <2 x float>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.8b
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = call <2 x float> @test_v2f32_v8i8_helper(<8 x i8> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <2 x float> %3, %3
     store <2 x float> %4, <2 x float>* %q
     ret void
@@ -296,9 +348,11 @@ define void @test_v2f32_v8i8(<8 x i8>* %p, <2 x float>* %q) {
 declare <2 x i32> @test_v2i32_i64_helper(i64 %p)
 define void @test_v2i32_i64(i64* %p, <2 x i32>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = call <2 x i32> @test_v2i32_i64_helper(i64 %2)
+    br label %return_bb
+return_bb:
     %4 = add <2 x i32> %3, %3
     store <2 x i32> %4, <2 x i32>* %q
     ret void
@@ -308,9 +362,11 @@ define void @test_v2i32_i64(i64* %p, <2 x i32>* %q) {
 declare <2 x i32> @test_v2i32_f64_helper(double %p)
 define void @test_v2i32_f64(double* %p, <2 x i32>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = call <2 x i32> @test_v2i32_f64_helper(double %2)
+    br label %return_bb
+return_bb:
     %4 = add <2 x i32> %3, %3
     store <2 x i32> %4, <2 x i32>* %q
     ret void
@@ -320,9 +376,11 @@ define void @test_v2i32_f64(double* %p, <2 x i32>* %q) {
 declare <2 x i32> @test_v2i32_v1i64_helper(<1 x i64> %p)
 define void @test_v2i32_v1i64(<1 x i64>* %p, <2 x i32>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = call <2 x i32> @test_v2i32_v1i64_helper(<1 x i64> %2)
+    br label %return_bb
+return_bb:
     %4 = add <2 x i32> %3, %3
     store <2 x i32> %4, <2 x i32>* %q
     ret void
@@ -333,9 +391,11 @@ declare <2 x i32> @test_v2i32_v2f32_helper(<2 x float> %p)
 define void @test_v2i32_v2f32(<2 x float>* %p, <2 x i32>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = call <2 x i32> @test_v2i32_v2f32_helper(<2 x float> %2)
+    br label %return_bb
+return_bb:
     %4 = add <2 x i32> %3, %3
     store <2 x i32> %4, <2 x i32>* %q
     ret void
@@ -346,9 +406,11 @@ declare <2 x i32> @test_v2i32_v4i16_helper(<4 x i16> %p)
 define void @test_v2i32_v4i16(<4 x i16>* %p, <2 x i32>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4h
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = call <2 x i32> @test_v2i32_v4i16_helper(<4 x i16> %2)
+    br label %return_bb
+return_bb:
     %4 = add <2 x i32> %3, %3
     store <2 x i32> %4, <2 x i32>* %q
     ret void
@@ -359,9 +421,11 @@ declare <2 x i32> @test_v2i32_v8i8_helper(<8 x i8> %p)
 define void @test_v2i32_v8i8(<8 x i8>* %p, <2 x i32>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.8b
 ; CHECK: rev64 v{{[0-9]+}}.2s
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = call <2 x i32> @test_v2i32_v8i8_helper(<8 x i8> %2)
+    br label %return_bb
+return_bb:
     %4 = add <2 x i32> %3, %3
     store <2 x i32> %4, <2 x i32>* %q
     ret void
@@ -371,9 +435,11 @@ define void @test_v2i32_v8i8(<8 x i8>* %p, <2 x i32>* %q) {
 declare <4 x i16> @test_v4i16_i64_helper(i64 %p)
 define void @test_v4i16_i64(i64* %p, <4 x i16>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4h
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = call <4 x i16> @test_v4i16_i64_helper(i64 %2)
+    br label %return_bb
+return_bb:
     %4 = add <4 x i16> %3, %3
     store <4 x i16> %4, <4 x i16>* %q
     ret void
@@ -383,9 +449,11 @@ define void @test_v4i16_i64(i64* %p, <4 x i16>* %q) {
 declare <4 x i16> @test_v4i16_f64_helper(double %p)
 define void @test_v4i16_f64(double* %p, <4 x i16>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4h
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = call <4 x i16> @test_v4i16_f64_helper(double %2)
+    br label %return_bb
+return_bb:
     %4 = add <4 x i16> %3, %3
     store <4 x i16> %4, <4 x i16>* %q
     ret void
@@ -395,9 +463,11 @@ define void @test_v4i16_f64(double* %p, <4 x i16>* %q) {
 declare <4 x i16> @test_v4i16_v1i64_helper(<1 x i64> %p)
 define void @test_v4i16_v1i64(<1 x i64>* %p, <4 x i16>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4h
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = call <4 x i16> @test_v4i16_v1i64_helper(<1 x i64> %2)
+    br label %return_bb
+return_bb:
     %4 = add <4 x i16> %3, %3
     store <4 x i16> %4, <4 x i16>* %q
     ret void
@@ -408,9 +478,11 @@ declare <4 x i16> @test_v4i16_v2f32_helper(<2 x float> %p)
 define void @test_v4i16_v2f32(<2 x float>* %p, <4 x i16>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: rev64 v{{[0-9]+}}.4h
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = call <4 x i16> @test_v4i16_v2f32_helper(<2 x float> %2)
+    br label %return_bb
+return_bb:
     %4 = add <4 x i16> %3, %3
     store <4 x i16> %4, <4 x i16>* %q
     ret void
@@ -421,9 +493,11 @@ declare <4 x i16> @test_v4i16_v2i32_helper(<2 x i32> %p)
 define void @test_v4i16_v2i32(<2 x i32>* %p, <4 x i16>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: rev64 v{{[0-9]+}}.4h
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = call <4 x i16> @test_v4i16_v2i32_helper(<2 x i32> %2)
+    br label %return_bb
+return_bb:
     %4 = add <4 x i16> %3, %3
     store <4 x i16> %4, <4 x i16>* %q
     ret void
@@ -434,9 +508,11 @@ declare <4 x i16> @test_v4i16_v8i8_helper(<8 x i8> %p)
 define void @test_v4i16_v8i8(<8 x i8>* %p, <4 x i16>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.8b
 ; CHECK: rev64 v{{[0-9]+}}.4h
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = call <4 x i16> @test_v4i16_v8i8_helper(<8 x i8> %2)
+    br label %return_bb
+return_bb:
     %4 = add <4 x i16> %3, %3
     store <4 x i16> %4, <4 x i16>* %q
     ret void
@@ -446,9 +522,11 @@ define void @test_v4i16_v8i8(<8 x i8>* %p, <4 x i16>* %q) {
 declare <8 x i8> @test_v8i8_i64_helper(i64 %p)
 define void @test_v8i8_i64(i64* %p, <8 x i8>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.8b
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = call <8 x i8> @test_v8i8_i64_helper(i64 %2)
+    br label %return_bb
+return_bb:
     %4 = add <8 x i8> %3, %3
     store <8 x i8> %4, <8 x i8>* %q
     ret void
@@ -458,9 +536,11 @@ define void @test_v8i8_i64(i64* %p, <8 x i8>* %q) {
 declare <8 x i8> @test_v8i8_f64_helper(double %p)
 define void @test_v8i8_f64(double* %p, <8 x i8>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.8b
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = call <8 x i8> @test_v8i8_f64_helper(double %2)
+    br label %return_bb
+return_bb:
     %4 = add <8 x i8> %3, %3
     store <8 x i8> %4, <8 x i8>* %q
     ret void
@@ -470,9 +550,11 @@ define void @test_v8i8_f64(double* %p, <8 x i8>* %q) {
 declare <8 x i8> @test_v8i8_v1i64_helper(<1 x i64> %p)
 define void @test_v8i8_v1i64(<1 x i64>* %p, <8 x i8>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.8b
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = call <8 x i8> @test_v8i8_v1i64_helper(<1 x i64> %2)
+    br label %return_bb
+return_bb:
     %4 = add <8 x i8> %3, %3
     store <8 x i8> %4, <8 x i8>* %q
     ret void
@@ -483,9 +565,11 @@ declare <8 x i8> @test_v8i8_v2f32_helper(<2 x float> %p)
 define void @test_v8i8_v2f32(<2 x float>* %p, <8 x i8>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: rev64 v{{[0-9]+}}.8b
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = call <8 x i8> @test_v8i8_v2f32_helper(<2 x float> %2)
+    br label %return_bb
+return_bb:
     %4 = add <8 x i8> %3, %3
     store <8 x i8> %4, <8 x i8>* %q
     ret void
@@ -496,9 +580,11 @@ declare <8 x i8> @test_v8i8_v2i32_helper(<2 x i32> %p)
 define void @test_v8i8_v2i32(<2 x i32>* %p, <8 x i8>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.2s
 ; CHECK: rev64 v{{[0-9]+}}.8b
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = call <8 x i8> @test_v8i8_v2i32_helper(<2 x i32> %2)
+    br label %return_bb
+return_bb:
     %4 = add <8 x i8> %3, %3
     store <8 x i8> %4, <8 x i8>* %q
     ret void
@@ -509,9 +595,11 @@ declare <8 x i8> @test_v8i8_v4i16_helper(<4 x i16> %p)
 define void @test_v8i8_v4i16(<4 x i16>* %p, <8 x i8>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4h
 ; CHECK: rev64 v{{[0-9]+}}.8b
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = call <8 x i8> @test_v8i8_v4i16_helper(<4 x i16> %2)
+    br label %return_bb
+return_bb:
     %4 = add <8 x i8> %3, %3
     store <8 x i8> %4, <8 x i8>* %q
     ret void
@@ -521,9 +609,11 @@ define void @test_v8i8_v4i16(<4 x i16>* %p, <8 x i8>* %q) {
 declare fp128 @test_f128_v2f64_helper(<2 x double> %p)
 define void @test_f128_v2f64(<2 x double>* %p, fp128* %q) {
 ; CHECK: ext
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = call fp128 @test_f128_v2f64_helper(<2 x double> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd fp128 %3, %3
     store fp128 %4, fp128* %q
     ret void
@@ -533,9 +623,11 @@ define void @test_f128_v2f64(<2 x double>* %p, fp128* %q) {
 declare fp128 @test_f128_v2i64_helper(<2 x i64> %p)
 define void @test_f128_v2i64(<2 x i64>* %p, fp128* %q) {
 ; CHECK: ext
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = call fp128 @test_f128_v2i64_helper(<2 x i64> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd fp128 %3, %3
     store fp128 %4, fp128* %q
     ret void
@@ -546,9 +638,11 @@ declare fp128 @test_f128_v4f32_helper(<4 x float> %p)
 define void @test_f128_v4f32(<4 x float>* %p, fp128* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = call fp128 @test_f128_v4f32_helper(<4 x float> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd fp128 %3, %3
     store fp128 %4, fp128* %q
     ret void
@@ -559,9 +653,11 @@ declare fp128 @test_f128_v4i32_helper(<4 x i32> %p)
 define void @test_f128_v4i32(<4 x i32>* %p, fp128* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = call fp128 @test_f128_v4i32_helper(<4 x i32> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd fp128 %3, %3
     store fp128 %4, fp128* %q
     ret void
@@ -572,9 +668,11 @@ declare fp128 @test_f128_v8i16_helper(<8 x i16> %p)
 define void @test_f128_v8i16(<8 x i16>* %p, fp128* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.8h
 ; CHECK: ext
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = call fp128 @test_f128_v8i16_helper(<8 x i16> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd fp128 %3, %3
     store fp128 %4, fp128* %q
     ret void
@@ -585,9 +683,11 @@ declare fp128 @test_f128_v16i8_helper(<16 x i8> %p)
 define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.16b
 ; CHECK: ext
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = call fp128 @test_f128_v16i8_helper(<16 x i8> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd fp128 %3, %3
     store fp128 %4, fp128* %q
     ret void
@@ -597,9 +697,11 @@ define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) {
 declare <2 x double> @test_v2f64_f128_helper(fp128 %p)
 define void @test_v2f64_f128(fp128* %p, <2 x double>* %q) {
 ; CHECK: ext
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = call <2 x double> @test_v2f64_f128_helper(fp128 %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <2 x double> %3, %3
     store <2 x double> %4, <2 x double>* %q
     ret void
@@ -610,9 +712,11 @@ declare <2 x double> @test_v2f64_v2i64_helper(<2 x i64> %p)
 define void @test_v2f64_v2i64(<2 x i64>* %p, <2 x double>* %q) {
 ; CHECK: ext
 ; CHECK: ext
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = call <2 x double> @test_v2f64_v2i64_helper(<2 x i64> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <2 x double> %3, %3
     store <2 x double> %4, <2 x double>* %q
     ret void
@@ -624,9 +728,11 @@ define void @test_v2f64_v4f32(<4 x float>* %p, <2 x double>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
 ; CHECK: ext
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = call <2 x double> @test_v2f64_v4f32_helper(<4 x float> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <2 x double> %3, %3
     store <2 x double> %4, <2 x double>* %q
     ret void
@@ -638,9 +744,11 @@ define void @test_v2f64_v4i32(<4 x i32>* %p, <2 x double>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
 ; CHECK: ext
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = call <2 x double> @test_v2f64_v4i32_helper(<4 x i32> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <2 x double> %3, %3
     store <2 x double> %4, <2 x double>* %q
     ret void
@@ -652,9 +760,11 @@ define void @test_v2f64_v8i16(<8 x i16>* %p, <2 x double>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.8h
 ; CHECK: ext
 ; CHECK: ext
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = call <2 x double> @test_v2f64_v8i16_helper(<8 x i16> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <2 x double> %3, %3
     store <2 x double> %4, <2 x double>* %q
     ret void
@@ -666,9 +776,11 @@ define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.16b
 ; CHECK: ext
 ; CHECK: ext
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = call <2 x double> @test_v2f64_v16i8_helper(<16 x i8> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <2 x double> %3, %3
     store <2 x double> %4, <2 x double>* %q
     ret void
@@ -678,9 +790,11 @@ define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) {
 declare <2 x i64> @test_v2i64_f128_helper(fp128 %p)
 define void @test_v2i64_f128(fp128* %p, <2 x i64>* %q) {
 ; CHECK: ext
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = call <2 x i64> @test_v2i64_f128_helper(fp128 %2)
+    br label %return_bb
+return_bb:
     %4 = add <2 x i64> %3, %3
     store <2 x i64> %4, <2 x i64>* %q
     ret void
@@ -691,9 +805,11 @@ declare <2 x i64> @test_v2i64_v2f64_helper(<2 x double> %p)
 define void @test_v2i64_v2f64(<2 x double>* %p, <2 x i64>* %q) {
 ; CHECK: ext
 ; CHECK: ext
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = call <2 x i64> @test_v2i64_v2f64_helper(<2 x double> %2)
+    br label %return_bb
+return_bb:
     %4 = add <2 x i64> %3, %3
     store <2 x i64> %4, <2 x i64>* %q
     ret void
@@ -705,9 +821,11 @@ define void @test_v2i64_v4f32(<4 x float>* %p, <2 x i64>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
 ; CHECK: ext
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = call <2 x i64> @test_v2i64_v4f32_helper(<4 x float> %2)
+    br label %return_bb
+return_bb:
     %4 = add <2 x i64> %3, %3
     store <2 x i64> %4, <2 x i64>* %q
     ret void
@@ -719,9 +837,11 @@ define void @test_v2i64_v4i32(<4 x i32>* %p, <2 x i64>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
 ; CHECK: ext
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = call <2 x i64> @test_v2i64_v4i32_helper(<4 x i32> %2)
+    br label %return_bb
+return_bb:
     %4 = add <2 x i64> %3, %3
     store <2 x i64> %4, <2 x i64>* %q
     ret void
@@ -733,9 +853,11 @@ define void @test_v2i64_v8i16(<8 x i16>* %p, <2 x i64>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.8h
 ; CHECK: ext
 ; CHECK: ext
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = call <2 x i64> @test_v2i64_v8i16_helper(<8 x i16> %2)
+    br label %return_bb
+return_bb:
     %4 = add <2 x i64> %3, %3
     store <2 x i64> %4, <2 x i64>* %q
     ret void
@@ -747,9 +869,11 @@ define void @test_v2i64_v16i8(<16 x i8>* %p, <2 x i64>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.16b
 ; CHECK: ext
 ; CHECK: ext
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = call <2 x i64> @test_v2i64_v16i8_helper(<16 x i8> %2)
+    br label %return_bb
+return_bb:
     %4 = add <2 x i64> %3, %3
     store <2 x i64> %4, <2 x i64>* %q
     ret void
@@ -760,9 +884,11 @@ declare <4 x float> @test_v4f32_f128_helper(fp128 %p)
 define void @test_v4f32_f128(fp128* %p, <4 x float>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = call <4 x float> @test_v4f32_f128_helper(fp128 %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <4 x float> %3, %3
     store <4 x float> %4, <4 x float>* %q
     ret void
@@ -774,9 +900,11 @@ define void @test_v4f32_v2f64(<2 x double>* %p, <4 x float>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = call <4 x float> @test_v4f32_v2f64_helper(<2 x double> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <4 x float> %3, %3
     store <4 x float> %4, <4 x float>* %q
     ret void
@@ -788,9 +916,11 @@ define void @test_v4f32_v2i64(<2 x i64>* %p, <4 x float>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = call <4 x float> @test_v4f32_v2i64_helper(<2 x i64> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <4 x float> %3, %3
     store <4 x float> %4, <4 x float>* %q
     ret void
@@ -803,9 +933,11 @@ define void @test_v4f32_v4i32(<4 x i32>* %p, <4 x float>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = call <4 x float> @test_v4f32_v4i32_helper(<4 x i32> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <4 x float> %3, %3
     store <4 x float> %4, <4 x float>* %q
     ret void
@@ -818,9 +950,11 @@ define void @test_v4f32_v8i16(<8 x i16>* %p, <4 x float>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = call <4 x float> @test_v4f32_v8i16_helper(<8 x i16> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <4 x float> %3, %3
     store <4 x float> %4, <4 x float>* %q
     ret void
@@ -833,9 +967,11 @@ define void @test_v4f32_v16i8(<16 x i8>* %p, <4 x float>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = call <4 x float> @test_v4f32_v16i8_helper(<16 x i8> %2)
+    br label %return_bb
+return_bb:
     %4 = fadd <4 x float> %3, %3
     store <4 x float> %4, <4 x float>* %q
     ret void
@@ -846,9 +982,11 @@ declare <4 x i32> @test_v4i32_f128_helper(fp128 %p)
 define void @test_v4i32_f128(fp128* %p, <4 x i32>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = call <4 x i32> @test_v4i32_f128_helper(fp128 %2)
+    br label %return_bb
+return_bb:
     %4 = add <4 x i32> %3, %3
     store <4 x i32> %4, <4 x i32>* %q
     ret void
@@ -860,9 +998,11 @@ define void @test_v4i32_v2f64(<2 x double>* %p, <4 x i32>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = call <4 x i32> @test_v4i32_v2f64_helper(<2 x double> %2)
+    br label %return_bb
+return_bb:
     %4 = add <4 x i32> %3, %3
     store <4 x i32> %4, <4 x i32>* %q
     ret void
@@ -874,9 +1014,11 @@ define void @test_v4i32_v2i64(<2 x i64>* %p, <4 x i32>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = call <4 x i32> @test_v4i32_v2i64_helper(<2 x i64> %2)
+    br label %return_bb
+return_bb:
     %4 = add <4 x i32> %3, %3
     store <4 x i32> %4, <4 x i32>* %q
     ret void
@@ -889,9 +1031,11 @@ define void @test_v4i32_v4f32(<4 x float>* %p, <4 x i32>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = call <4 x i32> @test_v4i32_v4f32_helper(<4 x float> %2)
+    br label %return_bb
+return_bb:
     %4 = add <4 x i32> %3, %3
     store <4 x i32> %4, <4 x i32>* %q
     ret void
@@ -904,9 +1048,11 @@ define void @test_v4i32_v8i16(<8 x i16>* %p, <4 x i32>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = call <4 x i32> @test_v4i32_v8i16_helper(<8 x i16> %2)
+    br label %return_bb
+return_bb:
     %4 = add <4 x i32> %3, %3
     store <4 x i32> %4, <4 x i32>* %q
     ret void
@@ -919,9 +1065,11 @@ define void @test_v4i32_v16i8(<16 x i8>* %p, <4 x i32>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.4s
 ; CHECK: ext
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = call <4 x i32> @test_v4i32_v16i8_helper(<16 x i8> %2)
+    br label %return_bb
+return_bb:
     %4 = add <4 x i32> %3, %3
     store <4 x i32> %4, <4 x i32>* %q
     ret void
@@ -932,9 +1080,11 @@ declare <8 x i16> @test_v8i16_f128_helper(fp128 %p)
 define void @test_v8i16_f128(fp128* %p, <8 x i16>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.8h
 ; CHECK: ext
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = call <8 x i16> @test_v8i16_f128_helper(fp128 %2)
+    br label %return_bb
+return_bb:
     %4 = add <8 x i16> %3, %3
     store <8 x i16> %4, <8 x i16>* %q
     ret void
@@ -946,9 +1096,11 @@ define void @test_v8i16_v2f64(<2 x double>* %p, <8 x i16>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.8h
 ; CHECK: ext
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = call <8 x i16> @test_v8i16_v2f64_helper(<2 x double> %2)
+    br label %return_bb
+return_bb:
     %4 = add <8 x i16> %3, %3
     store <8 x i16> %4, <8 x i16>* %q
     ret void
@@ -960,9 +1112,11 @@ define void @test_v8i16_v2i64(<2 x i64>* %p, <8 x i16>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.8h
 ; CHECK: ext
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = call <8 x i16> @test_v8i16_v2i64_helper(<2 x i64> %2)
+    br label %return_bb
+return_bb:
     %4 = add <8 x i16> %3, %3
     store <8 x i16> %4, <8 x i16>* %q
     ret void
@@ -975,9 +1129,11 @@ define void @test_v8i16_v4f32(<4 x float>* %p, <8 x i16>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.8h
 ; CHECK: ext
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = call <8 x i16> @test_v8i16_v4f32_helper(<4 x float> %2)
+    br label %return_bb
+return_bb:
     %4 = add <8 x i16> %3, %3
     store <8 x i16> %4, <8 x i16>* %q
     ret void
@@ -990,9 +1146,11 @@ define void @test_v8i16_v4i32(<4 x i32>* %p, <8 x i16>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.8h
 ; CHECK: ext
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = call <8 x i16> @test_v8i16_v4i32_helper(<4 x i32> %2)
+    br label %return_bb
+return_bb:
     %4 = add <8 x i16> %3, %3
     store <8 x i16> %4, <8 x i16>* %q
     ret void
@@ -1005,9 +1163,11 @@ define void @test_v8i16_v16i8(<16 x i8>* %p, <8 x i16>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.8h
 ; CHECK: ext
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = call <8 x i16> @test_v8i16_v16i8_helper(<16 x i8> %2)
+    br label %return_bb
+return_bb:
     %4 = add <8 x i16> %3, %3
     store <8 x i16> %4, <8 x i16>* %q
     ret void
@@ -1018,9 +1178,11 @@ declare <16 x i8> @test_v16i8_f128_helper(fp128 %p)
 define void @test_v16i8_f128(fp128* %p, <16 x i8>* %q) {
 ; CHECK: rev64 v{{[0-9]+}}.16b
 ; CHECK: ext
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = call <16 x i8> @test_v16i8_f128_helper(fp128 %2)
+    br label %return_bb
+return_bb:
     %4 = add <16 x i8> %3, %3
     store <16 x i8> %4, <16 x i8>* %q
     ret void
@@ -1032,9 +1194,11 @@ define void @test_v16i8_v2f64(<2 x double>* %p, <16 x i8>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.16b
 ; CHECK: ext
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = call <16 x i8> @test_v16i8_v2f64_helper(<2 x double> %2)
+    br label %return_bb
+return_bb:
     %4 = add <16 x i8> %3, %3
     store <16 x i8> %4, <16 x i8>* %q
     ret void
@@ -1046,9 +1210,11 @@ define void @test_v16i8_v2i64(<2 x i64>* %p, <16 x i8>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.16b
 ; CHECK: ext
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = call <16 x i8> @test_v16i8_v2i64_helper(<2 x i64> %2)
+    br label %return_bb
+return_bb:
     %4 = add <16 x i8> %3, %3
     store <16 x i8> %4, <16 x i8>* %q
     ret void
@@ -1061,9 +1227,11 @@ define void @test_v16i8_v4f32(<4 x float>* %p, <16 x i8>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.16b
 ; CHECK: ext
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = call <16 x i8> @test_v16i8_v4f32_helper(<4 x float> %2)
+    br label %return_bb
+return_bb:
     %4 = add <16 x i8> %3, %3
     store <16 x i8> %4, <16 x i8>* %q
     ret void
@@ -1076,9 +1244,11 @@ define void @test_v16i8_v4i32(<4 x i32>* %p, <16 x i8>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.16b
 ; CHECK: ext
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = call <16 x i8> @test_v16i8_v4i32_helper(<4 x i32> %2)
+    br label %return_bb
+return_bb:
     %4 = add <16 x i8> %3, %3
     store <16 x i8> %4, <16 x i8>* %q
     ret void
@@ -1091,9 +1261,11 @@ define void @test_v16i8_v8i16(<8 x i16>* %p, <16 x i8>* %q) {
 ; CHECK: ext
 ; CHECK: rev64 v{{[0-9]+}}.16b
 ; CHECK: ext
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = call <16 x i8> @test_v16i8_v8i16_helper(<8 x i16> %2)
+    br label %return_bb
+return_bb:
     %4 = add <16 x i8> %3, %3
     store <16 x i8> %4, <16 x i8>* %q
     ret void
diff --git a/test/CodeGen/AArch64/arm64-big-stack.ll b/test/CodeGen/AArch64/arm64-big-stack.ll
index 3f91bb3c2482..c9acbc5f054c 100644
--- a/test/CodeGen/AArch64/arm64-big-stack.ll
+++ b/test/CodeGen/AArch64/arm64-big-stack.ll
@@ -13,7 +13,7 @@ target triple = "arm64-apple-macosx10"
 define void @foo() nounwind ssp {
 entry:
   %buffer = alloca [33554432 x i8], align 1
-  %arraydecay = getelementptr inbounds [33554432 x i8]* %buffer, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [33554432 x i8], [33554432 x i8]* %buffer, i64 0, i64 0
   call void @doit(i8* %arraydecay) nounwind
   ret void
 }
diff --git a/test/CodeGen/AArch64/arm64-bitfield-extract.ll b/test/CodeGen/AArch64/arm64-bitfield-extract.ll
index 112efddd4fad..5dca92941211 100644
--- a/test/CodeGen/AArch64/arm64-bitfield-extract.ll
+++ b/test/CodeGen/AArch64/arm64-bitfield-extract.ll
@@ -12,8 +12,8 @@ define void @foo(%struct.X* nocapture %x, %struct.Y* nocapture %y) nounwind opts
 ; CHECK: ret
 
   %tmp = bitcast %struct.X* %x to i32*
-  %tmp1 = load i32* %tmp, align 4
-  %b = getelementptr inbounds %struct.Y* %y, i64 0, i32 1
+  %tmp1 = load i32, i32* %tmp, align 4
+  %b = getelementptr inbounds %struct.Y, %struct.Y* %y, i64 0, i32 1
   %bf.clear = lshr i32 %tmp1, 3
   %bf.clear.lobit = and i32 %bf.clear, 1
   %frombool = trunc i32 %bf.clear.lobit to i8
@@ -46,8 +46,8 @@ define void @fct1(%struct.Z* nocapture %x, %struct.A* nocapture %y) nounwind opt
 ; CHECK: ret
 
   %tmp = bitcast %struct.Z* %x to i64*
-  %tmp1 = load i64* %tmp, align 4
-  %b = getelementptr inbounds %struct.A* %y, i64 0, i32 0
+  %tmp1 = load i64, i64* %tmp, align 4
+  %b = getelementptr inbounds %struct.A, %struct.A* %y, i64 0, i32 0
   %bf.clear = lshr i64 %tmp1, 3
   %bf.clear.lobit = and i64 %bf.clear, 1
   store i64 %bf.clear.lobit, i64* %b, align 8
@@ -77,7 +77,7 @@ entry:
 ; CHECK-NEXT: bfxil [[REG1]], x1, #16, #24
 ; CHECK-NEXT: str [[REG1]],
 ; CHECK-NEXT: ret
-  %0 = load i64* %y, align 8
+  %0 = load i64, i64* %y, align 8
   %and = and i64 %0, -16777216
   %shr = lshr i64 %x, 16
   %and1 = and i64 %shr, 16777215
@@ -93,7 +93,7 @@ entry:
 ; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3
 ; CHECK-NEXT: str [[REG1]],
 ; CHECK-NEXT: ret
-  %0 = load i32* %y, align 8
+  %0 = load i32, i32* %y, align 8
   %and = and i32 %0, -8
   %shr = lshr i32 %x, 16
   %and1 = and i32 %shr, 7
@@ -112,7 +112,7 @@ entry:
 ; CHECK-NEXT: lsr [[REG2:w[0-9]+]], [[REG1]], #2
 ; CHECK-NEXT: str [[REG2]],
 ; CHECK-NEXT: ret
-  %0 = load i32* %y, align 8
+  %0 = load i32, i32* %y, align 8
   %and = and i32 %0, -8
   %shr = lshr i32 %x, 16
   %and1 = and i32 %shr, 7
@@ -133,7 +133,7 @@ entry:
 ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], [[REG1]], #2
 ; CHECK-NEXT: str [[REG2]],
 ; CHECK-NEXT: ret
-  %0 = load i32* %y, align 8
+  %0 = load i32, i32* %y, align 8
   %and = and i32 %0, -8
   %shr = lshr i32 %x, 16
   %and1 = and i32 %shr, 7
@@ -155,7 +155,7 @@ entry:
 ; CHECK-NEXT: lsr [[REG2:x[0-9]+]], [[REG1]], #2
 ; CHECK-NEXT: str [[REG2]],
 ; CHECK-NEXT: ret
-  %0 = load i64* %y, align 8
+  %0 = load i64, i64* %y, align 8
   %and = and i64 %0, -8
   %shr = lshr i64 %x, 16
   %and1 = and i64 %shr, 7
@@ -177,7 +177,7 @@ entry:
 ; CHECK-NEXT: lsl [[REG2:x[0-9]+]], [[REG1]], #2
 ; CHECK-NEXT: str [[REG2]],
 ; CHECK-NEXT: ret
-  %0 = load i64* %y, align 8
+  %0 = load i64, i64* %y, align 8
   %and = and i64 %0, -8
   %shr = lshr i64 %x, 16
   %and1 = and i64 %shr, 7
@@ -198,7 +198,7 @@ entry:
 ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], [[REG1]], #2
 ; CHECK-NEXT: str [[REG2]],
 ; CHECK-NEXT: ret
-  %0 = load i32* %y, align 8
+  %0 = load i32, i32* %y, align 8
   %and = and i32 %0, -8
   %and1 = and i32 %x, 7
   %or = or i32 %and, %and1
@@ -218,7 +218,7 @@ entry:
 ; CHECK-NEXT: lsl [[REG2:x[0-9]+]], [[REG1]], #2
 ; CHECK-NEXT: str [[REG2]],
 ; CHECK-NEXT: ret
-  %0 = load i64* %y, align 8
+  %0 = load i64, i64* %y, align 8
   %and = and i64 %0, -8
   %and1 = and i64 %x, 7
   %or = or i64 %and, %and1
@@ -247,7 +247,7 @@ entry:
 ; CHECK-NEXT: ubfx [[REG2:w[0-9]+]], [[REG1]], #2, #28
 ; CHECK-NEXT: str [[REG2]],
 ; CHECK-NEXT: ret
-  %0 = load i32* %y, align 8
+  %0 = load i32, i32* %y, align 8
   %and = and i32 %0, -8
   %shr = lshr i32 %x, 16
   %and1 = and i32 %shr, 7
@@ -270,7 +270,7 @@ entry:
 ; CHECK-NEXT: ubfx [[REG2:x[0-9]+]], [[REG1]], #2, #60
 ; CHECK-NEXT: str [[REG2]],
 ; CHECK-NEXT: ret
-  %0 = load i64* %y, align 8
+  %0 = load i64, i64* %y, align 8
   %and = and i64 %0, -8
   %shr = lshr i64 %x, 16
   %and1 = and i64 %shr, 7
@@ -296,7 +296,7 @@ entry:
 ; CHECK-NEXT: lsl [[REG3:w[0-9]+]], [[REG2]], #2
 ; CHECK-NEXT: str [[REG3]],
 ; CHECK-NEXT: ret
-  %0 = load i32* %y, align 8
+  %0 = load i32, i32* %y, align 8
   %and = and i32 %0, -256
   %shr = lshr i32 %x, 16
   %and1 = and i32 %shr, 255
@@ -326,7 +326,7 @@ entry:
 ; CHECK-NEXT: lsl [[REG3:x[0-9]+]], [[REG2]], #2
 ; CHECK-NEXT: str [[REG3]],
 ; CHECK-NEXT: ret
-  %0 = load i64* %y, align 8
+  %0 = load i64, i64* %y, align 8
   %and = and i64 %0, -256
   %shr = lshr i64 %x, 16
   %and1 = and i64 %shr, 255
@@ -357,7 +357,7 @@ entry:
 ; CHECK-NEXT: ubfx [[REG3:w[0-9]+]], [[REG2]], #2, #28
 ; CHECK-NEXT: str [[REG3]],
 ; CHECK-NEXT: ret
-  %0 = load i32* %y, align 8
+  %0 = load i32, i32* %y, align 8
   %and = and i32 %0, 1737056
   %shr = lshr i32 %x, 16
   %and1 = and i32 %shr, 7
@@ -386,7 +386,7 @@ entry:
 ; CHECK-NEXT: ubfx [[REG3:x[0-9]+]], [[REG2]], #2, #60
 ; CHECK-NEXT: str [[REG3]],
 ; CHECK-NEXT: ret
-  %0 = load i64* %y, align 8
+  %0 = load i64, i64* %y, align 8
   %and = and i64 %0, 1737056
   %shr = lshr i64 %x, 16
   %and1 = and i64 %shr, 7
@@ -421,8 +421,8 @@ entry:
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry
-  %arrayidx3 = getelementptr inbounds [65536 x i8]* @first_ones, i64 0, i64 %x.sroa.5.0.extract.shift
-  %0 = load i8* %arrayidx3, align 1
+  %arrayidx3 = getelementptr inbounds [65536 x i8], [65536 x i8]* @first_ones, i64 0, i64 %x.sroa.5.0.extract.shift
+  %0 = load i8, i8* %arrayidx3, align 1
   %conv = zext i8 %0 to i32
   br label %return
 
@@ -443,8 +443,8 @@ if.then7:                                         ; preds = %if.end
 ; CHECK-NOT: and
 ; CHECK-NOT: ubfm
   %idxprom10 = and i64 %x.sroa.3.0.extract.shift, 65535
-  %arrayidx11 = getelementptr inbounds [65536 x i8]* @first_ones, i64 0, i64 %idxprom10
-  %1 = load i8* %arrayidx11, align 1
+  %arrayidx11 = getelementptr inbounds [65536 x i8], [65536 x i8]* @first_ones, i64 0, i64 %idxprom10
+  %1 = load i8, i8* %arrayidx11, align 1
   %conv12 = zext i8 %1 to i32
   %add = add nsw i32 %conv12, 16
   br label %return
@@ -466,8 +466,8 @@ if.then17:                                        ; preds = %if.end13
 ; CHECK-NOT: and
 ; CHECK-NOT: ubfm
   %idxprom20 = and i64 %x.sroa.1.0.extract.shift, 65535
-  %arrayidx21 = getelementptr inbounds [65536 x i8]* @first_ones, i64 0, i64 %idxprom20
-  %2 = load i8* %arrayidx21, align 1
+  %arrayidx21 = getelementptr inbounds [65536 x i8], [65536 x i8]* @first_ones, i64 0, i64 %idxprom20
+  %2 = load i8, i8* %arrayidx21, align 1
   %conv22 = zext i8 %2 to i32
   %add23 = add nsw i32 %conv22, 32
   br label %return
@@ -509,8 +509,8 @@ define i64 @fct21(i64 %x) {
 entry:
   %shr = lshr i64 %x, 4
   %and = and i64 %shr, 15
-  %arrayidx = getelementptr inbounds [8 x [64 x i64]]* @arr, i64 0, i64 0, i64 %and
-  %0 = load i64* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds [8 x [64 x i64]], [8 x [64 x i64]]* @arr, i64 0, i64 0, i64 %and
+  %0 = load i64, i64* %arrayidx, align 8
   ret i64 %0
 }
 
diff --git a/test/CodeGen/AArch64/arm64-blockaddress.ll b/test/CodeGen/AArch64/arm64-blockaddress.ll
index ac4f19e65dff..5df840216352 100644
--- a/test/CodeGen/AArch64/arm64-blockaddress.ll
+++ b/test/CodeGen/AArch64/arm64-blockaddress.ll
@@ -25,6 +25,6 @@ entry:
   br label %mylabel
 
 mylabel:
-  %tmp = load volatile i64* %recover, align 8
+  %tmp = load volatile i64, i64* %recover, align 8
   ret i64 %tmp
 }
diff --git a/test/CodeGen/AArch64/arm64-call-tailcalls.ll b/test/CodeGen/AArch64/arm64-call-tailcalls.ll
index 487c1d9bec3b..6621db25da5b 100644
--- a/test/CodeGen/AArch64/arm64-call-tailcalls.ll
+++ b/test/CodeGen/AArch64/arm64-call-tailcalls.ll
@@ -9,7 +9,7 @@ define void @t2() {
 ; CHECK: ldr	x[[ADDR:[0-9]+]], [x[[GOTADDR]], _t@GOTPAGEOFF]
 ; CHECK: ldr	x[[DEST:[0-9]+]], [x[[ADDR]]]
 ; CHECK: br	x[[DEST]]
-  %tmp = load i32 ()** @t
+  %tmp = load i32 ()*, i32 ()** @t
   %tmp.upgrd.2 = tail call i32 %tmp()
   ret void
 }
@@ -53,9 +53,9 @@ bb:                                               ; preds = %entry
 
 define i32 @t8(i32 %x) nounwind ssp {
 ; CHECK-LABEL: t8:
+; CHECK: b	_c
 ; CHECK: b	_a
 ; CHECK: b	_b
-; CHECK: b	_c
   %and = and i32 %x, 1
   %tobool = icmp eq i32 %and, 0
   br i1 %tobool, label %if.end, label %if.then
diff --git a/test/CodeGen/AArch64/arm64-cast-opt.ll b/test/CodeGen/AArch64/arm64-cast-opt.ll
index 65a871d43685..463add5688e3 100644
--- a/test/CodeGen/AArch64/arm64-cast-opt.ll
+++ b/test/CodeGen/AArch64/arm64-cast-opt.ll
@@ -11,12 +11,12 @@ define zeroext i8 @foo(i32 %i1, i32 %i2) {
 ; CHECK-NOT: and
 entry:
   %idxprom = sext i32 %i1 to i64
-  %0 = load i8** @block, align 8
-  %arrayidx = getelementptr inbounds i8* %0, i64 %idxprom
-  %1 = load i8* %arrayidx, align 1
+  %0 = load i8*, i8** @block, align 8
+  %arrayidx = getelementptr inbounds i8, i8* %0, i64 %idxprom
+  %1 = load i8, i8* %arrayidx, align 1
   %idxprom1 = sext i32 %i2 to i64
-  %arrayidx2 = getelementptr inbounds i8* %0, i64 %idxprom1
-  %2 = load i8* %arrayidx2, align 1
+  %arrayidx2 = getelementptr inbounds i8, i8* %0, i64 %idxprom1
+  %2 = load i8, i8* %arrayidx2, align 1
   %cmp = icmp eq i8 %1, %2
   br i1 %cmp, label %return, label %if.then
 
diff --git a/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll b/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll
index b032d9c89ef6..4e47ab6c03f3 100644
--- a/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll
+++ b/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll
@@ -21,7 +21,7 @@ target triple = "arm64-apple-ios7.0.0"
 ; CHECK-NEXT b.cc
 define i32 @Maze1() nounwind ssp {
 entry:
-  %0 = load i64* @channelColumns, align 8, !tbaa !0
+  %0 = load i64, i64* @channelColumns, align 8, !tbaa !0
   %cmp90 = icmp eq i64 %0, 0
   br i1 %cmp90, label %for.end, label %for.body
 
@@ -29,51 +29,51 @@ for.body:                                         ; preds = %for.inc, %entry
   %1 = phi i64 [ %0, %entry ], [ %37, %for.inc ]
   %i.092 = phi i64 [ 1, %entry ], [ %inc53, %for.inc ]
   %numLeft.091 = phi i32 [ 0, %entry ], [ %numLeft.1, %for.inc ]
-  %2 = load i8** @mazeRoute, align 8, !tbaa !3
-  %arrayidx = getelementptr inbounds i8* %2, i64 %i.092
-  %3 = load i8* %arrayidx, align 1, !tbaa !1
+  %2 = load i8*, i8** @mazeRoute, align 8, !tbaa !3
+  %arrayidx = getelementptr inbounds i8, i8* %2, i64 %i.092
+  %3 = load i8, i8* %arrayidx, align 1, !tbaa !1
   %tobool = icmp eq i8 %3, 0
   br i1 %tobool, label %for.inc, label %if.then
 
 if.then:                                          ; preds = %for.body
-  %4 = load i64** @TOP, align 8, !tbaa !3
-  %arrayidx1 = getelementptr inbounds i64* %4, i64 %i.092
-  %5 = load i64* %arrayidx1, align 8, !tbaa !0
-  %6 = load i64** @netsAssign, align 8, !tbaa !3
-  %arrayidx2 = getelementptr inbounds i64* %6, i64 %5
-  %7 = load i64* %arrayidx2, align 8, !tbaa !0
-  %8 = load i64** @BOT, align 8, !tbaa !3
-  %arrayidx3 = getelementptr inbounds i64* %8, i64 %i.092
-  %9 = load i64* %arrayidx3, align 8, !tbaa !0
-  %arrayidx4 = getelementptr inbounds i64* %6, i64 %9
-  %10 = load i64* %arrayidx4, align 8, !tbaa !0
+  %4 = load i64*, i64** @TOP, align 8, !tbaa !3
+  %arrayidx1 = getelementptr inbounds i64, i64* %4, i64 %i.092
+  %5 = load i64, i64* %arrayidx1, align 8, !tbaa !0
+  %6 = load i64*, i64** @netsAssign, align 8, !tbaa !3
+  %arrayidx2 = getelementptr inbounds i64, i64* %6, i64 %5
+  %7 = load i64, i64* %arrayidx2, align 8, !tbaa !0
+  %8 = load i64*, i64** @BOT, align 8, !tbaa !3
+  %arrayidx3 = getelementptr inbounds i64, i64* %8, i64 %i.092
+  %9 = load i64, i64* %arrayidx3, align 8, !tbaa !0
+  %arrayidx4 = getelementptr inbounds i64, i64* %6, i64 %9
+  %10 = load i64, i64* %arrayidx4, align 8, !tbaa !0
   %cmp5 = icmp ugt i64 %i.092, 1
   %cmp6 = icmp ugt i64 %10, 1
   %or.cond = and i1 %cmp5, %cmp6
   br i1 %or.cond, label %land.lhs.true7, label %if.else
 
 land.lhs.true7:                                   ; preds = %if.then
-  %11 = load i64* @channelTracks, align 8, !tbaa !0
+  %11 = load i64, i64* @channelTracks, align 8, !tbaa !0
   %add = add i64 %11, 1
   %call = tail call fastcc i32 @Maze1Mech(i64 %i.092, i64 %add, i64 %10, i64 0, i64 %7, i32 -1, i32 -1)
   %tobool8 = icmp eq i32 %call, 0
   br i1 %tobool8, label %land.lhs.true7.if.else_crit_edge, label %if.then9
 
 land.lhs.true7.if.else_crit_edge:                 ; preds = %land.lhs.true7
-  %.pre = load i64* @channelColumns, align 8, !tbaa !0
+  %.pre = load i64, i64* @channelColumns, align 8, !tbaa !0
   br label %if.else
 
 if.then9:                                         ; preds = %land.lhs.true7
-  %12 = load i8** @mazeRoute, align 8, !tbaa !3
-  %arrayidx10 = getelementptr inbounds i8* %12, i64 %i.092
+  %12 = load i8*, i8** @mazeRoute, align 8, !tbaa !3
+  %arrayidx10 = getelementptr inbounds i8, i8* %12, i64 %i.092
   store i8 0, i8* %arrayidx10, align 1, !tbaa !1
-  %13 = load i64** @TOP, align 8, !tbaa !3
-  %arrayidx11 = getelementptr inbounds i64* %13, i64 %i.092
-  %14 = load i64* %arrayidx11, align 8, !tbaa !0
+  %13 = load i64*, i64** @TOP, align 8, !tbaa !3
+  %arrayidx11 = getelementptr inbounds i64, i64* %13, i64 %i.092
+  %14 = load i64, i64* %arrayidx11, align 8, !tbaa !0
   tail call fastcc void @CleanNet(i64 %14)
-  %15 = load i64** @BOT, align 8, !tbaa !3
-  %arrayidx12 = getelementptr inbounds i64* %15, i64 %i.092
-  %16 = load i64* %arrayidx12, align 8, !tbaa !0
+  %15 = load i64*, i64** @BOT, align 8, !tbaa !3
+  %arrayidx12 = getelementptr inbounds i64, i64* %15, i64 %i.092
+  %16 = load i64, i64* %arrayidx12, align 8, !tbaa !0
   tail call fastcc void @CleanNet(i64 %16)
   br label %for.inc
 
@@ -84,23 +84,23 @@ if.else:                                          ; preds = %land.lhs.true7.if.e
   br i1 %or.cond89, label %land.lhs.true16, label %if.else24
 
 land.lhs.true16:                                  ; preds = %if.else
-  %18 = load i64* @channelTracks, align 8, !tbaa !0
+  %18 = load i64, i64* @channelTracks, align 8, !tbaa !0
   %add17 = add i64 %18, 1
   %call18 = tail call fastcc i32 @Maze1Mech(i64 %i.092, i64 %add17, i64 %10, i64 0, i64 %7, i32 1, i32 -1)
   %tobool19 = icmp eq i32 %call18, 0
   br i1 %tobool19, label %if.else24, label %if.then20
 
 if.then20:                                        ; preds = %land.lhs.true16
-  %19 = load i8** @mazeRoute, align 8, !tbaa !3
-  %arrayidx21 = getelementptr inbounds i8* %19, i64 %i.092
+  %19 = load i8*, i8** @mazeRoute, align 8, !tbaa !3
+  %arrayidx21 = getelementptr inbounds i8, i8* %19, i64 %i.092
   store i8 0, i8* %arrayidx21, align 1, !tbaa !1
-  %20 = load i64** @TOP, align 8, !tbaa !3
-  %arrayidx22 = getelementptr inbounds i64* %20, i64 %i.092
-  %21 = load i64* %arrayidx22, align 8, !tbaa !0
+  %20 = load i64*, i64** @TOP, align 8, !tbaa !3
+  %arrayidx22 = getelementptr inbounds i64, i64* %20, i64 %i.092
+  %21 = load i64, i64* %arrayidx22, align 8, !tbaa !0
   tail call fastcc void @CleanNet(i64 %21)
-  %22 = load i64** @BOT, align 8, !tbaa !3
-  %arrayidx23 = getelementptr inbounds i64* %22, i64 %i.092
-  %23 = load i64* %arrayidx23, align 8, !tbaa !0
+  %22 = load i64*, i64** @BOT, align 8, !tbaa !3
+  %arrayidx23 = getelementptr inbounds i64, i64* %22, i64 %i.092
+  %23 = load i64, i64* %arrayidx23, align 8, !tbaa !0
   tail call fastcc void @CleanNet(i64 %23)
   br label %for.inc
 
@@ -108,7 +108,7 @@ if.else24:                                        ; preds = %land.lhs.true16, %i
   br i1 %cmp5, label %land.lhs.true26, label %if.else36
 
 land.lhs.true26:                                  ; preds = %if.else24
-  %24 = load i64* @channelTracks, align 8, !tbaa !0
+  %24 = load i64, i64* @channelTracks, align 8, !tbaa !0
   %cmp27 = icmp ult i64 %7, %24
   br i1 %cmp27, label %land.lhs.true28, label %if.else36
 
@@ -119,26 +119,26 @@ land.lhs.true28:                                  ; preds = %land.lhs.true26
   br i1 %tobool31, label %if.else36, label %if.then32
 
 if.then32:                                        ; preds = %land.lhs.true28
-  %25 = load i8** @mazeRoute, align 8, !tbaa !3
-  %arrayidx33 = getelementptr inbounds i8* %25, i64 %i.092
+  %25 = load i8*, i8** @mazeRoute, align 8, !tbaa !3
+  %arrayidx33 = getelementptr inbounds i8, i8* %25, i64 %i.092
   store i8 0, i8* %arrayidx33, align 1, !tbaa !1
-  %26 = load i64** @TOP, align 8, !tbaa !3
-  %arrayidx34 = getelementptr inbounds i64* %26, i64 %i.092
-  %27 = load i64* %arrayidx34, align 8, !tbaa !0
+  %26 = load i64*, i64** @TOP, align 8, !tbaa !3
+  %arrayidx34 = getelementptr inbounds i64, i64* %26, i64 %i.092
+  %27 = load i64, i64* %arrayidx34, align 8, !tbaa !0
   tail call fastcc void @CleanNet(i64 %27)
-  %28 = load i64** @BOT, align 8, !tbaa !3
-  %arrayidx35 = getelementptr inbounds i64* %28, i64 %i.092
-  %29 = load i64* %arrayidx35, align 8, !tbaa !0
+  %28 = load i64*, i64** @BOT, align 8, !tbaa !3
+  %arrayidx35 = getelementptr inbounds i64, i64* %28, i64 %i.092
+  %29 = load i64, i64* %arrayidx35, align 8, !tbaa !0
   tail call fastcc void @CleanNet(i64 %29)
   br label %for.inc
 
 if.else36:                                        ; preds = %land.lhs.true28, %land.lhs.true26, %if.else24
-  %30 = load i64* @channelColumns, align 8, !tbaa !0
+  %30 = load i64, i64* @channelColumns, align 8, !tbaa !0
   %cmp37 = icmp ult i64 %i.092, %30
   br i1 %cmp37, label %land.lhs.true38, label %if.else48
 
 land.lhs.true38:                                  ; preds = %if.else36
-  %31 = load i64* @channelTracks, align 8, !tbaa !0
+  %31 = load i64, i64* @channelTracks, align 8, !tbaa !0
   %cmp39 = icmp ult i64 %7, %31
   br i1 %cmp39, label %land.lhs.true40, label %if.else48
 
@@ -149,16 +149,16 @@ land.lhs.true40:                                  ; preds = %land.lhs.true38
   br i1 %tobool43, label %if.else48, label %if.then44
 
 if.then44:                                        ; preds = %land.lhs.true40
-  %32 = load i8** @mazeRoute, align 8, !tbaa !3
-  %arrayidx45 = getelementptr inbounds i8* %32, i64 %i.092
+  %32 = load i8*, i8** @mazeRoute, align 8, !tbaa !3
+  %arrayidx45 = getelementptr inbounds i8, i8* %32, i64 %i.092
   store i8 0, i8* %arrayidx45, align 1, !tbaa !1
-  %33 = load i64** @TOP, align 8, !tbaa !3
-  %arrayidx46 = getelementptr inbounds i64* %33, i64 %i.092
-  %34 = load i64* %arrayidx46, align 8, !tbaa !0
+  %33 = load i64*, i64** @TOP, align 8, !tbaa !3
+  %arrayidx46 = getelementptr inbounds i64, i64* %33, i64 %i.092
+  %34 = load i64, i64* %arrayidx46, align 8, !tbaa !0
   tail call fastcc void @CleanNet(i64 %34)
-  %35 = load i64** @BOT, align 8, !tbaa !3
-  %arrayidx47 = getelementptr inbounds i64* %35, i64 %i.092
-  %36 = load i64* %arrayidx47, align 8, !tbaa !0
+  %35 = load i64*, i64** @BOT, align 8, !tbaa !3
+  %arrayidx47 = getelementptr inbounds i64, i64* %35, i64 %i.092
+  %36 = load i64, i64* %arrayidx47, align 8, !tbaa !0
   tail call fastcc void @CleanNet(i64 %36)
   br label %for.inc
 
@@ -169,7 +169,7 @@ if.else48:                                        ; preds = %land.lhs.true40, %l
 for.inc:                                          ; preds = %if.else48, %if.then44, %if.then32, %if.then20, %if.then9, %for.body
   %numLeft.1 = phi i32 [ %numLeft.091, %if.then9 ], [ %numLeft.091, %if.then20 ], [ %numLeft.091, %if.then32 ], [ %numLeft.091, %if.then44 ], [ %inc, %if.else48 ], [ %numLeft.091, %for.body ]
   %inc53 = add i64 %i.092, 1
-  %37 = load i64* @channelColumns, align 8, !tbaa !0
+  %37 = load i64, i64* @channelColumns, align 8, !tbaa !0
   %cmp = icmp ugt i64 %inc53, %37
   br i1 %cmp, label %for.end, label %for.body
 
diff --git a/test/CodeGen/AArch64/arm64-ccmp.ll b/test/CodeGen/AArch64/arm64-ccmp.ll
index 63965f9538b5..ff18f7364337 100644
--- a/test/CodeGen/AArch64/arm64-ccmp.ll
+++ b/test/CodeGen/AArch64/arm64-ccmp.ll
@@ -281,9 +281,9 @@ if.end85:
 
 sw.bb.i.i:
   %ref.tr.i.i = phi %str1* [ %0, %sw.bb.i.i ], [ undef, %entry ]
-  %operands.i.i = getelementptr inbounds %str1* %ref.tr.i.i, i64 0, i32 0, i32 2
+  %operands.i.i = getelementptr inbounds %str1, %str1* %ref.tr.i.i, i64 0, i32 0, i32 2
   %arrayidx.i.i = bitcast i32* %operands.i.i to %str1**
-  %0 = load %str1** %arrayidx.i.i, align 8
-  %code1.i.i.phi.trans.insert = getelementptr inbounds %str1* %0, i64 0, i32 0, i32 0, i64 16
+  %0 = load %str1*, %str1** %arrayidx.i.i, align 8
+  %code1.i.i.phi.trans.insert = getelementptr inbounds %str1, %str1* %0, i64 0, i32 0, i32 0, i64 16
   br label %sw.bb.i.i
 }
diff --git a/test/CodeGen/AArch64/arm64-code-model-large-abs.ll b/test/CodeGen/AArch64/arm64-code-model-large-abs.ll
index 264da2da25bc..9f50fea370e4 100644
--- a/test/CodeGen/AArch64/arm64-code-model-large-abs.ll
+++ b/test/CodeGen/AArch64/arm64-code-model-large-abs.ll
@@ -18,7 +18,7 @@ define i8* @global_addr() {
 
 define i8 @global_i8() {
 ; CHECK-LABEL: global_i8:
-  %val = load i8* @var8
+  %val = load i8, i8* @var8
   ret i8 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
@@ -29,7 +29,7 @@ define i8 @global_i8() {
 
 define i16 @global_i16() {
 ; CHECK-LABEL: global_i16:
-  %val = load i16* @var16
+  %val = load i16, i16* @var16
   ret i16 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
@@ -40,7 +40,7 @@ define i16 @global_i16() {
 
 define i32 @global_i32() {
 ; CHECK-LABEL: global_i32:
-  %val = load i32* @var32
+  %val = load i32, i32* @var32
   ret i32 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
@@ -51,7 +51,7 @@ define i32 @global_i32() {
 
 define i64 @global_i64() {
 ; CHECK-LABEL: global_i64:
-  %val = load i64* @var64
+  %val = load i64, i64* @var64
   ret i64 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
diff --git a/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll b/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
new file mode 100644
index 000000000000..f0b8299a66e3
--- /dev/null
+++ b/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
@@ -0,0 +1,638 @@
+; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS
+; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -stress-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS
+; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -disable-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=DISABLE
+
+; CodeGenPrepare should move the zext into the block with the load
+; so that SelectionDAG can select it with the load.
+;
+; OPTALL-LABEL: @foo
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+; OPTALL-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; OPTALL: store i32 [[ZEXT]], i32* %q
+; OPTALL: ret
+define void @foo(i8* %p, i32* %q) {
+entry:
+  %t = load i8, i8* %p
+  %a = icmp slt i8 %t, 20
+  br i1 %a, label %true, label %false
+true:
+  %s = zext i8 %t to i32
+  store i32 %s, i32* %q
+  ret void
+false:
+  ret void
+}
+
+; Check that we manage to form a zextload is an operation with only one
+; argument to explicitly extend is in the the way.
+; OPTALL-LABEL: @promoteOneArg
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+; OPT-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT]], 2
+; Make sure the operation is not promoted when the promotion pass is disabled.
+; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], 2
+; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
+; OPTALL: store i32 [[RES]], i32* %q
+; OPTALL: ret
+define void @promoteOneArg(i8* %p, i32* %q) {
+entry:
+  %t = load i8, i8* %p
+  %add = add nuw i8 %t, 2
+  %a = icmp slt i8 %t, 20
+  br i1 %a, label %true, label %false
+true:
+  %s = zext i8 %add to i32
+  store i32 %s, i32* %q
+  ret void
+false:
+  ret void
+}
+
+; Check that we manage to form a sextload is an operation with only one
+; argument to explicitly extend is in the the way.
+; Version with sext.
+; OPTALL-LABEL: @promoteOneArgSExt
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
+; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2
+; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], 2
+; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
+; OPTALL: store i32 [[RES]], i32* %q
+; OPTALL: ret
+define void @promoteOneArgSExt(i8* %p, i32* %q) {
+entry:
+  %t = load i8, i8* %p
+  %add = add nsw i8 %t, 2
+  %a = icmp slt i8 %t, 20
+  br i1 %a, label %true, label %false
+true:
+  %s = sext i8 %add to i32
+  store i32 %s, i32* %q
+  ret void
+false:
+  ret void
+}
+
+; Check that we manage to form a zextload is an operation with two
+; arguments to explicitly extend is in the the way.
+; Extending %add will create two extensions:
+; 1. One for %b.
+; 2. One for %t.
+; #1 will not be removed as we do not know anything about %b.
+; #2 may not be merged with the load because %t is used in a comparison.
+; Since two extensions may be emitted in the end instead of one before the
+; transformation, the regular heuristic does not apply the optimization. 
+; 
+; OPTALL-LABEL: @promoteTwoArgZext
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+;
+; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32
+; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
+;
+; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
+; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
+;
+; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
+; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
+;
+; OPTALL: store i32 [[RES]], i32* %q
+; OPTALL: ret
+define void @promoteTwoArgZext(i8* %p, i32* %q, i8 %b) {
+entry:
+  %t = load i8, i8* %p
+  %add = add nuw i8 %t, %b
+  %a = icmp slt i8 %t, 20
+  br i1 %a, label %true, label %false
+true:
+  %s = zext i8 %add to i32
+  store i32 %s, i32* %q
+  ret void
+false:
+  ret void
+}
+
+; Check that we manage to form a sextload is an operation with two
+; arguments to explicitly extend is in the the way.
+; Version with sext.
+; OPTALL-LABEL: @promoteTwoArgSExt
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+;
+; STRESS-NEXT: [[SEXTLD:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
+; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i8 %b to i32
+; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXTLD]], [[SEXTB]]
+;
+; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b
+; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
+;
+; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b
+; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
+; OPTALL: store i32 [[RES]], i32* %q
+; OPTALL: ret
+define void @promoteTwoArgSExt(i8* %p, i32* %q, i8 %b) {
+entry:
+  %t = load i8, i8* %p
+  %add = add nsw i8 %t, %b
+  %a = icmp slt i8 %t, 20
+  br i1 %a, label %true, label %false
+true:
+  %s = sext i8 %add to i32
+  store i32 %s, i32* %q
+  ret void
+false:
+  ret void
+}
+
+; Check that we do not a zextload if we need to introduce more than
+; one additional extension.
+; OPTALL-LABEL: @promoteThreeArgZext
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+;
+; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32
+; STRESS-NEXT: [[TMP:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
+; STRESS-NEXT: [[ZEXTC:%[a-zA-Z_0-9-]+]] = zext i8 %c to i32
+; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[TMP]], [[ZEXTC]]
+;
+; NONSTRESS-NEXT: [[TMP:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
+; NONSTRESS-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[TMP]], %c
+; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
+;
+; DISABLE: add nuw i8
+; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8
+; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
+;
+; OPTALL: store i32 [[RES]], i32* %q
+; OPTALL: ret
+define void @promoteThreeArgZext(i8* %p, i32* %q, i8 %b, i8 %c) {
+entry:
+  %t = load i8, i8* %p
+  %tmp = add nuw i8 %t, %b
+  %add = add nuw i8 %tmp, %c
+  %a = icmp slt i8 %t, 20
+  br i1 %a, label %true, label %false
+true:
+  %s = zext i8 %add to i32
+  store i32 %s, i32* %q
+  ret void
+false:
+  ret void
+}
+
+; Check that we manage to form a zextload after promoting and merging
+; two extensions.
+; OPTALL-LABEL: @promoteMergeExtArgZExt
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+;
+; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i16 %b to i32
+; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
+;
+; NONSTRESS: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
+; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i16 [[ZEXTLD]], %b
+; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i16 [[ADD]] to i32
+;
+; DISABLE: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
+; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i16 [[ZEXTLD]], %b
+; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i16 [[ADD]] to i32
+;
+; OPTALL: store i32 [[RES]], i32* %q
+; OPTALL: ret
+define void @promoteMergeExtArgZExt(i8* %p, i32* %q, i16 %b) {
+entry:
+  %t = load i8, i8* %p
+  %ext = zext i8 %t to i16
+  %add = add nuw i16 %ext, %b
+  %a = icmp slt i8 %t, 20
+  br i1 %a, label %true, label %false
+true:
+  %s = zext i16 %add to i32
+  store i32 %s, i32* %q
+  ret void
+false:
+  ret void
+}
+
+; Check that we manage to form a sextload after promoting and merging
+; two extensions.
+; Version with sext.
+; OPTALL-LABEL: @promoteMergeExtArgSExt
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+;
+; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = sext i16 %b to i32
+; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXTLD]], [[ZEXTB]]
+;
+; NONSTRESS: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
+; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i16 [[ZEXTLD]], %b
+; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32
+;
+; DISABLE: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
+; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i16 [[ZEXTLD]], %b
+; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32
+; OPTALL: store i32 [[RES]], i32* %q
+; OPTALL: ret
+define void @promoteMergeExtArgSExt(i8* %p, i32* %q, i16 %b) {
+entry:
+  %t = load i8, i8* %p
+  %ext = zext i8 %t to i16
+  %add = add nsw i16 %ext, %b
+  %a = icmp slt i8 %t, 20
+  br i1 %a, label %true, label %false
+true:
+  %s = sext i16 %add to i32
+  store i32 %s, i32* %q
+  ret void
+false:
+  ret void
+}
+
+; Check that we manage to catch all the extload opportunities that are exposed
+; by the different iterations of codegen prepare.
+; Moreover, check that we do not promote more than we need to.
+; Here is what is happening in this test (not necessarly in this order):
+; 1. We try to promote the operand of %sextadd.
+;    a. This creates one sext of %ld2 and one of %zextld
+;    b. The sext of %ld2 can be combine with %ld2, so we remove one sext but
+;       introduced one. This is fine with the current heuristic: neutral.
+;    => We have one zext of %zextld left and we created one sext of %ld2.
+; 2. We try to promote the operand of %sextaddza.
+;    a. This creates one sext of %zexta and one of %zextld
+;    b. The sext of %zexta does not lead to any load, it stays here, even if it
+;       could have been combine with the zext of %a.
+;    c. The sext of %zextld leads to %ld and can be combined with it. This is
+;       done by promoting %zextld. This is fine with the current heuristic:
+;       neutral.
+;    => We have created a new zext of %ld and we created one sext of %zexta.
+; 3. We try to promote the operand of %sextaddb.
+;    a. This creates one sext of %b and one of %zextld
+;    b. The sext of %b is a dead-end, nothing to be done.
+;    c. Same thing as 2.c. happens.
+;    => We have created a new zext of %ld and we created one sext of %b.
+; 4. We try to promote the operand of the zext of %zextld introduced in #1.
+;    a. Same thing as 2.c. happens.
+;    b. %zextld does not have any other uses. It is dead coded.
+;    => We have created a new zext of %ld and we removed a zext of %zextld and
+;       a zext of %ld.
+; Currently we do not try to reuse existing extensions, so in the end we have
+; 3 identical zext of %ld. The extensions will be CSE'ed by SDag.
+;
+; OPTALL-LABEL: @severalPromotions
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %addr1
+; OPT-NEXT: [[ZEXTLD1_1:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
+; OPT-NEXT: [[ZEXTLD1_2:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
+; OPT-NEXT: [[ZEXTLD1_3:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
+; OPT-NEXT: [[LD2:%[a-zA-Z_0-9-]+]] = load i32, i32* %addr2
+; OPT-NEXT: [[SEXTLD2:%[a-zA-Z_0-9-]+]] = sext i32 [[LD2]] to i64
+; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTLD2]], [[ZEXTLD1_1]]
+; We do not combine this one: see 2.b.
+; OPT-NEXT: [[ZEXTA:%[a-zA-Z_0-9-]+]] = zext i8 %a to i32
+; OPT-NEXT: [[SEXTZEXTA:%[a-zA-Z_0-9-]+]] = sext i32 [[ZEXTA]] to i64
+; OPT-NEXT: [[RESZA:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTZEXTA]], [[ZEXTLD1_3]]
+; OPT-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64
+; OPT-NEXT: [[RESB:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTB]], [[ZEXTLD1_2]]
+;
+; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32
+; DISABLE: [[RES:%[a-zA-Z_0-9-]+]]  = sext i32 [[ADD]] to i64
+; DISABLE: [[ADDZA:%[a-zA-Z_0-9-]+]] = add nsw i32
+; DISABLE: [[RESZA:%[a-zA-Z_0-9-]+]]  = sext i32 [[ADDZA]] to i64
+; DISABLE: [[ADDB:%[a-zA-Z_0-9-]+]] = add nsw i32
+; DISABLE: [[RESB:%[a-zA-Z_0-9-]+]]  = sext i32 [[ADDB]] to i64
+;
+; OPTALL: call void @dummy(i64 [[RES]], i64 [[RESZA]], i64 [[RESB]])
+; OPTALL: ret
+define void @severalPromotions(i8* %addr1, i32* %addr2, i8 %a, i32 %b) {
+  %ld = load i8, i8* %addr1
+  %zextld = zext i8 %ld to i32
+  %ld2 = load i32, i32* %addr2
+  %add = add nsw i32 %ld2, %zextld
+  %sextadd = sext i32 %add to i64
+  %zexta = zext i8 %a to i32
+  %addza = add nsw i32 %zexta, %zextld
+  %sextaddza = sext i32 %addza to i64
+  %addb = add nsw i32 %b, %zextld
+  %sextaddb = sext i32 %addb to i64
+  call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb)
+  ret void
+}
+
+declare void @dummy(i64, i64, i64)
+
+; Make sure we do not try to promote vector types since the type promotion
+; helper does not support them for now.
+; OPTALL-LABEL: @vectorPromotion
+; OPTALL: [[SHL:%[a-zA-Z_0-9-]+]] = shl nuw nsw <2 x i32> zeroinitializer, <i32 8, i32 8>
+; OPTALL: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext <2 x i32> [[SHL]] to <2 x i64>
+; OPTALL: ret
+define void @vectorPromotion() {
+entry:
+  %a = shl nuw nsw <2 x i32> zeroinitializer, <i32 8, i32 8>
+  %b = zext <2 x i32> %a to <2 x i64>
+  ret void
+}
+
+@a = common global i32 0, align 4
+@c = common global [2 x i32] zeroinitializer, align 4
+
+; Make sure we support promotion of operands that produces a Value as opposed
+; to an instruction.
+; This used to cause a crash.
+; OPTALL-LABEL: @promotionOfArgEndsUpInValue
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i16, i16* %addr
+;
+; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i16 [[LD]] to i32
+; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw nsw i32 [[SEXT]], zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @c, i64 0, i64 1), i32* @a) to i32)
+;
+; DISABLE-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw nsw i16 [[LD]], zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @c, i64 0, i64 1), i32* @a) to i16)
+; DISABLE-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32
+;
+; OPTALL-NEXT: ret i32 [[RES]]
+define i32 @promotionOfArgEndsUpInValue(i16* %addr) {
+entry:
+  %val = load i16, i16* %addr
+  %add = add nuw nsw i16 %val, zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @c, i64 0, i64 1), i32* @a) to i16)
+  %conv3 = sext i16 %add to i32
+  ret i32 %conv3
+}
+
+; Check that we see that one zext can be derived from the other for free.
+; OPTALL-LABEL: @promoteTwoArgZextWithSourceExtendedTwice
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+;
+; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
+; OPT-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; OPT-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
+; OPT-NEXT: [[RES64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], 12
+; OPT-NEXT: store i32 [[RES32]], i32* %addr
+; OPT-NEXT: store i64 [[RES64]], i64* %q
+;
+; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
+; DISABLE-NEXT: [[RES2_32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], 12
+; DISABLE-NEXT: store i32 [[RES32]], i32* %addr
+; DISABLE-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i32 [[RES2_32]] to i64
+; DISABLE-NEXT: store i64 [[ZEXT64]], i64* %q
+;
+; OPTALL-NEXT: ret void
+define void @promoteTwoArgZextWithSourceExtendedTwice(i8* %p, i64* %q, i32 %b, i32* %addr) {
+entry:
+  %t = load i8, i8* %p
+  %zextt = zext i8 %t to i32
+  %add = add nuw i32 %zextt, %b
+  %add2 = add nuw i32 %zextt, 12
+  store i32 %add, i32 *%addr
+  %s = zext i32 %add2 to i64
+  store i64 %s, i64* %q
+  ret void
+}
+
+; Check that we do not increase the cost of the code.
+; The input has one free zext and one free sext. If we would have promoted
+; all the way through the load we would end up with a free zext and a
+; non-free sext (of %b).
+; OPTALL-LABEL: @doNotPromoteFreeSExtFromAddrMode
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+;
+; STRESS-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
+; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64
+; STRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXT64]], [[SEXTB]]
+; STRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = trunc i64 [[IDX64]] to i32
+;
+; NONSTRESS-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; NONSTRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
+; NONSTRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
+;
+; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
+; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
+;
+; OPTALL-NEXT: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i32, i32* %addr, i64 [[IDX64]]
+; OPTALL-NEXT: store i32 [[RES32]], i32* [[GEP]]
+; OPTALL-NEXT: ret void
+define void @doNotPromoteFreeSExtFromAddrMode(i8* %p, i32 %b, i32* %addr) {
+entry:
+  %t = load i8, i8* %p
+  %zextt = zext i8 %t to i32
+  %add = add nsw i32 %zextt, %b
+  %idx64 = sext i32 %add to i64
+  %staddr = getelementptr inbounds i32, i32* %addr, i64 %idx64
+  store i32 %add, i32 *%staddr
+  ret void
+}
+
+; Check that we do not increase the cost of the code.
+; The input has one free zext and one free sext. If we would have promoted
+; all the way through the load we would end up with a free zext and a
+; non-free sext (of %b).
+; OPTALL-LABEL: @doNotPromoteFreeSExtFromAddrMode64
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+;
+; STRESS-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
+; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64
+; STRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXT64]], [[SEXTB]]
+;
+; NONSTRESS-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; NONSTRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
+; NONSTRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
+;
+; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
+; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
+;
+; OPTALL-NEXT: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i64, i64* %addr, i64 [[IDX64]]
+; OPTALL-NEXT: store i64 %stuff, i64* [[GEP]]
+; OPTALL-NEXT: ret void
+define void @doNotPromoteFreeSExtFromAddrMode64(i8* %p, i32 %b, i64* %addr, i64 %stuff) {
+entry:
+  %t = load i8, i8* %p
+  %zextt = zext i8 %t to i32
+  %add = add nsw i32 %zextt, %b
+  %idx64 = sext i32 %add to i64
+  %staddr = getelementptr inbounds i64, i64* %addr, i64 %idx64
+  store i64 %stuff, i64 *%staddr
+  ret void
+}
+
+; Check that we do not increase the cost of the code.
+; The input has one free zext and one free sext. If we would have promoted
+; all the way through the load we would end up with a free zext and a
+; non-free sext (of %b).
+; OPTALL-LABEL: @doNotPromoteFreeSExtFromAddrMode128
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+;
+; STRESS-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
+; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64
+; STRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXT64]], [[SEXTB]]
+;
+; NONSTRESS-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; NONSTRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
+; NONSTRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
+;
+; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
+; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
+;
+; OPTALL-NEXT: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i128, i128* %addr, i64 [[IDX64]]
+; OPTALL-NEXT: store i128 %stuff, i128* [[GEP]]
+; OPTALL-NEXT: ret void
+define void @doNotPromoteFreeSExtFromAddrMode128(i8* %p, i32 %b, i128* %addr, i128 %stuff) {
+entry:
+  %t = load i8, i8* %p
+  %zextt = zext i8 %t to i32
+  %add = add nsw i32 %zextt, %b
+  %idx64 = sext i32 %add to i64
+  %staddr = getelementptr inbounds i128, i128* %addr, i64 %idx64
+  store i128 %stuff, i128 *%staddr
+  ret void
+}
+
+
+; Check that we do not increase the cost of the code.
+; The input has one free zext and one free sext. If we would have promoted
+; all the way through the load we would end up with a free zext and a
+; non-free sext (of %b).
+; OPTALL-LABEL: @promoteSExtFromAddrMode256
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+;
+; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
+; OPT-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64
+; OPT-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXT64]], [[SEXTB]]
+;
+; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
+; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
+;
+; OPTALL-NEXT: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i256, i256* %addr, i64 [[IDX64]]
+; OPTALL-NEXT: store i256 %stuff, i256* [[GEP]]
+; OPTALL-NEXT: ret void
+define void @promoteSExtFromAddrMode256(i8* %p, i32 %b, i256* %addr, i256 %stuff) {
+entry:
+  %t = load i8, i8* %p
+  %zextt = zext i8 %t to i32
+  %add = add nsw i32 %zextt, %b
+  %idx64 = sext i32 %add to i64
+  %staddr = getelementptr inbounds i256, i256* %addr, i64 %idx64
+  store i256 %stuff, i256 *%staddr
+  ret void
+}
+
+; Check that we do not increase the cost of the code.
+; The input has one free zext and one free zext.
+; When we promote all the way through the load, we end up with
+; a free zext and a non-free zext (of %b).
+; However, the current target lowering says zext i32 to i64 is free
+; so the promotion happens because the cost did not change and may
+; expose more opportunities.
+; This would need to be fixed at some point.
+; OPTALL-LABEL: @doNotPromoteFreeZExtFromAddrMode
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+;
+; This transformation should really happen only for stress mode.
+; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
+; OPT-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i32 %b to i64
+; OPT-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], [[ZEXTB]]
+; OPT-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = trunc i64 [[IDX64]] to i32
+;
+; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
+; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = zext i32 [[RES32]] to i64
+;
+; OPTALL-NEXT: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i32, i32* %addr, i64 [[IDX64]]
+; OPTALL-NEXT: store i32 [[RES32]], i32* [[GEP]]
+; OPTALL-NEXT: ret void
+define void @doNotPromoteFreeZExtFromAddrMode(i8* %p, i32 %b, i32* %addr) {
+entry:
+  %t = load i8, i8* %p
+  %zextt = zext i8 %t to i32
+  %add = add nuw i32 %zextt, %b
+  %idx64 = zext i32 %add to i64
+  %staddr = getelementptr inbounds i32, i32* %addr, i64 %idx64
+  store i32 %add, i32 *%staddr
+  ret void
+}
+
+; OPTALL-LABEL: @doNotPromoteFreeSExtFromShift
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+;
+; STRESS-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
+; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64
+; STRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXT64]], [[SEXTB]]
+;
+; NONSTRESS-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; NONSTRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
+; NONSTRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
+;
+; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
+; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
+;
+; OPTALL-NEXT: [[RES64:%[a-zA-Z_0-9-]+]] = shl i64 [[IDX64]], 12
+; OPTALL-NEXT: ret i64 %staddr
+define i64 @doNotPromoteFreeSExtFromShift(i8* %p, i32 %b) {
+entry:
+  %t = load i8, i8* %p
+  %zextt = zext i8 %t to i32
+  %add = add nsw i32 %zextt, %b
+  %idx64 = sext i32 %add to i64
+  %staddr = shl i64 %idx64, 12
+  ret i64 %staddr
+}
+
+; Same comment as doNotPromoteFreeZExtFromAddrMode.
+; OPTALL-LABEL: @doNotPromoteFreeZExtFromShift
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+;
+; This transformation should really happen only for stress mode.
+; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
+; OPT-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i32 %b to i64
+; OPT-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], [[ZEXTB]]
+;
+; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
+; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = zext i32 [[RES32]] to i64
+;
+; OPTALL-NEXT: [[RES64:%[a-zA-Z_0-9-]+]] = shl i64 [[IDX64]], 12
+; OPTALL-NEXT: ret i64 %staddr
+define i64 @doNotPromoteFreeZExtFromShift(i8* %p, i32 %b) {
+entry:
+  %t = load i8, i8* %p
+  %zextt = zext i8 %t to i32
+  %add = add nuw i32 %zextt, %b
+  %idx64 = zext i32 %add to i64
+  %staddr = shl i64 %idx64, 12
+  ret i64 %staddr
+}
+
+; The input has one free zext and one non-free sext.
+; When we promote all the way through to the load, we end up with
+; a free zext, a free sext (%ld1), and a non-free sext (of %cst).
+; However, we when generate load pair and the free sext(%ld1) becomes
+; non-free. So technically, we trade a non-free sext to two non-free
+; sext.
+; This would need to be fixed at some point.
+; OPTALL-LABEL: @doNotPromoteBecauseOfPairedLoad
+; OPTALL: [[LD0:%[a-zA-Z_0-9-]+]] = load i32, i32* %p
+; OPTALL: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i32, i32* %p, i64 1
+; OPTALL: [[LD1:%[a-zA-Z_0-9-]+]] = load i32, i32* [[GEP]]
+;
+; This transformation should really happen only for stress mode.
+; OPT-NEXT: [[SEXTLD1:%[a-zA-Z_0-9-]+]] = sext i32 [[LD1]] to i64
+; OPT-NEXT: [[SEXTCST:%[a-zA-Z_0-9-]+]] = sext i32 %cst to i64
+; OPT-NEXT: [[SEXTRES:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTLD1]], [[SEXTCST]]
+;
+; DISABLE-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[LD1]], %cst
+; DISABLE-NEXT: [[SEXTRES:%[a-zA-Z_0-9-]+]] = sext i32 [[RES]] to i64
+;
+; OPTALL-NEXT: [[ZEXTLD0:%[a-zA-Z_0-9-]+]] = zext i32 [[LD0]] to i64
+; OPTALL-NEXT: [[FINAL:%[a-zA-Z_0-9-]+]] = add i64 [[SEXTRES]], [[ZEXTLD0]]
+; OPTALL-NEXT: ret i64 [[FINAL]]
+define i64 @doNotPromoteBecauseOfPairedLoad(i32* %p, i32 %cst) {
+  %ld0 = load i32, i32* %p
+  %idxLd1 = getelementptr inbounds i32, i32* %p, i64 1
+  %ld1 = load i32, i32* %idxLd1
+  %res = add nsw i32 %ld1, %cst
+  %sextres = sext i32 %res to i64
+  %zextLd0 = zext i32 %ld0 to i64
+  %final = add i64 %sextres, %zextLd0
+  ret i64 %final
+}
diff --git a/test/CodeGen/AArch64/arm64-collect-loh-garbage-crash.ll b/test/CodeGen/AArch64/arm64-collect-loh-garbage-crash.ll
index 81cee38420aa..e34ef39bcfec 100644
--- a/test/CodeGen/AArch64/arm64-collect-loh-garbage-crash.ll
+++ b/test/CodeGen/AArch64/arm64-collect-loh-garbage-crash.ll
@@ -22,13 +22,13 @@ define void @foo() {
 entry:
   br label %if.then83
 if.then83:                                        ; preds = %if.end81
-  %tmp = load %"class.H4ISP::H4ISPDevice"** @pH4ISPDevice, align 8
+  %tmp = load %"class.H4ISP::H4ISPDevice"*, %"class.H4ISP::H4ISPDevice"** @pH4ISPDevice, align 8
   %call84 = call i32 @_ZN5H4ISP11H4ISPDevice32ISP_SelectBestMIPIFrequencyIndexEjPj(%"class.H4ISP::H4ISPDevice"* %tmp) #19
   tail call void asm sideeffect "", "~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27}"()
-  %tmp2 = load %"class.H4ISP::H4ISPDevice"** @pH4ISPDevice, align 8
+  %tmp2 = load %"class.H4ISP::H4ISPDevice"*, %"class.H4ISP::H4ISPDevice"** @pH4ISPDevice, align 8
   tail call void asm sideeffect "", "~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x28}"()
-  %pCameraManager.i268 = getelementptr inbounds %"class.H4ISP::H4ISPDevice"* %tmp2, i64 0, i32 3
-  %tmp3 = load %"class.H4ISP::H4ISPCameraManager"** %pCameraManager.i268, align 8
+  %pCameraManager.i268 = getelementptr inbounds %"class.H4ISP::H4ISPDevice", %"class.H4ISP::H4ISPDevice"* %tmp2, i64 0, i32 3
+  %tmp3 = load %"class.H4ISP::H4ISPCameraManager"*, %"class.H4ISP::H4ISPCameraManager"** %pCameraManager.i268, align 8
   %tobool.i269 = icmp eq %"class.H4ISP::H4ISPCameraManager"* %tmp3, null
   br i1 %tobool.i269, label %if.then83, label %end
 end:
diff --git a/test/CodeGen/AArch64/arm64-collect-loh-str.ll b/test/CodeGen/AArch64/arm64-collect-loh-str.ll
index d7bc00e318f7..8889cb4bf52a 100644
--- a/test/CodeGen/AArch64/arm64-collect-loh-str.ll
+++ b/test/CodeGen/AArch64/arm64-collect-loh-str.ll
@@ -15,8 +15,8 @@
 ; CHECK-NOT: AdrpAddStr
 define i32 @pptp_wan_init() {
 entry:
-  store i32* null, i32** getelementptr inbounds (%struct.anon* @pptp_wan_head, i64 0, i32 0), align 8
-  store i32** getelementptr inbounds (%struct.anon* @pptp_wan_head, i64 0, i32 0), i32*** getelementptr inbounds (%struct.anon* @pptp_wan_head, i64 0, i32 1), align 8
+  store i32* null, i32** getelementptr inbounds (%struct.anon, %struct.anon* @pptp_wan_head, i64 0, i32 0), align 8
+  store i32** getelementptr inbounds (%struct.anon, %struct.anon* @pptp_wan_head, i64 0, i32 0), i32*** getelementptr inbounds (%struct.anon, %struct.anon* @pptp_wan_head, i64 0, i32 1), align 8
   ret i32 0
 }
 
diff --git a/test/CodeGen/AArch64/arm64-collect-loh.ll b/test/CodeGen/AArch64/arm64-collect-loh.ll
index 6d73daac6209..c0aa63cc4331 100644
--- a/test/CodeGen/AArch64/arm64-collect-loh.ll
+++ b/test/CodeGen/AArch64/arm64-collect-loh.ll
@@ -12,7 +12,7 @@
 ; Function Attrs: noinline nounwind ssp
 define void @foo(i32 %t) {
 entry:
-  %tmp = load i32* @a, align 4
+  %tmp = load i32, i32* @a, align 4
   %add = add nsw i32 %tmp, %t
   store i32 %add, i32* @a, align 4
   ret void
@@ -32,22 +32,22 @@ entry:
   br i1 %cmp, label %if.then, label %if.end4
 
 if.then:                                          ; preds = %entry
-  %tmp = load i32* @a, align 4
+  %tmp = load i32, i32* @a, align 4
   %add = add nsw i32 %tmp, %t
   %cmp1 = icmp sgt i32 %add, 12
   br i1 %cmp1, label %if.then2, label %if.end4
 
 if.then2:                                         ; preds = %if.then
   tail call void @foo(i32 %add)
-  %tmp1 = load i32* @a, align 4
+  %tmp1 = load i32, i32* @a, align 4
   br label %if.end4
 
 if.end4:                                          ; preds = %if.then2, %if.then, %entry
   %t.addr.0 = phi i32 [ %tmp1, %if.then2 ], [ %t, %if.then ], [ %t, %entry ]
-  %tmp2 = load i32* @b, align 4
+  %tmp2 = load i32, i32* @b, align 4
   %add5 = add nsw i32 %tmp2, %t.addr.0
   tail call void @foo(i32 %add5)
-  %tmp3 = load i32* @b, align 4
+  %tmp3 = load i32, i32* @b, align 4
   %add6 = add nsw i32 %tmp3, %t.addr.0
   ret i32 %add6
 }
diff --git a/test/CodeGen/AArch64/arm64-complex-copy-noneon.ll b/test/CodeGen/AArch64/arm64-complex-copy-noneon.ll
index f65b11612828..938bc62808f5 100644
--- a/test/CodeGen/AArch64/arm64-complex-copy-noneon.ll
+++ b/test/CodeGen/AArch64/arm64-complex-copy-noneon.ll
@@ -8,13 +8,13 @@ define void @store_combine() nounwind {
   %src = alloca { double, double }, align 8
   %dst = alloca { double, double }, align 8
 
-  %src.realp = getelementptr inbounds { double, double }* %src, i32 0, i32 0
-  %src.real = load double* %src.realp
-  %src.imagp = getelementptr inbounds { double, double }* %src, i32 0, i32 1
-  %src.imag = load double* %src.imagp
+  %src.realp = getelementptr inbounds { double, double }, { double, double }* %src, i32 0, i32 0
+  %src.real = load double, double* %src.realp
+  %src.imagp = getelementptr inbounds { double, double }, { double, double }* %src, i32 0, i32 1
+  %src.imag = load double, double* %src.imagp
 
-  %dst.realp = getelementptr inbounds { double, double }* %dst, i32 0, i32 0
-  %dst.imagp = getelementptr inbounds { double, double }* %dst, i32 0, i32 1
+  %dst.realp = getelementptr inbounds { double, double }, { double, double }* %dst, i32 0, i32 0
+  %dst.imagp = getelementptr inbounds { double, double }, { double, double }* %dst, i32 0, i32 1
   store double %src.real, double* %dst.realp
   store double %src.imag, double* %dst.imagp
   ret void
diff --git a/test/CodeGen/AArch64/arm64-const-addr.ll b/test/CodeGen/AArch64/arm64-const-addr.ll
index c55a9226cc7a..ffc153344d3a 100644
--- a/test/CodeGen/AArch64/arm64-const-addr.ll
+++ b/test/CodeGen/AArch64/arm64-const-addr.ll
@@ -10,13 +10,13 @@ define i32 @test1() nounwind {
 ; CHECK-NEXT:   ldp w9, w10, [x8, #4]
 ; CHECK:        ldr w8, [x8, #12]
   %at = inttoptr i64 68141056 to %T*
-  %o1 = getelementptr %T* %at, i32 0, i32 1
-  %t1 = load i32* %o1
-  %o2 = getelementptr %T* %at, i32 0, i32 2
-  %t2 = load i32* %o2
+  %o1 = getelementptr %T, %T* %at, i32 0, i32 1
+  %t1 = load i32, i32* %o1
+  %o2 = getelementptr %T, %T* %at, i32 0, i32 2
+  %t2 = load i32, i32* %o2
   %a1 = add i32 %t1, %t2
-  %o3 = getelementptr %T* %at, i32 0, i32 3
-  %t3 = load i32* %o3
+  %o3 = getelementptr %T, %T* %at, i32 0, i32 3
+  %t3 = load i32, i32* %o3
   %a2 = add i32 %a1, %t3
   ret i32 %a2
 }
diff --git a/test/CodeGen/AArch64/arm64-convert-v4f64.ll b/test/CodeGen/AArch64/arm64-convert-v4f64.ll
index 7123e5e0b235..b8da39910312 100644
--- a/test/CodeGen/AArch64/arm64-convert-v4f64.ll
+++ b/test/CodeGen/AArch64/arm64-convert-v4f64.ll
@@ -3,31 +3,64 @@
 
 define <4 x i16> @fptosi_v4f64_to_v4i16(<4 x double>* %ptr) {
 ; CHECK: fptosi_v4f64_to_v4i16
-; CHECK-DAG: fcvtzs  v[[LHS:[0-9]+]].2d, v1.2d
-; CHECK-DAG: fcvtzs  v[[RHS:[0-9]+]].2d, v0.2d
-; CHECK-DAG: xtn  v[[LHS_NA:[0-9]+]].2s, v[[LHS]].2d
-; CHECK-DAG: xtn  v[[RHS_NA:[0-9]+]].2s, v[[RHS]].2d
-; CHECK:     uzp1  v0.4h, v[[RHS_NA]].4h, v[[LHS_NA]].4h
-  %tmp1 = load <4 x double>* %ptr
+; CHECK-DAG: fcvtzs  v[[LHS:[0-9]+]].2d, v0.2d
+; CHECK-DAG: fcvtzs  v[[RHS:[0-9]+]].2d, v1.2d
+; CHECK-DAG: xtn  v[[MID:[0-9]+]].2s, v[[LHS]].2d
+; CHECK-DAG: xtn2  v[[MID]].4s, v[[RHS]].2d
+; CHECK:     xtn  v0.4h, v[[MID]].4s
+  %tmp1 = load <4 x double>, <4 x double>* %ptr
   %tmp2 = fptosi <4 x double> %tmp1 to <4 x i16>
   ret <4 x i16> %tmp2
 }
 
 define <8 x i8> @fptosi_v4f64_to_v4i8(<8 x double>* %ptr) {
 ; CHECK: fptosi_v4f64_to_v4i8
-; CHECK-DAG:  fcvtzs  v[[CONV3:[0-9]+]].2d, v3.2d
-; CHECK-DAG:  fcvtzs  v[[CONV2:[0-9]+]].2d, v2.2d
-; CHECK-DAG:  fcvtzs  v[[CONV1:[0-9]+]].2d, v1.2d
 ; CHECK-DAG:  fcvtzs  v[[CONV0:[0-9]+]].2d, v0.2d
-; CHECK-DAG:  xtn  v[[NA3:[0-9]+]].2s, v[[CONV3]].2d
+; CHECK-DAG:  fcvtzs  v[[CONV1:[0-9]+]].2d, v1.2d
+; CHECK-DAG:  fcvtzs  v[[CONV2:[0-9]+]].2d, v2.2d
+; CHECK-DAG:  fcvtzs  v[[CONV3:[0-9]+]].2d, v3.2d
 ; CHECK-DAG:  xtn  v[[NA2:[0-9]+]].2s, v[[CONV2]].2d
-; CHECK-DAG:  xtn  v[[NA1:[0-9]+]].2s, v[[CONV1]].2d
+; CHECK-DAG:  xtn2  v[[NA2]].4s, v[[CONV3]].2d
 ; CHECK-DAG:  xtn  v[[NA0:[0-9]+]].2s, v[[CONV0]].2d
-; CHECK-DAG:  uzp1  v[[TMP1:[0-9]+]].4h, v[[CONV2]].4h, v[[CONV3]].4h
-; CHECK-DAG:  uzp1  v[[TMP2:[0-9]+]].4h, v[[CONV0]].4h, v[[CONV1]].4h
-; CHECK:      uzp1  v0.8b, v[[TMP2]].8b, v[[TMP1]].8b
-  %tmp1 = load <8 x double>* %ptr
+; CHECK-DAG:  xtn2  v[[NA0]].4s, v[[CONV1]].2d
+; CHECK-DAG:  xtn  v[[TMP1:[0-9]+]].4h, v[[NA0]].4s
+; CHECK-DAG:  xtn2  v[[TMP1]].8h, v[[NA2]].4s
+; CHECK:      xtn  v0.8b, v[[TMP1]].8h
+  %tmp1 = load <8 x double>, <8 x double>* %ptr
   %tmp2 = fptosi <8 x double> %tmp1 to <8 x i8>
   ret <8 x i8> %tmp2
 }
 
+define <4 x half> @uitofp_v4i64_to_v4f16(<4 x i64>* %ptr) {
+; CHECK: uitofp_v4i64_to_v4f16
+; CHECK-DAG: ucvtf  v[[LHS:[0-9]+]].2d, v0.2d
+; CHECK-DAG: ucvtf  v[[RHS:[0-9]+]].2d, v1.2d
+; CHECK-DAG: fcvtn  v[[MID:[0-9]+]].2s, v[[LHS]].2d
+; CHECK-DAG: fcvtn2  v[[MID]].4s, v[[RHS]].2d
+; CHECK:     fcvtn  v0.4h, v[[MID]].4s
+  %tmp1 = load <4 x i64>, <4 x i64>* %ptr
+  %tmp2 = uitofp <4 x i64> %tmp1 to <4 x half>
+  ret <4 x half> %tmp2
+}
+
+define <4 x i16> @trunc_v4i64_to_v4i16(<4 x i64>* %ptr) {
+; CHECK: trunc_v4i64_to_v4i16
+; CHECK: xtn
+; CHECK: xtn2
+; CHECK: xtn
+  %tmp1 = load <4 x i64>, <4 x i64>* %ptr
+  %tmp2 = trunc <4 x i64> %tmp1 to <4 x i16>
+  ret <4 x i16> %tmp2
+}
+
+define <4 x i16> @fptoui_v4f64_to_v4i16(<4 x double>* %ptr) {
+; CHECK: fptoui_v4f64_to_v4i16
+; CHECK-DAG: fcvtzu  v[[LHS:[0-9]+]].2d, v0.2d
+; CHECK-DAG: fcvtzu  v[[RHS:[0-9]+]].2d, v1.2d
+; CHECK-DAG: xtn  v[[MID:[0-9]+]].2s, v[[LHS]].2d
+; CHECK-DAG: xtn2  v[[MID]].4s, v[[RHS]].2d
+; CHECK:     xtn  v0.4h, v[[MID]].4s
+  %tmp1 = load <4 x double>, <4 x double>* %ptr
+  %tmp2 = fptoui <4 x double> %tmp1 to <4 x i16>
+  ret <4 x i16> %tmp2
+}
diff --git a/test/CodeGen/AArch64/arm64-cse.ll b/test/CodeGen/AArch64/arm64-cse.ll
index b74ece8d288b..8d4bf5dbeb75 100644
--- a/test/CodeGen/AArch64/arm64-cse.ll
+++ b/test/CodeGen/AArch64/arm64-cse.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O3 < %s -aarch64-atomic-cfg-tidy=0 -aarch64-gep-opt=false | FileCheck %s
+; RUN: llc -O3 < %s -aarch64-atomic-cfg-tidy=0 -aarch64-gep-opt=false -verify-machineinstrs | FileCheck %s
 target triple = "arm64-apple-ios"
 
 ; rdar://12462006
@@ -15,7 +15,7 @@ entry:
 ; CHECK: sub
 ; CHECK-NOT: sub
 ; CHECK: ret
- %0 = load i32* %offset, align 4
+ %0 = load i32, i32* %offset, align 4
  %cmp = icmp slt i32 %0, %size
  %s = sub nsw i32 %0, %size
  br i1 %cmp, label %return, label %if.end
@@ -25,7 +25,7 @@ if.end:
  %s2 = sub nsw i32 %s, %size
  %s3 = sub nsw i32 %sub, %s2
  store i32 %s3, i32* %offset, align 4
- %add.ptr = getelementptr inbounds i8* %base, i32 %sub
+ %add.ptr = getelementptr inbounds i8, i8* %base, i32 %sub
  br label %return
 
 return:
@@ -43,14 +43,14 @@ entry:
 ; CHECK: b.lt
 ; CHECK-NOT: sub
 ; CHECK: ret
- %0 = load i32* %offset, align 4
+ %0 = load i32, i32* %offset, align 4
  %cmp = icmp slt i32 %0, 1
  br i1 %cmp, label %return, label %if.end
 
 if.end:
  %sub = sub nsw i32 %0, 1
  store i32 %sub, i32* %offset, align 4
- %add.ptr = getelementptr inbounds i8* %base, i32 %sub
+ %add.ptr = getelementptr inbounds i8, i8* %base, i32 %sub
  br label %return
 
 return:
diff --git a/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll b/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll
index 2eb6307b201b..37f3504be935 100644
--- a/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll
+++ b/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll
@@ -17,9 +17,9 @@ target triple = "arm64-apple-ios"
 ; CHECK-NOT: str
 define void @test(%"struct.SU"* nocapture %su) {
 entry:
-  %r1 = getelementptr inbounds %"struct.SU"* %su, i64 1, i32 5
+  %r1 = getelementptr inbounds %"struct.SU", %"struct.SU"* %su, i64 1, i32 5
   %r2 = bitcast %"struct.BO"* %r1 to i48*
-  %r3 = load i48* %r2, align 8
+  %r3 = load i48, i48* %r2, align 8
   %r4 = and i48 %r3, -4294967296
   %r5 = or i48 0, %r4
   store i48 %r5, i48* %r2, align 8
diff --git a/test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll b/test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll
index 0679014e59ae..09483ea09bd3 100644
--- a/test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll
+++ b/test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll
@@ -14,22 +14,22 @@
 ; CHECK: ret
 define void @test(%class.Complex* nocapture %out, i64 %out_start) {
 entry:
-  %arrayidx = getelementptr inbounds %class.Complex* %out, i64 %out_start
+  %arrayidx = getelementptr inbounds %class.Complex, %class.Complex* %out, i64 %out_start
   %0 = bitcast %class.Complex* %arrayidx to i64*
-  %1 = load i64* %0, align 4
+  %1 = load i64, i64* %0, align 4
   %t0.sroa.0.0.extract.trunc = trunc i64 %1 to i32
   %2 = bitcast i32 %t0.sroa.0.0.extract.trunc to float
   %t0.sroa.2.0.extract.shift = lshr i64 %1, 32
   %t0.sroa.2.0.extract.trunc = trunc i64 %t0.sroa.2.0.extract.shift to i32
   %3 = bitcast i32 %t0.sroa.2.0.extract.trunc to float
   %add = add i64 %out_start, 8
-  %arrayidx2 = getelementptr inbounds %class.Complex* %out, i64 %add
-  %i.i = getelementptr inbounds %class.Complex* %arrayidx2, i64 0, i32 0
-  %4 = load float* %i.i, align 4
+  %arrayidx2 = getelementptr inbounds %class.Complex, %class.Complex* %out, i64 %add
+  %i.i = getelementptr inbounds %class.Complex, %class.Complex* %arrayidx2, i64 0, i32 0
+  %4 = load float, float* %i.i, align 4
   %add.i = fadd float %4, %2
   %retval.sroa.0.0.vec.insert.i = insertelement <2 x float> undef, float %add.i, i32 0
-  %r.i = getelementptr inbounds %class.Complex* %arrayidx2, i64 0, i32 1
-  %5 = load float* %r.i, align 4
+  %r.i = getelementptr inbounds %class.Complex, %class.Complex* %arrayidx2, i64 0, i32 1
+  %5 = load float, float* %r.i, align 4
   %add5.i = fadd float %5, %3
   %retval.sroa.0.4.vec.insert.i = insertelement <2 x float> %retval.sroa.0.0.vec.insert.i, float %add5.i, i32 1
   %ref.tmp.sroa.0.0.cast = bitcast %class.Complex* %arrayidx to <2 x float>*
@@ -46,22 +46,22 @@ entry:
 ; CHECK: ret
 define void @test_int(%class.Complex_int* nocapture %out, i64 %out_start) {
 entry:
-  %arrayidx = getelementptr inbounds %class.Complex_int* %out, i64 %out_start
+  %arrayidx = getelementptr inbounds %class.Complex_int, %class.Complex_int* %out, i64 %out_start
   %0 = bitcast %class.Complex_int* %arrayidx to i64*
-  %1 = load i64* %0, align 4
+  %1 = load i64, i64* %0, align 4
   %t0.sroa.0.0.extract.trunc = trunc i64 %1 to i32
   %2 = bitcast i32 %t0.sroa.0.0.extract.trunc to i32
   %t0.sroa.2.0.extract.shift = lshr i64 %1, 32
   %t0.sroa.2.0.extract.trunc = trunc i64 %t0.sroa.2.0.extract.shift to i32
   %3 = bitcast i32 %t0.sroa.2.0.extract.trunc to i32
   %add = add i64 %out_start, 8
-  %arrayidx2 = getelementptr inbounds %class.Complex_int* %out, i64 %add
-  %i.i = getelementptr inbounds %class.Complex_int* %arrayidx2, i64 0, i32 0
-  %4 = load i32* %i.i, align 4
+  %arrayidx2 = getelementptr inbounds %class.Complex_int, %class.Complex_int* %out, i64 %add
+  %i.i = getelementptr inbounds %class.Complex_int, %class.Complex_int* %arrayidx2, i64 0, i32 0
+  %4 = load i32, i32* %i.i, align 4
   %add.i = add i32 %4, %2
   %retval.sroa.0.0.vec.insert.i = insertelement <2 x i32> undef, i32 %add.i, i32 0
-  %r.i = getelementptr inbounds %class.Complex_int* %arrayidx2, i64 0, i32 1
-  %5 = load i32* %r.i, align 4
+  %r.i = getelementptr inbounds %class.Complex_int, %class.Complex_int* %arrayidx2, i64 0, i32 1
+  %5 = load i32, i32* %r.i, align 4
   %add5.i = add i32 %5, %3
   %retval.sroa.0.4.vec.insert.i = insertelement <2 x i32> %retval.sroa.0.0.vec.insert.i, i32 %add5.i, i32 1
   %ref.tmp.sroa.0.0.cast = bitcast %class.Complex_int* %arrayidx to <2 x i32>*
@@ -78,22 +78,22 @@ entry:
 ; CHECK: ret
 define void @test_long(%class.Complex_long* nocapture %out, i64 %out_start) {
 entry:
-  %arrayidx = getelementptr inbounds %class.Complex_long* %out, i64 %out_start
+  %arrayidx = getelementptr inbounds %class.Complex_long, %class.Complex_long* %out, i64 %out_start
   %0 = bitcast %class.Complex_long* %arrayidx to i128*
-  %1 = load i128* %0, align 4
+  %1 = load i128, i128* %0, align 4
   %t0.sroa.0.0.extract.trunc = trunc i128 %1 to i64
   %2 = bitcast i64 %t0.sroa.0.0.extract.trunc to i64
   %t0.sroa.2.0.extract.shift = lshr i128 %1, 64
   %t0.sroa.2.0.extract.trunc = trunc i128 %t0.sroa.2.0.extract.shift to i64
   %3 = bitcast i64 %t0.sroa.2.0.extract.trunc to i64
   %add = add i64 %out_start, 8
-  %arrayidx2 = getelementptr inbounds %class.Complex_long* %out, i64 %add
-  %i.i = getelementptr inbounds %class.Complex_long* %arrayidx2, i32 0, i32 0
-  %4 = load i64* %i.i, align 4
+  %arrayidx2 = getelementptr inbounds %class.Complex_long, %class.Complex_long* %out, i64 %add
+  %i.i = getelementptr inbounds %class.Complex_long, %class.Complex_long* %arrayidx2, i32 0, i32 0
+  %4 = load i64, i64* %i.i, align 4
   %add.i = add i64 %4, %2
   %retval.sroa.0.0.vec.insert.i = insertelement <2 x i64> undef, i64 %add.i, i32 0
-  %r.i = getelementptr inbounds %class.Complex_long* %arrayidx2, i32 0, i32 1
-  %5 = load i64* %r.i, align 4
+  %r.i = getelementptr inbounds %class.Complex_long, %class.Complex_long* %arrayidx2, i32 0, i32 1
+  %5 = load i64, i64* %r.i, align 4
   %add5.i = add i64 %5, %3
   %retval.sroa.0.4.vec.insert.i = insertelement <2 x i64> %retval.sroa.0.0.vec.insert.i, i64 %add5.i, i32 1
   %ref.tmp.sroa.0.0.cast = bitcast %class.Complex_long* %arrayidx to <2 x i64>*
diff --git a/test/CodeGen/AArch64/arm64-dup.ll b/test/CodeGen/AArch64/arm64-dup.ll
index 0c56b46c4176..c6b7de366d23 100644
--- a/test/CodeGen/AArch64/arm64-dup.ll
+++ b/test/CodeGen/AArch64/arm64-dup.ll
@@ -165,7 +165,7 @@ define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
 define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vduplane8:
 ;CHECK: dup.8b
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
 	ret <8 x i8> %tmp2
 }
@@ -173,7 +173,7 @@ define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vduplane16:
 ;CHECK: dup.4h
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
 	ret <4 x i16> %tmp2
 }
@@ -181,7 +181,7 @@ define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vduplane32:
 ;CHECK: dup.2s
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
 	ret <2 x i32> %tmp2
 }
@@ -189,7 +189,7 @@ define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
 define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vduplanefloat:
 ;CHECK: dup.2s
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 >
 	ret <2 x float> %tmp2
 }
@@ -197,7 +197,7 @@ define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
 define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vduplaneQ8:
 ;CHECK: dup.16b
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
 	ret <16 x i8> %tmp2
 }
@@ -205,7 +205,7 @@ define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
 define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vduplaneQ16:
 ;CHECK: dup.8h
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
 	ret <8 x i16> %tmp2
 }
@@ -213,7 +213,7 @@ define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
 define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vduplaneQ32:
 ;CHECK: dup.4s
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
 	ret <4 x i32> %tmp2
 }
@@ -221,7 +221,7 @@ define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
 define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vduplaneQfloat:
 ;CHECK: dup.4s
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
 	ret <4 x float> %tmp2
 }
@@ -321,3 +321,40 @@ entry:
   %sub = sub <4 x i16> %a, %mul
   ret <4 x i16> %sub
 }
+
+; Also test the DUP path in the PerfectShuffle generator.
+
+; CHECK-LABEL: test_perfectshuffle_dupext_v4i16:
+; CHECK-NEXT: dup.4h v0, v0[0]
+; CHECK-NEXT: ext.8b v0, v0, v1, #4
+define <4 x i16> @test_perfectshuffle_dupext_v4i16(<4 x i16> %a, <4 x i16> %b) nounwind {
+  %r = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
+  ret <4 x i16> %r
+}
+
+; CHECK-LABEL: test_perfectshuffle_dupext_v4f16:
+; CHECK-NEXT: dup.4h v0, v0[0]
+; CHECK-NEXT: ext.8b v0, v0, v1, #4
+; CHECK-NEXT: ret
+define <4 x half> @test_perfectshuffle_dupext_v4f16(<4 x half> %a, <4 x half> %b) nounwind {
+  %r = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
+  ret <4 x half> %r
+}
+
+; CHECK-LABEL: test_perfectshuffle_dupext_v4i32:
+; CHECK-NEXT: dup.4s v0, v0[0]
+; CHECK-NEXT: ext.16b v0, v0, v1, #8
+; CHECK-NEXT: ret
+define <4 x i32> @test_perfectshuffle_dupext_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
+  %r = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
+  ret <4 x i32> %r
+}
+
+; CHECK-LABEL: test_perfectshuffle_dupext_v4f32:
+; CHECK-NEXT: dup.4s v0, v0[0]
+; CHECK-NEXT: ext.16b v0, v0, v1, #8
+; CHECK-NEXT: ret
+define <4 x float> @test_perfectshuffle_dupext_v4f32(<4 x float> %a, <4 x float> %b) nounwind {
+  %r = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
+  ret <4 x float> %r
+}
diff --git a/test/CodeGen/AArch64/arm64-early-ifcvt.ll b/test/CodeGen/AArch64/arm64-early-ifcvt.ll
index 44150c29aeb0..8164f46664b6 100644
--- a/test/CodeGen/AArch64/arm64-early-ifcvt.ll
+++ b/test/CodeGen/AArch64/arm64-early-ifcvt.ll
@@ -14,8 +14,8 @@ do.body:
   %min.0 = phi i32 [ 0, %entry ], [ %min.1, %do.cond ]
   %n.addr.0 = phi i32 [ %n, %entry ], [ %dec, %do.cond ]
   %p.addr.0 = phi i32* [ %p, %entry ], [ %incdec.ptr, %do.cond ]
-  %incdec.ptr = getelementptr inbounds i32* %p.addr.0, i64 1
-  %0 = load i32* %p.addr.0, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %p.addr.0, i64 1
+  %0 = load i32, i32* %p.addr.0, align 4
   %cmp = icmp sgt i32 %0, %max.0
   br i1 %cmp, label %do.cond, label %if.else
 
@@ -400,7 +400,7 @@ entry:
   br label %for.body
 
 for.body:
-  %x0 = load i32* undef, align 4
+  %x0 = load i32, i32* undef, align 4
   br i1 undef, label %if.then.i146, label %is_sbox.exit155
 
 if.then.i146:
@@ -412,8 +412,8 @@ if.then.i146:
 is_sbox.exit155:                                  ; preds = %if.then.i146, %for.body
   %seg_offset.0.i151 = phi i32 [ %add9.i145, %if.then.i146 ], [ undef, %for.body ]
   %idxprom15.i152 = sext i32 %seg_offset.0.i151 to i64
-  %arrayidx18.i154 = getelementptr inbounds i32* null, i64 %idxprom15.i152
-  %x1 = load i32* %arrayidx18.i154, align 4
+  %arrayidx18.i154 = getelementptr inbounds i32, i32* null, i64 %idxprom15.i152
+  %x1 = load i32, i32* %arrayidx18.i154, align 4
   br i1 undef, label %for.body51, label %for.body
 
 for.body51:                                       ; preds = %is_sbox.exit155
diff --git a/test/CodeGen/AArch64/arm64-elf-globals.ll b/test/CodeGen/AArch64/arm64-elf-globals.ll
index 4ed44e7c17af..b1d5524aee87 100644
--- a/test/CodeGen/AArch64/arm64-elf-globals.ll
+++ b/test/CodeGen/AArch64/arm64-elf-globals.ll
@@ -9,7 +9,7 @@
 @var64 = external global i64, align 8
 
 define i8 @test_i8(i8 %new) {
-  %val = load i8* @var8, align 1
+  %val = load i8, i8* @var8, align 1
   store i8 %new, i8* @var8
   ret i8 %val
 ; CHECK-LABEL: test_i8:
@@ -31,7 +31,7 @@ define i8 @test_i8(i8 %new) {
 }
 
 define i16 @test_i16(i16 %new) {
-  %val = load i16* @var16, align 2
+  %val = load i16, i16* @var16, align 2
   store i16 %new, i16* @var16
   ret i16 %val
 ; CHECK-LABEL: test_i16:
@@ -44,7 +44,7 @@ define i16 @test_i16(i16 %new) {
 }
 
 define i32 @test_i32(i32 %new) {
-  %val = load i32* @var32, align 4
+  %val = load i32, i32* @var32, align 4
   store i32 %new, i32* @var32
   ret i32 %val
 ; CHECK-LABEL: test_i32:
@@ -57,7 +57,7 @@ define i32 @test_i32(i32 %new) {
 }
 
 define i64 @test_i64(i64 %new) {
-  %val = load i64* @var64, align 8
+  %val = load i64, i64* @var64, align 8
   store i64 %new, i64* @var64
   ret i64 %val
 ; CHECK-LABEL: test_i64:
@@ -83,8 +83,8 @@ define i64* @test_addr() {
 @protectedvar = protected global i32 0, align 4
 
 define i32 @test_vis() {
-  %lhs = load i32* @hiddenvar, align 4
-  %rhs = load i32* @protectedvar, align 4
+  %lhs = load i32, i32* @hiddenvar, align 4
+  %rhs = load i32, i32* @protectedvar, align 4
   %ret = add i32 %lhs, %rhs
   ret i32 %ret
 ; CHECK-PIC: adrp {{x[0-9]+}}, hiddenvar
@@ -96,8 +96,8 @@ define i32 @test_vis() {
 @var_default = external global [2 x i32]
 
 define i32 @test_default_align() {
-  %addr = getelementptr [2 x i32]* @var_default, i32 0, i32 0
-  %val = load i32* %addr
+  %addr = getelementptr [2 x i32], [2 x i32]* @var_default, i32 0, i32 0
+  %val = load i32, i32* %addr
   ret i32 %val
 ; CHECK-LABEL: test_default_align:
 ; CHECK: adrp x[[HIREG:[0-9]+]], var_default
@@ -106,7 +106,7 @@ define i32 @test_default_align() {
 
 define i64 @test_default_unaligned() {
   %addr = bitcast [2 x i32]* @var_default to i64*
-  %val = load i64* %addr
+  %val = load i64, i64* %addr
   ret i64 %val
 ; CHECK-LABEL: test_default_unaligned:
 ; CHECK: adrp [[HIREG:x[0-9]+]], var_default
diff --git a/test/CodeGen/AArch64/arm64-ext.ll b/test/CodeGen/AArch64/arm64-ext.ll
index 67860de51b0f..8315ffcfb078 100644
--- a/test/CodeGen/AArch64/arm64-ext.ll
+++ b/test/CodeGen/AArch64/arm64-ext.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextd:
 ;CHECK: {{ext.8b.*#3}}
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextRd:
 ;CHECK: {{ext.8b.*#5}}
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
 	ret <8 x i8> %tmp3
 }
@@ -21,8 +21,8 @@ define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextq:
 ;CHECK: {{ext.16b.*3}}
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
 	ret <16 x i8> %tmp3
 }
@@ -30,8 +30,8 @@ define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextRq:
 ;CHECK: {{ext.16b.*7}}
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
 	ret <16 x i8> %tmp3
 }
@@ -39,8 +39,8 @@ define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: test_vextd16:
 ;CHECK: {{ext.8b.*#6}}
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
 	ret <4 x i16> %tmp3
 }
@@ -48,8 +48,8 @@ define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: test_vextq32:
 ;CHECK: {{ext.16b.*12}}
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
 	ret <4 x i32> %tmp3
 }
@@ -59,8 +59,8 @@ define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextd_undef:
 ;CHECK: {{ext.8b.*}}
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10>
 	ret <8 x i8> %tmp3
 }
@@ -68,8 +68,8 @@ define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <8 x i8> @test_vextd_undef2(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextd_undef2:
 ;CHECK: {{ext.8b.*#6}}
-  %tmp1 = load <8 x i8>* %A
-  %tmp2 = load <8 x i8>* %B
+  %tmp1 = load <8 x i8>, <8 x i8>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 5>
   ret <8 x i8> %tmp3
 }
@@ -77,8 +77,8 @@ define <8 x i8> @test_vextd_undef2(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextRq_undef:
 ;CHECK: {{ext.16b.*#7}}
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 undef, i32 undef, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6>
 	ret <16 x i8> %tmp3
 }
@@ -86,7 +86,7 @@ define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @test_vextRq_undef2(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: test_vextRq_undef2:
 ;CHECK: {{ext.16b.*#10}}
-  %tmp1 = load <8 x i16>* %A
+  %tmp1 = load <8 x i16>, <8 x i16>* %A
   %vext = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 4>
   ret <8 x i16> %vext;
 }
@@ -101,8 +101,8 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: test_interleaved:
 ;CHECK: ext.8b
 ;CHECK: zip1.4h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 3, i32 8, i32 5, i32 9>
         ret <4 x i16> %tmp3
 }
@@ -111,8 +111,8 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: test_undef:
 ;CHECK: zip1.4h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9>
         ret <4 x i16> %tmp3
 }
diff --git a/test/CodeGen/AArch64/arm64-extend.ll b/test/CodeGen/AArch64/arm64-extend.ll
index afcaca2c4920..0ef68f8a5301 100644
--- a/test/CodeGen/AArch64/arm64-extend.ll
+++ b/test/CodeGen/AArch64/arm64-extend.ll
@@ -8,8 +8,8 @@ define i64 @foo(i32 %i) {
 ; CHECK:  ldrsw x0, [x[[REG1]], w0, sxtw #2]
 ; CHECK:  ret
   %idxprom = sext i32 %i to i64
-  %arrayidx = getelementptr inbounds [0 x i32]* @array, i64 0, i64 %idxprom
-  %tmp1 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @array, i64 0, i64 %idxprom
+  %tmp1 = load i32, i32* %arrayidx, align 4
   %conv = sext i32 %tmp1 to i64
   ret i64 %conv
 }
diff --git a/test/CodeGen/AArch64/arm64-extern-weak.ll b/test/CodeGen/AArch64/arm64-extern-weak.ll
index 06bd9270ba47..020c07c739d9 100644
--- a/test/CodeGen/AArch64/arm64-extern-weak.ll
+++ b/test/CodeGen/AArch64/arm64-extern-weak.ll
@@ -30,7 +30,7 @@ define i32()* @foo() {
 @arr_var = extern_weak global [10 x i32]
 
 define i32* @bar() {
-  %addr = getelementptr [10 x i32]* @arr_var, i32 0, i32 5
+  %addr = getelementptr [10 x i32], [10 x i32]* @arr_var, i32 0, i32 5
 ; CHECK: adrp x[[ARR_VAR_HI:[0-9]+]], :got:arr_var
 ; CHECK: ldr [[ARR_VAR:x[0-9]+]], [x[[ARR_VAR_HI]], :got_lo12:arr_var]
 ; CHECK: add x0, [[ARR_VAR]], #20
diff --git a/test/CodeGen/AArch64/arm64-extload-knownzero.ll b/test/CodeGen/AArch64/arm64-extload-knownzero.ll
index 14e5fd310d7b..642af876423a 100644
--- a/test/CodeGen/AArch64/arm64-extload-knownzero.ll
+++ b/test/CodeGen/AArch64/arm64-extload-knownzero.ll
@@ -9,7 +9,7 @@ entry:
 bb1:
 ; CHECK: %bb1
 ; CHECK: ldrh [[REG:w[0-9]+]]
-  %tmp2 = load i16* %ptr, align 2
+  %tmp2 = load i16, i16* %ptr, align 2
   br label %bb2
 bb2:
 ; CHECK: %bb2
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll b/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll
index d81bc7cee114..e4dc948c4603 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
+; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
 
 @sortlist = common global [5001 x i32] zeroinitializer, align 16
 @sortlist2 = common global [5001 x i64] zeroinitializer, align 16
@@ -13,7 +13,7 @@ entry:
 ; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]]
 ; CHECK: ldr w0, [x[[REG3]]]
 ; CHECK: ret
-  %0 = load i32* getelementptr inbounds ([5001 x i32]* @sortlist, i32 0, i64 5000), align 4
+  %0 = load i32, i32* getelementptr inbounds ([5001 x i32], [5001 x i32]* @sortlist, i32 0, i64 5000), align 4
   ret i32 %0
 }
 
@@ -26,7 +26,7 @@ entry:
 ; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]]
 ; CHECK: ldr x0, [x[[REG3]]]
 ; CHECK: ret
-  %0 = load i64* getelementptr inbounds ([5001 x i64]* @sortlist2, i32 0, i64 5000), align 4
+  %0 = load i64, i64* getelementptr inbounds ([5001 x i64], [5001 x i64]* @sortlist2, i32 0, i64 5000), align 4
   ret i64 %0
 }
 
@@ -40,8 +40,8 @@ entry:
 ; CHECK: movz x[[REG:[0-9]+]], #0xb3a, lsl #32
 ; CHECK: movk x[[REG]], #0x73ce, lsl #16
 ; CHECK: movk x[[REG]], #0x2ff2
-  %0 = load i8** @pd2, align 8
-  %arrayidx = getelementptr inbounds i8* %0, i64 12345678901234
-  %1 = load i8* %arrayidx, align 1
+  %0 = load i8*, i8** @pd2, align 8
+  %arrayidx = getelementptr inbounds i8, i8* %0, i64 12345678901234
+  %1 = load i8, i8* %arrayidx, align 1
   ret i8 %1
 }
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll b/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll
index a8417027ce2d..a506607a0a5d 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll
@@ -1,5 +1,5 @@
 ; This test should cause the TargetMaterializeAlloca to be invoked
-; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
+; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
 
 %struct.S1Ty = type { i64 }
 %struct.S2Ty = type { %struct.S1Ty, %struct.S1Ty }
@@ -18,7 +18,7 @@ entry:
 ; CHECK: mov [[REG:x[0-9]+]], sp
 ; CHECK-NEXT: add x0, [[REG]], #8
   %E = alloca %struct.S2Ty, align 4
-  %B = getelementptr inbounds %struct.S2Ty* %E, i32 0, i32 1
+  %B = getelementptr inbounds %struct.S2Ty, %struct.S2Ty* %E, i32 0, i32 1
   call void @takeS1(%struct.S1Ty* %B)
   ret void
 }
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-br.ll b/test/CodeGen/AArch64/arm64-fast-isel-br.ll
index f896d8517382..0ef7b143df80 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel-br.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-br.ll
@@ -1,9 +1,9 @@
-; RUN: llc -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -mcpu=cyclone -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -O0 -fast-isel-abort=1 -mtriple=arm64-apple-darwin -mcpu=cyclone -verify-machineinstrs < %s | FileCheck %s
 
 define void @branch1() nounwind uwtable ssp {
   %x = alloca i32, align 4
   store i32 0, i32* %x, align 4
-  %1 = load i32* %x, align 4
+  %1 = load i32, i32* %x, align 4
   %2 = icmp ne i32 %1, 0
   br i1 %2, label %3, label %4
 
@@ -23,7 +23,7 @@ define void @branch2() nounwind uwtable ssp {
   store i32 1, i32* %y, align 4
   store i32 1, i32* %x, align 4
   store i32 0, i32* %z, align 4
-  %2 = load i32* %x, align 4
+  %2 = load i32, i32* %x, align 4
   %3 = icmp ne i32 %2, 0
   br i1 %3, label %4, label %5
 
@@ -32,12 +32,12 @@ define void @branch2() nounwind uwtable ssp {
   br label %14
 
 ; <label>:5                                       ; preds = %0
-  %6 = load i32* %y, align 4
+  %6 = load i32, i32* %y, align 4
   %7 = icmp ne i32 %6, 0
   br i1 %7, label %8, label %13
 
 ; <label>:8                                       ; preds = %5
-  %9 = load i32* %z, align 4
+  %9 = load i32, i32* %z, align 4
   %10 = icmp ne i32 %9, 0
   br i1 %10, label %11, label %12
 
@@ -53,7 +53,7 @@ define void @branch2() nounwind uwtable ssp {
   br label %14
 
 ; <label>:14                                      ; preds = %4, %11, %12, %13
-  %15 = load i32* %1
+  %15 = load i32, i32* %1
   ret void
 }
 
@@ -93,7 +93,7 @@ entry:
   store i16 %b, i16* %b.addr, align 2
   store i32 %c, i32* %c.addr, align 4
   store i64 %d, i64* %d.addr, align 8
-  %0 = load i16* %b.addr, align 2
+  %0 = load i16, i16* %b.addr, align 2
 ; CHECK: and w0, w0, #0x1
 ; CHECK: cmp w0, #0
 ; CHECK: b.eq LBB4_2
@@ -105,7 +105,7 @@ if.then:                                          ; preds = %entry
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
-  %1 = load i32* %c.addr, align 4
+  %1 = load i32, i32* %c.addr, align 4
 ; CHECK: and w[[REG:[0-9]+]], w{{[0-9]+}}, #0x1
 ; CHECK: cmp w[[REG]], #0
 ; CHECK: b.eq LBB4_4
@@ -117,7 +117,7 @@ if.then3:                                         ; preds = %if.end
   br label %if.end4
 
 if.end4:                                          ; preds = %if.then3, %if.end
-  %2 = load i64* %d.addr, align 8
+  %2 = load i64, i64* %d.addr, align 8
 ; CHECK: cmp w{{[0-9]+}}, #0
 ; CHECK: b.eq LBB4_6
   %conv5 = trunc i64 %2 to i1
@@ -128,7 +128,7 @@ if.then7:                                         ; preds = %if.end4
   br label %if.end8
 
 if.end8:                                          ; preds = %if.then7, %if.end4
-  %3 = load i8* %a.addr, align 1
+  %3 = load i8, i8* %a.addr, align 1
   ret i8 %3
 }
 
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-call.ll b/test/CodeGen/AArch64/arm64-fast-isel-call.ll
index f1e2c40a33c4..d6957f9191e2 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel-call.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-call.ll
@@ -1,6 +1,6 @@
-; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=small -verify-machineinstrs -mtriple=arm64-apple-darwin   < %s | FileCheck %s
-; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=large -verify-machineinstrs -mtriple=arm64-apple-darwin   < %s | FileCheck %s --check-prefix=LARGE
-; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=small -verify-machineinstrs -mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -O0 -fast-isel-abort=2 -code-model=small -verify-machineinstrs -mtriple=arm64-apple-darwin   < %s | FileCheck %s
+; RUN: llc -O0 -fast-isel-abort=2 -code-model=large -verify-machineinstrs -mtriple=arm64-apple-darwin   < %s | FileCheck %s --check-prefix=LARGE
+; RUN: llc -O0 -fast-isel-abort=2 -code-model=small -verify-machineinstrs -mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-BE
 
 define void @call0() nounwind {
 entry:
@@ -23,7 +23,7 @@ define i32 @call1(i32 %a) nounwind {
 entry:
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
-  %tmp = load i32* %a.addr, align 4
+  %tmp = load i32, i32* %a.addr, align 4
   ret i32 %tmp
 }
 
@@ -35,7 +35,7 @@ entry:
 ; CHECK-NEXT:  bl _call1
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
-  %tmp = load i32* %a.addr, align 4
+  %tmp = load i32, i32* %a.addr, align 4
   %call = call i32 @call1(i32 %tmp)
   ret i32 %call
 }
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll b/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll
index e5151847a598..1b6886523311 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin -mcpu=cyclone < %s | FileCheck %s
+; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin -mcpu=cyclone < %s | FileCheck %s
 
 ;; Test various conversions.
 define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
@@ -27,16 +27,16 @@ entry:
   store i16 %b, i16* %b.addr, align 2
   store i32 %c, i32* %c.addr, align 4
   store i64 %d, i64* %d.addr, align 8
-  %tmp = load i64* %d.addr, align 8
+  %tmp = load i64, i64* %d.addr, align 8
   %conv = trunc i64 %tmp to i32
   store i32 %conv, i32* %c.addr, align 4
-  %tmp1 = load i32* %c.addr, align 4
+  %tmp1 = load i32, i32* %c.addr, align 4
   %conv2 = trunc i32 %tmp1 to i16
   store i16 %conv2, i16* %b.addr, align 2
-  %tmp3 = load i16* %b.addr, align 2
+  %tmp3 = load i16, i16* %b.addr, align 2
   %conv4 = trunc i16 %tmp3 to i8
   store i8 %conv4, i8* %a.addr, align 1
-  %tmp5 = load i8* %a.addr, align 1
+  %tmp5 = load i8, i8* %a.addr, align 1
   %conv6 = zext i8 %tmp5 to i32
   ret i32 %conv6
 }
@@ -66,16 +66,16 @@ entry:
   store i16 %b, i16* %b.addr, align 2
   store i32 %c, i32* %c.addr, align 4
   store i64 %d, i64* %d.addr, align 8
-  %tmp = load i8* %a.addr, align 1
+  %tmp = load i8, i8* %a.addr, align 1
   %conv = zext i8 %tmp to i16
   store i16 %conv, i16* %b.addr, align 2
-  %tmp1 = load i16* %b.addr, align 2
+  %tmp1 = load i16, i16* %b.addr, align 2
   %conv2 = zext i16 %tmp1 to i32
   store i32 %conv2, i32* %c.addr, align 4
-  %tmp3 = load i32* %c.addr, align 4
+  %tmp3 = load i32, i32* %c.addr, align 4
   %conv4 = zext i32 %tmp3 to i64
   store i64 %conv4, i64* %d.addr, align 8
-  %tmp5 = load i64* %d.addr, align 8
+  %tmp5 = load i64, i64* %d.addr, align 8
   ret i64 %tmp5
 }
 
@@ -121,16 +121,16 @@ entry:
   store i16 %b, i16* %b.addr, align 2
   store i32 %c, i32* %c.addr, align 4
   store i64 %d, i64* %d.addr, align 8
-  %tmp = load i8* %a.addr, align 1
+  %tmp = load i8, i8* %a.addr, align 1
   %conv = sext i8 %tmp to i16
   store i16 %conv, i16* %b.addr, align 2
-  %tmp1 = load i16* %b.addr, align 2
+  %tmp1 = load i16, i16* %b.addr, align 2
   %conv2 = sext i16 %tmp1 to i32
   store i32 %conv2, i32* %c.addr, align 4
-  %tmp3 = load i32* %c.addr, align 4
+  %tmp3 = load i32, i32* %c.addr, align 4
   %conv4 = sext i32 %tmp3 to i64
   store i64 %conv4, i64* %d.addr, align 8
-  %tmp5 = load i64* %d.addr, align 8
+  %tmp5 = load i64, i64* %d.addr, align 8
   ret i64 %tmp5
 }
 
@@ -409,7 +409,7 @@ define void @stack_trunc() nounwind {
 ; CHECK: add  sp, sp, #16
   %a = alloca i8, align 1
   %b = alloca i64, align 8
-  %c = load i64* %b, align 8
+  %c = load i64, i64* %b, align 8
   %d = trunc i64 %c to i8
   store i8 %d, i8* %a, align 1
   ret void
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-fcmp.ll b/test/CodeGen/AArch64/arm64-fast-isel-fcmp.ll
index 111b6bd3d49e..c77949f996c3 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel-fcmp.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-fcmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
+; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
 
 define zeroext i1 @fcmp_float1(float %a) {
 ; CHECK-LABEL: fcmp_float1
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-gv.ll b/test/CodeGen/AArch64/arm64-fast-isel-gv.ll
index 1a4e8eab2d84..ab29824ccb60 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel-gv.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-gv.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
+; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
 
 ; Test load/store of global value from global offset table.
 @seed = common global i64 0, align 8
@@ -26,12 +26,12 @@ entry:
 ; CHECK: and  [[REG8:x[0-9]+]], [[REG7]], #0xffff
 ; CHECK: str  [[REG8]], {{\[}}[[REG1]]{{\]}}
 ; CHECK: ldr  {{x[0-9]+}}, {{\[}}[[REG1]]{{\]}}
-  %0 = load i64* @seed, align 8
+  %0 = load i64, i64* @seed, align 8
   %mul = mul nsw i64 %0, 1309
   %add = add nsw i64 %mul, 13849
   %and = and i64 %add, 65535
   store i64 %and, i64* @seed, align 8
-  %1 = load i64* @seed, align 8
+  %1 = load i64, i64* @seed, align 8
   %conv = trunc i64 %1 to i32
   ret i32 %conv
 }
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll b/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll
index 245c70e8905f..4bc02ebdd3e1 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
+; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
 
 define i32 @icmp_eq_imm(i32 %a) nounwind ssp {
 entry:
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-indirectbr.ll b/test/CodeGen/AArch64/arm64-fast-isel-indirectbr.ll
index a5f45249678b..cb54e4530a58 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel-indirectbr.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-indirectbr.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
+; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
 
 @fn.table = internal global [2 x i8*] [i8* blockaddress(@fn, %ZERO), i8* blockaddress(@fn, %ONE)], align 8
 
@@ -8,10 +8,10 @@ entry:
   %retval = alloca i32, align 4
   %target.addr = alloca i32, align 4
   store i32 %target, i32* %target.addr, align 4
-  %0 = load i32* %target.addr, align 4
+  %0 = load i32, i32* %target.addr, align 4
   %idxprom = zext i32 %0 to i64
-  %arrayidx = getelementptr inbounds [2 x i8*]* @fn.table, i32 0, i64 %idxprom
-  %1 = load i8** %arrayidx, align 8
+  %arrayidx = getelementptr inbounds [2 x i8*], [2 x i8*]* @fn.table, i32 0, i64 %idxprom
+  %1 = load i8*, i8** %arrayidx, align 8
   br label %indirectgoto
 
 ZERO:                                             ; preds = %indirectgoto
@@ -25,7 +25,7 @@ ONE:                                              ; preds = %indirectgoto
   br label %return
 
 return:                                           ; preds = %ONE, %ZERO
-  %2 = load i32* %retval
+  %2 = load i32, i32* %retval
   ret i32 %2
 
 indirectgoto:                                     ; preds = %entry
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll b/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll
index 9ac3e4431830..bb2889eaf4be 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=arm64-apple-ios < %s | FileCheck %s --check-prefix=ARM64
+; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=arm64-apple-ios < %s | FileCheck %s --check-prefix=ARM64
 
 @message = global [80 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 16
 @temp = common global [80 x i8] zeroinitializer, align 16
@@ -11,7 +11,7 @@ define void @t1() {
 ; ARM64: movz x2, #0x50
 ; ARM64: uxtb w1, w9
 ; ARM64: bl _memset
-  call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i8 0, i64 80, i32 16, i1 false)
+  call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i8 0, i64 80, i32 16, i1 false)
   ret void
 }
 
@@ -25,7 +25,7 @@ define void @t2() {
 ; ARM64: add x1, x8, _message@PAGEOFF
 ; ARM64: movz x2, #0x50
 ; ARM64: bl _memcpy
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 80, i32 16, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 80, i32 16, i1 false)
   ret void
 }
 
@@ -39,7 +39,7 @@ define void @t3() {
 ; ARM64: add x1, x8, _message@PAGEOFF
 ; ARM64: movz x2, #0x14
 ; ARM64: bl _memmove
-  call void @llvm.memmove.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 20, i32 16, i1 false)
+  call void @llvm.memmove.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 20, i32 16, i1 false)
   ret void
 }
 
@@ -58,7 +58,7 @@ define void @t4() {
 ; ARM64: ldrb w11, [x9, #16]
 ; ARM64: strb w11, [x8, #16]
 ; ARM64: ret
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 17, i32 16, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 17, i32 16, i1 false)
   ret void
 }
 
@@ -75,7 +75,7 @@ define void @t5() {
 ; ARM64: ldrb w11, [x9, #16]
 ; ARM64: strb w11, [x8, #16]
 ; ARM64: ret
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 17, i32 8, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 17, i32 8, i1 false)
   ret void
 }
 
@@ -92,7 +92,7 @@ define void @t6() {
 ; ARM64: ldrb w10, [x9, #8]
 ; ARM64: strb w10, [x8, #8]
 ; ARM64: ret
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 9, i32 4, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 9, i32 4, i1 false)
   ret void
 }
 
@@ -111,7 +111,7 @@ define void @t7() {
 ; ARM64: ldrb w10, [x9, #6]
 ; ARM64: strb w10, [x8, #6]
 ; ARM64: ret
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 7, i32 2, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 7, i32 2, i1 false)
   ret void
 }
 
@@ -130,7 +130,7 @@ define void @t8() {
 ; ARM64: ldrb w10, [x9, #3]
 ; ARM64: strb w10, [x8, #3]
 ; ARM64: ret
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 4, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 4, i32 1, i1 false)
   ret void
 }
 
@@ -142,7 +142,7 @@ define void @test_distant_memcpy(i8* %dst) {
 ; ARM64: ldrb [[BYTE:w[0-9]+]], [x[[ADDR]]]
 ; ARM64: strb [[BYTE]], [x0]
   %array = alloca i8, i32 8192
-  %elem = getelementptr i8* %array, i32 8000
+  %elem = getelementptr i8, i8* %array, i32 8000
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %elem, i64 1, i32 1, i1 false)
   ret void
 }
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll b/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll
index 1dea5d944be0..b5a08c148930 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
+; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
 
 ; Materialize using fmov
 define float @fmov_float1() {
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-rem.ll b/test/CodeGen/AArch64/arm64-fast-isel-rem.ll
index 26f9afaccee7..05aa96997b57 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel-rem.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-rem.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
-; RUN: llc %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t
+; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
+; RUN: llc %s -O0 -fast-isel-abort=1 -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t
 ; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA
 
 ; CHECK-SSA-LABEL: Machine code for function t1
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-ret.ll b/test/CodeGen/AArch64/arm64-fast-isel-ret.ll
index f84c75504f64..1f6a60e77cc3 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel-ret.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-ret.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
+; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
 
 ;; Test returns.
 define void @t0() nounwind ssp {
@@ -16,7 +16,7 @@ entry:
 ; CHECK: ret
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
-  %tmp = load i32* %a.addr, align 4
+  %tmp = load i32, i32* %a.addr, align 4
   ret i32 %tmp
 }
 
@@ -28,7 +28,7 @@ entry:
 ; CHECK: ret
   %a.addr = alloca i64, align 8
   store i64 %a, i64* %a.addr, align 8
-  %tmp = load i64* %a.addr, align 8
+  %tmp = load i64, i64* %a.addr, align 8
   ret i64 %tmp
 }
 
@@ -38,7 +38,7 @@ entry:
 ; CHECK: sxth	w0, w0
   %a.addr = alloca i16, align 1
   store i16 %a, i16* %a.addr, align 1
-  %0 = load i16* %a.addr, align 1
+  %0 = load i16, i16* %a.addr, align 1
   ret i16 %0
 }
 
@@ -48,7 +48,7 @@ entry:
 ; CHECK: sxtb	w0, w0
   %a.addr = alloca i8, align 1
   store i8 %a, i8* %a.addr, align 1
-  %0 = load i8* %a.addr, align 1
+  %0 = load i8, i8* %a.addr, align 1
   ret i8 %0
 }
 
@@ -58,6 +58,6 @@ entry:
 ; CHECK: and w0, w0, #0x1
   %a.addr = alloca i1, align 1
   store i1 %a, i1* %a.addr, align 1
-  %0 = load i1* %a.addr, align 1
+  %0 = load i1, i1* %a.addr, align 1
   ret i1 %0
 }
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-store.ll b/test/CodeGen/AArch64/arm64-fast-isel-store.ll
index 9494d5553010..47d4cdb3321b 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel-store.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-store.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=aarch64-unknown-unknown                             -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-unknown-unknown -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-unknown-unknown -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 define void @store_i8(i8* %a) {
 ; CHECK-LABEL: store_i8
diff --git a/test/CodeGen/AArch64/arm64-fast-isel.ll b/test/CodeGen/AArch64/arm64-fast-isel.ll
index 434994607c62..9f83a9c359a2 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
+; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
 
 define void @t0(i32 %a) nounwind {
 entry:
@@ -9,7 +9,7 @@ entry:
 ; CHECK: ret
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr
-  %tmp = load i32* %a.addr
+  %tmp = load i32, i32* %a.addr
   store i32 %tmp, i32* %a.addr
   ret void
 }
@@ -22,7 +22,7 @@ define void @t1(i64 %a) nounwind {
 ; CHECK: ret
   %a.addr = alloca i64, align 4
   store i64 %a, i64* %a.addr
-  %tmp = load i64* %a.addr
+  %tmp = load i64, i64* %a.addr
   store i64 %tmp, i64* %a.addr
   ret void
 }
@@ -39,7 +39,7 @@ entry:
 ; CHECK: ret
   %a.addr = alloca i1, align 1
   store i1 %a, i1* %a.addr, align 1
-  %0 = load i1* %a.addr, align 1
+  %0 = load i1, i1* %a.addr, align 1
   ret i1 %0
 }
 
@@ -48,8 +48,8 @@ entry:
 ; CHECK-LABEL: t2:
 ; CHECK: ldur w0, [x0, #-4]
 ; CHECK: ret
-  %0 = getelementptr i32 *%ptr, i32 -1
-  %1 = load i32* %0, align 4
+  %0 = getelementptr i32, i32 *%ptr, i32 -1
+  %1 = load i32, i32* %0, align 4
   ret i32 %1
 }
 
@@ -58,8 +58,8 @@ entry:
 ; CHECK-LABEL: t3:
 ; CHECK: ldur w0, [x0, #-256]
 ; CHECK: ret
-  %0 = getelementptr i32 *%ptr, i32 -64
-  %1 = load i32* %0, align 4
+  %0 = getelementptr i32, i32 *%ptr, i32 -64
+  %1 = load i32, i32* %0, align 4
   ret i32 %1
 }
 
@@ -68,7 +68,7 @@ entry:
 ; CHECK-LABEL: t4:
 ; CHECK: stur wzr, [x0, #-4]
 ; CHECK: ret
-  %0 = getelementptr i32 *%ptr, i32 -1
+  %0 = getelementptr i32, i32 *%ptr, i32 -1
   store i32 0, i32* %0, align 4
   ret void
 }
@@ -78,7 +78,7 @@ entry:
 ; CHECK-LABEL: t5:
 ; CHECK: stur wzr, [x0, #-256]
 ; CHECK: ret
-  %0 = getelementptr i32 *%ptr, i32 -64
+  %0 = getelementptr i32, i32 *%ptr, i32 -64
   store i32 0, i32* %0, align 4
   ret void
 }
@@ -91,3 +91,45 @@ define void @t6() nounwind {
 }
 
 declare void @llvm.trap() nounwind
+
+define void @ands(i32* %addr) {
+; CHECK-LABEL: ands:
+; CHECK: tst [[COND:w[0-9]+]], #0x1
+; CHECK-NEXT: csel [[COND]],
+entry:
+  %cond91 = select i1 undef, i32 1, i32 2
+  store i32 %cond91, i32* %addr, align 4
+  ret void
+}
+
+define i64 @mul_umul(i64 %arg) {
+; CHECK-LABEL: mul_umul:
+; CHECK: mul x{{[0-9]+}}, [[ARG1:x[0-9]+]], [[ARG2:x[0-9]+]]
+; CHECK-NEXT: umulh x{{[0-9]+}}, [[ARG1]], [[ARG2]]
+entry:
+  %sub.ptr.div = sdiv exact i64 %arg, 8
+  %tmp = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %sub.ptr.div, i64 8)
+  %tmp1 = extractvalue { i64, i1 } %tmp, 0
+  ret i64 %tmp1
+}
+
+declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)
+
+define void @logicalReg() {
+; Make sure we generate a logical reg = reg, reg instruction without any
+; machine verifier errors.
+; CHECK-LABEL: logicalReg:
+; CHECK: orr w{{[0-9]+}}, w{{[0-9]+}}, w{{[0-9]+}}
+; CHECK: ret
+entry:
+  br i1 undef, label %cond.end, label %cond.false
+
+cond.false:
+  %cond = select i1 undef, i1 true, i1 false
+  br label %cond.end
+
+cond.end:
+  %cond13 = phi i1 [ %cond, %cond.false ], [ true, %entry ]
+  ret void
+}
+
diff --git a/test/CodeGen/AArch64/arm64-fastisel-gep-promote-before-add.ll b/test/CodeGen/AArch64/arm64-fastisel-gep-promote-before-add.ll
index af9fe0561737..8268bcff1f80 100644
--- a/test/CodeGen/AArch64/arm64-fastisel-gep-promote-before-add.ll
+++ b/test/CodeGen/AArch64/arm64-fastisel-gep-promote-before-add.ll
@@ -6,13 +6,13 @@ define zeroext i8 @gep_promotion(i8* %ptr) nounwind uwtable ssp {
 entry:
   %ptr.addr = alloca i8*, align 8
   %add = add i8 64, 64 ; 0x40 + 0x40
-  %0 = load i8** %ptr.addr, align 8
+  %0 = load i8*, i8** %ptr.addr, align 8
 
   ; CHECK-LABEL: _gep_promotion:
   ; CHECK: ldrb {{[a-z][0-9]+}}, {{\[[a-z][0-9]+\]}}
-  %arrayidx = getelementptr inbounds i8* %0, i8 %add
+  %arrayidx = getelementptr inbounds i8, i8* %0, i8 %add
 
-  %1 = load i8* %arrayidx, align 1
+  %1 = load i8, i8* %arrayidx, align 1
   ret i8 %1
 }
 
diff --git a/test/CodeGen/AArch64/arm64-fcopysign.ll b/test/CodeGen/AArch64/arm64-fcopysign.ll
index 66241df9444c..feffd41f002a 100644
--- a/test/CodeGen/AArch64/arm64-fcopysign.ll
+++ b/test/CodeGen/AArch64/arm64-fcopysign.ll
@@ -39,7 +39,7 @@ entry:
 ; CHECK: fcvt s0, d0
 ; CHECK: movi.4s v[[CONST:[0-9]+]], #0x80, lsl #24
 ; CHECK: bit.16b v{{[0-9]+}}, v0, v[[CONST]]
-  %0 = tail call double (...)* @bar() nounwind
+  %0 = tail call double (...) @bar() nounwind
   %1 = fptrunc double %0 to float
   %2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone
   %3 = fadd float %1, %2
diff --git a/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll b/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
index e51c38b2b95e..e41e19e50eea 100644
--- a/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
+++ b/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
@@ -6,7 +6,7 @@
 ; rdar://11855286
 define double @foo0(<2 x i64> %a) nounwind {
 ; CHECK:  scvtf.2d  [[REG:v[0-9]+]], v0, #9
-; CHECK-NEXT:  ins.d v0[0], [[REG]][1]
+; CHECK-NEXT:  mov  d0, [[REG]][1]
   %vecext = extractelement <2 x i64> %a, i32 1
   %fcvt_n = tail call double @llvm.aarch64.neon.vcvtfxs2fp.f64.i64(i64 %vecext, i32 9)
   ret double %fcvt_n
diff --git a/test/CodeGen/AArch64/arm64-fmax.ll b/test/CodeGen/AArch64/arm64-fmax.ll
index 94b745437bd3..ea281528b84c 100644
--- a/test/CodeGen/AArch64/arm64-fmax.ll
+++ b/test/CodeGen/AArch64/arm64-fmax.ll
@@ -1,29 +1,49 @@
 ; RUN: llc -march=arm64 -enable-no-nans-fp-math < %s | FileCheck %s
+; RUN: llc -march=arm64 < %s | FileCheck %s --check-prefix=CHECK-SAFE
 
-define double @test_direct(float %in) #1 {
+define double @test_direct(float %in) {
 ; CHECK-LABEL: test_direct:
+; CHECK-SAFE-LABEL: test_direct:
   %cmp = fcmp olt float %in, 0.000000e+00
   %longer = fpext float %in to double
   %val = select i1 %cmp, double 0.000000e+00, double %longer
   ret double %val
 
 ; CHECK: fmax
+; CHECK-SAFE: fmax
 }
 
-define double @test_cross(float %in) #1 {
+define double @test_cross(float %in) {
 ; CHECK-LABEL: test_cross:
+; CHECK-SAFE-LABEL: test_cross:
+  %cmp = fcmp ult float %in, 0.000000e+00
+  %longer = fpext float %in to double
+  %val = select i1 %cmp, double %longer, double 0.000000e+00
+  ret double %val
+
+; CHECK: fmin
+; CHECK-SAFE: fmin
+}
+
+; Same as previous, but with ordered comparison;
+; can't be converted in safe-math mode.
+define double @test_cross_fail_nan(float %in) {
+; CHECK-LABEL: test_cross_fail_nan:
+; CHECK-SAFE-LABEL: test_cross_fail_nan:
   %cmp = fcmp olt float %in, 0.000000e+00
   %longer = fpext float %in to double
   %val = select i1 %cmp, double %longer, double 0.000000e+00
   ret double %val
 
 ; CHECK: fmin
+; CHECK-SAFE: fcsel d0, d1, d0, mi
 }
 
 ; This isn't a min or a max, but passes the first condition for swapping the
 ; results. Make sure they're put back before we resort to the normal fcsel.
 define float @test_cross_fail(float %lhs, float %rhs) {
 ; CHECK-LABEL: test_cross_fail:
+; CHECK-SAFE-LABEL: test_cross_fail:
   %tst = fcmp une float %lhs, %rhs
   %res = select i1 %tst, float %rhs, float %lhs
   ret float %res
@@ -31,4 +51,12 @@ define float @test_cross_fail(float %lhs, float %rhs) {
   ; The register allocator would have to decide to be deliberately obtuse before
   ; other register were used.
 ; CHECK: fcsel s0, s1, s0, ne
-}
\ No newline at end of file
+; CHECK-SAFE: fcsel s0, s1, s0, ne
+}
+
+; Make sure the transformation isn't triggered for integers
+define i64 @test_integer(i64  %in) {
+  %cmp = icmp slt i64 %in, 0
+  %val = select i1 %cmp, i64 0, i64 %in
+  ret i64 %val
+}
diff --git a/test/CodeGen/AArch64/arm64-fmuladd.ll b/test/CodeGen/AArch64/arm64-fmuladd.ll
index 6c5eecabd755..cfc8b5fe65ef 100644
--- a/test/CodeGen/AArch64/arm64-fmuladd.ll
+++ b/test/CodeGen/AArch64/arm64-fmuladd.ll
@@ -4,9 +4,9 @@ define float @test_f32(float* %A, float* %B, float* %C) nounwind {
 ;CHECK-LABEL: test_f32:
 ;CHECK: fmadd
 ;CHECK-NOT: fmadd
-  %tmp1 = load float* %A
-  %tmp2 = load float* %B
-  %tmp3 = load float* %C
+  %tmp1 = load float, float* %A
+  %tmp2 = load float, float* %B
+  %tmp3 = load float, float* %C
   %tmp4 = call float @llvm.fmuladd.f32(float %tmp1, float %tmp2, float %tmp3)
   ret float %tmp4
 }
@@ -15,9 +15,9 @@ define <2 x float> @test_v2f32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C
 ;CHECK-LABEL: test_v2f32:
 ;CHECK: fmla.2s
 ;CHECK-NOT: fmla.2s
-  %tmp1 = load <2 x float>* %A
-  %tmp2 = load <2 x float>* %B
-  %tmp3 = load <2 x float>* %C
+  %tmp1 = load <2 x float>, <2 x float>* %A
+  %tmp2 = load <2 x float>, <2 x float>* %B
+  %tmp3 = load <2 x float>, <2 x float>* %C
   %tmp4 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2, <2 x float> %tmp3)
   ret <2 x float> %tmp4
 }
@@ -26,9 +26,9 @@ define <4 x float> @test_v4f32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C
 ;CHECK-LABEL: test_v4f32:
 ;CHECK: fmla.4s
 ;CHECK-NOT: fmla.4s
-  %tmp1 = load <4 x float>* %A
-  %tmp2 = load <4 x float>* %B
-  %tmp3 = load <4 x float>* %C
+  %tmp1 = load <4 x float>, <4 x float>* %A
+  %tmp2 = load <4 x float>, <4 x float>* %B
+  %tmp3 = load <4 x float>, <4 x float>* %C
   %tmp4 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %tmp1, <4 x float> %tmp2, <4 x float> %tmp3)
   ret <4 x float> %tmp4
 }
@@ -38,9 +38,9 @@ define <8 x float> @test_v8f32(<8 x float>* %A, <8 x float>* %B, <8 x float>* %C
 ;CHECK: fmla.4s
 ;CHECK: fmla.4s
 ;CHECK-NOT: fmla.4s
-  %tmp1 = load <8 x float>* %A
-  %tmp2 = load <8 x float>* %B
-  %tmp3 = load <8 x float>* %C
+  %tmp1 = load <8 x float>, <8 x float>* %A
+  %tmp2 = load <8 x float>, <8 x float>* %B
+  %tmp3 = load <8 x float>, <8 x float>* %C
   %tmp4 = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> %tmp1, <8 x float> %tmp2, <8 x float> %tmp3)
   ret <8 x float> %tmp4
 }
@@ -49,9 +49,9 @@ define double @test_f64(double* %A, double* %B, double* %C) nounwind {
 ;CHECK-LABEL: test_f64:
 ;CHECK: fmadd
 ;CHECK-NOT: fmadd
-  %tmp1 = load double* %A
-  %tmp2 = load double* %B
-  %tmp3 = load double* %C
+  %tmp1 = load double, double* %A
+  %tmp2 = load double, double* %B
+  %tmp3 = load double, double* %C
   %tmp4 = call double @llvm.fmuladd.f64(double %tmp1, double %tmp2, double %tmp3)
   ret double %tmp4
 }
@@ -60,9 +60,9 @@ define <2 x double> @test_v2f64(<2 x double>* %A, <2 x double>* %B, <2 x double>
 ;CHECK-LABEL: test_v2f64:
 ;CHECK: fmla.2d
 ;CHECK-NOT: fmla.2d
-  %tmp1 = load <2 x double>* %A
-  %tmp2 = load <2 x double>* %B
-  %tmp3 = load <2 x double>* %C
+  %tmp1 = load <2 x double>, <2 x double>* %A
+  %tmp2 = load <2 x double>, <2 x double>* %B
+  %tmp3 = load <2 x double>, <2 x double>* %C
   %tmp4 = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %tmp1, <2 x double> %tmp2, <2 x double> %tmp3)
   ret <2 x double> %tmp4
 }
@@ -72,9 +72,9 @@ define <4 x double> @test_v4f64(<4 x double>* %A, <4 x double>* %B, <4 x double>
 ;CHECK: fmla.2d
 ;CHECK: fmla.2d
 ;CHECK-NOT: fmla.2d
-  %tmp1 = load <4 x double>* %A
-  %tmp2 = load <4 x double>* %B
-  %tmp3 = load <4 x double>* %C
+  %tmp1 = load <4 x double>, <4 x double>* %A
+  %tmp2 = load <4 x double>, <4 x double>* %B
+  %tmp3 = load <4 x double>, <4 x double>* %C
   %tmp4 = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> %tmp1, <4 x double> %tmp2, <4 x double> %tmp3)
   ret <4 x double> %tmp4
 }
diff --git a/test/CodeGen/AArch64/arm64-fold-address.ll b/test/CodeGen/AArch64/arm64-fold-address.ll
index 1f0b918ecd9c..6d2ea17d3424 100644
--- a/test/CodeGen/AArch64/arm64-fold-address.ll
+++ b/test/CodeGen/AArch64/arm64-fold-address.ll
@@ -14,23 +14,23 @@ entry:
 ; CHECK: ldp d0, d1, [x[[REG]]]
 ; CHECK: ldp d2, d3, [x[[REG]], #16]
 ; CHECK: ret
-  %ivar = load i64* @"OBJC_IVAR_$_UIScreen._bounds", align 8, !invariant.load !4
+  %ivar = load i64, i64* @"OBJC_IVAR_$_UIScreen._bounds", align 8, !invariant.load !4
   %0 = bitcast %0* %self to i8*
-  %add.ptr = getelementptr inbounds i8* %0, i64 %ivar
+  %add.ptr = getelementptr inbounds i8, i8* %0, i64 %ivar
   %add.ptr10.0 = bitcast i8* %add.ptr to double*
-  %tmp11 = load double* %add.ptr10.0, align 8
+  %tmp11 = load double, double* %add.ptr10.0, align 8
   %add.ptr.sum = add i64 %ivar, 8
-  %add.ptr10.1 = getelementptr inbounds i8* %0, i64 %add.ptr.sum
+  %add.ptr10.1 = getelementptr inbounds i8, i8* %0, i64 %add.ptr.sum
   %1 = bitcast i8* %add.ptr10.1 to double*
-  %tmp12 = load double* %1, align 8
+  %tmp12 = load double, double* %1, align 8
   %add.ptr.sum17 = add i64 %ivar, 16
-  %add.ptr4.1 = getelementptr inbounds i8* %0, i64 %add.ptr.sum17
+  %add.ptr4.1 = getelementptr inbounds i8, i8* %0, i64 %add.ptr.sum17
   %add.ptr4.1.0 = bitcast i8* %add.ptr4.1 to double*
-  %tmp = load double* %add.ptr4.1.0, align 8
+  %tmp = load double, double* %add.ptr4.1.0, align 8
   %add.ptr4.1.sum = add i64 %ivar, 24
-  %add.ptr4.1.1 = getelementptr inbounds i8* %0, i64 %add.ptr4.1.sum
+  %add.ptr4.1.1 = getelementptr inbounds i8, i8* %0, i64 %add.ptr4.1.sum
   %2 = bitcast i8* %add.ptr4.1.1 to double*
-  %tmp5 = load double* %2, align 8
+  %tmp5 = load double, double* %2, align 8
   %insert14 = insertvalue %struct.CGPoint undef, double %tmp11, 0
   %insert16 = insertvalue %struct.CGPoint %insert14, double %tmp12, 1
   %insert = insertvalue %struct.CGRect undef, %struct.CGPoint %insert16, 0
@@ -46,20 +46,20 @@ entry:
 ; CHECK: ldr d0, [x0, x{{[0-9]+}}]
 ; CHECK-NOT: add x0, x0, x1
 ; CHECK: ret
-  %ivar = load i64* @"OBJC_IVAR_$_UIScreen._bounds", align 8, !invariant.load !4
+  %ivar = load i64, i64* @"OBJC_IVAR_$_UIScreen._bounds", align 8, !invariant.load !4
   %0 = bitcast %0* %self to i8*
-  %add.ptr = getelementptr inbounds i8* %0, i64 %ivar
+  %add.ptr = getelementptr inbounds i8, i8* %0, i64 %ivar
   %add.ptr10.0 = bitcast i8* %add.ptr to double*
-  %tmp11 = load double* %add.ptr10.0, align 8
-  %add.ptr10.1 = getelementptr inbounds i8* %0, i64 %ivar
+  %tmp11 = load double, double* %add.ptr10.0, align 8
+  %add.ptr10.1 = getelementptr inbounds i8, i8* %0, i64 %ivar
   %1 = bitcast i8* %add.ptr10.1 to double*
-  %tmp12 = load double* %1, align 8
-  %add.ptr4.1 = getelementptr inbounds i8* %0, i64 %ivar
+  %tmp12 = load double, double* %1, align 8
+  %add.ptr4.1 = getelementptr inbounds i8, i8* %0, i64 %ivar
   %add.ptr4.1.0 = bitcast i8* %add.ptr4.1 to double*
-  %tmp = load double* %add.ptr4.1.0, align 8
-  %add.ptr4.1.1 = getelementptr inbounds i8* %0, i64 %ivar
+  %tmp = load double, double* %add.ptr4.1.0, align 8
+  %add.ptr4.1.1 = getelementptr inbounds i8, i8* %0, i64 %ivar
   %2 = bitcast i8* %add.ptr4.1.1 to double*
-  %tmp5 = load double* %2, align 8
+  %tmp5 = load double, double* %2, align 8
   %insert14 = insertvalue %struct.CGPoint undef, double %tmp11, 0
   %insert16 = insertvalue %struct.CGPoint %insert14, double %tmp12, 1
   %insert = insertvalue %struct.CGRect undef, %struct.CGPoint %insert16, 0
diff --git a/test/CodeGen/AArch64/arm64-fold-lsl.ll b/test/CodeGen/AArch64/arm64-fold-lsl.ll
index ec65e467e37d..e1acd6fdea74 100644
--- a/test/CodeGen/AArch64/arm64-fold-lsl.ll
+++ b/test/CodeGen/AArch64/arm64-fold-lsl.ll
@@ -13,8 +13,8 @@ define i16 @load_halfword(%struct.a* %ctx, i32 %xor72) nounwind {
   %shr81 = lshr i32 %xor72, 9
   %conv82 = zext i32 %shr81 to i64
   %idxprom83 = and i64 %conv82, 255
-  %arrayidx86 = getelementptr inbounds %struct.a* %ctx, i64 0, i64 %idxprom83
-  %result = load i16* %arrayidx86, align 2
+  %arrayidx86 = getelementptr inbounds %struct.a, %struct.a* %ctx, i64 0, i64 %idxprom83
+  %result = load i16, i16* %arrayidx86, align 2
   ret i16 %result
 }
 
@@ -25,8 +25,8 @@ define i32 @load_word(%struct.b* %ctx, i32 %xor72) nounwind {
   %shr81 = lshr i32 %xor72, 9
   %conv82 = zext i32 %shr81 to i64
   %idxprom83 = and i64 %conv82, 255
-  %arrayidx86 = getelementptr inbounds %struct.b* %ctx, i64 0, i64 %idxprom83
-  %result = load i32* %arrayidx86, align 4
+  %arrayidx86 = getelementptr inbounds %struct.b, %struct.b* %ctx, i64 0, i64 %idxprom83
+  %result = load i32, i32* %arrayidx86, align 4
   ret i32 %result
 }
 
@@ -37,8 +37,8 @@ define i64 @load_doubleword(%struct.c* %ctx, i32 %xor72) nounwind {
   %shr81 = lshr i32 %xor72, 9
   %conv82 = zext i32 %shr81 to i64
   %idxprom83 = and i64 %conv82, 255
-  %arrayidx86 = getelementptr inbounds %struct.c* %ctx, i64 0, i64 %idxprom83
-  %result = load i64* %arrayidx86, align 8
+  %arrayidx86 = getelementptr inbounds %struct.c, %struct.c* %ctx, i64 0, i64 %idxprom83
+  %result = load i64, i64* %arrayidx86, align 8
   ret i64 %result
 }
 
@@ -49,7 +49,7 @@ define void @store_halfword(%struct.a* %ctx, i32 %xor72, i16 %val) nounwind {
   %shr81 = lshr i32 %xor72, 9
   %conv82 = zext i32 %shr81 to i64
   %idxprom83 = and i64 %conv82, 255
-  %arrayidx86 = getelementptr inbounds %struct.a* %ctx, i64 0, i64 %idxprom83
+  %arrayidx86 = getelementptr inbounds %struct.a, %struct.a* %ctx, i64 0, i64 %idxprom83
   store i16 %val, i16* %arrayidx86, align 8
   ret void
 }
@@ -61,7 +61,7 @@ define void @store_word(%struct.b* %ctx, i32 %xor72, i32 %val) nounwind {
   %shr81 = lshr i32 %xor72, 9
   %conv82 = zext i32 %shr81 to i64
   %idxprom83 = and i64 %conv82, 255
-  %arrayidx86 = getelementptr inbounds %struct.b* %ctx, i64 0, i64 %idxprom83
+  %arrayidx86 = getelementptr inbounds %struct.b, %struct.b* %ctx, i64 0, i64 %idxprom83
   store i32 %val, i32* %arrayidx86, align 8
   ret void
 }
@@ -73,7 +73,7 @@ define void @store_doubleword(%struct.c* %ctx, i32 %xor72, i64 %val) nounwind {
   %shr81 = lshr i32 %xor72, 9
   %conv82 = zext i32 %shr81 to i64
   %idxprom83 = and i64 %conv82, 255
-  %arrayidx86 = getelementptr inbounds %struct.c* %ctx, i64 0, i64 %idxprom83
+  %arrayidx86 = getelementptr inbounds %struct.c, %struct.c* %ctx, i64 0, i64 %idxprom83
   store i64 %val, i64* %arrayidx86, align 8
   ret void
 }
diff --git a/test/CodeGen/AArch64/arm64-fp128-folding.ll b/test/CodeGen/AArch64/arm64-fp128-folding.ll
index 6a7d203f5b17..4024dc984f63 100644
--- a/test/CodeGen/AArch64/arm64-fp128-folding.ll
+++ b/test/CodeGen/AArch64/arm64-fp128-folding.ll
@@ -8,7 +8,7 @@ define fp128 @test_folding() {
 ; CHECK-LABEL: test_folding:
   %l = alloca i32
   store i32 42, i32* %l
-  %val = load i32* %l
+  %val = load i32, i32* %l
   %fpval = sitofp i32 %val to fp128
   ; If the value is loaded from a constant pool into an fp128, it's been folded
   ; successfully.
diff --git a/test/CodeGen/AArch64/arm64-fp128.ll b/test/CodeGen/AArch64/arm64-fp128.ll
index b1d50102aa28..aaef39fcf512 100644
--- a/test/CodeGen/AArch64/arm64-fp128.ll
+++ b/test/CodeGen/AArch64/arm64-fp128.ll
@@ -6,8 +6,8 @@
 define fp128 @test_add() {
 ; CHECK-LABEL: test_add:
 
-  %lhs = load fp128* @lhs, align 16
-  %rhs = load fp128* @rhs, align 16
+  %lhs = load fp128, fp128* @lhs, align 16
+  %rhs = load fp128, fp128* @rhs, align 16
 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
 
@@ -19,8 +19,8 @@ define fp128 @test_add() {
 define fp128 @test_sub() {
 ; CHECK-LABEL: test_sub:
 
-  %lhs = load fp128* @lhs, align 16
-  %rhs = load fp128* @rhs, align 16
+  %lhs = load fp128, fp128* @lhs, align 16
+  %rhs = load fp128, fp128* @rhs, align 16
 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
 
@@ -32,8 +32,8 @@ define fp128 @test_sub() {
 define fp128 @test_mul() {
 ; CHECK-LABEL: test_mul:
 
-  %lhs = load fp128* @lhs, align 16
-  %rhs = load fp128* @rhs, align 16
+  %lhs = load fp128, fp128* @lhs, align 16
+  %rhs = load fp128, fp128* @rhs, align 16
 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
 
@@ -45,8 +45,8 @@ define fp128 @test_mul() {
 define fp128 @test_div() {
 ; CHECK-LABEL: test_div:
 
-  %lhs = load fp128* @lhs, align 16
-  %rhs = load fp128* @rhs, align 16
+  %lhs = load fp128, fp128* @lhs, align 16
+  %rhs = load fp128, fp128* @rhs, align 16
 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
 
@@ -60,7 +60,7 @@ define fp128 @test_div() {
 
 define void @test_fptosi() {
 ; CHECK-LABEL: test_fptosi:
-  %val = load fp128* @lhs, align 16
+  %val = load fp128, fp128* @lhs, align 16
 
   %val32 = fptosi fp128 %val to i32
   store i32 %val32, i32* @var32
@@ -75,7 +75,7 @@ define void @test_fptosi() {
 
 define void @test_fptoui() {
 ; CHECK-LABEL: test_fptoui:
-  %val = load fp128* @lhs, align 16
+  %val = load fp128, fp128* @lhs, align 16
 
   %val32 = fptoui fp128 %val to i32
   store i32 %val32, i32* @var32
@@ -91,12 +91,12 @@ define void @test_fptoui() {
 define void @test_sitofp() {
 ; CHECK-LABEL: test_sitofp:
 
-  %src32 = load i32* @var32
+  %src32 = load i32, i32* @var32
   %val32 = sitofp i32 %src32 to fp128
   store volatile fp128 %val32, fp128* @lhs
 ; CHECK: bl __floatsitf
 
-  %src64 = load i64* @var64
+  %src64 = load i64, i64* @var64
   %val64 = sitofp i64 %src64 to fp128
   store volatile fp128 %val64, fp128* @lhs
 ; CHECK: bl __floatditf
@@ -107,12 +107,12 @@ define void @test_sitofp() {
 define void @test_uitofp() {
 ; CHECK-LABEL: test_uitofp:
 
-  %src32 = load i32* @var32
+  %src32 = load i32, i32* @var32
   %val32 = uitofp i32 %src32 to fp128
   store volatile fp128 %val32, fp128* @lhs
 ; CHECK: bl __floatunsitf
 
-  %src64 = load i64* @var64
+  %src64 = load i64, i64* @var64
   %val64 = uitofp i64 %src64 to fp128
   store volatile fp128 %val64, fp128* @lhs
 ; CHECK: bl __floatunditf
@@ -123,8 +123,8 @@ define void @test_uitofp() {
 define i1 @test_setcc1() {
 ; CHECK-LABEL: test_setcc1:
 
-  %lhs = load fp128* @lhs, align 16
-  %rhs = load fp128* @rhs, align 16
+  %lhs = load fp128, fp128* @lhs, align 16
+  %rhs = load fp128, fp128* @rhs, align 16
 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
 
@@ -142,8 +142,8 @@ define i1 @test_setcc1() {
 define i1 @test_setcc2() {
 ; CHECK-LABEL: test_setcc2:
 
-  %lhs = load fp128* @lhs, align 16
-  %rhs = load fp128* @rhs, align 16
+  %lhs = load fp128, fp128* @lhs, align 16
+  %rhs = load fp128, fp128* @rhs, align 16
 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
 
@@ -164,8 +164,8 @@ define i1 @test_setcc2() {
 define i32 @test_br_cc() {
 ; CHECK-LABEL: test_br_cc:
 
-  %lhs = load fp128* @lhs, align 16
-  %rhs = load fp128* @rhs, align 16
+  %lhs = load fp128, fp128* @lhs, align 16
+  %rhs = load fp128, fp128* @rhs, align 16
 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
 
@@ -218,7 +218,7 @@ define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
 define void @test_round() {
 ; CHECK-LABEL: test_round:
 
-  %val = load fp128* @lhs, align 16
+  %val = load fp128, fp128* @lhs, align 16
 
   %float = fptrunc fp128 %val to float
   store float %float, float* @varfloat, align 4
@@ -236,15 +236,15 @@ define void @test_round() {
 define void @test_extend() {
 ; CHECK-LABEL: test_extend:
 
-  %val = load fp128* @lhs, align 16
+  %val = load fp128, fp128* @lhs, align 16
 
-  %float = load float* @varfloat
+  %float = load float, float* @varfloat
   %fromfloat = fpext float %float to fp128
   store volatile fp128 %fromfloat, fp128* @lhs, align 16
 ; CHECK: bl __extendsftf2
 ; CHECK: str q0, [{{x[0-9]+}}, :lo12:lhs]
 
-  %double = load double* @vardouble
+  %double = load double, double* @vardouble
   %fromdouble = fpext double %double to fp128
   store volatile fp128 %fromdouble, fp128* @lhs, align 16
 ; CHECK: bl __extenddftf2
diff --git a/test/CodeGen/AArch64/arm64-hello.ll b/test/CodeGen/AArch64/arm64-hello.ll
index a6346fb467fb..f1c4e9bbaed9 100644
--- a/test/CodeGen/AArch64/arm64-hello.ll
+++ b/test/CodeGen/AArch64/arm64-hello.ll
@@ -31,7 +31,7 @@ define i32 @main() nounwind ssp {
 entry:
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
-  %call = call i32 @puts(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0))
+  %call = call i32 @puts(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0))
   ret i32 %call
 }
 
diff --git a/test/CodeGen/AArch64/arm64-i16-subreg-extract.ll b/test/CodeGen/AArch64/arm64-i16-subreg-extract.ll
index ba759e32aae5..8d74ce7f5182 100644
--- a/test/CodeGen/AArch64/arm64-i16-subreg-extract.ll
+++ b/test/CodeGen/AArch64/arm64-i16-subreg-extract.ll
@@ -3,7 +3,7 @@
 define i32 @foo(<4 x i16>* %__a) nounwind {
 ; CHECK-LABEL: foo:
 ; CHECK: umov.h w{{[0-9]+}}, v{{[0-9]+}}[0]
-  %tmp18 = load <4 x i16>* %__a, align 8
+  %tmp18 = load <4 x i16>, <4 x i16>* %__a, align 8
   %vget_lane = extractelement <4 x i16> %tmp18, i32 0
   %conv = zext i16 %vget_lane to i32
   %mul = mul nsw i32 3, %conv
diff --git a/test/CodeGen/AArch64/arm64-indexed-memory.ll b/test/CodeGen/AArch64/arm64-indexed-memory.ll
index a8620f428da4..b52cddf600ac 100644
--- a/test/CodeGen/AArch64/arm64-indexed-memory.ll
+++ b/test/CodeGen/AArch64/arm64-indexed-memory.ll
@@ -4,8 +4,8 @@ define void @store64(i64** nocapture %out, i64 %index, i64 %spacing) nounwind no
 ; CHECK-LABEL: store64:
 ; CHECK: str x{{[0-9+]}}, [x{{[0-9+]}}], #8
 ; CHECK: ret
-  %tmp = load i64** %out, align 8
-  %incdec.ptr = getelementptr inbounds i64* %tmp, i64 1
+  %tmp = load i64*, i64** %out, align 8
+  %incdec.ptr = getelementptr inbounds i64, i64* %tmp, i64 1
   store i64 %spacing, i64* %tmp, align 4
   store i64* %incdec.ptr, i64** %out, align 8
   ret void
@@ -15,8 +15,8 @@ define void @store32(i32** nocapture %out, i32 %index, i32 %spacing) nounwind no
 ; CHECK-LABEL: store32:
 ; CHECK: str w{{[0-9+]}}, [x{{[0-9+]}}], #4
 ; CHECK: ret
-  %tmp = load i32** %out, align 8
-  %incdec.ptr = getelementptr inbounds i32* %tmp, i64 1
+  %tmp = load i32*, i32** %out, align 8
+  %incdec.ptr = getelementptr inbounds i32, i32* %tmp, i64 1
   store i32 %spacing, i32* %tmp, align 4
   store i32* %incdec.ptr, i32** %out, align 8
   ret void
@@ -26,8 +26,8 @@ define void @store16(i16** nocapture %out, i16 %index, i16 %spacing) nounwind no
 ; CHECK-LABEL: store16:
 ; CHECK: strh w{{[0-9+]}}, [x{{[0-9+]}}], #2
 ; CHECK: ret
-  %tmp = load i16** %out, align 8
-  %incdec.ptr = getelementptr inbounds i16* %tmp, i64 1
+  %tmp = load i16*, i16** %out, align 8
+  %incdec.ptr = getelementptr inbounds i16, i16* %tmp, i64 1
   store i16 %spacing, i16* %tmp, align 4
   store i16* %incdec.ptr, i16** %out, align 8
   ret void
@@ -37,8 +37,8 @@ define void @store8(i8** nocapture %out, i8 %index, i8 %spacing) nounwind noinli
 ; CHECK-LABEL: store8:
 ; CHECK: strb w{{[0-9+]}}, [x{{[0-9+]}}], #1
 ; CHECK: ret
-  %tmp = load i8** %out, align 8
-  %incdec.ptr = getelementptr inbounds i8* %tmp, i64 1
+  %tmp = load i8*, i8** %out, align 8
+  %incdec.ptr = getelementptr inbounds i8, i8* %tmp, i64 1
   store i8 %spacing, i8* %tmp, align 4
   store i8* %incdec.ptr, i8** %out, align 8
   ret void
@@ -48,8 +48,8 @@ define void @truncst64to32(i32** nocapture %out, i32 %index, i64 %spacing) nounw
 ; CHECK-LABEL: truncst64to32:
 ; CHECK: str w{{[0-9+]}}, [x{{[0-9+]}}], #4
 ; CHECK: ret
-  %tmp = load i32** %out, align 8
-  %incdec.ptr = getelementptr inbounds i32* %tmp, i64 1
+  %tmp = load i32*, i32** %out, align 8
+  %incdec.ptr = getelementptr inbounds i32, i32* %tmp, i64 1
   %trunc = trunc i64 %spacing to i32
   store i32 %trunc, i32* %tmp, align 4
   store i32* %incdec.ptr, i32** %out, align 8
@@ -60,8 +60,8 @@ define void @truncst64to16(i16** nocapture %out, i16 %index, i64 %spacing) nounw
 ; CHECK-LABEL: truncst64to16:
 ; CHECK: strh w{{[0-9+]}}, [x{{[0-9+]}}], #2
 ; CHECK: ret
-  %tmp = load i16** %out, align 8
-  %incdec.ptr = getelementptr inbounds i16* %tmp, i64 1
+  %tmp = load i16*, i16** %out, align 8
+  %incdec.ptr = getelementptr inbounds i16, i16* %tmp, i64 1
   %trunc = trunc i64 %spacing to i16
   store i16 %trunc, i16* %tmp, align 4
   store i16* %incdec.ptr, i16** %out, align 8
@@ -72,8 +72,8 @@ define void @truncst64to8(i8** nocapture %out, i8 %index, i64 %spacing) nounwind
 ; CHECK-LABEL: truncst64to8:
 ; CHECK: strb w{{[0-9+]}}, [x{{[0-9+]}}], #1
 ; CHECK: ret
-  %tmp = load i8** %out, align 8
-  %incdec.ptr = getelementptr inbounds i8* %tmp, i64 1
+  %tmp = load i8*, i8** %out, align 8
+  %incdec.ptr = getelementptr inbounds i8, i8* %tmp, i64 1
   %trunc = trunc i64 %spacing to i8
   store i8 %trunc, i8* %tmp, align 4
   store i8* %incdec.ptr, i8** %out, align 8
@@ -85,8 +85,8 @@ define void @storef32(float** nocapture %out, float %index, float %spacing) noun
 ; CHECK-LABEL: storef32:
 ; CHECK: str s{{[0-9+]}}, [x{{[0-9+]}}], #4
 ; CHECK: ret
-  %tmp = load float** %out, align 8
-  %incdec.ptr = getelementptr inbounds float* %tmp, i64 1
+  %tmp = load float*, float** %out, align 8
+  %incdec.ptr = getelementptr inbounds float, float* %tmp, i64 1
   store float %spacing, float* %tmp, align 4
   store float* %incdec.ptr, float** %out, align 8
   ret void
@@ -96,8 +96,8 @@ define void @storef64(double** nocapture %out, double %index, double %spacing) n
 ; CHECK-LABEL: storef64:
 ; CHECK: str d{{[0-9+]}}, [x{{[0-9+]}}], #8
 ; CHECK: ret
-  %tmp = load double** %out, align 8
-  %incdec.ptr = getelementptr inbounds double* %tmp, i64 1
+  %tmp = load double*, double** %out, align 8
+  %incdec.ptr = getelementptr inbounds double, double* %tmp, i64 1
   store double %spacing, double* %tmp, align 4
   store double* %incdec.ptr, double** %out, align 8
   ret void
@@ -108,8 +108,8 @@ define double * @pref64(double** nocapture %out, double %spacing) nounwind noinl
 ; CHECK: ldr     x0, [x0]
 ; CHECK-NEXT: str     d0, [x0, #32]!
 ; CHECK-NEXT: ret
-  %tmp = load double** %out, align 8
-  %ptr = getelementptr inbounds double* %tmp, i64 4
+  %tmp = load double*, double** %out, align 8
+  %ptr = getelementptr inbounds double, double* %tmp, i64 4
   store double %spacing, double* %ptr, align 4
   ret double *%ptr
 }
@@ -119,8 +119,8 @@ define float * @pref32(float** nocapture %out, float %spacing) nounwind noinline
 ; CHECK: ldr     x0, [x0]
 ; CHECK-NEXT: str     s0, [x0, #12]!
 ; CHECK-NEXT: ret
-  %tmp = load float** %out, align 8
-  %ptr = getelementptr inbounds float* %tmp, i64 3
+  %tmp = load float*, float** %out, align 8
+  %ptr = getelementptr inbounds float, float* %tmp, i64 3
   store float %spacing, float* %ptr, align 4
   ret float *%ptr
 }
@@ -130,8 +130,8 @@ define i64 * @pre64(i64** nocapture %out, i64 %spacing) nounwind noinline ssp {
 ; CHECK: ldr     x0, [x0]
 ; CHECK-NEXT: str     x1, [x0, #16]!
 ; CHECK-NEXT: ret
-  %tmp = load i64** %out, align 8
-  %ptr = getelementptr inbounds i64* %tmp, i64 2
+  %tmp = load i64*, i64** %out, align 8
+  %ptr = getelementptr inbounds i64, i64* %tmp, i64 2
   store i64 %spacing, i64* %ptr, align 4
   ret i64 *%ptr
 }
@@ -141,8 +141,8 @@ define i32 * @pre32(i32** nocapture %out, i32 %spacing) nounwind noinline ssp {
 ; CHECK: ldr     x0, [x0]
 ; CHECK-NEXT: str     w1, [x0, #8]!
 ; CHECK-NEXT: ret
-  %tmp = load i32** %out, align 8
-  %ptr = getelementptr inbounds i32* %tmp, i64 2
+  %tmp = load i32*, i32** %out, align 8
+  %ptr = getelementptr inbounds i32, i32* %tmp, i64 2
   store i32 %spacing, i32* %ptr, align 4
   ret i32 *%ptr
 }
@@ -152,8 +152,8 @@ define i16 * @pre16(i16** nocapture %out, i16 %spacing) nounwind noinline ssp {
 ; CHECK: ldr     x0, [x0]
 ; CHECK-NEXT: strh    w1, [x0, #4]!
 ; CHECK-NEXT: ret
-  %tmp = load i16** %out, align 8
-  %ptr = getelementptr inbounds i16* %tmp, i64 2
+  %tmp = load i16*, i16** %out, align 8
+  %ptr = getelementptr inbounds i16, i16* %tmp, i64 2
   store i16 %spacing, i16* %ptr, align 4
   ret i16 *%ptr
 }
@@ -163,8 +163,8 @@ define i8 * @pre8(i8** nocapture %out, i8 %spacing) nounwind noinline ssp {
 ; CHECK: ldr     x0, [x0]
 ; CHECK-NEXT: strb    w1, [x0, #2]!
 ; CHECK-NEXT: ret
-  %tmp = load i8** %out, align 8
-  %ptr = getelementptr inbounds i8* %tmp, i64 2
+  %tmp = load i8*, i8** %out, align 8
+  %ptr = getelementptr inbounds i8, i8* %tmp, i64 2
   store i8 %spacing, i8* %ptr, align 4
   ret i8 *%ptr
 }
@@ -174,8 +174,8 @@ define i32 * @pretrunc64to32(i32** nocapture %out, i64 %spacing) nounwind noinli
 ; CHECK: ldr     x0, [x0]
 ; CHECK-NEXT: str     w1, [x0, #8]!
 ; CHECK-NEXT: ret
-  %tmp = load i32** %out, align 8
-  %ptr = getelementptr inbounds i32* %tmp, i64 2
+  %tmp = load i32*, i32** %out, align 8
+  %ptr = getelementptr inbounds i32, i32* %tmp, i64 2
   %trunc = trunc i64 %spacing to i32
   store i32 %trunc, i32* %ptr, align 4
   ret i32 *%ptr
@@ -186,8 +186,8 @@ define i16 * @pretrunc64to16(i16** nocapture %out, i64 %spacing) nounwind noinli
 ; CHECK: ldr     x0, [x0]
 ; CHECK-NEXT: strh    w1, [x0, #4]!
 ; CHECK-NEXT: ret
-  %tmp = load i16** %out, align 8
-  %ptr = getelementptr inbounds i16* %tmp, i64 2
+  %tmp = load i16*, i16** %out, align 8
+  %ptr = getelementptr inbounds i16, i16* %tmp, i64 2
   %trunc = trunc i64 %spacing to i16
   store i16 %trunc, i16* %ptr, align 4
   ret i16 *%ptr
@@ -198,8 +198,8 @@ define i8 * @pretrunc64to8(i8** nocapture %out, i64 %spacing) nounwind noinline
 ; CHECK: ldr     x0, [x0]
 ; CHECK-NEXT: strb    w1, [x0, #2]!
 ; CHECK-NEXT: ret
-  %tmp = load i8** %out, align 8
-  %ptr = getelementptr inbounds i8* %tmp, i64 2
+  %tmp = load i8*, i8** %out, align 8
+  %ptr = getelementptr inbounds i8, i8* %tmp, i64 2
   %trunc = trunc i64 %spacing to i8
   store i8 %trunc, i8* %ptr, align 4
   ret i8 *%ptr
@@ -213,8 +213,8 @@ define double* @preidxf64(double* %src, double* %out) {
 ; CHECK: ldr     d0, [x0, #8]!
 ; CHECK: str     d0, [x1]
 ; CHECK: ret
-  %ptr = getelementptr inbounds double* %src, i64 1
-  %tmp = load double* %ptr, align 4
+  %ptr = getelementptr inbounds double, double* %src, i64 1
+  %tmp = load double, double* %ptr, align 4
   store double %tmp, double* %out, align 4
   ret double* %ptr
 }
@@ -224,8 +224,8 @@ define float* @preidxf32(float* %src, float* %out) {
 ; CHECK: ldr     s0, [x0, #4]!
 ; CHECK: str     s0, [x1]
 ; CHECK: ret
-  %ptr = getelementptr inbounds float* %src, i64 1
-  %tmp = load float* %ptr, align 4
+  %ptr = getelementptr inbounds float, float* %src, i64 1
+  %tmp = load float, float* %ptr, align 4
   store float %tmp, float* %out, align 4
   ret float* %ptr
 }
@@ -235,8 +235,8 @@ define i64* @preidx64(i64* %src, i64* %out) {
 ; CHECK: ldr     x[[REG:[0-9]+]], [x0, #8]!
 ; CHECK: str     x[[REG]], [x1]
 ; CHECK: ret
-  %ptr = getelementptr inbounds i64* %src, i64 1
-  %tmp = load i64* %ptr, align 4
+  %ptr = getelementptr inbounds i64, i64* %src, i64 1
+  %tmp = load i64, i64* %ptr, align 4
   store i64 %tmp, i64* %out, align 4
   ret i64* %ptr
 }
@@ -245,8 +245,8 @@ define i32* @preidx32(i32* %src, i32* %out) {
 ; CHECK: ldr     w[[REG:[0-9]+]], [x0, #4]!
 ; CHECK: str     w[[REG]], [x1]
 ; CHECK: ret
-  %ptr = getelementptr inbounds i32* %src, i64 1
-  %tmp = load i32* %ptr, align 4
+  %ptr = getelementptr inbounds i32, i32* %src, i64 1
+  %tmp = load i32, i32* %ptr, align 4
   store i32 %tmp, i32* %out, align 4
   ret i32* %ptr
 }
@@ -255,8 +255,8 @@ define i16* @preidx16zext32(i16* %src, i32* %out) {
 ; CHECK: ldrh    w[[REG:[0-9]+]], [x0, #2]!
 ; CHECK: str     w[[REG]], [x1]
 ; CHECK: ret
-  %ptr = getelementptr inbounds i16* %src, i64 1
-  %tmp = load i16* %ptr, align 4
+  %ptr = getelementptr inbounds i16, i16* %src, i64 1
+  %tmp = load i16, i16* %ptr, align 4
   %ext = zext i16 %tmp to i32
   store i32 %ext, i32* %out, align 4
   ret i16* %ptr
@@ -266,8 +266,8 @@ define i16* @preidx16zext64(i16* %src, i64* %out) {
 ; CHECK: ldrh    w[[REG:[0-9]+]], [x0, #2]!
 ; CHECK: str     x[[REG]], [x1]
 ; CHECK: ret
-  %ptr = getelementptr inbounds i16* %src, i64 1
-  %tmp = load i16* %ptr, align 4
+  %ptr = getelementptr inbounds i16, i16* %src, i64 1
+  %tmp = load i16, i16* %ptr, align 4
   %ext = zext i16 %tmp to i64
   store i64 %ext, i64* %out, align 4
   ret i16* %ptr
@@ -277,8 +277,8 @@ define i8* @preidx8zext32(i8* %src, i32* %out) {
 ; CHECK: ldrb    w[[REG:[0-9]+]], [x0, #1]!
 ; CHECK: str     w[[REG]], [x1]
 ; CHECK: ret
-  %ptr = getelementptr inbounds i8* %src, i64 1
-  %tmp = load i8* %ptr, align 4
+  %ptr = getelementptr inbounds i8, i8* %src, i64 1
+  %tmp = load i8, i8* %ptr, align 4
   %ext = zext i8 %tmp to i32
   store i32 %ext, i32* %out, align 4
   ret i8* %ptr
@@ -288,8 +288,8 @@ define i8* @preidx8zext64(i8* %src, i64* %out) {
 ; CHECK: ldrb    w[[REG:[0-9]+]], [x0, #1]!
 ; CHECK: str     x[[REG]], [x1]
 ; CHECK: ret
-  %ptr = getelementptr inbounds i8* %src, i64 1
-  %tmp = load i8* %ptr, align 4
+  %ptr = getelementptr inbounds i8, i8* %src, i64 1
+  %tmp = load i8, i8* %ptr, align 4
   %ext = zext i8 %tmp to i64
   store i64 %ext, i64* %out, align 4
   ret i8* %ptr
@@ -299,8 +299,8 @@ define i32* @preidx32sext64(i32* %src, i64* %out) {
 ; CHECK: ldrsw   x[[REG:[0-9]+]], [x0, #4]!
 ; CHECK: str     x[[REG]], [x1]
 ; CHECK: ret
-  %ptr = getelementptr inbounds i32* %src, i64 1
-  %tmp = load i32* %ptr, align 4
+  %ptr = getelementptr inbounds i32, i32* %src, i64 1
+  %tmp = load i32, i32* %ptr, align 4
   %ext = sext i32 %tmp to i64
   store i64 %ext, i64* %out, align 8
   ret i32* %ptr
@@ -310,8 +310,8 @@ define i16* @preidx16sext32(i16* %src, i32* %out) {
 ; CHECK: ldrsh   w[[REG:[0-9]+]], [x0, #2]!
 ; CHECK: str     w[[REG]], [x1]
 ; CHECK: ret
-  %ptr = getelementptr inbounds i16* %src, i64 1
-  %tmp = load i16* %ptr, align 4
+  %ptr = getelementptr inbounds i16, i16* %src, i64 1
+  %tmp = load i16, i16* %ptr, align 4
   %ext = sext i16 %tmp to i32
   store i32 %ext, i32* %out, align 4
   ret i16* %ptr
@@ -321,8 +321,8 @@ define i16* @preidx16sext64(i16* %src, i64* %out) {
 ; CHECK: ldrsh   x[[REG:[0-9]+]], [x0, #2]!
 ; CHECK: str     x[[REG]], [x1]
 ; CHECK: ret
-  %ptr = getelementptr inbounds i16* %src, i64 1
-  %tmp = load i16* %ptr, align 4
+  %ptr = getelementptr inbounds i16, i16* %src, i64 1
+  %tmp = load i16, i16* %ptr, align 4
   %ext = sext i16 %tmp to i64
   store i64 %ext, i64* %out, align 4
   ret i16* %ptr
@@ -332,8 +332,8 @@ define i8* @preidx8sext32(i8* %src, i32* %out) {
 ; CHECK: ldrsb   w[[REG:[0-9]+]], [x0, #1]!
 ; CHECK: str     w[[REG]], [x1]
 ; CHECK: ret
-  %ptr = getelementptr inbounds i8* %src, i64 1
-  %tmp = load i8* %ptr, align 4
+  %ptr = getelementptr inbounds i8, i8* %src, i64 1
+  %tmp = load i8, i8* %ptr, align 4
   %ext = sext i8 %tmp to i32
   store i32 %ext, i32* %out, align 4
   ret i8* %ptr
@@ -343,8 +343,8 @@ define i8* @preidx8sext64(i8* %src, i64* %out) {
 ; CHECK: ldrsb   x[[REG:[0-9]+]], [x0, #1]!
 ; CHECK: str     x[[REG]], [x1]
 ; CHECK: ret
-  %ptr = getelementptr inbounds i8* %src, i64 1
-  %tmp = load i8* %ptr, align 4
+  %ptr = getelementptr inbounds i8, i8* %src, i64 1
+  %tmp = load i8, i8* %ptr, align 4
   %ext = sext i8 %tmp to i64
   store i64 %ext, i64* %out, align 4
   ret i8* %ptr
@@ -358,6 +358,6 @@ define i64* @postidx_clobber(i64* %addr) nounwind noinline ssp {
 ; ret
  %paddr = bitcast i64* %addr to i64**
  store i64* %addr, i64** %paddr
- %newaddr = getelementptr i64* %addr, i32 1
+ %newaddr = getelementptr i64, i64* %addr, i32 1
  ret i64* %newaddr
 }
diff --git a/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll b/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll
index 917911ad2d40..14beb1ae9c36 100644
--- a/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll
+++ b/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll
@@ -9,9 +9,9 @@ target triple = "arm64-apple-ios7.0.0"
 ; Function Attrs: nounwind ssp
 define void @f(double* %P1) #0 {
 entry:
-  %arrayidx4 = getelementptr inbounds double* %P1, i64 1
-  %0 = load double* %arrayidx4, align 8, !tbaa !1
-  %1 = load double* %P1, align 8, !tbaa !1
+  %arrayidx4 = getelementptr inbounds double, double* %P1, i64 1
+  %0 = load double, double* %arrayidx4, align 8, !tbaa !1
+  %1 = load double, double* %P1, align 8, !tbaa !1
   %2 = insertelement <2 x double> undef, double %0, i32 0
   %3 = insertelement <2 x double> %2, double %1, i32 1
   %4 = fsub <2 x double> zeroinitializer, %3
diff --git a/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll b/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
index 9ee4063658b2..ba31513172d5 100644
--- a/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
+++ b/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
@@ -5,8 +5,8 @@
 define <8 x i8> @test_v8i8_pre_load(<8 x i8>* %addr) {
 ; CHECK-LABEL: test_v8i8_pre_load:
 ; CHECK: ldr d0, [x0, #40]!
-  %newaddr = getelementptr <8 x i8>* %addr, i32 5
-  %val = load <8 x i8>* %newaddr, align 8
+  %newaddr = getelementptr <8 x i8>, <8 x i8>* %addr, i32 5
+  %val = load <8 x i8>, <8 x i8>* %newaddr, align 8
   store <8 x i8>* %newaddr, <8 x i8>** bitcast(i8** @ptr to <8 x i8>**)
   ret <8 x i8> %val
 }
@@ -14,8 +14,8 @@ define <8 x i8> @test_v8i8_pre_load(<8 x i8>* %addr) {
 define <8 x i8> @test_v8i8_post_load(<8 x i8>* %addr) {
 ; CHECK-LABEL: test_v8i8_post_load:
 ; CHECK: ldr d0, [x0], #40
-  %newaddr = getelementptr <8 x i8>* %addr, i32 5
-  %val = load <8 x i8>* %addr, align 8
+  %newaddr = getelementptr <8 x i8>, <8 x i8>* %addr, i32 5
+  %val = load <8 x i8>, <8 x i8>* %addr, align 8
   store <8 x i8>* %newaddr, <8 x i8>** bitcast(i8** @ptr to <8 x i8>**)
   ret <8 x i8> %val
 }
@@ -23,7 +23,7 @@ define <8 x i8> @test_v8i8_post_load(<8 x i8>* %addr) {
 define void @test_v8i8_pre_store(<8 x i8> %in, <8 x i8>* %addr) {
 ; CHECK-LABEL: test_v8i8_pre_store:
 ; CHECK: str d0, [x0, #40]!
-  %newaddr = getelementptr <8 x i8>* %addr, i32 5
+  %newaddr = getelementptr <8 x i8>, <8 x i8>* %addr, i32 5
   store <8 x i8> %in, <8 x i8>* %newaddr, align 8
   store <8 x i8>* %newaddr, <8 x i8>** bitcast(i8** @ptr to <8 x i8>**)
   ret void
@@ -32,7 +32,7 @@ define void @test_v8i8_pre_store(<8 x i8> %in, <8 x i8>* %addr) {
 define void @test_v8i8_post_store(<8 x i8> %in, <8 x i8>* %addr) {
 ; CHECK-LABEL: test_v8i8_post_store:
 ; CHECK: str d0, [x0], #40
-  %newaddr = getelementptr <8 x i8>* %addr, i32 5
+  %newaddr = getelementptr <8 x i8>, <8 x i8>* %addr, i32 5
   store <8 x i8> %in, <8 x i8>* %addr, align 8
   store <8 x i8>* %newaddr, <8 x i8>** bitcast(i8** @ptr to <8 x i8>**)
   ret void
@@ -41,8 +41,8 @@ define void @test_v8i8_post_store(<8 x i8> %in, <8 x i8>* %addr) {
 define <4 x i16> @test_v4i16_pre_load(<4 x i16>* %addr) {
 ; CHECK-LABEL: test_v4i16_pre_load:
 ; CHECK: ldr d0, [x0, #40]!
-  %newaddr = getelementptr <4 x i16>* %addr, i32 5
-  %val = load <4 x i16>* %newaddr, align 8
+  %newaddr = getelementptr <4 x i16>, <4 x i16>* %addr, i32 5
+  %val = load <4 x i16>, <4 x i16>* %newaddr, align 8
   store <4 x i16>* %newaddr, <4 x i16>** bitcast(i8** @ptr to <4 x i16>**)
   ret <4 x i16> %val
 }
@@ -50,8 +50,8 @@ define <4 x i16> @test_v4i16_pre_load(<4 x i16>* %addr) {
 define <4 x i16> @test_v4i16_post_load(<4 x i16>* %addr) {
 ; CHECK-LABEL: test_v4i16_post_load:
 ; CHECK: ldr d0, [x0], #40
-  %newaddr = getelementptr <4 x i16>* %addr, i32 5
-  %val = load <4 x i16>* %addr, align 8
+  %newaddr = getelementptr <4 x i16>, <4 x i16>* %addr, i32 5
+  %val = load <4 x i16>, <4 x i16>* %addr, align 8
   store <4 x i16>* %newaddr, <4 x i16>** bitcast(i8** @ptr to <4 x i16>**)
   ret <4 x i16> %val
 }
@@ -59,7 +59,7 @@ define <4 x i16> @test_v4i16_post_load(<4 x i16>* %addr) {
 define void @test_v4i16_pre_store(<4 x i16> %in, <4 x i16>* %addr) {
 ; CHECK-LABEL: test_v4i16_pre_store:
 ; CHECK: str d0, [x0, #40]!
-  %newaddr = getelementptr <4 x i16>* %addr, i32 5
+  %newaddr = getelementptr <4 x i16>, <4 x i16>* %addr, i32 5
   store <4 x i16> %in, <4 x i16>* %newaddr, align 8
   store <4 x i16>* %newaddr, <4 x i16>** bitcast(i8** @ptr to <4 x i16>**)
   ret void
@@ -68,7 +68,7 @@ define void @test_v4i16_pre_store(<4 x i16> %in, <4 x i16>* %addr) {
 define void @test_v4i16_post_store(<4 x i16> %in, <4 x i16>* %addr) {
 ; CHECK-LABEL: test_v4i16_post_store:
 ; CHECK: str d0, [x0], #40
-  %newaddr = getelementptr <4 x i16>* %addr, i32 5
+  %newaddr = getelementptr <4 x i16>, <4 x i16>* %addr, i32 5
   store <4 x i16> %in, <4 x i16>* %addr, align 8
   store <4 x i16>* %newaddr, <4 x i16>** bitcast(i8** @ptr to <4 x i16>**)
   ret void
@@ -77,8 +77,8 @@ define void @test_v4i16_post_store(<4 x i16> %in, <4 x i16>* %addr) {
 define <2 x i32> @test_v2i32_pre_load(<2 x i32>* %addr) {
 ; CHECK-LABEL: test_v2i32_pre_load:
 ; CHECK: ldr d0, [x0, #40]!
-  %newaddr = getelementptr <2 x i32>* %addr, i32 5
-  %val = load <2 x i32>* %newaddr, align 8
+  %newaddr = getelementptr <2 x i32>, <2 x i32>* %addr, i32 5
+  %val = load <2 x i32>, <2 x i32>* %newaddr, align 8
   store <2 x i32>* %newaddr, <2 x i32>** bitcast(i8** @ptr to <2 x i32>**)
   ret <2 x i32> %val
 }
@@ -86,8 +86,8 @@ define <2 x i32> @test_v2i32_pre_load(<2 x i32>* %addr) {
 define <2 x i32> @test_v2i32_post_load(<2 x i32>* %addr) {
 ; CHECK-LABEL: test_v2i32_post_load:
 ; CHECK: ldr d0, [x0], #40
-  %newaddr = getelementptr <2 x i32>* %addr, i32 5
-  %val = load <2 x i32>* %addr, align 8
+  %newaddr = getelementptr <2 x i32>, <2 x i32>* %addr, i32 5
+  %val = load <2 x i32>, <2 x i32>* %addr, align 8
   store <2 x i32>* %newaddr, <2 x i32>** bitcast(i8** @ptr to <2 x i32>**)
   ret <2 x i32> %val
 }
@@ -95,7 +95,7 @@ define <2 x i32> @test_v2i32_post_load(<2 x i32>* %addr) {
 define void @test_v2i32_pre_store(<2 x i32> %in, <2 x i32>* %addr) {
 ; CHECK-LABEL: test_v2i32_pre_store:
 ; CHECK: str d0, [x0, #40]!
-  %newaddr = getelementptr <2 x i32>* %addr, i32 5
+  %newaddr = getelementptr <2 x i32>, <2 x i32>* %addr, i32 5
   store <2 x i32> %in, <2 x i32>* %newaddr, align 8
   store <2 x i32>* %newaddr, <2 x i32>** bitcast(i8** @ptr to <2 x i32>**)
   ret void
@@ -104,7 +104,7 @@ define void @test_v2i32_pre_store(<2 x i32> %in, <2 x i32>* %addr) {
 define void @test_v2i32_post_store(<2 x i32> %in, <2 x i32>* %addr) {
 ; CHECK-LABEL: test_v2i32_post_store:
 ; CHECK: str d0, [x0], #40
-  %newaddr = getelementptr <2 x i32>* %addr, i32 5
+  %newaddr = getelementptr <2 x i32>, <2 x i32>* %addr, i32 5
   store <2 x i32> %in, <2 x i32>* %addr, align 8
   store <2 x i32>* %newaddr, <2 x i32>** bitcast(i8** @ptr to <2 x i32>**)
   ret void
@@ -113,8 +113,8 @@ define void @test_v2i32_post_store(<2 x i32> %in, <2 x i32>* %addr) {
 define <2 x float> @test_v2f32_pre_load(<2 x float>* %addr) {
 ; CHECK-LABEL: test_v2f32_pre_load:
 ; CHECK: ldr d0, [x0, #40]!
-  %newaddr = getelementptr <2 x float>* %addr, i32 5
-  %val = load <2 x float>* %newaddr, align 8
+  %newaddr = getelementptr <2 x float>, <2 x float>* %addr, i32 5
+  %val = load <2 x float>, <2 x float>* %newaddr, align 8
   store <2 x float>* %newaddr, <2 x float>** bitcast(i8** @ptr to <2 x float>**)
   ret <2 x float> %val
 }
@@ -122,8 +122,8 @@ define <2 x float> @test_v2f32_pre_load(<2 x float>* %addr) {
 define <2 x float> @test_v2f32_post_load(<2 x float>* %addr) {
 ; CHECK-LABEL: test_v2f32_post_load:
 ; CHECK: ldr d0, [x0], #40
-  %newaddr = getelementptr <2 x float>* %addr, i32 5
-  %val = load <2 x float>* %addr, align 8
+  %newaddr = getelementptr <2 x float>, <2 x float>* %addr, i32 5
+  %val = load <2 x float>, <2 x float>* %addr, align 8
   store <2 x float>* %newaddr, <2 x float>** bitcast(i8** @ptr to <2 x float>**)
   ret <2 x float> %val
 }
@@ -131,7 +131,7 @@ define <2 x float> @test_v2f32_post_load(<2 x float>* %addr) {
 define void @test_v2f32_pre_store(<2 x float> %in, <2 x float>* %addr) {
 ; CHECK-LABEL: test_v2f32_pre_store:
 ; CHECK: str d0, [x0, #40]!
-  %newaddr = getelementptr <2 x float>* %addr, i32 5
+  %newaddr = getelementptr <2 x float>, <2 x float>* %addr, i32 5
   store <2 x float> %in, <2 x float>* %newaddr, align 8
   store <2 x float>* %newaddr, <2 x float>** bitcast(i8** @ptr to <2 x float>**)
   ret void
@@ -140,7 +140,7 @@ define void @test_v2f32_pre_store(<2 x float> %in, <2 x float>* %addr) {
 define void @test_v2f32_post_store(<2 x float> %in, <2 x float>* %addr) {
 ; CHECK-LABEL: test_v2f32_post_store:
 ; CHECK: str d0, [x0], #40
-  %newaddr = getelementptr <2 x float>* %addr, i32 5
+  %newaddr = getelementptr <2 x float>, <2 x float>* %addr, i32 5
   store <2 x float> %in, <2 x float>* %addr, align 8
   store <2 x float>* %newaddr, <2 x float>** bitcast(i8** @ptr to <2 x float>**)
   ret void
@@ -149,8 +149,8 @@ define void @test_v2f32_post_store(<2 x float> %in, <2 x float>* %addr) {
 define <1 x i64> @test_v1i64_pre_load(<1 x i64>* %addr) {
 ; CHECK-LABEL: test_v1i64_pre_load:
 ; CHECK: ldr d0, [x0, #40]!
-  %newaddr = getelementptr <1 x i64>* %addr, i32 5
-  %val = load <1 x i64>* %newaddr, align 8
+  %newaddr = getelementptr <1 x i64>, <1 x i64>* %addr, i32 5
+  %val = load <1 x i64>, <1 x i64>* %newaddr, align 8
   store <1 x i64>* %newaddr, <1 x i64>** bitcast(i8** @ptr to <1 x i64>**)
   ret <1 x i64> %val
 }
@@ -158,8 +158,8 @@ define <1 x i64> @test_v1i64_pre_load(<1 x i64>* %addr) {
 define <1 x i64> @test_v1i64_post_load(<1 x i64>* %addr) {
 ; CHECK-LABEL: test_v1i64_post_load:
 ; CHECK: ldr d0, [x0], #40
-  %newaddr = getelementptr <1 x i64>* %addr, i32 5
-  %val = load <1 x i64>* %addr, align 8
+  %newaddr = getelementptr <1 x i64>, <1 x i64>* %addr, i32 5
+  %val = load <1 x i64>, <1 x i64>* %addr, align 8
   store <1 x i64>* %newaddr, <1 x i64>** bitcast(i8** @ptr to <1 x i64>**)
   ret <1 x i64> %val
 }
@@ -167,7 +167,7 @@ define <1 x i64> @test_v1i64_post_load(<1 x i64>* %addr) {
 define void @test_v1i64_pre_store(<1 x i64> %in, <1 x i64>* %addr) {
 ; CHECK-LABEL: test_v1i64_pre_store:
 ; CHECK: str d0, [x0, #40]!
-  %newaddr = getelementptr <1 x i64>* %addr, i32 5
+  %newaddr = getelementptr <1 x i64>, <1 x i64>* %addr, i32 5
   store <1 x i64> %in, <1 x i64>* %newaddr, align 8
   store <1 x i64>* %newaddr, <1 x i64>** bitcast(i8** @ptr to <1 x i64>**)
   ret void
@@ -176,7 +176,7 @@ define void @test_v1i64_pre_store(<1 x i64> %in, <1 x i64>* %addr) {
 define void @test_v1i64_post_store(<1 x i64> %in, <1 x i64>* %addr) {
 ; CHECK-LABEL: test_v1i64_post_store:
 ; CHECK: str d0, [x0], #40
-  %newaddr = getelementptr <1 x i64>* %addr, i32 5
+  %newaddr = getelementptr <1 x i64>, <1 x i64>* %addr, i32 5
   store <1 x i64> %in, <1 x i64>* %addr, align 8
   store <1 x i64>* %newaddr, <1 x i64>** bitcast(i8** @ptr to <1 x i64>**)
   ret void
@@ -185,8 +185,8 @@ define void @test_v1i64_post_store(<1 x i64> %in, <1 x i64>* %addr) {
 define <16 x i8> @test_v16i8_pre_load(<16 x i8>* %addr) {
 ; CHECK-LABEL: test_v16i8_pre_load:
 ; CHECK: ldr q0, [x0, #80]!
-  %newaddr = getelementptr <16 x i8>* %addr, i32 5
-  %val = load <16 x i8>* %newaddr, align 8
+  %newaddr = getelementptr <16 x i8>, <16 x i8>* %addr, i32 5
+  %val = load <16 x i8>, <16 x i8>* %newaddr, align 8
   store <16 x i8>* %newaddr, <16 x i8>** bitcast(i8** @ptr to <16 x i8>**)
   ret <16 x i8> %val
 }
@@ -194,8 +194,8 @@ define <16 x i8> @test_v16i8_pre_load(<16 x i8>* %addr) {
 define <16 x i8> @test_v16i8_post_load(<16 x i8>* %addr) {
 ; CHECK-LABEL: test_v16i8_post_load:
 ; CHECK: ldr q0, [x0], #80
-  %newaddr = getelementptr <16 x i8>* %addr, i32 5
-  %val = load <16 x i8>* %addr, align 8
+  %newaddr = getelementptr <16 x i8>, <16 x i8>* %addr, i32 5
+  %val = load <16 x i8>, <16 x i8>* %addr, align 8
   store <16 x i8>* %newaddr, <16 x i8>** bitcast(i8** @ptr to <16 x i8>**)
   ret <16 x i8> %val
 }
@@ -203,7 +203,7 @@ define <16 x i8> @test_v16i8_post_load(<16 x i8>* %addr) {
 define void @test_v16i8_pre_store(<16 x i8> %in, <16 x i8>* %addr) {
 ; CHECK-LABEL: test_v16i8_pre_store:
 ; CHECK: str q0, [x0, #80]!
-  %newaddr = getelementptr <16 x i8>* %addr, i32 5
+  %newaddr = getelementptr <16 x i8>, <16 x i8>* %addr, i32 5
   store <16 x i8> %in, <16 x i8>* %newaddr, align 8
   store <16 x i8>* %newaddr, <16 x i8>** bitcast(i8** @ptr to <16 x i8>**)
   ret void
@@ -212,7 +212,7 @@ define void @test_v16i8_pre_store(<16 x i8> %in, <16 x i8>* %addr) {
 define void @test_v16i8_post_store(<16 x i8> %in, <16 x i8>* %addr) {
 ; CHECK-LABEL: test_v16i8_post_store:
 ; CHECK: str q0, [x0], #80
-  %newaddr = getelementptr <16 x i8>* %addr, i32 5
+  %newaddr = getelementptr <16 x i8>, <16 x i8>* %addr, i32 5
   store <16 x i8> %in, <16 x i8>* %addr, align 8
   store <16 x i8>* %newaddr, <16 x i8>** bitcast(i8** @ptr to <16 x i8>**)
   ret void
@@ -221,8 +221,8 @@ define void @test_v16i8_post_store(<16 x i8> %in, <16 x i8>* %addr) {
 define <8 x i16> @test_v8i16_pre_load(<8 x i16>* %addr) {
 ; CHECK-LABEL: test_v8i16_pre_load:
 ; CHECK: ldr q0, [x0, #80]!
-  %newaddr = getelementptr <8 x i16>* %addr, i32 5
-  %val = load <8 x i16>* %newaddr, align 8
+  %newaddr = getelementptr <8 x i16>, <8 x i16>* %addr, i32 5
+  %val = load <8 x i16>, <8 x i16>* %newaddr, align 8
   store <8 x i16>* %newaddr, <8 x i16>** bitcast(i8** @ptr to <8 x i16>**)
   ret <8 x i16> %val
 }
@@ -230,8 +230,8 @@ define <8 x i16> @test_v8i16_pre_load(<8 x i16>* %addr) {
 define <8 x i16> @test_v8i16_post_load(<8 x i16>* %addr) {
 ; CHECK-LABEL: test_v8i16_post_load:
 ; CHECK: ldr q0, [x0], #80
-  %newaddr = getelementptr <8 x i16>* %addr, i32 5
-  %val = load <8 x i16>* %addr, align 8
+  %newaddr = getelementptr <8 x i16>, <8 x i16>* %addr, i32 5
+  %val = load <8 x i16>, <8 x i16>* %addr, align 8
   store <8 x i16>* %newaddr, <8 x i16>** bitcast(i8** @ptr to <8 x i16>**)
   ret <8 x i16> %val
 }
@@ -239,7 +239,7 @@ define <8 x i16> @test_v8i16_post_load(<8 x i16>* %addr) {
 define void @test_v8i16_pre_store(<8 x i16> %in, <8 x i16>* %addr) {
 ; CHECK-LABEL: test_v8i16_pre_store:
 ; CHECK: str q0, [x0, #80]!
-  %newaddr = getelementptr <8 x i16>* %addr, i32 5
+  %newaddr = getelementptr <8 x i16>, <8 x i16>* %addr, i32 5
   store <8 x i16> %in, <8 x i16>* %newaddr, align 8
   store <8 x i16>* %newaddr, <8 x i16>** bitcast(i8** @ptr to <8 x i16>**)
   ret void
@@ -248,7 +248,7 @@ define void @test_v8i16_pre_store(<8 x i16> %in, <8 x i16>* %addr) {
 define void @test_v8i16_post_store(<8 x i16> %in, <8 x i16>* %addr) {
 ; CHECK-LABEL: test_v8i16_post_store:
 ; CHECK: str q0, [x0], #80
-  %newaddr = getelementptr <8 x i16>* %addr, i32 5
+  %newaddr = getelementptr <8 x i16>, <8 x i16>* %addr, i32 5
   store <8 x i16> %in, <8 x i16>* %addr, align 8
   store <8 x i16>* %newaddr, <8 x i16>** bitcast(i8** @ptr to <8 x i16>**)
   ret void
@@ -257,8 +257,8 @@ define void @test_v8i16_post_store(<8 x i16> %in, <8 x i16>* %addr) {
 define <4 x i32> @test_v4i32_pre_load(<4 x i32>* %addr) {
 ; CHECK-LABEL: test_v4i32_pre_load:
 ; CHECK: ldr q0, [x0, #80]!
-  %newaddr = getelementptr <4 x i32>* %addr, i32 5
-  %val = load <4 x i32>* %newaddr, align 8
+  %newaddr = getelementptr <4 x i32>, <4 x i32>* %addr, i32 5
+  %val = load <4 x i32>, <4 x i32>* %newaddr, align 8
   store <4 x i32>* %newaddr, <4 x i32>** bitcast(i8** @ptr to <4 x i32>**)
   ret <4 x i32> %val
 }
@@ -266,8 +266,8 @@ define <4 x i32> @test_v4i32_pre_load(<4 x i32>* %addr) {
 define <4 x i32> @test_v4i32_post_load(<4 x i32>* %addr) {
 ; CHECK-LABEL: test_v4i32_post_load:
 ; CHECK: ldr q0, [x0], #80
-  %newaddr = getelementptr <4 x i32>* %addr, i32 5
-  %val = load <4 x i32>* %addr, align 8
+  %newaddr = getelementptr <4 x i32>, <4 x i32>* %addr, i32 5
+  %val = load <4 x i32>, <4 x i32>* %addr, align 8
   store <4 x i32>* %newaddr, <4 x i32>** bitcast(i8** @ptr to <4 x i32>**)
   ret <4 x i32> %val
 }
@@ -275,7 +275,7 @@ define <4 x i32> @test_v4i32_post_load(<4 x i32>* %addr) {
 define void @test_v4i32_pre_store(<4 x i32> %in, <4 x i32>* %addr) {
 ; CHECK-LABEL: test_v4i32_pre_store:
 ; CHECK: str q0, [x0, #80]!
-  %newaddr = getelementptr <4 x i32>* %addr, i32 5
+  %newaddr = getelementptr <4 x i32>, <4 x i32>* %addr, i32 5
   store <4 x i32> %in, <4 x i32>* %newaddr, align 8
   store <4 x i32>* %newaddr, <4 x i32>** bitcast(i8** @ptr to <4 x i32>**)
   ret void
@@ -284,7 +284,7 @@ define void @test_v4i32_pre_store(<4 x i32> %in, <4 x i32>* %addr) {
 define void @test_v4i32_post_store(<4 x i32> %in, <4 x i32>* %addr) {
 ; CHECK-LABEL: test_v4i32_post_store:
 ; CHECK: str q0, [x0], #80
-  %newaddr = getelementptr <4 x i32>* %addr, i32 5
+  %newaddr = getelementptr <4 x i32>, <4 x i32>* %addr, i32 5
   store <4 x i32> %in, <4 x i32>* %addr, align 8
   store <4 x i32>* %newaddr, <4 x i32>** bitcast(i8** @ptr to <4 x i32>**)
   ret void
@@ -294,8 +294,8 @@ define void @test_v4i32_post_store(<4 x i32> %in, <4 x i32>* %addr) {
 define <4 x float> @test_v4f32_pre_load(<4 x float>* %addr) {
 ; CHECK-LABEL: test_v4f32_pre_load:
 ; CHECK: ldr q0, [x0, #80]!
-  %newaddr = getelementptr <4 x float>* %addr, i32 5
-  %val = load <4 x float>* %newaddr, align 8
+  %newaddr = getelementptr <4 x float>, <4 x float>* %addr, i32 5
+  %val = load <4 x float>, <4 x float>* %newaddr, align 8
   store <4 x float>* %newaddr, <4 x float>** bitcast(i8** @ptr to <4 x float>**)
   ret <4 x float> %val
 }
@@ -303,8 +303,8 @@ define <4 x float> @test_v4f32_pre_load(<4 x float>* %addr) {
 define <4 x float> @test_v4f32_post_load(<4 x float>* %addr) {
 ; CHECK-LABEL: test_v4f32_post_load:
 ; CHECK: ldr q0, [x0], #80
-  %newaddr = getelementptr <4 x float>* %addr, i32 5
-  %val = load <4 x float>* %addr, align 8
+  %newaddr = getelementptr <4 x float>, <4 x float>* %addr, i32 5
+  %val = load <4 x float>, <4 x float>* %addr, align 8
   store <4 x float>* %newaddr, <4 x float>** bitcast(i8** @ptr to <4 x float>**)
   ret <4 x float> %val
 }
@@ -312,7 +312,7 @@ define <4 x float> @test_v4f32_post_load(<4 x float>* %addr) {
 define void @test_v4f32_pre_store(<4 x float> %in, <4 x float>* %addr) {
 ; CHECK-LABEL: test_v4f32_pre_store:
 ; CHECK: str q0, [x0, #80]!
-  %newaddr = getelementptr <4 x float>* %addr, i32 5
+  %newaddr = getelementptr <4 x float>, <4 x float>* %addr, i32 5
   store <4 x float> %in, <4 x float>* %newaddr, align 8
   store <4 x float>* %newaddr, <4 x float>** bitcast(i8** @ptr to <4 x float>**)
   ret void
@@ -321,7 +321,7 @@ define void @test_v4f32_pre_store(<4 x float> %in, <4 x float>* %addr) {
 define void @test_v4f32_post_store(<4 x float> %in, <4 x float>* %addr) {
 ; CHECK-LABEL: test_v4f32_post_store:
 ; CHECK: str q0, [x0], #80
-  %newaddr = getelementptr <4 x float>* %addr, i32 5
+  %newaddr = getelementptr <4 x float>, <4 x float>* %addr, i32 5
   store <4 x float> %in, <4 x float>* %addr, align 8
   store <4 x float>* %newaddr, <4 x float>** bitcast(i8** @ptr to <4 x float>**)
   ret void
@@ -331,8 +331,8 @@ define void @test_v4f32_post_store(<4 x float> %in, <4 x float>* %addr) {
 define <2 x i64> @test_v2i64_pre_load(<2 x i64>* %addr) {
 ; CHECK-LABEL: test_v2i64_pre_load:
 ; CHECK: ldr q0, [x0, #80]!
-  %newaddr = getelementptr <2 x i64>* %addr, i32 5
-  %val = load <2 x i64>* %newaddr, align 8
+  %newaddr = getelementptr <2 x i64>, <2 x i64>* %addr, i32 5
+  %val = load <2 x i64>, <2 x i64>* %newaddr, align 8
   store <2 x i64>* %newaddr, <2 x i64>** bitcast(i8** @ptr to <2 x i64>**)
   ret <2 x i64> %val
 }
@@ -340,8 +340,8 @@ define <2 x i64> @test_v2i64_pre_load(<2 x i64>* %addr) {
 define <2 x i64> @test_v2i64_post_load(<2 x i64>* %addr) {
 ; CHECK-LABEL: test_v2i64_post_load:
 ; CHECK: ldr q0, [x0], #80
-  %newaddr = getelementptr <2 x i64>* %addr, i32 5
-  %val = load <2 x i64>* %addr, align 8
+  %newaddr = getelementptr <2 x i64>, <2 x i64>* %addr, i32 5
+  %val = load <2 x i64>, <2 x i64>* %addr, align 8
   store <2 x i64>* %newaddr, <2 x i64>** bitcast(i8** @ptr to <2 x i64>**)
   ret <2 x i64> %val
 }
@@ -349,7 +349,7 @@ define <2 x i64> @test_v2i64_post_load(<2 x i64>* %addr) {
 define void @test_v2i64_pre_store(<2 x i64> %in, <2 x i64>* %addr) {
 ; CHECK-LABEL: test_v2i64_pre_store:
 ; CHECK: str q0, [x0, #80]!
-  %newaddr = getelementptr <2 x i64>* %addr, i32 5
+  %newaddr = getelementptr <2 x i64>, <2 x i64>* %addr, i32 5
   store <2 x i64> %in, <2 x i64>* %newaddr, align 8
   store <2 x i64>* %newaddr, <2 x i64>** bitcast(i8** @ptr to <2 x i64>**)
   ret void
@@ -358,7 +358,7 @@ define void @test_v2i64_pre_store(<2 x i64> %in, <2 x i64>* %addr) {
 define void @test_v2i64_post_store(<2 x i64> %in, <2 x i64>* %addr) {
 ; CHECK-LABEL: test_v2i64_post_store:
 ; CHECK: str q0, [x0], #80
-  %newaddr = getelementptr <2 x i64>* %addr, i32 5
+  %newaddr = getelementptr <2 x i64>, <2 x i64>* %addr, i32 5
   store <2 x i64> %in, <2 x i64>* %addr, align 8
   store <2 x i64>* %newaddr, <2 x i64>** bitcast(i8** @ptr to <2 x i64>**)
   ret void
@@ -368,8 +368,8 @@ define void @test_v2i64_post_store(<2 x i64> %in, <2 x i64>* %addr) {
 define <2 x double> @test_v2f64_pre_load(<2 x double>* %addr) {
 ; CHECK-LABEL: test_v2f64_pre_load:
 ; CHECK: ldr q0, [x0, #80]!
-  %newaddr = getelementptr <2 x double>* %addr, i32 5
-  %val = load <2 x double>* %newaddr, align 8
+  %newaddr = getelementptr <2 x double>, <2 x double>* %addr, i32 5
+  %val = load <2 x double>, <2 x double>* %newaddr, align 8
   store <2 x double>* %newaddr, <2 x double>** bitcast(i8** @ptr to <2 x double>**)
   ret <2 x double> %val
 }
@@ -377,8 +377,8 @@ define <2 x double> @test_v2f64_pre_load(<2 x double>* %addr) {
 define <2 x double> @test_v2f64_post_load(<2 x double>* %addr) {
 ; CHECK-LABEL: test_v2f64_post_load:
 ; CHECK: ldr q0, [x0], #80
-  %newaddr = getelementptr <2 x double>* %addr, i32 5
-  %val = load <2 x double>* %addr, align 8
+  %newaddr = getelementptr <2 x double>, <2 x double>* %addr, i32 5
+  %val = load <2 x double>, <2 x double>* %addr, align 8
   store <2 x double>* %newaddr, <2 x double>** bitcast(i8** @ptr to <2 x double>**)
   ret <2 x double> %val
 }
@@ -386,7 +386,7 @@ define <2 x double> @test_v2f64_post_load(<2 x double>* %addr) {
 define void @test_v2f64_pre_store(<2 x double> %in, <2 x double>* %addr) {
 ; CHECK-LABEL: test_v2f64_pre_store:
 ; CHECK: str q0, [x0, #80]!
-  %newaddr = getelementptr <2 x double>* %addr, i32 5
+  %newaddr = getelementptr <2 x double>, <2 x double>* %addr, i32 5
   store <2 x double> %in, <2 x double>* %newaddr, align 8
   store <2 x double>* %newaddr, <2 x double>** bitcast(i8** @ptr to <2 x double>**)
   ret void
@@ -395,7 +395,7 @@ define void @test_v2f64_pre_store(<2 x double> %in, <2 x double>* %addr) {
 define void @test_v2f64_post_store(<2 x double> %in, <2 x double>* %addr) {
 ; CHECK-LABEL: test_v2f64_post_store:
 ; CHECK: str q0, [x0], #80
-  %newaddr = getelementptr <2 x double>* %addr, i32 5
+  %newaddr = getelementptr <2 x double>, <2 x double>* %addr, i32 5
   store <2 x double> %in, <2 x double>* %addr, align 8
   store <2 x double>* %newaddr, <2 x double>** bitcast(i8** @ptr to <2 x double>**)
   ret void
@@ -407,7 +407,7 @@ define i8* @test_v16i8_post_imm_st1_lane(<16 x i8> %in, i8* %addr) {
   %elt = extractelement <16 x i8> %in, i32 3
   store i8 %elt, i8* %addr
 
-  %newaddr = getelementptr i8* %addr, i32 1
+  %newaddr = getelementptr i8, i8* %addr, i32 1
   ret i8* %newaddr
 }
 
@@ -418,7 +418,7 @@ define i8* @test_v16i8_post_reg_st1_lane(<16 x i8> %in, i8* %addr) {
   %elt = extractelement <16 x i8> %in, i32 3
   store i8 %elt, i8* %addr
 
-  %newaddr = getelementptr i8* %addr, i32 2
+  %newaddr = getelementptr i8, i8* %addr, i32 2
   ret i8* %newaddr
 }
 
@@ -429,7 +429,7 @@ define i16* @test_v8i16_post_imm_st1_lane(<8 x i16> %in, i16* %addr) {
   %elt = extractelement <8 x i16> %in, i32 3
   store i16 %elt, i16* %addr
 
-  %newaddr = getelementptr i16* %addr, i32 1
+  %newaddr = getelementptr i16, i16* %addr, i32 1
   ret i16* %newaddr
 }
 
@@ -440,7 +440,7 @@ define i16* @test_v8i16_post_reg_st1_lane(<8 x i16> %in, i16* %addr) {
   %elt = extractelement <8 x i16> %in, i32 3
   store i16 %elt, i16* %addr
 
-  %newaddr = getelementptr i16* %addr, i32 2
+  %newaddr = getelementptr i16, i16* %addr, i32 2
   ret i16* %newaddr
 }
 
@@ -450,7 +450,7 @@ define i32* @test_v4i32_post_imm_st1_lane(<4 x i32> %in, i32* %addr) {
   %elt = extractelement <4 x i32> %in, i32 3
   store i32 %elt, i32* %addr
 
-  %newaddr = getelementptr i32* %addr, i32 1
+  %newaddr = getelementptr i32, i32* %addr, i32 1
   ret i32* %newaddr
 }
 
@@ -461,7 +461,7 @@ define i32* @test_v4i32_post_reg_st1_lane(<4 x i32> %in, i32* %addr) {
   %elt = extractelement <4 x i32> %in, i32 3
   store i32 %elt, i32* %addr
 
-  %newaddr = getelementptr i32* %addr, i32 2
+  %newaddr = getelementptr i32, i32* %addr, i32 2
   ret i32* %newaddr
 }
 
@@ -471,7 +471,7 @@ define float* @test_v4f32_post_imm_st1_lane(<4 x float> %in, float* %addr) {
   %elt = extractelement <4 x float> %in, i32 3
   store float %elt, float* %addr
 
-  %newaddr = getelementptr float* %addr, i32 1
+  %newaddr = getelementptr float, float* %addr, i32 1
   ret float* %newaddr
 }
 
@@ -482,7 +482,7 @@ define float* @test_v4f32_post_reg_st1_lane(<4 x float> %in, float* %addr) {
   %elt = extractelement <4 x float> %in, i32 3
   store float %elt, float* %addr
 
-  %newaddr = getelementptr float* %addr, i32 2
+  %newaddr = getelementptr float, float* %addr, i32 2
   ret float* %newaddr
 }
 
@@ -492,7 +492,7 @@ define i64* @test_v2i64_post_imm_st1_lane(<2 x i64> %in, i64* %addr) {
   %elt = extractelement <2 x i64> %in, i64 1
   store i64 %elt, i64* %addr
 
-  %newaddr = getelementptr i64* %addr, i64 1
+  %newaddr = getelementptr i64, i64* %addr, i64 1
   ret i64* %newaddr
 }
 
@@ -503,7 +503,7 @@ define i64* @test_v2i64_post_reg_st1_lane(<2 x i64> %in, i64* %addr) {
   %elt = extractelement <2 x i64> %in, i64 1
   store i64 %elt, i64* %addr
 
-  %newaddr = getelementptr i64* %addr, i64 2
+  %newaddr = getelementptr i64, i64* %addr, i64 2
   ret i64* %newaddr
 }
 
@@ -513,7 +513,7 @@ define double* @test_v2f64_post_imm_st1_lane(<2 x double> %in, double* %addr) {
   %elt = extractelement <2 x double> %in, i32 1
   store double %elt, double* %addr
 
-  %newaddr = getelementptr double* %addr, i32 1
+  %newaddr = getelementptr double, double* %addr, i32 1
   ret double* %newaddr
 }
 
@@ -524,7 +524,7 @@ define double* @test_v2f64_post_reg_st1_lane(<2 x double> %in, double* %addr) {
   %elt = extractelement <2 x double> %in, i32 1
   store double %elt, double* %addr
 
-  %newaddr = getelementptr double* %addr, i32 2
+  %newaddr = getelementptr double, double* %addr, i32 2
   ret double* %newaddr
 }
 
@@ -534,7 +534,7 @@ define i8* @test_v8i8_post_imm_st1_lane(<8 x i8> %in, i8* %addr) {
   %elt = extractelement <8 x i8> %in, i32 3
   store i8 %elt, i8* %addr
 
-  %newaddr = getelementptr i8* %addr, i32 1
+  %newaddr = getelementptr i8, i8* %addr, i32 1
   ret i8* %newaddr
 }
 
@@ -545,7 +545,7 @@ define i8* @test_v8i8_post_reg_st1_lane(<8 x i8> %in, i8* %addr) {
   %elt = extractelement <8 x i8> %in, i32 3
   store i8 %elt, i8* %addr
 
-  %newaddr = getelementptr i8* %addr, i32 2
+  %newaddr = getelementptr i8, i8* %addr, i32 2
   ret i8* %newaddr
 }
 
@@ -555,7 +555,7 @@ define i16* @test_v4i16_post_imm_st1_lane(<4 x i16> %in, i16* %addr) {
   %elt = extractelement <4 x i16> %in, i32 3
   store i16 %elt, i16* %addr
 
-  %newaddr = getelementptr i16* %addr, i32 1
+  %newaddr = getelementptr i16, i16* %addr, i32 1
   ret i16* %newaddr
 }
 
@@ -566,7 +566,7 @@ define i16* @test_v4i16_post_reg_st1_lane(<4 x i16> %in, i16* %addr) {
   %elt = extractelement <4 x i16> %in, i32 3
   store i16 %elt, i16* %addr
 
-  %newaddr = getelementptr i16* %addr, i32 2
+  %newaddr = getelementptr i16, i16* %addr, i32 2
   ret i16* %newaddr
 }
 
@@ -576,7 +576,7 @@ define i32* @test_v2i32_post_imm_st1_lane(<2 x i32> %in, i32* %addr) {
   %elt = extractelement <2 x i32> %in, i32 1
   store i32 %elt, i32* %addr
 
-  %newaddr = getelementptr i32* %addr, i32 1
+  %newaddr = getelementptr i32, i32* %addr, i32 1
   ret i32* %newaddr
 }
 
@@ -587,7 +587,7 @@ define i32* @test_v2i32_post_reg_st1_lane(<2 x i32> %in, i32* %addr) {
   %elt = extractelement <2 x i32> %in, i32 1
   store i32 %elt, i32* %addr
 
-  %newaddr = getelementptr i32* %addr, i32 2
+  %newaddr = getelementptr i32, i32* %addr, i32 2
   ret i32* %newaddr
 }
 
@@ -597,7 +597,7 @@ define float* @test_v2f32_post_imm_st1_lane(<2 x float> %in, float* %addr) {
   %elt = extractelement <2 x float> %in, i32 1
   store float %elt, float* %addr
 
-  %newaddr = getelementptr float* %addr, i32 1
+  %newaddr = getelementptr float, float* %addr, i32 1
   ret float* %newaddr
 }
 
@@ -608,7 +608,7 @@ define float* @test_v2f32_post_reg_st1_lane(<2 x float> %in, float* %addr) {
   %elt = extractelement <2 x float> %in, i32 1
   store float %elt, float* %addr
 
-  %newaddr = getelementptr float* %addr, i32 2
+  %newaddr = getelementptr float, float* %addr, i32 2
   ret float* %newaddr
 }
 
@@ -616,7 +616,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) {
 ;CHECK-LABEL: test_v16i8_post_imm_ld2:
 ;CHECK: ld2.16b { v0, v1 }, [x0], #32
   %ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 32
+  %tmp = getelementptr i8, i8* %A, i32 32
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8> } %ld2
 }
@@ -625,7 +625,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld2(i8* %A, i8** %ptr, i64
 ;CHECK-LABEL: test_v16i8_post_reg_ld2:
 ;CHECK: ld2.16b { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8> } %ld2
 }
@@ -637,7 +637,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld2(i8* %A, i8** %ptr) {
 ;CHECK-LABEL: test_v8i8_post_imm_ld2:
 ;CHECK: ld2.8b { v0, v1 }, [x0], #16
   %ld2 = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 16
+  %tmp = getelementptr i8, i8* %A, i32 16
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8> } %ld2
 }
@@ -646,7 +646,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld2(i8* %A, i8** %ptr, i64 %in
 ;CHECK-LABEL: test_v8i8_post_reg_ld2:
 ;CHECK: ld2.8b { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8> } %ld2
 }
@@ -658,7 +658,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld2(i16* %A, i16** %ptr) {
 ;CHECK-LABEL: test_v8i16_post_imm_ld2:
 ;CHECK: ld2.8h { v0, v1 }, [x0], #32
   %ld2 = tail call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 16
+  %tmp = getelementptr i16, i16* %A, i32 16
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16> } %ld2
 }
@@ -667,7 +667,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld2(i16* %A, i16** %ptr, i6
 ;CHECK-LABEL: test_v8i16_post_reg_ld2:
 ;CHECK: ld2.8h { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = tail call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16> } %ld2
 }
@@ -679,7 +679,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld2(i16* %A, i16** %ptr) {
 ;CHECK-LABEL: test_v4i16_post_imm_ld2:
 ;CHECK: ld2.4h { v0, v1 }, [x0], #16
   %ld2 = tail call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 8
+  %tmp = getelementptr i16, i16* %A, i32 8
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16> } %ld2
 }
@@ -688,7 +688,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld2(i16* %A, i16** %ptr, i6
 ;CHECK-LABEL: test_v4i16_post_reg_ld2:
 ;CHECK: ld2.4h { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = tail call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16> } %ld2
 }
@@ -700,7 +700,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld2(i32* %A, i32** %ptr) {
 ;CHECK-LABEL: test_v4i32_post_imm_ld2:
 ;CHECK: ld2.4s { v0, v1 }, [x0], #32
   %ld2 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 8
+  %tmp = getelementptr i32, i32* %A, i32 8
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32> } %ld2
 }
@@ -709,7 +709,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld2(i32* %A, i32** %ptr, i6
 ;CHECK-LABEL: test_v4i32_post_reg_ld2:
 ;CHECK: ld2.4s { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32> } %ld2
 }
@@ -721,7 +721,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld2(i32* %A, i32** %ptr) {
 ;CHECK-LABEL: test_v2i32_post_imm_ld2:
 ;CHECK: ld2.2s { v0, v1 }, [x0], #16
   %ld2 = tail call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 4
+  %tmp = getelementptr i32, i32* %A, i32 4
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32> } %ld2
 }
@@ -730,7 +730,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld2(i32* %A, i32** %ptr, i6
 ;CHECK-LABEL: test_v2i32_post_reg_ld2:
 ;CHECK: ld2.2s { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = tail call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32> } %ld2
 }
@@ -742,7 +742,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld2(i64* %A, i64** %ptr) {
 ;CHECK-LABEL: test_v2i64_post_imm_ld2:
 ;CHECK: ld2.2d { v0, v1 }, [x0], #32
   %ld2 = tail call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 4
+  %tmp = getelementptr i64, i64* %A, i32 4
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64> } %ld2
 }
@@ -751,7 +751,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld2(i64* %A, i64** %ptr, i6
 ;CHECK-LABEL: test_v2i64_post_reg_ld2:
 ;CHECK: ld2.2d { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = tail call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64> } %ld2
 }
@@ -763,7 +763,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld2(i64* %A, i64** %ptr) {
 ;CHECK-LABEL: test_v1i64_post_imm_ld2:
 ;CHECK: ld1.1d { v0, v1 }, [x0], #16
   %ld2 = tail call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 2
+  %tmp = getelementptr i64, i64* %A, i32 2
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64> } %ld2
 }
@@ -772,7 +772,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld2(i64* %A, i64** %ptr, i6
 ;CHECK-LABEL: test_v1i64_post_reg_ld2:
 ;CHECK: ld1.1d { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = tail call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64> } %ld2
 }
@@ -784,7 +784,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld2(float* %A, float**
 ;CHECK-LABEL: test_v4f32_post_imm_ld2:
 ;CHECK: ld2.4s { v0, v1 }, [x0], #32
   %ld2 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 8
+  %tmp = getelementptr float, float* %A, i32 8
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float> } %ld2
 }
@@ -793,7 +793,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld2(float* %A, float**
 ;CHECK-LABEL: test_v4f32_post_reg_ld2:
 ;CHECK: ld2.4s { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float> } %ld2
 }
@@ -805,7 +805,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld2(float* %A, float**
 ;CHECK-LABEL: test_v2f32_post_imm_ld2:
 ;CHECK: ld2.2s { v0, v1 }, [x0], #16
   %ld2 = tail call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 4
+  %tmp = getelementptr float, float* %A, i32 4
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float> } %ld2
 }
@@ -814,7 +814,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld2(float* %A, float**
 ;CHECK-LABEL: test_v2f32_post_reg_ld2:
 ;CHECK: ld2.2s { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = tail call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float> } %ld2
 }
@@ -826,7 +826,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld2(double* %A, doubl
 ;CHECK-LABEL: test_v2f64_post_imm_ld2:
 ;CHECK: ld2.2d { v0, v1 }, [x0], #32
   %ld2 = tail call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 4
+  %tmp = getelementptr double, double* %A, i32 4
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double> } %ld2
 }
@@ -835,7 +835,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld2(double* %A, doubl
 ;CHECK-LABEL: test_v2f64_post_reg_ld2:
 ;CHECK: ld2.2d { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = tail call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double> } %ld2
 }
@@ -847,7 +847,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld2(double* %A, doubl
 ;CHECK-LABEL: test_v1f64_post_imm_ld2:
 ;CHECK: ld1.1d { v0, v1 }, [x0], #16
   %ld2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 2
+  %tmp = getelementptr double, double* %A, i32 2
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double> } %ld2
 }
@@ -856,7 +856,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld2(double* %A, doubl
 ;CHECK-LABEL: test_v1f64_post_reg_ld2:
 ;CHECK: ld1.1d { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double> } %ld2
 }
@@ -868,7 +868,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld3(i8* %A, i8**
 ;CHECK-LABEL: test_v16i8_post_imm_ld3:
 ;CHECK: ld3.16b { v0, v1, v2 }, [x0], #48
   %ld3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 48
+  %tmp = getelementptr i8, i8* %A, i32 48
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3
 }
@@ -877,7 +877,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld3(i8* %A, i8**
 ;CHECK-LABEL: test_v16i8_post_reg_ld3:
 ;CHECK: ld3.16b { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3
 }
@@ -889,7 +889,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld3(i8* %A, i8** %pt
 ;CHECK-LABEL: test_v8i8_post_imm_ld3:
 ;CHECK: ld3.8b { v0, v1, v2 }, [x0], #24
   %ld3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 24
+  %tmp = getelementptr i8, i8* %A, i32 24
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3
 }
@@ -898,7 +898,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld3(i8* %A, i8** %pt
 ;CHECK-LABEL: test_v8i8_post_reg_ld3:
 ;CHECK: ld3.8b { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3
 }
@@ -910,7 +910,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld3(i16* %A, i16
 ;CHECK-LABEL: test_v8i16_post_imm_ld3:
 ;CHECK: ld3.8h { v0, v1, v2 }, [x0], #48
   %ld3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 24
+  %tmp = getelementptr i16, i16* %A, i32 24
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3
 }
@@ -919,7 +919,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld3(i16* %A, i16
 ;CHECK-LABEL: test_v8i16_post_reg_ld3:
 ;CHECK: ld3.8h { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3
 }
@@ -931,7 +931,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld3(i16* %A, i16
 ;CHECK-LABEL: test_v4i16_post_imm_ld3:
 ;CHECK: ld3.4h { v0, v1, v2 }, [x0], #24
   %ld3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 12
+  %tmp = getelementptr i16, i16* %A, i32 12
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3
 }
@@ -940,7 +940,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld3(i16* %A, i16
 ;CHECK-LABEL: test_v4i16_post_reg_ld3:
 ;CHECK: ld3.4h { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3
 }
@@ -952,7 +952,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld3(i32* %A, i32
 ;CHECK-LABEL: test_v4i32_post_imm_ld3:
 ;CHECK: ld3.4s { v0, v1, v2 }, [x0], #48
   %ld3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 12
+  %tmp = getelementptr i32, i32* %A, i32 12
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3
 }
@@ -961,7 +961,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld3(i32* %A, i32
 ;CHECK-LABEL: test_v4i32_post_reg_ld3:
 ;CHECK: ld3.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3
 }
@@ -973,7 +973,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld3(i32* %A, i32
 ;CHECK-LABEL: test_v2i32_post_imm_ld3:
 ;CHECK: ld3.2s { v0, v1, v2 }, [x0], #24
   %ld3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 6
+  %tmp = getelementptr i32, i32* %A, i32 6
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3
 }
@@ -982,7 +982,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld3(i32* %A, i32
 ;CHECK-LABEL: test_v2i32_post_reg_ld3:
 ;CHECK: ld3.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3
 }
@@ -994,7 +994,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld3(i64* %A, i64
 ;CHECK-LABEL: test_v2i64_post_imm_ld3:
 ;CHECK: ld3.2d { v0, v1, v2 }, [x0], #48
   %ld3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 6
+  %tmp = getelementptr i64, i64* %A, i32 6
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3
 }
@@ -1003,7 +1003,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld3(i64* %A, i64
 ;CHECK-LABEL: test_v2i64_post_reg_ld3:
 ;CHECK: ld3.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3
 }
@@ -1015,7 +1015,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld3(i64* %A, i64
 ;CHECK-LABEL: test_v1i64_post_imm_ld3:
 ;CHECK: ld1.1d { v0, v1, v2 }, [x0], #24
   %ld3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 3
+  %tmp = getelementptr i64, i64* %A, i32 3
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3
 }
@@ -1024,7 +1024,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld3(i64* %A, i64
 ;CHECK-LABEL: test_v1i64_post_reg_ld3:
 ;CHECK: ld1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3
 }
@@ -1036,7 +1036,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld3(float*
 ;CHECK-LABEL: test_v4f32_post_imm_ld3:
 ;CHECK: ld3.4s { v0, v1, v2 }, [x0], #48
   %ld3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 12
+  %tmp = getelementptr float, float* %A, i32 12
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float> } %ld3
 }
@@ -1045,7 +1045,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld3(float*
 ;CHECK-LABEL: test_v4f32_post_reg_ld3:
 ;CHECK: ld3.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float> } %ld3
 }
@@ -1057,7 +1057,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld3(float*
 ;CHECK-LABEL: test_v2f32_post_imm_ld3:
 ;CHECK: ld3.2s { v0, v1, v2 }, [x0], #24
   %ld3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 6
+  %tmp = getelementptr float, float* %A, i32 6
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float> } %ld3
 }
@@ -1066,7 +1066,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld3(float*
 ;CHECK-LABEL: test_v2f32_post_reg_ld3:
 ;CHECK: ld3.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float> } %ld3
 }
@@ -1078,7 +1078,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld3(dou
 ;CHECK-LABEL: test_v2f64_post_imm_ld3:
 ;CHECK: ld3.2d { v0, v1, v2 }, [x0], #48
   %ld3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 6
+  %tmp = getelementptr double, double* %A, i32 6
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double> } %ld3
 }
@@ -1087,7 +1087,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld3(dou
 ;CHECK-LABEL: test_v2f64_post_reg_ld3:
 ;CHECK: ld3.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double> } %ld3
 }
@@ -1099,7 +1099,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld3(dou
 ;CHECK-LABEL: test_v1f64_post_imm_ld3:
 ;CHECK: ld1.1d { v0, v1, v2 }, [x0], #24
   %ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 3
+  %tmp = getelementptr double, double* %A, i32 3
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double> } %ld3
 }
@@ -1108,7 +1108,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld3(dou
 ;CHECK-LABEL: test_v1f64_post_reg_ld3:
 ;CHECK: ld1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double> } %ld3
 }
@@ -1120,7 +1120,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld4(i
 ;CHECK-LABEL: test_v16i8_post_imm_ld4:
 ;CHECK: ld4.16b { v0, v1, v2, v3 }, [x0], #64
   %ld4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 64
+  %tmp = getelementptr i8, i8* %A, i32 64
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4
 }
@@ -1129,7 +1129,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld4(i
 ;CHECK-LABEL: test_v16i8_post_reg_ld4:
 ;CHECK: ld4.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4
 }
@@ -1141,7 +1141,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld4(i8* %A
 ;CHECK-LABEL: test_v8i8_post_imm_ld4:
 ;CHECK: ld4.8b { v0, v1, v2, v3 }, [x0], #32
   %ld4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 32
+  %tmp = getelementptr i8, i8* %A, i32 32
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4
 }
@@ -1150,7 +1150,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld4(i8* %A
 ;CHECK-LABEL: test_v8i8_post_reg_ld4:
 ;CHECK: ld4.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4
 }
@@ -1162,7 +1162,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld4(i
 ;CHECK-LABEL: test_v8i16_post_imm_ld4:
 ;CHECK: ld4.8h { v0, v1, v2, v3 }, [x0], #64
   %ld4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 32
+  %tmp = getelementptr i16, i16* %A, i32 32
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4
 }
@@ -1171,7 +1171,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld4(i
 ;CHECK-LABEL: test_v8i16_post_reg_ld4:
 ;CHECK: ld4.8h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4
 }
@@ -1183,7 +1183,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld4(i
 ;CHECK-LABEL: test_v4i16_post_imm_ld4:
 ;CHECK: ld4.4h { v0, v1, v2, v3 }, [x0], #32
   %ld4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 16
+  %tmp = getelementptr i16, i16* %A, i32 16
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4
 }
@@ -1192,7 +1192,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld4(i
 ;CHECK-LABEL: test_v4i16_post_reg_ld4:
 ;CHECK: ld4.4h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4
 }
@@ -1204,7 +1204,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld4(i
 ;CHECK-LABEL: test_v4i32_post_imm_ld4:
 ;CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], #64
   %ld4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 16
+  %tmp = getelementptr i32, i32* %A, i32 16
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4
 }
@@ -1213,7 +1213,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld4(i
 ;CHECK-LABEL: test_v4i32_post_reg_ld4:
 ;CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4
 }
@@ -1225,7 +1225,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld4(i
 ;CHECK-LABEL: test_v2i32_post_imm_ld4:
 ;CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], #32
   %ld4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 8
+  %tmp = getelementptr i32, i32* %A, i32 8
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4
 }
@@ -1234,7 +1234,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld4(i
 ;CHECK-LABEL: test_v2i32_post_reg_ld4:
 ;CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4
 }
@@ -1246,7 +1246,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld4(i
 ;CHECK-LABEL: test_v2i64_post_imm_ld4:
 ;CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], #64
   %ld4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 8
+  %tmp = getelementptr i64, i64* %A, i32 8
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4
 }
@@ -1255,7 +1255,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld4(i
 ;CHECK-LABEL: test_v2i64_post_reg_ld4:
 ;CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4
 }
@@ -1267,7 +1267,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld4(i
 ;CHECK-LABEL: test_v1i64_post_imm_ld4:
 ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], #32
   %ld4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 4
+  %tmp = getelementptr i64, i64* %A, i32 4
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4
 }
@@ -1276,7 +1276,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld4(i
 ;CHECK-LABEL: test_v1i64_post_reg_ld4:
 ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4
 }
@@ -1288,7 +1288,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_i
 ;CHECK-LABEL: test_v4f32_post_imm_ld4:
 ;CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], #64
   %ld4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 16
+  %tmp = getelementptr float, float* %A, i32 16
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4
 }
@@ -1297,7 +1297,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_r
 ;CHECK-LABEL: test_v4f32_post_reg_ld4:
 ;CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4
 }
@@ -1309,7 +1309,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_i
 ;CHECK-LABEL: test_v2f32_post_imm_ld4:
 ;CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], #32
   %ld4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 8
+  %tmp = getelementptr float, float* %A, i32 8
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4
 }
@@ -1318,7 +1318,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_r
 ;CHECK-LABEL: test_v2f32_post_reg_ld4:
 ;CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4
 }
@@ -1330,7 +1330,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po
 ;CHECK-LABEL: test_v2f64_post_imm_ld4:
 ;CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], #64
   %ld4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 8
+  %tmp = getelementptr double, double* %A, i32 8
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4
 }
@@ -1339,7 +1339,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po
 ;CHECK-LABEL: test_v2f64_post_reg_ld4:
 ;CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4
 }
@@ -1351,7 +1351,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po
 ;CHECK-LABEL: test_v1f64_post_imm_ld4:
 ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], #32
   %ld4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 4
+  %tmp = getelementptr double, double* %A, i32 4
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4
 }
@@ -1360,7 +1360,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po
 ;CHECK-LABEL: test_v1f64_post_reg_ld4:
 ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4
 }
@@ -1371,7 +1371,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x2(i8* %A, i8** %ptr) {
 ;CHECK-LABEL: test_v16i8_post_imm_ld1x2:
 ;CHECK: ld1.16b { v0, v1 }, [x0], #32
   %ld1x2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x2.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 32
+  %tmp = getelementptr i8, i8* %A, i32 32
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8> } %ld1x2
 }
@@ -1380,7 +1380,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld1x2(i8* %A, i8** %ptr, i6
 ;CHECK-LABEL: test_v16i8_post_reg_ld1x2:
 ;CHECK: ld1.16b { v0, v1 }, [x0], x{{[0-9]+}}
   %ld1x2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x2.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8> } %ld1x2
 }
@@ -1392,7 +1392,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld1x2(i8* %A, i8** %ptr) {
 ;CHECK-LABEL: test_v8i8_post_imm_ld1x2:
 ;CHECK: ld1.8b { v0, v1 }, [x0], #16
   %ld1x2 = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x2.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 16
+  %tmp = getelementptr i8, i8* %A, i32 16
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8> } %ld1x2
 }
@@ -1401,7 +1401,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld1x2(i8* %A, i8** %ptr, i64 %
 ;CHECK-LABEL: test_v8i8_post_reg_ld1x2:
 ;CHECK: ld1.8b { v0, v1 }, [x0], x{{[0-9]+}}
   %ld1x2 = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x2.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8> } %ld1x2
 }
@@ -1413,7 +1413,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld1x2(i16* %A, i16** %ptr)
 ;CHECK-LABEL: test_v8i16_post_imm_ld1x2:
 ;CHECK: ld1.8h { v0, v1 }, [x0], #32
   %ld1x2 = tail call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x2.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 16
+  %tmp = getelementptr i16, i16* %A, i32 16
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16> } %ld1x2
 }
@@ -1422,7 +1422,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld1x2(i16* %A, i16** %ptr,
 ;CHECK-LABEL: test_v8i16_post_reg_ld1x2:
 ;CHECK: ld1.8h { v0, v1 }, [x0], x{{[0-9]+}}
   %ld1x2 = tail call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x2.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16> } %ld1x2
 }
@@ -1434,7 +1434,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld1x2(i16* %A, i16** %ptr)
 ;CHECK-LABEL: test_v4i16_post_imm_ld1x2:
 ;CHECK: ld1.4h { v0, v1 }, [x0], #16
   %ld1x2 = tail call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 8
+  %tmp = getelementptr i16, i16* %A, i32 8
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16> } %ld1x2
 }
@@ -1443,7 +1443,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld1x2(i16* %A, i16** %ptr,
 ;CHECK-LABEL: test_v4i16_post_reg_ld1x2:
 ;CHECK: ld1.4h { v0, v1 }, [x0], x{{[0-9]+}}
   %ld1x2 = tail call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16> } %ld1x2
 }
@@ -1455,7 +1455,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld1x2(i32* %A, i32** %ptr)
 ;CHECK-LABEL: test_v4i32_post_imm_ld1x2:
 ;CHECK: ld1.4s { v0, v1 }, [x0], #32
   %ld1x2 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x2.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 8
+  %tmp = getelementptr i32, i32* %A, i32 8
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32> } %ld1x2
 }
@@ -1464,7 +1464,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld1x2(i32* %A, i32** %ptr,
 ;CHECK-LABEL: test_v4i32_post_reg_ld1x2:
 ;CHECK: ld1.4s { v0, v1 }, [x0], x{{[0-9]+}}
   %ld1x2 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x2.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32> } %ld1x2
 }
@@ -1476,7 +1476,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld1x2(i32* %A, i32** %ptr)
 ;CHECK-LABEL: test_v2i32_post_imm_ld1x2:
 ;CHECK: ld1.2s { v0, v1 }, [x0], #16
   %ld1x2 = tail call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x2.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 4
+  %tmp = getelementptr i32, i32* %A, i32 4
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32> } %ld1x2
 }
@@ -1485,7 +1485,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld1x2(i32* %A, i32** %ptr,
 ;CHECK-LABEL: test_v2i32_post_reg_ld1x2:
 ;CHECK: ld1.2s { v0, v1 }, [x0], x{{[0-9]+}}
   %ld1x2 = tail call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x2.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32> } %ld1x2
 }
@@ -1497,7 +1497,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld1x2(i64* %A, i64** %ptr)
 ;CHECK-LABEL: test_v2i64_post_imm_ld1x2:
 ;CHECK: ld1.2d { v0, v1 }, [x0], #32
   %ld1x2 = tail call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x2.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 4
+  %tmp = getelementptr i64, i64* %A, i32 4
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64> } %ld1x2
 }
@@ -1506,7 +1506,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld1x2(i64* %A, i64** %ptr,
 ;CHECK-LABEL: test_v2i64_post_reg_ld1x2:
 ;CHECK: ld1.2d { v0, v1 }, [x0], x{{[0-9]+}}
   %ld1x2 = tail call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x2.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64> } %ld1x2
 }
@@ -1518,7 +1518,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld1x2(i64* %A, i64** %ptr)
 ;CHECK-LABEL: test_v1i64_post_imm_ld1x2:
 ;CHECK: ld1.1d { v0, v1 }, [x0], #16
   %ld1x2 = tail call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x2.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 2
+  %tmp = getelementptr i64, i64* %A, i32 2
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64> } %ld1x2
 }
@@ -1527,7 +1527,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld1x2(i64* %A, i64** %ptr,
 ;CHECK-LABEL: test_v1i64_post_reg_ld1x2:
 ;CHECK: ld1.1d { v0, v1 }, [x0], x{{[0-9]+}}
   %ld1x2 = tail call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x2.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64> } %ld1x2
 }
@@ -1539,7 +1539,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld1x2(float* %A, float*
 ;CHECK-LABEL: test_v4f32_post_imm_ld1x2:
 ;CHECK: ld1.4s { v0, v1 }, [x0], #32
   %ld1x2 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x2.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 8
+  %tmp = getelementptr float, float* %A, i32 8
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float> } %ld1x2
 }
@@ -1548,7 +1548,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld1x2(float* %A, float*
 ;CHECK-LABEL: test_v4f32_post_reg_ld1x2:
 ;CHECK: ld1.4s { v0, v1 }, [x0], x{{[0-9]+}}
   %ld1x2 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x2.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float> } %ld1x2
 }
@@ -1560,7 +1560,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld1x2(float* %A, float*
 ;CHECK-LABEL: test_v2f32_post_imm_ld1x2:
 ;CHECK: ld1.2s { v0, v1 }, [x0], #16
   %ld1x2 = tail call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 4
+  %tmp = getelementptr float, float* %A, i32 4
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float> } %ld1x2
 }
@@ -1569,7 +1569,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld1x2(float* %A, float*
 ;CHECK-LABEL: test_v2f32_post_reg_ld1x2:
 ;CHECK: ld1.2s { v0, v1 }, [x0], x{{[0-9]+}}
   %ld1x2 = tail call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float> } %ld1x2
 }
@@ -1581,7 +1581,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld1x2(double* %A, dou
 ;CHECK-LABEL: test_v2f64_post_imm_ld1x2:
 ;CHECK: ld1.2d { v0, v1 }, [x0], #32
   %ld1x2 = tail call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x2.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 4
+  %tmp = getelementptr double, double* %A, i32 4
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double> } %ld1x2
 }
@@ -1590,7 +1590,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld1x2(double* %A, dou
 ;CHECK-LABEL: test_v2f64_post_reg_ld1x2:
 ;CHECK: ld1.2d { v0, v1 }, [x0], x{{[0-9]+}}
   %ld1x2 = tail call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x2.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double> } %ld1x2
 }
@@ -1602,7 +1602,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld1x2(double* %A, dou
 ;CHECK-LABEL: test_v1f64_post_imm_ld1x2:
 ;CHECK: ld1.1d { v0, v1 }, [x0], #16
   %ld1x2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 2
+  %tmp = getelementptr double, double* %A, i32 2
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double> } %ld1x2
 }
@@ -1611,7 +1611,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld1x2(double* %A, dou
 ;CHECK-LABEL: test_v1f64_post_reg_ld1x2:
 ;CHECK: ld1.1d { v0, v1 }, [x0], x{{[0-9]+}}
   %ld1x2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double> } %ld1x2
 }
@@ -1623,7 +1623,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x3(i8* %A, i8
 ;CHECK-LABEL: test_v16i8_post_imm_ld1x3:
 ;CHECK: ld1.16b { v0, v1, v2 }, [x0], #48
   %ld1x3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x3.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 48
+  %tmp = getelementptr i8, i8* %A, i32 48
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld1x3
 }
@@ -1632,7 +1632,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld1x3(i8* %A, i8
 ;CHECK-LABEL: test_v16i8_post_reg_ld1x3:
 ;CHECK: ld1.16b { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld1x3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x3.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld1x3
 }
@@ -1644,7 +1644,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld1x3(i8* %A, i8** %
 ;CHECK-LABEL: test_v8i8_post_imm_ld1x3:
 ;CHECK: ld1.8b { v0, v1, v2 }, [x0], #24
   %ld1x3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x3.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 24
+  %tmp = getelementptr i8, i8* %A, i32 24
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld1x3
 }
@@ -1653,7 +1653,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld1x3(i8* %A, i8** %
 ;CHECK-LABEL: test_v8i8_post_reg_ld1x3:
 ;CHECK: ld1.8b { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld1x3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x3.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld1x3
 }
@@ -1665,7 +1665,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld1x3(i16* %A, i
 ;CHECK-LABEL: test_v8i16_post_imm_ld1x3:
 ;CHECK: ld1.8h { v0, v1, v2 }, [x0], #48
   %ld1x3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x3.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 24
+  %tmp = getelementptr i16, i16* %A, i32 24
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld1x3
 }
@@ -1674,7 +1674,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld1x3(i16* %A, i
 ;CHECK-LABEL: test_v8i16_post_reg_ld1x3:
 ;CHECK: ld1.8h { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld1x3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x3.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld1x3
 }
@@ -1686,7 +1686,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld1x3(i16* %A, i
 ;CHECK-LABEL: test_v4i16_post_imm_ld1x3:
 ;CHECK: ld1.4h { v0, v1, v2 }, [x0], #24
   %ld1x3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x3.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 12
+  %tmp = getelementptr i16, i16* %A, i32 12
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld1x3
 }
@@ -1695,7 +1695,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld1x3(i16* %A, i
 ;CHECK-LABEL: test_v4i16_post_reg_ld1x3:
 ;CHECK: ld1.4h { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld1x3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x3.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld1x3
 }
@@ -1707,7 +1707,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld1x3(i32* %A, i
 ;CHECK-LABEL: test_v4i32_post_imm_ld1x3:
 ;CHECK: ld1.4s { v0, v1, v2 }, [x0], #48
   %ld1x3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x3.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 12
+  %tmp = getelementptr i32, i32* %A, i32 12
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld1x3
 }
@@ -1716,7 +1716,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld1x3(i32* %A, i
 ;CHECK-LABEL: test_v4i32_post_reg_ld1x3:
 ;CHECK: ld1.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld1x3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x3.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld1x3
 }
@@ -1728,7 +1728,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld1x3(i32* %A, i
 ;CHECK-LABEL: test_v2i32_post_imm_ld1x3:
 ;CHECK: ld1.2s { v0, v1, v2 }, [x0], #24
   %ld1x3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x3.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 6
+  %tmp = getelementptr i32, i32* %A, i32 6
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld1x3
 }
@@ -1737,7 +1737,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld1x3(i32* %A, i
 ;CHECK-LABEL: test_v2i32_post_reg_ld1x3:
 ;CHECK: ld1.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld1x3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x3.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld1x3
 }
@@ -1749,7 +1749,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld1x3(i64* %A, i
 ;CHECK-LABEL: test_v2i64_post_imm_ld1x3:
 ;CHECK: ld1.2d { v0, v1, v2 }, [x0], #48
   %ld1x3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x3.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 6
+  %tmp = getelementptr i64, i64* %A, i32 6
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld1x3
 }
@@ -1758,7 +1758,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld1x3(i64* %A, i
 ;CHECK-LABEL: test_v2i64_post_reg_ld1x3:
 ;CHECK: ld1.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld1x3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x3.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld1x3
 }
@@ -1770,7 +1770,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld1x3(i64* %A, i
 ;CHECK-LABEL: test_v1i64_post_imm_ld1x3:
 ;CHECK: ld1.1d { v0, v1, v2 }, [x0], #24
   %ld1x3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x3.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 3
+  %tmp = getelementptr i64, i64* %A, i32 3
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld1x3
 }
@@ -1779,7 +1779,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld1x3(i64* %A, i
 ;CHECK-LABEL: test_v1i64_post_reg_ld1x3:
 ;CHECK: ld1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld1x3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x3.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld1x3
 }
@@ -1791,7 +1791,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld1x3(floa
 ;CHECK-LABEL: test_v4f32_post_imm_ld1x3:
 ;CHECK: ld1.4s { v0, v1, v2 }, [x0], #48
   %ld1x3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x3.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 12
+  %tmp = getelementptr float, float* %A, i32 12
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float> } %ld1x3
 }
@@ -1800,7 +1800,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld1x3(floa
 ;CHECK-LABEL: test_v4f32_post_reg_ld1x3:
 ;CHECK: ld1.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld1x3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x3.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float> } %ld1x3
 }
@@ -1812,7 +1812,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld1x3(floa
 ;CHECK-LABEL: test_v2f32_post_imm_ld1x3:
 ;CHECK: ld1.2s { v0, v1, v2 }, [x0], #24
   %ld1x3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 6
+  %tmp = getelementptr float, float* %A, i32 6
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float> } %ld1x3
 }
@@ -1821,7 +1821,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld1x3(floa
 ;CHECK-LABEL: test_v2f32_post_reg_ld1x3:
 ;CHECK: ld1.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld1x3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float> } %ld1x3
 }
@@ -1833,7 +1833,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld1x3(d
 ;CHECK-LABEL: test_v2f64_post_imm_ld1x3:
 ;CHECK: ld1.2d { v0, v1, v2 }, [x0], #48
   %ld1x3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x3.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 6
+  %tmp = getelementptr double, double* %A, i32 6
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double> } %ld1x3
 }
@@ -1842,7 +1842,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld1x3(d
 ;CHECK-LABEL: test_v2f64_post_reg_ld1x3:
 ;CHECK: ld1.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld1x3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x3.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double> } %ld1x3
 }
@@ -1854,7 +1854,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld1x3(d
 ;CHECK-LABEL: test_v1f64_post_imm_ld1x3:
 ;CHECK: ld1.1d { v0, v1, v2 }, [x0], #24
   %ld1x3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x3.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 3
+  %tmp = getelementptr double, double* %A, i32 3
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double> } %ld1x3
 }
@@ -1863,7 +1863,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld1x3(d
 ;CHECK-LABEL: test_v1f64_post_reg_ld1x3:
 ;CHECK: ld1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld1x3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x3.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double> } %ld1x3
 }
@@ -1875,7 +1875,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x4
 ;CHECK-LABEL: test_v16i8_post_imm_ld1x4:
 ;CHECK: ld1.16b { v0, v1, v2, v3 }, [x0], #64
   %ld1x4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x4.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 64
+  %tmp = getelementptr i8, i8* %A, i32 64
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld1x4
 }
@@ -1884,7 +1884,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld1x4
 ;CHECK-LABEL: test_v16i8_post_reg_ld1x4:
 ;CHECK: ld1.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld1x4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x4.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld1x4
 }
@@ -1896,7 +1896,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld1x4(i8*
 ;CHECK-LABEL: test_v8i8_post_imm_ld1x4:
 ;CHECK: ld1.8b { v0, v1, v2, v3 }, [x0], #32
   %ld1x4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x4.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 32
+  %tmp = getelementptr i8, i8* %A, i32 32
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld1x4
 }
@@ -1905,7 +1905,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld1x4(i8*
 ;CHECK-LABEL: test_v8i8_post_reg_ld1x4:
 ;CHECK: ld1.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld1x4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x4.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld1x4
 }
@@ -1917,7 +1917,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld1x4
 ;CHECK-LABEL: test_v8i16_post_imm_ld1x4:
 ;CHECK: ld1.8h { v0, v1, v2, v3 }, [x0], #64
   %ld1x4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x4.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 32
+  %tmp = getelementptr i16, i16* %A, i32 32
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld1x4
 }
@@ -1926,7 +1926,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld1x4
 ;CHECK-LABEL: test_v8i16_post_reg_ld1x4:
 ;CHECK: ld1.8h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld1x4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x4.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld1x4
 }
@@ -1938,7 +1938,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld1x4
 ;CHECK-LABEL: test_v4i16_post_imm_ld1x4:
 ;CHECK: ld1.4h { v0, v1, v2, v3 }, [x0], #32
   %ld1x4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x4.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 16
+  %tmp = getelementptr i16, i16* %A, i32 16
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld1x4
 }
@@ -1947,7 +1947,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld1x4
 ;CHECK-LABEL: test_v4i16_post_reg_ld1x4:
 ;CHECK: ld1.4h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld1x4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x4.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld1x4
 }
@@ -1959,7 +1959,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld1x4
 ;CHECK-LABEL: test_v4i32_post_imm_ld1x4:
 ;CHECK: ld1.4s { v0, v1, v2, v3 }, [x0], #64
   %ld1x4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x4.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 16
+  %tmp = getelementptr i32, i32* %A, i32 16
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld1x4
 }
@@ -1968,7 +1968,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld1x4
 ;CHECK-LABEL: test_v4i32_post_reg_ld1x4:
 ;CHECK: ld1.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld1x4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x4.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld1x4
 }
@@ -1980,7 +1980,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld1x4
 ;CHECK-LABEL: test_v2i32_post_imm_ld1x4:
 ;CHECK: ld1.2s { v0, v1, v2, v3 }, [x0], #32
   %ld1x4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x4.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 8
+  %tmp = getelementptr i32, i32* %A, i32 8
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld1x4
 }
@@ -1989,7 +1989,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld1x4
 ;CHECK-LABEL: test_v2i32_post_reg_ld1x4:
 ;CHECK: ld1.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld1x4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x4.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld1x4
 }
@@ -2001,7 +2001,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld1x4
 ;CHECK-LABEL: test_v2i64_post_imm_ld1x4:
 ;CHECK: ld1.2d { v0, v1, v2, v3 }, [x0], #64
   %ld1x4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x4.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 8
+  %tmp = getelementptr i64, i64* %A, i32 8
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld1x4
 }
@@ -2010,7 +2010,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld1x4
 ;CHECK-LABEL: test_v2i64_post_reg_ld1x4:
 ;CHECK: ld1.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld1x4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x4.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld1x4
 }
@@ -2022,7 +2022,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld1x4
 ;CHECK-LABEL: test_v1i64_post_imm_ld1x4:
 ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], #32
   %ld1x4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x4.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 4
+  %tmp = getelementptr i64, i64* %A, i32 4
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld1x4
 }
@@ -2031,7 +2031,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld1x4
 ;CHECK-LABEL: test_v1i64_post_reg_ld1x4:
 ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld1x4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x4.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld1x4
 }
@@ -2043,7 +2043,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_i
 ;CHECK-LABEL: test_v4f32_post_imm_ld1x4:
 ;CHECK: ld1.4s { v0, v1, v2, v3 }, [x0], #64
   %ld1x4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x4.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 16
+  %tmp = getelementptr float, float* %A, i32 16
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld1x4
 }
@@ -2052,7 +2052,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_r
 ;CHECK-LABEL: test_v4f32_post_reg_ld1x4:
 ;CHECK: ld1.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld1x4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x4.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld1x4
 }
@@ -2064,7 +2064,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_i
 ;CHECK-LABEL: test_v2f32_post_imm_ld1x4:
 ;CHECK: ld1.2s { v0, v1, v2, v3 }, [x0], #32
   %ld1x4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 8
+  %tmp = getelementptr float, float* %A, i32 8
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld1x4
 }
@@ -2073,7 +2073,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_r
 ;CHECK-LABEL: test_v2f32_post_reg_ld1x4:
 ;CHECK: ld1.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld1x4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld1x4
 }
@@ -2085,7 +2085,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po
 ;CHECK-LABEL: test_v2f64_post_imm_ld1x4:
 ;CHECK: ld1.2d { v0, v1, v2, v3 }, [x0], #64
   %ld1x4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x4.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 8
+  %tmp = getelementptr double, double* %A, i32 8
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld1x4
 }
@@ -2094,7 +2094,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po
 ;CHECK-LABEL: test_v2f64_post_reg_ld1x4:
 ;CHECK: ld1.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld1x4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x4.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld1x4
 }
@@ -2106,7 +2106,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po
 ;CHECK-LABEL: test_v1f64_post_imm_ld1x4:
 ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], #32
   %ld1x4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x4.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 4
+  %tmp = getelementptr double, double* %A, i32 4
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld1x4
 }
@@ -2115,7 +2115,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po
 ;CHECK-LABEL: test_v1f64_post_reg_ld1x4:
 ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld1x4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x4.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld1x4
 }
@@ -2127,7 +2127,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2r(i8* %A, i8** %ptr) nou
 ;CHECK-LABEL: test_v16i8_post_imm_ld2r:
 ;CHECK: ld2r.16b { v0, v1 }, [x0], #2
   %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 2
+  %tmp = getelementptr i8, i8* %A, i32 2
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8> } %ld2
 }
@@ -2136,7 +2136,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld2r(i8* %A, i8** %ptr, i64
 ;CHECK-LABEL: test_v16i8_post_reg_ld2r:
 ;CHECK: ld2r.16b { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8> } %ld2
 }
@@ -2148,7 +2148,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld2r(i8* %A, i8** %ptr) nounwi
 ;CHECK-LABEL: test_v8i8_post_imm_ld2r:
 ;CHECK: ld2r.8b { v0, v1 }, [x0], #2
   %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 2
+  %tmp = getelementptr i8, i8* %A, i32 2
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8> } %ld2
 }
@@ -2157,7 +2157,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld2r(i8* %A, i8** %ptr, i64 %i
 ;CHECK-LABEL: test_v8i8_post_reg_ld2r:
 ;CHECK: ld2r.8b { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8> } %ld2
 }
@@ -2169,7 +2169,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld2r(i16* %A, i16** %ptr) n
 ;CHECK-LABEL: test_v8i16_post_imm_ld2r:
 ;CHECK: ld2r.8h { v0, v1 }, [x0], #4
   %ld2 = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2r.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 2
+  %tmp = getelementptr i16, i16* %A, i32 2
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16> } %ld2
 }
@@ -2178,7 +2178,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld2r(i16* %A, i16** %ptr, i
 ;CHECK-LABEL: test_v8i16_post_reg_ld2r:
 ;CHECK: ld2r.8h { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2r.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16> } %ld2
 }
@@ -2190,7 +2190,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld2r(i16* %A, i16** %ptr) n
 ;CHECK-LABEL: test_v4i16_post_imm_ld2r:
 ;CHECK: ld2r.4h { v0, v1 }, [x0], #4
   %ld2 = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 2
+  %tmp = getelementptr i16, i16* %A, i32 2
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16> } %ld2
 }
@@ -2199,7 +2199,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld2r(i16* %A, i16** %ptr, i
 ;CHECK-LABEL: test_v4i16_post_reg_ld2r:
 ;CHECK: ld2r.4h { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16> } %ld2
 }
@@ -2211,7 +2211,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld2r(i32* %A, i32** %ptr) n
 ;CHECK-LABEL: test_v4i32_post_imm_ld2r:
 ;CHECK: ld2r.4s { v0, v1 }, [x0], #8
   %ld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2r.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 2
+  %tmp = getelementptr i32, i32* %A, i32 2
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32> } %ld2
 }
@@ -2220,7 +2220,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld2r(i32* %A, i32** %ptr, i
 ;CHECK-LABEL: test_v4i32_post_reg_ld2r:
 ;CHECK: ld2r.4s { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2r.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32> } %ld2
 }
@@ -2231,7 +2231,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld2r(i32* %A, i32** %ptr) n
 ;CHECK-LABEL: test_v2i32_post_imm_ld2r:
 ;CHECK: ld2r.2s { v0, v1 }, [x0], #8
   %ld2 = call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2r.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 2
+  %tmp = getelementptr i32, i32* %A, i32 2
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32> } %ld2
 }
@@ -2240,7 +2240,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld2r(i32* %A, i32** %ptr, i
 ;CHECK-LABEL: test_v2i32_post_reg_ld2r:
 ;CHECK: ld2r.2s { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2r.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32> } %ld2
 }
@@ -2252,7 +2252,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld2r(i64* %A, i64** %ptr) n
 ;CHECK-LABEL: test_v2i64_post_imm_ld2r:
 ;CHECK: ld2r.2d { v0, v1 }, [x0], #16
   %ld2 = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2r.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 2
+  %tmp = getelementptr i64, i64* %A, i32 2
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64> } %ld2
 }
@@ -2261,7 +2261,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld2r(i64* %A, i64** %ptr, i
 ;CHECK-LABEL: test_v2i64_post_reg_ld2r:
 ;CHECK: ld2r.2d { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2r.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64> } %ld2
 }
@@ -2272,7 +2272,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld2r(i64* %A, i64** %ptr) n
 ;CHECK-LABEL: test_v1i64_post_imm_ld2r:
 ;CHECK: ld2r.1d { v0, v1 }, [x0], #16
   %ld2 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2r.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 2
+  %tmp = getelementptr i64, i64* %A, i32 2
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64> } %ld2
 }
@@ -2281,7 +2281,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld2r(i64* %A, i64** %ptr, i
 ;CHECK-LABEL: test_v1i64_post_reg_ld2r:
 ;CHECK: ld2r.1d { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2r.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64> } %ld2
 }
@@ -2293,7 +2293,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld2r(float* %A, float**
 ;CHECK-LABEL: test_v4f32_post_imm_ld2r:
 ;CHECK: ld2r.4s { v0, v1 }, [x0], #8
   %ld2 = call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2r.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 2
+  %tmp = getelementptr float, float* %A, i32 2
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float> } %ld2
 }
@@ -2302,7 +2302,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld2r(float* %A, float**
 ;CHECK-LABEL: test_v4f32_post_reg_ld2r:
 ;CHECK: ld2r.4s { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2r.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float> } %ld2
 }
@@ -2313,7 +2313,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld2r(float* %A, float**
 ;CHECK-LABEL: test_v2f32_post_imm_ld2r:
 ;CHECK: ld2r.2s { v0, v1 }, [x0], #8
   %ld2 = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2r.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 2
+  %tmp = getelementptr float, float* %A, i32 2
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float> } %ld2
 }
@@ -2322,7 +2322,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld2r(float* %A, float**
 ;CHECK-LABEL: test_v2f32_post_reg_ld2r:
 ;CHECK: ld2r.2s { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2r.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float> } %ld2
 }
@@ -2334,7 +2334,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld2r(double* %A, doub
 ;CHECK-LABEL: test_v2f64_post_imm_ld2r:
 ;CHECK: ld2r.2d { v0, v1 }, [x0], #16
   %ld2 = call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2r.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 2
+  %tmp = getelementptr double, double* %A, i32 2
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double> } %ld2
 }
@@ -2343,7 +2343,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld2r(double* %A, doub
 ;CHECK-LABEL: test_v2f64_post_reg_ld2r:
 ;CHECK: ld2r.2d { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2r.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double> } %ld2
 }
@@ -2354,7 +2354,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld2r(double* %A, doub
 ;CHECK-LABEL: test_v1f64_post_imm_ld2r:
 ;CHECK: ld2r.1d { v0, v1 }, [x0], #16
   %ld2 = call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2r.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 2
+  %tmp = getelementptr double, double* %A, i32 2
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double> } %ld2
 }
@@ -2363,7 +2363,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld2r(double* %A, doub
 ;CHECK-LABEL: test_v1f64_post_reg_ld2r:
 ;CHECK: ld2r.1d { v0, v1 }, [x0], x{{[0-9]+}}
   %ld2 = call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2r.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double> } %ld2
 }
@@ -2375,7 +2375,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld3r(i8* %A, i8*
 ;CHECK-LABEL: test_v16i8_post_imm_ld3r:
 ;CHECK: ld3r.16b { v0, v1, v2 }, [x0], #3
   %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 3
+  %tmp = getelementptr i8, i8* %A, i32 3
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3
 }
@@ -2384,7 +2384,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld3r(i8* %A, i8*
 ;CHECK-LABEL: test_v16i8_post_reg_ld3r:
 ;CHECK: ld3r.16b { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3
 }
@@ -2396,7 +2396,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld3r(i8* %A, i8** %p
 ;CHECK-LABEL: test_v8i8_post_imm_ld3r:
 ;CHECK: ld3r.8b { v0, v1, v2 }, [x0], #3
   %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 3
+  %tmp = getelementptr i8, i8* %A, i32 3
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3
 }
@@ -2405,7 +2405,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld3r(i8* %A, i8** %p
 ;CHECK-LABEL: test_v8i8_post_reg_ld3r:
 ;CHECK: ld3r.8b { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3
 }
@@ -2417,7 +2417,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld3r(i16* %A, i1
 ;CHECK-LABEL: test_v8i16_post_imm_ld3r:
 ;CHECK: ld3r.8h { v0, v1, v2 }, [x0], #6
   %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3r.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 3
+  %tmp = getelementptr i16, i16* %A, i32 3
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3
 }
@@ -2426,7 +2426,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld3r(i16* %A, i1
 ;CHECK-LABEL: test_v8i16_post_reg_ld3r:
 ;CHECK: ld3r.8h { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3r.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3
 }
@@ -2438,7 +2438,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld3r(i16* %A, i1
 ;CHECK-LABEL: test_v4i16_post_imm_ld3r:
 ;CHECK: ld3r.4h { v0, v1, v2 }, [x0], #6
   %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 3
+  %tmp = getelementptr i16, i16* %A, i32 3
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3
 }
@@ -2447,7 +2447,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld3r(i16* %A, i1
 ;CHECK-LABEL: test_v4i16_post_reg_ld3r:
 ;CHECK: ld3r.4h { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3
 }
@@ -2459,7 +2459,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld3r(i32* %A, i3
 ;CHECK-LABEL: test_v4i32_post_imm_ld3r:
 ;CHECK: ld3r.4s { v0, v1, v2 }, [x0], #12
   %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3r.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 3
+  %tmp = getelementptr i32, i32* %A, i32 3
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3
 }
@@ -2468,7 +2468,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld3r(i32* %A, i3
 ;CHECK-LABEL: test_v4i32_post_reg_ld3r:
 ;CHECK: ld3r.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3r.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3
 }
@@ -2479,7 +2479,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld3r(i32* %A, i3
 ;CHECK-LABEL: test_v2i32_post_imm_ld3r:
 ;CHECK: ld3r.2s { v0, v1, v2 }, [x0], #12
   %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3r.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 3
+  %tmp = getelementptr i32, i32* %A, i32 3
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3
 }
@@ -2488,7 +2488,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld3r(i32* %A, i3
 ;CHECK-LABEL: test_v2i32_post_reg_ld3r:
 ;CHECK: ld3r.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3r.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3
 }
@@ -2500,7 +2500,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld3r(i64* %A, i6
 ;CHECK-LABEL: test_v2i64_post_imm_ld3r:
 ;CHECK: ld3r.2d { v0, v1, v2 }, [x0], #24
   %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3r.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 3
+  %tmp = getelementptr i64, i64* %A, i32 3
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3
 }
@@ -2509,7 +2509,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld3r(i64* %A, i6
 ;CHECK-LABEL: test_v2i64_post_reg_ld3r:
 ;CHECK: ld3r.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3r.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3
 }
@@ -2520,7 +2520,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld3r(i64* %A, i6
 ;CHECK-LABEL: test_v1i64_post_imm_ld3r:
 ;CHECK: ld3r.1d { v0, v1, v2 }, [x0], #24
   %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3r.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 3
+  %tmp = getelementptr i64, i64* %A, i32 3
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3
 }
@@ -2529,7 +2529,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld3r(i64* %A, i6
 ;CHECK-LABEL: test_v1i64_post_reg_ld3r:
 ;CHECK: ld3r.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3r.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3
 }
@@ -2541,7 +2541,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld3r(float
 ;CHECK-LABEL: test_v4f32_post_imm_ld3r:
 ;CHECK: ld3r.4s { v0, v1, v2 }, [x0], #12
   %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3r.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 3
+  %tmp = getelementptr float, float* %A, i32 3
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float> } %ld3
 }
@@ -2550,7 +2550,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld3r(float
 ;CHECK-LABEL: test_v4f32_post_reg_ld3r:
 ;CHECK: ld3r.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3r.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float> } %ld3
 }
@@ -2561,7 +2561,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld3r(float
 ;CHECK-LABEL: test_v2f32_post_imm_ld3r:
 ;CHECK: ld3r.2s { v0, v1, v2 }, [x0], #12
   %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3r.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 3
+  %tmp = getelementptr float, float* %A, i32 3
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float> } %ld3
 }
@@ -2570,7 +2570,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld3r(float
 ;CHECK-LABEL: test_v2f32_post_reg_ld3r:
 ;CHECK: ld3r.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3r.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float> } %ld3
 }
@@ -2582,7 +2582,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld3r(do
 ;CHECK-LABEL: test_v2f64_post_imm_ld3r:
 ;CHECK: ld3r.2d { v0, v1, v2 }, [x0], #24
   %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3r.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 3
+  %tmp = getelementptr double, double* %A, i32 3
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double> } %ld3
 }
@@ -2591,7 +2591,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld3r(do
 ;CHECK-LABEL: test_v2f64_post_reg_ld3r:
 ;CHECK: ld3r.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3r.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double> } %ld3
 }
@@ -2602,7 +2602,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld3r(do
 ;CHECK-LABEL: test_v1f64_post_imm_ld3r:
 ;CHECK: ld3r.1d { v0, v1, v2 }, [x0], #24
   %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3r.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 3
+  %tmp = getelementptr double, double* %A, i32 3
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double> } %ld3
 }
@@ -2611,7 +2611,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld3r(do
 ;CHECK-LABEL: test_v1f64_post_reg_ld3r:
 ;CHECK: ld3r.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3r.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double> } %ld3
 }
@@ -2623,7 +2623,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld4r(
 ;CHECK-LABEL: test_v16i8_post_imm_ld4r:
 ;CHECK: ld4r.16b { v0, v1, v2, v3 }, [x0], #4
   %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4r.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 4
+  %tmp = getelementptr i8, i8* %A, i32 4
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4
 }
@@ -2632,7 +2632,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld4r(
 ;CHECK-LABEL: test_v16i8_post_reg_ld4r:
 ;CHECK: ld4r.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4r.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4
 }
@@ -2644,7 +2644,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld4r(i8* %
 ;CHECK-LABEL: test_v8i8_post_imm_ld4r:
 ;CHECK: ld4r.8b { v0, v1, v2, v3 }, [x0], #4
   %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4r.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 4
+  %tmp = getelementptr i8, i8* %A, i32 4
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4
 }
@@ -2653,7 +2653,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld4r(i8* %
 ;CHECK-LABEL: test_v8i8_post_reg_ld4r:
 ;CHECK: ld4r.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4r.v8i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4
 }
@@ -2665,7 +2665,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld4r(
 ;CHECK-LABEL: test_v8i16_post_imm_ld4r:
 ;CHECK: ld4r.8h { v0, v1, v2, v3 }, [x0], #8
   %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4r.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 4
+  %tmp = getelementptr i16, i16* %A, i32 4
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4
 }
@@ -2674,7 +2674,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld4r(
 ;CHECK-LABEL: test_v8i16_post_reg_ld4r:
 ;CHECK: ld4r.8h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4r.v8i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4
 }
@@ -2686,7 +2686,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld4r(
 ;CHECK-LABEL: test_v4i16_post_imm_ld4r:
 ;CHECK: ld4r.4h { v0, v1, v2, v3 }, [x0], #8
   %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4r.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i32 4
+  %tmp = getelementptr i16, i16* %A, i32 4
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4
 }
@@ -2695,7 +2695,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld4r(
 ;CHECK-LABEL: test_v4i16_post_reg_ld4r:
 ;CHECK: ld4r.4h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4r.v4i16.p0i16(i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4
 }
@@ -2707,7 +2707,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld4r(
 ;CHECK-LABEL: test_v4i32_post_imm_ld4r:
 ;CHECK: ld4r.4s { v0, v1, v2, v3 }, [x0], #16
   %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4r.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 4
+  %tmp = getelementptr i32, i32* %A, i32 4
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4
 }
@@ -2716,7 +2716,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld4r(
 ;CHECK-LABEL: test_v4i32_post_reg_ld4r:
 ;CHECK: ld4r.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4r.v4i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4
 }
@@ -2727,7 +2727,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld4r(
 ;CHECK-LABEL: test_v2i32_post_imm_ld4r:
 ;CHECK: ld4r.2s { v0, v1, v2, v3 }, [x0], #16
   %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4r.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i32 4
+  %tmp = getelementptr i32, i32* %A, i32 4
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4
 }
@@ -2736,7 +2736,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld4r(
 ;CHECK-LABEL: test_v2i32_post_reg_ld4r:
 ;CHECK: ld4r.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4r.v2i32.p0i32(i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4
 }
@@ -2748,7 +2748,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld4r(
 ;CHECK-LABEL: test_v2i64_post_imm_ld4r:
 ;CHECK: ld4r.2d { v0, v1, v2, v3 }, [x0], #32
   %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4r.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 4
+  %tmp = getelementptr i64, i64* %A, i32 4
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4
 }
@@ -2757,7 +2757,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld4r(
 ;CHECK-LABEL: test_v2i64_post_reg_ld4r:
 ;CHECK: ld4r.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4r.v2i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4
 }
@@ -2768,7 +2768,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld4r(
 ;CHECK-LABEL: test_v1i64_post_imm_ld4r:
 ;CHECK: ld4r.1d { v0, v1, v2, v3 }, [x0], #32
   %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4r.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i32 4
+  %tmp = getelementptr i64, i64* %A, i32 4
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4
 }
@@ -2777,7 +2777,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld4r(
 ;CHECK-LABEL: test_v1i64_post_reg_ld4r:
 ;CHECK: ld4r.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4r.v1i64.p0i64(i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4
 }
@@ -2789,7 +2789,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_i
 ;CHECK-LABEL: test_v4f32_post_imm_ld4r:
 ;CHECK: ld4r.4s { v0, v1, v2, v3 }, [x0], #16
   %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4r.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 4
+  %tmp = getelementptr float, float* %A, i32 4
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4
 }
@@ -2798,7 +2798,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_r
 ;CHECK-LABEL: test_v4f32_post_reg_ld4r:
 ;CHECK: ld4r.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4r.v4f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4
 }
@@ -2809,7 +2809,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_i
 ;CHECK-LABEL: test_v2f32_post_imm_ld4r:
 ;CHECK: ld4r.2s { v0, v1, v2, v3 }, [x0], #16
   %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4r.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i32 4
+  %tmp = getelementptr float, float* %A, i32 4
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4
 }
@@ -2818,7 +2818,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_r
 ;CHECK-LABEL: test_v2f32_post_reg_ld4r:
 ;CHECK: ld4r.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4r.v2f32.p0f32(float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4
 }
@@ -2830,7 +2830,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po
 ;CHECK-LABEL: test_v2f64_post_imm_ld4r:
 ;CHECK: ld4r.2d { v0, v1, v2, v3 }, [x0], #32
   %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4r.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 4
+  %tmp = getelementptr double, double* %A, i32 4
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4
 }
@@ -2839,7 +2839,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po
 ;CHECK-LABEL: test_v2f64_post_reg_ld4r:
 ;CHECK: ld4r.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4r.v2f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4
 }
@@ -2850,7 +2850,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po
 ;CHECK-LABEL: test_v1f64_post_imm_ld4r:
 ;CHECK: ld4r.1d { v0, v1, v2, v3 }, [x0], #32
   %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4r.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i32 4
+  %tmp = getelementptr double, double* %A, i32 4
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4
 }
@@ -2859,7 +2859,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po
 ;CHECK-LABEL: test_v1f64_post_reg_ld4r:
 ;CHECK: ld4r.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4r.v1f64.p0f64(double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4
 }
@@ -2871,7 +2871,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2lane(i8* %A, i8** %ptr,
 ;CHECK-LABEL: test_v16i8_post_imm_ld2lane:
 ;CHECK: ld2.b { v0, v1 }[0], [x0], #2
   %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i32 2
+  %tmp = getelementptr i8, i8* %A, i32 2
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8> } %ld2
 }
@@ -2880,7 +2880,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld2lane(i8* %A, i8** %ptr,
 ;CHECK-LABEL: test_v16i8_post_reg_ld2lane:
 ;CHECK: ld2.b { v0, v1 }[0], [x0], x{{[0-9]+}}
   %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8> } %ld2
 }
@@ -2892,7 +2892,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld2lane(i8* %A, i8** %ptr, <8
 ;CHECK-LABEL: test_v8i8_post_imm_ld2lane:
 ;CHECK: ld2.b { v0, v1 }[0], [x0], #2
   %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i32 2
+  %tmp = getelementptr i8, i8* %A, i32 2
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8> } %ld2
 }
@@ -2901,7 +2901,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld2lane(i8* %A, i8** %ptr, i64
 ;CHECK-LABEL: test_v8i8_post_reg_ld2lane:
 ;CHECK: ld2.b { v0, v1 }[0], [x0], x{{[0-9]+}}
   %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8> } %ld2
 }
@@ -2913,7 +2913,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld2lane(i16* %A, i16** %ptr
 ;CHECK-LABEL: test_v8i16_post_imm_ld2lane:
 ;CHECK: ld2.h { v0, v1 }[0], [x0], #4
   %ld2 = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i32 2
+  %tmp = getelementptr i16, i16* %A, i32 2
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16> } %ld2
 }
@@ -2922,7 +2922,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld2lane(i16* %A, i16** %ptr
 ;CHECK-LABEL: test_v8i16_post_reg_ld2lane:
 ;CHECK: ld2.h { v0, v1 }[0], [x0], x{{[0-9]+}}
   %ld2 = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16> } %ld2
 }
@@ -2934,7 +2934,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld2lane(i16* %A, i16** %ptr
 ;CHECK-LABEL: test_v4i16_post_imm_ld2lane:
 ;CHECK: ld2.h { v0, v1 }[0], [x0], #4
   %ld2 = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i32 2
+  %tmp = getelementptr i16, i16* %A, i32 2
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16> } %ld2
 }
@@ -2943,7 +2943,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld2lane(i16* %A, i16** %ptr
 ;CHECK-LABEL: test_v4i16_post_reg_ld2lane:
 ;CHECK: ld2.h { v0, v1 }[0], [x0], x{{[0-9]+}}
   %ld2 = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16> } %ld2
 }
@@ -2955,7 +2955,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld2lane(i32* %A, i32** %ptr
 ;CHECK-LABEL: test_v4i32_post_imm_ld2lane:
 ;CHECK: ld2.s { v0, v1 }[0], [x0], #8
   %ld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i32 2
+  %tmp = getelementptr i32, i32* %A, i32 2
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32> } %ld2
 }
@@ -2964,7 +2964,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld2lane(i32* %A, i32** %ptr
 ;CHECK-LABEL: test_v4i32_post_reg_ld2lane:
 ;CHECK: ld2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
   %ld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32> } %ld2
 }
@@ -2976,7 +2976,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld2lane(i32* %A, i32** %ptr
 ;CHECK-LABEL: test_v2i32_post_imm_ld2lane:
 ;CHECK: ld2.s { v0, v1 }[0], [x0], #8
   %ld2 = call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i32 2
+  %tmp = getelementptr i32, i32* %A, i32 2
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32> } %ld2
 }
@@ -2985,7 +2985,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld2lane(i32* %A, i32** %ptr
 ;CHECK-LABEL: test_v2i32_post_reg_ld2lane:
 ;CHECK: ld2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
   %ld2 = call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32> } %ld2
 }
@@ -2997,7 +2997,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld2lane(i64* %A, i64** %ptr
 ;CHECK-LABEL: test_v2i64_post_imm_ld2lane:
 ;CHECK: ld2.d { v0, v1 }[0], [x0], #16
   %ld2 = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i32 2
+  %tmp = getelementptr i64, i64* %A, i32 2
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64> } %ld2
 }
@@ -3006,7 +3006,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld2lane(i64* %A, i64** %ptr
 ;CHECK-LABEL: test_v2i64_post_reg_ld2lane:
 ;CHECK: ld2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
   %ld2 = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64> } %ld2
 }
@@ -3018,7 +3018,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld2lane(i64* %A, i64** %ptr
 ;CHECK-LABEL: test_v1i64_post_imm_ld2lane:
 ;CHECK: ld2.d { v0, v1 }[0], [x0], #16
   %ld2 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i32 2
+  %tmp = getelementptr i64, i64* %A, i32 2
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64> } %ld2
 }
@@ -3027,7 +3027,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld2lane(i64* %A, i64** %ptr
 ;CHECK-LABEL: test_v1i64_post_reg_ld2lane:
 ;CHECK: ld2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
   %ld2 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64> } %ld2
 }
@@ -3039,7 +3039,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld2lane(float* %A, floa
 ;CHECK-LABEL: test_v4f32_post_imm_ld2lane:
 ;CHECK: ld2.s { v0, v1 }[0], [x0], #8
   %ld2 = call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i32 2
+  %tmp = getelementptr float, float* %A, i32 2
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float> } %ld2
 }
@@ -3048,7 +3048,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld2lane(float* %A, floa
 ;CHECK-LABEL: test_v4f32_post_reg_ld2lane:
 ;CHECK: ld2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
   %ld2 = call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float> } %ld2
 }
@@ -3060,7 +3060,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld2lane(float* %A, floa
 ;CHECK-LABEL: test_v2f32_post_imm_ld2lane:
 ;CHECK: ld2.s { v0, v1 }[0], [x0], #8
   %ld2 = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i32 2
+  %tmp = getelementptr float, float* %A, i32 2
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float> } %ld2
 }
@@ -3069,7 +3069,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld2lane(float* %A, floa
 ;CHECK-LABEL: test_v2f32_post_reg_ld2lane:
 ;CHECK: ld2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
   %ld2 = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float> } %ld2
 }
@@ -3081,7 +3081,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld2lane(double* %A, d
 ;CHECK-LABEL: test_v2f64_post_imm_ld2lane:
 ;CHECK: ld2.d { v0, v1 }[0], [x0], #16
   %ld2 = call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i32 2
+  %tmp = getelementptr double, double* %A, i32 2
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double> } %ld2
 }
@@ -3090,7 +3090,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld2lane(double* %A, d
 ;CHECK-LABEL: test_v2f64_post_reg_ld2lane:
 ;CHECK: ld2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
   %ld2 = call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double> } %ld2
 }
@@ -3102,7 +3102,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld2lane(double* %A, d
 ;CHECK-LABEL: test_v1f64_post_imm_ld2lane:
 ;CHECK: ld2.d { v0, v1 }[0], [x0], #16
   %ld2 = call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i32 2
+  %tmp = getelementptr double, double* %A, i32 2
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double> } %ld2
 }
@@ -3111,7 +3111,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld2lane(double* %A, d
 ;CHECK-LABEL: test_v1f64_post_reg_ld2lane:
 ;CHECK: ld2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
   %ld2 = call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double> } %ld2
 }
@@ -3123,7 +3123,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld3lane(i8* %A,
 ;CHECK-LABEL: test_v16i8_post_imm_ld3lane:
 ;CHECK: ld3.b { v0, v1, v2 }[0], [x0], #3
   %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i32 3
+  %tmp = getelementptr i8, i8* %A, i32 3
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3
 }
@@ -3132,7 +3132,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld3lane(i8* %A,
 ;CHECK-LABEL: test_v16i8_post_reg_ld3lane:
 ;CHECK: ld3.b { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3
 }
@@ -3144,7 +3144,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld3lane(i8* %A, i8**
 ;CHECK-LABEL: test_v8i8_post_imm_ld3lane:
 ;CHECK: ld3.b { v0, v1, v2 }[0], [x0], #3
   %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i32 3
+  %tmp = getelementptr i8, i8* %A, i32 3
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3
 }
@@ -3153,7 +3153,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld3lane(i8* %A, i8**
 ;CHECK-LABEL: test_v8i8_post_reg_ld3lane:
 ;CHECK: ld3.b { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3
 }
@@ -3165,7 +3165,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld3lane(i16* %A,
 ;CHECK-LABEL: test_v8i16_post_imm_ld3lane:
 ;CHECK: ld3.h { v0, v1, v2 }[0], [x0], #6
   %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i32 3
+  %tmp = getelementptr i16, i16* %A, i32 3
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3
 }
@@ -3174,7 +3174,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld3lane(i16* %A,
 ;CHECK-LABEL: test_v8i16_post_reg_ld3lane:
 ;CHECK: ld3.h { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3
 }
@@ -3186,7 +3186,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld3lane(i16* %A,
 ;CHECK-LABEL: test_v4i16_post_imm_ld3lane:
 ;CHECK: ld3.h { v0, v1, v2 }[0], [x0], #6
   %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i32 3
+  %tmp = getelementptr i16, i16* %A, i32 3
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3
 }
@@ -3195,7 +3195,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld3lane(i16* %A,
 ;CHECK-LABEL: test_v4i16_post_reg_ld3lane:
 ;CHECK: ld3.h { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3
 }
@@ -3207,7 +3207,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld3lane(i32* %A,
 ;CHECK-LABEL: test_v4i32_post_imm_ld3lane:
 ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], #12
   %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i32 3
+  %tmp = getelementptr i32, i32* %A, i32 3
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3
 }
@@ -3216,7 +3216,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld3lane(i32* %A,
 ;CHECK-LABEL: test_v4i32_post_reg_ld3lane:
 ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3
 }
@@ -3228,7 +3228,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld3lane(i32* %A,
 ;CHECK-LABEL: test_v2i32_post_imm_ld3lane:
 ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], #12
   %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i32 3
+  %tmp = getelementptr i32, i32* %A, i32 3
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3
 }
@@ -3237,7 +3237,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld3lane(i32* %A,
 ;CHECK-LABEL: test_v2i32_post_reg_ld3lane:
 ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3
 }
@@ -3249,7 +3249,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld3lane(i64* %A,
 ;CHECK-LABEL: test_v2i64_post_imm_ld3lane:
 ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], #24
   %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i32 3
+  %tmp = getelementptr i64, i64* %A, i32 3
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3
 }
@@ -3258,7 +3258,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld3lane(i64* %A,
 ;CHECK-LABEL: test_v2i64_post_reg_ld3lane:
 ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3
 }
@@ -3270,7 +3270,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld3lane(i64* %A,
 ;CHECK-LABEL: test_v1i64_post_imm_ld3lane:
 ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], #24
   %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i32 3
+  %tmp = getelementptr i64, i64* %A, i32 3
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3
 }
@@ -3279,7 +3279,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld3lane(i64* %A,
 ;CHECK-LABEL: test_v1i64_post_reg_ld3lane:
 ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3
 }
@@ -3291,7 +3291,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld3lane(fl
 ;CHECK-LABEL: test_v4f32_post_imm_ld3lane:
 ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], #12
   %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i32 3
+  %tmp = getelementptr float, float* %A, i32 3
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float> } %ld3
 }
@@ -3300,7 +3300,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld3lane(fl
 ;CHECK-LABEL: test_v4f32_post_reg_ld3lane:
 ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float> } %ld3
 }
@@ -3312,7 +3312,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld3lane(fl
 ;CHECK-LABEL: test_v2f32_post_imm_ld3lane:
 ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], #12
   %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i32 3
+  %tmp = getelementptr float, float* %A, i32 3
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float> } %ld3
 }
@@ -3321,7 +3321,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld3lane(fl
 ;CHECK-LABEL: test_v2f32_post_reg_ld3lane:
 ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float> } %ld3
 }
@@ -3333,7 +3333,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld3lane
 ;CHECK-LABEL: test_v2f64_post_imm_ld3lane:
 ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], #24
   %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i32 3
+  %tmp = getelementptr double, double* %A, i32 3
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double> } %ld3
 }
@@ -3342,7 +3342,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld3lane
 ;CHECK-LABEL: test_v2f64_post_reg_ld3lane:
 ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double> } %ld3
 }
@@ -3354,7 +3354,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld3lane
 ;CHECK-LABEL: test_v1f64_post_imm_ld3lane:
 ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], #24
   %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i32 3
+  %tmp = getelementptr double, double* %A, i32 3
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double> } %ld3
 }
@@ -3363,7 +3363,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld3lane
 ;CHECK-LABEL: test_v1f64_post_reg_ld3lane:
 ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double> } %ld3
 }
@@ -3375,7 +3375,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld4la
 ;CHECK-LABEL: test_v16i8_post_imm_ld4lane:
 ;CHECK: ld4.b { v0, v1, v2, v3 }[0], [x0], #4
   %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i32 4
+  %tmp = getelementptr i8, i8* %A, i32 4
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4
 }
@@ -3384,7 +3384,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld4la
 ;CHECK-LABEL: test_v16i8_post_reg_ld4lane:
 ;CHECK: ld4.b { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4
 }
@@ -3396,7 +3396,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld4lane(i8
 ;CHECK-LABEL: test_v8i8_post_imm_ld4lane:
 ;CHECK: ld4.b { v0, v1, v2, v3 }[0], [x0], #4
   %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i32 4
+  %tmp = getelementptr i8, i8* %A, i32 4
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4
 }
@@ -3405,7 +3405,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld4lane(i8
 ;CHECK-LABEL: test_v8i8_post_reg_ld4lane:
 ;CHECK: ld4.b { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   store i8* %tmp, i8** %ptr
   ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4
 }
@@ -3417,7 +3417,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld4la
 ;CHECK-LABEL: test_v8i16_post_imm_ld4lane:
 ;CHECK: ld4.h { v0, v1, v2, v3 }[0], [x0], #8
   %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i32 4
+  %tmp = getelementptr i16, i16* %A, i32 4
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4
 }
@@ -3426,7 +3426,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld4la
 ;CHECK-LABEL: test_v8i16_post_reg_ld4lane:
 ;CHECK: ld4.h { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4
 }
@@ -3438,7 +3438,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld4la
 ;CHECK-LABEL: test_v4i16_post_imm_ld4lane:
 ;CHECK: ld4.h { v0, v1, v2, v3 }[0], [x0], #8
   %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i32 4
+  %tmp = getelementptr i16, i16* %A, i32 4
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4
 }
@@ -3447,7 +3447,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld4la
 ;CHECK-LABEL: test_v4i16_post_reg_ld4lane:
 ;CHECK: ld4.h { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   store i16* %tmp, i16** %ptr
   ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4
 }
@@ -3459,7 +3459,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld4la
 ;CHECK-LABEL: test_v4i32_post_imm_ld4lane:
 ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], #16
   %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i32 4
+  %tmp = getelementptr i32, i32* %A, i32 4
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4
 }
@@ -3468,7 +3468,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld4la
 ;CHECK-LABEL: test_v4i32_post_reg_ld4lane:
 ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4
 }
@@ -3480,7 +3480,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld4la
 ;CHECK-LABEL: test_v2i32_post_imm_ld4lane:
 ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], #16
   %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i32 4
+  %tmp = getelementptr i32, i32* %A, i32 4
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4
 }
@@ -3489,7 +3489,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld4la
 ;CHECK-LABEL: test_v2i32_post_reg_ld4lane:
 ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   store i32* %tmp, i32** %ptr
   ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4
 }
@@ -3501,7 +3501,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld4la
 ;CHECK-LABEL: test_v2i64_post_imm_ld4lane:
 ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], #32
   %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i32 4
+  %tmp = getelementptr i64, i64* %A, i32 4
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4
 }
@@ -3510,7 +3510,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld4la
 ;CHECK-LABEL: test_v2i64_post_reg_ld4lane:
 ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4
 }
@@ -3522,7 +3522,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld4la
 ;CHECK-LABEL: test_v1i64_post_imm_ld4lane:
 ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], #32
   %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i32 4
+  %tmp = getelementptr i64, i64* %A, i32 4
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4
 }
@@ -3531,7 +3531,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld4la
 ;CHECK-LABEL: test_v1i64_post_reg_ld4lane:
 ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   store i64* %tmp, i64** %ptr
   ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4
 }
@@ -3543,7 +3543,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_i
 ;CHECK-LABEL: test_v4f32_post_imm_ld4lane:
 ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], #16
   %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i32 4
+  %tmp = getelementptr float, float* %A, i32 4
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4
 }
@@ -3552,7 +3552,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_r
 ;CHECK-LABEL: test_v4f32_post_reg_ld4lane:
 ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4
 }
@@ -3564,7 +3564,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_i
 ;CHECK-LABEL: test_v2f32_post_imm_ld4lane:
 ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], #16
   %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i32 4
+  %tmp = getelementptr float, float* %A, i32 4
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4
 }
@@ -3573,7 +3573,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_r
 ;CHECK-LABEL: test_v2f32_post_reg_ld4lane:
 ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   store float* %tmp, float** %ptr
   ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4
 }
@@ -3585,7 +3585,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po
 ;CHECK-LABEL: test_v2f64_post_imm_ld4lane:
 ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], #32
   %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i32 4
+  %tmp = getelementptr double, double* %A, i32 4
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4
 }
@@ -3594,7 +3594,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po
 ;CHECK-LABEL: test_v2f64_post_reg_ld4lane:
 ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4
 }
@@ -3606,7 +3606,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po
 ;CHECK-LABEL: test_v1f64_post_imm_ld4lane:
 ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], #32
   %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i32 4
+  %tmp = getelementptr double, double* %A, i32 4
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4
 }
@@ -3615,7 +3615,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po
 ;CHECK-LABEL: test_v1f64_post_reg_ld4lane:
 ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   store double* %tmp, double** %ptr
   ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4
 }
@@ -3627,7 +3627,7 @@ define i8* @test_v16i8_post_imm_st2(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %
 ;CHECK-LABEL: test_v16i8_post_imm_st2:
 ;CHECK: st2.16b { v0, v1 }, [x0], #32
   call void @llvm.aarch64.neon.st2.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i8* %A)
-  %tmp = getelementptr i8* %A, i32 32
+  %tmp = getelementptr i8, i8* %A, i32 32
   ret i8* %tmp
 }
 
@@ -3635,7 +3635,7 @@ define i8* @test_v16i8_post_reg_st2(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %
 ;CHECK-LABEL: test_v16i8_post_reg_st2:
 ;CHECK: st2.16b { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -3646,7 +3646,7 @@ define i8* @test_v8i8_post_imm_st2(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C)
 ;CHECK-LABEL: test_v8i8_post_imm_st2:
 ;CHECK: st2.8b { v0, v1 }, [x0], #16
   call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i8* %A)
-  %tmp = getelementptr i8* %A, i32 16
+  %tmp = getelementptr i8, i8* %A, i32 16
   ret i8* %tmp
 }
 
@@ -3654,7 +3654,7 @@ define i8* @test_v8i8_post_reg_st2(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C,
 ;CHECK-LABEL: test_v8i8_post_reg_st2:
 ;CHECK: st2.8b { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -3665,7 +3665,7 @@ define i16* @test_v8i16_post_imm_st2(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16
 ;CHECK-LABEL: test_v8i16_post_imm_st2:
 ;CHECK: st2.8h { v0, v1 }, [x0], #32
   call void @llvm.aarch64.neon.st2.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i16* %A)
-  %tmp = getelementptr i16* %A, i32 16
+  %tmp = getelementptr i16, i16* %A, i32 16
   ret i16* %tmp
 }
 
@@ -3673,7 +3673,7 @@ define i16* @test_v8i16_post_reg_st2(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16
 ;CHECK-LABEL: test_v8i16_post_reg_st2:
 ;CHECK: st2.8h { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -3684,7 +3684,7 @@ define i16* @test_v4i16_post_imm_st2(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16
 ;CHECK-LABEL: test_v4i16_post_imm_st2:
 ;CHECK: st2.4h { v0, v1 }, [x0], #16
   call void @llvm.aarch64.neon.st2.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i16* %A)
-  %tmp = getelementptr i16* %A, i32 8
+  %tmp = getelementptr i16, i16* %A, i32 8
   ret i16* %tmp
 }
 
@@ -3692,7 +3692,7 @@ define i16* @test_v4i16_post_reg_st2(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16
 ;CHECK-LABEL: test_v4i16_post_reg_st2:
 ;CHECK: st2.4h { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -3703,7 +3703,7 @@ define i32* @test_v4i32_post_imm_st2(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32
 ;CHECK-LABEL: test_v4i32_post_imm_st2:
 ;CHECK: st2.4s { v0, v1 }, [x0], #32
   call void @llvm.aarch64.neon.st2.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i32* %A)
-  %tmp = getelementptr i32* %A, i32 8
+  %tmp = getelementptr i32, i32* %A, i32 8
   ret i32* %tmp
 }
 
@@ -3711,7 +3711,7 @@ define i32* @test_v4i32_post_reg_st2(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32
 ;CHECK-LABEL: test_v4i32_post_reg_st2:
 ;CHECK: st2.4s { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -3722,7 +3722,7 @@ define i32* @test_v2i32_post_imm_st2(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32
 ;CHECK-LABEL: test_v2i32_post_imm_st2:
 ;CHECK: st2.2s { v0, v1 }, [x0], #16
   call void @llvm.aarch64.neon.st2.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i32* %A)
-  %tmp = getelementptr i32* %A, i32 4
+  %tmp = getelementptr i32, i32* %A, i32 4
   ret i32* %tmp
 }
 
@@ -3730,7 +3730,7 @@ define i32* @test_v2i32_post_reg_st2(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32
 ;CHECK-LABEL: test_v2i32_post_reg_st2:
 ;CHECK: st2.2s { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -3741,7 +3741,7 @@ define i64* @test_v2i64_post_imm_st2(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64
 ;CHECK-LABEL: test_v2i64_post_imm_st2:
 ;CHECK: st2.2d { v0, v1 }, [x0], #32
   call void @llvm.aarch64.neon.st2.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64* %A)
-  %tmp = getelementptr i64* %A, i64 4
+  %tmp = getelementptr i64, i64* %A, i64 4
   ret i64* %tmp
 }
 
@@ -3749,7 +3749,7 @@ define i64* @test_v2i64_post_reg_st2(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64
 ;CHECK-LABEL: test_v2i64_post_reg_st2:
 ;CHECK: st2.2d { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -3760,7 +3760,7 @@ define i64* @test_v1i64_post_imm_st2(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64
 ;CHECK-LABEL: test_v1i64_post_imm_st2:
 ;CHECK: st1.1d { v0, v1 }, [x0], #16
   call void @llvm.aarch64.neon.st2.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64* %A)
-  %tmp = getelementptr i64* %A, i64 2
+  %tmp = getelementptr i64, i64* %A, i64 2
   ret i64* %tmp
 }
 
@@ -3768,7 +3768,7 @@ define i64* @test_v1i64_post_reg_st2(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64
 ;CHECK-LABEL: test_v1i64_post_reg_st2:
 ;CHECK: st1.1d { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -3779,7 +3779,7 @@ define float* @test_v4f32_post_imm_st2(float* %A, float** %ptr, <4 x float> %B,
 ;CHECK-LABEL: test_v4f32_post_imm_st2:
 ;CHECK: st2.4s { v0, v1 }, [x0], #32
   call void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float> %B, <4 x float> %C, float* %A)
-  %tmp = getelementptr float* %A, i32 8
+  %tmp = getelementptr float, float* %A, i32 8
   ret float* %tmp
 }
 
@@ -3787,7 +3787,7 @@ define float* @test_v4f32_post_reg_st2(float* %A, float** %ptr, <4 x float> %B,
 ;CHECK-LABEL: test_v4f32_post_reg_st2:
 ;CHECK: st2.4s { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float> %B, <4 x float> %C, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -3798,7 +3798,7 @@ define float* @test_v2f32_post_imm_st2(float* %A, float** %ptr, <2 x float> %B,
 ;CHECK-LABEL: test_v2f32_post_imm_st2:
 ;CHECK: st2.2s { v0, v1 }, [x0], #16
   call void @llvm.aarch64.neon.st2.v2f32.p0f32(<2 x float> %B, <2 x float> %C, float* %A)
-  %tmp = getelementptr float* %A, i32 4
+  %tmp = getelementptr float, float* %A, i32 4
   ret float* %tmp
 }
 
@@ -3806,7 +3806,7 @@ define float* @test_v2f32_post_reg_st2(float* %A, float** %ptr, <2 x float> %B,
 ;CHECK-LABEL: test_v2f32_post_reg_st2:
 ;CHECK: st2.2s { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2.v2f32.p0f32(<2 x float> %B, <2 x float> %C, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -3817,7 +3817,7 @@ define double* @test_v2f64_post_imm_st2(double* %A, double** %ptr, <2 x double>
 ;CHECK-LABEL: test_v2f64_post_imm_st2:
 ;CHECK: st2.2d { v0, v1 }, [x0], #32
   call void @llvm.aarch64.neon.st2.v2f64.p0f64(<2 x double> %B, <2 x double> %C, double* %A)
-  %tmp = getelementptr double* %A, i64 4
+  %tmp = getelementptr double, double* %A, i64 4
   ret double* %tmp
 }
 
@@ -3825,7 +3825,7 @@ define double* @test_v2f64_post_reg_st2(double* %A, double** %ptr, <2 x double>
 ;CHECK-LABEL: test_v2f64_post_reg_st2:
 ;CHECK: st2.2d { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2.v2f64.p0f64(<2 x double> %B, <2 x double> %C, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -3836,7 +3836,7 @@ define double* @test_v1f64_post_imm_st2(double* %A, double** %ptr, <1 x double>
 ;CHECK-LABEL: test_v1f64_post_imm_st2:
 ;CHECK: st1.1d { v0, v1 }, [x0], #16
   call void @llvm.aarch64.neon.st2.v1f64.p0f64(<1 x double> %B, <1 x double> %C, double* %A)
-  %tmp = getelementptr double* %A, i64 2
+  %tmp = getelementptr double, double* %A, i64 2
   ret double* %tmp
 }
 
@@ -3844,7 +3844,7 @@ define double* @test_v1f64_post_reg_st2(double* %A, double** %ptr, <1 x double>
 ;CHECK-LABEL: test_v1f64_post_reg_st2:
 ;CHECK: st1.1d { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2.v1f64.p0f64(<1 x double> %B, <1 x double> %C, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -3855,7 +3855,7 @@ define i8* @test_v16i8_post_imm_st3(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %
 ;CHECK-LABEL: test_v16i8_post_imm_st3:
 ;CHECK: st3.16b { v0, v1, v2 }, [x0], #48
   call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %A)
-  %tmp = getelementptr i8* %A, i32 48
+  %tmp = getelementptr i8, i8* %A, i32 48
   ret i8* %tmp
 }
 
@@ -3863,7 +3863,7 @@ define i8* @test_v16i8_post_reg_st3(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %
 ;CHECK-LABEL: test_v16i8_post_reg_st3:
 ;CHECK: st3.16b { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -3874,7 +3874,7 @@ define i8* @test_v8i8_post_imm_st3(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C,
 ;CHECK-LABEL: test_v8i8_post_imm_st3:
 ;CHECK: st3.8b { v0, v1, v2 }, [x0], #24
   call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %A)
-  %tmp = getelementptr i8* %A, i32 24
+  %tmp = getelementptr i8, i8* %A, i32 24
   ret i8* %tmp
 }
 
@@ -3882,7 +3882,7 @@ define i8* @test_v8i8_post_reg_st3(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C,
 ;CHECK-LABEL: test_v8i8_post_reg_st3:
 ;CHECK: st3.8b { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -3893,7 +3893,7 @@ define i16* @test_v8i16_post_imm_st3(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16
 ;CHECK-LABEL: test_v8i16_post_imm_st3:
 ;CHECK: st3.8h { v0, v1, v2 }, [x0], #48
   call void @llvm.aarch64.neon.st3.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %A)
-  %tmp = getelementptr i16* %A, i32 24
+  %tmp = getelementptr i16, i16* %A, i32 24
   ret i16* %tmp
 }
 
@@ -3901,7 +3901,7 @@ define i16* @test_v8i16_post_reg_st3(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16
 ;CHECK-LABEL: test_v8i16_post_reg_st3:
 ;CHECK: st3.8h { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -3912,7 +3912,7 @@ define i16* @test_v4i16_post_imm_st3(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16
 ;CHECK-LABEL: test_v4i16_post_imm_st3:
 ;CHECK: st3.4h { v0, v1, v2 }, [x0], #24
   call void @llvm.aarch64.neon.st3.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %A)
-  %tmp = getelementptr i16* %A, i32 12
+  %tmp = getelementptr i16, i16* %A, i32 12
   ret i16* %tmp
 }
 
@@ -3920,7 +3920,7 @@ define i16* @test_v4i16_post_reg_st3(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16
 ;CHECK-LABEL: test_v4i16_post_reg_st3:
 ;CHECK: st3.4h { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -3931,7 +3931,7 @@ define i32* @test_v4i32_post_imm_st3(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32
 ;CHECK-LABEL: test_v4i32_post_imm_st3:
 ;CHECK: st3.4s { v0, v1, v2 }, [x0], #48
   call void @llvm.aarch64.neon.st3.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %A)
-  %tmp = getelementptr i32* %A, i32 12
+  %tmp = getelementptr i32, i32* %A, i32 12
   ret i32* %tmp
 }
 
@@ -3939,7 +3939,7 @@ define i32* @test_v4i32_post_reg_st3(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32
 ;CHECK-LABEL: test_v4i32_post_reg_st3:
 ;CHECK: st3.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -3950,7 +3950,7 @@ define i32* @test_v2i32_post_imm_st3(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32
 ;CHECK-LABEL: test_v2i32_post_imm_st3:
 ;CHECK: st3.2s { v0, v1, v2 }, [x0], #24
   call void @llvm.aarch64.neon.st3.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %A)
-  %tmp = getelementptr i32* %A, i32 6
+  %tmp = getelementptr i32, i32* %A, i32 6
   ret i32* %tmp
 }
 
@@ -3958,7 +3958,7 @@ define i32* @test_v2i32_post_reg_st3(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32
 ;CHECK-LABEL: test_v2i32_post_reg_st3:
 ;CHECK: st3.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -3969,7 +3969,7 @@ define i64* @test_v2i64_post_imm_st3(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64
 ;CHECK-LABEL: test_v2i64_post_imm_st3:
 ;CHECK: st3.2d { v0, v1, v2 }, [x0], #48
   call void @llvm.aarch64.neon.st3.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %A)
-  %tmp = getelementptr i64* %A, i64 6
+  %tmp = getelementptr i64, i64* %A, i64 6
   ret i64* %tmp
 }
 
@@ -3977,7 +3977,7 @@ define i64* @test_v2i64_post_reg_st3(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64
 ;CHECK-LABEL: test_v2i64_post_reg_st3:
 ;CHECK: st3.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -3988,7 +3988,7 @@ define i64* @test_v1i64_post_imm_st3(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64
 ;CHECK-LABEL: test_v1i64_post_imm_st3:
 ;CHECK: st1.1d { v0, v1, v2 }, [x0], #24
   call void @llvm.aarch64.neon.st3.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %A)
-  %tmp = getelementptr i64* %A, i64 3
+  %tmp = getelementptr i64, i64* %A, i64 3
   ret i64* %tmp
 }
 
@@ -3996,7 +3996,7 @@ define i64* @test_v1i64_post_reg_st3(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64
 ;CHECK-LABEL: test_v1i64_post_reg_st3:
 ;CHECK: st1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -4007,7 +4007,7 @@ define float* @test_v4f32_post_imm_st3(float* %A, float** %ptr, <4 x float> %B,
 ;CHECK-LABEL: test_v4f32_post_imm_st3:
 ;CHECK: st3.4s { v0, v1, v2 }, [x0], #48
   call void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, float* %A)
-  %tmp = getelementptr float* %A, i32 12
+  %tmp = getelementptr float, float* %A, i32 12
   ret float* %tmp
 }
 
@@ -4015,7 +4015,7 @@ define float* @test_v4f32_post_reg_st3(float* %A, float** %ptr, <4 x float> %B,
 ;CHECK-LABEL: test_v4f32_post_reg_st3:
 ;CHECK: st3.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -4026,7 +4026,7 @@ define float* @test_v2f32_post_imm_st3(float* %A, float** %ptr, <2 x float> %B,
 ;CHECK-LABEL: test_v2f32_post_imm_st3:
 ;CHECK: st3.2s { v0, v1, v2 }, [x0], #24
   call void @llvm.aarch64.neon.st3.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, float* %A)
-  %tmp = getelementptr float* %A, i32 6
+  %tmp = getelementptr float, float* %A, i32 6
   ret float* %tmp
 }
 
@@ -4034,7 +4034,7 @@ define float* @test_v2f32_post_reg_st3(float* %A, float** %ptr, <2 x float> %B,
 ;CHECK-LABEL: test_v2f32_post_reg_st3:
 ;CHECK: st3.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -4045,7 +4045,7 @@ define double* @test_v2f64_post_imm_st3(double* %A, double** %ptr, <2 x double>
 ;CHECK-LABEL: test_v2f64_post_imm_st3:
 ;CHECK: st3.2d { v0, v1, v2 }, [x0], #48
   call void @llvm.aarch64.neon.st3.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, double* %A)
-  %tmp = getelementptr double* %A, i64 6
+  %tmp = getelementptr double, double* %A, i64 6
   ret double* %tmp
 }
 
@@ -4053,7 +4053,7 @@ define double* @test_v2f64_post_reg_st3(double* %A, double** %ptr, <2 x double>
 ;CHECK-LABEL: test_v2f64_post_reg_st3:
 ;CHECK: st3.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -4064,7 +4064,7 @@ define double* @test_v1f64_post_imm_st3(double* %A, double** %ptr, <1 x double>
 ;CHECK-LABEL: test_v1f64_post_imm_st3:
 ;CHECK: st1.1d { v0, v1, v2 }, [x0], #24
   call void @llvm.aarch64.neon.st3.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, double* %A)
-  %tmp = getelementptr double* %A, i64 3
+  %tmp = getelementptr double, double* %A, i64 3
   ret double* %tmp
 }
 
@@ -4072,7 +4072,7 @@ define double* @test_v1f64_post_reg_st3(double* %A, double** %ptr, <1 x double>
 ;CHECK-LABEL: test_v1f64_post_reg_st3:
 ;CHECK: st1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -4083,7 +4083,7 @@ define i8* @test_v16i8_post_imm_st4(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %
 ;CHECK-LABEL: test_v16i8_post_imm_st4:
 ;CHECK: st4.16b { v0, v1, v2, v3 }, [x0], #64
   call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i8* %A)
-  %tmp = getelementptr i8* %A, i32 64
+  %tmp = getelementptr i8, i8* %A, i32 64
   ret i8* %tmp
 }
 
@@ -4091,7 +4091,7 @@ define i8* @test_v16i8_post_reg_st4(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %
 ;CHECK-LABEL: test_v16i8_post_reg_st4:
 ;CHECK: st4.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -4102,7 +4102,7 @@ define i8* @test_v8i8_post_imm_st4(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C,
 ;CHECK-LABEL: test_v8i8_post_imm_st4:
 ;CHECK: st4.8b { v0, v1, v2, v3 }, [x0], #32
   call void @llvm.aarch64.neon.st4.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i8* %A)
-  %tmp = getelementptr i8* %A, i32 32
+  %tmp = getelementptr i8, i8* %A, i32 32
   ret i8* %tmp
 }
 
@@ -4110,7 +4110,7 @@ define i8* @test_v8i8_post_reg_st4(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C,
 ;CHECK-LABEL: test_v8i8_post_reg_st4:
 ;CHECK: st4.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -4121,7 +4121,7 @@ define i16* @test_v8i16_post_imm_st4(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16
 ;CHECK-LABEL: test_v8i16_post_imm_st4:
 ;CHECK: st4.8h { v0, v1, v2, v3 }, [x0], #64
   call void @llvm.aarch64.neon.st4.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i16* %A)
-  %tmp = getelementptr i16* %A, i32 32
+  %tmp = getelementptr i16, i16* %A, i32 32
   ret i16* %tmp
 }
 
@@ -4129,7 +4129,7 @@ define i16* @test_v8i16_post_reg_st4(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16
 ;CHECK-LABEL: test_v8i16_post_reg_st4:
 ;CHECK: st4.8h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -4140,7 +4140,7 @@ define i16* @test_v4i16_post_imm_st4(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16
 ;CHECK-LABEL: test_v4i16_post_imm_st4:
 ;CHECK: st4.4h { v0, v1, v2, v3 }, [x0], #32
   call void @llvm.aarch64.neon.st4.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i16* %A)
-  %tmp = getelementptr i16* %A, i32 16
+  %tmp = getelementptr i16, i16* %A, i32 16
   ret i16* %tmp
 }
 
@@ -4148,7 +4148,7 @@ define i16* @test_v4i16_post_reg_st4(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16
 ;CHECK-LABEL: test_v4i16_post_reg_st4:
 ;CHECK: st4.4h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -4159,7 +4159,7 @@ define i32* @test_v4i32_post_imm_st4(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32
 ;CHECK-LABEL: test_v4i32_post_imm_st4:
 ;CHECK: st4.4s { v0, v1, v2, v3 }, [x0], #64
   call void @llvm.aarch64.neon.st4.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i32* %A)
-  %tmp = getelementptr i32* %A, i32 16
+  %tmp = getelementptr i32, i32* %A, i32 16
   ret i32* %tmp
 }
 
@@ -4167,7 +4167,7 @@ define i32* @test_v4i32_post_reg_st4(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32
 ;CHECK-LABEL: test_v4i32_post_reg_st4:
 ;CHECK: st4.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -4178,7 +4178,7 @@ define i32* @test_v2i32_post_imm_st4(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32
 ;CHECK-LABEL: test_v2i32_post_imm_st4:
 ;CHECK: st4.2s { v0, v1, v2, v3 }, [x0], #32
   call void @llvm.aarch64.neon.st4.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i32* %A)
-  %tmp = getelementptr i32* %A, i32 8
+  %tmp = getelementptr i32, i32* %A, i32 8
   ret i32* %tmp
 }
 
@@ -4186,7 +4186,7 @@ define i32* @test_v2i32_post_reg_st4(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32
 ;CHECK-LABEL: test_v2i32_post_reg_st4:
 ;CHECK: st4.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -4197,7 +4197,7 @@ define i64* @test_v2i64_post_imm_st4(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64
 ;CHECK-LABEL: test_v2i64_post_imm_st4:
 ;CHECK: st4.2d { v0, v1, v2, v3 }, [x0], #64
   call void @llvm.aarch64.neon.st4.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64* %A)
-  %tmp = getelementptr i64* %A, i64 8
+  %tmp = getelementptr i64, i64* %A, i64 8
   ret i64* %tmp
 }
 
@@ -4205,7 +4205,7 @@ define i64* @test_v2i64_post_reg_st4(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64
 ;CHECK-LABEL: test_v2i64_post_reg_st4:
 ;CHECK: st4.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -4216,7 +4216,7 @@ define i64* @test_v1i64_post_imm_st4(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64
 ;CHECK-LABEL: test_v1i64_post_imm_st4:
 ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], #32
   call void @llvm.aarch64.neon.st4.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64* %A)
-  %tmp = getelementptr i64* %A, i64 4
+  %tmp = getelementptr i64, i64* %A, i64 4
   ret i64* %tmp
 }
 
@@ -4224,7 +4224,7 @@ define i64* @test_v1i64_post_reg_st4(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64
 ;CHECK-LABEL: test_v1i64_post_reg_st4:
 ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -4235,7 +4235,7 @@ define float* @test_v4f32_post_imm_st4(float* %A, float** %ptr, <4 x float> %B,
 ;CHECK-LABEL: test_v4f32_post_imm_st4:
 ;CHECK: st4.4s { v0, v1, v2, v3 }, [x0], #64
   call void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, float* %A)
-  %tmp = getelementptr float* %A, i32 16
+  %tmp = getelementptr float, float* %A, i32 16
   ret float* %tmp
 }
 
@@ -4243,7 +4243,7 @@ define float* @test_v4f32_post_reg_st4(float* %A, float** %ptr, <4 x float> %B,
 ;CHECK-LABEL: test_v4f32_post_reg_st4:
 ;CHECK: st4.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -4254,7 +4254,7 @@ define float* @test_v2f32_post_imm_st4(float* %A, float** %ptr, <2 x float> %B,
 ;CHECK-LABEL: test_v2f32_post_imm_st4:
 ;CHECK: st4.2s { v0, v1, v2, v3 }, [x0], #32
   call void @llvm.aarch64.neon.st4.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, float* %A)
-  %tmp = getelementptr float* %A, i32 8
+  %tmp = getelementptr float, float* %A, i32 8
   ret float* %tmp
 }
 
@@ -4262,7 +4262,7 @@ define float* @test_v2f32_post_reg_st4(float* %A, float** %ptr, <2 x float> %B,
 ;CHECK-LABEL: test_v2f32_post_reg_st4:
 ;CHECK: st4.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -4273,7 +4273,7 @@ define double* @test_v2f64_post_imm_st4(double* %A, double** %ptr, <2 x double>
 ;CHECK-LABEL: test_v2f64_post_imm_st4:
 ;CHECK: st4.2d { v0, v1, v2, v3 }, [x0], #64
   call void @llvm.aarch64.neon.st4.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, double* %A)
-  %tmp = getelementptr double* %A, i64 8
+  %tmp = getelementptr double, double* %A, i64 8
   ret double* %tmp
 }
 
@@ -4281,7 +4281,7 @@ define double* @test_v2f64_post_reg_st4(double* %A, double** %ptr, <2 x double>
 ;CHECK-LABEL: test_v2f64_post_reg_st4:
 ;CHECK: st4.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -4292,7 +4292,7 @@ define double* @test_v1f64_post_imm_st4(double* %A, double** %ptr, <1 x double>
 ;CHECK-LABEL: test_v1f64_post_imm_st4:
 ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], #32
   call void @llvm.aarch64.neon.st4.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, double* %A)
-  %tmp = getelementptr double* %A, i64 4
+  %tmp = getelementptr double, double* %A, i64 4
   ret double* %tmp
 }
 
@@ -4300,7 +4300,7 @@ define double* @test_v1f64_post_reg_st4(double* %A, double** %ptr, <1 x double>
 ;CHECK-LABEL: test_v1f64_post_reg_st4:
 ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -4311,7 +4311,7 @@ define i8* @test_v16i8_post_imm_st1x2(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8>
 ;CHECK-LABEL: test_v16i8_post_imm_st1x2:
 ;CHECK: st1.16b { v0, v1 }, [x0], #32
   call void @llvm.aarch64.neon.st1x2.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i8* %A)
-  %tmp = getelementptr i8* %A, i32 32
+  %tmp = getelementptr i8, i8* %A, i32 32
   ret i8* %tmp
 }
 
@@ -4319,7 +4319,7 @@ define i8* @test_v16i8_post_reg_st1x2(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8>
 ;CHECK-LABEL: test_v16i8_post_reg_st1x2:
 ;CHECK: st1.16b { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x2.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -4330,7 +4330,7 @@ define i8* @test_v8i8_post_imm_st1x2(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C
 ;CHECK-LABEL: test_v8i8_post_imm_st1x2:
 ;CHECK: st1.8b { v0, v1 }, [x0], #16
   call void @llvm.aarch64.neon.st1x2.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i8* %A)
-  %tmp = getelementptr i8* %A, i32 16
+  %tmp = getelementptr i8, i8* %A, i32 16
   ret i8* %tmp
 }
 
@@ -4338,7 +4338,7 @@ define i8* @test_v8i8_post_reg_st1x2(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C
 ;CHECK-LABEL: test_v8i8_post_reg_st1x2:
 ;CHECK: st1.8b { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x2.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -4349,7 +4349,7 @@ define i16* @test_v8i16_post_imm_st1x2(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i
 ;CHECK-LABEL: test_v8i16_post_imm_st1x2:
 ;CHECK: st1.8h { v0, v1 }, [x0], #32
   call void @llvm.aarch64.neon.st1x2.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i16* %A)
-  %tmp = getelementptr i16* %A, i32 16
+  %tmp = getelementptr i16, i16* %A, i32 16
   ret i16* %tmp
 }
 
@@ -4357,7 +4357,7 @@ define i16* @test_v8i16_post_reg_st1x2(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i
 ;CHECK-LABEL: test_v8i16_post_reg_st1x2:
 ;CHECK: st1.8h { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x2.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -4368,7 +4368,7 @@ define i16* @test_v4i16_post_imm_st1x2(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i
 ;CHECK-LABEL: test_v4i16_post_imm_st1x2:
 ;CHECK: st1.4h { v0, v1 }, [x0], #16
   call void @llvm.aarch64.neon.st1x2.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i16* %A)
-  %tmp = getelementptr i16* %A, i32 8
+  %tmp = getelementptr i16, i16* %A, i32 8
   ret i16* %tmp
 }
 
@@ -4376,7 +4376,7 @@ define i16* @test_v4i16_post_reg_st1x2(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i
 ;CHECK-LABEL: test_v4i16_post_reg_st1x2:
 ;CHECK: st1.4h { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x2.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -4387,7 +4387,7 @@ define i32* @test_v4i32_post_imm_st1x2(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i
 ;CHECK-LABEL: test_v4i32_post_imm_st1x2:
 ;CHECK: st1.4s { v0, v1 }, [x0], #32
   call void @llvm.aarch64.neon.st1x2.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i32* %A)
-  %tmp = getelementptr i32* %A, i32 8
+  %tmp = getelementptr i32, i32* %A, i32 8
   ret i32* %tmp
 }
 
@@ -4395,7 +4395,7 @@ define i32* @test_v4i32_post_reg_st1x2(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i
 ;CHECK-LABEL: test_v4i32_post_reg_st1x2:
 ;CHECK: st1.4s { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x2.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -4406,7 +4406,7 @@ define i32* @test_v2i32_post_imm_st1x2(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i
 ;CHECK-LABEL: test_v2i32_post_imm_st1x2:
 ;CHECK: st1.2s { v0, v1 }, [x0], #16
   call void @llvm.aarch64.neon.st1x2.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i32* %A)
-  %tmp = getelementptr i32* %A, i32 4
+  %tmp = getelementptr i32, i32* %A, i32 4
   ret i32* %tmp
 }
 
@@ -4414,7 +4414,7 @@ define i32* @test_v2i32_post_reg_st1x2(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i
 ;CHECK-LABEL: test_v2i32_post_reg_st1x2:
 ;CHECK: st1.2s { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x2.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -4425,7 +4425,7 @@ define i64* @test_v2i64_post_imm_st1x2(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i
 ;CHECK-LABEL: test_v2i64_post_imm_st1x2:
 ;CHECK: st1.2d { v0, v1 }, [x0], #32
   call void @llvm.aarch64.neon.st1x2.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64* %A)
-  %tmp = getelementptr i64* %A, i64 4
+  %tmp = getelementptr i64, i64* %A, i64 4
   ret i64* %tmp
 }
 
@@ -4433,7 +4433,7 @@ define i64* @test_v2i64_post_reg_st1x2(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i
 ;CHECK-LABEL: test_v2i64_post_reg_st1x2:
 ;CHECK: st1.2d { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x2.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -4444,7 +4444,7 @@ define i64* @test_v1i64_post_imm_st1x2(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i
 ;CHECK-LABEL: test_v1i64_post_imm_st1x2:
 ;CHECK: st1.1d { v0, v1 }, [x0], #16
   call void @llvm.aarch64.neon.st1x2.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64* %A)
-  %tmp = getelementptr i64* %A, i64 2
+  %tmp = getelementptr i64, i64* %A, i64 2
   ret i64* %tmp
 }
 
@@ -4452,7 +4452,7 @@ define i64* @test_v1i64_post_reg_st1x2(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i
 ;CHECK-LABEL: test_v1i64_post_reg_st1x2:
 ;CHECK: st1.1d { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x2.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -4463,7 +4463,7 @@ define float* @test_v4f32_post_imm_st1x2(float* %A, float** %ptr, <4 x float> %B
 ;CHECK-LABEL: test_v4f32_post_imm_st1x2:
 ;CHECK: st1.4s { v0, v1 }, [x0], #32
   call void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float> %B, <4 x float> %C, float* %A)
-  %tmp = getelementptr float* %A, i32 8
+  %tmp = getelementptr float, float* %A, i32 8
   ret float* %tmp
 }
 
@@ -4471,7 +4471,7 @@ define float* @test_v4f32_post_reg_st1x2(float* %A, float** %ptr, <4 x float> %B
 ;CHECK-LABEL: test_v4f32_post_reg_st1x2:
 ;CHECK: st1.4s { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float> %B, <4 x float> %C, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -4482,7 +4482,7 @@ define float* @test_v2f32_post_imm_st1x2(float* %A, float** %ptr, <2 x float> %B
 ;CHECK-LABEL: test_v2f32_post_imm_st1x2:
 ;CHECK: st1.2s { v0, v1 }, [x0], #16
   call void @llvm.aarch64.neon.st1x2.v2f32.p0f32(<2 x float> %B, <2 x float> %C, float* %A)
-  %tmp = getelementptr float* %A, i32 4
+  %tmp = getelementptr float, float* %A, i32 4
   ret float* %tmp
 }
 
@@ -4490,7 +4490,7 @@ define float* @test_v2f32_post_reg_st1x2(float* %A, float** %ptr, <2 x float> %B
 ;CHECK-LABEL: test_v2f32_post_reg_st1x2:
 ;CHECK: st1.2s { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x2.v2f32.p0f32(<2 x float> %B, <2 x float> %C, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -4501,7 +4501,7 @@ define double* @test_v2f64_post_imm_st1x2(double* %A, double** %ptr, <2 x double
 ;CHECK-LABEL: test_v2f64_post_imm_st1x2:
 ;CHECK: st1.2d { v0, v1 }, [x0], #32
   call void @llvm.aarch64.neon.st1x2.v2f64.p0f64(<2 x double> %B, <2 x double> %C, double* %A)
-  %tmp = getelementptr double* %A, i64 4
+  %tmp = getelementptr double, double* %A, i64 4
   ret double* %tmp
 }
 
@@ -4509,7 +4509,7 @@ define double* @test_v2f64_post_reg_st1x2(double* %A, double** %ptr, <2 x double
 ;CHECK-LABEL: test_v2f64_post_reg_st1x2:
 ;CHECK: st1.2d { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x2.v2f64.p0f64(<2 x double> %B, <2 x double> %C, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -4520,7 +4520,7 @@ define double* @test_v1f64_post_imm_st1x2(double* %A, double** %ptr, <1 x double
 ;CHECK-LABEL: test_v1f64_post_imm_st1x2:
 ;CHECK: st1.1d { v0, v1 }, [x0], #16
   call void @llvm.aarch64.neon.st1x2.v1f64.p0f64(<1 x double> %B, <1 x double> %C, double* %A)
-  %tmp = getelementptr double* %A, i64 2
+  %tmp = getelementptr double, double* %A, i64 2
   ret double* %tmp
 }
 
@@ -4528,7 +4528,7 @@ define double* @test_v1f64_post_reg_st1x2(double* %A, double** %ptr, <1 x double
 ;CHECK-LABEL: test_v1f64_post_reg_st1x2:
 ;CHECK: st1.1d { v0, v1 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x2.v1f64.p0f64(<1 x double> %B, <1 x double> %C, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -4539,7 +4539,7 @@ define i8* @test_v16i8_post_imm_st1x3(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8>
 ;CHECK-LABEL: test_v16i8_post_imm_st1x3:
 ;CHECK: st1.16b { v0, v1, v2 }, [x0], #48
   call void @llvm.aarch64.neon.st1x3.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %A)
-  %tmp = getelementptr i8* %A, i32 48
+  %tmp = getelementptr i8, i8* %A, i32 48
   ret i8* %tmp
 }
 
@@ -4547,7 +4547,7 @@ define i8* @test_v16i8_post_reg_st1x3(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8>
 ;CHECK-LABEL: test_v16i8_post_reg_st1x3:
 ;CHECK: st1.16b { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x3.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -4558,7 +4558,7 @@ define i8* @test_v8i8_post_imm_st1x3(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C
 ;CHECK-LABEL: test_v8i8_post_imm_st1x3:
 ;CHECK: st1.8b { v0, v1, v2 }, [x0], #24
   call void @llvm.aarch64.neon.st1x3.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %A)
-  %tmp = getelementptr i8* %A, i32 24
+  %tmp = getelementptr i8, i8* %A, i32 24
   ret i8* %tmp
 }
 
@@ -4566,7 +4566,7 @@ define i8* @test_v8i8_post_reg_st1x3(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C
 ;CHECK-LABEL: test_v8i8_post_reg_st1x3:
 ;CHECK: st1.8b { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x3.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -4577,7 +4577,7 @@ define i16* @test_v8i16_post_imm_st1x3(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i
 ;CHECK-LABEL: test_v8i16_post_imm_st1x3:
 ;CHECK: st1.8h { v0, v1, v2 }, [x0], #48
   call void @llvm.aarch64.neon.st1x3.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %A)
-  %tmp = getelementptr i16* %A, i32 24
+  %tmp = getelementptr i16, i16* %A, i32 24
   ret i16* %tmp
 }
 
@@ -4585,7 +4585,7 @@ define i16* @test_v8i16_post_reg_st1x3(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i
 ;CHECK-LABEL: test_v8i16_post_reg_st1x3:
 ;CHECK: st1.8h { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x3.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -4596,7 +4596,7 @@ define i16* @test_v4i16_post_imm_st1x3(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i
 ;CHECK-LABEL: test_v4i16_post_imm_st1x3:
 ;CHECK: st1.4h { v0, v1, v2 }, [x0], #24
   call void @llvm.aarch64.neon.st1x3.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %A)
-  %tmp = getelementptr i16* %A, i32 12
+  %tmp = getelementptr i16, i16* %A, i32 12
   ret i16* %tmp
 }
 
@@ -4604,7 +4604,7 @@ define i16* @test_v4i16_post_reg_st1x3(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i
 ;CHECK-LABEL: test_v4i16_post_reg_st1x3:
 ;CHECK: st1.4h { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x3.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -4615,7 +4615,7 @@ define i32* @test_v4i32_post_imm_st1x3(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i
 ;CHECK-LABEL: test_v4i32_post_imm_st1x3:
 ;CHECK: st1.4s { v0, v1, v2 }, [x0], #48
   call void @llvm.aarch64.neon.st1x3.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %A)
-  %tmp = getelementptr i32* %A, i32 12
+  %tmp = getelementptr i32, i32* %A, i32 12
   ret i32* %tmp
 }
 
@@ -4623,7 +4623,7 @@ define i32* @test_v4i32_post_reg_st1x3(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i
 ;CHECK-LABEL: test_v4i32_post_reg_st1x3:
 ;CHECK: st1.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x3.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -4634,7 +4634,7 @@ define i32* @test_v2i32_post_imm_st1x3(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i
 ;CHECK-LABEL: test_v2i32_post_imm_st1x3:
 ;CHECK: st1.2s { v0, v1, v2 }, [x0], #24
   call void @llvm.aarch64.neon.st1x3.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %A)
-  %tmp = getelementptr i32* %A, i32 6
+  %tmp = getelementptr i32, i32* %A, i32 6
   ret i32* %tmp
 }
 
@@ -4642,7 +4642,7 @@ define i32* @test_v2i32_post_reg_st1x3(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i
 ;CHECK-LABEL: test_v2i32_post_reg_st1x3:
 ;CHECK: st1.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x3.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -4653,7 +4653,7 @@ define i64* @test_v2i64_post_imm_st1x3(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i
 ;CHECK-LABEL: test_v2i64_post_imm_st1x3:
 ;CHECK: st1.2d { v0, v1, v2 }, [x0], #48
   call void @llvm.aarch64.neon.st1x3.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %A)
-  %tmp = getelementptr i64* %A, i64 6
+  %tmp = getelementptr i64, i64* %A, i64 6
   ret i64* %tmp
 }
 
@@ -4661,7 +4661,7 @@ define i64* @test_v2i64_post_reg_st1x3(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i
 ;CHECK-LABEL: test_v2i64_post_reg_st1x3:
 ;CHECK: st1.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x3.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -4672,7 +4672,7 @@ define i64* @test_v1i64_post_imm_st1x3(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i
 ;CHECK-LABEL: test_v1i64_post_imm_st1x3:
 ;CHECK: st1.1d { v0, v1, v2 }, [x0], #24
   call void @llvm.aarch64.neon.st1x3.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %A)
-  %tmp = getelementptr i64* %A, i64 3
+  %tmp = getelementptr i64, i64* %A, i64 3
   ret i64* %tmp
 }
 
@@ -4680,7 +4680,7 @@ define i64* @test_v1i64_post_reg_st1x3(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i
 ;CHECK-LABEL: test_v1i64_post_reg_st1x3:
 ;CHECK: st1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x3.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -4691,7 +4691,7 @@ define float* @test_v4f32_post_imm_st1x3(float* %A, float** %ptr, <4 x float> %B
 ;CHECK-LABEL: test_v4f32_post_imm_st1x3:
 ;CHECK: st1.4s { v0, v1, v2 }, [x0], #48
   call void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, float* %A)
-  %tmp = getelementptr float* %A, i32 12
+  %tmp = getelementptr float, float* %A, i32 12
   ret float* %tmp
 }
 
@@ -4699,7 +4699,7 @@ define float* @test_v4f32_post_reg_st1x3(float* %A, float** %ptr, <4 x float> %B
 ;CHECK-LABEL: test_v4f32_post_reg_st1x3:
 ;CHECK: st1.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -4710,7 +4710,7 @@ define float* @test_v2f32_post_imm_st1x3(float* %A, float** %ptr, <2 x float> %B
 ;CHECK-LABEL: test_v2f32_post_imm_st1x3:
 ;CHECK: st1.2s { v0, v1, v2 }, [x0], #24
   call void @llvm.aarch64.neon.st1x3.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, float* %A)
-  %tmp = getelementptr float* %A, i32 6
+  %tmp = getelementptr float, float* %A, i32 6
   ret float* %tmp
 }
 
@@ -4718,7 +4718,7 @@ define float* @test_v2f32_post_reg_st1x3(float* %A, float** %ptr, <2 x float> %B
 ;CHECK-LABEL: test_v2f32_post_reg_st1x3:
 ;CHECK: st1.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x3.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -4729,7 +4729,7 @@ define double* @test_v2f64_post_imm_st1x3(double* %A, double** %ptr, <2 x double
 ;CHECK-LABEL: test_v2f64_post_imm_st1x3:
 ;CHECK: st1.2d { v0, v1, v2 }, [x0], #48
   call void @llvm.aarch64.neon.st1x3.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, double* %A)
-  %tmp = getelementptr double* %A, i64 6
+  %tmp = getelementptr double, double* %A, i64 6
   ret double* %tmp
 }
 
@@ -4737,7 +4737,7 @@ define double* @test_v2f64_post_reg_st1x3(double* %A, double** %ptr, <2 x double
 ;CHECK-LABEL: test_v2f64_post_reg_st1x3:
 ;CHECK: st1.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x3.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -4748,7 +4748,7 @@ define double* @test_v1f64_post_imm_st1x3(double* %A, double** %ptr, <1 x double
 ;CHECK-LABEL: test_v1f64_post_imm_st1x3:
 ;CHECK: st1.1d { v0, v1, v2 }, [x0], #24
   call void @llvm.aarch64.neon.st1x3.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, double* %A)
-  %tmp = getelementptr double* %A, i64 3
+  %tmp = getelementptr double, double* %A, i64 3
   ret double* %tmp
 }
 
@@ -4756,7 +4756,7 @@ define double* @test_v1f64_post_reg_st1x3(double* %A, double** %ptr, <1 x double
 ;CHECK-LABEL: test_v1f64_post_reg_st1x3:
 ;CHECK: st1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x3.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -4767,7 +4767,7 @@ define i8* @test_v16i8_post_imm_st1x4(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8>
 ;CHECK-LABEL: test_v16i8_post_imm_st1x4:
 ;CHECK: st1.16b { v0, v1, v2, v3 }, [x0], #64
   call void @llvm.aarch64.neon.st1x4.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i8* %A)
-  %tmp = getelementptr i8* %A, i32 64
+  %tmp = getelementptr i8, i8* %A, i32 64
   ret i8* %tmp
 }
 
@@ -4775,7 +4775,7 @@ define i8* @test_v16i8_post_reg_st1x4(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8>
 ;CHECK-LABEL: test_v16i8_post_reg_st1x4:
 ;CHECK: st1.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x4.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -4786,7 +4786,7 @@ define i8* @test_v8i8_post_imm_st1x4(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C
 ;CHECK-LABEL: test_v8i8_post_imm_st1x4:
 ;CHECK: st1.8b { v0, v1, v2, v3 }, [x0], #32
   call void @llvm.aarch64.neon.st1x4.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i8* %A)
-  %tmp = getelementptr i8* %A, i32 32
+  %tmp = getelementptr i8, i8* %A, i32 32
   ret i8* %tmp
 }
 
@@ -4794,7 +4794,7 @@ define i8* @test_v8i8_post_reg_st1x4(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C
 ;CHECK-LABEL: test_v8i8_post_reg_st1x4:
 ;CHECK: st1.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x4.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -4805,7 +4805,7 @@ define i16* @test_v8i16_post_imm_st1x4(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i
 ;CHECK-LABEL: test_v8i16_post_imm_st1x4:
 ;CHECK: st1.8h { v0, v1, v2, v3 }, [x0], #64
   call void @llvm.aarch64.neon.st1x4.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i16* %A)
-  %tmp = getelementptr i16* %A, i32 32
+  %tmp = getelementptr i16, i16* %A, i32 32
   ret i16* %tmp
 }
 
@@ -4813,7 +4813,7 @@ define i16* @test_v8i16_post_reg_st1x4(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i
 ;CHECK-LABEL: test_v8i16_post_reg_st1x4:
 ;CHECK: st1.8h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x4.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -4824,7 +4824,7 @@ define i16* @test_v4i16_post_imm_st1x4(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i
 ;CHECK-LABEL: test_v4i16_post_imm_st1x4:
 ;CHECK: st1.4h { v0, v1, v2, v3 }, [x0], #32
   call void @llvm.aarch64.neon.st1x4.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i16* %A)
-  %tmp = getelementptr i16* %A, i32 16
+  %tmp = getelementptr i16, i16* %A, i32 16
   ret i16* %tmp
 }
 
@@ -4832,7 +4832,7 @@ define i16* @test_v4i16_post_reg_st1x4(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i
 ;CHECK-LABEL: test_v4i16_post_reg_st1x4:
 ;CHECK: st1.4h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x4.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -4843,7 +4843,7 @@ define i32* @test_v4i32_post_imm_st1x4(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i
 ;CHECK-LABEL: test_v4i32_post_imm_st1x4:
 ;CHECK: st1.4s { v0, v1, v2, v3 }, [x0], #64
   call void @llvm.aarch64.neon.st1x4.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i32* %A)
-  %tmp = getelementptr i32* %A, i32 16
+  %tmp = getelementptr i32, i32* %A, i32 16
   ret i32* %tmp
 }
 
@@ -4851,7 +4851,7 @@ define i32* @test_v4i32_post_reg_st1x4(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i
 ;CHECK-LABEL: test_v4i32_post_reg_st1x4:
 ;CHECK: st1.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x4.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -4862,7 +4862,7 @@ define i32* @test_v2i32_post_imm_st1x4(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i
 ;CHECK-LABEL: test_v2i32_post_imm_st1x4:
 ;CHECK: st1.2s { v0, v1, v2, v3 }, [x0], #32
   call void @llvm.aarch64.neon.st1x4.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i32* %A)
-  %tmp = getelementptr i32* %A, i32 8
+  %tmp = getelementptr i32, i32* %A, i32 8
   ret i32* %tmp
 }
 
@@ -4870,7 +4870,7 @@ define i32* @test_v2i32_post_reg_st1x4(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i
 ;CHECK-LABEL: test_v2i32_post_reg_st1x4:
 ;CHECK: st1.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x4.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -4881,7 +4881,7 @@ define i64* @test_v2i64_post_imm_st1x4(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i
 ;CHECK-LABEL: test_v2i64_post_imm_st1x4:
 ;CHECK: st1.2d { v0, v1, v2, v3 }, [x0], #64
   call void @llvm.aarch64.neon.st1x4.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64* %A)
-  %tmp = getelementptr i64* %A, i64 8
+  %tmp = getelementptr i64, i64* %A, i64 8
   ret i64* %tmp
 }
 
@@ -4889,7 +4889,7 @@ define i64* @test_v2i64_post_reg_st1x4(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i
 ;CHECK-LABEL: test_v2i64_post_reg_st1x4:
 ;CHECK: st1.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x4.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -4900,7 +4900,7 @@ define i64* @test_v1i64_post_imm_st1x4(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i
 ;CHECK-LABEL: test_v1i64_post_imm_st1x4:
 ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], #32
   call void @llvm.aarch64.neon.st1x4.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64* %A)
-  %tmp = getelementptr i64* %A, i64 4
+  %tmp = getelementptr i64, i64* %A, i64 4
   ret i64* %tmp
 }
 
@@ -4908,7 +4908,7 @@ define i64* @test_v1i64_post_reg_st1x4(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i
 ;CHECK-LABEL: test_v1i64_post_reg_st1x4:
 ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x4.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -4919,7 +4919,7 @@ define float* @test_v4f32_post_imm_st1x4(float* %A, float** %ptr, <4 x float> %B
 ;CHECK-LABEL: test_v4f32_post_imm_st1x4:
 ;CHECK: st1.4s { v0, v1, v2, v3 }, [x0], #64
   call void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, float* %A)
-  %tmp = getelementptr float* %A, i32 16
+  %tmp = getelementptr float, float* %A, i32 16
   ret float* %tmp
 }
 
@@ -4927,7 +4927,7 @@ define float* @test_v4f32_post_reg_st1x4(float* %A, float** %ptr, <4 x float> %B
 ;CHECK-LABEL: test_v4f32_post_reg_st1x4:
 ;CHECK: st1.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -4938,7 +4938,7 @@ define float* @test_v2f32_post_imm_st1x4(float* %A, float** %ptr, <2 x float> %B
 ;CHECK-LABEL: test_v2f32_post_imm_st1x4:
 ;CHECK: st1.2s { v0, v1, v2, v3 }, [x0], #32
   call void @llvm.aarch64.neon.st1x4.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, float* %A)
-  %tmp = getelementptr float* %A, i32 8
+  %tmp = getelementptr float, float* %A, i32 8
   ret float* %tmp
 }
 
@@ -4946,7 +4946,7 @@ define float* @test_v2f32_post_reg_st1x4(float* %A, float** %ptr, <2 x float> %B
 ;CHECK-LABEL: test_v2f32_post_reg_st1x4:
 ;CHECK: st1.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x4.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -4957,7 +4957,7 @@ define double* @test_v2f64_post_imm_st1x4(double* %A, double** %ptr, <2 x double
 ;CHECK-LABEL: test_v2f64_post_imm_st1x4:
 ;CHECK: st1.2d { v0, v1, v2, v3 }, [x0], #64
   call void @llvm.aarch64.neon.st1x4.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, double* %A)
-  %tmp = getelementptr double* %A, i64 8
+  %tmp = getelementptr double, double* %A, i64 8
   ret double* %tmp
 }
 
@@ -4965,7 +4965,7 @@ define double* @test_v2f64_post_reg_st1x4(double* %A, double** %ptr, <2 x double
 ;CHECK-LABEL: test_v2f64_post_reg_st1x4:
 ;CHECK: st1.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x4.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -4976,7 +4976,7 @@ define double* @test_v1f64_post_imm_st1x4(double* %A, double** %ptr, <1 x double
 ;CHECK-LABEL: test_v1f64_post_imm_st1x4:
 ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], #32
   call void @llvm.aarch64.neon.st1x4.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, double* %A)
-  %tmp = getelementptr double* %A, i64 4
+  %tmp = getelementptr double, double* %A, i64 4
   ret double* %tmp
 }
 
@@ -4984,7 +4984,7 @@ define double* @test_v1f64_post_reg_st1x4(double* %A, double** %ptr, <1 x double
 ;CHECK-LABEL: test_v1f64_post_reg_st1x4:
 ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st1x4.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -4993,13 +4993,13 @@ declare void @llvm.aarch64.neon.st1x4.v1f64.p0f64(<1 x double>, <1 x double>, <1
 
 define i8* @test_v16i8_post_imm_st2lanelane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C) {
   call void @llvm.aarch64.neon.st2lanelane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i64 1, i8* %A)
-  %tmp = getelementptr i8* %A, i32 2
+  %tmp = getelementptr i8, i8* %A, i32 2
   ret i8* %tmp
 }
 
 define i8* @test_v16i8_post_reg_st2lanelane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, i64 %inc) {
   call void @llvm.aarch64.neon.st2lanelane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i64 1, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -5010,7 +5010,7 @@ define i8* @test_v16i8_post_imm_st2lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i
 ;CHECK-LABEL: test_v16i8_post_imm_st2lane:
 ;CHECK: st2.b { v0, v1 }[0], [x0], #2
   call void @llvm.aarch64.neon.st2lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i32 2
+  %tmp = getelementptr i8, i8* %A, i32 2
   ret i8* %tmp
 }
 
@@ -5018,7 +5018,7 @@ define i8* @test_v16i8_post_reg_st2lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i
 ;CHECK-LABEL: test_v16i8_post_reg_st2lane:
 ;CHECK: st2.b { v0, v1 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -5029,7 +5029,7 @@ define i8* @test_v8i8_post_imm_st2lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8>
 ;CHECK-LABEL: test_v8i8_post_imm_st2lane:
 ;CHECK: st2.b { v0, v1 }[0], [x0], #2
   call void @llvm.aarch64.neon.st2lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i32 2
+  %tmp = getelementptr i8, i8* %A, i32 2
   ret i8* %tmp
 }
 
@@ -5037,7 +5037,7 @@ define i8* @test_v8i8_post_reg_st2lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8>
 ;CHECK-LABEL: test_v8i8_post_reg_st2lane:
 ;CHECK: st2.b { v0, v1 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -5048,7 +5048,7 @@ define i16* @test_v8i16_post_imm_st2lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x
 ;CHECK-LABEL: test_v8i16_post_imm_st2lane:
 ;CHECK: st2.h { v0, v1 }[0], [x0], #4
   call void @llvm.aarch64.neon.st2lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i32 2
+  %tmp = getelementptr i16, i16* %A, i32 2
   ret i16* %tmp
 }
 
@@ -5056,7 +5056,7 @@ define i16* @test_v8i16_post_reg_st2lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x
 ;CHECK-LABEL: test_v8i16_post_reg_st2lane:
 ;CHECK: st2.h { v0, v1 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -5067,7 +5067,7 @@ define i16* @test_v4i16_post_imm_st2lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x
 ;CHECK-LABEL: test_v4i16_post_imm_st2lane:
 ;CHECK: st2.h { v0, v1 }[0], [x0], #4
   call void @llvm.aarch64.neon.st2lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i32 2
+  %tmp = getelementptr i16, i16* %A, i32 2
   ret i16* %tmp
 }
 
@@ -5075,7 +5075,7 @@ define i16* @test_v4i16_post_reg_st2lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x
 ;CHECK-LABEL: test_v4i16_post_reg_st2lane:
 ;CHECK: st2.h { v0, v1 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -5086,7 +5086,7 @@ define i32* @test_v4i32_post_imm_st2lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x
 ;CHECK-LABEL: test_v4i32_post_imm_st2lane:
 ;CHECK: st2.s { v0, v1 }[0], [x0], #8
   call void @llvm.aarch64.neon.st2lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i32 2
+  %tmp = getelementptr i32, i32* %A, i32 2
   ret i32* %tmp
 }
 
@@ -5094,7 +5094,7 @@ define i32* @test_v4i32_post_reg_st2lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x
 ;CHECK-LABEL: test_v4i32_post_reg_st2lane:
 ;CHECK: st2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -5105,7 +5105,7 @@ define i32* @test_v2i32_post_imm_st2lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x
 ;CHECK-LABEL: test_v2i32_post_imm_st2lane:
 ;CHECK: st2.s { v0, v1 }[0], [x0], #8
   call void @llvm.aarch64.neon.st2lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i32 2
+  %tmp = getelementptr i32, i32* %A, i32 2
   ret i32* %tmp
 }
 
@@ -5113,7 +5113,7 @@ define i32* @test_v2i32_post_reg_st2lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x
 ;CHECK-LABEL: test_v2i32_post_reg_st2lane:
 ;CHECK: st2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -5124,7 +5124,7 @@ define i64* @test_v2i64_post_imm_st2lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x
 ;CHECK-LABEL: test_v2i64_post_imm_st2lane:
 ;CHECK: st2.d { v0, v1 }[0], [x0], #16
   call void @llvm.aarch64.neon.st2lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 2
+  %tmp = getelementptr i64, i64* %A, i64 2
   ret i64* %tmp
 }
 
@@ -5132,7 +5132,7 @@ define i64* @test_v2i64_post_reg_st2lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x
 ;CHECK-LABEL: test_v2i64_post_reg_st2lane:
 ;CHECK: st2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -5143,7 +5143,7 @@ define i64* @test_v1i64_post_imm_st2lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x
 ;CHECK-LABEL: test_v1i64_post_imm_st2lane:
 ;CHECK: st2.d { v0, v1 }[0], [x0], #16
   call void @llvm.aarch64.neon.st2lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 2
+  %tmp = getelementptr i64, i64* %A, i64 2
   ret i64* %tmp
 }
 
@@ -5151,7 +5151,7 @@ define i64* @test_v1i64_post_reg_st2lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x
 ;CHECK-LABEL: test_v1i64_post_reg_st2lane:
 ;CHECK: st2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -5162,7 +5162,7 @@ define float* @test_v4f32_post_imm_st2lane(float* %A, float** %ptr, <4 x float>
 ;CHECK-LABEL: test_v4f32_post_imm_st2lane:
 ;CHECK: st2.s { v0, v1 }[0], [x0], #8
   call void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i32 2
+  %tmp = getelementptr float, float* %A, i32 2
   ret float* %tmp
 }
 
@@ -5170,7 +5170,7 @@ define float* @test_v4f32_post_reg_st2lane(float* %A, float** %ptr, <4 x float>
 ;CHECK-LABEL: test_v4f32_post_reg_st2lane:
 ;CHECK: st2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -5181,7 +5181,7 @@ define float* @test_v2f32_post_imm_st2lane(float* %A, float** %ptr, <2 x float>
 ;CHECK-LABEL: test_v2f32_post_imm_st2lane:
 ;CHECK: st2.s { v0, v1 }[0], [x0], #8
   call void @llvm.aarch64.neon.st2lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i32 2
+  %tmp = getelementptr float, float* %A, i32 2
   ret float* %tmp
 }
 
@@ -5189,7 +5189,7 @@ define float* @test_v2f32_post_reg_st2lane(float* %A, float** %ptr, <2 x float>
 ;CHECK-LABEL: test_v2f32_post_reg_st2lane:
 ;CHECK: st2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -5200,7 +5200,7 @@ define double* @test_v2f64_post_imm_st2lane(double* %A, double** %ptr, <2 x doub
 ;CHECK-LABEL: test_v2f64_post_imm_st2lane:
 ;CHECK: st2.d { v0, v1 }[0], [x0], #16
   call void @llvm.aarch64.neon.st2lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 2
+  %tmp = getelementptr double, double* %A, i64 2
   ret double* %tmp
 }
 
@@ -5208,7 +5208,7 @@ define double* @test_v2f64_post_reg_st2lane(double* %A, double** %ptr, <2 x doub
 ;CHECK-LABEL: test_v2f64_post_reg_st2lane:
 ;CHECK: st2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -5219,7 +5219,7 @@ define double* @test_v1f64_post_imm_st2lane(double* %A, double** %ptr, <1 x doub
 ;CHECK-LABEL: test_v1f64_post_imm_st2lane:
 ;CHECK: st2.d { v0, v1 }[0], [x0], #16
   call void @llvm.aarch64.neon.st2lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 2
+  %tmp = getelementptr double, double* %A, i64 2
   ret double* %tmp
 }
 
@@ -5227,7 +5227,7 @@ define double* @test_v1f64_post_reg_st2lane(double* %A, double** %ptr, <1 x doub
 ;CHECK-LABEL: test_v1f64_post_reg_st2lane:
 ;CHECK: st2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st2lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -5238,7 +5238,7 @@ define i8* @test_v16i8_post_imm_st3lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i
 ;CHECK-LABEL: test_v16i8_post_imm_st3lane:
 ;CHECK: st3.b { v0, v1, v2 }[0], [x0], #3
   call void @llvm.aarch64.neon.st3lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i32 3
+  %tmp = getelementptr i8, i8* %A, i32 3
   ret i8* %tmp
 }
 
@@ -5246,7 +5246,7 @@ define i8* @test_v16i8_post_reg_st3lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i
 ;CHECK-LABEL: test_v16i8_post_reg_st3lane:
 ;CHECK: st3.b { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -5257,7 +5257,7 @@ define i8* @test_v8i8_post_imm_st3lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8>
 ;CHECK-LABEL: test_v8i8_post_imm_st3lane:
 ;CHECK: st3.b { v0, v1, v2 }[0], [x0], #3
   call void @llvm.aarch64.neon.st3lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i32 3
+  %tmp = getelementptr i8, i8* %A, i32 3
   ret i8* %tmp
 }
 
@@ -5265,7 +5265,7 @@ define i8* @test_v8i8_post_reg_st3lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8>
 ;CHECK-LABEL: test_v8i8_post_reg_st3lane:
 ;CHECK: st3.b { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -5276,7 +5276,7 @@ define i16* @test_v8i16_post_imm_st3lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x
 ;CHECK-LABEL: test_v8i16_post_imm_st3lane:
 ;CHECK: st3.h { v0, v1, v2 }[0], [x0], #6
   call void @llvm.aarch64.neon.st3lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i32 3
+  %tmp = getelementptr i16, i16* %A, i32 3
   ret i16* %tmp
 }
 
@@ -5284,7 +5284,7 @@ define i16* @test_v8i16_post_reg_st3lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x
 ;CHECK-LABEL: test_v8i16_post_reg_st3lane:
 ;CHECK: st3.h { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -5295,7 +5295,7 @@ define i16* @test_v4i16_post_imm_st3lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x
 ;CHECK-LABEL: test_v4i16_post_imm_st3lane:
 ;CHECK: st3.h { v0, v1, v2 }[0], [x0], #6
   call void @llvm.aarch64.neon.st3lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i32 3
+  %tmp = getelementptr i16, i16* %A, i32 3
   ret i16* %tmp
 }
 
@@ -5303,7 +5303,7 @@ define i16* @test_v4i16_post_reg_st3lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x
 ;CHECK-LABEL: test_v4i16_post_reg_st3lane:
 ;CHECK: st3.h { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -5314,7 +5314,7 @@ define i32* @test_v4i32_post_imm_st3lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x
 ;CHECK-LABEL: test_v4i32_post_imm_st3lane:
 ;CHECK: st3.s { v0, v1, v2 }[0], [x0], #12
   call void @llvm.aarch64.neon.st3lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i32 3
+  %tmp = getelementptr i32, i32* %A, i32 3
   ret i32* %tmp
 }
 
@@ -5322,7 +5322,7 @@ define i32* @test_v4i32_post_reg_st3lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x
 ;CHECK-LABEL: test_v4i32_post_reg_st3lane:
 ;CHECK: st3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -5333,7 +5333,7 @@ define i32* @test_v2i32_post_imm_st3lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x
 ;CHECK-LABEL: test_v2i32_post_imm_st3lane:
 ;CHECK: st3.s { v0, v1, v2 }[0], [x0], #12
   call void @llvm.aarch64.neon.st3lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i32 3
+  %tmp = getelementptr i32, i32* %A, i32 3
   ret i32* %tmp
 }
 
@@ -5341,7 +5341,7 @@ define i32* @test_v2i32_post_reg_st3lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x
 ;CHECK-LABEL: test_v2i32_post_reg_st3lane:
 ;CHECK: st3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -5352,7 +5352,7 @@ define i64* @test_v2i64_post_imm_st3lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x
 ;CHECK-LABEL: test_v2i64_post_imm_st3lane:
 ;CHECK: st3.d { v0, v1, v2 }[0], [x0], #24
   call void @llvm.aarch64.neon.st3lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 3
+  %tmp = getelementptr i64, i64* %A, i64 3
   ret i64* %tmp
 }
 
@@ -5360,7 +5360,7 @@ define i64* @test_v2i64_post_reg_st3lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x
 ;CHECK-LABEL: test_v2i64_post_reg_st3lane:
 ;CHECK: st3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -5371,7 +5371,7 @@ define i64* @test_v1i64_post_imm_st3lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x
 ;CHECK-LABEL: test_v1i64_post_imm_st3lane:
 ;CHECK: st3.d { v0, v1, v2 }[0], [x0], #24
   call void @llvm.aarch64.neon.st3lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 3
+  %tmp = getelementptr i64, i64* %A, i64 3
   ret i64* %tmp
 }
 
@@ -5379,7 +5379,7 @@ define i64* @test_v1i64_post_reg_st3lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x
 ;CHECK-LABEL: test_v1i64_post_reg_st3lane:
 ;CHECK: st3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -5390,7 +5390,7 @@ define float* @test_v4f32_post_imm_st3lane(float* %A, float** %ptr, <4 x float>
 ;CHECK-LABEL: test_v4f32_post_imm_st3lane:
 ;CHECK: st3.s { v0, v1, v2 }[0], [x0], #12
   call void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i32 3
+  %tmp = getelementptr float, float* %A, i32 3
   ret float* %tmp
 }
 
@@ -5398,7 +5398,7 @@ define float* @test_v4f32_post_reg_st3lane(float* %A, float** %ptr, <4 x float>
 ;CHECK-LABEL: test_v4f32_post_reg_st3lane:
 ;CHECK: st3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -5409,7 +5409,7 @@ define float* @test_v2f32_post_imm_st3lane(float* %A, float** %ptr, <2 x float>
 ;CHECK-LABEL: test_v2f32_post_imm_st3lane:
 ;CHECK: st3.s { v0, v1, v2 }[0], [x0], #12
   call void @llvm.aarch64.neon.st3lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i32 3
+  %tmp = getelementptr float, float* %A, i32 3
   ret float* %tmp
 }
 
@@ -5417,7 +5417,7 @@ define float* @test_v2f32_post_reg_st3lane(float* %A, float** %ptr, <2 x float>
 ;CHECK-LABEL: test_v2f32_post_reg_st3lane:
 ;CHECK: st3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -5428,7 +5428,7 @@ define double* @test_v2f64_post_imm_st3lane(double* %A, double** %ptr, <2 x doub
 ;CHECK-LABEL: test_v2f64_post_imm_st3lane:
 ;CHECK: st3.d { v0, v1, v2 }[0], [x0], #24
   call void @llvm.aarch64.neon.st3lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 3
+  %tmp = getelementptr double, double* %A, i64 3
   ret double* %tmp
 }
 
@@ -5436,7 +5436,7 @@ define double* @test_v2f64_post_reg_st3lane(double* %A, double** %ptr, <2 x doub
 ;CHECK-LABEL: test_v2f64_post_reg_st3lane:
 ;CHECK: st3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -5447,7 +5447,7 @@ define double* @test_v1f64_post_imm_st3lane(double* %A, double** %ptr, <1 x doub
 ;CHECK-LABEL: test_v1f64_post_imm_st3lane:
 ;CHECK: st3.d { v0, v1, v2 }[0], [x0], #24
   call void @llvm.aarch64.neon.st3lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 3
+  %tmp = getelementptr double, double* %A, i64 3
   ret double* %tmp
 }
 
@@ -5455,7 +5455,7 @@ define double* @test_v1f64_post_reg_st3lane(double* %A, double** %ptr, <1 x doub
 ;CHECK-LABEL: test_v1f64_post_reg_st3lane:
 ;CHECK: st3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st3lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -5466,7 +5466,7 @@ define i8* @test_v16i8_post_imm_st4lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i
 ;CHECK-LABEL: test_v16i8_post_imm_st4lane:
 ;CHECK: st4.b { v0, v1, v2, v3 }[0], [x0], #4
   call void @llvm.aarch64.neon.st4lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i32 4
+  %tmp = getelementptr i8, i8* %A, i32 4
   ret i8* %tmp
 }
 
@@ -5474,7 +5474,7 @@ define i8* @test_v16i8_post_reg_st4lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i
 ;CHECK-LABEL: test_v16i8_post_reg_st4lane:
 ;CHECK: st4.b { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -5485,7 +5485,7 @@ define i8* @test_v8i8_post_imm_st4lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8>
 ;CHECK-LABEL: test_v8i8_post_imm_st4lane:
 ;CHECK: st4.b { v0, v1, v2, v3 }[0], [x0], #4
   call void @llvm.aarch64.neon.st4lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i32 4
+  %tmp = getelementptr i8, i8* %A, i32 4
   ret i8* %tmp
 }
 
@@ -5493,7 +5493,7 @@ define i8* @test_v8i8_post_reg_st4lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8>
 ;CHECK-LABEL: test_v8i8_post_reg_st4lane:
 ;CHECK: st4.b { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, i8* %A)
-  %tmp = getelementptr i8* %A, i64 %inc
+  %tmp = getelementptr i8, i8* %A, i64 %inc
   ret i8* %tmp
 }
 
@@ -5504,7 +5504,7 @@ define i16* @test_v8i16_post_imm_st4lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x
 ;CHECK-LABEL: test_v8i16_post_imm_st4lane:
 ;CHECK: st4.h { v0, v1, v2, v3 }[0], [x0], #8
   call void @llvm.aarch64.neon.st4lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i32 4
+  %tmp = getelementptr i16, i16* %A, i32 4
   ret i16* %tmp
 }
 
@@ -5512,7 +5512,7 @@ define i16* @test_v8i16_post_reg_st4lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x
 ;CHECK-LABEL: test_v8i16_post_reg_st4lane:
 ;CHECK: st4.h { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -5523,7 +5523,7 @@ define i16* @test_v4i16_post_imm_st4lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x
 ;CHECK-LABEL: test_v4i16_post_imm_st4lane:
 ;CHECK: st4.h { v0, v1, v2, v3 }[0], [x0], #8
   call void @llvm.aarch64.neon.st4lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i32 4
+  %tmp = getelementptr i16, i16* %A, i32 4
   ret i16* %tmp
 }
 
@@ -5531,7 +5531,7 @@ define i16* @test_v4i16_post_reg_st4lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x
 ;CHECK-LABEL: test_v4i16_post_reg_st4lane:
 ;CHECK: st4.h { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, i16* %A)
-  %tmp = getelementptr i16* %A, i64 %inc
+  %tmp = getelementptr i16, i16* %A, i64 %inc
   ret i16* %tmp
 }
 
@@ -5542,7 +5542,7 @@ define i32* @test_v4i32_post_imm_st4lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x
 ;CHECK-LABEL: test_v4i32_post_imm_st4lane:
 ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], #16
   call void @llvm.aarch64.neon.st4lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i32 4
+  %tmp = getelementptr i32, i32* %A, i32 4
   ret i32* %tmp
 }
 
@@ -5550,7 +5550,7 @@ define i32* @test_v4i32_post_reg_st4lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x
 ;CHECK-LABEL: test_v4i32_post_reg_st4lane:
 ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -5561,7 +5561,7 @@ define i32* @test_v2i32_post_imm_st4lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x
 ;CHECK-LABEL: test_v2i32_post_imm_st4lane:
 ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], #16
   call void @llvm.aarch64.neon.st4lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i32 4
+  %tmp = getelementptr i32, i32* %A, i32 4
   ret i32* %tmp
 }
 
@@ -5569,7 +5569,7 @@ define i32* @test_v2i32_post_reg_st4lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x
 ;CHECK-LABEL: test_v2i32_post_reg_st4lane:
 ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, i32* %A)
-  %tmp = getelementptr i32* %A, i64 %inc
+  %tmp = getelementptr i32, i32* %A, i64 %inc
   ret i32* %tmp
 }
 
@@ -5580,7 +5580,7 @@ define i64* @test_v2i64_post_imm_st4lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x
 ;CHECK-LABEL: test_v2i64_post_imm_st4lane:
 ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], #32
   call void @llvm.aarch64.neon.st4lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 4
+  %tmp = getelementptr i64, i64* %A, i64 4
   ret i64* %tmp
 }
 
@@ -5588,7 +5588,7 @@ define i64* @test_v2i64_post_reg_st4lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x
 ;CHECK-LABEL: test_v2i64_post_reg_st4lane:
 ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -5599,7 +5599,7 @@ define i64* @test_v1i64_post_imm_st4lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x
 ;CHECK-LABEL: test_v1i64_post_imm_st4lane:
 ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], #32
   call void @llvm.aarch64.neon.st4lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 4
+  %tmp = getelementptr i64, i64* %A, i64 4
   ret i64* %tmp
 }
 
@@ -5607,7 +5607,7 @@ define i64* @test_v1i64_post_reg_st4lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x
 ;CHECK-LABEL: test_v1i64_post_reg_st4lane:
 ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, i64* %A)
-  %tmp = getelementptr i64* %A, i64 %inc
+  %tmp = getelementptr i64, i64* %A, i64 %inc
   ret i64* %tmp
 }
 
@@ -5618,7 +5618,7 @@ define float* @test_v4f32_post_imm_st4lane(float* %A, float** %ptr, <4 x float>
 ;CHECK-LABEL: test_v4f32_post_imm_st4lane:
 ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], #16
   call void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i32 4
+  %tmp = getelementptr float, float* %A, i32 4
   ret float* %tmp
 }
 
@@ -5626,7 +5626,7 @@ define float* @test_v4f32_post_reg_st4lane(float* %A, float** %ptr, <4 x float>
 ;CHECK-LABEL: test_v4f32_post_reg_st4lane:
 ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -5637,7 +5637,7 @@ define float* @test_v2f32_post_imm_st4lane(float* %A, float** %ptr, <2 x float>
 ;CHECK-LABEL: test_v2f32_post_imm_st4lane:
 ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], #16
   call void @llvm.aarch64.neon.st4lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i32 4
+  %tmp = getelementptr float, float* %A, i32 4
   ret float* %tmp
 }
 
@@ -5645,7 +5645,7 @@ define float* @test_v2f32_post_reg_st4lane(float* %A, float** %ptr, <2 x float>
 ;CHECK-LABEL: test_v2f32_post_reg_st4lane:
 ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, float* %A)
-  %tmp = getelementptr float* %A, i64 %inc
+  %tmp = getelementptr float, float* %A, i64 %inc
   ret float* %tmp
 }
 
@@ -5656,7 +5656,7 @@ define double* @test_v2f64_post_imm_st4lane(double* %A, double** %ptr, <2 x doub
 ;CHECK-LABEL: test_v2f64_post_imm_st4lane:
 ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], #32
   call void @llvm.aarch64.neon.st4lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 4
+  %tmp = getelementptr double, double* %A, i64 4
   ret double* %tmp
 }
 
@@ -5664,7 +5664,7 @@ define double* @test_v2f64_post_reg_st4lane(double* %A, double** %ptr, <2 x doub
 ;CHECK-LABEL: test_v2f64_post_reg_st4lane:
 ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -5675,7 +5675,7 @@ define double* @test_v1f64_post_imm_st4lane(double* %A, double** %ptr, <1 x doub
 ;CHECK-LABEL: test_v1f64_post_imm_st4lane:
 ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], #32
   call void @llvm.aarch64.neon.st4lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 4
+  %tmp = getelementptr double, double* %A, i64 4
   ret double* %tmp
 }
 
@@ -5683,7 +5683,7 @@ define double* @test_v1f64_post_reg_st4lane(double* %A, double** %ptr, <1 x doub
 ;CHECK-LABEL: test_v1f64_post_reg_st4lane:
 ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
   call void @llvm.aarch64.neon.st4lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, double* %A)
-  %tmp = getelementptr double* %A, i64 %inc
+  %tmp = getelementptr double, double* %A, i64 %inc
   ret double* %tmp
 }
 
@@ -5692,7 +5692,7 @@ declare void @llvm.aarch64.neon.st4lane.v1f64.p0f64(<1 x double>, <1 x double>,
 define <16 x i8> @test_v16i8_post_imm_ld1r(i8* %bar, i8** %ptr) {
 ; CHECK-LABEL: test_v16i8_post_imm_ld1r:
 ; CHECK: ld1r.16b { v0 }, [x0], #1
-  %tmp1 = load i8* %bar
+  %tmp1 = load i8, i8* %bar
   %tmp2 = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
   %tmp3 = insertelement <16 x i8> %tmp2, i8 %tmp1, i32 1
   %tmp4 = insertelement <16 x i8> %tmp3, i8 %tmp1, i32 2
@@ -5709,7 +5709,7 @@ define <16 x i8> @test_v16i8_post_imm_ld1r(i8* %bar, i8** %ptr) {
   %tmp15 = insertelement <16 x i8> %tmp14, i8 %tmp1, i32 13
   %tmp16 = insertelement <16 x i8> %tmp15, i8 %tmp1, i32 14
   %tmp17 = insertelement <16 x i8> %tmp16, i8 %tmp1, i32 15
-  %tmp18 = getelementptr i8* %bar, i64 1
+  %tmp18 = getelementptr i8, i8* %bar, i64 1
   store i8* %tmp18, i8** %ptr
   ret <16 x i8> %tmp17
 }
@@ -5717,7 +5717,7 @@ define <16 x i8> @test_v16i8_post_imm_ld1r(i8* %bar, i8** %ptr) {
 define <16 x i8> @test_v16i8_post_reg_ld1r(i8* %bar, i8** %ptr, i64 %inc) {
 ; CHECK-LABEL: test_v16i8_post_reg_ld1r:
 ; CHECK: ld1r.16b { v0 }, [x0], x{{[0-9]+}}
-  %tmp1 = load i8* %bar
+  %tmp1 = load i8, i8* %bar
   %tmp2 = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
   %tmp3 = insertelement <16 x i8> %tmp2, i8 %tmp1, i32 1
   %tmp4 = insertelement <16 x i8> %tmp3, i8 %tmp1, i32 2
@@ -5734,7 +5734,7 @@ define <16 x i8> @test_v16i8_post_reg_ld1r(i8* %bar, i8** %ptr, i64 %inc) {
   %tmp15 = insertelement <16 x i8> %tmp14, i8 %tmp1, i32 13
   %tmp16 = insertelement <16 x i8> %tmp15, i8 %tmp1, i32 14
   %tmp17 = insertelement <16 x i8> %tmp16, i8 %tmp1, i32 15
-  %tmp18 = getelementptr i8* %bar, i64 %inc
+  %tmp18 = getelementptr i8, i8* %bar, i64 %inc
   store i8* %tmp18, i8** %ptr
   ret <16 x i8> %tmp17
 }
@@ -5742,7 +5742,7 @@ define <16 x i8> @test_v16i8_post_reg_ld1r(i8* %bar, i8** %ptr, i64 %inc) {
 define <8 x i8> @test_v8i8_post_imm_ld1r(i8* %bar, i8** %ptr) {
 ; CHECK-LABEL: test_v8i8_post_imm_ld1r:
 ; CHECK: ld1r.8b { v0 }, [x0], #1
-  %tmp1 = load i8* %bar
+  %tmp1 = load i8, i8* %bar
   %tmp2 = insertelement <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
   %tmp3 = insertelement <8 x i8> %tmp2, i8 %tmp1, i32 1
   %tmp4 = insertelement <8 x i8> %tmp3, i8 %tmp1, i32 2
@@ -5751,7 +5751,7 @@ define <8 x i8> @test_v8i8_post_imm_ld1r(i8* %bar, i8** %ptr) {
   %tmp7 = insertelement <8 x i8> %tmp6, i8 %tmp1, i32 5
   %tmp8 = insertelement <8 x i8> %tmp7, i8 %tmp1, i32 6
   %tmp9 = insertelement <8 x i8> %tmp8, i8 %tmp1, i32 7
-  %tmp10 = getelementptr i8* %bar, i64 1
+  %tmp10 = getelementptr i8, i8* %bar, i64 1
   store i8* %tmp10, i8** %ptr
   ret <8 x i8> %tmp9
 }
@@ -5759,7 +5759,7 @@ define <8 x i8> @test_v8i8_post_imm_ld1r(i8* %bar, i8** %ptr) {
 define <8 x i8> @test_v8i8_post_reg_ld1r(i8* %bar, i8** %ptr, i64 %inc) {
 ; CHECK-LABEL: test_v8i8_post_reg_ld1r:
 ; CHECK: ld1r.8b { v0 }, [x0], x{{[0-9]+}}
-  %tmp1 = load i8* %bar
+  %tmp1 = load i8, i8* %bar
   %tmp2 = insertelement <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
   %tmp3 = insertelement <8 x i8> %tmp2, i8 %tmp1, i32 1
   %tmp4 = insertelement <8 x i8> %tmp3, i8 %tmp1, i32 2
@@ -5768,7 +5768,7 @@ define <8 x i8> @test_v8i8_post_reg_ld1r(i8* %bar, i8** %ptr, i64 %inc) {
   %tmp7 = insertelement <8 x i8> %tmp6, i8 %tmp1, i32 5
   %tmp8 = insertelement <8 x i8> %tmp7, i8 %tmp1, i32 6
   %tmp9 = insertelement <8 x i8> %tmp8, i8 %tmp1, i32 7
-  %tmp10 = getelementptr i8* %bar, i64 %inc
+  %tmp10 = getelementptr i8, i8* %bar, i64 %inc
   store i8* %tmp10, i8** %ptr
   ret <8 x i8> %tmp9
 }
@@ -5776,7 +5776,7 @@ define <8 x i8> @test_v8i8_post_reg_ld1r(i8* %bar, i8** %ptr, i64 %inc) {
 define <8 x i16> @test_v8i16_post_imm_ld1r(i16* %bar, i16** %ptr) {
 ; CHECK-LABEL: test_v8i16_post_imm_ld1r:
 ; CHECK: ld1r.8h { v0 }, [x0], #2
-  %tmp1 = load i16* %bar
+  %tmp1 = load i16, i16* %bar
   %tmp2 = insertelement <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0
   %tmp3 = insertelement <8 x i16> %tmp2, i16 %tmp1, i32 1
   %tmp4 = insertelement <8 x i16> %tmp3, i16 %tmp1, i32 2
@@ -5785,7 +5785,7 @@ define <8 x i16> @test_v8i16_post_imm_ld1r(i16* %bar, i16** %ptr) {
   %tmp7 = insertelement <8 x i16> %tmp6, i16 %tmp1, i32 5
   %tmp8 = insertelement <8 x i16> %tmp7, i16 %tmp1, i32 6
   %tmp9 = insertelement <8 x i16> %tmp8, i16 %tmp1, i32 7
-  %tmp10 = getelementptr i16* %bar, i64 1
+  %tmp10 = getelementptr i16, i16* %bar, i64 1
   store i16* %tmp10, i16** %ptr
   ret <8 x i16> %tmp9
 }
@@ -5793,7 +5793,7 @@ define <8 x i16> @test_v8i16_post_imm_ld1r(i16* %bar, i16** %ptr) {
 define <8 x i16> @test_v8i16_post_reg_ld1r(i16* %bar, i16** %ptr, i64 %inc) {
 ; CHECK-LABEL: test_v8i16_post_reg_ld1r:
 ; CHECK: ld1r.8h { v0 }, [x0], x{{[0-9]+}}
-  %tmp1 = load i16* %bar
+  %tmp1 = load i16, i16* %bar
   %tmp2 = insertelement <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0
   %tmp3 = insertelement <8 x i16> %tmp2, i16 %tmp1, i32 1
   %tmp4 = insertelement <8 x i16> %tmp3, i16 %tmp1, i32 2
@@ -5802,7 +5802,7 @@ define <8 x i16> @test_v8i16_post_reg_ld1r(i16* %bar, i16** %ptr, i64 %inc) {
   %tmp7 = insertelement <8 x i16> %tmp6, i16 %tmp1, i32 5
   %tmp8 = insertelement <8 x i16> %tmp7, i16 %tmp1, i32 6
   %tmp9 = insertelement <8 x i16> %tmp8, i16 %tmp1, i32 7
-  %tmp10 = getelementptr i16* %bar, i64 %inc
+  %tmp10 = getelementptr i16, i16* %bar, i64 %inc
   store i16* %tmp10, i16** %ptr
   ret <8 x i16> %tmp9
 }
@@ -5810,12 +5810,12 @@ define <8 x i16> @test_v8i16_post_reg_ld1r(i16* %bar, i16** %ptr, i64 %inc) {
 define <4 x i16> @test_v4i16_post_imm_ld1r(i16* %bar, i16** %ptr) {
 ; CHECK-LABEL: test_v4i16_post_imm_ld1r:
 ; CHECK: ld1r.4h { v0 }, [x0], #2
-  %tmp1 = load i16* %bar
+  %tmp1 = load i16, i16* %bar
   %tmp2 = insertelement <4 x i16> <i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0
   %tmp3 = insertelement <4 x i16> %tmp2, i16 %tmp1, i32 1
   %tmp4 = insertelement <4 x i16> %tmp3, i16 %tmp1, i32 2
   %tmp5 = insertelement <4 x i16> %tmp4, i16 %tmp1, i32 3
-  %tmp6 = getelementptr i16* %bar, i64 1
+  %tmp6 = getelementptr i16, i16* %bar, i64 1
   store i16* %tmp6, i16** %ptr
   ret <4 x i16> %tmp5
 }
@@ -5823,12 +5823,12 @@ define <4 x i16> @test_v4i16_post_imm_ld1r(i16* %bar, i16** %ptr) {
 define <4 x i16> @test_v4i16_post_reg_ld1r(i16* %bar, i16** %ptr, i64 %inc) {
 ; CHECK-LABEL: test_v4i16_post_reg_ld1r:
 ; CHECK: ld1r.4h { v0 }, [x0], x{{[0-9]+}}
-  %tmp1 = load i16* %bar
+  %tmp1 = load i16, i16* %bar
   %tmp2 = insertelement <4 x i16> <i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0
   %tmp3 = insertelement <4 x i16> %tmp2, i16 %tmp1, i32 1
   %tmp4 = insertelement <4 x i16> %tmp3, i16 %tmp1, i32 2
   %tmp5 = insertelement <4 x i16> %tmp4, i16 %tmp1, i32 3
-  %tmp6 = getelementptr i16* %bar, i64 %inc
+  %tmp6 = getelementptr i16, i16* %bar, i64 %inc
   store i16* %tmp6, i16** %ptr
   ret <4 x i16> %tmp5
 }
@@ -5836,12 +5836,12 @@ define <4 x i16> @test_v4i16_post_reg_ld1r(i16* %bar, i16** %ptr, i64 %inc) {
 define <4 x i32> @test_v4i32_post_imm_ld1r(i32* %bar, i32** %ptr) {
 ; CHECK-LABEL: test_v4i32_post_imm_ld1r:
 ; CHECK: ld1r.4s { v0 }, [x0], #4
-  %tmp1 = load i32* %bar
+  %tmp1 = load i32, i32* %bar
   %tmp2 = insertelement <4 x i32> <i32 undef, i32 undef, i32 undef, i32 undef>, i32 %tmp1, i32 0
   %tmp3 = insertelement <4 x i32> %tmp2, i32 %tmp1, i32 1
   %tmp4 = insertelement <4 x i32> %tmp3, i32 %tmp1, i32 2
   %tmp5 = insertelement <4 x i32> %tmp4, i32 %tmp1, i32 3
-  %tmp6 = getelementptr i32* %bar, i64 1
+  %tmp6 = getelementptr i32, i32* %bar, i64 1
   store i32* %tmp6, i32** %ptr
   ret <4 x i32> %tmp5
 }
@@ -5849,12 +5849,12 @@ define <4 x i32> @test_v4i32_post_imm_ld1r(i32* %bar, i32** %ptr) {
 define <4 x i32> @test_v4i32_post_reg_ld1r(i32* %bar, i32** %ptr, i64 %inc) {
 ; CHECK-LABEL: test_v4i32_post_reg_ld1r:
 ; CHECK: ld1r.4s { v0 }, [x0], x{{[0-9]+}}
-  %tmp1 = load i32* %bar
+  %tmp1 = load i32, i32* %bar
   %tmp2 = insertelement <4 x i32> <i32 undef, i32 undef, i32 undef, i32 undef>, i32 %tmp1, i32 0
   %tmp3 = insertelement <4 x i32> %tmp2, i32 %tmp1, i32 1
   %tmp4 = insertelement <4 x i32> %tmp3, i32 %tmp1, i32 2
   %tmp5 = insertelement <4 x i32> %tmp4, i32 %tmp1, i32 3
-  %tmp6 = getelementptr i32* %bar, i64 %inc
+  %tmp6 = getelementptr i32, i32* %bar, i64 %inc
   store i32* %tmp6, i32** %ptr
   ret <4 x i32> %tmp5
 }
@@ -5862,10 +5862,10 @@ define <4 x i32> @test_v4i32_post_reg_ld1r(i32* %bar, i32** %ptr, i64 %inc) {
 define <2 x i32> @test_v2i32_post_imm_ld1r(i32* %bar, i32** %ptr) {
 ; CHECK-LABEL: test_v2i32_post_imm_ld1r:
 ; CHECK: ld1r.2s { v0 }, [x0], #4
-  %tmp1 = load i32* %bar
+  %tmp1 = load i32, i32* %bar
   %tmp2 = insertelement <2 x i32> <i32 undef, i32 undef>, i32 %tmp1, i32 0
   %tmp3 = insertelement <2 x i32> %tmp2, i32 %tmp1, i32 1
-  %tmp4 = getelementptr i32* %bar, i64 1
+  %tmp4 = getelementptr i32, i32* %bar, i64 1
   store i32* %tmp4, i32** %ptr
   ret <2 x i32> %tmp3
 }
@@ -5873,10 +5873,10 @@ define <2 x i32> @test_v2i32_post_imm_ld1r(i32* %bar, i32** %ptr) {
 define <2 x i32> @test_v2i32_post_reg_ld1r(i32* %bar, i32** %ptr, i64 %inc) {
 ; CHECK-LABEL: test_v2i32_post_reg_ld1r:
 ; CHECK: ld1r.2s { v0 }, [x0], x{{[0-9]+}}
-  %tmp1 = load i32* %bar
+  %tmp1 = load i32, i32* %bar
   %tmp2 = insertelement <2 x i32> <i32 undef, i32 undef>, i32 %tmp1, i32 0
   %tmp3 = insertelement <2 x i32> %tmp2, i32 %tmp1, i32 1
-  %tmp4 = getelementptr i32* %bar, i64 %inc
+  %tmp4 = getelementptr i32, i32* %bar, i64 %inc
   store i32* %tmp4, i32** %ptr
   ret <2 x i32> %tmp3
 }
@@ -5884,10 +5884,10 @@ define <2 x i32> @test_v2i32_post_reg_ld1r(i32* %bar, i32** %ptr, i64 %inc) {
 define <2 x i64> @test_v2i64_post_imm_ld1r(i64* %bar, i64** %ptr) {
 ; CHECK-LABEL: test_v2i64_post_imm_ld1r:
 ; CHECK: ld1r.2d { v0 }, [x0], #8
-  %tmp1 = load i64* %bar
+  %tmp1 = load i64, i64* %bar
   %tmp2 = insertelement <2 x i64> <i64 undef, i64 undef>, i64 %tmp1, i32 0
   %tmp3 = insertelement <2 x i64> %tmp2, i64 %tmp1, i32 1
-  %tmp4 = getelementptr i64* %bar, i64 1
+  %tmp4 = getelementptr i64, i64* %bar, i64 1
   store i64* %tmp4, i64** %ptr
   ret <2 x i64> %tmp3
 }
@@ -5895,10 +5895,10 @@ define <2 x i64> @test_v2i64_post_imm_ld1r(i64* %bar, i64** %ptr) {
 define <2 x i64> @test_v2i64_post_reg_ld1r(i64* %bar, i64** %ptr, i64 %inc) {
 ; CHECK-LABEL: test_v2i64_post_reg_ld1r:
 ; CHECK: ld1r.2d { v0 }, [x0], x{{[0-9]+}}
-  %tmp1 = load i64* %bar
+  %tmp1 = load i64, i64* %bar
   %tmp2 = insertelement <2 x i64> <i64 undef, i64 undef>, i64 %tmp1, i32 0
   %tmp3 = insertelement <2 x i64> %tmp2, i64 %tmp1, i32 1
-  %tmp4 = getelementptr i64* %bar, i64 %inc
+  %tmp4 = getelementptr i64, i64* %bar, i64 %inc
   store i64* %tmp4, i64** %ptr
   ret <2 x i64> %tmp3
 }
@@ -5906,12 +5906,12 @@ define <2 x i64> @test_v2i64_post_reg_ld1r(i64* %bar, i64** %ptr, i64 %inc) {
 define <4 x float> @test_v4f32_post_imm_ld1r(float* %bar, float** %ptr) {
 ; CHECK-LABEL: test_v4f32_post_imm_ld1r:
 ; CHECK: ld1r.4s { v0 }, [x0], #4
-  %tmp1 = load float* %bar
+  %tmp1 = load float, float* %bar
   %tmp2 = insertelement <4 x float> <float undef, float undef, float undef, float undef>, float %tmp1, i32 0
   %tmp3 = insertelement <4 x float> %tmp2, float %tmp1, i32 1
   %tmp4 = insertelement <4 x float> %tmp3, float %tmp1, i32 2
   %tmp5 = insertelement <4 x float> %tmp4, float %tmp1, i32 3
-  %tmp6 = getelementptr float* %bar, i64 1
+  %tmp6 = getelementptr float, float* %bar, i64 1
   store float* %tmp6, float** %ptr
   ret <4 x float> %tmp5
 }
@@ -5919,12 +5919,12 @@ define <4 x float> @test_v4f32_post_imm_ld1r(float* %bar, float** %ptr) {
 define <4 x float> @test_v4f32_post_reg_ld1r(float* %bar, float** %ptr, i64 %inc) {
 ; CHECK-LABEL: test_v4f32_post_reg_ld1r:
 ; CHECK: ld1r.4s { v0 }, [x0], x{{[0-9]+}}
-  %tmp1 = load float* %bar
+  %tmp1 = load float, float* %bar
   %tmp2 = insertelement <4 x float> <float undef, float undef, float undef, float undef>, float %tmp1, i32 0
   %tmp3 = insertelement <4 x float> %tmp2, float %tmp1, i32 1
   %tmp4 = insertelement <4 x float> %tmp3, float %tmp1, i32 2
   %tmp5 = insertelement <4 x float> %tmp4, float %tmp1, i32 3
-  %tmp6 = getelementptr float* %bar, i64 %inc
+  %tmp6 = getelementptr float, float* %bar, i64 %inc
   store float* %tmp6, float** %ptr
   ret <4 x float> %tmp5
 }
@@ -5932,10 +5932,10 @@ define <4 x float> @test_v4f32_post_reg_ld1r(float* %bar, float** %ptr, i64 %inc
 define <2 x float> @test_v2f32_post_imm_ld1r(float* %bar, float** %ptr) {
 ; CHECK-LABEL: test_v2f32_post_imm_ld1r:
 ; CHECK: ld1r.2s { v0 }, [x0], #4
-  %tmp1 = load float* %bar
+  %tmp1 = load float, float* %bar
   %tmp2 = insertelement <2 x float> <float undef, float undef>, float %tmp1, i32 0
   %tmp3 = insertelement <2 x float> %tmp2, float %tmp1, i32 1
-  %tmp4 = getelementptr float* %bar, i64 1
+  %tmp4 = getelementptr float, float* %bar, i64 1
   store float* %tmp4, float** %ptr
   ret <2 x float> %tmp3
 }
@@ -5943,10 +5943,10 @@ define <2 x float> @test_v2f32_post_imm_ld1r(float* %bar, float** %ptr) {
 define <2 x float> @test_v2f32_post_reg_ld1r(float* %bar, float** %ptr, i64 %inc) {
 ; CHECK-LABEL: test_v2f32_post_reg_ld1r:
 ; CHECK: ld1r.2s { v0 }, [x0], x{{[0-9]+}}
-  %tmp1 = load float* %bar
+  %tmp1 = load float, float* %bar
   %tmp2 = insertelement <2 x float> <float undef, float undef>, float %tmp1, i32 0
   %tmp3 = insertelement <2 x float> %tmp2, float %tmp1, i32 1
-  %tmp4 = getelementptr float* %bar, i64 %inc
+  %tmp4 = getelementptr float, float* %bar, i64 %inc
   store float* %tmp4, float** %ptr
   ret <2 x float> %tmp3
 }
@@ -5954,10 +5954,10 @@ define <2 x float> @test_v2f32_post_reg_ld1r(float* %bar, float** %ptr, i64 %inc
 define <2 x double> @test_v2f64_post_imm_ld1r(double* %bar, double** %ptr) {
 ; CHECK-LABEL: test_v2f64_post_imm_ld1r:
 ; CHECK: ld1r.2d { v0 }, [x0], #8
-  %tmp1 = load double* %bar
+  %tmp1 = load double, double* %bar
   %tmp2 = insertelement <2 x double> <double undef, double undef>, double %tmp1, i32 0
   %tmp3 = insertelement <2 x double> %tmp2, double %tmp1, i32 1
-  %tmp4 = getelementptr double* %bar, i64 1
+  %tmp4 = getelementptr double, double* %bar, i64 1
   store double* %tmp4, double** %ptr
   ret <2 x double> %tmp3
 }
@@ -5965,10 +5965,10 @@ define <2 x double> @test_v2f64_post_imm_ld1r(double* %bar, double** %ptr) {
 define <2 x double> @test_v2f64_post_reg_ld1r(double* %bar, double** %ptr, i64 %inc) {
 ; CHECK-LABEL: test_v2f64_post_reg_ld1r:
 ; CHECK: ld1r.2d { v0 }, [x0], x{{[0-9]+}}
-  %tmp1 = load double* %bar
+  %tmp1 = load double, double* %bar
   %tmp2 = insertelement <2 x double> <double undef, double undef>, double %tmp1, i32 0
   %tmp3 = insertelement <2 x double> %tmp2, double %tmp1, i32 1
-  %tmp4 = getelementptr double* %bar, i64 %inc
+  %tmp4 = getelementptr double, double* %bar, i64 %inc
   store double* %tmp4, double** %ptr
   ret <2 x double> %tmp3
 }
@@ -5976,9 +5976,9 @@ define <2 x double> @test_v2f64_post_reg_ld1r(double* %bar, double** %ptr, i64 %
 define <16 x i8> @test_v16i8_post_imm_ld1lane(i8* %bar, i8** %ptr, <16 x i8> %A) {
 ; CHECK-LABEL: test_v16i8_post_imm_ld1lane:
 ; CHECK: ld1.b { v0 }[1], [x0], #1
-  %tmp1 = load i8* %bar
+  %tmp1 = load i8, i8* %bar
   %tmp2 = insertelement <16 x i8> %A, i8 %tmp1, i32 1
-  %tmp3 = getelementptr i8* %bar, i64 1
+  %tmp3 = getelementptr i8, i8* %bar, i64 1
   store i8* %tmp3, i8** %ptr
   ret <16 x i8> %tmp2
 }
@@ -5986,9 +5986,9 @@ define <16 x i8> @test_v16i8_post_imm_ld1lane(i8* %bar, i8** %ptr, <16 x i8> %A)
 define <16 x i8> @test_v16i8_post_reg_ld1lane(i8* %bar, i8** %ptr, i64 %inc, <16 x i8> %A) {
 ; CHECK-LABEL: test_v16i8_post_reg_ld1lane:
 ; CHECK: ld1.b { v0 }[1], [x0], x{{[0-9]+}}
-  %tmp1 = load i8* %bar
+  %tmp1 = load i8, i8* %bar
   %tmp2 = insertelement <16 x i8> %A, i8 %tmp1, i32 1
-  %tmp3 = getelementptr i8* %bar, i64 %inc
+  %tmp3 = getelementptr i8, i8* %bar, i64 %inc
   store i8* %tmp3, i8** %ptr
   ret <16 x i8> %tmp2
 }
@@ -5996,9 +5996,9 @@ define <16 x i8> @test_v16i8_post_reg_ld1lane(i8* %bar, i8** %ptr, i64 %inc, <16
 define <8 x i8> @test_v8i8_post_imm_ld1lane(i8* %bar, i8** %ptr, <8 x i8> %A) {
 ; CHECK-LABEL: test_v8i8_post_imm_ld1lane:
 ; CHECK: ld1.b { v0 }[1], [x0], #1
-  %tmp1 = load i8* %bar
+  %tmp1 = load i8, i8* %bar
   %tmp2 = insertelement <8 x i8> %A, i8 %tmp1, i32 1
-  %tmp3 = getelementptr i8* %bar, i64 1
+  %tmp3 = getelementptr i8, i8* %bar, i64 1
   store i8* %tmp3, i8** %ptr
   ret <8 x i8> %tmp2
 }
@@ -6006,9 +6006,9 @@ define <8 x i8> @test_v8i8_post_imm_ld1lane(i8* %bar, i8** %ptr, <8 x i8> %A) {
 define <8 x i8> @test_v8i8_post_reg_ld1lane(i8* %bar, i8** %ptr, i64 %inc, <8 x i8> %A) {
 ; CHECK-LABEL: test_v8i8_post_reg_ld1lane:
 ; CHECK: ld1.b { v0 }[1], [x0], x{{[0-9]+}}
-  %tmp1 = load i8* %bar
+  %tmp1 = load i8, i8* %bar
   %tmp2 = insertelement <8 x i8> %A, i8 %tmp1, i32 1
-  %tmp3 = getelementptr i8* %bar, i64 %inc
+  %tmp3 = getelementptr i8, i8* %bar, i64 %inc
   store i8* %tmp3, i8** %ptr
   ret <8 x i8> %tmp2
 }
@@ -6016,9 +6016,9 @@ define <8 x i8> @test_v8i8_post_reg_ld1lane(i8* %bar, i8** %ptr, i64 %inc, <8 x
 define <8 x i16> @test_v8i16_post_imm_ld1lane(i16* %bar, i16** %ptr, <8 x i16> %A) {
 ; CHECK-LABEL: test_v8i16_post_imm_ld1lane:
 ; CHECK: ld1.h { v0 }[1], [x0], #2
-  %tmp1 = load i16* %bar
+  %tmp1 = load i16, i16* %bar
   %tmp2 = insertelement <8 x i16> %A, i16 %tmp1, i32 1
-  %tmp3 = getelementptr i16* %bar, i64 1
+  %tmp3 = getelementptr i16, i16* %bar, i64 1
   store i16* %tmp3, i16** %ptr
   ret <8 x i16> %tmp2
 }
@@ -6026,9 +6026,9 @@ define <8 x i16> @test_v8i16_post_imm_ld1lane(i16* %bar, i16** %ptr, <8 x i16> %
 define <8 x i16> @test_v8i16_post_reg_ld1lane(i16* %bar, i16** %ptr, i64 %inc, <8 x i16> %A) {
 ; CHECK-LABEL: test_v8i16_post_reg_ld1lane:
 ; CHECK: ld1.h { v0 }[1], [x0], x{{[0-9]+}}
-  %tmp1 = load i16* %bar
+  %tmp1 = load i16, i16* %bar
   %tmp2 = insertelement <8 x i16> %A, i16 %tmp1, i32 1
-  %tmp3 = getelementptr i16* %bar, i64 %inc
+  %tmp3 = getelementptr i16, i16* %bar, i64 %inc
   store i16* %tmp3, i16** %ptr
   ret <8 x i16> %tmp2
 }
@@ -6036,9 +6036,9 @@ define <8 x i16> @test_v8i16_post_reg_ld1lane(i16* %bar, i16** %ptr, i64 %inc, <
 define <4 x i16> @test_v4i16_post_imm_ld1lane(i16* %bar, i16** %ptr, <4 x i16> %A) {
 ; CHECK-LABEL: test_v4i16_post_imm_ld1lane:
 ; CHECK: ld1.h { v0 }[1], [x0], #2
-  %tmp1 = load i16* %bar
+  %tmp1 = load i16, i16* %bar
   %tmp2 = insertelement <4 x i16> %A, i16 %tmp1, i32 1
-  %tmp3 = getelementptr i16* %bar, i64 1
+  %tmp3 = getelementptr i16, i16* %bar, i64 1
   store i16* %tmp3, i16** %ptr
   ret <4 x i16> %tmp2
 }
@@ -6046,9 +6046,9 @@ define <4 x i16> @test_v4i16_post_imm_ld1lane(i16* %bar, i16** %ptr, <4 x i16> %
 define <4 x i16> @test_v4i16_post_reg_ld1lane(i16* %bar, i16** %ptr, i64 %inc, <4 x i16> %A) {
 ; CHECK-LABEL: test_v4i16_post_reg_ld1lane:
 ; CHECK: ld1.h { v0 }[1], [x0], x{{[0-9]+}}
-  %tmp1 = load i16* %bar
+  %tmp1 = load i16, i16* %bar
   %tmp2 = insertelement <4 x i16> %A, i16 %tmp1, i32 1
-  %tmp3 = getelementptr i16* %bar, i64 %inc
+  %tmp3 = getelementptr i16, i16* %bar, i64 %inc
   store i16* %tmp3, i16** %ptr
   ret <4 x i16> %tmp2
 }
@@ -6056,9 +6056,9 @@ define <4 x i16> @test_v4i16_post_reg_ld1lane(i16* %bar, i16** %ptr, i64 %inc, <
 define <4 x i32> @test_v4i32_post_imm_ld1lane(i32* %bar, i32** %ptr, <4 x i32> %A) {
 ; CHECK-LABEL: test_v4i32_post_imm_ld1lane:
 ; CHECK: ld1.s { v0 }[1], [x0], #4
-  %tmp1 = load i32* %bar
+  %tmp1 = load i32, i32* %bar
   %tmp2 = insertelement <4 x i32> %A, i32 %tmp1, i32 1
-  %tmp3 = getelementptr i32* %bar, i64 1
+  %tmp3 = getelementptr i32, i32* %bar, i64 1
   store i32* %tmp3, i32** %ptr
   ret <4 x i32> %tmp2
 }
@@ -6066,9 +6066,9 @@ define <4 x i32> @test_v4i32_post_imm_ld1lane(i32* %bar, i32** %ptr, <4 x i32> %
 define <4 x i32> @test_v4i32_post_reg_ld1lane(i32* %bar, i32** %ptr, i64 %inc, <4 x i32> %A) {
 ; CHECK-LABEL: test_v4i32_post_reg_ld1lane:
 ; CHECK: ld1.s { v0 }[1], [x0], x{{[0-9]+}}
-  %tmp1 = load i32* %bar
+  %tmp1 = load i32, i32* %bar
   %tmp2 = insertelement <4 x i32> %A, i32 %tmp1, i32 1
-  %tmp3 = getelementptr i32* %bar, i64 %inc
+  %tmp3 = getelementptr i32, i32* %bar, i64 %inc
   store i32* %tmp3, i32** %ptr
   ret <4 x i32> %tmp2
 }
@@ -6076,9 +6076,9 @@ define <4 x i32> @test_v4i32_post_reg_ld1lane(i32* %bar, i32** %ptr, i64 %inc, <
 define <2 x i32> @test_v2i32_post_imm_ld1lane(i32* %bar, i32** %ptr, <2 x i32> %A) {
 ; CHECK-LABEL: test_v2i32_post_imm_ld1lane:
 ; CHECK: ld1.s { v0 }[1], [x0], #4
-  %tmp1 = load i32* %bar
+  %tmp1 = load i32, i32* %bar
   %tmp2 = insertelement <2 x i32> %A, i32 %tmp1, i32 1
-  %tmp3 = getelementptr i32* %bar, i64 1
+  %tmp3 = getelementptr i32, i32* %bar, i64 1
   store i32* %tmp3, i32** %ptr
   ret <2 x i32> %tmp2
 }
@@ -6086,9 +6086,9 @@ define <2 x i32> @test_v2i32_post_imm_ld1lane(i32* %bar, i32** %ptr, <2 x i32> %
 define <2 x i32> @test_v2i32_post_reg_ld1lane(i32* %bar, i32** %ptr, i64 %inc, <2 x i32> %A) {
 ; CHECK-LABEL: test_v2i32_post_reg_ld1lane:
 ; CHECK: ld1.s { v0 }[1], [x0], x{{[0-9]+}}
-  %tmp1 = load i32* %bar
+  %tmp1 = load i32, i32* %bar
   %tmp2 = insertelement <2 x i32> %A, i32 %tmp1, i32 1
-  %tmp3 = getelementptr i32* %bar, i64 %inc
+  %tmp3 = getelementptr i32, i32* %bar, i64 %inc
   store i32* %tmp3, i32** %ptr
   ret <2 x i32> %tmp2
 }
@@ -6096,9 +6096,9 @@ define <2 x i32> @test_v2i32_post_reg_ld1lane(i32* %bar, i32** %ptr, i64 %inc, <
 define <2 x i64> @test_v2i64_post_imm_ld1lane(i64* %bar, i64** %ptr, <2 x i64> %A) {
 ; CHECK-LABEL: test_v2i64_post_imm_ld1lane:
 ; CHECK: ld1.d { v0 }[1], [x0], #8
-  %tmp1 = load i64* %bar
+  %tmp1 = load i64, i64* %bar
   %tmp2 = insertelement <2 x i64> %A, i64 %tmp1, i32 1
-  %tmp3 = getelementptr i64* %bar, i64 1
+  %tmp3 = getelementptr i64, i64* %bar, i64 1
   store i64* %tmp3, i64** %ptr
   ret <2 x i64> %tmp2
 }
@@ -6106,9 +6106,9 @@ define <2 x i64> @test_v2i64_post_imm_ld1lane(i64* %bar, i64** %ptr, <2 x i64> %
 define <2 x i64> @test_v2i64_post_reg_ld1lane(i64* %bar, i64** %ptr, i64 %inc, <2 x i64> %A) {
 ; CHECK-LABEL: test_v2i64_post_reg_ld1lane:
 ; CHECK: ld1.d { v0 }[1], [x0], x{{[0-9]+}}
-  %tmp1 = load i64* %bar
+  %tmp1 = load i64, i64* %bar
   %tmp2 = insertelement <2 x i64> %A, i64 %tmp1, i32 1
-  %tmp3 = getelementptr i64* %bar, i64 %inc
+  %tmp3 = getelementptr i64, i64* %bar, i64 %inc
   store i64* %tmp3, i64** %ptr
   ret <2 x i64> %tmp2
 }
@@ -6116,9 +6116,9 @@ define <2 x i64> @test_v2i64_post_reg_ld1lane(i64* %bar, i64** %ptr, i64 %inc, <
 define <4 x float> @test_v4f32_post_imm_ld1lane(float* %bar, float** %ptr, <4 x float> %A) {
 ; CHECK-LABEL: test_v4f32_post_imm_ld1lane:
 ; CHECK: ld1.s { v0 }[1], [x0], #4
-  %tmp1 = load float* %bar
+  %tmp1 = load float, float* %bar
   %tmp2 = insertelement <4 x float> %A, float %tmp1, i32 1
-  %tmp3 = getelementptr float* %bar, i64 1
+  %tmp3 = getelementptr float, float* %bar, i64 1
   store float* %tmp3, float** %ptr
   ret <4 x float> %tmp2
 }
@@ -6126,9 +6126,9 @@ define <4 x float> @test_v4f32_post_imm_ld1lane(float* %bar, float** %ptr, <4 x
 define <4 x float> @test_v4f32_post_reg_ld1lane(float* %bar, float** %ptr, i64 %inc, <4 x float> %A) {
 ; CHECK-LABEL: test_v4f32_post_reg_ld1lane:
 ; CHECK: ld1.s { v0 }[1], [x0], x{{[0-9]+}}
-  %tmp1 = load float* %bar
+  %tmp1 = load float, float* %bar
   %tmp2 = insertelement <4 x float> %A, float %tmp1, i32 1
-  %tmp3 = getelementptr float* %bar, i64 %inc
+  %tmp3 = getelementptr float, float* %bar, i64 %inc
   store float* %tmp3, float** %ptr
   ret <4 x float> %tmp2
 }
@@ -6136,9 +6136,9 @@ define <4 x float> @test_v4f32_post_reg_ld1lane(float* %bar, float** %ptr, i64 %
 define <2 x float> @test_v2f32_post_imm_ld1lane(float* %bar, float** %ptr, <2 x float> %A) {
 ; CHECK-LABEL: test_v2f32_post_imm_ld1lane:
 ; CHECK: ld1.s { v0 }[1], [x0], #4
-  %tmp1 = load float* %bar
+  %tmp1 = load float, float* %bar
   %tmp2 = insertelement <2 x float> %A, float %tmp1, i32 1
-  %tmp3 = getelementptr float* %bar, i64 1
+  %tmp3 = getelementptr float, float* %bar, i64 1
   store float* %tmp3, float** %ptr
   ret <2 x float> %tmp2
 }
@@ -6146,9 +6146,9 @@ define <2 x float> @test_v2f32_post_imm_ld1lane(float* %bar, float** %ptr, <2 x
 define <2 x float> @test_v2f32_post_reg_ld1lane(float* %bar, float** %ptr, i64 %inc, <2 x float> %A) {
 ; CHECK-LABEL: test_v2f32_post_reg_ld1lane:
 ; CHECK: ld1.s { v0 }[1], [x0], x{{[0-9]+}}
-  %tmp1 = load float* %bar
+  %tmp1 = load float, float* %bar
   %tmp2 = insertelement <2 x float> %A, float %tmp1, i32 1
-  %tmp3 = getelementptr float* %bar, i64 %inc
+  %tmp3 = getelementptr float, float* %bar, i64 %inc
   store float* %tmp3, float** %ptr
   ret <2 x float> %tmp2
 }
@@ -6156,9 +6156,9 @@ define <2 x float> @test_v2f32_post_reg_ld1lane(float* %bar, float** %ptr, i64 %
 define <2 x double> @test_v2f64_post_imm_ld1lane(double* %bar, double** %ptr, <2 x double> %A) {
 ; CHECK-LABEL: test_v2f64_post_imm_ld1lane:
 ; CHECK: ld1.d { v0 }[1], [x0], #8
-  %tmp1 = load double* %bar
+  %tmp1 = load double, double* %bar
   %tmp2 = insertelement <2 x double> %A, double %tmp1, i32 1
-  %tmp3 = getelementptr double* %bar, i64 1
+  %tmp3 = getelementptr double, double* %bar, i64 1
   store double* %tmp3, double** %ptr
   ret <2 x double> %tmp2
 }
@@ -6166,9 +6166,52 @@ define <2 x double> @test_v2f64_post_imm_ld1lane(double* %bar, double** %ptr, <2
 define <2 x double> @test_v2f64_post_reg_ld1lane(double* %bar, double** %ptr, i64 %inc, <2 x double> %A) {
 ; CHECK-LABEL: test_v2f64_post_reg_ld1lane:
 ; CHECK: ld1.d { v0 }[1], [x0], x{{[0-9]+}}
-  %tmp1 = load double* %bar
+  %tmp1 = load double, double* %bar
   %tmp2 = insertelement <2 x double> %A, double %tmp1, i32 1
-  %tmp3 = getelementptr double* %bar, i64 %inc
+  %tmp3 = getelementptr double, double* %bar, i64 %inc
   store double* %tmp3, double** %ptr
   ret <2 x double> %tmp2
-}
\ No newline at end of file
+}
+
+; Check for dependencies between the vector and the scalar load.
+define <4 x float> @test_v4f32_post_reg_ld1lane_dep_vec_on_load(float* %bar, float** %ptr, i64 %inc, <4 x float>* %dep_ptr_1, <4 x float>* %dep_ptr_2) {
+; CHECK-LABEL: test_v4f32_post_reg_ld1lane_dep_vec_on_load:
+; CHECK: BB#0:
+; CHECK-NEXT: ldr s[[LD:[0-9]+]], [x0]
+; CHECK-NEXT: movi.2d v0, #0000000000000000
+; CHECK-NEXT: str q0, [x3]
+; CHECK-NEXT: ldr q0, [x4]
+; CHECK-NEXT: ins.s v0[1], v[[LD]][0]
+; CHECK-NEXT: add [[POST:x[0-9]]], x0, x2, lsl #2
+; CHECK-NEXT: str [[POST]], [x1]
+; CHECK-NEXT: ret
+  %tmp1 = load float, float* %bar
+  store <4 x float> zeroinitializer, <4 x float>* %dep_ptr_1, align 16
+  %A = load <4 x float>, <4 x float>* %dep_ptr_2, align 16
+  %tmp2 = insertelement <4 x float> %A, float %tmp1, i32 1
+  %tmp3 = getelementptr float, float* %bar, i64 %inc
+  store float* %tmp3, float** %ptr
+  ret <4 x float> %tmp2
+}
+
+; Make sure that we test the narrow V64 code path.
+; The tests above don't, because there, 64-bit insert_vector_elt nodes will be
+; widened to 128-bit before the LD1LANEpost combine has the chance to run,
+; making it avoid narrow vector types.
+; One way to trick that combine into running early is to force the vector ops
+; legalizer to run.  We achieve that using the ctpop.
+; PR23265
+define <4 x i16> @test_v4i16_post_reg_ld1lane_forced_narrow(i16* %bar, i16** %ptr, i64 %inc, <4 x i16> %A, <2 x i32>* %d) {
+; CHECK-LABEL: test_v4i16_post_reg_ld1lane_forced_narrow:
+; CHECK: ld1.h  { v0 }[1], [x0], x{{[0-9]+}}
+  %tmp1 = load i16, i16* %bar
+  %tmp2 = insertelement <4 x i16> %A, i16 %tmp1, i32 1
+  %tmp3 = getelementptr i16, i16* %bar, i64 %inc
+  store i16* %tmp3, i16** %ptr
+  %dl =  load <2 x i32>,  <2 x i32>* %d
+  %dr = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %dl)
+  store <2 x i32> %dr, <2 x i32>* %d
+  ret <4 x i16> %tmp2
+}
+
+declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>)
diff --git a/test/CodeGen/AArch64/arm64-inline-asm.ll b/test/CodeGen/AArch64/arm64-inline-asm.ll
index 9c8bcaadc17c..802d95826ce4 100644
--- a/test/CodeGen/AArch64/arm64-inline-asm.ll
+++ b/test/CodeGen/AArch64/arm64-inline-asm.ll
@@ -125,7 +125,7 @@ define void @t9() nounwind {
 entry:
   ; CHECK-LABEL: t9:
   %data = alloca <2 x double>, align 16
-  %0 = load <2 x double>* %data, align 16
+  %0 = load <2 x double>, <2 x double>* %data, align 16
   call void asm sideeffect "mov.2d v4, $0\0A", "w,~{v4}"(<2 x double> %0) nounwind
   ; CHECK: mov.2d v4, {{v[0-9]+}}
   ret void
@@ -136,8 +136,8 @@ entry:
   ; CHECK-LABEL: t10:
   %data = alloca <2 x float>, align 8
   %a = alloca [2 x float], align 4
-  %arraydecay = getelementptr inbounds [2 x float]* %a, i32 0, i32 0
-  %0 = load <2 x float>* %data, align 8
+  %arraydecay = getelementptr inbounds [2 x float], [2 x float]* %a, i32 0, i32 0
+  %0 = load <2 x float>, <2 x float>* %data, align 8
   call void asm sideeffect "ldr ${1:q}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind
   ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}]
   call void asm sideeffect "ldr ${1:d}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind
@@ -155,10 +155,10 @@ define void @t11() nounwind {
 entry:
   ; CHECK-LABEL: t11:
   %a = alloca i32, align 4
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   call void asm sideeffect "mov ${1:x}, ${0:x}\0A", "r,i"(i32 %0, i32 0) nounwind
   ; CHECK: mov xzr, {{x[0-9]+}}
-  %1 = load i32* %a, align 4
+  %1 = load i32, i32* %a, align 4
   call void asm sideeffect "mov ${1:w}, ${0:w}\0A", "r,i"(i32 %1, i32 0) nounwind
   ; CHECK: mov wzr, {{w[0-9]+}}
   ret void
@@ -168,9 +168,9 @@ define void @t12() nounwind {
 entry:
   ; CHECK-LABEL: t12:
   %data = alloca <4 x float>, align 16
-  %0 = load <4 x float>* %data, align 16
+  %0 = load <4 x float>, <4 x float>* %data, align 16
   call void asm sideeffect "mov.2d v4, $0\0A", "x,~{v4}"(<4 x float> %0) nounwind
-  ; CHECK mov.2d v4, {{v([0-9])|(1[0-5])}}
+  ; CHECK: mov.2d v4, {{v([0-9])|(1[0-5])}}
   ret void
 }
 
diff --git a/test/CodeGen/AArch64/arm64-join-reserved.ll b/test/CodeGen/AArch64/arm64-join-reserved.ll
index e99168b5eba3..dee034483541 100644
--- a/test/CodeGen/AArch64/arm64-join-reserved.ll
+++ b/test/CodeGen/AArch64/arm64-join-reserved.ll
@@ -10,7 +10,7 @@ target triple = "arm64-apple-macosx10"
 ; CHECK: ret
 define void @g() nounwind ssp {
 entry:
-  tail call void (i32, ...)* @f(i32 0, i32 0) nounwind
+  tail call void (i32, ...) @f(i32 0, i32 0) nounwind
   ret void
 }
 
diff --git a/test/CodeGen/AArch64/arm64-large-frame.ll b/test/CodeGen/AArch64/arm64-large-frame.ll
index 5a53da693882..c4cce36bcb74 100644
--- a/test/CodeGen/AArch64/arm64-large-frame.ll
+++ b/test/CodeGen/AArch64/arm64-large-frame.ll
@@ -23,7 +23,7 @@ define void @test_bigframe() {
 ; CHECK: add {{x[0-9]+}}, [[TMP1]], #3344
   store volatile i8* %var1, i8** @addr
 
-  %var1plus2 = getelementptr i8* %var1, i32 2
+  %var1plus2 = getelementptr i8, i8* %var1, i32 2
   store volatile i8* %var1plus2, i8** @addr
 
 ; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12
@@ -31,12 +31,12 @@ define void @test_bigframe() {
 ; CHECK: add {{x[0-9]+}}, [[TMP1]], #3328
   store volatile i8* %var2, i8** @addr
 
-  %var2plus2 = getelementptr i8* %var2, i32 2
+  %var2plus2 = getelementptr i8, i8* %var2, i32 2
   store volatile i8* %var2plus2, i8** @addr
 
   store volatile i8* %var3, i8** @addr
 
-  %var3plus2 = getelementptr i8* %var3, i32 2
+  %var3plus2 = getelementptr i8, i8* %var3, i32 2
   store volatile i8* %var3plus2, i8** @addr
 
 ; CHECK: add sp, sp, #4095, lsl #12
diff --git a/test/CodeGen/AArch64/arm64-ld1.ll b/test/CodeGen/AArch64/arm64-ld1.ll
index 72d808ccc347..a83a2703addc 100644
--- a/test/CodeGen/AArch64/arm64-ld1.ll
+++ b/test/CodeGen/AArch64/arm64-ld1.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -verify-machineinstrs -asm-verbose=false | FileCheck %s
 
 %struct.__neon_int8x8x2_t = type { <8 x i8>,  <8 x i8> }
 %struct.__neon_int8x8x3_t = type { <8 x i8>,  <8 x i8>,  <8 x i8> }
@@ -8,8 +8,8 @@ define %struct.__neon_int8x8x2_t @ld2_8b(i8* %A) nounwind {
 ; CHECK-LABEL: ld2_8b
 ; Make sure we are loading into the results defined by the ABI (i.e., v0, v1)
 ; and from the argument of the function also defined by ABI (i.e., x0)
-; CHECK ld2.8b { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld2.8b { v0, v1 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int8x8x2_t @llvm.aarch64.neon.ld2.v8i8.p0i8(i8* %A)
 	ret %struct.__neon_int8x8x2_t  %tmp2
 }
@@ -17,8 +17,8 @@ define %struct.__neon_int8x8x2_t @ld2_8b(i8* %A) nounwind {
 define %struct.__neon_int8x8x3_t @ld3_8b(i8* %A) nounwind {
 ; CHECK-LABEL: ld3_8b
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld3.8b { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld3.8b { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int8x8x3_t @llvm.aarch64.neon.ld3.v8i8.p0i8(i8* %A)
 	ret %struct.__neon_int8x8x3_t  %tmp2
 }
@@ -26,8 +26,8 @@ define %struct.__neon_int8x8x3_t @ld3_8b(i8* %A) nounwind {
 define %struct.__neon_int8x8x4_t @ld4_8b(i8* %A) nounwind {
 ; CHECK-LABEL: ld4_8b
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld4.8b { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld4.8b { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int8x8x4_t @llvm.aarch64.neon.ld4.v8i8.p0i8(i8* %A)
 	ret %struct.__neon_int8x8x4_t  %tmp2
 }
@@ -43,8 +43,8 @@ declare %struct.__neon_int8x8x4_t @llvm.aarch64.neon.ld4.v8i8.p0i8(i8*) nounwind
 define %struct.__neon_int8x16x2_t @ld2_16b(i8* %A) nounwind {
 ; CHECK-LABEL: ld2_16b
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld2.16b { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld2.16b { v0, v1 }, [x0]
+; CHECK-NEXT: ret
   %tmp2 = call %struct.__neon_int8x16x2_t @llvm.aarch64.neon.ld2.v16i8.p0i8(i8* %A)
   ret %struct.__neon_int8x16x2_t  %tmp2
 }
@@ -52,8 +52,8 @@ define %struct.__neon_int8x16x2_t @ld2_16b(i8* %A) nounwind {
 define %struct.__neon_int8x16x3_t @ld3_16b(i8* %A) nounwind {
 ; CHECK-LABEL: ld3_16b
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld3.16b { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld3.16b { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
   %tmp2 = call %struct.__neon_int8x16x3_t @llvm.aarch64.neon.ld3.v16i8.p0i8(i8* %A)
   ret %struct.__neon_int8x16x3_t  %tmp2
 }
@@ -61,8 +61,8 @@ define %struct.__neon_int8x16x3_t @ld3_16b(i8* %A) nounwind {
 define %struct.__neon_int8x16x4_t @ld4_16b(i8* %A) nounwind {
 ; CHECK-LABEL: ld4_16b
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld4.16b { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld4.16b { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
   %tmp2 = call %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4.v16i8.p0i8(i8* %A)
   ret %struct.__neon_int8x16x4_t  %tmp2
 }
@@ -78,8 +78,8 @@ declare %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4.v16i8.p0i8(i8*) nounwi
 define %struct.__neon_int16x4x2_t @ld2_4h(i16* %A) nounwind {
 ; CHECK-LABEL: ld2_4h
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld2.4h { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld2.4h { v0, v1 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int16x4x2_t @llvm.aarch64.neon.ld2.v4i16.p0i16(i16* %A)
 	ret %struct.__neon_int16x4x2_t  %tmp2
 }
@@ -87,8 +87,8 @@ define %struct.__neon_int16x4x2_t @ld2_4h(i16* %A) nounwind {
 define %struct.__neon_int16x4x3_t @ld3_4h(i16* %A) nounwind {
 ; CHECK-LABEL: ld3_4h
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld3.4h { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld3.4h { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int16x4x3_t @llvm.aarch64.neon.ld3.v4i16.p0i16(i16* %A)
 	ret %struct.__neon_int16x4x3_t  %tmp2
 }
@@ -96,8 +96,8 @@ define %struct.__neon_int16x4x3_t @ld3_4h(i16* %A) nounwind {
 define %struct.__neon_int16x4x4_t @ld4_4h(i16* %A) nounwind {
 ; CHECK-LABEL: ld4_4h
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld4.4h { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld4.4h { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int16x4x4_t @llvm.aarch64.neon.ld4.v4i16.p0i16(i16* %A)
 	ret %struct.__neon_int16x4x4_t  %tmp2
 }
@@ -113,8 +113,8 @@ declare %struct.__neon_int16x4x4_t @llvm.aarch64.neon.ld4.v4i16.p0i16(i16*) noun
 define %struct.__neon_int16x8x2_t @ld2_8h(i16* %A) nounwind {
 ; CHECK-LABEL: ld2_8h
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld2.8h { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld2.8h { v0, v1 }, [x0]
+; CHECK-NEXT: ret
   %tmp2 = call %struct.__neon_int16x8x2_t @llvm.aarch64.neon.ld2.v8i16.p0i16(i16* %A)
   ret %struct.__neon_int16x8x2_t  %tmp2
 }
@@ -122,8 +122,8 @@ define %struct.__neon_int16x8x2_t @ld2_8h(i16* %A) nounwind {
 define %struct.__neon_int16x8x3_t @ld3_8h(i16* %A) nounwind {
 ; CHECK-LABEL: ld3_8h
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld3.8h { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld3.8h { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
   %tmp2 = call %struct.__neon_int16x8x3_t @llvm.aarch64.neon.ld3.v8i16.p0i16(i16* %A)
   ret %struct.__neon_int16x8x3_t %tmp2
 }
@@ -131,8 +131,8 @@ define %struct.__neon_int16x8x3_t @ld3_8h(i16* %A) nounwind {
 define %struct.__neon_int16x8x4_t @ld4_8h(i16* %A) nounwind {
 ; CHECK-LABEL: ld4_8h
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld4.8h { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld4.8h { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
   %tmp2 = call %struct.__neon_int16x8x4_t @llvm.aarch64.neon.ld4.v8i16.p0i16(i16* %A)
   ret %struct.__neon_int16x8x4_t  %tmp2
 }
@@ -148,8 +148,8 @@ declare %struct.__neon_int16x8x4_t @llvm.aarch64.neon.ld4.v8i16.p0i16(i16*) noun
 define %struct.__neon_int32x2x2_t @ld2_2s(i32* %A) nounwind {
 ; CHECK-LABEL: ld2_2s
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld2.2s { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld2.2s { v0, v1 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int32x2x2_t @llvm.aarch64.neon.ld2.v2i32.p0i32(i32* %A)
 	ret %struct.__neon_int32x2x2_t  %tmp2
 }
@@ -157,8 +157,8 @@ define %struct.__neon_int32x2x2_t @ld2_2s(i32* %A) nounwind {
 define %struct.__neon_int32x2x3_t @ld3_2s(i32* %A) nounwind {
 ; CHECK-LABEL: ld3_2s
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld3.2s { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld3.2s { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int32x2x3_t @llvm.aarch64.neon.ld3.v2i32.p0i32(i32* %A)
 	ret %struct.__neon_int32x2x3_t  %tmp2
 }
@@ -166,8 +166,8 @@ define %struct.__neon_int32x2x3_t @ld3_2s(i32* %A) nounwind {
 define %struct.__neon_int32x2x4_t @ld4_2s(i32* %A) nounwind {
 ; CHECK-LABEL: ld4_2s
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld4.2s { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld4.2s { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int32x2x4_t @llvm.aarch64.neon.ld4.v2i32.p0i32(i32* %A)
 	ret %struct.__neon_int32x2x4_t  %tmp2
 }
@@ -183,8 +183,8 @@ declare %struct.__neon_int32x2x4_t @llvm.aarch64.neon.ld4.v2i32.p0i32(i32*) noun
 define %struct.__neon_int32x4x2_t @ld2_4s(i32* %A) nounwind {
 ; CHECK-LABEL: ld2_4s
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld2.4s { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld2.4s { v0, v1 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int32x4x2_t @llvm.aarch64.neon.ld2.v4i32.p0i32(i32* %A)
 	ret %struct.__neon_int32x4x2_t  %tmp2
 }
@@ -192,8 +192,8 @@ define %struct.__neon_int32x4x2_t @ld2_4s(i32* %A) nounwind {
 define %struct.__neon_int32x4x3_t @ld3_4s(i32* %A) nounwind {
 ; CHECK-LABEL: ld3_4s
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld3.4s { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld3.4s { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int32x4x3_t @llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %A)
 	ret %struct.__neon_int32x4x3_t  %tmp2
 }
@@ -201,8 +201,8 @@ define %struct.__neon_int32x4x3_t @ld3_4s(i32* %A) nounwind {
 define %struct.__neon_int32x4x4_t @ld4_4s(i32* %A) nounwind {
 ; CHECK-LABEL: ld4_4s
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld4.4s { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld4.4s { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int32x4x4_t @llvm.aarch64.neon.ld4.v4i32.p0i32(i32* %A)
 	ret %struct.__neon_int32x4x4_t  %tmp2
 }
@@ -218,8 +218,8 @@ declare %struct.__neon_int32x4x4_t @llvm.aarch64.neon.ld4.v4i32.p0i32(i32*) noun
 define %struct.__neon_int64x2x2_t @ld2_2d(i64* %A) nounwind {
 ; CHECK-LABEL: ld2_2d
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld2.2d { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld2.2d { v0, v1 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int64x2x2_t @llvm.aarch64.neon.ld2.v2i64.p0i64(i64* %A)
 	ret %struct.__neon_int64x2x2_t  %tmp2
 }
@@ -227,8 +227,8 @@ define %struct.__neon_int64x2x2_t @ld2_2d(i64* %A) nounwind {
 define %struct.__neon_int64x2x3_t @ld3_2d(i64* %A) nounwind {
 ; CHECK-LABEL: ld3_2d
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld3.2d { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld3.2d { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int64x2x3_t @llvm.aarch64.neon.ld3.v2i64.p0i64(i64* %A)
 	ret %struct.__neon_int64x2x3_t  %tmp2
 }
@@ -236,8 +236,8 @@ define %struct.__neon_int64x2x3_t @ld3_2d(i64* %A) nounwind {
 define %struct.__neon_int64x2x4_t @ld4_2d(i64* %A) nounwind {
 ; CHECK-LABEL: ld4_2d
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld4.2d { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld4.2d { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int64x2x4_t @llvm.aarch64.neon.ld4.v2i64.p0i64(i64* %A)
 	ret %struct.__neon_int64x2x4_t  %tmp2
 }
@@ -254,8 +254,8 @@ declare %struct.__neon_int64x2x4_t @llvm.aarch64.neon.ld4.v2i64.p0i64(i64*) noun
 define %struct.__neon_int64x1x2_t @ld2_1di64(i64* %A) nounwind {
 ; CHECK-LABEL: ld2_1di64
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld1.1d { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld1.1d { v0, v1 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int64x1x2_t @llvm.aarch64.neon.ld2.v1i64.p0i64(i64* %A)
 	ret %struct.__neon_int64x1x2_t  %tmp2
 }
@@ -263,8 +263,8 @@ define %struct.__neon_int64x1x2_t @ld2_1di64(i64* %A) nounwind {
 define %struct.__neon_int64x1x3_t @ld3_1di64(i64* %A) nounwind {
 ; CHECK-LABEL: ld3_1di64
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld1.1d { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld1.1d { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int64x1x3_t @llvm.aarch64.neon.ld3.v1i64.p0i64(i64* %A)
 	ret %struct.__neon_int64x1x3_t  %tmp2
 }
@@ -272,8 +272,8 @@ define %struct.__neon_int64x1x3_t @ld3_1di64(i64* %A) nounwind {
 define %struct.__neon_int64x1x4_t @ld4_1di64(i64* %A) nounwind {
 ; CHECK-LABEL: ld4_1di64
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld1.1d { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld1.1d { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int64x1x4_t @llvm.aarch64.neon.ld4.v1i64.p0i64(i64* %A)
 	ret %struct.__neon_int64x1x4_t  %tmp2
 }
@@ -291,8 +291,8 @@ declare %struct.__neon_int64x1x4_t @llvm.aarch64.neon.ld4.v1i64.p0i64(i64*) noun
 define %struct.__neon_float64x1x2_t @ld2_1df64(double* %A) nounwind {
 ; CHECK-LABEL: ld2_1df64
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld1.1d { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld1.1d { v0, v1 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A)
 	ret %struct.__neon_float64x1x2_t  %tmp2
 }
@@ -300,8 +300,8 @@ define %struct.__neon_float64x1x2_t @ld2_1df64(double* %A) nounwind {
 define %struct.__neon_float64x1x3_t @ld3_1df64(double* %A) nounwind {
 ; CHECK-LABEL: ld3_1df64
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld1.1d { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld1.1d { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld3.v1f64.p0f64(double* %A)
 	ret %struct.__neon_float64x1x3_t  %tmp2
 }
@@ -309,8 +309,8 @@ define %struct.__neon_float64x1x3_t @ld3_1df64(double* %A) nounwind {
 define %struct.__neon_float64x1x4_t @ld4_1df64(double* %A) nounwind {
 ; CHECK-LABEL: ld4_1df64
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld1.1d { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld1.1d { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_float64x1x4_t @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A)
 	ret %struct.__neon_float64x1x4_t  %tmp2
 }
@@ -323,8 +323,8 @@ declare %struct.__neon_float64x1x4_t @llvm.aarch64.neon.ld4.v1f64.p0f64(double*)
 define %struct.__neon_int8x16x2_t @ld2lane_16b(<16 x i8> %L1, <16 x i8> %L2, i8* %A) nounwind {
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld2lane_16b
-; CHECK ld2.b { v0, v1 }[1], [x0]
-; CHECK-NEXT ret
+; CHECK: ld2.b { v0, v1 }[1], [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int8x16x2_t @llvm.aarch64.neon.ld2lane.v16i8.p0i8(<16 x i8> %L1, <16 x i8> %L2, i64 1, i8* %A)
 	ret %struct.__neon_int8x16x2_t  %tmp2
 }
@@ -332,8 +332,8 @@ define %struct.__neon_int8x16x2_t @ld2lane_16b(<16 x i8> %L1, <16 x i8> %L2, i8*
 define %struct.__neon_int8x16x3_t @ld3lane_16b(<16 x i8> %L1, <16 x i8> %L2, <16 x i8> %L3, i8* %A) nounwind {
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld3lane_16b
-; CHECK ld3.b { v0, v1, v2 }[1], [x0]
-; CHECK-NEXT ret
+; CHECK: ld3.b { v0, v1, v2 }[1], [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int8x16x3_t @llvm.aarch64.neon.ld3lane.v16i8.p0i8(<16 x i8> %L1, <16 x i8> %L2, <16 x i8> %L3, i64 1, i8* %A)
 	ret %struct.__neon_int8x16x3_t  %tmp2
 }
@@ -341,8 +341,8 @@ define %struct.__neon_int8x16x3_t @ld3lane_16b(<16 x i8> %L1, <16 x i8> %L2, <16
 define %struct.__neon_int8x16x4_t @ld4lane_16b(<16 x i8> %L1, <16 x i8> %L2, <16 x i8> %L3, <16 x i8> %L4, i8* %A) nounwind {
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld4lane_16b
-; CHECK ld4.b { v0, v1, v2, v3 }[1], [x0]
-; CHECK-NEXT ret
+; CHECK: ld4.b { v0, v1, v2, v3 }[1], [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4lane.v16i8.p0i8(<16 x i8> %L1, <16 x i8> %L2, <16 x i8> %L3, <16 x i8> %L4, i64 1, i8* %A)
 	ret %struct.__neon_int8x16x4_t  %tmp2
 }
@@ -354,8 +354,8 @@ declare %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4lane.v16i8.p0i8(<16 x i
 define %struct.__neon_int16x8x2_t @ld2lane_8h(<8 x i16> %L1, <8 x i16> %L2, i16* %A) nounwind {
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld2lane_8h
-; CHECK ld2.h { v0, v1 }[1], [x0]
-; CHECK-NEXT ret
+; CHECK: ld2.h { v0, v1 }[1], [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int16x8x2_t @llvm.aarch64.neon.ld2lane.v8i16.p0i16(<8 x i16> %L1, <8 x i16> %L2, i64 1, i16* %A)
 	ret %struct.__neon_int16x8x2_t  %tmp2
 }
@@ -363,8 +363,8 @@ define %struct.__neon_int16x8x2_t @ld2lane_8h(<8 x i16> %L1, <8 x i16> %L2, i16*
 define %struct.__neon_int16x8x3_t @ld3lane_8h(<8 x i16> %L1, <8 x i16> %L2, <8 x i16> %L3, i16* %A) nounwind {
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld3lane_8h
-; CHECK ld3.h { v0, v1, v3 }[1], [x0]
-; CHECK-NEXT ret
+; CHECK: ld3.h { v0, v1, v2 }[1], [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int16x8x3_t @llvm.aarch64.neon.ld3lane.v8i16.p0i16(<8 x i16> %L1, <8 x i16> %L2, <8 x i16> %L3, i64 1, i16* %A)
 	ret %struct.__neon_int16x8x3_t  %tmp2
 }
@@ -372,8 +372,8 @@ define %struct.__neon_int16x8x3_t @ld3lane_8h(<8 x i16> %L1, <8 x i16> %L2, <8 x
 define %struct.__neon_int16x8x4_t @ld4lane_8h(<8 x i16> %L1, <8 x i16> %L2, <8 x i16> %L3, <8 x i16> %L4, i16* %A) nounwind {
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld4lane_8h
-; CHECK ld4.h { v0, v1, v2, v3 }[1], [x0]
-; CHECK-NEXT ret
+; CHECK: ld4.h { v0, v1, v2, v3 }[1], [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int16x8x4_t @llvm.aarch64.neon.ld4lane.v8i16.p0i16(<8 x i16> %L1, <8 x i16> %L2, <8 x i16> %L3, <8 x i16> %L4, i64 1, i16* %A)
 	ret %struct.__neon_int16x8x4_t  %tmp2
 }
@@ -385,8 +385,8 @@ declare %struct.__neon_int16x8x4_t @llvm.aarch64.neon.ld4lane.v8i16.p0i16(<8 x i
 define %struct.__neon_int32x4x2_t @ld2lane_4s(<4 x i32> %L1, <4 x i32> %L2, i32* %A) nounwind {
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld2lane_4s
-; CHECK ld2.s { v0, v1 }[1], [x0]
-; CHECK-NEXT ret
+; CHECK: ld2.s { v0, v1 }[1], [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int32x4x2_t @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32> %L1, <4 x i32> %L2, i64 1, i32* %A)
 	ret %struct.__neon_int32x4x2_t  %tmp2
 }
@@ -394,8 +394,8 @@ define %struct.__neon_int32x4x2_t @ld2lane_4s(<4 x i32> %L1, <4 x i32> %L2, i32*
 define %struct.__neon_int32x4x3_t @ld3lane_4s(<4 x i32> %L1, <4 x i32> %L2, <4 x i32> %L3, i32* %A) nounwind {
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld3lane_4s
-; CHECK ld3.s { v0, v1, v2 }[1], [x0]
-; CHECK-NEXT ret
+; CHECK: ld3.s { v0, v1, v2 }[1], [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int32x4x3_t @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x i32> %L1, <4 x i32> %L2, <4 x i32> %L3, i64 1, i32* %A)
 	ret %struct.__neon_int32x4x3_t  %tmp2
 }
@@ -403,8 +403,8 @@ define %struct.__neon_int32x4x3_t @ld3lane_4s(<4 x i32> %L1, <4 x i32> %L2, <4 x
 define %struct.__neon_int32x4x4_t @ld4lane_4s(<4 x i32> %L1, <4 x i32> %L2, <4 x i32> %L3, <4 x i32> %L4, i32* %A) nounwind {
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld4lane_4s
-; CHECK ld4.s { v0, v1, v2, v3 }[1], [x0]
-; CHECK-NEXT ret
+; CHECK: ld4.s { v0, v1, v2, v3 }[1], [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int32x4x4_t @llvm.aarch64.neon.ld4lane.v4i32.p0i32(<4 x i32> %L1, <4 x i32> %L2, <4 x i32> %L3, <4 x i32> %L4, i64 1, i32* %A)
 	ret %struct.__neon_int32x4x4_t  %tmp2
 }
@@ -416,8 +416,8 @@ declare %struct.__neon_int32x4x4_t @llvm.aarch64.neon.ld4lane.v4i32.p0i32(<4 x i
 define %struct.__neon_int64x2x2_t @ld2lane_2d(<2 x i64> %L1, <2 x i64> %L2, i64* %A) nounwind {
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld2lane_2d
-; CHECK ld2.d { v0, v1 }[1], [x0]
-; CHECK-NEXT ret
+; CHECK: ld2.d { v0, v1 }[1], [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int64x2x2_t @llvm.aarch64.neon.ld2lane.v2i64.p0i64(<2 x i64> %L1, <2 x i64> %L2, i64 1, i64* %A)
 	ret %struct.__neon_int64x2x2_t  %tmp2
 }
@@ -425,8 +425,8 @@ define %struct.__neon_int64x2x2_t @ld2lane_2d(<2 x i64> %L1, <2 x i64> %L2, i64*
 define %struct.__neon_int64x2x3_t @ld3lane_2d(<2 x i64> %L1, <2 x i64> %L2, <2 x i64> %L3, i64* %A) nounwind {
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld3lane_2d
-; CHECK ld3.d { v0, v1, v3 }[1], [x0]
-; CHECK-NEXT ret
+; CHECK: ld3.d { v0, v1, v2 }[1], [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int64x2x3_t @llvm.aarch64.neon.ld3lane.v2i64.p0i64(<2 x i64> %L1, <2 x i64> %L2, <2 x i64> %L3, i64 1, i64* %A)
 	ret %struct.__neon_int64x2x3_t  %tmp2
 }
@@ -434,8 +434,8 @@ define %struct.__neon_int64x2x3_t @ld3lane_2d(<2 x i64> %L1, <2 x i64> %L2, <2 x
 define %struct.__neon_int64x2x4_t @ld4lane_2d(<2 x i64> %L1, <2 x i64> %L2, <2 x i64> %L3, <2 x i64> %L4, i64* %A) nounwind {
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld4lane_2d
-; CHECK ld4.d { v0, v1, v2, v3 }[1], [x0]
-; CHECK-NEXT ret
+; CHECK: ld4.d { v0, v1, v2, v3 }[1], [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int64x2x4_t @llvm.aarch64.neon.ld4lane.v2i64.p0i64(<2 x i64> %L1, <2 x i64> %L2, <2 x i64> %L3, <2 x i64> %L4, i64 1, i64* %A)
 	ret %struct.__neon_int64x2x4_t  %tmp2
 }
@@ -448,8 +448,8 @@ define <8 x i8> @ld1r_8b(i8* %bar) {
 ; CHECK: ld1r_8b
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1r.8b { v0 }, [x0]
-; CHECK-NEXT ret
-  %tmp1 = load i8* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load i8, i8* %bar
   %tmp2 = insertelement <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
   %tmp3 = insertelement <8 x i8> %tmp2, i8 %tmp1, i32 1
   %tmp4 = insertelement <8 x i8> %tmp3, i8 %tmp1, i32 2
@@ -465,8 +465,8 @@ define <16 x i8> @ld1r_16b(i8* %bar) {
 ; CHECK: ld1r_16b
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1r.16b { v0 }, [x0]
-; CHECK-NEXT ret
-  %tmp1 = load i8* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load i8, i8* %bar
   %tmp2 = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
   %tmp3 = insertelement <16 x i8> %tmp2, i8 %tmp1, i32 1
   %tmp4 = insertelement <16 x i8> %tmp3, i8 %tmp1, i32 2
@@ -490,8 +490,8 @@ define <4 x i16> @ld1r_4h(i16* %bar) {
 ; CHECK: ld1r_4h
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1r.4h { v0 }, [x0]
-; CHECK-NEXT ret
-  %tmp1 = load i16* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load i16, i16* %bar
   %tmp2 = insertelement <4 x i16> <i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0
   %tmp3 = insertelement <4 x i16> %tmp2, i16 %tmp1, i32 1
   %tmp4 = insertelement <4 x i16> %tmp3, i16 %tmp1, i32 2
@@ -503,8 +503,8 @@ define <8 x i16> @ld1r_8h(i16* %bar) {
 ; CHECK: ld1r_8h
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1r.8h { v0 }, [x0]
-; CHECK-NEXT ret
-  %tmp1 = load i16* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load i16, i16* %bar
   %tmp2 = insertelement <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0
   %tmp3 = insertelement <8 x i16> %tmp2, i16 %tmp1, i32 1
   %tmp4 = insertelement <8 x i16> %tmp3, i16 %tmp1, i32 2
@@ -520,8 +520,8 @@ define <2 x i32> @ld1r_2s(i32* %bar) {
 ; CHECK: ld1r_2s
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1r.2s { v0 }, [x0]
-; CHECK-NEXT ret
-  %tmp1 = load i32* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load i32, i32* %bar
   %tmp2 = insertelement <2 x i32> <i32 undef, i32 undef>, i32 %tmp1, i32 0
   %tmp3 = insertelement <2 x i32> %tmp2, i32 %tmp1, i32 1
   ret <2 x i32> %tmp3
@@ -531,8 +531,8 @@ define <4 x i32> @ld1r_4s(i32* %bar) {
 ; CHECK: ld1r_4s
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1r.4s { v0 }, [x0]
-; CHECK-NEXT ret
-  %tmp1 = load i32* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load i32, i32* %bar
   %tmp2 = insertelement <4 x i32> <i32 undef, i32 undef, i32 undef, i32 undef>, i32 %tmp1, i32 0
   %tmp3 = insertelement <4 x i32> %tmp2, i32 %tmp1, i32 1
   %tmp4 = insertelement <4 x i32> %tmp3, i32 %tmp1, i32 2
@@ -544,8 +544,8 @@ define <2 x i64> @ld1r_2d(i64* %bar) {
 ; CHECK: ld1r_2d
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1r.2d { v0 }, [x0]
-; CHECK-NEXT ret
-  %tmp1 = load i64* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load i64, i64* %bar
   %tmp2 = insertelement <2 x i64> <i64 undef, i64 undef>, i64 %tmp1, i32 0
   %tmp3 = insertelement <2 x i64> %tmp2, i64 %tmp1, i32 1
   ret <2 x i64> %tmp3
@@ -554,8 +554,8 @@ define <2 x i64> @ld1r_2d(i64* %bar) {
 define %struct.__neon_int8x8x2_t @ld2r_8b(i8* %A) nounwind {
 ; CHECK: ld2r_8b
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.8b { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld2r.8b { v0, v1 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int8x8x2_t @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A)
 	ret %struct.__neon_int8x8x2_t  %tmp2
 }
@@ -563,8 +563,8 @@ define %struct.__neon_int8x8x2_t @ld2r_8b(i8* %A) nounwind {
 define %struct.__neon_int8x8x3_t @ld3r_8b(i8* %A) nounwind {
 ; CHECK: ld3r_8b
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.8b { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld3r.8b { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int8x8x3_t @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A)
 	ret %struct.__neon_int8x8x3_t  %tmp2
 }
@@ -572,8 +572,8 @@ define %struct.__neon_int8x8x3_t @ld3r_8b(i8* %A) nounwind {
 define %struct.__neon_int8x8x4_t @ld4r_8b(i8* %A) nounwind {
 ; CHECK: ld4r_8b
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.8b { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld4r.8b { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int8x8x4_t @llvm.aarch64.neon.ld4r.v8i8.p0i8(i8* %A)
 	ret %struct.__neon_int8x8x4_t  %tmp2
 }
@@ -585,8 +585,8 @@ declare %struct.__neon_int8x8x4_t @llvm.aarch64.neon.ld4r.v8i8.p0i8(i8*) nounwin
 define %struct.__neon_int8x16x2_t @ld2r_16b(i8* %A) nounwind {
 ; CHECK: ld2r_16b
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.16b { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld2r.16b { v0, v1 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int8x16x2_t @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A)
 	ret %struct.__neon_int8x16x2_t  %tmp2
 }
@@ -594,8 +594,8 @@ define %struct.__neon_int8x16x2_t @ld2r_16b(i8* %A) nounwind {
 define %struct.__neon_int8x16x3_t @ld3r_16b(i8* %A) nounwind {
 ; CHECK: ld3r_16b
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.16b { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld3r.16b { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int8x16x3_t @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A)
 	ret %struct.__neon_int8x16x3_t  %tmp2
 }
@@ -603,8 +603,8 @@ define %struct.__neon_int8x16x3_t @ld3r_16b(i8* %A) nounwind {
 define %struct.__neon_int8x16x4_t @ld4r_16b(i8* %A) nounwind {
 ; CHECK: ld4r_16b
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.16b { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld4r.16b { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4r.v16i8.p0i8(i8* %A)
 	ret %struct.__neon_int8x16x4_t  %tmp2
 }
@@ -616,8 +616,8 @@ declare %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4r.v16i8.p0i8(i8*) nounw
 define %struct.__neon_int16x4x2_t @ld2r_4h(i16* %A) nounwind {
 ; CHECK: ld2r_4h
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.4h { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld2r.4h { v0, v1 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int16x4x2_t @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16* %A)
 	ret %struct.__neon_int16x4x2_t  %tmp2
 }
@@ -625,8 +625,8 @@ define %struct.__neon_int16x4x2_t @ld2r_4h(i16* %A) nounwind {
 define %struct.__neon_int16x4x3_t @ld3r_4h(i16* %A) nounwind {
 ; CHECK: ld3r_4h
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.4h { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld3r.4h { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int16x4x3_t @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16* %A)
 	ret %struct.__neon_int16x4x3_t  %tmp2
 }
@@ -634,8 +634,8 @@ define %struct.__neon_int16x4x3_t @ld3r_4h(i16* %A) nounwind {
 define %struct.__neon_int16x4x4_t @ld4r_4h(i16* %A) nounwind {
 ; CHECK: ld4r_4h
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.4h { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld4r.4h { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int16x4x4_t @llvm.aarch64.neon.ld4r.v4i16.p0i16(i16* %A)
 	ret %struct.__neon_int16x4x4_t  %tmp2
 }
@@ -647,8 +647,8 @@ declare %struct.__neon_int16x4x4_t @llvm.aarch64.neon.ld4r.v4i16.p0i16(i16*) nou
 define %struct.__neon_int16x8x2_t @ld2r_8h(i16* %A) nounwind {
 ; CHECK: ld2r_8h
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.8h { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld2r.8h { v0, v1 }, [x0]
+; CHECK-NEXT: ret
   %tmp2 = call %struct.__neon_int16x8x2_t @llvm.aarch64.neon.ld2r.v8i16.p0i16(i16* %A)
   ret %struct.__neon_int16x8x2_t  %tmp2
 }
@@ -656,8 +656,8 @@ define %struct.__neon_int16x8x2_t @ld2r_8h(i16* %A) nounwind {
 define %struct.__neon_int16x8x3_t @ld3r_8h(i16* %A) nounwind {
 ; CHECK: ld3r_8h
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.8h { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld3r.8h { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
   %tmp2 = call %struct.__neon_int16x8x3_t @llvm.aarch64.neon.ld3r.v8i16.p0i16(i16* %A)
   ret %struct.__neon_int16x8x3_t  %tmp2
 }
@@ -665,8 +665,8 @@ define %struct.__neon_int16x8x3_t @ld3r_8h(i16* %A) nounwind {
 define %struct.__neon_int16x8x4_t @ld4r_8h(i16* %A) nounwind {
 ; CHECK: ld4r_8h
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.8h { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld4r.8h { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
   %tmp2 = call %struct.__neon_int16x8x4_t @llvm.aarch64.neon.ld4r.v8i16.p0i16(i16* %A)
   ret %struct.__neon_int16x8x4_t  %tmp2
 }
@@ -678,8 +678,8 @@ declare %struct.__neon_int16x8x4_t @llvm.aarch64.neon.ld4r.v8i16.p0i16(i16*) nou
 define %struct.__neon_int32x2x2_t @ld2r_2s(i32* %A) nounwind {
 ; CHECK: ld2r_2s
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.2s { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld2r.2s { v0, v1 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int32x2x2_t @llvm.aarch64.neon.ld2r.v2i32.p0i32(i32* %A)
 	ret %struct.__neon_int32x2x2_t  %tmp2
 }
@@ -687,8 +687,8 @@ define %struct.__neon_int32x2x2_t @ld2r_2s(i32* %A) nounwind {
 define %struct.__neon_int32x2x3_t @ld3r_2s(i32* %A) nounwind {
 ; CHECK: ld3r_2s
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.2s { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld3r.2s { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int32x2x3_t @llvm.aarch64.neon.ld3r.v2i32.p0i32(i32* %A)
 	ret %struct.__neon_int32x2x3_t  %tmp2
 }
@@ -696,8 +696,8 @@ define %struct.__neon_int32x2x3_t @ld3r_2s(i32* %A) nounwind {
 define %struct.__neon_int32x2x4_t @ld4r_2s(i32* %A) nounwind {
 ; CHECK: ld4r_2s
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.2s { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld4r.2s { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int32x2x4_t @llvm.aarch64.neon.ld4r.v2i32.p0i32(i32* %A)
 	ret %struct.__neon_int32x2x4_t  %tmp2
 }
@@ -709,8 +709,8 @@ declare %struct.__neon_int32x2x4_t @llvm.aarch64.neon.ld4r.v2i32.p0i32(i32*) nou
 define %struct.__neon_int32x4x2_t @ld2r_4s(i32* %A) nounwind {
 ; CHECK: ld2r_4s
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.4s { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld2r.4s { v0, v1 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int32x4x2_t @llvm.aarch64.neon.ld2r.v4i32.p0i32(i32* %A)
 	ret %struct.__neon_int32x4x2_t  %tmp2
 }
@@ -718,8 +718,8 @@ define %struct.__neon_int32x4x2_t @ld2r_4s(i32* %A) nounwind {
 define %struct.__neon_int32x4x3_t @ld3r_4s(i32* %A) nounwind {
 ; CHECK: ld3r_4s
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.4s { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld3r.4s { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int32x4x3_t @llvm.aarch64.neon.ld3r.v4i32.p0i32(i32* %A)
 	ret %struct.__neon_int32x4x3_t  %tmp2
 }
@@ -727,8 +727,8 @@ define %struct.__neon_int32x4x3_t @ld3r_4s(i32* %A) nounwind {
 define %struct.__neon_int32x4x4_t @ld4r_4s(i32* %A) nounwind {
 ; CHECK: ld4r_4s
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.4s { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld4r.4s { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int32x4x4_t @llvm.aarch64.neon.ld4r.v4i32.p0i32(i32* %A)
 	ret %struct.__neon_int32x4x4_t  %tmp2
 }
@@ -740,8 +740,8 @@ declare %struct.__neon_int32x4x4_t @llvm.aarch64.neon.ld4r.v4i32.p0i32(i32*) nou
 define %struct.__neon_int64x1x2_t @ld2r_1d(i64* %A) nounwind {
 ; CHECK: ld2r_1d
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.1d { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld2r.1d { v0, v1 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int64x1x2_t @llvm.aarch64.neon.ld2r.v1i64.p0i64(i64* %A)
 	ret %struct.__neon_int64x1x2_t  %tmp2
 }
@@ -749,8 +749,8 @@ define %struct.__neon_int64x1x2_t @ld2r_1d(i64* %A) nounwind {
 define %struct.__neon_int64x1x3_t @ld3r_1d(i64* %A) nounwind {
 ; CHECK: ld3r_1d
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.1d { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld3r.1d { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int64x1x3_t @llvm.aarch64.neon.ld3r.v1i64.p0i64(i64* %A)
 	ret %struct.__neon_int64x1x3_t  %tmp2
 }
@@ -758,8 +758,8 @@ define %struct.__neon_int64x1x3_t @ld3r_1d(i64* %A) nounwind {
 define %struct.__neon_int64x1x4_t @ld4r_1d(i64* %A) nounwind {
 ; CHECK: ld4r_1d
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.1d { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld4r.1d { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int64x1x4_t @llvm.aarch64.neon.ld4r.v1i64.p0i64(i64* %A)
 	ret %struct.__neon_int64x1x4_t  %tmp2
 }
@@ -771,8 +771,8 @@ declare %struct.__neon_int64x1x4_t @llvm.aarch64.neon.ld4r.v1i64.p0i64(i64*) nou
 define %struct.__neon_int64x2x2_t @ld2r_2d(i64* %A) nounwind {
 ; CHECK: ld2r_2d
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.2d { v0, v1 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld2r.2d { v0, v1 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int64x2x2_t @llvm.aarch64.neon.ld2r.v2i64.p0i64(i64* %A)
 	ret %struct.__neon_int64x2x2_t  %tmp2
 }
@@ -780,8 +780,8 @@ define %struct.__neon_int64x2x2_t @ld2r_2d(i64* %A) nounwind {
 define %struct.__neon_int64x2x3_t @ld3r_2d(i64* %A) nounwind {
 ; CHECK: ld3r_2d
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.2d { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld3r.2d { v0, v1, v2 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int64x2x3_t @llvm.aarch64.neon.ld3r.v2i64.p0i64(i64* %A)
 	ret %struct.__neon_int64x2x3_t  %tmp2
 }
@@ -789,8 +789,8 @@ define %struct.__neon_int64x2x3_t @ld3r_2d(i64* %A) nounwind {
 define %struct.__neon_int64x2x4_t @ld4r_2d(i64* %A) nounwind {
 ; CHECK: ld4r_2d
 ; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.2d { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
+; CHECK: ld4r.2d { v0, v1, v2, v3 }, [x0]
+; CHECK-NEXT: ret
 	%tmp2 = call %struct.__neon_int64x2x4_t @llvm.aarch64.neon.ld4r.v2i64.p0i64(i64* %A)
 	ret %struct.__neon_int64x2x4_t  %tmp2
 }
@@ -803,8 +803,8 @@ define <16 x i8> @ld1_16b(<16 x i8> %V, i8* %bar) {
 ; CHECK-LABEL: ld1_16b
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1.b { v0 }[0], [x0]
-; CHECK-NEXT ret
-  %tmp1 = load i8* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load i8, i8* %bar
   %tmp2 = insertelement <16 x i8> %V, i8 %tmp1, i32 0
   ret <16 x i8> %tmp2
 }
@@ -813,8 +813,8 @@ define <8 x i16> @ld1_8h(<8 x i16> %V, i16* %bar) {
 ; CHECK-LABEL: ld1_8h
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1.h { v0 }[0], [x0]
-; CHECK-NEXT ret
-  %tmp1 = load i16* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load i16, i16* %bar
   %tmp2 = insertelement <8 x i16> %V, i16 %tmp1, i32 0
   ret <8 x i16> %tmp2
 }
@@ -823,8 +823,8 @@ define <4 x i32> @ld1_4s(<4 x i32> %V, i32* %bar) {
 ; CHECK-LABEL: ld1_4s
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1.s { v0 }[0], [x0]
-; CHECK-NEXT ret
-  %tmp1 = load i32* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load i32, i32* %bar
   %tmp2 = insertelement <4 x i32> %V, i32 %tmp1, i32 0
   ret <4 x i32> %tmp2
 }
@@ -833,8 +833,8 @@ define <4 x float> @ld1_4s_float(<4 x float> %V, float* %bar) {
 ; CHECK-LABEL: ld1_4s_float:
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1.s { v0 }[0], [x0]
-; CHECK-NEXT ret
-  %tmp1 = load float* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load float, float* %bar
   %tmp2 = insertelement <4 x float> %V, float %tmp1, i32 0
   ret <4 x float> %tmp2
 }
@@ -843,8 +843,8 @@ define <2 x i64> @ld1_2d(<2 x i64> %V, i64* %bar) {
 ; CHECK-LABEL: ld1_2d
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1.d { v0 }[0], [x0]
-; CHECK-NEXT ret
-  %tmp1 = load i64* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load i64, i64* %bar
   %tmp2 = insertelement <2 x i64> %V, i64 %tmp1, i32 0
   ret <2 x i64> %tmp2
 }
@@ -853,8 +853,8 @@ define <2 x double> @ld1_2d_double(<2 x double> %V, double* %bar) {
 ; CHECK-LABEL: ld1_2d_double:
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1.d { v0 }[0], [x0]
-; CHECK-NEXT ret
-  %tmp1 = load double* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load double, double* %bar
   %tmp2 = insertelement <2 x double> %V, double %tmp1, i32 0
   ret <2 x double> %tmp2
 }
@@ -864,7 +864,7 @@ define <1 x i64> @ld1_1d(<1 x i64>* %p) {
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ldr [[REG:d[0-9]+]], [x0]
 ; CHECK-NEXT: ret
-  %tmp = load <1 x i64>* %p, align 8
+  %tmp = load <1 x i64>, <1 x i64>* %p, align 8
   ret <1 x i64> %tmp
 }
 
@@ -872,8 +872,8 @@ define <8 x i8> @ld1_8b(<8 x i8> %V, i8* %bar) {
 ; CHECK-LABEL: ld1_8b
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1.b { v0 }[0], [x0]
-; CHECK-NEXT ret
-  %tmp1 = load i8* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load i8, i8* %bar
   %tmp2 = insertelement <8 x i8> %V, i8 %tmp1, i32 0
   ret <8 x i8> %tmp2
 }
@@ -882,8 +882,8 @@ define <4 x i16> @ld1_4h(<4 x i16> %V, i16* %bar) {
 ; CHECK-LABEL: ld1_4h
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1.h { v0 }[0], [x0]
-; CHECK-NEXT ret
-  %tmp1 = load i16* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load i16, i16* %bar
   %tmp2 = insertelement <4 x i16> %V, i16 %tmp1, i32 0
   ret <4 x i16> %tmp2
 }
@@ -892,8 +892,8 @@ define <2 x i32> @ld1_2s(<2 x i32> %V, i32* %bar) {
 ; CHECK-LABEL: ld1_2s:
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1.s { v0 }[0], [x0]
-; CHECK-NEXT ret
-  %tmp1 = load i32* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load i32, i32* %bar
   %tmp2 = insertelement <2 x i32> %V, i32 %tmp1, i32 0
   ret <2 x i32> %tmp2
 }
@@ -902,8 +902,8 @@ define <2 x float> @ld1_2s_float(<2 x float> %V, float* %bar) {
 ; CHECK-LABEL: ld1_2s_float:
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1.s { v0 }[0], [x0]
-; CHECK-NEXT ret
-  %tmp1 = load float* %bar
+; CHECK-NEXT: ret
+  %tmp1 = load float, float* %bar
   %tmp2 = insertelement <2 x float> %V, float %tmp1, i32 0
   ret <2 x float> %tmp2
 }
@@ -919,12 +919,12 @@ entry:
 ; CHECK-NEXT: str d[[RESREGNUM]], [x2]
 ; CHECK-NEXT: ret
   %tmp = bitcast i8* %a to i32*
-  %tmp1 = load i32* %tmp, align 4
+  %tmp1 = load i32, i32* %tmp, align 4
   %tmp2 = insertelement <2 x i32> undef, i32 %tmp1, i32 0
   %lane = shufflevector <2 x i32> %tmp2, <2 x i32> undef, <2 x i32> zeroinitializer
   %tmp3 = bitcast <2 x i32> %lane to <8 x i8>
   %tmp4 = bitcast i8* %b to i32*
-  %tmp5 = load i32* %tmp4, align 4
+  %tmp5 = load i32, i32* %tmp4, align 4
   %tmp6 = insertelement <2 x i32> undef, i32 %tmp5, i32 0
   %lane1 = shufflevector <2 x i32> %tmp6, <2 x i32> undef, <2 x i32> zeroinitializer
   %tmp7 = bitcast <2 x i32> %lane1 to <8 x i8>
@@ -945,8 +945,8 @@ entry:
 ; CHECK-LABEL: ld1r_4s_float
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1r.4s { v0 }, [x0]
-; CHECK-NEXT ret
-  %tmp = load float* %x, align 4
+; CHECK-NEXT: ret
+  %tmp = load float, float* %x, align 4
   %tmp1 = insertelement <4 x float> undef, float %tmp, i32 0
   %tmp2 = insertelement <4 x float> %tmp1, float %tmp, i32 1
   %tmp3 = insertelement <4 x float> %tmp2, float %tmp, i32 2
@@ -959,8 +959,8 @@ entry:
 ; CHECK-LABEL: ld1r_2s_float
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1r.2s { v0 }, [x0]
-; CHECK-NEXT ret
-  %tmp = load float* %x, align 4
+; CHECK-NEXT: ret
+  %tmp = load float, float* %x, align 4
   %tmp1 = insertelement <2 x float> undef, float %tmp, i32 0
   %tmp2 = insertelement <2 x float> %tmp1, float %tmp, i32 1
   ret <2 x float> %tmp2
@@ -971,8 +971,8 @@ entry:
 ; CHECK-LABEL: ld1r_2d_double
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1r.2d { v0 }, [x0]
-; CHECK-NEXT ret
-  %tmp = load double* %x, align 4
+; CHECK-NEXT: ret
+  %tmp = load double, double* %x, align 4
   %tmp1 = insertelement <2 x double> undef, double %tmp, i32 0
   %tmp2 = insertelement <2 x double> %tmp1, double %tmp, i32 1
   ret <2 x double> %tmp2
@@ -983,8 +983,8 @@ entry:
 ; CHECK-LABEL: ld1r_1d_double
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ldr d0, [x0]
-; CHECK-NEXT ret
-  %tmp = load double* %x, align 4
+; CHECK-NEXT: ret
+  %tmp = load double, double* %x, align 4
   %tmp1 = insertelement <1 x double> undef, double %tmp, i32 0
   ret <1 x double> %tmp1
 }
@@ -994,8 +994,8 @@ entry:
 ; CHECK-LABEL: ld1r_4s_float_shuff
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1r.4s { v0 }, [x0]
-; CHECK-NEXT ret
-  %tmp = load float* %x, align 4
+; CHECK-NEXT: ret
+  %tmp = load float, float* %x, align 4
   %tmp1 = insertelement <4 x float> undef, float %tmp, i32 0
   %lane = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
   ret <4 x float> %lane
@@ -1006,8 +1006,8 @@ entry:
 ; CHECK-LABEL: ld1r_2s_float_shuff
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1r.2s { v0 }, [x0]
-; CHECK-NEXT ret
-  %tmp = load float* %x, align 4
+; CHECK-NEXT: ret
+  %tmp = load float, float* %x, align 4
   %tmp1 = insertelement <2 x float> undef, float %tmp, i32 0
   %lane = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
   ret <2 x float> %lane
@@ -1018,8 +1018,8 @@ entry:
 ; CHECK-LABEL: ld1r_2d_double_shuff
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ld1r.2d { v0 }, [x0]
-; CHECK-NEXT ret
-  %tmp = load double* %x, align 4
+; CHECK-NEXT: ret
+  %tmp = load double, double* %x, align 4
   %tmp1 = insertelement <2 x double> undef, double %tmp, i32 0
   %lane = shufflevector <2 x double> %tmp1, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %lane
@@ -1030,8 +1030,8 @@ entry:
 ; CHECK-LABEL: ld1r_1d_double_shuff
 ; Make sure we are using the operands defined by the ABI
 ; CHECK: ldr d0, [x0]
-; CHECK-NEXT ret
-  %tmp = load double* %x, align 4
+; CHECK-NEXT: ret
+  %tmp = load double, double* %x, align 4
   %tmp1 = insertelement <1 x double> undef, double %tmp, i32 0
   %lane = shufflevector <1 x double> %tmp1, <1 x double> undef, <1 x i32> zeroinitializer
   ret <1 x double> %lane
diff --git a/test/CodeGen/AArch64/arm64-ldp-aa.ll b/test/CodeGen/AArch64/arm64-ldp-aa.ll
new file mode 100644
index 000000000000..ad5c01cfe34e
--- /dev/null
+++ b/test/CodeGen/AArch64/arm64-ldp-aa.ll
@@ -0,0 +1,60 @@
+; RUN: llc < %s -march=arm64 -enable-misched=false -verify-machineinstrs | FileCheck %s
+
+; The next set of tests makes sure we can combine the second instruction into
+; the first.
+
+; CHECK-LABEL: ldp_int_aa
+; CHECK: ldp w8, w9, [x1]
+; CHECK: str w0, [x1, #8]
+; CHECK: ret
+define i32 @ldp_int_aa(i32 %a, i32* %p) nounwind {
+  %tmp = load i32, i32* %p, align 4
+  %str.ptr = getelementptr inbounds i32, i32* %p, i64 2
+  store i32 %a, i32* %str.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
+  %tmp1 = load i32, i32* %add.ptr, align 4
+  %add = add nsw i32 %tmp1, %tmp
+  ret i32 %add
+}
+
+; CHECK-LABEL: ldp_long_aa
+; CHECK: ldp x8, x9, [x1]
+; CHECK: str x0, [x1, #16]
+; CHECK: ret
+define i64 @ldp_long_aa(i64 %a, i64* %p) nounwind {
+  %tmp = load i64, i64* %p, align 8
+  %str.ptr = getelementptr inbounds i64, i64* %p, i64 2
+  store i64 %a, i64* %str.ptr, align 4
+  %add.ptr = getelementptr inbounds i64, i64* %p, i64 1
+  %tmp1 = load i64, i64* %add.ptr, align 8
+  %add = add nsw i64 %tmp1, %tmp
+  ret i64 %add
+}
+
+; CHECK-LABEL: ldp_float_aa
+; CHECK: str s0, [x0, #8]
+; CHECK: ldp s1, s0, [x0]
+; CHECK: ret
+define float @ldp_float_aa(float %a, float* %p) nounwind {
+  %tmp = load float, float* %p, align 4
+  %str.ptr = getelementptr inbounds float, float* %p, i64 2
+  store float %a, float* %str.ptr, align 4
+  %add.ptr = getelementptr inbounds float, float* %p, i64 1
+  %tmp1 = load float, float* %add.ptr, align 4
+  %add = fadd float %tmp, %tmp1
+  ret float %add
+}
+
+; CHECK-LABEL: ldp_double_aa
+; CHECK: str d0, [x0, #16]
+; CHECK: ldp d1, d0, [x0]
+; CHECK: ret
+define double @ldp_double_aa(double %a, double* %p) nounwind {
+  %tmp = load double, double* %p, align 8
+  %str.ptr = getelementptr inbounds double, double* %p, i64 2
+  store double %a, double* %str.ptr, align 4
+  %add.ptr = getelementptr inbounds double, double* %p, i64 1
+  %tmp1 = load double, double* %add.ptr, align 8
+  %add = fadd double %tmp, %tmp1
+  ret double %add
+}
diff --git a/test/CodeGen/AArch64/arm64-ldp.ll b/test/CodeGen/AArch64/arm64-ldp.ll
index 5a986261b31b..a192eab112fa 100644
--- a/test/CodeGen/AArch64/arm64-ldp.ll
+++ b/test/CodeGen/AArch64/arm64-ldp.ll
@@ -5,19 +5,58 @@
 ; CHECK: ldp_int
 ; CHECK: ldp
 define i32 @ldp_int(i32* %p) nounwind {
-  %tmp = load i32* %p, align 4
-  %add.ptr = getelementptr inbounds i32* %p, i64 1
-  %tmp1 = load i32* %add.ptr, align 4
+  %tmp = load i32, i32* %p, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
+  %tmp1 = load i32, i32* %add.ptr, align 4
   %add = add nsw i32 %tmp1, %tmp
   ret i32 %add
 }
 
+; CHECK: ldp_sext_int
+; CHECK: ldpsw
+define i64 @ldp_sext_int(i32* %p) nounwind {
+  %tmp = load i32, i32* %p, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
+  %tmp1 = load i32, i32* %add.ptr, align 4
+  %sexttmp = sext i32 %tmp to i64
+  %sexttmp1 = sext i32 %tmp1 to i64
+  %add = add nsw i64 %sexttmp1, %sexttmp
+  ret i64 %add
+}
+
+; CHECK-LABEL: ldp_half_sext_res0_int:
+; CHECK: ldp     w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0]
+; CHECK: sxtw     x[[DST1]], w[[DST1]]
+define i64 @ldp_half_sext_res0_int(i32* %p) nounwind {
+  %tmp = load i32, i32* %p, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
+  %tmp1 = load i32, i32* %add.ptr, align 4
+  %sexttmp = sext i32 %tmp to i64
+  %sexttmp1 = zext i32 %tmp1 to i64
+  %add = add nsw i64 %sexttmp1, %sexttmp
+  ret i64 %add
+}
+
+; CHECK-LABEL: ldp_half_sext_res1_int:
+; CHECK: ldp     w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0]
+; CHECK: sxtw     x[[DST2]], w[[DST2]]
+define i64 @ldp_half_sext_res1_int(i32* %p) nounwind {
+  %tmp = load i32, i32* %p, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
+  %tmp1 = load i32, i32* %add.ptr, align 4
+  %sexttmp = zext i32 %tmp to i64
+  %sexttmp1 = sext i32 %tmp1 to i64
+  %add = add nsw i64 %sexttmp1, %sexttmp
+  ret i64 %add
+}
+
+
 ; CHECK: ldp_long
 ; CHECK: ldp
 define i64 @ldp_long(i64* %p) nounwind {
-  %tmp = load i64* %p, align 8
-  %add.ptr = getelementptr inbounds i64* %p, i64 1
-  %tmp1 = load i64* %add.ptr, align 8
+  %tmp = load i64, i64* %p, align 8
+  %add.ptr = getelementptr inbounds i64, i64* %p, i64 1
+  %tmp1 = load i64, i64* %add.ptr, align 8
   %add = add nsw i64 %tmp1, %tmp
   ret i64 %add
 }
@@ -25,9 +64,9 @@ define i64 @ldp_long(i64* %p) nounwind {
 ; CHECK: ldp_float
 ; CHECK: ldp
 define float @ldp_float(float* %p) nounwind {
-  %tmp = load float* %p, align 4
-  %add.ptr = getelementptr inbounds float* %p, i64 1
-  %tmp1 = load float* %add.ptr, align 4
+  %tmp = load float, float* %p, align 4
+  %add.ptr = getelementptr inbounds float, float* %p, i64 1
+  %tmp1 = load float, float* %add.ptr, align 4
   %add = fadd float %tmp, %tmp1
   ret float %add
 }
@@ -35,9 +74,9 @@ define float @ldp_float(float* %p) nounwind {
 ; CHECK: ldp_double
 ; CHECK: ldp
 define double @ldp_double(double* %p) nounwind {
-  %tmp = load double* %p, align 8
-  %add.ptr = getelementptr inbounds double* %p, i64 1
-  %tmp1 = load double* %add.ptr, align 8
+  %tmp = load double, double* %p, align 8
+  %add.ptr = getelementptr inbounds double, double* %p, i64 1
+  %tmp1 = load double, double* %add.ptr, align 8
   %add = fadd double %tmp, %tmp1
   ret double %add
 }
@@ -48,23 +87,71 @@ define i32 @ldur_int(i32* %a) nounwind {
 ; LDUR_CHK: ldp     [[DST1:w[0-9]+]], [[DST2:w[0-9]+]], [x0, #-8]
 ; LDUR_CHK-NEXT: add     w{{[0-9]+}}, [[DST2]], [[DST1]]
 ; LDUR_CHK-NEXT: ret
-  %p1 = getelementptr inbounds i32* %a, i32 -1
-  %tmp1 = load i32* %p1, align 2
-  %p2 = getelementptr inbounds i32* %a, i32 -2
-  %tmp2 = load i32* %p2, align 2
+  %p1 = getelementptr inbounds i32, i32* %a, i32 -1
+  %tmp1 = load i32, i32* %p1, align 2
+  %p2 = getelementptr inbounds i32, i32* %a, i32 -2
+  %tmp2 = load i32, i32* %p2, align 2
   %tmp3 = add i32 %tmp1, %tmp2
   ret i32 %tmp3
 }
 
+define i64 @ldur_sext_int(i32* %a) nounwind {
+; LDUR_CHK: ldur_sext_int
+; LDUR_CHK: ldpsw     [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-8]
+; LDUR_CHK-NEXT: add     x{{[0-9]+}}, [[DST2]], [[DST1]]
+; LDUR_CHK-NEXT: ret
+  %p1 = getelementptr inbounds i32, i32* %a, i32 -1
+  %tmp1 = load i32, i32* %p1, align 2
+  %p2 = getelementptr inbounds i32, i32* %a, i32 -2
+  %tmp2 = load i32, i32* %p2, align 2
+  %sexttmp1 = sext i32 %tmp1 to i64
+  %sexttmp2 = sext i32 %tmp2 to i64
+  %tmp3 = add i64 %sexttmp1, %sexttmp2
+  ret i64 %tmp3
+}
+
+define i64 @ldur_half_sext_int_res0(i32* %a) nounwind {
+; LDUR_CHK: ldur_half_sext_int_res0
+; LDUR_CHK: ldp     w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-8]
+; LDUR_CHK: sxtw     x[[DST1]], w[[DST1]]
+; LDUR_CHK-NEXT: add     x{{[0-9]+}}, x[[DST2]], x[[DST1]]
+; LDUR_CHK-NEXT: ret
+  %p1 = getelementptr inbounds i32, i32* %a, i32 -1
+  %tmp1 = load i32, i32* %p1, align 2
+  %p2 = getelementptr inbounds i32, i32* %a, i32 -2
+  %tmp2 = load i32, i32* %p2, align 2
+  %sexttmp1 = zext i32 %tmp1 to i64
+  %sexttmp2 = sext i32 %tmp2 to i64
+  %tmp3 = add i64 %sexttmp1, %sexttmp2
+  ret i64 %tmp3
+}
+
+define i64 @ldur_half_sext_int_res1(i32* %a) nounwind {
+; LDUR_CHK: ldur_half_sext_int_res1
+; LDUR_CHK: ldp     w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-8]
+; LDUR_CHK: sxtw     x[[DST2]], w[[DST2]]
+; LDUR_CHK-NEXT: add     x{{[0-9]+}}, x[[DST2]], x[[DST1]]
+; LDUR_CHK-NEXT: ret
+  %p1 = getelementptr inbounds i32, i32* %a, i32 -1
+  %tmp1 = load i32, i32* %p1, align 2
+  %p2 = getelementptr inbounds i32, i32* %a, i32 -2
+  %tmp2 = load i32, i32* %p2, align 2
+  %sexttmp1 = sext i32 %tmp1 to i64
+  %sexttmp2 = zext i32 %tmp2 to i64
+  %tmp3 = add i64 %sexttmp1, %sexttmp2
+  ret i64 %tmp3
+}
+
+
 define i64 @ldur_long(i64* %a) nounwind ssp {
 ; LDUR_CHK: ldur_long
 ; LDUR_CHK: ldp     [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-16]
 ; LDUR_CHK-NEXT: add     x{{[0-9]+}}, [[DST2]], [[DST1]]
 ; LDUR_CHK-NEXT: ret
-  %p1 = getelementptr inbounds i64* %a, i64 -1
-  %tmp1 = load i64* %p1, align 2
-  %p2 = getelementptr inbounds i64* %a, i64 -2
-  %tmp2 = load i64* %p2, align 2
+  %p1 = getelementptr inbounds i64, i64* %a, i64 -1
+  %tmp1 = load i64, i64* %p1, align 2
+  %p2 = getelementptr inbounds i64, i64* %a, i64 -2
+  %tmp2 = load i64, i64* %p2, align 2
   %tmp3 = add i64 %tmp1, %tmp2
   ret i64 %tmp3
 }
@@ -74,10 +161,10 @@ define float @ldur_float(float* %a) {
 ; LDUR_CHK: ldp     [[DST1:s[0-9]+]], [[DST2:s[0-9]+]], [x0, #-8]
 ; LDUR_CHK-NEXT: add     s{{[0-9]+}}, [[DST2]], [[DST1]]
 ; LDUR_CHK-NEXT: ret
-  %p1 = getelementptr inbounds float* %a, i64 -1
-  %tmp1 = load float* %p1, align 2
-  %p2 = getelementptr inbounds float* %a, i64 -2
-  %tmp2 = load float* %p2, align 2
+  %p1 = getelementptr inbounds float, float* %a, i64 -1
+  %tmp1 = load float, float* %p1, align 2
+  %p2 = getelementptr inbounds float, float* %a, i64 -2
+  %tmp2 = load float, float* %p2, align 2
   %tmp3 = fadd float %tmp1, %tmp2
   ret float %tmp3
 }
@@ -87,10 +174,10 @@ define double @ldur_double(double* %a) {
 ; LDUR_CHK: ldp     [[DST1:d[0-9]+]], [[DST2:d[0-9]+]], [x0, #-16]
 ; LDUR_CHK-NEXT: add     d{{[0-9]+}}, [[DST2]], [[DST1]]
 ; LDUR_CHK-NEXT: ret
-  %p1 = getelementptr inbounds double* %a, i64 -1
-  %tmp1 = load double* %p1, align 2
-  %p2 = getelementptr inbounds double* %a, i64 -2
-  %tmp2 = load double* %p2, align 2
+  %p1 = getelementptr inbounds double, double* %a, i64 -1
+  %tmp1 = load double, double* %p1, align 2
+  %p2 = getelementptr inbounds double, double* %a, i64 -2
+  %tmp2 = load double, double* %p2, align 2
   %tmp3 = fadd double %tmp1, %tmp2
   ret double %tmp3
 }
@@ -102,14 +189,64 @@ define i64 @pairUpBarelyIn(i64* %a) nounwind ssp {
 ; LDUR_CHK: ldp     [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-256]
 ; LDUR_CHK-NEXT: add     x{{[0-9]+}}, [[DST2]], [[DST1]]
 ; LDUR_CHK-NEXT: ret
-  %p1 = getelementptr inbounds i64* %a, i64 -31
-  %tmp1 = load i64* %p1, align 2
-  %p2 = getelementptr inbounds i64* %a, i64 -32
-  %tmp2 = load i64* %p2, align 2
+  %p1 = getelementptr inbounds i64, i64* %a, i64 -31
+  %tmp1 = load i64, i64* %p1, align 2
+  %p2 = getelementptr inbounds i64, i64* %a, i64 -32
+  %tmp2 = load i64, i64* %p2, align 2
   %tmp3 = add i64 %tmp1, %tmp2
   ret i64 %tmp3
 }
 
+define i64 @pairUpBarelyInSext(i32* %a) nounwind ssp {
+; LDUR_CHK: pairUpBarelyInSext
+; LDUR_CHK-NOT: ldur
+; LDUR_CHK: ldpsw     [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-256]
+; LDUR_CHK-NEXT: add     x{{[0-9]+}}, [[DST2]], [[DST1]]
+; LDUR_CHK-NEXT: ret
+  %p1 = getelementptr inbounds i32, i32* %a, i64 -63
+  %tmp1 = load i32, i32* %p1, align 2
+  %p2 = getelementptr inbounds i32, i32* %a, i64 -64
+  %tmp2 = load i32, i32* %p2, align 2
+  %sexttmp1 = sext i32 %tmp1 to i64
+  %sexttmp2 = sext i32 %tmp2 to i64
+  %tmp3 = add i64 %sexttmp1, %sexttmp2
+  ret i64 %tmp3
+}
+
+define i64 @pairUpBarelyInHalfSextRes0(i32* %a) nounwind ssp {
+; LDUR_CHK: pairUpBarelyInHalfSextRes0
+; LDUR_CHK-NOT: ldur
+; LDUR_CHK: ldp     w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-256]
+; LDUR_CHK: sxtw     x[[DST1]], w[[DST1]]
+; LDUR_CHK-NEXT: add     x{{[0-9]+}}, x[[DST2]], x[[DST1]]
+; LDUR_CHK-NEXT: ret
+  %p1 = getelementptr inbounds i32, i32* %a, i64 -63
+  %tmp1 = load i32, i32* %p1, align 2
+  %p2 = getelementptr inbounds i32, i32* %a, i64 -64
+  %tmp2 = load i32, i32* %p2, align 2
+  %sexttmp1 = zext i32 %tmp1 to i64
+  %sexttmp2 = sext i32 %tmp2 to i64
+  %tmp3 = add i64 %sexttmp1, %sexttmp2
+  ret i64 %tmp3
+}
+
+define i64 @pairUpBarelyInHalfSextRes1(i32* %a) nounwind ssp {
+; LDUR_CHK: pairUpBarelyInHalfSextRes1
+; LDUR_CHK-NOT: ldur
+; LDUR_CHK: ldp     w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-256]
+; LDUR_CHK: sxtw     x[[DST2]], w[[DST2]]
+; LDUR_CHK-NEXT: add     x{{[0-9]+}}, x[[DST2]], x[[DST1]]
+; LDUR_CHK-NEXT: ret
+  %p1 = getelementptr inbounds i32, i32* %a, i64 -63
+  %tmp1 = load i32, i32* %p1, align 2
+  %p2 = getelementptr inbounds i32, i32* %a, i64 -64
+  %tmp2 = load i32, i32* %p2, align 2
+  %sexttmp1 = sext i32 %tmp1 to i64
+  %sexttmp2 = zext i32 %tmp2 to i64
+  %tmp3 = add i64 %sexttmp1, %sexttmp2
+  ret i64 %tmp3
+}
+
 define i64 @pairUpBarelyOut(i64* %a) nounwind ssp {
 ; LDUR_CHK: pairUpBarelyOut
 ; LDUR_CHK-NOT: ldp
@@ -117,14 +254,31 @@ define i64 @pairUpBarelyOut(i64* %a) nounwind ssp {
 ; are used---just check that there isn't an ldp before the add
 ; LDUR_CHK: add
 ; LDUR_CHK-NEXT: ret
-  %p1 = getelementptr inbounds i64* %a, i64 -32
-  %tmp1 = load i64* %p1, align 2
-  %p2 = getelementptr inbounds i64* %a, i64 -33
-  %tmp2 = load i64* %p2, align 2
+  %p1 = getelementptr inbounds i64, i64* %a, i64 -32
+  %tmp1 = load i64, i64* %p1, align 2
+  %p2 = getelementptr inbounds i64, i64* %a, i64 -33
+  %tmp2 = load i64, i64* %p2, align 2
   %tmp3 = add i64 %tmp1, %tmp2
   ret i64 %tmp3
 }
 
+define i64 @pairUpBarelyOutSext(i32* %a) nounwind ssp {
+; LDUR_CHK: pairUpBarelyOutSext
+; LDUR_CHK-NOT: ldp
+; Don't be fragile about which loads or manipulations of the base register
+; are used---just check that there isn't an ldp before the add
+; LDUR_CHK: add
+; LDUR_CHK-NEXT: ret
+  %p1 = getelementptr inbounds i32, i32* %a, i64 -64
+  %tmp1 = load i32, i32* %p1, align 2
+  %p2 = getelementptr inbounds i32, i32* %a, i64 -65
+  %tmp2 = load i32, i32* %p2, align 2
+  %sexttmp1 = sext i32 %tmp1 to i64
+  %sexttmp2 = sext i32 %tmp2 to i64
+  %tmp3 = add i64 %sexttmp1, %sexttmp2
+  ret i64 %tmp3
+}
+
 define i64 @pairUpNotAligned(i64* %a) nounwind ssp {
 ; LDUR_CHK: pairUpNotAligned
 ; LDUR_CHK-NOT: ldp
@@ -132,18 +286,43 @@ define i64 @pairUpNotAligned(i64* %a) nounwind ssp {
 ; LDUR_CHK-NEXT: ldur
 ; LDUR_CHK-NEXT: add
 ; LDUR_CHK-NEXT: ret
-  %p1 = getelementptr inbounds i64* %a, i64 -18
+  %p1 = getelementptr inbounds i64, i64* %a, i64 -18
   %bp1 = bitcast i64* %p1 to i8*
-  %bp1p1 = getelementptr inbounds i8* %bp1, i64 1
+  %bp1p1 = getelementptr inbounds i8, i8* %bp1, i64 1
   %dp1 = bitcast i8* %bp1p1 to i64*
-  %tmp1 = load i64* %dp1, align 1
+  %tmp1 = load i64, i64* %dp1, align 1
 
-  %p2 = getelementptr inbounds i64* %a, i64 -17
+  %p2 = getelementptr inbounds i64, i64* %a, i64 -17
   %bp2 = bitcast i64* %p2 to i8*
-  %bp2p1 = getelementptr inbounds i8* %bp2, i64 1
+  %bp2p1 = getelementptr inbounds i8, i8* %bp2, i64 1
   %dp2 = bitcast i8* %bp2p1 to i64*
-  %tmp2 = load i64* %dp2, align 1
+  %tmp2 = load i64, i64* %dp2, align 1
 
   %tmp3 = add i64 %tmp1, %tmp2
   ret i64 %tmp3
 }
+
+define i64 @pairUpNotAlignedSext(i32* %a) nounwind ssp {
+; LDUR_CHK: pairUpNotAlignedSext
+; LDUR_CHK-NOT: ldp
+; LDUR_CHK: ldursw
+; LDUR_CHK-NEXT: ldursw
+; LDUR_CHK-NEXT: add
+; LDUR_CHK-NEXT: ret
+  %p1 = getelementptr inbounds i32, i32* %a, i64 -18
+  %bp1 = bitcast i32* %p1 to i8*
+  %bp1p1 = getelementptr inbounds i8, i8* %bp1, i64 1
+  %dp1 = bitcast i8* %bp1p1 to i32*
+  %tmp1 = load i32, i32* %dp1, align 1
+
+  %p2 = getelementptr inbounds i32, i32* %a, i64 -17
+  %bp2 = bitcast i32* %p2 to i8*
+  %bp2p1 = getelementptr inbounds i8, i8* %bp2, i64 1
+  %dp2 = bitcast i8* %bp2p1 to i32*
+  %tmp2 = load i32, i32* %dp2, align 1
+
+  %sexttmp1 = sext i32 %tmp1 to i64
+  %sexttmp2 = sext i32 %tmp2 to i64
+  %tmp3 = add i64 %sexttmp1, %sexttmp2
+ ret i64 %tmp3
+}
diff --git a/test/CodeGen/AArch64/arm64-ldur.ll b/test/CodeGen/AArch64/arm64-ldur.ll
index 2848c06f9bb0..c4bf397d5d03 100644
--- a/test/CodeGen/AArch64/arm64-ldur.ll
+++ b/test/CodeGen/AArch64/arm64-ldur.ll
@@ -4,32 +4,32 @@ define i64 @_f0(i64* %p) {
 ; CHECK: f0:
 ; CHECK: ldur x0, [x0, #-8]
 ; CHECK-NEXT: ret
-  %tmp = getelementptr inbounds i64* %p, i64 -1
-  %ret = load i64* %tmp, align 2
+  %tmp = getelementptr inbounds i64, i64* %p, i64 -1
+  %ret = load i64, i64* %tmp, align 2
   ret i64 %ret
 }
 define i32 @_f1(i32* %p) {
 ; CHECK: f1:
 ; CHECK: ldur w0, [x0, #-4]
 ; CHECK-NEXT: ret
-  %tmp = getelementptr inbounds i32* %p, i64 -1
-  %ret = load i32* %tmp, align 2
+  %tmp = getelementptr inbounds i32, i32* %p, i64 -1
+  %ret = load i32, i32* %tmp, align 2
   ret i32 %ret
 }
 define i16 @_f2(i16* %p) {
 ; CHECK: f2:
 ; CHECK: ldurh w0, [x0, #-2]
 ; CHECK-NEXT: ret
-  %tmp = getelementptr inbounds i16* %p, i64 -1
-  %ret = load i16* %tmp, align 2
+  %tmp = getelementptr inbounds i16, i16* %p, i64 -1
+  %ret = load i16, i16* %tmp, align 2
   ret i16 %ret
 }
 define i8 @_f3(i8* %p) {
 ; CHECK: f3:
 ; CHECK: ldurb w0, [x0, #-1]
 ; CHECK-NEXT: ret
-  %tmp = getelementptr inbounds i8* %p, i64 -1
-  %ret = load i8* %tmp, align 2
+  %tmp = getelementptr inbounds i8, i8* %p, i64 -1
+  %ret = load i8, i8* %tmp, align 2
   ret i8 %ret
 }
 
@@ -37,9 +37,9 @@ define i64 @zext32(i8* %a) nounwind ssp {
 ; CHECK-LABEL: zext32:
 ; CHECK: ldur w0, [x0, #-12]
 ; CHECK-NEXT: ret
-  %p = getelementptr inbounds i8* %a, i64 -12
+  %p = getelementptr inbounds i8, i8* %a, i64 -12
   %tmp1 = bitcast i8* %p to i32*
-  %tmp2 = load i32* %tmp1, align 4
+  %tmp2 = load i32, i32* %tmp1, align 4
   %ret = zext i32 %tmp2 to i64
 
   ret i64 %ret
@@ -48,9 +48,9 @@ define i64 @zext16(i8* %a) nounwind ssp {
 ; CHECK-LABEL: zext16:
 ; CHECK: ldurh w0, [x0, #-12]
 ; CHECK-NEXT: ret
-  %p = getelementptr inbounds i8* %a, i64 -12
+  %p = getelementptr inbounds i8, i8* %a, i64 -12
   %tmp1 = bitcast i8* %p to i16*
-  %tmp2 = load i16* %tmp1, align 2
+  %tmp2 = load i16, i16* %tmp1, align 2
   %ret = zext i16 %tmp2 to i64
 
   ret i64 %ret
@@ -59,8 +59,8 @@ define i64 @zext8(i8* %a) nounwind ssp {
 ; CHECK-LABEL: zext8:
 ; CHECK: ldurb w0, [x0, #-12]
 ; CHECK-NEXT: ret
-  %p = getelementptr inbounds i8* %a, i64 -12
-  %tmp2 = load i8* %p, align 1
+  %p = getelementptr inbounds i8, i8* %a, i64 -12
+  %tmp2 = load i8, i8* %p, align 1
   %ret = zext i8 %tmp2 to i64
 
   ret i64 %ret
diff --git a/test/CodeGen/AArch64/arm64-memcpy-inline.ll b/test/CodeGen/AArch64/arm64-memcpy-inline.ll
index f921a592451d..2f91ce252336 100644
--- a/test/CodeGen/AArch64/arm64-memcpy-inline.ll
+++ b/test/CodeGen/AArch64/arm64-memcpy-inline.ll
@@ -22,7 +22,7 @@ entry:
 ; CHECK: strh [[REG1]], [x[[BASEREG2]], #8]
 ; CHECK: ldr [[REG2:x[0-9]+]],
 ; CHECK: str [[REG2]],
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x, %struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x, %struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false)
   ret i32 0
 }
 
@@ -33,7 +33,7 @@ entry:
 ; CHECK: stur [[DEST]], [x0, #15]
 ; CHECK: ldr [[DEST:q[0-9]+]], [x[[BASEREG]]]
 ; CHECK: str [[DEST]], [x0]
-  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8]* @.str1, i64 0, i64 0), i64 31, i32 1, i1 false)
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str1, i64 0, i64 0), i64 31, i32 1, i1 false)
   ret void
 }
 
@@ -45,7 +45,7 @@ entry:
 ; CHECK: str [[REG3]], [x0, #32]
 ; CHECK: ldp [[DEST1:q[0-9]+]], [[DEST2:q[0-9]+]], [x{{[0-9]+}}]
 ; CHECK: stp [[DEST1]], [[DEST2]], [x0]
-  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false)
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8], [36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false)
   ret void
 }
 
@@ -56,7 +56,7 @@ entry:
 ; CHECK: str [[REG4]], [x0, #16]
 ; CHECK: ldr [[DEST:q[0-9]+]], [x[[BASEREG]]]
 ; CHECK: str [[DEST]], [x0]
-  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false)
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false)
   ret void
 }
 
@@ -67,7 +67,7 @@ entry:
 ; CHECK: strh [[REG5]], [x0, #16]
 ; CHECK: ldr [[REG6:q[0-9]+]], [x{{[0-9]+}}]
 ; CHECK: str [[REG6]], [x0]
-  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
   ret void
 }
 
@@ -80,7 +80,7 @@ entry:
 ; CHECK: movz [[REG8:w[0-9]+]],
 ; CHECK: movk [[REG8]],
 ; CHECK: str [[REG8]], [x0]
-  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8]* @.str5, i64 0, i64 0), i64 7, i32 1, i1 false)
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str5, i64 0, i64 0), i64 7, i32 1, i1 false)
   ret void
 }
 
@@ -91,7 +91,7 @@ entry:
 ; CHECK: stur [[REG9]], [x{{[0-9]+}}, #6]
 ; CHECK: ldr
 ; CHECK: str
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([512 x i8]* @spool.splbuf, i64 0, i64 0), i8* getelementptr inbounds ([14 x i8]* @.str6, i64 0, i64 0), i64 14, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([512 x i8], [512 x i8]* @spool.splbuf, i64 0, i64 0), i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str6, i64 0, i64 0), i64 14, i32 1, i1 false)
   ret void
 }
 
diff --git a/test/CodeGen/AArch64/arm64-memset-inline.ll b/test/CodeGen/AArch64/arm64-memset-inline.ll
index 2e237f4a882d..56959ade0439 100644
--- a/test/CodeGen/AArch64/arm64-memset-inline.ll
+++ b/test/CodeGen/AArch64/arm64-memset-inline.ll
@@ -16,7 +16,7 @@ entry:
 ; CHECK: stp xzr, xzr, [sp, #16]
 ; CHECK: str xzr, [sp, #8]
   %buf = alloca [26 x i8], align 1
-  %0 = getelementptr inbounds [26 x i8]* %buf, i32 0, i32 0
+  %0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0
   call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false)
   call void @something(i8* %0) nounwind
   ret void
diff --git a/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll b/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
new file mode 100644
index 000000000000..5bc4d71501ba
--- /dev/null
+++ b/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=arm64-apple-ios -aarch64-strict-align < %s | FileCheck %s
+
+; Small (16-bytes here) unaligned memcpys should stay memcpy calls if
+; strict-alignment is turned on.
+define void @t0(i8* %out, i8* %in) {
+; CHECK-LABEL: t0:
+; CHECK:         orr w2, wzr, #0x10
+; CHECK-NEXT:    bl _memcpy
+entry:
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %out, i8* %in, i64 16, i32 1, i1 false)
+  ret void
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1)
diff --git a/test/CodeGen/AArch64/arm64-misched-basic-A53.ll b/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
index bc7ed7fbdf83..6db21043f670 100644
--- a/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
+++ b/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
@@ -34,44 +34,44 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %2 = load i32* %i, align 4
+  %2 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %2, 8
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %3 = load i32* %i, align 4
+  %3 = load i32, i32* %i, align 4
   %idxprom = sext i32 %3 to i64
-  %arrayidx = getelementptr inbounds [8 x i32]* %x, i32 0, i64 %idxprom
-  %4 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [8 x i32], [8 x i32]* %x, i32 0, i64 %idxprom
+  %4 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %4, 1
   store i32 %add, i32* %xx, align 4
-  %5 = load i32* %xx, align 4
+  %5 = load i32, i32* %xx, align 4
   %add1 = add nsw i32 %5, 12
   store i32 %add1, i32* %xx, align 4
-  %6 = load i32* %xx, align 4
+  %6 = load i32, i32* %xx, align 4
   %add2 = add nsw i32 %6, 23
   store i32 %add2, i32* %xx, align 4
-  %7 = load i32* %xx, align 4
+  %7 = load i32, i32* %xx, align 4
   %add3 = add nsw i32 %7, 34
   store i32 %add3, i32* %xx, align 4
-  %8 = load i32* %i, align 4
+  %8 = load i32, i32* %i, align 4
   %idxprom4 = sext i32 %8 to i64
-  %arrayidx5 = getelementptr inbounds [8 x i32]* %y, i32 0, i64 %idxprom4
-  %9 = load i32* %arrayidx5, align 4
-  %10 = load i32* %yy, align 4
+  %arrayidx5 = getelementptr inbounds [8 x i32], [8 x i32]* %y, i32 0, i64 %idxprom4
+  %9 = load i32, i32* %arrayidx5, align 4
+  %10 = load i32, i32* %yy, align 4
   %mul = mul nsw i32 %10, %9
   store i32 %mul, i32* %yy, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %11 = load i32* %i, align 4
+  %11 = load i32, i32* %i, align 4
   %inc = add nsw i32 %11, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %12 = load i32* %xx, align 4
-  %13 = load i32* %yy, align 4
+  %12 = load i32, i32* %xx, align 4
+  %13 = load i32, i32* %yy, align 4
   %add6 = add nsw i32 %12, %13
   ret i32 %add6
 }
@@ -116,7 +116,7 @@ attributes #1 = { nounwind }
 ; Nothing explicit to check other than llc not crashing.
 define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) {
   %ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0i8(i8* %A)
-  %tmp = getelementptr i8* %A, i32 32
+  %tmp = getelementptr i8, i8* %A, i32 32
   store i8* %tmp, i8** %ptr
   ret { <16 x i8>, <16 x i8> } %ld2
 }
diff --git a/test/CodeGen/AArch64/arm64-misched-basic-A57.ll b/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
index 238474a12c65..fac5f8ad2e9f 100644
--- a/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
+++ b/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
@@ -9,8 +9,8 @@
 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
 ; CHECK: ********** MI Scheduling **********
 ; CHECK: main:BB#2
-; CHECK LDR
-; CHECK Latency : 4
+; CHECK: LDR
+; CHECK: Latency : 4
 ; CHECK: *** Final schedule for BB#2 ***
 ; CHECK: LDR
 ; CHECK: LDR
@@ -41,31 +41,31 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %2 = load i32* %i, align 4
+  %2 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %2, 8
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %3 = load i32* %yy, align 4
-  %4 = load i32* %i, align 4
+  %3 = load i32, i32* %yy, align 4
+  %4 = load i32, i32* %i, align 4
   %idxprom = sext i32 %4 to i64
-  %arrayidx = getelementptr inbounds [8 x i32]* %x, i32 0, i64 %idxprom
-  %5 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [8 x i32], [8 x i32]* %x, i32 0, i64 %idxprom
+  %5 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %5, 1
   store i32 %add, i32* %xx, align 4
-  %6 = load i32* %xx, align 4
+  %6 = load i32, i32* %xx, align 4
   %add1 = add nsw i32 %6, 12
   store i32 %add1, i32* %xx, align 4
-  %7 = load i32* %xx, align 4
+  %7 = load i32, i32* %xx, align 4
   %add2 = add nsw i32 %7, 23
   store i32 %add2, i32* %xx, align 4
-  %8 = load i32* %xx, align 4
+  %8 = load i32, i32* %xx, align 4
   %add3 = add nsw i32 %8, 34
   store i32 %add3, i32* %xx, align 4
-  %9 = load i32* %i, align 4
+  %9 = load i32, i32* %i, align 4
   %idxprom4 = sext i32 %9 to i64
-  %arrayidx5 = getelementptr inbounds [8 x i32]* %y, i32 0, i64 %idxprom4
-  %10 = load i32* %arrayidx5, align 4
+  %arrayidx5 = getelementptr inbounds [8 x i32], [8 x i32]* %y, i32 0, i64 %idxprom4
+  %10 = load i32, i32* %arrayidx5, align 4
 
   %add4 = add nsw i32 %9, %add
   %add5 = add nsw i32 %10, %add1
@@ -92,14 +92,14 @@ for.body:                                         ; preds = %for.cond
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %11 = load i32* %i, align 4
+  %11 = load i32, i32* %i, align 4
   %inc = add nsw i32 %11, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %12 = load i32* %xx, align 4
-  %13 = load i32* %yy, align 4
+  %12 = load i32, i32* %xx, align 4
+  %13 = load i32, i32* %yy, align 4
   %add67 = add nsw i32 %12, %13
   ret i32 %add67
 }
diff --git a/test/CodeGen/AArch64/arm64-neon-copy.ll b/test/CodeGen/AArch64/arm64-neon-copy.ll
index 1cfba826d510..b74a40626cee 100644
--- a/test/CodeGen/AArch64/arm64-neon-copy.ll
+++ b/test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -188,7 +188,7 @@ define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {
 
 define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
 ; CHECK-LABEL: ins2f1:
-; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1]
+; CHECK: mov {{d[0-9]+}}, {{v[0-9]+}}.d[1]
   %tmp3 = extractelement <2 x double> %tmp1, i32 1
   %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
   ret <1 x double> %tmp4
@@ -1086,7 +1086,7 @@ define <2 x i32> @test_concat_diff_v1i32_v1i32(i32 %a, i32 %b) {
 ; CHECK-LABEL: test_concat_diff_v1i32_v1i32:
 ; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}}
 ; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}}
-; CHECK-NEXT: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK: ins {{v[0-9]+}}.s[1], w{{[0-9]+}}
 entry:
   %c = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %a)
   %d = insertelement <2 x i32> undef, i32 %c, i32 0
diff --git a/test/CodeGen/AArch64/arm64-neon-select_cc.ll b/test/CodeGen/AArch64/arm64-neon-select_cc.ll
index d334c0846ace..fe765f4ef984 100644
--- a/test/CodeGen/AArch64/arm64-neon-select_cc.ll
+++ b/test/CodeGen/AArch64/arm64-neon-select_cc.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
+; RUN: llc  -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast \
+; RUN:        < %s -verify-machineinstrs -asm-verbose=false | FileCheck %s
 
 define <8x i8> @test_select_cc_v8i8_i8(i8 %a, i8 %b, <8x i8> %c, <8x i8> %d ) {
 ; CHECK-LABEL: test_select_cc_v8i8_i8:
@@ -219,3 +220,30 @@ define <2 x i32> @test_select_cc_v2i32_icmpi1(i1 %cc, <2 x i32> %a, <2 x i32> %b
   %e = select i1 %cmp, <2 x i32> %a, <2 x i32> %b
   ret <2 x i32> %e
 }
+
+; Also make sure we support irregular/non-power-of-2 types such as v3f32.
+define <3 x float> @test_select_cc_v3f32_fcmp_f32(<3 x float> %a, <3 x float> %b, float %c1, float %c2) #0 {
+; CHECK-LABEL: test_select_cc_v3f32_fcmp_f32:
+; CHECK-NEXT: fcmeq [[MASK:v[0-9]+]].4s, v2.4s, v3.4s
+; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]
+; CHECK-NEXT: bsl [[DUPMASK:v[0-9]+]].16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, [[DUPMASK]].16b
+; CHECK-NEXT: ret
+  %cc = fcmp oeq float %c1, %c2
+  %r = select i1 %cc, <3 x float> %a, <3 x float> %b
+  ret <3 x float> %r
+}
+
+define <3 x float> @test_select_cc_v3f32_fcmp_f64(<3 x float> %a, <3 x float> %b, double %c1, double %c2) #0 {
+; CHECK-LABEL: test_select_cc_v3f32_fcmp_f64:
+; CHECK-NEXT: fcmeq [[MASK:v[0-9]+]].2d, v2.2d, v3.2d
+; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0]
+; CHECK-NEXT: bsl [[DUPMASK:v[0-9]+]].16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, [[DUPMASK]].16b
+; CHECK-NEXT: ret
+  %cc = fcmp oeq double %c1, %c2
+  %r = select i1 %cc, <3 x float> %a, <3 x float> %b
+  ret <3 x float> %r
+}
+
+attributes #0 = { nounwind}
diff --git a/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll b/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
index cca6bfef7307..b63200efb6b5 100644
--- a/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
+++ b/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
@@ -126,7 +126,7 @@ define <16 x i8> @test_vld1q_dup_s8(i8* %a) {
 ; CHECK-LABEL: test_vld1q_dup_s8:
 ; CHECK: ld1r {{{ ?v[0-9]+.16b ?}}}, [x0]
 entry:
-  %0 = load i8* %a, align 1
+  %0 = load i8, i8* %a, align 1
   %1 = insertelement <16 x i8> undef, i8 %0, i32 0
   %lane = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> zeroinitializer
   ret <16 x i8> %lane
@@ -136,7 +136,7 @@ define <8 x i16> @test_vld1q_dup_s16(i16* %a) {
 ; CHECK-LABEL: test_vld1q_dup_s16:
 ; CHECK: ld1r {{{ ?v[0-9]+.8h ?}}}, [x0]
 entry:
-  %0 = load i16* %a, align 2
+  %0 = load i16, i16* %a, align 2
   %1 = insertelement <8 x i16> undef, i16 %0, i32 0
   %lane = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> zeroinitializer
   ret <8 x i16> %lane
@@ -146,7 +146,7 @@ define <4 x i32> @test_vld1q_dup_s32(i32* %a) {
 ; CHECK-LABEL: test_vld1q_dup_s32:
 ; CHECK: ld1r {{{ ?v[0-9]+.4s ?}}}, [x0]
 entry:
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %1 = insertelement <4 x i32> undef, i32 %0, i32 0
   %lane = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> zeroinitializer
   ret <4 x i32> %lane
@@ -156,7 +156,7 @@ define <2 x i64> @test_vld1q_dup_s64(i64* %a) {
 ; CHECK-LABEL: test_vld1q_dup_s64:
 ; CHECK: ld1r {{{ ?v[0-9]+.2d ?}}}, [x0]
 entry:
-  %0 = load i64* %a, align 8
+  %0 = load i64, i64* %a, align 8
   %1 = insertelement <2 x i64> undef, i64 %0, i32 0
   %lane = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %lane
@@ -166,7 +166,7 @@ define <4 x float> @test_vld1q_dup_f32(float* %a) {
 ; CHECK-LABEL: test_vld1q_dup_f32:
 ; CHECK: ld1r {{{ ?v[0-9]+.4s ?}}}, [x0]
 entry:
-  %0 = load float* %a, align 4
+  %0 = load float, float* %a, align 4
   %1 = insertelement <4 x float> undef, float %0, i32 0
   %lane = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> zeroinitializer
   ret <4 x float> %lane
@@ -176,7 +176,7 @@ define <2 x double> @test_vld1q_dup_f64(double* %a) {
 ; CHECK-LABEL: test_vld1q_dup_f64:
 ; CHECK: ld1r {{{ ?v[0-9]+.2d ?}}}, [x0]
 entry:
-  %0 = load double* %a, align 8
+  %0 = load double, double* %a, align 8
   %1 = insertelement <2 x double> undef, double %0, i32 0
   %lane = shufflevector <2 x double> %1, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %lane
@@ -186,7 +186,7 @@ define <8 x i8> @test_vld1_dup_s8(i8* %a) {
 ; CHECK-LABEL: test_vld1_dup_s8:
 ; CHECK: ld1r {{{ ?v[0-9]+.8b ?}}}, [x0]
 entry:
-  %0 = load i8* %a, align 1
+  %0 = load i8, i8* %a, align 1
   %1 = insertelement <8 x i8> undef, i8 %0, i32 0
   %lane = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
   ret <8 x i8> %lane
@@ -196,7 +196,7 @@ define <4 x i16> @test_vld1_dup_s16(i16* %a) {
 ; CHECK-LABEL: test_vld1_dup_s16:
 ; CHECK: ld1r {{{ ?v[0-9]+.4h ?}}}, [x0]
 entry:
-  %0 = load i16* %a, align 2
+  %0 = load i16, i16* %a, align 2
   %1 = insertelement <4 x i16> undef, i16 %0, i32 0
   %lane = shufflevector <4 x i16> %1, <4 x i16> undef, <4 x i32> zeroinitializer
   ret <4 x i16> %lane
@@ -206,7 +206,7 @@ define <2 x i32> @test_vld1_dup_s32(i32* %a) {
 ; CHECK-LABEL: test_vld1_dup_s32:
 ; CHECK: ld1r {{{ ?v[0-9]+.2s ?}}}, [x0]
 entry:
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %1 = insertelement <2 x i32> undef, i32 %0, i32 0
   %lane = shufflevector <2 x i32> %1, <2 x i32> undef, <2 x i32> zeroinitializer
   ret <2 x i32> %lane
@@ -216,7 +216,7 @@ define <1 x i64> @test_vld1_dup_s64(i64* %a) {
 ; CHECK-LABEL: test_vld1_dup_s64:
 ; CHECK: ldr {{d[0-9]+}}, [x0]
 entry:
-  %0 = load i64* %a, align 8
+  %0 = load i64, i64* %a, align 8
   %1 = insertelement <1 x i64> undef, i64 %0, i32 0
   ret <1 x i64> %1
 }
@@ -225,7 +225,7 @@ define <2 x float> @test_vld1_dup_f32(float* %a) {
 ; CHECK-LABEL: test_vld1_dup_f32:
 ; CHECK: ld1r {{{ ?v[0-9]+.2s ?}}}, [x0]
 entry:
-  %0 = load float* %a, align 4
+  %0 = load float, float* %a, align 4
   %1 = insertelement <2 x float> undef, float %0, i32 0
   %lane = shufflevector <2 x float> %1, <2 x float> undef, <2 x i32> zeroinitializer
   ret <2 x float> %lane
@@ -235,7 +235,7 @@ define <1 x double> @test_vld1_dup_f64(double* %a) {
 ; CHECK-LABEL: test_vld1_dup_f64:
 ; CHECK: ldr {{d[0-9]+}}, [x0]
 entry:
-  %0 = load double* %a, align 8
+  %0 = load double, double* %a, align 8
   %1 = insertelement <1 x double> undef, double %0, i32 0
   ret <1 x double> %1
 }
@@ -247,7 +247,7 @@ define <1 x i64> @testDUP.v1i64(i64* %a, i64* %b) #0 {
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}]
 ; CHECK-DAG: fmov {{d[0-9]+}}, {{x[0-9]+}}
 ; CHECK-DAG: str {{x[0-9]+}}, [{{x[0-9]+}}]
-  %1 = load i64* %a, align 8
+  %1 = load i64, i64* %a, align 8
   store i64 %1, i64* %b, align 8
   %vecinit.i = insertelement <1 x i64> undef, i64 %1, i32 0
   ret <1 x i64> %vecinit.i
@@ -259,7 +259,7 @@ define <1 x double> @testDUP.v1f64(double* %a, double* %b) #0 {
 ; CHECK-LABEL: testDUP.v1f64:
 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}]
 ; CHECK: str {{d[0-9]+}}, [{{x[0-9]+}}]
-  %1 = load double* %a, align 8
+  %1 = load double, double* %a, align 8
   store double %1, double* %b, align 8
   %vecinit.i = insertelement <1 x double> undef, double %1, i32 0
   ret <1 x double> %vecinit.i
@@ -269,7 +269,7 @@ define <16 x i8> @test_vld1q_lane_s8(i8* %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vld1q_lane_s8:
 ; CHECK: ld1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
-  %0 = load i8* %a, align 1
+  %0 = load i8, i8* %a, align 1
   %vld1_lane = insertelement <16 x i8> %b, i8 %0, i32 15
   ret <16 x i8> %vld1_lane
 }
@@ -278,7 +278,7 @@ define <8 x i16> @test_vld1q_lane_s16(i16* %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vld1q_lane_s16:
 ; CHECK: ld1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
-  %0 = load i16* %a, align 2
+  %0 = load i16, i16* %a, align 2
   %vld1_lane = insertelement <8 x i16> %b, i16 %0, i32 7
   ret <8 x i16> %vld1_lane
 }
@@ -287,7 +287,7 @@ define <4 x i32> @test_vld1q_lane_s32(i32* %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vld1q_lane_s32:
 ; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %vld1_lane = insertelement <4 x i32> %b, i32 %0, i32 3
   ret <4 x i32> %vld1_lane
 }
@@ -296,7 +296,7 @@ define <2 x i64> @test_vld1q_lane_s64(i64* %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vld1q_lane_s64:
 ; CHECK: ld1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
-  %0 = load i64* %a, align 8
+  %0 = load i64, i64* %a, align 8
   %vld1_lane = insertelement <2 x i64> %b, i64 %0, i32 1
   ret <2 x i64> %vld1_lane
 }
@@ -305,7 +305,7 @@ define <4 x float> @test_vld1q_lane_f32(float* %a, <4 x float> %b) {
 ; CHECK-LABEL: test_vld1q_lane_f32:
 ; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
-  %0 = load float* %a, align 4
+  %0 = load float, float* %a, align 4
   %vld1_lane = insertelement <4 x float> %b, float %0, i32 3
   ret <4 x float> %vld1_lane
 }
@@ -314,7 +314,7 @@ define <2 x double> @test_vld1q_lane_f64(double* %a, <2 x double> %b) {
 ; CHECK-LABEL: test_vld1q_lane_f64:
 ; CHECK: ld1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
-  %0 = load double* %a, align 8
+  %0 = load double, double* %a, align 8
   %vld1_lane = insertelement <2 x double> %b, double %0, i32 1
   ret <2 x double> %vld1_lane
 }
@@ -323,7 +323,7 @@ define <8 x i8> @test_vld1_lane_s8(i8* %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vld1_lane_s8:
 ; CHECK: ld1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
-  %0 = load i8* %a, align 1
+  %0 = load i8, i8* %a, align 1
   %vld1_lane = insertelement <8 x i8> %b, i8 %0, i32 7
   ret <8 x i8> %vld1_lane
 }
@@ -332,7 +332,7 @@ define <4 x i16> @test_vld1_lane_s16(i16* %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vld1_lane_s16:
 ; CHECK: ld1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
-  %0 = load i16* %a, align 2
+  %0 = load i16, i16* %a, align 2
   %vld1_lane = insertelement <4 x i16> %b, i16 %0, i32 3
   ret <4 x i16> %vld1_lane
 }
@@ -341,7 +341,7 @@ define <2 x i32> @test_vld1_lane_s32(i32* %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vld1_lane_s32:
 ; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %vld1_lane = insertelement <2 x i32> %b, i32 %0, i32 1
   ret <2 x i32> %vld1_lane
 }
@@ -350,7 +350,7 @@ define <1 x i64> @test_vld1_lane_s64(i64* %a, <1 x i64> %b) {
 ; CHECK-LABEL: test_vld1_lane_s64:
 ; CHECK: ldr {{d[0-9]+}}, [x0]
 entry:
-  %0 = load i64* %a, align 8
+  %0 = load i64, i64* %a, align 8
   %vld1_lane = insertelement <1 x i64> undef, i64 %0, i32 0
   ret <1 x i64> %vld1_lane
 }
@@ -359,7 +359,7 @@ define <2 x float> @test_vld1_lane_f32(float* %a, <2 x float> %b) {
 ; CHECK-LABEL: test_vld1_lane_f32:
 ; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
-  %0 = load float* %a, align 4
+  %0 = load float, float* %a, align 4
   %vld1_lane = insertelement <2 x float> %b, float %0, i32 1
   ret <2 x float> %vld1_lane
 }
@@ -368,7 +368,7 @@ define <1 x double> @test_vld1_lane_f64(double* %a, <1 x double> %b) {
 ; CHECK-LABEL: test_vld1_lane_f64:
 ; CHECK: ldr {{d[0-9]+}}, [x0]
 entry:
-  %0 = load double* %a, align 8
+  %0 = load double, double* %a, align 8
   %vld1_lane = insertelement <1 x double> undef, double %0, i32 0
   ret <1 x double> %vld1_lane
 }
diff --git a/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll b/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll
index 74e3af8206f5..c739e9dcd906 100644
--- a/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll
+++ b/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll
@@ -50,9 +50,15 @@ define <1 x double> @test_select_v1i1_2(<1 x i64> %v1, <1 x i64> %v2, <1 x doubl
   ret <1 x double> %res
 }
 
+; For v1i64, it's not clear which of the vector or scalar compare is better.
+; Let's stick to the vector form, like for all other vector selects fed by a
+; scalar setcc.  If anything, it exposes more ILP.
 define <1 x i64> @test_select_v1i1_3(i64 %lhs, i64 %rhs, <1 x i64> %v3) {
 ; CHECK-LABEL: test_select_v1i1_3:
-; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK: fmov d{{[0-9]+}}, x{{[0-9]+}}
+; CHECK: fmov d{{[0-9]+}}, x{{[0-9]+}}
+; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
   %tst = icmp eq i64 %lhs, %rhs
   %evil = insertelement <1 x i1> undef, i1 %tst, i32 0
   %res = select <1 x i1> %evil, <1 x i64> zeroinitializer, <1 x i64> %v3
diff --git a/test/CodeGen/AArch64/arm64-neon-v8.1a.ll b/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
new file mode 100644
index 000000000000..51ed8a13cd2e
--- /dev/null
+++ b/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
@@ -0,0 +1,456 @@
+; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V8a
+; RUN: llc < %s -verify-machineinstrs -march=arm64 -mattr=+v8.1a -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V81a
+; RUN: llc < %s -verify-machineinstrs -march=arm64 -mattr=+v8.1a -aarch64-neon-syntax=apple | FileCheck %s --check-prefix=CHECK-V81a-apple
+
+declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)
+declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>)
+declare i32 @llvm.aarch64.neon.sqrdmulh.i32(i32, i32)
+declare i16 @llvm.aarch64.neon.sqrdmulh.i16(i16, i16)
+
+declare <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16>, <8 x i16>)
+declare <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)
+declare i32 @llvm.aarch64.neon.sqadd.i32(i32, i32)
+declare i16 @llvm.aarch64.neon.sqadd.i16(i16, i16)
+
+declare <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16>, <8 x i16>)
+declare <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)
+declare i32 @llvm.aarch64.neon.sqsub.i32(i32, i32)
+declare i16 @llvm.aarch64.neon.sqsub.i16(i16, i16)
+
+;-----------------------------------------------------------------------------
+; RDMA Vector
+; test for SIMDThreeSameVectorSQRDMLxHTiedHS
+
+define <4 x i16> @test_sqrdmlah_v4i16(<4 x i16> %acc, <4 x i16> %mhs, <4 x i16> %rhs) {
+; CHECK-LABEL: test_sqrdmlah_v4i16:
+   %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %mhs,  <4 x i16> %rhs)
+   %retval =  call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %acc,  <4 x i16> %prod)
+; CHECK-V8a:        sqrdmulh    v1.4h, v1.4h, v2.4h
+; CHECK-V81a:       sqrdmlah    v0.4h, v1.4h, v2.4h
+; CHECK-V81a-apple: sqrdmlah.4h v0,    v1,    v2
+   ret <4 x i16> %retval
+}
+
+define <8 x i16> @test_sqrdmlah_v8i16(<8 x i16> %acc, <8 x i16> %mhs, <8 x i16> %rhs) {
+; CHECK-LABEL: test_sqrdmlah_v8i16:
+   %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
+   %retval =  call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %acc, <8 x i16> %prod)
+; CHECK-V8a:        sqrdmulh    v1.8h, v1.8h, v2.8h
+; CHECK-V81a:       sqrdmlah    v0.8h, v1.8h, v2.8h
+; CHECK-V81a-apple: sqrdmlah.8h v0, v1, v2
+   ret <8 x i16> %retval
+}
+
+define <2 x i32> @test_sqrdmlah_v2i32(<2 x i32> %acc, <2 x i32> %mhs, <2 x i32> %rhs) {
+; CHECK-LABEL: test_sqrdmlah_v2i32:
+   %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs)
+   %retval =  call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %acc, <2 x i32> %prod)
+; CHECK-V8a:        sqrdmulh    v1.2s, v1.2s, v2.2s
+; CHECK-V81a:       sqrdmlah    v0.2s, v1.2s, v2.2s
+; CHECK-V81a-apple: sqrdmlah.2s v0,    v1,    v2
+   ret <2 x i32> %retval
+}
+
+define <4 x i32> @test_sqrdmlah_v4i32(<4 x i32> %acc, <4 x i32> %mhs, <4 x i32> %rhs) {
+; CHECK-LABEL: test_sqrdmlah_v4i32:
+   %prod = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs)
+   %retval =  call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %acc, <4 x i32> %prod)
+; CHECK-V81:        sqrdmulh    v1.4s, v1.4s, v2.4s
+; CHECK-V81a:       sqrdmlah    v0.4s, v1.4s, v2.4s
+; CHECK-V81a-apple: sqrdmlah.4s v0,    v1,    v2
+   ret <4 x i32> %retval
+}
+
+define <4 x i16> @test_sqrdmlsh_v4i16(<4 x i16> %acc, <4 x i16> %mhs, <4 x i16> %rhs) {
+; CHECK-LABEL: test_sqrdmlsh_v4i16:
+   %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %mhs,  <4 x i16> %rhs)
+   %retval =  call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %acc, <4 x i16> %prod)
+; CHECK-V8a:        sqrdmulh    v1.4h, v1.4h, v2.4h
+; CHECK-V81a:       sqrdmlsh    v0.4h, v1.4h, v2.4h
+; CHECK-V81a-apple: sqrdmlsh.4h v0,    v1,    v2
+   ret <4 x i16> %retval
+}
+
+define <8 x i16> @test_sqrdmlsh_v8i16(<8 x i16> %acc, <8 x i16> %mhs, <8 x i16> %rhs) {
+; CHECK-LABEL: test_sqrdmlsh_v8i16:
+   %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
+   %retval =  call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %acc, <8 x i16> %prod)
+; CHECK-V8a:        sqrdmulh    v1.8h, v1.8h, v2.8h
+; CHECK-V81a:       sqrdmlsh    v0.8h, v1.8h, v2.8h
+; CHECK-V81a-apple: sqrdmlsh.8h v0,    v1,    v2
+   ret <8 x i16> %retval
+}
+
+define <2 x i32> @test_sqrdmlsh_v2i32(<2 x i32> %acc, <2 x i32> %mhs, <2 x i32> %rhs) {
+; CHECK-LABEL: test_sqrdmlsh_v2i32:
+   %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs)
+   %retval =  call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %acc, <2 x i32> %prod)
+; CHECK-V8a:        sqrdmulh    v1.2s, v1.2s, v2.2s
+; CHECK-V81a:       sqrdmlsh    v0.2s, v1.2s, v2.2s
+; CHECK-V81a-apple: sqrdmlsh.2s v0,    v1,    v2
+   ret <2 x i32> %retval
+}
+
+define <4 x i32> @test_sqrdmlsh_v4i32(<4 x i32> %acc, <4 x i32> %mhs, <4 x i32> %rhs) {
+; CHECK-LABEL: test_sqrdmlsh_v4i32:
+   %prod = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs)
+   %retval =  call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %acc, <4 x i32> %prod)
+; CHECK-V8a:        sqrdmulh    v1.4s, v1.4s, v2.4s
+; CHECK-V81a:       sqrdmlsh    v0.4s, v1.4s, v2.4s
+; CHECK-V81a-apple: sqrdmlsh.4s v0,    v1,    v2
+   ret <4 x i32> %retval
+}
+
+;-----------------------------------------------------------------------------
+; RDMA Vector, by element
+; tests for vXiYY_indexed in SIMDIndexedSQRDMLxHSDTied
+
+define <4 x i16> @test_sqrdmlah_lane_s16(<4 x i16> %acc, <4 x i16> %x, <4 x i16> %v) {
+; CHECK-LABEL: test_sqrdmlah_lane_s16:
+entry:
+  %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+  %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle)
+  %retval =  call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %acc, <4 x i16> %prod)
+; CHECK-V8a :       sqrdmulh    v1.4h, v1.4h, v2.h[3]
+; CHECK-V81a:       sqrdmlah    v0.4h, v1.4h, v2.h[3]
+; CHECK-V81a-apple: sqrdmlah.4h v0,    v1,    v2[3]
+  ret <4 x i16> %retval
+}
+
+define <8 x i16> @test_sqrdmlahq_lane_s16(<8 x i16> %acc, <8 x i16> %x, <8 x i16> %v) {
+; CHECK-LABEL: test_sqrdmlahq_lane_s16:
+entry:
+  %shuffle = shufflevector <8 x i16> %v, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
+  %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle)
+  %retval =  call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %acc, <8 x i16> %prod)
+; CHECK-V8a:        sqrdmulh    v1.8h, v1.8h, v2.h[2]
+; CHECK-V81a:       sqrdmlah    v0.8h, v1.8h, v2.h[2]
+; CHECK-V81a-apple: sqrdmlah.8h v0,    v1,    v2[2]
+  ret <8 x i16> %retval
+}
+
+define <2 x i32> @test_sqrdmlah_lane_s32(<2 x i32> %acc, <2 x i32> %x, <2 x i32> %v) {
+; CHECK-LABEL: test_sqrdmlah_lane_s32:
+entry:
+  %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
+  %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle)
+  %retval =  call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %acc, <2 x i32> %prod)
+; CHECK-V8a:        sqrdmulh    v1.2s, v1.2s, v2.s[1]
+; CHECK-V81a:       sqrdmlah    v0.2s, v1.2s, v2.s[1]
+; CHECK-V81a-apple: sqrdmlah.2s v0,    v1,    v2[1]
+  ret <2 x i32> %retval
+}
+
+define <4 x i32> @test_sqrdmlahq_lane_s32(<4 x i32> %acc,<4 x i32> %x, <4 x i32> %v) {
+; CHECK-LABEL: test_sqrdmlahq_lane_s32:
+entry:
+  %shuffle = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> zeroinitializer
+  %prod = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle)
+  %retval =  call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %acc, <4 x i32> %prod)
+; CHECK-V8a:        sqrdmulh    v1.4s, v1.4s, v2.s[0]
+; CHECK-V81a:       sqrdmlah    v0.4s, v1.4s, v2.s[0]
+; CHECK-V81a-apple: sqrdmlah.4s v0,    v1,    v2[0]
+  ret <4 x i32> %retval
+}
+
+define <4 x i16> @test_sqrdmlsh_lane_s16(<4 x i16> %acc, <4 x i16> %x, <4 x i16> %v) {
+; CHECK-LABEL: test_sqrdmlsh_lane_s16:
+entry:
+  %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+  %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle)
+  %retval =  call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %acc, <4 x i16> %prod)
+; CHECK-V8a:        sqrdmulh    v1.4h, v1.4h, v2.h[3]
+; CHECK-V81a:       sqrdmlsh    v0.4h, v1.4h, v2.h[3]
+; CHECK-V81a-apple: sqrdmlsh.4h v0,    v1,    v2[3]
+  ret <4 x i16> %retval
+}
+
+define <8 x i16> @test_sqrdmlshq_lane_s16(<8 x i16> %acc, <8 x i16> %x, <8 x i16> %v) {
+; CHECK-LABEL: test_sqrdmlshq_lane_s16:
+entry:
+  %shuffle = shufflevector <8 x i16> %v, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
+  %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle)
+  %retval =  call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %acc, <8 x i16> %prod)
+; CHECK-V8a:        sqrdmulh    v1.8h, v1.8h, v2.h[2]
+; CHECK-V81a:       sqrdmlsh    v0.8h, v1.8h, v2.h[2]
+; CHECK-V81a-apple: sqrdmlsh.8h v0,    v1,    v2[2]
+  ret <8 x i16> %retval
+}
+
+define <2 x i32> @test_sqrdmlsh_lane_s32(<2 x i32> %acc, <2 x i32> %x, <2 x i32> %v) {
+; CHECK-LABEL: test_sqrdmlsh_lane_s32:
+entry:
+  %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
+  %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle)
+  %retval =  call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %acc, <2 x i32> %prod)
+; CHECK-V8a:        sqrdmulh    v1.2s, v1.2s, v2.s[1]
+; CHECK-V81a:       sqrdmlsh    v0.2s, v1.2s, v2.s[1]
+; CHECK-V81a-apple: sqrdmlsh.2s v0,    v1,    v2[1]
+  ret <2 x i32> %retval
+}
+
+define <4 x i32> @test_sqrdmlshq_lane_s32(<4 x i32> %acc,<4 x i32> %x, <4 x i32> %v) {
+; CHECK-LABEL: test_sqrdmlshq_lane_s32:
+entry:
+  %shuffle = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> zeroinitializer
+  %prod = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle)
+  %retval =  call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %acc, <4 x i32> %prod)
+; CHECK-V8a:        sqrdmulh    v1.4s, v1.4s, v2.s[0]
+; CHECK-V81a:       sqrdmlsh    v0.4s, v1.4s, v2.s[0]
+; CHECK-V81a-apple: sqrdmlsh.4s v0,    v1,    v2[0]
+  ret <4 x i32> %retval
+}
+
+;-----------------------------------------------------------------------------
+; RDMA Vector, by element, extracted
+; i16 tests are for vXi16_indexed in SIMDIndexedSQRDMLxHSDTied, with IR in ACLE style
+; i32 tests are for   "def : Pat" in SIMDIndexedSQRDMLxHSDTied
+
+define i16 @test_sqrdmlah_extracted_lane_s16(i16 %acc,<4 x i16> %x, <4 x i16> %v) {
+; CHECK-LABEL: test_sqrdmlah_extracted_lane_s16:
+entry:
+  %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 1,i32 1,i32 1,i32 1>
+  %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle)
+  %acc_vec = insertelement <4 x i16> undef, i16 %acc, i64 0
+  %retval_vec =  call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %acc_vec, <4 x i16> %prod)
+  %retval = extractelement <4 x i16> %retval_vec, i64 0
+; CHECK-V8a:        sqrdmulh    {{v[0-9]+}}.4h, v0.4h, v1.h[1]
+; CHECK-V81a:       sqrdmlah    {{v[2-9]+}}.4h, v0.4h, v1.h[1]
+; CHECK-V81a-apple: sqrdmlah.4h {{v[2-9]+}},    v0,    v1[1]
+  ret i16 %retval
+}
+
+define i16 @test_sqrdmlahq_extracted_lane_s16(i16 %acc,<8 x i16> %x, <8 x i16> %v) {
+; CHECK-LABEL: test_sqrdmlahq_extracted_lane_s16:
+entry:
+  %shuffle = shufflevector <8 x i16> %v, <8 x i16> undef, <8 x i32> <i32 1,i32 1,i32 1,i32 1, i32 1,i32 1,i32 1,i32 1>
+  %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle)
+  %acc_vec = insertelement <8 x i16> undef, i16 %acc, i64 0
+  %retval_vec =  call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %acc_vec, <8 x i16> %prod)
+  %retval = extractelement <8 x i16> %retval_vec, i64 0
+; CHECK-V8a:        sqrdmulh    {{v[0-9]+}}.8h, v0.8h, v1.h[1]
+; CHECK-V81a:       sqrdmlah    {{v[2-9]+}}.8h, v0.8h, v1.h[1]
+; CHECK-V81a-apple: sqrdmlah.8h {{v[2-9]+}},    v0,    v1[1]
+  ret i16 %retval
+}
+
+define i32 @test_sqrdmlah_extracted_lane_s32(i32 %acc,<2 x i32> %x, <2 x i32> %v) {
+; CHECK-LABEL: test_sqrdmlah_extracted_lane_s32:
+entry:
+  %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> zeroinitializer
+  %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle)
+  %extract = extractelement <2 x i32> %prod, i64 0
+  %retval =  call i32 @llvm.aarch64.neon.sqadd.i32(i32 %acc, i32 %extract)
+; CHECK-V8a:        sqrdmulh    v0.2s, v0.2s, v1.s[0]
+; CHECK-V81a:       sqrdmlah    v2.2s, v0.2s, v1.s[0]
+; CHECK-V81a-apple: sqrdmlah.2s v2,    v0,    v1[0]
+  ret i32 %retval
+}
+
+define i32 @test_sqrdmlahq_extracted_lane_s32(i32 %acc,<4 x i32> %x, <4 x i32> %v) {
+; CHECK-LABEL: test_sqrdmlahq_extracted_lane_s32:
+entry:
+  %shuffle = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> zeroinitializer
+  %prod = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle)
+  %extract = extractelement <4 x i32> %prod, i64 0
+  %retval =  call i32 @llvm.aarch64.neon.sqadd.i32(i32 %acc, i32 %extract)
+; CHECK-V8a:        sqrdmulh    v0.4s, v0.4s, v1.s[0]
+; CHECK-V81a:       sqrdmlah    v2.4s, v0.4s, v1.s[0]
+; CHECK-V81a-apple: sqrdmlah.4s v2,    v0,    v1[0]
+  ret i32 %retval
+}
+
+define i16 @test_sqrdmlsh_extracted_lane_s16(i16 %acc,<4 x i16> %x, <4 x i16> %v) {
+; CHECK-LABEL: test_sqrdmlsh_extracted_lane_s16:
+entry:
+  %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 1,i32 1,i32 1,i32 1>
+  %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle)
+  %acc_vec = insertelement <4 x i16> undef, i16 %acc, i64 0
+  %retval_vec =  call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %acc_vec, <4 x i16> %prod)
+  %retval = extractelement <4 x i16> %retval_vec, i64 0
+; CHECK-V8a:        sqrdmulh    {{v[0-9]+}}.4h, v0.4h, v1.h[1]
+; CHECK-V81a:       sqrdmlsh    {{v[2-9]+}}.4h, v0.4h, v1.h[1]
+; CHECK-V81a-apple: sqrdmlsh.4h {{v[2-9]+}},    v0,    v1[1]
+  ret i16 %retval
+}
+
+define i16 @test_sqrdmlshq_extracted_lane_s16(i16 %acc,<8 x i16> %x, <8 x i16> %v) {
+; CHECK-LABEL: test_sqrdmlshq_extracted_lane_s16:
+entry:
+  %shuffle = shufflevector <8 x i16> %v, <8 x i16> undef, <8 x i32> <i32 1,i32 1,i32 1,i32 1, i32 1,i32 1,i32 1,i32 1>
+  %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle)
+  %acc_vec = insertelement <8 x i16> undef, i16 %acc, i64 0
+  %retval_vec =  call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %acc_vec, <8 x i16> %prod)
+  %retval = extractelement <8 x i16> %retval_vec, i64 0
+; CHECK-V8a:        sqrdmulh    {{v[0-9]+}}.8h, v0.8h, v1.h[1]
+; CHECK-V81a:       sqrdmlsh    {{v[2-9]+}}.8h, v0.8h, v1.h[1]
+; CHECK-V81a-apple: sqrdmlsh.8h {{v[2-9]+}},    v0,    v1[1]
+  ret i16 %retval
+}
+
+define i32 @test_sqrdmlsh_extracted_lane_s32(i32 %acc,<2 x i32> %x, <2 x i32> %v) {
+; CHECK-LABEL: test_sqrdmlsh_extracted_lane_s32:
+entry:
+  %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> zeroinitializer
+  %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle)
+  %extract = extractelement <2 x i32> %prod, i64 0
+  %retval =  call i32 @llvm.aarch64.neon.sqsub.i32(i32 %acc, i32 %extract)
+; CHECK-V8a:        sqrdmulh    v0.2s, v0.2s, v1.s[0]
+; CHECK-V81a:       sqrdmlsh    v2.2s, v0.2s, v1.s[0]
+; CHECK-V81a-apple: sqrdmlsh.2s v2,    v0,    v1[0]
+  ret i32 %retval
+}
+
+define i32 @test_sqrdmlshq_extracted_lane_s32(i32 %acc,<4 x i32> %x, <4 x i32> %v) {
+; CHECK-LABEL: test_sqrdmlshq_extracted_lane_s32:
+entry:
+  %shuffle = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> zeroinitializer
+  %prod = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle)
+  %extract = extractelement <4 x i32> %prod, i64 0
+  %retval =  call i32 @llvm.aarch64.neon.sqsub.i32(i32 %acc, i32 %extract)
+; CHECK-V8a:        sqrdmulh    v0.4s, v0.4s, v1.s[0]
+; CHECK-V81a:       sqrdmlsh    v2.4s, v0.4s, v1.s[0]
+; CHECK-V81a-apple: sqrdmlsh.4s v2,    v0,    v1[0]
+  ret i32 %retval
+}
+
+;-----------------------------------------------------------------------------
+; RDMA Scalar
+; test for "def : Pat" near SIMDThreeScalarHSTied in AArch64InstInfo.td
+
+define i16 @test_sqrdmlah_v1i16(i16 %acc, i16 %x, i16 %y) {
+; CHECK-LABEL: test_sqrdmlah_v1i16:
+  %x_vec = insertelement <4 x i16> undef, i16 %x, i64 0
+  %y_vec = insertelement <4 x i16> undef, i16 %y, i64 0
+  %prod_vec = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %x_vec,  <4 x i16> %y_vec)
+  %acc_vec = insertelement <4 x i16> undef, i16 %acc, i64 0
+  %retval_vec =  call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %acc_vec,  <4 x i16> %prod_vec)
+  %retval = extractelement <4 x i16> %retval_vec, i64 0
+; CHECK-V8a:        sqrdmulh    {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK-V81a:       sqrdmlah    {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK-V81a-apple: sqrdmlah.4h {{v[0-9]+}},    {{v[0-9]+}},    {{v[0-9]+}}
+  ret i16 %retval
+}
+
+define i32 @test_sqrdmlah_v1i32(i32 %acc, i32 %x, i32 %y) {
+; CHECK-LABEL: test_sqrdmlah_v1i32:
+  %x_vec = insertelement <4 x i32> undef, i32 %x, i64 0
+  %y_vec = insertelement <4 x i32> undef, i32 %y, i64 0
+  %prod_vec = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %x_vec,  <4 x i32> %y_vec)
+  %acc_vec = insertelement <4 x i32> undef, i32 %acc, i64 0
+  %retval_vec =  call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %acc_vec,  <4 x i32> %prod_vec)
+  %retval = extractelement <4 x i32> %retval_vec, i64 0
+; CHECK-V8a:        sqrdmulh    {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK-V81a:       sqrdmlah    {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK-V81a-apple: sqrdmlah.4s {{v[0-9]+}},    {{v[0-9]+}},    {{v[0-9]+}}
+  ret i32 %retval
+}
+
+
+define i16 @test_sqrdmlsh_v1i16(i16 %acc, i16 %x, i16 %y) {
+; CHECK-LABEL: test_sqrdmlsh_v1i16:
+  %x_vec = insertelement <4 x i16> undef, i16 %x, i64 0
+  %y_vec = insertelement <4 x i16> undef, i16 %y, i64 0
+  %prod_vec = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %x_vec,  <4 x i16> %y_vec)
+  %acc_vec = insertelement <4 x i16> undef, i16 %acc, i64 0
+  %retval_vec =  call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %acc_vec,  <4 x i16> %prod_vec)
+  %retval = extractelement <4 x i16> %retval_vec, i64 0
+; CHECK-V8a:        sqrdmulh    {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK-V81a:       sqrdmlsh    {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK-V81a-apple: sqrdmlsh.4h {{v[0-9]+}},    {{v[0-9]+}},    {{v[0-9]+}}
+  ret i16 %retval
+}
+
+define i32 @test_sqrdmlsh_v1i32(i32 %acc, i32 %x, i32 %y) {
+; CHECK-LABEL: test_sqrdmlsh_v1i32:
+  %x_vec = insertelement <4 x i32> undef, i32 %x, i64 0
+  %y_vec = insertelement <4 x i32> undef, i32 %y, i64 0
+  %prod_vec = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %x_vec,  <4 x i32> %y_vec)
+  %acc_vec = insertelement <4 x i32> undef, i32 %acc, i64 0
+  %retval_vec =  call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %acc_vec,  <4 x i32> %prod_vec)
+  %retval = extractelement <4 x i32> %retval_vec, i64 0
+; CHECK-V8a:        sqrdmulh    {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK-V81a:       sqrdmlsh    {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK-V81a-apple: sqrdmlsh.4s {{v[0-9]+}},    {{v[0-9]+}},    {{v[0-9]+}}
+  ret i32 %retval
+}
+define i32 @test_sqrdmlah_i32(i32 %acc, i32 %mhs, i32 %rhs) {
+; CHECK-LABEL: test_sqrdmlah_i32:
+  %prod = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %mhs,  i32 %rhs)
+  %retval =  call i32 @llvm.aarch64.neon.sqadd.i32(i32 %acc,  i32 %prod)
+; CHECK-V8a:        sqrdmulh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-V81a:       sqrdmlah {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-V81a-apple: sqrdmlah {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+  ret i32 %retval
+}
+
+define i32 @test_sqrdmlsh_i32(i32 %acc, i32 %mhs, i32 %rhs) {
+; CHECK-LABEL: test_sqrdmlsh_i32:
+  %prod = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %mhs,  i32 %rhs)
+  %retval =  call i32 @llvm.aarch64.neon.sqsub.i32(i32 %acc,  i32 %prod)
+; CHECK-V8a:        sqrdmulh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-V81a:       sqrdmlsh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-V81a-apple: sqrdmlsh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+  ret i32 %retval
+}
+
+;-----------------------------------------------------------------------------
+; RDMA Scalar, by element
+; i16 tests are performed via tests in above chapter, with IR in ACLE style
+; i32 tests are for i32_indexed in SIMDIndexedSQRDMLxHSDTied
+
+define i16 @test_sqrdmlah_extract_i16(i16 %acc, i16 %x, <4 x i16> %y_vec) {
+; CHECK-LABEL: test_sqrdmlah_extract_i16:
+  %shuffle = shufflevector <4 x i16> %y_vec, <4 x i16> undef, <4 x i32> <i32 1,i32 1,i32 1,i32 1>
+  %x_vec = insertelement <4 x i16> undef, i16 %x, i64 0
+  %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %x_vec, <4 x i16> %shuffle)
+  %acc_vec = insertelement <4 x i16> undef, i16 %acc, i64 0
+  %retval_vec =  call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %acc_vec, <4 x i16> %prod)
+  %retval = extractelement <4 x i16> %retval_vec, i32 0
+; CHECK-V8a:        sqrdmulh    {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, v0.h[1]
+; CHECK-V81a:       sqrdmlah    {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, v0.h[1]
+; CHECK-V81a-apple: sqrdmlah.4h {{v[0-9]+}},    {{v[0-9]+}}, v0[1]
+  ret i16 %retval
+}
+
+define i32 @test_sqrdmlah_extract_i32(i32 %acc, i32 %mhs, <4 x i32> %rhs) {
+; CHECK-LABEL: test_sqrdmlah_extract_i32:
+  %extract = extractelement <4 x i32> %rhs, i32 3
+  %prod = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %mhs,  i32 %extract)
+  %retval =  call i32 @llvm.aarch64.neon.sqadd.i32(i32 %acc,  i32 %prod)
+; CHECK-V8a:        sqrdmulh   {{s[0-9]+}}, {{s[0-9]+}}, v0.s[3]
+; CHECK-V81a:       sqrdmlah   {{s[0-9]+}}, {{s[0-9]+}}, v0.s[3]
+; CHECK-V81a-apple: sqrdmlah.s {{s[0-9]+}}, {{s[0-9]+}}, v0[3]
+  ret i32 %retval
+}
+
+define i16 @test_sqrdmlshq_extract_i16(i16 %acc, i16 %x, <8 x i16> %y_vec) {
+; CHECK-LABEL: test_sqrdmlshq_extract_i16:
+  %shuffle = shufflevector <8 x i16> %y_vec, <8 x i16> undef, <8 x i32> <i32 1,i32 1,i32 1,i32 1,i32 1,i32 1,i32 1,i32 1>
+  %x_vec = insertelement <8 x i16> undef, i16 %x, i64 0
+  %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %x_vec, <8 x i16> %shuffle)
+  %acc_vec = insertelement <8 x i16> undef, i16 %acc, i64 0
+  %retval_vec =  call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %acc_vec, <8 x i16> %prod)
+  %retval = extractelement <8 x i16> %retval_vec, i32 0
+; CHECK-V8a:        sqrdmulh    {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, v0.h[1]
+; CHECK-V81a:       sqrdmlsh    {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, v0.h[1]
+; CHECK-V81a-apple: sqrdmlsh.8h {{v[0-9]+}},    {{v[0-9]+}}, v0[1]
+  ret i16 %retval
+}
+
+define i32 @test_sqrdmlsh_extract_i32(i32 %acc, i32 %mhs, <4 x i32> %rhs) {
+; CHECK-LABEL: test_sqrdmlsh_extract_i32:
+  %extract = extractelement <4 x i32> %rhs, i32 3
+  %prod = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %mhs,  i32 %extract)
+  %retval =  call i32 @llvm.aarch64.neon.sqsub.i32(i32 %acc,  i32 %prod)
+; CHECK-V8a:        sqrdmulh   {{s[0-9]+}}, {{s[0-9]+}}, v0.s[3]
+; CHECK-V81a:       sqrdmlsh   {{s[0-9]+}}, {{s[0-9]+}}, v0.s[3]
+; CHECK-V81a-apple: sqrdmlsh.s {{s[0-9]+}}, {{s[0-9]+}}, v0[3]
+  ret i32 %retval
+}
diff --git a/test/CodeGen/AArch64/arm64-patchpoint-scratch-regs.ll b/test/CodeGen/AArch64/arm64-patchpoint-scratch-regs.ll
index d39722b9c8a5..2651f119412b 100644
--- a/test/CodeGen/AArch64/arm64-patchpoint-scratch-regs.ll
+++ b/test/CodeGen/AArch64/arm64-patchpoint-scratch-regs.ll
@@ -7,9 +7,9 @@
 ; CHECK-NEXT: Ltmp
 ; CHECK-NEXT: nop
 define void @clobberScratch(i32* %p) {
-  %v = load i32* %p
+  %v = load i32, i32* %p
   tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 5, i32 20, i8* null, i32 0, i32* %p, i32 %v)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 5, i32 20, i8* null, i32 0, i32* %p, i32 %v)
   store i32 %v, i32* %p
   ret void
 }
diff --git a/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll b/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
index 8f79f80ba33d..b8236c5b2479 100644
--- a/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
+++ b/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
@@ -23,9 +23,9 @@ entry:
 ; FAST-NEXT:   movk  x16, #0xbeef
 ; FAST-NEXT:   blr x16
   %resolveCall2 = inttoptr i64 281474417671919 to i8*
-  %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2)
+  %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2)
   %resolveCall3 = inttoptr i64 244837814038255 to i8*
-  tail call webkit_jscc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveCall3, i32 2, i64 %p4, i64 %result)
+  tail call webkit_jscc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveCall3, i32 2, i64 %p4, i64 %result)
   ret void
 }
 
@@ -59,7 +59,7 @@ entry:
 ; FAST-NEXT:   movk  x16, #0xbeef
 ; FAST-NEXT:   blr x16
   %call = inttoptr i64 281474417671919 to i8*
-  %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6)
+  %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6)
   ret i64 %result
 }
 
@@ -101,7 +101,7 @@ entry:
 ; FAST-NEXT:   movk  x16, #0xbeef
 ; FAST-NEXT:   blr x16
   %call = inttoptr i64 281474417671919 to i8*
-  %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10)
+  %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10)
   ret i64 %result
 }
 
diff --git a/test/CodeGen/AArch64/arm64-patchpoint.ll b/test/CodeGen/AArch64/arm64-patchpoint.ll
index 278cba5d9f49..d9ec7e50ff80 100644
--- a/test/CodeGen/AArch64/arm64-patchpoint.ll
+++ b/test/CodeGen/AArch64/arm64-patchpoint.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone                             < %s | FileCheck %s
-; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -fast-isel -fast-isel-abort < %s | FileCheck %s
+; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
 
 ; Trivial patchpoint codegen
 ;
@@ -16,9 +16,9 @@ entry:
 ; CHECK-NEXT:  blr  x16
 ; CHECK:       ret
   %resolveCall2 = inttoptr i64 244837814094590 to i8*
-  %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
+  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
   %resolveCall3 = inttoptr i64 244837814094591 to i8*
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 3, i32 20, i8* %resolveCall3, i32 2, i64 %p1, i64 %result)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 20, i8* %resolveCall3, i32 2, i64 %p1, i64 %result)
   ret i64 %result
 }
 
@@ -38,7 +38,7 @@ entry:
   store i64 11, i64* %metadata
   store i64 12, i64* %metadata
   store i64 13, i64* %metadata
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
   ret void
 }
 
@@ -50,15 +50,15 @@ define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, i64* %tmp33, i64
 entry:
   %tmp80 = add i64 %tmp79, -16
   %tmp81 = inttoptr i64 %tmp80 to i64*
-  %tmp82 = load i64* %tmp81, align 8
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 14, i32 8, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82)
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 15, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
-  %tmp83 = load i64* %tmp33, align 8
+  %tmp82 = load i64, i64* %tmp81, align 8
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 8, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 15, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
+  %tmp83 = load i64, i64* %tmp33, align 8
   %tmp84 = add i64 %tmp83, -24
   %tmp85 = inttoptr i64 %tmp84 to i64*
-  %tmp86 = load i64* %tmp85, align 8
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 17, i32 8, i64 %arg, i64 %tmp10, i64 %tmp86)
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 18, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
+  %tmp86 = load i64, i64* %tmp85, align 8
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 17, i32 8, i64 %arg, i64 %tmp10, i64 %tmp86)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 18, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
   ret i64 10
 }
 
@@ -74,7 +74,7 @@ entry:
 ; CHECK-NEXT: nop
 ; CHECK-NEXT: ldp
 ; CHECK-NEXT: ret
-  %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* null, i32 2, i64 %p1, i64 %p2)
+  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* null, i32 2, i64 %p1, i64 %p2)
   ret void
 }
 
diff --git a/test/CodeGen/AArch64/arm64-pic-local-symbol.ll b/test/CodeGen/AArch64/arm64-pic-local-symbol.ll
index 627e741fc32d..dae243e8da2c 100644
--- a/test/CodeGen/AArch64/arm64-pic-local-symbol.ll
+++ b/test/CodeGen/AArch64/arm64-pic-local-symbol.ll
@@ -7,7 +7,7 @@ define i32 @get() {
 ; CHECK: get:
 ; CHECK: adrp x{{[0-9]+}}, a
 ; CHECK-NEXT: ldr w{{[0-9]+}}, [x{{[0-9]}}, :lo12:a]
-  %res = load i32* @a, align 4
+  %res = load i32, i32* @a, align 4
   ret i32 %res
 }
 
@@ -15,7 +15,7 @@ define void @foo() nounwind {
 ; CHECK: foo:
 ; CHECK: adrp x{{[0-9]}}, .L.str
 ; CHECK-NEXT: add x{{[0-9]}}, x{{[0-9]}}, :lo12:.L.str
-  tail call void @bar(i8* getelementptr inbounds ([6 x i8]* @.str, i64 0, i64 0))
+  tail call void @bar(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0))
   ret void
 }
 
diff --git a/test/CodeGen/AArch64/arm64-platform-reg.ll b/test/CodeGen/AArch64/arm64-platform-reg.ll
index b0d3ee0ff8a3..60672aa38486 100644
--- a/test/CodeGen/AArch64/arm64-platform-reg.ll
+++ b/test/CodeGen/AArch64/arm64-platform-reg.ll
@@ -11,7 +11,7 @@
 @var = global [30 x i64] zeroinitializer
 
 define void @keep_live() {
-  %val = load volatile [30 x i64]* @var
+  %val = load volatile [30 x i64], [30 x i64]* @var
   store volatile [30 x i64] %val, [30 x i64]* @var
 
 ; CHECK: ldr x18
diff --git a/test/CodeGen/AArch64/arm64-popcnt.ll b/test/CodeGen/AArch64/arm64-popcnt.ll
index 117ab3a5e05a..b0b529a13f41 100644
--- a/test/CodeGen/AArch64/arm64-popcnt.ll
+++ b/test/CodeGen/AArch64/arm64-popcnt.ll
@@ -4,7 +4,8 @@
 define i32 @cnt32_advsimd(i32 %x) nounwind readnone {
   %cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
   ret i32 %cnt
-; CHECK: fmov	s0, w0
+; CHECK: ubfx	x{{[0-9]+}}
+; CHECK: fmov	d0, x{{[0-9]+}}
 ; CHECK: cnt.8b	v0, v0
 ; CHECK: uaddlv.8b	h0, v0
 ; CHECK: fmov w0, s0
@@ -15,7 +16,24 @@ define i32 @cnt32_advsimd(i32 %x) nounwind readnone {
 ; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0x33333333
 ; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0xf0f0f0f
 ; CHECK-NONEON: mul
+}
 
+define i32 @cnt32_advsimd_2(<2 x i32> %x) {
+  %1 = extractelement <2 x i32> %x, i64 0
+  %2 = tail call i32 @llvm.ctpop.i32(i32 %1)
+  ret i32 %2
+; CHECK: fmov	w0, s0
+; CHECK: fmov	d0, x0
+; CHECK: cnt.8b	v0, v0
+; CHECK: uaddlv.8b	h0, v0
+; CHECK: fmov w0, s0
+; CHECK: ret
+; CHECK-NONEON-LABEL: cnt32_advsimd_2
+; CHECK-NONEON-NOT: 8b
+; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0x55555555
+; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0x33333333
+; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0xf0f0f0f
+; CHECK-NONEON: mul
 }
 
 define i64 @cnt64_advsimd(i64 %x) nounwind readnone {
diff --git a/test/CodeGen/AArch64/arm64-prefetch.ll b/test/CodeGen/AArch64/arm64-prefetch.ll
index aac3515c4278..bdeacb231fdd 100644
--- a/test/CodeGen/AArch64/arm64-prefetch.ll
+++ b/test/CodeGen/AArch64/arm64-prefetch.ll
@@ -35,79 +35,79 @@ entry:
   ; CHECK: prfum pstl1keep
   call void @llvm.prefetch(i8* %tmp, i32 1, i32 3, i32 1)
 
-  %tmp1 = load i32* %j.addr, align 4, !tbaa !0
+  %tmp1 = load i32, i32* %j.addr, align 4, !tbaa !0
   %add = add nsw i32 %tmp1, %i
   %idxprom = sext i32 %add to i64
-  %tmp2 = load i32** @a, align 8, !tbaa !3
-  %arrayidx = getelementptr inbounds i32* %tmp2, i64 %idxprom
+  %tmp2 = load i32*, i32** @a, align 8, !tbaa !3
+  %arrayidx = getelementptr inbounds i32, i32* %tmp2, i64 %idxprom
   %tmp3 = bitcast i32* %arrayidx to i8*
 
   ; CHECK: prfm pldl1strm
   call void @llvm.prefetch(i8* %tmp3, i32 0, i32 0, i32 1)
-  %tmp4 = load i32** @a, align 8, !tbaa !3
-  %arrayidx3 = getelementptr inbounds i32* %tmp4, i64 %idxprom
+  %tmp4 = load i32*, i32** @a, align 8, !tbaa !3
+  %arrayidx3 = getelementptr inbounds i32, i32* %tmp4, i64 %idxprom
   %tmp5 = bitcast i32* %arrayidx3 to i8*
 
   ; CHECK: prfm pldl3keep
   call void @llvm.prefetch(i8* %tmp5, i32 0, i32 1, i32 1)
-  %tmp6 = load i32** @a, align 8, !tbaa !3
-  %arrayidx6 = getelementptr inbounds i32* %tmp6, i64 %idxprom
+  %tmp6 = load i32*, i32** @a, align 8, !tbaa !3
+  %arrayidx6 = getelementptr inbounds i32, i32* %tmp6, i64 %idxprom
   %tmp7 = bitcast i32* %arrayidx6 to i8*
 
   ; CHECK: prfm pldl2keep
   call void @llvm.prefetch(i8* %tmp7, i32 0, i32 2, i32 1)
-  %tmp8 = load i32** @a, align 8, !tbaa !3
-  %arrayidx9 = getelementptr inbounds i32* %tmp8, i64 %idxprom
+  %tmp8 = load i32*, i32** @a, align 8, !tbaa !3
+  %arrayidx9 = getelementptr inbounds i32, i32* %tmp8, i64 %idxprom
   %tmp9 = bitcast i32* %arrayidx9 to i8*
 
   ; CHECK: prfm pldl1keep
   call void @llvm.prefetch(i8* %tmp9, i32 0, i32 3, i32 1)
-  %tmp10 = load i32** @a, align 8, !tbaa !3
-  %arrayidx12 = getelementptr inbounds i32* %tmp10, i64 %idxprom
+  %tmp10 = load i32*, i32** @a, align 8, !tbaa !3
+  %arrayidx12 = getelementptr inbounds i32, i32* %tmp10, i64 %idxprom
   %tmp11 = bitcast i32* %arrayidx12 to i8*
 
 
   ; CHECK: prfm plil1strm
   call void @llvm.prefetch(i8* %tmp11, i32 0, i32 0, i32 0)
-  %tmp12 = load i32** @a, align 8, !tbaa !3
-  %arrayidx15 = getelementptr inbounds i32* %tmp12, i64 %idxprom
+  %tmp12 = load i32*, i32** @a, align 8, !tbaa !3
+  %arrayidx15 = getelementptr inbounds i32, i32* %tmp12, i64 %idxprom
   %tmp13 = bitcast i32* %arrayidx3 to i8*
 
   ; CHECK: prfm plil3keep
   call void @llvm.prefetch(i8* %tmp13, i32 0, i32 1, i32 0)
-  %tmp14 = load i32** @a, align 8, !tbaa !3
-  %arrayidx18 = getelementptr inbounds i32* %tmp14, i64 %idxprom
+  %tmp14 = load i32*, i32** @a, align 8, !tbaa !3
+  %arrayidx18 = getelementptr inbounds i32, i32* %tmp14, i64 %idxprom
   %tmp15 = bitcast i32* %arrayidx6 to i8*
 
   ; CHECK: prfm plil2keep
   call void @llvm.prefetch(i8* %tmp15, i32 0, i32 2, i32 0)
-  %tmp16 = load i32** @a, align 8, !tbaa !3
-  %arrayidx21 = getelementptr inbounds i32* %tmp16, i64 %idxprom
+  %tmp16 = load i32*, i32** @a, align 8, !tbaa !3
+  %arrayidx21 = getelementptr inbounds i32, i32* %tmp16, i64 %idxprom
   %tmp17 = bitcast i32* %arrayidx9 to i8*
 
   ; CHECK: prfm plil1keep
   call void @llvm.prefetch(i8* %tmp17, i32 0, i32 3, i32 0)
-  %tmp18 = load i32** @a, align 8, !tbaa !3
-  %arrayidx24 = getelementptr inbounds i32* %tmp18, i64 %idxprom
+  %tmp18 = load i32*, i32** @a, align 8, !tbaa !3
+  %arrayidx24 = getelementptr inbounds i32, i32* %tmp18, i64 %idxprom
   %tmp19 = bitcast i32* %arrayidx12 to i8*
 
 
   ; CHECK: prfm pstl1strm
   call void @llvm.prefetch(i8* %tmp19, i32 1, i32 0, i32 1)
-  %tmp20 = load i32** @a, align 8, !tbaa !3
-  %arrayidx27 = getelementptr inbounds i32* %tmp20, i64 %idxprom
+  %tmp20 = load i32*, i32** @a, align 8, !tbaa !3
+  %arrayidx27 = getelementptr inbounds i32, i32* %tmp20, i64 %idxprom
   %tmp21 = bitcast i32* %arrayidx15 to i8*
 
   ; CHECK: prfm pstl3keep
   call void @llvm.prefetch(i8* %tmp21, i32 1, i32 1, i32 1)
-  %tmp22 = load i32** @a, align 8, !tbaa !3
-  %arrayidx30 = getelementptr inbounds i32* %tmp22, i64 %idxprom
+  %tmp22 = load i32*, i32** @a, align 8, !tbaa !3
+  %arrayidx30 = getelementptr inbounds i32, i32* %tmp22, i64 %idxprom
   %tmp23 = bitcast i32* %arrayidx18 to i8*
 
   ; CHECK: prfm pstl2keep
   call void @llvm.prefetch(i8* %tmp23, i32 1, i32 2, i32 1)
-  %tmp24 = load i32** @a, align 8, !tbaa !3
-  %arrayidx33 = getelementptr inbounds i32* %tmp24, i64 %idxprom
+  %tmp24 = load i32*, i32** @a, align 8, !tbaa !3
+  %arrayidx33 = getelementptr inbounds i32, i32* %tmp24, i64 %idxprom
   %tmp25 = bitcast i32* %arrayidx21 to i8*
 
   ; CHECK: prfm pstl1keep
diff --git a/test/CodeGen/AArch64/arm64-promote-const.ll b/test/CodeGen/AArch64/arm64-promote-const.ll
index 94fd8e33b892..0be2f5c08c00 100644
--- a/test/CodeGen/AArch64/arm64-promote-const.ll
+++ b/test/CodeGen/AArch64/arm64-promote-const.ll
@@ -40,7 +40,7 @@ define <16 x i8> @test2(<16 x i8> %arg) {
 entry:
 ; PROMOTED-LABEL: test2:
 ; In stress mode, constant vector are promoted
-; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1:__PromotedConst[0-9]+]]@PAGE
+; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1:__PromotedConst.[0-9]+]]@PAGE
 ; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
 ; Destination register is defined by ABI
 ; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
@@ -63,49 +63,23 @@ entry:
   ret <16 x i8> %add.i9
 }
 
-; Two different uses of the sane constant in two different basic blocks,
+; Two different uses of the same constant in two different basic blocks,
 ; one dominates the other
 define <16 x i8> @test3(<16 x i8> %arg, i32 %path) {
 ; PROMOTED-LABEL: test3:
 ; In stress mode, constant vector are promoted
 ; Since, the constant is the same as the previous function,
 ; the same address must be used
-; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE
-; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
-; Destination register is defined by ABI
-; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
-; PROMOTED-NEXT: cbnz w0, [[LABEL:LBB.*]]
-; Next BB
-; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV2:__PromotedConst[0-9]+]]@PAGE
-; PROMOTED-NEXT: ldr q[[REGNUM]], {{\[}}[[PAGEADDR]], [[CSTV2]]@PAGEOFF]
-; Next BB
-; PROMOTED-NEXT: [[LABEL]]:
-; PROMOTED-NEXT: mul.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]
-; PROMOTED-NEXT: add.16b v0, v0, [[DESTV]]
-; PROMOTED-NEXT: ret
+; PROMOTED: ldr
+; PROMOTED: ldr
+; PROMOTED-NOT: ldr
+; PROMOTED: ret
 
 ; REGULAR-LABEL: test3:
-; Regular mode does not elimitate common sub expression by its own.
-; In other words, the same loads appears several times.
-; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL1:lCP.*]]@PAGE
-; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL1]]@PAGEOFF]
-; Destination register is defined by ABI
-; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]]
-; REGULAR-NEXT: cbz w0, [[LABELelse:LBB.*]]
-; Next BB
-; Redundant load
-; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL1]]@PAGE
-; REGULAR-NEXT: ldr q[[REGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL1]]@PAGEOFF]
-; REGULAR-NEXT: b [[LABELend:LBB.*]]
-; Next BB
-; REGULAR-NEXT: [[LABELelse]]
-; REGULAR-NEXT: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL2:lCP.*]]@PAGE
-; REGULAR-NEXT: ldr q[[REGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL2]]@PAGEOFF]
-; Next BB
-; REGULAR-NEXT: [[LABELend]]:
-; REGULAR-NEXT: mul.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]
-; REGULAR-NEXT: add.16b v0, v0, [[DESTV]]
-; REGULAR-NEXT: ret
+; REGULAR: ldr
+; REGULAR: ldr
+; REGULAR-NOT: ldr
+; REGULAR: ret
 entry:
   %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
   %tobool = icmp eq i32 %path, 0
@@ -132,33 +106,14 @@ define <16 x i8> @test4(<16 x i8> %arg, i32 %path) {
 ; In stress mode, constant vector are promoted
 ; Since, the constant is the same as the previous function,
 ; the same address must be used
-; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE
-; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
-; Destination register is defined by ABI
-; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
-; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]]
-; Next BB
-; PROMOTED: mul.16b v0, v0, v[[REGNUM]]
-; Next BB
-; PROMOTED-NEXT: [[LABEL]]:
-; PROMOTED-NEXT: ret
-
+; PROMOTED: ldr
+; PROMOTED-NOT: ldr
+; PROMOTED: ret
 
 ; REGULAR-LABEL: test4:
-; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL3:lCP.*]]@PAGE
-; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL3]]@PAGEOFF]
-; Destination register is defined by ABI
-; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]]
-; REGULAR-NEXT: cbz w0, [[LABEL:LBB.*]]
-; Next BB
-; Redundant expression
-; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL3]]@PAGE
-; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL3]]@PAGEOFF]
-; Destination register is defined by ABI
-; REGULAR-NEXT: mul.16b v0, v0, v[[REGNUM]]
-; Next BB
-; REGULAR-NEXT: [[LABEL]]:
-; REGULAR-NEXT: ret
+; REGULAR: ldr
+; REGULAR-NOT: ldr
+; REGULAR: ret
 entry:
   %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
   %tobool = icmp eq i32 %path, 0
@@ -180,39 +135,13 @@ define <16 x i8> @test5(<16 x i8> %arg, i32 %path) {
 ; In stress mode, constant vector are promoted
 ; Since, the constant is the same as the previous function,
 ; the same address must be used
-; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE
-; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
-; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]]
-; Next BB
-; PROMOTED: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]
-; PROMOTED-NEXT: mul.16b v[[REGNUM]], [[DESTV]], v[[REGNUM]]
-; Next BB
-; PROMOTED-NEXT: [[LABEL]]:
-; PROMOTED-NEXT: mul.16b [[TMP1:v[0-9]+]], v[[REGNUM]], v[[REGNUM]]
-; PROMOTED-NEXT: mul.16b [[TMP2:v[0-9]+]], [[TMP1]], [[TMP1]]
-; PROMOTED-NEXT: mul.16b [[TMP3:v[0-9]+]], [[TMP2]], [[TMP2]]
-; PROMOTED-NEXT: mul.16b v0, [[TMP3]], [[TMP3]]
-; PROMOTED-NEXT: ret
+; PROMOTED: ldr
+; PROMOTED-NOT: ldr
+; PROMOTED: ret
 
 ; REGULAR-LABEL: test5:
-; REGULAR: cbz w0, [[LABELelse:LBB.*]]
-; Next BB
-; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
-; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
-; REGULAR-NEXT: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]
-; REGULAR-NEXT: mul.16b v[[DESTREGNUM:[0-9]+]], [[DESTV]], v[[REGNUM]]
-; REGULAR-NEXT: b [[LABELend:LBB.*]]
-; Next BB
-; REGULAR-NEXT: [[LABELelse]]
-; REGULAR-NEXT: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
-; REGULAR-NEXT: ldr q[[DESTREGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
-; Next BB
-; REGULAR-NEXT: [[LABELend]]:
-; REGULAR-NEXT: mul.16b [[TMP1:v[0-9]+]], v[[DESTREGNUM]], v[[DESTREGNUM]]
-; REGULAR-NEXT: mul.16b [[TMP2:v[0-9]+]], [[TMP1]], [[TMP1]]
-; REGULAR-NEXT: mul.16b [[TMP3:v[0-9]+]], [[TMP2]], [[TMP2]]
-; REGULAR-NEXT: mul.16b v0, [[TMP3]], [[TMP3]]
-; REGULAR-NEXT: ret
+; REGULAR: ldr
+; REGULAR: ret
 entry:
   %tobool = icmp eq i32 %path, 0
   br i1 %tobool, label %if.end, label %if.then
diff --git a/test/CodeGen/AArch64/arm64-redzone.ll b/test/CodeGen/AArch64/arm64-redzone.ll
index 9b0c384c4d9e..837249cb26c6 100644
--- a/test/CodeGen/AArch64/arm64-redzone.ll
+++ b/test/CodeGen/AArch64/arm64-redzone.ll
@@ -9,10 +9,10 @@ define i32 @foo(i32 %a, i32 %b) nounwind ssp {
   %x = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
   store i32 %b, i32* %b.addr, align 4
-  %tmp = load i32* %a.addr, align 4
-  %tmp1 = load i32* %b.addr, align 4
+  %tmp = load i32, i32* %a.addr, align 4
+  %tmp1 = load i32, i32* %b.addr, align 4
   %add = add nsw i32 %tmp, %tmp1
   store i32 %add, i32* %x, align 4
-  %tmp2 = load i32* %x, align 4
+  %tmp2 = load i32, i32* %x, align 4
   ret i32 %tmp2
 }
diff --git a/test/CodeGen/AArch64/arm64-register-offset-addressing.ll b/test/CodeGen/AArch64/arm64-register-offset-addressing.ll
index 045712bea6ac..7078ffca5218 100644
--- a/test/CodeGen/AArch64/arm64-register-offset-addressing.ll
+++ b/test/CodeGen/AArch64/arm64-register-offset-addressing.ll
@@ -5,8 +5,8 @@ define i8 @test_64bit_add(i16* %a, i64 %b) {
 ; CHECK: lsl [[REG:x[0-9]+]], x1, #1
 ; CHECK: ldrb w0, [x0, [[REG]]]
 ; CHECK: ret
-  %tmp1 = getelementptr inbounds i16* %a, i64 %b
-  %tmp2 = load i16* %tmp1
+  %tmp1 = getelementptr inbounds i16, i16* %a, i64 %b
+  %tmp2 = load i16, i16* %tmp1
   %tmp3 = trunc i16 %tmp2 to i8
   ret i8 %tmp3
 }
@@ -18,8 +18,8 @@ define void @ldst_8bit(i8* %base, i64 %offset) minsize {
 
    %off32.sext.tmp = shl i64 %offset, 32
    %off32.sext = ashr i64 %off32.sext.tmp, 32
-   %addr8_sxtw = getelementptr i8* %base, i64 %off32.sext
-   %val8_sxtw = load volatile i8* %addr8_sxtw
+   %addr8_sxtw = getelementptr i8, i8* %base, i64 %off32.sext
+   %val8_sxtw = load volatile i8, i8* %addr8_sxtw
    %val32_signed = sext i8 %val8_sxtw to i32
    store volatile i32 %val32_signed, i32* @var_32bit
 ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw]
@@ -28,7 +28,7 @@ define void @ldst_8bit(i8* %base, i64 %offset) minsize {
   %offset_uxtw = and i64 %offset, 4294967295
   %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw
   %addr_uxtw = inttoptr i64 %addrint1_uxtw to i8*
-  %val8_uxtw = load volatile i8* %addr_uxtw
+  %val8_uxtw = load volatile i8, i8* %addr_uxtw
   %newval8 = add i8 %val8_uxtw, 1
   store volatile i8 %newval8, i8* @var_8bit
 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw]
@@ -44,7 +44,7 @@ define void @ldst_16bit(i16* %base, i64 %offset) minsize {
   %offset_uxtw = and i64 %offset, 4294967295
   %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw
   %addr_uxtw = inttoptr i64 %addrint1_uxtw to i16*
-  %val8_uxtw = load volatile i16* %addr_uxtw
+  %val8_uxtw = load volatile i16, i16* %addr_uxtw
   %newval8 = add i16 %val8_uxtw, 1
   store volatile i16 %newval8, i16* @var_16bit
 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw]
@@ -54,7 +54,7 @@ define void @ldst_16bit(i16* %base, i64 %offset) minsize {
   %offset_sxtw = ashr i64 %offset_sxtw.tmp, 32
   %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw
   %addr_sxtw = inttoptr i64 %addrint_sxtw to i16*
-  %val16_sxtw = load volatile i16* %addr_sxtw
+  %val16_sxtw = load volatile i16, i16* %addr_sxtw
   %val64_signed = sext i16 %val16_sxtw to i64
   store volatile i64 %val64_signed, i64* @var_64bit
 ; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw]
@@ -65,7 +65,7 @@ define void @ldst_16bit(i16* %base, i64 %offset) minsize {
   %offset2_uxtwN = shl i64 %offset_uxtwN, 1
   %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN
   %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i16*
-  %val32 = load volatile i32* @var_32bit
+  %val32 = load volatile i32, i32* @var_32bit
   %val16_trunc32 = trunc i32 %val32 to i16
   store volatile i16 %val16_trunc32, i16* %addr_uxtwN
 ; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #1]
@@ -79,7 +79,7 @@ define void @ldst_32bit(i32* %base, i64 %offset) minsize {
   %offset_uxtw = and i64 %offset, 4294967295
   %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw
   %addr_uxtw = inttoptr i64 %addrint1_uxtw to i32*
-  %val32_uxtw = load volatile i32* %addr_uxtw
+  %val32_uxtw = load volatile i32, i32* %addr_uxtw
   %newval32 = add i32 %val32_uxtw, 1
   store volatile i32 %newval32, i32* @var_32bit
 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw]
@@ -89,7 +89,7 @@ define void @ldst_32bit(i32* %base, i64 %offset) minsize {
   %offset_sxtw = ashr i64 %offset_sxtw.tmp, 32
   %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw
   %addr_sxtw = inttoptr i64 %addrint_sxtw to i32*
-  %val32_sxtw = load volatile i32* %addr_sxtw
+  %val32_sxtw = load volatile i32, i32* %addr_sxtw
   %val64_signed = sext i32 %val32_sxtw to i64
   store volatile i64 %val64_signed, i64* @var_64bit
 ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw]
@@ -100,7 +100,7 @@ define void @ldst_32bit(i32* %base, i64 %offset) minsize {
   %offset2_uxtwN = shl i64 %offset_uxtwN, 2
   %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN
   %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i32*
-  %val32 = load volatile i32* @var_32bit
+  %val32 = load volatile i32, i32* @var_32bit
   store volatile i32 %val32, i32* %addr_uxtwN
 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #2]
    ret void
@@ -113,7 +113,7 @@ define void @ldst_64bit(i64* %base, i64 %offset) minsize {
   %offset_uxtw = and i64 %offset, 4294967295
   %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw
   %addr_uxtw = inttoptr i64 %addrint1_uxtw to i64*
-  %val64_uxtw = load volatile i64* %addr_uxtw
+  %val64_uxtw = load volatile i64, i64* %addr_uxtw
   %newval8 = add i64 %val64_uxtw, 1
   store volatile i64 %newval8, i64* @var_64bit
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw]
@@ -123,7 +123,7 @@ define void @ldst_64bit(i64* %base, i64 %offset) minsize {
   %offset_sxtw = ashr i64 %offset_sxtw.tmp, 32
   %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw
   %addr_sxtw = inttoptr i64 %addrint_sxtw to i64*
-  %val64_sxtw = load volatile i64* %addr_sxtw
+  %val64_sxtw = load volatile i64, i64* %addr_sxtw
   store volatile i64 %val64_sxtw, i64* @var_64bit
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw]
 
@@ -133,7 +133,7 @@ define void @ldst_64bit(i64* %base, i64 %offset) minsize {
   %offset2_uxtwN = shl i64 %offset_uxtwN, 3
   %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN
   %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i64*
-  %val64 = load volatile i64* @var_64bit
+  %val64 = load volatile i64, i64* @var_64bit
   store volatile i64 %val64, i64* %addr_uxtwN
 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #3]
    ret void
diff --git a/test/CodeGen/AArch64/arm64-regress-interphase-shift.ll b/test/CodeGen/AArch64/arm64-regress-interphase-shift.ll
index fec89334801e..d376aaf56817 100644
--- a/test/CodeGen/AArch64/arm64-regress-interphase-shift.ll
+++ b/test/CodeGen/AArch64/arm64-regress-interphase-shift.ll
@@ -11,7 +11,7 @@
 define void @foo(i64* nocapture %d) {
 ; CHECK-LABEL: foo:
 ; CHECK: rorv
-  %tmp = load i64* undef, align 8
+  %tmp = load i64, i64* undef, align 8
   %sub397 = sub i64 0, %tmp
   %and398 = and i64 %sub397, 4294967295
   %shr404 = lshr i64 %and398, 0
diff --git a/test/CodeGen/AArch64/arm64-return-vector.ll b/test/CodeGen/AArch64/arm64-return-vector.ll
index 9457d8bc6d07..3262c91c04df 100644
--- a/test/CodeGen/AArch64/arm64-return-vector.ll
+++ b/test/CodeGen/AArch64/arm64-return-vector.ll
@@ -6,6 +6,6 @@ define <2 x double> @test(<2 x double>* %p) nounwind {
 ; CHECK: test
 ; CHECK: ldr q0, [x0]
 ; CHECK: ret
-  %tmp1 = load <2 x double>* %p, align 16
+  %tmp1 = load <2 x double>, <2 x double>* %p, align 16
   ret <2 x double> %tmp1
 }
diff --git a/test/CodeGen/AArch64/arm64-rev.ll b/test/CodeGen/AArch64/arm64-rev.ll
index 30d9f4f3e670..74356d76d3c8 100644
--- a/test/CodeGen/AArch64/arm64-rev.ll
+++ b/test/CodeGen/AArch64/arm64-rev.ll
@@ -64,7 +64,7 @@ entry:
 define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64D8:
 ;CHECK: rev64.8b
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
 	ret <8 x i8> %tmp2
 }
@@ -72,7 +72,7 @@ define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
 define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64D16:
 ;CHECK: rev64.4h
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
 	ret <4 x i16> %tmp2
 }
@@ -80,7 +80,7 @@ define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
 define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64D32:
 ;CHECK: rev64.2s
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
 	ret <2 x i32> %tmp2
 }
@@ -88,7 +88,7 @@ define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
 define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64Df:
 ;CHECK: rev64.2s
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
 	ret <2 x float> %tmp2
 }
@@ -96,7 +96,7 @@ define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
 define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64Q8:
 ;CHECK: rev64.16b
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
 	ret <16 x i8> %tmp2
 }
@@ -104,7 +104,7 @@ define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
 define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64Q16:
 ;CHECK: rev64.8h
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
 	ret <8 x i16> %tmp2
 }
@@ -112,7 +112,7 @@ define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
 define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64Q32:
 ;CHECK: rev64.4s
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
 	ret <4 x i32> %tmp2
 }
@@ -120,7 +120,7 @@ define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
 define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64Qf:
 ;CHECK: rev64.4s
-	%tmp1 = load <4 x float>* %A
+	%tmp1 = load <4 x float>, <4 x float>* %A
 	%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
 	ret <4 x float> %tmp2
 }
@@ -128,7 +128,7 @@ define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
 define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: test_vrev32D8:
 ;CHECK: rev32.8b
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
 	ret <8 x i8> %tmp2
 }
@@ -136,7 +136,7 @@ define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
 define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: test_vrev32D16:
 ;CHECK: rev32.4h
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
 	ret <4 x i16> %tmp2
 }
@@ -144,7 +144,7 @@ define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
 define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: test_vrev32Q8:
 ;CHECK: rev32.16b
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
 	ret <16 x i8> %tmp2
 }
@@ -152,7 +152,7 @@ define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
 define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: test_vrev32Q16:
 ;CHECK: rev32.8h
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
 	ret <8 x i16> %tmp2
 }
@@ -160,7 +160,7 @@ define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
 define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: test_vrev16D8:
 ;CHECK: rev16.8b
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
 	ret <8 x i8> %tmp2
 }
@@ -168,7 +168,7 @@ define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
 define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: test_vrev16Q8:
 ;CHECK: rev16.16b
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
 	ret <16 x i8> %tmp2
 }
@@ -178,7 +178,7 @@ define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
 define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64D8_undef:
 ;CHECK: rev64.8b
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
 	ret <8 x i8> %tmp2
 }
@@ -186,7 +186,7 @@ define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
 define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: test_vrev32Q16_undef:
 ;CHECK: rev32.8h
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
 	ret <8 x i16> %tmp2
 }
@@ -199,7 +199,7 @@ define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst
 ; CHECK: st1.h
 entry:
   %0 = bitcast <4 x i16>* %source to <8 x i16>*
-  %tmp2 = load <8 x i16>* %0, align 4
+  %tmp2 = load <8 x i16>, <8 x i16>* %0, align 4
   %tmp3 = extractelement <8 x i16> %tmp2, i32 6
   %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0
   %tmp9 = extractelement <8 x i16> %tmp2, i32 5
@@ -215,9 +215,9 @@ define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest
 ; CHECK: rev64.4s
 entry:
   %0 = bitcast float* %source to <4 x float>*
-  %tmp2 = load <4 x float>* %0, align 4
+  %tmp2 = load <4 x float>, <4 x float>* %0, align 4
   %tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0>
-  %arrayidx8 = getelementptr inbounds <4 x float>* %dest, i32 11
+  %arrayidx8 = getelementptr inbounds <4 x float>, <4 x float>* %dest, i32 11
   store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4
   ret void
 }
diff --git a/test/CodeGen/AArch64/arm64-scaled_iv.ll b/test/CodeGen/AArch64/arm64-scaled_iv.ll
index 63428df9610c..24f04f44c3ea 100644
--- a/test/CodeGen/AArch64/arm64-scaled_iv.ll
+++ b/test/CodeGen/AArch64/arm64-scaled_iv.ll
@@ -17,15 +17,15 @@ for.body:                                         ; preds = %for.body, %entry
 ; CHECK-NOT: phi
   %indvars.iv = phi i64 [ 1, %entry ], [ %indvars.iv.next, %for.body ]
   %tmp = add nsw i64 %indvars.iv, -1
-  %arrayidx = getelementptr inbounds double* %b, i64 %tmp
-  %tmp1 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %b, i64 %tmp
+  %tmp1 = load double, double* %arrayidx, align 8
 ; The induction variable should carry the scaling factor: 1 * 8 = 8.
-; CHECK: [[IVNEXT]] = add nuw i64 [[IV]], 8
+; CHECK: [[IVNEXT]] = add nuw nsw i64 [[IV]], 8
   %indvars.iv.next = add i64 %indvars.iv, 1
-  %arrayidx2 = getelementptr inbounds double* %c, i64 %indvars.iv.next
-  %tmp2 = load double* %arrayidx2, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %c, i64 %indvars.iv.next
+  %tmp2 = load double, double* %arrayidx2, align 8
   %mul = fmul double %tmp1, %tmp2
-  %arrayidx4 = getelementptr inbounds double* %a, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds double, double* %a, i64 %indvars.iv
   store double %mul, double* %arrayidx4, align 8
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
 ; Comparison should be 19 * 8 = 152.
diff --git a/test/CodeGen/AArch64/arm64-scvt.ll b/test/CodeGen/AArch64/arm64-scvt.ll
index 8baaf22238d3..fc64d7bfda68 100644
--- a/test/CodeGen/AArch64/arm64-scvt.ll
+++ b/test/CodeGen/AArch64/arm64-scvt.ll
@@ -7,7 +7,7 @@ entry:
 ; CHECK-LABEL: t1:
 ; CHECK: ldr s0, [x0]
 ; CHECK: scvtf s0, s0
-  %tmp1 = load i32* %src, align 4
+  %tmp1 = load i32, i32* %src, align 4
   %tmp2 = sitofp i32 %tmp1 to float
   ret float %tmp2
 }
@@ -17,7 +17,7 @@ entry:
 ; CHECK-LABEL: t2:
 ; CHECK: ldr s0, [x0]
 ; CHECK: ucvtf s0, s0
-  %tmp1 = load i32* %src, align 4
+  %tmp1 = load i32, i32* %src, align 4
   %tmp2 = uitofp i32 %tmp1 to float
   ret float %tmp2
 }
@@ -27,7 +27,7 @@ entry:
 ; CHECK-LABEL: t3:
 ; CHECK: ldr d0, [x0]
 ; CHECK: scvtf d0, d0
-  %tmp1 = load i64* %src, align 4
+  %tmp1 = load i64, i64* %src, align 4
   %tmp2 = sitofp i64 %tmp1 to double
   ret double %tmp2
 }
@@ -37,7 +37,7 @@ entry:
 ; CHECK-LABEL: t4:
 ; CHECK: ldr d0, [x0]
 ; CHECK: ucvtf d0, d0
-  %tmp1 = load i64* %src, align 4
+  %tmp1 = load i64, i64* %src, align 4
   %tmp2 = uitofp i64 %tmp1 to double
   ret double %tmp2
 }
@@ -48,7 +48,7 @@ entry:
 ; CHECK-LABEL: t5:
 ; CHECK: ldr [[REG:w[0-9]+]], [x0]
 ; CHECK: scvtf d0, [[REG]]
-  %tmp1 = load i32* %src, align 4
+  %tmp1 = load i32, i32* %src, align 4
   %tmp2 = sitofp i32 %tmp1 to double
   ret double %tmp2
 }
@@ -75,8 +75,8 @@ define float @fct1(i8* nocapture %sp0) {
 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i8* %sp0, i64 1
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %addr = getelementptr i8, i8* %sp0, i64 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = uitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -88,8 +88,8 @@ define float @fct2(i16* nocapture %sp0) {
 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i16* %sp0, i64 1
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %addr = getelementptr i16, i16* %sp0, i64 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = uitofp i16 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -101,8 +101,8 @@ define float @fct3(i32* nocapture %sp0) {
 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i32* %sp0, i64 1
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %addr = getelementptr i32, i32* %sp0, i64 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = uitofp i32 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -115,8 +115,8 @@ define float @fct4(i64* nocapture %sp0) {
 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i64* %sp0, i64 1
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %addr = getelementptr i64, i64* %sp0, i64 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = uitofp i64 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -129,8 +129,8 @@ define float @fct5(i8* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i8* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %addr = getelementptr i8, i8* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = uitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -142,8 +142,8 @@ define float @fct6(i16* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i16* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %addr = getelementptr i16, i16* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = uitofp i16 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -155,8 +155,8 @@ define float @fct7(i32* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i32* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %addr = getelementptr i32, i32* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = uitofp i32 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -169,8 +169,8 @@ define float @fct8(i64* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i64* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %addr = getelementptr i64, i64* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = uitofp i64 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -184,8 +184,8 @@ define double @fct9(i8* nocapture %sp0) {
 ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i8* %sp0, i64 1
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %addr = getelementptr i8, i8* %sp0, i64 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = uitofp i8 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -197,8 +197,8 @@ define double @fct10(i16* nocapture %sp0) {
 ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i16* %sp0, i64 1
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %addr = getelementptr i16, i16* %sp0, i64 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = uitofp i16 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -210,8 +210,8 @@ define double @fct11(i32* nocapture %sp0) {
 ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i32* %sp0, i64 1
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %addr = getelementptr i32, i32* %sp0, i64 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = uitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -223,8 +223,8 @@ define double @fct12(i64* nocapture %sp0) {
 ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i64* %sp0, i64 1
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %addr = getelementptr i64, i64* %sp0, i64 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = uitofp i64 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -237,8 +237,8 @@ define double @fct13(i8* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i8* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %addr = getelementptr i8, i8* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = uitofp i8 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -250,8 +250,8 @@ define double @fct14(i16* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i16* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %addr = getelementptr i16, i16* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = uitofp i16 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -263,8 +263,8 @@ define double @fct15(i32* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i32* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %addr = getelementptr i32, i32* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = uitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -276,8 +276,8 @@ define double @fct16(i64* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i64* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %addr = getelementptr i64, i64* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = uitofp i64 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -293,7 +293,7 @@ entry:
   %bitcast = ptrtoint i8* %sp0 to i64
   %add = add i64 %bitcast, -1
   %addr = inttoptr i64 %add to i8*
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = uitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -307,7 +307,7 @@ define float @fct18(i16* nocapture %sp0) {
   %bitcast = ptrtoint i16* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i16*
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = uitofp i16 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -321,7 +321,7 @@ define float @fct19(i32* nocapture %sp0) {
   %bitcast = ptrtoint i32* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i32*
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = uitofp i32 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -336,7 +336,7 @@ define float @fct20(i64* nocapture %sp0) {
   %bitcast = ptrtoint i64* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i64*
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = uitofp i64 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -353,7 +353,7 @@ entry:
   %bitcast = ptrtoint i8* %sp0 to i64
   %add = add i64 %bitcast, -1
   %addr = inttoptr i64 %add to i8*
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = uitofp i8 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -367,7 +367,7 @@ define double @fct22(i16* nocapture %sp0) {
   %bitcast = ptrtoint i16* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i16*
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = uitofp i16 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -381,7 +381,7 @@ define double @fct23(i32* nocapture %sp0) {
   %bitcast = ptrtoint i32* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i32*
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = uitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -395,7 +395,7 @@ define double @fct24(i64* nocapture %sp0) {
   %bitcast = ptrtoint i64* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i64*
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = uitofp i64 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -415,8 +415,8 @@ define float @sfct1(i8* nocapture %sp0) {
 ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
 ; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i8* %sp0, i64 1
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %addr = getelementptr i8, i8* %sp0, i64 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -429,8 +429,8 @@ define float @sfct2(i16* nocapture %sp0) {
 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i16* %sp0, i64 1
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %addr = getelementptr i16, i16* %sp0, i64 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -442,8 +442,8 @@ define float @sfct3(i32* nocapture %sp0) {
 ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i32* %sp0, i64 1
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %addr = getelementptr i32, i32* %sp0, i64 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -456,8 +456,8 @@ define float @sfct4(i64* nocapture %sp0) {
 ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], x[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i64* %sp0, i64 1
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %addr = getelementptr i64, i64* %sp0, i64 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = sitofp i64 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -476,8 +476,8 @@ define float @sfct5(i8* nocapture %sp0, i64 %offset) {
 ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
 ; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i8* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %addr = getelementptr i8, i8* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -490,8 +490,8 @@ define float @sfct6(i16* nocapture %sp0, i64 %offset) {
 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i16* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %addr = getelementptr i16, i16* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -503,8 +503,8 @@ define float @sfct7(i32* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i32* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %addr = getelementptr i32, i32* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -517,8 +517,8 @@ define float @sfct8(i64* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], x[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i64* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %addr = getelementptr i64, i64* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = sitofp i64 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -531,8 +531,8 @@ define double @sfct9(i8* nocapture %sp0) {
 ; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i8* %sp0, i64 1
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %addr = getelementptr i8, i8* %sp0, i64 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -550,8 +550,8 @@ define double @sfct10(i16* nocapture %sp0) {
 ; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
 ; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i16* %sp0, i64 1
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %addr = getelementptr i16, i16* %sp0, i64 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -564,8 +564,8 @@ define double @sfct11(i32* nocapture %sp0) {
 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i32* %sp0, i64 1
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %addr = getelementptr i32, i32* %sp0, i64 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -577,8 +577,8 @@ define double @sfct12(i64* nocapture %sp0) {
 ; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i64* %sp0, i64 1
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %addr = getelementptr i64, i64* %sp0, i64 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = sitofp i64 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -591,8 +591,8 @@ define double @sfct13(i8* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i8* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %addr = getelementptr i8, i8* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -610,8 +610,8 @@ define double @sfct14(i16* nocapture %sp0, i64 %offset) {
 ; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
 ; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i16* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %addr = getelementptr i16, i16* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -624,8 +624,8 @@ define double @sfct15(i32* nocapture %sp0, i64 %offset) {
 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i32* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %addr = getelementptr i32, i32* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -637,8 +637,8 @@ define double @sfct16(i64* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i64* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %addr = getelementptr i64, i64* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = sitofp i64 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -660,7 +660,7 @@ entry:
   %bitcast = ptrtoint i8* %sp0 to i64
   %add = add i64 %bitcast, -1
   %addr = inttoptr i64 %add to i8*
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -675,7 +675,7 @@ define float @sfct18(i16* nocapture %sp0) {
   %bitcast = ptrtoint i16* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i16*
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -689,7 +689,7 @@ define float @sfct19(i32* nocapture %sp0) {
   %bitcast = ptrtoint i32* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i32*
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -704,7 +704,7 @@ define float @sfct20(i64* nocapture %sp0) {
   %bitcast = ptrtoint i64* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i64*
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = sitofp i64 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -721,7 +721,7 @@ entry:
   %bitcast = ptrtoint i8* %sp0 to i64
   %add = add i64 %bitcast, -1
   %addr = inttoptr i64 %add to i8*
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -741,7 +741,7 @@ define double @sfct22(i16* nocapture %sp0) {
   %bitcast = ptrtoint i16* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i16*
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -756,7 +756,7 @@ define double @sfct23(i32* nocapture %sp0) {
   %bitcast = ptrtoint i32* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i32*
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -770,7 +770,7 @@ define double @sfct24(i64* nocapture %sp0) {
   %bitcast = ptrtoint i64* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i64*
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = sitofp i64 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -787,7 +787,7 @@ entry:
   %bitcast = ptrtoint i8* %sp0 to i64
   %add = add i64 %bitcast, -1
   %addr = inttoptr i64 %add to i8*
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -799,8 +799,8 @@ define double @codesize_sfct11(i32* nocapture %sp0) minsize {
 ; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
-  %addr = getelementptr i32* %sp0, i64 1
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %addr = getelementptr i32, i32* %sp0, i64 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
diff --git a/test/CodeGen/AArch64/arm64-shrink-wrapping.ll b/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
new file mode 100644
index 000000000000..c1777513fa04
--- /dev/null
+++ b/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
@@ -0,0 +1,502 @@
+; RUN: llc %s -o - -enable-shrink-wrap=true | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
+; RUN: llc %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-apple-ios"
+
+
+; Initial motivating example: Simple diamond with a call just on one side.
+; CHECK-LABEL: foo:
+;
+; Compare the arguments and jump to exit.
+; No prologue needed.
+; ENABLE: cmp w0, w1
+; ENABLE-NEXT: b.ge [[EXIT_LABEL:LBB[0-9_]+]]
+;
+; Prologue code.
+; CHECK: stp [[SAVE_SP:x[0-9]+]], [[CSR:x[0-9]+]], [sp, #-16]!
+; CHECK-NEXT: mov [[SAVE_SP]], sp
+; CHECK-NEXT: sub sp, sp, #16
+;
+; Compare the arguments and jump to exit.
+; After the prologue is set.
+; DISABLE: cmp w0, w1
+; DISABLE-NEXT: b.ge [[EXIT_LABEL:LBB[0-9_]+]]
+;
+; Store %a in the alloca.
+; CHECK: stur w0, {{\[}}[[SAVE_SP]], #-4]
+; Set the alloca address in the second argument.
+; CHECK-NEXT: sub x1, [[SAVE_SP]], #4
+; Set the first argument to zero.
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: bl _doSomething
+; 
+; Without shrink-wrapping, epilogue is in the exit block.
+; DISABLE: [[EXIT_LABEL]]:
+; Epilogue code.
+; CHECK-NEXT: mov sp, [[SAVE_SP]]
+; CHECK-NEXT: ldp [[SAVE_SP]], [[CSR]], [sp], #16
+;
+; With shrink-wrapping, exit block is a simple return.
+; ENABLE: [[EXIT_LABEL]]:
+; CHECK-NEXT: ret
+define i32 @foo(i32 %a, i32 %b) {
+  %tmp = alloca i32, align 4
+  %tmp2 = icmp slt i32 %a, %b
+  br i1 %tmp2, label %true, label %false
+
+true:
+  store i32 %a, i32* %tmp, align 4
+  %tmp4 = call i32 @doSomething(i32 0, i32* %tmp)
+  br label %false
+
+false:
+  %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
+  ret i32 %tmp.0
+}
+
+; Function Attrs: optsize
+declare i32 @doSomething(i32, i32*)
+
+
+; Check that we do not perform the restore inside the loop whereas the save
+; is outside.
+; CHECK-LABEL: freqSaveAndRestoreOutsideLoop:
+;
+; Shrink-wrapping allows to skip the prologue in the else case.
+; ENABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; Prologue code.
+; CHECK: stp [[CSR1:x[0-9]+]], [[CSR2:x[0-9]+]], [sp, #-32]!
+; CHECK-NEXT: stp [[CSR3:x[0-9]+]], [[CSR4:x[0-9]+]], [sp, #16]
+; CHECK-NEXT: add [[NEW_SP:x[0-9]+]], sp, #16
+;
+; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; CHECK: mov [[SUM:w[0-9]+]], wzr
+; CHECK-NEXT: movz [[IV:w[0-9]+]], #0xa
+;
+; Next BB.
+; CHECK: [[LOOP:LBB[0-9_]+]]: ; %for.body
+; CHECK: bl _something
+; CHECK-NEXT: add [[SUM]], w0, [[SUM]]
+; CHECK-NEXT: sub [[IV]], [[IV]], #1
+; CHECK-NEXT: cbnz [[IV]], [[LOOP]]
+;
+; Next BB.
+; Copy SUM into the returned register + << 3.
+; CHECK: lsl w0, [[SUM]], #3
+;
+; Jump to epilogue.
+; DISABLE: b [[EPILOG_BB:LBB[0-9_]+]]
+;
+; DISABLE: [[ELSE_LABEL]]: ; %if.else
+; Shift second argument by one and store into returned register.
+; DISABLE: lsl w0, w1, #1
+; DISABLE: [[EPILOG_BB]]: ; %if.end
+;
+; Epilogue code.
+; CHECK: ldp [[CSR3]], [[CSR4]], [sp, #16]
+; CHECK-NEXT: ldp [[CSR1]], [[CSR2]], [sp], #32
+; CHECK-NEXT: ret
+;
+; ENABLE: [[ELSE_LABEL]]: ; %if.else
+; Shift second argument by one and store into returned register.
+; ENABLE: lsl w0, w1, #1
+; ENABLE: ret
+define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) {
+entry:
+  %tobool = icmp eq i32 %cond, 0
+  br i1 %tobool, label %if.else, label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %i.05 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
+  %sum.04 = phi i32 [ %add, %for.body ], [ 0, %entry ]
+  %call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)()
+  %add = add nsw i32 %call, %sum.04
+  %inc = add nuw nsw i32 %i.05, 1
+  %exitcond = icmp eq i32 %inc, 10
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  %shl = shl i32 %add, 3
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  %mul = shl nsw i32 %N, 1
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %for.end
+  %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
+  ret i32 %sum.1
+}
+
+declare i32 @something(...)
+
+; Check that we do not perform the shrink-wrapping inside the loop even
+; though that would be legal. The cost model must prevent that.
+; CHECK-LABEL: freqSaveAndRestoreOutsideLoop2:
+; Prologue code.
+; CHECK: stp [[CSR1:x[0-9]+]], [[CSR2:x[0-9]+]], [sp, #-32]!
+; CHECK-NEXT: stp [[CSR3:x[0-9]+]], [[CSR4:x[0-9]+]], [sp, #16]
+; CHECK-NEXT: add [[NEW_SP:x[0-9]+]], sp, #16
+; CHECK: mov [[SUM:w[0-9]+]], wzr
+; CHECK-NEXT: movz [[IV:w[0-9]+]], #0xa
+; Next BB.
+; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body
+; CHECK: bl _something
+; CHECK-NEXT: add [[SUM]], w0, [[SUM]]
+; CHECK-NEXT: sub [[IV]], [[IV]], #1
+; CHECK-NEXT: cbnz [[IV]], [[LOOP_LABEL]]
+; Next BB.
+; CHECK: ; %for.end
+; CHECK: mov w0, [[SUM]]
+; CHECK-NEXT: ldp [[CSR3]], [[CSR4]], [sp, #16]
+; CHECK-NEXT: ldp [[CSR1]], [[CSR2]], [sp], #32
+; CHECK-NEXT: ret
+define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.04 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %sum.03 = phi i32 [ 0, %entry ], [ %add, %for.body ]
+  %call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)()
+  %add = add nsw i32 %call, %sum.03
+  %inc = add nuw nsw i32 %i.04, 1
+  %exitcond = icmp eq i32 %inc, 10
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret i32 %add
+}
+
+; Check with a more complex case that we do not have save within the loop and
+; restore outside.
+; CHECK-LABEL: loopInfoSaveOutsideLoop:
+;
+; ENABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; Prologue code.
+; CHECK: stp [[CSR1:x[0-9]+]], [[CSR2:x[0-9]+]], [sp, #-32]!
+; CHECK-NEXT: stp [[CSR3:x[0-9]+]], [[CSR4:x[0-9]+]], [sp, #16]
+; CHECK-NEXT: add [[NEW_SP:x[0-9]+]], sp, #16
+;
+; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; CHECK: mov [[SUM:w[0-9]+]], wzr
+; CHECK-NEXT: movz [[IV:w[0-9]+]], #0xa
+;
+; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body
+; CHECK: bl _something
+; CHECK-NEXT: add [[SUM]], w0, [[SUM]]
+; CHECK-NEXT: sub [[IV]], [[IV]], #1
+; CHECK-NEXT: cbnz [[IV]], [[LOOP_LABEL]]
+; Next BB.
+; CHECK: bl _somethingElse
+; CHECK-NEXT: lsl w0, [[SUM]], #3
+;
+; Jump to epilogue.
+; DISABLE: b [[EPILOG_BB:LBB[0-9_]+]]
+;
+; DISABLE: [[ELSE_LABEL]]: ; %if.else
+; Shift second argument by one and store into returned register.
+; DISABLE: lsl w0, w1, #1
+; DISABLE: [[EPILOG_BB]]: ; %if.end
+; Epilogue code.
+; CHECK-NEXT: ldp [[CSR3]], [[CSR4]], [sp, #16]
+; CHECK-NEXT: ldp [[CSR1]], [[CSR2]], [sp], #32
+; CHECK-NEXT: ret
+;
+; ENABLE: [[ELSE_LABEL]]: ; %if.else
+; Shift second argument by one and store into returned register.
+; ENABLE: lsl w0, w1, #1
+; ENABLE: ret
+define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) {
+entry:
+  %tobool = icmp eq i32 %cond, 0
+  br i1 %tobool, label %if.else, label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %i.05 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
+  %sum.04 = phi i32 [ %add, %for.body ], [ 0, %entry ]
+  %call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)()
+  %add = add nsw i32 %call, %sum.04
+  %inc = add nuw nsw i32 %i.05, 1
+  %exitcond = icmp eq i32 %inc, 10
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  tail call void bitcast (void (...)* @somethingElse to void ()*)()
+  %shl = shl i32 %add, 3
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  %mul = shl nsw i32 %N, 1
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %for.end
+  %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
+  ret i32 %sum.1
+}
+
+declare void @somethingElse(...)
+
+; Check with a more complex case that we do not have restore within the loop and
+; save outside.
+; CHECK-LABEL: loopInfoRestoreOutsideLoop:
+;
+; ENABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; CHECK: stp [[CSR1:x[0-9]+]], [[CSR2:x[0-9]+]], [sp, #-32]!
+; CHECK-NEXT: stp [[CSR3:x[0-9]+]], [[CSR4:x[0-9]+]], [sp, #16]
+; CHECK-NEXT: add [[NEW_SP:x[0-9]+]], sp, #16
+;
+; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; CHECK: bl _somethingElse
+; CHECK-NEXT: mov [[SUM:w[0-9]+]], wzr
+; CHECK-NEXT: movz [[IV:w[0-9]+]], #0xa
+;
+; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body
+; CHECK: bl _something
+; CHECK-NEXT: add [[SUM]], w0, [[SUM]]
+; CHECK-NEXT: sub [[IV]], [[IV]], #1
+; CHECK-NEXT: cbnz [[IV]], [[LOOP_LABEL]]
+; Next BB.
+; CHECK: lsl w0, [[SUM]], #3
+;
+; Jump to epilogue.
+; DISABLE: b [[EPILOG_BB:LBB[0-9_]+]]
+;
+; DISABLE: [[ELSE_LABEL]]: ; %if.else
+; Shift second argument by one and store into returned register.
+; DISABLE: lsl w0, w1, #1
+; DISABLE: [[EPILOG_BB]]: ; %if.end
+; Epilogue code.
+; CHECK: ldp [[CSR3]], [[CSR4]], [sp, #16]
+; CHECK-NEXT: ldp [[CSR1]], [[CSR2]], [sp], #32
+; CHECK-NEXT: ret
+;
+; ENABLE: [[ELSE_LABEL]]: ; %if.else
+; Shift second argument by one and store into returned register.
+; ENABLE: lsl w0, w1, #1
+; ENABLE: ret
+define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) #0 {
+entry:
+  %tobool = icmp eq i32 %cond, 0
+  br i1 %tobool, label %if.else, label %if.then
+
+if.then:                                          ; preds = %entry
+  tail call void bitcast (void (...)* @somethingElse to void ()*)()
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %if.then
+  %i.05 = phi i32 [ 0, %if.then ], [ %inc, %for.body ]
+  %sum.04 = phi i32 [ 0, %if.then ], [ %add, %for.body ]
+  %call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)()
+  %add = add nsw i32 %call, %sum.04
+  %inc = add nuw nsw i32 %i.05, 1
+  %exitcond = icmp eq i32 %inc, 10
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  %shl = shl i32 %add, 3
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  %mul = shl nsw i32 %N, 1
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %for.end
+  %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
+  ret i32 %sum.1
+}
+
+; Check that we handle function with no frame information correctly.
+; CHECK-LABEL: emptyFrame:
+; CHECK: ; %entry
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
+define i32 @emptyFrame() {
+entry:
+  ret i32 0
+}
+
+; Check that we handle variadic function correctly.
+; CHECK-LABEL: variadicFunc:
+;
+; ENABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; Prologue code.
+; CHECK: sub sp, sp, #16
+; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; Sum is merged with the returned register.
+; CHECK: mov [[SUM:w0]], wzr
+; CHECK-NEXT: add [[VA_BASE:x[0-9]+]], sp, #16
+; CHECK-NEXT: str [[VA_BASE]], [sp, #8]
+; CHECK-NEXT: cmp w1, #1
+; CHECK-NEXT: b.lt [[IFEND_LABEL:LBB[0-9_]+]]
+;
+; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body
+; CHECK: ldr [[VA_ADDR:x[0-9]+]], [sp, #8]
+; CHECK-NEXT: add [[NEXT_VA_ADDR:x[0-9]+]], [[VA_ADDR]], #8
+; CHECK-NEXT: str [[NEXT_VA_ADDR]], [sp, #8]
+; CHECK-NEXT: ldr [[VA_VAL:w[0-9]+]], {{\[}}[[VA_ADDR]]]
+; CHECK-NEXT: add [[SUM]], [[SUM]], [[VA_VAL]]
+; CHECK-NEXT: sub w1, w1, #1
+; CHECK-NEXT: cbnz w1, [[LOOP_LABEL]]
+;
+; DISABLE-NEXT: b [[IFEND_LABEL]]
+; DISABLE: [[ELSE_LABEL]]: ; %if.else
+; DISABLE: lsl w0, w1, #1
+;
+; CHECK: [[IFEND_LABEL]]:
+; Epilogue code.
+; CHECK: add sp, sp, #16
+; CHECK-NEXT: ret
+;
+; ENABLE: [[ELSE_LABEL]]: ; %if.else
+; ENABLE: lsl w0, w1, #1
+; ENABLE-NEXT: ret
+define i32 @variadicFunc(i32 %cond, i32 %count, ...) #0 {
+entry:
+  %ap = alloca i8*, align 8
+  %tobool = icmp eq i32 %cond, 0
+  br i1 %tobool, label %if.else, label %if.then
+
+if.then:                                          ; preds = %entry
+  %ap1 = bitcast i8** %ap to i8*
+  call void @llvm.va_start(i8* %ap1)
+  %cmp6 = icmp sgt i32 %count, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %if.then, %for.body
+  %i.08 = phi i32 [ %inc, %for.body ], [ 0, %if.then ]
+  %sum.07 = phi i32 [ %add, %for.body ], [ 0, %if.then ]
+  %0 = va_arg i8** %ap, i32
+  %add = add nsw i32 %sum.07, %0
+  %inc = add nuw nsw i32 %i.08, 1
+  %exitcond = icmp eq i32 %inc, %count
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %if.then
+  %sum.0.lcssa = phi i32 [ 0, %if.then ], [ %add, %for.body ]
+  call void @llvm.va_end(i8* %ap1)
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  %mul = shl nsw i32 %count, 1
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %for.end
+  %sum.1 = phi i32 [ %sum.0.lcssa, %for.end ], [ %mul, %if.else ]
+  ret i32 %sum.1
+}
+
+declare void @llvm.va_start(i8*)
+
+declare void @llvm.va_end(i8*)
+
+; Check that we handle inline asm correctly.
+; CHECK-LABEL: inlineAsm:
+;
+; ENABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; Prologue code.
+; Make sure we save the CSR used in the inline asm: x19.
+; CHECK: stp [[CSR1:x[0-9]+]], [[CSR2:x19]], [sp, #-16]!
+;
+; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; CHECK: movz [[IV:w[0-9]+]], #0xa
+;
+; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body
+; Inline asm statement.
+; CHECK: add x19, x19, #1
+; CHECK: sub [[IV]], [[IV]], #1
+; CHECK-NEXT: cbnz [[IV]], [[LOOP_LABEL]]
+; Next BB.
+; CHECK: mov w0, wzr
+; Epilogue code.
+; CHECK-NEXT: ldp [[CSR1]], [[CSR2]], [sp], #16
+; CHECK-NEXT: ret
+; Next BB.
+; CHECK: [[ELSE_LABEL]]: ; %if.else
+; CHECK-NEXT: lsl w0, w1, #1
+; Epilogue code.
+; DISABLE-NEXT: ldp [[CSR1]], [[CSR2]], [sp], #16
+; CHECK-NEXT: ret
+define i32 @inlineAsm(i32 %cond, i32 %N) {
+entry:
+  %tobool = icmp eq i32 %cond, 0
+  br i1 %tobool, label %if.else, label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %i.03 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
+  tail call void asm sideeffect "add x19, x19, #1", "~{x19}"()
+  %inc = add nuw nsw i32 %i.03, 1
+  %exitcond = icmp eq i32 %inc, 10
+  br i1 %exitcond, label %if.end, label %for.body
+
+if.else:                                          ; preds = %entry
+  %mul = shl nsw i32 %N, 1
+  br label %if.end
+
+if.end:                                           ; preds = %for.body, %if.else
+  %sum.0 = phi i32 [ %mul, %if.else ], [ 0, %for.body ]
+  ret i32 %sum.0
+}
+
+; Check that we handle calls to variadic functions correctly.
+; CHECK-LABEL: callVariadicFunc:
+;
+; ENABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; Prologue code.
+; CHECK: stp [[CSR1:x[0-9]+]], [[CSR2:x[0-9]+]], [sp, #-16]!
+; CHECK-NEXT: mov [[NEW_SP:x[0-9]+]], sp
+; CHECK-NEXT: sub sp, sp, #48
+;
+; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
+; Setup of the varags.
+; CHECK: stp x1, x1, [sp, #32]
+; CHECK-NEXT: stp x1, x1, [sp, #16]
+; CHECK-NEXT: stp x1, x1, [sp]
+; CHECK-NEXT: mov w0, w1
+; CHECK-NEXT: bl _someVariadicFunc
+; CHECK-NEXT: lsl w0, w0, #3
+;
+; DISABLE: b [[IFEND_LABEL:LBB[0-9_]+]]
+; DISABLE: [[ELSE_LABEL]]: ; %if.else
+; DISABLE-NEXT: lsl w0, w1, #1
+; DISABLE: [[IFEND_LABEL]]: ; %if.end
+;
+; Epilogue code.
+; CHECK: mov sp, [[NEW_SP]]
+; CHECK-NEXT: ldp [[CSR1]], [[CSR2]], [sp], #16
+; CHECK-NEXT: ret
+;
+; ENABLE: [[ELSE_LABEL]]: ; %if.else
+; ENABLE-NEXT: lsl w0, w1, #1
+; ENABLE-NEXT: ret
+define i32 @callVariadicFunc(i32 %cond, i32 %N) {
+entry:
+  %tobool = icmp eq i32 %cond, 0
+  br i1 %tobool, label %if.else, label %if.then
+
+if.then:                                          ; preds = %entry
+  %call = tail call i32 (i32, ...) @someVariadicFunc(i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N)
+  %shl = shl i32 %call, 3
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  %mul = shl nsw i32 %N, 1
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  %sum.0 = phi i32 [ %shl, %if.then ], [ %mul, %if.else ]
+  ret i32 %sum.0
+}
+
+declare i32 @someVariadicFunc(i32, ...)
diff --git a/test/CodeGen/AArch64/arm64-sitofp-combine-chains.ll b/test/CodeGen/AArch64/arm64-sitofp-combine-chains.ll
index 10b433b97757..21131657820f 100644
--- a/test/CodeGen/AArch64/arm64-sitofp-combine-chains.ll
+++ b/test/CodeGen/AArch64/arm64-sitofp-combine-chains.ll
@@ -14,7 +14,7 @@ define float @foo() {
 ; CHECK: ldr [[SREG:s[0-9]+]], [x[[VARBASE]],
 ; CHECK: str wzr, [x[[VARBASE]],
 
-  %val = load i32* @var, align 4
+  %val = load i32, i32* @var, align 4
   store i32 0, i32* @var, align 4
 
   %fltval = sitofp i32 %val to float
diff --git a/test/CodeGen/AArch64/arm64-smaxv.ll b/test/CodeGen/AArch64/arm64-smaxv.ll
index 183e667643cc..8cc4502f6caa 100644
--- a/test/CodeGen/AArch64/arm64-smaxv.ll
+++ b/test/CodeGen/AArch64/arm64-smaxv.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s
+; RUN: llc -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false < %s | FileCheck %s
 
 define signext i8 @test_vmaxv_s8(<8 x i8> %a1) {
 ; CHECK: test_vmaxv_s8
@@ -65,6 +65,76 @@ entry:
   ret i32 %vmaxv.i
 }
 
+define <8 x i8> @test_vmaxv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
+; CHECK-LABEL: test_vmaxv_s8_used_by_laneop:
+; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a2)
+  %1 = trunc i32 %0 to i8
+  %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
+  ret <8 x i8> %2
+}
+
+define <4 x i16> @test_vmaxv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
+; CHECK-LABEL: test_vmaxv_s16_used_by_laneop:
+; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a2)
+  %1 = trunc i32 %0 to i16
+  %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
+  ret <4 x i16> %2
+}
+
+define <2 x i32> @test_vmaxv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
+; CHECK-LABEL: test_vmaxv_s32_used_by_laneop:
+; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v1, v1
+; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a2)
+  %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
+  ret <2 x i32> %1
+}
+
+define <16 x i8> @test_vmaxvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
+; CHECK-LABEL: test_vmaxvq_s8_used_by_laneop:
+; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a2)
+  %1 = trunc i32 %0 to i8
+  %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
+  ret <16 x i8> %2
+}
+
+define <8 x i16> @test_vmaxvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
+; CHECK-LABEL: test_vmaxvq_s16_used_by_laneop:
+; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a2)
+  %1 = trunc i32 %0 to i16
+  %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
+  ret <8 x i16> %2
+}
+
+define <4 x i32> @test_vmaxvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
+; CHECK-LABEL: test_vmaxvq_s32_used_by_laneop:
+; CHECK: smaxv.4s s[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a2)
+  %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
+  ret <4 x i32> %1
+}
+
 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32>)
 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16>)
 declare i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8>)
diff --git a/test/CodeGen/AArch64/arm64-sminv.ll b/test/CodeGen/AArch64/arm64-sminv.ll
index 195c4e59dc41..c1650b5fb294 100644
--- a/test/CodeGen/AArch64/arm64-sminv.ll
+++ b/test/CodeGen/AArch64/arm64-sminv.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s
+; RUN: llc -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false < %s | FileCheck %s
 
 define signext i8 @test_vminv_s8(<8 x i8> %a1) {
 ; CHECK: test_vminv_s8
@@ -65,6 +65,76 @@ entry:
   ret i32 %vminv.i
 }
 
+define <8 x i8> @test_vminv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
+; CHECK-LABEL: test_vminv_s8_used_by_laneop:
+; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a2)
+  %1 = trunc i32 %0 to i8
+  %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
+  ret <8 x i8> %2
+}
+
+define <4 x i16> @test_vminv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
+; CHECK-LABEL: test_vminv_s16_used_by_laneop:
+; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a2)
+  %1 = trunc i32 %0 to i16
+  %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
+  ret <4 x i16> %2
+}
+
+define <2 x i32> @test_vminv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
+; CHECK-LABEL: test_vminv_s32_used_by_laneop:
+; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v1, v1
+; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a2)
+  %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
+  ret <2 x i32> %1
+}
+
+define <16 x i8> @test_vminvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
+; CHECK-LABEL: test_vminvq_s8_used_by_laneop:
+; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a2)
+  %1 = trunc i32 %0 to i8
+  %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
+  ret <16 x i8> %2
+}
+
+define <8 x i16> @test_vminvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
+; CHECK-LABEL: test_vminvq_s16_used_by_laneop:
+; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a2)
+  %1 = trunc i32 %0 to i16
+  %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
+  ret <8 x i16> %2
+}
+
+define <4 x i32> @test_vminvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
+; CHECK-LABEL: test_vminvq_s32_used_by_laneop:
+; CHECK: sminv.4s s[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a2)
+  %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
+  ret <4 x i32> %1
+}
+
 declare i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32>)
 declare i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16>)
 declare i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8>)
diff --git a/test/CodeGen/AArch64/arm64-spill-lr.ll b/test/CodeGen/AArch64/arm64-spill-lr.ll
index fb6588e6ae46..88109088a2ff 100644
--- a/test/CodeGen/AArch64/arm64-spill-lr.ll
+++ b/test/CodeGen/AArch64/arm64-spill-lr.ll
@@ -11,31 +11,31 @@ entry:
   %stack = alloca [128 x i32], align 4
   %0 = bitcast [128 x i32]* %stack to i8*
   %idxprom = sext i32 %a to i64
-  %arrayidx = getelementptr inbounds [128 x i32]* %stack, i64 0, i64 %idxprom
+  %arrayidx = getelementptr inbounds [128 x i32], [128 x i32]* %stack, i64 0, i64 %idxprom
   store i32 %b, i32* %arrayidx, align 4
-  %1 = load volatile i32* @bar, align 4
-  %2 = load volatile i32* @bar, align 4
-  %3 = load volatile i32* @bar, align 4
-  %4 = load volatile i32* @bar, align 4
-  %5 = load volatile i32* @bar, align 4
-  %6 = load volatile i32* @bar, align 4
-  %7 = load volatile i32* @bar, align 4
-  %8 = load volatile i32* @bar, align 4
-  %9 = load volatile i32* @bar, align 4
-  %10 = load volatile i32* @bar, align 4
-  %11 = load volatile i32* @bar, align 4
-  %12 = load volatile i32* @bar, align 4
-  %13 = load volatile i32* @bar, align 4
-  %14 = load volatile i32* @bar, align 4
-  %15 = load volatile i32* @bar, align 4
-  %16 = load volatile i32* @bar, align 4
-  %17 = load volatile i32* @bar, align 4
-  %18 = load volatile i32* @bar, align 4
-  %19 = load volatile i32* @bar, align 4
-  %20 = load volatile i32* @bar, align 4
+  %1 = load volatile i32, i32* @bar, align 4
+  %2 = load volatile i32, i32* @bar, align 4
+  %3 = load volatile i32, i32* @bar, align 4
+  %4 = load volatile i32, i32* @bar, align 4
+  %5 = load volatile i32, i32* @bar, align 4
+  %6 = load volatile i32, i32* @bar, align 4
+  %7 = load volatile i32, i32* @bar, align 4
+  %8 = load volatile i32, i32* @bar, align 4
+  %9 = load volatile i32, i32* @bar, align 4
+  %10 = load volatile i32, i32* @bar, align 4
+  %11 = load volatile i32, i32* @bar, align 4
+  %12 = load volatile i32, i32* @bar, align 4
+  %13 = load volatile i32, i32* @bar, align 4
+  %14 = load volatile i32, i32* @bar, align 4
+  %15 = load volatile i32, i32* @bar, align 4
+  %16 = load volatile i32, i32* @bar, align 4
+  %17 = load volatile i32, i32* @bar, align 4
+  %18 = load volatile i32, i32* @bar, align 4
+  %19 = load volatile i32, i32* @bar, align 4
+  %20 = load volatile i32, i32* @bar, align 4
   %idxprom1 = sext i32 %c to i64
-  %arrayidx2 = getelementptr inbounds [128 x i32]* %stack, i64 0, i64 %idxprom1
-  %21 = load i32* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds [128 x i32], [128 x i32]* %stack, i64 0, i64 %idxprom1
+  %21 = load i32, i32* %arrayidx2, align 4
   %factor = mul i32 %h, -2
   %factor67 = mul i32 %g, -2
   %factor68 = mul i32 %f, -2
diff --git a/test/CodeGen/AArch64/arm64-spill.ll b/test/CodeGen/AArch64/arm64-spill.ll
index 47cdc2bd95e4..9c0cf38f9a2e 100644
--- a/test/CodeGen/AArch64/arm64-spill.ll
+++ b/test/CodeGen/AArch64/arm64-spill.ll
@@ -8,7 +8,7 @@
 ; CHECK: st1.2d
 define void @fpr128(<4 x float>* %p) nounwind ssp {
 entry:
-  %x = load <4 x float>* %p, align 16
+  %x = load <4 x float>, <4 x float>* %p, align 16
   call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15},~{q16},~{q17},~{q18},~{q19},~{q20},~{q21},~{q22},~{q23},~{q24},~{q25},~{q26},~{q27},~{q28},~{q29},~{q30},~{q31},~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp},~{memory}"() nounwind
   store <4 x float> %x, <4 x float>* %p, align 16
   ret void
diff --git a/test/CodeGen/AArch64/arm64-st1.ll b/test/CodeGen/AArch64/arm64-st1.ll
index 76d52f44b480..0387a91ea0e8 100644
--- a/test/CodeGen/AArch64/arm64-st1.ll
+++ b/test/CodeGen/AArch64/arm64-st1.ll
@@ -12,7 +12,7 @@ define void @st1lane_ro_16b(<16 x i8> %A, i8* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane_ro_16b
 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
 ; CHECK: st1.b { v0 }[1], [x[[XREG]]]
-  %ptr = getelementptr i8* %D, i64 %offset
+  %ptr = getelementptr i8, i8* %D, i64 %offset
   %tmp = extractelement <16 x i8> %A, i32 1
   store i8 %tmp, i8* %ptr
   ret void
@@ -22,7 +22,7 @@ define void @st1lane0_ro_16b(<16 x i8> %A, i8* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane0_ro_16b
 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
 ; CHECK: st1.b { v0 }[0], [x[[XREG]]]
-  %ptr = getelementptr i8* %D, i64 %offset
+  %ptr = getelementptr i8, i8* %D, i64 %offset
   %tmp = extractelement <16 x i8> %A, i32 0
   store i8 %tmp, i8* %ptr
   ret void
@@ -40,7 +40,7 @@ define void @st1lane_ro_8h(<8 x i16> %A, i16* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane_ro_8h
 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
 ; CHECK: st1.h { v0 }[1], [x[[XREG]]]
-  %ptr = getelementptr i16* %D, i64 %offset
+  %ptr = getelementptr i16, i16* %D, i64 %offset
   %tmp = extractelement <8 x i16> %A, i32 1
   store i16 %tmp, i16* %ptr
   ret void
@@ -49,7 +49,7 @@ define void @st1lane_ro_8h(<8 x i16> %A, i16* %D, i64 %offset) {
 define void @st1lane0_ro_8h(<8 x i16> %A, i16* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane0_ro_8h
 ; CHECK: str h0, [x0, x1, lsl #1]
-  %ptr = getelementptr i16* %D, i64 %offset
+  %ptr = getelementptr i16, i16* %D, i64 %offset
   %tmp = extractelement <8 x i16> %A, i32 0
   store i16 %tmp, i16* %ptr
   ret void
@@ -67,7 +67,7 @@ define void @st1lane_ro_4s(<4 x i32> %A, i32* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane_ro_4s
 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
 ; CHECK: st1.s { v0 }[1], [x[[XREG]]]
-  %ptr = getelementptr i32* %D, i64 %offset
+  %ptr = getelementptr i32, i32* %D, i64 %offset
   %tmp = extractelement <4 x i32> %A, i32 1
   store i32 %tmp, i32* %ptr
   ret void
@@ -76,7 +76,7 @@ define void @st1lane_ro_4s(<4 x i32> %A, i32* %D, i64 %offset) {
 define void @st1lane0_ro_4s(<4 x i32> %A, i32* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane0_ro_4s
 ; CHECK: str s0, [x0, x1, lsl #2]
-  %ptr = getelementptr i32* %D, i64 %offset
+  %ptr = getelementptr i32, i32* %D, i64 %offset
   %tmp = extractelement <4 x i32> %A, i32 0
   store i32 %tmp, i32* %ptr
   ret void
@@ -94,7 +94,7 @@ define void @st1lane_ro_4s_float(<4 x float> %A, float* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane_ro_4s_float
 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
 ; CHECK: st1.s { v0 }[1], [x[[XREG]]]
-  %ptr = getelementptr float* %D, i64 %offset
+  %ptr = getelementptr float, float* %D, i64 %offset
   %tmp = extractelement <4 x float> %A, i32 1
   store float %tmp, float* %ptr
   ret void
@@ -103,7 +103,7 @@ define void @st1lane_ro_4s_float(<4 x float> %A, float* %D, i64 %offset) {
 define void @st1lane0_ro_4s_float(<4 x float> %A, float* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane0_ro_4s_float
 ; CHECK: str s0, [x0, x1, lsl #2]
-  %ptr = getelementptr float* %D, i64 %offset
+  %ptr = getelementptr float, float* %D, i64 %offset
   %tmp = extractelement <4 x float> %A, i32 0
   store float %tmp, float* %ptr
   ret void
@@ -121,7 +121,7 @@ define void @st1lane_ro_2d(<2 x i64> %A, i64* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane_ro_2d
 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
 ; CHECK: st1.d { v0 }[1], [x[[XREG]]]
-  %ptr = getelementptr i64* %D, i64 %offset
+  %ptr = getelementptr i64, i64* %D, i64 %offset
   %tmp = extractelement <2 x i64> %A, i32 1
   store i64 %tmp, i64* %ptr
   ret void
@@ -130,7 +130,7 @@ define void @st1lane_ro_2d(<2 x i64> %A, i64* %D, i64 %offset) {
 define void @st1lane0_ro_2d(<2 x i64> %A, i64* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane0_ro_2d
 ; CHECK: str d0, [x0, x1, lsl #3]
-  %ptr = getelementptr i64* %D, i64 %offset
+  %ptr = getelementptr i64, i64* %D, i64 %offset
   %tmp = extractelement <2 x i64> %A, i32 0
   store i64 %tmp, i64* %ptr
   ret void
@@ -148,7 +148,7 @@ define void @st1lane_ro_2d_double(<2 x double> %A, double* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane_ro_2d_double
 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
 ; CHECK: st1.d { v0 }[1], [x[[XREG]]]
-  %ptr = getelementptr double* %D, i64 %offset
+  %ptr = getelementptr double, double* %D, i64 %offset
   %tmp = extractelement <2 x double> %A, i32 1
   store double %tmp, double* %ptr
   ret void
@@ -157,7 +157,7 @@ define void @st1lane_ro_2d_double(<2 x double> %A, double* %D, i64 %offset) {
 define void @st1lane0_ro_2d_double(<2 x double> %A, double* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane0_ro_2d_double
 ; CHECK: str d0, [x0, x1, lsl #3]
-  %ptr = getelementptr double* %D, i64 %offset
+  %ptr = getelementptr double, double* %D, i64 %offset
   %tmp = extractelement <2 x double> %A, i32 0
   store double %tmp, double* %ptr
   ret void
@@ -175,7 +175,7 @@ define void @st1lane_ro_8b(<8 x i8> %A, i8* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane_ro_8b
 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
 ; CHECK: st1.b { v0 }[1], [x[[XREG]]]
-  %ptr = getelementptr i8* %D, i64 %offset
+  %ptr = getelementptr i8, i8* %D, i64 %offset
   %tmp = extractelement <8 x i8> %A, i32 1
   store i8 %tmp, i8* %ptr
   ret void
@@ -185,7 +185,7 @@ define void @st1lane0_ro_8b(<8 x i8> %A, i8* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane0_ro_8b
 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
 ; CHECK: st1.b { v0 }[0], [x[[XREG]]]
-  %ptr = getelementptr i8* %D, i64 %offset
+  %ptr = getelementptr i8, i8* %D, i64 %offset
   %tmp = extractelement <8 x i8> %A, i32 0
   store i8 %tmp, i8* %ptr
   ret void
@@ -203,7 +203,7 @@ define void @st1lane_ro_4h(<4 x i16> %A, i16* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane_ro_4h
 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
 ; CHECK: st1.h { v0 }[1], [x[[XREG]]]
-  %ptr = getelementptr i16* %D, i64 %offset
+  %ptr = getelementptr i16, i16* %D, i64 %offset
   %tmp = extractelement <4 x i16> %A, i32 1
   store i16 %tmp, i16* %ptr
   ret void
@@ -212,7 +212,7 @@ define void @st1lane_ro_4h(<4 x i16> %A, i16* %D, i64 %offset) {
 define void @st1lane0_ro_4h(<4 x i16> %A, i16* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane0_ro_4h
 ; CHECK: str h0, [x0, x1, lsl #1]
-  %ptr = getelementptr i16* %D, i64 %offset
+  %ptr = getelementptr i16, i16* %D, i64 %offset
   %tmp = extractelement <4 x i16> %A, i32 0
   store i16 %tmp, i16* %ptr
   ret void
@@ -230,7 +230,7 @@ define void @st1lane_ro_2s(<2 x i32> %A, i32* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane_ro_2s
 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
 ; CHECK: st1.s { v0 }[1], [x[[XREG]]]
-  %ptr = getelementptr i32* %D, i64 %offset
+  %ptr = getelementptr i32, i32* %D, i64 %offset
   %tmp = extractelement <2 x i32> %A, i32 1
   store i32 %tmp, i32* %ptr
   ret void
@@ -239,7 +239,7 @@ define void @st1lane_ro_2s(<2 x i32> %A, i32* %D, i64 %offset) {
 define void @st1lane0_ro_2s(<2 x i32> %A, i32* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane0_ro_2s
 ; CHECK: str s0, [x0, x1, lsl #2]
-  %ptr = getelementptr i32* %D, i64 %offset
+  %ptr = getelementptr i32, i32* %D, i64 %offset
   %tmp = extractelement <2 x i32> %A, i32 0
   store i32 %tmp, i32* %ptr
   ret void
@@ -257,7 +257,7 @@ define void @st1lane_ro_2s_float(<2 x float> %A, float* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane_ro_2s_float
 ; CHECK: add x[[XREG:[0-9]+]], x0, x1
 ; CHECK: st1.s { v0 }[1], [x[[XREG]]]
-  %ptr = getelementptr float* %D, i64 %offset
+  %ptr = getelementptr float, float* %D, i64 %offset
   %tmp = extractelement <2 x float> %A, i32 1
   store float %tmp, float* %ptr
   ret void
@@ -266,7 +266,7 @@ define void @st1lane_ro_2s_float(<2 x float> %A, float* %D, i64 %offset) {
 define void @st1lane0_ro_2s_float(<2 x float> %A, float* %D, i64 %offset) {
 ; CHECK-LABEL: st1lane0_ro_2s_float
 ; CHECK: str s0, [x0, x1, lsl #2]
-  %ptr = getelementptr float* %D, i64 %offset
+  %ptr = getelementptr float, float* %D, i64 %offset
   %tmp = extractelement <2 x float> %A, i32 0
   store float %tmp, float* %ptr
   ret void
@@ -374,21 +374,21 @@ declare void @llvm.aarch64.neon.st4lane.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i
 
 define void @st2_8b(<8 x i8> %A, <8 x i8> %B, i8* %P) nounwind {
 ; CHECK-LABEL: st2_8b
-; CHECK st2.8b
+; CHECK: st2.8b
 	call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, i8* %P)
 	ret void
 }
 
 define void @st3_8b(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, i8* %P) nounwind {
 ; CHECK-LABEL: st3_8b
-; CHECK st3.8b
+; CHECK: st3.8b
 	call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, i8* %P)
 	ret void
 }
 
 define void @st4_8b(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %P) nounwind {
 ; CHECK-LABEL: st4_8b
-; CHECK st4.8b
+; CHECK: st4.8b
 	call void @llvm.aarch64.neon.st4.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %P)
 	ret void
 }
@@ -399,21 +399,21 @@ declare void @llvm.aarch64.neon.st4.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, <8 x
 
 define void @st2_16b(<16 x i8> %A, <16 x i8> %B, i8* %P) nounwind {
 ; CHECK-LABEL: st2_16b
-; CHECK st2.16b
+; CHECK: st2.16b
 	call void @llvm.aarch64.neon.st2.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, i8* %P)
 	ret void
 }
 
 define void @st3_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, i8* %P) nounwind {
 ; CHECK-LABEL: st3_16b
-; CHECK st3.16b
+; CHECK: st3.16b
 	call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, i8* %P)
 	ret void
 }
 
 define void @st4_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %P) nounwind {
 ; CHECK-LABEL: st4_16b
-; CHECK st4.16b
+; CHECK: st4.16b
 	call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %P)
 	ret void
 }
@@ -424,21 +424,21 @@ declare void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>,
 
 define void @st2_4h(<4 x i16> %A, <4 x i16> %B, i16* %P) nounwind {
 ; CHECK-LABEL: st2_4h
-; CHECK st2.4h
+; CHECK: st2.4h
 	call void @llvm.aarch64.neon.st2.v4i16.p0i16(<4 x i16> %A, <4 x i16> %B, i16* %P)
 	ret void
 }
 
 define void @st3_4h(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, i16* %P) nounwind {
 ; CHECK-LABEL: st3_4h
-; CHECK st3.4h
+; CHECK: st3.4h
 	call void @llvm.aarch64.neon.st3.v4i16.p0i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, i16* %P)
 	ret void
 }
 
 define void @st4_4h(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %P) nounwind {
 ; CHECK-LABEL: st4_4h
-; CHECK st4.4h
+; CHECK: st4.4h
 	call void @llvm.aarch64.neon.st4.v4i16.p0i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %P)
 	ret void
 }
@@ -449,21 +449,21 @@ declare void @llvm.aarch64.neon.st4.v4i16.p0i16(<4 x i16>, <4 x i16>, <4 x i16>,
 
 define void @st2_8h(<8 x i16> %A, <8 x i16> %B, i16* %P) nounwind {
 ; CHECK-LABEL: st2_8h
-; CHECK st2.8h
+; CHECK: st2.8h
 	call void @llvm.aarch64.neon.st2.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, i16* %P)
 	ret void
 }
 
 define void @st3_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, i16* %P) nounwind {
 ; CHECK-LABEL: st3_8h
-; CHECK st3.8h
+; CHECK: st3.8h
 	call void @llvm.aarch64.neon.st3.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, i16* %P)
 	ret void
 }
 
 define void @st4_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %P) nounwind {
 ; CHECK-LABEL: st4_8h
-; CHECK st4.8h
+; CHECK: st4.8h
 	call void @llvm.aarch64.neon.st4.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %P)
 	ret void
 }
@@ -474,21 +474,21 @@ declare void @llvm.aarch64.neon.st4.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>,
 
 define void @st2_2s(<2 x i32> %A, <2 x i32> %B, i32* %P) nounwind {
 ; CHECK-LABEL: st2_2s
-; CHECK st2.2s
+; CHECK: st2.2s
 	call void @llvm.aarch64.neon.st2.v2i32.p0i32(<2 x i32> %A, <2 x i32> %B, i32* %P)
 	ret void
 }
 
 define void @st3_2s(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32* %P) nounwind {
 ; CHECK-LABEL: st3_2s
-; CHECK st3.2s
+; CHECK: st3.2s
 	call void @llvm.aarch64.neon.st3.v2i32.p0i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32* %P)
 	ret void
 }
 
 define void @st4_2s(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %P) nounwind {
 ; CHECK-LABEL: st4_2s
-; CHECK st4.2s
+; CHECK: st4.2s
 	call void @llvm.aarch64.neon.st4.v2i32.p0i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %P)
 	ret void
 }
@@ -499,21 +499,21 @@ declare void @llvm.aarch64.neon.st4.v2i32.p0i32(<2 x i32>, <2 x i32>, <2 x i32>,
 
 define void @st2_4s(<4 x i32> %A, <4 x i32> %B, i32* %P) nounwind {
 ; CHECK-LABEL: st2_4s
-; CHECK st2.4s
+; CHECK: st2.4s
 	call void @llvm.aarch64.neon.st2.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, i32* %P)
 	ret void
 }
 
 define void @st3_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32* %P) nounwind {
 ; CHECK-LABEL: st3_4s
-; CHECK st3.4s
+; CHECK: st3.4s
 	call void @llvm.aarch64.neon.st3.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32* %P)
 	ret void
 }
 
 define void @st4_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %P) nounwind {
 ; CHECK-LABEL: st4_4s
-; CHECK st4.4s
+; CHECK: st4.4s
 	call void @llvm.aarch64.neon.st4.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %P)
 	ret void
 }
@@ -522,23 +522,24 @@ declare void @llvm.aarch64.neon.st2.v4i32.p0i32(<4 x i32>, <4 x i32>, i32*) noun
 declare void @llvm.aarch64.neon.st3.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, i32*) nounwind readonly
 declare void @llvm.aarch64.neon.st4.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32*) nounwind readonly
 
+; If there's only one element, st2/3/4 don't make much sense, stick to st1.
 define void @st2_1d(<1 x i64> %A, <1 x i64> %B, i64* %P) nounwind {
 ; CHECK-LABEL: st2_1d
-; CHECK st1.2d
+; CHECK: st1.1d
 	call void @llvm.aarch64.neon.st2.v1i64.p0i64(<1 x i64> %A, <1 x i64> %B, i64* %P)
 	ret void
 }
 
 define void @st3_1d(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, i64* %P) nounwind {
 ; CHECK-LABEL: st3_1d
-; CHECK st1.3d
+; CHECK: st1.1d
 	call void @llvm.aarch64.neon.st3.v1i64.p0i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, i64* %P)
 	ret void
 }
 
 define void @st4_1d(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %P) nounwind {
 ; CHECK-LABEL: st4_1d
-; CHECK st1.4d
+; CHECK: st1.1d
 	call void @llvm.aarch64.neon.st4.v1i64.p0i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %P)
 	ret void
 }
@@ -549,21 +550,21 @@ declare void @llvm.aarch64.neon.st4.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>,
 
 define void @st2_2d(<2 x i64> %A, <2 x i64> %B, i64* %P) nounwind {
 ; CHECK-LABEL: st2_2d
-; CHECK st2.2d
+; CHECK: st2.2d
 	call void @llvm.aarch64.neon.st2.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, i64* %P)
 	ret void
 }
 
 define void @st3_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, i64* %P) nounwind {
 ; CHECK-LABEL: st3_2d
-; CHECK st2.3d
+; CHECK: st3.2d
 	call void @llvm.aarch64.neon.st3.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, i64* %P)
 	ret void
 }
 
 define void @st4_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %P) nounwind {
 ; CHECK-LABEL: st4_2d
-; CHECK st2.4d
+; CHECK: st4.2d
 	call void @llvm.aarch64.neon.st4.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %P)
 	ret void
 }
diff --git a/test/CodeGen/AArch64/arm64-stack-no-frame.ll b/test/CodeGen/AArch64/arm64-stack-no-frame.ll
index b5970c00ff94..22a67070a129 100644
--- a/test/CodeGen/AArch64/arm64-stack-no-frame.ll
+++ b/test/CodeGen/AArch64/arm64-stack-no-frame.ll
@@ -9,10 +9,10 @@ define void @test_stack_no_frame() {
 ; CHECK: test_stack_no_frame
 ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
   %local = alloca [20 x i64]
-  %val = load volatile [20 x i64]* @global, align 8
+  %val = load volatile [20 x i64], [20 x i64]* @global, align 8
   store volatile [20 x i64] %val, [20 x i64]* %local, align 8
 
-  %val2 = load volatile [20 x i64]* %local, align 8
+  %val2 = load volatile [20 x i64], [20 x i64]* %local, align 8
   store volatile [20 x i64] %val2, [20 x i64]* @global, align 8
 
 ; CHECK: add sp, sp, #[[STACKSIZE]]
diff --git a/test/CodeGen/AArch64/arm64-stackmap-nops.ll b/test/CodeGen/AArch64/arm64-stackmap-nops.ll
index 5915b64edf0a..2647ac442969 100644
--- a/test/CodeGen/AArch64/arm64-stackmap-nops.ll
+++ b/test/CodeGen/AArch64/arm64-stackmap-nops.ll
@@ -8,7 +8,7 @@ entry:
 ; CHECK:      nop
 ; CHECK-NEXT: nop
 ; CHECK-NOT:  nop
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  0, i32  16)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  0, i32  16)
   ret void
 }
 
diff --git a/test/CodeGen/AArch64/arm64-stackmap.ll b/test/CodeGen/AArch64/arm64-stackmap.ll
index 144c2fd2ee38..1a4df7a6f2d6 100644
--- a/test/CodeGen/AArch64/arm64-stackmap.ll
+++ b/test/CodeGen/AArch64/arm64-stackmap.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=arm64-apple-darwin                             < %s | FileCheck %s
-; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort < %s | FileCheck %s
+; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
 ;
 ; Note: Print verbose stackmaps using -debug-only=stackmaps.
 
@@ -78,7 +78,7 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 define void @constantargs() {
 entry:
   %0 = inttoptr i64 244837814094590 to i8*
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 1, i32 20, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 20, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296)
   ret void
 }
 
@@ -100,7 +100,7 @@ entry:
   ; Runtime void->void call.
   call void inttoptr (i64 244837814094590 to void ()*)()
   ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
   ret void
 }
 
@@ -126,7 +126,7 @@ entry:
 cold:
   ; OSR patchpoint with 12-byte nop-slide and 2 live vars.
   %thunk = inttoptr i64 244837814094590 to i8*
-  call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 4, i32 20, i8* %thunk, i32 0, i64 %a, i64 %b)
+  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 20, i8* %thunk, i32 0, i64 %a, i64 %b)
   unreachable
 ret:
   ret void
@@ -142,7 +142,7 @@ ret:
 define i64 @propertyRead(i64* %obj) {
 entry:
   %resolveRead = inttoptr i64 244837814094590 to i8*
-  %result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveRead, i32 1, i64* %obj)
+  %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveRead, i32 1, i64* %obj)
   %add = add i64 %result, 3
   ret i64 %add
 }
@@ -162,7 +162,7 @@ entry:
 define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
 entry:
   %resolveWrite = inttoptr i64 244837814094590 to i8*
-  call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
+  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
   ret void
 }
 
@@ -184,7 +184,7 @@ entry:
 define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
   %resolveCall = inttoptr i64 244837814094590 to i8*
-  call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 7, i32 20, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
+  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 20, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
   ret void
 }
 
@@ -206,7 +206,7 @@ entry:
 define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
   %resolveCall = inttoptr i64 244837814094590 to i8*
-  %result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 8, i32 20, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
+  %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 20, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
   %add = add i64 %result, 3
   ret i64 %add
 }
@@ -226,7 +226,7 @@ entry:
 ; CHECK-NEXT:   .short 29
 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) {
 entry:
-  call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 11, i32 20, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
+  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 20, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
   ret void
 }
 
@@ -245,7 +245,7 @@ entry:
 ; CHECK-NEXT:   .short 29
 define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) {
 entry:
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29)
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29)
   ret void
 }
 
@@ -263,7 +263,7 @@ entry:
 ; CHECK-NEXT:   .long   33
 
 define void @liveConstant() {
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 15, i32 8, i32 33)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 15, i32 8, i32 33)
   ret void
 }
 
@@ -280,7 +280,7 @@ define void @liveConstant() {
 ; CHECK-NEXT:   .long   -{{[0-9]+}}
 define void @clobberLR(i32 %a) {
   tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x31}"() nounwind
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 16, i32 8, i32 %a)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 8, i32 %a)
   ret void
 }
 
diff --git a/test/CodeGen/AArch64/arm64-stp-aa.ll b/test/CodeGen/AArch64/arm64-stp-aa.ll
new file mode 100644
index 000000000000..82d343d976b5
--- /dev/null
+++ b/test/CodeGen/AArch64/arm64-stp-aa.ll
@@ -0,0 +1,111 @@
+; RUN: llc < %s -march=arm64 -enable-misched=false -aarch64-stp-suppress=false -verify-machineinstrs | FileCheck %s
+
+; The next set of tests makes sure we can combine the second instruction into
+; the first.
+
+; CHECK-LABEL: stp_int_aa
+; CHECK: stp w0, w1, [x2]
+; CHECK: ldr w0, [x2, #8]
+; CHECK: ret
+define i32 @stp_int_aa(i32 %a, i32 %b, i32* nocapture %p) nounwind {
+  store i32 %a, i32* %p, align 4
+  %ld.ptr = getelementptr inbounds i32, i32* %p, i64 2
+  %tmp = load i32, i32* %ld.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
+  store i32 %b, i32* %add.ptr, align 4
+  ret i32 %tmp
+}
+
+; CHECK-LABEL: stp_long_aa
+; CHECK: stp x0, x1, [x2]
+; CHECK: ldr x0, [x2, #16]
+; CHECK: ret
+define i64 @stp_long_aa(i64 %a, i64 %b, i64* nocapture %p) nounwind {
+  store i64 %a, i64* %p, align 8
+  %ld.ptr = getelementptr inbounds i64, i64* %p, i64 2
+  %tmp = load i64, i64* %ld.ptr, align 4
+  %add.ptr = getelementptr inbounds i64, i64* %p, i64 1
+  store i64 %b, i64* %add.ptr, align 8
+  ret i64 %tmp
+}
+
+; CHECK-LABEL: stp_float_aa
+; CHECK: stp s0, s1, [x0]
+; CHECK: ldr s0, [x0, #8]
+; CHECK: ret
+define float @stp_float_aa(float %a, float %b, float* nocapture %p) nounwind {
+  store float %a, float* %p, align 4
+  %ld.ptr = getelementptr inbounds float, float* %p, i64 2
+  %tmp = load float, float* %ld.ptr, align 4
+  %add.ptr = getelementptr inbounds float, float* %p, i64 1
+  store float %b, float* %add.ptr, align 4
+  ret float %tmp
+}
+
+; CHECK-LABEL: stp_double_aa
+; CHECK: stp d0, d1, [x0]
+; CHECK: ldr d0, [x0, #16]
+; CHECK: ret
+define double @stp_double_aa(double %a, double %b, double* nocapture %p) nounwind {
+  store double %a, double* %p, align 8
+  %ld.ptr = getelementptr inbounds double, double* %p, i64 2
+  %tmp = load double, double* %ld.ptr, align 4
+  %add.ptr = getelementptr inbounds double, double* %p, i64 1
+  store double %b, double* %add.ptr, align 8
+  ret double %tmp
+}
+
+; The next set of tests makes sure we can combine the first instruction into
+; the second.
+
+; CHECK-LABEL: stp_int_aa_after
+; CHECK: ldr w0, [x3, #4]
+; CHECK: stp w1, w2, [x3]
+; CHECK: ret
+define i32 @stp_int_aa_after(i32 %w0, i32 %a, i32 %b, i32* nocapture %p) nounwind {
+  store i32 %a, i32* %p, align 4
+  %ld.ptr = getelementptr inbounds i32, i32* %p, i64 1
+  %tmp = load i32, i32* %ld.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
+  store i32 %b, i32* %add.ptr, align 4
+  ret i32 %tmp
+}
+
+; CHECK-LABEL: stp_long_aa_after
+; CHECK: ldr x0, [x3, #8]
+; CHECK: stp x1, x2, [x3]
+; CHECK: ret
+define i64 @stp_long_aa_after(i64 %x0, i64 %a, i64 %b, i64* nocapture %p) nounwind {
+  store i64 %a, i64* %p, align 8
+  %ld.ptr = getelementptr inbounds i64, i64* %p, i64 1
+  %tmp = load i64, i64* %ld.ptr, align 4
+  %add.ptr = getelementptr inbounds i64, i64* %p, i64 1
+  store i64 %b, i64* %add.ptr, align 8
+  ret i64 %tmp
+}
+
+; CHECK-LABEL: stp_float_aa_after
+; CHECK: ldr s0, [x0, #4]
+; CHECK: stp s1, s2, [x0]
+; CHECK: ret
+define float @stp_float_aa_after(float %s0, float %a, float %b, float* nocapture %p) nounwind {
+  store float %a, float* %p, align 4
+  %ld.ptr = getelementptr inbounds float, float* %p, i64 1
+  %tmp = load float, float* %ld.ptr, align 4
+  %add.ptr = getelementptr inbounds float, float* %p, i64 1
+  store float %b, float* %add.ptr, align 4
+  ret float %tmp
+}
+
+; CHECK-LABEL: stp_double_aa_after
+; CHECK: ldr d0, [x0, #8]
+; CHECK: stp d1, d2, [x0]
+; CHECK: ret
+define double @stp_double_aa_after(double %d0, double %a, double %b, double* nocapture %p) nounwind {
+  store double %a, double* %p, align 8
+  %ld.ptr = getelementptr inbounds double, double* %p, i64 1
+  %tmp = load double, double* %ld.ptr, align 4
+  %add.ptr = getelementptr inbounds double, double* %p, i64 1
+  store double %b, double* %add.ptr, align 8
+  ret double %tmp
+}
diff --git a/test/CodeGen/AArch64/arm64-stp.ll b/test/CodeGen/AArch64/arm64-stp.ll
index 40bdf22c995c..4d76396471ad 100644
--- a/test/CodeGen/AArch64/arm64-stp.ll
+++ b/test/CodeGen/AArch64/arm64-stp.ll
@@ -6,7 +6,7 @@
 ; CHECK: stp w0, w1, [x2]
 define void @stp_int(i32 %a, i32 %b, i32* nocapture %p) nounwind {
   store i32 %a, i32* %p, align 4
-  %add.ptr = getelementptr inbounds i32* %p, i64 1
+  %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
   store i32 %b, i32* %add.ptr, align 4
   ret void
 }
@@ -15,7 +15,7 @@ define void @stp_int(i32 %a, i32 %b, i32* nocapture %p) nounwind {
 ; CHECK: stp x0, x1, [x2]
 define void @stp_long(i64 %a, i64 %b, i64* nocapture %p) nounwind {
   store i64 %a, i64* %p, align 8
-  %add.ptr = getelementptr inbounds i64* %p, i64 1
+  %add.ptr = getelementptr inbounds i64, i64* %p, i64 1
   store i64 %b, i64* %add.ptr, align 8
   ret void
 }
@@ -24,7 +24,7 @@ define void @stp_long(i64 %a, i64 %b, i64* nocapture %p) nounwind {
 ; CHECK: stp s0, s1, [x0]
 define void @stp_float(float %a, float %b, float* nocapture %p) nounwind {
   store float %a, float* %p, align 4
-  %add.ptr = getelementptr inbounds float* %p, i64 1
+  %add.ptr = getelementptr inbounds float, float* %p, i64 1
   store float %b, float* %add.ptr, align 4
   ret void
 }
@@ -33,7 +33,7 @@ define void @stp_float(float %a, float %b, float* nocapture %p) nounwind {
 ; CHECK: stp d0, d1, [x0]
 define void @stp_double(double %a, double %b, double* nocapture %p) nounwind {
   store double %a, double* %p, align 8
-  %add.ptr = getelementptr inbounds double* %p, i64 1
+  %add.ptr = getelementptr inbounds double, double* %p, i64 1
   store double %b, double* %add.ptr, align 8
   ret void
 }
@@ -43,9 +43,9 @@ define void @stur_int(i32 %a, i32 %b, i32* nocapture %p) nounwind {
 ; STUR_CHK: stur_int
 ; STUR_CHK: stp w{{[0-9]+}}, {{w[0-9]+}}, [x{{[0-9]+}}, #-8]
 ; STUR_CHK-NEXT: ret
-  %p1 = getelementptr inbounds i32* %p, i32 -1
+  %p1 = getelementptr inbounds i32, i32* %p, i32 -1
   store i32 %a, i32* %p1, align 2
-  %p2 = getelementptr inbounds i32* %p, i32 -2
+  %p2 = getelementptr inbounds i32, i32* %p, i32 -2
   store i32 %b, i32* %p2, align 2
   ret void
 }
@@ -54,9 +54,9 @@ define void @stur_long(i64 %a, i64 %b, i64* nocapture %p) nounwind {
 ; STUR_CHK: stur_long
 ; STUR_CHK: stp x{{[0-9]+}}, {{x[0-9]+}}, [x{{[0-9]+}}, #-16]
 ; STUR_CHK-NEXT: ret
-  %p1 = getelementptr inbounds i64* %p, i32 -1
+  %p1 = getelementptr inbounds i64, i64* %p, i32 -1
   store i64 %a, i64* %p1, align 2
-  %p2 = getelementptr inbounds i64* %p, i32 -2
+  %p2 = getelementptr inbounds i64, i64* %p, i32 -2
   store i64 %b, i64* %p2, align 2
   ret void
 }
@@ -65,9 +65,9 @@ define void @stur_float(float %a, float %b, float* nocapture %p) nounwind {
 ; STUR_CHK: stur_float
 ; STUR_CHK: stp s{{[0-9]+}}, {{s[0-9]+}}, [x{{[0-9]+}}, #-8]
 ; STUR_CHK-NEXT: ret
-  %p1 = getelementptr inbounds float* %p, i32 -1
+  %p1 = getelementptr inbounds float, float* %p, i32 -1
   store float %a, float* %p1, align 2
-  %p2 = getelementptr inbounds float* %p, i32 -2
+  %p2 = getelementptr inbounds float, float* %p, i32 -2
   store float %b, float* %p2, align 2
   ret void
 }
@@ -76,9 +76,9 @@ define void @stur_double(double %a, double %b, double* nocapture %p) nounwind {
 ; STUR_CHK: stur_double
 ; STUR_CHK: stp d{{[0-9]+}}, {{d[0-9]+}}, [x{{[0-9]+}}, #-16]
 ; STUR_CHK-NEXT: ret
-  %p1 = getelementptr inbounds double* %p, i32 -1
+  %p1 = getelementptr inbounds double, double* %p, i32 -1
   store double %a, double* %p1, align 2
-  %p2 = getelementptr inbounds double* %p, i32 -2
+  %p2 = getelementptr inbounds double, double* %p, i32 -2
   store double %b, double* %p2, align 2
   ret void
 }
diff --git a/test/CodeGen/AArch64/arm64-strict-align.ll b/test/CodeGen/AArch64/arm64-strict-align.ll
index 5d137043a691..b707527f3c0c 100644
--- a/test/CodeGen/AArch64/arm64-strict-align.ll
+++ b/test/CodeGen/AArch64/arm64-strict-align.ll
@@ -10,7 +10,7 @@ define i32 @f0(i32* nocapture %p) nounwind {
 
 ; CHECK: ldr w0, [x0]
 ; CHECK: ret
-  %tmp = load i32* %p, align 2
+  %tmp = load i32, i32* %p, align 2
   ret i32 %tmp
 }
 
@@ -21,6 +21,6 @@ define i64 @f1(i64* nocapture %p) nounwind {
 
 ; CHECK: ldr x0, [x0]
 ; CHECK: ret
-  %tmp = load i64* %p, align 4
+  %tmp = load i64, i64* %p, align 4
   ret i64 %tmp
 }
diff --git a/test/CodeGen/AArch64/arm64-stur.ll b/test/CodeGen/AArch64/arm64-stur.ll
index a2e684dc9528..5f4cb9f3d95a 100644
--- a/test/CodeGen/AArch64/arm64-stur.ll
+++ b/test/CodeGen/AArch64/arm64-stur.ll
@@ -6,7 +6,7 @@ define void @foo1(i32* %p, i64 %val) nounwind {
 ; CHECK: 	stur	w1, [x0, #-4]
 ; CHECK-NEXT: 	ret
   %tmp1 = trunc i64 %val to i32
-  %ptr = getelementptr inbounds i32* %p, i64 -1
+  %ptr = getelementptr inbounds i32, i32* %p, i64 -1
   store i32 %tmp1, i32* %ptr, align 4
   ret void
 }
@@ -15,7 +15,7 @@ define void @foo2(i16* %p, i64 %val) nounwind {
 ; CHECK: 	sturh	w1, [x0, #-2]
 ; CHECK-NEXT: 	ret
   %tmp1 = trunc i64 %val to i16
-  %ptr = getelementptr inbounds i16* %p, i64 -1
+  %ptr = getelementptr inbounds i16, i16* %p, i64 -1
   store i16 %tmp1, i16* %ptr, align 2
   ret void
 }
@@ -24,7 +24,7 @@ define void @foo3(i8* %p, i64 %val) nounwind {
 ; CHECK: 	sturb	w1, [x0, #-1]
 ; CHECK-NEXT: 	ret
   %tmp1 = trunc i64 %val to i8
-  %ptr = getelementptr inbounds i8* %p, i64 -1
+  %ptr = getelementptr inbounds i8, i8* %p, i64 -1
   store i8 %tmp1, i8* %ptr, align 1
   ret void
 }
@@ -33,7 +33,7 @@ define void @foo4(i16* %p, i32 %val) nounwind {
 ; CHECK: 	sturh	w1, [x0, #-2]
 ; CHECK-NEXT: 	ret
   %tmp1 = trunc i32 %val to i16
-  %ptr = getelementptr inbounds i16* %p, i32 -1
+  %ptr = getelementptr inbounds i16, i16* %p, i32 -1
   store i16 %tmp1, i16* %ptr, align 2
   ret void
 }
@@ -42,7 +42,7 @@ define void @foo5(i8* %p, i32 %val) nounwind {
 ; CHECK: 	sturb	w1, [x0, #-1]
 ; CHECK-NEXT: 	ret
   %tmp1 = trunc i32 %val to i8
-  %ptr = getelementptr inbounds i8* %p, i32 -1
+  %ptr = getelementptr inbounds i8, i8* %p, i32 -1
   store i8 %tmp1, i8* %ptr, align 1
   ret void
 }
@@ -53,7 +53,7 @@ define void @foo(%struct.X* nocapture %p) nounwind optsize ssp {
 ; CHECK: stur    xzr, [x0, #12]
 ; CHECK-NEXT: stur    xzr, [x0, #4]
 ; CHECK-NEXT: ret
-  %B = getelementptr inbounds %struct.X* %p, i64 0, i32 1
+  %B = getelementptr inbounds %struct.X, %struct.X* %p, i64 0, i32 1
   %val = bitcast i64* %B to i8*
   call void @llvm.memset.p0i8.i64(i8* %val, i8 0, i64 16, i32 1, i1 false)
   ret void
diff --git a/test/CodeGen/AArch64/arm64-this-return.ll b/test/CodeGen/AArch64/arm64-this-return.ll
index 30f5b9b064a3..3be1a69237d7 100644
--- a/test/CodeGen/AArch64/arm64-this-return.ll
+++ b/test/CodeGen/AArch64/arm64-this-return.ll
@@ -23,7 +23,7 @@ entry:
 ; CHECK: b {{_?B_ctor_base}}
   %0 = bitcast %struct.C* %this to %struct.A*
   %call = tail call %struct.A* @A_ctor_base(%struct.A* %0)
-  %1 = getelementptr inbounds %struct.C* %this, i32 0, i32 0
+  %1 = getelementptr inbounds %struct.C, %struct.C* %this, i32 0, i32 0
   %call2 = tail call %struct.B* @B_ctor_base(%struct.B* %1, i32 %x)
   ret %struct.C* %this
 }
@@ -37,7 +37,7 @@ entry:
 ; CHECK-NOT: b {{_?B_ctor_base_nothisret}}
   %0 = bitcast %struct.C* %this to %struct.A*
   %call = tail call %struct.A* @A_ctor_base_nothisret(%struct.A* %0)
-  %1 = getelementptr inbounds %struct.C* %this, i32 0, i32 0
+  %1 = getelementptr inbounds %struct.C, %struct.C* %this, i32 0, i32 0
   %call2 = tail call %struct.B* @B_ctor_base_nothisret(%struct.B* %1, i32 %x)
   ret %struct.C* %this
 }
@@ -65,7 +65,7 @@ entry:
 ; CHECK: bl {{_?B_ctor_complete}}
 ; CHECK-NOT: mov x0, {{x[0-9]+}}
 ; CHECK: b {{_?B_ctor_complete}}
-  %b = getelementptr inbounds %struct.D* %this, i32 0, i32 0
+  %b = getelementptr inbounds %struct.D, %struct.D* %this, i32 0, i32 0
   %call = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x)
   %call2 = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x)
   ret %struct.D* %this
@@ -75,9 +75,9 @@ define %struct.E* @E_ctor_base(%struct.E* %this, i32 %x) {
 entry:
 ; CHECK-LABEL: E_ctor_base:
 ; CHECK-NOT: b {{_?B_ctor_complete}}
-  %b = getelementptr inbounds %struct.E* %this, i32 0, i32 0
+  %b = getelementptr inbounds %struct.E, %struct.E* %this, i32 0, i32 0
   %call = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x)
-  %b2 = getelementptr inbounds %struct.E* %this, i32 0, i32 1
+  %b2 = getelementptr inbounds %struct.E, %struct.E* %this, i32 0, i32 1
   %call2 = tail call %struct.B* @B_ctor_complete(%struct.B* %b2, i32 %x)
   ret %struct.E* %this
 }
diff --git a/test/CodeGen/AArch64/arm64-tls-darwin.ll b/test/CodeGen/AArch64/arm64-tls-darwin.ll
index 5e8ec33ba417..fa4e833d45e1 100644
--- a/test/CodeGen/AArch64/arm64-tls-darwin.ll
+++ b/test/CodeGen/AArch64/arm64-tls-darwin.ll
@@ -13,6 +13,6 @@ define i8 @get_var() {
 ; CHECK: blr [[TLV_GET_ADDR]]
 ; CHECK: ldrb w0, [x0]
 
-  %val = load i8* @var, align 1
+  %val = load i8, i8* @var, align 1
   ret i8 %val
 }
diff --git a/test/CodeGen/AArch64/arm64-tls-dynamic-together.ll b/test/CodeGen/AArch64/arm64-tls-dynamic-together.ll
index 3daae625c84a..f94f88a1183f 100644
--- a/test/CodeGen/AArch64/arm64-tls-dynamic-together.ll
+++ b/test/CodeGen/AArch64/arm64-tls-dynamic-together.ll
@@ -10,7 +10,7 @@
 define i32 @test_generaldynamic() {
 ; CHECK-LABEL: test_generaldynamic:
 
-  %val = load i32* @general_dynamic_var
+  %val = load i32, i32* @general_dynamic_var
   ret i32 %val
 
 ; CHECK: .tlsdesccall general_dynamic_var
diff --git a/test/CodeGen/AArch64/arm64-tls-dynamics.ll b/test/CodeGen/AArch64/arm64-tls-dynamics.ll
index a89c2c5e6fd5..88700a153437 100644
--- a/test/CodeGen/AArch64/arm64-tls-dynamics.ll
+++ b/test/CodeGen/AArch64/arm64-tls-dynamics.ll
@@ -8,7 +8,7 @@
 define i32 @test_generaldynamic() {
 ; CHECK-LABEL: test_generaldynamic:
 
-  %val = load i32* @general_dynamic_var
+  %val = load i32, i32* @general_dynamic_var
   ret i32 %val
 
 ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var
@@ -72,7 +72,7 @@ define i32* @test_generaldynamic_addr() {
 define i32 @test_localdynamic() {
 ; CHECK-LABEL: test_localdynamic:
 
-  %val = load i32* @local_dynamic_var
+  %val = load i32, i32* @local_dynamic_var
   ret i32 %val
 
 ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
@@ -151,8 +151,8 @@ define i32* @test_localdynamic_addr() {
 define i32 @test_localdynamic_deduplicate() {
 ; CHECK-LABEL: test_localdynamic_deduplicate:
 
-  %val = load i32* @local_dynamic_var
-  %val2 = load i32* @local_dynamic_var2
+  %val = load i32, i32* @local_dynamic_var
+  %val2 = load i32, i32* @local_dynamic_var2
 
   %sum = add i32 %val, %val2
   ret i32 %sum
diff --git a/test/CodeGen/AArch64/arm64-tls-execs.ll b/test/CodeGen/AArch64/arm64-tls-execs.ll
index e6d3d680f417..deced6988815 100644
--- a/test/CodeGen/AArch64/arm64-tls-execs.ll
+++ b/test/CodeGen/AArch64/arm64-tls-execs.ll
@@ -5,7 +5,7 @@
 
 define i32 @test_initial_exec() {
 ; CHECK-LABEL: test_initial_exec:
-  %val = load i32* @initial_exec_var
+  %val = load i32, i32* @initial_exec_var
 
 ; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var
 ; CHECK: ldr x[[TP_OFFSET:[0-9]+]], [x[[GOTADDR]], :gottprel_lo12:initial_exec_var]
@@ -36,7 +36,7 @@ define i32* @test_initial_exec_addr() {
 
 define i32 @test_local_exec() {
 ; CHECK-LABEL: test_local_exec:
-  %val = load i32* @local_exec_var
+  %val = load i32, i32* @local_exec_var
 
 ; CHECK: mrs x[[R1:[0-9]+]], TPIDR_EL0
 ; CHECK: add x[[R2:[0-9]+]], x[[R1]], :tprel_hi12:local_exec_var
diff --git a/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll b/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll
index 923742d0370e..1b1681dc49f3 100644
--- a/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll
+++ b/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll
@@ -8,11 +8,11 @@ define i32 @func(i32 %i, i32 %j, i32 %k) #0 {
 entry:
 ; CHECK: ldr {{w[0-9]+}}, [x[[REG:[0-9]+]], #4]
 ; CHECK: str {{w[0-9]+}}, [x[[REG]], #8]
-  %0 = load i32** @a, align 8, !tbaa !1
-  %arrayidx = getelementptr inbounds i32* %0, i64 2
+  %0 = load i32*, i32** @a, align 8, !tbaa !1
+  %arrayidx = getelementptr inbounds i32, i32* %0, i64 2
   store i32 %i, i32* %arrayidx, align 4, !tbaa !5
-  %arrayidx1 = getelementptr inbounds i32* %0, i64 1
-  %1 = load i32* %arrayidx1, align 4, !tbaa !5
+  %arrayidx1 = getelementptr inbounds i32, i32* %0, i64 1
+  %1 = load i32, i32* %arrayidx1, align 4, !tbaa !5
   %add = add nsw i32 %k, %i
   store i32 %add, i32* @m, align 4, !tbaa !5
   ret i32 %1
diff --git a/test/CodeGen/AArch64/arm64-trn.ll b/test/CodeGen/AArch64/arm64-trn.ll
index 2db7a14e7549..92ccf05a3c94 100644
--- a/test/CodeGen/AArch64/arm64-trn.ll
+++ b/test/CodeGen/AArch64/arm64-trn.ll
@@ -5,8 +5,8 @@ define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: trn1.8b
 ;CHECK: trn2.8b
 ;CHECK-NEXT: add.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
 	%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
         %tmp5 = add <8 x i8> %tmp3, %tmp4
@@ -18,8 +18,8 @@ define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: trn1.4h
 ;CHECK: trn2.4h
 ;CHECK-NEXT: add.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
 	%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
         %tmp5 = add <4 x i16> %tmp3, %tmp4
@@ -32,8 +32,8 @@ define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK: zip1.2s
 ;CHECK: zip2.2s
 ;CHECK-NEXT: add.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>
 	%tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>
         %tmp5 = add <2 x i32> %tmp3, %tmp4
@@ -45,8 +45,8 @@ define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK: zip1.2s
 ;CHECK: zip2.2s
 ;CHECK-NEXT: fadd.2s
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2>
 	%tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3>
         %tmp5 = fadd <2 x float> %tmp3, %tmp4
@@ -58,8 +58,8 @@ define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK: trn1.16b
 ;CHECK: trn2.16b
 ;CHECK-NEXT: add.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
 	%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
         %tmp5 = add <16 x i8> %tmp3, %tmp4
@@ -71,8 +71,8 @@ define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK: trn1.8h
 ;CHECK: trn2.8h
 ;CHECK-NEXT: add.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
 	%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
         %tmp5 = add <8 x i16> %tmp3, %tmp4
@@ -84,8 +84,8 @@ define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK: trn1.4s
 ;CHECK: trn2.4s
 ;CHECK-NEXT: add.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
 	%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
         %tmp5 = add <4 x i32> %tmp3, %tmp4
@@ -97,8 +97,8 @@ define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK: trn1.4s
 ;CHECK: trn2.4s
 ;CHECK-NEXT: fadd.4s
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
 	%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
         %tmp5 = fadd <4 x float> %tmp3, %tmp4
@@ -112,8 +112,8 @@ define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: trn1.8b
 ;CHECK: trn2.8b
 ;CHECK-NEXT: add.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14>
 	%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
         %tmp5 = add <8 x i8> %tmp3, %tmp4
@@ -125,8 +125,8 @@ define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK: trn1.8h
 ;CHECK: trn2.8h
 ;CHECK-NEXT: add.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14>
 	%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
         %tmp5 = add <8 x i16> %tmp3, %tmp4
diff --git a/test/CodeGen/AArch64/arm64-trunc-store.ll b/test/CodeGen/AArch64/arm64-trunc-store.ll
index cf15247e1524..7cde629b33ae 100644
--- a/test/CodeGen/AArch64/arm64-trunc-store.ll
+++ b/test/CodeGen/AArch64/arm64-trunc-store.ll
@@ -25,10 +25,10 @@ define void @fct32(i32 %arg, i64 %var) {
 ; CHECK-NEXT: str w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #2]
 ; CHECK-NEXT: ret
 bb:
-  %.pre37 = load i32** @zptr32, align 8
+  %.pre37 = load i32*, i32** @zptr32, align 8
   %dec = add nsw i32 %arg, -1
   %idxprom8 = sext i32 %dec to i64
-  %arrayidx9 = getelementptr inbounds i32* %.pre37, i64 %idxprom8
+  %arrayidx9 = getelementptr inbounds i32, i32* %.pre37, i64 %idxprom8
   %tmp = trunc i64 %var to i32
   store i32 %tmp, i32* %arrayidx9, align 4
   ret void
@@ -45,10 +45,10 @@ define void @fct16(i32 %arg, i64 %var) {
 ; CHECK-NEXT: strh w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #1]
 ; CHECK-NEXT: ret
 bb:
-  %.pre37 = load i16** @zptr16, align 8
+  %.pre37 = load i16*, i16** @zptr16, align 8
   %dec = add nsw i32 %arg, -1
   %idxprom8 = sext i32 %dec to i64
-  %arrayidx9 = getelementptr inbounds i16* %.pre37, i64 %idxprom8
+  %arrayidx9 = getelementptr inbounds i16, i16* %.pre37, i64 %idxprom8
   %tmp = trunc i64 %var to i16
   store i16 %tmp, i16* %arrayidx9, align 4
   ret void
@@ -65,10 +65,10 @@ define void @fct8(i32 %arg, i64 %var) {
 ; CHECK-NEXT: sturb w1, {{\[}}[[ADDR]], #-1]
 ; CHECK-NEXT: ret
 bb:
-  %.pre37 = load i8** @zptr8, align 8
+  %.pre37 = load i8*, i8** @zptr8, align 8
   %dec = add nsw i32 %arg, -1
   %idxprom8 = sext i32 %dec to i64
-  %arrayidx9 = getelementptr inbounds i8* %.pre37, i64 %idxprom8
+  %arrayidx9 = getelementptr inbounds i8, i8* %.pre37, i64 %idxprom8
   %tmp = trunc i64 %var to i8
   store i8 %tmp, i8* %arrayidx9, align 4
   ret void
diff --git a/test/CodeGen/AArch64/arm64-umaxv.ll b/test/CodeGen/AArch64/arm64-umaxv.ll
index d523f317d087..a77f228cb156 100644
--- a/test/CodeGen/AArch64/arm64-umaxv.ll
+++ b/test/CodeGen/AArch64/arm64-umaxv.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
 
 define i32 @vmax_u8x8(<8 x i8> %a) nounwind ssp {
 ; CHECK-LABEL: vmax_u8x8:
@@ -86,7 +86,79 @@ return:
   ret i32 %retval.0
 }
 
+define <8 x i8> @test_vmaxv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
+; CHECK-LABEL: test_vmaxv_u8_used_by_laneop:
+; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2)
+  %1 = trunc i32 %0 to i8
+  %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
+  ret <8 x i8> %2
+}
+
+define <4 x i16> @test_vmaxv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
+; CHECK-LABEL: test_vmaxv_u16_used_by_laneop:
+; CHECK: umaxv.4h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a2)
+  %1 = trunc i32 %0 to i16
+  %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
+  ret <4 x i16> %2
+}
+
+define <2 x i32> @test_vmaxv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
+; CHECK-LABEL: test_vmaxv_u32_used_by_laneop:
+; CHECK: umaxp.2s v[[REGNUM:[0-9]+]], v1, v1
+; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32> %a2)
+  %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
+  ret <2 x i32> %1
+}
+
+define <16 x i8> @test_vmaxvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
+; CHECK-LABEL: test_vmaxvq_u8_used_by_laneop:
+; CHECK: umaxv.16b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a2)
+  %1 = trunc i32 %0 to i8
+  %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
+  ret <16 x i8> %2
+}
+
+define <8 x i16> @test_vmaxvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
+; CHECK-LABEL: test_vmaxvq_u16_used_by_laneop:
+; CHECK: umaxv.8h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a2)
+  %1 = trunc i32 %0 to i16
+  %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
+  ret <8 x i16> %2
+}
+
+define <4 x i32> @test_vmaxvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
+; CHECK-LABEL: test_vmaxvq_u32_used_by_laneop:
+; CHECK: umaxv.4s s[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> %a2)
+  %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
+  ret <4 x i32> %1
+}
+
 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) nounwind readnone
 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>) nounwind readnone
 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>) nounwind readnone
 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) nounwind readnone
+declare i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32>) nounwind readnone
+declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>) nounwind readnone
diff --git a/test/CodeGen/AArch64/arm64-uminv.ll b/test/CodeGen/AArch64/arm64-uminv.ll
index 3bade4b28b8f..2181db46ea96 100644
--- a/test/CodeGen/AArch64/arm64-uminv.ll
+++ b/test/CodeGen/AArch64/arm64-uminv.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
 
 define i32 @vmin_u8x8(<8 x i8> %a) nounwind ssp {
 ; CHECK-LABEL: vmin_u8x8:
@@ -86,7 +86,78 @@ return:
   ret i32 %retval.0
 }
 
+define <8 x i8> @test_vminv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
+; CHECK-LABEL: test_vminv_u8_used_by_laneop:
+; CHECK: uminv.8b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a2)
+  %1 = trunc i32 %0 to i8
+  %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
+  ret <8 x i8> %2
+}
+
+define <4 x i16> @test_vminv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
+; CHECK-LABEL: test_vminv_u16_used_by_laneop:
+; CHECK: uminv.4h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a2)
+  %1 = trunc i32 %0 to i16
+  %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
+  ret <4 x i16> %2
+}
+
+define <2 x i32> @test_vminv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
+; CHECK-LABEL: test_vminv_u32_used_by_laneop:
+; CHECK: uminp.2s v[[REGNUM:[0-9]+]], v1, v1
+; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v2i32(<2 x i32> %a2)
+  %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
+  ret <2 x i32> %1
+}
+
+define <16 x i8> @test_vminvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
+; CHECK-LABEL: test_vminvq_u8_used_by_laneop:
+; CHECK: uminv.16b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a2)
+  %1 = trunc i32 %0 to i8
+  %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
+  ret <16 x i8> %2
+}
+
+define <8 x i16> @test_vminvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
+; CHECK-LABEL: test_vminvq_u16_used_by_laneop:
+; CHECK: uminv.8h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a2)
+  %1 = trunc i32 %0 to i16
+  %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
+  ret <8 x i16> %2
+}
+
+define <4 x i32> @test_vminvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
+; CHECK-LABEL: test_vminvq_u32_used_by_laneop:
+; CHECK: uminv.4s s[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32> %a2)
+  %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
+  ret <4 x i32> %1
+}
 declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>) nounwind readnone
 declare i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16>) nounwind readnone
 declare i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16>) nounwind readnone
 declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>) nounwind readnone
+declare i32 @llvm.aarch64.neon.uminv.i32.v2i32(<2 x i32>) nounwind readnone
+declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>) nounwind readnone
diff --git a/test/CodeGen/AArch64/arm64-unaligned_ldst.ll b/test/CodeGen/AArch64/arm64-unaligned_ldst.ll
index 20b80c09f72f..dab8b0f5b6d1 100644
--- a/test/CodeGen/AArch64/arm64-unaligned_ldst.ll
+++ b/test/CodeGen/AArch64/arm64-unaligned_ldst.ll
@@ -9,7 +9,7 @@ entry:
 ; CHECK: str [[X0]], [x0]
   %tmp1 = bitcast i8* %b to i64*
   %tmp2 = bitcast i8* %a to i64*
-  %tmp3 = load i64* %tmp1, align 1
+  %tmp3 = load i64, i64* %tmp1, align 1
   store i64 %tmp3, i64* %tmp2, align 1
   ret void
 }
@@ -22,7 +22,7 @@ entry:
 ; CHECK: str [[W0]], [x0]
   %tmp1 = bitcast i8* %b to i32*
   %tmp2 = bitcast i8* %a to i32*
-  %tmp3 = load i32* %tmp1, align 1
+  %tmp3 = load i32, i32* %tmp1, align 1
   store i32 %tmp3, i32* %tmp2, align 1
   ret void
 }
@@ -35,7 +35,7 @@ entry:
 ; CHECK: strh [[W0]], [x0]
   %tmp1 = bitcast i8* %b to i16*
   %tmp2 = bitcast i8* %a to i16*
-  %tmp3 = load i16* %tmp1, align 1
+  %tmp3 = load i16, i16* %tmp1, align 1
   store i16 %tmp3, i16* %tmp2, align 1
   ret void
 }
diff --git a/test/CodeGen/AArch64/arm64-uzp.ll b/test/CodeGen/AArch64/arm64-uzp.ll
index cdd8d31c9981..517ebae6dabd 100644
--- a/test/CodeGen/AArch64/arm64-uzp.ll
+++ b/test/CodeGen/AArch64/arm64-uzp.ll
@@ -5,8 +5,8 @@ define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: uzp1.8b
 ;CHECK: uzp2.8b
 ;CHECK-NEXT: add.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
 	%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
         %tmp5 = add <8 x i8> %tmp3, %tmp4
@@ -18,8 +18,8 @@ define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: uzp1.4h
 ;CHECK: uzp2.4h
 ;CHECK-NEXT: add.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
 	%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
         %tmp5 = add <4 x i16> %tmp3, %tmp4
@@ -31,8 +31,8 @@ define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK: uzp1.16b
 ;CHECK: uzp2.16b
 ;CHECK-NEXT: add.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
 	%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
         %tmp5 = add <16 x i8> %tmp3, %tmp4
@@ -44,8 +44,8 @@ define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK: uzp1.8h
 ;CHECK: uzp2.8h
 ;CHECK-NEXT: add.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
 	%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
         %tmp5 = add <8 x i16> %tmp3, %tmp4
@@ -57,8 +57,8 @@ define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK: uzp1.4s
 ;CHECK: uzp2.4s
 ;CHECK-NEXT: add.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
 	%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
         %tmp5 = add <4 x i32> %tmp3, %tmp4
@@ -70,8 +70,8 @@ define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK: uzp1.4s
 ;CHECK: uzp2.4s
 ;CHECK-NEXT: fadd.4s
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
 	%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
         %tmp5 = fadd <4 x float> %tmp3, %tmp4
@@ -85,8 +85,8 @@ define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: uzp1.8b
 ;CHECK: uzp2.8b
 ;CHECK-NEXT: add.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14>
 	%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15>
         %tmp5 = add <8 x i8> %tmp3, %tmp4
@@ -98,8 +98,8 @@ define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK: uzp1.8h
 ;CHECK: uzp2.8h
 ;CHECK-NEXT: add.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14>
 	%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>
         %tmp5 = add <8 x i16> %tmp3, %tmp4
diff --git a/test/CodeGen/AArch64/arm64-vabs.ll b/test/CodeGen/AArch64/arm64-vabs.ll
index fae2b90e5ba1..a52c4ebf13e7 100644
--- a/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/test/CodeGen/AArch64/arm64-vabs.ll
@@ -4,8 +4,8 @@
 define <8 x i16> @sabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: sabdl8h:
 ;CHECK: sabdl.8h
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
         %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
         ret <8 x i16> %tmp4
@@ -14,8 +14,8 @@ define <8 x i16> @sabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @sabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sabdl4s:
 ;CHECK: sabdl.4s
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
         %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
         ret <4 x i32> %tmp4
@@ -24,8 +24,8 @@ define <4 x i32> @sabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @sabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sabdl2d:
 ;CHECK: sabdl.2d
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
         %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
         ret <2 x i64> %tmp4
@@ -34,8 +34,8 @@ define <2 x i64> @sabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @sabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: sabdl2_8h:
 ;CHECK: sabdl2.8h
-        %load1 = load <16 x i8>* %A
-        %load2 = load <16 x i8>* %B
+        %load1 = load <16 x i8>, <16 x i8>* %A
+        %load2 = load <16 x i8>, <16 x i8>* %B
         %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
@@ -46,8 +46,8 @@ define <8 x i16> @sabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i32> @sabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sabdl2_4s:
 ;CHECK: sabdl2.4s
-        %load1 = load <8 x i16>* %A
-        %load2 = load <8 x i16>* %B
+        %load1 = load <8 x i16>, <8 x i16>* %A
+        %load2 = load <8 x i16>, <8 x i16>* %B
         %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
         %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -58,8 +58,8 @@ define <4 x i32> @sabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i64> @sabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sabdl2_2d:
 ;CHECK: sabdl2.2d
-        %load1 = load <4 x i32>* %A
-        %load2 = load <4 x i32>* %B
+        %load1 = load <4 x i32>, <4 x i32>* %A
+        %load2 = load <4 x i32>, <4 x i32>* %B
         %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
         %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -70,8 +70,8 @@ define <2 x i64> @sabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <8 x i16> @uabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: uabdl8h:
 ;CHECK: uabdl.8h
-  %tmp1 = load <8 x i8>* %A
-  %tmp2 = load <8 x i8>* %B
+  %tmp1 = load <8 x i8>, <8 x i8>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
   %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
   ret <8 x i16> %tmp4
@@ -80,8 +80,8 @@ define <8 x i16> @uabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @uabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: uabdl4s:
 ;CHECK: uabdl.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
   %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
@@ -90,8 +90,8 @@ define <4 x i32> @uabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @uabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: uabdl2d:
 ;CHECK: uabdl.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
   %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
@@ -100,8 +100,8 @@ define <2 x i64> @uabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @uabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: uabdl2_8h:
 ;CHECK: uabdl2.8h
-  %load1 = load <16 x i8>* %A
-  %load2 = load <16 x i8>* %B
+  %load1 = load <16 x i8>, <16 x i8>* %A
+  %load2 = load <16 x i8>, <16 x i8>* %B
   %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
 
@@ -113,8 +113,8 @@ define <8 x i16> @uabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i32> @uabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: uabdl2_4s:
 ;CHECK: uabdl2.4s
-  %load1 = load <8 x i16>* %A
-  %load2 = load <8 x i16>* %B
+  %load1 = load <8 x i16>, <8 x i16>* %A
+  %load2 = load <8 x i16>, <8 x i16>* %B
   %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -125,8 +125,8 @@ define <4 x i32> @uabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i64> @uabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: uabdl2_2d:
 ;CHECK: uabdl2.2d
-  %load1 = load <4 x i32>* %A
-  %load2 = load <4 x i32>* %B
+  %load1 = load <4 x i32>, <4 x i32>* %A
+  %load2 = load <4 x i32>, <4 x i32>* %B
   %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -137,8 +137,8 @@ define <2 x i64> @uabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x float> @fabd_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: fabd_2s:
 ;CHECK: fabd.2s
-        %tmp1 = load <2 x float>* %A
-        %tmp2 = load <2 x float>* %B
+        %tmp1 = load <2 x float>, <2 x float>* %A
+        %tmp2 = load <2 x float>, <2 x float>* %B
         %tmp3 = call <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
         ret <2 x float> %tmp3
 }
@@ -146,8 +146,8 @@ define <2 x float> @fabd_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x float> @fabd_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: fabd_4s:
 ;CHECK: fabd.4s
-        %tmp1 = load <4 x float>* %A
-        %tmp2 = load <4 x float>* %B
+        %tmp1 = load <4 x float>, <4 x float>* %A
+        %tmp2 = load <4 x float>, <4 x float>* %B
         %tmp3 = call <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
         ret <4 x float> %tmp3
 }
@@ -155,8 +155,8 @@ define <4 x float> @fabd_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x double> @fabd_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
 ;CHECK-LABEL: fabd_2d:
 ;CHECK: fabd.2d
-        %tmp1 = load <2 x double>* %A
-        %tmp2 = load <2 x double>* %B
+        %tmp1 = load <2 x double>, <2 x double>* %A
+        %tmp2 = load <2 x double>, <2 x double>* %B
         %tmp3 = call <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
         ret <2 x double> %tmp3
 }
@@ -168,8 +168,8 @@ declare <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double>, <2 x double>) n
 define <8 x i8> @sabd_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: sabd_8b:
 ;CHECK: sabd.8b
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
         ret <8 x i8> %tmp3
 }
@@ -177,8 +177,8 @@ define <8 x i8> @sabd_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @sabd_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: sabd_16b:
 ;CHECK: sabd.16b
-        %tmp1 = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
         ret <16 x i8> %tmp3
 }
@@ -186,8 +186,8 @@ define <16 x i8> @sabd_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @sabd_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sabd_4h:
 ;CHECK: sabd.4h
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
         ret <4 x i16> %tmp3
 }
@@ -195,8 +195,8 @@ define <4 x i16> @sabd_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @sabd_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sabd_8h:
 ;CHECK: sabd.8h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
         ret <8 x i16> %tmp3
 }
@@ -204,8 +204,8 @@ define <8 x i16> @sabd_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @sabd_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sabd_2s:
 ;CHECK: sabd.2s
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
         ret <2 x i32> %tmp3
 }
@@ -213,8 +213,8 @@ define <2 x i32> @sabd_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @sabd_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sabd_4s:
 ;CHECK: sabd.4s
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
         ret <4 x i32> %tmp3
 }
@@ -229,8 +229,8 @@ declare <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32>, <4 x i32>) nounwind r
 define <8 x i8> @uabd_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: uabd_8b:
 ;CHECK: uabd.8b
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
         ret <8 x i8> %tmp3
 }
@@ -238,8 +238,8 @@ define <8 x i8> @uabd_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @uabd_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: uabd_16b:
 ;CHECK: uabd.16b
-        %tmp1 = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
         ret <16 x i8> %tmp3
 }
@@ -247,8 +247,8 @@ define <16 x i8> @uabd_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @uabd_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: uabd_4h:
 ;CHECK: uabd.4h
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
         ret <4 x i16> %tmp3
 }
@@ -256,8 +256,8 @@ define <4 x i16> @uabd_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @uabd_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: uabd_8h:
 ;CHECK: uabd.8h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
         ret <8 x i16> %tmp3
 }
@@ -265,8 +265,8 @@ define <8 x i16> @uabd_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @uabd_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: uabd_2s:
 ;CHECK: uabd.2s
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
         ret <2 x i32> %tmp3
 }
@@ -274,8 +274,8 @@ define <2 x i32> @uabd_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @uabd_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: uabd_4s:
 ;CHECK: uabd.4s
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
         ret <4 x i32> %tmp3
 }
@@ -290,7 +290,7 @@ declare <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32>, <4 x i32>) nounwind r
 define <8 x i8> @sqabs_8b(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: sqabs_8b:
 ;CHECK: sqabs.8b
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqabs.v8i8(<8 x i8> %tmp1)
         ret <8 x i8> %tmp3
 }
@@ -298,7 +298,7 @@ define <8 x i8> @sqabs_8b(<8 x i8>* %A) nounwind {
 define <16 x i8> @sqabs_16b(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: sqabs_16b:
 ;CHECK: sqabs.16b
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqabs.v16i8(<16 x i8> %tmp1)
         ret <16 x i8> %tmp3
 }
@@ -306,7 +306,7 @@ define <16 x i8> @sqabs_16b(<16 x i8>* %A) nounwind {
 define <4 x i16> @sqabs_4h(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqabs_4h:
 ;CHECK: sqabs.4h
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqabs.v4i16(<4 x i16> %tmp1)
         ret <4 x i16> %tmp3
 }
@@ -314,7 +314,7 @@ define <4 x i16> @sqabs_4h(<4 x i16>* %A) nounwind {
 define <8 x i16> @sqabs_8h(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqabs_8h:
 ;CHECK: sqabs.8h
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqabs.v8i16(<8 x i16> %tmp1)
         ret <8 x i16> %tmp3
 }
@@ -322,7 +322,7 @@ define <8 x i16> @sqabs_8h(<8 x i16>* %A) nounwind {
 define <2 x i32> @sqabs_2s(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqabs_2s:
 ;CHECK: sqabs.2s
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqabs.v2i32(<2 x i32> %tmp1)
         ret <2 x i32> %tmp3
 }
@@ -330,7 +330,7 @@ define <2 x i32> @sqabs_2s(<2 x i32>* %A) nounwind {
 define <4 x i32> @sqabs_4s(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqabs_4s:
 ;CHECK: sqabs.4s
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqabs.v4i32(<4 x i32> %tmp1)
         ret <4 x i32> %tmp3
 }
@@ -345,7 +345,7 @@ declare <4 x i32> @llvm.aarch64.neon.sqabs.v4i32(<4 x i32>) nounwind readnone
 define <8 x i8> @sqneg_8b(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: sqneg_8b:
 ;CHECK: sqneg.8b
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqneg.v8i8(<8 x i8> %tmp1)
         ret <8 x i8> %tmp3
 }
@@ -353,7 +353,7 @@ define <8 x i8> @sqneg_8b(<8 x i8>* %A) nounwind {
 define <16 x i8> @sqneg_16b(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: sqneg_16b:
 ;CHECK: sqneg.16b
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqneg.v16i8(<16 x i8> %tmp1)
         ret <16 x i8> %tmp3
 }
@@ -361,7 +361,7 @@ define <16 x i8> @sqneg_16b(<16 x i8>* %A) nounwind {
 define <4 x i16> @sqneg_4h(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqneg_4h:
 ;CHECK: sqneg.4h
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqneg.v4i16(<4 x i16> %tmp1)
         ret <4 x i16> %tmp3
 }
@@ -369,7 +369,7 @@ define <4 x i16> @sqneg_4h(<4 x i16>* %A) nounwind {
 define <8 x i16> @sqneg_8h(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqneg_8h:
 ;CHECK: sqneg.8h
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqneg.v8i16(<8 x i16> %tmp1)
         ret <8 x i16> %tmp3
 }
@@ -377,7 +377,7 @@ define <8 x i16> @sqneg_8h(<8 x i16>* %A) nounwind {
 define <2 x i32> @sqneg_2s(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqneg_2s:
 ;CHECK: sqneg.2s
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqneg.v2i32(<2 x i32> %tmp1)
         ret <2 x i32> %tmp3
 }
@@ -385,7 +385,7 @@ define <2 x i32> @sqneg_2s(<2 x i32>* %A) nounwind {
 define <4 x i32> @sqneg_4s(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqneg_4s:
 ;CHECK: sqneg.4s
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqneg.v4i32(<4 x i32> %tmp1)
         ret <4 x i32> %tmp3
 }
@@ -400,7 +400,7 @@ declare <4 x i32> @llvm.aarch64.neon.sqneg.v4i32(<4 x i32>) nounwind readnone
 define <8 x i8> @abs_8b(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: abs_8b:
 ;CHECK: abs.8b
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.abs.v8i8(<8 x i8> %tmp1)
         ret <8 x i8> %tmp3
 }
@@ -408,7 +408,7 @@ define <8 x i8> @abs_8b(<8 x i8>* %A) nounwind {
 define <16 x i8> @abs_16b(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: abs_16b:
 ;CHECK: abs.16b
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.abs.v16i8(<16 x i8> %tmp1)
         ret <16 x i8> %tmp3
 }
@@ -416,7 +416,7 @@ define <16 x i8> @abs_16b(<16 x i8>* %A) nounwind {
 define <4 x i16> @abs_4h(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: abs_4h:
 ;CHECK: abs.4h
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.abs.v4i16(<4 x i16> %tmp1)
         ret <4 x i16> %tmp3
 }
@@ -424,7 +424,7 @@ define <4 x i16> @abs_4h(<4 x i16>* %A) nounwind {
 define <8 x i16> @abs_8h(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: abs_8h:
 ;CHECK: abs.8h
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.abs.v8i16(<8 x i16> %tmp1)
         ret <8 x i16> %tmp3
 }
@@ -432,7 +432,7 @@ define <8 x i16> @abs_8h(<8 x i16>* %A) nounwind {
 define <2 x i32> @abs_2s(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: abs_2s:
 ;CHECK: abs.2s
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.abs.v2i32(<2 x i32> %tmp1)
         ret <2 x i32> %tmp3
 }
@@ -440,7 +440,7 @@ define <2 x i32> @abs_2s(<2 x i32>* %A) nounwind {
 define <4 x i32> @abs_4s(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: abs_4s:
 ;CHECK: abs.4s
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.abs.v4i32(<4 x i32> %tmp1)
         ret <4 x i32> %tmp3
 }
@@ -471,9 +471,9 @@ declare i64 @llvm.aarch64.neon.abs.i64(i64) nounwind readnone
 define <8 x i16> @sabal8h(<8 x i8>* %A, <8 x i8>* %B,  <8 x i16>* %C) nounwind {
 ;CHECK-LABEL: sabal8h:
 ;CHECK: sabal.8h
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
-        %tmp3 = load <8 x i16>* %C
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
+        %tmp3 = load <8 x i16>, <8 x i16>* %C
         %tmp4 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
         %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
         %tmp5 = add <8 x i16> %tmp3, %tmp4.1
@@ -483,9 +483,9 @@ define <8 x i16> @sabal8h(<8 x i8>* %A, <8 x i8>* %B,  <8 x i16>* %C) nounwind {
 define <4 x i32> @sabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: sabal4s:
 ;CHECK: sabal.4s
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
-        %tmp3 = load <4 x i32>* %C
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
+        %tmp3 = load <4 x i32>, <4 x i32>* %C
         %tmp4 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
         %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
         %tmp5 = add <4 x i32> %tmp3, %tmp4.1
@@ -495,9 +495,9 @@ define <4 x i32> @sabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind
 define <2 x i64> @sabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
 ;CHECK-LABEL: sabal2d:
 ;CHECK: sabal.2d
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
-        %tmp3 = load <2 x i64>* %C
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
+        %tmp3 = load <2 x i64>, <2 x i64>* %C
         %tmp4 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
         %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
         %tmp4.1.1 = zext <2 x i32> %tmp4 to <2 x i64>
@@ -508,9 +508,9 @@ define <2 x i64> @sabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind
 define <8 x i16> @sabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwind {
 ;CHECK-LABEL: sabal2_8h:
 ;CHECK: sabal2.8h
-        %load1 = load <16 x i8>* %A
-        %load2 = load <16 x i8>* %B
-        %tmp3 = load <8 x i16>* %C
+        %load1 = load <16 x i8>, <16 x i8>* %A
+        %load2 = load <16 x i8>, <16 x i8>* %B
+        %tmp3 = load <8 x i16>, <8 x i16>* %C
         %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         %tmp4 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
@@ -522,9 +522,9 @@ define <8 x i16> @sabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwin
 define <4 x i32> @sabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: sabal2_4s:
 ;CHECK: sabal2.4s
-        %load1 = load <8 x i16>* %A
-        %load2 = load <8 x i16>* %B
-        %tmp3 = load <4 x i32>* %C
+        %load1 = load <8 x i16>, <8 x i16>* %A
+        %load2 = load <8 x i16>, <8 x i16>* %B
+        %tmp3 = load <4 x i32>, <4 x i32>* %C
         %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
         %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
         %tmp4 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -536,9 +536,9 @@ define <4 x i32> @sabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwin
 define <2 x i64> @sabal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
 ;CHECK-LABEL: sabal2_2d:
 ;CHECK: sabal2.2d
-        %load1 = load <4 x i32>* %A
-        %load2 = load <4 x i32>* %B
-        %tmp3 = load <2 x i64>* %C
+        %load1 = load <4 x i32>, <4 x i32>* %A
+        %load2 = load <4 x i32>, <4 x i32>* %B
+        %tmp3 = load <2 x i64>, <2 x i64>* %C
         %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
         %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
         %tmp4 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -550,9 +550,9 @@ define <2 x i64> @sabal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwin
 define <8 x i16> @uabal8h(<8 x i8>* %A, <8 x i8>* %B,  <8 x i16>* %C) nounwind {
 ;CHECK-LABEL: uabal8h:
 ;CHECK: uabal.8h
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
-        %tmp3 = load <8 x i16>* %C
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
+        %tmp3 = load <8 x i16>, <8 x i16>* %C
         %tmp4 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
         %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
         %tmp5 = add <8 x i16> %tmp3, %tmp4.1
@@ -562,9 +562,9 @@ define <8 x i16> @uabal8h(<8 x i8>* %A, <8 x i8>* %B,  <8 x i16>* %C) nounwind {
 define <4 x i32> @uabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: uabal4s:
 ;CHECK: uabal.4s
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
-        %tmp3 = load <4 x i32>* %C
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
+        %tmp3 = load <4 x i32>, <4 x i32>* %C
         %tmp4 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
         %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
         %tmp5 = add <4 x i32> %tmp3, %tmp4.1
@@ -574,9 +574,9 @@ define <4 x i32> @uabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind
 define <2 x i64> @uabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
 ;CHECK-LABEL: uabal2d:
 ;CHECK: uabal.2d
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
-        %tmp3 = load <2 x i64>* %C
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
+        %tmp3 = load <2 x i64>, <2 x i64>* %C
         %tmp4 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
         %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
         %tmp5 = add <2 x i64> %tmp3, %tmp4.1
@@ -586,9 +586,9 @@ define <2 x i64> @uabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind
 define <8 x i16> @uabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwind {
 ;CHECK-LABEL: uabal2_8h:
 ;CHECK: uabal2.8h
-        %load1 = load <16 x i8>* %A
-        %load2 = load <16 x i8>* %B
-        %tmp3 = load <8 x i16>* %C
+        %load1 = load <16 x i8>, <16 x i8>* %A
+        %load2 = load <16 x i8>, <16 x i8>* %B
+        %tmp3 = load <8 x i16>, <8 x i16>* %C
         %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         %tmp4 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
@@ -600,9 +600,9 @@ define <8 x i16> @uabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwin
 define <4 x i32> @uabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: uabal2_4s:
 ;CHECK: uabal2.4s
-        %load1 = load <8 x i16>* %A
-        %load2 = load <8 x i16>* %B
-        %tmp3 = load <4 x i32>* %C
+        %load1 = load <8 x i16>, <8 x i16>* %A
+        %load2 = load <8 x i16>, <8 x i16>* %B
+        %tmp3 = load <4 x i32>, <4 x i32>* %C
         %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
         %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
         %tmp4 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -614,9 +614,9 @@ define <4 x i32> @uabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwin
 define <2 x i64> @uabal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
 ;CHECK-LABEL: uabal2_2d:
 ;CHECK: uabal2.2d
-        %load1 = load <4 x i32>* %A
-        %load2 = load <4 x i32>* %B
-        %tmp3 = load <2 x i64>* %C
+        %load1 = load <4 x i32>, <4 x i32>* %A
+        %load2 = load <4 x i32>, <4 x i32>* %B
+        %tmp3 = load <2 x i64>, <2 x i64>* %C
         %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
         %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
         %tmp4 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -628,10 +628,10 @@ define <2 x i64> @uabal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwin
 define <8 x i8> @saba_8b(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ;CHECK-LABEL: saba_8b:
 ;CHECK: saba.8b
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
-        %tmp4 = load <8 x i8>* %C
+        %tmp4 = load <8 x i8>, <8 x i8>* %C
         %tmp5 = add <8 x i8> %tmp3, %tmp4
         ret <8 x i8> %tmp5
 }
@@ -639,10 +639,10 @@ define <8 x i8> @saba_8b(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 define <16 x i8> @saba_16b(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
 ;CHECK-LABEL: saba_16b:
 ;CHECK: saba.16b
-        %tmp1 = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
-        %tmp4 = load <16 x i8>* %C
+        %tmp4 = load <16 x i8>, <16 x i8>* %C
         %tmp5 = add <16 x i8> %tmp3, %tmp4
         ret <16 x i8> %tmp5
 }
@@ -650,10 +650,10 @@ define <16 x i8> @saba_16b(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
 define <4 x i16> @saba_4h(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK-LABEL: saba_4h:
 ;CHECK: saba.4h
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
-        %tmp4 = load <4 x i16>* %C
+        %tmp4 = load <4 x i16>, <4 x i16>* %C
         %tmp5 = add <4 x i16> %tmp3, %tmp4
         ret <4 x i16> %tmp5
 }
@@ -661,10 +661,10 @@ define <4 x i16> @saba_4h(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 define <8 x i16> @saba_8h(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
 ;CHECK-LABEL: saba_8h:
 ;CHECK: saba.8h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
-        %tmp4 = load <8 x i16>* %C
+        %tmp4 = load <8 x i16>, <8 x i16>* %C
         %tmp5 = add <8 x i16> %tmp3, %tmp4
         ret <8 x i16> %tmp5
 }
@@ -672,10 +672,10 @@ define <8 x i16> @saba_8h(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
 define <2 x i32> @saba_2s(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK-LABEL: saba_2s:
 ;CHECK: saba.2s
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
-        %tmp4 = load <2 x i32>* %C
+        %tmp4 = load <2 x i32>, <2 x i32>* %C
         %tmp5 = add <2 x i32> %tmp3, %tmp4
         ret <2 x i32> %tmp5
 }
@@ -683,10 +683,10 @@ define <2 x i32> @saba_2s(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 define <4 x i32> @saba_4s(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: saba_4s:
 ;CHECK: saba.4s
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
-        %tmp4 = load <4 x i32>* %C
+        %tmp4 = load <4 x i32>, <4 x i32>* %C
         %tmp5 = add <4 x i32> %tmp3, %tmp4
         ret <4 x i32> %tmp5
 }
@@ -694,10 +694,10 @@ define <4 x i32> @saba_4s(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind
 define <8 x i8> @uaba_8b(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ;CHECK-LABEL: uaba_8b:
 ;CHECK: uaba.8b
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
-        %tmp4 = load <8 x i8>* %C
+        %tmp4 = load <8 x i8>, <8 x i8>* %C
         %tmp5 = add <8 x i8> %tmp3, %tmp4
         ret <8 x i8> %tmp5
 }
@@ -705,10 +705,10 @@ define <8 x i8> @uaba_8b(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 define <16 x i8> @uaba_16b(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
 ;CHECK-LABEL: uaba_16b:
 ;CHECK: uaba.16b
-        %tmp1 = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
-        %tmp4 = load <16 x i8>* %C
+        %tmp4 = load <16 x i8>, <16 x i8>* %C
         %tmp5 = add <16 x i8> %tmp3, %tmp4
         ret <16 x i8> %tmp5
 }
@@ -716,10 +716,10 @@ define <16 x i8> @uaba_16b(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
 define <4 x i16> @uaba_4h(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK-LABEL: uaba_4h:
 ;CHECK: uaba.4h
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
-        %tmp4 = load <4 x i16>* %C
+        %tmp4 = load <4 x i16>, <4 x i16>* %C
         %tmp5 = add <4 x i16> %tmp3, %tmp4
         ret <4 x i16> %tmp5
 }
@@ -727,10 +727,10 @@ define <4 x i16> @uaba_4h(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 define <8 x i16> @uaba_8h(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
 ;CHECK-LABEL: uaba_8h:
 ;CHECK: uaba.8h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
-        %tmp4 = load <8 x i16>* %C
+        %tmp4 = load <8 x i16>, <8 x i16>* %C
         %tmp5 = add <8 x i16> %tmp3, %tmp4
         ret <8 x i16> %tmp5
 }
@@ -738,10 +738,10 @@ define <8 x i16> @uaba_8h(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
 define <2 x i32> @uaba_2s(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK-LABEL: uaba_2s:
 ;CHECK: uaba.2s
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
-        %tmp4 = load <2 x i32>* %C
+        %tmp4 = load <2 x i32>, <2 x i32>* %C
         %tmp5 = add <2 x i32> %tmp3, %tmp4
         ret <2 x i32> %tmp5
 }
@@ -749,10 +749,10 @@ define <2 x i32> @uaba_2s(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 define <4 x i32> @uaba_4s(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: uaba_4s:
 ;CHECK: uaba.4s
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
-        %tmp4 = load <4 x i32>* %C
+        %tmp4 = load <4 x i32>, <4 x i32>* %C
         %tmp5 = add <4 x i32> %tmp3, %tmp4
         ret <4 x i32> %tmp5
 }
diff --git a/test/CodeGen/AArch64/arm64-vadd.ll b/test/CodeGen/AArch64/arm64-vadd.ll
index 9ed8aa6d7c5d..e3d8dd256956 100644
--- a/test/CodeGen/AArch64/arm64-vadd.ll
+++ b/test/CodeGen/AArch64/arm64-vadd.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @addhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: addhn8b:
 ;CHECK: addhn.8b
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
         ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @addhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i16> @addhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: addhn4h:
 ;CHECK: addhn.4h
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
         ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @addhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i32> @addhn2s(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: addhn2s:
 ;CHECK: addhn.2s
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.addhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
         ret <2 x i32> %tmp3
 }
@@ -65,8 +65,8 @@ declare <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16>, <8 x i16>) nounwind re
 define <8 x i8> @raddhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: raddhn8b:
 ;CHECK: raddhn.8b
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
         ret <8 x i8> %tmp3
 }
@@ -74,8 +74,8 @@ define <8 x i8> @raddhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i16> @raddhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: raddhn4h:
 ;CHECK: raddhn.4h
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
         ret <4 x i16> %tmp3
 }
@@ -83,8 +83,8 @@ define <4 x i16> @raddhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i32> @raddhn2s(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: raddhn2s:
 ;CHECK: raddhn.2s
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
         ret <2 x i32> %tmp3
 }
@@ -126,8 +126,8 @@ declare <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16>, <8 x i16>) nounwind r
 define <8 x i16> @saddl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: saddl8h:
 ;CHECK: saddl.8h
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
   %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
   %tmp5 = add <8 x i16> %tmp3, %tmp4
@@ -137,8 +137,8 @@ define <8 x i16> @saddl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @saddl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: saddl4s:
 ;CHECK: saddl.4s
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
   %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
   %tmp5 = add <4 x i32> %tmp3, %tmp4
@@ -148,8 +148,8 @@ define <4 x i32> @saddl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @saddl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: saddl2d:
 ;CHECK: saddl.2d
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
   %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
   %tmp5 = add <2 x i64> %tmp3, %tmp4
@@ -207,8 +207,8 @@ define <2 x i64> @saddl2_2d(<4 x i32> %a, <4 x i32> %b) nounwind  {
 define <8 x i16> @uaddl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: uaddl8h:
 ;CHECK: uaddl.8h
-  %tmp1 = load <8 x i8>* %A
-  %tmp2 = load <8 x i8>* %B
+  %tmp1 = load <8 x i8>, <8 x i8>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
   %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
   %tmp5 = add <8 x i16> %tmp3, %tmp4
@@ -218,8 +218,8 @@ define <8 x i16> @uaddl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @uaddl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: uaddl4s:
 ;CHECK: uaddl.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
   %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
   %tmp5 = add <4 x i32> %tmp3, %tmp4
@@ -229,8 +229,8 @@ define <4 x i32> @uaddl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @uaddl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: uaddl2d:
 ;CHECK: uaddl.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
   %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
   %tmp5 = add <2 x i64> %tmp3, %tmp4
@@ -289,8 +289,8 @@ define <2 x i64> @uaddl2_2d(<4 x i32> %a, <4 x i32> %b) nounwind  {
 define <8 x i16> @uaddw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: uaddw8h:
 ;CHECK: uaddw.8h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
   %tmp4 = add <8 x i16> %tmp1, %tmp3
         ret <8 x i16> %tmp4
@@ -299,8 +299,8 @@ define <8 x i16> @uaddw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @uaddw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: uaddw4s:
 ;CHECK: uaddw.4s
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
   %tmp4 = add <4 x i32> %tmp1, %tmp3
         ret <4 x i32> %tmp4
@@ -309,8 +309,8 @@ define <4 x i32> @uaddw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @uaddw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: uaddw2d:
 ;CHECK: uaddw.2d
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
   %tmp4 = add <2 x i64> %tmp1, %tmp3
         ret <2 x i64> %tmp4
@@ -319,9 +319,9 @@ define <2 x i64> @uaddw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @uaddw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: uaddw2_8h:
 ;CHECK: uaddw2.8h
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
 
-        %tmp2 = load <16 x i8>* %B
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         %ext2 = zext <8 x i8> %high2 to <8 x i16>
 
@@ -332,9 +332,9 @@ define <8 x i16> @uaddw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 define <4 x i32> @uaddw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: uaddw2_4s:
 ;CHECK: uaddw2.4s
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
 
-        %tmp2 = load <8 x i16>* %B
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
         %ext2 = zext <4 x i16> %high2 to <4 x i32>
 
@@ -345,9 +345,9 @@ define <4 x i32> @uaddw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 define <2 x i64> @uaddw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: uaddw2_2d:
 ;CHECK: uaddw2.2d
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
 
-        %tmp2 = load <4 x i32>* %B
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
         %ext2 = zext <2 x i32> %high2 to <2 x i64>
 
@@ -358,8 +358,8 @@ define <2 x i64> @uaddw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind {
 define <8 x i16> @saddw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: saddw8h:
 ;CHECK: saddw.8h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
         %tmp4 = add <8 x i16> %tmp1, %tmp3
         ret <8 x i16> %tmp4
@@ -368,8 +368,8 @@ define <8 x i16> @saddw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @saddw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: saddw4s:
 ;CHECK: saddw.4s
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
         %tmp4 = add <4 x i32> %tmp1, %tmp3
         ret <4 x i32> %tmp4
@@ -378,8 +378,8 @@ define <4 x i32> @saddw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @saddw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: saddw2d:
 ;CHECK: saddw.2d
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
         %tmp4 = add <2 x i64> %tmp1, %tmp3
         ret <2 x i64> %tmp4
@@ -388,9 +388,9 @@ define <2 x i64> @saddw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @saddw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: saddw2_8h:
 ;CHECK: saddw2.8h
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
 
-        %tmp2 = load <16 x i8>* %B
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         %ext2 = sext <8 x i8> %high2 to <8 x i16>
 
@@ -401,9 +401,9 @@ define <8 x i16> @saddw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 define <4 x i32> @saddw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: saddw2_4s:
 ;CHECK: saddw2.4s
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
 
-        %tmp2 = load <8 x i16>* %B
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
         %ext2 = sext <4 x i16> %high2 to <4 x i32>
 
@@ -414,9 +414,9 @@ define <4 x i32> @saddw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 define <2 x i64> @saddw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: saddw2_2d:
 ;CHECK: saddw2.2d
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
 
-        %tmp2 = load <4 x i32>* %B
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
         %ext2 = sext <2 x i32> %high2 to <2 x i64>
 
@@ -427,7 +427,7 @@ define <2 x i64> @saddw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind {
 define <4 x i16> @saddlp4h(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: saddlp4h:
 ;CHECK: saddlp.4h
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %tmp1)
         ret <4 x i16> %tmp3
 }
@@ -435,7 +435,7 @@ define <4 x i16> @saddlp4h(<8 x i8>* %A) nounwind {
 define <2 x i32> @saddlp2s(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: saddlp2s:
 ;CHECK: saddlp.2s
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %tmp1)
         ret <2 x i32> %tmp3
 }
@@ -443,7 +443,7 @@ define <2 x i32> @saddlp2s(<4 x i16>* %A) nounwind {
 define <1 x i64> @saddlp1d(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: saddlp1d:
 ;CHECK: saddlp.1d
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp3 = call <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32> %tmp1)
         ret <1 x i64> %tmp3
 }
@@ -451,7 +451,7 @@ define <1 x i64> @saddlp1d(<2 x i32>* %A) nounwind {
 define <8 x i16> @saddlp8h(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: saddlp8h:
 ;CHECK: saddlp.8h
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %tmp1)
         ret <8 x i16> %tmp3
 }
@@ -459,7 +459,7 @@ define <8 x i16> @saddlp8h(<16 x i8>* %A) nounwind {
 define <4 x i32> @saddlp4s(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: saddlp4s:
 ;CHECK: saddlp.4s
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %tmp1)
         ret <4 x i32> %tmp3
 }
@@ -467,7 +467,7 @@ define <4 x i32> @saddlp4s(<8 x i16>* %A) nounwind {
 define <2 x i64> @saddlp2d(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: saddlp2d:
 ;CHECK: saddlp.2d
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> %tmp1)
         ret <2 x i64> %tmp3
 }
@@ -483,7 +483,7 @@ declare <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32>) nounwind read
 define <4 x i16> @uaddlp4h(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: uaddlp4h:
 ;CHECK: uaddlp.4h
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %tmp1)
         ret <4 x i16> %tmp3
 }
@@ -491,7 +491,7 @@ define <4 x i16> @uaddlp4h(<8 x i8>* %A) nounwind {
 define <2 x i32> @uaddlp2s(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: uaddlp2s:
 ;CHECK: uaddlp.2s
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %tmp1)
         ret <2 x i32> %tmp3
 }
@@ -499,7 +499,7 @@ define <2 x i32> @uaddlp2s(<4 x i16>* %A) nounwind {
 define <1 x i64> @uaddlp1d(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: uaddlp1d:
 ;CHECK: uaddlp.1d
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp3 = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %tmp1)
         ret <1 x i64> %tmp3
 }
@@ -507,7 +507,7 @@ define <1 x i64> @uaddlp1d(<2 x i32>* %A) nounwind {
 define <8 x i16> @uaddlp8h(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: uaddlp8h:
 ;CHECK: uaddlp.8h
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %tmp1)
         ret <8 x i16> %tmp3
 }
@@ -515,7 +515,7 @@ define <8 x i16> @uaddlp8h(<16 x i8>* %A) nounwind {
 define <4 x i32> @uaddlp4s(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: uaddlp4s:
 ;CHECK: uaddlp.4s
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %tmp1)
         ret <4 x i32> %tmp3
 }
@@ -523,7 +523,7 @@ define <4 x i32> @uaddlp4s(<8 x i16>* %A) nounwind {
 define <2 x i64> @uaddlp2d(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: uaddlp2d:
 ;CHECK: uaddlp.2d
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %tmp1)
         ret <2 x i64> %tmp3
 }
@@ -539,9 +539,9 @@ declare <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32>) nounwind read
 define <4 x i16> @sadalp4h(<8 x i8>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sadalp4h:
 ;CHECK: sadalp.4h
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %tmp1)
-        %tmp4 = load <4 x i16>* %B
+        %tmp4 = load <4 x i16>, <4 x i16>* %B
         %tmp5 = add <4 x i16> %tmp3, %tmp4
         ret <4 x i16> %tmp5
 }
@@ -549,9 +549,9 @@ define <4 x i16> @sadalp4h(<8 x i8>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @sadalp2s(<4 x i16>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sadalp2s:
 ;CHECK: sadalp.2s
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %tmp1)
-        %tmp4 = load <2 x i32>* %B
+        %tmp4 = load <2 x i32>, <2 x i32>* %B
         %tmp5 = add <2 x i32> %tmp3, %tmp4
         ret <2 x i32> %tmp5
 }
@@ -559,9 +559,9 @@ define <2 x i32> @sadalp2s(<4 x i16>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @sadalp8h(<16 x i8>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sadalp8h:
 ;CHECK: sadalp.8h
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %tmp1)
-        %tmp4 = load <8 x i16>* %B
+        %tmp4 = load <8 x i16>, <8 x i16>* %B
         %tmp5 = add <8 x i16> %tmp3, %tmp4
         ret <8 x i16> %tmp5
 }
@@ -569,9 +569,9 @@ define <8 x i16> @sadalp8h(<16 x i8>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @sadalp4s(<8 x i16>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sadalp4s:
 ;CHECK: sadalp.4s
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %tmp1)
-        %tmp4 = load <4 x i32>* %B
+        %tmp4 = load <4 x i32>, <4 x i32>* %B
         %tmp5 = add <4 x i32> %tmp3, %tmp4
         ret <4 x i32> %tmp5
 }
@@ -579,9 +579,9 @@ define <4 x i32> @sadalp4s(<8 x i16>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @sadalp2d(<4 x i32>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: sadalp2d:
 ;CHECK: sadalp.2d
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> %tmp1)
-        %tmp4 = load <2 x i64>* %B
+        %tmp4 = load <2 x i64>, <2 x i64>* %B
         %tmp5 = add <2 x i64> %tmp3, %tmp4
         ret <2 x i64> %tmp5
 }
@@ -589,9 +589,9 @@ define <2 x i64> @sadalp2d(<4 x i32>* %A, <2 x i64>* %B) nounwind {
 define <4 x i16> @uadalp4h(<8 x i8>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: uadalp4h:
 ;CHECK: uadalp.4h
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %tmp1)
-        %tmp4 = load <4 x i16>* %B
+        %tmp4 = load <4 x i16>, <4 x i16>* %B
         %tmp5 = add <4 x i16> %tmp3, %tmp4
         ret <4 x i16> %tmp5
 }
@@ -599,9 +599,9 @@ define <4 x i16> @uadalp4h(<8 x i8>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @uadalp2s(<4 x i16>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: uadalp2s:
 ;CHECK: uadalp.2s
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %tmp1)
-        %tmp4 = load <2 x i32>* %B
+        %tmp4 = load <2 x i32>, <2 x i32>* %B
         %tmp5 = add <2 x i32> %tmp3, %tmp4
         ret <2 x i32> %tmp5
 }
@@ -609,9 +609,9 @@ define <2 x i32> @uadalp2s(<4 x i16>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @uadalp8h(<16 x i8>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: uadalp8h:
 ;CHECK: uadalp.8h
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %tmp1)
-        %tmp4 = load <8 x i16>* %B
+        %tmp4 = load <8 x i16>, <8 x i16>* %B
         %tmp5 = add <8 x i16> %tmp3, %tmp4
         ret <8 x i16> %tmp5
 }
@@ -619,9 +619,9 @@ define <8 x i16> @uadalp8h(<16 x i8>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @uadalp4s(<8 x i16>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: uadalp4s:
 ;CHECK: uadalp.4s
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %tmp1)
-        %tmp4 = load <4 x i32>* %B
+        %tmp4 = load <4 x i32>, <4 x i32>* %B
         %tmp5 = add <4 x i32> %tmp3, %tmp4
         ret <4 x i32> %tmp5
 }
@@ -629,9 +629,9 @@ define <4 x i32> @uadalp4s(<8 x i16>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @uadalp2d(<4 x i32>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: uadalp2d:
 ;CHECK: uadalp.2d
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %tmp1)
-        %tmp4 = load <2 x i64>* %B
+        %tmp4 = load <2 x i64>, <2 x i64>* %B
         %tmp5 = add <2 x i64> %tmp3, %tmp4
         ret <2 x i64> %tmp5
 }
@@ -639,8 +639,8 @@ define <2 x i64> @uadalp2d(<4 x i32>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @addp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: addp_8b:
 ;CHECK: addp.8b
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.addp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
         ret <8 x i8> %tmp3
 }
@@ -648,8 +648,8 @@ define <8 x i8> @addp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @addp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: addp_16b:
 ;CHECK: addp.16b
-        %tmp1 = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.addp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
         ret <16 x i8> %tmp3
 }
@@ -657,8 +657,8 @@ define <16 x i8> @addp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @addp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: addp_4h:
 ;CHECK: addp.4h
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
         ret <4 x i16> %tmp3
 }
@@ -666,8 +666,8 @@ define <4 x i16> @addp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @addp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: addp_8h:
 ;CHECK: addp.8h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.addp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
         ret <8 x i16> %tmp3
 }
@@ -675,8 +675,8 @@ define <8 x i16> @addp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @addp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: addp_2s:
 ;CHECK: addp.2s
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.addp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
         ret <2 x i32> %tmp3
 }
@@ -684,8 +684,8 @@ define <2 x i32> @addp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @addp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: addp_4s:
 ;CHECK: addp.4s
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.addp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
         ret <4 x i32> %tmp3
 }
@@ -693,8 +693,8 @@ define <4 x i32> @addp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @addp_2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: addp_2d:
 ;CHECK: addp.2d
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
         ret <2 x i64> %tmp3
 }
@@ -710,8 +710,8 @@ declare <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64>, <2 x i64>) nounwind r
 define <2 x float> @faddp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: faddp_2s:
 ;CHECK: faddp.2s
-        %tmp1 = load <2 x float>* %A
-        %tmp2 = load <2 x float>* %B
+        %tmp1 = load <2 x float>, <2 x float>* %A
+        %tmp2 = load <2 x float>, <2 x float>* %B
         %tmp3 = call <2 x float> @llvm.aarch64.neon.addp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
         ret <2 x float> %tmp3
 }
@@ -719,8 +719,8 @@ define <2 x float> @faddp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x float> @faddp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: faddp_4s:
 ;CHECK: faddp.4s
-        %tmp1 = load <4 x float>* %A
-        %tmp2 = load <4 x float>* %B
+        %tmp1 = load <4 x float>, <4 x float>* %A
+        %tmp2 = load <4 x float>, <4 x float>* %B
         %tmp3 = call <4 x float> @llvm.aarch64.neon.addp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
         ret <4 x float> %tmp3
 }
@@ -728,8 +728,8 @@ define <4 x float> @faddp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x double> @faddp_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
 ;CHECK-LABEL: faddp_2d:
 ;CHECK: faddp.2d
-        %tmp1 = load <2 x double>* %A
-        %tmp2 = load <2 x double>* %B
+        %tmp1 = load <2 x double>, <2 x double>* %A
+        %tmp2 = load <2 x double>, <2 x double>* %B
         %tmp3 = call <2 x double> @llvm.aarch64.neon.addp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
         ret <2 x double> %tmp3
 }
@@ -805,8 +805,8 @@ define <2 x i64> @ssubl2_duplhs(i32 %lhs, <4 x i32> %rhs) {
 define <8 x i8> @addhn8b_natural(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: addhn8b_natural:
 ;CHECK: addhn.8b
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %sum = add <8 x i16> %tmp1, %tmp2
         %high_bits = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
         %narrowed = trunc <8 x i16> %high_bits to <8 x i8>
@@ -816,8 +816,8 @@ define <8 x i8> @addhn8b_natural(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i16> @addhn4h_natural(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: addhn4h_natural:
 ;CHECK: addhn.4h
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %sum = add <4 x i32> %tmp1, %tmp2
         %high_bits = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>
         %narrowed = trunc <4 x i32> %high_bits to <4 x i16>
@@ -827,8 +827,8 @@ define <4 x i16> @addhn4h_natural(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i32> @addhn2s_natural(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: addhn2s_natural:
 ;CHECK: addhn.2s
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %sum = add <2 x i64> %tmp1, %tmp2
         %high_bits = lshr <2 x i64> %sum, <i64 32, i64 32>
         %narrowed = trunc <2 x i64> %high_bits to <2 x i32>
@@ -838,8 +838,8 @@ define <2 x i32> @addhn2s_natural(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @addhn2_16b_natural(<8 x i8> %low, <8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: addhn2_16b_natural:
 ;CHECK: addhn2.16b
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %sum = add <8 x i16> %tmp1, %tmp2
         %high_bits = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
         %narrowed = trunc <8 x i16> %high_bits to <8 x i8>
@@ -850,8 +850,8 @@ define <16 x i8> @addhn2_16b_natural(<8 x i8> %low, <8 x i16>* %A, <8 x i16>* %B
 define <8 x i16> @addhn2_8h_natural(<4 x i16> %low, <4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: addhn2_8h_natural:
 ;CHECK: addhn2.8h
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %sum = add <4 x i32> %tmp1, %tmp2
         %high_bits = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>
         %narrowed = trunc <4 x i32> %high_bits to <4 x i16>
@@ -862,8 +862,8 @@ define <8 x i16> @addhn2_8h_natural(<4 x i16> %low, <4 x i32>* %A, <4 x i32>* %B
 define <4 x i32> @addhn2_4s_natural(<2 x i32> %low, <2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: addhn2_4s_natural:
 ;CHECK: addhn2.4s
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %sum = add <2 x i64> %tmp1, %tmp2
         %high_bits = lshr <2 x i64> %sum, <i64 32, i64 32>
         %narrowed = trunc <2 x i64> %high_bits to <2 x i32>
@@ -874,8 +874,8 @@ define <4 x i32> @addhn2_4s_natural(<2 x i32> %low, <2 x i64>* %A, <2 x i64>* %B
 define <8 x i8> @subhn8b_natural(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: subhn8b_natural:
 ;CHECK: subhn.8b
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %diff = sub <8 x i16> %tmp1, %tmp2
         %high_bits = lshr <8 x i16> %diff, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
         %narrowed = trunc <8 x i16> %high_bits to <8 x i8>
@@ -885,8 +885,8 @@ define <8 x i8> @subhn8b_natural(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i16> @subhn4h_natural(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: subhn4h_natural:
 ;CHECK: subhn.4h
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %diff = sub <4 x i32> %tmp1, %tmp2
         %high_bits = lshr <4 x i32> %diff, <i32 16, i32 16, i32 16, i32 16>
         %narrowed = trunc <4 x i32> %high_bits to <4 x i16>
@@ -896,8 +896,8 @@ define <4 x i16> @subhn4h_natural(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i32> @subhn2s_natural(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: subhn2s_natural:
 ;CHECK: subhn.2s
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %diff = sub <2 x i64> %tmp1, %tmp2
         %high_bits = lshr <2 x i64> %diff, <i64 32, i64 32>
         %narrowed = trunc <2 x i64> %high_bits to <2 x i32>
@@ -907,8 +907,8 @@ define <2 x i32> @subhn2s_natural(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @subhn2_16b_natural(<8 x i8> %low, <8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: subhn2_16b_natural:
 ;CHECK: subhn2.16b
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %diff = sub <8 x i16> %tmp1, %tmp2
         %high_bits = lshr <8 x i16> %diff, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
         %narrowed = trunc <8 x i16> %high_bits to <8 x i8>
@@ -919,8 +919,8 @@ define <16 x i8> @subhn2_16b_natural(<8 x i8> %low, <8 x i16>* %A, <8 x i16>* %B
 define <8 x i16> @subhn2_8h_natural(<4 x i16> %low, <4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: subhn2_8h_natural:
 ;CHECK: subhn2.8h
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %diff = sub <4 x i32> %tmp1, %tmp2
         %high_bits = lshr <4 x i32> %diff, <i32 16, i32 16, i32 16, i32 16>
         %narrowed = trunc <4 x i32> %high_bits to <4 x i16>
@@ -931,8 +931,8 @@ define <8 x i16> @subhn2_8h_natural(<4 x i16> %low, <4 x i32>* %A, <4 x i32>* %B
 define <4 x i32> @subhn2_4s_natural(<2 x i32> %low, <2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: subhn2_4s_natural:
 ;CHECK: subhn2.4s
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %diff = sub <2 x i64> %tmp1, %tmp2
         %high_bits = lshr <2 x i64> %diff, <i64 32, i64 32>
         %narrowed = trunc <2 x i64> %high_bits to <2 x i32>
diff --git a/test/CodeGen/AArch64/arm64-vaddv.ll b/test/CodeGen/AArch64/arm64-vaddv.ll
index 2d92ce6ea570..589319bb3227 100644
--- a/test/CodeGen/AArch64/arm64-vaddv.ll
+++ b/test/CodeGen/AArch64/arm64-vaddv.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -mcpu=cyclone | FileCheck %s
+; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -asm-verbose=false -mcpu=cyclone | FileCheck %s
 
 define signext i8 @test_vaddv_s8(<8 x i8> %a1) {
 ; CHECK-LABEL: test_vaddv_s8:
@@ -11,6 +11,18 @@ entry:
   ret i8 %0
 }
 
+define <8 x i8> @test_vaddv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
+; CHECK-LABEL: test_vaddv_s8_used_by_laneop:
+; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a2)
+  %1 = trunc i32 %0 to i8
+  %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
+  ret <8 x i8> %2
+}
+
 define signext i16 @test_vaddv_s16(<4 x i16> %a1) {
 ; CHECK-LABEL: test_vaddv_s16:
 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
@@ -22,6 +34,18 @@ entry:
   ret i16 %0
 }
 
+define <4 x i16> @test_vaddv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
+; CHECK-LABEL: test_vaddv_s16_used_by_laneop:
+; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a2)
+  %1 = trunc i32 %0 to i16
+  %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
+  ret <4 x i16> %2
+}
+
 define i32 @test_vaddv_s32(<2 x i32> %a1) {
 ; CHECK-LABEL: test_vaddv_s32:
 ; 2 x i32 is not supported by the ISA, thus, this is a special case
@@ -33,6 +57,17 @@ entry:
   ret i32 %vaddv.i
 }
 
+define <2 x i32> @test_vaddv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
+; CHECK-LABEL: test_vaddv_s32_used_by_laneop:
+; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1
+; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> %a2)
+  %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
+  ret <2 x i32> %1
+}
+
 define i64 @test_vaddv_s64(<2 x i64> %a1) {
 ; CHECK-LABEL: test_vaddv_s64:
 ; CHECK: addp.2d [[REGNUM:d[0-9]+]], v0
@@ -43,6 +78,17 @@ entry:
   ret i64 %vaddv.i
 }
 
+define <2 x i64> @test_vaddv_s64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) {
+; CHECK-LABEL: test_vaddv_s64_used_by_laneop:
+; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.d v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> %a2)
+  %1 = insertelement <2 x i64> %a1, i64 %0, i64 1
+  ret <2 x i64> %1
+}
+
 define zeroext i8 @test_vaddv_u8(<8 x i8> %a1) {
 ; CHECK-LABEL: test_vaddv_u8:
 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
@@ -54,6 +100,18 @@ entry:
   ret i8 %0
 }
 
+define <8 x i8> @test_vaddv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
+; CHECK-LABEL: test_vaddv_u8_used_by_laneop:
+; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a2)
+  %1 = trunc i32 %0 to i8
+  %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
+  ret <8 x i8> %2
+}
+
 define i32 @test_vaddv_u8_masked(<8 x i8> %a1) {
 ; CHECK-LABEL: test_vaddv_u8_masked:
 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
@@ -76,6 +134,18 @@ entry:
   ret i16 %0
 }
 
+define <4 x i16> @test_vaddv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
+; CHECK-LABEL: test_vaddv_u16_used_by_laneop:
+; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a2)
+  %1 = trunc i32 %0 to i16
+  %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
+  ret <4 x i16> %2
+}
+
 define i32 @test_vaddv_u16_masked(<4 x i16> %a1) {
 ; CHECK-LABEL: test_vaddv_u16_masked:
 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
@@ -98,6 +168,17 @@ entry:
   ret i32 %vaddv.i
 }
 
+define <2 x i32> @test_vaddv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
+; CHECK-LABEL: test_vaddv_u32_used_by_laneop:
+; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1
+; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32> %a2)
+  %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
+  ret <2 x i32> %1
+}
+
 define float @test_vaddv_f32(<2 x float> %a1) {
 ; CHECK-LABEL: test_vaddv_f32:
 ; CHECK: faddp.2s s0, v0
@@ -136,6 +217,17 @@ entry:
   ret i64 %vaddv.i
 }
 
+define <2 x i64> @test_vaddv_u64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) {
+; CHECK-LABEL: test_vaddv_u64_used_by_laneop:
+; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.d v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a2)
+  %1 = insertelement <2 x i64> %a1, i64 %0, i64 1
+  ret <2 x i64> %1
+}
+
 define <1 x i64> @test_vaddv_u64_to_vec(<2 x i64> %a1) {
 ; CHECK-LABEL: test_vaddv_u64_to_vec:
 ; CHECK: addp.2d d0, v0
@@ -159,6 +251,18 @@ entry:
   ret i8 %0
 }
 
+define <16 x i8> @test_vaddvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
+; CHECK-LABEL: test_vaddvq_s8_used_by_laneop:
+; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a2)
+  %1 = trunc i32 %0 to i8
+  %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
+  ret <16 x i8> %2
+}
+
 define signext i16 @test_vaddvq_s16(<8 x i16> %a1) {
 ; CHECK-LABEL: test_vaddvq_s16:
 ; CHECK: addv.8h h[[REGNUM:[0-9]+]], v0
@@ -170,6 +274,18 @@ entry:
   ret i16 %0
 }
 
+define <8 x i16> @test_vaddvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
+; CHECK-LABEL: test_vaddvq_s16_used_by_laneop:
+; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a2)
+  %1 = trunc i32 %0 to i16
+  %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
+  ret <8 x i16> %2
+}
+
 define i32 @test_vaddvq_s32(<4 x i32> %a1) {
 ; CHECK-LABEL: test_vaddvq_s32:
 ; CHECK: addv.4s [[REGNUM:s[0-9]+]], v0
@@ -180,6 +296,17 @@ entry:
   ret i32 %vaddv.i
 }
 
+define <4 x i32> @test_vaddvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
+; CHECK-LABEL: test_vaddvq_s32_used_by_laneop:
+; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a2)
+  %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
+  ret <4 x i32> %1
+}
+
 define zeroext i8 @test_vaddvq_u8(<16 x i8> %a1) {
 ; CHECK-LABEL: test_vaddvq_u8:
 ; CHECK: addv.16b b[[REGNUM:[0-9]+]], v0
@@ -191,6 +318,18 @@ entry:
   ret i8 %0
 }
 
+define <16 x i8> @test_vaddvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
+; CHECK-LABEL: test_vaddvq_u8_used_by_laneop:
+; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> %a2)
+  %1 = trunc i32 %0 to i8
+  %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
+  ret <16 x i8> %2
+}
+
 define zeroext i16 @test_vaddvq_u16(<8 x i16> %a1) {
 ; CHECK-LABEL: test_vaddvq_u16:
 ; CHECK: addv.8h h[[REGNUM:[0-9]+]], v0
@@ -202,6 +341,18 @@ entry:
   ret i16 %0
 }
 
+define <8 x i16> @test_vaddvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
+; CHECK-LABEL: test_vaddvq_u16_used_by_laneop:
+; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a2)
+  %1 = trunc i32 %0 to i16
+  %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
+  ret <8 x i16> %2
+}
+
 define i32 @test_vaddvq_u32(<4 x i32> %a1) {
 ; CHECK-LABEL: test_vaddvq_u32:
 ; CHECK: addv.4s [[REGNUM:s[0-9]+]], v0
@@ -212,6 +363,17 @@ entry:
   ret i32 %vaddv.i
 }
 
+define <4 x i32> @test_vaddvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
+; CHECK-LABEL: test_vaddvq_u32_used_by_laneop:
+; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
+entry:
+  %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a2)
+  %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
+  ret <4 x i32> %1
+}
+
 declare i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32>)
 
 declare i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16>)
diff --git a/test/CodeGen/AArch64/arm64-vbitwise.ll b/test/CodeGen/AArch64/arm64-vbitwise.ll
index 93de95e52e53..9cfcaafe9491 100644
--- a/test/CodeGen/AArch64/arm64-vbitwise.ll
+++ b/test/CodeGen/AArch64/arm64-vbitwise.ll
@@ -3,7 +3,7 @@
 define <8 x i8> @rbit_8b(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: rbit_8b:
 ;CHECK: rbit.8b
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8> %tmp1)
 	ret <8 x i8> %tmp3
 }
@@ -11,7 +11,7 @@ define <8 x i8> @rbit_8b(<8 x i8>* %A) nounwind {
 define <16 x i8> @rbit_16b(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: rbit_16b:
 ;CHECK: rbit.16b
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8> %tmp1)
 	ret <16 x i8> %tmp3
 }
@@ -22,7 +22,7 @@ declare <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8>) nounwind readnone
 define <8 x i16> @sxtl8h(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: sxtl8h:
 ;CHECK: sshll.8h
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
   %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
   ret <8 x i16> %tmp2
 }
@@ -30,7 +30,7 @@ define <8 x i16> @sxtl8h(<8 x i8>* %A) nounwind {
 define <8 x i16> @uxtl8h(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: uxtl8h:
 ;CHECK: ushll.8h
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
   %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
   ret <8 x i16> %tmp2
 }
@@ -38,7 +38,7 @@ define <8 x i16> @uxtl8h(<8 x i8>* %A) nounwind {
 define <4 x i32> @sxtl4s(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: sxtl4s:
 ;CHECK: sshll.4s
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
   %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
   ret <4 x i32> %tmp2
 }
@@ -46,7 +46,7 @@ define <4 x i32> @sxtl4s(<4 x i16>* %A) nounwind {
 define <4 x i32> @uxtl4s(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: uxtl4s:
 ;CHECK: ushll.4s
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
   %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
   ret <4 x i32> %tmp2
 }
@@ -54,7 +54,7 @@ define <4 x i32> @uxtl4s(<4 x i16>* %A) nounwind {
 define <2 x i64> @sxtl2d(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: sxtl2d:
 ;CHECK: sshll.2d
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
   %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
   ret <2 x i64> %tmp2
 }
@@ -62,7 +62,7 @@ define <2 x i64> @sxtl2d(<2 x i32>* %A) nounwind {
 define <2 x i64> @uxtl2d(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: uxtl2d:
 ;CHECK: ushll.2d
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
   %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
   ret <2 x i64> %tmp2
 }
@@ -76,7 +76,7 @@ entry:
 ; CHECK: movi.2d [[REG1:v[0-9]+]], #0x0000ff000000ff
 ; CHECK: and.16b v{{[0-9]+}}, v{{[0-9]+}}, [[REG1]]
   %0 = bitcast i8* %src to <16 x i8>*
-  %1 = load <16 x i8>* %0, align 16
+  %1 = load <16 x i8>, <16 x i8>* %0, align 16
   %and.i = and <16 x i8> %1, <i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0>
   %2 = bitcast <16 x i8> %and.i to <8 x i16>
   %vshl_n = shl <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
diff --git a/test/CodeGen/AArch64/arm64-vcmp.ll b/test/CodeGen/AArch64/arm64-vcmp.ll
index 982ab09ee69e..1b33eb58e86f 100644
--- a/test/CodeGen/AArch64/arm64-vcmp.ll
+++ b/test/CodeGen/AArch64/arm64-vcmp.ll
@@ -16,8 +16,8 @@ define void @fcmltz_4s(<4 x float> %a, <4 x i16>* %p) nounwind {
 define <2 x i32> @facge_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: facge_2s:
 ;CHECK: facge.2s
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.facge.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -25,8 +25,8 @@ define <2 x i32> @facge_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x i32> @facge_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: facge_4s:
 ;CHECK: facge.4s
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.facge.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -34,8 +34,8 @@ define <4 x i32> @facge_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x i64> @facge_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
 ;CHECK-LABEL: facge_2d:
 ;CHECK: facge.2d
-	%tmp1 = load <2 x double>* %A
-	%tmp2 = load <2 x double>* %B
+	%tmp1 = load <2 x double>, <2 x double>* %A
+	%tmp2 = load <2 x double>, <2 x double>* %B
 	%tmp3 = call <2 x i64> @llvm.aarch64.neon.facge.v2i64.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -47,8 +47,8 @@ declare <2 x i64> @llvm.aarch64.neon.facge.v2i64.v2f64(<2 x double>, <2 x double
 define <2 x i32> @facgt_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: facgt_2s:
 ;CHECK: facgt.2s
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.facgt.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -56,8 +56,8 @@ define <2 x i32> @facgt_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x i32> @facgt_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: facgt_4s:
 ;CHECK: facgt.4s
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.facgt.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -65,8 +65,8 @@ define <4 x i32> @facgt_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x i64> @facgt_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
 ;CHECK-LABEL: facgt_2d:
 ;CHECK: facgt.2d
-	%tmp1 = load <2 x double>* %A
-	%tmp2 = load <2 x double>* %B
+	%tmp1 = load <2 x double>, <2 x double>* %A
+	%tmp2 = load <2 x double>, <2 x double>* %B
 	%tmp3 = call <2 x i64> @llvm.aarch64.neon.facgt.v2i64.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -112,8 +112,8 @@ declare i32 @llvm.aarch64.neon.facgt.i32.f32(float, float)
 define <8 x i8> @cmtst_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: cmtst_8b:
 ;CHECK: cmtst.8b
-  %tmp1 = load <8 x i8>* %A
-  %tmp2 = load <8 x i8>* %B
+  %tmp1 = load <8 x i8>, <8 x i8>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
   %commonbits = and <8 x i8> %tmp1, %tmp2
   %mask = icmp ne <8 x i8> %commonbits, zeroinitializer
   %res = sext <8 x i1> %mask to <8 x i8>
@@ -123,8 +123,8 @@ define <8 x i8> @cmtst_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @cmtst_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: cmtst_16b:
 ;CHECK: cmtst.16b
-  %tmp1 = load <16 x i8>* %A
-  %tmp2 = load <16 x i8>* %B
+  %tmp1 = load <16 x i8>, <16 x i8>* %A
+  %tmp2 = load <16 x i8>, <16 x i8>* %B
   %commonbits = and <16 x i8> %tmp1, %tmp2
   %mask = icmp ne <16 x i8> %commonbits, zeroinitializer
   %res = sext <16 x i1> %mask to <16 x i8>
@@ -134,8 +134,8 @@ define <16 x i8> @cmtst_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @cmtst_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: cmtst_4h:
 ;CHECK: cmtst.4h
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %commonbits = and <4 x i16> %tmp1, %tmp2
   %mask = icmp ne <4 x i16> %commonbits, zeroinitializer
   %res = sext <4 x i1> %mask to <4 x i16>
@@ -145,8 +145,8 @@ define <4 x i16> @cmtst_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @cmtst_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: cmtst_8h:
 ;CHECK: cmtst.8h
-  %tmp1 = load <8 x i16>* %A
-  %tmp2 = load <8 x i16>* %B
+  %tmp1 = load <8 x i16>, <8 x i16>* %A
+  %tmp2 = load <8 x i16>, <8 x i16>* %B
   %commonbits = and <8 x i16> %tmp1, %tmp2
   %mask = icmp ne <8 x i16> %commonbits, zeroinitializer
   %res = sext <8 x i1> %mask to <8 x i16>
@@ -156,8 +156,8 @@ define <8 x i16> @cmtst_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @cmtst_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: cmtst_2s:
 ;CHECK: cmtst.2s
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %commonbits = and <2 x i32> %tmp1, %tmp2
   %mask = icmp ne <2 x i32> %commonbits, zeroinitializer
   %res = sext <2 x i1> %mask to <2 x i32>
@@ -167,8 +167,8 @@ define <2 x i32> @cmtst_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @cmtst_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: cmtst_4s:
 ;CHECK: cmtst.4s
-  %tmp1 = load <4 x i32>* %A
-  %tmp2 = load <4 x i32>* %B
+  %tmp1 = load <4 x i32>, <4 x i32>* %A
+  %tmp2 = load <4 x i32>, <4 x i32>* %B
   %commonbits = and <4 x i32> %tmp1, %tmp2
   %mask = icmp ne <4 x i32> %commonbits, zeroinitializer
   %res = sext <4 x i1> %mask to <4 x i32>
@@ -178,8 +178,8 @@ define <4 x i32> @cmtst_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @cmtst_2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: cmtst_2d:
 ;CHECK: cmtst.2d
-  %tmp1 = load <2 x i64>* %A
-  %tmp2 = load <2 x i64>* %B
+  %tmp1 = load <2 x i64>, <2 x i64>* %A
+  %tmp2 = load <2 x i64>, <2 x i64>* %B
   %commonbits = and <2 x i64> %tmp1, %tmp2
   %mask = icmp ne <2 x i64> %commonbits, zeroinitializer
   %res = sext <2 x i1> %mask to <2 x i64>
diff --git a/test/CodeGen/AArch64/arm64-vcnt.ll b/test/CodeGen/AArch64/arm64-vcnt.ll
index 903501ec16a9..5cff10cb8d16 100644
--- a/test/CodeGen/AArch64/arm64-vcnt.ll
+++ b/test/CodeGen/AArch64/arm64-vcnt.ll
@@ -3,7 +3,7 @@
 define <8 x i8> @cls_8b(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: cls_8b:
 ;CHECK: cls.8b
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.cls.v8i8(<8 x i8> %tmp1)
 	ret <8 x i8> %tmp3
 }
@@ -11,7 +11,7 @@ define <8 x i8> @cls_8b(<8 x i8>* %A) nounwind {
 define <16 x i8> @cls_16b(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: cls_16b:
 ;CHECK: cls.16b
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.cls.v16i8(<16 x i8> %tmp1)
 	ret <16 x i8> %tmp3
 }
@@ -19,7 +19,7 @@ define <16 x i8> @cls_16b(<16 x i8>* %A) nounwind {
 define <4 x i16> @cls_4h(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: cls_4h:
 ;CHECK: cls.4h
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.cls.v4i16(<4 x i16> %tmp1)
 	ret <4 x i16> %tmp3
 }
@@ -27,7 +27,7 @@ define <4 x i16> @cls_4h(<4 x i16>* %A) nounwind {
 define <8 x i16> @cls_8h(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: cls_8h:
 ;CHECK: cls.8h
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.cls.v8i16(<8 x i16> %tmp1)
 	ret <8 x i16> %tmp3
 }
@@ -35,7 +35,7 @@ define <8 x i16> @cls_8h(<8 x i16>* %A) nounwind {
 define <2 x i32> @cls_2s(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: cls_2s:
 ;CHECK: cls.2s
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.cls.v2i32(<2 x i32> %tmp1)
 	ret <2 x i32> %tmp3
 }
@@ -43,7 +43,7 @@ define <2 x i32> @cls_2s(<2 x i32>* %A) nounwind {
 define <4 x i32> @cls_4s(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: cls_4s:
 ;CHECK: cls.4s
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.cls.v4i32(<4 x i32> %tmp1)
 	ret <4 x i32> %tmp3
 }
diff --git a/test/CodeGen/AArch64/arm64-vcvt.ll b/test/CodeGen/AArch64/arm64-vcvt.ll
index 6570f0e3e7eb..13d2d288b2c4 100644
--- a/test/CodeGen/AArch64/arm64-vcvt.ll
+++ b/test/CodeGen/AArch64/arm64-vcvt.ll
@@ -675,7 +675,7 @@ define void @autogen_SD28458(<8 x double> %val.f64, <8 x float>* %addr.f32) {
 ;CHECK: fcvt
 ;CHECK: ret
 define void @autogen_SD19225(<8 x double>* %addr.f64, <8 x float>* %addr.f32) {
-  %A = load <8 x float>* %addr.f32
+  %A = load <8 x float>, <8 x float>* %addr.f32
   %Tr53 = fpext <8 x float> %A to <8 x double>
   store <8 x double> %Tr53, <8 x double>* %addr.f64
   ret void
diff --git a/test/CodeGen/AArch64/arm64-vector-imm.ll b/test/CodeGen/AArch64/arm64-vector-imm.ll
index 9fb088b9a497..d3de88d2049d 100644
--- a/test/CodeGen/AArch64/arm64-vector-imm.ll
+++ b/test/CodeGen/AArch64/arm64-vector-imm.ll
@@ -5,7 +5,7 @@ define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind {
 ; CHECK-NOT: mov
 ; CHECK-NOT: mvn
 ; CHECK: orr
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
 	ret <8 x i8> %tmp3
 }
@@ -15,7 +15,7 @@ define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind {
 ; CHECK-NOT: mov
 ; CHECK-NOT: mvn
 ; CHECK: orr
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
 	ret <16 x i8> %tmp3
 }
@@ -25,7 +25,7 @@ define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
 ; CHECK-NOT: mov
 ; CHECK-NOT: mvn
 ; CHECK: bic
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
 	ret <8 x i8> %tmp3
 }
@@ -35,7 +35,7 @@ define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
 ; CHECK-NOT: mov
 ; CHECK-NOT: mvn
 ; CHECK: bic
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
 	ret <16 x i8> %tmp3
 }
diff --git a/test/CodeGen/AArch64/arm64-vector-ldst.ll b/test/CodeGen/AArch64/arm64-vector-ldst.ll
index c00191577d17..26b9d62c8f6a 100644
--- a/test/CodeGen/AArch64/arm64-vector-ldst.ll
+++ b/test/CodeGen/AArch64/arm64-vector-ldst.ll
@@ -12,8 +12,8 @@ entry:
 ; CHECK-LABEL: t1:
 ; CHECK: ldr x[[REG:[0-9]+]], [x0]
 ; CHECK: str q0, [x[[REG]]]
-  %tmp1 = load %type1** %argtable, align 8
-  %tmp2 = getelementptr inbounds %type1* %tmp1, i64 0, i32 0
+  %tmp1 = load %type1*, %type1** %argtable, align 8
+  %tmp2 = getelementptr inbounds %type1, %type1* %tmp1, i64 0, i32 0
   store <16 x i8> zeroinitializer, <16 x i8>* %tmp2, align 16
   ret void
 }
@@ -23,8 +23,8 @@ entry:
 ; CHECK-LABEL: t2:
 ; CHECK: ldr x[[REG:[0-9]+]], [x0]
 ; CHECK: str d0, [x[[REG]]]
-  %tmp1 = load %type2** %argtable, align 8
-  %tmp2 = getelementptr inbounds %type2* %tmp1, i64 0, i32 0
+  %tmp1 = load %type2*, %type2** %argtable, align 8
+  %tmp2 = getelementptr inbounds %type2, %type2* %tmp1, i64 0, i32 0
   store <8 x i8> zeroinitializer, <8 x i8>* %tmp2, align 8
   ret void
 }
@@ -51,10 +51,10 @@ entry:
 ; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]
 ; CHECK: ldr [[BASE:x[0-9]+]],
 ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
-  %arrayidx = getelementptr inbounds <2 x i64>* %array, i64 %offset
-  %tmp = load <2 x i64>* %arrayidx, align 16
-  %tmp1 = load <2 x i64>** @globalArray64x2, align 8
-  %arrayidx1 = getelementptr inbounds <2 x i64>* %tmp1, i64 %offset
+  %arrayidx = getelementptr inbounds <2 x i64>, <2 x i64>* %array, i64 %offset
+  %tmp = load <2 x i64>, <2 x i64>* %arrayidx, align 16
+  %tmp1 = load <2 x i64>*, <2 x i64>** @globalArray64x2, align 8
+  %arrayidx1 = getelementptr inbounds <2 x i64>, <2 x i64>* %tmp1, i64 %offset
   store <2 x i64> %tmp, <2 x i64>* %arrayidx1, align 16
   ret void
 }
@@ -65,10 +65,10 @@ entry:
 ; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
 ; CHECK: ldr [[BASE:x[0-9]+]],
 ; CHECK: str [[DEST]], {{\[}}[[BASE]], #80]
-  %arrayidx = getelementptr inbounds <2 x i64>* %array, i64 3
-  %tmp = load <2 x i64>* %arrayidx, align 16
-  %tmp1 = load <2 x i64>** @globalArray64x2, align 8
-  %arrayidx1 = getelementptr inbounds <2 x i64>* %tmp1, i64 5
+  %arrayidx = getelementptr inbounds <2 x i64>, <2 x i64>* %array, i64 3
+  %tmp = load <2 x i64>, <2 x i64>* %arrayidx, align 16
+  %tmp1 = load <2 x i64>*, <2 x i64>** @globalArray64x2, align 8
+  %arrayidx1 = getelementptr inbounds <2 x i64>, <2 x i64>* %tmp1, i64 5
   store <2 x i64> %tmp, <2 x i64>* %arrayidx1, align 16
   ret void
 }
@@ -80,10 +80,10 @@ entry:
 ; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
 ; CHECK: ldr [[BASE:x[0-9]+]],
 ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
-  %arrayidx = getelementptr inbounds <4 x i32>* %array, i64 %offset
-  %tmp = load <4 x i32>* %arrayidx, align 16
-  %tmp1 = load <4 x i32>** @globalArray32x4, align 8
-  %arrayidx1 = getelementptr inbounds <4 x i32>* %tmp1, i64 %offset
+  %arrayidx = getelementptr inbounds <4 x i32>, <4 x i32>* %array, i64 %offset
+  %tmp = load <4 x i32>, <4 x i32>* %arrayidx, align 16
+  %tmp1 = load <4 x i32>*, <4 x i32>** @globalArray32x4, align 8
+  %arrayidx1 = getelementptr inbounds <4 x i32>, <4 x i32>* %tmp1, i64 %offset
   store <4 x i32> %tmp, <4 x i32>* %arrayidx1, align 16
   ret void
 }
@@ -94,10 +94,10 @@ entry:
 ; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
 ; CHECK: ldr [[BASE:x[0-9]+]],
 ; CHECK: str [[DEST]], {{\[}}[[BASE]], #80]
-  %arrayidx = getelementptr inbounds <4 x i32>* %array, i64 3
-  %tmp = load <4 x i32>* %arrayidx, align 16
-  %tmp1 = load <4 x i32>** @globalArray32x4, align 8
-  %arrayidx1 = getelementptr inbounds <4 x i32>* %tmp1, i64 5
+  %arrayidx = getelementptr inbounds <4 x i32>, <4 x i32>* %array, i64 3
+  %tmp = load <4 x i32>, <4 x i32>* %arrayidx, align 16
+  %tmp1 = load <4 x i32>*, <4 x i32>** @globalArray32x4, align 8
+  %arrayidx1 = getelementptr inbounds <4 x i32>, <4 x i32>* %tmp1, i64 5
   store <4 x i32> %tmp, <4 x i32>* %arrayidx1, align 16
   ret void
 }
@@ -109,10 +109,10 @@ entry:
 ; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
 ; CHECK: ldr [[BASE:x[0-9]+]],
 ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
-  %arrayidx = getelementptr inbounds <8 x i16>* %array, i64 %offset
-  %tmp = load <8 x i16>* %arrayidx, align 16
-  %tmp1 = load <8 x i16>** @globalArray16x8, align 8
-  %arrayidx1 = getelementptr inbounds <8 x i16>* %tmp1, i64 %offset
+  %arrayidx = getelementptr inbounds <8 x i16>, <8 x i16>* %array, i64 %offset
+  %tmp = load <8 x i16>, <8 x i16>* %arrayidx, align 16
+  %tmp1 = load <8 x i16>*, <8 x i16>** @globalArray16x8, align 8
+  %arrayidx1 = getelementptr inbounds <8 x i16>, <8 x i16>* %tmp1, i64 %offset
   store <8 x i16> %tmp, <8 x i16>* %arrayidx1, align 16
   ret void
 }
@@ -123,10 +123,10 @@ entry:
 ; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
 ; CHECK: ldr [[BASE:x[0-9]+]],
 ; CHECK: str [[DEST]], {{\[}}[[BASE]], #80]
-  %arrayidx = getelementptr inbounds <8 x i16>* %array, i64 3
-  %tmp = load <8 x i16>* %arrayidx, align 16
-  %tmp1 = load <8 x i16>** @globalArray16x8, align 8
-  %arrayidx1 = getelementptr inbounds <8 x i16>* %tmp1, i64 5
+  %arrayidx = getelementptr inbounds <8 x i16>, <8 x i16>* %array, i64 3
+  %tmp = load <8 x i16>, <8 x i16>* %arrayidx, align 16
+  %tmp1 = load <8 x i16>*, <8 x i16>** @globalArray16x8, align 8
+  %arrayidx1 = getelementptr inbounds <8 x i16>, <8 x i16>* %tmp1, i64 5
   store <8 x i16> %tmp, <8 x i16>* %arrayidx1, align 16
   ret void
 }
@@ -138,10 +138,10 @@ entry:
 ; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
 ; CHECK: ldr [[BASE:x[0-9]+]],
 ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
-  %arrayidx = getelementptr inbounds <16 x i8>* %array, i64 %offset
-  %tmp = load <16 x i8>* %arrayidx, align 16
-  %tmp1 = load <16 x i8>** @globalArray8x16, align 8
-  %arrayidx1 = getelementptr inbounds <16 x i8>* %tmp1, i64 %offset
+  %arrayidx = getelementptr inbounds <16 x i8>, <16 x i8>* %array, i64 %offset
+  %tmp = load <16 x i8>, <16 x i8>* %arrayidx, align 16
+  %tmp1 = load <16 x i8>*, <16 x i8>** @globalArray8x16, align 8
+  %arrayidx1 = getelementptr inbounds <16 x i8>, <16 x i8>* %tmp1, i64 %offset
   store <16 x i8> %tmp, <16 x i8>* %arrayidx1, align 16
   ret void
 }
@@ -152,10 +152,10 @@ entry:
 ; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
 ; CHECK: ldr [[BASE:x[0-9]+]],
 ; CHECK: str [[DEST]], {{\[}}[[BASE]], #80]
-  %arrayidx = getelementptr inbounds <16 x i8>* %array, i64 3
-  %tmp = load <16 x i8>* %arrayidx, align 16
-  %tmp1 = load <16 x i8>** @globalArray8x16, align 8
-  %arrayidx1 = getelementptr inbounds <16 x i8>* %tmp1, i64 5
+  %arrayidx = getelementptr inbounds <16 x i8>, <16 x i8>* %array, i64 3
+  %tmp = load <16 x i8>, <16 x i8>* %arrayidx, align 16
+  %tmp1 = load <16 x i8>*, <16 x i8>** @globalArray8x16, align 8
+  %arrayidx1 = getelementptr inbounds <16 x i8>, <16 x i8>* %tmp1, i64 5
   store <16 x i8> %tmp, <16 x i8>* %arrayidx1, align 16
   ret void
 }
@@ -167,10 +167,10 @@ entry:
 ; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
 ; CHECK: ldr [[BASE:x[0-9]+]],
 ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
-  %arrayidx = getelementptr inbounds <1 x i64>* %array, i64 %offset
-  %tmp = load <1 x i64>* %arrayidx, align 8
-  %tmp1 = load <1 x i64>** @globalArray64x1, align 8
-  %arrayidx1 = getelementptr inbounds <1 x i64>* %tmp1, i64 %offset
+  %arrayidx = getelementptr inbounds <1 x i64>, <1 x i64>* %array, i64 %offset
+  %tmp = load <1 x i64>, <1 x i64>* %arrayidx, align 8
+  %tmp1 = load <1 x i64>*, <1 x i64>** @globalArray64x1, align 8
+  %arrayidx1 = getelementptr inbounds <1 x i64>, <1 x i64>* %tmp1, i64 %offset
   store <1 x i64> %tmp, <1 x i64>* %arrayidx1, align 8
   ret void
 }
@@ -181,10 +181,10 @@ entry:
 ; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24]
 ; CHECK: ldr [[BASE:x[0-9]+]],
 ; CHECK: str [[DEST]], {{\[}}[[BASE]], #40]
-  %arrayidx = getelementptr inbounds <1 x i64>* %array, i64 3
-  %tmp = load <1 x i64>* %arrayidx, align 8
-  %tmp1 = load <1 x i64>** @globalArray64x1, align 8
-  %arrayidx1 = getelementptr inbounds <1 x i64>* %tmp1, i64 5
+  %arrayidx = getelementptr inbounds <1 x i64>, <1 x i64>* %array, i64 3
+  %tmp = load <1 x i64>, <1 x i64>* %arrayidx, align 8
+  %tmp1 = load <1 x i64>*, <1 x i64>** @globalArray64x1, align 8
+  %arrayidx1 = getelementptr inbounds <1 x i64>, <1 x i64>* %tmp1, i64 5
   store <1 x i64> %tmp, <1 x i64>* %arrayidx1, align 8
   ret void
 }
@@ -196,10 +196,10 @@ entry:
 ; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
 ; CHECK: ldr [[BASE:x[0-9]+]],
 ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
-  %arrayidx = getelementptr inbounds <2 x i32>* %array, i64 %offset
-  %tmp = load <2 x i32>* %arrayidx, align 8
-  %tmp1 = load <2 x i32>** @globalArray32x2, align 8
-  %arrayidx1 = getelementptr inbounds <2 x i32>* %tmp1, i64 %offset
+  %arrayidx = getelementptr inbounds <2 x i32>, <2 x i32>* %array, i64 %offset
+  %tmp = load <2 x i32>, <2 x i32>* %arrayidx, align 8
+  %tmp1 = load <2 x i32>*, <2 x i32>** @globalArray32x2, align 8
+  %arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %tmp1, i64 %offset
   store <2 x i32> %tmp, <2 x i32>* %arrayidx1, align 8
   ret void
 }
@@ -210,10 +210,10 @@ entry:
 ; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24]
 ; CHECK: ldr [[BASE:x[0-9]+]],
 ; CHECK: str [[DEST]], {{\[}}[[BASE]], #40]
-  %arrayidx = getelementptr inbounds <2 x i32>* %array, i64 3
-  %tmp = load <2 x i32>* %arrayidx, align 8
-  %tmp1 = load <2 x i32>** @globalArray32x2, align 8
-  %arrayidx1 = getelementptr inbounds <2 x i32>* %tmp1, i64 5
+  %arrayidx = getelementptr inbounds <2 x i32>, <2 x i32>* %array, i64 3
+  %tmp = load <2 x i32>, <2 x i32>* %arrayidx, align 8
+  %tmp1 = load <2 x i32>*, <2 x i32>** @globalArray32x2, align 8
+  %arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %tmp1, i64 5
   store <2 x i32> %tmp, <2 x i32>* %arrayidx1, align 8
   ret void
 }
@@ -225,10 +225,10 @@ entry:
 ; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
 ; CHECK: ldr [[BASE:x[0-9]+]],
 ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
-  %arrayidx = getelementptr inbounds <4 x i16>* %array, i64 %offset
-  %tmp = load <4 x i16>* %arrayidx, align 8
-  %tmp1 = load <4 x i16>** @globalArray16x4, align 8
-  %arrayidx1 = getelementptr inbounds <4 x i16>* %tmp1, i64 %offset
+  %arrayidx = getelementptr inbounds <4 x i16>, <4 x i16>* %array, i64 %offset
+  %tmp = load <4 x i16>, <4 x i16>* %arrayidx, align 8
+  %tmp1 = load <4 x i16>*, <4 x i16>** @globalArray16x4, align 8
+  %arrayidx1 = getelementptr inbounds <4 x i16>, <4 x i16>* %tmp1, i64 %offset
   store <4 x i16> %tmp, <4 x i16>* %arrayidx1, align 8
   ret void
 }
@@ -239,10 +239,10 @@ entry:
 ; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24]
 ; CHECK: ldr [[BASE:x[0-9]+]],
 ; CHECK: str [[DEST]], {{\[}}[[BASE]], #40]
-  %arrayidx = getelementptr inbounds <4 x i16>* %array, i64 3
-  %tmp = load <4 x i16>* %arrayidx, align 8
-  %tmp1 = load <4 x i16>** @globalArray16x4, align 8
-  %arrayidx1 = getelementptr inbounds <4 x i16>* %tmp1, i64 5
+  %arrayidx = getelementptr inbounds <4 x i16>, <4 x i16>* %array, i64 3
+  %tmp = load <4 x i16>, <4 x i16>* %arrayidx, align 8
+  %tmp1 = load <4 x i16>*, <4 x i16>** @globalArray16x4, align 8
+  %arrayidx1 = getelementptr inbounds <4 x i16>, <4 x i16>* %tmp1, i64 5
   store <4 x i16> %tmp, <4 x i16>* %arrayidx1, align 8
   ret void
 }
@@ -254,10 +254,10 @@ entry:
 ; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
 ; CHECK: ldr [[BASE:x[0-9]+]],
 ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
-  %arrayidx = getelementptr inbounds <8 x i8>* %array, i64 %offset
-  %tmp = load <8 x i8>* %arrayidx, align 8
-  %tmp1 = load <8 x i8>** @globalArray8x8, align 8
-  %arrayidx1 = getelementptr inbounds <8 x i8>* %tmp1, i64 %offset
+  %arrayidx = getelementptr inbounds <8 x i8>, <8 x i8>* %array, i64 %offset
+  %tmp = load <8 x i8>, <8 x i8>* %arrayidx, align 8
+  %tmp1 = load <8 x i8>*, <8 x i8>** @globalArray8x8, align 8
+  %arrayidx1 = getelementptr inbounds <8 x i8>, <8 x i8>* %tmp1, i64 %offset
   store <8 x i8> %tmp, <8 x i8>* %arrayidx1, align 8
   ret void
 }
@@ -270,7 +270,7 @@ define <1 x i64> @fct0() nounwind readonly ssp {
 entry:
 ; CHECK-LABEL: fct0:
 ; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
-  %0 = load <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <1 x i64>*), align 8
+  %0 = load <1 x i64>, <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <1 x i64>*), align 8
   ret <1 x i64> %0
 }
 
@@ -278,7 +278,7 @@ define <2 x i32> @fct1() nounwind readonly ssp {
 entry:
 ; CHECK-LABEL: fct1:
 ; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
-  %0 = load <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <2 x i32>*), align 8
+  %0 = load <2 x i32>, <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <2 x i32>*), align 8
   ret <2 x i32> %0
 }
 
@@ -286,7 +286,7 @@ define <4 x i16> @fct2() nounwind readonly ssp {
 entry:
 ; CHECK-LABEL: fct2:
 ; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
-  %0 = load <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <4 x i16>*), align 8
+  %0 = load <4 x i16>, <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <4 x i16>*), align 8
   ret <4 x i16> %0
 }
 
@@ -294,7 +294,7 @@ define <8 x i8> @fct3() nounwind readonly ssp {
 entry:
 ; CHECK-LABEL: fct3:
 ; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
-  %0 = load <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <8 x i8>*), align 8
+  %0 = load <8 x i8>, <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <8 x i8>*), align 8
   ret <8 x i8> %0
 }
 
@@ -302,7 +302,7 @@ define <2 x i64> @fct4() nounwind readonly ssp {
 entry:
 ; CHECK-LABEL: fct4:
 ; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
-  %0 = load <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <2 x i64>*), align 16
+  %0 = load <2 x i64>, <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <2 x i64>*), align 16
   ret <2 x i64> %0
 }
 
@@ -310,7 +310,7 @@ define <4 x i32> @fct5() nounwind readonly ssp {
 entry:
 ; CHECK-LABEL: fct5:
 ; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
-  %0 = load <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <4 x i32>*), align 16
+  %0 = load <4 x i32>, <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <4 x i32>*), align 16
   ret <4 x i32> %0
 }
 
@@ -318,7 +318,7 @@ define <8 x i16> @fct6() nounwind readonly ssp {
 entry:
 ; CHECK-LABEL: fct6:
 ; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
-  %0 = load <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <8 x i16>*), align 16
+  %0 = load <8 x i16>, <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <8 x i16>*), align 16
   ret <8 x i16> %0
 }
 
@@ -326,7 +326,7 @@ define <16 x i8> @fct7() nounwind readonly ssp {
 entry:
 ; CHECK-LABEL: fct7:
 ; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
-  %0 = load <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <16 x i8>*), align 16
+  %0 = load <16 x i8>, <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <16 x i8>*), align 16
   ret <16 x i8> %0
 }
 
@@ -335,8 +335,8 @@ entry:
 ; CHECK-LABEL: fct8:
 ; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
 ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
-  %0 = load <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <1 x i64>*), align 8
-  store <1 x i64> %0, <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <1 x i64>*), align 8
+  %0 = load <1 x i64>, <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <1 x i64>*), align 8
+  store <1 x i64> %0, <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <1 x i64>*), align 8
   ret void
 }
 
@@ -345,8 +345,8 @@ entry:
 ; CHECK-LABEL: fct9:
 ; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
 ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
-  %0 = load <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <2 x i32>*), align 8
-  store <2 x i32> %0, <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <2 x i32>*), align 8
+  %0 = load <2 x i32>, <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <2 x i32>*), align 8
+  store <2 x i32> %0, <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <2 x i32>*), align 8
   ret void
 }
 
@@ -355,8 +355,8 @@ entry:
 ; CHECK-LABEL: fct10:
 ; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
 ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
-  %0 = load <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <4 x i16>*), align 8
-  store <4 x i16> %0, <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <4 x i16>*), align 8
+  %0 = load <4 x i16>, <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <4 x i16>*), align 8
+  store <4 x i16> %0, <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <4 x i16>*), align 8
   ret void
 }
 
@@ -365,8 +365,8 @@ entry:
 ; CHECK-LABEL: fct11:
 ; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
 ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
-  %0 = load <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <8 x i8>*), align 8
-  store <8 x i8> %0, <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <8 x i8>*), align 8
+  %0 = load <8 x i8>, <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <8 x i8>*), align 8
+  store <8 x i8> %0, <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <8 x i8>*), align 8
   ret void
 }
 
@@ -375,8 +375,8 @@ entry:
 ; CHECK-LABEL: fct12:
 ; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
 ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
-  %0 = load <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <2 x i64>*), align 16
-  store <2 x i64> %0, <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <2 x i64>*), align 16
+  %0 = load <2 x i64>, <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <2 x i64>*), align 16
+  store <2 x i64> %0, <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <2 x i64>*), align 16
   ret void
 }
 
@@ -385,8 +385,8 @@ entry:
 ; CHECK-LABEL: fct13:
 ; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
 ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
-  %0 = load <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <4 x i32>*), align 16
-  store <4 x i32> %0, <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <4 x i32>*), align 16
+  %0 = load <4 x i32>, <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <4 x i32>*), align 16
+  store <4 x i32> %0, <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <4 x i32>*), align 16
   ret void
 }
 
@@ -395,8 +395,8 @@ entry:
 ; CHECK-LABEL: fct14:
 ; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
 ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
-  %0 = load <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <8 x i16>*), align 16
-  store <8 x i16> %0, <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <8 x i16>*), align 16
+  %0 = load <8 x i16>, <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <8 x i16>*), align 16
+  store <8 x i16> %0, <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <8 x i16>*), align 16
   ret void
 }
 
@@ -405,8 +405,8 @@ entry:
 ; CHECK-LABEL: fct15:
 ; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
 ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
-  %0 = load <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <16 x i8>*), align 16
-  store <16 x i8> %0, <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <16 x i8>*), align 16
+  %0 = load <16 x i8>, <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <16 x i8>*), align 16
+  store <16 x i8> %0, <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <16 x i8>*), align 16
   ret void
 }
 
@@ -419,8 +419,8 @@ define <8 x i8> @fct16(i8* nocapture %sp0) {
 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
 ; CHECK-NEXT: mul.8b v0, v[[REGNUM]], v[[REGNUM]]
 entry:
-  %addr = getelementptr i8* %sp0, i64 1
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %addr = getelementptr i8, i8* %sp0, i64 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %vec = insertelement <8 x i8> undef, i8 %pix_sp0.0.copyload, i32 0
   %vmull.i = mul <8 x i8> %vec, %vec
   ret <8 x i8> %vmull.i
@@ -431,8 +431,8 @@ define <16 x i8> @fct17(i8* nocapture %sp0) {
 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
 ; CHECK-NEXT: mul.16b v0, v[[REGNUM]], v[[REGNUM]]
 entry:
-  %addr = getelementptr i8* %sp0, i64 1
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %addr = getelementptr i8, i8* %sp0, i64 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %vec = insertelement <16 x i8> undef, i8 %pix_sp0.0.copyload, i32 0
   %vmull.i = mul <16 x i8> %vec, %vec
   ret <16 x i8> %vmull.i
@@ -443,8 +443,8 @@ define <4 x i16> @fct18(i16* nocapture %sp0) {
 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
 ; CHECK-NEXT: mul.4h v0, v[[REGNUM]], v[[REGNUM]]
 entry:
-  %addr = getelementptr i16* %sp0, i64 1
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %addr = getelementptr i16, i16* %sp0, i64 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %vec = insertelement <4 x i16> undef, i16 %pix_sp0.0.copyload, i32 0
   %vmull.i = mul <4 x i16> %vec, %vec
   ret <4 x i16> %vmull.i
@@ -455,8 +455,8 @@ define <8 x i16> @fct19(i16* nocapture %sp0) {
 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
 ; CHECK-NEXT: mul.8h v0, v[[REGNUM]], v[[REGNUM]]
 entry:
-  %addr = getelementptr i16* %sp0, i64 1
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %addr = getelementptr i16, i16* %sp0, i64 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %vec = insertelement <8 x i16> undef, i16 %pix_sp0.0.copyload, i32 0
   %vmull.i = mul <8 x i16> %vec, %vec
   ret <8 x i16> %vmull.i
@@ -467,8 +467,8 @@ define <2 x i32> @fct20(i32* nocapture %sp0) {
 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
 ; CHECK-NEXT: mul.2s v0, v[[REGNUM]], v[[REGNUM]]
 entry:
-  %addr = getelementptr i32* %sp0, i64 1
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %addr = getelementptr i32, i32* %sp0, i64 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
   %vmull.i = mul <2 x i32> %vec, %vec
   ret <2 x i32> %vmull.i
@@ -479,8 +479,8 @@ define <4 x i32> @fct21(i32* nocapture %sp0) {
 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
 ; CHECK-NEXT: mul.4s v0, v[[REGNUM]], v[[REGNUM]]
 entry:
-  %addr = getelementptr i32* %sp0, i64 1
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %addr = getelementptr i32, i32* %sp0, i64 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %vec = insertelement <4 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
   %vmull.i = mul <4 x i32> %vec, %vec
   ret <4 x i32> %vmull.i
@@ -490,8 +490,8 @@ define <1 x i64> @fct22(i64* nocapture %sp0) {
 ; CHECK-LABEL: fct22:
 ; CHECK: ldr d0, [x0, #8]
 entry:
-  %addr = getelementptr i64* %sp0, i64 1
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %addr = getelementptr i64, i64* %sp0, i64 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %vec = insertelement <1 x i64> undef, i64 %pix_sp0.0.copyload, i32 0
    ret <1 x i64> %vec
 }
@@ -500,8 +500,8 @@ define <2 x i64> @fct23(i64* nocapture %sp0) {
 ; CHECK-LABEL: fct23:
 ; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, #8]
 entry:
-  %addr = getelementptr i64* %sp0, i64 1
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %addr = getelementptr i64, i64* %sp0, i64 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %vec = insertelement <2 x i64> undef, i64 %pix_sp0.0.copyload, i32 0
   ret <2 x i64> %vec
 }
@@ -513,8 +513,8 @@ define <8 x i8> @fct24(i8* nocapture %sp0, i64 %offset) {
 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
 ; CHECK-NEXT: mul.8b v0, v[[REGNUM]], v[[REGNUM]]
 entry:
-  %addr = getelementptr i8* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %addr = getelementptr i8, i8* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %vec = insertelement <8 x i8> undef, i8 %pix_sp0.0.copyload, i32 0
   %vmull.i = mul <8 x i8> %vec, %vec
   ret <8 x i8> %vmull.i
@@ -525,8 +525,8 @@ define <16 x i8> @fct25(i8* nocapture %sp0, i64 %offset) {
 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
 ; CHECK-NEXT: mul.16b v0, v[[REGNUM]], v[[REGNUM]]
 entry:
-  %addr = getelementptr i8* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %addr = getelementptr i8, i8* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %vec = insertelement <16 x i8> undef, i8 %pix_sp0.0.copyload, i32 0
   %vmull.i = mul <16 x i8> %vec, %vec
   ret <16 x i8> %vmull.i
@@ -537,8 +537,8 @@ define <4 x i16> @fct26(i16* nocapture %sp0, i64 %offset) {
 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
 ; CHECK-NEXT: mul.4h v0, v[[REGNUM]], v[[REGNUM]]
 entry:
-  %addr = getelementptr i16* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %addr = getelementptr i16, i16* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %vec = insertelement <4 x i16> undef, i16 %pix_sp0.0.copyload, i32 0
   %vmull.i = mul <4 x i16> %vec, %vec
   ret <4 x i16> %vmull.i
@@ -549,8 +549,8 @@ define <8 x i16> @fct27(i16* nocapture %sp0, i64 %offset) {
 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
 ; CHECK-NEXT: mul.8h v0, v[[REGNUM]], v[[REGNUM]]
 entry:
-  %addr = getelementptr i16* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %addr = getelementptr i16, i16* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %vec = insertelement <8 x i16> undef, i16 %pix_sp0.0.copyload, i32 0
   %vmull.i = mul <8 x i16> %vec, %vec
   ret <8 x i16> %vmull.i
@@ -561,8 +561,8 @@ define <2 x i32> @fct28(i32* nocapture %sp0, i64 %offset) {
 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
 ; CHECK-NEXT: mul.2s v0, v[[REGNUM]], v[[REGNUM]]
 entry:
-  %addr = getelementptr i32* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %addr = getelementptr i32, i32* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
   %vmull.i = mul <2 x i32> %vec, %vec
   ret <2 x i32> %vmull.i
@@ -573,8 +573,8 @@ define <4 x i32> @fct29(i32* nocapture %sp0, i64 %offset) {
 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
 ; CHECK-NEXT: mul.4s v0, v[[REGNUM]], v[[REGNUM]]
 entry:
-  %addr = getelementptr i32* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %addr = getelementptr i32, i32* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %vec = insertelement <4 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
   %vmull.i = mul <4 x i32> %vec, %vec
   ret <4 x i32> %vmull.i
@@ -584,8 +584,8 @@ define <1 x i64> @fct30(i64* nocapture %sp0, i64 %offset) {
 ; CHECK-LABEL: fct30:
 ; CHECK: ldr d0, [x0, x1, lsl #3]
 entry:
-  %addr = getelementptr i64* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %addr = getelementptr i64, i64* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %vec = insertelement <1 x i64> undef, i64 %pix_sp0.0.copyload, i32 0
    ret <1 x i64> %vec
 }
@@ -594,8 +594,8 @@ define <2 x i64> @fct31(i64* nocapture %sp0, i64 %offset) {
 ; CHECK-LABEL: fct31:
 ; CHECK: ldr d0, [x0, x1, lsl #3]
 entry:
-  %addr = getelementptr i64* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %addr = getelementptr i64, i64* %sp0, i64 %offset
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %vec = insertelement <2 x i64> undef, i64 %pix_sp0.0.copyload, i32 0
   ret <2 x i64> %vec
 }
diff --git a/test/CodeGen/AArch64/arm64-vext.ll b/test/CodeGen/AArch64/arm64-vext.ll
index 2240dfd5a1ae..fa57eeb246cc 100644
--- a/test/CodeGen/AArch64/arm64-vext.ll
+++ b/test/CodeGen/AArch64/arm64-vext.ll
@@ -6,12 +6,12 @@ define void @test_vext_s8() nounwind ssp {
   %xS8x8 = alloca <8 x i8>, align 8
   %__a = alloca <8 x i8>, align 8
   %__b = alloca <8 x i8>, align 8
-  %tmp = load <8 x i8>* %xS8x8, align 8
+  %tmp = load <8 x i8>, <8 x i8>* %xS8x8, align 8
   store <8 x i8> %tmp, <8 x i8>* %__a, align 8
-  %tmp1 = load <8 x i8>* %xS8x8, align 8
+  %tmp1 = load <8 x i8>, <8 x i8>* %xS8x8, align 8
   store <8 x i8> %tmp1, <8 x i8>* %__b, align 8
-  %tmp2 = load <8 x i8>* %__a, align 8
-  %tmp3 = load <8 x i8>* %__b, align 8
+  %tmp2 = load <8 x i8>, <8 x i8>* %__a, align 8
+  %tmp3 = load <8 x i8>, <8 x i8>* %__b, align 8
   %vext = shufflevector <8 x i8> %tmp2, <8 x i8> %tmp3, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
   store <8 x i8> %vext, <8 x i8>* %xS8x8, align 8
   ret void
@@ -23,12 +23,12 @@ define void @test_vext_u8() nounwind ssp {
   %xU8x8 = alloca <8 x i8>, align 8
   %__a = alloca <8 x i8>, align 8
   %__b = alloca <8 x i8>, align 8
-  %tmp = load <8 x i8>* %xU8x8, align 8
+  %tmp = load <8 x i8>, <8 x i8>* %xU8x8, align 8
   store <8 x i8> %tmp, <8 x i8>* %__a, align 8
-  %tmp1 = load <8 x i8>* %xU8x8, align 8
+  %tmp1 = load <8 x i8>, <8 x i8>* %xU8x8, align 8
   store <8 x i8> %tmp1, <8 x i8>* %__b, align 8
-  %tmp2 = load <8 x i8>* %__a, align 8
-  %tmp3 = load <8 x i8>* %__b, align 8
+  %tmp2 = load <8 x i8>, <8 x i8>* %__a, align 8
+  %tmp3 = load <8 x i8>, <8 x i8>* %__b, align 8
   %vext = shufflevector <8 x i8> %tmp2, <8 x i8> %tmp3, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
   store <8 x i8> %vext, <8 x i8>* %xU8x8, align 8
   ret void
@@ -40,12 +40,12 @@ define void @test_vext_p8() nounwind ssp {
   %xP8x8 = alloca <8 x i8>, align 8
   %__a = alloca <8 x i8>, align 8
   %__b = alloca <8 x i8>, align 8
-  %tmp = load <8 x i8>* %xP8x8, align 8
+  %tmp = load <8 x i8>, <8 x i8>* %xP8x8, align 8
   store <8 x i8> %tmp, <8 x i8>* %__a, align 8
-  %tmp1 = load <8 x i8>* %xP8x8, align 8
+  %tmp1 = load <8 x i8>, <8 x i8>* %xP8x8, align 8
   store <8 x i8> %tmp1, <8 x i8>* %__b, align 8
-  %tmp2 = load <8 x i8>* %__a, align 8
-  %tmp3 = load <8 x i8>* %__b, align 8
+  %tmp2 = load <8 x i8>, <8 x i8>* %__a, align 8
+  %tmp3 = load <8 x i8>, <8 x i8>* %__b, align 8
   %vext = shufflevector <8 x i8> %tmp2, <8 x i8> %tmp3, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
   store <8 x i8> %vext, <8 x i8>* %xP8x8, align 8
   ret void
@@ -57,13 +57,13 @@ define void @test_vext_s16() nounwind ssp {
   %xS16x4 = alloca <4 x i16>, align 8
   %__a = alloca <4 x i16>, align 8
   %__b = alloca <4 x i16>, align 8
-  %tmp = load <4 x i16>* %xS16x4, align 8
+  %tmp = load <4 x i16>, <4 x i16>* %xS16x4, align 8
   store <4 x i16> %tmp, <4 x i16>* %__a, align 8
-  %tmp1 = load <4 x i16>* %xS16x4, align 8
+  %tmp1 = load <4 x i16>, <4 x i16>* %xS16x4, align 8
   store <4 x i16> %tmp1, <4 x i16>* %__b, align 8
-  %tmp2 = load <4 x i16>* %__a, align 8
+  %tmp2 = load <4 x i16>, <4 x i16>* %__a, align 8
   %tmp3 = bitcast <4 x i16> %tmp2 to <8 x i8>
-  %tmp4 = load <4 x i16>* %__b, align 8
+  %tmp4 = load <4 x i16>, <4 x i16>* %__b, align 8
   %tmp5 = bitcast <4 x i16> %tmp4 to <8 x i8>
   %tmp6 = bitcast <8 x i8> %tmp3 to <4 x i16>
   %tmp7 = bitcast <8 x i8> %tmp5 to <4 x i16>
@@ -78,13 +78,13 @@ define void @test_vext_u16() nounwind ssp {
   %xU16x4 = alloca <4 x i16>, align 8
   %__a = alloca <4 x i16>, align 8
   %__b = alloca <4 x i16>, align 8
-  %tmp = load <4 x i16>* %xU16x4, align 8
+  %tmp = load <4 x i16>, <4 x i16>* %xU16x4, align 8
   store <4 x i16> %tmp, <4 x i16>* %__a, align 8
-  %tmp1 = load <4 x i16>* %xU16x4, align 8
+  %tmp1 = load <4 x i16>, <4 x i16>* %xU16x4, align 8
   store <4 x i16> %tmp1, <4 x i16>* %__b, align 8
-  %tmp2 = load <4 x i16>* %__a, align 8
+  %tmp2 = load <4 x i16>, <4 x i16>* %__a, align 8
   %tmp3 = bitcast <4 x i16> %tmp2 to <8 x i8>
-  %tmp4 = load <4 x i16>* %__b, align 8
+  %tmp4 = load <4 x i16>, <4 x i16>* %__b, align 8
   %tmp5 = bitcast <4 x i16> %tmp4 to <8 x i8>
   %tmp6 = bitcast <8 x i8> %tmp3 to <4 x i16>
   %tmp7 = bitcast <8 x i8> %tmp5 to <4 x i16>
@@ -99,13 +99,13 @@ define void @test_vext_p16() nounwind ssp {
   %xP16x4 = alloca <4 x i16>, align 8
   %__a = alloca <4 x i16>, align 8
   %__b = alloca <4 x i16>, align 8
-  %tmp = load <4 x i16>* %xP16x4, align 8
+  %tmp = load <4 x i16>, <4 x i16>* %xP16x4, align 8
   store <4 x i16> %tmp, <4 x i16>* %__a, align 8
-  %tmp1 = load <4 x i16>* %xP16x4, align 8
+  %tmp1 = load <4 x i16>, <4 x i16>* %xP16x4, align 8
   store <4 x i16> %tmp1, <4 x i16>* %__b, align 8
-  %tmp2 = load <4 x i16>* %__a, align 8
+  %tmp2 = load <4 x i16>, <4 x i16>* %__a, align 8
   %tmp3 = bitcast <4 x i16> %tmp2 to <8 x i8>
-  %tmp4 = load <4 x i16>* %__b, align 8
+  %tmp4 = load <4 x i16>, <4 x i16>* %__b, align 8
   %tmp5 = bitcast <4 x i16> %tmp4 to <8 x i8>
   %tmp6 = bitcast <8 x i8> %tmp3 to <4 x i16>
   %tmp7 = bitcast <8 x i8> %tmp5 to <4 x i16>
@@ -120,13 +120,13 @@ define void @test_vext_s32() nounwind ssp {
   %xS32x2 = alloca <2 x i32>, align 8
   %__a = alloca <2 x i32>, align 8
   %__b = alloca <2 x i32>, align 8
-  %tmp = load <2 x i32>* %xS32x2, align 8
+  %tmp = load <2 x i32>, <2 x i32>* %xS32x2, align 8
   store <2 x i32> %tmp, <2 x i32>* %__a, align 8
-  %tmp1 = load <2 x i32>* %xS32x2, align 8
+  %tmp1 = load <2 x i32>, <2 x i32>* %xS32x2, align 8
   store <2 x i32> %tmp1, <2 x i32>* %__b, align 8
-  %tmp2 = load <2 x i32>* %__a, align 8
+  %tmp2 = load <2 x i32>, <2 x i32>* %__a, align 8
   %tmp3 = bitcast <2 x i32> %tmp2 to <8 x i8>
-  %tmp4 = load <2 x i32>* %__b, align 8
+  %tmp4 = load <2 x i32>, <2 x i32>* %__b, align 8
   %tmp5 = bitcast <2 x i32> %tmp4 to <8 x i8>
   %tmp6 = bitcast <8 x i8> %tmp3 to <2 x i32>
   %tmp7 = bitcast <8 x i8> %tmp5 to <2 x i32>
@@ -141,13 +141,13 @@ define void @test_vext_u32() nounwind ssp {
   %xU32x2 = alloca <2 x i32>, align 8
   %__a = alloca <2 x i32>, align 8
   %__b = alloca <2 x i32>, align 8
-  %tmp = load <2 x i32>* %xU32x2, align 8
+  %tmp = load <2 x i32>, <2 x i32>* %xU32x2, align 8
   store <2 x i32> %tmp, <2 x i32>* %__a, align 8
-  %tmp1 = load <2 x i32>* %xU32x2, align 8
+  %tmp1 = load <2 x i32>, <2 x i32>* %xU32x2, align 8
   store <2 x i32> %tmp1, <2 x i32>* %__b, align 8
-  %tmp2 = load <2 x i32>* %__a, align 8
+  %tmp2 = load <2 x i32>, <2 x i32>* %__a, align 8
   %tmp3 = bitcast <2 x i32> %tmp2 to <8 x i8>
-  %tmp4 = load <2 x i32>* %__b, align 8
+  %tmp4 = load <2 x i32>, <2 x i32>* %__b, align 8
   %tmp5 = bitcast <2 x i32> %tmp4 to <8 x i8>
   %tmp6 = bitcast <8 x i8> %tmp3 to <2 x i32>
   %tmp7 = bitcast <8 x i8> %tmp5 to <2 x i32>
@@ -162,13 +162,13 @@ define void @test_vext_f32() nounwind ssp {
   %xF32x2 = alloca <2 x float>, align 8
   %__a = alloca <2 x float>, align 8
   %__b = alloca <2 x float>, align 8
-  %tmp = load <2 x float>* %xF32x2, align 8
+  %tmp = load <2 x float>, <2 x float>* %xF32x2, align 8
   store <2 x float> %tmp, <2 x float>* %__a, align 8
-  %tmp1 = load <2 x float>* %xF32x2, align 8
+  %tmp1 = load <2 x float>, <2 x float>* %xF32x2, align 8
   store <2 x float> %tmp1, <2 x float>* %__b, align 8
-  %tmp2 = load <2 x float>* %__a, align 8
+  %tmp2 = load <2 x float>, <2 x float>* %__a, align 8
   %tmp3 = bitcast <2 x float> %tmp2 to <8 x i8>
-  %tmp4 = load <2 x float>* %__b, align 8
+  %tmp4 = load <2 x float>, <2 x float>* %__b, align 8
   %tmp5 = bitcast <2 x float> %tmp4 to <8 x i8>
   %tmp6 = bitcast <8 x i8> %tmp3 to <2 x float>
   %tmp7 = bitcast <8 x i8> %tmp5 to <2 x float>
@@ -184,13 +184,13 @@ define void @test_vext_s64() nounwind ssp {
   %xS64x1 = alloca <1 x i64>, align 8
   %__a = alloca <1 x i64>, align 8
   %__b = alloca <1 x i64>, align 8
-  %tmp = load <1 x i64>* %xS64x1, align 8
+  %tmp = load <1 x i64>, <1 x i64>* %xS64x1, align 8
   store <1 x i64> %tmp, <1 x i64>* %__a, align 8
-  %tmp1 = load <1 x i64>* %xS64x1, align 8
+  %tmp1 = load <1 x i64>, <1 x i64>* %xS64x1, align 8
   store <1 x i64> %tmp1, <1 x i64>* %__b, align 8
-  %tmp2 = load <1 x i64>* %__a, align 8
+  %tmp2 = load <1 x i64>, <1 x i64>* %__a, align 8
   %tmp3 = bitcast <1 x i64> %tmp2 to <8 x i8>
-  %tmp4 = load <1 x i64>* %__b, align 8
+  %tmp4 = load <1 x i64>, <1 x i64>* %__b, align 8
   %tmp5 = bitcast <1 x i64> %tmp4 to <8 x i8>
   %tmp6 = bitcast <8 x i8> %tmp3 to <1 x i64>
   %tmp7 = bitcast <8 x i8> %tmp5 to <1 x i64>
@@ -206,13 +206,13 @@ define void @test_vext_u64() nounwind ssp {
   %xU64x1 = alloca <1 x i64>, align 8
   %__a = alloca <1 x i64>, align 8
   %__b = alloca <1 x i64>, align 8
-  %tmp = load <1 x i64>* %xU64x1, align 8
+  %tmp = load <1 x i64>, <1 x i64>* %xU64x1, align 8
   store <1 x i64> %tmp, <1 x i64>* %__a, align 8
-  %tmp1 = load <1 x i64>* %xU64x1, align 8
+  %tmp1 = load <1 x i64>, <1 x i64>* %xU64x1, align 8
   store <1 x i64> %tmp1, <1 x i64>* %__b, align 8
-  %tmp2 = load <1 x i64>* %__a, align 8
+  %tmp2 = load <1 x i64>, <1 x i64>* %__a, align 8
   %tmp3 = bitcast <1 x i64> %tmp2 to <8 x i8>
-  %tmp4 = load <1 x i64>* %__b, align 8
+  %tmp4 = load <1 x i64>, <1 x i64>* %__b, align 8
   %tmp5 = bitcast <1 x i64> %tmp4 to <8 x i8>
   %tmp6 = bitcast <8 x i8> %tmp3 to <1 x i64>
   %tmp7 = bitcast <8 x i8> %tmp5 to <1 x i64>
@@ -227,12 +227,12 @@ define void @test_vextq_s8() nounwind ssp {
   %xS8x16 = alloca <16 x i8>, align 16
   %__a = alloca <16 x i8>, align 16
   %__b = alloca <16 x i8>, align 16
-  %tmp = load <16 x i8>* %xS8x16, align 16
+  %tmp = load <16 x i8>, <16 x i8>* %xS8x16, align 16
   store <16 x i8> %tmp, <16 x i8>* %__a, align 16
-  %tmp1 = load <16 x i8>* %xS8x16, align 16
+  %tmp1 = load <16 x i8>, <16 x i8>* %xS8x16, align 16
   store <16 x i8> %tmp1, <16 x i8>* %__b, align 16
-  %tmp2 = load <16 x i8>* %__a, align 16
-  %tmp3 = load <16 x i8>* %__b, align 16
+  %tmp2 = load <16 x i8>, <16 x i8>* %__a, align 16
+  %tmp3 = load <16 x i8>, <16 x i8>* %__b, align 16
   %vext = shufflevector <16 x i8> %tmp2, <16 x i8> %tmp3, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
   store <16 x i8> %vext, <16 x i8>* %xS8x16, align 16
   ret void
@@ -244,12 +244,12 @@ define void @test_vextq_u8() nounwind ssp {
   %xU8x16 = alloca <16 x i8>, align 16
   %__a = alloca <16 x i8>, align 16
   %__b = alloca <16 x i8>, align 16
-  %tmp = load <16 x i8>* %xU8x16, align 16
+  %tmp = load <16 x i8>, <16 x i8>* %xU8x16, align 16
   store <16 x i8> %tmp, <16 x i8>* %__a, align 16
-  %tmp1 = load <16 x i8>* %xU8x16, align 16
+  %tmp1 = load <16 x i8>, <16 x i8>* %xU8x16, align 16
   store <16 x i8> %tmp1, <16 x i8>* %__b, align 16
-  %tmp2 = load <16 x i8>* %__a, align 16
-  %tmp3 = load <16 x i8>* %__b, align 16
+  %tmp2 = load <16 x i8>, <16 x i8>* %__a, align 16
+  %tmp3 = load <16 x i8>, <16 x i8>* %__b, align 16
   %vext = shufflevector <16 x i8> %tmp2, <16 x i8> %tmp3, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20>
   store <16 x i8> %vext, <16 x i8>* %xU8x16, align 16
   ret void
@@ -261,12 +261,12 @@ define void @test_vextq_p8() nounwind ssp {
   %xP8x16 = alloca <16 x i8>, align 16
   %__a = alloca <16 x i8>, align 16
   %__b = alloca <16 x i8>, align 16
-  %tmp = load <16 x i8>* %xP8x16, align 16
+  %tmp = load <16 x i8>, <16 x i8>* %xP8x16, align 16
   store <16 x i8> %tmp, <16 x i8>* %__a, align 16
-  %tmp1 = load <16 x i8>* %xP8x16, align 16
+  %tmp1 = load <16 x i8>, <16 x i8>* %xP8x16, align 16
   store <16 x i8> %tmp1, <16 x i8>* %__b, align 16
-  %tmp2 = load <16 x i8>* %__a, align 16
-  %tmp3 = load <16 x i8>* %__b, align 16
+  %tmp2 = load <16 x i8>, <16 x i8>* %__a, align 16
+  %tmp3 = load <16 x i8>, <16 x i8>* %__b, align 16
   %vext = shufflevector <16 x i8> %tmp2, <16 x i8> %tmp3, <16 x i32> <i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21>
   store <16 x i8> %vext, <16 x i8>* %xP8x16, align 16
   ret void
@@ -278,13 +278,13 @@ define void @test_vextq_s16() nounwind ssp {
   %xS16x8 = alloca <8 x i16>, align 16
   %__a = alloca <8 x i16>, align 16
   %__b = alloca <8 x i16>, align 16
-  %tmp = load <8 x i16>* %xS16x8, align 16
+  %tmp = load <8 x i16>, <8 x i16>* %xS16x8, align 16
   store <8 x i16> %tmp, <8 x i16>* %__a, align 16
-  %tmp1 = load <8 x i16>* %xS16x8, align 16
+  %tmp1 = load <8 x i16>, <8 x i16>* %xS16x8, align 16
   store <8 x i16> %tmp1, <8 x i16>* %__b, align 16
-  %tmp2 = load <8 x i16>* %__a, align 16
+  %tmp2 = load <8 x i16>, <8 x i16>* %__a, align 16
   %tmp3 = bitcast <8 x i16> %tmp2 to <16 x i8>
-  %tmp4 = load <8 x i16>* %__b, align 16
+  %tmp4 = load <8 x i16>, <8 x i16>* %__b, align 16
   %tmp5 = bitcast <8 x i16> %tmp4 to <16 x i8>
   %tmp6 = bitcast <16 x i8> %tmp3 to <8 x i16>
   %tmp7 = bitcast <16 x i8> %tmp5 to <8 x i16>
@@ -299,13 +299,13 @@ define void @test_vextq_u16() nounwind ssp {
   %xU16x8 = alloca <8 x i16>, align 16
   %__a = alloca <8 x i16>, align 16
   %__b = alloca <8 x i16>, align 16
-  %tmp = load <8 x i16>* %xU16x8, align 16
+  %tmp = load <8 x i16>, <8 x i16>* %xU16x8, align 16
   store <8 x i16> %tmp, <8 x i16>* %__a, align 16
-  %tmp1 = load <8 x i16>* %xU16x8, align 16
+  %tmp1 = load <8 x i16>, <8 x i16>* %xU16x8, align 16
   store <8 x i16> %tmp1, <8 x i16>* %__b, align 16
-  %tmp2 = load <8 x i16>* %__a, align 16
+  %tmp2 = load <8 x i16>, <8 x i16>* %__a, align 16
   %tmp3 = bitcast <8 x i16> %tmp2 to <16 x i8>
-  %tmp4 = load <8 x i16>* %__b, align 16
+  %tmp4 = load <8 x i16>, <8 x i16>* %__b, align 16
   %tmp5 = bitcast <8 x i16> %tmp4 to <16 x i8>
   %tmp6 = bitcast <16 x i8> %tmp3 to <8 x i16>
   %tmp7 = bitcast <16 x i8> %tmp5 to <8 x i16>
@@ -320,13 +320,13 @@ define void @test_vextq_p16() nounwind ssp {
   %xP16x8 = alloca <8 x i16>, align 16
   %__a = alloca <8 x i16>, align 16
   %__b = alloca <8 x i16>, align 16
-  %tmp = load <8 x i16>* %xP16x8, align 16
+  %tmp = load <8 x i16>, <8 x i16>* %xP16x8, align 16
   store <8 x i16> %tmp, <8 x i16>* %__a, align 16
-  %tmp1 = load <8 x i16>* %xP16x8, align 16
+  %tmp1 = load <8 x i16>, <8 x i16>* %xP16x8, align 16
   store <8 x i16> %tmp1, <8 x i16>* %__b, align 16
-  %tmp2 = load <8 x i16>* %__a, align 16
+  %tmp2 = load <8 x i16>, <8 x i16>* %__a, align 16
   %tmp3 = bitcast <8 x i16> %tmp2 to <16 x i8>
-  %tmp4 = load <8 x i16>* %__b, align 16
+  %tmp4 = load <8 x i16>, <8 x i16>* %__b, align 16
   %tmp5 = bitcast <8 x i16> %tmp4 to <16 x i8>
   %tmp6 = bitcast <16 x i8> %tmp3 to <8 x i16>
   %tmp7 = bitcast <16 x i8> %tmp5 to <8 x i16>
@@ -341,13 +341,13 @@ define void @test_vextq_s32() nounwind ssp {
   %xS32x4 = alloca <4 x i32>, align 16
   %__a = alloca <4 x i32>, align 16
   %__b = alloca <4 x i32>, align 16
-  %tmp = load <4 x i32>* %xS32x4, align 16
+  %tmp = load <4 x i32>, <4 x i32>* %xS32x4, align 16
   store <4 x i32> %tmp, <4 x i32>* %__a, align 16
-  %tmp1 = load <4 x i32>* %xS32x4, align 16
+  %tmp1 = load <4 x i32>, <4 x i32>* %xS32x4, align 16
   store <4 x i32> %tmp1, <4 x i32>* %__b, align 16
-  %tmp2 = load <4 x i32>* %__a, align 16
+  %tmp2 = load <4 x i32>, <4 x i32>* %__a, align 16
   %tmp3 = bitcast <4 x i32> %tmp2 to <16 x i8>
-  %tmp4 = load <4 x i32>* %__b, align 16
+  %tmp4 = load <4 x i32>, <4 x i32>* %__b, align 16
   %tmp5 = bitcast <4 x i32> %tmp4 to <16 x i8>
   %tmp6 = bitcast <16 x i8> %tmp3 to <4 x i32>
   %tmp7 = bitcast <16 x i8> %tmp5 to <4 x i32>
@@ -362,13 +362,13 @@ define void @test_vextq_u32() nounwind ssp {
   %xU32x4 = alloca <4 x i32>, align 16
   %__a = alloca <4 x i32>, align 16
   %__b = alloca <4 x i32>, align 16
-  %tmp = load <4 x i32>* %xU32x4, align 16
+  %tmp = load <4 x i32>, <4 x i32>* %xU32x4, align 16
   store <4 x i32> %tmp, <4 x i32>* %__a, align 16
-  %tmp1 = load <4 x i32>* %xU32x4, align 16
+  %tmp1 = load <4 x i32>, <4 x i32>* %xU32x4, align 16
   store <4 x i32> %tmp1, <4 x i32>* %__b, align 16
-  %tmp2 = load <4 x i32>* %__a, align 16
+  %tmp2 = load <4 x i32>, <4 x i32>* %__a, align 16
   %tmp3 = bitcast <4 x i32> %tmp2 to <16 x i8>
-  %tmp4 = load <4 x i32>* %__b, align 16
+  %tmp4 = load <4 x i32>, <4 x i32>* %__b, align 16
   %tmp5 = bitcast <4 x i32> %tmp4 to <16 x i8>
   %tmp6 = bitcast <16 x i8> %tmp3 to <4 x i32>
   %tmp7 = bitcast <16 x i8> %tmp5 to <4 x i32>
@@ -383,13 +383,13 @@ define void @test_vextq_f32() nounwind ssp {
   %xF32x4 = alloca <4 x float>, align 16
   %__a = alloca <4 x float>, align 16
   %__b = alloca <4 x float>, align 16
-  %tmp = load <4 x float>* %xF32x4, align 16
+  %tmp = load <4 x float>, <4 x float>* %xF32x4, align 16
   store <4 x float> %tmp, <4 x float>* %__a, align 16
-  %tmp1 = load <4 x float>* %xF32x4, align 16
+  %tmp1 = load <4 x float>, <4 x float>* %xF32x4, align 16
   store <4 x float> %tmp1, <4 x float>* %__b, align 16
-  %tmp2 = load <4 x float>* %__a, align 16
+  %tmp2 = load <4 x float>, <4 x float>* %__a, align 16
   %tmp3 = bitcast <4 x float> %tmp2 to <16 x i8>
-  %tmp4 = load <4 x float>* %__b, align 16
+  %tmp4 = load <4 x float>, <4 x float>* %__b, align 16
   %tmp5 = bitcast <4 x float> %tmp4 to <16 x i8>
   %tmp6 = bitcast <16 x i8> %tmp3 to <4 x float>
   %tmp7 = bitcast <16 x i8> %tmp5 to <4 x float>
@@ -404,13 +404,13 @@ define void @test_vextq_s64() nounwind ssp {
   %xS64x2 = alloca <2 x i64>, align 16
   %__a = alloca <2 x i64>, align 16
   %__b = alloca <2 x i64>, align 16
-  %tmp = load <2 x i64>* %xS64x2, align 16
+  %tmp = load <2 x i64>, <2 x i64>* %xS64x2, align 16
   store <2 x i64> %tmp, <2 x i64>* %__a, align 16
-  %tmp1 = load <2 x i64>* %xS64x2, align 16
+  %tmp1 = load <2 x i64>, <2 x i64>* %xS64x2, align 16
   store <2 x i64> %tmp1, <2 x i64>* %__b, align 16
-  %tmp2 = load <2 x i64>* %__a, align 16
+  %tmp2 = load <2 x i64>, <2 x i64>* %__a, align 16
   %tmp3 = bitcast <2 x i64> %tmp2 to <16 x i8>
-  %tmp4 = load <2 x i64>* %__b, align 16
+  %tmp4 = load <2 x i64>, <2 x i64>* %__b, align 16
   %tmp5 = bitcast <2 x i64> %tmp4 to <16 x i8>
   %tmp6 = bitcast <16 x i8> %tmp3 to <2 x i64>
   %tmp7 = bitcast <16 x i8> %tmp5 to <2 x i64>
@@ -425,13 +425,13 @@ define void @test_vextq_u64() nounwind ssp {
   %xU64x2 = alloca <2 x i64>, align 16
   %__a = alloca <2 x i64>, align 16
   %__b = alloca <2 x i64>, align 16
-  %tmp = load <2 x i64>* %xU64x2, align 16
+  %tmp = load <2 x i64>, <2 x i64>* %xU64x2, align 16
   store <2 x i64> %tmp, <2 x i64>* %__a, align 16
-  %tmp1 = load <2 x i64>* %xU64x2, align 16
+  %tmp1 = load <2 x i64>, <2 x i64>* %xU64x2, align 16
   store <2 x i64> %tmp1, <2 x i64>* %__b, align 16
-  %tmp2 = load <2 x i64>* %__a, align 16
+  %tmp2 = load <2 x i64>, <2 x i64>* %__a, align 16
   %tmp3 = bitcast <2 x i64> %tmp2 to <16 x i8>
-  %tmp4 = load <2 x i64>* %__b, align 16
+  %tmp4 = load <2 x i64>, <2 x i64>* %__b, align 16
   %tmp5 = bitcast <2 x i64> %tmp4 to <16 x i8>
   %tmp6 = bitcast <16 x i8> %tmp3 to <2 x i64>
   %tmp7 = bitcast <16 x i8> %tmp5 to <2 x i64>
diff --git a/test/CodeGen/AArch64/arm64-vhadd.ll b/test/CodeGen/AArch64/arm64-vhadd.ll
index 6178bf9809dd..2e82b2a72541 100644
--- a/test/CodeGen/AArch64/arm64-vhadd.ll
+++ b/test/CodeGen/AArch64/arm64-vhadd.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @shadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: shadd8b:
 ;CHECK: shadd.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.shadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @shadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @shadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: shadd16b:
 ;CHECK: shadd.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.shadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -21,8 +21,8 @@ define <16 x i8> @shadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @shadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: shadd4h:
 ;CHECK: shadd.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.shadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -30,8 +30,8 @@ define <4 x i16> @shadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @shadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: shadd8h:
 ;CHECK: shadd.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -39,8 +39,8 @@ define <8 x i16> @shadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @shadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: shadd2s:
 ;CHECK: shadd.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.shadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -48,8 +48,8 @@ define <2 x i32> @shadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @shadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: shadd4s:
 ;CHECK: shadd.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.shadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -57,8 +57,8 @@ define <4 x i32> @shadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <8 x i8> @uhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: uhadd8b:
 ;CHECK: uhadd.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.uhadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -66,8 +66,8 @@ define <8 x i8> @uhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @uhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: uhadd16b:
 ;CHECK: uhadd.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.uhadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -75,8 +75,8 @@ define <16 x i8> @uhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @uhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: uhadd4h:
 ;CHECK: uhadd.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.uhadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -84,8 +84,8 @@ define <4 x i16> @uhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @uhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: uhadd8h:
 ;CHECK: uhadd.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -93,8 +93,8 @@ define <8 x i16> @uhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @uhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: uhadd2s:
 ;CHECK: uhadd.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.uhadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -102,8 +102,8 @@ define <2 x i32> @uhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @uhadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: uhadd4s:
 ;CHECK: uhadd.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.uhadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -127,8 +127,8 @@ declare <4 x i32> @llvm.aarch64.neon.uhadd.v4i32(<4 x i32>, <4 x i32>) nounwind
 define <8 x i8> @srhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: srhadd8b:
 ;CHECK: srhadd.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.srhadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -136,8 +136,8 @@ define <8 x i8> @srhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @srhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: srhadd16b:
 ;CHECK: srhadd.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.srhadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -145,8 +145,8 @@ define <16 x i8> @srhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @srhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: srhadd4h:
 ;CHECK: srhadd.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.srhadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -154,8 +154,8 @@ define <4 x i16> @srhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @srhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: srhadd8h:
 ;CHECK: srhadd.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -163,8 +163,8 @@ define <8 x i16> @srhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @srhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: srhadd2s:
 ;CHECK: srhadd.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.srhadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -172,8 +172,8 @@ define <2 x i32> @srhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @srhadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: srhadd4s:
 ;CHECK: srhadd.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.srhadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -181,8 +181,8 @@ define <4 x i32> @srhadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <8 x i8> @urhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: urhadd8b:
 ;CHECK: urhadd.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.urhadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -190,8 +190,8 @@ define <8 x i8> @urhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @urhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: urhadd16b:
 ;CHECK: urhadd.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.urhadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -199,8 +199,8 @@ define <16 x i8> @urhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @urhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: urhadd4h:
 ;CHECK: urhadd.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.urhadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -208,8 +208,8 @@ define <4 x i16> @urhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @urhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: urhadd8h:
 ;CHECK: urhadd.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -217,8 +217,8 @@ define <8 x i16> @urhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @urhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: urhadd2s:
 ;CHECK: urhadd.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.urhadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -226,8 +226,8 @@ define <2 x i32> @urhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @urhadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: urhadd4s:
 ;CHECK: urhadd.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.urhadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
diff --git a/test/CodeGen/AArch64/arm64-vhsub.ll b/test/CodeGen/AArch64/arm64-vhsub.ll
index 13bfda3899e5..e50fd3d35896 100644
--- a/test/CodeGen/AArch64/arm64-vhsub.ll
+++ b/test/CodeGen/AArch64/arm64-vhsub.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @shsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: shsub8b:
 ;CHECK: shsub.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.shsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @shsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @shsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: shsub16b:
 ;CHECK: shsub.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.shsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -21,8 +21,8 @@ define <16 x i8> @shsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @shsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: shsub4h:
 ;CHECK: shsub.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.shsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -30,8 +30,8 @@ define <4 x i16> @shsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @shsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: shsub8h:
 ;CHECK: shsub.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.shsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -39,8 +39,8 @@ define <8 x i16> @shsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @shsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: shsub2s:
 ;CHECK: shsub.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.shsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -48,8 +48,8 @@ define <2 x i32> @shsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @shsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: shsub4s:
 ;CHECK: shsub.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.shsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -57,8 +57,8 @@ define <4 x i32> @shsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <8 x i8> @uhsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: uhsub8b:
 ;CHECK: uhsub.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.uhsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -66,8 +66,8 @@ define <8 x i8> @uhsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @uhsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: uhsub16b:
 ;CHECK: uhsub.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.uhsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -75,8 +75,8 @@ define <16 x i8> @uhsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @uhsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: uhsub4h:
 ;CHECK: uhsub.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.uhsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -84,8 +84,8 @@ define <4 x i16> @uhsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @uhsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: uhsub8h:
 ;CHECK: uhsub.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.uhsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -93,8 +93,8 @@ define <8 x i16> @uhsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @uhsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: uhsub2s:
 ;CHECK: uhsub.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.uhsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -102,8 +102,8 @@ define <2 x i32> @uhsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @uhsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: uhsub4s:
 ;CHECK: uhsub.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.uhsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
diff --git a/test/CodeGen/AArch64/arm64-virtual_base.ll b/test/CodeGen/AArch64/arm64-virtual_base.ll
index cb9595453348..703d81a8d4fe 100644
--- a/test/CodeGen/AArch64/arm64-virtual_base.ll
+++ b/test/CodeGen/AArch64/arm64-virtual_base.ll
@@ -39,9 +39,9 @@ define void @Precompute_Patch_Values(%struct.Bicubic_Patch_Struct* %Shape) {
 ; CHECK-NEXT: stur [[VAL2]], {{\[}}sp, #216]
 entry:
   %Control_Points = alloca [16 x [3 x double]], align 8
-  %arraydecay5.3.1 = getelementptr inbounds [16 x [3 x double]]* %Control_Points, i64 0, i64 9, i64 0
+  %arraydecay5.3.1 = getelementptr inbounds [16 x [3 x double]], [16 x [3 x double]]* %Control_Points, i64 0, i64 9, i64 0
   %tmp14 = bitcast double* %arraydecay5.3.1 to i8*
-  %arraydecay11.3.1 = getelementptr inbounds %struct.Bicubic_Patch_Struct* %Shape, i64 0, i32 12, i64 1, i64 3, i64 0
+  %arraydecay11.3.1 = getelementptr inbounds %struct.Bicubic_Patch_Struct, %struct.Bicubic_Patch_Struct* %Shape, i64 0, i32 12, i64 1, i64 3, i64 0
   %tmp15 = bitcast double* %arraydecay11.3.1 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 24, i32 1, i1 false)
   ret void
diff --git a/test/CodeGen/AArch64/arm64-vmax.ll b/test/CodeGen/AArch64/arm64-vmax.ll
index 3f2c134dec6e..7e363231b360 100644
--- a/test/CodeGen/AArch64/arm64-vmax.ll
+++ b/test/CodeGen/AArch64/arm64-vmax.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @smax_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: smax_8b:
 ;CHECK: smax.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.smax.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @smax_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @smax_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: smax_16b:
 ;CHECK: smax.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.smax.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -21,8 +21,8 @@ define <16 x i8> @smax_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @smax_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: smax_4h:
 ;CHECK: smax.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.smax.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -30,8 +30,8 @@ define <4 x i16> @smax_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @smax_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: smax_8h:
 ;CHECK: smax.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.smax.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -39,8 +39,8 @@ define <8 x i16> @smax_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @smax_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: smax_2s:
 ;CHECK: smax.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -48,8 +48,8 @@ define <2 x i32> @smax_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @smax_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: smax_4s:
 ;CHECK: smax.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -64,8 +64,8 @@ declare <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32>, <4 x i32>) nounwind r
 define <8 x i8> @umax_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: umax_8b:
 ;CHECK: umax.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.umax.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -73,8 +73,8 @@ define <8 x i8> @umax_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @umax_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: umax_16b:
 ;CHECK: umax.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.umax.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -82,8 +82,8 @@ define <16 x i8> @umax_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @umax_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: umax_4h:
 ;CHECK: umax.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.umax.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -91,8 +91,8 @@ define <4 x i16> @umax_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @umax_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: umax_8h:
 ;CHECK: umax.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.umax.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -100,8 +100,8 @@ define <8 x i16> @umax_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @umax_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: umax_2s:
 ;CHECK: umax.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -109,8 +109,8 @@ define <2 x i32> @umax_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @umax_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: umax_4s:
 ;CHECK: umax.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -125,8 +125,8 @@ declare <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32>, <4 x i32>) nounwind r
 define <8 x i8> @smin_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: smin_8b:
 ;CHECK: smin.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.smin.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -134,8 +134,8 @@ define <8 x i8> @smin_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @smin_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: smin_16b:
 ;CHECK: smin.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.smin.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -143,8 +143,8 @@ define <16 x i8> @smin_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @smin_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: smin_4h:
 ;CHECK: smin.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.smin.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -152,8 +152,8 @@ define <4 x i16> @smin_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @smin_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: smin_8h:
 ;CHECK: smin.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.smin.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -161,8 +161,8 @@ define <8 x i16> @smin_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @smin_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: smin_2s:
 ;CHECK: smin.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.smin.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -170,8 +170,8 @@ define <2 x i32> @smin_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @smin_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: smin_4s:
 ;CHECK: smin.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -186,8 +186,8 @@ declare <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32>, <4 x i32>) nounwind r
 define <8 x i8> @umin_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: umin_8b:
 ;CHECK: umin.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.umin.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -195,8 +195,8 @@ define <8 x i8> @umin_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @umin_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: umin_16b:
 ;CHECK: umin.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.umin.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -204,8 +204,8 @@ define <16 x i8> @umin_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @umin_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: umin_4h:
 ;CHECK: umin.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.umin.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -213,8 +213,8 @@ define <4 x i16> @umin_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @umin_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: umin_8h:
 ;CHECK: umin.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.umin.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -222,8 +222,8 @@ define <8 x i16> @umin_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @umin_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: umin_2s:
 ;CHECK: umin.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -231,8 +231,8 @@ define <2 x i32> @umin_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @umin_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: umin_4s:
 ;CHECK: umin.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -249,8 +249,8 @@ declare <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32>, <4 x i32>) nounwind r
 define <8 x i8> @smaxp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: smaxp_8b:
 ;CHECK: smaxp.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.smaxp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -258,8 +258,8 @@ define <8 x i8> @smaxp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @smaxp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: smaxp_16b:
 ;CHECK: smaxp.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.smaxp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -267,8 +267,8 @@ define <16 x i8> @smaxp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @smaxp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: smaxp_4h:
 ;CHECK: smaxp.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.smaxp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -276,8 +276,8 @@ define <4 x i16> @smaxp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @smaxp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: smaxp_8h:
 ;CHECK: smaxp.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.smaxp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -285,8 +285,8 @@ define <8 x i16> @smaxp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @smaxp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: smaxp_2s:
 ;CHECK: smaxp.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.smaxp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -294,8 +294,8 @@ define <2 x i32> @smaxp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @smaxp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: smaxp_4s:
 ;CHECK: smaxp.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.smaxp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -310,8 +310,8 @@ declare <4 x i32> @llvm.aarch64.neon.smaxp.v4i32(<4 x i32>, <4 x i32>) nounwind
 define <8 x i8> @umaxp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: umaxp_8b:
 ;CHECK: umaxp.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.umaxp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -319,8 +319,8 @@ define <8 x i8> @umaxp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @umaxp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: umaxp_16b:
 ;CHECK: umaxp.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.umaxp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -328,8 +328,8 @@ define <16 x i8> @umaxp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @umaxp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: umaxp_4h:
 ;CHECK: umaxp.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.umaxp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -337,8 +337,8 @@ define <4 x i16> @umaxp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @umaxp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: umaxp_8h:
 ;CHECK: umaxp.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.umaxp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -346,8 +346,8 @@ define <8 x i16> @umaxp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @umaxp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: umaxp_2s:
 ;CHECK: umaxp.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.umaxp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -355,8 +355,8 @@ define <2 x i32> @umaxp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @umaxp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: umaxp_4s:
 ;CHECK: umaxp.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.umaxp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -373,8 +373,8 @@ declare <4 x i32> @llvm.aarch64.neon.umaxp.v4i32(<4 x i32>, <4 x i32>) nounwind
 define <8 x i8> @sminp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: sminp_8b:
 ;CHECK: sminp.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.sminp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -382,8 +382,8 @@ define <8 x i8> @sminp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @sminp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: sminp_16b:
 ;CHECK: sminp.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.sminp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -391,8 +391,8 @@ define <16 x i8> @sminp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @sminp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sminp_4h:
 ;CHECK: sminp.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.sminp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -400,8 +400,8 @@ define <4 x i16> @sminp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @sminp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sminp_8h:
 ;CHECK: sminp.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.sminp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -409,8 +409,8 @@ define <8 x i16> @sminp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @sminp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sminp_2s:
 ;CHECK: sminp.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.sminp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -418,8 +418,8 @@ define <2 x i32> @sminp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @sminp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sminp_4s:
 ;CHECK: sminp.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.sminp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -434,8 +434,8 @@ declare <4 x i32> @llvm.aarch64.neon.sminp.v4i32(<4 x i32>, <4 x i32>) nounwind
 define <8 x i8> @uminp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: uminp_8b:
 ;CHECK: uminp.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.uminp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -443,8 +443,8 @@ define <8 x i8> @uminp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @uminp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: uminp_16b:
 ;CHECK: uminp.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.uminp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -452,8 +452,8 @@ define <16 x i8> @uminp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @uminp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: uminp_4h:
 ;CHECK: uminp.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.uminp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -461,8 +461,8 @@ define <4 x i16> @uminp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @uminp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: uminp_8h:
 ;CHECK: uminp.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.uminp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -470,8 +470,8 @@ define <8 x i16> @uminp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @uminp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: uminp_2s:
 ;CHECK: uminp.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.uminp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -479,8 +479,8 @@ define <2 x i32> @uminp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @uminp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: uminp_4s:
 ;CHECK: uminp.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.uminp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -495,8 +495,8 @@ declare <4 x i32> @llvm.aarch64.neon.uminp.v4i32(<4 x i32>, <4 x i32>) nounwind
 define <2 x float> @fmax_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: fmax_2s:
 ;CHECK: fmax.2s
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.aarch64.neon.fmax.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
@@ -504,8 +504,8 @@ define <2 x float> @fmax_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x float> @fmax_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: fmax_4s:
 ;CHECK: fmax.4s
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x float> @llvm.aarch64.neon.fmax.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x float> %tmp3
 }
@@ -513,8 +513,8 @@ define <4 x float> @fmax_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x double> @fmax_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
 ;CHECK-LABEL: fmax_2d:
 ;CHECK: fmax.2d
-	%tmp1 = load <2 x double>* %A
-	%tmp2 = load <2 x double>* %B
+	%tmp1 = load <2 x double>, <2 x double>* %A
+	%tmp2 = load <2 x double>, <2 x double>* %B
 	%tmp3 = call <2 x double> @llvm.aarch64.neon.fmax.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
 	ret <2 x double> %tmp3
 }
@@ -526,8 +526,8 @@ declare <2 x double> @llvm.aarch64.neon.fmax.v2f64(<2 x double>, <2 x double>) n
 define <2 x float> @fmaxp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: fmaxp_2s:
 ;CHECK: fmaxp.2s
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.aarch64.neon.fmaxp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
@@ -535,8 +535,8 @@ define <2 x float> @fmaxp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x float> @fmaxp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: fmaxp_4s:
 ;CHECK: fmaxp.4s
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x float> @llvm.aarch64.neon.fmaxp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x float> %tmp3
 }
@@ -544,8 +544,8 @@ define <4 x float> @fmaxp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x double> @fmaxp_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
 ;CHECK-LABEL: fmaxp_2d:
 ;CHECK: fmaxp.2d
-	%tmp1 = load <2 x double>* %A
-	%tmp2 = load <2 x double>* %B
+	%tmp1 = load <2 x double>, <2 x double>* %A
+	%tmp2 = load <2 x double>, <2 x double>* %B
 	%tmp3 = call <2 x double> @llvm.aarch64.neon.fmaxp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
 	ret <2 x double> %tmp3
 }
@@ -557,8 +557,8 @@ declare <2 x double> @llvm.aarch64.neon.fmaxp.v2f64(<2 x double>, <2 x double>)
 define <2 x float> @fmin_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: fmin_2s:
 ;CHECK: fmin.2s
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.aarch64.neon.fmin.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
@@ -566,8 +566,8 @@ define <2 x float> @fmin_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x float> @fmin_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: fmin_4s:
 ;CHECK: fmin.4s
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x float> @llvm.aarch64.neon.fmin.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x float> %tmp3
 }
@@ -575,8 +575,8 @@ define <4 x float> @fmin_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x double> @fmin_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
 ;CHECK-LABEL: fmin_2d:
 ;CHECK: fmin.2d
-	%tmp1 = load <2 x double>* %A
-	%tmp2 = load <2 x double>* %B
+	%tmp1 = load <2 x double>, <2 x double>* %A
+	%tmp2 = load <2 x double>, <2 x double>* %B
 	%tmp3 = call <2 x double> @llvm.aarch64.neon.fmin.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
 	ret <2 x double> %tmp3
 }
@@ -588,8 +588,8 @@ declare <2 x double> @llvm.aarch64.neon.fmin.v2f64(<2 x double>, <2 x double>) n
 define <2 x float> @fminp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: fminp_2s:
 ;CHECK: fminp.2s
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.aarch64.neon.fminp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
@@ -597,8 +597,8 @@ define <2 x float> @fminp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x float> @fminp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: fminp_4s:
 ;CHECK: fminp.4s
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x float> @llvm.aarch64.neon.fminp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x float> %tmp3
 }
@@ -606,8 +606,8 @@ define <4 x float> @fminp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x double> @fminp_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
 ;CHECK-LABEL: fminp_2d:
 ;CHECK: fminp.2d
-	%tmp1 = load <2 x double>* %A
-	%tmp2 = load <2 x double>* %B
+	%tmp1 = load <2 x double>, <2 x double>* %A
+	%tmp2 = load <2 x double>, <2 x double>* %B
 	%tmp3 = call <2 x double> @llvm.aarch64.neon.fminp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
 	ret <2 x double> %tmp3
 }
@@ -619,8 +619,8 @@ declare <2 x double> @llvm.aarch64.neon.fminp.v2f64(<2 x double>, <2 x double>)
 define <2 x float> @fminnmp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: fminnmp_2s:
 ;CHECK: fminnmp.2s
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.aarch64.neon.fminnmp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
@@ -628,8 +628,8 @@ define <2 x float> @fminnmp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x float> @fminnmp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: fminnmp_4s:
 ;CHECK: fminnmp.4s
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x float> @llvm.aarch64.neon.fminnmp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x float> %tmp3
 }
@@ -637,8 +637,8 @@ define <4 x float> @fminnmp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x double> @fminnmp_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
 ;CHECK-LABEL: fminnmp_2d:
 ;CHECK: fminnmp.2d
-	%tmp1 = load <2 x double>* %A
-	%tmp2 = load <2 x double>* %B
+	%tmp1 = load <2 x double>, <2 x double>* %A
+	%tmp2 = load <2 x double>, <2 x double>* %B
 	%tmp3 = call <2 x double> @llvm.aarch64.neon.fminnmp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
 	ret <2 x double> %tmp3
 }
@@ -650,8 +650,8 @@ declare <2 x double> @llvm.aarch64.neon.fminnmp.v2f64(<2 x double>, <2 x double>
 define <2 x float> @fmaxnmp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: fmaxnmp_2s:
 ;CHECK: fmaxnmp.2s
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.aarch64.neon.fmaxnmp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
@@ -659,8 +659,8 @@ define <2 x float> @fmaxnmp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x float> @fmaxnmp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: fmaxnmp_4s:
 ;CHECK: fmaxnmp.4s
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x float> @llvm.aarch64.neon.fmaxnmp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x float> %tmp3
 }
@@ -668,8 +668,8 @@ define <4 x float> @fmaxnmp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x double> @fmaxnmp_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
 ;CHECK-LABEL: fmaxnmp_2d:
 ;CHECK: fmaxnmp.2d
-	%tmp1 = load <2 x double>* %A
-	%tmp2 = load <2 x double>* %B
+	%tmp1 = load <2 x double>, <2 x double>* %A
+	%tmp2 = load <2 x double>, <2 x double>* %B
 	%tmp3 = call <2 x double> @llvm.aarch64.neon.fmaxnmp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
 	ret <2 x double> %tmp3
 }
diff --git a/test/CodeGen/AArch64/arm64-vmul.ll b/test/CodeGen/AArch64/arm64-vmul.ll
index 6fa60fe346af..3df847ec3748 100644
--- a/test/CodeGen/AArch64/arm64-vmul.ll
+++ b/test/CodeGen/AArch64/arm64-vmul.ll
@@ -4,8 +4,8 @@
 define <8 x i16> @smull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: smull8h:
 ;CHECK: smull.8h
-  %tmp1 = load <8 x i8>* %A
-  %tmp2 = load <8 x i8>* %B
+  %tmp1 = load <8 x i8>, <8 x i8>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
   ret <8 x i16> %tmp3
 }
@@ -13,8 +13,8 @@ define <8 x i16> @smull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @smull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: smull4s:
 ;CHECK: smull.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
   ret <4 x i32> %tmp3
 }
@@ -22,8 +22,8 @@ define <4 x i32> @smull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @smull2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: smull2d:
 ;CHECK: smull.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
   ret <2 x i64> %tmp3
 }
@@ -35,8 +35,8 @@ declare <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32>, <2 x i32>) nounwind
 define <8 x i16> @umull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: umull8h:
 ;CHECK: umull.8h
-  %tmp1 = load <8 x i8>* %A
-  %tmp2 = load <8 x i8>* %B
+  %tmp1 = load <8 x i8>, <8 x i8>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
   ret <8 x i16> %tmp3
 }
@@ -44,8 +44,8 @@ define <8 x i16> @umull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @umull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: umull4s:
 ;CHECK: umull.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
   ret <4 x i32> %tmp3
 }
@@ -53,8 +53,8 @@ define <4 x i32> @umull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @umull2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: umull2d:
 ;CHECK: umull.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
   ret <2 x i64> %tmp3
 }
@@ -66,8 +66,8 @@ declare <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32>, <2 x i32>) nounwind
 define <4 x i32> @sqdmull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqdmull4s:
 ;CHECK: sqdmull.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
   ret <4 x i32> %tmp3
 }
@@ -75,8 +75,8 @@ define <4 x i32> @sqdmull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @sqdmull2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqdmull2d:
 ;CHECK: sqdmull.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
   ret <2 x i64> %tmp3
 }
@@ -84,8 +84,8 @@ define <2 x i64> @sqdmull2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @sqdmull2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqdmull2_4s:
 ;CHECK: sqdmull2.4s
-  %load1 = load <8 x i16>* %A
-  %load2 = load <8 x i16>* %B
+  %load1 = load <8 x i16>, <8 x i16>* %A
+  %load2 = load <8 x i16>, <8 x i16>* %B
   %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -95,8 +95,8 @@ define <4 x i32> @sqdmull2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i64> @sqdmull2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqdmull2_2d:
 ;CHECK: sqdmull2.2d
-  %load1 = load <4 x i32>* %A
-  %load2 = load <4 x i32>* %B
+  %load1 = load <4 x i32>, <4 x i32>* %A
+  %load2 = load <4 x i32>, <4 x i32>* %B
   %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -110,8 +110,8 @@ declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>) nounwin
 define <8 x i16> @pmull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: pmull8h:
 ;CHECK: pmull.8h
-  %tmp1 = load <8 x i8>* %A
-  %tmp2 = load <8 x i8>* %B
+  %tmp1 = load <8 x i8>, <8 x i8>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
   ret <8 x i16> %tmp3
 }
@@ -121,8 +121,8 @@ declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>) nounwind re
 define <4 x i16> @sqdmulh_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqdmulh_4h:
 ;CHECK: sqdmulh.4h
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
   ret <4 x i16> %tmp3
 }
@@ -130,8 +130,8 @@ define <4 x i16> @sqdmulh_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @sqdmulh_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqdmulh_8h:
 ;CHECK: sqdmulh.8h
-  %tmp1 = load <8 x i16>* %A
-  %tmp2 = load <8 x i16>* %B
+  %tmp1 = load <8 x i16>, <8 x i16>* %A
+  %tmp2 = load <8 x i16>, <8 x i16>* %B
   %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
   ret <8 x i16> %tmp3
 }
@@ -139,8 +139,8 @@ define <8 x i16> @sqdmulh_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @sqdmulh_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqdmulh_2s:
 ;CHECK: sqdmulh.2s
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
   ret <2 x i32> %tmp3
 }
@@ -148,8 +148,8 @@ define <2 x i32> @sqdmulh_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @sqdmulh_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqdmulh_4s:
 ;CHECK: sqdmulh.4s
-  %tmp1 = load <4 x i32>* %A
-  %tmp2 = load <4 x i32>* %B
+  %tmp1 = load <4 x i32>, <4 x i32>* %A
+  %tmp2 = load <4 x i32>, <4 x i32>* %B
   %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
   ret <4 x i32> %tmp3
 }
@@ -157,8 +157,8 @@ define <4 x i32> @sqdmulh_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define i32 @sqdmulh_1s(i32* %A, i32* %B) nounwind {
 ;CHECK-LABEL: sqdmulh_1s:
 ;CHECK: sqdmulh s0, {{s[0-9]+}}, {{s[0-9]+}}
-  %tmp1 = load i32* %A
-  %tmp2 = load i32* %B
+  %tmp1 = load i32, i32* %A
+  %tmp2 = load i32, i32* %B
   %tmp3 = call i32 @llvm.aarch64.neon.sqdmulh.i32(i32 %tmp1, i32 %tmp2)
   ret i32 %tmp3
 }
@@ -172,8 +172,8 @@ declare i32 @llvm.aarch64.neon.sqdmulh.i32(i32, i32) nounwind readnone
 define <4 x i16> @sqrdmulh_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqrdmulh_4h:
 ;CHECK: sqrdmulh.4h
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
   ret <4 x i16> %tmp3
 }
@@ -181,8 +181,8 @@ define <4 x i16> @sqrdmulh_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @sqrdmulh_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqrdmulh_8h:
 ;CHECK: sqrdmulh.8h
-  %tmp1 = load <8 x i16>* %A
-  %tmp2 = load <8 x i16>* %B
+  %tmp1 = load <8 x i16>, <8 x i16>* %A
+  %tmp2 = load <8 x i16>, <8 x i16>* %B
   %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
   ret <8 x i16> %tmp3
 }
@@ -190,8 +190,8 @@ define <8 x i16> @sqrdmulh_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @sqrdmulh_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqrdmulh_2s:
 ;CHECK: sqrdmulh.2s
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
   ret <2 x i32> %tmp3
 }
@@ -199,8 +199,8 @@ define <2 x i32> @sqrdmulh_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @sqrdmulh_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqrdmulh_4s:
 ;CHECK: sqrdmulh.4s
-  %tmp1 = load <4 x i32>* %A
-  %tmp2 = load <4 x i32>* %B
+  %tmp1 = load <4 x i32>, <4 x i32>* %A
+  %tmp2 = load <4 x i32>, <4 x i32>* %B
   %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
   ret <4 x i32> %tmp3
 }
@@ -208,8 +208,8 @@ define <4 x i32> @sqrdmulh_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define i32 @sqrdmulh_1s(i32* %A, i32* %B) nounwind {
 ;CHECK-LABEL: sqrdmulh_1s:
 ;CHECK: sqrdmulh s0, {{s[0-9]+}}, {{s[0-9]+}}
-  %tmp1 = load i32* %A
-  %tmp2 = load i32* %B
+  %tmp1 = load i32, i32* %A
+  %tmp2 = load i32, i32* %B
   %tmp3 = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %tmp1, i32 %tmp2)
   ret i32 %tmp3
 }
@@ -223,8 +223,8 @@ declare i32 @llvm.aarch64.neon.sqrdmulh.i32(i32, i32) nounwind readnone
 define <2 x float> @fmulx_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: fmulx_2s:
 ;CHECK: fmulx.2s
-  %tmp1 = load <2 x float>* %A
-  %tmp2 = load <2 x float>* %B
+  %tmp1 = load <2 x float>, <2 x float>* %A
+  %tmp2 = load <2 x float>, <2 x float>* %B
   %tmp3 = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
   ret <2 x float> %tmp3
 }
@@ -232,8 +232,8 @@ define <2 x float> @fmulx_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x float> @fmulx_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: fmulx_4s:
 ;CHECK: fmulx.4s
-  %tmp1 = load <4 x float>* %A
-  %tmp2 = load <4 x float>* %B
+  %tmp1 = load <4 x float>, <4 x float>* %A
+  %tmp2 = load <4 x float>, <4 x float>* %B
   %tmp3 = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
   ret <4 x float> %tmp3
 }
@@ -241,8 +241,8 @@ define <4 x float> @fmulx_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x double> @fmulx_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
 ;CHECK-LABEL: fmulx_2d:
 ;CHECK: fmulx.2d
-  %tmp1 = load <2 x double>* %A
-  %tmp2 = load <2 x double>* %B
+  %tmp1 = load <2 x double>, <2 x double>* %A
+  %tmp2 = load <2 x double>, <2 x double>* %B
   %tmp3 = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
   ret <2 x double> %tmp3
 }
@@ -254,9 +254,9 @@ declare <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double>, <2 x double>)
 define <4 x i32> @smlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: smlal4s:
 ;CHECK: smlal.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp4 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
   %tmp5 = add <4 x i32> %tmp3, %tmp4
   ret <4 x i32> %tmp5
@@ -265,9 +265,9 @@ define <4 x i32> @smlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind
 define <2 x i64> @smlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
 ;CHECK-LABEL: smlal2d:
 ;CHECK: smlal.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp4 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
   %tmp5 = add <2 x i64> %tmp3, %tmp4
   ret <2 x i64> %tmp5
@@ -276,9 +276,9 @@ define <2 x i64> @smlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind
 define <4 x i32> @smlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: smlsl4s:
 ;CHECK: smlsl.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp4 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
   %tmp5 = sub <4 x i32> %tmp3, %tmp4
   ret <4 x i32> %tmp5
@@ -287,9 +287,9 @@ define <4 x i32> @smlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind
 define <2 x i64> @smlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
 ;CHECK-LABEL: smlsl2d:
 ;CHECK: smlsl.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp4 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
   %tmp5 = sub <2 x i64> %tmp3, %tmp4
   ret <2 x i64> %tmp5
@@ -303,9 +303,9 @@ declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)
 define <4 x i32> @sqdmlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: sqdmlal4s:
 ;CHECK: sqdmlal.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
   %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
   ret <4 x i32> %tmp5
@@ -314,9 +314,9 @@ define <4 x i32> @sqdmlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwin
 define <2 x i64> @sqdmlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
 ;CHECK-LABEL: sqdmlal2d:
 ;CHECK: sqdmlal.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
   %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
   ret <2 x i64> %tmp5
@@ -325,9 +325,9 @@ define <2 x i64> @sqdmlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwin
 define <4 x i32> @sqdmlal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: sqdmlal2_4s:
 ;CHECK: sqdmlal2.4s
-  %load1 = load <8 x i16>* %A
-  %load2 = load <8 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %load1 = load <8 x i16>, <8 x i16>* %A
+  %load2 = load <8 x i16>, <8 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -338,9 +338,9 @@ define <4 x i32> @sqdmlal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounw
 define <2 x i64> @sqdmlal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
 ;CHECK-LABEL: sqdmlal2_2d:
 ;CHECK: sqdmlal2.2d
-  %load1 = load <4 x i32>* %A
-  %load2 = load <4 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %load1 = load <4 x i32>, <4 x i32>* %A
+  %load2 = load <4 x i32>, <4 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -351,9 +351,9 @@ define <2 x i64> @sqdmlal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounw
 define <4 x i32> @sqdmlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: sqdmlsl4s:
 ;CHECK: sqdmlsl.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
   %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
   ret <4 x i32> %tmp5
@@ -362,9 +362,9 @@ define <4 x i32> @sqdmlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwin
 define <2 x i64> @sqdmlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
 ;CHECK-LABEL: sqdmlsl2d:
 ;CHECK: sqdmlsl.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
   %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
   ret <2 x i64> %tmp5
@@ -373,9 +373,9 @@ define <2 x i64> @sqdmlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwin
 define <4 x i32> @sqdmlsl2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: sqdmlsl2_4s:
 ;CHECK: sqdmlsl2.4s
-  %load1 = load <8 x i16>* %A
-  %load2 = load <8 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %load1 = load <8 x i16>, <8 x i16>* %A
+  %load2 = load <8 x i16>, <8 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -386,9 +386,9 @@ define <4 x i32> @sqdmlsl2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounw
 define <2 x i64> @sqdmlsl2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
 ;CHECK-LABEL: sqdmlsl2_2d:
 ;CHECK: sqdmlsl2.2d
-  %load1 = load <4 x i32>* %A
-  %load2 = load <4 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %load1 = load <4 x i32>, <4 x i32>* %A
+  %load2 = load <4 x i32>, <4 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -399,9 +399,9 @@ define <2 x i64> @sqdmlsl2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounw
 define <4 x i32> @umlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: umlal4s:
 ;CHECK: umlal.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp4 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
   %tmp5 = add <4 x i32> %tmp3, %tmp4
   ret <4 x i32> %tmp5
@@ -410,9 +410,9 @@ define <4 x i32> @umlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind
 define <2 x i64> @umlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
 ;CHECK-LABEL: umlal2d:
 ;CHECK: umlal.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp4 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
   %tmp5 = add <2 x i64> %tmp3, %tmp4
   ret <2 x i64> %tmp5
@@ -421,9 +421,9 @@ define <2 x i64> @umlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind
 define <4 x i32> @umlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: umlsl4s:
 ;CHECK: umlsl.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp4 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
   %tmp5 = sub <4 x i32> %tmp3, %tmp4
   ret <4 x i32> %tmp5
@@ -432,9 +432,9 @@ define <4 x i32> @umlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind
 define <2 x i64> @umlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
 ;CHECK-LABEL: umlsl2d:
 ;CHECK: umlsl.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp4 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
   %tmp5 = sub <2 x i64> %tmp3, %tmp4
   ret <2 x i64> %tmp5
@@ -443,9 +443,9 @@ define <2 x i64> @umlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind
 define <2 x float> @fmla_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
 ;CHECK-LABEL: fmla_2s:
 ;CHECK: fmla.2s
-  %tmp1 = load <2 x float>* %A
-  %tmp2 = load <2 x float>* %B
-  %tmp3 = load <2 x float>* %C
+  %tmp1 = load <2 x float>, <2 x float>* %A
+  %tmp2 = load <2 x float>, <2 x float>* %B
+  %tmp3 = load <2 x float>, <2 x float>* %C
   %tmp4 = call <2 x float> @llvm.fma.v2f32(<2 x float> %tmp1, <2 x float> %tmp2, <2 x float> %tmp3)
   ret <2 x float> %tmp4
 }
@@ -453,9 +453,9 @@ define <2 x float> @fmla_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n
 define <4 x float> @fmla_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
 ;CHECK-LABEL: fmla_4s:
 ;CHECK: fmla.4s
-  %tmp1 = load <4 x float>* %A
-  %tmp2 = load <4 x float>* %B
-  %tmp3 = load <4 x float>* %C
+  %tmp1 = load <4 x float>, <4 x float>* %A
+  %tmp2 = load <4 x float>, <4 x float>* %B
+  %tmp3 = load <4 x float>, <4 x float>* %C
   %tmp4 = call <4 x float> @llvm.fma.v4f32(<4 x float> %tmp1, <4 x float> %tmp2, <4 x float> %tmp3)
   ret <4 x float> %tmp4
 }
@@ -463,9 +463,9 @@ define <4 x float> @fmla_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) n
 define <2 x double> @fmla_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* %C) nounwind {
 ;CHECK-LABEL: fmla_2d:
 ;CHECK: fmla.2d
-  %tmp1 = load <2 x double>* %A
-  %tmp2 = load <2 x double>* %B
-  %tmp3 = load <2 x double>* %C
+  %tmp1 = load <2 x double>, <2 x double>* %A
+  %tmp2 = load <2 x double>, <2 x double>* %B
+  %tmp3 = load <2 x double>, <2 x double>* %C
   %tmp4 = call <2 x double> @llvm.fma.v2f64(<2 x double> %tmp1, <2 x double> %tmp2, <2 x double> %tmp3)
   ret <2 x double> %tmp4
 }
@@ -477,9 +477,9 @@ declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) n
 define <2 x float> @fmls_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
 ;CHECK-LABEL: fmls_2s:
 ;CHECK: fmls.2s
-  %tmp1 = load <2 x float>* %A
-  %tmp2 = load <2 x float>* %B
-  %tmp3 = load <2 x float>* %C
+  %tmp1 = load <2 x float>, <2 x float>* %A
+  %tmp2 = load <2 x float>, <2 x float>* %B
+  %tmp3 = load <2 x float>, <2 x float>* %C
   %tmp4 = fsub <2 x float> <float -0.0, float -0.0>, %tmp2
   %tmp5 = call <2 x float> @llvm.fma.v2f32(<2 x float> %tmp1, <2 x float> %tmp4, <2 x float> %tmp3)
   ret <2 x float> %tmp5
@@ -488,9 +488,9 @@ define <2 x float> @fmls_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n
 define <4 x float> @fmls_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
 ;CHECK-LABEL: fmls_4s:
 ;CHECK: fmls.4s
-  %tmp1 = load <4 x float>* %A
-  %tmp2 = load <4 x float>* %B
-  %tmp3 = load <4 x float>* %C
+  %tmp1 = load <4 x float>, <4 x float>* %A
+  %tmp2 = load <4 x float>, <4 x float>* %B
+  %tmp3 = load <4 x float>, <4 x float>* %C
   %tmp4 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %tmp2
   %tmp5 = call <4 x float> @llvm.fma.v4f32(<4 x float> %tmp1, <4 x float> %tmp4, <4 x float> %tmp3)
   ret <4 x float> %tmp5
@@ -499,9 +499,9 @@ define <4 x float> @fmls_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) n
 define <2 x double> @fmls_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* %C) nounwind {
 ;CHECK-LABEL: fmls_2d:
 ;CHECK: fmls.2d
-  %tmp1 = load <2 x double>* %A
-  %tmp2 = load <2 x double>* %B
-  %tmp3 = load <2 x double>* %C
+  %tmp1 = load <2 x double>, <2 x double>* %A
+  %tmp2 = load <2 x double>, <2 x double>* %B
+  %tmp3 = load <2 x double>, <2 x double>* %C
   %tmp4 = fsub <2 x double> <double -0.0, double -0.0>, %tmp2
   %tmp5 = call <2 x double> @llvm.fma.v2f64(<2 x double> %tmp1, <2 x double> %tmp4, <2 x double> %tmp3)
   ret <2 x double> %tmp5
@@ -510,9 +510,9 @@ define <2 x double> @fmls_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* %
 define <2 x float> @fmls_commuted_neg_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
 ;CHECK-LABEL: fmls_commuted_neg_2s:
 ;CHECK: fmls.2s
-  %tmp1 = load <2 x float>* %A
-  %tmp2 = load <2 x float>* %B
-  %tmp3 = load <2 x float>* %C
+  %tmp1 = load <2 x float>, <2 x float>* %A
+  %tmp2 = load <2 x float>, <2 x float>* %B
+  %tmp3 = load <2 x float>, <2 x float>* %C
   %tmp4 = fsub <2 x float> <float -0.0, float -0.0>, %tmp2
   %tmp5 = call <2 x float> @llvm.fma.v2f32(<2 x float> %tmp4, <2 x float> %tmp1, <2 x float> %tmp3)
   ret <2 x float> %tmp5
@@ -521,9 +521,9 @@ define <2 x float> @fmls_commuted_neg_2s(<2 x float>* %A, <2 x float>* %B, <2 x
 define <4 x float> @fmls_commuted_neg_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
 ;CHECK-LABEL: fmls_commuted_neg_4s:
 ;CHECK: fmls.4s
-  %tmp1 = load <4 x float>* %A
-  %tmp2 = load <4 x float>* %B
-  %tmp3 = load <4 x float>* %C
+  %tmp1 = load <4 x float>, <4 x float>* %A
+  %tmp2 = load <4 x float>, <4 x float>* %B
+  %tmp3 = load <4 x float>, <4 x float>* %C
   %tmp4 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %tmp2
   %tmp5 = call <4 x float> @llvm.fma.v4f32(<4 x float> %tmp4, <4 x float> %tmp1, <4 x float> %tmp3)
   ret <4 x float> %tmp5
@@ -532,9 +532,9 @@ define <4 x float> @fmls_commuted_neg_4s(<4 x float>* %A, <4 x float>* %B, <4 x
 define <2 x double> @fmls_commuted_neg_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* %C) nounwind {
 ;CHECK-LABEL: fmls_commuted_neg_2d:
 ;CHECK: fmls.2d
-  %tmp1 = load <2 x double>* %A
-  %tmp2 = load <2 x double>* %B
-  %tmp3 = load <2 x double>* %C
+  %tmp1 = load <2 x double>, <2 x double>* %A
+  %tmp2 = load <2 x double>, <2 x double>* %B
+  %tmp3 = load <2 x double>, <2 x double>* %C
   %tmp4 = fsub <2 x double> <double -0.0, double -0.0>, %tmp2
   %tmp5 = call <2 x double> @llvm.fma.v2f64(<2 x double> %tmp4, <2 x double> %tmp1, <2 x double> %tmp3)
   ret <2 x double> %tmp5
@@ -609,8 +609,8 @@ define <4 x i16> @mul_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: mul_4h:
 ;CHECK-NOT: dup
 ;CHECK: mul.4h
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp4 = mul <4 x i16> %tmp1, %tmp3
   ret <4 x i16> %tmp4
@@ -620,8 +620,8 @@ define <8 x i16> @mul_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: mul_8h:
 ;CHECK-NOT: dup
 ;CHECK: mul.8h
-  %tmp1 = load <8 x i16>* %A
-  %tmp2 = load <8 x i16>* %B
+  %tmp1 = load <8 x i16>, <8 x i16>* %A
+  %tmp2 = load <8 x i16>, <8 x i16>* %B
   %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
   %tmp4 = mul <8 x i16> %tmp1, %tmp3
   ret <8 x i16> %tmp4
@@ -631,8 +631,8 @@ define <2 x i32> @mul_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: mul_2s:
 ;CHECK-NOT: dup
 ;CHECK: mul.2s
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp4 = mul <2 x i32> %tmp1, %tmp3
   ret <2 x i32> %tmp4
@@ -642,8 +642,8 @@ define <4 x i32> @mul_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: mul_4s:
 ;CHECK-NOT: dup
 ;CHECK: mul.4s
-  %tmp1 = load <4 x i32>* %A
-  %tmp2 = load <4 x i32>* %B
+  %tmp1 = load <4 x i32>, <4 x i32>* %A
+  %tmp2 = load <4 x i32>, <4 x i32>* %B
   %tmp3 = shufflevector <4 x i32> %tmp2, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp4 = mul <4 x i32> %tmp1, %tmp3
   ret <4 x i32> %tmp4
@@ -661,8 +661,8 @@ define <2 x float> @fmul_lane_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: fmul_lane_2s:
 ;CHECK-NOT: dup
 ;CHECK: fmul.2s
-  %tmp1 = load <2 x float>* %A
-  %tmp2 = load <2 x float>* %B
+  %tmp1 = load <2 x float>, <2 x float>* %A
+  %tmp2 = load <2 x float>, <2 x float>* %B
   %tmp3 = shufflevector <2 x float> %tmp2, <2 x float> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp4 = fmul <2 x float> %tmp1, %tmp3
   ret <2 x float> %tmp4
@@ -672,8 +672,8 @@ define <4 x float> @fmul_lane_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: fmul_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: fmul.4s
-  %tmp1 = load <4 x float>* %A
-  %tmp2 = load <4 x float>* %B
+  %tmp1 = load <4 x float>, <4 x float>* %A
+  %tmp2 = load <4 x float>, <4 x float>* %B
   %tmp3 = shufflevector <4 x float> %tmp2, <4 x float> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp4 = fmul <4 x float> %tmp1, %tmp3
   ret <4 x float> %tmp4
@@ -683,8 +683,8 @@ define <2 x double> @fmul_lane_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
 ;CHECK-LABEL: fmul_lane_2d:
 ;CHECK-NOT: dup
 ;CHECK: fmul.2d
-  %tmp1 = load <2 x double>* %A
-  %tmp2 = load <2 x double>* %B
+  %tmp1 = load <2 x double>, <2 x double>* %A
+  %tmp2 = load <2 x double>, <2 x double>* %B
   %tmp3 = shufflevector <2 x double> %tmp2, <2 x double> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp4 = fmul <2 x double> %tmp1, %tmp3
   ret <2 x double> %tmp4
@@ -714,8 +714,8 @@ define <2 x float> @fmulx_lane_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: fmulx_lane_2s:
 ;CHECK-NOT: dup
 ;CHECK: fmulx.2s
-  %tmp1 = load <2 x float>* %A
-  %tmp2 = load <2 x float>* %B
+  %tmp1 = load <2 x float>, <2 x float>* %A
+  %tmp2 = load <2 x float>, <2 x float>* %B
   %tmp3 = shufflevector <2 x float> %tmp2, <2 x float> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp4 = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %tmp1, <2 x float> %tmp3)
   ret <2 x float> %tmp4
@@ -725,8 +725,8 @@ define <4 x float> @fmulx_lane_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: fmulx_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: fmulx.4s
-  %tmp1 = load <4 x float>* %A
-  %tmp2 = load <4 x float>* %B
+  %tmp1 = load <4 x float>, <4 x float>* %A
+  %tmp2 = load <4 x float>, <4 x float>* %B
   %tmp3 = shufflevector <4 x float> %tmp2, <4 x float> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp4 = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %tmp1, <4 x float> %tmp3)
   ret <4 x float> %tmp4
@@ -736,8 +736,8 @@ define <2 x double> @fmulx_lane_2d(<2 x double>* %A, <2 x double>* %B) nounwind
 ;CHECK-LABEL: fmulx_lane_2d:
 ;CHECK-NOT: dup
 ;CHECK: fmulx.2d
-  %tmp1 = load <2 x double>* %A
-  %tmp2 = load <2 x double>* %B
+  %tmp1 = load <2 x double>, <2 x double>* %A
+  %tmp2 = load <2 x double>, <2 x double>* %B
   %tmp3 = shufflevector <2 x double> %tmp2, <2 x double> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp4 = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %tmp1, <2 x double> %tmp3)
   ret <2 x double> %tmp4
@@ -747,8 +747,8 @@ define <4 x i16> @sqdmulh_lane_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqdmulh_lane_4h:
 ;CHECK-NOT: dup
 ;CHECK: sqdmulh.4h
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp4 = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp3)
   ret <4 x i16> %tmp4
@@ -758,8 +758,8 @@ define <8 x i16> @sqdmulh_lane_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqdmulh_lane_8h:
 ;CHECK-NOT: dup
 ;CHECK: sqdmulh.8h
-  %tmp1 = load <8 x i16>* %A
-  %tmp2 = load <8 x i16>* %B
+  %tmp1 = load <8 x i16>, <8 x i16>* %A
+  %tmp2 = load <8 x i16>, <8 x i16>* %B
   %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
   %tmp4 = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp3)
   ret <8 x i16> %tmp4
@@ -769,8 +769,8 @@ define <2 x i32> @sqdmulh_lane_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqdmulh_lane_2s:
 ;CHECK-NOT: dup
 ;CHECK: sqdmulh.2s
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp4 = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp3)
   ret <2 x i32> %tmp4
@@ -780,8 +780,8 @@ define <4 x i32> @sqdmulh_lane_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqdmulh_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: sqdmulh.4s
-  %tmp1 = load <4 x i32>* %A
-  %tmp2 = load <4 x i32>* %B
+  %tmp1 = load <4 x i32>, <4 x i32>* %A
+  %tmp2 = load <4 x i32>, <4 x i32>* %B
   %tmp3 = shufflevector <4 x i32> %tmp2, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp3)
   ret <4 x i32> %tmp4
@@ -800,8 +800,8 @@ define <4 x i16> @sqrdmulh_lane_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqrdmulh_lane_4h:
 ;CHECK-NOT: dup
 ;CHECK: sqrdmulh.4h
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp4 = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp3)
   ret <4 x i16> %tmp4
@@ -811,8 +811,8 @@ define <8 x i16> @sqrdmulh_lane_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqrdmulh_lane_8h:
 ;CHECK-NOT: dup
 ;CHECK: sqrdmulh.8h
-  %tmp1 = load <8 x i16>* %A
-  %tmp2 = load <8 x i16>* %B
+  %tmp1 = load <8 x i16>, <8 x i16>* %A
+  %tmp2 = load <8 x i16>, <8 x i16>* %B
   %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
   %tmp4 = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp3)
   ret <8 x i16> %tmp4
@@ -822,8 +822,8 @@ define <2 x i32> @sqrdmulh_lane_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqrdmulh_lane_2s:
 ;CHECK-NOT: dup
 ;CHECK: sqrdmulh.2s
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp4 = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp3)
   ret <2 x i32> %tmp4
@@ -833,8 +833,8 @@ define <4 x i32> @sqrdmulh_lane_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqrdmulh_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: sqrdmulh.4s
-  %tmp1 = load <4 x i32>* %A
-  %tmp2 = load <4 x i32>* %B
+  %tmp1 = load <4 x i32>, <4 x i32>* %A
+  %tmp2 = load <4 x i32>, <4 x i32>* %B
   %tmp3 = shufflevector <4 x i32> %tmp2, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp3)
   ret <4 x i32> %tmp4
@@ -853,8 +853,8 @@ define <4 x i32> @sqdmull_lane_4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqdmull_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: sqdmull.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3)
   ret <4 x i32> %tmp4
@@ -864,8 +864,8 @@ define <2 x i64> @sqdmull_lane_2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqdmull_lane_2d:
 ;CHECK-NOT: dup
 ;CHECK: sqdmull.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3)
   ret <2 x i64> %tmp4
@@ -875,8 +875,8 @@ define <4 x i32> @sqdmull2_lane_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqdmull2_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: sqdmull2.4s
-  %load1 = load <8 x i16>* %A
-  %load2 = load <8 x i16>* %B
+  %load1 = load <8 x i16>, <8 x i16>* %A
+  %load2 = load <8 x i16>, <8 x i16>* %B
   %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -887,8 +887,8 @@ define <2 x i64> @sqdmull2_lane_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqdmull2_lane_2d:
 ;CHECK-NOT: dup
 ;CHECK: sqdmull2.2d
-  %load1 = load <4 x i32>* %A
-  %load2 = load <4 x i32>* %B
+  %load1 = load <4 x i32>, <4 x i32>* %A
+  %load2 = load <4 x i32>, <4 x i32>* %B
   %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
   %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -899,8 +899,8 @@ define <4 x i32> @umull_lane_4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: umull_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: umull.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp4 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3)
   ret <4 x i32> %tmp4
@@ -910,8 +910,8 @@ define <2 x i64> @umull_lane_2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: umull_lane_2d:
 ;CHECK-NOT: dup
 ;CHECK: umull.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp4 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3)
   ret <2 x i64> %tmp4
@@ -921,8 +921,8 @@ define <4 x i32> @smull_lane_4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: smull_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: smull.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp4 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3)
   ret <4 x i32> %tmp4
@@ -932,8 +932,8 @@ define <2 x i64> @smull_lane_2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: smull_lane_2d:
 ;CHECK-NOT: dup
 ;CHECK: smull.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp4 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3)
   ret <2 x i64> %tmp4
@@ -943,9 +943,9 @@ define <4 x i32> @smlal_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nou
 ;CHECK-LABEL: smlal_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: smlal.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp5 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
   %tmp6 = add <4 x i32> %tmp3, %tmp5
@@ -956,9 +956,9 @@ define <2 x i64> @smlal_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nou
 ;CHECK-LABEL: smlal_lane_2d:
 ;CHECK-NOT: dup
 ;CHECK: smlal.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp5 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
   %tmp6 = add <2 x i64> %tmp3, %tmp5
@@ -969,9 +969,9 @@ define <4 x i32> @sqdmlal_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) n
 ;CHECK-LABEL: sqdmlal_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: sqdmlal.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
   %tmp6 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5)
@@ -982,9 +982,9 @@ define <2 x i64> @sqdmlal_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) n
 ;CHECK-LABEL: sqdmlal_lane_2d:
 ;CHECK-NOT: dup
 ;CHECK: sqdmlal.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
   %tmp6 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5)
@@ -995,9 +995,9 @@ define <4 x i32> @sqdmlal2_lane_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C)
 ;CHECK-LABEL: sqdmlal2_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: sqdmlal2.4s
-  %load1 = load <8 x i16>* %A
-  %load2 = load <8 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %load1 = load <8 x i16>, <8 x i16>* %A
+  %load2 = load <8 x i16>, <8 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -1009,9 +1009,9 @@ define <2 x i64> @sqdmlal2_lane_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C)
 ;CHECK-LABEL: sqdmlal2_lane_2d:
 ;CHECK-NOT: dup
 ;CHECK: sqdmlal2.2d
-  %load1 = load <4 x i32>* %A
-  %load2 = load <4 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %load1 = load <4 x i32>, <4 x i32>* %A
+  %load2 = load <4 x i32>, <4 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
   %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -1069,9 +1069,9 @@ define <4 x i32> @umlal_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nou
 ;CHECK-LABEL: umlal_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: umlal.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp5 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
   %tmp6 = add <4 x i32> %tmp3, %tmp5
@@ -1082,9 +1082,9 @@ define <2 x i64> @umlal_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nou
 ;CHECK-LABEL: umlal_lane_2d:
 ;CHECK-NOT: dup
 ;CHECK: umlal.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp5 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
   %tmp6 = add <2 x i64> %tmp3, %tmp5
@@ -1096,9 +1096,9 @@ define <4 x i32> @smlsl_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nou
 ;CHECK-LABEL: smlsl_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: smlsl.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp5 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
   %tmp6 = sub <4 x i32> %tmp3, %tmp5
@@ -1109,9 +1109,9 @@ define <2 x i64> @smlsl_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nou
 ;CHECK-LABEL: smlsl_lane_2d:
 ;CHECK-NOT: dup
 ;CHECK: smlsl.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp5 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
   %tmp6 = sub <2 x i64> %tmp3, %tmp5
@@ -1122,9 +1122,9 @@ define <4 x i32> @sqdmlsl_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) n
 ;CHECK-LABEL: sqdmlsl_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: sqdmlsl.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
   %tmp6 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5)
@@ -1135,9 +1135,9 @@ define <2 x i64> @sqdmlsl_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) n
 ;CHECK-LABEL: sqdmlsl_lane_2d:
 ;CHECK-NOT: dup
 ;CHECK: sqdmlsl.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
   %tmp6 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5)
@@ -1148,9 +1148,9 @@ define <4 x i32> @sqdmlsl2_lane_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C)
 ;CHECK-LABEL: sqdmlsl2_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: sqdmlsl2.4s
-  %load1 = load <8 x i16>* %A
-  %load2 = load <8 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %load1 = load <8 x i16>, <8 x i16>* %A
+  %load2 = load <8 x i16>, <8 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -1162,9 +1162,9 @@ define <2 x i64> @sqdmlsl2_lane_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C)
 ;CHECK-LABEL: sqdmlsl2_lane_2d:
 ;CHECK-NOT: dup
 ;CHECK: sqdmlsl2.2d
-  %load1 = load <4 x i32>* %A
-  %load2 = load <4 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %load1 = load <4 x i32>, <4 x i32>* %A
+  %load2 = load <4 x i32>, <4 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
   %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -1176,9 +1176,9 @@ define <4 x i32> @umlsl_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nou
 ;CHECK-LABEL: umlsl_lane_4s:
 ;CHECK-NOT: dup
 ;CHECK: umlsl.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
-  %tmp3 = load <4 x i32>* %C
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %tmp5 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
   %tmp6 = sub <4 x i32> %tmp3, %tmp5
@@ -1189,9 +1189,9 @@ define <2 x i64> @umlsl_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nou
 ;CHECK-LABEL: umlsl_lane_2d:
 ;CHECK-NOT: dup
 ;CHECK: umlsl.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
-  %tmp3 = load <2 x i64>* %C
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
   %tmp5 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
   %tmp6 = sub <2 x i64> %tmp3, %tmp5
diff --git a/test/CodeGen/AArch64/arm64-volatile.ll b/test/CodeGen/AArch64/arm64-volatile.ll
index e00ac5acb5fb..28facb6da7c6 100644
--- a/test/CodeGen/AArch64/arm64-volatile.ll
+++ b/test/CodeGen/AArch64/arm64-volatile.ll
@@ -4,10 +4,10 @@ define i64 @normal_load(i64* nocapture %bar) nounwind readonly {
 ; CHECK: ldp
 ; CHECK-NEXT: add
 ; CHECK-NEXT: ret
-  %add.ptr = getelementptr inbounds i64* %bar, i64 1
-  %tmp = load i64* %add.ptr, align 8
-  %add.ptr1 = getelementptr inbounds i64* %bar, i64 2
-  %tmp1 = load i64* %add.ptr1, align 8
+  %add.ptr = getelementptr inbounds i64, i64* %bar, i64 1
+  %tmp = load i64, i64* %add.ptr, align 8
+  %add.ptr1 = getelementptr inbounds i64, i64* %bar, i64 2
+  %tmp1 = load i64, i64* %add.ptr1, align 8
   %add = add nsw i64 %tmp1, %tmp
   ret i64 %add
 }
@@ -18,10 +18,10 @@ define i64 @volatile_load(i64* nocapture %bar) nounwind {
 ; CHECK-NEXT: ldr
 ; CHECK-NEXT: add
 ; CHECK-NEXT: ret
-  %add.ptr = getelementptr inbounds i64* %bar, i64 1
-  %tmp = load volatile i64* %add.ptr, align 8
-  %add.ptr1 = getelementptr inbounds i64* %bar, i64 2
-  %tmp1 = load volatile i64* %add.ptr1, align 8
+  %add.ptr = getelementptr inbounds i64, i64* %bar, i64 1
+  %tmp = load volatile i64, i64* %add.ptr, align 8
+  %add.ptr1 = getelementptr inbounds i64, i64* %bar, i64 2
+  %tmp1 = load volatile i64, i64* %add.ptr1, align 8
   %add = add nsw i64 %tmp1, %tmp
   ret i64 %add
 }
diff --git a/test/CodeGen/AArch64/arm64-vqadd.ll b/test/CodeGen/AArch64/arm64-vqadd.ll
index 20f7e2c7a893..9932899c6424 100644
--- a/test/CodeGen/AArch64/arm64-vqadd.ll
+++ b/test/CodeGen/AArch64/arm64-vqadd.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @sqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: sqadd8b:
 ;CHECK: sqadd.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @sqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @sqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqadd4h:
 ;CHECK: sqadd.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @sqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @sqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqadd2s:
 ;CHECK: sqadd.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @sqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @uqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: uqadd8b:
 ;CHECK: uqadd.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.uqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -39,8 +39,8 @@ define <8 x i8> @uqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @uqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: uqadd4h:
 ;CHECK: uqadd.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.uqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -48,8 +48,8 @@ define <4 x i16> @uqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @uqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: uqadd2s:
 ;CHECK: uqadd.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.uqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -57,8 +57,8 @@ define <2 x i32> @uqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @sqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: sqadd16b:
 ;CHECK: sqadd.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -66,8 +66,8 @@ define <16 x i8> @sqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @sqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqadd8h:
 ;CHECK: sqadd.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -75,8 +75,8 @@ define <8 x i16> @sqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @sqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqadd4s:
 ;CHECK: sqadd.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -84,8 +84,8 @@ define <4 x i32> @sqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @sqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: sqadd2d:
 ;CHECK: sqadd.2d
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -93,8 +93,8 @@ define <2 x i64> @sqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @uqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: uqadd16b:
 ;CHECK: uqadd.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.uqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -102,8 +102,8 @@ define <16 x i8> @uqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @uqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: uqadd8h:
 ;CHECK: uqadd.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.uqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -111,8 +111,8 @@ define <8 x i16> @uqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @uqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: uqadd4s:
 ;CHECK: uqadd.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.uqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -120,8 +120,8 @@ define <4 x i32> @uqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @uqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: uqadd2d:
 ;CHECK: uqadd.2d
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.aarch64.neon.uqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -149,8 +149,8 @@ declare <2 x i64> @llvm.aarch64.neon.uqadd.v2i64(<2 x i64>, <2 x i64>) nounwind
 define <8 x i8> @usqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: usqadd8b:
 ;CHECK: usqadd.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -158,8 +158,8 @@ define <8 x i8> @usqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @usqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: usqadd4h:
 ;CHECK: usqadd.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -167,8 +167,8 @@ define <4 x i16> @usqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @usqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: usqadd2s:
 ;CHECK: usqadd.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.usqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -176,8 +176,8 @@ define <2 x i32> @usqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @usqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: usqadd16b:
 ;CHECK: usqadd.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.usqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -185,8 +185,8 @@ define <16 x i8> @usqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @usqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: usqadd8h:
 ;CHECK: usqadd.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.usqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -194,8 +194,8 @@ define <8 x i16> @usqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @usqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: usqadd4s:
 ;CHECK: usqadd.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.usqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -203,8 +203,8 @@ define <4 x i32> @usqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @usqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: usqadd2d:
 ;CHECK: usqadd.2d
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.aarch64.neon.usqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -238,8 +238,8 @@ declare <2 x i64> @llvm.aarch64.neon.usqadd.v2i64(<2 x i64>, <2 x i64>) nounwind
 define <8 x i8> @suqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: suqadd8b:
 ;CHECK: suqadd.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -247,8 +247,8 @@ define <8 x i8> @suqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @suqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: suqadd4h:
 ;CHECK: suqadd.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -256,8 +256,8 @@ define <4 x i16> @suqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @suqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: suqadd2s:
 ;CHECK: suqadd.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.suqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -265,8 +265,8 @@ define <2 x i32> @suqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @suqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: suqadd16b:
 ;CHECK: suqadd.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.suqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -274,8 +274,8 @@ define <16 x i8> @suqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @suqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: suqadd8h:
 ;CHECK: suqadd.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.suqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -283,8 +283,8 @@ define <8 x i16> @suqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @suqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: suqadd4s:
 ;CHECK: suqadd.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.suqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -292,8 +292,8 @@ define <4 x i32> @suqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @suqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: suqadd2d:
 ;CHECK: suqadd.2d
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.aarch64.neon.suqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
diff --git a/test/CodeGen/AArch64/arm64-vqsub.ll b/test/CodeGen/AArch64/arm64-vqsub.ll
index dde3ac3478e4..4fc588d689f9 100644
--- a/test/CodeGen/AArch64/arm64-vqsub.ll
+++ b/test/CodeGen/AArch64/arm64-vqsub.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @sqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: sqsub8b:
 ;CHECK: sqsub.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @sqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @sqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqsub4h:
 ;CHECK: sqsub.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @sqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @sqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqsub2s:
 ;CHECK: sqsub.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @sqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @uqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: uqsub8b:
 ;CHECK: uqsub.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.aarch64.neon.uqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -39,8 +39,8 @@ define <8 x i8> @uqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @uqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: uqsub4h:
 ;CHECK: uqsub.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -48,8 +48,8 @@ define <4 x i16> @uqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @uqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: uqsub2s:
 ;CHECK: uqsub.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.uqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -57,8 +57,8 @@ define <2 x i32> @uqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @sqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: sqsub16b:
 ;CHECK: sqsub.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.sqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -66,8 +66,8 @@ define <16 x i8> @sqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @sqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqsub8h:
 ;CHECK: sqsub.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -75,8 +75,8 @@ define <8 x i16> @sqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @sqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqsub4s:
 ;CHECK: sqsub.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -84,8 +84,8 @@ define <4 x i32> @sqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @sqsub2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: sqsub2d:
 ;CHECK: sqsub.2d
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -93,8 +93,8 @@ define <2 x i64> @sqsub2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @uqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: uqsub16b:
 ;CHECK: uqsub.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.aarch64.neon.uqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -102,8 +102,8 @@ define <16 x i8> @uqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @uqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: uqsub8h:
 ;CHECK: uqsub.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.aarch64.neon.uqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -111,8 +111,8 @@ define <8 x i16> @uqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @uqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: uqsub4s:
 ;CHECK: uqsub.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.uqsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -120,8 +120,8 @@ define <4 x i32> @uqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @uqsub2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: uqsub2d:
 ;CHECK: uqsub.2d
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.aarch64.neon.uqsub.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
diff --git a/test/CodeGen/AArch64/arm64-vshift.ll b/test/CodeGen/AArch64/arm64-vshift.ll
index 65bd50cbe9d0..d5a12483db40 100644
--- a/test/CodeGen/AArch64/arm64-vshift.ll
+++ b/test/CodeGen/AArch64/arm64-vshift.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @sqshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: sqshl8b:
 ;CHECK: sqshl.8b
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
         ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @sqshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @sqshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqshl4h:
 ;CHECK: sqshl.4h
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
         ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @sqshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @sqshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqshl2s:
 ;CHECK: sqshl.2s
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
         ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @sqshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @uqshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: uqshl8b:
 ;CHECK: uqshl.8b
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
         ret <8 x i8> %tmp3
 }
@@ -39,8 +39,8 @@ define <8 x i8> @uqshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @uqshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: uqshl4h:
 ;CHECK: uqshl.4h
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
         ret <4 x i16> %tmp3
 }
@@ -48,8 +48,8 @@ define <4 x i16> @uqshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @uqshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: uqshl2s:
 ;CHECK: uqshl.2s
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
         ret <2 x i32> %tmp3
 }
@@ -57,8 +57,8 @@ define <2 x i32> @uqshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @sqshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: sqshl16b:
 ;CHECK: sqshl.16b
-        %tmp1 = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
         ret <16 x i8> %tmp3
 }
@@ -66,8 +66,8 @@ define <16 x i8> @sqshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @sqshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqshl8h:
 ;CHECK: sqshl.8h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
         ret <8 x i16> %tmp3
 }
@@ -75,8 +75,8 @@ define <8 x i16> @sqshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @sqshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqshl4s:
 ;CHECK: sqshl.4s
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
         ret <4 x i32> %tmp3
 }
@@ -84,8 +84,8 @@ define <4 x i32> @sqshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @sqshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: sqshl2d:
 ;CHECK: sqshl.2d
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
         ret <2 x i64> %tmp3
 }
@@ -93,8 +93,8 @@ define <2 x i64> @sqshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @uqshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: uqshl16b:
 ;CHECK: uqshl.16b
-        %tmp1 = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
         ret <16 x i8> %tmp3
 }
@@ -102,8 +102,8 @@ define <16 x i8> @uqshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @uqshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: uqshl8h:
 ;CHECK: uqshl.8h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
         ret <8 x i16> %tmp3
 }
@@ -111,8 +111,8 @@ define <8 x i16> @uqshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @uqshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: uqshl4s:
 ;CHECK: uqshl.4s
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
         ret <4 x i32> %tmp3
 }
@@ -120,8 +120,8 @@ define <4 x i32> @uqshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @uqshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: uqshl2d:
 ;CHECK: uqshl.2d
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
         ret <2 x i64> %tmp3
 }
@@ -149,8 +149,8 @@ declare <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64>, <2 x i64>) nounwind
 define <8 x i8> @srshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: srshl8b:
 ;CHECK: srshl.8b
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
         ret <8 x i8> %tmp3
 }
@@ -158,8 +158,8 @@ define <8 x i8> @srshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @srshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: srshl4h:
 ;CHECK: srshl.4h
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
         ret <4 x i16> %tmp3
 }
@@ -167,8 +167,8 @@ define <4 x i16> @srshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @srshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: srshl2s:
 ;CHECK: srshl.2s
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
         ret <2 x i32> %tmp3
 }
@@ -176,8 +176,8 @@ define <2 x i32> @srshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @urshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: urshl8b:
 ;CHECK: urshl.8b
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
         ret <8 x i8> %tmp3
 }
@@ -185,8 +185,8 @@ define <8 x i8> @urshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @urshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: urshl4h:
 ;CHECK: urshl.4h
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
         ret <4 x i16> %tmp3
 }
@@ -194,8 +194,8 @@ define <4 x i16> @urshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @urshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: urshl2s:
 ;CHECK: urshl.2s
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
         ret <2 x i32> %tmp3
 }
@@ -203,8 +203,8 @@ define <2 x i32> @urshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @srshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: srshl16b:
 ;CHECK: srshl.16b
-        %tmp1 = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
         ret <16 x i8> %tmp3
 }
@@ -212,8 +212,8 @@ define <16 x i8> @srshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @srshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: srshl8h:
 ;CHECK: srshl.8h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
         ret <8 x i16> %tmp3
 }
@@ -221,8 +221,8 @@ define <8 x i16> @srshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @srshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: srshl4s:
 ;CHECK: srshl.4s
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
         ret <4 x i32> %tmp3
 }
@@ -230,8 +230,8 @@ define <4 x i32> @srshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @srshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: srshl2d:
 ;CHECK: srshl.2d
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
         ret <2 x i64> %tmp3
 }
@@ -239,8 +239,8 @@ define <2 x i64> @srshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @urshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: urshl16b:
 ;CHECK: urshl.16b
-        %tmp1 = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
         ret <16 x i8> %tmp3
 }
@@ -248,8 +248,8 @@ define <16 x i8> @urshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @urshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: urshl8h:
 ;CHECK: urshl.8h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
         ret <8 x i16> %tmp3
 }
@@ -257,8 +257,8 @@ define <8 x i16> @urshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @urshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: urshl4s:
 ;CHECK: urshl.4s
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
         ret <4 x i32> %tmp3
 }
@@ -266,8 +266,8 @@ define <4 x i32> @urshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @urshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: urshl2d:
 ;CHECK: urshl.2d
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
         ret <2 x i64> %tmp3
 }
@@ -295,8 +295,8 @@ declare <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64>, <2 x i64>) nounwind
 define <8 x i8> @sqrshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: sqrshl8b:
 ;CHECK: sqrshl.8b
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
         ret <8 x i8> %tmp3
 }
@@ -304,8 +304,8 @@ define <8 x i8> @sqrshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @sqrshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqrshl4h:
 ;CHECK: sqrshl.4h
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
         ret <4 x i16> %tmp3
 }
@@ -313,8 +313,8 @@ define <4 x i16> @sqrshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @sqrshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqrshl2s:
 ;CHECK: sqrshl.2s
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
         ret <2 x i32> %tmp3
 }
@@ -322,8 +322,8 @@ define <2 x i32> @sqrshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @uqrshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: uqrshl8b:
 ;CHECK: uqrshl.8b
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
         ret <8 x i8> %tmp3
 }
@@ -331,8 +331,8 @@ define <8 x i8> @uqrshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @uqrshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: uqrshl4h:
 ;CHECK: uqrshl.4h
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
         ret <4 x i16> %tmp3
 }
@@ -340,8 +340,8 @@ define <4 x i16> @uqrshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @uqrshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: uqrshl2s:
 ;CHECK: uqrshl.2s
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
         ret <2 x i32> %tmp3
 }
@@ -349,8 +349,8 @@ define <2 x i32> @uqrshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @sqrshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: sqrshl16b:
 ;CHECK: sqrshl.16b
-        %tmp1 = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqrshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
         ret <16 x i8> %tmp3
 }
@@ -358,8 +358,8 @@ define <16 x i8> @sqrshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @sqrshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqrshl8h:
 ;CHECK: sqrshl.8h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqrshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
         ret <8 x i16> %tmp3
 }
@@ -367,8 +367,8 @@ define <8 x i16> @sqrshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @sqrshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqrshl4s:
 ;CHECK: sqrshl.4s
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqrshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
         ret <4 x i32> %tmp3
 }
@@ -376,8 +376,8 @@ define <4 x i32> @sqrshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @sqrshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: sqrshl2d:
 ;CHECK: sqrshl.2d
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqrshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
         ret <2 x i64> %tmp3
 }
@@ -385,8 +385,8 @@ define <2 x i64> @sqrshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @uqrshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: uqrshl16b:
 ;CHECK: uqrshl.16b
-        %tmp1 = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqrshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
         ret <16 x i8> %tmp3
 }
@@ -394,8 +394,8 @@ define <16 x i8> @uqrshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @uqrshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: uqrshl8h:
 ;CHECK: uqrshl.8h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqrshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
         ret <8 x i16> %tmp3
 }
@@ -403,8 +403,8 @@ define <8 x i16> @uqrshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @uqrshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: uqrshl4s:
 ;CHECK: uqrshl.4s
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqrshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
         ret <4 x i32> %tmp3
 }
@@ -412,8 +412,8 @@ define <4 x i32> @uqrshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @uqrshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: uqrshl2d:
 ;CHECK: uqrshl.2d
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqrshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
         ret <2 x i64> %tmp3
 }
@@ -441,7 +441,7 @@ declare <2 x i64> @llvm.aarch64.neon.uqrshl.v2i64(<2 x i64>, <2 x i64>) nounwind
 define <8 x i8> @urshr8b(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: urshr8b:
 ;CHECK: urshr.8b
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
         ret <8 x i8> %tmp3
 }
@@ -449,7 +449,7 @@ define <8 x i8> @urshr8b(<8 x i8>* %A) nounwind {
 define <4 x i16> @urshr4h(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: urshr4h:
 ;CHECK: urshr.4h
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
         ret <4 x i16> %tmp3
 }
@@ -457,7 +457,7 @@ define <4 x i16> @urshr4h(<4 x i16>* %A) nounwind {
 define <2 x i32> @urshr2s(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: urshr2s:
 ;CHECK: urshr.2s
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
         ret <2 x i32> %tmp3
 }
@@ -465,7 +465,7 @@ define <2 x i32> @urshr2s(<2 x i32>* %A) nounwind {
 define <16 x i8> @urshr16b(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: urshr16b:
 ;CHECK: urshr.16b
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
         ret <16 x i8> %tmp3
 }
@@ -473,7 +473,7 @@ define <16 x i8> @urshr16b(<16 x i8>* %A) nounwind {
 define <8 x i16> @urshr8h(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: urshr8h:
 ;CHECK: urshr.8h
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
         ret <8 x i16> %tmp3
 }
@@ -481,7 +481,7 @@ define <8 x i16> @urshr8h(<8 x i16>* %A) nounwind {
 define <4 x i32> @urshr4s(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: urshr4s:
 ;CHECK: urshr.4s
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
         ret <4 x i32> %tmp3
 }
@@ -489,7 +489,7 @@ define <4 x i32> @urshr4s(<4 x i32>* %A) nounwind {
 define <2 x i64> @urshr2d(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: urshr2d:
 ;CHECK: urshr.2d
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
         ret <2 x i64> %tmp3
 }
@@ -497,7 +497,7 @@ define <2 x i64> @urshr2d(<2 x i64>* %A) nounwind {
 define <8 x i8> @srshr8b(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: srshr8b:
 ;CHECK: srshr.8b
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
         ret <8 x i8> %tmp3
 }
@@ -505,7 +505,7 @@ define <8 x i8> @srshr8b(<8 x i8>* %A) nounwind {
 define <4 x i16> @srshr4h(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: srshr4h:
 ;CHECK: srshr.4h
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
         ret <4 x i16> %tmp3
 }
@@ -513,7 +513,7 @@ define <4 x i16> @srshr4h(<4 x i16>* %A) nounwind {
 define <2 x i32> @srshr2s(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: srshr2s:
 ;CHECK: srshr.2s
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
         ret <2 x i32> %tmp3
 }
@@ -521,7 +521,7 @@ define <2 x i32> @srshr2s(<2 x i32>* %A) nounwind {
 define <16 x i8> @srshr16b(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: srshr16b:
 ;CHECK: srshr.16b
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
         ret <16 x i8> %tmp3
 }
@@ -529,7 +529,7 @@ define <16 x i8> @srshr16b(<16 x i8>* %A) nounwind {
 define <8 x i16> @srshr8h(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: srshr8h:
 ;CHECK: srshr.8h
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
         ret <8 x i16> %tmp3
 }
@@ -537,7 +537,7 @@ define <8 x i16> @srshr8h(<8 x i16>* %A) nounwind {
 define <4 x i32> @srshr4s(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: srshr4s:
 ;CHECK: srshr.4s
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
         ret <4 x i32> %tmp3
 }
@@ -545,7 +545,7 @@ define <4 x i32> @srshr4s(<4 x i32>* %A) nounwind {
 define <2 x i64> @srshr2d(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: srshr2d:
 ;CHECK: srshr.2d
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
         ret <2 x i64> %tmp3
 }
@@ -553,7 +553,7 @@ define <2 x i64> @srshr2d(<2 x i64>* %A) nounwind {
 define <8 x i8> @sqshlu8b(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: sqshlu8b:
 ;CHECK: sqshlu.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
         ret <8 x i8> %tmp3
 }
@@ -561,7 +561,7 @@ define <8 x i8> @sqshlu8b(<8 x i8>* %A) nounwind {
 define <4 x i16> @sqshlu4h(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqshlu4h:
 ;CHECK: sqshlu.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
         ret <4 x i16> %tmp3
 }
@@ -569,7 +569,7 @@ define <4 x i16> @sqshlu4h(<4 x i16>* %A) nounwind {
 define <2 x i32> @sqshlu2s(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqshlu2s:
 ;CHECK: sqshlu.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)
         ret <2 x i32> %tmp3
 }
@@ -577,7 +577,7 @@ define <2 x i32> @sqshlu2s(<2 x i32>* %A) nounwind {
 define <16 x i8> @sqshlu16b(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: sqshlu16b:
 ;CHECK: sqshlu.16b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
         ret <16 x i8> %tmp3
 }
@@ -585,7 +585,7 @@ define <16 x i8> @sqshlu16b(<16 x i8>* %A) nounwind {
 define <8 x i16> @sqshlu8h(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqshlu8h:
 ;CHECK: sqshlu.8h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
         ret <8 x i16> %tmp3
 }
@@ -593,7 +593,7 @@ define <8 x i16> @sqshlu8h(<8 x i16>* %A) nounwind {
 define <4 x i32> @sqshlu4s(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqshlu4s:
 ;CHECK: sqshlu.4s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
         ret <4 x i32> %tmp3
 }
@@ -601,7 +601,7 @@ define <4 x i32> @sqshlu4s(<4 x i32>* %A) nounwind {
 define <2 x i64> @sqshlu2d(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: sqshlu2d:
 ;CHECK: sqshlu.2d v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)
         ret <2 x i64> %tmp3
 }
@@ -619,7 +619,7 @@ declare <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64>, <2 x i64>) nounwind
 define <8 x i8> @rshrn8b(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: rshrn8b:
 ;CHECK: rshrn.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %tmp1, i32 1)
         ret <8 x i8> %tmp3
 }
@@ -627,7 +627,7 @@ define <8 x i8> @rshrn8b(<8 x i16>* %A) nounwind {
 define <4 x i16> @rshrn4h(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: rshrn4h:
 ;CHECK: rshrn.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %tmp1, i32 1)
         ret <4 x i16> %tmp3
 }
@@ -635,7 +635,7 @@ define <4 x i16> @rshrn4h(<4 x i32>* %A) nounwind {
 define <2 x i32> @rshrn2s(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: rshrn2s:
 ;CHECK: rshrn.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %tmp1, i32 1)
         ret <2 x i32> %tmp3
 }
@@ -643,8 +643,8 @@ define <2 x i32> @rshrn2s(<2 x i64>* %A) nounwind {
 define <16 x i8> @rshrn16b(<8 x i8> *%ret, <8 x i16>* %A) nounwind {
 ;CHECK-LABEL: rshrn16b:
 ;CHECK: rshrn2.16b v0, {{v[0-9]+}}, #1
-        %out = load <8 x i8>* %ret
-        %tmp1 = load <8 x i16>* %A
+        %out = load <8 x i8>, <8 x i8>* %ret
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %tmp1, i32 1)
         %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         ret <16 x i8> %tmp4
@@ -653,8 +653,8 @@ define <16 x i8> @rshrn16b(<8 x i8> *%ret, <8 x i16>* %A) nounwind {
 define <8 x i16> @rshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 ;CHECK-LABEL: rshrn8h:
 ;CHECK: rshrn2.8h v0, {{v[0-9]+}}, #1
-        %out = load <4 x i16>* %ret
-        %tmp1 = load <4 x i32>* %A
+        %out = load <4 x i16>, <4 x i16>* %ret
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %tmp1, i32 1)
         %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
         ret <8 x i16> %tmp4
@@ -663,8 +663,8 @@ define <8 x i16> @rshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 define <4 x i32> @rshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
 ;CHECK-LABEL: rshrn4s:
 ;CHECK: rshrn2.4s v0, {{v[0-9]+}}, #1
-        %out = load <2 x i32>* %ret
-        %tmp1 = load <2 x i64>* %A
+        %out = load <2 x i32>, <2 x i32>* %ret
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %tmp1, i32 1)
         %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
         ret <4 x i32> %tmp4
@@ -677,7 +677,7 @@ declare <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64>, i32) nounwind readno
 define <8 x i8> @shrn8b(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: shrn8b:
 ;CHECK: shrn.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp2 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
         %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>
         ret <8 x i8> %tmp3
@@ -686,7 +686,7 @@ define <8 x i8> @shrn8b(<8 x i16>* %A) nounwind {
 define <4 x i16> @shrn4h(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: shrn4h:
 ;CHECK: shrn.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp2 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
         %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>
         ret <4 x i16> %tmp3
@@ -695,7 +695,7 @@ define <4 x i16> @shrn4h(<4 x i32>* %A) nounwind {
 define <2 x i32> @shrn2s(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: shrn2s:
 ;CHECK: shrn.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp2 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
         %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>
         ret <2 x i32> %tmp3
@@ -704,8 +704,8 @@ define <2 x i32> @shrn2s(<2 x i64>* %A) nounwind {
 define <16 x i8> @shrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
 ;CHECK-LABEL: shrn16b:
 ;CHECK: shrn2.16b v0, {{v[0-9]+}}, #1
-        %out = load <8 x i8>* %ret
-        %tmp1 = load <8 x i16>* %A
+        %out = load <8 x i8>, <8 x i8>* %ret
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp2 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
         %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>
         %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -715,8 +715,8 @@ define <16 x i8> @shrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
 define <8 x i16> @shrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 ;CHECK-LABEL: shrn8h:
 ;CHECK: shrn2.8h v0, {{v[0-9]+}}, #1
-        %out = load <4 x i16>* %ret
-        %tmp1 = load <4 x i32>* %A
+        %out = load <4 x i16>, <4 x i16>* %ret
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp2 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
         %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>
         %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -726,8 +726,8 @@ define <8 x i16> @shrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 define <4 x i32> @shrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
 ;CHECK-LABEL: shrn4s:
 ;CHECK: shrn2.4s v0, {{v[0-9]+}}, #1
-        %out = load <2 x i32>* %ret
-        %tmp1 = load <2 x i64>* %A
+        %out = load <2 x i32>, <2 x i32>* %ret
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp2 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
         %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>
         %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -748,7 +748,7 @@ define i32 @sqshrn1s(i64 %A) nounwind {
 define <8 x i8> @sqshrn8b(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqshrn8b:
 ;CHECK: sqshrn.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1)
         ret <8 x i8> %tmp3
 }
@@ -756,7 +756,7 @@ define <8 x i8> @sqshrn8b(<8 x i16>* %A) nounwind {
 define <4 x i16> @sqshrn4h(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqshrn4h:
 ;CHECK: sqshrn.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1)
         ret <4 x i16> %tmp3
 }
@@ -764,7 +764,7 @@ define <4 x i16> @sqshrn4h(<4 x i32>* %A) nounwind {
 define <2 x i32> @sqshrn2s(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: sqshrn2s:
 ;CHECK: sqshrn.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1)
         ret <2 x i32> %tmp3
 }
@@ -773,8 +773,8 @@ define <2 x i32> @sqshrn2s(<2 x i64>* %A) nounwind {
 define <16 x i8> @sqshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqshrn16b:
 ;CHECK: sqshrn2.16b v0, {{v[0-9]+}}, #1
-        %out = load <8 x i8>* %ret
-        %tmp1 = load <8 x i16>* %A
+        %out = load <8 x i8>, <8 x i8>* %ret
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1)
         %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         ret <16 x i8> %tmp4
@@ -783,8 +783,8 @@ define <16 x i8> @sqshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
 define <8 x i16> @sqshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqshrn8h:
 ;CHECK: sqshrn2.8h v0, {{v[0-9]+}}, #1
-        %out = load <4 x i16>* %ret
-        %tmp1 = load <4 x i32>* %A
+        %out = load <4 x i16>, <4 x i16>* %ret
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1)
         %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
         ret <8 x i16> %tmp4
@@ -793,8 +793,8 @@ define <8 x i16> @sqshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 define <4 x i32> @sqshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
 ;CHECK-LABEL: sqshrn4s:
 ;CHECK: sqshrn2.4s v0, {{v[0-9]+}}, #1
-        %out = load <2 x i32>* %ret
-        %tmp1 = load <2 x i64>* %A
+        %out = load <2 x i32>, <2 x i32>* %ret
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1)
         %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
         ret <4 x i32> %tmp4
@@ -815,7 +815,7 @@ define i32 @sqshrun1s(i64 %A) nounwind {
 define <8 x i8> @sqshrun8b(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqshrun8b:
 ;CHECK: sqshrun.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> %tmp1, i32 1)
         ret <8 x i8> %tmp3
 }
@@ -823,7 +823,7 @@ define <8 x i8> @sqshrun8b(<8 x i16>* %A) nounwind {
 define <4 x i16> @sqshrun4h(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqshrun4h:
 ;CHECK: sqshrun.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %tmp1, i32 1)
         ret <4 x i16> %tmp3
 }
@@ -831,7 +831,7 @@ define <4 x i16> @sqshrun4h(<4 x i32>* %A) nounwind {
 define <2 x i32> @sqshrun2s(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: sqshrun2s:
 ;CHECK: sqshrun.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> %tmp1, i32 1)
         ret <2 x i32> %tmp3
 }
@@ -839,8 +839,8 @@ define <2 x i32> @sqshrun2s(<2 x i64>* %A) nounwind {
 define <16 x i8> @sqshrun16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqshrun16b:
 ;CHECK: sqshrun2.16b v0, {{v[0-9]+}}, #1
-        %out = load <8 x i8>* %ret
-        %tmp1 = load <8 x i16>* %A
+        %out = load <8 x i8>, <8 x i8>* %ret
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> %tmp1, i32 1)
         %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         ret <16 x i8> %tmp4
@@ -849,8 +849,8 @@ define <16 x i8> @sqshrun16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
 define <8 x i16> @sqshrun8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqshrun8h:
 ;CHECK: sqshrun2.8h v0, {{v[0-9]+}}, #1
-        %out = load <4 x i16>* %ret
-        %tmp1 = load <4 x i32>* %A
+        %out = load <4 x i16>, <4 x i16>* %ret
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %tmp1, i32 1)
         %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
         ret <8 x i16> %tmp4
@@ -859,8 +859,8 @@ define <8 x i16> @sqshrun8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 define <4 x i32> @sqshrun4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
 ;CHECK-LABEL: sqshrun4s:
 ;CHECK: sqshrun2.4s v0, {{v[0-9]+}}, #1
-        %out = load <2 x i32>* %ret
-        %tmp1 = load <2 x i64>* %A
+        %out = load <2 x i32>, <2 x i32>* %ret
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> %tmp1, i32 1)
         %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
         ret <4 x i32> %tmp4
@@ -881,7 +881,7 @@ define i32 @sqrshrn1s(i64 %A) nounwind {
 define <8 x i8> @sqrshrn8b(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqrshrn8b:
 ;CHECK: sqrshrn.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
         ret <8 x i8> %tmp3
 }
@@ -889,7 +889,7 @@ define <8 x i8> @sqrshrn8b(<8 x i16>* %A) nounwind {
 define <4 x i16> @sqrshrn4h(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqrshrn4h:
 ;CHECK: sqrshrn.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
         ret <4 x i16> %tmp3
 }
@@ -897,7 +897,7 @@ define <4 x i16> @sqrshrn4h(<4 x i32>* %A) nounwind {
 define <2 x i32> @sqrshrn2s(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: sqrshrn2s:
 ;CHECK: sqrshrn.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
         ret <2 x i32> %tmp3
 }
@@ -905,8 +905,8 @@ define <2 x i32> @sqrshrn2s(<2 x i64>* %A) nounwind {
 define <16 x i8> @sqrshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqrshrn16b:
 ;CHECK: sqrshrn2.16b v0, {{v[0-9]+}}, #1
-        %out = load <8 x i8>* %ret
-        %tmp1 = load <8 x i16>* %A
+        %out = load <8 x i8>, <8 x i8>* %ret
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
         %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         ret <16 x i8> %tmp4
@@ -915,8 +915,8 @@ define <16 x i8> @sqrshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
 define <8 x i16> @sqrshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqrshrn8h:
 ;CHECK: sqrshrn2.8h v0, {{v[0-9]+}}, #1
-        %out = load <4 x i16>* %ret
-        %tmp1 = load <4 x i32>* %A
+        %out = load <4 x i16>, <4 x i16>* %ret
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
         %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
         ret <8 x i16> %tmp4
@@ -925,8 +925,8 @@ define <8 x i16> @sqrshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 define <4 x i32> @sqrshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
 ;CHECK-LABEL: sqrshrn4s:
 ;CHECK: sqrshrn2.4s v0, {{v[0-9]+}}, #1
-        %out = load <2 x i32>* %ret
-        %tmp1 = load <2 x i64>* %A
+        %out = load <2 x i32>, <2 x i32>* %ret
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
         %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
         ret <4 x i32> %tmp4
@@ -947,7 +947,7 @@ define i32 @sqrshrun1s(i64 %A) nounwind {
 define <8 x i8> @sqrshrun8b(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqrshrun8b:
 ;CHECK: sqrshrun.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %tmp1, i32 1)
         ret <8 x i8> %tmp3
 }
@@ -955,7 +955,7 @@ define <8 x i8> @sqrshrun8b(<8 x i16>* %A) nounwind {
 define <4 x i16> @sqrshrun4h(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqrshrun4h:
 ;CHECK: sqrshrun.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %tmp1, i32 1)
         ret <4 x i16> %tmp3
 }
@@ -963,7 +963,7 @@ define <4 x i16> @sqrshrun4h(<4 x i32>* %A) nounwind {
 define <2 x i32> @sqrshrun2s(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: sqrshrun2s:
 ;CHECK: sqrshrun.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> %tmp1, i32 1)
         ret <2 x i32> %tmp3
 }
@@ -971,8 +971,8 @@ define <2 x i32> @sqrshrun2s(<2 x i64>* %A) nounwind {
 define <16 x i8> @sqrshrun16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqrshrun16b:
 ;CHECK: sqrshrun2.16b v0, {{v[0-9]+}}, #1
-        %out = load <8 x i8>* %ret
-        %tmp1 = load <8 x i16>* %A
+        %out = load <8 x i8>, <8 x i8>* %ret
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %tmp1, i32 1)
         %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         ret <16 x i8> %tmp4
@@ -981,8 +981,8 @@ define <16 x i8> @sqrshrun16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
 define <8 x i16> @sqrshrun8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqrshrun8h:
 ;CHECK: sqrshrun2.8h v0, {{v[0-9]+}}, #1
-        %out = load <4 x i16>* %ret
-        %tmp1 = load <4 x i32>* %A
+        %out = load <4 x i16>, <4 x i16>* %ret
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %tmp1, i32 1)
         %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
         ret <8 x i16> %tmp4
@@ -991,8 +991,8 @@ define <8 x i16> @sqrshrun8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 define <4 x i32> @sqrshrun4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
 ;CHECK-LABEL: sqrshrun4s:
 ;CHECK: sqrshrun2.4s v0, {{v[0-9]+}}, #1
-        %out = load <2 x i32>* %ret
-        %tmp1 = load <2 x i64>* %A
+        %out = load <2 x i32>, <2 x i32>* %ret
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> %tmp1, i32 1)
         %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
         ret <4 x i32> %tmp4
@@ -1013,7 +1013,7 @@ define i32 @uqrshrn1s(i64 %A) nounwind {
 define <8 x i8> @uqrshrn8b(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: uqrshrn8b:
 ;CHECK: uqrshrn.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
         ret <8 x i8> %tmp3
 }
@@ -1021,7 +1021,7 @@ define <8 x i8> @uqrshrn8b(<8 x i16>* %A) nounwind {
 define <4 x i16> @uqrshrn4h(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: uqrshrn4h:
 ;CHECK: uqrshrn.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
         ret <4 x i16> %tmp3
 }
@@ -1029,7 +1029,7 @@ define <4 x i16> @uqrshrn4h(<4 x i32>* %A) nounwind {
 define <2 x i32> @uqrshrn2s(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: uqrshrn2s:
 ;CHECK: uqrshrn.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
         ret <2 x i32> %tmp3
 }
@@ -1037,8 +1037,8 @@ define <2 x i32> @uqrshrn2s(<2 x i64>* %A) nounwind {
 define <16 x i8> @uqrshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
 ;CHECK-LABEL: uqrshrn16b:
 ;CHECK: uqrshrn2.16b v0, {{v[0-9]+}}, #1
-        %out = load <8 x i8>* %ret
-        %tmp1 = load <8 x i16>* %A
+        %out = load <8 x i8>, <8 x i8>* %ret
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
         %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         ret <16 x i8> %tmp4
@@ -1047,8 +1047,8 @@ define <16 x i8> @uqrshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
 define <8 x i16> @uqrshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 ;CHECK-LABEL: uqrshrn8h:
 ;CHECK: uqrshrn2.8h v0, {{v[0-9]+}}, #1
-        %out = load <4 x i16>* %ret
-        %tmp1 = load <4 x i32>* %A
+        %out = load <4 x i16>, <4 x i16>* %ret
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
         %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
         ret <8 x i16> %tmp4
@@ -1057,8 +1057,8 @@ define <8 x i16> @uqrshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 define <4 x i32> @uqrshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
 ;CHECK-LABEL: uqrshrn4s:
 ;CHECK: uqrshrn2.4s v0, {{v[0-9]+}}, #1
-        %out = load <2 x i32>* %ret
-        %tmp1 = load <2 x i64>* %A
+        %out = load <2 x i32>, <2 x i32>* %ret
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
         %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
         ret <4 x i32> %tmp4
@@ -1079,7 +1079,7 @@ define i32 @uqshrn1s(i64 %A) nounwind {
 define <8 x i8> @uqshrn8b(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: uqshrn8b:
 ;CHECK: uqshrn.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)
         ret <8 x i8> %tmp3
 }
@@ -1087,7 +1087,7 @@ define <8 x i8> @uqshrn8b(<8 x i16>* %A) nounwind {
 define <4 x i16> @uqshrn4h(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: uqshrn4h:
 ;CHECK: uqshrn.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)
         ret <4 x i16> %tmp3
 }
@@ -1095,7 +1095,7 @@ define <4 x i16> @uqshrn4h(<4 x i32>* %A) nounwind {
 define <2 x i32> @uqshrn2s(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: uqshrn2s:
 ;CHECK: uqshrn.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1)
         ret <2 x i32> %tmp3
 }
@@ -1103,8 +1103,8 @@ define <2 x i32> @uqshrn2s(<2 x i64>* %A) nounwind {
 define <16 x i8> @uqshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
 ;CHECK-LABEL: uqshrn16b:
 ;CHECK: uqshrn2.16b v0, {{v[0-9]+}}, #1
-        %out = load <8 x i8>* %ret
-        %tmp1 = load <8 x i16>* %A
+        %out = load <8 x i8>, <8 x i8>* %ret
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)
         %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         ret <16 x i8> %tmp4
@@ -1113,8 +1113,8 @@ define <16 x i8> @uqshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
 define <8 x i16> @uqshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 ;CHECK-LABEL: uqshrn8h:
 ;CHECK: uqshrn2.8h v0, {{v[0-9]+}}, #1
-  %out = load <4 x i16>* %ret
-  %tmp1 = load <4 x i32>* %A
+  %out = load <4 x i16>, <4 x i16>* %ret
+  %tmp1 = load <4 x i32>, <4 x i32>* %A
   %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)
   %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %tmp4
@@ -1123,8 +1123,8 @@ define <8 x i16> @uqshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
 define <4 x i32> @uqshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
 ;CHECK-LABEL: uqshrn4s:
 ;CHECK: uqshrn2.4s v0, {{v[0-9]+}}, #1
-  %out = load <2 x i32>* %ret
-  %tmp1 = load <2 x i64>* %A
+  %out = load <2 x i32>, <2 x i32>* %ret
+  %tmp1 = load <2 x i64>, <2 x i64>* %A
   %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1)
   %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x i32> %tmp4
@@ -1138,7 +1138,7 @@ declare <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64>, i32) nounwind readn
 define <8 x i16> @ushll8h(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: ushll8h:
 ;CHECK: ushll.8h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
         %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
         ret <8 x i16> %tmp3
@@ -1147,7 +1147,7 @@ define <8 x i16> @ushll8h(<8 x i8>* %A) nounwind {
 define <4 x i32> @ushll4s(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: ushll4s:
 ;CHECK: ushll.4s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
         %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
         ret <4 x i32> %tmp3
@@ -1156,7 +1156,7 @@ define <4 x i32> @ushll4s(<4 x i16>* %A) nounwind {
 define <2 x i64> @ushll2d(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: ushll2d:
 ;CHECK: ushll.2d v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
         %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
         ret <2 x i64> %tmp3
@@ -1165,7 +1165,7 @@ define <2 x i64> @ushll2d(<2 x i32>* %A) nounwind {
 define <8 x i16> @ushll2_8h(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: ushll2_8h:
 ;CHECK: ushll2.8h v0, {{v[0-9]+}}, #1
-        %load1 = load <16 x i8>* %A
+        %load1 = load <16 x i8>, <16 x i8>* %A
         %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
         %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1175,7 +1175,7 @@ define <8 x i16> @ushll2_8h(<16 x i8>* %A) nounwind {
 define <4 x i32> @ushll2_4s(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: ushll2_4s:
 ;CHECK: ushll2.4s v0, {{v[0-9]+}}, #1
-        %load1 = load <8 x i16>* %A
+        %load1 = load <8 x i16>, <8 x i16>* %A
         %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
         %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
         %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
@@ -1185,7 +1185,7 @@ define <4 x i32> @ushll2_4s(<8 x i16>* %A) nounwind {
 define <2 x i64> @ushll2_2d(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: ushll2_2d:
 ;CHECK: ushll2.2d v0, {{v[0-9]+}}, #1
-        %load1 = load <4 x i32>* %A
+        %load1 = load <4 x i32>, <4 x i32>* %A
         %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
         %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
         %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
@@ -1195,7 +1195,7 @@ define <2 x i64> @ushll2_2d(<4 x i32>* %A) nounwind {
 define <8 x i16> @sshll8h(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: sshll8h:
 ;CHECK: sshll.8h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
         %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
         ret <8 x i16> %tmp3
@@ -1204,7 +1204,7 @@ define <8 x i16> @sshll8h(<8 x i8>* %A) nounwind {
 define <4 x i32> @sshll4s(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: sshll4s:
 ;CHECK: sshll.4s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
         %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
         ret <4 x i32> %tmp3
@@ -1213,7 +1213,7 @@ define <4 x i32> @sshll4s(<4 x i16>* %A) nounwind {
 define <2 x i64> @sshll2d(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: sshll2d:
 ;CHECK: sshll.2d v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
         %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
         ret <2 x i64> %tmp3
@@ -1222,7 +1222,7 @@ define <2 x i64> @sshll2d(<2 x i32>* %A) nounwind {
 define <8 x i16> @sshll2_8h(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: sshll2_8h:
 ;CHECK: sshll2.8h v0, {{v[0-9]+}}, #1
-        %load1 = load <16 x i8>* %A
+        %load1 = load <16 x i8>, <16 x i8>* %A
         %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
         %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1232,7 +1232,7 @@ define <8 x i16> @sshll2_8h(<16 x i8>* %A) nounwind {
 define <4 x i32> @sshll2_4s(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: sshll2_4s:
 ;CHECK: sshll2.4s v0, {{v[0-9]+}}, #1
-        %load1 = load <8 x i16>* %A
+        %load1 = load <8 x i16>, <8 x i16>* %A
         %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
         %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
         %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
@@ -1242,7 +1242,7 @@ define <4 x i32> @sshll2_4s(<8 x i16>* %A) nounwind {
 define <2 x i64> @sshll2_2d(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: sshll2_2d:
 ;CHECK: sshll2.2d v0, {{v[0-9]+}}, #1
-        %load1 = load <4 x i32>* %A
+        %load1 = load <4 x i32>, <4 x i32>* %A
         %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
         %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
         %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
@@ -1252,7 +1252,7 @@ define <2 x i64> @sshll2_2d(<4 x i32>* %A) nounwind {
 define <8 x i8> @sqshli8b(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: sqshli8b:
 ;CHECK: sqshl.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
         ret <8 x i8> %tmp3
 }
@@ -1260,7 +1260,7 @@ define <8 x i8> @sqshli8b(<8 x i8>* %A) nounwind {
 define <4 x i16> @sqshli4h(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqshli4h:
 ;CHECK: sqshl.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
         ret <4 x i16> %tmp3
 }
@@ -1268,7 +1268,7 @@ define <4 x i16> @sqshli4h(<4 x i16>* %A) nounwind {
 define <2 x i32> @sqshli2s(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqshli2s:
 ;CHECK: sqshl.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)
         ret <2 x i32> %tmp3
 }
@@ -1276,7 +1276,7 @@ define <2 x i32> @sqshli2s(<2 x i32>* %A) nounwind {
 define <16 x i8> @sqshli16b(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: sqshli16b:
 ;CHECK: sqshl.16b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
         ret <16 x i8> %tmp3
 }
@@ -1284,7 +1284,7 @@ define <16 x i8> @sqshli16b(<16 x i8>* %A) nounwind {
 define <8 x i16> @sqshli8h(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: sqshli8h:
 ;CHECK: sqshl.8h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
         ret <8 x i16> %tmp3
 }
@@ -1292,7 +1292,7 @@ define <8 x i16> @sqshli8h(<8 x i16>* %A) nounwind {
 define <4 x i32> @sqshli4s(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: sqshli4s:
 ;CHECK: sqshl.4s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
         ret <4 x i32> %tmp3
 }
@@ -1300,7 +1300,7 @@ define <4 x i32> @sqshli4s(<4 x i32>* %A) nounwind {
 define <2 x i64> @sqshli2d(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: sqshli2d:
 ;CHECK: sqshl.2d v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)
         ret <2 x i64> %tmp3
 }
@@ -1308,7 +1308,7 @@ define <2 x i64> @sqshli2d(<2 x i64>* %A) nounwind {
 define <8 x i8> @uqshli8b(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: uqshli8b:
 ;CHECK: uqshl.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
         ret <8 x i8> %tmp3
 }
@@ -1317,7 +1317,7 @@ define <8 x i8> @uqshli8b_1(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: uqshli8b_1:
 ;CHECK: movi.8b [[REG:v[0-9]+]], #0x8
 ;CHECK: uqshl.8b v0, v0, [[REG]]
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>)
         ret <8 x i8> %tmp3
 }
@@ -1325,7 +1325,7 @@ define <8 x i8> @uqshli8b_1(<8 x i8>* %A) nounwind {
 define <4 x i16> @uqshli4h(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: uqshli4h:
 ;CHECK: uqshl.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
         ret <4 x i16> %tmp3
 }
@@ -1333,7 +1333,7 @@ define <4 x i16> @uqshli4h(<4 x i16>* %A) nounwind {
 define <2 x i32> @uqshli2s(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: uqshli2s:
 ;CHECK: uqshl.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)
         ret <2 x i32> %tmp3
 }
@@ -1341,7 +1341,7 @@ define <2 x i32> @uqshli2s(<2 x i32>* %A) nounwind {
 define <16 x i8> @uqshli16b(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: uqshli16b:
 ;CHECK: uqshl.16b
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
         ret <16 x i8> %tmp3
 }
@@ -1349,7 +1349,7 @@ define <16 x i8> @uqshli16b(<16 x i8>* %A) nounwind {
 define <8 x i16> @uqshli8h(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: uqshli8h:
 ;CHECK: uqshl.8h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
         ret <8 x i16> %tmp3
 }
@@ -1357,7 +1357,7 @@ define <8 x i16> @uqshli8h(<8 x i16>* %A) nounwind {
 define <4 x i32> @uqshli4s(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: uqshli4s:
 ;CHECK: uqshl.4s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
         ret <4 x i32> %tmp3
 }
@@ -1365,7 +1365,7 @@ define <4 x i32> @uqshli4s(<4 x i32>* %A) nounwind {
 define <2 x i64> @uqshli2d(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: uqshli2d:
 ;CHECK: uqshl.2d v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)
         ret <2 x i64> %tmp3
 }
@@ -1373,9 +1373,9 @@ define <2 x i64> @uqshli2d(<2 x i64>* %A) nounwind {
 define <8 x i8> @ursra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: ursra8b:
 ;CHECK: ursra.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
-        %tmp4 = load <8 x i8>* %B
+        %tmp4 = load <8 x i8>, <8 x i8>* %B
         %tmp5 = add <8 x i8> %tmp3, %tmp4
         ret <8 x i8> %tmp5
 }
@@ -1383,9 +1383,9 @@ define <8 x i8> @ursra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @ursra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: ursra4h:
 ;CHECK: ursra.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
-        %tmp4 = load <4 x i16>* %B
+        %tmp4 = load <4 x i16>, <4 x i16>* %B
         %tmp5 = add <4 x i16> %tmp3, %tmp4
         ret <4 x i16> %tmp5
 }
@@ -1393,9 +1393,9 @@ define <4 x i16> @ursra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @ursra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: ursra2s:
 ;CHECK: ursra.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
-        %tmp4 = load <2 x i32>* %B
+        %tmp4 = load <2 x i32>, <2 x i32>* %B
         %tmp5 = add <2 x i32> %tmp3, %tmp4
         ret <2 x i32> %tmp5
 }
@@ -1403,9 +1403,9 @@ define <2 x i32> @ursra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @ursra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: ursra16b:
 ;CHECK: ursra.16b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
-        %tmp4 = load <16 x i8>* %B
+        %tmp4 = load <16 x i8>, <16 x i8>* %B
         %tmp5 = add <16 x i8> %tmp3, %tmp4
          ret <16 x i8> %tmp5
 }
@@ -1413,9 +1413,9 @@ define <16 x i8> @ursra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @ursra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: ursra8h:
 ;CHECK: ursra.8h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
-        %tmp4 = load <8 x i16>* %B
+        %tmp4 = load <8 x i16>, <8 x i16>* %B
         %tmp5 = add <8 x i16> %tmp3, %tmp4
          ret <8 x i16> %tmp5
 }
@@ -1423,9 +1423,9 @@ define <8 x i16> @ursra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @ursra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: ursra4s:
 ;CHECK: ursra.4s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
-        %tmp4 = load <4 x i32>* %B
+        %tmp4 = load <4 x i32>, <4 x i32>* %B
         %tmp5 = add <4 x i32> %tmp3, %tmp4
          ret <4 x i32> %tmp5
 }
@@ -1433,9 +1433,9 @@ define <4 x i32> @ursra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @ursra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: ursra2d:
 ;CHECK: ursra.2d v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
-        %tmp4 = load <2 x i64>* %B
+        %tmp4 = load <2 x i64>, <2 x i64>* %B
         %tmp5 = add <2 x i64> %tmp3, %tmp4
          ret <2 x i64> %tmp5
 }
@@ -1443,9 +1443,9 @@ define <2 x i64> @ursra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @srsra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: srsra8b:
 ;CHECK: srsra.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
-        %tmp4 = load <8 x i8>* %B
+        %tmp4 = load <8 x i8>, <8 x i8>* %B
         %tmp5 = add <8 x i8> %tmp3, %tmp4
         ret <8 x i8> %tmp5
 }
@@ -1453,9 +1453,9 @@ define <8 x i8> @srsra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @srsra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: srsra4h:
 ;CHECK: srsra.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
-        %tmp4 = load <4 x i16>* %B
+        %tmp4 = load <4 x i16>, <4 x i16>* %B
         %tmp5 = add <4 x i16> %tmp3, %tmp4
         ret <4 x i16> %tmp5
 }
@@ -1463,9 +1463,9 @@ define <4 x i16> @srsra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @srsra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: srsra2s:
 ;CHECK: srsra.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
-        %tmp4 = load <2 x i32>* %B
+        %tmp4 = load <2 x i32>, <2 x i32>* %B
         %tmp5 = add <2 x i32> %tmp3, %tmp4
         ret <2 x i32> %tmp5
 }
@@ -1473,9 +1473,9 @@ define <2 x i32> @srsra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @srsra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: srsra16b:
 ;CHECK: srsra.16b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
-        %tmp4 = load <16 x i8>* %B
+        %tmp4 = load <16 x i8>, <16 x i8>* %B
         %tmp5 = add <16 x i8> %tmp3, %tmp4
          ret <16 x i8> %tmp5
 }
@@ -1483,9 +1483,9 @@ define <16 x i8> @srsra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @srsra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: srsra8h:
 ;CHECK: srsra.8h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
-        %tmp4 = load <8 x i16>* %B
+        %tmp4 = load <8 x i16>, <8 x i16>* %B
         %tmp5 = add <8 x i16> %tmp3, %tmp4
          ret <8 x i16> %tmp5
 }
@@ -1493,9 +1493,9 @@ define <8 x i16> @srsra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @srsra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: srsra4s:
 ;CHECK: srsra.4s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
-        %tmp4 = load <4 x i32>* %B
+        %tmp4 = load <4 x i32>, <4 x i32>* %B
         %tmp5 = add <4 x i32> %tmp3, %tmp4
          ret <4 x i32> %tmp5
 }
@@ -1503,9 +1503,9 @@ define <4 x i32> @srsra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @srsra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: srsra2d:
 ;CHECK: srsra.2d v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
-        %tmp4 = load <2 x i64>* %B
+        %tmp4 = load <2 x i64>, <2 x i64>* %B
         %tmp5 = add <2 x i64> %tmp3, %tmp4
          ret <2 x i64> %tmp5
 }
@@ -1513,9 +1513,9 @@ define <2 x i64> @srsra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @usra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: usra8b:
 ;CHECK: usra.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = lshr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
-        %tmp4 = load <8 x i8>* %B
+        %tmp4 = load <8 x i8>, <8 x i8>* %B
         %tmp5 = add <8 x i8> %tmp3, %tmp4
         ret <8 x i8> %tmp5
 }
@@ -1523,9 +1523,9 @@ define <8 x i8> @usra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @usra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: usra4h:
 ;CHECK: usra.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = lshr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
-        %tmp4 = load <4 x i16>* %B
+        %tmp4 = load <4 x i16>, <4 x i16>* %B
         %tmp5 = add <4 x i16> %tmp3, %tmp4
         ret <4 x i16> %tmp5
 }
@@ -1533,9 +1533,9 @@ define <4 x i16> @usra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @usra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: usra2s:
 ;CHECK: usra.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp3 = lshr <2 x i32> %tmp1, <i32 1, i32 1>
-        %tmp4 = load <2 x i32>* %B
+        %tmp4 = load <2 x i32>, <2 x i32>* %B
         %tmp5 = add <2 x i32> %tmp3, %tmp4
         ret <2 x i32> %tmp5
 }
@@ -1543,9 +1543,9 @@ define <2 x i32> @usra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @usra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: usra16b:
 ;CHECK: usra.16b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = lshr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
-        %tmp4 = load <16 x i8>* %B
+        %tmp4 = load <16 x i8>, <16 x i8>* %B
         %tmp5 = add <16 x i8> %tmp3, %tmp4
          ret <16 x i8> %tmp5
 }
@@ -1553,9 +1553,9 @@ define <16 x i8> @usra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @usra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: usra8h:
 ;CHECK: usra.8h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
-        %tmp4 = load <8 x i16>* %B
+        %tmp4 = load <8 x i16>, <8 x i16>* %B
         %tmp5 = add <8 x i16> %tmp3, %tmp4
          ret <8 x i16> %tmp5
 }
@@ -1563,9 +1563,9 @@ define <8 x i16> @usra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @usra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: usra4s:
 ;CHECK: usra.4s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
-        %tmp4 = load <4 x i32>* %B
+        %tmp4 = load <4 x i32>, <4 x i32>* %B
         %tmp5 = add <4 x i32> %tmp3, %tmp4
          ret <4 x i32> %tmp5
 }
@@ -1573,9 +1573,9 @@ define <4 x i32> @usra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @usra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: usra2d:
 ;CHECK: usra.2d v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
-        %tmp4 = load <2 x i64>* %B
+        %tmp4 = load <2 x i64>, <2 x i64>* %B
         %tmp5 = add <2 x i64> %tmp3, %tmp4
          ret <2 x i64> %tmp5
 }
@@ -1583,9 +1583,9 @@ define <2 x i64> @usra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @ssra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: ssra8b:
 ;CHECK: ssra.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp3 = ashr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
-        %tmp4 = load <8 x i8>* %B
+        %tmp4 = load <8 x i8>, <8 x i8>* %B
         %tmp5 = add <8 x i8> %tmp3, %tmp4
         ret <8 x i8> %tmp5
 }
@@ -1593,9 +1593,9 @@ define <8 x i8> @ssra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @ssra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: ssra4h:
 ;CHECK: ssra.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp3 = ashr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
-        %tmp4 = load <4 x i16>* %B
+        %tmp4 = load <4 x i16>, <4 x i16>* %B
         %tmp5 = add <4 x i16> %tmp3, %tmp4
         ret <4 x i16> %tmp5
 }
@@ -1603,9 +1603,9 @@ define <4 x i16> @ssra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @ssra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: ssra2s:
 ;CHECK: ssra.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %tmp3 = ashr <2 x i32> %tmp1, <i32 1, i32 1>
-        %tmp4 = load <2 x i32>* %B
+        %tmp4 = load <2 x i32>, <2 x i32>* %B
         %tmp5 = add <2 x i32> %tmp3, %tmp4
         ret <2 x i32> %tmp5
 }
@@ -1613,9 +1613,9 @@ define <2 x i32> @ssra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @ssra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: ssra16b:
 ;CHECK: ssra.16b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp3 = ashr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
-        %tmp4 = load <16 x i8>* %B
+        %tmp4 = load <16 x i8>, <16 x i8>* %B
         %tmp5 = add <16 x i8> %tmp3, %tmp4
          ret <16 x i8> %tmp5
 }
@@ -1623,9 +1623,9 @@ define <16 x i8> @ssra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @ssra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: ssra8h:
 ;CHECK: ssra.8h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp3 = ashr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
-        %tmp4 = load <8 x i16>* %B
+        %tmp4 = load <8 x i16>, <8 x i16>* %B
         %tmp5 = add <8 x i16> %tmp3, %tmp4
          ret <8 x i16> %tmp5
 }
@@ -1633,9 +1633,9 @@ define <8 x i16> @ssra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @ssra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: ssra4s:
 ;CHECK: ssra.4s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp3 = ashr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
-        %tmp4 = load <4 x i32>* %B
+        %tmp4 = load <4 x i32>, <4 x i32>* %B
         %tmp5 = add <4 x i32> %tmp3, %tmp4
          ret <4 x i32> %tmp5
 }
@@ -1643,9 +1643,9 @@ define <4 x i32> @ssra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @ssra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: ssra2d:
 ;CHECK: ssra.2d v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp3 = ashr <2 x i64> %tmp1, <i64 1, i64 1>
-        %tmp4 = load <2 x i64>* %B
+        %tmp4 = load <2 x i64>, <2 x i64>* %B
         %tmp5 = add <2 x i64> %tmp3, %tmp4
          ret <2 x i64> %tmp5
 }
@@ -1655,8 +1655,8 @@ define <8 x i8> @shr_orr8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: shr.8b v0, {{v[0-9]+}}, #1
 ;CHECK-NEXT: orr.8b
 ;CHECK-NEXT: ret
-        %tmp1 = load <8 x i8>* %A
-        %tmp4 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp4 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = lshr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
         %tmp5 = or <8 x i8> %tmp3, %tmp4
         ret <8 x i8> %tmp5
@@ -1667,8 +1667,8 @@ define <4 x i16> @shr_orr4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: shr.4h v0, {{v[0-9]+}}, #1
 ;CHECK-NEXT: orr.8b
 ;CHECK-NEXT: ret
-        %tmp1 = load <4 x i16>* %A
-        %tmp4 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp4 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = lshr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
         %tmp5 = or <4 x i16> %tmp3, %tmp4
         ret <4 x i16> %tmp5
@@ -1679,8 +1679,8 @@ define <2 x i32> @shr_orr2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK: shr.2s v0, {{v[0-9]+}}, #1
 ;CHECK-NEXT: orr.8b
 ;CHECK-NEXT: ret
-        %tmp1 = load <2 x i32>* %A
-        %tmp4 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp4 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = lshr <2 x i32> %tmp1, <i32 1, i32 1>
         %tmp5 = or <2 x i32> %tmp3, %tmp4
         ret <2 x i32> %tmp5
@@ -1691,8 +1691,8 @@ define <16 x i8> @shr_orr16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK: shr.16b v0, {{v[0-9]+}}, #1
 ;CHECK-NEXT: orr.16b
 ;CHECK-NEXT: ret
-        %tmp1 = load <16 x i8>* %A
-        %tmp4 = load <16 x i8>* %B
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
+        %tmp4 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = lshr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
         %tmp5 = or <16 x i8> %tmp3, %tmp4
          ret <16 x i8> %tmp5
@@ -1703,8 +1703,8 @@ define <8 x i16> @shr_orr8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK: shr.8h v0, {{v[0-9]+}}, #1
 ;CHECK-NEXT: orr.16b
 ;CHECK-NEXT: ret
-        %tmp1 = load <8 x i16>* %A
-        %tmp4 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp4 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
         %tmp5 = or <8 x i16> %tmp3, %tmp4
          ret <8 x i16> %tmp5
@@ -1715,8 +1715,8 @@ define <4 x i32> @shr_orr4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK: shr.4s v0, {{v[0-9]+}}, #1
 ;CHECK-NEXT: orr.16b
 ;CHECK-NEXT: ret
-        %tmp1 = load <4 x i32>* %A
-        %tmp4 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp4 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
         %tmp5 = or <4 x i32> %tmp3, %tmp4
          ret <4 x i32> %tmp5
@@ -1727,8 +1727,8 @@ define <2 x i64> @shr_orr2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK: shr.2d v0, {{v[0-9]+}}, #1
 ;CHECK-NEXT: orr.16b
 ;CHECK-NEXT: ret
-        %tmp1 = load <2 x i64>* %A
-        %tmp4 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp4 = load <2 x i64>, <2 x i64>* %B
         %tmp3 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
         %tmp5 = or <2 x i64> %tmp3, %tmp4
          ret <2 x i64> %tmp5
@@ -1739,8 +1739,8 @@ define <8 x i8> @shl_orr8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: shl.8b v0, {{v[0-9]+}}, #1
 ;CHECK-NEXT: orr.8b
 ;CHECK-NEXT: ret
-        %tmp1 = load <8 x i8>* %A
-        %tmp4 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp4 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = shl <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
         %tmp5 = or <8 x i8> %tmp3, %tmp4
         ret <8 x i8> %tmp5
@@ -1751,8 +1751,8 @@ define <4 x i16> @shl_orr4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: shl.4h v0, {{v[0-9]+}}, #1
 ;CHECK-NEXT: orr.8b
 ;CHECK-NEXT: ret
-        %tmp1 = load <4 x i16>* %A
-        %tmp4 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp4 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = shl <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
         %tmp5 = or <4 x i16> %tmp3, %tmp4
         ret <4 x i16> %tmp5
@@ -1763,8 +1763,8 @@ define <2 x i32> @shl_orr2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK: shl.2s v0, {{v[0-9]+}}, #1
 ;CHECK-NEXT: orr.8b
 ;CHECK-NEXT: ret
-        %tmp1 = load <2 x i32>* %A
-        %tmp4 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp4 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = shl <2 x i32> %tmp1, <i32 1, i32 1>
         %tmp5 = or <2 x i32> %tmp3, %tmp4
         ret <2 x i32> %tmp5
@@ -1775,8 +1775,8 @@ define <16 x i8> @shl_orr16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK: shl.16b v0, {{v[0-9]+}}, #1
 ;CHECK-NEXT: orr.16b
 ;CHECK-NEXT: ret
-        %tmp1 = load <16 x i8>* %A
-        %tmp4 = load <16 x i8>* %B
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
+        %tmp4 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shl <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
         %tmp5 = or <16 x i8> %tmp3, %tmp4
          ret <16 x i8> %tmp5
@@ -1787,8 +1787,8 @@ define <8 x i16> @shl_orr8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK: shl.8h v0, {{v[0-9]+}}, #1
 ;CHECK-NEXT: orr.16b
 ;CHECK-NEXT: ret
-        %tmp1 = load <8 x i16>* %A
-        %tmp4 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp4 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = shl <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
         %tmp5 = or <8 x i16> %tmp3, %tmp4
          ret <8 x i16> %tmp5
@@ -1799,8 +1799,8 @@ define <4 x i32> @shl_orr4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK: shl.4s v0, {{v[0-9]+}}, #1
 ;CHECK-NEXT: orr.16b
 ;CHECK-NEXT: ret
-        %tmp1 = load <4 x i32>* %A
-        %tmp4 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp4 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = shl <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
         %tmp5 = or <4 x i32> %tmp3, %tmp4
          ret <4 x i32> %tmp5
@@ -1811,8 +1811,8 @@ define <2 x i64> @shl_orr2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK: shl.2d v0, {{v[0-9]+}}, #1
 ;CHECK-NEXT: orr.16b
 ;CHECK-NEXT: ret
-        %tmp1 = load <2 x i64>* %A
-        %tmp4 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp4 = load <2 x i64>, <2 x i64>* %B
         %tmp3 = shl <2 x i64> %tmp1, <i64 1, i64 1>
         %tmp5 = or <2 x i64> %tmp3, %tmp4
          ret <2 x i64> %tmp5
@@ -1838,8 +1838,8 @@ define <4 x i32> @shll_high(<8 x i16> %in) {
 define <8 x i8> @sli8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: sli8b:
 ;CHECK: sli.8b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.vsli.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, i32 1)
         ret <8 x i8> %tmp3
 }
@@ -1847,8 +1847,8 @@ define <8 x i8> @sli8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @sli4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sli4h:
 ;CHECK: sli.4h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.vsli.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, i32 1)
         ret <4 x i16> %tmp3
 }
@@ -1856,8 +1856,8 @@ define <4 x i16> @sli4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @sli2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sli2s:
 ;CHECK: sli.2s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.vsli.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, i32 1)
         ret <2 x i32> %tmp3
 }
@@ -1865,8 +1865,8 @@ define <2 x i32> @sli2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @sli1d(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: sli1d:
 ;CHECK: sli d0, {{d[0-9]+}}, #1
-        %tmp1 = load <1 x i64>* %A
-        %tmp2 = load <1 x i64>* %B
+        %tmp1 = load <1 x i64>, <1 x i64>* %A
+        %tmp2 = load <1 x i64>, <1 x i64>* %B
         %tmp3 = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, i32 1)
         ret <1 x i64> %tmp3
 }
@@ -1874,8 +1874,8 @@ define <1 x i64> @sli1d(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @sli16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: sli16b:
 ;CHECK: sli.16b v0, {{v[0-9]+}}, #1
-        %tmp1 = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = call <16 x i8> @llvm.aarch64.neon.vsli.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, i32 1)
         ret <16 x i8> %tmp3
 }
@@ -1883,8 +1883,8 @@ define <16 x i8> @sli16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @sli8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sli8h:
 ;CHECK: sli.8h v0, {{v[0-9]+}}, #1
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i16> @llvm.aarch64.neon.vsli.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, i32 1)
         ret <8 x i16> %tmp3
 }
@@ -1892,8 +1892,8 @@ define <8 x i16> @sli8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @sli4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sli4s:
 ;CHECK: sli.4s v0, {{v[0-9]+}}, #1
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i32> @llvm.aarch64.neon.vsli.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, i32 1)
         ret <4 x i32> %tmp3
 }
@@ -1901,8 +1901,8 @@ define <4 x i32> @sli4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @sli2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: sli2d:
 ;CHECK: sli.2d v0, {{v[0-9]+}}, #1
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %tmp3 = call <2 x i64> @llvm.aarch64.neon.vsli.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, i32 1)
         ret <2 x i64> %tmp3
 }
diff --git a/test/CodeGen/AArch64/arm64-vshr.ll b/test/CodeGen/AArch64/arm64-vshr.ll
index 21eb579f2522..8d263f22c54e 100644
--- a/test/CodeGen/AArch64/arm64-vshr.ll
+++ b/test/CodeGen/AArch64/arm64-vshr.ll
@@ -10,8 +10,8 @@ entry:
   %b.addr = alloca <8 x i16>, align 16
   store <8 x i16> %a, <8 x i16>* %a.addr, align 16
   store <8 x i16> %b, <8 x i16>* %b.addr, align 16
-  %0 = load <8 x i16>* %a.addr, align 16
-  %1 = load <8 x i16>* %b.addr, align 16
+  %0 = load <8 x i16>, <8 x i16>* %a.addr, align 16
+  %1 = load <8 x i16>, <8 x i16>* %b.addr, align 16
   %shr = ashr <8 x i16> %0, %1
   ret <8 x i16> %shr
 }
@@ -25,8 +25,8 @@ entry:
   %b.addr = alloca <4 x i32>, align 32
   store <4 x i32> %a, <4 x i32>* %a.addr, align 32
   store <4 x i32> %b, <4 x i32>* %b.addr, align 32
-  %0 = load <4 x i32>* %a.addr, align 32
-  %1 = load <4 x i32>* %b.addr, align 32
+  %0 = load <4 x i32>, <4 x i32>* %a.addr, align 32
+  %1 = load <4 x i32>, <4 x i32>* %b.addr, align 32
   %shr = ashr <4 x i32> %0, %1
   ret <4 x i32> %shr
 }
@@ -40,8 +40,8 @@ entry:
   %b.addr = alloca <8 x i16>, align 16
   store <8 x i16> %a, <8 x i16>* %a.addr, align 16
   store <8 x i16> %b, <8 x i16>* %b.addr, align 16
-  %0 = load <8 x i16>* %a.addr, align 16
-  %1 = load <8 x i16>* %b.addr, align 16
+  %0 = load <8 x i16>, <8 x i16>* %a.addr, align 16
+  %1 = load <8 x i16>, <8 x i16>* %b.addr, align 16
   %shr = lshr <8 x i16> %0, %1
   ret <8 x i16> %shr
 }
diff --git a/test/CodeGen/AArch64/arm64-vshuffle.ll b/test/CodeGen/AArch64/arm64-vshuffle.ll
index 62fd96102d01..15ea21b7638d 100644
--- a/test/CodeGen/AArch64/arm64-vshuffle.ll
+++ b/test/CodeGen/AArch64/arm64-vshuffle.ll
@@ -1,22 +1,8 @@
 ; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -mcpu=cyclone | FileCheck %s
 
 
-; The mask:
-; CHECK: lCPI0_0:
-; CHECK:  .byte   2                       ; 0x2
-; CHECK:  .byte   255                     ; 0xff
-; CHECK:  .byte   6                       ; 0x6
-; CHECK:  .byte   255                     ; 0xff
-; The second vector is legalized to undef and the elements of the first vector
-; are used instead.
-; CHECK:  .byte   2                       ; 0x2
-; CHECK:  .byte   4                       ; 0x4
-; CHECK:  .byte   6                       ; 0x6
-; CHECK:  .byte   0                       ; 0x0
 ; CHECK: test1
-; CHECK: ldr d[[REG0:[0-9]+]], [{{.*}}, lCPI0_0
-; CHECK: movi.8h v[[REG1:[0-9]+]], #0x1, lsl #8
-; CHECK: tbl.8b  v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]]
+; CHECK: movi d[[REG0:[0-9]+]], #0000000000000000
 define <8 x i1> @test1() {
 entry:
   %Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
@@ -29,19 +15,17 @@ entry:
 }
 
 ; CHECK: lCPI1_0:
-; CHECK:          .byte   2                       ; 0x2
-; CHECK:          .byte   255                     ; 0xff
-; CHECK:          .byte   6                       ; 0x6
-; CHECK:          .byte   255                     ; 0xff
-; CHECK:          .byte   10                      ; 0xa
-; CHECK:          .byte   12                      ; 0xc
-; CHECK:          .byte   14                      ; 0xe
+; CHECK:          .byte   0                       ; 0x0
+; CHECK:          .byte   0                       ; 0x0
+; CHECK:          .byte   0                       ; 0x0
+; CHECK:          .byte   0                       ; 0x0
+; CHECK:          .byte   1                       ; 0x1
+; CHECK:          .byte   0                       ; 0x0
+; CHECK:          .byte   0                       ; 0x0
 ; CHECK:          .byte   0                       ; 0x0
 ; CHECK: test2
-; CHECK: ldr     d[[REG0:[0-9]+]], [{{.*}}, lCPI1_0@PAGEOFF]
-; CHECK: adrp    x[[REG2:[0-9]+]], lCPI1_1@PAGE
-; CHECK: ldr     q[[REG1:[0-9]+]], [x[[REG2]], lCPI1_1@PAGEOFF]
-; CHECK: tbl.8b  v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]]
+; CHECK: adrp    x[[REG2:[0-9]+]], lCPI1_0@PAGE
+; CHECK: ldr     d[[REG1:[0-9]+]], [x[[REG2]], lCPI1_0@PAGEOFF]
 define <8 x i1>@test2() {
 bb:
   %Shuff = shufflevector <8 x i1> zeroinitializer,
@@ -51,28 +35,8 @@ bb:
   ret <8 x i1> %Shuff
 }
 
-; CHECK: lCPI2_0:
-; CHECK:         .byte   2                       ; 0x2
-; CHECK:         .byte   255                     ; 0xff
-; CHECK:         .byte   6                       ; 0x6
-; CHECK:         .byte   255                     ; 0xff
-; CHECK:         .byte   10                      ; 0xa
-; CHECK:         .byte   12                      ; 0xc
-; CHECK:         .byte   14                      ; 0xe
-; CHECK:         .byte   0                       ; 0x0
-; CHECK:         .byte   2                       ; 0x2
-; CHECK:         .byte   255                     ; 0xff
-; CHECK:         .byte   6                       ; 0x6
-; CHECK:         .byte   255                     ; 0xff
-; CHECK:         .byte   10                      ; 0xa
-; CHECK:         .byte   12                      ; 0xc
-; CHECK:         .byte   14                      ; 0xe
-; CHECK:         .byte   0                       ; 0x0
 ; CHECK: test3
-; CHECK: adrp    x[[REG3:[0-9]+]], lCPI2_0@PAGE
-; CHECK: ldr     q[[REG0:[0-9]+]], [x[[REG3]], lCPI2_0@PAGEOFF]
-; CHECK: ldr     q[[REG1:[0-9]+]], [x[[REG3]], lCPI2_1@PAGEOFF]
-; CHECK: tbl.16b v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]]
+; CHECK: movi.4s v{{[0-9]+}}, #0x1
 define <16 x i1> @test3(i1* %ptr, i32 %v) {
 bb:
   %Shuff = shufflevector <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>, <16 x i1> undef,
@@ -81,29 +45,26 @@ bb:
                  i32 14, i32 0>
   ret <16 x i1> %Shuff
 }
-; CHECK: lCPI3_1:
-; CHECK:         .byte   2                       ; 0x2
+; CHECK: lCPI3_0:
+; CHECK:         .byte   0                       ; 0x0
+; CHECK:         .byte   0                       ; 0x0
+; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   1                       ; 0x1
-; CHECK:         .byte   6                       ; 0x6
-; CHECK:         .byte   18                      ; 0x12
-; CHECK:         .byte   10                      ; 0xa
-; CHECK:         .byte   12                      ; 0xc
-; CHECK:         .byte   14                      ; 0xe
 ; CHECK:         .byte   0                       ; 0x0
-; CHECK:         .byte   2                       ; 0x2
-; CHECK:         .byte   31                      ; 0x1f
-; CHECK:         .byte   6                       ; 0x6
-; CHECK:         .byte   30                      ; 0x1e
-; CHECK:         .byte   10                      ; 0xa
-; CHECK:         .byte   12                      ; 0xc
-; CHECK:         .byte   14                      ; 0xe
+; CHECK:         .byte   0                       ; 0x0
+; CHECK:         .byte   0                       ; 0x0
+; CHECK:         .byte   0                       ; 0x0
+; CHECK:         .byte   0                       ; 0x0
+; CHECK:         .byte   0                       ; 0x0
+; CHECK:         .byte   0                       ; 0x0
+; CHECK:         .byte   0                       ; 0x0
+; CHECK:         .byte   0                       ; 0x0
+; CHECK:         .byte   0                       ; 0x0
+; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   0                       ; 0x0
 ; CHECK: _test4:
-; CHECK:         ldr     q[[REG1:[0-9]+]]
-; CHECK:         movi.2d v[[REG0:[0-9]+]], #0000000000000000
-; CHECK:         adrp    x[[REG3:[0-9]+]], lCPI3_1@PAGE
-; CHECK:         ldr     q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_1@PAGEOFF]
-; CHECK:         tbl.16b v{{[0-9]+}}, { v[[REG0]], v[[REG1]] }, v[[REG2]]
+; CHECK:         adrp    x[[REG3:[0-9]+]], lCPI3_0@PAGE
+; CHECK:         ldr     q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_0@PAGEOFF]
 define <16 x i1> @test4(i1* %ptr, i32 %v) {
 bb:
   %Shuff = shufflevector <16 x i1> zeroinitializer,
diff --git a/test/CodeGen/AArch64/arm64-vsqrt.ll b/test/CodeGen/AArch64/arm64-vsqrt.ll
index 02b7c7ec5d80..20aebd9cae36 100644
--- a/test/CodeGen/AArch64/arm64-vsqrt.ll
+++ b/test/CodeGen/AArch64/arm64-vsqrt.ll
@@ -3,8 +3,8 @@
 define <2 x float> @frecps_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: frecps_2s:
 ;CHECK: frecps.2s
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
@@ -12,8 +12,8 @@ define <2 x float> @frecps_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x float> @frecps_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: frecps_4s:
 ;CHECK: frecps.4s
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x float> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x float> @frecps_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x double> @frecps_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
 ;CHECK-LABEL: frecps_2d:
 ;CHECK: frecps.2d
-	%tmp1 = load <2 x double>* %A
-	%tmp2 = load <2 x double>* %B
+	%tmp1 = load <2 x double>, <2 x double>* %A
+	%tmp2 = load <2 x double>, <2 x double>* %B
 	%tmp3 = call <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
 	ret <2 x double> %tmp3
 }
@@ -35,8 +35,8 @@ declare <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double>, <2 x double>)
 define <2 x float> @frsqrts_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: frsqrts_2s:
 ;CHECK: frsqrts.2s
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.aarch64.neon.frsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
@@ -44,8 +44,8 @@ define <2 x float> @frsqrts_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x float> @frsqrts_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: frsqrts_4s:
 ;CHECK: frsqrts.4s
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x float> @llvm.aarch64.neon.frsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x float> %tmp3
 }
@@ -53,8 +53,8 @@ define <4 x float> @frsqrts_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x double> @frsqrts_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
 ;CHECK-LABEL: frsqrts_2d:
 ;CHECK: frsqrts.2d
-	%tmp1 = load <2 x double>* %A
-	%tmp2 = load <2 x double>* %B
+	%tmp1 = load <2 x double>, <2 x double>* %A
+	%tmp2 = load <2 x double>, <2 x double>* %B
 	%tmp3 = call <2 x double> @llvm.aarch64.neon.frsqrts.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
 	ret <2 x double> %tmp3
 }
@@ -66,7 +66,7 @@ declare <2 x double> @llvm.aarch64.neon.frsqrts.v2f64(<2 x double>, <2 x double>
 define <2 x float> @frecpe_2s(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: frecpe_2s:
 ;CHECK: frecpe.2s
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp3 = call <2 x float> @llvm.aarch64.neon.frecpe.v2f32(<2 x float> %tmp1)
 	ret <2 x float> %tmp3
 }
@@ -74,7 +74,7 @@ define <2 x float> @frecpe_2s(<2 x float>* %A) nounwind {
 define <4 x float> @frecpe_4s(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: frecpe_4s:
 ;CHECK: frecpe.4s
-	%tmp1 = load <4 x float>* %A
+	%tmp1 = load <4 x float>, <4 x float>* %A
 	%tmp3 = call <4 x float> @llvm.aarch64.neon.frecpe.v4f32(<4 x float> %tmp1)
 	ret <4 x float> %tmp3
 }
@@ -82,7 +82,7 @@ define <4 x float> @frecpe_4s(<4 x float>* %A) nounwind {
 define <2 x double> @frecpe_2d(<2 x double>* %A) nounwind {
 ;CHECK-LABEL: frecpe_2d:
 ;CHECK: frecpe.2d
-	%tmp1 = load <2 x double>* %A
+	%tmp1 = load <2 x double>, <2 x double>* %A
 	%tmp3 = call <2 x double> @llvm.aarch64.neon.frecpe.v2f64(<2 x double> %tmp1)
 	ret <2 x double> %tmp3
 }
@@ -90,7 +90,7 @@ define <2 x double> @frecpe_2d(<2 x double>* %A) nounwind {
 define float @frecpe_s(float* %A) nounwind {
 ;CHECK-LABEL: frecpe_s:
 ;CHECK: frecpe s0, {{s[0-9]+}}
-  %tmp1 = load float* %A
+  %tmp1 = load float, float* %A
   %tmp3 = call float @llvm.aarch64.neon.frecpe.f32(float %tmp1)
   ret float %tmp3
 }
@@ -98,7 +98,7 @@ define float @frecpe_s(float* %A) nounwind {
 define double @frecpe_d(double* %A) nounwind {
 ;CHECK-LABEL: frecpe_d:
 ;CHECK: frecpe d0, {{d[0-9]+}}
-  %tmp1 = load double* %A
+  %tmp1 = load double, double* %A
   %tmp3 = call double @llvm.aarch64.neon.frecpe.f64(double %tmp1)
   ret double %tmp3
 }
@@ -112,7 +112,7 @@ declare double @llvm.aarch64.neon.frecpe.f64(double) nounwind readnone
 define float @frecpx_s(float* %A) nounwind {
 ;CHECK-LABEL: frecpx_s:
 ;CHECK: frecpx s0, {{s[0-9]+}}
-  %tmp1 = load float* %A
+  %tmp1 = load float, float* %A
   %tmp3 = call float @llvm.aarch64.neon.frecpx.f32(float %tmp1)
   ret float %tmp3
 }
@@ -120,7 +120,7 @@ define float @frecpx_s(float* %A) nounwind {
 define double @frecpx_d(double* %A) nounwind {
 ;CHECK-LABEL: frecpx_d:
 ;CHECK: frecpx d0, {{d[0-9]+}}
-  %tmp1 = load double* %A
+  %tmp1 = load double, double* %A
   %tmp3 = call double @llvm.aarch64.neon.frecpx.f64(double %tmp1)
   ret double %tmp3
 }
@@ -131,7 +131,7 @@ declare double @llvm.aarch64.neon.frecpx.f64(double) nounwind readnone
 define <2 x float> @frsqrte_2s(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: frsqrte_2s:
 ;CHECK: frsqrte.2s
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp3 = call <2 x float> @llvm.aarch64.neon.frsqrte.v2f32(<2 x float> %tmp1)
 	ret <2 x float> %tmp3
 }
@@ -139,7 +139,7 @@ define <2 x float> @frsqrte_2s(<2 x float>* %A) nounwind {
 define <4 x float> @frsqrte_4s(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: frsqrte_4s:
 ;CHECK: frsqrte.4s
-	%tmp1 = load <4 x float>* %A
+	%tmp1 = load <4 x float>, <4 x float>* %A
 	%tmp3 = call <4 x float> @llvm.aarch64.neon.frsqrte.v4f32(<4 x float> %tmp1)
 	ret <4 x float> %tmp3
 }
@@ -147,7 +147,7 @@ define <4 x float> @frsqrte_4s(<4 x float>* %A) nounwind {
 define <2 x double> @frsqrte_2d(<2 x double>* %A) nounwind {
 ;CHECK-LABEL: frsqrte_2d:
 ;CHECK: frsqrte.2d
-	%tmp1 = load <2 x double>* %A
+	%tmp1 = load <2 x double>, <2 x double>* %A
 	%tmp3 = call <2 x double> @llvm.aarch64.neon.frsqrte.v2f64(<2 x double> %tmp1)
 	ret <2 x double> %tmp3
 }
@@ -155,7 +155,7 @@ define <2 x double> @frsqrte_2d(<2 x double>* %A) nounwind {
 define float @frsqrte_s(float* %A) nounwind {
 ;CHECK-LABEL: frsqrte_s:
 ;CHECK: frsqrte s0, {{s[0-9]+}}
-  %tmp1 = load float* %A
+  %tmp1 = load float, float* %A
   %tmp3 = call float @llvm.aarch64.neon.frsqrte.f32(float %tmp1)
   ret float %tmp3
 }
@@ -163,7 +163,7 @@ define float @frsqrte_s(float* %A) nounwind {
 define double @frsqrte_d(double* %A) nounwind {
 ;CHECK-LABEL: frsqrte_d:
 ;CHECK: frsqrte d0, {{d[0-9]+}}
-  %tmp1 = load double* %A
+  %tmp1 = load double, double* %A
   %tmp3 = call double @llvm.aarch64.neon.frsqrte.f64(double %tmp1)
   ret double %tmp3
 }
@@ -177,7 +177,7 @@ declare double @llvm.aarch64.neon.frsqrte.f64(double) nounwind readnone
 define <2 x i32> @urecpe_2s(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: urecpe_2s:
 ;CHECK: urecpe.2s
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.urecpe.v2i32(<2 x i32> %tmp1)
 	ret <2 x i32> %tmp3
 }
@@ -185,7 +185,7 @@ define <2 x i32> @urecpe_2s(<2 x i32>* %A) nounwind {
 define <4 x i32> @urecpe_4s(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: urecpe_4s:
 ;CHECK: urecpe.4s
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.urecpe.v4i32(<4 x i32> %tmp1)
 	ret <4 x i32> %tmp3
 }
@@ -196,7 +196,7 @@ declare <4 x i32> @llvm.aarch64.neon.urecpe.v4i32(<4 x i32>) nounwind readnone
 define <2 x i32> @ursqrte_2s(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: ursqrte_2s:
 ;CHECK: ursqrte.2s
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp3 = call <2 x i32> @llvm.aarch64.neon.ursqrte.v2i32(<2 x i32> %tmp1)
 	ret <2 x i32> %tmp3
 }
@@ -204,7 +204,7 @@ define <2 x i32> @ursqrte_2s(<2 x i32>* %A) nounwind {
 define <4 x i32> @ursqrte_4s(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: ursqrte_4s:
 ;CHECK: ursqrte.4s
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp3 = call <4 x i32> @llvm.aarch64.neon.ursqrte.v4i32(<4 x i32> %tmp1)
 	ret <4 x i32> %tmp3
 }
diff --git a/test/CodeGen/AArch64/arm64-vsra.ll b/test/CodeGen/AArch64/arm64-vsra.ll
index 5e9cef3e7e28..d480dfe1f7d8 100644
--- a/test/CodeGen/AArch64/arm64-vsra.ll
+++ b/test/CodeGen/AArch64/arm64-vsra.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsras8:
 ;CHECK: ssra.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = ashr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
         %tmp4 = add <8 x i8> %tmp1, %tmp3
 	ret <8 x i8> %tmp4
@@ -13,8 +13,8 @@ define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsras16:
 ;CHECK: ssra.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = ashr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
         %tmp4 = add <4 x i16> %tmp1, %tmp3
 	ret <4 x i16> %tmp4
@@ -23,8 +23,8 @@ define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsras32:
 ;CHECK: ssra.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = ashr <2 x i32> %tmp2, < i32 31, i32 31 >
         %tmp4 = add <2 x i32> %tmp1, %tmp3
 	ret <2 x i32> %tmp4
@@ -33,8 +33,8 @@ define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsraQs8:
 ;CHECK: ssra.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = ashr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
         %tmp4 = add <16 x i8> %tmp1, %tmp3
 	ret <16 x i8> %tmp4
@@ -43,8 +43,8 @@ define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsraQs16:
 ;CHECK: ssra.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = ashr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
         %tmp4 = add <8 x i16> %tmp1, %tmp3
 	ret <8 x i16> %tmp4
@@ -53,8 +53,8 @@ define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsraQs32:
 ;CHECK: ssra.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = ashr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
         %tmp4 = add <4 x i32> %tmp1, %tmp3
 	ret <4 x i32> %tmp4
@@ -63,8 +63,8 @@ define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vsraQs64:
 ;CHECK: ssra.2d
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = ashr <2 x i64> %tmp2, < i64 63, i64 63 >
         %tmp4 = add <2 x i64> %tmp1, %tmp3
 	ret <2 x i64> %tmp4
@@ -73,8 +73,8 @@ define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsrau8:
 ;CHECK: usra.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = lshr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
         %tmp4 = add <8 x i8> %tmp1, %tmp3
 	ret <8 x i8> %tmp4
@@ -83,8 +83,8 @@ define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsrau16:
 ;CHECK: usra.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = lshr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
         %tmp4 = add <4 x i16> %tmp1, %tmp3
 	ret <4 x i16> %tmp4
@@ -93,8 +93,8 @@ define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsrau32:
 ;CHECK: usra.2s
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = lshr <2 x i32> %tmp2, < i32 31, i32 31 >
         %tmp4 = add <2 x i32> %tmp1, %tmp3
 	ret <2 x i32> %tmp4
@@ -104,8 +104,8 @@ define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsraQu8:
 ;CHECK: usra.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = lshr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
         %tmp4 = add <16 x i8> %tmp1, %tmp3
 	ret <16 x i8> %tmp4
@@ -114,8 +114,8 @@ define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsraQu16:
 ;CHECK: usra.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = lshr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
         %tmp4 = add <8 x i16> %tmp1, %tmp3
 	ret <8 x i16> %tmp4
@@ -124,8 +124,8 @@ define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsraQu32:
 ;CHECK: usra.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = lshr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
         %tmp4 = add <4 x i32> %tmp1, %tmp3
 	ret <4 x i32> %tmp4
@@ -134,8 +134,8 @@ define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vsraQu64:
 ;CHECK: usra.2d
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = lshr <2 x i64> %tmp2, < i64 63, i64 63 >
         %tmp4 = add <2 x i64> %tmp1, %tmp3
 	ret <2 x i64> %tmp4
diff --git a/test/CodeGen/AArch64/arm64-vsub.ll b/test/CodeGen/AArch64/arm64-vsub.ll
index c2c8755c0669..6b44b56b7bf0 100644
--- a/test/CodeGen/AArch64/arm64-vsub.ll
+++ b/test/CodeGen/AArch64/arm64-vsub.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @subhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: subhn8b:
 ;CHECK: subhn.8b
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
         ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @subhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i16> @subhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: subhn4h:
 ;CHECK: subhn.4h
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.subhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
         ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @subhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i32> @subhn2s(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: subhn2s:
 ;CHECK: subhn.2s
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.subhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
         ret <2 x i32> %tmp3
 }
@@ -64,8 +64,8 @@ declare <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16>, <8 x i16>) nounwind re
 define <8 x i8> @rsubhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: rsubhn8b:
 ;CHECK: rsubhn.8b
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
         ret <8 x i8> %tmp3
 }
@@ -73,8 +73,8 @@ define <8 x i8> @rsubhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i16> @rsubhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: rsubhn4h:
 ;CHECK: rsubhn.4h
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i32>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
         ret <4 x i16> %tmp3
 }
@@ -82,8 +82,8 @@ define <4 x i16> @rsubhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i32> @rsubhn2s(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: rsubhn2s:
 ;CHECK: rsubhn.2s
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i64>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i64>, <2 x i64>* %B
         %tmp3 = call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
         ret <2 x i32> %tmp3
 }
@@ -125,8 +125,8 @@ declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind r
 define <8 x i16> @ssubl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: ssubl8h:
 ;CHECK: ssubl.8h
-        %tmp1 = load <8 x i8>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
   %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
   %tmp5 = sub <8 x i16> %tmp3, %tmp4
@@ -136,8 +136,8 @@ define <8 x i16> @ssubl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @ssubl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: ssubl4s:
 ;CHECK: ssubl.4s
-        %tmp1 = load <4 x i16>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
   %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
   %tmp5 = sub <4 x i32> %tmp3, %tmp4
@@ -147,8 +147,8 @@ define <4 x i32> @ssubl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @ssubl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: ssubl2d:
 ;CHECK: ssubl.2d
-        %tmp1 = load <2 x i32>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
   %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
   %tmp5 = sub <2 x i64> %tmp3, %tmp4
@@ -158,11 +158,11 @@ define <2 x i64> @ssubl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @ssubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: ssubl2_8h:
 ;CHECK: ssubl2.8h
-        %tmp1 = load <16 x i8>* %A
+        %tmp1 = load <16 x i8>, <16 x i8>* %A
         %high1 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         %ext1 = sext <8 x i8> %high1 to <8 x i16>
 
-        %tmp2 = load <16 x i8>* %B
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         %ext2 = sext <8 x i8> %high2 to <8 x i16>
 
@@ -173,11 +173,11 @@ define <8 x i16> @ssubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i32> @ssubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: ssubl2_4s:
 ;CHECK: ssubl2.4s
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %high1 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
         %ext1 = sext <4 x i16> %high1 to <4 x i32>
 
-        %tmp2 = load <8 x i16>* %B
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
         %ext2 = sext <4 x i16> %high2 to <4 x i32>
 
@@ -188,11 +188,11 @@ define <4 x i32> @ssubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i64> @ssubl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: ssubl2_2d:
 ;CHECK: ssubl2.2d
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %high1 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
         %ext1 = sext <2 x i32> %high1 to <2 x i64>
 
-        %tmp2 = load <4 x i32>* %B
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
         %ext2 = sext <2 x i32> %high2 to <2 x i64>
 
@@ -203,8 +203,8 @@ define <2 x i64> @ssubl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <8 x i16> @usubl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: usubl8h:
 ;CHECK: usubl.8h
-  %tmp1 = load <8 x i8>* %A
-  %tmp2 = load <8 x i8>* %B
+  %tmp1 = load <8 x i8>, <8 x i8>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
   %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
   %tmp5 = sub <8 x i16> %tmp3, %tmp4
@@ -214,8 +214,8 @@ define <8 x i16> @usubl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @usubl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: usubl4s:
 ;CHECK: usubl.4s
-  %tmp1 = load <4 x i16>* %A
-  %tmp2 = load <4 x i16>* %B
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
   %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
   %tmp5 = sub <4 x i32> %tmp3, %tmp4
@@ -225,8 +225,8 @@ define <4 x i32> @usubl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @usubl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: usubl2d:
 ;CHECK: usubl.2d
-  %tmp1 = load <2 x i32>* %A
-  %tmp2 = load <2 x i32>* %B
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
   %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
   %tmp5 = sub <2 x i64> %tmp3, %tmp4
@@ -236,11 +236,11 @@ define <2 x i64> @usubl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @usubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: usubl2_8h:
 ;CHECK: usubl2.8h
-  %tmp1 = load <16 x i8>* %A
+  %tmp1 = load <16 x i8>, <16 x i8>* %A
   %high1 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %ext1 = zext <8 x i8> %high1 to <8 x i16>
 
-  %tmp2 = load <16 x i8>* %B
+  %tmp2 = load <16 x i8>, <16 x i8>* %B
   %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %ext2 = zext <8 x i8> %high2 to <8 x i16>
 
@@ -251,11 +251,11 @@ define <8 x i16> @usubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i32> @usubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: usubl2_4s:
 ;CHECK: usubl2.4s
-  %tmp1 = load <8 x i16>* %A
+  %tmp1 = load <8 x i16>, <8 x i16>* %A
   %high1 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %ext1 = zext <4 x i16> %high1 to <4 x i32>
 
-  %tmp2 = load <8 x i16>* %B
+  %tmp2 = load <8 x i16>, <8 x i16>* %B
   %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %ext2 = zext <4 x i16> %high2 to <4 x i32>
 
@@ -266,11 +266,11 @@ define <4 x i32> @usubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i64> @usubl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: usubl2_2d:
 ;CHECK: usubl2.2d
-  %tmp1 = load <4 x i32>* %A
+  %tmp1 = load <4 x i32>, <4 x i32>* %A
   %high1 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %ext1 = zext <2 x i32> %high1 to <2 x i64>
 
-  %tmp2 = load <4 x i32>* %B
+  %tmp2 = load <4 x i32>, <4 x i32>* %B
   %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %ext2 = zext <2 x i32> %high2 to <2 x i64>
 
@@ -281,8 +281,8 @@ define <2 x i64> @usubl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <8 x i16> @ssubw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: ssubw8h:
 ;CHECK: ssubw.8h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
   %tmp4 = sub <8 x i16> %tmp1, %tmp3
         ret <8 x i16> %tmp4
@@ -291,8 +291,8 @@ define <8 x i16> @ssubw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @ssubw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: ssubw4s:
 ;CHECK: ssubw.4s
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
   %tmp4 = sub <4 x i32> %tmp1, %tmp3
         ret <4 x i32> %tmp4
@@ -301,8 +301,8 @@ define <4 x i32> @ssubw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @ssubw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: ssubw2d:
 ;CHECK: ssubw.2d
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
   %tmp4 = sub <2 x i64> %tmp1, %tmp3
         ret <2 x i64> %tmp4
@@ -311,9 +311,9 @@ define <2 x i64> @ssubw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @ssubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: ssubw2_8h:
 ;CHECK: ssubw2.8h
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
 
-        %tmp2 = load <16 x i8>* %B
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         %ext2 = sext <8 x i8> %high2 to <8 x i16>
 
@@ -324,9 +324,9 @@ define <8 x i16> @ssubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 define <4 x i32> @ssubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: ssubw2_4s:
 ;CHECK: ssubw2.4s
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
 
-        %tmp2 = load <8 x i16>* %B
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
         %ext2 = sext <4 x i16> %high2 to <4 x i32>
 
@@ -337,9 +337,9 @@ define <4 x i32> @ssubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 define <2 x i64> @ssubw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: ssubw2_2d:
 ;CHECK: ssubw2.2d
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
 
-        %tmp2 = load <4 x i32>* %B
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
         %ext2 = sext <2 x i32> %high2 to <2 x i64>
 
@@ -350,8 +350,8 @@ define <2 x i64> @ssubw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind {
 define <8 x i16> @usubw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: usubw8h:
 ;CHECK: usubw.8h
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i8>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
   %tmp4 = sub <8 x i16> %tmp1, %tmp3
         ret <8 x i16> %tmp4
@@ -360,8 +360,8 @@ define <8 x i16> @usubw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @usubw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: usubw4s:
 ;CHECK: usubw.4s
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i16>* %B
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
   %tmp4 = sub <4 x i32> %tmp1, %tmp3
         ret <4 x i32> %tmp4
@@ -370,8 +370,8 @@ define <4 x i32> @usubw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @usubw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: usubw2d:
 ;CHECK: usubw.2d
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i32>* %B
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
   %tmp4 = sub <2 x i64> %tmp1, %tmp3
         ret <2 x i64> %tmp4
@@ -380,9 +380,9 @@ define <2 x i64> @usubw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @usubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: usubw2_8h:
 ;CHECK: usubw2.8h
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
 
-        %tmp2 = load <16 x i8>* %B
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         %ext2 = zext <8 x i8> %high2 to <8 x i16>
 
@@ -393,9 +393,9 @@ define <8 x i16> @usubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 define <4 x i32> @usubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: usubw2_4s:
 ;CHECK: usubw2.4s
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
 
-        %tmp2 = load <8 x i16>* %B
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
         %ext2 = zext <4 x i16> %high2 to <4 x i32>
 
@@ -406,9 +406,9 @@ define <4 x i32> @usubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 define <2 x i64> @usubw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: usubw2_2d:
 ;CHECK: usubw2.2d
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
 
-        %tmp2 = load <4 x i32>* %B
+        %tmp2 = load <4 x i32>, <4 x i32>* %B
         %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
         %ext2 = zext <2 x i32> %high2 to <2 x i64>
 
diff --git a/test/CodeGen/AArch64/arm64-weak-reference.ll b/test/CodeGen/AArch64/arm64-weak-reference.ll
index b2135e0960cb..e8074def4e6e 100644
--- a/test/CodeGen/AArch64/arm64-weak-reference.ll
+++ b/test/CodeGen/AArch64/arm64-weak-reference.ll
@@ -5,6 +5,6 @@
 define i32 @fn() nounwind ssp {
 ; CHECK-LABEL: fn:
 ; CHECK: .weak_reference
-  %val = load i32* @x, align 4
+  %val = load i32, i32* @x, align 4
   ret i32 %val
 }
diff --git a/test/CodeGen/AArch64/arm64-xaluo.ll b/test/CodeGen/AArch64/arm64-xaluo.ll
index 59ce6848afb9..ce9c0a64b587 100644
--- a/test/CodeGen/AArch64/arm64-xaluo.ll
+++ b/test/CodeGen/AArch64/arm64-xaluo.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0                             -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 ;
 ; Get the actual value of the overflow bit.
diff --git a/test/CodeGen/AArch64/arm64-zextload-unscaled.ll b/test/CodeGen/AArch64/arm64-zextload-unscaled.ll
index c475dbd21eee..321cf10fe45c 100644
--- a/test/CodeGen/AArch64/arm64-zextload-unscaled.ll
+++ b/test/CodeGen/AArch64/arm64-zextload-unscaled.ll
@@ -6,8 +6,8 @@ define void @test_zextloadi1_unscaled(i1* %base) {
 ; CHECK-LABEL: test_zextloadi1_unscaled:
 ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7]
 
-  %addr = getelementptr i1* %base, i32 -7
-  %val = load i1* %addr, align 1
+  %addr = getelementptr i1, i1* %base, i32 -7
+  %val = load i1, i1* %addr, align 1
 
   %extended = zext i1 %val to i32
   store i32 %extended, i32* @var32, align 4
@@ -18,8 +18,8 @@ define void @test_zextloadi8_unscaled(i8* %base) {
 ; CHECK-LABEL: test_zextloadi8_unscaled:
 ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7]
 
-  %addr = getelementptr i8* %base, i32 -7
-  %val = load i8* %addr, align 1
+  %addr = getelementptr i8, i8* %base, i32 -7
+  %val = load i8, i8* %addr, align 1
 
   %extended = zext i8 %val to i32
   store i32 %extended, i32* @var32, align 4
@@ -30,8 +30,8 @@ define void @test_zextloadi16_unscaled(i16* %base) {
 ; CHECK-LABEL: test_zextloadi16_unscaled:
 ; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #-14]
 
-  %addr = getelementptr i16* %base, i32 -7
-  %val = load i16* %addr, align 2
+  %addr = getelementptr i16, i16* %base, i32 -7
+  %val = load i16, i16* %addr, align 2
 
   %extended = zext i16 %val to i32
   store i32 %extended, i32* @var32, align 4
diff --git a/test/CodeGen/AArch64/arm64-zip.ll b/test/CodeGen/AArch64/arm64-zip.ll
index 304b28099432..ddce002c25db 100644
--- a/test/CodeGen/AArch64/arm64-zip.ll
+++ b/test/CodeGen/AArch64/arm64-zip.ll
@@ -5,8 +5,8 @@ define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: zip1.8b
 ;CHECK: zip2.8b
 ;CHECK-NEXT: add.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
 	%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
         %tmp5 = add <8 x i8> %tmp3, %tmp4
@@ -18,8 +18,8 @@ define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: zip1.4h
 ;CHECK: zip2.4h
 ;CHECK-NEXT: add.4h
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
 	%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
         %tmp5 = add <4 x i16> %tmp3, %tmp4
@@ -31,8 +31,8 @@ define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK: zip1.16b
 ;CHECK: zip2.16b
 ;CHECK-NEXT: add.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
 	%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
         %tmp5 = add <16 x i8> %tmp3, %tmp4
@@ -44,8 +44,8 @@ define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK: zip1.8h
 ;CHECK: zip2.8h
 ;CHECK-NEXT: add.8h
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
 	%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
         %tmp5 = add <8 x i16> %tmp3, %tmp4
@@ -57,8 +57,8 @@ define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK: zip1.4s
 ;CHECK: zip2.4s
 ;CHECK-NEXT: add.4s
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
 	%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
         %tmp5 = add <4 x i32> %tmp3, %tmp4
@@ -70,8 +70,8 @@ define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK: zip1.4s
 ;CHECK: zip2.4s
 ;CHECK-NEXT: fadd.4s
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
 	%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
         %tmp5 = fadd <4 x float> %tmp3, %tmp4
@@ -85,8 +85,8 @@ define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: zip1.8b
 ;CHECK: zip2.8b
 ;CHECK-NEXT: add.8b
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11>
 	%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15>
         %tmp5 = add <8 x i8> %tmp3, %tmp4
@@ -98,8 +98,8 @@ define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK: zip1.16b
 ;CHECK: zip2.16b
 ;CHECK-NEXT: add.16b
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
 	%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31>
         %tmp5 = add <16 x i8> %tmp3, %tmp4
diff --git a/test/CodeGen/AArch64/assertion-rc-mismatch.ll b/test/CodeGen/AArch64/assertion-rc-mismatch.ll
index bcf206ec9bed..c216c448e11b 100644
--- a/test/CodeGen/AArch64/assertion-rc-mismatch.ll
+++ b/test/CodeGen/AArch64/assertion-rc-mismatch.ll
@@ -11,8 +11,8 @@ if:
   br label %end
 else:
   %tmp3 = call i8* @llvm.returnaddress(i32 0)
-  %ptr = getelementptr inbounds i8* %tmp3, i64 -16
-  %ld = load i8* %ptr, align 4
+  %ptr = getelementptr inbounds i8, i8* %tmp3, i64 -16
+  %ld = load i8, i8* %ptr, align 4
   %tmp2 = inttoptr i8 %ld to i8*
   br label %end
 end:
diff --git a/test/CodeGen/AArch64/atomic-ops-not-barriers.ll b/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
index da095a0a42c5..44e777161e8e 100644
--- a/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
+++ b/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
@@ -4,7 +4,7 @@ define i32 @foo(i32* %var, i1 %cond) {
 ; CHECK-LABEL: foo:
   br i1 %cond, label %atomic_ver, label %simple_ver
 simple_ver:
-  %oldval = load i32* %var
+  %oldval = load i32, i32* %var
   %newval = add nsw i32 %oldval, -1
   store i32 %newval, i32* %var
   br label %somewhere
diff --git a/test/CodeGen/AArch64/atomic-ops.ll b/test/CodeGen/AArch64/atomic-ops.ll
index ef209e9c6e5b..cb90caeadc1f 100644
--- a/test/CodeGen/AArch64/atomic-ops.ll
+++ b/test/CodeGen/AArch64/atomic-ops.ll
@@ -972,7 +972,7 @@ define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
 
 define i8 @test_atomic_load_monotonic_i8() nounwind {
 ; CHECK-LABEL: test_atomic_load_monotonic_i8:
-  %val = load atomic i8* @var8 monotonic, align 1
+  %val = load atomic i8, i8* @var8 monotonic, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp x[[HIADDR:[0-9]+]], var8
 ; CHECK: ldrb w0, [x[[HIADDR]], {{#?}}:lo12:var8]
@@ -986,7 +986,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i8*
 
-  %val = load atomic i8* %addr monotonic, align 1
+  %val = load atomic i8, i8* %addr monotonic, align 1
 ; CHECK-NOT: dmb
 ; CHECK: ldrb w0, [x0, x1]
 ; CHECK-NOT: dmb
@@ -996,7 +996,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
 
 define i8 @test_atomic_load_acquire_i8() nounwind {
 ; CHECK-LABEL: test_atomic_load_acquire_i8:
-  %val = load atomic i8* @var8 acquire, align 1
+  %val = load atomic i8, i8* @var8 acquire, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK-NOT: dmb
@@ -1009,7 +1009,7 @@ define i8 @test_atomic_load_acquire_i8() nounwind {
 
 define i8 @test_atomic_load_seq_cst_i8() nounwind {
 ; CHECK-LABEL: test_atomic_load_seq_cst_i8:
-  %val = load atomic i8* @var8 seq_cst, align 1
+  %val = load atomic i8, i8* @var8 seq_cst, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var8
 ; CHECK-NOT: dmb
@@ -1022,7 +1022,7 @@ define i8 @test_atomic_load_seq_cst_i8() nounwind {
 
 define i16 @test_atomic_load_monotonic_i16() nounwind {
 ; CHECK-LABEL: test_atomic_load_monotonic_i16:
-  %val = load atomic i16* @var16 monotonic, align 2
+  %val = load atomic i16, i16* @var16 monotonic, align 2
 ; CHECK-NOT: dmb
 ; CHECK: adrp x[[HIADDR:[0-9]+]], var16
 ; CHECK-NOT: dmb
@@ -1037,7 +1037,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i32*
 
-  %val = load atomic i32* %addr monotonic, align 4
+  %val = load atomic i32, i32* %addr monotonic, align 4
 ; CHECK-NOT: dmb
 ; CHECK: ldr w0, [x0, x1]
 ; CHECK-NOT: dmb
@@ -1047,7 +1047,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind
 
 define i64 @test_atomic_load_seq_cst_i64() nounwind {
 ; CHECK-LABEL: test_atomic_load_seq_cst_i64:
-  %val = load atomic i64* @var64 seq_cst, align 8
+  %val = load atomic i64, i64* @var64 seq_cst, align 8
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var64
 ; CHECK-NOT: dmb
diff --git a/test/CodeGen/AArch64/basic-pic.ll b/test/CodeGen/AArch64/basic-pic.ll
index 62d41bcead6b..8765a6d1267c 100644
--- a/test/CodeGen/AArch64/basic-pic.ll
+++ b/test/CodeGen/AArch64/basic-pic.ll
@@ -5,7 +5,7 @@
 define i32 @get_globalvar() {
 ; CHECK-LABEL: get_globalvar:
 
-  %val = load i32* @var
+  %val = load i32, i32* @var
 ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
 ; CHECK: ldr x[[GOTLOC:[0-9]+]], [x[[GOTHI]], {{#?}}:got_lo12:var]
 ; CHECK: ldr w0, [x[[GOTLOC]]]
@@ -16,7 +16,7 @@ define i32 @get_globalvar() {
 define i32* @get_globalvaraddr() {
 ; CHECK-LABEL: get_globalvaraddr:
 
-  %val = load i32* @var
+  %val = load i32, i32* @var
 ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
 ; CHECK: ldr x0, [x[[GOTHI]], {{#?}}:got_lo12:var]
 
@@ -28,7 +28,7 @@ define i32* @get_globalvaraddr() {
 define i32 @get_hiddenvar() {
 ; CHECK-LABEL: get_hiddenvar:
 
-  %val = load i32* @hiddenvar
+  %val = load i32, i32* @hiddenvar
 ; CHECK: adrp x[[HI:[0-9]+]], hiddenvar
 ; CHECK: ldr w0, [x[[HI]], {{#?}}:lo12:hiddenvar]
 
@@ -38,7 +38,7 @@ define i32 @get_hiddenvar() {
 define i32* @get_hiddenvaraddr() {
 ; CHECK-LABEL: get_hiddenvaraddr:
 
-  %val = load i32* @hiddenvar
+  %val = load i32, i32* @hiddenvar
 ; CHECK: adrp [[HI:x[0-9]+]], hiddenvar
 ; CHECK: add x0, [[HI]], {{#?}}:lo12:hiddenvar
 
diff --git a/test/CodeGen/AArch64/bitcast.ll b/test/CodeGen/AArch64/bitcast.ll
new file mode 100644
index 000000000000..e88ea9ec0213
--- /dev/null
+++ b/test/CodeGen/AArch64/bitcast.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -mtriple=aarch64--linux-gnu | FileCheck %s
+
+; PR23065: SCALAR_TO_VECTOR implies the top elements 1 to N-1 of the N-element vector are undefined.
+
+define <4 x i16> @foo1(<2 x i32> %a) {
+; CHECK-LABEL: foo1:
+; CHECK:       movi	d0, #0000000000000000
+; CHECK-NEXT:  ret
+
+  %1 = shufflevector <2 x i32> <i32 58712, i32 undef>, <2 x i32> %a, <2 x i32> <i32 0, i32 2>
+; Can't optimize the following bitcast to scalar_to_vector.
+  %2 = bitcast <2 x i32> %1 to <4 x i16>
+  %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+  ret <4 x i16> %3
+}
+
+define <4 x i16> @foo2(<2 x i32> %a) {
+; CHECK-LABEL: foo2:
+; CHECK:       movi	d0, #0000000000000000
+; CHECK-NEXT:  ret
+
+  %1 = shufflevector <2 x i32> <i32 712, i32 undef>, <2 x i32> %a, <2 x i32> <i32 0, i32 2>
+; Can't optimize the following bitcast to scalar_to_vector.
+  %2 = bitcast <2 x i32> %1 to <4 x i16>
+  %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+  ret <4 x i16> %3
+}
diff --git a/test/CodeGen/AArch64/bitfield-insert-0.ll b/test/CodeGen/AArch64/bitfield-insert-0.ll
index da0ed8af3126..21f3895154c7 100644
--- a/test/CodeGen/AArch64/bitfield-insert-0.ll
+++ b/test/CodeGen/AArch64/bitfield-insert-0.ll
@@ -6,10 +6,10 @@
 define void @test_bfi0(i32* %existing, i32* %new) {
 ; CHECK: bfxil {{w[0-9]+}}, {{w[0-9]+}}, #0, #18
 
-  %oldval = load volatile i32* %existing
+  %oldval = load volatile i32, i32* %existing
   %oldval_keep = and i32 %oldval, 4294705152 ; 0xfffc_0000
 
-  %newval = load volatile i32* %new
+  %newval = load volatile i32, i32* %new
   %newval_masked = and i32 %newval, 262143 ; = 0x0003_ffff
 
   %combined = or i32 %newval_masked, %oldval_keep
diff --git a/test/CodeGen/AArch64/bitfield-insert.ll b/test/CodeGen/AArch64/bitfield-insert.ll
index 2369a55aa92d..9b731fa72a47 100644
--- a/test/CodeGen/AArch64/bitfield-insert.ll
+++ b/test/CodeGen/AArch64/bitfield-insert.ll
@@ -28,10 +28,10 @@ define void @test_whole32(i32* %existing, i32* %new) {
 
 ; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #26, #5
 
-  %oldval = load volatile i32* %existing
+  %oldval = load volatile i32, i32* %existing
   %oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff
 
-  %newval = load volatile i32* %new
+  %newval = load volatile i32, i32* %new
   %newval_shifted = shl i32 %newval, 26
   %newval_masked = and i32 %newval_shifted, 2080374784 ; = 0x7c000000
 
@@ -47,10 +47,10 @@ define void @test_whole64(i64* %existing, i64* %new) {
 ; CHECK-NOT: and
 ; CHECK: ret
 
-  %oldval = load volatile i64* %existing
+  %oldval = load volatile i64, i64* %existing
   %oldval_keep = and i64 %oldval, 18446742974265032703 ; = 0xffffff0003ffffffL
 
-  %newval = load volatile i64* %new
+  %newval = load volatile i64, i64* %new
   %newval_shifted = shl i64 %newval, 26
   %newval_masked = and i64 %newval_shifted, 1099444518912 ; = 0xfffc000000
 
@@ -68,10 +68,10 @@ define void @test_whole32_from64(i64* %existing, i64* %new) {
 
 ; CHECK: ret
 
-  %oldval = load volatile i64* %existing
+  %oldval = load volatile i64, i64* %existing
   %oldval_keep = and i64 %oldval, 4294901760 ; = 0xffff0000
 
-  %newval = load volatile i64* %new
+  %newval = load volatile i64, i64* %new
   %newval_masked = and i64 %newval, 65535 ; = 0xffff
 
   %combined = or i64 %oldval_keep, %newval_masked
@@ -86,10 +86,10 @@ define void @test_32bit_masked(i32 *%existing, i32 *%new) {
 ; CHECK: and
 ; CHECK: bfi [[INSERT:w[0-9]+]], {{w[0-9]+}}, #3, #4
 
-  %oldval = load volatile i32* %existing
+  %oldval = load volatile i32, i32* %existing
   %oldval_keep = and i32 %oldval, 135 ; = 0x87
 
-  %newval = load volatile i32* %new
+  %newval = load volatile i32, i32* %new
   %newval_shifted = shl i32 %newval, 3
   %newval_masked = and i32 %newval_shifted, 120 ; = 0x78
 
@@ -104,10 +104,10 @@ define void @test_64bit_masked(i64 *%existing, i64 *%new) {
 ; CHECK: and
 ; CHECK: bfi [[INSERT:x[0-9]+]], {{x[0-9]+}}, #40, #8
 
-  %oldval = load volatile i64* %existing
+  %oldval = load volatile i64, i64* %existing
   %oldval_keep = and i64 %oldval, 1095216660480 ; = 0xff_0000_0000
 
-  %newval = load volatile i64* %new
+  %newval = load volatile i64, i64* %new
   %newval_shifted = shl i64 %newval, 40
   %newval_masked = and i64 %newval_shifted, 280375465082880 ; = 0xff00_0000_0000
 
@@ -124,10 +124,10 @@ define void @test_32bit_complexmask(i32 *%existing, i32 *%new) {
 ; CHECK: and
 ; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4
 
-  %oldval = load volatile i32* %existing
+  %oldval = load volatile i32, i32* %existing
   %oldval_keep = and i32 %oldval, 647 ; = 0x287
 
-  %newval = load volatile i32* %new
+  %newval = load volatile i32, i32* %new
   %newval_shifted = shl i32 %newval, 3
   %newval_masked = and i32 %newval_shifted, 120 ; = 0x278
 
@@ -144,10 +144,10 @@ define void @test_32bit_badmask(i32 *%existing, i32 *%new) {
 ; CHECK-NOT: bfm
 ; CHECK: ret
 
-  %oldval = load volatile i32* %existing
+  %oldval = load volatile i32, i32* %existing
   %oldval_keep = and i32 %oldval, 135 ; = 0x87
 
-  %newval = load volatile i32* %new
+  %newval = load volatile i32, i32* %new
   %newval_shifted = shl i32 %newval, 3
   %newval_masked = and i32 %newval_shifted, 632 ; = 0x278
 
@@ -164,10 +164,10 @@ define void @test_64bit_badmask(i64 *%existing, i64 *%new) {
 ; CHECK-NOT: bfm
 ; CHECK: ret
 
-  %oldval = load volatile i64* %existing
+  %oldval = load volatile i64, i64* %existing
   %oldval_keep = and i64 %oldval, 135 ; = 0x87
 
-  %newval = load volatile i64* %new
+  %newval = load volatile i64, i64* %new
   %newval_shifted = shl i64 %newval, 3
   %newval_masked = and i64 %newval_shifted, 664 ; = 0x278
 
@@ -182,10 +182,10 @@ define void @test_64bit_badmask(i64 *%existing, i64 *%new) {
 define void @test_32bit_with_shr(i32* %existing, i32* %new) {
 ; CHECK-LABEL: test_32bit_with_shr:
 
-  %oldval = load volatile i32* %existing
+  %oldval = load volatile i32, i32* %existing
   %oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff
 
-  %newval = load i32* %new
+  %newval = load i32, i32* %new
   %newval_shifted = shl i32 %newval, 12
   %newval_masked = and i32 %newval_shifted, 2080374784 ; = 0x7c000000
 
diff --git a/test/CodeGen/AArch64/bitfield.ll b/test/CodeGen/AArch64/bitfield.ll
index 0e1265372bd8..78399c80b5de 100644
--- a/test/CodeGen/AArch64/bitfield.ll
+++ b/test/CodeGen/AArch64/bitfield.ll
@@ -180,7 +180,7 @@ define i32 @test_ubfx32(i32* %addr) {
 ; CHECK-LABEL: test_ubfx32:
 ; CHECK: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #23, #3
 
-   %fields = load i32* %addr
+   %fields = load i32, i32* %addr
    %shifted = lshr i32 %fields, 23
    %masked = and i32 %shifted, 7
    ret i32 %masked
@@ -189,7 +189,7 @@ define i32 @test_ubfx32(i32* %addr) {
 define i64 @test_ubfx64(i64* %addr) {
 ; CHECK-LABEL: test_ubfx64:
 ; CHECK: ubfx {{x[0-9]+}}, {{x[0-9]+}}, #25, #10
-   %fields = load i64* %addr
+   %fields = load i64, i64* %addr
    %shifted = lshr i64 %fields, 25
    %masked = and i64 %shifted, 1023
    ret i64 %masked
@@ -199,7 +199,7 @@ define i32 @test_sbfx32(i32* %addr) {
 ; CHECK-LABEL: test_sbfx32:
 ; CHECK: sbfx {{w[0-9]+}}, {{w[0-9]+}}, #6, #3
 
-   %fields = load i32* %addr
+   %fields = load i32, i32* %addr
    %shifted = shl i32 %fields, 23
    %extended = ashr i32 %shifted, 29
    ret i32 %extended
@@ -209,7 +209,7 @@ define i64 @test_sbfx64(i64* %addr) {
 ; CHECK-LABEL: test_sbfx64:
 ; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #63
 
-   %fields = load i64* %addr
+   %fields = load i64, i64* %addr
    %shifted = shl i64 %fields, 1
    %extended = ashr i64 %shifted, 1
    ret i64 %extended
diff --git a/test/CodeGen/AArch64/blockaddress.ll b/test/CodeGen/AArch64/blockaddress.ll
index 3a5dbdc945ca..e93c69fd3ea3 100644
--- a/test/CodeGen/AArch64/blockaddress.ll
+++ b/test/CodeGen/AArch64/blockaddress.ll
@@ -6,7 +6,7 @@
 define void @test_blockaddress() {
 ; CHECK-LABEL: test_blockaddress:
   store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr
-  %val = load volatile i8** @addr
+  %val = load volatile i8*, i8** @addr
   indirectbr i8* %val, [label %block]
 ; CHECK: adrp [[DEST_HI:x[0-9]+]], [[DEST_LBL:.Ltmp[0-9]+]]
 ; CHECK: add [[DEST:x[0-9]+]], [[DEST_HI]], {{#?}}:lo12:[[DEST_LBL]]
diff --git a/test/CodeGen/AArch64/bool-loads.ll b/test/CodeGen/AArch64/bool-loads.ll
index 881aeaa15dd5..b0ee1b4aec54 100644
--- a/test/CodeGen/AArch64/bool-loads.ll
+++ b/test/CodeGen/AArch64/bool-loads.ll
@@ -5,7 +5,7 @@
 define i32 @test_sextloadi32() {
 ; CHECK-LABEL: test_sextloadi32
 
-  %val = load i1* @var
+  %val = load i1, i1* @var
   %ret = sext i1 %val to i32
 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
 ; CHECK: {{sbfx x[0-9]+, x[0-9]+, #0, #1|sbfx w[0-9]+, w[0-9]+, #0, #1}}
@@ -17,7 +17,7 @@ define i32 @test_sextloadi32() {
 define i64 @test_sextloadi64() {
 ; CHECK-LABEL: test_sextloadi64
 
-  %val = load i1* @var
+  %val = load i1, i1* @var
   %ret = sext i1 %val to i64
 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
 ; CHECK: {{sbfx x[0-9]+, x[0-9]+, #0, #1}}
@@ -32,7 +32,7 @@ define i32 @test_zextloadi32() {
 ; It's not actually necessary that "ret" is next, but as far as LLVM
 ; is concerned only 0 or 1 should be loadable so no extension is
 ; necessary.
-  %val = load i1* @var
+  %val = load i1, i1* @var
   %ret = zext i1 %val to i32
 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
 
@@ -46,7 +46,7 @@ define i64 @test_zextloadi64() {
 ; It's not actually necessary that "ret" is next, but as far as LLVM
 ; is concerned only 0 or 1 should be loadable so no extension is
 ; necessary.
-  %val = load i1* @var
+  %val = load i1, i1* @var
   %ret = zext i1 %val to i64
 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
 
diff --git a/test/CodeGen/AArch64/br-to-eh-lpad.ll b/test/CodeGen/AArch64/br-to-eh-lpad.ll
index 20bffd9e4129..f304ba4ca286 100644
--- a/test/CodeGen/AArch64/br-to-eh-lpad.ll
+++ b/test/CodeGen/AArch64/br-to-eh-lpad.ll
@@ -30,12 +30,12 @@ invoke.cont7:
   unreachable
 
 if.end50.thread:
-  tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str1, i64 0, i64 0), i32 125)
-  tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str1, i64 0, i64 0), i32 128)
+  tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 125)
+  tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 128)
   unreachable
 
 invoke.cont33:
-  tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str1, i64 0, i64 0), i32 119)
+  tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 119)
   unreachable
 
 invoke.cont41:
@@ -51,7 +51,7 @@ lpad40:
   br label %finally.catchall
 
 finally.catchall:
-  tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str1, i64 0, i64 0), i32 125)
+  tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 125)
   unreachable
 }
 
diff --git a/test/CodeGen/AArch64/breg.ll b/test/CodeGen/AArch64/breg.ll
index 952404495ce5..42061a851db2 100644
--- a/test/CodeGen/AArch64/breg.ll
+++ b/test/CodeGen/AArch64/breg.ll
@@ -4,7 +4,7 @@
 
 define void @foo() {
 ; CHECK-LABEL: foo:
-  %lab = load i8** @stored_label
+  %lab = load i8*, i8** @stored_label
   indirectbr i8* %lab, [label  %otherlab, label %retlab]
 ; CHECK: adrp {{x[0-9]+}}, stored_label
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:stored_label]
diff --git a/test/CodeGen/AArch64/callee-save.ll b/test/CodeGen/AArch64/callee-save.ll
index 046e6ceac077..123403988d44 100644
--- a/test/CodeGen/AArch64/callee-save.ll
+++ b/test/CodeGen/AArch64/callee-save.ll
@@ -12,38 +12,38 @@ define void @foo() {
 
   ; Create lots of live variables to exhaust the supply of
   ; caller-saved registers
-  %val1 = load volatile float* @var
-  %val2 = load volatile float* @var
-  %val3 = load volatile float* @var
-  %val4 = load volatile float* @var
-  %val5 = load volatile float* @var
-  %val6 = load volatile float* @var
-  %val7 = load volatile float* @var
-  %val8 = load volatile float* @var
-  %val9 = load volatile float* @var
-  %val10 = load volatile float* @var
-  %val11 = load volatile float* @var
-  %val12 = load volatile float* @var
-  %val13 = load volatile float* @var
-  %val14 = load volatile float* @var
-  %val15 = load volatile float* @var
-  %val16 = load volatile float* @var
-  %val17 = load volatile float* @var
-  %val18 = load volatile float* @var
-  %val19 = load volatile float* @var
-  %val20 = load volatile float* @var
-  %val21 = load volatile float* @var
-  %val22 = load volatile float* @var
-  %val23 = load volatile float* @var
-  %val24 = load volatile float* @var
-  %val25 = load volatile float* @var
-  %val26 = load volatile float* @var
-  %val27 = load volatile float* @var
-  %val28 = load volatile float* @var
-  %val29 = load volatile float* @var
-  %val30 = load volatile float* @var
-  %val31 = load volatile float* @var
-  %val32 = load volatile float* @var
+  %val1 = load volatile float, float* @var
+  %val2 = load volatile float, float* @var
+  %val3 = load volatile float, float* @var
+  %val4 = load volatile float, float* @var
+  %val5 = load volatile float, float* @var
+  %val6 = load volatile float, float* @var
+  %val7 = load volatile float, float* @var
+  %val8 = load volatile float, float* @var
+  %val9 = load volatile float, float* @var
+  %val10 = load volatile float, float* @var
+  %val11 = load volatile float, float* @var
+  %val12 = load volatile float, float* @var
+  %val13 = load volatile float, float* @var
+  %val14 = load volatile float, float* @var
+  %val15 = load volatile float, float* @var
+  %val16 = load volatile float, float* @var
+  %val17 = load volatile float, float* @var
+  %val18 = load volatile float, float* @var
+  %val19 = load volatile float, float* @var
+  %val20 = load volatile float, float* @var
+  %val21 = load volatile float, float* @var
+  %val22 = load volatile float, float* @var
+  %val23 = load volatile float, float* @var
+  %val24 = load volatile float, float* @var
+  %val25 = load volatile float, float* @var
+  %val26 = load volatile float, float* @var
+  %val27 = load volatile float, float* @var
+  %val28 = load volatile float, float* @var
+  %val29 = load volatile float, float* @var
+  %val30 = load volatile float, float* @var
+  %val31 = load volatile float, float* @var
+  %val32 = load volatile float, float* @var
 
   store volatile float %val1, float* @var
   store volatile float %val2, float* @var
diff --git a/test/CodeGen/AArch64/cmpwithshort.ll b/test/CodeGen/AArch64/cmpwithshort.ll
index 14efdcc9d188..65909974af73 100644
--- a/test/CodeGen/AArch64/cmpwithshort.ll
+++ b/test/CodeGen/AArch64/cmpwithshort.ll
@@ -5,8 +5,8 @@ define i16 @test_1cmp_signed_1(i16* %ptr1) {
 ; CHECK: ldrsh
 ; CHECK-NEXT: cmn
 entry:
-  %addr = getelementptr inbounds i16* %ptr1, i16 0
-  %val = load i16* %addr, align 2
+  %addr = getelementptr inbounds i16, i16* %ptr1, i16 0
+  %val = load i16, i16* %addr, align 2
   %cmp = icmp eq i16 %val, -1
   br i1 %cmp, label %if, label %if.then
 if:
@@ -20,8 +20,8 @@ define i16 @test_1cmp_signed_2(i16* %ptr1) {
 ; CHECK: ldrsh
 ; CHECK-NEXT: cmn
 entry:
-  %addr = getelementptr inbounds i16* %ptr1, i16 0
-  %val = load i16* %addr, align 2
+  %addr = getelementptr inbounds i16, i16* %ptr1, i16 0
+  %val = load i16, i16* %addr, align 2
   %cmp = icmp sge i16 %val, -1
   br i1 %cmp, label %if, label %if.then
 if:
@@ -35,8 +35,8 @@ define i16 @test_1cmp_unsigned_1(i16* %ptr1) {
 ; CHECK: ldrsh
 ; CHECK-NEXT: cmn
 entry:
-  %addr = getelementptr inbounds i16* %ptr1, i16 0
-  %val = load i16* %addr, align 2
+  %addr = getelementptr inbounds i16, i16* %ptr1, i16 0
+  %val = load i16, i16* %addr, align 2
   %cmp = icmp uge i16 %val, -1
   br i1 %cmp, label %if, label %if.then
 if:
diff --git a/test/CodeGen/AArch64/code-model-large-abs.ll b/test/CodeGen/AArch64/code-model-large-abs.ll
index ca92500855b4..1680815d93ea 100644
--- a/test/CodeGen/AArch64/code-model-large-abs.ll
+++ b/test/CodeGen/AArch64/code-model-large-abs.ll
@@ -18,7 +18,7 @@ define i8* @global_addr() {
 
 define i8 @global_i8() {
 ; CHECK-LABEL: global_i8:
-  %val = load i8* @var8
+  %val = load i8, i8* @var8
   ret i8 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
@@ -29,7 +29,7 @@ define i8 @global_i8() {
 
 define i16 @global_i16() {
 ; CHECK-LABEL: global_i16:
-  %val = load i16* @var16
+  %val = load i16, i16* @var16
   ret i16 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
@@ -40,7 +40,7 @@ define i16 @global_i16() {
 
 define i32 @global_i32() {
 ; CHECK-LABEL: global_i32:
-  %val = load i32* @var32
+  %val = load i32, i32* @var32
   ret i32 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
@@ -51,7 +51,7 @@ define i32 @global_i32() {
 
 define i64 @global_i64() {
 ; CHECK-LABEL: global_i64:
-  %val = load i64* @var64
+  %val = load i64, i64* @var64
   ret i64 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
diff --git a/test/CodeGen/AArch64/combine-comparisons-by-cse.ll b/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
index df8dc87176cc..c78fabac6187 100644
--- a/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
+++ b/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
@@ -15,13 +15,13 @@ define i32 @combine_gt_ge_10() #0 {
 ; CHECK-NOT: cmp
 ; CHECK: b.lt
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp sgt i32 %0, 10
   br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
 
 land.lhs.true:                                    ; preds = %entry
-  %1 = load i32* @b, align 4
-  %2 = load i32* @c, align 4
+  %1 = load i32, i32* @b, align 4
+  %2 = load i32, i32* @c, align 4
   %cmp1 = icmp eq i32 %1, %2
   br i1 %cmp1, label %return, label %land.lhs.true3
 
@@ -30,8 +30,8 @@ lor.lhs.false:                                    ; preds = %entry
   br i1 %cmp2, label %land.lhs.true3, label %if.end
 
 land.lhs.true3:                                   ; preds = %lor.lhs.false, %land.lhs.true
-  %3 = load i32* @b, align 4
-  %4 = load i32* @d, align 4
+  %3 = load i32, i32* @b, align 4
+  %4 = load i32, i32* @d, align 4
   %cmp4 = icmp eq i32 %3, %4
   br i1 %cmp4, label %return, label %if.end
 
@@ -52,13 +52,13 @@ define i32 @combine_gt_lt_5() #0 {
 ; CHECK-NOT: cmp
 ; CHECK: b.ge
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp sgt i32 %0, 5
   br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
 
 land.lhs.true:                                    ; preds = %entry
-  %1 = load i32* @b, align 4
-  %2 = load i32* @c, align 4
+  %1 = load i32, i32* @b, align 4
+  %2 = load i32, i32* @c, align 4
   %cmp1 = icmp eq i32 %1, %2
   br i1 %cmp1, label %return, label %if.end
 
@@ -67,8 +67,8 @@ lor.lhs.false:                                    ; preds = %entry
   br i1 %cmp2, label %land.lhs.true3, label %if.end
 
 land.lhs.true3:                                   ; preds = %lor.lhs.false
-  %3 = load i32* @b, align 4
-  %4 = load i32* @d, align 4
+  %3 = load i32, i32* @b, align 4
+  %4 = load i32, i32* @d, align 4
   %cmp4 = icmp eq i32 %3, %4
   br i1 %cmp4, label %return, label %if.end
 
@@ -89,13 +89,13 @@ define i32 @combine_lt_ge_5() #0 {
 ; CHECK-NOT: cmp
 ; CHECK: b.gt
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp slt i32 %0, 5
   br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
 
 land.lhs.true:                                    ; preds = %entry
-  %1 = load i32* @b, align 4
-  %2 = load i32* @c, align 4
+  %1 = load i32, i32* @b, align 4
+  %2 = load i32, i32* @c, align 4
   %cmp1 = icmp eq i32 %1, %2
   br i1 %cmp1, label %return, label %land.lhs.true3
 
@@ -104,8 +104,8 @@ lor.lhs.false:                                    ; preds = %entry
   br i1 %cmp2, label %land.lhs.true3, label %if.end
 
 land.lhs.true3:                                   ; preds = %lor.lhs.false, %land.lhs.true
-  %3 = load i32* @b, align 4
-  %4 = load i32* @d, align 4
+  %3 = load i32, i32* @b, align 4
+  %4 = load i32, i32* @d, align 4
   %cmp4 = icmp eq i32 %3, %4
   br i1 %cmp4, label %return, label %if.end
 
@@ -126,13 +126,13 @@ define i32 @combine_lt_gt_5() #0 {
 ; CHECK-NOT: cmp
 ; CHECK: b.le
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp slt i32 %0, 5
   br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
 
 land.lhs.true:                                    ; preds = %entry
-  %1 = load i32* @b, align 4
-  %2 = load i32* @c, align 4
+  %1 = load i32, i32* @b, align 4
+  %2 = load i32, i32* @c, align 4
   %cmp1 = icmp eq i32 %1, %2
   br i1 %cmp1, label %return, label %if.end
 
@@ -141,8 +141,8 @@ lor.lhs.false:                                    ; preds = %entry
   br i1 %cmp2, label %land.lhs.true3, label %if.end
 
 land.lhs.true3:                                   ; preds = %lor.lhs.false
-  %3 = load i32* @b, align 4
-  %4 = load i32* @d, align 4
+  %3 = load i32, i32* @b, align 4
+  %4 = load i32, i32* @d, align 4
   %cmp4 = icmp eq i32 %3, %4
   br i1 %cmp4, label %return, label %if.end
 
@@ -163,13 +163,13 @@ define i32 @combine_gt_lt_n5() #0 {
 ; CHECK-NOT: cmn
 ; CHECK: b.ge
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp sgt i32 %0, -5
   br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
 
 land.lhs.true:                                    ; preds = %entry
-  %1 = load i32* @b, align 4
-  %2 = load i32* @c, align 4
+  %1 = load i32, i32* @b, align 4
+  %2 = load i32, i32* @c, align 4
   %cmp1 = icmp eq i32 %1, %2
   br i1 %cmp1, label %return, label %if.end
 
@@ -178,8 +178,8 @@ lor.lhs.false:                                    ; preds = %entry
   br i1 %cmp2, label %land.lhs.true3, label %if.end
 
 land.lhs.true3:                                   ; preds = %lor.lhs.false
-  %3 = load i32* @b, align 4
-  %4 = load i32* @d, align 4
+  %3 = load i32, i32* @b, align 4
+  %4 = load i32, i32* @d, align 4
   %cmp4 = icmp eq i32 %3, %4
   br i1 %cmp4, label %return, label %if.end
 
@@ -200,13 +200,13 @@ define i32 @combine_lt_gt_n5() #0 {
 ; CHECK-NOT: cmn
 ; CHECK: b.le
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp slt i32 %0, -5
   br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
 
 land.lhs.true:                                    ; preds = %entry
-  %1 = load i32* @b, align 4
-  %2 = load i32* @c, align 4
+  %1 = load i32, i32* @b, align 4
+  %2 = load i32, i32* @c, align 4
   %cmp1 = icmp eq i32 %1, %2
   br i1 %cmp1, label %return, label %if.end
 
@@ -215,8 +215,8 @@ lor.lhs.false:                                    ; preds = %entry
   br i1 %cmp2, label %land.lhs.true3, label %if.end
 
 land.lhs.true3:                                   ; preds = %lor.lhs.false
-  %3 = load i32* @b, align 4
-  %4 = load i32* @d, align 4
+  %3 = load i32, i32* @b, align 4
+  %4 = load i32, i32* @d, align 4
   %cmp4 = icmp eq i32 %3, %4
   br i1 %cmp4, label %return, label %if.end
 
@@ -237,18 +237,18 @@ declare %struct.Struct* @Update(%struct.Struct*) #1
 ; no checks for this case, it just should be processed without errors
 define void @combine_non_adjacent_cmp_br(%struct.Struct* nocapture readonly %hdCall) #0 {
 entry:
-  %size = getelementptr inbounds %struct.Struct* %hdCall, i64 0, i32 0
-  %0 = load i64* %size, align 8
+  %size = getelementptr inbounds %struct.Struct, %struct.Struct* %hdCall, i64 0, i32 0
+  %0 = load i64, i64* %size, align 8
   br label %land.rhs
 
 land.rhs:
   %rp.06 = phi i64 [ %0, %entry ], [ %sub, %while.body ]
-  %1 = load i64* inttoptr (i64 24 to i64*), align 8
+  %1 = load i64, i64* inttoptr (i64 24 to i64*), align 8
   %cmp2 = icmp sgt i64 %1, 0
   br i1 %cmp2, label %while.body, label %while.end
 
 while.body:
-  %2 = load %struct.Struct** @glob, align 8
+  %2 = load %struct.Struct*, %struct.Struct** @glob, align 8
   %call = tail call %struct.Struct* @Update(%struct.Struct* %2) #2
   %sub = add nsw i64 %rp.06, -2
   %cmp = icmp slt i64 %0, %rp.06
@@ -268,7 +268,7 @@ define i32 @do_nothing_if_resultant_opcodes_would_differ() #0 {
 ; CHECK: cmp
 ; CHECK: b.gt
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp4 = icmp slt i32 %0, -1
   br i1 %cmp4, label %while.body.preheader, label %while.end
 
@@ -283,7 +283,7 @@ while.body:                                       ; preds = %while.body, %while.
   br i1 %cmp, label %while.body, label %while.cond.while.end_crit_edge
 
 while.cond.while.end_crit_edge:                   ; preds = %while.body
-  %.pre = load i32* @a, align 4
+  %.pre = load i32, i32* @a, align 4
   br label %while.end
 
 while.end:                                        ; preds = %while.cond.while.end_crit_edge, %entry
@@ -292,8 +292,8 @@ while.end:                                        ; preds = %while.cond.while.en
   br i1 %cmp1, label %land.lhs.true, label %if.end
 
 land.lhs.true:                                    ; preds = %while.end
-  %2 = load i32* @b, align 4
-  %3 = load i32* @d, align 4
+  %2 = load i32, i32* @b, align 4
+  %3 = load i32, i32* @d, align 4
   %cmp2 = icmp eq i32 %2, %3
   br i1 %cmp2, label %return, label %if.end
 
@@ -312,7 +312,7 @@ define i32 @do_nothing_if_compares_can_not_be_adjusted_to_each_other() #0 {
 ; CHECK: cmn
 ; CHECK: b.lt
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp4 = icmp slt i32 %0, 1
   br i1 %cmp4, label %while.body.preheader, label %while.end
 
@@ -330,13 +330,13 @@ while.end.loopexit:                               ; preds = %while.body
   br label %while.end
 
 while.end:                                        ; preds = %while.end.loopexit, %entry
-  %1 = load i32* @c, align 4
+  %1 = load i32, i32* @c, align 4
   %cmp1 = icmp sgt i32 %1, -3
   br i1 %cmp1, label %land.lhs.true, label %if.end
 
 land.lhs.true:                                    ; preds = %while.end
-  %2 = load i32* @b, align 4
-  %3 = load i32* @d, align 4
+  %2 = load i32, i32* @b, align 4
+  %3 = load i32, i32* @d, align 4
   %cmp2 = icmp eq i32 %2, %3
   br i1 %cmp2, label %return, label %if.end
 
@@ -366,7 +366,6 @@ define i32 @fcmpri(i32 %argc, i8** nocapture readonly %argv) {
 ; CHECK-LABEL-DAG: .LBB9_3
 ; CHECK: cmp w19, #0
 ; CHECK: fcmp d8, #0.0
-; CHECK: b.gt .LBB9_5
 ; CHECK-NOT: cmp w19, #1
 ; CHECK-NOT: b.ge .LBB9_5
 
@@ -375,8 +374,8 @@ entry:
   br i1 %cmp, label %land.lhs.true, label %if.end
 
 land.lhs.true:                                    ; preds = %entry
-  %arrayidx = getelementptr inbounds i8** %argv, i64 1
-  %0 = load i8** %arrayidx, align 8
+  %arrayidx = getelementptr inbounds i8*, i8** %argv, i64 1
+  %0 = load i8*, i8** %arrayidx, align 8
   %cmp1 = icmp eq i8* %0, null
   br i1 %cmp1, label %if.end, label %return
 
diff --git a/test/CodeGen/AArch64/compare-branch.ll b/test/CodeGen/AArch64/compare-branch.ll
index a1a87cf51a1a..4e0f69d195c2 100644
--- a/test/CodeGen/AArch64/compare-branch.ll
+++ b/test/CodeGen/AArch64/compare-branch.ll
@@ -6,25 +6,25 @@
 define void @foo() {
 ; CHECK-LABEL: foo:
 
-  %val1 = load volatile i32* @var32
+  %val1 = load volatile i32, i32* @var32
   %tst1 = icmp eq i32 %val1, 0
   br i1 %tst1, label %end, label %test2
 ; CHECK: cbz {{w[0-9]+}}, .LBB
 
 test2:
-  %val2 = load volatile i32* @var32
+  %val2 = load volatile i32, i32* @var32
   %tst2 = icmp ne i32 %val2, 0
   br i1 %tst2, label %end, label %test3
 ; CHECK: cbnz {{w[0-9]+}}, .LBB
 
 test3:
-  %val3 = load volatile i64* @var64
+  %val3 = load volatile i64, i64* @var64
   %tst3 = icmp eq i64 %val3, 0
   br i1 %tst3, label %end, label %test4
 ; CHECK: cbz {{x[0-9]+}}, .LBB
 
 test4:
-  %val4 = load volatile i64* @var64
+  %val4 = load volatile i64, i64* @var64
   %tst4 = icmp ne i64 %val4, 0
   br i1 %tst4, label %end, label %test5
 ; CHECK: cbnz {{x[0-9]+}}, .LBB
diff --git a/test/CodeGen/AArch64/complex-copy-noneon.ll b/test/CodeGen/AArch64/complex-copy-noneon.ll
index 4ae547856ecd..b7c704336023 100644
--- a/test/CodeGen/AArch64/complex-copy-noneon.ll
+++ b/test/CodeGen/AArch64/complex-copy-noneon.ll
@@ -8,13 +8,13 @@ define void @store_combine() nounwind {
   %src = alloca { double, double }, align 8
   %dst = alloca { double, double }, align 8
 
-  %src.realp = getelementptr inbounds { double, double }* %src, i32 0, i32 0
-  %src.real = load double* %src.realp
-  %src.imagp = getelementptr inbounds { double, double }* %src, i32 0, i32 1
-  %src.imag = load double* %src.imagp
+  %src.realp = getelementptr inbounds { double, double }, { double, double }* %src, i32 0, i32 0
+  %src.real = load double, double* %src.realp
+  %src.imagp = getelementptr inbounds { double, double }, { double, double }* %src, i32 0, i32 1
+  %src.imag = load double, double* %src.imagp
 
-  %dst.realp = getelementptr inbounds { double, double }* %dst, i32 0, i32 0
-  %dst.imagp = getelementptr inbounds { double, double }* %dst, i32 0, i32 1
+  %dst.realp = getelementptr inbounds { double, double }, { double, double }* %dst, i32 0, i32 0
+  %dst.imagp = getelementptr inbounds { double, double }, { double, double }* %dst, i32 0, i32 1
   store double %src.real, double* %dst.realp
   store double %src.imag, double* %dst.imagp
   ret void
diff --git a/test/CodeGen/AArch64/complex-int-to-fp.ll b/test/CodeGen/AArch64/complex-int-to-fp.ll
index 5c943f95c355..1102553ab551 100644
--- a/test/CodeGen/AArch64/complex-int-to-fp.ll
+++ b/test/CodeGen/AArch64/complex-int-to-fp.ll
@@ -4,7 +4,7 @@
 ; CHECK: scvtf
 ; CHECK: ret
 define void @autogen_SD19655(<2 x i64>* %addr, <2 x float>* %addrfloat) {
-  %T = load <2 x i64>* %addr
+  %T = load <2 x i64>, <2 x i64>* %addr
   %F = sitofp <2 x i64> %T to <2 x float>
   store <2 x float> %F, <2 x float>* %addrfloat
   ret void
diff --git a/test/CodeGen/AArch64/concat_vector-scalar-combine.ll b/test/CodeGen/AArch64/concat_vector-scalar-combine.ll
new file mode 100644
index 000000000000..1c64af636cb3
--- /dev/null
+++ b/test/CodeGen/AArch64/concat_vector-scalar-combine.ll
@@ -0,0 +1,125 @@
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+; Test the (concat_vectors (bitcast (scalar)), ..) pattern.
+
+define <8 x i8> @test_concat_scalar_v2i8_to_v8i8_dup(i32 %x) #0 {
+entry:
+; CHECK-LABEL: test_concat_scalar_v2i8_to_v8i8_dup:
+; CHECK-NEXT: dup.4h v0, w0
+; CHECK-NEXT: ret
+  %t = trunc i32 %x to i16
+  %0 = bitcast i16 %t to <2 x i8>
+  %1 = shufflevector <2 x i8> %0, <2 x i8> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
+  ret <8 x i8> %1
+}
+
+define <8 x i8> @test_concat_scalar_v4i8_to_v8i8_dup(i32 %x) #0 {
+entry:
+; CHECK-LABEL: test_concat_scalar_v4i8_to_v8i8_dup:
+; CHECK-NEXT: dup.2s v0, w0
+; CHECK-NEXT: ret
+  %0 = bitcast i32 %x to <4 x i8>
+  %1 = shufflevector <4 x i8> %0, <4 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  ret <8 x i8> %1
+}
+
+define <8 x i16> @test_concat_scalar_v2i16_to_v8i16_dup(i32 %x) #0 {
+entry:
+; CHECK-LABEL: test_concat_scalar_v2i16_to_v8i16_dup:
+; CHECK-NEXT: dup.4s v0, w0
+; CHECK-NEXT: ret
+  %0 = bitcast i32 %x to <2 x i16>
+  %1 = shufflevector <2 x i16> %0, <2 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 2, i32 0, i32 1, i32 0, i32 1>
+  ret <8 x i16> %1
+}
+
+define <8 x i8> @test_concat_scalars_2x_v2i8_to_v8i8(i32 %x, i32 %y) #0 {
+entry:
+; CHECK-LABEL: test_concat_scalars_2x_v2i8_to_v8i8:
+; CHECK-NEXT: ins.h v0[0], w0
+; CHECK-NEXT: ins.h v0[1], w1
+; CHECK-NEXT: ins.h v0[3], w1
+; CHECK-NEXT: ret
+  %tx = trunc i32 %x to i16
+  %ty = trunc i32 %y to i16
+  %bx = bitcast i16 %tx to <2 x i8>
+  %by = bitcast i16 %ty to <2 x i8>
+  %r = shufflevector <2 x i8> %bx, <2 x i8> %by, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 2, i32 3>
+  ret <8 x i8> %r
+}
+
+define <8 x i8> @test_concat_scalars_2x_v4i8_to_v8i8_dup(i32 %x, i32 %y) #0 {
+entry:
+; CHECK-LABEL: test_concat_scalars_2x_v4i8_to_v8i8_dup:
+; CHECK-NEXT: fmov s0, w1
+; CHECK-NEXT: ins.s v0[1], w0
+; CHECK-NEXT: ret
+  %bx = bitcast i32 %x to <4 x i8>
+  %by = bitcast i32 %y to <4 x i8>
+  %r = shufflevector <4 x i8> %bx, <4 x i8> %by, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+  ret <8 x i8> %r
+}
+
+define <8 x i16> @test_concat_scalars_2x_v2i16_to_v8i16_dup(i32 %x, i32 %y) #0 {
+entry:
+; CHECK-LABEL: test_concat_scalars_2x_v2i16_to_v8i16_dup:
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: ins.s v0[1], w1
+; CHECK-NEXT: ins.s v0[2], w1
+; CHECK-NEXT: ins.s v0[3], w0
+; CHECK-NEXT: ret
+  %bx = bitcast i32 %x to <2 x i16>
+  %by = bitcast i32 %y to <2 x i16>
+  %r = shufflevector <2 x i16> %bx, <2 x i16> %by, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1>
+  ret <8 x i16> %r
+}
+
+; Also make sure we minimize bitcasts.
+
+; This is a pretty artificial testcase: make sure we bitcast to floating-point
+; if any of the scalars is floating-point.
+define <8 x i8> @test_concat_scalars_mixed_2x_v2i8_to_v8i8(float %dummy, i32 %x, half %y) #0 {
+entry:
+; CHECK-LABEL: test_concat_scalars_mixed_2x_v2i8_to_v8i8:
+; CHECK-NEXT: fmov s[[X:[0-9]+]], w0
+; CHECK-NEXT: ins.h v0[0], v[[X]][0]
+; CHECK-NEXT: ins.h v0[1], v1[0]
+; CHECK-NEXT: ins.h v0[2], v[[X]][0]
+; CHECK-NEXT: ins.h v0[3], v1[0]
+; CHECK-NEXT: ret
+  %t = trunc i32 %x to i16
+  %0 = bitcast i16 %t to <2 x i8>
+  %y0 = bitcast half %y to <2 x i8>
+  %1 = shufflevector <2 x i8> %0, <2 x i8> %y0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  ret <8 x i8> %1
+}
+
+define <2 x float> @test_concat_scalars_fp_2x_v2i8_to_v8i8(float %dummy, half %x, half %y) #0 {
+entry:
+; CHECK-LABEL: test_concat_scalars_fp_2x_v2i8_to_v8i8:
+; CHECK-NEXT: ins.h v0[0], v1[0]
+; CHECK-NEXT: ins.h v0[1], v2[0]
+; CHECK-NEXT: ins.h v0[2], v1[0]
+; CHECK-NEXT: ins.h v0[3], v2[0]
+; CHECK-NEXT: ret
+  %0 = bitcast half %x to <2 x i8>
+  %y0 = bitcast half %y to <2 x i8>
+  %1 = shufflevector <2 x i8> %0, <2 x i8> %y0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %2 = bitcast <8 x i8> %1 to <2 x float>
+  ret <2 x float> %2
+}
+
+define <4 x float> @test_concat_scalar_fp_v2i16_to_v16i8_dup(float %x) #0 {
+entry:
+; CHECK-LABEL: test_concat_scalar_fp_v2i16_to_v16i8_dup:
+; CHECK-NEXT: dup.4s v0, v0[0]
+; CHECK-NEXT: ret
+  %0 = bitcast float %x to <2 x i16>
+  %1 = shufflevector <2 x i16> %0, <2 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 2, i32 0, i32 1, i32 0, i32 1>
+  %2 = bitcast <8 x i16> %1 to <4 x float>
+  ret <4 x float> %2
+}
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/AArch64/concat_vector-truncate-combine.ll b/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
new file mode 100644
index 000000000000..ee5278600422
--- /dev/null
+++ b/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -mtriple arm64-apple-darwin -asm-verbose=false | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+; Test the (concat_vectors (trunc), (trunc)) pattern.
+
+define <4 x i16> @test_concat_truncate_v2i64_to_v4i16(<2 x i64> %a, <2 x i64> %b) #0 {
+entry:
+; CHECK-LABEL: test_concat_truncate_v2i64_to_v4i16:
+; CHECK-NEXT: uzp1.4s v0, v0, v1
+; CHECK-NEXT: xtn.4h v0, v0
+; CHECK-NEXT: ret
+  %at = trunc <2 x i64> %a to <2 x i16>
+  %bt = trunc <2 x i64> %b to <2 x i16>
+  %shuffle = shufflevector <2 x i16> %at, <2 x i16> %bt, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  ret <4 x i16> %shuffle
+}
+
+define <8 x i8> @test_concat_truncate_v4i32_to_v8i8(<4 x i32> %a, <4 x i32> %b) #0 {
+entry:
+; CHECK-LABEL: test_concat_truncate_v4i32_to_v8i8:
+; CHECK-NEXT: uzp1.8h v0, v0, v1
+; CHECK-NEXT: xtn.8b v0, v0
+; CHECK-NEXT: ret
+  %at = trunc <4 x i32> %a to <4 x i8>
+  %bt = trunc <4 x i32> %b to <4 x i8>
+  %shuffle = shufflevector <4 x i8> %at, <4 x i8> %bt, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  ret <8 x i8> %shuffle
+}
+
+define <8 x i16> @test_concat_truncate_v4i32_to_v8i16(<4 x i32> %a, <4 x i32> %b) #0 {
+entry:
+; CHECK-LABEL: test_concat_truncate_v4i32_to_v8i16:
+; CHECK-NEXT: xtn.4h v0, v0
+; CHECK-NEXT: xtn2.8h v0, v1
+; CHECK-NEXT: ret
+  %at = trunc <4 x i32> %a to <4 x i16>
+  %bt = trunc <4 x i32> %b to <4 x i16>
+  %shuffle = shufflevector <4 x i16> %at, <4 x i16> %bt, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  ret <8 x i16> %shuffle
+}
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/AArch64/concat_vector-truncated-scalar-combine.ll b/test/CodeGen/AArch64/concat_vector-truncated-scalar-combine.ll
new file mode 100644
index 000000000000..eb6c80df855a
--- /dev/null
+++ b/test/CodeGen/AArch64/concat_vector-truncated-scalar-combine.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -asm-verbose=false | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+; Test the (concat_vectors (bitcast (trunc (scalar))), undef..) pattern.
+
+define <8 x i8> @test_concat_from_truncated_scalar(i32 %x) #0 {
+entry:
+; CHECK-LABEL: test_concat_from_truncated_scalar:
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: ret
+  %t = trunc i32 %x to i16
+  %0 = bitcast i16 %t to <2 x i8>
+  %1 = shufflevector <2 x i8> %0, <2 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
+  ret <8 x i8> %1
+}
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/AArch64/cpus.ll b/test/CodeGen/AArch64/cpus.ll
index f0f36bd5cea5..1266842fcc6d 100644
--- a/test/CodeGen/AArch64/cpus.ll
+++ b/test/CodeGen/AArch64/cpus.ll
@@ -4,6 +4,7 @@
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=generic 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a72 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID
 
 ; CHECK-NOT: {{.*}}  is not a recognized processor for this target
diff --git a/test/CodeGen/AArch64/dag-combine-invaraints.ll b/test/CodeGen/AArch64/dag-combine-invaraints.ll
index 115fc64174c8..ac2d057ff3c9 100644
--- a/test/CodeGen/AArch64/dag-combine-invaraints.ll
+++ b/test/CodeGen/AArch64/dag-combine-invaraints.ll
@@ -12,15 +12,15 @@ main_:
   store i32 0, i32* %tmp
   store i32 15, i32* %i32T, align 4
   store i32 5, i32* %i32F, align 4
-  %tmp6 = load i32* %tmp, align 4
+  %tmp6 = load i32, i32* %tmp, align 4
   %tmp7 = icmp ne i32 %tmp6, 0
   %tmp8 = xor i1 %tmp7, true
-  %tmp9 = load i32* %i32T, align 4
-  %tmp10 = load i32* %i32F, align 4
+  %tmp9 = load i32, i32* %i32T, align 4
+  %tmp10 = load i32, i32* %i32F, align 4
   %DHSelect = select i1 %tmp8, i32 %tmp9, i32 %tmp10
   store i32 %DHSelect, i32* %i32X, align 4
-  %tmp15 = load i32* %i32X, align 4
-  %tmp17 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str2, i32 0, i32 0), i32 %tmp15)
+  %tmp15 = load i32, i32* %i32X, align 4
+  %tmp17 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str2, i32 0, i32 0), i32 %tmp15)
   ret i32 0
 
 ; CHECK: main:
diff --git a/test/CodeGen/AArch64/dp-3source.ll b/test/CodeGen/AArch64/dp-3source.ll
index bd96ec728f52..3982fea95d6c 100644
--- a/test/CodeGen/AArch64/dp-3source.ll
+++ b/test/CodeGen/AArch64/dp-3source.ll
@@ -168,8 +168,8 @@ define i64 @test_umnegl(i32 %lhs, i32 %rhs) {
 
 define void @test_mneg(){
 ; CHECK-LABEL: test_mneg:
-  %1 = load i32* @a, align 4
-  %2 = load i32* @b, align 4
+  %1 = load i32, i32* @a, align 4
+  %2 = load i32, i32* @b, align 4
   %3 = sub i32 0, %1
   %4 = mul i32 %2, %3
   store i32 %4, i32* @c, align 4
diff --git a/test/CodeGen/AArch64/dp1.ll b/test/CodeGen/AArch64/dp1.ll
index 662b41588541..4247afa11b76 100644
--- a/test/CodeGen/AArch64/dp1.ll
+++ b/test/CodeGen/AArch64/dp1.ll
@@ -5,7 +5,7 @@
 
 define void @rev_i32() {
 ; CHECK-LABEL: rev_i32:
-    %val0_tmp = load i32* @var32
+    %val0_tmp = load i32, i32* @var32
     %val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)
 ; CHECK: rev	{{w[0-9]+}}, {{w[0-9]+}}
     store volatile i32 %val1_tmp, i32* @var32
@@ -14,7 +14,7 @@ define void @rev_i32() {
 
 define void @rev_i64() {
 ; CHECK-LABEL: rev_i64:
-    %val0_tmp = load i64* @var64
+    %val0_tmp = load i64, i64* @var64
     %val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)
 ; CHECK: rev	{{x[0-9]+}}, {{x[0-9]+}}
     store volatile i64 %val1_tmp, i64* @var64
@@ -23,7 +23,7 @@ define void @rev_i64() {
 
 define void @rev32_i64() {
 ; CHECK-LABEL: rev32_i64:
-    %val0_tmp = load i64* @var64
+    %val0_tmp = load i64, i64* @var64
     %val1_tmp = shl i64 %val0_tmp, 32
     %val5_tmp = sub i64 64, 32
     %val2_tmp = lshr i64 %val0_tmp, %val5_tmp
@@ -36,7 +36,7 @@ define void @rev32_i64() {
 
 define void @rev16_i32() {
 ; CHECK-LABEL: rev16_i32:
-    %val0_tmp = load i32* @var32
+    %val0_tmp = load i32, i32* @var32
     %val1_tmp = shl i32 %val0_tmp, 16
     %val2_tmp = lshr i32 %val0_tmp, 16
     %val3_tmp = or i32 %val1_tmp, %val2_tmp
@@ -48,7 +48,7 @@ define void @rev16_i32() {
 
 define void @clz_zerodef_i32() {
 ; CHECK-LABEL: clz_zerodef_i32:
-    %val0_tmp = load i32* @var32
+    %val0_tmp = load i32, i32* @var32
     %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0)
 ; CHECK: clz	{{w[0-9]+}}, {{w[0-9]+}}
     store volatile i32 %val4_tmp, i32* @var32
@@ -57,7 +57,7 @@ define void @clz_zerodef_i32() {
 
 define void @clz_zerodef_i64() {
 ; CHECK-LABEL: clz_zerodef_i64:
-    %val0_tmp = load i64* @var64
+    %val0_tmp = load i64, i64* @var64
     %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0)
 ; CHECK: clz	{{x[0-9]+}}, {{x[0-9]+}}
     store volatile i64 %val4_tmp, i64* @var64
@@ -66,7 +66,7 @@ define void @clz_zerodef_i64() {
 
 define void @clz_zeroundef_i32() {
 ; CHECK-LABEL: clz_zeroundef_i32:
-    %val0_tmp = load i32* @var32
+    %val0_tmp = load i32, i32* @var32
     %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1)
 ; CHECK: clz	{{w[0-9]+}}, {{w[0-9]+}}
     store volatile i32 %val4_tmp, i32* @var32
@@ -75,7 +75,7 @@ define void @clz_zeroundef_i32() {
 
 define void @clz_zeroundef_i64() {
 ; CHECK-LABEL: clz_zeroundef_i64:
-    %val0_tmp = load i64* @var64
+    %val0_tmp = load i64, i64* @var64
     %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1)
 ; CHECK: clz	{{x[0-9]+}}, {{x[0-9]+}}
     store volatile i64 %val4_tmp, i64* @var64
@@ -84,7 +84,7 @@ define void @clz_zeroundef_i64() {
 
 define void @cttz_zerodef_i32() {
 ; CHECK-LABEL: cttz_zerodef_i32:
-    %val0_tmp = load i32* @var32
+    %val0_tmp = load i32, i32* @var32
     %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0)
 ; CHECK: rbit   [[REVERSED:w[0-9]+]], {{w[0-9]+}}
 ; CHECK: clz	{{w[0-9]+}}, [[REVERSED]]
@@ -94,7 +94,7 @@ define void @cttz_zerodef_i32() {
 
 define void @cttz_zerodef_i64() {
 ; CHECK-LABEL: cttz_zerodef_i64:
-    %val0_tmp = load i64* @var64
+    %val0_tmp = load i64, i64* @var64
     %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0)
 ; CHECK: rbit   [[REVERSED:x[0-9]+]], {{x[0-9]+}}
 ; CHECK: clz	{{x[0-9]+}}, [[REVERSED]]
@@ -104,7 +104,7 @@ define void @cttz_zerodef_i64() {
 
 define void @cttz_zeroundef_i32() {
 ; CHECK-LABEL: cttz_zeroundef_i32:
-    %val0_tmp = load i32* @var32
+    %val0_tmp = load i32, i32* @var32
     %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1)
 ; CHECK: rbit   [[REVERSED:w[0-9]+]], {{w[0-9]+}}
 ; CHECK: clz	{{w[0-9]+}}, [[REVERSED]]
@@ -114,7 +114,7 @@ define void @cttz_zeroundef_i32() {
 
 define void @cttz_zeroundef_i64() {
 ; CHECK-LABEL: cttz_zeroundef_i64:
-    %val0_tmp = load i64* @var64
+    %val0_tmp = load i64, i64* @var64
     %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1)
 ; CHECK: rbit   [[REVERSED:x[0-9]+]], {{x[0-9]+}}
 ; CHECK: clz	{{x[0-9]+}}, [[REVERSED]]
@@ -126,7 +126,7 @@ define void @cttz_zeroundef_i64() {
 ; ISelLowering.
 define void @ctpop_i32() {
 ; CHECK-LABEL: ctpop_i32:
-    %val0_tmp = load i32* @var32
+    %val0_tmp = load i32, i32* @var32
     %val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp)
     store volatile i32 %val4_tmp, i32* @var32
     ret void
@@ -134,7 +134,7 @@ define void @ctpop_i32() {
 
 define void @ctpop_i64() {
 ; CHECK-LABEL: ctpop_i64:
-    %val0_tmp = load i64* @var64
+    %val0_tmp = load i64, i64* @var64
     %val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp)
     store volatile i64 %val4_tmp, i64* @var64
     ret void
diff --git a/test/CodeGen/AArch64/dp2.ll b/test/CodeGen/AArch64/dp2.ll
index 71b31696372a..0cd2d7ed84a7 100644
--- a/test/CodeGen/AArch64/dp2.ll
+++ b/test/CodeGen/AArch64/dp2.ll
@@ -7,8 +7,8 @@
 
 define void @rorv_i64() {
 ; CHECK-LABEL: rorv_i64:
-    %val0_tmp = load i64* @var64_0
-    %val1_tmp = load i64* @var64_1
+    %val0_tmp = load i64, i64* @var64_0
+    %val1_tmp = load i64, i64* @var64_1
     %val2_tmp = sub i64 64, %val1_tmp
     %val3_tmp = shl i64 %val0_tmp, %val2_tmp
     %val4_tmp = lshr i64 %val0_tmp, %val1_tmp
@@ -20,8 +20,8 @@ define void @rorv_i64() {
 
 define void @asrv_i64() {
 ; CHECK-LABEL: asrv_i64:
-    %val0_tmp = load i64* @var64_0
-    %val1_tmp = load i64* @var64_1
+    %val0_tmp = load i64, i64* @var64_0
+    %val1_tmp = load i64, i64* @var64_1
     %val4_tmp = ashr i64 %val0_tmp, %val1_tmp
 ; CHECK: {{asr|asrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
     store volatile i64 %val4_tmp, i64* @var64_1
@@ -30,8 +30,8 @@ define void @asrv_i64() {
 
 define void @lsrv_i64() {
 ; CHECK-LABEL: lsrv_i64:
-    %val0_tmp = load i64* @var64_0
-    %val1_tmp = load i64* @var64_1
+    %val0_tmp = load i64, i64* @var64_0
+    %val1_tmp = load i64, i64* @var64_1
     %val4_tmp = lshr i64 %val0_tmp, %val1_tmp
 ; CHECK: {{lsr|lsrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
     store volatile i64 %val4_tmp, i64* @var64_0
@@ -40,8 +40,8 @@ define void @lsrv_i64() {
 
 define void @lslv_i64() {
 ; CHECK-LABEL: lslv_i64:
-    %val0_tmp = load i64* @var64_0
-    %val1_tmp = load i64* @var64_1
+    %val0_tmp = load i64, i64* @var64_0
+    %val1_tmp = load i64, i64* @var64_1
     %val4_tmp = shl i64 %val0_tmp, %val1_tmp
 ; CHECK: {{lsl|lslv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
     store volatile i64 %val4_tmp, i64* @var64_1
@@ -50,8 +50,8 @@ define void @lslv_i64() {
 
 define void @udiv_i64() {
 ; CHECK-LABEL: udiv_i64:
-    %val0_tmp = load i64* @var64_0
-    %val1_tmp = load i64* @var64_1
+    %val0_tmp = load i64, i64* @var64_0
+    %val1_tmp = load i64, i64* @var64_1
     %val4_tmp = udiv i64 %val0_tmp, %val1_tmp
 ; CHECK: udiv	{{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
     store volatile i64 %val4_tmp, i64* @var64_0
@@ -60,8 +60,8 @@ define void @udiv_i64() {
 
 define void @sdiv_i64() {
 ; CHECK-LABEL: sdiv_i64:
-    %val0_tmp = load i64* @var64_0
-    %val1_tmp = load i64* @var64_1
+    %val0_tmp = load i64, i64* @var64_0
+    %val1_tmp = load i64, i64* @var64_1
     %val4_tmp = sdiv i64 %val0_tmp, %val1_tmp
 ; CHECK: sdiv	{{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
     store volatile i64 %val4_tmp, i64* @var64_1
@@ -71,8 +71,8 @@ define void @sdiv_i64() {
 
 define void @lsrv_i32() {
 ; CHECK-LABEL: lsrv_i32:
-    %val0_tmp = load i32* @var32_0
-    %val1_tmp = load i32* @var32_1
+    %val0_tmp = load i32, i32* @var32_0
+    %val1_tmp = load i32, i32* @var32_1
     %val2_tmp = add i32 1, %val1_tmp
     %val4_tmp = lshr i32 %val0_tmp, %val2_tmp
 ; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
@@ -82,8 +82,8 @@ define void @lsrv_i32() {
 
 define void @lslv_i32() {
 ; CHECK-LABEL: lslv_i32:
-    %val0_tmp = load i32* @var32_0
-    %val1_tmp = load i32* @var32_1
+    %val0_tmp = load i32, i32* @var32_0
+    %val1_tmp = load i32, i32* @var32_1
     %val2_tmp = add i32 1, %val1_tmp
     %val4_tmp = shl i32 %val0_tmp, %val2_tmp
 ; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
@@ -93,8 +93,8 @@ define void @lslv_i32() {
 
 define void @rorv_i32() {
 ; CHECK-LABEL: rorv_i32:
-    %val0_tmp = load i32* @var32_0
-    %val6_tmp = load i32* @var32_1
+    %val0_tmp = load i32, i32* @var32_0
+    %val6_tmp = load i32, i32* @var32_1
     %val1_tmp = add i32 1, %val6_tmp
     %val2_tmp = sub i32 32, %val1_tmp
     %val3_tmp = shl i32 %val0_tmp, %val2_tmp
@@ -107,8 +107,8 @@ define void @rorv_i32() {
 
 define void @asrv_i32() {
 ; CHECK-LABEL: asrv_i32:
-    %val0_tmp = load i32* @var32_0
-    %val1_tmp = load i32* @var32_1
+    %val0_tmp = load i32, i32* @var32_0
+    %val1_tmp = load i32, i32* @var32_1
     %val2_tmp = add i32 1, %val1_tmp
     %val4_tmp = ashr i32 %val0_tmp, %val2_tmp
 ; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
@@ -118,8 +118,8 @@ define void @asrv_i32() {
 
 define void @sdiv_i32() {
 ; CHECK-LABEL: sdiv_i32:
-    %val0_tmp = load i32* @var32_0
-    %val1_tmp = load i32* @var32_1
+    %val0_tmp = load i32, i32* @var32_0
+    %val1_tmp = load i32, i32* @var32_1
     %val4_tmp = sdiv i32 %val0_tmp, %val1_tmp
 ; CHECK: sdiv	{{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
     store volatile i32 %val4_tmp, i32* @var32_1
@@ -128,8 +128,8 @@ define void @sdiv_i32() {
 
 define void @udiv_i32() {
 ; CHECK-LABEL: udiv_i32:
-    %val0_tmp = load i32* @var32_0
-    %val1_tmp = load i32* @var32_1
+    %val0_tmp = load i32, i32* @var32_0
+    %val1_tmp = load i32, i32* @var32_1
     %val4_tmp = udiv i32 %val0_tmp, %val1_tmp
 ; CHECK: udiv	{{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
     store volatile i32 %val4_tmp, i32* @var32_0
@@ -141,7 +141,7 @@ define void @udiv_i32() {
 define i32 @test_lsl32() {
 ; CHECK-LABEL: test_lsl32:
 
-  %val = load i32* @var32_0
+  %val = load i32, i32* @var32_0
   %ret = shl i32 1, %val
 ; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
 
@@ -151,7 +151,7 @@ define i32 @test_lsl32() {
 define i32 @test_lsr32() {
 ; CHECK-LABEL: test_lsr32:
 
-  %val = load i32* @var32_0
+  %val = load i32, i32* @var32_0
   %ret = lshr i32 1, %val
 ; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
 
@@ -161,7 +161,7 @@ define i32 @test_lsr32() {
 define i32 @test_asr32(i32 %in) {
 ; CHECK-LABEL: test_asr32:
 
-  %val = load i32* @var32_0
+  %val = load i32, i32* @var32_0
   %ret = ashr i32 %in, %val
 ; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
 
diff --git a/test/CodeGen/AArch64/eliminate-trunc.ll b/test/CodeGen/AArch64/eliminate-trunc.ll
index ea86a084cb42..bc4ac7d71704 100644
--- a/test/CodeGen/AArch64/eliminate-trunc.ll
+++ b/test/CodeGen/AArch64/eliminate-trunc.ll
@@ -14,11 +14,11 @@ entry:
 
 for.body4.us:
   %indvars.iv = phi i64 [ 0, %for.body4.lr.ph.us ], [ %indvars.iv.next, %for.body4.us ]
-  %arrayidx6.us = getelementptr inbounds [8 x i8]* %a, i64 %indvars.iv26, i64 %indvars.iv
-  %0 = load i8* %arrayidx6.us, align 1
+  %arrayidx6.us = getelementptr inbounds [8 x i8], [8 x i8]* %a, i64 %indvars.iv26, i64 %indvars.iv
+  %0 = load i8, i8* %arrayidx6.us, align 1
   %idxprom7.us = zext i8 %0 to i64
-  %arrayidx8.us = getelementptr inbounds i8* %box, i64 %idxprom7.us
-  %1 = load i8* %arrayidx8.us, align 1
+  %arrayidx8.us = getelementptr inbounds i8, i8* %box, i64 %idxprom7.us
+  %1 = load i8, i8* %arrayidx8.us, align 1
   store i8 %1, i8* %arrayidx6.us, align 1
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %2 = trunc i64 %indvars.iv.next to i32
diff --git a/test/CodeGen/AArch64/extern-weak.ll b/test/CodeGen/AArch64/extern-weak.ll
index f647c4bcda51..2203c0c4e698 100644
--- a/test/CodeGen/AArch64/extern-weak.ll
+++ b/test/CodeGen/AArch64/extern-weak.ll
@@ -31,7 +31,7 @@ define i32()* @foo() {
 @arr_var = extern_weak global [10 x i32]
 
 define i32* @bar() {
-  %addr = getelementptr [10 x i32]* @arr_var, i32 0, i32 5
+  %addr = getelementptr [10 x i32], [10 x i32]* @arr_var, i32 0, i32 5
 
 
 ; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:arr_var
diff --git a/test/CodeGen/AArch64/f16-convert.ll b/test/CodeGen/AArch64/f16-convert.ll
index 12412d45aa6e..8caa1f574a7b 100644
--- a/test/CodeGen/AArch64/f16-convert.ll
+++ b/test/CodeGen/AArch64/f16-convert.ll
@@ -6,7 +6,7 @@ define float @load0(i16* nocapture readonly %a) nounwind {
 ; CHECK-NEXT: fcvt s0, [[HREG]]
 ; CHECK-NEXT: ret
 
-  %tmp = load i16* %a, align 2
+  %tmp = load i16, i16* %a, align 2
   %tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp)
   ret float %tmp1
 }
@@ -17,7 +17,7 @@ define double @load1(i16* nocapture readonly %a) nounwind {
 ; CHECK-NEXT: fcvt d0, [[HREG]]
 ; CHECK-NEXT: ret
 
-  %tmp = load i16* %a, align 2
+  %tmp = load i16, i16* %a, align 2
   %conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp)
   ret double %conv
 }
@@ -29,8 +29,8 @@ define float @load2(i16* nocapture readonly %a, i32 %i) nounwind {
 ; CHECK-NEXT: ret
 
   %idxprom = sext i32 %i to i64
-  %arrayidx = getelementptr inbounds i16* %a, i64 %idxprom
-  %tmp = load i16* %arrayidx, align 2
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom
+  %tmp = load i16, i16* %arrayidx, align 2
   %tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp)
   ret float %tmp1
 }
@@ -42,8 +42,8 @@ define double @load3(i16* nocapture readonly %a, i32 %i) nounwind {
 ; CHECK-NEXT: ret
 
   %idxprom = sext i32 %i to i64
-  %arrayidx = getelementptr inbounds i16* %a, i64 %idxprom
-  %tmp = load i16* %arrayidx, align 2
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom
+  %tmp = load i16, i16* %arrayidx, align 2
   %conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp)
   ret double %conv
 }
@@ -54,8 +54,8 @@ define float @load4(i16* nocapture readonly %a, i64 %i) nounwind {
 ; CHECK-NEXT: fcvt s0, [[HREG]]
 ; CHECK-NEXT: ret
 
-  %arrayidx = getelementptr inbounds i16* %a, i64 %i
-  %tmp = load i16* %arrayidx, align 2
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 %i
+  %tmp = load i16, i16* %arrayidx, align 2
   %tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp)
   ret float %tmp1
 }
@@ -66,8 +66,8 @@ define double @load5(i16* nocapture readonly %a, i64 %i) nounwind {
 ; CHECK-NEXT: fcvt d0, [[HREG]]
 ; CHECK-NEXT: ret
 
-  %arrayidx = getelementptr inbounds i16* %a, i64 %i
-  %tmp = load i16* %arrayidx, align 2
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 %i
+  %tmp = load i16, i16* %arrayidx, align 2
   %conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp)
   ret double %conv
 }
@@ -78,8 +78,8 @@ define float @load6(i16* nocapture readonly %a) nounwind {
 ; CHECK-NEXT: fcvt s0, [[HREG]]
 ; CHECK-NEXT: ret
 
-  %arrayidx = getelementptr inbounds i16* %a, i64 10
-  %tmp = load i16* %arrayidx, align 2
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 10
+  %tmp = load i16, i16* %arrayidx, align 2
   %tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp)
   ret float %tmp1
 }
@@ -90,8 +90,8 @@ define double @load7(i16* nocapture readonly %a) nounwind {
 ; CHECK-NEXT: fcvt d0, [[HREG]]
 ; CHECK-NEXT: ret
 
-  %arrayidx = getelementptr inbounds i16* %a, i64 10
-  %tmp = load i16* %arrayidx, align 2
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 10
+  %tmp = load i16, i16* %arrayidx, align 2
   %conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp)
   ret double %conv
 }
@@ -102,8 +102,8 @@ define float @load8(i16* nocapture readonly %a) nounwind {
 ; CHECK-NEXT: fcvt s0, [[HREG]]
 ; CHECK-NEXT: ret
 
-  %arrayidx = getelementptr inbounds i16* %a, i64 -10
-  %tmp = load i16* %arrayidx, align 2
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 -10
+  %tmp = load i16, i16* %arrayidx, align 2
   %tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp)
   ret float %tmp1
 }
@@ -114,8 +114,8 @@ define double @load9(i16* nocapture readonly %a) nounwind {
 ; CHECK-NEXT: fcvt d0, [[HREG]]
 ; CHECK-NEXT: ret
 
-  %arrayidx = getelementptr inbounds i16* %a, i64 -10
-  %tmp = load i16* %arrayidx, align 2
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 -10
+  %tmp = load i16, i16* %arrayidx, align 2
   %conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp)
   ret double %conv
 }
@@ -133,7 +133,8 @@ define void @store0(i16* nocapture %a, float %val) nounwind {
 
 define void @store1(i16* nocapture %a, double %val) nounwind {
 ; CHECK-LABEL: store1:
-; CHECK-NEXT: fcvt h0, d0
+; CHECK-NEXT: fcvt s0, d0
+; CHECK-NEXT: fcvt h0, s0
 ; CHECK-NEXT: str  h0, [x0]
 ; CHECK-NEXT: ret
 
@@ -151,21 +152,22 @@ define void @store2(i16* nocapture %a, i32 %i, float %val) nounwind {
 
   %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %val)
   %idxprom = sext i32 %i to i64
-  %arrayidx = getelementptr inbounds i16* %a, i64 %idxprom
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom
   store i16 %tmp, i16* %arrayidx, align 2
   ret void
 }
 
 define void @store3(i16* nocapture %a, i32 %i, double %val) nounwind {
 ; CHECK-LABEL: store3:
-; CHECK-NEXT: fcvt h0, d0
+; CHECK-NEXT: fcvt s0, d0
+; CHECK-NEXT: fcvt h0, s0
 ; CHECK-NEXT: str h0, [x0, w1, sxtw #1]
 ; CHECK-NEXT: ret
 
   %conv = fptrunc double %val to float
   %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %conv)
   %idxprom = sext i32 %i to i64
-  %arrayidx = getelementptr inbounds i16* %a, i64 %idxprom
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom
   store i16 %tmp, i16* %arrayidx, align 2
   ret void
 }
@@ -177,20 +179,21 @@ define void @store4(i16* nocapture %a, i64 %i, float %val) nounwind {
 ; CHECK-NEXT: ret
 
   %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %val)
-  %arrayidx = getelementptr inbounds i16* %a, i64 %i
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 %i
   store i16 %tmp, i16* %arrayidx, align 2
   ret void
 }
 
 define void @store5(i16* nocapture %a, i64 %i, double %val) nounwind {
 ; CHECK-LABEL: store5:
-; CHECK-NEXT: fcvt h0, d0
+; CHECK-NEXT: fcvt s0, d0
+; CHECK-NEXT: fcvt h0, s0
 ; CHECK-NEXT: str h0, [x0, x1, lsl #1]
 ; CHECK-NEXT: ret
 
   %conv = fptrunc double %val to float
   %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %conv)
-  %arrayidx = getelementptr inbounds i16* %a, i64 %i
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 %i
   store i16 %tmp, i16* %arrayidx, align 2
   ret void
 }
@@ -202,20 +205,21 @@ define void @store6(i16* nocapture %a, float %val) nounwind {
 ; CHECK-NEXT: ret
 
   %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %val)
-  %arrayidx = getelementptr inbounds i16* %a, i64 10
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 10
   store i16 %tmp, i16* %arrayidx, align 2
   ret void
 }
 
 define void @store7(i16* nocapture %a, double %val) nounwind {
 ; CHECK-LABEL: store7:
-; CHECK-NEXT: fcvt h0, d0
+; CHECK-NEXT: fcvt s0, d0
+; CHECK-NEXT: fcvt h0, s0
 ; CHECK-NEXT: str h0, [x0, #20]
 ; CHECK-NEXT: ret
 
   %conv = fptrunc double %val to float
   %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %conv)
-  %arrayidx = getelementptr inbounds i16* %a, i64 10
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 10
   store i16 %tmp, i16* %arrayidx, align 2
   ret void
 }
@@ -227,20 +231,21 @@ define void @store8(i16* nocapture %a, float %val) nounwind {
 ; CHECK-NEXT: ret
 
   %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %val)
-  %arrayidx = getelementptr inbounds i16* %a, i64 -10
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 -10
   store i16 %tmp, i16* %arrayidx, align 2
   ret void
 }
 
 define void @store9(i16* nocapture %a, double %val) nounwind {
 ; CHECK-LABEL: store9:
-; CHECK-NEXT: fcvt h0, d0
+; CHECK-NEXT: fcvt s0, d0
+; CHECK-NEXT: fcvt h0, s0
 ; CHECK-NEXT: stur h0, [x0, #-20]
 ; CHECK-NEXT: ret
 
   %conv = fptrunc double %val to float
   %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %conv)
-  %arrayidx = getelementptr inbounds i16* %a, i64 -10
+  %arrayidx = getelementptr inbounds i16, i16* %a, i64 -10
   store i16 %tmp, i16* %arrayidx, align 2
   ret void
 }
diff --git a/test/CodeGen/AArch64/f16-instructions.ll b/test/CodeGen/AArch64/f16-instructions.ll
new file mode 100644
index 000000000000..be5e2e51385d
--- /dev/null
+++ b/test/CodeGen/AArch64/f16-instructions.ll
@@ -0,0 +1,765 @@
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+; CHECK-LABEL: test_fadd:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fadd s0, s0, s1
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_fadd(half %a, half %b) #0 {
+  %r = fadd half %a, %b
+  ret half %r
+}
+
+; CHECK-LABEL: test_fsub:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fsub s0, s0, s1
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_fsub(half %a, half %b) #0 {
+  %r = fsub half %a, %b
+  ret half %r
+}
+
+; CHECK-LABEL: test_fmul:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fmul s0, s0, s1
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_fmul(half %a, half %b) #0 {
+  %r = fmul half %a, %b
+  ret half %r
+}
+
+; CHECK-LABEL: test_fdiv:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fdiv s0, s0, s1
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_fdiv(half %a, half %b) #0 {
+  %r = fdiv half %a, %b
+  ret half %r
+}
+
+; CHECK-LABEL: test_frem:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: mov  x29, sp
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: bl {{_?}}fmodf
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ldp x29, x30, [sp], #16
+; CHECK-NEXT: ret
+define half @test_frem(half %a, half %b) #0 {
+  %r = frem half %a, %b
+  ret half %r
+}
+
+; CHECK-LABEL: test_store:
+; CHECK-NEXT: str  h0, [x0]
+; CHECK-NEXT: ret
+define void @test_store(half %a, half* %b) #0 {
+  store half %a, half* %b
+  ret void
+}
+
+; CHECK-LABEL: test_load:
+; CHECK-NEXT: ldr  h0, [x0]
+; CHECK-NEXT: ret
+define half @test_load(half* %a) #0 {
+  %r = load half, half* %a
+  ret half %r
+}
+
+
+declare half @test_callee(half %a, half %b) #0
+
+; CHECK-LABEL: test_call:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: mov  x29, sp
+; CHECK-NEXT: bl {{_?}}test_callee
+; CHECK-NEXT: ldp x29, x30, [sp], #16
+; CHECK-NEXT: ret
+define half @test_call(half %a, half %b) #0 {
+  %r = call half @test_callee(half %a, half %b)
+  ret half %r
+}
+
+; CHECK-LABEL: test_call_flipped:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: mov  x29, sp
+; CHECK-NEXT: mov.16b  v2, v0
+; CHECK-NEXT: mov.16b  v0, v1
+; CHECK-NEXT: mov.16b  v1, v2
+; CHECK-NEXT: bl {{_?}}test_callee
+; CHECK-NEXT: ldp x29, x30, [sp], #16
+; CHECK-NEXT: ret
+define half @test_call_flipped(half %a, half %b) #0 {
+  %r = call half @test_callee(half %b, half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_tailcall_flipped:
+; CHECK-NEXT: mov.16b  v2, v0
+; CHECK-NEXT: mov.16b  v0, v1
+; CHECK-NEXT: mov.16b  v1, v2
+; CHECK-NEXT: b {{_?}}test_callee
+define half @test_tailcall_flipped(half %a, half %b) #0 {
+  %r = tail call half @test_callee(half %b, half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_select:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: cmp  w0, #0
+; CHECK-NEXT: fcsel s0, s0, s1, ne
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_select(half %a, half %b, i1 zeroext %c) #0 {
+  %r = select i1 %c, half %a, half %b
+  ret half %r
+}
+
+; CHECK-LABEL: test_select_cc:
+; CHECK-DAG: fcvt s3, h3
+; CHECK-DAG: fcvt s2, h2
+; CHECK-DAG: fcvt s1, h1
+; CHECK-DAG: fcvt s0, h0
+; CHECK-DAG: fcmp s2, s3
+; CHECK-DAG: cset [[CC:w[0-9]+]], ne
+; CHECK-DAG: cmp [[CC]], #0
+; CHECK-NEXT: fcsel s0, s0, s1, ne
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_select_cc(half %a, half %b, half %c, half %d) #0 {
+  %cc = fcmp une half %c, %d
+  %r = select i1 %cc, half %a, half %b
+  ret half %r
+}
+
+; CHECK-LABEL: test_fcmp_une:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: cset  w0, ne
+; CHECK-NEXT: ret
+define i1 @test_fcmp_une(half %a, half %b) #0 {
+  %r = fcmp une half %a, %b
+  ret i1 %r
+}
+
+; CHECK-LABEL: test_fcmp_ueq:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: orr [[TRUE:w[0-9]+]], wzr, #0x1
+; CHECK-NEXT: csel [[CC:w[0-9]+]], [[TRUE]], wzr, eq
+; CHECK-NEXT: csel w0, [[TRUE]], [[CC]], vs
+; CHECK-NEXT: ret
+define i1 @test_fcmp_ueq(half %a, half %b) #0 {
+  %r = fcmp ueq half %a, %b
+  ret i1 %r
+}
+
+; CHECK-LABEL: test_fcmp_ugt:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: cset  w0, hi
+; CHECK-NEXT: ret
+define i1 @test_fcmp_ugt(half %a, half %b) #0 {
+  %r = fcmp ugt half %a, %b
+  ret i1 %r
+}
+
+; CHECK-LABEL: test_fcmp_uge:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: cset  w0, pl
+; CHECK-NEXT: ret
+define i1 @test_fcmp_uge(half %a, half %b) #0 {
+  %r = fcmp uge half %a, %b
+  ret i1 %r
+}
+
+; CHECK-LABEL: test_fcmp_ult:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: cset  w0, lt
+; CHECK-NEXT: ret
+define i1 @test_fcmp_ult(half %a, half %b) #0 {
+  %r = fcmp ult half %a, %b
+  ret i1 %r
+}
+
+; CHECK-LABEL: test_fcmp_ule:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: cset  w0, le
+; CHECK-NEXT: ret
+define i1 @test_fcmp_ule(half %a, half %b) #0 {
+  %r = fcmp ule half %a, %b
+  ret i1 %r
+}
+
+
+; CHECK-LABEL: test_fcmp_uno:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: cset  w0, vs
+; CHECK-NEXT: ret
+define i1 @test_fcmp_uno(half %a, half %b) #0 {
+  %r = fcmp uno half %a, %b
+  ret i1 %r
+}
+
+; CHECK-LABEL: test_fcmp_one:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: orr [[TRUE:w[0-9]+]], wzr, #0x1
+; CHECK-NEXT: csel [[CC:w[0-9]+]], [[TRUE]], wzr, mi
+; CHECK-NEXT: csel w0, [[TRUE]], [[CC]], gt
+; CHECK-NEXT: ret
+define i1 @test_fcmp_one(half %a, half %b) #0 {
+  %r = fcmp one half %a, %b
+  ret i1 %r
+}
+
+; CHECK-LABEL: test_fcmp_oeq:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: cset  w0, eq
+; CHECK-NEXT: ret
+define i1 @test_fcmp_oeq(half %a, half %b) #0 {
+  %r = fcmp oeq half %a, %b
+  ret i1 %r
+}
+
+; CHECK-LABEL: test_fcmp_ogt:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: cset  w0, gt
+; CHECK-NEXT: ret
+define i1 @test_fcmp_ogt(half %a, half %b) #0 {
+  %r = fcmp ogt half %a, %b
+  ret i1 %r
+}
+
+; CHECK-LABEL: test_fcmp_oge:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: cset  w0, ge
+; CHECK-NEXT: ret
+define i1 @test_fcmp_oge(half %a, half %b) #0 {
+  %r = fcmp oge half %a, %b
+  ret i1 %r
+}
+
+; CHECK-LABEL: test_fcmp_olt:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: cset  w0, mi
+; CHECK-NEXT: ret
+define i1 @test_fcmp_olt(half %a, half %b) #0 {
+  %r = fcmp olt half %a, %b
+  ret i1 %r
+}
+
+; CHECK-LABEL: test_fcmp_ole:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: cset  w0, ls
+; CHECK-NEXT: ret
+define i1 @test_fcmp_ole(half %a, half %b) #0 {
+  %r = fcmp ole half %a, %b
+  ret i1 %r
+}
+
+; CHECK-LABEL: test_fcmp_ord:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: cset  w0, vc
+; CHECK-NEXT: ret
+define i1 @test_fcmp_ord(half %a, half %b) #0 {
+  %r = fcmp ord half %a, %b
+  ret i1 %r
+}
+
+; CHECK-LABEL: test_br_cc:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: b.mi [[BRCC_ELSE:.?LBB[0-9_]+]]
+; CHECK-NEXT: str  wzr, [x0]
+; CHECK-NEXT: ret
+; CHECK-NEXT: [[BRCC_ELSE]]:
+; CHECK-NEXT: str  wzr, [x1]
+; CHECK-NEXT: ret
+define void @test_br_cc(half %a, half %b, i32* %p1, i32* %p2) #0 {
+  %c = fcmp uge half %a, %b
+  br i1 %c, label %then, label %else
+then:
+  store i32 0, i32* %p1
+  ret void
+else:
+  store i32 0, i32* %p2
+  ret void
+}
+
+; CHECK-LABEL: test_phi:
+; CHECK: mov  x[[PTR:[0-9]+]], x0
+; CHECK: ldr  h[[AB:[0-9]+]], [x[[PTR]]]
+; CHECK: [[LOOP:LBB[0-9_]+]]:
+; CHECK: mov.16b  v[[R:[0-9]+]], v[[AB]]
+; CHECK: ldr  h[[AB]], [x[[PTR]]]
+; CHECK: mov  x0, x[[PTR]]
+; CHECK: bl {{_?}}test_dummy
+; CHECK: mov.16b  v0, v[[R]]
+; CHECK: ret
+define half @test_phi(half* %p1) #0 {
+entry:
+  %a = load half, half* %p1
+  br label %loop
+loop:
+  %r = phi half [%a, %entry], [%b, %loop]
+  %b = load half, half* %p1
+  %c = call i1 @test_dummy(half* %p1)
+  br i1 %c, label %loop, label %return
+return:
+  ret half %r
+}
+declare i1 @test_dummy(half* %p1) #0
+
+; CHECK-LABEL: test_fptosi_i32:
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcvtzs w0, s0
+; CHECK-NEXT: ret
+define i32 @test_fptosi_i32(half %a) #0 {
+  %r = fptosi half %a to i32
+  ret i32 %r
+}
+
+; CHECK-LABEL: test_fptosi_i64:
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcvtzs x0, s0
+; CHECK-NEXT: ret
+define i64 @test_fptosi_i64(half %a) #0 {
+  %r = fptosi half %a to i64
+  ret i64 %r
+}
+
+; CHECK-LABEL: test_fptoui_i32:
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcvtzu w0, s0
+; CHECK-NEXT: ret
+define i32 @test_fptoui_i32(half %a) #0 {
+  %r = fptoui half %a to i32
+  ret i32 %r
+}
+
+; CHECK-LABEL: test_fptoui_i64:
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcvtzu x0, s0
+; CHECK-NEXT: ret
+define i64 @test_fptoui_i64(half %a) #0 {
+  %r = fptoui half %a to i64
+  ret i64 %r
+}
+
+; CHECK-LABEL: test_uitofp_i32:
+; CHECK-NEXT: ucvtf s0, w0
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_uitofp_i32(i32 %a) #0 {
+  %r = uitofp i32 %a to half
+  ret half %r
+}
+
+; CHECK-LABEL: test_uitofp_i64:
+; CHECK-NEXT: ucvtf s0, x0
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_uitofp_i64(i64 %a) #0 {
+  %r = uitofp i64 %a to half
+  ret half %r
+}
+
+; CHECK-LABEL: test_sitofp_i32:
+; CHECK-NEXT: scvtf s0, w0
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_sitofp_i32(i32 %a) #0 {
+  %r = sitofp i32 %a to half
+  ret half %r
+}
+
+; CHECK-LABEL: test_sitofp_i64:
+; CHECK-NEXT: scvtf s0, x0
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_sitofp_i64(i64 %a) #0 {
+  %r = sitofp i64 %a to half
+  ret half %r
+}
+
+; CHECK-LABEL: test_fptrunc_float:
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+
+define half @test_fptrunc_float(float %a) #0 {
+  %r = fptrunc float %a to half
+  ret half %r
+}
+
+; CHECK-LABEL: test_fptrunc_double:
+; CHECK-NEXT: fcvt h0, d0
+; CHECK-NEXT: ret
+define half @test_fptrunc_double(double %a) #0 {
+  %r = fptrunc double %a to half
+  ret half %r
+}
+
+; CHECK-LABEL: test_fpext_float:
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: ret
+define float @test_fpext_float(half %a) #0 {
+  %r = fpext half %a to float
+  ret float %r
+}
+
+; CHECK-LABEL: test_fpext_double:
+; CHECK-NEXT: fcvt d0, h0
+; CHECK-NEXT: ret
+define double @test_fpext_double(half %a) #0 {
+  %r = fpext half %a to double
+  ret double %r
+}
+
+
+; CHECK-LABEL: test_bitcast_halftoi16:
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
+define i16 @test_bitcast_halftoi16(half %a) #0 {
+  %r = bitcast half %a to i16
+  ret i16 %r
+}
+
+; CHECK-LABEL: test_bitcast_i16tohalf:
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: ret
+define half @test_bitcast_i16tohalf(i16 %a) #0 {
+  %r = bitcast i16 %a to half
+  ret half %r
+}
+
+
+declare half @llvm.sqrt.f16(half %a) #0
+declare half @llvm.powi.f16(half %a, i32 %b) #0
+declare half @llvm.sin.f16(half %a) #0
+declare half @llvm.cos.f16(half %a) #0
+declare half @llvm.pow.f16(half %a, half %b) #0
+declare half @llvm.exp.f16(half %a) #0
+declare half @llvm.exp2.f16(half %a) #0
+declare half @llvm.log.f16(half %a) #0
+declare half @llvm.log10.f16(half %a) #0
+declare half @llvm.log2.f16(half %a) #0
+declare half @llvm.fma.f16(half %a, half %b, half %c) #0
+declare half @llvm.fabs.f16(half %a) #0
+declare half @llvm.minnum.f16(half %a, half %b) #0
+declare half @llvm.maxnum.f16(half %a, half %b) #0
+declare half @llvm.copysign.f16(half %a, half %b) #0
+declare half @llvm.floor.f16(half %a) #0
+declare half @llvm.ceil.f16(half %a) #0
+declare half @llvm.trunc.f16(half %a) #0
+declare half @llvm.rint.f16(half %a) #0
+declare half @llvm.nearbyint.f16(half %a) #0
+declare half @llvm.round.f16(half %a) #0
+declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #0
+
+; CHECK-LABEL: test_sqrt:
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fsqrt s0, s0
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_sqrt(half %a) #0 {
+  %r = call half @llvm.sqrt.f16(half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_powi:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: mov  x29, sp
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: bl {{_?}}__powisf2
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ldp x29, x30, [sp], #16
+; CHECK-NEXT: ret
+define half @test_powi(half %a, i32 %b) #0 {
+  %r = call half @llvm.powi.f16(half %a, i32 %b)
+  ret half %r
+}
+
+; CHECK-LABEL: test_sin:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: mov  x29, sp
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: bl {{_?}}sinf
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ldp x29, x30, [sp], #16
+; CHECK-NEXT: ret
+define half @test_sin(half %a) #0 {
+  %r = call half @llvm.sin.f16(half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_cos:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: mov  x29, sp
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: bl {{_?}}cosf
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ldp x29, x30, [sp], #16
+; CHECK-NEXT: ret
+define half @test_cos(half %a) #0 {
+  %r = call half @llvm.cos.f16(half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_pow:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: mov  x29, sp
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: bl {{_?}}powf
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ldp x29, x30, [sp], #16
+; CHECK-NEXT: ret
+define half @test_pow(half %a, half %b) #0 {
+  %r = call half @llvm.pow.f16(half %a, half %b)
+  ret half %r
+}
+
+; CHECK-LABEL: test_exp:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: mov  x29, sp
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: bl {{_?}}expf
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ldp x29, x30, [sp], #16
+; CHECK-NEXT: ret
+define half @test_exp(half %a) #0 {
+  %r = call half @llvm.exp.f16(half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_exp2:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: mov  x29, sp
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: bl {{_?}}exp2f
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ldp x29, x30, [sp], #16
+; CHECK-NEXT: ret
+define half @test_exp2(half %a) #0 {
+  %r = call half @llvm.exp2.f16(half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_log:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: mov  x29, sp
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: bl {{_?}}logf
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ldp x29, x30, [sp], #16
+; CHECK-NEXT: ret
+define half @test_log(half %a) #0 {
+  %r = call half @llvm.log.f16(half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_log10:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: mov  x29, sp
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: bl {{_?}}log10f
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ldp x29, x30, [sp], #16
+; CHECK-NEXT: ret
+define half @test_log10(half %a) #0 {
+  %r = call half @llvm.log10.f16(half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_log2:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: mov  x29, sp
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: bl {{_?}}log2f
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ldp x29, x30, [sp], #16
+; CHECK-NEXT: ret
+define half @test_log2(half %a) #0 {
+  %r = call half @llvm.log2.f16(half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_fma:
+; CHECK-NEXT: fcvt s2, h2
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fmadd s0, s0, s1, s2
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_fma(half %a, half %b, half %c) #0 {
+  %r = call half @llvm.fma.f16(half %a, half %b, half %c)
+  ret half %r
+}
+
+; CHECK-LABEL: test_fabs:
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fabs s0, s0
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_fabs(half %a) #0 {
+  %r = call half @llvm.fabs.f16(half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_minnum:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: mov  x29, sp
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: bl {{_?}}fminf
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ldp x29, x30, [sp], #16
+; CHECK-NEXT: ret
+define half @test_minnum(half %a, half %b) #0 {
+  %r = call half @llvm.minnum.f16(half %a, half %b)
+  ret half %r
+}
+
+; CHECK-LABEL: test_maxnum:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: mov  x29, sp
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: bl {{_?}}fmaxf
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ldp x29, x30, [sp], #16
+; CHECK-NEXT: ret
+define half @test_maxnum(half %a, half %b) #0 {
+  %r = call half @llvm.maxnum.f16(half %a, half %b)
+  ret half %r
+}
+
+; CHECK-LABEL: test_copysign:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: movi.4s v2, #0x80, lsl #24
+; CHECK-NEXT: bit.16b v0, v1, v2
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_copysign(half %a, half %b) #0 {
+  %r = call half @llvm.copysign.f16(half %a, half %b)
+  ret half %r
+}
+
+; CHECK-LABEL: test_floor:
+; CHECK-NEXT: fcvt s1, h0
+; CHECK-NEXT: frintm s0, s1
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: frintx s1, s1
+; CHECK-NEXT: ret
+define half @test_floor(half %a) #0 {
+  %r = call half @llvm.floor.f16(half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_ceil:
+; CHECK-NEXT: fcvt s1, h0
+; CHECK-NEXT: frintp s0, s1
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: frintx s1, s1
+; CHECK-NEXT: ret
+define half @test_ceil(half %a) #0 {
+  %r = call half @llvm.ceil.f16(half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_trunc:
+; CHECK-NEXT: fcvt s1, h0
+; CHECK-NEXT: frintz s0, s1
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: frintx s1, s1
+; CHECK-NEXT: ret
+define half @test_trunc(half %a) #0 {
+  %r = call half @llvm.trunc.f16(half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_rint:
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: frintx s0, s0
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_rint(half %a) #0 {
+  %r = call half @llvm.rint.f16(half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_nearbyint:
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: frinti s0, s0
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_nearbyint(half %a) #0 {
+  %r = call half @llvm.nearbyint.f16(half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_round:
+; CHECK-NEXT: fcvt s1, h0
+; CHECK-NEXT: frinta s0, s1
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: frintx s1, s1
+; CHECK-NEXT: ret
+define half @test_round(half %a) #0 {
+  %r = call half @llvm.round.f16(half %a)
+  ret half %r
+}
+
+; CHECK-LABEL: test_fmuladd:
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fmul s0, s0, s1
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcvt s1, h2
+; CHECK-NEXT: fadd s0, s0, s1
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_fmuladd(half %a, half %b, half %c) #0 {
+  %r = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
+  ret half %r
+}
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/AArch64/fast-isel-address-extends.ll b/test/CodeGen/AArch64/fast-isel-address-extends.ll
new file mode 100644
index 000000000000..6a17ec502a02
--- /dev/null
+++ b/test/CodeGen/AArch64/fast-isel-address-extends.ll
@@ -0,0 +1,39 @@
+; RUN: llc %s -o - -O0 -verify-machineinstrs -fast-isel=true | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-apple-ios8.0.0"
+
+; This test was trying to fold the sext %tmp142 in to the address arithmetic in %sunkaddr1.
+; This was incorrect as %.mux isn't available in the last bb.
+
+; CHECK: sxtw [[REG:x[0-9]+]]
+; CHECK: strh wzr, {{\[}}[[REG]], {{.*}}, lsl #1]
+
+; Function Attrs: nounwind optsize ssp
+define void @EdgeLoop(i32 %dir, i32 %edge, i32 %width, i16* %tmp89, i32 %tmp136, i16 %tmp144) #0 {
+bb:
+  %tmp2 = icmp eq i32 %dir, 0
+  %.mux = select i1 %tmp2, i32 %width, i32 1
+  %tmp142 = sext i32 %.mux to i64
+  %tmp151 = shl nsw i64 %tmp142, 1
+  %tmp153 = getelementptr inbounds i16, i16* %tmp89, i64 %tmp151
+  %tmp154 = load i16, i16* %tmp153, align 2
+  %tmp155 = zext i16 %tmp154 to i32
+  br i1 %tmp2, label %bb225, label %bb212
+
+bb212:                                            ; preds = %bb
+  store i16 %tmp144, i16* %tmp89, align 2
+  ret void
+
+bb225:                                            ; preds = %bb
+  %tmp248 = trunc i32 %tmp155 to i16
+  store i16 %tmp248, i16* %tmp89, align 2
+  %sunkaddr = ptrtoint i16* %tmp89 to i64
+  %sunkaddr1 = mul i64 %tmp142, 2
+  %sunkaddr2 = add i64 %sunkaddr, %sunkaddr1
+  %sunkaddr3 = inttoptr i64 %sunkaddr2 to i16*
+  store i16 0, i16* %sunkaddr3, align 2
+  ret void
+}
+
+attributes #0 = { nounwind optsize ssp }
diff --git a/test/CodeGen/AArch64/fast-isel-addressing-modes.ll b/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
index d86f00d38622..6ab6a66c355d 100644
--- a/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
+++ b/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
@@ -1,53 +1,53 @@
 ; RUN: llc -mtriple=aarch64-apple-darwin                             -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
 
 ; Load / Store Base Register only
 define zeroext i1 @load_breg_i1(i1* %a) {
 ; CHECK-LABEL: load_breg_i1
 ; CHECK:       ldrb {{w[0-9]+}}, [x0]
-  %1 = load i1* %a
+  %1 = load i1, i1* %a
   ret i1 %1
 }
 
 define zeroext i8 @load_breg_i8(i8* %a) {
 ; CHECK-LABEL: load_breg_i8
 ; CHECK:       ldrb {{w[0-9]+}}, [x0]
-  %1 = load i8* %a
+  %1 = load i8, i8* %a
   ret i8 %1
 }
 
 define zeroext i16 @load_breg_i16(i16* %a) {
 ; CHECK-LABEL: load_breg_i16
 ; CHECK:       ldrh {{w[0-9]+}}, [x0]
-  %1 = load i16* %a
+  %1 = load i16, i16* %a
   ret i16 %1
 }
 
 define i32 @load_breg_i32(i32* %a) {
 ; CHECK-LABEL: load_breg_i32
 ; CHECK:       ldr {{w[0-9]+}}, [x0]
-  %1 = load i32* %a
+  %1 = load i32, i32* %a
   ret i32 %1
 }
 
 define i64 @load_breg_i64(i64* %a) {
 ; CHECK-LABEL: load_breg_i64
 ; CHECK:       ldr {{x[0-9]+}}, [x0]
-  %1 = load i64* %a
+  %1 = load i64, i64* %a
   ret i64 %1
 }
 
 define float @load_breg_f32(float* %a) {
 ; CHECK-LABEL: load_breg_f32
 ; CHECK:       ldr {{s[0-9]+}}, [x0]
-  %1 = load float* %a
+  %1 = load float, float* %a
   ret float %1
 }
 
 define double @load_breg_f64(double* %a) {
 ; CHECK-LABEL: load_breg_f64
 ; CHECK:       ldr {{d[0-9]+}}, [x0]
-  %1 = load double* %a
+  %1 = load double, double* %a
   ret double %1
 }
 
@@ -113,7 +113,7 @@ define i32 @load_immoff_1() {
 ; CHECK:       orr {{w|x}}[[REG:[0-9]+]], {{wzr|xzr}}, #0x80
 ; CHECK:       ldr {{w[0-9]+}}, {{\[}}x[[REG]]{{\]}}
   %1 = inttoptr i64 128 to i32*
-  %2 = load i32* %1
+  %2 = load i32, i32* %1
   ret i32 %2
 }
 
@@ -124,7 +124,7 @@ define i32 @load_breg_immoff_1(i64 %a) {
 ; CHECK:       ldur {{w[0-9]+}}, [x0, #-256]
   %1 = add i64 %a, -256
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   ret i32 %3
 }
 
@@ -135,7 +135,7 @@ define i32 @load_breg_immoff_2(i64 %a) {
 ; CHECK-NEXT:  ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
   %1 = add i64 %a, -257
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   ret i32 %3
 }
 
@@ -145,7 +145,7 @@ define i32 @load_breg_immoff_3(i64 %a) {
 ; CHECK:       ldur {{w[0-9]+}}, [x0, #255]
   %1 = add i64 %a, 255
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   ret i32 %3
 }
 
@@ -156,7 +156,7 @@ define i32 @load_breg_immoff_4(i64 %a) {
 ; CHECK-NEXT:  ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
   %1 = add i64 %a, 257
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   ret i32 %3
 }
 
@@ -166,7 +166,7 @@ define i32 @load_breg_immoff_5(i64 %a) {
 ; CHECK:       ldr {{w[0-9]+}}, [x0, #16380]
   %1 = add i64 %a, 16380
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   ret i32 %3
 }
 
@@ -180,7 +180,7 @@ define i32 @load_breg_immoff_6(i64 %a) {
 ; FAST-NEXT:  ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
   %1 = add i64 %a, 16384
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   ret i32 %3
 }
 
@@ -255,7 +255,7 @@ define i64 @load_breg_immoff_7(i64 %a) {
 ; CHECK:       ldr {{x[0-9]+}}, [x0, #48]
   %1 = add i64 %a, 48
   %2 = inttoptr i64 %1 to i64*
-  %3 = load i64* %2
+  %3 = load i64, i64* %2
   ret i64 %3
 }
 
@@ -265,7 +265,7 @@ define i64 @load_breg_immoff_8(i64 %a) {
 ; CHECK:       ldr {{x[0-9]+}}, [x0, #48]
   %1 = add i64 48, %a
   %2 = inttoptr i64 %1 to i64*
-  %3 = load i64* %2
+  %3 = load i64, i64* %2
   ret i64 %3
 }
 
@@ -275,7 +275,7 @@ define i64 @load_breg_offreg_1(i64 %a, i64 %b) {
 ; CHECK:       ldr {{x[0-9]+}}, [x0, x1]
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i64*
-  %3 = load i64* %2
+  %3 = load i64, i64* %2
   ret i64 %3
 }
 
@@ -285,7 +285,7 @@ define i64 @load_breg_offreg_2(i64 %a, i64 %b) {
 ; CHECK:       ldr {{x[0-9]+}}, [x1, x0]
   %1 = add i64 %b, %a
   %2 = inttoptr i64 %1 to i64*
-  %3 = load i64* %2
+  %3 = load i64, i64* %2
   ret i64 %3
 }
 
@@ -297,7 +297,7 @@ define i64 @load_breg_offreg_immoff_1(i64 %a, i64 %b) {
   %1 = add i64 %a, %b
   %2 = add i64 %1, 48
   %3 = inttoptr i64 %2 to i64*
-  %4 = load i64* %3
+  %4 = load i64, i64* %3
   ret i64 %4
 }
 
@@ -312,7 +312,7 @@ define i64 @load_breg_offreg_immoff_2(i64 %a, i64 %b) {
   %1 = add i64 %a, %b
   %2 = add i64 %1, 61440
   %3 = inttoptr i64 %2 to i64*
-  %4 = load i64* %3
+  %4 = load i64, i64* %3
   ret i64 %4
 }
 
@@ -323,7 +323,7 @@ define i32 @load_shift_offreg_1(i64 %a) {
 ; CHECK:       ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
   %1 = shl i64 %a, 2
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   ret i32 %3
 }
 
@@ -333,7 +333,7 @@ define i32 @load_mul_offreg_1(i64 %a) {
 ; CHECK:       ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
   %1 = mul i64 %a, 4
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   ret i32 %3
 }
 
@@ -344,7 +344,7 @@ define i32 @load_breg_shift_offreg_1(i64 %a, i64 %b) {
   %1 = shl i64 %a, 2
   %2 = add i64 %1, %b
   %3 = inttoptr i64 %2 to i32*
-  %4 = load i32* %3
+  %4 = load i32, i32* %3
   ret i32 %4
 }
 
@@ -354,7 +354,7 @@ define i32 @load_breg_shift_offreg_2(i64 %a, i64 %b) {
   %1 = shl i64 %a, 2
   %2 = add i64 %b, %1
   %3 = inttoptr i64 %2 to i32*
-  %4 = load i32* %3
+  %4 = load i32, i32* %3
   ret i32 %4
 }
 
@@ -369,7 +369,7 @@ define i32 @load_breg_shift_offreg_3(i64 %a, i64 %b) {
   %2 = shl i64 %b, 2
   %3 = add i64 %1, %2
   %4 = inttoptr i64 %3 to i32*
-  %5 = load i32* %4
+  %5 = load i32, i32* %4
   ret i32 %5
 }
 
@@ -384,7 +384,7 @@ define i32 @load_breg_shift_offreg_4(i64 %a, i64 %b) {
   %2 = shl i64 %b, 2
   %3 = add i64 %2, %1
   %4 = inttoptr i64 %3 to i32*
-  %5 = load i32* %4
+  %5 = load i32, i32* %4
   ret i32 %5
 }
 
@@ -399,7 +399,7 @@ define i32 @load_breg_shift_offreg_5(i64 %a, i64 %b) {
   %2 = shl i64 %b, 3
   %3 = add i64 %1, %2
   %4 = inttoptr i64 %3 to i32*
-  %5 = load i32* %4
+  %5 = load i32, i32* %4
   ret i32 %5
 }
 
@@ -409,7 +409,7 @@ define i32 @load_breg_mul_offreg_1(i64 %a, i64 %b) {
   %1 = mul i64 %a, 4
   %2 = add i64 %1, %b
   %3 = inttoptr i64 %2 to i32*
-  %4 = load i32* %3
+  %4 = load i32, i32* %3
   ret i32 %4
 }
 
@@ -419,7 +419,7 @@ define zeroext i8 @load_breg_and_offreg_1(i64 %a, i64 %b) {
   %1 = and i64 %a, 4294967295
   %2 = add i64 %1, %b
   %3 = inttoptr i64 %2 to i8*
-  %4 = load i8* %3
+  %4 = load i8, i8* %3
   ret i8 %4
 }
 
@@ -430,7 +430,7 @@ define zeroext i16 @load_breg_and_offreg_2(i64 %a, i64 %b) {
   %2 = shl i64 %1, 1
   %3 = add i64 %2, %b
   %4 = inttoptr i64 %3 to i16*
-  %5 = load i16* %4
+  %5 = load i16, i16* %4
   ret i16 %5
 }
 
@@ -441,7 +441,7 @@ define i32 @load_breg_and_offreg_3(i64 %a, i64 %b) {
   %2 = shl i64 %1, 2
   %3 = add i64 %2, %b
   %4 = inttoptr i64 %3 to i32*
-  %5 = load i32* %4
+  %5 = load i32, i32* %4
   ret i32 %5
 }
 
@@ -452,7 +452,7 @@ define i64 @load_breg_and_offreg_4(i64 %a, i64 %b) {
   %2 = shl i64 %1, 3
   %3 = add i64 %2, %b
   %4 = inttoptr i64 %3 to i64*
-  %5 = load i64* %4
+  %5 = load i64, i64* %4
   ret i64 %5
 }
 
@@ -464,7 +464,7 @@ define i64 @load_breg_and_offreg_5(i64 %a, i64 %b, i64 %c) {
   %1 = and i64 %a, %c
   %2 = add i64 %1, %b
   %3 = inttoptr i64 %2 to i64*
-  %4 = load i64* %3
+  %4 = load i64, i64* %3
   ret i64 %4
 }
 
@@ -476,7 +476,7 @@ define i64 @load_breg_and_offreg_6(i64 %a, i64 %b, i64 %c) {
   %2 = shl i64 %1, 3
   %3 = add i64 %2, %b
   %4 = inttoptr i64 %3 to i64*
-  %5 = load i64* %4
+  %5 = load i64, i64* %4
   ret i64 %5
 }
 
@@ -488,7 +488,7 @@ define i32 @load_breg_zext_shift_offreg_1(i32 %a, i64 %b) {
   %2 = shl i64 %1, 2
   %3 = add i64 %2, %b
   %4 = inttoptr i64 %3 to i32*
-  %5 = load i32* %4
+  %5 = load i32, i32* %4
   ret i32 %5
 }
 
@@ -499,7 +499,7 @@ define i32 @load_breg_zext_shift_offreg_2(i32 %a, i64 %b) {
   %2 = shl i64 %1, 2
   %3 = add i64 %b, %2
   %4 = inttoptr i64 %3 to i32*
-  %5 = load i32* %4
+  %5 = load i32, i32* %4
   ret i32 %5
 }
 
@@ -510,7 +510,7 @@ define i32 @load_breg_zext_mul_offreg_1(i32 %a, i64 %b) {
   %2 = mul i64 %1, 4
   %3 = add i64 %2, %b
   %4 = inttoptr i64 %3 to i32*
-  %5 = load i32* %4
+  %5 = load i32, i32* %4
   ret i32 %5
 }
 
@@ -521,7 +521,7 @@ define i32 @load_breg_sext_shift_offreg_1(i32 %a, i64 %b) {
   %2 = shl i64 %1, 2
   %3 = add i64 %2, %b
   %4 = inttoptr i64 %3 to i32*
-  %5 = load i32* %4
+  %5 = load i32, i32* %4
   ret i32 %5
 }
 
@@ -532,7 +532,7 @@ define i32 @load_breg_sext_shift_offreg_2(i32 %a, i64 %b) {
   %2 = shl i64 %1, 2
   %3 = add i64 %b, %2
   %4 = inttoptr i64 %3 to i32*
-  %5 = load i32* %4
+  %5 = load i32, i32* %4
   ret i32 %5
 }
 
@@ -546,7 +546,7 @@ define i32 @load_breg_sext_shift_offreg_3(i32 %a, i64 %b) {
   %3 = shl i64 %2, 2
   %4 = add i64 %b, %3
   %5 = inttoptr i64 %4 to i32*
-  %6 = load i32* %5
+  %6 = load i32, i32* %5
   ret i32 %6
 }
 
@@ -558,7 +558,7 @@ define i32 @load_breg_sext_mul_offreg_1(i32 %a, i64 %b) {
   %2 = mul i64 %1, 4
   %3 = add i64 %2, %b
   %4 = inttoptr i64 %3 to i32*
-  %5 = load i32* %4
+  %5 = load i32, i32* %4
   ret i32 %5
 }
 
@@ -571,7 +571,7 @@ define i64 @load_sext_shift_offreg_imm1(i32 %a) {
   %2 = shl i64 %1, 3
   %3 = add i64 %2, 8
   %4 = inttoptr i64 %3 to i64*
-  %5 = load i64* %4
+  %5 = load i64, i64* %4
   ret i64 %5
 }
 
@@ -585,7 +585,7 @@ define i64 @load_breg_sext_shift_offreg_imm1(i32 %a, i64 %b) {
   %3 = add i64 %b, %2
   %4 = add i64 %3, 8
   %5 = inttoptr i64 %4 to i64*
-  %6 = load i64* %5
+  %6 = load i64, i64* %5
   ret i64 %6
 }
 
@@ -594,7 +594,7 @@ define i64 @kill_reg(i64 %a) {
   %1 = sub i64 %a, 8
   %2 = add i64 %1, 96
   %3 = inttoptr i64 %2 to i64*
-  %4 = load i64* %3
+  %4 = load i64, i64* %3
   %5 = add i64 %2, %4
   ret i64 %5
 }
@@ -621,7 +621,7 @@ define i32 @load_fi(i64 %i) {
   %3 = mul i64 %i, 4
   %4 = add i64 %2, %3
   %5 = inttoptr i64 %4 to i32*
-  %6 = load i32* %5, align 4
+  %6 = load i32, i32* %5, align 4
   ret i32 %6
 }
 
diff --git a/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll b/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll
index bc4a210df62b..da6ddbf5101e 100644
--- a/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll
+++ b/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 ; CHECK-label: test_or
 ; CHECK:       cbnz w0, {{LBB[0-9]+_2}}
diff --git a/test/CodeGen/AArch64/fast-isel-branch_weights.ll b/test/CodeGen/AArch64/fast-isel-branch_weights.ll
index 70dbdf216c7d..ff57bbb33c48 100644
--- a/test/CodeGen/AArch64/fast-isel-branch_weights.ll
+++ b/test/CodeGen/AArch64/fast-isel-branch_weights.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0                             -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 ; Test if the BBs are reordred according to their branch weights.
 define i64 @branch_weights_test(i64 %a, i64 %b) {
diff --git a/test/CodeGen/AArch64/fast-isel-call-return.ll b/test/CodeGen/AArch64/fast-isel-call-return.ll
index 9b10969417df..a03b12e8d3ea 100644
--- a/test/CodeGen/AArch64/fast-isel-call-return.ll
+++ b/test/CodeGen/AArch64/fast-isel-call-return.ll
@@ -1,4 +1,4 @@
-; RUN: llc -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-linux-gnu"
 
diff --git a/test/CodeGen/AArch64/fast-isel-cbz.ll b/test/CodeGen/AArch64/fast-isel-cbz.ll
index 6e31a045d285..a407b269dd82 100644
--- a/test/CodeGen/AArch64/fast-isel-cbz.ll
+++ b/test/CodeGen/AArch64/fast-isel-cbz.ll
@@ -1,4 +1,4 @@
-; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s
+; RUN: llc -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s
 
 define i32 @icmp_eq_i1(i1 %a) {
 ; CHECK-LABEL: icmp_eq_i1
diff --git a/test/CodeGen/AArch64/fast-isel-cmp-branch.ll b/test/CodeGen/AArch64/fast-isel-cmp-branch.ll
index 3651f194efda..1ac358f37aa8 100644
--- a/test/CodeGen/AArch64/fast-isel-cmp-branch.ll
+++ b/test/CodeGen/AArch64/fast-isel-cmp-branch.ll
@@ -1,5 +1,5 @@
 ; RUN: llc                             -aarch64-atomic-cfg-tidy=0 -mtriple=aarch64-apple-darwin < %s | FileCheck %s
-; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -mtriple=aarch64-apple-darwin < %s | FileCheck %s
+; RUN: llc -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=0 -mtriple=aarch64-apple-darwin < %s | FileCheck %s
 
 define i32 @fcmp_oeq(float %x, float %y) {
 ; CHECK-LABEL: fcmp_oeq
diff --git a/test/CodeGen/AArch64/fast-isel-folding.ll b/test/CodeGen/AArch64/fast-isel-folding.ll
index 6b524ff2c099..883933b79923 100644
--- a/test/CodeGen/AArch64/fast-isel-folding.ll
+++ b/test/CodeGen/AArch64/fast-isel-folding.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-apple-darwin -O0 -fast-isel-abort -verify-machineinstrs < %s
+; RUN: llc -mtriple=aarch64-apple-darwin -O0 -fast-isel-abort=1 -verify-machineinstrs < %s
 
 ; Test that we don't fold the shift.
 define i64 @fold_shift_test(i64 %a, i1 %c) {
diff --git a/test/CodeGen/AArch64/fast-isel-gep.ll b/test/CodeGen/AArch64/fast-isel-gep.ll
index 4dc0a05894f1..33adcdc3c464 100644
--- a/test/CodeGen/AArch64/fast-isel-gep.ll
+++ b/test/CodeGen/AArch64/fast-isel-gep.ll
@@ -1,11 +1,11 @@
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 %struct.foo = type { i32, i64, float, double }
 
 define double* @test_struct(%struct.foo* %f) {
 ; CHECK-LABEL: test_struct
 ; CHECK:       add x0, x0, #24
-  %1 = getelementptr inbounds %struct.foo* %f, i64 0, i32 3
+  %1 = getelementptr inbounds %struct.foo, %struct.foo* %f, i64 0, i32 3
   ret double* %1
 }
 
@@ -13,21 +13,21 @@ define i32* @test_array1(i32* %a, i64 %i) {
 ; CHECK-LABEL: test_array1
 ; CHECK:       orr [[REG:x[0-9]+]], xzr, #0x4
 ; CHECK-NEXT:  madd  x0, x1, [[REG]], x0
-  %1 = getelementptr inbounds i32* %a, i64 %i
+  %1 = getelementptr inbounds i32, i32* %a, i64 %i
   ret i32* %1
 }
 
 define i32* @test_array2(i32* %a) {
 ; CHECK-LABEL: test_array2
 ; CHECK:       add  x0, x0, #16
-  %1 = getelementptr inbounds i32* %a, i64 4
+  %1 = getelementptr inbounds i32, i32* %a, i64 4
   ret i32* %1
 }
 
 define i32* @test_array3(i32* %a) {
 ; CHECK-LABEL: test_array3
 ; CHECK:       add x0, x0, #1, lsl #12
-  %1 = getelementptr inbounds i32* %a, i64 1024
+  %1 = getelementptr inbounds i32, i32* %a, i64 1024
   ret i32* %1
 }
 
@@ -35,7 +35,7 @@ define i32* @test_array4(i32* %a) {
 ; CHECK-LABEL: test_array4
 ; CHECK:       movz [[REG:x[0-9]+]], #0x1008
 ; CHECK-NEXR:  add x0, x0, [[REG]]
-  %1 = getelementptr inbounds i32* %a, i64 1026
+  %1 = getelementptr inbounds i32, i32* %a, i64 1026
   ret i32* %1
 }
 
@@ -44,6 +44,6 @@ define i32* @test_array5(i32* %a, i32 %i) {
 ; CHECK:       sxtw [[REG1:x[0-9]+]], w1
 ; CHECK-NEXT:  orr  [[REG2:x[0-9]+]], xzr, #0x4
 ; CHECK-NEXT:  madd  {{x[0-9]+}}, [[REG1]], [[REG2]], x0
-  %1 = getelementptr inbounds i32* %a, i32 %i
+  %1 = getelementptr inbounds i32, i32* %a, i32 %i
   ret i32* %1
 }
diff --git a/test/CodeGen/AArch64/fast-isel-int-ext.ll b/test/CodeGen/AArch64/fast-isel-int-ext.ll
index 866febac2622..4b2cab5fa728 100644
--- a/test/CodeGen/AArch64/fast-isel-int-ext.ll
+++ b/test/CodeGen/AArch64/fast-isel-int-ext.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 ;
 ; Test that we only use the sign/zero extend in the address calculation when
@@ -13,7 +13,7 @@ define i64 @load_addr_shift_zext1(i32 %a, i64 %b) {
   %2 = shl i64 %1, 3
   %3 = add i64 %b, %2
   %4 = inttoptr i64 %3 to i64*
-  %5 = load i64* %4
+  %5 = load i64, i64* %4
   ret i64 %5
 }
 
@@ -24,7 +24,7 @@ define i64 @load_addr_shift_zext2(i32 zeroext %a, i64 %b) {
   %2 = shl i64 %1, 3
   %3 = add i64 %b, %2
   %4 = inttoptr i64 %3 to i64*
-  %5 = load i64* %4
+  %5 = load i64, i64* %4
   ret i64 %5
 }
 
@@ -35,7 +35,7 @@ define i64 @load_addr_shift_zext3(i32 signext %a, i64 %b) {
   %2 = shl i64 %1, 3
   %3 = add i64 %b, %2
   %4 = inttoptr i64 %3 to i64*
-  %5 = load i64* %4
+  %5 = load i64, i64* %4
   ret i64 %5
 }
 
@@ -46,7 +46,7 @@ define i64 @load_addr_shift_sext1(i32 %a, i64 %b) {
   %2 = shl i64 %1, 3
   %3 = add i64 %b, %2
   %4 = inttoptr i64 %3 to i64*
-  %5 = load i64* %4
+  %5 = load i64, i64* %4
   ret i64 %5
 }
 
@@ -57,7 +57,7 @@ define i64 @load_addr_shift_sext2(i32 zeroext %a, i64 %b) {
   %2 = shl i64 %1, 3
   %3 = add i64 %b, %2
   %4 = inttoptr i64 %3 to i64*
-  %5 = load i64* %4
+  %5 = load i64, i64* %4
   ret i64 %5
 }
 
@@ -68,7 +68,7 @@ define i64 @load_addr_shift_sext3(i32 signext %a, i64 %b) {
   %2 = shl i64 %1, 3
   %3 = add i64 %b, %2
   %4 = inttoptr i64 %3 to i64*
-  %5 = load i64* %4
+  %5 = load i64, i64* %4
   ret i64 %5
 }
 
@@ -82,7 +82,7 @@ define i64 @load_addr_mul_zext1(i32 %a, i64 %b) {
   %2 = mul i64 %1, 8
   %3 = add i64 %b, %2
   %4 = inttoptr i64 %3 to i64*
-  %5 = load i64* %4
+  %5 = load i64, i64* %4
   ret i64 %5
 }
 
@@ -93,7 +93,7 @@ define i64 @load_addr_mul_zext2(i32 zeroext %a, i64 %b) {
   %2 = mul i64 %1, 8
   %3 = add i64 %b, %2
   %4 = inttoptr i64 %3 to i64*
-  %5 = load i64* %4
+  %5 = load i64, i64* %4
   ret i64 %5
 }
 
@@ -104,7 +104,7 @@ define i64 @load_addr_mul_zext3(i32 signext %a, i64 %b) {
   %2 = mul i64 %1, 8
   %3 = add i64 %b, %2
   %4 = inttoptr i64 %3 to i64*
-  %5 = load i64* %4
+  %5 = load i64, i64* %4
   ret i64 %5
 }
 
@@ -115,7 +115,7 @@ define i64 @load_addr_mul_sext1(i32 %a, i64 %b) {
   %2 = mul i64 %1, 8
   %3 = add i64 %b, %2
   %4 = inttoptr i64 %3 to i64*
-  %5 = load i64* %4
+  %5 = load i64, i64* %4
   ret i64 %5
 }
 
@@ -126,7 +126,7 @@ define i64 @load_addr_mul_sext2(i32 zeroext %a, i64 %b) {
   %2 = mul i64 %1, 8
   %3 = add i64 %b, %2
   %4 = inttoptr i64 %3 to i64*
-  %5 = load i64* %4
+  %5 = load i64, i64* %4
   ret i64 %5
 }
 
@@ -137,7 +137,7 @@ define i64 @load_addr_mul_sext3(i32 signext %a, i64 %b) {
   %2 = mul i64 %1, 8
   %3 = add i64 %b, %2
   %4 = inttoptr i64 %3 to i64*
-  %5 = load i64* %4
+  %5 = load i64, i64* %4
   ret i64 %5
 }
 
@@ -153,7 +153,7 @@ define i32 @load_unscaled_zext_i8_to_i32(i64 %a) {
 ; CHECK-NOT:   uxtb
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   %4 = zext i8 %3 to i32
   ret i32 %4
 }
@@ -164,7 +164,7 @@ define i32 @load_unscaled_zext_i16_to_i32(i64 %a) {
 ; CHECK-NOT:   uxth
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   %4 = zext i16 %3 to i32
   ret i32 %4
 }
@@ -175,7 +175,7 @@ define i64 @load_unscaled_zext_i8_to_i64(i64 %a) {
 ; CHECK-NOT:   uxtb
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   %4 = zext i8 %3 to i64
   ret i64 %4
 }
@@ -186,7 +186,7 @@ define i64 @load_unscaled_zext_i16_to_i64(i64 %a) {
 ; CHECK-NOT:   uxth
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   %4 = zext i16 %3 to i64
   ret i64 %4
 }
@@ -197,7 +197,7 @@ define i64 @load_unscaled_zext_i32_to_i64(i64 %a) {
 ; CHECK-NOT:   uxtw
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   %4 = zext i32 %3 to i64
   ret i64 %4
 }
@@ -208,7 +208,7 @@ define i32 @load_unscaled_sext_i8_to_i32(i64 %a) {
 ; CHECK-NOT:   sxtb
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   %4 = sext i8 %3 to i32
   ret i32 %4
 }
@@ -219,7 +219,7 @@ define i32 @load_unscaled_sext_i16_to_i32(i64 %a) {
 ; CHECK-NOT:   sxth
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   %4 = sext i16 %3 to i32
   ret i32 %4
 }
@@ -230,7 +230,7 @@ define i64 @load_unscaled_sext_i8_to_i64(i64 %a) {
 ; CHECK-NOT:   sxtb
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   %4 = sext i8 %3 to i64
   ret i64 %4
 }
@@ -241,7 +241,7 @@ define i64 @load_unscaled_sext_i16_to_i64(i64 %a) {
 ; CHECK-NOT:   sxth
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   %4 = sext i16 %3 to i64
   ret i64 %4
 }
@@ -252,7 +252,7 @@ define i64 @load_unscaled_sext_i32_to_i64(i64 %a) {
 ; CHECK-NOT:   sxtw
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   %4 = sext i32 %3 to i64
   ret i64 %4
 }
@@ -264,7 +264,7 @@ define i32 @load_register_zext_i8_to_i32(i64 %a, i64 %b) {
 ; CHECK-NOT:   uxtb
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   %4 = zext i8 %3 to i32
   ret i32 %4
 }
@@ -275,7 +275,7 @@ define i32 @load_register_zext_i16_to_i32(i64 %a, i64 %b) {
 ; CHECK-NOT:   uxth
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   %4 = zext i16 %3 to i32
   ret i32 %4
 }
@@ -286,7 +286,7 @@ define i64 @load_register_zext_i8_to_i64(i64 %a, i64 %b) {
 ; CHECK-NOT:   uxtb
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   %4 = zext i8 %3 to i64
   ret i64 %4
 }
@@ -297,7 +297,7 @@ define i64 @load_register_zext_i16_to_i64(i64 %a, i64 %b) {
 ; CHECK-NOT:   uxth
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   %4 = zext i16 %3 to i64
   ret i64 %4
 }
@@ -308,7 +308,7 @@ define i64 @load_register_zext_i32_to_i64(i64 %a, i64 %b) {
 ; CHECK-NOT:   uxtw
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   %4 = zext i32 %3 to i64
   ret i64 %4
 }
@@ -319,7 +319,7 @@ define i32 @load_register_sext_i8_to_i32(i64 %a, i64 %b) {
 ; CHECK-NOT:   sxtb
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   %4 = sext i8 %3 to i32
   ret i32 %4
 }
@@ -330,7 +330,7 @@ define i32 @load_register_sext_i16_to_i32(i64 %a, i64 %b) {
 ; CHECK-NOT:   sxth
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   %4 = sext i16 %3 to i32
   ret i32 %4
 }
@@ -341,7 +341,7 @@ define i64 @load_register_sext_i8_to_i64(i64 %a, i64 %b) {
 ; CHECK-NOT:   sxtb
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   %4 = sext i8 %3 to i64
   ret i64 %4
 }
@@ -352,7 +352,7 @@ define i64 @load_register_sext_i16_to_i64(i64 %a, i64 %b) {
 ; CHECK-NOT:   sxth
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   %4 = sext i16 %3 to i64
   ret i64 %4
 }
@@ -363,7 +363,7 @@ define i64 @load_register_sext_i32_to_i64(i64 %a, i64 %b) {
 ; CHECK-NOT:   sxtw
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   %4 = sext i32 %3 to i64
   ret i64 %4
 }
@@ -376,7 +376,7 @@ define i32 @load_extend_zext_i8_to_i32(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i8*
-  %4 = load i8* %3
+  %4 = load i8, i8* %3
   %5 = zext i8 %4 to i32
   ret i32 %5
 }
@@ -388,7 +388,7 @@ define i32 @load_extend_zext_i16_to_i32(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i16*
-  %4 = load i16* %3
+  %4 = load i16, i16* %3
   %5 = zext i16 %4 to i32
   ret i32 %5
 }
@@ -400,7 +400,7 @@ define i64 @load_extend_zext_i8_to_i64(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i8*
-  %4 = load i8* %3
+  %4 = load i8, i8* %3
   %5 = zext i8 %4 to i64
   ret i64 %5
 }
@@ -412,7 +412,7 @@ define i64 @load_extend_zext_i16_to_i64(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i16*
-  %4 = load i16* %3
+  %4 = load i16, i16* %3
   %5 = zext i16 %4 to i64
   ret i64 %5
 }
@@ -424,7 +424,7 @@ define i64 @load_extend_zext_i32_to_i64(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i32*
-  %4 = load i32* %3
+  %4 = load i32, i32* %3
   %5 = zext i32 %4 to i64
   ret i64 %5
 }
@@ -436,7 +436,7 @@ define i32 @load_extend_sext_i8_to_i32(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i8*
-  %4 = load i8* %3
+  %4 = load i8, i8* %3
   %5 = sext i8 %4 to i32
   ret i32 %5
 }
@@ -448,7 +448,7 @@ define i32 @load_extend_sext_i16_to_i32(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i16*
-  %4 = load i16* %3
+  %4 = load i16, i16* %3
   %5 = sext i16 %4 to i32
   ret i32 %5
 }
@@ -460,7 +460,7 @@ define i64 @load_extend_sext_i8_to_i64(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i8*
-  %4 = load i8* %3
+  %4 = load i8, i8* %3
   %5 = sext i8 %4 to i64
   ret i64 %5
 }
@@ -472,7 +472,7 @@ define i64 @load_extend_sext_i16_to_i64(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i16*
-  %4 = load i16* %3
+  %4 = load i16, i16* %3
   %5 = sext i16 %4 to i64
   ret i64 %5
 }
@@ -484,7 +484,7 @@ define i64 @load_extend_sext_i32_to_i64(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i32*
-  %4 = load i32* %3
+  %4 = load i32, i32* %3
   %5 = sext i32 %4 to i64
   ret i64 %5
 }
diff --git a/test/CodeGen/AArch64/fast-isel-int-ext2.ll b/test/CodeGen/AArch64/fast-isel-int-ext2.ll
index 8df26b26971a..93741d6c12d6 100644
--- a/test/CodeGen/AArch64/fast-isel-int-ext2.ll
+++ b/test/CodeGen/AArch64/fast-isel-int-ext2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=false -disable-cgp-branch-opts -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=false -disable-cgp-branch-opts -verify-machineinstrs < %s | FileCheck %s
 
 ;
 ; Test folding of the sign-/zero-extend into the load instruction.
@@ -11,7 +11,7 @@ define i32 @load_unscaled_zext_i8_to_i32(i64 %a) {
 ; CHECK-NOT:   uxtb
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   br label %bb2
 
 bb2:
@@ -25,7 +25,7 @@ define i32 @load_unscaled_zext_i16_to_i32(i64 %a) {
 ; CHECK-NOT:   uxth
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   br label %bb2
 
 bb2:
@@ -39,7 +39,7 @@ define i64 @load_unscaled_zext_i8_to_i64(i64 %a) {
 ; CHECK-NOT:   uxtb
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   br label %bb2
 
 bb2:
@@ -53,7 +53,7 @@ define i64 @load_unscaled_zext_i16_to_i64(i64 %a) {
 ; CHECK-NOT:   uxth
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   br label %bb2
 
 bb2:
@@ -67,7 +67,7 @@ define i64 @load_unscaled_zext_i32_to_i64(i64 %a) {
 ; CHECK-NOT:   uxtw
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   br label %bb2
 
 bb2:
@@ -81,7 +81,7 @@ define i32 @load_unscaled_sext_i8_to_i32(i64 %a) {
 ; CHECK-NOT:   sxtb
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   br label %bb2
 
 bb2:
@@ -95,7 +95,7 @@ define i32 @load_unscaled_sext_i16_to_i32(i64 %a) {
 ; CHECK-NOT:   sxth
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   br label %bb2
 
 bb2:
@@ -109,7 +109,7 @@ define i64 @load_unscaled_sext_i8_to_i64(i64 %a) {
 ; CHECK-NOT:   sxtb
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   br label %bb2
 
 bb2:
@@ -123,7 +123,7 @@ define i64 @load_unscaled_sext_i16_to_i64(i64 %a) {
 ; CHECK-NOT:   sxth
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   br label %bb2
 
 bb2:
@@ -137,7 +137,7 @@ define i64 @load_unscaled_sext_i32_to_i64(i64 %a) {
 ; CHECK-NOT:   sxtw
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   br label %bb2
 
 bb2:
@@ -152,7 +152,7 @@ define i32 @load_register_zext_i8_to_i32(i64 %a, i64 %b) {
 ; CHECK-NOT:   uxtb
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   br label %bb2
 
 bb2:
@@ -166,7 +166,7 @@ define i32 @load_register_zext_i16_to_i32(i64 %a, i64 %b) {
 ; CHECK-NOT:   uxth
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   br label %bb2
 
 bb2:
@@ -180,7 +180,7 @@ define i64 @load_register_zext_i8_to_i64(i64 %a, i64 %b) {
 ; CHECK-NOT:   uxtb
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   br label %bb2
 
 bb2:
@@ -194,7 +194,7 @@ define i64 @load_register_zext_i16_to_i64(i64 %a, i64 %b) {
 ; CHECK-NOT:   uxth
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   br label %bb2
 
 bb2:
@@ -208,7 +208,7 @@ define i64 @load_register_zext_i32_to_i64(i64 %a, i64 %b) {
 ; CHECK-NOT:   uxtw
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   br label %bb2
 
 bb2:
@@ -222,7 +222,7 @@ define i32 @load_register_sext_i8_to_i32(i64 %a, i64 %b) {
 ; CHECK-NOT:   sxtb
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   br label %bb2
 
 bb2:
@@ -236,7 +236,7 @@ define i32 @load_register_sext_i16_to_i32(i64 %a, i64 %b) {
 ; CHECK-NOT:   sxth
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   br label %bb2
 
 bb2:
@@ -250,7 +250,7 @@ define i64 @load_register_sext_i8_to_i64(i64 %a, i64 %b) {
 ; CHECK-NOT:   sxtb
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i8*
-  %3 = load i8* %2
+  %3 = load i8, i8* %2
   br label %bb2
 
 bb2:
@@ -264,7 +264,7 @@ define i64 @load_register_sext_i16_to_i64(i64 %a, i64 %b) {
 ; CHECK-NOT:   sxth
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i16*
-  %3 = load i16* %2
+  %3 = load i16, i16* %2
   br label %bb2
 
 bb2:
@@ -278,7 +278,7 @@ define i64 @load_register_sext_i32_to_i64(i64 %a, i64 %b) {
 ; CHECK-NOT:   sxtw
   %1 = add i64 %a, %b
   %2 = inttoptr i64 %1 to i32*
-  %3 = load i32* %2
+  %3 = load i32, i32* %2
   br label %bb2
 
 bb2:
@@ -294,7 +294,7 @@ define i32 @load_extend_zext_i8_to_i32(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i8*
-  %4 = load i8* %3
+  %4 = load i8, i8* %3
   br label %bb2
 
 bb2:
@@ -309,7 +309,7 @@ define i32 @load_extend_zext_i16_to_i32(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i16*
-  %4 = load i16* %3
+  %4 = load i16, i16* %3
   br label %bb2
 
 bb2:
@@ -324,7 +324,7 @@ define i64 @load_extend_zext_i8_to_i64(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i8*
-  %4 = load i8* %3
+  %4 = load i8, i8* %3
   br label %bb2
 
 bb2:
@@ -339,7 +339,7 @@ define i64 @load_extend_zext_i16_to_i64(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i16*
-  %4 = load i16* %3
+  %4 = load i16, i16* %3
   br label %bb2
 
 bb2:
@@ -354,7 +354,7 @@ define i64 @load_extend_zext_i32_to_i64(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i32*
-  %4 = load i32* %3
+  %4 = load i32, i32* %3
   br label %bb2
 
 bb2:
@@ -369,7 +369,7 @@ define i32 @load_extend_sext_i8_to_i32(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i8*
-  %4 = load i8* %3
+  %4 = load i8, i8* %3
   br label %bb2
 
 bb2:
@@ -384,7 +384,7 @@ define i32 @load_extend_sext_i16_to_i32(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i16*
-  %4 = load i16* %3
+  %4 = load i16, i16* %3
   br label %bb2
 
 bb2:
@@ -399,7 +399,7 @@ define i64 @load_extend_sext_i8_to_i64(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i8*
-  %4 = load i8* %3
+  %4 = load i8, i8* %3
   br label %bb2
 
 bb2:
@@ -414,7 +414,7 @@ define i64 @load_extend_sext_i16_to_i64(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i16*
-  %4 = load i16* %3
+  %4 = load i16, i16* %3
   br label %bb2
 
 bb2:
@@ -429,7 +429,7 @@ define i64 @load_extend_sext_i32_to_i64(i64 %a, i32 %b) {
   %1 = sext i32 %b to i64
   %2 = add i64 %a, %1
   %3 = inttoptr i64 %2 to i32*
-  %4 = load i32* %3
+  %4 = load i32, i32* %3
   br label %bb2
 
 bb2:
diff --git a/test/CodeGen/AArch64/fast-isel-int-ext3.ll b/test/CodeGen/AArch64/fast-isel-int-ext3.ll
index 5d55a6b38f6b..83740c8af5f2 100644
--- a/test/CodeGen/AArch64/fast-isel-int-ext3.ll
+++ b/test/CodeGen/AArch64/fast-isel-int-ext3.ll
@@ -11,7 +11,7 @@ define i32 @load_unscaled_zext_i8_to_i32(i64 %a) {
 ; CHECK:       uxtb w0, [[REG]]
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8 addrspace(256)*
-  %3 = load i8 addrspace(256)* %2
+  %3 = load i8, i8 addrspace(256)* %2
   %4 = zext i8 %3 to i32
   ret i32 %4
 }
@@ -22,7 +22,7 @@ define i32 @load_unscaled_zext_i16_to_i32(i64 %a) {
 ; CHECK:       uxth w0, [[REG]]
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16 addrspace(256)*
-  %3 = load i16 addrspace(256)* %2
+  %3 = load i16, i16 addrspace(256)* %2
   %4 = zext i16 %3 to i32
   ret i32 %4
 }
@@ -33,7 +33,7 @@ define i64 @load_unscaled_zext_i8_to_i64(i64 %a) {
 ; CHECK:       ubfx x0, x[[REG]], #0, #8
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8 addrspace(256)*
-  %3 = load i8 addrspace(256)* %2
+  %3 = load i8, i8 addrspace(256)* %2
   %4 = zext i8 %3 to i64
   ret i64 %4
 }
@@ -44,7 +44,7 @@ define i64 @load_unscaled_zext_i16_to_i64(i64 %a) {
 ; CHECK:       ubfx x0, x[[REG]], #0, #16
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16 addrspace(256)*
-  %3 = load i16 addrspace(256)* %2
+  %3 = load i16, i16 addrspace(256)* %2
   %4 = zext i16 %3 to i64
   ret i64 %4
 }
@@ -55,7 +55,7 @@ define i64 @load_unscaled_zext_i32_to_i64(i64 %a) {
 ; CHECK:       ubfx x0, x[[REG]], #0, #32
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i32 addrspace(256)*
-  %3 = load i32 addrspace(256)* %2
+  %3 = load i32, i32 addrspace(256)* %2
   %4 = zext i32 %3 to i64
   ret i64 %4
 }
@@ -66,7 +66,7 @@ define i32 @load_unscaled_sext_i8_to_i32(i64 %a) {
 ; CHECK:       sxtb w0, [[REG]]
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8 addrspace(256)*
-  %3 = load i8 addrspace(256)* %2
+  %3 = load i8, i8 addrspace(256)* %2
   %4 = sext i8 %3 to i32
   ret i32 %4
 }
@@ -77,7 +77,7 @@ define i32 @load_unscaled_sext_i16_to_i32(i64 %a) {
 ; CHECK:       sxth w0, [[REG]]
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16 addrspace(256)*
-  %3 = load i16 addrspace(256)* %2
+  %3 = load i16, i16 addrspace(256)* %2
   %4 = sext i16 %3 to i32
   ret i32 %4
 }
@@ -88,7 +88,7 @@ define i64 @load_unscaled_sext_i8_to_i64(i64 %a) {
 ; CHECK:       sxtb x0, [[REG]]
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8 addrspace(256)*
-  %3 = load i8 addrspace(256)* %2
+  %3 = load i8, i8 addrspace(256)* %2
   %4 = sext i8 %3 to i64
   ret i64 %4
 }
@@ -99,7 +99,7 @@ define i64 @load_unscaled_sext_i16_to_i64(i64 %a) {
 ; CHECK:       sxth x0, [[REG]]
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16 addrspace(256)*
-  %3 = load i16 addrspace(256)* %2
+  %3 = load i16, i16 addrspace(256)* %2
   %4 = sext i16 %3 to i64
   ret i64 %4
 }
@@ -110,7 +110,7 @@ define i64 @load_unscaled_sext_i32_to_i64(i64 %a) {
 ; CHECK:       sxtw x0, [[REG]]
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i32 addrspace(256)*
-  %3 = load i32 addrspace(256)* %2
+  %3 = load i32, i32 addrspace(256)* %2
   %4 = sext i32 %3 to i64
   ret i64 %4
 }
diff --git a/test/CodeGen/AArch64/fast-isel-int-ext4.ll b/test/CodeGen/AArch64/fast-isel-int-ext4.ll
index f25bb98af758..1ab951bf0712 100644
--- a/test/CodeGen/AArch64/fast-isel-int-ext4.ll
+++ b/test/CodeGen/AArch64/fast-isel-int-ext4.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 define i32 @kill_flag(i16 signext %a) {
 ; CHECK-LABEL: kill_flag
diff --git a/test/CodeGen/AArch64/fast-isel-int-ext5.ll b/test/CodeGen/AArch64/fast-isel-int-ext5.ll
new file mode 100644
index 000000000000..0f9ec62811df
--- /dev/null
+++ b/test/CodeGen/AArch64/fast-isel-int-ext5.ll
@@ -0,0 +1,19 @@
+; RUN: llc -mtriple=aarch64-apple-darwin -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
+
+; CHECK-LABEL: int_ext_opt
+define i64 @int_ext_opt(i8* %addr, i1 %c1, i1 %c2) {
+entry:
+  %0 = load i8, i8* %addr
+  br i1 %c1, label %bb1, label %bb2
+
+bb1:
+  %1 = zext i8 %0 to i64
+  br i1 %c2, label %bb2, label %exit
+
+bb2:
+  %2 = phi i64 [1, %entry], [%1, %bb1]
+  ret i64 %2
+
+exit:
+  ret i64 0
+}
diff --git a/test/CodeGen/AArch64/fast-isel-logic-op.ll b/test/CodeGen/AArch64/fast-isel-logic-op.ll
index 2c7486e4cf8a..89c5f2c48024 100644
--- a/test/CodeGen/AArch64/fast-isel-logic-op.ll
+++ b/test/CodeGen/AArch64/fast-isel-logic-op.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=0                  -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 ; AND
 define zeroext i1 @and_rr_i1(i1 signext %a, i1 signext %b) {
diff --git a/test/CodeGen/AArch64/fast-isel-memcpy.ll b/test/CodeGen/AArch64/fast-isel-memcpy.ll
index 9161dad249a9..07595a954db0 100644
--- a/test/CodeGen/AArch64/fast-isel-memcpy.ll
+++ b/test/CodeGen/AArch64/fast-isel-memcpy.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 ; Test that we don't segfault.
 ; CHECK-LABEL: test
diff --git a/test/CodeGen/AArch64/fast-isel-mul.ll b/test/CodeGen/AArch64/fast-isel-mul.ll
index f2fda27c2f7b..9d6fd00008e8 100644
--- a/test/CodeGen/AArch64/fast-isel-mul.ll
+++ b/test/CodeGen/AArch64/fast-isel-mul.ll
@@ -1,4 +1,4 @@
-; RUN: llc -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s
+; RUN: llc -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s
 
 define zeroext i8 @test_mul8(i8 %lhs, i8 %rhs) {
 ; CHECK-LABEL: test_mul8:
diff --git a/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll b/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll
index 8d2d39a1a1ff..34d7983ff5fa 100644
--- a/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll
+++ b/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -code-model=small -verify-machineinstrs < %s | FileCheck %s --check-prefix=SMALL
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -code-model=small -verify-machineinstrs < %s | FileCheck %s --check-prefix=SMALL
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE
 
 define float @frem_f32(float %a, float %b) {
 ; SMALL-LABEL: frem_f32
diff --git a/test/CodeGen/AArch64/fast-isel-sdiv.ll b/test/CodeGen/AArch64/fast-isel-sdiv.ll
index 30807767fa79..3c8de43af6c1 100644
--- a/test/CodeGen/AArch64/fast-isel-sdiv.ll
+++ b/test/CodeGen/AArch64/fast-isel-sdiv.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=aarch64-apple-darwin                             -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 define i32 @sdiv_i32_exact(i32 %a) {
 ; CHECK-LABEL: sdiv_i32_exact
diff --git a/test/CodeGen/AArch64/fast-isel-select.ll b/test/CodeGen/AArch64/fast-isel-select.ll
index 928e9d46741d..e06f74cb7fef 100644
--- a/test/CodeGen/AArch64/fast-isel-select.ll
+++ b/test/CodeGen/AArch64/fast-isel-select.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=aarch64-apple-darwin                             -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 ; First test the different supported value types for select.
 define zeroext i1 @select_i1(i1 zeroext %c, i1 zeroext %a, i1 zeroext %b) {
diff --git a/test/CodeGen/AArch64/fast-isel-shift.ll b/test/CodeGen/AArch64/fast-isel-shift.ll
index ce4ba49f4999..36fab0d51ed5 100644
--- a/test/CodeGen/AArch64/fast-isel-shift.ll
+++ b/test/CodeGen/AArch64/fast-isel-shift.ll
@@ -1,4 +1,4 @@
-; RUN: llc -fast-isel -fast-isel-abort -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -fast-isel -fast-isel-abort=1 -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
 
 ; CHECK-LABEL: asr_zext_i1_i16
 ; CHECK:       uxth {{w[0-9]*}}, wzr
diff --git a/test/CodeGen/AArch64/fast-isel-sqrt.ll b/test/CodeGen/AArch64/fast-isel-sqrt.ll
index 1331d5c7de5b..80a0a469cd94 100644
--- a/test/CodeGen/AArch64/fast-isel-sqrt.ll
+++ b/test/CodeGen/AArch64/fast-isel-sqrt.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=arm64-apple-darwin                             -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 define float @test_sqrt_f32(float %a) {
 ; CHECK-LABEL: test_sqrt_f32
diff --git a/test/CodeGen/AArch64/fast-isel-tbz.ll b/test/CodeGen/AArch64/fast-isel-tbz.ll
index a5f02ffa39ac..598826763787 100644
--- a/test/CodeGen/AArch64/fast-isel-tbz.ll
+++ b/test/CodeGen/AArch64/fast-isel-tbz.ll
@@ -1,5 +1,5 @@
 ; RUN: llc                             -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK %s
-; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK --check-prefix=FAST %s
+; RUN: llc -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK --check-prefix=FAST %s
 
 define i32 @icmp_eq_i8(i8 zeroext %a) {
 ; CHECK-LABEL: icmp_eq_i8
diff --git a/test/CodeGen/AArch64/fast-isel-trunc.ll b/test/CodeGen/AArch64/fast-isel-trunc.ll
index 55937eb76fa9..af58abe1f0c1 100644
--- a/test/CodeGen/AArch64/fast-isel-trunc.ll
+++ b/test/CodeGen/AArch64/fast-isel-trunc.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s
 
 ; Test that %1 doesn't get the kill flag set before its last use.
 define i32 @test_trunc(i32 %a) {
diff --git a/test/CodeGen/AArch64/fast-isel-vector-arithmetic.ll b/test/CodeGen/AArch64/fast-isel-vector-arithmetic.ll
index eaa0db527949..82b8d47cd80e 100644
--- a/test/CodeGen/AArch64/fast-isel-vector-arithmetic.ll
+++ b/test/CodeGen/AArch64/fast-isel-vector-arithmetic.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=aarch64-apple-darwin                                                   -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -fast-isel-abort-args -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=2 -verify-machineinstrs < %s | FileCheck %s
 
 ; Vector Integer Add
 define <8 x i8> @add_v8i8_rr(<8 x i8> %a, <8 x i8> %b) {
diff --git a/test/CodeGen/AArch64/fast-isel-vret.ll b/test/CodeGen/AArch64/fast-isel-vret.ll
index 9ad92273d3af..d8a56ce48d76 100644
--- a/test/CodeGen/AArch64/fast-isel-vret.ll
+++ b/test/CodeGen/AArch64/fast-isel-vret.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 ; Test that we don't abort fast-isle for ret
 define <8 x i8> @ret_v8i8(<8 x i8> %a, <8 x i8> %b) {
diff --git a/test/CodeGen/AArch64/floatdp_1source.ll b/test/CodeGen/AArch64/floatdp_1source.ll
index 8c02787a2340..ec7d32dbfae6 100644
--- a/test/CodeGen/AArch64/floatdp_1source.ll
+++ b/test/CodeGen/AArch64/floatdp_1source.ll
@@ -27,7 +27,7 @@ declare double @nearbyint(double) readonly
 
 define void @simple_float() {
 ; CHECK-LABEL: simple_float:
-  %val1 = load volatile float* @varfloat
+  %val1 = load volatile float, float* @varfloat
 
   %valabs = call float @fabsf(float %val1)
   store volatile float %valabs, float* @varfloat
@@ -66,7 +66,7 @@ define void @simple_float() {
 
 define void @simple_double() {
 ; CHECK-LABEL: simple_double:
-  %val1 = load volatile double* @vardouble
+  %val1 = load volatile double, double* @vardouble
 
   %valabs = call double @fabs(double %val1)
   store volatile double %valabs, double* @vardouble
@@ -106,9 +106,9 @@ define void @simple_double() {
 define void @converts() {
 ; CHECK-LABEL: converts:
 
-  %val16 = load volatile half* @varhalf
-  %val32 = load volatile float* @varfloat
-  %val64 = load volatile double* @vardouble
+  %val16 = load volatile half, half* @varhalf
+  %val32 = load volatile float, float* @varfloat
+  %val64 = load volatile double, double* @vardouble
 
   %val16to32 = fpext half %val16 to float
   store volatile float %val16to32, float* @varfloat
diff --git a/test/CodeGen/AArch64/floatdp_2source.ll b/test/CodeGen/AArch64/floatdp_2source.ll
index 262271784ec6..30e2856a4f5b 100644
--- a/test/CodeGen/AArch64/floatdp_2source.ll
+++ b/test/CodeGen/AArch64/floatdp_2source.ll
@@ -5,7 +5,7 @@
 
 define void @testfloat() {
 ; CHECK-LABEL: testfloat:
-  %val1 = load float* @varfloat
+  %val1 = load float, float* @varfloat
 
   %val2 = fadd float %val1, %val1
 ; CHECK: fadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
@@ -33,7 +33,7 @@ define void @testfloat() {
 
 define void @testdouble() {
 ; CHECK-LABEL: testdouble:
-  %val1 = load double* @vardouble
+  %val1 = load double, double* @vardouble
 
   %val2 = fadd double %val1, %val1
 ; CHECK: fadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
diff --git a/test/CodeGen/AArch64/fold-constants.ll b/test/CodeGen/AArch64/fold-constants.ll
new file mode 100644
index 000000000000..2dd0d1245930
--- /dev/null
+++ b/test/CodeGen/AArch64/fold-constants.ll
@@ -0,0 +1,21 @@
+; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
+
+define i64 @dotests_616() {
+; CHECK-LABEL: dotests_616
+; CHECK:       movi d0, #0000000000000000
+; CHECK-NEXT:  umov w8, v0.b[2]
+; CHECK-NEXT:  sbfx w8, w8, #0, #1
+; CHECK-NEXT:  fmov s0, w8
+; CHECK-NEXT:  fmov x0, d0
+; CHECK-NEXT:  ret
+entry:
+  %0 = bitcast <2 x i64> zeroinitializer to <8 x i16>
+  %1 = and <8 x i16> zeroinitializer, %0
+  %2 = icmp ne <8 x i16> %1, zeroinitializer
+  %3 = extractelement <8 x i1> %2, i32 2
+  %vgetq_lane285 = sext i1 %3 to i16
+  %vset_lane = insertelement <4 x i16> undef, i16 %vgetq_lane285, i32 0
+  %4 = bitcast <4 x i16> %vset_lane to <1 x i64>
+  %vget_lane = extractelement <1 x i64> %4, i32 0
+  ret i64 %vget_lane
+}
diff --git a/test/CodeGen/AArch64/fp128-folding.ll b/test/CodeGen/AArch64/fp128-folding.ll
index 892b19c5cf33..5027e83c292a 100644
--- a/test/CodeGen/AArch64/fp128-folding.ll
+++ b/test/CodeGen/AArch64/fp128-folding.ll
@@ -8,7 +8,7 @@ define fp128 @test_folding() {
 ; CHECK-LABEL: test_folding:
   %l = alloca i32
   store i32 42, i32* %l
-  %val = load i32* %l
+  %val = load i32, i32* %l
   %fpval = sitofp i32 %val to fp128
   ; If the value is loaded from a constant pool into an fp128, it's been folded
   ; successfully.
diff --git a/test/CodeGen/AArch64/fp16-instructions.ll b/test/CodeGen/AArch64/fp16-instructions.ll
deleted file mode 100644
index 7a44cd128cb0..000000000000
--- a/test/CodeGen/AArch64/fp16-instructions.ll
+++ /dev/null
@@ -1,109 +0,0 @@
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
-
-define half @add_h(half %a, half %b) {
-entry:
-; CHECK-LABEL: add_h:
-; CHECK-DAG: fcvt [[OP1:s[0-9]+]], h0
-; CHECK-DAG: fcvt [[OP2:s[0-9]+]], h1
-; CHECK: fadd [[RES:s[0-9]+]], [[OP1]], [[OP2]]
-; CHECK: fcvt h0, [[RES]]
-  %0 = fadd half %a, %b
-  ret half %0
-}
-
-
-define half @sub_h(half %a, half %b) {
-entry:
-; CHECK-LABEL: sub_h:
-; CHECK-DAG: fcvt [[OP1:s[0-9]+]], h0
-; CHECK-DAG: fcvt [[OP2:s[0-9]+]], h1
-; CHECK: fsub [[RES:s[0-9]+]], [[OP1]], [[OP2]]
-; CHECK: fcvt h0, [[RES]]
-  %0 = fsub half %a, %b
-  ret half %0
-}
-
-
-define half @mul_h(half %a, half %b) {
-entry:
-; CHECK-LABEL: mul_h:
-; CHECK-DAG: fcvt [[OP1:s[0-9]+]], h0
-; CHECK-DAG: fcvt [[OP2:s[0-9]+]], h1
-; CHECK: fmul [[RES:s[0-9]+]], [[OP1]], [[OP2]]
-; CHECK: fcvt h0, [[RES]]
-  %0 = fmul half %a, %b
-  ret half %0
-}
-
-
-define half @div_h(half %a, half %b) {
-entry:
-; CHECK-LABEL: div_h:
-; CHECK-DAG: fcvt [[OP1:s[0-9]+]], h0
-; CHECK-DAG: fcvt [[OP2:s[0-9]+]], h1
-; CHECK: fdiv [[RES:s[0-9]+]], [[OP1]], [[OP2]]
-; CHECK: fcvt h0, [[RES]]
-  %0 = fdiv half %a, %b
-  ret half %0
-}
-
-
-define half @load_h(half* %a) {
-entry:
-; CHECK-LABEL: load_h:
-; CHECK: ldr h0, [x0]
-  %0 = load half* %a, align 4
-  ret half %0
-}
-
-
-define void @store_h(half* %a, half %b) {
-entry:
-; CHECK-LABEL: store_h:
-; CHECK: str h0, [x0]
-  store half %b, half* %a, align 4
-  ret void
-}
-
-define half @s_to_h(float %a) {
-; CHECK-LABEL: s_to_h:
-; CHECK: fcvt h0, s0
-  %1 = fptrunc float %a to half
-  ret half %1
-}
-
-define half @d_to_h(double %a) {
-; CHECK-LABEL: d_to_h:
-; CHECK: fcvt h0, d0
-  %1 = fptrunc double %a to half
-  ret half %1
-}
-
-define float @h_to_s(half %a) {
-; CHECK-LABEL: h_to_s:
-; CHECK: fcvt s0, h0
-  %1 = fpext half %a to float
-  ret float %1
-}
-
-define double @h_to_d(half %a) {
-; CHECK-LABEL: h_to_d:
-; CHECK: fcvt d0, h0
-  %1 = fpext half %a to double
-  ret double %1
-}
-
-define half @bitcast_i_to_h(i16 %a) {
-; CHECK-LABEL: bitcast_i_to_h:
-; CHECK: fmov s0, w0
-  %1 = bitcast i16 %a to half
-  ret half %1
-}
-
-
-define i16 @bitcast_h_to_i(half %a) {
-; CHECK-LABEL: bitcast_h_to_i:
-; CHECK: fmov w0, s0
-  %1 = bitcast half %a to i16
-  ret i16 %1
-}
diff --git a/test/CodeGen/AArch64/fp16-v16-instructions.ll b/test/CodeGen/AArch64/fp16-v16-instructions.ll
new file mode 100644
index 000000000000..1af2bd10912f
--- /dev/null
+++ b/test/CodeGen/AArch64/fp16-v16-instructions.ll
@@ -0,0 +1,105 @@
+; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
+
+
+define <16 x half> @sitofp_i32(<16 x i32> %a) #0 {
+; CHECK-LABEL: sitofp_i32:
+; CHECK-DAG: scvtf [[S0:v[0-9]+\.4s]], v0.4s
+; CHECK-DAG: scvtf [[S1:v[0-9]+\.4s]], v1.4s
+; CHECK-DAG: scvtf [[S2:v[0-9]+\.4s]], v2.4s
+; CHECK-DAG: scvtf [[S3:v[0-9]+\.4s]], v3.4s
+; CHECK-DAG: fcvtn v0.4h, [[S0]]
+; CHECK-DAG: fcvtn v1.4h, [[S2]]
+; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
+; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
+; CHECK-DAg: ins v0.d[1], v[[R1]].d[0]
+; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
+
+  %1 = sitofp <16 x i32> %a to <16 x half>
+  ret <16 x half> %1
+}
+
+
+define <16 x half> @sitofp_i64(<16 x i64> %a) #0 {
+; CHECK-LABEL: sitofp_i64:
+; CHECK-DAG: scvtf [[D0:v[0-9]+\.2d]], v0.2d
+; CHECK-DAG: scvtf [[D1:v[0-9]+\.2d]], v1.2d
+; CHECK-DAG: scvtf [[D2:v[0-9]+\.2d]], v2.2d
+; CHECK-DAG: scvtf [[D3:v[0-9]+\.2d]], v3.2d
+; CHECK-DAG: scvtf [[D4:v[0-9]+\.2d]], v4.2d
+; CHECK-DAG: scvtf [[D5:v[0-9]+\.2d]], v5.2d
+; CHECK-DAG: scvtf [[D6:v[0-9]+\.2d]], v6.2d
+; CHECK-DAG: scvtf [[D7:v[0-9]+\.2d]], v7.2d
+
+; CHECK-DAG: fcvtn [[S0:v[0-9]+]].2s, [[D0]]
+; CHECK-DAG: fcvtn [[S1:v[0-9]+]].2s, [[D2]]
+; CHECK-DAG: fcvtn [[S2:v[0-9]+]].2s, [[D4]]
+; CHECK-DAG: fcvtn [[S3:v[0-9]+]].2s, [[D6]]
+
+; CHECK-DAG: fcvtn2 [[S0]].4s, [[D1]]
+; CHECK-DAG: fcvtn2 [[S1]].4s, [[D3]]
+; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
+; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]
+
+; CHECK-DAG: fcvtn v0.4h, [[S0]].4s
+; CHECK-DAG: fcvtn v1.4h, [[S2]].4s
+; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s
+; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s
+; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
+; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
+
+  %1 = sitofp <16 x i64> %a to <16 x half>
+  ret <16 x half> %1
+}
+
+
+define <16 x half> @uitofp_i32(<16 x i32> %a) #0 {
+; CHECK-LABEL: uitofp_i32:
+; CHECK-DAG: ucvtf [[S0:v[0-9]+\.4s]], v0.4s
+; CHECK-DAG: ucvtf [[S1:v[0-9]+\.4s]], v1.4s
+; CHECK-DAG: ucvtf [[S2:v[0-9]+\.4s]], v2.4s
+; CHECK-DAG: ucvtf [[S3:v[0-9]+\.4s]], v3.4s
+; CHECK-DAG: fcvtn v0.4h, [[S0]]
+; CHECK-DAG: fcvtn v1.4h, [[S2]]
+; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
+; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
+; CHECK-DAg: ins v0.d[1], v[[R1]].d[0]
+; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
+
+  %1 = uitofp <16 x i32> %a to <16 x half>
+  ret <16 x half> %1
+}
+
+
+define <16 x half> @uitofp_i64(<16 x i64> %a) #0 {
+; CHECK-LABEL: uitofp_i64:
+; CHECK-DAG: ucvtf [[D0:v[0-9]+\.2d]], v0.2d
+; CHECK-DAG: ucvtf [[D1:v[0-9]+\.2d]], v1.2d
+; CHECK-DAG: ucvtf [[D2:v[0-9]+\.2d]], v2.2d
+; CHECK-DAG: ucvtf [[D3:v[0-9]+\.2d]], v3.2d
+; CHECK-DAG: ucvtf [[D4:v[0-9]+\.2d]], v4.2d
+; CHECK-DAG: ucvtf [[D5:v[0-9]+\.2d]], v5.2d
+; CHECK-DAG: ucvtf [[D6:v[0-9]+\.2d]], v6.2d
+; CHECK-DAG: ucvtf [[D7:v[0-9]+\.2d]], v7.2d
+
+; CHECK-DAG: fcvtn [[S0:v[0-9]+]].2s, [[D0]]
+; CHECK-DAG: fcvtn [[S1:v[0-9]+]].2s, [[D2]]
+; CHECK-DAG: fcvtn [[S2:v[0-9]+]].2s, [[D4]]
+; CHECK-DAG: fcvtn [[S3:v[0-9]+]].2s, [[D6]]
+
+; CHECK-DAG: fcvtn2 [[S0]].4s, [[D1]]
+; CHECK-DAG: fcvtn2 [[S1]].4s, [[D3]]
+; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
+; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]
+
+; CHECK-DAG: fcvtn v0.4h, [[S0]].4s
+; CHECK-DAG: fcvtn v1.4h, [[S2]].4s
+; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s
+; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s
+; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
+; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
+
+  %1 = uitofp <16 x i64> %a to <16 x half>
+  ret <16 x half> %1
+}
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/AArch64/fp16-v4-instructions.ll b/test/CodeGen/AArch64/fp16-v4-instructions.ll
index 8e8968108c78..0dbda152fca9 100644
--- a/test/CodeGen/AArch64/fp16-v4-instructions.ll
+++ b/test/CodeGen/AArch64/fp16-v4-instructions.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi | FileCheck %s
 
 define <4 x half> @add_h(<4 x half> %a, <4 x half> %b) {
 entry:
@@ -12,6 +12,15 @@ entry:
 }
 
 
+define <4 x half> @build_h4(<4 x half> %a) {
+entry:
+; CHECK-LABEL: build_h4:
+; CHECK: movz [[GPR:w[0-9]+]], #0x3ccd
+; CHECK: dup v0.4h, [[GPR]]
+  ret <4 x half> <half 0xH3CCD, half 0xH3CCD, half 0xH3CCD, half 0xH3CCD>
+}
+
+
 define <4 x half> @sub_h(<4 x half> %a, <4 x half> %b) {
 entry:
 ; CHECK-LABEL: sub_h:
@@ -52,7 +61,7 @@ define <4 x half> @load_h(<4 x half>* %a) {
 entry:
 ; CHECK-LABEL: load_h:
 ; CHECK: ldr d0, [x0]
-  %0 = load <4 x half>* %a, align 4
+  %0 = load <4 x half>, <4 x half>* %a, align 4
   ret <4 x half> %0
 }
 
@@ -120,3 +129,93 @@ define <4 x i16> @bitcast_h_to_i(float, <4 x half> %a) {
   %2 = bitcast <4 x half> %a to <4 x i16>
   ret <4 x i16> %2
 }
+
+
+define <4 x half> @sitofp_i8(<4 x i8> %a) #0 {
+; CHECK-LABEL: sitofp_i8:
+; CHECK-NEXT: shl [[OP1:v[0-9]+\.4h]], v0.4h, #8
+; CHECK-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
+; CHECK-NEXT: sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
+; CHECK-NEXT: scvtf [[OP4:v[0-9]+\.4s]], [[OP3]]
+; CHECK-NEXT: fcvtn v0.4h, [[OP4]]
+; CHECK-NEXT: ret
+  %1 = sitofp <4 x i8> %a to <4 x half>
+  ret <4 x half> %1
+}
+
+
+define <4 x half> @sitofp_i16(<4 x i16> %a) #0 {
+; CHECK-LABEL: sitofp_i16:
+; CHECK-NEXT: sshll [[OP1:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-NEXT: scvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
+; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
+; CHECK-NEXT: ret
+  %1 = sitofp <4 x i16> %a to <4 x half>
+  ret <4 x half> %1
+}
+
+
+define <4 x half> @sitofp_i32(<4 x i32> %a) #0 {
+; CHECK-LABEL: sitofp_i32:
+; CHECK-NEXT: scvtf [[OP1:v[0-9]+\.4s]], v0.4s
+; CHECK-NEXT: fcvtn v0.4h, [[OP1]]
+  %1 = sitofp <4 x i32> %a to <4 x half>
+  ret <4 x half> %1
+}
+
+
+define <4 x half> @sitofp_i64(<4 x i64> %a) #0 {
+; CHECK-LABEL: sitofp_i64:
+; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d
+; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d
+; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
+; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
+; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
+  %1 = sitofp <4 x i64> %a to <4 x half>
+  ret <4 x half> %1
+}
+
+define <4 x half> @uitofp_i8(<4 x i8> %a) #0 {
+; CHECK-LABEL: uitofp_i8:
+; CHECK-NEXT: bic v0.4h, #0xff, lsl #8
+; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
+; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
+; CHECK-NEXT: ret
+  %1 = uitofp <4 x i8> %a to <4 x half>
+  ret <4 x half> %1
+}
+
+
+define <4 x half> @uitofp_i16(<4 x i16> %a) #0 {
+; CHECK-LABEL: uitofp_i16:
+; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
+; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
+; CHECK-NEXT: ret
+  %1 = uitofp <4 x i16> %a to <4 x half>
+  ret <4 x half> %1
+}
+
+
+define <4 x half> @uitofp_i32(<4 x i32> %a) #0 {
+; CHECK-LABEL: uitofp_i32:
+; CHECK-NEXT: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
+; CHECK-NEXT: fcvtn v0.4h, [[OP1]]
+  %1 = uitofp <4 x i32> %a to <4 x half>
+  ret <4 x half> %1
+}
+
+
+define <4 x half> @uitofp_i64(<4 x i64> %a) #0 {
+; CHECK-LABEL: uitofp_i64:
+; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d
+; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
+; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
+; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
+; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
+  %1 = uitofp <4 x i64> %a to <4 x half>
+  ret <4 x half> %1
+}
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/AArch64/fp16-v8-instructions.ll b/test/CodeGen/AArch64/fp16-v8-instructions.ll
index 9ee2296ace83..10a8c22d6f7e 100644
--- a/test/CodeGen/AArch64/fp16-v8-instructions.ll
+++ b/test/CodeGen/AArch64/fp16-v8-instructions.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi | FileCheck %s
 
 define <8 x half> @add_h(<8 x half> %a, <8 x half> %b) {
 entry:
@@ -164,7 +164,7 @@ define <8 x half> @load_h(<8 x half>* %a) {
 entry:
 ; CHECK-LABEL: load_h:
 ; CHECK: ldr q0, [x0]
-  %0 = load <8 x half>* %a, align 4
+  %0 = load <8 x half>, <8 x half>* %a, align 4
   ret <8 x half> %0
 }
 
@@ -188,10 +188,10 @@ define <8 x half> @s_to_h(<8 x float> %a) {
 
 define <8 x half> @d_to_h(<8 x double> %a) {
 ; CHECK-LABEL: d_to_h:
-; CHECK-DAG: ins v{{[0-9]+}}.d
-; CHECK-DAG: ins v{{[0-9]+}}.d
-; CHECK-DAG: ins v{{[0-9]+}}.d
-; CHECK-DAG: ins v{{[0-9]+}}.d
+; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
+; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
+; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
+; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
@@ -253,3 +253,109 @@ define <8 x i16> @bitcast_h_to_i(float, <8 x half> %a) {
   ret <8 x i16> %2
 }
 
+
+define <8 x half> @sitofp_i8(<8 x i8> %a) #0 {
+; CHECK-LABEL: sitofp_i8:
+; CHECK-NEXT: sshll v[[REG1:[0-9]+]].8h, v0.8b, #0
+; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
+; CHECK-NEXT: sshll  [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
+; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]]
+; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
+; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
+; CHECK-DAG: fcvtn v0.4h, [[HIF]]
+; CHECK: ins v0.d[1], v[[LOREG]].d[0]
+  %1 = sitofp <8 x i8> %a to <8 x half>
+  ret <8 x half> %1
+}
+
+
+define <8 x half> @sitofp_i16(<8 x i16> %a) #0 {
+; CHECK-LABEL: sitofp_i16:
+; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
+; CHECK-NEXT: sshll  [[HI:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]]
+; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
+; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
+; CHECK-DAG: fcvtn v0.4h, [[HIF]]
+; CHECK: ins v0.d[1], v[[LOREG]].d[0]
+  %1 = sitofp <8 x i16> %a to <8 x half>
+  ret <8 x half> %1
+}
+
+
+define <8 x half> @sitofp_i32(<8 x i32> %a) #0 {
+; CHECK-LABEL: sitofp_i32:
+; CHECK-DAG: scvtf [[OP1:v[0-9]+\.4s]], v0.4s
+; CHECK-DAG: scvtf [[OP2:v[0-9]+\.4s]], v1.4s
+; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
+; CHECK-DAG: fcvtn v0.4h, [[OP1]]
+; CHECK: ins v0.d[1], v[[REG]].d[0]
+  %1 = sitofp <8 x i32> %a to <8 x half>
+  ret <8 x half> %1
+}
+
+
+define <8 x half> @sitofp_i64(<8 x i64> %a) #0 {
+; CHECK-LABEL: sitofp_i64:
+; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d
+; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d
+; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
+; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
+; CHECK: fcvtn v0.4h, [[OP3]].4s
+  %1 = sitofp <8 x i64> %a to <8 x half>
+  ret <8 x half> %1
+}
+
+define <8 x half> @uitofp_i8(<8 x i8> %a) #0 {
+; CHECK-LABEL: uitofp_i8:
+; CHECK-NEXT: ushll v[[REG1:[0-9]+]].8h, v0.8b, #0
+; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
+; CHECK-NEXT: ushll  [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
+; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]]
+; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
+; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
+; CHECK-DAG: fcvtn v0.4h, [[HIF]]
+; CHECK: ins v0.d[1], v[[LOREG]].d[0]
+  %1 = uitofp <8 x i8> %a to <8 x half>
+  ret <8 x half> %1
+}
+
+
+define <8 x half> @uitofp_i16(<8 x i16> %a) #0 {
+; CHECK-LABEL: uitofp_i16:
+; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
+; CHECK-NEXT: ushll  [[HI:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]]
+; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
+; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
+; CHECK-DAG: fcvtn v0.4h, [[HIF]]
+; CHECK: ins v0.d[1], v[[LOREG]].d[0]
+  %1 = uitofp <8 x i16> %a to <8 x half>
+  ret <8 x half> %1
+}
+
+
+define <8 x half> @uitofp_i32(<8 x i32> %a) #0 {
+; CHECK-LABEL: uitofp_i32:
+; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
+; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.4s]], v1.4s
+; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
+; CHECK-DAG: fcvtn v0.4h, [[OP1]]
+; CHECK: ins v0.d[1], v[[REG]].d[0]
+  %1 = uitofp <8 x i32> %a to <8 x half>
+  ret <8 x half> %1
+}
+
+
+define <8 x half> @uitofp_i64(<8 x i64> %a) #0 {
+; CHECK-LABEL: uitofp_i64:
+; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d
+; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
+; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
+; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
+; CHECK: fcvtn v0.4h, [[OP3]].4s
+  %1 = uitofp <8 x i64> %a to <8 x half>
+  ret <8 x half> %1
+}
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/AArch64/fp16-vector-load-store.ll b/test/CodeGen/AArch64/fp16-vector-load-store.ll
index edbbffe001c5..b71b39f1acd1 100644
--- a/test/CodeGen/AArch64/fp16-vector-load-store.ll
+++ b/test/CodeGen/AArch64/fp16-vector-load-store.ll
@@ -5,7 +5,7 @@ define <4 x half> @load_64(<4 x half>* nocapture readonly %a) #0 {
 ; CHECK-LABEL: load_64:
 ; CHECK: ldr d0, [x0]
 entry:
-  %0 = load <4 x half>* %a, align 8
+  %0 = load <4 x half>, <4 x half>* %a, align 8
   ret <4 x half> %0
 }
 
@@ -14,7 +14,7 @@ define <8 x half> @load_128(<8 x half>* nocapture readonly %a) #0 {
 ; CHECK-LABEL: load_128:
 ; CHECK: ldr q0, [x0]
 entry:
-  %0 = load <8 x half>* %a, align 16
+  %0 = load <8 x half>, <8 x half>* %a, align 16
   ret <8 x half> %0
 }
 
@@ -23,7 +23,7 @@ define <4 x half> @load_dup_64(half* nocapture readonly %a) #0 {
 ; CHECK-LABEL: load_dup_64:
 ; CHECK: ld1r { v0.4h }, [x0]
 entry:
-  %0 = load half* %a, align 2
+  %0 = load half, half* %a, align 2
   %1 = insertelement <4 x half> undef, half %0, i32 0
   %2 = shufflevector <4 x half> %1, <4 x half> undef, <4 x i32> zeroinitializer
   ret <4 x half> %2
@@ -34,7 +34,7 @@ define <8 x half> @load_dup_128(half* nocapture readonly %a) #0 {
 ; CHECK-LABEL: load_dup_128:
 ; CHECK: ld1r { v0.8h }, [x0]
 entry:
-  %0 = load half* %a, align 2
+  %0 = load half, half* %a, align 2
   %1 = insertelement <8 x half> undef, half %0, i32 0
   %2 = shufflevector <8 x half> %1, <8 x half> undef, <8 x i32> zeroinitializer
   ret <8 x half> %2
@@ -45,7 +45,7 @@ define <4 x half> @load_lane_64(half* nocapture readonly %a, <4 x half> %b) #0 {
 ; CHECK-LABEL: load_lane_64:
 ; CHECK: ld1 { v0.h }[2], [x0]
 entry:
-  %0 = load half* %a, align 2
+  %0 = load half, half* %a, align 2
   %1 = insertelement <4 x half> %b, half %0, i32 2
   ret <4 x half> %1
 }
@@ -55,7 +55,7 @@ define <8 x half> @load_lane_128(half* nocapture readonly %a, <8 x half> %b) #0
 ; CHECK-LABEL: load_lane_128:
 ; CHECK: ld1 { v0.h }[5], [x0]
 entry:
-  %0 = load half* %a, align 2
+  %0 = load half, half* %a, align 2
   %1 = insertelement <8 x half> %b, half %0, i32 5
   ret <8 x half> %1
 }
diff --git a/test/CodeGen/AArch64/fp16-vector-nvcast.ll b/test/CodeGen/AArch64/fp16-vector-nvcast.ll
new file mode 100644
index 000000000000..83e0df74c3da
--- /dev/null
+++ b/test/CodeGen/AArch64/fp16-vector-nvcast.ll
@@ -0,0 +1,89 @@
+; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi | FileCheck %s
+
+; Test pattern (v4f16 (AArch64NvCast (v2i32 FPR64:$src)))
+define void @nvcast_v2i32(<4 x half>* %a) #0 {
+; CHECK-LABEL: nvcast_v2i32:
+; CHECK-NEXT: movi v[[REG:[0-9]+]].2s, #0xab, lsl #16
+; CHECK-NEXT: str d[[REG]], [x0]
+; CHECK-NEXT: ret
+  store volatile <4 x half> <half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB>, <4 x half>* %a
+  ret void
+}
+
+
+; Test pattern (v4f16 (AArch64NvCast (v4i16 FPR64:$src)))
+define void @nvcast_v4i16(<4 x half>* %a) #0 {
+; CHECK-LABEL: nvcast_v4i16:
+; CHECK-NEXT: movi v[[REG:[0-9]+]].4h, #0xab
+; CHECK-NEXT: str d[[REG]], [x0]
+; CHECK-NEXT: ret
+  store volatile <4 x half> <half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB>, <4 x half>* %a
+  ret void
+}
+
+
+; Test pattern (v4f16 (AArch64NvCast (v8i8 FPR64:$src)))
+define void @nvcast_v8i8(<4 x half>* %a) #0 {
+; CHECK-LABEL: nvcast_v8i8:
+; CHECK-NEXT: movi v[[REG:[0-9]+]].8b, #0xab
+; CHECK-NEXT: str d[[REG]], [x0]
+; CHECK-NEXT: ret
+  store volatile <4 x half> <half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB>, <4 x half>* %a
+  ret void
+}
+
+
+; Test pattern (v4f16 (AArch64NvCast (f64 FPR64:$src)))
+define void @nvcast_f64(<4 x half>* %a) #0 {
+; CHECK-LABEL: nvcast_f64:
+; CHECK-NEXT: movi d[[REG:[0-9]+]], #0000000000000000
+; CHECK-NEXT: str d[[REG]], [x0]
+; CHECK-NEXT: ret
+  store volatile <4 x half> zeroinitializer, <4 x half>* %a
+  ret void
+}
+
+; Test pattern (v8f16 (AArch64NvCast (v4i32 FPR128:$src)))
+define void @nvcast_v4i32(<8 x half>* %a) #0 {
+; CHECK-LABEL: nvcast_v4i32:
+; CHECK-NEXT: movi v[[REG:[0-9]+]].4s, #0xab, lsl #16
+; CHECK-NEXT: str q[[REG]], [x0]
+; CHECK-NEXT: ret
+  store volatile <8 x half> <half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB>, <8 x half>* %a
+  ret void
+}
+
+
+; Test pattern (v8f16 (AArch64NvCast (v8i16 FPR128:$src)))
+define void @nvcast_v8i16(<8 x half>* %a) #0 {
+; CHECK-LABEL: nvcast_v8i16:
+; CHECK-NEXT: movi v[[REG:[0-9]+]].8h, #0xab
+; CHECK-NEXT: str q[[REG]], [x0]
+; CHECK-NEXT: ret
+  store volatile <8 x half> <half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB>, <8 x half>* %a
+  ret void
+}
+
+
+; Test pattern (v8f16 (AArch64NvCast (v16i8 FPR128:$src)))
+define void @nvcast_v16i8(<8 x half>* %a) #0 {
+; CHECK-LABEL: nvcast_v16i8:
+; CHECK-NEXT: movi v[[REG:[0-9]+]].16b, #0xab
+; CHECK-NEXT: str q[[REG]], [x0]
+; CHECK-NEXT: ret
+  store volatile <8 x half> <half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB>, <8 x half>* %a
+  ret void
+}
+
+
+; Test pattern (v8f16 (AArch64NvCast (v2i64 FPR128:$src)))
+define void @nvcast_v2i64(<8 x half>* %a) #0 {
+; CHECK-LABEL: nvcast_v2i64:
+; CHECK-NEXT: movi v[[REG:[0-9]+]].2d, #0000000000000000
+; CHECK-NEXT: str q[[REG]], [x0]
+; CHECK-NEXT: ret
+  store volatile <8 x half> zeroinitializer, <8 x half>* %a
+  ret void
+}
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/AArch64/fpimm.ll b/test/CodeGen/AArch64/fpimm.ll
index b7db9182a393..6acb11108afc 100644
--- a/test/CodeGen/AArch64/fpimm.ll
+++ b/test/CodeGen/AArch64/fpimm.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu                                                  -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large                             -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE
-; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE
+; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE
 
 @varf32 = global float 0.0
 @varf64 = global double 0.0
@@ -8,7 +8,7 @@
 define void @check_float() {
 ; CHECK-LABEL: check_float:
 
-  %val = load float* @varf32
+  %val = load float, float* @varf32
   %newval1 = fadd float %val, 8.5
   store volatile float %newval1, float* @varf32
 ; CHECK-DAG: fmov [[EIGHT5:s[0-9]+]], #8.5
@@ -24,7 +24,7 @@ define void @check_float() {
 define void @check_double() {
 ; CHECK-LABEL: check_double:
 
-  %val = load double* @varf64
+  %val = load double, double* @varf64
   %newval1 = fadd double %val, 8.5
   store volatile double %newval1, double* @varf64
 ; CHECK-DAG: fmov {{d[0-9]+}}, #8.5
diff --git a/test/CodeGen/AArch64/frameaddr.ll b/test/CodeGen/AArch64/frameaddr.ll
index d6bb50e57a73..d965809d875e 100644
--- a/test/CodeGen/AArch64/frameaddr.ll
+++ b/test/CodeGen/AArch64/frameaddr.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=aarch64-apple-darwin                             -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 define i8* @test_frameaddress0() nounwind {
 entry:
diff --git a/test/CodeGen/AArch64/free-zext.ll b/test/CodeGen/AArch64/free-zext.ll
index d69105eec381..cff11f85bda4 100644
--- a/test/CodeGen/AArch64/free-zext.ll
+++ b/test/CodeGen/AArch64/free-zext.ll
@@ -5,9 +5,9 @@ define i64 @test_free_zext(i8* %a, i16* %b) {
 ; CHECK-DAG: ldrb w[[A:[0-9]+]], [x0]
 ; CHECK: ldrh w[[B:[0-9]+]], [x1]
 ; CHECK: add x0, x[[B]], x[[A]]
-  %1 = load i8* %a, align 1
+  %1 = load i8, i8* %a, align 1
   %conv = zext i8 %1 to i64
-  %2 = load i16* %b, align 2
+  %2 = load i16, i16* %b, align 2
   %conv1 = zext i16 %2 to i64
   %add = add nsw i64 %conv1, %conv
   ret i64 %add
diff --git a/test/CodeGen/AArch64/func-argpassing.ll b/test/CodeGen/AArch64/func-argpassing.ll
index 9fc9a5f0190f..9100ae39282b 100644
--- a/test/CodeGen/AArch64/func-argpassing.ll
+++ b/test/CodeGen/AArch64/func-argpassing.ll
@@ -34,16 +34,16 @@ define void @add_floats(float %val1, float %val2) {
 ; with memcpy.
 define void @take_struct(%myStruct* byval %structval) {
 ; CHECK-LABEL: take_struct:
-    %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
-    %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
+    %addr0 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 2
+    %addr1 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 0
 
-    %val0 = load volatile i32* %addr0
+    %val0 = load volatile i32, i32* %addr0
     ; Some weird move means x0 is used for one access
 ; CHECK: ldr [[REG32:w[0-9]+]], [{{x[0-9]+|sp}}, #12]
     store volatile i32 %val0, i32* @var32
 ; CHECK: str [[REG32]], [{{x[0-9]+}}, {{#?}}:lo12:var32]
 
-    %val1 = load volatile i64* %addr1
+    %val1 = load volatile i64, i64* %addr1
 ; CHECK: ldr [[REG64:x[0-9]+]], [{{x[0-9]+|sp}}]
     store volatile i64 %val1, i64* @var64
 ; CHECK: str [[REG64]], [{{x[0-9]+}}, {{#?}}:lo12:var64]
@@ -55,16 +55,16 @@ define void @take_struct(%myStruct* byval %structval) {
 define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) {
 ; CHECK-LABEL: check_byval_align:
 
-    %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
-    %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
+    %addr0 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 2
+    %addr1 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 0
 
-    %val0 = load volatile i32* %addr0
+    %val0 = load volatile i32, i32* %addr0
     ; Some weird move means x0 is used for one access
 ; CHECK: ldr [[REG32:w[0-9]+]], [sp, #28]
     store i32 %val0, i32* @var32
 ; CHECK: str [[REG32]], [{{x[0-9]+}}, {{#?}}:lo12:var32]
 
-    %val1 = load volatile i64* %addr1
+    %val1 = load volatile i64, i64* %addr1
 ; CHECK: ldr [[REG64:x[0-9]+]], [sp, #16]
     store i64 %val1, i64* @var64
 ; CHECK: str [[REG64]], [{{x[0-9]+}}, {{#?}}:lo12:var64]
@@ -74,7 +74,7 @@ define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %st
 
 define i32 @return_int() {
 ; CHECK-LABEL: return_int:
-    %val = load i32* @var32
+    %val = load i32, i32* @var32
     ret i32 %val
 ; CHECK: ldr w0, [{{x[0-9]+}}, {{#?}}:lo12:var32]
     ; Make sure epilogue follows
@@ -94,7 +94,7 @@ define double @return_double() {
 define [2 x i64] @return_struct() {
 ; CHECK-LABEL: return_struct:
     %addr = bitcast %myStruct* @varstruct to [2 x i64]*
-    %val = load [2 x i64]* %addr
+    %val = load [2 x i64], [2 x i64]* %addr
     ret [2 x i64] %val
 ; CHECK: add x[[VARSTRUCT:[0-9]+]], {{x[0-9]+}}, :lo12:varstruct
 ; CHECK: ldp x0, x1, [x[[VARSTRUCT]]]
@@ -108,9 +108,9 @@ define [2 x i64] @return_struct() {
 ; if LLVM does it to %myStruct too. So this is the simplest check
 define void @return_large_struct(%myStruct* sret %retval) {
 ; CHECK-LABEL: return_large_struct:
-    %addr0 = getelementptr %myStruct* %retval, i64 0, i32 0
-    %addr1 = getelementptr %myStruct* %retval, i64 0, i32 1
-    %addr2 = getelementptr %myStruct* %retval, i64 0, i32 2
+    %addr0 = getelementptr %myStruct, %myStruct* %retval, i64 0, i32 0
+    %addr1 = getelementptr %myStruct, %myStruct* %retval, i64 0, i32 1
+    %addr2 = getelementptr %myStruct, %myStruct* %retval, i64 0, i32 2
 
     store i64 42, i64* %addr0
     store i8 2, i8* %addr1
@@ -129,8 +129,8 @@ define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var
                           i32* %var6, %myStruct* byval %struct, i32* byval %stacked,
                           double %notstacked) {
 ; CHECK-LABEL: struct_on_stack:
-    %addr = getelementptr %myStruct* %struct, i64 0, i32 0
-    %val64 = load volatile i64* %addr
+    %addr = getelementptr %myStruct, %myStruct* %struct, i64 0, i32 0
+    %val64 = load volatile i64, i64* %addr
     store volatile i64 %val64, i64* @var64
     ; Currently nothing on local stack, so struct should be at sp
 ; CHECK: ldr [[VAL64:x[0-9]+]], [sp]
@@ -141,7 +141,7 @@ define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var
 ; CHECK: str d0, [{{x[0-9]+}}, {{#?}}:lo12:vardouble
 ; CHECK-NOFP-NOT: str d0,
 
-    %retval = load volatile i32* %stacked
+    %retval = load volatile i32, i32* %stacked
     ret i32 %retval
 ; CHECK-LE: ldr w0, [sp, #16]
 }
diff --git a/test/CodeGen/AArch64/func-calls.ll b/test/CodeGen/AArch64/func-calls.ll
index 16157f83aaca..22a33157fd55 100644
--- a/test/CodeGen/AArch64/func-calls.ll
+++ b/test/CodeGen/AArch64/func-calls.ll
@@ -21,15 +21,15 @@ declare void @take_floats(float %val1, float %val2)
 
 define void @simple_args() {
 ; CHECK-LABEL: simple_args:
-  %char1 = load i8* @var8
-  %char2 = load i8* @var8_2
+  %char1 = load i8, i8* @var8
+  %char2 = load i8, i8* @var8_2
   call void @take_i8s(i8 %char1, i8 %char2)
 ; CHECK-DAG: ldrb w0, [{{x[0-9]+}}, {{#?}}:lo12:var8]
 ; CHECK-DAG: ldrb w1, [{{x[0-9]+}}, {{#?}}:lo12:var8_2]
 ; CHECK: bl take_i8s
 
-  %float1 = load float* @varfloat
-  %float2 = load float* @varfloat_2
+  %float1 = load float, float* @varfloat
+  %float2 = load float, float* @varfloat_2
   call void @take_floats(float %float1, float %float2)
 ; CHECK-DAG: ldr s1, [{{x[0-9]+}}, {{#?}}:lo12:varfloat_2]
 ; CHECK-DAG: ldr s0, [{{x[0-9]+}}, {{#?}}:lo12:varfloat]
@@ -124,7 +124,7 @@ declare void @check_i128_regalign(i32 %val0, i128 %val1)
 
 define void @check_i128_align() {
 ; CHECK-LABEL: check_i128_align:
-  %val = load i128* @var128
+  %val = load i128, i128* @var128
   call void @check_i128_stackalign(i32 0, i32 1, i32 2, i32 3,
                                    i32 4, i32 5, i32 6, i32 7,
                                    i32 42, i128 %val)
@@ -152,7 +152,7 @@ define void @check_i128_align() {
 
 define void @check_indirect_call() {
 ; CHECK-LABEL: check_indirect_call:
-  %func = load void()** @fptr
+  %func = load void()*, void()** @fptr
   call void %func()
 ; CHECK: ldr [[FPTR:x[0-9]+]], [{{x[0-9]+}}, {{#?}}:lo12:fptr]
 ; CHECK: blr [[FPTR]]
diff --git a/test/CodeGen/AArch64/funcptr_cast.ll b/test/CodeGen/AArch64/funcptr_cast.ll
index a00b7bcaf6a2..506485ec5b0c 100644
--- a/test/CodeGen/AArch64/funcptr_cast.ll
+++ b/test/CodeGen/AArch64/funcptr_cast.ll
@@ -6,7 +6,7 @@ define i8 @test() {
 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, :lo12:foo
 ; CHECK: ldrb w0, [{{x[0-9]+}}]
 entry:
-  %0 = load i8* bitcast (void (...)* @foo to i8*), align 1
+  %0 = load i8, i8* bitcast (void (...)* @foo to i8*), align 1
   ret i8 %0
 }
 
diff --git a/test/CodeGen/AArch64/function-subtarget-features.ll b/test/CodeGen/AArch64/function-subtarget-features.ll
new file mode 100644
index 000000000000..fca6c931655a
--- /dev/null
+++ b/test/CodeGen/AArch64/function-subtarget-features.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-gnu"
+
+; This test verifies that we can enable subtarget features via
+; the function attributes and generate appropriate code (or,
+; in this case, select the instruction at all).
+
+; Function Attrs: nounwind
+define <16 x i8> @foo(<16 x i8> %data, <16 x i8> %key) #0 {
+  %vaeseq_v.i = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
+  ret <16 x i8> %vaeseq_v.i
+}
+
+; CHECK: foo
+; CHECK: aese
+
+; Function Attrs: nounwind readnone
+declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8>, <16 x i8>)
+
+attributes #0 = { nounwind "target-features"="+neon,+crc,+crypto" }
diff --git a/test/CodeGen/AArch64/ghc-cc.ll b/test/CodeGen/AArch64/ghc-cc.ll
index 505bd5fca66d..01ed78558c79 100644
--- a/test/CodeGen/AArch64/ghc-cc.ll
+++ b/test/CodeGen/AArch64/ghc-cc.ll
@@ -51,7 +51,7 @@ entry:
   ; CHECK-NEXT:  bl      bar_i64
   ; CHECK-NEXT:  ret
 
-  %0 = load i64* @base
+  %0 = load i64, i64* @base
   tail call ghccc void @bar_i64( i64 %0 ) nounwind
   ret void
 }
@@ -64,7 +64,7 @@ entry:
   ; CHECK-NEXT:  bl      bar_float
   ; CHECK-NEXT:  ret
 
-  %0 = load float* @f1
+  %0 = load float, float* @f1
   tail call ghccc void @bar_float( float %0 ) nounwind
   ret void
 }
@@ -77,7 +77,7 @@ entry:
   ; CHECK-NEXT:  bl      bar_double
   ; CHECK-NEXT:  ret
 
-  %0 = load double* @d1
+  %0 = load double, double* @d1
   tail call ghccc void @bar_double( double %0 ) nounwind
   ret void
 }
diff --git a/test/CodeGen/AArch64/global-alignment.ll b/test/CodeGen/AArch64/global-alignment.ll
index 451b9d6741ee..657778e34187 100644
--- a/test/CodeGen/AArch64/global-alignment.ll
+++ b/test/CodeGen/AArch64/global-alignment.ll
@@ -11,7 +11,7 @@ define i64 @test_align32() {
 
   ; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to
   ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load.
-  %val = load i64* %addr
+  %val = load i64, i64* %addr
 ; CHECK: adrp [[HIBITS:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[HIBITS]], {{#?}}:lo12:var32
 ; CHECK: ldr x0, [x[[ADDR]]]
@@ -25,7 +25,7 @@ define i64 @test_align64() {
 
   ; However, var64 *is* properly aligned and emitting an adrp/add/ldr would be
   ; inefficient.
-  %val = load i64* %addr
+  %val = load i64, i64* %addr
 ; CHECK: adrp x[[HIBITS:[0-9]+]], var64
 ; CHECK-NOT: add x[[HIBITS]]
 ; CHECK: ldr x0, [x[[HIBITS]], {{#?}}:lo12:var64]
@@ -39,7 +39,7 @@ define i64 @test_var32_align64() {
 
   ; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to
   ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load.
-  %val = load i64* %addr
+  %val = load i64, i64* %addr
 ; CHECK: adrp x[[HIBITS:[0-9]+]], var32_align64
 ; CHECK-NOT: add x[[HIBITS]]
 ; CHECK: ldr x0, [x[[HIBITS]], {{#?}}:lo12:var32_align64]
@@ -52,7 +52,7 @@ define i64 @test_var32_alias() {
   %addr = bitcast [3 x i32]* @alias to i64*
 
   ; Test that we can find the alignment for aliases.
-  %val = load i64* %addr
+  %val = load i64, i64* %addr
 ; CHECK: adrp x[[HIBITS:[0-9]+]], alias
 ; CHECK-NOT: add x[[HIBITS]]
 ; CHECK: ldr x0, [x[[HIBITS]], {{#?}}:lo12:alias]
@@ -68,7 +68,7 @@ define i64 @test_yet_another_var() {
   ; @yet_another_var has a preferred alignment of 8, but that's not enough if
   ; we're going to be linking against other things. Its ABI alignment is only 4
   ; so we can't fold the load.
-  %val = load i64* bitcast({i32, i32}* @yet_another_var to i64*)
+  %val = load i64, i64* bitcast({i32, i32}* @yet_another_var to i64*)
 ; CHECK: adrp [[HIBITS:x[0-9]+]], yet_another_var
 ; CHECK: add x[[ADDR:[0-9]+]], [[HIBITS]], {{#?}}:lo12:yet_another_var
 ; CHECK: ldr x0, [x[[ADDR]]]
diff --git a/test/CodeGen/AArch64/global-merge-1.ll b/test/CodeGen/AArch64/global-merge-1.ll
index 7dc8da1c444b..14b04303ffb3 100644
--- a/test/CodeGen/AArch64/global-merge-1.ll
+++ b/test/CodeGen/AArch64/global-merge-1.ll
@@ -1,11 +1,11 @@
-; RUN: llc %s -mtriple=aarch64-none-linux-gnu -enable-global-merge -o - | FileCheck %s
-; RUN: llc %s -mtriple=aarch64-none-linux-gnu -enable-global-merge -global-merge-on-external -o - | FileCheck %s
+; RUN: llc %s -mtriple=aarch64-none-linux-gnu -aarch64-global-merge -o - | FileCheck %s
+; RUN: llc %s -mtriple=aarch64-none-linux-gnu -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s
 
-; RUN: llc %s -mtriple=aarch64-linux-gnuabi -enable-global-merge -o - | FileCheck %s
-; RUN: llc %s -mtriple=aarch64-linux-gnuabi -enable-global-merge -global-merge-on-external -o - | FileCheck %s
+; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-global-merge -o - | FileCheck %s
+; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s
 
-; RUN: llc %s -mtriple=aarch64-apple-ios -enable-global-merge -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS
-; RUN: llc %s -mtriple=aarch64-apple-ios -enable-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS
+; RUN: llc %s -mtriple=aarch64-apple-ios -aarch64-global-merge -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS
+; RUN: llc %s -mtriple=aarch64-apple-ios -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS
 
 @m = internal global i32 0, align 4
 @n = internal global i32 0, align 4
diff --git a/test/CodeGen/AArch64/global-merge-2.ll b/test/CodeGen/AArch64/global-merge-2.ll
index 70b700c7e57a..af684039bf10 100644
--- a/test/CodeGen/AArch64/global-merge-2.ll
+++ b/test/CodeGen/AArch64/global-merge-2.ll
@@ -1,6 +1,6 @@
-; RUN: llc %s -mtriple=aarch64-none-linux-gnu -enable-global-merge -global-merge-on-external -o - | FileCheck %s
-; RUN: llc %s -mtriple=aarch64-linux-gnuabi -enable-global-merge -global-merge-on-external -o - | FileCheck %s
-; RUN: llc %s -mtriple=aarch64-apple-ios -enable-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS
+; RUN: llc %s -mtriple=aarch64-none-linux-gnu -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s
+; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s
+; RUN: llc %s -mtriple=aarch64-apple-ios -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS
 
 @x = global i32 0, align 4
 @y = global i32 0, align 4
diff --git a/test/CodeGen/AArch64/global-merge-3.ll b/test/CodeGen/AArch64/global-merge-3.ll
index d455d40edcc2..925108308e56 100644
--- a/test/CodeGen/AArch64/global-merge-3.ll
+++ b/test/CodeGen/AArch64/global-merge-3.ll
@@ -1,6 +1,6 @@
-; RUN: llc %s -mtriple=aarch64-none-linux-gnu -enable-global-merge -global-merge-on-external -o - | FileCheck %s
-; RUN: llc %s -mtriple=aarch64-linux-gnuabi -enable-global-merge -global-merge-on-external -o - | FileCheck %s
-; RUN: llc %s -mtriple=aarch64-apple-ios -enable-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS
+; RUN: llc %s -mtriple=aarch64-none-linux-gnu -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s
+; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s
+; RUN: llc %s -mtriple=aarch64-apple-ios -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS
 
 @x = global [1000 x i32] zeroinitializer, align 1
 @y = global [1000 x i32] zeroinitializer, align 1
@@ -12,8 +12,8 @@ define void @f1(i32 %a1, i32 %a2, i32 %a3) {
 ;CHECK-APPLE-IOS: add	x8, x8, __MergedGlobals_x@PAGEOFF
 ;CHECK-APPLE-IOS: adrp	x9, __MergedGlobals_y@PAGE
 ;CHECK-APPLE-IOS: add	x9, x9, __MergedGlobals_y@PAGEOFF
-  %x3 = getelementptr inbounds [1000 x i32]* @x, i32 0, i64 3
-  %y3 = getelementptr inbounds [1000 x i32]* @y, i32 0, i64 3
+  %x3 = getelementptr inbounds [1000 x i32], [1000 x i32]* @x, i32 0, i64 3
+  %y3 = getelementptr inbounds [1000 x i32], [1000 x i32]* @y, i32 0, i64 3
   store i32 %a1, i32* %x3, align 4
   store i32 %a2, i32* %y3, align 4
   store i32 %a3, i32* @z, align 4
diff --git a/test/CodeGen/AArch64/global-merge-4.ll b/test/CodeGen/AArch64/global-merge-4.ll
index a525ccd8dee3..bc6b68a9c046 100644
--- a/test/CodeGen/AArch64/global-merge-4.ll
+++ b/test/CodeGen/AArch64/global-merge-4.ll
@@ -1,4 +1,4 @@
-; RUN: llc %s -mtriple=aarch64-linux-gnuabi -enable-global-merge -o - | FileCheck %s
+; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-global-merge -o - | FileCheck %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
 target triple = "arm64-apple-ios7.0.0"
@@ -10,25 +10,25 @@ target triple = "arm64-apple-ios7.0.0"
 ; Function Attrs: nounwind ssp
 define internal void @initialize() #0 {
   %1 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
-  store i32 %1, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 0), align 4
+  store i32 %1, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 0), align 4
   %2 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
-  store i32 %2, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 0), align 4
+  store i32 %2, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 0), align 4
   %3 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
-  store i32 %3, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 1), align 4
+  store i32 %3, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 1), align 4
   %4 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
-  store i32 %4, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 1), align 4
+  store i32 %4, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 1), align 4
   %5 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
-  store i32 %5, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 2), align 4
+  store i32 %5, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 2), align 4
   %6 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
-  store i32 %6, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 2), align 4
+  store i32 %6, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 2), align 4
   %7 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
-  store i32 %7, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 3), align 4
+  store i32 %7, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 3), align 4
   %8 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
-  store i32 %8, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 3), align 4
+  store i32 %8, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 3), align 4
   %9 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
-  store i32 %9, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 4), align 4
+  store i32 %9, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 4), align 4
   %10 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
-  store i32 %10, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 4), align 4
+  store i32 %10, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 4), align 4
   ret void
 }
 
@@ -36,32 +36,32 @@ declare i32 @calc(...)
 
 ; Function Attrs: nounwind ssp
 define internal void @calculate() #0 {
-  %1 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 0), align 4
-  %2 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 0), align 4
+  %1 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 0), align 4
+  %2 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 0), align 4
   %3 = mul nsw i32 %2, %1
-  store i32 %3, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 0), align 4
-  %4 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 1), align 4
-  %5 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 1), align 4
+  store i32 %3, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i64 0, i64 0), align 4
+  %4 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 1), align 4
+  %5 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 1), align 4
   %6 = mul nsw i32 %5, %4
-  store i32 %6, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 1), align 4
-  %7 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 2), align 4
-  %8 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 2), align 4
+  store i32 %6, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i64 0, i64 1), align 4
+  %7 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 2), align 4
+  %8 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 2), align 4
   %9 = mul nsw i32 %8, %7
-  store i32 %9, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 2), align 4
-  %10 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 3), align 4
-  %11 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 3), align 4
+  store i32 %9, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i64 0, i64 2), align 4
+  %10 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 3), align 4
+  %11 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 3), align 4
   %12 = mul nsw i32 %11, %10
-  store i32 %12, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 3), align 4
-  %13 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 4), align 4
-  %14 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 4), align 4
+  store i32 %12, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i64 0, i64 3), align 4
+  %13 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 4), align 4
+  %14 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 4), align 4
   %15 = mul nsw i32 %14, %13
-  store i32 %15, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 4), align 4
+  store i32 %15, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i64 0, i64 4), align 4
   ret void
 }
 
 ; Function Attrs: nounwind readnone ssp
 define internal i32* @returnFoo() #1 {
-  ret i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 0)
+  ret i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i64 0, i64 0)
 }
 
 ;CHECK:	.type	_MergedGlobals,@object  // @_MergedGlobals
diff --git a/test/CodeGen/AArch64/global-merge-group-by-use.ll b/test/CodeGen/AArch64/global-merge-group-by-use.ll
new file mode 100644
index 000000000000..ddc044ed9e08
--- /dev/null
+++ b/test/CodeGen/AArch64/global-merge-group-by-use.ll
@@ -0,0 +1,94 @@
+; RUN: llc -mtriple=aarch64-apple-ios -asm-verbose=false -aarch64-collect-loh=false \
+; RUN:   -aarch64-global-merge -global-merge-group-by-use -global-merge-ignore-single-use=false \
+; RUN:   %s -o - | FileCheck %s
+
+; We assume that globals of the same size aren't reordered inside a set.
+
+; Check that we create two MergedGlobal instances for two functions using
+; disjoint sets of globals
+
+@m1 = internal global i32 0, align 4
+@n1 = internal global i32 0, align 4
+
+; CHECK-LABEL: f1:
+define void @f1(i32 %a1, i32 %a2) #0 {
+; CHECK-NEXT: adrp x8, [[SET1:__MergedGlobals.[0-9]*]]@PAGE
+; CHECK-NEXT: add x8, x8, [[SET1]]@PAGEOFF
+; CHECK-NEXT: stp w0, w1, [x8]
+; CHECK-NEXT: ret
+  store i32 %a1, i32* @m1, align 4
+  store i32 %a2, i32* @n1, align 4
+  ret void
+}
+
+@m2 = internal global i32 0, align 4
+@n2 = internal global i32 0, align 4
+@o2 = internal global i32 0, align 4
+
+; CHECK-LABEL: f2:
+define void @f2(i32 %a1, i32 %a2, i32 %a3) #0 {
+; CHECK-NEXT: adrp x8, [[SET2:__MergedGlobals.[0-9]*]]@PAGE
+; CHECK-NEXT: add x8, x8, [[SET2]]@PAGEOFF
+; CHECK-NEXT: stp w0, w1, [x8]
+; CHECK-NEXT: str w2, [x8, #8]
+; CHECK-NEXT: ret
+  store i32 %a1, i32* @m2, align 4
+  store i32 %a2, i32* @n2, align 4
+  store i32 %a3, i32* @o2, align 4
+  ret void
+}
+
+; Sanity-check (don't worry about cost models) that we pick the biggest subset
+; of all global used "together" directly or indirectly.  Here, that means
+; merging n3, m4, and n4 together, but ignoring m3.
+
+@m3 = internal global i32 0, align 4
+@n3 = internal global i32 0, align 4
+
+; CHECK-LABEL: f3:
+define void @f3(i32 %a1, i32 %a2) #0 {
+; CHECK-NEXT: adrp x8, _m3@PAGE
+; CHECK-NEXT: adrp x9, [[SET3:__MergedGlobals[0-9]*]]@PAGE
+; CHECK-NEXT: str w0, [x8, _m3@PAGEOFF]
+; CHECK-NEXT: str w1, [x9, [[SET3]]@PAGEOFF]
+; CHECK-NEXT: ret
+  store i32 %a1, i32* @m3, align 4
+  store i32 %a2, i32* @n3, align 4
+  ret void
+}
+
+@m4 = internal global i32 0, align 4
+@n4 = internal global i32 0, align 4
+
+; CHECK-LABEL: f4:
+define void @f4(i32 %a1, i32 %a2, i32 %a3) #0 {
+; CHECK-NEXT: adrp x8, [[SET3]]@PAGE
+; CHECK-NEXT: add x8, x8, [[SET3]]@PAGEOFF
+; CHECK-NEXT: stp w0, w1, [x8, #4]
+; CHECK-NEXT: str w2, [x8]
+; CHECK-NEXT: ret
+  store i32 %a1, i32* @m4, align 4
+  store i32 %a2, i32* @n4, align 4
+  store i32 %a3, i32* @n3, align 4
+  ret void
+}
+
+; Finally, check that we don't do anything with one-element global sets.
+@o5 = internal global i32 0, align 4
+
+; CHECK-LABEL: f5:
+define void @f5(i32 %a1) #0 {
+; CHECK-NEXT: adrp x8, _o5@PAGE
+; CHECK-NEXT: str w0, [x8, _o5@PAGEOFF]
+; CHECK-NEXT: ret
+  store i32 %a1, i32* @o5, align 4
+  ret void
+}
+
+; CHECK-DAG: .zerofill __DATA,__bss,_o5,4,2
+
+; CHECK-DAG: .zerofill __DATA,__bss,[[SET1]],8,3
+; CHECK-DAG: .zerofill __DATA,__bss,[[SET2]],12,3
+; CHECK-DAG: .zerofill __DATA,__bss,[[SET3]],12,3
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/AArch64/global-merge-ignore-single-use.ll b/test/CodeGen/AArch64/global-merge-ignore-single-use.ll
new file mode 100644
index 000000000000..e6de4699132a
--- /dev/null
+++ b/test/CodeGen/AArch64/global-merge-ignore-single-use.ll
@@ -0,0 +1,63 @@
+; RUN: llc -mtriple=aarch64-apple-ios -asm-verbose=false -aarch64-collect-loh=false \
+; RUN:   -aarch64-global-merge -global-merge-group-by-use -global-merge-ignore-single-use \
+; RUN:   %s -o - | FileCheck %s
+
+; We assume that globals of the same size aren't reordered inside a set.
+
+@m1 = internal global i32 0, align 4
+@n1 = internal global i32 0, align 4
+@o1 = internal global i32 0, align 4
+
+; CHECK-LABEL: f1:
+define void @f1(i32 %a1, i32 %a2) #0 {
+; CHECK-NEXT: adrp x8, [[SET:__MergedGlobals]]@PAGE
+; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF
+; CHECK-NEXT: stp w0, w1, [x8]
+; CHECK-NEXT: ret
+  store i32 %a1, i32* @m1, align 4
+  store i32 %a2, i32* @n1, align 4
+  ret void
+}
+
+@m2 = internal global i32 0, align 4
+@n2 = internal global i32 0, align 4
+
+; CHECK-LABEL: f2:
+define void @f2(i32 %a1, i32 %a2, i32 %a3) #0 {
+; CHECK-NEXT: adrp x8, [[SET]]@PAGE
+; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF
+; CHECK-NEXT: stp w0, w1, [x8]
+; CHECK-NEXT: str w2, [x8, #8]
+; CHECK-NEXT: ret
+  store i32 %a1, i32* @m1, align 4
+  store i32 %a2, i32* @n1, align 4
+  store i32 %a3, i32* @o1, align 4
+  ret void
+}
+
+; CHECK-LABEL: f3:
+define void @f3(i32 %a1, i32 %a2) #0 {
+; CHECK-NEXT: adrp x8, [[SET]]@PAGE
+; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF
+; CHECK-NEXT: stp w0, w1, [x8, #12]
+; CHECK-NEXT: ret
+  store i32 %a1, i32* @m2, align 4
+  store i32 %a2, i32* @n2, align 4
+  ret void
+}
+
+@o2 = internal global i32 0, align 4
+
+; CHECK-LABEL: f4:
+define void @f4(i32 %a1) #0 {
+; CHECK-NEXT: adrp x8, _o2@PAGE
+; CHECK-NEXT: str w0, [x8, _o2@PAGEOFF]
+; CHECK-NEXT: ret
+  store i32 %a1, i32* @o2, align 4
+  ret void
+}
+
+; CHECK-DAG: .zerofill __DATA,__bss,[[SET]],20,4
+; CHECK-DAG: .zerofill __DATA,__bss,_o2,4,2
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/AArch64/half.ll b/test/CodeGen/AArch64/half.ll
index a46094b9fb85..d4cbbc918a84 100644
--- a/test/CodeGen/AArch64/half.ll
+++ b/test/CodeGen/AArch64/half.ll
@@ -4,7 +4,7 @@ define void @test_load_store(half* %in, half* %out) {
 ; CHECK-LABEL: test_load_store:
 ; CHECK: ldr [[TMP:h[0-9]+]], [x0]
 ; CHECK: str [[TMP]], [x1]
-  %val = load half* %in
+  %val = load half, half* %in
   store half %val, half* %out
   ret void
 }
@@ -12,7 +12,7 @@ define void @test_load_store(half* %in, half* %out) {
 define i16 @test_bitcast_from_half(half* %addr) {
 ; CHECK-LABEL: test_bitcast_from_half:
 ; CHECK: ldrh w0, [x0]
-  %val = load half* %addr
+  %val = load half, half* %addr
   %val_int = bitcast half %val to i16
   ret i16 %val_int
 }
@@ -50,7 +50,7 @@ define float @test_extend32(half* %addr) {
 ; CHECK-LABEL: test_extend32:
 ; CHECK: fcvt {{s[0-9]+}}, {{h[0-9]+}}
 
-  %val16 = load half* %addr
+  %val16 = load half, half* %addr
   %val32 = fpext half %val16 to float
   ret float %val32
 }
@@ -59,7 +59,7 @@ define double @test_extend64(half* %addr) {
 ; CHECK-LABEL: test_extend64:
 ; CHECK: fcvt {{d[0-9]+}}, {{h[0-9]+}}
 
-  %val16 = load half* %addr
+  %val16 = load half, half* %addr
   %val32 = fpext half %val16 to double
   ret double %val32
 }
diff --git a/test/CodeGen/AArch64/i1-contents.ll b/test/CodeGen/AArch64/i1-contents.ll
index 7f133fc3ea83..a3830e41ec5b 100644
--- a/test/CodeGen/AArch64/i1-contents.ll
+++ b/test/CodeGen/AArch64/i1-contents.ll
@@ -32,7 +32,7 @@ define i1 @produce_i1_ret() {
 ; CHECK-LABEL: produce_i1_ret:
 ; CHECK: ldr [[VAR32:w[0-9]+]], [{{x[0-9]+}}, :lo12:var]
 ; CHECK: and w0, [[VAR32]], #{{0x1|0xff}}
-  %val = load %big* @var
+  %val = load %big, %big* @var
   %val1 = trunc %big %val to i1
   ret i1 %val1
 }
@@ -42,7 +42,7 @@ define void @produce_i1_arg() {
 ; CHECK: ldr [[VAR32:w[0-9]+]], [{{x[0-9]+}}, :lo12:var]
 ; CHECK: and w0, [[VAR32]], #{{0x1|0xff}}
 ; CHECK: bl consume_i1_arg
-  %val = load %big* @var
+  %val = load %big, %big* @var
   %val1 = trunc %big %val to i1
   call void @consume_i1_arg(i1 %val1)
   ret void
diff --git a/test/CodeGen/AArch64/i128-align.ll b/test/CodeGen/AArch64/i128-align.ll
index a1b4d6f5a446..c948739853bb 100644
--- a/test/CodeGen/AArch64/i128-align.ll
+++ b/test/CodeGen/AArch64/i128-align.ll
@@ -8,7 +8,7 @@ define i64 @check_size() {
 ; CHECK-LABEL: check_size:
   %starti = ptrtoint %struct* @var to i64
 
-  %endp = getelementptr %struct* @var, i64 1
+  %endp = getelementptr %struct, %struct* @var, i64 1
   %endi = ptrtoint %struct* %endp to i64
 
   %diff = sub i64 %endi, %starti
@@ -20,7 +20,7 @@ define i64 @check_field() {
 ; CHECK-LABEL: check_field:
   %starti = ptrtoint %struct* @var to i64
 
-  %endp = getelementptr %struct* @var, i64 0, i32 1
+  %endp = getelementptr %struct, %struct* @var, i64 0, i32 1
   %endi = ptrtoint i128* %endp to i64
 
   %diff = sub i64 %endi, %starti
diff --git a/test/CodeGen/AArch64/inline-asm-globaladdress.ll b/test/CodeGen/AArch64/inline-asm-globaladdress.ll
new file mode 100644
index 000000000000..adebabaa29be
--- /dev/null
+++ b/test/CodeGen/AArch64/inline-asm-globaladdress.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -mtriple aarch64-gnu-linux | FileCheck %s
+; RUN: llc < %s -mtriple arm64-apple-darwin | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+; CHECK-LABEL: test_inlineasm_globaladdress:
+; CHECK: b {{_?}}test_symbol
+define void @test_inlineasm_globaladdress() {
+  call void asm sideeffect "b $0", "i"(void ()* @test_symbol)
+  ret void
+}
+
+; CHECK-LABEL: test_inlineasm_globaladdress_offset:
+; CHECK: b {{_?}}test_symbol+4
+define void @test_inlineasm_globaladdress_offset() {
+  call void asm sideeffect "b $0", "i"(void ()* bitcast (i8* getelementptr (i8, i8* bitcast (void ()* @test_symbol to i8*), i64 4) to void ()*))
+  ret void
+}
+
+declare void @test_symbol()
diff --git a/test/CodeGen/AArch64/intrinsics-memory-barrier.ll b/test/CodeGen/AArch64/intrinsics-memory-barrier.ll
index 09e34ae2d2ed..2a73fee7718a 100644
--- a/test/CodeGen/AArch64/intrinsics-memory-barrier.ll
+++ b/test/CodeGen/AArch64/intrinsics-memory-barrier.ll
@@ -22,7 +22,7 @@ define void @test_dmb_reordering(i32 %a, i32 %b, i32* %d) {
 
   call void @llvm.aarch64.dmb(i32 15); CHECK: dmb sy
 
-  %d1 = getelementptr i32* %d, i64 1
+  %d1 = getelementptr i32, i32* %d, i64 1
   store i32 %b, i32* %d1             ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #4]
 
   ret void
@@ -34,7 +34,7 @@ define void @test_dsb_reordering(i32 %a, i32 %b, i32* %d) {
 
   call void @llvm.aarch64.dsb(i32 15); CHECK: dsb sy
 
-  %d1 = getelementptr i32* %d, i64 1
+  %d1 = getelementptr i32, i32* %d, i64 1
   store i32 %b, i32* %d1             ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #4]
 
   ret void
@@ -46,7 +46,7 @@ define void @test_isb_reordering(i32 %a, i32 %b, i32* %d) {
 
   call void @llvm.aarch64.isb(i32 15); CHECK: isb
 
-  %d1 = getelementptr i32* %d, i64 1
+  %d1 = getelementptr i32, i32* %d, i64 1
   store i32 %b, i32* %d1             ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #4]
 
   ret void
diff --git a/test/CodeGen/AArch64/large_shift.ll b/test/CodeGen/AArch64/large_shift.ll
new file mode 100644
index 000000000000..f72c97d25aa3
--- /dev/null
+++ b/test/CodeGen/AArch64/large_shift.ll
@@ -0,0 +1,21 @@
+; RUN: llc -march=aarch64 -o - %s
+target triple = "arm64-unknown-unknown"
+
+; Make sure we don't run into an assert in the aarch64 code selection when
+; DAGCombining fails.
+
+declare void @t()
+
+define void @foo() {
+  %c = bitcast i64 270458 to i64
+  %t0 = lshr i64 %c, 422383
+  %t1 = trunc i64 %t0 to i1
+  br i1 %t1, label %BB1, label %BB0
+
+BB0:
+  call void @t()
+  br label %BB1
+
+BB1:
+  ret void
+}
diff --git a/test/CodeGen/AArch64/ldst-opt.ll b/test/CodeGen/AArch64/ldst-opt.ll
index e4f4295c8503..b2c11c7517c0 100644
--- a/test/CodeGen/AArch64/ldst-opt.ll
+++ b/test/CodeGen/AArch64/ldst-opt.ll
@@ -30,11 +30,11 @@ define void @load-pre-indexed-word(%struct.word* %ptr) nounwind {
 ; CHECK-LABEL: load-pre-indexed-word
 ; CHECK: ldr w{{[0-9]+}}, [x{{[0-9]+}}, #32]!
 entry:
-  %a = getelementptr inbounds %struct.word* %ptr, i64 0, i32 1, i32 0
-  %add = load i32* %a, align 4
+  %a = getelementptr inbounds %struct.word, %struct.word* %ptr, i64 0, i32 1, i32 0
+  %add = load i32, i32* %a, align 4
   br label %bar
 bar:
-  %c = getelementptr inbounds %struct.word* %ptr, i64 0, i32 1
+  %c = getelementptr inbounds %struct.word, %struct.word* %ptr, i64 0, i32 1
   tail call void @bar_word(%s.word* %c, i32 %add)
   ret void
 }
@@ -43,11 +43,11 @@ define void @store-pre-indexed-word(%struct.word* %ptr, i32 %val) nounwind {
 ; CHECK-LABEL: store-pre-indexed-word
 ; CHECK: str w{{[0-9]+}}, [x{{[0-9]+}}, #32]!
 entry:
-  %a = getelementptr inbounds %struct.word* %ptr, i64 0, i32 1, i32 0
+  %a = getelementptr inbounds %struct.word, %struct.word* %ptr, i64 0, i32 1, i32 0
   store i32 %val, i32* %a, align 4
   br label %bar
 bar:
-  %c = getelementptr inbounds %struct.word* %ptr, i64 0, i32 1
+  %c = getelementptr inbounds %struct.word, %struct.word* %ptr, i64 0, i32 1
   tail call void @bar_word(%s.word* %c, i32 %val)
   ret void
 }
@@ -58,11 +58,11 @@ define void @load-pre-indexed-doubleword(%struct.doubleword* %ptr) nounwind {
 ; CHECK-LABEL: load-pre-indexed-doubleword
 ; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}, #32]!
 entry:
-  %a = getelementptr inbounds %struct.doubleword* %ptr, i64 0, i32 1, i32 0
-  %add = load i64* %a, align 4
+  %a = getelementptr inbounds %struct.doubleword, %struct.doubleword* %ptr, i64 0, i32 1, i32 0
+  %add = load i64, i64* %a, align 4
   br label %bar
 bar:
-  %c = getelementptr inbounds %struct.doubleword* %ptr, i64 0, i32 1
+  %c = getelementptr inbounds %struct.doubleword, %struct.doubleword* %ptr, i64 0, i32 1
   tail call void @bar_doubleword(%s.doubleword* %c, i64 %add)
   ret void
 }
@@ -71,11 +71,11 @@ define void @store-pre-indexed-doubleword(%struct.doubleword* %ptr, i64 %val) no
 ; CHECK-LABEL: store-pre-indexed-doubleword
 ; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}, #32]!
 entry:
-  %a = getelementptr inbounds %struct.doubleword* %ptr, i64 0, i32 1, i32 0
+  %a = getelementptr inbounds %struct.doubleword, %struct.doubleword* %ptr, i64 0, i32 1, i32 0
   store i64 %val, i64* %a, align 4
   br label %bar
 bar:
-  %c = getelementptr inbounds %struct.doubleword* %ptr, i64 0, i32 1
+  %c = getelementptr inbounds %struct.doubleword, %struct.doubleword* %ptr, i64 0, i32 1
   tail call void @bar_doubleword(%s.doubleword* %c, i64 %val)
   ret void
 }
@@ -86,11 +86,11 @@ define void @load-pre-indexed-quadword(%struct.quadword* %ptr) nounwind {
 ; CHECK-LABEL: load-pre-indexed-quadword
 ; CHECK: ldr q{{[0-9]+}}, [x{{[0-9]+}}, #32]!
 entry:
-  %a = getelementptr inbounds %struct.quadword* %ptr, i64 0, i32 1, i32 0
-  %add = load fp128* %a, align 4
+  %a = getelementptr inbounds %struct.quadword, %struct.quadword* %ptr, i64 0, i32 1, i32 0
+  %add = load fp128, fp128* %a, align 4
   br label %bar
 bar:
-  %c = getelementptr inbounds %struct.quadword* %ptr, i64 0, i32 1
+  %c = getelementptr inbounds %struct.quadword, %struct.quadword* %ptr, i64 0, i32 1
   tail call void @bar_quadword(%s.quadword* %c, fp128 %add)
   ret void
 }
@@ -99,11 +99,11 @@ define void @store-pre-indexed-quadword(%struct.quadword* %ptr, fp128 %val) noun
 ; CHECK-LABEL: store-pre-indexed-quadword
 ; CHECK: str q{{[0-9]+}}, [x{{[0-9]+}}, #32]!
 entry:
-  %a = getelementptr inbounds %struct.quadword* %ptr, i64 0, i32 1, i32 0
+  %a = getelementptr inbounds %struct.quadword, %struct.quadword* %ptr, i64 0, i32 1, i32 0
   store fp128 %val, fp128* %a, align 4
   br label %bar
 bar:
-  %c = getelementptr inbounds %struct.quadword* %ptr, i64 0, i32 1
+  %c = getelementptr inbounds %struct.quadword, %struct.quadword* %ptr, i64 0, i32 1
   tail call void @bar_quadword(%s.quadword* %c, fp128 %val)
   ret void
 }
@@ -114,11 +114,11 @@ define void @load-pre-indexed-float(%struct.float* %ptr) nounwind {
 ; CHECK-LABEL: load-pre-indexed-float
 ; CHECK: ldr s{{[0-9]+}}, [x{{[0-9]+}}, #32]!
 entry:
-  %a = getelementptr inbounds %struct.float* %ptr, i64 0, i32 1, i32 0
-  %add = load float* %a, align 4
+  %a = getelementptr inbounds %struct.float, %struct.float* %ptr, i64 0, i32 1, i32 0
+  %add = load float, float* %a, align 4
   br label %bar
 bar:
-  %c = getelementptr inbounds %struct.float* %ptr, i64 0, i32 1
+  %c = getelementptr inbounds %struct.float, %struct.float* %ptr, i64 0, i32 1
   tail call void @bar_float(%s.float* %c, float %add)
   ret void
 }
@@ -127,11 +127,11 @@ define void @store-pre-indexed-float(%struct.float* %ptr, float %val) nounwind {
 ; CHECK-LABEL: store-pre-indexed-float
 ; CHECK: str s{{[0-9]+}}, [x{{[0-9]+}}, #32]!
 entry:
-  %a = getelementptr inbounds %struct.float* %ptr, i64 0, i32 1, i32 0
+  %a = getelementptr inbounds %struct.float, %struct.float* %ptr, i64 0, i32 1, i32 0
   store float %val, float* %a, align 4
   br label %bar
 bar:
-  %c = getelementptr inbounds %struct.float* %ptr, i64 0, i32 1
+  %c = getelementptr inbounds %struct.float, %struct.float* %ptr, i64 0, i32 1
   tail call void @bar_float(%s.float* %c, float %val)
   ret void
 }
@@ -142,11 +142,11 @@ define void @load-pre-indexed-double(%struct.double* %ptr) nounwind {
 ; CHECK-LABEL: load-pre-indexed-double
 ; CHECK: ldr d{{[0-9]+}}, [x{{[0-9]+}}, #32]!
 entry:
-  %a = getelementptr inbounds %struct.double* %ptr, i64 0, i32 1, i32 0
-  %add = load double* %a, align 4
+  %a = getelementptr inbounds %struct.double, %struct.double* %ptr, i64 0, i32 1, i32 0
+  %add = load double, double* %a, align 4
   br label %bar
 bar:
-  %c = getelementptr inbounds %struct.double* %ptr, i64 0, i32 1
+  %c = getelementptr inbounds %struct.double, %struct.double* %ptr, i64 0, i32 1
   tail call void @bar_double(%s.double* %c, double %add)
   ret void
 }
@@ -155,11 +155,11 @@ define void @store-pre-indexed-double(%struct.double* %ptr, double %val) nounwin
 ; CHECK-LABEL: store-pre-indexed-double
 ; CHECK: str d{{[0-9]+}}, [x{{[0-9]+}}, #32]!
 entry:
-  %a = getelementptr inbounds %struct.double* %ptr, i64 0, i32 1, i32 0
+  %a = getelementptr inbounds %struct.double, %struct.double* %ptr, i64 0, i32 1, i32 0
   store double %val, double* %a, align 4
   br label %bar
 bar:
-  %c = getelementptr inbounds %struct.double* %ptr, i64 0, i32 1
+  %c = getelementptr inbounds %struct.double, %struct.double* %ptr, i64 0, i32 1
   tail call void @bar_double(%s.double* %c, double %val)
   ret void
 }
@@ -186,15 +186,15 @@ define i32 @load-pre-indexed-word2(%pre.struct.i32** %this, i1 %cond,
 ; CHECK: ldr w{{[0-9]+}}, [x{{[0-9]+}}, #4]!
   br i1 %cond, label %if.then, label %if.end
 if.then:
-  %load1 = load %pre.struct.i32** %this
-  %gep1 = getelementptr inbounds %pre.struct.i32* %load1, i64 0, i32 1
+  %load1 = load %pre.struct.i32*, %pre.struct.i32** %this
+  %gep1 = getelementptr inbounds %pre.struct.i32, %pre.struct.i32* %load1, i64 0, i32 1
   br label %return
 if.end:
-  %gep2 = getelementptr inbounds %pre.struct.i32* %load2, i64 0, i32 2
+  %gep2 = getelementptr inbounds %pre.struct.i32, %pre.struct.i32* %load2, i64 0, i32 2
   br label %return
 return:
   %retptr = phi i32* [ %gep1, %if.then ], [ %gep2, %if.end ]
-  %ret = load i32* %retptr
+  %ret = load i32, i32* %retptr
   ret i32 %ret
 }
 
@@ -204,15 +204,15 @@ define i64 @load-pre-indexed-doubleword2(%pre.struct.i64** %this, i1 %cond,
 ; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}, #8]!
   br i1 %cond, label %if.then, label %if.end
 if.then:
-  %load1 = load %pre.struct.i64** %this
-  %gep1 = getelementptr inbounds %pre.struct.i64* %load1, i64 0, i32 1
+  %load1 = load %pre.struct.i64*, %pre.struct.i64** %this
+  %gep1 = getelementptr inbounds %pre.struct.i64, %pre.struct.i64* %load1, i64 0, i32 1
   br label %return
 if.end:
-  %gep2 = getelementptr inbounds %pre.struct.i64* %load2, i64 0, i32 2
+  %gep2 = getelementptr inbounds %pre.struct.i64, %pre.struct.i64* %load2, i64 0, i32 2
   br label %return
 return:
   %retptr = phi i64* [ %gep1, %if.then ], [ %gep2, %if.end ]
-  %ret = load i64* %retptr
+  %ret = load i64, i64* %retptr
   ret i64 %ret
 }
 
@@ -222,15 +222,15 @@ define <2 x i64> @load-pre-indexed-quadword2(%pre.struct.i128** %this, i1 %cond,
 ; CHECK: ldr q{{[0-9]+}}, [x{{[0-9]+}}, #16]!
   br i1 %cond, label %if.then, label %if.end
 if.then:
-  %load1 = load %pre.struct.i128** %this
-  %gep1 = getelementptr inbounds %pre.struct.i128* %load1, i64 0, i32 1
+  %load1 = load %pre.struct.i128*, %pre.struct.i128** %this
+  %gep1 = getelementptr inbounds %pre.struct.i128, %pre.struct.i128* %load1, i64 0, i32 1
   br label %return
 if.end:
-  %gep2 = getelementptr inbounds %pre.struct.i128* %load2, i64 0, i32 2
+  %gep2 = getelementptr inbounds %pre.struct.i128, %pre.struct.i128* %load2, i64 0, i32 2
   br label %return
 return:
   %retptr = phi <2 x i64>* [ %gep1, %if.then ], [ %gep2, %if.end ]
-  %ret = load <2 x i64>* %retptr
+  %ret = load <2 x i64>, <2 x i64>* %retptr
   ret <2 x i64> %ret
 }
 
@@ -240,15 +240,15 @@ define float @load-pre-indexed-float2(%pre.struct.float** %this, i1 %cond,
 ; CHECK: ldr s{{[0-9]+}}, [x{{[0-9]+}}, #4]!
   br i1 %cond, label %if.then, label %if.end
 if.then:
-  %load1 = load %pre.struct.float** %this
-  %gep1 = getelementptr inbounds %pre.struct.float* %load1, i64 0, i32 1
+  %load1 = load %pre.struct.float*, %pre.struct.float** %this
+  %gep1 = getelementptr inbounds %pre.struct.float, %pre.struct.float* %load1, i64 0, i32 1
   br label %return
 if.end:
-  %gep2 = getelementptr inbounds %pre.struct.float* %load2, i64 0, i32 2
+  %gep2 = getelementptr inbounds %pre.struct.float, %pre.struct.float* %load2, i64 0, i32 2
   br label %return
 return:
   %retptr = phi float* [ %gep1, %if.then ], [ %gep2, %if.end ]
-  %ret = load float* %retptr
+  %ret = load float, float* %retptr
   ret float %ret
 }
 
@@ -258,15 +258,15 @@ define double @load-pre-indexed-double2(%pre.struct.double** %this, i1 %cond,
 ; CHECK: ldr d{{[0-9]+}}, [x{{[0-9]+}}, #8]!
   br i1 %cond, label %if.then, label %if.end
 if.then:
-  %load1 = load %pre.struct.double** %this
-  %gep1 = getelementptr inbounds %pre.struct.double* %load1, i64 0, i32 1
+  %load1 = load %pre.struct.double*, %pre.struct.double** %this
+  %gep1 = getelementptr inbounds %pre.struct.double, %pre.struct.double* %load1, i64 0, i32 1
   br label %return
 if.end:
-  %gep2 = getelementptr inbounds %pre.struct.double* %load2, i64 0, i32 2
+  %gep2 = getelementptr inbounds %pre.struct.double, %pre.struct.double* %load2, i64 0, i32 2
   br label %return
 return:
   %retptr = phi double* [ %gep1, %if.then ], [ %gep2, %if.end ]
-  %ret = load double* %retptr
+  %ret = load double, double* %retptr
   ret double %ret
 }
 
@@ -287,11 +287,11 @@ define void @store-pre-indexed-word2(%pre.struct.i32** %this, i1 %cond,
 ; CHECK: str w{{[0-9]+}}, [x{{[0-9]+}}, #4]!
   br i1 %cond, label %if.then, label %if.end
 if.then:
-  %load1 = load %pre.struct.i32** %this
-  %gep1 = getelementptr inbounds %pre.struct.i32* %load1, i64 0, i32 1
+  %load1 = load %pre.struct.i32*, %pre.struct.i32** %this
+  %gep1 = getelementptr inbounds %pre.struct.i32, %pre.struct.i32* %load1, i64 0, i32 1
   br label %return
 if.end:
-  %gep2 = getelementptr inbounds %pre.struct.i32* %load2, i64 0, i32 2
+  %gep2 = getelementptr inbounds %pre.struct.i32, %pre.struct.i32* %load2, i64 0, i32 2
   br label %return
 return:
   %retptr = phi i32* [ %gep1, %if.then ], [ %gep2, %if.end ]
@@ -306,11 +306,11 @@ define void @store-pre-indexed-doubleword2(%pre.struct.i64** %this, i1 %cond,
 ; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}, #8]!
   br i1 %cond, label %if.then, label %if.end
 if.then:
-  %load1 = load %pre.struct.i64** %this
-  %gep1 = getelementptr inbounds %pre.struct.i64* %load1, i64 0, i32 1
+  %load1 = load %pre.struct.i64*, %pre.struct.i64** %this
+  %gep1 = getelementptr inbounds %pre.struct.i64, %pre.struct.i64* %load1, i64 0, i32 1
   br label %return
 if.end:
-  %gep2 = getelementptr inbounds %pre.struct.i64* %load2, i64 0, i32 2
+  %gep2 = getelementptr inbounds %pre.struct.i64, %pre.struct.i64* %load2, i64 0, i32 2
   br label %return
 return:
   %retptr = phi i64* [ %gep1, %if.then ], [ %gep2, %if.end ]
@@ -325,11 +325,11 @@ define void @store-pre-indexed-quadword2(%pre.struct.i128** %this, i1 %cond,
 ; CHECK: str q{{[0-9]+}}, [x{{[0-9]+}}, #16]!
   br i1 %cond, label %if.then, label %if.end
 if.then:
-  %load1 = load %pre.struct.i128** %this
-  %gep1 = getelementptr inbounds %pre.struct.i128* %load1, i64 0, i32 1
+  %load1 = load %pre.struct.i128*, %pre.struct.i128** %this
+  %gep1 = getelementptr inbounds %pre.struct.i128, %pre.struct.i128* %load1, i64 0, i32 1
   br label %return
 if.end:
-  %gep2 = getelementptr inbounds %pre.struct.i128* %load2, i64 0, i32 2
+  %gep2 = getelementptr inbounds %pre.struct.i128, %pre.struct.i128* %load2, i64 0, i32 2
   br label %return
 return:
   %retptr = phi <2 x i64>* [ %gep1, %if.then ], [ %gep2, %if.end ]
@@ -344,11 +344,11 @@ define void @store-pre-indexed-float2(%pre.struct.float** %this, i1 %cond,
 ; CHECK: str s{{[0-9]+}}, [x{{[0-9]+}}, #4]!
   br i1 %cond, label %if.then, label %if.end
 if.then:
-  %load1 = load %pre.struct.float** %this
-  %gep1 = getelementptr inbounds %pre.struct.float* %load1, i64 0, i32 1
+  %load1 = load %pre.struct.float*, %pre.struct.float** %this
+  %gep1 = getelementptr inbounds %pre.struct.float, %pre.struct.float* %load1, i64 0, i32 1
   br label %return
 if.end:
-  %gep2 = getelementptr inbounds %pre.struct.float* %load2, i64 0, i32 2
+  %gep2 = getelementptr inbounds %pre.struct.float, %pre.struct.float* %load2, i64 0, i32 2
   br label %return
 return:
   %retptr = phi float* [ %gep1, %if.then ], [ %gep2, %if.end ]
@@ -363,11 +363,11 @@ define void @store-pre-indexed-double2(%pre.struct.double** %this, i1 %cond,
 ; CHECK: str d{{[0-9]+}}, [x{{[0-9]+}}, #8]!
   br i1 %cond, label %if.then, label %if.end
 if.then:
-  %load1 = load %pre.struct.double** %this
-  %gep1 = getelementptr inbounds %pre.struct.double* %load1, i64 0, i32 1
+  %load1 = load %pre.struct.double*, %pre.struct.double** %this
+  %gep1 = getelementptr inbounds %pre.struct.double, %pre.struct.double* %load1, i64 0, i32 1
   br label %return
 if.end:
-  %gep2 = getelementptr inbounds %pre.struct.double* %load2, i64 0, i32 2
+  %gep2 = getelementptr inbounds %pre.struct.double, %pre.struct.double* %load2, i64 0, i32 2
   br label %return
 return:
   %retptr = phi double* [ %gep1, %if.then ], [ %gep2, %if.end ]
@@ -389,19 +389,19 @@ define void @load-post-indexed-word(i32* %array, i64 %count) nounwind {
 ; CHECK-LABEL: load-post-indexed-word
 ; CHECK: ldr w{{[0-9]+}}, [x{{[0-9]+}}], #16
 entry:
-  %gep1 = getelementptr i32* %array, i64 2
+  %gep1 = getelementptr i32, i32* %array, i64 2
   br label %body
 
 body:
   %iv2 = phi i32* [ %gep3, %body ], [ %gep1, %entry ]
   %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ]
-  %gep2 = getelementptr i32* %iv2, i64 -1
-  %load = load i32* %gep2
+  %gep2 = getelementptr i32, i32* %iv2, i64 -1
+  %load = load i32, i32* %gep2
   call void @use-word(i32 %load)
-  %load2 = load i32* %iv2
+  %load2 = load i32, i32* %iv2
   call void @use-word(i32 %load2)
   %iv.next = add i64 %iv, -4
-  %gep3 = getelementptr i32* %iv2, i64 4
+  %gep3 = getelementptr i32, i32* %iv2, i64 4
   %cond = icmp eq i64 %iv.next, 0
   br i1 %cond, label %exit, label %body
 
@@ -413,19 +413,19 @@ define void @load-post-indexed-doubleword(i64* %array, i64 %count) nounwind {
 ; CHECK-LABEL: load-post-indexed-doubleword
 ; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}], #32
 entry:
-  %gep1 = getelementptr i64* %array, i64 2
+  %gep1 = getelementptr i64, i64* %array, i64 2
   br label %body
 
 body:
   %iv2 = phi i64* [ %gep3, %body ], [ %gep1, %entry ]
   %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ]
-  %gep2 = getelementptr i64* %iv2, i64 -1
-  %load = load i64* %gep2
+  %gep2 = getelementptr i64, i64* %iv2, i64 -1
+  %load = load i64, i64* %gep2
   call void @use-doubleword(i64 %load)
-  %load2 = load i64* %iv2
+  %load2 = load i64, i64* %iv2
   call void @use-doubleword(i64 %load2)
   %iv.next = add i64 %iv, -4
-  %gep3 = getelementptr i64* %iv2, i64 4
+  %gep3 = getelementptr i64, i64* %iv2, i64 4
   %cond = icmp eq i64 %iv.next, 0
   br i1 %cond, label %exit, label %body
 
@@ -437,19 +437,19 @@ define void @load-post-indexed-quadword(<2 x i64>* %array, i64 %count) nounwind
 ; CHECK-LABEL: load-post-indexed-quadword
 ; CHECK: ldr q{{[0-9]+}}, [x{{[0-9]+}}], #64
 entry:
-  %gep1 = getelementptr <2 x i64>* %array, i64 2
+  %gep1 = getelementptr <2 x i64>, <2 x i64>* %array, i64 2
   br label %body
 
 body:
   %iv2 = phi <2 x i64>* [ %gep3, %body ], [ %gep1, %entry ]
   %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ]
-  %gep2 = getelementptr <2 x i64>* %iv2, i64 -1
-  %load = load <2 x i64>* %gep2
+  %gep2 = getelementptr <2 x i64>, <2 x i64>* %iv2, i64 -1
+  %load = load <2 x i64>, <2 x i64>* %gep2
   call void @use-quadword(<2 x i64> %load)
-  %load2 = load <2 x i64>* %iv2
+  %load2 = load <2 x i64>, <2 x i64>* %iv2
   call void @use-quadword(<2 x i64> %load2)
   %iv.next = add i64 %iv, -4
-  %gep3 = getelementptr <2 x i64>* %iv2, i64 4
+  %gep3 = getelementptr <2 x i64>, <2 x i64>* %iv2, i64 4
   %cond = icmp eq i64 %iv.next, 0
   br i1 %cond, label %exit, label %body
 
@@ -461,19 +461,19 @@ define void @load-post-indexed-float(float* %array, i64 %count) nounwind {
 ; CHECK-LABEL: load-post-indexed-float
 ; CHECK: ldr s{{[0-9]+}}, [x{{[0-9]+}}], #16
 entry:
-  %gep1 = getelementptr float* %array, i64 2
+  %gep1 = getelementptr float, float* %array, i64 2
   br label %body
 
 body:
   %iv2 = phi float* [ %gep3, %body ], [ %gep1, %entry ]
   %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ]
-  %gep2 = getelementptr float* %iv2, i64 -1
-  %load = load float* %gep2
+  %gep2 = getelementptr float, float* %iv2, i64 -1
+  %load = load float, float* %gep2
   call void @use-float(float %load)
-  %load2 = load float* %iv2
+  %load2 = load float, float* %iv2
   call void @use-float(float %load2)
   %iv.next = add i64 %iv, -4
-  %gep3 = getelementptr float* %iv2, i64 4
+  %gep3 = getelementptr float, float* %iv2, i64 4
   %cond = icmp eq i64 %iv.next, 0
   br i1 %cond, label %exit, label %body
 
@@ -485,19 +485,19 @@ define void @load-post-indexed-double(double* %array, i64 %count) nounwind {
 ; CHECK-LABEL: load-post-indexed-double
 ; CHECK: ldr d{{[0-9]+}}, [x{{[0-9]+}}], #32
 entry:
-  %gep1 = getelementptr double* %array, i64 2
+  %gep1 = getelementptr double, double* %array, i64 2
   br label %body
 
 body:
   %iv2 = phi double* [ %gep3, %body ], [ %gep1, %entry ]
   %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ]
-  %gep2 = getelementptr double* %iv2, i64 -1
-  %load = load double* %gep2
+  %gep2 = getelementptr double, double* %iv2, i64 -1
+  %load = load double, double* %gep2
   call void @use-double(double %load)
-  %load2 = load double* %iv2
+  %load2 = load double, double* %iv2
   call void @use-double(double %load2)
   %iv.next = add i64 %iv, -4
-  %gep3 = getelementptr double* %iv2, i64 4
+  %gep3 = getelementptr double, double* %iv2, i64 4
   %cond = icmp eq i64 %iv.next, 0
   br i1 %cond, label %exit, label %body
 
@@ -519,18 +519,18 @@ define void @store-post-indexed-word(i32* %array, i64 %count, i32 %val) nounwind
 ; CHECK-LABEL: store-post-indexed-word
 ; CHECK: str w{{[0-9]+}}, [x{{[0-9]+}}], #16
 entry:
-  %gep1 = getelementptr i32* %array, i64 2
+  %gep1 = getelementptr i32, i32* %array, i64 2
   br label %body
 
 body:
   %iv2 = phi i32* [ %gep3, %body ], [ %gep1, %entry ]
   %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ]
-  %gep2 = getelementptr i32* %iv2, i64 -1
-  %load = load i32* %gep2
+  %gep2 = getelementptr i32, i32* %iv2, i64 -1
+  %load = load i32, i32* %gep2
   call void @use-word(i32 %load)
   store i32 %val, i32* %iv2
   %iv.next = add i64 %iv, -4
-  %gep3 = getelementptr i32* %iv2, i64 4
+  %gep3 = getelementptr i32, i32* %iv2, i64 4
   %cond = icmp eq i64 %iv.next, 0
   br i1 %cond, label %exit, label %body
 
@@ -542,18 +542,18 @@ define void @store-post-indexed-doubleword(i64* %array, i64 %count, i64 %val) no
 ; CHECK-LABEL: store-post-indexed-doubleword
 ; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}], #32
 entry:
-  %gep1 = getelementptr i64* %array, i64 2
+  %gep1 = getelementptr i64, i64* %array, i64 2
   br label %body
 
 body:
   %iv2 = phi i64* [ %gep3, %body ], [ %gep1, %entry ]
   %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ]
-  %gep2 = getelementptr i64* %iv2, i64 -1
-  %load = load i64* %gep2
+  %gep2 = getelementptr i64, i64* %iv2, i64 -1
+  %load = load i64, i64* %gep2
   call void @use-doubleword(i64 %load)
   store i64 %val, i64* %iv2
   %iv.next = add i64 %iv, -4
-  %gep3 = getelementptr i64* %iv2, i64 4
+  %gep3 = getelementptr i64, i64* %iv2, i64 4
   %cond = icmp eq i64 %iv.next, 0
   br i1 %cond, label %exit, label %body
 
@@ -565,18 +565,18 @@ define void @store-post-indexed-quadword(<2 x i64>* %array, i64 %count, <2 x i64
 ; CHECK-LABEL: store-post-indexed-quadword
 ; CHECK: str q{{[0-9]+}}, [x{{[0-9]+}}], #64
 entry:
-  %gep1 = getelementptr <2 x i64>* %array, i64 2
+  %gep1 = getelementptr <2 x i64>, <2 x i64>* %array, i64 2
   br label %body
 
 body:
   %iv2 = phi <2 x i64>* [ %gep3, %body ], [ %gep1, %entry ]
   %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ]
-  %gep2 = getelementptr <2 x i64>* %iv2, i64 -1
-  %load = load <2 x i64>* %gep2
+  %gep2 = getelementptr <2 x i64>, <2 x i64>* %iv2, i64 -1
+  %load = load <2 x i64>, <2 x i64>* %gep2
   call void @use-quadword(<2 x i64> %load)
   store <2 x i64> %val, <2 x i64>* %iv2
   %iv.next = add i64 %iv, -4
-  %gep3 = getelementptr <2 x i64>* %iv2, i64 4
+  %gep3 = getelementptr <2 x i64>, <2 x i64>* %iv2, i64 4
   %cond = icmp eq i64 %iv.next, 0
   br i1 %cond, label %exit, label %body
 
@@ -588,18 +588,18 @@ define void @store-post-indexed-float(float* %array, i64 %count, float %val) nou
 ; CHECK-LABEL: store-post-indexed-float
 ; CHECK: str s{{[0-9]+}}, [x{{[0-9]+}}], #16
 entry:
-  %gep1 = getelementptr float* %array, i64 2
+  %gep1 = getelementptr float, float* %array, i64 2
   br label %body
 
 body:
   %iv2 = phi float* [ %gep3, %body ], [ %gep1, %entry ]
   %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ]
-  %gep2 = getelementptr float* %iv2, i64 -1
-  %load = load float* %gep2
+  %gep2 = getelementptr float, float* %iv2, i64 -1
+  %load = load float, float* %gep2
   call void @use-float(float %load)
   store float %val, float* %iv2
   %iv.next = add i64 %iv, -4
-  %gep3 = getelementptr float* %iv2, i64 4
+  %gep3 = getelementptr float, float* %iv2, i64 4
   %cond = icmp eq i64 %iv.next, 0
   br i1 %cond, label %exit, label %body
 
@@ -611,18 +611,18 @@ define void @store-post-indexed-double(double* %array, i64 %count, double %val)
 ; CHECK-LABEL: store-post-indexed-double
 ; CHECK: str d{{[0-9]+}}, [x{{[0-9]+}}], #32
 entry:
-  %gep1 = getelementptr double* %array, i64 2
+  %gep1 = getelementptr double, double* %array, i64 2
   br label %body
 
 body:
   %iv2 = phi double* [ %gep3, %body ], [ %gep1, %entry ]
   %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ]
-  %gep2 = getelementptr double* %iv2, i64 -1
-  %load = load double* %gep2
+  %gep2 = getelementptr double, double* %iv2, i64 -1
+  %load = load double, double* %gep2
   call void @use-double(double %load)
   store double %val, double* %iv2
   %iv.next = add i64 %iv, -4
-  %gep3 = getelementptr double* %iv2, i64 4
+  %gep3 = getelementptr double, double* %iv2, i64 4
   %cond = icmp eq i64 %iv.next, 0
   br i1 %cond, label %exit, label %body
 
@@ -655,15 +655,15 @@ for.body:
   %phi1 = phi i32* [ %gep4, %for.body ], [ %b, %0 ]
   %phi2 = phi i32* [ %gep3, %for.body ], [ %a, %0 ]
   %i = phi i64 [ %dec.i, %for.body], [ %count, %0 ]
-  %gep1 = getelementptr i32* %phi1, i64 -1
-  %load1 = load i32* %gep1
-  %gep2 = getelementptr i32* %phi2, i64 -1
+  %gep1 = getelementptr i32, i32* %phi1, i64 -1
+  %load1 = load i32, i32* %gep1
+  %gep2 = getelementptr i32, i32* %phi2, i64 -1
   store i32 %load1, i32* %gep2
-  %load2 = load i32* %phi1
+  %load2 = load i32, i32* %phi1
   store i32 %load2, i32* %phi2
   %dec.i = add nsw i64 %i, -1
-  %gep3 = getelementptr i32* %phi2, i64 -2
-  %gep4 = getelementptr i32* %phi1, i64 -2
+  %gep3 = getelementptr i32, i32* %phi2, i64 -2
+  %gep4 = getelementptr i32, i32* %phi1, i64 -2
   %cond = icmp sgt i64 %dec.i, 0
   br i1 %cond, label %for.body, label %end
 end:
@@ -679,15 +679,15 @@ for.body:
   %phi1 = phi i64* [ %gep4, %for.body ], [ %b, %0 ]
   %phi2 = phi i64* [ %gep3, %for.body ], [ %a, %0 ]
   %i = phi i64 [ %dec.i, %for.body], [ %count, %0 ]
-  %gep1 = getelementptr i64* %phi1, i64 -1
-  %load1 = load i64* %gep1
-  %gep2 = getelementptr i64* %phi2, i64 -1
+  %gep1 = getelementptr i64, i64* %phi1, i64 -1
+  %load1 = load i64, i64* %gep1
+  %gep2 = getelementptr i64, i64* %phi2, i64 -1
   store i64 %load1, i64* %gep2
-  %load2 = load i64* %phi1
+  %load2 = load i64, i64* %phi1
   store i64 %load2, i64* %phi2
   %dec.i = add nsw i64 %i, -1
-  %gep3 = getelementptr i64* %phi2, i64 -2
-  %gep4 = getelementptr i64* %phi1, i64 -2
+  %gep3 = getelementptr i64, i64* %phi2, i64 -2
+  %gep4 = getelementptr i64, i64* %phi1, i64 -2
   %cond = icmp sgt i64 %dec.i, 0
   br i1 %cond, label %for.body, label %end
 end:
@@ -703,15 +703,15 @@ for.body:
   %phi1 = phi <2 x i64>* [ %gep4, %for.body ], [ %b, %0 ]
   %phi2 = phi <2 x i64>* [ %gep3, %for.body ], [ %a, %0 ]
   %i = phi i64 [ %dec.i, %for.body], [ %count, %0 ]
-  %gep1 = getelementptr <2 x i64>* %phi1, i64 -1
-  %load1 = load <2 x i64>* %gep1
-  %gep2 = getelementptr <2 x i64>* %phi2, i64 -1
+  %gep1 = getelementptr <2 x i64>, <2 x i64>* %phi1, i64 -1
+  %load1 = load <2 x i64>, <2 x i64>* %gep1
+  %gep2 = getelementptr <2 x i64>, <2 x i64>* %phi2, i64 -1
   store <2 x i64> %load1, <2 x i64>* %gep2
-  %load2 = load <2 x i64>* %phi1
+  %load2 = load <2 x i64>, <2 x i64>* %phi1
   store <2 x i64> %load2, <2 x i64>* %phi2
   %dec.i = add nsw i64 %i, -1
-  %gep3 = getelementptr <2 x i64>* %phi2, i64 -2
-  %gep4 = getelementptr <2 x i64>* %phi1, i64 -2
+  %gep3 = getelementptr <2 x i64>, <2 x i64>* %phi2, i64 -2
+  %gep4 = getelementptr <2 x i64>, <2 x i64>* %phi1, i64 -2
   %cond = icmp sgt i64 %dec.i, 0
   br i1 %cond, label %for.body, label %end
 end:
@@ -727,15 +727,15 @@ for.body:
   %phi1 = phi float* [ %gep4, %for.body ], [ %b, %0 ]
   %phi2 = phi float* [ %gep3, %for.body ], [ %a, %0 ]
   %i = phi i64 [ %dec.i, %for.body], [ %count, %0 ]
-  %gep1 = getelementptr float* %phi1, i64 -1
-  %load1 = load float* %gep1
-  %gep2 = getelementptr float* %phi2, i64 -1
+  %gep1 = getelementptr float, float* %phi1, i64 -1
+  %load1 = load float, float* %gep1
+  %gep2 = getelementptr float, float* %phi2, i64 -1
   store float %load1, float* %gep2
-  %load2 = load float* %phi1
+  %load2 = load float, float* %phi1
   store float %load2, float* %phi2
   %dec.i = add nsw i64 %i, -1
-  %gep3 = getelementptr float* %phi2, i64 -2
-  %gep4 = getelementptr float* %phi1, i64 -2
+  %gep3 = getelementptr float, float* %phi2, i64 -2
+  %gep4 = getelementptr float, float* %phi1, i64 -2
   %cond = icmp sgt i64 %dec.i, 0
   br i1 %cond, label %for.body, label %end
 end:
@@ -751,15 +751,15 @@ for.body:
   %phi1 = phi double* [ %gep4, %for.body ], [ %b, %0 ]
   %phi2 = phi double* [ %gep3, %for.body ], [ %a, %0 ]
   %i = phi i64 [ %dec.i, %for.body], [ %count, %0 ]
-  %gep1 = getelementptr double* %phi1, i64 -1
-  %load1 = load double* %gep1
-  %gep2 = getelementptr double* %phi2, i64 -1
+  %gep1 = getelementptr double, double* %phi1, i64 -1
+  %load1 = load double, double* %gep1
+  %gep2 = getelementptr double, double* %phi2, i64 -1
   store double %load1, double* %gep2
-  %load2 = load double* %phi1
+  %load2 = load double, double* %phi1
   store double %load2, double* %phi2
   %dec.i = add nsw i64 %i, -1
-  %gep3 = getelementptr double* %phi2, i64 -2
-  %gep4 = getelementptr double* %phi1, i64 -2
+  %gep3 = getelementptr double, double* %phi2, i64 -2
+  %gep4 = getelementptr double, double* %phi1, i64 -2
   %cond = icmp sgt i64 %dec.i, 0
   br i1 %cond, label %for.body, label %end
 end:
diff --git a/test/CodeGen/AArch64/ldst-regoffset.ll b/test/CodeGen/AArch64/ldst-regoffset.ll
index e2fa08bcce69..85d6db104b66 100644
--- a/test/CodeGen/AArch64/ldst-regoffset.ll
+++ b/test/CodeGen/AArch64/ldst-regoffset.ll
@@ -12,14 +12,14 @@
 define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) minsize {
 ; CHECK-LABEL: ldst_8bit:
 
-   %addr8_sxtw = getelementptr i8* %base, i32 %off32
-   %val8_sxtw = load volatile i8* %addr8_sxtw
+   %addr8_sxtw = getelementptr i8, i8* %base, i32 %off32
+   %val8_sxtw = load volatile i8, i8* %addr8_sxtw
    %val32_signed = sext i8 %val8_sxtw to i32
    store volatile i32 %val32_signed, i32* @var_32bit
 ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{[wx][0-9]+}}, sxtw]
 
-  %addr_lsl = getelementptr i8* %base, i64 %off64
-  %val8_lsl = load volatile i8* %addr_lsl
+  %addr_lsl = getelementptr i8, i8* %base, i64 %off64
+  %val8_lsl = load volatile i8, i8* %addr_lsl
   %val32_unsigned = zext i8 %val8_lsl to i32
   store volatile i32 %val32_unsigned, i32* @var_32bit
 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]
@@ -28,7 +28,7 @@ define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) minsize {
   %offset_uxtw = zext i32 %off32 to i64
   %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw
   %addr_uxtw = inttoptr i64 %addrint1_uxtw to i8*
-  %val8_uxtw = load volatile i8* %addr_uxtw
+  %val8_uxtw = load volatile i8, i8* %addr_uxtw
   %newval8 = add i8 %val8_uxtw, 1
   store volatile i8 %newval8, i8* @var_8bit
 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw]
@@ -40,14 +40,14 @@ define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) minsize {
 define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) minsize {
 ; CHECK-LABEL: ldst_16bit:
 
-   %addr8_sxtwN = getelementptr i16* %base, i32 %off32
-   %val8_sxtwN = load volatile i16* %addr8_sxtwN
+   %addr8_sxtwN = getelementptr i16, i16* %base, i32 %off32
+   %val8_sxtwN = load volatile i16, i16* %addr8_sxtwN
    %val32_signed = sext i16 %val8_sxtwN to i32
    store volatile i32 %val32_signed, i32* @var_32bit
 ; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #1]
 
-  %addr_lslN = getelementptr i16* %base, i64 %off64
-  %val8_lslN = load volatile i16* %addr_lslN
+  %addr_lslN = getelementptr i16, i16* %base, i64 %off64
+  %val8_lslN = load volatile i16, i16* %addr_lslN
   %val32_unsigned = zext i16 %val8_lslN to i32
   store volatile i32 %val32_unsigned, i32* @var_32bit
 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #1]
@@ -56,7 +56,7 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) minsize {
   %offset_uxtw = zext i32 %off32 to i64
   %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw
   %addr_uxtw = inttoptr i64 %addrint1_uxtw to i16*
-  %val8_uxtw = load volatile i16* %addr_uxtw
+  %val8_uxtw = load volatile i16, i16* %addr_uxtw
   %newval8 = add i16 %val8_uxtw, 1
   store volatile i16 %newval8, i16* @var_16bit
 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw]
@@ -65,7 +65,7 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) minsize {
   %offset_sxtw = sext i32 %off32 to i64
   %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw
   %addr_sxtw = inttoptr i64 %addrint_sxtw to i16*
-  %val16_sxtw = load volatile i16* %addr_sxtw
+  %val16_sxtw = load volatile i16, i16* %addr_sxtw
   %val64_signed = sext i16 %val16_sxtw to i64
   store volatile i64 %val64_signed, i64* @var_64bit
 ; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{[wx][0-9]+}}, sxtw]
@@ -74,7 +74,7 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) minsize {
   %base_lsl = ptrtoint i16* %base to i64
   %addrint_lsl = add i64 %base_lsl, %off64
   %addr_lsl = inttoptr i64 %addrint_lsl to i16*
-  %val16_lsl = load volatile i16* %addr_lsl
+  %val16_lsl = load volatile i16, i16* %addr_lsl
   %val64_unsigned = zext i16 %val16_lsl to i64
   store volatile i64 %val64_unsigned, i64* @var_64bit
 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]
@@ -84,7 +84,7 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) minsize {
   %offset2_uxtwN = shl i64 %offset_uxtwN, 1
   %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN
   %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i16*
-  %val32 = load volatile i32* @var_32bit
+  %val32 = load volatile i32, i32* @var_32bit
   %val16_trunc32 = trunc i32 %val32 to i16
   store volatile i16 %val16_trunc32, i16* %addr_uxtwN
 ; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #1]
@@ -94,13 +94,13 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) minsize {
 define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) minsize {
 ; CHECK-LABEL: ldst_32bit:
 
-   %addr_sxtwN = getelementptr i32* %base, i32 %off32
-   %val_sxtwN = load volatile i32* %addr_sxtwN
+   %addr_sxtwN = getelementptr i32, i32* %base, i32 %off32
+   %val_sxtwN = load volatile i32, i32* %addr_sxtwN
    store volatile i32 %val_sxtwN, i32* @var_32bit
 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #2]
 
-  %addr_lslN = getelementptr i32* %base, i64 %off64
-  %val_lslN = load volatile i32* %addr_lslN
+  %addr_lslN = getelementptr i32, i32* %base, i64 %off64
+  %val_lslN = load volatile i32, i32* %addr_lslN
   store volatile i32 %val_lslN, i32* @var_32bit
 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #2]
 
@@ -108,7 +108,7 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) minsize {
   %offset_uxtw = zext i32 %off32 to i64
   %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw
   %addr_uxtw = inttoptr i64 %addrint1_uxtw to i32*
-  %val_uxtw = load volatile i32* %addr_uxtw
+  %val_uxtw = load volatile i32, i32* %addr_uxtw
   %newval8 = add i32 %val_uxtw, 1
   store volatile i32 %newval8, i32* @var_32bit
 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw]
@@ -118,7 +118,7 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) minsize {
   %offset_sxtw = sext i32 %off32 to i64
   %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw
   %addr_sxtw = inttoptr i64 %addrint_sxtw to i32*
-  %val16_sxtw = load volatile i32* %addr_sxtw
+  %val16_sxtw = load volatile i32, i32* %addr_sxtw
   %val64_signed = sext i32 %val16_sxtw to i64
   store volatile i64 %val64_signed, i64* @var_64bit
 ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]
@@ -127,7 +127,7 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) minsize {
   %base_lsl = ptrtoint i32* %base to i64
   %addrint_lsl = add i64 %base_lsl, %off64
   %addr_lsl = inttoptr i64 %addrint_lsl to i32*
-  %val16_lsl = load volatile i32* %addr_lsl
+  %val16_lsl = load volatile i32, i32* %addr_lsl
   %val64_unsigned = zext i32 %val16_lsl to i64
   store volatile i64 %val64_unsigned, i64* @var_64bit
 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]
@@ -137,7 +137,7 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) minsize {
   %offset2_uxtwN = shl i64 %offset_uxtwN, 2
   %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN
   %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i32*
-  %val32 = load volatile i32* @var_32bit
+  %val32 = load volatile i32, i32* @var_32bit
   store volatile i32 %val32, i32* %addr_uxtwN
 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #2]
    ret void
@@ -146,13 +146,13 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) minsize {
 define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) minsize {
 ; CHECK-LABEL: ldst_64bit:
 
-   %addr_sxtwN = getelementptr i64* %base, i32 %off32
-   %val_sxtwN = load volatile i64* %addr_sxtwN
+   %addr_sxtwN = getelementptr i64, i64* %base, i32 %off32
+   %val_sxtwN = load volatile i64, i64* %addr_sxtwN
    store volatile i64 %val_sxtwN, i64* @var_64bit
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #3]
 
-  %addr_lslN = getelementptr i64* %base, i64 %off64
-  %val_lslN = load volatile i64* %addr_lslN
+  %addr_lslN = getelementptr i64, i64* %base, i64 %off64
+  %val_lslN = load volatile i64, i64* %addr_lslN
   store volatile i64 %val_lslN, i64* @var_64bit
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #3]
 
@@ -160,7 +160,7 @@ define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) minsize {
   %offset_uxtw = zext i32 %off32 to i64
   %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw
   %addr_uxtw = inttoptr i64 %addrint1_uxtw to i64*
-  %val8_uxtw = load volatile i64* %addr_uxtw
+  %val8_uxtw = load volatile i64, i64* %addr_uxtw
   %newval8 = add i64 %val8_uxtw, 1
   store volatile i64 %newval8, i64* @var_64bit
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw]
@@ -169,14 +169,14 @@ define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) minsize {
   %offset_sxtw = sext i32 %off32 to i64
   %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw
   %addr_sxtw = inttoptr i64 %addrint_sxtw to i64*
-  %val64_sxtw = load volatile i64* %addr_sxtw
+  %val64_sxtw = load volatile i64, i64* %addr_sxtw
   store volatile i64 %val64_sxtw, i64* @var_64bit
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]
 
   %base_lsl = ptrtoint i64* %base to i64
   %addrint_lsl = add i64 %base_lsl, %off64
   %addr_lsl = inttoptr i64 %addrint_lsl to i64*
-  %val64_lsl = load volatile i64* %addr_lsl
+  %val64_lsl = load volatile i64, i64* %addr_lsl
   store volatile i64 %val64_lsl, i64* @var_64bit
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]
 
@@ -185,7 +185,7 @@ define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) minsize {
   %offset2_uxtwN = shl i64 %offset_uxtwN, 3
   %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN
   %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i64*
-  %val64 = load volatile i64* @var_64bit
+  %val64 = load volatile i64, i64* @var_64bit
   store volatile i64 %val64, i64* %addr_uxtwN
 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #3]
    ret void
@@ -194,14 +194,14 @@ define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) minsize {
 define void @ldst_float(float* %base, i32 %off32, i64 %off64) minsize {
 ; CHECK-LABEL: ldst_float:
 
-   %addr_sxtwN = getelementptr float* %base, i32 %off32
-   %val_sxtwN = load volatile float* %addr_sxtwN
+   %addr_sxtwN = getelementptr float, float* %base, i32 %off32
+   %val_sxtwN = load volatile float, float* %addr_sxtwN
    store volatile float %val_sxtwN, float* @var_float
 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #2]
 ; CHECK-NOFP-NOT: ldr {{s[0-9]+}},
 
-  %addr_lslN = getelementptr float* %base, i64 %off64
-  %val_lslN = load volatile float* %addr_lslN
+  %addr_lslN = getelementptr float, float* %base, i64 %off64
+  %val_lslN = load volatile float, float* %addr_lslN
   store volatile float %val_lslN, float* @var_float
 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #2]
 ; CHECK-NOFP-NOT: ldr {{s[0-9]+}},
@@ -210,7 +210,7 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) minsize {
   %offset_uxtw = zext i32 %off32 to i64
   %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw
   %addr_uxtw = inttoptr i64 %addrint1_uxtw to float*
-  %val_uxtw = load volatile float* %addr_uxtw
+  %val_uxtw = load volatile float, float* %addr_uxtw
   store volatile float %val_uxtw, float* @var_float
 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw]
 ; CHECK-NOFP-NOT: ldr {{s[0-9]+}},
@@ -219,7 +219,7 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) minsize {
   %offset_sxtw = sext i32 %off32 to i64
   %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw
   %addr_sxtw = inttoptr i64 %addrint_sxtw to float*
-  %val64_sxtw = load volatile float* %addr_sxtw
+  %val64_sxtw = load volatile float, float* %addr_sxtw
   store volatile float %val64_sxtw, float* @var_float
 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]
 ; CHECK-NOFP-NOT: ldr {{s[0-9]+}},
@@ -227,7 +227,7 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) minsize {
   %base_lsl = ptrtoint float* %base to i64
   %addrint_lsl = add i64 %base_lsl, %off64
   %addr_lsl = inttoptr i64 %addrint_lsl to float*
-  %val64_lsl = load volatile float* %addr_lsl
+  %val64_lsl = load volatile float, float* %addr_lsl
   store volatile float %val64_lsl, float* @var_float
 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]
 ; CHECK-NOFP-NOT: ldr {{s[0-9]+}},
@@ -237,7 +237,7 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) minsize {
   %offset2_uxtwN = shl i64 %offset_uxtwN, 2
   %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN
   %addr_uxtwN = inttoptr i64 %addrint_uxtwN to float*
-  %val64 = load volatile float* @var_float
+  %val64 = load volatile float, float* @var_float
   store volatile float %val64, float* %addr_uxtwN
 ; CHECK: str {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #2]
 ; CHECK-NOFP-NOT: ldr {{s[0-9]+}},
@@ -247,14 +247,14 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) minsize {
 define void @ldst_double(double* %base, i32 %off32, i64 %off64) minsize {
 ; CHECK-LABEL: ldst_double:
 
-   %addr_sxtwN = getelementptr double* %base, i32 %off32
-   %val_sxtwN = load volatile double* %addr_sxtwN
+   %addr_sxtwN = getelementptr double, double* %base, i32 %off32
+   %val_sxtwN = load volatile double, double* %addr_sxtwN
    store volatile double %val_sxtwN, double* @var_double
 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #3]
 ; CHECK-NOFP-NOT: ldr {{d[0-9]+}},
 
-  %addr_lslN = getelementptr double* %base, i64 %off64
-  %val_lslN = load volatile double* %addr_lslN
+  %addr_lslN = getelementptr double, double* %base, i64 %off64
+  %val_lslN = load volatile double, double* %addr_lslN
   store volatile double %val_lslN, double* @var_double
 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #3]
 ; CHECK-NOFP-NOT: ldr {{d[0-9]+}},
@@ -263,7 +263,7 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) minsize {
   %offset_uxtw = zext i32 %off32 to i64
   %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw
   %addr_uxtw = inttoptr i64 %addrint1_uxtw to double*
-  %val_uxtw = load volatile double* %addr_uxtw
+  %val_uxtw = load volatile double, double* %addr_uxtw
   store volatile double %val_uxtw, double* @var_double
 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw]
 ; CHECK-NOFP-NOT: ldr {{d[0-9]+}},
@@ -272,7 +272,7 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) minsize {
   %offset_sxtw = sext i32 %off32 to i64
   %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw
   %addr_sxtw = inttoptr i64 %addrint_sxtw to double*
-  %val64_sxtw = load volatile double* %addr_sxtw
+  %val64_sxtw = load volatile double, double* %addr_sxtw
   store volatile double %val64_sxtw, double* @var_double
 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]
 ; CHECK-NOFP-NOT: ldr {{d[0-9]+}},
@@ -280,7 +280,7 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) minsize {
   %base_lsl = ptrtoint double* %base to i64
   %addrint_lsl = add i64 %base_lsl, %off64
   %addr_lsl = inttoptr i64 %addrint_lsl to double*
-  %val64_lsl = load volatile double* %addr_lsl
+  %val64_lsl = load volatile double, double* %addr_lsl
   store volatile double %val64_lsl, double* @var_double
 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]
 ; CHECK-NOFP-NOT: ldr {{d[0-9]+}},
@@ -290,7 +290,7 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) minsize {
   %offset2_uxtwN = shl i64 %offset_uxtwN, 3
   %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN
   %addr_uxtwN = inttoptr i64 %addrint_uxtwN to double*
-  %val64 = load volatile double* @var_double
+  %val64 = load volatile double, double* @var_double
   store volatile double %val64, double* %addr_uxtwN
 ; CHECK: str {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #3]
 ; CHECK-NOFP-NOT: ldr {{d[0-9]+}},
@@ -301,14 +301,14 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) minsize {
 define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) minsize {
 ; CHECK-LABEL: ldst_128bit:
 
-   %addr_sxtwN = getelementptr fp128* %base, i32 %off32
-   %val_sxtwN = load volatile fp128* %addr_sxtwN
+   %addr_sxtwN = getelementptr fp128, fp128* %base, i32 %off32
+   %val_sxtwN = load volatile fp128, fp128* %addr_sxtwN
    store volatile fp128 %val_sxtwN, fp128* %base
 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4]
 ; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4]
 
-  %addr_lslN = getelementptr fp128* %base, i64 %off64
-  %val_lslN = load volatile fp128* %addr_lslN
+  %addr_lslN = getelementptr fp128, fp128* %base, i64 %off64
+  %val_lslN = load volatile fp128, fp128* %addr_lslN
   store volatile fp128 %val_lslN, fp128* %base
 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #4]
 ; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4]
@@ -317,7 +317,7 @@ define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) minsize {
   %offset_uxtw = zext i32 %off32 to i64
   %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw
   %addr_uxtw = inttoptr i64 %addrint1_uxtw to fp128*
-  %val_uxtw = load volatile fp128* %addr_uxtw
+  %val_uxtw = load volatile fp128, fp128* %addr_uxtw
   store volatile fp128 %val_uxtw, fp128* %base
 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw]
 ; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4]
@@ -326,7 +326,7 @@ define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) minsize {
   %offset_sxtw = sext i32 %off32 to i64
   %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw
   %addr_sxtw = inttoptr i64 %addrint_sxtw to fp128*
-  %val64_sxtw = load volatile fp128* %addr_sxtw
+  %val64_sxtw = load volatile fp128, fp128* %addr_sxtw
   store volatile fp128 %val64_sxtw, fp128* %base
 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]
 ; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4]
@@ -334,7 +334,7 @@ define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) minsize {
   %base_lsl = ptrtoint fp128* %base to i64
   %addrint_lsl = add i64 %base_lsl, %off64
   %addr_lsl = inttoptr i64 %addrint_lsl to fp128*
-  %val64_lsl = load volatile fp128* %addr_lsl
+  %val64_lsl = load volatile fp128, fp128* %addr_lsl
   store volatile fp128 %val64_lsl, fp128* %base
 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]
 ; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4]
@@ -344,7 +344,7 @@ define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) minsize {
   %offset2_uxtwN = shl i64 %offset_uxtwN, 4
   %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN
   %addr_uxtwN = inttoptr i64 %addrint_uxtwN to fp128*
-  %val64 = load volatile fp128* %base
+  %val64 = load volatile fp128, fp128* %base
   store volatile fp128 %val64, fp128* %addr_uxtwN
 ; CHECK: str {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #4]
 ; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4]
diff --git a/test/CodeGen/AArch64/ldst-unscaledimm.ll b/test/CodeGen/AArch64/ldst-unscaledimm.ll
index 1de8443d9ed2..a3625975822c 100644
--- a/test/CodeGen/AArch64/ldst-unscaledimm.ll
+++ b/test/CodeGen/AArch64/ldst-unscaledimm.ll
@@ -16,32 +16,32 @@ define void @ldst_8bit() {
 
 ; No architectural support for loads to 16-bit or 8-bit since we
 ; promote i8 during lowering.
-  %addr_8bit = load i8** @varptr
+  %addr_8bit = load i8*, i8** @varptr
 
 ; match a sign-extending load 8-bit -> 32-bit
-   %addr_sext32 = getelementptr i8* %addr_8bit, i64 -256
-   %val8_sext32 = load volatile i8* %addr_sext32
+   %addr_sext32 = getelementptr i8, i8* %addr_8bit, i64 -256
+   %val8_sext32 = load volatile i8, i8* %addr_sext32
    %val32_signed = sext i8 %val8_sext32 to i32
    store volatile i32 %val32_signed, i32* @var_32bit
 ; CHECK: ldursb {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
 
 ; match a zero-extending load volatile 8-bit -> 32-bit
-  %addr_zext32 = getelementptr i8* %addr_8bit, i64 -12
-  %val8_zext32 = load volatile i8* %addr_zext32
+  %addr_zext32 = getelementptr i8, i8* %addr_8bit, i64 -12
+  %val8_zext32 = load volatile i8, i8* %addr_zext32
   %val32_unsigned = zext i8 %val8_zext32 to i32
   store volatile i32 %val32_unsigned, i32* @var_32bit
 ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-12]
 
 ; match an any-extending load volatile 8-bit -> 32-bit
-  %addr_anyext = getelementptr i8* %addr_8bit, i64 -1
-  %val8_anyext = load volatile i8* %addr_anyext
+  %addr_anyext = getelementptr i8, i8* %addr_8bit, i64 -1
+  %val8_anyext = load volatile i8, i8* %addr_anyext
   %newval8 = add i8 %val8_anyext, 1
   store volatile i8 %newval8, i8* @var_8bit
 ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
 
 ; match a sign-extending load volatile 8-bit -> 64-bit
-  %addr_sext64 = getelementptr i8* %addr_8bit, i64 -5
-  %val8_sext64 = load volatile i8* %addr_sext64
+  %addr_sext64 = getelementptr i8, i8* %addr_8bit, i64 -5
+  %val8_sext64 = load volatile i8, i8* %addr_sext64
   %val64_signed = sext i8 %val8_sext64 to i64
   store volatile i64 %val64_signed, i64* @var_64bit
 ; CHECK: ldursb {{x[0-9]+}}, [{{x[0-9]+}}, #-5]
@@ -49,22 +49,22 @@ define void @ldst_8bit() {
 ; match a zero-extending load volatile 8-bit -> 64-bit.
 ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits
 ; of x0 so it's identical to load volatileing to 32-bits.
-  %addr_zext64 = getelementptr i8* %addr_8bit, i64 -9
-  %val8_zext64 = load volatile i8* %addr_zext64
+  %addr_zext64 = getelementptr i8, i8* %addr_8bit, i64 -9
+  %val8_zext64 = load volatile i8, i8* %addr_zext64
   %val64_unsigned = zext i8 %val8_zext64 to i64
   store volatile i64 %val64_unsigned, i64* @var_64bit
 ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-9]
 
 ; truncating store volatile 32-bits to 8-bits
-  %addr_trunc32 = getelementptr i8* %addr_8bit, i64 -256
-  %val32 = load volatile i32* @var_32bit
+  %addr_trunc32 = getelementptr i8, i8* %addr_8bit, i64 -256
+  %val32 = load volatile i32, i32* @var_32bit
   %val8_trunc32 = trunc i32 %val32 to i8
   store volatile i8 %val8_trunc32, i8* %addr_trunc32
 ; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
 
 ; truncating store volatile 64-bits to 8-bits
-  %addr_trunc64 = getelementptr i8* %addr_8bit, i64 -1
-  %val64 = load volatile i64* @var_64bit
+  %addr_trunc64 = getelementptr i8, i8* %addr_8bit, i64 -1
+  %val64 = load volatile i64, i64* @var_64bit
   %val8_trunc64 = trunc i64 %val64 to i8
   store volatile i8 %val8_trunc64, i8* %addr_trunc64
 ; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
@@ -77,36 +77,36 @@ define void @ldst_16bit() {
 
 ; No architectural support for loads to 16-bit or 16-bit since we
 ; promote i16 during lowering.
-  %addr_8bit = load i8** @varptr
+  %addr_8bit = load i8*, i8** @varptr
 
 ; match a sign-extending load 16-bit -> 32-bit
-   %addr8_sext32 = getelementptr i8* %addr_8bit, i64 -256
+   %addr8_sext32 = getelementptr i8, i8* %addr_8bit, i64 -256
    %addr_sext32 = bitcast i8* %addr8_sext32 to i16*
-   %val16_sext32 = load volatile i16* %addr_sext32
+   %val16_sext32 = load volatile i16, i16* %addr_sext32
    %val32_signed = sext i16 %val16_sext32 to i32
    store volatile i32 %val32_signed, i32* @var_32bit
 ; CHECK: ldursh {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
 
 ; match a zero-extending load volatile 16-bit -> 32-bit. With offset that would be unaligned.
-  %addr8_zext32 = getelementptr i8* %addr_8bit, i64 15
+  %addr8_zext32 = getelementptr i8, i8* %addr_8bit, i64 15
   %addr_zext32 = bitcast i8* %addr8_zext32 to i16*
-  %val16_zext32 = load volatile i16* %addr_zext32
+  %val16_zext32 = load volatile i16, i16* %addr_zext32
   %val32_unsigned = zext i16 %val16_zext32 to i32
   store volatile i32 %val32_unsigned, i32* @var_32bit
 ; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #15]
 
 ; match an any-extending load volatile 16-bit -> 32-bit
-  %addr8_anyext = getelementptr i8* %addr_8bit, i64 -1
+  %addr8_anyext = getelementptr i8, i8* %addr_8bit, i64 -1
   %addr_anyext = bitcast i8* %addr8_anyext to i16*
-  %val16_anyext = load volatile i16* %addr_anyext
+  %val16_anyext = load volatile i16, i16* %addr_anyext
   %newval16 = add i16 %val16_anyext, 1
   store volatile i16 %newval16, i16* @var_16bit
 ; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
 
 ; match a sign-extending load volatile 16-bit -> 64-bit
-  %addr8_sext64 = getelementptr i8* %addr_8bit, i64 -5
+  %addr8_sext64 = getelementptr i8, i8* %addr_8bit, i64 -5
   %addr_sext64 = bitcast i8* %addr8_sext64 to i16*
-  %val16_sext64 = load volatile i16* %addr_sext64
+  %val16_sext64 = load volatile i16, i16* %addr_sext64
   %val64_signed = sext i16 %val16_sext64 to i64
   store volatile i64 %val64_signed, i64* @var_64bit
 ; CHECK: ldursh {{x[0-9]+}}, [{{x[0-9]+}}, #-5]
@@ -114,25 +114,25 @@ define void @ldst_16bit() {
 ; match a zero-extending load volatile 16-bit -> 64-bit.
 ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits
 ; of x0 so it's identical to load volatileing to 32-bits.
-  %addr8_zext64 = getelementptr i8* %addr_8bit, i64 9
+  %addr8_zext64 = getelementptr i8, i8* %addr_8bit, i64 9
   %addr_zext64 = bitcast i8* %addr8_zext64 to i16*
-  %val16_zext64 = load volatile i16* %addr_zext64
+  %val16_zext64 = load volatile i16, i16* %addr_zext64
   %val64_unsigned = zext i16 %val16_zext64 to i64
   store volatile i64 %val64_unsigned, i64* @var_64bit
 ; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #9]
 
 ; truncating store volatile 32-bits to 16-bits
-  %addr8_trunc32 = getelementptr i8* %addr_8bit, i64 -256
+  %addr8_trunc32 = getelementptr i8, i8* %addr_8bit, i64 -256
   %addr_trunc32 = bitcast i8* %addr8_trunc32 to i16*
-  %val32 = load volatile i32* @var_32bit
+  %val32 = load volatile i32, i32* @var_32bit
   %val16_trunc32 = trunc i32 %val32 to i16
   store volatile i16 %val16_trunc32, i16* %addr_trunc32
 ; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
 
 ; truncating store volatile 64-bits to 16-bits
-  %addr8_trunc64 = getelementptr i8* %addr_8bit, i64 -1
+  %addr8_trunc64 = getelementptr i8, i8* %addr_8bit, i64 -1
   %addr_trunc64 = bitcast i8* %addr8_trunc64 to i16*
-  %val64 = load volatile i64* @var_64bit
+  %val64 = load volatile i64, i64* @var_64bit
   %val16_trunc64 = trunc i64 %val64 to i16
   store volatile i16 %val16_trunc64, i16* %addr_trunc64
 ; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
@@ -143,41 +143,41 @@ define void @ldst_16bit() {
 define void @ldst_32bit() {
 ; CHECK-LABEL: ldst_32bit:
 
-  %addr_8bit = load i8** @varptr
+  %addr_8bit = load i8*, i8** @varptr
 
 ; Straight 32-bit load/store
-  %addr32_8_noext = getelementptr i8* %addr_8bit, i64 1
+  %addr32_8_noext = getelementptr i8, i8* %addr_8bit, i64 1
   %addr32_noext = bitcast i8* %addr32_8_noext to i32*
-  %val32_noext = load volatile i32* %addr32_noext
+  %val32_noext = load volatile i32, i32* %addr32_noext
   store volatile i32 %val32_noext, i32* %addr32_noext
 ; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #1]
 ; CHECK: stur {{w[0-9]+}}, [{{x[0-9]+}}, #1]
 
 ; Zero-extension to 64-bits
-  %addr32_8_zext = getelementptr i8* %addr_8bit, i64 -256
+  %addr32_8_zext = getelementptr i8, i8* %addr_8bit, i64 -256
   %addr32_zext = bitcast i8* %addr32_8_zext to i32*
-  %val32_zext = load volatile i32* %addr32_zext
+  %val32_zext = load volatile i32, i32* %addr32_zext
   %val64_unsigned = zext i32 %val32_zext to i64
   store volatile i64 %val64_unsigned, i64* @var_64bit
 ; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
 
 ; Sign-extension to 64-bits
-  %addr32_8_sext = getelementptr i8* %addr_8bit, i64 -12
+  %addr32_8_sext = getelementptr i8, i8* %addr_8bit, i64 -12
   %addr32_sext = bitcast i8* %addr32_8_sext to i32*
-  %val32_sext = load volatile i32* %addr32_sext
+  %val32_sext = load volatile i32, i32* %addr32_sext
   %val64_signed = sext i32 %val32_sext to i64
   store volatile i64 %val64_signed, i64* @var_64bit
 ; CHECK: ldursw {{x[0-9]+}}, [{{x[0-9]+}}, #-12]
 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
 
 ; Truncation from 64-bits
-  %addr64_8_trunc = getelementptr i8* %addr_8bit, i64 255
+  %addr64_8_trunc = getelementptr i8, i8* %addr_8bit, i64 255
   %addr64_trunc = bitcast i8* %addr64_8_trunc to i64*
-  %addr32_8_trunc = getelementptr i8* %addr_8bit, i64 -20
+  %addr32_8_trunc = getelementptr i8, i8* %addr_8bit, i64 -20
   %addr32_trunc = bitcast i8* %addr32_8_trunc to i32*
 
-  %val64_trunc = load volatile i64* %addr64_trunc
+  %val64_trunc = load volatile i64, i64* %addr64_trunc
   %val32_trunc = trunc i64 %val64_trunc to i32
   store volatile i32 %val32_trunc, i32* %addr32_trunc
 ; CHECK: ldur {{x[0-9]+}}, [{{x[0-9]+}}, #255]
@@ -189,11 +189,11 @@ define void @ldst_32bit() {
 define void @ldst_float() {
 ; CHECK-LABEL: ldst_float:
 
-  %addr_8bit = load i8** @varptr
-  %addrfp_8 = getelementptr i8* %addr_8bit, i64 -5
+  %addr_8bit = load i8*, i8** @varptr
+  %addrfp_8 = getelementptr i8, i8* %addr_8bit, i64 -5
   %addrfp = bitcast i8* %addrfp_8 to float*
 
-  %valfp = load volatile float* %addrfp
+  %valfp = load volatile float, float* %addrfp
 ; CHECK: ldur {{s[0-9]+}}, [{{x[0-9]+}}, #-5]
 ; CHECK-NOFP-NOT: ldur {{s[0-9]+}},
 
@@ -207,11 +207,11 @@ define void @ldst_float() {
 define void @ldst_double() {
 ; CHECK-LABEL: ldst_double:
 
-  %addr_8bit = load i8** @varptr
-  %addrfp_8 = getelementptr i8* %addr_8bit, i64 4
+  %addr_8bit = load i8*, i8** @varptr
+  %addrfp_8 = getelementptr i8, i8* %addr_8bit, i64 4
   %addrfp = bitcast i8* %addrfp_8 to double*
 
-  %valfp = load volatile double* %addrfp
+  %valfp = load volatile double, double* %addrfp
 ; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #4]
 ; CHECK-NOFP-NOT: ldur {{d[0-9]+}},
 
diff --git a/test/CodeGen/AArch64/ldst-unsignedimm.ll b/test/CodeGen/AArch64/ldst-unsignedimm.ll
index e171d22b6c7c..9777d3ed0ff9 100644
--- a/test/CodeGen/AArch64/ldst-unsignedimm.ll
+++ b/test/CodeGen/AArch64/ldst-unsignedimm.ll
@@ -16,26 +16,26 @@ define void @ldst_8bit() {
 ; promote i8 during lowering.
 
 ; match a sign-extending load 8-bit -> 32-bit
-   %val8_sext32 = load volatile i8* @var_8bit
+   %val8_sext32 = load volatile i8, i8* @var_8bit
    %val32_signed = sext i8 %val8_sext32 to i32
    store volatile i32 %val32_signed, i32* @var_32bit
 ; CHECK: adrp {{x[0-9]+}}, var_8bit
 ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
 
 ; match a zero-extending load volatile 8-bit -> 32-bit
-  %val8_zext32 = load volatile i8* @var_8bit
+  %val8_zext32 = load volatile i8, i8* @var_8bit
   %val32_unsigned = zext i8 %val8_zext32 to i32
   store volatile i32 %val32_unsigned, i32* @var_32bit
 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
 
 ; match an any-extending load volatile 8-bit -> 32-bit
-  %val8_anyext = load volatile i8* @var_8bit
+  %val8_anyext = load volatile i8, i8* @var_8bit
   %newval8 = add i8 %val8_anyext, 1
   store volatile i8 %newval8, i8* @var_8bit
 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
 
 ; match a sign-extending load volatile 8-bit -> 64-bit
-  %val8_sext64 = load volatile i8* @var_8bit
+  %val8_sext64 = load volatile i8, i8* @var_8bit
   %val64_signed = sext i8 %val8_sext64 to i64
   store volatile i64 %val64_signed, i64* @var_64bit
 ; CHECK: ldrsb {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
@@ -43,19 +43,19 @@ define void @ldst_8bit() {
 ; match a zero-extending load volatile 8-bit -> 64-bit.
 ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits
 ; of x0 so it's identical to load volatileing to 32-bits.
-  %val8_zext64 = load volatile i8* @var_8bit
+  %val8_zext64 = load volatile i8, i8* @var_8bit
   %val64_unsigned = zext i8 %val8_zext64 to i64
   store volatile i64 %val64_unsigned, i64* @var_64bit
 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
 
 ; truncating store volatile 32-bits to 8-bits
-  %val32 = load volatile i32* @var_32bit
+  %val32 = load volatile i32, i32* @var_32bit
   %val8_trunc32 = trunc i32 %val32 to i8
   store volatile i8 %val8_trunc32, i8* @var_8bit
 ; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
 
 ; truncating store volatile 64-bits to 8-bits
-  %val64 = load volatile i64* @var_64bit
+  %val64 = load volatile i64, i64* @var_64bit
   %val8_trunc64 = trunc i64 %val64 to i8
   store volatile i8 %val8_trunc64, i8* @var_8bit
 ; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
@@ -70,26 +70,26 @@ define void @ldst_16bit() {
 ; lowering.
 
 ; match a sign-extending load volatile 16-bit -> 32-bit
-  %val16_sext32 = load volatile i16* @var_16bit
+  %val16_sext32 = load volatile i16, i16* @var_16bit
   %val32_signed = sext i16 %val16_sext32 to i32
   store volatile i32 %val32_signed, i32* @var_32bit
 ; CHECK: adrp {{x[0-9]+}}, var_16bit
 ; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
 
 ; match a zero-extending load volatile 16-bit -> 32-bit
-  %val16_zext32 = load volatile i16* @var_16bit
+  %val16_zext32 = load volatile i16, i16* @var_16bit
   %val32_unsigned = zext i16 %val16_zext32 to i32
   store volatile i32 %val32_unsigned, i32* @var_32bit
 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
 
 ; match an any-extending load volatile 16-bit -> 32-bit
-  %val16_anyext = load volatile i16* @var_16bit
+  %val16_anyext = load volatile i16, i16* @var_16bit
   %newval16 = add i16 %val16_anyext, 1
   store volatile i16 %newval16, i16* @var_16bit
 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
 
 ; match a sign-extending load volatile 16-bit -> 64-bit
-  %val16_sext64 = load volatile i16* @var_16bit
+  %val16_sext64 = load volatile i16, i16* @var_16bit
   %val64_signed = sext i16 %val16_sext64 to i64
   store volatile i64 %val64_signed, i64* @var_64bit
 ; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
@@ -97,19 +97,19 @@ define void @ldst_16bit() {
 ; match a zero-extending load volatile 16-bit -> 64-bit.
 ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits
 ; of x0 so it's identical to load volatileing to 32-bits.
-  %val16_zext64 = load volatile i16* @var_16bit
+  %val16_zext64 = load volatile i16, i16* @var_16bit
   %val64_unsigned = zext i16 %val16_zext64 to i64
   store volatile i64 %val64_unsigned, i64* @var_64bit
 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
 
 ; truncating store volatile 32-bits to 16-bits
-  %val32 = load volatile i32* @var_32bit
+  %val32 = load volatile i32, i32* @var_32bit
   %val16_trunc32 = trunc i32 %val32 to i16
   store volatile i16 %val16_trunc32, i16* @var_16bit
 ; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
 
 ; truncating store volatile 64-bits to 16-bits
-  %val64 = load volatile i64* @var_64bit
+  %val64 = load volatile i64, i64* @var_64bit
   %val16_trunc64 = trunc i64 %val64 to i16
   store volatile i16 %val16_trunc64, i16* @var_16bit
 ; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
@@ -121,28 +121,28 @@ define void @ldst_32bit() {
 ; CHECK-LABEL: ldst_32bit:
 
 ; Straight 32-bit load/store
-  %val32_noext = load volatile i32* @var_32bit
+  %val32_noext = load volatile i32, i32* @var_32bit
   store volatile i32 %val32_noext, i32* @var_32bit
 ; CHECK: adrp {{x[0-9]+}}, var_32bit
 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
 
 ; Zero-extension to 64-bits
-  %val32_zext = load volatile i32* @var_32bit
+  %val32_zext = load volatile i32, i32* @var_32bit
   %val64_unsigned = zext i32 %val32_zext to i64
   store volatile i64 %val64_unsigned, i64* @var_64bit
 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
 
 ; Sign-extension to 64-bits
-  %val32_sext = load volatile i32* @var_32bit
+  %val32_sext = load volatile i32, i32* @var_32bit
   %val64_signed = sext i32 %val32_sext to i64
   store volatile i64 %val64_signed, i64* @var_64bit
 ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
 
 ; Truncation from 64-bits
-  %val64_trunc = load volatile i64* @var_64bit
+  %val64_trunc = load volatile i64, i64* @var_64bit
   %val32_trunc = trunc i64 %val64_trunc to i32
   store volatile i32 %val32_trunc, i32* @var_32bit
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
@@ -163,62 +163,62 @@ define void @ldst_32bit() {
 
 define void @ldst_complex_offsets() {
 ; CHECK: ldst_complex_offsets
-  %arr8_addr = load volatile i8** @arr8
+  %arr8_addr = load volatile i8*, i8** @arr8
 ; CHECK: adrp {{x[0-9]+}}, arr8
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr8]
 
-  %arr8_sub1_addr = getelementptr i8* %arr8_addr, i64 1
-  %arr8_sub1 = load volatile i8* %arr8_sub1_addr
+  %arr8_sub1_addr = getelementptr i8, i8* %arr8_addr, i64 1
+  %arr8_sub1 = load volatile i8, i8* %arr8_sub1_addr
   store volatile i8 %arr8_sub1, i8* @var_8bit
 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #1]
 
-  %arr8_sub4095_addr = getelementptr i8* %arr8_addr, i64 4095
-  %arr8_sub4095 = load volatile i8* %arr8_sub4095_addr
+  %arr8_sub4095_addr = getelementptr i8, i8* %arr8_addr, i64 4095
+  %arr8_sub4095 = load volatile i8, i8* %arr8_sub4095_addr
   store volatile i8 %arr8_sub4095, i8* @var_8bit
 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #4095]
 
 
-  %arr16_addr = load volatile i16** @arr16
+  %arr16_addr = load volatile i16*, i16** @arr16
 ; CHECK: adrp {{x[0-9]+}}, arr16
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr16]
 
-  %arr16_sub1_addr = getelementptr i16* %arr16_addr, i64 1
-  %arr16_sub1 = load volatile i16* %arr16_sub1_addr
+  %arr16_sub1_addr = getelementptr i16, i16* %arr16_addr, i64 1
+  %arr16_sub1 = load volatile i16, i16* %arr16_sub1_addr
   store volatile i16 %arr16_sub1, i16* @var_16bit
 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #2]
 
-  %arr16_sub4095_addr = getelementptr i16* %arr16_addr, i64 4095
-  %arr16_sub4095 = load volatile i16* %arr16_sub4095_addr
+  %arr16_sub4095_addr = getelementptr i16, i16* %arr16_addr, i64 4095
+  %arr16_sub4095 = load volatile i16, i16* %arr16_sub4095_addr
   store volatile i16 %arr16_sub4095, i16* @var_16bit
 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #8190]
 
 
-  %arr32_addr = load volatile i32** @arr32
+  %arr32_addr = load volatile i32*, i32** @arr32
 ; CHECK: adrp {{x[0-9]+}}, arr32
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr32]
 
-  %arr32_sub1_addr = getelementptr i32* %arr32_addr, i64 1
-  %arr32_sub1 = load volatile i32* %arr32_sub1_addr
+  %arr32_sub1_addr = getelementptr i32, i32* %arr32_addr, i64 1
+  %arr32_sub1 = load volatile i32, i32* %arr32_sub1_addr
   store volatile i32 %arr32_sub1, i32* @var_32bit
 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #4]
 
-  %arr32_sub4095_addr = getelementptr i32* %arr32_addr, i64 4095
-  %arr32_sub4095 = load volatile i32* %arr32_sub4095_addr
+  %arr32_sub4095_addr = getelementptr i32, i32* %arr32_addr, i64 4095
+  %arr32_sub4095 = load volatile i32, i32* %arr32_sub4095_addr
   store volatile i32 %arr32_sub4095, i32* @var_32bit
 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #16380]
 
 
-  %arr64_addr = load volatile i64** @arr64
+  %arr64_addr = load volatile i64*, i64** @arr64
 ; CHECK: adrp {{x[0-9]+}}, arr64
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr64]
 
-  %arr64_sub1_addr = getelementptr i64* %arr64_addr, i64 1
-  %arr64_sub1 = load volatile i64* %arr64_sub1_addr
+  %arr64_sub1_addr = getelementptr i64, i64* %arr64_addr, i64 1
+  %arr64_sub1 = load volatile i64, i64* %arr64_sub1_addr
   store volatile i64 %arr64_sub1, i64* @var_64bit
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #8]
 
-  %arr64_sub4095_addr = getelementptr i64* %arr64_addr, i64 4095
-  %arr64_sub4095 = load volatile i64* %arr64_sub4095_addr
+  %arr64_sub4095_addr = getelementptr i64, i64* %arr64_addr, i64 4095
+  %arr64_sub4095 = load volatile i64, i64* %arr64_sub4095_addr
   store volatile i64 %arr64_sub4095, i64* @var_64bit
 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #32760]
 
@@ -228,7 +228,7 @@ define void @ldst_complex_offsets() {
 define void @ldst_float() {
 ; CHECK-LABEL: ldst_float:
 
-   %valfp = load volatile float* @var_float
+   %valfp = load volatile float, float* @var_float
 ; CHECK: adrp {{x[0-9]+}}, var_float
 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_float]
 ; CHECK-NOFP-NOT: ldr {{s[0-9]+}},
@@ -243,7 +243,7 @@ define void @ldst_float() {
 define void @ldst_double() {
 ; CHECK-LABEL: ldst_double:
 
-   %valfp = load volatile double* @var_double
+   %valfp = load volatile double, double* @var_double
 ; CHECK: adrp {{x[0-9]+}}, var_double
 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_double]
 ; CHECK-NOFP-NOT: ldr {{d[0-9]+}},
diff --git a/test/CodeGen/AArch64/lit.local.cfg b/test/CodeGen/AArch64/lit.local.cfg
index 125995cebf11..f4626c7e0a43 100644
--- a/test/CodeGen/AArch64/lit.local.cfg
+++ b/test/CodeGen/AArch64/lit.local.cfg
@@ -6,5 +6,5 @@ if not 'AArch64' in config.root.targets:
     config.unsupported = True
 
 # For now we don't test arm64-win32.
-if re.search(r'cygwin|mingw32|win32', config.target_triple):
+if re.search(r'cygwin|mingw32|win32|windows-gnu|windows-msvc', config.target_triple):
     config.unsupported = True
diff --git a/test/CodeGen/AArch64/literal_pools_float.ll b/test/CodeGen/AArch64/literal_pools_float.ll
index e53b8b62c6f3..f5d6a17f3a11 100644
--- a/test/CodeGen/AArch64/literal_pools_float.ll
+++ b/test/CodeGen/AArch64/literal_pools_float.ll
@@ -9,7 +9,7 @@
 define void @floating_lits() {
 ; CHECK-LABEL: floating_lits:
 
-  %floatval = load float* @varfloat
+  %floatval = load float, float* @varfloat
   %newfloat = fadd float %floatval, 128.0
 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]]
 ; CHECK: ldr [[LIT128:s[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
@@ -26,7 +26,7 @@ define void @floating_lits() {
 
   store float %newfloat, float* @varfloat
 
-  %doubleval = load double* @vardouble
+  %doubleval = load double, double* @vardouble
   %newdouble = fadd double %doubleval, 129.0
 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]]
 ; CHECK: ldr [[LIT129:d[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
diff --git a/test/CodeGen/AArch64/local_vars.ll b/test/CodeGen/AArch64/local_vars.ll
index 2f5b9f2adb48..332d660eef36 100644
--- a/test/CodeGen/AArch64/local_vars.ll
+++ b/test/CodeGen/AArch64/local_vars.ll
@@ -49,7 +49,7 @@ define void @stack_local() {
 ; CHECK-LABEL: stack_local:
 ; CHECK: sub sp, sp, #16
 
-  %val = load i64* @var
+  %val = load i64, i64* @var
   store i64 %val, i64* %local_var
 ; CHECK-DAG: str {{x[0-9]+}}, [sp, #{{[0-9]+}}]
 
diff --git a/test/CodeGen/AArch64/logical_shifted_reg.ll b/test/CodeGen/AArch64/logical_shifted_reg.ll
index b249d72e0f90..6b3246d1db8b 100644
--- a/test/CodeGen/AArch64/logical_shifted_reg.ll
+++ b/test/CodeGen/AArch64/logical_shifted_reg.ll
@@ -8,8 +8,8 @@
 
 define void @logical_32bit() minsize {
 ; CHECK-LABEL: logical_32bit:
-  %val1 = load i32* @var1_32
-  %val2 = load i32* @var2_32
+  %val1 = load i32, i32* @var1_32
+  %val2 = load i32, i32* @var2_32
 
   ; First check basic and/bic/or/orn/eor/eon patterns with no shift
   %neg_val2 = xor i32 -1, %val2
@@ -98,8 +98,8 @@ define void @logical_32bit() minsize {
 
 define void @logical_64bit() minsize {
 ; CHECK-LABEL: logical_64bit:
-  %val1 = load i64* @var1_64
-  %val2 = load i64* @var2_64
+  %val1 = load i64, i64* @var1_64
+  %val2 = load i64, i64* @var2_64
 
   ; First check basic and/bic/or/orn/eor/eon patterns with no shift
   %neg_val2 = xor i64 -1, %val2
@@ -191,8 +191,8 @@ define void @logical_64bit() minsize {
 
 define void @flag_setting() {
 ; CHECK-LABEL: flag_setting:
-  %val1 = load i64* @var1_64
-  %val2 = load i64* @var2_64
+  %val1 = load i64, i64* @var1_64
+  %val2 = load i64, i64* @var2_64
 
 ; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}}
 ; CHECK: b.gt .L
diff --git a/test/CodeGen/AArch64/machine-copy-prop.ll b/test/CodeGen/AArch64/machine-copy-prop.ll
index 92d877d40f59..6bacf852907e 100644
--- a/test/CodeGen/AArch64/machine-copy-prop.ll
+++ b/test/CodeGen/AArch64/machine-copy-prop.ll
@@ -47,7 +47,7 @@ if.end:                                           ; preds = %if.then, %entry
   %vld2_lane1.1.extract = extractvalue { <1 x i64>, <1 x i64> } %vld2_lane1, 1
   %t3 = bitcast <2 x i64>* %val1 to i8*
   call void @llvm.aarch64.neon.st2.v1i64.p0i8(<1 x i64> %vld2_lane1.0.extract, <1 x i64> %vld2_lane1.1.extract, i8* %t3)
-  %t4 = load <2 x i64>* %val1, align 16
+  %t4 = load <2 x i64>, <2 x i64>* %val1, align 16
   %vsubhn = sub <2 x i64> <i64 11, i64 0>, %t4
   %vsubhn1 = lshr <2 x i64> %vsubhn, <i64 32, i64 32>
   %vsubhn2 = trunc <2 x i64> %vsubhn1 to <2 x i32>
diff --git a/test/CodeGen/AArch64/machine-sink-kill-flags.ll b/test/CodeGen/AArch64/machine-sink-kill-flags.ll
new file mode 100644
index 000000000000..590e1692ef8b
--- /dev/null
+++ b/test/CodeGen/AArch64/machine-sink-kill-flags.ll
@@ -0,0 +1,29 @@
+; RUN: llc %s -o - -fast-isel=true -O1 -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-apple-ios8.0.0"
+
+; The machine verifier was asserting on this test because the AND instruction was
+; sunk below the test which killed %tmp340.
+; The kill flags on the test had to be cleared because the AND was going to read
+; registers in a BB after the test instruction.
+
+; CHECK: %bb343
+; CHECK: and
+
+define i32 @test(i32* %ptr) {
+bb:
+  br label %.thread
+
+.thread:                                          ; preds = %.thread, %bb
+  %loc = phi i32 [ %next_iter, %.thread ], [ 0, %bb ]
+  %next_iter = lshr i32 %loc, 1
+  %tmp340 = sub i32 %loc, 1
+  %tmp341 = and i32 %tmp340, 1
+  %tmp342 = icmp eq i32 %tmp341, 0
+  br i1 %tmp342, label %bb343, label %.thread
+
+bb343:                                            ; preds = %.thread
+  store i32 %tmp341, i32* %ptr, align 4
+  ret i32 -1
+}
diff --git a/test/CodeGen/AArch64/machine_cse.ll b/test/CodeGen/AArch64/machine_cse.ll
index bc9ab1078759..032199e62181 100644
--- a/test/CodeGen/AArch64/machine_cse.ll
+++ b/test/CodeGen/AArch64/machine_cse.ll
@@ -14,11 +14,11 @@ define void @combine-sign-comparisons-by-cse(i32 *%arg) {
 ; CHECK: b.le
 
 entry:
-  %a = load i32* @a, align 4
-  %b = load i32* @b, align 4
-  %c = load i32* @c, align 4
-  %d = load i32* @d, align 4
-  %e = load i32* @e, align 4
+  %a = load i32, i32* @a, align 4
+  %b = load i32, i32* @b, align 4
+  %c = load i32, i32* @c, align 4
+  %d = load i32, i32* @d, align 4
+  %e = load i32, i32* @e, align 4
 
   %cmp = icmp slt i32 %a, %e
   br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
diff --git a/test/CodeGen/AArch64/merge-store.ll b/test/CodeGen/AArch64/merge-store.ll
new file mode 100644
index 000000000000..18dbad4ce25b
--- /dev/null
+++ b/test/CodeGen/AArch64/merge-store.ll
@@ -0,0 +1,20 @@
+; RUN: llc -march aarch64 %s -o - | FileCheck %s
+
+@g0 = external global <3 x float>, align 16
+@g1 = external global <3 x float>, align 4
+
+; CHECK: ldr s[[R0:[0-9]+]], {{\[}}[[R1:x[0-9]+]]{{\]}}, #4
+; CHECK: ld1{{\.?s?}} { v[[R0]]{{\.?s?}} }[1], {{\[}}[[R1]]{{\]}}
+; CHECK: str d[[R0]]
+
+define void @blam() {
+  %tmp4 = getelementptr inbounds <3 x float>, <3 x float>* @g1, i64 0, i64 0
+  %tmp5 = load <3 x float>, <3 x float>* @g0, align 16
+  %tmp6 = extractelement <3 x float> %tmp5, i64 0
+  store float %tmp6, float* %tmp4
+  %tmp7 = getelementptr inbounds float, float* %tmp4, i64 1
+  %tmp8 = load <3 x float>, <3 x float>* @g0, align 16
+  %tmp9 = extractelement <3 x float> %tmp8, i64 1
+  store float %tmp9, float* %tmp7
+  ret void;
+}
diff --git a/test/CodeGen/AArch64/minmax.ll b/test/CodeGen/AArch64/minmax.ll
new file mode 100644
index 000000000000..a6b5adebe107
--- /dev/null
+++ b/test/CodeGen/AArch64/minmax.ll
@@ -0,0 +1,96 @@
+; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
+
+; CHECK-LABEL: t1
+; CHECK: smax
+define <4 x i32> @t1(<4 x i32> %a, <4 x i32> %b) {
+  %t1 = icmp sgt <4 x i32> %a, %b
+  %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
+  ret <4 x i32> %t2
+}
+
+; CHECK-LABEL: t2
+; CHECK: smin
+define <4 x i32> @t2(<4 x i32> %a, <4 x i32> %b) {
+  %t1 = icmp slt <4 x i32> %a, %b
+  %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
+  ret <4 x i32> %t2
+}
+
+; CHECK-LABEL: t3
+; CHECK: umax
+define <4 x i32> @t3(<4 x i32> %a, <4 x i32> %b) {
+  %t1 = icmp ugt <4 x i32> %a, %b
+  %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
+  ret <4 x i32> %t2
+}
+
+; CHECK-LABEL: t4
+; CHECK: umin
+define <8 x i8> @t4(<8 x i8> %a, <8 x i8> %b) {
+  %t1 = icmp ult <8 x i8> %a, %b
+  %t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b
+  ret <8 x i8> %t2
+}
+
+; CHECK-LABEL: t5
+; CHECK: smin
+define <4 x i16> @t5(<4 x i16> %a, <4 x i16> %b) {
+  %t1 = icmp sgt <4 x i16> %b, %a
+  %t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b
+  ret <4 x i16> %t2
+}
+
+; CHECK-LABEL: t6
+; CHECK: smax
+define <2 x i32> @t6(<2 x i32> %a, <2 x i32> %b) {
+  %t1 = icmp slt <2 x i32> %b, %a
+  %t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b
+  ret <2 x i32> %t2
+}
+
+; CHECK-LABEL: t7
+; CHECK: umin
+define <16 x i8> @t7(<16 x i8> %a, <16 x i8> %b) {
+  %t1 = icmp ugt <16 x i8> %b, %a
+  %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b
+  ret <16 x i8> %t2
+}
+
+; CHECK-LABEL: t8
+; CHECK: umax
+define <8 x i16> @t8(<8 x i16> %a, <8 x i16> %b) {
+  %t1 = icmp ult <8 x i16> %b, %a
+  %t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b
+  ret <8 x i16> %t2
+}
+
+; CHECK-LABEL: t9
+; CHECK: umin
+; CHECK: smax
+define <4 x i32> @t9(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
+  %t1 = icmp ugt <4 x i32> %b, %a
+  %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
+  %t3 = icmp sge <4 x i32> %t2, %c
+  %t4 = select <4 x i1> %t3, <4 x i32> %t2, <4 x i32> %c
+  ret <4 x i32> %t4
+}
+
+; CHECK-LABEL: t10
+; CHECK: smax
+; CHECK: smax
+define <8 x i32> @t10(<8 x i32> %a, <8 x i32> %b) {
+  %t1 = icmp sgt <8 x i32> %a, %b
+  %t2 = select <8 x i1> %t1, <8 x i32> %a, <8 x i32> %b
+  ret <8 x i32> %t2
+}
+
+; CHECK-LABEL: t11
+; CHECK: smin
+; CHECK: smin
+; CHECK: smin
+; CHECK: smin
+define <16 x i32> @t11(<16 x i32> %a, <16 x i32> %b) {
+  %t1 = icmp sle <16 x i32> %a, %b
+  %t2 = select <16 x i1> %t1, <16 x i32> %a, <16 x i32> %b
+  ret <16 x i32> %t2
+}
diff --git a/test/CodeGen/AArch64/mul_pow2.ll b/test/CodeGen/AArch64/mul_pow2.ll
index efc0ec8c40e3..b828223ef1c9 100644
--- a/test/CodeGen/AArch64/mul_pow2.ll
+++ b/test/CodeGen/AArch64/mul_pow2.ll
@@ -74,8 +74,7 @@ define i32 @ntest2(i32 %x) {
 
 define i32 @ntest3(i32 %x) {
 ; CHECK-LABEL: ntest3
-; CHECK: add {{w[0-9]+}}, w0, w0, lsl #1
-; CHECK: neg w0, {{w[0-9]+}}
+; CHECK: sub w0, w0, w0, lsl #2
 
   %mul = mul nsw i32 %x, -3
   ret i32 %mul
diff --git a/test/CodeGen/AArch64/neon-fpround_f128.ll b/test/CodeGen/AArch64/neon-fpround_f128.ll
index a93f3f2723c3..265664ee9442 100644
--- a/test/CodeGen/AArch64/neon-fpround_f128.ll
+++ b/test/CodeGen/AArch64/neon-fpround_f128.ll
@@ -3,7 +3,7 @@
 define <1 x double> @test_fpround_v1f128(<1 x fp128>* %a) {
 ; CHECK-LABEL: test_fpround_v1f128:
 ; CHECK: bl __trunctfdf2
-  %b = load <1 x fp128>* %a
+  %b = load <1 x fp128>, <1 x fp128>* %a
   %c = fptrunc <1 x fp128> %b to <1 x double>
   ret <1 x double> %c
 }
@@ -12,7 +12,7 @@ define <2 x double> @test_fpround_v2f128(<2 x fp128>* %a) {
 ; CHECK-LABEL: test_fpround_v2f128:
 ; CHECK: bl __trunctfdf2
 ; CHECK: bl __trunctfdf2
-  %b = load <2 x fp128>* %a
+  %b = load <2 x fp128>, <2 x fp128>* %a
   %c = fptrunc <2 x fp128> %b to <2 x double>
   ret <2 x double> %c
 }
diff --git a/test/CodeGen/AArch64/neon-scalar-copy.ll b/test/CodeGen/AArch64/neon-scalar-copy.ll
index 6afac315a961..3f770600ac59 100644
--- a/test/CodeGen/AArch64/neon-scalar-copy.ll
+++ b/test/CodeGen/AArch64/neon-scalar-copy.ll
@@ -1,101 +1,145 @@
-; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -asm-verbose=false < %s | FileCheck %s
 
-
-define float @test_dup_sv2S(<2 x float> %v) {
- ; CHECK-LABEL: test_dup_sv2S
- ; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1]
+define float @test_dup_sv2S(<2 x float> %v) #0 {
+ ; CHECK-LABEL: test_dup_sv2S:
+ ; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1]
+ ; CHECK-NEXT: ret
  %tmp1 = extractelement <2 x float> %v, i32 1
  ret float  %tmp1
 }
 
-define float @test_dup_sv2S_0(<2 x float> %v) {
- ; CHECK-LABEL: test_dup_sv2S_0
+define float @test_dup_sv2S_0(<2 x float> %v) #0 {
+ ; CHECK-LABEL: test_dup_sv2S_0:
  ; CHECK-NOT: dup {{[vsd][0-9]+}}
  ; CHECK-NOT: ins {{[vsd][0-9]+}}
- ; CHECK: ret
+ ; CHECK-NEXT: ret
  %tmp1 = extractelement <2 x float> %v, i32 0
  ret float  %tmp1
 }
 
-define float @test_dup_sv4S(<4 x float> %v) {
- ; CHECK-LABEL: test_dup_sv4S
+define float @test_dup_sv4S(<4 x float> %v) #0 {
+ ; CHECK-LABEL: test_dup_sv4S:
+ ; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1]
+ ; CHECK-NEXT: ret
+ %tmp1 = extractelement <4 x float> %v, i32 1
+ ret float  %tmp1
+}
+
+define float @test_dup_sv4S_0(<4 x float> %v) #0 {
+ ; CHECK-LABEL: test_dup_sv4S_0:
  ; CHECK-NOT: dup {{[vsd][0-9]+}}
  ; CHECK-NOT: ins {{[vsd][0-9]+}}
- ; CHECK: ret
+ ; CHECK-NEXT: ret
  %tmp1 = extractelement <4 x float> %v, i32 0
  ret float  %tmp1
 }
 
-define double @test_dup_dvD(<1 x double> %v) {
- ; CHECK-LABEL: test_dup_dvD
+define double @test_dup_dvD(<1 x double> %v) #0 {
+ ; CHECK-LABEL: test_dup_dvD:
  ; CHECK-NOT: dup {{[vsd][0-9]+}}
  ; CHECK-NOT: ins {{[vsd][0-9]+}}
- ; CHECK: ret
+ ; CHECK-NEXT: ret
  %tmp1 = extractelement <1 x double> %v, i32 0
  ret double  %tmp1
 }
 
-define double @test_dup_dv2D(<2 x double> %v) {
- ; CHECK-LABEL: test_dup_dv2D
- ; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1]
+define double @test_dup_dv2D(<2 x double> %v) #0 {
+ ; CHECK-LABEL: test_dup_dv2D:
+ ; CHECK-NEXT: mov d{{[0-9]+}}, {{v[0-9]+}}.d[1]
+ ; CHECK-NEXT: ret
  %tmp1 = extractelement <2 x double> %v, i32 1
  ret double  %tmp1
 }
 
-define double @test_dup_dv2D_0(<2 x double> %v) {
- ; CHECK-LABEL: test_dup_dv2D_0
- ; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1]
- ; CHECK: ret
- %tmp1 = extractelement <2 x double> %v, i32 1
+define double @test_dup_dv2D_0(<2 x double> %v) #0 {
+ ; CHECK-LABEL: test_dup_dv2D_0:
+ ; CHECK-NOT: dup {{[vsd][0-9]+}}
+ ; CHECK-NOT: ins {{[vsd][0-9]+}}
+ ; CHECK-NEXT: ret
+ %tmp1 = extractelement <2 x double> %v, i32 0
  ret double  %tmp1
 }
 
-define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) {
- ; CHECK-LABEL: test_vector_dup_bv16B
+define half @test_dup_hv8H(<8 x half> %v) #0 {
+ ; CHECK-LABEL: test_dup_hv8H:
+ ; CHECK-NEXT: mov h{{[0-9]+}}, {{v[0-9]+}}.h[1]
+ ; CHECK-NEXT: ret
+ %tmp1 = extractelement <8 x half> %v, i32 1
+ ret half  %tmp1
+}
+
+define half @test_dup_hv8H_0(<8 x half> %v) #0 {
+ ; CHECK-LABEL: test_dup_hv8H_0:
+ ; CHECK-NOT: dup {{[vsdh][0-9]+}}
+ ; CHECK-NOT: ins {{[vsdh][0-9]+}}
+ ; CHECK-NEXT: ret
+ %tmp1 = extractelement <8 x half> %v, i32 0
+ ret half  %tmp1
+}
+
+define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) #0 {
+ ; CHECK-LABEL: test_vector_dup_bv16B:
+ ; CHECK-NEXT: umov [[W:w[0-9]+]], v0.b[14]
+ ; CHECK-NEXT: fmov s0, [[W]]
+ ; CHECK-NEXT: ret
  %shuffle.i = shufflevector <16 x i8> %v1, <16 x i8> undef, <1 x i32> <i32 14> 
  ret <1 x i8> %shuffle.i
 }
 
-define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) {
- ; CHECK-LABEL: test_vector_dup_bv8B
+define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) #0 {
+ ; CHECK-LABEL: test_vector_dup_bv8B:
+ ; CHECK-NEXT: dup v0.8b, v0.b[7]
+ ; CHECK-NEXT: ret
  %shuffle.i = shufflevector <8 x i8> %v1, <8 x i8> undef, <1 x i32> <i32 7> 
  ret <1 x i8> %shuffle.i
 }
 
-define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) {
- ; CHECK-LABEL: test_vector_dup_hv8H
+define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) #0 {
+ ; CHECK-LABEL: test_vector_dup_hv8H:
+ ; CHECK-NEXT: umov [[W:w[0-9]+]], v0.h[7]
+ ; CHECK-NEXT: fmov s0, [[W]]
+ ; CHECK-NEXT: ret
  %shuffle.i = shufflevector <8 x i16> %v1, <8 x i16> undef, <1 x i32> <i32 7> 
  ret <1 x i16> %shuffle.i
 }
 
-define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) {
- ; CHECK-LABEL: test_vector_dup_hv4H
+define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) #0 {
+ ; CHECK-LABEL: test_vector_dup_hv4H:
+ ; CHECK-NEXT: dup v0.4h, v0.h[3]
+ ; CHECK-NEXT: ret
  %shuffle.i = shufflevector <4 x i16> %v1, <4 x i16> undef, <1 x i32> <i32 3> 
  ret <1 x i16> %shuffle.i
 }
 
-define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) {
- ; CHECK-LABEL: test_vector_dup_sv4S
+define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) #0 {
+ ; CHECK-LABEL: test_vector_dup_sv4S:
+ ; CHECK-NEXT: mov  [[W:w[0-9]+]], v0.s[3]
+ ; CHECK-NEXT: fmov s0, [[W]]
+ ; CHECK-NEXT: ret
  %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32> <i32 3> 
  ret <1 x i32> %shuffle
 }
 
-define <1 x i32> @test_vector_dup_sv2S(<2 x i32> %v1) {
- ; CHECK-LABEL: test_vector_dup_sv2S
+define <1 x i32> @test_vector_dup_sv2S(<2 x i32> %v1) #0 {
+ ; CHECK-LABEL: test_vector_dup_sv2S:
+ ; CHECK-NEXT: dup v0.2s, v0.s[1]
+ ; CHECK-NEXT: ret
  %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <1 x i32> <i32 1> 
  ret <1 x i32> %shuffle
 }
 
-define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) {
- ; CHECK-LABEL: test_vector_dup_dv2D
- ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #8
+define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) #0 {
+ ; CHECK-LABEL: test_vector_dup_dv2D:
+ ; CHECK-NEXT: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #8
+ ; CHECK-NEXT: ret
  %shuffle.i = shufflevector <2 x i64> %v1, <2 x i64> undef, <1 x i32> <i32 1> 
  ret <1 x i64> %shuffle.i
 }
 
-define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) {
-  ; CHECK-LABEL: test_vector_copy_dup_dv2D
-  ; CHECK: {{dup|mov}} {{d[0-9]+}}, {{v[0-9]+}}.d[1]
+define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) #0 {
+  ; CHECK-LABEL: test_vector_copy_dup_dv2D:
+  ; CHECK-NEXT: {{dup|mov}} {{d[0-9]+}}, {{v[0-9]+}}.d[1]
+  ; CHECK-NEXT: ret
   %vget_lane = extractelement <2 x i64> %c, i32 1
   %vset_lane = insertelement <1 x i64> undef, i64 %vget_lane, i32 0
   ret <1 x i64> %vset_lane
@@ -118,3 +162,5 @@ define void @test_out_of_range_insert(<4 x i32> %vec, i32 %elt) {
   insertelement <4 x i32> %vec, i32 %elt, i32 4
   ret void
 }
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/AArch64/neon-truncStore-extLoad.ll b/test/CodeGen/AArch64/neon-truncStore-extLoad.ll
index 1df3719c8867..0d5ebb324ecb 100644
--- a/test/CodeGen/AArch64/neon-truncStore-extLoad.ll
+++ b/test/CodeGen/AArch64/neon-truncStore-extLoad.ll
@@ -34,7 +34,7 @@ define void @truncStore.v8i16(<8 x i16> %a, <8 x i8>* %result) {
 define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) {
 ; CHECK-LABEL: loadSExt.v4i8:
 ; CHECK: ldrsb
-  %a = load <4 x i8>* %ref
+  %a = load <4 x i8>, <4 x i8>* %ref
   %conv = sext <4 x i8> %a to <4 x i32>
   ret <4 x i32> %conv
 }
@@ -42,7 +42,7 @@ define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) {
 define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) {
 ; CHECK-LABEL: loadZExt.v4i8:
 ; CHECK: ldrb
-  %a = load <4 x i8>* %ref
+  %a = load <4 x i8>, <4 x i8>* %ref
   %conv = zext <4 x i8> %a to <4 x i32>
   ret <4 x i32> %conv
 }
@@ -50,7 +50,7 @@ define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) {
 define i32 @loadExt.i32(<4 x i8>* %ref) {
 ; CHECK-LABEL: loadExt.i32:
 ; CHECK: ldrb
-  %a = load <4 x i8>* %ref
+  %a = load <4 x i8>, <4 x i8>* %ref
   %vecext = extractelement <4 x i8> %a, i32 0
   %conv = zext i8 %vecext to i32
   ret i32 %conv
diff --git a/test/CodeGen/AArch64/nzcv-save.ll b/test/CodeGen/AArch64/nzcv-save.ll
index 32baff3dbe64..f8f42ec9b1a9 100644
--- a/test/CodeGen/AArch64/nzcv-save.ll
+++ b/test/CodeGen/AArch64/nzcv-save.ll
@@ -7,8 +7,8 @@
 ; must be saved for later.
 define void @f(i256* nocapture %a, i256* nocapture %b, i256* nocapture %cc, i256* nocapture %dd) nounwind uwtable noinline ssp {
 entry:
-  %c = load i256* %cc
-  %d = load i256* %dd
+  %c = load i256, i256* %cc
+  %d = load i256, i256* %dd
   %add = add nsw i256 %c, %d
   store i256 %add, i256* %a, align 8
   %or = or i256 %c, 1606938044258990275541962092341162602522202993782792835301376
diff --git a/test/CodeGen/AArch64/or-combine.ll b/test/CodeGen/AArch64/or-combine.ll
new file mode 100644
index 000000000000..c6c343a3f79c
--- /dev/null
+++ b/test/CodeGen/AArch64/or-combine.ll
@@ -0,0 +1,44 @@
+; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
+
+define i32 @test_consts(i32 %in) {
+; CHECK-LABEL: test_consts:
+; CHECK-NOT: bfxil
+; CHECK-NOT: and
+; CHECK-NOT: orr
+; CHECK: ret
+
+  %lo = and i32 %in, 65535
+  %hi = and i32 %in, -65536
+  %res = or i32 %lo, %hi
+  ret i32 %res
+}
+
+define i32 @test_generic(i32 %in, i32 %mask1, i32 %mask2) {
+; CHECK-LABEL: test_generic:
+; CHECK: orr [[FULL_MASK:w[0-9]+]], w1, w2
+; CHECK: and w0, w0, [[FULL_MASK]]
+
+  %lo = and i32 %in, %mask1
+  %hi = and i32 %in, %mask2
+  %res = or i32 %lo, %hi
+  ret i32 %res
+}
+
+; In this case the transformation isn't profitable, since %lo and %hi
+; are used more than once.
+define [3 x i32] @test_reuse(i32 %in, i32 %mask1, i32 %mask2) {
+; CHECK-LABEL: test_reuse:
+; CHECK-DAG: and w1, w0, w1
+; CHECK-DAG: and w2, w0, w2
+; CHECK-DAG: orr w0, w1, w2
+
+  %lo = and i32 %in, %mask1
+  %hi = and i32 %in, %mask2
+  %recombine = or i32 %lo, %hi
+
+  %res.tmp0 = insertvalue [3 x i32] undef, i32 %recombine, 0
+  %res.tmp1 = insertvalue [3 x i32] %res.tmp0, i32 %lo, 1
+  %res = insertvalue [3 x i32] %res.tmp1, i32 %hi, 2
+
+  ret [3 x i32] %res
+}
diff --git a/test/CodeGen/AArch64/paired-load.ll b/test/CodeGen/AArch64/paired-load.ll
index 3dddb9eff325..e6d2d4f51164 100644
--- a/test/CodeGen/AArch64/paired-load.ll
+++ b/test/CodeGen/AArch64/paired-load.ll
@@ -6,10 +6,10 @@ target triple = "aarch64-linux-gnu"
 ; CHECK: ldp
 ; CHECK: stp
 define void @f(i64* %p, i64* %q) {
-  %addr2 = getelementptr i64* %q, i32 1
-  %addr = getelementptr i64* %p, i32 1
-  %x = load i64* %p
-  %y = load i64* %addr
+  %addr2 = getelementptr i64, i64* %q, i32 1
+  %addr = getelementptr i64, i64* %p, i32 1
+  %x = load i64, i64* %p
+  %y = load i64, i64* %addr
   store i64 %x, i64* %q
   store i64 %y, i64* %addr2
   ret void
diff --git a/test/CodeGen/AArch64/pic-eh-stubs.ll b/test/CodeGen/AArch64/pic-eh-stubs.ll
index 93ee0e67b901..f761a87783ce 100644
--- a/test/CodeGen/AArch64/pic-eh-stubs.ll
+++ b/test/CodeGen/AArch64/pic-eh-stubs.ll
@@ -38,7 +38,7 @@ catch:                                            ; preds = %lpad
   %3 = extractvalue { i8*, i32 } %0, 0
   %4 = tail call i8* @__cxa_begin_catch(i8* %3) nounwind
   %5 = bitcast i8* %4 to i32*
-  %exn.scalar = load i32* %5, align 4
+  %exn.scalar = load i32, i32* %5, align 4
   tail call void @__cxa_end_catch() nounwind
   br label %return
 
diff --git a/test/CodeGen/AArch64/print-mrs-system-register.ll b/test/CodeGen/AArch64/print-mrs-system-register.ll
new file mode 100644
index 000000000000..3411ed6161bd
--- /dev/null
+++ b/test/CodeGen/AArch64/print-mrs-system-register.ll
@@ -0,0 +1,11 @@
+; RUN: llc -mtriple=arm64-apple-darwin %s -o - | FileCheck %s
+
+; CHECK: mrs x0, CPM_IOACC_CTL_EL3
+
+define void @foo1() #0 {
+entry:
+  tail call void asm sideeffect "mrs x0, cpm_ioacc_ctl_el3", ""()
+  ret void
+}
+
+attributes #0 = { "target-cpu"="cyclone" }
diff --git a/test/CodeGen/AArch64/ragreedy-csr.ll b/test/CodeGen/AArch64/ragreedy-csr.ll
index 31ff543117ff..94eeba7c7954 100644
--- a/test/CodeGen/AArch64/ragreedy-csr.ll
+++ b/test/CodeGen/AArch64/ragreedy-csr.ll
@@ -35,31 +35,31 @@ declare i32 @__maskrune(i32, i64) #7
 define fastcc i32 @prune_match(%struct.Connector_struct* nocapture readonly %a, %struct.Connector_struct* nocapture readonly %b) #9 {
 entry:
   %label56 = bitcast %struct.Connector_struct* %a to i16*
-  %0 = load i16* %label56, align 2
+  %0 = load i16, i16* %label56, align 2
   %label157 = bitcast %struct.Connector_struct* %b to i16*
-  %1 = load i16* %label157, align 2
+  %1 = load i16, i16* %label157, align 2
   %cmp = icmp eq i16 %0, %1
   br i1 %cmp, label %if.end, label %return, !prof !988
 if.end:
-  %priority = getelementptr inbounds %struct.Connector_struct* %a, i64 0, i32 2
-  %2 = load i8* %priority, align 1
-  %priority5 = getelementptr inbounds %struct.Connector_struct* %b, i64 0, i32 2
-  %3 = load i8* %priority5, align 1
-  %string = getelementptr inbounds %struct.Connector_struct* %a, i64 0, i32 5
-  %4 = load i8** %string, align 8
-  %string7 = getelementptr inbounds %struct.Connector_struct* %b, i64 0, i32 5
-  %5 = load i8** %string7, align 8
+  %priority = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %a, i64 0, i32 2
+  %2 = load i8, i8* %priority, align 1
+  %priority5 = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %b, i64 0, i32 2
+  %3 = load i8, i8* %priority5, align 1
+  %string = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %a, i64 0, i32 5
+  %4 = load i8*, i8** %string, align 8
+  %string7 = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %b, i64 0, i32 5
+  %5 = load i8*, i8** %string7, align 8
   br label %while.cond
 while.cond:
   %lsr.iv27 = phi i64 [ %lsr.iv.next28, %if.end17 ], [ 0, %if.end ]
-  %scevgep55 = getelementptr i8* %4, i64 %lsr.iv27
-  %6 = load i8* %scevgep55, align 1
+  %scevgep55 = getelementptr i8, i8* %4, i64 %lsr.iv27
+  %6 = load i8, i8* %scevgep55, align 1
   %idxprom.i.i = sext i8 %6 to i64
   %isascii.i.i224 = icmp sgt i8 %6, -1
   br i1 %isascii.i.i224, label %cond.true.i.i, label %cond.false.i.i, !prof !181
 cond.true.i.i:
-  %arrayidx.i.i = getelementptr inbounds %struct._RuneLocale* @_DefaultRuneLocale, i64 0, i32 5, i64 %idxprom.i.i
-  %7 = load i32* %arrayidx.i.i, align 4
+  %arrayidx.i.i = getelementptr inbounds %struct._RuneLocale, %struct._RuneLocale* @_DefaultRuneLocale, i64 0, i32 5, i64 %idxprom.i.i
+  %7 = load i32, i32* %arrayidx.i.i, align 4
   %and.i.i = and i32 %7, 32768
   br label %isupper.exit
 cond.false.i.i:
@@ -75,13 +75,13 @@ lor.rhs:
   %sunkaddr = ptrtoint i8* %5 to i64
   %sunkaddr58 = add i64 %sunkaddr, %lsr.iv27
   %sunkaddr59 = inttoptr i64 %sunkaddr58 to i8*
-  %9 = load i8* %sunkaddr59, align 1
+  %9 = load i8, i8* %sunkaddr59, align 1
   %idxprom.i.i214 = sext i8 %9 to i64
   %isascii.i.i213225 = icmp sgt i8 %9, -1
   br i1 %isascii.i.i213225, label %cond.true.i.i217, label %cond.false.i.i219, !prof !181
 cond.true.i.i217:
-  %arrayidx.i.i215 = getelementptr inbounds %struct._RuneLocale* @_DefaultRuneLocale, i64 0, i32 5, i64 %idxprom.i.i214
-  %10 = load i32* %arrayidx.i.i215, align 4
+  %arrayidx.i.i215 = getelementptr inbounds %struct._RuneLocale, %struct._RuneLocale* @_DefaultRuneLocale, i64 0, i32 5, i64 %idxprom.i.i214
+  %10 = load i32, i32* %arrayidx.i.i215, align 4
   %and.i.i216 = and i32 %10, 32768
   br label %isupper.exit223
 cond.false.i.i219:
@@ -97,11 +97,11 @@ while.body:
   %sunkaddr60 = ptrtoint i8* %4 to i64
   %sunkaddr61 = add i64 %sunkaddr60, %lsr.iv27
   %sunkaddr62 = inttoptr i64 %sunkaddr61 to i8*
-  %12 = load i8* %sunkaddr62, align 1
+  %12 = load i8, i8* %sunkaddr62, align 1
   %sunkaddr63 = ptrtoint i8* %5 to i64
   %sunkaddr64 = add i64 %sunkaddr63, %lsr.iv27
   %sunkaddr65 = inttoptr i64 %sunkaddr64 to i8*
-  %13 = load i8* %sunkaddr65, align 1
+  %13 = load i8, i8* %sunkaddr65, align 1
   %cmp14 = icmp eq i8 %12, %13
   br i1 %cmp14, label %if.end17, label %return, !prof !991
 if.end17:
@@ -115,13 +115,13 @@ if.then23:
   %sunkaddr66 = ptrtoint %struct.Connector_struct* %a to i64
   %sunkaddr67 = add i64 %sunkaddr66, 16
   %sunkaddr68 = inttoptr i64 %sunkaddr67 to i8**
-  %16 = load i8** %sunkaddr68, align 8
-  %17 = load i8* %16, align 1
+  %16 = load i8*, i8** %sunkaddr68, align 8
+  %17 = load i8, i8* %16, align 1
   %cmp26 = icmp eq i8 %17, 83
   %sunkaddr69 = ptrtoint i8* %4 to i64
   %sunkaddr70 = add i64 %sunkaddr69, %lsr.iv27
   %sunkaddr71 = inttoptr i64 %sunkaddr70 to i8*
-  %18 = load i8* %sunkaddr71, align 1
+  %18 = load i8, i8* %sunkaddr71, align 1
   br i1 %cmp26, label %land.lhs.true28, label %while.cond59.preheader, !prof !993
 land.lhs.true28:
   switch i8 %18, label %land.rhs.preheader [
@@ -132,24 +132,24 @@ land.lhs.true35:
   %sunkaddr72 = ptrtoint i8* %5 to i64
   %sunkaddr73 = add i64 %sunkaddr72, %lsr.iv27
   %sunkaddr74 = inttoptr i64 %sunkaddr73 to i8*
-  %19 = load i8* %sunkaddr74, align 1
+  %19 = load i8, i8* %sunkaddr74, align 1
   switch i8 %19, label %land.rhs.preheader [
     i8 112, label %land.lhs.true43
   ], !prof !995
 land.lhs.true43:
   %20 = ptrtoint i8* %16 to i64
   %21 = sub i64 0, %20
-  %scevgep52 = getelementptr i8* %4, i64 %21
-  %scevgep53 = getelementptr i8* %scevgep52, i64 %lsr.iv27
-  %scevgep54 = getelementptr i8* %scevgep53, i64 -1
+  %scevgep52 = getelementptr i8, i8* %4, i64 %21
+  %scevgep53 = getelementptr i8, i8* %scevgep52, i64 %lsr.iv27
+  %scevgep54 = getelementptr i8, i8* %scevgep53, i64 -1
   %cmp45 = icmp eq i8* %scevgep54, null
   br i1 %cmp45, label %return, label %lor.lhs.false47, !prof !996
 lor.lhs.false47:
   %22 = ptrtoint i8* %16 to i64
   %23 = sub i64 0, %22
-  %scevgep47 = getelementptr i8* %4, i64 %23
-  %scevgep48 = getelementptr i8* %scevgep47, i64 %lsr.iv27
-  %scevgep49 = getelementptr i8* %scevgep48, i64 -2
+  %scevgep47 = getelementptr i8, i8* %4, i64 %23
+  %scevgep48 = getelementptr i8, i8* %scevgep47, i64 %lsr.iv27
+  %scevgep49 = getelementptr i8, i8* %scevgep48, i64 -2
   %cmp50 = icmp eq i8* %scevgep49, null
   br i1 %cmp50, label %land.lhs.true52, label %while.cond59.preheader, !prof !997
 land.lhs.true52:
@@ -157,7 +157,7 @@ land.lhs.true52:
   %sunkaddr76 = add i64 %sunkaddr75, %lsr.iv27
   %sunkaddr77 = add i64 %sunkaddr76, -1
   %sunkaddr78 = inttoptr i64 %sunkaddr77 to i8*
-  %24 = load i8* %sunkaddr78, align 1
+  %24 = load i8, i8* %sunkaddr78, align 1
   %cmp55 = icmp eq i8 %24, 73
   %cmp61233 = icmp eq i8 %18, 0
   %or.cond265 = or i1 %cmp55, %cmp61233
@@ -166,14 +166,14 @@ while.cond59.preheader:
   %cmp61233.old = icmp eq i8 %18, 0
   br i1 %cmp61233.old, label %return, label %land.rhs.preheader, !prof !999
 land.rhs.preheader:
-  %scevgep33 = getelementptr i8* %5, i64 %lsr.iv27
-  %scevgep43 = getelementptr i8* %4, i64 %lsr.iv27
+  %scevgep33 = getelementptr i8, i8* %5, i64 %lsr.iv27
+  %scevgep43 = getelementptr i8, i8* %4, i64 %lsr.iv27
   br label %land.rhs
 land.rhs:
   %lsr.iv = phi i64 [ 0, %land.rhs.preheader ], [ %lsr.iv.next, %if.then83 ]
   %25 = phi i8 [ %27, %if.then83 ], [ %18, %land.rhs.preheader ]
-  %scevgep34 = getelementptr i8* %scevgep33, i64 %lsr.iv
-  %26 = load i8* %scevgep34, align 1
+  %scevgep34 = getelementptr i8, i8* %scevgep33, i64 %lsr.iv
+  %26 = load i8, i8* %scevgep34, align 1
   %cmp64 = icmp eq i8 %26, 0
   br i1 %cmp64, label %return, label %while.body66, !prof !1000
 while.body66:
@@ -187,9 +187,9 @@ lor.lhs.false74:
   %or.cond208 = or i1 %cmp77, %cmp81
   br i1 %or.cond208, label %return, label %if.then83, !prof !1002
 if.then83:
-  %scevgep44 = getelementptr i8* %scevgep43, i64 %lsr.iv
-  %scevgep45 = getelementptr i8* %scevgep44, i64 1
-  %27 = load i8* %scevgep45, align 1
+  %scevgep44 = getelementptr i8, i8* %scevgep43, i64 %lsr.iv
+  %scevgep45 = getelementptr i8, i8* %scevgep44, i64 1
+  %27 = load i8, i8* %scevgep45, align 1
   %cmp61 = icmp eq i8 %27, 0
   %lsr.iv.next = add i64 %lsr.iv, 1
   br i1 %cmp61, label %return, label %land.rhs, !prof !999
@@ -202,18 +202,18 @@ while.cond95.preheader:
   %sunkaddr79 = ptrtoint i8* %4 to i64
   %sunkaddr80 = add i64 %sunkaddr79, %lsr.iv27
   %sunkaddr81 = inttoptr i64 %sunkaddr80 to i8*
-  %28 = load i8* %sunkaddr81, align 1
+  %28 = load i8, i8* %sunkaddr81, align 1
   %cmp97238 = icmp eq i8 %28, 0
   br i1 %cmp97238, label %return, label %land.rhs99.preheader, !prof !1004
 land.rhs99.preheader:
-  %scevgep31 = getelementptr i8* %5, i64 %lsr.iv27
-  %scevgep40 = getelementptr i8* %4, i64 %lsr.iv27
+  %scevgep31 = getelementptr i8, i8* %5, i64 %lsr.iv27
+  %scevgep40 = getelementptr i8, i8* %4, i64 %lsr.iv27
   br label %land.rhs99
 land.rhs99:
   %lsr.iv17 = phi i64 [ 0, %land.rhs99.preheader ], [ %lsr.iv.next18, %if.then117 ]
   %29 = phi i8 [ %31, %if.then117 ], [ %28, %land.rhs99.preheader ]
-  %scevgep32 = getelementptr i8* %scevgep31, i64 %lsr.iv17
-  %30 = load i8* %scevgep32, align 1
+  %scevgep32 = getelementptr i8, i8* %scevgep31, i64 %lsr.iv17
+  %30 = load i8, i8* %scevgep32, align 1
   %cmp101 = icmp eq i8 %30, 0
   br i1 %cmp101, label %return, label %while.body104, !prof !1005
 while.body104:
@@ -224,9 +224,9 @@ while.body104:
   %or.cond210 = or i1 %or.cond209, %cmp115
   br i1 %or.cond210, label %if.then117, label %return, !prof !1006
 if.then117:
-  %scevgep41 = getelementptr i8* %scevgep40, i64 %lsr.iv17
-  %scevgep42 = getelementptr i8* %scevgep41, i64 1
-  %31 = load i8* %scevgep42, align 1
+  %scevgep41 = getelementptr i8, i8* %scevgep40, i64 %lsr.iv17
+  %scevgep42 = getelementptr i8, i8* %scevgep41, i64 1
+  %31 = load i8, i8* %scevgep42, align 1
   %cmp97 = icmp eq i8 %31, 0
   %lsr.iv.next18 = add i64 %lsr.iv17, 1
   br i1 %cmp97, label %return, label %land.rhs99, !prof !1004
@@ -239,18 +239,18 @@ while.cond130.preheader:
   %sunkaddr82 = ptrtoint i8* %4 to i64
   %sunkaddr83 = add i64 %sunkaddr82, %lsr.iv27
   %sunkaddr84 = inttoptr i64 %sunkaddr83 to i8*
-  %32 = load i8* %sunkaddr84, align 1
+  %32 = load i8, i8* %sunkaddr84, align 1
   %cmp132244 = icmp eq i8 %32, 0
   br i1 %cmp132244, label %return, label %land.rhs134.preheader, !prof !1008
 land.rhs134.preheader:
-  %scevgep29 = getelementptr i8* %5, i64 %lsr.iv27
-  %scevgep37 = getelementptr i8* %4, i64 %lsr.iv27
+  %scevgep29 = getelementptr i8, i8* %5, i64 %lsr.iv27
+  %scevgep37 = getelementptr i8, i8* %4, i64 %lsr.iv27
   br label %land.rhs134
 land.rhs134:
   %lsr.iv22 = phi i64 [ 0, %land.rhs134.preheader ], [ %lsr.iv.next23, %if.then152 ]
   %33 = phi i8 [ %35, %if.then152 ], [ %32, %land.rhs134.preheader ]
-  %scevgep30 = getelementptr i8* %scevgep29, i64 %lsr.iv22
-  %34 = load i8* %scevgep30, align 1
+  %scevgep30 = getelementptr i8, i8* %scevgep29, i64 %lsr.iv22
+  %34 = load i8, i8* %scevgep30, align 1
   %cmp136 = icmp eq i8 %34, 0
   br i1 %cmp136, label %return, label %while.body139, !prof !1009
 while.body139:
@@ -261,9 +261,9 @@ while.body139:
   %or.cond212 = or i1 %or.cond211, %cmp150
   br i1 %or.cond212, label %if.then152, label %return, !prof !1010
 if.then152:
-  %scevgep38 = getelementptr i8* %scevgep37, i64 %lsr.iv22
-  %scevgep39 = getelementptr i8* %scevgep38, i64 1
-  %35 = load i8* %scevgep39, align 1
+  %scevgep38 = getelementptr i8, i8* %scevgep37, i64 %lsr.iv22
+  %scevgep39 = getelementptr i8, i8* %scevgep38, i64 1
+  %35 = load i8, i8* %scevgep39, align 1
   %cmp132 = icmp eq i8 %35, 0
   %lsr.iv.next23 = add i64 %lsr.iv22, 1
   br i1 %cmp132, label %return, label %land.rhs134, !prof !1008
diff --git a/test/CodeGen/AArch64/regress-tail-livereg.ll b/test/CodeGen/AArch64/regress-tail-livereg.ll
index 03c3f33d9477..965aa0d062d5 100644
--- a/test/CodeGen/AArch64/regress-tail-livereg.ll
+++ b/test/CodeGen/AArch64/regress-tail-livereg.ll
@@ -5,7 +5,7 @@ declare void @bar()
 
 define void @foo() {
 ; CHECK-LABEL: foo:
-       %func = load void()** @var
+       %func = load void()*, void()** @var
 
        ; Calling a function encourages @foo to use a callee-saved register,
        ; which makes it a natural choice for the tail call itself. But we don't
diff --git a/test/CodeGen/AArch64/regress-tblgen-chains.ll b/test/CodeGen/AArch64/regress-tblgen-chains.ll
index 477d99625eec..0d301bbd502a 100644
--- a/test/CodeGen/AArch64/regress-tblgen-chains.ll
+++ b/test/CodeGen/AArch64/regress-tblgen-chains.ll
@@ -19,7 +19,7 @@ define i64 @test_chains() {
   call void @bar(i8* %locvar)
 ; CHECK: bl {{_?bar}}
 
-  %inc.1 = load i8* %locvar
+  %inc.1 = load i8, i8* %locvar
   %inc.2 = zext i8 %inc.1 to i64
   %inc.3 = add i64 %inc.2, 1
   %inc.4 = trunc i64 %inc.3 to i8
@@ -30,7 +30,7 @@ define i64 @test_chains() {
 ; CHECK: sturb {{w[0-9]+}}, [x29, [[LOCADDR]]]
 ; CHECK: ldurb {{w[0-9]+}}, [x29, [[LOCADDR]]]
 
-  %ret.1 = load i8* %locvar
+  %ret.1 = load i8, i8* %locvar
   %ret.2 = zext i8 %ret.1 to i64
   ret i64 %ret.2
 ; CHECK: ret
diff --git a/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll b/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
index c3167e4f4bdd..66a5ed6e5277 100644
--- a/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
+++ b/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
@@ -7,15 +7,15 @@ define void @test_w29_reserved() {
 ; CHECK-LABEL: test_w29_reserved:
 ; CHECK: add x29, sp, #{{[0-9]+}}
 
-  %val1 = load volatile i32* @var
-  %val2 = load volatile i32* @var
-  %val3 = load volatile i32* @var
-  %val4 = load volatile i32* @var
-  %val5 = load volatile i32* @var
-  %val6 = load volatile i32* @var
-  %val7 = load volatile i32* @var
-  %val8 = load volatile i32* @var
-  %val9 = load volatile i32* @var
+  %val1 = load volatile i32, i32* @var
+  %val2 = load volatile i32, i32* @var
+  %val3 = load volatile i32, i32* @var
+  %val4 = load volatile i32, i32* @var
+  %val5 = load volatile i32, i32* @var
+  %val6 = load volatile i32, i32* @var
+  %val7 = load volatile i32, i32* @var
+  %val8 = load volatile i32, i32* @var
+  %val9 = load volatile i32, i32* @var
 
 ; CHECK-NOT: ldr w29,
 
diff --git a/test/CodeGen/AArch64/remat-float0.ll b/test/CodeGen/AArch64/remat-float0.ll
new file mode 100644
index 000000000000..29af7818cf38
--- /dev/null
+++ b/test/CodeGen/AArch64/remat-float0.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -verify-machineinstrs | FileCheck %s
+
+; Check that float 0 gets rematerialized with an fmov of zero reg instead
+; of spilled/filled.
+
+declare void @bar(float)
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK: fmov s0, wzr
+; CHECK: bl bar
+; CHECK: fmov s0, wzr
+; CHECK: bl bar
+  call void @bar(float 0.000000e+00)
+  call void asm sideeffect "", "~{s0},~{s1},~{s2},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"()
+  call void @bar(float 0.000000e+00)
+  ret void
+}
diff --git a/test/CodeGen/AArch64/remat.ll b/test/CodeGen/AArch64/remat.ll
index 32b3ed2d9ac4..8b3e6dd5ad92 100644
--- a/test/CodeGen/AArch64/remat.ll
+++ b/test/CodeGen/AArch64/remat.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
diff --git a/test/CodeGen/AArch64/rm_redundant_cmp.ll b/test/CodeGen/AArch64/rm_redundant_cmp.ll
index 36dc118ed1a5..f66af7fd6270 100644
--- a/test/CodeGen/AArch64/rm_redundant_cmp.ll
+++ b/test/CodeGen/AArch64/rm_redundant_cmp.ll
@@ -15,13 +15,13 @@ define void @test_i16_2cmp_signed_1() {
 ; CHECK-NOT: cmp
 ; CHECK: b.ne
 entry:
-  %0 = load i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 1), align 2
-  %1 = load i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 2), align 2
+  %0 = load i16, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 1), align 2
+  %1 = load i16, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 2), align 2
   %cmp = icmp sgt i16 %0, %1
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  store i16 %0, i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2
+  store i16 %0, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2
   br label %if.end8
 
 if.else:                                          ; preds = %entry
@@ -29,7 +29,7 @@ if.else:                                          ; preds = %entry
   br i1 %cmp5, label %if.then7, label %if.end8
 
 if.then7:                                         ; preds = %if.else
-  store i16 %0, i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2
+  store i16 %0, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2
   br label %if.end8
 
 if.end8:                                          ; preds = %if.else, %if.then7, %if.then
@@ -43,13 +43,13 @@ define void @test_i16_2cmp_signed_2() {
 ; CHECK-NOT: cmp
 ; CHECK: b.ge
 entry:
-  %0 = load i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 1), align 2
-  %1 = load i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 2), align 2
+  %0 = load i16, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 1), align 2
+  %1 = load i16, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 2), align 2
   %cmp = icmp sgt i16 %0, %1
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  store i16 %0, i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2
+  store i16 %0, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2
   br label %if.end8
 
 if.else:                                          ; preds = %entry
@@ -57,7 +57,7 @@ if.else:                                          ; preds = %entry
   br i1 %cmp5, label %if.then7, label %if.end8
 
 if.then7:                                         ; preds = %if.else
-  store i16 %1, i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2
+  store i16 %1, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2
   br label %if.end8
 
 if.end8:                                          ; preds = %if.else, %if.then7, %if.then
@@ -71,13 +71,13 @@ define void @test_i16_2cmp_unsigned_1() {
 ; CHECK-NOT: cmp
 ; CHECK: b.ne
 entry:
-  %0 = load i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 1), align 2
-  %1 = load i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 2), align 2
+  %0 = load i16, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 1), align 2
+  %1 = load i16, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 2), align 2
   %cmp = icmp ugt i16 %0, %1
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  store i16 %0, i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2
+  store i16 %0, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2
   br label %if.end8
 
 if.else:                                          ; preds = %entry
@@ -85,7 +85,7 @@ if.else:                                          ; preds = %entry
   br i1 %cmp5, label %if.then7, label %if.end8
 
 if.then7:                                         ; preds = %if.else
-  store i16 %0, i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2
+  store i16 %0, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2
   br label %if.end8
 
 if.end8:                                          ; preds = %if.else, %if.then7, %if.then
@@ -99,13 +99,13 @@ define void @test_i16_2cmp_unsigned_2() {
 ; CHECK-NOT: cmp
 ; CHECK: b.hs
 entry:
-  %0 = load i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 1), align 2
-  %1 = load i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 2), align 2
+  %0 = load i16, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 1), align 2
+  %1 = load i16, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 2), align 2
   %cmp = icmp ugt i16 %0, %1
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  store i16 %0, i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2
+  store i16 %0, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2
   br label %if.end8
 
 if.else:                                          ; preds = %entry
@@ -113,7 +113,7 @@ if.else:                                          ; preds = %entry
   br i1 %cmp5, label %if.then7, label %if.end8
 
 if.then7:                                         ; preds = %if.else
-  store i16 %1, i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2
+  store i16 %1, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2
   br label %if.end8
 
 if.end8:                                          ; preds = %if.else, %if.then7, %if.then
@@ -136,13 +136,13 @@ define void @test_i8_2cmp_signed_1() {
 ; CHECK-NOT: cmp
 ; CHECK: b.ne
 entry:
-  %0 = load i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 1), align 2
-  %1 = load i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 2), align 2
+  %0 = load i8, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 1), align 2
+  %1 = load i8, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 2), align 2
   %cmp = icmp sgt i8 %0, %1
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  store i8 %0, i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2
+  store i8 %0, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2
   br label %if.end8
 
 if.else:                                          ; preds = %entry
@@ -150,7 +150,7 @@ if.else:                                          ; preds = %entry
   br i1 %cmp5, label %if.then7, label %if.end8
 
 if.then7:                                         ; preds = %if.else
-  store i8 %0, i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2
+  store i8 %0, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2
   br label %if.end8
 
 if.end8:                                          ; preds = %if.else, %if.then7, %if.then
@@ -164,13 +164,13 @@ define void @test_i8_2cmp_signed_2() {
 ; CHECK-NOT: cmp
 ; CHECK: b.ge
 entry:
-  %0 = load i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 1), align 2
-  %1 = load i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 2), align 2
+  %0 = load i8, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 1), align 2
+  %1 = load i8, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 2), align 2
   %cmp = icmp sgt i8 %0, %1
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  store i8 %0, i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2
+  store i8 %0, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2
   br label %if.end8
 
 if.else:                                          ; preds = %entry
@@ -178,7 +178,7 @@ if.else:                                          ; preds = %entry
   br i1 %cmp5, label %if.then7, label %if.end8
 
 if.then7:                                         ; preds = %if.else
-  store i8 %1, i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2
+  store i8 %1, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2
   br label %if.end8
 
 if.end8:                                          ; preds = %if.else, %if.then7, %if.then
@@ -192,13 +192,13 @@ define void @test_i8_2cmp_unsigned_1() {
 ; CHECK-NOT: cmp
 ; CHECK: b.ne
 entry:
-  %0 = load i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 1), align 2
-  %1 = load i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 2), align 2
+  %0 = load i8, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 1), align 2
+  %1 = load i8, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 2), align 2
   %cmp = icmp ugt i8 %0, %1
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  store i8 %0, i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2
+  store i8 %0, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2
   br label %if.end8
 
 if.else:                                          ; preds = %entry
@@ -206,7 +206,7 @@ if.else:                                          ; preds = %entry
   br i1 %cmp5, label %if.then7, label %if.end8
 
 if.then7:                                         ; preds = %if.else
-  store i8 %0, i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2
+  store i8 %0, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2
   br label %if.end8
 
 if.end8:                                          ; preds = %if.else, %if.then7, %if.then
@@ -220,13 +220,13 @@ define void @test_i8_2cmp_unsigned_2() {
 ; CHECK-NOT: cmp
 ; CHECK: b.hs
 entry:
-  %0 = load i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 1), align 2
-  %1 = load i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 2), align 2
+  %0 = load i8, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 1), align 2
+  %1 = load i8, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 2), align 2
   %cmp = icmp ugt i8 %0, %1
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  store i8 %0, i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2
+  store i8 %0, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2
   br label %if.end8
 
 if.else:                                          ; preds = %entry
@@ -234,7 +234,7 @@ if.else:                                          ; preds = %entry
   br i1 %cmp5, label %if.then7, label %if.end8
 
 if.then7:                                         ; preds = %if.else
-  store i8 %1, i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2
+  store i8 %1, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2
   br label %if.end8
 
 if.end8:                                          ; preds = %if.else, %if.then7, %if.then
diff --git a/test/CodeGen/AArch64/sibling-call.ll b/test/CodeGen/AArch64/sibling-call.ll
index 34e3bb410e8c..a68fdec4cfbc 100644
--- a/test/CodeGen/AArch64/sibling-call.ll
+++ b/test/CodeGen/AArch64/sibling-call.ll
@@ -75,8 +75,8 @@ define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
 
 ; CHECK: ldr [[VAL0:x[0-9]+]],
 ; CHECK: ldr [[VAL1:x[0-9]+]],
-; CHECK: str [[VAL1]],
 ; CHECK: str [[VAL0]],
+; CHECK: str [[VAL1]],
 
 ; CHECK-NOT: add sp, sp,
 ; CHECK: b callee_stack16
@@ -88,7 +88,7 @@ define void @indirect_tail() {
 ; CHECK-LABEL: indirect_tail:
 ; CHECK-NOT: sub sp, sp
 
-  %fptr = load void(i32)** @func
+  %fptr = load void(i32)*, void(i32)** @func
   tail call void %fptr(i32 42)
   ret void
 ; CHECK: ldr [[FPTR:x[1-9]+]], [{{x[0-9]+}}, {{#?}}:lo12:func]
diff --git a/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll b/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll
index bedbf5facbb7..eb4937e75f61 100644
--- a/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll
+++ b/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll
@@ -15,7 +15,7 @@
 define i32 @test_stack_guard_remat2() {
 entry:
   %StackGuardSlot = alloca i8*
-  %StackGuard = load i8** bitcast (i64** @__stack_chk_guard to i8**)
+  %StackGuard = load i8*, i8** bitcast (i64** @__stack_chk_guard to i8**)
   call void @llvm.stackprotector(i8* %StackGuard, i8** %StackGuardSlot)
   %container = alloca [32 x i8], align 1
   call void @llvm.stackprotectorcheck(i8** bitcast (i64** @__stack_chk_guard to i8**))
diff --git a/test/CodeGen/AArch64/stack_guard_remat.ll b/test/CodeGen/AArch64/stack_guard_remat.ll
index cee7266abdcc..d6bae62e5edc 100644
--- a/test/CodeGen/AArch64/stack_guard_remat.ll
+++ b/test/CodeGen/AArch64/stack_guard_remat.ll
@@ -30,7 +30,7 @@ entry:
   %a1 = alloca [256 x i32], align 4
   %0 = bitcast [256 x i32]* %a1 to i8*
   call void @llvm.lifetime.start(i64 1024, i8* %0)
-  %arraydecay = getelementptr inbounds [256 x i32]* %a1, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [256 x i32], [256 x i32]* %a1, i64 0, i64 0
   call void @foo3(i32* %arraydecay)
   call void asm sideeffect "foo2", "~{w0},~{w1},~{w2},~{w3},~{w4},~{w5},~{w6},~{w7},~{w8},~{w9},~{w10},~{w11},~{w12},~{w13},~{w14},~{w15},~{w16},~{w17},~{w18},~{w19},~{w20},~{w21},~{w22},~{w23},~{w24},~{w25},~{w26},~{w27},~{w28},~{w29},~{w30}"()
   call void @llvm.lifetime.end(i64 1024, i8* %0)
diff --git a/test/CodeGen/AArch64/stackmap-liveness.ll b/test/CodeGen/AArch64/stackmap-liveness.ll
new file mode 100644
index 000000000000..6b37aac16f9e
--- /dev/null
+++ b/test/CodeGen/AArch64/stackmap-liveness.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s -mtriple=aarch64-apple-darwin | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+; CHECK-LABEL:  .section  __LLVM_STACKMAPS,__llvm_stackmaps
+; CHECK-NEXT:   __LLVM_StackMaps:
+; Header
+; CHECK-NEXT:   .byte 1
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 0
+; Num Functions
+; CHECK-NEXT:   .long 1
+; Num LargeConstants
+; CHECK-NEXT:   .long   0
+; Num Callsites
+; CHECK-NEXT:   .long   1
+
+; Functions and stack size
+; CHECK-NEXT:   .quad _stackmap_liveness
+; CHECK-NEXT:   .quad 16
+
+; Test that the return register is recognized as an live-out.
+define i64 @stackmap_liveness(i1 %c) {
+; CHECK-LABEL:  .long L{{.*}}-_stackmap_liveness
+; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .short  0
+; Padding
+; CHECK-NEXT:   .short  0
+; Num LiveOut Entries: 1
+; CHECK-NEXT:   .short  2
+; LiveOut Entry 0: X0
+; CHECK-NEXT:   .short 0
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .byte 8
+; LiveOut Entry 1: SP
+; CHECK-NEXT:   .short 31
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .byte 8
+; Align
+; CHECK-NEXT:   .align  3
+  %1 = select i1 %c, i64 1, i64 2
+  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 32, i8* null, i32 0)
+  ret i64 %1
+}
+
+declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
+
diff --git a/test/CodeGen/AArch64/tail-call.ll b/test/CodeGen/AArch64/tail-call.ll
index 7fb39545a32e..e5766154bb46 100644
--- a/test/CodeGen/AArch64/tail-call.ll
+++ b/test/CodeGen/AArch64/tail-call.ll
@@ -103,3 +103,41 @@ define fastcc void @caller_weak() {
   tail call void @callee_weak()
   ret void
 }
+
+declare { [2 x float] } @get_vec2()
+
+define { [3 x float] } @test_add_elem() {
+; CHECK-LABEL: test_add_elem:
+; CHECK: bl get_vec2
+; CHECK: fmov s2, #1.0
+; CHECK: ret
+
+  %call = tail call { [2 x float] } @get_vec2()
+  %arr = extractvalue { [2 x float] } %call, 0
+  %arr.0 = extractvalue [2 x float] %arr, 0
+  %arr.1 = extractvalue [2 x float] %arr, 1
+
+  %res.0 = insertvalue { [3 x float] } undef, float %arr.0, 0, 0
+  %res.01 = insertvalue { [3 x float] } %res.0, float %arr.1, 0, 1
+  %res.012 = insertvalue { [3 x float] } %res.01, float 1.000000e+00, 0, 2
+  ret { [3 x float] } %res.012
+}
+
+declare double @get_double()
+define { double, [2 x double] } @test_mismatched_insert() {
+; CHECK-LABEL: test_mismatched_insert:
+; CHECK: bl get_double
+; CHECK: bl get_double
+; CHECK: bl get_double
+; CHECK: ret
+
+  %val0 = call double @get_double()
+  %val1 = call double @get_double()
+  %val2 = tail call double @get_double()
+
+  %res.0 = insertvalue { double, [2 x double] } undef, double %val0, 0
+  %res.01 = insertvalue { double, [2 x double] } %res.0, double %val1, 1, 0
+  %res.012 = insertvalue { double, [2 x double] } %res.01, double %val2, 1, 1
+
+  ret { double, [2 x double] } %res.012
+}
diff --git a/test/CodeGen/AArch64/tailcall-explicit-sret.ll b/test/CodeGen/AArch64/tailcall-explicit-sret.ll
index f4ad65584095..4d80f2ac5c12 100644
--- a/test/CodeGen/AArch64/tailcall-explicit-sret.ll
+++ b/test/CodeGen/AArch64/tailcall-explicit-sret.ll
@@ -42,7 +42,7 @@ define void @test_tailcall_explicit_sret_alloca_unused() #0 {
 ; CHECK: ret
 define void @test_tailcall_explicit_sret_alloca_dummyusers(i1024* %ptr) #0 {
   %l = alloca i1024, align 8
-  %r = load i1024* %ptr, align 8
+  %r = load i1024, i1024* %ptr, align 8
   store i1024 %r, i1024* %l, align 8
   tail call void @test_explicit_sret(i1024* %l)
   ret void
@@ -55,7 +55,7 @@ define void @test_tailcall_explicit_sret_alloca_dummyusers(i1024* %ptr) #0 {
 ; CHECK-NEXT: bl _test_explicit_sret
 ; CHECK: ret
 define void @test_tailcall_explicit_sret_gep(i1024* %ptr) #0 {
-  %ptr2 = getelementptr i1024* %ptr, i32 1
+  %ptr2 = getelementptr i1024, i1024* %ptr, i32 1
   tail call void @test_explicit_sret(i1024* %ptr2)
   ret void
 }
@@ -70,7 +70,7 @@ define void @test_tailcall_explicit_sret_gep(i1024* %ptr) #0 {
 define i1024 @test_tailcall_explicit_sret_alloca_returned() #0 {
   %l = alloca i1024, align 8
   tail call void @test_explicit_sret(i1024* %l)
-  %r = load i1024* %l, align 8
+  %r = load i1024, i1024* %l, align 8
   ret i1024 %r
 }
 
@@ -85,7 +85,7 @@ define i1024 @test_tailcall_explicit_sret_alloca_returned() #0 {
 define void @test_indirect_tailcall_explicit_sret_nosret_arg(i1024* sret %arg, void (i1024*)* %f) #0 {
   %l = alloca i1024, align 8
   tail call void %f(i1024* %l)
-  %r = load i1024* %l, align 8
+  %r = load i1024, i1024* %l, align 8
   store i1024 %r, i1024* %arg, align 8
   ret void
 }
diff --git a/test/CodeGen/AArch64/tailcall-mem-intrinsics.ll b/test/CodeGen/AArch64/tailcall-mem-intrinsics.ll
new file mode 100644
index 000000000000..b970fb124151
--- /dev/null
+++ b/test/CodeGen/AArch64/tailcall-mem-intrinsics.ll
@@ -0,0 +1,31 @@
+; RUN: llc -mtriple=aarch64-unknown-unknown < %s | FileCheck %s
+
+; CHECK-LABEL: tail_memcpy:
+; CHECK: b memcpy
+define void @tail_memcpy(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 {
+entry:
+  tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: tail_memmove:
+; CHECK: b memmove
+define void @tail_memmove(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 {
+entry:
+  tail call void @llvm.memmove.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: tail_memset:
+; CHECK: b memset
+define void @tail_memset(i8* nocapture %p, i8 %c, i32 %n) #0 {
+entry:
+  tail call void @llvm.memset.p0i8.i32(i8* %p, i8 %c, i32 %n, i32 1, i1 false)
+  ret void
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0
+declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0
+declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) #0
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/AArch64/tailcall_misched_graph.ll b/test/CodeGen/AArch64/tailcall_misched_graph.ll
new file mode 100644
index 000000000000..343ffab57e35
--- /dev/null
+++ b/test/CodeGen/AArch64/tailcall_misched_graph.ll
@@ -0,0 +1,42 @@
+; RUN: llc -mcpu=cyclone -debug-only=misched < %s 2>&1 | FileCheck %s
+
+; REQUIRES: asserts
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-apple-ios7.0.0"
+
+define void @caller2(i8* %a0, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9) {
+entry:
+  tail call void @callee2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a0)
+  ret void
+}
+
+declare void @callee2(i8*, i8*, i8*, i8*, i8*,
+                      i8*, i8*, i8*, i8*, i8*)
+
+; Make sure there is a dependence between the load and store to the same stack
+; location during a tail call. Tail calls clobber the incoming argument area and
+; therefore it is not safe to assume argument locations are invariant.
+; PR23459 has a test case that we where miscompiling because of this at the
+; time.
+
+; CHECK: Frame Objects
+; CHECK:  fi#-4: {{.*}} fixed, at location [SP+8]
+; CHECK:  fi#-3: {{.*}} fixed, at location [SP]
+; CHECK:  fi#-2: {{.*}} fixed, at location [SP+8]
+; CHECK:  fi#-1: {{.*}} fixed, at location [SP]
+
+; CHECK:  [[VRA:%vreg.*]]<def> = LDRXui <fi#-1>
+; CHECK:  [[VRB:%vreg.*]]<def> = LDRXui <fi#-2>
+; CHECK:  STRXui %vreg{{.*}}, <fi#-4>
+; CHECK:  STRXui [[VRB]], <fi#-3>
+
+; Make sure that there is an dependence edge between fi#-2 and fi#-4.
+; Without this edge the scheduler would be free to move the store accross the load.
+
+; CHECK: SU({{.*}}):   [[VRB]]<def> = LDRXui <fi#-2>
+; CHECK-NOT: SU
+; CHECK:  Successors:
+; CHECK:   ch  SU([[DEPSTORE:.*]]): Latency=0
+
+; CHECK: SU([[DEPSTORE]]):   STRXui %vreg0, <fi#-4>
diff --git a/test/CodeGen/AArch64/tbz-tbnz.ll b/test/CodeGen/AArch64/tbz-tbnz.ll
index c77043cae94f..8863f70444d1 100644
--- a/test/CodeGen/AArch64/tbz-tbnz.ll
+++ b/test/CodeGen/AArch64/tbz-tbnz.ll
@@ -211,7 +211,7 @@ define void @test11(i64 %val1, i64* %ptr) {
 ; CHECK-NOT: cmp
 ; CHECK: tbz [[CMP]], #63
 
-  %val = load i64* %ptr
+  %val = load i64, i64* %ptr
   %tst = icmp slt i64 %val, 0
   br i1 %tst, label %if.then, label %if.end
 
diff --git a/test/CodeGen/AArch64/tst-br.ll b/test/CodeGen/AArch64/tst-br.ll
index 5dc7b5df475a..345c4d9ba95a 100644
--- a/test/CodeGen/AArch64/tst-br.ll
+++ b/test/CodeGen/AArch64/tst-br.ll
@@ -9,8 +9,8 @@
 define i32 @test_tbz() {
 ; CHECK-LABEL: test_tbz:
 
-  %val = load i32* @var32
-  %val64 = load i64* @var64
+  %val = load i32, i32* @var32
+  %val64 = load i64, i64* @var64
 
   %tbit0 = and i32 %val, 32768
   %tst0 = icmp ne i32 %tbit0, 0
diff --git a/test/CodeGen/AArch64/vcvt-oversize.ll b/test/CodeGen/AArch64/vcvt-oversize.ll
new file mode 100644
index 000000000000..066a4b666204
--- /dev/null
+++ b/test/CodeGen/AArch64/vcvt-oversize.ll
@@ -0,0 +1,16 @@
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
+
+define <8 x i8> @float_to_i8(<8 x float>* %in) {
+; CHECK-LABEL: float_to_i8:
+; CHECK-DAG: fadd v[[LSB:[0-9]+]].4s, v0.4s, v0.4s
+; CHECK-DAG: fadd v[[MSB:[0-9]+]].4s, v1.4s, v1.4s
+; CHECK-DAG: fcvtzu v[[LSB2:[0-9]+]].4s, v[[LSB]].4s
+; CHECK-DAG: fcvtzu v[[MSB2:[0-9]+]].4s, v[[MSB]].4s
+; CHECK-DAG: xtn v[[TMP:[0-9]+]].4h, v[[LSB]].4s
+; CHECK-DAG: xtn2 v[[TMP]].8h, v[[MSB]].4s
+; CHECK-DAG: xtn v0.8b, v[[TMP]].8h
+  %l = load <8 x float>, <8 x float>* %in
+  %scale = fmul <8 x float> %l, <float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0>
+  %conv = fptoui <8 x float> %scale to <8 x i8>
+  ret <8 x i8> %conv
+}
diff --git a/test/CodeGen/AArch64/zero-reg.ll b/test/CodeGen/AArch64/zero-reg.ll
index bc112ab8db98..62b2ea34ade1 100644
--- a/test/CodeGen/AArch64/zero-reg.ll
+++ b/test/CodeGen/AArch64/zero-reg.ll
@@ -21,7 +21,7 @@ define void @test_sp(i32 %val) {
 ; Important correctness point here is that LLVM doesn't try to use xzr
 ; as an addressing register: "str w0, [xzr]" is not a valid A64
 ; instruction (0b11111 in the Rn field would mean "sp").
-  %addr = getelementptr i32* null, i64 0
+  %addr = getelementptr i32, i32* null, i64 0
   store i32 %val, i32* %addr
 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+|sp}}]
 
diff --git a/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll b/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll
index f8bd886aa9e1..b719f9f4d235 100644
--- a/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll
+++ b/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll
@@ -11,9 +11,9 @@ bb169.i:                ; preds = %entry
         ret void
 
 cond_true11:            ; preds = %entry
-        %tmp.i32 = load %struct.layer_data** @ld                ; <%struct.layer_data*> [#uses=2]
-        %tmp3.i35 = getelementptr %struct.layer_data* %tmp.i32, i32 0, i32 1, i32 2048; <i8*> [#uses=2]
-        %tmp.i36 = getelementptr %struct.layer_data* %tmp.i32, i32 0, i32 2          ; <i8**> [#uses=1]
+        %tmp.i32 = load %struct.layer_data*, %struct.layer_data** @ld                ; <%struct.layer_data*> [#uses=2]
+        %tmp3.i35 = getelementptr %struct.layer_data, %struct.layer_data* %tmp.i32, i32 0, i32 1, i32 2048; <i8*> [#uses=2]
+        %tmp.i36 = getelementptr %struct.layer_data, %struct.layer_data* %tmp.i32, i32 0, i32 2          ; <i8**> [#uses=1]
         store i8* %tmp3.i35, i8** %tmp.i36
         store i8* %tmp3.i35, i8** null
         ret void
diff --git a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
index e7c0129a7752..4ba81e01ad31 100644
--- a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
+++ b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
@@ -1,5 +1,9 @@
 ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6,+vfp2 | FileCheck %s
+; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6,+vfp2 | FileCheck --check-prefix=DOMAIN %s
 
+; The execution domain checking code would translate vmovs to vorr whether or not
+; we had NEON instructions. Verify we don't if we're not compiled with NEON.
+; DOMAIN-NOT: vorr
 @quant_coef = external global [6 x [4 x [4 x i32]]]		; <[6 x [4 x [4 x i32]]]*> [#uses=1]
 @dequant_coef = external global [6 x [4 x [4 x i32]]]		; <[6 x [4 x [4 x i32]]]*> [#uses=1]
 @A = external global [4 x [4 x i32]]		; <[4 x [4 x i32]]*> [#uses=1]
@@ -15,15 +19,15 @@ entry:
 	br label %cond_next489
 
 cond_next489:		; preds = %cond_false, %bb471
-	%j.7.in = load i8* null		; <i8> [#uses=1]
-	%i.8.in = load i8* null		; <i8> [#uses=1]
+	%j.7.in = load i8, i8* null		; <i8> [#uses=1]
+	%i.8.in = load i8, i8* null		; <i8> [#uses=1]
 	%i.8 = zext i8 %i.8.in to i32		; <i32> [#uses=4]
 	%j.7 = zext i8 %j.7.in to i32		; <i32> [#uses=4]
-	%tmp495 = getelementptr [4 x [4 x i32]]* %predicted_block, i32 0, i32 %i.8, i32 %j.7		; <i32*> [#uses=2]
-	%tmp496 = load i32* %tmp495		; <i32> [#uses=2]
-	%tmp502 = load i32* null		; <i32> [#uses=1]
-	%tmp542 = getelementptr [6 x [4 x [4 x i32]]]* @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7		; <i32*> [#uses=1]
-	%tmp543 = load i32* %tmp542		; <i32> [#uses=1]
+	%tmp495 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* %predicted_block, i32 0, i32 %i.8, i32 %j.7		; <i32*> [#uses=2]
+	%tmp496 = load i32, i32* %tmp495		; <i32> [#uses=2]
+	%tmp502 = load i32, i32* null		; <i32> [#uses=1]
+	%tmp542 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7		; <i32*> [#uses=1]
+	%tmp543 = load i32, i32* %tmp542		; <i32> [#uses=1]
 	%tmp548 = ashr i32 0, 0		; <i32> [#uses=3]
 	%tmp561 = sub i32 0, %tmp496		; <i32> [#uses=3]
 	%abscond563 = icmp sgt i32 %tmp561, -1		; <i1> [#uses=1]
@@ -35,10 +39,10 @@ cond_next489:		; preds = %cond_false, %bb471
 	br i1 %tmp579, label %bb712, label %cond_next589
 
 cond_next589:		; preds = %cond_next489
-	%tmp605 = getelementptr [6 x [4 x [4 x i32]]]* @dequant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7		; <i32*> [#uses=1]
-	%tmp606 = load i32* %tmp605		; <i32> [#uses=1]
-	%tmp612 = load i32* null		; <i32> [#uses=1]
-	%tmp629 = load i32* null		; <i32> [#uses=1]
+	%tmp605 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @dequant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7		; <i32*> [#uses=1]
+	%tmp606 = load i32, i32* %tmp605		; <i32> [#uses=1]
+	%tmp612 = load i32, i32* null		; <i32> [#uses=1]
+	%tmp629 = load i32, i32* null		; <i32> [#uses=1]
 	%tmp629a = sitofp i32 %tmp629 to double		; <double> [#uses=1]
 	%tmp631 = fmul double %tmp629a, 0.000000e+00		; <double> [#uses=1]
 	%tmp632 = fadd double 0.000000e+00, %tmp631		; <double> [#uses=1]
@@ -85,9 +89,9 @@ bb737:		; preds = %cond_false689
 
 cond_true740:		; preds = %bb737
 	%tmp761 = call fastcc i32 @sign( i32 %tmp576, i32 0 )		; <i32> [#uses=1]
-	%tmp780 = load i32* null		; <i32> [#uses=1]
-	%tmp785 = getelementptr [4 x [4 x i32]]* @A, i32 0, i32 %i.8, i32 %j.7		; <i32*> [#uses=1]
-	%tmp786 = load i32* %tmp785		; <i32> [#uses=1]
+	%tmp780 = load i32, i32* null		; <i32> [#uses=1]
+	%tmp785 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* @A, i32 0, i32 %i.8, i32 %j.7		; <i32*> [#uses=1]
+	%tmp786 = load i32, i32* %tmp785		; <i32> [#uses=1]
 	%tmp781 = mul i32 %tmp780, %tmp761		; <i32> [#uses=1]
 	%tmp787 = mul i32 %tmp781, %tmp786		; <i32> [#uses=1]
 	%tmp789 = shl i32 %tmp787, 0		; <i32> [#uses=1]
@@ -96,7 +100,7 @@ cond_true740:		; preds = %bb737
 
 cond_next791:		; preds = %cond_true740, %bb737
 	%ilev.1 = phi i32 [ %tmp790, %cond_true740 ], [ 0, %bb737 ]		; <i32> [#uses=1]
-	%tmp796 = load i32* %tmp495		; <i32> [#uses=1]
+	%tmp796 = load i32, i32* %tmp495		; <i32> [#uses=1]
 	%tmp798 = add i32 %tmp796, %ilev.1		; <i32> [#uses=1]
 	%tmp812 = mul i32 0, %tmp502		; <i32> [#uses=0]
 	%tmp818 = call fastcc i32 @sign( i32 0, i32 %tmp798 )		; <i32> [#uses=0]
diff --git a/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll b/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll
index 83b26d340062..472a345a0d71 100644
--- a/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll
+++ b/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll
@@ -4,10 +4,10 @@ define fastcc i8* @read_sleb128(i8* %p, i32* %val) {
 	br label %bb
 
 bb:		; preds = %bb, %0
-	%p_addr.0 = getelementptr i8* %p, i32 0		; <i8*> [#uses=1]
-	%tmp2 = load i8* %p_addr.0		; <i8> [#uses=2]
+	%p_addr.0 = getelementptr i8, i8* %p, i32 0		; <i8*> [#uses=1]
+	%tmp2 = load i8, i8* %p_addr.0		; <i8> [#uses=2]
 	%tmp4.rec = add i32 0, 1		; <i32> [#uses=1]
-	%tmp4 = getelementptr i8* %p, i32 %tmp4.rec		; <i8*> [#uses=1]
+	%tmp4 = getelementptr i8, i8* %p, i32 %tmp4.rec		; <i8*> [#uses=1]
 	%tmp56 = zext i8 %tmp2 to i32		; <i32> [#uses=1]
 	%tmp7 = and i32 %tmp56, 127		; <i32> [#uses=1]
 	%tmp9 = shl i32 %tmp7, 0		; <i32> [#uses=1]
diff --git a/test/CodeGen/ARM/2007-03-13-InstrSched.ll b/test/CodeGen/ARM/2007-03-13-InstrSched.ll
index 4783f3707690..9c0143be06c3 100644
--- a/test/CodeGen/ARM/2007-03-13-InstrSched.ll
+++ b/test/CodeGen/ARM/2007-03-13-InstrSched.ll
@@ -23,30 +23,30 @@ bb74:		; preds = %bb26, %newFuncRoot
 	%d1.1 = phi i32 [ %tmp54, %bb26 ], [ 8192, %newFuncRoot ]		; <i32> [#uses=2]
 	%d2.1 = phi i32 [ %tmp64, %bb26 ], [ 8192, %newFuncRoot ]		; <i32> [#uses=2]
 	%d3.1 = phi i32 [ %tmp69, %bb26 ], [ 8192, %newFuncRoot ]		; <i32> [#uses=2]
-	%fm.1 = load i32* %fm.1.in		; <i32> [#uses=4]
+	%fm.1 = load i32, i32* %fm.1.in		; <i32> [#uses=4]
 	icmp eq i32 %fp.1.rec, %tmp8		; <i1>:0 [#uses=1]
 	br i1 %0, label %bb78.exitStub, label %bb26
 
 bb26:		; preds = %bb74
-	%tmp28 = getelementptr i32** %tmp1, i32 %fp.1.rec		; <i32**> [#uses=1]
-	%tmp30 = load i32** %tmp28		; <i32*> [#uses=4]
-	%tmp33 = getelementptr i32* %tmp30, i32 %i.0196.0.ph		; <i32*> [#uses=1]
-	%tmp34 = load i32* %tmp33		; <i32> [#uses=1]
-	%tmp38 = getelementptr i32* %tmp30, i32 %tmp36224		; <i32*> [#uses=1]
-	%tmp39 = load i32* %tmp38		; <i32> [#uses=1]
+	%tmp28 = getelementptr i32*, i32** %tmp1, i32 %fp.1.rec		; <i32**> [#uses=1]
+	%tmp30 = load i32*, i32** %tmp28		; <i32*> [#uses=4]
+	%tmp33 = getelementptr i32, i32* %tmp30, i32 %i.0196.0.ph		; <i32*> [#uses=1]
+	%tmp34 = load i32, i32* %tmp33		; <i32> [#uses=1]
+	%tmp38 = getelementptr i32, i32* %tmp30, i32 %tmp36224		; <i32*> [#uses=1]
+	%tmp39 = load i32, i32* %tmp38		; <i32> [#uses=1]
 	%tmp42 = mul i32 %tmp34, %fm.1		; <i32> [#uses=1]
 	%tmp44 = add i32 %tmp42, %d0.1		; <i32> [#uses=1]
-	%tmp48 = getelementptr i32* %tmp30, i32 %tmp46223		; <i32*> [#uses=1]
-	%tmp49 = load i32* %tmp48		; <i32> [#uses=1]
+	%tmp48 = getelementptr i32, i32* %tmp30, i32 %tmp46223		; <i32*> [#uses=1]
+	%tmp49 = load i32, i32* %tmp48		; <i32> [#uses=1]
 	%tmp52 = mul i32 %tmp39, %fm.1		; <i32> [#uses=1]
 	%tmp54 = add i32 %tmp52, %d1.1		; <i32> [#uses=1]
-	%tmp58 = getelementptr i32* %tmp30, i32 %tmp56222		; <i32*> [#uses=1]
-	%tmp59 = load i32* %tmp58		; <i32> [#uses=1]
+	%tmp58 = getelementptr i32, i32* %tmp30, i32 %tmp56222		; <i32*> [#uses=1]
+	%tmp59 = load i32, i32* %tmp58		; <i32> [#uses=1]
 	%tmp62 = mul i32 %tmp49, %fm.1		; <i32> [#uses=1]
 	%tmp64 = add i32 %tmp62, %d2.1		; <i32> [#uses=1]
 	%tmp67 = mul i32 %tmp59, %fm.1		; <i32> [#uses=1]
 	%tmp69 = add i32 %tmp67, %d3.1		; <i32> [#uses=1]
 	%tmp71.rec = add i32 %fp.1.rec, 1		; <i32> [#uses=2]
-	%tmp71 = getelementptr i32* %tmp1011, i32 %tmp71.rec		; <i32*> [#uses=1]
+	%tmp71 = getelementptr i32, i32* %tmp1011, i32 %tmp71.rec		; <i32*> [#uses=1]
 	br label %bb74
 }
diff --git a/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll b/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll
index b0953dc8b61f..7c425961958c 100644
--- a/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll
+++ b/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll
@@ -41,7 +41,7 @@ entry:
 	%spec.1961.adj.ins = or i64 %spec.1961.adj, 0		; <i64> [#uses=2]
 	%tmp10959 = lshr i64 %spec.1961.adj.ins, 32		; <i64> [#uses=2]
 	%tmp1920 = inttoptr i64 %tmp10959 to %struct.tree_common*		; <%struct.tree_common*> [#uses=1]
-	%tmp21 = getelementptr %struct.tree_common* %tmp1920, i32 0, i32 3		; <i8*> [#uses=1]
+	%tmp21 = getelementptr %struct.tree_common, %struct.tree_common* %tmp1920, i32 0, i32 3		; <i8*> [#uses=1]
 	%tmp2122 = bitcast i8* %tmp21 to i32*		; <i32*> [#uses=1]
 	br i1 false, label %cond_next53, label %cond_true
 
@@ -71,7 +71,7 @@ cond_next856:		; preds = %cond_true851
 	ret void
 
 bb866:		; preds = %cond_true851
-	%tmp874 = load i32* %tmp2122		; <i32> [#uses=1]
+	%tmp874 = load i32, i32* %tmp2122		; <i32> [#uses=1]
 	%tmp876877 = trunc i32 %tmp874 to i8		; <i8> [#uses=1]
 	icmp eq i8 %tmp876877, 1		; <i1>:0 [#uses=1]
 	br i1 %0, label %cond_next881, label %cond_true878
@@ -81,9 +81,9 @@ cond_true878:		; preds = %bb866
 
 cond_next881:		; preds = %bb866
 	%tmp884885 = inttoptr i64 %tmp10959 to %struct.tree_identifier*		; <%struct.tree_identifier*> [#uses=1]
-	%tmp887 = getelementptr %struct.tree_identifier* %tmp884885, i32 0, i32 1, i32 0		; <i8**> [#uses=1]
-	%tmp888 = load i8** %tmp887		; <i8*> [#uses=1]
-	tail call void (i32, ...)* @error( i32 undef, i8* %tmp888 )
+	%tmp887 = getelementptr %struct.tree_identifier, %struct.tree_identifier* %tmp884885, i32 0, i32 1, i32 0		; <i8**> [#uses=1]
+	%tmp888 = load i8*, i8** %tmp887		; <i8*> [#uses=1]
+	tail call void (i32, ...) @error( i32 undef, i8* %tmp888 )
 	ret void
 
 cond_true918:		; preds = %cond_false841
diff --git a/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll b/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll
index e4635f50279d..2a0ef770f3bc 100644
--- a/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll
+++ b/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll
@@ -13,7 +13,7 @@ cond_true340:		; preds = %entry
 	ret void
 
 cond_next416:		; preds = %entry
-	%tmp1085 = load %struct.rtx_def** %ad_addr		; <%struct.rtx_def*> [#uses=1]
+	%tmp1085 = load %struct.rtx_def*, %struct.rtx_def** %ad_addr		; <%struct.rtx_def*> [#uses=1]
 	br i1 false, label %bb1084, label %cond_true418
 
 cond_true418:		; preds = %cond_next416
@@ -23,9 +23,9 @@ bb1084:		; preds = %cond_next416
 	br i1 false, label %cond_true1092, label %cond_next1102
 
 cond_true1092:		; preds = %bb1084
-	%tmp1094 = getelementptr %struct.rtx_def* %tmp1085, i32 0, i32 3		; <%struct.u*> [#uses=1]
+	%tmp1094 = getelementptr %struct.rtx_def, %struct.rtx_def* %tmp1085, i32 0, i32 3		; <%struct.u*> [#uses=1]
 	%tmp10981099 = bitcast %struct.u* %tmp1094 to %struct.rtx_def**		; <%struct.rtx_def**> [#uses=2]
-	%tmp1101 = load %struct.rtx_def** %tmp10981099		; <%struct.rtx_def*> [#uses=1]
+	%tmp1101 = load %struct.rtx_def*, %struct.rtx_def** %tmp10981099		; <%struct.rtx_def*> [#uses=1]
 	store %struct.rtx_def* %tmp1101, %struct.rtx_def** %ad_addr
 	br label %cond_next1102
 
diff --git a/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll b/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll
index f24def31f97a..7b74e6ce948f 100644
--- a/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll
+++ b/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll
@@ -28,7 +28,7 @@ entry:
 	br i1 false, label %bb.preheader, label %return
 
 bb.preheader:		; preds = %entry
-	%tbl.014.us = load i32* null		; <i32> [#uses=1]
+	%tbl.014.us = load i32, i32* null		; <i32> [#uses=1]
 	br i1 false, label %cond_next.us, label %bb
 
 cond_next51.us:		; preds = %cond_next.us, %cond_true33.us.cond_true46.us_crit_edge
@@ -40,8 +40,8 @@ cond_true33.us.cond_true46.us_crit_edge:		; preds = %cond_next.us
 	br label %cond_next51.us
 
 cond_next.us:		; preds = %bb.preheader
-	%tmp37.us = getelementptr %struct.X_Y* %cinfo, i32 0, i32 17, i32 %tbl.014.us		; <%struct.H_TBL**> [#uses=3]
-	%tmp4524.us = load %struct.H_TBL** %tmp37.us		; <%struct.H_TBL*> [#uses=1]
+	%tmp37.us = getelementptr %struct.X_Y, %struct.X_Y* %cinfo, i32 0, i32 17, i32 %tbl.014.us		; <%struct.H_TBL**> [#uses=3]
+	%tmp4524.us = load %struct.H_TBL*, %struct.H_TBL** %tmp37.us		; <%struct.H_TBL*> [#uses=1]
 	icmp eq %struct.H_TBL* %tmp4524.us, null		; <i1>:0 [#uses=1]
 	br i1 %0, label %cond_true33.us.cond_true46.us_crit_edge, label %cond_next51.us
 
diff --git a/test/CodeGen/ARM/2007-04-03-PEIBug.ll b/test/CodeGen/ARM/2007-04-03-PEIBug.ll
index cf5094fb3800..87863bd3ec15 100644
--- a/test/CodeGen/ARM/2007-04-03-PEIBug.ll
+++ b/test/CodeGen/ARM/2007-04-03-PEIBug.ll
@@ -5,7 +5,7 @@ entry:
 	%A = alloca [1123 x i32], align 16		; <[1123 x i32]*> [#uses=1]
 	%B = alloca [3123 x i32], align 16		; <[3123 x i32]*> [#uses=1]
 	%C = alloca [12312 x i32], align 16		; <[12312 x i32]*> [#uses=1]
-	%tmp = call i32 (...)* @bar( [3123 x i32]* %B, [1123 x i32]* %A, [12312 x i32]* %C )		; <i32> [#uses=0]
+	%tmp = call i32 (...) @bar( [3123 x i32]* %B, [1123 x i32]* %A, [12312 x i32]* %C )		; <i32> [#uses=0]
 	ret i32 undef
 }
 
diff --git a/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll b/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll
index e001cde8351b..11f3003e05b5 100644
--- a/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll
+++ b/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll
@@ -8,9 +8,9 @@
 
 define internal void @_ZN1B1iEv(%struct.B* %this) {
 entry:
-	%tmp1 = getelementptr %struct.B* %this, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp2 = load i32* %tmp1		; <i32> [#uses=1]
-	%tmp4 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8]* @str, i32 0, i32 0), i32 %tmp2 )		; <i32> [#uses=0]
+	%tmp1 = getelementptr %struct.B, %struct.B* %this, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp2 = load i32, i32* %tmp1		; <i32> [#uses=1]
+	%tmp4 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([7 x i8], [7 x i8]* @str, i32 0, i32 0), i32 %tmp2 )		; <i32> [#uses=0]
 	ret void
 }
 
@@ -18,9 +18,9 @@ declare i32 @printf(i8*, ...)
 
 define internal void @_ZN1B1jEv(%struct.B* %this) {
 entry:
-	%tmp1 = getelementptr %struct.B* %this, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp2 = load i32* %tmp1		; <i32> [#uses=1]
-	%tmp4 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8]* @str1, i32 0, i32 0), i32 %tmp2 )		; <i32> [#uses=0]
+	%tmp1 = getelementptr %struct.B, %struct.B* %this, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp2 = load i32, i32* %tmp1		; <i32> [#uses=1]
+	%tmp4 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([7 x i8], [7 x i8]* @str1, i32 0, i32 0), i32 %tmp2 )		; <i32> [#uses=0]
 	ret void
 }
 
@@ -29,70 +29,70 @@ entry:
 	%b.i29 = alloca %struct.B, align 4		; <%struct.B*> [#uses=3]
 	%b.i1 = alloca %struct.B, align 4		; <%struct.B*> [#uses=3]
 	%b.i = alloca %struct.B, align 4		; <%struct.B*> [#uses=3]
-	%tmp2.i = getelementptr %struct.B* %b.i, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp2.i = getelementptr %struct.B, %struct.B* %b.i, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 4, i32* %tmp2.i
 	br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit, label %cond_true.i
 
 cond_true.i:		; preds = %entry
 	%b2.i = bitcast %struct.B* %b.i to i8*		; <i8*> [#uses=1]
-	%ctg23.i = getelementptr i8* %b2.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)		; <i8*> [#uses=1]
+	%ctg23.i = getelementptr i8, i8* %b2.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)		; <i8*> [#uses=1]
 	%tmp121314.i = bitcast i8* %ctg23.i to i32 (...)***		; <i32 (...)***> [#uses=1]
-	%tmp15.i = load i32 (...)*** %tmp121314.i		; <i32 (...)**> [#uses=1]
+	%tmp15.i = load i32 (...)**, i32 (...)*** %tmp121314.i		; <i32 (...)**> [#uses=1]
 	%tmp151.i = bitcast i32 (...)** %tmp15.i to i8*		; <i8*> [#uses=1]
-	%ctg2.i = getelementptr i8* %tmp151.i, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32)		; <i8*> [#uses=1]
+	%ctg2.i = getelementptr i8, i8* %tmp151.i, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32)		; <i8*> [#uses=1]
 	%tmp2021.i = bitcast i8* %ctg2.i to i32 (...)**		; <i32 (...)**> [#uses=1]
-	%tmp22.i = load i32 (...)** %tmp2021.i		; <i32 (...)*> [#uses=1]
+	%tmp22.i = load i32 (...)*, i32 (...)** %tmp2021.i		; <i32 (...)*> [#uses=1]
 	%tmp2223.i = bitcast i32 (...)* %tmp22.i to void (%struct.B*)*		; <void (%struct.B*)*> [#uses=1]
 	br label %_Z3fooiM1BFvvE.exit
 
 _Z3fooiM1BFvvE.exit:		; preds = %cond_true.i, %entry
 	%iftmp.2.0.i = phi void (%struct.B*)* [ %tmp2223.i, %cond_true.i ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to void (%struct.B*)*), %entry ]		; <void (%struct.B*)*> [#uses=1]
 	%b4.i = bitcast %struct.B* %b.i to i8*		; <i8*> [#uses=1]
-	%ctg25.i = getelementptr i8* %b4.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)		; <i8*> [#uses=1]
+	%ctg25.i = getelementptr i8, i8* %b4.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)		; <i8*> [#uses=1]
 	%tmp3031.i = bitcast i8* %ctg25.i to %struct.B*		; <%struct.B*> [#uses=1]
 	call void %iftmp.2.0.i( %struct.B* %tmp3031.i )
-	%tmp2.i30 = getelementptr %struct.B* %b.i29, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp2.i30 = getelementptr %struct.B, %struct.B* %b.i29, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 6, i32* %tmp2.i30
 	br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit56, label %cond_true.i46
 
 cond_true.i46:		; preds = %_Z3fooiM1BFvvE.exit
 	%b2.i35 = bitcast %struct.B* %b.i29 to i8*		; <i8*> [#uses=1]
-	%ctg23.i36 = getelementptr i8* %b2.i35, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1)		; <i8*> [#uses=1]
+	%ctg23.i36 = getelementptr i8, i8* %b2.i35, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1)		; <i8*> [#uses=1]
 	%tmp121314.i37 = bitcast i8* %ctg23.i36 to i32 (...)***		; <i32 (...)***> [#uses=1]
-	%tmp15.i38 = load i32 (...)*** %tmp121314.i37		; <i32 (...)**> [#uses=1]
+	%tmp15.i38 = load i32 (...)**, i32 (...)*** %tmp121314.i37		; <i32 (...)**> [#uses=1]
 	%tmp151.i41 = bitcast i32 (...)** %tmp15.i38 to i8*		; <i8*> [#uses=1]
-	%ctg2.i42 = getelementptr i8* %tmp151.i41, i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32)		; <i8*> [#uses=1]
+	%ctg2.i42 = getelementptr i8, i8* %tmp151.i41, i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32)		; <i8*> [#uses=1]
 	%tmp2021.i43 = bitcast i8* %ctg2.i42 to i32 (...)**		; <i32 (...)**> [#uses=1]
-	%tmp22.i44 = load i32 (...)** %tmp2021.i43		; <i32 (...)*> [#uses=1]
+	%tmp22.i44 = load i32 (...)*, i32 (...)** %tmp2021.i43		; <i32 (...)*> [#uses=1]
 	%tmp2223.i45 = bitcast i32 (...)* %tmp22.i44 to void (%struct.B*)*		; <void (%struct.B*)*> [#uses=1]
 	br label %_Z3fooiM1BFvvE.exit56
 
 _Z3fooiM1BFvvE.exit56:		; preds = %cond_true.i46, %_Z3fooiM1BFvvE.exit
 	%iftmp.2.0.i49 = phi void (%struct.B*)* [ %tmp2223.i45, %cond_true.i46 ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to void (%struct.B*)*), %_Z3fooiM1BFvvE.exit ]		; <void (%struct.B*)*> [#uses=1]
 	%b4.i53 = bitcast %struct.B* %b.i29 to i8*		; <i8*> [#uses=1]
-	%ctg25.i54 = getelementptr i8* %b4.i53, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1)		; <i8*> [#uses=1]
+	%ctg25.i54 = getelementptr i8, i8* %b4.i53, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1)		; <i8*> [#uses=1]
 	%tmp3031.i55 = bitcast i8* %ctg25.i54 to %struct.B*		; <%struct.B*> [#uses=1]
 	call void %iftmp.2.0.i49( %struct.B* %tmp3031.i55 )
-	%tmp2.i2 = getelementptr %struct.B* %b.i1, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp2.i2 = getelementptr %struct.B, %struct.B* %b.i1, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 -1, i32* %tmp2.i2
 	br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit28, label %cond_true.i18
 
 cond_true.i18:		; preds = %_Z3fooiM1BFvvE.exit56
 	%b2.i7 = bitcast %struct.B* %b.i1 to i8*		; <i8*> [#uses=1]
-	%ctg23.i8 = getelementptr i8* %b2.i7, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)		; <i8*> [#uses=1]
+	%ctg23.i8 = getelementptr i8, i8* %b2.i7, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)		; <i8*> [#uses=1]
 	%tmp121314.i9 = bitcast i8* %ctg23.i8 to i32 (...)***		; <i32 (...)***> [#uses=1]
-	%tmp15.i10 = load i32 (...)*** %tmp121314.i9		; <i32 (...)**> [#uses=1]
+	%tmp15.i10 = load i32 (...)**, i32 (...)*** %tmp121314.i9		; <i32 (...)**> [#uses=1]
 	%tmp151.i13 = bitcast i32 (...)** %tmp15.i10 to i8*		; <i8*> [#uses=1]
-	%ctg2.i14 = getelementptr i8* %tmp151.i13, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32)		; <i8*> [#uses=1]
+	%ctg2.i14 = getelementptr i8, i8* %tmp151.i13, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32)		; <i8*> [#uses=1]
 	%tmp2021.i15 = bitcast i8* %ctg2.i14 to i32 (...)**		; <i32 (...)**> [#uses=1]
-	%tmp22.i16 = load i32 (...)** %tmp2021.i15		; <i32 (...)*> [#uses=1]
+	%tmp22.i16 = load i32 (...)*, i32 (...)** %tmp2021.i15		; <i32 (...)*> [#uses=1]
 	%tmp2223.i17 = bitcast i32 (...)* %tmp22.i16 to void (%struct.B*)*		; <void (%struct.B*)*> [#uses=1]
 	br label %_Z3fooiM1BFvvE.exit28
 
 _Z3fooiM1BFvvE.exit28:		; preds = %cond_true.i18, %_Z3fooiM1BFvvE.exit56
 	%iftmp.2.0.i21 = phi void (%struct.B*)* [ %tmp2223.i17, %cond_true.i18 ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to void (%struct.B*)*), %_Z3fooiM1BFvvE.exit56 ]		; <void (%struct.B*)*> [#uses=1]
 	%b4.i25 = bitcast %struct.B* %b.i1 to i8*		; <i8*> [#uses=1]
-	%ctg25.i26 = getelementptr i8* %b4.i25, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)		; <i8*> [#uses=1]
+	%ctg25.i26 = getelementptr i8, i8* %b4.i25, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)		; <i8*> [#uses=1]
 	%tmp3031.i27 = bitcast i8* %ctg25.i26 to %struct.B*		; <%struct.B*> [#uses=1]
 	call void %iftmp.2.0.i21( %struct.B* %tmp3031.i27 )
 	ret i32 0
diff --git a/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll b/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll
index a89e937d3e10..05c2ff4f7ca2 100644
--- a/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll
+++ b/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll
@@ -9,15 +9,15 @@ target triple = "arm-apple-darwin8"
 
 define fastcc void @EvaluateDevelopment() {
 entry:
-        %tmp7 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 7)         ; <i64> [#uses=1]
-        %tmp50 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 0)                ; <i64> [#uses=1]
-        %tmp52 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 1)                ; <i64> [#uses=1]
+        %tmp7 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 7)         ; <i64> [#uses=1]
+        %tmp50 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 0)                ; <i64> [#uses=1]
+        %tmp52 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 1)                ; <i64> [#uses=1]
         %tmp53 = or i64 %tmp52, %tmp50          ; <i64> [#uses=1]
-        %tmp57.b = load i1* @rank_mask.1.b              ; <i1> [#uses=1]
+        %tmp57.b = load i1, i1* @rank_mask.1.b              ; <i1> [#uses=1]
         %tmp57 = select i1 %tmp57.b, i64 71776119061217280, i64 0               ; <i64> [#uses=1]
         %tmp58 = and i64 %tmp57, %tmp7          ; <i64> [#uses=1]
         %tmp59 = lshr i64 %tmp58, 8             ; <i64> [#uses=1]
-        %tmp63 = load i64* getelementptr ([8 x i64]* @file_mask, i32 0, i32 4)          ; <i64> [#uses=1]
+        %tmp63 = load i64, i64* getelementptr ([8 x i64], [8 x i64]* @file_mask, i32 0, i32 4)          ; <i64> [#uses=1]
         %tmp64 = or i64 %tmp63, 0               ; <i64> [#uses=1]
         %tmp65 = and i64 %tmp59, %tmp53         ; <i64> [#uses=1]
         %tmp66 = and i64 %tmp65, %tmp64         ; <i64> [#uses=1]
diff --git a/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll b/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll
index 25ac52e5ec77..50573b457c37 100644
--- a/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll
+++ b/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll
@@ -14,7 +14,7 @@
 
 define fastcc void @Draw7(i32 %Option, i32* %Status) {
 entry:
-	%tmp115.b = load i1* @FirstTime.4637.b		; <i1> [#uses=1]
+	%tmp115.b = load i1, i1* @FirstTime.4637.b		; <i1> [#uses=1]
 	br i1 %tmp115.b, label %cond_next239, label %cond_next.i
 
 cond_next.i:		; preds = %entry
@@ -88,19 +88,19 @@ cond_next1267:		; preds = %cond_next1235
 	br i1 %tmp1148, label %cond_next1275, label %cond_true1272
 
 cond_true1272:		; preds = %cond_next1267
-	%tmp1273 = load %struct.TestObj** null		; <%struct.TestObj*> [#uses=2]
+	%tmp1273 = load %struct.TestObj*, %struct.TestObj** null		; <%struct.TestObj*> [#uses=2]
 	%tmp2930.i = ptrtoint %struct.TestObj* %tmp1273 to i32		; <i32> [#uses=1]
 	%tmp42.i348 = sub i32 0, %tmp2930.i		; <i32> [#uses=1]
-	%tmp45.i = getelementptr %struct.TestObj* %tmp1273, i32 0, i32 0		; <i8**> [#uses=2]
-	%tmp48.i = load i8** %tmp45.i		; <i8*> [#uses=1]
-	%tmp50.i350 = call i32 (i8*, i8*, ...)* @sprintf( i8* getelementptr ([256 x i8]* @Msg, i32 0, i32 0), i8* getelementptr ([48 x i8]* @.str53615, i32 0, i32 0), i8* null, i8** %tmp45.i, i8* %tmp48.i )		; <i32> [#uses=0]
+	%tmp45.i = getelementptr %struct.TestObj, %struct.TestObj* %tmp1273, i32 0, i32 0		; <i8**> [#uses=2]
+	%tmp48.i = load i8*, i8** %tmp45.i		; <i8*> [#uses=1]
+	%tmp50.i350 = call i32 (i8*, i8*, ...) @sprintf( i8* getelementptr ([256 x i8], [256 x i8]* @Msg, i32 0, i32 0), i8* getelementptr ([48 x i8], [48 x i8]* @.str53615, i32 0, i32 0), i8* null, i8** %tmp45.i, i8* %tmp48.i )		; <i32> [#uses=0]
 	br i1 false, label %cond_true.i632.i, label %Ut_TraceMsg.exit648.i
 
 cond_true.i632.i:		; preds = %cond_true1272
 	ret void
 
 Ut_TraceMsg.exit648.i:		; preds = %cond_true1272
-	%tmp57.i = getelementptr i8* null, i32 %tmp42.i348		; <i8*> [#uses=0]
+	%tmp57.i = getelementptr i8, i8* null, i32 %tmp42.i348		; <i8*> [#uses=0]
 	ret void
 
 cond_next1275:		; preds = %cond_next1267
diff --git a/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll b/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll
index 90a3b372937e..f49c805469a0 100644
--- a/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll
+++ b/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll
@@ -17,45 +17,45 @@ entry:
 	%retval = alloca i32, align 4		; <i32*> [#uses=1]
 	store i32 %i, i32* %i_addr
 	store i32 %q, i32* %q_addr
-	%tmp = load i32* %i_addr		; <i32> [#uses=1]
+	%tmp = load i32, i32* %i_addr		; <i32> [#uses=1]
 	%tmp1 = icmp ne i32 %tmp, 0		; <i1> [#uses=1]
 	%tmp12 = zext i1 %tmp1 to i8		; <i8> [#uses=1]
 	%toBool = icmp ne i8 %tmp12, 0		; <i1> [#uses=1]
 	br i1 %toBool, label %cond_true, label %cond_false
 
 cond_true:		; preds = %entry
-	%tmp3 = call i32 (...)* @bar( )		; <i32> [#uses=0]
-	%tmp4 = call i32 (...)* @baz( i32 5, i32 6 )		; <i32> [#uses=0]
+	%tmp3 = call i32 (...) @bar( )		; <i32> [#uses=0]
+	%tmp4 = call i32 (...) @baz( i32 5, i32 6 )		; <i32> [#uses=0]
 	br label %cond_next
 
 cond_false:		; preds = %entry
-	%tmp5 = call i32 (...)* @foo( )		; <i32> [#uses=0]
-	%tmp6 = call i32 (...)* @baz( i32 5, i32 6 )		; <i32> [#uses=0]
+	%tmp5 = call i32 (...) @foo( )		; <i32> [#uses=0]
+	%tmp6 = call i32 (...) @baz( i32 5, i32 6 )		; <i32> [#uses=0]
 	br label %cond_next
 
 cond_next:		; preds = %cond_false, %cond_true
-	%tmp7 = load i32* %q_addr		; <i32> [#uses=1]
+	%tmp7 = load i32, i32* %q_addr		; <i32> [#uses=1]
 	%tmp8 = icmp ne i32 %tmp7, 0		; <i1> [#uses=1]
 	%tmp89 = zext i1 %tmp8 to i8		; <i8> [#uses=1]
 	%toBool10 = icmp ne i8 %tmp89, 0		; <i1> [#uses=1]
 	br i1 %toBool10, label %cond_true11, label %cond_false15
 
 cond_true11:		; preds = %cond_next
-	%tmp13 = call i32 (...)* @foo( )		; <i32> [#uses=0]
-	%tmp14 = call i32 (...)* @quux( i32 3, i32 4 )		; <i32> [#uses=0]
+	%tmp13 = call i32 (...) @foo( )		; <i32> [#uses=0]
+	%tmp14 = call i32 (...) @quux( i32 3, i32 4 )		; <i32> [#uses=0]
 	br label %cond_next18
 
 cond_false15:		; preds = %cond_next
-	%tmp16 = call i32 (...)* @bar( )		; <i32> [#uses=0]
-	%tmp17 = call i32 (...)* @quux( i32 3, i32 4 )		; <i32> [#uses=0]
+	%tmp16 = call i32 (...) @bar( )		; <i32> [#uses=0]
+	%tmp17 = call i32 (...) @quux( i32 3, i32 4 )		; <i32> [#uses=0]
 	br label %cond_next18
 
 cond_next18:		; preds = %cond_false15, %cond_true11
-	%tmp19 = call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp19 = call i32 (...) @bar( )		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %cond_next18
-	%retval20 = load i32* %retval		; <i32> [#uses=1]
+	%retval20 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval20
 }
 
diff --git a/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll b/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll
index 37e41ecc4b1e..421d501a2ca9 100644
--- a/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll
+++ b/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll
@@ -19,46 +19,46 @@ entry:
 	%retval = alloca i32, align 4		; <i32*> [#uses=1]
 	store i32 %i, i32* %i_addr
 	store i32 %q, i32* %q_addr
-	%tmp = load i32* %i_addr		; <i32> [#uses=1]
+	%tmp = load i32, i32* %i_addr		; <i32> [#uses=1]
 	%tmp1 = icmp ne i32 %tmp, 0		; <i1> [#uses=1]
 	%tmp12 = zext i1 %tmp1 to i8		; <i8> [#uses=1]
 	%toBool = icmp ne i8 %tmp12, 0		; <i1> [#uses=1]
 	br i1 %toBool, label %cond_true, label %cond_false
 
 cond_true:		; preds = %entry
-	%tmp3 = call i32 (...)* @bar( )		; <i32> [#uses=0]
-	%tmp4 = call i32 (...)* @baz( i32 5, i32 6 )		; <i32> [#uses=0]
-	%tmp7 = load i32* %q_addr		; <i32> [#uses=1]
+	%tmp3 = call i32 (...) @bar( )		; <i32> [#uses=0]
+	%tmp4 = call i32 (...) @baz( i32 5, i32 6 )		; <i32> [#uses=0]
+	%tmp7 = load i32, i32* %q_addr		; <i32> [#uses=1]
 	%tmp8 = icmp ne i32 %tmp7, 0		; <i1> [#uses=1]
 	%tmp89 = zext i1 %tmp8 to i8		; <i8> [#uses=1]
 	%toBool10 = icmp ne i8 %tmp89, 0		; <i1> [#uses=1]
 	br i1 %toBool10, label %cond_true11, label %cond_false15
 
 cond_false:		; preds = %entry
-	%tmp5 = call i32 (...)* @foo( )		; <i32> [#uses=0]
-	%tmp6 = call i32 (...)* @baz( i32 5, i32 6 )		; <i32> [#uses=0]
-	%tmp27 = load i32* %q_addr		; <i32> [#uses=1]
+	%tmp5 = call i32 (...) @foo( )		; <i32> [#uses=0]
+	%tmp6 = call i32 (...) @baz( i32 5, i32 6 )		; <i32> [#uses=0]
+	%tmp27 = load i32, i32* %q_addr		; <i32> [#uses=1]
 	%tmp28 = icmp ne i32 %tmp27, 0		; <i1> [#uses=1]
 	%tmp289 = zext i1 %tmp28 to i8		; <i8> [#uses=1]
 	%toBool210 = icmp ne i8 %tmp289, 0		; <i1> [#uses=1]
 	br i1 %toBool210, label %cond_true11, label %cond_false15
 
 cond_true11:		; preds = %cond_next
-	%tmp13 = call i32 (...)* @foo( )		; <i32> [#uses=0]
-	%tmp14 = call i32 (...)* @quux( i32 3, i32 4 )		; <i32> [#uses=0]
+	%tmp13 = call i32 (...) @foo( )		; <i32> [#uses=0]
+	%tmp14 = call i32 (...) @quux( i32 3, i32 4 )		; <i32> [#uses=0]
 	br label %cond_next18
 
 cond_false15:		; preds = %cond_next
-	%tmp16 = call i32 (...)* @bar( )		; <i32> [#uses=0]
-	%tmp17 = call i32 (...)* @quux( i32 3, i32 4 )		; <i32> [#uses=0]
+	%tmp16 = call i32 (...) @bar( )		; <i32> [#uses=0]
+	%tmp17 = call i32 (...) @quux( i32 3, i32 4 )		; <i32> [#uses=0]
 	br label %cond_next18
 
 cond_next18:		; preds = %cond_false15, %cond_true11
-	%tmp19 = call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp19 = call i32 (...) @bar( )		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %cond_next18
-	%retval20 = load i32* %retval		; <i32> [#uses=1]
+	%retval20 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval20
 }
 
diff --git a/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll b/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll
index 30ae7237395e..52cc37e24084 100644
--- a/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll
+++ b/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll
@@ -29,46 +29,46 @@ entry:
 	%retval = alloca i32, align 4		; <i32*> [#uses=1]
 	store i32 %i, i32* %i_addr
 	store i32 %q, i32* %q_addr
-	%tmp = load i32* %i_addr		; <i32> [#uses=1]
+	%tmp = load i32, i32* %i_addr		; <i32> [#uses=1]
 	%tmp1 = icmp ne i32 %tmp, 0		; <i1> [#uses=1]
 	%tmp12 = zext i1 %tmp1 to i8		; <i8> [#uses=1]
 	%toBool = icmp ne i8 %tmp12, 0		; <i1> [#uses=1]
 	br i1 %toBool, label %cond_true, label %cond_false
 
 cond_true:		; preds = %entry
-	%tmp3 = call i32 (...)* @bar( )		; <i32> [#uses=0]
-	%tmp4 = call i32 (...)* @baz( i32 5, i32 6 )		; <i32> [#uses=0]
-	%tmp7 = load i32* %q_addr		; <i32> [#uses=1]
+	%tmp3 = call i32 (...) @bar( )		; <i32> [#uses=0]
+	%tmp4 = call i32 (...) @baz( i32 5, i32 6 )		; <i32> [#uses=0]
+	%tmp7 = load i32, i32* %q_addr		; <i32> [#uses=1]
 	%tmp8 = icmp ne i32 %tmp7, 0		; <i1> [#uses=1]
 	%tmp89 = zext i1 %tmp8 to i8		; <i8> [#uses=1]
 	%toBool10 = icmp ne i8 %tmp89, 0		; <i1> [#uses=1]
 	br i1 %toBool10, label %cond_true11, label %cond_false15
 
 cond_false:		; preds = %entry
-	%tmp5 = call i32 (...)* @foo( )		; <i32> [#uses=0]
-	%tmp6 = call i32 (...)* @baz( i32 5, i32 6 )		; <i32> [#uses=0]
-	%tmp27 = load i32* %q_addr		; <i32> [#uses=1]
+	%tmp5 = call i32 (...) @foo( )		; <i32> [#uses=0]
+	%tmp6 = call i32 (...) @baz( i32 5, i32 6 )		; <i32> [#uses=0]
+	%tmp27 = load i32, i32* %q_addr		; <i32> [#uses=1]
 	%tmp28 = icmp ne i32 %tmp27, 0		; <i1> [#uses=1]
 	%tmp289 = zext i1 %tmp28 to i8		; <i8> [#uses=1]
 	%toBool210 = icmp ne i8 %tmp289, 0		; <i1> [#uses=1]
 	br i1 %toBool210, label %cond_true11, label %cond_false15
 
 cond_true11:		; preds = %cond_next
-	%tmp13 = call i32 (...)* @foo( )		; <i32> [#uses=0]
-	%tmp14 = call i32 (...)* @quux( i32 3, i32 4 )		; <i32> [#uses=0]
+	%tmp13 = call i32 (...) @foo( )		; <i32> [#uses=0]
+	%tmp14 = call i32 (...) @quux( i32 3, i32 4 )		; <i32> [#uses=0]
 	br label %cond_next18
 
 cond_false15:		; preds = %cond_next
-	%tmp16 = call i32 (...)* @bar( )		; <i32> [#uses=0]
-	%tmp17 = call i32 (...)* @quux( i32 3, i32 4 )		; <i32> [#uses=0]
+	%tmp16 = call i32 (...) @bar( )		; <i32> [#uses=0]
+	%tmp17 = call i32 (...) @quux( i32 3, i32 4 )		; <i32> [#uses=0]
 	br label %cond_next18
 
 cond_next18:		; preds = %cond_false15, %cond_true11
-	%tmp19 = call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp19 = call i32 (...) @bar( )		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %cond_next18
-	%retval20 = load i32* %retval		; <i32> [#uses=1]
+	%retval20 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval20
 }
 
diff --git a/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll b/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll
index 5988c65dae6c..e0b28e874b90 100644
--- a/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll
+++ b/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll
@@ -17,10 +17,10 @@ cond_false:		; preds = %entry
 bb140:		; preds = %bb140, %cond_false
 	%indvar = phi i32 [ 0, %cond_false ], [ %indvar.next, %bb140 ]		; <i32> [#uses=2]
 	%edge.230.0.rec = shl i32 %indvar, 1		; <i32> [#uses=3]
-	%edge.230.0 = getelementptr %struct.shape_edge_t* null, i32 %edge.230.0.rec		; <%struct.shape_edge_t*> [#uses=1]
+	%edge.230.0 = getelementptr %struct.shape_edge_t, %struct.shape_edge_t* null, i32 %edge.230.0.rec		; <%struct.shape_edge_t*> [#uses=1]
 	%edge.230.0.sum6970 = or i32 %edge.230.0.rec, 1		; <i32> [#uses=2]
-	%tmp154 = getelementptr %struct.shape_edge_t* null, i32 %edge.230.0.sum6970		; <%struct.shape_edge_t*> [#uses=1]
-	%tmp11.i5 = getelementptr %struct.shape_edge_t* null, i32 %edge.230.0.sum6970, i32 0		; <%struct.shape_edge_t**> [#uses=1]
+	%tmp154 = getelementptr %struct.shape_edge_t, %struct.shape_edge_t* null, i32 %edge.230.0.sum6970		; <%struct.shape_edge_t*> [#uses=1]
+	%tmp11.i5 = getelementptr %struct.shape_edge_t, %struct.shape_edge_t* null, i32 %edge.230.0.sum6970, i32 0		; <%struct.shape_edge_t**> [#uses=1]
 	store %struct.shape_edge_t* %edge.230.0, %struct.shape_edge_t** %tmp11.i5
 	store %struct.shape_edge_t* %tmp154, %struct.shape_edge_t** null
 	%tmp16254.0.rec = add i32 %edge.230.0.rec, 2		; <i32> [#uses=1]
diff --git a/test/CodeGen/ARM/2007-08-15-ReuseBug.ll b/test/CodeGen/ARM/2007-08-15-ReuseBug.ll
index 30b72e09a114..76b6221d0222 100644
--- a/test/CodeGen/ARM/2007-08-15-ReuseBug.ll
+++ b/test/CodeGen/ARM/2007-08-15-ReuseBug.ll
@@ -44,13 +44,13 @@ bb102.i:		; preds = %cond_next212.i
 	br i1 false, label %cond_true110.i, label %cond_next123.i
 
 cond_true110.i:		; preds = %bb102.i
-	%tmp116.i = getelementptr i8** %argv_addr.2321.0.i, i32 2		; <i8**> [#uses=1]
-	%tmp117.i = load i8** %tmp116.i		; <i8*> [#uses=1]
-	%tmp126425.i = call %struct.FILE* @fopen( i8* %tmp117.i, i8* getelementptr ([2 x i8]* @.str44, i32 0, i32 0) )		; <%struct.FILE*> [#uses=0]
+	%tmp116.i = getelementptr i8*, i8** %argv_addr.2321.0.i, i32 2		; <i8**> [#uses=1]
+	%tmp117.i = load i8*, i8** %tmp116.i		; <i8*> [#uses=1]
+	%tmp126425.i = call %struct.FILE* @fopen( i8* %tmp117.i, i8* getelementptr ([2 x i8], [2 x i8]* @.str44, i32 0, i32 0) )		; <%struct.FILE*> [#uses=0]
 	ret i32 0
 
 cond_next123.i:		; preds = %bb102.i
-	%tmp122.i = getelementptr i8* %tmp215.i, i32 2		; <i8*> [#uses=0]
+	%tmp122.i = getelementptr i8, i8* %tmp215.i, i32 2		; <i8*> [#uses=0]
 	ret i32 0
 
 bb162.i:		; preds = %cond_next212.i
@@ -58,12 +58,12 @@ bb162.i:		; preds = %cond_next212.i
 
 C_addcmd.exit120.i:		; preds = %cond_next212.i
 	%tmp3.i.i.i.i105.i = call i8* @calloc( i32 15, i32 1 )		; <i8*> [#uses=1]
-	%tmp1.i108.i = getelementptr [100 x i8*]* @_C_cmds, i32 0, i32 0		; <i8**> [#uses=1]
+	%tmp1.i108.i = getelementptr [100 x i8*], [100 x i8*]* @_C_cmds, i32 0, i32 0		; <i8**> [#uses=1]
 	store i8* %tmp3.i.i.i.i105.i, i8** %tmp1.i108.i, align 4
-	%tmp.i91.i = load i32* @_C_nextcmd, align 4		; <i32> [#uses=1]
+	%tmp.i91.i = load i32, i32* @_C_nextcmd, align 4		; <i32> [#uses=1]
 	store i32 0, i32* @_C_nextcmd, align 4
 	%tmp3.i.i.i.i95.i = call i8* @calloc( i32 15, i32 1 )		; <i8*> [#uses=1]
-	%tmp1.i98.i = getelementptr [100 x i8*]* @_C_cmds, i32 0, i32 %tmp.i91.i		; <i8**> [#uses=1]
+	%tmp1.i98.i = getelementptr [100 x i8*], [100 x i8*]* @_C_cmds, i32 0, i32 %tmp.i91.i		; <i8**> [#uses=1]
 	store i8* %tmp3.i.i.i.i95.i, i8** %tmp1.i98.i, align 4
 	br label %cond_next212.i
 
@@ -77,8 +77,8 @@ cond_next212.i:		; preds = %cond_next212.i, %cond_next212.i, %cond_next212.i, %c
 	%max_d.3 = phi i32 [ -1, %entry ], [ %max_d.3, %bb30.i ], [ %max_d.3, %bb21.i ], [ %max_d.3, %C_addcmd.exit120.i ], [ 0, %bb192.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ]		; <i32> [#uses=7]
 	%argv_addr.2321.0.i = phi i8** [ %argv, %entry ], [ %tmp214.i, %bb192.i ], [ %tmp214.i, %C_addcmd.exit120.i ], [ %tmp214.i, %bb30.i ], [ %tmp214.i, %bb21.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ]		; <i8**> [#uses=2]
 	%argc_addr.2358.0.i = phi i32 [ %argc, %entry ], [ %tmp205399.i, %bb30.i ], [ 0, %bb21.i ], [ 0, %C_addcmd.exit120.i ], [ 0, %bb192.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ]		; <i32> [#uses=1]
-	%tmp214.i = getelementptr i8** %argv_addr.2321.0.i, i32 1		; <i8**> [#uses=9]
-	%tmp215.i = load i8** %tmp214.i		; <i8*> [#uses=1]
+	%tmp214.i = getelementptr i8*, i8** %argv_addr.2321.0.i, i32 1		; <i8**> [#uses=9]
+	%tmp215.i = load i8*, i8** %tmp214.i		; <i8*> [#uses=1]
 	%tmp1314.i = sext i8 0 to i32		; <i32> [#uses=1]
 	switch i32 %tmp1314.i, label %bb192.i [
 		 i32 76, label %C_addcmd.exit120.i
diff --git a/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll b/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll
index 3754db01fdd1..989410552f3f 100644
--- a/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll
+++ b/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll
@@ -10,7 +10,7 @@
 define i32 @vorbis_staticbook_pack(%struct.static_codebook* %c, %struct.oggpack_buffer* %opb) {
 entry:
 	%opb_addr = alloca %struct.oggpack_buffer*		; <%struct.oggpack_buffer**> [#uses=1]
-	%tmp1 = load %struct.oggpack_buffer** %opb_addr, align 4		; <%struct.oggpack_buffer*> [#uses=1]
+	%tmp1 = load %struct.oggpack_buffer*, %struct.oggpack_buffer** %opb_addr, align 4		; <%struct.oggpack_buffer*> [#uses=1]
 	call void @oggpack_write( %struct.oggpack_buffer* %tmp1, i32 5653314, i32 24 ) nounwind 
 	call void @oggpack_write( %struct.oggpack_buffer* null, i32 0, i32 24 ) nounwind 
 	unreachable
diff --git a/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll b/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll
index 5fbed0da5ce8..03b473a4658a 100644
--- a/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll
+++ b/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll
@@ -8,7 +8,7 @@
 
 define %"struct.kc::impl_ID"* @_ZN2kc18f_typeofunpsubtermEPNS_15impl_unpsubtermEPNS_7impl_IDE(%"struct.kc::impl_Ccode_option"* %a_unpsubterm, %"struct.kc::impl_ID"* %a_operator) {
 entry:
-	%tmp8 = getelementptr %"struct.kc::impl_Ccode_option"* %a_unpsubterm, i32 0, i32 0, i32 0		; <i32 (...)***> [#uses=0]
+	%tmp8 = getelementptr %"struct.kc::impl_Ccode_option", %"struct.kc::impl_Ccode_option"* %a_unpsubterm, i32 0, i32 0, i32 0		; <i32 (...)***> [#uses=0]
 	br i1 false, label %bb41, label %bb55
 
 bb41:		; preds = %entry
diff --git a/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll b/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll
index dabe62003d9f..b0a50a49a76d 100644
--- a/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll
+++ b/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll
@@ -4,7 +4,7 @@ define i32 @main(i32 %argc, i8** %argv) {
 entry:
 	br label %bb1
 bb1:		; preds = %entry
-	%tmp3.i.i = load i8* null, align 1		; <i8> [#uses=1]
+	%tmp3.i.i = load i8, i8* null, align 1		; <i8> [#uses=1]
 	%tmp4.i.i = icmp slt i8 %tmp3.i.i, 0		; <i1> [#uses=1]
 	br i1 %tmp4.i.i, label %bb2, label %bb3
 bb2:		; preds = %bb1
diff --git a/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll b/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll
index 94c562bf0129..753f9e3d1331 100644
--- a/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll
+++ b/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll
@@ -11,9 +11,9 @@ bb74.i:		; preds = %bb88.i, %bb74.i, %entry
 bb88.i:		; preds = %bb74.i
 	br i1 false, label %mandel.exit, label %bb74.i
 mandel.exit:		; preds = %bb88.i
-	%tmp2 = load volatile double* getelementptr ({ double, double }* @accum, i32 0, i32 0), align 8		; <double> [#uses=1]
+	%tmp2 = load volatile double, double* getelementptr ({ double, double }, { double, double }* @accum, i32 0, i32 0), align 8		; <double> [#uses=1]
 	%tmp23 = fptosi double %tmp2 to i32		; <i32> [#uses=1]
-	%tmp5 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i32 %tmp23 )		; <i32> [#uses=0]
+	%tmp5 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %tmp23 )		; <i32> [#uses=0]
 	ret i32 0
 }
 
diff --git a/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll b/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll
index 6b39a76d0d19..4b1aa19ef067 100644
--- a/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll
+++ b/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll
@@ -46,7 +46,7 @@ bb17.i:		; preds = %cond_next119.i
 cond_true53.i:		; preds = %bb17.i
 	ret { i16, %struct.rnode* }* null
 cond_false99.i:		; preds = %bb17.i
-        %malloccall = tail call i8* @malloc(i32 trunc (i64 mul nuw (i64 ptrtoint (i1** getelementptr (i1** null, i32 1) to i64), i64 2) to i32))
+        %malloccall = tail call i8* @malloc(i32 trunc (i64 mul nuw (i64 ptrtoint (i1** getelementptr (i1*, i1** null, i32 1) to i64), i64 2) to i32))
         %tmp106.i = bitcast i8* %malloccall to %struct.ch_set*
 	br i1 false, label %bb126.i, label %cond_next119.i
 cond_next119.i:		; preds = %cond_false99.i, %bb42
diff --git a/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll b/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll
index c9a8a67ac5f9..1ededa3c3877 100644
--- a/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll
+++ b/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll
@@ -24,7 +24,7 @@ define void @main(i32 %argc, i8** %argv) noreturn  {
 entry:
 	br i1 false, label %cond_next48, label %cond_false674
 cond_next48:		; preds = %entry
-	%tmp61 = call %struct.FILE* @fopen( i8* null, i8* getelementptr ([2 x i8]* @.str127, i32 0, i32 0) )		; <%struct.FILE*> [#uses=2]
+	%tmp61 = call %struct.FILE* @fopen( i8* null, i8* getelementptr ([2 x i8], [2 x i8]* @.str127, i32 0, i32 0) )		; <%struct.FILE*> [#uses=2]
 	br i1 false, label %bb220.i.i.i, label %bb62.preheader.i.i.i
 bb62.preheader.i.i.i:		; preds = %cond_next48
 	ret void
@@ -53,11 +53,11 @@ bb177.i393.i:		; preds = %bb40.i.i
 bb192.i.i:		; preds = %bb177.i393.i
 	ret void
 cond_false373.i.i:		; preds = %bb.i350.i
-	%tmp376.i.i = call i32 @strcmp( i8* null, i8* getelementptr ([9 x i8]* @.str8115, i32 0, i32 0) )		; <i32> [#uses=0]
+	%tmp376.i.i = call i32 @strcmp( i8* null, i8* getelementptr ([9 x i8], [9 x i8]* @.str8115, i32 0, i32 0) )		; <i32> [#uses=0]
 	br i1 false, label %cond_true380.i.i, label %cond_next602.i.i
 cond_true380.i.i:		; preds = %cond_false373.i.i
 	%tmp394.i418.i = add i32 %cell.0.i.i, 1		; <i32> [#uses=1]
-	%tmp397.i420.i = load %struct.cellbox** null, align 4		; <%struct.cellbox*> [#uses=1]
+	%tmp397.i420.i = load %struct.cellbox*, %struct.cellbox** null, align 4		; <%struct.cellbox*> [#uses=1]
 	br label %bb398.i.i
 bb398.i.i:		; preds = %bb398.i.i, %cond_true380.i.i
 	br i1 false, label %bb414.i.i, label %bb398.i.i
@@ -73,10 +73,10 @@ bb609.i.i:		; preds = %cond_next602.i.i
 	br label %bb620.i.i
 bb620.i.i:		; preds = %bb620.i.i, %bb609.i.i
 	%indvar166.i465.i = phi i32 [ %indvar.next167.i.i, %bb620.i.i ], [ 0, %bb609.i.i ]		; <i32> [#uses=1]
-	%tmp640.i.i = call i32 (%struct.FILE*, i8*, ...)* @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null )		; <i32> [#uses=0]
-	%tmp648.i.i = load i32* null, align 4		; <i32> [#uses=1]
+	%tmp640.i.i = call i32 (%struct.FILE*, i8*, ...) @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8], [5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null )		; <i32> [#uses=0]
+	%tmp648.i.i = load i32, i32* null, align 4		; <i32> [#uses=1]
 	%tmp650.i468.i = icmp sgt i32 0, %tmp648.i.i		; <i1> [#uses=1]
-	%tmp624.i469.i = call i32 (%struct.FILE*, i8*, ...)* @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null )		; <i32> [#uses=0]
+	%tmp624.i469.i = call i32 (%struct.FILE*, i8*, ...) @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8], [5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null )		; <i32> [#uses=0]
 	%indvar.next167.i.i = add i32 %indvar166.i465.i, 1		; <i32> [#uses=1]
 	br i1 %tmp650.i468.i, label %bb653.i.i.loopexit, label %bb620.i.i
 bb653.i.i.loopexit:		; preds = %bb620.i.i
@@ -108,7 +108,7 @@ declare fastcc i32 @init_outer_loop(%struct.lame_global_flags*, double*, %struct
 
 define fastcc void @outer_loop(%struct.lame_global_flags* %gfp, double* %xr, i32 %targ_bits, double* %best_noise, %struct.III_psy_xmin* %l3_xmin, i32* %l3_enc, %struct.III_scalefac_t* %scalefac, %struct.gr_info* %cod_info, i32 %ch) {
 entry:
-	%cod_info.182 = getelementptr %struct.gr_info* %cod_info, i32 0, i32 1		; <i32*> [#uses=1]
+	%cod_info.182 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 1		; <i32*> [#uses=1]
 	br label %bb
 bb:		; preds = %bb226, %entry
 	%save_cod_info.1.1 = phi i32 [ undef, %entry ], [ %save_cod_info.1.1, %bb226 ]		; <i32> [#uses=2]
@@ -126,7 +126,7 @@ cond_true163:		; preds = %cond_next144
 bb.i53:		; preds = %cond_true163
 	ret void
 bb34.i:		; preds = %cond_true163
-	%tmp37.i55 = load i32* null, align 4		; <i32> [#uses=1]
+	%tmp37.i55 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	br i1 false, label %bb65.preheader.i, label %bb78.i
 bb65.preheader.i:		; preds = %bb34.i
 	br label %bb65.outer.us.i
@@ -148,16 +148,16 @@ bb226.backedge.i:		; preds = %cond_next215.i, %bb151.i
 bb155.i:		; preds = %cond_next215.i, %bb151.i
 	%indvar90.i = phi i32 [ %indvar.next91.i, %cond_next215.i ], [ 0, %bb151.i ]		; <i32> [#uses=2]
 	%sfb.3.reg2mem.0.i = add i32 %indvar90.i, %tmp37.i55		; <i32> [#uses=4]
-	%tmp161.i = getelementptr [4 x [21 x double]]* null, i32 0, i32 %tmp15747.i, i32 %sfb.3.reg2mem.0.i		; <double*> [#uses=1]
-	%tmp162.i74 = load double* %tmp161.i, align 4		; <double> [#uses=0]
+	%tmp161.i = getelementptr [4 x [21 x double]], [4 x [21 x double]]* null, i32 0, i32 %tmp15747.i, i32 %sfb.3.reg2mem.0.i		; <double*> [#uses=1]
+	%tmp162.i74 = load double, double* %tmp161.i, align 4		; <double> [#uses=0]
 	br i1 false, label %cond_true167.i, label %cond_next215.i
 cond_true167.i:		; preds = %bb155.i
-	%tmp173.i = getelementptr %struct.III_scalefac_t* null, i32 0, i32 1, i32 %sfb.3.reg2mem.0.i, i32 %i.154.i		; <i32*> [#uses=1]
+	%tmp173.i = getelementptr %struct.III_scalefac_t, %struct.III_scalefac_t* null, i32 0, i32 1, i32 %sfb.3.reg2mem.0.i, i32 %i.154.i		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp173.i, align 4
-	%tmp182.1.i = getelementptr [14 x i32]* @scalefac_band.1, i32 0, i32 %sfb.3.reg2mem.0.i		; <i32*> [#uses=0]
+	%tmp182.1.i = getelementptr [14 x i32], [14 x i32]* @scalefac_band.1, i32 0, i32 %sfb.3.reg2mem.0.i		; <i32*> [#uses=0]
 	%tmp185.i78 = add i32 %sfb.3.reg2mem.0.i, 1		; <i32> [#uses=1]
-	%tmp187.1.i = getelementptr [14 x i32]* @scalefac_band.1, i32 0, i32 %tmp185.i78		; <i32*> [#uses=1]
-	%tmp188.i = load i32* %tmp187.1.i, align 4		; <i32> [#uses=1]
+	%tmp187.1.i = getelementptr [14 x i32], [14 x i32]* @scalefac_band.1, i32 0, i32 %tmp185.i78		; <i32*> [#uses=1]
+	%tmp188.i = load i32, i32* %tmp187.1.i, align 4		; <i32> [#uses=1]
 	%tmp21153.i = icmp slt i32 0, %tmp188.i		; <i1> [#uses=1]
 	br i1 %tmp21153.i, label %bb190.preheader.i, label %cond_next215.i
 bb190.preheader.i:		; preds = %cond_true167.i
@@ -190,9 +190,9 @@ bb231:		; preds = %bb226
 
 define fastcc void @outer_loop2(%struct.lame_global_flags* %gfp, double* %xr, i32 %targ_bits, double* %best_noise, %struct.III_psy_xmin* %l3_xmin, i32* %l3_enc, %struct.III_scalefac_t* %scalefac, %struct.gr_info* %cod_info, i32 %ch) {
 entry:
-	%cod_info.20128.1 = getelementptr %struct.gr_info* %cod_info, i32 0, i32 20, i32 1		; <i32*> [#uses=1]
-	%cod_info.20128.2 = getelementptr %struct.gr_info* %cod_info, i32 0, i32 20, i32 2		; <i32*> [#uses=1]
-	%cod_info.20128.3 = getelementptr %struct.gr_info* %cod_info, i32 0, i32 20, i32 3		; <i32*> [#uses=1]
+	%cod_info.20128.1 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 20, i32 1		; <i32*> [#uses=1]
+	%cod_info.20128.2 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 20, i32 2		; <i32*> [#uses=1]
+	%cod_info.20128.3 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 20, i32 3		; <i32*> [#uses=1]
 	br label %bb
 bb:		; preds = %bb226, %entry
 	%save_cod_info.19.1 = phi i32* [ undef, %entry ], [ %save_cod_info.19.0, %bb226 ]		; <i32*> [#uses=1]
@@ -224,7 +224,7 @@ cond_next144:		; preds = %cond_next104, %bb
 	%over.1 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ]		; <i32> [#uses=1]
 	%best_over.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ]		; <i32> [#uses=1]
 	%notdone.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ]		; <i32> [#uses=1]
-	%tmp147 = load i32* null, align 4		; <i32> [#uses=1]
+	%tmp147 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	%tmp148 = icmp eq i32 %tmp147, 0		; <i1> [#uses=1]
 	%tmp153 = icmp eq i32 %over.1, 0		; <i1> [#uses=1]
 	%bothcond = and i1 %tmp148, %tmp153		; <i1> [#uses=1]
diff --git a/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll b/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll
index 71aa6037a137..85ef8302a18a 100644
--- a/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll
+++ b/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll
@@ -21,14 +21,14 @@ entry:
 	br i1 false, label %init_orig_buffers.exit, label %cond_true.i29
 
 cond_true.i29:		; preds = %entry
-	%tmp17.i = load i32* getelementptr (%struct.ImageParameters* @images, i32 0, i32 20), align 8		; <i32> [#uses=1]
-	%tmp20.i27 = load i32* getelementptr (%struct.ImageParameters* @images, i32 0, i32 16), align 8		; <i32> [#uses=1]
+	%tmp17.i = load i32, i32* getelementptr (%struct.ImageParameters, %struct.ImageParameters* @images, i32 0, i32 20), align 8		; <i32> [#uses=1]
+	%tmp20.i27 = load i32, i32* getelementptr (%struct.ImageParameters, %struct.ImageParameters* @images, i32 0, i32 16), align 8		; <i32> [#uses=1]
 	%tmp8.i.i = select i1 false, i32 1, i32 0		; <i32> [#uses=1]
 	br label %bb.i8.us.i
 
 bb.i8.us.i:		; preds = %get_mem2Dpel.exit.i.us.i, %cond_true.i29
 	%j.04.i.us.i = phi i32 [ %indvar.next39.i, %get_mem2Dpel.exit.i.us.i ], [ 0, %cond_true.i29 ]		; <i32> [#uses=2]
-	%tmp13.i.us.i = getelementptr i16*** null, i32 %j.04.i.us.i		; <i16***> [#uses=0]
+	%tmp13.i.us.i = getelementptr i16**, i16*** null, i32 %j.04.i.us.i		; <i16***> [#uses=0]
 	%tmp15.i.i.us.i = tail call i8* @calloc( i32 0, i32 2 )		; <i8*> [#uses=0]
 	store i16* null, i16** null, align 4
 	br label %bb.i.i.us.i
diff --git a/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll b/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll
index aa61d86e1389..3d69e4fefbc2 100644
--- a/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll
+++ b/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll
@@ -9,7 +9,7 @@ declare fastcc i32 @get_mem2Dint(i32***, i32, i32)
 
 define fastcc void @init_global_buffers() nounwind {
 entry:
-	%tmp151 = tail call fastcc i32 @get_mem2Dint( i32*** getelementptr (%struct.Decoders* @decoders, i32 0, i32 0), i32 16, i32 16 )		; <i32> [#uses=1]
+	%tmp151 = tail call fastcc i32 @get_mem2Dint( i32*** getelementptr (%struct.Decoders, %struct.Decoders* @decoders, i32 0, i32 0), i32 16, i32 16 )		; <i32> [#uses=1]
 	%tmp158 = tail call i8* @calloc( i32 0, i32 4 )		; <i8*> [#uses=0]
 	br i1 false, label %cond_true166, label %bb190.preheader
 
diff --git a/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll b/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll
index e86bc1ba5ccc..cf98d7f91df0 100644
--- a/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll
+++ b/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll
@@ -4,6 +4,6 @@
 define void @main({ i32 }*) {
 entry:
 	%sret1 = alloca { i32 }		; <{ i32 }*> [#uses=1]
-	load { i32 }* %sret1		; <{ i32 }>:1 [#uses=0]
+	load { i32 }, { i32 }* %sret1		; <{ i32 }>:1 [#uses=0]
 	ret void
 }
diff --git a/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll b/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll
index adb011277604..dfbbeb9968c4 100644
--- a/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll
+++ b/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll
@@ -8,6 +8,6 @@
 
 define i32 @__gcov_close() nounwind {
 entry:
-	load i32* getelementptr (%struct.__gcov_var* @__gcov_var, i32 0, i32 5), align 4		; <i32>:0 [#uses=1]
+	load i32, i32* getelementptr (%struct.__gcov_var, %struct.__gcov_var* @__gcov_var, i32 0, i32 5), align 4		; <i32>:0 [#uses=1]
 	ret i32 %0
 }
diff --git a/test/CodeGen/ARM/2009-02-16-SpillerBug.ll b/test/CodeGen/ARM/2009-02-16-SpillerBug.ll
index 4c0c59ccfbc6..cad5440bddc9 100644
--- a/test/CodeGen/ARM/2009-02-16-SpillerBug.ll
+++ b/test/CodeGen/ARM/2009-02-16-SpillerBug.ll
@@ -81,13 +81,13 @@ bb244:		; preds = %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122
 	br i1 %0, label %bb435, label %bb433
 
 bb394:		; preds = %bb122
-	call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 3, i8* getelementptr ([23 x i8]* @"\01LC13423", i32 0, i32 0), i32 0, %struct.FILE_POS* @no_file_pos, i8* getelementptr ([13 x i8]* @"\01LC18972", i32 0, i32 0), i8* null) nounwind
+	call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...) @Error(i32 1, i32 3, i8* getelementptr ([23 x i8], [23 x i8]* @"\01LC13423", i32 0, i32 0), i32 0, %struct.FILE_POS* @no_file_pos, i8* getelementptr ([13 x i8], [13 x i8]* @"\01LC18972", i32 0, i32 0), i8* null) nounwind
 	br label %bb396
 
 bb396:		; preds = %bb394, %bb131, %bb122, %bb122, %bb122, %bb122, %RESUME
 	%stop_link.3 = phi %struct.rec* [ null, %RESUME ], [ %stop_link.3, %bb394 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %link.1, %bb131 ]		; <%struct.rec*> [#uses=7]
 	%headers_seen.1 = phi i32 [ 0, %RESUME ], [ %headers_seen.1, %bb394 ], [ 1, %bb122 ], [ 1, %bb122 ], [ 1, %bb122 ], [ 1, %bb122 ], [ %headers_seen.1, %bb131 ]		; <i32> [#uses=2]
-	%link.1 = load %struct.rec** null		; <%struct.rec*> [#uses=2]
+	%link.1 = load %struct.rec*, %struct.rec** null		; <%struct.rec*> [#uses=2]
 	%1 = icmp eq %struct.rec* %link.1, %hd		; <i1> [#uses=1]
 	br i1 %1, label %bb398, label %bb122
 
diff --git a/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll b/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll
index a48f0033acc8..a14589fa47d8 100644
--- a/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll
+++ b/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll
@@ -15,6 +15,6 @@ entry:
 	br label %return
 
 return:		; preds = %entry
-	%2 = load i32* %retval		; <i32> [#uses=1]
+	%2 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %2
 }
diff --git a/test/CodeGen/ARM/2009-02-27-SpillerBug.ll b/test/CodeGen/ARM/2009-02-27-SpillerBug.ll
index bc5e6023409f..d9ec4d28c5d7 100644
--- a/test/CodeGen/ARM/2009-02-27-SpillerBug.ll
+++ b/test/CodeGen/ARM/2009-02-27-SpillerBug.ll
@@ -28,12 +28,12 @@ bb53:		; preds = %bb52
 	br i1 %phitmp, label %bb55, label %bb52
 
 bb55:		; preds = %bb53
-	%4 = load double* @a, align 4		; <double> [#uses=10]
+	%4 = load double, double* @a, align 4		; <double> [#uses=10]
 	%5 = fadd double %4, 0.000000e+00		; <double> [#uses=16]
 	%6 = fcmp ogt double %k.4, 0.000000e+00		; <i1> [#uses=1]
 	%.pn404 = fmul double %4, %4		; <double> [#uses=4]
 	%.pn402 = fmul double %5, %5		; <double> [#uses=5]
-	%.pn165.in = load double* @N		; <double> [#uses=5]
+	%.pn165.in = load double, double* @N		; <double> [#uses=5]
 	%.pn198 = fmul double 0.000000e+00, %5		; <double> [#uses=1]
 	%.pn185 = fsub double -0.000000e+00, 0.000000e+00		; <double> [#uses=1]
 	%.pn147 = fsub double -0.000000e+00, 0.000000e+00		; <double> [#uses=1]
diff --git a/test/CodeGen/ARM/2009-03-07-SpillerBug.ll b/test/CodeGen/ARM/2009-03-07-SpillerBug.ll
index 377bbd211752..567400318ee0 100644
--- a/test/CodeGen/ARM/2009-03-07-SpillerBug.ll
+++ b/test/CodeGen/ARM/2009-03-07-SpillerBug.ll
@@ -42,7 +42,7 @@ bb3:                                              ; preds = %entry
   %17 = fdiv double %16, %0
   %18 = fadd double 0.000000e+00, %17
   %19 = call double @acos(double %18) nounwind readonly
-  %20 = load double* null, align 4
+  %20 = load double, double* null, align 4
   %21 = fmul double %20, 0x401921FB54442D18
   %22 = call double @sin(double %19) nounwind readonly
   %23 = fmul double %22, 0.000000e+00
diff --git a/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll b/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll
index 7bb1429872b9..a9d5480e72c9 100644
--- a/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll
+++ b/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll
@@ -6,7 +6,7 @@
 
 define fastcc %struct.node_t* @_ZL6createP6node_tii3v_tS1_d(%struct.node_t* %n, i32 %lvl, i32 %dist, i64 %c.0.0, i64 %c.0.1, i64 %c.0.2, i64 %d.0.0, i64 %d.0.1, i64 %d.0.2, double %r) nounwind {
 entry:
-	%0 = getelementptr %struct.node_t* %n, i32 0, i32 1		; <%struct.hit_t*> [#uses=1]
+	%0 = getelementptr %struct.node_t, %struct.node_t* %n, i32 0, i32 1		; <%struct.hit_t*> [#uses=1]
 	%1 = bitcast %struct.hit_t* %0 to i256*		; <i256*> [#uses=1]
 	store i256 0, i256* %1, align 4
 	unreachable
diff --git a/test/CodeGen/ARM/2009-04-06-AsmModifier.ll b/test/CodeGen/ARM/2009-04-06-AsmModifier.ll
index e90c5b322db7..bc7dbd4f6953 100644
--- a/test/CodeGen/ARM/2009-04-06-AsmModifier.ll
+++ b/test/CodeGen/ARM/2009-04-06-AsmModifier.ll
@@ -8,14 +8,14 @@ entry:
 	store i32 0, i32* %retval
 	%res = alloca i32		; <i32*> [#uses=0]
 	%fh = alloca i32		; <i32*> [#uses=1]
-	%1 = load i32* %fh		; <i32> [#uses=1]
-	%2 = load i32* %ptr		; <i32> [#uses=1]
+	%1 = load i32, i32* %fh		; <i32> [#uses=1]
+	%2 = load i32, i32* %ptr		; <i32> [#uses=1]
 	%3 = call i32 asm "mov r0, $2; mov r1, $3; swi ${1:a}; mov $0, r0", "=r,i,r,r,~{r0},~{r1}"(i32 107, i32 %1, i32 %2) nounwind		; <i32> [#uses=1]
         store i32 %3, i32* %retval
 	br label %return
 
 return:		; preds = %entry
-	%4 = load i32* %retval		; <i32> [#uses=1]
+	%4 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %4
 }
 
diff --git a/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll b/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll
index ade6a10afef6..edeae9b88bce 100644
--- a/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll
+++ b/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll
@@ -8,11 +8,11 @@ entry:
 	%b = alloca { double, double }		; <{ double, double }*> [#uses=1]
 	store { i32, { double, double }* } %d_arg, { i32, { double, double }* }* %d
 	store i32 %x_arg, i32* %x
-	%tmp = load i32* %x		; <i32> [#uses=1]
-	%tmp1 = getelementptr { i32, { double, double }* }* %d, i32 0, i32 1		; <{ double, double }**> [#uses=1]
-	%.ptr = load { double, double }** %tmp1		; <{ double, double }*> [#uses=1]
-	%tmp2 = getelementptr { double, double }* %.ptr, i32 %tmp		; <{ double, double }*> [#uses=1]
-	%tmp3 = load { double, double }* %tmp2		; <{ double, double }> [#uses=1]
+	%tmp = load i32, i32* %x		; <i32> [#uses=1]
+	%tmp1 = getelementptr { i32, { double, double }* }, { i32, { double, double }* }* %d, i32 0, i32 1		; <{ double, double }**> [#uses=1]
+	%.ptr = load { double, double }*, { double, double }** %tmp1		; <{ double, double }*> [#uses=1]
+	%tmp2 = getelementptr { double, double }, { double, double }* %.ptr, i32 %tmp		; <{ double, double }*> [#uses=1]
+	%tmp3 = load { double, double }, { double, double }* %tmp2		; <{ double, double }> [#uses=1]
 	store { double, double } %tmp3, { double, double }* %b
 	ret void
 }
diff --git a/test/CodeGen/ARM/2009-04-08-FREM.ll b/test/CodeGen/ARM/2009-04-08-FREM.ll
index 606c6b1471b4..e0f9485888d9 100644
--- a/test/CodeGen/ARM/2009-04-08-FREM.ll
+++ b/test/CodeGen/ARM/2009-04-08-FREM.ll
@@ -4,6 +4,6 @@ declare i32 @printf(i8*, ...)
 
 define i32 @main() {
 	%rem_r = frem double 0.000000e+00, 0.000000e+00		; <double> [#uses=1]
-	%1 = call i32 (i8*, ...)* @printf(i8* null, double %rem_r)		; <i32> [#uses=0]
+	%1 = call i32 (i8*, ...) @printf(i8* null, double %rem_r)		; <i32> [#uses=0]
 	ret i32 0
 }
diff --git a/test/CodeGen/ARM/2009-04-08-FloatUndef.ll b/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
index 9e32e05b040b..949e1072b2b6 100644
--- a/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
+++ b/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
@@ -2,7 +2,7 @@
 
 define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>* %CONST) {
 entry:
-	%input2 = load <4 x float>* null, align 16		; <<4 x float>> [#uses=2]
+	%input2 = load <4 x float>, <4 x float>* null, align 16		; <<4 x float>> [#uses=2]
 	%shuffle7 = shufflevector <4 x float> %input2, <4 x float> <float 0.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>		; <<4 x float>> [#uses=1]
 	%mul1 = fmul <4 x float> %shuffle7, zeroinitializer		; <<4 x float>> [#uses=1]
 	%add2 = fadd <4 x float> %mul1, %input2		; <<4 x float>> [#uses=1]
diff --git a/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll b/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll
index 5b1746301f4e..f2532d798f83 100644
--- a/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll
+++ b/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll
@@ -4,7 +4,7 @@
 define void @foo(...) nounwind {
 entry:
 	%rr = alloca i32		; <i32*> [#uses=2]
-	%0 = load i32* %rr		; <i32> [#uses=1]
+	%0 = load i32, i32* %rr		; <i32> [#uses=1]
 	%1 = call i32 asm "nop", "=r,0"(i32 %0) nounwind		; <i32> [#uses=1]
 	store i32 %1, i32* %rr
 	br label %return
diff --git a/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll b/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll
index 524b5ebddc0a..ac641f99dbf9 100644
--- a/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll
+++ b/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll
@@ -5,7 +5,7 @@
 define i16 @fn16(i16 %arg0.0, <2 x i16> %arg1, i16 %arg2.0) nounwind {
 entry:
 	store <2 x i16> %arg1, <2 x i16>* null
-	%0 = call i32 (i8*, ...)* @printf(i8* getelementptr ([30 x i8]* @.str, i32 0, i32 0), i32 0) nounwind		; <i32> [#uses=0]
+	%0 = call i32 (i8*, ...) @printf(i8* getelementptr ([30 x i8], [30 x i8]* @.str, i32 0, i32 0), i32 0) nounwind		; <i32> [#uses=0]
 	ret i16 0
 }
 
diff --git a/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll b/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll
index 2bc7df028534..ae005dbf4b13 100644
--- a/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll
+++ b/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll
@@ -19,8 +19,8 @@ bb1:		; preds = %bb
 
 bb3:		; preds = %bb1, %bb
 	%iftmp.0.0 = phi i32 [ 0, %bb1 ], [ -1, %bb ]		; <i32> [#uses=1]
-	%1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([7 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 %iftmp.0.0) nounwind		; <i32> [#uses=0]
-	%2 = load %struct.List** null, align 4		; <%struct.List*> [#uses=2]
+	%1 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([7 x i8], [7 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 %iftmp.0.0) nounwind		; <i32> [#uses=0]
+	%2 = load %struct.List*, %struct.List** null, align 4		; <%struct.List*> [#uses=2]
 	%phitmp = icmp eq %struct.List* %2, null		; <i1> [#uses=1]
 	br i1 %phitmp, label %bb5, label %bb
 
diff --git a/test/CodeGen/ARM/2009-06-02-ISelCrash.ll b/test/CodeGen/ARM/2009-06-02-ISelCrash.ll
index 403e3f6509f3..7bbb8090c849 100644
--- a/test/CodeGen/ARM/2009-06-02-ISelCrash.ll
+++ b/test/CodeGen/ARM/2009-06-02-ISelCrash.ll
@@ -57,6 +57,6 @@ Fft.exit.i:		; preds = %bb7.i.i
 	br i1 undef, label %bb5.i, label %bb1.outer2.i.i.outer
 
 bb5.i:		; preds = %Fft.exit.i
-	%0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([15 x i8]* @"\01LC", i32 0, i32 0), double undef, double undef) nounwind		; <i32> [#uses=0]
+	%0 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([15 x i8], [15 x i8]* @"\01LC", i32 0, i32 0), double undef, double undef) nounwind		; <i32> [#uses=0]
 	unreachable
 }
diff --git a/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll b/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll
index 98e002302558..17beb3c25947 100644
--- a/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll
+++ b/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll
@@ -136,7 +136,7 @@ bb138:		; preds = %bb77
 	br label %bb141
 
 bb139:		; preds = %bb141
-	%scevgep441442881 = load i16* undef		; <i16> [#uses=1]
+	%scevgep441442881 = load i16, i16* undef		; <i16> [#uses=1]
 	%1 = icmp ugt i16 %scevgep441442881, %0		; <i1> [#uses=1]
 	br i1 %1, label %bb141, label %bb142
 
diff --git a/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll b/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll
index 7e9b066984f9..4ab54c2e8faf 100644
--- a/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll
+++ b/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll
@@ -5,9 +5,9 @@
 
 define void @simplify_unary_real(i8* nocapture %p) nounwind {
 entry:
-	%tmp121 = load i64* null, align 4		; <i64> [#uses=1]
-	%0 = getelementptr %struct.rtx_def* null, i32 0, i32 3, i32 3, i32 0		; <i64*> [#uses=1]
-	%tmp122 = load i64* %0, align 4		; <i64> [#uses=1]
+	%tmp121 = load i64, i64* null, align 4		; <i64> [#uses=1]
+	%0 = getelementptr %struct.rtx_def, %struct.rtx_def* null, i32 0, i32 3, i32 3, i32 0		; <i64*> [#uses=1]
+	%tmp122 = load i64, i64* %0, align 4		; <i64> [#uses=1]
 	%1 = zext i64 undef to i192		; <i192> [#uses=2]
 	%2 = zext i64 %tmp121 to i192		; <i192> [#uses=1]
 	%3 = shl i192 %2, 64		; <i192> [#uses=2]
diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll
index 812f0188f19a..e9c4b0335dc0 100644
--- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll
+++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll
@@ -35,26 +35,26 @@ bb10:		; preds = %bb9
 	unreachable
 
 bb11:		; preds = %bb9
-	%0 = load i32* undef, align 4		; <i32> [#uses=2]
+	%0 = load i32, i32* undef, align 4		; <i32> [#uses=2]
 	%1 = add i32 %0, 1		; <i32> [#uses=2]
 	store i32 %1, i32* undef, align 4
-	%2 = load i32* undef, align 4		; <i32> [#uses=1]
+	%2 = load i32, i32* undef, align 4		; <i32> [#uses=1]
 	store i32 %2, i32* @nn, align 4
 	store i32 0, i32* @al_len, align 4
 	store i32 0, i32* @no_mat, align 4
 	store i32 0, i32* @no_mis, align 4
-	%3 = getelementptr i8* %B, i32 %0		; <i8*> [#uses=1]
+	%3 = getelementptr i8, i8* %B, i32 %0		; <i8*> [#uses=1]
 	tail call  void @diff(i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind
 	%4 = sitofp i32 undef to double		; <double> [#uses=1]
 	%5 = fdiv double %4, 1.000000e+01		; <double> [#uses=1]
-	%6 = tail call  i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind		; <i32> [#uses=0]
-	%7 = load i32* @al_len, align 4		; <i32> [#uses=1]
-	%8 = load i32* @no_mat, align 4		; <i32> [#uses=1]
-	%9 = load i32* @no_mis, align 4		; <i32> [#uses=1]
+	%6 = tail call  i32 (i8*, ...) @printf(i8* getelementptr ([29 x i8], [29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind		; <i32> [#uses=0]
+	%7 = load i32, i32* @al_len, align 4		; <i32> [#uses=1]
+	%8 = load i32, i32* @no_mat, align 4		; <i32> [#uses=1]
+	%9 = load i32, i32* @no_mis, align 4		; <i32> [#uses=1]
 	%10 = sub i32 %7, %8		; <i32> [#uses=1]
 	%11 = sub i32 %10, %9		; <i32> [#uses=1]
-	%12 = tail call  i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind		; <i32> [#uses=0]
-	%13 = tail call  i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind		; <i32> [#uses=0]
+	%12 = tail call  i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind		; <i32> [#uses=0]
+	%13 = tail call  i32 (i8*, ...) @printf(i8* getelementptr ([47 x i8], [47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind		; <i32> [#uses=0]
 	br i1 undef, label %bb15, label %bb12
 
 bb12:		; preds = %bb11
diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll
index f5fb97c0ef53..08291e62b65e 100644
--- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll
+++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll
@@ -33,19 +33,19 @@ bb10:		; preds = %bb9
 	unreachable
 
 bb11:		; preds = %bb9
-	%0 = load i32* undef, align 4		; <i32> [#uses=3]
+	%0 = load i32, i32* undef, align 4		; <i32> [#uses=3]
 	%1 = add i32 %0, 1		; <i32> [#uses=2]
 	store i32 %1, i32* undef, align 4
-	%2 = load i32* undef, align 4		; <i32> [#uses=2]
+	%2 = load i32, i32* undef, align 4		; <i32> [#uses=2]
 	%3 = sub i32 %2, %0		; <i32> [#uses=1]
 	store i32 0, i32* @no_mat, align 4
 	store i32 0, i32* @no_mis, align 4
-	%4 = getelementptr i8* %B, i32 %0		; <i8*> [#uses=1]
+	%4 = getelementptr i8, i8* %B, i32 %0		; <i8*> [#uses=1]
 	tail call  void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind
-	%5 = tail call  i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind		; <i32> [#uses=0]
-	%6 = load i32* @no_mis, align 4		; <i32> [#uses=1]
-	%7 = tail call  i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind		; <i32> [#uses=0]
-	%8 = tail call  i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind		; <i32> [#uses=0]
+	%5 = tail call  i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind		; <i32> [#uses=0]
+	%6 = load i32, i32* @no_mis, align 4		; <i32> [#uses=1]
+	%7 = tail call  i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind		; <i32> [#uses=0]
+	%8 = tail call  i32 (i8*, ...) @printf(i8* getelementptr ([47 x i8], [47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind		; <i32> [#uses=0]
 	br i1 undef, label %bb15, label %bb12
 
 bb12:		; preds = %bb11
diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll
index d7e4c90abb18..cf7325ddf895 100644
--- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll
+++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll
@@ -28,7 +28,7 @@ bb11:		; preds = %bb9
 	br i1 undef, label %bb15, label %bb12
 
 bb12:		; preds = %bb11
-	%0 = load i32** @JJ, align 4		; <i32*> [#uses=1]
+	%0 = load i32*, i32** @JJ, align 4		; <i32*> [#uses=1]
 	br label %bb228.i
 
 bb74.i:		; preds = %bb228.i
@@ -84,10 +84,10 @@ bb167.i:		; preds = %bb163.i
 bb168.i:		; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
 	%fi.5.i = phi i32 [ undef, %bb167.i ], [ %ci.910.i, %bb158.i ], [ undef, %bb160.i ], [ %ci.910.i, %bb161.i ], [ undef, %bb163.i ]		; <i32> [#uses=1]
 	%fj.4.i = phi i32 [ undef, %bb167.i ], [ undef, %bb158.i ], [ %fj.515.i, %bb160.i ], [ undef, %bb161.i ], [ %fj.515.i, %bb163.i ]		; <i32> [#uses=2]
-	%scevgep88.i = getelementptr i32* null, i32 %i.121.i		; <i32*> [#uses=3]
-	%4 = load i32* %scevgep88.i, align 4		; <i32> [#uses=2]
-	%scevgep89.i = getelementptr i32* %0, i32 %i.121.i		; <i32*> [#uses=3]
-	%5 = load i32* %scevgep89.i, align 4		; <i32> [#uses=1]
+	%scevgep88.i = getelementptr i32, i32* null, i32 %i.121.i		; <i32*> [#uses=3]
+	%4 = load i32, i32* %scevgep88.i, align 4		; <i32> [#uses=2]
+	%scevgep89.i = getelementptr i32, i32* %0, i32 %i.121.i		; <i32*> [#uses=3]
+	%5 = load i32, i32* %scevgep89.i, align 4		; <i32> [#uses=1]
 	%ci.10.i = select i1 undef, i32 %pi.316.i, i32 %i.121.i		; <i32> [#uses=0]
 	%cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef		; <i32> [#uses=0]
 	%6 = icmp slt i32 undef, 0		; <i1> [#uses=3]
@@ -95,8 +95,8 @@ bb168.i:		; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
 	%cj.11.i100 = select i1 %6, i32 %fj.4.i, i32 %5		; <i32> [#uses=1]
 	%c.14.i = select i1 %6, i32 0, i32 undef		; <i32> [#uses=2]
 	store i32 %c.14.i, i32* undef, align 4
-	%7 = load i32* %scevgep88.i, align 4		; <i32> [#uses=1]
-	%8 = load i32* %scevgep89.i, align 4		; <i32> [#uses=1]
+	%7 = load i32, i32* %scevgep88.i, align 4		; <i32> [#uses=1]
+	%8 = load i32, i32* %scevgep89.i, align 4		; <i32> [#uses=1]
 	store i32 %ci.12.i, i32* %scevgep88.i, align 4
 	store i32 %cj.11.i100, i32* %scevgep89.i, align 4
 	store i32 %4, i32* undef, align 4
diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll
index 77c133a80f95..203608ac1d40 100644
--- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll
+++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll
@@ -22,7 +22,7 @@ bb6:		; preds = %bb6, %bb5
 	br i1 undef, label %bb8, label %bb6
 
 bb8:		; preds = %bb6, %bb5
-	%0 = load i8** @name1, align 4		; <i8*> [#uses=0]
+	%0 = load i8*, i8** @name1, align 4		; <i8*> [#uses=0]
 	br label %bb15
 
 bb9:		; preds = %bb15
@@ -33,15 +33,15 @@ bb10:		; preds = %bb9
 
 bb11:		; preds = %bb9
 	store i32 0, i32* @no_mis, align 4
-	%1 = getelementptr i8* %A, i32 0		; <i8*> [#uses=1]
-	%2 = getelementptr i8* %B, i32 0		; <i8*> [#uses=1]
+	%1 = getelementptr i8, i8* %A, i32 0		; <i8*> [#uses=1]
+	%2 = getelementptr i8, i8* %B, i32 0		; <i8*> [#uses=1]
 	tail call  void @diff(i8* %1, i8* %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind
 	br i1 undef, label %bb15, label %bb12
 
 bb12:		; preds = %bb11
-	%3 = load i32** @II, align 4		; <i32*> [#uses=1]
-	%4 = load i32* @r, align 4		; <i32> [#uses=1]
-	%5 = load i32* @qr, align 4		; <i32> [#uses=1]
+	%3 = load i32*, i32** @II, align 4		; <i32*> [#uses=1]
+	%4 = load i32, i32* @r, align 4		; <i32> [#uses=1]
+	%5 = load i32, i32* @qr, align 4		; <i32> [#uses=1]
 	br label %bb228.i
 
 bb74.i:		; preds = %bb228.i
@@ -95,12 +95,12 @@ bb168.i:		; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
 	%fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ]		; <i32> [#uses=2]
 	%fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ]		; <i32> [#uses=2]
 	%f.5.i = phi i32 [ %7, %bb167.i ], [ %8, %bb158.i ], [ %7, %bb160.i ], [ %7, %bb161.i ], [ %7, %bb163.i ]		; <i32> [#uses=2]
-	%scevgep88.i = getelementptr i32* %3, i32 undef		; <i32*> [#uses=1]
+	%scevgep88.i = getelementptr i32, i32* %3, i32 undef		; <i32*> [#uses=1]
 	%ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef		; <i32> [#uses=0]
 	%ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef		; <i32> [#uses=1]
 	%cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef		; <i32> [#uses=1]
 	%c.14.i = select i1 undef, i32 %f.5.i, i32 undef		; <i32> [#uses=1]
-	%10 = load i32* %scevgep88.i, align 4		; <i32> [#uses=1]
+	%10 = load i32, i32* %scevgep88.i, align 4		; <i32> [#uses=1]
 	br i1 undef, label %bb211.i, label %bb218.i
 
 bb211.i:		; preds = %bb168.i
@@ -110,7 +110,7 @@ bb218.i:		; preds = %bb211.i, %bb168.i
 	br i1 undef, label %bb220.i, label %bb158.i
 
 bb220.i:		; preds = %bb218.i, %bb153.i
-	%11 = getelementptr i32* null, i32 %6		; <i32*> [#uses=1]
+	%11 = getelementptr i32, i32* null, i32 %6		; <i32*> [#uses=1]
 	store i32 undef, i32* %11, align 4
 	br i1 undef, label %bb221.i, label %bb228.i
 
diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
index 16f5d1dc150f..b3c91ed3fb0d 100644
--- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
+++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
@@ -28,7 +28,7 @@ bb11:		; preds = %bb9
 	br i1 undef, label %bb15, label %bb12
 
 bb12:		; preds = %bb11
-	%0 = load i32** @XX, align 4		; <i32*> [#uses=0]
+	%0 = load i32*, i32** @XX, align 4		; <i32*> [#uses=0]
 	br label %bb228.i
 
 bb74.i:		; preds = %bb228.i
diff --git a/test/CodeGen/ARM/2009-07-01-CommuteBug.ll b/test/CodeGen/ARM/2009-07-01-CommuteBug.ll
index f0d79ce25c97..55039dd7f57b 100644
--- a/test/CodeGen/ARM/2009-07-01-CommuteBug.ll
+++ b/test/CodeGen/ARM/2009-07-01-CommuteBug.ll
@@ -30,9 +30,9 @@ bb11:		; preds = %bb9
 	br i1 undef, label %bb15, label %bb12
 
 bb12:		; preds = %bb11
-	%0 = load i32** @II, align 4		; <i32*> [#uses=1]
-	%1 = load i32** @JJ, align 4		; <i32*> [#uses=1]
-	%2 = load i32* @qr, align 4		; <i32> [#uses=1]
+	%0 = load i32*, i32** @II, align 4		; <i32*> [#uses=1]
+	%1 = load i32*, i32** @JJ, align 4		; <i32*> [#uses=1]
+	%2 = load i32, i32* @qr, align 4		; <i32> [#uses=1]
 	br label %bb228.i
 
 bb74.i:		; preds = %bb228.i
@@ -90,15 +90,15 @@ bb168.i:		; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
 	%fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ]		; <i32> [#uses=2]
 	%fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ]		; <i32> [#uses=2]
 	%f.5.i = phi i32 [ %3, %bb167.i ], [ %4, %bb158.i ], [ %3, %bb160.i ], [ %3, %bb161.i ], [ %3, %bb163.i ]		; <i32> [#uses=2]
-	%scevgep88.i = getelementptr i32* %0, i32 undef		; <i32*> [#uses=2]
-	%scevgep89.i = getelementptr i32* %1, i32 undef		; <i32*> [#uses=2]
+	%scevgep88.i = getelementptr i32, i32* %0, i32 undef		; <i32*> [#uses=2]
+	%scevgep89.i = getelementptr i32, i32* %1, i32 undef		; <i32*> [#uses=2]
 	%ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef		; <i32> [#uses=0]
 	%cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef		; <i32> [#uses=0]
 	%ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef		; <i32> [#uses=2]
 	%cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef		; <i32> [#uses=2]
 	%c.14.i = select i1 undef, i32 %f.5.i, i32 undef		; <i32> [#uses=1]
-	%6 = load i32* %scevgep88.i, align 4		; <i32> [#uses=1]
-	%7 = load i32* %scevgep89.i, align 4		; <i32> [#uses=1]
+	%6 = load i32, i32* %scevgep88.i, align 4		; <i32> [#uses=1]
+	%7 = load i32, i32* %scevgep89.i, align 4		; <i32> [#uses=1]
 	store i32 %ci.12.i, i32* %scevgep88.i, align 4
 	store i32 %cj.11.i100, i32* %scevgep89.i, align 4
 	br i1 undef, label %bb211.i, label %bb218.i
diff --git a/test/CodeGen/ARM/2009-07-18-RewriterBug.ll b/test/CodeGen/ARM/2009-07-18-RewriterBug.ll
index 454fee5c5ae1..2146dd330822 100644
--- a/test/CodeGen/ARM/2009-07-18-RewriterBug.ll
+++ b/test/CodeGen/ARM/2009-07-18-RewriterBug.ll
@@ -16,43 +16,43 @@ entry:
 	br i1 %0, label %bb8, label %bb
 
 bb:		; preds = %entry
-	%1 = getelementptr %struct.VERTEX* %tree, i32 0, i32 2		; <%struct.VERTEX**> [#uses=1]
-	%2 = load %struct.VERTEX** %1, align 4		; <%struct.VERTEX*> [#uses=2]
+	%1 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 2		; <%struct.VERTEX**> [#uses=1]
+	%2 = load %struct.VERTEX*, %struct.VERTEX** %1, align 4		; <%struct.VERTEX*> [#uses=2]
 	%3 = icmp eq %struct.VERTEX* %2, null		; <i1> [#uses=1]
 	br i1 %3, label %bb7, label %bb1.i
 
 bb1.i:		; preds = %bb1.i, %bb
 	%tree_addr.0.i = phi %struct.VERTEX* [ %5, %bb1.i ], [ %tree, %bb ]		; <%struct.VERTEX*> [#uses=3]
-	%4 = getelementptr %struct.VERTEX* %tree_addr.0.i, i32 0, i32 1		; <%struct.VERTEX**> [#uses=1]
-	%5 = load %struct.VERTEX** %4, align 4		; <%struct.VERTEX*> [#uses=2]
+	%4 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree_addr.0.i, i32 0, i32 1		; <%struct.VERTEX**> [#uses=1]
+	%5 = load %struct.VERTEX*, %struct.VERTEX** %4, align 4		; <%struct.VERTEX*> [#uses=2]
 	%6 = icmp eq %struct.VERTEX* %5, null		; <i1> [#uses=1]
 	br i1 %6, label %get_low.exit, label %bb1.i
 
 get_low.exit:		; preds = %bb1.i
 	call  void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delright, %struct.VERTEX* %2, %struct.VERTEX* %extra) nounwind
-	%7 = getelementptr %struct.VERTEX* %tree, i32 0, i32 1		; <%struct.VERTEX**> [#uses=1]
-	%8 = load %struct.VERTEX** %7, align 4		; <%struct.VERTEX*> [#uses=1]
+	%7 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 1		; <%struct.VERTEX**> [#uses=1]
+	%8 = load %struct.VERTEX*, %struct.VERTEX** %7, align 4		; <%struct.VERTEX*> [#uses=1]
 	call  void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delleft, %struct.VERTEX* %8, %struct.VERTEX* %tree) nounwind
-	%9 = getelementptr %struct.EDGE_PAIR* %delleft, i32 0, i32 0		; <%struct.edge_rec**> [#uses=1]
-	%10 = load %struct.edge_rec** %9, align 8		; <%struct.edge_rec*> [#uses=2]
-	%11 = getelementptr %struct.EDGE_PAIR* %delleft, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%12 = load %struct.edge_rec** %11, align 4		; <%struct.edge_rec*> [#uses=1]
-	%13 = getelementptr %struct.EDGE_PAIR* %delright, i32 0, i32 0		; <%struct.edge_rec**> [#uses=1]
-	%14 = load %struct.edge_rec** %13, align 8		; <%struct.edge_rec*> [#uses=1]
-	%15 = getelementptr %struct.EDGE_PAIR* %delright, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%16 = load %struct.edge_rec** %15, align 4		; <%struct.edge_rec*> [#uses=2]
+	%9 = getelementptr %struct.EDGE_PAIR, %struct.EDGE_PAIR* %delleft, i32 0, i32 0		; <%struct.edge_rec**> [#uses=1]
+	%10 = load %struct.edge_rec*, %struct.edge_rec** %9, align 8		; <%struct.edge_rec*> [#uses=2]
+	%11 = getelementptr %struct.EDGE_PAIR, %struct.EDGE_PAIR* %delleft, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%12 = load %struct.edge_rec*, %struct.edge_rec** %11, align 4		; <%struct.edge_rec*> [#uses=1]
+	%13 = getelementptr %struct.EDGE_PAIR, %struct.EDGE_PAIR* %delright, i32 0, i32 0		; <%struct.edge_rec**> [#uses=1]
+	%14 = load %struct.edge_rec*, %struct.edge_rec** %13, align 8		; <%struct.edge_rec*> [#uses=1]
+	%15 = getelementptr %struct.EDGE_PAIR, %struct.EDGE_PAIR* %delright, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%16 = load %struct.edge_rec*, %struct.edge_rec** %15, align 4		; <%struct.edge_rec*> [#uses=2]
 	br label %bb.i
 
 bb.i:		; preds = %bb4.i, %get_low.exit
 	%rdi_addr.0.i = phi %struct.edge_rec* [ %14, %get_low.exit ], [ %72, %bb4.i ]		; <%struct.edge_rec*> [#uses=2]
 	%ldi_addr.1.i = phi %struct.edge_rec* [ %12, %get_low.exit ], [ %ldi_addr.0.i, %bb4.i ]		; <%struct.edge_rec*> [#uses=3]
-	%17 = getelementptr %struct.edge_rec* %rdi_addr.0.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%18 = load %struct.VERTEX** %17, align 4		; <%struct.VERTEX*> [#uses=3]
+	%17 = getelementptr %struct.edge_rec, %struct.edge_rec* %rdi_addr.0.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%18 = load %struct.VERTEX*, %struct.VERTEX** %17, align 4		; <%struct.VERTEX*> [#uses=3]
 	%19 = ptrtoint %struct.edge_rec* %ldi_addr.1.i to i32		; <i32> [#uses=1]
-	%20 = getelementptr %struct.VERTEX* %18, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%21 = load double* %20, align 4		; <double> [#uses=3]
-	%22 = getelementptr %struct.VERTEX* %18, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%23 = load double* %22, align 4		; <double> [#uses=3]
+	%20 = getelementptr %struct.VERTEX, %struct.VERTEX* %18, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%21 = load double, double* %20, align 4		; <double> [#uses=3]
+	%22 = getelementptr %struct.VERTEX, %struct.VERTEX* %18, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%23 = load double, double* %22, align 4		; <double> [#uses=3]
 	br label %bb2.i
 
 bb1.i1:		; preds = %bb2.i
@@ -62,8 +62,8 @@ bb1.i1:		; preds = %bb2.i
 	%27 = and i32 %24, -64		; <i32> [#uses=1]
 	%28 = or i32 %26, %27		; <i32> [#uses=1]
 	%29 = inttoptr i32 %28 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%30 = getelementptr %struct.edge_rec* %29, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%31 = load %struct.edge_rec** %30, align 4		; <%struct.edge_rec*> [#uses=1]
+	%30 = getelementptr %struct.edge_rec, %struct.edge_rec* %29, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%31 = load %struct.edge_rec*, %struct.edge_rec** %30, align 4		; <%struct.edge_rec*> [#uses=1]
 	%32 = ptrtoint %struct.edge_rec* %31 to i32		; <i32> [#uses=2]
 	%33 = add i32 %32, 16		; <i32> [#uses=1]
 	%34 = and i32 %33, 63		; <i32> [#uses=1]
@@ -78,18 +78,18 @@ bb2.i:		; preds = %bb1.i1, %bb.i
 	%ldi_addr.0.i = phi %struct.edge_rec* [ %ldi_addr.1.i, %bb.i ], [ %37, %bb1.i1 ]		; <%struct.edge_rec*> [#uses=4]
 	%.pn6.in.i = xor i32 %.pn6.in.in.i, 32		; <i32> [#uses=1]
 	%.pn6.i = inttoptr i32 %.pn6.in.i to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%t1.0.in.i = getelementptr %struct.edge_rec* %ldi_addr.1.pn.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%t2.0.in.i = getelementptr %struct.edge_rec* %.pn6.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%t1.0.i = load %struct.VERTEX** %t1.0.in.i		; <%struct.VERTEX*> [#uses=2]
-	%t2.0.i = load %struct.VERTEX** %t2.0.in.i		; <%struct.VERTEX*> [#uses=2]
-	%38 = getelementptr %struct.VERTEX* %t1.0.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%39 = load double* %38, align 4		; <double> [#uses=3]
-	%40 = getelementptr %struct.VERTEX* %t1.0.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%41 = load double* %40, align 4		; <double> [#uses=3]
-	%42 = getelementptr %struct.VERTEX* %t2.0.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%43 = load double* %42, align 4		; <double> [#uses=1]
-	%44 = getelementptr %struct.VERTEX* %t2.0.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%45 = load double* %44, align 4		; <double> [#uses=1]
+	%t1.0.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %ldi_addr.1.pn.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%t2.0.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %.pn6.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%t1.0.i = load %struct.VERTEX*, %struct.VERTEX** %t1.0.in.i		; <%struct.VERTEX*> [#uses=2]
+	%t2.0.i = load %struct.VERTEX*, %struct.VERTEX** %t2.0.in.i		; <%struct.VERTEX*> [#uses=2]
+	%38 = getelementptr %struct.VERTEX, %struct.VERTEX* %t1.0.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%39 = load double, double* %38, align 4		; <double> [#uses=3]
+	%40 = getelementptr %struct.VERTEX, %struct.VERTEX* %t1.0.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%41 = load double, double* %40, align 4		; <double> [#uses=3]
+	%42 = getelementptr %struct.VERTEX, %struct.VERTEX* %t2.0.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%43 = load double, double* %42, align 4		; <double> [#uses=1]
+	%44 = getelementptr %struct.VERTEX, %struct.VERTEX* %t2.0.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%45 = load double, double* %44, align 4		; <double> [#uses=1]
 	%46 = fsub double %39, %21		; <double> [#uses=1]
 	%47 = fsub double %45, %23		; <double> [#uses=1]
 	%48 = fmul double %46, %47		; <double> [#uses=1]
@@ -104,12 +104,12 @@ bb3.i:		; preds = %bb2.i
 	%54 = ptrtoint %struct.edge_rec* %rdi_addr.0.i to i32		; <i32> [#uses=1]
 	%55 = xor i32 %54, 32		; <i32> [#uses=3]
 	%56 = inttoptr i32 %55 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
-	%57 = getelementptr %struct.edge_rec* %56, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%58 = load %struct.VERTEX** %57, align 4		; <%struct.VERTEX*> [#uses=2]
-	%59 = getelementptr %struct.VERTEX* %58, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%60 = load double* %59, align 4		; <double> [#uses=1]
-	%61 = getelementptr %struct.VERTEX* %58, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%62 = load double* %61, align 4		; <double> [#uses=1]
+	%57 = getelementptr %struct.edge_rec, %struct.edge_rec* %56, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%58 = load %struct.VERTEX*, %struct.VERTEX** %57, align 4		; <%struct.VERTEX*> [#uses=2]
+	%59 = getelementptr %struct.VERTEX, %struct.VERTEX* %58, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%60 = load double, double* %59, align 4		; <double> [#uses=1]
+	%61 = getelementptr %struct.VERTEX, %struct.VERTEX* %58, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%62 = load double, double* %61, align 4		; <double> [#uses=1]
 	%63 = fsub double %60, %39		; <double> [#uses=1]
 	%64 = fsub double %23, %41		; <double> [#uses=1]
 	%65 = fmul double %63, %64		; <double> [#uses=1]
@@ -121,8 +121,8 @@ bb3.i:		; preds = %bb2.i
 	br i1 %70, label %bb4.i, label %bb5.i
 
 bb4.i:		; preds = %bb3.i
-	%71 = getelementptr %struct.edge_rec* %56, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%72 = load %struct.edge_rec** %71, align 4		; <%struct.edge_rec*> [#uses=1]
+	%71 = getelementptr %struct.edge_rec, %struct.edge_rec* %56, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%72 = load %struct.edge_rec*, %struct.edge_rec** %71, align 4		; <%struct.edge_rec*> [#uses=1]
 	br label %bb.i
 
 bb5.i:		; preds = %bb3.i
@@ -131,110 +131,110 @@ bb5.i:		; preds = %bb3.i
 	%75 = and i32 %55, -64		; <i32> [#uses=1]
 	%76 = or i32 %74, %75		; <i32> [#uses=1]
 	%77 = inttoptr i32 %76 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%78 = getelementptr %struct.edge_rec* %77, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%79 = load %struct.edge_rec** %78, align 4		; <%struct.edge_rec*> [#uses=1]
+	%78 = getelementptr %struct.edge_rec, %struct.edge_rec* %77, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%79 = load %struct.edge_rec*, %struct.edge_rec** %78, align 4		; <%struct.edge_rec*> [#uses=1]
 	%80 = ptrtoint %struct.edge_rec* %79 to i32		; <i32> [#uses=2]
 	%81 = add i32 %80, 16		; <i32> [#uses=1]
 	%82 = and i32 %81, 63		; <i32> [#uses=1]
 	%83 = and i32 %80, -64		; <i32> [#uses=1]
 	%84 = or i32 %82, %83		; <i32> [#uses=1]
 	%85 = inttoptr i32 %84 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%86 = getelementptr %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%87 = load %struct.VERTEX** %86, align 4		; <%struct.VERTEX*> [#uses=1]
+	%86 = getelementptr %struct.edge_rec, %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%87 = load %struct.VERTEX*, %struct.VERTEX** %86, align 4		; <%struct.VERTEX*> [#uses=1]
 	%88 = call  %struct.edge_rec* @alloc_edge() nounwind		; <%struct.edge_rec*> [#uses=6]
-	%89 = getelementptr %struct.edge_rec* %88, i32 0, i32 1		; <%struct.edge_rec**> [#uses=4]
+	%89 = getelementptr %struct.edge_rec, %struct.edge_rec* %88, i32 0, i32 1		; <%struct.edge_rec**> [#uses=4]
 	store %struct.edge_rec* %88, %struct.edge_rec** %89, align 4
-	%90 = getelementptr %struct.edge_rec* %88, i32 0, i32 0		; <%struct.VERTEX**> [#uses=2]
+	%90 = getelementptr %struct.edge_rec, %struct.edge_rec* %88, i32 0, i32 0		; <%struct.VERTEX**> [#uses=2]
 	store %struct.VERTEX* %18, %struct.VERTEX** %90, align 4
 	%91 = ptrtoint %struct.edge_rec* %88 to i32		; <i32> [#uses=5]
 	%92 = add i32 %91, 16		; <i32> [#uses=2]
 	%93 = inttoptr i32 %92 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
 	%94 = add i32 %91, 48		; <i32> [#uses=1]
 	%95 = inttoptr i32 %94 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
-	%96 = getelementptr %struct.edge_rec* %93, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%96 = getelementptr %struct.edge_rec, %struct.edge_rec* %93, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %95, %struct.edge_rec** %96, align 4
 	%97 = add i32 %91, 32		; <i32> [#uses=1]
 	%98 = inttoptr i32 %97 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=3]
-	%99 = getelementptr %struct.edge_rec* %98, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%99 = getelementptr %struct.edge_rec, %struct.edge_rec* %98, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %98, %struct.edge_rec** %99, align 4
-	%100 = getelementptr %struct.edge_rec* %98, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%100 = getelementptr %struct.edge_rec, %struct.edge_rec* %98, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
 	store %struct.VERTEX* %87, %struct.VERTEX** %100, align 4
-	%101 = getelementptr %struct.edge_rec* %95, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%101 = getelementptr %struct.edge_rec, %struct.edge_rec* %95, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %93, %struct.edge_rec** %101, align 4
-	%102 = load %struct.edge_rec** %89, align 4		; <%struct.edge_rec*> [#uses=1]
+	%102 = load %struct.edge_rec*, %struct.edge_rec** %89, align 4		; <%struct.edge_rec*> [#uses=1]
 	%103 = ptrtoint %struct.edge_rec* %102 to i32		; <i32> [#uses=2]
 	%104 = add i32 %103, 16		; <i32> [#uses=1]
 	%105 = and i32 %104, 63		; <i32> [#uses=1]
 	%106 = and i32 %103, -64		; <i32> [#uses=1]
 	%107 = or i32 %105, %106		; <i32> [#uses=1]
 	%108 = inttoptr i32 %107 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%109 = getelementptr %struct.edge_rec* %85, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%110 = load %struct.edge_rec** %109, align 4		; <%struct.edge_rec*> [#uses=1]
+	%109 = getelementptr %struct.edge_rec, %struct.edge_rec* %85, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%110 = load %struct.edge_rec*, %struct.edge_rec** %109, align 4		; <%struct.edge_rec*> [#uses=1]
 	%111 = ptrtoint %struct.edge_rec* %110 to i32		; <i32> [#uses=2]
 	%112 = add i32 %111, 16		; <i32> [#uses=1]
 	%113 = and i32 %112, 63		; <i32> [#uses=1]
 	%114 = and i32 %111, -64		; <i32> [#uses=1]
 	%115 = or i32 %113, %114		; <i32> [#uses=1]
 	%116 = inttoptr i32 %115 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%117 = getelementptr %struct.edge_rec* %116, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%118 = load %struct.edge_rec** %117, align 4		; <%struct.edge_rec*> [#uses=1]
-	%119 = getelementptr %struct.edge_rec* %108, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%120 = load %struct.edge_rec** %119, align 4		; <%struct.edge_rec*> [#uses=1]
+	%117 = getelementptr %struct.edge_rec, %struct.edge_rec* %116, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%118 = load %struct.edge_rec*, %struct.edge_rec** %117, align 4		; <%struct.edge_rec*> [#uses=1]
+	%119 = getelementptr %struct.edge_rec, %struct.edge_rec* %108, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%120 = load %struct.edge_rec*, %struct.edge_rec** %119, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %118, %struct.edge_rec** %119, align 4
 	store %struct.edge_rec* %120, %struct.edge_rec** %117, align 4
-	%121 = load %struct.edge_rec** %89, align 4		; <%struct.edge_rec*> [#uses=1]
-	%122 = load %struct.edge_rec** %109, align 4		; <%struct.edge_rec*> [#uses=1]
+	%121 = load %struct.edge_rec*, %struct.edge_rec** %89, align 4		; <%struct.edge_rec*> [#uses=1]
+	%122 = load %struct.edge_rec*, %struct.edge_rec** %109, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %121, %struct.edge_rec** %109, align 4
 	store %struct.edge_rec* %122, %struct.edge_rec** %89, align 4
 	%123 = xor i32 %91, 32		; <i32> [#uses=1]
 	%124 = inttoptr i32 %123 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=3]
-	%125 = getelementptr %struct.edge_rec* %124, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%126 = load %struct.edge_rec** %125, align 4		; <%struct.edge_rec*> [#uses=1]
+	%125 = getelementptr %struct.edge_rec, %struct.edge_rec* %124, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%126 = load %struct.edge_rec*, %struct.edge_rec** %125, align 4		; <%struct.edge_rec*> [#uses=1]
 	%127 = ptrtoint %struct.edge_rec* %126 to i32		; <i32> [#uses=2]
 	%128 = add i32 %127, 16		; <i32> [#uses=1]
 	%129 = and i32 %128, 63		; <i32> [#uses=1]
 	%130 = and i32 %127, -64		; <i32> [#uses=1]
 	%131 = or i32 %129, %130		; <i32> [#uses=1]
 	%132 = inttoptr i32 %131 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%133 = getelementptr %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%134 = load %struct.edge_rec** %133, align 4		; <%struct.edge_rec*> [#uses=1]
+	%133 = getelementptr %struct.edge_rec, %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%134 = load %struct.edge_rec*, %struct.edge_rec** %133, align 4		; <%struct.edge_rec*> [#uses=1]
 	%135 = ptrtoint %struct.edge_rec* %134 to i32		; <i32> [#uses=2]
 	%136 = add i32 %135, 16		; <i32> [#uses=1]
 	%137 = and i32 %136, 63		; <i32> [#uses=1]
 	%138 = and i32 %135, -64		; <i32> [#uses=1]
 	%139 = or i32 %137, %138		; <i32> [#uses=1]
 	%140 = inttoptr i32 %139 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%141 = getelementptr %struct.edge_rec* %140, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%142 = load %struct.edge_rec** %141, align 4		; <%struct.edge_rec*> [#uses=1]
-	%143 = getelementptr %struct.edge_rec* %132, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%144 = load %struct.edge_rec** %143, align 4		; <%struct.edge_rec*> [#uses=1]
+	%141 = getelementptr %struct.edge_rec, %struct.edge_rec* %140, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%142 = load %struct.edge_rec*, %struct.edge_rec** %141, align 4		; <%struct.edge_rec*> [#uses=1]
+	%143 = getelementptr %struct.edge_rec, %struct.edge_rec* %132, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%144 = load %struct.edge_rec*, %struct.edge_rec** %143, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %142, %struct.edge_rec** %143, align 4
 	store %struct.edge_rec* %144, %struct.edge_rec** %141, align 4
-	%145 = load %struct.edge_rec** %125, align 4		; <%struct.edge_rec*> [#uses=1]
-	%146 = load %struct.edge_rec** %133, align 4		; <%struct.edge_rec*> [#uses=2]
+	%145 = load %struct.edge_rec*, %struct.edge_rec** %125, align 4		; <%struct.edge_rec*> [#uses=1]
+	%146 = load %struct.edge_rec*, %struct.edge_rec** %133, align 4		; <%struct.edge_rec*> [#uses=2]
 	store %struct.edge_rec* %145, %struct.edge_rec** %133, align 4
 	store %struct.edge_rec* %146, %struct.edge_rec** %125, align 4
 	%147 = and i32 %92, 63		; <i32> [#uses=1]
 	%148 = and i32 %91, -64		; <i32> [#uses=1]
 	%149 = or i32 %147, %148		; <i32> [#uses=1]
 	%150 = inttoptr i32 %149 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%151 = getelementptr %struct.edge_rec* %150, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%152 = load %struct.edge_rec** %151, align 4		; <%struct.edge_rec*> [#uses=1]
+	%151 = getelementptr %struct.edge_rec, %struct.edge_rec* %150, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%152 = load %struct.edge_rec*, %struct.edge_rec** %151, align 4		; <%struct.edge_rec*> [#uses=1]
 	%153 = ptrtoint %struct.edge_rec* %152 to i32		; <i32> [#uses=2]
 	%154 = add i32 %153, 16		; <i32> [#uses=1]
 	%155 = and i32 %154, 63		; <i32> [#uses=1]
 	%156 = and i32 %153, -64		; <i32> [#uses=1]
 	%157 = or i32 %155, %156		; <i32> [#uses=1]
 	%158 = inttoptr i32 %157 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%159 = load %struct.VERTEX** %90, align 4		; <%struct.VERTEX*> [#uses=1]
-	%160 = getelementptr %struct.edge_rec* %124, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%161 = load %struct.VERTEX** %160, align 4		; <%struct.VERTEX*> [#uses=1]
-	%162 = getelementptr %struct.edge_rec* %16, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%163 = load %struct.VERTEX** %162, align 4		; <%struct.VERTEX*> [#uses=1]
+	%159 = load %struct.VERTEX*, %struct.VERTEX** %90, align 4		; <%struct.VERTEX*> [#uses=1]
+	%160 = getelementptr %struct.edge_rec, %struct.edge_rec* %124, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%161 = load %struct.VERTEX*, %struct.VERTEX** %160, align 4		; <%struct.VERTEX*> [#uses=1]
+	%162 = getelementptr %struct.edge_rec, %struct.edge_rec* %16, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%163 = load %struct.VERTEX*, %struct.VERTEX** %162, align 4		; <%struct.VERTEX*> [#uses=1]
 	%164 = icmp eq %struct.VERTEX* %163, %159		; <i1> [#uses=1]
 	%rdo_addr.0.i = select i1 %164, %struct.edge_rec* %88, %struct.edge_rec* %16		; <%struct.edge_rec*> [#uses=3]
-	%165 = getelementptr %struct.edge_rec* %10, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%166 = load %struct.VERTEX** %165, align 4		; <%struct.VERTEX*> [#uses=1]
+	%165 = getelementptr %struct.edge_rec, %struct.edge_rec* %10, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%166 = load %struct.VERTEX*, %struct.VERTEX** %165, align 4		; <%struct.VERTEX*> [#uses=1]
 	%167 = icmp eq %struct.VERTEX* %166, %161		; <i1> [#uses=1]
 	%ldo_addr.0.ph.i = select i1 %167, %struct.edge_rec* %124, %struct.edge_rec* %10		; <%struct.edge_rec*> [#uses=3]
 	br label %bb9.i
@@ -243,32 +243,32 @@ bb9.i:		; preds = %bb25.i, %bb24.i, %bb5.i
 	%lcand.2.i = phi %struct.edge_rec* [ %146, %bb5.i ], [ %lcand.1.i, %bb24.i ], [ %739, %bb25.i ]		; <%struct.edge_rec*> [#uses=5]
 	%rcand.2.i = phi %struct.edge_rec* [ %158, %bb5.i ], [ %666, %bb24.i ], [ %rcand.1.i, %bb25.i ]		; <%struct.edge_rec*> [#uses=5]
 	%basel.0.i = phi %struct.edge_rec* [ %88, %bb5.i ], [ %595, %bb24.i ], [ %716, %bb25.i ]		; <%struct.edge_rec*> [#uses=2]
-	%168 = getelementptr %struct.edge_rec* %lcand.2.i, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%169 = load %struct.edge_rec** %168, align 4		; <%struct.edge_rec*> [#uses=3]
-	%170 = getelementptr %struct.edge_rec* %basel.0.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=3]
-	%171 = load %struct.VERTEX** %170, align 4		; <%struct.VERTEX*> [#uses=4]
+	%168 = getelementptr %struct.edge_rec, %struct.edge_rec* %lcand.2.i, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%169 = load %struct.edge_rec*, %struct.edge_rec** %168, align 4		; <%struct.edge_rec*> [#uses=3]
+	%170 = getelementptr %struct.edge_rec, %struct.edge_rec* %basel.0.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=3]
+	%171 = load %struct.VERTEX*, %struct.VERTEX** %170, align 4		; <%struct.VERTEX*> [#uses=4]
 	%172 = ptrtoint %struct.edge_rec* %basel.0.i to i32		; <i32> [#uses=3]
 	%173 = xor i32 %172, 32		; <i32> [#uses=1]
 	%174 = inttoptr i32 %173 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
-	%175 = getelementptr %struct.edge_rec* %174, i32 0, i32 0		; <%struct.VERTEX**> [#uses=3]
-	%176 = load %struct.VERTEX** %175, align 4		; <%struct.VERTEX*> [#uses=3]
+	%175 = getelementptr %struct.edge_rec, %struct.edge_rec* %174, i32 0, i32 0		; <%struct.VERTEX**> [#uses=3]
+	%176 = load %struct.VERTEX*, %struct.VERTEX** %175, align 4		; <%struct.VERTEX*> [#uses=3]
 	%177 = ptrtoint %struct.edge_rec* %169 to i32		; <i32> [#uses=1]
 	%178 = xor i32 %177, 32		; <i32> [#uses=1]
 	%179 = inttoptr i32 %178 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%180 = getelementptr %struct.edge_rec* %179, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%181 = load %struct.VERTEX** %180, align 4		; <%struct.VERTEX*> [#uses=2]
-	%182 = getelementptr %struct.VERTEX* %171, i32 0, i32 0, i32 0		; <double*> [#uses=2]
-	%183 = load double* %182, align 4		; <double> [#uses=2]
-	%184 = getelementptr %struct.VERTEX* %171, i32 0, i32 0, i32 1		; <double*> [#uses=2]
-	%185 = load double* %184, align 4		; <double> [#uses=2]
-	%186 = getelementptr %struct.VERTEX* %181, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%187 = load double* %186, align 4		; <double> [#uses=1]
-	%188 = getelementptr %struct.VERTEX* %181, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%189 = load double* %188, align 4		; <double> [#uses=1]
-	%190 = getelementptr %struct.VERTEX* %176, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%191 = load double* %190, align 4		; <double> [#uses=2]
-	%192 = getelementptr %struct.VERTEX* %176, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%193 = load double* %192, align 4		; <double> [#uses=2]
+	%180 = getelementptr %struct.edge_rec, %struct.edge_rec* %179, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%181 = load %struct.VERTEX*, %struct.VERTEX** %180, align 4		; <%struct.VERTEX*> [#uses=2]
+	%182 = getelementptr %struct.VERTEX, %struct.VERTEX* %171, i32 0, i32 0, i32 0		; <double*> [#uses=2]
+	%183 = load double, double* %182, align 4		; <double> [#uses=2]
+	%184 = getelementptr %struct.VERTEX, %struct.VERTEX* %171, i32 0, i32 0, i32 1		; <double*> [#uses=2]
+	%185 = load double, double* %184, align 4		; <double> [#uses=2]
+	%186 = getelementptr %struct.VERTEX, %struct.VERTEX* %181, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%187 = load double, double* %186, align 4		; <double> [#uses=1]
+	%188 = getelementptr %struct.VERTEX, %struct.VERTEX* %181, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%189 = load double, double* %188, align 4		; <double> [#uses=1]
+	%190 = getelementptr %struct.VERTEX, %struct.VERTEX* %176, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%191 = load double, double* %190, align 4		; <double> [#uses=2]
+	%192 = getelementptr %struct.VERTEX, %struct.VERTEX* %176, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%193 = load double, double* %192, align 4		; <double> [#uses=2]
 	%194 = fsub double %183, %191		; <double> [#uses=1]
 	%195 = fsub double %189, %193		; <double> [#uses=1]
 	%196 = fmul double %194, %195		; <double> [#uses=1]
@@ -280,8 +280,8 @@ bb9.i:		; preds = %bb25.i, %bb24.i, %bb5.i
 	br i1 %201, label %bb10.i, label %bb13.i
 
 bb10.i:		; preds = %bb9.i
-	%202 = getelementptr %struct.VERTEX* %171, i32 0, i32 0, i32 2		; <double*> [#uses=1]
-	%avail_edge.promoted25 = load %struct.edge_rec** @avail_edge		; <%struct.edge_rec*> [#uses=1]
+	%202 = getelementptr %struct.VERTEX, %struct.VERTEX* %171, i32 0, i32 0, i32 2		; <double*> [#uses=1]
+	%avail_edge.promoted25 = load %struct.edge_rec*, %struct.edge_rec** @avail_edge		; <%struct.edge_rec*> [#uses=1]
 	br label %bb12.i
 
 bb11.i:		; preds = %bb12.i
@@ -291,38 +291,38 @@ bb11.i:		; preds = %bb12.i
 	%206 = and i32 %203, -64		; <i32> [#uses=3]
 	%207 = or i32 %205, %206		; <i32> [#uses=1]
 	%208 = inttoptr i32 %207 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%209 = getelementptr %struct.edge_rec* %208, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%210 = load %struct.edge_rec** %209, align 4		; <%struct.edge_rec*> [#uses=1]
+	%209 = getelementptr %struct.edge_rec, %struct.edge_rec* %208, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%210 = load %struct.edge_rec*, %struct.edge_rec** %209, align 4		; <%struct.edge_rec*> [#uses=1]
 	%211 = ptrtoint %struct.edge_rec* %210 to i32		; <i32> [#uses=2]
 	%212 = add i32 %211, 16		; <i32> [#uses=1]
 	%213 = and i32 %212, 63		; <i32> [#uses=1]
 	%214 = and i32 %211, -64		; <i32> [#uses=1]
 	%215 = or i32 %213, %214		; <i32> [#uses=1]
 	%216 = inttoptr i32 %215 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%217 = getelementptr %struct.edge_rec* %lcand.0.i, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%218 = load %struct.edge_rec** %217, align 4		; <%struct.edge_rec*> [#uses=1]
+	%217 = getelementptr %struct.edge_rec, %struct.edge_rec* %lcand.0.i, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%218 = load %struct.edge_rec*, %struct.edge_rec** %217, align 4		; <%struct.edge_rec*> [#uses=1]
 	%219 = ptrtoint %struct.edge_rec* %218 to i32		; <i32> [#uses=2]
 	%220 = add i32 %219, 16		; <i32> [#uses=1]
 	%221 = and i32 %220, 63		; <i32> [#uses=1]
 	%222 = and i32 %219, -64		; <i32> [#uses=1]
 	%223 = or i32 %221, %222		; <i32> [#uses=1]
 	%224 = inttoptr i32 %223 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%225 = getelementptr %struct.edge_rec* %216, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%226 = load %struct.edge_rec** %225, align 4		; <%struct.edge_rec*> [#uses=1]
+	%225 = getelementptr %struct.edge_rec, %struct.edge_rec* %216, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%226 = load %struct.edge_rec*, %struct.edge_rec** %225, align 4		; <%struct.edge_rec*> [#uses=1]
 	%227 = ptrtoint %struct.edge_rec* %226 to i32		; <i32> [#uses=2]
 	%228 = add i32 %227, 16		; <i32> [#uses=1]
 	%229 = and i32 %228, 63		; <i32> [#uses=1]
 	%230 = and i32 %227, -64		; <i32> [#uses=1]
 	%231 = or i32 %229, %230		; <i32> [#uses=1]
 	%232 = inttoptr i32 %231 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%233 = getelementptr %struct.edge_rec* %232, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%234 = load %struct.edge_rec** %233, align 4		; <%struct.edge_rec*> [#uses=1]
-	%235 = getelementptr %struct.edge_rec* %224, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%236 = load %struct.edge_rec** %235, align 4		; <%struct.edge_rec*> [#uses=1]
+	%233 = getelementptr %struct.edge_rec, %struct.edge_rec* %232, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%234 = load %struct.edge_rec*, %struct.edge_rec** %233, align 4		; <%struct.edge_rec*> [#uses=1]
+	%235 = getelementptr %struct.edge_rec, %struct.edge_rec* %224, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%236 = load %struct.edge_rec*, %struct.edge_rec** %235, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %234, %struct.edge_rec** %235, align 4
 	store %struct.edge_rec* %236, %struct.edge_rec** %233, align 4
-	%237 = load %struct.edge_rec** %217, align 4		; <%struct.edge_rec*> [#uses=1]
-	%238 = load %struct.edge_rec** %225, align 4		; <%struct.edge_rec*> [#uses=1]
+	%237 = load %struct.edge_rec*, %struct.edge_rec** %217, align 4		; <%struct.edge_rec*> [#uses=1]
+	%238 = load %struct.edge_rec*, %struct.edge_rec** %225, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %237, %struct.edge_rec** %225, align 4
 	store %struct.edge_rec* %238, %struct.edge_rec** %217, align 4
 	%239 = xor i32 %203, 32		; <i32> [#uses=2]
@@ -330,8 +330,8 @@ bb11.i:		; preds = %bb12.i
 	%241 = and i32 %240, 63		; <i32> [#uses=1]
 	%242 = or i32 %241, %206		; <i32> [#uses=1]
 	%243 = inttoptr i32 %242 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%244 = getelementptr %struct.edge_rec* %243, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%245 = load %struct.edge_rec** %244, align 4		; <%struct.edge_rec*> [#uses=1]
+	%244 = getelementptr %struct.edge_rec, %struct.edge_rec* %243, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%245 = load %struct.edge_rec*, %struct.edge_rec** %244, align 4		; <%struct.edge_rec*> [#uses=1]
 	%246 = ptrtoint %struct.edge_rec* %245 to i32		; <i32> [#uses=2]
 	%247 = add i32 %246, 16		; <i32> [#uses=1]
 	%248 = and i32 %247, 63		; <i32> [#uses=1]
@@ -339,39 +339,39 @@ bb11.i:		; preds = %bb12.i
 	%250 = or i32 %248, %249		; <i32> [#uses=1]
 	%251 = inttoptr i32 %250 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
 	%252 = inttoptr i32 %239 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%253 = getelementptr %struct.edge_rec* %252, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%254 = load %struct.edge_rec** %253, align 4		; <%struct.edge_rec*> [#uses=1]
+	%253 = getelementptr %struct.edge_rec, %struct.edge_rec* %252, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%254 = load %struct.edge_rec*, %struct.edge_rec** %253, align 4		; <%struct.edge_rec*> [#uses=1]
 	%255 = ptrtoint %struct.edge_rec* %254 to i32		; <i32> [#uses=2]
 	%256 = add i32 %255, 16		; <i32> [#uses=1]
 	%257 = and i32 %256, 63		; <i32> [#uses=1]
 	%258 = and i32 %255, -64		; <i32> [#uses=1]
 	%259 = or i32 %257, %258		; <i32> [#uses=1]
 	%260 = inttoptr i32 %259 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%261 = getelementptr %struct.edge_rec* %251, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%262 = load %struct.edge_rec** %261, align 4		; <%struct.edge_rec*> [#uses=1]
+	%261 = getelementptr %struct.edge_rec, %struct.edge_rec* %251, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%262 = load %struct.edge_rec*, %struct.edge_rec** %261, align 4		; <%struct.edge_rec*> [#uses=1]
 	%263 = ptrtoint %struct.edge_rec* %262 to i32		; <i32> [#uses=2]
 	%264 = add i32 %263, 16		; <i32> [#uses=1]
 	%265 = and i32 %264, 63		; <i32> [#uses=1]
 	%266 = and i32 %263, -64		; <i32> [#uses=1]
 	%267 = or i32 %265, %266		; <i32> [#uses=1]
 	%268 = inttoptr i32 %267 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%269 = getelementptr %struct.edge_rec* %268, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%270 = load %struct.edge_rec** %269, align 4		; <%struct.edge_rec*> [#uses=1]
-	%271 = getelementptr %struct.edge_rec* %260, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%272 = load %struct.edge_rec** %271, align 4		; <%struct.edge_rec*> [#uses=1]
+	%269 = getelementptr %struct.edge_rec, %struct.edge_rec* %268, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%270 = load %struct.edge_rec*, %struct.edge_rec** %269, align 4		; <%struct.edge_rec*> [#uses=1]
+	%271 = getelementptr %struct.edge_rec, %struct.edge_rec* %260, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%272 = load %struct.edge_rec*, %struct.edge_rec** %271, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %270, %struct.edge_rec** %271, align 4
 	store %struct.edge_rec* %272, %struct.edge_rec** %269, align 4
-	%273 = load %struct.edge_rec** %253, align 4		; <%struct.edge_rec*> [#uses=1]
-	%274 = load %struct.edge_rec** %261, align 4		; <%struct.edge_rec*> [#uses=1]
+	%273 = load %struct.edge_rec*, %struct.edge_rec** %253, align 4		; <%struct.edge_rec*> [#uses=1]
+	%274 = load %struct.edge_rec*, %struct.edge_rec** %261, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %273, %struct.edge_rec** %261, align 4
 	store %struct.edge_rec* %274, %struct.edge_rec** %253, align 4
 	%275 = inttoptr i32 %206 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
-	%276 = getelementptr %struct.edge_rec* %275, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%276 = getelementptr %struct.edge_rec, %struct.edge_rec* %275, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %avail_edge.tmp.026, %struct.edge_rec** %276, align 4
-	%277 = getelementptr %struct.edge_rec* %t.0.i, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%278 = load %struct.edge_rec** %277, align 4		; <%struct.edge_rec*> [#uses=2]
-	%.pre.i = load double* %182, align 4		; <double> [#uses=1]
-	%.pre22.i = load double* %184, align 4		; <double> [#uses=1]
+	%277 = getelementptr %struct.edge_rec, %struct.edge_rec* %t.0.i, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%278 = load %struct.edge_rec*, %struct.edge_rec** %277, align 4		; <%struct.edge_rec*> [#uses=2]
+	%.pre.i = load double, double* %182, align 4		; <double> [#uses=1]
+	%.pre22.i = load double, double* %184, align 4		; <double> [#uses=1]
 	br label %bb12.i
 
 bb12.i:		; preds = %bb11.i, %bb10.i
@@ -389,37 +389,37 @@ bb12.i:		; preds = %bb11.i, %bb10.i
 	%.pn4.in.i = xor i32 %.pn4.in.in.i, 32		; <i32> [#uses=1]
 	%.pn5.i = inttoptr i32 %.pn5.in.i to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
 	%.pn4.i = inttoptr i32 %.pn4.in.i to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%v1.0.in.i = getelementptr %struct.edge_rec* %.pn5.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%v2.0.in.i = getelementptr %struct.edge_rec* %.pn4.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%v3.0.in.i = getelementptr %struct.edge_rec* %lcand.2.pn.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%v1.0.i = load %struct.VERTEX** %v1.0.in.i		; <%struct.VERTEX*> [#uses=3]
-	%v2.0.i = load %struct.VERTEX** %v2.0.in.i		; <%struct.VERTEX*> [#uses=3]
-	%v3.0.i = load %struct.VERTEX** %v3.0.in.i		; <%struct.VERTEX*> [#uses=3]
-	%281 = load double* %202, align 4		; <double> [#uses=3]
-	%282 = getelementptr %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%283 = load double* %282, align 4		; <double> [#uses=1]
+	%v1.0.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %.pn5.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%v2.0.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %.pn4.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%v3.0.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %lcand.2.pn.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%v1.0.i = load %struct.VERTEX*, %struct.VERTEX** %v1.0.in.i		; <%struct.VERTEX*> [#uses=3]
+	%v2.0.i = load %struct.VERTEX*, %struct.VERTEX** %v2.0.in.i		; <%struct.VERTEX*> [#uses=3]
+	%v3.0.i = load %struct.VERTEX*, %struct.VERTEX** %v3.0.in.i		; <%struct.VERTEX*> [#uses=3]
+	%281 = load double, double* %202, align 4		; <double> [#uses=3]
+	%282 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%283 = load double, double* %282, align 4		; <double> [#uses=1]
 	%284 = fsub double %283, %280		; <double> [#uses=2]
-	%285 = getelementptr %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%286 = load double* %285, align 4		; <double> [#uses=1]
+	%285 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%286 = load double, double* %285, align 4		; <double> [#uses=1]
 	%287 = fsub double %286, %279		; <double> [#uses=2]
-	%288 = getelementptr %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 2		; <double*> [#uses=1]
-	%289 = load double* %288, align 4		; <double> [#uses=1]
-	%290 = getelementptr %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%291 = load double* %290, align 4		; <double> [#uses=1]
+	%288 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 2		; <double*> [#uses=1]
+	%289 = load double, double* %288, align 4		; <double> [#uses=1]
+	%290 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%291 = load double, double* %290, align 4		; <double> [#uses=1]
 	%292 = fsub double %291, %280		; <double> [#uses=2]
-	%293 = getelementptr %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%294 = load double* %293, align 4		; <double> [#uses=1]
+	%293 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%294 = load double, double* %293, align 4		; <double> [#uses=1]
 	%295 = fsub double %294, %279		; <double> [#uses=2]
-	%296 = getelementptr %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 2		; <double*> [#uses=1]
-	%297 = load double* %296, align 4		; <double> [#uses=1]
-	%298 = getelementptr %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%299 = load double* %298, align 4		; <double> [#uses=1]
+	%296 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 2		; <double*> [#uses=1]
+	%297 = load double, double* %296, align 4		; <double> [#uses=1]
+	%298 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%299 = load double, double* %298, align 4		; <double> [#uses=1]
 	%300 = fsub double %299, %280		; <double> [#uses=2]
-	%301 = getelementptr %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%302 = load double* %301, align 4		; <double> [#uses=1]
+	%301 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%302 = load double, double* %301, align 4		; <double> [#uses=1]
 	%303 = fsub double %302, %279		; <double> [#uses=2]
-	%304 = getelementptr %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 2		; <double*> [#uses=1]
-	%305 = load double* %304, align 4		; <double> [#uses=1]
+	%304 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 2		; <double*> [#uses=1]
+	%305 = load double, double* %304, align 4		; <double> [#uses=1]
 	%306 = fsub double %289, %281		; <double> [#uses=1]
 	%307 = fmul double %292, %303		; <double> [#uses=1]
 	%308 = fmul double %295, %300		; <double> [#uses=1]
@@ -442,8 +442,8 @@ bb12.i:		; preds = %bb11.i, %bb10.i
 
 bb13.loopexit.i:		; preds = %bb12.i
 	store %struct.edge_rec* %avail_edge.tmp.026, %struct.edge_rec** @avail_edge
-	%.pre23.i = load %struct.VERTEX** %170, align 4		; <%struct.VERTEX*> [#uses=1]
-	%.pre24.i = load %struct.VERTEX** %175, align 4		; <%struct.VERTEX*> [#uses=1]
+	%.pre23.i = load %struct.VERTEX*, %struct.VERTEX** %170, align 4		; <%struct.VERTEX*> [#uses=1]
+	%.pre24.i = load %struct.VERTEX*, %struct.VERTEX** %175, align 4		; <%struct.VERTEX*> [#uses=1]
 	br label %bb13.i
 
 bb13.i:		; preds = %bb13.loopexit.i, %bb9.i
@@ -456,8 +456,8 @@ bb13.i:		; preds = %bb13.loopexit.i, %bb9.i
 	%329 = and i32 %326, -64		; <i32> [#uses=1]
 	%330 = or i32 %328, %329		; <i32> [#uses=1]
 	%331 = inttoptr i32 %330 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%332 = getelementptr %struct.edge_rec* %331, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%333 = load %struct.edge_rec** %332, align 4		; <%struct.edge_rec*> [#uses=1]
+	%332 = getelementptr %struct.edge_rec, %struct.edge_rec* %331, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%333 = load %struct.edge_rec*, %struct.edge_rec** %332, align 4		; <%struct.edge_rec*> [#uses=1]
 	%334 = ptrtoint %struct.edge_rec* %333 to i32		; <i32> [#uses=2]
 	%335 = add i32 %334, 16		; <i32> [#uses=1]
 	%336 = and i32 %335, 63		; <i32> [#uses=1]
@@ -465,20 +465,20 @@ bb13.i:		; preds = %bb13.loopexit.i, %bb9.i
 	%338 = or i32 %336, %337		; <i32> [#uses=3]
 	%339 = xor i32 %338, 32		; <i32> [#uses=1]
 	%340 = inttoptr i32 %339 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%341 = getelementptr %struct.edge_rec* %340, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%342 = load %struct.VERTEX** %341, align 4		; <%struct.VERTEX*> [#uses=2]
-	%343 = getelementptr %struct.VERTEX* %325, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%344 = load double* %343, align 4		; <double> [#uses=1]
-	%345 = getelementptr %struct.VERTEX* %325, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%346 = load double* %345, align 4		; <double> [#uses=1]
-	%347 = getelementptr %struct.VERTEX* %342, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%348 = load double* %347, align 4		; <double> [#uses=1]
-	%349 = getelementptr %struct.VERTEX* %342, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%350 = load double* %349, align 4		; <double> [#uses=1]
-	%351 = getelementptr %struct.VERTEX* %324, i32 0, i32 0, i32 0		; <double*> [#uses=2]
-	%352 = load double* %351, align 4		; <double> [#uses=3]
-	%353 = getelementptr %struct.VERTEX* %324, i32 0, i32 0, i32 1		; <double*> [#uses=2]
-	%354 = load double* %353, align 4		; <double> [#uses=3]
+	%341 = getelementptr %struct.edge_rec, %struct.edge_rec* %340, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%342 = load %struct.VERTEX*, %struct.VERTEX** %341, align 4		; <%struct.VERTEX*> [#uses=2]
+	%343 = getelementptr %struct.VERTEX, %struct.VERTEX* %325, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%344 = load double, double* %343, align 4		; <double> [#uses=1]
+	%345 = getelementptr %struct.VERTEX, %struct.VERTEX* %325, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%346 = load double, double* %345, align 4		; <double> [#uses=1]
+	%347 = getelementptr %struct.VERTEX, %struct.VERTEX* %342, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%348 = load double, double* %347, align 4		; <double> [#uses=1]
+	%349 = getelementptr %struct.VERTEX, %struct.VERTEX* %342, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%350 = load double, double* %349, align 4		; <double> [#uses=1]
+	%351 = getelementptr %struct.VERTEX, %struct.VERTEX* %324, i32 0, i32 0, i32 0		; <double*> [#uses=2]
+	%352 = load double, double* %351, align 4		; <double> [#uses=3]
+	%353 = getelementptr %struct.VERTEX, %struct.VERTEX* %324, i32 0, i32 0, i32 1		; <double*> [#uses=2]
+	%354 = load double, double* %353, align 4		; <double> [#uses=3]
 	%355 = fsub double %344, %352		; <double> [#uses=1]
 	%356 = fsub double %350, %354		; <double> [#uses=1]
 	%357 = fmul double %355, %356		; <double> [#uses=1]
@@ -490,8 +490,8 @@ bb13.i:		; preds = %bb13.loopexit.i, %bb9.i
 	br i1 %362, label %bb14.i, label %bb17.i
 
 bb14.i:		; preds = %bb13.i
-	%363 = getelementptr %struct.VERTEX* %324, i32 0, i32 0, i32 2		; <double*> [#uses=1]
-	%avail_edge.promoted = load %struct.edge_rec** @avail_edge		; <%struct.edge_rec*> [#uses=1]
+	%363 = getelementptr %struct.VERTEX, %struct.VERTEX* %324, i32 0, i32 0, i32 2		; <double*> [#uses=1]
+	%avail_edge.promoted = load %struct.edge_rec*, %struct.edge_rec** @avail_edge		; <%struct.edge_rec*> [#uses=1]
 	br label %bb16.i
 
 bb15.i:		; preds = %bb16.i
@@ -501,38 +501,38 @@ bb15.i:		; preds = %bb16.i
 	%367 = and i32 %364, -64		; <i32> [#uses=3]
 	%368 = or i32 %366, %367		; <i32> [#uses=1]
 	%369 = inttoptr i32 %368 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%370 = getelementptr %struct.edge_rec* %369, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%371 = load %struct.edge_rec** %370, align 4		; <%struct.edge_rec*> [#uses=1]
+	%370 = getelementptr %struct.edge_rec, %struct.edge_rec* %369, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%371 = load %struct.edge_rec*, %struct.edge_rec** %370, align 4		; <%struct.edge_rec*> [#uses=1]
 	%372 = ptrtoint %struct.edge_rec* %371 to i32		; <i32> [#uses=2]
 	%373 = add i32 %372, 16		; <i32> [#uses=1]
 	%374 = and i32 %373, 63		; <i32> [#uses=1]
 	%375 = and i32 %372, -64		; <i32> [#uses=1]
 	%376 = or i32 %374, %375		; <i32> [#uses=1]
 	%377 = inttoptr i32 %376 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%378 = getelementptr %struct.edge_rec* %rcand.0.i, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%379 = load %struct.edge_rec** %378, align 4		; <%struct.edge_rec*> [#uses=1]
+	%378 = getelementptr %struct.edge_rec, %struct.edge_rec* %rcand.0.i, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%379 = load %struct.edge_rec*, %struct.edge_rec** %378, align 4		; <%struct.edge_rec*> [#uses=1]
 	%380 = ptrtoint %struct.edge_rec* %379 to i32		; <i32> [#uses=2]
 	%381 = add i32 %380, 16		; <i32> [#uses=1]
 	%382 = and i32 %381, 63		; <i32> [#uses=1]
 	%383 = and i32 %380, -64		; <i32> [#uses=1]
 	%384 = or i32 %382, %383		; <i32> [#uses=1]
 	%385 = inttoptr i32 %384 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%386 = getelementptr %struct.edge_rec* %377, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%387 = load %struct.edge_rec** %386, align 4		; <%struct.edge_rec*> [#uses=1]
+	%386 = getelementptr %struct.edge_rec, %struct.edge_rec* %377, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%387 = load %struct.edge_rec*, %struct.edge_rec** %386, align 4		; <%struct.edge_rec*> [#uses=1]
 	%388 = ptrtoint %struct.edge_rec* %387 to i32		; <i32> [#uses=2]
 	%389 = add i32 %388, 16		; <i32> [#uses=1]
 	%390 = and i32 %389, 63		; <i32> [#uses=1]
 	%391 = and i32 %388, -64		; <i32> [#uses=1]
 	%392 = or i32 %390, %391		; <i32> [#uses=1]
 	%393 = inttoptr i32 %392 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%394 = getelementptr %struct.edge_rec* %393, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%395 = load %struct.edge_rec** %394, align 4		; <%struct.edge_rec*> [#uses=1]
-	%396 = getelementptr %struct.edge_rec* %385, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%397 = load %struct.edge_rec** %396, align 4		; <%struct.edge_rec*> [#uses=1]
+	%394 = getelementptr %struct.edge_rec, %struct.edge_rec* %393, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%395 = load %struct.edge_rec*, %struct.edge_rec** %394, align 4		; <%struct.edge_rec*> [#uses=1]
+	%396 = getelementptr %struct.edge_rec, %struct.edge_rec* %385, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%397 = load %struct.edge_rec*, %struct.edge_rec** %396, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %395, %struct.edge_rec** %396, align 4
 	store %struct.edge_rec* %397, %struct.edge_rec** %394, align 4
-	%398 = load %struct.edge_rec** %378, align 4		; <%struct.edge_rec*> [#uses=1]
-	%399 = load %struct.edge_rec** %386, align 4		; <%struct.edge_rec*> [#uses=1]
+	%398 = load %struct.edge_rec*, %struct.edge_rec** %378, align 4		; <%struct.edge_rec*> [#uses=1]
+	%399 = load %struct.edge_rec*, %struct.edge_rec** %386, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %398, %struct.edge_rec** %386, align 4
 	store %struct.edge_rec* %399, %struct.edge_rec** %378, align 4
 	%400 = xor i32 %364, 32		; <i32> [#uses=2]
@@ -540,8 +540,8 @@ bb15.i:		; preds = %bb16.i
 	%402 = and i32 %401, 63		; <i32> [#uses=1]
 	%403 = or i32 %402, %367		; <i32> [#uses=1]
 	%404 = inttoptr i32 %403 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%405 = getelementptr %struct.edge_rec* %404, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%406 = load %struct.edge_rec** %405, align 4		; <%struct.edge_rec*> [#uses=1]
+	%405 = getelementptr %struct.edge_rec, %struct.edge_rec* %404, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%406 = load %struct.edge_rec*, %struct.edge_rec** %405, align 4		; <%struct.edge_rec*> [#uses=1]
 	%407 = ptrtoint %struct.edge_rec* %406 to i32		; <i32> [#uses=2]
 	%408 = add i32 %407, 16		; <i32> [#uses=1]
 	%409 = and i32 %408, 63		; <i32> [#uses=1]
@@ -549,49 +549,49 @@ bb15.i:		; preds = %bb16.i
 	%411 = or i32 %409, %410		; <i32> [#uses=1]
 	%412 = inttoptr i32 %411 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
 	%413 = inttoptr i32 %400 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%414 = getelementptr %struct.edge_rec* %413, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%415 = load %struct.edge_rec** %414, align 4		; <%struct.edge_rec*> [#uses=1]
+	%414 = getelementptr %struct.edge_rec, %struct.edge_rec* %413, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%415 = load %struct.edge_rec*, %struct.edge_rec** %414, align 4		; <%struct.edge_rec*> [#uses=1]
 	%416 = ptrtoint %struct.edge_rec* %415 to i32		; <i32> [#uses=2]
 	%417 = add i32 %416, 16		; <i32> [#uses=1]
 	%418 = and i32 %417, 63		; <i32> [#uses=1]
 	%419 = and i32 %416, -64		; <i32> [#uses=1]
 	%420 = or i32 %418, %419		; <i32> [#uses=1]
 	%421 = inttoptr i32 %420 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%422 = getelementptr %struct.edge_rec* %412, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%423 = load %struct.edge_rec** %422, align 4		; <%struct.edge_rec*> [#uses=1]
+	%422 = getelementptr %struct.edge_rec, %struct.edge_rec* %412, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%423 = load %struct.edge_rec*, %struct.edge_rec** %422, align 4		; <%struct.edge_rec*> [#uses=1]
 	%424 = ptrtoint %struct.edge_rec* %423 to i32		; <i32> [#uses=2]
 	%425 = add i32 %424, 16		; <i32> [#uses=1]
 	%426 = and i32 %425, 63		; <i32> [#uses=1]
 	%427 = and i32 %424, -64		; <i32> [#uses=1]
 	%428 = or i32 %426, %427		; <i32> [#uses=1]
 	%429 = inttoptr i32 %428 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%430 = getelementptr %struct.edge_rec* %429, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%431 = load %struct.edge_rec** %430, align 4		; <%struct.edge_rec*> [#uses=1]
-	%432 = getelementptr %struct.edge_rec* %421, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%433 = load %struct.edge_rec** %432, align 4		; <%struct.edge_rec*> [#uses=1]
+	%430 = getelementptr %struct.edge_rec, %struct.edge_rec* %429, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%431 = load %struct.edge_rec*, %struct.edge_rec** %430, align 4		; <%struct.edge_rec*> [#uses=1]
+	%432 = getelementptr %struct.edge_rec, %struct.edge_rec* %421, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%433 = load %struct.edge_rec*, %struct.edge_rec** %432, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %431, %struct.edge_rec** %432, align 4
 	store %struct.edge_rec* %433, %struct.edge_rec** %430, align 4
-	%434 = load %struct.edge_rec** %414, align 4		; <%struct.edge_rec*> [#uses=1]
-	%435 = load %struct.edge_rec** %422, align 4		; <%struct.edge_rec*> [#uses=1]
+	%434 = load %struct.edge_rec*, %struct.edge_rec** %414, align 4		; <%struct.edge_rec*> [#uses=1]
+	%435 = load %struct.edge_rec*, %struct.edge_rec** %422, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %434, %struct.edge_rec** %422, align 4
 	store %struct.edge_rec* %435, %struct.edge_rec** %414, align 4
 	%436 = inttoptr i32 %367 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
-	%437 = getelementptr %struct.edge_rec* %436, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%437 = getelementptr %struct.edge_rec, %struct.edge_rec* %436, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %avail_edge.tmp.0, %struct.edge_rec** %437, align 4
 	%438 = add i32 %t.1.in.i, 16		; <i32> [#uses=1]
 	%439 = and i32 %438, 63		; <i32> [#uses=1]
 	%440 = and i32 %t.1.in.i, -64		; <i32> [#uses=1]
 	%441 = or i32 %439, %440		; <i32> [#uses=1]
 	%442 = inttoptr i32 %441 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%443 = getelementptr %struct.edge_rec* %442, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%444 = load %struct.edge_rec** %443, align 4		; <%struct.edge_rec*> [#uses=1]
+	%443 = getelementptr %struct.edge_rec, %struct.edge_rec* %442, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%444 = load %struct.edge_rec*, %struct.edge_rec** %443, align 4		; <%struct.edge_rec*> [#uses=1]
 	%445 = ptrtoint %struct.edge_rec* %444 to i32		; <i32> [#uses=2]
 	%446 = add i32 %445, 16		; <i32> [#uses=1]
 	%447 = and i32 %446, 63		; <i32> [#uses=1]
 	%448 = and i32 %445, -64		; <i32> [#uses=1]
 	%449 = or i32 %447, %448		; <i32> [#uses=2]
-	%.pre25.i = load double* %351, align 4		; <double> [#uses=1]
-	%.pre26.i = load double* %353, align 4		; <double> [#uses=1]
+	%.pre25.i = load double, double* %351, align 4		; <double> [#uses=1]
+	%.pre26.i = load double, double* %353, align 4		; <double> [#uses=1]
 	br label %bb16.i
 
 bb16.i:		; preds = %bb15.i, %bb14.i
@@ -609,37 +609,37 @@ bb16.i:		; preds = %bb15.i, %bb14.i
 	%.pn.in.i = xor i32 %.pn.in.in.i, 32		; <i32> [#uses=1]
 	%.pn3.i = inttoptr i32 %.pn3.in.i to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
 	%.pn.i = inttoptr i32 %.pn.in.i to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%v1.1.in.i = getelementptr %struct.edge_rec* %.pn3.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%v2.1.in.i = getelementptr %struct.edge_rec* %.pn.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%v3.1.in.i = getelementptr %struct.edge_rec* %rcand.2.pn.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%v1.1.i = load %struct.VERTEX** %v1.1.in.i		; <%struct.VERTEX*> [#uses=3]
-	%v2.1.i = load %struct.VERTEX** %v2.1.in.i		; <%struct.VERTEX*> [#uses=3]
-	%v3.1.i = load %struct.VERTEX** %v3.1.in.i		; <%struct.VERTEX*> [#uses=3]
-	%452 = load double* %363, align 4		; <double> [#uses=3]
-	%453 = getelementptr %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%454 = load double* %453, align 4		; <double> [#uses=1]
+	%v1.1.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %.pn3.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%v2.1.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %.pn.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%v3.1.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %rcand.2.pn.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%v1.1.i = load %struct.VERTEX*, %struct.VERTEX** %v1.1.in.i		; <%struct.VERTEX*> [#uses=3]
+	%v2.1.i = load %struct.VERTEX*, %struct.VERTEX** %v2.1.in.i		; <%struct.VERTEX*> [#uses=3]
+	%v3.1.i = load %struct.VERTEX*, %struct.VERTEX** %v3.1.in.i		; <%struct.VERTEX*> [#uses=3]
+	%452 = load double, double* %363, align 4		; <double> [#uses=3]
+	%453 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%454 = load double, double* %453, align 4		; <double> [#uses=1]
 	%455 = fsub double %454, %451		; <double> [#uses=2]
-	%456 = getelementptr %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%457 = load double* %456, align 4		; <double> [#uses=1]
+	%456 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%457 = load double, double* %456, align 4		; <double> [#uses=1]
 	%458 = fsub double %457, %450		; <double> [#uses=2]
-	%459 = getelementptr %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 2		; <double*> [#uses=1]
-	%460 = load double* %459, align 4		; <double> [#uses=1]
-	%461 = getelementptr %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%462 = load double* %461, align 4		; <double> [#uses=1]
+	%459 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 2		; <double*> [#uses=1]
+	%460 = load double, double* %459, align 4		; <double> [#uses=1]
+	%461 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%462 = load double, double* %461, align 4		; <double> [#uses=1]
 	%463 = fsub double %462, %451		; <double> [#uses=2]
-	%464 = getelementptr %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%465 = load double* %464, align 4		; <double> [#uses=1]
+	%464 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%465 = load double, double* %464, align 4		; <double> [#uses=1]
 	%466 = fsub double %465, %450		; <double> [#uses=2]
-	%467 = getelementptr %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 2		; <double*> [#uses=1]
-	%468 = load double* %467, align 4		; <double> [#uses=1]
-	%469 = getelementptr %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%470 = load double* %469, align 4		; <double> [#uses=1]
+	%467 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 2		; <double*> [#uses=1]
+	%468 = load double, double* %467, align 4		; <double> [#uses=1]
+	%469 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%470 = load double, double* %469, align 4		; <double> [#uses=1]
 	%471 = fsub double %470, %451		; <double> [#uses=2]
-	%472 = getelementptr %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%473 = load double* %472, align 4		; <double> [#uses=1]
+	%472 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%473 = load double, double* %472, align 4		; <double> [#uses=1]
 	%474 = fsub double %473, %450		; <double> [#uses=2]
-	%475 = getelementptr %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 2		; <double*> [#uses=1]
-	%476 = load double* %475, align 4		; <double> [#uses=1]
+	%475 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 2		; <double*> [#uses=1]
+	%476 = load double, double* %475, align 4		; <double> [#uses=1]
 	%477 = fsub double %460, %452		; <double> [#uses=1]
 	%478 = fmul double %463, %474		; <double> [#uses=1]
 	%479 = fmul double %466, %471		; <double> [#uses=1]
@@ -662,8 +662,8 @@ bb16.i:		; preds = %bb15.i, %bb14.i
 
 bb17.loopexit.i:		; preds = %bb16.i
 	store %struct.edge_rec* %avail_edge.tmp.0, %struct.edge_rec** @avail_edge
-	%.pre27.i = load %struct.VERTEX** %170, align 4		; <%struct.VERTEX*> [#uses=1]
-	%.pre28.i = load %struct.VERTEX** %175, align 4		; <%struct.VERTEX*> [#uses=1]
+	%.pre27.i = load %struct.VERTEX*, %struct.VERTEX** %170, align 4		; <%struct.VERTEX*> [#uses=1]
+	%.pre28.i = load %struct.VERTEX*, %struct.VERTEX** %175, align 4		; <%struct.VERTEX*> [#uses=1]
 	br label %bb17.i
 
 bb17.i:		; preds = %bb17.loopexit.i, %bb13.i
@@ -673,20 +673,20 @@ bb17.i:		; preds = %bb17.loopexit.i, %bb13.i
 	%497 = ptrtoint %struct.edge_rec* %lcand.1.i to i32		; <i32> [#uses=1]
 	%498 = xor i32 %497, 32		; <i32> [#uses=1]
 	%499 = inttoptr i32 %498 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
-	%500 = getelementptr %struct.edge_rec* %499, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%501 = load %struct.VERTEX** %500, align 4		; <%struct.VERTEX*> [#uses=4]
-	%502 = getelementptr %struct.VERTEX* %496, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%503 = load double* %502, align 4		; <double> [#uses=1]
-	%504 = getelementptr %struct.VERTEX* %496, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%505 = load double* %504, align 4		; <double> [#uses=1]
-	%506 = getelementptr %struct.VERTEX* %501, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%507 = load double* %506, align 4		; <double> [#uses=2]
-	%508 = getelementptr %struct.VERTEX* %501, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%509 = load double* %508, align 4		; <double> [#uses=2]
-	%510 = getelementptr %struct.VERTEX* %495, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%511 = load double* %510, align 4		; <double> [#uses=3]
-	%512 = getelementptr %struct.VERTEX* %495, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%513 = load double* %512, align 4		; <double> [#uses=3]
+	%500 = getelementptr %struct.edge_rec, %struct.edge_rec* %499, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%501 = load %struct.VERTEX*, %struct.VERTEX** %500, align 4		; <%struct.VERTEX*> [#uses=4]
+	%502 = getelementptr %struct.VERTEX, %struct.VERTEX* %496, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%503 = load double, double* %502, align 4		; <double> [#uses=1]
+	%504 = getelementptr %struct.VERTEX, %struct.VERTEX* %496, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%505 = load double, double* %504, align 4		; <double> [#uses=1]
+	%506 = getelementptr %struct.VERTEX, %struct.VERTEX* %501, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%507 = load double, double* %506, align 4		; <double> [#uses=2]
+	%508 = getelementptr %struct.VERTEX, %struct.VERTEX* %501, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%509 = load double, double* %508, align 4		; <double> [#uses=2]
+	%510 = getelementptr %struct.VERTEX, %struct.VERTEX* %495, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%511 = load double, double* %510, align 4		; <double> [#uses=3]
+	%512 = getelementptr %struct.VERTEX, %struct.VERTEX* %495, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%513 = load double, double* %512, align 4		; <double> [#uses=3]
 	%514 = fsub double %503, %511		; <double> [#uses=2]
 	%515 = fsub double %509, %513		; <double> [#uses=1]
 	%516 = fmul double %514, %515		; <double> [#uses=1]
@@ -698,12 +698,12 @@ bb17.i:		; preds = %bb17.loopexit.i, %bb13.i
 	%522 = ptrtoint %struct.edge_rec* %rcand.1.i to i32		; <i32> [#uses=3]
 	%523 = xor i32 %522, 32		; <i32> [#uses=1]
 	%524 = inttoptr i32 %523 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%525 = getelementptr %struct.edge_rec* %524, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%526 = load %struct.VERTEX** %525, align 4		; <%struct.VERTEX*> [#uses=4]
-	%527 = getelementptr %struct.VERTEX* %526, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%528 = load double* %527, align 4		; <double> [#uses=4]
-	%529 = getelementptr %struct.VERTEX* %526, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%530 = load double* %529, align 4		; <double> [#uses=4]
+	%525 = getelementptr %struct.edge_rec, %struct.edge_rec* %524, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%526 = load %struct.VERTEX*, %struct.VERTEX** %525, align 4		; <%struct.VERTEX*> [#uses=4]
+	%527 = getelementptr %struct.VERTEX, %struct.VERTEX* %526, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%528 = load double, double* %527, align 4		; <double> [#uses=4]
+	%529 = getelementptr %struct.VERTEX, %struct.VERTEX* %526, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%530 = load double, double* %529, align 4		; <double> [#uses=4]
 	%531 = fsub double %530, %513		; <double> [#uses=1]
 	%532 = fmul double %514, %531		; <double> [#uses=1]
 	%533 = fsub double %528, %511		; <double> [#uses=1]
@@ -714,38 +714,38 @@ bb17.i:		; preds = %bb17.loopexit.i, %bb13.i
 	br i1 %537, label %bb21.i, label %do_merge.exit
 
 bb21.i:		; preds = %bb17.i
-	%538 = getelementptr %struct.edge_rec* %lcand.1.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%539 = load %struct.VERTEX** %538, align 4		; <%struct.VERTEX*> [#uses=3]
-	%540 = getelementptr %struct.edge_rec* %rcand.1.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%541 = load %struct.VERTEX** %540, align 4		; <%struct.VERTEX*> [#uses=3]
+	%538 = getelementptr %struct.edge_rec, %struct.edge_rec* %lcand.1.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%539 = load %struct.VERTEX*, %struct.VERTEX** %538, align 4		; <%struct.VERTEX*> [#uses=3]
+	%540 = getelementptr %struct.edge_rec, %struct.edge_rec* %rcand.1.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%541 = load %struct.VERTEX*, %struct.VERTEX** %540, align 4		; <%struct.VERTEX*> [#uses=3]
 	br i1 %521, label %bb22.i, label %bb24.i
 
 bb22.i:		; preds = %bb21.i
 	br i1 %536, label %bb23.i, label %bb25.i
 
 bb23.i:		; preds = %bb22.i
-	%542 = getelementptr %struct.VERTEX* %526, i32 0, i32 0, i32 2		; <double*> [#uses=1]
-	%543 = load double* %542, align 4		; <double> [#uses=3]
+	%542 = getelementptr %struct.VERTEX, %struct.VERTEX* %526, i32 0, i32 0, i32 2		; <double*> [#uses=1]
+	%543 = load double, double* %542, align 4		; <double> [#uses=3]
 	%544 = fsub double %507, %528		; <double> [#uses=2]
 	%545 = fsub double %509, %530		; <double> [#uses=2]
-	%546 = getelementptr %struct.VERTEX* %501, i32 0, i32 0, i32 2		; <double*> [#uses=1]
-	%547 = load double* %546, align 4		; <double> [#uses=1]
-	%548 = getelementptr %struct.VERTEX* %539, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%549 = load double* %548, align 4		; <double> [#uses=1]
+	%546 = getelementptr %struct.VERTEX, %struct.VERTEX* %501, i32 0, i32 0, i32 2		; <double*> [#uses=1]
+	%547 = load double, double* %546, align 4		; <double> [#uses=1]
+	%548 = getelementptr %struct.VERTEX, %struct.VERTEX* %539, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%549 = load double, double* %548, align 4		; <double> [#uses=1]
 	%550 = fsub double %549, %528		; <double> [#uses=2]
-	%551 = getelementptr %struct.VERTEX* %539, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%552 = load double* %551, align 4		; <double> [#uses=1]
+	%551 = getelementptr %struct.VERTEX, %struct.VERTEX* %539, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%552 = load double, double* %551, align 4		; <double> [#uses=1]
 	%553 = fsub double %552, %530		; <double> [#uses=2]
-	%554 = getelementptr %struct.VERTEX* %539, i32 0, i32 0, i32 2		; <double*> [#uses=1]
-	%555 = load double* %554, align 4		; <double> [#uses=1]
-	%556 = getelementptr %struct.VERTEX* %541, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%557 = load double* %556, align 4		; <double> [#uses=1]
+	%554 = getelementptr %struct.VERTEX, %struct.VERTEX* %539, i32 0, i32 0, i32 2		; <double*> [#uses=1]
+	%555 = load double, double* %554, align 4		; <double> [#uses=1]
+	%556 = getelementptr %struct.VERTEX, %struct.VERTEX* %541, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%557 = load double, double* %556, align 4		; <double> [#uses=1]
 	%558 = fsub double %557, %528		; <double> [#uses=2]
-	%559 = getelementptr %struct.VERTEX* %541, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%560 = load double* %559, align 4		; <double> [#uses=1]
+	%559 = getelementptr %struct.VERTEX, %struct.VERTEX* %541, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%560 = load double, double* %559, align 4		; <double> [#uses=1]
 	%561 = fsub double %560, %530		; <double> [#uses=2]
-	%562 = getelementptr %struct.VERTEX* %541, i32 0, i32 0, i32 2		; <double*> [#uses=1]
-	%563 = load double* %562, align 4		; <double> [#uses=1]
+	%562 = getelementptr %struct.VERTEX, %struct.VERTEX* %541, i32 0, i32 0, i32 2		; <double*> [#uses=1]
+	%563 = load double, double* %562, align 4		; <double> [#uses=1]
 	%564 = fsub double %547, %543		; <double> [#uses=1]
 	%565 = fmul double %550, %561		; <double> [#uses=1]
 	%566 = fmul double %553, %558		; <double> [#uses=1]
@@ -772,8 +772,8 @@ bb24.i:		; preds = %bb23.i, %bb21.i
 	%584 = and i32 %522, -64		; <i32> [#uses=1]
 	%585 = or i32 %583, %584		; <i32> [#uses=1]
 	%586 = inttoptr i32 %585 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%587 = getelementptr %struct.edge_rec* %586, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%588 = load %struct.edge_rec** %587, align 4		; <%struct.edge_rec*> [#uses=1]
+	%587 = getelementptr %struct.edge_rec, %struct.edge_rec* %586, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%588 = load %struct.edge_rec*, %struct.edge_rec** %587, align 4		; <%struct.edge_rec*> [#uses=1]
 	%589 = ptrtoint %struct.edge_rec* %588 to i32		; <i32> [#uses=2]
 	%590 = add i32 %589, 16		; <i32> [#uses=1]
 	%591 = and i32 %590, 63		; <i32> [#uses=1]
@@ -781,76 +781,76 @@ bb24.i:		; preds = %bb23.i, %bb21.i
 	%593 = or i32 %591, %592		; <i32> [#uses=1]
 	%594 = inttoptr i32 %593 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
 	%595 = call  %struct.edge_rec* @alloc_edge() nounwind		; <%struct.edge_rec*> [#uses=5]
-	%596 = getelementptr %struct.edge_rec* %595, i32 0, i32 1		; <%struct.edge_rec**> [#uses=4]
+	%596 = getelementptr %struct.edge_rec, %struct.edge_rec* %595, i32 0, i32 1		; <%struct.edge_rec**> [#uses=4]
 	store %struct.edge_rec* %595, %struct.edge_rec** %596, align 4
-	%597 = getelementptr %struct.edge_rec* %595, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%597 = getelementptr %struct.edge_rec, %struct.edge_rec* %595, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
 	store %struct.VERTEX* %526, %struct.VERTEX** %597, align 4
 	%598 = ptrtoint %struct.edge_rec* %595 to i32		; <i32> [#uses=5]
 	%599 = add i32 %598, 16		; <i32> [#uses=1]
 	%600 = inttoptr i32 %599 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
 	%601 = add i32 %598, 48		; <i32> [#uses=1]
 	%602 = inttoptr i32 %601 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
-	%603 = getelementptr %struct.edge_rec* %600, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%603 = getelementptr %struct.edge_rec, %struct.edge_rec* %600, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %602, %struct.edge_rec** %603, align 4
 	%604 = add i32 %598, 32		; <i32> [#uses=1]
 	%605 = inttoptr i32 %604 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=3]
-	%606 = getelementptr %struct.edge_rec* %605, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%606 = getelementptr %struct.edge_rec, %struct.edge_rec* %605, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %605, %struct.edge_rec** %606, align 4
-	%607 = getelementptr %struct.edge_rec* %605, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%607 = getelementptr %struct.edge_rec, %struct.edge_rec* %605, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
 	store %struct.VERTEX* %495, %struct.VERTEX** %607, align 4
-	%608 = getelementptr %struct.edge_rec* %602, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%608 = getelementptr %struct.edge_rec, %struct.edge_rec* %602, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %600, %struct.edge_rec** %608, align 4
-	%609 = load %struct.edge_rec** %596, align 4		; <%struct.edge_rec*> [#uses=1]
+	%609 = load %struct.edge_rec*, %struct.edge_rec** %596, align 4		; <%struct.edge_rec*> [#uses=1]
 	%610 = ptrtoint %struct.edge_rec* %609 to i32		; <i32> [#uses=2]
 	%611 = add i32 %610, 16		; <i32> [#uses=1]
 	%612 = and i32 %611, 63		; <i32> [#uses=1]
 	%613 = and i32 %610, -64		; <i32> [#uses=1]
 	%614 = or i32 %612, %613		; <i32> [#uses=1]
 	%615 = inttoptr i32 %614 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%616 = getelementptr %struct.edge_rec* %594, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%617 = load %struct.edge_rec** %616, align 4		; <%struct.edge_rec*> [#uses=1]
+	%616 = getelementptr %struct.edge_rec, %struct.edge_rec* %594, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%617 = load %struct.edge_rec*, %struct.edge_rec** %616, align 4		; <%struct.edge_rec*> [#uses=1]
 	%618 = ptrtoint %struct.edge_rec* %617 to i32		; <i32> [#uses=2]
 	%619 = add i32 %618, 16		; <i32> [#uses=1]
 	%620 = and i32 %619, 63		; <i32> [#uses=1]
 	%621 = and i32 %618, -64		; <i32> [#uses=1]
 	%622 = or i32 %620, %621		; <i32> [#uses=1]
 	%623 = inttoptr i32 %622 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%624 = getelementptr %struct.edge_rec* %623, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%625 = load %struct.edge_rec** %624, align 4		; <%struct.edge_rec*> [#uses=1]
-	%626 = getelementptr %struct.edge_rec* %615, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%627 = load %struct.edge_rec** %626, align 4		; <%struct.edge_rec*> [#uses=1]
+	%624 = getelementptr %struct.edge_rec, %struct.edge_rec* %623, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%625 = load %struct.edge_rec*, %struct.edge_rec** %624, align 4		; <%struct.edge_rec*> [#uses=1]
+	%626 = getelementptr %struct.edge_rec, %struct.edge_rec* %615, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%627 = load %struct.edge_rec*, %struct.edge_rec** %626, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %625, %struct.edge_rec** %626, align 4
 	store %struct.edge_rec* %627, %struct.edge_rec** %624, align 4
-	%628 = load %struct.edge_rec** %596, align 4		; <%struct.edge_rec*> [#uses=1]
-	%629 = load %struct.edge_rec** %616, align 4		; <%struct.edge_rec*> [#uses=1]
+	%628 = load %struct.edge_rec*, %struct.edge_rec** %596, align 4		; <%struct.edge_rec*> [#uses=1]
+	%629 = load %struct.edge_rec*, %struct.edge_rec** %616, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %628, %struct.edge_rec** %616, align 4
 	store %struct.edge_rec* %629, %struct.edge_rec** %596, align 4
 	%630 = xor i32 %598, 32		; <i32> [#uses=2]
 	%631 = inttoptr i32 %630 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%632 = getelementptr %struct.edge_rec* %631, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%633 = load %struct.edge_rec** %632, align 4		; <%struct.edge_rec*> [#uses=1]
+	%632 = getelementptr %struct.edge_rec, %struct.edge_rec* %631, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%633 = load %struct.edge_rec*, %struct.edge_rec** %632, align 4		; <%struct.edge_rec*> [#uses=1]
 	%634 = ptrtoint %struct.edge_rec* %633 to i32		; <i32> [#uses=2]
 	%635 = add i32 %634, 16		; <i32> [#uses=1]
 	%636 = and i32 %635, 63		; <i32> [#uses=1]
 	%637 = and i32 %634, -64		; <i32> [#uses=1]
 	%638 = or i32 %636, %637		; <i32> [#uses=1]
 	%639 = inttoptr i32 %638 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%640 = getelementptr %struct.edge_rec* %174, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%641 = load %struct.edge_rec** %640, align 4		; <%struct.edge_rec*> [#uses=1]
+	%640 = getelementptr %struct.edge_rec, %struct.edge_rec* %174, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%641 = load %struct.edge_rec*, %struct.edge_rec** %640, align 4		; <%struct.edge_rec*> [#uses=1]
 	%642 = ptrtoint %struct.edge_rec* %641 to i32		; <i32> [#uses=2]
 	%643 = add i32 %642, 16		; <i32> [#uses=1]
 	%644 = and i32 %643, 63		; <i32> [#uses=1]
 	%645 = and i32 %642, -64		; <i32> [#uses=1]
 	%646 = or i32 %644, %645		; <i32> [#uses=1]
 	%647 = inttoptr i32 %646 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%648 = getelementptr %struct.edge_rec* %647, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%649 = load %struct.edge_rec** %648, align 4		; <%struct.edge_rec*> [#uses=1]
-	%650 = getelementptr %struct.edge_rec* %639, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%651 = load %struct.edge_rec** %650, align 4		; <%struct.edge_rec*> [#uses=1]
+	%648 = getelementptr %struct.edge_rec, %struct.edge_rec* %647, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%649 = load %struct.edge_rec*, %struct.edge_rec** %648, align 4		; <%struct.edge_rec*> [#uses=1]
+	%650 = getelementptr %struct.edge_rec, %struct.edge_rec* %639, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%651 = load %struct.edge_rec*, %struct.edge_rec** %650, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %649, %struct.edge_rec** %650, align 4
 	store %struct.edge_rec* %651, %struct.edge_rec** %648, align 4
-	%652 = load %struct.edge_rec** %632, align 4		; <%struct.edge_rec*> [#uses=1]
-	%653 = load %struct.edge_rec** %640, align 4		; <%struct.edge_rec*> [#uses=1]
+	%652 = load %struct.edge_rec*, %struct.edge_rec** %632, align 4		; <%struct.edge_rec*> [#uses=1]
+	%653 = load %struct.edge_rec*, %struct.edge_rec** %640, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %652, %struct.edge_rec** %640, align 4
 	store %struct.edge_rec* %653, %struct.edge_rec** %632, align 4
 	%654 = add i32 %630, 48		; <i32> [#uses=1]
@@ -858,8 +858,8 @@ bb24.i:		; preds = %bb23.i, %bb21.i
 	%656 = and i32 %598, -64		; <i32> [#uses=1]
 	%657 = or i32 %655, %656		; <i32> [#uses=1]
 	%658 = inttoptr i32 %657 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%659 = getelementptr %struct.edge_rec* %658, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%660 = load %struct.edge_rec** %659, align 4		; <%struct.edge_rec*> [#uses=1]
+	%659 = getelementptr %struct.edge_rec, %struct.edge_rec* %658, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%660 = load %struct.edge_rec*, %struct.edge_rec** %659, align 4		; <%struct.edge_rec*> [#uses=1]
 	%661 = ptrtoint %struct.edge_rec* %660 to i32		; <i32> [#uses=2]
 	%662 = add i32 %661, 16		; <i32> [#uses=1]
 	%663 = and i32 %662, 63		; <i32> [#uses=1]
@@ -874,8 +874,8 @@ bb25.i:		; preds = %bb23.i, %bb22.i
 	%669 = and i32 %172, -64		; <i32> [#uses=1]
 	%670 = or i32 %668, %669		; <i32> [#uses=1]
 	%671 = inttoptr i32 %670 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%672 = getelementptr %struct.edge_rec* %671, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%673 = load %struct.edge_rec** %672, align 4		; <%struct.edge_rec*> [#uses=1]
+	%672 = getelementptr %struct.edge_rec, %struct.edge_rec* %671, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%673 = load %struct.edge_rec*, %struct.edge_rec** %672, align 4		; <%struct.edge_rec*> [#uses=1]
 	%674 = ptrtoint %struct.edge_rec* %673 to i32		; <i32> [#uses=2]
 	%675 = add i32 %674, 16		; <i32> [#uses=1]
 	%676 = and i32 %675, 63		; <i32> [#uses=1]
@@ -883,84 +883,84 @@ bb25.i:		; preds = %bb23.i, %bb22.i
 	%678 = or i32 %676, %677		; <i32> [#uses=1]
 	%679 = inttoptr i32 %678 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
 	%680 = call  %struct.edge_rec* @alloc_edge() nounwind		; <%struct.edge_rec*> [#uses=4]
-	%681 = getelementptr %struct.edge_rec* %680, i32 0, i32 1		; <%struct.edge_rec**> [#uses=5]
+	%681 = getelementptr %struct.edge_rec, %struct.edge_rec* %680, i32 0, i32 1		; <%struct.edge_rec**> [#uses=5]
 	store %struct.edge_rec* %680, %struct.edge_rec** %681, align 4
-	%682 = getelementptr %struct.edge_rec* %680, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%682 = getelementptr %struct.edge_rec, %struct.edge_rec* %680, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
 	store %struct.VERTEX* %501, %struct.VERTEX** %682, align 4
 	%683 = ptrtoint %struct.edge_rec* %680 to i32		; <i32> [#uses=4]
 	%684 = add i32 %683, 16		; <i32> [#uses=1]
 	%685 = inttoptr i32 %684 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
 	%686 = add i32 %683, 48		; <i32> [#uses=1]
 	%687 = inttoptr i32 %686 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
-	%688 = getelementptr %struct.edge_rec* %685, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%688 = getelementptr %struct.edge_rec, %struct.edge_rec* %685, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %687, %struct.edge_rec** %688, align 4
 	%689 = add i32 %683, 32		; <i32> [#uses=1]
 	%690 = inttoptr i32 %689 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=3]
-	%691 = getelementptr %struct.edge_rec* %690, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%691 = getelementptr %struct.edge_rec, %struct.edge_rec* %690, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %690, %struct.edge_rec** %691, align 4
-	%692 = getelementptr %struct.edge_rec* %690, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%692 = getelementptr %struct.edge_rec, %struct.edge_rec* %690, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
 	store %struct.VERTEX* %496, %struct.VERTEX** %692, align 4
-	%693 = getelementptr %struct.edge_rec* %687, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%693 = getelementptr %struct.edge_rec, %struct.edge_rec* %687, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %685, %struct.edge_rec** %693, align 4
-	%694 = load %struct.edge_rec** %681, align 4		; <%struct.edge_rec*> [#uses=1]
+	%694 = load %struct.edge_rec*, %struct.edge_rec** %681, align 4		; <%struct.edge_rec*> [#uses=1]
 	%695 = ptrtoint %struct.edge_rec* %694 to i32		; <i32> [#uses=2]
 	%696 = add i32 %695, 16		; <i32> [#uses=1]
 	%697 = and i32 %696, 63		; <i32> [#uses=1]
 	%698 = and i32 %695, -64		; <i32> [#uses=1]
 	%699 = or i32 %697, %698		; <i32> [#uses=1]
 	%700 = inttoptr i32 %699 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%701 = getelementptr %struct.edge_rec* %499, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%702 = load %struct.edge_rec** %701, align 4		; <%struct.edge_rec*> [#uses=1]
+	%701 = getelementptr %struct.edge_rec, %struct.edge_rec* %499, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%702 = load %struct.edge_rec*, %struct.edge_rec** %701, align 4		; <%struct.edge_rec*> [#uses=1]
 	%703 = ptrtoint %struct.edge_rec* %702 to i32		; <i32> [#uses=2]
 	%704 = add i32 %703, 16		; <i32> [#uses=1]
 	%705 = and i32 %704, 63		; <i32> [#uses=1]
 	%706 = and i32 %703, -64		; <i32> [#uses=1]
 	%707 = or i32 %705, %706		; <i32> [#uses=1]
 	%708 = inttoptr i32 %707 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%709 = getelementptr %struct.edge_rec* %708, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%710 = load %struct.edge_rec** %709, align 4		; <%struct.edge_rec*> [#uses=1]
-	%711 = getelementptr %struct.edge_rec* %700, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%712 = load %struct.edge_rec** %711, align 4		; <%struct.edge_rec*> [#uses=1]
+	%709 = getelementptr %struct.edge_rec, %struct.edge_rec* %708, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%710 = load %struct.edge_rec*, %struct.edge_rec** %709, align 4		; <%struct.edge_rec*> [#uses=1]
+	%711 = getelementptr %struct.edge_rec, %struct.edge_rec* %700, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%712 = load %struct.edge_rec*, %struct.edge_rec** %711, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %710, %struct.edge_rec** %711, align 4
 	store %struct.edge_rec* %712, %struct.edge_rec** %709, align 4
-	%713 = load %struct.edge_rec** %681, align 4		; <%struct.edge_rec*> [#uses=1]
-	%714 = load %struct.edge_rec** %701, align 4		; <%struct.edge_rec*> [#uses=1]
+	%713 = load %struct.edge_rec*, %struct.edge_rec** %681, align 4		; <%struct.edge_rec*> [#uses=1]
+	%714 = load %struct.edge_rec*, %struct.edge_rec** %701, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %713, %struct.edge_rec** %701, align 4
 	store %struct.edge_rec* %714, %struct.edge_rec** %681, align 4
 	%715 = xor i32 %683, 32		; <i32> [#uses=1]
 	%716 = inttoptr i32 %715 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
-	%717 = getelementptr %struct.edge_rec* %716, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%718 = load %struct.edge_rec** %717, align 4		; <%struct.edge_rec*> [#uses=1]
+	%717 = getelementptr %struct.edge_rec, %struct.edge_rec* %716, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%718 = load %struct.edge_rec*, %struct.edge_rec** %717, align 4		; <%struct.edge_rec*> [#uses=1]
 	%719 = ptrtoint %struct.edge_rec* %718 to i32		; <i32> [#uses=2]
 	%720 = add i32 %719, 16		; <i32> [#uses=1]
 	%721 = and i32 %720, 63		; <i32> [#uses=1]
 	%722 = and i32 %719, -64		; <i32> [#uses=1]
 	%723 = or i32 %721, %722		; <i32> [#uses=1]
 	%724 = inttoptr i32 %723 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%725 = getelementptr %struct.edge_rec* %679, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%726 = load %struct.edge_rec** %725, align 4		; <%struct.edge_rec*> [#uses=1]
+	%725 = getelementptr %struct.edge_rec, %struct.edge_rec* %679, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%726 = load %struct.edge_rec*, %struct.edge_rec** %725, align 4		; <%struct.edge_rec*> [#uses=1]
 	%727 = ptrtoint %struct.edge_rec* %726 to i32		; <i32> [#uses=2]
 	%728 = add i32 %727, 16		; <i32> [#uses=1]
 	%729 = and i32 %728, 63		; <i32> [#uses=1]
 	%730 = and i32 %727, -64		; <i32> [#uses=1]
 	%731 = or i32 %729, %730		; <i32> [#uses=1]
 	%732 = inttoptr i32 %731 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%733 = getelementptr %struct.edge_rec* %732, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%734 = load %struct.edge_rec** %733, align 4		; <%struct.edge_rec*> [#uses=1]
-	%735 = getelementptr %struct.edge_rec* %724, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%736 = load %struct.edge_rec** %735, align 4		; <%struct.edge_rec*> [#uses=1]
+	%733 = getelementptr %struct.edge_rec, %struct.edge_rec* %732, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%734 = load %struct.edge_rec*, %struct.edge_rec** %733, align 4		; <%struct.edge_rec*> [#uses=1]
+	%735 = getelementptr %struct.edge_rec, %struct.edge_rec* %724, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%736 = load %struct.edge_rec*, %struct.edge_rec** %735, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %734, %struct.edge_rec** %735, align 4
 	store %struct.edge_rec* %736, %struct.edge_rec** %733, align 4
-	%737 = load %struct.edge_rec** %717, align 4		; <%struct.edge_rec*> [#uses=1]
-	%738 = load %struct.edge_rec** %725, align 4		; <%struct.edge_rec*> [#uses=1]
+	%737 = load %struct.edge_rec*, %struct.edge_rec** %717, align 4		; <%struct.edge_rec*> [#uses=1]
+	%738 = load %struct.edge_rec*, %struct.edge_rec** %725, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %737, %struct.edge_rec** %725, align 4
 	store %struct.edge_rec* %738, %struct.edge_rec** %717, align 4
-	%739 = load %struct.edge_rec** %681, align 4		; <%struct.edge_rec*> [#uses=1]
+	%739 = load %struct.edge_rec*, %struct.edge_rec** %681, align 4		; <%struct.edge_rec*> [#uses=1]
 	br label %bb9.i
 
 do_merge.exit:		; preds = %bb17.i
-	%740 = getelementptr %struct.edge_rec* %ldo_addr.0.ph.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%741 = load %struct.VERTEX** %740, align 4		; <%struct.VERTEX*> [#uses=1]
+	%740 = getelementptr %struct.edge_rec, %struct.edge_rec* %ldo_addr.0.ph.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%741 = load %struct.VERTEX*, %struct.VERTEX** %740, align 4		; <%struct.VERTEX*> [#uses=1]
 	%742 = icmp eq %struct.VERTEX* %741, %tree_addr.0.i		; <i1> [#uses=1]
 	br i1 %742, label %bb5.loopexit, label %bb2
 
@@ -969,29 +969,29 @@ bb2:		; preds = %bb2, %do_merge.exit
 	%743 = ptrtoint %struct.edge_rec* %ldo.07 to i32		; <i32> [#uses=1]
 	%744 = xor i32 %743, 32		; <i32> [#uses=1]
 	%745 = inttoptr i32 %744 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%746 = getelementptr %struct.edge_rec* %745, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%747 = load %struct.edge_rec** %746, align 4		; <%struct.edge_rec*> [#uses=3]
-	%748 = getelementptr %struct.edge_rec* %747, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%749 = load %struct.VERTEX** %748, align 4		; <%struct.VERTEX*> [#uses=1]
+	%746 = getelementptr %struct.edge_rec, %struct.edge_rec* %745, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%747 = load %struct.edge_rec*, %struct.edge_rec** %746, align 4		; <%struct.edge_rec*> [#uses=3]
+	%748 = getelementptr %struct.edge_rec, %struct.edge_rec* %747, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%749 = load %struct.VERTEX*, %struct.VERTEX** %748, align 4		; <%struct.VERTEX*> [#uses=1]
 	%750 = icmp eq %struct.VERTEX* %749, %tree_addr.0.i		; <i1> [#uses=1]
 	br i1 %750, label %bb5.loopexit, label %bb2
 
 bb4:		; preds = %bb5.loopexit, %bb4
 	%rdo.05 = phi %struct.edge_rec* [ %755, %bb4 ], [ %rdo_addr.0.i, %bb5.loopexit ]		; <%struct.edge_rec*> [#uses=1]
-	%751 = getelementptr %struct.edge_rec* %rdo.05, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%752 = load %struct.edge_rec** %751, align 4		; <%struct.edge_rec*> [#uses=1]
+	%751 = getelementptr %struct.edge_rec, %struct.edge_rec* %rdo.05, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%752 = load %struct.edge_rec*, %struct.edge_rec** %751, align 4		; <%struct.edge_rec*> [#uses=1]
 	%753 = ptrtoint %struct.edge_rec* %752 to i32		; <i32> [#uses=1]
 	%754 = xor i32 %753, 32		; <i32> [#uses=1]
 	%755 = inttoptr i32 %754 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=3]
-	%756 = getelementptr %struct.edge_rec* %755, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%757 = load %struct.VERTEX** %756, align 4		; <%struct.VERTEX*> [#uses=1]
+	%756 = getelementptr %struct.edge_rec, %struct.edge_rec* %755, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%757 = load %struct.VERTEX*, %struct.VERTEX** %756, align 4		; <%struct.VERTEX*> [#uses=1]
 	%758 = icmp eq %struct.VERTEX* %757, %extra		; <i1> [#uses=1]
 	br i1 %758, label %bb6, label %bb4
 
 bb5.loopexit:		; preds = %bb2, %do_merge.exit
 	%ldo.0.lcssa = phi %struct.edge_rec* [ %ldo_addr.0.ph.i, %do_merge.exit ], [ %747, %bb2 ]		; <%struct.edge_rec*> [#uses=1]
-	%759 = getelementptr %struct.edge_rec* %rdo_addr.0.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%760 = load %struct.VERTEX** %759, align 4		; <%struct.VERTEX*> [#uses=1]
+	%759 = getelementptr %struct.edge_rec, %struct.edge_rec* %rdo_addr.0.i, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%760 = load %struct.VERTEX*, %struct.VERTEX** %759, align 4		; <%struct.VERTEX*> [#uses=1]
 	%761 = icmp eq %struct.VERTEX* %760, %extra		; <i1> [#uses=1]
 	br i1 %761, label %bb6, label %bb4
 
@@ -1002,17 +1002,17 @@ bb6:		; preds = %bb5.loopexit, %bb4
 	br label %bb15
 
 bb7:		; preds = %bb
-	%762 = getelementptr %struct.VERTEX* %tree, i32 0, i32 1		; <%struct.VERTEX**> [#uses=1]
-	%763 = load %struct.VERTEX** %762, align 4		; <%struct.VERTEX*> [#uses=4]
+	%762 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 1		; <%struct.VERTEX**> [#uses=1]
+	%763 = load %struct.VERTEX*, %struct.VERTEX** %762, align 4		; <%struct.VERTEX*> [#uses=4]
 	%764 = icmp eq %struct.VERTEX* %763, null		; <i1> [#uses=1]
 	%765 = call  %struct.edge_rec* @alloc_edge() nounwind		; <%struct.edge_rec*> [#uses=5]
-	%766 = getelementptr %struct.edge_rec* %765, i32 0, i32 1		; <%struct.edge_rec**> [#uses=4]
+	%766 = getelementptr %struct.edge_rec, %struct.edge_rec* %765, i32 0, i32 1		; <%struct.edge_rec**> [#uses=4]
 	store %struct.edge_rec* %765, %struct.edge_rec** %766, align 4
-	%767 = getelementptr %struct.edge_rec* %765, i32 0, i32 0		; <%struct.VERTEX**> [#uses=3]
+	%767 = getelementptr %struct.edge_rec, %struct.edge_rec* %765, i32 0, i32 0		; <%struct.VERTEX**> [#uses=3]
 	br i1 %764, label %bb10, label %bb11
 
 bb8:		; preds = %entry
-	%768 = call  i32 @puts(i8* getelementptr ([21 x i8]* @_2E_str7, i32 0, i32 0)) nounwind		; <i32> [#uses=0]
+	%768 = call  i32 @puts(i8* getelementptr ([21 x i8], [21 x i8]* @_2E_str7, i32 0, i32 0)) nounwind		; <i32> [#uses=0]
 	call  void @exit(i32 -1) noreturn nounwind
 	unreachable
 
@@ -1023,15 +1023,15 @@ bb10:		; preds = %bb7
 	%771 = inttoptr i32 %770 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
 	%772 = add i32 %769, 48		; <i32> [#uses=1]
 	%773 = inttoptr i32 %772 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
-	%774 = getelementptr %struct.edge_rec* %771, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%774 = getelementptr %struct.edge_rec, %struct.edge_rec* %771, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %773, %struct.edge_rec** %774, align 4
 	%775 = add i32 %769, 32		; <i32> [#uses=1]
 	%776 = inttoptr i32 %775 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=3]
-	%777 = getelementptr %struct.edge_rec* %776, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%777 = getelementptr %struct.edge_rec, %struct.edge_rec* %776, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %776, %struct.edge_rec** %777, align 4
-	%778 = getelementptr %struct.edge_rec* %776, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%778 = getelementptr %struct.edge_rec, %struct.edge_rec* %776, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
 	store %struct.VERTEX* %extra, %struct.VERTEX** %778, align 4
-	%779 = getelementptr %struct.edge_rec* %773, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%779 = getelementptr %struct.edge_rec, %struct.edge_rec* %773, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %771, %struct.edge_rec** %779, align 4
 	%780 = xor i32 %769, 32		; <i32> [#uses=1]
 	br label %bb15
@@ -1043,164 +1043,164 @@ bb11:		; preds = %bb7
 	%783 = inttoptr i32 %782 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
 	%784 = add i32 %781, 48		; <i32> [#uses=1]
 	%785 = inttoptr i32 %784 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
-	%786 = getelementptr %struct.edge_rec* %783, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%786 = getelementptr %struct.edge_rec, %struct.edge_rec* %783, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %785, %struct.edge_rec** %786, align 4
 	%787 = add i32 %781, 32		; <i32> [#uses=1]
 	%788 = inttoptr i32 %787 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=3]
-	%789 = getelementptr %struct.edge_rec* %788, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%789 = getelementptr %struct.edge_rec, %struct.edge_rec* %788, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %788, %struct.edge_rec** %789, align 4
-	%790 = getelementptr %struct.edge_rec* %788, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%790 = getelementptr %struct.edge_rec, %struct.edge_rec* %788, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
 	store %struct.VERTEX* %tree, %struct.VERTEX** %790, align 4
-	%791 = getelementptr %struct.edge_rec* %785, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%791 = getelementptr %struct.edge_rec, %struct.edge_rec* %785, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %783, %struct.edge_rec** %791, align 4
 	%792 = call  %struct.edge_rec* @alloc_edge() nounwind		; <%struct.edge_rec*> [#uses=4]
-	%793 = getelementptr %struct.edge_rec* %792, i32 0, i32 1		; <%struct.edge_rec**> [#uses=4]
+	%793 = getelementptr %struct.edge_rec, %struct.edge_rec* %792, i32 0, i32 1		; <%struct.edge_rec**> [#uses=4]
 	store %struct.edge_rec* %792, %struct.edge_rec** %793, align 4
-	%794 = getelementptr %struct.edge_rec* %792, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%794 = getelementptr %struct.edge_rec, %struct.edge_rec* %792, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
 	store %struct.VERTEX* %tree, %struct.VERTEX** %794, align 4
 	%795 = ptrtoint %struct.edge_rec* %792 to i32		; <i32> [#uses=5]
 	%796 = add i32 %795, 16		; <i32> [#uses=1]
 	%797 = inttoptr i32 %796 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
 	%798 = add i32 %795, 48		; <i32> [#uses=2]
 	%799 = inttoptr i32 %798 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
-	%800 = getelementptr %struct.edge_rec* %797, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%800 = getelementptr %struct.edge_rec, %struct.edge_rec* %797, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %799, %struct.edge_rec** %800, align 4
 	%801 = add i32 %795, 32		; <i32> [#uses=1]
 	%802 = inttoptr i32 %801 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=3]
-	%803 = getelementptr %struct.edge_rec* %802, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%803 = getelementptr %struct.edge_rec, %struct.edge_rec* %802, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %802, %struct.edge_rec** %803, align 4
-	%804 = getelementptr %struct.edge_rec* %802, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%804 = getelementptr %struct.edge_rec, %struct.edge_rec* %802, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
 	store %struct.VERTEX* %extra, %struct.VERTEX** %804, align 4
-	%805 = getelementptr %struct.edge_rec* %799, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%805 = getelementptr %struct.edge_rec, %struct.edge_rec* %799, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %797, %struct.edge_rec** %805, align 4
 	%806 = xor i32 %781, 32		; <i32> [#uses=1]
 	%807 = inttoptr i32 %806 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%808 = getelementptr %struct.edge_rec* %807, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%809 = load %struct.edge_rec** %808, align 4		; <%struct.edge_rec*> [#uses=1]
+	%808 = getelementptr %struct.edge_rec, %struct.edge_rec* %807, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%809 = load %struct.edge_rec*, %struct.edge_rec** %808, align 4		; <%struct.edge_rec*> [#uses=1]
 	%810 = ptrtoint %struct.edge_rec* %809 to i32		; <i32> [#uses=2]
 	%811 = add i32 %810, 16		; <i32> [#uses=1]
 	%812 = and i32 %811, 63		; <i32> [#uses=1]
 	%813 = and i32 %810, -64		; <i32> [#uses=1]
 	%814 = or i32 %812, %813		; <i32> [#uses=1]
 	%815 = inttoptr i32 %814 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%816 = load %struct.edge_rec** %793, align 4		; <%struct.edge_rec*> [#uses=1]
+	%816 = load %struct.edge_rec*, %struct.edge_rec** %793, align 4		; <%struct.edge_rec*> [#uses=1]
 	%817 = ptrtoint %struct.edge_rec* %816 to i32		; <i32> [#uses=2]
 	%818 = add i32 %817, 16		; <i32> [#uses=1]
 	%819 = and i32 %818, 63		; <i32> [#uses=1]
 	%820 = and i32 %817, -64		; <i32> [#uses=1]
 	%821 = or i32 %819, %820		; <i32> [#uses=1]
 	%822 = inttoptr i32 %821 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%823 = getelementptr %struct.edge_rec* %822, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%824 = load %struct.edge_rec** %823, align 4		; <%struct.edge_rec*> [#uses=1]
-	%825 = getelementptr %struct.edge_rec* %815, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%826 = load %struct.edge_rec** %825, align 4		; <%struct.edge_rec*> [#uses=1]
+	%823 = getelementptr %struct.edge_rec, %struct.edge_rec* %822, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%824 = load %struct.edge_rec*, %struct.edge_rec** %823, align 4		; <%struct.edge_rec*> [#uses=1]
+	%825 = getelementptr %struct.edge_rec, %struct.edge_rec* %815, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%826 = load %struct.edge_rec*, %struct.edge_rec** %825, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %824, %struct.edge_rec** %825, align 4
 	store %struct.edge_rec* %826, %struct.edge_rec** %823, align 4
-	%827 = load %struct.edge_rec** %808, align 4		; <%struct.edge_rec*> [#uses=1]
-	%828 = load %struct.edge_rec** %793, align 4		; <%struct.edge_rec*> [#uses=1]
+	%827 = load %struct.edge_rec*, %struct.edge_rec** %808, align 4		; <%struct.edge_rec*> [#uses=1]
+	%828 = load %struct.edge_rec*, %struct.edge_rec** %793, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %827, %struct.edge_rec** %793, align 4
 	store %struct.edge_rec* %828, %struct.edge_rec** %808, align 4
 	%829 = xor i32 %795, 32		; <i32> [#uses=3]
 	%830 = inttoptr i32 %829 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%831 = getelementptr %struct.edge_rec* %830, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
-	%832 = load %struct.VERTEX** %831, align 4		; <%struct.VERTEX*> [#uses=1]
+	%831 = getelementptr %struct.edge_rec, %struct.edge_rec* %830, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%832 = load %struct.VERTEX*, %struct.VERTEX** %831, align 4		; <%struct.VERTEX*> [#uses=1]
 	%833 = and i32 %798, 63		; <i32> [#uses=1]
 	%834 = and i32 %795, -64		; <i32> [#uses=1]
 	%835 = or i32 %833, %834		; <i32> [#uses=1]
 	%836 = inttoptr i32 %835 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%837 = getelementptr %struct.edge_rec* %836, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%838 = load %struct.edge_rec** %837, align 4		; <%struct.edge_rec*> [#uses=1]
+	%837 = getelementptr %struct.edge_rec, %struct.edge_rec* %836, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%838 = load %struct.edge_rec*, %struct.edge_rec** %837, align 4		; <%struct.edge_rec*> [#uses=1]
 	%839 = ptrtoint %struct.edge_rec* %838 to i32		; <i32> [#uses=2]
 	%840 = add i32 %839, 16		; <i32> [#uses=1]
 	%841 = and i32 %840, 63		; <i32> [#uses=1]
 	%842 = and i32 %839, -64		; <i32> [#uses=1]
 	%843 = or i32 %841, %842		; <i32> [#uses=1]
 	%844 = inttoptr i32 %843 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%845 = load %struct.VERTEX** %767, align 4		; <%struct.VERTEX*> [#uses=1]
+	%845 = load %struct.VERTEX*, %struct.VERTEX** %767, align 4		; <%struct.VERTEX*> [#uses=1]
 	%846 = call  %struct.edge_rec* @alloc_edge() nounwind		; <%struct.edge_rec*> [#uses=4]
-	%847 = getelementptr %struct.edge_rec* %846, i32 0, i32 1		; <%struct.edge_rec**> [#uses=7]
+	%847 = getelementptr %struct.edge_rec, %struct.edge_rec* %846, i32 0, i32 1		; <%struct.edge_rec**> [#uses=7]
 	store %struct.edge_rec* %846, %struct.edge_rec** %847, align 4
-	%848 = getelementptr %struct.edge_rec* %846, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%848 = getelementptr %struct.edge_rec, %struct.edge_rec* %846, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
 	store %struct.VERTEX* %832, %struct.VERTEX** %848, align 4
 	%849 = ptrtoint %struct.edge_rec* %846 to i32		; <i32> [#uses=6]
 	%850 = add i32 %849, 16		; <i32> [#uses=2]
 	%851 = inttoptr i32 %850 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
 	%852 = add i32 %849, 48		; <i32> [#uses=1]
 	%853 = inttoptr i32 %852 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
-	%854 = getelementptr %struct.edge_rec* %851, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%854 = getelementptr %struct.edge_rec, %struct.edge_rec* %851, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %853, %struct.edge_rec** %854, align 4
 	%855 = add i32 %849, 32		; <i32> [#uses=1]
 	%856 = inttoptr i32 %855 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=3]
-	%857 = getelementptr %struct.edge_rec* %856, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%857 = getelementptr %struct.edge_rec, %struct.edge_rec* %856, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %856, %struct.edge_rec** %857, align 4
-	%858 = getelementptr %struct.edge_rec* %856, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
+	%858 = getelementptr %struct.edge_rec, %struct.edge_rec* %856, i32 0, i32 0		; <%struct.VERTEX**> [#uses=1]
 	store %struct.VERTEX* %845, %struct.VERTEX** %858, align 4
-	%859 = getelementptr %struct.edge_rec* %853, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%859 = getelementptr %struct.edge_rec, %struct.edge_rec* %853, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %851, %struct.edge_rec** %859, align 4
-	%860 = load %struct.edge_rec** %847, align 4		; <%struct.edge_rec*> [#uses=1]
+	%860 = load %struct.edge_rec*, %struct.edge_rec** %847, align 4		; <%struct.edge_rec*> [#uses=1]
 	%861 = ptrtoint %struct.edge_rec* %860 to i32		; <i32> [#uses=2]
 	%862 = add i32 %861, 16		; <i32> [#uses=1]
 	%863 = and i32 %862, 63		; <i32> [#uses=1]
 	%864 = and i32 %861, -64		; <i32> [#uses=1]
 	%865 = or i32 %863, %864		; <i32> [#uses=1]
 	%866 = inttoptr i32 %865 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%867 = getelementptr %struct.edge_rec* %844, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%868 = load %struct.edge_rec** %867, align 4		; <%struct.edge_rec*> [#uses=1]
+	%867 = getelementptr %struct.edge_rec, %struct.edge_rec* %844, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%868 = load %struct.edge_rec*, %struct.edge_rec** %867, align 4		; <%struct.edge_rec*> [#uses=1]
 	%869 = ptrtoint %struct.edge_rec* %868 to i32		; <i32> [#uses=2]
 	%870 = add i32 %869, 16		; <i32> [#uses=1]
 	%871 = and i32 %870, 63		; <i32> [#uses=1]
 	%872 = and i32 %869, -64		; <i32> [#uses=1]
 	%873 = or i32 %871, %872		; <i32> [#uses=1]
 	%874 = inttoptr i32 %873 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%875 = getelementptr %struct.edge_rec* %874, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%876 = load %struct.edge_rec** %875, align 4		; <%struct.edge_rec*> [#uses=1]
-	%877 = getelementptr %struct.edge_rec* %866, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%878 = load %struct.edge_rec** %877, align 4		; <%struct.edge_rec*> [#uses=1]
+	%875 = getelementptr %struct.edge_rec, %struct.edge_rec* %874, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%876 = load %struct.edge_rec*, %struct.edge_rec** %875, align 4		; <%struct.edge_rec*> [#uses=1]
+	%877 = getelementptr %struct.edge_rec, %struct.edge_rec* %866, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%878 = load %struct.edge_rec*, %struct.edge_rec** %877, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %876, %struct.edge_rec** %877, align 4
 	store %struct.edge_rec* %878, %struct.edge_rec** %875, align 4
-	%879 = load %struct.edge_rec** %847, align 4		; <%struct.edge_rec*> [#uses=1]
-	%880 = load %struct.edge_rec** %867, align 4		; <%struct.edge_rec*> [#uses=1]
+	%879 = load %struct.edge_rec*, %struct.edge_rec** %847, align 4		; <%struct.edge_rec*> [#uses=1]
+	%880 = load %struct.edge_rec*, %struct.edge_rec** %867, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %879, %struct.edge_rec** %867, align 4
 	store %struct.edge_rec* %880, %struct.edge_rec** %847, align 4
 	%881 = xor i32 %849, 32		; <i32> [#uses=3]
 	%882 = inttoptr i32 %881 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%883 = getelementptr %struct.edge_rec* %882, i32 0, i32 1		; <%struct.edge_rec**> [#uses=6]
-	%884 = load %struct.edge_rec** %883, align 4		; <%struct.edge_rec*> [#uses=1]
+	%883 = getelementptr %struct.edge_rec, %struct.edge_rec* %882, i32 0, i32 1		; <%struct.edge_rec**> [#uses=6]
+	%884 = load %struct.edge_rec*, %struct.edge_rec** %883, align 4		; <%struct.edge_rec*> [#uses=1]
 	%885 = ptrtoint %struct.edge_rec* %884 to i32		; <i32> [#uses=2]
 	%886 = add i32 %885, 16		; <i32> [#uses=1]
 	%887 = and i32 %886, 63		; <i32> [#uses=1]
 	%888 = and i32 %885, -64		; <i32> [#uses=1]
 	%889 = or i32 %887, %888		; <i32> [#uses=1]
 	%890 = inttoptr i32 %889 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%891 = load %struct.edge_rec** %766, align 4		; <%struct.edge_rec*> [#uses=1]
+	%891 = load %struct.edge_rec*, %struct.edge_rec** %766, align 4		; <%struct.edge_rec*> [#uses=1]
 	%892 = ptrtoint %struct.edge_rec* %891 to i32		; <i32> [#uses=2]
 	%893 = add i32 %892, 16		; <i32> [#uses=1]
 	%894 = and i32 %893, 63		; <i32> [#uses=1]
 	%895 = and i32 %892, -64		; <i32> [#uses=1]
 	%896 = or i32 %894, %895		; <i32> [#uses=1]
 	%897 = inttoptr i32 %896 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%898 = getelementptr %struct.edge_rec* %897, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%899 = load %struct.edge_rec** %898, align 4		; <%struct.edge_rec*> [#uses=1]
-	%900 = getelementptr %struct.edge_rec* %890, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%901 = load %struct.edge_rec** %900, align 4		; <%struct.edge_rec*> [#uses=1]
+	%898 = getelementptr %struct.edge_rec, %struct.edge_rec* %897, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%899 = load %struct.edge_rec*, %struct.edge_rec** %898, align 4		; <%struct.edge_rec*> [#uses=1]
+	%900 = getelementptr %struct.edge_rec, %struct.edge_rec* %890, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%901 = load %struct.edge_rec*, %struct.edge_rec** %900, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %899, %struct.edge_rec** %900, align 4
 	store %struct.edge_rec* %901, %struct.edge_rec** %898, align 4
-	%902 = load %struct.edge_rec** %883, align 4		; <%struct.edge_rec*> [#uses=1]
-	%903 = load %struct.edge_rec** %766, align 4		; <%struct.edge_rec*> [#uses=1]
+	%902 = load %struct.edge_rec*, %struct.edge_rec** %883, align 4		; <%struct.edge_rec*> [#uses=1]
+	%903 = load %struct.edge_rec*, %struct.edge_rec** %766, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %902, %struct.edge_rec** %766, align 4
 	store %struct.edge_rec* %903, %struct.edge_rec** %883, align 4
-	%904 = getelementptr %struct.VERTEX* %763, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%905 = load double* %904, align 4		; <double> [#uses=2]
-	%906 = getelementptr %struct.VERTEX* %763, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%907 = load double* %906, align 4		; <double> [#uses=2]
-	%908 = getelementptr %struct.VERTEX* %extra, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%909 = load double* %908, align 4		; <double> [#uses=3]
-	%910 = getelementptr %struct.VERTEX* %extra, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%911 = load double* %910, align 4		; <double> [#uses=3]
-	%912 = getelementptr %struct.VERTEX* %tree, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%913 = load double* %912, align 4		; <double> [#uses=3]
-	%914 = getelementptr %struct.VERTEX* %tree, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%915 = load double* %914, align 4		; <double> [#uses=3]
+	%904 = getelementptr %struct.VERTEX, %struct.VERTEX* %763, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%905 = load double, double* %904, align 4		; <double> [#uses=2]
+	%906 = getelementptr %struct.VERTEX, %struct.VERTEX* %763, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%907 = load double, double* %906, align 4		; <double> [#uses=2]
+	%908 = getelementptr %struct.VERTEX, %struct.VERTEX* %extra, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%909 = load double, double* %908, align 4		; <double> [#uses=3]
+	%910 = getelementptr %struct.VERTEX, %struct.VERTEX* %extra, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%911 = load double, double* %910, align 4		; <double> [#uses=3]
+	%912 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%913 = load double, double* %912, align 4		; <double> [#uses=3]
+	%914 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%915 = load double, double* %914, align 4		; <double> [#uses=3]
 	%916 = fsub double %905, %913		; <double> [#uses=1]
 	%917 = fsub double %911, %915		; <double> [#uses=1]
 	%918 = fmul double %916, %917		; <double> [#uses=1]
@@ -1227,79 +1227,79 @@ bb14:		; preds = %bb13
 	%933 = and i32 %849, -64		; <i32> [#uses=3]
 	%934 = or i32 %932, %933		; <i32> [#uses=1]
 	%935 = inttoptr i32 %934 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%936 = getelementptr %struct.edge_rec* %935, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%937 = load %struct.edge_rec** %936, align 4		; <%struct.edge_rec*> [#uses=1]
+	%936 = getelementptr %struct.edge_rec, %struct.edge_rec* %935, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%937 = load %struct.edge_rec*, %struct.edge_rec** %936, align 4		; <%struct.edge_rec*> [#uses=1]
 	%938 = ptrtoint %struct.edge_rec* %937 to i32		; <i32> [#uses=2]
 	%939 = add i32 %938, 16		; <i32> [#uses=1]
 	%940 = and i32 %939, 63		; <i32> [#uses=1]
 	%941 = and i32 %938, -64		; <i32> [#uses=1]
 	%942 = or i32 %940, %941		; <i32> [#uses=1]
 	%943 = inttoptr i32 %942 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%944 = load %struct.edge_rec** %847, align 4		; <%struct.edge_rec*> [#uses=1]
+	%944 = load %struct.edge_rec*, %struct.edge_rec** %847, align 4		; <%struct.edge_rec*> [#uses=1]
 	%945 = ptrtoint %struct.edge_rec* %944 to i32		; <i32> [#uses=2]
 	%946 = add i32 %945, 16		; <i32> [#uses=1]
 	%947 = and i32 %946, 63		; <i32> [#uses=1]
 	%948 = and i32 %945, -64		; <i32> [#uses=1]
 	%949 = or i32 %947, %948		; <i32> [#uses=1]
 	%950 = inttoptr i32 %949 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%951 = getelementptr %struct.edge_rec* %943, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%952 = load %struct.edge_rec** %951, align 4		; <%struct.edge_rec*> [#uses=1]
+	%951 = getelementptr %struct.edge_rec, %struct.edge_rec* %943, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%952 = load %struct.edge_rec*, %struct.edge_rec** %951, align 4		; <%struct.edge_rec*> [#uses=1]
 	%953 = ptrtoint %struct.edge_rec* %952 to i32		; <i32> [#uses=2]
 	%954 = add i32 %953, 16		; <i32> [#uses=1]
 	%955 = and i32 %954, 63		; <i32> [#uses=1]
 	%956 = and i32 %953, -64		; <i32> [#uses=1]
 	%957 = or i32 %955, %956		; <i32> [#uses=1]
 	%958 = inttoptr i32 %957 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%959 = getelementptr %struct.edge_rec* %958, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%960 = load %struct.edge_rec** %959, align 4		; <%struct.edge_rec*> [#uses=1]
-	%961 = getelementptr %struct.edge_rec* %950, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%962 = load %struct.edge_rec** %961, align 4		; <%struct.edge_rec*> [#uses=1]
+	%959 = getelementptr %struct.edge_rec, %struct.edge_rec* %958, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%960 = load %struct.edge_rec*, %struct.edge_rec** %959, align 4		; <%struct.edge_rec*> [#uses=1]
+	%961 = getelementptr %struct.edge_rec, %struct.edge_rec* %950, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%962 = load %struct.edge_rec*, %struct.edge_rec** %961, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %960, %struct.edge_rec** %961, align 4
 	store %struct.edge_rec* %962, %struct.edge_rec** %959, align 4
-	%963 = load %struct.edge_rec** %847, align 4		; <%struct.edge_rec*> [#uses=1]
-	%964 = load %struct.edge_rec** %951, align 4		; <%struct.edge_rec*> [#uses=1]
+	%963 = load %struct.edge_rec*, %struct.edge_rec** %847, align 4		; <%struct.edge_rec*> [#uses=1]
+	%964 = load %struct.edge_rec*, %struct.edge_rec** %951, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %963, %struct.edge_rec** %951, align 4
 	store %struct.edge_rec* %964, %struct.edge_rec** %847, align 4
 	%965 = add i32 %881, 16		; <i32> [#uses=1]
 	%966 = and i32 %965, 63		; <i32> [#uses=1]
 	%967 = or i32 %966, %933		; <i32> [#uses=1]
 	%968 = inttoptr i32 %967 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%969 = getelementptr %struct.edge_rec* %968, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
-	%970 = load %struct.edge_rec** %969, align 4		; <%struct.edge_rec*> [#uses=1]
+	%969 = getelementptr %struct.edge_rec, %struct.edge_rec* %968, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%970 = load %struct.edge_rec*, %struct.edge_rec** %969, align 4		; <%struct.edge_rec*> [#uses=1]
 	%971 = ptrtoint %struct.edge_rec* %970 to i32		; <i32> [#uses=2]
 	%972 = add i32 %971, 16		; <i32> [#uses=1]
 	%973 = and i32 %972, 63		; <i32> [#uses=1]
 	%974 = and i32 %971, -64		; <i32> [#uses=1]
 	%975 = or i32 %973, %974		; <i32> [#uses=1]
 	%976 = inttoptr i32 %975 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%977 = load %struct.edge_rec** %883, align 4		; <%struct.edge_rec*> [#uses=1]
+	%977 = load %struct.edge_rec*, %struct.edge_rec** %883, align 4		; <%struct.edge_rec*> [#uses=1]
 	%978 = ptrtoint %struct.edge_rec* %977 to i32		; <i32> [#uses=2]
 	%979 = add i32 %978, 16		; <i32> [#uses=1]
 	%980 = and i32 %979, 63		; <i32> [#uses=1]
 	%981 = and i32 %978, -64		; <i32> [#uses=1]
 	%982 = or i32 %980, %981		; <i32> [#uses=1]
 	%983 = inttoptr i32 %982 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%984 = getelementptr %struct.edge_rec* %976, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
-	%985 = load %struct.edge_rec** %984, align 4		; <%struct.edge_rec*> [#uses=1]
+	%984 = getelementptr %struct.edge_rec, %struct.edge_rec* %976, i32 0, i32 1		; <%struct.edge_rec**> [#uses=3]
+	%985 = load %struct.edge_rec*, %struct.edge_rec** %984, align 4		; <%struct.edge_rec*> [#uses=1]
 	%986 = ptrtoint %struct.edge_rec* %985 to i32		; <i32> [#uses=2]
 	%987 = add i32 %986, 16		; <i32> [#uses=1]
 	%988 = and i32 %987, 63		; <i32> [#uses=1]
 	%989 = and i32 %986, -64		; <i32> [#uses=1]
 	%990 = or i32 %988, %989		; <i32> [#uses=1]
 	%991 = inttoptr i32 %990 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=1]
-	%992 = getelementptr %struct.edge_rec* %991, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%993 = load %struct.edge_rec** %992, align 4		; <%struct.edge_rec*> [#uses=1]
-	%994 = getelementptr %struct.edge_rec* %983, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
-	%995 = load %struct.edge_rec** %994, align 4		; <%struct.edge_rec*> [#uses=1]
+	%992 = getelementptr %struct.edge_rec, %struct.edge_rec* %991, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%993 = load %struct.edge_rec*, %struct.edge_rec** %992, align 4		; <%struct.edge_rec*> [#uses=1]
+	%994 = getelementptr %struct.edge_rec, %struct.edge_rec* %983, i32 0, i32 1		; <%struct.edge_rec**> [#uses=2]
+	%995 = load %struct.edge_rec*, %struct.edge_rec** %994, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %993, %struct.edge_rec** %994, align 4
 	store %struct.edge_rec* %995, %struct.edge_rec** %992, align 4
-	%996 = load %struct.edge_rec** %883, align 4		; <%struct.edge_rec*> [#uses=1]
-	%997 = load %struct.edge_rec** %984, align 4		; <%struct.edge_rec*> [#uses=1]
+	%996 = load %struct.edge_rec*, %struct.edge_rec** %883, align 4		; <%struct.edge_rec*> [#uses=1]
+	%997 = load %struct.edge_rec*, %struct.edge_rec** %984, align 4		; <%struct.edge_rec*> [#uses=1]
 	store %struct.edge_rec* %996, %struct.edge_rec** %984, align 4
 	store %struct.edge_rec* %997, %struct.edge_rec** %883, align 4
 	%998 = inttoptr i32 %933 to %struct.edge_rec*		; <%struct.edge_rec*> [#uses=2]
-	%999 = load %struct.edge_rec** @avail_edge, align 4		; <%struct.edge_rec*> [#uses=1]
-	%1000 = getelementptr %struct.edge_rec* %998, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
+	%999 = load %struct.edge_rec*, %struct.edge_rec** @avail_edge, align 4		; <%struct.edge_rec*> [#uses=1]
+	%1000 = getelementptr %struct.edge_rec, %struct.edge_rec* %998, i32 0, i32 1		; <%struct.edge_rec**> [#uses=1]
 	store %struct.edge_rec* %999, %struct.edge_rec** %1000, align 4
 	store %struct.edge_rec* %998, %struct.edge_rec** @avail_edge, align 4
 	br label %bb15
diff --git a/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll b/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll
index d477ba9835be..d746b104baf8 100644
--- a/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll
+++ b/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll
@@ -83,7 +83,7 @@ bb45:		; preds = %bb43.preheader, %cli_calloc.exit54
 	br i1 undef, label %cli_calloc.exit70.thread, label %cli_calloc.exit70
 
 bb52:		; preds = %cli_calloc.exit
-	%0 = load i16* undef, align 4		; <i16> [#uses=1]
+	%0 = load i16, i16* undef, align 4		; <i16> [#uses=1]
 	%1 = icmp eq i16 %0, 0		; <i1> [#uses=1]
 	%iftmp.20.0 = select i1 %1, i8* %hexsig, i8* null		; <i8*> [#uses=1]
 	%2 = tail call  i32 @strlen(i8* %iftmp.20.0) nounwind readonly		; <i32> [#uses=0]
diff --git a/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll b/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
index bc4a95c3e00b..156fd8843bcf 100644
--- a/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
+++ b/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
@@ -65,9 +65,9 @@ bb18:		; preds = %bb18, %bb.nph
 	br i1 undef, label %bb18, label %bb22
 
 bb22:		; preds = %bb18, %bb17
-	%0 = getelementptr i8* null, i32 10		; <i8*> [#uses=1]
+	%0 = getelementptr i8, i8* null, i32 10		; <i8*> [#uses=1]
 	%1 = bitcast i8* %0 to i16*		; <i16*> [#uses=1]
-	%2 = load i16* %1, align 2		; <i16> [#uses=1]
+	%2 = load i16, i16* %1, align 2		; <i16> [#uses=1]
 	%3 = add i16 %2, 1		; <i16> [#uses=1]
 	%4 = zext i16 %3 to i32		; <i32> [#uses=1]
 	%5 = mul i32 %4, 3		; <i32> [#uses=1]
diff --git a/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll b/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll
index 5003fbdedb27..01591c80362d 100644
--- a/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll
+++ b/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll
@@ -12,7 +12,7 @@ bb:		; preds = %bb, %entry
 	br i1 undef, label %bb28, label %bb
 
 bb28:		; preds = %bb
-	%0 = load double* @a, align 4		; <double> [#uses=2]
+	%0 = load double, double* @a, align 4		; <double> [#uses=2]
 	%1 = fadd double %0, undef		; <double> [#uses=2]
 	br i1 undef, label %bb59, label %bb60
 
diff --git a/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll b/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
index a656c495f796..e277b4cf91a6 100644
--- a/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
+++ b/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
@@ -13,17 +13,17 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store <4 x i32> %v, <4 x i32>* %v_addr
 	store i32 %f, i32* %f_addr
-	%1 = load <4 x i32>* %v_addr, align 16		; <<4 x i32>> [#uses=1]
-	%2 = load i32* %f_addr, align 4		; <i32> [#uses=1]
+	%1 = load <4 x i32>, <4 x i32>* %v_addr, align 16		; <<4 x i32>> [#uses=1]
+	%2 = load i32, i32* %f_addr, align 4		; <i32> [#uses=1]
 	%3 = insertelement <4 x i32> undef, i32 %2, i32 0		; <<4 x i32>> [#uses=1]
 	%4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> zeroinitializer		; <<4 x i32>> [#uses=1]
 	%5 = mul <4 x i32> %1, %4		; <<4 x i32>> [#uses=1]
 	store <4 x i32> %5, <4 x i32>* %0, align 16
-	%6 = load <4 x i32>* %0, align 16		; <<4 x i32>> [#uses=1]
+	%6 = load <4 x i32>, <4 x i32>* %0, align 16		; <<4 x i32>> [#uses=1]
 	store <4 x i32> %6, <4 x i32>* %retval, align 16
 	br label %return
 
 return:		; preds = %entry
-	%retval1 = load <4 x i32>* %retval		; <<4 x i32>> [#uses=1]
+	%retval1 = load <4 x i32>, <4 x i32>* %retval		; <<4 x i32>> [#uses=1]
 	ret <4 x i32> %retval1
 }
diff --git a/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll b/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
index 4b4101556f18..a5e9692a0082 100644
--- a/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
+++ b/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
@@ -28,8 +28,8 @@ bb7:                                              ; preds = %bb2
 
 bb8:                                              ; preds = %bb7, %entry
   %2 = phi i32 [ 0, %entry ], [ %1, %bb7 ]        ; <i32> [#uses=3]
-  %scevgep22 = getelementptr %struct.iovec* %iov, i32 %2, i32 0; <i8**> [#uses=0]
-  %3 = load i32* %nr_segs, align 4                ; <i32> [#uses=1]
+  %scevgep22 = getelementptr %struct.iovec, %struct.iovec* %iov, i32 %2, i32 0; <i8**> [#uses=0]
+  %3 = load i32, i32* %nr_segs, align 4                ; <i32> [#uses=1]
   %4 = icmp ult i32 %2, %3                        ; <i1> [#uses=1]
   br i1 %4, label %bb, label %bb9
 
diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
index c598fe6e2e1a..0d258e66b7e0 100644
--- a/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
+++ b/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
@@ -9,18 +9,18 @@ target triple = "armv7-apple-darwin9"
 
 define %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind {
 entry:
-  %t.idx51.val.i = load double* null              ; <double> [#uses=1]
+  %t.idx51.val.i = load double, double* null              ; <double> [#uses=1]
   br i1 undef, label %bb4.i, label %bb.i
 
 bb.i:                                             ; preds = %entry
   unreachable
 
 bb4.i:                                            ; preds = %entry
-  %0 = load %struct.tree** @g, align 4         ; <%struct.tree*> [#uses=2]
-  %.idx45.i = getelementptr %struct.tree* %0, i32 0, i32 1 ; <double*> [#uses=1]
-  %.idx45.val.i = load double* %.idx45.i          ; <double> [#uses=1]
-  %.idx46.i = getelementptr %struct.tree* %0, i32 0, i32 2 ; <double*> [#uses=1]
-  %.idx46.val.i = load double* %.idx46.i          ; <double> [#uses=1]
+  %0 = load %struct.tree*, %struct.tree** @g, align 4         ; <%struct.tree*> [#uses=2]
+  %.idx45.i = getelementptr %struct.tree, %struct.tree* %0, i32 0, i32 1 ; <double*> [#uses=1]
+  %.idx45.val.i = load double, double* %.idx45.i          ; <double> [#uses=1]
+  %.idx46.i = getelementptr %struct.tree, %struct.tree* %0, i32 0, i32 2 ; <double*> [#uses=1]
+  %.idx46.val.i = load double, double* %.idx46.i          ; <double> [#uses=1]
   %1 = fsub double 0.000000e+00, %.idx45.val.i    ; <double> [#uses=2]
   %2 = fmul double %1, %1                         ; <double> [#uses=1]
   %3 = fsub double %t.idx51.val.i, %.idx46.val.i  ; <double> [#uses=2]
diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
index cc92c26aeece..489d4e45236c 100644
--- a/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
+++ b/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
@@ -32,7 +32,7 @@ bb9:                                              ; preds = %bb7
   br label %bb11
 
 bb11:                                             ; preds = %bb9, %bb7
-  %1 = getelementptr %struct.icstruct* %agg.result, i32 0, i32 0, i32 0 ; <i32*> [#uses=1]
+  %1 = getelementptr %struct.icstruct, %struct.icstruct* %agg.result, i32 0, i32 0, i32 0 ; <i32*> [#uses=1]
   store i32 0, i32* %1
   ret void
 }
diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
index 382038eb13ef..133fc0588a91 100644
--- a/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
+++ b/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
@@ -14,14 +14,14 @@ entry:
   br i1 %p, label %bb8, label %bb1
 
 bb1:                                              ; preds = %entry
-  %malloccall = tail call i8* @malloc(i32 ptrtoint (%struct.Village* getelementptr (%struct.Village* null, i32 1) to i32))
+  %malloccall = tail call i8* @malloc(i32 ptrtoint (%struct.Village* getelementptr (%struct.Village, %struct.Village* null, i32 1) to i32))
   %0 = bitcast i8* %malloccall to %struct.Village*
   %exp2 = call double @ldexp(double 1.000000e+00, i32 %level) nounwind ; <double> [#uses=1]
   %.c = fptosi double %exp2 to i32                ; <i32> [#uses=1]
   store i32 %.c, i32* null
-  %1 = getelementptr %struct.Village* %0, i32 0, i32 3, i32 6, i32 0 ; <%struct.List**> [#uses=1]
+  %1 = getelementptr %struct.Village, %struct.Village* %0, i32 0, i32 3, i32 6, i32 0 ; <%struct.List**> [#uses=1]
   store %struct.List* null, %struct.List** %1
-  %2 = getelementptr %struct.Village* %0, i32 0, i32 3, i32 6, i32 2 ; <%struct.List**> [#uses=1]
+  %2 = getelementptr %struct.Village, %struct.Village* %0, i32 0, i32 3, i32 6, i32 2 ; <%struct.List**> [#uses=1]
   store %struct.List* null, %struct.List** %2
   ret %struct.Village* %0
 
diff --git a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll
index a016809857e7..2f6e428351d7 100644
--- a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll
+++ b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll
@@ -1,7 +1,9 @@
 ; RUN: llc < %s -mtriple=arm-apple-darwin9 -march=arm | FileCheck %s
 
-; CHECK: L_LSDA_0:
-
+; CHECK: .cfi_lsda 16, [[LABEL:.*]]
+; CHECK: .long  [[LABEL]]-
+; CHECK: [[LABEL]]:
+; CHECK: .byte   255                     @ @LPStart Encoding = omit
 
 %struct.A = type { i32* }
 
@@ -22,14 +24,14 @@ invcont:                                          ; preds = %entry
   br label %return
 
 bb:                                               ; preds = %ppad
-  %eh_select = load i32* %eh_selector
+  %eh_select = load i32, i32* %eh_selector
   store i32 %eh_select, i32* %save_filt.1, align 4
-  %eh_value = load i8** %eh_exception
+  %eh_value = load i8*, i8** %eh_exception
   store i8* %eh_value, i8** %save_eptr.0, align 4
   call void @_ZN1AD1Ev(%struct.A* %a) nounwind
-  %0 = load i8** %save_eptr.0, align 4
+  %0 = load i8*, i8** %save_eptr.0, align 4
   store i8* %0, i8** %eh_exception, align 4
-  %1 = load i32* %save_filt.1, align 4
+  %1 = load i32, i32* %save_filt.1, align 4
   store i32 %1, i32* %eh_selector, align 4
   br label %Unwind
 
@@ -49,7 +51,7 @@ ppad:                                             ; preds = %lpad
   br label %bb
 
 Unwind:                                           ; preds = %bb
-  %eh_ptr3 = load i8** %eh_exception
+  %eh_ptr3 = load i8*, i8** %eh_exception
   call void @_Unwind_SjLj_Resume(i8* %eh_ptr3)
   unreachable
 }
@@ -61,8 +63,8 @@ entry:
   store %struct.A* %this, %struct.A** %this_addr
   %0 = call i8* @_Znwm(i32 4)
   %1 = bitcast i8* %0 to i32*
-  %2 = load %struct.A** %this_addr, align 4
-  %3 = getelementptr inbounds %struct.A* %2, i32 0, i32 0
+  %2 = load %struct.A*, %struct.A** %this_addr, align 4
+  %3 = getelementptr inbounds %struct.A, %struct.A* %2, i32 0, i32 0
   store i32* %1, i32** %3, align 4
   br label %return
 
@@ -77,9 +79,9 @@ entry:
   %this_addr = alloca %struct.A*
   %"alloca point" = bitcast i32 0 to i32
   store %struct.A* %this, %struct.A** %this_addr
-  %0 = load %struct.A** %this_addr, align 4
-  %1 = getelementptr inbounds %struct.A* %0, i32 0, i32 0
-  %2 = load i32** %1, align 4
+  %0 = load %struct.A*, %struct.A** %this_addr, align 4
+  %1 = getelementptr inbounds %struct.A, %struct.A* %0, i32 0, i32 0
+  %2 = load i32*, i32** %1, align 4
   %3 = bitcast i32* %2 to i8*
   call void @_ZdlPv(i8* %3) nounwind
   br label %bb
diff --git a/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll b/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
index b078ec06dbb8..a6d128d9e0ce 100644
--- a/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
+++ b/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
@@ -4,7 +4,7 @@
 define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind {
 ;CHECK-LABEL: v2regbug:
 ;CHECK: vzip.16
-	%tmp1 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %B
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32><i32 0, i32 0, i32 1, i32 1>
 	ret <4 x i16> %tmp2
 }
diff --git a/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll b/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
index 426bd17590b7..4437d37e9f4a 100644
--- a/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
+++ b/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
@@ -2,8 +2,8 @@
 ; pr4939
 
 define void @test(double* %x, double* %y) nounwind {
-  %1 = load double* %x
-  %2 = load double* %y
+  %1 = load double, double* %x
+  %2 = load double, double* %y
   %3 = fsub double -0.000000e+00, %1
   %4 = fcmp ugt double %2, %3
   br i1 %4, label %bb1, label %bb2
diff --git a/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll b/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll
index 13adb24e2f6f..de927a8f8b66 100644
--- a/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll
+++ b/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll
@@ -13,10 +13,10 @@ declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwin
 
 define arm_aapcs_vfpcc i8 @foo(%struct.fr* nocapture %this, %struct.obb* %box) nounwind {
 entry:
-  %val.i.i = load <4 x float>* undef              ; <<4 x float>> [#uses=1]
-  %val2.i.i = load <4 x float>* null              ; <<4 x float>> [#uses=1]
-  %elt3.i.i = getelementptr inbounds %struct.obb* %box, i32 0, i32 0, i32 2, i32 0 ; <<4 x float>*> [#uses=1]
-  %val4.i.i = load <4 x float>* %elt3.i.i         ; <<4 x float>> [#uses=1]
+  %val.i.i = load <4 x float>, <4 x float>* undef              ; <<4 x float>> [#uses=1]
+  %val2.i.i = load <4 x float>, <4 x float>* null              ; <<4 x float>> [#uses=1]
+  %elt3.i.i = getelementptr inbounds %struct.obb, %struct.obb* %box, i32 0, i32 0, i32 2, i32 0 ; <<4 x float>*> [#uses=1]
+  %val4.i.i = load <4 x float>, <4 x float>* %elt3.i.i         ; <<4 x float>> [#uses=1]
   %0 = shufflevector <2 x float> undef, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
   %1 = fadd <4 x float> undef, zeroinitializer    ; <<4 x float>> [#uses=1]
   br label %bb33
diff --git a/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll b/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll
index dd9a6fd12d7e..b8a1479fd34c 100644
--- a/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll
+++ b/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll
@@ -16,13 +16,13 @@ define arm_aapcs_vfpcc <4 x float> @foo(i8* nocapture %pBuffer, i32 %numItems) n
   %tmp3738 = inttoptr i32 %tmp37 to float*
   %tmp39 = add i32 %1, 24
   %tmp3940 = inttoptr i32 %tmp39 to float*
-  %2 = load float* %lsr.iv2641, align 4
-  %3 = load float* %tmp2930, align 4
-  %4 = load float* %tmp3132, align 4
-  %5 = load float* %tmp3334, align 4
-  %6 = load float* %tmp3536, align 4
-  %7 = load float* %tmp3738, align 4
-  %8 = load float* %tmp3940, align 4
+  %2 = load float, float* %lsr.iv2641, align 4
+  %3 = load float, float* %tmp2930, align 4
+  %4 = load float, float* %tmp3132, align 4
+  %5 = load float, float* %tmp3334, align 4
+  %6 = load float, float* %tmp3536, align 4
+  %7 = load float, float* %tmp3738, align 4
+  %8 = load float, float* %tmp3940, align 4
   %9 = insertelement <4 x float> undef, float %6, i32 0
   %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> zeroinitializer
   %11 = insertelement <4 x float> %10, float %7, i32 1
diff --git a/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll b/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll
index 2ff479b21781..4bbd04705643 100644
--- a/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll
+++ b/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll
@@ -9,7 +9,7 @@ define arm_aapcs_vfpcc %struct.1* @hhh3(%struct.1* %this, <4 x float> %lenation.
 entry:
   %0 = call arm_aapcs_vfpcc  %struct.4* @sss1(%struct.4* undef, float 0.000000e+00) nounwind ; <%struct.4*> [#uses=0]
   %1 = call arm_aapcs_vfpcc  %struct.4* @qqq1(%struct.4* null, float 5.000000e-01) nounwind ; <%struct.4*> [#uses=0]
-  %val92 = load <4 x float>* null                 ; <<4 x float>> [#uses=1]
+  %val92 = load <4 x float>, <4 x float>* null                 ; <<4 x float>> [#uses=1]
   %2 = call arm_aapcs_vfpcc  %struct.4* @zzz2(%struct.4* undef, <4 x float> %val92) nounwind ; <%struct.4*> [#uses=0]
   ret %struct.1* %this
 }
diff --git a/test/CodeGen/ARM/2009-09-24-spill-align.ll b/test/CodeGen/ARM/2009-09-24-spill-align.ll
index 224bd019481d..4502542809f7 100644
--- a/test/CodeGen/ARM/2009-09-24-spill-align.ll
+++ b/test/CodeGen/ARM/2009-09-24-spill-align.ll
@@ -7,7 +7,7 @@ entry:
   %out_poly16_t = alloca i16                      ; <i16*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
 ; CHECK: vldr
-  %0 = load <4 x i16>* %arg0_poly16x4_t, align 8  ; <<4 x i16>> [#uses=1]
+  %0 = load <4 x i16>, <4 x i16>* %arg0_poly16x4_t, align 8  ; <<4 x i16>> [#uses=1]
   %1 = extractelement <4 x i16> %0, i32 1         ; <i16> [#uses=1]
   store i16 %1, i16* %out_poly16_t, align 2
   br label %return
diff --git a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
index e2ff164502ce..287384fbc214 100644
--- a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
+++ b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
@@ -11,9 +11,9 @@ define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.
   %x76 = fmul double %y.0, 0.000000e+00           ; <double> [#uses=1]
   %x77 = fadd double %y.0, 0.000000e+00           ; <double> [#uses=1]
   %tmpr = fadd double %x.0, %x76                  ; <double> [#uses=1]
-  %agg.result.0 = getelementptr %0* %agg.result, i32 0, i32 0 ; <double*> [#uses=1]
+  %agg.result.0 = getelementptr %0, %0* %agg.result, i32 0, i32 0 ; <double*> [#uses=1]
   store double %tmpr, double* %agg.result.0, align 8
-  %agg.result.1 = getelementptr %0* %agg.result, i32 0, i32 1 ; <double*> [#uses=1]
+  %agg.result.1 = getelementptr %0, %0* %agg.result, i32 0, i32 1 ; <double*> [#uses=1]
   store double %x77, double* %agg.result.1, align 8
   ret void
 }
diff --git a/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll b/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll
index 465368b0ba8d..641036f684b9 100644
--- a/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll
+++ b/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll
@@ -6,8 +6,8 @@ entry:
   br i1 undef, label %return, label %bb
 
 bb:                                               ; preds = %bb, %entry
-  %0 = load float* undef, align 4                 ; <float> [#uses=1]
-  %1 = load float* null, align 4                  ; <float> [#uses=1]
+  %0 = load float, float* undef, align 4                 ; <float> [#uses=1]
+  %1 = load float, float* null, align 4                  ; <float> [#uses=1]
   %2 = insertelement <4 x float> undef, float undef, i32 1 ; <<4 x float>> [#uses=1]
   %3 = insertelement <4 x float> %2, float %1, i32 2 ; <<4 x float>> [#uses=2]
   %4 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1]
diff --git a/test/CodeGen/ARM/2009-10-16-Scope.ll b/test/CodeGen/ARM/2009-10-16-Scope.ll
index de05644fc901..3f47488372b8 100644
--- a/test/CodeGen/ARM/2009-10-16-Scope.ll
+++ b/test/CodeGen/ARM/2009-10-16-Scope.ll
@@ -9,7 +9,7 @@ entry:
   br label %do.body, !dbg !0
 
 do.body:                                          ; preds = %entry
-  call void @llvm.dbg.declare(metadata i32* %count_, metadata !4, metadata !{!"0x102"})
+  call void @llvm.dbg.declare(metadata i32* %count_, metadata !4, metadata !DIExpression()), !dbg !DILocation(scope: !5)
   %conv = ptrtoint i32* %count_ to i32, !dbg !0   ; <i32> [#uses=1]
   %call = call i32 @foo(i32 %conv) ssp, !dbg !0   ; <i32> [#uses=0]
   br label %do.end, !dbg !0
@@ -22,13 +22,13 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 
 declare i32 @foo(i32) ssp
 
-!0 = !MDLocation(line: 5, column: 2, scope: !1)
-!1 = !{!"0xb\001\001\000", null, !2}; [DW_TAG_lexical_block ]
-!2 = !{!"0x2e\00bar\00bar\00bar\004\000\001\000\006\000\000\000", i32 0, !3, null, null, null, null, null, null}; [DW_TAG_subprogram ]
-!3 = !{!"0x11\0012\00clang 1.1\001\00\000\00\000", !8, null, !9, null, null, null}; [DW_TAG_compile_unit ]
-!4 = !{!"0x100\00count_\005\000", !5, !3, !6}; [ DW_TAG_auto_variable ]
-!5 = !{!"0xb\001\001\000", null, !1}; [DW_TAG_lexical_block ]
-!6 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !3}; [DW_TAG_base_type ]
-!7 = !MDLocation(line: 6, column: 1, scope: !2)
-!8 = !{!"genmodes.i", !"/Users/yash/Downloads"}
+!0 = !DILocation(line: 5, column: 2, scope: !1)
+!1 = distinct !DILexicalBlock(line: 1, column: 1, file: null, scope: !2)
+!2 = !DISubprogram(name: "bar", linkageName: "bar", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !3)
+!3 = !DICompileUnit(language: DW_LANG_C99, producer: "clang 1.1", isOptimized: true, emissionKind: 0, file: !8, retainedTypes: !9)
+!4 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "count_", line: 5, scope: !5, file: !3, type: !6)
+!5 = distinct !DILexicalBlock(line: 1, column: 1, file: null, scope: !1)
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!7 = !DILocation(line: 6, column: 1, scope: !2)
+!8 = !DIFile(filename: "genmodes.i", directory: "/Users/yash/Downloads")
 !9 = !{i32 0}
diff --git a/test/CodeGen/ARM/2009-10-27-double-align.ll b/test/CodeGen/ARM/2009-10-27-double-align.ll
index b37de9dbbdfd..39f3292e260b 100644
--- a/test/CodeGen/ARM/2009-10-27-double-align.ll
+++ b/test/CodeGen/ARM/2009-10-27-double-align.ll
@@ -8,7 +8,7 @@ entry:
 ;CHECK: [sp, #8]
 ;CHECK: [sp, #12]
 ;CHECK: [sp]
-        tail call  void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00)
+        tail call  void (i8*, ...) @f(i8* getelementptr ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00)
         ret void
 }
 
diff --git a/test/CodeGen/ARM/2009-11-01-NeonMoves.ll b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll
index a18a8308044c..1fc10564a460 100644
--- a/test/CodeGen/ARM/2009-11-01-NeonMoves.ll
+++ b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll
@@ -8,7 +8,7 @@ target triple = "armv7-eabi"
 define arm_aapcs_vfpcc void @bar(%foo* noalias sret %agg.result, <4 x float> %quat.0) nounwind {
 entry:
   %quat_addr = alloca %foo, align 16              ; <%foo*> [#uses=2]
-  %0 = getelementptr inbounds %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1]
+  %0 = getelementptr inbounds %foo, %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1]
   store <4 x float> %quat.0, <4 x float>* %0
   %1 = call arm_aapcs_vfpcc  <4 x float> @quux(%foo* %quat_addr) nounwind ; <<4 x float>> [#uses=3]
   %2 = fmul <4 x float> %1, %1                    ; <<4 x float>> [#uses=2]
diff --git a/test/CodeGen/ARM/2009-11-02-NegativeLane.ll b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll
index 2597b413ec7c..154cd65e4ec1 100644
--- a/test/CodeGen/ARM/2009-11-02-NegativeLane.ll
+++ b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll
@@ -8,7 +8,7 @@ entry:
 
 bb:                                               ; preds = %bb, %entry
 ; CHECK: vld1.16 {d16[], d17[]}
-  %0 = load i16* undef, align 2
+  %0 = load i16, i16* undef, align 2
   %1 = insertelement <8 x i16> undef, i16 %0, i32 2
   %2 = insertelement <8 x i16> %1, i16 undef, i32 3
   %3 = mul <8 x i16> %2, %2
diff --git a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
index 38eb0ea2c891..9632c7730105 100644
--- a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
+++ b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
@@ -6,7 +6,7 @@ target triple = "armv7-eabi"
 
 define arm_aapcs_vfpcc void @foo() {
 entry:
-  %0 = load float* null, align 4                  ; <float> [#uses=2]
+  %0 = load float, float* null, align 4                  ; <float> [#uses=2]
   %1 = fmul float %0, undef                       ; <float> [#uses=2]
   %2 = fmul float 0.000000e+00, %1                ; <float> [#uses=2]
   %3 = fmul float %0, %1                          ; <float> [#uses=1]
@@ -18,7 +18,7 @@ entry:
   %7 = fsub float %2, undef                       ; <float> [#uses=1]
   %8 = fsub float 0.000000e+00, undef             ; <float> [#uses=3]
   %9 = fadd float %2, undef                       ; <float> [#uses=3]
-  %10 = load float* undef, align 8                ; <float> [#uses=3]
+  %10 = load float, float* undef, align 8                ; <float> [#uses=3]
   %11 = fmul float %8, %10                        ; <float> [#uses=1]
   %12 = fadd float undef, %11                     ; <float> [#uses=2]
   %13 = fmul float undef, undef                   ; <float> [#uses=1]
@@ -30,10 +30,10 @@ entry:
   %19 = fadd float %18, 0.000000e+00              ; <float> [#uses=1]
   %20 = fmul float undef, %10                     ; <float> [#uses=1]
   %21 = fadd float %19, %20                       ; <float> [#uses=1]
-  %22 = load float* undef, align 8                ; <float> [#uses=1]
+  %22 = load float, float* undef, align 8                ; <float> [#uses=1]
   %23 = fmul float %5, %22                        ; <float> [#uses=1]
   %24 = fadd float %23, undef                     ; <float> [#uses=1]
-  %25 = load float* undef, align 8                ; <float> [#uses=2]
+  %25 = load float, float* undef, align 8                ; <float> [#uses=2]
   %26 = fmul float %8, %25                        ; <float> [#uses=1]
   %27 = fadd float %24, %26                       ; <float> [#uses=1]
   %28 = fmul float %9, %25                        ; <float> [#uses=1]
diff --git a/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll b/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll
index 6cce02dd48cf..07e910b3e07b 100644
--- a/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll
+++ b/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll
@@ -13,11 +13,11 @@ entry:
   br i1 undef, label %bb85, label %bb
 
 bb:                                               ; preds = %entry
-  %0 = getelementptr inbounds %bar* null, i32 0, i32 0, i32 0, i32 2 ; <float*> [#uses=2]
-  %1 = load float* undef, align 4                 ; <float> [#uses=1]
+  %0 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 2 ; <float*> [#uses=2]
+  %1 = load float, float* undef, align 4                 ; <float> [#uses=1]
   %2 = fsub float 0.000000e+00, undef             ; <float> [#uses=2]
   %3 = fmul float 0.000000e+00, undef             ; <float> [#uses=1]
-  %4 = load float* %0, align 4                    ; <float> [#uses=3]
+  %4 = load float, float* %0, align 4                    ; <float> [#uses=3]
   %5 = fmul float %4, %2                          ; <float> [#uses=1]
   %6 = fsub float %3, %5                          ; <float> [#uses=1]
   %7 = fmul float %4, undef                       ; <float> [#uses=1]
diff --git a/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll b/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll
index 3ff663124819..9eddcf71cb3b 100644
--- a/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll
+++ b/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll
@@ -19,22 +19,22 @@ bb2.i:                                            ; preds = %bb
   br label %bb3.i
 
 bb3.i:                                            ; preds = %bb2.i, %bb
-  %0 = getelementptr inbounds %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=0]
+  %0 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=0]
   %1 = fsub float 0.000000e+00, undef             ; <float> [#uses=1]
-  %2 = getelementptr inbounds %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=2]
-  %3 = load float* %2, align 4                    ; <float> [#uses=1]
-  %4 = getelementptr inbounds %quuz* %a, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
+  %2 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=2]
+  %3 = load float, float* %2, align 4                    ; <float> [#uses=1]
+  %4 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
   %5 = fsub float %3, undef                       ; <float> [#uses=2]
-  %6 = getelementptr inbounds %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=2]
-  %7 = load float* %6, align 4                    ; <float> [#uses=1]
+  %6 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=2]
+  %7 = load float, float* %6, align 4                    ; <float> [#uses=1]
   %8 = fsub float %7, undef                       ; <float> [#uses=1]
-  %9 = getelementptr inbounds %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=2]
-  %10 = load float* %9, align 4                   ; <float> [#uses=1]
+  %9 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=2]
+  %10 = load float, float* %9, align 4                   ; <float> [#uses=1]
   %11 = fsub float %10, undef                     ; <float> [#uses=2]
-  %12 = getelementptr inbounds %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=2]
-  %13 = load float* %12, align 4                  ; <float> [#uses=1]
+  %12 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=2]
+  %13 = load float, float* %12, align 4                  ; <float> [#uses=1]
   %14 = fsub float %13, undef                     ; <float> [#uses=1]
-  %15 = load float* undef, align 4                ; <float> [#uses=1]
+  %15 = load float, float* undef, align 4                ; <float> [#uses=1]
   %16 = fsub float %15, undef                     ; <float> [#uses=1]
   %17 = fmul float %5, %16                        ; <float> [#uses=1]
   %18 = fsub float %17, 0.000000e+00              ; <float> [#uses=5]
@@ -44,19 +44,19 @@ bb3.i:                                            ; preds = %bb2.i, %bb
   %22 = fmul float %5, %11                        ; <float> [#uses=1]
   %23 = fsub float %21, %22                       ; <float> [#uses=2]
   store float %18, float* undef
-  %24 = getelementptr inbounds %bar* null, i32 0, i32 0, i32 0, i32 1 ; <float*> [#uses=2]
+  %24 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 1 ; <float*> [#uses=2]
   store float %20, float* %24
   store float %23, float* undef
-  %25 = getelementptr inbounds %bar* null, i32 0, i32 0, i32 0, i32 3 ; <float*> [#uses=0]
+  %25 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 3 ; <float*> [#uses=0]
   %26 = fmul float %18, %18                       ; <float> [#uses=1]
   %27 = fadd float %26, undef                     ; <float> [#uses=1]
   %28 = fadd float %27, undef                     ; <float> [#uses=1]
   %29 = call arm_aapcs_vfpcc  float @sqrtf(float %28) readnone ; <float> [#uses=1]
-  %30 = load float* null, align 4                 ; <float> [#uses=2]
-  %31 = load float* %4, align 4                   ; <float> [#uses=2]
-  %32 = load float* %2, align 4                   ; <float> [#uses=2]
-  %33 = load float* null, align 4                 ; <float> [#uses=3]
-  %34 = load float* %6, align 4                   ; <float> [#uses=2]
+  %30 = load float, float* null, align 4                 ; <float> [#uses=2]
+  %31 = load float, float* %4, align 4                   ; <float> [#uses=2]
+  %32 = load float, float* %2, align 4                   ; <float> [#uses=2]
+  %33 = load float, float* null, align 4                 ; <float> [#uses=3]
+  %34 = load float, float* %6, align 4                   ; <float> [#uses=2]
   %35 = fsub float %33, %34                       ; <float> [#uses=2]
   %36 = fmul float %20, %35                       ; <float> [#uses=1]
   %37 = fsub float %36, undef                     ; <float> [#uses=1]
@@ -71,12 +71,12 @@ bb3.i:                                            ; preds = %bb2.i, %bb
   %46 = fadd float %44, %45                       ; <float> [#uses=1]
   %47 = fmul float %33, %43                       ; <float> [#uses=1]
   %48 = fadd float %46, %47                       ; <float> [#uses=2]
-  %49 = load float* %9, align 4                   ; <float> [#uses=2]
+  %49 = load float, float* %9, align 4                   ; <float> [#uses=2]
   %50 = fsub float %30, %49                       ; <float> [#uses=1]
-  %51 = load float* %12, align 4                  ; <float> [#uses=3]
+  %51 = load float, float* %12, align 4                  ; <float> [#uses=3]
   %52 = fsub float %32, %51                       ; <float> [#uses=2]
-  %53 = load float* undef, align 4                ; <float> [#uses=2]
-  %54 = load float* %24, align 4                  ; <float> [#uses=2]
+  %53 = load float, float* undef, align 4                ; <float> [#uses=2]
+  %54 = load float, float* %24, align 4                  ; <float> [#uses=2]
   %55 = fmul float %54, undef                     ; <float> [#uses=1]
   %56 = fmul float undef, %52                     ; <float> [#uses=1]
   %57 = fsub float %55, %56                       ; <float> [#uses=1]
@@ -93,7 +93,7 @@ bb3.i:                                            ; preds = %bb2.i, %bb
   %68 = fsub float %51, %31                       ; <float> [#uses=1]
   %69 = fsub float %53, %33                       ; <float> [#uses=1]
   %70 = fmul float undef, %67                     ; <float> [#uses=1]
-  %71 = load float* undef, align 4                ; <float> [#uses=2]
+  %71 = load float, float* undef, align 4                ; <float> [#uses=2]
   %72 = fmul float %71, %69                       ; <float> [#uses=1]
   %73 = fsub float %70, %72                       ; <float> [#uses=1]
   %74 = fmul float %71, %68                       ; <float> [#uses=1]
diff --git a/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll b/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll
index 832ff4fa0987..8a14804dcf85 100644
--- a/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll
+++ b/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll
@@ -11,7 +11,7 @@
 
 define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quuz* %a, %quuz* %b, %quuz* %c, i8 zeroext %forced) {
 entry:
-  %0 = load %bar** undef, align 4                 ; <%bar*> [#uses=2]
+  %0 = load %bar*, %bar** undef, align 4                 ; <%bar*> [#uses=2]
   br i1 false, label %bb85, label %bb
 
 bb:                                               ; preds = %entry
@@ -21,13 +21,13 @@ bb2.i:                                            ; preds = %bb
   br label %bb3.i
 
 bb3.i:                                            ; preds = %bb2.i, %bb
-  %1 = getelementptr inbounds %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1]
+  %1 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1]
   %2 = fsub float 0.000000e+00, undef             ; <float> [#uses=1]
-  %3 = getelementptr inbounds %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
-  %4 = getelementptr inbounds %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=1]
+  %3 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
+  %4 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=1]
   %5 = fsub float 0.000000e+00, undef             ; <float> [#uses=1]
-  %6 = getelementptr inbounds %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1]
-  %7 = getelementptr inbounds %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
+  %6 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1]
+  %7 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
   %8 = fsub float undef, undef                    ; <float> [#uses=1]
   %9 = fmul float 0.000000e+00, %8                ; <float> [#uses=1]
   %10 = fmul float %5, 0.000000e+00               ; <float> [#uses=1]
@@ -36,17 +36,17 @@ bb3.i:                                            ; preds = %bb2.i, %bb
   %13 = fmul float 0.000000e+00, undef            ; <float> [#uses=1]
   %14 = fsub float %12, %13                       ; <float> [#uses=2]
   store float %14, float* undef
-  %15 = getelementptr inbounds %bar* %0, i32 0, i32 0, i32 0, i32 3 ; <float*> [#uses=1]
+  %15 = getelementptr inbounds %bar, %bar* %0, i32 0, i32 0, i32 0, i32 3 ; <float*> [#uses=1]
   store float 0.000000e+00, float* %15
   %16 = fmul float %11, %11                       ; <float> [#uses=1]
   %17 = fadd float %16, 0.000000e+00              ; <float> [#uses=1]
   %18 = fadd float %17, undef                     ; <float> [#uses=1]
   %19 = call arm_aapcs_vfpcc  float @sqrtf(float %18) readnone ; <float> [#uses=2]
   %20 = fcmp ogt float %19, 0x3F1A36E2E0000000    ; <i1> [#uses=1]
-  %21 = load float* %1, align 4                   ; <float> [#uses=2]
-  %22 = load float* %3, align 4                   ; <float> [#uses=2]
-  %23 = load float* undef, align 4                ; <float> [#uses=2]
-  %24 = load float* %4, align 4                   ; <float> [#uses=2]
+  %21 = load float, float* %1, align 4                   ; <float> [#uses=2]
+  %22 = load float, float* %3, align 4                   ; <float> [#uses=2]
+  %23 = load float, float* undef, align 4                ; <float> [#uses=2]
+  %24 = load float, float* %4, align 4                   ; <float> [#uses=2]
   %25 = fsub float %23, %24                       ; <float> [#uses=2]
   %26 = fmul float 0.000000e+00, %25              ; <float> [#uses=1]
   %27 = fsub float %26, undef                     ; <float> [#uses=1]
@@ -59,11 +59,11 @@ bb3.i:                                            ; preds = %bb2.i, %bb
   %34 = fadd float %32, %33                       ; <float> [#uses=1]
   %35 = fmul float %23, %31                       ; <float> [#uses=1]
   %36 = fadd float %34, %35                       ; <float> [#uses=1]
-  %37 = load float* %6, align 4                   ; <float> [#uses=2]
-  %38 = load float* %7, align 4                   ; <float> [#uses=2]
+  %37 = load float, float* %6, align 4                   ; <float> [#uses=2]
+  %38 = load float, float* %7, align 4                   ; <float> [#uses=2]
   %39 = fsub float %22, %38                       ; <float> [#uses=2]
-  %40 = load float* undef, align 4                ; <float> [#uses=1]
-  %41 = load float* null, align 4                 ; <float> [#uses=2]
+  %40 = load float, float* undef, align 4                ; <float> [#uses=1]
+  %41 = load float, float* null, align 4                 ; <float> [#uses=2]
   %42 = fmul float %41, undef                     ; <float> [#uses=1]
   %43 = fmul float undef, %39                     ; <float> [#uses=1]
   %44 = fsub float %42, %43                       ; <float> [#uses=1]
@@ -80,7 +80,7 @@ bb3.i:                                            ; preds = %bb2.i, %bb
   %55 = fmul float undef, undef                   ; <float> [#uses=1]
   %56 = fsub float %54, %55                       ; <float> [#uses=1]
   %57 = fmul float undef, %53                     ; <float> [#uses=1]
-  %58 = load float* undef, align 4                ; <float> [#uses=2]
+  %58 = load float, float* undef, align 4                ; <float> [#uses=2]
   %59 = fmul float %58, undef                     ; <float> [#uses=1]
   %60 = fsub float %57, %59                       ; <float> [#uses=1]
   %61 = fmul float %58, undef                     ; <float> [#uses=1]
@@ -100,7 +100,7 @@ bb3.i:                                            ; preds = %bb2.i, %bb
   br i1 %72, label %bb4.i97, label %ccc.exit98
 
 bb4.i97:                                          ; preds = %bb3.i
-  %73 = load %bar** undef, align 4                ; <%bar*> [#uses=0]
+  %73 = load %bar*, %bar** undef, align 4                ; <%bar*> [#uses=0]
   br label %ccc.exit98
 
 ccc.exit98:                                       ; preds = %bb4.i97, %bb3.i
diff --git a/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll b/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll
index f89a5de77b3f..8cba9116481e 100644
--- a/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll
+++ b/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll
@@ -11,9 +11,9 @@ entry:
 ;CHECK: vtrn.16
   %0 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
   %1 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
-  %agg.result1218.0 = getelementptr %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 0, i32 0 ; <<8 x i16>*>
+  %agg.result1218.0 = getelementptr %struct.int16x8x2_t, %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 0, i32 0 ; <<8 x i16>*>
   store <8 x i16> %0, <8 x i16>* %agg.result1218.0, align 16
-  %agg.result12.1.0 = getelementptr %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 1, i32 0 ; <<8 x i16>*>
+  %agg.result12.1.0 = getelementptr %struct.int16x8x2_t, %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 1, i32 0 ; <<8 x i16>*>
   store <8 x i16> %1, <8 x i16>* %agg.result12.1.0, align 16
   ret void
 }
@@ -25,9 +25,9 @@ define void @t2(%struct.int16x8x2_t* nocapture %ptr, <4 x i16> %a.0, <4 x i16> %
 entry:
   %0 = shufflevector <4 x i16> %a.0, <4 x i16> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 undef, i32 undef, i32 undef, i32 undef>
   %1 = shufflevector <4 x i16> %a.0, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
-  %ptr26.0 = getelementptr inbounds %struct.int16x8x2_t* %ptr, i32 0, i32 0, i32 0, i32 0
+  %ptr26.0 = getelementptr inbounds %struct.int16x8x2_t, %struct.int16x8x2_t* %ptr, i32 0, i32 0, i32 0, i32 0
   store <8 x i16> %0, <8 x i16>* %ptr26.0, align 16
-  %ptr20.1.0 = getelementptr inbounds %struct.int16x8x2_t* %ptr, i32 0, i32 0, i32 1, i32 0
+  %ptr20.1.0 = getelementptr inbounds %struct.int16x8x2_t, %struct.int16x8x2_t* %ptr, i32 0, i32 0, i32 1, i32 0
   store <8 x i16> %1, <8 x i16>* %ptr20.1.0, align 16
   ret void
 }
diff --git a/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll b/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll
index f7adf73263ff..d21b488bb3a0 100644
--- a/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll
+++ b/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi
 
 define void @"java.lang.String::getChars"([84 x i8]* %method, i32 %base_pc, [788 x i8]* %thread) {
-  %1 = load i32* undef                            ; <i32> [#uses=1]
+  %1 = load i32, i32* undef                            ; <i32> [#uses=1]
   %2 = sub i32 %1, 48                             ; <i32> [#uses=1]
   br i1 undef, label %stack_overflow, label %no_overflow
 
@@ -10,13 +10,13 @@ stack_overflow:                                   ; preds = %0
 
 no_overflow:                                      ; preds = %0
   %frame = inttoptr i32 %2 to [17 x i32]*         ; <[17 x i32]*> [#uses=4]
-  %3 = load i32* undef                            ; <i32> [#uses=1]
-  %4 = load i32* null                             ; <i32> [#uses=1]
-  %5 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 13 ; <i32*> [#uses=1]
+  %3 = load i32, i32* undef                            ; <i32> [#uses=1]
+  %4 = load i32, i32* null                             ; <i32> [#uses=1]
+  %5 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 13 ; <i32*> [#uses=1]
   %6 = bitcast i32* %5 to [8 x i8]**              ; <[8 x i8]**> [#uses=1]
-  %7 = load [8 x i8]** %6                         ; <[8 x i8]*> [#uses=1]
-  %8 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 12 ; <i32*> [#uses=1]
-  %9 = load i32* %8                               ; <i32> [#uses=1]
+  %7 = load [8 x i8]*, [8 x i8]** %6                         ; <[8 x i8]*> [#uses=1]
+  %8 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 12 ; <i32*> [#uses=1]
+  %9 = load i32, i32* %8                               ; <i32> [#uses=1]
   br i1 undef, label %bci_13, label %bci_4
 
 bci_13:                                           ; preds = %no_overflow
@@ -27,18 +27,18 @@ bci_30:                                           ; preds = %bci_13
 
 bci_46:                                           ; preds = %bci_30
   %10 = sub i32 %4, %3                            ; <i32> [#uses=1]
-  %11 = load [8 x i8]** null                      ; <[8 x i8]*> [#uses=1]
+  %11 = load [8 x i8]*, [8 x i8]** null                      ; <[8 x i8]*> [#uses=1]
   %callee = bitcast [8 x i8]* %11 to [84 x i8]*   ; <[84 x i8]*> [#uses=1]
   %12 = bitcast i8* undef to i32*                 ; <i32*> [#uses=1]
-  %base_pc7 = load i32* %12                       ; <i32> [#uses=2]
+  %base_pc7 = load i32, i32* %12                       ; <i32> [#uses=2]
   %13 = add i32 %base_pc7, 0                      ; <i32> [#uses=1]
   %14 = inttoptr i32 %13 to void ([84 x i8]*, i32, [788 x i8]*)** ; <void ([84 x i8]*, i32, [788 x i8]*)**> [#uses=1]
-  %entry_point = load void ([84 x i8]*, i32, [788 x i8]*)** %14 ; <void ([84 x i8]*, i32, [788 x i8]*)*> [#uses=1]
-  %15 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 1 ; <i32*> [#uses=1]
+  %entry_point = load void ([84 x i8]*, i32, [788 x i8]*)*, void ([84 x i8]*, i32, [788 x i8]*)** %14 ; <void ([84 x i8]*, i32, [788 x i8]*)*> [#uses=1]
+  %15 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 1 ; <i32*> [#uses=1]
   %16 = ptrtoint i32* %15 to i32                  ; <i32> [#uses=1]
   %stack_pointer_addr9 = bitcast i8* undef to i32* ; <i32*> [#uses=1]
   store i32 %16, i32* %stack_pointer_addr9
-  %17 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 2 ; <i32*> [#uses=1]
+  %17 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 2 ; <i32*> [#uses=1]
   store i32 %9, i32* %17
   store i32 %10, i32* undef
   store [84 x i8]* %method, [84 x i8]** undef
diff --git a/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll b/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll
index 5e75d460aa7f..a1923ec2c3e0 100644
--- a/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll
+++ b/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll
@@ -9,10 +9,10 @@ stack_overflow:                                   ; preds = %0
 
 no_overflow:                                      ; preds = %0
   %frame = inttoptr i32 %1 to [17 x i32]*         ; <[17 x i32]*> [#uses=4]
-  %2 = load i32* null                             ; <i32> [#uses=2]
-  %3 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 14 ; <i32*> [#uses=1]
-  %4 = load i32* %3                               ; <i32> [#uses=2]
-  %5 = load [8 x i8]** undef                      ; <[8 x i8]*> [#uses=2]
+  %2 = load i32, i32* null                             ; <i32> [#uses=2]
+  %3 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 14 ; <i32*> [#uses=1]
+  %4 = load i32, i32* %3                               ; <i32> [#uses=2]
+  %5 = load [8 x i8]*, [8 x i8]** undef                      ; <[8 x i8]*> [#uses=2]
   br i1 undef, label %bci_13, label %bci_4
 
 bci_13:                                           ; preds = %no_overflow
@@ -33,11 +33,11 @@ no_exception:                                     ; preds = %bci_46
   ret void
 
 bci_35:                                           ; preds = %bci_30
-  %7 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 15 ; <i32*> [#uses=1]
+  %7 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 15 ; <i32*> [#uses=1]
   store i32 %2, i32* %7
-  %8 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 14 ; <i32*> [#uses=1]
+  %8 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 14 ; <i32*> [#uses=1]
   store i32 %4, i32* %8
-  %9 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 13 ; <i32*> [#uses=1]
+  %9 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 13 ; <i32*> [#uses=1]
   %10 = bitcast i32* %9 to [8 x i8]**             ; <[8 x i8]**> [#uses=1]
   store [8 x i8]* %5, [8 x i8]** %10
   call void inttoptr (i32 13839116 to void ([788 x i8]*, i32)*)([788 x i8]* %thread, i32 7)
diff --git a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll
index 6f7db9352188..638b26c73146 100644
--- a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll
+++ b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll
@@ -5,7 +5,7 @@ target triple = "armv4t-apple-darwin10"
 
 define hidden i32 @__addvsi3(i32 %a, i32 %b) nounwind {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 %b, i64 0, metadata !0, metadata !{!"0x102"})
+  tail call void @llvm.dbg.value(metadata i32 %b, i64 0, metadata !0, metadata !DIExpression()), !dbg !DILocation(scope: !1)
   %0 = add nsw i32 %b, %a, !dbg !9                ; <i32> [#uses=1]
   ret i32 %0, !dbg !11
 }
@@ -14,19 +14,19 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 
 !llvm.dbg.cu = !{!3}
 !llvm.module.flags = !{!15}
-!0 = !{!"0x101\00b\0093\000", !1, !2, !6} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00__addvsi3\00__addvsi3\00__addvsi3\0094\000\001\000\006\000\000\000", !12, null, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !12} ; [ DW_TAG_file_type ]
-!12 = !{!"libgcc2.c", !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc"}
-!3 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)\001\00\000\00\000", !12, !13, !13, !14, null, null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !12, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 93, arg: 0, scope: !1, file: !2, type: !6)
+!1 = !DISubprogram(name: "__addvsi3", linkageName: "__addvsi3", line: 94, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !12, scope: null, type: !4)
+!2 = !DIFile(filename: "libgcc2.c", directory: "/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc")
+!12 = !DIFile(filename: "libgcc2.c", directory: "/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc")
+!3 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)", isOptimized: true, emissionKind: 0, file: !12, enums: !13, retainedTypes: !13, subprograms: !14)
+!4 = !DISubroutineType(types: !5)
 !5 = !{!6, !6, !6}
-!6 = !{!"0x16\00SItype\00152\000\000\000\000", !12, null, !8} ; [ DW_TAG_typedef ]
-!7 = !{!"0x29", !"libgcc2.h", !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc", !3} ; [ DW_TAG_file_type ]
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", !12, !2} ; [ DW_TAG_base_type ]
-!9 = !MDLocation(line: 95, scope: !10)
-!10 = !{!"0xb\0094\000\000", !12, !1} ; [ DW_TAG_lexical_block ]
-!11 = !MDLocation(line: 100, scope: !10)
-!13 = !{i32 0}
+!6 = !DIDerivedType(tag: DW_TAG_typedef, name: "SItype", line: 152, file: !12, baseType: !8)
+!7 = !DIFile(filename: "libgcc2.h", directory: "/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc")
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DILocation(line: 95, scope: !10)
+!10 = distinct !DILexicalBlock(line: 94, column: 0, file: !12, scope: !1)
+!11 = !DILocation(line: 100, scope: !10)
+!13 = !{}
 !14 = !{!1}
-!15 = !{i32 1, !"Debug Info Version", i32 2}
+!15 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll b/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll
index 7d4cc6e3a75a..5f5489a1ca74 100644
--- a/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll
+++ b/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll
@@ -82,17 +82,17 @@ cond_true1369.preheader:                          ; preds = %cond_true1254
   ret void
 
 bb1567:                                           ; preds = %cond_true1254
-  %tmp1591 = load i64* getelementptr inbounds (%struct.CHESS_POSITION* @search, i32 0, i32 4) ; <i64> [#uses=1]
+  %tmp1591 = load i64, i64* getelementptr inbounds (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 4) ; <i64> [#uses=1]
   %tmp1572 = tail call fastcc i32 @FirstOne()     ; <i32> [#uses=1]
-  %tmp1594 = load i32* undef                      ; <i32> [#uses=1]
+  %tmp1594 = load i32, i32* undef                      ; <i32> [#uses=1]
   %tmp1594.upgrd.5 = trunc i32 %tmp1594 to i8     ; <i8> [#uses=1]
   %shift.upgrd.6 = zext i8 %tmp1594.upgrd.5 to i64 ; <i64> [#uses=1]
   %tmp1595 = lshr i64 %tmp1591, %shift.upgrd.6    ; <i64> [#uses=1]
   %tmp1595.upgrd.7 = trunc i64 %tmp1595 to i32    ; <i32> [#uses=1]
   %tmp1596 = and i32 %tmp1595.upgrd.7, 255        ; <i32> [#uses=1]
   %gep.upgrd.8 = zext i32 %tmp1596 to i64         ; <i64> [#uses=1]
-  %tmp1598 = getelementptr [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; <i32*> [#uses=1]
-  %tmp1599 = load i32* %tmp1598                   ; <i32> [#uses=1]
+  %tmp1598 = getelementptr [64 x [256 x i32]], [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; <i32*> [#uses=1]
+  %tmp1599 = load i32, i32* %tmp1598                   ; <i32> [#uses=1]
   %tmp1602 = sub i32 0, %tmp1599                  ; <i32> [#uses=1]
   br i1 undef, label %cond_next1637, label %cond_true1607
 
diff --git a/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll b/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll
index 946164321a2c..deb588403265 100644
--- a/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll
+++ b/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll
@@ -16,15 +16,15 @@ entry:
   %vla10 = alloca i8, i32 undef, align 1          ; <i8*> [#uses=1]
   %vla14 = alloca i8, i32 undef, align 1          ; <i8*> [#uses=1]
   %vla18 = alloca i8, i32 undef, align 1          ; <i8*> [#uses=1]
-  %tmp21 = load i32* undef                        ; <i32> [#uses=1]
+  %tmp21 = load i32, i32* undef                        ; <i32> [#uses=1]
   %0 = mul i32 1, %tmp21                          ; <i32> [#uses=1]
   %vla22 = alloca i8, i32 %0, align 1             ; <i8*> [#uses=1]
-  call  void (...)* @zz(i8* getelementptr inbounds ([1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1)
+  call  void (...) @zz(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1)
   br i1 undef, label %if.then, label %if.end36
 
 if.then:                                          ; preds = %entry
-  %call = call  i32 (...)* @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; <i32> [#uses=0]
-  %call35 = call  i32 (...)* @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; <i32> [#uses=0]
+  %call = call  i32 (...) @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; <i32> [#uses=0]
+  %call35 = call  i32 (...) @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; <i32> [#uses=0]
   unreachable
 
 if.end36:                                         ; preds = %entry
diff --git a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
index b040b2d91cd6..24469cc3717e 100644
--- a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
+++ b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
@@ -16,12 +16,12 @@ entry:
 ; THUMB-DAG:       movs [[VAL:r[0-9]+]], #0
 ; THUMB-NOT: str {{[a-z0-9]+}}, [{{[a-z0-9]+}}], {{[a-z0-9]+}}
 ; THUMB:     str [[VAL]], [r[[ADDR]]]
-  %0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1]
+  %0 = getelementptr inbounds %struct.foo, %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1]
   store i32 0, i32* inttoptr (i32 8 to i32*), align 8
   br i1 %tst, label %bb.nph96, label %bb3
 
 bb3:                                              ; preds = %entry
-  %1 = load i64* %0, align 4                      ; <i64> [#uses=0]
+  %1 = load i64, i64* %0, align 4                      ; <i64> [#uses=0]
   ret i8 42
 
 bb.nph96:                                         ; preds = %entry
diff --git a/test/CodeGen/ARM/2010-05-19-Shuffles.ll b/test/CodeGen/ARM/2010-05-19-Shuffles.ll
index 587c0afcb714..94d0f4abfb7e 100644
--- a/test/CodeGen/ARM/2010-05-19-Shuffles.ll
+++ b/test/CodeGen/ARM/2010-05-19-Shuffles.ll
@@ -14,7 +14,7 @@ define <8 x i8> @f2(<8 x i8> %x) nounwind {
 }
 
 define void @f3(<4 x i64>* %xp) nounwind {
-  %x = load <4 x i64>* %xp
+  %x = load <4 x i64>, <4 x i64>* %xp
   %y = shufflevector <4 x i64> %x, <4 x i64> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 1>
   store <4 x i64> %y, <4 x i64>* %xp
   ret void
diff --git a/test/CodeGen/ARM/2010-05-21-BuildVector.ll b/test/CodeGen/ARM/2010-05-21-BuildVector.ll
index 5bc08b037a1c..6a6ccf3d0a01 100644
--- a/test/CodeGen/ARM/2010-05-21-BuildVector.ll
+++ b/test/CodeGen/ARM/2010-05-21-BuildVector.ll
@@ -3,36 +3,36 @@
 
 define void @test(float* %fltp, i32 %packedValue, float* %table) nounwind {
 entry:
-  %0 = load float* %fltp
+  %0 = load float, float* %fltp
   %1 = insertelement <4 x float> undef, float %0, i32 0
   %2 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> zeroinitializer
   %3 = shl i32 %packedValue, 16
   %4 = ashr i32 %3, 30
   %.sum = add i32 %4, 4
-  %5 = getelementptr inbounds float* %table, i32 %.sum
+  %5 = getelementptr inbounds float, float* %table, i32 %.sum
 ;CHECK: vldr s
-  %6 = load float* %5, align 4
+  %6 = load float, float* %5, align 4
   %tmp11 = insertelement <4 x float> undef, float %6, i32 0
   %7 = shl i32 %packedValue, 18
   %8 = ashr i32 %7, 30
   %.sum12 = add i32 %8, 4
-  %9 = getelementptr inbounds float* %table, i32 %.sum12
+  %9 = getelementptr inbounds float, float* %table, i32 %.sum12
 ;CHECK: vldr s
-  %10 = load float* %9, align 4
+  %10 = load float, float* %9, align 4
   %tmp9 = insertelement <4 x float> %tmp11, float %10, i32 1
   %11 = shl i32 %packedValue, 20
   %12 = ashr i32 %11, 30
   %.sum13 = add i32 %12, 4
-  %13 = getelementptr inbounds float* %table, i32 %.sum13
+  %13 = getelementptr inbounds float, float* %table, i32 %.sum13
 ;CHECK: vldr s
-  %14 = load float* %13, align 4
+  %14 = load float, float* %13, align 4
   %tmp7 = insertelement <4 x float> %tmp9, float %14, i32 2
   %15 = shl i32 %packedValue, 22
   %16 = ashr i32 %15, 30
   %.sum14 = add i32 %16, 4
-  %17 = getelementptr inbounds float* %table, i32 %.sum14
+  %17 = getelementptr inbounds float, float* %table, i32 %.sum14
 ;CHECK: vldr s
-  %18 = load float* %17, align 4
+  %18 = load float, float* %17, align 4
   %tmp5 = insertelement <4 x float> %tmp7, float %18, i32 3
   %19 = fmul <4 x float> %tmp5, %2
   %20 = bitcast float* %fltp to i8*
diff --git a/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll b/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll
index f7ceb6e7e480..f86c3ba9ef6e 100644
--- a/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll
+++ b/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll
@@ -6,7 +6,7 @@
 define void @foo(%struct.__int8x8x2_t* nocapture %a, i8* %b) nounwind {
 entry:
  %0 = bitcast %struct.__int8x8x2_t* %a to i128*  ; <i128*> [#uses=1]
- %srcval = load i128* %0, align 8                ; <i128> [#uses=2]
+ %srcval = load i128, i128* %0, align 8                ; <i128> [#uses=2]
  %tmp6 = trunc i128 %srcval to i64               ; <i64> [#uses=1]
  %tmp8 = lshr i128 %srcval, 64                   ; <i128> [#uses=1]
  %tmp9 = trunc i128 %tmp8 to i64                 ; <i64> [#uses=1]
diff --git a/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll b/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll
index 816a6d4f4b93..6f55ac058054 100644
--- a/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll
+++ b/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll
@@ -13,15 +13,15 @@
 define void @TW_oldinput(%struct.FILE* nocapture %fp) nounwind {
 entry:
   %xcenter = alloca i32, align 4                  ; <i32*> [#uses=2]
-  %0 = call i32 (%struct.FILE*, i8*, ...)* @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1]
+  %0 = call i32 (%struct.FILE*, i8*, ...) @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1]
   %1 = icmp eq i32 %0, 4                          ; <i1> [#uses=1]
   br i1 %1, label %bb, label %return
 
 bb:                                               ; preds = %bb445, %entry
-  %2 = load %struct.cellbox** undef, align 4      ; <%struct.cellbox*> [#uses=2]
-  %3 = getelementptr inbounds %struct.cellbox* %2, i32 0, i32 3 ; <i32*> [#uses=1]
+  %2 = load %struct.cellbox*, %struct.cellbox** undef, align 4      ; <%struct.cellbox*> [#uses=2]
+  %3 = getelementptr inbounds %struct.cellbox, %struct.cellbox* %2, i32 0, i32 3 ; <i32*> [#uses=1]
   store i32 undef, i32* %3, align 4
-  %4 = load i32* undef, align 4                   ; <i32> [#uses=3]
+  %4 = load i32, i32* undef, align 4                   ; <i32> [#uses=3]
   %5 = icmp eq i32 undef, 1                       ; <i1> [#uses=1]
   br i1 %5, label %bb10, label %bb445
 
@@ -29,12 +29,12 @@ bb10:                                             ; preds = %bb
   br i1 undef, label %bb11, label %bb445
 
 bb11:                                             ; preds = %bb10
-  %6 = load %struct.tilebox** undef, align 4      ; <%struct.tilebox*> [#uses=3]
-  %7 = load %struct.termbox** null, align 4       ; <%struct.termbox*> [#uses=1]
-  %8 = getelementptr inbounds %struct.tilebox* %6, i32 0, i32 13 ; <i32*> [#uses=1]
-  %9 = load i32* %8, align 4                      ; <i32> [#uses=3]
-  %10 = getelementptr inbounds %struct.tilebox* %6, i32 0, i32 15 ; <i32*> [#uses=1]
-  %11 = load i32* %10, align 4                    ; <i32> [#uses=1]
+  %6 = load %struct.tilebox*, %struct.tilebox** undef, align 4      ; <%struct.tilebox*> [#uses=3]
+  %7 = load %struct.termbox*, %struct.termbox** null, align 4       ; <%struct.termbox*> [#uses=1]
+  %8 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %6, i32 0, i32 13 ; <i32*> [#uses=1]
+  %9 = load i32, i32* %8, align 4                      ; <i32> [#uses=3]
+  %10 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %6, i32 0, i32 15 ; <i32*> [#uses=1]
+  %11 = load i32, i32* %10, align 4                    ; <i32> [#uses=1]
   br i1 false, label %bb12, label %bb13
 
 bb12:                                             ; preds = %bb11
@@ -67,7 +67,7 @@ bb21:                                             ; preds = %bb13
   %25 = zext i1 %not.461 to i32                   ; <i32> [#uses=1]
   %iftmp.43.0 = add i32 %23, %iftmp.41.0.neg      ; <i32> [#uses=1]
   %26 = add i32 %iftmp.43.0, %25                  ; <i32> [#uses=1]
-  %27 = getelementptr inbounds %struct.tilebox* %6, i32 0, i32 10 ; <i32*> [#uses=1]
+  %27 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %6, i32 0, i32 10 ; <i32*> [#uses=1]
   store i32 %26, i32* %27, align 4
   %28 = fptosi double undef to i32                ; <i32> [#uses=1]
   %iftmp.45.0 = add i32 %28, %iftmp.40.0.neg      ; <i32> [#uses=1]
@@ -77,7 +77,7 @@ bb21:                                             ; preds = %bb13
 
 bb36:                                             ; preds = %bb43.loopexit, %bb36
   %termptr.0478 = phi %struct.termbox* [ %42, %bb36 ], [ %7, %bb43.loopexit ] ; <%struct.termbox*> [#uses=1]
-  %30 = load i32* undef, align 4                  ; <i32> [#uses=1]
+  %30 = load i32, i32* undef, align 4                  ; <i32> [#uses=1]
   %31 = sub nsw i32 %30, %9                       ; <i32> [#uses=1]
   %32 = sitofp i32 %31 to double                  ; <double> [#uses=1]
   %33 = fdiv double %32, 0.000000e+00             ; <double> [#uses=1]
@@ -92,8 +92,8 @@ bb36:                                             ; preds = %bb43.loopexit, %bb3
   %iftmp.47.0 = add i32 %39, %iftmp.40.0.neg      ; <i32> [#uses=1]
   %40 = add i32 %iftmp.47.0, 0                    ; <i32> [#uses=1]
   store i32 %40, i32* undef, align 4
-  %41 = getelementptr inbounds %struct.termbox* %termptr.0478, i32 0, i32 0 ; <%struct.termbox**> [#uses=1]
-  %42 = load %struct.termbox** %41, align 4       ; <%struct.termbox*> [#uses=2]
+  %41 = getelementptr inbounds %struct.termbox, %struct.termbox* %termptr.0478, i32 0, i32 0 ; <%struct.termbox**> [#uses=1]
+  %42 = load %struct.termbox*, %struct.termbox** %41, align 4       ; <%struct.termbox*> [#uses=2]
   %43 = icmp eq %struct.termbox* %42, null        ; <i1> [#uses=1]
   br i1 %43, label %bb52.loopexit, label %bb36
 
@@ -127,9 +127,9 @@ bb248:                                            ; preds = %bb322, %bb.nph485
   br i1 %45, label %bb322, label %bb249
 
 bb249:                                            ; preds = %bb248
-  %46 = getelementptr inbounds %struct.cellbox* %2, i32 0, i32 21, i32 undef ; <%struct.tilebox**> [#uses=1]
-  %47 = load %struct.tilebox** %46, align 4       ; <%struct.tilebox*> [#uses=1]
-  %48 = getelementptr inbounds %struct.tilebox* %47, i32 0, i32 11 ; <i32*> [#uses=1]
+  %46 = getelementptr inbounds %struct.cellbox, %struct.cellbox* %2, i32 0, i32 21, i32 undef ; <%struct.tilebox**> [#uses=1]
+  %47 = load %struct.tilebox*, %struct.tilebox** %46, align 4       ; <%struct.tilebox*> [#uses=1]
+  %48 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %47, i32 0, i32 11 ; <i32*> [#uses=1]
   store i32 undef, i32* %48, align 4
   unreachable
 
@@ -137,7 +137,7 @@ bb322:                                            ; preds = %bb248
   br i1 undef, label %bb248, label %bb445
 
 bb445:                                            ; preds = %bb322, %bb10, %bb
-  %49 = call i32 (%struct.FILE*, i8*, ...)* @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1]
+  %49 = call i32 (%struct.FILE*, i8*, ...) @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1]
   %50 = icmp eq i32 %49, 4                        ; <i1> [#uses=1]
   br i1 %50, label %bb, label %return
 
diff --git a/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll b/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll
index ac8e80904eda..bead8d9781e8 100755
--- a/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll
+++ b/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll
@@ -33,9 +33,9 @@ define %"struct.llvm::Init"* @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9
 ;CHECK:  bx  r12  @ TAILCALL
 entry:
   %.loc = alloca i32                              ; <i32*> [#uses=2]
-  %tmp.i = getelementptr inbounds %"class.llvm::StringInit"* %this, i32 0, i32 0, i32 4 ; <i8*> [#uses=1]
+  %tmp.i = getelementptr inbounds %"class.llvm::StringInit", %"class.llvm::StringInit"* %this, i32 0, i32 0, i32 4 ; <i8*> [#uses=1]
   %0 = bitcast i8* %tmp.i to %"struct.llvm::Init"** ; <%"struct.llvm::Init"**> [#uses=1]
-  %tmp2.i = load %"struct.llvm::Init"** %0        ; <%"struct.llvm::Init"*> [#uses=2]
+  %tmp2.i = load %"struct.llvm::Init"*, %"struct.llvm::Init"** %0        ; <%"struct.llvm::Init"*> [#uses=2]
   %1 = icmp eq %"struct.llvm::Init"* %tmp2.i, null ; <i1> [#uses=1]
   br i1 %1, label %entry.return_crit_edge, label %tmpbb
 
@@ -52,17 +52,17 @@ tmpbb:                                            ; preds = %entry
   br label %return
 
 if.then:                                          ; preds = %tmpbb
-  %tmp2.i.i.i.i = getelementptr inbounds %"class.llvm::StringInit"* %this, i32 0, i32 1, i32 0, i32 0 ; <i8**> [#uses=1]
-  %tmp3.i.i.i.i = load i8** %tmp2.i.i.i.i         ; <i8*> [#uses=2]
-  %arrayidx.i.i.i.i = getelementptr inbounds i8* %tmp3.i.i.i.i, i32 -12 ; <i8*> [#uses=1]
+  %tmp2.i.i.i.i = getelementptr inbounds %"class.llvm::StringInit", %"class.llvm::StringInit"* %this, i32 0, i32 1, i32 0, i32 0 ; <i8**> [#uses=1]
+  %tmp3.i.i.i.i = load i8*, i8** %tmp2.i.i.i.i         ; <i8*> [#uses=2]
+  %arrayidx.i.i.i.i = getelementptr inbounds i8, i8* %tmp3.i.i.i.i, i32 -12 ; <i8*> [#uses=1]
   %tmp.i.i.i = bitcast i8* %arrayidx.i.i.i.i to i32* ; <i32*> [#uses=1]
-  %tmp2.i.i.i = load i32* %tmp.i.i.i              ; <i32> [#uses=1]
-  %tmp.i5 = getelementptr inbounds %"class.llvm::Record"* %R, i32 0, i32 4 ; <%"class.std::vector"*> [#uses=1]
-  %tmp2.i.i = getelementptr inbounds %"class.llvm::Record"* %R, i32 0, i32 4, i32 0, i32 4 ; <i8*> [#uses=1]
+  %tmp2.i.i.i = load i32, i32* %tmp.i.i.i              ; <i32> [#uses=1]
+  %tmp.i5 = getelementptr inbounds %"class.llvm::Record", %"class.llvm::Record"* %R, i32 0, i32 4 ; <%"class.std::vector"*> [#uses=1]
+  %tmp2.i.i = getelementptr inbounds %"class.llvm::Record", %"class.llvm::Record"* %R, i32 0, i32 4, i32 0, i32 4 ; <i8*> [#uses=1]
   %4 = bitcast i8* %tmp2.i.i to %"class.llvm::RecordVal"** ; <%"class.llvm::RecordVal"**> [#uses=1]
-  %tmp3.i.i6 = load %"class.llvm::RecordVal"** %4 ; <%"class.llvm::RecordVal"*> [#uses=1]
+  %tmp3.i.i6 = load %"class.llvm::RecordVal"*, %"class.llvm::RecordVal"** %4 ; <%"class.llvm::RecordVal"*> [#uses=1]
   %tmp5.i.i = bitcast %"class.std::vector"* %tmp.i5 to %"class.llvm::RecordVal"** ; <%"class.llvm::RecordVal"**> [#uses=1]
-  %tmp6.i.i = load %"class.llvm::RecordVal"** %tmp5.i.i ; <%"class.llvm::RecordVal"*> [#uses=5]
+  %tmp6.i.i = load %"class.llvm::RecordVal"*, %"class.llvm::RecordVal"** %tmp5.i.i ; <%"class.llvm::RecordVal"*> [#uses=5]
   %sub.ptr.lhs.cast.i.i = ptrtoint %"class.llvm::RecordVal"* %tmp3.i.i6 to i32 ; <i32> [#uses=1]
   %sub.ptr.rhs.cast.i.i = ptrtoint %"class.llvm::RecordVal"* %tmp6.i.i to i32 ; <i32> [#uses=1]
   %sub.ptr.sub.i.i = sub i32 %sub.ptr.lhs.cast.i.i, %sub.ptr.rhs.cast.i.i ; <i32> [#uses=1]
@@ -71,14 +71,14 @@ if.then:                                          ; preds = %tmpbb
 
 codeRepl:                                         ; preds = %if.then
   %targetBlock = call i1 @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs_for.cond.i(i32 %sub.ptr.div.i.i, %"class.llvm::RecordVal"* %tmp6.i.i, i32 %tmp2.i.i.i, i8* %tmp3.i.i.i.i, i32* %.loc) ; <i1> [#uses=1]
-  %.reload = load i32* %.loc                      ; <i32> [#uses=3]
+  %.reload = load i32, i32* %.loc                      ; <i32> [#uses=3]
   br i1 %targetBlock, label %for.cond.i.return_crit_edge, label %_ZN4llvm6Record8getValueENS_9StringRefE.exit
 
 for.cond.i.return_crit_edge:                      ; preds = %codeRepl
   br label %return
 
 _ZN4llvm6Record8getValueENS_9StringRefE.exit:     ; preds = %codeRepl
-  %add.ptr.i.i = getelementptr inbounds %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload ; <%"class.llvm::RecordVal"*> [#uses=2]
+  %add.ptr.i.i = getelementptr inbounds %"class.llvm::RecordVal", %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload ; <%"class.llvm::RecordVal"*> [#uses=2]
   %tobool5 = icmp eq %"class.llvm::RecordVal"* %add.ptr.i.i, null ; <i1> [#uses=1]
   br i1 %tobool5, label %_ZN4llvm6Record8getValueENS_9StringRefE.exit.return_crit_edge, label %if.then6
 
@@ -100,8 +100,8 @@ land.lhs.true.return_crit_edge:                   ; preds = %land.lhs.true
   br label %return
 
 lor.lhs.false:                                    ; preds = %land.lhs.true
-  %tmp.i3 = getelementptr inbounds %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1]
-  %tmp2.i4 = load %"struct.llvm::Init"** %tmp.i3  ; <%"struct.llvm::Init"*> [#uses=2]
+  %tmp.i3 = getelementptr inbounds %"class.llvm::RecordVal", %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1]
+  %tmp2.i4 = load %"struct.llvm::Init"*, %"struct.llvm::Init"** %tmp.i3  ; <%"struct.llvm::Init"*> [#uses=2]
   %5 = icmp eq %"struct.llvm::Init"* %tmp2.i4, null ; <i1> [#uses=1]
   br i1 %5, label %lor.lhs.false.if.end_crit_edge, label %tmpbb1
 
@@ -121,21 +121,21 @@ tmpbb1:                                           ; preds = %lor.lhs.false
   br label %if.end
 
 if.end:                                           ; preds = %.if.end_crit_edge, %lor.lhs.false.if.end_crit_edge, %if.then6.if.end_crit_edge
-  %tmp.i1 = getelementptr inbounds %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1]
-  %tmp2.i2 = load %"struct.llvm::Init"** %tmp.i1  ; <%"struct.llvm::Init"*> [#uses=3]
+  %tmp.i1 = getelementptr inbounds %"class.llvm::RecordVal", %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1]
+  %tmp2.i2 = load %"struct.llvm::Init"*, %"struct.llvm::Init"** %tmp.i1  ; <%"struct.llvm::Init"*> [#uses=3]
   %8 = bitcast %"class.llvm::StringInit"* %this to %"struct.llvm::Init"* ; <%"struct.llvm::Init"*> [#uses=1]
   %cmp19 = icmp eq %"struct.llvm::Init"* %tmp2.i2, %8 ; <i1> [#uses=1]
   br i1 %cmp19, label %cond.false, label %cond.end
 
 cond.false:                                       ; preds = %if.end
-  tail call void @__assert_fail(i8* getelementptr inbounds ([45 x i8]* @.str51, i32 0, i32 0), i8* getelementptr inbounds ([47 x i8]* @.str8, i32 0, i32 0), i32 1141, i8* getelementptr inbounds ([116 x i8]* @__PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs, i32 0, i32 0)) noreturn
+  tail call void @__assert_fail(i8* getelementptr inbounds ([45 x i8], [45 x i8]* @.str51, i32 0, i32 0), i8* getelementptr inbounds ([47 x i8], [47 x i8]* @.str8, i32 0, i32 0), i32 1141, i8* getelementptr inbounds ([116 x i8], [116 x i8]* @__PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs, i32 0, i32 0)) noreturn
   unreachable
 
 cond.end:                                         ; preds = %if.end
   %9 = bitcast %"struct.llvm::Init"* %tmp2.i2 to %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)***> [#uses=1]
-  %10 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** %9 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1]
-  %vfn = getelementptr inbounds %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %10, i32 8 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1]
-  %11 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %vfn ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*> [#uses=1]
+  %10 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**, %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** %9 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1]
+  %vfn = getelementptr inbounds %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*, %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %10, i32 8 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1]
+  %11 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*, %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %vfn ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*> [#uses=1]
   %call25 = tail call %"struct.llvm::Init"* %11(%"struct.llvm::Init"* %tmp2.i2, %"class.llvm::Record"* %R, %"class.llvm::RecordVal"* %RV, %"class.std::basic_string"* %FieldName) ; <%"struct.llvm::Init"*> [#uses=1]
   ret %"struct.llvm::Init"* %call25
 
diff --git a/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll
index 18b3be0aba5c..95bb2769759e 100644
--- a/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll
+++ b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll
@@ -7,21 +7,21 @@ target triple = "thumbv7-apple-darwin3.0.0-iphoneos"
 
 define void @x0(i8* nocapture %buf, i32 %nbytes) nounwind optsize {
 entry:
-  tail call void @llvm.dbg.value(metadata i8* %buf, i64 0, metadata !0, metadata !{!"0x102"}), !dbg !15
-  tail call void @llvm.dbg.value(metadata i32 %nbytes, i64 0, metadata !8, metadata !{!"0x102"}), !dbg !16
-  %tmp = load i32* @length, !dbg !17              ; <i32> [#uses=3]
+  tail call void @llvm.dbg.value(metadata i8* %buf, i64 0, metadata !0, metadata !DIExpression()), !dbg !15
+  tail call void @llvm.dbg.value(metadata i32 %nbytes, i64 0, metadata !8, metadata !DIExpression()), !dbg !16
+  %tmp = load i32, i32* @length, !dbg !17              ; <i32> [#uses=3]
   %cmp = icmp eq i32 %tmp, -1, !dbg !17           ; <i1> [#uses=1]
   %cmp.not = xor i1 %cmp, true                    ; <i1> [#uses=1]
   %cmp3 = icmp ult i32 %tmp, %nbytes, !dbg !17    ; <i1> [#uses=1]
   %or.cond = and i1 %cmp.not, %cmp3               ; <i1> [#uses=1]
-  tail call void @llvm.dbg.value(metadata i32 %tmp, i64 0, metadata !8, metadata !{!"0x102"}), !dbg !17
+  tail call void @llvm.dbg.value(metadata i32 %tmp, i64 0, metadata !8, metadata !DIExpression()), !dbg !17
   %nbytes.addr.0 = select i1 %or.cond, i32 %tmp, i32 %nbytes ; <i32> [#uses=1]
-  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !19
+  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !10, metadata !DIExpression()), !dbg !19
   br label %while.cond, !dbg !20
 
 while.cond:                                       ; preds = %while.body, %entry
   %0 = phi i32 [ 0, %entry ], [ %inc, %while.body ] ; <i32> [#uses=3]
-  %buf.addr.0 = getelementptr i8* %buf, i32 %0    ; <i8*> [#uses=1]
+  %buf.addr.0 = getelementptr i8, i8* %buf, i32 %0    ; <i8*> [#uses=1]
   %cmp7 = icmp ult i32 %0, %nbytes.addr.0, !dbg !20 ; <i1> [#uses=1]
   br i1 %cmp7, label %land.rhs, label %while.end, !dbg !20
 
@@ -47,30 +47,30 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.lv.fn = !{!0, !8, !10, !12}
 !llvm.dbg.gv = !{!14}
 
-!0 = !{!"0x101\00buf\004\000", !1, !2, !6} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00x0\00x0\00x0\005\000\001\000\006\000\000\000", !26, null, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !26} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\0012\00clang 2.0\001\00\00\00\00", !26, null, null, null, null, null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !26, !2, null, !5, null} ; [ DW_TAG_subroutine_type ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "buf", line: 4, arg: 0, scope: !1, file: !2, type: !6)
+!1 = !DISubprogram(name: "x0", linkageName: "x0", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !26, scope: null, type: !4)
+!2 = !DIFile(filename: "t.c", directory: "/private/tmp")
+!3 = !DICompileUnit(language: DW_LANG_C99, producer: "clang 2.0", isOptimized: true, file: !26)
+!4 = !DISubroutineType(types: !5)
 !5 = !{null}
-!6 = !{!"0xf\00\000\0032\0032\000\000", !26, !2, !7} ; [ DW_TAG_pointer_type ]
-!7 = !{!"0x24\00unsigned char\000\008\008\000\000\008", !26, !2} ; [ DW_TAG_base_type ]
-!8 = !{!"0x101\00nbytes\004\000", !1, !2, !9} ; [ DW_TAG_arg_variable ]
-!9 = !{!"0x24\00unsigned long\000\0032\0032\000\000\007", !26, !2} ; [ DW_TAG_base_type ]
-!10 = !{!"0x100\00nread\006\000", !11, !2, !9} ; [ DW_TAG_auto_variable ]
-!11 = !{!"0xb\005\001\000", !26, !1} ; [ DW_TAG_lexical_block ]
-!12 = !{!"0x100\00c\007\000", !11, !2, !13} ; [ DW_TAG_auto_variable ]
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", !26, !2} ; [ DW_TAG_base_type ]
-!14 = !{!"0x34\00length\00length\00length\001\000\001", !2, !2, !13, i32* @length} ; [ DW_TAG_variable ]
-!15 = !MDLocation(line: 4, column: 24, scope: !1)
-!16 = !MDLocation(line: 4, column: 43, scope: !1)
-!17 = !MDLocation(line: 9, column: 2, scope: !11)
+!6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !26, scope: !2, baseType: !7)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char)
+!8 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "nbytes", line: 4, arg: 0, scope: !1, file: !2, type: !9)
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned long", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "nread", line: 6, scope: !11, file: !2, type: !9)
+!11 = distinct !DILexicalBlock(line: 5, column: 1, file: !26, scope: !1)
+!12 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "c", line: 7, scope: !11, file: !2, type: !13)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!14 = !DIGlobalVariable(name: "length", linkageName: "length", line: 1, isLocal: false, isDefinition: true, scope: !2, file: !2, type: !13, variable: i32* @length)
+!15 = !DILocation(line: 4, column: 24, scope: !1)
+!16 = !DILocation(line: 4, column: 43, scope: !1)
+!17 = !DILocation(line: 9, column: 2, scope: !11)
 !18 = !{i32 0}
-!19 = !MDLocation(line: 10, column: 2, scope: !11)
-!20 = !MDLocation(line: 11, column: 2, scope: !11)
-!21 = !MDLocation(line: 12, column: 3, scope: !22)
-!22 = !{!"0xb\0011\0045\000", !26, !11} ; [ DW_TAG_lexical_block ]
-!23 = !MDLocation(line: 13, column: 3, scope: !22)
-!24 = !MDLocation(line: 14, column: 2, scope: !22)
-!25 = !MDLocation(line: 15, column: 1, scope: !11)
-!26 = !{!"t.c", !"/private/tmp"}
+!19 = !DILocation(line: 10, column: 2, scope: !11)
+!20 = !DILocation(line: 11, column: 2, scope: !11)
+!21 = !DILocation(line: 12, column: 3, scope: !22)
+!22 = distinct !DILexicalBlock(line: 11, column: 45, file: !26, scope: !11)
+!23 = !DILocation(line: 13, column: 3, scope: !22)
+!24 = !DILocation(line: 14, column: 2, scope: !22)
+!25 = !DILocation(line: 15, column: 1, scope: !11)
+!26 = !DIFile(filename: "t.c", directory: "/private/tmp")
diff --git a/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll b/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
index fcabc900afa6..03362a8e51f9 100644
--- a/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
+++ b/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
@@ -7,8 +7,8 @@ define i32 @main(i32 %argc, i8** %argv) nounwind {
 entry:
   %0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2> ; <<2 x i64>> [#uses=1]
   store <2 x i64> %0, <2 x i64>* undef, align 16
-  %val4723 = load <8 x i16>* undef                ; <<8 x i16>> [#uses=1]
-  call void @PrintShortX(i8* getelementptr inbounds ([21 x i8]* @.str271, i32 0, i32 0), <8 x i16> %val4723, i32 0) nounwind
+  %val4723 = load <8 x i16>, <8 x i16>* undef                ; <<8 x i16>> [#uses=1]
+  call void @PrintShortX(i8* getelementptr inbounds ([21 x i8], [21 x i8]* @.str271, i32 0, i32 0), <8 x i16> %val4723, i32 0) nounwind
   ret i32 undef
 }
 
diff --git a/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll b/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll
index 80822c2c426b..b02efea929fa 100644
--- a/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll
+++ b/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll
@@ -9,7 +9,7 @@ target triple = "thumbv7-apple-darwin10.0.0"
 @d = internal global i32 0, align 4               ; <i32*> [#uses=6]
 @_ZTVN10__cxxabiv117__class_type_infoE = external global i8* ; <i8**> [#uses=1]
 @_ZTS1A = internal constant [3 x i8] c"1A\00"     ; <[3 x i8]*> [#uses=1]
-@_ZTI1A = internal constant %0 { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv117__class_type_infoE, i32 2) to i8*), i8* getelementptr inbounds ([3 x i8]* @_ZTS1A, i32 0, i32 0) } ; <%0*> [#uses=1]
+@_ZTI1A = internal constant %0 { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i32 2) to i8*), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @_ZTS1A, i32 0, i32 0) } ; <%0*> [#uses=1]
 @.str2 = private constant [18 x i8] c"c == %d, d == %d\0A\00" ; <[18 x i8]*> [#uses=1]
 @.str3 = private constant [16 x i8] c"A(const A&) %d\0A\00" ; <[16 x i8]*> [#uses=1]
 @.str4 = private constant [9 x i8] c"~A() %d\0A\00" ; <[9 x i8]*> [#uses=1]
@@ -29,10 +29,10 @@ declare void @_Unwind_SjLj_Resume(i8*)
 
 define internal void @_ZN1AD1Ev(%struct.A* nocapture %this) nounwind ssp align 2 {
 entry:
-  %tmp.i = getelementptr inbounds %struct.A* %this, i32 0, i32 0 ; <i32*> [#uses=1]
-  %tmp2.i = load i32* %tmp.i                      ; <i32> [#uses=1]
-  %call.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str4, i32 0, i32 0), i32 %tmp2.i) nounwind ; <i32> [#uses=0]
-  %tmp3.i = load i32* @d                          ; <i32> [#uses=1]
+  %tmp.i = getelementptr inbounds %struct.A, %struct.A* %this, i32 0, i32 0 ; <i32*> [#uses=1]
+  %tmp2.i = load i32, i32* %tmp.i                      ; <i32> [#uses=1]
+  %call.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str4, i32 0, i32 0), i32 %tmp2.i) nounwind ; <i32> [#uses=0]
+  %tmp3.i = load i32, i32* @d                          ; <i32> [#uses=1]
   %inc.i = add nsw i32 %tmp3.i, 1                 ; <i32> [#uses=1]
   store i32 %inc.i, i32* @d
   ret void
@@ -42,11 +42,11 @@ declare void @__cxa_throw(i8*, i8*, i8*)
 
 define i32 @main() ssp {
 entry:
-  %puts.i = tail call i32 @puts(i8* getelementptr inbounds ([14 x i8]* @str, i32 0, i32 0)) ; <i32> [#uses=0]
+  %puts.i = tail call i32 @puts(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @str, i32 0, i32 0)) ; <i32> [#uses=0]
   %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind ; <i8*> [#uses=2]
   %tmp2.i.i.i = bitcast i8* %exception.i to i32*  ; <i32*> [#uses=1]
   store i32 1, i32* %tmp2.i.i.i
-  %call.i.i.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str5, i32 0, i32 0), i32 1) nounwind ; <i32> [#uses=0]
+  %call.i.i.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str5, i32 0, i32 0), i32 1) nounwind ; <i32> [#uses=0]
   invoke void @__cxa_throw(i8* %exception.i, i8* bitcast (%0* @_ZTI1A to i8*), i8* bitcast (void (%struct.A*)* @_ZN1AD1Ev to i8*)) noreturn
           to label %.noexc unwind label %lpad
 
@@ -55,17 +55,17 @@ entry:
 
 try.cont:                                         ; preds = %lpad
   %0 = tail call i8* @__cxa_get_exception_ptr(i8* %exn) nounwind ; <i8*> [#uses=0]
-  %call.i.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str3, i32 0, i32 0), i32 2) nounwind ; <i32> [#uses=0]
+  %call.i.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str3, i32 0, i32 0), i32 2) nounwind ; <i32> [#uses=0]
   %1 = tail call i8* @__cxa_begin_catch(i8* %exn) nounwind ; <i8*> [#uses=0]
-  %puts = tail call i32 @puts(i8* getelementptr inbounds ([8 x i8]* @str1, i32 0, i32 0)) ; <i32> [#uses=0]
-  %call.i.i3 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str4, i32 0, i32 0), i32 2) nounwind ; <i32> [#uses=0]
-  %tmp3.i.i = load i32* @d                        ; <i32> [#uses=1]
+  %puts = tail call i32 @puts(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @str1, i32 0, i32 0)) ; <i32> [#uses=0]
+  %call.i.i3 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str4, i32 0, i32 0), i32 2) nounwind ; <i32> [#uses=0]
+  %tmp3.i.i = load i32, i32* @d                        ; <i32> [#uses=1]
   %inc.i.i4 = add nsw i32 %tmp3.i.i, 1            ; <i32> [#uses=1]
   store i32 %inc.i.i4, i32* @d
   tail call void @__cxa_end_catch()
-  %tmp13 = load i32* @d                           ; <i32> [#uses=1]
-  %call14 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([18 x i8]* @.str2, i32 0, i32 0), i32 2, i32 %tmp13) ; <i32> [#uses=0]
-  %tmp16 = load i32* @d                           ; <i32> [#uses=1]
+  %tmp13 = load i32, i32* @d                           ; <i32> [#uses=1]
+  %call14 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str2, i32 0, i32 0), i32 2, i32 %tmp13) ; <i32> [#uses=0]
+  %tmp16 = load i32, i32* @d                           ; <i32> [#uses=1]
   %cmp = icmp ne i32 %tmp16, 2                    ; <i1> [#uses=1]
   %conv = zext i1 %cmp to i32                     ; <i32> [#uses=1]
   ret i32 %conv
diff --git a/test/CodeGen/ARM/2010-08-04-EHCrash.ll b/test/CodeGen/ARM/2010-08-04-EHCrash.ll
index 4b47085afd5e..13214c521530 100644
--- a/test/CodeGen/ARM/2010-08-04-EHCrash.ll
+++ b/test/CodeGen/ARM/2010-08-04-EHCrash.ll
@@ -12,17 +12,17 @@ entry:
   br label %return
 
 bb:                                               ; No predecessors!
-  %eh_select = load i32* %eh_selector             ; <i32> [#uses=1]
+  %eh_select = load i32, i32* %eh_selector             ; <i32> [#uses=1]
   store i32 %eh_select, i32* %save_filt.936, align 4
-  %eh_value = load i8** %eh_exception             ; <i8*> [#uses=1]
+  %eh_value = load i8*, i8** %eh_exception             ; <i8*> [#uses=1]
   store i8* %eh_value, i8** %save_eptr.935, align 4
   invoke arm_apcscc  void @func3()
           to label %invcont unwind label %lpad
 
 invcont:                                          ; preds = %bb
-  %tmp6 = load i8** %save_eptr.935, align 4          ; <i8*> [#uses=1]
+  %tmp6 = load i8*, i8** %save_eptr.935, align 4          ; <i8*> [#uses=1]
   store i8* %tmp6, i8** %eh_exception, align 4
-  %tmp7 = load i32* %save_filt.936, align 4          ; <i32> [#uses=1]
+  %tmp7 = load i32, i32* %save_filt.936, align 4          ; <i32> [#uses=1]
   store i32 %tmp7, i32* %eh_selector, align 4
   br label %Unwind
 
@@ -38,7 +38,7 @@ lpad:                                             ; preds = %bb
               cleanup
   %exn = extractvalue { i8*, i32 } %eh_ptr, 0
   store i8* %exn, i8** %eh_exception
-  %eh_ptr13 = load i8** %eh_exception             ; <i8*> [#uses=1]
+  %eh_ptr13 = load i8*, i8** %eh_exception             ; <i8*> [#uses=1]
   %eh_select14 = extractvalue { i8*, i32 } %eh_ptr, 1
   store i32 %eh_select14, i32* %eh_selector
   br label %ppad
@@ -47,7 +47,7 @@ ppad:
   br label %bb12
 
 Unwind:
-  %eh_ptr15 = load i8** %eh_exception
+  %eh_ptr15 = load i8*, i8** %eh_exception
   call arm_apcscc  void @_Unwind_SjLj_Resume(i8* %eh_ptr15)
   unreachable
 }
diff --git a/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/test/CodeGen/ARM/2010-08-04-StackVariable.ll
index f71a6c9732a6..953e2bbf291c 100644
--- a/test/CodeGen/ARM/2010-08-04-StackVariable.ll
+++ b/test/CodeGen/ARM/2010-08-04-StackVariable.ll
@@ -6,20 +6,20 @@
 define i32 @_Z3fooi4SVal(i32 %i, %struct.SVal* noalias %location) nounwind ssp {
 entry:
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !23, metadata !{!"0x102"}), !dbg !24
-  call void @llvm.dbg.value(metadata %struct.SVal* %location, i64 0, metadata !25, metadata !{!"0x102"}), !dbg !24
+  call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !23, metadata !DIExpression()), !dbg !24
+  call void @llvm.dbg.value(metadata %struct.SVal* %location, i64 0, metadata !25, metadata !DIExpression()), !dbg !24
   %0 = icmp ne i32 %i, 0, !dbg !27                ; <i1> [#uses=1]
   br i1 %0, label %bb, label %bb1, !dbg !27
 
 bb:                                               ; preds = %entry
-  %1 = getelementptr inbounds %struct.SVal* %location, i32 0, i32 1, !dbg !29 ; <i32*> [#uses=1]
-  %2 = load i32* %1, align 8, !dbg !29            ; <i32> [#uses=1]
+  %1 = getelementptr inbounds %struct.SVal, %struct.SVal* %location, i32 0, i32 1, !dbg !29 ; <i32*> [#uses=1]
+  %2 = load i32, i32* %1, align 8, !dbg !29            ; <i32> [#uses=1]
   %3 = add i32 %2, %i, !dbg !29                   ; <i32> [#uses=1]
   br label %bb2, !dbg !29
 
 bb1:                                              ; preds = %entry
-  %4 = getelementptr inbounds %struct.SVal* %location, i32 0, i32 1, !dbg !30 ; <i32*> [#uses=1]
-  %5 = load i32* %4, align 8, !dbg !30            ; <i32> [#uses=1]
+  %4 = getelementptr inbounds %struct.SVal, %struct.SVal* %location, i32 0, i32 1, !dbg !30 ; <i32*> [#uses=1]
+  %5 = load i32, i32* %4, align 8, !dbg !30            ; <i32> [#uses=1]
   %6 = sub i32 %5, 1, !dbg !30                    ; <i32> [#uses=1]
   br label %bb2, !dbg !30
 
@@ -34,10 +34,10 @@ return:                                           ; preds = %bb2
 define linkonce_odr void @_ZN4SValC1Ev(%struct.SVal* %this) nounwind ssp align 2  {
 entry:
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.value(metadata %struct.SVal* %this, i64 0, metadata !31, metadata !{!"0x102"}), !dbg !34
-  %0 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 0, !dbg !34 ; <i8**> [#uses=1]
+  call void @llvm.dbg.value(metadata %struct.SVal* %this, i64 0, metadata !31, metadata !DIExpression()), !dbg !34
+  %0 = getelementptr inbounds %struct.SVal, %struct.SVal* %this, i32 0, i32 0, !dbg !34 ; <i8**> [#uses=1]
   store i8* null, i8** %0, align 8, !dbg !34
-  %1 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 1, !dbg !34 ; <i32*> [#uses=1]
+  %1 = getelementptr inbounds %struct.SVal, %struct.SVal* %this, i32 0, i32 1, !dbg !34 ; <i32*> [#uses=1]
   store i32 0, i32* %1, align 8, !dbg !34
   br label %return, !dbg !34
 
@@ -52,20 +52,20 @@ entry:
   %0 = alloca %struct.SVal                        ; <%struct.SVal*> [#uses=3]
   %v = alloca %struct.SVal                        ; <%struct.SVal*> [#uses=4]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.declare(metadata %struct.SVal* %v, metadata !38, metadata !{!"0x102"}), !dbg !41
+  call void @llvm.dbg.declare(metadata %struct.SVal* %v, metadata !38, metadata !DIExpression()), !dbg !41
   call void @_ZN4SValC1Ev(%struct.SVal* %v) nounwind, !dbg !41
-  %1 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 1, !dbg !42 ; <i32*> [#uses=1]
+  %1 = getelementptr inbounds %struct.SVal, %struct.SVal* %v, i32 0, i32 1, !dbg !42 ; <i32*> [#uses=1]
   store i32 1, i32* %1, align 8, !dbg !42
-  %2 = getelementptr inbounds %struct.SVal* %0, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1]
-  %3 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1]
-  %4 = load i8** %3, align 8, !dbg !43            ; <i8*> [#uses=1]
+  %2 = getelementptr inbounds %struct.SVal, %struct.SVal* %0, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1]
+  %3 = getelementptr inbounds %struct.SVal, %struct.SVal* %v, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1]
+  %4 = load i8*, i8** %3, align 8, !dbg !43            ; <i8*> [#uses=1]
   store i8* %4, i8** %2, align 8, !dbg !43
-  %5 = getelementptr inbounds %struct.SVal* %0, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1]
-  %6 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1]
-  %7 = load i32* %6, align 8, !dbg !43            ; <i32> [#uses=1]
+  %5 = getelementptr inbounds %struct.SVal, %struct.SVal* %0, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1]
+  %6 = getelementptr inbounds %struct.SVal, %struct.SVal* %v, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1]
+  %7 = load i32, i32* %6, align 8, !dbg !43            ; <i32> [#uses=1]
   store i32 %7, i32* %5, align 8, !dbg !43
   %8 = call i32 @_Z3fooi4SVal(i32 2, %struct.SVal* noalias %0) nounwind, !dbg !43 ; <i32> [#uses=0]
-  call void @llvm.dbg.value(metadata i32 %8, i64 0, metadata !44, metadata !{!"0x102"}), !dbg !43
+  call void @llvm.dbg.value(metadata i32 %8, i64 0, metadata !44, metadata !DIExpression()), !dbg !43
   br label %return, !dbg !45
 
 return:                                           ; preds = %entry
@@ -77,53 +77,53 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!3}
 !llvm.module.flags = !{!49}
 
-!0 = !{!"0x2e\00SVal\00SVal\00\0011\000\000\000\006\000\000\000", !48, !1, !14, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x13\00SVal\001\00128\0064\000\000\000", !48, null, null, !4, null, null, null} ; [ DW_TAG_structure_type ] [SVal] [line 1, size 128, align 64, offset 0] [def] [from ]
-!2 = !{!"0x29", !48} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\004\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\000\00\000\00\001", !48, !47, !47, !46, !47,  !47} ; [ DW_TAG_compile_unit ]
+!0 = !DISubprogram(name: "SVal", line: 11, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !48, scope: !1, type: !14)
+!1 = !DICompositeType(tag: DW_TAG_structure_type, name: "SVal", line: 1, size: 128, align: 64, file: !48, elements: !4)
+!2 = !DIFile(filename: "small.cc", directory: "/Users/manav/R8248330")
+!3 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: false, emissionKind: 1, file: !48, enums: !47, retainedTypes: !47, subprograms: !46, globals: !47, imports:  !47)
 !4 = !{!5, !7, !0, !9}
-!5 = !{!"0xd\00Data\007\0064\0064\000\000", !48, !1, !6} ; [ DW_TAG_member ]
-!6 = !{!"0xf\00\000\0064\0064\000\000", !48, null, null} ; [ DW_TAG_pointer_type ]
-!7 = !{!"0xd\00Kind\008\0032\0032\0064\000", !48, !1, !8} ; [ DW_TAG_member ]
-!8 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", !48, null} ; [ DW_TAG_base_type ]
-!9 = !{!"0x2e\00~SVal\00~SVal\00\0012\000\000\000\006\000\000\000", !48, !1, !10, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!10 = !{!"0x15\00\000\000\000\000\000\000", !48, null, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DIDerivedType(tag: DW_TAG_member, name: "Data", line: 7, size: 64, align: 64, file: !48, scope: !1, baseType: !6)
+!6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !48, baseType: null)
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "Kind", line: 8, size: 32, align: 32, offset: 64, file: !48, scope: !1, baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!9 = !DISubprogram(name: "~SVal", line: 12, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !48, scope: !1, type: !10)
+!10 = !DISubroutineType(types: !11)
 !11 = !{null, !12, !13}
-!12 = !{!"0xf\00\000\0064\0064\000\0064", !48, null, !1} ; [ DW_TAG_pointer_type ]
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", !48, null} ; [ DW_TAG_base_type ]
-!14 = !{!"0x15\00\000\000\000\000\000\000", !48, null, null, !15, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, file: !48, baseType: !1)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!14 = !DISubroutineType(types: !15)
 !15 = !{null, !12}
-!16 = !{!"0x2e\00SVal\00SVal\00_ZN4SValC1Ev\0011\000\001\000\006\000\000\000", !48, !1, !14, null, void (%struct.SVal*)* @_ZN4SValC1Ev, null, null, null} ; [ DW_TAG_subprogram ]
-!17 = !{!"0x2e\00foo\00foo\00_Z3fooi4SVal\0016\000\001\000\006\000\000\000", !48, !2, !18, null, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal, null, null, null} ; [ DW_TAG_subprogram ]
-!18 = !{!"0x15\00\000\000\000\000\000\000", !48, null, null, !19, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!16 = !DISubprogram(name: "SVal", linkageName: "_ZN4SValC1Ev", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !48, scope: !1, type: !14, function: void (%struct.SVal*)* @_ZN4SValC1Ev)
+!17 = !DISubprogram(name: "foo", linkageName: "_Z3fooi4SVal", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !48, scope: !2, type: !18, function: i32 (i32, %struct.SVal*)* @_Z3fooi4SVal)
+!18 = !DISubroutineType(types: !19)
 !19 = !{!13, !13, !1}
-!20 = !{!"0x2e\00main\00main\00main\0023\000\001\000\006\000\000\000", !48, !2, !21, null, i32 ()* @main, null, null, null} ; [ DW_TAG_subprogram ]
-!21 = !{!"0x15\00\000\000\000\000\000\000", !48, null, null, !22, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!20 = !DISubprogram(name: "main", linkageName: "main", line: 23, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !48, scope: !2, type: !21, function: i32 ()* @main)
+!21 = !DISubroutineType(types: !22)
 !22 = !{!13}
-!23 = !{!"0x101\00i\0016\000", !17, !2, !13} ; [ DW_TAG_arg_variable ]
-!24 = !MDLocation(line: 16, scope: !17)
-!25 = !{!"0x101\00location\0016\000", !17, !2, !26} ; [ DW_TAG_arg_variable ]
-!26 = !{!"0x10\00SVal\000\0064\0064\000\000", !48, !2, !1} ; [ DW_TAG_reference_type ]
-!27 = !MDLocation(line: 17, scope: !28)
-!28 = !{!"0xb\0016\000\002", !2, !17} ; [ DW_TAG_lexical_block ]
-!29 = !MDLocation(line: 18, scope: !28)
-!30 = !MDLocation(line: 20, scope: !28)
-!31 = !{!"0x101\00this\0011\000", !16, !2, !32} ; [ DW_TAG_arg_variable ]
-!32 = !{!"0x26\00\000\0064\0064\000\0064", !48, !2, !33} ; [ DW_TAG_const_type ]
-!33 = !{!"0xf\00\000\0064\0064\000\000", !48, !2, !1} ; [ DW_TAG_pointer_type ]
-!34 = !MDLocation(line: 11, scope: !16)
-!35 = !MDLocation(line: 11, scope: !36)
-!36 = !{!"0xb\0011\000\001", !48, !37} ; [ DW_TAG_lexical_block ]
-!37 = !{!"0xb\0011\000\000", !48, !16} ; [ DW_TAG_lexical_block ]
-!38 = !{!"0x100\00v\0024\000", !39, !2, !1} ; [ DW_TAG_auto_variable ]
-!39 = !{!"0xb\0023\000\004", !48, !40} ; [ DW_TAG_lexical_block ]
-!40 = !{!"0xb\0023\000\003", !48, !20} ; [ DW_TAG_lexical_block ]
-!41 = !MDLocation(line: 24, scope: !39)
-!42 = !MDLocation(line: 25, scope: !39)
-!43 = !MDLocation(line: 26, scope: !39)
-!44 = !{!"0x100\00k\0026\000", !39, !2, !13} ; [ DW_TAG_auto_variable ]
-!45 = !MDLocation(line: 27, scope: !39)
+!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 16, arg: 0, scope: !17, file: !2, type: !13)
+!24 = !DILocation(line: 16, scope: !17)
+!25 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "location", line: 16, arg: 0, scope: !17, file: !2, type: !26)
+!26 = !DIDerivedType(tag: DW_TAG_reference_type, name: "SVal", size: 64, align: 64, file: !48, scope: !2, baseType: !1)
+!27 = !DILocation(line: 17, scope: !28)
+!28 = distinct !DILexicalBlock(line: 16, column: 0, file: !2, scope: !17)
+!29 = !DILocation(line: 18, scope: !28)
+!30 = !DILocation(line: 20, scope: !28)
+!31 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 11, arg: 0, scope: !16, file: !2, type: !32)
+!32 = !DIDerivedType(tag: DW_TAG_const_type, size: 64, align: 64, flags: DIFlagArtificial, file: !48, scope: !2, baseType: !33)
+!33 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !48, scope: !2, baseType: !1)
+!34 = !DILocation(line: 11, scope: !16)
+!35 = !DILocation(line: 11, scope: !36)
+!36 = distinct !DILexicalBlock(line: 11, column: 0, file: !48, scope: !37)
+!37 = distinct !DILexicalBlock(line: 11, column: 0, file: !48, scope: !16)
+!38 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "v", line: 24, scope: !39, file: !2, type: !1)
+!39 = distinct !DILexicalBlock(line: 23, column: 0, file: !48, scope: !40)
+!40 = distinct !DILexicalBlock(line: 23, column: 0, file: !48, scope: !20)
+!41 = !DILocation(line: 24, scope: !39)
+!42 = !DILocation(line: 25, scope: !39)
+!43 = !DILocation(line: 26, scope: !39)
+!44 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 26, scope: !39, file: !2, type: !13)
+!45 = !DILocation(line: 27, scope: !39)
 !46 = !{!16, !17, !20}
 !47 = !{}
-!48 = !{!"small.cc", !"/Users/manav/R8248330"}
-!49 = !{i32 1, !"Debug Info Version", i32 2}
+!48 = !DIFile(filename: "small.cc", directory: "/Users/manav/R8248330")
+!49 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll b/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll
index 80a19649635a..09428ce9c339 100644
--- a/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll
+++ b/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll
@@ -34,34 +34,34 @@ bb28.i:                                           ; preds = %bb28.i, %bb27.i
 
 presymmetry.exit:                                 ; preds = %bb28.i
   %tmp175387 = or i32 undef, 12
-  %scevgep101.i = getelementptr i32* %in, i32 undef
+  %scevgep101.i = getelementptr i32, i32* %in, i32 undef
   %tmp189401 = or i32 undef, 7
-  %scevgep97.i = getelementptr i32* %in, i32 undef
+  %scevgep97.i = getelementptr i32, i32* %in, i32 undef
   %tmp198410 = or i32 undef, 1
-  %scevgep.i48 = getelementptr i32* %in, i32 undef
-  %0 = load i32* %scevgep.i48, align 4
+  %scevgep.i48 = getelementptr i32, i32* %in, i32 undef
+  %0 = load i32, i32* %scevgep.i48, align 4
   %1 = add nsw i32 %0, 0
   store i32 %1, i32* undef, align 4
   %asmtmp.i.i33.i.i.i = tail call %0 asm "smull\09$0, $1, $2, $3", "=&r,=&r,%r,r,~{cc}"(i32 undef, i32 1518500250) nounwind
   %asmresult1.i.i34.i.i.i = extractvalue %0 %asmtmp.i.i33.i.i.i, 1
   %2 = shl i32 %asmresult1.i.i34.i.i.i, 1
-  %3 = load i32* null, align 4
-  %4 = load i32* undef, align 4
+  %3 = load i32, i32* null, align 4
+  %4 = load i32, i32* undef, align 4
   %5 = sub nsw i32 %3, %4
-  %6 = load i32* undef, align 4
-  %7 = load i32* null, align 4
+  %6 = load i32, i32* undef, align 4
+  %7 = load i32, i32* null, align 4
   %8 = sub nsw i32 %6, %7
-  %9 = load i32* %scevgep97.i, align 4
-  %10 = load i32* undef, align 4
+  %9 = load i32, i32* %scevgep97.i, align 4
+  %10 = load i32, i32* undef, align 4
   %11 = sub nsw i32 %9, %10
-  %12 = load i32* null, align 4
-  %13 = load i32* %scevgep101.i, align 4
+  %12 = load i32, i32* null, align 4
+  %13 = load i32, i32* %scevgep101.i, align 4
   %14 = sub nsw i32 %12, %13
-  %15 = load i32* %scevgep.i48, align 4
-  %16 = load i32* null, align 4
+  %15 = load i32, i32* %scevgep.i48, align 4
+  %16 = load i32, i32* null, align 4
   %17 = add nsw i32 %16, %15
   %18 = sub nsw i32 %15, %16
-  %19 = load i32* undef, align 4
+  %19 = load i32, i32* undef, align 4
   %20 = add nsw i32 %19, %2
   %21 = sub nsw i32 %19, %2
   %22 = add nsw i32 %14, %5
diff --git a/test/CodeGen/ARM/2010-12-08-tpsoft.ll b/test/CodeGen/ARM/2010-12-08-tpsoft.ll
index 1351a26756ef..9dfe4da27677 100644
--- a/test/CodeGen/ARM/2010-12-08-tpsoft.ll
+++ b/test/CodeGen/ARM/2010-12-08-tpsoft.ll
@@ -12,7 +12,7 @@
 
 define arm_aapcs_vfpcc i32 @main() nounwind {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   switch i32 %0, label %bb2 [
     i32 12, label %bb
     i32 13, label %bb1
diff --git a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll
index f13bc1214a5a..f04e053b2e04 100644
--- a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll
+++ b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll
@@ -12,14 +12,9 @@
 ; ASM:          .type   array00,%object         @ @array00
 ; ASM-NEXT:     .local  array00
 ; ASM-NEXT:     .comm   array00,80,1
-; ASM-NEXT:     .type   _MergedGlobals,%object  @ @_MergedGlobals
+; ASM-NEXT:     .type   sum,%object  @ @sum
 
 
-; OBJ:      Sections [
-; OBJ:        Section {
-; OBJ:          Index: 4
-; OBJ-NEXT:     Name: .bss
-
 ; OBJ:      Symbols [
 ; OBJ:        Symbol {
 ; OBJ:          Name: array00
@@ -31,9 +26,9 @@
 ; OBJ-NEXT:     Section: .bss
 
 define i32 @main(i32 %argc) nounwind {
-  %1 = load i32* @sum, align 4
-  %2 = getelementptr [80 x i8]* @array00, i32 0, i32 %argc
-  %3 = load i8* %2
+  %1 = load i32, i32* @sum, align 4
+  %2 = getelementptr [80 x i8], [80 x i8]* @array00, i32 0, i32 %argc
+  %3 = load i8, i8* %2
   %4 = zext i8 %3 to i32
   %5 = add i32 %1, %4
   ret i32 %5
diff --git a/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll b/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll
index a2f50b587b22..783c82eb88b7 100644
--- a/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll
+++ b/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll
@@ -9,7 +9,7 @@ entry:
   br label %bb
 
 bb:
-  %p.2 = getelementptr [8096 x i8]* %buf, i32 0, i32 0
+  %p.2 = getelementptr [8096 x i8], [8096 x i8]* %buf, i32 0, i32 0
   store i8 undef, i8* %p.2, align 1
   ret void
 }
diff --git a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll
index 67dda672719c..9a5baf21b8fb 100644
--- a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll
+++ b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -filetype=obj < %s | llvm-dwarfdump -debug-dump=info - | FileCheck %s
+; RUN: llc -arm-global-merge -global-merge-group-by-use=false -filetype=obj < %s | llvm-dwarfdump -debug-dump=info - | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32"
 target triple = "thumbv7-apple-darwin10"
@@ -30,9 +30,9 @@ target triple = "thumbv7-apple-darwin10"
 
 define zeroext i8 @get1(i8 zeroext %a) nounwind optsize {
 entry:
-  tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !30
-  %0 = load i8* @x1, align 4, !dbg !30
-  tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !30
+  tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !10, metadata !DIExpression()), !dbg !30
+  %0 = load i8, i8* @x1, align 4, !dbg !30
+  tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !11, metadata !DIExpression()), !dbg !30
   store i8 %a, i8* @x1, align 4, !dbg !30
   ret i8 %0, !dbg !31
 }
@@ -41,36 +41,36 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 
 define zeroext i8 @get2(i8 zeroext %a) nounwind optsize {
 entry:
-  tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !32
-  %0 = load i8* @x2, align 4, !dbg !32
-  tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !32
+  tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !18, metadata !DIExpression()), !dbg !32
+  %0 = load i8, i8* @x2, align 4, !dbg !32
+  tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !19, metadata !DIExpression()), !dbg !32
   store i8 %a, i8* @x2, align 4, !dbg !32
   ret i8 %0, !dbg !33
 }
 
 define zeroext i8 @get3(i8 zeroext %a) nounwind optsize {
 entry:
-  tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !21, metadata !{!"0x102"}), !dbg !34
-  %0 = load i8* @x3, align 4, !dbg !34
-  tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !22, metadata !{!"0x102"}), !dbg !34
+  tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !21, metadata !DIExpression()), !dbg !34
+  %0 = load i8, i8* @x3, align 4, !dbg !34
+  tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !22, metadata !DIExpression()), !dbg !34
   store i8 %a, i8* @x3, align 4, !dbg !34
   ret i8 %0, !dbg !35
 }
 
 define zeroext i8 @get4(i8 zeroext %a) nounwind optsize {
 entry:
-  tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !24, metadata !{!"0x102"}), !dbg !36
-  %0 = load i8* @x4, align 4, !dbg !36
-  tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !25, metadata !{!"0x102"}), !dbg !36
+  tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !24, metadata !DIExpression()), !dbg !36
+  %0 = load i8, i8* @x4, align 4, !dbg !36
+  tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !25, metadata !DIExpression()), !dbg !36
   store i8 %a, i8* @x4, align 4, !dbg !36
   ret i8 %0, !dbg !37
 }
 
 define zeroext i8 @get5(i8 zeroext %a) nounwind optsize {
 entry:
-  tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !38
-  %0 = load i8* @x5, align 4, !dbg !38
-  tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !28, metadata !{!"0x102"}), !dbg !38
+  tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !27, metadata !DIExpression()), !dbg !38
+  %0 = load i8, i8* @x5, align 4, !dbg !38
+  tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !28, metadata !DIExpression()), !dbg !38
   store i8 %a, i8* @x5, align 4, !dbg !38
   ret i8 %0, !dbg !39
 }
@@ -78,46 +78,46 @@ entry:
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!49}
 
-!0 = !{!"0x2e\00get1\00get1\00get1\004\000\001\000\006\00256\001\004", !47, !1, !3, null, i8 (i8)* @get1, null, null, !42} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !47} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)\001\00\000\00\000", !47, !48, !48, !40, !41,  !48} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !47, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "get1", linkageName: "get1", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 4, file: !47, scope: !1, type: !3, function: i8 (i8)* @get1, variables: !42)
+!1 = !DIFile(filename: "foo.c", directory: "/tmp/")
+!2 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", isOptimized: true, emissionKind: 0, file: !47, enums: !48, retainedTypes: !48, subprograms: !40, globals: !41, imports:  !48)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5, !5}
-!5 = !{!"0x24\00_Bool\000\008\008\000\000\002", !47, !1} ; [ DW_TAG_base_type ]
-!6 = !{!"0x2e\00get2\00get2\00get2\007\000\001\000\006\00256\001\007", !47, !1, !3, null, i8 (i8)* @get2, null, null, !43} ; [ DW_TAG_subprogram ]
-!7 = !{!"0x2e\00get3\00get3\00get3\0010\000\001\000\006\00256\001\0010", !47, !1, !3, null, i8 (i8)* @get3, null, null, !44} ; [ DW_TAG_subprogram ]
-!8 = !{!"0x2e\00get4\00get4\00get4\0013\000\001\000\006\00256\001\0013", !47, !1, !3, null, i8 (i8)* @get4, null, null, !45} ; [ DW_TAG_subprogram ]
-!9 = !{!"0x2e\00get5\00get5\00get5\0016\000\001\000\006\00256\001\0016", !47, !1, !3, null, i8 (i8)* @get5, null, null, !46} ; [ DW_TAG_subprogram ]
-!10 = !{!"0x101\00a\004\000", !0, !1, !5} ; [ DW_TAG_arg_variable ]
-!11 = !{!"0x100\00b\004\000", !12, !1, !5} ; [ DW_TAG_auto_variable ]
-!12 = !{!"0xb\004\000\000", !47, !0} ; [ DW_TAG_lexical_block ]
-!13 = !{!"0x34\00x1\00x1\00\003\001\001", !1, !1, !5, i8* @x1, null} ; [ DW_TAG_variable ]
-!14 = !{!"0x34\00x2\00x2\00\006\001\001", !1, !1, !5, i8* @x2, null} ; [ DW_TAG_variable ]
-!15 = !{!"0x34\00x3\00x3\00\009\001\001", !1, !1, !5, i8* @x3, null} ; [ DW_TAG_variable ]
-!16 = !{!"0x34\00x4\00x4\00\0012\001\001", !1, !1, !5, i8* @x4, null} ; [ DW_TAG_variable ]
-!17 = !{!"0x34\00x5\00x5\00\0015\000\001", !1, !1, !5, i8* @x5, null} ; [ DW_TAG_variable ]
-!18 = !{!"0x101\00a\007\000", !6, !1, !5} ; [ DW_TAG_arg_variable ]
-!19 = !{!"0x100\00b\007\000", !20, !1, !5} ; [ DW_TAG_auto_variable ]
-!20 = !{!"0xb\007\000\001", !47, !6} ; [ DW_TAG_lexical_block ]
-!21 = !{!"0x101\00a\0010\000", !7, !1, !5} ; [ DW_TAG_arg_variable ]
-!22 = !{!"0x100\00b\0010\000", !23, !1, !5} ; [ DW_TAG_auto_variable ]
-!23 = !{!"0xb\0010\000\002", !47, !7} ; [ DW_TAG_lexical_block ]
-!24 = !{!"0x101\00a\0013\000", !8, !1, !5} ; [ DW_TAG_arg_variable ]
-!25 = !{!"0x100\00b\0013\000", !26, !1, !5} ; [ DW_TAG_auto_variable ]
-!26 = !{!"0xb\0013\000\003", !47, !8} ; [ DW_TAG_lexical_block ]
-!27 = !{!"0x101\00a\0016\000", !9, !1, !5} ; [ DW_TAG_arg_variable ]
-!28 = !{!"0x100\00b\0016\000", !29, !1, !5} ; [ DW_TAG_auto_variable ]
-!29 = !{!"0xb\0016\000\004", !47, !9} ; [ DW_TAG_lexical_block ]
-!30 = !MDLocation(line: 4, scope: !0)
-!31 = !MDLocation(line: 4, scope: !12)
-!32 = !MDLocation(line: 7, scope: !6)
-!33 = !MDLocation(line: 7, scope: !20)
-!34 = !MDLocation(line: 10, scope: !7)
-!35 = !MDLocation(line: 10, scope: !23)
-!36 = !MDLocation(line: 13, scope: !8)
-!37 = !MDLocation(line: 13, scope: !26)
-!38 = !MDLocation(line: 16, scope: !9)
-!39 = !MDLocation(line: 16, scope: !29)
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "_Bool", size: 8, align: 8, encoding: DW_ATE_boolean)
+!6 = !DISubprogram(name: "get2", linkageName: "get2", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 7, file: !47, scope: !1, type: !3, function: i8 (i8)* @get2, variables: !43)
+!7 = !DISubprogram(name: "get3", linkageName: "get3", line: 10, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 10, file: !47, scope: !1, type: !3, function: i8 (i8)* @get3, variables: !44)
+!8 = !DISubprogram(name: "get4", linkageName: "get4", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 13, file: !47, scope: !1, type: !3, function: i8 (i8)* @get4, variables: !45)
+!9 = !DISubprogram(name: "get5", linkageName: "get5", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 16, file: !47, scope: !1, type: !3, function: i8 (i8)* @get5, variables: !46)
+!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 4, arg: 0, scope: !0, file: !1, type: !5)
+!11 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 4, scope: !12, file: !1, type: !5)
+!12 = distinct !DILexicalBlock(line: 4, column: 0, file: !47, scope: !0)
+!13 = !DIGlobalVariable(name: "x1", line: 3, isLocal: true, isDefinition: true, scope: !1, file: !1, type: !5, variable: i8* @x1)
+!14 = !DIGlobalVariable(name: "x2", line: 6, isLocal: true, isDefinition: true, scope: !1, file: !1, type: !5, variable: i8* @x2)
+!15 = !DIGlobalVariable(name: "x3", line: 9, isLocal: true, isDefinition: true, scope: !1, file: !1, type: !5, variable: i8* @x3)
+!16 = !DIGlobalVariable(name: "x4", line: 12, isLocal: true, isDefinition: true, scope: !1, file: !1, type: !5, variable: i8* @x4)
+!17 = !DIGlobalVariable(name: "x5", line: 15, isLocal: false, isDefinition: true, scope: !1, file: !1, type: !5, variable: i8* @x5)
+!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 7, arg: 0, scope: !6, file: !1, type: !5)
+!19 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 7, scope: !20, file: !1, type: !5)
+!20 = distinct !DILexicalBlock(line: 7, column: 0, file: !47, scope: !6)
+!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 10, arg: 0, scope: !7, file: !1, type: !5)
+!22 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 10, scope: !23, file: !1, type: !5)
+!23 = distinct !DILexicalBlock(line: 10, column: 0, file: !47, scope: !7)
+!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 13, arg: 0, scope: !8, file: !1, type: !5)
+!25 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 13, scope: !26, file: !1, type: !5)
+!26 = distinct !DILexicalBlock(line: 13, column: 0, file: !47, scope: !8)
+!27 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 16, arg: 0, scope: !9, file: !1, type: !5)
+!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 16, scope: !29, file: !1, type: !5)
+!29 = distinct !DILexicalBlock(line: 16, column: 0, file: !47, scope: !9)
+!30 = !DILocation(line: 4, scope: !0)
+!31 = !DILocation(line: 4, scope: !12)
+!32 = !DILocation(line: 7, scope: !6)
+!33 = !DILocation(line: 7, scope: !20)
+!34 = !DILocation(line: 10, scope: !7)
+!35 = !DILocation(line: 10, scope: !23)
+!36 = !DILocation(line: 13, scope: !8)
+!37 = !DILocation(line: 13, scope: !26)
+!38 = !DILocation(line: 16, scope: !9)
+!39 = !DILocation(line: 16, scope: !29)
 !40 = !{!0, !6, !7, !8, !9}
 !41 = !{!13, !14, !15, !16, !17}
 !42 = !{!10, !11}
@@ -125,6 +125,6 @@ entry:
 !44 = !{!21, !22}
 !45 = !{!24, !25}
 !46 = !{!27, !28}
-!47 = !{!"foo.c", !"/tmp/"}
+!47 = !DIFile(filename: "foo.c", directory: "/tmp/")
 !48 = !{}
-!49 = !{i32 1, !"Debug Info Version", i32 2}
+!49 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll b/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll
index 3950c9e081f7..8403dd991360 100644
--- a/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll
+++ b/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll
@@ -19,7 +19,7 @@ bb3:                                              ; preds = %bb, %entry
   br i1 %tst, label %bb46, label %bb8
 
 bb8:                                              ; preds = %bb3
-  %1 = getelementptr inbounds i8* %0, i32 0
+  %1 = getelementptr inbounds i8, i8* %0, i32 0
   store i8 0, i8* %1, align 1
   %2 = call i32 @ptou() nounwind
   ; CHECK: umull [[REGISTER:lr|r[0-9]+]],
diff --git a/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll b/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll
index f3d788818afc..e96641bf6671 100644
--- a/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll
+++ b/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll
@@ -39,12 +39,12 @@ bb134:                                            ; preds = %bb131
   unreachable
 
 bb135:                                            ; preds = %meshBB396
-  %uriHash.1.phi.load = load i32* undef
-  %.load120 = load i8*** %.SV116
-  %.phi24 = load i8* null
-  %.phi26 = load i8** null
+  %uriHash.1.phi.load = load i32, i32* undef
+  %.load120 = load i8**, i8*** %.SV116
+  %.phi24 = load i8, i8* null
+  %.phi26 = load i8*, i8** null
   store i8 %.phi24, i8* %.phi26, align 1
-  %0 = getelementptr inbounds i8* %.phi26, i32 1
+  %0 = getelementptr inbounds i8, i8* %.phi26, i32 1
   store i8* %0, i8** %.load120, align 4
   ; CHECK: mul [[REGISTER:lr|r[0-9]+]],
   ; CHECK-NOT: [[REGISTER]],
@@ -52,7 +52,7 @@ bb135:                                            ; preds = %meshBB396
   %1 = mul i32 %uriHash.1.phi.load, 1000003
   %2 = xor i32 0, %1
   store i32 %2, i32* null
-  %3 = load i8* null, align 1
+  %3 = load i8, i8* null, align 1
   %4 = icmp eq i8 %3, 0
   store i8* %0, i8** undef
   br i1 %4, label %meshBB472, label %bb131
diff --git a/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll b/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll
index 81babe0b4b19..c447a1f25b65 100644
--- a/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll
+++ b/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll
@@ -17,10 +17,10 @@ bb:                                               ; preds = %entry
 bb1:                                              ; preds = %entry
   %0 = call %struct.ui* @vn_pp_to_ui(i32* undef) nounwind
   call void @llvm.memset.p0i8.i32(i8* undef, i8 0, i32 40, i32 4, i1 false)
-  %1 = getelementptr inbounds %struct.ui* %0, i32 0, i32 0
+  %1 = getelementptr inbounds %struct.ui, %struct.ui* %0, i32 0, i32 0
   store %struct.mo* undef, %struct.mo** %1, align 4
-  %2 = getelementptr inbounds %struct.ui* %0, i32 0, i32 5
-  %3 = load i64* %2, align 4
+  %2 = getelementptr inbounds %struct.ui, %struct.ui* %0, i32 0, i32 5
+  %3 = load i64, i64* %2, align 4
   %4 = call i32 @mo_create_nnm(%struct.mo* undef, i64 %3, i32** undef) nounwind
   br i1 undef, label %bb3, label %bb2
 
diff --git a/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
index 837feb6e85c2..92bdd19a7b3d 100644
--- a/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
+++ b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
@@ -18,11 +18,11 @@ for.body.lr.ph:
 for.body:                                         ; preds = %_Z14printIsNotZeroi.exit17.for.body_crit_edge, %for.body.lr.ph
   %tmp3 = phi i1 [ false, %for.body.lr.ph ], [ %phitmp27, %_Z14printIsNotZeroi.exit17.for.body_crit_edge ]
   %i.022 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %_Z14printIsNotZeroi.exit17.for.body_crit_edge ]
-  %x = getelementptr %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 0
-  %y = getelementptr %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 1
+  %x = getelementptr %struct.Outer, %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 0
+  %y = getelementptr %struct.Outer, %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 1
   %inc = add i32 %i.022, 1
-  %tmp8 = load i32* %x, align 4
-  %tmp11 = load i32* %y, align 4
+  %tmp8 = load i32, i32* %x, align 4
+  %tmp11 = load i32, i32* %y, align 4
   %mul = mul nsw i32 %tmp11, %tmp8
   %tobool.i14 = icmp eq i32 %mul, 0
   br i1 %tobool.i14, label %_Z14printIsNotZeroi.exit17, label %if.then.i16
@@ -34,8 +34,8 @@ _Z14printIsNotZeroi.exit17:                       ; preds = %_Z14printIsNotZeroi
   br label %_Z14printIsNotZeroi.exit17.for.body_crit_edge
 
 _Z14printIsNotZeroi.exit17.for.body_crit_edge:    ; preds = %_Z14printIsNotZeroi.exit17
-  %b.phi.trans.insert = getelementptr %struct.Outer* @oStruct, i32 0, i32 1, i32 %inc, i32 3
-  %tmp3.pre = load i8* %b.phi.trans.insert, align 1
+  %b.phi.trans.insert = getelementptr %struct.Outer, %struct.Outer* @oStruct, i32 0, i32 1, i32 %inc, i32 3
+  %tmp3.pre = load i8, i8* %b.phi.trans.insert, align 1
   %phitmp27 = icmp eq i8 %val8, 0
   br label %for.body
 
diff --git a/test/CodeGen/ARM/2011-04-07-schediv.ll b/test/CodeGen/ARM/2011-04-07-schediv.ll
index f3dd3dd5811e..7f603157c5d3 100644
--- a/test/CodeGen/ARM/2011-04-07-schediv.ll
+++ b/test/CodeGen/ARM/2011-04-07-schediv.ll
@@ -18,10 +18,10 @@ entry:
 bb:                                               ; preds = %entry, %bb
   %j.05 = phi i32 [ %2, %bb ], [ 0, %entry ]
   %tmp = mul i32 %j.05, %src_copy_start_index
-  %uglygep = getelementptr i8* %src_copy_start6, i32 %tmp
+  %uglygep = getelementptr i8, i8* %src_copy_start6, i32 %tmp
   %src_copy_start_addr.04 = bitcast i8* %uglygep to float*
-  %dst_copy_start_addr.03 = getelementptr float* %dst_copy_start, i32 %j.05
-  %1 = load float* %src_copy_start_addr.04, align 4
+  %dst_copy_start_addr.03 = getelementptr float, float* %dst_copy_start, i32 %j.05
+  %1 = load float, float* %src_copy_start_addr.04, align 4
   store float %1, float* %dst_copy_start_addr.03, align 4
   %2 = add i32 %j.05, 1
   %exitcond = icmp eq i32 %2, %src_width
diff --git a/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll
index e30c9c615053..54fc9b049b8e 100644
--- a/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll
+++ b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll
@@ -18,8 +18,8 @@ for.body:
 ; CHECK: mov{{.*}} r{{[0-9]+}}, #{{[01]}}
 ; CHECK: mov{{.*}} r{{[0-9]+}}, #{{[01]}}
 ; CHECK-NOT: mov r{{[0-9]+}}, #{{[01]}}
-  %arrayidx = getelementptr i32* %A, i32 %0
-  %tmp4 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr i32, i32* %A, i32 %0
+  %tmp4 = load i32, i32* %arrayidx, align 4
   %cmp6 = icmp eq i32 %tmp4, %value
   br i1 %cmp6, label %return, label %for.inc
 
diff --git a/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll b/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll
index e9a6793a768a..8ad654fc8f9d 100644
--- a/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll
+++ b/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll
@@ -7,7 +7,7 @@ target triple = "thumbv7-apple-darwin10.0.0"
 define void @_Z8TestCasev() nounwind ssp {
 entry:
   %a = alloca float, align 4
-  %tmp = load float* %a, align 4
+  %tmp = load float, float* %a, align 4
   call void asm sideeffect "", "w,~{s0},~{s16}"(float %tmp) nounwind, !srcloc !0
   ret void
 }
diff --git a/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll b/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll
index e712e08ddb6a..f17884e0fa41 100644
--- a/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll
+++ b/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll
@@ -12,7 +12,7 @@ entry:
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  tail call void (...)* @g(i32 %a, i32 %b) nounwind
+  tail call void (...) @g(i32 %a, i32 %b) nounwind
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
diff --git a/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll
index 5404cf57a59f..864e2917b7bb 100644
--- a/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll
+++ b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll
@@ -12,7 +12,7 @@ entry:
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  tail call void (...)* @h(i32 %a, i32 %b) nounwind
+  tail call void (...) @h(i32 %a, i32 %b) nounwind
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
@@ -31,7 +31,7 @@ entry:
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  tail call void (...)* @h(i32 %a, i32 %b) nounwind
+  tail call void (...) @h(i32 %a, i32 %b) nounwind
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
diff --git a/test/CodeGen/ARM/2011-04-26-SchedTweak.ll b/test/CodeGen/ARM/2011-04-26-SchedTweak.ll
index 057c19948c35..ee6d79c39f2f 100644
--- a/test/CodeGen/ARM/2011-04-26-SchedTweak.ll
+++ b/test/CodeGen/ARM/2011-04-26-SchedTweak.ll
@@ -22,7 +22,7 @@ entry:
   %block_count = alloca i32, align 4
   %index_cache = alloca i32, align 4
   store i32 0, i32* %index_cache, align 4
-  %tmp = load i32* @G, align 4
+  %tmp = load i32, i32* @G, align 4
   %tmp1 = call i32 @bar(i32 0, i32 0, i32 %tmp) nounwind
   switch i32 %tmp1, label %bb8 [
     i32 0, label %bb
@@ -31,7 +31,7 @@ entry:
   ]
 
 bb:
-  %tmp2 = load i32* @G, align 4
+  %tmp2 = load i32, i32* @G, align 4
   %tmp4 = icmp eq i32 %tmp2, 0
   br i1 %tmp4, label %bb1, label %bb8
 
@@ -41,14 +41,14 @@ bb1:
 ; CHECK: blx _Get
 ; CHECK: umull
 ; CHECK: blx _foo
-  %tmp5 = load i32* %block_size, align 4
-  %tmp6 = load i32* %block_count, align 4
+  %tmp5 = load i32, i32* %block_size, align 4
+  %tmp6 = load i32, i32* %block_count, align 4
   %tmp7 = call %struct.FF* @Get() nounwind
   store %struct.FF* %tmp7, %struct.FF** @FuncPtr, align 4
   %tmp10 = zext i32 %tmp6 to i64
   %tmp11 = zext i32 %tmp5 to i64
   %tmp12 = mul nsw i64 %tmp10, %tmp11
-  %tmp13 = call i32 @foo(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0), i64 %tmp12, i32 %tmp5) nounwind
+  %tmp13 = call i32 @foo(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), i64 %tmp12, i32 %tmp5) nounwind
   br label %bb8
 
 bb4:
diff --git a/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll b/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll
index 091d037356de..aac8f7b3a026 100644
--- a/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll
+++ b/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -arm-global-merge -global-merge-group-by-use=false | FileCheck %s
 ; CHECK: .zerofill __DATA,__bss,__MergedGlobals,16,2
 
 @prev = external global [0 x i16]
diff --git a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll
index 3edc946825bb..067c719f491c 100644
--- a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll
+++ b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -filetype=obj < %s | llvm-dwarfdump -debug-dump=info - | FileCheck %s
+; RUN: llc -arm-global-merge -global-merge-group-by-use=false -filetype=obj < %s | llvm-dwarfdump -debug-dump=info - | FileCheck %s
 
 ; Check debug info output for merged global.
 ; DW_AT_location
@@ -29,41 +29,41 @@ target triple = "thumbv7-apple-macosx10.7.0"
 @x5 = global i32 0, align 4
 
 define i32 @get1(i32 %a) nounwind optsize ssp {
-  tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !30
-  %1 = load i32* @x1, align 4, !dbg !31
-  tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !31
+  tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !10, metadata !DIExpression()), !dbg !30
+  %1 = load i32, i32* @x1, align 4, !dbg !31
+  tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !11, metadata !DIExpression()), !dbg !31
   store i32 %a, i32* @x1, align 4, !dbg !31
   ret i32 %1, !dbg !31
 }
 
 define i32 @get2(i32 %a) nounwind optsize ssp {
-  tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !32
-  %1 = load i32* @x2, align 4, !dbg !33
-  tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !33
+  tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !13, metadata !DIExpression()), !dbg !32
+  %1 = load i32, i32* @x2, align 4, !dbg !33
+  tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !14, metadata !DIExpression()), !dbg !33
   store i32 %a, i32* @x2, align 4, !dbg !33
   ret i32 %1, !dbg !33
 }
 
 define i32 @get3(i32 %a) nounwind optsize ssp {
-  tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !34
-  %1 = load i32* @x3, align 4, !dbg !35
-  tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !35
+  tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !16, metadata !DIExpression()), !dbg !34
+  %1 = load i32, i32* @x3, align 4, !dbg !35
+  tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !17, metadata !DIExpression()), !dbg !35
   store i32 %a, i32* @x3, align 4, !dbg !35
   ret i32 %1, !dbg !35
 }
 
 define i32 @get4(i32 %a) nounwind optsize ssp {
-  tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !36
-  %1 = load i32* @x4, align 4, !dbg !37
-  tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !20, metadata !{!"0x102"}), !dbg !37
+  tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !19, metadata !DIExpression()), !dbg !36
+  %1 = load i32, i32* @x4, align 4, !dbg !37
+  tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !20, metadata !DIExpression()), !dbg !37
   store i32 %a, i32* @x4, align 4, !dbg !37
   ret i32 %1, !dbg !37
 }
 
 define i32 @get5(i32 %a) nounwind optsize ssp {
-  tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !38
-  %1 = load i32* @x5, align 4, !dbg !39
-  tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !28, metadata !{!"0x102"}), !dbg !39
+  tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !27, metadata !DIExpression()), !dbg !38
+  %1 = load i32, i32* @x5, align 4, !dbg !39
+  tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !28, metadata !DIExpression()), !dbg !39
   store i32 %a, i32* @x5, align 4, !dbg !39
   ret i32 %1, !dbg !39
 }
@@ -73,43 +73,43 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!49}
 
-!0 = !{!"0x11\0012\00clang\001\00\000\00\001", !47, !48, !48, !40, !41,  !48} ; [ DW_TAG_compile_unit ]
-!1 = !{!"0x2e\00get1\00get1\00\005\000\001\000\006\00256\001\005", !47, !2, !3, null, i32 (i32)* @get1, null, null, !42} ; [ DW_TAG_subprogram ] [line 5] [def] [get1]
-!2 = !{!"0x29", !47} ; [ DW_TAG_file_type ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !47, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang", isOptimized: true, emissionKind: 1, file: !47, enums: !48, retainedTypes: !48, subprograms: !40, globals: !41, imports:  !48)
+!1 = !DISubprogram(name: "get1", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !47, scope: !2, type: !3, function: i32 (i32)* @get1, variables: !42)
+!2 = !DIFile(filename: "ss3.c", directory: "/private/tmp")
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ]
-!6 = !{!"0x2e\00get2\00get2\00\008\000\001\000\006\00256\001\008", !47, !2, !3, null, i32 (i32)* @get2, null, null, !43} ; [ DW_TAG_subprogram ] [line 8] [def] [get2]
-!7 = !{!"0x2e\00get3\00get3\00\0011\000\001\000\006\00256\001\0011", !47, !2, !3, null, i32 (i32)* @get3, null, null, !44} ; [ DW_TAG_subprogram ] [line 11] [def] [get3]
-!8 = !{!"0x2e\00get4\00get4\00\0014\000\001\000\006\00256\001\0014", !47, !2, !3, null, i32 (i32)* @get4, null, null, !45} ; [ DW_TAG_subprogram ] [line 14] [def] [get4]
-!9 = !{!"0x2e\00get5\00get5\00\0017\000\001\000\006\00256\001\0017", !47, !2, !3, null, i32 (i32)* @get5, null, null, !46} ; [ DW_TAG_subprogram ] [line 17] [def] [get5]
-!10 = !{!"0x101\00a\0016777221\000", !1, !2, !5} ; [ DW_TAG_arg_variable ]
-!11 = !{!"0x100\00b\005\000", !12, !2, !5} ; [ DW_TAG_auto_variable ]
-!12 = !{!"0xb\005\0019\000", !47, !1} ; [ DW_TAG_lexical_block ]
-!13 = !{!"0x101\00a\0016777224\000", !6, !2, !5} ; [ DW_TAG_arg_variable ]
-!14 = !{!"0x100\00b\008\000", !15, !2, !5} ; [ DW_TAG_auto_variable ]
-!15 = !{!"0xb\008\0017\001", !47, !6} ; [ DW_TAG_lexical_block ]
-!16 = !{!"0x101\00a\0016777227\000", !7, !2, !5} ; [ DW_TAG_arg_variable ]
-!17 = !{!"0x100\00b\0011\000", !18, !2, !5} ; [ DW_TAG_auto_variable ]
-!18 = !{!"0xb\0011\0019\002", !47, !7} ; [ DW_TAG_lexical_block ]
-!19 = !{!"0x101\00a\0016777230\000", !8, !2, !5} ; [ DW_TAG_arg_variable ]
-!20 = !{!"0x100\00b\0014\000", !21, !2, !5} ; [ DW_TAG_auto_variable ]
-!21 = !{!"0xb\0014\0019\003", !47, !8} ; [ DW_TAG_lexical_block ]
-!25 = !{!"0x34\00x1\00x1\00\004\001\001", !0, !2, !5, i32* @x1, null} ; [ DW_TAG_variable ]
-!26 = !{!"0x34\00x2\00x2\00\007\001\001", !0, !2, !5, i32* @x2, null} ; [ DW_TAG_variable ]
-!27 = !{!"0x101\00a\0016777233\000", !9, !2, !5} ; [ DW_TAG_arg_variable ]
-!28 = !{!"0x100\00b\0017\000", !29, !2, !5} ; [ DW_TAG_auto_variable ]
-!29 = !{!"0xb\0017\0019\004", !47, !9} ; [ DW_TAG_lexical_block ]
-!30 = !MDLocation(line: 5, column: 16, scope: !1)
-!31 = !MDLocation(line: 5, column: 32, scope: !12)
-!32 = !MDLocation(line: 8, column: 14, scope: !6)
-!33 = !MDLocation(line: 8, column: 29, scope: !15)
-!34 = !MDLocation(line: 11, column: 16, scope: !7)
-!35 = !MDLocation(line: 11, column: 32, scope: !18)
-!36 = !MDLocation(line: 14, column: 16, scope: !8)
-!37 = !MDLocation(line: 14, column: 32, scope: !21)
-!38 = !MDLocation(line: 17, column: 16, scope: !9)
-!39 = !MDLocation(line: 17, column: 32, scope: !29)
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DISubprogram(name: "get2", line: 8, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 8, file: !47, scope: !2, type: !3, function: i32 (i32)* @get2, variables: !43)
+!7 = !DISubprogram(name: "get3", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !47, scope: !2, type: !3, function: i32 (i32)* @get3, variables: !44)
+!8 = !DISubprogram(name: "get4", line: 14, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 14, file: !47, scope: !2, type: !3, function: i32 (i32)* @get4, variables: !45)
+!9 = !DISubprogram(name: "get5", line: 17, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 17, file: !47, scope: !2, type: !3, function: i32 (i32)* @get5, variables: !46)
+!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 5, arg: 1, scope: !1, file: !2, type: !5)
+!11 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 5, scope: !12, file: !2, type: !5)
+!12 = distinct !DILexicalBlock(line: 5, column: 19, file: !47, scope: !1)
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 8, arg: 1, scope: !6, file: !2, type: !5)
+!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 8, scope: !15, file: !2, type: !5)
+!15 = distinct !DILexicalBlock(line: 8, column: 17, file: !47, scope: !6)
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 11, arg: 1, scope: !7, file: !2, type: !5)
+!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 11, scope: !18, file: !2, type: !5)
+!18 = distinct !DILexicalBlock(line: 11, column: 19, file: !47, scope: !7)
+!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 14, arg: 1, scope: !8, file: !2, type: !5)
+!20 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 14, scope: !21, file: !2, type: !5)
+!21 = distinct !DILexicalBlock(line: 14, column: 19, file: !47, scope: !8)
+!25 = !DIGlobalVariable(name: "x1", line: 4, isLocal: true, isDefinition: true, scope: !0, file: !2, type: !5, variable: i32* @x1)
+!26 = !DIGlobalVariable(name: "x2", line: 7, isLocal: true, isDefinition: true, scope: !0, file: !2, type: !5, variable: i32* @x2)
+!27 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 17, arg: 1, scope: !9, file: !2, type: !5)
+!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 17, scope: !29, file: !2, type: !5)
+!29 = distinct !DILexicalBlock(line: 17, column: 19, file: !47, scope: !9)
+!30 = !DILocation(line: 5, column: 16, scope: !1)
+!31 = !DILocation(line: 5, column: 32, scope: !12)
+!32 = !DILocation(line: 8, column: 14, scope: !6)
+!33 = !DILocation(line: 8, column: 29, scope: !15)
+!34 = !DILocation(line: 11, column: 16, scope: !7)
+!35 = !DILocation(line: 11, column: 32, scope: !18)
+!36 = !DILocation(line: 14, column: 16, scope: !8)
+!37 = !DILocation(line: 14, column: 32, scope: !21)
+!38 = !DILocation(line: 17, column: 16, scope: !9)
+!39 = !DILocation(line: 17, column: 32, scope: !29)
 !40 = !{!1, !6, !7, !8, !9}
 !41 = !{!25, !26}
 !42 = !{!10, !11}
@@ -117,6 +117,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !44 = !{!16, !17}
 !45 = !{!19, !20}
 !46 = !{!27, !28}
-!47 = !{!"ss3.c", !"/private/tmp"}
+!47 = !DIFile(filename: "ss3.c", directory: "/private/tmp")
 !48 = !{}
-!49 = !{i32 1, !"Debug Info Version", i32 2}
+!49 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/ARM/2011-08-29-SchedCycle.ll b/test/CodeGen/ARM/2011-08-29-SchedCycle.ll
index be188ef630f2..fb8454479508 100644
--- a/test/CodeGen/ARM/2011-08-29-SchedCycle.ll
+++ b/test/CodeGen/ARM/2011-08-29-SchedCycle.ll
@@ -32,7 +32,7 @@
 
 define void @t() nounwind {
 entry:
-  %tmp = load i64* undef, align 4
+  %tmp = load i64, i64* undef, align 4
   %tmp5 = udiv i64 %tmp, 30
   %tmp13 = and i64 %tmp5, 64739244643450880
   %tmp16 = sub i64 0, %tmp13
diff --git a/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll b/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll
index 6647ed8106d5..d9b38b5e5735 100644
--- a/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll
+++ b/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll
@@ -17,13 +17,13 @@ bb25.lr.ph:                                       ; preds = %entry
 bb.i:                                             ; preds = %bb5.i
   %1 = shl nsw i32 %k_addr.0.i, 1
   %.sum8.i = add i32 %1, -1
-  %2 = getelementptr inbounds [256 x i32]* %heap, i32 0, i32 %.sum8.i
-  %3 = load i32* %2, align 4
+  %2 = getelementptr inbounds [256 x i32], [256 x i32]* %heap, i32 0, i32 %.sum8.i
+  %3 = load i32, i32* %2, align 4
   br i1 false, label %bb5.i, label %bb4.i
 
 bb4.i:                                            ; preds = %bb.i
   %.sum10.i = add i32 %k_addr.0.i, -1
-  %4 = getelementptr inbounds [256 x i32]* %heap, i32 0, i32 %.sum10.i
+  %4 = getelementptr inbounds [256 x i32], [256 x i32]* %heap, i32 0, i32 %.sum10.i
   store i32 %3, i32* %4, align 4
   br label %bb5.i
 
diff --git a/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll b/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
index 8fe91028e0c2..2561af707d75 100644
--- a/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
+++ b/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
@@ -11,12 +11,12 @@ target triple = "armv7-none-linux-gnueabi"
 @z2 = common global <4 x i16> zeroinitializer
 
 define void @f() {
-  %1 = load <3 x i16>* @x1
-  %2 = load <3 x i16>* @y1
+  %1 = load <3 x i16>, <3 x i16>* @x1
+  %2 = load <3 x i16>, <3 x i16>* @y1
   %3 = sdiv <3 x i16> %1, %2
   store <3 x i16> %3, <3 x i16>* @z1
-  %4 = load <4 x i16>* @x2
-  %5 = load <4 x i16>* @y2
+  %4 = load <4 x i16>, <4 x i16>* @x2
+  %5 = load <4 x i16>, <4 x i16>* @y2
   %6 = sdiv <4 x i16> %4, %5
   store <4 x i16> %6, <4 x i16>* @z2
   ret void
diff --git a/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll b/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll
index c6f4a93def13..53e3bed53831 100644
--- a/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll
+++ b/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll
@@ -4,7 +4,7 @@
 ; ARM target specific dag combine created a cycle in DAG.
 
 define void @t() nounwind ssp {
-  %1 = load i64* undef, align 4
+  %1 = load i64, i64* undef, align 4
   %2 = shl i32 5, 0
   %3 = zext i32 %2 to i64
   %4 = and i64 %1, %3
diff --git a/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll b/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll
index 09db740b7f76..86596d6282fd 100644
--- a/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll
+++ b/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll
@@ -4,16 +4,16 @@ target triple = "armv6-none-linux-gnueabi"
 
 define void @sample_test(i8* %.T0348, i16* nocapture %sourceA, i16* nocapture %destValues) {
 L.entry:
-  %0 = call i32 (...)* @get_index(i8* %.T0348, i32 0)
+  %0 = call i32 (...) @get_index(i8* %.T0348, i32 0)
   %1 = bitcast i16* %destValues to i8*
   %2 = mul i32 %0, 6
-  %3 = getelementptr i8* %1, i32 %2
+  %3 = getelementptr i8, i8* %1, i32 %2
   %4 = bitcast i8* %3 to <3 x i16>*
-  %5 = load <3 x i16>* %4, align 1
+  %5 = load <3 x i16>, <3 x i16>* %4, align 1
   %6 = bitcast i16* %sourceA to i8*
-  %7 = getelementptr i8* %6, i32 %2
+  %7 = getelementptr i8, i8* %6, i32 %2
   %8 = bitcast i8* %7 to <3 x i16>*
-  %9 = load <3 x i16>* %8, align 1
+  %9 = load <3 x i16>, <3 x i16>* %8, align 1
   %10 = or <3 x i16> %9, %5
   store <3 x i16> %10, <3 x i16>* %4, align 1
   ret void
diff --git a/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll b/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
index a707a92c9fa0..e7059716c49b 100644
--- a/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
+++ b/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
@@ -7,8 +7,8 @@
 
 define void @test_neon_vector_add_2xi8() nounwind {
 ; CHECK-LABEL: test_neon_vector_add_2xi8:
-  %1 = load <2 x i8>* @i8_src1
-  %2 = load <2 x i8>* @i8_src2
+  %1 = load <2 x i8>, <2 x i8>* @i8_src1
+  %2 = load <2 x i8>, <2 x i8>* @i8_src2
   %3 = add <2 x i8> %1, %2
   store <2 x i8> %3, <2 x i8>* @i8_res
   ret void
@@ -16,8 +16,8 @@ define void @test_neon_vector_add_2xi8() nounwind {
 
 define void @test_neon_ld_st_volatile_with_ashr_2xi8() {
 ; CHECK-LABEL: test_neon_ld_st_volatile_with_ashr_2xi8:
-  %1 = load volatile <2 x i8>* @i8_src1
-  %2 = load volatile <2 x i8>* @i8_src2
+  %1 = load volatile <2 x i8>, <2 x i8>* @i8_src1
+  %2 = load volatile <2 x i8>, <2 x i8>* @i8_src2
   %3 = ashr <2 x i8> %1, %2
   store volatile <2 x i8> %3, <2 x i8>* @i8_res
   ret void
diff --git a/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll b/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll
index c1554d848c44..6dc9d4b7025d 100644
--- a/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll
+++ b/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll
@@ -8,7 +8,7 @@ declare <2 x i16> @foo_v2i16(<2 x i16>) nounwind
 
 define void @test_neon_call_return_v2i16() {
 ; CHECK-LABEL: test_neon_call_return_v2i16:
-  %1 = load <2 x i16>* @src1_v2i16
+  %1 = load <2 x i16>, <2 x i16>* @src1_v2i16
   %2 = call <2 x i16> @foo_v2i16(<2 x i16> %1) nounwind
   store <2 x i16> %2, <2 x i16>* @res_v2i16
   ret void
diff --git a/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll b/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll
index c50461a42d8b..1da93bdd7c94 100644
--- a/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll
+++ b/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll
@@ -4,7 +4,7 @@ define <2 x i32> @test1(<2 x double>* %A) {
 ; CHECK: test1
 ; CHECK: vcvt.s32.f64
 ; CHECK: vcvt.s32.f64
-  %tmp1 = load <2 x double>* %A
+  %tmp1 = load <2 x double>, <2 x double>* %A
 	%tmp2 = fptosi <2 x double> %tmp1 to <2 x i32>
 	ret <2 x i32> %tmp2
 }
@@ -13,7 +13,7 @@ define <2 x i32> @test2(<2 x double>* %A) {
 ; CHECK: test2
 ; CHECK: vcvt.u32.f64
 ; CHECK: vcvt.u32.f64
-  %tmp1 = load <2 x double>* %A
+  %tmp1 = load <2 x double>, <2 x double>* %A
 	%tmp2 = fptoui <2 x double> %tmp1 to <2 x i32>
 	ret <2 x i32> %tmp2
 }
@@ -22,7 +22,7 @@ define <2 x double> @test3(<2 x i32>* %A) {
 ; CHECK: test3
 ; CHECK: vcvt.f64.s32
 ; CHECK: vcvt.f64.s32
-  %tmp1 = load <2 x i32>* %A
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = sitofp <2 x i32> %tmp1 to <2 x double>
 	ret <2 x double> %tmp2
 }
@@ -31,7 +31,7 @@ define <2 x double> @test4(<2 x i32>* %A) {
 ; CHECK: test4
 ; CHECK: vcvt.f64.u32
 ; CHECK: vcvt.f64.u32
-  %tmp1 = load <2 x i32>* %A
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = uitofp <2 x i32> %tmp1 to <2 x double>
 	ret <2 x double> %tmp2
 }
diff --git a/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll b/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll
index 52aa0bfaa545..7f4057143a07 100644
--- a/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll
+++ b/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll
@@ -18,38 +18,38 @@ target triple = "thumbv7-apple-ios"
 define void @Compute_Axis_Rotation_Transform(%struct.Transform_Struct.0.11.12.17.43.46.56.58.60* nocapture %transform, double* nocapture %V1, double %angle) nounwind {
 entry:
   store double 1.000000e+00, double* null, align 4
-  %arrayidx5.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 1
+  %arrayidx5.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 1
   store double 0.000000e+00, double* %arrayidx5.1.i, align 4
-  %arrayidx5.2.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 2
+  %arrayidx5.2.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 2
   store double 0.000000e+00, double* %arrayidx5.2.i, align 4
-  %arrayidx5.114.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 0
+  %arrayidx5.114.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 0
   store double 0.000000e+00, double* %arrayidx5.114.i, align 4
-  %arrayidx5.1.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 1
+  %arrayidx5.1.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 1
   store double 1.000000e+00, double* %arrayidx5.1.1.i, align 4
   store double 0.000000e+00, double* null, align 4
   store double 1.000000e+00, double* null, align 4
   store double 0.000000e+00, double* null, align 4
   %call = tail call double @cos(double %angle) nounwind readnone
   %call1 = tail call double @sin(double %angle) nounwind readnone
-  %0 = load double* %V1, align 4
-  %arrayidx2 = getelementptr inbounds double* %V1, i32 1
-  %1 = load double* %arrayidx2, align 4
+  %0 = load double, double* %V1, align 4
+  %arrayidx2 = getelementptr inbounds double, double* %V1, i32 1
+  %1 = load double, double* %arrayidx2, align 4
   %mul = fmul double %0, %1
   %sub = fsub double 1.000000e+00, %call
   %mul3 = fmul double %mul, %sub
-  %2 = load double* undef, align 4
+  %2 = load double, double* undef, align 4
   %mul5 = fmul double %2, %call1
   %add = fadd double %mul3, %mul5
   store double %add, double* %arrayidx5.1.i, align 4
-  %3 = load double* %V1, align 4
+  %3 = load double, double* %V1, align 4
   %mul11 = fmul double %3, undef
   %mul13 = fmul double %mul11, %sub
-  %4 = load double* %arrayidx2, align 4
+  %4 = load double, double* %arrayidx2, align 4
   %mul15 = fmul double %4, %call1
   %sub16 = fsub double %mul13, %mul15
   store double %sub16, double* %arrayidx5.2.i, align 4
-  %5 = load double* %V1, align 4
-  %6 = load double* %arrayidx2, align 4
+  %5 = load double, double* %V1, align 4
+  %6 = load double, double* %arrayidx2, align 4
   %mul22 = fmul double %5, %6
   %mul24 = fmul double %mul22, %sub
   %sub27 = fsub double %mul24, undef
diff --git a/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll b/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll
index bc496b99f4a6..d820d688fde9 100644
--- a/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll
+++ b/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll
@@ -15,14 +15,14 @@ define hidden void @foo() {
 ; CHECK: ldr.w
 ; CHECK-NOT: ldm
 entry:
-  %tmp13 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 0), align 1
-  %tmp15 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 1), align 1
-  %tmp17 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 2), align 1
-  %tmp19 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 3), align 1
-  %tmp = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 0), align 1
-  %tmp3 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 1), align 1
-  %tmp4 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 2), align 1
-  %tmp5 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 3), align 1
+  %tmp13 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 0), align 1
+  %tmp15 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 1), align 1
+  %tmp17 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 2), align 1
+  %tmp19 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 3), align 1
+  %tmp = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 0), align 1
+  %tmp3 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 1), align 1
+  %tmp4 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 2), align 1
+  %tmp5 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 3), align 1
   %insert21 = insertvalue [4 x i32] undef, i32 %tmp13, 0
   %insert23 = insertvalue [4 x i32] %insert21, i32 %tmp15, 1
   %insert25 = insertvalue [4 x i32] %insert23, i32 %tmp17, 2
diff --git a/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
index 86b58c8186b0..404aca13cdba 100644
--- a/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
+++ b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
@@ -16,7 +16,7 @@ define void @test_sqrt(<4 x float>* %X) nounwind {
 ; CHECK:      vst1.64  {{.*}}
 
 L.entry:
-  %0 = load <4 x float>* @A, align 16
+  %0 = load <4 x float>, <4 x float>* @A, align 16
   %1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0)
   store <4 x float> %1, <4 x float>* %X, align 16
   ret void
@@ -48,7 +48,7 @@ define void @test_cos(<4 x float>* %X) nounwind {
 ; CHECK:      vst1.64
 
 L.entry:
-  %0 = load <4 x float>* @A, align 16
+  %0 = load <4 x float>, <4 x float>* @A, align 16
   %1 = call <4 x float> @llvm.cos.v4f32(<4 x float> %0)
   store <4 x float> %1, <4 x float>* %X, align 16
   ret void
@@ -79,7 +79,7 @@ define void @test_exp(<4 x float>* %X) nounwind {
 ; CHECK:      vst1.64
 
 L.entry:
-  %0 = load <4 x float>* @A, align 16
+  %0 = load <4 x float>, <4 x float>* @A, align 16
   %1 = call <4 x float> @llvm.exp.v4f32(<4 x float> %0)
   store <4 x float> %1, <4 x float>* %X, align 16
   ret void
@@ -110,7 +110,7 @@ define void @test_exp2(<4 x float>* %X) nounwind {
 ; CHECK:      vst1.64
 
 L.entry:
-  %0 = load <4 x float>* @A, align 16
+  %0 = load <4 x float>, <4 x float>* @A, align 16
   %1 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %0)
   store <4 x float> %1, <4 x float>* %X, align 16
   ret void
@@ -141,7 +141,7 @@ define void @test_log10(<4 x float>* %X) nounwind {
 ; CHECK:      vst1.64
 
 L.entry:
-  %0 = load <4 x float>* @A, align 16
+  %0 = load <4 x float>, <4 x float>* @A, align 16
   %1 = call <4 x float> @llvm.log10.v4f32(<4 x float> %0)
   store <4 x float> %1, <4 x float>* %X, align 16
   ret void
@@ -172,7 +172,7 @@ define void @test_log(<4 x float>* %X) nounwind {
 ; CHECK:      vst1.64
 
 L.entry:
-  %0 = load <4 x float>* @A, align 16
+  %0 = load <4 x float>, <4 x float>* @A, align 16
   %1 = call <4 x float> @llvm.log.v4f32(<4 x float> %0)
   store <4 x float> %1, <4 x float>* %X, align 16
   ret void
@@ -203,7 +203,7 @@ define void @test_log2(<4 x float>* %X) nounwind {
 ; CHECK:      vst1.64
 
 L.entry:
-  %0 = load <4 x float>* @A, align 16
+  %0 = load <4 x float>, <4 x float>* @A, align 16
   %1 = call <4 x float> @llvm.log2.v4f32(<4 x float> %0)
   store <4 x float> %1, <4 x float>* %X, align 16
   ret void
@@ -236,7 +236,7 @@ define void @test_pow(<4 x float>* %X) nounwind {
 
 L.entry:
 
-  %0 = load <4 x float>* @A, align 16
+  %0 = load <4 x float>, <4 x float>* @A, align 16
   %1 = call <4 x float> @llvm.pow.v4f32(<4 x float> %0, <4 x float> <float 2., float 2., float 2., float 2.>)
 
   store <4 x float> %1, <4 x float>* %X, align 16
@@ -259,7 +259,7 @@ define void @test_powi(<4 x float>* %X) nounwind {
 
 L.entry:
 
-  %0 = load <4 x float>* @A, align 16
+  %0 = load <4 x float>, <4 x float>* @A, align 16
   %1 = call <4 x float> @llvm.powi.v4f32(<4 x float> %0, i32 2)
 
   store <4 x float> %1, <4 x float>* %X, align 16
@@ -292,7 +292,7 @@ define void @test_sin(<4 x float>* %X) nounwind {
 ; CHECK:      vst1.64
 
 L.entry:
-  %0 = load <4 x float>* @A, align 16
+  %0 = load <4 x float>, <4 x float>* @A, align 16
   %1 = call <4 x float> @llvm.sin.v4f32(<4 x float> %0)
   store <4 x float> %1, <4 x float>* %X, align 16
   ret void
@@ -323,7 +323,7 @@ define void @test_floor(<4 x float>* %X) nounwind {
 ; CHECK:      vst1.64
 
 L.entry:
-  %0 = load <4 x float>* @A, align 16
+  %0 = load <4 x float>, <4 x float>* @A, align 16
   %1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0)
   store <4 x float> %1, <4 x float>* %X, align 16
   ret void
diff --git a/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll b/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll
index 0c90f4cf949a..0d324404d7be 100644
--- a/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll
+++ b/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll
@@ -8,9 +8,9 @@ target triple = "thumbv7-apple-darwin10"
 @x2 = internal global i64 12
 
 define i64 @f() {
-  %ax = load i32* @x1
+  %ax = load i32, i32* @x1
   %a = zext i32 %ax to i64
-  %b = load i64* @x2
+  %b = load i64, i64* @x2
   %c = add i64 %a, %b
   ret i64 %c
 }
diff --git a/test/CodeGen/ARM/2011-12-14-machine-sink.ll b/test/CodeGen/ARM/2011-12-14-machine-sink.ll
index 9334bf36d805..88019f450e36 100644
--- a/test/CodeGen/ARM/2011-12-14-machine-sink.ll
+++ b/test/CodeGen/ARM/2011-12-14-machine-sink.ll
@@ -5,7 +5,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-
 target triple = "thumbv7-apple-ios4.0.0"
 ; STATS-NOT: machine-sink
 
-define i32 @foo(i32 %h) nounwind readonly ssp {
+define i32 @foo(i32 %h, i32 %arg1) nounwind readonly ssp {
 entry:
   br label %for.cond
 
@@ -14,33 +14,26 @@ for.cond:                                         ; preds = %for.body, %entry
   br i1 %cmp, label %for.body, label %if.end299
 
 for.body:                                         ; preds = %for.cond
-  %v.5 = select i1 undef, i32 undef, i32 0
-  %0 = load i8* undef, align 1
+  %cond0 = icmp ne i32 %arg1, 42
+  %v.5 = select i1 %cond0, i32 undef, i32 0
+  %0 = load i8, i8* undef, align 1
   %conv88 = zext i8 %0 to i32
   %sub89 = sub nsw i32 0, %conv88
-  %v.8 = select i1 undef, i32 undef, i32 %sub89
-  %1 = load i8* null, align 1
+  %cond1 = icmp ne i32 %arg1, 23
+  %v.8 = select i1 %cond1, i32 undef, i32 %sub89
+  %1 = load i8, i8* null, align 1
   %conv108 = zext i8 %1 to i32
-  %2 = load i8* undef, align 1
+  %2 = load i8, i8* undef, align 1
   %conv110 = zext i8 %2 to i32
   %sub111 = sub nsw i32 %conv108, %conv110
   %cmp112 = icmp slt i32 %sub111, 0
   %sub115 = sub nsw i32 0, %sub111
-  %v.10 = select i1 %cmp112, i32 %sub115, i32 %sub111
-  %add62 = add i32 0, %v.5
-  %add73 = add i32 %add62, 0
-  %add84 = add i32 %add73, 0
-  %add95 = add i32 %add84, %v.8
-  %add106 = add i32 %add95, 0
-  %add117 = add i32 %add106, %v.10
-  %add128 = add i32 %add117, 0
-  %add139 = add i32 %add128, 0
-  %add150 = add i32 %add139, 0
-  %add161 = add i32 %add150, 0
-  %add172 = add i32 %add161, 0
+  %abs = select i1 %cmp112, i32 %sub115, i32 %sub111
+  %add95 = add i32 %v.5, %v.8
+  %add117 = add i32 %add95, %abs
   br i1 undef, label %for.cond, label %if.end299
 
 if.end299:                                        ; preds = %for.body, %for.cond
-  %s.10 = phi i32 [ %add172, %for.body ], [ 0, %for.cond ]
+  %s.10 = phi i32 [ %add117, %for.body ], [ 0, %for.cond ]
   ret i32 %s.10
 }
diff --git a/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll b/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll
index ddb76326947c..40d1f628aaae 100644
--- a/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll
+++ b/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll
@@ -22,13 +22,13 @@ bb:
   store i32 %b, i32* %tmp1, align 4
   store i8* %d, i8** %tmp2, align 4
   store i1 false, i1* %tmp3
-  %tmp7 = load i8** %c
+  %tmp7 = load i8*, i8** %c
   %tmp10 = invoke %0* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %0* (i8*, i8*, %0*)*)(i8* %tmp7, i8* %d, %0* null)
           to label %bb11 unwind label %bb15
 
 bb11:                                             ; preds = %bb
   store %0* %tmp10, %0** %myException, align 4
-  %tmp12 = load %0** %myException, align 4
+  %tmp12 = load %0*, %0** %myException, align 4
   %tmp13 = bitcast %0* %tmp12 to i8*
   invoke void @objc_exception_throw(i8* %tmp13) noreturn
           to label %bb14 unwind label %bb15
diff --git a/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll b/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll
index 0f1c452b8678..3f827f8e702f 100644
--- a/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll
+++ b/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll
@@ -18,7 +18,7 @@ bb3:                                              ; preds = %bb4, %bb2
   br i1 %tmp, label %bb4, label %bb67
 
 bb4:                                              ; preds = %bb3
-  %tmp5 = load <4 x i32>* undef, align 16
+  %tmp5 = load <4 x i32>, <4 x i32>* undef, align 16
   %tmp6 = and <4 x i32> %tmp5, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>
   %tmp7 = or <4 x i32> %tmp6, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
   %tmp8 = bitcast <4 x i32> %tmp7 to <4 x float>
@@ -41,9 +41,9 @@ bb4:                                              ; preds = %bb3
   %tmp24 = trunc i128 %tmp23 to i64
   %tmp25 = insertvalue [2 x i64] undef, i64 %tmp24, 0
   %tmp26 = insertvalue [2 x i64] %tmp25, i64 0, 1
-  %tmp27 = load float* undef, align 4
+  %tmp27 = load float, float* undef, align 4
   %tmp28 = insertelement <4 x float> undef, float %tmp27, i32 3
-  %tmp29 = load <4 x i32>* undef, align 16
+  %tmp29 = load <4 x i32>, <4 x i32>* undef, align 16
   %tmp30 = and <4 x i32> %tmp29, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>
   %tmp31 = or <4 x i32> %tmp30, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
   %tmp32 = bitcast <4 x i32> %tmp31 to <4 x float>
@@ -52,10 +52,10 @@ bb4:                                              ; preds = %bb3
   %tmp35 = fmul <4 x float> %tmp34, undef
   %tmp36 = fmul <4 x float> %tmp35, undef
   %tmp37 = call arm_aapcs_vfpcc  i8* undef(i8* undef) nounwind
-  %tmp38 = load float* undef, align 4
+  %tmp38 = load float, float* undef, align 4
   %tmp39 = insertelement <2 x float> undef, float %tmp38, i32 0
   %tmp40 = call arm_aapcs_vfpcc  i8* undef(i8* undef) nounwind
-  %tmp41 = load float* undef, align 4
+  %tmp41 = load float, float* undef, align 4
   %tmp42 = insertelement <4 x float> undef, float %tmp41, i32 3
   %tmp43 = shufflevector <2 x float> %tmp39, <2 x float> undef, <4 x i32> zeroinitializer
   %tmp44 = fmul <4 x float> %tmp33, %tmp43
@@ -64,10 +64,10 @@ bb4:                                              ; preds = %bb3
   %tmp47 = fmul <4 x float> %tmp46, %tmp36
   %tmp48 = fadd <4 x float> undef, %tmp47
   %tmp49 = call arm_aapcs_vfpcc  i8* undef(i8* undef) nounwind
-  %tmp50 = load float* undef, align 4
+  %tmp50 = load float, float* undef, align 4
   %tmp51 = insertelement <4 x float> undef, float %tmp50, i32 3
   %tmp52 = call arm_aapcs_vfpcc float* null(i8* undef) nounwind
-  %tmp54 = load float* %tmp52, align 4
+  %tmp54 = load float, float* %tmp52, align 4
   %tmp55 = insertelement <4 x float> undef, float %tmp54, i32 3
   %tmp56 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %tmp22
   %tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounwind
diff --git a/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll b/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll
index 61623ec1b6a4..b70b7f6f3b2e 100644
--- a/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll
+++ b/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll
@@ -7,7 +7,7 @@ target triple = "armv7-none-linux-eabi"
 ; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE.
 define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 {
 bb:
-  %tmp = load <2 x float>* undef, align 8
+  %tmp = load <2 x float>, <2 x float>* undef, align 8
   %tmp2 = extractelement <2 x float> %tmp, i32 0
   %tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0
   %tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1
diff --git a/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll b/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll
index a9e2ebb7fe12..2484f0d42ed3 100644
--- a/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll
+++ b/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll
@@ -56,9 +56,9 @@ bb3:                                              ; preds = %bb2
   %tmp39 = shufflevector <2 x i64> %tmp38, <2 x i64> undef, <1 x i32> zeroinitializer
   %tmp40 = bitcast <1 x i64> %tmp39 to <2 x float>
   %tmp41 = shufflevector <2 x float> %tmp40, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
-  %tmp42 = load <4 x float>* null, align 16
+  %tmp42 = load <4 x float>, <4 x float>* null, align 16
   %tmp43 = fmul <4 x float> %tmp42, %tmp41
-  %tmp44 = load <4 x float>* undef, align 16
+  %tmp44 = load <4 x float>, <4 x float>* undef, align 16
   %tmp45 = fadd <4 x float> undef, %tmp43
   %tmp46 = fadd <4 x float> undef, %tmp45
   %tmp47 = bitcast <4 x float> %tmp36 to <2 x i64>
@@ -76,7 +76,7 @@ bb3:                                              ; preds = %bb2
   %tmp59 = fmul <4 x float> undef, %tmp58
   %tmp60 = fadd <4 x float> %tmp59, undef
   %tmp61 = fadd <4 x float> %tmp60, zeroinitializer
-  %tmp62 = load void (i8*, i8*)** undef, align 4
+  %tmp62 = load void (i8*, i8*)*, void (i8*, i8*)** undef, align 4
   call arm_aapcs_vfpcc  void %tmp62(i8* sret undef, i8* undef) nounwind
   %tmp63 = bitcast <4 x float> %tmp46 to i128
   %tmp64 = bitcast <4 x float> %tmp54 to i128
@@ -96,7 +96,7 @@ bb3:                                              ; preds = %bb2
   call arm_aapcs_vfpcc  void @bar(i8* sret null, [8 x i64] %tmp77) nounwind
   %tmp78 = call arm_aapcs_vfpcc  i8* null(i8* null) nounwind
   %tmp79 = bitcast i8* %tmp78 to i512*
-  %tmp80 = load i512* %tmp79, align 16
+  %tmp80 = load i512, i512* %tmp79, align 16
   %tmp81 = lshr i512 %tmp80, 128
   %tmp82 = trunc i512 %tmp80 to i128
   %tmp83 = trunc i512 %tmp81 to i128
diff --git a/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll b/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll
index 6c7aaad7c692..b0411384b96a 100644
--- a/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll
+++ b/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll
@@ -10,7 +10,7 @@ target triple = "armv7-none-linux-gnueabi"
 @foo = external global %0, align 16
 
 define arm_aapcs_vfpcc void @bar(float, i1 zeroext, i1 zeroext) nounwind {
-  %4 = load <4 x float>* getelementptr inbounds (%0* @foo, i32 0, i32 0), align 16
+  %4 = load <4 x float>, <4 x float>* getelementptr inbounds (%0, %0* @foo, i32 0, i32 0), align 16
   %5 = extractelement <4 x float> %4, i32 0
   %6 = extractelement <4 x float> %4, i32 1
   %7 = extractelement <4 x float> %4, i32 2
diff --git a/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll b/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll
index 6206cd74d584..6fb760c4bcc7 100644
--- a/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll
+++ b/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll
@@ -7,7 +7,7 @@
 define void @test_hi_short3(<3 x i16> * nocapture %srcA, <2 x i16> * nocapture %dst) nounwind {
 entry:
 ; CHECK: vst1.32
-  %0 = load <3 x i16> * %srcA, align 8
+  %0 = load <3 x i16> , <3 x i16> * %srcA, align 8
   %1 = shufflevector <3 x i16> %0, <3 x i16> undef, <2 x i32> <i32 2, i32 undef>
   store <2 x i16> %1, <2 x i16> * %dst, align 4
   ret void
diff --git a/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll
index a288015d6016..6f92613fa1ff 100644
--- a/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll
+++ b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll
@@ -27,13 +27,13 @@
 define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind {
 entry:
   store volatile i32 65540, i32* %p1, align 4
-  %0 = load volatile i32* %p2, align 4
+  %0 = load volatile i32, i32* %p2, align 4
   ret i32 %0
 }
 
 define i32 @f2(i32* nocapture %p1, i32* nocapture %p2) nounwind {
 entry:
   store i32 65540, i32* %p1, align 4
-  %0 = load i32* %p2, align 4
+  %0 = load i32, i32* %p2, align 4
   ret i32 %0
 }
diff --git a/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll b/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll
index 70e307934559..6e0b828ad24f 100644
--- a/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll
+++ b/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll
@@ -129,7 +129,7 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable
   %45 = fmul <4 x float> undef, undef
   %46 = fmul <4 x float> %45, %43
   %47 = fmul <4 x float> undef, %44
-  %48 = load <4 x float>* undef, align 8
+  %48 = load <4 x float>, <4 x float>* undef, align 8
   %49 = bitcast <4 x float> %48 to <2 x i64>
   %50 = shufflevector <2 x i64> %49, <2 x i64> undef, <1 x i32> <i32 1>
   %51 = bitcast <1 x i64> %50 to <2 x float>
diff --git a/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll b/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll
index bdcd1b6ad4b7..576dff4d001e 100644
--- a/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll
+++ b/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll
@@ -6,7 +6,7 @@ target triple = "armv7-none-linux-gnueabi"
 
 define void @test_hi_char8() noinline {
 entry:
-  %0 = load <4 x i8>* undef, align 1
+  %0 = load <4 x i8>, <4 x i8>* undef, align 1
   store <4 x i8> %0, <4 x i8>* null, align 4
   ret void
 }
diff --git a/test/CodeGen/ARM/2012-08-09-neon-extload.ll b/test/CodeGen/ARM/2012-08-09-neon-extload.ll
index a7108253cb62..285a431a6ecf 100644
--- a/test/CodeGen/ARM/2012-08-09-neon-extload.ll
+++ b/test/CodeGen/ARM/2012-08-09-neon-extload.ll
@@ -14,7 +14,7 @@
 define void @test_v2i8tov2i32() {
 ; CHECK-LABEL: test_v2i8tov2i32:
 
-  %i8val = load <2 x i8>* @var_v2i8
+  %i8val = load <2 x i8>, <2 x i8>* @var_v2i8
 
   %i32val = sext <2 x i8> %i8val to <2 x i32>
   store <2 x i32> %i32val, <2 x i32>* @var_v2i32
@@ -28,7 +28,7 @@ define void @test_v2i8tov2i32() {
 define void @test_v2i8tov2i64() {
 ; CHECK-LABEL: test_v2i8tov2i64:
 
-  %i8val = load <2 x i8>* @var_v2i8
+  %i8val = load <2 x i8>, <2 x i8>* @var_v2i8
 
   %i64val = sext <2 x i8> %i8val to <2 x i64>
   store <2 x i64> %i64val, <2 x i64>* @var_v2i64
@@ -46,7 +46,7 @@ define void @test_v2i8tov2i64() {
 define void @test_v4i8tov4i16() {
 ; CHECK-LABEL: test_v4i8tov4i16:
 
-  %i8val = load <4 x i8>* @var_v4i8
+  %i8val = load <4 x i8>, <4 x i8>* @var_v4i8
 
   %i16val = sext <4 x i8> %i8val to <4 x i16>
   store <4 x i16> %i16val, <4 x i16>* @var_v4i16
@@ -61,7 +61,7 @@ define void @test_v4i8tov4i16() {
 define void @test_v4i8tov4i32() {
 ; CHECK-LABEL: test_v4i8tov4i32:
 
-  %i8val = load <4 x i8>* @var_v4i8
+  %i8val = load <4 x i8>, <4 x i8>* @var_v4i8
 
   %i16val = sext <4 x i8> %i8val to <4 x i32>
   store <4 x i32> %i16val, <4 x i32>* @var_v4i32
@@ -75,7 +75,7 @@ define void @test_v4i8tov4i32() {
 define void @test_v2i16tov2i32() {
 ; CHECK-LABEL: test_v2i16tov2i32:
 
-  %i16val = load <2 x i16>* @var_v2i16
+  %i16val = load <2 x i16>, <2 x i16>* @var_v2i16
 
   %i32val = sext <2 x i16> %i16val to <2 x i32>
   store <2 x i32> %i32val, <2 x i32>* @var_v2i32
@@ -90,7 +90,7 @@ define void @test_v2i16tov2i32() {
 define void @test_v2i16tov2i64() {
 ; CHECK-LABEL: test_v2i16tov2i64:
 
-  %i16val = load <2 x i16>* @var_v2i16
+  %i16val = load <2 x i16>, <2 x i16>* @var_v2i16
 
   %i64val = sext <2 x i16> %i16val to <2 x i64>
   store <2 x i64> %i64val, <2 x i64>* @var_v2i64
diff --git a/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll b/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
index e8d4fb22a59f..3a851d68f0a4 100644
--- a/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
+++ b/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
@@ -15,7 +15,7 @@
 define void @sextload_v4i8_c(<4 x i8>* %v) nounwind {
 ;CHECK-LABEL: sextload_v4i8_c:
 entry:
-  %0 = load <4 x i8>* %v, align 8
+  %0 = load <4 x i8>, <4 x i8>* %v, align 8
   %v0  = sext <4 x i8> %0 to <4 x i32>
 ;CHECK: vmull
   %v1 = mul <4 x i32>  %v0, <i32 3, i32 3, i32 3, i32 3>
@@ -28,7 +28,7 @@ entry:
 define void @sextload_v2i8_c(<2 x i8>* %v) nounwind {
 ;CHECK-LABEL: sextload_v2i8_c:
 entry:
-  %0   = load <2 x i8>* %v, align 8
+  %0   = load <2 x i8>, <2 x i8>* %v, align 8
   %v0  = sext <2 x i8>  %0 to <2 x i64>
 ;CHECK: vmull
   %v1  = mul <2 x i64>  %v0, <i64 3, i64 3>
@@ -41,7 +41,7 @@ entry:
 define void @sextload_v2i16_c(<2 x i16>* %v) nounwind {
 ;CHECK-LABEL: sextload_v2i16_c:
 entry:
-  %0   = load <2 x i16>* %v, align 8
+  %0   = load <2 x i16>, <2 x i16>* %v, align 8
   %v0  = sext <2 x i16>  %0 to <2 x i64>
 ;CHECK: vmull
   %v1  = mul <2 x i64>  %v0, <i64 3, i64 3>
@@ -56,10 +56,10 @@ entry:
 define void @sextload_v4i8_v(<4 x i8>* %v, <4 x i8>* %p) nounwind {
 ;CHECK-LABEL: sextload_v4i8_v:
 entry:
-  %0 = load <4 x i8>* %v, align 8
+  %0 = load <4 x i8>, <4 x i8>* %v, align 8
   %v0  = sext <4 x i8> %0 to <4 x i32>
 
-  %1  = load <4 x i8>* %p, align 8
+  %1  = load <4 x i8>, <4 x i8>* %p, align 8
   %v2 = sext <4 x i8> %1 to <4 x i32>
 ;CHECK: vmull
   %v1 = mul <4 x i32>  %v0, %v2
@@ -72,10 +72,10 @@ entry:
 define void @sextload_v2i8_v(<2 x i8>* %v, <2 x i8>* %p) nounwind {
 ;CHECK-LABEL: sextload_v2i8_v:
 entry:
-  %0 = load <2 x i8>* %v, align 8
+  %0 = load <2 x i8>, <2 x i8>* %v, align 8
   %v0  = sext <2 x i8> %0 to <2 x i64>
 
-  %1  = load <2 x i8>* %p, align 8
+  %1  = load <2 x i8>, <2 x i8>* %p, align 8
   %v2 = sext <2 x i8> %1 to <2 x i64>
 ;CHECK: vmull
   %v1 = mul <2 x i64>  %v0, %v2
@@ -88,10 +88,10 @@ entry:
 define void @sextload_v2i16_v(<2 x i16>* %v, <2 x i16>* %p) nounwind {
 ;CHECK-LABEL: sextload_v2i16_v:
 entry:
-  %0 = load <2 x i16>* %v, align 8
+  %0 = load <2 x i16>, <2 x i16>* %v, align 8
   %v0  = sext <2 x i16> %0 to <2 x i64>
 
-  %1  = load <2 x i16>* %p, align 8
+  %1  = load <2 x i16>, <2 x i16>* %p, align 8
   %v2 = sext <2 x i16> %1 to <2 x i64>
 ;CHECK: vmull
   %v1 = mul <2 x i64>  %v0, %v2
@@ -106,10 +106,10 @@ entry:
 define void @sextload_v4i8_vs(<4 x i8>* %v, <4 x i16>* %p) nounwind {
 ;CHECK-LABEL: sextload_v4i8_vs:
 entry:
-  %0 = load <4 x i8>* %v, align 8
+  %0 = load <4 x i8>, <4 x i8>* %v, align 8
   %v0  = sext <4 x i8> %0 to <4 x i32>
 
-  %1  = load <4 x i16>* %p, align 8
+  %1  = load <4 x i16>, <4 x i16>* %p, align 8
   %v2 = sext <4 x i16> %1 to <4 x i32>
 ;CHECK: vmull
   %v1 = mul <4 x i32>  %v0, %v2
@@ -122,10 +122,10 @@ entry:
 define void @sextload_v2i8_vs(<2 x i8>* %v, <2 x i16>* %p) nounwind {
 ;CHECK-LABEL: sextload_v2i8_vs:
 entry:
-  %0 = load <2 x i8>* %v, align 8
+  %0 = load <2 x i8>, <2 x i8>* %v, align 8
   %v0  = sext <2 x i8> %0 to <2 x i64>
 
-  %1  = load <2 x i16>* %p, align 8
+  %1  = load <2 x i16>, <2 x i16>* %p, align 8
   %v2 = sext <2 x i16> %1 to <2 x i64>
 ;CHECK: vmull
   %v1 = mul <2 x i64>  %v0, %v2
@@ -138,10 +138,10 @@ entry:
 define void @sextload_v2i16_vs(<2 x i16>* %v, <2 x i32>* %p) nounwind {
 ;CHECK-LABEL: sextload_v2i16_vs:
 entry:
-  %0 = load <2 x i16>* %v, align 8
+  %0 = load <2 x i16>, <2 x i16>* %v, align 8
   %v0  = sext <2 x i16> %0 to <2 x i64>
 
-  %1  = load <2 x i32>* %p, align 8
+  %1  = load <2 x i32>, <2 x i32>* %p, align 8
   %v2 = sext <2 x i32> %1 to <2 x i64>
 ;CHECK: vmull
   %v1 = mul <2 x i64>  %v0, %v2
diff --git a/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll b/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll
index ec7f72d7c2e8..545bfc73c590 100644
--- a/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll
+++ b/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll
@@ -21,17 +21,17 @@ define void @findEdges(i8*) nounwind ssp {
   %6 = phi i8* [ %19, %5 ], [ %0, %1 ]
   %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* null, i32 1)
   %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %7, 0
-  %9 = getelementptr inbounds i8* null, i32 3
+  %9 = getelementptr inbounds i8, i8* null, i32 3
   %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %9, i32 1)
   %11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %10, 2
   %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %6, i32 1)
   %13 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 0
   %14 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 1
-  %15 = getelementptr inbounds i8* %6, i32 3
+  %15 = getelementptr inbounds i8, i8* %6, i32 3
   %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %15, i32 1)
   %17 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 1
   %18 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 2
-  %19 = getelementptr inbounds i8* %6, i32 48
+  %19 = getelementptr inbounds i8, i8* %6, i32 48
   %20 = bitcast <16 x i8> %13 to <2 x i64>
   %21 = bitcast <16 x i8> %8 to <2 x i64>
   %22 = bitcast <16 x i8> %14 to <2 x i64>
diff --git a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
index f864c8cbfcb5..4a1341c4d6e7 100644
--- a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
+++ b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
@@ -10,7 +10,9 @@ declare void @llvm.va_end(i8*) nounwind
 ; CHECK-LABEL: test_byval_8_bytes_alignment:
 define void @test_byval_8_bytes_alignment(i32 %i, ...) {
 entry:
-; CHECK: stm     r0, {r1, r2, r3}
+; CHECK: sub       sp, sp, #12
+; CHECK: sub       sp, sp, #4
+; CHECK: stmib     sp, {r1, r2, r3}
   %g = alloca i8*
   %g1 = bitcast i8** %g to i8*
   call void @llvm.va_start(i8* %g1)
@@ -31,7 +33,7 @@ entry:
 ; CHECK: movw r0, #555
 define i32 @main() {
 entry:
-  call void (i32, ...)* @test_byval_8_bytes_alignment(i32 555, %struct_t* byval @static_val)
+  call void (i32, ...) @test_byval_8_bytes_alignment(i32 555, %struct_t* byval @static_val)
   ret i32 0
 }
 
@@ -44,9 +46,9 @@ declare void @f(double);
 ; CHECK-NOT:   str     r1
 define void @test_byval_8_bytes_alignment_fixed_arg(i32 %n1, %struct_t* byval %val) nounwind {
 entry:
-  %a = getelementptr inbounds %struct_t* %val, i32 0, i32 0
-  %0 = load double* %a
-  call void (double)* @f(double %0)
+  %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0
+  %0 = load double, double* %a
+  call void (double) @f(double %0)
   ret void
 }
 
@@ -58,6 +60,6 @@ entry:
 ; CHECK: movw r0, #555
 define i32 @main_fixed_arg() {
 entry:
-  call void (i32, %struct_t*)* @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval @static_val)
+  call void (i32, %struct_t*) @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval @static_val)
   ret i32 0
 }
diff --git a/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll b/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
index c9ccc103e2fa..34af9026b52e 100644
--- a/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
+++ b/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
@@ -12,8 +12,8 @@ declare i32 @printf(i8*, ...)
 ; CHECK:       vldr    d16, [sp, #8]
 define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, %struct_t* byval %val) nounwind {
 entry:
-  %a = getelementptr inbounds %struct_t* %val, i32 0, i32 0
-  %0 = load double* %a
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), double %0)
+  %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0
+  %0 = load double, double* %a
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), double %0)
   ret void
 }
diff --git a/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll b/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
index 0028eec80f44..ff3b7e16188e 100644
--- a/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
+++ b/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
@@ -10,8 +10,9 @@ define void @t(i32 %a, %struct.s* byval %s) nounwind {
 entry:
 
 ; Here we need to only check proper start address of restored %s argument.
-; CHECK:      sub     sp, sp, #16
+; CHECK:      sub     sp, sp, #12
 ; CHECK:      push    {r11, lr}
+; CHECK:      sub     sp, sp, #4
 ; CHECK:      add     r0, sp, #12
 ; CHECK:      stm     r0, {r1, r2, r3}
 ; CHECK:      add     r0, sp, #12
diff --git a/test/CodeGen/ARM/2013-01-21-PR14992.ll b/test/CodeGen/ARM/2013-01-21-PR14992.ll
index 014686feee0e..4c1f2a741e47 100644
--- a/test/CodeGen/ARM/2013-01-21-PR14992.ll
+++ b/test/CodeGen/ARM/2013-01-21-PR14992.ll
@@ -6,12 +6,12 @@
 ;CHECK-LABEL: foo:
 define i32 @foo(i32* %a) nounwind optsize {
 entry:
-  %0 = load i32* %a, align 4
-  %arrayidx1 = getelementptr inbounds i32* %a, i32 1
-  %1 = load i32* %arrayidx1, align 4
-  %arrayidx2 = getelementptr inbounds i32* %a, i32 2
-  %2 = load i32* %arrayidx2, align 4
-  %add.ptr = getelementptr inbounds i32* %a, i32 3
+  %0 = load i32, i32* %a, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %a, i32 1
+  %1 = load i32, i32* %arrayidx1, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 2
+  %2 = load i32, i32* %arrayidx2, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %a, i32 3
 ;Make sure we do not have a duplicated register in the front of the reg list
 ;EXPECTED:  ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], {{r[0-9]+}},
 ;CHECK-NOT: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], [[REG]],
diff --git a/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
index c5eba7d4773c..c38dd16f0d27 100644
--- a/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
+++ b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
@@ -2,26 +2,26 @@
 ;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
 
 ;CHECK-LABEL: foo:
-;CHECK: 	sub	sp, sp, #8
+;CHECK: 	sub	sp, sp, #16
 ;CHECK: 	push	{r11, lr}
-;CHECK: 	str	r0, [sp, #12]
-;CHECK: 	add	r0, sp, #12
+;CHECK: 	str	r0, [sp, #8]
+;CHECK: 	add	r0, sp, #8
 ;CHECK: 	bl	fooUseParam
 ;CHECK: 	pop	{r11, lr}
-;CHECK: 	add	sp, sp, #8
+;CHECK: 	add	sp, sp, #16
 ;CHECK: 	mov	pc, lr
 
 ;CHECK-LABEL: foo2:
-;CHECK: 	sub	sp, sp, #8
+;CHECK: 	sub	sp, sp, #16
 ;CHECK: 	push	{r11, lr}
 ;CHECK: 	str	r0, [sp, #8]
 ;CHECK: 	add	r0, sp, #8
-;CHECK: 	str	r2, [sp, #12]
+;CHECK: 	str	r2, [sp, #16]
 ;CHECK: 	bl	fooUseParam
-;CHECK: 	add	r0, sp, #12
+;CHECK: 	add	r0, sp, #16
 ;CHECK: 	bl	fooUseParam
 ;CHECK: 	pop	{r11, lr}
-;CHECK: 	add	sp, sp, #8
+;CHECK: 	add	sp, sp, #16
 ;CHECK: 	mov	pc, lr
 
 ;CHECK-LABEL: doFoo:
diff --git a/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll b/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll
index 446403d79cac..5e82b0925b24 100644
--- a/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll
+++ b/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll
@@ -33,7 +33,7 @@ define void @foo2(double %p0, ; --> D0
                   %struct_t* byval %p10) ; --> Stack+8
 {
 entry:
-;CHECK:     push.w {r11, lr}
+;CHECK:     push {r7, lr}
 ;CHECK-NOT: stm
 ;CHECK:     add r0, sp, #16
 ;CHECK:     bl fooUseStruct
diff --git a/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll b/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll
index 459992818749..6c8b0ff2de19 100644
--- a/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll
+++ b/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll
@@ -9,9 +9,9 @@ define void @sample_test(<8 x i64> * %secondSource, <8 x i64> * %source, <8 x i6
 entry:
 
 ; Load %source
-  %s0 = load <8 x i64> * %source, align 64
-  %arrayidx64 = getelementptr inbounds <8 x i64> * %source, i32 6
-  %s120 = load <8 x i64> * %arrayidx64, align 64
+  %s0 = load <8 x i64> , <8 x i64> * %source, align 64
+  %arrayidx64 = getelementptr inbounds <8 x i64>, <8 x i64> * %source, i32 6
+  %s120 = load <8 x i64> , <8 x i64> * %arrayidx64, align 64
   %s122 = bitcast <8 x i64> %s120 to i512
   %data.i.i677.48.extract.shift = lshr i512 %s122, 384
   %data.i.i677.48.extract.trunc = trunc i512 %data.i.i677.48.extract.shift to i64
@@ -33,9 +33,9 @@ entry:
   %s130 = insertelement <8 x i64> %s129, i64 %data.i.i677.56.extract.trunc, i32 7
 
 ; Load %secondSource
-  %s1 = load <8 x i64> * %secondSource, align 64
-  %arrayidx67 = getelementptr inbounds <8 x i64> * %secondSource, i32 6
-  %s121 = load <8 x i64> * %arrayidx67, align 64
+  %s1 = load <8 x i64> , <8 x i64> * %secondSource, align 64
+  %arrayidx67 = getelementptr inbounds <8 x i64>, <8 x i64> * %secondSource, i32 6
+  %s121 = load <8 x i64> , <8 x i64> * %arrayidx67, align 64
   %s131 = bitcast <8 x i64> %s121 to i512
   %data.i1.i676.48.extract.shift = lshr i512 %s131, 384
   %data.i1.i676.48.extract.trunc = trunc i512 %data.i1.i676.48.extract.shift to i64
@@ -61,10 +61,10 @@ entry:
   %vecinit35.i.i700 = shufflevector <8 x i64> %vecinit28.i.i699, <8 x i64> %s139, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 13, i32 undef, i32 undef>
   %vecinit42.i.i701 = shufflevector <8 x i64> %vecinit35.i.i700, <8 x i64> %s139, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 14, i32 undef>
   %vecinit49.i.i702 = shufflevector <8 x i64> %vecinit42.i.i701, <8 x i64> %s130, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15>
-  %arrayidx72 = getelementptr inbounds <8 x i64> * %dest, i32 6
+  %arrayidx72 = getelementptr inbounds <8 x i64>, <8 x i64> * %dest, i32 6
   store <8 x i64> %vecinit49.i.i702, <8 x i64> * %arrayidx72, align 64
-  %arrayidx78 = getelementptr inbounds <8 x i64> * %secondSource, i32 7
-  %s141 = load <8 x i64> * %arrayidx78, align 64
+  %arrayidx78 = getelementptr inbounds <8 x i64>, <8 x i64> * %secondSource, i32 7
+  %s141 = load <8 x i64> , <8 x i64> * %arrayidx78, align 64
   %s151 = bitcast <8 x i64> %s141 to i512
   %data.i1.i649.32.extract.shift = lshr i512 %s151, 256
   %data.i1.i649.32.extract.trunc = trunc i512 %data.i1.i649.32.extract.shift to i64
@@ -76,7 +76,7 @@ entry:
   %data.i1.i649.8.extract.shift = lshr i512 %s151, 64
   %data.i1.i649.8.extract.trunc = trunc i512 %data.i1.i649.8.extract.shift to i64
   %s155 = insertelement <8 x i64> %s154, i64 %data.i1.i649.8.extract.trunc, i32 3
-  %arrayidx83 = getelementptr inbounds <8 x i64> * %dest, i32 7
+  %arrayidx83 = getelementptr inbounds <8 x i64>, <8 x i64> * %dest, i32 7
   store <8 x i64> %s155, <8 x i64> * %arrayidx83, align 64
   ret void
 }
diff --git a/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll b/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll
index 0e0537ec5bfc..d18dbd2db9b4 100644
--- a/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll
+++ b/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll
@@ -14,8 +14,8 @@ define void @printfn(i32 %a, i16 signext %b, double %C, i8 signext %E) {
 entry:
   %conv = sext i16 %b to i32
   %conv1 = sext i8 %E to i32
-  %call = tail call i32 (i8*, ...)* @printf(
-	i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), ; --> R0
+  %call = tail call i32 (i8*, ...) @printf(
+	i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), ; --> R0
         i32 %a,                                          ; --> R1
         i32 %conv,                                       ; --> R2
         double %C,                                       ; --> SP, NCRN := R4
diff --git a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll
index e79a3ba741ec..c93d2a2d34fb 100644
--- a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll
+++ b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll
@@ -21,11 +21,12 @@ define void @foo(double %vfp0,     ; --> D0,     NSAA=SP
 		 i32 %p2,          ; --> R3,     NSAA=SP+8 
                  i32 %p3) #0 {     ; --> SP+4,   NSAA=SP+12
 entry:
-  ;CHECK: sub sp, #8
-  ;CHECK: push.w {r11, lr}
-  ;CHECK: add r0, sp, #8
-  ;CHECK: str r2, [sp, #12]
-  ;CHECK: str r1, [sp, #8]
+  ;CHECK: sub sp, #12
+  ;CHECK: push {r7, lr}
+  ;CHECK: sub sp, #4
+  ;CHECK: add r0, sp, #12
+  ;CHECK: str r2, [sp, #16]
+  ;CHECK: str r1, [sp, #12]
   ;CHECK: bl  fooUseStruct
   call void @fooUseStruct(%st_t* %p1)
   ret void
diff --git a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll
index 212bbc2ee9c8..944a60c06107 100644
--- a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll
+++ b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll
@@ -19,7 +19,7 @@ define void @foo(double %vfp0,     ; --> D0,              NSAA=SP
 		 i32 %p2) #0 {     ; --> SP+24,           NSAA=SP+24 
                  
 entry:
-  ;CHECK:  push.w {r11, lr}
+  ;CHECK:  push {r7, lr}
   ;CHECK:  ldr    r0, [sp, #32]
   ;CHECK:  bl     fooUseI32
   call void @fooUseI32(i32 %p2)
diff --git a/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll b/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll
index efb82027b70d..aabbfae8b879 100644
--- a/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll
+++ b/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll
@@ -7,46 +7,46 @@ entry:
         %add = add nsw i32 %mul17, %w
         %sub19 = sub i32 %add, %Width
         %sub20 = add i32 %sub19, -1
-        %arrayidx21 = getelementptr inbounds i8* %call1, i32 %sub20
-        %0 = load i8* %arrayidx21, align 1
+        %arrayidx21 = getelementptr inbounds i8, i8* %call1, i32 %sub20
+        %0 = load i8, i8* %arrayidx21, align 1
         %conv22 = zext i8 %0 to i32
-        %arrayidx25 = getelementptr inbounds i8* %call1, i32 %sub19
-        %1 = load i8* %arrayidx25, align 1
+        %arrayidx25 = getelementptr inbounds i8, i8* %call1, i32 %sub19
+        %1 = load i8, i8* %arrayidx25, align 1
         %conv26 = zext i8 %1 to i32
         %mul23189 = add i32 %conv26, %conv22
         %add30 = add i32 %sub19, 1
-        %arrayidx31 = getelementptr inbounds i8* %call1, i32 %add30
-        %2 = load i8* %arrayidx31, align 1
+        %arrayidx31 = getelementptr inbounds i8, i8* %call1, i32 %add30
+        %2 = load i8, i8* %arrayidx31, align 1
         %conv32 = zext i8 %2 to i32
 ; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1]
 ; CHECK-NEXT: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #1]
         %add28190 = add i32 %mul23189, %conv32
         %sub35 = add i32 %add, -1
-        %arrayidx36 = getelementptr inbounds i8* %call1, i32 %sub35
-        %3 = load i8* %arrayidx36, align 1
+        %arrayidx36 = getelementptr inbounds i8, i8* %call1, i32 %sub35
+        %3 = load i8, i8* %arrayidx36, align 1
         %conv37 = zext i8 %3 to i32
         %add34191 = add i32 %add28190, %conv37
-        %arrayidx40 = getelementptr inbounds i8* %call1, i32 %add
-        %4 = load i8* %arrayidx40, align 1
+        %arrayidx40 = getelementptr inbounds i8, i8* %call1, i32 %add
+        %4 = load i8, i8* %arrayidx40, align 1
         %conv41 = zext i8 %4 to i32
         %mul42 = mul nsw i32 %conv41, 255
         %add44 = add i32 %add, 1
-        %arrayidx45 = getelementptr inbounds i8* %call1, i32 %add44
-        %5 = load i8* %arrayidx45, align 1
+        %arrayidx45 = getelementptr inbounds i8, i8* %call1, i32 %add44
+        %5 = load i8, i8* %arrayidx45, align 1
         %conv46 = zext i8 %5 to i32
 ; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1]
 ; CHECK-NEXT: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #1]
         %add49 = add i32 %add, %Width
         %sub50 = add i32 %add49, -1
-        %arrayidx51 = getelementptr inbounds i8* %call1, i32 %sub50
-        %6 = load i8* %arrayidx51, align 1
+        %arrayidx51 = getelementptr inbounds i8, i8* %call1, i32 %sub50
+        %6 = load i8, i8* %arrayidx51, align 1
         %conv52 = zext i8 %6 to i32
-        %arrayidx56 = getelementptr inbounds i8* %call1, i32 %add49
-        %7 = load i8* %arrayidx56, align 1
+        %arrayidx56 = getelementptr inbounds i8, i8* %call1, i32 %add49
+        %7 = load i8, i8* %arrayidx56, align 1
         %conv57 = zext i8 %7 to i32
         %add61 = add i32 %add49, 1
-        %arrayidx62 = getelementptr inbounds i8* %call1, i32 %add61
-        %8 = load i8* %arrayidx62, align 1
+        %arrayidx62 = getelementptr inbounds i8, i8* %call1, i32 %add61
+        %8 = load i8, i8* %arrayidx62, align 1
         %conv63 = zext i8 %8 to i32
 ; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1]
 ; CHECK-NEXT: ldrb{{[.w]*}} r{{[0-9]*}}, [r{{[0-9]*}}, #1]
@@ -58,7 +58,7 @@ entry:
         %add65 = add i32 %tmp196, %mul42
         %9 = lshr i32 %add65, 8
         %conv68 = trunc i32 %9 to i8
-        %arrayidx69 = getelementptr inbounds i8* %call3, i32 %add
+        %arrayidx69 = getelementptr inbounds i8, i8* %call3, i32 %add
         store i8 %conv68, i8* %arrayidx69, align 1
         ret i8 %conv68
 }
diff --git a/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll b/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll
index 7bf03a16c6fb..3c20c6b53633 100644
--- a/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll
+++ b/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll
@@ -4,7 +4,7 @@
 %struct.S227 = type { [49 x i32], i32 }
 
 define void @check227(
-                      i32 %b,                              
+                      i32 %b,
                       %struct.S227* byval nocapture %arg0,
                       %struct.S227* %arg1) {
 ; b --> R0
@@ -13,14 +13,16 @@ define void @check227(
 
 entry:
 
-;CHECK:  sub   sp, sp, #16
+;CHECK:  sub   sp, sp, #12
 ;CHECK:  push  {r11, lr}
+;CHECK:  sub   sp, sp, #4
 ;CHECK:  add   r0, sp, #12
 ;CHECK:  stm   r0, {r1, r2, r3}
 ;CHECK:  ldr   r0, [sp, #212]
 ;CHECK:  bl    useInt
+;CHECK:  add   sp, sp, #4
 ;CHECK:  pop   {r11, lr}
-;CHECK:  add   sp, sp, #16
+;CHECK:  add   sp, sp, #12
 
   %0 = ptrtoint %struct.S227* %arg1 to i32
   tail call void @useInt(i32 %0)
diff --git a/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll b/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll
index 0130f7ab68f5..617271264b4f 100644
--- a/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll
+++ b/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll
@@ -10,7 +10,7 @@ define arm_aapcscc void @f2(i8 signext %a) #0 {
 entry:
   %a.addr = alloca i8, align 1
   store i8 %a, i8* %a.addr, align 1
-  %0 = load i8* %a.addr, align 1
+  %0 = load i8, i8* %a.addr, align 1
   %conv = sext i8 %0 to i32
   %shr = ashr i32 %conv, 56
   %conv1 = trunc i32 %shr to i8
diff --git a/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll b/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
index 05a4ef05e958..979df3072fbf 100644
--- a/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
+++ b/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
@@ -17,7 +17,7 @@ entry:
 ; CHECK: vorr q9, q9, q10
 ; CHECK: vst1.32 {d18, d19}, [r0]
 vector.body:
-  %wide.load = load <4 x i32>* undef, align 4
+  %wide.load = load <4 x i32>, <4 x i32>* undef, align 4
   %0 = and <4 x i32> %wide.load, <i32 -16711936, i32 -16711936, i32 -16711936, i32 -16711936>
   %1 = sub <4 x i32> %wide.load, zeroinitializer
   %2 = and <4 x i32> %1, <i32 16711680, i32 16711680, i32 16711680, i32 16711680>
diff --git a/test/CodeGen/ARM/2013-10-11-select-stalls.ll b/test/CodeGen/ARM/2013-10-11-select-stalls.ll
index 33c0587226a8..d6045c7b8c8c 100644
--- a/test/CodeGen/ARM/2013-10-11-select-stalls.ll
+++ b/test/CodeGen/ARM/2013-10-11-select-stalls.ll
@@ -7,7 +7,7 @@ define <16 x i8> @multiselect(i32 %avail, i8* %foo, i8* %bar) {
 entry:
   %vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %foo, i32 1)
   %vld2 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %bar, i32 1)
-  %and = and i32 %avail, 1
+  %and = and i32 %avail, 3
   %tobool = icmp eq i32 %and, 0
   %retv = select i1 %tobool, <16 x i8> %vld1, <16 x i8> %vld2
   ret <16 x i8> %retv
diff --git a/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll b/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
index 6c0fbd00bd1a..ef575f4c41ec 100644
--- a/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
+++ b/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
@@ -4,7 +4,7 @@
 define void @vst(i8* %m, [4 x i64] %v) {
 entry:
 ; CHECK: vst:
-; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use>
+; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use,kill>
 
   %v0 = extractvalue [4 x i64] %v, 0
   %v1 = extractvalue [4 x i64] %v, 1
@@ -38,13 +38,13 @@ entry:
 define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
 ; CHECK: vtbx4:
 ; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use>
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load %struct.__neon_int8x8x4_t* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B
         %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
         %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
         %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
-	%tmp7 = load <8 x i8>* %C
+	%tmp7 = load <8 x i8>, <8 x i8>* %C
 	%tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
   call void @bar2(%struct.__neon_int8x8x4_t %tmp2, <8 x i8> %tmp8)
 	ret <8 x i8> %tmp8
diff --git a/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll b/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll
index 33bfa2fa61cd..5b2fc57359ad 100644
--- a/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll
+++ b/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll
@@ -13,15 +13,16 @@ declare void @usePtr(%struct8bytes8align*)
 ; c -> sp+0..sp+7
 define void @foo1(i32 %a, %struct12bytes* byval %b, i64 %c) {
 ; CHECK-LABEL: foo1
-; CHECK: sub  sp, sp, #16
+; CHECK: sub  sp, sp, #12
 ; CHECK: push  {r11, lr}
+; CHECK: sub sp, sp, #4
 ; CHECK: add  [[SCRATCH:r[0-9]+]], sp, #12
 ; CHECK: stm  [[SCRATCH]], {r1, r2, r3}
 ; CHECK: ldr  r0, [sp, #24]
 ; CHECK: ldr  r1, [sp, #28]
 ; CHECK: bl  useLong
 ; CHECK: pop  {r11, lr}
-; CHECK: add  sp, sp, #16
+; CHECK: add  sp, sp, #12
 
   call void @useLong(i64 %c)
   ret void
diff --git a/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll b/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll
index df7d2457e763..1abc40f2c16e 100644
--- a/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll
+++ b/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll
@@ -8,7 +8,7 @@ define i32* @earlyclobber-str-post(i32* %addr) nounwind {
 ; CHECK-NOT: str r[[REG:[0-9]+]], [r[[REG]]], #4
   %val = ptrtoint i32* %addr to i32
   store i32 %val, i32* %addr
-  %new = getelementptr i32* %addr, i32 1
+  %new = getelementptr i32, i32* %addr, i32 1
   ret i32* %new
 }
 
@@ -18,7 +18,7 @@ define i16* @earlyclobber-strh-post(i16* %addr) nounwind {
   %val = ptrtoint i16* %addr to i32
   %tr = trunc i32 %val to i16
   store i16 %tr, i16* %addr
-  %new = getelementptr i16* %addr, i32 1
+  %new = getelementptr i16, i16* %addr, i32 1
   ret i16* %new
 }
 
@@ -28,6 +28,6 @@ define i8* @earlyclobber-strb-post(i8* %addr) nounwind {
   %val = ptrtoint i8* %addr to i32
   %tr = trunc i32 %val to i8
   store i8 %tr, i8* %addr
-  %new = getelementptr i8* %addr, i32 1
+  %new = getelementptr i8, i8* %addr, i32 1
   ret i8* %new
 }
diff --git a/test/CodeGen/ARM/2014-08-04-muls-it.ll b/test/CodeGen/ARM/2014-08-04-muls-it.ll
index 4636bff880a8..5ba1347433db 100644
--- a/test/CodeGen/ARM/2014-08-04-muls-it.ll
+++ b/test/CodeGen/ARM/2014-08-04-muls-it.ll
@@ -17,9 +17,7 @@ if.end:                                           ; preds = %if.then, %entry
 
 ; CHECK-LABEL: function
 ; CHECK: cmp r0, r1
-; CHECK: bne [[LABEL:[.*]]]
 ; CHECK-NOT: mulseq r0, r0, r0
-; CHECK: [[LABEL]]
-; CHECK: muls r0, r0, r0
+; CHECK: muleq r0, r0, r0
 ; CHECK: bx lr
 
diff --git a/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll b/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll
index f3cc3d82121f..2efd91f503e5 100644
--- a/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll
+++ b/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll
@@ -1,55 +1,48 @@
 ; RUN: llc -mtriple=thumbv4t-none--eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V4T
 ; RUN: llc -mtriple=thumbv6m-none--eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V6M
 
-; CHECK-LABEL: foo
-define i32 @foo(i32 %z, ...) #0 {
-entry:
-  %a = alloca i32, align 4
-  %b = alloca i32, align 4
-  %c = alloca i32, align 4
-  %d = alloca i32, align 4
-  %e = alloca i32, align 4
-  %f = alloca i32, align 4
-  %g = alloca i32, align 4
-  %h = alloca i32, align 4
-
-  store i32 1, i32* %a, align 4
-  store i32 2, i32* %b, align 4
-  store i32 3, i32* %c, align 4
-  store i32 4, i32* %d, align 4
-  store i32 5, i32* %e, align 4
-  store i32 6, i32* %f, align 4
-  store i32 7, i32* %g, align 4
-  store i32 8, i32* %h, align 4
-
-  %0 = load i32* %a, align 4
-  %1 = load i32* %b, align 4
-  %2 = load i32* %c, align 4
-  %3 = load i32* %d, align 4
-  %4 = load i32* %e, align 4
-  %5 = load i32* %f, align 4
-  %6 = load i32* %g, align 4
-  %7 = load i32* %h, align 4
-
-  %add  = add nsw i32 %0, %1
-  %add4 = add nsw i32 %add, %2
-  %add5 = add nsw i32 %add4, %3
-  %add6 = add nsw i32 %add5, %4
-  %add7 = add nsw i32 %add6, %5
-  %add8 = add nsw i32 %add7, %6
-  %add9 = add nsw i32 %add8, %7
-
-  %addz = add nsw i32 %add9, %z
-  call void @llvm.va_start(i8* null)
-  ret i32 %addz
-
-; CHECK:      sub sp, #40
-; CHECK-NEXT: add [[BASE:r[0-9]]], sp, #8
-
-; CHECK-V4T:  movs [[NEWBASE:r[0-9]]], [[BASE]]
-; CHECK-V6M:  mov [[NEWBASE:r[0-9]]], [[BASE]]
-; CHECK-NEXT: adds [[NEWBASE]], #8
+; CHECK-LABEL: test1
+define i32 @test1(i32* %p) {
+
+; Offsets less than 8 can be generated in a single add
+; CHECK: adds [[NEWBASE:r[0-9]]], r0, #4
+  %1 = getelementptr inbounds i32, i32* %p, i32 1
+  %2 = getelementptr inbounds i32, i32* %p, i32 2
+  %3 = getelementptr inbounds i32, i32* %p, i32 3
+  %4 = getelementptr inbounds i32, i32* %p, i32 4
+
 ; CHECK-NEXT: ldm [[NEWBASE]],
+  %5 = load i32, i32* %1, align 4
+  %6 = load i32, i32* %2, align 4
+  %7 = load i32, i32* %3, align 4
+  %8 = load i32, i32* %4, align 4
+
+  %9 = add nsw i32 %5, %6
+  %10 = add nsw i32 %9, %7
+  %11 = add nsw i32 %10, %8
+  ret i32 %11
 }
 
-declare void @llvm.va_start(i8*) nounwind
+; CHECK-LABEL: test2
+define i32 @test2(i32* %p) {
+
+; Offsets >=8 require a mov and an add
+; CHECK-V4T:  movs [[NEWBASE:r[0-9]]], r0
+; CHECK-V6M:  mov [[NEWBASE:r[0-9]]], r0
+; CHECK-NEXT: adds [[NEWBASE]], #8
+  %1 = getelementptr inbounds i32, i32* %p, i32 2
+  %2 = getelementptr inbounds i32, i32* %p, i32 3
+  %3 = getelementptr inbounds i32, i32* %p, i32 4
+  %4 = getelementptr inbounds i32, i32* %p, i32 5
+
+; CHECK-NEXT: ldm [[NEWBASE]],
+  %5 = load i32, i32* %1, align 4
+  %6 = load i32, i32* %2, align 4
+  %7 = load i32, i32* %3, align 4
+  %8 = load i32, i32* %4, align 4
+
+  %9 = add nsw i32 %5, %6
+  %10 = add nsw i32 %9, %7
+  %11 = add nsw i32 %10, %8
+  ret i32 %11
+}
diff --git a/test/CodeGen/ARM/MergeConsecutiveStores.ll b/test/CodeGen/ARM/MergeConsecutiveStores.ll
index 06c87e986a83..3f7d625244bd 100644
--- a/test/CodeGen/ARM/MergeConsecutiveStores.ll
+++ b/test/CodeGen/ARM/MergeConsecutiveStores.ll
@@ -12,17 +12,17 @@ define void @MergeLoadStoreBaseIndexOffset(i32* %a, i8* %b, i8* %c, i32 %n) {
   %.09 = phi i32 [ %n, %0 ], [ %11, %1 ]
   %.08 = phi i8* [ %b, %0 ], [ %10, %1 ]
   %.0 = phi i32* [ %a, %0 ], [ %2, %1 ]
-  %2 = getelementptr inbounds i32* %.0, i32 1
-  %3 = load i32* %.0, align 1
-  %4 = getelementptr inbounds i8* %c, i32 %3
-  %5 = load i8* %4, align 1
+  %2 = getelementptr inbounds i32, i32* %.0, i32 1
+  %3 = load i32, i32* %.0, align 1
+  %4 = getelementptr inbounds i8, i8* %c, i32 %3
+  %5 = load i8, i8* %4, align 1
   %6 = add i32 %3, 1
-  %7 = getelementptr inbounds i8* %c, i32 %6
-  %8 = load i8* %7, align 1
+  %7 = getelementptr inbounds i8, i8* %c, i32 %6
+  %8 = load i8, i8* %7, align 1
   store i8 %5, i8* %.08, align 1
-  %9 = getelementptr inbounds i8* %.08, i32 1
+  %9 = getelementptr inbounds i8, i8* %.08, i32 1
   store i8 %8, i8* %9, align 1
-  %10 = getelementptr inbounds i8* %.08, i32 2
+  %10 = getelementptr inbounds i8, i8* %.08, i32 2
   %11 = add nsw i32 %.09, -1
   %12 = icmp eq i32 %11, 0
   br i1 %12, label %13, label %1
@@ -44,18 +44,18 @@ define void @MergeLoadStoreBaseIndexOffsetSext(i8* %a, i8* %b, i8* %c, i32 %n) {
   %.09 = phi i32 [ %n, %0 ], [ %12, %1 ]
   %.08 = phi i8* [ %b, %0 ], [ %11, %1 ]
   %.0 = phi i8* [ %a, %0 ], [ %2, %1 ]
-  %2 = getelementptr inbounds i8* %.0, i32 1
-  %3 = load i8* %.0, align 1
+  %2 = getelementptr inbounds i8, i8* %.0, i32 1
+  %3 = load i8, i8* %.0, align 1
   %4 = sext i8 %3 to i32
-  %5 = getelementptr inbounds i8* %c, i32 %4
-  %6 = load i8* %5, align 1
+  %5 = getelementptr inbounds i8, i8* %c, i32 %4
+  %6 = load i8, i8* %5, align 1
   %7 = add i32 %4, 1
-  %8 = getelementptr inbounds i8* %c, i32 %7
-  %9 = load i8* %8, align 1
+  %8 = getelementptr inbounds i8, i8* %c, i32 %7
+  %9 = load i8, i8* %8, align 1
   store i8 %6, i8* %.08, align 1
-  %10 = getelementptr inbounds i8* %.08, i32 1
+  %10 = getelementptr inbounds i8, i8* %.08, i32 1
   store i8 %9, i8* %10, align 1
-  %11 = getelementptr inbounds i8* %.08, i32 2
+  %11 = getelementptr inbounds i8, i8* %.08, i32 2
   %12 = add nsw i32 %.09, -1
   %13 = icmp eq i32 %12, 0
   br i1 %13, label %14, label %1
@@ -76,19 +76,19 @@ define void @loadStoreBaseIndexOffsetSextNoSex(i8* %a, i8* %b, i8* %c, i32 %n) {
   %.09 = phi i32 [ %n, %0 ], [ %12, %1 ]
   %.08 = phi i8* [ %b, %0 ], [ %11, %1 ]
   %.0 = phi i8* [ %a, %0 ], [ %2, %1 ]
-  %2 = getelementptr inbounds i8* %.0, i32 1
-  %3 = load i8* %.0, align 1
+  %2 = getelementptr inbounds i8, i8* %.0, i32 1
+  %3 = load i8, i8* %.0, align 1
   %4 = sext i8 %3 to i32
-  %5 = getelementptr inbounds i8* %c, i32 %4
-  %6 = load i8* %5, align 1
+  %5 = getelementptr inbounds i8, i8* %c, i32 %4
+  %6 = load i8, i8* %5, align 1
   %7 = add i8 %3, 1
   %wrap.4 = sext i8 %7 to i32
-  %8 = getelementptr inbounds i8* %c, i32 %wrap.4
-  %9 = load i8* %8, align 1
+  %8 = getelementptr inbounds i8, i8* %c, i32 %wrap.4
+  %9 = load i8, i8* %8, align 1
   store i8 %6, i8* %.08, align 1
-  %10 = getelementptr inbounds i8* %.08, i32 1
+  %10 = getelementptr inbounds i8, i8* %.08, i32 1
   store i8 %9, i8* %10, align 1
-  %11 = getelementptr inbounds i8* %.08, i32 2
+  %11 = getelementptr inbounds i8, i8* %.08, i32 2
   %12 = add nsw i32 %.09, -1
   %13 = icmp eq i32 %12, 0
   br i1 %13, label %14, label %1
diff --git a/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll b/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll
index a82f6141dbb3..a314259e499e 100644
--- a/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll
+++ b/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll
@@ -10,10 +10,10 @@ entry:
   %i.addr = alloca i32, align 4
   %buffer = alloca [4096 x i8], align 1
   store i32 %i, i32* %i.addr, align 4
-  %0 = load i32* %i.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
   %rem = urem i32 %0, 4096
-  %arrayidx = getelementptr inbounds [4096 x i8]* %buffer, i32 0, i32 %rem
-  %1 = load volatile i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 %rem
+  %1 = load volatile i8, i8* %arrayidx, align 1
   ret i8 %1
 }
 
diff --git a/test/CodeGen/ARM/Windows/dllimport.ll b/test/CodeGen/ARM/Windows/dllimport.ll
index bc737bd41827..6786be3322e3 100644
--- a/test/CodeGen/ARM/Windows/dllimport.ll
+++ b/test/CodeGen/ARM/Windows/dllimport.ll
@@ -8,7 +8,7 @@ declare dllimport arm_aapcs_vfpcc i32 @external()
 declare arm_aapcs_vfpcc i32 @internal()
 
 define arm_aapcs_vfpcc i32 @get_var() {
-  %1 = load i32* @var, align 4
+  %1 = load i32, i32* @var, align 4
   ret i32 %1
 }
 
@@ -20,7 +20,7 @@ define arm_aapcs_vfpcc i32 @get_var() {
 ; CHECK: bx lr
 
 define arm_aapcs_vfpcc i32 @get_ext() {
-  %1 = load i32* @ext, align 4
+  %1 = load i32, i32* @ext, align 4
   ret i32 %1
 }
 
diff --git a/test/CodeGen/ARM/Windows/frame-register.ll b/test/CodeGen/ARM/Windows/frame-register.ll
index 31167d7352e3..7ecfc1a71714 100644
--- a/test/CodeGen/ARM/Windows/frame-register.ll
+++ b/test/CodeGen/ARM/Windows/frame-register.ll
@@ -8,12 +8,12 @@ entry:
   %i.addr = alloca i32, align 4
   %j = alloca i32, align 4
   store i32 %i, i32* %i.addr, align 4
-  %0 = load i32* %i.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
   %add = add nsw i32 %0, 1
   store i32 %add, i32* %j, align 4
-  %1 = load i32* %j, align 4
+  %1 = load i32, i32* %j, align 4
   call void @callee(i32 %1)
-  %2 = load i32* %j, align 4
+  %2 = load i32, i32* %j, align 4
   %add1 = add nsw i32 %2, 1
   ret i32 %add1
 }
diff --git a/test/CodeGen/ARM/Windows/long-calls.ll b/test/CodeGen/ARM/Windows/long-calls.ll
index e35f414579af..21c95fac91c5 100644
--- a/test/CodeGen/ARM/Windows/long-calls.ll
+++ b/test/CodeGen/ARM/Windows/long-calls.ll
@@ -10,7 +10,7 @@ entry:
 }
 
 ; CHECK-LABEL: caller
-; CHECK: ldr [[REG:r[0-9]+]], [[CPI:.LCPI[_0-9]+]]
+; CHECK: ldr [[REG:r[0-9]+]], [[CPI:LCPI[_0-9]+]]
 ; CHECK: bx [[REG]]
 ; CHECK: .align 2
 ; CHECK: [[CPI]]:
diff --git a/test/CodeGen/ARM/Windows/movw-movt-relocations.ll b/test/CodeGen/ARM/Windows/movw-movt-relocations.ll
index 3ae6428d3a6b..c21aee087cf4 100644
--- a/test/CodeGen/ARM/Windows/movw-movt-relocations.ll
+++ b/test/CodeGen/ARM/Windows/movw-movt-relocations.ll
@@ -10,8 +10,8 @@
 ; Function Attrs: nounwind optsize readonly
 define i32 @relocation(i32 %j, i32 %k) {
 entry:
-  %0 = load i32* @i, align 4
-  %1 = load i32* @j, align 4
+  %0 = load i32, i32* @i, align 4
+  %1 = load i32, i32* @j, align 4
   %add = add nsw i32 %1, %0
   ret i32 %add
 }
diff --git a/test/CodeGen/ARM/Windows/pic.ll b/test/CodeGen/ARM/Windows/pic.ll
index 28d371f45217..9ef7c35c5530 100644
--- a/test/CodeGen/ARM/Windows/pic.ll
+++ b/test/CodeGen/ARM/Windows/pic.ll
@@ -5,7 +5,7 @@
 
 define arm_aapcs_vfpcc i8 @return_external() {
 entry:
-  %0 = load i8* @external, align 1
+  %0 = load i8, i8* @external, align 1
   ret i8 %0
 }
 
diff --git a/test/CodeGen/ARM/Windows/read-only-data.ll b/test/CodeGen/ARM/Windows/read-only-data.ll
index 0438d68b55c6..c387d1d5137c 100644
--- a/test/CodeGen/ARM/Windows/read-only-data.ll
+++ b/test/CodeGen/ARM/Windows/read-only-data.ll
@@ -6,7 +6,7 @@ declare arm_aapcs_vfpcc void @callee(i8*)
 
 define arm_aapcs_vfpcc void @function() {
 entry:
-  call arm_aapcs_vfpcc void @callee(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0))
+  call arm_aapcs_vfpcc void @callee(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0))
   ret void
 }
 
diff --git a/test/CodeGen/ARM/Windows/stack-probe-non-default.ll b/test/CodeGen/ARM/Windows/stack-probe-non-default.ll
new file mode 100644
index 000000000000..d66e93ad34ee
--- /dev/null
+++ b/test/CodeGen/ARM/Windows/stack-probe-non-default.ll
@@ -0,0 +1,27 @@
+; RUN: llc -mtriple thumbv7-windows -mcpu cortex-a9 -o - %s \
+; RUN:     | FileCheck %s -check-prefix CHECK-DEFAULT-CODE-MODEL
+
+; RUN: llc -mtriple thumbv7-windows -mcpu cortex-a9 -code-model large -o - %s \
+; RUN:     | FileCheck %s -check-prefix CHECK-LARGE-CODE-MODEL
+
+declare dllimport arm_aapcs_vfpcc void @initialise(i8*)
+
+define dllexport arm_aapcs_vfpcc signext i8 @function(i32 %offset) #0 {
+entry:
+  %buffer = alloca [4096 x i8], align 1
+  %0 = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 0
+  call arm_aapcs_vfpcc void @initialise(i8* %0)
+  %arrayidx = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 %offset
+  %1 = load i8, i8* %arrayidx, align 1
+  ret i8 %1
+}
+
+attributes #0 = { "stack-probe-size"="8096" }
+
+; CHECK-DEFAULT-CODE-MODEL-NOT: __chkstk
+; CHECK-DEFAULT-CODE-MODEL: sub.w sp, sp, #4096
+
+; CHECK-LARGE-CODE-MODEL-NOT: movw r12, :lower16:__chkstk
+; CHECK-LARGE-CODE-MODEL-NOT: movt r12, :upper16:__chkstk
+; CHECK-LARGE-CODE-MODEL: sub.w sp, sp, #4096
+
diff --git a/test/CodeGen/ARM/Windows/vla.ll b/test/CodeGen/ARM/Windows/vla.ll
index 56901dee0dfa..1c0632e25e55 100644
--- a/test/CodeGen/ARM/Windows/vla.ll
+++ b/test/CodeGen/ARM/Windows/vla.ll
@@ -8,8 +8,8 @@
 define arm_aapcs_vfpcc i8 @function(i32 %sz, i32 %idx) {
 entry:
   %vla = alloca i8, i32 %sz, align 1
-  %arrayidx = getelementptr inbounds i8* %vla, i32 %idx
-  %0 = load volatile i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %vla, i32 %idx
+  %0 = load volatile i8, i8* %arrayidx, align 1
   ret i8 %0
 }
 
diff --git a/test/CodeGen/ARM/a15-partial-update.ll b/test/CodeGen/ARM/a15-partial-update.ll
index 5747253d56b7..576eb7a24393 100644
--- a/test/CodeGen/ARM/a15-partial-update.ll
+++ b/test/CodeGen/ARM/a15-partial-update.ll
@@ -10,7 +10,7 @@ define <2 x float> @t1(float* %A, <2 x float> %B) {
 ; generated.
 
 ; CHECK-NOT: vmov.{{.*}} d{{[0-9]+}},
-  %tmp2 = load float* %A, align 4
+  %tmp2 = load float, float* %A, align 4
   %tmp3 = insertelement <2 x float> %B, float %tmp2, i32 1
   ret <2 x float> %tmp3
 }
@@ -27,9 +27,9 @@ loop:
 ; CHECK: vmov.{{.*}} d{{[0-9]+}},
   %oldcount = phi i32 [0, %entry], [%newcount, %loop]
   %newcount = add i32 %oldcount, 1
-  %p1 = getelementptr <4 x i8> *%in, i32 %newcount
-  %p2 = getelementptr <4 x i8> *%out, i32 %newcount
-  %tmp1 = load <4 x i8> *%p1, align 4
+  %p1 = getelementptr <4 x i8>, <4 x i8> *%in, i32 %newcount
+  %p2 = getelementptr <4 x i8>, <4 x i8> *%out, i32 %newcount
+  %tmp1 = load <4 x i8> , <4 x i8> *%p1, align 4
   store <4 x i8> %tmp1, <4 x i8> *%p2
   %cmp = icmp eq i32 %newcount, %n
   br i1 %cmp, label %loop, label %ret
diff --git a/test/CodeGen/ARM/addrmode.ll b/test/CodeGen/ARM/addrmode.ll
index 8fd1da791f1f..52bb9a20662e 100644
--- a/test/CodeGen/ARM/addrmode.ll
+++ b/test/CodeGen/ARM/addrmode.ll
@@ -4,14 +4,14 @@
 define i32 @t1(i32 %a) {
 	%b = mul i32 %a, 9
         %c = inttoptr i32 %b to i32*
-        %d = load i32* %c
+        %d = load i32, i32* %c
 	ret i32 %d
 }
 
 define i32 @t2(i32 %a) {
 	%b = mul i32 %a, -7
         %c = inttoptr i32 %b to i32*
-        %d = load i32* %c
+        %d = load i32, i32* %c
 	ret i32 %d
 }
 
diff --git a/test/CodeGen/ARM/aggregate-padding.ll b/test/CodeGen/ARM/aggregate-padding.ll
new file mode 100644
index 000000000000..bc46a9cdf913
--- /dev/null
+++ b/test/CodeGen/ARM/aggregate-padding.ll
@@ -0,0 +1,101 @@
+; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s
+
+; [2 x i64] should be contiguous when split (e.g. we shouldn't try to align all
+; i32 components to 64 bits). Also makes sure i64 based types are properly
+; aligned on the stack.
+define i64 @test_i64_contiguous_on_stack([8 x double], float, i32 %in, [2 x i64] %arg) nounwind {
+; CHECK-LABEL: test_i64_contiguous_on_stack:
+; CHECK-DAG: ldr [[LO0:r[0-9]+]], [sp, #8]
+; CHECK-DAG: ldr [[HI0:r[0-9]+]], [sp, #12]
+; CHECK-DAG: ldr [[LO1:r[0-9]+]], [sp, #16]
+; CHECK-DAG: ldr [[HI1:r[0-9]+]], [sp, #20]
+; CHECK: adds r0, [[LO0]], [[LO1]]
+; CHECK: adc r1, [[HI0]], [[HI1]]
+
+  %val1 = extractvalue [2 x i64] %arg, 0
+  %val2 = extractvalue [2 x i64] %arg, 1
+  %sum = add i64 %val1, %val2
+  ret i64 %sum
+}
+
+; [2 x i64] should try to use looks for 4 regs, not 8 (which might happen if the
+; i64 -> i32, i32 split wasn't handled correctly).
+define i64 @test_2xi64_uses_4_regs([8 x double], float, [2 x i64] %arg) nounwind {
+; CHECK-LABEL: test_2xi64_uses_4_regs:
+; CHECK-DAG: mov r0, r2
+; CHECK-DAG: mov r1, r3
+
+  %val = extractvalue [2 x i64] %arg, 1
+  ret i64 %val
+}
+
+; An aggregate should be able to split between registers and stack if there is
+; nothing else on the stack.
+define i32 @test_aggregates_split([8 x double], i32, [4 x i32] %arg) nounwind {
+; CHECK-LABEL: test_aggregates_split:
+; CHECK: ldr [[VAL3:r[0-9]+]], [sp]
+; CHECK: add r0, r1, [[VAL3]]
+
+  %val0 = extractvalue [4 x i32] %arg, 0
+  %val3 = extractvalue [4 x i32] %arg, 3
+  %sum = add i32 %val0, %val3
+  ret i32 %sum
+}
+
+; If an aggregate has to be moved entirely onto the stack, nothing should be
+; able to use r0-r3 any more. Also checks that [2 x i64] properly aligned when
+; it uses regs.
+define i32 @test_no_int_backfilling([8 x double], float, i32, [2 x i64], i32 %arg) nounwind {
+; CHECK-LABEL: test_no_int_backfilling:
+; CHECK: ldr r0, [sp, #24]
+  ret i32 %arg
+}
+
+; Even if the argument was successfully allocated as reg block, there should be
+; no backfillig to r1.
+define i32 @test_no_int_backfilling_regsonly(i32, [1 x i64], i32 %arg) {
+; CHECK-LABEL: test_no_int_backfilling_regsonly:
+; CHECK: ldr r0, [sp]
+  ret i32 %arg
+}
+
+; If an aggregate has to be moved entirely onto the stack, nothing should be
+; able to use r0-r3 any more.
+define float @test_no_float_backfilling([7 x double], [4 x i32], i32, [4 x double], float %arg) nounwind {
+; CHECK-LABEL: test_no_float_backfilling:
+; CHECK: vldr s0, [sp, #40]
+  ret float %arg
+}
+
+; They're a bit pointless, but types like [N x i8] should work as well.
+define i8 @test_i8_in_regs(i32, [3 x i8] %arg) {
+; CHECK-LABEL: test_i8_in_regs:
+; CHECK: add r0, r1, r3
+  %val0 = extractvalue [3 x i8] %arg, 0
+  %val2 = extractvalue [3 x i8] %arg, 2
+  %sum = add i8 %val0, %val2
+  ret i8 %sum
+}
+
+define i16 @test_i16_split(i32, i32, [3 x i16] %arg) {
+; CHECK-LABEL: test_i16_split:
+; CHECK: ldrh [[VAL2:r[0-9]+]], [sp]
+; CHECK: add r0, r2, [[VAL2]]
+  %val0 = extractvalue [3 x i16] %arg, 0
+  %val2 = extractvalue [3 x i16] %arg, 2
+  %sum = add i16 %val0, %val2
+  ret i16 %sum
+}
+
+; Beware: on the stack each i16 still gets a 32-bit slot, the array is not
+; packed.
+define i16 @test_i16_forced_stack([8 x double], double, i32, i32, [3 x i16] %arg) {
+; CHECK-LABEL: test_i16_forced_stack:
+; CHECK-DAG: ldrh [[VAL0:r[0-9]+]], [sp, #8]
+; CHECK-DAG: ldrh [[VAL2:r[0-9]+]], [sp, #16]
+; CHECK: add r0, [[VAL0]], [[VAL2]]
+  %val0 = extractvalue [3 x i16] %arg, 0
+  %val2 = extractvalue [3 x i16] %arg, 2
+  %sum = add i16 %val0, %val2
+  ret i16 %sum
+}
diff --git a/test/CodeGen/ARM/aliases.ll b/test/CodeGen/ARM/aliases.ll
index 5a737ad995ac..04ca3e875487 100644
--- a/test/CodeGen/ARM/aliases.ll
+++ b/test/CodeGen/ARM/aliases.ll
@@ -33,12 +33,12 @@ define i32 @foo_f() {
 
 define i32 @test() {
 entry:
-   %tmp = load i32* @foo1
-   %tmp1 = load i32* @foo2
-   %tmp0 = load i32* @bar_i
+   %tmp = load i32, i32* @foo1
+   %tmp1 = load i32, i32* @foo2
+   %tmp0 = load i32, i32* @bar_i
    %tmp2 = call i32 @foo_f()
    %tmp3 = add i32 %tmp, %tmp2
-   %tmp4 = call %FunTy* @bar_f()
+   %tmp4 = call i32 @bar_f()
    %tmp5 = add i32 %tmp3, %tmp4
    %tmp6 = add i32 %tmp1, %tmp5
    %tmp7 = add i32 %tmp6, %tmp0
diff --git a/test/CodeGen/ARM/alloc-no-stack-realign.ll b/test/CodeGen/ARM/alloc-no-stack-realign.ll
index 24c28baff881..600fb6aa44b1 100644
--- a/test/CodeGen/ARM/alloc-no-stack-realign.ll
+++ b/test/CodeGen/ARM/alloc-no-stack-realign.ll
@@ -9,8 +9,8 @@
 define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" {
 entry:
 ; NO-REALIGN-LABEL: test1
-; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
-; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
+; NO-REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]
+; NO-REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
 ; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
 ; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
@@ -21,21 +21,19 @@ entry:
 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
-; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
-; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
+; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]!
 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
 
 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0:0]], #48
 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0]], #32
 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
-; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
-; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
+; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!
 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
  %retval = alloca <16 x float>, align 16
- %0 = load <16 x float>* @T3_retval, align 16
+ %0 = load <16 x float>, <16 x float>* @T3_retval, align 16
  store <16 x float> %0, <16 x float>* %retval
- %1 = load <16 x float>* %retval
+ %1 = load <16 x float>, <16 x float>* %retval
  store <16 x float> %1, <16 x float>* %agg.result, align 16
  ret void
 }
@@ -44,8 +42,8 @@ define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp {
 entry:
 ; REALIGN-LABEL: test2
 ; REALIGN: bfc sp, #0, #6
-; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
-; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
+; REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]
+; REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
 ; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
 ; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
 ; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
@@ -65,13 +63,12 @@ entry:
 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
 ; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #32
 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
-; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #16
-; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
+; REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!
 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
  %retval = alloca <16 x float>, align 16
- %0 = load <16 x float>* @T3_retval, align 16
+ %0 = load <16 x float>, <16 x float>* @T3_retval, align 16
  store <16 x float> %0, <16 x float>* %retval
- %1 = load <16 x float>* %retval
+ %1 = load <16 x float>, <16 x float>* %retval
  store <16 x float> %1, <16 x float>* %agg.result, align 16
  ret void
 }
diff --git a/test/CodeGen/ARM/arguments.ll b/test/CodeGen/ARM/arguments.ll
index e7fbf9f28eff..3b1d8dd09153 100644
--- a/test/CodeGen/ARM/arguments.ll
+++ b/test/CodeGen/ARM/arguments.ll
@@ -18,7 +18,7 @@ define i32 @f2() nounwind optsize {
 ; DARWIN-LABEL: f2:
 ; DARWIN: mov	r3, #128
 entry:
-  %0 = tail call i32 (i32, ...)* @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; <i32> [#uses=1]
+  %0 = tail call i32 (i32, ...) @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; <i32> [#uses=1]
   %not. = icmp ne i32 %0, 128                     ; <i1> [#uses=1]
   %.0 = zext i1 %not. to i32                      ; <i32> [#uses=1]
   ret i32 %.0
diff --git a/test/CodeGen/ARM/arm-and-tst-peephole.ll b/test/CodeGen/ARM/arm-and-tst-peephole.ll
index 14eef832e693..04eae8f9afec 100644
--- a/test/CodeGen/ARM/arm-and-tst-peephole.ll
+++ b/test/CodeGen/ARM/arm-and-tst-peephole.ll
@@ -8,12 +8,12 @@
 
 %struct.Foo = type { i8* }
 
-; ARM:   foo
-; THUMB: foo
-; T2:    foo
+; ARM-LABEL:   foo:
+; THUMB-LABEL: foo:
+; T2-LABEL:    foo:
 define %struct.Foo* @foo(%struct.Foo* %this, i32 %acc) nounwind readonly align 2 {
 entry:
-  %scevgep = getelementptr %struct.Foo* %this, i32 1
+  %scevgep = getelementptr %struct.Foo, %struct.Foo* %this, i32 1
   br label %tailrecurse
 
 tailrecurse:                                      ; preds = %sw.bb, %entry
@@ -21,8 +21,8 @@ tailrecurse:                                      ; preds = %sw.bb, %entry
   %lsr.iv = phi i32 [ %lsr.iv.next, %sw.bb ], [ 1, %entry ]
   %acc.tr = phi i32 [ %or, %sw.bb ], [ %acc, %entry ]
   %lsr.iv24 = bitcast %struct.Foo* %lsr.iv2 to i8**
-  %scevgep5 = getelementptr i8** %lsr.iv24, i32 -1
-  %tmp2 = load i8** %scevgep5
+  %scevgep5 = getelementptr i8*, i8** %lsr.iv24, i32 -1
+  %tmp2 = load i8*, i8** %scevgep5
   %0 = ptrtoint i8* %tmp2 to i32
 
 ; ARM:      ands {{r[0-9]+}}, {{r[0-9]+}}, #3
@@ -49,20 +49,20 @@ tailrecurse.switch:                               ; preds = %tailrecurse
 ; V8-NEXT: beq
 ; V8-NEXT: %tailrecurse.switch
 ; V8: cmp
-; V8-NEXT: beq
+; V8-NEXT: bne
 ; V8-NEXT: b	
 ; The trailing space in the last line checks that the branch is unconditional
   switch i32 %and, label %sw.epilog [
     i32 1, label %sw.bb
     i32 3, label %sw.bb6
     i32 2, label %sw.bb8
-  ]
+  ], !prof !1
 
 sw.bb:                                            ; preds = %tailrecurse.switch, %tailrecurse
   %shl = shl i32 %acc.tr, 1
   %or = or i32 %and, %shl
   %lsr.iv.next = add i32 %lsr.iv, 1
-  %scevgep3 = getelementptr %struct.Foo* %lsr.iv2, i32 1
+  %scevgep3 = getelementptr %struct.Foo, %struct.Foo* %lsr.iv2, i32 1
   br label %tailrecurse
 
 sw.bb6:                                           ; preds = %tailrecurse.switch
@@ -70,7 +70,7 @@ sw.bb6:                                           ; preds = %tailrecurse.switch
 
 sw.bb8:                                           ; preds = %tailrecurse.switch
   %tmp1 = add i32 %acc.tr, %lsr.iv
-  %add.ptr11 = getelementptr inbounds %struct.Foo* %this, i32 %tmp1
+  %add.ptr11 = getelementptr inbounds %struct.Foo, %struct.Foo* %this, i32 %tmp1
   ret %struct.Foo* %add.ptr11
 
 sw.epilog:                                        ; preds = %tailrecurse.switch
@@ -83,14 +83,14 @@ sw.epilog:                                        ; preds = %tailrecurse.switch
 
 %struct.S = type { i8* (i8*)*, [1 x i8] }
 
-; ARM: bar
-; THUMB: bar
-; T2: bar
+; ARM-LABEL: bar:
+; THUMB-LABEL: bar:
+; T2-LABEL: bar:
 ; V8-LABEL: bar:
 define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly {
 entry:
-  %0 = getelementptr inbounds %struct.S* %x, i32 0, i32 1, i32 0
-  %1 = load i8* %0, align 1
+  %0 = getelementptr inbounds %struct.S, %struct.S* %x, i32 0, i32 1, i32 0
+  %1 = load i8, i8* %0, align 1
   %2 = zext i8 %1 to i32
 ; ARM: ands
 ; THUMB: ands
@@ -103,8 +103,8 @@ entry:
 
 bb:                                               ; preds = %entry
 ; V8-NEXT: %bb
-  %5 = getelementptr inbounds %struct.S* %y, i32 0, i32 1, i32 0
-  %6 = load i8* %5, align 1
+  %5 = getelementptr inbounds %struct.S, %struct.S* %y, i32 0, i32 1, i32 0
+  %6 = load i8, i8* %5, align 1
   %7 = zext i8 %6 to i32
 ; ARM: andsne
 ; THUMB: ands
@@ -134,3 +134,27 @@ bb4:                                              ; preds = %bb2
 return:                                           ; preds = %bb2, %bb, %entry
   ret i8 1
 }
+
+
+; We were looking through multiple COPY instructions to find an AND we might
+; fold into a TST, but in doing so we changed the register being tested allowing
+; folding of unrelated tests (in this case, a TST against r1 was eliminated in
+; favour of an AND of r0).
+
+; ARM-LABEL: test_tst_assessment:
+; THUMB-LABEL: test_tst_assessment:
+; T2-LABEL: test_tst_assessment:
+; V8-LABEL: test_tst_assessment:
+define i32 @test_tst_assessment(i1 %lhs, i1 %rhs) {
+  %lhs32 = zext i1 %lhs to i32
+  %rhs32 = zext i1 %rhs to i32
+  %diff = sub nsw i32 %lhs32, %rhs32
+; ARM: tst r1, #1
+; THUMB: movs [[RTMP:r[0-9]+]], #1
+; THUMB: tst r1, [[RTMP]]
+; T2: tst.w r1, #1
+; V8: tst.w r1, #1
+  ret i32 %diff
+}
+
+!1 = !{!"branch_weights", i32 1, i32 1, i32 3, i32 2 }
diff --git a/test/CodeGen/ARM/arm-asm.ll b/test/CodeGen/ARM/arm-asm.ll
index e869abeb2dd6..f9199ff82b38 100644
--- a/test/CodeGen/ARM/arm-asm.ll
+++ b/test/CodeGen/ARM/arm-asm.ll
@@ -2,6 +2,6 @@
 
 define void @frame_dummy() {
 entry:
-        %tmp1 = tail call void (i8*)* (void (i8*)*)* asm "", "=r,0,~{dirflag},~{fpsr},~{flags}"( void (i8*)* null )           ; <void (i8*)*> [#uses=0]
+        %tmp1 = tail call void (i8*)* (void (i8*)*) asm "", "=r,0,~{dirflag},~{fpsr},~{flags}"( void (i8*)* null )           ; <void (i8*)*> [#uses=0]
         ret void
 }
diff --git a/test/CodeGen/ARM/arm-modifier.ll b/test/CodeGen/ARM/arm-modifier.ll
index 580f7e7a90c7..67d468e8abd2 100644
--- a/test/CodeGen/ARM/arm-modifier.ll
+++ b/test/CodeGen/ARM/arm-modifier.ll
@@ -6,8 +6,8 @@ entry:
   %scale2.addr = alloca float, align 4
   store float %scale, float* %scale.addr, align 4
   store float %scale2, float* %scale2.addr, align 4
-  %tmp = load float* %scale.addr, align 4
-  %tmp1 = load float* %scale2.addr, align 4
+  %tmp = load float, float* %scale.addr, align 4
+  %tmp1 = load float, float* %scale2.addr, align 4
   call void asm sideeffect "vmul.f32    q0, q0, ${0:y} \0A\09vmul.f32    q1, q1, ${0:y} \0A\09vmul.f32    q1, q0, ${1:y} \0A\09", "w,w,~{q0},~{q1}"(float %tmp, float %tmp1) nounwind
   ret i32 0
 }
@@ -49,8 +49,8 @@ entry:
 ; CHECK: stm {{lr|r[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}}
 ; CHECK: adds {{lr|r[0-9]+}}, [[REG1]]
 ; CHECK: ldm {{lr|r[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}}
-%tmp = load i64* @f3_var, align 4
-%tmp1 = load i64* @f3_var2, align 4
+%tmp = load i64, i64* @f3_var, align 4
+%tmp1 = load i64, i64* @f3_var2, align 4
 %0 = call i64 asm sideeffect "stm ${0:m}, ${1:M}\0A\09adds $3, $1\0A\09", "=*m,=r,1,r"(i64** @f3_ptr, i64 %tmp, i64 %tmp1) nounwind
 store i64 %0, i64* @f3_var, align 4
 %1 = call i64 asm sideeffect "ldm ${1:m}, ${0:M}\0A\09", "=r,*m"(i64** @f3_ptr) nounwind
diff --git a/test/CodeGen/ARM/arm-negative-stride.ll b/test/CodeGen/ARM/arm-negative-stride.ll
index 7decb974e268..2ea15cf429e1 100644
--- a/test/CodeGen/ARM/arm-negative-stride.ll
+++ b/test/CodeGen/ARM/arm-negative-stride.ll
@@ -12,7 +12,7 @@ entry:
 bb:             ; preds = %bb, %entry
         %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]          ; <i32> [#uses=2]
         %i_addr.09.0 = sub i32 %i, %indvar              ; <i32> [#uses=1]
-        %tmp2 = getelementptr i32* %P, i32 %i_addr.09.0         ; <i32*> [#uses=1]
+        %tmp2 = getelementptr i32, i32* %P, i32 %i_addr.09.0         ; <i32*> [#uses=1]
         store i32 %A, i32* %tmp2
         %indvar.next = add i32 %indvar, 1               ; <i32> [#uses=2]
         icmp eq i32 %indvar.next, %i            ; <i1>:1 [#uses=1]
@@ -34,7 +34,7 @@ entry:
 bb:             ; preds = %bb, %entry
         %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]          ; <i32> [#uses=2]
         %i_addr.09.0 = sub i32 %i, %indvar              ; <i32> [#uses=1]
-        %tmp2 = getelementptr i32* %P, i32 %i_addr.09.0         ; <i32*> [#uses=1]
+        %tmp2 = getelementptr i32, i32* %P, i32 %i_addr.09.0         ; <i32*> [#uses=1]
         store i32 %A, i32* %tmp2
         store i32 %indvar, i32* null
         %indvar.next = add i32 %indvar, 1               ; <i32> [#uses=2]
diff --git a/test/CodeGen/ARM/arm-ttype-target2.ll b/test/CodeGen/ARM/arm-ttype-target2.ll
index 4d61cb5bb3a5..754a16d90877 100644
--- a/test/CodeGen/ARM/arm-ttype-target2.ll
+++ b/test/CodeGen/ARM/arm-ttype-target2.ll
@@ -2,7 +2,7 @@
 
 @_ZTVN10__cxxabiv117__class_type_infoE = external global i8*
 @_ZTS3Foo = linkonce_odr constant [5 x i8] c"3Foo\00"
-@_ZTI3Foo = linkonce_odr unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv117__class_type_infoE, i32 2) to i8*), i8* getelementptr inbounds ([5 x i8]* @_ZTS3Foo, i32 0, i32 0) }
+@_ZTI3Foo = linkonce_odr unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i32 2) to i8*), i8* getelementptr inbounds ([5 x i8], [5 x i8]* @_ZTS3Foo, i32 0, i32 0) }
 
 define i32 @main() {
 entry:
diff --git a/test/CodeGen/ARM/atomic-64bit.ll b/test/CodeGen/ARM/atomic-64bit.ll
index 0c0769f1b145..7510d6ccdc33 100644
--- a/test/CodeGen/ARM/atomic-64bit.ll
+++ b/test/CodeGen/ARM/atomic-64bit.ll
@@ -214,7 +214,7 @@ define i64 @test8(i64* %ptr) {
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: dmb {{ish$}}
 
-  %r = load atomic i64* %ptr seq_cst, align 8
+  %r = load atomic i64, i64* %ptr seq_cst, align 8
   ret i64 %r
 }
 
diff --git a/test/CodeGen/ARM/atomic-load-store.ll b/test/CodeGen/ARM/atomic-load-store.ll
index af13dfc80d2d..5db81781a7f7 100644
--- a/test/CodeGen/ARM/atomic-load-store.ll
+++ b/test/CodeGen/ARM/atomic-load-store.ll
@@ -44,7 +44,7 @@ define i32 @test2(i32* %ptr) {
 ; THUMBM-LABEL: test2
 ; THUMBM: ldr
 ; THUMBM: dmb sy
-  %val = load atomic i32* %ptr seq_cst, align 4
+  %val = load atomic i32, i32* %ptr seq_cst, align 4
   ret i32 %val
 }
 
@@ -76,7 +76,7 @@ define void @test3(i8* %ptr1, i8* %ptr2) {
 ; ARMV6-NOT: mcr
 ; THUMBM-LABEL: test3
 ; THUMBM-NOT: dmb sy
-  %val = load atomic i8* %ptr1 unordered, align 1
+  %val = load atomic i8, i8* %ptr1 unordered, align 1
   store atomic i8 %val, i8* %ptr2 unordered, align 1
   ret void
 }
@@ -87,7 +87,7 @@ define void @test4(i8* %ptr1, i8* %ptr2) {
 ; THUMBONE: ___sync_lock_test_and_set_1
 ; ARMV6-LABEL: test4
 ; THUMBM-LABEL: test4
-  %val = load atomic i8* %ptr1 seq_cst, align 1
+  %val = load atomic i8, i8* %ptr1 seq_cst, align 1
   store atomic i8 %val, i8* %ptr2 seq_cst, align 1
   ret void
 }
@@ -95,7 +95,7 @@ define void @test4(i8* %ptr1, i8* %ptr2) {
 define i64 @test_old_load_64bit(i64* %p) {
 ; ARMV4-LABEL: test_old_load_64bit
 ; ARMV4: ___sync_val_compare_and_swap_8
-  %1 = load atomic i64* %p seq_cst, align 8
+  %1 = load atomic i64, i64* %p seq_cst, align 8
   ret i64 %1
 }
 
diff --git a/test/CodeGen/ARM/atomic-op.ll b/test/CodeGen/ARM/atomic-op.ll
index 1ac86485c556..db32bffdd5d1 100644
--- a/test/CodeGen/ARM/atomic-op.ll
+++ b/test/CodeGen/ARM/atomic-op.ll
@@ -25,7 +25,7 @@ entry:
 	store i32 3855, i32* %ort
 	store i32 3855, i32* %xort
 	store i32 4, i32* %temp
-	%tmp = load i32* %temp
+	%tmp = load i32, i32* %temp
   ; CHECK: ldrex
   ; CHECK: add
   ; CHECK: strex
@@ -308,8 +308,8 @@ define i32 @test_cmpxchg_fail_order1(i32 *%addr, i32 %desired, i32 %new) {
 
 define i32 @load_load_add_acquire(i32* %mem1, i32* %mem2) nounwind {
 ; CHECK-LABEL: load_load_add_acquire
-  %val1 = load atomic i32* %mem1 acquire, align 4
-  %val2 = load atomic i32* %mem2 acquire, align 4
+  %val1 = load atomic i32, i32* %mem1 acquire, align 4
+  %val2 = load atomic i32, i32* %mem2 acquire, align 4
   %tmp = add i32 %val1, %val2
 
 ; CHECK: ldr {{r[0-9]}}, [r0]
@@ -353,7 +353,7 @@ define void @store_store_release(i32* %mem1, i32 %val1, i32* %mem2, i32 %val2) {
 
 define void @load_fence_store_monotonic(i32* %mem1, i32* %mem2) {
 ; CHECK-LABEL: load_fence_store_monotonic
-  %val = load atomic i32* %mem1 monotonic, align 4
+  %val = load atomic i32, i32* %mem1 monotonic, align 4
   fence seq_cst
   store atomic i32 %val, i32* %mem2 monotonic, align 4
 
diff --git a/test/CodeGen/ARM/atomic-ops-v8.ll b/test/CodeGen/ARM/atomic-ops-v8.ll
index 7072aaaf733d..db5007b0758d 100644
--- a/test/CodeGen/ARM/atomic-ops-v8.ll
+++ b/test/CodeGen/ARM/atomic-ops-v8.ll
@@ -1166,7 +1166,7 @@ define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
 
 define i8 @test_atomic_load_monotonic_i8() nounwind {
 ; CHECK-LABEL: test_atomic_load_monotonic_i8:
-  %val = load atomic i8* @var8 monotonic, align 1
+  %val = load atomic i8, i8* @var8 monotonic, align 1
 ; CHECK-NOT: dmb
 ; CHECK-NOT: mcr
 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
@@ -1183,7 +1183,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i8*
 
-  %val = load atomic i8* %addr monotonic, align 1
+  %val = load atomic i8, i8* %addr monotonic, align 1
 ; CHECK-NOT: dmb
 ; CHECK-NOT: mcr
 ; CHECK-LE: ldrb r0, [r0, r2]
@@ -1196,7 +1196,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
 
 define i8 @test_atomic_load_acquire_i8() nounwind {
 ; CHECK-LABEL: test_atomic_load_acquire_i8:
-  %val = load atomic i8* @var8 acquire, align 1
+  %val = load atomic i8, i8* @var8 acquire, align 1
 ; CHECK-NOT: dmb
 ; CHECK-NOT: mcr
 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
@@ -1213,7 +1213,7 @@ define i8 @test_atomic_load_acquire_i8() nounwind {
 
 define i8 @test_atomic_load_seq_cst_i8() nounwind {
 ; CHECK-LABEL: test_atomic_load_seq_cst_i8:
-  %val = load atomic i8* @var8 seq_cst, align 1
+  %val = load atomic i8, i8* @var8 seq_cst, align 1
 ; CHECK-NOT: dmb
 ; CHECK-NOT: mcr
 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
@@ -1230,7 +1230,7 @@ define i8 @test_atomic_load_seq_cst_i8() nounwind {
 
 define i16 @test_atomic_load_monotonic_i16() nounwind {
 ; CHECK-LABEL: test_atomic_load_monotonic_i16:
-  %val = load atomic i16* @var16 monotonic, align 2
+  %val = load atomic i16, i16* @var16 monotonic, align 2
 ; CHECK-NOT: dmb
 ; CHECK-NOT: mcr
 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
@@ -1251,7 +1251,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i32*
 
-  %val = load atomic i32* %addr monotonic, align 4
+  %val = load atomic i32, i32* %addr monotonic, align 4
 ; CHECK-NOT: dmb
 ; CHECK-NOT: mcr
 ; CHECK-LE: ldr r0, [r0, r2]
@@ -1264,7 +1264,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind
 
 define i64 @test_atomic_load_seq_cst_i64() nounwind {
 ; CHECK-LABEL: test_atomic_load_seq_cst_i64:
-  %val = load atomic i64* @var64 seq_cst, align 8
+  %val = load atomic i64, i64* @var64 seq_cst, align 8
 ; CHECK-NOT: dmb
 ; CHECK-NOT: mcr
 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
@@ -1296,7 +1296,7 @@ define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val)
   %addr = inttoptr i64 %addr_int to i8*
 
   store atomic i8 %val, i8* %addr monotonic, align 1
-; CHECK-LE: ldrb{{(\.w)?}} [[VAL:r[0-9]+]], [sp]
+; CHECK-LE: ldr{{b?(\.w)?}} [[VAL:r[0-9]+]], [sp]
 ; CHECK-LE: strb [[VAL]], [r0, r2]
 ; CHECK-BE: ldrb{{(\.w)?}} [[VAL:r[0-9]+]], [sp, #3]
 ; CHECK-BE: strb [[VAL]], [r1, r3]
@@ -1399,7 +1399,7 @@ define i32 @not.barriers(i32* %var, i1 %cond) {
 ; CHECK-LABEL: not.barriers:
   br i1 %cond, label %atomic_ver, label %simple_ver
 simple_ver:
-  %oldval = load i32* %var
+  %oldval = load i32, i32* %var
   %newval = add nsw i32 %oldval, -1
   store i32 %newval, i32* %var
   br label %somewhere
diff --git a/test/CodeGen/ARM/available_externally.ll b/test/CodeGen/ARM/available_externally.ll
index d925b5c77706..055074738e5c 100644
--- a/test/CodeGen/ARM/available_externally.ll
+++ b/test/CodeGen/ARM/available_externally.ll
@@ -5,7 +5,7 @@
 @B = external hidden constant i32
 
 define i32 @t1() {
-  %tmp = load i32* @A
+  %tmp = load i32, i32* @A
   store i32 %tmp, i32* @B
   ret i32 %tmp
 }
diff --git a/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/test/CodeGen/ARM/avoid-cpsr-rmw.ll
index 0217a4a8fb83..c3de07e03b6b 100644
--- a/test/CodeGen/ARM/avoid-cpsr-rmw.ll
+++ b/test/CodeGen/ARM/avoid-cpsr-rmw.ll
@@ -30,19 +30,19 @@ while.body:
 ; CHECK-NOT: muls
   %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
   %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
-  %0 = load i32* %ptr1.addr.09, align 4
-  %arrayidx1 = getelementptr inbounds i32* %ptr1.addr.09, i32 1
-  %1 = load i32* %arrayidx1, align 4
-  %arrayidx3 = getelementptr inbounds i32* %ptr1.addr.09, i32 2
-  %2 = load i32* %arrayidx3, align 4
-  %arrayidx4 = getelementptr inbounds i32* %ptr1.addr.09, i32 3
-  %3 = load i32* %arrayidx4, align 4
-  %add.ptr = getelementptr inbounds i32* %ptr1.addr.09, i32 4
+  %0 = load i32, i32* %ptr1.addr.09, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 1
+  %1 = load i32, i32* %arrayidx1, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 2
+  %2 = load i32, i32* %arrayidx3, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 3
+  %3 = load i32, i32* %arrayidx4, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 4
   %mul = mul i32 %1, %0
   %mul5 = mul i32 %mul, %2
   %mul6 = mul i32 %mul5, %3
   store i32 %mul6, i32* %ptr2.addr.08, align 4
-  %incdec.ptr = getelementptr inbounds i32* %ptr2.addr.08, i32 -1
+  %incdec.ptr = getelementptr inbounds i32, i32* %ptr2.addr.08, i32 -1
   %tobool = icmp eq i32* %incdec.ptr, null
   br i1 %tobool, label %while.end, label %while.body
 
@@ -64,19 +64,19 @@ while.body:
 ; CHECK: muls
   %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
   %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
-  %0 = load i32* %ptr1.addr.09, align 4
-  %arrayidx1 = getelementptr inbounds i32* %ptr1.addr.09, i32 1
-  %1 = load i32* %arrayidx1, align 4
-  %arrayidx3 = getelementptr inbounds i32* %ptr1.addr.09, i32 2
-  %2 = load i32* %arrayidx3, align 4
-  %arrayidx4 = getelementptr inbounds i32* %ptr1.addr.09, i32 3
-  %3 = load i32* %arrayidx4, align 4
-  %add.ptr = getelementptr inbounds i32* %ptr1.addr.09, i32 4
+  %0 = load i32, i32* %ptr1.addr.09, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 1
+  %1 = load i32, i32* %arrayidx1, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 2
+  %2 = load i32, i32* %arrayidx3, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 3
+  %3 = load i32, i32* %arrayidx4, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 4
   %mul = mul i32 %1, %0
   %mul5 = mul i32 %mul, %2
   %mul6 = mul i32 %mul5, %3
   store i32 %mul6, i32* %ptr2.addr.08, align 4
-  %incdec.ptr = getelementptr inbounds i32* %ptr2.addr.08, i32 -1
+  %incdec.ptr = getelementptr inbounds i32, i32* %ptr2.addr.08, i32 -1
   %tobool = icmp eq i32* %incdec.ptr, null
   br i1 %tobool, label %while.end, label %while.body
 
@@ -92,21 +92,21 @@ entry:
 ; CHECK: vmrs APSR_nzcv, fpscr
 ; CHECK: if.then
 ; CHECK-NOT: movs
-  %0 = load double* %q, align 4
+  %0 = load double, double* %q, align 4
   %cmp = fcmp olt double %0, 1.000000e+01
-  %incdec.ptr1 = getelementptr inbounds i32* %p, i32 1
+  %incdec.ptr1 = getelementptr inbounds i32, i32* %p, i32 1
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:
   store i32 7, i32* %p, align 4
-  %incdec.ptr2 = getelementptr inbounds i32* %p, i32 2
+  %incdec.ptr2 = getelementptr inbounds i32, i32* %p, i32 2
   store i32 8, i32* %incdec.ptr1, align 4
   store i32 9, i32* %incdec.ptr2, align 4
   br label %if.end
 
 if.else:
   store i32 3, i32* %p, align 4
-  %incdec.ptr5 = getelementptr inbounds i32* %p, i32 2
+  %incdec.ptr5 = getelementptr inbounds i32, i32* %p, i32 2
   store i32 5, i32* %incdec.ptr1, align 4
   store i32 6, i32* %incdec.ptr5, align 4
   br label %if.end
diff --git a/test/CodeGen/ARM/bfi.ll b/test/CodeGen/ARM/bfi.ll
index bce09da7618a..0661960d1ae0 100644
--- a/test/CodeGen/ARM/bfi.ll
+++ b/test/CodeGen/ARM/bfi.ll
@@ -9,7 +9,7 @@ entry:
 ; CHECK: f1
 ; CHECK: mov r2, #10
 ; CHECK: bfi r1, r2, #22, #4
-  %0 = load i32* bitcast (%struct.F* @X to i32*), align 4 ; <i32> [#uses=1]
+  %0 = load i32, i32* bitcast (%struct.F* @X to i32*), align 4 ; <i32> [#uses=1]
   %1 = and i32 %0, -62914561                      ; <i32> [#uses=1]
   %2 = or i32 %1, 41943040                        ; <i32> [#uses=1]
   store i32 %2, i32* bitcast (%struct.F* @X to i32*), align 4
diff --git a/test/CodeGen/ARM/bfx.ll b/test/CodeGen/ARM/bfx.ll
index 46f49e9fab20..edb0c1a5a54a 100644
--- a/test/CodeGen/ARM/bfx.ll
+++ b/test/CodeGen/ARM/bfx.ll
@@ -41,13 +41,13 @@ entry:
   %and1 = lshr i32 %x, 16
   %shr2 = and i32 %and1, 255
   %shr4 = lshr i32 %x, 24
-  %arrayidx = getelementptr inbounds i32* %ctx, i32 %shr4
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx5 = getelementptr inbounds i32* %ctx, i32 %shr2
-  %1 = load i32* %arrayidx5, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %ctx, i32 %shr4
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx5 = getelementptr inbounds i32, i32* %ctx, i32 %shr2
+  %1 = load i32, i32* %arrayidx5, align 4
   %add = add i32 %1, %0
-  %arrayidx6 = getelementptr inbounds i32* %ctx, i32 %shr
-  %2 = load i32* %arrayidx6, align 4
+  %arrayidx6 = getelementptr inbounds i32, i32* %ctx, i32 %shr
+  %2 = load i32, i32* %arrayidx6, align 4
   %add7 = add i32 %add, %2
   ret i32 %add7
 }
diff --git a/test/CodeGen/ARM/big-endian-neon-bitconv.ll b/test/CodeGen/ARM/big-endian-neon-bitconv.ll
index 427d2e731428..b5a840a48f7a 100644
--- a/test/CodeGen/ARM/big-endian-neon-bitconv.ll
+++ b/test/CodeGen/ARM/big-endian-neon-bitconv.ll
@@ -19,7 +19,7 @@ define void @conv_i64_to_v8i8( i64 %val,  <8 x i8>* %store ) {
 ; CHECK-LABEL: conv_i64_to_v8i8:
 ; CHECK: vrev64.8
   %v = bitcast i64 %val to <8 x i8>
-  %w = load <8 x i8>* @v8i8
+  %w = load <8 x i8>, <8 x i8>* @v8i8
   %a = add <8 x i8> %v, %w
   store <8 x i8> %a, <8 x i8>* %store
   ret void
@@ -28,8 +28,8 @@ define void @conv_i64_to_v8i8( i64 %val,  <8 x i8>* %store ) {
 define void @conv_v8i8_to_i64( <8 x i8>* %load, <8 x i8>* %store ) {
 ; CHECK-LABEL: conv_v8i8_to_i64:
 ; CHECK: vrev64.8
-  %v = load <8 x i8>* %load
-  %w = load <8 x i8>* @v8i8
+  %v = load <8 x i8>, <8 x i8>* %load
+  %w = load <8 x i8>, <8 x i8>* @v8i8
   %a = add <8 x i8> %v, %w
   %f = bitcast <8 x i8> %a to i64
   call void @conv_i64_to_v8i8( i64 %f, <8 x i8>* %store )
@@ -40,7 +40,7 @@ define void @conv_i64_to_v4i16( i64 %val,  <4 x i16>* %store ) {
 ; CHECK-LABEL: conv_i64_to_v4i16:
 ; CHECK: vrev64.16
   %v = bitcast i64 %val to <4 x i16>
-  %w = load <4 x i16>* @v4i16
+  %w = load <4 x i16>, <4 x i16>* @v4i16
   %a = add <4 x i16> %v, %w
   store <4 x i16> %a, <4 x i16>* %store
   ret void
@@ -49,8 +49,8 @@ define void @conv_i64_to_v4i16( i64 %val,  <4 x i16>* %store ) {
 define void @conv_v4i16_to_i64( <4 x i16>* %load, <4 x i16>* %store ) {
 ; CHECK-LABEL: conv_v4i16_to_i64:
 ; CHECK: vrev64.16
-  %v = load <4 x i16>* %load
-  %w = load <4 x i16>* @v4i16
+  %v = load <4 x i16>, <4 x i16>* %load
+  %w = load <4 x i16>, <4 x i16>* @v4i16
   %a = add <4 x i16> %v, %w
   %f = bitcast <4 x i16> %a to i64
   call void @conv_i64_to_v4i16( i64 %f, <4 x i16>* %store )
@@ -61,7 +61,7 @@ define void @conv_i64_to_v2i32( i64 %val,  <2 x i32>* %store ) {
 ; CHECK-LABEL: conv_i64_to_v2i32:
 ; CHECK: vrev64.32
   %v = bitcast i64 %val to <2 x i32>
-  %w = load <2 x i32>* @v2i32
+  %w = load <2 x i32>, <2 x i32>* @v2i32
   %a = add <2 x i32> %v, %w
   store <2 x i32> %a, <2 x i32>* %store
   ret void
@@ -70,8 +70,8 @@ define void @conv_i64_to_v2i32( i64 %val,  <2 x i32>* %store ) {
 define void @conv_v2i32_to_i64( <2 x i32>* %load, <2 x i32>* %store ) {
 ; CHECK-LABEL: conv_v2i32_to_i64:
 ; CHECK: vrev64.32
-  %v = load <2 x i32>* %load
-  %w = load <2 x i32>* @v2i32
+  %v = load <2 x i32>, <2 x i32>* %load
+  %w = load <2 x i32>, <2 x i32>* @v2i32
   %a = add <2 x i32> %v, %w
   %f = bitcast <2 x i32> %a to i64
   call void @conv_i64_to_v2i32( i64 %f, <2 x i32>* %store )
@@ -82,7 +82,7 @@ define void @conv_i64_to_v2f32( i64 %val,  <2 x float>* %store ) {
 ; CHECK-LABEL: conv_i64_to_v2f32:
 ; CHECK: vrev64.32
   %v = bitcast i64 %val to <2 x float>
-  %w = load <2 x float>* @v2f32
+  %w = load <2 x float>, <2 x float>* @v2f32
   %a = fadd <2 x float> %v, %w
   store <2 x float> %a, <2 x float>* %store
   ret void
@@ -91,8 +91,8 @@ define void @conv_i64_to_v2f32( i64 %val,  <2 x float>* %store ) {
 define void @conv_v2f32_to_i64( <2 x float>* %load, <2 x float>* %store ) {
 ; CHECK-LABEL: conv_v2f32_to_i64:
 ; CHECK: vrev64.32
-  %v = load <2 x float>* %load
-  %w = load <2 x float>* @v2f32
+  %v = load <2 x float>, <2 x float>* %load
+  %w = load <2 x float>, <2 x float>* @v2f32
   %a = fadd <2 x float> %v, %w
   %f = bitcast <2 x float> %a to i64
   call void @conv_i64_to_v2f32( i64 %f, <2 x float>* %store )
@@ -103,7 +103,7 @@ define void @conv_f64_to_v8i8( double %val,  <8 x i8>* %store ) {
 ; CHECK-LABEL: conv_f64_to_v8i8:
 ; CHECK: vrev64.8
   %v = bitcast double %val to <8 x i8>
-  %w = load <8 x i8>* @v8i8
+  %w = load <8 x i8>, <8 x i8>* @v8i8
   %a = add <8 x i8> %v, %w
   store <8 x i8> %a, <8 x i8>* %store
   ret void
@@ -112,8 +112,8 @@ define void @conv_f64_to_v8i8( double %val,  <8 x i8>* %store ) {
 define void @conv_v8i8_to_f64( <8 x i8>* %load, <8 x i8>* %store ) {
 ; CHECK-LABEL: conv_v8i8_to_f64:
 ; CHECK: vrev64.8
-  %v = load <8 x i8>* %load
-  %w = load <8 x i8>* @v8i8
+  %v = load <8 x i8>, <8 x i8>* %load
+  %w = load <8 x i8>, <8 x i8>* @v8i8
   %a = add <8 x i8> %v, %w
   %f = bitcast <8 x i8> %a to double
   call void @conv_f64_to_v8i8( double %f, <8 x i8>* %store )
@@ -124,7 +124,7 @@ define void @conv_f64_to_v4i16( double %val,  <4 x i16>* %store ) {
 ; CHECK-LABEL: conv_f64_to_v4i16:
 ; CHECK: vrev64.16
   %v = bitcast double %val to <4 x i16>
-  %w = load <4 x i16>* @v4i16
+  %w = load <4 x i16>, <4 x i16>* @v4i16
   %a = add <4 x i16> %v, %w
   store <4 x i16> %a, <4 x i16>* %store
   ret void
@@ -133,8 +133,8 @@ define void @conv_f64_to_v4i16( double %val,  <4 x i16>* %store ) {
 define void @conv_v4i16_to_f64( <4 x i16>* %load, <4 x i16>* %store ) {
 ; CHECK-LABEL: conv_v4i16_to_f64:
 ; CHECK: vrev64.16
-  %v = load <4 x i16>* %load
-  %w = load <4 x i16>* @v4i16
+  %v = load <4 x i16>, <4 x i16>* %load
+  %w = load <4 x i16>, <4 x i16>* @v4i16
   %a = add <4 x i16> %v, %w
   %f = bitcast <4 x i16> %a to double
   call void @conv_f64_to_v4i16( double %f, <4 x i16>* %store )
@@ -145,7 +145,7 @@ define void @conv_f64_to_v2i32( double %val,  <2 x i32>* %store ) {
 ; CHECK-LABEL: conv_f64_to_v2i32:
 ; CHECK: vrev64.32
   %v = bitcast double %val to <2 x i32>
-  %w = load <2 x i32>* @v2i32
+  %w = load <2 x i32>, <2 x i32>* @v2i32
   %a = add <2 x i32> %v, %w
   store <2 x i32> %a, <2 x i32>* %store
   ret void
@@ -154,8 +154,8 @@ define void @conv_f64_to_v2i32( double %val,  <2 x i32>* %store ) {
 define void @conv_v2i32_to_f64( <2 x i32>* %load, <2 x i32>* %store ) {
 ; CHECK-LABEL: conv_v2i32_to_f64:
 ; CHECK: vrev64.32
-  %v = load <2 x i32>* %load
-  %w = load <2 x i32>* @v2i32
+  %v = load <2 x i32>, <2 x i32>* %load
+  %w = load <2 x i32>, <2 x i32>* @v2i32
   %a = add <2 x i32> %v, %w
   %f = bitcast <2 x i32> %a to double
   call void @conv_f64_to_v2i32( double %f, <2 x i32>* %store )
@@ -166,7 +166,7 @@ define void @conv_f64_to_v2f32( double %val,  <2 x float>* %store ) {
 ; CHECK-LABEL: conv_f64_to_v2f32:
 ; CHECK: vrev64.32
   %v = bitcast double %val to <2 x float>
-  %w = load <2 x float>* @v2f32
+  %w = load <2 x float>, <2 x float>* @v2f32
   %a = fadd <2 x float> %v, %w
   store <2 x float> %a, <2 x float>* %store
   ret void
@@ -175,8 +175,8 @@ define void @conv_f64_to_v2f32( double %val,  <2 x float>* %store ) {
 define void @conv_v2f32_to_f64( <2 x float>* %load, <2 x float>* %store ) {
 ; CHECK-LABEL: conv_v2f32_to_f64:
 ; CHECK: vrev64.32
-  %v = load <2 x float>* %load
-  %w = load <2 x float>* @v2f32
+  %v = load <2 x float>, <2 x float>* %load
+  %w = load <2 x float>, <2 x float>* @v2f32
   %a = fadd <2 x float> %v, %w
   %f = bitcast <2 x float> %a to double
   call void @conv_f64_to_v2f32( double %f, <2 x float>* %store )
@@ -190,7 +190,7 @@ define void @conv_i128_to_v16i8( i128 %val,  <16 x i8>* %store ) {
 ; CHECK-LABEL: conv_i128_to_v16i8:
 ; CHECK: vrev32.8
   %v = bitcast i128 %val to <16 x i8>
-  %w = load  <16 x i8>* @v16i8
+  %w = load  <16 x i8>,  <16 x i8>* @v16i8
   %a = add <16 x i8> %v, %w
   store <16 x i8> %a, <16 x i8>* %store
   ret void
@@ -199,8 +199,8 @@ define void @conv_i128_to_v16i8( i128 %val,  <16 x i8>* %store ) {
 define void @conv_v16i8_to_i128( <16 x i8>* %load, <16 x i8>* %store ) {
 ; CHECK-LABEL: conv_v16i8_to_i128:
 ; CHECK: vrev32.8
-  %v = load <16 x i8>* %load
-  %w = load <16 x i8>* @v16i8
+  %v = load <16 x i8>, <16 x i8>* %load
+  %w = load <16 x i8>, <16 x i8>* @v16i8
   %a = add <16 x i8> %v, %w
   %f = bitcast <16 x i8> %a to i128
   call void @conv_i128_to_v16i8( i128 %f, <16 x i8>* %store )
@@ -211,7 +211,7 @@ define void @conv_i128_to_v8i16( i128 %val,  <8 x i16>* %store ) {
 ; CHECK-LABEL: conv_i128_to_v8i16:
 ; CHECK: vrev32.16
   %v = bitcast i128 %val to <8 x i16>
-  %w = load  <8 x i16>* @v8i16
+  %w = load  <8 x i16>,  <8 x i16>* @v8i16
   %a = add <8 x i16> %v, %w
   store <8 x i16> %a, <8 x i16>* %store
   ret void
@@ -220,8 +220,8 @@ define void @conv_i128_to_v8i16( i128 %val,  <8 x i16>* %store ) {
 define void @conv_v8i16_to_i128( <8 x i16>* %load, <8 x i16>* %store ) {
 ; CHECK-LABEL: conv_v8i16_to_i128:
 ; CHECK: vrev32.16
-  %v = load <8 x i16>* %load
-  %w = load <8 x i16>* @v8i16
+  %v = load <8 x i16>, <8 x i16>* %load
+  %w = load <8 x i16>, <8 x i16>* @v8i16
   %a = add <8 x i16> %v, %w
   %f = bitcast <8 x i16> %a to i128
   call void @conv_i128_to_v8i16( i128 %f, <8 x i16>* %store )
@@ -232,7 +232,7 @@ define void @conv_i128_to_v4i32( i128 %val,  <4 x i32>* %store ) {
 ; CHECK-LABEL: conv_i128_to_v4i32:
 ; CHECK: vrev64.32
   %v = bitcast i128 %val to <4 x i32>
-  %w = load <4 x i32>* @v4i32
+  %w = load <4 x i32>, <4 x i32>* @v4i32
   %a = add <4 x i32> %v, %w
   store <4 x i32> %a, <4 x i32>* %store
   ret void
@@ -241,8 +241,8 @@ define void @conv_i128_to_v4i32( i128 %val,  <4 x i32>* %store ) {
 define void @conv_v4i32_to_i128( <4 x i32>* %load, <4 x i32>* %store ) {
 ; CHECK-LABEL: conv_v4i32_to_i128:
 ; CHECK: vrev64.32
-  %v = load <4 x i32>* %load
-  %w = load <4 x i32>* @v4i32
+  %v = load <4 x i32>, <4 x i32>* %load
+  %w = load <4 x i32>, <4 x i32>* @v4i32
   %a = add <4 x i32> %v, %w
   %f = bitcast <4 x i32> %a to i128
   call void @conv_i128_to_v4i32( i128 %f, <4 x i32>* %store )
@@ -253,7 +253,7 @@ define void @conv_i128_to_v4f32( i128 %val,  <4 x float>* %store ) {
 ; CHECK-LABEL: conv_i128_to_v4f32:
 ; CHECK: vrev64.32
   %v = bitcast i128 %val to <4 x float>
-  %w = load <4 x float>* @v4f32
+  %w = load <4 x float>, <4 x float>* @v4f32
   %a = fadd <4 x float> %v, %w
   store <4 x float> %a, <4 x float>* %store
   ret void
@@ -262,8 +262,8 @@ define void @conv_i128_to_v4f32( i128 %val,  <4 x float>* %store ) {
 define void @conv_v4f32_to_i128( <4 x float>* %load, <4 x float>* %store ) {
 ; CHECK-LABEL: conv_v4f32_to_i128:
 ; CHECK: vrev64.32
-  %v = load <4 x float>* %load
-  %w = load <4 x float>* @v4f32
+  %v = load <4 x float>, <4 x float>* %load
+  %w = load <4 x float>, <4 x float>* @v4f32
   %a = fadd <4 x float> %v, %w
   %f = bitcast <4 x float> %a to i128
   call void @conv_i128_to_v4f32( i128 %f, <4 x float>* %store )
@@ -274,7 +274,7 @@ define void @conv_f128_to_v2f64( fp128 %val,  <2 x double>* %store ) {
 ; CHECK-LABEL: conv_f128_to_v2f64:
 ; CHECK: vrev64.32
   %v = bitcast fp128 %val to <2 x double>
-  %w = load <2 x double>* @v2f64
+  %w = load <2 x double>, <2 x double>* @v2f64
   %a = fadd <2 x double> %v, %w
   store <2 x double> %a, <2 x double>* %store
   ret void
@@ -283,8 +283,8 @@ define void @conv_f128_to_v2f64( fp128 %val,  <2 x double>* %store ) {
 define void @conv_v2f64_to_f128( <2 x double>* %load, <2 x double>* %store ) {
 ; CHECK-LABEL: conv_v2f64_to_f128:
 ; CHECK: vrev64.32
-  %v = load <2 x double>* %load
-  %w = load <2 x double>* @v2f64
+  %v = load <2 x double>, <2 x double>* %load
+  %w = load <2 x double>, <2 x double>* @v2f64
   %a = fadd <2 x double> %v, %w
   %f = bitcast <2 x double> %a to fp128
   call void @conv_f128_to_v2f64( fp128 %f, <2 x double>* %store )
@@ -295,7 +295,7 @@ define void @conv_f128_to_v16i8( fp128 %val,  <16 x i8>* %store ) {
 ; CHECK-LABEL: conv_f128_to_v16i8:
 ; CHECK: vrev32.8
   %v = bitcast fp128 %val to <16 x i8>
-  %w = load  <16 x i8>* @v16i8
+  %w = load  <16 x i8>,  <16 x i8>* @v16i8
   %a = add <16 x i8> %v, %w
   store <16 x i8> %a, <16 x i8>* %store
   ret void
@@ -304,8 +304,8 @@ define void @conv_f128_to_v16i8( fp128 %val,  <16 x i8>* %store ) {
 define void @conv_v16i8_to_f128( <16 x i8>* %load, <16 x i8>* %store ) {
 ; CHECK-LABEL: conv_v16i8_to_f128:
 ; CHECK: vrev32.8
-  %v = load <16 x i8>* %load
-  %w = load <16 x i8>* @v16i8
+  %v = load <16 x i8>, <16 x i8>* %load
+  %w = load <16 x i8>, <16 x i8>* @v16i8
   %a = add <16 x i8> %v, %w
   %f = bitcast <16 x i8> %a to fp128
   call void @conv_f128_to_v16i8( fp128 %f, <16 x i8>* %store )
@@ -316,7 +316,7 @@ define void @conv_f128_to_v8i16( fp128 %val,  <8 x i16>* %store ) {
 ; CHECK-LABEL: conv_f128_to_v8i16:
 ; CHECK: vrev32.16
   %v = bitcast fp128 %val to <8 x i16>
-  %w = load  <8 x i16>* @v8i16
+  %w = load  <8 x i16>,  <8 x i16>* @v8i16
   %a = add <8 x i16> %v, %w
   store <8 x i16> %a, <8 x i16>* %store
   ret void
@@ -325,8 +325,8 @@ define void @conv_f128_to_v8i16( fp128 %val,  <8 x i16>* %store ) {
 define void @conv_v8i16_to_f128( <8 x i16>* %load, <8 x i16>* %store ) {
 ; CHECK-LABEL: conv_v8i16_to_f128:
 ; CHECK: vrev32.16
-  %v = load <8 x i16>* %load
-  %w = load <8 x i16>* @v8i16
+  %v = load <8 x i16>, <8 x i16>* %load
+  %w = load <8 x i16>, <8 x i16>* @v8i16
   %a = add <8 x i16> %v, %w
   %f = bitcast <8 x i16> %a to fp128
   call void @conv_f128_to_v8i16( fp128 %f, <8 x i16>* %store )
@@ -337,7 +337,7 @@ define void @conv_f128_to_v4f32( fp128 %val,  <4 x float>* %store ) {
 ; CHECK-LABEL: conv_f128_to_v4f32:
 ; CHECK: vrev64.32
   %v = bitcast fp128 %val to <4 x float>
-  %w = load <4 x float>* @v4f32
+  %w = load <4 x float>, <4 x float>* @v4f32
   %a = fadd <4 x float> %v, %w
   store <4 x float> %a, <4 x float>* %store
   ret void
@@ -346,8 +346,8 @@ define void @conv_f128_to_v4f32( fp128 %val,  <4 x float>* %store ) {
 define void @conv_v4f32_to_f128( <4 x float>* %load, <4 x float>* %store ) {
 ; CHECK-LABEL: conv_v4f32_to_f128:
 ; CHECK: vrev64.32
-  %v = load <4 x float>* %load
-  %w = load <4 x float>* @v4f32
+  %v = load <4 x float>, <4 x float>* %load
+  %w = load <4 x float>, <4 x float>* @v4f32
   %a = fadd <4 x float> %v, %w
   %f = bitcast <4 x float> %a to fp128
   call void @conv_f128_to_v4f32( fp128 %f, <4 x float>* %store )
diff --git a/test/CodeGen/ARM/big-endian-neon-extend.ll b/test/CodeGen/ARM/big-endian-neon-extend.ll
index 931c6c3979c6..f8542b708b8a 100644
--- a/test/CodeGen/ARM/big-endian-neon-extend.ll
+++ b/test/CodeGen/ARM/big-endian-neon-extend.ll
@@ -2,11 +2,14 @@
 
 define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ) {
 ; CHECK-LABEL: vector_ext_2i8_to_2i64:
-; CHECK:       vld1.16 {[[REG:d[0-9]+]]
-; CHECK:       vmov.i64 {{q[0-9]+}}, #0xff
-; CHECK:       vrev16.8  [[REG]], [[REG]]
-; CHECK:       vmovl.u8  {{q[0-9]+}}, [[REG]]
-  %1 = load <2 x i8>* %loadaddr
+; CHECK:      vld1.16   {[[REG:d[0-9]+]][0]}, [r0:16]
+; CHECK-NEXT: vrev16.8  [[REG]], [[REG]]
+; CHECK-NEXT: vmovl.u8  [[QREG:q[0-9]+]], [[REG]]
+; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
+; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
+; CHECK-NEXT: vst1.64   {[[REG]], {{d[0-9]+}}}, [r1]
+; CHECK-NEXT: bx        lr
+  %1 = load <2 x i8>, <2 x i8>* %loadaddr
   %2 = zext <2 x i8> %1 to <2 x i64>
   store <2 x i64> %2, <2 x i64>* %storeaddr
   ret void
@@ -14,11 +17,13 @@ define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr
 
 define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeaddr ) {
 ; CHECK-LABEL: vector_ext_2i16_to_2i64:
-; CHECK:       vld1.32 {[[REG:d[0-9]+]]
-; CHECK:       vmov.i64 {{q[0-9]+}}, #0xffff
-; CHECK:       vrev32.16  [[REG]], [[REG]]
-; CHECK:       vmovl.u16  {{q[0-9]+}}, [[REG]]
-  %1 = load <2 x i16>* %loadaddr
+; CHECK:      vld1.32   {[[REG:d[0-9]+]][0]}, [r0:32]
+; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
+; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
+; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
+; CHECK-NEXT: vst1.64   {[[REG]], {{d[0-9]+}}}, [r1]
+; CHECK-NEXT: bx        lr
+  %1 = load <2 x i16>, <2 x i16>* %loadaddr
   %2 = zext <2 x i16> %1 to <2 x i64>
   store <2 x i64> %2, <2 x i64>* %storeaddr
   ret void
@@ -27,9 +32,14 @@ define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeadd
 
 define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr ) {
 ; CHECK-LABEL: vector_ext_2i8_to_2i32:
-; CHECK:       vld1.16 {[[REG:d[0-9]+]]
-; CHECK:       vrev16.8  [[REG]], [[REG]]
-  %1 = load <2 x i8>* %loadaddr
+; CHECK:      vld1.16   {[[REG:d[0-9]+]][0]}, [r0:16]
+; CHECK-NEXT: vrev16.8  [[REG]], [[REG]]
+; CHECK-NEXT: vmovl.u8  [[QREG:q[0-9]+]], [[REG]]
+; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
+; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
+; CHECK-NEXT: vstr      [[REG]], [r1]
+; CHECK-NEXT: bx        lr
+  %1 = load <2 x i8>, <2 x i8>* %loadaddr
   %2 = zext <2 x i8> %1 to <2 x i32>
   store <2 x i32> %2, <2 x i32>* %storeaddr
   ret void
@@ -37,10 +47,13 @@ define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr
 
 define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeaddr ) {
 ; CHECK-LABEL: vector_ext_2i16_to_2i32:
-; CHECK:       vld1.32 {[[REG:d[0-9]+]]
-; CHECK:       vrev32.16  [[REG]], [[REG]]
-; CHECK:       vmovl.u16  {{q[0-9]+}}, [[REG]]
-  %1 = load <2 x i16>* %loadaddr
+; CHECK:      vld1.32   {[[REG:d[0-9]+]][0]}, [r0:32]
+; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
+; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
+; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
+; CHECK-NEXT: vstr      [[REG]], [r1]
+; CHECK-NEXT: bx        lr
+  %1 = load <2 x i16>, <2 x i16>* %loadaddr
   %2 = zext <2 x i16> %1 to <2 x i32>
   store <2 x i32> %2, <2 x i32>* %storeaddr
   ret void
@@ -48,10 +61,16 @@ define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeadd
 
 define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr ) {
 ; CHECK-LABEL: vector_ext_2i8_to_2i16:
-; CHECK:       vld1.16 {[[REG:d[0-9]+]]
-; CHECK:       vrev16.8  [[REG]], [[REG]]
-; CHECK:       vmovl.u8  {{q[0-9]+}}, [[REG]]
-  %1 = load <2 x i8>* %loadaddr
+; CHECK:      vld1.16   {[[REG:d[0-9]+]][0]}, [r0:16]
+; CHECK-NEXT: vrev16.8  [[REG]], [[REG]]
+; CHECK-NEXT: vmovl.u8  [[QREG:q[0-9]+]], [[REG]]
+; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
+; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
+; CHECK-NEXT: vuzp.16   [[REG]], {{d[0-9]+}}
+; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}}
+; CHECK-NEXT: vst1.32   {[[REG]][0]}, [r1:32]
+; CHECK-NEXT: bx        lr
+  %1 = load <2 x i8>, <2 x i8>* %loadaddr
   %2 = zext <2 x i8> %1 to <2 x i16>
   store <2 x i16> %2, <2 x i16>* %storeaddr
   ret void
@@ -59,10 +78,14 @@ define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr
 
 define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr ) {
 ; CHECK-LABEL: vector_ext_4i8_to_4i32:
-; CHECK:       vld1.32 {[[REG:d[0-9]+]]
-; CHECK:       vrev32.8  [[REG]], [[REG]]
-; CHECK:       vmovl.u8  {{q[0-9]+}}, [[REG]]
-  %1 = load <4 x i8>* %loadaddr
+; CHECK:      vld1.32   {[[REG:d[0-9]+]][0]}, [r0:32]
+; CHECK-NEXT: vrev32.8  [[REG]], [[REG]]
+; CHECK-NEXT: vmovl.u8  [[QREG:q[0-9]+]], [[REG]]
+; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
+; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
+; CHECK-NEXT: vst1.64   {[[REG]], {{d[0-9]+}}}, [r1]
+; CHECK-NEXT: bx        lr
+  %1 = load <4 x i8>, <4 x i8>* %loadaddr
   %2 = zext <4 x i8> %1 to <4 x i32>
   store <4 x i32> %2, <4 x i32>* %storeaddr
   ret void
@@ -70,12 +93,14 @@ define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr
 
 define void @vector_ext_4i8_to_4i16( <4 x i8>* %loadaddr, <4 x i16>* %storeaddr ) {
 ; CHECK-LABEL: vector_ext_4i8_to_4i16:
-; CHECK:       vld1.32 {[[REG:d[0-9]+]]
-; CHECK:       vrev32.8  [[REG]], [[REG]]
-; CHECK:       vmovl.u8  {{q[0-9]+}}, [[REG]]
-  %1 = load <4 x i8>* %loadaddr
+; CHECK:      vld1.32   {[[REG:d[0-9]+]][0]}, [r0:32]
+; CHECK-NEXT: vrev32.8  [[REG]], [[REG]]
+; CHECK-NEXT: vmovl.u8  [[QREG:q[0-9]+]], [[REG]]
+; CHECK-NEXT: vrev64.16 [[REG]], [[REG]]
+; CHECK-NEXT: vstr      [[REG]], [r1]
+; CHECK-NEXT: bx        lr
+  %1 = load <4 x i8>, <4 x i8>* %loadaddr
   %2 = zext <4 x i8> %1 to <4 x i16>
   store <4 x i16> %2, <4 x i16>* %storeaddr
   ret void
 }
-
diff --git a/test/CodeGen/ARM/big-endian-neon-trunc-store.ll b/test/CodeGen/ARM/big-endian-neon-trunc-store.ll
index 65147ad5d3f7..cbfc46ed255b 100644
--- a/test/CodeGen/ARM/big-endian-neon-trunc-store.ll
+++ b/test/CodeGen/ARM/big-endian-neon-trunc-store.ll
@@ -6,7 +6,7 @@ define void @vector_trunc_store_2i64_to_2i16( <2 x i64>* %loadaddr, <2 x i16>* %
 ; CHECK:       vrev32.16  [[REG]], [[REG]]
 ; CHECK:       vuzp.16    [[REG]], [[REG2:d[0-9]+]]
 ; CHECK:       vrev32.16  [[REG]], [[REG2]]
-  %1 = load <2 x i64>* %loadaddr
+  %1 = load <2 x i64>, <2 x i64>* %loadaddr
   %2 = trunc <2 x i64> %1 to <2 x i16>
   store <2 x i16> %2, <2 x i16>* %storeaddr
   ret void
@@ -18,7 +18,7 @@ define void @vector_trunc_store_4i32_to_4i8( <4 x i32>* %loadaddr, <4 x i8>* %st
 ; CHECK:       vrev16.8  [[REG]], [[REG]]
 ; CHECK:       vuzp.8    [[REG]], [[REG2:d[0-9]+]]
 ; CHECK:       vrev32.8  [[REG]], [[REG2]]
-  %1 = load <4 x i32>* %loadaddr
+  %1 = load <4 x i32>, <4 x i32>* %loadaddr
   %2 = trunc <4 x i32> %1 to <4 x i8>
   store <4 x i8> %2, <4 x i8>* %storeaddr
   ret void
diff --git a/test/CodeGen/ARM/big-endian-ret-f64.ll b/test/CodeGen/ARM/big-endian-ret-f64.ll
index 614bfc0a5b3a..f83e0864100c 100644
--- a/test/CodeGen/ARM/big-endian-ret-f64.ll
+++ b/test/CodeGen/ARM/big-endian-ret-f64.ll
@@ -6,7 +6,7 @@ define double @fn() {
 ; CHECK: ldr r0, [sp]
 ; CHECK: ldr r1, [sp, #4]
   %r = alloca double, align 8
-  %1 = load double* %r, align 8
+  %1 = load double, double* %r, align 8
   ret double %1
 }
 
diff --git a/test/CodeGen/ARM/big-endian-vector-caller.ll b/test/CodeGen/ARM/big-endian-vector-caller.ll
index d01b0a7c974f..54bda66c54a9 100644
--- a/test/CodeGen/ARM/big-endian-vector-caller.ll
+++ b/test/CodeGen/ARM/big-endian-vector-caller.ll
@@ -7,7 +7,7 @@ define void @test_i64_f64(double* %p, i64* %q) {
 ; SOFT: vadd.f64 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vadd.f64 d0
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = call i64 @test_i64_f64_helper(double %2)
     %4 = add i64 %3, %3
@@ -23,7 +23,7 @@ define void @test_i64_v1i64(<1 x i64>* %p, i64* %q) {
 ; SOFT: vadd.i64 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vadd.i64 d0
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = call i64 @test_i64_v1i64_helper(<1 x i64> %2)
     %4 = add i64 %3, %3
@@ -39,7 +39,7 @@ define void @test_i64_v2f32(<2 x float>* %p, i64* %q) {
 ; SOFT: vrev64.32 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.32 d0
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = call i64 @test_i64_v2f32_helper(<2 x float> %2)
     %4 = add i64 %3, %3
@@ -55,7 +55,7 @@ define void @test_i64_v2i32(<2 x i32>* %p, i64* %q) {
 ; SOFT: vrev64.32 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.32 d0
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = call i64 @test_i64_v2i32_helper(<2 x i32> %2)
     %4 = add i64 %3, %3
@@ -71,7 +71,7 @@ define void @test_i64_v4i16(<4 x i16>* %p, i64* %q) {
 ; SOFT: vrev64.16 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.16 d0
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = call i64 @test_i64_v4i16_helper(<4 x i16> %2)
     %4 = add i64 %3, %3
@@ -87,7 +87,7 @@ define void @test_i64_v8i8(<8 x i8>* %p, i64* %q) {
 ; SOFT: vrev64.8 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.8 d0
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = call i64 @test_i64_v8i8_helper(<8 x i8> %2)
     %4 = add i64 %3, %3
@@ -102,7 +102,7 @@ declare double @test_f64_i64_helper(i64 %p)
 define void @test_f64_i64(i64* %p, double* %q) {
 ; CHECK: adds r1
 ; CHECK: adc r0
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = call double @test_f64_i64_helper(i64 %2)
     %4 = fadd double %3, %3
@@ -119,7 +119,7 @@ define void @test_f64_v1i64(<1 x i64>* %p, double* %q) {
 ; SOFT: vadd.i64 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vadd.i64 d0
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = call double @test_f64_v1i64_helper(<1 x i64> %2)
     %4 = fadd double %3, %3
@@ -136,7 +136,7 @@ define void @test_f64_v2f32(<2 x float>* %p, double* %q) {
 ; SOFT: vrev64.32 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.32 d0
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = call double @test_f64_v2f32_helper(<2 x float> %2)
     %4 = fadd double %3, %3
@@ -153,7 +153,7 @@ define void @test_f64_v2i32(<2 x i32>* %p, double* %q) {
 ; SOFT: vrev64.32 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.32 d0
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = call double @test_f64_v2i32_helper(<2 x i32> %2)
     %4 = fadd double %3, %3
@@ -170,7 +170,7 @@ define void @test_f64_v4i16(<4 x i16>* %p, double* %q) {
 ; SOFT: vrev64.16 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.16 d0
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = call double @test_f64_v4i16_helper(<4 x i16> %2)
     %4 = fadd double %3, %3
@@ -187,7 +187,7 @@ define void @test_f64_v8i8(<8 x i8>* %p, double* %q) {
 ; SOFT: vrev64.8 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.8 d0
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = call double @test_f64_v8i8_helper(<8 x i8> %2)
     %4 = fadd double %3, %3
@@ -203,7 +203,7 @@ declare <1 x i64> @test_v1i64_i64_helper(i64 %p)
 define void @test_v1i64_i64(i64* %p, <1 x i64>* %q) {
 ; CHECK: adds r1
 ; CHECK: adc r0
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = call <1 x i64> @test_v1i64_i64_helper(i64 %2)
     %4 = add <1 x i64> %3, %3
@@ -220,7 +220,7 @@ define void @test_v1i64_f64(double* %p, <1 x i64>* %q) {
 ; SOFT: vadd.f64 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vadd.f64 d0
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = call <1 x i64> @test_v1i64_f64_helper(double %2)
     %4 = add <1 x i64> %3, %3
@@ -237,7 +237,7 @@ define void @test_v1i64_v2f32(<2 x float>* %p, <1 x i64>* %q) {
 ; HARD: vrev64.32 d0
 ; SOFT: vadd.f32 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = call <1 x i64> @test_v1i64_v2f32_helper(<2 x float> %2)
     %4 = add <1 x i64> %3, %3
@@ -255,7 +255,7 @@ define void @test_v1i64_v2i32(<2 x i32>* %p, <1 x i64>* %q) {
 ; SOFT: vadd.i32 [[REG:d[0-9]+]]
 ; SOFT: vrev64.32 [[REG]]
 ; SOFT: vmov r1, r0, [[REG]]
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = call <1 x i64> @test_v1i64_v2i32_helper(<2 x i32> %2)
     %4 = add <1 x i64> %3, %3
@@ -272,7 +272,7 @@ define void @test_v1i64_v4i16(<4 x i16>* %p, <1 x i64>* %q) {
 ; SOFT: vrev64.16 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.16 d0
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = call <1 x i64> @test_v1i64_v4i16_helper(<4 x i16> %2)
     %4 = add <1 x i64> %3, %3
@@ -289,7 +289,7 @@ define void @test_v1i64_v8i8(<8 x i8>* %p, <1 x i64>* %q) {
 ; SOFT: vrev64.8 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.8 d0
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = call <1 x i64> @test_v1i64_v8i8_helper(<8 x i8> %2)
     %4 = add <1 x i64> %3, %3
@@ -305,7 +305,7 @@ declare <2 x float> @test_v2f32_i64_helper(i64 %p)
 define void @test_v2f32_i64(i64* %p, <2 x float>* %q) {
 ; CHECK: adds r1
 ; CHECK: adc r0
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = call <2 x float> @test_v2f32_i64_helper(i64 %2)
     %4 = fadd <2 x float> %3, %3
@@ -322,7 +322,7 @@ define void @test_v2f32_f64(double* %p, <2 x float>* %q) {
 ; SOFT: vadd.f64 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vadd.f64 d0
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = call <2 x float> @test_v2f32_f64_helper(double %2)
     %4 = fadd <2 x float> %3, %3
@@ -339,7 +339,7 @@ define void @test_v2f32_v1i64(<1 x i64>* %p, <2 x float>* %q) {
 ; SOFT: vadd.i64 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vadd.i64 d0
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = call <2 x float> @test_v2f32_v1i64_helper(<1 x i64> %2)
     %4 = fadd <2 x float> %3, %3
@@ -357,7 +357,7 @@ define void @test_v2f32_v2i32(<2 x i32>* %p, <2 x float>* %q) {
 ; SOFT: vadd.i32 [[REG:d[0-9]+]]
 ; SOFT: vrev64.32 [[REG]]
 ; SOFT: vmov r1, r0, [[REG]]
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = call <2 x float> @test_v2f32_v2i32_helper(<2 x i32> %2)
     %4 = fadd <2 x float> %3, %3
@@ -374,7 +374,7 @@ define void @test_v2f32_v4i16(<4 x i16>* %p, <2 x float>* %q) {
 ; SOFT: vrev64.16 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.16 d0
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = call <2 x float> @test_v2f32_v4i16_helper(<4 x i16> %2)
     %4 = fadd <2 x float> %3, %3
@@ -391,7 +391,7 @@ define void @test_v2f32_v8i8(<8 x i8>* %p, <2 x float>* %q) {
 ; SOFT: vrev64.8 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.8 d0
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = call <2 x float> @test_v2f32_v8i8_helper(<8 x i8> %2)
     %4 = fadd <2 x float> %3, %3
@@ -407,7 +407,7 @@ declare <2 x i32> @test_v2i32_i64_helper(i64 %p)
 define void @test_v2i32_i64(i64* %p, <2 x i32>* %q) {
 ; CHECK: adds r1
 ; CHECK: adc r0
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = call <2 x i32> @test_v2i32_i64_helper(i64 %2)
     %4 = add <2 x i32> %3, %3
@@ -424,7 +424,7 @@ define void @test_v2i32_f64(double* %p, <2 x i32>* %q) {
 ; SOFT: vadd.f64 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vadd.f64 d0
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = call <2 x i32> @test_v2i32_f64_helper(double %2)
     %4 = add <2 x i32> %3, %3
@@ -441,7 +441,7 @@ define void @test_v2i32_v1i64(<1 x i64>* %p, <2 x i32>* %q) {
 ; SOFT: vadd.i64 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vadd.i64 d0
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = call <2 x i32> @test_v2i32_v1i64_helper(<1 x i64> %2)
     %4 = add <2 x i32> %3, %3
@@ -460,7 +460,7 @@ define void @test_v2i32_v2f32(<2 x float>* %p, <2 x i32>* %q) {
 ; SOFT: vadd.f32 [[REG:d[0-9]+]]
 ; SOFT: vrev64.32 [[REG]]
 ; SOFT: vmov r1, r0, [[REG]]
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = call <2 x i32> @test_v2i32_v2f32_helper(<2 x float> %2)
     %4 = add <2 x i32> %3, %3
@@ -477,7 +477,7 @@ define void @test_v2i32_v4i16(<4 x i16>* %p, <2 x i32>* %q) {
 ; SOFT: vrev64.16 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.16 d0
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = call <2 x i32> @test_v2i32_v4i16_helper(<4 x i16> %2)
     %4 = add <2 x i32> %3, %3
@@ -494,7 +494,7 @@ define void @test_v2i32_v8i8(<8 x i8>* %p, <2 x i32>* %q) {
 ; SOFT: vrev64.8 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.8 d0
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = call <2 x i32> @test_v2i32_v8i8_helper(<8 x i8> %2)
     %4 = add <2 x i32> %3, %3
@@ -510,7 +510,7 @@ declare <4 x i16> @test_v4i16_i64_helper(i64 %p)
 define void @test_v4i16_i64(i64* %p, <4 x i16>* %q) {
 ; CHECK: adds r1
 ; CHECK: adc r0
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = call <4 x i16> @test_v4i16_i64_helper(i64 %2)
     %4 = add <4 x i16> %3, %3
@@ -527,7 +527,7 @@ define void @test_v4i16_f64(double* %p, <4 x i16>* %q) {
 ; SOFT: vadd.f64 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vadd.f64 d0
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = call <4 x i16> @test_v4i16_f64_helper(double %2)
     %4 = add <4 x i16> %3, %3
@@ -544,7 +544,7 @@ define void @test_v4i16_v1i64(<1 x i64>* %p, <4 x i16>* %q) {
 ; SOFT: vadd.i64 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vadd.i64 d0
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = call <4 x i16> @test_v4i16_v1i64_helper(<1 x i64> %2)
     %4 = add <4 x i16> %3, %3
@@ -563,7 +563,7 @@ define void @test_v4i16_v2f32(<2 x float>* %p, <4 x i16>* %q) {
 ; SOFT: vadd.f32 [[REG:d[0-9]+]]
 ; SOFT: vrev64.32 [[REG]]
 ; SOFT: vmov r1, r0, [[REG]]
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = call <4 x i16> @test_v4i16_v2f32_helper(<2 x float> %2)
     %4 = add <4 x i16> %3, %3
@@ -582,7 +582,7 @@ define void @test_v4i16_v2i32(<2 x i32>* %p, <4 x i16>* %q) {
 ; SOFT: vadd.i32 [[REG:d[0-9]+]]
 ; SOFT: vrev64.32 [[REG]]
 ; SOFT: vmov r1, r0, [[REG]]
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = call <4 x i16> @test_v4i16_v2i32_helper(<2 x i32> %2)
     %4 = add <4 x i16> %3, %3
@@ -599,7 +599,7 @@ define void @test_v4i16_v8i8(<8 x i8>* %p, <4 x i16>* %q) {
 ; SOFT: vrev64.8 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.8 d0
-    %1 = load <8 x i8>* %p
+    %1 = load <8 x i8>, <8 x i8>* %p
     %2 = add <8 x i8> %1, %1
     %3 = call <4 x i16> @test_v4i16_v8i8_helper(<8 x i8> %2)
     %4 = add <4 x i16> %3, %3
@@ -615,7 +615,7 @@ declare <8 x i8> @test_v8i8_i64_helper(i64 %p)
 define void @test_v8i8_i64(i64* %p, <8 x i8>* %q) {
 ; CHECK: adds r1
 ; CHECK: adc r0
-    %1 = load i64* %p
+    %1 = load i64, i64* %p
     %2 = add i64 %1, %1
     %3 = call <8 x i8> @test_v8i8_i64_helper(i64 %2)
     %4 = add <8 x i8> %3, %3
@@ -632,7 +632,7 @@ define void @test_v8i8_f64(double* %p, <8 x i8>* %q) {
 ; SOFT: vadd.f64 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vadd.f64 d0
-    %1 = load double* %p
+    %1 = load double, double* %p
     %2 = fadd double %1, %1
     %3 = call <8 x i8> @test_v8i8_f64_helper(double %2)
     %4 = add <8 x i8> %3, %3
@@ -649,7 +649,7 @@ define void @test_v8i8_v1i64(<1 x i64>* %p, <8 x i8>* %q) {
 ; SOFT: vadd.i64 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vadd.i64 d0
-    %1 = load <1 x i64>* %p
+    %1 = load <1 x i64>, <1 x i64>* %p
     %2 = add <1 x i64> %1, %1
     %3 = call <8 x i8> @test_v8i8_v1i64_helper(<1 x i64> %2)
     %4 = add <8 x i8> %3, %3
@@ -666,7 +666,7 @@ define void @test_v8i8_v2f32(<2 x float>* %p, <8 x i8>* %q) {
 ; SOFT: vrev64.32 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.32 d0
-    %1 = load <2 x float>* %p
+    %1 = load <2 x float>, <2 x float>* %p
     %2 = fadd <2 x float> %1, %1
     %3 = call <8 x i8> @test_v8i8_v2f32_helper(<2 x float> %2)
     %4 = add <8 x i8> %3, %3
@@ -683,7 +683,7 @@ define void @test_v8i8_v2i32(<2 x i32>* %p, <8 x i8>* %q) {
 ; SOFT: vrev64.32 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.32 d0
-    %1 = load <2 x i32>* %p
+    %1 = load <2 x i32>, <2 x i32>* %p
     %2 = add <2 x i32> %1, %1
     %3 = call <8 x i8> @test_v8i8_v2i32_helper(<2 x i32> %2)
     %4 = add <8 x i8> %3, %3
@@ -700,7 +700,7 @@ define void @test_v8i8_v4i16(<4 x i16>* %p, <8 x i8>* %q) {
 ; SOFT: vrev64.16 [[REG:d[0-9]+]]
 ; SOFT: vmov r1, r0, [[REG]]
 ; HARD: vrev64.16 d0
-    %1 = load <4 x i16>* %p
+    %1 = load <4 x i16>, <4 x i16>* %p
     %2 = add <4 x i16> %1, %1
     %3 = call <8 x i8> @test_v8i8_v4i16_helper(<4 x i16> %2)
     %4 = add <8 x i8> %3, %3
@@ -720,7 +720,7 @@ define void @test_f128_v2f64(<2 x double>* %p, fp128* %q) {
 ; SOFT: vmov r3, r2, [[REG2]]
 ; HARD: vadd.f64 d1
 ; HARD: vadd.f64 d0
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = call fp128 @test_f128_v2f64_helper(<2 x double> %2)
     %4 = fadd fp128 %3, %3
@@ -735,7 +735,7 @@ define void @test_f128_v2i64(<2 x i64>* %p, fp128* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vadd.i64 q0
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = call fp128 @test_f128_v2i64_helper(<2 x i64> %2)
     %4 = fadd fp128 %3, %3
@@ -750,7 +750,7 @@ define void @test_f128_v4f32(<4 x float>* %p, fp128* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.32 q0
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = call fp128 @test_f128_v4f32_helper(<4 x float> %2)
     %4 = fadd fp128 %3, %3
@@ -765,7 +765,7 @@ define void @test_f128_v4i32(<4 x i32>* %p, fp128* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.32 q0
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = call fp128 @test_f128_v4i32_helper(<4 x i32> %2)
     %4 = fadd fp128 %3, %3
@@ -780,7 +780,7 @@ define void @test_f128_v8i16(<8 x i16>* %p, fp128* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.16 q0
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = call fp128 @test_f128_v8i16_helper(<8 x i16> %2)
     %4 = fadd fp128 %3, %3
@@ -795,7 +795,7 @@ define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.8 q0
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = call fp128 @test_f128_v16i8_helper(<16 x i8> %2)
     %4 = fadd fp128 %3, %3
@@ -807,7 +807,7 @@ define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) {
 ; CHECK-LABEL: test_v2f64_f128:
 declare <2 x double> @test_v2f64_f128_helper(fp128 %p)
 define void @test_v2f64_f128(fp128* %p, <2 x double>* %q) {
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = call <2 x double> @test_v2f64_f128_helper(fp128 %2)
     %4 = fadd <2 x double> %3, %3
@@ -824,7 +824,7 @@ define void @test_v2f64_v2i64(<2 x i64>* %p, <2 x double>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vadd.i64 q0
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = call <2 x double> @test_v2f64_v2i64_helper(<2 x i64> %2)
     %4 = fadd <2 x double> %3, %3
@@ -840,7 +840,7 @@ define void @test_v2f64_v4f32(<4 x float>* %p, <2 x double>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.32 q0
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = call <2 x double> @test_v2f64_v4f32_helper(<4 x float> %2)
     %4 = fadd <2 x double> %3, %3
@@ -856,7 +856,7 @@ define void @test_v2f64_v4i32(<4 x i32>* %p, <2 x double>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.32 q0
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = call <2 x double> @test_v2f64_v4i32_helper(<4 x i32> %2)
     %4 = fadd <2 x double> %3, %3
@@ -872,7 +872,7 @@ define void @test_v2f64_v8i16(<8 x i16>* %p, <2 x double>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.16 q0
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = call <2 x double> @test_v2f64_v8i16_helper(<8 x i16> %2)
     %4 = fadd <2 x double> %3, %3
@@ -888,7 +888,7 @@ define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.8 q0
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = call <2 x double> @test_v2f64_v16i8_helper(<16 x i8> %2)
     %4 = fadd <2 x double> %3, %3
@@ -901,7 +901,7 @@ define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) {
 ; CHECK-LABEL: test_v2i64_f128:
 declare <2 x i64> @test_v2i64_f128_helper(fp128 %p)
 define void @test_v2i64_f128(fp128* %p, <2 x i64>* %q) {
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = call <2 x i64> @test_v2i64_f128_helper(fp128 %2)
     %4 = add <2 x i64> %3, %3
@@ -918,7 +918,7 @@ define void @test_v2i64_v2f64(<2 x double>* %p, <2 x i64>* %q) {
 ; SOFT: vmov r3, r2, [[REG2]]
 ; HARD: vadd.f64 d1
 ; HARD: vadd.f64 d0
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = call <2 x i64> @test_v2i64_v2f64_helper(<2 x double> %2)
     %4 = add <2 x i64> %3, %3
@@ -934,7 +934,7 @@ define void @test_v2i64_v4f32(<4 x float>* %p, <2 x i64>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.32 q0
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = call <2 x i64> @test_v2i64_v4f32_helper(<4 x float> %2)
     %4 = add <2 x i64> %3, %3
@@ -950,7 +950,7 @@ define void @test_v2i64_v4i32(<4 x i32>* %p, <2 x i64>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.32 q0
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = call <2 x i64> @test_v2i64_v4i32_helper(<4 x i32> %2)
     %4 = add <2 x i64> %3, %3
@@ -966,7 +966,7 @@ define void @test_v2i64_v8i16(<8 x i16>* %p, <2 x i64>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.16 q0
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = call <2 x i64> @test_v2i64_v8i16_helper(<8 x i16> %2)
     %4 = add <2 x i64> %3, %3
@@ -982,7 +982,7 @@ define void @test_v2i64_v16i8(<16 x i8>* %p, <2 x i64>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.8 q0
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = call <2 x i64> @test_v2i64_v16i8_helper(<16 x i8> %2)
     %4 = add <2 x i64> %3, %3
@@ -995,7 +995,7 @@ define void @test_v2i64_v16i8(<16 x i8>* %p, <2 x i64>* %q) {
 ; CHECK-LABEL: test_v4f32_f128:
 declare <4 x float> @test_v4f32_f128_helper(fp128 %p)
 define void @test_v4f32_f128(fp128* %p, <4 x float>* %q) {
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = call <4 x float> @test_v4f32_f128_helper(fp128 %2)
     %4 = fadd <4 x float> %3, %3
@@ -1012,7 +1012,7 @@ define void @test_v4f32_v2f64(<2 x double>* %p, <4 x float>* %q) {
 ; SOFT: vmov r3, r2
 ; HARD: vadd.f64  d1
 ; HARD: vadd.f64  d0
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = call <4 x float> @test_v4f32_v2f64_helper(<2 x double> %2)
     %4 = fadd <4 x float> %3, %3
@@ -1028,7 +1028,7 @@ define void @test_v4f32_v2i64(<2 x i64>* %p, <4 x float>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vadd.i64 q0
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = call <4 x float> @test_v4f32_v2i64_helper(<2 x i64> %2)
     %4 = fadd <4 x float> %3, %3
@@ -1044,7 +1044,7 @@ define void @test_v4f32_v4i32(<4 x i32>* %p, <4 x float>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.32 q0
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = call <4 x float> @test_v4f32_v4i32_helper(<4 x i32> %2)
     %4 = fadd <4 x float> %3, %3
@@ -1060,7 +1060,7 @@ define void @test_v4f32_v8i16(<8 x i16>* %p, <4 x float>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.16 q0
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = call <4 x float> @test_v4f32_v8i16_helper(<8 x i16> %2)
     %4 = fadd <4 x float> %3, %3
@@ -1076,7 +1076,7 @@ define void @test_v4f32_v16i8(<16 x i8>* %p, <4 x float>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.8 q0
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = call <4 x float> @test_v4f32_v16i8_helper(<16 x i8> %2)
     %4 = fadd <4 x float> %3, %3
@@ -1089,7 +1089,7 @@ define void @test_v4f32_v16i8(<16 x i8>* %p, <4 x float>* %q) {
 ; CHECK-LABEL: test_v4i32_f128:
 declare <4 x i32> @test_v4i32_f128_helper(fp128 %p)
 define void @test_v4i32_f128(fp128* %p, <4 x i32>* %q) {
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = call <4 x i32> @test_v4i32_f128_helper(fp128 %2)
     %4 = add <4 x i32> %3, %3
@@ -1106,7 +1106,7 @@ define void @test_v4i32_v2f64(<2 x double>* %p, <4 x i32>* %q) {
 ; SOFT: vmov r3, r2
 ; HARD: vadd.f64 d1
 ; HARD: vadd.f64 d0
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = call <4 x i32> @test_v4i32_v2f64_helper(<2 x double> %2)
     %4 = add <4 x i32> %3, %3
@@ -1122,7 +1122,7 @@ define void @test_v4i32_v2i64(<2 x i64>* %p, <4 x i32>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vadd.i64 q0
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = call <4 x i32> @test_v4i32_v2i64_helper(<2 x i64> %2)
     %4 = add <4 x i32> %3, %3
@@ -1138,7 +1138,7 @@ define void @test_v4i32_v4f32(<4 x float>* %p, <4 x i32>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.32 q0
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = call <4 x i32> @test_v4i32_v4f32_helper(<4 x float> %2)
     %4 = add <4 x i32> %3, %3
@@ -1154,7 +1154,7 @@ define void @test_v4i32_v8i16(<8 x i16>* %p, <4 x i32>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.16 q0
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = call <4 x i32> @test_v4i32_v8i16_helper(<8 x i16> %2)
     %4 = add <4 x i32> %3, %3
@@ -1170,7 +1170,7 @@ define void @test_v4i32_v16i8(<16 x i8>* %p, <4 x i32>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.8 q0
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = call <4 x i32> @test_v4i32_v16i8_helper(<16 x i8> %2)
     %4 = add <4 x i32> %3, %3
@@ -1183,7 +1183,7 @@ define void @test_v4i32_v16i8(<16 x i8>* %p, <4 x i32>* %q) {
 ; CHECK-LABEL: test_v8i16_f128:
 declare <8 x i16> @test_v8i16_f128_helper(fp128 %p)
 define void @test_v8i16_f128(fp128* %p, <8 x i16>* %q) {
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = call <8 x i16> @test_v8i16_f128_helper(fp128 %2)
     %4 = add <8 x i16> %3, %3
@@ -1200,7 +1200,7 @@ define void @test_v8i16_v2f64(<2 x double>* %p, <8 x i16>* %q) {
 ; SOFT: vmov r3, r2
 ; HARD: vadd.f64 d1
 ; HARD: vadd.f64 d0
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = call <8 x i16> @test_v8i16_v2f64_helper(<2 x double> %2)
     %4 = add <8 x i16> %3, %3
@@ -1216,7 +1216,7 @@ define void @test_v8i16_v2i64(<2 x i64>* %p, <8 x i16>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vadd.i64 q0
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = call <8 x i16> @test_v8i16_v2i64_helper(<2 x i64> %2)
     %4 = add <8 x i16> %3, %3
@@ -1232,7 +1232,7 @@ define void @test_v8i16_v4f32(<4 x float>* %p, <8 x i16>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.32 q0
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = call <8 x i16> @test_v8i16_v4f32_helper(<4 x float> %2)
     %4 = add <8 x i16> %3, %3
@@ -1248,7 +1248,7 @@ define void @test_v8i16_v4i32(<4 x i32>* %p, <8 x i16>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.32 q0
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = call <8 x i16> @test_v8i16_v4i32_helper(<4 x i32> %2)
     %4 = add <8 x i16> %3, %3
@@ -1264,7 +1264,7 @@ define void @test_v8i16_v16i8(<16 x i8>* %p, <8 x i16>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.8 q0
-    %1 = load <16 x i8>* %p
+    %1 = load <16 x i8>, <16 x i8>* %p
     %2 = add <16 x i8> %1, %1
     %3 = call <8 x i16> @test_v8i16_v16i8_helper(<16 x i8> %2)
     %4 = add <8 x i16> %3, %3
@@ -1277,7 +1277,7 @@ define void @test_v8i16_v16i8(<16 x i8>* %p, <8 x i16>* %q) {
 ; CHECK-LABEL: test_v16i8_f128:
 declare <16 x i8> @test_v16i8_f128_helper(fp128 %p)
 define void @test_v16i8_f128(fp128* %p, <16 x i8>* %q) {
-    %1 = load fp128* %p
+    %1 = load fp128, fp128* %p
     %2 = fadd fp128 %1, %1
     %3 = call <16 x i8> @test_v16i8_f128_helper(fp128 %2)
     %4 = add <16 x i8> %3, %3
@@ -1294,7 +1294,7 @@ define void @test_v16i8_v2f64(<2 x double>* %p, <16 x i8>* %q) {
 ; SOFT: vmov r3, r2
 ; HARD: vadd.f64 d1
 ; HARD: vadd.f64 d0
-    %1 = load <2 x double>* %p
+    %1 = load <2 x double>, <2 x double>* %p
     %2 = fadd <2 x double> %1, %1
     %3 = call <16 x i8> @test_v16i8_v2f64_helper(<2 x double> %2)
     %4 = add <16 x i8> %3, %3
@@ -1310,7 +1310,7 @@ define void @test_v16i8_v2i64(<2 x i64>* %p, <16 x i8>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vadd.i64 q0
-    %1 = load <2 x i64>* %p
+    %1 = load <2 x i64>, <2 x i64>* %p
     %2 = add <2 x i64> %1, %1
     %3 = call <16 x i8> @test_v16i8_v2i64_helper(<2 x i64> %2)
     %4 = add <16 x i8> %3, %3
@@ -1326,7 +1326,7 @@ define void @test_v16i8_v4f32(<4 x float>* %p, <16 x i8>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.32 q0
-    %1 = load <4 x float>* %p
+    %1 = load <4 x float>, <4 x float>* %p
     %2 = fadd <4 x float> %1, %1
     %3 = call <16 x i8> @test_v16i8_v4f32_helper(<4 x float> %2)
     %4 = add <16 x i8> %3, %3
@@ -1342,7 +1342,7 @@ define void @test_v16i8_v4i32(<4 x i32>* %p, <16 x i8>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.32 q0
-    %1 = load <4 x i32>* %p
+    %1 = load <4 x i32>, <4 x i32>* %p
     %2 = add <4 x i32> %1, %1
     %3 = call <16 x i8> @test_v16i8_v4i32_helper(<4 x i32> %2)
     %4 = add <16 x i8> %3, %3
@@ -1358,7 +1358,7 @@ define void @test_v16i8_v8i16(<8 x i16>* %p, <16 x i8>* %q) {
 ; SOFT: vmov r1, r0
 ; SOFT: vmov r3, r2
 ; HARD: vrev64.16 q0
-    %1 = load <8 x i16>* %p
+    %1 = load <8 x i16>, <8 x i16>* %p
     %2 = add <8 x i16> %1, %1
     %3 = call <16 x i8> @test_v16i8_v8i16_helper(<8 x i16> %2)
     %4 = add <16 x i8> %3, %3
diff --git a/test/CodeGen/ARM/bswap16.ll b/test/CodeGen/ARM/bswap16.ll
index 70c62d294eec..dc0e468b72dc 100644
--- a/test/CodeGen/ARM/bswap16.ll
+++ b/test/CodeGen/ARM/bswap16.ll
@@ -4,7 +4,7 @@
 
 define void @test1(i16* nocapture %data) {
 entry:
-  %0 = load i16* %data, align 2
+  %0 = load i16, i16* %data, align 2
   %1 = tail call i16 @llvm.bswap.i16(i16 %0)
   store i16 %1, i16* %data, align 2
   ret void
@@ -30,7 +30,7 @@ entry:
 
 define i16 @test3(i16* nocapture %data) {
 entry:
-  %0 = load i16* %data, align 2
+  %0 = load i16, i16* %data, align 2
   %1 = tail call i16 @llvm.bswap.i16(i16 %0)
   ret i16 %1
 
diff --git a/test/CodeGen/ARM/build-attributes.ll b/test/CodeGen/ARM/build-attributes.ll
index 2e382308bf51..1982fa98ef41 100644
--- a/test/CodeGen/ARM/build-attributes.ll
+++ b/test/CodeGen/ARM/build-attributes.ll
@@ -7,6 +7,8 @@
 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi | FileCheck %s --check-prefix=V6M
 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST
+; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi | FileCheck %s --check-prefix=V6M
+; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST
 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s | FileCheck %s --check-prefix=ARM1156T2F-S
 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast  | FileCheck %s --check-prefix=ARM1156T2F-S-FAST
 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
@@ -53,9 +55,21 @@
 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0
 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0-FAST
 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
+; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus | FileCheck %s --check-prefix=CORTEX-M0PLUS
+; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0PLUS-FAST
+; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
+; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 | FileCheck %s --check-prefix=CORTEX-M1
+; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M1-FAST
+; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
+; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 | FileCheck %s --check-prefix=SC000
+; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=SC000-FAST
+; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=CORTEX-M3
 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M3-FAST
 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
+; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=sc300 | FileCheck %s --check-prefix=SC300
+; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=sc300  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=SC300-FAST
+; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=sc300 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT
 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M4-SOFT-FAST
 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-M4-HARD
@@ -67,15 +81,26 @@
 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=+fp-only-sp  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M7-FAST
 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CORTEX-M7-DOUBLE
 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
+; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r4 | FileCheck %s --check-prefix=CORTEX-R4
+; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r4f | FileCheck %s --check-prefix=CORTEX-R4F
 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5
 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R5-FAST
 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
+; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 | FileCheck %s --check-prefix=CORTEX-R7
+; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R7-FAST
+; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53
 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A53-FAST
 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57
 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A57-FAST
 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
+; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=CORTEX-A72
+; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A72-FAST
+; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
+; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi | FileCheck %s --check-prefix=GENERIC-ARMV8_1-A
+; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=GENERIC-ARMV8_1-A-FAST
+; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s  --check-prefix=CORTEX-A7-CHECK
 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s  --check-prefix=CORTEX-A7-CHECK-FAST
 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2,-vfp3,-vfp4,-neon | FileCheck %s --check-prefix=CORTEX-A7-NOFPU
@@ -92,10 +117,17 @@
 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi | FileCheck %s --check-prefix=PCS-R9-USE
 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -arm-reserve-r9 | FileCheck %s --check-prefix=PCS-R9-RESERVE
 
+; ARMv8.1a (AArch32)
+; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi | FileCheck %s --check-prefix=NO-STRICT-ALIGN
 ; ARMv8a (AArch32)
 ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
 ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
 ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
 ; ARMv7a
 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
@@ -113,6 +145,11 @@
 ; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s | FileCheck %s --check-prefix=STRICT-ALIGN
 ; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
 ; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
+; ARMv6k
+; RUN: llc < %s -mtriple=armv6k-none-netbsd-gnueabi -mcpu=arm1176j-s | FileCheck %s --check-prefix=NO-STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s | FileCheck %s --check-prefix=STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
 ; ARMv6m
 ; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -arm-no-strict-align -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN
 ; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -arm-strict-align -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN
@@ -162,6 +199,8 @@
 ; V6-FAST-NOT:   .eabi_attribute 22
 ; V6-FAST:   .eabi_attribute 23, 1
 
+;; We emit 6, 12 for both v6-M and v6S-M, technically this is incorrect for
+;; V6-M, however we don't model the OS extension so this is fine.
 ; V6M:  .eabi_attribute 6, 12
 ; V6M-NOT:  .eabi_attribute 7
 ; V6M:  .eabi_attribute 8, 0
@@ -723,6 +762,102 @@
 ; CORTEX-M0-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-M0-FAST:  .eabi_attribute 23, 1
 
+; CORTEX-M0PLUS:  .cpu cortex-m0plus
+; CORTEX-M0PLUS:  .eabi_attribute 6, 12
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 7
+; CORTEX-M0PLUS:  .eabi_attribute 8, 0
+; CORTEX-M0PLUS:  .eabi_attribute 9, 1
+; CORTEX-M0PLUS-NOT:   .eabi_attribute 19
+;; We default to IEEE 754 compliance
+; CORTEX-M0PLUS:  .eabi_attribute 20, 1
+; CORTEX-M0PLUS:  .eabi_attribute 21, 1
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 22
+; CORTEX-M0PLUS:  .eabi_attribute 23, 3
+; CORTEX-M0PLUS:  .eabi_attribute 24, 1
+; CORTEX-M0PLUS:  .eabi_attribute 25, 1
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 27
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 28
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 36
+; CORTEX-M0PLUS:  .eabi_attribute 38, 1
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 42
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 44
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 68
+
+; CORTEX-M0PLUS-FAST-NOT:   .eabi_attribute 19
+;; Despite the M0+ CPU having no FPU in this scenario, we chose to
+;; flush to positive zero here. There's no hardware support doing
+;; this, but the fast maths software library might and such behaviour
+;; would match hardware support on this architecture revision if it
+;; existed.
+; CORTEX-M0PLUS-FAST-NOT:  .eabi_attribute 20
+; CORTEX-M0PLUS-FAST-NOT:  .eabi_attribute 21
+; CORTEX-M0PLUS-FAST-NOT:  .eabi_attribute 22
+; CORTEX-M0PLUS-FAST:  .eabi_attribute 23, 1
+
+; CORTEX-M1:  .cpu cortex-m1
+; CORTEX-M1:  .eabi_attribute 6, 12
+; CORTEX-M1-NOT:  .eabi_attribute 7
+; CORTEX-M1:  .eabi_attribute 8, 0
+; CORTEX-M1:  .eabi_attribute 9, 1
+; CORTEX-M1-NOT:   .eabi_attribute 19
+;; We default to IEEE 754 compliance
+; CORTEX-M1:  .eabi_attribute 20, 1
+; CORTEX-M1:  .eabi_attribute 21, 1
+; CORTEX-M1-NOT:  .eabi_attribute 22
+; CORTEX-M1:  .eabi_attribute 23, 3
+; CORTEX-M1:  .eabi_attribute 24, 1
+; CORTEX-M1:  .eabi_attribute 25, 1
+; CORTEX-M1-NOT:  .eabi_attribute 27
+; CORTEX-M1-NOT:  .eabi_attribute 28
+; CORTEX-M1-NOT:  .eabi_attribute 36
+; CORTEX-M1:  .eabi_attribute 38, 1
+; CORTEX-M1-NOT:  .eabi_attribute 42
+; CORTEX-M1-NOT:  .eabi_attribute 44
+; CORTEX-M1-NOT:  .eabi_attribute 68
+
+; CORTEX-M1-FAST-NOT:   .eabi_attribute 19
+;; Despite the M1 CPU having no FPU in this scenario, we chose to
+;; flush to positive zero here. There's no hardware support doing
+;; this, but the fast maths software library might and such behaviour
+;; would match hardware support on this architecture revision if it
+;; existed.
+; CORTEX-M1-FAST-NOT:  .eabi_attribute 20
+; CORTEX-M1-FAST-NOT:  .eabi_attribute 21
+; CORTEX-M1-FAST-NOT:  .eabi_attribute 22
+; CORTEX-M1-FAST:  .eabi_attribute 23, 1
+
+; SC000:  .cpu sc000
+; SC000:  .eabi_attribute 6, 12
+; SC000-NOT:  .eabi_attribute 7
+; SC000:  .eabi_attribute 8, 0
+; SC000:  .eabi_attribute 9, 1
+; SC000-NOT:   .eabi_attribute 19
+;; We default to IEEE 754 compliance
+; SC000:  .eabi_attribute 20, 1
+; SC000:  .eabi_attribute 21, 1
+; SC000-NOT:  .eabi_attribute 22
+; SC000:  .eabi_attribute 23, 3
+; SC000:  .eabi_attribute 24, 1
+; SC000:  .eabi_attribute 25, 1
+; SC000-NOT:  .eabi_attribute 27
+; SC000-NOT:  .eabi_attribute 28
+; SC000-NOT:  .eabi_attribute 36
+; SC000:  .eabi_attribute 38, 1
+; SC000-NOT:  .eabi_attribute 42
+; SC000-NOT:  .eabi_attribute 44
+; SC000-NOT:  .eabi_attribute 68
+
+; SC000-FAST-NOT:   .eabi_attribute 19
+;; Despite the SC000 CPU having no FPU in this scenario, we chose to
+;; flush to positive zero here. There's no hardware support doing
+;; this, but the fast maths software library might and such behaviour
+;; would match hardware support on this architecture revision if it
+;; existed.
+; SC000-FAST-NOT:  .eabi_attribute 20
+; SC000-FAST-NOT:  .eabi_attribute 21
+; SC000-FAST-NOT:  .eabi_attribute 22
+; SC000-FAST:  .eabi_attribute 23, 1
+
 ; CORTEX-M3:  .cpu cortex-m3
 ; CORTEX-M3:  .eabi_attribute 6, 10
 ; CORTEX-M3:  .eabi_attribute 7, 77
@@ -753,6 +888,36 @@
 ; CORTEX-M3-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-M3-FAST:  .eabi_attribute 23, 1
 
+; SC300:  .cpu sc300
+; SC300:  .eabi_attribute 6, 10
+; SC300:  .eabi_attribute 7, 77
+; SC300:  .eabi_attribute 8, 0
+; SC300:  .eabi_attribute 9, 2
+; SC300-NOT:   .eabi_attribute 19
+;; We default to IEEE 754 compliance
+; SC300:  .eabi_attribute 20, 1
+; SC300:  .eabi_attribute 21, 1
+; SC300-NOT:  .eabi_attribute 22
+; SC300:  .eabi_attribute 23, 3
+; SC300:  .eabi_attribute 24, 1
+; SC300:  .eabi_attribute 25, 1
+; SC300-NOT:  .eabi_attribute 27
+; SC300-NOT:  .eabi_attribute 28
+; SC300-NOT:  .eabi_attribute 36
+; SC300:  .eabi_attribute 38, 1
+; SC300-NOT:  .eabi_attribute 42
+; SC300-NOT:  .eabi_attribute 44
+; SC300-NOT:  .eabi_attribute 68
+
+; SC300-FAST-NOT:   .eabi_attribute 19
+;; Despite there being no FPU, we chose to flush to zero preserving
+;; sign. This matches what the hardware would do for this architecture
+;; revision.
+; SC300-FAST:  .eabi_attribute 20, 2
+; SC300-FAST-NOT:  .eabi_attribute 21
+; SC300-FAST-NOT:  .eabi_attribute 22
+; SC300-FAST:  .eabi_attribute 23, 1
+
 ; CORTEX-M4-SOFT:  .cpu cortex-m4
 ; CORTEX-M4-SOFT:  .eabi_attribute 6, 13
 ; CORTEX-M4-SOFT:  .eabi_attribute 7, 77
@@ -835,6 +1000,7 @@
 ; CORTEX-M7-DOUBLE-NOT: .eabi_attribute 27
 ; CORTEX-M7:  .eabi_attribute 36, 1
 ; CORTEX-M7:  .eabi_attribute 38, 1
+; CORTEX-M7-NOT:  .eabi_attribute 44
 ; CORTEX-M7:  .eabi_attribute 14, 0
 
 ; CORTEX-M7-NOFPU-FAST-NOT:   .eabi_attribute 19
@@ -848,6 +1014,49 @@
 ; CORTEX-M7-NOFPU-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-M7-NOFPU-FAST:  .eabi_attribute 23, 1
 
+; CORTEX-R4:  .cpu cortex-r4
+; CORTEX-R4:  .eabi_attribute 6, 10
+; CORTEX-R4:  .eabi_attribute 7, 82
+; CORTEX-R4:  .eabi_attribute 8, 1
+; CORTEX-R4:  .eabi_attribute 9, 2
+; CORTEX-R4-NOT:  .fpu vfpv3-d16
+; CORTEX-R4-NOT:   .eabi_attribute 19
+;; We default to IEEE 754 compliance
+; CORTEX-R4:  .eabi_attribute 20, 1
+; CORTEX-R4:  .eabi_attribute 21, 1
+; CORTEX-R4-NOT:  .eabi_attribute 22
+; CORTEX-R4:  .eabi_attribute 23, 3
+; CORTEX-R4:  .eabi_attribute 24, 1
+; CORTEX-R4:  .eabi_attribute 25, 1
+; CORTEX-R4-NOT:  .eabi_attribute 28
+; CORTEX-R4-NOT:  .eabi_attribute 36
+; CORTEX-R4:  .eabi_attribute 38, 1
+; CORTEX-R4-NOT:  .eabi_attribute 42
+; CORTEX-R4-NOT:  .eabi_attribute 44
+; CORTEX-R4-NOT:  .eabi_attribute 68
+
+; CORTEX-R4F:  .cpu cortex-r4f
+; CORTEX-R4F:  .eabi_attribute 6, 10
+; CORTEX-R4F:  .eabi_attribute 7, 82
+; CORTEX-R4F:  .eabi_attribute 8, 1
+; CORTEX-R4F:  .eabi_attribute 9, 2
+; CORTEX-R4F:  .fpu vfpv3-d16
+; CORTEX-R4F-NOT:   .eabi_attribute 19
+;; We default to IEEE 754 compliance
+; CORTEX-R4F:  .eabi_attribute 20, 1
+; CORTEX-R4F:  .eabi_attribute 21, 1
+; CORTEX-R4F-NOT:  .eabi_attribute 22
+; CORTEX-R4F:  .eabi_attribute 23, 3
+; CORTEX-R4F:  .eabi_attribute 24, 1
+; CORTEX-R4F:  .eabi_attribute 25, 1
+; CORTEX-R4F:  .eabi_attribute 27, 1
+; CORTEX-R4F-NOT:  .eabi_attribute 28
+; CORTEX-R4F-NOT:  .eabi_attribute 36
+; CORTEX-R4F:  .eabi_attribute 38, 1
+; CORTEX-R4F-NOT:  .eabi_attribute 42
+; CORTEX-R4F-NOT:  .eabi_attribute 44
+; CORTEX-R4F-NOT:  .eabi_attribute 68
+
 ; CORTEX-R5:  .cpu cortex-r5
 ; CORTEX-R5:  .eabi_attribute 6, 10
 ; CORTEX-R5:  .eabi_attribute 7, 82
@@ -877,6 +1086,35 @@
 ; CORTEX-R5-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-R5-FAST:  .eabi_attribute 23, 1
 
+; CORTEX-R7:  .cpu cortex-r7
+; CORTEX-R7:  .eabi_attribute 6, 10
+; CORTEX-R7:  .eabi_attribute 7, 82
+; CORTEX-R7:  .eabi_attribute 8, 1
+; CORTEX-R7:  .eabi_attribute 9, 2
+; CORTEX-R7:  .fpu vfpv3-d16
+; CORTEX-R7-NOT:   .eabi_attribute 19
+;; We default to IEEE 754 compliance
+; CORTEX-R7:  .eabi_attribute 20, 1
+; CORTEX-R7:  .eabi_attribute 21, 1
+; CORTEX-R7-NOT:  .eabi_attribute 22
+; CORTEX-R7:  .eabi_attribute 23, 3
+; CORTEX-R7:  .eabi_attribute 24, 1
+; CORTEX-R7:  .eabi_attribute 25, 1
+; CORTEX-R7:  .eabi_attribute 27, 1
+; CORTEX-R7-NOT:  .eabi_attribute 28
+; CORTEX-R7-NOT:  .eabi_attribute 36
+; CORTEX-R7:  .eabi_attribute 38, 1
+; CORTEX-R7:  .eabi_attribute 42, 1
+; CORTEX-R7:  .eabi_attribute 44, 2
+; CORTEX-R7-NOT:  .eabi_attribute 68
+
+; CORTEX-R7-FAST-NOT:   .eabi_attribute 19
+;; The R7 has the VFPv3 FP unit, which always flushes preserving sign.
+; CORTEX-R7-FAST:  .eabi_attribute 20, 2
+; CORTEX-R7-FAST-NOT:  .eabi_attribute 21
+; CORTEX-R7-FAST-NOT:  .eabi_attribute 22
+; CORTEX-R7-FAST:  .eabi_attribute 23, 1
+
 ; CORTEX-A53:  .cpu cortex-a53
 ; CORTEX-A53:  .eabi_attribute 6, 14
 ; CORTEX-A53:  .eabi_attribute 7, 65
@@ -937,6 +1175,65 @@
 ; CORTEX-A57-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-A57-FAST:  .eabi_attribute 23, 1
 
+; CORTEX-A72:  .cpu cortex-a72
+; CORTEX-A72:  .eabi_attribute 6, 14
+; CORTEX-A72:  .eabi_attribute 7, 65
+; CORTEX-A72:  .eabi_attribute 8, 1
+; CORTEX-A72:  .eabi_attribute 9, 2
+; CORTEX-A72:  .fpu crypto-neon-fp-armv8
+; CORTEX-A72:  .eabi_attribute 12, 3
+; CORTEX-A72-NOT:   .eabi_attribute 19
+;; We default to IEEE 754 compliance
+; CORTEX-A72:  .eabi_attribute 20, 1
+; CORTEX-A72:  .eabi_attribute 21, 1
+; CORTEX-A72-NOT:  .eabi_attribute 22
+; CORTEX-A72:  .eabi_attribute 23, 3
+; CORTEX-A72:  .eabi_attribute 24, 1
+; CORTEX-A72:  .eabi_attribute 25, 1
+; CORTEX-A72-NOT:  .eabi_attribute 27
+; CORTEX-A72-NOT:  .eabi_attribute 28
+; CORTEX-A72:  .eabi_attribute 36, 1
+; CORTEX-A72:  .eabi_attribute 38, 1
+; CORTEX-A72:  .eabi_attribute 42, 1
+; CORTEX-A72-NOT:  .eabi_attribute 44
+; CORTEX-A72:  .eabi_attribute 68, 3
+
+; CORTEX-A72-FAST-NOT:   .eabi_attribute 19
+;; The A72 has the ARMv8 FP unit, which always flushes preserving sign.
+; CORTEX-A72-FAST:  .eabi_attribute 20, 2
+; CORTEX-A72-FAST-NOT:  .eabi_attribute 21
+; CORTEX-A72-FAST-NOT:  .eabi_attribute 22
+; CORTEX-A72-FAST:  .eabi_attribute 23, 1
+
+; GENERIC-ARMV8_1-A:  .eabi_attribute 6, 14
+; GENERIC-ARMV8_1-A:  .eabi_attribute 7, 65
+; GENERIC-ARMV8_1-A:  .eabi_attribute 8, 1
+; GENERIC-ARMV8_1-A:  .eabi_attribute 9, 2
+; GENERIC-ARMV8_1-A:  .fpu crypto-neon-fp-armv8
+; GENERIC-ARMV8_1-A:  .eabi_attribute 12, 4
+; GENERIC-ARMV8_1-A-NOT:   .eabi_attribute 19
+;; We default to IEEE 754 compliance
+; GENERIC-ARMV8_1-A:  .eabi_attribute 20, 1
+; GENERIC-ARMV8_1-A:  .eabi_attribute 21, 1
+; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 22
+; GENERIC-ARMV8_1-A:  .eabi_attribute 23, 3
+; GENERIC-ARMV8_1-A:  .eabi_attribute 24, 1
+; GENERIC-ARMV8_1-A:  .eabi_attribute 25, 1
+; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 27
+; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 28
+; GENERIC-ARMV8_1-A:  .eabi_attribute 36, 1
+; GENERIC-ARMV8_1-A:  .eabi_attribute 38, 1
+; GENERIC-ARMV8_1-A:  .eabi_attribute 42, 1
+; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 44
+; GENERIC-ARMV8_1-A:  .eabi_attribute 68, 3
+
+; GENERIC-ARMV8_1-A-FAST-NOT:   .eabi_attribute 19
+;; GENERIC-ARMV8_1-A has the ARMv8 FP unit, which always flushes preserving sign.
+; GENERIC-ARMV8_1-A-FAST:  .eabi_attribute 20, 2
+; GENERIC-ARMV8_1-A-FAST-NOT:  .eabi_attribute 21
+; GENERIC-ARMV8_1-A-FAST-NOT:  .eabi_attribute 22
+; GENERIC-ARMV8_1-A-FAST:  .eabi_attribute 23, 1
+
 ; RELOC-PIC:  .eabi_attribute 15, 1
 ; RELOC-PIC:  .eabi_attribute 16, 1
 ; RELOC-PIC:  .eabi_attribute 17, 2
diff --git a/test/CodeGen/ARM/bx_fold.ll b/test/CodeGen/ARM/bx_fold.ll
index 5533038fb828..f6651ae8004e 100644
--- a/test/CodeGen/ARM/bx_fold.ll
+++ b/test/CodeGen/ARM/bx_fold.ll
@@ -6,7 +6,7 @@ entry:
 
 bb:		; preds = %bb1
 	%gep.upgrd.1 = zext i32 %indvar to i64		; <i64> [#uses=1]
-	%tmp7 = getelementptr i8* %L, i64 %gep.upgrd.1		; <i8*> [#uses=1]
+	%tmp7 = getelementptr i8, i8* %L, i64 %gep.upgrd.1		; <i8*> [#uses=1]
 	store i8 0, i8* %tmp7
 	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=1]
 	br label %bb1
@@ -14,7 +14,7 @@ bb:		; preds = %bb1
 bb1:		; preds = %bb, %entry
 	%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]		; <i32> [#uses=3]
 	%i.0 = bitcast i32 %indvar to i32		; <i32> [#uses=2]
-	%tmp = tail call i32 (...)* @bar( )		; <i32> [#uses=1]
+	%tmp = tail call i32 (...) @bar( )		; <i32> [#uses=1]
 	%tmp2 = add i32 %i.0, %tmp		; <i32> [#uses=1]
 	%Ptr_addr.0 = sub i32 %Ptr, %tmp2		; <i32> [#uses=0]
 	%tmp12 = icmp eq i32 %i.0, %Ptr		; <i1> [#uses=1]
diff --git a/test/CodeGen/ARM/byval-align.ll b/test/CodeGen/ARM/byval-align.ll
new file mode 100644
index 000000000000..a26b5a795756
--- /dev/null
+++ b/test/CodeGen/ARM/byval-align.ll
@@ -0,0 +1,76 @@
+; RUN: llc -mtriple=thumbv7-apple-ios8.0 %s -o - | FileCheck %s
+
+; This checks that alignments greater than 4 are respected by APCS
+; targets. Mostly here to make sure *some* correct code is created after some
+; simplifying refactoring; at the time of writing there were no actual APCS
+; users of byval alignments > 4, so no real calls for ABI stability.
+
+; "byval align 16" can't fit in any regs with an i8* taking up r0.
+define i32 @test_align16(i8*, [4 x i32]* byval align 16 %b) {
+; CHECK-LABEL: test_align16:
+; CHECK-NOT: sub sp
+; CHECK: push {r4, r7, lr}
+; CHECK: add r7, sp, #4
+
+; CHECK: ldr r0, [r7, #8]
+
+  call void @bar()
+  %valptr = getelementptr [4 x i32], [4 x i32]* %b, i32 0, i32 0
+  %val = load i32, i32* %valptr
+  ret i32 %val
+}
+
+; byval align 8 can, but we used to incorrectly set r7 here (miscalculating the
+; space taken up by arg regs).
+define i32 @test_align8(i8*, [4 x i32]* byval align 8 %b) {
+; CHECK-LABEL: test_align8:
+; CHECK: sub sp, #8
+; CHECK: push {r4, r7, lr}
+; CHECK: add r7, sp, #4
+
+; CHECK-DAG: str r2, [r7, #8]
+; CHECK-DAG: str r3, [r7, #12]
+
+; CHECK: ldr r0, [r7, #8]
+
+  call void @bar()
+  %valptr = getelementptr [4 x i32], [4 x i32]* %b, i32 0, i32 0
+  %val = load i32, i32* %valptr
+  ret i32 %val
+}
+
+; "byval align 32" can't fit in regs no matter what: it would be misaligned
+; unless the incoming stack was deliberately misaligned.
+define i32 @test_align32(i8*, [4 x i32]* byval align 32 %b) {
+; CHECK-LABEL: test_align32:
+; CHECK-NOT: sub sp
+; CHECK: push {r4, r7, lr}
+; CHECK: add r7, sp, #4
+
+; CHECK: ldr r0, [r7, #8]
+
+  call void @bar()
+  %valptr = getelementptr [4 x i32], [4 x i32]* %b, i32 0, i32 0
+  %val = load i32, i32* %valptr
+  ret i32 %val
+}
+
+; When passing an object "byval align N", the stack must be at least N-aligned.
+define void @test_call_align16() {
+; CHECK-LABEL: test_call_align16:
+; CHECK: push {r4, r7, lr}
+; CHECK: add r7, sp, #4
+
+; CHECK: mov [[TMP:r[0-9]+]], sp
+; CHECK: bfc [[TMP]], #0, #4
+; CHECK: mov sp, [[TMP]]
+
+; While we're here, make sure the caller also puts it at sp
+  ; CHECK: mov r[[BASE:[0-9]+]], sp
+  ; CHECK: vst1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]]
+  call i32 @test_align16(i8* null, [4 x i32]* byval align 16 @var)
+  ret void
+}
+
+@var = global [4 x i32] zeroinitializer
+declare void @bar()
diff --git a/test/CodeGen/ARM/cache-intrinsic.ll b/test/CodeGen/ARM/cache-intrinsic.ll
index 6048917ee9a3..12b55c7081db 100644
--- a/test/CodeGen/ARM/cache-intrinsic.ll
+++ b/test/CodeGen/ARM/cache-intrinsic.ll
@@ -10,10 +10,10 @@ define i32 @main() {
 entry:
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0))
-  %call1 = call i8* @strcpy(i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds ([25 x i8]* @.str1, i32 0, i32 0)) #3
-  call void @llvm.clear_cache(i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds (i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0), i32 32)) #3
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0))
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0))
+  %call1 = call i8* @strcpy(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str1, i32 0, i32 0)) #3
+  call void @llvm.clear_cache(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds (i8, i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i32 32)) #3
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0))
   ret i32 0
 }
 
diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll
index a35fd7476465..b2b6aaec8131 100644
--- a/test/CodeGen/ARM/call-tc.ll
+++ b/test/CodeGen/ARM/call-tc.ll
@@ -24,7 +24,7 @@ define void @t2() {
 ; CHECKT2D: ldr
 ; CHECKT2D-NEXT: ldr
 ; CHECKT2D-NEXT: bx r0
-        %tmp = load i32 ()** @t         ; <i32 ()*> [#uses=1]
+        %tmp = load i32 ()*, i32 ()** @t         ; <i32 ()*> [#uses=1]
         %tmp.upgrd.2 = tail call i32 %tmp( )            ; <i32> [#uses=0]
         ret void
 }
@@ -153,7 +153,7 @@ define i32 @t9() nounwind {
 ; CHECKT2D: b.w ___divsi3
   %lock = alloca %class.MutexLock, align 1
   %1 = call %class.MutexLock* @_ZN9MutexLockC1Ev(%class.MutexLock* %lock)
-  %2 = load i32* @x, align 4
+  %2 = load i32, i32* @x, align 4
   %3 = sdiv i32 1000, %2
   %4 = call %class.MutexLock* @_ZN9MutexLockD1Ev(%class.MutexLock* %lock)
   ret i32 %3
@@ -170,7 +170,7 @@ define float @libcall_tc_test2(float* nocapture %a, float %b) {
 ; CHECKT2D-LABEL: libcall_tc_test2:
 ; CHECKT2D: blx _floorf
 ; CHECKT2D: b.w _truncf
-  %1 = load float* %a, align 4
+  %1 = load float, float* %a, align 4
   %call = tail call float @floorf(float %1)
   store float %call, float* %a, align 4
   %call1 = tail call float @truncf(float %b)
diff --git a/test/CodeGen/ARM/call.ll b/test/CodeGen/ARM/call.ll
index f6301cf02032..87252a91e1b0 100644
--- a/test/CodeGen/ARM/call.ll
+++ b/test/CodeGen/ARM/call.ll
@@ -20,7 +20,7 @@ define void @f() {
 define void @g.upgrd.1() {
 ; CHECKV4: mov lr, pc
 ; CHECKV5: blx
-        %tmp = load i32 ()** @t         ; <i32 ()*> [#uses=1]
+        %tmp = load i32 ()*, i32 ()** @t         ; <i32 ()*> [#uses=1]
         %tmp.upgrd.2 = call i32 %tmp( )            ; <i32> [#uses=0]
         ret void
 }
@@ -30,10 +30,10 @@ define i32* @m_231b(i32, i32, i32*, i32*, i32*) nounwind {
 ; CHECKV4: bx r{{.*}}
 BB0:
   %5 = inttoptr i32 %0 to i32*                    ; <i32*> [#uses=1]
-  %t35 = load volatile i32* %5                    ; <i32> [#uses=1]
+  %t35 = load volatile i32, i32* %5                    ; <i32> [#uses=1]
   %6 = inttoptr i32 %t35 to i32**                 ; <i32**> [#uses=1]
-  %7 = getelementptr i32** %6, i32 86             ; <i32**> [#uses=1]
-  %8 = load i32** %7                              ; <i32*> [#uses=1]
+  %7 = getelementptr i32*, i32** %6, i32 86             ; <i32**> [#uses=1]
+  %8 = load i32*, i32** %7                              ; <i32*> [#uses=1]
   %9 = bitcast i32* %8 to i32* (i32, i32*, i32, i32*, i32*, i32*)* ; <i32* (i32, i32*, i32, i32*, i32*, i32*)*> [#uses=1]
   %10 = call i32* %9(i32 %0, i32* null, i32 %1, i32* %2, i32* %3, i32* %4) ; <i32*> [#uses=1]
   ret i32* %10
diff --git a/test/CodeGen/ARM/call_nolink.ll b/test/CodeGen/ARM/call_nolink.ll
index 48fa3a62ffb0..0cd5bcd086c8 100644
--- a/test/CodeGen/ARM/call_nolink.ll
+++ b/test/CodeGen/ARM/call_nolink.ll
@@ -22,32 +22,32 @@ bb115.i.i.bb115.i.i_crit_edge:		; preds = %bb115.i.i
 
 bb115.i.i:		; preds = %bb115.i.i.bb115.i.i_crit_edge, %newFuncRoot
 	%i_addr.3210.0.i.i = phi i32 [ %tmp166.i.i, %bb115.i.i.bb115.i.i_crit_edge ], [ 0, %newFuncRoot ]		; <i32> [#uses=7]
-	%tmp124.i.i = getelementptr [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 0		; <i32*> [#uses=1]
-	%tmp125.i.i = load i32* %tmp124.i.i		; <i32> [#uses=1]
-	%tmp126.i.i = getelementptr [14 x i32]* @r, i32 0, i32 %tmp125.i.i		; <i32*> [#uses=1]
-	%tmp127.i.i = load i32* %tmp126.i.i		; <i32> [#uses=1]
-	%tmp131.i.i = getelementptr [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 1		; <i32*> [#uses=1]
-	%tmp132.i.i = load i32* %tmp131.i.i		; <i32> [#uses=1]
-	%tmp133.i.i = getelementptr [14 x i32]* @r, i32 0, i32 %tmp132.i.i		; <i32*> [#uses=1]
-	%tmp134.i.i = load i32* %tmp133.i.i		; <i32> [#uses=1]
-	%tmp138.i.i = getelementptr [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 2		; <i32*> [#uses=1]
-	%tmp139.i.i = load i32* %tmp138.i.i		; <i32> [#uses=1]
-	%tmp140.i.i = getelementptr [14 x i32]* @r, i32 0, i32 %tmp139.i.i		; <i32*> [#uses=1]
-	%tmp141.i.i = load i32* %tmp140.i.i		; <i32> [#uses=1]
+	%tmp124.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 0		; <i32*> [#uses=1]
+	%tmp125.i.i = load i32, i32* %tmp124.i.i		; <i32> [#uses=1]
+	%tmp126.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp125.i.i		; <i32*> [#uses=1]
+	%tmp127.i.i = load i32, i32* %tmp126.i.i		; <i32> [#uses=1]
+	%tmp131.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 1		; <i32*> [#uses=1]
+	%tmp132.i.i = load i32, i32* %tmp131.i.i		; <i32> [#uses=1]
+	%tmp133.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp132.i.i		; <i32*> [#uses=1]
+	%tmp134.i.i = load i32, i32* %tmp133.i.i		; <i32> [#uses=1]
+	%tmp138.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 2		; <i32*> [#uses=1]
+	%tmp139.i.i = load i32, i32* %tmp138.i.i		; <i32> [#uses=1]
+	%tmp140.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp139.i.i		; <i32*> [#uses=1]
+	%tmp141.i.i = load i32, i32* %tmp140.i.i		; <i32> [#uses=1]
 	%tmp143.i.i = add i32 %i_addr.3210.0.i.i, 12		; <i32> [#uses=1]
-	%tmp146.i.i = getelementptr [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 0		; <i32*> [#uses=1]
-	%tmp147.i.i = load i32* %tmp146.i.i		; <i32> [#uses=1]
-	%tmp149.i.i = getelementptr [13 x %struct.anon]* @isa, i32 0, i32 %tmp147.i.i, i32 0		; <i32 (i32, i32, i32)**> [#uses=1]
-	%tmp150.i.i = load i32 (i32, i32, i32)** %tmp149.i.i		; <i32 (i32, i32, i32)*> [#uses=1]
+	%tmp146.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 0		; <i32*> [#uses=1]
+	%tmp147.i.i = load i32, i32* %tmp146.i.i		; <i32> [#uses=1]
+	%tmp149.i.i = getelementptr [13 x %struct.anon], [13 x %struct.anon]* @isa, i32 0, i32 %tmp147.i.i, i32 0		; <i32 (i32, i32, i32)**> [#uses=1]
+	%tmp150.i.i = load i32 (i32, i32, i32)*, i32 (i32, i32, i32)** %tmp149.i.i		; <i32 (i32, i32, i32)*> [#uses=1]
 	%tmp154.i.i = tail call i32 %tmp150.i.i( i32 %tmp127.i.i, i32 %tmp134.i.i, i32 %tmp141.i.i )		; <i32> [#uses=1]
-	%tmp155.i.i = getelementptr [14 x i32]* @r, i32 0, i32 %tmp143.i.i		; <i32*> [#uses=1]
+	%tmp155.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp143.i.i		; <i32*> [#uses=1]
 	store i32 %tmp154.i.i, i32* %tmp155.i.i
-	%tmp159.i.i = getelementptr [2 x i32]* @counter, i32 0, i32 %i_addr.3210.0.i.i		; <i32*> [#uses=2]
-	%tmp160.i.i = load i32* %tmp159.i.i		; <i32> [#uses=1]
+	%tmp159.i.i = getelementptr [2 x i32], [2 x i32]* @counter, i32 0, i32 %i_addr.3210.0.i.i		; <i32*> [#uses=2]
+	%tmp160.i.i = load i32, i32* %tmp159.i.i		; <i32> [#uses=1]
 	%tmp161.i.i = add i32 %tmp160.i.i, 1		; <i32> [#uses=1]
 	store i32 %tmp161.i.i, i32* %tmp159.i.i
 	%tmp166.i.i = add i32 %i_addr.3210.0.i.i, 1		; <i32> [#uses=2]
-	%tmp168.i.i = load i32* @numi		; <i32> [#uses=1]
+	%tmp168.i.i = load i32, i32* @numi		; <i32> [#uses=1]
 	icmp slt i32 %tmp166.i.i, %tmp168.i.i		; <i1>:0 [#uses=1]
 	br i1 %0, label %bb115.i.i.bb115.i.i_crit_edge, label %bb115.i.i.bb170.i.i_crit_edge.exitStub
 }
diff --git a/test/CodeGen/ARM/coalesce-dbgvalue.ll b/test/CodeGen/ARM/coalesce-dbgvalue.ll
index 4e5fb5e5c60f..cd2ab257207a 100644
--- a/test/CodeGen/ARM/coalesce-dbgvalue.ll
+++ b/test/CodeGen/ARM/coalesce-dbgvalue.ll
@@ -27,11 +27,11 @@ for.cond1:                                        ; preds = %for.end9, %for.cond
 
 for.body2:                                        ; preds = %for.cond1
   store i32 %storemerge11, i32* @b, align 4, !dbg !26
-  tail call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !28
-  %0 = load i64* @a, align 8, !dbg !29
+  tail call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !11, metadata !DIExpression()), !dbg !28
+  %0 = load i64, i64* @a, align 8, !dbg !29
   %xor = xor i64 %0, %e.1.ph, !dbg !29
   %conv3 = trunc i64 %xor to i32, !dbg !29
-  tail call void @llvm.dbg.value(metadata i32 %conv3, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !29
+  tail call void @llvm.dbg.value(metadata i32 %conv3, i64 0, metadata !10, metadata !DIExpression()), !dbg !29
   %tobool4 = icmp eq i32 %conv3, 0, !dbg !29
   br i1 %tobool4, label %land.end, label %land.rhs, !dbg !29
 
@@ -44,7 +44,7 @@ land.end:                                         ; preds = %land.rhs, %for.body
   %1 = phi i1 [ false, %for.body2 ], [ %tobool5, %land.rhs ]
   %land.ext = zext i1 %1 to i32
   %call6 = tail call i32 bitcast (i32 (...)* @fn2 to i32 (i32, i32*)*)(i32 %land.ext, i32* null) #3
-  %2 = load i32* @b, align 4, !dbg !26
+  %2 = load i32, i32* @b, align 4, !dbg !26
   %inc8 = add nsw i32 %2, 1, !dbg !26
   %phitmp = and i64 %xor, 4294967295, !dbg !26
   br label %for.cond1.outer, !dbg !26
@@ -52,7 +52,7 @@ land.end:                                         ; preds = %land.rhs, %for.body
 for.cond1.outer:                                  ; preds = %land.end, %for.cond1.preheader
   %storemerge11.ph = phi i32 [ %inc8, %land.end ], [ 0, %for.cond1.preheader ]
   %e.1.ph = phi i64 [ %phitmp, %land.end ], [ 0, %for.cond1.preheader ]
-  %3 = load i32* @d, align 4, !dbg !31
+  %3 = load i32, i32* @d, align 4, !dbg !31
   %tobool10 = icmp eq i32 %3, 0, !dbg !31
   br label %for.cond1
 
@@ -79,33 +79,33 @@ attributes #3 = { nounwind }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!33}
 
-!0 = !{!"0x11\0012\00clang version 3.4 (trunk 182024) (llvm/trunk 182023)\001\00\000\00\000", !1, !2, !2, !3, !15, !2} ; [ DW_TAG_compile_unit ] [/d/b/pr16110.c] [DW_LANG_C99]
-!1 = !{!"pr16110.c", !"/d/b"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 182024) (llvm/trunk 182023)", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !15, imports: !2)
+!1 = !DIFile(filename: "pr16110.c", directory: "/d/b")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00pr16110\00pr16110\00\007\000\001\000\006\000\001\007", !1, !5, !6, null, i32 ()* @pr16110, null, null, !9} ; [ DW_TAG_subprogram ] [line 7] [def] [pr16110]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/d/b/pr16110.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "pr16110", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 7, file: !1, scope: !5, type: !6, function: i32 ()* @pr16110, variables: !9)
+!5 = !DIFile(filename: "pr16110.c", directory: "/d/b")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{!10, !11}
-!10 = !{!"0x100\00e\008\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [e] [line 8]
-!11 = !{!"0x100\00f\0013\000", !12, !5, !14} ; [ DW_TAG_auto_variable ] [f] [line 13]
-!12 = !{!"0xb\0012\000\002", !1, !13} ; [ DW_TAG_lexical_block ] [/d/b/pr16110.c]
-!13 = !{!"0xb\0012\000\001", !1, !4} ; [ DW_TAG_lexical_block ] [/d/b/pr16110.c]
-!14 = !{!"0xf\00\000\0032\0032\000\000", null, null, !8} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from int]
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "e", line: 8, scope: !4, file: !5, type: !8)
+!11 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "f", line: 13, scope: !12, file: !5, type: !14)
+!12 = distinct !DILexicalBlock(line: 12, column: 0, file: !1, scope: !13)
+!13 = distinct !DILexicalBlock(line: 12, column: 0, file: !1, scope: !4)
+!14 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !8)
 !15 = !{!16, !18, !19, !20}
-!16 = !{!"0x34\00a\00a\00\001\000\001", null, !5, !17, i64* @a, null} ; [ DW_TAG_variable ] [a] [line 1] [def]
-!17 = !{!"0x24\00long long int\000\0064\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [long long int] [line 0, size 64, align 32, offset 0, enc DW_ATE_signed]
-!18 = !{!"0x34\00b\00b\00\002\000\001", null, !5, !8, i32* @b, null} ; [ DW_TAG_variable ] [b] [line 2] [def]
-!19 = !{!"0x34\00c\00c\00\003\000\001", null, !5, !8, i32* @c, null} ; [ DW_TAG_variable ] [c] [line 3] [def]
-!20 = !{!"0x34\00d\00d\00\004\000\001", null, !5, !8, i32* @d, null} ; [ DW_TAG_variable ] [d] [line 4] [def]
-!21 = !MDLocation(line: 10, scope: !22)
-!22 = !{!"0xb\0010\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/d/b/pr16110.c]
-!26 = !MDLocation(line: 12, scope: !13)
+!16 = !DIGlobalVariable(name: "a", line: 1, isLocal: false, isDefinition: true, scope: null, file: !5, type: !17, variable: i64* @a)
+!17 = !DIBasicType(tag: DW_TAG_base_type, name: "long long int", size: 64, align: 32, encoding: DW_ATE_signed)
+!18 = !DIGlobalVariable(name: "b", line: 2, isLocal: false, isDefinition: true, scope: null, file: !5, type: !8, variable: i32* @b)
+!19 = !DIGlobalVariable(name: "c", line: 3, isLocal: false, isDefinition: true, scope: null, file: !5, type: !8, variable: i32* @c)
+!20 = !DIGlobalVariable(name: "d", line: 4, isLocal: false, isDefinition: true, scope: null, file: !5, type: !8, variable: i32* @d)
+!21 = !DILocation(line: 10, scope: !22)
+!22 = distinct !DILexicalBlock(line: 10, column: 0, file: !1, scope: !4)
+!26 = !DILocation(line: 12, scope: !13)
 !27 = !{i32* null}
-!28 = !MDLocation(line: 13, scope: !12)
-!29 = !MDLocation(line: 14, scope: !12)
-!31 = !MDLocation(line: 16, scope: !4)
-!32 = !MDLocation(line: 18, scope: !4)
-!33 = !{i32 1, !"Debug Info Version", i32 2}
+!28 = !DILocation(line: 13, scope: !12)
+!29 = !DILocation(line: 14, scope: !12)
+!31 = !DILocation(line: 16, scope: !4)
+!32 = !DILocation(line: 18, scope: !4)
+!33 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/ARM/coalesce-subregs.ll b/test/CodeGen/ARM/coalesce-subregs.ll
index e7bd5f41bb4b..72fefeacfc5b 100644
--- a/test/CodeGen/ARM/coalesce-subregs.ll
+++ b/test/CodeGen/ARM/coalesce-subregs.ll
@@ -16,7 +16,7 @@ entry:
   %0 = bitcast float* %p to i8*
   %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
   %vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
-  %add.ptr = getelementptr inbounds float* %p, i32 8
+  %add.ptr = getelementptr inbounds float, float* %p, i32 8
   %1 = bitcast float* %add.ptr to i8*
   tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> undef, i32 4)
   ret void
@@ -29,7 +29,7 @@ entry:
   %0 = bitcast float* %p to i8*
   %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
   %vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
-  %add.ptr = getelementptr inbounds float* %p, i32 8
+  %add.ptr = getelementptr inbounds float, float* %p, i32 8
   %1 = bitcast float* %add.ptr to i8*
   %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4)
   %vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0
@@ -50,7 +50,7 @@ do.body:                                          ; preds = %do.body, %entry
   %qq0.0.1.0 = phi <4 x float> [ %vld224, %entry ], [ %vld2216, %do.body ]
   %c.addr.0 = phi i32 [ %c, %entry ], [ %dec, %do.body ]
   %p.addr.0 = phi float* [ %p, %entry ], [ %add.ptr, %do.body ]
-  %add.ptr = getelementptr inbounds float* %p.addr.0, i32 8
+  %add.ptr = getelementptr inbounds float, float* %p.addr.0, i32 8
   %1 = bitcast float* %add.ptr to i8*
   %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4)
   %vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0
@@ -85,29 +85,29 @@ declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounw
 ; CHECK-NOT: vorr
 define void @f3(float* %p, float* %q) nounwind ssp {
 entry:
-  %arrayidx = getelementptr inbounds float* %p, i32 3
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %p, i32 3
+  %0 = load float, float* %arrayidx, align 4
   %vecins = insertelement <2 x float> undef, float %0, i32 1
   %tobool = icmp eq float* %q, null
   br i1 %tobool, label %if.else, label %if.then
 
 if.then:                                          ; preds = %entry
-  %1 = load float* %q, align 4
-  %arrayidx2 = getelementptr inbounds float* %q, i32 1
-  %2 = load float* %arrayidx2, align 4
+  %1 = load float, float* %q, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %q, i32 1
+  %2 = load float, float* %arrayidx2, align 4
   %add = fadd float %1, %2
   %vecins3 = insertelement <2 x float> %vecins, float %add, i32 0
   br label %if.end
 
 if.else:                                          ; preds = %entry
-  %arrayidx4 = getelementptr inbounds float* %p, i32 2
-  %3 = load float* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds float, float* %p, i32 2
+  %3 = load float, float* %arrayidx4, align 4
   %vecins5 = insertelement <2 x float> %vecins, float %3, i32 0
   br label %if.end
 
 if.end:                                           ; preds = %if.else, %if.then
   %x.0 = phi <2 x float> [ %vecins3, %if.then ], [ %vecins5, %if.else ]
-  %add.ptr = getelementptr inbounds float* %p, i32 4
+  %add.ptr = getelementptr inbounds float, float* %p, i32 4
   %4 = bitcast float* %add.ptr to i8*
   tail call void @llvm.arm.neon.vst1.v2f32(i8* %4, <2 x float> %x.0, i32 4)
   ret void
@@ -129,9 +129,9 @@ entry:
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry
-  %1 = load float* %q, align 4
-  %arrayidx1 = getelementptr inbounds float* %q, i32 1
-  %2 = load float* %arrayidx1, align 4
+  %1 = load float, float* %q, align 4
+  %arrayidx1 = getelementptr inbounds float, float* %q, i32 1
+  %2 = load float, float* %arrayidx1, align 4
   %add = fadd float %1, %2
   %vecins = insertelement <2 x float> %vld1, float %add, i32 1
   br label %if.end
@@ -164,13 +164,13 @@ entry:
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry
-  %arrayidx = getelementptr inbounds float* %q, i32 1
-  %1 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %q, i32 1
+  %1 = load float, float* %arrayidx, align 4
   %add4 = fadd float %vecext, %1
-  %2 = load float* %q, align 4
+  %2 = load float, float* %q, align 4
   %add6 = fadd float %vecext1, %2
-  %arrayidx7 = getelementptr inbounds float* %q, i32 2
-  %3 = load float* %arrayidx7, align 4
+  %arrayidx7 = getelementptr inbounds float, float* %q, i32 2
+  %3 = load float, float* %arrayidx7, align 4
   %add8 = fadd float %vecext2, %3
   br label %if.end
 
@@ -231,7 +231,7 @@ bb3:                                              ; preds = %bb12, %bb
   br i1 undef, label %bb10, label %bb12
 
 bb10:                                             ; preds = %bb3
-  %tmp11 = load <4 x float>* undef, align 8
+  %tmp11 = load <4 x float>, <4 x float>* undef, align 8
   br label %bb12
 
 bb12:                                             ; preds = %bb10, %bb3
@@ -293,7 +293,6 @@ bb:
 ; CHECK: adjustCopiesBackFrom
 ; The shuffle in if.else3 must be preserved even though adjustCopiesBackFrom
 ; is tempted to remove it.
-; CHECK: %if.else3
 ; CHECK: vorr d
 define internal void @adjustCopiesBackFrom(<2 x i64>* noalias nocapture sret %agg.result, <2 x i64> %in) {
 entry:
@@ -334,7 +333,7 @@ for.body:                                         ; preds = %for.end, %entry
   br i1 undef, label %for.body29, label %for.end
 
 for.body29:                                       ; preds = %for.body29, %for.body
-  %0 = load <2 x double>* null, align 1
+  %0 = load <2 x double>, <2 x double>* null, align 1
   %splat40 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer
   %mul41 = fmul <2 x double> undef, %splat40
   %add42 = fadd <2 x double> undef, %mul41
diff --git a/test/CodeGen/ARM/code-placement.ll b/test/CodeGen/ARM/code-placement.ll
index 70d85c91c8ca..bf5cf52d8b54 100644
--- a/test/CodeGen/ARM/code-placement.ll
+++ b/test/CodeGen/ARM/code-placement.ll
@@ -18,8 +18,8 @@ bb:
 ; CHECK: bx lr
   %list_addr.05 = phi %struct.list_head* [ %2, %bb ], [ %list, %entry ]
   %next.04 = phi %struct.list_head* [ %list_addr.05, %bb ], [ null, %entry ]
-  %1 = getelementptr inbounds %struct.list_head* %list_addr.05, i32 0, i32 0
-  %2 = load %struct.list_head** %1, align 4
+  %1 = getelementptr inbounds %struct.list_head, %struct.list_head* %list_addr.05, i32 0, i32 0
+  %2 = load %struct.list_head*, %struct.list_head** %1, align 4
   store %struct.list_head* %next.04, %struct.list_head** %1, align 4
   %3 = icmp eq %struct.list_head* %2, null
   br i1 %3, label %bb2, label %bb
@@ -45,8 +45,8 @@ bb1:                                              ; preds = %bb2.preheader, %bb1
   %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %bb2.preheader ] ; <i32> [#uses=2]
   %sum.08 = phi i32 [ %2, %bb1 ], [ %sum.110, %bb2.preheader ] ; <i32> [#uses=1]
   %tmp17 = sub i32 %i.07, %indvar                 ; <i32> [#uses=1]
-  %scevgep = getelementptr i32* %src, i32 %tmp17  ; <i32*> [#uses=1]
-  %1 = load i32* %scevgep, align 4                ; <i32> [#uses=1]
+  %scevgep = getelementptr i32, i32* %src, i32 %tmp17  ; <i32*> [#uses=1]
+  %1 = load i32, i32* %scevgep, align 4                ; <i32> [#uses=1]
   %2 = add nsw i32 %1, %sum.08                    ; <i32> [#uses=2]
   %indvar.next = add i32 %indvar, 1               ; <i32> [#uses=2]
   %exitcond = icmp eq i32 %indvar.next, %size     ; <i1> [#uses=1]
diff --git a/test/CodeGen/ARM/combine-movc-sub.ll b/test/CodeGen/ARM/combine-movc-sub.ll
new file mode 100644
index 000000000000..6a5f7bdd38e9
--- /dev/null
+++ b/test/CodeGen/ARM/combine-movc-sub.ll
@@ -0,0 +1,63 @@
+; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7s-apple-unknown"
+
+; The subtract instruction %3 will be optimized (combined and predicated) with the select
+; inside the loop.  In this case, the kill flag on the subtract should be removed or else
+; it will fail verification.
+
+%struct.PROOFSEARCH_HELP = type { %struct.LIST_HELP*, %struct.LIST_HELP*, %struct.LIST_HELP*, %struct.LIST_HELP*, %struct.SHARED_INDEX_NODE*, %struct.LIST_HELP*, %struct.SHARED_INDEX_NODE*, %struct.LIST_HELP*, %struct.SORTTHEORY_HELP*, %struct.SORTTHEORY_HELP*, %struct.SORTTHEORY_HELP*, %struct.SHARED_INDEX_NODE*, %struct.LIST_HELP*, i32*, i32*, %struct.LIST_HELP*, i32, i32, i32, i32, i32, i32, i32, i32 }
+%struct.SORTTHEORY_HELP = type { %struct.st*, [4000 x %struct.NODE_HELP*], %struct.LIST_HELP*, %struct.LIST_HELP*, i32 }
+%struct.st = type { %struct.subst*, %struct.LIST_HELP*, %struct.LIST_HELP*, i16, i16 }
+%struct.subst = type { %struct.subst*, i32, %struct.term* }
+%struct.term = type { i32, %union.anon, %struct.LIST_HELP*, i32, i32 }
+%union.anon = type { %struct.LIST_HELP* }
+%struct.NODE_HELP = type { %struct.LIST_HELP*, i32, i32, i32, %struct.LIST_HELP*, i32 }
+%struct.SHARED_INDEX_NODE = type { %struct.st*, [3001 x %struct.term*], [4000 x %struct.term*], i32 }
+%struct.LIST_HELP = type { %struct.LIST_HELP*, i8* }
+%struct.CLAUSE_HELP = type { i32, i32, i32, i32, i32*, i32, %struct.LIST_HELP*, %struct.LIST_HELP*, i32, i32, %struct.LITERAL_HELP**, i32, i32, i32, i32 }
+%struct.LITERAL_HELP = type { i32, i32, i32, %struct.CLAUSE_HELP*, %struct.term* }
+
+declare void @foo(%struct.PROOFSEARCH_HELP*, %struct.CLAUSE_HELP*)
+
+; CHECK-LABEL: @test
+; CHECK: it
+; CHECK-NEXT: sub
+
+define hidden fastcc %struct.LIST_HELP* @test(%struct.PROOFSEARCH_HELP* %Search, %struct.LIST_HELP* %ClauseList, i32 %Level, %struct.LIST_HELP** nocapture %New) {
+entry:
+  %cmp4.i.i = icmp ugt i32 %Level, 31
+  %0 = add i32 %Level, -32
+  %1 = lshr i32 %0, 5
+  %2 = shl nuw i32 %1, 5
+  %3 = sub i32 %0, %2
+  %4 = add nuw nsw i32 %1, 1
+  br label %for.body
+
+for.body:                                         ; preds = %for.inc, %entry
+  %Scan.038 = phi %struct.LIST_HELP* [ %ClauseList, %entry ], [ %9, %for.inc ]
+  %car.i33 = getelementptr inbounds %struct.LIST_HELP, %struct.LIST_HELP* %Scan.038, i32 0, i32 1
+  %5 = bitcast i8** %car.i33 to %struct.CLAUSE_HELP**
+  %6 = load %struct.CLAUSE_HELP*, %struct.CLAUSE_HELP** %5, align 4
+  %. = add i32 %4, 10
+  %.Level = select i1 %cmp4.i.i, i32 %3, i32 %Level
+  %splitfield.i = getelementptr inbounds %struct.CLAUSE_HELP, %struct.CLAUSE_HELP* %6, i32 0, i32 4
+  %7 = load i32*, i32** %splitfield.i, align 4
+  %arrayidx.i = getelementptr inbounds i32, i32* %7, i32 %.
+  %8 = load i32, i32* %arrayidx.i, align 4
+  %shl.i = shl i32 1, %.Level
+  %and.i = and i32 %8, %shl.i
+  %cmp4.i = icmp eq i32 %and.i, 0
+  br i1 %cmp4.i, label %for.inc, label %if.then
+
+if.then:                                          ; preds = %for.body
+  tail call void @foo(%struct.PROOFSEARCH_HELP* %Search, %struct.CLAUSE_HELP* %6)
+  store i8* null, i8** %car.i33, align 4
+  br label %for.inc
+
+for.inc:                                          ; preds = %if.then, %for.body
+  %cdr.i = getelementptr inbounds %struct.LIST_HELP, %struct.LIST_HELP* %Scan.038, i32 0, i32 0
+  %9 = load %struct.LIST_HELP*, %struct.LIST_HELP** %cdr.i, align 4
+  br label %for.body
+}
diff --git a/test/CodeGen/ARM/commute-movcc.ll b/test/CodeGen/ARM/commute-movcc.ll
index fbc25b45b6ff..2978d317ad78 100644
--- a/test/CodeGen/ARM/commute-movcc.ll
+++ b/test/CodeGen/ARM/commute-movcc.ll
@@ -31,8 +31,8 @@ for.body:                                         ; preds = %entry, %if.end8
   %i.012 = phi i32 [ 0, %entry ], [ %inc, %if.end8 ]
   %BestCost.011 = phi i32 [ -1, %entry ], [ %BestCost.1, %if.end8 ]
   %BestIdx.010 = phi i32 [ 0, %entry ], [ %BestIdx.1, %if.end8 ]
-  %arrayidx = getelementptr inbounds i32* %a, i32 %i.012
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %i.012
+  %0 = load i32, i32* %arrayidx, align 4
   %mul = mul i32 %0, %0
   %sub = add nsw i32 %i.012, -5
   %cmp2 = icmp eq i32 %sub, %Pref
diff --git a/test/CodeGen/ARM/compare-call.ll b/test/CodeGen/ARM/compare-call.ll
index 323eb1f2dd3c..f45ed73adb71 100644
--- a/test/CodeGen/ARM/compare-call.ll
+++ b/test/CodeGen/ARM/compare-call.ll
@@ -2,14 +2,14 @@
 
 define void @test3(float* %glob, i32 %X) {
 entry:
-        %tmp = load float* %glob                ; <float> [#uses=1]
-        %tmp2 = getelementptr float* %glob, i32 2               ; <float*> [#uses=1]
-        %tmp3 = load float* %tmp2               ; <float> [#uses=1]
+        %tmp = load float, float* %glob                ; <float> [#uses=1]
+        %tmp2 = getelementptr float, float* %glob, i32 2               ; <float*> [#uses=1]
+        %tmp3 = load float, float* %tmp2               ; <float> [#uses=1]
         %tmp.upgrd.1 = fcmp ogt float %tmp, %tmp3               ; <i1> [#uses=1]
         br i1 %tmp.upgrd.1, label %cond_true, label %UnifiedReturnBlock
 
 cond_true:              ; preds = %entry
-        %tmp.upgrd.2 = tail call i32 (...)* @bar( )             ; <i32> [#uses=0]
+        %tmp.upgrd.2 = tail call i32 (...) @bar( )             ; <i32> [#uses=0]
         ret void
 
 UnifiedReturnBlock:             ; preds = %entry
diff --git a/test/CodeGen/ARM/copy-paired-reg.ll b/test/CodeGen/ARM/copy-paired-reg.ll
index 17a4461c682b..453fac4b1504 100644
--- a/test/CodeGen/ARM/copy-paired-reg.ll
+++ b/test/CodeGen/ARM/copy-paired-reg.ll
@@ -11,7 +11,7 @@ define void @f() {
   store atomic i64 0, i64* %c seq_cst, align 8
   store atomic i64 0, i64* %d seq_cst, align 8
 
-  %e = load atomic i64* %d seq_cst, align 8
+  %e = load atomic i64, i64* %d seq_cst, align 8
 
   ret void
 }
diff --git a/test/CodeGen/ARM/crash-O0.ll b/test/CodeGen/ARM/crash-O0.ll
index 8855bb99aaf9..f92af999be51 100644
--- a/test/CodeGen/ARM/crash-O0.ll
+++ b/test/CodeGen/ARM/crash-O0.ll
@@ -21,8 +21,8 @@ entry:
   %letter = alloca i8                             ; <i8*> [#uses=0]
   %prodvers = alloca [256 x i8]                   ; <[256 x i8]*> [#uses=1]
   %buildver = alloca [256 x i8]                   ; <[256 x i8]*> [#uses=0]
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* getelementptr inbounds ([256 x i8]* @.str523, i32 0, i32 0), i32 256, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* getelementptr inbounds ([256 x i8], [256 x i8]* @.str523, i32 0, i32 0), i32 256, i32 1, i1 false)
   %prodvers2 = bitcast [256 x i8]* %prodvers to i8* ; <i8*> [#uses=1]
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %prodvers2, i8* getelementptr inbounds ([256 x i8]* @.str523, i32 0, i32 0), i32 256, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %prodvers2, i8* getelementptr inbounds ([256 x i8], [256 x i8]* @.str523, i32 0, i32 0), i32 256, i32 1, i1 false)
   unreachable
 }
diff --git a/test/CodeGen/ARM/crash-greedy-v6.ll b/test/CodeGen/ARM/crash-greedy-v6.ll
index e165dbdf087a..287c081ac5ec 100644
--- a/test/CodeGen/ARM/crash-greedy-v6.ll
+++ b/test/CodeGen/ARM/crash-greedy-v6.ll
@@ -32,13 +32,13 @@ for.body:                                         ; preds = %for.body, %for.body
 ; SOURCE-SCHED: cmp
 ; SOURCE-SCHED: bne
   %i.031 = phi i32 [ 0, %for.body.lr.ph ], [ %0, %for.body ]
-  %arrayidx11 = getelementptr float* %t, i32 %i.031
-  %arrayidx15 = getelementptr float* %u, i32 %i.031
-  %arrayidx19 = getelementptr i8* %red, i32 %i.031
-  %arrayidx22 = getelementptr i8* %green, i32 %i.031
-  %arrayidx25 = getelementptr i8* %blue, i32 %i.031
-  %arrayidx28 = getelementptr i8* %alpha, i32 %i.031
-  %tmp12 = load float* %arrayidx11, align 4
+  %arrayidx11 = getelementptr float, float* %t, i32 %i.031
+  %arrayidx15 = getelementptr float, float* %u, i32 %i.031
+  %arrayidx19 = getelementptr i8, i8* %red, i32 %i.031
+  %arrayidx22 = getelementptr i8, i8* %green, i32 %i.031
+  %arrayidx25 = getelementptr i8, i8* %blue, i32 %i.031
+  %arrayidx28 = getelementptr i8, i8* %alpha, i32 %i.031
+  %tmp12 = load float, float* %arrayidx11, align 4
   tail call fastcc void @sample_3d_nearest(i8* %tObj, i8* undef, float undef, float %tmp12, float undef, i8* %arrayidx19, i8* %arrayidx22, i8* %arrayidx25, i8* %arrayidx28)
   %0 = add i32 %i.031, 1
   %exitcond = icmp eq i32 %0, %n
diff --git a/test/CodeGen/ARM/crash.ll b/test/CodeGen/ARM/crash.ll
index 4e3e2010b07a..3b01d8113b9c 100644
--- a/test/CodeGen/ARM/crash.ll
+++ b/test/CodeGen/ARM/crash.ll
@@ -5,7 +5,7 @@
 
 define void @func() nounwind {
 entry:
-  %tmp = load i32* undef, align 4
+  %tmp = load i32, i32* undef, align 4
   br label %bb1
 
 bb1:
@@ -17,7 +17,7 @@ bb1:
 
 bb2:
   %tmp120 = add i32 %tmp119, 0
-  %scevgep810.i = getelementptr %struct.foo* null, i32 %tmp120, i32 1
+  %scevgep810.i = getelementptr %struct.foo, %struct.foo* null, i32 %tmp120, i32 1
   store i32 undef, i32* %scevgep810.i, align 4
   br i1 undef, label %bb2, label %bb3
 
diff --git a/test/CodeGen/ARM/cse-call.ll b/test/CodeGen/ARM/cse-call.ll
index eff5de5a2428..4e61a3495b80 100644
--- a/test/CodeGen/ARM/cse-call.ll
+++ b/test/CodeGen/ARM/cse-call.ll
@@ -23,8 +23,8 @@ while.body37:                                     ; preds = %while.body37, %entr
   br i1 false, label %while.end42, label %while.body37
 
 while.end42:                                      ; preds = %while.body37, %entry
-  %. = select i1 undef, i8* getelementptr inbounds ([200 x i8]* @F_floatmul.man1, i32 0, i32 0), i8* getelementptr inbounds ([200 x i8]* @F_floatmul.man2, i32 0, i32 0)
-  %.92 = select i1 undef, i8* getelementptr inbounds ([200 x i8]* @F_floatmul.man2, i32 0, i32 0), i8* getelementptr inbounds ([200 x i8]* @F_floatmul.man1, i32 0, i32 0)
+  %. = select i1 undef, i8* getelementptr inbounds ([200 x i8], [200 x i8]* @F_floatmul.man1, i32 0, i32 0), i8* getelementptr inbounds ([200 x i8], [200 x i8]* @F_floatmul.man2, i32 0, i32 0)
+  %.92 = select i1 undef, i8* getelementptr inbounds ([200 x i8], [200 x i8]* @F_floatmul.man2, i32 0, i32 0), i8* getelementptr inbounds ([200 x i8], [200 x i8]* @F_floatmul.man1, i32 0, i32 0)
   tail call void bitcast (void (...)* @S_trimzeros to void (i8*)*)(i8* %.92) nounwind
   %call47 = tail call i32 @strlen(i8* %.) nounwind
   unreachable
diff --git a/test/CodeGen/ARM/cse-ldrlit.ll b/test/CodeGen/ARM/cse-ldrlit.ll
index 3f5d4c2e3c29..4f369d0a78ea 100644
--- a/test/CodeGen/ARM/cse-ldrlit.ll
+++ b/test/CodeGen/ARM/cse-ldrlit.ll
@@ -9,11 +9,11 @@
 declare void @bar(i32*)
 
 define void @foo() {
-  %flag = load i32* getelementptr inbounds([16 x i32]* @var, i32 0, i32 1)
+  %flag = load i32, i32* getelementptr inbounds([16 x i32], [16 x i32]* @var, i32 0, i32 1)
   %tst = icmp eq i32 %flag, 0
   br i1 %tst, label %true, label %false
 true:
-  tail call void @bar(i32* getelementptr inbounds([16 x i32]* @var, i32 0, i32 4))
+  tail call void @bar(i32* getelementptr inbounds([16 x i32], [16 x i32]* @var, i32 0, i32 4))
   ret void
 false:
   ret void
diff --git a/test/CodeGen/ARM/cse-libcalls.ll b/test/CodeGen/ARM/cse-libcalls.ll
index 4f5b7592c844..1255ec5a78f1 100644
--- a/test/CodeGen/ARM/cse-libcalls.ll
+++ b/test/CodeGen/ARM/cse-libcalls.ll
@@ -10,7 +10,7 @@ target triple = "i386-apple-darwin8"
 
 define double @u_f_nonbon(double %lambda) nounwind {
 entry:
-	%tmp19.i.i = load double* null, align 4		; <double> [#uses=2]
+	%tmp19.i.i = load double, double* null, align 4		; <double> [#uses=2]
 	%tmp6.i = fcmp olt double %tmp19.i.i, 1.000000e+00		; <i1> [#uses=1]
 	%dielectric.0.i = select i1 %tmp6.i, double 1.000000e+00, double %tmp19.i.i		; <double> [#uses=1]
 	%tmp10.i4 = fdiv double 0x4074C2D71F36262D, %dielectric.0.i		; <double> [#uses=1]
diff --git a/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll b/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
index 8950abdef6a3..8b7153503b1f 100644
--- a/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
+++ b/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
@@ -2,10 +2,10 @@
 
 ; CHECK-LABEL: f:
 define float @f(<4 x i16>* nocapture %in) {
-  ; CHECK: vldr
+  ; CHECK: vld1
   ; CHECK: vmovl.u16
   ; CHECK-NOT: vand
-  %1 = load <4 x i16>* %in
+  %1 = load <4 x i16>, <4 x i16>* %in
   ; CHECK: vcvt.f32.u32
   %2 = uitofp <4 x i16> %1 to <4 x float>
   %3 = extractelement <4 x float> %2, i32 0
@@ -21,7 +21,7 @@ define float @f(<4 x i16>* nocapture %in) {
 
 define float @g(<4 x i16>* nocapture %in) {
   ; CHECK: vldr
-  %1 = load <4 x i16>* %in
+  %1 = load <4 x i16>, <4 x i16>* %in
   ; CHECK-NOT: uxth
   %2 = extractelement <4 x i16> %1, i32 0
   ; CHECK: vcvt.f32.u32
diff --git a/test/CodeGen/ARM/darwin-section-order.ll b/test/CodeGen/ARM/darwin-section-order.ll
deleted file mode 100644
index 701028c0a537..000000000000
--- a/test/CodeGen/ARM/darwin-section-order.ll
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
-
-; CHECK: .section	__TEXT,__text,regular,pure_instructions
-; CHECK: .section	__TEXT,myprecious
-; CHECK: .section	__TEXT,__textcoal_nt,coalesced,pure_instructions
-; CHECK: .section	__TEXT,__const_coal,coalesced
-; CHECK: .section	__TEXT,__picsymbolstub4,symbol_stubs,none,16
-; CHECK: .section	__TEXT,__StaticInit,regular,pure_instructions
-
-
-define void @normal() nounwind readnone {
-; CHECK: .section	__TEXT,__text,regular,pure_instructions
-; CHECK: _normal:
-  ret void
-}
-
-define void @special() nounwind readnone section "__TEXT,myprecious" {
-; CHECK: .section	__TEXT,myprecious
-; CHECK: _special:
-  ret void
-}
diff --git a/test/CodeGen/ARM/debug-frame-large-stack.ll b/test/CodeGen/ARM/debug-frame-large-stack.ll
index 1addf639bfe4..1f814e70d543 100644
--- a/test/CodeGen/ARM/debug-frame-large-stack.ll
+++ b/test/CodeGen/ARM/debug-frame-large-stack.ll
@@ -48,7 +48,7 @@ define i32 @test3() {
 	%tmp = alloca i32, align 4
 	%a = alloca [805306369 x i8], align 16
 	store i32 0, i32* %tmp
-	%tmp1 = load i32* %tmp
+	%tmp1 = load i32, i32* %tmp
         ret i32 %tmp1
 }
 
diff --git a/test/CodeGen/ARM/debug-frame-vararg.ll b/test/CodeGen/ARM/debug-frame-vararg.ll
index 05521d80646c..19e55fe02354 100644
--- a/test/CodeGen/ARM/debug-frame-vararg.ll
+++ b/test/CodeGen/ARM/debug-frame-vararg.ll
@@ -25,90 +25,88 @@
 !llvm.module.flags = !{!9, !10}
 !llvm.ident = !{!11}
 
-!0 = !{!"0x11\0012\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/var.c] [DW_LANG_C99]
-!1 = !{!"var.c", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "var.c", directory: "/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00sum\00sum\00\005\000\001\000\006\00256\000\005", !1, !5, !6, null, i32 (i32, ...)* @sum, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [sum]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/var.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "sum", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, function: i32 (i32, ...)* @sum, variables: !2)
+!5 = !DIFile(filename: "var.c", directory: "/tmp")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 4}
-!10 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !{i32 1, !"Debug Info Version", i32 3}
 !11 = !{!"clang version 3.5 "}
-!12 = !{!"0x101\00count\0016777221\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [count] [line 5]
-!13 = !MDLocation(line: 5, scope: !4)
-!14 = !{!"0x100\00vl\006\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [vl] [line 6]
-!15 = !{!"0x16\00va_list\0030\000\000\000\000", !16, null, !17} ; [ DW_TAG_typedef ] [va_list] [line 30, size 0, align 0, offset 0] [from __builtin_va_list]
-!16 = !{!"/linux-x86_64-high/gcc_4.7.2/dbg/llvm/bin/../lib/clang/3.5/include/stdarg.h", !"/tmp"}
-!17 = !{!"0x16\00__builtin_va_list\006\000\000\000\000", !1, null, !18} ; [ DW_TAG_typedef ] [__builtin_va_list] [line 6, size 0, align 0, offset 0] [from __va_list]
-!18 = !{!"0x13\00__va_list\006\0032\0032\000\000\000", !1, null, null, !19, null, null, null} ; [ DW_TAG_structure_type ] [__va_list] [line 6, size 32, align 32, offset 0] [def] [from ]
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "count", line: 5, arg: 1, scope: !4, file: !5, type: !8)
+!13 = !DILocation(line: 5, scope: !4)
+!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vl", line: 6, scope: !4, file: !5, type: !15)
+!15 = !DIDerivedType(tag: DW_TAG_typedef, name: "va_list", line: 30, file: !16, baseType: !17)
+!16 = !DIFile(filename: "/linux-x86_64-high/gcc_4.7.2/dbg/llvm/bin/../lib/clang/3.5/include/stdarg.h", directory: "/tmp")
+!17 = !DIDerivedType(tag: DW_TAG_typedef, name: "__builtin_va_list", line: 6, file: !1, baseType: !18)
+!18 = !DICompositeType(tag: DW_TAG_structure_type, name: "__va_list", line: 6, size: 32, align: 32, file: !1, elements: !19)
 !19 = !{!20}
-!20 = !{!"0xd\00__ap\006\0032\0032\000\000", !1, !18, !21} ; [ DW_TAG_member ] [__ap] [line 6, size 32, align 32, offset 0] [from ]
-!21 = !{!"0xf\00\000\0032\0032\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from ]
-!22 = !MDLocation(line: 6, scope: !4)
-!23 = !MDLocation(line: 7, scope: !4)
-!24 = !{!"0x100\00sum\008\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [sum] [line 8]
-!25 = !MDLocation(line: 8, scope: !4)
-!26 = !{!"0x100\00i\009\000", !27, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 9]
-!27 = !{!"0xb\009\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/tmp/var.c]
-!28 = !MDLocation(line: 9, scope: !27)
-!29 = !MDLocation(line: 10, scope: !30)
-!30 = !{!"0xb\009\000\001", !1, !27} ; [ DW_TAG_lexical_block ] [/tmp/var.c]
-!31 = !MDLocation(line: 11, scope: !30)
-!32 = !MDLocation(line: 12, scope: !4)
-!33 = !MDLocation(line: 13, scope: !4)
+!20 = !DIDerivedType(tag: DW_TAG_member, name: "__ap", line: 6, size: 32, align: 32, file: !1, scope: !18, baseType: !21)
+!21 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: null)
+!22 = !DILocation(line: 6, scope: !4)
+!23 = !DILocation(line: 7, scope: !4)
+!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "sum", line: 8, scope: !4, file: !5, type: !8)
+!25 = !DILocation(line: 8, scope: !4)
+!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 9, scope: !27, file: !5, type: !8)
+!27 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !4)
+!28 = !DILocation(line: 9, scope: !27)
+!29 = !DILocation(line: 10, scope: !30)
+!30 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !27)
+!31 = !DILocation(line: 11, scope: !30)
+!32 = !DILocation(line: 12, scope: !4)
+!33 = !DILocation(line: 13, scope: !4)
 
 ; CHECK-FP-LABEL: sum
 ; CHECK-FP: .cfi_startproc
-; CHECK-FP: sub    sp, sp, #16
-; CHECK-FP: .cfi_def_cfa_offset 16
+; CHECK-FP: sub    sp, sp, #12
+; CHECK-FP: .cfi_def_cfa_offset 12
 ; CHECK-FP: push   {r4, lr}
+; CHECK-FP: .cfi_def_cfa_offset 20
+; CHECK-FP: .cfi_offset lr, -16
+; CHECK-FP: .cfi_offset r4, -20
+; CHECK-FP: sub    sp, sp, #4
 ; CHECK-FP: .cfi_def_cfa_offset 24
-; CHECK-FP: .cfi_offset lr, -20
-; CHECK-FP: .cfi_offset r4, -24
-; CHECK-FP: sub    sp, sp, #8
-; CHECK-FP: .cfi_def_cfa_offset 32
 
 ; CHECK-FP-ELIM-LABEL: sum
 ; CHECK-FP-ELIM: .cfi_startproc
-; CHECK-FP-ELIM: sub    sp, sp, #16
-; CHECK-FP-ELIM: .cfi_def_cfa_offset 16
+; CHECK-FP-ELIM: sub    sp, sp, #12
+; CHECK-FP-ELIM: .cfi_def_cfa_offset 12
 ; CHECK-FP-ELIM: push   {r4, r10, r11, lr}
-; CHECK-FP-ELIM: .cfi_def_cfa_offset 32
-; CHECK-FP-ELIM: .cfi_offset lr, -20
-; CHECK-FP-ELIM: .cfi_offset r11, -24
-; CHECK-FP-ELIM: .cfi_offset r10, -28
-; CHECK-FP-ELIM: .cfi_offset r4, -32
+; CHECK-FP-ELIM: .cfi_def_cfa_offset 28
+; CHECK-FP-ELIM: .cfi_offset lr, -16
+; CHECK-FP-ELIM: .cfi_offset r11, -20
+; CHECK-FP-ELIM: .cfi_offset r10, -24
+; CHECK-FP-ELIM: .cfi_offset r4, -28
 ; CHECK-FP-ELIM: add    r11, sp, #8
-; CHECK-FP-ELIM: .cfi_def_cfa r11, 24
+; CHECK-FP-ELIM: .cfi_def_cfa r11, 20
 
 ; CHECK-THUMB-FP-LABEL: sum
 ; CHECK-THUMB-FP: .cfi_startproc
-; CHECK-THUMB-FP: sub    sp, #16
-; CHECK-THUMB-FP: .cfi_def_cfa_offset 16
-; CHECK-THUMB-FP: push   {r4, r5, r7, lr}
-; CHECK-THUMB-FP: .cfi_def_cfa_offset 32
-; CHECK-THUMB-FP: .cfi_offset lr, -20
-; CHECK-THUMB-FP: .cfi_offset r7, -24
-; CHECK-THUMB-FP: .cfi_offset r5, -28
-; CHECK-THUMB-FP: .cfi_offset r4, -32
-; CHECK-THUMB-FP: sub    sp, #8
-; CHECK-THUMB-FP: .cfi_def_cfa_offset 40
+; CHECK-THUMB-FP: sub    sp, #12
+; CHECK-THUMB-FP: .cfi_def_cfa_offset 12
+; CHECK-THUMB-FP: push   {r4, lr}
+; CHECK-THUMB-FP: .cfi_def_cfa_offset 20
+; CHECK-THUMB-FP: .cfi_offset lr, -16
+; CHECK-THUMB-FP: .cfi_offset r4, -20
+; CHECK-THUMB-FP: sub    sp, #4
+; CHECK-THUMB-FP: .cfi_def_cfa_offset 24
 
 ; CHECK-THUMB-FP-ELIM-LABEL: sum
 ; CHECK-THUMB-FP-ELIM: .cfi_startproc
-; CHECK-THUMB-FP-ELIM: sub    sp, #16
-; CHECK-THUMB-FP-ELIM: .cfi_def_cfa_offset 16
-; CHECK-THUMB-FP-ELIM: push   {r4, r5, r7, lr}
-; CHECK-THUMB-FP-ELIM: .cfi_def_cfa_offset 32
-; CHECK-THUMB-FP-ELIM: .cfi_offset lr, -20
-; CHECK-THUMB-FP-ELIM: .cfi_offset r7, -24
-; CHECK-THUMB-FP-ELIM: .cfi_offset r5, -28
-; CHECK-THUMB-FP-ELIM: .cfi_offset r4, -32
+; CHECK-THUMB-FP-ELIM: sub    sp, #12
+; CHECK-THUMB-FP-ELIM: .cfi_def_cfa_offset 12
+; CHECK-THUMB-FP-ELIM: push   {r4, r6, r7, lr}
+; CHECK-THUMB-FP-ELIM: .cfi_def_cfa_offset 28
+; CHECK-THUMB-FP-ELIM: .cfi_offset lr, -16
+; CHECK-THUMB-FP-ELIM: .cfi_offset r7, -20
+; CHECK-THUMB-FP-ELIM: .cfi_offset r6, -24
+; CHECK-THUMB-FP-ELIM: .cfi_offset r4, -28
 ; CHECK-THUMB-FP-ELIM: add    r7, sp, #8
-; CHECK-THUMB-FP-ELIM: .cfi_def_cfa r7, 24
+; CHECK-THUMB-FP-ELIM: .cfi_def_cfa r7, 20
 
 define i32 @sum(i32 %count, ...) {
 entry:
@@ -120,11 +118,11 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %i.05 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
-  %ap.cur = load i8** %vl, align 4
-  %ap.next = getelementptr i8* %ap.cur, i32 4
+  %ap.cur = load i8*, i8** %vl, align 4
+  %ap.next = getelementptr i8, i8* %ap.cur, i32 4
   store i8* %ap.next, i8** %vl, align 4
   %0 = bitcast i8* %ap.cur to i32*
-  %1 = load i32* %0, align 4
+  %1 = load i32, i32* %0, align 4
   %call = call i32 @foo(i32 %1) #1
   %inc = add nsw i32 %i.05, 1
   %exitcond = icmp eq i32 %inc, %count
diff --git a/test/CodeGen/ARM/debug-frame.ll b/test/CodeGen/ARM/debug-frame.ll
index 16e2c4c59f96..134829254e3f 100644
--- a/test/CodeGen/ARM/debug-frame.ll
+++ b/test/CodeGen/ARM/debug-frame.ll
@@ -128,41 +128,41 @@ declare void @_ZSt9terminatev()
 !llvm.module.flags = !{!10, !11}
 !llvm.ident = !{!12}
 
-!0 = !{!"0x11\004\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/exp.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"exp.cpp", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "exp.cpp", directory: "/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00test\00test\00_Z4testiiiiiddddd\004\000\001\000\006\00256\000\005", !1, !5, !6, null, void (i32, i32, i32, i32, i32, double, double, double, double, double)* @_Z4testiiiiiddddd, null, null, !2} ; [ DW_TAG_subprogram ] [line 4] [def] [scope 5] [test]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/exp.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "test", linkageName: "_Z4testiiiiiddddd", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, function: void (i32, i32, i32, i32, i32, double, double, double, double, double)* @_Z4testiiiiiddddd, variables: !2)
+!5 = !DIFile(filename: "exp.cpp", directory: "/tmp")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null, !8, !8, !8, !8, !8, !9, !9, !9, !9, !9}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x24\00double\000\0064\0064\000\000\004", null, null} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 64, encoding: DW_ATE_float)
 !10 = !{i32 2, !"Dwarf Version", i32 4}
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!11 = !{i32 1, !"Debug Info Version", i32 3}
 !12 = !{!"clang version 3.5 "}
-!13 = !{!"0x101\00a\0016777220\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [a] [line 4]
-!14 = !MDLocation(line: 4, scope: !4)
-!15 = !{!"0x101\00b\0033554436\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [b] [line 4]
-!16 = !{!"0x101\00c\0050331652\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [c] [line 4]
-!17 = !{!"0x101\00d\0067108868\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [d] [line 4]
-!18 = !{!"0x101\00e\0083886084\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [e] [line 4]
-!19 = !{!"0x101\00m\00100663301\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [m] [line 5]
-!20 = !MDLocation(line: 5, scope: !4)
-!21 = !{!"0x101\00n\00117440517\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [n] [line 5]
-!22 = !{!"0x101\00p\00134217733\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [p] [line 5]
-!23 = !{!"0x101\00q\00150994949\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [q] [line 5]
-!24 = !{!"0x101\00r\00167772165\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [r] [line 5]
-!25 = !MDLocation(line: 7, scope: !26)
-!26 = !{!"0xb\006\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/tmp/exp.cpp]
-!27 = !MDLocation(line: 8, scope: !26)
-!28 = !MDLocation(line: 11, scope: !26)
-!29 = !MDLocation(line: 9, scope: !30)
-!30 = !{!"0xb\008\000\001", !1, !4} ; [ DW_TAG_lexical_block ] [/tmp/exp.cpp]
-!31 = !MDLocation(line: 10, scope: !30)
-!32 = !MDLocation(line: 10, scope: !4)
-!33 = !MDLocation(line: 11, scope: !4)
-!34 = !MDLocation(line: 11, scope: !30)
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 4, arg: 1, scope: !4, file: !5, type: !8)
+!14 = !DILocation(line: 4, scope: !4)
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 4, arg: 2, scope: !4, file: !5, type: !8)
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 3, scope: !4, file: !5, type: !8)
+!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "d", line: 4, arg: 4, scope: !4, file: !5, type: !8)
+!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "e", line: 4, arg: 5, scope: !4, file: !5, type: !8)
+!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "m", line: 5, arg: 6, scope: !4, file: !5, type: !9)
+!20 = !DILocation(line: 5, scope: !4)
+!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "n", line: 5, arg: 7, scope: !4, file: !5, type: !9)
+!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p", line: 5, arg: 8, scope: !4, file: !5, type: !9)
+!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "q", line: 5, arg: 9, scope: !4, file: !5, type: !9)
+!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "r", line: 5, arg: 10, scope: !4, file: !5, type: !9)
+!25 = !DILocation(line: 7, scope: !26)
+!26 = distinct !DILexicalBlock(line: 6, column: 0, file: !1, scope: !4)
+!27 = !DILocation(line: 8, scope: !26)
+!28 = !DILocation(line: 11, scope: !26)
+!29 = !DILocation(line: 9, scope: !30)
+!30 = distinct !DILexicalBlock(line: 8, column: 0, file: !1, scope: !4)
+!31 = !DILocation(line: 10, scope: !30)
+!32 = !DILocation(line: 10, scope: !4)
+!33 = !DILocation(line: 11, scope: !4)
+!34 = !DILocation(line: 11, scope: !30)
 
 ; CHECK-FP-LABEL: _Z4testiiiiiddddd:
 ; CHECK-FP:   .cfi_startproc
@@ -179,7 +179,7 @@ declare void @_ZSt9terminatev()
 ; CHECK-FP:   .cfi_offset r4, -36
 ; CHECK-FP:   add    r11, sp, #28
 ; CHECK-FP:   .cfi_def_cfa r11, 8
-; CHECK-FP:   sub    sp, sp, #28
+; CHECK-FP:   sub    sp, sp, #44
 ; CHECK-FP:   .cfi_endproc
 
 ; CHECK-FP-ELIM-LABEL: _Z4testiiiiiddddd:
@@ -195,8 +195,8 @@ declare void @_ZSt9terminatev()
 ; CHECK-FP-ELIM:   .cfi_offset r6, -28
 ; CHECK-FP-ELIM:   .cfi_offset r5, -32
 ; CHECK-FP-ELIM:   .cfi_offset r4, -36
-; CHECK-FP-ELIM:   sub   sp, sp, #28
-; CHECK-FP-ELIM:   .cfi_def_cfa_offset 64
+; CHECK-FP-ELIM:   sub   sp, sp, #36
+; CHECK-FP-ELIM:   .cfi_def_cfa_offset 72
 ; CHECK-FP-ELIM:   .cfi_endproc
 
 ; CHECK-V7-FP-LABEL: _Z4testiiiiiddddd:
@@ -264,14 +264,14 @@ declare void @_ZSt9terminatev()
 
 ; CHECK-THUMB-V7-FP-LABEL: _Z4testiiiiiddddd:
 ; CHECK-THUMB-V7-FP:   .cfi_startproc
-; CHECK-THUMB-V7-FP:   push.w   {r4, r7, r11, lr}
+; CHECK-THUMB-V7-FP:   push   {r4, r6, r7, lr}
 ; CHECK-THUMB-V7-FP:   .cfi_def_cfa_offset 16
 ; CHECK-THUMB-V7-FP:   .cfi_offset lr, -4
-; CHECK-THUMB-V7-FP:   .cfi_offset r11, -8
-; CHECK-THUMB-V7-FP:   .cfi_offset r7, -12
+; CHECK-THUMB-V7-FP:   .cfi_offset r7, -8
+; CHECK-THUMB-V7-FP:   .cfi_offset r6, -12
 ; CHECK-THUMB-V7-FP:   .cfi_offset r4, -16
-; CHECK-THUMB-V7-FP:   add    r7, sp, #4
-; CHECK-THUMB-V7-FP:   .cfi_def_cfa r7, 12
+; CHECK-THUMB-V7-FP:   add    r7, sp, #8
+; CHECK-THUMB-V7-FP:   .cfi_def_cfa r7, 8
 ; CHECK-THUMB-V7-FP:   vpush  {d8, d9, d10, d11, d12}
 ; CHECK-THUMB-V7-FP:   .cfi_offset d12, -24
 ; CHECK-THUMB-V7-FP:   .cfi_offset d11, -32
@@ -300,14 +300,14 @@ declare void @_ZSt9terminatev()
 
 ; CHECK-THUMB-V7-FP-NOIAS-LABEL: _Z4testiiiiiddddd:
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_startproc
-; CHECK-THUMB-V7-FP-NOIAS:   push.w   {r4, r7, r11, lr}
+; CHECK-THUMB-V7-FP-NOIAS:   push   {r4, r6, r7, lr}
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_def_cfa_offset 16
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 14, -4
-; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 11, -8
-; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 7, -12
+; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 7, -8
+; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 6, -12
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 4, -16
-; CHECK-THUMB-V7-FP-NOIAS:   add    r7, sp, #4
-; CHECK-THUMB-V7-FP-NOIAS:   .cfi_def_cfa 7, 12
+; CHECK-THUMB-V7-FP-NOIAS:   add    r7, sp, #8
+; CHECK-THUMB-V7-FP-NOIAS:   .cfi_def_cfa 7, 8
 ; CHECK-THUMB-V7-FP-NOIAS:   vpush  {d8, d9, d10, d11, d12}
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 268, -24
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 267, -32
@@ -404,11 +404,11 @@ entry:
 
 ; CHECK-THUMB-V7-FP-ELIM-LABEL: test2:
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_startproc
-; CHECK-THUMB-V7-FP-ELIM:   push.w  {r11, lr}
+; CHECK-THUMB-V7-FP-ELIM:   push  {r7, lr}
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_def_cfa_offset 8
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset lr, -4
-; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset r11, -8
-; CHECK-THUMB-V7-FP-ELIM:   pop.w   {r11, pc}
+; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset r7, -8
+; CHECK-THUMB-V7-FP-ELIM:   pop   {r7, pc}
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_endproc
 
 
@@ -522,13 +522,13 @@ entry:
 
 ; CHECK-THUMB-V7-FP-ELIM-LABEL: test3:
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_startproc
-; CHECK-THUMB-V7-FP-ELIM:   push.w  {r4, r5, r11, lr}
+; CHECK-THUMB-V7-FP-ELIM:   push  {r4, r5, r7, lr}
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_def_cfa_offset 16
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset lr, -4
-; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset r11, -8
+; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset r7, -8
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset r5, -12
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset r4, -16
-; CHECK-THUMB-V7-FP-ELIM:   pop.w   {r4, r5, r11, pc}
+; CHECK-THUMB-V7-FP-ELIM:   pop   {r4, r5, r7, pc}
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_endproc
 
 
diff --git a/test/CodeGen/ARM/debug-info-arg.ll b/test/CodeGen/ARM/debug-info-arg.ll
index 8679589a4865..84eae77794a4 100644
--- a/test/CodeGen/ARM/debug-info-arg.ll
+++ b/test/CodeGen/ARM/debug-info-arg.ll
@@ -7,13 +7,13 @@ target triple = "thumbv7-apple-ios"
 %struct.tag_s = type { i32, i32, i32 }
 
 define void @foo(%struct.tag_s* nocapture %this, %struct.tag_s* %c, i64 %x, i64 %y, %struct.tag_s* nocapture %ptr1, %struct.tag_s* nocapture %ptr2) nounwind ssp {
-  tail call void @llvm.dbg.value(metadata %struct.tag_s* %this, i64 0, metadata !5, metadata !{!"0x102"}), !dbg !20
-  tail call void @llvm.dbg.value(metadata %struct.tag_s* %c, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !21
-  tail call void @llvm.dbg.value(metadata i64 %x, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !22
-  tail call void @llvm.dbg.value(metadata i64 %y, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !23
+  tail call void @llvm.dbg.value(metadata %struct.tag_s* %this, i64 0, metadata !5, metadata !DIExpression()), !dbg !20
+  tail call void @llvm.dbg.value(metadata %struct.tag_s* %c, i64 0, metadata !13, metadata !DIExpression()), !dbg !21
+  tail call void @llvm.dbg.value(metadata i64 %x, i64 0, metadata !14, metadata !DIExpression()), !dbg !22
+  tail call void @llvm.dbg.value(metadata i64 %y, i64 0, metadata !17, metadata !DIExpression()), !dbg !23
 ;CHECK:	@DEBUG_VALUE: foo:y <- [R7+8]
-  tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr1, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !24
-  tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr2, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !25
+  tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr1, i64 0, metadata !18, metadata !DIExpression()), !dbg !24
+  tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr2, i64 0, metadata !19, metadata !DIExpression()), !dbg !25
   %1 = icmp eq %struct.tag_s* %c, null, !dbg !26
   br i1 %1, label %3, label %2, !dbg !26
 
@@ -32,37 +32,37 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!33}
 
-!0 = !{!"0x11\0012\00Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)\001\00\000\00\001", !32, !4, !4, !30, null,  null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"0x2e\00foo\00foo\00\0011\000\001\000\006\00256\001\0011", !2, !2, !3, null, void (%struct.tag_s*, %struct.tag_s*, i64, i64, %struct.tag_s*, %struct.tag_s*)* @foo, null, null, !31} ; [ DW_TAG_subprogram ] [line 11] [def] [foo]
-!2 = !{!"0x29", !32} ; [ DW_TAG_file_type ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !32, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", isOptimized: true, emissionKind: 1, file: !32, enums: !{}, retainedTypes: !{}, subprograms: !30, imports:  null)
+!1 = !DISubprogram(name: "foo", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !2, scope: !2, type: !3, function: void (%struct.tag_s*, %struct.tag_s*, i64, i64, %struct.tag_s*, %struct.tag_s*)* @foo, variables: !31)
+!2 = !DIFile(filename: "one.c", directory: "/Volumes/Athwagate/R10048772")
+!3 = !DISubroutineType(types: !4)
 !4 = !{null}
-!5 = !{!"0x101\00this\0016777227\000", !1, !2, !6} ; [ DW_TAG_arg_variable ]
-!6 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !7} ; [ DW_TAG_pointer_type ]
-!7 = !{!"0x13\00tag_s\005\0096\0032\000\000\000", !32, !0, null, !8, null, null, null} ; [ DW_TAG_structure_type ] [tag_s] [line 5, size 96, align 32, offset 0] [def] [from ]
+!5 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 11, arg: 1, scope: !1, file: !2, type: !6)
+!6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !7)
+!7 = !DICompositeType(tag: DW_TAG_structure_type, name: "tag_s", line: 5, size: 96, align: 32, file: !32, scope: !0, elements: !8)
 !8 = !{!9, !11, !12}
-!9 = !{!"0xd\00x\006\0032\0032\000\000", !32, !7, !10} ; [ DW_TAG_member ]
-!10 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ]
-!11 = !{!"0xd\00y\007\0032\0032\0032\000", !32, !7, !10} ; [ DW_TAG_member ]
-!12 = !{!"0xd\00z\008\0032\0032\0064\000", !32, !7, !10} ; [ DW_TAG_member ]
-!13 = !{!"0x101\00c\0033554443\000", !1, !2, !6} ; [ DW_TAG_arg_variable ]
-!14 = !{!"0x101\00x\0050331659\000", !1, !2, !15} ; [ DW_TAG_arg_variable ]
-!15 = !{!"0x16\00UInt64\001\000\000\000\000", !32, !0, !16} ; [ DW_TAG_typedef ]
-!16 = !{!"0x24\00long long unsigned int\000\0064\0032\000\000\007", null, !0} ; [ DW_TAG_base_type ]
-!17 = !{!"0x101\00y\0067108875\000", !1, !2, !15} ; [ DW_TAG_arg_variable ]
-!18 = !{!"0x101\00ptr1\0083886091\000", !1, !2, !6} ; [ DW_TAG_arg_variable ]
-!19 = !{!"0x101\00ptr2\00100663307\000", !1, !2, !6} ; [ DW_TAG_arg_variable ]
-!20 = !MDLocation(line: 11, column: 24, scope: !1)
-!21 = !MDLocation(line: 11, column: 44, scope: !1)
-!22 = !MDLocation(line: 11, column: 54, scope: !1)
-!23 = !MDLocation(line: 11, column: 64, scope: !1)
-!24 = !MDLocation(line: 11, column: 81, scope: !1)
-!25 = !MDLocation(line: 11, column: 101, scope: !1)
-!26 = !MDLocation(line: 12, column: 3, scope: !27)
-!27 = !{!"0xb\0011\00107\000", !2, !1} ; [ DW_TAG_lexical_block ]
-!28 = !MDLocation(line: 13, column: 5, scope: !27)
-!29 = !MDLocation(line: 14, column: 1, scope: !27)
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 6, size: 32, align: 32, file: !32, scope: !7, baseType: !10)
+!10 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!11 = !DIDerivedType(tag: DW_TAG_member, name: "y", line: 7, size: 32, align: 32, offset: 32, file: !32, scope: !7, baseType: !10)
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "z", line: 8, size: 32, align: 32, offset: 64, file: !32, scope: !7, baseType: !10)
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 11, arg: 2, scope: !1, file: !2, type: !6)
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 11, arg: 3, scope: !1, file: !2, type: !15)
+!15 = !DIDerivedType(tag: DW_TAG_typedef, name: "UInt64", line: 1, file: !32, scope: !0, baseType: !16)
+!16 = !DIBasicType(tag: DW_TAG_base_type, name: "long long unsigned int", size: 64, align: 32, encoding: DW_ATE_unsigned)
+!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "y", line: 11, arg: 4, scope: !1, file: !2, type: !15)
+!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr1", line: 11, arg: 5, scope: !1, file: !2, type: !6)
+!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr2", line: 11, arg: 6, scope: !1, file: !2, type: !6)
+!20 = !DILocation(line: 11, column: 24, scope: !1)
+!21 = !DILocation(line: 11, column: 44, scope: !1)
+!22 = !DILocation(line: 11, column: 54, scope: !1)
+!23 = !DILocation(line: 11, column: 64, scope: !1)
+!24 = !DILocation(line: 11, column: 81, scope: !1)
+!25 = !DILocation(line: 11, column: 101, scope: !1)
+!26 = !DILocation(line: 12, column: 3, scope: !27)
+!27 = distinct !DILexicalBlock(line: 11, column: 107, file: !2, scope: !1)
+!28 = !DILocation(line: 13, column: 5, scope: !27)
+!29 = !DILocation(line: 14, column: 1, scope: !27)
 !30 = !{!1}
 !31 = !{!5, !13, !14, !17, !18, !19}
-!32 = !{!"one.c", !"/Volumes/Athwagate/R10048772"}
-!33 = !{i32 1, !"Debug Info Version", i32 2}
+!32 = !DIFile(filename: "one.c", directory: "/Volumes/Athwagate/R10048772")
+!33 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/ARM/debug-info-blocks.ll b/test/CodeGen/ARM/debug-info-blocks.ll
index 3bf6ad91c86e..366102755174 100644
--- a/test/CodeGen/ARM/debug-info-blocks.ll
+++ b/test/CodeGen/ARM/debug-info-blocks.ll
@@ -31,62 +31,62 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load
   %1 = alloca %0*, align 4
   %bounds = alloca %struct.CR, align 4
   %data = alloca %struct.CR, align 4
-  call void @llvm.dbg.value(metadata i8* %.block_descriptor, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !129
+  call void @llvm.dbg.value(metadata i8* %.block_descriptor, i64 0, metadata !27, metadata !DIExpression()), !dbg !129
   store %0* %loadedMydata, %0** %1, align 4
-  call void @llvm.dbg.declare(metadata %0** %1, metadata !130, metadata !{!"0x102"}), !dbg !131
+  call void @llvm.dbg.declare(metadata %0** %1, metadata !130, metadata !DIExpression()), !dbg !131
   %2 = bitcast %struct.CR* %bounds to %1*
-  %3 = getelementptr %1* %2, i32 0, i32 0
+  %3 = getelementptr %1, %1* %2, i32 0, i32 0
   store [4 x i32] %bounds.coerce0, [4 x i32]* %3
-  call void @llvm.dbg.declare(metadata %struct.CR* %bounds, metadata !132, metadata !{!"0x102"}), !dbg !133
+  call void @llvm.dbg.declare(metadata %struct.CR* %bounds, metadata !132, metadata !DIExpression()), !dbg !133
   %4 = bitcast %struct.CR* %data to %1*
-  %5 = getelementptr %1* %4, i32 0, i32 0
+  %5 = getelementptr %1, %1* %4, i32 0, i32 0
   store [4 x i32] %data.coerce0, [4 x i32]* %5
-  call void @llvm.dbg.declare(metadata %struct.CR* %data, metadata !134, metadata !{!"0x102"}), !dbg !135
+  call void @llvm.dbg.declare(metadata %struct.CR* %data, metadata !134, metadata !DIExpression()), !dbg !135
   %6 = bitcast i8* %.block_descriptor to %2*
-  %7 = getelementptr inbounds %2* %6, i32 0, i32 6
+  %7 = getelementptr inbounds %2, %2* %6, i32 0, i32 6
   call void @llvm.dbg.declare(metadata %2* %6, metadata !136, metadata !163), !dbg !137
   call void @llvm.dbg.declare(metadata %2* %6, metadata !138, metadata !164), !dbg !137
   call void @llvm.dbg.declare(metadata %2* %6, metadata !139, metadata !165), !dbg !140
-  %8 = load %0** %1, align 4, !dbg !141
-  %9 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_13", !dbg !141
+  %8 = load %0*, %0** %1, align 4, !dbg !141
+  %9 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_13", !dbg !141
   %10 = bitcast %0* %8 to i8*, !dbg !141
   %11 = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %10, i8* %9), !dbg !141
   %12 = bitcast i8* %11 to %0*, !dbg !141
-  %13 = getelementptr inbounds %2* %6, i32 0, i32 5, !dbg !141
-  %14 = load i8** %13, !dbg !141
+  %13 = getelementptr inbounds %2, %2* %6, i32 0, i32 5, !dbg !141
+  %14 = load i8*, i8** %13, !dbg !141
   %15 = bitcast i8* %14 to %struct.__block_byref_mydata*, !dbg !141
-  %16 = getelementptr inbounds %struct.__block_byref_mydata* %15, i32 0, i32 1, !dbg !141
-  %17 = load %struct.__block_byref_mydata** %16, !dbg !141
-  %18 = getelementptr inbounds %struct.__block_byref_mydata* %17, i32 0, i32 6, !dbg !141
+  %16 = getelementptr inbounds %struct.__block_byref_mydata, %struct.__block_byref_mydata* %15, i32 0, i32 1, !dbg !141
+  %17 = load %struct.__block_byref_mydata*, %struct.__block_byref_mydata** %16, !dbg !141
+  %18 = getelementptr inbounds %struct.__block_byref_mydata, %struct.__block_byref_mydata* %17, i32 0, i32 6, !dbg !141
   store %0* %12, %0** %18, align 4, !dbg !141
-  %19 = getelementptr inbounds %2* %6, i32 0, i32 6, !dbg !143
-  %20 = load %3** %19, align 4, !dbg !143
-  %21 = load i32* @"OBJC_IVAR_$_MyWork._data", !dbg !143
+  %19 = getelementptr inbounds %2, %2* %6, i32 0, i32 6, !dbg !143
+  %20 = load %3*, %3** %19, align 4, !dbg !143
+  %21 = load i32, i32* @"OBJC_IVAR_$_MyWork._data", !dbg !143
   %22 = bitcast %3* %20 to i8*, !dbg !143
-  %23 = getelementptr inbounds i8* %22, i32 %21, !dbg !143
+  %23 = getelementptr inbounds i8, i8* %22, i32 %21, !dbg !143
   %24 = bitcast i8* %23 to %struct.CR*, !dbg !143
   %25 = bitcast %struct.CR* %24 to i8*, !dbg !143
   %26 = bitcast %struct.CR* %data to i8*, !dbg !143
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %25, i8* %26, i32 16, i32 4, i1 false), !dbg !143
-  %27 = getelementptr inbounds %2* %6, i32 0, i32 6, !dbg !144
-  %28 = load %3** %27, align 4, !dbg !144
-  %29 = load i32* @"OBJC_IVAR_$_MyWork._bounds", !dbg !144
+  %27 = getelementptr inbounds %2, %2* %6, i32 0, i32 6, !dbg !144
+  %28 = load %3*, %3** %27, align 4, !dbg !144
+  %29 = load i32, i32* @"OBJC_IVAR_$_MyWork._bounds", !dbg !144
   %30 = bitcast %3* %28 to i8*, !dbg !144
-  %31 = getelementptr inbounds i8* %30, i32 %29, !dbg !144
+  %31 = getelementptr inbounds i8, i8* %30, i32 %29, !dbg !144
   %32 = bitcast i8* %31 to %struct.CR*, !dbg !144
   %33 = bitcast %struct.CR* %32 to i8*, !dbg !144
   %34 = bitcast %struct.CR* %bounds to i8*, !dbg !144
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %33, i8* %34, i32 16, i32 4, i1 false), !dbg !144
-  %35 = getelementptr inbounds %2* %6, i32 0, i32 6, !dbg !145
-  %36 = load %3** %35, align 4, !dbg !145
-  %37 = getelementptr inbounds %2* %6, i32 0, i32 5, !dbg !145
-  %38 = load i8** %37, !dbg !145
+  %35 = getelementptr inbounds %2, %2* %6, i32 0, i32 6, !dbg !145
+  %36 = load %3*, %3** %35, align 4, !dbg !145
+  %37 = getelementptr inbounds %2, %2* %6, i32 0, i32 5, !dbg !145
+  %38 = load i8*, i8** %37, !dbg !145
   %39 = bitcast i8* %38 to %struct.__block_byref_mydata*, !dbg !145
-  %40 = getelementptr inbounds %struct.__block_byref_mydata* %39, i32 0, i32 1, !dbg !145
-  %41 = load %struct.__block_byref_mydata** %40, !dbg !145
-  %42 = getelementptr inbounds %struct.__block_byref_mydata* %41, i32 0, i32 6, !dbg !145
-  %43 = load %0** %42, align 4, !dbg !145
-  %44 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_222", !dbg !145
+  %40 = getelementptr inbounds %struct.__block_byref_mydata, %struct.__block_byref_mydata* %39, i32 0, i32 1, !dbg !145
+  %41 = load %struct.__block_byref_mydata*, %struct.__block_byref_mydata** %40, !dbg !145
+  %42 = getelementptr inbounds %struct.__block_byref_mydata, %struct.__block_byref_mydata* %41, i32 0, i32 6, !dbg !145
+  %43 = load %0*, %0** %42, align 4, !dbg !145
+  %44 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_222", !dbg !145
   %45 = bitcast %3* %36 to i8*, !dbg !145
   call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %0*)*)(i8* %45, i8* %44, %0* %43), !dbg !145
   ret void, !dbg !146
@@ -95,169 +95,169 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!162}
 
-!0 = !{!"0x11\0016\00Apple clang version 2.1\000\00\002\00\001", !153, !147, !26, !148, null, null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"0x4\00\00248\0032\0032\000\000\000", !160, !0, null, !3, null, null, null} ; [ DW_TAG_enumeration_type ] [line 248, size 32, align 32, offset 0] [def] [from ]
-!2 = !{!"0x29", !160} ; [ DW_TAG_file_type ]
+!0 = !DICompileUnit(language: DW_LANG_ObjC, producer: "Apple clang version 2.1", isOptimized: false, runtimeVersion: 2, emissionKind: 1, file: !153, enums: !147, retainedTypes: !{}, subprograms: !148)
+!1 = !DICompositeType(tag: DW_TAG_enumeration_type, line: 248, size: 32, align: 32, file: !160, scope: !0, elements: !3)
+!2 = !DIFile(filename: "header.h", directory: "/Volumes/Sandbox/llvm")
 !3 = !{!4}
-!4 = !{!"0x28\00Ver1\000"} ; [ DW_TAG_enumerator ]
-!5 = !{!"0x4\00Mode\0079\0032\0032\000\000\000", !160, !0, null, !7, null, null, null} ; [ DW_TAG_enumeration_type ] [Mode] [line 79, size 32, align 32, offset 0] [def] [from ]
-!6 = !{!"0x29", !161} ; [ DW_TAG_file_type ]
+!4 = !DIEnumerator(name: "Ver1", value: 0) ; [ DW_TAG_enumerator ]
+!5 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "Mode", line: 79, size: 32, align: 32, file: !160, scope: !0, elements: !7)
+!6 = !DIFile(filename: "header2.h", directory: "/Volumes/Sandbox/llvm")
 !7 = !{!8}
-!8 = !{!"0x28\00One\000"} ; [ DW_TAG_enumerator ]
-!9 = !{!"0x4\00\0015\0032\0032\000\000\000", !149, !0, null, !11, null, null, null} ; [ DW_TAG_enumeration_type ] [line 15, size 32, align 32, offset 0] [def] [from ]
-!10 = !{!"0x29", !149} ; [ DW_TAG_file_type ]
+!8 = !DIEnumerator(name: "One", value: 0) ; [ DW_TAG_enumerator ]
+!9 = !DICompositeType(tag: DW_TAG_enumeration_type, line: 15, size: 32, align: 32, file: !149, scope: !0, elements: !11)
+!10 = !DIFile(filename: "header3.h", directory: "/Volumes/Sandbox/llvm")
 !11 = !{!12, !13}
-!12 = !{!"0x28\00Unknown\000"} ; [ DW_TAG_enumerator ]
-!13 = !{!"0x28\00Known\001"} ; [ DW_TAG_enumerator ]
-!14 = !{!"0x4\00\0020\0032\0032\000\000\000", !150, !0, null, !16, null, null, null} ; [ DW_TAG_enumeration_type ] [line 20, size 32, align 32, offset 0] [def] [from ]
-!15 = !{!"0x29", !150} ; [ DW_TAG_file_type ]
+!12 = !DIEnumerator(name: "Unknown", value: 0) ; [ DW_TAG_enumerator ]
+!13 = !DIEnumerator(name: "Known", value: 1) ; [ DW_TAG_enumerator ]
+!14 = !DICompositeType(tag: DW_TAG_enumeration_type, line: 20, size: 32, align: 32, file: !150, scope: !0, elements: !16)
+!15 = !DIFile(filename: "Private.h", directory: "/Volumes/Sandbox/llvm")
 !16 = !{!17, !18}
-!17 = !{!"0x28\00Single\000"} ; [ DW_TAG_enumerator ]
-!18 = !{!"0x28\00Double\001"} ; [ DW_TAG_enumerator ]
-!19 = !{!"0x4\00\0014\0032\0032\000\000\000", !151, !0, null, !21, null, null, null} ; [ DW_TAG_enumeration_type ] [line 14, size 32, align 32, offset 0] [def] [from ]
-!20 = !{!"0x29", !151} ; [ DW_TAG_file_type ]
+!17 = !DIEnumerator(name: "Single", value: 0) ; [ DW_TAG_enumerator ]
+!18 = !DIEnumerator(name: "Double", value: 1) ; [ DW_TAG_enumerator ]
+!19 = !DICompositeType(tag: DW_TAG_enumeration_type, line: 14, size: 32, align: 32, file: !151, scope: !0, elements: !21)
+!20 = !DIFile(filename: "header4.h", directory: "/Volumes/Sandbox/llvm")
 !21 = !{!22}
-!22 = !{!"0x28\00Eleven\000"} ; [ DW_TAG_enumerator ]
-!23 = !{!"0x2e\00foobar_func_block_invoke_0\00foobar_func_block_invoke_0\00\00609\001\001\000\006\00256\000\00609", !152, !24, !25, null, void (i8*, %0*, [4 x i32], [4 x i32])* @foobar_func_block_invoke_0, null, null, null} ; [ DW_TAG_subprogram ] [line 609] [local] [def] [foobar_func_block_invoke_0]
-!24 = !{!"0x29", !152} ; [ DW_TAG_file_type ]
-!25 = !{!"0x15\00\000\000\000\000\000\000", !152, !24, null, !26, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!22 = !DIEnumerator(name: "Eleven", value: 0) ; [ DW_TAG_enumerator ]
+!23 = !DISubprogram(name: "foobar_func_block_invoke_0", line: 609, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 609, file: !152, scope: !24, type: !25, function: void (i8*, %0*, [4 x i32], [4 x i32])* @foobar_func_block_invoke_0)
+!24 = !DIFile(filename: "MyLibrary.m", directory: "/Volumes/Sandbox/llvm")
+!25 = !DISubroutineType(types: !26)
 !26 = !{null}
-!27 = !{!"0x101\00.block_descriptor\0016777825\0064", !23, !24, !28} ; [ DW_TAG_arg_variable ]
-!28 = !{!"0xf\00\000\0032\000\000\000", null, !0, !29} ; [ DW_TAG_pointer_type ]
-!29 = !{!"0x13\00__block_literal_14\00609\00256\0032\000\000\000", !152, !24, null, !30, null, null, null} ; [ DW_TAG_structure_type ] [__block_literal_14] [line 609, size 256, align 32, offset 0] [def] [from ]
+!27 = !DILocalVariable(tag: DW_TAG_arg_variable, name: ".block_descriptor", line: 609, arg: 1, flags: DIFlagArtificial, scope: !23, file: !24, type: !28)
+!28 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, scope: !0, baseType: !29)
+!29 = !DICompositeType(tag: DW_TAG_structure_type, name: "__block_literal_14", line: 609, size: 256, align: 32, file: !152, scope: !24, elements: !30)
 !30 = !{!31, !33, !35, !36, !37, !48, !89, !124}
-!31 = !{!"0xd\00__isa\00609\0032\0032\000\000", !152, !24, !32} ; [ DW_TAG_member ]
-!32 = !{!"0xf\00\000\0032\0032\000\000", null, !0, null} ; [ DW_TAG_pointer_type ]
-!33 = !{!"0xd\00__flags\00609\0032\0032\0032\000", !152, !24, !34} ; [ DW_TAG_member ]
-!34 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ]
-!35 = !{!"0xd\00__reserved\00609\0032\0032\0064\000", !152, !24, !34} ; [ DW_TAG_member ]
-!36 = !{!"0xd\00__FuncPtr\00609\0032\0032\0096\000", !152, !24, !32} ; [ DW_TAG_member ]
-!37 = !{!"0xd\00__descriptor\00609\0032\0032\00128\000", !152, !24, !38} ; [ DW_TAG_member ]
-!38 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !39} ; [ DW_TAG_pointer_type ]
-!39 = !{!"0x13\00__block_descriptor_withcopydispose\00307\00128\0032\000\000\000", !153, !0, null, !41, null, null, null} ; [ DW_TAG_structure_type ] [__block_descriptor_withcopydispose] [line 307, size 128, align 32, offset 0] [def] [from ]
-!40 = !{!"0x29", !153} ; [ DW_TAG_file_type ]
+!31 = !DIDerivedType(tag: DW_TAG_member, name: "__isa", line: 609, size: 32, align: 32, file: !152, scope: !24, baseType: !32)
+!32 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: null)
+!33 = !DIDerivedType(tag: DW_TAG_member, name: "__flags", line: 609, size: 32, align: 32, offset: 32, file: !152, scope: !24, baseType: !34)
+!34 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!35 = !DIDerivedType(tag: DW_TAG_member, name: "__reserved", line: 609, size: 32, align: 32, offset: 64, file: !152, scope: !24, baseType: !34)
+!36 = !DIDerivedType(tag: DW_TAG_member, name: "__FuncPtr", line: 609, size: 32, align: 32, offset: 96, file: !152, scope: !24, baseType: !32)
+!37 = !DIDerivedType(tag: DW_TAG_member, name: "__descriptor", line: 609, size: 32, align: 32, offset: 128, file: !152, scope: !24, baseType: !38)
+!38 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !39)
+!39 = !DICompositeType(tag: DW_TAG_structure_type, name: "__block_descriptor_withcopydispose", line: 307, size: 128, align: 32, file: !153, scope: !0, elements: !41)
+!40 = !DIFile(filename: "MyLibrary.i", directory: "/Volumes/Sandbox/llvm")
 !41 = !{!42, !44, !45, !47}
-!42 = !{!"0xd\00reserved\00307\0032\0032\000\000", !153, !40, !43} ; [ DW_TAG_member ]
-!43 = !{!"0x24\00long unsigned int\000\0032\0032\000\000\007", null, !0} ; [ DW_TAG_base_type ]
-!44 = !{!"0xd\00Size\00307\0032\0032\0032\000", !153, !40, !43} ; [ DW_TAG_member ]
-!45 = !{!"0xd\00CopyFuncPtr\00307\0032\0032\0064\000", !153, !40, !46} ; [ DW_TAG_member ]
-!46 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !32} ; [ DW_TAG_pointer_type ]
-!47 = !{!"0xd\00DestroyFuncPtr\00307\0032\0032\0096\000", !153, !40, !46} ; [ DW_TAG_member ]
-!48 = !{!"0xd\00mydata\00609\0032\0032\00160\000", !152, !24, !49} ; [ DW_TAG_member ]
-!49 = !{!"0xf\00\000\0032\000\000\000", null, !0, !50} ; [ DW_TAG_pointer_type ]
-!50 = !{!"0x13\00\000\00224\000\000\0016\000", !152, !24, null, !51, null, null, null} ; [ DW_TAG_structure_type ] [line 0, size 224, align 0, offset 0] [def] [from ]
+!42 = !DIDerivedType(tag: DW_TAG_member, name: "reserved", line: 307, size: 32, align: 32, file: !153, scope: !40, baseType: !43)
+!43 = !DIBasicType(tag: DW_TAG_base_type, name: "long unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!44 = !DIDerivedType(tag: DW_TAG_member, name: "Size", line: 307, size: 32, align: 32, offset: 32, file: !153, scope: !40, baseType: !43)
+!45 = !DIDerivedType(tag: DW_TAG_member, name: "CopyFuncPtr", line: 307, size: 32, align: 32, offset: 64, file: !153, scope: !40, baseType: !46)
+!46 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !32)
+!47 = !DIDerivedType(tag: DW_TAG_member, name: "DestroyFuncPtr", line: 307, size: 32, align: 32, offset: 96, file: !153, scope: !40, baseType: !46)
+!48 = !DIDerivedType(tag: DW_TAG_member, name: "mydata", line: 609, size: 32, align: 32, offset: 160, file: !152, scope: !24, baseType: !49)
+!49 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, scope: !0, baseType: !50)
+!50 = !DICompositeType(tag: DW_TAG_structure_type, size: 224, flags: DIFlagBlockByrefStruct, file: !152, scope: !24, elements: !51)
 !51 = !{!52, !53, !54, !55, !56, !57, !58}
-!52 = !{!"0xd\00__isa\000\0032\0032\000\000", !152, !24, !32} ; [ DW_TAG_member ]
-!53 = !{!"0xd\00__forwarding\000\0032\0032\0032\000", !152, !24, !32} ; [ DW_TAG_member ]
-!54 = !{!"0xd\00__flags\000\0032\0032\0064\000", !152, !24, !34} ; [ DW_TAG_member ]
-!55 = !{!"0xd\00__size\000\0032\0032\0096\000", !152, !24, !34} ; [ DW_TAG_member ]
-!56 = !{!"0xd\00__copy_helper\000\0032\0032\00128\000", !152, !24, !32} ; [ DW_TAG_member ]
-!57 = !{!"0xd\00__destroy_helper\000\0032\0032\00160\000", !152, !24, !32} ; [ DW_TAG_member ]
-!58 = !{!"0xd\00mydata\000\0032\0032\00192\000", !152, !24, !59} ; [ DW_TAG_member ]
-!59 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !60} ; [ DW_TAG_pointer_type ]
-!60 = !{!"0x13\00UIMydata\0026\00128\0032\000\000\0016", !154, !24, null, !62, null, null, null} ; [ DW_TAG_structure_type ] [UIMydata] [line 26, size 128, align 32, offset 0] [def] [from ]
-!61 = !{!"0x29", !154} ; [ DW_TAG_file_type ]
+!52 = !DIDerivedType(tag: DW_TAG_member, name: "__isa", size: 32, align: 32, file: !152, scope: !24, baseType: !32)
+!53 = !DIDerivedType(tag: DW_TAG_member, name: "__forwarding", size: 32, align: 32, offset: 32, file: !152, scope: !24, baseType: !32)
+!54 = !DIDerivedType(tag: DW_TAG_member, name: "__flags", size: 32, align: 32, offset: 64, file: !152, scope: !24, baseType: !34)
+!55 = !DIDerivedType(tag: DW_TAG_member, name: "__size", size: 32, align: 32, offset: 96, file: !152, scope: !24, baseType: !34)
+!56 = !DIDerivedType(tag: DW_TAG_member, name: "__copy_helper", size: 32, align: 32, offset: 128, file: !152, scope: !24, baseType: !32)
+!57 = !DIDerivedType(tag: DW_TAG_member, name: "__destroy_helper", size: 32, align: 32, offset: 160, file: !152, scope: !24, baseType: !32)
+!58 = !DIDerivedType(tag: DW_TAG_member, name: "mydata", size: 32, align: 32, offset: 192, file: !152, scope: !24, baseType: !59)
+!59 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !60)
+!60 = !DICompositeType(tag: DW_TAG_structure_type, name: "UIMydata", line: 26, size: 128, align: 32, runtimeLang: DW_LANG_ObjC, file: !154, scope: !24, elements: !62)
+!61 = !DIFile(filename: "header11.h", directory: "/Volumes/Sandbox/llvm")
 !62 = !{!63, !71, !75, !79}
-!63 = !{!"0x1c\00\000\000\000\000\000", !60, null, !64} ; [ DW_TAG_inheritance ]
-!64 = !{!"0x13\00NSO\0066\0032\0032\000\000\0016", !155, !40, null, !66, null, null, null} ; [ DW_TAG_structure_type ] [NSO] [line 66, size 32, align 32, offset 0] [def] [from ]
-!65 = !{!"0x29", !155} ; [ DW_TAG_file_type ]
+!63 = !DIDerivedType(tag: DW_TAG_inheritance, file: !61, baseType: !64)
+!64 = !DICompositeType(tag: DW_TAG_structure_type, name: "NSO", line: 66, size: 32, align: 32, runtimeLang: DW_LANG_ObjC, file: !155, scope: !40, elements: !66)
+!65 = !DIFile(filename: "NSO.h", directory: "/Volumes/Sandbox/llvm")
 !66 = !{!67}
-!67 = !{!"0xd\00isa\0067\0032\0032\000\002", !155, !65, !68, !"", !"", !"", i32 0} ; [ DW_TAG_member ]
-!68 = !{!"0x16\00Class\00197\000\000\000\000", !153, !0, !69} ; [ DW_TAG_typedef ]
-!69 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !70} ; [ DW_TAG_pointer_type ]
-!70 = !{!"0x13\00objc_class\000\000\000\000\004\000", !153, !0, null, null, null, null, null} ; [ DW_TAG_structure_type ] [objc_class] [line 0, size 0, align 0, offset 0] [decl] [from ]
-!71 = !{!"0xd\00_mydataRef\0028\0032\0032\0032\000", !154, !61, !72, !"", !"", !"", i32 0} ; [ DW_TAG_member ]
-!72 = !{!"0x16\00CFTypeRef\00313\000\000\000\000", !152, !0, !73} ; [ DW_TAG_typedef ]
-!73 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !74} ; [ DW_TAG_pointer_type ]
-!74 = !{!"0x26\00\000\000\000\000\000", null, !0, null} ; [ DW_TAG_const_type ]
-!75 = !{!"0xd\00_scale\0029\0032\0032\0064\000", !154, !61, !76, !"", !"", !"", i32 0} ; [ DW_TAG_member ]
-!76 = !{!"0x16\00Float\0089\000\000\000\000", !156, !0, !78} ; [ DW_TAG_typedef ]
-!77 = !{!"0x29", !156} ; [ DW_TAG_file_type ]
-!78 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !0} ; [ DW_TAG_base_type ]
-!79 = !{!"0xd\00_mydataFlags\0037\008\008\0096\000", !154, !61, !80, !"", !"", !"", i32 0} ; [ DW_TAG_member ]
-!80 = !{!"0x13\00\0030\008\008\000\000\000", !154, !0, null, !81, null, null, null} ; [ DW_TAG_structure_type ] [line 30, size 8, align 8, offset 0] [def] [from ]
+!67 = !DIDerivedType(tag: DW_TAG_member, name: "isa", line: 67, size: 32, align: 32, flags: DIFlagProtected, file: !155, scope: !65, baseType: !68, extraData: !"")
+!68 = !DIDerivedType(tag: DW_TAG_typedef, name: "Class", line: 197, file: !153, scope: !0, baseType: !69)
+!69 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !70)
+!70 = !DICompositeType(tag: DW_TAG_structure_type, name: "objc_class", flags: DIFlagFwdDecl, file: !153, scope: !0)
+!71 = !DIDerivedType(tag: DW_TAG_member, name: "_mydataRef", line: 28, size: 32, align: 32, offset: 32, file: !154, scope: !61, baseType: !72, extraData: !"")
+!72 = !DIDerivedType(tag: DW_TAG_typedef, name: "CFTypeRef", line: 313, file: !152, scope: !0, baseType: !73)
+!73 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !74)
+!74 = !DIDerivedType(tag: DW_TAG_const_type, scope: !0, baseType: null)
+!75 = !DIDerivedType(tag: DW_TAG_member, name: "_scale", line: 29, size: 32, align: 32, offset: 64, file: !154, scope: !61, baseType: !76, extraData: !"")
+!76 = !DIDerivedType(tag: DW_TAG_typedef, name: "Float", line: 89, file: !156, scope: !0, baseType: !78)
+!77 = !DIFile(filename: "header12.h", directory: "/Volumes/Sandbox/llvm")
+!78 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float)
+!79 = !DIDerivedType(tag: DW_TAG_member, name: "_mydataFlags", line: 37, size: 8, align: 8, offset: 96, file: !154, scope: !61, baseType: !80, extraData: !"")
+!80 = !DICompositeType(tag: DW_TAG_structure_type, line: 30, size: 8, align: 8, file: !154, scope: !0, elements: !81)
 !81 = !{!82, !84, !85, !86, !87, !88}
-!82 = !{!"0xd\00named\0031\001\0032\000\000", !154, !61, !83} ; [ DW_TAG_member ]
-!83 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, !0} ; [ DW_TAG_base_type ]
-!84 = !{!"0xd\00mydataO\0032\003\0032\001\000", !154, !61, !83} ; [ DW_TAG_member ]
-!85 = !{!"0xd\00cached\0033\001\0032\004\000", !154, !61, !83} ; [ DW_TAG_member ]
-!86 = !{!"0xd\00hasBeenCached\0034\001\0032\005\000", !154, !61, !83} ; [ DW_TAG_member ]
-!87 = !{!"0xd\00hasPattern\0035\001\0032\006\000", !154, !61, !83} ; [ DW_TAG_member ]
-!88 = !{!"0xd\00isCIMydata\0036\001\0032\007\000", !154, !61, !83} ; [ DW_TAG_member ]
-!89 = !{!"0xd\00self\00609\0032\0032\00192\000", !152, !24, !90} ; [ DW_TAG_member ]
-!90 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !91} ; [ DW_TAG_pointer_type ]
-!91 = !{!"0x13\00MyWork\0036\00384\0032\000\000\0016", !152, !40, null, !92, null, null, null} ; [ DW_TAG_structure_type ] [MyWork] [line 36, size 384, align 32, offset 0] [def] [from ]
+!82 = !DIDerivedType(tag: DW_TAG_member, name: "named", line: 31, size: 1, align: 32, file: !154, scope: !61, baseType: !83)
+!83 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!84 = !DIDerivedType(tag: DW_TAG_member, name: "mydataO", line: 32, size: 3, align: 32, offset: 1, file: !154, scope: !61, baseType: !83)
+!85 = !DIDerivedType(tag: DW_TAG_member, name: "cached", line: 33, size: 1, align: 32, offset: 4, file: !154, scope: !61, baseType: !83)
+!86 = !DIDerivedType(tag: DW_TAG_member, name: "hasBeenCached", line: 34, size: 1, align: 32, offset: 5, file: !154, scope: !61, baseType: !83)
+!87 = !DIDerivedType(tag: DW_TAG_member, name: "hasPattern", line: 35, size: 1, align: 32, offset: 6, file: !154, scope: !61, baseType: !83)
+!88 = !DIDerivedType(tag: DW_TAG_member, name: "isCIMydata", line: 36, size: 1, align: 32, offset: 7, file: !154, scope: !61, baseType: !83)
+!89 = !DIDerivedType(tag: DW_TAG_member, name: "self", line: 609, size: 32, align: 32, offset: 192, file: !152, scope: !24, baseType: !90)
+!90 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !91)
+!91 = !DICompositeType(tag: DW_TAG_structure_type, name: "MyWork", line: 36, size: 384, align: 32, runtimeLang: DW_LANG_ObjC, file: !152, scope: !40, elements: !92)
 !92 = !{!93, !98, !101, !107, !123}
-!93 = !{!"0x1c\00\000\000\000\000\000", !152, !91, !94} ; [ DW_TAG_inheritance ]
-!94 = !{!"0x13\00twork\0043\0032\0032\000\000\0016", !157, !40, null, !96, null, null, null} ; [ DW_TAG_structure_type ] [twork] [line 43, size 32, align 32, offset 0] [def] [from ]
-!95 = !{!"0x29", !157} ; [ DW_TAG_file_type ]
+!93 = !DIDerivedType(tag: DW_TAG_inheritance, file: !152, scope: !91, baseType: !94)
+!94 = !DICompositeType(tag: DW_TAG_structure_type, name: "twork", line: 43, size: 32, align: 32, runtimeLang: DW_LANG_ObjC, file: !157, scope: !40, elements: !96)
+!95 = !DIFile(filename: "header13.h", directory: "/Volumes/Sandbox/llvm")
 !96 = !{!97}
-!97 = !{!"0x1c\00\000\000\000\000\000", !94, null, !64} ; [ DW_TAG_inheritance ]
-!98 = !{!"0xd\00_itemID\0038\0064\0032\0032\001", !152, !24, !99, !"", !"", !"", i32 0} ; [ DW_TAG_member ]
-!99 = !{!"0x16\00uint64_t\0055\000\000\000\000", !153, !0, !100} ; [ DW_TAG_typedef ]
-!100 = !{!"0x24\00long long unsigned int\000\0064\0032\000\000\007", null, !0} ; [ DW_TAG_base_type ]
-!101 = !{!"0xd\00_library\0039\0032\0032\0096\001", !152, !24, !102, !"", !"", !"", i32 0} ; [ DW_TAG_member ]
-!102 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !103} ; [ DW_TAG_pointer_type ]
-!103 = !{!"0x13\00MyLibrary2\0022\0032\0032\000\000\0016", !158, !40, null, !105, null, null, null} ; [ DW_TAG_structure_type ] [MyLibrary2] [line 22, size 32, align 32, offset 0] [def] [from ]
-!104 = !{!"0x29", !158} ; [ DW_TAG_file_type ]
+!97 = !DIDerivedType(tag: DW_TAG_inheritance, file: !95, baseType: !64)
+!98 = !DIDerivedType(tag: DW_TAG_member, name: "_itemID", line: 38, size: 64, align: 32, offset: 32, flags: DIFlagPrivate, file: !152, scope: !24, baseType: !99, extraData: !"")
+!99 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint64_t", line: 55, file: !153, scope: !0, baseType: !100)
+!100 = !DIBasicType(tag: DW_TAG_base_type, name: "long long unsigned int", size: 64, align: 32, encoding: DW_ATE_unsigned)
+!101 = !DIDerivedType(tag: DW_TAG_member, name: "_library", line: 39, size: 32, align: 32, offset: 96, flags: DIFlagPrivate, file: !152, scope: !24, baseType: !102, extraData: !"")
+!102 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !103)
+!103 = !DICompositeType(tag: DW_TAG_structure_type, name: "MyLibrary2", line: 22, size: 32, align: 32, runtimeLang: DW_LANG_ObjC, file: !158, scope: !40, elements: !105)
+!104 = !DIFile(filename: "header14.h", directory: "/Volumes/Sandbox/llvm")
 !105 = !{!106}
-!106 = !{!"0x1c\00\000\000\000\000\000", !103, null, !64} ; [ DW_TAG_inheritance ]
-!107 = !{!"0xd\00_bounds\0040\00128\0032\00128\001", !152, !24, !108, !"", !"", !"", i32 0} ; [ DW_TAG_member ]
-!108 = !{!"0x16\00CR\0033\000\000\000\000", !153, !0, !109} ; [ DW_TAG_typedef ]
-!109 = !{!"0x13\00CR\0029\00128\0032\000\000\000", !156, !0, null, !110, null, null, null} ; [ DW_TAG_structure_type ] [CR] [line 29, size 128, align 32, offset 0] [def] [from ]
+!106 = !DIDerivedType(tag: DW_TAG_inheritance, file: !104, baseType: !64)
+!107 = !DIDerivedType(tag: DW_TAG_member, name: "_bounds", line: 40, size: 128, align: 32, offset: 128, flags: DIFlagPrivate, file: !152, scope: !24, baseType: !108, extraData: !"")
+!108 = !DIDerivedType(tag: DW_TAG_typedef, name: "CR", line: 33, file: !153, scope: !0, baseType: !109)
+!109 = !DICompositeType(tag: DW_TAG_structure_type, name: "CR", line: 29, size: 128, align: 32, file: !156, scope: !0, elements: !110)
 !110 = !{!111, !117}
-!111 = !{!"0xd\00origin\0030\0064\0032\000\000", !156, !77, !112} ; [ DW_TAG_member ]
-!112 = !{!"0x16\00CP\0017\000\000\000\000", !156, !0, !113} ; [ DW_TAG_typedef ]
-!113 = !{!"0x13\00CP\0013\0064\0032\000\000\000", !156, !0, null, !114, null, null, null} ; [ DW_TAG_structure_type ] [CP] [line 13, size 64, align 32, offset 0] [def] [from ]
+!111 = !DIDerivedType(tag: DW_TAG_member, name: "origin", line: 30, size: 64, align: 32, file: !156, scope: !77, baseType: !112)
+!112 = !DIDerivedType(tag: DW_TAG_typedef, name: "CP", line: 17, file: !156, scope: !0, baseType: !113)
+!113 = !DICompositeType(tag: DW_TAG_structure_type, name: "CP", line: 13, size: 64, align: 32, file: !156, scope: !0, elements: !114)
 !114 = !{!115, !116}
-!115 = !{!"0xd\00x\0014\0032\0032\000\000", !156, !77, !76} ; [ DW_TAG_member ]
-!116 = !{!"0xd\00y\0015\0032\0032\0032\000", !156, !77, !76} ; [ DW_TAG_member ]
-!117 = !{!"0xd\00size\0031\0064\0032\0064\000", !156, !77, !118} ; [ DW_TAG_member ]
-!118 = !{!"0x16\00Size\0025\000\000\000\000", !156, !0, !119} ; [ DW_TAG_typedef ]
-!119 = !{!"0x13\00Size\0021\0064\0032\000\000\000", !156, !0, null, !120, null, null, null} ; [ DW_TAG_structure_type ] [Size] [line 21, size 64, align 32, offset 0] [def] [from ]
+!115 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 14, size: 32, align: 32, file: !156, scope: !77, baseType: !76)
+!116 = !DIDerivedType(tag: DW_TAG_member, name: "y", line: 15, size: 32, align: 32, offset: 32, file: !156, scope: !77, baseType: !76)
+!117 = !DIDerivedType(tag: DW_TAG_member, name: "size", line: 31, size: 64, align: 32, offset: 64, file: !156, scope: !77, baseType: !118)
+!118 = !DIDerivedType(tag: DW_TAG_typedef, name: "Size", line: 25, file: !156, scope: !0, baseType: !119)
+!119 = !DICompositeType(tag: DW_TAG_structure_type, name: "Size", line: 21, size: 64, align: 32, file: !156, scope: !0, elements: !120)
 !120 = !{!121, !122}
-!121 = !{!"0xd\00width\0022\0032\0032\000\000", !156, !77, !76} ; [ DW_TAG_member ]
-!122 = !{!"0xd\00height\0023\0032\0032\0032\000", !156, !77, !76} ; [ DW_TAG_member ]
-!123 = !{!"0xd\00_data\0040\00128\0032\00256\001", !152, !24, !108, !"", !"", !"", i32 0} ; [ DW_TAG_member ]
-!124 = !{!"0xd\00semi\00609\0032\0032\00224\000", !152, !24, !125} ; [ DW_TAG_member ]
-!125 = !{!"0x16\00d_t\0035\000\000\000\000", !152, !0, !126} ; [ DW_TAG_typedef ]
-!126 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !127} ; [ DW_TAG_pointer_type ]
-!127 = !{!"0x13\00my_struct\0049\000\000\000\004\000", !159, !0, null, null, null, null, null} ; [ DW_TAG_structure_type ] [my_struct] [line 49, size 0, align 0, offset 0] [decl] [from ]
-!128 = !{!"0x29", !159} ; [ DW_TAG_file_type ]
-!129 = !MDLocation(line: 609, column: 144, scope: !23)
-!130 = !{!"0x101\00loadedMydata\0033555041\000", !23, !24, !59} ; [ DW_TAG_arg_variable ]
-!131 = !MDLocation(line: 609, column: 155, scope: !23)
-!132 = !{!"0x101\00bounds\0050332257\000", !23, !24, !108} ; [ DW_TAG_arg_variable ]
-!133 = !MDLocation(line: 609, column: 175, scope: !23)
-!134 = !{!"0x101\00data\0067109473\000", !23, !24, !108} ; [ DW_TAG_arg_variable ]
-!135 = !MDLocation(line: 609, column: 190, scope: !23)
-!136 = !{!"0x100\00mydata\00604\000", !23, !24, !50} ; [ DW_TAG_auto_variable ]
-!137 = !MDLocation(line: 604, column: 49, scope: !23)
-!138 = !{!"0x100\00self\00604\000", !23, !40, !90} ; [ DW_TAG_auto_variable ]
-!139 = !{!"0x100\00semi\00607\000", !23, !24, !125} ; [ DW_TAG_auto_variable ]
-!140 = !MDLocation(line: 607, column: 30, scope: !23)
-!141 = !MDLocation(line: 610, column: 17, scope: !142)
-!142 = !{!"0xb\00609\00200\0094", !152, !23} ; [ DW_TAG_lexical_block ]
-!143 = !MDLocation(line: 611, column: 17, scope: !142)
-!144 = !MDLocation(line: 612, column: 17, scope: !142)
-!145 = !MDLocation(line: 613, column: 17, scope: !142)
-!146 = !MDLocation(line: 615, column: 13, scope: !142)
+!121 = !DIDerivedType(tag: DW_TAG_member, name: "width", line: 22, size: 32, align: 32, file: !156, scope: !77, baseType: !76)
+!122 = !DIDerivedType(tag: DW_TAG_member, name: "height", line: 23, size: 32, align: 32, offset: 32, file: !156, scope: !77, baseType: !76)
+!123 = !DIDerivedType(tag: DW_TAG_member, name: "_data", line: 40, size: 128, align: 32, offset: 256, flags: DIFlagPrivate, file: !152, scope: !24, baseType: !108, extraData: !"")
+!124 = !DIDerivedType(tag: DW_TAG_member, name: "semi", line: 609, size: 32, align: 32, offset: 224, file: !152, scope: !24, baseType: !125)
+!125 = !DIDerivedType(tag: DW_TAG_typedef, name: "d_t", line: 35, file: !152, scope: !0, baseType: !126)
+!126 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !127)
+!127 = !DICompositeType(tag: DW_TAG_structure_type, name: "my_struct", line: 49, flags: DIFlagFwdDecl, file: !159, scope: !0)
+!128 = !DIFile(filename: "header15.h", directory: "/Volumes/Sandbox/llvm")
+!129 = !DILocation(line: 609, column: 144, scope: !23)
+!130 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "loadedMydata", line: 609, arg: 2, scope: !23, file: !24, type: !59)
+!131 = !DILocation(line: 609, column: 155, scope: !23)
+!132 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "bounds", line: 609, arg: 3, scope: !23, file: !24, type: !108)
+!133 = !DILocation(line: 609, column: 175, scope: !23)
+!134 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "data", line: 609, arg: 4, scope: !23, file: !24, type: !108)
+!135 = !DILocation(line: 609, column: 190, scope: !23)
+!136 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "mydata", line: 604, scope: !23, file: !24, type: !50)
+!137 = !DILocation(line: 604, column: 49, scope: !23)
+!138 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "self", line: 604, scope: !23, file: !40, type: !90)
+!139 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "semi", line: 607, scope: !23, file: !24, type: !125)
+!140 = !DILocation(line: 607, column: 30, scope: !23)
+!141 = !DILocation(line: 610, column: 17, scope: !142)
+!142 = distinct !DILexicalBlock(line: 609, column: 200, file: !152, scope: !23)
+!143 = !DILocation(line: 611, column: 17, scope: !142)
+!144 = !DILocation(line: 612, column: 17, scope: !142)
+!145 = !DILocation(line: 613, column: 17, scope: !142)
+!146 = !DILocation(line: 615, column: 13, scope: !142)
 !147 = !{!1, !1, !5, !5, !9, !14, !19, !19, !14, !14, !14, !19, !19, !19}
 !148 = !{!23}
-!149 = !{!"header3.h", !"/Volumes/Sandbox/llvm"}
-!150 = !{!"Private.h", !"/Volumes/Sandbox/llvm"}
-!151 = !{!"header4.h", !"/Volumes/Sandbox/llvm"}
-!152 = !{!"MyLibrary.m", !"/Volumes/Sandbox/llvm"}
-!153 = !{!"MyLibrary.i", !"/Volumes/Sandbox/llvm"}
-!154 = !{!"header11.h", !"/Volumes/Sandbox/llvm"}
-!155 = !{!"NSO.h", !"/Volumes/Sandbox/llvm"}
-!156 = !{!"header12.h", !"/Volumes/Sandbox/llvm"}
-!157 = !{!"header13.h", !"/Volumes/Sandbox/llvm"}
-!158 = !{!"header14.h", !"/Volumes/Sandbox/llvm"}
-!159 = !{!"header15.h", !"/Volumes/Sandbox/llvm"}
-!160 = !{!"header.h", !"/Volumes/Sandbox/llvm"}
+!149 = !DIFile(filename: "header3.h", directory: "/Volumes/Sandbox/llvm")
+!150 = !DIFile(filename: "Private.h", directory: "/Volumes/Sandbox/llvm")
+!151 = !DIFile(filename: "header4.h", directory: "/Volumes/Sandbox/llvm")
+!152 = !DIFile(filename: "MyLibrary.m", directory: "/Volumes/Sandbox/llvm")
+!153 = !DIFile(filename: "MyLibrary.i", directory: "/Volumes/Sandbox/llvm")
+!154 = !DIFile(filename: "header11.h", directory: "/Volumes/Sandbox/llvm")
+!155 = !DIFile(filename: "NSO.h", directory: "/Volumes/Sandbox/llvm")
+!156 = !DIFile(filename: "header12.h", directory: "/Volumes/Sandbox/llvm")
+!157 = !DIFile(filename: "header13.h", directory: "/Volumes/Sandbox/llvm")
+!158 = !DIFile(filename: "header14.h", directory: "/Volumes/Sandbox/llvm")
+!159 = !DIFile(filename: "header15.h", directory: "/Volumes/Sandbox/llvm")
+!160 = !DIFile(filename: "header.h", directory: "/Volumes/Sandbox/llvm")
 !161 = !{!"header2.h", !"/Volumes/Sandbox/llvm"}
-!162 = !{i32 1, !"Debug Info Version", i32 2}
-!163 = !{!"0x102\0034\0020\006\0034\004\006\0034\0024"} ; [ DW_TAG_expression ] [DW_OP_plus 20 DW_OP_deref DW_OP_plus 4 DW_OP_deref DW_OP_plus 24]
-!164 = !{!"0x102\0034\0024"} ; [ DW_TAG_expression ] [DW_OP_plus 24]
-!165 = !{!"0x102\0034\0028"} ; [ DW_TAG_expression ] [DW_OP_plus 28]
+!162 = !{i32 1, !"Debug Info Version", i32 3}
+!163 = !DIExpression(DW_OP_plus, 20, DW_OP_deref, DW_OP_plus, 4, DW_OP_deref, DW_OP_plus, 24)
+!164 = !DIExpression(DW_OP_deref, DW_OP_plus, 24)
+!165 = !DIExpression(DW_OP_deref, DW_OP_plus, 28)
diff --git a/test/CodeGen/ARM/debug-info-branch-folding.ll b/test/CodeGen/ARM/debug-info-branch-folding.ll
index 94756953de0a..03b4d6b38151 100644
--- a/test/CodeGen/ARM/debug-info-branch-folding.ll
+++ b/test/CodeGen/ARM/debug-info-branch-folding.ll
@@ -20,18 +20,18 @@ entry:
 
 for.body9:                                        ; preds = %for.body9, %entry
   %add19 = fadd <4 x float> undef, <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, !dbg !39
-  tail call void @llvm.dbg.value(metadata <4 x float> %add19, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !39
+  tail call void @llvm.dbg.value(metadata <4 x float> %add19, i64 0, metadata !27, metadata !DIExpression()), !dbg !39
   %add20 = fadd <4 x float> undef, <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, !dbg !39
-  tail call void @llvm.dbg.value(metadata <4 x float> %add20, i64 0, metadata !28, metadata !{!"0x102"}), !dbg !39
+  tail call void @llvm.dbg.value(metadata <4 x float> %add20, i64 0, metadata !28, metadata !DIExpression()), !dbg !39
   br i1 %cond, label %for.end54, label %for.body9, !dbg !44
 
 for.end54:                                        ; preds = %for.body9
   %tmp115 = extractelement <4 x float> %add19, i32 1
   %conv6.i75 = fpext float %tmp115 to double, !dbg !45
-  %call.i82 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45
+  %call.i82 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45
   %tmp116 = extractelement <4 x float> %add20, i32 1
   %conv6.i76 = fpext float %tmp116 to double, !dbg !45
-  %call.i83 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i76, double undef, double undef) nounwind, !dbg !45
+  %call.i83 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i76, double undef, double undef) nounwind, !dbg !45
   ret i32 0, !dbg !49
 }
 
@@ -42,60 +42,60 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.module.flags = !{!56}
 !llvm.dbg.cu = !{!2}
 
-!0 = !{!"0x2e\00test0001\00test0001\00\003\000\001\000\006\00256\001\000", !54, null, !3, i32 0, <4 x float> (float)* @test0001, null, null, !51} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !54} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 3.0 (trunk 129915)\001\00\000\00\001", !54, !17, !17, !50, null,  null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !54, !1, i32 0, !4, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = !DISubprogram(name: "test0001", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !54, scope: null, type: !3, function: <4 x float> (float)* @test0001, variables: !51)
+!1 = !DIFile(filename: "build2.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !54, enums: !{}, retainedTypes: !{}, subprograms: !50, imports:  null)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x16\00v4f32\0014\000\000\000\000", !54, !2, !6} ; [ DW_TAG_typedef ]
-!6 = !{!"0x1\00\000\00128\00128\000\000", !54, !2, !7, !8, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 128, offset 0] [from float]
-!7 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !2} ; [ DW_TAG_base_type ]
+!5 = !DIDerivedType(tag: DW_TAG_typedef, name: "v4f32", line: 14, file: !54, scope: !2, baseType: !6)
+!6 = !DICompositeType(tag: DW_TAG_array_type, size: 128, align: 128, file: !54, scope: !2, baseType: !7, elements: !8)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float)
 !8 = !{!9}
-!9 = !{!"0x21\000\004"}         ; [ DW_TAG_subrange_type ]
-!10 = !{!"0x2e\00main\00main\00\0059\000\001\000\006\00256\001\000", !54, null, !11, null, i32 (i32, i8**, i1)* @main, null, null, !52} ; [ DW_TAG_subprogram ] [line 59] [def] [scope 0] [main]
-!11 = !{!"0x15\00\000\000\000\000\000\000", !54, !1, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!9 = !DISubrange(count: 4)
+!10 = !DISubprogram(name: "main", line: 59, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !54, scope: null, type: !11, function: i32 (i32, i8**, i1)* @main, variables: !52)
+!11 = !DISubroutineType(types: !12)
 !12 = !{!13}
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ]
-!14 = !{!"0x2e\00printFV\00printFV\00\0041\001\001\000\006\00256\001\000", !55, null, !16, null, null, null, null, !53} ; [ DW_TAG_subprogram ] [line 41] [local] [def] [scope 0] [printFV]
-!15 = !{!"0x29", !55} ; [ DW_TAG_file_type ]
-!16 = !{!"0x15\00\000\000\000\000\000\000", !55, !15, null, !17, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!14 = !DISubprogram(name: "printFV", line: 41, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !55, scope: null, type: !16, variables: !53)
+!15 = !DIFile(filename: "/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", directory: "/private/tmp")
+!16 = !DISubroutineType(types: !17)
 !17 = !{null}
-!18 = !{!"0x101\00a\0016777219\000", !0, !1, !7} ; [ DW_TAG_arg_variable ]
-!19 = !{!"0x101\00argc\0016777275\000", !10, !1, !13} ; [ DW_TAG_arg_variable ]
-!20 = !{!"0x101\00argv\0033554491\000", !10, !1, !21} ; [ DW_TAG_arg_variable ]
-!21 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !22} ; [ DW_TAG_pointer_type ]
-!22 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !23} ; [ DW_TAG_pointer_type ]
-!23 = !{!"0x24\00char\000\008\008\000\000\006", null, !2} ; [ DW_TAG_base_type ]
-!24 = !{!"0x100\00i\0060\000", !25, !1, !13} ; [ DW_TAG_auto_variable ]
-!25 = !{!"0xb\0059\0033\0014", !1, !10} ; [ DW_TAG_lexical_block ]
-!26 = !{!"0x100\00j\0060\000", !25, !1, !13} ; [ DW_TAG_auto_variable ]
-!27 = !{!"0x100\00x\0061\000", !25, !1, !5} ; [ DW_TAG_auto_variable ]
-!28 = !{!"0x100\00y\0062\000", !25, !1, !5} ; [ DW_TAG_auto_variable ]
-!29 = !{!"0x100\00z\0063\000", !25, !1, !5} ; [ DW_TAG_auto_variable ]
-!30 = !{!"0x101\00F\0016777257\000", !14, !15, !31} ; [ DW_TAG_arg_variable ]
-!31 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !32} ; [ DW_TAG_pointer_type ]
-!32 = !{!"0x16\00FV\0025\000\000\000\000", !55, !2, !33} ; [ DW_TAG_typedef ]
-!33 = !{!"0x17\00\0022\00128\00128\000\000\000", !55, !2, i32 0, !34, null} ; [ DW_TAG_union_type ]
+!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 3, arg: 1, scope: !0, file: !1, type: !7)
+!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 59, arg: 1, scope: !10, file: !1, type: !13)
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 59, arg: 2, scope: !10, file: !1, type: !21)
+!21 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !22)
+!22 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !23)
+!23 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 60, scope: !25, file: !1, type: !13)
+!25 = distinct !DILexicalBlock(line: 59, column: 33, file: !1, scope: !10)
+!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 60, scope: !25, file: !1, type: !13)
+!27 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 61, scope: !25, file: !1, type: !5)
+!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y", line: 62, scope: !25, file: !1, type: !5)
+!29 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "z", line: 63, scope: !25, file: !1, type: !5)
+!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "F", line: 41, arg: 1, scope: !14, file: !15, type: !31)
+!31 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !32)
+!32 = !DIDerivedType(tag: DW_TAG_typedef, name: "FV", line: 25, file: !55, scope: !2, baseType: !33)
+!33 = !DICompositeType(tag: DW_TAG_union_type, line: 22, size: 128, align: 128, file: !55, scope: !2, elements: !34)
 !34 = !{!35, !37}
-!35 = !{!"0xd\00V\0023\00128\00128\000\000", !55, !15, !36} ; [ DW_TAG_member ]
-!36 = !{!"0x16\00v4sf\003\000\000\000\000", !55, !2, !6} ; [ DW_TAG_typedef ]
-!37 = !{!"0xd\00A\0024\00128\0032\000\000", !55, !15, !38} ; [ DW_TAG_member ]
-!38 = !{!"0x1\00\000\00128\0032\000\000", null, !2, !7, !8, i32 0, i32 0} ; [ DW_TAG_array_type ]
-!39 = !MDLocation(line: 79, column: 7, scope: !40)
-!40 = !{!"0xb\0075\0035\0018", !1, !41} ; [ DW_TAG_lexical_block ]
-!41 = !{!"0xb\0075\005\0017", !1, !42} ; [ DW_TAG_lexical_block ]
-!42 = !{!"0xb\0071\0032\0016", !1, !43} ; [ DW_TAG_lexical_block ]
-!43 = !{!"0xb\0071\003\0015", !1, !25} ; [ DW_TAG_lexical_block ]
-!44 = !MDLocation(line: 75, column: 5, scope: !42)
-!45 = !MDLocation(line: 42, column: 2, scope: !46, inlinedAt: !48)
-!46 = !{!"0xb\0042\002\0020", !15, !47} ; [ DW_TAG_lexical_block ]
-!47 = !{!"0xb\0041\0028\0019", !15, !14} ; [ DW_TAG_lexical_block ]
-!48 = !MDLocation(line: 95, column: 3, scope: !25)
-!49 = !MDLocation(line: 99, column: 3, scope: !25)
+!35 = !DIDerivedType(tag: DW_TAG_member, name: "V", line: 23, size: 128, align: 128, file: !55, scope: !15, baseType: !36)
+!36 = !DIDerivedType(tag: DW_TAG_typedef, name: "v4sf", line: 3, file: !55, scope: !2, baseType: !6)
+!37 = !DIDerivedType(tag: DW_TAG_member, name: "A", line: 24, size: 128, align: 32, file: !55, scope: !15, baseType: !38)
+!38 = !DICompositeType(tag: DW_TAG_array_type, size: 128, align: 32, scope: !2, baseType: !7, elements: !8)
+!39 = !DILocation(line: 79, column: 7, scope: !40)
+!40 = distinct !DILexicalBlock(line: 75, column: 35, file: !1, scope: !41)
+!41 = distinct !DILexicalBlock(line: 75, column: 5, file: !1, scope: !42)
+!42 = distinct !DILexicalBlock(line: 71, column: 32, file: !1, scope: !43)
+!43 = distinct !DILexicalBlock(line: 71, column: 3, file: !1, scope: !25)
+!44 = !DILocation(line: 75, column: 5, scope: !42)
+!45 = !DILocation(line: 42, column: 2, scope: !46, inlinedAt: !48)
+!46 = distinct !DILexicalBlock(line: 42, column: 2, file: !15, scope: !47)
+!47 = distinct !DILexicalBlock(line: 41, column: 28, file: !15, scope: !14)
+!48 = !DILocation(line: 95, column: 3, scope: !25)
+!49 = !DILocation(line: 99, column: 3, scope: !25)
 !50 = !{!0, !10, !14}
 !51 = !{!18}
 !52 = !{!19, !20, !24, !26, !27, !28, !29}
 !53 = !{!30}
-!54 = !{!"build2.c", !"/private/tmp"}
-!55 = !{!"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", !"/private/tmp"}
-!56 = !{i32 1, !"Debug Info Version", i32 2}
+!54 = !DIFile(filename: "build2.c", directory: "/private/tmp")
+!55 = !DIFile(filename: "/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", directory: "/private/tmp")
+!56 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/ARM/debug-info-d16-reg.ll b/test/CodeGen/ARM/debug-info-d16-reg.ll
index 85b510f175ee..27bd3b8639c4 100644
--- a/test/CodeGen/ARM/debug-info-d16-reg.ll
+++ b/test/CodeGen/ARM/debug-info-d16-reg.ll
@@ -12,21 +12,21 @@ target triple = "thumbv7-apple-darwin10"
 
 define i32 @inlineprinter(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize {
 entry:
-  tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !26
-  tail call void @llvm.dbg.value(metadata double %val, i64 0, metadata !20, metadata !{!"0x102"}), !dbg !26
-  tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !21, metadata !{!"0x102"}), !dbg !26
+  tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !19, metadata !DIExpression()), !dbg !26
+  tail call void @llvm.dbg.value(metadata double %val, i64 0, metadata !20, metadata !DIExpression()), !dbg !26
+  tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !21, metadata !DIExpression()), !dbg !26
   %0 = zext i8 %c to i32, !dbg !27
-  %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !27
+  %1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !27
   ret i32 0, !dbg !29
 }
 
 define i32 @printer(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize noinline {
 entry:
-  tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !30
-  tail call void @llvm.dbg.value(metadata double %val, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !30
-  tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !30
+  tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !16, metadata !DIExpression()), !dbg !30
+  tail call void @llvm.dbg.value(metadata double %val, i64 0, metadata !17, metadata !DIExpression()), !dbg !30
+  tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !18, metadata !DIExpression()), !dbg !30
   %0 = zext i8 %c to i32, !dbg !31
-  %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !31
+  %1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !31
   ret i32 0, !dbg !33
 }
 
@@ -36,20 +36,20 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !22, metadata !{!"0x102"}), !dbg !34
-  tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !23, metadata !{!"0x102"}), !dbg !34
+  tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !22, metadata !DIExpression()), !dbg !34
+  tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !23, metadata !DIExpression()), !dbg !34
   %0 = sitofp i32 %argc to double, !dbg !35
   %1 = fadd double %0, 5.555552e+05, !dbg !35
-  tail call void @llvm.dbg.value(metadata double %1, i64 0, metadata !24, metadata !{!"0x102"}), !dbg !35
-  %2 = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0)) nounwind, !dbg !36
-  %3 = getelementptr inbounds i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !37
+  tail call void @llvm.dbg.value(metadata double %1, i64 0, metadata !24, metadata !DIExpression()), !dbg !35
+  %2 = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0)) nounwind, !dbg !36
+  %3 = getelementptr inbounds i8, i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !37
   %4 = trunc i32 %argc to i8, !dbg !37
   %5 = add i8 %4, 97, !dbg !37
-  tail call void @llvm.dbg.value(metadata i8* %3, i64 0, metadata !19, metadata !{!"0x102"}) nounwind, !dbg !38
-  tail call void @llvm.dbg.value(metadata double %1, i64 0, metadata !20, metadata !{!"0x102"}) nounwind, !dbg !38
-  tail call void @llvm.dbg.value(metadata i8 %5, i64 0, metadata !21, metadata !{!"0x102"}) nounwind, !dbg !38
+  tail call void @llvm.dbg.value(metadata i8* %3, i64 0, metadata !49, metadata !DIExpression()) nounwind, !dbg !38
+  tail call void @llvm.dbg.value(metadata double %1, i64 0, metadata !50, metadata !DIExpression()) nounwind, !dbg !38
+  tail call void @llvm.dbg.value(metadata i8 %5, i64 0, metadata !51, metadata !DIExpression()) nounwind, !dbg !38
   %6 = zext i8 %5 to i32, !dbg !39
-  %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %3, double %1, i32 %6) nounwind, !dbg !39
+  %7 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %3, double %1, i32 %6) nounwind, !dbg !39
   %8 = tail call i32 @printer(i8* %3, double %1, i8 zeroext %5) nounwind, !dbg !40
   ret i32 0, !dbg !41
 }
@@ -59,52 +59,57 @@ declare i32 @puts(i8* nocapture) nounwind
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!48}
 
-!0 = !{!"0x2e\00printer\00printer\00printer\0012\000\001\000\006\00256\001\0012", !46, !1, !3, null, i32 (i8*, double, i8)* @printer, null, null, !43} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !46} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\001\00(LLVM build 00)\001\00\000\00\001", !46, !47, !47, !42, null,  null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !46, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "printer", linkageName: "printer", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 12, file: !46, scope: !1, type: !3, function: i32 (i8*, double, i8)* @printer, variables: !43)
+!1 = !DIFile(filename: "a.c", directory: "/tmp/")
+!2 = !DICompileUnit(language: DW_LANG_C89, producer: "(LLVM build 00)", isOptimized: true, emissionKind: 1, file: !46, enums: !47, retainedTypes: !47, subprograms: !42, imports:  null)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5, !6, !7, !8}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", !46, !1} ; [ DW_TAG_base_type ]
-!6 = !{!"0xf\00\000\0032\0032\000\000", !46, !1, null} ; [ DW_TAG_pointer_type ]
-!7 = !{!"0x24\00double\000\0064\0032\000\000\004", !46, !1} ; [ DW_TAG_base_type ]
-!8 = !{!"0x24\00unsigned char\000\008\008\000\000\008", !46, !1} ; [ DW_TAG_base_type ]
-!9 = !{!"0x2e\00inlineprinter\00inlineprinter\00inlineprinter\005\000\001\000\006\00256\001\005", !46, !1, !3, null, i32 (i8*, double, i8)* @inlineprinter, null, null, !44} ; [ DW_TAG_subprogram ]
-!10 = !{!"0x2e\00main\00main\00main\0018\000\001\000\006\00256\001\0018", !46, !1, !11, null, i32 (i32, i8**)* @main, null, null, !45} ; [ DW_TAG_subprogram ]
-!11 = !{!"0x15\00\000\000\000\000\000\000", !46, !1, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !46, scope: !1, baseType: null)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 32, encoding: DW_ATE_float)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char)
+!9 = !DISubprogram(name: "inlineprinter", linkageName: "inlineprinter", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !46, scope: !1, type: !3, function: i32 (i8*, double, i8)* @inlineprinter, variables: !44)
+!10 = !DISubprogram(name: "main", linkageName: "main", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 18, file: !46, scope: !1, type: !11, function: i32 (i32, i8**)* @main, variables: !45)
+!11 = !DISubroutineType(types: !12)
 !12 = !{!5, !5, !13}
-!13 = !{!"0xf\00\000\0032\0032\000\000", !46, !1, !14} ; [ DW_TAG_pointer_type ]
-!14 = !{!"0xf\00\000\0032\0032\000\000", !46, !1, !15} ; [ DW_TAG_pointer_type ]
-!15 = !{!"0x24\00char\000\008\008\000\000\006", !46, !1} ; [ DW_TAG_base_type ]
-!16 = !{!"0x101\00ptr\0011\000", !0, !1, !6} ; [ DW_TAG_arg_variable ]
-!17 = !{!"0x101\00val\0011\000", !0, !1, !7} ; [ DW_TAG_arg_variable ]
-!18 = !{!"0x101\00c\0011\000", !0, !1, !8} ; [ DW_TAG_arg_variable ]
-!19 = !{!"0x101\00ptr\004\000", !9, !1, !6} ; [ DW_TAG_arg_variable ]
-!20 = !{!"0x101\00val\004\000", !9, !1, !7} ; [ DW_TAG_arg_variable ]
-!21 = !{!"0x101\00c\004\000", !9, !1, !8} ; [ DW_TAG_arg_variable ]
-!22 = !{!"0x101\00argc\0017\000", !10, !1, !5} ; [ DW_TAG_arg_variable ]
-!23 = !{!"0x101\00argv\0017\000", !10, !1, !13} ; [ DW_TAG_arg_variable ]
-!24 = !{!"0x100\00dval\0019\000", !25, !1, !7} ; [ DW_TAG_auto_variable ]
-!25 = !{!"0xb\0018\000\002", !46, !10} ; [ DW_TAG_lexical_block ]
-!26 = !MDLocation(line: 4, scope: !9)
-!27 = !MDLocation(line: 6, scope: !28)
-!28 = !{!"0xb\005\000\001", !46, !9} ; [ DW_TAG_lexical_block ]
-!29 = !MDLocation(line: 7, scope: !28)
-!30 = !MDLocation(line: 11, scope: !0)
-!31 = !MDLocation(line: 13, scope: !32)
-!32 = !{!"0xb\0012\000\000", !46, !0} ; [ DW_TAG_lexical_block ]
-!33 = !MDLocation(line: 14, scope: !32)
-!34 = !MDLocation(line: 17, scope: !10)
-!35 = !MDLocation(line: 19, scope: !25)
-!36 = !MDLocation(line: 20, scope: !25)
-!37 = !MDLocation(line: 21, scope: !25)
-!38 = !MDLocation(line: 4, scope: !9, inlinedAt: !37)
-!39 = !MDLocation(line: 6, scope: !28, inlinedAt: !37)
-!40 = !MDLocation(line: 22, scope: !25)
-!41 = !MDLocation(line: 23, scope: !25)
+!13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !46, scope: !1, baseType: !14)
+!14 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !46, scope: !1, baseType: !15)
+!15 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 11, arg: 1, scope: !0, file: !1, type: !6)
+!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 11, arg: 2, scope: !0, file: !1, type: !7)
+!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 11, arg: 3, scope: !0, file: !1, type: !8)
+!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 1, scope: !9, file: !1, type: !6)
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 2, scope: !9, file: !1, type: !7)
+!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 3, scope: !9, file: !1, type: !8)
+
+!49 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 1, scope: !9, file: !1, type: !6)
+!50 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 2, scope: !9, file: !1, type: !7)
+!51 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 2, scope: !9, file: !1, type: !8)
+
+!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 17, arg: 0, scope: !10, file: !1, type: !5)
+!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 17, arg: 0, scope: !10, file: !1, type: !13)
+!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "dval", line: 19, scope: !25, file: !1, type: !7)
+!25 = distinct !DILexicalBlock(line: 18, column: 0, file: !46, scope: !10)
+!26 = !DILocation(line: 4, scope: !9)
+!27 = !DILocation(line: 6, scope: !28)
+!28 = distinct !DILexicalBlock(line: 5, column: 0, file: !46, scope: !9)
+!29 = !DILocation(line: 7, scope: !28)
+!30 = !DILocation(line: 11, scope: !0)
+!31 = !DILocation(line: 13, scope: !32)
+!32 = distinct !DILexicalBlock(line: 12, column: 0, file: !46, scope: !0)
+!33 = !DILocation(line: 14, scope: !32)
+!34 = !DILocation(line: 17, scope: !10)
+!35 = !DILocation(line: 19, scope: !25)
+!36 = !DILocation(line: 20, scope: !25)
+!37 = !DILocation(line: 21, scope: !25)
+!38 = !DILocation(line: 4, scope: !9, inlinedAt: !37)
+!39 = !DILocation(line: 6, scope: !28, inlinedAt: !37)
+!40 = !DILocation(line: 22, scope: !25)
+!41 = !DILocation(line: 23, scope: !25)
 !42 = !{!0, !9, !10}
 !43 = !{!16, !17, !18}
 !44 = !{!19, !20, !21}
 !45 = !{!22, !23, !24}
-!46 = !{!"a.c", !"/tmp/"}
-!47 = !{i32 0}
-!48 = !{i32 1, !"Debug Info Version", i32 2}
+!46 = !DIFile(filename: "a.c", directory: "/tmp/")
+!47 = !{}
+!48 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/ARM/debug-info-no-frame.ll b/test/CodeGen/ARM/debug-info-no-frame.ll
new file mode 100644
index 000000000000..e00563cc47c4
--- /dev/null
+++ b/test/CodeGen/ARM/debug-info-no-frame.ll
@@ -0,0 +1,36 @@
+; RUN: llc -mtriple=armv7-none-linux-gnueabihf < %s -o - | FileCheck %s
+
+; Function Attrs: nounwind
+define void @need_cfi_def_cfa_offset() #0 {
+; CHECK-LABEL: need_cfi_def_cfa_offset:
+; CHECK: sub	sp, sp, #4
+; CHECK: .cfi_def_cfa_offset 4
+entry:
+  %Depth = alloca i32, align 4
+  call void @llvm.dbg.declare(metadata i32* %Depth, metadata !9, metadata !10), !dbg !11
+  store i32 2, i32* %Depth, align 4, !dbg !11
+  ret void, !dbg !12
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7, !8}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false)
+!1 = !DIFile(filename: "file.c", directory: "/dir")
+!2 = !{}
+!3 = !DISubprogram(name: "need_cfi_def_cfa_offset", scope: !1, file: !1, line: 1, type: !4, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, function: void ()* @need_cfi_def_cfa_offset, variables: !2)
+!4 = !DISubroutineType(types: !5)
+!5 = !{null}
+!6 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!7 = !{i32 2, !"Dwarf Version", i32 4}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
+!9 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "Depth", scope: !3, file: !1, line: 3, type: !6)
+!10 = !DIExpression()
+!11 = !DILocation(line: 3, column: 9, scope: !3)
+!12 = !DILocation(line: 7, column: 5, scope: !3)
diff --git a/test/CodeGen/ARM/debug-info-qreg.ll b/test/CodeGen/ARM/debug-info-qreg.ll
index c05df6ab3d51..665818fc0b2e 100644
--- a/test/CodeGen/ARM/debug-info-qreg.ll
+++ b/test/CodeGen/ARM/debug-info-qreg.ll
@@ -3,13 +3,13 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-
 target triple = "thumbv7-apple-macosx10.6.7"
 
 ;CHECK: sub-register DW_OP_regx
-;CHECK-NEXT: ascii
+;CHECK-NEXT: 256
 ;CHECK-NEXT: DW_OP_piece
-;CHECK-NEXT: byte   8
+;CHECK-NEXT: 8
 ;CHECK-NEXT: sub-register DW_OP_regx
-;CHECK-NEXT: ascii
+;CHECK-NEXT: 257
 ;CHECK-NEXT: DW_OP_piece
-;CHECK-NEXT: byte   8
+;CHECK-NEXT: 8
 
 @.str = external constant [13 x i8]
 
@@ -24,10 +24,10 @@ for.body9:                                        ; preds = %for.body9, %entry
   br i1 undef, label %for.end54, label %for.body9, !dbg !44
 
 for.end54:                                        ; preds = %for.body9
-  tail call void @llvm.dbg.value(metadata <4 x float> %add19, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !39
+  tail call void @llvm.dbg.value(metadata <4 x float> %add19, i64 0, metadata !27, metadata !DIExpression()), !dbg !39
   %tmp115 = extractelement <4 x float> %add19, i32 1
   %conv6.i75 = fpext float %tmp115 to double, !dbg !45
-  %call.i82 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45
+  %call.i82 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45
   ret i32 0, !dbg !49
 }
 
@@ -38,60 +38,60 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!56}
 
-!0 = !{!"0x2e\00test0001\00test0001\00\003\000\001\000\006\00256\001\003", !54, !1, !3, null, <4 x float> (float)* @test0001, null, null, !51} ; [ DW_TAG_subprogram ] [line 3] [def] [test0001]
-!1 = !{!"0x29", !54} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 3.0 (trunk 129915)\001\00\000\00\001", !54, !17, !17, !50, null,  null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !54, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "test0001", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !54, scope: !1, type: !3, function: <4 x float> (float)* @test0001, variables: !51)
+!1 = !DIFile(filename: "build2.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !54, enums: !{}, retainedTypes: !{}, subprograms: !50, imports:  null)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x16\00v4f32\0014\000\000\000\000", !54, !2, !6} ; [ DW_TAG_typedef ]
-!6 = !{!"0x1\00\000\00128\00128\000\000", !2, null, !7, !8, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 128, offset 0] [from float]
-!7 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !2} ; [ DW_TAG_base_type ]
+!5 = !DIDerivedType(tag: DW_TAG_typedef, name: "v4f32", line: 14, file: !54, scope: !2, baseType: !6)
+!6 = !DICompositeType(tag: DW_TAG_array_type, size: 128, align: 128, file: !1, baseType: !7, elements: !8)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float)
 !8 = !{!9}
-!9 = !{!"0x21\000\004"}         ; [ DW_TAG_subrange_type ]
-!10 = !{!"0x2e\00main\00main\00\0059\000\001\000\006\00256\001\0059", !54, !1, !11, null, i32 (i32, i8**)* @main, null, null, !52} ; [ DW_TAG_subprogram ] [line 59] [def] [main]
-!11 = !{!"0x15\00\000\000\000\000\000\000", !54, !1, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!9 = !DISubrange(count: 4)
+!10 = !DISubprogram(name: "main", line: 59, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 59, file: !54, scope: !1, type: !11, function: i32 (i32, i8**)* @main, variables: !52)
+!11 = !DISubroutineType(types: !12)
 !12 = !{!13}
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ]
-!14 = !{!"0x2e\00printFV\00printFV\00\0041\001\001\000\006\00256\001\0041", !55, !15, !16, null, null, null, null, !53} ; [ DW_TAG_subprogram ] [line 41] [local] [def] [printFV]
-!15 = !{!"0x29", !55} ; [ DW_TAG_file_type ]
-!16 = !{!"0x15\00\000\000\000\000\000\000", !55, !15, null, !17, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!14 = !DISubprogram(name: "printFV", line: 41, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 41, file: !55, scope: !15, type: !16, variables: !53)
+!15 = !DIFile(filename: "/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", directory: "/private/tmp")
+!16 = !DISubroutineType(types: !17)
 !17 = !{null}
-!18 = !{!"0x101\00a\0016777219\000", !0, !1, !7} ; [ DW_TAG_arg_variable ]
-!19 = !{!"0x101\00argc\0016777275\000", !10, !1, !13} ; [ DW_TAG_arg_variable ]
-!20 = !{!"0x101\00argv\0033554491\000", !10, !1, !21} ; [ DW_TAG_arg_variable ]
-!21 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !22} ; [ DW_TAG_pointer_type ]
-!22 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !23} ; [ DW_TAG_pointer_type ]
-!23 = !{!"0x24\00char\000\008\008\000\000\006", null, !2} ; [ DW_TAG_base_type ]
-!24 = !{!"0x100\00i\0060\000", !25, !1, !13} ; [ DW_TAG_auto_variable ]
-!25 = !{!"0xb\0059\0033\0014", !54, !10} ; [ DW_TAG_lexical_block ]
-!26 = !{!"0x100\00j\0060\000", !25, !1, !13} ; [ DW_TAG_auto_variable ]
-!27 = !{!"0x100\00x\0061\000", !25, !1, !5} ; [ DW_TAG_auto_variable ]
-!28 = !{!"0x100\00y\0062\000", !25, !1, !5} ; [ DW_TAG_auto_variable ]
-!29 = !{!"0x100\00z\0063\000", !25, !1, !5} ; [ DW_TAG_auto_variable ]
-!30 = !{!"0x101\00F\0016777257\000", !14, !15, !31} ; [ DW_TAG_arg_variable ]
-!31 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !32} ; [ DW_TAG_pointer_type ]
-!32 = !{!"0x16\00FV\0025\000\000\000\000", !55, !2, !33} ; [ DW_TAG_typedef ]
-!33 = !{!"0x17\00\0022\00128\00128\000\000\000", !55, !2, i32 0, !34, null} ; [ DW_TAG_union_type ]
+!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 3, arg: 1, scope: !0, file: !1, type: !7)
+!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 59, arg: 1, scope: !10, file: !1, type: !13)
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 59, arg: 2, scope: !10, file: !1, type: !21)
+!21 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !22)
+!22 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !23)
+!23 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 60, scope: !25, file: !1, type: !13)
+!25 = distinct !DILexicalBlock(line: 59, column: 33, file: !54, scope: !10)
+!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 60, scope: !25, file: !1, type: !13)
+!27 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 61, scope: !25, file: !1, type: !5)
+!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y", line: 62, scope: !25, file: !1, type: !5)
+!29 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "z", line: 63, scope: !25, file: !1, type: !5)
+!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "F", line: 41, arg: 1, scope: !14, file: !15, type: !31)
+!31 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !32)
+!32 = !DIDerivedType(tag: DW_TAG_typedef, name: "FV", line: 25, file: !55, scope: !2, baseType: !33)
+!33 = !DICompositeType(tag: DW_TAG_union_type, line: 22, size: 128, align: 128, file: !55, scope: !2, elements: !34)
 !34 = !{!35, !37}
-!35 = !{!"0xd\00V\0023\00128\00128\000\000", !55, !15, !36} ; [ DW_TAG_member ]
-!36 = !{!"0x16\00v4sf\003\000\000\000\000", !55, !2, !6} ; [ DW_TAG_typedef ]
-!37 = !{!"0xd\00A\0024\00128\0032\000\000", !55, !15, !38} ; [ DW_TAG_member ]
-!38 = !{!"0x1\00\000\00128\0032\000\000", null, !2, !7, !8, i32 0, i32 0} ; [ DW_TAG_array_type ]
-!39 = !MDLocation(line: 79, column: 7, scope: !40)
-!40 = !{!"0xb\0075\0035\0018", !54, !41} ; [ DW_TAG_lexical_block ]
-!41 = !{!"0xb\0075\005\0017", !54, !42} ; [ DW_TAG_lexical_block ]
-!42 = !{!"0xb\0071\0032\0016", !54, !43} ; [ DW_TAG_lexical_block ]
-!43 = !{!"0xb\0071\003\0015", !54, !25} ; [ DW_TAG_lexical_block ]
-!44 = !MDLocation(line: 75, column: 5, scope: !42)
-!45 = !MDLocation(line: 42, column: 2, scope: !46, inlinedAt: !48)
-!46 = !{!"0xb\0042\002\0020", !55, !47} ; [ DW_TAG_lexical_block ]
-!47 = !{!"0xb\0041\0028\0019", !55, !14} ; [ DW_TAG_lexical_block ]
-!48 = !MDLocation(line: 95, column: 3, scope: !25)
-!49 = !MDLocation(line: 99, column: 3, scope: !25)
+!35 = !DIDerivedType(tag: DW_TAG_member, name: "V", line: 23, size: 128, align: 128, file: !55, scope: !15, baseType: !36)
+!36 = !DIDerivedType(tag: DW_TAG_typedef, name: "v4sf", line: 3, file: !55, scope: !2, baseType: !6)
+!37 = !DIDerivedType(tag: DW_TAG_member, name: "A", line: 24, size: 128, align: 32, file: !55, scope: !15, baseType: !38)
+!38 = !DICompositeType(tag: DW_TAG_array_type, size: 128, align: 32, scope: !2, baseType: !7, elements: !8)
+!39 = !DILocation(line: 79, column: 7, scope: !40)
+!40 = distinct !DILexicalBlock(line: 75, column: 35, file: !54, scope: !41)
+!41 = distinct !DILexicalBlock(line: 75, column: 5, file: !54, scope: !42)
+!42 = distinct !DILexicalBlock(line: 71, column: 32, file: !54, scope: !43)
+!43 = distinct !DILexicalBlock(line: 71, column: 3, file: !54, scope: !25)
+!44 = !DILocation(line: 75, column: 5, scope: !42)
+!45 = !DILocation(line: 42, column: 2, scope: !46, inlinedAt: !48)
+!46 = distinct !DILexicalBlock(line: 42, column: 2, file: !55, scope: !47)
+!47 = distinct !DILexicalBlock(line: 41, column: 28, file: !55, scope: !14)
+!48 = !DILocation(line: 95, column: 3, scope: !25)
+!49 = !DILocation(line: 99, column: 3, scope: !25)
 !50 = !{!0, !10, !14}
 !51 = !{!18}
 !52 = !{!19, !20, !24, !26, !27, !28, !29}
 !53 = !{!30}
-!54 = !{!"build2.c", !"/private/tmp"}
-!55 = !{!"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", !"/private/tmp"}
-!56 = !{i32 1, !"Debug Info Version", i32 2}
+!54 = !DIFile(filename: "build2.c", directory: "/private/tmp")
+!55 = !DIFile(filename: "/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", directory: "/private/tmp")
+!56 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/ARM/debug-info-s16-reg.ll b/test/CodeGen/ARM/debug-info-s16-reg.ll
index 9b303dde2e35..ec080f20db9c 100644
--- a/test/CodeGen/ARM/debug-info-s16-reg.ll
+++ b/test/CodeGen/ARM/debug-info-s16-reg.ll
@@ -2,7 +2,7 @@
 ; Radar 9309221
 ; Test dwarf reg no for s16
 ;CHECK: super-register DW_OP_regx
-;CHECK-NEXT: ascii
+;CHECK-NEXT: 264
 ;CHECK-NEXT: DW_OP_piece
 ;CHECK-NEXT: 4
 
@@ -14,12 +14,12 @@ target triple = "thumbv7-apple-macosx10.6.7"
 
 define i32 @inlineprinter(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize ssp {
 entry:
-  tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !8, metadata !{!"0x102"}), !dbg !24
-  tail call void @llvm.dbg.value(metadata float %val, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !25
-  tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !12, metadata !{!"0x102"}), !dbg !26
+  tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !8, metadata !DIExpression()), !dbg !24
+  tail call void @llvm.dbg.value(metadata float %val, i64 0, metadata !10, metadata !DIExpression()), !dbg !25
+  tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !12, metadata !DIExpression()), !dbg !26
   %conv = fpext float %val to double, !dbg !27
   %conv3 = zext i8 %c to i32, !dbg !27
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !27
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !27
   ret i32 0, !dbg !29
 }
 
@@ -27,33 +27,33 @@ declare i32 @printf(i8* nocapture, ...) nounwind optsize
 
 define i32 @printer(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize noinline ssp {
 entry:
-  tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !30
-  tail call void @llvm.dbg.value(metadata float %val, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !31
-  tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !32
+  tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !14, metadata !DIExpression()), !dbg !30
+  tail call void @llvm.dbg.value(metadata float %val, i64 0, metadata !15, metadata !DIExpression()), !dbg !31
+  tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !16, metadata !DIExpression()), !dbg !32
   %conv = fpext float %val to double, !dbg !33
   %conv3 = zext i8 %c to i32, !dbg !33
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !33
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !33
   ret i32 0, !dbg !35
 }
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize ssp {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !36
-  tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !37
+  tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !17, metadata !DIExpression()), !dbg !36
+  tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !18, metadata !DIExpression()), !dbg !37
   %conv = sitofp i32 %argc to double, !dbg !38
   %add = fadd double %conv, 5.555552e+05, !dbg !38
   %conv1 = fptrunc double %add to float, !dbg !38
-  tail call void @llvm.dbg.value(metadata float %conv1, i64 0, metadata !22, metadata !{!"0x102"}), !dbg !38
-  %call = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0)) nounwind optsize, !dbg !39
-  %add.ptr = getelementptr i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !40
+  tail call void @llvm.dbg.value(metadata float %conv1, i64 0, metadata !22, metadata !DIExpression()), !dbg !38
+  %call = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0)) nounwind optsize, !dbg !39
+  %add.ptr = getelementptr i8, i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !40
   %add5 = add nsw i32 %argc, 97, !dbg !40
   %conv6 = trunc i32 %add5 to i8, !dbg !40
-  tail call void @llvm.dbg.value(metadata i8* %add.ptr, i64 0, metadata !8, metadata !{!"0x102"}) nounwind, !dbg !41
-  tail call void @llvm.dbg.value(metadata float %conv1, i64 0, metadata !10, metadata !{!"0x102"}) nounwind, !dbg !42
-  tail call void @llvm.dbg.value(metadata i8 %conv6, i64 0, metadata !12, metadata !{!"0x102"}) nounwind, !dbg !43
+  tail call void @llvm.dbg.value(metadata i8* %add.ptr, i64 0, metadata !58, metadata !DIExpression()) nounwind, !dbg !41
+  tail call void @llvm.dbg.value(metadata float %conv1, i64 0, metadata !60, metadata !DIExpression()) nounwind, !dbg !42
+  tail call void @llvm.dbg.value(metadata i8 %conv6, i64 0, metadata !62, metadata !DIExpression()) nounwind, !dbg !43
   %conv.i = fpext float %conv1 to double, !dbg !44
   %conv3.i = and i32 %add5, 255, !dbg !44
-  %call.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %add.ptr, double %conv.i, i32 %conv3.i) nounwind optsize, !dbg !44
+  %call.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %add.ptr, double %conv.i, i32 %conv3.i) nounwind optsize, !dbg !44
   %call14 = tail call i32 @printer(i8* %add.ptr, float %conv1, i8 zeroext %conv6) optsize, !dbg !45
   ret i32 0, !dbg !46
 }
@@ -65,57 +65,62 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!53}
 
-!0 = !{!"0x2e\00inlineprinter\00inlineprinter\00\005\000\001\000\006\00256\001\005", !51, !1, !3, null, i32 (i8*, float, i8)* @inlineprinter, null, null, !48} ; [ DW_TAG_subprogram ] [line 5] [def] [inlineprinter]
-!1 = !{!"0x29", !51} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 3.0 (trunk 129915)\001\00\000\00\001", !51, !52, !52, !47, null,  null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !51, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "inlineprinter", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !51, scope: !1, type: !3, function: i32 (i8*, float, i8)* @inlineprinter, variables: !48)
+!1 = !DIFile(filename: "a.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !51, enums: !52, retainedTypes: !52, subprograms: !47, imports:  null)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ]
-!6 = !{!"0x2e\00printer\00printer\00\0012\000\001\000\006\00256\001\0012", !51, !1, !3, null, i32 (i8*, float, i8)* @printer, null, null, !49} ; [ DW_TAG_subprogram ] [line 12] [def] [printer]
-!7 = !{!"0x2e\00main\00main\00\0018\000\001\000\006\00256\001\0018", !51, !1, !3, null, i32 (i32, i8**)* @main, null, null, !50} ; [ DW_TAG_subprogram ] [line 18] [def] [main]
-!8 = !{!"0x101\00ptr\0016777220\000", !0, !1, !9} ; [ DW_TAG_arg_variable ]
-!9 = !{!"0xf\00\000\0032\0032\000\000", null, !2, null} ; [ DW_TAG_pointer_type ]
-!10 = !{!"0x101\00val\0033554436\000", !0, !1, !11} ; [ DW_TAG_arg_variable ]
-!11 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !2} ; [ DW_TAG_base_type ]
-!12 = !{!"0x101\00c\0050331652\000", !0, !1, !13} ; [ DW_TAG_arg_variable ]
-!13 = !{!"0x24\00unsigned char\000\008\008\000\000\008", null, !2} ; [ DW_TAG_base_type ]
-!14 = !{!"0x101\00ptr\0016777227\000", !6, !1, !9} ; [ DW_TAG_arg_variable ]
-!15 = !{!"0x101\00val\0033554443\000", !6, !1, !11} ; [ DW_TAG_arg_variable ]
-!16 = !{!"0x101\00c\0050331659\000", !6, !1, !13} ; [ DW_TAG_arg_variable ]
-!17 = !{!"0x101\00argc\0016777233\000", !7, !1, !5} ; [ DW_TAG_arg_variable ]
-!18 = !{!"0x101\00argv\0033554449\000", !7, !1, !19} ; [ DW_TAG_arg_variable ]
-!19 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !20} ; [ DW_TAG_pointer_type ]
-!20 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !21} ; [ DW_TAG_pointer_type ]
-!21 = !{!"0x24\00char\000\008\008\000\000\006", null, !2} ; [ DW_TAG_base_type ]
-!22 = !{!"0x100\00dval\0019\000", !23, !1, !11} ; [ DW_TAG_auto_variable ]
-!23 = !{!"0xb\0018\001\002", !51, !7} ; [ DW_TAG_lexical_block ]
-!24 = !MDLocation(line: 4, column: 22, scope: !0)
-!25 = !MDLocation(line: 4, column: 33, scope: !0)
-!26 = !MDLocation(line: 4, column: 52, scope: !0)
-!27 = !MDLocation(line: 6, column: 3, scope: !28)
-!28 = !{!"0xb\005\001\000", !51, !0} ; [ DW_TAG_lexical_block ]
-!29 = !MDLocation(line: 7, column: 3, scope: !28)
-!30 = !MDLocation(line: 11, column: 42, scope: !6)
-!31 = !MDLocation(line: 11, column: 53, scope: !6)
-!32 = !MDLocation(line: 11, column: 72, scope: !6)
-!33 = !MDLocation(line: 13, column: 3, scope: !34)
-!34 = !{!"0xb\0012\001\001", !51, !6} ; [ DW_TAG_lexical_block ]
-!35 = !MDLocation(line: 14, column: 3, scope: !34)
-!36 = !MDLocation(line: 17, column: 15, scope: !7)
-!37 = !MDLocation(line: 17, column: 28, scope: !7)
-!38 = !MDLocation(line: 19, column: 31, scope: !23)
-!39 = !MDLocation(line: 20, column: 3, scope: !23)
-!40 = !MDLocation(line: 21, column: 3, scope: !23)
-!41 = !MDLocation(line: 4, column: 22, scope: !0, inlinedAt: !40)
-!42 = !MDLocation(line: 4, column: 33, scope: !0, inlinedAt: !40)
-!43 = !MDLocation(line: 4, column: 52, scope: !0, inlinedAt: !40)
-!44 = !MDLocation(line: 6, column: 3, scope: !28, inlinedAt: !40)
-!45 = !MDLocation(line: 22, column: 3, scope: !23)
-!46 = !MDLocation(line: 23, column: 1, scope: !23)
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DISubprogram(name: "printer", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 12, file: !51, scope: !1, type: !3, function: i32 (i8*, float, i8)* @printer, variables: !49)
+!7 = !DISubprogram(name: "main", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 18, file: !51, scope: !1, type: !3, function: i32 (i32, i8**)* @main, variables: !50)
+!8 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 1, scope: !0, file: !1, type: !9)
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: null)
+!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 2, scope: !0, file: !1, type: !11)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float)
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 3, scope: !0, file: !1, type: !13)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char)
+
+!58 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 1, scope: !0, file: !1, type: !9)
+!60 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 2, scope: !0, file: !1, type: !11)
+!62 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 3, scope: !0, file: !1, type: !13)
+
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 11, arg: 1, scope: !6, file: !1, type: !9)
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 11, arg: 2, scope: !6, file: !1, type: !11)
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 11, arg: 3, scope: !6, file: !1, type: !13)
+!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 17, arg: 1, scope: !7, file: !1, type: !5)
+!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 17, arg: 2, scope: !7, file: !1, type: !19)
+!19 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !20)
+!20 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !21)
+!21 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!22 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "dval", line: 19, scope: !23, file: !1, type: !11)
+!23 = distinct !DILexicalBlock(line: 18, column: 1, file: !51, scope: !7)
+!24 = !DILocation(line: 4, column: 22, scope: !0)
+!25 = !DILocation(line: 4, column: 33, scope: !0)
+!26 = !DILocation(line: 4, column: 52, scope: !0)
+!27 = !DILocation(line: 6, column: 3, scope: !28)
+!28 = distinct !DILexicalBlock(line: 5, column: 1, file: !51, scope: !0)
+!29 = !DILocation(line: 7, column: 3, scope: !28)
+!30 = !DILocation(line: 11, column: 42, scope: !6)
+!31 = !DILocation(line: 11, column: 53, scope: !6)
+!32 = !DILocation(line: 11, column: 72, scope: !6)
+!33 = !DILocation(line: 13, column: 3, scope: !34)
+!34 = distinct !DILexicalBlock(line: 12, column: 1, file: !51, scope: !6)
+!35 = !DILocation(line: 14, column: 3, scope: !34)
+!36 = !DILocation(line: 17, column: 15, scope: !7)
+!37 = !DILocation(line: 17, column: 28, scope: !7)
+!38 = !DILocation(line: 19, column: 31, scope: !23)
+!39 = !DILocation(line: 20, column: 3, scope: !23)
+!40 = !DILocation(line: 21, column: 3, scope: !23)
+!41 = !DILocation(line: 4, column: 22, scope: !0, inlinedAt: !40)
+!42 = !DILocation(line: 4, column: 33, scope: !0, inlinedAt: !40)
+!43 = !DILocation(line: 4, column: 52, scope: !0, inlinedAt: !40)
+!44 = !DILocation(line: 6, column: 3, scope: !28, inlinedAt: !40)
+!45 = !DILocation(line: 22, column: 3, scope: !23)
+!46 = !DILocation(line: 23, column: 1, scope: !23)
 !47 = !{!0, !6, !7}
 !48 = !{!8, !10, !12}
 !49 = !{!14, !15, !16}
 !50 = !{!17, !18, !22}
-!51 = !{!"a.c", !"/private/tmp"}
-!52 = !{i32 0}
-!53 = !{i32 1, !"Debug Info Version", i32 2}
+!51 = !DIFile(filename: "a.c", directory: "/private/tmp")
+!52 = !{}
+!53 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/ARM/debug-info-sreg2.ll b/test/CodeGen/ARM/debug-info-sreg2.ll
index 977a6f27677c..f22559efad4d 100644
--- a/test/CodeGen/ARM/debug-info-sreg2.ll
+++ b/test/CodeGen/ARM/debug-info-sreg2.ll
@@ -15,7 +15,7 @@ target triple = "thumbv7-apple-macosx10.6.7"
 define void @_Z3foov() optsize ssp {
 entry:
   %call = tail call float @_Z3barv() optsize, !dbg !11
-  tail call void @llvm.dbg.value(metadata float %call, i64 0, metadata !5, metadata !{!"0x102"}), !dbg !11
+  tail call void @llvm.dbg.value(metadata float %call, i64 0, metadata !5, metadata !DIExpression()), !dbg !11
   %call16 = tail call float @_Z2f2v() optsize, !dbg !12
   %cmp7 = fcmp olt float %call, %call16, !dbg !12
   br i1 %cmp7, label %for.body, label %for.end, !dbg !12
@@ -43,24 +43,24 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!20}
 
-!0 = !{!"0x11\004\00clang version 3.0 (trunk 130845)\001\00\000\00\001", !18, !19, !19, !16, null,  null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"0x2e\00foo\00foo\00_Z3foov\005\000\001\000\006\00256\001\005", !18, !2, !3, null, void ()* @_Z3foov, null, null, !17} ; [ DW_TAG_subprogram ] [line 5] [def] [foo]
-!2 = !{!"0x29", !18} ; [ DW_TAG_file_type ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !18, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.0 (trunk 130845)", isOptimized: true, emissionKind: 1, file: !18, enums: !19, retainedTypes: !19, subprograms: !16, imports:  null)
+!1 = !DISubprogram(name: "foo", linkageName: "_Z3foov", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !18, scope: !2, type: !3, function: void ()* @_Z3foov, variables: !17)
+!2 = !DIFile(filename: "k.cc", directory: "/private/tmp")
+!3 = !DISubroutineType(types: !4)
 !4 = !{null}
-!5 = !{!"0x100\00k\006\000", !6, !2, !7} ; [ DW_TAG_auto_variable ]
-!6 = !{!"0xb\005\0012\000", !18, !1} ; [ DW_TAG_lexical_block ]
-!7 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !0} ; [ DW_TAG_base_type ]
-!8 = !{!"0x100\00y\008\000", !9, !2, !7} ; [ DW_TAG_auto_variable ]
-!9 = !{!"0xb\007\0025\002", !18, !10} ; [ DW_TAG_lexical_block ]
-!10 = !{!"0xb\007\003\001", !18, !6} ; [ DW_TAG_lexical_block ]
-!11 = !MDLocation(line: 6, column: 18, scope: !6)
-!12 = !MDLocation(line: 7, column: 3, scope: !6)
-!13 = !MDLocation(line: 8, column: 20, scope: !9)
-!14 = !MDLocation(line: 7, column: 20, scope: !10)
-!15 = !MDLocation(line: 10, column: 1, scope: !6)
+!5 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 6, scope: !6, file: !2, type: !7)
+!6 = distinct !DILexicalBlock(line: 5, column: 12, file: !18, scope: !1)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float)
+!8 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y", line: 8, scope: !9, file: !2, type: !7)
+!9 = distinct !DILexicalBlock(line: 7, column: 25, file: !18, scope: !10)
+!10 = distinct !DILexicalBlock(line: 7, column: 3, file: !18, scope: !6)
+!11 = !DILocation(line: 6, column: 18, scope: !6)
+!12 = !DILocation(line: 7, column: 3, scope: !6)
+!13 = !DILocation(line: 8, column: 20, scope: !9)
+!14 = !DILocation(line: 7, column: 20, scope: !10)
+!15 = !DILocation(line: 10, column: 1, scope: !6)
 !16 = !{!1}
 !17 = !{!5, !8}
-!18 = !{!"k.cc", !"/private/tmp"}
-!19 = !{i32 0}
-!20 = !{i32 1, !"Debug Info Version", i32 2}
+!18 = !DIFile(filename: "k.cc", directory: "/private/tmp")
+!19 = !{}
+!20 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/ARM/debug-segmented-stacks.ll b/test/CodeGen/ARM/debug-segmented-stacks.ll
index 7ea5665a7a9b..47d366e49ded 100644
--- a/test/CodeGen/ARM/debug-segmented-stacks.ll
+++ b/test/CodeGen/ARM/debug-segmented-stacks.ll
@@ -39,40 +39,40 @@ define void @test_basic() #0 {
 ; ARM-linux       .cfi_same_value r5
 }
 
-!0 = !{!"0x11\0012\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/var.c] [DW_LANG_C99]
-!1 = !{!"var.c", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "var.c", directory: "/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00test_basic\00test_basic\00\005\000\001\000\006\00256\000\005", !1, !5, !6, null, void ()* @test_basic, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [sum]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/var.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "test_basic", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, function: void ()* @test_basic, variables: !2)
+!5 = !DIFile(filename: "var.c", directory: "/tmp")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 4}
-!10 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !{i32 1, !"Debug Info Version", i32 3}
 !11 = !{!"clang version 3.5 "}
-!12 = !{!"0x101\00count\0016777221\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [count] [line 5]
-!13 = !MDLocation(line: 5, scope: !4)
-!14 = !{!"0x100\00vl\006\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [vl] [line 6]
-!15 = !{!"0x16\00va_list\0030\000\000\000\000", !16, null, !17} ; [ DW_TAG_typedef ] [va_list] [line 30, size 0, align 0, offset 0] [from __builtin_va_list]
-!16 = !{!"/linux-x86_64-high/gcc_4.7.2/dbg/llvm/bin/../lib/clang/3.5/include/stdarg.h", !"/tmp"}
-!17 = !{!"0x16\00__builtin_va_list\006\000\000\000\000", !1, null, !18} ; [ DW_TAG_typedef ] [__builtin_va_list] [line 6, size 0, align 0, offset 0] [from __va_list]
-!18 = !{!"0x13\00__va_list\006\0032\0032\000\000\000", !1, null, null, !19, null, null, null} ; [ DW_TAG_structure_type ] [__va_list] [line 6, size 32, align 32, offset 0] [def] [from ]
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "count", line: 5, arg: 1, scope: !4, file: !5, type: !8)
+!13 = !DILocation(line: 5, scope: !4)
+!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vl", line: 6, scope: !4, file: !5, type: !15)
+!15 = !DIDerivedType(tag: DW_TAG_typedef, name: "va_list", line: 30, file: !16, baseType: !17)
+!16 = !DIFile(filename: "/linux-x86_64-high/gcc_4.7.2/dbg/llvm/bin/../lib/clang/3.5/include/stdarg.h", directory: "/tmp")
+!17 = !DIDerivedType(tag: DW_TAG_typedef, name: "__builtin_va_list", line: 6, file: !1, baseType: !18)
+!18 = !DICompositeType(tag: DW_TAG_structure_type, name: "__va_list", line: 6, size: 32, align: 32, file: !1, elements: !19)
 !19 = !{!20}
-!20 = !{!"0xd\00__ap\006\0032\0032\000\000", !1, !18, !21} ; [ DW_TAG_member ] [__ap] [line 6, size 32, align 32, offset 0] [from ]
-!21 = !{!"0xf\00\000\0032\0032\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from ]
-!22 = !MDLocation(line: 6, scope: !4)
-!23 = !MDLocation(line: 7, scope: !4)
-!24 = !{!"0x100\00test_basic\008\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [sum] [line 8]
-!25 = !MDLocation(line: 8, scope: !4)
-!26 = !{!"0x100\00i\009\000", !27, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 9]
-!27 = !{!"0xb\009\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/tmp/var.c]
-!28 = !MDLocation(line: 9, scope: !27)
-!29 = !MDLocation(line: 10, scope: !30)
-!30 = !{!"0xb\009\000\001", !1, !27} ; [ DW_TAG_lexical_block ] [/tmp/var.c]
-!31 = !MDLocation(line: 11, scope: !30)
-!32 = !MDLocation(line: 12, scope: !4)
-!33 = !MDLocation(line: 13, scope: !4)
+!20 = !DIDerivedType(tag: DW_TAG_member, name: "__ap", line: 6, size: 32, align: 32, file: !1, scope: !18, baseType: !21)
+!21 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: null)
+!22 = !DILocation(line: 6, scope: !4)
+!23 = !DILocation(line: 7, scope: !4)
+!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "test_basic", line: 8, scope: !4, file: !5, type: !8)
+!25 = !DILocation(line: 8, scope: !4)
+!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 9, scope: !27, file: !5, type: !8)
+!27 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !4)
+!28 = !DILocation(line: 9, scope: !27)
+!29 = !DILocation(line: 10, scope: !30)
+!30 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !27)
+!31 = !DILocation(line: 11, scope: !30)
+!32 = !DILocation(line: 12, scope: !4)
+!33 = !DILocation(line: 13, scope: !4)
 
 ; Just to prevent the alloca from being optimized away
 declare void @dummy_use(i32*, i32)
diff --git a/test/CodeGen/ARM/disable-fp-elim.ll b/test/CodeGen/ARM/disable-fp-elim.ll
new file mode 100644
index 000000000000..dafeda2ac762
--- /dev/null
+++ b/test/CodeGen/ARM/disable-fp-elim.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -mtriple armv7-none-linux-gnueabi -O1 | FileCheck %s --check-prefix=DISABLE-FP-ELIM
+; RUN: llc < %s -mtriple armv7-none-linux-gnueabi -disable-fp-elim -O1 | FileCheck %s --check-prefix=DISABLE-FP-ELIM
+; RUN: llc < %s -mtriple armv7-none-linux-gnueabi -disable-fp-elim=false -O1 | FileCheck %s --check-prefix=ENABLE-FP-ELIM
+; RUN: llc < %s -mtriple armv7-none-linux-gnueabi -disable-fp-elim=false -O0 | FileCheck %s --check-prefix=DISABLE-FP-ELIM
+
+; Check that command line option "-disable-fp-elim" overrides function attribute
+; "no-frame-pointer-elim". Also, check frame pointer elimination is disabled
+; when fast-isel is used.
+
+; ENABLE-FP-ELIM-NOT: .setfp
+; DISABLE-FP-ELIM: .setfp r11, sp
+
+define i32 @foo1(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) #0 {
+entry:
+  %call = tail call i32 @foo2(i32 %a)
+  %add = add i32 %c, %b
+  %add1 = add i32 %add, %d
+  %add2 = add i32 %add1, %e
+  %add3 = add i32 %add2, %call
+  ret i32 %add3
+}
+
+declare i32 @foo2(i32)
+
+attributes #0 = { nounwind "no-frame-pointer-elim"="true" }
diff --git a/test/CodeGen/ARM/div.ll b/test/CodeGen/ARM/div.ll
index a339c816c578..7b298fee42a5 100644
--- a/test/CodeGen/ARM/div.ll
+++ b/test/CodeGen/ARM/div.ll
@@ -1,11 +1,13 @@
-; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-ARM
-; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift     | FileCheck %s -check-prefix=CHECK-HWDIV
-; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | FileCheck %s -check-prefix=CHECK-HWDIV
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8    | FileCheck %s -check-prefix=CHECK-SWDIV
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift        | FileCheck %s -check-prefix=CHECK-HWDIV
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4    | FileCheck %s -check-prefix=CHECK-SWDIV
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f   | FileCheck %s -check-prefix=CHECK-SWDIV
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5    | FileCheck %s -check-prefix=CHECK-HWDIV
 
 define i32 @f1(i32 %a, i32 %b) {
 entry:
-; CHECK-ARM: f1
-; CHECK-ARM: __divsi3
+; CHECK-SWDIV: f1
+; CHECK-SWDIV: __divsi3
 
 ; CHECK-HWDIV: f1
 ; CHECK-HWDIV: sdiv
@@ -15,8 +17,8 @@ entry:
 
 define i32 @f2(i32 %a, i32 %b) {
 entry:
-; CHECK-ARM: f2
-; CHECK-ARM: __udivsi3
+; CHECK-SWDIV: f2
+; CHECK-SWDIV: __udivsi3
 
 ; CHECK-HWDIV: f2
 ; CHECK-HWDIV: udiv
@@ -26,8 +28,8 @@ entry:
 
 define i32 @f3(i32 %a, i32 %b) {
 entry:
-; CHECK-ARM: f3
-; CHECK-ARM: __modsi3
+; CHECK-SWDIV: f3
+; CHECK-SWDIV: __modsi3
 
 ; CHECK-HWDIV: f3
 ; CHECK-HWDIV: sdiv
@@ -38,8 +40,8 @@ entry:
 
 define i32 @f4(i32 %a, i32 %b) {
 entry:
-; CHECK-ARM: f4
-; CHECK-ARM: __umodsi3
+; CHECK-SWDIV: f4
+; CHECK-SWDIV: __umodsi3
 
 ; CHECK-HWDIV: f4
 ; CHECK-HWDIV: udiv
diff --git a/test/CodeGen/ARM/divmod.ll b/test/CodeGen/ARM/divmod.ll
index 7be0c796bd21..9336d0c477d1 100644
--- a/test/CodeGen/ARM/divmod.ll
+++ b/test/CodeGen/ARM/divmod.ll
@@ -16,7 +16,7 @@ entry:
   %div = sdiv i32 %x, %y
   store i32 %div, i32* %P, align 4
   %rem = srem i32 %x, %y
-  %arrayidx6 = getelementptr inbounds i32* %P, i32 1
+  %arrayidx6 = getelementptr inbounds i32, i32* %P, i32 1
   store i32 %rem, i32* %arrayidx6, align 4
   ret void
 }
@@ -34,7 +34,7 @@ entry:
   %div = udiv i32 %x, %y
   store i32 %div, i32* %P, align 4
   %rem = urem i32 %x, %y
-  %arrayidx6 = getelementptr inbounds i32* %P, i32 1
+  %arrayidx6 = getelementptr inbounds i32, i32* %P, i32 1
   store i32 %rem, i32* %arrayidx6, align 4
   ret void
 }
@@ -47,7 +47,7 @@ define void @do_indent(i32 %cols) nounwind {
 entry:
 ; A8-LABEL: do_indent:
 ; SWIFT-LABEL: do_indent:
-  %0 = load i32* @flags, align 4
+  %0 = load i32, i32* @flags, align 4
   %1 = and i32 %0, 67108864
   %2 = icmp eq i32 %1, 0
   br i1 %2, label %bb1, label %bb
@@ -57,7 +57,7 @@ bb:
 ; SWIFT: sdiv
 ; SWIFT: mls
 ; SWIFT-NOT: bl __divmodsi4
-  %3 = load i32* @tabsize, align 4
+  %3 = load i32, i32* @tabsize, align 4
   %4 = srem i32 %cols, %3
   %5 = sdiv i32 %cols, %3
   %6 = tail call i32 @llvm.objectsize.i32.p0i8(i8* null, i1 false)
@@ -66,7 +66,7 @@ bb:
 
 bb1:
   %line_indent_len.0 = phi i32 [ %4, %bb ], [ 0, %entry ]
-  %8 = getelementptr inbounds i8* null, i32 %line_indent_len.0
+  %8 = getelementptr inbounds i8, i8* null, i32 %line_indent_len.0
   store i8 0, i8* %8, align 1
   ret void
 }
diff --git a/test/CodeGen/ARM/dwarf-eh.ll b/test/CodeGen/ARM/dwarf-eh.ll
index 0b8a072ec95c..c890206b3532 100644
--- a/test/CodeGen/ARM/dwarf-eh.ll
+++ b/test/CodeGen/ARM/dwarf-eh.ll
@@ -2,6 +2,10 @@
 ; RUN: FileCheck %s
 ; RUN: llc -mtriple=arm-netbsd-eabi -o - -filetype=asm %s \
 ; RUN: -relocation-model=pic | FileCheck -check-prefix=CHECK-PIC %s
+; RUN: llc -mtriple=armv7-bitrig-gnueabihf -o - -filetype=asm %s | \
+; RUN: FileCheck %s
+; RUN: llc -mtriple=armv7-bitrig-gnueabihf -o - -filetype=asm %s \
+; RUN: -relocation-model=pic | FileCheck -check-prefix=CHECK-PIC %s
 
 ; ModuleID = 'test.cc'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
@@ -11,7 +15,7 @@ target triple = "armv5e--netbsd-eabi"
 
 @_ZTVN10__cxxabiv117__class_type_infoE = external global i8*
 @_ZTS9exception = linkonce_odr constant [11 x i8] c"9exception\00"
-@_ZTI9exception = linkonce_odr unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv117__class_type_infoE, i32 2) to i8*), i8* getelementptr inbounds ([11 x i8]* @_ZTS9exception, i32 0, i32 0) }
+@_ZTI9exception = linkonce_odr unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i32 2) to i8*), i8* getelementptr inbounds ([11 x i8], [11 x i8]* @_ZTS9exception, i32 0, i32 0) }
 
 define void @f() uwtable {
   %1 = alloca i8*
@@ -30,12 +34,12 @@ define void @f() uwtable {
   store i32 %7, i32* %2
   br label %8
 
-  %9 = load i32* %2
+  %9 = load i32, i32* %2
   %10 = call i32 @llvm.eh.typeid.for(i8* bitcast ({ i8*, i8* }* @_ZTI9exception to i8*)) nounwind
   %11 = icmp eq i32 %9, %10
   br i1 %11, label %12, label %17
 
-  %13 = load i8** %1
+  %13 = load i8*, i8** %1
   %14 = call i8* @__cxa_begin_catch(i8* %13) #3
   %15 = bitcast i8* %14 to %struct.exception*
   store %struct.exception* %15, %struct.exception** %e
@@ -44,8 +48,8 @@ define void @f() uwtable {
 
   ret void
 
-  %18 = load i8** %1
-  %19 = load i32* %2
+  %18 = load i8*, i8** %1
+  %19 = load i32, i32* %2
   %20 = insertvalue { i8*, i32 } undef, i8* %18, 0
   %21 = insertvalue { i8*, i32 } %20, i32 %19, 1
   resume { i8*, i32 } %21
diff --git a/test/CodeGen/ARM/dyn-stackalloc.ll b/test/CodeGen/ARM/dyn-stackalloc.ll
index 4ac5b8a31e5f..5b963fd64dea 100644
--- a/test/CodeGen/ARM/dyn-stackalloc.ll
+++ b/test/CodeGen/ARM/dyn-stackalloc.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm-eabi %s -o /dev/null
+; RUN: llc -mcpu=generic -mtriple=arm-eabi -verify-machineinstrs < %s | FileCheck %s
 
 %struct.comment = type { i8**, i32*, i32, i8* }
 %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
@@ -7,7 +7,19 @@
 @str215 = external global [2 x i8]
 
 define void @t1(%struct.state* %v) {
-  %tmp6 = load i32* null
+
+; Make sure we generate:
+;   sub	sp, sp, r1
+; instead of:
+;   sub	r1, sp, r1
+;   mov	sp, r1
+
+; CHECK-LABEL: @t1
+; CHECK: bic [[REG1:r[0-9]+]],
+; CHECK-NOT: sub r{{[0-9]+}}, sp, [[REG1]]
+; CHECK: sub sp, sp, [[REG1]]
+
+  %tmp6 = load i32, i32* null
   %tmp8 = alloca float, i32 %tmp6
   store i32 1, i32* null
   br i1 false, label %bb123.preheader, label %return
@@ -17,8 +29,8 @@ bb123.preheader:                                  ; preds = %0
 
 bb43:                                             ; preds = %bb123.preheader
   call fastcc void @f1(float* %tmp8, float* null, i32 0)
-  %tmp70 = load i32* null
-  %tmp85 = getelementptr float* %tmp8, i32 0
+  %tmp70 = load i32, i32* null
+  %tmp85 = getelementptr float, float* %tmp8, i32 0
   call fastcc void @f2(float* null, float* null, float* %tmp85, i32 %tmp70)
   ret void
 
@@ -38,8 +50,8 @@ define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) {
   %tmp6 = alloca i8, i32 %tmp5
   %tmp9 = call i8* @strcpy(i8* %tmp6, i8* %tag)
   %tmp6.len = call i32 @strlen(i8* %tmp6)
-  %tmp6.indexed = getelementptr i8* %tmp6, i32 %tmp6.len
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp6.indexed, i8* getelementptr inbounds ([2 x i8]* @str215, i32 0, i32 0), i32 2, i32 1, i1 false)
+  %tmp6.indexed = getelementptr i8, i8* %tmp6, i32 %tmp6.len
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp6.indexed, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str215, i32 0, i32 0), i32 2, i32 1, i1 false)
   %tmp15 = call i8* @strcat(i8* %tmp6, i8* %contents)
   call fastcc void @comment_add(%struct.comment* %vc, i8* %tmp6)
   ret void
diff --git a/test/CodeGen/ARM/ehabi.ll b/test/CodeGen/ARM/ehabi.ll
index ebf0c2a00330..088e48d2d793 100644
--- a/test/CodeGen/ARM/ehabi.ll
+++ b/test/CodeGen/ARM/ehabi.ll
@@ -146,8 +146,8 @@ declare void @_ZSt9terminatev()
 ; CHECK-FP:   push   {r4, r5, r6, r7, r8, r9, r10, r11, lr}
 ; CHECK-FP:   .setfp r11, sp, #28
 ; CHECK-FP:   add    r11, sp, #28
-; CHECK-FP:   .pad   #28
-; CHECK-FP:   sub    sp, sp, #28
+; CHECK-FP:   .pad   #44
+; CHECK-FP:   sub    sp, sp, #44
 ; CHECK-FP:   .personality __gxx_personality_v0
 ; CHECK-FP:   .handlerdata
 ; CHECK-FP:   .fnend
@@ -156,8 +156,8 @@ declare void @_ZSt9terminatev()
 ; CHECK-FP-ELIM:   .fnstart
 ; CHECK-FP-ELIM:   .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
 ; CHECK-FP-ELIM:   push  {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-FP-ELIM:   .pad  #28
-; CHECK-FP-ELIM:   sub   sp, sp, #28
+; CHECK-FP-ELIM:   .pad  #36
+; CHECK-FP-ELIM:   sub   sp, sp, #36
 ; CHECK-FP-ELIM:   .personality __gxx_personality_v0
 ; CHECK-FP-ELIM:   .handlerdata
 ; CHECK-FP-ELIM:   .fnend
@@ -205,7 +205,7 @@ declare void @_ZSt9terminatev()
 ; DWARF-FP:    .cfi_offset r4, -36
 ; DWARF-FP:    add r11, sp, #28
 ; DWARF-FP:    .cfi_def_cfa r11, 8
-; DWARF-FP:    sub sp, sp, #28
+; DWARF-FP:    sub sp, sp, #44
 ; DWARF-FP:    sub sp, r11, #28
 ; DWARF-FP:    pop {r4, r5, r6, r7, r8, r9, r10, r11, lr}
 ; DWARF-FP:    mov pc, lr
@@ -226,9 +226,9 @@ declare void @_ZSt9terminatev()
 ; DWARF-FP-ELIM:    .cfi_offset r6, -28
 ; DWARF-FP-ELIM:    .cfi_offset r5, -32
 ; DWARF-FP-ELIM:    .cfi_offset r4, -36
-; DWARF-FP-ELIM:    sub sp, sp, #28
-; DWARF-FP-ELIM:    .cfi_def_cfa_offset 64
-; DWARF-FP-ELIM:    add sp, sp, #28
+; DWARF-FP-ELIM:    sub sp, sp, #36
+; DWARF-FP-ELIM:    .cfi_def_cfa_offset 72
+; DWARF-FP-ELIM:    add sp, sp, #36
 ; DWARF-FP-ELIM:    pop {r4, r5, r6, r7, r8, r9, r10, r11, lr}
 ; DWARF-FP-ELIM:    mov pc, lr
 ; DWARF-FP-ELIM:    .cfi_endproc
diff --git a/test/CodeGen/ARM/emit-big-cst.ll b/test/CodeGen/ARM/emit-big-cst.ll
index 01d789c492fe..7453e8caa946 100644
--- a/test/CodeGen/ARM/emit-big-cst.ll
+++ b/test/CodeGen/ARM/emit-big-cst.ll
@@ -11,7 +11,7 @@
 
 define void @accessBig(i64* %storage) {
   %addr = bitcast i64* %storage to i82*
-  %bigLoadedCst = load volatile i82* @bigCst
+  %bigLoadedCst = load volatile i82, i82* @bigCst
   %tmp = add i82 %bigLoadedCst, 1
   store i82 %tmp, i82* %addr
   ret void
diff --git a/test/CodeGen/ARM/extload-knownzero.ll b/test/CodeGen/ARM/extload-knownzero.ll
index f55b95104b86..da340f7a9431 100644
--- a/test/CodeGen/ARM/extload-knownzero.ll
+++ b/test/CodeGen/ARM/extload-knownzero.ll
@@ -8,7 +8,7 @@ entry:
   br i1 %tmp1, label %bb1, label %bb2
 bb1:
 ; CHECK: ldrh
-  %tmp2 = load i16* %ptr, align 2
+  %tmp2 = load i16, i16* %ptr, align 2
   br label %bb2
 bb2:
 ; CHECK-NOT: uxth
diff --git a/test/CodeGen/ARM/extloadi1.ll b/test/CodeGen/ARM/extloadi1.ll
index 2504c6c61e3e..a67859d60d19 100644
--- a/test/CodeGen/ARM/extloadi1.ll
+++ b/test/CodeGen/ARM/extloadi1.ll
@@ -4,7 +4,7 @@
 
 define void @__mf_sigusr1_respond() {
 entry:
-        %tmp8.b = load i1* @handler_installed.6144.b            ; <i1> [#uses=1]
+        %tmp8.b = load i1, i1* @handler_installed.6144.b            ; <i1> [#uses=1]
         br i1 false, label %cond_true7, label %cond_next
 
 cond_next:              ; preds = %entry
diff --git a/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll b/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll
index 05a6bab99dbf..d759d2d52c36 100644
--- a/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll
+++ b/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
 
 %struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] }
 %struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] }
@@ -14,10 +14,10 @@ entry:
 ; ARM: t1
 ; THUMB: t1
   %addr = alloca i32*, align 4
-  store i32* getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]]* @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), i32** %addr, align 4
+  store i32* getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]], [2 x [2 x [2 x [2 x [2 x i32]]]]]* @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), i32** %addr, align 4
 ; ARM: add r0, r0, #124
 ; THUMB: adds r0, #124
-  %0 = load i32** %addr, align 4
+  %0 = load i32*, i32** %addr, align 4
   ret i32* %0
 }
 
@@ -26,11 +26,11 @@ entry:
 ; ARM: t2
 ; THUMB: t2
   %addr = alloca i32*, align 4
-  store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4
+  store i32* getelementptr inbounds ([3 x [3 x %struct.A]], [3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4
 ; ARM: movw [[R:r[0-9]+]], #1148
 ; ARM: add r0, r{{[0-9]+}}, [[R]]
 ; THUMB: addw r0, r0, #1148
-  %0 = load i32** %addr, align 4
+  %0 = load i32*, i32** %addr, align 4
   ret i32* %0
 }
 
@@ -39,10 +39,10 @@ entry:
 ; ARM: t3
 ; THUMB: t3
   %addr = alloca i32*, align 4
-  store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), i32** %addr, align 4
+  store i32* getelementptr inbounds ([3 x [3 x %struct.A]], [3 x [3 x %struct.A]]* @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), i32** %addr, align 4
 ; ARM: add r0, r0, #140
 ; THUMB: adds r0, #140
-  %0 = load i32** %addr, align 4
+  %0 = load i32*, i32** %addr, align 4
   ret i32* %0
 }
 
@@ -51,7 +51,7 @@ entry:
 ; ARM: t4
 ; THUMB: t4
   %addr = alloca i32*, align 4
-  store i32* getelementptr inbounds ([2 x [2 x [2 x %struct.B]]]* @B, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 3, i32 1, i32 2, i32 1), i32** %addr, align 4
+  store i32* getelementptr inbounds ([2 x [2 x [2 x %struct.B]]], [2 x [2 x [2 x %struct.B]]]* @B, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 3, i32 1, i32 2, i32 1), i32** %addr, align 4
 ; ARM-NOT: movw r{{[0-9]}}, #1060
 ; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #4
 ; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #132
@@ -61,6 +61,6 @@ entry:
 ; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #4
 ; ARM: movw r{{[0-9]}}, #1284
 ; THUMB: addw r{{[0-9]}}, r{{[0-9]}}, #1284
-  %0 = load i32** %addr, align 4
+  %0 = load i32*, i32** %addr, align 4
   ret i32* %0
 }
diff --git a/test/CodeGen/ARM/fast-isel-align.ll b/test/CodeGen/ARM/fast-isel-align.ll
index 9c9a18858289..39085db95316 100644
--- a/test/CodeGen/ARM/fast-isel-align.ll
+++ b/test/CodeGen/ARM/fast-isel-align.ll
@@ -1,20 +1,20 @@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
 ; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
 ; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
 
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
 ; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
 ; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
 
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
 
-; RUN: llc < %s -O0  -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
-; RUN: llc < %s -O0  -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
-; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0  -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
+; RUN: llc < %s -O0  -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
+; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
 ; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
 ; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
 
@@ -34,8 +34,8 @@ entry:
 ; THUMB: str r1, [r0]
 
   %add = fadd float %x, %y
-  %0 = load %struct.anon** @a, align 4
-  %x1 = getelementptr inbounds %struct.anon* %0, i32 0, i32 0
+  %0 = load %struct.anon*, %struct.anon** @a, align 4
+  %x1 = getelementptr inbounds %struct.anon, %struct.anon* %0, i32 0, i32 0
   store float %add, float* %x1, align 1
   ret void
 }
@@ -51,7 +51,7 @@ entry:
 ; ARM: @word_aligned_f64_store
 ; THUMB: @word_aligned_f64_store
   %add = fadd double %a, %b
-  store double %add, double* getelementptr inbounds (%struct.anon.0* @foo_unpacked, i32 0, i32 0), align 4
+  store double %add, double* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @foo_unpacked, i32 0, i32 0), align 4
 ; ARM: vstr d16, [r0]
 ; THUMB: vstr d16, [r0]
   ret void
@@ -66,9 +66,9 @@ entry:
 ; THUMB: @unaligned_f32_load
   %0 = alloca %class.TAlignTest*, align 4
   store %class.TAlignTest* %this, %class.TAlignTest** %0, align 4
-  %1 = load %class.TAlignTest** %0
-  %2 = getelementptr inbounds %class.TAlignTest* %1, i32 0, i32 1
-  %3 = load float* %2, align 1
+  %1 = load %class.TAlignTest*, %class.TAlignTest** %0
+  %2 = getelementptr inbounds %class.TAlignTest, %class.TAlignTest* %1, i32 0, i32 1
+  %3 = load float, float* %2, align 1
   %4 = fcmp une float %3, 0.000000e+00
 ; ARM: ldr r[[R:[0-9]+]], [r0, #2]
 ; ARM: vmov s0, r[[R]]
@@ -103,7 +103,7 @@ entry:
 ; THUMB-STRICT-ALIGN: ldrb
 ; THUMB-STRICT-ALIGN: ldrb
 
-  %0 = load i16* %x, align 1
+  %0 = load i16, i16* %x, align 1
   ret i16 %0
 }
 
@@ -139,6 +139,6 @@ entry:
 ; THUMB-STRICT-ALIGN: ldrb
 ; THUMB-STRICT-ALIGN: ldrb
 
-  %0 = load i32* %x, align 1
+  %0 = load i32, i32* %x, align 1
   ret i32 %0
 }
diff --git a/test/CodeGen/ARM/fast-isel-binary.ll b/test/CodeGen/ARM/fast-isel-binary.ll
index e1a2a4f33835..3211fd6f2422 100644
--- a/test/CodeGen/ARM/fast-isel-binary.ll
+++ b/test/CodeGen/ARM/fast-isel-binary.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 ; Test add with non-legal types
 
diff --git a/test/CodeGen/ARM/fast-isel-br-const.ll b/test/CodeGen/ARM/fast-isel-br-const.ll
index 2e28b08fc8d6..988664b86b80 100644
--- a/test/CodeGen/ARM/fast-isel-br-const.ll
+++ b/test/CodeGen/ARM/fast-isel-br-const.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp {
 entry:
diff --git a/test/CodeGen/ARM/fast-isel-br-phi.ll b/test/CodeGen/ARM/fast-isel-br-phi.ll
index 3b9d4652b755..fb0f0153898b 100644
--- a/test/CodeGen/ARM/fast-isel-br-phi.ll
+++ b/test/CodeGen/ARM/fast-isel-br-phi.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios
 
 ; This test ensures HandlePHINodesInSuccessorBlocks() is able to promote basic
 ; non-legal integer types (i.e., i1, i8, i16).
diff --git a/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll b/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll
index da829e929ef0..2c660179aa3c 100644
--- a/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll
+++ b/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 ; Fast-isel can't handle non-double multi-reg retvals.
 ; This test just check to make sure we don't hit the assert in FinishCall.
diff --git a/test/CodeGen/ARM/fast-isel-call.ll b/test/CodeGen/ARM/fast-isel-call.ll
index 74b31bd9e67f..bd170f30d979 100644
--- a/test/CodeGen/ARM/fast-isel-call.ll
+++ b/test/CodeGen/ARM/fast-isel-call.ll
@@ -1,12 +1,12 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP
 
 ; Note that some of these tests assume that relocations are either
 ; movw/movt or constant pool loads. Different platforms will select
@@ -157,7 +157,7 @@ define void @foo3() uwtable {
 ; THUMB: blx     r1
   %fptr = alloca i32 (i32)*, align 8
   store i32 (i32)* @bar0, i32 (i32)** %fptr, align 8
-  %1 = load i32 (i32)** %fptr, align 8
+  %1 = load i32 (i32)*, i32 (i32)** %fptr, align 8
   %call = call i32 %1(i32 0)
   ret void
 }
diff --git a/test/CodeGen/ARM/fast-isel-cmp-imm.ll b/test/CodeGen/ARM/fast-isel-cmp-imm.ll
index 55baf488a425..a9d7e4580638 100644
--- a/test/CodeGen/ARM/fast-isel-cmp-imm.ll
+++ b/test/CodeGen/ARM/fast-isel-cmp-imm.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
 
 define void @t1a(float %a) uwtable ssp {
 entry:
diff --git a/test/CodeGen/ARM/fast-isel-conversion.ll b/test/CodeGen/ARM/fast-isel-conversion.ll
index 5983493a818b..46b5e78fb662 100644
--- a/test/CodeGen/ARM/fast-isel-conversion.ll
+++ b/test/CodeGen/ARM/fast-isel-conversion.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 ; Test sitofp
 
diff --git a/test/CodeGen/ARM/fast-isel-crash.ll b/test/CodeGen/ARM/fast-isel-crash.ll
index ec9cf8d95019..885ca69834d3 100644
--- a/test/CodeGen/ARM/fast-isel-crash.ll
+++ b/test/CodeGen/ARM/fast-isel-crash.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-darwin
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-linux-gnueabi
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=thumbv7-apple-darwin
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=thumbv7-linux-gnueabi
 
 %union.anon = type { <16 x i32> }
 
diff --git a/test/CodeGen/ARM/fast-isel-deadcode.ll b/test/CodeGen/ARM/fast-isel-deadcode.ll
index c3eed30692b8..e584c54b48a2 100644
--- a/test/CodeGen/ARM/fast-isel-deadcode.ll
+++ b/test/CodeGen/ARM/fast-isel-deadcode.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 ; Target-specific selector can't properly handle the double because it isn't
 ; being passed via a register, so the materialized arguments become dead code.
diff --git a/test/CodeGen/ARM/fast-isel-ext.ll b/test/CodeGen/ARM/fast-isel-ext.ll
index de0dd1917eb7..b792f7a90738 100644
--- a/test/CodeGen/ARM/fast-isel-ext.ll
+++ b/test/CodeGen/ARM/fast-isel-ext.ll
@@ -1,10 +1,10 @@
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v7
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
+; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
+; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v7
+; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv4t-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6
+; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv4t-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6
+; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv5-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6
+; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv5-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6
+; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
 
 ; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports
 ; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always
diff --git a/test/CodeGen/ARM/fast-isel-fold.ll b/test/CodeGen/ARM/fast-isel-fold.ll
index e8ed8cbf34e9..37e93c0a7018 100644
--- a/test/CodeGen/ARM/fast-isel-fold.ll
+++ b/test/CodeGen/ARM/fast-isel-fold.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
 
 @a = global i8 1, align 1
 @b = global i16 2, align 2
@@ -14,7 +14,7 @@ define void @t1() nounwind uwtable ssp {
 ; THUMB: ldrb
 ; THUMB-NOT: uxtb
 ; THUMB-NOT: and{{.*}}, #255
-  %1 = load i8* @a, align 1
+  %1 = load i8, i8* @a, align 1
   call void @foo1(i8 zeroext %1)
   ret void
 }
@@ -26,7 +26,7 @@ define void @t2() nounwind uwtable ssp {
 ; THUMB: t2
 ; THUMB: ldrh
 ; THUMB-NOT: uxth
-  %1 = load i16* @b, align 2
+  %1 = load i16, i16* @b, align 2
   call void @foo2(i16 zeroext %1)
   ret void
 }
@@ -43,7 +43,7 @@ define i32 @t3() nounwind uwtable ssp {
 ; THUMB: ldrb
 ; THUMB-NOT: uxtb
 ; THUMB-NOT: and{{.*}}, #255
-  %1 = load i8* @a, align 1
+  %1 = load i8, i8* @a, align 1
   %2 = zext i8 %1 to i32
   ret i32 %2
 }
@@ -55,7 +55,7 @@ define i32 @t4() nounwind uwtable ssp {
 ; THUMB: t4
 ; THUMB: ldrh
 ; THUMB-NOT: uxth
-  %1 = load i16* @b, align 2
+  %1 = load i16, i16* @b, align 2
   %2 = zext i16 %1 to i32
   ret i32 %2
 }
@@ -67,7 +67,7 @@ define i32 @t5() nounwind uwtable ssp {
 ; THUMB: t5
 ; THUMB: ldrsh
 ; THUMB-NOT: sxth
-  %1 = load i16* @b, align 2
+  %1 = load i16, i16* @b, align 2
   %2 = sext i16 %1 to i32
   ret i32 %2
 }
@@ -79,7 +79,7 @@ define i32 @t6() nounwind uwtable ssp {
 ; THUMB: t6
 ; THUMB: ldrsb
 ; THUMB-NOT: sxtb
-  %1 = load i8* @a, align 2
+  %1 = load i8, i8* @a, align 2
   %2 = sext i8 %1 to i32
   ret i32 %2
 }
diff --git a/test/CodeGen/ARM/fast-isel-frameaddr.ll b/test/CodeGen/ARM/fast-isel-frameaddr.ll
index 93cdbbbbd86e..75d582f4ee3a 100644
--- a/test/CodeGen/ARM/fast-isel-frameaddr.ll
+++ b/test/CodeGen/ARM/fast-isel-frameaddr.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=DARWIN-ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=LINUX-ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=DARWIN-THUMB2
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-linux-gnueabi | FileCheck %s --check-prefix=LINUX-THUMB2
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=DARWIN-ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=LINUX-ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=DARWIN-THUMB2
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=thumbv7-linux-gnueabi | FileCheck %s --check-prefix=LINUX-THUMB2
 
 define i8* @frameaddr_index0() nounwind {
 entry:
diff --git a/test/CodeGen/ARM/fast-isel-icmp.ll b/test/CodeGen/ARM/fast-isel-icmp.ll
index 85f449e3d71d..bd7c2d096a8c 100644
--- a/test/CodeGen/ARM/fast-isel-icmp.ll
+++ b/test/CodeGen/ARM/fast-isel-icmp.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
 
 define i32 @icmp_i16_signed(i16 %a, i16 %b) nounwind {
 entry:
diff --git a/test/CodeGen/ARM/fast-isel-indirectbr.ll b/test/CodeGen/ARM/fast-isel-indirectbr.ll
index 2456ef442040..91648d36a694 100644
--- a/test/CodeGen/ARM/fast-isel-indirectbr.ll
+++ b/test/CodeGen/ARM/fast-isel-indirectbr.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 define void @t1(i8* %x) {
 entry:
diff --git a/test/CodeGen/ARM/fast-isel-intrinsic.ll b/test/CodeGen/ARM/fast-isel-intrinsic.ll
index b09931dc4e2f..6b434b74ca79 100644
--- a/test/CodeGen/ARM/fast-isel-intrinsic.ll
+++ b/test/CodeGen/ARM/fast-isel-intrinsic.ll
@@ -1,9 +1,9 @@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-LONG
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-LONG
 
 ; Note that some of these tests assume that relocations are either
 ; movw/movt or constant pool loads. Different platforms will select
@@ -39,7 +39,7 @@ define void @t1() nounwind ssp {
 ; THUMB-LONG: movt r3, :upper16:L_memset$non_lazy_ptr
 ; THUMB-LONG: ldr r3, [r3]
 ; THUMB-LONG: blx r3
-  call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @message1, i32 0, i32 5), i8 64, i32 10, i32 4, i1 false)
+  call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @message1, i32 0, i32 5), i8 64, i32 10, i32 4, i1 false)
   ret void
 }
 
@@ -78,7 +78,7 @@ define void @t2() nounwind ssp {
 ; THUMB-LONG: movt r3, :upper16:L_memcpy$non_lazy_ptr
 ; THUMB-LONG: ldr r3, [r3]
 ; THUMB-LONG: blx r3
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 17, i32 4, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 17, i32 4, i1 false)
   ret void
 }
 
@@ -115,7 +115,7 @@ define void @t3() nounwind ssp {
 ; THUMB-LONG: movt r3, :upper16:L_memmove$non_lazy_ptr
 ; THUMB-LONG: ldr r3, [r3]
 ; THUMB-LONG: blx r3
-  call void @llvm.memmove.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 1, i1 false)
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i32 1, i1 false)
   ret void
 }
 
@@ -142,7 +142,7 @@ define void @t4() nounwind ssp {
 ; THUMB: ldrh r1, [r0, #24]
 ; THUMB: strh r1, [r0, #12]
 ; THUMB: bx lr
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 4, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i32 4, i1 false)
   ret void
 }
 
@@ -179,7 +179,7 @@ define void @t5() nounwind ssp {
 ; THUMB: ldrh r1, [r0, #24]
 ; THUMB: strh r1, [r0, #12]
 ; THUMB: bx lr
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 2, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i32 2, i1 false)
   ret void
 }
 
@@ -234,14 +234,14 @@ define void @t6() nounwind ssp {
 ; THUMB: ldrb r1, [r0, #25]
 ; THUMB: strb r1, [r0, #13]
 ; THUMB: bx lr
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i32 1, i1 false)
   ret void
 }
 
 ; rdar://13202135
 define void @t7() nounwind ssp {
 ; Just make sure this doesn't assert when we have an odd length and an alignment of 2.
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 3, i32 2, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 3, i32 2, i1 false)
   ret void
 }
 
diff --git a/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll b/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll
index cf294bcfbece..cce914b094f7 100644
--- a/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll
+++ b/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll
@@ -1,10 +1,10 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM
 
 define i32 @t1(i32* nocapture %ptr) nounwind readonly {
 entry:
 ; ARM: t1
-  %add.ptr = getelementptr inbounds i32* %ptr, i32 1
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 1
+  %0 = load i32, i32* %add.ptr, align 4
 ; ARM: ldr r{{[0-9]}}, [r0, #4]
   ret i32 %0
 }
@@ -12,8 +12,8 @@ entry:
 define i32 @t2(i32* nocapture %ptr) nounwind readonly {
 entry:
 ; ARM: t2
-  %add.ptr = getelementptr inbounds i32* %ptr, i32 63
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 63
+  %0 = load i32, i32* %add.ptr, align 4
 ; ARM: ldr.w r{{[0-9]}}, [r0, #252]
   ret i32 %0
 }
@@ -21,8 +21,8 @@ entry:
 define zeroext i16 @t3(i16* nocapture %ptr) nounwind readonly {
 entry:
 ; ARM: t3
-  %add.ptr = getelementptr inbounds i16* %ptr, i16 1
-  %0 = load i16* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i16, i16* %ptr, i16 1
+  %0 = load i16, i16* %add.ptr, align 4
 ; ARM: ldrh r{{[0-9]}}, [r0, #2]
   ret i16 %0
 }
@@ -30,8 +30,8 @@ entry:
 define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly {
 entry:
 ; ARM: t4
-  %add.ptr = getelementptr inbounds i16* %ptr, i16 63
-  %0 = load i16* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i16, i16* %ptr, i16 63
+  %0 = load i16, i16* %add.ptr, align 4
 ; ARM: ldrh.w r{{[0-9]}}, [r0, #126]
   ret i16 %0
 }
@@ -39,8 +39,8 @@ entry:
 define zeroext i8 @t5(i8* nocapture %ptr) nounwind readonly {
 entry:
 ; ARM: t5
-  %add.ptr = getelementptr inbounds i8* %ptr, i8 1
-  %0 = load i8* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i8, i8* %ptr, i8 1
+  %0 = load i8, i8* %add.ptr, align 4
 ; ARM: ldrb r{{[0-9]}}, [r0, #1]
   ret i8 %0
 }
@@ -48,8 +48,8 @@ entry:
 define zeroext i8 @t6(i8* nocapture %ptr) nounwind readonly {
 entry:
 ; ARM: t6
-  %add.ptr = getelementptr inbounds i8* %ptr, i8 63
-  %0 = load i8* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i8, i8* %ptr, i8 63
+  %0 = load i8, i8* %add.ptr, align 4
 ; ARM: ldrb.w r{{[0-9]}}, [r0, #63]
   ret i8 %0
 }
diff --git a/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll b/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
index d9c9cc459c7e..f24100b36db9 100644
--- a/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
+++ b/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
@@ -1,10 +1,10 @@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
 
 define i32 @t1(i32* nocapture %ptr) nounwind readonly {
 entry:
 ; THUMB: t1
-  %add.ptr = getelementptr inbounds i32* %ptr, i32 -1
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -1
+  %0 = load i32, i32* %add.ptr, align 4
 ; THUMB: ldr r{{[0-9]}}, [r0, #-4]
   ret i32 %0
 }
@@ -12,8 +12,8 @@ entry:
 define i32 @t2(i32* nocapture %ptr) nounwind readonly {
 entry:
 ; THUMB: t2
-  %add.ptr = getelementptr inbounds i32* %ptr, i32 -63
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -63
+  %0 = load i32, i32* %add.ptr, align 4
 ; THUMB: ldr r{{[0-9]}}, [r0, #-252]
   ret i32 %0
 }
@@ -21,8 +21,8 @@ entry:
 define i32 @t3(i32* nocapture %ptr) nounwind readonly {
 entry:
 ; THUMB: t3
-  %add.ptr = getelementptr inbounds i32* %ptr, i32 -64
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -64
+  %0 = load i32, i32* %add.ptr, align 4
 ; THUMB: ldr r{{[0-9]}}, [r0]
   ret i32 %0
 }
@@ -30,8 +30,8 @@ entry:
 define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly {
 entry:
 ; THUMB: t4
-  %add.ptr = getelementptr inbounds i16* %ptr, i32 -1
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -1
+  %0 = load i16, i16* %add.ptr, align 2
 ; THUMB: ldrh r{{[0-9]}}, [r0, #-2]
   ret i16 %0
 }
@@ -39,8 +39,8 @@ entry:
 define zeroext i16 @t5(i16* nocapture %ptr) nounwind readonly {
 entry:
 ; THUMB: t5
-  %add.ptr = getelementptr inbounds i16* %ptr, i32 -127
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -127
+  %0 = load i16, i16* %add.ptr, align 2
 ; THUMB: ldrh r{{[0-9]}}, [r0, #-254]
   ret i16 %0
 }
@@ -48,8 +48,8 @@ entry:
 define zeroext i16 @t6(i16* nocapture %ptr) nounwind readonly {
 entry:
 ; THUMB: t6
-  %add.ptr = getelementptr inbounds i16* %ptr, i32 -128
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -128
+  %0 = load i16, i16* %add.ptr, align 2
 ; THUMB: ldrh r{{[0-9]}}, [r0]
   ret i16 %0
 }
@@ -57,8 +57,8 @@ entry:
 define zeroext i8 @t7(i8* nocapture %ptr) nounwind readonly {
 entry:
 ; THUMB: t7
-  %add.ptr = getelementptr inbounds i8* %ptr, i32 -1
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -1
+  %0 = load i8, i8* %add.ptr, align 1
 ; THUMB: ldrb r{{[0-9]}}, [r0, #-1]
   ret i8 %0
 }
@@ -66,8 +66,8 @@ entry:
 define zeroext i8 @t8(i8* nocapture %ptr) nounwind readonly {
 entry:
 ; THUMB: t8
-  %add.ptr = getelementptr inbounds i8* %ptr, i32 -255
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -255
+  %0 = load i8, i8* %add.ptr, align 1
 ; THUMB: ldrb r{{[0-9]}}, [r0, #-255]
   ret i8 %0
 }
@@ -75,8 +75,8 @@ entry:
 define zeroext i8 @t9(i8* nocapture %ptr) nounwind readonly {
 entry:
 ; THUMB: t9
-  %add.ptr = getelementptr inbounds i8* %ptr, i32 -256
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -256
+  %0 = load i8, i8* %add.ptr, align 1
 ; THUMB: ldrb r{{[0-9]}}, [r0]
   ret i8 %0
 }
@@ -84,7 +84,7 @@ entry:
 define void @t10(i32* nocapture %ptr) nounwind {
 entry:
 ; THUMB: t10
-  %add.ptr = getelementptr inbounds i32* %ptr, i32 -1
+  %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -1
   store i32 0, i32* %add.ptr, align 4
 ; THUMB: str r{{[0-9]}}, [r0, #-4]
   ret void
@@ -93,7 +93,7 @@ entry:
 define void @t11(i32* nocapture %ptr) nounwind {
 entry:
 ; THUMB: t11
-  %add.ptr = getelementptr inbounds i32* %ptr, i32 -63
+  %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -63
   store i32 0, i32* %add.ptr, align 4
 ; THUMB: str r{{[0-9]}}, [r0, #-252]
   ret void
@@ -102,7 +102,7 @@ entry:
 define void @t12(i32* nocapture %ptr) nounwind {
 entry:
 ; THUMB: t12
-  %add.ptr = getelementptr inbounds i32* %ptr, i32 -64
+  %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -64
   store i32 0, i32* %add.ptr, align 4
 ; THUMB: str r{{[0-9]}}, [r0]
   ret void
@@ -111,7 +111,7 @@ entry:
 define void @t13(i16* nocapture %ptr) nounwind {
 entry:
 ; THUMB: t13
-  %add.ptr = getelementptr inbounds i16* %ptr, i32 -1
+  %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -1
   store i16 0, i16* %add.ptr, align 2
 ; THUMB: strh r{{[0-9]}}, [r0, #-2]
   ret void
@@ -120,7 +120,7 @@ entry:
 define void @t14(i16* nocapture %ptr) nounwind {
 entry:
 ; THUMB: t14
-  %add.ptr = getelementptr inbounds i16* %ptr, i32 -127
+  %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -127
   store i16 0, i16* %add.ptr, align 2
 ; THUMB: strh r{{[0-9]}}, [r0, #-254]
   ret void
@@ -129,7 +129,7 @@ entry:
 define void @t15(i16* nocapture %ptr) nounwind {
 entry:
 ; THUMB: t15
-  %add.ptr = getelementptr inbounds i16* %ptr, i32 -128
+  %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -128
   store i16 0, i16* %add.ptr, align 2
 ; THUMB: strh r{{[0-9]}}, [r0]
   ret void
@@ -138,7 +138,7 @@ entry:
 define void @t16(i8* nocapture %ptr) nounwind {
 entry:
 ; THUMB: t16
-  %add.ptr = getelementptr inbounds i8* %ptr, i32 -1
+  %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -1
   store i8 0, i8* %add.ptr, align 1
 ; THUMB: strb r{{[0-9]}}, [r0, #-1]
   ret void
@@ -147,7 +147,7 @@ entry:
 define void @t17(i8* nocapture %ptr) nounwind {
 entry:
 ; THUMB: t17
-  %add.ptr = getelementptr inbounds i8* %ptr, i32 -255
+  %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -255
   store i8 0, i8* %add.ptr, align 1
 ; THUMB: strb r{{[0-9]}}, [r0, #-255]
   ret void
@@ -156,7 +156,7 @@ entry:
 define void @t18(i8* nocapture %ptr) nounwind {
 entry:
 ; THUMB: t18
-  %add.ptr = getelementptr inbounds i8* %ptr, i32 -256
+  %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -256
   store i8 0, i8* %add.ptr, align 1
 ; THUMB: strb r{{[0-9]}}, [r0]
   ret void
diff --git a/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll b/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
index c05ea398d72e..ca512970c9cf 100644
--- a/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
+++ b/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
@@ -1,12 +1,12 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; rdar://10418009
 
 define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t1
-  %add.ptr = getelementptr inbounds i16* %a, i64 -8
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %a, i64 -8
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: ldrh r0, [r0, #-16]
   ret i16 %0
 }
@@ -14,8 +14,8 @@ entry:
 define zeroext i16 @t2(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t2
-  %add.ptr = getelementptr inbounds i16* %a, i64 -16
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %a, i64 -16
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: ldrh r0, [r0, #-32]
   ret i16 %0
 }
@@ -23,8 +23,8 @@ entry:
 define zeroext i16 @t3(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t3
-  %add.ptr = getelementptr inbounds i16* %a, i64 -127
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %a, i64 -127
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: ldrh r0, [r0, #-254]
   ret i16 %0
 }
@@ -32,8 +32,8 @@ entry:
 define zeroext i16 @t4(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t4
-  %add.ptr = getelementptr inbounds i16* %a, i64 -128
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %a, i64 -128
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: mvn r{{[1-9]}}, #255
 ; ARM: add r0, r0, r{{[1-9]}}
 ; ARM: ldrh r0, [r0]
@@ -43,8 +43,8 @@ entry:
 define zeroext i16 @t5(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t5
-  %add.ptr = getelementptr inbounds i16* %a, i64 8
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %a, i64 8
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: ldrh r0, [r0, #16]
   ret i16 %0
 }
@@ -52,8 +52,8 @@ entry:
 define zeroext i16 @t6(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t6
-  %add.ptr = getelementptr inbounds i16* %a, i64 16
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %a, i64 16
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: ldrh r0, [r0, #32]
   ret i16 %0
 }
@@ -61,8 +61,8 @@ entry:
 define zeroext i16 @t7(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t7
-  %add.ptr = getelementptr inbounds i16* %a, i64 127
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %a, i64 127
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: ldrh r0, [r0, #254]
   ret i16 %0
 }
@@ -70,8 +70,8 @@ entry:
 define zeroext i16 @t8(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t8
-  %add.ptr = getelementptr inbounds i16* %a, i64 128
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %a, i64 128
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: add r0, r0, #256
 ; ARM: ldrh r0, [r0]
   ret i16 %0
@@ -80,7 +80,7 @@ entry:
 define void @t9(i16* nocapture %a) nounwind uwtable ssp {
 entry:
 ; ARM: t9
-  %add.ptr = getelementptr inbounds i16* %a, i64 -8
+  %add.ptr = getelementptr inbounds i16, i16* %a, i64 -8
   store i16 0, i16* %add.ptr, align 2
 ; ARM: strh	r1, [r0, #-16]
   ret void
@@ -91,7 +91,7 @@ entry:
 define void @t10(i16* nocapture %a) nounwind uwtable ssp {
 entry:
 ; ARM: t10
-  %add.ptr = getelementptr inbounds i16* %a, i64 -128
+  %add.ptr = getelementptr inbounds i16, i16* %a, i64 -128
   store i16 0, i16* %add.ptr, align 2
 ; ARM: mvn r{{[1-9]}}, #255
 ; ARM: add r0, r0, r{{[1-9]}}
@@ -102,7 +102,7 @@ entry:
 define void @t11(i16* nocapture %a) nounwind uwtable ssp {
 entry:
 ; ARM: t11
-  %add.ptr = getelementptr inbounds i16* %a, i64 8
+  %add.ptr = getelementptr inbounds i16, i16* %a, i64 8
   store i16 0, i16* %add.ptr, align 2
 ; ARM: strh r{{[1-9]}}, [r0, #16]
   ret void
@@ -113,7 +113,7 @@ entry:
 define void @t12(i16* nocapture %a) nounwind uwtable ssp {
 entry:
 ; ARM: t12
-  %add.ptr = getelementptr inbounds i16* %a, i64 128
+  %add.ptr = getelementptr inbounds i16, i16* %a, i64 128
   store i16 0, i16* %add.ptr, align 2
 ; ARM: add r0, r0, #256
 ; ARM: strh r{{[1-9]}}, [r0]
@@ -123,8 +123,8 @@ entry:
 define signext i8 @t13(i8* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t13
-  %add.ptr = getelementptr inbounds i8* %a, i64 -8
-  %0 = load i8* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i8, i8* %a, i64 -8
+  %0 = load i8, i8* %add.ptr, align 2
 ; ARM: ldrsb r0, [r0, #-8]
   ret i8 %0
 }
@@ -132,8 +132,8 @@ entry:
 define signext i8 @t14(i8* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t14
-  %add.ptr = getelementptr inbounds i8* %a, i64 -255
-  %0 = load i8* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i8, i8* %a, i64 -255
+  %0 = load i8, i8* %add.ptr, align 2
 ; ARM: ldrsb r0, [r0, #-255]
   ret i8 %0
 }
@@ -141,8 +141,8 @@ entry:
 define signext i8 @t15(i8* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t15
-  %add.ptr = getelementptr inbounds i8* %a, i64 -256
-  %0 = load i8* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i8, i8* %a, i64 -256
+  %0 = load i8, i8* %add.ptr, align 2
 ; ARM: mvn r{{[1-9]}}, #255
 ; ARM: add r0, r0, r{{[1-9]}}
 ; ARM: ldrsb r0, [r0]
diff --git a/test/CodeGen/ARM/fast-isel-load-store-verify.ll b/test/CodeGen/ARM/fast-isel-load-store-verify.ll
index 710d88b3158c..acf10c8b719e 100644
--- a/test/CodeGen/ARM/fast-isel-load-store-verify.ll
+++ b/test/CodeGen/ARM/fast-isel-load-store-verify.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ALL
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ALL
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ALL
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ALL
 
 ; FIXME Add tests for thumbv7, they currently fail MI verification because
 ;       of a mismatch in register classes in uses.
@@ -17,7 +17,7 @@ define i8 @t1() nounwind uwtable ssp {
 ; ALL: @t1
 ; ALL: ldrb
 ; ALL: add
-  %1 = load i8* @a, align 1
+  %1 = load i8, i8* @a, align 1
   %2 = add nsw i8 %1, 1
   ret i8 %2
 }
@@ -26,7 +26,7 @@ define i16 @t2() nounwind uwtable ssp {
 ; ALL: @t2
 ; ALL: ldrh
 ; ALL: add
-  %1 = load i16* @b, align 2
+  %1 = load i16, i16* @b, align 2
   %2 = add nsw i16 %1, 1
   ret i16 %2
 }
@@ -35,7 +35,7 @@ define i32 @t3() nounwind uwtable ssp {
 ; ALL: @t3
 ; ALL: ldr
 ; ALL: add
-  %1 = load i32* @c, align 4
+  %1 = load i32, i32* @c, align 4
   %2 = add nsw i32 %1, 1
   ret i32 %2
 }
diff --git a/test/CodeGen/ARM/fast-isel-mvn.ll b/test/CodeGen/ARM/fast-isel-mvn.ll
index 886f2daa21dd..89b7c05158cd 100644
--- a/test/CodeGen/ARM/fast-isel-mvn.ll
+++ b/test/CodeGen/ARM/fast-isel-mvn.ll
@@ -1,8 +1,8 @@
-; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-apple-ios     < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
-; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
-; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=thumbv7-apple-ios   < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
-; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -arm-use-movt=true  -mtriple=thumbv7-apple-ios   < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB
-; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -arm-use-movt=true  -mtriple=armv7-apple-ios     < %s | FileCheck %s --check-prefix=MOVT
+; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-apple-ios     < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
+; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
+; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=thumbv7-apple-ios   < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
+; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=true  -mtriple=thumbv7-apple-ios   < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB
+; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=true  -mtriple=armv7-apple-ios     < %s | FileCheck %s --check-prefix=MOVT
 ; rdar://10412592
 
 define void @t1() nounwind {
diff --git a/test/CodeGen/ARM/fast-isel-pic.ll b/test/CodeGen/ARM/fast-isel-pic.ll
index 838c103e7c09..70e15daaca62 100644
--- a/test/CodeGen/ARM/fast-isel-pic.ll
+++ b/test/CodeGen/ARM/fast-isel-pic.ll
@@ -1,8 +1,8 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF
 
 @g = global i32 0, align 4
 
@@ -29,7 +29,7 @@ entry:
 ; ARMv7-ELF-NEXT: add r[[reg2]], pc
 ; ARMv7-ELF: ldr r[[reg3:[0-9]+]],
 ; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
-  %tmp = load i32* @g
+  %tmp = load i32, i32* @g
   ret i32 %tmp
 }
 
@@ -60,6 +60,6 @@ entry:
 ; ARMv7-ELF-NEXT: add r[[reg5]], pc
 ; ARMv7-ELF: ldr r[[reg6:[0-9]+]],
 ; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]]
-  %tmp = load i32* @i
+  %tmp = load i32, i32* @i
   ret i32 %tmp
 }
diff --git a/test/CodeGen/ARM/fast-isel-pred.ll b/test/CodeGen/ARM/fast-isel-pred.ll
index 48f93225b6b8..ae8b67d7157b 100644
--- a/test/CodeGen/ARM/fast-isel-pred.ll
+++ b/test/CodeGen/ARM/fast-isel-pred.ll
@@ -7,9 +7,9 @@ entry:
   %X = alloca <4 x i32>, align 16
   %Y = alloca <4 x float>, align 16
   store i32 0, i32* %retval
-  %tmp = load <4 x i32>* %X, align 16
+  %tmp = load <4 x i32>, <4 x i32>* %X, align 16
   call void @__aa(<4 x i32> %tmp, i8* null, i32 3, <4 x float>* %Y)
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -24,15 +24,15 @@ entry:
   store i8* %p, i8** %p.addr, align 4
   store i32 %offset, i32* %offset.addr, align 4
   store <4 x float>* %constants, <4 x float>** %constants.addr, align 4
-  %tmp = load <4 x i32>* %v.addr, align 16
+  %tmp = load <4 x i32>, <4 x i32>* %v.addr, align 16
   store <4 x i32> %tmp, <4 x i32>* %__a.addr.i, align 16
-  %tmp.i = load <4 x i32>* %__a.addr.i, align 16
+  %tmp.i = load <4 x i32>, <4 x i32>* %__a.addr.i, align 16
   %0 = bitcast <4 x i32> %tmp.i to <16 x i8>
   %1 = bitcast <16 x i8> %0 to <4 x i32>
   %vcvt.i = sitofp <4 x i32> %1 to <4 x float>
-  %tmp1 = load i8** %p.addr, align 4
-  %tmp2 = load i32* %offset.addr, align 4
-  %tmp3 = load <4 x float>** %constants.addr, align 4
+  %tmp1 = load i8*, i8** %p.addr, align 4
+  %tmp2 = load i32, i32* %offset.addr, align 4
+  %tmp3 = load <4 x float>*, <4 x float>** %constants.addr, align 4
   call void @__bb(<4 x float> %vcvt.i, i8* %tmp1, i32 %tmp2, <4 x float>* %tmp3)
   ret void
 }
@@ -48,12 +48,12 @@ entry:
   store i8* %p, i8** %p.addr, align 4
   store i32 %offset, i32* %offset.addr, align 4
   store <4 x float>* %constants, <4 x float>** %constants.addr, align 4
-  %tmp = load i64* %data, align 4
-  %tmp1 = load i8** %p.addr, align 4
-  %tmp2 = load i32* %offset.addr, align 4
-  %add.ptr = getelementptr i8* %tmp1, i32 %tmp2
+  %tmp = load i64, i64* %data, align 4
+  %tmp1 = load i8*, i8** %p.addr, align 4
+  %tmp2 = load i32, i32* %offset.addr, align 4
+  %add.ptr = getelementptr i8, i8* %tmp1, i32 %tmp2
   %0 = bitcast i8* %add.ptr to i64*
-  %arrayidx = getelementptr inbounds i64* %0, i32 0
+  %arrayidx = getelementptr inbounds i64, i64* %0, i32 0
   store i64 %tmp, i64* %arrayidx
   ret void
 }
diff --git a/test/CodeGen/ARM/fast-isel-redefinition.ll b/test/CodeGen/ARM/fast-isel-redefinition.ll
index ee150facac96..a1c8657cb811 100644
--- a/test/CodeGen/ARM/fast-isel-redefinition.ll
+++ b/test/CodeGen/ARM/fast-isel-redefinition.ll
@@ -1,11 +1,11 @@
-; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -optimize-regalloc -regalloc=basic < %s
+; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -optimize-regalloc -regalloc=basic < %s
 ; This isn't exactly a useful set of command-line options, but check that it
 ; doesn't crash.  (It was crashing because a register was getting redefined.)
 
 target triple = "thumbv7-apple-macosx10.6.7"
 
 define i32 @f(i32* %x) nounwind ssp {
-  %y = getelementptr inbounds i32* %x, i32 5000
-  %tmp103 = load i32* %y, align 4
+  %y = getelementptr inbounds i32, i32* %x, i32 5000
+  %tmp103 = load i32, i32* %y, align 4
   ret i32 %tmp103
 }
diff --git a/test/CodeGen/ARM/fast-isel-remat-same-constant.ll b/test/CodeGen/ARM/fast-isel-remat-same-constant.ll
new file mode 100644
index 000000000000..d64cf8022ed4
--- /dev/null
+++ b/test/CodeGen/ARM/fast-isel-remat-same-constant.ll
@@ -0,0 +1,29 @@
+; RUN: llc %s -o - -fast-isel=true -O0 -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7-apple-ios8.0.0"
+
+; This test failed with verify machine instrs due to incorrect kill flags on the add instructions
+; generated by the GEPs.  The first add generated killed the vreg for the #6680 constant which should
+; be correct.  However, the second add is also a constant expression and the local value save area grows
+; down.  This meant the next use of the vreg for #6680 was after the first which had killed it.
+
+; CHECK: #6680
+
+%struct.RD_8x8DATA = type { i32, [16 x [16 x i32]], [16 x [16 x i32]], [16 x [16 x i32]], [3 x [16 x [16 x i32]]], [4 x i16], [4 x i8], [4 x i8], [4 x i8], [16 x [16 x i16]], [16 x [16 x i16]], [16 x [16 x i32]] }
+
+@tr8x8 = external global %struct.RD_8x8DATA, align 4
+@tr4x4 = external global %struct.RD_8x8DATA, align 4
+
+; Function Attrs: noreturn
+declare void @foo(i16*, i16*) #0
+
+; Function Attrs: minsize
+define i32 @test() #1 {
+bb:
+  call void @foo(i16* getelementptr inbounds (%struct.RD_8x8DATA, %struct.RD_8x8DATA* @tr8x8, i32 0, i32 10, i32 0, i32 0), i16* getelementptr inbounds (%struct.RD_8x8DATA, %struct.RD_8x8DATA* @tr4x4, i32 0, i32 10, i32 0, i32 0))
+  unreachable
+}
+
+attributes #0 = { noreturn }
+attributes #1 = { minsize }
diff --git a/test/CodeGen/ARM/fast-isel-ret.ll b/test/CodeGen/ARM/fast-isel-ret.ll
index 8a68309dc831..f66479c2cfa3 100644
--- a/test/CodeGen/ARM/fast-isel-ret.ll
+++ b/test/CodeGen/ARM/fast-isel-ret.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s
 
 ; Sign-extend of i1 currently not supported by fast-isel
 ;define signext i1 @ret0(i1 signext %a) nounwind uwtable ssp {
diff --git a/test/CodeGen/ARM/fast-isel-select.ll b/test/CodeGen/ARM/fast-isel-select.ll
index 549c97e24dcd..4eef1d6bb988 100644
--- a/test/CodeGen/ARM/fast-isel-select.ll
+++ b/test/CodeGen/ARM/fast-isel-select.ll
@@ -1,18 +1,18 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv8-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv8-apple-ios | FileCheck %s --check-prefix=THUMB
 
 define i32 @t1(i1 %c) nounwind readnone {
 entry:
 ; ARM: t1
 ; ARM: movw r{{[1-9]}}, #10
-; ARM: cmp r0, #0
+; ARM: tst r0, #1
 ; ARM: moveq r{{[1-9]}}, #20
 ; ARM: mov r0, r{{[1-9]}}
 ; THUMB: t1
 ; THUMB: movs r{{[1-9]}}, #10
-; THUMB: cmp r0, #0
+; THUMB: tst.w r0, #1
 ; THUMB: it eq
 ; THUMB: moveq r{{[1-9]}}, #20
 ; THUMB: mov r0, r{{[1-9]}}
@@ -23,11 +23,11 @@ entry:
 define i32 @t2(i1 %c, i32 %a) nounwind readnone {
 entry:
 ; ARM: t2
-; ARM: cmp r0, #0
+; ARM: tst r0, #1
 ; ARM: moveq r{{[1-9]}}, #20
 ; ARM: mov r0, r{{[1-9]}}
 ; THUMB: t2
-; THUMB: cmp r0, #0
+; THUMB: tst.w r0, #1
 ; THUMB: it eq
 ; THUMB: moveq r{{[1-9]}}, #20
 ; THUMB: mov r0, r{{[1-9]}}
@@ -38,11 +38,11 @@ entry:
 define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone {
 entry:
 ; ARM: t3
-; ARM: cmp r0, #0
+; ARM: tst r0, #1
 ; ARM: movne r2, r1
 ; ARM: add r0, r2, r1
 ; THUMB: t3
-; THUMB: cmp r0, #0
+; THUMB: tst.w r0, #1
 ; THUMB: it ne
 ; THUMB: movne r2, r1
 ; THUMB: add.w r0, r2, r1
@@ -55,12 +55,12 @@ define i32 @t4(i1 %c) nounwind readnone {
 entry:
 ; ARM: t4
 ; ARM: mvn r{{[1-9]}}, #9
-; ARM: cmp r0, #0
+; ARM: tst r0, #1
 ; ARM: mvneq r{{[1-9]}}, #0
 ; ARM: mov r0, r{{[1-9]}}
 ; THUMB-LABEL: t4
 ; THUMB: mvn [[REG:r[1-9]+]], #9
-; THUMB: cmp r0, #0
+; THUMB: tst.w r0, #1
 ; THUMB: it eq
 ; THUMB: mvneq [[REG]], #0
 ; THUMB: mov r0, [[REG]]
@@ -71,11 +71,11 @@ entry:
 define i32 @t5(i1 %c, i32 %a) nounwind readnone {
 entry:
 ; ARM: t5
-; ARM: cmp r0, #0
+; ARM: tst r0, #1
 ; ARM: mvneq r{{[1-9]}}, #1
 ; ARM: mov r0, r{{[1-9]}}
 ; THUMB: t5
-; THUMB: cmp r0, #0
+; THUMB: tst.w r0, #1
 ; THUMB: it eq
 ; THUMB: mvneq r{{[1-9]}}, #1
 ; THUMB: mov r0, r{{[1-9]}}
@@ -87,11 +87,11 @@ entry:
 define i32 @t6(i1 %c, i32 %a) nounwind readnone {
 entry:
 ; ARM: t6
-; ARM: cmp r0, #0
+; ARM: tst r0, #1
 ; ARM: mvneq r{{[1-9]}}, #978944
 ; ARM: mov r0, r{{[1-9]}}
 ; THUMB: t6
-; THUMB: cmp r0, #0
+; THUMB: tst.w r0, #1
 ; THUMB: it eq
 ; THUMB: mvneq r{{[1-9]}}, #978944
 ; THUMB: mov r0, r{{[1-9]}}
diff --git a/test/CodeGen/ARM/fast-isel-shift-materialize.ll b/test/CodeGen/ARM/fast-isel-shift-materialize.ll
new file mode 100644
index 000000000000..ab36a979d71b
--- /dev/null
+++ b/test/CodeGen/ARM/fast-isel-shift-materialize.ll
@@ -0,0 +1,25 @@
+; RUN: llc %s -o - -verify-machineinstrs -fast-isel=true | FileCheck %s
+
+target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7-apple-ios8.0.0"
+
+; When materializing the '2' for the shifts below, the second shift kills the vreg
+; we materialize in to.  However, the first shift was also killing that vreg.
+; This fails the machine verifier because the second use then thinks its reading an
+; undefined register.
+
+; CHECK: lsr.w
+; CHECK: lsr.w
+
+declare void @foo(i32, i32)
+
+; Function Attrs: minsize
+define i32 @test(i32 %tmp3, i32 %tmp9) #0 {
+bb:
+  %tmp4 = lshr i32 %tmp3, 2
+  %tmp10 = lshr i32 %tmp9, 2
+  call void @foo(i32 %tmp10, i32 %tmp4)
+  unreachable
+}
+
+attributes #0 = { minsize }
diff --git a/test/CodeGen/ARM/fast-isel-shifter.ll b/test/CodeGen/ARM/fast-isel-shifter.ll
index eb4b2b2ce0ae..87b861f35396 100644
--- a/test/CodeGen/ARM/fast-isel-shifter.ll
+++ b/test/CodeGen/ARM/fast-isel-shifter.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
 
 define i32 @shl() nounwind ssp {
 entry:
diff --git a/test/CodeGen/ARM/fast-isel-static.ll b/test/CodeGen/ARM/fast-isel-static.ll
index 9bd0a51e7120..c3980cb51f67 100644
--- a/test/CodeGen/ARM/fast-isel-static.ll
+++ b/test/CodeGen/ARM/fast-isel-static.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s
-; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s
-; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s
-; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s
+; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s
+; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s
+; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s
+; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s
 
 define void @myadd(float* %sum, float* %addend) nounwind {
 entry:
@@ -9,12 +9,12 @@ entry:
   %addend.addr = alloca float*, align 4
   store float* %sum, float** %sum.addr, align 4
   store float* %addend, float** %addend.addr, align 4
-  %tmp = load float** %sum.addr, align 4
-  %tmp1 = load float* %tmp
-  %tmp2 = load float** %addend.addr, align 4
-  %tmp3 = load float* %tmp2
+  %tmp = load float*, float** %sum.addr, align 4
+  %tmp1 = load float, float* %tmp
+  %tmp2 = load float*, float** %addend.addr, align 4
+  %tmp3 = load float, float* %tmp2
   %add = fadd float %tmp1, %tmp3
-  %tmp4 = load float** %sum.addr, align 4
+  %tmp4 = load float*, float** %sum.addr, align 4
   store float %add, float* %tmp4
   ret void
 }
diff --git a/test/CodeGen/ARM/fast-isel-update-valuemap-for-extract.ll b/test/CodeGen/ARM/fast-isel-update-valuemap-for-extract.ll
new file mode 100644
index 000000000000..18d60fee189f
--- /dev/null
+++ b/test/CodeGen/ARM/fast-isel-update-valuemap-for-extract.ll
@@ -0,0 +1,24 @@
+; RUN: llc %s -o - -fast-isel=true -O0 -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7-apple-ios8.0.0"
+
+; This test ensures that when fast-isel rewrites uses of the vreg for %tmp29, it also
+; updates kill flags on the shift instruction generated as part of the gep.
+; This was failing instruction verification.
+
+; CHECK-LABEL: @test
+
+%struct.node = type opaque
+
+declare void @foo([4 x i32], %struct.node*)
+
+define void @test([4 x i32] %xpic.coerce, %struct.node* %t) {
+bb:
+  %tmp29 = extractvalue [4 x i32] %xpic.coerce, 0
+  %tmp40 = bitcast %struct.node* %t to [8 x %struct.node*]*
+  %tmp41 = getelementptr inbounds [8 x %struct.node*], [8 x %struct.node*]* %tmp40, i32 0, i32 %tmp29
+  %tmp42 = load %struct.node*, %struct.node** %tmp41, align 4
+  call void @foo([4 x i32] %xpic.coerce, %struct.node* %tmp42)
+  ret void
+}
diff --git a/test/CodeGen/ARM/fast-isel-vaddd.ll b/test/CodeGen/ARM/fast-isel-vaddd.ll
new file mode 100644
index 000000000000..2aa269a9774d
--- /dev/null
+++ b/test/CodeGen/ARM/fast-isel-vaddd.ll
@@ -0,0 +1,33 @@
+; RUN: llc %s -o - -verify-machineinstrs -fast-isel=true -mattr=+vfp4 -mattr=+neon | FileCheck %s
+
+target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7s-apple-ios8.0.0"
+
+%union.DV = type { <2 x double> }
+
+; Fast-ISel was incorrectly trying to codegen <2 x double> adds and returning only a single vadds
+; Check that we generate the 2 vaddd's we expect
+
+; CHECK: vadd.f64
+; CHECK: vadd.f64
+
+define i32 @main(i32 %argc, i8** nocapture readnone %Argv, <2 x double> %tmp31) {
+bb:
+  %Ad = alloca %union.DV, align 16
+  %tmp32 = getelementptr inbounds %union.DV, %union.DV* %Ad, i32 0, i32 0
+  %tmp33 = fadd <2 x double> %tmp31, %tmp31
+  br label %bb37
+
+bb37:                                             ; preds = %bb37, %bb
+  %i.02 = phi i32 [ 0, %bb ], [ %tmp38, %bb37 ]
+  store <2 x double> %tmp33, <2 x double>* %tmp32, align 16
+  %tmp38 = add nuw nsw i32 %i.02, 1
+  %exitcond = icmp eq i32 %tmp38, 500000
+  br i1 %exitcond, label %bb39, label %bb37
+
+bb39:                                             ; preds = %bb37
+  call fastcc void @printDV(%union.DV* %Ad)
+  ret i32 0
+}
+
+declare hidden fastcc void @printDV(%union.DV* nocapture readonly)
diff --git a/test/CodeGen/ARM/fast-isel-vararg.ll b/test/CodeGen/ARM/fast-isel-vararg.ll
index 3ff2b151ab5f..35442eea1005 100644
--- a/test/CodeGen/ARM/fast-isel-vararg.ll
+++ b/test/CodeGen/ARM/fast-isel-vararg.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 define i32 @VarArg() nounwind {
 entry:
@@ -10,11 +10,11 @@ entry:
   %m = alloca i32, align 4
   %n = alloca i32, align 4
   %tmp = alloca i32, align 4
-  %0 = load i32* %i, align 4
-  %1 = load i32* %j, align 4
-  %2 = load i32* %k, align 4
-  %3 = load i32* %m, align 4
-  %4 = load i32* %n, align 4
+  %0 = load i32, i32* %i, align 4
+  %1 = load i32, i32* %j, align 4
+  %2 = load i32, i32* %k, align 4
+  %3 = load i32, i32* %m, align 4
+  %4 = load i32, i32* %n, align 4
 ; ARM: VarArg
 ; ARM: mov [[FP:r[0-9]+]], sp
 ; ARM: sub sp, sp, #32
@@ -37,9 +37,9 @@ entry:
 ; THUMB: str.w {{[a-z0-9]+}}, [sp]
 ; THUMB: str.w {{[a-z0-9]+}}, [sp, #4]
 ; THUMB: bl {{_?}}CallVariadic
-  %call = call i32 (i32, ...)* @CallVariadic(i32 5, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4)
+  %call = call i32 (i32, ...) @CallVariadic(i32 5, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4)
   store i32 %call, i32* %tmp, align 4
-  %5 = load i32* %tmp, align 4
+  %5 = load i32, i32* %tmp, align 4
   ret i32 %5
 }
 
diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll
index 5981cab7dcb1..49460220c47c 100644
--- a/test/CodeGen/ARM/fast-isel.ll
+++ b/test/CodeGen/ARM/fast-isel.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
 
 ; Very basic fast-isel functionality.
 define i32 @test0(i32 %a, i32 %b) nounwind {
@@ -9,8 +9,8 @@ entry:
   %b.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr
   store i32 %b, i32* %b.addr
-  %tmp = load i32* %a.addr
-  %tmp1 = load i32* %b.addr
+  %tmp = load i32, i32* %a.addr
+  %tmp1 = load i32, i32* %b.addr
   %add = add nsw i32 %tmp, %tmp1
   ret i32 %add
 }
@@ -110,9 +110,9 @@ bb2:
 ; ARM: sxth
 
 bb3:
-  %c1 = load i8* %ptr3
-  %c2 = load i16* %ptr2
-  %c3 = load i32* %ptr1
+  %c1 = load i8, i8* %ptr3
+  %c2 = load i16, i16* %ptr2
+  %c3 = load i32, i32* %ptr1
   %c4 = zext i8 %c1 to i32
   %c5 = sext i16 %c2 to i32
   %c6 = add i32 %c4, %c5
@@ -138,7 +138,7 @@ bb3:
 @test4g = external global i32
 
 define void @test4() {
-  %a = load i32* @test4g
+  %a = load i32, i32* @test4g
   %b = add i32 %a, 1
   store i32 %b, i32* @test4g
   ret void
diff --git a/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll b/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll
index a32ab6d09317..232ab50c3ee5 100644
--- a/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll
+++ b/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll
@@ -6,13 +6,13 @@ define zeroext i8 @gep_promotion(i8* %ptr) nounwind uwtable ssp {
 entry:
   %ptr.addr = alloca i8*, align 8
   %add = add i8 64, 64 ; 0x40 + 0x40
-  %0 = load i8** %ptr.addr, align 8
+  %0 = load i8*, i8** %ptr.addr, align 8
 
   ; CHECK-LABEL: _gep_promotion:
   ; CHECK: ldrb {{r[0-9]+}}, {{\[r[0-9]+\]}}
-  %arrayidx = getelementptr inbounds i8* %0, i8 %add
+  %arrayidx = getelementptr inbounds i8, i8* %0, i8 %add
 
-  %1 = load i8* %arrayidx, align 1
+  %1 = load i8, i8* %arrayidx, align 1
   ret i8 %1
 }
 
diff --git a/test/CodeGen/ARM/fcopysign.ll b/test/CodeGen/ARM/fcopysign.ll
index 1de057208ce3..d013fbf8c15a 100644
--- a/test/CodeGen/ARM/fcopysign.ll
+++ b/test/CodeGen/ARM/fcopysign.ll
@@ -48,7 +48,7 @@ entry:
 ; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000
 ; SOFT: vshr.u64 [[REG7]], [[REG7]], #32
 ; SOFT: vbsl [[REG6]], [[REG7]], 
-  %0 = tail call double (...)* @bar() nounwind
+  %0 = tail call double (...) @bar() nounwind
   %1 = fptrunc double %0 to float
   %2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone
   %3 = fadd float %1, %2
diff --git a/test/CodeGen/ARM/flag-crash.ll b/test/CodeGen/ARM/flag-crash.ll
index 9c61944a2154..66eb8a51c18a 100644
--- a/test/CodeGen/ARM/flag-crash.ll
+++ b/test/CodeGen/ARM/flag-crash.ll
@@ -5,13 +5,13 @@
 
 define fastcc void @func(%struct.gs_matrix* nocapture %pm1) nounwind {
 entry:
-  %0 = getelementptr inbounds %struct.gs_matrix* %pm1, i32 0, i32 6
-  %1 = load float* %0, align 4
-  %2 = getelementptr inbounds %struct.gs_matrix* %pm1, i32 0, i32 8
-  %3 = load float* %2, align 4
-  %4 = getelementptr inbounds %struct.gs_matrix* %pm1, i32 0, i32 2
+  %0 = getelementptr inbounds %struct.gs_matrix, %struct.gs_matrix* %pm1, i32 0, i32 6
+  %1 = load float, float* %0, align 4
+  %2 = getelementptr inbounds %struct.gs_matrix, %struct.gs_matrix* %pm1, i32 0, i32 8
+  %3 = load float, float* %2, align 4
+  %4 = getelementptr inbounds %struct.gs_matrix, %struct.gs_matrix* %pm1, i32 0, i32 2
   %5 = bitcast float* %4 to i32*
-  %6 = load i32* %5, align 4
+  %6 = load i32, i32* %5, align 4
   %7 = or i32 0, %6
   %.mask = and i32 %7, 2147483647
   %8 = icmp eq i32 %.mask, 0
diff --git a/test/CodeGen/ARM/fnegs.ll b/test/CodeGen/ARM/fnegs.ll
index 65fe9e36fa1d..3a4767e9173f 100644
--- a/test/CodeGen/ARM/fnegs.ll
+++ b/test/CodeGen/ARM/fnegs.ll
@@ -21,7 +21,7 @@
 
 define float @test1(float* %a) {
 entry:
-	%0 = load float* %a, align 4		; <float> [#uses=2]
+	%0 = load float, float* %a, align 4		; <float> [#uses=2]
 	%1 = fsub float -0.000000e+00, %0		; <float> [#uses=2]
 	%2 = fpext float %1 to double		; <double> [#uses=1]
 	%3 = fcmp olt double %2, 1.234000e+00		; <i1> [#uses=1]
@@ -48,7 +48,7 @@ entry:
 
 define float @test2(float* %a) {
 entry:
-	%0 = load float* %a, align 4		; <float> [#uses=2]
+	%0 = load float, float* %a, align 4		; <float> [#uses=2]
 	%1 = fmul float -1.000000e+00, %0		; <float> [#uses=2]
 	%2 = fpext float %1 to double		; <double> [#uses=1]
 	%3 = fcmp olt double %2, 1.234000e+00		; <i1> [#uses=1]
diff --git a/test/CodeGen/ARM/fold-stack-adjust.ll b/test/CodeGen/ARM/fold-stack-adjust.ll
index c5ff82eaf830..1fd9bd9e47a3 100644
--- a/test/CodeGen/ARM/fold-stack-adjust.ll
+++ b/test/CodeGen/ARM/fold-stack-adjust.ll
@@ -12,11 +12,11 @@ declare void @bar(i8*)
 
 define void @check_simple() minsize {
 ; CHECK-LABEL: check_simple:
-; CHECK: push.w {r7, r8, r9, r10, r11, lr}
+; CHECK: push {r3, r4, r5, r6, r7, lr}
 ; CHECK-NOT: sub sp, sp,
 ; ...
 ; CHECK-NOT: add sp, sp,
-; CHECK: pop.w {r0, r1, r2, r3, r11, pc}
+; CHECK: pop {r0, r1, r2, r3, r7, pc}
 
 ; CHECK-T1-LABEL: check_simple:
 ; CHECK-T1: push {r3, r4, r5, r6, r7, lr}
@@ -44,11 +44,11 @@ define void @check_simple() minsize {
 
 define void @check_simple_too_big() minsize {
 ; CHECK-LABEL: check_simple_too_big:
-; CHECK: push.w {r11, lr}
+; CHECK: push {r7, lr}
 ; CHECK: sub sp,
 ; ...
 ; CHECK: add sp,
-; CHECK: pop.w {r11, pc}
+; CHECK: pop {r7, pc}
   %var = alloca i8, i32 64
   call void @bar(i8* %var)
   ret void
@@ -82,7 +82,7 @@ define void @check_vfp_fold() minsize {
 
   %var = alloca i8, i32 16
 
-  %tmp = load %bigVec* @var
+  %tmp = load %bigVec, %bigVec* @var
   call void @bar(i8* %var)
   store %bigVec %tmp, %bigVec* @var
 
@@ -93,11 +93,11 @@ define void @check_vfp_fold() minsize {
 ; folded in except that doing so would clobber the value being returned.
 define i64 @check_no_return_clobber() minsize {
 ; CHECK-LABEL: check_no_return_clobber:
-; CHECK: push.w {r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK: push {r1, r2, r3, r4, r5, r6, r7, lr}
 ; CHECK-NOT: sub sp,
 ; ...
 ; CHECK: add sp, #24
-; CHECK: pop.w {r11, pc}
+; CHECK: pop {r7, pc}
 
   ; Just to keep iOS FileCheck within previous function:
 ; CHECK-IOS-LABEL: check_no_return_clobber:
@@ -119,7 +119,7 @@ define arm_aapcs_vfpcc double @check_vfp_no_return_clobber() minsize {
 
   %var = alloca i8, i32 64
 
-  %tmp = load %bigVec* @var
+  %tmp = load %bigVec, %bigVec* @var
   call void @bar(i8* %var)
   store %bigVec %tmp, %bigVec* @var
 
@@ -152,7 +152,7 @@ define void @test_fold_point(i1 %tst) minsize {
 
   ; We want a long-lived floating register so that a callee-saved dN is used and
   ; there's both a vpop and a pop.
-  %live_val = load double* @dbl
+  %live_val = load double, double* @dbl
   br i1 %tst, label %true, label %end
 true:
   call void @bar(i8* %var)
@@ -176,9 +176,9 @@ define void @test_varsize(...) minsize {
 
 ; CHECK-LABEL: test_varsize:
 ; CHECK: sub	sp, #16
-; CHECK: push.w {r9, r10, r11, lr}
+; CHECK: push	{r5, r6, r7, lr}
 ; ...
-; CHECK: pop.w	{r2, r3, r11, lr}
+; CHECK: pop.w	{r2, r3, r7, lr}
 ; CHECK: add	sp, #16
 ; CHECK: bx	lr
 
diff --git a/test/CodeGen/ARM/fp.ll b/test/CodeGen/ARM/fp.ll
index 7e1f000e88d9..cc47e3baddad 100644
--- a/test/CodeGen/ARM/fp.ll
+++ b/test/CodeGen/ARM/fp.ll
@@ -45,7 +45,7 @@ define double @h(double* %v) {
 ;CHECK: vldr
 ;CHECK-NEXT: vmov
 entry:
-        %tmp = load double* %v          ; <double> [#uses=1]
+        %tmp = load double, double* %v          ; <double> [#uses=1]
         ret double %tmp
 }
 
diff --git a/test/CodeGen/ARM/fp16-promote.ll b/test/CodeGen/ARM/fp16-promote.ll
new file mode 100644
index 000000000000..e691c2bb8a97
--- /dev/null
+++ b/test/CodeGen/ARM/fp16-promote.ll
@@ -0,0 +1,903 @@
+; RUN: llc -asm-verbose=false < %s -mattr=+vfp3,+fp16 | FileCheck %s -check-prefix=CHECK-FP16 -check-prefix=CHECK-ALL
+; RUN: llc -asm-verbose=false < %s | FileCheck %s -check-prefix=CHECK-LIBCALL -check-prefix=CHECK-ALL
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
+target triple = "armv7-eabihf"
+
+; CHECK-FP16-LABEL: test_fadd:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vadd.f32
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_fadd:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: vadd.f32
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_fadd(half* %p, half* %q) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %r = fadd half %a, %b
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_fsub:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vsub.f32
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_fsub:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: vsub.f32
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_fsub(half* %p, half* %q) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %r = fsub half %a, %b
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_fmul:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vmul.f32
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_fmul
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: vmul.f32
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_fmul(half* %p, half* %q) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %r = fmul half %a, %b
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_fdiv:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vdiv.f32
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_fdiv
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: vdiv.f32
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_fdiv(half* %p, half* %q) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %r = fdiv half %a, %b
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_frem:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl fmodf
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_frem
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl fmodf
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_frem(half* %p, half* %q) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %r = frem half %a, %b
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-ALL-LABEL: test_load_store:
+; CHECK-ALL-NEXT: .fnstart
+; CHECK-ALL-NEXT: ldrh r0, [r0]
+; CHECK-ALL-NEXT: strh r0, [r1]
+; CHECK-ALL-NEXT: bx lr
+define void @test_load_store(half* %p, half* %q) #0 {
+  %a = load half, half* %p, align 2
+  store half %a, half* %q
+  ret void
+}
+
+; Testing only successfull compilation of function calls.  In ARM ABI, half
+; args and returns are handled as f32.
+
+declare half @test_callee(half %a, half %b) #0
+
+; CHECK-ALL-LABEL: test_call:
+; CHECK-ALL-NEXT: .fnstart
+; CHECK-ALL-NEXT: push {r11, lr}
+; CHECK-ALL-NEXT: bl test_callee
+; CHECK-ALL-NEXT: pop {r11, pc}
+define half @test_call(half %a, half %b) #0 {
+  %r = call half @test_callee(half %a, half %b)
+  ret half %r
+}
+
+; CHECK-ALL-LABEL: test_call_flipped:
+; CHECK-ALL-NEXT: .fnstart
+; CHECK-ALL-NEXT: push {r11, lr}
+; CHECK-ALL-NEXT: mov r2, r0
+; CHECK-ALL-NEXT: mov r0, r1
+; CHECK-ALL-NEXT: mov r1, r2
+; CHECK-ALL-NEXT: bl test_callee
+; CHECK-ALL-NEXT: pop {r11, pc}
+define half @test_call_flipped(half %a, half %b) #0 {
+  %r = call half @test_callee(half %b, half %a)
+  ret half %r
+}
+
+; CHECK-ALL-LABEL: test_tailcall_flipped:
+; CHECK-ALL-NEXT: .fnstart
+; CHECK-ALL-NEXT: mov r2, r0
+; CHECK-ALL-NEXT: mov r0, r1
+; CHECK-ALL-NEXT: mov r1, r2
+; CHECK-ALL-NEXT: b test_callee
+define half @test_tailcall_flipped(half %a, half %b) #0 {
+  %r = tail call half @test_callee(half %b, half %a)
+  ret half %r
+}
+
+; Optimizer picks %p or %q based on %c and only loads that value
+; No conversion is needed
+; CHECK-ALL-LABEL: test_select:
+; CHECK-ALL-NEXT: .fnstart
+; CHECK-ALL-NEXT: cmp r2, #0
+; CHECK-ALL-NEXT: movne r1, r0
+; CHECK-ALL-NEXT: ldrh r1, [r1]
+; CHECK-ALL-NEXT: strh r1, [r0]
+; CHECK-ALL-NEXT: bx lr
+define void @test_select(half* %p, half* %q, i1 zeroext %c) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %r = select i1 %c, half %a, half %b
+  store half %r, half* %p
+  ret void
+}
+
+; Test only two variants of fcmp.  These get translated to f32 vcmpe
+; instructions anyway.
+; CHECK-FP16-LABEL: test_fcmp_une:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcmpe.f32
+; CHECK-FP16: vmrs APSR_nzcv, fpscr
+; CHECK-FP16: movwne
+; CHECK-LIBCALL-LABEL: test_fcmp_une:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: vcmpe.f32
+; CHECK-LIBCALL: movwne
+define i1 @test_fcmp_une(half* %p, half* %q) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %r = fcmp une half %a, %b
+  ret i1 %r
+}
+
+; CHECK-FP16-LABEL: test_fcmp_ueq:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcmpe.f32
+; CHECK-FP16: vmrs APSR_nzcv, fpscr
+; CHECK-FP16: movweq
+; CHECK-FP16: movwvs
+; CHECK-LIBCALL-LABEL: test_fcmp_ueq:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: vcmpe.f32
+; CHECK-LIBCALL: movweq
+define i1 @test_fcmp_ueq(half* %p, half* %q) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %r = fcmp ueq half %a, %b
+  ret i1 %r
+}
+
+; CHECK-FP16-LABEL: test_br_cc:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcmpe.f32
+; CHECK-FP16: vmrs APSR_nzcv, fpscr
+; CHECK-FP16: strmi
+; CHECK-FP16: strpl
+; CHECK-LIBCALL-LABEL: test_br_cc:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: vcmpe.f32
+; CHECK-LIBCALL: strmi
+; CHECK-LIBCALL: strpl
+define void @test_br_cc(half* %p, half* %q, i32* %p1, i32* %p2) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %c = fcmp uge half %a, %b
+  br i1 %c, label %then, label %else
+then:
+  store i32 0, i32* %p1
+  ret void
+else:
+  store i32 0, i32* %p2
+  ret void
+}
+
+declare i1 @test_dummy(half* %p) #0
+; CHECK-FP16-LABEL: test_phi:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: [[LOOP:.LBB[1-9_]+]]:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl      test_dummy
+; CHECK-FP16: bne     [[LOOP]]
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_phi:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: [[LOOP:.LBB[1-9_]+]]:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl test_dummy
+; CHECK-LIBCALL: bne     [[LOOP]]
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_phi(half* %p) #0 {
+entry:
+  %a = load half, half* %p
+  br label %loop
+loop:
+  %r = phi half [%a, %entry], [%b, %loop]
+  %b = load half, half* %p
+  %c = call i1 @test_dummy(half* %p)
+  br i1 %c, label %loop, label %return
+return:
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_fptosi_i32:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvt.s32.f32
+; CHECK-LIBCALL-LABEL: test_fptosi_i32:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: vcvt.s32.f32
+define i32 @test_fptosi_i32(half* %p) #0 {
+  %a = load half, half* %p, align 2
+  %r = fptosi half %a to i32
+  ret i32 %r
+}
+
+; CHECK-FP16-LABEL: test_fptosi_i64:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl __aeabi_f2lz
+; CHECK-LIBCALL-LABEL: test_fptosi_i64:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __aeabi_f2lz
+define i64 @test_fptosi_i64(half* %p) #0 {
+  %a = load half, half* %p, align 2
+  %r = fptosi half %a to i64
+  ret i64 %r
+}
+
+; CHECK-FP16-LABEL: test_fptoui_i32:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvt.u32.f32
+; CHECK-LIBCALL-LABEL: test_fptoui_i32:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: vcvt.u32.f32
+define i32 @test_fptoui_i32(half* %p) #0 {
+  %a = load half, half* %p, align 2
+  %r = fptoui half %a to i32
+  ret i32 %r
+}
+
+; CHECK-FP16-LABEL: test_fptoui_i64:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl __aeabi_f2ulz
+; CHECK-LIBCALL-LABEL: test_fptoui_i64:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __aeabi_f2ulz
+define i64 @test_fptoui_i64(half* %p) #0 {
+  %a = load half, half* %p, align 2
+  %r = fptoui half %a to i64
+  ret i64 %r
+}
+
+; CHECK-FP16-LABEL: test_sitofp_i32:
+; CHECK-FP16: vcvt.f32.s32
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_sitofp_i32:
+; CHECK-LIBCALL: vcvt.f32.s32
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_sitofp_i32(i32 %a, half* %p) #0 {
+  %r = sitofp i32 %a to half
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_uitofp_i32:
+; CHECK-FP16: vcvt.f32.u32
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_uitofp_i32:
+; CHECK-LIBCALL: vcvt.f32.u32
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_uitofp_i32(i32 %a, half* %p) #0 {
+  %r = uitofp i32 %a to half
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_sitofp_i64:
+; CHECK-FP16: bl __aeabi_l2f
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_sitofp_i64:
+; CHECK-LIBCALL: bl __aeabi_l2f
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_sitofp_i64(i64 %a, half* %p) #0 {
+  %r = sitofp i64 %a to half
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_uitofp_i64:
+; CHECK-FP16: bl __aeabi_ul2f
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_uitofp_i64:
+; CHECK-LIBCALL: bl __aeabi_ul2f
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_uitofp_i64(i64 %a, half* %p) #0 {
+  %r = uitofp i64 %a to half
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_fptrunc_float:
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_fptrunc_float:
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_fptrunc_float(float %f, half* %p) #0 {
+  %a = fptrunc float %f to half
+  store half %a, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_fptrunc_double:
+; CHECK-FP16: bl __aeabi_d2h
+; CHECK-LIBCALL-LABEL: test_fptrunc_double:
+; CHECK-LIBCALL: bl __aeabi_d2h
+define void @test_fptrunc_double(double %d, half* %p) #0 {
+  %a = fptrunc double %d to half
+  store half %a, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_fpextend_float:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-LIBCALL-LABEL: test_fpextend_float:
+; CHECK-LIBCALL: b __gnu_h2f_ieee
+define float @test_fpextend_float(half* %p) {
+  %a = load half, half* %p, align 2
+  %r = fpext half %a to float
+  ret float %r
+}
+
+; CHECK-FP16-LABEL: test_fpextend_double:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvt.f64.f32
+; CHECK-LIBCALL-LABEL: test_fpextend_double:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: vcvt.f64.f32
+define double @test_fpextend_double(half* %p) {
+  %a = load half, half* %p, align 2
+  %r = fpext half %a to double
+  ret double %r
+}
+
+; CHECK-ALL-LABEL: test_bitcast_halftoi16:
+; CHECK-ALL-NEXT: .fnstart
+; CHECK-ALL-NEXT: ldrh r0, [r0]
+; CHECK-ALL-NEXT: bx lr
+define i16 @test_bitcast_halftoi16(half* %p) #0 {
+  %a = load half, half* %p, align 2
+  %r = bitcast half %a to i16
+  ret i16 %r
+}
+
+; CHECK-ALL-LABEL: test_bitcast_i16tohalf:
+; CHECK-ALL-NEXT: .fnstart
+; CHECK-ALL-NEXT: strh r0, [r1]
+; CHECK-ALL-NEXT: bx lr
+define void @test_bitcast_i16tohalf(i16 %a, half* %p) #0 {
+  %r = bitcast i16 %a to half
+  store half %r, half* %p
+  ret void
+}
+
+declare half @llvm.sqrt.f16(half %a) #0
+declare half @llvm.powi.f16(half %a, i32 %b) #0
+declare half @llvm.sin.f16(half %a) #0
+declare half @llvm.cos.f16(half %a) #0
+declare half @llvm.pow.f16(half %a, half %b) #0
+declare half @llvm.exp.f16(half %a) #0
+declare half @llvm.exp2.f16(half %a) #0
+declare half @llvm.log.f16(half %a) #0
+declare half @llvm.log10.f16(half %a) #0
+declare half @llvm.log2.f16(half %a) #0
+declare half @llvm.fma.f16(half %a, half %b, half %c) #0
+declare half @llvm.fabs.f16(half %a) #0
+declare half @llvm.minnum.f16(half %a, half %b) #0
+declare half @llvm.maxnum.f16(half %a, half %b) #0
+declare half @llvm.copysign.f16(half %a, half %b) #0
+declare half @llvm.floor.f16(half %a) #0
+declare half @llvm.ceil.f16(half %a) #0
+declare half @llvm.trunc.f16(half %a) #0
+declare half @llvm.rint.f16(half %a) #0
+declare half @llvm.nearbyint.f16(half %a) #0
+declare half @llvm.round.f16(half %a) #0
+declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #0
+
+; CHECK-FP16-LABEL: test_sqrt:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vsqrt.f32
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_sqrt:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: vsqrt.f32
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_sqrt(half* %p) #0 {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.sqrt.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_fpowi:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl __powisf2
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_fpowi:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __powisf2
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_fpowi(half* %p, i32 %b) #0 {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.powi.f16(half %a, i32 %b)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_sin:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl sinf
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_sin:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl sinf
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_sin(half* %p) #0 {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.sin.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_cos:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl cosf
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_cos:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl cosf
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_cos(half* %p) #0 {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.cos.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_pow:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl powf
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_pow:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl powf
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_pow(half* %p, half* %q) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %r = call half @llvm.pow.f16(half %a, half %b)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_exp:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl expf
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_exp:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl expf
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_exp(half* %p) #0 {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.exp.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_exp2:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl exp2f
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_exp2:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl exp2f
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_exp2(half* %p) #0 {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.exp2.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_log:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl logf
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_log:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl logf
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_log(half* %p) #0 {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.log.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_log10:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl log10f
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_log10:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl log10f
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_log10(half* %p) #0 {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.log10.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_log2:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl log2f
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_log2:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl log2f
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_log2(half* %p) #0 {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.log2.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_fma:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl fmaf
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_fma:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl fmaf
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_fma(half* %p, half* %q, half* %r) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %c = load half, half* %r, align 2
+  %v = call half @llvm.fma.f16(half %a, half %b, half %c)
+  store half %v, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_fabs:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vabs.f32
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_fabs:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bfc
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_fabs(half* %p) {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.fabs.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_minnum:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl fminf
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_minnum:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl fminf
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_minnum(half* %p, half* %q) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %r = call half @llvm.minnum.f16(half %a, half %b)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_maxnum:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl fmaxf
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_maxnum:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl fmaxf
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_maxnum(half* %p, half* %q) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %r = call half @llvm.maxnum.f16(half %a, half %b)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_copysign:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vbsl
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_copysign:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: vbsl
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_copysign(half* %p, half* %q) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %r = call half @llvm.copysign.f16(half %a, half %b)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_floor:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl floorf
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_floor:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl floorf
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_floor(half* %p) {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.floor.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_ceil:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl ceilf
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_ceil:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl ceilf
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_ceil(half* %p) {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.ceil.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_trunc:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl truncf
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_trunc:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl truncf
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_trunc(half* %p) {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.trunc.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_rint:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl rintf
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_rint:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl rintf
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_rint(half* %p) {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.rint.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_nearbyint:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl nearbyintf
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_nearbyint:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl nearbyintf
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_nearbyint(half* %p) {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.nearbyint.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_round:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: bl roundf
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_round:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl roundf
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_round(half* %p) {
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.round.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_fmuladd:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-FP16: vmla.f32
+; CHECK-FP16: vcvtb.f16.f32
+; CHECK-LIBCALL-LABEL: test_fmuladd:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+; CHECK-LIBCALL: vmla.f32
+; CHECK-LIBCALL: bl __gnu_f2h_ieee
+define void @test_fmuladd(half* %p, half* %q, half* %r) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %c = load half, half* %r, align 2
+  %v = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
+  store half %v, half* %p
+  ret void
+}
+
+; f16 vectors are not legal in the backend.  Vector elements are not assigned
+; to the register, but are stored in the stack instead.  Hence insertelement
+; and extractelement have these extra loads and stores.
+
+; CHECK-ALL-LABEL: test_insertelement:
+; CHECK-ALL-NEXT: .fnstart
+; CHECK-ALL-NEXT: sub sp, sp, #8
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: strh
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: strh
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: strh
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: strh
+; CHECK-ALL-NEXT: mov
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: add
+; CHECK-ALL-NEXT: strh
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: strh
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: strh
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: strh
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: strh
+; CHECK-ALL-NEXT: add sp, sp, #8
+; CHECK-ALL-NEXT: bx lr
+define void @test_insertelement(half* %p, <4 x half>* %q, i32 %i) #0 {
+  %a = load half, half* %p, align 2
+  %b = load <4 x half>, <4 x half>* %q, align 8
+  %c = insertelement <4 x half> %b, half %a, i32 %i
+  store <4 x half> %c, <4 x half>* %q
+  ret void
+}
+
+; CHECK-ALL-LABEL: test_extractelement:
+; CHECK-ALL-NEXT: .fnstart
+; CHECK-ALL-NEXT: sub sp, sp, #8
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: orr
+; CHECK-ALL-NEXT: str
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: orr
+; CHECK-ALL-NEXT: str
+; CHECK-ALL-NEXT: mov
+; CHECK-ALL-NEXT: add
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: strh
+; CHECK-ALL-NEXT: add sp, sp, #8
+; CHECK-ALL-NEXT: bx lr
+define void @test_extractelement(half* %p, <4 x half>* %q, i32 %i) #0 {
+  %a = load <4 x half>, <4 x half>* %q, align 8
+  %b = extractelement <4 x half> %a, i32 %i
+  store half %b, half* %p
+  ret void
+}
+
+; test struct operations
+
+%struct.dummy = type { i32, half }
+
+; CHECK-ALL-LABEL: test_insertvalue:
+; CHECK-ALL-NEXT: .fnstart
+; CHECK-ALL-NEXT: ldr
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: strh
+; CHECK-ALL-NEXT: str
+; CHECK-ALL-NEXT: bx lr
+define void @test_insertvalue(%struct.dummy* %p, half* %q) {
+  %a = load %struct.dummy, %struct.dummy* %p
+  %b = load half, half* %q
+  %c = insertvalue %struct.dummy %a, half %b, 1
+  store %struct.dummy %c, %struct.dummy* %p
+  ret void
+}
+
+; CHECK-ALL-LABEL: test_extractvalue:
+; CHECK-ALL-NEXT: .fnstart
+; CHECK-ALL-NEXT: ldrh
+; CHECK-ALL-NEXT: strh
+; CHECK-ALL-NEXT: bx lr
+define void @test_extractvalue(%struct.dummy* %p, half* %q) {
+  %a = load %struct.dummy, %struct.dummy* %p
+  %b = extractvalue %struct.dummy %a, 1
+  store half %b, half* %q
+  ret void
+}
+
+; CHECK-FP16-LABEL: test_struct_return:
+; CHECK-FP16: vcvtb.f32.f16
+; CHECK-LIBCALL-LABEL: test_struct_return:
+; CHECK-LIBCALL: bl __gnu_h2f_ieee
+define %struct.dummy @test_struct_return(%struct.dummy* %p) {
+  %a = load %struct.dummy, %struct.dummy* %p
+  ret %struct.dummy %a
+}
+
+; CHECK-ALL-LABEL: test_struct_arg:
+; CHECK-ALL-NEXT: .fnstart
+; CHECK-ALL-NEXT: mov r0, r1
+; CHECK-ALL-NEXT: bx lr
+define half @test_struct_arg(%struct.dummy %p) {
+  %a = extractvalue %struct.dummy %p, 1
+  ret half %a
+}
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/ARM/fp16.ll b/test/CodeGen/ARM/fp16.ll
index 5a926acc5430..25fbf9070cb6 100644
--- a/test/CodeGen/ARM/fp16.ll
+++ b/test/CodeGen/ARM/fp16.ll
@@ -16,8 +16,8 @@ define void @foo() nounwind {
 ; CHECK-ARMV8-LABEL: foo:
 ; CHECK-SOFTFLOAT-LABEL: foo:
 entry:
-  %0 = load i16* @x, align 2
-  %1 = load i16* @y, align 2
+  %0 = load i16, i16* @x, align 2
+  %1 = load i16, i16* @y, align 2
   %2 = tail call float @llvm.convert.from.fp16.f32(i16 %0)
 ; CHECK: __gnu_h2f_ieee
 ; CHECK-FP16: vcvtb.f32.f16
diff --git a/test/CodeGen/ARM/fpcmp-opt.ll b/test/CodeGen/ARM/fpcmp-opt.ll
index eab5988e3eb4..45bb6d2f702d 100644
--- a/test/CodeGen/ARM/fpcmp-opt.ll
+++ b/test/CodeGen/ARM/fpcmp-opt.ll
@@ -13,8 +13,8 @@ entry:
 ; CHECK: vcmpe.f32 [[S1]], [[S0]]
 ; CHECK: vmrs APSR_nzcv, fpscr
 ; CHECK: beq
-  %0 = load float* %a
-  %1 = load float* %b
+  %0 = load float, float* %a
+  %1 = load float, float* %b
   %2 = fcmp une float %0, %1
   br i1 %2, label %bb1, label %bb2
 
@@ -41,7 +41,7 @@ entry:
 ; CHECK-NOT: vcmpe.f32
 ; CHECK-NOT: vmrs
 ; CHECK: bne
-  %0 = load double* %a
+  %0 = load double, double* %a
   %1 = fcmp oeq double %0, 0.000000e+00
   br i1 %1, label %bb1, label %bb2
 
@@ -64,7 +64,7 @@ entry:
 ; CHECK-NOT: vcmpe.f32
 ; CHECK-NOT: vmrs
 ; CHECK: bne
-  %0 = load float* %a
+  %0 = load float, float* %a
   %1 = fcmp oeq float %0, 0.000000e+00
   br i1 %1, label %bb1, label %bb2
 
diff --git a/test/CodeGen/ARM/fpmem.ll b/test/CodeGen/ARM/fpmem.ll
index 3a454ed9631c..23fbea911e5e 100644
--- a/test/CodeGen/ARM/fpmem.ll
+++ b/test/CodeGen/ARM/fpmem.ll
@@ -9,7 +9,7 @@ define float @f1(float %a) {
 define float @f2(float* %v, float %u) {
 ; CHECK-LABEL: f2:
 ; CHECK: vldr{{.*}}[
-        %tmp = load float* %v           ; <float> [#uses=1]
+        %tmp = load float, float* %v           ; <float> [#uses=1]
         %tmp1 = fadd float %tmp, %u              ; <float> [#uses=1]
         ret float %tmp1
 }
@@ -17,8 +17,8 @@ define float @f2(float* %v, float %u) {
 define float @f2offset(float* %v, float %u) {
 ; CHECK-LABEL: f2offset:
 ; CHECK: vldr{{.*}}, #4]
-        %addr = getelementptr float* %v, i32 1
-        %tmp = load float* %addr
+        %addr = getelementptr float, float* %v, i32 1
+        %tmp = load float, float* %addr
         %tmp1 = fadd float %tmp, %u
         ret float %tmp1
 }
@@ -26,8 +26,8 @@ define float @f2offset(float* %v, float %u) {
 define float @f2noffset(float* %v, float %u) {
 ; CHECK-LABEL: f2noffset:
 ; CHECK: vldr{{.*}}, #-4]
-        %addr = getelementptr float* %v, i32 -1
-        %tmp = load float* %addr
+        %addr = getelementptr float, float* %v, i32 -1
+        %tmp = load float, float* %addr
         %tmp1 = fadd float %tmp, %u
         ret float %tmp1
 }
diff --git a/test/CodeGen/ARM/fptoint.ll b/test/CodeGen/ARM/fptoint.ll
index f50d0b96fe99..6cbb30b23fbe 100644
--- a/test/CodeGen/ARM/fptoint.ll
+++ b/test/CodeGen/ARM/fptoint.ll
@@ -4,13 +4,13 @@
 @u = weak global i32 0		; <i32*> [#uses=2]
 
 define i32 @foo1(float *%x) {
-        %tmp1 = load float* %x
+        %tmp1 = load float, float* %x
 	%tmp2 = bitcast float %tmp1 to i32
 	ret i32 %tmp2
 }
 
 define i64 @foo2(double *%x) {
-        %tmp1 = load double* %x
+        %tmp1 = load double, double* %x
 	%tmp2 = bitcast double %tmp1 to i64
 	ret i64 %tmp2
 }
diff --git a/test/CodeGen/ARM/frame-register.ll b/test/CodeGen/ARM/frame-register.ll
index e6a55bddaf1c..0cc5005ec488 100644
--- a/test/CodeGen/ARM/frame-register.ll
+++ b/test/CodeGen/ARM/frame-register.ll
@@ -17,12 +17,12 @@ entry:
   %i.addr = alloca i32, align 4
   %j = alloca i32, align 4
   store i32 %i, i32* %i.addr, align 4
-  %0 = load i32* %i.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
   %add = add nsw i32 %0, 1
   store i32 %add, i32* %j, align 4
-  %1 = load i32* %j, align 4
+  %1 = load i32, i32* %j, align 4
   call void @callee(i32 %1)
-  %2 = load i32* %j, align 4
+  %2 = load i32, i32* %j, align 4
   %add1 = add nsw i32 %2, 1
   ret i32 %add1
 }
@@ -30,9 +30,9 @@ entry:
 ; CHECK-ARM: push {r11, lr}
 ; CHECK-ARM: mov r11, sp
 
-; CHECK-THUMB: push {r4, r6, r7, lr}
-; CHECK-THUMB: add r7, sp, #8
+; CHECK-THUMB: push {r7, lr}
+; CHECK-THUMB: add r7, sp, #0
 
 ; CHECK-DARWIN-ARM: push {r7, lr}
-; CHECK-DARWIN-THUMB: push {r4, r7, lr}
+; CHECK-DARWIN-THUMB: push {r7, lr}
 
diff --git a/test/CodeGen/ARM/fusedMAC.ll b/test/CodeGen/ARM/fusedMAC.ll
index e29f291dc2c5..6f6cdc11491e 100644
--- a/test/CodeGen/ARM/fusedMAC.ll
+++ b/test/CodeGen/ARM/fusedMAC.ll
@@ -144,7 +144,7 @@ entry:
 define float @test_fnms_f32(float %a, float %b, float* %c) nounwind readnone ssp {
 ; CHECK: test_fnms_f32
 ; CHECK: vfnms.f32
-  %tmp1 = load float* %c, align 4
+  %tmp1 = load float, float* %c, align 4
   %tmp2 = fsub float -0.0, %tmp1
   %tmp3 = tail call float @llvm.fma.f32(float %a, float %b, float %tmp2) nounwind readnone
   ret float %tmp3 
diff --git a/test/CodeGen/ARM/ghc-tcreturn-lowered.ll b/test/CodeGen/ARM/ghc-tcreturn-lowered.ll
index 623b4220c21f..f34f8f1a66c1 100644
--- a/test/CodeGen/ARM/ghc-tcreturn-lowered.ll
+++ b/test/CodeGen/ARM/ghc-tcreturn-lowered.ll
@@ -15,7 +15,7 @@ define ghccc void @test_direct_tail() {
 define ghccc void @test_indirect_tail() {
 ; CHECK-LABEL: test_indirect_tail:
 ; CHECK: bx {{r[0-9]+}}
-  %func = load void()** @ind_func
-  tail call ghccc void()* %func()
+  %func = load void()*, void()** @ind_func
+  tail call ghccc void() %func()
   ret void
 }
diff --git a/test/CodeGen/ARM/global-merge-1.ll b/test/CodeGen/ARM/global-merge-1.ll
index e5d4def938df..d4d9b0f9d1f3 100644
--- a/test/CodeGen/ARM/global-merge-1.ll
+++ b/test/CodeGen/ARM/global-merge-1.ll
@@ -1,9 +1,12 @@
 ; RUN: llc %s -O0 -o - | FileCheck -check-prefix=NO-MERGE %s
-; RUN: llc %s -O0 -o - -enable-global-merge=false | FileCheck -check-prefix=NO-MERGE %s
-; RUN: llc %s -O0 -o - -enable-global-merge=true | FileCheck -check-prefix=NO-MERGE %s
-; RUN: llc %s -O1 -o - | FileCheck -check-prefix=MERGE %s
-; RUN: llc %s -O1 -o - -enable-global-merge=false | FileCheck -check-prefix=NO-MERGE %s
-; RUN: llc %s -O1 -o - -enable-global-merge=true | FileCheck -check-prefix=MERGE %s
+; RUN: llc %s -O0 -o - -arm-global-merge=false | FileCheck -check-prefix=NO-MERGE %s
+; RUN: llc %s -O0 -o - -arm-global-merge=true | FileCheck -check-prefix=MERGE %s
+; RUN: llc %s -O1 -o - | FileCheck -check-prefix=NO-MERGE %s
+; RUN: llc %s -O1 -o - -arm-global-merge=false | FileCheck -check-prefix=NO-MERGE %s
+; RUN: llc %s -O1 -o - -arm-global-merge=true | FileCheck -check-prefix=MERGE %s
+; RUN: llc %s -O3 -o - | FileCheck -check-prefix=MERGE %s
+; RUN: llc %s -O3 -o - -arm-global-merge=false | FileCheck -check-prefix=NO-MERGE %s
+; RUN: llc %s -O3 -o - -arm-global-merge=true | FileCheck -check-prefix=MERGE %s
 
 ; MERGE-NOT: .zerofill __DATA,__bss,_bar,20,2
 ; MERGE-NOT: .zerofill __DATA,__bss,_baz,20,2
@@ -29,25 +32,25 @@ target triple = "thumbv7-apple-ios3.0.0"
 ; Function Attrs: nounwind ssp
 define internal void @initialize() #0 {
   %1 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
-  store i32 %1, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 0), align 4, !tbaa !1
+  store i32 %1, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 0), align 4, !tbaa !1
   %2 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
-  store i32 %2, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 0), align 4, !tbaa !1
+  store i32 %2, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 0), align 4, !tbaa !1
   %3 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
-  store i32 %3, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 1), align 4, !tbaa !1
+  store i32 %3, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 1), align 4, !tbaa !1
   %4 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
-  store i32 %4, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 1), align 4, !tbaa !1
+  store i32 %4, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 1), align 4, !tbaa !1
   %5 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
-  store i32 %5, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 2), align 4, !tbaa !1
+  store i32 %5, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 2), align 4, !tbaa !1
   %6 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
-  store i32 %6, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 2), align 4, !tbaa !1
+  store i32 %6, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 2), align 4, !tbaa !1
   %7 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
-  store i32 %7, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 3), align 4, !tbaa !1
+  store i32 %7, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 3), align 4, !tbaa !1
   %8 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
-  store i32 %8, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 3), align 4, !tbaa !1
+  store i32 %8, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 3), align 4, !tbaa !1
   %9 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
-  store i32 %9, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 4), align 4, !tbaa !1
+  store i32 %9, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 4), align 4, !tbaa !1
   %10 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
-  store i32 %10, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 4), align 4, !tbaa !1
+  store i32 %10, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 4), align 4, !tbaa !1
   ret void
 }
 
@@ -55,20 +58,20 @@ declare i32 @calc(...) #1
 
 ; Function Attrs: nounwind ssp
 define internal void @calculate() #0 {
-  %1 = load <4 x i32>* bitcast ([5 x i32]* @bar to <4 x i32>*), align 4
-  %2 = load <4 x i32>* bitcast ([5 x i32]* @baz to <4 x i32>*), align 4
+  %1 = load <4 x i32>, <4 x i32>* bitcast ([5 x i32]* @bar to <4 x i32>*), align 4
+  %2 = load <4 x i32>, <4 x i32>* bitcast ([5 x i32]* @baz to <4 x i32>*), align 4
   %3 = mul <4 x i32> %2, %1
   store <4 x i32> %3, <4 x i32>* bitcast ([5 x i32]* @foo to <4 x i32>*), align 4
-  %4 = load i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 4), align 4, !tbaa !1
-  %5 = load i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 4), align 4, !tbaa !1
+  %4 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 4), align 4, !tbaa !1
+  %5 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 4), align 4, !tbaa !1
   %6 = mul nsw i32 %5, %4
-  store i32 %6, i32* getelementptr inbounds ([5 x i32]* @foo, i32 0, i32 4), align 4, !tbaa !1
+  store i32 %6, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i32 0, i32 4), align 4, !tbaa !1
   ret void
 }
 
 ; Function Attrs: nounwind readnone ssp
 define internal i32* @returnFoo() #2 {
-  ret i32* getelementptr inbounds ([5 x i32]* @foo, i32 0, i32 0)
+  ret i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i32 0, i32 0)
 }
 
 attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/CodeGen/ARM/global-merge-addrspace.ll b/test/CodeGen/ARM/global-merge-addrspace.ll
index 0efa690bde28..8f40a4c28a76 100644
--- a/test/CodeGen/ARM/global-merge-addrspace.ll
+++ b/test/CodeGen/ARM/global-merge-addrspace.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=thumb-apple-darwin -arm-global-merge -global-merge-group-by-use=false | FileCheck %s
 ; Test the GlobalMerge pass. Check that the pass does not crash when using
 ; multiple address spaces.
 
@@ -7,6 +7,6 @@
 @g2 = internal addrspace(1) global i32 2
 
 
-; CHECK: _MergedGlobals1:
+; CHECK: _MergedGlobals.1:
 @g3 = internal addrspace(2) global i32 3
 @g4 = internal addrspace(2) global i32 4
diff --git a/test/CodeGen/ARM/global-merge.ll b/test/CodeGen/ARM/global-merge.ll
index f88e92796196..e8c8289098a7 100644
--- a/test/CodeGen/ARM/global-merge.ll
+++ b/test/CodeGen/ARM/global-merge.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumb-apple-darwin -global-merge-on-const=true | FileCheck %s
+; RUN: llc < %s -mtriple=thumb-apple-darwin -arm-global-merge -global-merge-group-by-use=false -global-merge-on-const=true | FileCheck %s
 ; Test the ARMGlobalMerge pass.  Use -march=thumb because it has a small
 ; value for the maximum offset (127).
 
@@ -59,16 +59,16 @@ declare void @__cxa_end_catch()
 ; Make sure that the complete variable fits within the range of the maximum
 ; offset.  Having the starting offset in range is not sufficient.
 ; When this works properly, @g3 is placed in a separate chunk of merged globals.
-; CHECK: _MergedGlobals1:
+; CHECK: _MergedGlobals.1:
 @g3 = internal global [30 x i32] [ i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10 ], align 4
 
 ; Global variables that can be placed in BSS should be kept together in a
 ; separate pool of merged globals.
-; CHECK: _MergedGlobals2
+; CHECK: _MergedGlobals.2
 @g4 = internal global i32 0
 @g5 = internal global i32 0
 
 ; Global variables that are constant can be merged together
-; CHECK: _MergedGlobals3
+; CHECK: _MergedGlobals.3
 @g6 = internal constant [12 x i32] zeroinitializer, align 4
 @g7 = internal constant [12 x i32] zeroinitializer, align 4
diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll
index 2c599bf011a7..bab96dadce55 100644
--- a/test/CodeGen/ARM/globals.ll
+++ b/test/CodeGen/ARM/globals.ll
@@ -6,7 +6,7 @@
 @G = external global i32
 
 define i32 @test1() {
-	%tmp = load i32* @G
+	%tmp = load i32, i32* @G
 	ret i32 %tmp
 }
 
diff --git a/test/CodeGen/ARM/gv-stubs-crash.ll b/test/CodeGen/ARM/gv-stubs-crash.ll
index c4c4180a6200..6e82afeacf88 100644
--- a/test/CodeGen/ARM/gv-stubs-crash.ll
+++ b/test/CodeGen/ARM/gv-stubs-crash.ll
@@ -4,7 +4,7 @@
 @Exn = external hidden unnamed_addr constant { i8*, i8* }
 
 define hidden void @func(i32* %this, i32* %e) optsize align 2 {
-  %e.ld = load i32* %e, align 4
+  %e.ld = load i32, i32* %e, align 4
   %inv = invoke zeroext i1 @func2(i32* %this, i32 %e.ld) optsize
           to label %ret unwind label %lpad
 
diff --git a/test/CodeGen/ARM/half.ll b/test/CodeGen/ARM/half.ll
index 10cebb38c565..b40eaf638519 100644
--- a/test/CodeGen/ARM/half.ll
+++ b/test/CodeGen/ARM/half.ll
@@ -6,7 +6,7 @@ define void @test_load_store(half* %in, half* %out) {
 ; CHECK-LABEL: test_load_store:
 ; CHECK: ldrh [[TMP:r[0-9]+]], [r0]
 ; CHECK: strh [[TMP]], [r1]
-  %val = load half* %in
+  %val = load half, half* %in
   store half %val, half* %out
   ret void
 }
@@ -14,7 +14,7 @@ define void @test_load_store(half* %in, half* %out) {
 define i16 @test_bitcast_from_half(half* %addr) {
 ; CHECK-LABEL: test_bitcast_from_half:
 ; CHECK: ldrh r0, [r0]
-  %val = load half* %addr
+  %val = load half, half* %addr
   %val_int = bitcast half %val to i16
   ret i16 %val_int
 }
@@ -30,10 +30,10 @@ define void @test_bitcast_to_half(half* %addr, i16 %in) {
 define float @test_extend32(half* %addr) {
 ; CHECK-LABEL: test_extend32:
 
-; CHECK-OLD: b.w ___gnu_h2f_ieee
+; CHECK-OLD: b.w ___extendhfsf2
 ; CHECK-F16: vcvtb.f32.f16
 ; CHECK-V8: vcvtb.f32.f16
-  %val16 = load half* %addr
+  %val16 = load half, half* %addr
   %val32 = fpext half %val16 to float
   ret float %val32
 }
@@ -41,12 +41,12 @@ define float @test_extend32(half* %addr) {
 define double @test_extend64(half* %addr) {
 ; CHECK-LABEL: test_extend64:
 
-; CHECK-OLD: blx ___gnu_h2f_ieee
+; CHECK-OLD: blx ___extendhfsf2
 ; CHECK-OLD: vcvt.f64.f32
 ; CHECK-F16: vcvtb.f32.f16
 ; CHECK-F16: vcvt.f64.f32
 ; CHECK-V8: vcvtb.f64.f16
-  %val16 = load half* %addr
+  %val16 = load half, half* %addr
   %val32 = fpext half %val16 to double
   ret double %val32
 }
@@ -54,7 +54,7 @@ define double @test_extend64(half* %addr) {
 define void @test_trunc32(float %in, half* %addr) {
 ; CHECK-LABEL: test_trunc32:
 
-; CHECK-OLD: blx ___gnu_f2h_ieee
+; CHECK-OLD: blx ___truncsfhf2
 ; CHECK-F16: vcvtb.f16.f32
 ; CHECK-V8: vcvtb.f16.f32
   %val16 = fptrunc float %in to half
diff --git a/test/CodeGen/ARM/hello.ll b/test/CodeGen/ARM/hello.ll
index d2685854dba0..08e6104bbcf6 100644
--- a/test/CodeGen/ARM/hello.ll
+++ b/test/CodeGen/ARM/hello.ll
@@ -10,7 +10,7 @@
 @str = internal constant [12 x i8] c"Hello World\00"
 
 define i32 @main() {
-	%tmp = call i32 @puts( i8* getelementptr ([12 x i8]* @str, i32 0, i64 0) )		; <i32> [#uses=0]
+	%tmp = call i32 @puts( i8* getelementptr ([12 x i8], [12 x i8]* @str, i32 0, i64 0) )		; <i32> [#uses=0]
 	ret i32 0
 }
 
diff --git a/test/CodeGen/ARM/hidden-vis-2.ll b/test/CodeGen/ARM/hidden-vis-2.ll
index 18d38d40072c..a104f354295d 100644
--- a/test/CodeGen/ARM/hidden-vis-2.ll
+++ b/test/CodeGen/ARM/hidden-vis-2.ll
@@ -7,6 +7,6 @@ entry:
 ; CHECK-LABEL: t:
 ; CHECK: ldr
 ; CHECK-NEXT: ldr
-	%0 = load i32* @x, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* @x, align 4		; <i32> [#uses=1]
 	ret i32 %0
 }
diff --git a/test/CodeGen/ARM/hidden-vis-3.ll b/test/CodeGen/ARM/hidden-vis-3.ll
index 3bc3312e9c4e..0cf2f779704d 100644
--- a/test/CodeGen/ARM/hidden-vis-3.ll
+++ b/test/CodeGen/ARM/hidden-vis-3.ll
@@ -10,8 +10,8 @@ entry:
 ; CHECK: LCPI0_1:
 ; CHECK-NEXT: .long _y
 
-	%0 = load i32* @x, align 4		; <i32> [#uses=1]
-	%1 = load i32* @y, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* @x, align 4		; <i32> [#uses=1]
+	%1 = load i32, i32* @y, align 4		; <i32> [#uses=1]
 	%2 = add i32 %1, %0		; <i32> [#uses=1]
 	ret i32 %2
 }
diff --git a/test/CodeGen/ARM/ifconv-kills.ll b/test/CodeGen/ARM/ifconv-kills.ll
index de80c927cea5..3a458e481936 100644
--- a/test/CodeGen/ARM/ifconv-kills.ll
+++ b/test/CodeGen/ARM/ifconv-kills.ll
@@ -10,15 +10,15 @@ entry:
 ; present something which can be easily if-converted
 if.then:
   ; %R0 should be killed here
-  %valt = load i32* %ptr, align 4
+  %valt = load i32, i32* %ptr, align 4
   br label %return
 
 if.else:
   ; %R0 should be killed here, however after if-conversion the %R0 kill
   ; has to be removed because if.then will follow after this and still
   ; read it.
-  %addr = getelementptr inbounds i32* %ptr, i32 4
-  %vale = load i32* %addr, align 4
+  %addr = getelementptr inbounds i32, i32* %ptr, i32 4
+  %vale = load i32, i32* %addr, align 4
   br label %return
 
 return:
diff --git a/test/CodeGen/ARM/ifconv-regmask.ll b/test/CodeGen/ARM/ifconv-regmask.ll
index d45f65f9567f..2144ca6e4074 100644
--- a/test/CodeGen/ARM/ifconv-regmask.ll
+++ b/test/CodeGen/ARM/ifconv-regmask.ll
@@ -7,7 +7,7 @@
 ; Function Attrs: nounwind ssp
 define i32 @sfu() {
 entry:
-  %bf.load = load i32* getelementptr inbounds (%union.opcode* @opcode, i32 0, i32 0), align 4
+  %bf.load = load i32, i32* getelementptr inbounds (%union.opcode, %union.opcode* @opcode, i32 0, i32 0), align 4
   %bf.lshr = lshr i32 %bf.load, 26
   %bf.clear = and i32 %bf.lshr, 7
   switch i32 %bf.clear, label %return [
diff --git a/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll b/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
index f76fd302774b..4e6924fe5b6b 100644
--- a/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
+++ b/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
@@ -50,7 +50,7 @@ if.else.i.i:
   br label %_ZN1M6spliceEv.exit
 
 _ZN1M6spliceEv.exit:
-  %LIS = getelementptr inbounds %classK* %this, i32 0, i32 1
+  %LIS = getelementptr inbounds %classK, %classK* %this, i32 0, i32 1
   call void @_ZN1F10handleMoveEb(%classF* %LIS, i1 zeroext false)
   unreachable
 }
diff --git a/test/CodeGen/ARM/ifcvt-branch-weight.ll b/test/CodeGen/ARM/ifcvt-branch-weight.ll
index 2d12a899f4b3..41d78e53acc7 100644
--- a/test/CodeGen/ARM/ifcvt-branch-weight.ll
+++ b/test/CodeGen/ARM/ifcvt-branch-weight.ll
@@ -3,16 +3,16 @@
 %struct.S = type { i8* (i8*)*, [1 x i8] }
 define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly {
 entry:
-  %0 = getelementptr inbounds %struct.S* %x, i32 0, i32 1, i32 0
-  %1 = load i8* %0, align 1
+  %0 = getelementptr inbounds %struct.S, %struct.S* %x, i32 0, i32 1, i32 0
+  %1 = load i8, i8* %0, align 1
   %2 = zext i8 %1 to i32
   %3 = and i32 %2, 112
   %4 = icmp eq i32 %3, 0
   br i1 %4, label %return, label %bb
 
 bb:
-  %5 = getelementptr inbounds %struct.S* %y, i32 0, i32 1, i32 0
-  %6 = load i8* %5, align 1
+  %5 = getelementptr inbounds %struct.S, %struct.S* %y, i32 0, i32 1, i32 0
+  %6 = load i8, i8* %5, align 1
   %7 = zext i8 %6 to i32
   %8 = and i32 %7, 112
   %9 = icmp eq i32 %8, 0
diff --git a/test/CodeGen/ARM/ifcvt-dead-def.ll b/test/CodeGen/ARM/ifcvt-dead-def.ll
new file mode 100644
index 000000000000..77a3f5c0961f
--- /dev/null
+++ b/test/CodeGen/ARM/ifcvt-dead-def.ll
@@ -0,0 +1,55 @@
+; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7-unknown-unknown"
+
+%struct.ref_s = type { %union.v, i16, i16 }
+%union.v = type { i32 }
+%struct.gs_color_s = type { i16, i16, i16, i16, i8, i8 }
+
+; In this case, the if converter was cloning the return instruction so that we had
+;   r2<def> = ...
+;   return [pred] r2<dead,def>
+;   ldr <r2, kill>
+;   return
+; The problem here was that the dead def on the first return was making the machine verifier
+; think that the load read from an undefined register.  We need to remove the dead flag from
+; the return, and also add an implicit use of the prior value of r2.
+
+; CHECK: ldrh
+
+; Function Attrs: minsize nounwind optsize ssp
+define i32 @test(%struct.ref_s* %pref1, %struct.ref_s* %pref2, %struct.gs_color_s** %tmp152) #0 {
+bb:
+  %nref = alloca %struct.ref_s, align 4
+  %tmp46 = call %struct.ref_s* @name_string_ref(%struct.ref_s* %pref1, %struct.ref_s* %nref) #2
+  %tmp153 = load %struct.gs_color_s*, %struct.gs_color_s** %tmp152, align 4
+  %tmp154 = bitcast %struct.ref_s* %pref2 to %struct.gs_color_s**
+  %tmp155 = load %struct.gs_color_s*, %struct.gs_color_s** %tmp154, align 4
+  %tmp162 = getelementptr inbounds %struct.gs_color_s, %struct.gs_color_s* %tmp153, i32 0, i32 1
+  %tmp163 = load i16, i16* %tmp162, align 2
+  %tmp164 = getelementptr inbounds %struct.gs_color_s, %struct.gs_color_s* %tmp155, i32 0, i32 1
+  %tmp165 = load i16, i16* %tmp164, align 2
+  %tmp166 = icmp eq i16 %tmp163, %tmp165
+  br i1 %tmp166, label %bb167, label %bb173
+
+bb167:                                            ; preds = %bb
+  %tmp168 = getelementptr inbounds %struct.gs_color_s, %struct.gs_color_s* %tmp153, i32 0, i32 2
+  %tmp169 = load i16, i16* %tmp168, align 2
+  %tmp170 = getelementptr inbounds %struct.gs_color_s, %struct.gs_color_s* %tmp155, i32 0, i32 2
+  %tmp171 = load i16, i16* %tmp170, align 2
+  %tmp172 = icmp eq i16 %tmp169, %tmp171
+  br label %bb173
+
+bb173:                                            ; preds = %bb167, %bb
+  %tmp174 = phi i1 [ false, %bb ], [ %tmp172, %bb167 ]
+  %tmp175 = zext i1 %tmp174 to i32
+  ret i32 %tmp175
+}
+
+; Function Attrs: minsize optsize
+declare %struct.ref_s* @name_string_ref(%struct.ref_s*, %struct.ref_s*) #1
+
+attributes #0 = { minsize nounwind optsize }
+attributes #1 = { minsize optsize }
+attributes #2 = { minsize nounwind optsize }
diff --git a/test/CodeGen/ARM/ifcvt-iter-indbr.ll b/test/CodeGen/ARM/ifcvt-iter-indbr.ll
new file mode 100644
index 000000000000..75e9d77d7920
--- /dev/null
+++ b/test/CodeGen/ARM/ifcvt-iter-indbr.ll
@@ -0,0 +1,56 @@
+; RUN: llc < %s -mtriple thumbv7s-apple-darwin  -asm-verbose=false | FileCheck %s
+
+declare i32 @foo(i32)
+declare i8* @bar(i32, i8*, i8*)
+
+; Verify that we don't try to iteratively re-ifconvert a block with a
+; (predicated) indirectbr terminator.
+; If we do, we would ignore its fallthrough successor.
+
+
+; CHECK-LABEL: test:
+; CHECK:       cmp {{.*}}, #21
+; CHECK-NEXT:  itt eq
+; CHECK-NEXT:  streq.w
+; CHECK-NEXT:  moveq pc
+; CHECK-NEXT: LBB{{[0-9_]+}}:
+; CHECK-NEXT:  cmp {{.*}}, #42
+; CHECK-NEXT:  itt ne
+; CHECK-NEXT:  strne.w
+; CHECK-NEXT:  movne pc
+; CHECK-NEXT: Ltmp
+; CHECK-NEXT: LBB0_2:
+; CHECK-NEXT:  movw r0, #1234
+; CHECK-NEXT:  b [[FOOCALL:LBB[0-9_]+]]
+; CHECK-NEXT: Ltmp
+; CHECK-NEXT: LBB{{[0-9_]+}}:
+; CHECK-NEXT:  movw r0, #4567
+; CHECK-NEXT: [[FOOCALL]]:
+; CHECK-NEXT:  blx _foo
+
+define i32 @test(i32 %a, i32 %a2, i32* %p, i32* %p2) {
+entry:
+  %dst1 = call i8* @bar(i32 1, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2))
+  %dst2 = call i8* @bar(i32 2, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2))
+  %dst3 = call i8* @bar(i32 3, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2))
+  %cc1 = icmp eq i32 %a, 21
+  br i1 %cc1, label %cc1t, label %cc1f
+
+cc1t:
+  store i32 %a, i32* %p
+  indirectbr i8* %dst3, [label %bb1, label %bb2]
+
+cc1f:
+  %cc2 = icmp ne i32 %a2, 42
+  br i1 %cc2, label %cc2t, label %bb1
+cc2t:
+  store i32 %a, i32* %p2
+  indirectbr i8* %dst1, [label %bb1, label %bb2]
+
+bb1:
+  %ret_bb1 = call i32 @foo(i32 1234)
+  ret i32 %ret_bb1
+bb2:
+  %ret_bb2 = call i32 @foo(i32 4567)
+  ret i32 %ret_bb2
+}
diff --git a/test/CodeGen/ARM/ifcvt-regmask-noreturn.ll b/test/CodeGen/ARM/ifcvt-regmask-noreturn.ll
new file mode 100644
index 000000000000..cf04fc90504a
--- /dev/null
+++ b/test/CodeGen/ARM/ifcvt-regmask-noreturn.ll
@@ -0,0 +1,45 @@
+; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7s-apple-ios8.0.0"
+
+@debw = external global i8*, align 4
+
+; This test ensures that the stack_chk call correctly puts implicit uses/defs for the regsiters
+; live across it when if converting.  This will be R0 which is passed to the call to free at the end
+; of the function.
+; Prior to this change, the stack_chk call (which does not return) would clobber R0 in its regmask,
+; leading to verifier errors because the later use of R0 in free() is not live.
+
+; CHECK-LABEL: @test
+; CHECK: stack_chk_fail
+
+; Function Attrs: ssp
+define void @test(i32 %argc, i8** nocapture readonly %argv, i32* %ptr, i32 %val) #0 {
+entry:
+  %count.i = alloca [256 x i32], align 4
+  %cmp284.i = icmp eq i32 %val, 0
+  br i1 %cmp284.i, label %for.end31.i, label %for.body21.i
+
+for.body21.i:                                     ; preds = %entry
+  %arrayidx23.i = getelementptr inbounds [256 x i32], [256 x i32]* %count.i, i32 0, i32 1
+  %tmp20 = load i32, i32* %arrayidx23.i, align 4, !tbaa !0
+  store i32 %tmp20, i32* %ptr, align 4, !tbaa !0
+  br label %for.end31.i
+
+for.end31.i:                                      ; preds = %for.body21.i, %entry
+  %tmp21 = load i8*, i8** @debw, align 4, !tbaa !4
+  tail call void @free(i8* %tmp21)
+  ret void
+}
+
+declare void @free(i8* nocapture)
+
+attributes #0 = { ssp "stack-protector-buffer-size"="8" }
+
+!0 = !{!1, !1, i64 0}
+!1 = !{!"int", !2, i64 0}
+!2 = !{!"omnipotent char", !3, i64 0}
+!3 = !{!"Simple C/C++ TBAA"}
+!4 = !{!5, !5, i64 0}
+!5 = !{!"any pointer", !2, i64 0}
diff --git a/test/CodeGen/ARM/ifcvt11.ll b/test/CodeGen/ARM/ifcvt11.ll
index dba8a3f1a6af..eae41e21c610 100644
--- a/test/CodeGen/ARM/ifcvt11.ll
+++ b/test/CodeGen/ARM/ifcvt11.ll
@@ -21,10 +21,10 @@ bb:                                               ; preds = %bb4, %bb.nph
 ; CHECK: vmrs APSR_nzcv, fpscr
   %r.19 = phi i32 [ 0, %bb.nph ], [ %r.0, %bb4 ]
   %n.08 = phi i32 [ 0, %bb.nph ], [ %10, %bb4 ]
-  %scevgep10 = getelementptr inbounds %struct.xyz_t* %p, i32 %n.08, i32 0
-  %scevgep11 = getelementptr %struct.xyz_t* %p, i32 %n.08, i32 1
-  %3 = load double* %scevgep10, align 4
-  %4 = load double* %scevgep11, align 4
+  %scevgep10 = getelementptr inbounds %struct.xyz_t, %struct.xyz_t* %p, i32 %n.08, i32 0
+  %scevgep11 = getelementptr %struct.xyz_t, %struct.xyz_t* %p, i32 %n.08, i32 1
+  %3 = load double, double* %scevgep10, align 4
+  %4 = load double, double* %scevgep11, align 4
   %5 = fcmp uge double %3, %4
   br i1 %5, label %bb3, label %bb1
 
@@ -34,8 +34,8 @@ bb1:                                              ; preds = %bb
 ; CHECK-NOT: vmrsmi
 ; CHECK: vcmpe.f64
 ; CHECK: vmrs APSR_nzcv, fpscr
-  %scevgep12 = getelementptr %struct.xyz_t* %p, i32 %n.08, i32 2
-  %6 = load double* %scevgep12, align 4
+  %scevgep12 = getelementptr %struct.xyz_t, %struct.xyz_t* %p, i32 %n.08, i32 2
+  %6 = load double, double* %scevgep12, align 4
   %7 = fcmp uge double %3, %6
   br i1 %7, label %bb3, label %bb2
 
diff --git a/test/CodeGen/ARM/ifcvt3.ll b/test/CodeGen/ARM/ifcvt3.ll
index 5da63dc5f022..e53d989ad529 100644
--- a/test/CodeGen/ARM/ifcvt3.ll
+++ b/test/CodeGen/ARM/ifcvt3.ll
@@ -4,8 +4,8 @@
 
 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
 ; CHECK-LABEL: t1:
-; CHECK: cmp r2, #1
-; CHECK: cmpne r2, #7
+; CHECK: cmp r2, #7
+; CHECK: cmpne r2, #1
 	switch i32 %c, label %cond_next [
 		 i32 1, label %cond_true
 		 i32 7, label %cond_true
diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll
index 31e3e00c468e..3aa2139cc03a 100644
--- a/test/CodeGen/ARM/ifcvt5.ll
+++ b/test/CodeGen/ARM/ifcvt5.ll
@@ -6,7 +6,7 @@
 
 define void @foo(i32 %a) {
 entry:
-	%tmp = load i32** @x		; <i32*> [#uses=1]
+	%tmp = load i32*, i32** @x		; <i32*> [#uses=1]
 	store i32 %a, i32* %tmp
 	ret void
 }
diff --git a/test/CodeGen/ARM/ifcvt6.ll b/test/CodeGen/ARM/ifcvt6.ll
index a00dedaee670..78901930e4b2 100644
--- a/test/CodeGen/ARM/ifcvt6.ll
+++ b/test/CodeGen/ARM/ifcvt6.ll
@@ -10,7 +10,7 @@ entry:
 	br i1 %tmp7, label %cond_true, label %UnifiedReturnBlock
 
 cond_true:		; preds = %entry
-	%tmp10 = call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp10 = call i32 (...) @bar( )		; <i32> [#uses=0]
 	ret void
 
 UnifiedReturnBlock:		; preds = %entry
diff --git a/test/CodeGen/ARM/ifcvt7.ll b/test/CodeGen/ARM/ifcvt7.ll
index 476ed4d47c64..e0d2b7cffb44 100644
--- a/test/CodeGen/ARM/ifcvt7.ll
+++ b/test/CodeGen/ARM/ifcvt7.ll
@@ -11,9 +11,9 @@ entry:
 	br label %tailrecurse
 
 tailrecurse:		; preds = %bb, %entry
-	%tmp6 = load %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=1]
-	%tmp9 = load %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=2]
-	%tmp12 = load %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=1]
+	%tmp6 = load %struct.quad_struct*, %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=1]
+	%tmp9 = load %struct.quad_struct*, %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=2]
+	%tmp12 = load %struct.quad_struct*, %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=1]
 	%tmp14 = icmp eq %struct.quad_struct* null, null		; <i1> [#uses=1]
 	%tmp17 = icmp eq %struct.quad_struct* %tmp6, null		; <i1> [#uses=1]
 	%tmp23 = icmp eq %struct.quad_struct* %tmp9, null		; <i1> [#uses=1]
diff --git a/test/CodeGen/ARM/illegal-vector-bitcast.ll b/test/CodeGen/ARM/illegal-vector-bitcast.ll
index 7208fffbcc85..766b3d7ca433 100644
--- a/test/CodeGen/ARM/illegal-vector-bitcast.ll
+++ b/test/CodeGen/ARM/illegal-vector-bitcast.ll
@@ -3,10 +3,10 @@
 
 define void @foo(<8 x float>* %f, <8 x float>* %g, <4 x i64>* %y)
 {
-  %h = load <8 x float>* %f
+  %h = load <8 x float>, <8 x float>* %f
   %i = fmul <8 x float> %h, <float 0x3FF19999A0000000, float 0x400A666660000000, float 0x40119999A0000000, float 0x40159999A0000000, float 0.5, float 0x3FE3333340000000, float 0x3FE6666660000000, float 0x3FE99999A0000000>
   %m = bitcast <8 x float> %i to <4 x i64>
-  %z = load <4 x i64>* %y
+  %z = load <4 x i64>, <4 x i64>* %y
   %n = mul <4 x i64> %z, %m
   %p = bitcast <4 x i64> %n to <8 x float>
   store <8 x float> %p, <8 x float>* %g
diff --git a/test/CodeGen/ARM/indirect-reg-input.ll b/test/CodeGen/ARM/indirect-reg-input.ll
index 17f6a9c96f68..e82e1dee9428 100644
--- a/test/CodeGen/ARM/indirect-reg-input.ll
+++ b/test/CodeGen/ARM/indirect-reg-input.ll
@@ -8,7 +8,7 @@
 
 define void @switch_to_stack(%struct.my_stack* %stack) nounwind {
 entry:
-  %regs = getelementptr inbounds %struct.my_stack* %stack, i32 0, i32 0
+  %regs = getelementptr inbounds %struct.my_stack, %struct.my_stack* %stack, i32 0, i32 0
   tail call void asm "\0A", "=*r,*0"(%struct.myjmp_buf* %regs, %struct.myjmp_buf* %regs)
   ret void
 }
diff --git a/test/CodeGen/ARM/indirectbr-2.ll b/test/CodeGen/ARM/indirectbr-2.ll
index 0c41da658009..ca068db1db0e 100644
--- a/test/CodeGen/ARM/indirectbr-2.ll
+++ b/test/CodeGen/ARM/indirectbr-2.ll
@@ -15,7 +15,7 @@
 
 define i32 @func() nounwind ssp {
   %1 = alloca i32, align 4
-  %2 = load i32* @foo, align 4
+  %2 = load i32, i32* @foo, align 4
   %3 = icmp eq i32 %2, 34879
   br label %4
 
@@ -23,17 +23,17 @@ define i32 @func() nounwind ssp {
   %5 = zext i1 %3 to i32
   %6 = mul i32 %5, 287
   %7 = add i32 %6, 2
-  %8 = getelementptr [2 x i32]* @DWJumpTable2808, i32 0, i32 %5
-  %9 = load i32* %8
+  %8 = getelementptr [2 x i32], [2 x i32]* @DWJumpTable2808, i32 0, i32 %5
+  %9 = load i32, i32* %8
   %10 = add i32 %9, ptrtoint (i8* blockaddress(@func, %4) to i32)
   %11 = inttoptr i32 %10 to i8*
-  %12 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([45 x i8]* @0, i32 0, i32 0))
+  %12 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([45 x i8], [45 x i8]* @0, i32 0, i32 0))
   indirectbr i8* %11, [label %13, label %14]
 
 ; <label>:13                                      ; preds = %4
   %tmp14 = phi i32 [ %7, %4 ]
   store i32 23958, i32* @foo, align 4
-  %tmp15 = load i32* %1, align 4
+  %tmp15 = load i32, i32* %1, align 4
   %tmp16 = icmp eq i32 %tmp15, 0
   %tmp17 = zext i1 %tmp16 to i32
   %tmp21 = add i32 %tmp17, %tmp14
diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll
index 7c49cb310f39..d15ef14b4493 100644
--- a/test/CodeGen/ARM/indirectbr.ll
+++ b/test/CodeGen/ARM/indirectbr.ll
@@ -16,7 +16,7 @@ entry:
 ; THUMB: [[NEXTADDR_PCBASE:LPC0_[0-9]]]:
 ; THUMB: add r[[NEXTADDR_REG]], pc
 
-  %0 = load i8** @nextaddr, align 4               ; <i8*> [#uses=2]
+  %0 = load i8*, i8** @nextaddr, align 4               ; <i8*> [#uses=2]
   %1 = icmp eq i8* %0, null                       ; <i1> [#uses=1]
 ; indirect branch gets duplicated here
 ; ARM: bx
@@ -31,8 +31,8 @@ bb2:                                              ; preds = %entry, %bb3
   indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
 
 bb3:                                              ; preds = %entry
-  %2 = getelementptr inbounds [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1]
-  %gotovar.4.0.pre = load i8** %2, align 4        ; <i8*> [#uses=1]
+  %2 = getelementptr inbounds [5 x i8*], [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1]
+  %gotovar.4.0.pre = load i8*, i8** %2, align 4        ; <i8*> [#uses=1]
   br label %bb2
 
 L5:                                               ; preds = %bb2
diff --git a/test/CodeGen/ARM/inline-diagnostics.ll b/test/CodeGen/ARM/inline-diagnostics.ll
index 0276abf2f5fa..3f5b73c5a211 100644
--- a/test/CodeGen/ARM/inline-diagnostics.ll
+++ b/test/CodeGen/ARM/inline-diagnostics.ll
@@ -8,8 +8,8 @@ define float @inline_func(float %f1, float %f2) #0 {
   %c2 = alloca %struct.float4, align 4
   %c3 = alloca %struct.float4, align 4
   call void asm sideeffect "vmul.f32 ${2:q}, ${0:q}, ${1:q}", "=*r,=*r,*w"(%struct.float4* %c1, %struct.float4* %c2, %struct.float4* %c3) #1, !srcloc !1
-  %x = getelementptr inbounds %struct.float4* %c3, i32 0, i32 0
-  %1 = load float* %x, align 4
+  %x = getelementptr inbounds %struct.float4, %struct.float4* %c3, i32 0, i32 0
+  %1 = load float, float* %x, align 4
   ret float %1
 }
 
diff --git a/test/CodeGen/ARM/inlineasm-64bit.ll b/test/CodeGen/ARM/inlineasm-64bit.ll
index d098a4383bc6..8e747c5eb650 100644
--- a/test/CodeGen/ARM/inlineasm-64bit.ll
+++ b/test/CodeGen/ARM/inlineasm-64bit.ll
@@ -35,7 +35,7 @@ entry:
 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
 
   tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
-  %incdec.ptr = getelementptr inbounds i64* %p, i32 1
+  %incdec.ptr = getelementptr inbounds i64, i64* %p, i32 1
   tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
   tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
   ret void
diff --git a/test/CodeGen/ARM/interrupt-attr.ll b/test/CodeGen/ARM/interrupt-attr.ll
index c6da09d156b7..43bd5815a558 100644
--- a/test/CodeGen/ARM/interrupt-attr.ll
+++ b/test/CodeGen/ARM/interrupt-attr.ll
@@ -35,7 +35,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" {
   ; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to
   ; appropriate sentinel so no special return needed).
 ; CHECK-M-LABEL: irq_fn:
-; CHECK-M: push.w {r4, r10, r11, lr}
+; CHECK-M: push.w {r4, r7, r11, lr}
 ; CHECK-M: add.w r11, sp, #8
 ; CHECK-M: mov r4, sp
 ; CHECK-M: bfc r4, #0, #3
@@ -43,7 +43,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" {
 ; CHECK-M: bl _bar
 ; CHECK-M: sub.w r4, r11, #8
 ; CHECK-M: mov sp, r4
-; CHECK-M: pop.w {r4, r10, r11, pc}
+; CHECK-M: pop.w {r4, r7, r11, pc}
 
   call arm_aapcscc void @bar()
   ret void
@@ -65,7 +65,7 @@ define arm_aapcscc void @fiq_fn() alignstack(8) "interrupt"="FIQ" {
 
 ; CHECK-A-THUMB-LABEL: fiq_fn:
 ; CHECK-M-LABEL: fiq_fn:
-  %val = load volatile [16 x i32]* @bigvar
+  %val = load volatile [16 x i32], [16 x i32]* @bigvar
   store volatile [16 x i32] %val, [16 x i32]* @bigvar
   ret void
 }
@@ -81,7 +81,7 @@ define arm_aapcscc void @swi_fn() alignstack(8) "interrupt"="SWI" {
 ; CHECK-A: pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr}
 ; CHECK-A: subs pc, lr, #0
 
-  %val = load volatile [16 x i32]* @bigvar
+  %val = load volatile [16 x i32], [16 x i32]* @bigvar
   store volatile [16 x i32] %val, [16 x i32]* @bigvar
   ret void
 }
@@ -126,8 +126,8 @@ define arm_aapcscc void @floating_fn() alignstack(8) "interrupt"="IRQ" {
 ; CHECK-A-NOT: vstr
 ; CHECK-A-NOT: vstm
 ; CHECK-A: vadd.f64 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
-  %lhs = load volatile double* @var
-  %rhs = load volatile double* @var
+  %lhs = load volatile double, double* @var
+  %rhs = load volatile double, double* @var
   %sum = fadd double %lhs, %rhs
   store double %sum, double* @var
   ret void
diff --git a/test/CodeGen/ARM/intrinsics-crypto.ll b/test/CodeGen/ARM/intrinsics-crypto.ll
index 96413d341e4c..6e5efd85a347 100644
--- a/test/CodeGen/ARM/intrinsics-crypto.ll
+++ b/test/CodeGen/ARM/intrinsics-crypto.ll
@@ -1,8 +1,8 @@
 ; RUN: llc < %s -mtriple=armv8 -mattr=+crypto | FileCheck %s
 
 define arm_aapcs_vfpcc <16 x i8> @test_aesde(<16 x i8>* %a, <16 x i8> *%b) {
-  %tmp = load <16 x i8>* %a
-  %tmp2 = load <16 x i8>* %b
+  %tmp = load <16 x i8>, <16 x i8>* %a
+  %tmp2 = load <16 x i8>, <16 x i8>* %b
   %tmp3 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %tmp, <16 x i8> %tmp2)
   ; CHECK: aesd.8 q{{[0-9]+}}, q{{[0-9]+}}
   %tmp4 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %tmp3, <16 x i8> %tmp2)
@@ -15,9 +15,9 @@ define arm_aapcs_vfpcc <16 x i8> @test_aesde(<16 x i8>* %a, <16 x i8> *%b) {
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_sha(<4 x i32> *%a, <4 x i32> *%b, <4 x i32> *%c) {
-  %tmp = load <4 x i32>* %a
-  %tmp2 = load <4 x i32>* %b
-  %tmp3 = load <4 x i32>* %c
+  %tmp = load <4 x i32>, <4 x i32>* %a
+  %tmp2 = load <4 x i32>, <4 x i32>* %b
+  %tmp3 = load <4 x i32>, <4 x i32>* %c
   %scalar = extractelement <4 x i32> %tmp, i32 0
   %resscalar = call i32 @llvm.arm.neon.sha1h(i32 %scalar)
   %res1 = insertelement <4 x i32> undef, i32 %resscalar, i32 0
diff --git a/test/CodeGen/ARM/intrinsics-memory-barrier.ll b/test/CodeGen/ARM/intrinsics-memory-barrier.ll
index 5ee0b3e59902..5626d38aae4b 100644
--- a/test/CodeGen/ARM/intrinsics-memory-barrier.ll
+++ b/test/CodeGen/ARM/intrinsics-memory-barrier.ll
@@ -18,7 +18,7 @@ define void @test_dmb_reordering(i32 %a, i32 %b, i32* %d) {
 
   call void @llvm.arm.dmb(i32 15)    ; CHECK: dmb sy
 
-  %d1 = getelementptr i32* %d, i32 1
+  %d1 = getelementptr i32, i32* %d, i32 1
   store i32 %b, i32* %d1             ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4]
 
   ret void
@@ -31,7 +31,7 @@ define void @test_dsb_reordering(i32 %a, i32 %b, i32* %d) {
 
   call void @llvm.arm.dsb(i32 15)    ; CHECK: dsb sy
 
-  %d1 = getelementptr i32* %d, i32 1
+  %d1 = getelementptr i32, i32* %d, i32 1
   store i32 %b, i32* %d1             ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4]
 
   ret void
@@ -44,7 +44,7 @@ define void @test_isb_reordering(i32 %a, i32 %b, i32* %d) {
 
   call void @llvm.arm.isb(i32 15)    ; CHECK: isb sy
 
-  %d1 = getelementptr i32* %d, i32 1
+  %d1 = getelementptr i32, i32* %d, i32 1
   store i32 %b, i32* %d1             ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4]
 
   ret void
diff --git a/test/CodeGen/ARM/invoke-donothing-assert.ll b/test/CodeGen/ARM/invoke-donothing-assert.ll
index 0b607f7edf38..aab3556c5477 100644
--- a/test/CodeGen/ARM/invoke-donothing-assert.ll
+++ b/test/CodeGen/ARM/invoke-donothing-assert.ll
@@ -46,7 +46,7 @@ new.notnull.i.i:
   br label %cleanup
 
 cleanup:
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %inc294 = add nsw i32 %0, 4
   store i32 %inc294, i32* %a, align 4
   br i1 false, label %_ZN3lol5ArrayIivvvvvvvED1Ev.exit, label %delete.notnull.i.i.i1409
diff --git a/test/CodeGen/ARM/isel-v8i32-crash.ll b/test/CodeGen/ARM/isel-v8i32-crash.ll
index 0116fe8de7cc..f1745bd47279 100644
--- a/test/CodeGen/ARM/isel-v8i32-crash.ll
+++ b/test/CodeGen/ARM/isel-v8i32-crash.ll
@@ -15,7 +15,7 @@ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
 define void @func(i16* nocapture %pb, float* nocapture readonly %pf) #0 {
 entry:
   %0 = bitcast float* %pf to <8 x float>*
-  %1 = load <8 x float>* %0, align 4
+  %1 = load <8 x float>, <8 x float>* %0, align 4
   %2 = fmul <8 x float> %1, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
   %3 = fptosi <8 x float> %2 to <8 x i16>
   %4 = bitcast i16* %pb to <8 x i16>*
diff --git a/test/CodeGen/ARM/krait-cpu-div-attribute.ll b/test/CodeGen/ARM/krait-cpu-div-attribute.ll
new file mode 100644
index 000000000000..222664a904ca
--- /dev/null
+++ b/test/CodeGen/ARM/krait-cpu-div-attribute.ll
@@ -0,0 +1,36 @@
+; Tests the genration of ".arch_extension" attribute for hardware
+; division on krait CPU. For now, krait is recognized as "cortex-a9" + hwdiv
+; Also, tests for the hwdiv instruction on krait CPU
+
+; check for arch_extension/cpu directive
+; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=krait | FileCheck %s --check-prefix=DIV_EXTENSION
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=krait | FileCheck %s --check-prefix=DIV_EXTENSION
+; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 | FileCheck %s --check-prefix=NODIV_KRAIT
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=cortex-a9 | FileCheck %s --check-prefix=NODIV_KRAIT
+; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=krait -mattr=-hwdiv,-hwdiv-arm | FileCheck %s --check-prefix=NODIV_KRAIT
+
+; check if correct instruction is emitted by integrated assembler
+; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=krait -filetype=obj | llvm-objdump -mcpu=krait -triple armv7-linux-gnueabi -d - | FileCheck %s --check-prefix=HWDIV
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=krait -filetype=obj | llvm-objdump -mcpu=krait -triple thumbv7-linux-gnueabi -d - | FileCheck %s --check-prefix=HWDIV
+
+; arch_extension attribute
+; DIV_EXTENSION:  .cpu cortex-a9
+; DIV_EXTENSION:  .arch_extension idiv
+; NODIV_KRAIT-NOT:  .arch_extension idiv
+; HWDIV: sdiv
+
+define i32 @main() #0 {
+entry:
+  %retval = alloca i32, align 4
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 0, i32* %retval
+  store volatile i32 100, i32* %b, align 4
+  store volatile i32 32, i32* %c, align 4
+  %0 = load volatile i32, i32* %b, align 4
+  %1 = load volatile i32, i32* %c, align 4
+  %div = sdiv i32 %0, %1
+  store volatile i32 %div, i32* %a, align 4
+  ret i32 0
+}
diff --git a/test/CodeGen/ARM/large-stack.ll b/test/CodeGen/ARM/large-stack.ll
index 1a9a1fadeebe..e2d4de341ec2 100644
--- a/test/CodeGen/ARM/large-stack.ll
+++ b/test/CodeGen/ARM/large-stack.ll
@@ -15,6 +15,6 @@ define i32 @test3() {
 	%tmp = alloca i32, align 4
 	%a = alloca [805306369 x i8], align 16
 	store i32 0, i32* %tmp
-	%tmp1 = load i32* %tmp
+	%tmp1 = load i32, i32* %tmp
         ret i32 %tmp1
 }
diff --git a/test/CodeGen/ARM/ldm.ll b/test/CodeGen/ARM/ldm.ll
index 3977da6da9cb..65e972f4e1b4 100644
--- a/test/CodeGen/ARM/ldm.ll
+++ b/test/CodeGen/ARM/ldm.ll
@@ -8,8 +8,8 @@ define i32 @t1() {
 ; CHECK: pop
 ; V4T-LABEL: t1:
 ; V4T: pop
-        %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0)            ; <i32> [#uses=1]
-        %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1)           ; <i32> [#uses=1]
+        %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 0)            ; <i32> [#uses=1]
+        %tmp3 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 1)           ; <i32> [#uses=1]
         %tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 )                ; <i32> [#uses=1]
         ret i32 %tmp4
 }
@@ -19,9 +19,9 @@ define i32 @t2() {
 ; CHECK: pop
 ; V4T-LABEL: t2:
 ; V4T: pop
-        %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2)            ; <i32> [#uses=1]
-        %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3)           ; <i32> [#uses=1]
-        %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4)           ; <i32> [#uses=1]
+        %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 2)            ; <i32> [#uses=1]
+        %tmp3 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 3)           ; <i32> [#uses=1]
+        %tmp5 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 4)           ; <i32> [#uses=1]
         %tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 )             ; <i32> [#uses=1]
         ret i32 %tmp6
 }
@@ -34,9 +34,9 @@ define i32 @t3() {
 ; V4T: ldmib
 ; V4T: pop
 ; V4T-NEXT: bx lr
-        %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1)            ; <i32> [#uses=1]
-        %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2)           ; <i32> [#uses=1]
-        %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3)           ; <i32> [#uses=1]
+        %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 1)            ; <i32> [#uses=1]
+        %tmp3 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 2)           ; <i32> [#uses=1]
+        %tmp5 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 3)           ; <i32> [#uses=1]
         %tmp6 = call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 )             ; <i32> [#uses=1]
         ret i32 %tmp6
 }
diff --git a/test/CodeGen/ARM/ldr.ll b/test/CodeGen/ARM/ldr.ll
index 57e9977ff872..bd4de5de669c 100644
--- a/test/CodeGen/ARM/ldr.ll
+++ b/test/CodeGen/ARM/ldr.ll
@@ -4,7 +4,7 @@ define i32 @f1(i32* %v) {
 ; CHECK-LABEL: f1:
 ; CHECK: ldr r0
 entry:
-        %tmp = load i32* %v
+        %tmp = load i32, i32* %v
         ret i32 %tmp
 }
 
@@ -12,8 +12,8 @@ define i32 @f2(i32* %v) {
 ; CHECK-LABEL: f2:
 ; CHECK: ldr r0
 entry:
-        %tmp2 = getelementptr i32* %v, i32 1023
-        %tmp = load i32* %tmp2
+        %tmp2 = getelementptr i32, i32* %v, i32 1023
+        %tmp = load i32, i32* %tmp2
         ret i32 %tmp
 }
 
@@ -22,8 +22,8 @@ define i32 @f3(i32* %v) {
 ; CHECK: mov
 ; CHECK: ldr r0
 entry:
-        %tmp2 = getelementptr i32* %v, i32 1024
-        %tmp = load i32* %tmp2
+        %tmp2 = getelementptr i32, i32* %v, i32 1024
+        %tmp = load i32, i32* %tmp2
         ret i32 %tmp
 }
 
@@ -34,7 +34,7 @@ define i32 @f4(i32 %base) {
 entry:
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i32*
-        %tmp3 = load i32* %tmp2
+        %tmp3 = load i32, i32* %tmp2
         ret i32 %tmp3
 }
 
@@ -44,7 +44,7 @@ define i32 @f5(i32 %base, i32 %offset) {
 entry:
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i32*
-        %tmp3 = load i32* %tmp2
+        %tmp3 = load i32, i32* %tmp2
         ret i32 %tmp3
 }
 
@@ -55,7 +55,7 @@ entry:
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
         %tmp3 = inttoptr i32 %tmp2 to i32*
-        %tmp4 = load i32* %tmp3
+        %tmp4 = load i32, i32* %tmp3
         ret i32 %tmp4
 }
 
@@ -66,6 +66,6 @@ entry:
         %tmp1 = lshr i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
         %tmp3 = inttoptr i32 %tmp2 to i32*
-        %tmp4 = load i32* %tmp3
+        %tmp4 = load i32, i32* %tmp3
         ret i32 %tmp4
 }
diff --git a/test/CodeGen/ARM/ldr_ext.ll b/test/CodeGen/ARM/ldr_ext.ll
index 31aaba5c3c21..15efb50c9a9a 100644
--- a/test/CodeGen/ARM/ldr_ext.ll
+++ b/test/CodeGen/ARM/ldr_ext.ll
@@ -2,28 +2,28 @@
 
 define i32 @test1(i8* %t1) nounwind {
 ; CHECK: ldrb
-    %tmp.u = load i8* %t1
+    %tmp.u = load i8, i8* %t1
     %tmp1.s = zext i8 %tmp.u to i32
     ret i32 %tmp1.s
 }
 
 define i32 @test2(i16* %t1) nounwind {
 ; CHECK: ldrh
-    %tmp.u = load i16* %t1
+    %tmp.u = load i16, i16* %t1
     %tmp1.s = zext i16 %tmp.u to i32
     ret i32 %tmp1.s
 }
 
 define i32 @test3(i8* %t0) nounwind {
 ; CHECK: ldrsb
-    %tmp.s = load i8* %t0
+    %tmp.s = load i8, i8* %t0
     %tmp1.s = sext i8 %tmp.s to i32
     ret i32 %tmp1.s
 }
 
 define i32 @test4(i16* %t0) nounwind {
 ; CHECK: ldrsh
-    %tmp.s = load i16* %t0
+    %tmp.s = load i16, i16* %t0
     %tmp1.s = sext i16 %tmp.s to i32
     ret i32 %tmp1.s
 }
@@ -31,7 +31,7 @@ define i32 @test4(i16* %t0) nounwind {
 define i32 @test5() nounwind {
 ; CHECK: mov r0, #0
 ; CHECK: ldrsh
-    %tmp.s = load i16* null
+    %tmp.s = load i16, i16* null
     %tmp1.s = sext i16 %tmp.s to i32
     ret i32 %tmp1.s
 }
diff --git a/test/CodeGen/ARM/ldr_frame.ll b/test/CodeGen/ARM/ldr_frame.ll
index ed964ecd3f83..01b18bccc337 100644
--- a/test/CodeGen/ARM/ldr_frame.ll
+++ b/test/CodeGen/ARM/ldr_frame.ll
@@ -2,30 +2,30 @@
 
 define i32 @f1() {
 	%buf = alloca [32 x i32], align 4
-	%tmp = getelementptr [32 x i32]* %buf, i32 0, i32 0
-	%tmp1 = load i32* %tmp
+	%tmp = getelementptr [32 x i32], [32 x i32]* %buf, i32 0, i32 0
+	%tmp1 = load i32, i32* %tmp
 	ret i32 %tmp1
 }
 
 define i32 @f2() {
 	%buf = alloca [32 x i8], align 4
-	%tmp = getelementptr [32 x i8]* %buf, i32 0, i32 0
-	%tmp1 = load i8* %tmp
+	%tmp = getelementptr [32 x i8], [32 x i8]* %buf, i32 0, i32 0
+	%tmp1 = load i8, i8* %tmp
         %tmp2 = zext i8 %tmp1 to i32
 	ret i32 %tmp2
 }
 
 define i32 @f3() {
 	%buf = alloca [32 x i32], align 4
-	%tmp = getelementptr [32 x i32]* %buf, i32 0, i32 32
-	%tmp1 = load i32* %tmp
+	%tmp = getelementptr [32 x i32], [32 x i32]* %buf, i32 0, i32 32
+	%tmp1 = load i32, i32* %tmp
 	ret i32 %tmp1
 }
 
 define i32 @f4() {
 	%buf = alloca [32 x i8], align 4
-	%tmp = getelementptr [32 x i8]* %buf, i32 0, i32 2
-	%tmp1 = load i8* %tmp
+	%tmp = getelementptr [32 x i8], [32 x i8]* %buf, i32 0, i32 2
+	%tmp1 = load i8, i8* %tmp
         %tmp2 = zext i8 %tmp1 to i32
 	ret i32 %tmp2
 }
diff --git a/test/CodeGen/ARM/ldr_post.ll b/test/CodeGen/ARM/ldr_post.ll
index 2558b16f3d3c..139c6f45e520 100644
--- a/test/CodeGen/ARM/ldr_post.ll
+++ b/test/CodeGen/ARM/ldr_post.ll
@@ -7,7 +7,7 @@
 define i32 @test1(i32 %a, i32 %b, i32 %c) {
         %tmp1 = mul i32 %a, %b          ; <i32> [#uses=2]
         %tmp2 = inttoptr i32 %tmp1 to i32*              ; <i32*> [#uses=1]
-        %tmp3 = load i32* %tmp2         ; <i32> [#uses=1]
+        %tmp3 = load i32, i32* %tmp2         ; <i32> [#uses=1]
         %tmp4 = sub i32 %tmp1, %c               ; <i32> [#uses=1]
         %tmp5 = mul i32 %tmp4, %tmp3            ; <i32> [#uses=1]
         ret i32 %tmp5
@@ -19,7 +19,7 @@ define i32 @test1(i32 %a, i32 %b, i32 %c) {
 define i32 @test2(i32 %a, i32 %b) {
         %tmp1 = mul i32 %a, %b          ; <i32> [#uses=2]
         %tmp2 = inttoptr i32 %tmp1 to i32*              ; <i32*> [#uses=1]
-        %tmp3 = load i32* %tmp2         ; <i32> [#uses=1]
+        %tmp3 = load i32, i32* %tmp2         ; <i32> [#uses=1]
         %tmp4 = sub i32 %tmp1, 16               ; <i32> [#uses=1]
         %tmp5 = mul i32 %tmp4, %tmp3            ; <i32> [#uses=1]
         ret i32 %tmp5
diff --git a/test/CodeGen/ARM/ldr_pre.ll b/test/CodeGen/ARM/ldr_pre.ll
index a97927a20ab1..c6c76e222836 100644
--- a/test/CodeGen/ARM/ldr_pre.ll
+++ b/test/CodeGen/ARM/ldr_pre.ll
@@ -5,8 +5,8 @@
 ; CHECK: ldr {{.*!}}
 ; CHECK-NOT: ldr
 define i32* @test1(i32* %X, i32* %dest) {
-        %Y = getelementptr i32* %X, i32 4               ; <i32*> [#uses=2]
-        %A = load i32* %Y               ; <i32> [#uses=1]
+        %Y = getelementptr i32, i32* %X, i32 4               ; <i32*> [#uses=2]
+        %A = load i32, i32* %Y               ; <i32> [#uses=1]
         store i32 %A, i32* %dest
         ret i32* %Y
 }
@@ -17,7 +17,7 @@ define i32* @test1(i32* %X, i32* %dest) {
 define i32 @test2(i32 %a, i32 %b, i32 %c) {
         %tmp1 = sub i32 %a, %b          ; <i32> [#uses=2]
         %tmp2 = inttoptr i32 %tmp1 to i32*              ; <i32*> [#uses=1]
-        %tmp3 = load i32* %tmp2         ; <i32> [#uses=1]
+        %tmp3 = load i32, i32* %tmp2         ; <i32> [#uses=1]
         %tmp4 = sub i32 %tmp1, %c               ; <i32> [#uses=1]
         %tmp5 = add i32 %tmp4, %tmp3            ; <i32> [#uses=1]
         ret i32 %tmp5
diff --git a/test/CodeGen/ARM/ldrd-memoper.ll b/test/CodeGen/ARM/ldrd-memoper.ll
index f1a1121f6aa4..744fbd5efb86 100644
--- a/test/CodeGen/ARM/ldrd-memoper.ll
+++ b/test/CodeGen/ARM/ldrd-memoper.ll
@@ -8,8 +8,8 @@
 ; CHECK: Formed {{.*}} t2LDRD{{.*}} mem:LD4[%0] LD4[%0+4]
 define i64 @t(i64 %a) nounwind readonly {
 entry:
-	%0 = load i64** @b, align 4
-	%1 = load i64* %0, align 4
+	%0 = load i64*, i64** @b, align 4
+	%1 = load i64, i64* %0, align 4
 	%2 = mul i64 %1, %a
 	ret i64 %2
 }
diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll
index caef2e78bbfa..7ce846844e05 100644
--- a/test/CodeGen/ARM/ldrd.ll
+++ b/test/CodeGen/ARM/ldrd.ll
@@ -19,8 +19,8 @@ entry:
 ; M3-LABEL: t:
 ; M3-NOT: ldrd
 
-	%0 = load i64** @b, align 4
-	%1 = load i64* %0, align 4
+	%0 = load i64*, i64** @b, align 4
+	%1 = load i64, i64* %0, align 4
 	%2 = mul i64 %1, %a
 	ret i64 %2
 }
@@ -53,12 +53,12 @@ entry:
 
 bb:                                               ; preds = %bb, %entry
   %i.03 = phi i32 [ %tmp, %bb ], [ 0, %entry ]    ; <i32> [#uses=3]
-  %scevgep = getelementptr i32* %a, i32 %i.03     ; <i32*> [#uses=1]
-  %scevgep4 = getelementptr i32* %b, i32 %i.03    ; <i32*> [#uses=1]
+  %scevgep = getelementptr i32, i32* %a, i32 %i.03     ; <i32*> [#uses=1]
+  %scevgep4 = getelementptr i32, i32* %b, i32 %i.03    ; <i32*> [#uses=1]
   %tmp = add i32 %i.03, 1                         ; <i32> [#uses=3]
-  %scevgep5 = getelementptr i32* %a, i32 %tmp     ; <i32*> [#uses=1]
-  %2 = load i32* %scevgep, align 4                ; <i32> [#uses=1]
-  %3 = load i32* %scevgep5, align 4               ; <i32> [#uses=1]
+  %scevgep5 = getelementptr i32, i32* %a, i32 %tmp     ; <i32*> [#uses=1]
+  %2 = load i32, i32* %scevgep, align 4                ; <i32> [#uses=1]
+  %3 = load i32, i32* %scevgep5, align 4               ; <i32> [#uses=1]
   %4 = add nsw i32 %3, %2                         ; <i32> [#uses=1]
   store i32 %4, i32* %scevgep4, align 4
   %exitcond = icmp eq i32 %tmp, %0                ; <i1> [#uses=1]
@@ -84,10 +84,10 @@ entry:
 ; A8-NEXT: str [[FIELD1]], {{\[}}[[BASE]]{{\]}}
   %orig_blocks = alloca [256 x i16], align 2
   %0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start(i64 512, i8* %0) nounwind
-  %tmp1 = load i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 1), align 4
-  %tmp2 = load i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 2), align 4
+  %tmp1 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 1), align 4
+  %tmp2 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 2), align 4
   %add = add nsw i32 %tmp2, %tmp1
-  store i32 %add, i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 0), align 4
+  store i32 %add, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 0), align 4
   call void @llvm.lifetime.end(i64 512, i8* %0) nounwind
   ret void
 }
diff --git a/test/CodeGen/ARM/ldst-f32-2-i32.ll b/test/CodeGen/ARM/ldst-f32-2-i32.ll
index 61c459c7435e..d00f44e8e885 100644
--- a/test/CodeGen/ARM/ldst-f32-2-i32.ll
+++ b/test/CodeGen/ARM/ldst-f32-2-i32.ll
@@ -14,10 +14,10 @@ bb:
 ; CHECK: str [[REGISTER]], [{{r[0-9]+}}], #4
   %j.05 = phi i32 [ %2, %bb ], [ 0, %entry ]
   %tmp = mul i32 %j.05, %index
-  %uglygep = getelementptr i8* %src6, i32 %tmp
+  %uglygep = getelementptr i8, i8* %src6, i32 %tmp
   %src_addr.04 = bitcast i8* %uglygep to float*
-  %dst_addr.03 = getelementptr float* %dst, i32 %j.05
-  %1 = load float* %src_addr.04, align 4
+  %dst_addr.03 = getelementptr float, float* %dst, i32 %j.05
+  %1 = load float, float* %src_addr.04, align 4
   store float %1, float* %dst_addr.03, align 4
   %2 = add i32 %j.05, 1
   %exitcond = icmp eq i32 %2, %width
diff --git a/test/CodeGen/ARM/ldstrex-m.ll b/test/CodeGen/ARM/ldstrex-m.ll
index b50699f4cde6..3d83a9d78e35 100644
--- a/test/CodeGen/ARM/ldstrex-m.ll
+++ b/test/CodeGen/ARM/ldstrex-m.ll
@@ -4,7 +4,7 @@
 ; CHECK-NOT: ldrexd
 define i64 @f0(i64* %p) nounwind readonly {
 entry:
-  %0 = load atomic i64* %p seq_cst, align 8
+  %0 = load atomic i64, i64* %p seq_cst, align 8
   ret i64 %0
 }
 
@@ -29,7 +29,7 @@ entry:
 ; CHECK: ldr
 define i32 @f3(i32* %p) nounwind readonly {
 entry:
-  %0 = load atomic i32* %p seq_cst, align 4
+  %0 = load atomic i32, i32* %p seq_cst, align 4
   ret i32 %0
 }
 
@@ -37,7 +37,7 @@ entry:
 ; CHECK: ldrb
 define i8 @f4(i8* %p) nounwind readonly {
 entry:
-  %0 = load atomic i8* %p seq_cst, align 4
+  %0 = load atomic i8, i8* %p seq_cst, align 4
   ret i8 %0
 }
 
diff --git a/test/CodeGen/ARM/ldstrex.ll b/test/CodeGen/ARM/ldstrex.ll
index a40e255e83ea..59349f72a8fe 100644
--- a/test/CodeGen/ARM/ldstrex.ll
+++ b/test/CodeGen/ARM/ldstrex.ll
@@ -106,24 +106,24 @@ declare void @llvm.arm.clrex() nounwind
 
 define void @excl_addrmode() {
 ; CHECK-T2ADDRMODE-LABEL: excl_addrmode:
-  %base1020 = load i32** @base
-  %offset1020 = getelementptr i32* %base1020, i32 255
+  %base1020 = load i32*, i32** @base
+  %offset1020 = getelementptr i32, i32* %base1020, i32 255
   call i32 @llvm.arm.ldrex.p0i32(i32* %offset1020)
   call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1020)
 ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [{{r[0-9]+}}, #1020]
 ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}, #1020]
 
-  %base1024 = load i32** @base
-  %offset1024 = getelementptr i32* %base1024, i32 256
+  %base1024 = load i32*, i32** @base
+  %offset1024 = getelementptr i32, i32* %base1024, i32 256
   call i32 @llvm.arm.ldrex.p0i32(i32* %offset1024)
   call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1024)
 ; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], {{r[0-9]+}}, #1024
 ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
 ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
 
-  %base1 = load i32** @base
+  %base1 = load i32*, i32** @base
   %addr8 = bitcast i32* %base1 to i8*
-  %offset1_8 = getelementptr i8* %addr8, i32 1
+  %offset1_8 = getelementptr i8, i8* %addr8, i32 1
   %offset1 = bitcast i8* %offset1_8 to i32*
   call i32 @llvm.arm.ldrex.p0i32(i32* %offset1)
   call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1)
diff --git a/test/CodeGen/ARM/load-global.ll b/test/CodeGen/ARM/load-global.ll
index 00ca2e8b1b75..34748bc848bd 100644
--- a/test/CodeGen/ARM/load-global.ll
+++ b/test/CodeGen/ARM/load-global.ll
@@ -45,6 +45,6 @@ define i32 @test1() {
 ; LINUX: ldr r0, [r1, r0]
 ; LINUX: ldr r0, [r0]
 ; LINUX: .long G(GOT)
-	%tmp = load i32* @G
+	%tmp = load i32, i32* @G
 	ret i32 %tmp
 }
diff --git a/test/CodeGen/ARM/load.ll b/test/CodeGen/ARM/load.ll
index ca16adc00822..3b2d637cb26e 100644
--- a/test/CodeGen/ARM/load.ll
+++ b/test/CodeGen/ARM/load.ll
@@ -2,28 +2,28 @@
 
 define i32 @f1(i8* %p) {
 entry:
-        %tmp = load i8* %p              ; <i8> [#uses=1]
+        %tmp = load i8, i8* %p              ; <i8> [#uses=1]
         %tmp1 = sext i8 %tmp to i32              ; <i32> [#uses=1]
         ret i32 %tmp1
 }
 
 define i32 @f2(i8* %p) {
 entry:
-        %tmp = load i8* %p              ; <i8> [#uses=1]
+        %tmp = load i8, i8* %p              ; <i8> [#uses=1]
         %tmp2 = zext i8 %tmp to i32              ; <i32> [#uses=1]
         ret i32 %tmp2
 }
 
 define i32 @f3(i16* %p) {
 entry:
-        %tmp = load i16* %p             ; <i16> [#uses=1]
+        %tmp = load i16, i16* %p             ; <i16> [#uses=1]
         %tmp3 = sext i16 %tmp to i32             ; <i32> [#uses=1]
         ret i32 %tmp3
 }
 
 define i32 @f4(i16* %p) {
 entry:
-        %tmp = load i16* %p             ; <i16> [#uses=1]
+        %tmp = load i16, i16* %p             ; <i16> [#uses=1]
         %tmp4 = zext i16 %tmp to i32             ; <i32> [#uses=1]
         ret i32 %tmp4
 }
diff --git a/test/CodeGen/ARM/load_i1_select.ll b/test/CodeGen/ARM/load_i1_select.ll
index 7a208ea41752..48cd4eae58fa 100644
--- a/test/CodeGen/ARM/load_i1_select.ll
+++ b/test/CodeGen/ARM/load_i1_select.ll
@@ -11,7 +11,7 @@ target triple = "thumbv7-apple-ios0.0.0"
 ; CHECK: tst.w r[[R0]], #1
 define void @foo(i8* %call, double* %p) nounwind {
 entry:
-  %tmp2 = load i8* %call
+  %tmp2 = load i8, i8* %call
   %tmp3 = trunc i8 %tmp2 to i1
   %cond = select i1 %tmp3, double 2.000000e+00, double 1.000000e+00
   store double %cond, double* %p
diff --git a/test/CodeGen/ARM/long.ll b/test/CodeGen/ARM/long.ll
index d0bff4a906e0..1807813d9305 100644
--- a/test/CodeGen/ARM/long.ll
+++ b/test/CodeGen/ARM/long.ll
@@ -85,6 +85,6 @@ define i64 @f10() {
 ; CHECK-LABEL: f10:
 entry:
         %a = alloca i64, align 8                ; <i64*> [#uses=1]
-        %retval = load i64* %a          ; <i64> [#uses=1]
+        %retval = load i64, i64* %a          ; <i64> [#uses=1]
         ret i64 %retval
 }
diff --git a/test/CodeGen/ARM/longMAC.ll b/test/CodeGen/ARM/longMAC.ll
index fed6ec02f32d..3f30fd40b7e7 100644
--- a/test/CodeGen/ARM/longMAC.ll
+++ b/test/CodeGen/ARM/longMAC.ll
@@ -75,3 +75,44 @@ define i64 @MACLongTest5(i64 %c, i32 %a, i32 %b) {
   %add = add i64 %mul, %c
   ret i64 %add
 }
+
+define i64 @MACLongTest6(i32 %a, i32 %b, i32 %c, i32 %d) {
+;CHECK-LABEL: MACLongTest6:
+;CHECK: smull   r12, lr, r1, r0
+;CHECK: smlal   r12, lr, r3, r2
+  %conv = sext i32 %a to i64
+  %conv1 = sext i32 %b to i64
+  %mul = mul nsw i64 %conv1, %conv
+  %conv2 = sext i32 %c to i64
+  %conv3 = sext i32 %d to i64
+  %mul4 = mul nsw i64 %conv3, %conv2
+  %add = add nsw i64 %mul4, %mul
+  ret i64 %add
+}
+
+define i64 @MACLongTest7(i64 %acc, i32 %lhs, i32 %rhs) {
+;CHECK-LABEL: MACLongTest7:
+;CHECK-NOT: smlal
+  %conv = sext i32 %lhs to i64
+  %conv1 = sext i32 %rhs to i64
+  %mul = mul nsw i64 %conv1, %conv
+  %shl = shl i64 %mul, 32
+  %shr = lshr i64 %mul, 32
+  %or = or i64 %shl, %shr
+  %add = add i64 %or, %acc
+  ret i64 %add
+}
+
+define i64 @MACLongTest8(i64 %acc, i32 %lhs, i32 %rhs) {
+;CHECK-LABEL: MACLongTest8:
+;CHECK-NOT: smlal
+  %conv = zext i32 %lhs to i64
+  %conv1 = zext i32 %rhs to i64
+  %mul = mul nuw i64 %conv1, %conv
+  %and = and i64 %mul, 4294967295
+  %shl = shl i64 %mul, 32
+  %or = or i64 %and, %shl
+  %add = add i64 %or, %acc
+  ret i64 %add
+}
+
diff --git a/test/CodeGen/ARM/lsr-code-insertion.ll b/test/CodeGen/ARM/lsr-code-insertion.ll
index 153fd8fe34e4..aa2b2d26d121 100644
--- a/test/CodeGen/ARM/lsr-code-insertion.ll
+++ b/test/CodeGen/ARM/lsr-code-insertion.ll
@@ -22,17 +22,17 @@ entry:
 bb:		; preds = %cond_next59, %entry
 	%indvar = phi i32 [ 0, %entry ], [ %k.069.0, %cond_next59 ]		; <i32> [#uses=6]
 	%k.069.0 = add i32 %indvar, 1		; <i32> [#uses=3]
-	%tmp3 = getelementptr i32* %mpp, i32 %indvar		; <i32*> [#uses=1]
-	%tmp4 = load i32* %tmp3		; <i32> [#uses=1]
-	%tmp8 = getelementptr i32* %tpmm, i32 %indvar		; <i32*> [#uses=1]
-	%tmp9 = load i32* %tmp8		; <i32> [#uses=1]
+	%tmp3 = getelementptr i32, i32* %mpp, i32 %indvar		; <i32*> [#uses=1]
+	%tmp4 = load i32, i32* %tmp3		; <i32> [#uses=1]
+	%tmp8 = getelementptr i32, i32* %tpmm, i32 %indvar		; <i32*> [#uses=1]
+	%tmp9 = load i32, i32* %tmp8		; <i32> [#uses=1]
 	%tmp10 = add i32 %tmp9, %tmp4		; <i32> [#uses=2]
-	%tmp13 = getelementptr i32* %mc, i32 %k.069.0		; <i32*> [#uses=5]
+	%tmp13 = getelementptr i32, i32* %mc, i32 %k.069.0		; <i32*> [#uses=5]
 	store i32 %tmp10, i32* %tmp13
-	%tmp17 = getelementptr i32* %ip, i32 %indvar		; <i32*> [#uses=1]
-	%tmp18 = load i32* %tmp17		; <i32> [#uses=1]
-	%tmp22 = getelementptr i32* %tpim, i32 %indvar		; <i32*> [#uses=1]
-	%tmp23 = load i32* %tmp22		; <i32> [#uses=1]
+	%tmp17 = getelementptr i32, i32* %ip, i32 %indvar		; <i32*> [#uses=1]
+	%tmp18 = load i32, i32* %tmp17		; <i32> [#uses=1]
+	%tmp22 = getelementptr i32, i32* %tpim, i32 %indvar		; <i32*> [#uses=1]
+	%tmp23 = load i32, i32* %tmp22		; <i32> [#uses=1]
 	%tmp24 = add i32 %tmp23, %tmp18		; <i32> [#uses=2]
 	%tmp30 = icmp sgt i32 %tmp24, %tmp10		; <i1> [#uses=1]
 	br i1 %tmp30, label %cond_true, label %cond_next
@@ -42,9 +42,9 @@ cond_true:		; preds = %bb
 	br label %cond_next
 
 cond_next:		; preds = %cond_true, %bb
-	%tmp39 = load i32* %tmp13		; <i32> [#uses=1]
-	%tmp42 = getelementptr i32* %ms, i32 %k.069.0		; <i32*> [#uses=1]
-	%tmp43 = load i32* %tmp42		; <i32> [#uses=1]
+	%tmp39 = load i32, i32* %tmp13		; <i32> [#uses=1]
+	%tmp42 = getelementptr i32, i32* %ms, i32 %k.069.0		; <i32*> [#uses=1]
+	%tmp43 = load i32, i32* %tmp42		; <i32> [#uses=1]
 	%tmp44 = add i32 %tmp43, %tmp39		; <i32> [#uses=2]
 	store i32 %tmp44, i32* %tmp13
 	%tmp52 = icmp slt i32 %tmp44, -987654321		; <i1> [#uses=1]
diff --git a/test/CodeGen/ARM/lsr-icmp-imm.ll b/test/CodeGen/ARM/lsr-icmp-imm.ll
index 103642b8b72f..ef98727344e5 100644
--- a/test/CodeGen/ARM/lsr-icmp-imm.ll
+++ b/test/CodeGen/ARM/lsr-icmp-imm.ll
@@ -18,8 +18,8 @@ for.body:                                         ; preds = %entry, %for.body
   %bi.06 = phi i32 [ %i.addr.0.bi.0, %for.body ], [ 0, %entry ]
   %i.addr.05 = phi i32 [ %sub, %for.body ], [ %i, %entry ]
   %b.04 = phi i32 [ %.b.0, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i32 %i.addr.05
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %i.addr.05
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %0, %b.04
   %.b.0 = select i1 %cmp1, i32 %0, i32 %b.04
   %i.addr.0.bi.0 = select i1 %cmp1, i32 %i.addr.05, i32 %bi.06
diff --git a/test/CodeGen/ARM/lsr-scale-addr-mode.ll b/test/CodeGen/ARM/lsr-scale-addr-mode.ll
index 948024163ba7..063ef76d95c9 100644
--- a/test/CodeGen/ARM/lsr-scale-addr-mode.ll
+++ b/test/CodeGen/ARM/lsr-scale-addr-mode.ll
@@ -9,7 +9,7 @@ entry:
 cond_next:		; preds = %cond_next, %entry
 	%indvar = phi i32 [ 0, %entry ], [ %tmp25, %cond_next ]		; <i32> [#uses=1]
 	%tmp25 = add i32 %indvar, 1		; <i32> [#uses=3]
-	%tmp36 = getelementptr i32* %a, i32 %tmp25		; <i32*> [#uses=1]
+	%tmp36 = getelementptr i32, i32* %a, i32 %tmp25		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp36
 	icmp eq i32 %tmp25, -1		; <i1>:0 [#uses=1]
 	br i1 %0, label %return, label %cond_next
diff --git a/test/CodeGen/ARM/lsr-unfolded-offset.ll b/test/CodeGen/ARM/lsr-unfolded-offset.ll
index 3ad60d47b53b..17292cfe2896 100644
--- a/test/CodeGen/ARM/lsr-unfolded-offset.ll
+++ b/test/CodeGen/ARM/lsr-unfolded-offset.ll
@@ -23,10 +23,10 @@ entry:
 outer.loop:                                 ; preds = %for.inc69, %entry
   %overlap.081 = phi i32 [ %overlap.4, %for.inc69 ], [ 0, %entry ]
   %0 = phi i32 [ %inc71, %for.inc69 ], [ 0, %entry ]
-  %offset = getelementptr %struct.partition_entry* %part, i32 %0, i32 2
-  %len = getelementptr %struct.partition_entry* %part, i32 %0, i32 3
-  %tmp5 = load i64* %offset, align 4
-  %tmp15 = load i64* %len, align 4
+  %offset = getelementptr %struct.partition_entry, %struct.partition_entry* %part, i32 %0, i32 2
+  %len = getelementptr %struct.partition_entry, %struct.partition_entry* %part, i32 %0, i32 3
+  %tmp5 = load i64, i64* %offset, align 4
+  %tmp15 = load i64, i64* %len, align 4
   %add = add nsw i64 %tmp15, %tmp5
   br label %inner.loop
 
@@ -37,10 +37,10 @@ inner.loop:                                       ; preds = %for.inc, %outer.loo
   br i1 %cmp23, label %for.inc, label %if.end
 
 if.end:                                           ; preds = %inner.loop
-  %len39 = getelementptr %struct.partition_entry* %part, i32 %1, i32 3
-  %offset28 = getelementptr %struct.partition_entry* %part, i32 %1, i32 2
-  %tmp29 = load i64* %offset28, align 4
-  %tmp40 = load i64* %len39, align 4
+  %len39 = getelementptr %struct.partition_entry, %struct.partition_entry* %part, i32 %1, i32 3
+  %offset28 = getelementptr %struct.partition_entry, %struct.partition_entry* %part, i32 %1, i32 2
+  %tmp29 = load i64, i64* %offset28, align 4
+  %tmp40 = load i64, i64* %len39, align 4
   %add41 = add nsw i64 %tmp40, %tmp29
   %cmp44 = icmp sge i64 %tmp29, %tmp5
   %cmp47 = icmp slt i64 %tmp29, %add
diff --git a/test/CodeGen/ARM/machine-cse-cmp.ll b/test/CodeGen/ARM/machine-cse-cmp.ll
index 7e4b309fd9d1..1f92ff4e1192 100644
--- a/test/CodeGen/ARM/machine-cse-cmp.ll
+++ b/test/CodeGen/ARM/machine-cse-cmp.ll
@@ -30,14 +30,14 @@ entry:
 ; CHECK: poplt
 ; CHECK-NOT: cmp
 ; CHECK: movle
-  %0 = load i32* @foo, align 4
+  %0 = load i32, i32* @foo, align 4
   %cmp28 = icmp sgt i32 %0, 0
   br i1 %cmp28, label %for.body.lr.ph, label %for.cond1.preheader
 
 for.body.lr.ph:                                   ; preds = %entry
   %1 = icmp sgt i32 %0, 1
   %smax = select i1 %1, i32 %0, i32 1
-  call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([250 x i8]* @bar, i32 0, i32 0), i8 0, i32 %smax, i32 1, i1 false)
+  call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([250 x i8], [250 x i8]* @bar, i32 0, i32 0), i8 0, i32 %smax, i32 1, i1 false)
   unreachable
 
 for.cond1.preheader:                              ; preds = %entry
@@ -53,7 +53,7 @@ entry:
 ; CHECK-NOT: sub
 ; CHECK: cmp
 ; CHECK: blt
-%0 = load i32* %offset, align 4
+%0 = load i32, i32* %offset, align 4
 %cmp = icmp slt i32 %0, %size
 %s = sub nsw i32 %0, %size
 %size2 = sub nsw i32 %size, 0
@@ -70,7 +70,7 @@ if.end:
 ; CHECK-NOT: sub
 ; CHECK: str
 store i32 %s3, i32* %offset, align 4
-%add.ptr = getelementptr inbounds i8* %base, i32 %sub
+%add.ptr = getelementptr inbounds i8, i8* %base, i32 %sub
 br label %return
 
 return:
diff --git a/test/CodeGen/ARM/machine-licm.ll b/test/CodeGen/ARM/machine-licm.ll
index ca6550178f92..a1eec78e453f 100644
--- a/test/CodeGen/ARM/machine-licm.ll
+++ b/test/CodeGen/ARM/machine-licm.ll
@@ -39,14 +39,14 @@ bb.nph:                                           ; preds = %entry
 ; THUMB: LCPI0_0:
 ; THUMB-NOT: LCPI0_1:
 ; THUMB: .section
-  %.pre = load i32* @GV, align 4                  ; <i32> [#uses=1]
+  %.pre = load i32, i32* @GV, align 4                  ; <i32> [#uses=1]
   br label %bb
 
 bb:                                               ; preds = %bb, %bb.nph
   %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ]    ; <i32> [#uses=1]
   %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ]     ; <i32> [#uses=2]
-  %scevgep = getelementptr i32* %vals, i32 %i.03  ; <i32*> [#uses=1]
-  %2 = load i32* %scevgep, align 4                ; <i32> [#uses=1]
+  %scevgep = getelementptr i32, i32* %vals, i32 %i.03  ; <i32*> [#uses=1]
+  %2 = load i32, i32* %scevgep, align 4                ; <i32> [#uses=1]
   %3 = add nsw i32 %1, %2                         ; <i32> [#uses=2]
   store i32 %3, i32* @GV, align 4
   %4 = add i32 %i.03, 1                           ; <i32> [#uses=2]
diff --git a/test/CodeGen/ARM/memcpy-inline.ll b/test/CodeGen/ARM/memcpy-inline.ll
index 84ce4a7f0e79..4ea26e1c59a3 100644
--- a/test/CodeGen/ARM/memcpy-inline.ll
+++ b/test/CodeGen/ARM/memcpy-inline.ll
@@ -23,20 +23,20 @@ entry:
 ; CHECK-T1: strb [[TREG1]],
 ; CHECK-T1: ldrh [[TREG2:r[0-9]]],
 ; CHECK-T1: strh [[TREG2]]
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x, %struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x, %struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false)
   ret i32 0
 }
 
 define void @t1(i8* nocapture %C) nounwind {
 entry:
 ; CHECK-LABEL: t1:
-; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
+; CHECK: vld1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
 ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
 ; CHECK: adds r0, #15
 ; CHECK: adds r1, #15
 ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
 ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
-  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8]* @.str1, i64 0, i64 0), i64 31, i32 1, i1 false)
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str1, i64 0, i64 0), i64 31, i32 1, i1 false)
   ret void
 }
 
@@ -46,35 +46,32 @@ entry:
 ; CHECK: movw [[REG2:r[0-9]+]], #16716
 ; CHECK: movt [[REG2:r[0-9]+]], #72
 ; CHECK: str [[REG2]], [r0, #32]
-; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
-; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
-; CHECK: adds r0, #16
-; CHECK: adds r1, #16
-; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
+; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
+; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
+; CHECK: vld1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
 ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
-  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false)
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8], [36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false)
   ret void
 }
 
 define void @t3(i8* nocapture %C) nounwind {
 entry:
 ; CHECK-LABEL: t3:
-; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
-; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
-; CHECK: adds r0, #16
-; CHECK: adds r1, #16
-; CHECK: vld1.8 {d{{[0-9]+}}}, [r1]
+; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
+; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
+; CHECK: vldr d{{[0-9]+}}, [r1]
 ; CHECK: vst1.8 {d{{[0-9]+}}}, [r0]
-  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false)
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false)
   ret void
 }
 
 define void @t4(i8* nocapture %C) nounwind {
 entry:
 ; CHECK-LABEL: t4:
-; CHECK: vld1.8 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1]
-; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]
-  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
+; CHECK: vld1.64 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1]
+; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]!
+; CHECK: strh [[REG5:r[0-9]+]], [r0]
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
   ret void
 }
 
@@ -93,25 +90,25 @@ entry:
 ; CHECK-T1: strb [[TREG3]],
 ; CHECK-T1: movs [[TREG4:r[0-9]]],
 ; CHECK-T1: strb [[TREG4]],
-  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8]* @.str5, i64 0, i64 0), i64 7, i32 1, i1 false)
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str5, i64 0, i64 0), i64 7, i32 1, i1 false)
   ret void
 }
 
 define void @t6() nounwind {
 entry:
 ; CHECK-LABEL: t6:
-; CHECK: vld1.8 {[[REG9:d[0-9]+]]}, [r0]
+; CHECK: vldr [[REG9:d[0-9]+]], [r0]
 ; CHECK: vstr [[REG9]], [r1]
 ; CHECK: adds r1, #6
 ; CHECK: adds r0, #6
-; CHECK: vld1.8
+; CHECK: vld1.16
 ; CHECK: vst1.16
 ; CHECK-T1-LABEL: t6:
 ; CHECK-T1: movs [[TREG5:r[0-9]]],
 ; CHECK-T1: strh [[TREG5]],
 ; CHECK-T1: ldr [[TREG6:r[0-9]]],
 ; CHECK-T1: str [[TREG6]]
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([512 x i8]* @spool.splbuf, i64 0, i64 0), i8* getelementptr inbounds ([14 x i8]* @.str6, i64 0, i64 0), i64 14, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([512 x i8], [512 x i8]* @spool.splbuf, i64 0, i64 0), i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str6, i64 0, i64 0), i64 14, i32 1, i1 false)
   ret void
 }
 
diff --git a/test/CodeGen/ARM/memfunc.ll b/test/CodeGen/ARM/memfunc.ll
index 8d3800b43c14..5223983a7f30 100644
--- a/test/CodeGen/ARM/memfunc.ll
+++ b/test/CodeGen/ARM/memfunc.ll
@@ -1,33 +1,375 @@
-; RUN: llc < %s -mtriple=armv7-apple-ios -o - | FileCheck %s
-; RUN: llc < %s -mtriple=thumbv7m-none-macho -o - | FileCheck %s --check-prefix=DARWIN
-; RUN: llc < %s -mtriple=arm-none-eabi -o - | FileCheck --check-prefix=EABI %s
-; RUN: llc < %s -mtriple=arm-none-eabihf -o - | FileCheck --check-prefix=EABI %s
+; RUN: llc < %s -mtriple=armv7-apple-ios -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-IOS --check-prefix=CHECK
+; RUN: llc < %s -mtriple=thumbv7m-none-macho -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-DARWIN --check-prefix=CHECK
+; RUN: llc < %s -mtriple=arm-none-eabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI --check-prefix=CHECK
+; RUN: llc < %s -mtriple=arm-none-eabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI --check-prefix=CHECK
 
-@from = common global [500 x i32] zeroinitializer, align 4
-@to = common global [500 x i32] zeroinitializer, align 4
+define void @f1(i8* %dest, i8* %src) {
+entry:
+  ; CHECK-LABEL: f1
+
+  ; CHECK-IOS: memmove
+  ; CHECK-DARWIN: memmove
+  ; CHECK-EABI: __aeabi_memmove
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 0, i1 false)
+
+  ; CHECK-IOS: memcpy
+  ; CHECK-DARWIN: memcpy
+  ; CHECK-EABI: __aeabi_memcpy
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 0, i1 false)
+
+  ; EABI memset swaps arguments
+  ; CHECK-IOS: mov r1, #1
+  ; CHECK-IOS: memset
+  ; CHECK-DARWIN: movs r1, #1
+  ; CHECK-DARWIN: memset
+  ; CHECK-EABI: mov r2, #1
+  ; CHECK-EABI: __aeabi_memset
+  call void @llvm.memset.p0i8.i32(i8* %dest, i8 1, i32 500, i32 0, i1 false)
+
+  ; EABI uses memclr if value set to 0
+  ; CHECK-IOS: mov r1, #0
+  ; CHECK-IOS: memset
+  ; CHECK-DARWIN: movs r1, #0
+  ; CHECK-DARWIN: memset
+  ; CHECK-EABI: __aeabi_memclr
+  call void @llvm.memset.p0i8.i32(i8* %dest, i8 0, i32 500, i32 0, i1 false)
+  
+  ; EABI uses aligned function variants if possible
+
+  ; CHECK-IOS: memmove
+  ; CHECK-DARWIN: memmove
+  ; CHECK-EABI: __aeabi_memmove4
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 4, i1 false)
+
+  ; CHECK-IOS: memcpy
+  ; CHECK-DARWIN: memcpy
+  ; CHECK-EABI: __aeabi_memcpy4
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 4, i1 false)
+
+  ; CHECK-IOS: memset
+  ; CHECK-DARWIN: memset
+  ; CHECK-EABI: __aeabi_memset4
+  call void @llvm.memset.p0i8.i32(i8* %dest, i8 1, i32 500, i32 4, i1 false)
+
+  ; CHECK-IOS: memset
+  ; CHECK-DARWIN: memset
+  ; CHECK-EABI: __aeabi_memclr4
+  call void @llvm.memset.p0i8.i32(i8* %dest, i8 0, i32 500, i32 4, i1 false)
+
+  ; CHECK-IOS: memmove
+  ; CHECK-DARWIN: memmove
+  ; CHECK-EABI: __aeabi_memmove8
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 8, i1 false)
+
+  ; CHECK-IOS: memcpy
+  ; CHECK-DARWIN: memcpy
+  ; CHECK-EABI: __aeabi_memcpy8
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 8, i1 false)
+
+  ; CHECK-IOS: memset
+  ; CHECK-DARWIN: memset
+  ; CHECK-EABI: __aeabi_memset8
+  call void @llvm.memset.p0i8.i32(i8* %dest, i8 1, i32 500, i32 8, i1 false)
+
+  ; CHECK-IOS: memset
+  ; CHECK-DARWIN: memset
+  ; CHECK-EABI: __aeabi_memclr8
+  call void @llvm.memset.p0i8.i32(i8* %dest, i8 0, i32 500, i32 8, i1 false)
+
+  unreachable
+}
+
+; Check that alloca arguments to memory intrinsics are automatically aligned if at least 8 bytes in size
+define void @f2(i8* %dest, i32 %n) {
+entry:
+  ; CHECK-LABEL: f2
+
+  ; IOS (ARMv7) should 8-byte align, others should 4-byte align
+  ; CHECK-IOS: add r1, sp, #32
+  ; CHECK-IOS: memmove
+  ; CHECK-DARWIN: add r1, sp, #28
+  ; CHECK-DARWIN: memmove
+  ; CHECK-EABI: add r1, sp, #28
+  ; CHECK-EABI: __aeabi_memmove
+  %arr0 = alloca [9 x i8], align 1
+  %0 = bitcast [9 x i8]* %arr0 to i8*
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false)
+
+  ; CHECK: add r1, sp, #16
+  ; CHECK-IOS: memcpy
+  ; CHECK-DARWIN: memcpy
+  ; CHECK-EABI: __aeabi_memcpy
+  %arr1 = alloca [9 x i8], align 1
+  %1 = bitcast [9 x i8]* %arr1 to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false)
+
+  ; CHECK-IOS: mov r0, sp
+  ; CHECK-IOS: mov r1, #1
+  ; CHECK-IOS: memset
+  ; CHECK-DARWIN: add r0, sp, #4
+  ; CHECK-DARWIN: movs r1, #1
+  ; CHECK-DARWIN: memset
+  ; CHECK-EABI: add r0, sp, #4
+  ; CHECK-EABI: mov r2, #1
+  ; CHECK-EABI: __aeabi_memset
+  %arr2 = alloca [9 x i8], align 1
+  %2 = bitcast [9 x i8]* %arr2 to i8*
+  call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false)
+
+  unreachable
+}
+
+; Check that alloca arguments are not aligned if less than 8 bytes in size
+define void @f3(i8* %dest, i32 %n) {
+entry:
+  ; CHECK-LABEL: f3
 
-define void @f() {
+  ; CHECK: {{add(.w)? r1, sp, #17|sub(.w)? r1, r7, #15}}
+  ; CHECK-IOS: memmove
+  ; CHECK-DARWIN: memmove
+  ; CHECK-EABI: __aeabi_memmove
+  %arr0 = alloca [7 x i8], align 1
+  %0 = bitcast [7 x i8]* %arr0 to i8*
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false)
+
+  ; CHECK: {{add(.w)? r1, sp, #10}}
+  ; CHECK-IOS: memcpy
+  ; CHECK-DARWIN: memcpy
+  ; CHECK-EABI: __aeabi_memcpy
+  %arr1 = alloca [7 x i8], align 1
+  %1 = bitcast [7 x i8]* %arr1 to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false)
+
+  ; CHECK: {{add(.w)? r0, sp, #3}}
+  ; CHECK-IOS: mov r1, #1
+  ; CHECK-IOS: memset
+  ; CHECK-DARWIN: movs r1, #1
+  ; CHECK-DARWIN: memset
+  ; CHECK-EABI: mov r2, #1
+  ; CHECK-EABI: __aeabi_memset
+  %arr2 = alloca [7 x i8], align 1
+  %2 = bitcast [7 x i8]* %arr2 to i8*
+  call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false)
+
+  unreachable
+}
+
+; Check that alloca arguments are not aligned if size+offset is less than 8 bytes
+define void @f4(i8* %dest, i32 %n) {
 entry:
+  ; CHECK-LABEL: f4
+
+  ; CHECK: {{add(.w)? r., sp, #23|sub(.w)? r., r7, #17}}
+  ; CHECK-IOS: memmove
+  ; CHECK-DARWIN: memmove
+  ; CHECK-EABI: __aeabi_memmove
+  %arr0 = alloca [9 x i8], align 1
+  %0 = getelementptr inbounds [9 x i8], [9 x i8]* %arr0, i32 0, i32 4
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false)
 
-        ; CHECK: memmove
-        ; EABI: __aeabi_memmove
-        call void @llvm.memmove.p0i8.p0i8.i32(i8* bitcast ([500 x i32]* @from to i8*), i8* bitcast ([500 x i32]* @to to i8*), i32 500, i32 0, i1 false)
+  ; CHECK: {{add(.w)? r., sp, #(10|14)}}
+  ; CHECK-IOS: memcpy
+  ; CHECK-DARWIN: memcpy
+  ; CHECK-EABI: __aeabi_memcpy
+  %arr1 = alloca [9 x i8], align 1
+  %1 = getelementptr inbounds [9 x i8], [9 x i8]* %arr1, i32 0, i32 4
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false)
 
-        ; CHECK: memcpy
-        ; EABI: __aeabi_memcpy
-        call void @llvm.memcpy.p0i8.p0i8.i32(i8* bitcast ([500 x i32]* @from to i8*), i8* bitcast ([500 x i32]* @to to i8*), i32 500, i32 0, i1 false)
+  ; CHECK: {{add(.w)? r., sp, #(1|5)}}
+  ; CHECK-IOS: mov r1, #1
+  ; CHECK-IOS: memset
+  ; CHECK-DARWIN: movs r1, #1
+  ; CHECK-DARWIN: memset
+  ; CHECK-EABI: mov r2, #1
+  ; CHECK-EABI: __aeabi_memset
+  %arr2 = alloca [9 x i8], align 1
+  %2 = getelementptr inbounds [9 x i8], [9 x i8]* %arr2, i32 0, i32 4
+  call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false)
 
-        ; EABI memset swaps arguments
-        ; CHECK: mov r1, #0
-        ; CHECK: memset
-        ; DARWIN: movs r1, #0
-        ; DARWIN: memset
-        ; EABI: mov r2, #0
-        ; EABI: __aeabi_memset
-        call void @llvm.memset.p0i8.i32(i8* bitcast ([500 x i32]* @from to i8*), i8 0, i32 500, i32 0, i1 false)
-        unreachable
+  unreachable
 }
 
+; Check that alloca arguments are not aligned if the offset is not a multiple of 4
+define void @f5(i8* %dest, i32 %n) {
+entry:
+  ; CHECK-LABEL: f5
+
+  ; CHECK: {{add(.w)? r., sp, #27|sub(.w)? r., r7, #21}}
+  ; CHECK-IOS: memmove
+  ; CHECK-DARWIN: memmove
+  ; CHECK-EABI: __aeabi_memmove
+  %arr0 = alloca [13 x i8], align 1
+  %0 = getelementptr inbounds [13 x i8], [13 x i8]* %arr0, i32 0, i32 1
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false)
+
+  ; CHECK: {{add(.w)? r., sp, #(10|14)}}
+  ; CHECK-IOS: memcpy
+  ; CHECK-DARWIN: memcpy
+  ; CHECK-EABI: __aeabi_memcpy
+  %arr1 = alloca [13 x i8], align 1
+  %1 = getelementptr inbounds [13 x i8], [13 x i8]* %arr1, i32 0, i32 1
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false)
+
+  ; CHECK: {{add(.w)? r., sp, #(1|5)}}
+  ; CHECK-IOS: mov r1, #1
+  ; CHECK-IOS: memset
+  ; CHECK-DARWIN: movs r1, #1
+  ; CHECK-DARWIN: memset
+  ; CHECK-EABI: mov r2, #1
+  ; CHECK-EABI: __aeabi_memset
+  %arr2 = alloca [13 x i8], align 1
+  %2 = getelementptr inbounds [13 x i8], [13 x i8]* %arr2, i32 0, i32 1
+  call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false)
+
+  unreachable
+}
+
+; Check that alloca arguments are not aligned if the offset is unknown
+define void @f6(i8* %dest, i32 %n, i32 %i) {
+entry:
+  ; CHECK-LABEL: f6
+
+  ; CHECK: {{add(.w)? r., sp, #27|sub(.w)? r., r7, #25}}
+  ; CHECK-IOS: memmove
+  ; CHECK-DARWIN: memmove
+  ; CHECK-EABI: __aeabi_memmove
+  %arr0 = alloca [13 x i8], align 1
+  %0 = getelementptr inbounds [13 x i8], [13 x i8]* %arr0, i32 0, i32 %i
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false)
+
+  ; CHECK: {{add(.w)? r., sp, #(10|14)}}
+  ; CHECK-IOS: memcpy
+  ; CHECK-DARWIN: memcpy
+  ; CHECK-EABI: __aeabi_memcpy
+  %arr1 = alloca [13 x i8], align 1
+  %1 = getelementptr inbounds [13 x i8], [13 x i8]* %arr1, i32 0, i32 %i
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false)
+
+  ; CHECK: {{add(.w)? r., sp, #(1|5)}}
+  ; CHECK-IOS: mov r1, #1
+  ; CHECK-IOS: memset
+  ; CHECK-DARWIN: movs r1, #1
+  ; CHECK-DARWIN: memset
+  ; CHECK-EABI: mov r2, #1
+  ; CHECK-EABI: __aeabi_memset
+  %arr2 = alloca [13 x i8], align 1
+  %2 = getelementptr inbounds [13 x i8], [13 x i8]* %arr2, i32 0, i32 %i
+  call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false)
+
+  unreachable
+}
+
+; Check that alloca arguments are not aligned if the GEP is not inbounds
+define void @f7(i8* %dest, i32 %n) {
+entry:
+  ; CHECK-LABEL: f7
+
+  ; CHECK: {{add(.w)? r., sp, #27|sub(.w)? r., r7, #21}}
+  ; CHECK-IOS: memmove
+  ; CHECK-DARWIN: memmove
+  ; CHECK-EABI: __aeabi_memmove
+  %arr0 = alloca [13 x i8], align 1
+  %0 = getelementptr [13 x i8], [13 x i8]* %arr0, i32 0, i32 4
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false)
+
+  ; CHECK: {{add(.w)? r., sp, #(10|14)}}
+  ; CHECK-IOS: memcpy
+  ; CHECK-DARWIN: memcpy
+  ; CHECK-EABI: __aeabi_memcpy
+  %arr1 = alloca [13 x i8], align 1
+  %1 = getelementptr [13 x i8], [13 x i8]* %arr1, i32 0, i32 4
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false)
+
+  ; CHECK: {{add(.w)? r., sp, #(1|5)}}
+  ; CHECK-IOS: mov r1, #1
+  ; CHECK-IOS: memset
+  ; CHECK-DARWIN: movs r1, #1
+  ; CHECK-DARWIN: memset
+  ; CHECK-EABI: mov r2, #1
+  ; CHECK-EABI: __aeabi_memset
+  %arr2 = alloca [13 x i8], align 1
+  %2 = getelementptr [13 x i8], [13 x i8]* %arr2, i32 0, i32 4
+  call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false)
+
+  unreachable
+}
+
+; Check that alloca arguments are not aligned when the offset is past the end of the allocation
+define void @f8(i8* %dest, i32 %n) {
+entry:
+  ; CHECK-LABEL: f8
+
+  ; CHECK: {{add(.w)? r., sp, #27|sub(.w)? r., r7, #21}}
+  ; CHECK-IOS: memmove
+  ; CHECK-DARWIN: memmove
+  ; CHECK-EABI: __aeabi_memmove
+  %arr0 = alloca [13 x i8], align 1
+  %0 = getelementptr inbounds [13 x i8], [13 x i8]* %arr0, i32 0, i32 16
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false)
+
+  ; CHECK: {{add(.w)? r., sp, #(10|14)}}
+  ; CHECK-IOS: memcpy
+  ; CHECK-DARWIN: memcpy
+  ; CHECK-EABI: __aeabi_memcpy
+  %arr1 = alloca [13 x i8], align 1
+  %1 = getelementptr inbounds [13 x i8], [13 x i8]* %arr1, i32 0, i32 16
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false)
+
+  ; CHECK: {{add(.w)? r., sp, #(1|5)}}
+  ; CHECK-IOS: mov r1, #1
+  ; CHECK-IOS: memset
+  ; CHECK-DARWIN: movs r1, #1
+  ; CHECK-DARWIN: memset
+  ; CHECK-EABI: mov r2, #1
+  ; CHECK-EABI: __aeabi_memset
+  %arr2 = alloca [13 x i8], align 1
+  %2 = getelementptr inbounds [13 x i8], [13 x i8]* %arr2, i32 0, i32 16
+  call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false)
+
+  unreachable
+}
+
+; Check that global variables are aligned if they are large enough, but only if
+; they are defined in this object and don't have an explicit section.
+@arr1 = global [7 x i8] c"\01\02\03\04\05\06\07", align 1
+@arr2 = global [8 x i8] c"\01\02\03\04\05\06\07\08", align 1
+@arr3 = global [7 x i8] c"\01\02\03\04\05\06\07", section "foo,bar", align 1
+@arr4 = global [8 x i8] c"\01\02\03\04\05\06\07\08", section "foo,bar", align 1
+@arr5 = weak global [7 x i8] c"\01\02\03\04\05\06\07", align 1
+@arr6 = weak_odr global [7 x i8] c"\01\02\03\04\05\06\07", align 1
+@arr7 = external global [7 x i8], align 1
+define void @f9(i8* %dest, i32 %n) {
+entry:
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr1, i32 0, i32 0), i32 %n, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @arr2, i32 0, i32 0), i32 %n, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr3, i32 0, i32 0), i32 %n, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @arr4, i32 0, i32 0), i32 %n, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr5, i32 0, i32 0), i32 %n, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr6, i32 0, i32 0), i32 %n, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr7, i32 0, i32 0), i32 %n, i32 1, i1 false)
+
+  unreachable
+}
+
+; CHECK: {{\.data|\.section.+data}}
+; CHECK-NOT: .align
+; CHECK: arr1:
+; CHECK-IOS: .align 3
+; CHECK-DARWIN: .align 2
+; CHECK-EABI: .align 2
+; CHECK: arr2:
+; CHECK: {{\.section.+foo,bar}}
+; CHECK-NOT: .align
+; CHECK: arr3:
+; CHECK-NOT: .align
+; CHECK: arr4:
+; CHECK: {{\.data|\.section.+data}}
+; CHECK-NOT: .align
+; CHECK: arr5:
+; CHECK-NOT: .align
+; CHECK: arr6:
+; CHECK-NOT: arr7:
+
 declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
 declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
diff --git a/test/CodeGen/ARM/memset-inline.ll b/test/CodeGen/ARM/memset-inline.ll
index 4e86d05b0a1c..191db1e20a25 100644
--- a/test/CodeGen/ARM/memset-inline.ll
+++ b/test/CodeGen/ARM/memset-inline.ll
@@ -17,9 +17,9 @@ entry:
 ; CHECK: add.w r1, r0, #10
 ; CHECK: vmov.i32 {{q[0-9]+}}, #0x0
 ; CHECK: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
-; CHECK: vst1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
+; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
   %buf = alloca [26 x i8], align 1
-  %0 = getelementptr inbounds [26 x i8]* %buf, i32 0, i32 0
+  %0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0
   call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false)
   call void @something(i8* %0) nounwind
   ret void
diff --git a/test/CodeGen/ARM/minsize-litpools.ll b/test/CodeGen/ARM/minsize-litpools.ll
index d5cd2a9b72e1..d5452ed0f909 100644
--- a/test/CodeGen/ARM/minsize-litpools.ll
+++ b/test/CodeGen/ARM/minsize-litpools.ll
@@ -12,7 +12,7 @@ define i32 @small_global() minsize {
 ; CHECK: ldr r[[GLOBDEST:[0-9]+]], {{.?LCPI0_0}}
 ; CHECK: ldr r0, [r[[GLOBDEST]]]
 
-  %val = load i32* @var
+  %val = load i32, i32* @var
   ret i32 %val
 }
 
@@ -21,6 +21,6 @@ define i32 @big_global() {
 ; CHECK: movw [[GLOBDEST:r[0-9]+]], :lower16:var
 ; CHECK: movt [[GLOBDEST]], :upper16:var
 
-  %val = load i32* @var
+  %val = load i32, i32* @var
   ret i32 %val
 }
diff --git a/test/CodeGen/ARM/misched-copy-arm.ll b/test/CodeGen/ARM/misched-copy-arm.ll
index bb2d42ca9ede..330252a90d7c 100644
--- a/test/CodeGen/ARM/misched-copy-arm.ll
+++ b/test/CodeGen/ARM/misched-copy-arm.ll
@@ -18,8 +18,8 @@ for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %s.05 = phi i32 [ %mul, %for.body ], [ 0, %entry ]
   %indvars.iv.next = add i32 %indvars.iv, %s
-  %arrayidx = getelementptr inbounds i32* %d, i32 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %d, i32 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %mul = mul nsw i32 %0, %s.05
   %exitcond = icmp eq i32 %indvars.iv.next, %a
   br i1 %exitcond, label %for.end, label %for.body
@@ -63,9 +63,9 @@ if.then24:                                        ; preds = %while.cond
 
 if.end28:                                         ; preds = %if.then24, %while.cond, %while.cond
   %dst.1 = phi %struct.rtx_def* [ undef, %if.then24 ], [ %dst.0, %while.cond ], [ %dst.0, %while.cond ]
-  %arrayidx30 = getelementptr inbounds %struct.rtx_def* %dst.1, i32 0, i32 1, i32 0
+  %arrayidx30 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %dst.1, i32 0, i32 1, i32 0
   %rtx31 = bitcast %union.rtunion_def* %arrayidx30 to %struct.rtx_def**
-  %0 = load %struct.rtx_def** %rtx31, align 4
+  %0 = load %struct.rtx_def*, %struct.rtx_def** %rtx31, align 4
   br label %while.cond
 
 if.then46:                                        ; preds = %while.cond
diff --git a/test/CodeGen/ARM/movcc-double.ll b/test/CodeGen/ARM/movcc-double.ll
new file mode 100644
index 000000000000..9ce708d9bd36
--- /dev/null
+++ b/test/CodeGen/ARM/movcc-double.ll
@@ -0,0 +1,50 @@
+; RUN: llc -o - %s | FileCheck %s
+target triple = "arm-unknown-unknown"
+
+; select with and i1/or i1 condition should be implemented as a series of 2
+; cmovs, not by producing two conditions and using and on them.
+
+define i32 @select_and(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5) {
+; CHECK-LABEL: select_and
+; CHECK-NOT: tst
+; CHECK-NOT: movne
+; CHECK: mov{{lo|hs}}
+; CHECK: mov{{lo|hs}}
+  %cmp0 = icmp ult i32 %a0, %a1
+  %cmp1 = icmp ult i32 %a2, %a3
+  %and = and i1 %cmp0, %cmp1
+  %res = select i1 %and, i32 %a4, i32 %a5
+  ret i32 %res
+}
+
+define i32 @select_or(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5) {
+; select with and i1 condition should be implemented as a series of 2 cmovs, not
+; by producing two conditions and using and on them.
+; CHECK-LABEL: select_or
+; CHECK-NOT: orss
+; CHECK-NOT: tst
+; CHECK: mov{{lo|hs}}
+; CHECK: mov{{lo|hs}}
+  %cmp0 = icmp ult i32 %a0, %a1
+  %cmp1 = icmp ult i32 %a2, %a3
+  %and = or i1 %cmp0, %cmp1
+  %res = select i1 %and, i32 %a4, i32 %a5
+  ret i32 %res
+}
+
+; If one of the conditions is materialized as a 0/1 value anyway, then the
+; sequence of 2 cmovs should not be used.
+
+@var32 = global i32 0
+define i32 @select_noopt(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
+; CHECK-LABEL: select_noopt
+; CHECK: orrs
+; CHECK: movne
+  %cmp0 = icmp ult i32 %a0, %a1
+  %cmp1 = icmp ult i32 %a1, %a2
+  %or = or i1 %cmp0, %cmp1
+  %zero_one = zext i1 %or to i32
+  store volatile i32 %zero_one, i32* @var32
+  %res = select i1 %or, i32 %a3, i32 %a4
+  ret i32 %res
+}
diff --git a/test/CodeGen/ARM/mult-alt-generic-arm.ll b/test/CodeGen/ARM/mult-alt-generic-arm.ll
index 05e9b0facd6c..208b05475870 100644
--- a/test/CodeGen/ARM/mult-alt-generic-arm.ll
+++ b/test/CodeGen/ARM/mult-alt-generic-arm.ll
@@ -33,10 +33,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,<r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,r<"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -48,10 +48,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,>r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,r>"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -63,7 +63,7 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
@@ -120,10 +120,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r,imr"(i32 1) nounwind
@@ -137,15 +137,15 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r,X"(i32 1) nounwind
   store i32 %2, i32* %out0, align 4
-  %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %3, i32* %out0, align 4
 ; No lowering support.
 ;  %4 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind
@@ -159,14 +159,14 @@ define arm_aapcscc void @single_p() nounwind {
 entry:
   %out0 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
-  %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
 }
 
 define arm_aapcscc void @multi_m() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*m|r,m|r"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
@@ -191,10 +191,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|<r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|r<"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -206,10 +206,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|>r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|r>"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -221,7 +221,7 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|m"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
@@ -278,10 +278,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 1) nounwind
@@ -295,15 +295,15 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 1) nounwind
   store i32 %2, i32* %out0, align 4
-  %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %3, i32* %out0, align 4
 ; No lowering support.
 ;  %4 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind
@@ -317,7 +317,7 @@ define arm_aapcscc void @multi_p() nounwind {
 entry:
   %out0 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
-  %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
 }
diff --git a/test/CodeGen/ARM/negative-offset.ll b/test/CodeGen/ARM/negative-offset.ll
index 7b949fd71fe1..bafc9645471c 100644
--- a/test/CodeGen/ARM/negative-offset.ll
+++ b/test/CodeGen/ARM/negative-offset.ll
@@ -7,10 +7,10 @@ entry:
 ;CHECK-NOT: sub
 ;CHECK: ldr r{{.*}}, [r0, #-16]
 ;CHECK: ldr r{{.*}}, [r0, #-8]
-  %arrayidx = getelementptr inbounds i32* %p, i32 -4
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %p, i32 -2
-  %1 = load i32* %arrayidx1, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %p, i32 -4
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %p, i32 -2
+  %1 = load i32, i32* %arrayidx1, align 4
   %add = add nsw i32 %1, %0
   ret i32 %add
 }
diff --git a/test/CodeGen/ARM/neon-spfp.ll b/test/CodeGen/ARM/neon-spfp.ll
index dd2e67fe7753..4eeaa8abfab2 100644
--- a/test/CodeGen/ARM/neon-spfp.ll
+++ b/test/CodeGen/ARM/neon-spfp.ll
@@ -64,7 +64,7 @@ for.body:                                         ; preds = %for.body, %entry
 ; CHECK-DARWINA15: vmul.f32 s{{[0-9]*}}
 ; CHECK-DARWINSWIFT: vmul.f32 d{{[0-9]*}}
   %conv = fpext float %mul to double
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), double %conv) #1
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), double %conv) #1
   %inc = add nsw i32 %i.04, 1
   %exitcond = icmp eq i32 %inc, 16000
   br i1 %exitcond, label %for.end, label %for.body
diff --git a/test/CodeGen/ARM/neon-v8.1a.ll b/test/CodeGen/ARM/neon-v8.1a.ll
new file mode 100644
index 000000000000..91259139d446
--- /dev/null
+++ b/test/CodeGen/ARM/neon-v8.1a.ll
@@ -0,0 +1,166 @@
+; RUN: llc < %s -mtriple=armv8 -mattr=+v8.1a | FileCheck %s
+
+;-----------------------------------------------------------------------------
+; RDMA Vector
+
+declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>)
+declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>)
+
+declare <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16>, <8 x i16>)
+declare <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32>, <4 x i32>)
+
+declare <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16>, <8 x i16>)
+declare <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i16> @test_vqrdmlah_v4i16(<4 x i16> %acc, <4 x i16> %mhs, <4 x i16> %rhs) {
+; CHECK-LABEL: test_vqrdmlah_v4i16:
+   %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs,  <4 x i16> %rhs)
+   %retval =  call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %acc,  <4 x i16> %prod)
+; CHECK: vqrdmlah.s16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
+   ret <4 x i16> %retval
+}
+
+define <8 x i16> @test_vqrdmlah_v8i16(<8 x i16> %acc, <8 x i16> %mhs, <8 x i16> %rhs) {
+; CHECK-LABEL: test_vqrdmlah_v8i16:
+   %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
+   %retval =  call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %acc, <8 x i16> %prod)
+; CHECK: vqrdmlah.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
+   ret <8 x i16> %retval
+}
+
+define <2 x i32> @test_vqrdmlah_v2i32(<2 x i32> %acc, <2 x i32> %mhs, <2 x i32> %rhs) {
+; CHECK-LABEL: test_vqrdmlah_v2i32:
+   %prod = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs)
+   %retval =  call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %acc, <2 x i32> %prod)
+; CHECK: vqrdmlah.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
+   ret <2 x i32> %retval
+}
+
+define <4 x i32> @test_vqrdmlah_v4i32(<4 x i32> %acc, <4 x i32> %mhs, <4 x i32> %rhs) {
+; CHECK-LABEL: test_vqrdmlah_v4i32:
+   %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs)
+   %retval =  call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %acc, <4 x i32> %prod)
+; CHECK: vqrdmlah.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
+   ret <4 x i32> %retval
+}
+
+define <4 x i16> @test_vqrdmlsh_v4i16(<4 x i16> %acc, <4 x i16> %mhs, <4 x i16> %rhs) {
+; CHECK-LABEL: test_vqrdmlsh_v4i16:
+   %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs,  <4 x i16> %rhs)
+   %retval =  call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %acc, <4 x i16> %prod)
+; CHECK: vqrdmlsh.s16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
+   ret <4 x i16> %retval
+}
+
+define <8 x i16> @test_vqrdmlsh_v8i16(<8 x i16> %acc, <8 x i16> %mhs, <8 x i16> %rhs) {
+; CHECK-LABEL: test_vqrdmlsh_v8i16:
+   %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
+   %retval =  call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %acc, <8 x i16> %prod)
+; CHECK: vqrdmlsh.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
+   ret <8 x i16> %retval
+}
+
+define <2 x i32> @test_vqrdmlsh_v2i32(<2 x i32> %acc, <2 x i32> %mhs, <2 x i32> %rhs) {
+; CHECK-LABEL: test_vqrdmlsh_v2i32:
+   %prod = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs)
+   %retval =  call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %acc, <2 x i32> %prod)
+; CHECK: vqrdmlsh.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
+   ret <2 x i32> %retval
+}
+
+define <4 x i32> @test_vqrdmlsh_v4i32(<4 x i32> %acc, <4 x i32> %mhs, <4 x i32> %rhs) {
+; CHECK-LABEL: test_vqrdmlsh_v4i32:
+   %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs)
+   %retval =  call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %acc, <4 x i32> %prod)
+; CHECK: vqrdmlsh.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
+   ret <4 x i32> %retval
+}
+
+;-----------------------------------------------------------------------------
+; RDMA Scalar
+
+define <4 x i16> @test_vqrdmlah_lane_s16(<4 x i16> %acc, <4 x i16> %x, <4 x i16> %v) {
+; CHECK-LABEL: test_vqrdmlah_lane_s16:
+entry:
+  %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+  %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle)
+  %retval =  call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %acc, <4 x i16> %prod)
+; CHECK: vqrdmlah.s16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}[3]
+  ret <4 x i16> %retval
+}
+
+define <8 x i16> @test_vqrdmlahq_lane_s16(<8 x i16> %acc, <8 x i16> %x, <4 x i16> %v) {
+; CHECK-LABEL: test_vqrdmlahq_lane_s16:
+entry:
+  %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
+  %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle)
+  %retval =  call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %acc, <8 x i16> %prod)
+; CHECK: vqrdmlah.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{d[0-9]+}}[2]
+  ret <8 x i16> %retval
+}
+
+define <2 x i32> @test_vqrdmlah_lane_s32(<2 x i32> %acc, <2 x i32> %x, <2 x i32> %v) {
+; CHECK-LABEL: test_vqrdmlah_lane_s32:
+entry:
+  %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
+  %prod = tail call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle)
+  %retval =  call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %acc, <2 x i32> %prod)
+; CHECK: vqrdmlah.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}[1]
+  ret <2 x i32> %retval
+}
+
+define <4 x i32> @test_vqrdmlahq_lane_s32(<4 x i32> %acc,<4 x i32> %x, <2 x i32> %v) {
+; CHECK-LABEL: test_vqrdmlahq_lane_s32:
+entry:
+  %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <4 x i32> zeroinitializer
+  %prod = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle)
+  %retval =  call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %acc, <4 x i32> %prod)
+; CHECK: vqrdmlah.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{d[0-9]+}}[0]
+  ret <4 x i32> %retval
+}
+
+define <4 x i16> @test_vqrdmlsh_lane_s16(<4 x i16> %acc, <4 x i16> %x, <4 x i16> %v) {
+; CHECK-LABEL: test_vqrdmlsh_lane_s16:
+entry:
+  %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+  %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle)
+  %retval =  call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %acc, <4 x i16> %prod)
+; CHECK: vqrdmlsh.s16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}[3]
+  ret <4 x i16> %retval
+}
+
+define <8 x i16> @test_vqrdmlshq_lane_s16(<8 x i16> %acc, <8 x i16> %x, <4 x i16> %v) {
+; CHECK-LABEL: test_vqrdmlshq_lane_s16:
+entry:
+  %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
+  %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle)
+  %retval =  call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %acc, <8 x i16> %prod)
+; CHECK: vqrdmlsh.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{d[0-9]+}}[2]
+  ret <8 x i16> %retval
+}
+
+define <2 x i32> @test_vqrdmlsh_lane_s32(<2 x i32> %acc, <2 x i32> %x, <2 x i32> %v) {
+; CHECK-LABEL: test_vqrdmlsh_lane_s32:
+entry:
+  %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
+  %prod = tail call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle)
+  %retval =  call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %acc, <2 x i32> %prod)
+; CHECK: vqrdmlsh.s32  {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}[1]
+  ret <2 x i32> %retval
+}
+
+define <4 x i32> @test_vqrdmlshq_lane_s32(<4 x i32> %acc,<4 x i32> %x, <2 x i32> %v) {
+; CHECK-LABEL: test_vqrdmlshq_lane_s32:
+entry:
+  %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <4 x i32> zeroinitializer
+  %prod = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle)
+  %retval =  call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %acc, <4 x i32> %prod)
+; CHECK: vqrdmlsh.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{d[0-9]+}}[0]
+  ret <4 x i32> %retval
+}
diff --git a/test/CodeGen/ARM/neon_cmp.ll b/test/CodeGen/ARM/neon_cmp.ll
index e1662c43c647..fcf4486fa46d 100644
--- a/test/CodeGen/ARM/neon_cmp.ll
+++ b/test/CodeGen/ARM/neon_cmp.ll
@@ -4,8 +4,8 @@
 ; radar://13191881
 ; CHECK: vfcmp
 define void @vfcmp(<2 x double>* %a, <2 x double>* %b) {
-  %wide.load = load <2 x double>* %a, align 4
-  %wide.load2 = load <2 x double>* %b, align 4
+  %wide.load = load <2 x double>, <2 x double>* %a, align 4
+  %wide.load2 = load <2 x double>, <2 x double>* %b, align 4
 ; CHECK-NOT: vdup.32
 ; CHECK-NOT: vmovn.i64
   %v1 = fcmp olt <2 x double> %wide.load, %wide.load2
diff --git a/test/CodeGen/ARM/neon_div.ll b/test/CodeGen/ARM/neon_div.ll
index 4f1607ed5baf..e185c2a8afbc 100644
--- a/test/CodeGen/ARM/neon_div.ll
+++ b/test/CodeGen/ARM/neon_div.ll
@@ -7,8 +7,8 @@ define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: vrecpe.f32
 ;CHECK: vmovn.i32
 ;CHECK: vmovn.i16
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = sdiv <8 x i8> %tmp1, %tmp2
 	ret <8 x i8> %tmp3
 }
@@ -21,8 +21,8 @@ define <8 x i8> @udivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: vrecps.f32
 ;CHECK: vmovn.i32
 ;CHECK: vqmovun.s16
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = udiv <8 x i8> %tmp1, %tmp2
 	ret <8 x i8> %tmp3
 }
@@ -31,8 +31,8 @@ define <4 x i16> @sdivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: vrecpe.f32
 ;CHECK: vrecps.f32
 ;CHECK: vmovn.i32
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = sdiv <4 x i16> %tmp1, %tmp2
 	ret <4 x i16> %tmp3
 }
@@ -42,8 +42,8 @@ define <4 x i16> @udivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: vrecps.f32
 ;CHECK: vrecps.f32
 ;CHECK: vmovn.i32
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = udiv <4 x i16> %tmp1, %tmp2
 	ret <4 x i16> %tmp3
 }
diff --git a/test/CodeGen/ARM/neon_fpconv.ll b/test/CodeGen/ARM/neon_fpconv.ll
index 8e37ce778182..61ac4098a6dd 100644
--- a/test/CodeGen/ARM/neon_fpconv.ll
+++ b/test/CodeGen/ARM/neon_fpconv.ll
@@ -19,7 +19,7 @@ define <2 x double> @vextend(<2 x float> %a) {
 ; CHECK: vsitofp_double
 define void @vsitofp_double(<2 x i32>* %loadaddr,
                             <2 x double>* %storeaddr) {
-  %v0 = load <2 x i32>* %loadaddr
+  %v0 = load <2 x i32>, <2 x i32>* %loadaddr
 ; CHECK:      vldr
 ; CHECK-NEXT:	vcvt.f64.s32
 ; CHECK-NEXT:	vcvt.f64.s32
@@ -31,7 +31,7 @@ define void @vsitofp_double(<2 x i32>* %loadaddr,
 ; CHECK: vuitofp_double
 define void @vuitofp_double(<2 x i32>* %loadaddr,
                             <2 x double>* %storeaddr) {
-  %v0 = load <2 x i32>* %loadaddr
+  %v0 = load <2 x i32>, <2 x i32>* %loadaddr
 ; CHECK:      vldr
 ; CHECK-NEXT:	vcvt.f64.u32
 ; CHECK-NEXT:	vcvt.f64.u32
diff --git a/test/CodeGen/ARM/neon_ld1.ll b/test/CodeGen/ARM/neon_ld1.ll
index 9fd3fc5f341a..f4d601905537 100644
--- a/test/CodeGen/ARM/neon_ld1.ll
+++ b/test/CodeGen/ARM/neon_ld1.ll
@@ -7,8 +7,8 @@
 ; CHECK: vstr d
 define void @t1(<2 x i32>* %r, <4 x i16>* %a, <4 x i16>* %b) nounwind {
 entry:
-	%0 = load <4 x i16>* %a, align 8		; <<4 x i16>> [#uses=1]
-	%1 = load <4 x i16>* %b, align 8		; <<4 x i16>> [#uses=1]
+	%0 = load <4 x i16>, <4 x i16>* %a, align 8		; <<4 x i16>> [#uses=1]
+	%1 = load <4 x i16>, <4 x i16>* %b, align 8		; <<4 x i16>> [#uses=1]
 	%2 = add <4 x i16> %0, %1		; <<4 x i16>> [#uses=1]
 	%3 = bitcast <4 x i16> %2 to <2 x i32>		; <<2 x i32>> [#uses=1]
 	store <2 x i32> %3, <2 x i32>* %r, align 8
@@ -22,8 +22,8 @@ entry:
 ; CHECK: vmov r0, r1, d
 define <2 x i32> @t2(<4 x i16>* %a, <4 x i16>* %b) nounwind readonly {
 entry:
-	%0 = load <4 x i16>* %a, align 8		; <<4 x i16>> [#uses=1]
-	%1 = load <4 x i16>* %b, align 8		; <<4 x i16>> [#uses=1]
+	%0 = load <4 x i16>, <4 x i16>* %a, align 8		; <<4 x i16>> [#uses=1]
+	%1 = load <4 x i16>, <4 x i16>* %b, align 8		; <<4 x i16>> [#uses=1]
 	%2 = sub <4 x i16> %0, %1		; <<4 x i16>> [#uses=1]
 	%3 = bitcast <4 x i16> %2 to <2 x i32>		; <<2 x i32>> [#uses=1]
 	ret <2 x i32> %3
diff --git a/test/CodeGen/ARM/neon_ld2.ll b/test/CodeGen/ARM/neon_ld2.ll
index 571a16a061df..5bd6ae6d2a98 100644
--- a/test/CodeGen/ARM/neon_ld2.ll
+++ b/test/CodeGen/ARM/neon_ld2.ll
@@ -13,8 +13,8 @@
 ; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
 define void @t1(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 entry:
-	%0 = load <2 x i64>* %a, align 16		; <<2 x i64>> [#uses=1]
-	%1 = load <2 x i64>* %b, align 16		; <<2 x i64>> [#uses=1]
+	%0 = load <2 x i64>, <2 x i64>* %a, align 16		; <<2 x i64>> [#uses=1]
+	%1 = load <2 x i64>, <2 x i64>* %b, align 16		; <<2 x i64>> [#uses=1]
 	%2 = add <2 x i64> %0, %1		; <<2 x i64>> [#uses=1]
 	%3 = bitcast <2 x i64> %2 to <4 x i32>		; <<4 x i32>> [#uses=1]
 	store <4 x i32> %3, <4 x i32>* %r, align 16
@@ -35,8 +35,8 @@ entry:
 ; SWIFT: vmov r2, r3, d
 define <4 x i32> @t2(<2 x i64>* %a, <2 x i64>* %b) nounwind readonly {
 entry:
-	%0 = load <2 x i64>* %a, align 16		; <<2 x i64>> [#uses=1]
-	%1 = load <2 x i64>* %b, align 16		; <<2 x i64>> [#uses=1]
+	%0 = load <2 x i64>, <2 x i64>* %a, align 16		; <<2 x i64>> [#uses=1]
+	%1 = load <2 x i64>, <2 x i64>* %b, align 16		; <<2 x i64>> [#uses=1]
 	%2 = sub <2 x i64> %0, %1		; <<2 x i64>> [#uses=1]
 	%3 = bitcast <2 x i64> %2 to <4 x i32>		; <<4 x i32>> [#uses=1]
 	ret <4 x i32> %3
@@ -50,8 +50,8 @@ entry:
 ; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}}
 define void @t3(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 entry:
-	%0 = load <2 x i64>* %a, align 8
-	%1 = load <2 x i64>* %b, align 8
+	%0 = load <2 x i64>, <2 x i64>* %a, align 8
+	%1 = load <2 x i64>, <2 x i64>* %b, align 8
 	%2 = add <2 x i64> %0, %1
 	%3 = bitcast <2 x i64> %2 to <4 x i32>
 	store <4 x i32> %3, <4 x i32>* %r, align 8
diff --git a/test/CodeGen/ARM/neon_spill.ll b/test/CodeGen/ARM/neon_spill.ll
index d286d16486c1..04f08f43840f 100644
--- a/test/CodeGen/ARM/neon_spill.ll
+++ b/test/CodeGen/ARM/neon_spill.ll
@@ -24,7 +24,7 @@ declare arm_aapcs_vfpcc %2** @func4()
 define arm_aapcs_vfpcc void @foo(%3* nocapture) nounwind align 2 {
   call void @llvm.arm.neon.vst4.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind
   %2 = call arm_aapcs_vfpcc  %0** @func2() nounwind
-  %3 = load %0** %2, align 4
+  %3 = load %0*, %0** %2, align 4
   store float 0.000000e+00, float* undef, align 4
   %4 = call arm_aapcs_vfpcc  %2* @func3(%2* undef, %2* undef, i32 2956) nounwind
   call arm_aapcs_vfpcc  void @func1(%0* %3, float* undef, float* undef, %2* undef)
diff --git a/test/CodeGen/ARM/no-fpu.ll b/test/CodeGen/ARM/no-fpu.ll
index fff4bccb80e9..c5d1f1951d7c 100644
--- a/test/CodeGen/ARM/no-fpu.ll
+++ b/test/CodeGen/ARM/no-fpu.ll
@@ -6,7 +6,7 @@
 ; Check no NEON instructions are selected when feature is disabled.
 define void @neonop(i64* nocapture readonly %a, i64* nocapture %b) #0 {
   %1 = bitcast i64* %a to <2 x i64>*
-  %wide.load = load <2 x i64>* %1, align 8
+  %wide.load = load <2 x i64>, <2 x i64>* %1, align 8
   ; NONEON-NOVFP-NOT: vld1.64
   ; NONEON-NOT: vld1.64
   %add = add <2 x i64> %wide.load, %wide.load
diff --git a/test/CodeGen/ARM/no-tail-call.ll b/test/CodeGen/ARM/no-tail-call.ll
index 3a8cb21bee92..5a5d43c28714 100644
--- a/test/CodeGen/ARM/no-tail-call.ll
+++ b/test/CodeGen/ARM/no-tail-call.ll
@@ -17,28 +17,28 @@ entry:
   %0 = alloca %foo, align 4
   %1 = alloca %foo, align 4
   %2 = alloca %foo, align 4
-  %.native = getelementptr inbounds %foo* %0, i32 0, i32 0
-  %.native.value = getelementptr inbounds %Sf* %.native, i32 0, i32 0
+  %.native = getelementptr inbounds %foo, %foo* %0, i32 0, i32 0
+  %.native.value = getelementptr inbounds %Sf, %Sf* %.native, i32 0, i32 0
   store float 0.000000e+00, float* %.native.value, align 4
-  %.native1 = getelementptr inbounds %foo* %1, i32 0, i32 0
-  %.native1.value = getelementptr inbounds %Sf* %.native1, i32 0, i32 0
+  %.native1 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0
+  %.native1.value = getelementptr inbounds %Sf, %Sf* %.native1, i32 0, i32 0
   store float 1.000000e+00, float* %.native1.value, align 4
-  %.native2 = getelementptr inbounds %foo* %2, i32 0, i32 0
-  %.native2.value = getelementptr inbounds %Sf* %.native2, i32 0, i32 0
+  %.native2 = getelementptr inbounds %foo, %foo* %2, i32 0, i32 0
+  %.native2.value = getelementptr inbounds %Sf, %Sf* %.native2, i32 0, i32 0
   store float 5.000000e+00, float* %.native2.value, align 4
   br i1 true, label %3, label %4
 
 ; <label>:3                                       ; preds = %entry
-  %.native4 = getelementptr inbounds %foo* %1, i32 0, i32 0
-  %.native4.value = getelementptr inbounds %Sf* %.native4, i32 0, i32 0
+  %.native4 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0
+  %.native4.value = getelementptr inbounds %Sf, %Sf* %.native4, i32 0, i32 0
   store float 2.000000e+00, float* %.native4.value, align 4
   br label %4
 
 ; <label>:4                                       ; preds = %3, %entry
   %5 = call float @llvm.ceil.f32(float 5.000000e+00)
-  %.native3 = getelementptr inbounds %foo* %1, i32 0, i32 0
-  %.native3.value = getelementptr inbounds %Sf* %.native3, i32 0, i32 0
-  %6 = load float* %.native3.value, align 4
+  %.native3 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0
+  %.native3.value = getelementptr inbounds %Sf, %Sf* %.native3, i32 0, i32 0
+  %6 = load float, float* %.native3.value, align 4
   %7 = call float @llvm.ceil.f32(float %6)
   %8 = insertvalue { float, float, float } { float 0.000000e+00, float undef, float undef }, float %5, 1
   %9 = insertvalue { float, float, float } %8, float %7, 2
@@ -55,28 +55,28 @@ entry:
   %0 = alloca %foo, align 4
   %1 = alloca %foo, align 4
   %2 = alloca %foo, align 4
-  %.native = getelementptr inbounds %foo* %0, i32 0, i32 0
-  %.native.value = getelementptr inbounds %Sf* %.native, i32 0, i32 0
+  %.native = getelementptr inbounds %foo, %foo* %0, i32 0, i32 0
+  %.native.value = getelementptr inbounds %Sf, %Sf* %.native, i32 0, i32 0
   store float 0.000000e+00, float* %.native.value, align 4
-  %.native1 = getelementptr inbounds %foo* %1, i32 0, i32 0
-  %.native1.value = getelementptr inbounds %Sf* %.native1, i32 0, i32 0
+  %.native1 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0
+  %.native1.value = getelementptr inbounds %Sf, %Sf* %.native1, i32 0, i32 0
   store float 1.000000e+00, float* %.native1.value, align 4
-  %.native2 = getelementptr inbounds %foo* %2, i32 0, i32 0
-  %.native2.value = getelementptr inbounds %Sf* %.native2, i32 0, i32 0
+  %.native2 = getelementptr inbounds %foo, %foo* %2, i32 0, i32 0
+  %.native2.value = getelementptr inbounds %Sf, %Sf* %.native2, i32 0, i32 0
   store float 5.000000e+00, float* %.native2.value, align 4
   br i1 true, label %3, label %4
 
 ; <label>:3                                       ; preds = %entry
-  %.native4 = getelementptr inbounds %foo* %1, i32 0, i32 0
-  %.native4.value = getelementptr inbounds %Sf* %.native4, i32 0, i32 0
+  %.native4 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0
+  %.native4.value = getelementptr inbounds %Sf, %Sf* %.native4, i32 0, i32 0
   store float 2.000000e+00, float* %.native4.value, align 4
   br label %4
 
 ; <label>:4                                       ; preds = %3, %entry
   %5 = call float @llvm.ceil.f32(float 5.000000e+00)
-  %.native3 = getelementptr inbounds %foo* %1, i32 0, i32 0
-  %.native3.value = getelementptr inbounds %Sf* %.native3, i32 0, i32 0
-  %6 = load float* %.native3.value, align 4
+  %.native3 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0
+  %.native3.value = getelementptr inbounds %Sf, %Sf* %.native3, i32 0, i32 0
+  %6 = load float, float* %.native3.value, align 4
   %7 = call float @llvm.ceil.f32(float %6)
   %8 = insertvalue { float, float } { float 0.000000e+00, float undef }, float %7, 1
   ret { float, float } %8
diff --git a/test/CodeGen/ARM/none-macho.ll b/test/CodeGen/ARM/none-macho.ll
index 2a7878fee300..733ba4ba2d2c 100644
--- a/test/CodeGen/ARM/none-macho.ll
+++ b/test/CodeGen/ARM/none-macho.ll
@@ -2,16 +2,11 @@
 ; RUN: llc -mtriple=thumbv7m-none-macho -O0 %s -o - -relocation-model=pic -disable-fp-elim | FileCheck %s
 ; RUN: llc -mtriple=thumbv7m-none-macho -filetype=obj %s -o /dev/null
 
-  ; Bare-metal should probably "declare" segments just like normal MachO
-; CHECK: __picsymbolstub4
-; CHECK: __StaticInit
-; CHECK: __text
-
 @var = external global i32
 
 define i32 @test_litpool() minsize {
 ; CHECK-LABEL: test_litpool:
-  %val = load i32* @var
+  %val = load i32, i32* @var
   ret i32 %val
 
   ; Lit-pool entries need to produce a "$non_lazy_ptr" version of the symbol.
@@ -21,7 +16,7 @@ define i32 @test_litpool() minsize {
 
 define i32 @test_movw_movt() {
 ; CHECK-LABEL: test_movw_movt:
-  %val = load i32* @var
+  %val = load i32, i32* @var
   ret i32 %val
 
   ; movw/movt should also address their symbols MachO-style
@@ -56,7 +51,7 @@ define i32 @test_frame_ptr() {
 %big_arr = type [8 x i32]
 define void @test_two_areas(%big_arr* %addr) {
 ; CHECK-LABEL: test_two_areas:
-  %val = load %big_arr* %addr
+  %val = load %big_arr, %big_arr* %addr
   call void @test_trap()
   store %big_arr %val, %big_arr* %addr
 
diff --git a/test/CodeGen/ARM/noopt-dmb-v7.ll b/test/CodeGen/ARM/noopt-dmb-v7.ll
new file mode 100644
index 000000000000..56a29c8a17e8
--- /dev/null
+++ b/test/CodeGen/ARM/noopt-dmb-v7.ll
@@ -0,0 +1,15 @@
+; Ensure that adjacent duplicated barriers are not removed at -O0.
+; RUN: llc -O0 < %s -mtriple=armv7 -mattr=+db | FileCheck %s
+
+define i32 @t1() {
+entry:
+  fence seq_cst
+  fence seq_cst
+  fence seq_cst
+  ret i32 0
+}
+
+; CHECK: @ BB#0: @ %entry
+; CHECK-NEXT: dmb ish
+; CHECK-NEXT: dmb ish
+; CHECK-NEXT: dmb ish
diff --git a/test/CodeGen/ARM/nop_concat_vectors.ll b/test/CodeGen/ARM/nop_concat_vectors.ll
index c81090095a99..fa0e892f9e24 100644
--- a/test/CodeGen/ARM/nop_concat_vectors.ll
+++ b/test/CodeGen/ARM/nop_concat_vectors.ll
@@ -5,7 +5,7 @@
 ;CHECK-NOT: vst1.32
 ;CHECK: bx
 define void @foo(<16 x i8>* %J) {
-  %A = load <16 x i8>* %J
+  %A = load <16 x i8>, <16 x i8>* %J
   %T1 = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %T2 = shufflevector <8 x i8>  %T1, <8 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   store <16 x i8> %T2, <16 x i8>* %J
diff --git a/test/CodeGen/ARM/null-streamer.ll b/test/CodeGen/ARM/null-streamer.ll
index 350c45e5bebe..19ad22a4bdb8 100644
--- a/test/CodeGen/ARM/null-streamer.ll
+++ b/test/CodeGen/ARM/null-streamer.ll
@@ -5,3 +5,5 @@ define i32 @main()  {
 entry:
   ret i32 0
 }
+
+module asm ".fnstart"
diff --git a/test/CodeGen/ARM/odr_comdat.ll b/test/CodeGen/ARM/odr_comdat.ll
deleted file mode 100644
index e28b5788ef6d..000000000000
--- a/test/CodeGen/ARM/odr_comdat.ll
+++ /dev/null
@@ -1,16 +0,0 @@
-; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=ARMGNUEABI
-
-; Checking that a comdat group gets generated correctly for a static member 
-; of instantiated C++ templates.
-; see http://sourcery.mentor.com/public/cxx-abi/abi.html#vague-itemplate
-; section 5.2.6 Instantiated templates
-; "Any static member data object is emitted in a COMDAT identified by its mangled 
-;  name, in any object file with a reference to its name symbol."
-
-; Case 1: variable is not explicitly initialized, and ends up in a .bss section
-; ARMGNUEABI: .section        .bss._ZN1CIiE1iE,"aGw",%nobits,_ZN1CIiE1iE,comdat
-@_ZN1CIiE1iE = weak_odr global i32 0, align 4
-
-; Case 2: variable is explicitly initialized, and ends up in a .data section
-; ARMGNUEABI: .section        .data._ZN1CIiE1jE,"aGw",%progbits,_ZN1CIiE1jE,comdat
-@_ZN1CIiE1jE = weak_odr global i32 12, align 4
diff --git a/test/CodeGen/ARM/optimize-dmbs-v7.ll b/test/CodeGen/ARM/optimize-dmbs-v7.ll
index 64f5e202d36a..34a55aa718a3 100644
--- a/test/CodeGen/ARM/optimize-dmbs-v7.ll
+++ b/test/CodeGen/ARM/optimize-dmbs-v7.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=armv7 -mattr=+db | FileCheck %s
+; RUN: llc -O1 < %s -mtriple=armv7 -mattr=+db | FileCheck %s
 
 @x1 = global i32 0, align 4
 @x2 = global i32 0, align 4
diff --git a/test/CodeGen/ARM/optselect-regclass.ll b/test/CodeGen/ARM/optselect-regclass.ll
index 0acb2f2f0ecc..4c5d44c352b2 100644
--- a/test/CodeGen/ARM/optselect-regclass.ll
+++ b/test/CodeGen/ARM/optselect-regclass.ll
@@ -9,7 +9,7 @@
 ; Function Attrs: nounwind ssp
 define void @xfr() {
 entry:
-  %bf.load4 = load i32* getelementptr inbounds (%union.opcode.0.2.5.8.15.28* @opcode, i32 0, i32 0), align 4
+  %bf.load4 = load i32, i32* getelementptr inbounds (%union.opcode.0.2.5.8.15.28, %union.opcode.0.2.5.8.15.28* @opcode, i32 0, i32 0), align 4
   %bf.clear10 = and i32 %bf.load4, 65535
   %and11 = and i32 %bf.load4, 32768
   %tobool12 = icmp ne i32 %and11, 0
@@ -17,7 +17,7 @@ entry:
   %or = or i32 %cond13, %bf.clear10
   %shl = shl nuw i32 %or, 2
   %add = add i32 0, %shl
-  tail call void (i8*, i32, i32, i8*, ...)* @__sprintf_chk(i8* getelementptr inbounds ([50 x i8]* @operands, i32 0, i32 0), i32 0, i32 50, i8* getelementptr inbounds ([13 x i8]* @.str86, i32 0, i32 0), i32 undef, i32 undef, i32 %add)
+  tail call void (i8*, i32, i32, i8*, ...) @__sprintf_chk(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @operands, i32 0, i32 0), i32 0, i32 50, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str86, i32 0, i32 0), i32 undef, i32 undef, i32 %add)
   ret void
 }
 
diff --git a/test/CodeGen/ARM/phi.ll b/test/CodeGen/ARM/phi.ll
index 5a8f623e6f50..ff85052175c8 100644
--- a/test/CodeGen/ARM/phi.ll
+++ b/test/CodeGen/ARM/phi.ll
@@ -9,17 +9,17 @@ entry:
   br i1 %a, label %lblock, label %rblock
 
 lblock:
-  %lbranch = getelementptr i32* %b, i32 1
+  %lbranch = getelementptr i32, i32* %b, i32 1
   br label %end
 
 rblock:
-  %rbranch = getelementptr i32* %b, i32 1
+  %rbranch = getelementptr i32, i32* %b, i32 1
   br label %end
   
 end:
 ; CHECK: ldr	r0, [r1, #4]
   %gep = phi i32* [%lbranch, %lblock], [%rbranch, %rblock]
-  %r = load i32* %gep
+  %r = load i32, i32* %gep
 ; CHECK-NEXT: bx	lr
   ret i32 %r
 }
diff --git a/test/CodeGen/ARM/popcnt.ll b/test/CodeGen/ARM/popcnt.ll
index 7ace640c6b61..74f90640ca6e 100644
--- a/test/CodeGen/ARM/popcnt.ll
+++ b/test/CodeGen/ARM/popcnt.ll
@@ -4,7 +4,7 @@
 define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vcnt8:
 ;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)
 	ret <8 x i8> %tmp2
 }
@@ -12,7 +12,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
 define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vcntQ8:
 ;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)
 	ret <16 x i8> %tmp2
 }
@@ -24,7 +24,7 @@ define <4 x i16> @vcnt16(<4 x i16>* %A) nounwind {
 ; CHECK: vadd.i8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
 ; CHECK: vuzp.8 {{d[0-9]+}}, {{d[0-9]+}}
 ; CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.ctpop.v4i16(<4 x i16> %tmp1)
 	ret <4 x i16> %tmp2
 }
@@ -36,7 +36,7 @@ define <8 x i16> @vcntQ16(<8 x i16>* %A) nounwind {
 ; CHECK: vadd.i8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
 ; CHECK: vuzp.8 {{q[0-9]+}}, {{q[0-9]+}}
 ; CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %tmp1)
 	ret <8 x i16> %tmp2
 }
@@ -51,7 +51,7 @@ define <2 x i32> @vcnt32(<2 x i32>* %A) nounwind {
 ; CHECK: vrev32.16 {{d[0-9]+}}, {{d[0-9]+}}
 ; CHECK: vuzp.16 {{d[0-9]+}}, {{d[0-9]+}}
 ; CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %tmp1)
 	ret <2 x i32> %tmp2
 }
@@ -66,7 +66,7 @@ define <4 x i32> @vcntQ32(<4 x i32>* %A) nounwind {
 ; CHECK: vrev32.16 {{q[0-9]+}}, {{q[0-9]+}}
 ; CHECK: vuzp.16 {{q[0-9]+}}, {{q[0-9]+}}
 ; CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %tmp1)
 	ret <4 x i32> %tmp2
 }
@@ -81,7 +81,7 @@ declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
 define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vclz8:
 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
 	ret <8 x i8> %tmp2
 }
@@ -89,7 +89,7 @@ define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vclz16:
 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
 	ret <4 x i16> %tmp2
 }
@@ -97,7 +97,7 @@ define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vclz32:
 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
 	ret <2 x i32> %tmp2
 }
@@ -105,7 +105,7 @@ define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
 define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vclzQ8:
 ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
 	ret <16 x i8> %tmp2
 }
@@ -113,7 +113,7 @@ define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vclzQ16:
 ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
 	ret <8 x i16> %tmp2
 }
@@ -121,7 +121,7 @@ define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vclzQ32:
 ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
 	ret <4 x i32> %tmp2
 }
@@ -137,7 +137,7 @@ declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
 define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vclss8:
 ;CHECK: vcls.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
 	ret <8 x i8> %tmp2
 }
@@ -145,7 +145,7 @@ define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vclss16:
 ;CHECK: vcls.s16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
 	ret <4 x i16> %tmp2
 }
@@ -153,7 +153,7 @@ define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vclss32:
 ;CHECK: vcls.s32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
 	ret <2 x i32> %tmp2
 }
@@ -161,7 +161,7 @@ define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
 define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vclsQs8:
 ;CHECK: vcls.s8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
 	ret <16 x i8> %tmp2
 }
@@ -169,7 +169,7 @@ define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vclsQs16:
 ;CHECK: vcls.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
 	ret <8 x i16> %tmp2
 }
@@ -177,7 +177,7 @@ define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vclsQs32:
 ;CHECK: vcls.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
 	ret <4 x i32> %tmp2
 }
diff --git a/test/CodeGen/ARM/pr13249.ll b/test/CodeGen/ARM/pr13249.ll
index 4bc881035497..cede6007ba16 100644
--- a/test/CodeGen/ARM/pr13249.ll
+++ b/test/CodeGen/ARM/pr13249.ll
@@ -6,19 +6,19 @@ bb:
 
 bb3:                                              ; preds = %bb3, %bb
   %tmp = phi i8* [ %tmp5, %bb3 ], [ %arg, %bb ]
-  %tmp4 = load i8* %tmp, align 1
-  %tmp5 = getelementptr inbounds i8* %tmp, i32 1
+  %tmp4 = load i8, i8* %tmp, align 1
+  %tmp5 = getelementptr inbounds i8, i8* %tmp, i32 1
   br i1 undef, label %bb3, label %bb7
 
 bb7:                                              ; preds = %bb13, %bb3
   %tmp8 = phi i8 [ %tmp14, %bb13 ], [ %tmp4, %bb3 ]
   %tmp9 = phi i8* [ %tmp12, %bb13 ], [ %tmp, %bb3 ]
   %tmp10 = icmp ne i8 %tmp8, %arg1
-  %tmp12 = getelementptr inbounds i8* %tmp9, i32 1
+  %tmp12 = getelementptr inbounds i8, i8* %tmp9, i32 1
   br i1 %tmp10, label %bb13, label %bb15
 
 bb13:                                             ; preds = %bb7
-  %tmp14 = load i8* %tmp12, align 1
+  %tmp14 = load i8, i8* %tmp12, align 1
   br label %bb7
 
 bb15:                                             ; preds = %bb7
diff --git a/test/CodeGen/ARM/pr18364-movw.ll b/test/CodeGen/ARM/pr18364-movw.ll
index fdcf15485f1c..b783522c42b8 100644
--- a/test/CodeGen/ARM/pr18364-movw.ll
+++ b/test/CodeGen/ARM/pr18364-movw.ll
@@ -14,8 +14,8 @@ entry:
   %z = alloca i64, align 8
   store i64 1, i64* %y, align 8
   store i64 11579764786944, i64* %z, align 8
-  %0 = load i64* %y, align 8
-  %1 = load i64* %z, align 8
+  %0 = load i64, i64* %y, align 8
+  %1 = load i64, i64* %z, align 8
   %sub = sub i64 %0, %1
   ret i64 %sub
 }
diff --git a/test/CodeGen/ARM/pr3502.ll b/test/CodeGen/ARM/pr3502.ll
index 606d9698b977..4ec982ebea2b 100644
--- a/test/CodeGen/ARM/pr3502.ll
+++ b/test/CodeGen/ARM/pr3502.ll
@@ -11,7 +11,7 @@ define void @SomeCall(i32 %num) nounwind {
 entry:
 	tail call void asm sideeffect "mcr p15, 0, $0, c7, c10, 4 \0A\09", "r,~{memory}"(i32 0) nounwind
 	tail call void asm sideeffect "mcr p15,0,$0,c7,c14,0", "r,~{memory}"(i32 0) nounwind
-	%0 = load %struct.SHARED_AREA** null, align 4		; <%struct.SHARED_AREA*> [#uses=1]
+	%0 = load %struct.SHARED_AREA*, %struct.SHARED_AREA** null, align 4		; <%struct.SHARED_AREA*> [#uses=1]
 	%1 = ptrtoint %struct.SHARED_AREA* %0 to i32		; <i32> [#uses=1]
 	%2 = lshr i32 %1, 20		; <i32> [#uses=1]
 	%3 = tail call i32 @SetCurrEntry(i32 %2, i32 0) nounwind		; <i32> [#uses=0]
diff --git a/test/CodeGen/ARM/prefetch.ll b/test/CodeGen/ARM/prefetch.ll
index 7fdc5b65c70e..447411d510e9 100644
--- a/test/CodeGen/ARM/prefetch.ll
+++ b/test/CodeGen/ARM/prefetch.ll
@@ -31,7 +31,7 @@ entry:
 
 ; THUMB2-LABEL: t2:
 ; THUMB2: pld [r0, #1023]
-  %tmp = getelementptr i8* %ptr, i32 1023
+  %tmp = getelementptr i8, i8* %ptr, i32 1023
   tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3, i32 1 )
   ret void
 }
@@ -89,8 +89,8 @@ entry:
 ;THUMB2: pld [sp, #50]
 
 %red = alloca [100 x i8], align 1
-%0 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 0
-%1 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 50
+%0 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 0
+%1 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 50
 call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1)
 call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1)
 ret void
diff --git a/test/CodeGen/ARM/print-memb-operand.ll b/test/CodeGen/ARM/print-memb-operand.ll
new file mode 100644
index 000000000000..7748efb3a08a
--- /dev/null
+++ b/test/CodeGen/ARM/print-memb-operand.ll
@@ -0,0 +1,12 @@
+; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s
+
+; CHECK: dmb ld
+
+define void @test2() #0 {
+  call void @llvm.arm.dmb(i32 13)
+  ret void
+}
+
+declare void @llvm.arm.dmb(i32)
+
+attributes #0 = { "target-cpu"="cyclone" }
diff --git a/test/CodeGen/ARM/private.ll b/test/CodeGen/ARM/private.ll
index e48c292db466..fab8f37f989a 100644
--- a/test/CodeGen/ARM/private.ll
+++ b/test/CodeGen/ARM/private.ll
@@ -15,7 +15,7 @@ define private void @foo() {
 
 define i32 @bar() {
         call void @foo()
-	%1 = load i32* @baz, align 4
+	%1 = load i32, i32* @baz, align 4
         ret i32 %1
 }
 
diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll
index feed5ad2830a..507ee48cafc2 100644
--- a/test/CodeGen/ARM/reg_sequence.ll
+++ b/test/CodeGen/ARM/reg_sequence.ll
@@ -19,10 +19,10 @@ entry:
 ; CHECK:        vshrn.i32
 ; CHECK-NOT:    vmov d
 ; CHECK-NEXT:   vst1.16
-  %0 = getelementptr inbounds %struct.int32x4_t* %vT0ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1]
-  %1 = load <4 x i32>* %0, align 16               ; <<4 x i32>> [#uses=1]
-  %2 = getelementptr inbounds %struct.int32x4_t* %vT1ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1]
-  %3 = load <4 x i32>* %2, align 16               ; <<4 x i32>> [#uses=1]
+  %0 = getelementptr inbounds %struct.int32x4_t, %struct.int32x4_t* %vT0ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1]
+  %1 = load <4 x i32>, <4 x i32>* %0, align 16               ; <<4 x i32>> [#uses=1]
+  %2 = getelementptr inbounds %struct.int32x4_t, %struct.int32x4_t* %vT1ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1]
+  %3 = load <4 x i32>, <4 x i32>* %2, align 16               ; <<4 x i32>> [#uses=1]
   %4 = bitcast i16* %i_ptr to i8*                 ; <i8*> [#uses=1]
   %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4, i32 1) ; <<8 x i16>> [#uses=1]
   %6 = bitcast <8 x i16> %5 to <2 x double>       ; <<2 x double>> [#uses=2]
@@ -55,20 +55,20 @@ entry:
 ; CHECK-NOT:    vmov
 ; CHECK:        vst1.16
 ; CHECK:        vst1.16
-  %0 = getelementptr inbounds %struct.int16x8_t* %vT0ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1]
-  %1 = load <8 x i16>* %0, align 16               ; <<8 x i16>> [#uses=1]
-  %2 = getelementptr inbounds %struct.int16x8_t* %vT1ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1]
-  %3 = load <8 x i16>* %2, align 16               ; <<8 x i16>> [#uses=1]
+  %0 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %vT0ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1]
+  %1 = load <8 x i16>, <8 x i16>* %0, align 16               ; <<8 x i16>> [#uses=1]
+  %2 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %vT1ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1]
+  %3 = load <8 x i16>, <8 x i16>* %2, align 16               ; <<8 x i16>> [#uses=1]
   %4 = bitcast i16* %i_ptr to i8*                 ; <i8*> [#uses=1]
   %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4, i32 1) ; <<8 x i16>> [#uses=1]
-  %6 = getelementptr inbounds i16* %i_ptr, i32 8  ; <i16*> [#uses=1]
+  %6 = getelementptr inbounds i16, i16* %i_ptr, i32 8  ; <i16*> [#uses=1]
   %7 = bitcast i16* %6 to i8*                     ; <i8*> [#uses=1]
   %8 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %7, i32 1) ; <<8 x i16>> [#uses=1]
   %9 = mul <8 x i16> %1, %5                       ; <<8 x i16>> [#uses=1]
   %10 = mul <8 x i16> %3, %8                      ; <<8 x i16>> [#uses=1]
   %11 = bitcast i16* %o_ptr to i8*                ; <i8*> [#uses=1]
   tail call void @llvm.arm.neon.vst1.v8i16(i8* %11, <8 x i16> %9, i32 1)
-  %12 = getelementptr inbounds i16* %o_ptr, i32 8 ; <i16*> [#uses=1]
+  %12 = getelementptr inbounds i16, i16* %o_ptr, i32 8 ; <i16*> [#uses=1]
   %13 = bitcast i16* %12 to i8*                   ; <i8*> [#uses=1]
   tail call void @llvm.arm.neon.vst1.v8i16(i8* %13, <8 x i16> %10, i32 1)
   ret void
@@ -102,7 +102,7 @@ entry:
 ; CHECK:        bne
   %tmp1 = bitcast i32* %in to i8*                 ; <i8*> [#uses=1]
   %tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp1, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
-  %tmp3 = getelementptr inbounds i32* %in, i32 8  ; <i32*> [#uses=1]
+  %tmp3 = getelementptr inbounds i32, i32* %in, i32 8  ; <i32*> [#uses=1]
   %tmp4 = bitcast i32* %tmp3 to i8*               ; <i8*> [#uses=1]
   %tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp4, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
   %tmp8 = bitcast i32* %out to i8*                ; <i8*> [#uses=1]
@@ -146,7 +146,7 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind {
 ; CHECK-NOT:    vmov
 ; CHECK:        vadd.i16
   %tmp0 = bitcast i16* %A to i8*                  ; <i8*> [#uses=1]
-  %tmp1 = load <8 x i16>* %B                      ; <<8 x i16>> [#uses=2]
+  %tmp1 = load <8 x i16>, <8 x i16>* %B                      ; <<8 x i16>> [#uses=2]
   %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 1) ; <%struct.__neon_int16x8x2_t> [#uses=2]
   %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 ; <<8 x i16>> [#uses=1]
   %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 ; <<8 x i16>> [#uses=1]
@@ -159,7 +159,7 @@ define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind {
 ; CHECK:        vldr
 ; CHECK:        vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]]
 ; CHECK-NEXT:   vld2.8 {d[[D1]][1], d[[D0]][1]}
-  %tmp1 = load <8 x i8>* %B                       ; <<8 x i8>> [#uses=2]
+  %tmp1 = load <8 x i8>, <8 x i8>* %B                       ; <<8 x i8>> [#uses=2]
   %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2]
   %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 ; <<8 x i8>> [#uses=1]
   %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 ; <<8 x i8>> [#uses=1]
diff --git a/test/CodeGen/ARM/regpair_hint_phys.ll b/test/CodeGen/ARM/regpair_hint_phys.ll
new file mode 100644
index 000000000000..8585a4c207c1
--- /dev/null
+++ b/test/CodeGen/ARM/regpair_hint_phys.ll
@@ -0,0 +1,22 @@
+; RUN: llc -o - %s
+; ARM target used to fail an assertion if RegPair{Odd|Even} hint pointed to a
+; physreg.
+target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7-apple-tvos8.3.0"
+
+declare i8* @llvm.frameaddress(i32) #1
+declare i8* @llvm.returnaddress(i32) #1
+
+@somevar = global [2 x i32] [i32 0, i32 0]
+
+define void @__ubsan_handle_shift_out_of_bounds() #0 {
+entry:
+  %0 = tail call i8* @llvm.frameaddress(i32 0)
+  %1 = ptrtoint i8* %0 to i32
+  %2 = tail call i8* @llvm.returnaddress(i32 0)
+  %3 = ptrtoint i8* %2 to i32
+  %val0 = insertvalue [2 x i32] [i32 undef, i32 undef], i32 %3, 0
+  %val1 = insertvalue [2 x i32] %val0, i32 %1, 1
+  store [2 x i32] %val1, [2 x i32]* @somevar, align 8
+  ret void
+}
diff --git a/test/CodeGen/ARM/saxpy10-a9.ll b/test/CodeGen/ARM/saxpy10-a9.ll
index f8f5e18fcf5e..91610f1a232d 100644
--- a/test/CodeGen/ARM/saxpy10-a9.ll
+++ b/test/CodeGen/ARM/saxpy10-a9.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mtriple=thumbv7-apple-ios7.0.0 -float-abi=hard -mcpu=cortex-a9 -misched-postra -misched-bench -scheditins=false | FileCheck %s
+; RUN: llc < %s -march=arm -mtriple=thumbv7-apple-ios7.0.0 -float-abi=hard -mcpu=cortex-a9 -misched-postra -enable-misched -pre-RA-sched=source -scheditins=false | FileCheck %s
 ;
 ; Test MI-Sched suppory latency based stalls on in in-order pipeline
 ; using the new machine model.
@@ -14,15 +14,12 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-
 ; CHECK: vldr
 ; CHECK: vldr
 ; CHECK: vldr
-; CHECK: vldr
+; CHECK-NEXT: vldr
+; CHECK-NEXT: vmul
 ; CHECK-NEXT: vadd
 ; CHECK-NEXT: vadd
 ; CHECK-NEXT: vldr
 ; CHECK-NEXT: vldr
-; CHECK-NEXT: vldr
-; CHECK-NEXT: vadd
-; CHECK-NEXT: vmul
-; CHECK-NEXT: vldr
 ; CHECK-NEXT: vadd
 ; CHECK-NEXT: vadd
 ; CHECK-NEXT: vmul
@@ -31,6 +28,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-
 ; CHECK-NEXT: vadd
 ; CHECK-NEXT: vldr
 ; CHECK-NEXT: vmul
+; CHECK-NEXT: vldr
 ; CHECK-NEXT: vadd
 ; CHECK-NEXT: vldr
 ; CHECK-NEXT: vadd
@@ -48,6 +46,8 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-
 ; CHECK-NEXT: vmul
 ; CHECK-NEXT: vadd
 ; CHECK-NEXT: vldr
+; CHECK-NEXT: vadd
+; CHECK-NEXT: vldr
 ; CHECK-NEXT: vmul
 ; CHECK-NEXT: vadd
 ; CHECK-NEXT: vldr
@@ -63,72 +63,72 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-
 ; This accumulates a sum rather than storing each result.
 define float @saxpy10(float* nocapture readonly %data1, float* nocapture readonly %data2, float %a) {
 entry:
-  %0 = load float* %data1, align 4
+  %0 = load float, float* %data1, align 4
   %mul = fmul float %0, %a
-  %1 = load float* %data2, align 4
+  %1 = load float, float* %data2, align 4
   %add = fadd float %mul, %1
   %add2 = fadd float %add, 0.000000e+00
-  %arrayidx.1 = getelementptr inbounds float* %data1, i32 1
-  %2 = load float* %arrayidx.1, align 4
+  %arrayidx.1 = getelementptr inbounds float, float* %data1, i32 1
+  %2 = load float, float* %arrayidx.1, align 4
   %mul.1 = fmul float %2, %a
-  %arrayidx1.1 = getelementptr inbounds float* %data2, i32 1
-  %3 = load float* %arrayidx1.1, align 4
+  %arrayidx1.1 = getelementptr inbounds float, float* %data2, i32 1
+  %3 = load float, float* %arrayidx1.1, align 4
   %add.1 = fadd float %mul.1, %3
   %add2.1 = fadd float %add2, %add.1
-  %arrayidx.2 = getelementptr inbounds float* %data1, i32 2
-  %4 = load float* %arrayidx.2, align 4
+  %arrayidx.2 = getelementptr inbounds float, float* %data1, i32 2
+  %4 = load float, float* %arrayidx.2, align 4
   %mul.2 = fmul float %4, %a
-  %arrayidx1.2 = getelementptr inbounds float* %data2, i32 2
-  %5 = load float* %arrayidx1.2, align 4
+  %arrayidx1.2 = getelementptr inbounds float, float* %data2, i32 2
+  %5 = load float, float* %arrayidx1.2, align 4
   %add.2 = fadd float %mul.2, %5
   %add2.2 = fadd float %add2.1, %add.2
-  %arrayidx.3 = getelementptr inbounds float* %data1, i32 3
-  %6 = load float* %arrayidx.3, align 4
+  %arrayidx.3 = getelementptr inbounds float, float* %data1, i32 3
+  %6 = load float, float* %arrayidx.3, align 4
   %mul.3 = fmul float %6, %a
-  %arrayidx1.3 = getelementptr inbounds float* %data2, i32 3
-  %7 = load float* %arrayidx1.3, align 4
+  %arrayidx1.3 = getelementptr inbounds float, float* %data2, i32 3
+  %7 = load float, float* %arrayidx1.3, align 4
   %add.3 = fadd float %mul.3, %7
   %add2.3 = fadd float %add2.2, %add.3
-  %arrayidx.4 = getelementptr inbounds float* %data1, i32 4
-  %8 = load float* %arrayidx.4, align 4
+  %arrayidx.4 = getelementptr inbounds float, float* %data1, i32 4
+  %8 = load float, float* %arrayidx.4, align 4
   %mul.4 = fmul float %8, %a
-  %arrayidx1.4 = getelementptr inbounds float* %data2, i32 4
-  %9 = load float* %arrayidx1.4, align 4
+  %arrayidx1.4 = getelementptr inbounds float, float* %data2, i32 4
+  %9 = load float, float* %arrayidx1.4, align 4
   %add.4 = fadd float %mul.4, %9
   %add2.4 = fadd float %add2.3, %add.4
-  %arrayidx.5 = getelementptr inbounds float* %data1, i32 5
-  %10 = load float* %arrayidx.5, align 4
+  %arrayidx.5 = getelementptr inbounds float, float* %data1, i32 5
+  %10 = load float, float* %arrayidx.5, align 4
   %mul.5 = fmul float %10, %a
-  %arrayidx1.5 = getelementptr inbounds float* %data2, i32 5
-  %11 = load float* %arrayidx1.5, align 4
+  %arrayidx1.5 = getelementptr inbounds float, float* %data2, i32 5
+  %11 = load float, float* %arrayidx1.5, align 4
   %add.5 = fadd float %mul.5, %11
   %add2.5 = fadd float %add2.4, %add.5
-  %arrayidx.6 = getelementptr inbounds float* %data1, i32 6
-  %12 = load float* %arrayidx.6, align 4
+  %arrayidx.6 = getelementptr inbounds float, float* %data1, i32 6
+  %12 = load float, float* %arrayidx.6, align 4
   %mul.6 = fmul float %12, %a
-  %arrayidx1.6 = getelementptr inbounds float* %data2, i32 6
-  %13 = load float* %arrayidx1.6, align 4
+  %arrayidx1.6 = getelementptr inbounds float, float* %data2, i32 6
+  %13 = load float, float* %arrayidx1.6, align 4
   %add.6 = fadd float %mul.6, %13
   %add2.6 = fadd float %add2.5, %add.6
-  %arrayidx.7 = getelementptr inbounds float* %data1, i32 7
-  %14 = load float* %arrayidx.7, align 4
+  %arrayidx.7 = getelementptr inbounds float, float* %data1, i32 7
+  %14 = load float, float* %arrayidx.7, align 4
   %mul.7 = fmul float %14, %a
-  %arrayidx1.7 = getelementptr inbounds float* %data2, i32 7
-  %15 = load float* %arrayidx1.7, align 4
+  %arrayidx1.7 = getelementptr inbounds float, float* %data2, i32 7
+  %15 = load float, float* %arrayidx1.7, align 4
   %add.7 = fadd float %mul.7, %15
   %add2.7 = fadd float %add2.6, %add.7
-  %arrayidx.8 = getelementptr inbounds float* %data1, i32 8
-  %16 = load float* %arrayidx.8, align 4
+  %arrayidx.8 = getelementptr inbounds float, float* %data1, i32 8
+  %16 = load float, float* %arrayidx.8, align 4
   %mul.8 = fmul float %16, %a
-  %arrayidx1.8 = getelementptr inbounds float* %data2, i32 8
-  %17 = load float* %arrayidx1.8, align 4
+  %arrayidx1.8 = getelementptr inbounds float, float* %data2, i32 8
+  %17 = load float, float* %arrayidx1.8, align 4
   %add.8 = fadd float %mul.8, %17
   %add2.8 = fadd float %add2.7, %add.8
-  %arrayidx.9 = getelementptr inbounds float* %data1, i32 9
-  %18 = load float* %arrayidx.9, align 4
+  %arrayidx.9 = getelementptr inbounds float, float* %data1, i32 9
+  %18 = load float, float* %arrayidx.9, align 4
   %mul.9 = fmul float %18, %a
-  %arrayidx1.9 = getelementptr inbounds float* %data2, i32 9
-  %19 = load float* %arrayidx1.9, align 4
+  %arrayidx1.9 = getelementptr inbounds float, float* %data2, i32 9
+  %19 = load float, float* %arrayidx1.9, align 4
   %add.9 = fadd float %mul.9, %19
   %add2.9 = fadd float %add2.8, %add.9
   ret float %add2.9
diff --git a/test/CodeGen/ARM/sched-it-debug-nodes.ll b/test/CodeGen/ARM/sched-it-debug-nodes.ll
new file mode 100644
index 000000000000..7906e7c7581e
--- /dev/null
+++ b/test/CodeGen/ARM/sched-it-debug-nodes.ll
@@ -0,0 +1,88 @@
+; RUN: llc -mtriple thumbv7 -print-before=post-RA-sched -print-after=post-RA-sched %s -o /dev/null 2>&1 | FileCheck %s
+
+; ModuleID = '<stdin>'
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "thumbv7"
+
+%struct.s = type opaque
+
+; Function Attrs: nounwind
+define arm_aapcscc i32 @f(%struct.s* %s, i32 %u, i8* %b, i32 %n) #0 {
+entry:
+  tail call void @llvm.dbg.value(metadata %struct.s* %s, i64 0, metadata !19, metadata !28), !dbg !29
+  tail call void @llvm.dbg.value(metadata i32 %u, i64 0, metadata !20, metadata !28), !dbg !29
+  tail call void @llvm.dbg.value(metadata i8* %b, i64 0, metadata !21, metadata !28), !dbg !29
+  tail call void @llvm.dbg.value(metadata i32 %n, i64 0, metadata !22, metadata !28), !dbg !29
+  %cmp = icmp ult i32 %n, 4, !dbg !30
+  br i1 %cmp, label %return, label %if.end, !dbg !32
+
+if.end:                                           ; preds = %entry
+  tail call arm_aapcscc void @g(%struct.s* %s, i8* %b, i32 %n) #3, !dbg !33
+  br label %return, !dbg !34
+
+return:                                           ; preds = %entry, %if.end
+  %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ]
+  ret i32 %retval.0, !dbg !35
+}
+
+; NOTE: This is checking that the register in the DEBUG_VALUE node is not
+; accidentally being marked as KILL.  The DBG_VALUE node gets introduced in
+; If-Conversion, and gets bundled into the IT block.  The Post RA Scheduler
+; attempts to schedule the Machine Instr, and tries to tag the register in the
+; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen!  (or
+; hopefully, triggering an assert).
+
+; CHECK: BUNDLE %ITSTATE<imp-def,dead>
+; CHECK:  * DBG_VALUE %R1, %noreg, !"u"
+; CHECK-NOT:  * DBG_VALUE %R1<kill>, %noreg, !"u"
+
+declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!23, !24, !25, !26}
+!llvm.ident = !{!27}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0  (llvm/trunk 237059)", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<stdin>", directory: "/Users/compnerd/Source/llvm")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "f", scope: !5, file: !5, line: 9, type: !6, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: true, function: i32 (%struct.s*, i32, i8*, i32)* @f, variables: !18)
+!5 = !DIFile(filename: "<stdin>", directory: "/Users/compnerd/Source/llvm")
+!6 = !DISubroutineType(types: !7)
+!7 = !{!8, !9, !12, !13, !17}
+!8 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 32, align: 32)
+!10 = !DIDerivedType(tag: DW_TAG_typedef, name: "s", file: !5, line: 5, baseType: !11)
+!11 = !DICompositeType(tag: DW_TAG_structure_type, name: "s", file: !5, line: 5, flags: DIFlagFwdDecl)
+!12 = !DIBasicType(name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !14, size: 32, align: 32)
+!14 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !15)
+!15 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint8_t", file: !5, line: 2, baseType: !16)
+!16 = !DIBasicType(name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char)
+!17 = !DIDerivedType(tag: DW_TAG_typedef, name: "size_t", file: !5, line: 3, baseType: !12)
+!18 = !{!19, !20, !21, !22}
+!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "s", arg: 1, scope: !4, file: !5, line: 9, type: !9)
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "u", arg: 2, scope: !4, file: !5, line: 9, type: !12)
+!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", arg: 3, scope: !4, file: !5, line: 9, type: !13)
+!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "n", arg: 4, scope: !4, file: !5, line: 9, type: !17)
+!23 = !{i32 2, !"Dwarf Version", i32 4}
+!24 = !{i32 2, !"Debug Info Version", i32 3}
+!25 = !{i32 1, !"wchar_size", i32 4}
+!26 = !{i32 1, !"min_enum_size", i32 4}
+!27 = !{!"clang version 3.7.0  (llvm/trunk 237059)"}
+!28 = !DIExpression()
+!29 = !DILocation(line: 9, scope: !4)
+!30 = !DILocation(line: 10, scope: !31)
+!31 = distinct !DILexicalBlock(scope: !4, file: !5, line: 10)
+!32 = !DILocation(line: 10, scope: !4)
+!33 = !DILocation(line: 13, scope: !4)
+!34 = !DILocation(line: 14, scope: !4)
+!35 = !DILocation(line: 15, scope: !4)
diff --git a/test/CodeGen/ARM/section-name.ll b/test/CodeGen/ARM/section-name.ll
index a0aad4733bc8..a4c6054197f3 100644
--- a/test/CodeGen/ARM/section-name.ll
+++ b/test/CodeGen/ARM/section-name.ll
@@ -16,7 +16,7 @@ entry:
   ret void
 }
 
-; CHECK: .section .text.test3,"axG",%progbits,test3,comdat
+; CHECK: .text
 ; CHECK: .weak test3
 ; CHECK: .type test3,%function
 define linkonce_odr void @test3() {
diff --git a/test/CodeGen/ARM/segmented-stacks.ll b/test/CodeGen/ARM/segmented-stacks.ll
index 9873bf332948..cbb124de11c3 100644
--- a/test/CodeGen/ARM/segmented-stacks.ll
+++ b/test/CodeGen/ARM/segmented-stacks.ll
@@ -55,7 +55,7 @@ define void @test_basic() #0 {
 }
 
 define i32 @test_nested(i32 * nest %closure, i32 %other) #0 {
-       %addend = load i32 * %closure
+       %addend = load i32 , i32 * %closure
        %result = add i32 %other, %addend
        %mem = alloca i32, i32 10
        call void @dummy_use (i32* %mem, i32 10)
diff --git a/test/CodeGen/ARM/select_xform.ll b/test/CodeGen/ARM/select_xform.ll
index 326eb512d858..460ca8f18405 100644
--- a/test/CodeGen/ARM/select_xform.ll
+++ b/test/CodeGen/ARM/select_xform.ll
@@ -183,7 +183,7 @@ define i32 @t12(i32 %a, i32 %b) nounwind {
 ; Handle frame index operands.
 define void @pr13628() nounwind uwtable align 2 {
   %x3 = alloca i8, i32 256, align 8
-  %x4 = load i8* undef, align 1
+  %x4 = load i8, i8* undef, align 1
   %x5 = icmp ne i8 %x4, 0
   %x6 = select i1 %x5, i8* %x3, i8* null
   call void @bar(i8* %x6) nounwind
diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll
index f14adcae663c..6f5c0e8279a9 100644
--- a/test/CodeGen/ARM/shifter_operand.ll
+++ b/test/CodeGen/ARM/shifter_operand.ll
@@ -43,8 +43,8 @@ entry:
         %tmp3 = inttoptr i32 %tmp2 to i32*
         %tmp4 = add i32 %base2, %tmp1
         %tmp5 = inttoptr i32 %tmp4 to i32*
-        %tmp6 = load i32* %tmp3
-        %tmp7 = load i32* %tmp5
+        %tmp6 = load i32, i32* %tmp3
+        %tmp7 = load i32, i32* %tmp5
         %tmp8 = add i32 %tmp7, %tmp6
         ret i32 %tmp8
 }
@@ -64,11 +64,11 @@ entry:
 ; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
 ; A9: str [[REG]], [r0, r1, lsl #2]
 ; A9-NOT: str [[REG]], [r0]
-  %0 = tail call i8* (...)* @malloc(i32 undef) nounwind
+  %0 = tail call i8* (...) @malloc(i32 undef) nounwind
   %1 = bitcast i8* %0 to i32*
   %2 = sext i16 %addr to i32
-  %3 = getelementptr inbounds i32* %1, i32 %2
-  %4 = load i32* %3, align 4
+  %3 = getelementptr inbounds i32, i32* %1, i32 %2
+  %4 = load i32, i32* %3, align 4
   %5 = add nsw i32 %4, 1
   store i32 %5, i32* %3, align 4
   ret void
diff --git a/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll b/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll
index d8241d0dc380..f85203e381b9 100644
--- a/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll
+++ b/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O1 -mtriple thumbv7-apple-ios6
+; RUN: llc < %s -O1 -mtriple thumbv7-apple-ios6 | FileCheck %s
 ; Just make sure no one tries to make the assumption that the normal edge of an
 ; invoke is never a critical edge.  Previously, this code would assert.
 
@@ -65,3 +65,129 @@ declare i32 @__gxx_personality_sj0(...)
 declare void @release(i8*)
 
 declare void @terminatev()
+
+; Make sure that the instruction DemoteRegToStack inserts to reload
+; %call.i.i.i14.i.i follows the instruction that saves the value to the stack in
+; basic block %entry.do.body.i.i.i_crit_edge.
+; Previously, DemoteRegToStack would insert a load instruction into the entry
+; block to reload %call.i.i.i14.i.i before the phi instruction (%0) in block
+; %do.body.i.i.i.
+
+; CHECK-LABEL: __Z4foo1c:
+; CHECK: blx __Znwm
+; CHECK: {{.*}}@ %entry.do.body.i.i.i_crit_edge
+; CHECK: str r0, [sp, [[OFFSET:#[0-9]+]]]
+; CHECK: ldr [[R0:r[0-9]+]], [sp, [[OFFSET]]]
+; CHECK: {{.*}}@ %do.body.i.i.i
+; CHECK: cbz [[R0]]
+
+%"class.std::__1::basic_string" = type { %"class.std::__1::__compressed_pair" }
+%"class.std::__1::__compressed_pair" = type { %"class.std::__1::__libcpp_compressed_pair_imp" }
+%"class.std::__1::__libcpp_compressed_pair_imp" = type { %"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__rep" }
+%"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__rep" = type { %union.anon }
+%union.anon = type { %"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__long" }
+%"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__long" = type { i32, i32, i8* }
+
+@.str = private unnamed_addr constant [12 x i8] c"some_string\00", align 1
+
+define void @_Z4foo1c(i8 signext %a) {
+entry:
+  %s1 = alloca %"class.std::__1::basic_string", align 4
+  call void @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEPKcm(%"class.std::__1::basic_string"* %s1, i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), i32 11)
+  %call.i.i.i14.i.i = invoke noalias i8* @_Znwm(i32 1024)
+          to label %do.body.i.i.i unwind label %lpad.body
+
+do.body.i.i.i:                                    ; preds = %entry, %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i
+  %lsr.iv = phi i32 [ %lsr.iv.next, %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i ], [ -1024, %entry ]
+  %0 = phi i8* [ %incdec.ptr.i.i.i, %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i ], [ %call.i.i.i14.i.i, %entry ]
+  %new.isnull.i.i.i.i = icmp eq i8* %0, null
+  br i1 %new.isnull.i.i.i.i, label %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i, label %new.notnull.i.i.i.i
+
+new.notnull.i.i.i.i:                              ; preds = %do.body.i.i.i
+  store i8 %a, i8* %0, align 1
+  br label %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i
+
+_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i: ; preds = %new.notnull.i.i.i.i, %do.body.i.i.i
+  %1 = phi i8* [ null, %do.body.i.i.i ], [ %0, %new.notnull.i.i.i.i ]
+  %incdec.ptr.i.i.i = getelementptr inbounds i8, i8* %1, i32 1
+  %lsr.iv.next = add i32 %lsr.iv, 1
+  %cmp.i16.i.i = icmp eq i32 %lsr.iv.next, 0
+  br i1 %cmp.i16.i.i, label %invoke.cont, label %do.body.i.i.i
+
+invoke.cont:                                      ; preds = %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i
+  invoke void @_Z4foo2Pci(i8* %call.i.i.i14.i.i, i32 1024)
+          to label %invoke.cont5 unwind label %lpad2
+
+invoke.cont5:                                     ; preds = %invoke.cont
+  %cmp.i.i.i15 = icmp eq i8* %call.i.i.i14.i.i, null
+  br i1 %cmp.i.i.i15, label %invoke.cont6, label %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i19
+
+_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i19: ; preds = %invoke.cont5
+  call void @_ZdlPv(i8* %call.i.i.i14.i.i)
+  br label %invoke.cont6
+
+invoke.cont6:                                     ; preds = %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i19, %invoke.cont5
+  %call10 = call %"class.std::__1::basic_string"* @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(%"class.std::__1::basic_string"* %s1)
+  ret void
+
+lpad.body:                                        ; preds = %entry
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*)
+          cleanup
+  %3 = extractvalue { i8*, i32 } %2, 0
+  %4 = extractvalue { i8*, i32 } %2, 1
+  br label %ehcleanup
+
+lpad2:                                            ; preds = %invoke.cont
+  %5 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*)
+          cleanup
+  %6 = extractvalue { i8*, i32 } %5, 0
+  %7 = extractvalue { i8*, i32 } %5, 1
+  %cmp.i.i.i21 = icmp eq i8* %call.i.i.i14.i.i, null
+  br i1 %cmp.i.i.i21, label %ehcleanup, label %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26
+
+_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26: ; preds = %lpad2
+  call void @_ZdlPv(i8* %call.i.i.i14.i.i)
+  br label %ehcleanup
+
+ehcleanup:                                        ; preds = %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26, %lpad2, %lpad.body
+  %exn.slot.0 = phi i8* [ %3, %lpad.body ], [ %6, %lpad2 ], [ %6, %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26 ]
+  %ehselector.slot.0 = phi i32 [ %4, %lpad.body ], [ %7, %lpad2 ], [ %7, %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26 ]
+  %call12 = invoke %"class.std::__1::basic_string"* @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(%"class.std::__1::basic_string"* %s1)
+          to label %eh.resume unwind label %terminate.lpad
+
+eh.resume:                                        ; preds = %ehcleanup
+  %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn.slot.0, 0
+  %lpad.val13 = insertvalue { i8*, i32 } %lpad.val, i32 %ehselector.slot.0, 1
+  resume { i8*, i32 } %lpad.val13
+
+terminate.lpad:                                   ; preds = %ehcleanup
+  %8 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*)
+          catch i8* null
+  %9 = extractvalue { i8*, i32 } %8, 0
+  call void @__clang_call_terminate(i8* %9)
+  unreachable
+}
+
+declare void @_Z4foo2Pci(i8*, i32)
+
+define linkonce_odr hidden void @__clang_call_terminate(i8*) {
+  %2 = tail call i8* @__cxa_begin_catch(i8* %0)
+  tail call void @_ZSt9terminatev()
+  unreachable
+}
+
+declare i8* @__cxa_begin_catch(i8*)
+declare void @_ZSt9terminatev()
+declare %"class.std::__1::basic_string"* @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(%"class.std::__1::basic_string"* returned)
+declare void @_ZdlPv(i8*) #3
+declare noalias i8* @_Znwm(i32)
+declare void @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEPKcm(%"class.std::__1::basic_string"*, i8*, i32)
+declare void @_Unwind_SjLj_Register({ i8*, i32, [4 x i32], i8*, i8*, [5 x i8*] }*)
+declare void @_Unwind_SjLj_Unregister({ i8*, i32, [4 x i32], i8*, i8*, [5 x i8*] }*)
+declare i8* @llvm.frameaddress(i32)
+declare i8* @llvm.stacksave()
+declare void @llvm.stackrestore(i8*)
+declare i32 @llvm.eh.sjlj.setjmp(i8*)
+declare i8* @llvm.eh.sjlj.lsda()
+declare void @llvm.eh.sjlj.callsite(i32)
+declare void @llvm.eh.sjlj.functioncontext(i8*)
diff --git a/test/CodeGen/ARM/smul.ll b/test/CodeGen/ARM/smul.ll
index b7ddd10a5682..13873f511e1f 100644
--- a/test/CodeGen/ARM/smul.ll
+++ b/test/CodeGen/ARM/smul.ll
@@ -7,7 +7,7 @@
 define i32 @f1(i32 %y) {
 ; CHECK: f1
 ; CHECK: smulbt
-        %tmp = load i16* @x             ; <i16> [#uses=1]
+        %tmp = load i16, i16* @x             ; <i16> [#uses=1]
         %tmp1 = add i16 %tmp, 2         ; <i16> [#uses=1]
         %tmp2 = sext i16 %tmp1 to i32           ; <i32> [#uses=1]
         %tmp3 = ashr i32 %y, 16         ; <i32> [#uses=1]
diff --git a/test/CodeGen/ARM/space-directive.ll b/test/CodeGen/ARM/space-directive.ll
index 55be1991fe82..24f0d0aadf60 100644
--- a/test/CodeGen/ARM/space-directive.ll
+++ b/test/CodeGen/ARM/space-directive.ll
@@ -11,7 +11,7 @@ define i32 @test_space() minsize {
 ; CHECK: [[PAST_CP]]:
 ; CHECK: .zero 10000
   %addr = inttoptr i32 12345678 to i32*
-  %val = load i32* %addr
+  %val = load i32, i32* %addr
   call i32 @llvm.arm.space(i32 10000, i32 undef)
   ret i32 %val
 }
diff --git a/test/CodeGen/ARM/spill-q.ll b/test/CodeGen/ARM/spill-q.ll
index 425fc12755cd..1a102e3d971f 100644
--- a/test/CodeGen/ARM/spill-q.ll
+++ b/test/CodeGen/ARM/spill-q.ll
@@ -43,7 +43,7 @@ entry:
   store float 0.000000e+00, float* undef, align 4
   %ld12 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
   store float 0.000000e+00, float* undef, align 4
-  %val173 = load <4 x float>* undef               ; <<4 x float>> [#uses=1]
+  %val173 = load <4 x float>, <4 x float>* undef               ; <<4 x float>> [#uses=1]
   br label %bb4
 
 bb4:                                              ; preds = %bb193, %entry
diff --git a/test/CodeGen/ARM/ssp-data-layout.ll b/test/CodeGen/ARM/ssp-data-layout.ll
index e7dafac7020d..92fa0809ed2d 100644
--- a/test/CodeGen/ARM/ssp-data-layout.ll
+++ b/test/CodeGen/ARM/ssp-data-layout.ll
@@ -21,13 +21,13 @@
 define void @layout_ssp() ssp {
 entry:
 ; Expected stack layout for ssp is
-;  180 large_char          . Group 1, nested arrays, arrays >= ssp-buffer-size
-;  172 struct_large_char   .
-;  168 scalar1             | Everything else
-;  164 scalar2
-;  160 scalar3
-;  156 addr-of
-;  152 small_nonchar (84+68)
+;  176 large_char          . Group 1, nested arrays, arrays >= ssp-buffer-size
+;  168 struct_large_char   .
+;  164 scalar1             | Everything else
+;  160 scalar2
+;  156 scalar3
+;  152 addr-of
+;  148 small_nonchar
 ;  112 large_nonchar
 ;  110 small_char
 ;  108 struct_small_char
@@ -35,27 +35,25 @@ entry:
 ;   68 struct_small_nonchar
 
 ; CHECK: layout_ssp:
-; r[[SP]] is used as an offset into the stack later
-; CHECK: add r[[SP:[0-9]+]], sp, #68
 
 ; CHECK: bl get_scalar1
-; CHECK: str r0, [sp, #168]
+; CHECK: str r0, [sp, #164]
 ; CHECK: bl end_scalar1
 
 ; CHECK: bl get_scalar2
-; CHECK: str r0, [sp, #164]
+; CHECK: str r0, [sp, #160]
 ; CHECK: bl end_scalar2
 
 ; CHECK: bl get_scalar3
-; CHECK: str r0, [sp, #160]
+; CHECK: str r0, [sp, #156]
 ; CHECK: bl end_scalar3
 
 ; CHECK: bl get_addrof
-; CHECK: str r0, [sp, #156]
+; CHECK: str r0, [sp, #152]
 ; CHECK: bl end_addrof
 
 ; CHECK: get_small_nonchar
-; CHECK: strh r0, [r[[SP]], #84]
+; CHECK: strh r0, [sp, #148]
 ; CHECK: bl end_small_nonchar
 
 ; CHECK: bl get_large_nonchar
@@ -67,11 +65,11 @@ entry:
 ; CHECK: bl end_small_char
 
 ; CHECK: bl get_large_char
-; CHECK: strb r0, [sp, #180]
+; CHECK: strb r0, [sp, #176]
 ; CHECK: bl end_large_char
 
 ; CHECK: bl get_struct_large_char
-; CHECK: strb r0, [sp, #172]
+; CHECK: strb r0, [sp, #168]
 ; CHECK: bl end_struct_large_char
 
 ; CHECK: bl get_struct_small_char
@@ -83,7 +81,7 @@ entry:
 ; CHECK: bl end_struct_large_nonchar
 
 ; CHECK: bl get_struct_small_nonchar
-; CHECK: strh r0, [r[[SP]]]
+; CHECK: strh r0, [sp, #68]
 ; CHECK: bl end_struct_small_nonchar
   %x = alloca i32, align 4
   %y = alloca i32, align 4
@@ -110,58 +108,58 @@ entry:
   store i32 %call3, i32* %ptr, align 4
   call void @end_addrof()
   %call4 = call signext i16 @get_small_nonchar()
-  %arrayidx = getelementptr inbounds [2 x i16]* %small2, i32 0, i64 0
+  %arrayidx = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i64 0
   store i16 %call4, i16* %arrayidx, align 2
   call void @end_small_nonchar()
   %call5 = call i32 @get_large_nonchar()
-  %arrayidx6 = getelementptr inbounds [8 x i32]* %large2, i32 0, i64 0
+  %arrayidx6 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i64 0
   store i32 %call5, i32* %arrayidx6, align 4
   call void @end_large_nonchar()
   %call7 = call signext i8 @get_small_char()
-  %arrayidx8 = getelementptr inbounds [2 x i8]* %small, i32 0, i64 0
+  %arrayidx8 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i64 0
   store i8 %call7, i8* %arrayidx8, align 1
   call void @end_small_char()
   %call9 = call signext i8 @get_large_char()
-  %arrayidx10 = getelementptr inbounds [8 x i8]* %large, i32 0, i64 0
+  %arrayidx10 = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i64 0
   store i8 %call9, i8* %arrayidx10, align 1
   call void @end_large_char()
   %call11 = call signext i8 @get_struct_large_char()
-  %foo = getelementptr inbounds %struct.struct_large_char* %a, i32 0, i32 0
-  %arrayidx12 = getelementptr inbounds [8 x i8]* %foo, i32 0, i64 0
+  %foo = getelementptr inbounds %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
+  %arrayidx12 = getelementptr inbounds [8 x i8], [8 x i8]* %foo, i32 0, i64 0
   store i8 %call11, i8* %arrayidx12, align 1
   call void @end_struct_large_char()
   %call13 = call signext i8 @get_struct_small_char()
-  %foo14 = getelementptr inbounds %struct.struct_small_char* %b, i32 0, i32 0
-  %arrayidx15 = getelementptr inbounds [2 x i8]* %foo14, i32 0, i64 0
+  %foo14 = getelementptr inbounds %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
+  %arrayidx15 = getelementptr inbounds [2 x i8], [2 x i8]* %foo14, i32 0, i64 0
   store i8 %call13, i8* %arrayidx15, align 1
   call void @end_struct_small_char()
   %call16 = call i32 @get_struct_large_nonchar()
-  %foo17 = getelementptr inbounds %struct.struct_large_nonchar* %c, i32 0, i32 0
-  %arrayidx18 = getelementptr inbounds [8 x i32]* %foo17, i32 0, i64 0
+  %foo17 = getelementptr inbounds %struct.struct_large_nonchar, %struct.struct_large_nonchar* %c, i32 0, i32 0
+  %arrayidx18 = getelementptr inbounds [8 x i32], [8 x i32]* %foo17, i32 0, i64 0
   store i32 %call16, i32* %arrayidx18, align 4
   call void @end_struct_large_nonchar()
   %call19 = call signext i16 @get_struct_small_nonchar()
-  %foo20 = getelementptr inbounds %struct.struct_small_nonchar* %d, i32 0, i32 0
-  %arrayidx21 = getelementptr inbounds [2 x i16]* %foo20, i32 0, i64 0
+  %foo20 = getelementptr inbounds %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
+  %arrayidx21 = getelementptr inbounds [2 x i16], [2 x i16]* %foo20, i32 0, i64 0
   store i16 %call19, i16* %arrayidx21, align 2
   call void @end_struct_small_nonchar()
-  %arraydecay = getelementptr inbounds [8 x i8]* %large, i32 0, i32 0
-  %arraydecay22 = getelementptr inbounds [2 x i8]* %small, i32 0, i32 0
-  %arraydecay23 = getelementptr inbounds [8 x i32]* %large2, i32 0, i32 0
-  %arraydecay24 = getelementptr inbounds [2 x i16]* %small2, i32 0, i32 0
-  %0 = load i32* %x, align 4
-  %1 = load i32* %y, align 4
-  %2 = load i32* %z, align 4
-  %coerce.dive = getelementptr %struct.struct_large_char* %a, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i32 0
+  %arraydecay22 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i32 0
+  %arraydecay23 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i32 0
+  %arraydecay24 = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i32 0
+  %0 = load i32, i32* %x, align 4
+  %1 = load i32, i32* %y, align 4
+  %2 = load i32, i32* %z, align 4
+  %coerce.dive = getelementptr %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
   %3 = bitcast [8 x i8]* %coerce.dive to i64*
-  %4 = load i64* %3, align 1
-  %coerce.dive25 = getelementptr %struct.struct_small_char* %b, i32 0, i32 0
+  %4 = load i64, i64* %3, align 1
+  %coerce.dive25 = getelementptr %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
   %5 = bitcast [2 x i8]* %coerce.dive25 to i16*
-  %6 = load i16* %5, align 1
-  %coerce.dive26 = getelementptr %struct.struct_small_nonchar* %d, i32 0, i32 0
+  %6 = load i16, i16* %5, align 1
+  %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
   %7 = bitcast [2 x i16]* %coerce.dive26 to i32*
-  %8 = load i32* %7, align 1
-  call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
+  %8 = load i32, i32* %7, align 1
+  call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
   ret void
 }
 
@@ -182,8 +180,6 @@ entry:
 ; 68   scalar3                +
 ;   
 ; CHECK: layout_sspstrong:
-; r[[SP]] is used as an offset into the stack later
-; CHECK: add r[[SP:[0-9]+]], sp, #84
 
 ; CHECK: bl get_scalar1
 ; CHECK: str r0, [sp, #76]
@@ -202,7 +198,7 @@ entry:
 ; CHECK: bl end_addrof
 
 ; CHECK: get_small_nonchar
-; CHECK: strh r0, [r[[SP]], #8]
+; CHECK: strh r0, [sp, #92]
 ; CHECK: bl end_small_nonchar
 
 ; CHECK: bl get_large_nonchar
@@ -230,7 +226,7 @@ entry:
 ; CHECK: bl end_struct_large_nonchar
 
 ; CHECK: bl get_struct_small_nonchar
-; CHECK: strh r0, [r[[SP]]]
+; CHECK: strh r0, [sp, #84]
 ; CHECK: bl end_struct_small_nonchar
   %x = alloca i32, align 4
   %y = alloca i32, align 4
@@ -257,58 +253,58 @@ entry:
   store i32 %call3, i32* %ptr, align 4
   call void @end_addrof()
   %call4 = call signext i16 @get_small_nonchar()
-  %arrayidx = getelementptr inbounds [2 x i16]* %small2, i32 0, i64 0
+  %arrayidx = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i64 0
   store i16 %call4, i16* %arrayidx, align 2
   call void @end_small_nonchar()
   %call5 = call i32 @get_large_nonchar()
-  %arrayidx6 = getelementptr inbounds [8 x i32]* %large2, i32 0, i64 0
+  %arrayidx6 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i64 0
   store i32 %call5, i32* %arrayidx6, align 4
   call void @end_large_nonchar()
   %call7 = call signext i8 @get_small_char()
-  %arrayidx8 = getelementptr inbounds [2 x i8]* %small, i32 0, i64 0
+  %arrayidx8 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i64 0
   store i8 %call7, i8* %arrayidx8, align 1
   call void @end_small_char()
   %call9 = call signext i8 @get_large_char()
-  %arrayidx10 = getelementptr inbounds [8 x i8]* %large, i32 0, i64 0
+  %arrayidx10 = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i64 0
   store i8 %call9, i8* %arrayidx10, align 1
   call void @end_large_char()
   %call11 = call signext i8 @get_struct_large_char()
-  %foo = getelementptr inbounds %struct.struct_large_char* %a, i32 0, i32 0
-  %arrayidx12 = getelementptr inbounds [8 x i8]* %foo, i32 0, i64 0
+  %foo = getelementptr inbounds %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
+  %arrayidx12 = getelementptr inbounds [8 x i8], [8 x i8]* %foo, i32 0, i64 0
   store i8 %call11, i8* %arrayidx12, align 1
   call void @end_struct_large_char()
   %call13 = call signext i8 @get_struct_small_char()
-  %foo14 = getelementptr inbounds %struct.struct_small_char* %b, i32 0, i32 0
-  %arrayidx15 = getelementptr inbounds [2 x i8]* %foo14, i32 0, i64 0
+  %foo14 = getelementptr inbounds %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
+  %arrayidx15 = getelementptr inbounds [2 x i8], [2 x i8]* %foo14, i32 0, i64 0
   store i8 %call13, i8* %arrayidx15, align 1
   call void @end_struct_small_char()
   %call16 = call i32 @get_struct_large_nonchar()
-  %foo17 = getelementptr inbounds %struct.struct_large_nonchar* %c, i32 0, i32 0
-  %arrayidx18 = getelementptr inbounds [8 x i32]* %foo17, i32 0, i64 0
+  %foo17 = getelementptr inbounds %struct.struct_large_nonchar, %struct.struct_large_nonchar* %c, i32 0, i32 0
+  %arrayidx18 = getelementptr inbounds [8 x i32], [8 x i32]* %foo17, i32 0, i64 0
   store i32 %call16, i32* %arrayidx18, align 4
   call void @end_struct_large_nonchar()
   %call19 = call signext i16 @get_struct_small_nonchar()
-  %foo20 = getelementptr inbounds %struct.struct_small_nonchar* %d, i32 0, i32 0
-  %arrayidx21 = getelementptr inbounds [2 x i16]* %foo20, i32 0, i64 0
+  %foo20 = getelementptr inbounds %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
+  %arrayidx21 = getelementptr inbounds [2 x i16], [2 x i16]* %foo20, i32 0, i64 0
   store i16 %call19, i16* %arrayidx21, align 2
   call void @end_struct_small_nonchar()
-  %arraydecay = getelementptr inbounds [8 x i8]* %large, i32 0, i32 0
-  %arraydecay22 = getelementptr inbounds [2 x i8]* %small, i32 0, i32 0
-  %arraydecay23 = getelementptr inbounds [8 x i32]* %large2, i32 0, i32 0
-  %arraydecay24 = getelementptr inbounds [2 x i16]* %small2, i32 0, i32 0
-  %0 = load i32* %x, align 4
-  %1 = load i32* %y, align 4
-  %2 = load i32* %z, align 4
-  %coerce.dive = getelementptr %struct.struct_large_char* %a, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i32 0
+  %arraydecay22 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i32 0
+  %arraydecay23 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i32 0
+  %arraydecay24 = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i32 0
+  %0 = load i32, i32* %x, align 4
+  %1 = load i32, i32* %y, align 4
+  %2 = load i32, i32* %z, align 4
+  %coerce.dive = getelementptr %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
   %3 = bitcast [8 x i8]* %coerce.dive to i64*
-  %4 = load i64* %3, align 1
-  %coerce.dive25 = getelementptr %struct.struct_small_char* %b, i32 0, i32 0
+  %4 = load i64, i64* %3, align 1
+  %coerce.dive25 = getelementptr %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
   %5 = bitcast [2 x i8]* %coerce.dive25 to i16*
-  %6 = load i16* %5, align 1
-  %coerce.dive26 = getelementptr %struct.struct_small_nonchar* %d, i32 0, i32 0
+  %6 = load i16, i16* %5, align 1
+  %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
   %7 = bitcast [2 x i16]* %coerce.dive26 to i32*
-  %8 = load i32* %7, align 1
-  call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
+  %8 = load i32, i32* %7, align 1
+  call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
   ret void
 }
 
@@ -317,8 +313,6 @@ entry:
 ; Expected stack layout for sspreq is the same as sspstrong
 ;   
 ; CHECK: layout_sspreq:
-; r[[SP]] is used as an offset into the stack later
-; CHECK: add r[[SP:[0-9]+]], sp, #84
 
 ; CHECK: bl get_scalar1
 ; CHECK: str r0, [sp, #76]
@@ -337,7 +331,7 @@ entry:
 ; CHECK: bl end_addrof
 
 ; CHECK: get_small_nonchar
-; CHECK: strh r0, [r[[SP]], #8]
+; CHECK: strh r0, [sp, #92]
 ; CHECK: bl end_small_nonchar
 
 ; CHECK: bl get_large_nonchar
@@ -365,7 +359,7 @@ entry:
 ; CHECK: bl end_struct_large_nonchar
 
 ; CHECK: bl get_struct_small_nonchar
-; CHECK: strh r0, [r[[SP]]]
+; CHECK: strh r0, [sp, #84]
 ; CHECK: bl end_struct_small_nonchar
   %x = alloca i32, align 4
   %y = alloca i32, align 4
@@ -392,58 +386,58 @@ entry:
   store i32 %call3, i32* %ptr, align 4
   call void @end_addrof()
   %call4 = call signext i16 @get_small_nonchar()
-  %arrayidx = getelementptr inbounds [2 x i16]* %small2, i32 0, i64 0
+  %arrayidx = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i64 0
   store i16 %call4, i16* %arrayidx, align 2
   call void @end_small_nonchar()
   %call5 = call i32 @get_large_nonchar()
-  %arrayidx6 = getelementptr inbounds [8 x i32]* %large2, i32 0, i64 0
+  %arrayidx6 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i64 0
   store i32 %call5, i32* %arrayidx6, align 4
   call void @end_large_nonchar()
   %call7 = call signext i8 @get_small_char()
-  %arrayidx8 = getelementptr inbounds [2 x i8]* %small, i32 0, i64 0
+  %arrayidx8 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i64 0
   store i8 %call7, i8* %arrayidx8, align 1
   call void @end_small_char()
   %call9 = call signext i8 @get_large_char()
-  %arrayidx10 = getelementptr inbounds [8 x i8]* %large, i32 0, i64 0
+  %arrayidx10 = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i64 0
   store i8 %call9, i8* %arrayidx10, align 1
   call void @end_large_char()
   %call11 = call signext i8 @get_struct_large_char()
-  %foo = getelementptr inbounds %struct.struct_large_char* %a, i32 0, i32 0
-  %arrayidx12 = getelementptr inbounds [8 x i8]* %foo, i32 0, i64 0
+  %foo = getelementptr inbounds %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
+  %arrayidx12 = getelementptr inbounds [8 x i8], [8 x i8]* %foo, i32 0, i64 0
   store i8 %call11, i8* %arrayidx12, align 1
   call void @end_struct_large_char()
   %call13 = call signext i8 @get_struct_small_char()
-  %foo14 = getelementptr inbounds %struct.struct_small_char* %b, i32 0, i32 0
-  %arrayidx15 = getelementptr inbounds [2 x i8]* %foo14, i32 0, i64 0
+  %foo14 = getelementptr inbounds %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
+  %arrayidx15 = getelementptr inbounds [2 x i8], [2 x i8]* %foo14, i32 0, i64 0
   store i8 %call13, i8* %arrayidx15, align 1
   call void @end_struct_small_char()
   %call16 = call i32 @get_struct_large_nonchar()
-  %foo17 = getelementptr inbounds %struct.struct_large_nonchar* %c, i32 0, i32 0
-  %arrayidx18 = getelementptr inbounds [8 x i32]* %foo17, i32 0, i64 0
+  %foo17 = getelementptr inbounds %struct.struct_large_nonchar, %struct.struct_large_nonchar* %c, i32 0, i32 0
+  %arrayidx18 = getelementptr inbounds [8 x i32], [8 x i32]* %foo17, i32 0, i64 0
   store i32 %call16, i32* %arrayidx18, align 4
   call void @end_struct_large_nonchar()
   %call19 = call signext i16 @get_struct_small_nonchar()
-  %foo20 = getelementptr inbounds %struct.struct_small_nonchar* %d, i32 0, i32 0
-  %arrayidx21 = getelementptr inbounds [2 x i16]* %foo20, i32 0, i64 0
+  %foo20 = getelementptr inbounds %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
+  %arrayidx21 = getelementptr inbounds [2 x i16], [2 x i16]* %foo20, i32 0, i64 0
   store i16 %call19, i16* %arrayidx21, align 2
   call void @end_struct_small_nonchar()
-  %arraydecay = getelementptr inbounds [8 x i8]* %large, i32 0, i32 0
-  %arraydecay22 = getelementptr inbounds [2 x i8]* %small, i32 0, i32 0
-  %arraydecay23 = getelementptr inbounds [8 x i32]* %large2, i32 0, i32 0
-  %arraydecay24 = getelementptr inbounds [2 x i16]* %small2, i32 0, i32 0
-  %0 = load i32* %x, align 4
-  %1 = load i32* %y, align 4
-  %2 = load i32* %z, align 4
-  %coerce.dive = getelementptr %struct.struct_large_char* %a, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i32 0
+  %arraydecay22 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i32 0
+  %arraydecay23 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i32 0
+  %arraydecay24 = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i32 0
+  %0 = load i32, i32* %x, align 4
+  %1 = load i32, i32* %y, align 4
+  %2 = load i32, i32* %z, align 4
+  %coerce.dive = getelementptr %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
   %3 = bitcast [8 x i8]* %coerce.dive to i64*
-  %4 = load i64* %3, align 1
-  %coerce.dive25 = getelementptr %struct.struct_small_char* %b, i32 0, i32 0
+  %4 = load i64, i64* %3, align 1
+  %coerce.dive25 = getelementptr %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
   %5 = bitcast [2 x i8]* %coerce.dive25 to i16*
-  %6 = load i16* %5, align 1
-  %coerce.dive26 = getelementptr %struct.struct_small_nonchar* %d, i32 0, i32 0
+  %6 = load i16, i16* %5, align 1
+  %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
   %7 = bitcast [2 x i16]* %coerce.dive26 to i32*
-  %8 = load i32* %7, align 1
-  call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
+  %8 = load i32, i32* %7, align 1
+  call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
   ret void
 }
 
@@ -463,26 +457,26 @@ entry:
   %d1 = alloca %struct.struct_large_nonchar, align 8
   %d2 = alloca %struct.struct_small_nonchar, align 2
   %call = call signext i8 @get_struct_small_char()
-  %foo = getelementptr inbounds %struct.struct_small_char* %a, i32 0, i32 0
-  %arrayidx = getelementptr inbounds [2 x i8]* %foo, i32 0, i64 0
+  %foo = getelementptr inbounds %struct.struct_small_char, %struct.struct_small_char* %a, i32 0, i32 0
+  %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* %foo, i32 0, i64 0
   store i8 %call, i8* %arrayidx, align 1
   call void @end_struct_small_char()
   %call1 = call signext i8 @get_struct_large_char2()
-  %foo2 = getelementptr inbounds %struct.struct_large_char2* %b, i32 0, i32 1
-  %arrayidx3 = getelementptr inbounds [8 x i8]* %foo2, i32 0, i64 0
+  %foo2 = getelementptr inbounds %struct.struct_large_char2, %struct.struct_large_char2* %b, i32 0, i32 1
+  %arrayidx3 = getelementptr inbounds [8 x i8], [8 x i8]* %foo2, i32 0, i64 0
   store i8 %call1, i8* %arrayidx3, align 1
   call void @end_struct_large_char2()
   %0 = bitcast %struct.struct_large_char2* %b to %struct.struct_large_char*
-  %coerce.dive = getelementptr %struct.struct_large_char* %0, i32 0, i32 0
+  %coerce.dive = getelementptr %struct.struct_large_char, %struct.struct_large_char* %0, i32 0, i32 0
   %1 = bitcast [8 x i8]* %coerce.dive to i64*
-  %2 = load i64* %1, align 1
-  %coerce.dive4 = getelementptr %struct.struct_small_char* %a, i32 0, i32 0
+  %2 = load i64, i64* %1, align 1
+  %coerce.dive4 = getelementptr %struct.struct_small_char, %struct.struct_small_char* %a, i32 0, i32 0
   %3 = bitcast [2 x i8]* %coerce.dive4 to i16*
-  %4 = load i16* %3, align 1
-  %coerce.dive5 = getelementptr %struct.struct_small_nonchar* %d2, i32 0, i32 0
+  %4 = load i16, i16* %3, align 1
+  %coerce.dive5 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d2, i32 0, i32 0
   %5 = bitcast [2 x i16]* %coerce.dive5 to i32*
-  %6 = load i32* %5, align 1
-  call void @takes_all(i64 %2, i16 %4, %struct.struct_large_nonchar* byval align 8 %d1, i32 %6, i8* null, i8* null, i32* null, i16* null, i32* null, i32 0, i32 0, i32 0)
+  %6 = load i32, i32* %5, align 1
+  call void @takes_all(i64 %2, i16 %4, %struct.struct_large_nonchar* byval align 4 %d1, i32 %6, i8* null, i8* null, i32* null, i16* null, i32* null, i32 0, i32 0, i32 0)
   ret void
 }
 
diff --git a/test/CodeGen/ARM/stack-alignment.ll b/test/CodeGen/ARM/stack-alignment.ll
index 153f92e25f62..ac14a5959d1f 100644
--- a/test/CodeGen/ARM/stack-alignment.ll
+++ b/test/CodeGen/ARM/stack-alignment.ll
@@ -40,65 +40,65 @@ entry:
 ; CHECK-THUMB2:      bfc	r4, #0, #12
 ; CHECK-THUMB2-NEXT: mov	sp, r4
   %a = alloca i8, align 4096
-  %0 = load double* %d, align 4
-  %arrayidx1 = getelementptr inbounds double* %d, i32 1
-  %1 = load double* %arrayidx1, align 4
-  %arrayidx2 = getelementptr inbounds double* %d, i32 2
-  %2 = load double* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds double* %d, i32 3
-  %3 = load double* %arrayidx3, align 4
-  %arrayidx4 = getelementptr inbounds double* %d, i32 4
-  %4 = load double* %arrayidx4, align 4
-  %arrayidx5 = getelementptr inbounds double* %d, i32 5
-  %5 = load double* %arrayidx5, align 4
-  %arrayidx6 = getelementptr inbounds double* %d, i32 6
-  %6 = load double* %arrayidx6, align 4
-  %arrayidx7 = getelementptr inbounds double* %d, i32 7
-  %7 = load double* %arrayidx7, align 4
-  %arrayidx8 = getelementptr inbounds double* %d, i32 8
-  %8 = load double* %arrayidx8, align 4
-  %arrayidx9 = getelementptr inbounds double* %d, i32 9
-  %9 = load double* %arrayidx9, align 4
-  %arrayidx10 = getelementptr inbounds double* %d, i32 10
-  %10 = load double* %arrayidx10, align 4
-  %arrayidx11 = getelementptr inbounds double* %d, i32 11
-  %11 = load double* %arrayidx11, align 4
-  %arrayidx12 = getelementptr inbounds double* %d, i32 12
-  %12 = load double* %arrayidx12, align 4
-  %arrayidx13 = getelementptr inbounds double* %d, i32 13
-  %13 = load double* %arrayidx13, align 4
-  %arrayidx14 = getelementptr inbounds double* %d, i32 14
-  %14 = load double* %arrayidx14, align 4
-  %arrayidx15 = getelementptr inbounds double* %d, i32 15
-  %15 = load double* %arrayidx15, align 4
-  %arrayidx16 = getelementptr inbounds double* %d, i32 16
-  %16 = load double* %arrayidx16, align 4
-  %arrayidx17 = getelementptr inbounds double* %d, i32 17
-  %17 = load double* %arrayidx17, align 4
-  %arrayidx18 = getelementptr inbounds double* %d, i32 18
-  %18 = load double* %arrayidx18, align 4
-  %arrayidx19 = getelementptr inbounds double* %d, i32 19
-  %19 = load double* %arrayidx19, align 4
-  %arrayidx20 = getelementptr inbounds double* %d, i32 20
-  %20 = load double* %arrayidx20, align 4
-  %arrayidx21 = getelementptr inbounds double* %d, i32 21
-  %21 = load double* %arrayidx21, align 4
-  %arrayidx22 = getelementptr inbounds double* %d, i32 22
-  %22 = load double* %arrayidx22, align 4
-  %arrayidx23 = getelementptr inbounds double* %d, i32 23
-  %23 = load double* %arrayidx23, align 4
-  %arrayidx24 = getelementptr inbounds double* %d, i32 24
-  %24 = load double* %arrayidx24, align 4
-  %arrayidx25 = getelementptr inbounds double* %d, i32 25
-  %25 = load double* %arrayidx25, align 4
-  %arrayidx26 = getelementptr inbounds double* %d, i32 26
-  %26 = load double* %arrayidx26, align 4
-  %arrayidx27 = getelementptr inbounds double* %d, i32 27
-  %27 = load double* %arrayidx27, align 4
-  %arrayidx28 = getelementptr inbounds double* %d, i32 28
-  %28 = load double* %arrayidx28, align 4
-  %arrayidx29 = getelementptr inbounds double* %d, i32 29
-  %29 = load double* %arrayidx29, align 4
+  %0 = load double, double* %d, align 4
+  %arrayidx1 = getelementptr inbounds double, double* %d, i32 1
+  %1 = load double, double* %arrayidx1, align 4
+  %arrayidx2 = getelementptr inbounds double, double* %d, i32 2
+  %2 = load double, double* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds double, double* %d, i32 3
+  %3 = load double, double* %arrayidx3, align 4
+  %arrayidx4 = getelementptr inbounds double, double* %d, i32 4
+  %4 = load double, double* %arrayidx4, align 4
+  %arrayidx5 = getelementptr inbounds double, double* %d, i32 5
+  %5 = load double, double* %arrayidx5, align 4
+  %arrayidx6 = getelementptr inbounds double, double* %d, i32 6
+  %6 = load double, double* %arrayidx6, align 4
+  %arrayidx7 = getelementptr inbounds double, double* %d, i32 7
+  %7 = load double, double* %arrayidx7, align 4
+  %arrayidx8 = getelementptr inbounds double, double* %d, i32 8
+  %8 = load double, double* %arrayidx8, align 4
+  %arrayidx9 = getelementptr inbounds double, double* %d, i32 9
+  %9 = load double, double* %arrayidx9, align 4
+  %arrayidx10 = getelementptr inbounds double, double* %d, i32 10
+  %10 = load double, double* %arrayidx10, align 4
+  %arrayidx11 = getelementptr inbounds double, double* %d, i32 11
+  %11 = load double, double* %arrayidx11, align 4
+  %arrayidx12 = getelementptr inbounds double, double* %d, i32 12
+  %12 = load double, double* %arrayidx12, align 4
+  %arrayidx13 = getelementptr inbounds double, double* %d, i32 13
+  %13 = load double, double* %arrayidx13, align 4
+  %arrayidx14 = getelementptr inbounds double, double* %d, i32 14
+  %14 = load double, double* %arrayidx14, align 4
+  %arrayidx15 = getelementptr inbounds double, double* %d, i32 15
+  %15 = load double, double* %arrayidx15, align 4
+  %arrayidx16 = getelementptr inbounds double, double* %d, i32 16
+  %16 = load double, double* %arrayidx16, align 4
+  %arrayidx17 = getelementptr inbounds double, double* %d, i32 17
+  %17 = load double, double* %arrayidx17, align 4
+  %arrayidx18 = getelementptr inbounds double, double* %d, i32 18
+  %18 = load double, double* %arrayidx18, align 4
+  %arrayidx19 = getelementptr inbounds double, double* %d, i32 19
+  %19 = load double, double* %arrayidx19, align 4
+  %arrayidx20 = getelementptr inbounds double, double* %d, i32 20
+  %20 = load double, double* %arrayidx20, align 4
+  %arrayidx21 = getelementptr inbounds double, double* %d, i32 21
+  %21 = load double, double* %arrayidx21, align 4
+  %arrayidx22 = getelementptr inbounds double, double* %d, i32 22
+  %22 = load double, double* %arrayidx22, align 4
+  %arrayidx23 = getelementptr inbounds double, double* %d, i32 23
+  %23 = load double, double* %arrayidx23, align 4
+  %arrayidx24 = getelementptr inbounds double, double* %d, i32 24
+  %24 = load double, double* %arrayidx24, align 4
+  %arrayidx25 = getelementptr inbounds double, double* %d, i32 25
+  %25 = load double, double* %arrayidx25, align 4
+  %arrayidx26 = getelementptr inbounds double, double* %d, i32 26
+  %26 = load double, double* %arrayidx26, align 4
+  %arrayidx27 = getelementptr inbounds double, double* %d, i32 27
+  %27 = load double, double* %arrayidx27, align 4
+  %arrayidx28 = getelementptr inbounds double, double* %d, i32 28
+  %28 = load double, double* %arrayidx28, align 4
+  %arrayidx29 = getelementptr inbounds double, double* %d, i32 29
+  %29 = load double, double* %arrayidx29, align 4
   %div = fdiv double %29, %28
   %div30 = fdiv double %div, %27
   %div31 = fdiv double %div30, %26
@@ -159,6 +159,6 @@ entry:
   %div86 = fdiv double %div85, %29
   %mul = fmul double %div57, %div86
   %conv = fptosi double %mul to i32
-  %add.ptr = getelementptr inbounds i8* %a, i32 %conv
+  %add.ptr = getelementptr inbounds i8, i8* %a, i32 %conv
   ret i8* %add.ptr
 }
diff --git a/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll b/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll
index f5cda14861af..2a7a82da8f69 100644
--- a/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll
+++ b/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll
@@ -14,9 +14,9 @@ target triple = "armv7s-apple-ios6.0.0"
 define i32 @main() #0 {
 entry:
   %title = alloca [15 x i8], align 1
-  %0 = getelementptr inbounds [15 x i8]* %title, i32 0, i32 0
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* getelementptr inbounds ([15 x i8]* @main.title, i32 0, i32 0), i32 15, i32 1, i1 false)
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i8* %0) #3
+  %0 = getelementptr inbounds [15 x i8], [15 x i8]* %title, i32 0, i32 0
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* getelementptr inbounds ([15 x i8], [15 x i8]* @main.title, i32 0, i32 0), i32 15, i32 1, i1 false)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i8* %0) #3
   ret i32 0
 }
 
diff --git a/test/CodeGen/ARM/stack_guard_remat.ll b/test/CodeGen/ARM/stack_guard_remat.ll
index 7c89b99b8f97..99d499498450 100644
--- a/test/CodeGen/ARM/stack_guard_remat.ll
+++ b/test/CodeGen/ARM/stack_guard_remat.ll
@@ -52,7 +52,7 @@ define i32 @test_stack_guard_remat() #0 {
   %a1 = alloca [256 x i32], align 4
   %1 = bitcast [256 x i32]* %a1 to i8*
   call void @llvm.lifetime.start(i64 1024, i8* %1)
-  %2 = getelementptr inbounds [256 x i32]* %a1, i32 0, i32 0
+  %2 = getelementptr inbounds [256 x i32], [256 x i32]* %a1, i32 0, i32 0
   call void @foo3(i32* %2) #3
   call void asm sideeffect "foo2", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{sp},~{lr}"()
   call void @llvm.lifetime.end(i64 1024, i8* %1)
diff --git a/test/CodeGen/ARM/stm.ll b/test/CodeGen/ARM/stm.ll
index 82dc14d14646..88207e6be105 100644
--- a/test/CodeGen/ARM/stm.ll
+++ b/test/CodeGen/ARM/stm.ll
@@ -10,7 +10,7 @@ entry:
 ; CHECK: main
 ; CHECK: push
 ; CHECK: stm
-	%0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([26 x i8]* @"\01LC1", i32 0, i32 0), i32 -2, i32 -3, i32 2, i32 -6) nounwind		; <i32> [#uses=0]
-	%1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([32 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 1, i32 0, i32 1, i32 0, i32 1) nounwind		; <i32> [#uses=0]
+	%0 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([26 x i8], [26 x i8]* @"\01LC1", i32 0, i32 0), i32 -2, i32 -3, i32 2, i32 -6) nounwind		; <i32> [#uses=0]
+	%1 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([32 x i8], [32 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 1, i32 0, i32 1, i32 0, i32 1) nounwind		; <i32> [#uses=0]
 	ret i32 0
 }
diff --git a/test/CodeGen/ARM/str_post.ll b/test/CodeGen/ARM/str_post.ll
index a4f864065d5e..0933e15dab4e 100644
--- a/test/CodeGen/ARM/str_post.ll
+++ b/test/CodeGen/ARM/str_post.ll
@@ -3,7 +3,7 @@
 define i16 @test1(i32* %X, i16* %A) {
 ; CHECK-LABEL: test1:
 ; CHECK: strh {{.*}}[{{.*}}], #-4
-        %Y = load i32* %X               ; <i32> [#uses=1]
+        %Y = load i32, i32* %X               ; <i32> [#uses=1]
         %tmp1 = trunc i32 %Y to i16             ; <i16> [#uses=1]
         store i16 %tmp1, i16* %A
         %tmp2 = ptrtoint i16* %A to i16         ; <i16> [#uses=1]
@@ -14,7 +14,7 @@ define i16 @test1(i32* %X, i16* %A) {
 define i32 @test2(i32* %X, i32* %A) {
 ; CHECK-LABEL: test2:
 ; CHECK: str {{.*}}[{{.*}}],
-        %Y = load i32* %X               ; <i32> [#uses=1]
+        %Y = load i32, i32* %X               ; <i32> [#uses=1]
         store i32 %Y, i32* %A
         %tmp1 = ptrtoint i32* %A to i32         ; <i32> [#uses=1]
         %tmp2 = sub i32 %tmp1, 4                ; <i32> [#uses=1]
diff --git a/test/CodeGen/ARM/str_pre-2.ll b/test/CodeGen/ARM/str_pre-2.ll
index 5ce2bcecb476..4b8b4c6bca72 100644
--- a/test/CodeGen/ARM/str_pre-2.ll
+++ b/test/CodeGen/ARM/str_pre-2.ll
@@ -7,8 +7,8 @@ entry:
 ; CHECK: push {r4, r5, lr}
 ; CHECK: pop {r4, r5, pc}
         call void asm sideeffect "", "~{r4},~{r5}"() nounwind
-	%0 = load i64** @b, align 4
-	%1 = load i64* %0, align 4
+	%0 = load i64*, i64** @b, align 4
+	%1 = load i64, i64* %0, align 4
 	%2 = mul i64 %1, %a
 	ret i64 %2
 }
diff --git a/test/CodeGen/ARM/str_pre.ll b/test/CodeGen/ARM/str_pre.ll
index 60e6e9ecfeb3..848261f83e31 100644
--- a/test/CodeGen/ARM/str_pre.ll
+++ b/test/CodeGen/ARM/str_pre.ll
@@ -1,16 +1,16 @@
 ; RUN: llc -mtriple=arm-eabi %s -o -  | FileCheck %s
 
 define void @test1(i32* %X, i32* %A, i32** %dest) {
-        %B = load i32* %A               ; <i32> [#uses=1]
-        %Y = getelementptr i32* %X, i32 4               ; <i32*> [#uses=2]
+        %B = load i32, i32* %A               ; <i32> [#uses=1]
+        %Y = getelementptr i32, i32* %X, i32 4               ; <i32*> [#uses=2]
         store i32 %B, i32* %Y
         store i32* %Y, i32** %dest
         ret void
 }
 
 define i16* @test2(i16* %X, i32* %A) {
-        %B = load i32* %A               ; <i32> [#uses=1]
-        %Y = getelementptr i16* %X, i32 4               ; <i16*> [#uses=2]
+        %B = load i32, i32* %A               ; <i32> [#uses=1]
+        %Y = getelementptr i16, i16* %X, i32 4               ; <i16*> [#uses=2]
         %tmp = trunc i32 %B to i16              ; <i16> [#uses=1]
         store i16 %tmp, i16* %Y
         ret i16* %Y
diff --git a/test/CodeGen/ARM/struct-byval-frame-index.ll b/test/CodeGen/ARM/struct-byval-frame-index.ll
index 0fd55ec6c943..52f70fe1e0f8 100644
--- a/test/CodeGen/ARM/struct-byval-frame-index.ll
+++ b/test/CodeGen/ARM/struct-byval-frame-index.ll
@@ -72,10 +72,10 @@ declare void @SetMotionVectorsMB(%structK* nocapture, i32) #1
 ; Function Attrs: nounwind
 define void @set_stored_macroblock_parameters() #1 {
 entry:
-  %0 = load %structB** @img, align 4
-  %1 = load i32* undef, align 4
-  %mb_data = getelementptr inbounds %structB* %0, i32 0, i32 61
-  %2 = load %structK** %mb_data, align 4
+  %0 = load %structB*, %structB** @img, align 4
+  %1 = load i32, i32* undef, align 4
+  %mb_data = getelementptr inbounds %structB, %structB* %0, i32 0, i32 61
+  %2 = load %structK*, %structK** %mb_data, align 4
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
@@ -110,7 +110,7 @@ for.body119:                                      ; preds = %for.body119, %for.c
 
 if.end164:                                        ; preds = %for.body119, %for.cond47.preheader, %if.end43
   store i32*** null, i32**** @cofDC, align 4
-  %mb_type = getelementptr inbounds %structK* %2, i32 %1, i32 8
+  %mb_type = getelementptr inbounds %structK, %structK* %2, i32 %1, i32 8
   br i1 undef, label %if.end230, label %if.then169
 
 if.then169:                                       ; preds = %if.end164
@@ -124,7 +124,7 @@ for.cond210.preheader:                            ; preds = %if.then169
 
 if.end230:                                        ; preds = %if.end164
   tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* bitcast ([4 x i32]* @b8mode to i8*), i32 16, i32 4, i1 false)
-  %b8pdir = getelementptr inbounds %structK* %2, i32 %1, i32 15
+  %b8pdir = getelementptr inbounds %structK, %structK* %2, i32 %1, i32 15
   %3 = bitcast [4 x i32]* %b8pdir to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %3, i8* bitcast ([4 x i32]* @b8pdir to i8*), i32 16, i32 4, i1 false)
   br i1 undef, label %if.end236, label %if.then233
@@ -134,7 +134,7 @@ if.then233:                                       ; preds = %if.end230
 
 if.end236:                                        ; preds = %if.end230
   %cmp242 = icmp ne i16 undef, 8
-  %4 = load i32* @luma_transform_size_8x8_flag, align 4
+  %4 = load i32, i32* @luma_transform_size_8x8_flag, align 4
   %tobool245 = icmp ne i32 %4, 0
   %or.cond812 = or i1 %cmp242, %tobool245
   br i1 %or.cond812, label %if.end249, label %land.lhs.true246
@@ -150,51 +150,51 @@ if.then248:                                       ; preds = %land.lhs.true246
   br label %if.end249
 
 if.end249:                                        ; preds = %if.then248, %land.lhs.true246, %if.end236
-  %5 = load i32* @luma_transform_size_8x8_flag, align 4
-  %6 = load %structA** @rdopt, align 4
-  %luma_transform_size_8x8_flag264 = getelementptr inbounds %structA* %6, i32 0, i32 21
+  %5 = load i32, i32* @luma_transform_size_8x8_flag, align 4
+  %6 = load %structA*, %structA** @rdopt, align 4
+  %luma_transform_size_8x8_flag264 = getelementptr inbounds %structA, %structA* %6, i32 0, i32 21
   store i32 %5, i32* %luma_transform_size_8x8_flag264, align 4
-  %7 = load i32* undef, align 4
+  %7 = load i32, i32* undef, align 4
   %add281 = add nsw i32 %7, 0
   br label %for.body285
 
 for.body285:                                      ; preds = %for.inc503, %if.end249
   %8 = phi %structB* [ undef, %if.end249 ], [ %.pre1155, %for.inc503 ]
   %i.21103 = phi i32 [ 0, %if.end249 ], [ %inc504, %for.inc503 ]
-  %block_x286 = getelementptr inbounds %structB* %8, i32 0, i32 37
-  %9 = load i32* %block_x286, align 4
+  %block_x286 = getelementptr inbounds %structB, %structB* %8, i32 0, i32 37
+  %9 = load i32, i32* %block_x286, align 4
   %add287 = add nsw i32 %9, %i.21103
   %shr289 = ashr i32 %i.21103, 1
   %add290 = add nsw i32 %shr289, 0
-  %arrayidx292 = getelementptr inbounds %structK* %2, i32 %1, i32 15, i32 %add290
-  %10 = load %structM** @enc_picture, align 4
-  %ref_idx = getelementptr inbounds %structM* %10, i32 0, i32 35
-  %11 = load i8**** %ref_idx, align 4
-  %12 = load i8*** %11, align 4
-  %arrayidx313 = getelementptr inbounds i8** %12, i32 %add281
-  %13 = load i8** %arrayidx313, align 4
-  %arrayidx314 = getelementptr inbounds i8* %13, i32 %add287
+  %arrayidx292 = getelementptr inbounds %structK, %structK* %2, i32 %1, i32 15, i32 %add290
+  %10 = load %structM*, %structM** @enc_picture, align 4
+  %ref_idx = getelementptr inbounds %structM, %structM* %10, i32 0, i32 35
+  %11 = load i8***, i8**** %ref_idx, align 4
+  %12 = load i8**, i8*** %11, align 4
+  %arrayidx313 = getelementptr inbounds i8*, i8** %12, i32 %add281
+  %13 = load i8*, i8** %arrayidx313, align 4
+  %arrayidx314 = getelementptr inbounds i8, i8* %13, i32 %add287
   store i8 -1, i8* %arrayidx314, align 1
-  %14 = load %structB** @img, align 4
-  %MbaffFrameFlag327 = getelementptr inbounds %structB* %14, i32 0, i32 100
-  %15 = load i32* %MbaffFrameFlag327, align 4
+  %14 = load %structB*, %structB** @img, align 4
+  %MbaffFrameFlag327 = getelementptr inbounds %structB, %structB* %14, i32 0, i32 100
+  %15 = load i32, i32* %MbaffFrameFlag327, align 4
   %tobool328 = icmp eq i32 %15, 0
   br i1 %tobool328, label %if.end454, label %if.then329
 
 if.then329:                                       ; preds = %for.body285
-  %16 = load %structA** @rdopt, align 4
+  %16 = load %structA*, %structA** @rdopt, align 4
   br label %if.end454
 
 if.end454:                                        ; preds = %if.then329, %for.body285
-  %17 = load i32* %arrayidx292, align 4
+  %17 = load i32, i32* %arrayidx292, align 4
   %cmp457 = icmp eq i32 %17, 0
   br i1 %cmp457, label %if.then475, label %lor.lhs.false459
 
 lor.lhs.false459:                                 ; preds = %if.end454
-  %18 = load i32* %mb_type, align 4
+  %18 = load i32, i32* %mb_type, align 4
   switch i32 %18, label %for.inc503 [
     i32 9, label %if.then475
-    i32 10, label %if.then475
+    i32 11, label %if.then475
     i32 13, label %if.then475
     i32 14, label %if.then475
   ]
@@ -205,7 +205,7 @@ if.then475:                                       ; preds = %lor.lhs.false459, %
 
 for.inc503:                                       ; preds = %if.then475, %lor.lhs.false459
   %inc504 = add nsw i32 %i.21103, 1
-  %.pre1155 = load %structB** @img, align 4
+  %.pre1155 = load %structB*, %structB** @img, align 4
   br label %for.body285
 }
 
diff --git a/test/CodeGen/ARM/struct_byval.ll b/test/CodeGen/ARM/struct_byval.ll
index 130925a0c237..d7b9b477ec1e 100644
--- a/test/CodeGen/ARM/struct_byval.ll
+++ b/test/CodeGen/ARM/struct_byval.ll
@@ -1,5 +1,9 @@
 ; RUN: llc < %s -mtriple=armv7-apple-ios6.0 | FileCheck %s
 ; RUN: llc < %s -mtriple=thumbv7-apple-ios6.0 | FileCheck %s -check-prefix=THUMB
+; RUN: llc < %s -mtriple=armv7-unknown-nacl-gnueabi | FileCheck %s -check-prefix=NACL
+; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi | FileCheck %s -check-prefix=NOMOVT
+
+; NOMOVT-NOT: movt
 
 ; rdar://9877866
 %struct.SmallStruct = type { i32, [8 x i32], [37 x i8] }
@@ -33,6 +37,14 @@ entry:
 ; THUMB: sub
 ; THUMB: str
 ; THUMB: bne
+; NACL-LABEL: g:
+; Ensure that use movw instead of constpool for the loop trip count. But don't
+; match the __stack_chk_guard movw
+; NACL: movw r{{[1-9]}}, #
+; NACL: ldr
+; NACL: sub
+; NACL: str
+; NACL: bne
   %st = alloca %struct.LargeStruct, align 4
   %call = call i32 @e2(%struct.LargeStruct* byval %st)
   ret i32 0
@@ -51,6 +63,11 @@ entry:
 ; THUMB: sub
 ; THUMB: vst1
 ; THUMB: bne
+; NACL: movw r{{[1-9]}}, #
+; NACL: vld1
+; NACL: sub
+; NACL: vst1
+; NACL: bne
   %st = alloca %struct.LargeStruct, align 16
   %call = call i32 @e3(%struct.LargeStruct* byval align 16 %st)
   ret i32 0
@@ -80,7 +97,7 @@ define void @f4(%struct.SmallStruct* nocapture byval %s) nounwind optsize {
 ; THUMB-LABEL: f4
 ; THUMB: blx _consumestruct
 entry:
-  %addr = getelementptr inbounds %struct.SmallStruct* %s, i32 0, i32 0
+  %addr = getelementptr inbounds %struct.SmallStruct, %struct.SmallStruct* %s, i32 0, i32 0
   %0 = bitcast i32* %addr to i8*
   tail call void @consumestruct(i8* %0, i32 80) optsize
   ret void
@@ -104,7 +121,7 @@ define void @f6(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture b
 ; THUMB-LABEL: f6
 ; THUMB: b.w _consumestruct
 entry:
-  %addr = getelementptr inbounds %struct.SmallStruct* %s, i32 0, i32 0
+  %addr = getelementptr inbounds %struct.SmallStruct, %struct.SmallStruct* %s, i32 0, i32 0
   %0 = bitcast i32* %addr to i8*
   tail call void @consumestruct(i8* %0, i32 80) optsize
   ret void
diff --git a/test/CodeGen/ARM/sub-cmp-peephole.ll b/test/CodeGen/ARM/sub-cmp-peephole.ll
index f7328dc580ef..32038883469b 100644
--- a/test/CodeGen/ARM/sub-cmp-peephole.ll
+++ b/test/CodeGen/ARM/sub-cmp-peephole.ll
@@ -169,7 +169,7 @@ entry:
 ; CHECK: sub
 ; CHECK: cmp
 ; CHECK: bge
-  %load = load i32* @t, align 4
+  %load = load i32, i32* @t, align 4
   %sub = sub i32 %load, 17
   %cmp = icmp slt i32 %sub, 0
   br i1 %cmp, label %if.then, label %if.else
@@ -191,7 +191,7 @@ entry:
 ; CHECK: sub
 ; CHECK: cmp
 ; CHECK: bhs
-  %load = load i32* @t, align 4
+  %load = load i32, i32* @t, align 4
   %sub = sub i32 %load, 17
   %cmp = icmp ult i32 %sub, 0
   br i1 %cmp, label %if.then, label %if.else
diff --git a/test/CodeGen/ARM/swift-atomics.ll b/test/CodeGen/ARM/swift-atomics.ll
index 8b100f1f41f2..ca7e7fb299bf 100644
--- a/test/CodeGen/ARM/swift-atomics.ll
+++ b/test/CodeGen/ARM/swift-atomics.ll
@@ -33,7 +33,7 @@ define i32 @test_seq_cst(i32* %p, i32 %v) {
 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
 
   store atomic i32 %v, i32* %p seq_cst, align 4
-  %val = load atomic i32* %p seq_cst, align 4
+  %val = load atomic i32, i32* %p seq_cst, align 4
   ret i32 %val
 }
 
@@ -46,6 +46,6 @@ define i32 @test_acq(i32* %addr) {
 
 ; CHECK-STRICT-ATOMIC-LABEL: test_acq:
 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
-  %val = load atomic i32* %addr acquire, align 4
+  %val = load atomic i32, i32* %addr acquire, align 4
   ret i32 %val
 }
diff --git a/test/CodeGen/ARM/swift-vldm.ll b/test/CodeGen/ARM/swift-vldm.ll
index 67ae00ad7db8..9e507279fa09 100644
--- a/test/CodeGen/ARM/swift-vldm.ll
+++ b/test/CodeGen/ARM/swift-vldm.ll
@@ -12,14 +12,14 @@ declare fastcc void @force_register(double %d0, double %d1, double %d2, double %
 
 define void @test_vldm(double* %x, double * %y) {
 entry:
-  %addr1 = getelementptr double * %x, i32 1
-  %addr2 = getelementptr double * %x, i32 2
-  %addr3 = getelementptr double * %x, i32 3
-  %d0 = load double * %y
-  %d1 = load double * %x
-  %d2 = load double * %addr1
-  %d3 = load double * %addr2
-  %d4 = load double * %addr3
+  %addr1 = getelementptr double, double * %x, i32 1
+  %addr2 = getelementptr double, double * %x, i32 2
+  %addr3 = getelementptr double, double * %x, i32 3
+  %d0 = load double , double * %y
+  %d1 = load double , double * %x
+  %d2 = load double , double * %addr1
+  %d3 = load double , double * %addr2
+  %d4 = load double , double * %addr3
   ; We are trying to force x[0-3] in registers d1 to d4 so that we can test we
   ; don't form a "vldmia rX, {d1, d2, d3, d4}".
   ; We are relying on the calling convention and that register allocation
diff --git a/test/CodeGen/ARM/t2abs-killflags.ll b/test/CodeGen/ARM/t2abs-killflags.ll
new file mode 100644
index 000000000000..eed8f6719aec
--- /dev/null
+++ b/test/CodeGen/ARM/t2abs-killflags.ll
@@ -0,0 +1,23 @@
+; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7s-unknown-unknown"
+
+; Test that we don't crash the machine verifier when expanding t2ABS.
+; It was applying the kill flag to its source, even if the original t2ABS didn't
+; kill the operand prior to pseudo expansion.
+
+; Function Attrs: noreturn
+declare void @foo(i32, i32) #0
+
+; CHECK-LABEL: @test
+; CHECK: rsbmi
+define void @test(i32 %arg) {
+  %cmp58 = icmp slt i32 %arg, 0
+  %sub62 = sub nsw i32 0, %arg
+  %l.1 = select i1 %cmp58, i32 %sub62, i32 %arg
+  call void @foo(i32 %l.1, i32 %arg) #0
+  unreachable
+}
+
+attributes #0 = { noreturn }
diff --git a/test/CodeGen/ARM/tail-dup-kill-flags.ll b/test/CodeGen/ARM/tail-dup-kill-flags.ll
new file mode 100644
index 000000000000..bce6cdc4e28d
--- /dev/null
+++ b/test/CodeGen/ARM/tail-dup-kill-flags.ll
@@ -0,0 +1,54 @@
+; RUN: llc %s -o - -fast-isel=true -O1 -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7-apple-ios8.0.0"
+
+; Tail duplication was incorrectly leaving kill flags on the duplicated instructions.
+; The machine verifier is able to spot this error, so this test should pass if it passes verification.
+
+; CHECK-LABEL: @test
+
+%struct.cdiff_ctx = type { i8*, %struct.cdiff_node*, %struct.cdiff_node*, %struct.cdiff_node*, %struct.cdiff_node* }
+%struct.cdiff_node = type { i32, i8*, i8*, %struct.cdiff_node* }
+
+declare i32 @logg(i32)
+
+define hidden i32 @test(%struct.cdiff_ctx* nocapture %ctx, %struct.cdiff_node* %tmp10) {
+bb:
+  br label %.outer
+
+bb33:                                             ; preds = %bb92, %.outer
+  %lines.0 = phi i32 [ %tmp37, %bb92 ], [ %lines.0.ph, %.outer ]
+  %tmp37 = add i32 %lines.0, 1
+  %tmp39 = load i32, i32* %tmp57, align 4
+  %tmp40 = icmp eq i32 %tmp39, %tmp37
+  br i1 %tmp40, label %bb41, label %bb92
+
+bb41:                                             ; preds = %bb33
+  %tmp45 = call i32 @strncmp()
+  %tmp46 = icmp eq i32 %tmp45, 0
+  br i1 %tmp46, label %bb53, label %bb47
+
+bb47:                                             ; preds = %bb41
+  %tmp52 = call i32 @logg(i32 %tmp37)
+  ret i32 -1
+
+bb53:                                             ; preds = %bb41
+  %tmp54 = getelementptr inbounds %struct.cdiff_node, %struct.cdiff_node* %del.0.ph, i32 0, i32 3
+  %tmp55 = load %struct.cdiff_node*, %struct.cdiff_node** %tmp54, align 4
+  br label %.outer
+
+.outer:                                           ; preds = %bb53, %bb
+  %del.0.ph = phi %struct.cdiff_node* [ %tmp55, %bb53 ], [ null, %bb ]
+  %lines.0.ph = phi i32 [ 1, %bb53 ], [ 0, %bb ]
+  %tmp57 = getelementptr inbounds %struct.cdiff_node, %struct.cdiff_node* %del.0.ph, i32 0, i32 0
+  br label %bb33
+
+bb92:                                             ; preds = %bb33
+  %tmp93 = call i32 @puts()
+  br label %bb33
+}
+
+declare i32 @strncmp()
+
+declare i32 @puts()
diff --git a/test/CodeGen/ARM/tail-dup.ll b/test/CodeGen/ARM/tail-dup.ll
index d654056eaf3d..407bdf7524b1 100644
--- a/test/CodeGen/ARM/tail-dup.ll
+++ b/test/CodeGen/ARM/tail-dup.ll
@@ -11,28 +11,28 @@
 
 define i32 @fn(i32* nocapture %opcodes) nounwind readonly ssp {
 entry:
-  %0 = load i32* %opcodes, align 4
-  %arrayidx = getelementptr inbounds [3 x i8*]* @fn.codetable, i32 0, i32 %0
+  %0 = load i32, i32* %opcodes, align 4
+  %arrayidx = getelementptr inbounds [3 x i8*], [3 x i8*]* @fn.codetable, i32 0, i32 %0
   br label %indirectgoto
 
 INCREMENT:                                        ; preds = %indirectgoto
   %inc = add nsw i32 %result.0, 1
-  %1 = load i32* %opcodes.addr.0, align 4
-  %arrayidx2 = getelementptr inbounds [3 x i8*]* @fn.codetable, i32 0, i32 %1
+  %1 = load i32, i32* %opcodes.addr.0, align 4
+  %arrayidx2 = getelementptr inbounds [3 x i8*], [3 x i8*]* @fn.codetable, i32 0, i32 %1
   br label %indirectgoto
 
 DECREMENT:                                        ; preds = %indirectgoto
   %dec = add nsw i32 %result.0, -1
-  %2 = load i32* %opcodes.addr.0, align 4
-  %arrayidx4 = getelementptr inbounds [3 x i8*]* @fn.codetable, i32 0, i32 %2
+  %2 = load i32, i32* %opcodes.addr.0, align 4
+  %arrayidx4 = getelementptr inbounds [3 x i8*], [3 x i8*]* @fn.codetable, i32 0, i32 %2
   br label %indirectgoto
 
 indirectgoto:                                     ; preds = %DECREMENT, %INCREMENT, %entry
   %result.0 = phi i32 [ 0, %entry ], [ %dec, %DECREMENT ], [ %inc, %INCREMENT ]
   %opcodes.pn = phi i32* [ %opcodes, %entry ], [ %opcodes.addr.0, %DECREMENT ], [ %opcodes.addr.0, %INCREMENT ]
   %indirect.goto.dest.in = phi i8** [ %arrayidx, %entry ], [ %arrayidx4, %DECREMENT ], [ %arrayidx2, %INCREMENT ]
-  %opcodes.addr.0 = getelementptr inbounds i32* %opcodes.pn, i32 1
-  %indirect.goto.dest = load i8** %indirect.goto.dest.in, align 4
+  %opcodes.addr.0 = getelementptr inbounds i32, i32* %opcodes.pn, i32 1
+  %indirect.goto.dest = load i8*, i8** %indirect.goto.dest.in, align 4
   indirectbr i8* %indirect.goto.dest, [label %RETURN, label %INCREMENT, label %DECREMENT]
 
 RETURN:                                           ; preds = %indirectgoto
diff --git a/test/CodeGen/ARM/test-sharedidx.ll b/test/CodeGen/ARM/test-sharedidx.ll
index 9203f166ffa9..377996c4c3c8 100644
--- a/test/CodeGen/ARM/test-sharedidx.ll
+++ b/test/CodeGen/ARM/test-sharedidx.ll
@@ -23,15 +23,15 @@ for.body:                                         ; preds = %entry, %for.body.3
 ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]!
 ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]!
   %i.09 = phi i32 [ %add5.3, %for.body.3 ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i8* %a, i32 %i.09
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %a, i32 %i.09
+  %0 = load i8, i8* %arrayidx, align 1
   %conv6 = zext i8 %0 to i32
-  %arrayidx1 = getelementptr inbounds i8* %b, i32 %i.09
-  %1 = load i8* %arrayidx1, align 1
+  %arrayidx1 = getelementptr inbounds i8, i8* %b, i32 %i.09
+  %1 = load i8, i8* %arrayidx1, align 1
   %conv27 = zext i8 %1 to i32
   %add = add nsw i32 %conv27, %conv6
   %conv3 = trunc i32 %add to i8
-  %arrayidx4 = getelementptr inbounds i8* %c, i32 %i.09
+  %arrayidx4 = getelementptr inbounds i8, i8* %c, i32 %i.09
   store i8 %conv3, i8* %arrayidx4, align 1
   %add5 = add i32 %i.09, %s
   %cmp = icmp ult i32 %add5, %len
@@ -44,15 +44,15 @@ for.body.1:                                       ; preds = %for.body
 ; CHECK: %for.body.1
 ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]!
 ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]!
-  %arrayidx.1 = getelementptr inbounds i8* %a, i32 %add5
-  %2 = load i8* %arrayidx.1, align 1
+  %arrayidx.1 = getelementptr inbounds i8, i8* %a, i32 %add5
+  %2 = load i8, i8* %arrayidx.1, align 1
   %conv6.1 = zext i8 %2 to i32
-  %arrayidx1.1 = getelementptr inbounds i8* %b, i32 %add5
-  %3 = load i8* %arrayidx1.1, align 1
+  %arrayidx1.1 = getelementptr inbounds i8, i8* %b, i32 %add5
+  %3 = load i8, i8* %arrayidx1.1, align 1
   %conv27.1 = zext i8 %3 to i32
   %add.1 = add nsw i32 %conv27.1, %conv6.1
   %conv3.1 = trunc i32 %add.1 to i8
-  %arrayidx4.1 = getelementptr inbounds i8* %c, i32 %add5
+  %arrayidx4.1 = getelementptr inbounds i8, i8* %c, i32 %add5
   store i8 %conv3.1, i8* %arrayidx4.1, align 1
   %add5.1 = add i32 %add5, %s
   %cmp.1 = icmp ult i32 %add5.1, %len
@@ -62,15 +62,15 @@ for.body.2:                                       ; preds = %for.body.1
 ; CHECK: %for.body.2
 ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]!
 ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]!
-  %arrayidx.2 = getelementptr inbounds i8* %a, i32 %add5.1
-  %4 = load i8* %arrayidx.2, align 1
+  %arrayidx.2 = getelementptr inbounds i8, i8* %a, i32 %add5.1
+  %4 = load i8, i8* %arrayidx.2, align 1
   %conv6.2 = zext i8 %4 to i32
-  %arrayidx1.2 = getelementptr inbounds i8* %b, i32 %add5.1
-  %5 = load i8* %arrayidx1.2, align 1
+  %arrayidx1.2 = getelementptr inbounds i8, i8* %b, i32 %add5.1
+  %5 = load i8, i8* %arrayidx1.2, align 1
   %conv27.2 = zext i8 %5 to i32
   %add.2 = add nsw i32 %conv27.2, %conv6.2
   %conv3.2 = trunc i32 %add.2 to i8
-  %arrayidx4.2 = getelementptr inbounds i8* %c, i32 %add5.1
+  %arrayidx4.2 = getelementptr inbounds i8, i8* %c, i32 %add5.1
   store i8 %conv3.2, i8* %arrayidx4.2, align 1
   %add5.2 = add i32 %add5.1, %s
   %cmp.2 = icmp ult i32 %add5.2, %len
@@ -80,15 +80,15 @@ for.body.3:                                       ; preds = %for.body.2
 ; CHECK: %for.body.3
 ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]!
 ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]!
-  %arrayidx.3 = getelementptr inbounds i8* %a, i32 %add5.2
-  %6 = load i8* %arrayidx.3, align 1
+  %arrayidx.3 = getelementptr inbounds i8, i8* %a, i32 %add5.2
+  %6 = load i8, i8* %arrayidx.3, align 1
   %conv6.3 = zext i8 %6 to i32
-  %arrayidx1.3 = getelementptr inbounds i8* %b, i32 %add5.2
-  %7 = load i8* %arrayidx1.3, align 1
+  %arrayidx1.3 = getelementptr inbounds i8, i8* %b, i32 %add5.2
+  %7 = load i8, i8* %arrayidx1.3, align 1
   %conv27.3 = zext i8 %7 to i32
   %add.3 = add nsw i32 %conv27.3, %conv6.3
   %conv3.3 = trunc i32 %add.3 to i8
-  %arrayidx4.3 = getelementptr inbounds i8* %c, i32 %add5.2
+  %arrayidx4.3 = getelementptr inbounds i8, i8* %c, i32 %add5.2
   store i8 %conv3.3, i8* %arrayidx4.3, align 1
   %add5.3 = add i32 %add5.2, %s
   %cmp.3 = icmp ult i32 %add5.3, %len
diff --git a/test/CodeGen/ARM/this-return.ll b/test/CodeGen/ARM/this-return.ll
index c681a1c80958..802f880c1380 100644
--- a/test/CodeGen/ARM/this-return.ll
+++ b/test/CodeGen/ARM/this-return.ll
@@ -29,7 +29,7 @@ entry:
 ; CHECKT2D: b.w _B_ctor_base
   %0 = bitcast %struct.C* %this to %struct.A*
   %call = tail call %struct.A* @A_ctor_base(%struct.A* %0)
-  %1 = getelementptr inbounds %struct.C* %this, i32 0, i32 0
+  %1 = getelementptr inbounds %struct.C, %struct.C* %this, i32 0, i32 0
   %call2 = tail call %struct.B* @B_ctor_base(%struct.B* %1, i32 %x)
   ret %struct.C* %this
 }
@@ -48,7 +48,7 @@ entry:
 ; CHECKT2D-NOT: b.w _B_ctor_base_nothisret
   %0 = bitcast %struct.C* %this to %struct.A*
   %call = tail call %struct.A* @A_ctor_base_nothisret(%struct.A* %0)
-  %1 = getelementptr inbounds %struct.C* %this, i32 0, i32 0
+  %1 = getelementptr inbounds %struct.C, %struct.C* %this, i32 0, i32 0
   %call2 = tail call %struct.B* @B_ctor_base_nothisret(%struct.B* %1, i32 %x)
   ret %struct.C* %this
 }
@@ -85,7 +85,7 @@ entry:
 ; CHECKT2D: blx _B_ctor_complete
 ; CHECKT2D-NOT: mov r0, {{r[0-9]+}}
 ; CHECKT2D: b.w _B_ctor_complete
-  %b = getelementptr inbounds %struct.D* %this, i32 0, i32 0
+  %b = getelementptr inbounds %struct.D, %struct.D* %this, i32 0, i32 0
   %call = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x)
   %call2 = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x)
   ret %struct.D* %this
@@ -97,9 +97,9 @@ entry:
 ; CHECKELF-NOT: b B_ctor_complete
 ; CHECKT2D-LABEL: E_ctor_base:
 ; CHECKT2D-NOT: b.w _B_ctor_complete
-  %b = getelementptr inbounds %struct.E* %this, i32 0, i32 0
+  %b = getelementptr inbounds %struct.E, %struct.E* %this, i32 0, i32 0
   %call = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x)
-  %b2 = getelementptr inbounds %struct.E* %this, i32 0, i32 1
+  %b2 = getelementptr inbounds %struct.E, %struct.E* %this, i32 0, i32 1
   %call2 = tail call %struct.B* @B_ctor_complete(%struct.B* %b2, i32 %x)
   ret %struct.E* %this
 }
diff --git a/test/CodeGen/ARM/thumb-alignment.ll b/test/CodeGen/ARM/thumb-alignment.ll
new file mode 100644
index 000000000000..c11d4b6da3c9
--- /dev/null
+++ b/test/CodeGen/ARM/thumb-alignment.ll
@@ -0,0 +1,54 @@
+; RUN: llc -relocation-model=pic -mtriple=thumbv7-unknown-linux -o - %s | FileCheck %s
+
+@x = external global i32
+
+; CHECK: .globl	foo
+; CHECK-NEXT: .align	2
+define i32* @foo() {
+  ret i32* @x
+}
+
+; CHECK: .globl	bar
+; CHECK-NEXT: .align	1
+define i32* @bar() {
+  ret i32* zeroinitializer
+}
+
+@a = external global i32
+@b = external global i32
+@c = external global i32
+@d = external global i32
+
+; Create a Thumb-2 jump table, which should force alignment to 4 bytes.
+
+; CHECK: .globl	baz
+; CHECK-NEXT: .align	2
+; CHECK: adr.w
+define i32 @baz() {
+  %1 = load i32, i32* @c, align 4
+  switch i32 %1, label %7 [
+    i32 1, label %2
+    i32 4, label %5
+    i32 9, label %5
+    i32 3, label %8
+  ]
+
+; <label>:2
+  %3 = load i32, i32* @a, align 4
+  %4 = tail call i32 bitcast (i32 (...)* @fn2 to i32 (i32 (...)*, i32, i32)*)(i32 (...)* bitcast (i32 ()* @baz to i32 (...)*), i32 0, i32 %3) #2
+  br label %8
+
+; <label>:5
+  %6 = load i32, i32* @d, align 4
+  store i32 %6, i32* @b, align 4
+  br label %8
+
+; <label>:7
+  br label %8
+
+; <label>:8
+  %e.0 = phi i32 [ 1, %7 ], [ 1, %2 ], [ 0, %0 ], [ 0, %5 ]
+  ret i32 %e.0
+}
+
+declare i32 @fn2(...)
diff --git a/test/CodeGen/ARM/thumb-big-stack.ll b/test/CodeGen/ARM/thumb-big-stack.ll
new file mode 100644
index 000000000000..e5cbb9747a7e
--- /dev/null
+++ b/test/CodeGen/ARM/thumb-big-stack.ll
@@ -0,0 +1,6844 @@
+; RUN: llc %s -O0 -verify-machineinstrs -o - | FileCheck %s
+; This file uses to trigger a machine verifier error because we
+; were generating a stack adjustement with SP as second argument,
+; which is unpredictable behavior for t2ADDrr.
+; This file has been generated from the constpool test of the test-suite.
+target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7s-apple-ios"
+
+@.str = external unnamed_addr constant [21 x i8], align 1
+
+; CHECK-LABEL: f:
+; CHECK: movw [[ADDR:(r[0-9]+|lr)]], #
+; CHECK-NEXT: add [[ADDR]], sp
+; CHECK-NEXT: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, {{\[}}[[ADDR]]:128]
+define <4 x float> @f(<4 x float> %x) {
+entry:
+  %.compoundliteral7837 = alloca <4 x float>, align 16
+  %.compoundliteral7865 = alloca <4 x float>, align 16
+  %.compoundliteral7991 = alloca <4 x float>, align 16
+  %.compoundliteral8019 = alloca <4 x float>, align 16
+  %.compoundliteral8061 = alloca <4 x float>, align 16
+  %.compoundliteral8075 = alloca <4 x float>, align 16
+  %.compoundliteral8089 = alloca <4 x float>, align 16
+  %.compoundliteral8103 = alloca <4 x float>, align 16
+  %.compoundliteral8117 = alloca <4 x float>, align 16
+  %.compoundliteral8145 = alloca <4 x float>, align 16
+  %.compoundliteral8243 = alloca <4 x float>, align 16
+  %.compoundliteral8285 = alloca <4 x float>, align 16
+  %.compoundliteral8299 = alloca <4 x float>, align 16
+  %.compoundliteral8313 = alloca <4 x float>, align 16
+  %.compoundliteral8327 = alloca <4 x float>, align 16
+  %.compoundliteral9601 = alloca <4 x float>, align 16
+  %.compoundliteral9615 = alloca <4 x float>, align 16
+  %.compoundliteral9629 = alloca <4 x float>, align 16
+  %.compoundliteral9657 = alloca <4 x float>, align 16
+  %.compoundliteral9755 = alloca <4 x float>, align 16
+  %.compoundliteral9769 = alloca <4 x float>, align 16
+  %.compoundliteral9853 = alloca <4 x float>, align 16
+  %.compoundliteral9867 = alloca <4 x float>, align 16
+  %.compoundliteral9895 = alloca <4 x float>, align 16
+  %.compoundliteral9909 = alloca <4 x float>, align 16
+  %.compoundliteral9923 = alloca <4 x float>, align 16
+  %.compoundliteral9937 = alloca <4 x float>, align 16
+  %.compoundliteral9951 = alloca <4 x float>, align 16
+  %.compoundliteral9979 = alloca <4 x float>, align 16
+  %.compoundliteral10021 = alloca <4 x float>, align 16
+  %.compoundliteral10049 = alloca <4 x float>, align 16
+  %.compoundliteral10063 = alloca <4 x float>, align 16
+  %.compoundliteral10077 = alloca <4 x float>, align 16
+  %.compoundliteral10091 = alloca <4 x float>, align 16
+  %.compoundliteral10119 = alloca <4 x float>, align 16
+  %.compoundliteral10133 = alloca <4 x float>, align 16
+  %.compoundliteral10147 = alloca <4 x float>, align 16
+  %.compoundliteral10161 = alloca <4 x float>, align 16
+  %.compoundliteral10203 = alloca <4 x float>, align 16
+  %.compoundliteral10231 = alloca <4 x float>, align 16
+  %.compoundliteral10385 = alloca <4 x float>, align 16
+  %.compoundliteral10399 = alloca <4 x float>, align 16
+  %.compoundliteral10413 = alloca <4 x float>, align 16
+  %.compoundliteral10539 = alloca <4 x float>, align 16
+  %.compoundliteral10553 = alloca <4 x float>, align 16
+  %.compoundliteral10567 = alloca <4 x float>, align 16
+  %.compoundliteral10581 = alloca <4 x float>, align 16
+  %.compoundliteral10595 = alloca <4 x float>, align 16
+  %.compoundliteral10609 = alloca <4 x float>, align 16
+  %.compoundliteral10623 = alloca <4 x float>, align 16
+  %.compoundliteral10637 = alloca <4 x float>, align 16
+  %.compoundliteral10665 = alloca <4 x float>, align 16
+  %.compoundliteral10693 = alloca <4 x float>, align 16
+  %.compoundliteral10707 = alloca <4 x float>, align 16
+  %.compoundliteral10721 = alloca <4 x float>, align 16
+  %.compoundliteral10735 = alloca <4 x float>, align 16
+  %.compoundliteral10749 = alloca <4 x float>, align 16
+  %.compoundliteral10763 = alloca <4 x float>, align 16
+  %.compoundliteral10945 = alloca <4 x float>, align 16
+  %.compoundliteral10959 = alloca <4 x float>, align 16
+  %.compoundliteral10987 = alloca <4 x float>, align 16
+  %.compoundliteral11001 = alloca <4 x float>, align 16
+  %.compoundliteral11015 = alloca <4 x float>, align 16
+  %.compoundliteral11197 = alloca <4 x float>, align 16
+  %.compoundliteral11421 = alloca <4 x float>, align 16
+  %.compoundliteral11435 = alloca <4 x float>, align 16
+  %.compoundliteral11463 = alloca <4 x float>, align 16
+  %.compoundliteral11477 = alloca <4 x float>, align 16
+  %.compoundliteral11491 = alloca <4 x float>, align 16
+  %.compoundliteral11519 = alloca <4 x float>, align 16
+  %.compoundliteral11533 = alloca <4 x float>, align 16
+  %.compoundliteral11547 = alloca <4 x float>, align 16
+  %.compoundliteral11631 = alloca <4 x float>, align 16
+  %.compoundliteral11645 = alloca <4 x float>, align 16
+  %.compoundliteral11659 = alloca <4 x float>, align 16
+  %.compoundliteral11701 = alloca <4 x float>, align 16
+  %.compoundliteral11743 = alloca <4 x float>, align 16
+  %.compoundliteral11757 = alloca <4 x float>, align 16
+  %.compoundliteral11771 = alloca <4 x float>, align 16
+  %.compoundliteral11785 = alloca <4 x float>, align 16
+  %.compoundliteral11799 = alloca <4 x float>, align 16
+  %.compoundliteral11827 = alloca <4 x float>, align 16
+  %.compoundliteral11841 = alloca <4 x float>, align 16
+  %.compoundliteral11855 = alloca <4 x float>, align 16
+  %.compoundliteral11869 = alloca <4 x float>, align 16
+  %.compoundliteral11939 = alloca <4 x float>, align 16
+  %.compoundliteral11953 = alloca <4 x float>, align 16
+  %.compoundliteral11967 = alloca <4 x float>, align 16
+  %.compoundliteral11981 = alloca <4 x float>, align 16
+  %.compoundliteral11995 = alloca <4 x float>, align 16
+  %.compoundliteral12023 = alloca <4 x float>, align 16
+  %.compoundliteral12051 = alloca <4 x float>, align 16
+  %.compoundliteral12065 = alloca <4 x float>, align 16
+  %.compoundliteral12247 = alloca <4 x float>, align 16
+  %.compoundliteral12261 = alloca <4 x float>, align 16
+  %.compoundliteral12275 = alloca <4 x float>, align 16
+  %.compoundliteral12499 = alloca <4 x float>, align 16
+  %.compoundliteral12541 = alloca <4 x float>, align 16
+  %.compoundliteral12555 = alloca <4 x float>, align 16
+  %.compoundliteral12751 = alloca <4 x float>, align 16
+  %.compoundliteral12891 = alloca <4 x float>, align 16
+  %.compoundliteral12905 = alloca <4 x float>, align 16
+  %.compoundliteral12919 = alloca <4 x float>, align 16
+  %.compoundliteral12933 = alloca <4 x float>, align 16
+  %.compoundliteral12947 = alloca <4 x float>, align 16
+  %.compoundliteral12961 = alloca <4 x float>, align 16
+  %.compoundliteral12975 = alloca <4 x float>, align 16
+  %.compoundliteral12989 = alloca <4 x float>, align 16
+  %.compoundliteral13003 = alloca <4 x float>, align 16
+  %.compoundliteral13017 = alloca <4 x float>, align 16
+  %.compoundliteral13031 = alloca <4 x float>, align 16
+  %.compoundliteral13423 = alloca <4 x float>, align 16
+  %.compoundliteral13437 = alloca <4 x float>, align 16
+  %.compoundliteral13493 = alloca <4 x float>, align 16
+  %.compoundliteral13535 = alloca <4 x float>, align 16
+  %.compoundliteral13549 = alloca <4 x float>, align 16
+  %.compoundliteral13647 = alloca <4 x float>, align 16
+  %.compoundliteral13675 = alloca <4 x float>, align 16
+  %.compoundliteral13689 = alloca <4 x float>, align 16
+  %.compoundliteral13703 = alloca <4 x float>, align 16
+  %.compoundliteral13717 = alloca <4 x float>, align 16
+  %.compoundliteral13745 = alloca <4 x float>, align 16
+  %.compoundliteral13759 = alloca <4 x float>, align 16
+  %.compoundliteral13773 = alloca <4 x float>, align 16
+  %.compoundliteral13787 = alloca <4 x float>, align 16
+  %.compoundliteral13941 = alloca <4 x float>, align 16
+  %.compoundliteral13969 = alloca <4 x float>, align 16
+  %.compoundliteral13983 = alloca <4 x float>, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40746999A0000000, float 0xC0719B3340000000, float 0xC070B66660000000, float 0xC07404CCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40701B3340000000, float 0x405B866660000000, float 0xC0763999A0000000, float 4.895000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp1 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add68 = fadd <4 x float> %tmp1, %tmp
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add68, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp2 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add76 = fadd float undef, 0x4074C999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp3 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins77 = insertelement <4 x float> %tmp3, float %add76, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins77, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp4 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext78 = extractelement <4 x float> %tmp4, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add79 = fadd float %vecext78, 0x40776E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp5 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins80 = insertelement <4 x float> %tmp5, float %add79, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins80, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40678CCCC0000000, float 0xC03E4CCCC0000000, float -4.170000e+02, float -1.220000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp6 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add82 = fadd <4 x float> undef, %tmp6
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add82, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp7 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext83 = extractelement <4 x float> %tmp7, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add84 = fadd float %vecext83, 1.300000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp8 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins85 = insertelement <4 x float> %tmp8, float %add84, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins85, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp9 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext86 = extractelement <4 x float> %tmp9, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add93 = fadd float undef, 0xC076C66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp10 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins94 = insertelement <4 x float> %tmp10, float %add93, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x406C2999A0000000, float 8.050000e+01, float 0xC0794999A0000000, float 0xC073E4CCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp11 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp12 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add96 = fadd <4 x float> %tmp12, %tmp11
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp13 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext97 = extractelement <4 x float> %tmp13, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add98 = fadd float %vecext97, 0x4079E66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp14 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins102 = insertelement <4 x float> undef, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins102, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp15 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add104 = fadd float undef, 0x406AB999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp16 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC0531999A0000000, float 0xC0737999A0000000, float 0x407CB33340000000, float 0xC06DCCCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext579 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add580 = fadd float %vecext579, 0xC07424CCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp17 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins581 = insertelement <4 x float> %tmp17, float %add580, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins581, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp18 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext582 = extractelement <4 x float> %tmp18, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add583 = fadd float %vecext582, 0x40444CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp19 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext590 = extractelement <4 x float> %tmp19, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add591 = fadd float %vecext590, 1.725000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins592 = insertelement <4 x float> undef, float %add591, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins592, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp20 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add594 = fadd float undef, 0xC05B466660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add605 = fadd float undef, 0x407164CCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp21 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add616 = fadd float undef, 1.885000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp22 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp23 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins620 = insertelement <4 x float> undef, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins620, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext621 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add622 = fadd float %vecext621, 0x40709B3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins623 = insertelement <4 x float> undef, float %add622, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins623, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp24 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext624 = extractelement <4 x float> %tmp24, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add625 = fadd float %vecext624, 0xC064033340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp25 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins626 = insertelement <4 x float> %tmp25, float %add625, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins626, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x404D0CCCC0000000, float 3.955000e+02, float 0xC0334CCCC0000000, float 0x40754E6660000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp26 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp27 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add628 = fadd <4 x float> %tmp27, %tmp26
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add628, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp28 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext629 = extractelement <4 x float> %tmp28, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add630 = fadd float %vecext629, 0x40730CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp29 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins631 = insertelement <4 x float> %tmp29, float %add630, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins631, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp30 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext632 = extractelement <4 x float> %tmp30, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add633 = fadd float %vecext632, 0xC0630999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp31 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins634 = insertelement <4 x float> %tmp31, float %add633, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins634, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp32 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext635 = extractelement <4 x float> %tmp32, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add636 = fadd float %vecext635, 0xC078833340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp33 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp34 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp35 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add658 = fadd float undef, 0xC04A4CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext663 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp36 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins665 = insertelement <4 x float> %tmp36, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext694 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add695 = fadd float %vecext694, 0xC03CCCCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp37 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins696 = insertelement <4 x float> %tmp37, float %add695, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins696, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC069FCCCC0000000, float 0xC07C6E6660000000, float 0x4067E33340000000, float 0x4078DB3340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp38 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext699 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add703 = fadd float undef, 0x4068F33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins704 = insertelement <4 x float> undef, float %add703, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins704, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp39 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp40 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins710 = insertelement <4 x float> %tmp40, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins710, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC05D9999A0000000, float 0x405D6CCCC0000000, float 0x40765CCCC0000000, float 0xC07C64CCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp41 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp42 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add712 = fadd <4 x float> %tmp42, %tmp41
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add712, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp43 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext713 = extractelement <4 x float> %tmp43, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp44 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins715 = insertelement <4 x float> %tmp44, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp45 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext716 = extractelement <4 x float> %tmp45, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add717 = fadd float %vecext716, -4.315000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp46 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins718 = insertelement <4 x float> %tmp46, float %add717, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins718, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp47 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext719 = extractelement <4 x float> %tmp47, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add723 = fadd float undef, 0xC06A6CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins724 = insertelement <4 x float> undef, float %add723, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add726 = fadd <4 x float> undef, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext730 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add731 = fadd float %vecext730, 0xC0759CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp48 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins732 = insertelement <4 x float> %tmp48, float %add731, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins732, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp49 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext733 = extractelement <4 x float> %tmp49, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp50 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins738 = insertelement <4 x float> %tmp50, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x406E6CCCC0000000, float 0xC07A766660000000, float 0xC0608CCCC0000000, float 0xC063333340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp51 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add740 = fadd <4 x float> undef, %tmp51
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp52 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext741 = extractelement <4 x float> %tmp52, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add742 = fadd float %vecext741, 0xC07984CCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp53 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins743 = insertelement <4 x float> %tmp53, float %add742, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins743, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp54 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp55 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add754 = fadd <4 x float> %tmp55, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add754, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp56 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext755 = extractelement <4 x float> %tmp56, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add756 = fadd float %vecext755, 0xC070ACCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp57 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins757 = insertelement <4 x float> %tmp57, float %add756, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add765 = fadd float undef, 0x405BA66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp58 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins766 = insertelement <4 x float> %tmp58, float %add765, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp59 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext769 = extractelement <4 x float> %tmp59, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add770 = fadd float %vecext769, 0x40797199A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp60 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins771 = insertelement <4 x float> %tmp60, float %add770, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins771, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp61 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add776 = fadd float undef, 0xC055F33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins777 = insertelement <4 x float> undef, float %add776, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp62 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp63 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add782 = fadd <4 x float> %tmp63, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add782, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp64 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext783 = extractelement <4 x float> %tmp64, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add784 = fadd float %vecext783, -3.455000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC07A866660000000, float 0xC05CF999A0000000, float 0xC0757199A0000000, float -3.845000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add796 = fadd <4 x float> undef, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add796, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp65 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add801 = fadd float undef, 3.045000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp66 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins802 = insertelement <4 x float> %tmp66, float %add801, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins802, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext803 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp67 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp68 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add810 = fadd <4 x float> undef, %tmp68
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add810, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp69 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext811 = extractelement <4 x float> %tmp69, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp70 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins813 = insertelement <4 x float> %tmp70, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext817 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add818 = fadd float %vecext817, -4.830000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins822 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins822, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 2.700000e+01, float 0xC05F666660000000, float 0xC07D0199A0000000, float 0x407A6CCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp71 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp72 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add824 = fadd <4 x float> %tmp72, %tmp71
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add838 = fadd <4 x float> undef, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add838, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp73 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext839 = extractelement <4 x float> %tmp73, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add849 = fadd float undef, 0xC07C266660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC07D566660000000, float 0xC06D233340000000, float 0x4068B33340000000, float 0xC07ADCCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp74 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add852 = fadd <4 x float> %tmp74, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext856 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add857 = fadd float %vecext856, 0xC070666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp75 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp76 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext859 = extractelement <4 x float> %tmp76, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add860 = fadd float %vecext859, 4.705000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp77 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins861 = insertelement <4 x float> %tmp77, float %add860, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins889 = insertelement <4 x float> undef, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins889, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp78 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext890 = extractelement <4 x float> %tmp78, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add891 = fadd float %vecext890, 0xC070633340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp79 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins892 = insertelement <4 x float> %tmp79, float %add891, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins892, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x4063D33340000000, float 0xC076433340000000, float 0x407C966660000000, float 0xC07B5199A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp80 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp81 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add894 = fadd <4 x float> %tmp81, %tmp80
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add894, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext895 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add896 = fadd float %vecext895, 0xC070F33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins897 = insertelement <4 x float> undef, float %add896, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp82 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext898 = extractelement <4 x float> %tmp82, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add899 = fadd float %vecext898, 0xC076F33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins900 = insertelement <4 x float> undef, float %add899, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp83 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext901 = extractelement <4 x float> %tmp83, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add902 = fadd float %vecext901, 0xC054ECCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp84 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins903 = insertelement <4 x float> %tmp84, float %add902, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins903, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext904 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add905 = fadd float %vecext904, 0x4056A66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp85 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins906 = insertelement <4 x float> %tmp85, float %add905, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC07EFCCCC0000000, float 1.795000e+02, float 0x407E3E6660000000, float 0x4070633340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp86 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp87 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add908 = fadd <4 x float> %tmp87, %tmp86
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add908, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp88 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp89 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp90 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext912 = extractelement <4 x float> %tmp90, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add913 = fadd float %vecext912, 2.575000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins914 = insertelement <4 x float> undef, float %add913, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp91 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext915 = extractelement <4 x float> %tmp91, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add916 = fadd float %vecext915, -3.115000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp92 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins917 = insertelement <4 x float> %tmp92, float %add916, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins917, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp93 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext918 = extractelement <4 x float> %tmp93, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add919 = fadd float %vecext918, 2.950000e+01
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp94 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins920 = insertelement <4 x float> %tmp94, float %add919, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins920, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp95 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins925 = insertelement <4 x float> %tmp95, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins925, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp96 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add927 = fadd float undef, 0xC0501999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp97 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins928 = insertelement <4 x float> %tmp97, float %add927, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext929 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add930 = fadd float %vecext929, 0xC07C8B3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp98 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins931 = insertelement <4 x float> %tmp98, float %add930, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC047B33340000000, float 0x404ACCCCC0000000, float 0x40708E6660000000, float 0x4060F999A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp99 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp100 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext937 = extractelement <4 x float> %tmp100, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add941 = fadd float undef, -4.665000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins942 = insertelement <4 x float> undef, float %add941, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins942, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp101 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext943 = extractelement <4 x float> %tmp101, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add944 = fadd float %vecext943, 4.580000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp102 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins945 = insertelement <4 x float> %tmp102, float %add944, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins945, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp103 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add947 = fadd float undef, 0xC051933340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp104 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins948 = insertelement <4 x float> %tmp104, float %add947, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins948, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x4060CCCCC0000000, float 0xC07BAB3340000000, float 0xC061233340000000, float 0xC076C199A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp105 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add955 = fadd float undef, 0x4077F4CCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp106 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins956 = insertelement <4 x float> %tmp106, float %add955, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins956, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext971 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add972 = fadd float %vecext971, 0x4024333340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp107 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins973 = insertelement <4 x float> %tmp107, float %add972, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins973, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp108 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext974 = extractelement <4 x float> %tmp108, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins976 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins976, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x407E266660000000, float -1.225000e+02, float 0x407EB199A0000000, float 0x407BA199A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp109 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp110 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add978 = fadd <4 x float> %tmp110, %tmp109
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp111 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp112 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext982 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add983 = fadd float %vecext982, 0x407E1B3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins984 = insertelement <4 x float> undef, float %add983, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins984, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp113 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext985 = extractelement <4 x float> %tmp113, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add986 = fadd float %vecext985, 0x406C8CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp114 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins987 = insertelement <4 x float> %tmp114, float %add986, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins987, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp115 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp116 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins995 = insertelement <4 x float> %tmp116, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins995, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp117 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add997 = fadd float undef, 0xC0798999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp118 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins998 = insertelement <4 x float> %tmp118, float %add997, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins998, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp119 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1013 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1014 = fadd float %vecext1013, 3.105000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp120 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp121 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1016 = extractelement <4 x float> %tmp121, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1017 = fadd float %vecext1016, 0x406A1999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp122 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1030 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1031 = fadd float %vecext1030, 2.010000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp123 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp124 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1085 = insertelement <4 x float> %tmp124, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp125 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1086 = extractelement <4 x float> %tmp125, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1087 = fadd float %vecext1086, -1.575000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp126 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1088 = insertelement <4 x float> %tmp126, float %add1087, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1088, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp127 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1090 = fadd <4 x float> undef, %tmp127
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp128 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1094 = extractelement <4 x float> %tmp128, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1095 = fadd float %vecext1094, 0x4072C999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp129 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1096 = insertelement <4 x float> %tmp129, float %add1095, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1096, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp130 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1097 = extractelement <4 x float> %tmp130, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1098 = fadd float %vecext1097, 0xC073E999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp131 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1099 = insertelement <4 x float> %tmp131, float %add1098, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1099, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp132 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1100 = extractelement <4 x float> %tmp132, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1101 = fadd float %vecext1100, 2.885000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp133 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1102 = insertelement <4 x float> %tmp133, float %add1101, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1102, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x4059866660000000, float 0x4072466660000000, float 0xC078FE6660000000, float 0xC058ACCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp134 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1104 = fadd <4 x float> undef, %tmp134
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp135 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1105 = extractelement <4 x float> %tmp135, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1106 = fadd float %vecext1105, 0xC078A999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp136 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1107 = insertelement <4 x float> %tmp136, float %add1106, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1108 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp137 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1110 = insertelement <4 x float> %tmp137, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1110, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp138 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1111 = extractelement <4 x float> %tmp138, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1112 = fadd float %vecext1111, 0x407D566660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp139 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1113 = insertelement <4 x float> %tmp139, float %add1112, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1113, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1115 = fadd float undef, 0x4072B33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1116 = insertelement <4 x float> undef, float %add1115, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1116, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC0721999A0000000, float 0x4075633340000000, float 0x40794199A0000000, float 0x4061066660000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp140 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1118 = fadd <4 x float> %tmp140, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add1118, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp141 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1119 = extractelement <4 x float> %tmp141, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1120 = fadd float %vecext1119, 0xC065A66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1121 = insertelement <4 x float> undef, float %add1120, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1121, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp142 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1122 = extractelement <4 x float> %tmp142, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1123 = fadd float %vecext1122, 0x4072533340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp143 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1124 = insertelement <4 x float> %tmp143, float %add1123, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1125 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1127 = insertelement <4 x float> undef, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1127, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp144 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1128 = extractelement <4 x float> %tmp144, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1129 = fadd float %vecext1128, 0x405C866660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp145 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1130 = insertelement <4 x float> %tmp145, float %add1129, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC06D6CCCC0000000, float 0xC032E66660000000, float -1.005000e+02, float 0x40765B3340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp146 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp147 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1132 = fadd <4 x float> %tmp147, %tmp146
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp148 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1133 = extractelement <4 x float> %tmp148, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1134 = fadd float %vecext1133, 0xC07EB999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp149 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1135 = insertelement <4 x float> %tmp149, float %add1134, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1135, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp150 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1136 = extractelement <4 x float> %tmp150, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp151 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1138 = insertelement <4 x float> %tmp151, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1138, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp152 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1140 = fadd float undef, 0x407AE999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp153 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1141 = insertelement <4 x float> %tmp153, float %add1140, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1142 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1143 = fadd float %vecext1142, 0x407A24CCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp154 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1144 = insertelement <4 x float> %tmp154, float %add1143, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1144, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp155 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp156 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1146 = fadd <4 x float> %tmp156, %tmp155
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add1146, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp157 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1148 = fadd float undef, 4.145000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp158 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1158 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1158, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40603999A0000000, float -9.150000e+01, float 0xC051E66660000000, float -4.825000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1218 = fadd float undef, 0xC078733340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1219 = insertelement <4 x float> undef, float %add1218, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC0655CCCC0000000, float -4.900000e+01, float -4.525000e+02, float 4.205000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp159 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1279 = extractelement <4 x float> %tmp159, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1280 = fadd float %vecext1279, 0xC062D999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp160 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1281 = insertelement <4 x float> %tmp160, float %add1280, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1281, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp161 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1282 = extractelement <4 x float> %tmp161, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1283 = fadd float %vecext1282, 4.365000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp162 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1284 = insertelement <4 x float> %tmp162, float %add1283, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1284, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp163 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp164 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1286 = fadd <4 x float> %tmp164, %tmp163
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add1286, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp165 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1288 = fadd float undef, 0xC0731199A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp166 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp167 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1444 = extractelement <4 x float> %tmp167, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1460 = insertelement <4 x float> undef, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1460, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp168 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1462 = fadd float undef, -1.670000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1463 = insertelement <4 x float> undef, float %add1462, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp169 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1464 = extractelement <4 x float> %tmp169, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1465 = fadd float %vecext1464, 0xC066333340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp170 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1466 = insertelement <4 x float> %tmp170, float %add1465, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1466, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 3.885000e+02, float 0x4054266660000000, float -9.500000e+01, float 8.500000e+01>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp171 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp172 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1468 = fadd <4 x float> %tmp172, %tmp171
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add1468, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp173 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1470 = fadd float undef, 0x4033B33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp174 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1471 = insertelement <4 x float> %tmp174, float %add1470, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1471, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp175 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1472 = extractelement <4 x float> %tmp175, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1473 = fadd float %vecext1472, 0xC05F666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp176 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1474 = insertelement <4 x float> %tmp176, float %add1473, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp177 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1475 = extractelement <4 x float> %tmp177, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp178 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1477 = insertelement <4 x float> %tmp178, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1477, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp179 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1478 = extractelement <4 x float> %tmp179, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1479 = fadd float %vecext1478, 0x407E2E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp180 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1480 = insertelement <4 x float> %tmp180, float %add1479, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1480, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC061B33340000000, float 3.290000e+02, float 0xC067766660000000, float 0x407DB33340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp181 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp182 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp183 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1483 = extractelement <4 x float> %tmp183, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1484 = fadd float %vecext1483, 0xC053D999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp184 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp185 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1486 = extractelement <4 x float> %tmp185, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1502 = insertelement <4 x float> undef, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1502, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1503 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1504 = fadd float %vecext1503, -2.475000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp186 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1505 = insertelement <4 x float> %tmp186, float %add1504, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1505, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp187 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1506 = extractelement <4 x float> %tmp187, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1507 = fadd float %vecext1506, 0x40715199A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp188 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1508 = insertelement <4 x float> %tmp188, float %add1507, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1508, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40762B3340000000, float 0xC074566660000000, float 0xC07C74CCC0000000, float 0xC053F999A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp189 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp190 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1510 = fadd <4 x float> %tmp190, %tmp189
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add1510, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp191 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp192 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1654 = extractelement <4 x float> %tmp192, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1655 = fadd float %vecext1654, 0xC07D8CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp193 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1656 = insertelement <4 x float> %tmp193, float %add1655, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1656, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1658 = fadd float undef, 0x40709999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp194 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1660 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1661 = fadd float %vecext1660, 0xC06F166660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp195 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1662 = insertelement <4 x float> %tmp195, float %add1661, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1662, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC075266660000000, float 0xC072C4CCC0000000, float 0x407C4E6660000000, float -4.485000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1676 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp196 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1692 = fadd <4 x float> %tmp196, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add1692, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp197 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1693 = extractelement <4 x float> %tmp197, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1694 = fadd float %vecext1693, 0x407A1999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp198 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1695 = insertelement <4 x float> %tmp198, float %add1694, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1695, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp199 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1696 = extractelement <4 x float> %tmp199, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1697 = fadd float %vecext1696, 2.850000e+01
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp200 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1698 = insertelement <4 x float> %tmp200, float %add1697, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1698, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp201 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1699 = extractelement <4 x float> %tmp201, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp202 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1701 = insertelement <4 x float> %tmp202, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1701, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp203 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1704 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC075933340000000, float 0xC0489999A0000000, float 0xC078AB3340000000, float 0x406DFCCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp204 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp205 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp206 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1709 = insertelement <4 x float> %tmp206, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1709, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp207 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1713 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1714 = fadd float %vecext1713, 0xC0703199A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1723 = insertelement <4 x float> undef, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp208 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1730 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1731 = fadd float %vecext1730, 4.130000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp209 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1732 = insertelement <4 x float> %tmp209, float %add1731, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1732, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40551999A0000000, float 0xC0708999A0000000, float 0xC054F33340000000, float 0xC07C5999A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp210 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1734 = fadd <4 x float> undef, %tmp210
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp211 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1736 = fadd float undef, 0x407C3999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp212 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1737 = insertelement <4 x float> %tmp212, float %add1736, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp213 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1738 = extractelement <4 x float> %tmp213, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1739 = fadd float %vecext1738, 0xC0711E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp214 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1740 = insertelement <4 x float> %tmp214, float %add1739, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1740, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp215 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1741 = extractelement <4 x float> %tmp215, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1742 = fadd float %vecext1741, -2.545000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp216 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1743 = insertelement <4 x float> %tmp216, float %add1742, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1743, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1744 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp217 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1746 = insertelement <4 x float> %tmp217, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC076466660000000, float 0x4060BCCCC0000000, float 0x405EF999A0000000, float 0x4074766660000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp218 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1748 = fadd <4 x float> undef, %tmp218
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add1748, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp219 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1750 = fadd float undef, 0x407C6B3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1751 = insertelement <4 x float> undef, float %add1750, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp220 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1752 = extractelement <4 x float> %tmp220, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1753 = fadd float %vecext1752, 0x40730CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp221 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1754 = insertelement <4 x float> %tmp221, float %add1753, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp222 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1755 = extractelement <4 x float> %tmp222, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1756 = fadd float %vecext1755, 0xC059F33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp223 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1759 = fadd float undef, 0x40678999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp224 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1760 = insertelement <4 x float> %tmp224, float %add1759, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1760, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x405E333340000000, float 0x40571999A0000000, float 0xC02E333340000000, float 0x4053A66660000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp225 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1762 = fadd <4 x float> undef, %tmp225
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add1762, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp226 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1763 = extractelement <4 x float> %tmp226, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1764 = fadd float %vecext1763, 0xC0299999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp227 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1765 = insertelement <4 x float> %tmp227, float %add1764, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1765, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp228 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1766 = extractelement <4 x float> %tmp228, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1767 = fadd float %vecext1766, 0x407DDE6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp229 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1768 = insertelement <4 x float> %tmp229, float %add1767, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1768, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1769 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1770 = fadd float %vecext1769, 0x407A1B3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp230 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1771 = insertelement <4 x float> %tmp230, float %add1770, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1771, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp231 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp232 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp233 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp234 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1779 = insertelement <4 x float> %tmp234, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1779, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp235 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp236 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1783 = extractelement <4 x float> %tmp236, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1784 = fadd float %vecext1783, 0x405E933340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1785 = insertelement <4 x float> undef, float %add1784, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1785, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC07074CCC0000000, float 0xC04D666660000000, float 3.235000e+02, float 0xC0724199A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp237 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1790 = fadd <4 x float> undef, %tmp237
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp238 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1791 = extractelement <4 x float> %tmp238, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1792 = fadd float %vecext1791, 0x4077DE6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp239 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1793 = insertelement <4 x float> %tmp239, float %add1792, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1793, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp240 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1795 = fadd float undef, 0x4055266660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp241 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1796 = insertelement <4 x float> %tmp241, float %add1795, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1799 = insertelement <4 x float> undef, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1800 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp242 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float -6.600000e+01, float 0xC07B2199A0000000, float 0x4011333340000000, float 0xC0635CCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp243 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp244 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp245 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp246 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1865 = fadd float undef, -2.235000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp247 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1866 = insertelement <4 x float> %tmp247, float %add1865, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp248 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp249 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1872 = insertelement <4 x float> %tmp249, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x406B8999A0000000, float 0xC0696CCCC0000000, float 0xC07A34CCC0000000, float 0x407654CCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp250 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1874 = fadd <4 x float> %tmp250, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add1874, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1875 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp251 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1894 = insertelement <4 x float> %tmp251, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp252 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1895 = extractelement <4 x float> %tmp252, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1900 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1900, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1905 = insertelement <4 x float> undef, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1905, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp253 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1906 = extractelement <4 x float> %tmp253, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1907 = fadd float %vecext1906, 0xC07E5E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1908 = insertelement <4 x float> undef, float %add1907, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1908, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1909 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp254 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1912 = extractelement <4 x float> %tmp254, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1913 = fadd float %vecext1912, 0xC063ECCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp255 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp256 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1916 = fadd <4 x float> %tmp256, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add1916, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1923 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp257 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1927 = fadd float undef, 0x40761999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp258 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1928 = insertelement <4 x float> %tmp258, float %add1927, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1928, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 7.100000e+01, float 0xC0634999A0000000, float 0x407B0B3340000000, float 0xC07DE999A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp259 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp260 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1930 = fadd <4 x float> %tmp260, %tmp259
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp261 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp262 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1933 = insertelement <4 x float> %tmp262, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1933, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp263 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1934 = extractelement <4 x float> %tmp263, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1935 = fadd float %vecext1934, 0xC07D3199A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp264 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1936 = insertelement <4 x float> %tmp264, float %add1935, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1940 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1942 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float -8.200000e+01, float 0xC04C733340000000, float 0xC077ACCCC0000000, float 0x4074566660000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp265 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp266 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp267 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1945 = extractelement <4 x float> %tmp267, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1946 = fadd float %vecext1945, 0xC074866660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1953 = insertelement <4 x float> undef, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1953, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp268 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp269 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp270 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1958 = fadd <4 x float> %tmp270, %tmp269
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp271 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1959 = extractelement <4 x float> %tmp271, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1960 = fadd float %vecext1959, 0x4065ACCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1962 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1963 = fadd float %vecext1962, 0xC07134CCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp272 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1964 = insertelement <4 x float> %tmp272, float %add1963, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1964, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1965 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp273 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1967 = insertelement <4 x float> %tmp273, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1967, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp274 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1968 = extractelement <4 x float> %tmp274, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1969 = fadd float %vecext1968, 7.100000e+01
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp275 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1970 = insertelement <4 x float> %tmp275, float %add1969, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1970, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x402E9999A0000000, float 0x407344CCC0000000, float -4.165000e+02, float 0x4078FCCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp276 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp277 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp278 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1975 = insertelement <4 x float> %tmp278, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1975, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp279 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1976 = extractelement <4 x float> %tmp279, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1978 = insertelement <4 x float> undef, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1978, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1979 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1981 = insertelement <4 x float> undef, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1981, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1984 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1984, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC06A766660000000, float 0xC07CE4CCC0000000, float -1.055000e+02, float 0x40786E6660000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1990 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext1996 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add1997 = fadd float %vecext1996, -1.400000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp280 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins1998 = insertelement <4 x float> %tmp280, float %add1997, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins1998, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC0794E6660000000, float 0xC073CCCCC0000000, float 0x407994CCC0000000, float 6.500000e+01>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2004 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2005 = fadd float %vecext2004, -1.970000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp281 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2006 = insertelement <4 x float> %tmp281, float %add2005, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2006, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp282 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2007 = extractelement <4 x float> %tmp282, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp283 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2009 = insertelement <4 x float> %tmp283, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp284 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2010 = extractelement <4 x float> %tmp284, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2011 = fadd float %vecext2010, 0xC074533340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp285 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2012 = insertelement <4 x float> %tmp285, float %add2011, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2012, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC04E733340000000, float 0xC074566660000000, float 0x4079F66660000000, float 0xC0705B3340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp286 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp287 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp288 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2015 = extractelement <4 x float> %tmp288, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2016 = fadd float %vecext2015, 0xC060633340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp289 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2017 = insertelement <4 x float> %tmp289, float %add2016, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2022 = fadd float undef, 8.350000e+01
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp290 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2023 = insertelement <4 x float> %tmp290, float %add2022, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp291 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2024 = extractelement <4 x float> %tmp291, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp292 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2028 = fadd <4 x float> %tmp292, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add2028, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2029 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2030 = fadd float %vecext2029, -9.450000e+01
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp293 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp294 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2036 = fadd float undef, 0x407DE66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp295 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp296 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp297 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp298 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp299 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2045 = insertelement <4 x float> %tmp299, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2045, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp300 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2046 = extractelement <4 x float> %tmp300, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2047 = fadd float %vecext2046, 0xC065433340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2052 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp301 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2054 = insertelement <4 x float> %tmp301, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2054, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x4024666660000000, float 0x4079366660000000, float 0x40721B3340000000, float 0x406E533340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp302 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2056 = fadd <4 x float> undef, %tmp302
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add2056, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp303 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp304 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2062 = insertelement <4 x float> %tmp304, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2062, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp305 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp306 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2066 = extractelement <4 x float> %tmp306, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2067 = fadd float %vecext2066, 0x40690999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2068 = insertelement <4 x float> undef, float %add2067, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2068, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC07EFCCCC0000000, float -3.420000e+02, float 0xC07BC999A0000000, float 0x40751999A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp307 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp308 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2070 = fadd <4 x float> %tmp308, %tmp307
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add2070, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp309 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2071 = extractelement <4 x float> %tmp309, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2072 = fadd float %vecext2071, 0x4057733340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp310 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2073 = insertelement <4 x float> %tmp310, float %add2072, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2073, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp311 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2074 = extractelement <4 x float> %tmp311, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp312 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2076 = insertelement <4 x float> %tmp312, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp313 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2077 = extractelement <4 x float> %tmp313, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2078 = fadd float %vecext2077, 0x4061F999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp314 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2079 = insertelement <4 x float> %tmp314, float %add2078, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2079, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp315 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2080 = extractelement <4 x float> %tmp315, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2081 = fadd float %vecext2080, 0x407A1B3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp316 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2082 = insertelement <4 x float> %tmp316, float %add2081, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2082, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40764E6660000000, float 0x40501999A0000000, float 0xC079A4CCC0000000, float 0x4050533340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp317 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp318 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp319 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2085 = extractelement <4 x float> %tmp319, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2086 = fadd float %vecext2085, 0x406E666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2087 = insertelement <4 x float> undef, float %add2086, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2087, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2480 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2481 = fadd float %vecext2480, 0x4039666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2483 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2484 = fadd float %vecext2483, 0xC06A3999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp320 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2485 = insertelement <4 x float> %tmp320, float %add2484, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2485, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp321 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2487 = fadd float undef, 2.030000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp322 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x4073DE6660000000, float 0x4067CCCCC0000000, float 0xC03F1999A0000000, float 4.350000e+01>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2491 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp323 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp324 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2494 = extractelement <4 x float> %tmp324, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2495 = fadd float %vecext2494, 0xC0743CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp325 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2499 = insertelement <4 x float> undef, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2499, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2500 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2501 = fadd float %vecext2500, 0x40796E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp326 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp327 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2508 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2518 = fadd <4 x float> undef, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp328 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2519 = extractelement <4 x float> %tmp328, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2520 = fadd float %vecext2519, 0xC0399999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp329 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2534 = fadd float undef, 0x4072C66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2536 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2537 = fadd float %vecext2536, 0x407D066660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp330 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2538 = insertelement <4 x float> %tmp330, float %add2537, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2538, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2539 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2540 = fadd float %vecext2539, 0x406F9999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2580 = insertelement <4 x float> undef, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2580, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp331 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2581 = extractelement <4 x float> %tmp331, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2582 = fadd float %vecext2581, 0x406BE66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2583 = insertelement <4 x float> undef, float %add2582, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2583, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2584 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2585 = fadd float %vecext2584, 3.585000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp332 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40773199A0000000, float 0x407D7999A0000000, float 0xC0717199A0000000, float 0xC07E9CCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2590 = fadd float undef, 0x407B1999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp333 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp334 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2672 = fadd <4 x float> undef, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add2672, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp335 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2676 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2677 = fadd float %vecext2676, 0x406D6999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp336 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2678 = insertelement <4 x float> %tmp336, float %add2677, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2678, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp337 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2679 = extractelement <4 x float> %tmp337, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2681 = insertelement <4 x float> undef, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2681, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp338 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2682 = extractelement <4 x float> %tmp338, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2684 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp339 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp340 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp341 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2688 = fadd float undef, 0x4063266660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2692 = insertelement <4 x float> undef, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2692, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp342 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2696 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2697 = fadd float %vecext2696, 4.140000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp343 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins2698 = insertelement <4 x float> %tmp343, float %add2697, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins2698, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40547999A0000000, float 0xC060633340000000, float 0x4075766660000000, float 0x4072D33340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp344 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp345 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2700 = fadd <4 x float> %tmp345, %tmp344
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add2700, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp346 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp347 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp348 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext2704 = extractelement <4 x float> %tmp348, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add2705 = fadd float %vecext2704, 4.700000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp349 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3121 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3125 = fadd float undef, 0xC06F266660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3126 = insertelement <4 x float> undef, float %add3125, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3126, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp350 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3127 = extractelement <4 x float> %tmp350, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3128 = fadd float %vecext3127, 0x40638999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp351 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3129 = insertelement <4 x float> %tmp351, float %add3128, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3129, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp352 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3131 = fadd float undef, 3.215000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp353 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp354 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3134 = fadd <4 x float> %tmp354, %tmp353
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add3134, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp355 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3136 = fadd float undef, 0x4074333340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3140 = insertelement <4 x float> undef, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3140, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp356 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3141 = extractelement <4 x float> %tmp356, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3142 = fadd float %vecext3141, 2.425000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp357 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3143 = insertelement <4 x float> %tmp357, float %add3142, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3143, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp358 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3144 = extractelement <4 x float> %tmp358, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3145 = fadd float %vecext3144, -3.760000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp359 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3146 = insertelement <4 x float> %tmp359, float %add3145, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3146, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp360 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3272 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3272, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x407B4999A0000000, float 0x40695CCCC0000000, float 0xC05C0CCCC0000000, float 0x407EB33340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp361 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp362 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3274 = fadd <4 x float> %tmp362, %tmp361
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add3274, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp363 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3275 = extractelement <4 x float> %tmp363, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3276 = fadd float %vecext3275, 0x4058066660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp364 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3277 = insertelement <4 x float> %tmp364, float %add3276, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3277, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp365 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3278 = extractelement <4 x float> %tmp365, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3279 = fadd float %vecext3278, 0xC053666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3280 = insertelement <4 x float> undef, float %add3279, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3280, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp366 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3281 = extractelement <4 x float> %tmp366, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3282 = fadd float %vecext3281, 0xC0650CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp367 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3283 = insertelement <4 x float> %tmp367, float %add3282, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3283, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp368 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3284 = extractelement <4 x float> %tmp368, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3285 = fadd float %vecext3284, 0x4062533340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3286 = insertelement <4 x float> undef, float %add3285, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp369 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp370 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3289 = extractelement <4 x float> %tmp370, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3290 = fadd float %vecext3289, 0xC07E133340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp371 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3291 = insertelement <4 x float> %tmp371, float %add3290, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3291, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3292 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp372 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp373 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3328 = insertelement <4 x float> %tmp373, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3330 = fadd <4 x float> undef, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add3330, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3331 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3332 = fadd float %vecext3331, 0x4061633340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp374 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3333 = insertelement <4 x float> %tmp374, float %add3332, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3333, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3334 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3335 = fadd float %vecext3334, 0x401B333340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3336 = insertelement <4 x float> undef, float %add3335, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp375 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3337 = extractelement <4 x float> %tmp375, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3338 = fadd float %vecext3337, 0x403C4CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp376 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3339 = insertelement <4 x float> %tmp376, float %add3338, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3339, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp377 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3340 = extractelement <4 x float> %tmp377, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp378 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3342 = insertelement <4 x float> %tmp378, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp379 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3344 = fadd <4 x float> %tmp379, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add3344, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp380 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3345 = extractelement <4 x float> %tmp380, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3346 = fadd float %vecext3345, 0x407E7E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp381 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3347 = insertelement <4 x float> %tmp381, float %add3346, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3348 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3349 = fadd float %vecext3348, 0xC05F666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp382 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3350 = insertelement <4 x float> %tmp382, float %add3349, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3350, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3352 = fadd float undef, 0xC06ACCCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp383 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3423 = insertelement <4 x float> undef, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3423, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3424 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3425 = fadd float %vecext3424, 0xC05DB33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp384 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3426 = insertelement <4 x float> %tmp384, float %add3425, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3426, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 2.795000e+02, float -4.065000e+02, float 0xC05CD999A0000000, float 1.825000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp385 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp386 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3428 = fadd <4 x float> %tmp386, %tmp385
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp387 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3429 = extractelement <4 x float> %tmp387, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3430 = fadd float %vecext3429, 0x40695CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp388 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3431 = insertelement <4 x float> %tmp388, float %add3430, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3431, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp389 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3432 = extractelement <4 x float> %tmp389, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3433 = fadd float %vecext3432, 0x4052A66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp390 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3434 = insertelement <4 x float> %tmp390, float %add3433, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3434, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3435 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp391 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3437 = insertelement <4 x float> %tmp391, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3437, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp392 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3438 = extractelement <4 x float> %tmp392, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3439 = fadd float %vecext3438, 0xC071D999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC0798199A0000000, float -3.385000e+02, float 0xC050066660000000, float 0xC075E999A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp393 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp394 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3442 = fadd <4 x float> %tmp394, %tmp393
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add3442, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3443 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3444 = fadd float %vecext3443, 0xC07CF999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp395 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3446 = extractelement <4 x float> %tmp395, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3447 = fadd float %vecext3446, 0xC06E4999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp396 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3448 = insertelement <4 x float> %tmp396, float %add3447, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3448, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp397 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3449 = extractelement <4 x float> %tmp397, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3450 = fadd float %vecext3449, 0x40779B3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp398 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3451 = insertelement <4 x float> %tmp398, float %add3450, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3451, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3453 = fadd float undef, 0xC07ADCCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp399 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3454 = insertelement <4 x float> %tmp399, float %add3453, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3454, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp400 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3457 = extractelement <4 x float> %tmp400, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3458 = fadd float %vecext3457, -4.440000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3459 = insertelement <4 x float> undef, float %add3458, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3459, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp401 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3460 = extractelement <4 x float> %tmp401, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp402 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3462 = insertelement <4 x float> %tmp402, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3462, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp403 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3464 = fadd float undef, 0xC057B999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp404 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3465 = insertelement <4 x float> %tmp404, float %add3464, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3465, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp405 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3466 = extractelement <4 x float> %tmp405, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3467 = fadd float %vecext3466, 0xC07A9CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp406 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x405C3999A0000000, float 0xC07C6B3340000000, float 0x407ACB3340000000, float 0xC06E0999A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp407 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp408 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3477 = extractelement <4 x float> %tmp408, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3479 = insertelement <4 x float> undef, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3479, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3480 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3481 = fadd float %vecext3480, 0xC053F33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp409 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3482 = insertelement <4 x float> %tmp409, float %add3481, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3482, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 3.565000e+02, float 0xC0464CCCC0000000, float 0x4037666660000000, float 0xC0788CCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp410 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3484 = fadd <4 x float> %tmp410, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add3484, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp411 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3486 = fadd float undef, -1.415000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3487 = insertelement <4 x float> undef, float %add3486, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3487, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp412 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3488 = extractelement <4 x float> %tmp412, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3489 = fadd float %vecext3488, 0x405A1999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp413 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3490 = insertelement <4 x float> %tmp413, float %add3489, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3490, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3492 = fadd float undef, 0x4078066660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp414 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3493 = insertelement <4 x float> %tmp414, float %add3492, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3493, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp415 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3495 = fadd float undef, 0xC0798999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp416 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3496 = insertelement <4 x float> %tmp416, float %add3495, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3496, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp417 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp418 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3498 = fadd <4 x float> %tmp418, %tmp417
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add3498, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3499 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3500 = fadd float %vecext3499, -1.605000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3501 = insertelement <4 x float> undef, float %add3500, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp419 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3502 = extractelement <4 x float> %tmp419, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3503 = fadd float %vecext3502, 0x4058C66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp420 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3506 = fadd float undef, 0xC074DB3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp421 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins3507 = insertelement <4 x float> %tmp421, float %add3506, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins3507, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3509 = fadd float undef, 0xC066033340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp422 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x404B333340000000, float 4.680000e+02, float 0x40577999A0000000, float 0xC07D9999A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp423 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3513 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add3514 = fadd float %vecext3513, 2.300000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp424 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp425 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext3516 = extractelement <4 x float> %tmp425, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5414 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5414, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp426 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp427 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5416 = fadd <4 x float> %tmp427, %tmp426
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add5416, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp428 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5418 = fadd float undef, 0xC07ED999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp429 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5419 = insertelement <4 x float> %tmp429, float %add5418, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5624 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5624, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC07B4999A0000000, float 0x4078B33340000000, float 0xC07674CCC0000000, float 0xC07C533340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5626 = fadd <4 x float> undef, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add5626, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5627 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp430 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5629 = insertelement <4 x float> %tmp430, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5629, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp431 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5630 = extractelement <4 x float> %tmp431, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5631 = fadd float %vecext5630, 0x405EECCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5632 = insertelement <4 x float> undef, float %add5631, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5632, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp432 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5688 = insertelement <4 x float> %tmp432, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5688, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp433 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5689 = extractelement <4 x float> %tmp433, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp434 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5691 = insertelement <4 x float> %tmp434, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5691, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5692 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float -4.350000e+02, float 0xC0775CCCC0000000, float 0xC0714999A0000000, float 0xC0661999A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp435 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5696 = fadd <4 x float> undef, %tmp435
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add5696, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5701 = fadd float undef, 0x4077D4CCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp436 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5702 = insertelement <4 x float> %tmp436, float %add5701, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5702, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp437 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp438 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5705 = insertelement <4 x float> %tmp438, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5705, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp439 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5706 = extractelement <4 x float> %tmp439, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5707 = fadd float %vecext5706, 0xC0780B3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp440 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5708 = insertelement <4 x float> %tmp440, float %add5707, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5708, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x405D666660000000, float 0xC069333340000000, float 0x407B6B3340000000, float 0xC06EB33340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp441 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp442 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5710 = fadd <4 x float> %tmp442, %tmp441
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add5710, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp443 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5711 = extractelement <4 x float> %tmp443, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5712 = fadd float %vecext5711, 1.850000e+01
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp444 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5713 = insertelement <4 x float> %tmp444, float %add5712, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5713, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp445 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp446 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5716 = insertelement <4 x float> %tmp446, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp447 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5724 = fadd <4 x float> %tmp447, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add5724, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp448 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5748 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp449 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5750 = insertelement <4 x float> %tmp449, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40692999A0000000, float 0xC07C4CCCC0000000, float 0x407D1E6660000000, float 0x407B4199A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp450 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5752 = fadd <4 x float> undef, %tmp450
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5754 = fadd float undef, 0xC064033340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp451 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5755 = insertelement <4 x float> %tmp451, float %add5754, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5755, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp452 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5756 = extractelement <4 x float> %tmp452, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5757 = fadd float %vecext5756, 0x40787B3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp453 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5758 = insertelement <4 x float> %tmp453, float %add5757, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5758, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp454 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5759 = extractelement <4 x float> %tmp454, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp455 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5761 = insertelement <4 x float> %tmp455, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5761, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp456 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5762 = extractelement <4 x float> %tmp456, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5763 = fadd float %vecext5762, 0x40703E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp457 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5764 = insertelement <4 x float> %tmp457, float %add5763, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5764, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x407A6B3340000000, float 0x40470CCCC0000000, float 0xC076F4CCC0000000, float 0x40791999A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5766 = fadd <4 x float> undef, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add5766, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp458 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5767 = extractelement <4 x float> %tmp458, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5768 = fadd float %vecext5767, 0x4065533340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp459 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5769 = insertelement <4 x float> %tmp459, float %add5768, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5769, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5771 = fadd float undef, 8.000000e+00
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp460 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5772 = insertelement <4 x float> %tmp460, float %add5771, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp461 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5796 = fadd float undef, 0x4058ECCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5797 = insertelement <4 x float> undef, float %add5796, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5797, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp462 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5798 = extractelement <4 x float> %tmp462, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp463 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5800 = insertelement <4 x float> %tmp463, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp464 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5801 = extractelement <4 x float> %tmp464, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5802 = fadd float %vecext5801, 0xC072A199A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp465 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5803 = insertelement <4 x float> %tmp465, float %add5802, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5803, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp466 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5804 = extractelement <4 x float> %tmp466, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5805 = fadd float %vecext5804, 0x40785999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp467 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5806 = insertelement <4 x float> %tmp467, float %add5805, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5806, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp468 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp469 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5809 = extractelement <4 x float> %tmp469, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5810 = fadd float %vecext5809, 0x407B7B3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp470 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp471 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5818 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5819 = fadd float %vecext5818, 0x4071733340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp472 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5820 = insertelement <4 x float> %tmp472, float %add5819, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5820, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40514CCCC0000000, float 0x406A7999A0000000, float 0xC078766660000000, float 0xC0522CCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp473 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp474 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5822 = fadd <4 x float> %tmp474, %tmp473
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add5822, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp475 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5823 = extractelement <4 x float> %tmp475, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp476 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5825 = insertelement <4 x float> %tmp476, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp477 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5826 = extractelement <4 x float> %tmp477, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5827 = fadd float %vecext5826, 0x407F14CCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp478 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5828 = insertelement <4 x float> %tmp478, float %add5827, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5828, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp479 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5829 = extractelement <4 x float> %tmp479, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5830 = fadd float %vecext5829, 3.350000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp480 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5831 = insertelement <4 x float> %tmp480, float %add5830, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float -3.370000e+02, float 0xC072DE6660000000, float -2.670000e+02, float 0x4062333340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp481 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5837 = extractelement <4 x float> %tmp481, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5839 = insertelement <4 x float> undef, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5839, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp482 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5840 = extractelement <4 x float> %tmp482, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp483 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5842 = insertelement <4 x float> %tmp483, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5842, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp484 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp485 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5845 = insertelement <4 x float> %tmp485, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5845, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC06EC999A0000000, float 0x406D5999A0000000, float 0x4056F33340000000, float 0xC07E14CCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5850 = fadd <4 x float> undef, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add5850, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp486 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5852 = fadd float undef, 2.985000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp487 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5853 = insertelement <4 x float> %tmp487, float %add5852, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5853, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp488 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5854 = extractelement <4 x float> %tmp488, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5855 = fadd float %vecext5854, 0xC053F999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp489 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5856 = insertelement <4 x float> %tmp489, float %add5855, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5856, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp490 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5858 = fadd float undef, 0x4071666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp491 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5859 = insertelement <4 x float> %tmp491, float %add5858, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5859, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp492 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5860 = extractelement <4 x float> %tmp492, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp493 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5899 = extractelement <4 x float> %tmp493, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5900 = fadd float %vecext5899, -2.700000e+01
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp494 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5901 = insertelement <4 x float> %tmp494, float %add5900, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5901, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5914 = fadd float undef, 0x40786E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5918 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5918, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x406F266660000000, float 7.900000e+01, float -4.695000e+02, float -4.880000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5920 = fadd <4 x float> undef, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add5920, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5934 = fadd <4 x float> undef, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5935 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5936 = fadd float %vecext5935, 0xC056B999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp495 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp496 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5994 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add5995 = fadd float %vecext5994, 0x4051666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins5996 = insertelement <4 x float> undef, float %add5995, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins5996, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp497 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext5997 = extractelement <4 x float> %tmp497, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp498 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6000 = extractelement <4 x float> %tmp498, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6001 = fadd float %vecext6000, -7.600000e+01
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp499 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6002 = insertelement <4 x float> %tmp499, float %add6001, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6002, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC07EA199A0000000, float 0x407DC33340000000, float 0xC0753199A0000000, float -3.895000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp500 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6004 = fadd <4 x float> undef, %tmp500
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6004, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp501 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6005 = extractelement <4 x float> %tmp501, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp502 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6007 = insertelement <4 x float> %tmp502, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp503 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6008 = extractelement <4 x float> %tmp503, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp504 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6024 = insertelement <4 x float> %tmp504, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6024, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp505 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6025 = extractelement <4 x float> %tmp505, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6026 = fadd float %vecext6025, 3.700000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp506 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6027 = insertelement <4 x float> %tmp506, float %add6026, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6027, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6028 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6029 = fadd float %vecext6028, 0x4071666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp507 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6030 = insertelement <4 x float> %tmp507, float %add6029, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6030, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC0527999A0000000, float 0xC06AD999A0000000, float 0x3FF6666660000000, float 0xC03F666660000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp508 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp509 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp510 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6033 = extractelement <4 x float> %tmp510, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp511 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6036 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6037 = fadd float %vecext6036, 0xC075CB3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6038 = insertelement <4 x float> undef, float %add6037, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6038, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp512 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6040 = fadd float undef, 0x4071ECCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp513 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6041 = insertelement <4 x float> %tmp513, float %add6040, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6041, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp514 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6042 = extractelement <4 x float> %tmp514, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6043 = fadd float %vecext6042, 0xC07DD33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp515 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6044 = insertelement <4 x float> %tmp515, float %add6043, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6044, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC065FCCCC0000000, float 0x40767CCCC0000000, float 0x4079D4CCC0000000, float 0xC07314CCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp516 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp517 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6046 = fadd <4 x float> %tmp517, %tmp516
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6046, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6047 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp518 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6049 = insertelement <4 x float> %tmp518, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6049, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp519 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6050 = extractelement <4 x float> %tmp519, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6051 = fadd float %vecext6050, 0x407E4E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6055 = insertelement <4 x float> undef, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6056 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp520 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6061 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp521 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp522 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6067 = extractelement <4 x float> %tmp522, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6068 = fadd float %vecext6067, 0x40768E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6070 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6071 = fadd float %vecext6070, 0xC07C6CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6072 = insertelement <4 x float> undef, float %add6071, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6072, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40546CCCC0000000, float 0x4067D66660000000, float 0xC060E33340000000, float 0x4061533340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp523 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp524 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6074 = fadd <4 x float> %tmp524, %tmp523
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6074, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp525 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6075 = extractelement <4 x float> %tmp525, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6076 = fadd float %vecext6075, 0x405D733340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp526 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6077 = insertelement <4 x float> %tmp526, float %add6076, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6077, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp527 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6079 = fadd float undef, 0xC07E9B3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp528 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp529 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6082 = fadd float undef, 0x407DCE6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6083 = insertelement <4 x float> undef, float %add6082, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6083, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp530 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6084 = extractelement <4 x float> %tmp530, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6085 = fadd float %vecext6084, 0xC061A33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6086 = insertelement <4 x float> undef, float %add6085, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6086, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x4055C66660000000, float 0x40735199A0000000, float 0xC0713199A0000000, float 0x40729B3340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp531 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp532 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6088 = fadd <4 x float> %tmp532, %tmp531
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6088, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp533 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6089 = extractelement <4 x float> %tmp533, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6107 = fadd float undef, 0xC06A166660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp534 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6108 = insertelement <4 x float> %tmp534, float %add6107, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6108, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp535 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6109 = extractelement <4 x float> %tmp535, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6110 = fadd float %vecext6109, 0x4070FB3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp536 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp537 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6112 = extractelement <4 x float> %tmp537, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6113 = fadd float %vecext6112, 0xC04AF33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp538 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp539 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6117 = extractelement <4 x float> %tmp539, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6118 = fadd float %vecext6117, 0x407AB33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp540 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6119 = insertelement <4 x float> %tmp540, float %add6118, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6119, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp541 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6120 = extractelement <4 x float> %tmp541, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6121 = fadd float %vecext6120, 0x405AE66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp542 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6122 = insertelement <4 x float> %tmp542, float %add6121, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6122, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6123 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6124 = fadd float %vecext6123, -4.385000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp543 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6126 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp544 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6128 = insertelement <4 x float> %tmp544, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6128, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float -2.980000e+02, float 0xC06F0CCCC0000000, float 0xC054A66660000000, float 0xC040CCCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp545 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp546 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6130 = fadd <4 x float> %tmp546, %tmp545
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp547 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6131 = extractelement <4 x float> %tmp547, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6132 = fadd float %vecext6131, 0x407BDE6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6133 = insertelement <4 x float> undef, float %add6132, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6133, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6134 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6135 = fadd float %vecext6134, 0xC06B7999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp548 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6136 = insertelement <4 x float> %tmp548, float %add6135, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6137 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6138 = fadd float %vecext6137, 0x40752199A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp549 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6172 = fadd <4 x float> undef, %tmp549
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp550 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp551 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6178 = insertelement <4 x float> %tmp551, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6178, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp552 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6179 = extractelement <4 x float> %tmp552, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6180 = fadd float %vecext6179, -3.905000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp553 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6181 = insertelement <4 x float> %tmp553, float %add6180, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp554 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6182 = extractelement <4 x float> %tmp554, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6183 = fadd float %vecext6182, 1.515000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp555 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6184 = insertelement <4 x float> %tmp555, float %add6183, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6184, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp556 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6189 = insertelement <4 x float> undef, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6189, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp557 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6190 = extractelement <4 x float> %tmp557, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6191 = fadd float %vecext6190, 0xC07BD33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp558 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6192 = insertelement <4 x float> %tmp558, float %add6191, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6192, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp559 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp560 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6196 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6197 = fadd float %vecext6196, -4.070000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp561 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6198 = insertelement <4 x float> %tmp561, float %add6197, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x407904CCC0000000, float 0x406A833340000000, float 4.895000e+02, float 0x40648999A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp562 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp563 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6200 = fadd <4 x float> %tmp563, %tmp562
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6200, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp564 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6201 = extractelement <4 x float> %tmp564, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp565 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6203 = insertelement <4 x float> %tmp565, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp566 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6204 = extractelement <4 x float> %tmp566, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6205 = fadd float %vecext6204, 1.740000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp567 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6206 = insertelement <4 x float> %tmp567, float %add6205, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp568 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6209 = insertelement <4 x float> %tmp568, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6209, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp569 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6210 = extractelement <4 x float> %tmp569, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp570 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6219 = fadd float undef, 0xC0596CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp571 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6220 = insertelement <4 x float> %tmp571, float %add6219, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6224 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6225 = fadd float %vecext6224, 0xC074533340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp572 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6228 = fadd <4 x float> undef, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6228, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6229 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6230 = fadd float %vecext6229, 1.695000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp573 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6231 = insertelement <4 x float> %tmp573, float %add6230, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6231, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp574 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6232 = extractelement <4 x float> %tmp574, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6233 = fadd float %vecext6232, 0x4079C33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp575 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6234 = insertelement <4 x float> %tmp575, float %add6233, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6234, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6235 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6236 = fadd float %vecext6235, 0xC07D8199A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6237 = insertelement <4 x float> undef, float %add6236, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6237, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp576 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6245 = insertelement <4 x float> undef, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6245, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp577 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6246 = extractelement <4 x float> %tmp577, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6247 = fadd float %vecext6246, 0x40631999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp578 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6251 = insertelement <4 x float> undef, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp579 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6253 = fadd float undef, 0xC0692999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6254 = insertelement <4 x float> undef, float %add6253, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6254, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 4.600000e+02, float 0xC0777B3340000000, float 0x40351999A0000000, float 0xC06E433340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp580 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp581 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6256 = fadd <4 x float> %tmp581, %tmp580
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6256, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp582 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6257 = extractelement <4 x float> %tmp582, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6258 = fadd float %vecext6257, 4.670000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp583 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6259 = insertelement <4 x float> %tmp583, float %add6258, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6259, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp584 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6260 = extractelement <4 x float> %tmp584, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6261 = fadd float %vecext6260, 0xC05F733340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp585 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6262 = insertelement <4 x float> %tmp585, float %add6261, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6262, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp586 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6263 = extractelement <4 x float> %tmp586, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp587 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6265 = insertelement <4 x float> %tmp587, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6265, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp588 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6266 = extractelement <4 x float> %tmp588, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6267 = fadd float %vecext6266, 0x407174CCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp589 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6268 = insertelement <4 x float> %tmp589, float %add6267, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6268, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float -3.130000e+02, float 0xC079733340000000, float -4.660000e+02, float 0xC064E66660000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp590 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp591 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6270 = fadd <4 x float> %tmp591, %tmp590
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6270, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp592 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6271 = extractelement <4 x float> %tmp592, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6272 = fadd float %vecext6271, 1.765000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp593 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6273 = insertelement <4 x float> %tmp593, float %add6272, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6273, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp594 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6274 = extractelement <4 x float> %tmp594, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6275 = fadd float %vecext6274, 0x402C666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp595 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6276 = insertelement <4 x float> %tmp595, float %add6275, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6276, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp596 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6277 = extractelement <4 x float> %tmp596, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6278 = fadd float %vecext6277, -8.450000e+01
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp597 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6279 = insertelement <4 x float> %tmp597, float %add6278, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6279, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp598 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6280 = extractelement <4 x float> %tmp598, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6281 = fadd float %vecext6280, 0xC07A133340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6282 = insertelement <4 x float> undef, float %add6281, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6282, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x4067ECCCC0000000, float 0xC040CCCCC0000000, float 0xC0762E6660000000, float -4.750000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6284 = fadd <4 x float> undef, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6285 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6289 = fadd float undef, 0xC0738999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp599 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6293 = insertelement <4 x float> %tmp599, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6293, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp600 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6294 = extractelement <4 x float> %tmp600, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6295 = fadd float %vecext6294, 0xC01CCCCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6296 = insertelement <4 x float> undef, float %add6295, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6296, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40704199A0000000, float 0x40753CCCC0000000, float 0xC07E2199A0000000, float 0xC068833340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp601 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6298 = fadd <4 x float> undef, %tmp601
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6298, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp602 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6299 = extractelement <4 x float> %tmp602, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6300 = fadd float %vecext6299, 0x4074B33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp603 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6301 = insertelement <4 x float> %tmp603, float %add6300, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6301, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp604 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6302 = extractelement <4 x float> %tmp604, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6303 = fadd float %vecext6302, 0xC05B333340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp605 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6304 = insertelement <4 x float> %tmp605, float %add6303, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6304, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp606 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6305 = extractelement <4 x float> %tmp606, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6306 = fadd float %vecext6305, 0x4077E999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6307 = insertelement <4 x float> undef, float %add6306, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6307, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp607 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6308 = extractelement <4 x float> %tmp607, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6309 = fadd float %vecext6308, 0x40707E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp608 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6310 = insertelement <4 x float> %tmp608, float %add6309, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6310, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x407A233340000000, float 0x406DA33340000000, float 3.725000e+02, float 0x40761199A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp609 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp610 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6312 = fadd <4 x float> %tmp610, %tmp609
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6312, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp611 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6313 = extractelement <4 x float> %tmp611, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6314 = fadd float %vecext6313, 0xC07CF33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp612 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6315 = insertelement <4 x float> %tmp612, float %add6314, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp613 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6655 = extractelement <4 x float> %tmp613, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6656 = fadd float %vecext6655, 2.185000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp614 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6657 = insertelement <4 x float> %tmp614, float %add6656, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6657, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6660 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6660, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC064E33340000000, float 0xC064833340000000, float 0xC0673CCCC0000000, float 0xC074266660000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp615 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6663 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6664 = fadd float %vecext6663, 0xC05B7999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp616 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6665 = insertelement <4 x float> %tmp616, float %add6664, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp617 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6669 = extractelement <4 x float> %tmp617, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp618 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC07CC4CCC0000000, float 0x404EE66660000000, float 0xC0754CCCC0000000, float 0xC0744B3340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp619 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6676 = fadd <4 x float> %tmp619, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6676, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp620 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6677 = extractelement <4 x float> %tmp620, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6678 = fadd float %vecext6677, 0x4077F4CCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp621 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6679 = insertelement <4 x float> %tmp621, float %add6678, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6680 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6681 = fadd float %vecext6680, 0x4061766660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp622 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp623 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6683 = extractelement <4 x float> %tmp623, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6684 = fadd float %vecext6683, 0x40718999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp624 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6685 = insertelement <4 x float> %tmp624, float %add6684, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6685, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp625 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6686 = extractelement <4 x float> %tmp625, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6687 = fadd float %vecext6686, 0x4076D66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp626 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6688 = insertelement <4 x float> %tmp626, float %add6687, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6688, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 7.500000e+00, float 0x4077E33340000000, float 0xC0596CCCC0000000, float 0xC07D4E6660000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp627 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6690 = fadd <4 x float> undef, %tmp627
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6690, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp628 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6691 = extractelement <4 x float> %tmp628, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6692 = fadd float %vecext6691, 3.250000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp629 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6693 = insertelement <4 x float> %tmp629, float %add6692, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6693, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp630 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6694 = extractelement <4 x float> %tmp630, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6695 = fadd float %vecext6694, 0x407DF999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp631 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6696 = insertelement <4 x float> %tmp631, float %add6695, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6696, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp632 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6697 = extractelement <4 x float> %tmp632, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6698 = fadd float %vecext6697, 0xC075FE6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp633 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6699 = insertelement <4 x float> %tmp633, float %add6698, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6699, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp634 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6700 = extractelement <4 x float> %tmp634, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6701 = fadd float %vecext6700, 0xC07BCE6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp635 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6702 = insertelement <4 x float> %tmp635, float %add6701, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6702, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40772CCCC0000000, float 0xC0625CCCC0000000, float 6.200000e+01, float 0xC06ADCCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp636 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp637 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6707 = insertelement <4 x float> undef, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6707, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp638 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6708 = extractelement <4 x float> %tmp638, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp639 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp640 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6714 = extractelement <4 x float> %tmp640, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6715 = fadd float %vecext6714, 0xC0537999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp641 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6716 = insertelement <4 x float> %tmp641, float %add6715, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6719 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6720 = fadd float %vecext6719, 2.870000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp642 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6721 = insertelement <4 x float> %tmp642, float %add6720, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp643 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6722 = extractelement <4 x float> %tmp643, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6723 = fadd float %vecext6722, 0xC07704CCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp644 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6724 = insertelement <4 x float> %tmp644, float %add6723, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp645 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6726 = fadd float undef, 0x4059B999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp646 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6727 = insertelement <4 x float> %tmp646, float %add6726, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6727, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6728 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6729 = fadd float %vecext6728, 0xC073466660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC0309999A0000000, float -2.715000e+02, float 1.620000e+02, float 0x40674CCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp647 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp648 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6732 = fadd <4 x float> %tmp648, %tmp647
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6732, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp649 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6733 = extractelement <4 x float> %tmp649, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6734 = fadd float %vecext6733, 0x4040733340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp650 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6735 = insertelement <4 x float> %tmp650, float %add6734, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6735, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp651 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6736 = extractelement <4 x float> %tmp651, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6737 = fadd float %vecext6736, 0xC07B74CCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp652 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6738 = insertelement <4 x float> %tmp652, float %add6737, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6738, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp653 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6739 = extractelement <4 x float> %tmp653, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6740 = fadd float %vecext6739, 0x40699CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp654 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6741 = insertelement <4 x float> %tmp654, float %add6740, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6741, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp655 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6742 = extractelement <4 x float> %tmp655, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6743 = fadd float %vecext6742, 0x4078533340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp656 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6744 = insertelement <4 x float> %tmp656, float %add6743, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6744, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp657 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp658 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6746 = fadd <4 x float> %tmp658, %tmp657
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6746, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp659 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6749 = insertelement <4 x float> undef, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6749, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp660 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6751 = fadd float undef, 0x4075DE6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6752 = insertelement <4 x float> undef, float %add6751, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6752, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp661 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6753 = extractelement <4 x float> %tmp661, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6754 = fadd float %vecext6753, 0xC008CCCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6755 = insertelement <4 x float> undef, float %add6754, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6755, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp662 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6756 = extractelement <4 x float> %tmp662, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6757 = fadd float %vecext6756, 0x406CA999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp663 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6758 = insertelement <4 x float> %tmp663, float %add6757, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6758, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x403D1999A0000000, float 0xC05F533340000000, float 3.945000e+02, float 3.950000e+01>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp664 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6760 = fadd <4 x float> undef, %tmp664
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6760, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp665 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6761 = extractelement <4 x float> %tmp665, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6762 = fadd float %vecext6761, 2.860000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6763 = insertelement <4 x float> undef, float %add6762, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp666 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC079BE6660000000, float 4.930000e+02, float 0x406CC33340000000, float 0xC062E999A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp667 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6774 = fadd <4 x float> undef, %tmp667
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp668 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6775 = extractelement <4 x float> %tmp668, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6776 = fadd float %vecext6775, 0x407B8199A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp669 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6777 = insertelement <4 x float> %tmp669, float %add6776, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6777, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp670 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6778 = extractelement <4 x float> %tmp670, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6779 = fadd float %vecext6778, 0x401C666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp671 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6784 = extractelement <4 x float> %tmp671, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6875 = insertelement <4 x float> undef, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6875, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp672 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6876 = extractelement <4 x float> %tmp672, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6877 = fadd float %vecext6876, 0x4073A66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6878 = insertelement <4 x float> undef, float %add6877, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6878, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6888 = fadd float undef, 0x4057CCCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp673 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6889 = insertelement <4 x float> %tmp673, float %add6888, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6889, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp674 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6890 = extractelement <4 x float> %tmp674, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6891 = fadd float %vecext6890, -4.430000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp675 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6892 = insertelement <4 x float> %tmp675, float %add6891, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6892, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp676 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6893 = extractelement <4 x float> %tmp676, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6894 = fadd float %vecext6893, -3.280000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp677 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6895 = insertelement <4 x float> %tmp677, float %add6894, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6895, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp678 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp679 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp680 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6900 = fadd <4 x float> %tmp680, %tmp679
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6900, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp681 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6901 = extractelement <4 x float> %tmp681, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6902 = fadd float %vecext6901, 0x4079DCCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp682 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6903 = insertelement <4 x float> %tmp682, float %add6902, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6903, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6905 = fadd float undef, 0x4031B33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp683 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6906 = insertelement <4 x float> %tmp683, float %add6905, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp684 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6912 = insertelement <4 x float> %tmp684, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 3.315000e+02, float 0xC066C999A0000000, float 0xC061F33340000000, float 0x4071166660000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp685 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp686 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6914 = fadd <4 x float> %tmp686, %tmp685
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6914, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6915 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6920 = insertelement <4 x float> undef, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6920, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6921 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6922 = fadd float %vecext6921, 0xC064066660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp687 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6926 = insertelement <4 x float> %tmp687, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6926, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC03C4CCCC0000000, float 0xC07E5199A0000000, float -8.250000e+01, float 0xC043B33340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp688 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp689 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6928 = fadd <4 x float> %tmp689, %tmp688
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6928, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6930 = fadd float undef, -4.590000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6931 = insertelement <4 x float> undef, float %add6930, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6931, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp690 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6932 = extractelement <4 x float> %tmp690, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6933 = fadd float %vecext6932, 0xC063F999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp691 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp692 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6935 = extractelement <4 x float> %tmp692, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6936 = fadd float %vecext6935, -3.335000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp693 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6937 = insertelement <4 x float> %tmp693, float %add6936, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp694 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6938 = extractelement <4 x float> %tmp694, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6939 = fadd float %vecext6938, 0x405F3999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6942 = fadd <4 x float> undef, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6943 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6944 = fadd float %vecext6943, 0x40530CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp695 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6950 = fadd float undef, 0xC078F33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp696 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6951 = insertelement <4 x float> %tmp696, float %add6950, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6951, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp697 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6952 = extractelement <4 x float> %tmp697, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6953 = fadd float %vecext6952, 0xC06E5999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp698 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6954 = insertelement <4 x float> %tmp698, float %add6953, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6954, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp699 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp700 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6956 = fadd <4 x float> %tmp700, %tmp699
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6956, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp701 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6957 = extractelement <4 x float> %tmp701, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6958 = fadd float %vecext6957, 0xC077633340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp702 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6959 = insertelement <4 x float> %tmp702, float %add6958, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6959, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp703 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6963 = extractelement <4 x float> %tmp703, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6964 = fadd float %vecext6963, 0x4068666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp704 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6965 = insertelement <4 x float> %tmp704, float %add6964, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6965, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6975 = fadd float undef, 0x406AF33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp705 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6976 = insertelement <4 x float> %tmp705, float %add6975, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6976, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp706 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp707 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6984 = fadd <4 x float> %tmp707, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6984, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp708 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6985 = extractelement <4 x float> %tmp708, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6986 = fadd float %vecext6985, 0xC05E266660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp709 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6987 = insertelement <4 x float> %tmp709, float %add6986, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6987, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp710 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6988 = extractelement <4 x float> %tmp710, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6989 = fadd float %vecext6988, 0x40706E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp711 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins6996 = insertelement <4 x float> %tmp711, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins6996, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x4077A4CCC0000000, float 0xC0757199A0000000, float 0xC072F4CCC0000000, float 0xC071DCCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp712 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp713 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add6998 = fadd <4 x float> %tmp713, %tmp712
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add6998, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp714 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext6999 = extractelement <4 x float> %tmp714, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7000 = fadd float %vecext6999, 0x4076233340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp715 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7001 = insertelement <4 x float> %tmp715, float %add7000, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7001, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp716 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7002 = extractelement <4 x float> %tmp716, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7003 = fadd float %vecext7002, 0x403BCCCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp717 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7004 = insertelement <4 x float> %tmp717, float %add7003, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp718 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7140 = fadd float undef, 0x403D333340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7141 = insertelement <4 x float> undef, float %add7140, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7142 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7143 = fadd float %vecext7142, 0xC058F999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7144 = insertelement <4 x float> undef, float %add7143, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp719 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7148 = extractelement <4 x float> %tmp719, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7149 = fadd float %vecext7148, 0x4075333340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp720 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7150 = insertelement <4 x float> %tmp720, float %add7149, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7150, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 1.700000e+02, float 0xC077B4CCC0000000, float 0x40625999A0000000, float 0x406C166660000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp721 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7152 = fadd <4 x float> %tmp721, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add7152, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7156 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7157 = fadd float %vecext7156, 0xC05F533340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp722 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7158 = insertelement <4 x float> %tmp722, float %add7157, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7158, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp723 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7159 = extractelement <4 x float> %tmp723, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7160 = fadd float %vecext7159, 0x407A5999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp724 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7161 = insertelement <4 x float> %tmp724, float %add7160, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7161, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7168 = fadd float undef, 0xC072F199A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp725 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7170 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7171 = fadd float %vecext7170, 0x406AACCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7172 = insertelement <4 x float> undef, float %add7171, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7172, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7173 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp726 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7419 = extractelement <4 x float> %tmp726, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7420 = fadd float %vecext7419, 0x404EA66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7421 = insertelement <4 x float> undef, float %add7420, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7421, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp727 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7422 = extractelement <4 x float> %tmp727, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7423 = fadd float %vecext7422, 4.800000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp728 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7424 = insertelement <4 x float> %tmp728, float %add7423, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7424, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp729 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7425 = extractelement <4 x float> %tmp729, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7426 = fadd float %vecext7425, 0xC072C999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp730 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7427 = insertelement <4 x float> %tmp730, float %add7426, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7427, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7428 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp731 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7568 = extractelement <4 x float> %tmp731, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7569 = fadd float %vecext7568, 1.090000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp732 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7570 = insertelement <4 x float> %tmp732, float %add7569, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7570, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40745199A0000000, float 0xC0411999A0000000, float -5.650000e+01, float -4.005000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp733 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp734 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7572 = fadd <4 x float> %tmp734, %tmp733
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add7572, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7573 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7574 = fadd float %vecext7573, -3.920000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp735 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7575 = insertelement <4 x float> %tmp735, float %add7574, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7575, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp736 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7577 = fadd float undef, 0xC051666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp737 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp738 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7579 = extractelement <4 x float> %tmp738, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7580 = fadd float %vecext7579, 0x407E9199A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7581 = insertelement <4 x float> undef, float %add7580, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7581, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp739 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7582 = extractelement <4 x float> %tmp739, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7583 = fadd float %vecext7582, 2.760000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp740 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7584 = insertelement <4 x float> %tmp740, float %add7583, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC057533340000000, float 0x4060A33340000000, float 0x40791E6660000000, float 2.455000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp741 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp742 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7586 = fadd <4 x float> %tmp742, %tmp741
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add7586, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp743 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7587 = extractelement <4 x float> %tmp743, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7588 = fadd float %vecext7587, 6.100000e+01
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp744 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp745 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7590 = extractelement <4 x float> %tmp745, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7591 = fadd float %vecext7590, -3.935000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp746 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7592 = insertelement <4 x float> %tmp746, float %add7591, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7592, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp747 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7593 = extractelement <4 x float> %tmp747, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7595 = insertelement <4 x float> undef, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7595, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp748 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7596 = extractelement <4 x float> %tmp748, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7597 = fadd float %vecext7596, 0x407E666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x406A766660000000, float 0xBFC99999A0000000, float 0xC0751B3340000000, float -4.075000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp749 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7616 = fadd float undef, 0xC04DE66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp750 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7617 = insertelement <4 x float> %tmp750, float %add7616, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7617, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp751 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7618 = extractelement <4 x float> %tmp751, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7619 = fadd float %vecext7618, 6.050000e+01
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp752 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7620 = insertelement <4 x float> %tmp752, float %add7619, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7620, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp753 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7622 = fadd float undef, 0xC054B999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp754 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7626 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7626, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp755 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp756 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7628 = fadd <4 x float> %tmp756, %tmp755
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add7628, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp757 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7629 = extractelement <4 x float> %tmp757, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7630 = fadd float %vecext7629, 0xC05E2CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp758 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7631 = insertelement <4 x float> %tmp758, float %add7630, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7639 = fadd float undef, 0x407C5999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp759 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7640 = insertelement <4 x float> %tmp759, float %add7639, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x406AA66660000000, float 0x4067C66660000000, float 0xC054866660000000, float -2.400000e+01>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp760 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7642 = fadd <4 x float> %tmp760, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp761 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7644 = fadd float undef, 0xC0758999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp762 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7646 = extractelement <4 x float> %tmp762, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7647 = fadd float %vecext7646, 0xC07A3B3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp763 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7648 = insertelement <4 x float> %tmp763, float %add7647, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7648, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp764 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7649 = extractelement <4 x float> %tmp764, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7650 = fadd float %vecext7649, 0x40760CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp765 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7651 = insertelement <4 x float> %tmp765, float %add7650, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7651, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp766 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7652 = extractelement <4 x float> %tmp766, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7653 = fadd float %vecext7652, 0x40620CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp767 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7654 = insertelement <4 x float> %tmp767, float %add7653, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7654, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp768 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp769 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7656 = fadd <4 x float> %tmp769, %tmp768
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add7656, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp770 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7657 = extractelement <4 x float> %tmp770, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7658 = fadd float %vecext7657, 0xC06EF999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp771 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7659 = insertelement <4 x float> %tmp771, float %add7658, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7659, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp772 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7660 = extractelement <4 x float> %tmp772, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7661 = fadd float %vecext7660, 0x404B9999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp773 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7662 = insertelement <4 x float> %tmp773, float %add7661, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7662, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp774 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7663 = extractelement <4 x float> %tmp774, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7664 = fadd float %vecext7663, 0x4074B66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp775 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7665 = insertelement <4 x float> %tmp775, float %add7664, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7665, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp776 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7666 = extractelement <4 x float> %tmp776, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7667 = fadd float %vecext7666, 0x4074166660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7668 = insertelement <4 x float> undef, float %add7667, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7668, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp777 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp778 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7670 = fadd <4 x float> %tmp778, %tmp777
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp779 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7671 = extractelement <4 x float> %tmp779, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7672 = fadd float %vecext7671, 0x406F166660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7726 = fadd <4 x float> undef, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp780 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7727 = extractelement <4 x float> %tmp780, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp781 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp782 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7731 = fadd float undef, 1.900000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp783 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7732 = insertelement <4 x float> %tmp783, float %add7731, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7732, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp784 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7735 = insertelement <4 x float> %tmp784, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7735, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp785 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext7736 = extractelement <4 x float> %tmp785, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7737 = fadd float %vecext7736, 0xC06AF66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins7850 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins7850, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x4062A33340000000, float 2.290000e+02, float 0x40509999A0000000, float 0xC078BE6660000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp786 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp787 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add7852 = fadd <4 x float> %tmp787, %tmp786
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add7852, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp788 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9396 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9397 = fadd float %vecext9396, 0xC074533340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp789 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9398 = insertelement <4 x float> %tmp789, float %add9397, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9398, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9399 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp790 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9401 = insertelement <4 x float> %tmp790, float undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp791 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9402 = extractelement <4 x float> %tmp791, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9403 = fadd float %vecext9402, 0xC03E4CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp792 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9404 = insertelement <4 x float> %tmp792, float %add9403, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9404, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp793 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp794 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9407 = extractelement <4 x float> %tmp794, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9408 = fadd float %vecext9407, 0x407B2999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp795 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9410 = extractelement <4 x float> %tmp795, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9411 = fadd float %vecext9410, 0x40726E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp796 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp797 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9413 = extractelement <4 x float> %tmp797, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9414 = fadd float %vecext9413, 0xC057ECCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp798 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9415 = insertelement <4 x float> %tmp798, float %add9414, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9415, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp799 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9416 = extractelement <4 x float> %tmp799, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9417 = fadd float %vecext9416, 0x406B0CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp800 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9418 = insertelement <4 x float> %tmp800, float %add9417, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9418, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 3.555000e+02, float 0xC062E33340000000, float 0x4065C66660000000, float -3.645000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp801 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp802 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9420 = fadd <4 x float> %tmp802, %tmp801
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add9420, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp803 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9421 = extractelement <4 x float> %tmp803, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp804 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9423 = insertelement <4 x float> %tmp804, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9423, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp805 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9424 = extractelement <4 x float> %tmp805, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9425 = fadd float %vecext9424, 0x4079C199A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp806 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9426 = insertelement <4 x float> %tmp806, float %add9425, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9426, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp807 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9428 = fadd float undef, 0xC065466660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp808 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9429 = insertelement <4 x float> %tmp808, float %add9428, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9429, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp809 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9430 = extractelement <4 x float> %tmp809, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9431 = fadd float %vecext9430, 0xC0742CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp810 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9432 = insertelement <4 x float> %tmp810, float %add9431, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC07C7E6660000000, float 1.205000e+02, float 0x4050D999A0000000, float 0xC06B233340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp811 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp812 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9434 = fadd <4 x float> %tmp812, %tmp811
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9436 = fadd float undef, -3.185000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp813 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9437 = insertelement <4 x float> %tmp813, float %add9436, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp814 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp815 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9441 = extractelement <4 x float> %tmp815, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9442 = fadd float %vecext9441, 0xC079CE6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp816 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9443 = insertelement <4 x float> %tmp816, float %add9442, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9443, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp817 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9444 = extractelement <4 x float> %tmp817, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9445 = fadd float %vecext9444, 0xC06F533340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp818 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9446 = insertelement <4 x float> %tmp818, float %add9445, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9446, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp819 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp820 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9448 = fadd <4 x float> %tmp820, %tmp819
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add9448, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9450 = fadd float undef, 0xC0718199A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp821 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9451 = insertelement <4 x float> %tmp821, float %add9450, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9451, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp822 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp823 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9454 = insertelement <4 x float> %tmp823, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9454, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp824 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9455 = extractelement <4 x float> %tmp824, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9456 = fadd float %vecext9455, -3.380000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp825 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9457 = insertelement <4 x float> %tmp825, float %add9456, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9457, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9458 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp826 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9460 = insertelement <4 x float> %tmp826, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9460, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x407B5E6660000000, float 0x40648999A0000000, float 0xC06B966660000000, float 0x40341999A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp827 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9462 = fadd <4 x float> %tmp827, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add9462, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp828 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9463 = extractelement <4 x float> %tmp828, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp829 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9465 = insertelement <4 x float> %tmp829, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9467 = fadd float undef, 0x405D666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp830 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9468 = insertelement <4 x float> %tmp830, float %add9467, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9468, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp831 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9470 = fadd float undef, 0x4077033340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp832 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9472 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9473 = fadd float %vecext9472, 0x402DCCCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp833 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9474 = insertelement <4 x float> %tmp833, float %add9473, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9474, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x404F733340000000, float 0x407AB4CCC0000000, float 0x40605999A0000000, float 0xC03E4CCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp834 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp835 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9476 = fadd <4 x float> %tmp835, %tmp834
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add9476, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp836 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9477 = extractelement <4 x float> %tmp836, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9478 = fadd float %vecext9477, 0xC07F266660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp837 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9479 = insertelement <4 x float> %tmp837, float %add9478, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9479, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp838 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9481 = fadd float undef, 0x407BE33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp839 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9482 = insertelement <4 x float> %tmp839, float %add9481, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9482, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9483 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9484 = fadd float %vecext9483, 0xC073E999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp840 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9485 = insertelement <4 x float> %tmp840, float %add9484, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9485, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp841 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9486 = extractelement <4 x float> %tmp841, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9487 = fadd float %vecext9486, 0x4076E66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp842 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC076B999A0000000, float 0xC0706CCCC0000000, float 0x407904CCC0000000, float 0x407EE199A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp843 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp844 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9491 = extractelement <4 x float> %tmp844, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9492 = fadd float %vecext9491, 0x407C166660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9495 = fadd float undef, 0x407DBB3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp845 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9496 = insertelement <4 x float> %tmp845, float %add9495, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9496, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp846 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9497 = extractelement <4 x float> %tmp846, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9498 = fadd float %vecext9497, 0x4042CCCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp847 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9499 = insertelement <4 x float> %tmp847, float %add9498, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9499, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp848 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9501 = fadd float undef, 0x407D5CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp849 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9502 = insertelement <4 x float> %tmp849, float %add9501, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9502, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp850 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9504 = fadd <4 x float> %tmp850, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add9504, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp851 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9506 = fadd float undef, 0x4076EE6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp852 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9507 = insertelement <4 x float> %tmp852, float %add9506, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9507, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp853 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9509 = fadd float undef, 0xC0535999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp854 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp855 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9511 = extractelement <4 x float> %tmp855, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9512 = fadd float %vecext9511, 0xC076766660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp856 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9513 = insertelement <4 x float> %tmp856, float %add9512, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9513, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp857 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9514 = extractelement <4 x float> %tmp857, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp858 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9516 = insertelement <4 x float> %tmp858, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9516, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x407254CCC0000000, float 0x407844CCC0000000, float 0xC04D9999A0000000, float 0xC0550CCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp859 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp860 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9518 = fadd <4 x float> %tmp860, %tmp859
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp861 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp862 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9521 = insertelement <4 x float> %tmp862, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9521, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp863 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9522 = extractelement <4 x float> %tmp863, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9523 = fadd float %vecext9522, 0x4029333340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp864 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9524 = insertelement <4 x float> %tmp864, float %add9523, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9524, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp865 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9526 = fadd float undef, 0x4072833340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp866 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9527 = insertelement <4 x float> %tmp866, float %add9526, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9527, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp867 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9530 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9530, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x4072F4CCC0000000, float 0x4065CCCCC0000000, float 0x4051D33340000000, float 0x40680CCCC0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp868 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp869 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9532 = fadd <4 x float> %tmp869, %tmp868
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9533 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp870 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9535 = insertelement <4 x float> %tmp870, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9535, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp871 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9536 = extractelement <4 x float> %tmp871, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9537 = fadd float %vecext9536, 0xC079F199A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp872 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9538 = insertelement <4 x float> %tmp872, float %add9537, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9538, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp873 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9542 = extractelement <4 x float> %tmp873, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9543 = fadd float %vecext9542, 0x4050D999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9576 = fadd float undef, 0x40219999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9577 = insertelement <4 x float> undef, float %add9576, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9577, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp874 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9580 = insertelement <4 x float> undef, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9580, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp875 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9581 = extractelement <4 x float> %tmp875, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9582 = fadd float %vecext9581, 0xC07EF33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp876 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9583 = insertelement <4 x float> %tmp876, float %add9582, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9583, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp877 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9673 = extractelement <4 x float> undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9674 = fadd float %vecext9673, 0xC04CF33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp878 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9675 = insertelement <4 x float> %tmp878, float %add9674, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9675, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9676 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9677 = fadd float %vecext9676, 1.455000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp879 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9678 = insertelement <4 x float> %tmp879, float %add9677, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp880 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9679 = extractelement <4 x float> %tmp880, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9680 = fadd float %vecext9679, 0x4073A33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp881 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9681 = insertelement <4 x float> %tmp881, float %add9680, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9681, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp882 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9682 = extractelement <4 x float> %tmp882, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp883 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9686 = fadd <4 x float> %tmp883, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add9686, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp884 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9687 = extractelement <4 x float> %tmp884, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9688 = fadd float %vecext9687, 0xC046666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp885 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9689 = insertelement <4 x float> %tmp885, float %add9688, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9690 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9691 = fadd float %vecext9690, 0x4034CCCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp886 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9692 = insertelement <4 x float> %tmp886, float %add9691, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp887 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9693 = extractelement <4 x float> %tmp887, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9694 = fadd float %vecext9693, -3.710000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp888 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9695 = insertelement <4 x float> %tmp888, float %add9694, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9695, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp889 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9697 = fadd float undef, 0x4058D33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp890 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9698 = insertelement <4 x float> %tmp890, float %add9697, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9698, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x4062CCCCC0000000, float 0x407AD999A0000000, float 0x40582CCCC0000000, float 0xC0712B3340000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp891 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9700 = fadd <4 x float> %tmp891, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp892 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9701 = extractelement <4 x float> %tmp892, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9702 = fadd float %vecext9701, 0x406DC33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp893 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9703 = insertelement <4 x float> %tmp893, float %add9702, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9703, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp894 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9704 = extractelement <4 x float> %tmp894, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9705 = fadd float %vecext9704, 0xC073B33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp895 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9706 = insertelement <4 x float> %tmp895, float %add9705, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9706, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9707 = extractelement <4 x float> undef, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9708 = fadd float %vecext9707, 0xC0729999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp896 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9709 = insertelement <4 x float> %tmp896, float %add9708, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9709, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp897 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9710 = extractelement <4 x float> %tmp897, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9712 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9712, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x4069F33340000000, float 0xC048266660000000, float 0x40638CCCC0000000, float 0xC07EC199A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp898 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9714 = fadd <4 x float> undef, %tmp898
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add9714, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp899 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9715 = extractelement <4 x float> %tmp899, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp900 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9717 = insertelement <4 x float> %tmp900, float undef, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9717, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp901 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9718 = extractelement <4 x float> %tmp901, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9719 = fadd float %vecext9718, 0x406BC66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp902 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9720 = insertelement <4 x float> %tmp902, float %add9719, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9720, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp903 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9721 = extractelement <4 x float> %tmp903, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9722 = fadd float %vecext9721, -3.860000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp904 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9723 = insertelement <4 x float> %tmp904, float %add9722, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9723, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp905 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9724 = extractelement <4 x float> %tmp905, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9725 = fadd float %vecext9724, 0x407CF199A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp906 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9726 = insertelement <4 x float> %tmp906, float %add9725, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9726, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float -4.575000e+02, float 0x40713E6660000000, float 0x407D133340000000, float -1.425000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp907 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9728 = fadd <4 x float> %tmp907, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add9728, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp908 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9729 = extractelement <4 x float> %tmp908, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9730 = fadd float %vecext9729, 0x4079FB3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp909 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9731 = insertelement <4 x float> %tmp909, float %add9730, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9731, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp910 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9733 = fadd float undef, 0xC050F33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp911 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9734 = insertelement <4 x float> %tmp911, float %add9733, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9734, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp912 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9735 = extractelement <4 x float> %tmp912, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9736 = fadd float %vecext9735, 0x40582CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp913 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9737 = insertelement <4 x float> %tmp913, float %add9736, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9737, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp914 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9738 = extractelement <4 x float> %tmp914, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9740 = insertelement <4 x float> undef, float undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9740, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 2.150000e+02, float 0x405A2CCCC0000000, float 2.310000e+02, float 0x404E1999A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp915 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp916 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp917 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9743 = extractelement <4 x float> %tmp917, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9744 = fadd float %vecext9743, -2.510000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9745 = insertelement <4 x float> undef, float %add9744, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9745, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp918 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9746 = extractelement <4 x float> %tmp918, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9747 = fadd float %vecext9746, 4.685000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp919 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9748 = insertelement <4 x float> %tmp919, float %add9747, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9748, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp920 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9749 = extractelement <4 x float> %tmp920, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9750 = fadd float %vecext9749, 1.600000e+01
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp921 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9751 = insertelement <4 x float> %tmp921, float %add9750, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9751, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp922 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9752 = extractelement <4 x float> %tmp922, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9753 = fadd float %vecext9752, -2.600000e+01
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp923 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9754 = insertelement <4 x float> %tmp923, float %add9753, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9754, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 2.590000e+02, float 0x407B7199A0000000, float 0xC07ED199A0000000, float 0xC064FCCCC0000000>, <4 x float>* %.compoundliteral9755
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp924 = load <4 x float>, <4 x float>* %.compoundliteral9755
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp925 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9756 = fadd <4 x float> %tmp925, %tmp924
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp926 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9757 = extractelement <4 x float> %tmp926, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9758 = fadd float %vecext9757, -1.810000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp927 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9759 = insertelement <4 x float> %tmp927, float %add9758, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9759, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp928 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9760 = extractelement <4 x float> %tmp928, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9761 = fadd float %vecext9760, 0xC07C3E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp929 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9762 = insertelement <4 x float> %tmp929, float %add9761, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9762, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp930 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9764 = fadd float undef, 0xC060E66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp931 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9765 = insertelement <4 x float> %tmp931, float %add9764, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9765, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp932 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9766 = extractelement <4 x float> %tmp932, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9767 = fadd float %vecext9766, 0xC0753E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp933 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9768 = insertelement <4 x float> %tmp933, float %add9767, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9768, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x4032CCCCC0000000, float -9.600000e+01, float -5.000000e+02, float 0x4078EE6660000000>, <4 x float>* %.compoundliteral9769
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp934 = load <4 x float>, <4 x float>* %.compoundliteral9769
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp935 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9770 = fadd <4 x float> %tmp935, %tmp934
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add9770, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp936 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9771 = extractelement <4 x float> %tmp936, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9772 = fadd float %vecext9771, 0xC0733E6660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp937 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9773 = insertelement <4 x float> %tmp937, float %add9772, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9773, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp938 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9774 = extractelement <4 x float> %tmp938, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add9775 = fadd float %vecext9774, 1.715000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp939 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9776 = insertelement <4 x float> %tmp939, float %add9775, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins9776, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext9816 = extractelement <4 x float> undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp940 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins9818 = insertelement <4 x float> %tmp940, float undef, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp941 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10388 = fadd float undef, 4.755000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp942 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10389 = insertelement <4 x float> %tmp942, float %add10388, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10389, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp943 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10390 = extractelement <4 x float> %tmp943, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10391 = fadd float %vecext10390, 0xC05AECCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp944 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10392 = insertelement <4 x float> %tmp944, float %add10391, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10392, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp945 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp946 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10405 = fadd float undef, -5.650000e+01
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp947 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10406 = insertelement <4 x float> %tmp947, float %add10405, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10406, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp948 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10407 = extractelement <4 x float> %tmp948, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10408 = fadd float %vecext10407, 0xC06A633340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp949 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10409 = insertelement <4 x float> %tmp949, float %add10408, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10409, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp950 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10410 = extractelement <4 x float> %tmp950, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10411 = fadd float %vecext10410, 0xC078D66660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp951 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float -2.340000e+02, float -4.720000e+02, float 4.350000e+02, float 0xC059A66660000000>, <4 x float>* %.compoundliteral10413
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp952 = load <4 x float>, <4 x float>* %.compoundliteral10413
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp953 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10414 = fadd <4 x float> %tmp953, %tmp952
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add10414, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp954 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10415 = extractelement <4 x float> %tmp954, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10416 = fadd float %vecext10415, 3.450000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp955 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10417 = insertelement <4 x float> %tmp955, float %add10416, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10417, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp956 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10418 = extractelement <4 x float> %tmp956, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10419 = fadd float %vecext10418, -6.000000e+00
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp957 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10420 = insertelement <4 x float> %tmp957, float %add10419, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10420, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10422 = fadd float undef, 0xC0662CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10424 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> undef, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x402B333340000000, float 0x40735E6660000000, float 0xC0567999A0000000, float 2.050000e+02>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp958 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp959 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10428 = fadd <4 x float> %tmp959, %tmp958
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add10428, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp960 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10429 = extractelement <4 x float> %tmp960, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10430 = fadd float %vecext10429, 0xC075166660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp961 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10436 = fadd float undef, 0xC06AF33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp962 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10437 = insertelement <4 x float> %tmp962, float %add10436, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10437, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10438 = extractelement <4 x float> undef, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10439 = fadd float %vecext10438, 0x405C7999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp963 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10440 = insertelement <4 x float> %tmp963, float %add10439, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10440, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC065E999A0000000, float 0x4067D33340000000, float 0xC070133340000000, float 0x406B666660000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp964 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp965 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10443 = extractelement <4 x float> %tmp965, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10444 = fadd float %vecext10443, 0xC06CA999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp966 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10445 = insertelement <4 x float> %tmp966, float %add10444, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10445, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp967 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10446 = extractelement <4 x float> %tmp967, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10447 = fadd float %vecext10446, 0x4064B999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp968 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10448 = insertelement <4 x float> %tmp968, float %add10447, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10448, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp969 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10449 = extractelement <4 x float> %tmp969, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10450 = fadd float %vecext10449, 0x407B3CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp970 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10451 = insertelement <4 x float> %tmp970, float %add10450, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10451, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp971 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10452 = extractelement <4 x float> %tmp971, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10453 = fadd float %vecext10452, -2.225000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10454 = insertelement <4 x float> undef, float %add10453, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x406AFCCCC0000000, float 0xC07604CCC0000000, float 6.900000e+01, float 0xC060A66660000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp972 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp973 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10456 = fadd <4 x float> %tmp973, %tmp972
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %add10456, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp974 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10457 = extractelement <4 x float> %tmp974, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10458 = fadd float %vecext10457, 2.375000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10459 = insertelement <4 x float> undef, float %add10458, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10459, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp975 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10460 = extractelement <4 x float> %tmp975, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10461 = fadd float %vecext10460, 0xC06B3999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp976 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10462 = insertelement <4 x float> %tmp976, float %add10461, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp977 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10463 = extractelement <4 x float> %tmp977, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10464 = fadd float %vecext10463, 0x40655999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp978 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10465 = insertelement <4 x float> %tmp978, float %add10464, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10465, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp979 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10466 = extractelement <4 x float> %tmp979, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10467 = fadd float %vecext10466, 0xC07B6999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp980 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10468 = insertelement <4 x float> %tmp980, float %add10467, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10468, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x4078833340000000, float 0x40786CCCC0000000, float 0xC0468CCCC0000000, float 0xC0793199A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp981 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10470 = fadd <4 x float> %tmp981, undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp982 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10471 = extractelement <4 x float> %tmp982, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10472 = fadd float %vecext10471, 0x40710CCCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp983 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10473 = insertelement <4 x float> %tmp983, float %add10472, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10473, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp984 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10474 = extractelement <4 x float> %tmp984, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10475 = fadd float %vecext10474, 0x40709B3340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp985 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10476 = insertelement <4 x float> %tmp985, float %add10475, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10476, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10489 = fadd float undef, 0x4074666660000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp986 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10490 = insertelement <4 x float> %tmp986, float %add10489, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10490, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp987 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp988 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10508 = extractelement <4 x float> %tmp988, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10509 = fadd float %vecext10508, 0xC027333340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp989 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10510 = insertelement <4 x float> %tmp989, float %add10509, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10510, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0x40656999A0000000, float 0xC073766660000000, float 1.685000e+02, float 0x40765199A0000000>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp990 = load <4 x float>, <4 x float>* undef
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10512 = fadd <4 x float> undef, %tmp990
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp991 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10513 = extractelement <4 x float> %tmp991, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10514 = fadd float %vecext10513, 0x405BB999A0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp992 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10515 = insertelement <4 x float> %tmp992, float %add10514, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10515, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp993 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10562 = fadd float undef, 2.035000e+02
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp994 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10563 = insertelement <4 x float> %tmp994, float %add10562, i32 2
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10563, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp995 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10564 = extractelement <4 x float> %tmp995, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10565 = fadd float %vecext10564, 0x407AE4CCC0000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp996 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10566 = insertelement <4 x float> %tmp996, float %add10565, i32 3
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10566, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> <float 0xC068B999A0000000, float 0xC050E66660000000, float 0xC0725999A0000000, float 0xC054D33340000000>, <4 x float>* %.compoundliteral10567
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp997 = load <4 x float>, <4 x float>* %.compoundliteral10567
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp998 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10568 = fadd <4 x float> %tmp998, %tmp997
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp999 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10569 = extractelement <4 x float> %tmp999, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10570 = fadd float %vecext10569, 0x4074C33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp1000 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10571 = insertelement <4 x float> %tmp1000, float %add10570, i32 0
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10571, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp1001 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecext10572 = extractelement <4 x float> %tmp1001, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %add10573 = fadd float %vecext10572, 0x407DF33340000000
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %tmp1002 = load <4 x float>, <4 x float>* undef, align 16
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  %vecins10574 = insertelement <4 x float> %tmp1002, float %add10573, i32 1
+  tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
+  store <4 x float> %vecins10574, <4 x float>* undef, align 16
+  %tmp1003 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10575 = extractelement <4 x float> %tmp1003, i32 2
+  %tmp1004 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10577 = insertelement <4 x float> %tmp1004, float undef, i32 2
+  store <4 x float> %vecins10577, <4 x float>* undef, align 16
+  %tmp1005 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10578 = extractelement <4 x float> %tmp1005, i32 3
+  %add10579 = fadd float %vecext10578, 0x4076566660000000
+  %tmp1006 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10580 = insertelement <4 x float> %tmp1006, float %add10579, i32 3
+  store <4 x float> %vecins10580, <4 x float>* undef, align 16
+  store <4 x float> <float 0x407CAB3340000000, float 1.685000e+02, float 0xC07B866660000000, float 0xC061ACCCC0000000>, <4 x float>* %.compoundliteral10581
+  %tmp1007 = load <4 x float>, <4 x float>* %.compoundliteral10581
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %tmp1008 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10583 = extractelement <4 x float> %tmp1008, i32 0
+  %add10584 = fadd float %vecext10583, 0xC060533340000000
+  %tmp1009 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10585 = insertelement <4 x float> %tmp1009, float %add10584, i32 0
+  store <4 x float> %vecins10585, <4 x float>* undef, align 16
+  %tmp1010 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10586 = extractelement <4 x float> %tmp1010, i32 1
+  %add10587 = fadd float %vecext10586, 0xC0694CCCC0000000
+  %tmp1011 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10588 = insertelement <4 x float> %tmp1011, float %add10587, i32 1
+  store <4 x float> %vecins10588, <4 x float>* undef, align 16
+  %tmp1012 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10589 = extractelement <4 x float> %tmp1012, i32 2
+  %add10590 = fadd float %vecext10589, 0xC0541999A0000000
+  %tmp1013 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10591 = insertelement <4 x float> %tmp1013, float %add10590, i32 2
+  store <4 x float> %vecins10591, <4 x float>* undef, align 16
+  %tmp1014 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10592 = extractelement <4 x float> %tmp1014, i32 3
+  %add10593 = fadd float %vecext10592, 0xC06C566660000000
+  %tmp1015 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10594 = insertelement <4 x float> %tmp1015, float %add10593, i32 3
+  store <4 x float> %vecins10594, <4 x float>* undef, align 16
+  store <4 x float> <float 0x407A3199A0000000, float 0xC0659999A0000000, float 0x407E0999A0000000, float 0xC0334CCCC0000000>, <4 x float>* %.compoundliteral10595
+  %tmp1016 = load <4 x float>, <4 x float>* %.compoundliteral10595
+  %tmp1017 = load <4 x float>, <4 x float>* undef, align 16
+  %add10596 = fadd <4 x float> %tmp1017, %tmp1016
+  store <4 x float> %add10596, <4 x float>* undef, align 16
+  %tmp1018 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10597 = extractelement <4 x float> %tmp1018, i32 0
+  %add10598 = fadd float %vecext10597, 0x40640999A0000000
+  %tmp1019 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10599 = insertelement <4 x float> %tmp1019, float %add10598, i32 0
+  store <4 x float> %vecins10599, <4 x float>* undef, align 16
+  %tmp1020 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10600 = extractelement <4 x float> %tmp1020, i32 1
+  %add10601 = fadd float %vecext10600, 0xC073966660000000
+  %tmp1021 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10602 = insertelement <4 x float> %tmp1021, float %add10601, i32 1
+  %tmp1022 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10603 = extractelement <4 x float> %tmp1022, i32 2
+  %add10604 = fadd float %vecext10603, 1.780000e+02
+  %tmp1023 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10605 = insertelement <4 x float> %tmp1023, float %add10604, i32 2
+  store <4 x float> %vecins10605, <4 x float>* undef, align 16
+  %tmp1024 = load <4 x float>, <4 x float>* undef, align 16
+  %add10607 = fadd float undef, 0x4070A33340000000
+  %tmp1025 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> <float 0x407C5999A0000000, float 0x4046733340000000, float 0xC06E6CCCC0000000, float 0xC063C33340000000>, <4 x float>* %.compoundliteral10609
+  %tmp1026 = load <4 x float>, <4 x float>* %.compoundliteral10609
+  %tmp1027 = load <4 x float>, <4 x float>* undef, align 16
+  %tmp1028 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10611 = extractelement <4 x float> %tmp1028, i32 0
+  %add10612 = fadd float %vecext10611, 0x40757199A0000000
+  %vecins10613 = insertelement <4 x float> undef, float %add10612, i32 0
+  store <4 x float> %vecins10613, <4 x float>* undef, align 16
+  %tmp1029 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10614 = extractelement <4 x float> %tmp1029, i32 1
+  %add10615 = fadd float %vecext10614, 0x40740CCCC0000000
+  %tmp1030 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10616 = insertelement <4 x float> %tmp1030, float %add10615, i32 1
+  store <4 x float> %vecins10616, <4 x float>* undef, align 16
+  %tmp1031 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10617 = extractelement <4 x float> %tmp1031, i32 2
+  %add10618 = fadd float %vecext10617, 0xC012CCCCC0000000
+  %tmp1032 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10619 = insertelement <4 x float> %tmp1032, float %add10618, i32 2
+  store <4 x float> %vecins10619, <4 x float>* undef, align 16
+  %tmp1033 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10620 = extractelement <4 x float> %tmp1033, i32 3
+  %add10621 = fadd float %vecext10620, 0x406E566660000000
+  %tmp1034 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> <float 0x407B2199A0000000, float 0xC07D9CCCC0000000, float -4.350000e+01, float 0xC07D3B3340000000>, <4 x float>* %.compoundliteral10623
+  %tmp1035 = load <4 x float>, <4 x float>* %.compoundliteral10623
+  %add10624 = fadd <4 x float> undef, %tmp1035
+  %tmp1036 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10625 = extractelement <4 x float> %tmp1036, i32 0
+  %tmp1037 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10627 = insertelement <4 x float> %tmp1037, float undef, i32 0
+  store <4 x float> %vecins10627, <4 x float>* undef, align 16
+  %tmp1038 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10628 = extractelement <4 x float> %tmp1038, i32 1
+  %add10629 = fadd float %vecext10628, 0x407E3CCCC0000000
+  %tmp1039 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10630 = insertelement <4 x float> %tmp1039, float %add10629, i32 1
+  store <4 x float> %vecins10630, <4 x float>* undef, align 16
+  %tmp1040 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10631 = extractelement <4 x float> %tmp1040, i32 2
+  %tmp1041 = load <4 x float>, <4 x float>* undef, align 16
+  %tmp1042 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10634 = extractelement <4 x float> %tmp1042, i32 3
+  %add10635 = fadd float %vecext10634, 0xC067533340000000
+  %tmp1043 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10636 = insertelement <4 x float> %tmp1043, float %add10635, i32 3
+  store <4 x float> %vecins10636, <4 x float>* undef, align 16
+  store <4 x float> <float 1.950000e+02, float 0x407E8E6660000000, float 0x407D7CCCC0000000, float 0x407E166660000000>, <4 x float>* %.compoundliteral10637
+  %tmp1044 = load <4 x float>, <4 x float>* undef, align 16
+  %add10638 = fadd <4 x float> %tmp1044, undef
+  %tmp1045 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10639 = extractelement <4 x float> %tmp1045, i32 0
+  %add10640 = fadd float %vecext10639, 0x406CA33340000000
+  %tmp1046 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10641 = insertelement <4 x float> %tmp1046, float %add10640, i32 0
+  store <4 x float> %vecins10641, <4 x float>* undef, align 16
+  %tmp1047 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10642 = extractelement <4 x float> %tmp1047, i32 1
+  %add10643 = fadd float %vecext10642, 0xC07C8999A0000000
+  %tmp1048 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10644 = insertelement <4 x float> %tmp1048, float %add10643, i32 1
+  store <4 x float> %vecins10644, <4 x float>* undef, align 16
+  %tmp1049 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10645 = extractelement <4 x float> %tmp1049, i32 2
+  %tmp1050 = load <4 x float>, <4 x float>* undef, align 16
+  %tmp1051 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10748 = insertelement <4 x float> undef, float undef, i32 3
+  %tmp1052 = load <4 x float>, <4 x float>* %.compoundliteral10749
+  %add10750 = fadd <4 x float> undef, %tmp1052
+  store <4 x float> %add10750, <4 x float>* undef, align 16
+  %tmp1053 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10751 = extractelement <4 x float> %tmp1053, i32 0
+  %add10752 = fadd float %vecext10751, 0x4071B33340000000
+  %tmp1054 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10753 = insertelement <4 x float> %tmp1054, float %add10752, i32 0
+  store <4 x float> %vecins10753, <4 x float>* undef, align 16
+  %tmp1055 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10754 = extractelement <4 x float> %tmp1055, i32 1
+  %add10755 = fadd float %vecext10754, 0xC076A66660000000
+  %tmp1056 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10756 = insertelement <4 x float> %tmp1056, float %add10755, i32 1
+  store <4 x float> %vecins10756, <4 x float>* undef, align 16
+  %tmp1057 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10757 = extractelement <4 x float> %tmp1057, i32 2
+  %add10758 = fadd float %vecext10757, 3.800000e+01
+  %tmp1058 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10759 = insertelement <4 x float> %tmp1058, float %add10758, i32 2
+  store <4 x float> %vecins10759, <4 x float>* undef, align 16
+  %tmp1059 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10760 = extractelement <4 x float> %tmp1059, i32 3
+  store <4 x float> undef, <4 x float>* undef, align 16
+  store <4 x float> <float 0xC075BB3340000000, float 0x4074D4CCC0000000, float 0xC07A466660000000, float 0xC0691CCCC0000000>, <4 x float>* %.compoundliteral10763
+  %tmp1060 = load <4 x float>, <4 x float>* %.compoundliteral10763
+  %tmp1061 = load <4 x float>, <4 x float>* undef, align 16
+  %tmp1062 = load <4 x float>, <4 x float>* undef, align 16
+  %add10985 = fadd float undef, 0x405E933340000000
+  %tmp1063 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10986 = insertelement <4 x float> %tmp1063, float %add10985, i32 3
+  store <4 x float> %vecins10986, <4 x float>* undef, align 16
+  store <4 x float> <float 0xC0721E6660000000, float -4.180000e+02, float 0x406F366660000000, float 0xC055F999A0000000>, <4 x float>* %.compoundliteral10987
+  %tmp1064 = load <4 x float>, <4 x float>* %.compoundliteral10987
+  %tmp1065 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10994 = insertelement <4 x float> %tmp1065, float undef, i32 1
+  %tmp1066 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10995 = extractelement <4 x float> %tmp1066, i32 2
+  %add10996 = fadd float %vecext10995, 0x406F9999A0000000
+  %tmp1067 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins10997 = insertelement <4 x float> %tmp1067, float %add10996, i32 2
+  store <4 x float> %vecins10997, <4 x float>* undef, align 16
+  %tmp1068 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext10998 = extractelement <4 x float> %tmp1068, i32 3
+  %add10999 = fadd float %vecext10998, -2.765000e+02
+  %tmp1069 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11000 = insertelement <4 x float> %tmp1069, float %add10999, i32 3
+  store <4 x float> %vecins11000, <4 x float>* undef, align 16
+  store <4 x float> <float 0x4078F999A0000000, float 0xC06D166660000000, float 0x40501999A0000000, float 0x406FC999A0000000>, <4 x float>* %.compoundliteral11001
+  %tmp1070 = load <4 x float>, <4 x float>* undef, align 16
+  %add11002 = fadd <4 x float> %tmp1070, undef
+  %vecext11003 = extractelement <4 x float> undef, i32 0
+  %vecext11009 = extractelement <4 x float> undef, i32 2
+  %tmp1071 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11033 = insertelement <4 x float> %tmp1071, float undef, i32 0
+  store <4 x float> %vecins11033, <4 x float>* undef, align 16
+  %tmp1072 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11034 = extractelement <4 x float> %tmp1072, i32 1
+  %add11035 = fadd float %vecext11034, 0x4056D33340000000
+  %tmp1073 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11036 = insertelement <4 x float> %tmp1073, float %add11035, i32 1
+  store <4 x float> %vecins11036, <4 x float>* undef, align 16
+  %tmp1074 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11037 = extractelement <4 x float> %tmp1074, i32 2
+  %add11038 = fadd float %vecext11037, 0xC06EA33340000000
+  %tmp1075 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %tmp1076 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11040 = extractelement <4 x float> %tmp1076, i32 3
+  %add11041 = fadd float %vecext11040, 0x40746CCCC0000000
+  %tmp1077 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11042 = insertelement <4 x float> %tmp1077, float %add11041, i32 3
+  store <4 x float> <float 0x405DD999A0000000, float -3.775000e+02, float -1.265000e+02, float 0xC065C66660000000>, <4 x float>* undef
+  %tmp1078 = load <4 x float>, <4 x float>* undef, align 16
+  %add11044 = fadd <4 x float> %tmp1078, undef
+  store <4 x float> %add11044, <4 x float>* undef, align 16
+  %tmp1079 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11045 = extractelement <4 x float> %tmp1079, i32 0
+  %add11046 = fadd float %vecext11045, 0xC076E66660000000
+  %tmp1080 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11047 = insertelement <4 x float> %tmp1080, float %add11046, i32 0
+  %tmp1081 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11048 = extractelement <4 x float> %tmp1081, i32 1
+  %add11049 = fadd float %vecext11048, 4.100000e+02
+  %vecins11064 = insertelement <4 x float> undef, float undef, i32 1
+  %add11074 = fadd float undef, 0xC06FF999A0000000
+  %tmp1082 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11075 = insertelement <4 x float> %tmp1082, float %add11074, i32 0
+  store <4 x float> %vecins11075, <4 x float>* undef, align 16
+  %add11077 = fadd float undef, 0xC075D33340000000
+  %tmp1083 = load <4 x float>, <4 x float>* undef, align 16
+  %tmp1084 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %tmp1085 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11093 = extractelement <4 x float> %tmp1085, i32 2
+  %add11094 = fadd float %vecext11093, 0xC07CD66660000000
+  %tmp1086 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11095 = insertelement <4 x float> %tmp1086, float %add11094, i32 2
+  store <4 x float> %vecins11095, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  store <4 x float> <float 0x4061F66660000000, float 0xC076DB3340000000, float 0xC055A66660000000, float 2.415000e+02>, <4 x float>* undef
+  %tmp1087 = load <4 x float>, <4 x float>* undef
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %tmp1088 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11513 = extractelement <4 x float> %tmp1088, i32 2
+  %add11514 = fadd float %vecext11513, 0xC07C7199A0000000
+  %vecins11515 = insertelement <4 x float> undef, float %add11514, i32 2
+  store <4 x float> %vecins11515, <4 x float>* undef, align 16
+  %add11520 = fadd <4 x float> undef, undef
+  store <4 x float> %add11520, <4 x float>* undef, align 16
+  %vecext11521 = extractelement <4 x float> undef, i32 0
+  %add11522 = fadd float %vecext11521, 0x4041733340000000
+  %tmp1089 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %tmp1090 = load <4 x float>, <4 x float>* undef
+  %tmp1091 = load <4 x float>, <4 x float>* undef, align 16
+  %add11562 = fadd <4 x float> %tmp1091, %tmp1090
+  %tmp1092 = load <4 x float>, <4 x float>* undef, align 16
+  %add11564 = fadd float undef, 0xC0411999A0000000
+  %tmp1093 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11565 = insertelement <4 x float> %tmp1093, float %add11564, i32 0
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %vecext11586 = extractelement <4 x float> undef, i32 3
+  %add11587 = fadd float %vecext11586, 3.760000e+02
+  %tmp1094 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  store <4 x float> <float 0xC06ED999A0000000, float 1.380000e+02, float 0xC073AB3340000000, float 0x4078A66660000000>, <4 x float>* undef
+  %tmp1095 = load <4 x float>, <4 x float>* undef
+  %tmp1096 = load <4 x float>, <4 x float>* undef, align 16
+  %tmp1097 = load <4 x float>, <4 x float>* undef, align 16
+  %tmp1098 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11593 = insertelement <4 x float> %tmp1098, float undef, i32 0
+  %vecext11594 = extractelement <4 x float> undef, i32 1
+  %tmp1099 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11596 = insertelement <4 x float> %tmp1099, float undef, i32 1
+  store <4 x float> %vecins11596, <4 x float>* undef, align 16
+  %tmp1100 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11597 = extractelement <4 x float> %tmp1100, i32 2
+  %add11598 = fadd float %vecext11597, 0x40430CCCC0000000
+  %tmp1101 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11599 = insertelement <4 x float> %tmp1101, float %add11598, i32 2
+  %tmp1102 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11600 = extractelement <4 x float> %tmp1102, i32 3
+  %tmp1103 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11602 = insertelement <4 x float> %tmp1103, float undef, i32 3
+  store <4 x float> %vecins11602, <4 x float>* undef, align 16
+  %tmp1104 = load <4 x float>, <4 x float>* undef
+  %tmp1105 = load <4 x float>, <4 x float>* undef, align 16
+  %add11604 = fadd <4 x float> %tmp1105, %tmp1104
+  %tmp1106 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11605 = extractelement <4 x float> %tmp1106, i32 0
+  %tmp1107 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11607 = insertelement <4 x float> %tmp1107, float undef, i32 0
+  %vecins11621 = insertelement <4 x float> undef, float undef, i32 0
+  %vecins11630 = insertelement <4 x float> undef, float undef, i32 3
+  store <4 x float> %vecins11630, <4 x float>* undef, align 16
+  store <4 x float> <float -1.190000e+02, float 0x402F666660000000, float 0xC07BD33340000000, float -1.595000e+02>, <4 x float>* %.compoundliteral11631
+  %tmp1108 = load <4 x float>, <4 x float>* %.compoundliteral11631
+  %tmp1109 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %add11634 = fadd float undef, -1.075000e+02
+  %vecext11647 = extractelement <4 x float> undef, i32 0
+  %add11648 = fadd float %vecext11647, 0x40775999A0000000
+  %tmp1110 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11650 = extractelement <4 x float> undef, i32 1
+  %tmp1111 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11784 = insertelement <4 x float> %tmp1111, float undef, i32 3
+  store <4 x float> %vecins11784, <4 x float>* undef, align 16
+  store <4 x float> <float 1.605000e+02, float 0x4068366660000000, float 2.820000e+02, float 0x407CF66660000000>, <4 x float>* %.compoundliteral11785
+  %tmp1112 = load <4 x float>, <4 x float>* %.compoundliteral11785
+  %add11786 = fadd <4 x float> undef, %tmp1112
+  store <4 x float> %add11786, <4 x float>* undef, align 16
+  %tmp1113 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11787 = extractelement <4 x float> %tmp1113, i32 0
+  %vecext11807 = extractelement <4 x float> undef, i32 2
+  %add11808 = fadd float %vecext11807, 4.535000e+02
+  %tmp1114 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11810 = extractelement <4 x float> undef, i32 3
+  %add11811 = fadd float %vecext11810, 0x4068F66660000000
+  %tmp1115 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11812 = insertelement <4 x float> %tmp1115, float %add11811, i32 3
+  store <4 x float> %vecins11812, <4 x float>* undef, align 16
+  %tmp1116 = load <4 x float>, <4 x float>* undef
+  %tmp1117 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11958 = extractelement <4 x float> undef, i32 1
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %vecext11961 = extractelement <4 x float> undef, i32 2
+  %add11962 = fadd float %vecext11961, -3.680000e+02
+  %tmp1118 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %add11965 = fadd float undef, 0x4061133340000000
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %tmp1119 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11975 = extractelement <4 x float> %tmp1119, i32 2
+  %tmp1120 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11977 = insertelement <4 x float> %tmp1120, float undef, i32 2
+  store <4 x float> %vecins11977, <4 x float>* undef, align 16
+  %vecext11978 = extractelement <4 x float> undef, i32 3
+  %add11979 = fadd float %vecext11978, 0xC0688999A0000000
+  %tmp1121 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins11980 = insertelement <4 x float> %tmp1121, float %add11979, i32 3
+  store <4 x float> %vecins11980, <4 x float>* undef, align 16
+  %add11982 = fadd <4 x float> undef, undef
+  store <4 x float> %add11982, <4 x float>* undef, align 16
+  %tmp1122 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext11983 = extractelement <4 x float> %tmp1122, i32 0
+  %add11984 = fadd float %vecext11983, 0xC075966660000000
+  %tmp1123 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12005 = insertelement <4 x float> undef, float undef, i32 2
+  store <4 x float> %vecins12005, <4 x float>* undef, align 16
+  %tmp1124 = load <4 x float>, <4 x float>* undef, align 16
+  %add12007 = fadd float undef, 0xC07124CCC0000000
+  %vecins12008 = insertelement <4 x float> undef, float %add12007, i32 3
+  store <4 x float> %vecins12008, <4 x float>* undef, align 16
+  %tmp1125 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %tmp1126 = load <4 x float>, <4 x float>* undef, align 16
+  %add12012 = fadd float undef, 0xC0750CCCC0000000
+  %tmp1127 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12013 = insertelement <4 x float> %tmp1127, float %add12012, i32 0
+  store <4 x float> %vecins12013, <4 x float>* undef, align 16
+  %tmp1128 = load <4 x float>, <4 x float>* undef, align 16
+  %add12015 = fadd float undef, 0x4079CE6660000000
+  %tmp1129 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12016 = insertelement <4 x float> %tmp1129, float %add12015, i32 1
+  store <4 x float> %vecins12016, <4 x float>* undef, align 16
+  %add12018 = fadd float undef, 3.555000e+02
+  %tmp1130 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12019 = insertelement <4 x float> %tmp1130, float %add12018, i32 2
+  %tmp1131 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext12020 = extractelement <4 x float> %tmp1131, i32 3
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %vecext12028 = extractelement <4 x float> undef, i32 1
+  store <4 x float> undef, <4 x float>* undef, align 16
+  store <4 x float> <float 0x40791999A0000000, float 0x407C7CCCC0000000, float 0x4070F33340000000, float 0xC056ECCCC0000000>, <4 x float>* undef
+  %tmp1132 = load <4 x float>, <4 x float>* undef, align 16
+  %add12038 = fadd <4 x float> %tmp1132, undef
+  %tmp1133 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext12042 = extractelement <4 x float> %tmp1133, i32 1
+  %add12043 = fadd float %vecext12042, 0x402F9999A0000000
+  %tmp1134 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12044 = insertelement <4 x float> %tmp1134, float %add12043, i32 1
+  store <4 x float> %vecins12044, <4 x float>* undef, align 16
+  %vecext12045 = extractelement <4 x float> undef, i32 2
+  %add12046 = fadd float %vecext12045, 0xC07EF33340000000
+  %tmp1135 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12047 = insertelement <4 x float> %tmp1135, float %add12046, i32 2
+  store <4 x float> %vecins12047, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %tmp1136 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext12112 = extractelement <4 x float> %tmp1136, i32 1
+  %tmp1137 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %add12116 = fadd float undef, 0xC074F4CCC0000000
+  %tmp1138 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12117 = insertelement <4 x float> %tmp1138, float %add12116, i32 2
+  store <4 x float> %vecins12117, <4 x float>* undef, align 16
+  %tmp1139 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext12118 = extractelement <4 x float> %tmp1139, i32 3
+  %add12119 = fadd float %vecext12118, 0xC0638CCCC0000000
+  %tmp1140 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12120 = insertelement <4 x float> %tmp1140, float %add12119, i32 3
+  %add12152 = fadd float undef, 0x4039333340000000
+  %tmp1141 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12153 = insertelement <4 x float> %tmp1141, float %add12152, i32 0
+  %vecext12154 = extractelement <4 x float> undef, i32 1
+  %add12155 = fadd float %vecext12154, 0xC07BBB3340000000
+  %tmp1142 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12156 = insertelement <4 x float> %tmp1142, float %add12155, i32 1
+  %tmp1143 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext12157 = extractelement <4 x float> %tmp1143, i32 2
+  %add12158 = fadd float %vecext12157, 0xC0428CCCC0000000
+  %tmp1144 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12159 = insertelement <4 x float> %tmp1144, float %add12158, i32 2
+  %tmp1145 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext12160 = extractelement <4 x float> %tmp1145, i32 3
+  %add12161 = fadd float %vecext12160, 0x407B1999A0000000
+  %tmp1146 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12162 = insertelement <4 x float> %tmp1146, float %add12161, i32 3
+  store <4 x float> %vecins12162, <4 x float>* undef, align 16
+  %tmp1147 = load <4 x float>, <4 x float>* undef
+  %tmp1148 = load <4 x float>, <4 x float>* undef, align 16
+  %tmp1149 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext12182 = extractelement <4 x float> %tmp1149, i32 1
+  %tmp1150 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  store <4 x float> <float 0x4061833340000000, float 0x405CA66660000000, float -1.275000e+02, float 0x405BC66660000000>, <4 x float>* undef
+  %add12208 = fadd float undef, 0x407854CCC0000000
+  %tmp1151 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %tmp1152 = load <4 x float>, <4 x float>* undef, align 16
+  %tmp1153 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12218 = insertelement <4 x float> undef, float undef, i32 3
+  store <4 x float> %vecins12218, <4 x float>* undef, align 16
+  store <4 x float> <float 0x407C3CCCC0000000, float 0xC057C66660000000, float 2.605000e+02, float 0xC07974CCC0000000>, <4 x float>* undef
+  %tmp1154 = load <4 x float>, <4 x float>* undef
+  %tmp1155 = load <4 x float>, <4 x float>* undef, align 16
+  %add12220 = fadd <4 x float> %tmp1155, %tmp1154
+  %tmp1156 = load <4 x float>, <4 x float>* undef, align 16
+  %tmp1157 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12223 = insertelement <4 x float> %tmp1157, float undef, i32 0
+  store <4 x float> %vecins12223, <4 x float>* undef, align 16
+  %tmp1158 = load <4 x float>, <4 x float>* undef, align 16
+  %add12242 = fadd float undef, 0x4067E33340000000
+  %tmp1159 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12243 = insertelement <4 x float> %tmp1159, float %add12242, i32 2
+  store <4 x float> %vecins12243, <4 x float>* undef, align 16
+  %tmp1160 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext12244 = extractelement <4 x float> %tmp1160, i32 3
+  %add12245 = fadd float %vecext12244, 0x4071AE6660000000
+  %tmp1161 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12246 = insertelement <4 x float> %tmp1161, float %add12245, i32 3
+  store <4 x float> %vecins12246, <4 x float>* undef, align 16
+  store <4 x float> <float -4.880000e+02, float 0xC079966660000000, float -8.450000e+01, float 0xC0464CCCC0000000>, <4 x float>* %.compoundliteral12247
+  %tmp1162 = load <4 x float>, <4 x float>* %.compoundliteral12247
+  %tmp1163 = load <4 x float>, <4 x float>* undef, align 16
+  %add12248 = fadd <4 x float> %tmp1163, %tmp1162
+  store <4 x float> %add12248, <4 x float>* undef, align 16
+  %tmp1164 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext12249 = extractelement <4 x float> %tmp1164, i32 0
+  %add12250 = fadd float %vecext12249, 1.075000e+02
+  %tmp1165 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %tmp1166 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext12252 = extractelement <4 x float> %tmp1166, i32 1
+  %add12253 = fadd float %vecext12252, 0xC0662CCCC0000000
+  %tmp1167 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins12254 = insertelement <4 x float> %tmp1167, float %add12253, i32 1
+  store <4 x float> %vecins12254, <4 x float>* undef, align 16
+  %tmp1168 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext12255 = extractelement <4 x float> %tmp1168, i32 2
+  %add12256 = fadd float %vecext12255, 0x40554CCCC0000000
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %add13141 = fadd float undef, 0x40768999A0000000
+  %tmp1169 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13142 = insertelement <4 x float> %tmp1169, float %add13141, i32 3
+  store <4 x float> %vecins13142, <4 x float>* undef, align 16
+  %tmp1170 = load <4 x float>, <4 x float>* undef
+  %add13144 = fadd <4 x float> undef, %tmp1170
+  store <4 x float> %add13144, <4 x float>* undef, align 16
+  %tmp1171 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13145 = extractelement <4 x float> %tmp1171, i32 0
+  %add13146 = fadd float %vecext13145, 3.975000e+02
+  %tmp1172 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13378 = extractelement <4 x float> %tmp1172, i32 3
+  %add13379 = fadd float %vecext13378, 0xC053B33340000000
+  %tmp1173 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13380 = insertelement <4 x float> %tmp1173, float %add13379, i32 3
+  store <4 x float> %vecins13380, <4 x float>* undef, align 16
+  %tmp1174 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13408 = insertelement <4 x float> %tmp1174, float undef, i32 3
+  store <4 x float> %vecins13408, <4 x float>* undef, align 16
+  store <4 x float> <float 0xC0455999A0000000, float 0xC07D366660000000, float 4.240000e+02, float -1.670000e+02>, <4 x float>* undef
+  %tmp1175 = load <4 x float>, <4 x float>* undef
+  %tmp1176 = load <4 x float>, <4 x float>* undef, align 16
+  %add13410 = fadd <4 x float> %tmp1176, %tmp1175
+  store <4 x float> %add13410, <4 x float>* undef, align 16
+  %tmp1177 = load <4 x float>, <4 x float>* undef, align 16
+  %add13412 = fadd float undef, 0xC0708999A0000000
+  %tmp1178 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13413 = insertelement <4 x float> %tmp1178, float %add13412, i32 0
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %vecext13428 = extractelement <4 x float> undef, i32 1
+  %add13429 = fadd float %vecext13428, 0xC063BCCCC0000000
+  %tmp1179 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13430 = insertelement <4 x float> %tmp1179, float %add13429, i32 1
+  store <4 x float> %vecins13430, <4 x float>* undef, align 16
+  %tmp1180 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13431 = extractelement <4 x float> %tmp1180, i32 2
+  %vecins13433 = insertelement <4 x float> undef, float undef, i32 2
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %add13449 = fadd float undef, 4.590000e+02
+  %tmp1181 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13450 = insertelement <4 x float> %tmp1181, float %add13449, i32 3
+  store <4 x float> %vecins13450, <4 x float>* undef, align 16
+  store <4 x float> <float 0xC073A66660000000, float 0xC041B33340000000, float 0x4066233340000000, float 0x4071C33340000000>, <4 x float>* undef
+  %tmp1182 = load <4 x float>, <4 x float>* undef
+  %tmp1183 = load <4 x float>, <4 x float>* undef, align 16
+  %add13452 = fadd <4 x float> %tmp1183, %tmp1182
+  store <4 x float> %add13452, <4 x float>* undef, align 16
+  %tmp1184 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13453 = extractelement <4 x float> %tmp1184, i32 0
+  %add13454 = fadd float %vecext13453, 0xC072866660000000
+  %tmp1185 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13455 = insertelement <4 x float> %tmp1185, float %add13454, i32 0
+  %add13471 = fadd float undef, 0xC0556CCCC0000000
+  %tmp1186 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13472 = insertelement <4 x float> %tmp1186, float %add13471, i32 1
+  store <4 x float> %vecins13472, <4 x float>* undef, align 16
+  %tmp1187 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13473 = extractelement <4 x float> %tmp1187, i32 2
+  %add13474 = fadd float %vecext13473, 0xC0786999A0000000
+  %tmp1188 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13475 = insertelement <4 x float> %tmp1188, float %add13474, i32 2
+  store <4 x float> %vecins13475, <4 x float>* undef, align 16
+  %add13477 = fadd float undef, 0xC07C3E6660000000
+  %tmp1189 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13478 = insertelement <4 x float> %tmp1189, float %add13477, i32 3
+  store <4 x float> %vecins13478, <4 x float>* undef, align 16
+  store <4 x float> <float -4.740000e+02, float 0x4023CCCCC0000000, float 0xC05C266660000000, float 0x407B7199A0000000>, <4 x float>* undef
+  %tmp1190 = load <4 x float>, <4 x float>* undef, align 16
+  %add13480 = fadd <4 x float> %tmp1190, undef
+  store <4 x float> %add13480, <4 x float>* undef, align 16
+  %tmp1191 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13481 = extractelement <4 x float> %tmp1191, i32 0
+  %add13482 = fadd float %vecext13481, 0xC07BA4CCC0000000
+  %tmp1192 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13483 = insertelement <4 x float> %tmp1192, float %add13482, i32 0
+  store <4 x float> %vecins13483, <4 x float>* undef, align 16
+  %tmp1193 = load <4 x float>, <4 x float>* undef, align 16
+  %add13485 = fadd float undef, 0x406B1999A0000000
+  %tmp1194 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13486 = insertelement <4 x float> %tmp1194, float %add13485, i32 1
+  store <4 x float> %vecins13486, <4 x float>* undef, align 16
+  %tmp1195 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13487 = extractelement <4 x float> %tmp1195, i32 2
+  %add13488 = fadd float %vecext13487, 0x40647999A0000000
+  %tmp1196 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13489 = insertelement <4 x float> %tmp1196, float %add13488, i32 2
+  store <4 x float> %vecins13489, <4 x float>* undef, align 16
+  %tmp1197 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13490 = extractelement <4 x float> %tmp1197, i32 3
+  %tmp1198 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13492 = insertelement <4 x float> %tmp1198, float undef, i32 3
+  store <4 x float> %vecins13492, <4 x float>* undef, align 16
+  %tmp1199 = load <4 x float>, <4 x float>* %.compoundliteral13493
+  %tmp1200 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %vecins13548 = insertelement <4 x float> undef, float undef, i32 3
+  store <4 x float> <float 4.540000e+02, float 3.760000e+02, float 0x406EA33340000000, float 0x405AACCCC0000000>, <4 x float>* %.compoundliteral13549
+  %tmp1201 = load <4 x float>, <4 x float>* undef, align 16
+  %add13552 = fadd float undef, 3.230000e+02
+  %tmp1202 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13553 = insertelement <4 x float> %tmp1202, float %add13552, i32 0
+  %tmp1203 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13554 = extractelement <4 x float> %tmp1203, i32 1
+  %tmp1204 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13556 = insertelement <4 x float> %tmp1204, float undef, i32 1
+  store <4 x float> %vecins13556, <4 x float>* undef, align 16
+  %tmp1205 = load <4 x float>, <4 x float>* undef, align 16
+  %add13558 = fadd float undef, 2.625000e+02
+  %tmp1206 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13559 = insertelement <4 x float> %tmp1206, float %add13558, i32 2
+  store <4 x float> %vecins13559, <4 x float>* undef, align 16
+  %add13575 = fadd float undef, -4.725000e+02
+  %tmp1207 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13576 = insertelement <4 x float> %tmp1207, float %add13575, i32 3
+  store <4 x float> %vecins13576, <4 x float>* undef, align 16
+  store <4 x float> <float 0x40334CCCC0000000, float 0xC0785CCCC0000000, float 0xC078D66660000000, float 3.745000e+02>, <4 x float>* undef
+  %tmp1208 = load <4 x float>, <4 x float>* undef
+  %tmp1209 = load <4 x float>, <4 x float>* undef, align 16
+  %add13578 = fadd <4 x float> %tmp1209, %tmp1208
+  store <4 x float> %add13578, <4 x float>* undef, align 16
+  %tmp1210 = load <4 x float>, <4 x float>* undef, align 16
+  %tmp1211 = load <4 x float>, <4 x float>* undef, align 16
+  %add13592 = fadd <4 x float> %tmp1211, undef
+  store <4 x float> %add13592, <4 x float>* undef, align 16
+  %tmp1212 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13593 = extractelement <4 x float> %tmp1212, i32 0
+  %add13594 = fadd float %vecext13593, 0xC0708B3340000000
+  %tmp1213 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %tmp1214 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13596 = extractelement <4 x float> %tmp1214, i32 1
+  %add13597 = fadd float %vecext13596, 0x40660999A0000000
+  %vecins13604 = insertelement <4 x float> undef, float undef, i32 3
+  store <4 x float> %vecins13604, <4 x float>* undef, align 16
+  store <4 x float> <float 0x407B4999A0000000, float 0xC067F66660000000, float 0xC068F999A0000000, float 0xC079233340000000>, <4 x float>* undef
+  %tmp1215 = load <4 x float>, <4 x float>* undef, align 16
+  %add13606 = fadd <4 x float> %tmp1215, undef
+  %tmp1216 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13607 = extractelement <4 x float> %tmp1216, i32 0
+  %vecins13609 = insertelement <4 x float> undef, float undef, i32 0
+  %tmp1217 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %tmp1218 = load <4 x float>, <4 x float>* undef, align 16
+  %add13622 = fadd float undef, -3.390000e+02
+  %vecins13623 = insertelement <4 x float> undef, float %add13622, i32 0
+  store <4 x float> %vecins13623, <4 x float>* undef, align 16
+  %tmp1219 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13624 = extractelement <4 x float> %tmp1219, i32 1
+  %add13625 = fadd float %vecext13624, 0x405C3999A0000000
+  %vecext13627 = extractelement <4 x float> undef, i32 2
+  %add13628 = fadd float %vecext13627, 0xC067033340000000
+  %tmp1220 = load <4 x float>, <4 x float>* undef, align 16
+  %tmp1221 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13630 = extractelement <4 x float> %tmp1221, i32 3
+  %add13631 = fadd float %vecext13630, 0xC060333340000000
+  %tmp1222 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13632 = insertelement <4 x float> %tmp1222, float %add13631, i32 3
+  store <4 x float> %vecins13632, <4 x float>* undef, align 16
+  store <4 x float> <float 0x4078D66660000000, float 0x4048B33340000000, float 0x4051466660000000, float -2.965000e+02>, <4 x float>* undef
+  %tmp1223 = load <4 x float>, <4 x float>* undef
+  %tmp1224 = load <4 x float>, <4 x float>* undef, align 16
+  %add13634 = fadd <4 x float> %tmp1224, %tmp1223
+  store <4 x float> %add13634, <4 x float>* undef, align 16
+  %vecext13635 = extractelement <4 x float> undef, i32 0
+  %add13636 = fadd float %vecext13635, 0x406A5999A0000000
+  %tmp1225 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13637 = insertelement <4 x float> %tmp1225, float %add13636, i32 0
+  store <4 x float> %vecins13637, <4 x float>* undef, align 16
+  %tmp1226 = load <4 x float>, <4 x float>* undef, align 16
+  %tmp1227 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13643 = insertelement <4 x float> %tmp1227, float undef, i32 2
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %tmp1228 = load <4 x float>, <4 x float>* undef, align 16
+  %add13785 = fadd float undef, 0x4068866660000000
+  %tmp1229 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13786 = insertelement <4 x float> %tmp1229, float %add13785, i32 3
+  store <4 x float> %vecins13786, <4 x float>* undef, align 16
+  store <4 x float> <float 0x407704CCC0000000, float 0x4047B33340000000, float 0x40797B3340000000, float 0xC0652CCCC0000000>, <4 x float>* %.compoundliteral13787
+  %tmp1230 = load <4 x float>, <4 x float>* undef, align 16
+  %add13788 = fadd <4 x float> %tmp1230, undef
+  %tmp1231 = load <4 x float>, <4 x float>* undef
+  %tmp1232 = load <4 x float>, <4 x float>* undef, align 16
+  %add13802 = fadd <4 x float> %tmp1232, %tmp1231
+  store <4 x float> %add13802, <4 x float>* undef, align 16
+  %tmp1233 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13803 = extractelement <4 x float> %tmp1233, i32 0
+  %add13804 = fadd float %vecext13803, -2.900000e+01
+  %tmp1234 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13805 = insertelement <4 x float> %tmp1234, float %add13804, i32 0
+  store <4 x float> %vecins13805, <4 x float>* undef, align 16
+  %tmp1235 = load <4 x float>, <4 x float>* undef, align 16
+  %add13807 = fadd float undef, 6.400000e+01
+  %tmp1236 = load <4 x float>, <4 x float>* undef, align 16
+  %tmp1237 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13809 = extractelement <4 x float> %tmp1237, i32 2
+  %tmp1238 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13812 = extractelement <4 x float> %tmp1238, i32 3
+  %add13813 = fadd float %vecext13812, -3.615000e+02
+  %vecins13814 = insertelement <4 x float> undef, float %add13813, i32 3
+  store <4 x float> %vecins13814, <4 x float>* undef, align 16
+  store <4 x float> <float -2.270000e+02, float -1.500000e+01, float 0x407084CCC0000000, float -1.425000e+02>, <4 x float>* undef
+  %tmp1239 = load <4 x float>, <4 x float>* undef
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %tmp1240 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13817 = extractelement <4 x float> %tmp1240, i32 0
+  %vecins13856 = insertelement <4 x float> undef, float undef, i32 3
+  store <4 x float> %vecins13856, <4 x float>* undef, align 16
+  store <4 x float> <float 0x40656CCCC0000000, float 0xC0656999A0000000, float 0x40778E6660000000, float 0x407ECE6660000000>, <4 x float>* undef
+  %tmp1241 = load <4 x float>, <4 x float>* undef
+  %tmp1242 = load <4 x float>, <4 x float>* undef, align 16
+  store <4 x float> undef, <4 x float>* undef, align 16
+  %tmp1243 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13859 = extractelement <4 x float> %tmp1243, i32 0
+  %tmp1244 = load <4 x float>, <4 x float>* undef, align 16
+  %vecins13861 = insertelement <4 x float> %tmp1244, float undef, i32 0
+  %tmp1245 = load <4 x float>, <4 x float>* undef, align 16
+  %vecext13862 = extractelement <4 x float> %tmp1245, i32 1
+  %add13863 = fadd float %vecext13862, -1.380000e+02
+  %vecins13864 = insertelement <4 x float> undef, float %add13863, i32 1
+  %vecins13867 = insertelement <4 x float> undef, float undef, i32 2
+  store <4 x float> %vecins13867, <4 x float>* undef, align 16
+  %tmp1246 = load <4 x float>, <4 x float>* undef, align 16
+  %tmp1247 = load <4 x float>, <4 x float>* undef, align 16
+  ret <4 x float> undef
+}
+
+declare i32 @printf(i8*, ...)
diff --git a/test/CodeGen/ARM/thumb1-varalloc.ll b/test/CodeGen/ARM/thumb1-varalloc.ll
index 8d5888d38f97..0637be03d565 100644
--- a/test/CodeGen/ARM/thumb1-varalloc.ll
+++ b/test/CodeGen/ARM/thumb1-varalloc.ll
@@ -12,7 +12,7 @@ entry:
 ; CHECK-LABEL: foo:
 
 	%size = alloca i32, align 4
-	%0 = load i8** @__bar, align 4
+	%0 = load i8*, i8** @__bar, align 4
 	%1 = icmp eq i8* %0, null
 	br i1 %1, label %bb1, label %bb3
 ; CHECK: bne
@@ -22,7 +22,7 @@ bb1:
 	%2 = alloca [1026 x i8], align 1
 ; CHECK: mov     [[R0:r[0-9]+]], sp
 ; CHECK: adds    {{r[0-9]+}}, [[R0]], {{r[0-9]+}}
-	%3 = getelementptr inbounds [1026 x i8]* %2, i32 0, i32 0
+	%3 = getelementptr inbounds [1026 x i8], [1026 x i8]* %2, i32 0, i32 0
 	%4 = call i32 @_called_func(i8* %3, i32* %size) nounwind
 	%5 = icmp eq i32 %4, 0
 	br i1 %5, label %bb2, label %bb3
@@ -43,26 +43,6 @@ bb3:
 declare noalias i8* @strdup(i8* nocapture) nounwind
 declare i32 @_called_func(i8*, i32*) nounwind
 
-; Variable ending up at unaligned offset from sp (i.e. not a multiple of 4)
-define void @test_local_var_addr() {
-; CHECK-LABEL: test_local_var_addr:
-
-  %addr1 = alloca i8
-  %addr2 = alloca i8
-
-; CHECK: mov r0, sp
-; CHECK: adds r0, #{{[0-9]+}}
-; CHECK: blx
-  call void @take_ptr(i8* %addr1)
-
-; CHECK: mov r0, sp
-; CHECK: adds r0, #{{[0-9]+}}
-; CHECK: blx
-  call void @take_ptr(i8* %addr2)
-
-  ret void
-}
-
 ; Simple variable ending up *at* sp.
 define void @test_simple_var() {
 ; CHECK-LABEL: test_simple_var:
@@ -126,14 +106,16 @@ define void @test_local_var_offset_1020() {
   ret void
 }
 
-; Max range addressable with tADDrSPi + tADDi8
-define void @test_local_var_offset_1275() {
-; CHECK-LABEL: test_local_var_offset_1275
+; Max range addressable with tADDrSPi + tADDi8 is 1275, however the automatic
+; 4-byte aligning of objects on the stack combined with 8-byte stack alignment
+; means that 1268 is the max offset we can use.
+define void @test_local_var_offset_1268() {
+; CHECK-LABEL: test_local_var_offset_1268
   %addr1 = alloca i8, i32 1
-  %addr2 = alloca i8, i32 1275
+  %addr2 = alloca i8, i32 1268
 
 ; CHECK: add r0, sp, #1020
-; CHECK: adds r0, #255
+; CHECK: adds r0, #248
 ; CHECK-NEXT: blx
   call void @take_ptr(i8* %addr1)
 
diff --git a/test/CodeGen/ARM/thumb1_return_sequence.ll b/test/CodeGen/ARM/thumb1_return_sequence.ll
index 318e6e402370..9c62faeaa684 100644
--- a/test/CodeGen/ARM/thumb1_return_sequence.ll
+++ b/test/CodeGen/ARM/thumb1_return_sequence.ll
@@ -3,7 +3,7 @@
 
 ; CHECK-V4T-LABEL: clobberframe
 ; CHECK-V5T-LABEL: clobberframe
-define <4 x i32> @clobberframe() #0 {
+define <4 x i32> @clobberframe(<6 x i32>* %p) #0 {
 entry:
 ; Prologue
 ; --------
@@ -11,11 +11,12 @@ entry:
 ; CHECK-V4T:    sub sp,
 ; CHECK-V5T:    push {[[SAVED:(r[4567](, )?)+]], lr}
 
-  %b = alloca <4 x i32>, align 16
+  %b = alloca <6 x i32>, align 16
   %a = alloca <4 x i32>, align 16
-  store <4 x i32> <i32 42, i32 42, i32 42, i32 42>, <4 x i32>* %b, align 16
+  %stuff = load <6 x i32>, <6 x i32>* %p, align 16
+  store <6 x i32> %stuff, <6 x i32>* %b, align 16
   store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16
-  %0 = load <4 x i32>* %a, align 16
+  %0 = load <4 x i32>, <4 x i32>* %a, align 16
   ret <4 x i32> %0
 
 ; Epilogue
@@ -45,7 +46,7 @@ entry:
   %a = alloca <4 x i32>, align 16
   store <4 x i32> <i32 42, i32 42, i32 42, i32 42>, <4 x i32>* %b, align 16
   store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16
-  %0 = load <4 x i32>* %a, align 16
+  %0 = load <4 x i32>, <4 x i32>* %a, align 16
   call void @llvm.va_start(i8* null)
   ret <4 x i32> %0
 
@@ -70,40 +71,25 @@ entry:
 
 ; CHECK-V4T-LABEL: simpleframe
 ; CHECK-V5T-LABEL: simpleframe
-define i32 @simpleframe() #0 {
+define i32 @simpleframe(<6 x i32>* %p) #0 {
 entry:
 ; Prologue
 ; --------
 ; CHECK-V4T:    push    {[[SAVED:(r[4567](, )?)+]], lr}
 ; CHECK-V5T:    push    {[[SAVED:(r[4567](, )?)+]], lr}
 
-  %a = alloca i32, align 4
-  %b = alloca i32, align 4
-  %c = alloca i32, align 4
-  %d = alloca i32, align 4
-  store i32 1, i32* %a, align 4
-  store i32 2, i32* %b, align 4
-  store i32 3, i32* %c, align 4
-  store i32 4, i32* %d, align 4
-  %0 = load i32* %a, align 4
-  %inc = add nsw i32 %0, 1
-  store i32 %inc, i32* %a, align 4
-  %1 = load i32* %b, align 4
-  %inc1 = add nsw i32 %1, 1
-  store i32 %inc1, i32* %b, align 4
-  %2 = load i32* %c, align 4
-  %inc2 = add nsw i32 %2, 1
-  store i32 %inc2, i32* %c, align 4
-  %3 = load i32* %d, align 4
-  %inc3 = add nsw i32 %3, 1
-  store i32 %inc3, i32* %d, align 4
-  %4 = load i32* %a, align 4
-  %5 = load i32* %b, align 4
-  %add = add nsw i32 %4, %5
-  %6 = load i32* %c, align 4
-  %add4 = add nsw i32 %add, %6
-  %7 = load i32* %d, align 4
-  %add5 = add nsw i32 %add4, %7
+  %0 = load <6 x i32>, <6 x i32>* %p, align 16
+  %1 = extractelement <6 x i32> %0, i32 0
+  %2 = extractelement <6 x i32> %0, i32 1
+  %3 = extractelement <6 x i32> %0, i32 2
+  %4 = extractelement <6 x i32> %0, i32 3
+  %5 = extractelement <6 x i32> %0, i32 4
+  %6 = extractelement <6 x i32> %0, i32 5
+  %add1 = add nsw i32 %1, %2
+  %add2 = add nsw i32 %add1, %3
+  %add3 = add nsw i32 %add2, %4
+  %add4 = add nsw i32 %add3, %5
+  %add5 = add nsw i32 %add4, %6
   ret i32 %add5
 
 ; Epilogue
@@ -135,24 +121,24 @@ entry:
   store i32 2, i32* %b, align 4
   store i32 3, i32* %c, align 4
   store i32 4, i32* %d, align 4
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %a, align 4
-  %1 = load i32* %b, align 4
+  %1 = load i32, i32* %b, align 4
   %inc1 = add nsw i32 %1, 1
   store i32 %inc1, i32* %b, align 4
-  %2 = load i32* %c, align 4
+  %2 = load i32, i32* %c, align 4
   %inc2 = add nsw i32 %2, 1
   store i32 %inc2, i32* %c, align 4
-  %3 = load i32* %d, align 4
+  %3 = load i32, i32* %d, align 4
   %inc3 = add nsw i32 %3, 1
   store i32 %inc3, i32* %d, align 4
-  %4 = load i32* %a, align 4
-  %5 = load i32* %b, align 4
+  %4 = load i32, i32* %a, align 4
+  %5 = load i32, i32* %b, align 4
   %add = add nsw i32 %4, %5
-  %6 = load i32* %c, align 4
+  %6 = load i32, i32* %c, align 4
   %add4 = add nsw i32 %add, %6
-  %7 = load i32* %d, align 4
+  %7 = load i32, i32* %d, align 4
   %add5 = add nsw i32 %add4, %7
   %add6 = add nsw i32 %add5, %i
   call void @llvm.va_start(i8* null)
diff --git a/test/CodeGen/ARM/thumb2-size-reduction-internal-flags.ll b/test/CodeGen/ARM/thumb2-size-reduction-internal-flags.ll
new file mode 100644
index 000000000000..578777f97c50
--- /dev/null
+++ b/test/CodeGen/ARM/thumb2-size-reduction-internal-flags.ll
@@ -0,0 +1,173 @@
+; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7s-apple-ios8.0.0"
+
+%struct.cells = type { i32, i32, %struct.cells* }
+
+@reg_len = external global i32, align 4
+
+; The thumb2 size reduction pass commutes arguments to make the first src of an add the same as the dest.
+; It needs to also move the internal flag when commuting arguments.
+
+; CHECK-LABEL: @simulate
+
+; Function Attrs: nounwind optsize ssp
+define i32 @simulate(i32 %iterations, %struct.cells* nocapture %present, double %prob, i8* nocapture readonly %structure) {
+entry:
+  %0 = load i32, i32* @reg_len, align 4, !tbaa !3
+  %sub = add nsw i32 %0, -1
+  %div = sdiv i32 %sub, 31
+  %rem2 = srem i32 %sub, 31
+  %cmp35202 = icmp sgt i32 %rem2, 0
+  br label %for.cond3.preheader
+
+for.cond3.preheader:                              ; preds = %if.end85, %entry
+  %call192 = tail call i32 @lrand48() #2
+  br label %for.cond6.preheader
+
+for.cond34.preheader:                             ; preds = %for.inc30
+  br i1 %cmp35202, label %for.body37, label %for.end73
+
+for.cond6.preheader:                              ; preds = %for.inc30, %for.cond3.preheader
+  %call197 = phi i32 [ %call, %for.inc30 ], [ %call192, %for.cond3.preheader ]
+  %i.0196 = phi i32 [ %inc31, %for.inc30 ], [ 0, %for.cond3.preheader ]
+  %temp.1195 = phi %struct.cells* [ %5, %for.inc30 ], [ %present, %for.cond3.preheader ]
+  %savefaulty.0194 = phi i32 [ %add12, %for.inc30 ], [ 0, %for.cond3.preheader ]
+  %savef_free.0193 = phi i32 [ %add11, %for.inc30 ], [ 0, %for.cond3.preheader ]
+  br label %for.body8
+
+for.body8:                                        ; preds = %for.body8, %for.cond6.preheader
+  %randv.0190 = phi i32 [ %call197, %for.cond6.preheader ], [ %shr, %for.body8 ]
+  %j.0189 = phi i32 [ 0, %for.cond6.preheader ], [ %inc, %for.body8 ]
+  %temp.2188 = phi %struct.cells* [ %temp.1195, %for.cond6.preheader ], [ %5, %for.body8 ]
+  %savefaulty.1187 = phi i32 [ %savefaulty.0194, %for.cond6.preheader ], [ %add12, %for.body8 ]
+  %savef_free.1186 = phi i32 [ %savef_free.0193, %for.cond6.preheader ], [ %add11, %for.body8 ]
+  %f_free = getelementptr inbounds %struct.cells, %struct.cells* %temp.2188, i32 0, i32 0
+  %1 = load i32, i32* %f_free, align 4, !tbaa !7
+  %add11 = add nsw i32 %1, %savef_free.1186
+  %faulty = getelementptr inbounds %struct.cells, %struct.cells* %temp.2188, i32 0, i32 1
+  %2 = load i32, i32* %faulty, align 4, !tbaa !10
+  %add12 = add nsw i32 %2, %savefaulty.1187
+  %next = getelementptr inbounds %struct.cells, %struct.cells* %temp.2188, i32 0, i32 2
+  %3 = load %struct.cells*, %struct.cells** %next, align 4, !tbaa !11
+  %f_free13 = getelementptr inbounds %struct.cells, %struct.cells* %3, i32 0, i32 0
+  %4 = load i32, i32* %f_free13, align 4, !tbaa !7
+  %add14 = add nsw i32 %4, %randv.0190
+  %and = and i32 %add14, 1
+  store i32 %and, i32* %f_free, align 4, !tbaa !7
+  %call16 = tail call i32 @lrand48() #2
+  %rem17 = srem i32 %call16, 1000
+  %conv18 = sitofp i32 %rem17 to double
+  %div19 = fdiv double %conv18, 1.000000e+03
+  %cmp20 = fcmp olt double %div19, %prob
+  %xor = zext i1 %cmp20 to i32
+  %randv.1 = xor i32 %xor, %randv.0190
+  %5 = load %struct.cells*, %struct.cells** %next, align 4, !tbaa !11
+  %faulty25 = getelementptr inbounds %struct.cells, %struct.cells* %5, i32 0, i32 1
+  %6 = load i32, i32* %faulty25, align 4, !tbaa !10
+  %add26 = add nsw i32 %randv.1, %6
+  %and27 = and i32 %add26, 1
+  store i32 %and27, i32* %faulty, align 4, !tbaa !10
+  %shr = ashr i32 %randv.0190, 1
+  %inc = add nuw nsw i32 %j.0189, 1
+  %exitcond = icmp eq i32 %inc, 31
+  br i1 %exitcond, label %for.inc30, label %for.body8
+
+for.inc30:                                        ; preds = %for.body8
+  %inc31 = add nuw nsw i32 %i.0196, 1
+  %cmp4 = icmp slt i32 %inc31, %div
+  %call = tail call i32 @lrand48() #2
+  br i1 %cmp4, label %for.cond6.preheader, label %for.cond34.preheader
+
+for.body37:                                       ; preds = %for.body37, %for.cond34.preheader
+  %randv.2207 = phi i32 [ %shr70, %for.body37 ], [ %call, %for.cond34.preheader ]
+  %temp.3205 = phi %struct.cells* [ %9, %for.body37 ], [ %5, %for.cond34.preheader ]
+  %f_free45 = getelementptr inbounds %struct.cells, %struct.cells* %temp.3205, i32 0, i32 0
+  %.pre220 = getelementptr inbounds %struct.cells, %struct.cells* %temp.3205, i32 0, i32 1
+  %next50 = getelementptr inbounds %struct.cells, %struct.cells* %temp.3205, i32 0, i32 2
+  %7 = load %struct.cells*, %struct.cells** %next50, align 4, !tbaa !11
+  %f_free51 = getelementptr inbounds %struct.cells, %struct.cells* %7, i32 0, i32 0
+  %8 = load i32, i32* %f_free51, align 4, !tbaa !7
+  %add52 = add nsw i32 %8, %randv.2207
+  %and53 = and i32 %add52, 1
+  store i32 %and53, i32* %f_free45, align 4, !tbaa !7
+  %call55 = tail call i32 @lrand48() #2
+  %rem56 = srem i32 %call55, 1000
+  %conv57 = sitofp i32 %rem56 to double
+  %div58 = fdiv double %conv57, 1.000000e+03
+  %cmp59 = fcmp olt double %div58, %prob
+  %xor62 = zext i1 %cmp59 to i32
+  %randv.3 = xor i32 %xor62, %randv.2207
+  %9 = load %struct.cells*, %struct.cells** %next50, align 4, !tbaa !11
+  %faulty65 = getelementptr inbounds %struct.cells, %struct.cells* %9, i32 0, i32 1
+  %10 = load i32, i32* %faulty65, align 4, !tbaa !10
+  %add66 = add nsw i32 %randv.3, %10
+  %and67 = and i32 %add66, 1
+  store i32 %and67, i32* %.pre220, align 4, !tbaa !10
+  %shr70 = ashr i32 %randv.2207, 1
+  br label %for.body37
+
+for.end73:                                        ; preds = %for.cond34.preheader
+  %call74 = tail call i32 @lrand48() #2
+  %11 = load i32, i32* @reg_len, align 4, !tbaa !3
+  %sub75 = add nsw i32 %11, -1
+  %arrayidx76 = getelementptr inbounds i8, i8* %structure, i32 %sub75
+  %12 = load i8, i8* %arrayidx76, align 1, !tbaa !12
+  %cmp78 = icmp eq i8 %12, 49
+  %f_free81 = getelementptr inbounds %struct.cells, %struct.cells* %5, i32 0, i32 0
+  br i1 %cmp78, label %if.then80, label %for.end73.if.end85_crit_edge
+
+for.end73.if.end85_crit_edge:                     ; preds = %for.end73
+  %.pre222 = getelementptr inbounds %struct.cells, %struct.cells* %5, i32 0, i32 1
+  br label %if.end85
+
+if.then80:                                        ; preds = %for.end73
+  %13 = load i32, i32* %f_free81, align 4, !tbaa !7
+  %add82 = add nsw i32 %13, %add11
+  %faulty83 = getelementptr inbounds %struct.cells, %struct.cells* %5, i32 0, i32 1
+  %14 = load i32, i32* %faulty83, align 4, !tbaa !10
+  %add84 = add nsw i32 %14, %add12
+  br label %if.end85
+
+if.end85:                                         ; preds = %if.then80, %for.end73.if.end85_crit_edge
+  %faulty100.pre-phi = phi i32* [ %.pre222, %for.end73.if.end85_crit_edge ], [ %faulty83, %if.then80 ]
+  %savef_free.5 = phi i32 [ %add11, %for.end73.if.end85_crit_edge ], [ %add82, %if.then80 ]
+  %savefaulty.5 = phi i32 [ %add12, %for.end73.if.end85_crit_edge ], [ %add84, %if.then80 ]
+  %add86 = add nsw i32 %savef_free.5, %call74
+  %and87 = and i32 %add86, 1
+  store i32 %and87, i32* %f_free81, align 4, !tbaa !7
+  %call89 = tail call i32 @lrand48() #2
+  %rem90 = srem i32 %call89, 10000
+  %conv91 = sitofp i32 %rem90 to double
+  %div92 = fdiv double %conv91, 1.000000e+04
+  %cmp93 = fcmp olt double %div92, %prob
+  %xor96 = zext i1 %cmp93 to i32
+  %randv.4 = xor i32 %xor96, %call74
+  %add98 = add nsw i32 %randv.4, %savefaulty.5
+  %and99 = and i32 %add98, 1
+  store i32 %and99, i32* %faulty100.pre-phi, align 4, !tbaa !10
+  br label %for.cond3.preheader
+}
+
+; Function Attrs: optsize
+declare i32 @lrand48()
+
+attributes #2 = { nounwind optsize }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, !"min_enum_size", i32 4}
+!2 = !{!"clang version 3.7.0 (trunk 236243)"}
+!3 = !{!4, !4, i64 0}
+!4 = !{!"int", !5, i64 0}
+!5 = !{!"omnipotent char", !6, i64 0}
+!6 = !{!"Simple C/C++ TBAA"}
+!7 = !{!8, !4, i64 0}
+!8 = !{!"cells", !4, i64 0, !4, i64 4, !9, i64 8}
+!9 = !{!"any pointer", !5, i64 0}
+!10 = !{!8, !4, i64 4}
+!11 = !{!8, !9, i64 8}
+!12 = !{!5, !5, i64 0}
diff --git a/test/CodeGen/ARM/thumb_indirect_calls.ll b/test/CodeGen/ARM/thumb_indirect_calls.ll
index 16a55a882d9a..9f1950c743c0 100644
--- a/test/CodeGen/ARM/thumb_indirect_calls.ll
+++ b/test/CodeGen/ARM/thumb_indirect_calls.ll
@@ -6,7 +6,7 @@
 ; CHECK-LABEL foo:
 define void @foo(i32 %x) {
 entry:
-  %0 = load void (i32)** @f, align 4
+  %0 = load void (i32)*, void (i32)** @f, align 4
   tail call void %0(i32 %x)
   ret void
 
diff --git a/test/CodeGen/ARM/tls1.ll b/test/CodeGen/ARM/tls1.ll
index b03f76b6ef08..d492522955ec 100644
--- a/test/CodeGen/ARM/tls1.ll
+++ b/test/CodeGen/ARM/tls1.ll
@@ -12,7 +12,7 @@
 
 define i32 @f() {
 entry:
-	%tmp1 = load i32* @i		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* @i		; <i32> [#uses=1]
 	ret i32 %tmp1
 }
 
diff --git a/test/CodeGen/ARM/tls2.ll b/test/CodeGen/ARM/tls2.ll
index 24b4794b061a..d522da8f5714 100644
--- a/test/CodeGen/ARM/tls2.ll
+++ b/test/CodeGen/ARM/tls2.ll
@@ -12,7 +12,7 @@ define i32 @f() {
 ; CHECK-PIC-LABEL: f:
 ; CHECK-PIC: __tls_get_addr
 entry:
-	%tmp1 = load i32* @i		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* @i		; <i32> [#uses=1]
 	ret i32 %tmp1
 }
 
diff --git a/test/CodeGen/ARM/tls3.ll b/test/CodeGen/ARM/tls3.ll
index e0e944f70c5d..7e17b13a3c99 100644
--- a/test/CodeGen/ARM/tls3.ll
+++ b/test/CodeGen/ARM/tls3.ll
@@ -6,6 +6,6 @@
 
 define i32 @main() {
 entry:
-	%tmp2 = load i32* getelementptr (%struct.anon* @teste, i32 0, i32 0), align 8		; <i32> [#uses=1]
+	%tmp2 = load i32, i32* getelementptr (%struct.anon, %struct.anon* @teste, i32 0, i32 0), align 8		; <i32> [#uses=1]
 	ret i32 %tmp2
 }
diff --git a/test/CodeGen/ARM/trunc_ldr.ll b/test/CodeGen/ARM/trunc_ldr.ll
index 2ce9b894d55a..ca7ad9a2fc62 100644
--- a/test/CodeGen/ARM/trunc_ldr.ll
+++ b/test/CodeGen/ARM/trunc_ldr.ll
@@ -4,18 +4,18 @@
 	%struct.B = type { float, float, i32, i32, i32, [0 x i8] }
 
 define i8 @f1(%struct.A* %d) {
-	%tmp2 = getelementptr %struct.A* %d, i32 0, i32 4
+	%tmp2 = getelementptr %struct.A, %struct.A* %d, i32 0, i32 4
 	%tmp23 = bitcast i16* %tmp2 to i32*
-	%tmp4 = load i32* %tmp23
+	%tmp4 = load i32, i32* %tmp23
 	%tmp512 = lshr i32 %tmp4, 24
 	%tmp56 = trunc i32 %tmp512 to i8
 	ret i8 %tmp56
 }
 
 define i32 @f2(%struct.A* %d) {
-	%tmp2 = getelementptr %struct.A* %d, i32 0, i32 4
+	%tmp2 = getelementptr %struct.A, %struct.A* %d, i32 0, i32 4
 	%tmp23 = bitcast i16* %tmp2 to i32*
-	%tmp4 = load i32* %tmp23
+	%tmp4 = load i32, i32* %tmp23
 	%tmp512 = lshr i32 %tmp4, 24
 	%tmp56 = trunc i32 %tmp512 to i8
         %tmp57 = sext i8 %tmp56 to i32
diff --git a/test/CodeGen/ARM/truncstore-dag-combine.ll b/test/CodeGen/ARM/truncstore-dag-combine.ll
index 360e3e13f59e..11fa022451f6 100644
--- a/test/CodeGen/ARM/truncstore-dag-combine.ll
+++ b/test/CodeGen/ARM/truncstore-dag-combine.ll
@@ -3,7 +3,7 @@
 define void @bar(i8* %P, i16* %Q) {
 entry:
 	%P1 = bitcast i8* %P to i16*		; <i16*> [#uses=1]
-	%tmp = load i16* %Q, align 1		; <i16> [#uses=1]
+	%tmp = load i16, i16* %Q, align 1		; <i16> [#uses=1]
 	store i16 %tmp, i16* %P1, align 1
 	ret void
 }
@@ -11,7 +11,7 @@ entry:
 define void @foo(i8* %P, i32* %Q) {
 entry:
 	%P1 = bitcast i8* %P to i32*		; <i32*> [#uses=1]
-	%tmp = load i32* %Q, align 1		; <i32> [#uses=1]
+	%tmp = load i32, i32* %Q, align 1		; <i32> [#uses=1]
 	store i32 %tmp, i32* %P1, align 1
 	ret void
 }
diff --git a/test/CodeGen/ARM/twoaddrinstr.ll b/test/CodeGen/ARM/twoaddrinstr.ll
index 01df3b42d107..97a49334b742 100644
--- a/test/CodeGen/ARM/twoaddrinstr.ll
+++ b/test/CodeGen/ARM/twoaddrinstr.ll
@@ -12,7 +12,7 @@ define void @PR13378() nounwind {
 ; CHECK-NEXT:   vst1.32
 
 entry:
-  %0 = load <4 x float>* undef, align 4
+  %0 = load <4 x float>, <4 x float>* undef, align 4
   store <4 x float> zeroinitializer, <4 x float>* undef, align 4
   store <4 x float> %0, <4 x float>* undef, align 4
   %1 = insertelement <4 x float> %0, float 1.000000e+00, i32 3
diff --git a/test/CodeGen/ARM/uint64tof64.ll b/test/CodeGen/ARM/uint64tof64.ll
index 32eb225a2ad6..cd35ce74d8ee 100644
--- a/test/CodeGen/ARM/uint64tof64.ll
+++ b/test/CodeGen/ARM/uint64tof64.ll
@@ -7,10 +7,10 @@
 
 define fastcc void @t() {
 entry:
-	%0 = load i64* null, align 4		; <i64> [#uses=1]
+	%0 = load i64, i64* null, align 4		; <i64> [#uses=1]
 	%1 = uitofp i64 %0 to double		; <double> [#uses=1]
 	%2 = fdiv double 0.000000e+00, %1		; <double> [#uses=1]
-	%3 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* null, i8* getelementptr ([54 x i8]* @"\01LC10", i32 0, i32 0), i64 0, double %2)		; <i32> [#uses=0]
+	%3 = call i32 (%struct.FILE*, i8*, ...) @fprintf(%struct.FILE* null, i8* getelementptr ([54 x i8], [54 x i8]* @"\01LC10", i32 0, i32 0), i64 0, double %2)		; <i32> [#uses=0]
 	ret void
 }
 
diff --git a/test/CodeGen/ARM/umulo-32.ll b/test/CodeGen/ARM/umulo-32.ll
index 19875ce94071..1c8357314c28 100644
--- a/test/CodeGen/ARM/umulo-32.ll
+++ b/test/CodeGen/ARM/umulo-32.ll
@@ -28,7 +28,7 @@ store i32 0, i32* %1
 store i32 %argc, i32* %2, align 4
 store i8** %argv, i8*** %3, align 4
 store i32 10, i32* %m_degree, align 4
-%4 = load i32* %m_degree, align 4
+%4 = load i32, i32* %m_degree, align 4
 %5 = call %umul.ty @llvm.umul.with.overflow.i32(i32 %4, i32 8)
 %6 = extractvalue %umul.ty %5, 1
 %7 = extractvalue %umul.ty %5, 0
diff --git a/test/CodeGen/ARM/unaligned_load_store.ll b/test/CodeGen/ARM/unaligned_load_store.ll
index 72163ae30c38..0be3917ffa26 100644
--- a/test/CodeGen/ARM/unaligned_load_store.ll
+++ b/test/CodeGen/ARM/unaligned_load_store.ll
@@ -28,7 +28,7 @@ entry:
 
   %__src1.i = bitcast i8* %b to i32*              ; <i32*> [#uses=1]
   %__dest2.i = bitcast i8* %a to i32*             ; <i32*> [#uses=1]
-  %tmp.i = load i32* %__src1.i, align 1           ; <i32> [#uses=1]
+  %tmp.i = load i32, i32* %__src1.i, align 1           ; <i32> [#uses=1]
   store i32 %tmp.i, i32* %__dest2.i, align 1
   ret void
 }
@@ -44,7 +44,7 @@ entry:
 ; UNALIGNED-LABEL: hword:
 ; UNALIGNED: vld1.16
 ; UNALIGNED: vst1.16
-  %tmp = load double* %a, align 2
+  %tmp = load double, double* %a, align 2
   store double %tmp, double* %b, align 2
   ret void
 }
@@ -60,7 +60,7 @@ entry:
 ; UNALIGNED-LABEL: byte:
 ; UNALIGNED: vld1.8
 ; UNALIGNED: vst1.8
-  %tmp = load double* %a, align 1
+  %tmp = load double, double* %a, align 1
   store double %tmp, double* %b, align 1
   ret void
 }
@@ -76,7 +76,7 @@ entry:
 ; UNALIGNED: ldr
 ; UNALIGNED-NOT: strb
 ; UNALIGNED: str
-  %tmp = load i32* %a, align 1
+  %tmp = load i32, i32* %a, align 1
   store i32 %tmp, i32* %b, align 1
   ret void
 }
diff --git a/test/CodeGen/ARM/unaligned_load_store_vector.ll b/test/CodeGen/ARM/unaligned_load_store_vector.ll
index 000ed489c4c0..abb523c22757 100644
--- a/test/CodeGen/ARM/unaligned_load_store_vector.ll
+++ b/test/CodeGen/ARM/unaligned_load_store_vector.ll
@@ -6,12 +6,12 @@
 define void @v64_v8i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v64_v8i8_1:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <8 x i8>*
   %vo  = bitcast i8* %po to <8 x i8>*
 ;CHECK: vld1.8
-  %v1 = load  <8 x i8>* %vi, align 1
+  %v1 = load  <8 x i8>,  <8 x i8>* %vi, align 1
 ;CHECK: vst1.8
   store <8 x i8> %v1, <8 x i8>* %vo, align 1
   ret void
@@ -24,12 +24,12 @@ entry:
 define void @v64_v4i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v64_v4i16_1:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <4 x i16>*
   %vo  = bitcast i8* %po to <4 x i16>*
 ;CHECK: vld1.8
-  %v1 = load  <4 x i16>* %vi, align 1
+  %v1 = load  <4 x i16>,  <4 x i16>* %vi, align 1
 ;CHECK: vst1.8
   store <4 x i16> %v1, <4 x i16>* %vo, align 1
   ret void
@@ -42,12 +42,12 @@ entry:
 define void @v64_v2i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v64_v2i32_1:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <2 x i32>*
   %vo  = bitcast i8* %po to <2 x i32>*
 ;CHECK: vld1.8
-  %v1 = load  <2 x i32>* %vi, align 1
+  %v1 = load  <2 x i32>,  <2 x i32>* %vi, align 1
 ;CHECK: vst1.8
   store <2 x i32> %v1, <2 x i32>* %vo, align 1
   ret void
@@ -60,12 +60,12 @@ entry:
 define void @v64_v2f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v64_v2f32_1:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <2 x float>*
   %vo  = bitcast i8* %po to <2 x float>*
 ;CHECK: vld1.8
-  %v1 = load  <2 x float>* %vi, align 1
+  %v1 = load  <2 x float>,  <2 x float>* %vi, align 1
 ;CHECK: vst1.8
   store <2 x float> %v1, <2 x float>* %vo, align 1
   ret void
@@ -78,12 +78,12 @@ entry:
 define void @v128_v16i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v128_v16i8_1:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <16 x i8>*
   %vo  = bitcast i8* %po to <16 x i8>*
 ;CHECK: vld1.8
-  %v1 = load  <16 x i8>* %vi, align 1
+  %v1 = load  <16 x i8>,  <16 x i8>* %vi, align 1
 ;CHECK: vst1.8
   store <16 x i8> %v1, <16 x i8>* %vo, align 1
   ret void
@@ -96,12 +96,12 @@ entry:
 define void @v128_v8i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v128_v8i16_1:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <8 x i16>*
   %vo  = bitcast i8* %po to <8 x i16>*
 ;CHECK: vld1.8
-  %v1 = load  <8 x i16>* %vi, align 1
+  %v1 = load  <8 x i16>,  <8 x i16>* %vi, align 1
 ;CHECK: vst1.8
   store <8 x i16> %v1, <8 x i16>* %vo, align 1
   ret void
@@ -114,12 +114,12 @@ entry:
 define void @v128_v4i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v128_v4i32_1:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <4 x i32>*
   %vo  = bitcast i8* %po to <4 x i32>*
 ;CHECK: vld1.8
-  %v1 = load  <4 x i32>* %vi, align 1
+  %v1 = load  <4 x i32>,  <4 x i32>* %vi, align 1
 ;CHECK: vst1.8
   store <4 x i32> %v1, <4 x i32>* %vo, align 1
   ret void
@@ -132,12 +132,12 @@ entry:
 define void @v128_v2i64_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v128_v2i64_1:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <2 x i64>*
   %vo  = bitcast i8* %po to <2 x i64>*
 ;CHECK: vld1.8
-  %v1 = load  <2 x i64>* %vi, align 1
+  %v1 = load  <2 x i64>,  <2 x i64>* %vi, align 1
 ;CHECK: vst1.8
   store <2 x i64> %v1, <2 x i64>* %vo, align 1
   ret void
@@ -150,12 +150,12 @@ entry:
 define void @v128_v4f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v128_v4f32_1:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <4 x float>*
   %vo  = bitcast i8* %po to <4 x float>*
 ;CHECK: vld1.8
-  %v1 = load  <4 x float>* %vi, align 1
+  %v1 = load  <4 x float>,  <4 x float>* %vi, align 1
 ;CHECK: vst1.8
   store <4 x float> %v1, <4 x float>* %vo, align 1
   ret void
@@ -168,12 +168,12 @@ entry:
 define void @v64_v8i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v64_v8i8_2:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <8 x i8>*
   %vo  = bitcast i8* %po to <8 x i8>*
 ;CHECK: vld1.16
-  %v1 = load  <8 x i8>* %vi, align 2
+  %v1 = load  <8 x i8>,  <8 x i8>* %vi, align 2
 ;CHECK: vst1.16
   store <8 x i8> %v1, <8 x i8>* %vo, align 2
   ret void
@@ -186,12 +186,12 @@ entry:
 define void @v64_v4i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v64_v4i16_2:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <4 x i16>*
   %vo  = bitcast i8* %po to <4 x i16>*
 ;CHECK: vld1.16
-  %v1 = load  <4 x i16>* %vi, align 2
+  %v1 = load  <4 x i16>,  <4 x i16>* %vi, align 2
 ;CHECK: vst1.16
   store <4 x i16> %v1, <4 x i16>* %vo, align 2
   ret void
@@ -204,12 +204,12 @@ entry:
 define void @v64_v2i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v64_v2i32_2:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <2 x i32>*
   %vo  = bitcast i8* %po to <2 x i32>*
 ;CHECK: vld1.16
-  %v1 = load  <2 x i32>* %vi, align 2
+  %v1 = load  <2 x i32>,  <2 x i32>* %vi, align 2
 ;CHECK: vst1.16
   store <2 x i32> %v1, <2 x i32>* %vo, align 2
   ret void
@@ -222,12 +222,12 @@ entry:
 define void @v64_v2f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v64_v2f32_2:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <2 x float>*
   %vo  = bitcast i8* %po to <2 x float>*
 ;CHECK: vld1.16
-  %v1 = load  <2 x float>* %vi, align 2
+  %v1 = load  <2 x float>,  <2 x float>* %vi, align 2
 ;CHECK: vst1.16
   store <2 x float> %v1, <2 x float>* %vo, align 2
   ret void
@@ -240,12 +240,12 @@ entry:
 define void @v128_v16i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v128_v16i8_2:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <16 x i8>*
   %vo  = bitcast i8* %po to <16 x i8>*
 ;CHECK: vld1.16
-  %v1 = load  <16 x i8>* %vi, align 2
+  %v1 = load  <16 x i8>,  <16 x i8>* %vi, align 2
 ;CHECK: vst1.16
   store <16 x i8> %v1, <16 x i8>* %vo, align 2
   ret void
@@ -258,12 +258,12 @@ entry:
 define void @v128_v8i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v128_v8i16_2:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <8 x i16>*
   %vo  = bitcast i8* %po to <8 x i16>*
 ;CHECK: vld1.16
-  %v1 = load  <8 x i16>* %vi, align 2
+  %v1 = load  <8 x i16>,  <8 x i16>* %vi, align 2
 ;CHECK: vst1.16
   store <8 x i16> %v1, <8 x i16>* %vo, align 2
   ret void
@@ -276,12 +276,12 @@ entry:
 define void @v128_v4i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v128_v4i32_2:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <4 x i32>*
   %vo  = bitcast i8* %po to <4 x i32>*
 ;CHECK: vld1.16
-  %v1 = load  <4 x i32>* %vi, align 2
+  %v1 = load  <4 x i32>,  <4 x i32>* %vi, align 2
 ;CHECK: vst1.16
   store <4 x i32> %v1, <4 x i32>* %vo, align 2
   ret void
@@ -294,12 +294,12 @@ entry:
 define void @v128_v2i64_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v128_v2i64_2:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <2 x i64>*
   %vo  = bitcast i8* %po to <2 x i64>*
 ;CHECK: vld1.16
-  %v1 = load  <2 x i64>* %vi, align 2
+  %v1 = load  <2 x i64>,  <2 x i64>* %vi, align 2
 ;CHECK: vst1.16
   store <2 x i64> %v1, <2 x i64>* %vo, align 2
   ret void
@@ -312,12 +312,12 @@ entry:
 define void @v128_v4f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v128_v4f32_2:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <4 x float>*
   %vo  = bitcast i8* %po to <4 x float>*
 ;CHECK: vld1.16
-  %v1 = load  <4 x float>* %vi, align 2
+  %v1 = load  <4 x float>,  <4 x float>* %vi, align 2
 ;CHECK: vst1.16
   store <4 x float> %v1, <4 x float>* %vo, align 2
   ret void
@@ -330,12 +330,12 @@ entry:
 define void @v64_v8i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v64_v8i8_4:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <8 x i8>*
   %vo  = bitcast i8* %po to <8 x i8>*
 ;CHECK: vldr
-  %v1 = load  <8 x i8>* %vi, align 4
+  %v1 = load  <8 x i8>,  <8 x i8>* %vi, align 4
 ;CHECK: vstr
   store <8 x i8> %v1, <8 x i8>* %vo, align 4
   ret void
@@ -348,12 +348,12 @@ entry:
 define void @v64_v4i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v64_v4i16_4:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <4 x i16>*
   %vo  = bitcast i8* %po to <4 x i16>*
 ;CHECK: vldr
-  %v1 = load  <4 x i16>* %vi, align 4
+  %v1 = load  <4 x i16>,  <4 x i16>* %vi, align 4
 ;CHECK: vstr
   store <4 x i16> %v1, <4 x i16>* %vo, align 4
   ret void
@@ -366,12 +366,12 @@ entry:
 define void @v64_v2i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v64_v2i32_4:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <2 x i32>*
   %vo  = bitcast i8* %po to <2 x i32>*
 ;CHECK: vldr
-  %v1 = load  <2 x i32>* %vi, align 4
+  %v1 = load  <2 x i32>,  <2 x i32>* %vi, align 4
 ;CHECK: vstr
   store <2 x i32> %v1, <2 x i32>* %vo, align 4
   ret void
@@ -384,12 +384,12 @@ entry:
 define void @v64_v2f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v64_v2f32_4:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <2 x float>*
   %vo  = bitcast i8* %po to <2 x float>*
 ;CHECK: vldr
-  %v1 = load  <2 x float>* %vi, align 4
+  %v1 = load  <2 x float>,  <2 x float>* %vi, align 4
 ;CHECK: vstr
   store <2 x float> %v1, <2 x float>* %vo, align 4
   ret void
@@ -402,12 +402,12 @@ entry:
 define void @v128_v16i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v128_v16i8_4:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <16 x i8>*
   %vo  = bitcast i8* %po to <16 x i8>*
 ;CHECK: vld1.32
-  %v1 = load  <16 x i8>* %vi, align 4
+  %v1 = load  <16 x i8>,  <16 x i8>* %vi, align 4
 ;CHECK: vst1.32
   store <16 x i8> %v1, <16 x i8>* %vo, align 4
   ret void
@@ -420,12 +420,12 @@ entry:
 define void @v128_v8i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v128_v8i16_4:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <8 x i16>*
   %vo  = bitcast i8* %po to <8 x i16>*
 ;CHECK: vld1.32
-  %v1 = load  <8 x i16>* %vi, align 4
+  %v1 = load  <8 x i16>,  <8 x i16>* %vi, align 4
 ;CHECK: vst1.32
   store <8 x i16> %v1, <8 x i16>* %vo, align 4
   ret void
@@ -438,12 +438,12 @@ entry:
 define void @v128_v4i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v128_v4i32_4:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <4 x i32>*
   %vo  = bitcast i8* %po to <4 x i32>*
 ;CHECK: vld1.32
-  %v1 = load  <4 x i32>* %vi, align 4
+  %v1 = load  <4 x i32>,  <4 x i32>* %vi, align 4
 ;CHECK: vst1.32
   store <4 x i32> %v1, <4 x i32>* %vo, align 4
   ret void
@@ -456,12 +456,12 @@ entry:
 define void @v128_v2i64_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v128_v2i64_4:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <2 x i64>*
   %vo  = bitcast i8* %po to <2 x i64>*
 ;CHECK: vld1.32
-  %v1 = load  <2 x i64>* %vi, align 4
+  %v1 = load  <2 x i64>,  <2 x i64>* %vi, align 4
 ;CHECK: vst1.32
   store <2 x i64> %v1, <2 x i64>* %vo, align 4
   ret void
@@ -474,12 +474,12 @@ entry:
 define void @v128_v4f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
 ;CHECK-LABEL: v128_v4f32_4:
 entry:
-  %po = getelementptr i8* %out, i32 0
-  %pi = getelementptr i8* %in,  i32 0
+  %po = getelementptr i8, i8* %out, i32 0
+  %pi = getelementptr i8, i8* %in,  i32 0
   %vi  = bitcast i8* %pi to <4 x float>*
   %vo  = bitcast i8* %po to <4 x float>*
 ;CHECK: vld1.32
-  %v1 = load  <4 x float>* %vi, align 4
+  %v1 = load  <4 x float>,  <4 x float>* %vi, align 4
 ;CHECK: vst1.32
   store <4 x float> %v1, <4 x float>* %vo, align 4
   ret void
diff --git a/test/CodeGen/ARM/undef-sext.ll b/test/CodeGen/ARM/undef-sext.ll
index c6d76d0017df..bb06bcbaf44c 100644
--- a/test/CodeGen/ARM/undef-sext.ll
+++ b/test/CodeGen/ARM/undef-sext.ll
@@ -8,7 +8,7 @@ entry:
 ; CHECK: ldr r0, [r0]
 ; CHECK: bx lr
   %0 = sext i16 undef to i32
-  %1 = getelementptr inbounds i32* %a, i32 %0
-  %2 = load i32* %1, align 4
+  %1 = getelementptr inbounds i32, i32* %a, i32 %0
+  %2 = load i32, i32* %1, align 4
   ret i32 %2
 }
diff --git a/test/CodeGen/ARM/vaba.ll b/test/CodeGen/ARM/vaba.ll
index 6478b1843c69..4323f3184469 100644
--- a/test/CodeGen/ARM/vaba.ll
+++ b/test/CodeGen/ARM/vaba.ll
@@ -3,9 +3,9 @@
 define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ;CHECK-LABEL: vabas8:
 ;CHECK: vaba.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
-	%tmp3 = load <8 x i8>* %C
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
+	%tmp3 = load <8 x i8>, <8 x i8>* %C
 	%tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
 	%tmp5 = add <8 x i8> %tmp1, %tmp4
 	ret <8 x i8> %tmp5
@@ -14,9 +14,9 @@ define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK-LABEL: vabas16:
 ;CHECK: vaba.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
-	%tmp3 = load <4 x i16>* %C
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
+	%tmp3 = load <4 x i16>, <4 x i16>* %C
 	%tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
 	%tmp5 = add <4 x i16> %tmp1, %tmp4
 	ret <4 x i16> %tmp5
@@ -25,9 +25,9 @@ define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK-LABEL: vabas32:
 ;CHECK: vaba.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
-	%tmp3 = load <2 x i32>* %C
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
+	%tmp3 = load <2 x i32>, <2 x i32>* %C
 	%tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
 	%tmp5 = add <2 x i32> %tmp1, %tmp4
 	ret <2 x i32> %tmp5
@@ -36,9 +36,9 @@ define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ;CHECK-LABEL: vabau8:
 ;CHECK: vaba.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
-	%tmp3 = load <8 x i8>* %C
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
+	%tmp3 = load <8 x i8>, <8 x i8>* %C
 	%tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
 	%tmp5 = add <8 x i8> %tmp1, %tmp4
 	ret <8 x i8> %tmp5
@@ -47,9 +47,9 @@ define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK-LABEL: vabau16:
 ;CHECK: vaba.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
-	%tmp3 = load <4 x i16>* %C
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
+	%tmp3 = load <4 x i16>, <4 x i16>* %C
 	%tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
 	%tmp5 = add <4 x i16> %tmp1, %tmp4
 	ret <4 x i16> %tmp5
@@ -58,9 +58,9 @@ define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK-LABEL: vabau32:
 ;CHECK: vaba.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
-	%tmp3 = load <2 x i32>* %C
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
+	%tmp3 = load <2 x i32>, <2 x i32>* %C
 	%tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
 	%tmp5 = add <2 x i32> %tmp1, %tmp4
 	ret <2 x i32> %tmp5
@@ -69,9 +69,9 @@ define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
 ;CHECK-LABEL: vabaQs8:
 ;CHECK: vaba.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
-	%tmp3 = load <16 x i8>* %C
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
+	%tmp3 = load <16 x i8>, <16 x i8>* %C
 	%tmp4 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3)
 	%tmp5 = add <16 x i8> %tmp1, %tmp4
 	ret <16 x i8> %tmp5
@@ -80,9 +80,9 @@ define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
 define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
 ;CHECK-LABEL: vabaQs16:
 ;CHECK: vaba.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
-	%tmp3 = load <8 x i16>* %C
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
+	%tmp3 = load <8 x i16>, <8 x i16>* %C
 	%tmp4 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3)
 	%tmp5 = add <8 x i16> %tmp1, %tmp4
 	ret <8 x i16> %tmp5
@@ -91,9 +91,9 @@ define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
 define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: vabaQs32:
 ;CHECK: vaba.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
-	%tmp3 = load <4 x i32>* %C
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
+	%tmp3 = load <4 x i32>, <4 x i32>* %C
 	%tmp4 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3)
 	%tmp5 = add <4 x i32> %tmp1, %tmp4
 	ret <4 x i32> %tmp5
@@ -102,9 +102,9 @@ define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind
 define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
 ;CHECK-LABEL: vabaQu8:
 ;CHECK: vaba.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
-	%tmp3 = load <16 x i8>* %C
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
+	%tmp3 = load <16 x i8>, <16 x i8>* %C
 	%tmp4 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3)
 	%tmp5 = add <16 x i8> %tmp1, %tmp4
 	ret <16 x i8> %tmp5
@@ -113,9 +113,9 @@ define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
 define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
 ;CHECK-LABEL: vabaQu16:
 ;CHECK: vaba.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
-	%tmp3 = load <8 x i16>* %C
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
+	%tmp3 = load <8 x i16>, <8 x i16>* %C
 	%tmp4 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3)
 	%tmp5 = add <8 x i16> %tmp1, %tmp4
 	ret <8 x i16> %tmp5
@@ -124,9 +124,9 @@ define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
 define <4 x i32> @vabaQu32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: vabaQu32:
 ;CHECK: vaba.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
-	%tmp3 = load <4 x i32>* %C
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
+	%tmp3 = load <4 x i32>, <4 x i32>* %C
 	%tmp4 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3)
 	%tmp5 = add <4 x i32> %tmp1, %tmp4
 	ret <4 x i32> %tmp5
@@ -151,9 +151,9 @@ declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind read
 define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ;CHECK-LABEL: vabals8:
 ;CHECK: vabal.s8
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i8>* %B
-	%tmp3 = load <8 x i8>* %C
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
+	%tmp3 = load <8 x i8>, <8 x i8>* %C
 	%tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
 	%tmp5 = zext <8 x i8> %tmp4 to <8 x i16>
 	%tmp6 = add <8 x i16> %tmp1, %tmp5
@@ -163,9 +163,9 @@ define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK-LABEL: vabals16:
 ;CHECK: vabal.s16
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i16>* %B
-	%tmp3 = load <4 x i16>* %C
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
+	%tmp3 = load <4 x i16>, <4 x i16>* %C
 	%tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
 	%tmp5 = zext <4 x i16> %tmp4 to <4 x i32>
 	%tmp6 = add <4 x i32> %tmp1, %tmp5
@@ -175,9 +175,9 @@ define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK-LABEL: vabals32:
 ;CHECK: vabal.s32
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i32>* %B
-	%tmp3 = load <2 x i32>* %C
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
+	%tmp3 = load <2 x i32>, <2 x i32>* %C
 	%tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
 	%tmp5 = zext <2 x i32> %tmp4 to <2 x i64>
 	%tmp6 = add <2 x i64> %tmp1, %tmp5
@@ -187,9 +187,9 @@ define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ;CHECK-LABEL: vabalu8:
 ;CHECK: vabal.u8
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i8>* %B
-	%tmp3 = load <8 x i8>* %C
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
+	%tmp3 = load <8 x i8>, <8 x i8>* %C
 	%tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
 	%tmp5 = zext <8 x i8> %tmp4 to <8 x i16>
 	%tmp6 = add <8 x i16> %tmp1, %tmp5
@@ -199,9 +199,9 @@ define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK-LABEL: vabalu16:
 ;CHECK: vabal.u16
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i16>* %B
-	%tmp3 = load <4 x i16>* %C
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
+	%tmp3 = load <4 x i16>, <4 x i16>* %C
 	%tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
 	%tmp5 = zext <4 x i16> %tmp4 to <4 x i32>
 	%tmp6 = add <4 x i32> %tmp1, %tmp5
@@ -211,9 +211,9 @@ define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 define <2 x i64> @vabalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK-LABEL: vabalu32:
 ;CHECK: vabal.u32
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i32>* %B
-	%tmp3 = load <2 x i32>* %C
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
+	%tmp3 = load <2 x i32>, <2 x i32>* %C
 	%tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
 	%tmp5 = zext <2 x i32> %tmp4 to <2 x i64>
 	%tmp6 = add <2 x i64> %tmp1, %tmp5
diff --git a/test/CodeGen/ARM/vabd.ll b/test/CodeGen/ARM/vabd.ll
index 9ba8be28c776..548b8a340461 100644
--- a/test/CodeGen/ARM/vabd.ll
+++ b/test/CodeGen/ARM/vabd.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vabds8:
 ;CHECK: vabd.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vabds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vabds16:
 ;CHECK: vabd.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @vabds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vabds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vabds32:
 ;CHECK: vabd.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @vabds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @vabdu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vabdu8:
 ;CHECK: vabd.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -39,8 +39,8 @@ define <8 x i8> @vabdu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vabdu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vabdu16:
 ;CHECK: vabd.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -48,8 +48,8 @@ define <4 x i16> @vabdu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vabdu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vabdu32:
 ;CHECK: vabd.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -57,8 +57,8 @@ define <2 x i32> @vabdu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <2 x float> @vabdf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vabdf32:
 ;CHECK: vabd.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.arm.neon.vabds.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
@@ -66,8 +66,8 @@ define <2 x float> @vabdf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <16 x i8> @vabdQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vabdQs8:
 ;CHECK: vabd.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -75,8 +75,8 @@ define <16 x i8> @vabdQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vabdQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vabdQs16:
 ;CHECK: vabd.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -84,8 +84,8 @@ define <8 x i16> @vabdQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vabdQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vabdQs32:
 ;CHECK: vabd.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -93,8 +93,8 @@ define <4 x i32> @vabdQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <16 x i8> @vabdQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vabdQu8:
 ;CHECK: vabd.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -102,8 +102,8 @@ define <16 x i8> @vabdQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vabdQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vabdQu16:
 ;CHECK: vabd.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -111,8 +111,8 @@ define <8 x i16> @vabdQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vabdQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vabdQu32:
 ;CHECK: vabd.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -120,8 +120,8 @@ define <4 x i32> @vabdQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <4 x float> @vabdQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vabdQf32:
 ;CHECK: vabd.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x float> %tmp3
 }
@@ -149,8 +149,8 @@ declare <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float>, <4 x float>) nounwin
 define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vabdls8:
 ;CHECK: vabdl.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	%tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
 	ret <8 x i16> %tmp4
@@ -159,8 +159,8 @@ define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vabdls16:
 ;CHECK: vabdl.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	%tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
 	ret <4 x i32> %tmp4
@@ -169,8 +169,8 @@ define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vabdls32:
 ;CHECK: vabdl.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	%tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
 	ret <2 x i64> %tmp4
@@ -179,8 +179,8 @@ define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vabdlu8:
 ;CHECK: vabdl.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	%tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
 	ret <8 x i16> %tmp4
@@ -189,8 +189,8 @@ define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vabdlu16:
 ;CHECK: vabdl.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	%tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
 	ret <4 x i32> %tmp4
@@ -199,8 +199,8 @@ define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @vabdlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vabdlu32:
 ;CHECK: vabdl.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	%tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
 	ret <2 x i64> %tmp4
diff --git a/test/CodeGen/ARM/vabs.ll b/test/CodeGen/ARM/vabs.ll
index 3a1aec86edfe..38c6d6c28aed 100644
--- a/test/CodeGen/ARM/vabs.ll
+++ b/test/CodeGen/ARM/vabs.ll
@@ -3,7 +3,7 @@
 define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vabss8:
 ;CHECK: vabs.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1)
 	ret <8 x i8> %tmp2
 }
@@ -11,7 +11,7 @@ define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vabss16:
 ;CHECK: vabs.s16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1)
 	ret <4 x i16> %tmp2
 }
@@ -19,7 +19,7 @@ define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vabss32:
 ;CHECK: vabs.s32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1)
 	ret <2 x i32> %tmp2
 }
@@ -27,7 +27,7 @@ define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
 define <2 x float> @vabsf32(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vabsf32:
 ;CHECK: vabs.f32
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp2 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %tmp1)
 	ret <2 x float> %tmp2
 }
@@ -35,7 +35,7 @@ define <2 x float> @vabsf32(<2 x float>* %A) nounwind {
 define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vabsQs8:
 ;CHECK: vabs.s8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1)
 	ret <16 x i8> %tmp2
 }
@@ -43,7 +43,7 @@ define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vabsQs16:
 ;CHECK: vabs.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1)
 	ret <8 x i16> %tmp2
 }
@@ -51,7 +51,7 @@ define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vabsQs32:
 ;CHECK: vabs.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1)
 	ret <4 x i32> %tmp2
 }
@@ -59,7 +59,7 @@ define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind {
 define <4 x float> @vabsQf32(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: vabsQf32:
 ;CHECK: vabs.f32
-	%tmp1 = load <4 x float>* %A
+	%tmp1 = load <4 x float>, <4 x float>* %A
 	%tmp2 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %tmp1)
 	ret <4 x float> %tmp2
 }
@@ -77,7 +77,7 @@ declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone
 define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vqabss8:
 ;CHECK: vqabs.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1)
 	ret <8 x i8> %tmp2
 }
@@ -85,7 +85,7 @@ define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqabss16:
 ;CHECK: vqabs.s16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1)
 	ret <4 x i16> %tmp2
 }
@@ -93,7 +93,7 @@ define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqabss32:
 ;CHECK: vqabs.s32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1)
 	ret <2 x i32> %tmp2
 }
@@ -101,7 +101,7 @@ define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind {
 define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vqabsQs8:
 ;CHECK: vqabs.s8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1)
 	ret <16 x i8> %tmp2
 }
@@ -109,7 +109,7 @@ define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqabsQs16:
 ;CHECK: vqabs.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1)
 	ret <8 x i16> %tmp2
 }
@@ -117,7 +117,7 @@ define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqabsQs32:
 ;CHECK: vqabs.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1)
 	ret <4 x i32> %tmp2
 }
diff --git a/test/CodeGen/ARM/vadd.ll b/test/CodeGen/ARM/vadd.ll
index 86b0d0297018..dd35dd1ccfb9 100644
--- a/test/CodeGen/ARM/vadd.ll
+++ b/test/CodeGen/ARM/vadd.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vaddi8:
 ;CHECK: vadd.i8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = add <8 x i8> %tmp1, %tmp2
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vaddi16:
 ;CHECK: vadd.i16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = add <4 x i16> %tmp1, %tmp2
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vaddi32:
 ;CHECK: vadd.i32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = add <2 x i32> %tmp1, %tmp2
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vaddi64:
 ;CHECK: vadd.i64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = add <1 x i64> %tmp1, %tmp2
 	ret <1 x i64> %tmp3
 }
@@ -39,8 +39,8 @@ define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vaddf32:
 ;CHECK: vadd.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fadd <2 x float> %tmp1, %tmp2
 	ret <2 x float> %tmp3
 }
@@ -48,8 +48,8 @@ define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vaddQi8:
 ;CHECK: vadd.i8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = add <16 x i8> %tmp1, %tmp2
 	ret <16 x i8> %tmp3
 }
@@ -57,8 +57,8 @@ define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vaddQi16:
 ;CHECK: vadd.i16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = add <8 x i16> %tmp1, %tmp2
 	ret <8 x i16> %tmp3
 }
@@ -66,8 +66,8 @@ define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vaddQi32:
 ;CHECK: vadd.i32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = add <4 x i32> %tmp1, %tmp2
 	ret <4 x i32> %tmp3
 }
@@ -75,8 +75,8 @@ define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vaddQi64:
 ;CHECK: vadd.i64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = add <2 x i64> %tmp1, %tmp2
 	ret <2 x i64> %tmp3
 }
@@ -84,8 +84,8 @@ define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vaddQf32:
 ;CHECK: vadd.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = fadd <4 x float> %tmp1, %tmp2
 	ret <4 x float> %tmp3
 }
@@ -93,8 +93,8 @@ define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vraddhni16:
 ;CHECK: vraddhn.i16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -102,8 +102,8 @@ define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vraddhni32:
 ;CHECK: vraddhn.i32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -111,8 +111,8 @@ define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i32> @vraddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vraddhni64:
 ;CHECK: vraddhn.i64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -151,8 +151,8 @@ define <2 x i32> @vaddhni64_natural(<2 x i64> %A, <2 x i64> %B) nounwind {
 define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vaddls8:
 ;CHECK: vaddl.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
 	%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
 	%tmp5 = add <8 x i16> %tmp3, %tmp4
@@ -162,8 +162,8 @@ define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vaddls16:
 ;CHECK: vaddl.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
 	%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
 	%tmp5 = add <4 x i32> %tmp3, %tmp4
@@ -173,8 +173,8 @@ define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vaddls32:
 ;CHECK: vaddl.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
 	%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
 	%tmp5 = add <2 x i64> %tmp3, %tmp4
@@ -184,8 +184,8 @@ define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vaddlu8:
 ;CHECK: vaddl.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
 	%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
 	%tmp5 = add <8 x i16> %tmp3, %tmp4
@@ -195,8 +195,8 @@ define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vaddlu16:
 ;CHECK: vaddl.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
 	%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
 	%tmp5 = add <4 x i32> %tmp3, %tmp4
@@ -206,8 +206,8 @@ define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vaddlu32:
 ;CHECK: vaddl.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
 	%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
 	%tmp5 = add <2 x i64> %tmp3, %tmp4
@@ -217,8 +217,8 @@ define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vaddws8:
 ;CHECK: vaddw.s8
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
 	%tmp4 = add <8 x i16> %tmp1, %tmp3
 	ret <8 x i16> %tmp4
@@ -227,8 +227,8 @@ define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vaddws16:
 ;CHECK: vaddw.s16
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
 	%tmp4 = add <4 x i32> %tmp1, %tmp3
 	ret <4 x i32> %tmp4
@@ -237,8 +237,8 @@ define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vaddws32:
 ;CHECK: vaddw.s32
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
 	%tmp4 = add <2 x i64> %tmp1, %tmp3
 	ret <2 x i64> %tmp4
@@ -247,8 +247,8 @@ define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vaddwu8:
 ;CHECK: vaddw.u8
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
 	%tmp4 = add <8 x i16> %tmp1, %tmp3
 	ret <8 x i16> %tmp4
@@ -257,8 +257,8 @@ define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vaddwu16:
 ;CHECK: vaddw.u16
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
 	%tmp4 = add <4 x i32> %tmp1, %tmp3
 	ret <4 x i32> %tmp4
@@ -267,8 +267,8 @@ define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @vaddwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vaddwu32:
 ;CHECK: vaddw.u32
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
 	%tmp4 = add <2 x i64> %tmp1, %tmp3
 	ret <2 x i64> %tmp4
diff --git a/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll b/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll
index 148a79df0cb8..4879d73894d6 100644
--- a/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll
+++ b/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll
@@ -21,10 +21,10 @@ define void @varargs_func(i32 %arg1, ...) {
 ; CHECK-LABEL: varargs_func:
 ; Reserve space for the varargs save area.  This currently reserves
 ; more than enough (16 bytes rather than the 12 bytes needed).
-; CHECK: sub sp, sp, #16
+; CHECK: sub sp, sp, #12
 ; CHECK: push {r11, lr}
 ; Align the stack pointer to a multiple of 16.
-; CHECK: sub sp, sp, #8
+; CHECK: sub sp, sp, #12
 ; Calculate the address of the varargs save area and save varargs
 ; arguments into it.
 ; CHECK-NEXT: add r0, sp, #20
diff --git a/test/CodeGen/ARM/vargs.ll b/test/CodeGen/ARM/vargs.ll
index 3b810f36cc79..41ec03857f08 100644
--- a/test/CodeGen/ARM/vargs.ll
+++ b/test/CodeGen/ARM/vargs.ll
@@ -4,8 +4,8 @@
 
 define i32 @main() {
 entry:
-        %tmp = call i32 (i8*, ...)* @printf( i8* getelementptr ([43 x i8]* @str, i32 0, i64 0), i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10 )         ; <i32> [#uses=0]
-        %tmp2 = call i32 (i8*, ...)* @printf( i8* getelementptr ([43 x i8]* @str, i32 0, i64 0), i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1 )                ; <i32> [#uses=0]
+        %tmp = call i32 (i8*, ...) @printf( i8* getelementptr ([43 x i8], [43 x i8]* @str, i32 0, i64 0), i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10 )         ; <i32> [#uses=0]
+        %tmp2 = call i32 (i8*, ...) @printf( i8* getelementptr ([43 x i8], [43 x i8]* @str, i32 0, i64 0), i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1 )                ; <i32> [#uses=0]
         ret i32 11
 }
 
diff --git a/test/CodeGen/ARM/vargs_align.ll b/test/CodeGen/ARM/vargs_align.ll
index 3abb57ee51f8..6dc71352214b 100644
--- a/test/CodeGen/ARM/vargs_align.ll
+++ b/test/CodeGen/ARM/vargs_align.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=EABI
+; RUN: llc < %s -mtriple=armv7-linux-gnueabihf | FileCheck %s -check-prefix=EABI
 ; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | FileCheck %s -check-prefix=OABI
 
 define i32 @f(i32 %a, ...) {
@@ -8,16 +8,20 @@ entry:
 	%tmp = alloca i32, align 4		; <i32*> [#uses=2]
 	store i32 %a, i32* %a_addr
 	store i32 0, i32* %tmp
-	%tmp1 = load i32* %tmp		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* %tmp		; <i32> [#uses=1]
 	store i32 %tmp1, i32* %retval
 	call void @llvm.va_start(i8* null)
+	call void asm sideeffect "", "~{d8}"()
 	br label %return
 
 return:		; preds = %entry
-	%retval2 = load i32* %retval		; <i32> [#uses=1]
+	%retval2 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval2
-; EABI: add sp, sp, #12
 ; EABI: add sp, sp, #16
+; EABI: vpop {d8}
+; EABI: add sp, sp, #4
+; EABI: add sp, sp, #12
+
 ; OABI: add sp, sp, #12
 ; OABI: add sp, sp, #12
 }
diff --git a/test/CodeGen/ARM/vbits.ll b/test/CodeGen/ARM/vbits.ll
index dfeaacf2085f..db9bc6ccdd0c 100644
--- a/test/CodeGen/ARM/vbits.ll
+++ b/test/CodeGen/ARM/vbits.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: v_andi8:
 ;CHECK: vand
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = and <8 x i8> %tmp1, %tmp2
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: v_andi16:
 ;CHECK: vand
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = and <4 x i16> %tmp1, %tmp2
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: v_andi32:
 ;CHECK: vand
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = and <2 x i32> %tmp1, %tmp2
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: v_andi64:
 ;CHECK: vand
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = and <1 x i64> %tmp1, %tmp2
 	ret <1 x i64> %tmp3
 }
@@ -39,8 +39,8 @@ define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: v_andQi8:
 ;CHECK: vand
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = and <16 x i8> %tmp1, %tmp2
 	ret <16 x i8> %tmp3
 }
@@ -48,8 +48,8 @@ define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: v_andQi16:
 ;CHECK: vand
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = and <8 x i16> %tmp1, %tmp2
 	ret <8 x i16> %tmp3
 }
@@ -57,8 +57,8 @@ define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: v_andQi32:
 ;CHECK: vand
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = and <4 x i32> %tmp1, %tmp2
 	ret <4 x i32> %tmp3
 }
@@ -66,8 +66,8 @@ define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: v_andQi64:
 ;CHECK: vand
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = and <2 x i64> %tmp1, %tmp2
 	ret <2 x i64> %tmp3
 }
@@ -75,8 +75,8 @@ define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: v_bici8:
 ;CHECK: vbic
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
 	%tmp4 = and <8 x i8> %tmp1, %tmp3
 	ret <8 x i8> %tmp4
@@ -85,8 +85,8 @@ define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: v_bici16:
 ;CHECK: vbic
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 >
 	%tmp4 = and <4 x i16> %tmp1, %tmp3
 	ret <4 x i16> %tmp4
@@ -95,8 +95,8 @@ define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: v_bici32:
 ;CHECK: vbic
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 >
 	%tmp4 = and <2 x i32> %tmp1, %tmp3
 	ret <2 x i32> %tmp4
@@ -105,8 +105,8 @@ define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: v_bici64:
 ;CHECK: vbic
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = xor <1 x i64> %tmp2, < i64 -1 >
 	%tmp4 = and <1 x i64> %tmp1, %tmp3
 	ret <1 x i64> %tmp4
@@ -115,8 +115,8 @@ define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: v_bicQi8:
 ;CHECK: vbic
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
 	%tmp4 = and <16 x i8> %tmp1, %tmp3
 	ret <16 x i8> %tmp4
@@ -125,8 +125,8 @@ define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: v_bicQi16:
 ;CHECK: vbic
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
 	%tmp4 = and <8 x i16> %tmp1, %tmp3
 	ret <8 x i16> %tmp4
@@ -135,8 +135,8 @@ define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: v_bicQi32:
 ;CHECK: vbic
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 >
 	%tmp4 = and <4 x i32> %tmp1, %tmp3
 	ret <4 x i32> %tmp4
@@ -145,8 +145,8 @@ define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: v_bicQi64:
 ;CHECK: vbic
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 >
 	%tmp4 = and <2 x i64> %tmp1, %tmp3
 	ret <2 x i64> %tmp4
@@ -155,8 +155,8 @@ define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: v_eori8:
 ;CHECK: veor
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = xor <8 x i8> %tmp1, %tmp2
 	ret <8 x i8> %tmp3
 }
@@ -164,8 +164,8 @@ define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: v_eori16:
 ;CHECK: veor
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = xor <4 x i16> %tmp1, %tmp2
 	ret <4 x i16> %tmp3
 }
@@ -173,8 +173,8 @@ define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: v_eori32:
 ;CHECK: veor
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = xor <2 x i32> %tmp1, %tmp2
 	ret <2 x i32> %tmp3
 }
@@ -182,8 +182,8 @@ define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: v_eori64:
 ;CHECK: veor
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = xor <1 x i64> %tmp1, %tmp2
 	ret <1 x i64> %tmp3
 }
@@ -191,8 +191,8 @@ define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: v_eorQi8:
 ;CHECK: veor
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = xor <16 x i8> %tmp1, %tmp2
 	ret <16 x i8> %tmp3
 }
@@ -200,8 +200,8 @@ define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: v_eorQi16:
 ;CHECK: veor
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = xor <8 x i16> %tmp1, %tmp2
 	ret <8 x i16> %tmp3
 }
@@ -209,8 +209,8 @@ define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: v_eorQi32:
 ;CHECK: veor
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = xor <4 x i32> %tmp1, %tmp2
 	ret <4 x i32> %tmp3
 }
@@ -218,8 +218,8 @@ define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: v_eorQi64:
 ;CHECK: veor
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = xor <2 x i64> %tmp1, %tmp2
 	ret <2 x i64> %tmp3
 }
@@ -227,7 +227,7 @@ define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: v_mvni8:
 ;CHECK: vmvn
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
 	ret <8 x i8> %tmp2
 }
@@ -235,7 +235,7 @@ define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind {
 define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: v_mvni16:
 ;CHECK: vmvn
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 >
 	ret <4 x i16> %tmp2
 }
@@ -243,7 +243,7 @@ define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind {
 define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: v_mvni32:
 ;CHECK: vmvn
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 >
 	ret <2 x i32> %tmp2
 }
@@ -251,7 +251,7 @@ define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind {
 define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind {
 ;CHECK-LABEL: v_mvni64:
 ;CHECK: vmvn
-	%tmp1 = load <1 x i64>* %A
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
 	%tmp2 = xor <1 x i64> %tmp1, < i64 -1 >
 	ret <1 x i64> %tmp2
 }
@@ -259,7 +259,7 @@ define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind {
 define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: v_mvnQi8:
 ;CHECK: vmvn
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
 	ret <16 x i8> %tmp2
 }
@@ -267,7 +267,7 @@ define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind {
 define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: v_mvnQi16:
 ;CHECK: vmvn
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
 	ret <8 x i16> %tmp2
 }
@@ -275,7 +275,7 @@ define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind {
 define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: v_mvnQi32:
 ;CHECK: vmvn
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 >
 	ret <4 x i32> %tmp2
 }
@@ -283,7 +283,7 @@ define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind {
 define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: v_mvnQi64:
 ;CHECK: vmvn
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 >
 	ret <2 x i64> %tmp2
 }
@@ -291,8 +291,8 @@ define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind {
 define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: v_orri8:
 ;CHECK: vorr
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = or <8 x i8> %tmp1, %tmp2
 	ret <8 x i8> %tmp3
 }
@@ -300,8 +300,8 @@ define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: v_orri16:
 ;CHECK: vorr
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = or <4 x i16> %tmp1, %tmp2
 	ret <4 x i16> %tmp3
 }
@@ -309,8 +309,8 @@ define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: v_orri32:
 ;CHECK: vorr
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = or <2 x i32> %tmp1, %tmp2
 	ret <2 x i32> %tmp3
 }
@@ -318,8 +318,8 @@ define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: v_orri64:
 ;CHECK: vorr
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = or <1 x i64> %tmp1, %tmp2
 	ret <1 x i64> %tmp3
 }
@@ -327,8 +327,8 @@ define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: v_orrQi8:
 ;CHECK: vorr
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = or <16 x i8> %tmp1, %tmp2
 	ret <16 x i8> %tmp3
 }
@@ -336,8 +336,8 @@ define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: v_orrQi16:
 ;CHECK: vorr
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = or <8 x i16> %tmp1, %tmp2
 	ret <8 x i16> %tmp3
 }
@@ -345,8 +345,8 @@ define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: v_orrQi32:
 ;CHECK: vorr
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = or <4 x i32> %tmp1, %tmp2
 	ret <4 x i32> %tmp3
 }
@@ -354,8 +354,8 @@ define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: v_orrQi64:
 ;CHECK: vorr
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = or <2 x i64> %tmp1, %tmp2
 	ret <2 x i64> %tmp3
 }
@@ -363,8 +363,8 @@ define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: v_orni8:
 ;CHECK: vorn
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
 	%tmp4 = or <8 x i8> %tmp1, %tmp3
 	ret <8 x i8> %tmp4
@@ -373,8 +373,8 @@ define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: v_orni16:
 ;CHECK: vorn
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 >
 	%tmp4 = or <4 x i16> %tmp1, %tmp3
 	ret <4 x i16> %tmp4
@@ -383,8 +383,8 @@ define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: v_orni32:
 ;CHECK: vorn
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 >
 	%tmp4 = or <2 x i32> %tmp1, %tmp3
 	ret <2 x i32> %tmp4
@@ -393,8 +393,8 @@ define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: v_orni64:
 ;CHECK: vorn
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = xor <1 x i64> %tmp2, < i64 -1 >
 	%tmp4 = or <1 x i64> %tmp1, %tmp3
 	ret <1 x i64> %tmp4
@@ -403,8 +403,8 @@ define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: v_ornQi8:
 ;CHECK: vorn
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
 	%tmp4 = or <16 x i8> %tmp1, %tmp3
 	ret <16 x i8> %tmp4
@@ -413,8 +413,8 @@ define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: v_ornQi16:
 ;CHECK: vorn
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
 	%tmp4 = or <8 x i16> %tmp1, %tmp3
 	ret <8 x i16> %tmp4
@@ -423,8 +423,8 @@ define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: v_ornQi32:
 ;CHECK: vorn
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 >
 	%tmp4 = or <4 x i32> %tmp1, %tmp3
 	ret <4 x i32> %tmp4
@@ -433,8 +433,8 @@ define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: v_ornQi64:
 ;CHECK: vorn
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 >
 	%tmp4 = or <2 x i64> %tmp1, %tmp3
 	ret <2 x i64> %tmp4
@@ -443,8 +443,8 @@ define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vtsti8:
 ;CHECK: vtst.8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = and <8 x i8> %tmp1, %tmp2
 	%tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
         %tmp5 = sext <8 x i1> %tmp4 to <8 x i8>
@@ -454,8 +454,8 @@ define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vtsti16:
 ;CHECK: vtst.16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = and <4 x i16> %tmp1, %tmp2
 	%tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer
         %tmp5 = sext <4 x i1> %tmp4 to <4 x i16>
@@ -465,8 +465,8 @@ define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vtsti32:
 ;CHECK: vtst.32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = and <2 x i32> %tmp1, %tmp2
 	%tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer
         %tmp5 = sext <2 x i1> %tmp4 to <2 x i32>
@@ -476,8 +476,8 @@ define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vtstQi8:
 ;CHECK: vtst.8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = and <16 x i8> %tmp1, %tmp2
 	%tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer
         %tmp5 = sext <16 x i1> %tmp4 to <16 x i8>
@@ -487,8 +487,8 @@ define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vtstQi16:
 ;CHECK: vtst.16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = and <8 x i16> %tmp1, %tmp2
 	%tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer
         %tmp5 = sext <8 x i1> %tmp4 to <8 x i16>
@@ -498,8 +498,8 @@ define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vtstQi32:
 ;CHECK: vtst.32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = and <4 x i32> %tmp1, %tmp2
 	%tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer
         %tmp5 = sext <4 x i1> %tmp4 to <4 x i32>
@@ -511,7 +511,7 @@ define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind {
 ; CHECK-NOT: vmov
 ; CHECK-NOT: vmvn
 ; CHECK: vorr
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
 	ret <8 x i8> %tmp3
 }
@@ -521,7 +521,7 @@ define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind {
 ; CHECK-NOT: vmov
 ; CHECK-NOT: vmvn
 ; CHECK: vorr
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
 	ret <16 x i8> %tmp3
 }
@@ -531,7 +531,7 @@ define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
 ; CHECK-NOT: vmov
 ; CHECK-NOT: vmvn
 ; CHECK: vbic
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
 	ret <8 x i8> %tmp3
 }
@@ -541,7 +541,7 @@ define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
 ; CHECK-NOT: vmov
 ; CHECK-NOT: vmvn
 ; CHECK: vbic
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
 	ret <16 x i8> %tmp3
 }
diff --git a/test/CodeGen/ARM/vbsl-constant.ll b/test/CodeGen/ARM/vbsl-constant.ll
index 5e033fe2a647..6bcbbc8fa878 100644
--- a/test/CodeGen/ARM/vbsl-constant.ll
+++ b/test/CodeGen/ARM/vbsl-constant.ll
@@ -5,9 +5,9 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ;CHECK: vldr
 ;CHECK: vldr
 ;CHECK: vbsl
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
-	%tmp3 = load <8 x i8>* %C
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
+	%tmp3 = load <8 x i8>, <8 x i8>* %C
 	%tmp4 = and <8 x i8> %tmp1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
 	%tmp6 = and <8 x i8> %tmp3, <i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4>
 	%tmp7 = or <8 x i8> %tmp4, %tmp6
@@ -19,9 +19,9 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 ;CHECK: vldr
 ;CHECK: vldr
 ;CHECK: vbsl
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
-	%tmp3 = load <4 x i16>* %C
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
+	%tmp3 = load <4 x i16>, <4 x i16>* %C
 	%tmp4 = and <4 x i16> %tmp1, <i16 3, i16 3, i16 3, i16 3>
 	%tmp6 = and <4 x i16> %tmp3, <i16 -4, i16 -4, i16 -4, i16 -4>
 	%tmp7 = or <4 x i16> %tmp4, %tmp6
@@ -33,9 +33,9 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 ;CHECK: vldr
 ;CHECK: vldr
 ;CHECK: vbsl
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
-	%tmp3 = load <2 x i32>* %C
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
+	%tmp3 = load <2 x i32>, <2 x i32>* %C
 	%tmp4 = and <2 x i32> %tmp1, <i32 3, i32 3>
 	%tmp6 = and <2 x i32> %tmp3, <i32 -4, i32 -4>
 	%tmp7 = or <2 x i32> %tmp4, %tmp6
@@ -48,9 +48,9 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind
 ;CHECK: vldr
 ;CHECK: vldr
 ;CHECK: vbsl
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
-	%tmp3 = load <1 x i64>* %C
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
+	%tmp3 = load <1 x i64>, <1 x i64>* %C
 	%tmp4 = and <1 x i64> %tmp1, <i64 3>
 	%tmp6 = and <1 x i64> %tmp3, <i64 -4>
 	%tmp7 = or <1 x i64> %tmp4, %tmp6
@@ -62,9 +62,9 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
 ;CHECK: vld1.32
 ;CHECK: vld1.32
 ;CHECK: vbsl
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
-	%tmp3 = load <16 x i8>* %C
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
+	%tmp3 = load <16 x i8>, <16 x i8>* %C
 	%tmp4 = and <16 x i8> %tmp1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
 	%tmp6 = and <16 x i8> %tmp3, <i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4>
 	%tmp7 = or <16 x i8> %tmp4, %tmp6
@@ -76,9 +76,9 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwin
 ;CHECK: vld1.32
 ;CHECK: vld1.32
 ;CHECK: vbsl
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
-	%tmp3 = load <8 x i16>* %C
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
+	%tmp3 = load <8 x i16>, <8 x i16>* %C
 	%tmp4 = and <8 x i16> %tmp1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
 	%tmp6 = and <8 x i16> %tmp3, <i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4>
 	%tmp7 = or <8 x i16> %tmp4, %tmp6
@@ -90,9 +90,9 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwin
 ;CHECK: vld1.32
 ;CHECK: vld1.32
 ;CHECK: vbsl
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
-	%tmp3 = load <4 x i32>* %C
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
+	%tmp3 = load <4 x i32>, <4 x i32>* %C
 	%tmp4 = and <4 x i32> %tmp1, <i32 3, i32 3, i32 3, i32 3>
 	%tmp6 = and <4 x i32> %tmp3, <i32 -4, i32 -4, i32 -4, i32 -4>
 	%tmp7 = or <4 x i32> %tmp4, %tmp6
@@ -105,9 +105,9 @@ define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwin
 ;CHECK: vld1.32
 ;CHECK: vld1.64
 ;CHECK: vbsl
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
-	%tmp3 = load <2 x i64>* %C
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
+	%tmp3 = load <2 x i64>, <2 x i64>* %C
 	%tmp4 = and <2 x i64> %tmp1, <i64 3, i64 3>
 	%tmp6 = and <2 x i64> %tmp3, <i64 -4, i64 -4>
 	%tmp7 = or <2 x i64> %tmp4, %tmp6
diff --git a/test/CodeGen/ARM/vbsl.ll b/test/CodeGen/ARM/vbsl.ll
index ddc37cc82441..6812dd90a100 100644
--- a/test/CodeGen/ARM/vbsl.ll
+++ b/test/CodeGen/ARM/vbsl.ll
@@ -5,9 +5,9 @@
 define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ;CHECK-LABEL: v_bsli8:
 ;CHECK: vbsl
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
-	%tmp3 = load <8 x i8>* %C
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
+	%tmp3 = load <8 x i8>, <8 x i8>* %C
 	%tmp4 = and <8 x i8> %tmp1, %tmp2
 	%tmp5 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
 	%tmp6 = and <8 x i8> %tmp5, %tmp3
@@ -18,9 +18,9 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK-LABEL: v_bsli16:
 ;CHECK: vbsl
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
-	%tmp3 = load <4 x i16>* %C
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
+	%tmp3 = load <4 x i16>, <4 x i16>* %C
 	%tmp4 = and <4 x i16> %tmp1, %tmp2
 	%tmp5 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 >
 	%tmp6 = and <4 x i16> %tmp5, %tmp3
@@ -31,9 +31,9 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK-LABEL: v_bsli32:
 ;CHECK: vbsl
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
-	%tmp3 = load <2 x i32>* %C
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
+	%tmp3 = load <2 x i32>, <2 x i32>* %C
 	%tmp4 = and <2 x i32> %tmp1, %tmp2
 	%tmp5 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 >
 	%tmp6 = and <2 x i32> %tmp5, %tmp3
@@ -44,9 +44,9 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
 ;CHECK-LABEL: v_bsli64:
 ;CHECK: vbsl
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
-	%tmp3 = load <1 x i64>* %C
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
+	%tmp3 = load <1 x i64>, <1 x i64>* %C
 	%tmp4 = and <1 x i64> %tmp1, %tmp2
 	%tmp5 = xor <1 x i64> %tmp1, < i64 -1 >
 	%tmp6 = and <1 x i64> %tmp5, %tmp3
@@ -57,9 +57,9 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind
 define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
 ;CHECK-LABEL: v_bslQi8:
 ;CHECK: vbsl
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
-	%tmp3 = load <16 x i8>* %C
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
+	%tmp3 = load <16 x i8>, <16 x i8>* %C
 	%tmp4 = and <16 x i8> %tmp1, %tmp2
 	%tmp5 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
 	%tmp6 = and <16 x i8> %tmp5, %tmp3
@@ -70,9 +70,9 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
 define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
 ;CHECK-LABEL: v_bslQi16:
 ;CHECK: vbsl
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
-	%tmp3 = load <8 x i16>* %C
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
+	%tmp3 = load <8 x i16>, <8 x i16>* %C
 	%tmp4 = and <8 x i16> %tmp1, %tmp2
 	%tmp5 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
 	%tmp6 = and <8 x i16> %tmp5, %tmp3
@@ -83,9 +83,9 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwin
 define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: v_bslQi32:
 ;CHECK: vbsl
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
-	%tmp3 = load <4 x i32>* %C
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
+	%tmp3 = load <4 x i32>, <4 x i32>* %C
 	%tmp4 = and <4 x i32> %tmp1, %tmp2
 	%tmp5 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 >
 	%tmp6 = and <4 x i32> %tmp5, %tmp3
@@ -96,9 +96,9 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwin
 define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
 ;CHECK-LABEL: v_bslQi64:
 ;CHECK: vbsl
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
-	%tmp3 = load <2 x i64>* %C
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
+	%tmp3 = load <2 x i64>, <2 x i64>* %C
 	%tmp4 = and <2 x i64> %tmp1, %tmp2
 	%tmp5 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 >
 	%tmp6 = and <2 x i64> %tmp5, %tmp3
diff --git a/test/CodeGen/ARM/vceq.ll b/test/CodeGen/ARM/vceq.ll
index e3202e402cc7..3772401a2f95 100644
--- a/test/CodeGen/ARM/vceq.ll
+++ b/test/CodeGen/ARM/vceq.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vceqi8:
 ;CHECK: vceq.i8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = icmp eq <8 x i8> %tmp1, %tmp2
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
 	ret <8 x i8> %tmp4
@@ -13,8 +13,8 @@ define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vceqi16:
 ;CHECK: vceq.i16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = icmp eq <4 x i16> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
 	ret <4 x i16> %tmp4
@@ -23,8 +23,8 @@ define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vceqi32:
 ;CHECK: vceq.i32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = icmp eq <2 x i32> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -33,8 +33,8 @@ define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vceqf32:
 ;CHECK: vceq.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fcmp oeq <2 x float> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -43,8 +43,8 @@ define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vceqQi8:
 ;CHECK: vceq.i8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = icmp eq <16 x i8> %tmp1, %tmp2
         %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
 	ret <16 x i8> %tmp4
@@ -53,8 +53,8 @@ define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vceqQi16:
 ;CHECK: vceq.i16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = icmp eq <8 x i16> %tmp1, %tmp2
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
 	ret <8 x i16> %tmp4
@@ -63,8 +63,8 @@ define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vceqQi32:
 ;CHECK: vceq.i32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = icmp eq <4 x i32> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
 	ret <4 x i32> %tmp4
@@ -73,8 +73,8 @@ define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vceqQf32:
 ;CHECK: vceq.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = fcmp oeq <4 x float> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
 	ret <4 x i32> %tmp4
@@ -85,7 +85,7 @@ define <8 x i8> @vceqi8Z(<8 x i8>* %A) nounwind {
 ;CHECK-NOT: vmov
 ;CHECK-NOT: vmvn
 ;CHECK: vceq.i8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp3 = icmp eq <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
 	ret <8 x i8> %tmp4
diff --git a/test/CodeGen/ARM/vcge.ll b/test/CodeGen/ARM/vcge.ll
index 3739f5ee8c51..2cd33cf3a422 100644
--- a/test/CodeGen/ARM/vcge.ll
+++ b/test/CodeGen/ARM/vcge.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vcges8:
 ;CHECK: vcge.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = icmp sge <8 x i8> %tmp1, %tmp2
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
 	ret <8 x i8> %tmp4
@@ -13,8 +13,8 @@ define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vcges16:
 ;CHECK: vcge.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = icmp sge <4 x i16> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
 	ret <4 x i16> %tmp4
@@ -23,8 +23,8 @@ define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vcges32:
 ;CHECK: vcge.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = icmp sge <2 x i32> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -33,8 +33,8 @@ define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vcgeu8:
 ;CHECK: vcge.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = icmp uge <8 x i8> %tmp1, %tmp2
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
 	ret <8 x i8> %tmp4
@@ -43,8 +43,8 @@ define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vcgeu16:
 ;CHECK: vcge.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = icmp uge <4 x i16> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
 	ret <4 x i16> %tmp4
@@ -53,8 +53,8 @@ define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vcgeu32:
 ;CHECK: vcge.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = icmp uge <2 x i32> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -63,8 +63,8 @@ define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vcgef32:
 ;CHECK: vcge.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fcmp oge <2 x float> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -73,8 +73,8 @@ define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vcgeQs8:
 ;CHECK: vcge.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = icmp sge <16 x i8> %tmp1, %tmp2
         %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
 	ret <16 x i8> %tmp4
@@ -83,8 +83,8 @@ define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vcgeQs16:
 ;CHECK: vcge.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = icmp sge <8 x i16> %tmp1, %tmp2
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
 	ret <8 x i16> %tmp4
@@ -93,8 +93,8 @@ define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vcgeQs32:
 ;CHECK: vcge.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = icmp sge <4 x i32> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
 	ret <4 x i32> %tmp4
@@ -103,8 +103,8 @@ define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vcgeQu8:
 ;CHECK: vcge.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = icmp uge <16 x i8> %tmp1, %tmp2
         %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
 	ret <16 x i8> %tmp4
@@ -113,8 +113,8 @@ define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vcgeQu16:
 ;CHECK: vcge.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = icmp uge <8 x i16> %tmp1, %tmp2
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
 	ret <8 x i16> %tmp4
@@ -123,8 +123,8 @@ define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vcgeQu32:
 ;CHECK: vcge.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = icmp uge <4 x i32> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
 	ret <4 x i32> %tmp4
@@ -133,8 +133,8 @@ define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vcgeQf32:
 ;CHECK: vcge.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = fcmp oge <4 x float> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
 	ret <4 x i32> %tmp4
@@ -143,8 +143,8 @@ define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vacgef32:
 ;CHECK: vacge.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -152,8 +152,8 @@ define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vacgeQf32:
 ;CHECK: vacge.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -166,7 +166,7 @@ define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind {
 ;CHECK-NOT: vmov
 ;CHECK-NOT: vmvn
 ;CHECK: vcge.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp3 = icmp sge <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
 	ret <8 x i8> %tmp4
@@ -177,7 +177,7 @@ define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind {
 ;CHECK-NOT: vmov
 ;CHECK-NOT: vmvn
 ;CHECK: vcle.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp3 = icmp sle <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
 	ret <8 x i8> %tmp4
diff --git a/test/CodeGen/ARM/vcgt.ll b/test/CodeGen/ARM/vcgt.ll
index 2f736f689ab1..c39c939d6c95 100644
--- a/test/CodeGen/ARM/vcgt.ll
+++ b/test/CodeGen/ARM/vcgt.ll
@@ -4,8 +4,8 @@
 define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vcgts8:
 ;CHECK: vcgt.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = icmp sgt <8 x i8> %tmp1, %tmp2
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
 	ret <8 x i8> %tmp4
@@ -14,8 +14,8 @@ define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vcgts16:
 ;CHECK: vcgt.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = icmp sgt <4 x i16> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
 	ret <4 x i16> %tmp4
@@ -24,8 +24,8 @@ define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vcgts32:
 ;CHECK: vcgt.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = icmp sgt <2 x i32> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -34,8 +34,8 @@ define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vcgtu8:
 ;CHECK: vcgt.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = icmp ugt <8 x i8> %tmp1, %tmp2
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
 	ret <8 x i8> %tmp4
@@ -44,8 +44,8 @@ define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vcgtu16:
 ;CHECK: vcgt.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = icmp ugt <4 x i16> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
 	ret <4 x i16> %tmp4
@@ -54,8 +54,8 @@ define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vcgtu32:
 ;CHECK: vcgt.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = icmp ugt <2 x i32> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -64,8 +64,8 @@ define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vcgtf32:
 ;CHECK: vcgt.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fcmp ogt <2 x float> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -74,8 +74,8 @@ define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vcgtQs8:
 ;CHECK: vcgt.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = icmp sgt <16 x i8> %tmp1, %tmp2
         %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
 	ret <16 x i8> %tmp4
@@ -84,8 +84,8 @@ define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vcgtQs16:
 ;CHECK: vcgt.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = icmp sgt <8 x i16> %tmp1, %tmp2
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
 	ret <8 x i16> %tmp4
@@ -94,8 +94,8 @@ define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vcgtQs32:
 ;CHECK: vcgt.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = icmp sgt <4 x i32> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
 	ret <4 x i32> %tmp4
@@ -104,8 +104,8 @@ define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vcgtQu8:
 ;CHECK: vcgt.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = icmp ugt <16 x i8> %tmp1, %tmp2
         %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
 	ret <16 x i8> %tmp4
@@ -114,8 +114,8 @@ define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vcgtQu16:
 ;CHECK: vcgt.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = icmp ugt <8 x i16> %tmp1, %tmp2
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
 	ret <8 x i16> %tmp4
@@ -124,8 +124,8 @@ define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vcgtQu32:
 ;CHECK: vcgt.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = icmp ugt <4 x i32> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
 	ret <4 x i32> %tmp4
@@ -134,8 +134,8 @@ define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vcgtQf32:
 ;CHECK: vcgt.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
 	ret <4 x i32> %tmp4
@@ -144,8 +144,8 @@ define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vacgtf32:
 ;CHECK: vacgt.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -153,8 +153,8 @@ define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vacgtQf32:
 ;CHECK: vacgt.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -165,8 +165,8 @@ define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK: vmov.i32 [[Q0:q[0-9]+]], #0x1
 ;CHECK: vcgt.f32 [[Q1:q[0-9]+]]
 ;CHECK: vand [[Q2:q[0-9]+]], [[Q1]], [[Q0]]
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2
         %tmp4 = zext <4 x i1> %tmp3 to <4 x i32>
 	ret <4 x i32> %tmp4
@@ -180,7 +180,7 @@ define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind {
 ;CHECK-NOT: vmov
 ;CHECK-NOT: vmvn
 ;CHECK: vcgt.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp3 = icmp sgt <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
 	ret <8 x i8> %tmp4
@@ -191,7 +191,7 @@ define <8 x i8> @vclti8Z(<8 x i8>* %A) nounwind {
 ;CHECK-NOT: vmov
 ;CHECK-NOT: vmvn
 ;CHECK: vclt.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp3 = icmp slt <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
 	ret <8 x i8> %tmp4
diff --git a/test/CodeGen/ARM/vcnt.ll b/test/CodeGen/ARM/vcnt.ll
index 390559b82807..de251c58e6b9 100644
--- a/test/CodeGen/ARM/vcnt.ll
+++ b/test/CodeGen/ARM/vcnt.ll
@@ -4,7 +4,7 @@
 define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vcnt8:
 ;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)
 	ret <8 x i8> %tmp2
 }
@@ -12,7 +12,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
 define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vcntQ8:
 ;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)
 	ret <16 x i8> %tmp2
 }
@@ -23,7 +23,7 @@ declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone
 define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vclz8:
 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
 	ret <8 x i8> %tmp2
 }
@@ -31,7 +31,7 @@ define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vclz16:
 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
 	ret <4 x i16> %tmp2
 }
@@ -39,7 +39,7 @@ define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vclz32:
 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
 	ret <2 x i32> %tmp2
 }
@@ -47,7 +47,7 @@ define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
 define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vclzQ8:
 ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
 	ret <16 x i8> %tmp2
 }
@@ -55,7 +55,7 @@ define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vclzQ16:
 ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
 	ret <8 x i16> %tmp2
 }
@@ -63,7 +63,7 @@ define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vclzQ32:
 ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
 	ret <4 x i32> %tmp2
 }
@@ -79,7 +79,7 @@ declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
 define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vclss8:
 ;CHECK: vcls.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
 	ret <8 x i8> %tmp2
 }
@@ -87,7 +87,7 @@ define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vclss16:
 ;CHECK: vcls.s16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
 	ret <4 x i16> %tmp2
 }
@@ -95,7 +95,7 @@ define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vclss32:
 ;CHECK: vcls.s32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
 	ret <2 x i32> %tmp2
 }
@@ -103,7 +103,7 @@ define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
 define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vclsQs8:
 ;CHECK: vcls.s8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
 	ret <16 x i8> %tmp2
 }
@@ -111,7 +111,7 @@ define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vclsQs16:
 ;CHECK: vcls.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
 	ret <8 x i16> %tmp2
 }
@@ -119,7 +119,7 @@ define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vclsQs32:
 ;CHECK: vcls.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
 	ret <4 x i32> %tmp2
 }
diff --git a/test/CodeGen/ARM/vcombine.ll b/test/CodeGen/ARM/vcombine.ll
index 33aa71df0be3..9491c15aef58 100644
--- a/test/CodeGen/ARM/vcombine.ll
+++ b/test/CodeGen/ARM/vcombine.ll
@@ -7,8 +7,8 @@ define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ; CHECK-LE: vmov r2, r3, d17
 ; CHECK-BE: vmov r1, r0, d16
 ; CHECK-BE: vmov r3, r2, d17
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
 	ret <16 x i8> %tmp3
 }
@@ -19,8 +19,8 @@ define <8 x i16> @vcombine16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ; CHECK-LE: vmov r2, r3, d17
 ; CHECK-BE: vmov r1, r0, d16
 ; CHECK-BE: vmov r3, r2, d17
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
 	ret <8 x i16> %tmp3
 }
@@ -31,8 +31,8 @@ define <4 x i32> @vcombine32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ; CHECK-LE: vmov r2, r3, d17
 ; CHECK-BE: vmov r1, r0, d16
 ; CHECK-BE: vmov r3, r2, d17
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
 	ret <4 x i32> %tmp3
 }
@@ -43,8 +43,8 @@ define <4 x float> @vcombinefloat(<2 x float>* %A, <2 x float>* %B) nounwind {
 ; CHECK-LE: vmov r2, r3, d17
 ; CHECK-BE: vmov r1, r0, d16
 ; CHECK-BE: vmov r3, r2, d17
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
 	ret <4 x float> %tmp3
 }
@@ -55,8 +55,8 @@ define <2 x i64> @vcombine64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ; CHECK-LE: vmov r2, r3, d17
 ; CHECK-BE: vmov r1, r0, d16
 ; CHECK-BE: vmov r3, r2, d17
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = shufflevector <1 x i64> %tmp1, <1 x i64> %tmp2, <2 x i32> <i32 0, i32 1>
 	ret <2 x i64> %tmp3
 }
@@ -69,7 +69,7 @@ define <4 x i16> @vget_low16(<8 x i16>* %A) nounwind {
 ; CHECK-NOT: vst
 ; CHECK-LE: vmov r0, r1, d16
 ; CHECK-BE: vmov r1, r0, d16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
         ret <4 x i16> %tmp2
 }
@@ -79,7 +79,7 @@ define <8 x i8> @vget_high8(<16 x i8>* %A) nounwind {
 ; CHECK-NOT: vst
 ; CHECK-LE: vmov r0, r1, d17
 ; CHECK-BE: vmov r1, r0, d16
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
         ret <8 x i8> %tmp2
 }
diff --git a/test/CodeGen/ARM/vcvt-cost.ll b/test/CodeGen/ARM/vcvt-cost.ll
index 5e56a5b34cf0..c80450a28400 100644
--- a/test/CodeGen/ARM/vcvt-cost.ll
+++ b/test/CodeGen/ARM/vcvt-cost.ll
@@ -9,7 +9,7 @@ define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
 ; CHECK: vmovl.s8
 ; CHECK: vmovl.s16
 ; CHECK: vmovl.s16
-  %v0 = load %T0_5* %loadaddr
+  %v0 = load %T0_5, %T0_5* %loadaddr
 ; COST: func_cvt5
 ; COST: cost of 3 {{.*}} sext
   %r = sext %T0_5 %v0 to %T1_5
@@ -25,7 +25,7 @@ define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) {
 ; CHECK: vmovl.u8
 ; CHECK: vmovl.u16
 ; CHECK: vmovl.u16
-  %v0 = load %TA0_5* %loadaddr
+  %v0 = load %TA0_5, %TA0_5* %loadaddr
 ; COST: func_cvt1
 ; COST: cost of 3 {{.*}} zext
   %r = zext %TA0_5 %v0 to %TA1_5
@@ -40,7 +40,7 @@ define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) {
 ; CHECK: vmovn.i32
 ; CHECK: vmovn.i32
 ; CHECK: vmovn.i16
-  %v0 = load %T0_51* %loadaddr
+  %v0 = load %T0_51, %T0_51* %loadaddr
 ; COST: func_cvt51
 ; COST: cost of 3 {{.*}} trunc
   %r = trunc %T0_51 %v0 to %T1_51
@@ -56,7 +56,7 @@ define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
 ; CHECK: vmovl.s16
 ; CHECK: vmovl.s16
 ; CHECK: vmovl.s16
-  %v0 = load %TT0_5* %loadaddr
+  %v0 = load %TT0_5, %TT0_5* %loadaddr
 ; COST: func_cvt52
 ; COST: cost of 6 {{.*}} sext
   %r = sext %TT0_5 %v0 to %TT1_5
@@ -73,7 +73,7 @@ define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) {
 ; CHECK: vmovl.u16
 ; CHECK: vmovl.u16
 ; CHECK: vmovl.u16
-  %v0 = load %TTA0_5* %loadaddr
+  %v0 = load %TTA0_5, %TTA0_5* %loadaddr
 ; COST: func_cvt12
 ; COST: cost of 6 {{.*}} zext
   %r = zext %TTA0_5 %v0 to %TTA1_5
@@ -91,7 +91,7 @@ define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) {
 ; CHECK: vmovn.i32
 ; CHECK: vmovn.i16
 ; CHECK: vmovn.i16
-  %v0 = load %TT0_51* %loadaddr
+  %v0 = load %TT0_51, %TT0_51* %loadaddr
 ; COST: func_cvt512
 ; COST: cost of 6 {{.*}} trunc
   %r = trunc %TT0_51 %v0 to %TT1_51
@@ -103,7 +103,7 @@ define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) {
 define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
 ; CHECK: vmovl.s32
 ; CHECK: vmovl.s32
-  %v0 = load <4 x i16>* %loadaddr
+  %v0 = load <4 x i16>, <4 x i16>* %loadaddr
 ; COST: sext_v4i16_v4i64
 ; COST: cost of 3 {{.*}} sext
   %r = sext <4 x i16> %v0 to <4 x i64>
@@ -115,7 +115,7 @@ define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
 define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
 ; CHECK: vmovl.u32
 ; CHECK: vmovl.u32
-  %v0 = load <4 x i16>* %loadaddr
+  %v0 = load <4 x i16>, <4 x i16>* %loadaddr
 ; COST: zext_v4i16_v4i64
 ; COST: cost of 3 {{.*}} zext
   %r = zext <4 x i16> %v0 to <4 x i64>
@@ -129,7 +129,7 @@ define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
 ; CHECK: vmovl.s32
 ; CHECK: vmovl.s32
 ; CHECK: vmovl.s32
-  %v0 = load <8 x i16>* %loadaddr
+  %v0 = load <8 x i16>, <8 x i16>* %loadaddr
 ; COST: sext_v8i16_v8i64
 ; COST: cost of 6 {{.*}} sext
   %r = sext <8 x i16> %v0 to <8 x i64>
@@ -143,7 +143,7 @@ define void @zext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
 ; CHECK: vmovl.u32
 ; CHECK: vmovl.u32
 ; CHECK: vmovl.u32
-  %v0 = load <8 x i16>* %loadaddr
+  %v0 = load <8 x i16>, <8 x i16>* %loadaddr
 ; COST: zext_v8i16_v8i64
 ; COST: cost of 6 {{.*}} zext
   %r = zext <8 x i16> %v0 to <8 x i64>
diff --git a/test/CodeGen/ARM/vcvt-v8.ll b/test/CodeGen/ARM/vcvt-v8.ll
index c449009e1e1f..9d5972fa4da5 100644
--- a/test/CodeGen/ARM/vcvt-v8.ll
+++ b/test/CodeGen/ARM/vcvt-v8.ll
@@ -2,7 +2,7 @@
 define <4 x i32> @vcvtasq(<4 x float>* %A) {
 ; CHECK: vcvtasq
 ; CHECK: vcvta.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
-  %tmp1 = load <4 x float>* %A
+  %tmp1 = load <4 x float>, <4 x float>* %A
   %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %tmp1)
   ret <4 x i32> %tmp2
 }
@@ -10,7 +10,7 @@ define <4 x i32> @vcvtasq(<4 x float>* %A) {
 define <2 x i32> @vcvtasd(<2 x float>* %A) {
 ; CHECK: vcvtasd
 ; CHECK: vcvta.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
-  %tmp1 = load <2 x float>* %A
+  %tmp1 = load <2 x float>, <2 x float>* %A
   %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %tmp1)
   ret <2 x i32> %tmp2
 }
@@ -18,7 +18,7 @@ define <2 x i32> @vcvtasd(<2 x float>* %A) {
 define <4 x i32> @vcvtnsq(<4 x float>* %A) {
 ; CHECK: vcvtnsq
 ; CHECK: vcvtn.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
-  %tmp1 = load <4 x float>* %A
+  %tmp1 = load <4 x float>, <4 x float>* %A
   %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %tmp1)
   ret <4 x i32> %tmp2
 }
@@ -26,7 +26,7 @@ define <4 x i32> @vcvtnsq(<4 x float>* %A) {
 define <2 x i32> @vcvtnsd(<2 x float>* %A) {
 ; CHECK: vcvtnsd
 ; CHECK: vcvtn.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
-  %tmp1 = load <2 x float>* %A
+  %tmp1 = load <2 x float>, <2 x float>* %A
   %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %tmp1)
   ret <2 x i32> %tmp2
 }
@@ -34,7 +34,7 @@ define <2 x i32> @vcvtnsd(<2 x float>* %A) {
 define <4 x i32> @vcvtpsq(<4 x float>* %A) {
 ; CHECK: vcvtpsq
 ; CHECK: vcvtp.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
-  %tmp1 = load <4 x float>* %A
+  %tmp1 = load <4 x float>, <4 x float>* %A
   %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %tmp1)
   ret <4 x i32> %tmp2
 }
@@ -42,7 +42,7 @@ define <4 x i32> @vcvtpsq(<4 x float>* %A) {
 define <2 x i32> @vcvtpsd(<2 x float>* %A) {
 ; CHECK: vcvtpsd
 ; CHECK: vcvtp.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
-  %tmp1 = load <2 x float>* %A
+  %tmp1 = load <2 x float>, <2 x float>* %A
   %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %tmp1)
   ret <2 x i32> %tmp2
 }
@@ -50,7 +50,7 @@ define <2 x i32> @vcvtpsd(<2 x float>* %A) {
 define <4 x i32> @vcvtmsq(<4 x float>* %A) {
 ; CHECK: vcvtmsq
 ; CHECK: vcvtm.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
-  %tmp1 = load <4 x float>* %A
+  %tmp1 = load <4 x float>, <4 x float>* %A
   %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float> %tmp1)
   ret <4 x i32> %tmp2
 }
@@ -58,7 +58,7 @@ define <4 x i32> @vcvtmsq(<4 x float>* %A) {
 define <2 x i32> @vcvtmsd(<2 x float>* %A) {
 ; CHECK: vcvtmsd
 ; CHECK: vcvtm.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
-  %tmp1 = load <2 x float>* %A
+  %tmp1 = load <2 x float>, <2 x float>* %A
   %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float> %tmp1)
   ret <2 x i32> %tmp2
 }
@@ -66,7 +66,7 @@ define <2 x i32> @vcvtmsd(<2 x float>* %A) {
 define <4 x i32> @vcvtauq(<4 x float>* %A) {
 ; CHECK: vcvtauq
 ; CHECK: vcvta.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
-  %tmp1 = load <4 x float>* %A
+  %tmp1 = load <4 x float>, <4 x float>* %A
   %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %tmp1)
   ret <4 x i32> %tmp2
 }
@@ -74,7 +74,7 @@ define <4 x i32> @vcvtauq(<4 x float>* %A) {
 define <2 x i32> @vcvtaud(<2 x float>* %A) {
 ; CHECK: vcvtaud
 ; CHECK: vcvta.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
-  %tmp1 = load <2 x float>* %A
+  %tmp1 = load <2 x float>, <2 x float>* %A
   %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %tmp1)
   ret <2 x i32> %tmp2
 }
@@ -82,7 +82,7 @@ define <2 x i32> @vcvtaud(<2 x float>* %A) {
 define <4 x i32> @vcvtnuq(<4 x float>* %A) {
 ; CHECK: vcvtnuq
 ; CHECK: vcvtn.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
-  %tmp1 = load <4 x float>* %A
+  %tmp1 = load <4 x float>, <4 x float>* %A
   %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %tmp1)
   ret <4 x i32> %tmp2
 }
@@ -90,7 +90,7 @@ define <4 x i32> @vcvtnuq(<4 x float>* %A) {
 define <2 x i32> @vcvtnud(<2 x float>* %A) {
 ; CHECK: vcvtnud
 ; CHECK: vcvtn.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
-  %tmp1 = load <2 x float>* %A
+  %tmp1 = load <2 x float>, <2 x float>* %A
   %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %tmp1)
   ret <2 x i32> %tmp2
 }
@@ -98,7 +98,7 @@ define <2 x i32> @vcvtnud(<2 x float>* %A) {
 define <4 x i32> @vcvtpuq(<4 x float>* %A) {
 ; CHECK: vcvtpuq
 ; CHECK: vcvtp.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
-  %tmp1 = load <4 x float>* %A
+  %tmp1 = load <4 x float>, <4 x float>* %A
   %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %tmp1)
   ret <4 x i32> %tmp2
 }
@@ -106,7 +106,7 @@ define <4 x i32> @vcvtpuq(<4 x float>* %A) {
 define <2 x i32> @vcvtpud(<2 x float>* %A) {
 ; CHECK: vcvtpud
 ; CHECK: vcvtp.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
-  %tmp1 = load <2 x float>* %A
+  %tmp1 = load <2 x float>, <2 x float>* %A
   %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %tmp1)
   ret <2 x i32> %tmp2
 }
@@ -114,7 +114,7 @@ define <2 x i32> @vcvtpud(<2 x float>* %A) {
 define <4 x i32> @vcvtmuq(<4 x float>* %A) {
 ; CHECK: vcvtmuq
 ; CHECK: vcvtm.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
-  %tmp1 = load <4 x float>* %A
+  %tmp1 = load <4 x float>, <4 x float>* %A
   %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float> %tmp1)
   ret <4 x i32> %tmp2
 }
@@ -122,7 +122,7 @@ define <4 x i32> @vcvtmuq(<4 x float>* %A) {
 define <2 x i32> @vcvtmud(<2 x float>* %A) {
 ; CHECK: vcvtmud
 ; CHECK: vcvtm.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
-  %tmp1 = load <2 x float>* %A
+  %tmp1 = load <2 x float>, <2 x float>* %A
   %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtmu.v2i32.v2f32(<2 x float> %tmp1)
   ret <2 x i32> %tmp2
 }
diff --git a/test/CodeGen/ARM/vcvt.ll b/test/CodeGen/ARM/vcvt.ll
index af4e6a3b0465..78105f7e0ad1 100644
--- a/test/CodeGen/ARM/vcvt.ll
+++ b/test/CodeGen/ARM/vcvt.ll
@@ -3,7 +3,7 @@
 define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvt_f32tos32:
 ;CHECK: vcvt.s32.f32
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp2 = fptosi <2 x float> %tmp1 to <2 x i32>
 	ret <2 x i32> %tmp2
 }
@@ -11,7 +11,7 @@ define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
 define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvt_f32tou32:
 ;CHECK: vcvt.u32.f32
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp2 = fptoui <2 x float> %tmp1 to <2 x i32>
 	ret <2 x i32> %tmp2
 }
@@ -19,7 +19,7 @@ define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
 define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvt_s32tof32:
 ;CHECK: vcvt.f32.s32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = sitofp <2 x i32> %tmp1 to <2 x float>
 	ret <2 x float> %tmp2
 }
@@ -27,7 +27,7 @@ define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
 define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvt_u32tof32:
 ;CHECK: vcvt.f32.u32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = uitofp <2 x i32> %tmp1 to <2 x float>
 	ret <2 x float> %tmp2
 }
@@ -35,7 +35,7 @@ define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
 define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_f32tos32:
 ;CHECK: vcvt.s32.f32
-	%tmp1 = load <4 x float>* %A
+	%tmp1 = load <4 x float>, <4 x float>* %A
 	%tmp2 = fptosi <4 x float> %tmp1 to <4 x i32>
 	ret <4 x i32> %tmp2
 }
@@ -43,7 +43,7 @@ define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
 define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_f32tou32:
 ;CHECK: vcvt.u32.f32
-	%tmp1 = load <4 x float>* %A
+	%tmp1 = load <4 x float>, <4 x float>* %A
 	%tmp2 = fptoui <4 x float> %tmp1 to <4 x i32>
 	ret <4 x i32> %tmp2
 }
@@ -51,7 +51,7 @@ define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
 define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_s32tof32:
 ;CHECK: vcvt.f32.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = sitofp <4 x i32> %tmp1 to <4 x float>
 	ret <4 x float> %tmp2
 }
@@ -59,7 +59,7 @@ define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
 define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_u32tof32:
 ;CHECK: vcvt.f32.u32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = uitofp <4 x i32> %tmp1 to <4 x float>
 	ret <4 x float> %tmp2
 }
@@ -67,7 +67,7 @@ define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
 define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvt_n_f32tos32:
 ;CHECK: vcvt.s32.f32
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
 	ret <2 x i32> %tmp2
 }
@@ -75,7 +75,7 @@ define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
 define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvt_n_f32tou32:
 ;CHECK: vcvt.u32.f32
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
 	ret <2 x i32> %tmp2
 }
@@ -83,7 +83,7 @@ define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
 define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvt_n_s32tof32:
 ;CHECK: vcvt.f32.s32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
 	ret <2 x float> %tmp2
 }
@@ -91,7 +91,7 @@ define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
 define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvt_n_u32tof32:
 ;CHECK: vcvt.f32.u32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
 	ret <2 x float> %tmp2
 }
@@ -104,7 +104,7 @@ declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwi
 define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_n_f32tos32:
 ;CHECK: vcvt.s32.f32
-	%tmp1 = load <4 x float>* %A
+	%tmp1 = load <4 x float>, <4 x float>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
 	ret <4 x i32> %tmp2
 }
@@ -112,7 +112,7 @@ define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
 define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_n_f32tou32:
 ;CHECK: vcvt.u32.f32
-	%tmp1 = load <4 x float>* %A
+	%tmp1 = load <4 x float>, <4 x float>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
 	ret <4 x i32> %tmp2
 }
@@ -120,7 +120,7 @@ define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
 define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_n_s32tof32:
 ;CHECK: vcvt.f32.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
 	ret <4 x float> %tmp2
 }
@@ -128,7 +128,7 @@ define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
 define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_n_u32tof32:
 ;CHECK: vcvt.f32.u32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
 	ret <4 x float> %tmp2
 }
@@ -141,7 +141,7 @@ declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwi
 define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vcvt_f16tof32:
 ;CHECK: vcvt.f32.f16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %tmp1)
 	ret <4 x float> %tmp2
 }
@@ -149,7 +149,7 @@ define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind {
 define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvt_f32tof16:
 ;CHECK: vcvt.f16.f32
-	%tmp1 = load <4 x float>* %A
+	%tmp1 = load <4 x float>, <4 x float>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %tmp1)
 	ret <4 x i16> %tmp2
 }
@@ -180,8 +180,8 @@ define <2 x i64> @fix_float_to_i64(<2 x float> %in) {
 
 define <4 x i16> @fix_double_to_i16(<4 x double> %in) {
 ; CHECK-LABEL: fix_double_to_i16:
-; CHECK: vcvt.s32.f64
-; CHECK: vcvt.s32.f64
+; CHECK: vcvt.u32.f64
+; CHECK: vcvt.u32.f64
 
   %scale = fmul <4 x double> %in, <double 2.0, double 2.0, double 2.0, double 2.0>
   %conv = fptoui <4 x double> %scale to <4 x i16>
diff --git a/test/CodeGen/ARM/vcvt_combine.ll b/test/CodeGen/ARM/vcvt_combine.ll
index 07ba230757be..0c856e8d7617 100644
--- a/test/CodeGen/ARM/vcvt_combine.ll
+++ b/test/CodeGen/ARM/vcvt_combine.ll
@@ -7,7 +7,7 @@
 ; CHECK-NOT: vmul
 define void @t0() nounwind {
 entry:
-  %tmp = load float* @in, align 4
+  %tmp = load float, float* @in, align 4
   %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
   %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
   %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00>
@@ -23,7 +23,7 @@ declare void @foo_int32x2_t(<2 x i32>)
 ; CHECK-NOT: vmul
 define void @t1() nounwind {
 entry:
-  %tmp = load float* @in, align 4
+  %tmp = load float, float* @in, align 4
   %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
   %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
   %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00>
@@ -39,7 +39,7 @@ declare void @foo_uint32x2_t(<2 x i32>)
 ; CHECK: vmul
 define void @t2() nounwind {
 entry:
-  %tmp = load float* @in, align 4
+  %tmp = load float, float* @in, align 4
   %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
   %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
   %mul.i = fmul <2 x float> %vecinit2.i, <float 0x401B333340000000, float 0x401B333340000000>
@@ -53,7 +53,7 @@ entry:
 ; CHECK: vmul
 define void @t3() nounwind {
 entry:
-  %tmp = load float* @in, align 4
+  %tmp = load float, float* @in, align 4
   %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
   %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
   %mul.i = fmul <2 x float> %vecinit2.i, <float 0x4200000000000000, float 0x4200000000000000>
@@ -67,7 +67,7 @@ entry:
 ; CHECK-NOT: vmul
 define void @t4() nounwind {
 entry:
-  %tmp = load float* @in, align 4
+  %tmp = load float, float* @in, align 4
   %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
   %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
   %mul.i = fmul <2 x float> %vecinit2.i, <float 0x41F0000000000000, float 0x41F0000000000000>
@@ -81,7 +81,7 @@ entry:
 ; CHECK-NOT: vmul
 define void @t5() nounwind {
 entry:
-  %tmp = load float* @in, align 4
+  %tmp = load float, float* @in, align 4
   %vecinit.i = insertelement <4 x float> undef, float %tmp, i32 0
   %vecinit2.i = insertelement <4 x float> %vecinit.i, float %tmp, i32 1
   %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %tmp, i32 2
diff --git a/test/CodeGen/ARM/vdiv_combine.ll b/test/CodeGen/ARM/vdiv_combine.ll
index 96807f7280f8..8c6e4ba35054 100644
--- a/test/CodeGen/ARM/vdiv_combine.ll
+++ b/test/CodeGen/ARM/vdiv_combine.ll
@@ -11,7 +11,7 @@ declare void @foo_int32x4_t(<4 x i32>)
 ; CHECK-NOT: {{vdiv|vmul}}
 define void @t1() nounwind {
 entry:
-  %tmp = load i32* @iin, align 4
+  %tmp = load i32, i32* @iin, align 4
   %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
   %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
   %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
@@ -27,7 +27,7 @@ declare void @foo_float32x2_t(<2 x float>)
 ; CHECK-NOT: {{vdiv|vmul}}
 define void @t2() nounwind {
 entry:
-  %tmp = load i32* @uin, align 4
+  %tmp = load i32, i32* @uin, align 4
   %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
   %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
   %vcvt.i = uitofp <2 x i32> %vecinit2.i to <2 x float>
@@ -41,7 +41,7 @@ entry:
 ; CHECK: {{vdiv|vmul}}
 define void @t3() nounwind {
 entry:
-  %tmp = load i32* @iin, align 4
+  %tmp = load i32, i32* @iin, align 4
   %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
   %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
   %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
@@ -55,7 +55,7 @@ entry:
 ; CHECK: {{vdiv|vmul}}
 define void @t4() nounwind {
 entry:
-  %tmp = load i32* @iin, align 4
+  %tmp = load i32, i32* @iin, align 4
   %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
   %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
   %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
@@ -69,7 +69,7 @@ entry:
 ; CHECK-NOT: {{vdiv|vmul}}
 define void @t5() nounwind {
 entry:
-  %tmp = load i32* @iin, align 4
+  %tmp = load i32, i32* @iin, align 4
   %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
   %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
   %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
@@ -83,7 +83,7 @@ entry:
 ; CHECK-NOT: {{vdiv|vmul}}
 define void @t6() nounwind {
 entry:
-  %tmp = load i32* @iin, align 4
+  %tmp = load i32, i32* @iin, align 4
   %vecinit.i = insertelement <4 x i32> undef, i32 %tmp, i32 0
   %vecinit2.i = insertelement <4 x i32> %vecinit.i, i32 %tmp, i32 1
   %vecinit4.i = insertelement <4 x i32> %vecinit2.i, i32 %tmp, i32 2
diff --git a/test/CodeGen/ARM/vdup.ll b/test/CodeGen/ARM/vdup.ll
index 89f355c68751..36eebbfc4650 100644
--- a/test/CodeGen/ARM/vdup.ll
+++ b/test/CodeGen/ARM/vdup.ll
@@ -166,7 +166,7 @@ define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
 define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vduplane8:
 ;CHECK: vdup.8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
 	ret <8 x i8> %tmp2
 }
@@ -174,7 +174,7 @@ define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vduplane16:
 ;CHECK: vdup.16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
 	ret <4 x i16> %tmp2
 }
@@ -182,7 +182,7 @@ define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vduplane32:
 ;CHECK: vdup.32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
 	ret <2 x i32> %tmp2
 }
@@ -190,7 +190,7 @@ define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
 define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vduplanefloat:
 ;CHECK: vdup.32
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 >
 	ret <2 x float> %tmp2
 }
@@ -198,7 +198,7 @@ define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
 define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vduplaneQ8:
 ;CHECK: vdup.8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
 	ret <16 x i8> %tmp2
 }
@@ -206,7 +206,7 @@ define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
 define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vduplaneQ16:
 ;CHECK: vdup.16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
 	ret <8 x i16> %tmp2
 }
@@ -214,7 +214,7 @@ define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
 define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vduplaneQ32:
 ;CHECK: vdup.32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
 	ret <4 x i32> %tmp2
 }
@@ -222,7 +222,7 @@ define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
 define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vduplaneQfloat:
 ;CHECK: vdup.32
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
 	ret <4 x float> %tmp2
 }
@@ -347,17 +347,17 @@ define <2 x float> @check_spr_splat2(<2 x float> %p, i16 %q) {
 
 define <4 x float> @check_spr_splat4(<4 x float> %p, i16 %q) {
 ;CHECK-LABEL: check_spr_splat4:
-;CHECK: vdup.32 q
+;CHECK: vld1.16
   %conv = sitofp i16 %q to float
   %splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 0
   %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
   %sub = fsub <4 x float> %splat.splat, %p
   ret <4 x float> %sub
 }
-
+; Same codegen as above test; scalar is splatted using vld1, so shuffle index is irrelevant.
 define <4 x float> @check_spr_splat4_lane1(<4 x float> %p, i16 %q) {
 ;CHECK-LABEL: check_spr_splat4_lane1:
-;CHECK: vdup.32 q{{.*}}, d{{.*}}[1]
+;CHECK: vld1.16
   %conv = sitofp i16 %q to float
   %splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 1
   %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
diff --git a/test/CodeGen/ARM/vector-DAGCombine.ll b/test/CodeGen/ARM/vector-DAGCombine.ll
index 759da2235e41..29f4bb972a24 100644
--- a/test/CodeGen/ARM/vector-DAGCombine.ll
+++ b/test/CodeGen/ARM/vector-DAGCombine.ll
@@ -21,12 +21,20 @@ bb.i19:                                           ; preds = %bb.i19, %bb3
 define void @test_illegal_build_vector() nounwind {
 entry:
   store <2 x i64> undef, <2 x i64>* undef, align 16
-  %0 = load <16 x i8>* undef, align 16            ; <<16 x i8>> [#uses=1]
+  %0 = load <16 x i8>, <16 x i8>* undef, align 16            ; <<16 x i8>> [#uses=1]
   %1 = or <16 x i8> zeroinitializer, %0           ; <<16 x i8>> [#uses=1]
   store <16 x i8> %1, <16 x i8>* undef, align 16
   ret void
 }
 
+; PR22678
+; Check CONCAT_VECTORS DAG combiner pass doesn't introduce illegal types.
+define void @test_pr22678() {
+  %1 = fptoui <16 x float> undef to <16 x i8>
+  store <16 x i8> %1, <16 x i8>* undef
+  ret void
+}
+
 ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
 ; converted back to be used as a vector type.
 ; CHECK-LABEL: test_vmovrrd_combine:
@@ -55,7 +63,7 @@ bb2:
 ; Test trying to do a ShiftCombine on illegal types.
 ; The vector should be split first.
 define void @lshrIllegalType(<8 x i32>* %A) nounwind {
-       %tmp1 = load <8 x i32>* %A
+       %tmp1 = load <8 x i32>, <8 x i32>* %A
        %tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
        store <8 x i32> %tmp2, <8 x i32>* %A
        ret void
@@ -81,7 +89,7 @@ declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind
 define void @i64_buildvector(i64* %ptr, <2 x i64>* %vp) nounwind {
 ; CHECK: i64_buildvector
 ; CHECK: vldr
-  %t0 = load i64* %ptr, align 4
+  %t0 = load i64, i64* %ptr, align 4
   %t1 = insertelement <2 x i64> undef, i64 %t0, i32 0
   store <2 x i64> %t1, <2 x i64>* %vp
   ret void
@@ -90,8 +98,8 @@ define void @i64_buildvector(i64* %ptr, <2 x i64>* %vp) nounwind {
 define void @i64_insertelement(i64* %ptr, <2 x i64>* %vp) nounwind {
 ; CHECK: i64_insertelement
 ; CHECK: vldr
-  %t0 = load i64* %ptr, align 4
-  %vec = load <2 x i64>* %vp
+  %t0 = load i64, i64* %ptr, align 4
+  %vec = load <2 x i64>, <2 x i64>* %vp
   %t1 = insertelement <2 x i64> %vec, i64 %t0, i32 0
   store <2 x i64> %t1, <2 x i64>* %vp
   ret void
@@ -100,7 +108,7 @@ define void @i64_insertelement(i64* %ptr, <2 x i64>* %vp) nounwind {
 define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind {
 ; CHECK: i64_extractelement
 ; CHECK: vstr
-  %vec = load <2 x i64>* %vp
+  %vec = load <2 x i64>, <2 x i64>* %vp
   %t1 = extractelement <2 x i64> %vec, i32 0
   store i64 %t1, i64* %ptr
   ret void
@@ -108,7 +116,7 @@ define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind {
 
 ; Test trying to do a AND Combine on illegal types.
 define void @andVec(<3 x i8>* %A) nounwind {
-  %tmp = load <3 x i8>* %A, align 4
+  %tmp = load <3 x i8>, <3 x i8>* %A, align 4
   %and = and <3 x i8> %tmp, <i8 7, i8 7, i8 7>
   store <3 x i8> %and, <3 x i8>* %A
   ret void
@@ -117,7 +125,7 @@ define void @andVec(<3 x i8>* %A) nounwind {
 
 ; Test trying to do an OR Combine on illegal types.
 define void @orVec(<3 x i8>* %A) nounwind {
-  %tmp = load <3 x i8>* %A, align 4
+  %tmp = load <3 x i8>, <3 x i8>* %A, align 4
   %or = or <3 x i8> %tmp, <i8 7, i8 7, i8 7>
   store <3 x i8> %or, <3 x i8>* %A
   ret void
@@ -138,7 +146,7 @@ define i16 @foldBuildVectors() {
 ; shuffles.
 ; CHECK-LABEL: reverse_v8i16:
 define void @reverse_v8i16(<8 x i16>* %loadaddr, <8 x i16>* %storeaddr) {
-  %v0 = load <8 x i16>* %loadaddr
+  %v0 = load <8 x i16>, <8 x i16>* %loadaddr
   ; CHECK: vrev64.16
   ; CHECK: vext.16
   %v1 = shufflevector <8 x i16> %v0, <8 x i16> undef,
@@ -151,7 +159,7 @@ define void @reverse_v8i16(<8 x i16>* %loadaddr, <8 x i16>* %storeaddr) {
 ; shuffles.
 ; CHECK-LABEL: reverse_v16i8:
 define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) {
-  %v0 = load <16 x i8>* %loadaddr
+  %v0 = load <16 x i8>, <16 x i8>* %loadaddr
   ; CHECK: vrev64.8
   ; CHECK: vext.8
   %v1 = shufflevector <16 x i8> %v0, <16 x i8> undef,
@@ -172,9 +180,9 @@ define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) {
 define <8 x i16> @t3(i8 zeroext %xf, i8* nocapture %sp0, i8* nocapture %sp1, i32* nocapture %outp) {
 entry:
   %pix_sp0.0.cast = bitcast i8* %sp0 to i32*
-  %pix_sp0.0.copyload = load i32* %pix_sp0.0.cast, align 1
+  %pix_sp0.0.copyload = load i32, i32* %pix_sp0.0.cast, align 1
   %pix_sp1.0.cast = bitcast i8* %sp1 to i32*
-  %pix_sp1.0.copyload = load i32* %pix_sp1.0.cast, align 1
+  %pix_sp1.0.copyload = load i32, i32* %pix_sp1.0.cast, align 1
   %vecinit = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
   %vecinit1 = insertelement <2 x i32> %vecinit, i32 %pix_sp1.0.copyload, i32 1
   %0 = bitcast <2 x i32> %vecinit1 to <8 x i8>
@@ -192,7 +200,7 @@ define <8 x i16> @t4(i8* nocapture %sp0) {
 ; CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r0]
 entry:
   %pix_sp0.0.cast = bitcast i8* %sp0 to i32*
-  %pix_sp0.0.copyload = load i32* %pix_sp0.0.cast, align 1
+  %pix_sp0.0.copyload = load i32, i32* %pix_sp0.0.cast, align 1
   %vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
   %0 = bitcast <2 x i32> %vec to <8 x i8>
   %vmull.i = tail call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %0, <8 x i8> %0)
@@ -211,11 +219,11 @@ entry:
 define <8 x i16> @t5(i8* nocapture %sp0, i8* nocapture %sp1, i8* nocapture %sp2) {
 entry:
   %pix_sp0.0.cast = bitcast i8* %sp0 to i32*
-  %pix_sp0.0.copyload = load i32* %pix_sp0.0.cast, align 1
+  %pix_sp0.0.copyload = load i32, i32* %pix_sp0.0.cast, align 1
   %pix_sp1.0.cast = bitcast i8* %sp1 to i32*
-  %pix_sp1.0.copyload = load i32* %pix_sp1.0.cast, align 1
+  %pix_sp1.0.copyload = load i32, i32* %pix_sp1.0.cast, align 1
   %pix_sp2.0.cast = bitcast i8* %sp2 to i32*
-  %pix_sp2.0.copyload = load i32* %pix_sp2.0.cast, align 1
+  %pix_sp2.0.copyload = load i32, i32* %pix_sp2.0.cast, align 1
   %vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 1
   %vecinit1 = insertelement <2 x i32> %vec, i32 %pix_sp1.0.copyload, i32 0
   %vecinit2 = insertelement <2 x i32> %vec, i32 %pix_sp2.0.copyload, i32 0
diff --git a/test/CodeGen/ARM/vector-extend-narrow.ll b/test/CodeGen/ARM/vector-extend-narrow.ll
index f3218969c78e..d054bfda615e 100644
--- a/test/CodeGen/ARM/vector-extend-narrow.ll
+++ b/test/CodeGen/ARM/vector-extend-narrow.ll
@@ -2,9 +2,9 @@
 
 ; CHECK-LABEL: f:
 define float @f(<4 x i16>* nocapture %in) {
-  ; CHECK: vldr
+  ; CHECK: vld1
   ; CHECK: vmovl.u16
-  %1 = load <4 x i16>* %in
+  %1 = load <4 x i16>, <4 x i16>* %in
   ; CHECK: vcvt.f32.u32
   %2 = uitofp <4 x i16> %1 to <4 x float>
   %3 = extractelement <4 x float> %2, i32 0
@@ -25,7 +25,7 @@ define float @g(<4 x i8>* nocapture %in) {
   ; CHECK: vld1
   ; CHECK: vmovl.u8
   ; CHECK: vmovl.u16
-  %1 = load <4 x i8>* %in
+  %1 = load <4 x i8>, <4 x i8>* %in
   ; CHECK: vcvt.f32.u32
   %2 = uitofp <4 x i8> %1 to <4 x float>
   %3 = extractelement <4 x float> %2, i32 0
@@ -58,7 +58,7 @@ define <4 x i8> @i(<4 x i8>* %x) {
   ; CHECK: vrecps
   ; CHECK: vmul
   ; CHECK: vmovn
-  %1 = load <4 x i8>* %x, align 4
+  %1 = load <4 x i8>, <4 x i8>* %x, align 4
   %2 = sdiv <4 x i8> zeroinitializer, %1
   ret <4 x i8> %2
 }
@@ -68,7 +68,7 @@ define <4 x i32> @j(<4 x i8>* %in) nounwind {
   ; CHECK: vmovl.u8
   ; CHECK: vmovl.u16
   ; CHECK-NOT: vand
-  %1 = load <4 x i8>* %in, align 4
+  %1 = load <4 x i8>, <4 x i8>* %in, align 4
   %2 = zext <4 x i8> %1 to <4 x i32>
   ret <4 x i32> %2
 }
diff --git a/test/CodeGen/ARM/vector-load.ll b/test/CodeGen/ARM/vector-load.ll
new file mode 100644
index 000000000000..17f134f458a2
--- /dev/null
+++ b/test/CodeGen/ARM/vector-load.ll
@@ -0,0 +1,253 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7s-apple-ios8.0.0"
+
+define <8 x i8> @load_v8i8(<8 x i8>** %ptr) {
+;CHECK-LABEL: load_v8i8:
+;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
+	%A = load <8 x i8>*, <8 x i8>** %ptr
+	%lA = load <8 x i8>, <8 x i8>* %A, align 1
+	ret <8 x i8> %lA
+}
+
+define <8 x i8> @load_v8i8_update(<8 x i8>** %ptr) {
+;CHECK-LABEL: load_v8i8_update:
+;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <8 x i8>*, <8 x i8>** %ptr
+	%lA = load <8 x i8>, <8 x i8>* %A, align 1
+	%inc = getelementptr <8 x i8>, <8 x i8>* %A, i38 1
+        store <8 x i8>* %inc, <8 x i8>** %ptr
+	ret <8 x i8> %lA
+}
+
+define <4 x i16> @load_v4i16(<4 x i16>** %ptr) {
+;CHECK-LABEL: load_v4i16:
+;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
+	%A = load <4 x i16>*, <4 x i16>** %ptr
+	%lA = load <4 x i16>, <4 x i16>* %A, align 1
+	ret <4 x i16> %lA
+}
+
+define <4 x i16> @load_v4i16_update(<4 x i16>** %ptr) {
+;CHECK-LABEL: load_v4i16_update:
+;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <4 x i16>*, <4 x i16>** %ptr
+	%lA = load <4 x i16>, <4 x i16>* %A, align 1
+	%inc = getelementptr <4 x i16>, <4 x i16>* %A, i34 1
+        store <4 x i16>* %inc, <4 x i16>** %ptr
+	ret <4 x i16> %lA
+}
+
+define <2 x i32> @load_v2i32(<2 x i32>** %ptr) {
+;CHECK-LABEL: load_v2i32:
+;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
+	%A = load <2 x i32>*, <2 x i32>** %ptr
+	%lA = load <2 x i32>, <2 x i32>* %A, align 1
+	ret <2 x i32> %lA
+}
+
+define <2 x i32> @load_v2i32_update(<2 x i32>** %ptr) {
+;CHECK-LABEL: load_v2i32_update:
+;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <2 x i32>*, <2 x i32>** %ptr
+	%lA = load <2 x i32>, <2 x i32>* %A, align 1
+	%inc = getelementptr <2 x i32>, <2 x i32>* %A, i32 1
+        store <2 x i32>* %inc, <2 x i32>** %ptr
+	ret <2 x i32> %lA
+}
+
+define <2 x float> @load_v2f32(<2 x float>** %ptr) {
+;CHECK-LABEL: load_v2f32:
+;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
+	%A = load <2 x float>*, <2 x float>** %ptr
+	%lA = load <2 x float>, <2 x float>* %A, align 1
+	ret <2 x float> %lA
+}
+
+define <2 x float> @load_v2f32_update(<2 x float>** %ptr) {
+;CHECK-LABEL: load_v2f32_update:
+;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <2 x float>*, <2 x float>** %ptr
+	%lA = load <2 x float>, <2 x float>* %A, align 1
+	%inc = getelementptr <2 x float>, <2 x float>* %A, i32 1
+        store <2 x float>* %inc, <2 x float>** %ptr
+	ret <2 x float> %lA
+}
+
+define <1 x i64> @load_v1i64(<1 x i64>** %ptr) {
+;CHECK-LABEL: load_v1i64:
+;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
+	%A = load <1 x i64>*, <1 x i64>** %ptr
+	%lA = load <1 x i64>, <1 x i64>* %A, align 1
+	ret <1 x i64> %lA
+}
+
+define <1 x i64> @load_v1i64_update(<1 x i64>** %ptr) {
+;CHECK-LABEL: load_v1i64_update:
+;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <1 x i64>*, <1 x i64>** %ptr
+	%lA = load <1 x i64>, <1 x i64>* %A, align 1
+	%inc = getelementptr <1 x i64>, <1 x i64>* %A, i31 1
+        store <1 x i64>* %inc, <1 x i64>** %ptr
+	ret <1 x i64> %lA
+}
+
+define <16 x i8> @load_v16i8(<16 x i8>** %ptr) {
+;CHECK-LABEL: load_v16i8:
+;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
+	%A = load <16 x i8>*, <16 x i8>** %ptr
+	%lA = load <16 x i8>, <16 x i8>* %A, align 1
+	ret <16 x i8> %lA
+}
+
+define <16 x i8> @load_v16i8_update(<16 x i8>** %ptr) {
+;CHECK-LABEL: load_v16i8_update:
+;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <16 x i8>*, <16 x i8>** %ptr
+	%lA = load <16 x i8>, <16 x i8>* %A, align 1
+	%inc = getelementptr <16 x i8>, <16 x i8>* %A, i316 1
+        store <16 x i8>* %inc, <16 x i8>** %ptr
+	ret <16 x i8> %lA
+}
+
+define <8 x i16> @load_v8i16(<8 x i16>** %ptr) {
+;CHECK-LABEL: load_v8i16:
+;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
+	%A = load <8 x i16>*, <8 x i16>** %ptr
+	%lA = load <8 x i16>, <8 x i16>* %A, align 1
+	ret <8 x i16> %lA
+}
+
+define <8 x i16> @load_v8i16_update(<8 x i16>** %ptr) {
+;CHECK-LABEL: load_v8i16_update:
+;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <8 x i16>*, <8 x i16>** %ptr
+	%lA = load <8 x i16>, <8 x i16>* %A, align 1
+	%inc = getelementptr <8 x i16>, <8 x i16>* %A, i38 1
+        store <8 x i16>* %inc, <8 x i16>** %ptr
+	ret <8 x i16> %lA
+}
+
+define <4 x i32> @load_v4i32(<4 x i32>** %ptr) {
+;CHECK-LABEL: load_v4i32:
+;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
+	%A = load <4 x i32>*, <4 x i32>** %ptr
+	%lA = load <4 x i32>, <4 x i32>* %A, align 1
+	ret <4 x i32> %lA
+}
+
+define <4 x i32> @load_v4i32_update(<4 x i32>** %ptr) {
+;CHECK-LABEL: load_v4i32_update:
+;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <4 x i32>*, <4 x i32>** %ptr
+	%lA = load <4 x i32>, <4 x i32>* %A, align 1
+	%inc = getelementptr <4 x i32>, <4 x i32>* %A, i34 1
+        store <4 x i32>* %inc, <4 x i32>** %ptr
+	ret <4 x i32> %lA
+}
+
+define <4 x float> @load_v4f32(<4 x float>** %ptr) {
+;CHECK-LABEL: load_v4f32:
+;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
+	%A = load <4 x float>*, <4 x float>** %ptr
+	%lA = load <4 x float>, <4 x float>* %A, align 1
+	ret <4 x float> %lA
+}
+
+define <4 x float> @load_v4f32_update(<4 x float>** %ptr) {
+;CHECK-LABEL: load_v4f32_update:
+;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <4 x float>*, <4 x float>** %ptr
+	%lA = load <4 x float>, <4 x float>* %A, align 1
+	%inc = getelementptr <4 x float>, <4 x float>* %A, i34 1
+        store <4 x float>* %inc, <4 x float>** %ptr
+	ret <4 x float> %lA
+}
+
+define <2 x i64> @load_v2i64(<2 x i64>** %ptr) {
+;CHECK-LABEL: load_v2i64:
+;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
+	%A = load <2 x i64>*, <2 x i64>** %ptr
+	%lA = load <2 x i64>, <2 x i64>* %A, align 1
+	ret <2 x i64> %lA
+}
+
+define <2 x i64> @load_v2i64_update(<2 x i64>** %ptr) {
+;CHECK-LABEL: load_v2i64_update:
+;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <2 x i64>*, <2 x i64>** %ptr
+	%lA = load <2 x i64>, <2 x i64>* %A, align 1
+	%inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
+        store <2 x i64>* %inc, <2 x i64>** %ptr
+	ret <2 x i64> %lA
+}
+
+; Make sure we change the type to match alignment if necessary.
+define <2 x i64> @load_v2i64_update_aligned2(<2 x i64>** %ptr) {
+;CHECK-LABEL: load_v2i64_update_aligned2:
+;CHECK: vld1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <2 x i64>*, <2 x i64>** %ptr
+	%lA = load <2 x i64>, <2 x i64>* %A, align 2
+	%inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
+        store <2 x i64>* %inc, <2 x i64>** %ptr
+	ret <2 x i64> %lA
+}
+
+define <2 x i64> @load_v2i64_update_aligned4(<2 x i64>** %ptr) {
+;CHECK-LABEL: load_v2i64_update_aligned4:
+;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <2 x i64>*, <2 x i64>** %ptr
+	%lA = load <2 x i64>, <2 x i64>* %A, align 4
+	%inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
+        store <2 x i64>* %inc, <2 x i64>** %ptr
+	ret <2 x i64> %lA
+}
+
+define <2 x i64> @load_v2i64_update_aligned8(<2 x i64>** %ptr) {
+;CHECK-LABEL: load_v2i64_update_aligned8:
+;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <2 x i64>*, <2 x i64>** %ptr
+	%lA = load <2 x i64>, <2 x i64>* %A, align 8
+	%inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
+        store <2 x i64>* %inc, <2 x i64>** %ptr
+	ret <2 x i64> %lA
+}
+
+define <2 x i64> @load_v2i64_update_aligned16(<2 x i64>** %ptr) {
+;CHECK-LABEL: load_v2i64_update_aligned16:
+;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]!
+	%A = load <2 x i64>*, <2 x i64>** %ptr
+	%lA = load <2 x i64>, <2 x i64>* %A, align 16
+	%inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
+        store <2 x i64>* %inc, <2 x i64>** %ptr
+	ret <2 x i64> %lA
+}
+
+; Make sure we don't break smaller-than-dreg extloads.
+define <4 x i32> @zextload_v8i8tov8i32(<4 x i8>** %ptr) {
+;CHECK-LABEL: zextload_v8i8tov8i32:
+;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [{{r[0-9]+}}:32]
+;CHECK: vmovl.u8        {{q[0-9]+}}, {{d[0-9]+}}
+;CHECK: vmovl.u16       {{q[0-9]+}}, {{d[0-9]+}}
+	%A = load <4 x i8>*, <4 x i8>** %ptr
+	%lA = load <4 x i8>, <4 x i8>* %A, align 4
+        %zlA = zext <4 x i8> %lA to <4 x i32>
+	ret <4 x i32> %zlA
+}
+
+define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) {
+;CHECK-LABEL: zextload_v8i8tov8i32_fake_update:
+;CHECK: ldr.w   r[[PTRREG:[0-9]+]], [r0]
+;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r[[PTRREG]]:32]
+;CHECK: add.w   r[[INCREG:[0-9]+]], r[[PTRREG]], #16
+;CHECK: str.w   r[[INCREG]], [r0]
+;CHECK: vmovl.u8        {{q[0-9]+}}, {{d[0-9]+}}
+;CHECK: vmovl.u16       {{q[0-9]+}}, {{d[0-9]+}}
+	%A = load <4 x i8>*, <4 x i8>** %ptr
+	%lA = load <4 x i8>, <4 x i8>* %A, align 4
+	%inc = getelementptr <4 x i8>, <4 x i8>* %A, i38 4
+        store <4 x i8>* %inc, <4 x i8>** %ptr
+        %zlA = zext <4 x i8> %lA to <4 x i32>
+	ret <4 x i32> %zlA
+}
diff --git a/test/CodeGen/ARM/vector-promotion.ll b/test/CodeGen/ARM/vector-promotion.ll
index 42ceb60c47f5..1dabee386089 100644
--- a/test/CodeGen/ARM/vector-promotion.ll
+++ b/test/CodeGen/ARM/vector-promotion.ll
@@ -3,7 +3,7 @@
 ; RUN: llc -mtriple=thumbv7-apple-ios %s -o - -mattr=+neon | FileCheck --check-prefix=ASM %s
 
 ; IR-BOTH-LABEL: @simpleOneInstructionPromotion
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; IR-BOTH-NEXT: [[VECTOR_OR:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[LOAD]], <i32 undef, i32 1>
 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[VECTOR_OR]], i32 1
 ; IR-BOTH-NEXT: store i32 [[EXTRACT]], i32* %dest
@@ -16,7 +16,7 @@
 ; ASM-NEXT: vst1.32 {[[LOAD]][1]}, [r1:32]
 ; ASM-NEXT: bx
 define void @simpleOneInstructionPromotion(<2 x i32>* %addr1, i32* %dest) {
-  %in1 = load <2 x i32>* %addr1, align 8
+  %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
   %extract = extractelement <2 x i32> %in1, i32 1
   %out = or i32 %extract, 1
   store i32 %out, i32* %dest, align 4
@@ -24,7 +24,7 @@ define void @simpleOneInstructionPromotion(<2 x i32>* %addr1, i32* %dest) {
 }
 
 ; IR-BOTH-LABEL: @unsupportedInstructionForPromotion
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 0
 ; IR-BOTH-NEXT: [[CMP:%[a-zA-Z_0-9-]+]] = icmp eq i32 [[EXTRACT]], %in2
 ; IR-BOTH-NEXT: store i1 [[CMP]], i1* %dest
@@ -35,7 +35,7 @@ define void @simpleOneInstructionPromotion(<2 x i32>* %addr1, i32* %dest) {
 ; ASM: vmov.32 {{r[0-9]+}}, [[LOAD]]
 ; ASM: bx
 define void @unsupportedInstructionForPromotion(<2 x i32>* %addr1, i32 %in2, i1* %dest) {
-  %in1 = load <2 x i32>* %addr1, align 8
+  %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
   %extract = extractelement <2 x i32> %in1, i32 0
   %out = icmp eq i32 %extract, %in2
   store i1 %out, i1* %dest, align 4
@@ -44,7 +44,7 @@ define void @unsupportedInstructionForPromotion(<2 x i32>* %addr1, i32 %in2, i1*
 
 
 ; IR-BOTH-LABEL: @unsupportedChainInDifferentBBs
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 0
 ; IR-BOTH-NEXT: br i1 %bool, label %bb2, label %end
 ; BB2
@@ -58,7 +58,7 @@ define void @unsupportedInstructionForPromotion(<2 x i32>* %addr1, i32 %in2, i1*
 ; ASM: bx
 define void @unsupportedChainInDifferentBBs(<2 x i32>* %addr1, i32* %dest, i1 %bool) {
 bb1:
-  %in1 = load <2 x i32>* %addr1, align 8
+  %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
   %extract = extractelement <2 x i32> %in1, i32 0
   br i1 %bool, label %bb2, label %end
 bb2: 
@@ -70,7 +70,7 @@ end:
 }
 
 ; IR-LABEL: @chainOfInstructionsToPromote
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; IR-BOTH-NEXT: [[VECTOR_OR1:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[LOAD]], <i32 1, i32 undef>
 ; IR-BOTH-NEXT: [[VECTOR_OR2:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[VECTOR_OR1]], <i32 1, i32 undef>
 ; IR-BOTH-NEXT: [[VECTOR_OR3:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[VECTOR_OR2]], <i32 1, i32 undef>
@@ -87,7 +87,7 @@ end:
 ; ASM-NOT: vmov.32 {{r[0-9]+}}, [[LOAD]]
 ; ASM: bx
 define void @chainOfInstructionsToPromote(<2 x i32>* %addr1, i32* %dest) {
-  %in1 = load <2 x i32>* %addr1, align 8
+  %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
   %extract = extractelement <2 x i32> %in1, i32 0
   %out1 = or i32 %extract, 1
   %out2 = or i32 %out1, 1
@@ -101,7 +101,7 @@ define void @chainOfInstructionsToPromote(<2 x i32>* %addr1, i32* %dest) {
 }
 
 ; IR-BOTH-LABEL: @unsupportedMultiUses
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
 ; IR-BOTH-NEXT: [[OR:%[a-zA-Z_0-9-]+]] = or i32 [[EXTRACT]], 1
 ; IR-BOTH-NEXT: store i32 [[OR]], i32* %dest
@@ -112,7 +112,7 @@ define void @chainOfInstructionsToPromote(<2 x i32>* %addr1, i32* %dest) {
 ; ASM: vmov.32 {{r[0-9]+}}, [[LOAD]]
 ; ASM: bx
 define i32 @unsupportedMultiUses(<2 x i32>* %addr1, i32* %dest) {
-  %in1 = load <2 x i32>* %addr1, align 8
+  %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
   %extract = extractelement <2 x i32> %in1, i32 1
   %out = or i32 %extract, 1
   store i32 %out, i32* %dest, align 4
@@ -122,7 +122,7 @@ define i32 @unsupportedMultiUses(<2 x i32>* %addr1, i32* %dest) {
 ; Check that we promote we a splat constant when this is a division.
 ; The NORMAL mode does not promote anything as divisions are not legal.
 ; IR-BOTH-LABEL: @udivCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; Scalar version:
 ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 [[EXTRACT]], 7
@@ -133,7 +133,7 @@ define i32 @unsupportedMultiUses(<2 x i32>* %addr1, i32* %dest) {
 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
 ; IR-BOTH-NEXT: ret
 define void @udivCase(<2 x i32>* %addr1, i32* %dest) {
-  %in1 = load <2 x i32>* %addr1, align 8
+  %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
   %extract = extractelement <2 x i32> %in1, i32 1
   %out = udiv i32 %extract, 7
   store i32 %out, i32* %dest, align 4
@@ -141,7 +141,7 @@ define void @udivCase(<2 x i32>* %addr1, i32* %dest) {
 }
 
 ; IR-BOTH-LABEL: @uremCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; Scalar version:
 ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = urem i32 [[EXTRACT]], 7
@@ -152,7 +152,7 @@ define void @udivCase(<2 x i32>* %addr1, i32* %dest) {
 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
 ; IR-BOTH-NEXT: ret 
 define void @uremCase(<2 x i32>* %addr1, i32* %dest) {
-  %in1 = load <2 x i32>* %addr1, align 8
+  %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
   %extract = extractelement <2 x i32> %in1, i32 1
   %out = urem i32 %extract, 7
   store i32 %out, i32* %dest, align 4
@@ -160,7 +160,7 @@ define void @uremCase(<2 x i32>* %addr1, i32* %dest) {
 }
 
 ; IR-BOTH-LABEL: @sdivCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; Scalar version:
 ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sdiv i32 [[EXTRACT]], 7
@@ -171,7 +171,7 @@ define void @uremCase(<2 x i32>* %addr1, i32* %dest) {
 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
 ; IR-BOTH-NEXT: ret 
 define void @sdivCase(<2 x i32>* %addr1, i32* %dest) {
-  %in1 = load <2 x i32>* %addr1, align 8
+  %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
   %extract = extractelement <2 x i32> %in1, i32 1
   %out = sdiv i32 %extract, 7
   store i32 %out, i32* %dest, align 4
@@ -179,7 +179,7 @@ define void @sdivCase(<2 x i32>* %addr1, i32* %dest) {
 }
 
 ; IR-BOTH-LABEL: @sremCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; Scalar version:
 ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = srem i32 [[EXTRACT]], 7
@@ -190,7 +190,7 @@ define void @sdivCase(<2 x i32>* %addr1, i32* %dest) {
 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
 ; IR-BOTH-NEXT: ret 
 define void @sremCase(<2 x i32>* %addr1, i32* %dest) {
-  %in1 = load <2 x i32>* %addr1, align 8
+  %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
   %extract = extractelement <2 x i32> %in1, i32 1
   %out = srem i32 %extract, 7
   store i32 %out, i32* %dest, align 4
@@ -198,7 +198,7 @@ define void @sremCase(<2 x i32>* %addr1, i32* %dest) {
 }
 
 ; IR-BOTH-LABEL: @fdivCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1
 ; Scalar version:  
 ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1
 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = fdiv float [[EXTRACT]], 7.0
@@ -209,7 +209,7 @@ define void @sremCase(<2 x i32>* %addr1, i32* %dest) {
 ; IR-BOTH-NEXT: store float [[RES]], float* %dest
 ; IR-BOTH-NEXT: ret
 define void @fdivCase(<2 x float>* %addr1, float* %dest) {
-  %in1 = load <2 x float>* %addr1, align 8   
+  %in1 = load <2 x float>, <2 x float>* %addr1, align 8   
   %extract = extractelement <2 x float> %in1, i32 1
   %out = fdiv float %extract, 7.0
   store float %out, float* %dest, align 4
@@ -217,7 +217,7 @@ define void @fdivCase(<2 x float>* %addr1, float* %dest) {
 }
 
 ; IR-BOTH-LABEL: @fremCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1
 ; Scalar version:  
 ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1
 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = frem float [[EXTRACT]], 7.0
@@ -228,7 +228,7 @@ define void @fdivCase(<2 x float>* %addr1, float* %dest) {
 ; IR-BOTH-NEXT: store float [[RES]], float* %dest
 ; IR-BOTH-NEXT: ret
 define void @fremCase(<2 x float>* %addr1, float* %dest) {
-  %in1 = load <2 x float>* %addr1, align 8   
+  %in1 = load <2 x float>, <2 x float>* %addr1, align 8   
   %extract = extractelement <2 x float> %in1, i32 1
   %out = frem float %extract, 7.0
   store float %out, float* %dest, align 4
@@ -238,13 +238,13 @@ define void @fremCase(<2 x float>* %addr1, float* %dest) {
 ; Check that we do not promote when we may introduce undefined behavior
 ; like division by zero.
 ; IR-BOTH-LABEL: @undefDivCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
 ; IR-BOTH-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 7, [[EXTRACT]]
 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
 ; IR-BOTH-NEXT: ret
 define void @undefDivCase(<2 x i32>* %addr1, i32* %dest) {
-  %in1 = load <2 x i32>* %addr1, align 8
+  %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
   %extract = extractelement <2 x i32> %in1, i32 1
   %out = udiv i32 7, %extract
   store i32 %out, i32* %dest, align 4
@@ -255,13 +255,13 @@ define void @undefDivCase(<2 x i32>* %addr1, i32* %dest) {
 ; Check that we do not promote when we may introduce undefined behavior
 ; like division by zero.
 ; IR-BOTH-LABEL: @undefRemCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
 ; IR-BOTH-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = srem i32 7, [[EXTRACT]]
 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
 ; IR-BOTH-NEXT: ret
 define void @undefRemCase(<2 x i32>* %addr1, i32* %dest) {
-  %in1 = load <2 x i32>* %addr1, align 8
+  %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
   %extract = extractelement <2 x i32> %in1, i32 1
   %out = srem i32 7, %extract
   store i32 %out, i32* %dest, align 4
@@ -271,7 +271,7 @@ define void @undefRemCase(<2 x i32>* %addr1, i32* %dest) {
 ; Check that we use an undef mask for undefined behavior if the fast-math
 ; flag is set.
 ; IR-BOTH-LABEL: @undefConstantFRemCaseWithFastMath
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1
 ; Scalar version:  
 ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1
 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = frem nnan float [[EXTRACT]], 7.0
@@ -282,7 +282,7 @@ define void @undefRemCase(<2 x i32>* %addr1, i32* %dest) {
 ; IR-BOTH-NEXT: store float [[RES]], float* %dest
 ; IR-BOTH-NEXT: ret
 define void @undefConstantFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest) {
-  %in1 = load <2 x float>* %addr1, align 8   
+  %in1 = load <2 x float>, <2 x float>* %addr1, align 8   
   %extract = extractelement <2 x float> %in1, i32 1
   %out = frem nnan float %extract, 7.0
   store float %out, float* %dest, align 4
@@ -292,7 +292,7 @@ define void @undefConstantFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest
 ; Check that we use an undef mask for undefined behavior if the fast-math
 ; flag is set.
 ; IR-BOTH-LABEL: @undefVectorFRemCaseWithFastMath
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1
 ; Scalar version:  
 ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1
 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = frem nnan float 7.000000e+00, [[EXTRACT]]
@@ -303,7 +303,7 @@ define void @undefConstantFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest
 ; IR-BOTH-NEXT: store float [[RES]], float* %dest
 ; IR-BOTH-NEXT: ret
 define void @undefVectorFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest) {
-  %in1 = load <2 x float>* %addr1, align 8   
+  %in1 = load <2 x float>, <2 x float>* %addr1, align 8   
   %extract = extractelement <2 x float> %in1, i32 1
   %out = frem nnan float 7.0, %extract
   store float %out, float* %dest, align 4
@@ -314,7 +314,7 @@ define void @undefVectorFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest)
 ; This requires the STRESS mode, as floating point value are
 ; not promote on armv7.
 ; IR-BOTH-LABEL: @simpleOneInstructionPromotionFloat
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1
 ; Scalar version: 
 ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1
 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = fadd float [[EXTRACT]], 1.0
@@ -325,7 +325,7 @@ define void @undefVectorFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest)
 ; IR-BOTH-NEXT: store float [[RES]], float* %dest
 ; IR-BOTH-NEXT: ret
 define void @simpleOneInstructionPromotionFloat(<2 x float>* %addr1, float* %dest) {
-  %in1 = load <2 x float>* %addr1, align 8
+  %in1 = load <2 x float>, <2 x float>* %addr1, align 8
   %extract = extractelement <2 x float> %in1, i32 1
   %out = fadd float %extract, 1.0
   store float %out, float* %dest, align 4
@@ -337,7 +337,7 @@ define void @simpleOneInstructionPromotionFloat(<2 x float>* %addr1, float* %des
 ; This requires the STRESS modes, as variable index are expensive
 ; to lower.
 ; IR-BOTH-LABEL: @simpleOneInstructionPromotionVariableIdx
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; Scalar version:
 ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 %idx
 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = or i32 [[EXTRACT]], 1
@@ -348,7 +348,7 @@ define void @simpleOneInstructionPromotionFloat(<2 x float>* %addr1, float* %des
 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
 ; IR-BOTH-NEXT: ret
 define void @simpleOneInstructionPromotionVariableIdx(<2 x i32>* %addr1, i32* %dest, i32 %idx) {
-  %in1 = load <2 x i32>* %addr1, align 8
+  %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
   %extract = extractelement <2 x i32> %in1, i32 %idx
   %out = or i32 %extract, 1
   store i32 %out, i32* %dest, align 4
@@ -360,7 +360,7 @@ define void @simpleOneInstructionPromotionVariableIdx(<2 x i32>* %addr1, i32* %d
 ; as legal or custom, althought the actual assembly is better if we were
 ; promoting it.
 ; IR-BOTH-LABEL: @simpleOneInstructionPromotion8x8
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <8 x i8>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <8 x i8>, <8 x i8>* %addr1
 ; Scalar version:  
 ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <8 x i8> [[LOAD]], i32 1
 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = or i8 [[EXTRACT]], 1
@@ -371,7 +371,7 @@ define void @simpleOneInstructionPromotionVariableIdx(<2 x i32>* %addr1, i32* %d
 ; IR-BOTH-NEXT: store i8 [[RES]], i8* %dest
 ; IR-BOTH-NEXT: ret
 define void @simpleOneInstructionPromotion8x8(<8 x i8>* %addr1, i8* %dest) {
-  %in1 = load <8 x i8>* %addr1, align 8
+  %in1 = load <8 x i8>, <8 x i8>* %addr1, align 8
   %extract = extractelement <8 x i8> %in1, i32 1
   %out = or i8 %extract, 1
   store i8 %out, i8* %dest, align 4
@@ -381,7 +381,7 @@ define void @simpleOneInstructionPromotion8x8(<8 x i8>* %addr1, i8* %dest) {
 ; Check that we optimized the sequence correctly when it can be
 ; lowered on a Q register.
 ; IR-BOTH-LABEL: @simpleOneInstructionPromotion
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <4 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <4 x i32>, <4 x i32>* %addr1
 ; IR-BOTH-NEXT: [[VECTOR_OR:%[a-zA-Z_0-9-]+]] = or <4 x i32> [[LOAD]], <i32 undef, i32 1, i32 undef, i32 undef>
 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <4 x i32> [[VECTOR_OR]], i32 1
 ; IR-BOTH-NEXT: store i32 [[EXTRACT]], i32* %dest
@@ -395,7 +395,7 @@ define void @simpleOneInstructionPromotion8x8(<8 x i8>* %addr1, i8* %dest) {
 ; ASM-NEXT: vst1.32 {[[LOAD]][1]}, [r1]
 ; ASM-NEXT: bx
 define void @simpleOneInstructionPromotion4x32(<4 x i32>* %addr1, i32* %dest) {
-  %in1 = load <4 x i32>* %addr1, align 8
+  %in1 = load <4 x i32>, <4 x i32>* %addr1, align 8
   %extract = extractelement <4 x i32> %in1, i32 1
   %out = or i32 %extract, 1
   store i32 %out, i32* %dest, align 1
diff --git a/test/CodeGen/ARM/vector-spilling.ll b/test/CodeGen/ARM/vector-spilling.ll
index 746c6dfcd114..9e3225ebcda0 100644
--- a/test/CodeGen/ARM/vector-spilling.ll
+++ b/test/CodeGen/ARM/vector-spilling.ll
@@ -10,22 +10,22 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; CHECK: vldmia
 define void @test(<8 x i64>* %src) #0 {
 entry:
-  %0 = getelementptr inbounds <8 x i64>* %src, i32 0
-  %1 = load <8 x i64>* %0, align 8
+  %0 = getelementptr inbounds <8 x i64>, <8 x i64>* %src, i32 0
+  %1 = load <8 x i64>, <8 x i64>* %0, align 8
 
-  %2 = getelementptr inbounds <8 x i64>* %src, i32 1
-  %3 = load <8 x i64>* %2, align 8
+  %2 = getelementptr inbounds <8 x i64>, <8 x i64>* %src, i32 1
+  %3 = load <8 x i64>, <8 x i64>* %2, align 8
 
-  %4 = getelementptr inbounds <8 x i64>* %src, i32 2
-  %5 = load <8 x i64>* %4, align 8
+  %4 = getelementptr inbounds <8 x i64>, <8 x i64>* %src, i32 2
+  %5 = load <8 x i64>, <8 x i64>* %4, align 8
 
-  %6 = getelementptr inbounds <8 x i64>* %src, i32 3
-  %7 = load <8 x i64>* %6, align 8
+  %6 = getelementptr inbounds <8 x i64>, <8 x i64>* %src, i32 3
+  %7 = load <8 x i64>, <8 x i64>* %6, align 8
 
   %8 = shufflevector <8 x i64> %1, <8 x i64> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
   %9 = shufflevector <8 x i64> %1, <8 x i64> %3, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
 
-  tail call void(<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>)* @foo(<8 x i64> %1, <8 x i64> %3, <8 x i64> %5, <8 x i64> %7, <8 x i64> %8, <8 x i64> %9)
+  tail call void(<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>) @foo(<8 x i64> %1, <8 x i64> %3, <8 x i64> %5, <8 x i64> %7, <8 x i64> %8, <8 x i64> %9)
   ret void
 }
 
diff --git a/test/CodeGen/ARM/vector-store.ll b/test/CodeGen/ARM/vector-store.ll
new file mode 100644
index 000000000000..30baa9a20ddc
--- /dev/null
+++ b/test/CodeGen/ARM/vector-store.ll
@@ -0,0 +1,258 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7s-apple-ios8.0.0"
+
+define void @store_v8i8(<8 x i8>** %ptr, <8 x i8> %val) {
+;CHECK-LABEL: store_v8i8:
+;CHECK: str r1, [r0]
+	%A = load <8 x i8>*, <8 x i8>** %ptr
+	store  <8 x i8> %val, <8 x i8>* %A, align 1
+	ret void
+}
+
+define void @store_v8i8_update(<8 x i8>** %ptr, <8 x i8> %val) {
+;CHECK-LABEL: store_v8i8_update:
+;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <8 x i8>*, <8 x i8>** %ptr
+	store  <8 x i8> %val, <8 x i8>* %A, align 1
+	%inc = getelementptr <8 x i8>, <8 x i8>* %A, i38 1
+        store <8 x i8>* %inc, <8 x i8>** %ptr
+	ret void
+}
+
+define void @store_v4i16(<4 x i16>** %ptr, <4 x i16> %val) {
+;CHECK-LABEL: store_v4i16:
+;CHECK: str r1, [r0]
+	%A = load <4 x i16>*, <4 x i16>** %ptr
+	store  <4 x i16> %val, <4 x i16>* %A, align 1
+	ret void
+}
+
+define void @store_v4i16_update(<4 x i16>** %ptr, <4 x i16> %val) {
+;CHECK-LABEL: store_v4i16_update:
+;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <4 x i16>*, <4 x i16>** %ptr
+	store  <4 x i16> %val, <4 x i16>* %A, align 1
+	%inc = getelementptr <4 x i16>, <4 x i16>* %A, i34 1
+        store <4 x i16>* %inc, <4 x i16>** %ptr
+	ret void
+}
+
+define void @store_v2i32(<2 x i32>** %ptr, <2 x i32> %val) {
+;CHECK-LABEL: store_v2i32:
+;CHECK: str r1, [r0]
+	%A = load <2 x i32>*, <2 x i32>** %ptr
+	store  <2 x i32> %val, <2 x i32>* %A, align 1
+	ret void
+}
+
+define void @store_v2i32_update(<2 x i32>** %ptr, <2 x i32> %val) {
+;CHECK-LABEL: store_v2i32_update:
+;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <2 x i32>*, <2 x i32>** %ptr
+	store  <2 x i32> %val, <2 x i32>* %A, align 1
+	%inc = getelementptr <2 x i32>, <2 x i32>* %A, i32 1
+        store <2 x i32>* %inc, <2 x i32>** %ptr
+	ret void
+}
+
+define void @store_v2f32(<2 x float>** %ptr, <2 x float> %val) {
+;CHECK-LABEL: store_v2f32:
+;CHECK: str r1, [r0]
+	%A = load <2 x float>*, <2 x float>** %ptr
+	store  <2 x float> %val, <2 x float>* %A, align 1
+	ret void
+}
+
+define void @store_v2f32_update(<2 x float>** %ptr, <2 x float> %val) {
+;CHECK-LABEL: store_v2f32_update:
+;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <2 x float>*, <2 x float>** %ptr
+	store  <2 x float> %val, <2 x float>* %A, align 1
+	%inc = getelementptr <2 x float>, <2 x float>* %A, i32 1
+        store <2 x float>* %inc, <2 x float>** %ptr
+	ret void
+}
+
+define void @store_v1i64(<1 x i64>** %ptr, <1 x i64> %val) {
+;CHECK-LABEL: store_v1i64:
+;CHECK: str r1, [r0]
+	%A = load <1 x i64>*, <1 x i64>** %ptr
+	store  <1 x i64> %val, <1 x i64>* %A, align 1
+	ret void
+}
+
+define void @store_v1i64_update(<1 x i64>** %ptr, <1 x i64> %val) {
+;CHECK-LABEL: store_v1i64_update:
+;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <1 x i64>*, <1 x i64>** %ptr
+	store  <1 x i64> %val, <1 x i64>* %A, align 1
+	%inc = getelementptr <1 x i64>, <1 x i64>* %A, i31 1
+        store <1 x i64>* %inc, <1 x i64>** %ptr
+	ret void
+}
+
+define void @store_v16i8(<16 x i8>** %ptr, <16 x i8> %val) {
+;CHECK-LABEL: store_v16i8:
+;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
+	%A = load <16 x i8>*, <16 x i8>** %ptr
+	store  <16 x i8> %val, <16 x i8>* %A, align 1
+	ret void
+}
+
+define void @store_v16i8_update(<16 x i8>** %ptr, <16 x i8> %val) {
+;CHECK-LABEL: store_v16i8_update:
+;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <16 x i8>*, <16 x i8>** %ptr
+	store  <16 x i8> %val, <16 x i8>* %A, align 1
+	%inc = getelementptr <16 x i8>, <16 x i8>* %A, i316 1
+        store <16 x i8>* %inc, <16 x i8>** %ptr
+	ret void
+}
+
+define void @store_v8i16(<8 x i16>** %ptr, <8 x i16> %val) {
+;CHECK-LABEL: store_v8i16:
+;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
+	%A = load <8 x i16>*, <8 x i16>** %ptr
+	store  <8 x i16> %val, <8 x i16>* %A, align 1
+	ret void
+}
+
+define void @store_v8i16_update(<8 x i16>** %ptr, <8 x i16> %val) {
+;CHECK-LABEL: store_v8i16_update:
+;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <8 x i16>*, <8 x i16>** %ptr
+	store  <8 x i16> %val, <8 x i16>* %A, align 1
+	%inc = getelementptr <8 x i16>, <8 x i16>* %A, i38 1
+        store <8 x i16>* %inc, <8 x i16>** %ptr
+	ret void
+}
+
+define void @store_v4i32(<4 x i32>** %ptr, <4 x i32> %val) {
+;CHECK-LABEL: store_v4i32:
+;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
+	%A = load <4 x i32>*, <4 x i32>** %ptr
+	store  <4 x i32> %val, <4 x i32>* %A, align 1
+	ret void
+}
+
+define void @store_v4i32_update(<4 x i32>** %ptr, <4 x i32> %val) {
+;CHECK-LABEL: store_v4i32_update:
+;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <4 x i32>*, <4 x i32>** %ptr
+	store  <4 x i32> %val, <4 x i32>* %A, align 1
+	%inc = getelementptr <4 x i32>, <4 x i32>* %A, i34 1
+        store <4 x i32>* %inc, <4 x i32>** %ptr
+	ret void
+}
+
+define void @store_v4f32(<4 x float>** %ptr, <4 x float> %val) {
+;CHECK-LABEL: store_v4f32:
+;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
+	%A = load <4 x float>*, <4 x float>** %ptr
+	store  <4 x float> %val, <4 x float>* %A, align 1
+	ret void
+}
+
+define void @store_v4f32_update(<4 x float>** %ptr, <4 x float> %val) {
+;CHECK-LABEL: store_v4f32_update:
+;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <4 x float>*, <4 x float>** %ptr
+	store  <4 x float> %val, <4 x float>* %A, align 1
+	%inc = getelementptr <4 x float>, <4 x float>* %A, i34 1
+        store <4 x float>* %inc, <4 x float>** %ptr
+	ret void
+}
+
+define void @store_v2i64(<2 x i64>** %ptr, <2 x i64> %val) {
+;CHECK-LABEL: store_v2i64:
+;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
+	%A = load <2 x i64>*, <2 x i64>** %ptr
+	store  <2 x i64> %val, <2 x i64>* %A, align 1
+	ret void
+}
+
+define void @store_v2i64_update(<2 x i64>** %ptr, <2 x i64> %val) {
+;CHECK-LABEL: store_v2i64_update:
+;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <2 x i64>*, <2 x i64>** %ptr
+	store  <2 x i64> %val, <2 x i64>* %A, align 1
+	%inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
+        store <2 x i64>* %inc, <2 x i64>** %ptr
+	ret void
+}
+
+define void @store_v2i64_update_aligned2(<2 x i64>** %ptr, <2 x i64> %val) {
+;CHECK-LABEL: store_v2i64_update_aligned2:
+;CHECK: vst1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <2 x i64>*, <2 x i64>** %ptr
+	store  <2 x i64> %val, <2 x i64>* %A, align 2
+	%inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
+        store <2 x i64>* %inc, <2 x i64>** %ptr
+	ret void
+}
+
+define void @store_v2i64_update_aligned4(<2 x i64>** %ptr, <2 x i64> %val) {
+;CHECK-LABEL: store_v2i64_update_aligned4:
+;CHECK: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <2 x i64>*, <2 x i64>** %ptr
+	store  <2 x i64> %val, <2 x i64>* %A, align 4
+	%inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
+        store <2 x i64>* %inc, <2 x i64>** %ptr
+	ret void
+}
+
+define void @store_v2i64_update_aligned8(<2 x i64>** %ptr, <2 x i64> %val) {
+;CHECK-LABEL: store_v2i64_update_aligned8:
+;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
+	%A = load <2 x i64>*, <2 x i64>** %ptr
+	store  <2 x i64> %val, <2 x i64>* %A, align 8
+	%inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
+        store <2 x i64>* %inc, <2 x i64>** %ptr
+	ret void
+}
+
+define void @store_v2i64_update_aligned16(<2 x i64>** %ptr, <2 x i64> %val) {
+;CHECK-LABEL: store_v2i64_update_aligned16:
+;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]!
+	%A = load <2 x i64>*, <2 x i64>** %ptr
+	store  <2 x i64> %val, <2 x i64>* %A, align 16
+	%inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
+        store <2 x i64>* %inc, <2 x i64>** %ptr
+	ret void
+}
+
+define void @truncstore_v4i32tov4i8(<4 x i8>** %ptr, <4 x i32> %val) {
+;CHECK-LABEL: truncstore_v4i32tov4i8:
+;CHECK: ldr.w   r9, [sp]
+;CHECK: vmov    {{d[0-9]+}}, r3, r9
+;CHECK: vmov    {{d[0-9]+}}, r1, r2
+;CHECK: vmovn.i32       [[VECLO:d[0-9]+]], {{q[0-9]+}}
+;CHECK: vuzp.8  [[VECLO]], {{d[0-9]+}}
+;CHECK: ldr     r[[PTRREG:[0-9]+]], [r0]
+;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32]
+	%A = load <4 x i8>*, <4 x i8>** %ptr
+        %trunc = trunc <4 x i32> %val to <4 x i8>
+	store  <4 x i8> %trunc, <4 x i8>* %A, align 4
+	ret void
+}
+
+define void @truncstore_v4i32tov4i8_fake_update(<4 x i8>** %ptr, <4 x i32> %val) {
+;CHECK-LABEL: truncstore_v4i32tov4i8_fake_update:
+;CHECK: ldr.w   r9, [sp]
+;CHECK: vmov    {{d[0-9]+}}, r3, r9
+;CHECK: vmov    {{d[0-9]+}}, r1, r2
+;CHECK: movs    [[IMM16:r[0-9]+]], #16
+;CHECK: vmovn.i32       [[VECLO:d[0-9]+]], {{q[0-9]+}}
+;CHECK: vuzp.8  [[VECLO]], {{d[0-9]+}}
+;CHECK: ldr     r[[PTRREG:[0-9]+]], [r0]
+;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32], [[IMM16]]
+;CHECK: str     r[[PTRREG]], [r0]
+	%A = load <4 x i8>*, <4 x i8>** %ptr
+        %trunc = trunc <4 x i32> %val to <4 x i8>
+	store  <4 x i8> %trunc, <4 x i8>* %A, align 4
+	%inc = getelementptr <4 x i8>, <4 x i8>* %A, i38 4
+        store <4 x i8>* %inc, <4 x i8>** %ptr
+	ret void
+}
diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll
index 4407451244e9..72ecf0ef0626 100644
--- a/test/CodeGen/ARM/vext.ll
+++ b/test/CodeGen/ARM/vext.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextd:
 ;CHECK: vext
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextRd:
 ;CHECK: vext
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
 	ret <8 x i8> %tmp3
 }
@@ -21,8 +21,8 @@ define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextq:
 ;CHECK: vext
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
 	ret <16 x i8> %tmp3
 }
@@ -30,8 +30,8 @@ define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextRq:
 ;CHECK: vext
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
 	ret <16 x i8> %tmp3
 }
@@ -39,8 +39,8 @@ define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: test_vextd16:
 ;CHECK: vext
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
 	ret <4 x i16> %tmp3
 }
@@ -48,8 +48,8 @@ define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: test_vextq32:
 ;CHECK: vext
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
 	ret <4 x i32> %tmp3
 }
@@ -59,8 +59,8 @@ define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextd_undef:
 ;CHECK: vext
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10>
 	ret <8 x i8> %tmp3
 }
@@ -68,8 +68,8 @@ define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextRq_undef:
 ;CHECK: vext
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 undef, i32 undef, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6>
 	ret <16 x i8> %tmp3
 }
@@ -118,8 +118,8 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK: vext.16
 ;CHECK-NOT: vext.16
 ;CHECK: vzip.16
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 3, i32 8, i32 5, i32 9>
         ret <4 x i16> %tmp3
 }
@@ -128,8 +128,8 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: test_undef:
 ;CHECK: vzip.16
-        %tmp1 = load <8 x i16>* %A
-        %tmp2 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
+        %tmp2 = load <8 x i16>, <8 x i16>* %B
         %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9>
         ret <4 x i16> %tmp3
 }
@@ -143,7 +143,7 @@ define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind {
 ;CHECK: vmov.16 [[REG]][1]
 ;CHECK: vmov.16 [[REG]][2]
 ;CHECK: vmov.16 [[REG]][3]
-        %tmp1 = load <32 x i16>* %B
+        %tmp1 = load <32 x i16>, <32 x i16>* %B
         %tmp2 = shufflevector <32 x i16> %tmp1, <32 x i16> undef, <4 x i32> <i32 0, i32 8, i32 16, i32 24>
         ret <4 x i16> %tmp2
 }
@@ -156,7 +156,7 @@ define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
 ;CHECK: vmov.16 [[REG]][1]
 ;CHECK: vmov.16 [[REG]][2]
 ;CHECK: vmov.16 [[REG]][3]
-        %tmp1 = load <8 x i16>* %B
+        %tmp1 = load <8 x i16>, <8 x i16>* %B
         %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
         ret <4 x i16> %tmp2
 }
@@ -174,8 +174,8 @@ define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK: vmov.16 [[REG2]][1]
 ;CHECK: vmov.16 [[REG2]][2]
 ;CHECK: vmov.16 [[REG2]][3]
-       %tmp1 = load <8 x i16>* %A
-       %tmp2 = load <8 x i16>* %B
+       %tmp1 = load <8 x i16>, <8 x i16>* %A
+       %tmp2 = load <8 x i16>, <8 x i16>* %B
        %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9>
        ret <8 x i16> %tmp3
 }
@@ -185,7 +185,7 @@ define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind {
 ; CHECK-LABEL: test_elem_mismatch:
 ; CHECK: vstr
-  %tmp0 = load <2 x i64>* %src, align 16
+  %tmp0 = load <2 x i64>, <2 x i64>* %src, align 16
   %tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32>
   %tmp2 = extractelement <4 x i32> %tmp1, i32 0
   %tmp3 = extractelement <4 x i32> %tmp1, i32 2
diff --git a/test/CodeGen/ARM/vfcmp.ll b/test/CodeGen/ARM/vfcmp.ll
index 4b2fea9baa09..8673b7d639d6 100644
--- a/test/CodeGen/ARM/vfcmp.ll
+++ b/test/CodeGen/ARM/vfcmp.ll
@@ -7,8 +7,8 @@ define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vcunef32:
 ;CHECK: vceq.f32
 ;CHECK-NEXT: vmvn
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fcmp une <2 x float> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -18,8 +18,8 @@ define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vcoltf32:
 ;CHECK: vcgt.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fcmp olt <2 x float> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -29,8 +29,8 @@ define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vcolef32:
 ;CHECK: vcge.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fcmp ole <2 x float> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -41,8 +41,8 @@ define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vcugef32:
 ;CHECK: vcgt.f32
 ;CHECK-NEXT: vmvn
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fcmp uge <2 x float> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -53,8 +53,8 @@ define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vculef32:
 ;CHECK: vcgt.f32
 ;CHECK-NEXT: vmvn
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fcmp ule <2 x float> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -65,8 +65,8 @@ define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vcugtf32:
 ;CHECK: vcge.f32
 ;CHECK-NEXT: vmvn
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fcmp ugt <2 x float> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -77,8 +77,8 @@ define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vcultf32:
 ;CHECK: vcge.f32
 ;CHECK-NEXT: vmvn
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fcmp ult <2 x float> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -91,8 +91,8 @@ define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-NEXT: vcgt.f32
 ;CHECK-NEXT: vorr
 ;CHECK-NEXT: vmvn
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fcmp ueq <2 x float> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -104,8 +104,8 @@ define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK: vcgt.f32
 ;CHECK-NEXT: vcgt.f32
 ;CHECK-NEXT: vorr
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fcmp one <2 x float> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -118,8 +118,8 @@ define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-NEXT: vcgt.f32
 ;CHECK-NEXT: vorr
 ;CHECK-NEXT: vmvn
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fcmp uno <2 x float> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -131,8 +131,8 @@ define <2 x i32> @vcordf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK: vcge.f32
 ;CHECK-NEXT: vcgt.f32
 ;CHECK-NEXT: vorr
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fcmp ord <2 x float> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
diff --git a/test/CodeGen/ARM/vfp-libcalls.ll b/test/CodeGen/ARM/vfp-libcalls.ll
index 9d4e194e90ee..b08073ab62b3 100644
--- a/test/CodeGen/ARM/vfp-libcalls.ll
+++ b/test/CodeGen/ARM/vfp-libcalls.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple=armv6-apple-ios -mcpu=arm1136jf-s -o - %s | FileCheck %s --check-prefix=CHECK-HARD
 ; RUN: llc -mtriple=thumbv6-apple-ios -mcpu=arm1136jf-s -o - %s | FileCheck %s --check-prefix=CHECK-SOFTISH
-; RUN: llc -mtriple=armv7s-apple-ios -soft-float -mcpu=arm1136jf-s -o - %s | FileCheck %s --check-prefix=CHECK-SOFT
+; RUN: llc -mtriple=armv7s-apple-ios -mattr=+soft-float -mcpu=arm1136jf-s -o - %s | FileCheck %s --check-prefix=CHECK-SOFT
 
 define float @test_call(float %a, float %b) {
 ; CHECK-HARD: vadd.f32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
@@ -8,4 +8,4 @@ define float @test_call(float %a, float %b) {
 ; CHECK-SOFT: bl ___addsf3{{$}}
   %sum = fadd float %a, %b
   ret float %sum
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/ARM/vfp-regs-dwarf.ll b/test/CodeGen/ARM/vfp-regs-dwarf.ll
index b67f770bfd13..eca0c26e5562 100644
--- a/test/CodeGen/ARM/vfp-regs-dwarf.ll
+++ b/test/CodeGen/ARM/vfp-regs-dwarf.ll
@@ -31,14 +31,14 @@ define void @stack_offsets() {
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!8, !9}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/Users/tim/llvm/build/tmp.c] [DW_LANG_C99]
-!1 = !{!"tmp.c", !"/Users/tim/llvm/build"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "tmp.c", directory: "/Users/tim/llvm/build")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00bar\00bar\00\001\000\001\000\006\000\000\001", !1, !5, !6, null, void ()* @stack_offsets, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [bar]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/Users/tim/llvm/build/tmp.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "bar", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void ()* @stack_offsets, variables: !2)
+!5 = !DIFile(filename: "tmp.c", directory: "/Users/tim/llvm/build")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
 !8 = !{i32 2, !"Dwarf Version", i32 4}
-!9 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !{i32 1, !"Debug Info Version", i32 3}
 
diff --git a/test/CodeGen/ARM/vfp.ll b/test/CodeGen/ARM/vfp.ll
index 5d2943cbfd2f..03c0354aa1df 100644
--- a/test/CodeGen/ARM/vfp.ll
+++ b/test/CodeGen/ARM/vfp.ll
@@ -2,8 +2,8 @@
 ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+vfp2 -disable-post-ra -regalloc=basic | FileCheck %s
 
 define void @test(float* %P, double* %D) {
-	%A = load float* %P		; <float> [#uses=1]
-	%B = load double* %D		; <double> [#uses=1]
+	%A = load float, float* %P		; <float> [#uses=1]
+	%B = load double, double* %D		; <double> [#uses=1]
 	store float %A, float* %P
 	store double %B, double* %D
 	ret void
@@ -15,11 +15,11 @@ declare double @fabs(double)
 
 define void @test_abs(float* %P, double* %D) {
 ;CHECK-LABEL: test_abs:
-	%a = load float* %P		; <float> [#uses=1]
+	%a = load float, float* %P		; <float> [#uses=1]
 ;CHECK: vabs.f32
 	%b = call float @fabsf( float %a ) readnone	; <float> [#uses=1]
 	store float %b, float* %P
-	%A = load double* %D		; <double> [#uses=1]
+	%A = load double, double* %D		; <double> [#uses=1]
 ;CHECK: vabs.f64
 	%B = call double @fabs( double %A ) readnone	; <double> [#uses=1]
 	store double %B, double* %D
@@ -28,10 +28,10 @@ define void @test_abs(float* %P, double* %D) {
 
 define void @test_add(float* %P, double* %D) {
 ;CHECK-LABEL: test_add:
-	%a = load float* %P		; <float> [#uses=2]
+	%a = load float, float* %P		; <float> [#uses=2]
 	%b = fadd float %a, %a		; <float> [#uses=1]
 	store float %b, float* %P
-	%A = load double* %D		; <double> [#uses=2]
+	%A = load double, double* %D		; <double> [#uses=2]
 	%B = fadd double %A, %A		; <double> [#uses=1]
 	store double %B, double* %D
 	ret void
@@ -39,11 +39,11 @@ define void @test_add(float* %P, double* %D) {
 
 define void @test_ext_round(float* %P, double* %D) {
 ;CHECK-LABEL: test_ext_round:
-	%a = load float* %P		; <float> [#uses=1]
+	%a = load float, float* %P		; <float> [#uses=1]
 ;CHECK: vcvt.f64.f32
 ;CHECK: vcvt.f32.f64
 	%b = fpext float %a to double		; <double> [#uses=1]
-	%A = load double* %D		; <double> [#uses=1]
+	%A = load double, double* %D		; <double> [#uses=1]
 	%B = fptrunc double %A to float		; <float> [#uses=1]
 	store double %b, double* %D
 	store float %B, float* %P
@@ -52,9 +52,9 @@ define void @test_ext_round(float* %P, double* %D) {
 
 define void @test_fma(float* %P1, float* %P2, float* %P3) {
 ;CHECK-LABEL: test_fma:
-	%a1 = load float* %P1		; <float> [#uses=1]
-	%a2 = load float* %P2		; <float> [#uses=1]
-	%a3 = load float* %P3		; <float> [#uses=1]
+	%a1 = load float, float* %P1		; <float> [#uses=1]
+	%a2 = load float, float* %P2		; <float> [#uses=1]
+	%a3 = load float, float* %P3		; <float> [#uses=1]
 ;CHECK: vnmls.f32
 	%X = fmul float %a1, %a2		; <float> [#uses=1]
 	%Y = fsub float %X, %a3		; <float> [#uses=1]
@@ -64,7 +64,7 @@ define void @test_fma(float* %P1, float* %P2, float* %P3) {
 
 define i32 @test_ftoi(float* %P1) {
 ;CHECK-LABEL: test_ftoi:
-	%a1 = load float* %P1		; <float> [#uses=1]
+	%a1 = load float, float* %P1		; <float> [#uses=1]
 ;CHECK: vcvt.s32.f32
 	%b1 = fptosi float %a1 to i32		; <i32> [#uses=1]
 	ret i32 %b1
@@ -72,7 +72,7 @@ define i32 @test_ftoi(float* %P1) {
 
 define i32 @test_ftou(float* %P1) {
 ;CHECK-LABEL: test_ftou:
-	%a1 = load float* %P1		; <float> [#uses=1]
+	%a1 = load float, float* %P1		; <float> [#uses=1]
 ;CHECK: vcvt.u32.f32
 	%b1 = fptoui float %a1 to i32		; <i32> [#uses=1]
 	ret i32 %b1
@@ -80,7 +80,7 @@ define i32 @test_ftou(float* %P1) {
 
 define i32 @test_dtoi(double* %P1) {
 ;CHECK-LABEL: test_dtoi:
-	%a1 = load double* %P1		; <double> [#uses=1]
+	%a1 = load double, double* %P1		; <double> [#uses=1]
 ;CHECK: vcvt.s32.f64
 	%b1 = fptosi double %a1 to i32		; <i32> [#uses=1]
 	ret i32 %b1
@@ -88,7 +88,7 @@ define i32 @test_dtoi(double* %P1) {
 
 define i32 @test_dtou(double* %P1) {
 ;CHECK-LABEL: test_dtou:
-	%a1 = load double* %P1		; <double> [#uses=1]
+	%a1 = load double, double* %P1		; <double> [#uses=1]
 ;CHECK: vcvt.u32.f64
 	%b1 = fptoui double %a1 to i32		; <i32> [#uses=1]
 	ret i32 %b1
@@ -113,9 +113,9 @@ define void @test_utod2(double* %P1, i8 %X) {
 define void @test_cmp(float* %glob, i32 %X) {
 ;CHECK-LABEL: test_cmp:
 entry:
-	%tmp = load float* %glob		; <float> [#uses=2]
-	%tmp3 = getelementptr float* %glob, i32 2		; <float*> [#uses=1]
-	%tmp4 = load float* %tmp3		; <float> [#uses=2]
+	%tmp = load float, float* %glob		; <float> [#uses=2]
+	%tmp3 = getelementptr float, float* %glob, i32 2		; <float*> [#uses=1]
+	%tmp4 = load float, float* %tmp3		; <float> [#uses=2]
 	%tmp.upgrd.1 = fcmp oeq float %tmp, %tmp4		; <i1> [#uses=1]
 	%tmp5 = fcmp uno float %tmp, %tmp4		; <i1> [#uses=1]
 	%tmp6 = or i1 %tmp.upgrd.1, %tmp5		; <i1> [#uses=1]
@@ -124,11 +124,11 @@ entry:
 	br i1 %tmp6, label %cond_true, label %cond_false
 
 cond_true:		; preds = %entry
-	%tmp.upgrd.2 = tail call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp.upgrd.2 = tail call i32 (...) @bar( )		; <i32> [#uses=0]
 	ret void
 
 cond_false:		; preds = %entry
-	%tmp7 = tail call i32 (...)* @baz( )		; <i32> [#uses=0]
+	%tmp7 = tail call i32 (...) @baz( )		; <i32> [#uses=0]
 	ret void
 }
 
@@ -141,16 +141,16 @@ declare i32 @baz(...)
 define void @test_cmpfp0(float* %glob, i32 %X) {
 ;CHECK-LABEL: test_cmpfp0:
 entry:
-	%tmp = load float* %glob		; <float> [#uses=1]
+	%tmp = load float, float* %glob		; <float> [#uses=1]
 ;CHECK: vcmpe.f32
 	%tmp.upgrd.3 = fcmp ogt float %tmp, 0.000000e+00		; <i1> [#uses=1]
 	br i1 %tmp.upgrd.3, label %cond_true, label %cond_false
 
 cond_true:		; preds = %entry
-	%tmp.upgrd.4 = tail call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp.upgrd.4 = tail call i32 (...) @bar( )		; <i32> [#uses=0]
 	ret void
 
 cond_false:		; preds = %entry
-	%tmp1 = tail call i32 (...)* @baz( )		; <i32> [#uses=0]
+	%tmp1 = tail call i32 (...) @baz( )		; <i32> [#uses=0]
 	ret void
 }
diff --git a/test/CodeGen/ARM/vget_lane.ll b/test/CodeGen/ARM/vget_lane.ll
index 2518ee2278cc..d4cbfad5be6f 100644
--- a/test/CodeGen/ARM/vget_lane.ll
+++ b/test/CodeGen/ARM/vget_lane.ll
@@ -5,7 +5,7 @@ target triple = "thumbv7-elf"
 define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vget_lanes8:
 ;CHECK: vmov.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = extractelement <8 x i8> %tmp1, i32 1
 	%tmp3 = sext i8 %tmp2 to i32
 	ret i32 %tmp3
@@ -14,7 +14,7 @@ define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
 define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vget_lanes16:
 ;CHECK: vmov.s16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = extractelement <4 x i16> %tmp1, i32 1
 	%tmp3 = sext i16 %tmp2 to i32
 	ret i32 %tmp3
@@ -23,7 +23,7 @@ define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
 define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vget_laneu8:
 ;CHECK: vmov.u8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = extractelement <8 x i8> %tmp1, i32 1
 	%tmp3 = zext i8 %tmp2 to i32
 	ret i32 %tmp3
@@ -32,7 +32,7 @@ define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
 define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vget_laneu16:
 ;CHECK: vmov.u16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = extractelement <4 x i16> %tmp1, i32 1
 	%tmp3 = zext i16 %tmp2 to i32
 	ret i32 %tmp3
@@ -42,7 +42,7 @@ define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
 define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vget_lanei32:
 ;CHECK: vmov.32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = add <2 x i32> %tmp1, %tmp1
 	%tmp3 = extractelement <2 x i32> %tmp2, i32 1
 	ret i32 %tmp3
@@ -51,7 +51,7 @@ define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
 define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vgetQ_lanes8:
 ;CHECK: vmov.s8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = extractelement <16 x i8> %tmp1, i32 1
 	%tmp3 = sext i8 %tmp2 to i32
 	ret i32 %tmp3
@@ -60,7 +60,7 @@ define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
 define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vgetQ_lanes16:
 ;CHECK: vmov.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = extractelement <8 x i16> %tmp1, i32 1
 	%tmp3 = sext i16 %tmp2 to i32
 	ret i32 %tmp3
@@ -69,7 +69,7 @@ define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
 define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vgetQ_laneu8:
 ;CHECK: vmov.u8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = extractelement <16 x i8> %tmp1, i32 1
 	%tmp3 = zext i8 %tmp2 to i32
 	ret i32 %tmp3
@@ -78,7 +78,7 @@ define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
 define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vgetQ_laneu16:
 ;CHECK: vmov.u16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = extractelement <8 x i16> %tmp1, i32 1
 	%tmp3 = zext i16 %tmp2 to i32
 	ret i32 %tmp3
@@ -88,7 +88,7 @@ define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
 define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vgetQ_lanei32:
 ;CHECK: vmov.32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = add <4 x i32> %tmp1, %tmp1
 	%tmp3 = extractelement <4 x i32> %tmp2, i32 1
 	ret i32 %tmp3
@@ -100,7 +100,7 @@ entry:
   %arg0_uint16x4_t = alloca <4 x i16>             ; <<4 x i16>*> [#uses=1]
   %out_uint16_t = alloca i16                      ; <i16*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  %0 = load <4 x i16>* %arg0_uint16x4_t, align 8  ; <<4 x i16>> [#uses=1]
+  %0 = load <4 x i16>, <4 x i16>* %arg0_uint16x4_t, align 8  ; <<4 x i16>> [#uses=1]
   %1 = extractelement <4 x i16> %0, i32 1         ; <i16> [#uses=1]
   %2 = add i16 %1, %1
   store i16 %2, i16* %out_uint16_t, align 2
@@ -116,7 +116,7 @@ entry:
   %arg0_uint8x8_t = alloca <8 x i8>               ; <<8 x i8>*> [#uses=1]
   %out_uint8_t = alloca i8                        ; <i8*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  %0 = load <8 x i8>* %arg0_uint8x8_t, align 8    ; <<8 x i8>> [#uses=1]
+  %0 = load <8 x i8>, <8 x i8>* %arg0_uint8x8_t, align 8    ; <<8 x i8>> [#uses=1]
   %1 = extractelement <8 x i8> %0, i32 1          ; <i8> [#uses=1]
   %2 = add i8 %1, %1
   store i8 %2, i8* %out_uint8_t, align 1
@@ -132,7 +132,7 @@ entry:
   %arg0_uint16x8_t = alloca <8 x i16>             ; <<8 x i16>*> [#uses=1]
   %out_uint16_t = alloca i16                      ; <i16*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  %0 = load <8 x i16>* %arg0_uint16x8_t, align 16 ; <<8 x i16>> [#uses=1]
+  %0 = load <8 x i16>, <8 x i16>* %arg0_uint16x8_t, align 16 ; <<8 x i16>> [#uses=1]
   %1 = extractelement <8 x i16> %0, i32 1         ; <i16> [#uses=1]
   %2 = add i16 %1, %1
   store i16 %2, i16* %out_uint16_t, align 2
@@ -148,7 +148,7 @@ entry:
   %arg0_uint8x16_t = alloca <16 x i8>             ; <<16 x i8>*> [#uses=1]
   %out_uint8_t = alloca i8                        ; <i8*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  %0 = load <16 x i8>* %arg0_uint8x16_t, align 16 ; <<16 x i8>> [#uses=1]
+  %0 = load <16 x i8>, <16 x i8>* %arg0_uint8x16_t, align 16 ; <<16 x i8>> [#uses=1]
   %1 = extractelement <16 x i8> %0, i32 1         ; <i8> [#uses=1]
   %2 = add i8 %1, %1
   store i8 %2, i8* %out_uint8_t, align 1
@@ -161,7 +161,7 @@ return:                                           ; preds = %entry
 define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind {
 ;CHECK-LABEL: vset_lane8:
 ;CHECK: vmov.8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = insertelement <8 x i8> %tmp1, i8 %B, i32 1
 	ret <8 x i8> %tmp2
 }
@@ -169,7 +169,7 @@ define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind {
 define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind {
 ;CHECK-LABEL: vset_lane16:
 ;CHECK: vmov.16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = insertelement <4 x i16> %tmp1, i16 %B, i32 1
 	ret <4 x i16> %tmp2
 }
@@ -177,7 +177,7 @@ define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind {
 define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind {
 ;CHECK-LABEL: vset_lane32:
 ;CHECK: vmov.32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = insertelement <2 x i32> %tmp1, i32 %B, i32 1
 	ret <2 x i32> %tmp2
 }
@@ -185,7 +185,7 @@ define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind {
 define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind {
 ;CHECK-LABEL: vsetQ_lane8:
 ;CHECK: vmov.8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = insertelement <16 x i8> %tmp1, i8 %B, i32 1
 	ret <16 x i8> %tmp2
 }
@@ -193,7 +193,7 @@ define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind {
 define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind {
 ;CHECK-LABEL: vsetQ_lane16:
 ;CHECK: vmov.16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = insertelement <8 x i16> %tmp1, i16 %B, i32 1
 	ret <8 x i16> %tmp2
 }
@@ -201,7 +201,7 @@ define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind {
 define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
 ;CHECK-LABEL: vsetQ_lane32:
 ;CHECK: vmov.32 d{{.*}}[1], r1
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1
 	ret <4 x i32> %tmp2
 }
@@ -219,14 +219,14 @@ entry:
 ; be an immediate constant.  Make sure a variable lane number is handled.
 
 define i32 @vget_variable_lanes8(<8 x i8>* %A, i32 %B) nounwind {
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = extractelement <8 x i8> %tmp1, i32 %B
 	%tmp3 = sext i8 %tmp2 to i32
 	ret i32 %tmp3
 }
 
 define i32 @vgetQ_variable_lanei32(<4 x i32>* %A, i32 %B) nounwind {
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = add <4 x i32> %tmp1, %tmp1
 	%tmp3 = extractelement <4 x i32> %tmp2, i32 %B
 	ret i32 %tmp3
diff --git a/test/CodeGen/ARM/vhadd.ll b/test/CodeGen/ARM/vhadd.ll
index 6183db3702b3..01e239d5c73a 100644
--- a/test/CodeGen/ARM/vhadd.ll
+++ b/test/CodeGen/ARM/vhadd.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vhadds8:
 ;CHECK: vhadd.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vhadds16:
 ;CHECK: vhadd.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vhadds32:
 ;CHECK: vhadd.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vhaddu8:
 ;CHECK: vhadd.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -39,8 +39,8 @@ define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vhaddu16:
 ;CHECK: vhadd.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -48,8 +48,8 @@ define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vhaddu32:
 ;CHECK: vhadd.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -57,8 +57,8 @@ define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vhaddQs8:
 ;CHECK: vhadd.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -66,8 +66,8 @@ define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vhaddQs16:
 ;CHECK: vhadd.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -75,8 +75,8 @@ define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vhaddQs32:
 ;CHECK: vhadd.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -84,8 +84,8 @@ define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vhaddQu8:
 ;CHECK: vhadd.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -93,8 +93,8 @@ define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vhaddQu16:
 ;CHECK: vhadd.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -102,8 +102,8 @@ define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vhaddQu32:
 ;CHECK: vhadd.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -127,8 +127,8 @@ declare <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind rea
 define <8 x i8> @vrhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vrhadds8:
 ;CHECK: vrhadd.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -136,8 +136,8 @@ define <8 x i8> @vrhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vrhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vrhadds16:
 ;CHECK: vrhadd.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -145,8 +145,8 @@ define <4 x i16> @vrhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vrhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vrhadds32:
 ;CHECK: vrhadd.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vrhadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -154,8 +154,8 @@ define <2 x i32> @vrhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @vrhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vrhaddu8:
 ;CHECK: vrhadd.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vrhaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -163,8 +163,8 @@ define <8 x i8> @vrhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vrhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vrhaddu16:
 ;CHECK: vrhadd.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -172,8 +172,8 @@ define <4 x i16> @vrhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vrhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vrhaddu32:
 ;CHECK: vrhadd.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vrhaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -181,8 +181,8 @@ define <2 x i32> @vrhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @vrhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vrhaddQs8:
 ;CHECK: vrhadd.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -190,8 +190,8 @@ define <16 x i8> @vrhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vrhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vrhaddQs16:
 ;CHECK: vrhadd.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -199,8 +199,8 @@ define <8 x i16> @vrhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vrhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vrhaddQs32:
 ;CHECK: vrhadd.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -208,8 +208,8 @@ define <4 x i32> @vrhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <16 x i8> @vrhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vrhaddQu8:
 ;CHECK: vrhadd.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -217,8 +217,8 @@ define <16 x i8> @vrhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vrhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vrhaddQu16:
 ;CHECK: vrhadd.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -226,8 +226,8 @@ define <8 x i16> @vrhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vrhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vrhaddQu32:
 ;CHECK: vrhadd.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
diff --git a/test/CodeGen/ARM/vhsub.ll b/test/CodeGen/ARM/vhsub.ll
index f1a0cb27f576..7b3b29ac6e1a 100644
--- a/test/CodeGen/ARM/vhsub.ll
+++ b/test/CodeGen/ARM/vhsub.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vhsubs8:
 ;CHECK: vhsub.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vhsubs16:
 ;CHECK: vhsub.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vhsubs32:
 ;CHECK: vhsub.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vhsubu8:
 ;CHECK: vhsub.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -39,8 +39,8 @@ define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vhsubu16:
 ;CHECK: vhsub.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -48,8 +48,8 @@ define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vhsubu32:
 ;CHECK: vhsub.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -57,8 +57,8 @@ define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vhsubQs8:
 ;CHECK: vhsub.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -66,8 +66,8 @@ define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vhsubQs16:
 ;CHECK: vhsub.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -75,8 +75,8 @@ define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vhsubQs32:
 ;CHECK: vhsub.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -84,8 +84,8 @@ define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vhsubQu8:
 ;CHECK: vhsub.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -93,8 +93,8 @@ define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vhsubQu16:
 ;CHECK: vhsub.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -102,8 +102,8 @@ define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vhsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vhsubQu32:
 ;CHECK: vhsub.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
diff --git a/test/CodeGen/ARM/vicmp.ll b/test/CodeGen/ARM/vicmp.ll
index bebb32062f71..21b104a0d045 100644
--- a/test/CodeGen/ARM/vicmp.ll
+++ b/test/CodeGen/ARM/vicmp.ll
@@ -10,8 +10,8 @@ define <8 x i8> @vcnei8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vcnei8:
 ;CHECK: vceq.i8
 ;CHECK-NEXT: vmvn
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = icmp ne <8 x i8> %tmp1, %tmp2
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
 	ret <8 x i8> %tmp4
@@ -21,8 +21,8 @@ define <4 x i16> @vcnei16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vcnei16:
 ;CHECK: vceq.i16
 ;CHECK-NEXT: vmvn
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = icmp ne <4 x i16> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
 	ret <4 x i16> %tmp4
@@ -32,8 +32,8 @@ define <2 x i32> @vcnei32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vcnei32:
 ;CHECK: vceq.i32
 ;CHECK-NEXT: vmvn
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = icmp ne <2 x i32> %tmp1, %tmp2
         %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
 	ret <2 x i32> %tmp4
@@ -43,8 +43,8 @@ define <16 x i8> @vcneQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vcneQi8:
 ;CHECK: vceq.i8
 ;CHECK-NEXT: vmvn
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = icmp ne <16 x i8> %tmp1, %tmp2
         %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
 	ret <16 x i8> %tmp4
@@ -54,8 +54,8 @@ define <8 x i16> @vcneQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vcneQi16:
 ;CHECK: vceq.i16
 ;CHECK-NEXT: vmvn
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = icmp ne <8 x i16> %tmp1, %tmp2
         %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
 	ret <8 x i16> %tmp4
@@ -65,8 +65,8 @@ define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vcneQi32:
 ;CHECK: vceq.i32
 ;CHECK-NEXT: vmvn
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = icmp ne <4 x i32> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
 	ret <4 x i32> %tmp4
@@ -75,8 +75,8 @@ define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vcltQs8:
 ;CHECK: vcgt.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = icmp slt <16 x i8> %tmp1, %tmp2
         %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
 	ret <16 x i8> %tmp4
@@ -85,8 +85,8 @@ define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vcles16:
 ;CHECK: vcge.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = icmp sle <4 x i16> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
 	ret <4 x i16> %tmp4
@@ -95,8 +95,8 @@ define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vcltu16:
 ;CHECK: vcgt.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = icmp ult <4 x i16> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
 	ret <4 x i16> %tmp4
@@ -105,8 +105,8 @@ define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <4 x i32> @vcleQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vcleQu32:
 ;CHECK: vcge.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = icmp ule <4 x i32> %tmp1, %tmp2
         %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
 	ret <4 x i32> %tmp4
diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll
index db640f54b0e6..8064ea4a320a 100644
--- a/test/CodeGen/ARM/vld1.ll
+++ b/test/CodeGen/ARM/vld1.ll
@@ -23,10 +23,10 @@ define <4 x i16> @vld1i16(i16* %A) nounwind {
 define <4 x i16> @vld1i16_update(i16** %ptr) nounwind {
 ;CHECK-LABEL: vld1i16_update:
 ;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]!
-	%A = load i16** %ptr
+	%A = load i16*, i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1)
-	%tmp2 = getelementptr i16* %A, i32 4
+	%tmp2 = getelementptr i16, i16* %A, i32 4
 	       store i16* %tmp2, i16** %ptr
 	ret <4 x i16> %tmp1
 }
@@ -43,10 +43,10 @@ define <2 x i32> @vld1i32(i32* %A) nounwind {
 define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind {
 ;CHECK-LABEL: vld1i32_update:
 ;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}}
-	%A = load i32** %ptr
+	%A = load i32*, i32** %ptr
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1)
-	%tmp2 = getelementptr i32* %A, i32 %inc
+	%tmp2 = getelementptr i32, i32* %A, i32 %inc
 	store i32* %tmp2, i32** %ptr
 	ret <2 x i32> %tmp1
 }
@@ -79,9 +79,9 @@ define <16 x i8> @vld1Qi8(i8* %A) nounwind {
 define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
 ;CHECK-LABEL: vld1Qi8_update:
 ;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}:64]!
-	%A = load i8** %ptr
+	%A = load i8*, i8** %ptr
 	%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
-	%tmp2 = getelementptr i8* %A, i32 16
+	%tmp2 = getelementptr i8, i8* %A, i32 16
 	store i8* %tmp2, i8** %ptr
 	ret <16 x i8> %tmp1
 }
diff --git a/test/CodeGen/ARM/vld2.ll b/test/CodeGen/ARM/vld2.ll
index 7ac5cc709b33..391b49152cd9 100644
--- a/test/CodeGen/ARM/vld2.ll
+++ b/test/CodeGen/ARM/vld2.ll
@@ -60,13 +60,13 @@ define <2 x float> @vld2f(float* %A) nounwind {
 define <2 x float> @vld2f_update(float** %ptr) nounwind {
 ;CHECK-LABEL: vld2f_update:
 ;CHECK: vld2.32 {d16, d17}, [r1]!
-	%A = load float** %ptr
+	%A = load float*, float** %ptr
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 1)
 	%tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
 	%tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
 	%tmp4 = fadd <2 x float> %tmp2, %tmp3
-	%tmp5 = getelementptr float* %A, i32 4
+	%tmp5 = getelementptr float, float* %A, i32 4
 	store float* %tmp5, float** %ptr
 	ret <2 x float> %tmp4
 }
@@ -98,12 +98,12 @@ define <16 x i8> @vld2Qi8(i8* %A) nounwind {
 define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind {
 ;CHECK-LABEL: vld2Qi8_update:
 ;CHECK: vld2.8 {d16, d17, d18, d19}, [r2:128], r1
-	%A = load i8** %ptr
+	%A = load i8*, i8** %ptr
 	%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 16)
         %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
         %tmp4 = add <16 x i8> %tmp2, %tmp3
-	%tmp5 = getelementptr i8* %A, i32 %inc
+	%tmp5 = getelementptr i8, i8* %A, i32 %inc
 	store i8* %tmp5, i8** %ptr
 	ret <16 x i8> %tmp4
 }
diff --git a/test/CodeGen/ARM/vld3.ll b/test/CodeGen/ARM/vld3.ll
index 171a03c24da1..0d14179ba73a 100644
--- a/test/CodeGen/ARM/vld3.ll
+++ b/test/CodeGen/ARM/vld3.ll
@@ -38,13 +38,13 @@ define <4 x i16> @vld3i16(i16* %A) nounwind {
 define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind {
 ;CHECK-LABEL: vld3i16_update:
 ;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}}
-	%A = load i16** %ptr
+	%A = load i16*, i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1)
 	%tmp2 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 0
 	%tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 2
 	%tmp4 = add <4 x i16> %tmp2, %tmp3
-	%tmp5 = getelementptr i16* %A, i32 %inc
+	%tmp5 = getelementptr i16, i16* %A, i32 %inc
 	store i16* %tmp5, i16** %ptr
 	ret <4 x i16> %tmp4
 }
@@ -88,7 +88,7 @@ define <1 x i64> @vld3i64_update(i64** %ptr, i64* %A) nounwind {
 ;CHECK: vld1.64	{d16, d17, d18}, [r1:64]!
         %tmp0 = bitcast i64* %A to i8*
         %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0, i32 16)
-        %tmp5 = getelementptr i64* %A, i32 3
+        %tmp5 = getelementptr i64, i64* %A, i32 3
         store i64* %tmp5, i64** %ptr
         %tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 2
@@ -137,13 +137,13 @@ define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind {
 ;CHECK-LABEL: vld3Qi32_update:
 ;CHECK: vld3.32 {d16, d18, d20}, [r[[R:[0-9]+]]]!
 ;CHECK: vld3.32 {d17, d19, d21}, [r[[R]]]!
-	%A = load i32** %ptr
+	%A = load i32*, i32** %ptr
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8* %tmp0, i32 1)
 	%tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0
 	%tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2
 	%tmp4 = add <4 x i32> %tmp2, %tmp3
-	%tmp5 = getelementptr i32* %A, i32 12
+	%tmp5 = getelementptr i32, i32* %A, i32 12
 	store i32* %tmp5, i32** %ptr
 	ret <4 x i32> %tmp4
 }
diff --git a/test/CodeGen/ARM/vld4.ll b/test/CodeGen/ARM/vld4.ll
index 94ad143ae0fd..575e0fa717fb 100644
--- a/test/CodeGen/ARM/vld4.ll
+++ b/test/CodeGen/ARM/vld4.ll
@@ -26,12 +26,12 @@ define <8 x i8> @vld4i8(i8* %A) nounwind {
 define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind {
 ;CHECK-LABEL: vld4i8_update:
 ;CHECK: vld4.8 {d16, d17, d18, d19}, [r2:128], r1
-	%A = load i8** %ptr
+	%A = load i8*, i8** %ptr
 	%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16)
 	%tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
 	%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2
 	%tmp4 = add <8 x i8> %tmp2, %tmp3
-	%tmp5 = getelementptr i8* %A, i32 %inc
+	%tmp5 = getelementptr i8, i8* %A, i32 %inc
 	store i8* %tmp5, i8** %ptr
 	ret <8 x i8> %tmp4
 }
@@ -88,7 +88,7 @@ define <1 x i64> @vld4i64_update(i64** %ptr, i64* %A) nounwind {
 ;CHECK: vld1.64 {d16, d17, d18, d19}, [r1:256]!
         %tmp0 = bitcast i64* %A to i8*
         %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 64)
-        %tmp5 = getelementptr i64* %A, i32 4
+        %tmp5 = getelementptr i64, i64* %A, i32 4
         store i64* %tmp5, i64** %ptr
         %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2
@@ -126,13 +126,13 @@ define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind {
 ;CHECK-LABEL: vld4Qi16_update:
 ;CHECK: vld4.16 {d16, d18, d20, d22}, [r1:64]!
 ;CHECK: vld4.16 {d17, d19, d21, d23}, [r1:64]!
-	%A = load i16** %ptr
+	%A = load i16*, i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 8)
 	%tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0
 	%tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2
 	%tmp4 = add <8 x i16> %tmp2, %tmp3
-	%tmp5 = getelementptr i16* %A, i32 32
+	%tmp5 = getelementptr i16, i16* %A, i32 32
 	store i16* %tmp5, i16** %ptr
 	ret <8 x i16> %tmp4
 }
diff --git a/test/CodeGen/ARM/vlddup.ll b/test/CodeGen/ARM/vlddup.ll
index 64aac562c1eb..09304d87d53b 100644
--- a/test/CodeGen/ARM/vlddup.ll
+++ b/test/CodeGen/ARM/vlddup.ll
@@ -4,7 +4,7 @@ define <8 x i8> @vld1dupi8(i8* %A) nounwind {
 ;CHECK-LABEL: vld1dupi8:
 ;Check the (default) alignment value.
 ;CHECK: vld1.8 {d16[]}, [r0]
-	%tmp1 = load i8* %A, align 8
+	%tmp1 = load i8, i8* %A, align 8
 	%tmp2 = insertelement <8 x i8> undef, i8 %tmp1, i32 0
 	%tmp3 = shufflevector <8 x i8> %tmp2, <8 x i8> undef, <8 x i32> zeroinitializer
         ret <8 x i8> %tmp3
@@ -14,7 +14,7 @@ define <4 x i16> @vld1dupi16(i16* %A) nounwind {
 ;CHECK-LABEL: vld1dupi16:
 ;Check the alignment value.  Max for this instruction is 16 bits:
 ;CHECK: vld1.16 {d16[]}, [r0:16]
-	%tmp1 = load i16* %A, align 8
+	%tmp1 = load i16, i16* %A, align 8
 	%tmp2 = insertelement <4 x i16> undef, i16 %tmp1, i32 0
 	%tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> undef, <4 x i32> zeroinitializer
         ret <4 x i16> %tmp3
@@ -24,7 +24,7 @@ define <2 x i32> @vld1dupi32(i32* %A) nounwind {
 ;CHECK-LABEL: vld1dupi32:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vld1.32 {d16[]}, [r0:32]
-	%tmp1 = load i32* %A, align 8
+	%tmp1 = load i32, i32* %A, align 8
 	%tmp2 = insertelement <2 x i32> undef, i32 %tmp1, i32 0
 	%tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> undef, <2 x i32> zeroinitializer
         ret <2 x i32> %tmp3
@@ -33,7 +33,7 @@ define <2 x i32> @vld1dupi32(i32* %A) nounwind {
 define <2 x float> @vld1dupf(float* %A) nounwind {
 ;CHECK-LABEL: vld1dupf:
 ;CHECK: vld1.32 {d16[]}, [r0:32]
-	%tmp0 = load float* %A
+	%tmp0 = load float, float* %A
         %tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
         %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
         ret <2 x float> %tmp2
@@ -43,7 +43,7 @@ define <16 x i8> @vld1dupQi8(i8* %A) nounwind {
 ;CHECK-LABEL: vld1dupQi8:
 ;Check the (default) alignment value.
 ;CHECK: vld1.8 {d16[], d17[]}, [r0]
-	%tmp1 = load i8* %A, align 8
+	%tmp1 = load i8, i8* %A, align 8
 	%tmp2 = insertelement <16 x i8> undef, i8 %tmp1, i32 0
 	%tmp3 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <16 x i32> zeroinitializer
         ret <16 x i8> %tmp3
@@ -52,7 +52,7 @@ define <16 x i8> @vld1dupQi8(i8* %A) nounwind {
 define <4 x float> @vld1dupQf(float* %A) nounwind {
 ;CHECK-LABEL: vld1dupQf:
 ;CHECK: vld1.32 {d16[], d17[]}, [r0:32]
-        %tmp0 = load float* %A
+        %tmp0 = load float, float* %A
         %tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
         %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
         ret <4 x float> %tmp2
@@ -93,7 +93,7 @@ define <4 x i16> @vld2dupi16(i8* %A) nounwind {
 define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind {
 ;CHECK-LABEL: vld2dupi16_update:
 ;CHECK: vld2.16 {d16[], d17[]}, [r1]!
-	%A = load i16** %ptr
+	%A = load i16*, i16** %ptr
         %A2 = bitcast i16* %A to i8*
 	%tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %A2, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2)
 	%tmp1 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 0
@@ -101,7 +101,7 @@ define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind {
 	%tmp3 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 1
 	%tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer
 	%tmp5 = add <4 x i16> %tmp2, %tmp4
-	%tmp6 = getelementptr i16* %A, i32 2
+	%tmp6 = getelementptr i16, i16* %A, i32 2
 	store i16* %tmp6, i16** %ptr
 	ret <4 x i16> %tmp5
 }
@@ -130,7 +130,7 @@ declare %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i8*, <2 x i32>,
 define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind {
 ;CHECK-LABEL: vld3dupi8_update:
 ;CHECK: vld3.8 {d16[], d17[], d18[]}, [r2], r1
-	%A = load i8** %ptr
+	%A = load i8*, i8** %ptr
 	%tmp0 = tail call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 8)
 	%tmp1 = extractvalue %struct.__neon_int8x8x3_t %tmp0, 0
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
@@ -140,7 +140,7 @@ define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind {
 	%tmp6 = shufflevector <8 x i8> %tmp5, <8 x i8> undef, <8 x i32> zeroinitializer
 	%tmp7 = add <8 x i8> %tmp2, %tmp4
 	%tmp8 = add <8 x i8> %tmp7, %tmp6
-	%tmp9 = getelementptr i8* %A, i32 %inc
+	%tmp9 = getelementptr i8, i8* %A, i32 %inc
 	store i8* %tmp9, i8** %ptr
 	ret <8 x i8> %tmp8
 }
@@ -171,7 +171,7 @@ declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8*, <4 x i16>,
 define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind {
 ;CHECK-LABEL: vld4dupi16_update:
 ;CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r1]!
-	%A = load i16** %ptr
+	%A = load i16*, i16** %ptr
         %A2 = bitcast i16* %A to i8*
 	%tmp0 = tail call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8* %A2, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 1)
 	%tmp1 = extractvalue %struct.__neon_int16x4x4_t %tmp0, 0
@@ -185,7 +185,7 @@ define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind {
 	%tmp9 = add <4 x i16> %tmp2, %tmp4
 	%tmp10 = add <4 x i16> %tmp6, %tmp8
 	%tmp11 = add <4 x i16> %tmp9, %tmp10
-	%tmp12 = getelementptr i16* %A, i32 4
+	%tmp12 = getelementptr i16, i16* %A, i32 4
 	store i16* %tmp12, i16** %ptr
 	ret <4 x i16> %tmp11
 }
diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll
index c7d69ff9780a..ac2be7f87f53 100644
--- a/test/CodeGen/ARM/vldlane.ll
+++ b/test/CodeGen/ARM/vldlane.ll
@@ -7,8 +7,8 @@ define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vld1lanei8:
 ;Check the (default) alignment value.
 ;CHECK: vld1.8 {d16[3]}, [r0]
-	%tmp1 = load <8 x i8>* %B
-	%tmp2 = load i8* %A, align 8
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
+	%tmp2 = load i8, i8* %A, align 8
 	%tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 3
         ret <8 x i8> %tmp3
 }
@@ -17,8 +17,8 @@ define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vld1lanei16:
 ;Check the alignment value.  Max for this instruction is 16 bits:
 ;CHECK: vld1.16 {d16[2]}, [r0:16]
-	%tmp1 = load <4 x i16>* %B
-	%tmp2 = load i16* %A, align 8
+	%tmp1 = load <4 x i16>, <4 x i16>* %B
+	%tmp2 = load i16, i16* %A, align 8
 	%tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 2
         ret <4 x i16> %tmp3
 }
@@ -27,8 +27,8 @@ define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vld1lanei32:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vld1.32 {d16[1]}, [r0:32]
-	%tmp1 = load <2 x i32>* %B
-	%tmp2 = load i32* %A, align 8
+	%tmp1 = load <2 x i32>, <2 x i32>* %B
+	%tmp2 = load i32, i32* %A, align 8
 	%tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
         ret <2 x i32> %tmp3
 }
@@ -37,8 +37,8 @@ define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vld1lanei32a32:
 ;Check the alignment value.  Legal values are none or :32.
 ;CHECK: vld1.32 {d16[1]}, [r0:32]
-	%tmp1 = load <2 x i32>* %B
-	%tmp2 = load i32* %A, align 4
+	%tmp1 = load <2 x i32>, <2 x i32>* %B
+	%tmp2 = load i32, i32* %A, align 4
 	%tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
         ret <2 x i32> %tmp3
 }
@@ -46,8 +46,8 @@ define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind {
 define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vld1lanef:
 ;CHECK: vld1.32 {d16[1]}, [r0:32]
-	%tmp1 = load <2 x float>* %B
-	%tmp2 = load float* %A, align 4
+	%tmp1 = load <2 x float>, <2 x float>* %B
+	%tmp2 = load float, float* %A, align 4
 	%tmp3 = insertelement <2 x float> %tmp1, float %tmp2, i32 1
 	ret <2 x float> %tmp3
 }
@@ -55,8 +55,8 @@ define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind {
 define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vld1laneQi8:
 ;CHECK: vld1.8 {d17[1]}, [r0]
-	%tmp1 = load <16 x i8>* %B
-	%tmp2 = load i8* %A, align 8
+	%tmp1 = load <16 x i8>, <16 x i8>* %B
+	%tmp2 = load i8, i8* %A, align 8
 	%tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 9
 	ret <16 x i8> %tmp3
 }
@@ -64,8 +64,8 @@ define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vld1laneQi16:
 ;CHECK: vld1.16 {d17[1]}, [r0:16]
-	%tmp1 = load <8 x i16>* %B
-	%tmp2 = load i16* %A, align 8
+	%tmp1 = load <8 x i16>, <8 x i16>* %B
+	%tmp2 = load i16, i16* %A, align 8
 	%tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 5
 	ret <8 x i16> %tmp3
 }
@@ -73,8 +73,8 @@ define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vld1laneQi32:
 ;CHECK: vld1.32 {d17[1]}, [r0:32]
-	%tmp1 = load <4 x i32>* %B
-	%tmp2 = load i32* %A, align 8
+	%tmp1 = load <4 x i32>, <4 x i32>* %B
+	%tmp2 = load i32, i32* %A, align 8
 	%tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 3
 	ret <4 x i32> %tmp3
 }
@@ -82,8 +82,8 @@ define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vld1laneQf:
 ;CHECK: vld1.32 {d16[0]}, [r0:32]
-	%tmp1 = load <4 x float>* %B
-	%tmp2 = load float* %A
+	%tmp1 = load <4 x float>, <4 x float>* %B
+	%tmp2 = load float, float* %A
 	%tmp3 = insertelement <4 x float> %tmp1, float %tmp2, i32 0
 	ret <4 x float> %tmp3
 }
@@ -101,7 +101,7 @@ define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vld2lanei8:
 ;Check the alignment value.  Max for this instruction is 16 bits:
 ;CHECK: vld2.8 {d16[1], d17[1]}, [r0:16]
-	%tmp1 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
 	%tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
         %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1
@@ -114,7 +114,7 @@ define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vld2.16 {d16[1], d17[1]}, [r0:32]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %B
 	%tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
         %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 1
@@ -126,7 +126,7 @@ define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vld2lanei32:
 ;CHECK: vld2.32
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %B
 	%tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
         %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1
@@ -138,14 +138,14 @@ define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind {
 define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vld2lanei32_update:
 ;CHECK: vld2.32 {d16[1], d17[1]}, [{{r[0-9]+}}]!
-	%A = load i32** %ptr
+	%A = load i32*, i32** %ptr
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %B
 	%tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
 	%tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0
 	%tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1
 	%tmp5 = add <2 x i32> %tmp3, %tmp4
-	%tmp6 = getelementptr i32* %A, i32 2
+	%tmp6 = getelementptr i32, i32* %A, i32 2
 	store i32* %tmp6, i32** %ptr
 	ret <2 x i32> %tmp5
 }
@@ -154,7 +154,7 @@ define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vld2lanef:
 ;CHECK: vld2.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %B
 	%tmp2 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
         %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 1
@@ -167,7 +167,7 @@ define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 ;Check the (default) alignment.
 ;CHECK: vld2.16 {d17[1], d19[1]}, [{{r[0-9]+}}]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %B
 	%tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1)
         %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1
@@ -180,7 +180,7 @@ define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld2.32 {d17[0], d19[0]}, [{{r[0-9]+}}:64]
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %B
 	%tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16)
         %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1
@@ -192,7 +192,7 @@ define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vld2laneQf:
 ;CHECK: vld2.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %B
 	%tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
         %tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 1
@@ -221,7 +221,7 @@ declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8*, <4 x flo
 define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vld3lanei8:
 ;CHECK: vld3.8
-	%tmp1 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
 	%tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
         %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1
@@ -236,7 +236,7 @@ define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind {
 ;Check the (default) alignment value.  VLD3 does not support alignment.
 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %B
 	%tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
         %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 1
@@ -250,7 +250,7 @@ define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vld3lanei32:
 ;CHECK: vld3.32
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %B
 	%tmp2 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
         %tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 1
@@ -264,7 +264,7 @@ define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vld3lanef:
 ;CHECK: vld3.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %B
 	%tmp2 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
         %tmp3 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 1
@@ -279,7 +279,7 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 ;Check the (default) alignment value.  VLD3 does not support alignment.
 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %B
 	%tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8)
         %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1
@@ -293,16 +293,16 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
 ;CHECK-LABEL: vld3laneQi16_update:
 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}], {{r[0-9]+}}
-	%A = load i16** %ptr
+	%A = load i16*, i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %B
 	%tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8)
 	%tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0
 	%tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1
 	%tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2
 	%tmp6 = add <8 x i16> %tmp3, %tmp4
 	%tmp7 = add <8 x i16> %tmp5, %tmp6
-	%tmp8 = getelementptr i16* %A, i32 %inc
+	%tmp8 = getelementptr i16, i16* %A, i32 %inc
 	store i16* %tmp8, i16** %ptr
 	ret <8 x i16> %tmp7
 }
@@ -311,7 +311,7 @@ define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vld3laneQi32:
 ;CHECK: vld3.32
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %B
 	%tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 3, i32 1)
         %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 1
@@ -325,7 +325,7 @@ define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vld3laneQf:
 ;CHECK: vld3.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %B
 	%tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
         %tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 1
@@ -357,7 +357,7 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vld4lanei8:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vld4.8 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}:32]
-	%tmp1 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
 	%tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
         %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
@@ -373,8 +373,8 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
 define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vld4lanei8_update:
 ;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:32]!
-	%A = load i8** %ptr
-	%tmp1 = load <8 x i8>* %B
+	%A = load i8*, i8** %ptr
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
 	%tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
 	%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
 	%tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
@@ -383,7 +383,7 @@ define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
 	%tmp7 = add <8 x i8> %tmp3, %tmp4
 	%tmp8 = add <8 x i8> %tmp5, %tmp6
 	%tmp9 = add <8 x i8> %tmp7, %tmp8
-	%tmp10 = getelementptr i8* %A, i32 4
+	%tmp10 = getelementptr i8, i8* %A, i32 4
 	store i8* %tmp10, i8** %ptr
 	ret <8 x i8> %tmp9
 }
@@ -394,7 +394,7 @@ define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind {
 ;being loaded is ignored.
 ;CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %B
 	%tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 4)
         %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 1
@@ -412,7 +412,7 @@ define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind {
 ;it is smaller than the total size of the memory being loaded.
 ;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:64]
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %B
 	%tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 8)
         %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 1
@@ -428,7 +428,7 @@ define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vld4lanef:
 ;CHECK: vld4.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %B
 	%tmp2 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
         %tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 1
@@ -445,7 +445,7 @@ define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [{{r[0-9]+}}:64]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %B
 	%tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 16)
         %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 1
@@ -462,7 +462,7 @@ define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 ;Check the (default) alignment.
 ;CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [{{r[0-9]+}}]
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %B
 	%tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1)
         %tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 1
@@ -478,7 +478,7 @@ define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vld4laneQf:
 ;CHECK: vld4.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %B
 	%tmp2 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
         %tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 1
diff --git a/test/CodeGen/ARM/vldm-liveness.ll b/test/CodeGen/ARM/vldm-liveness.ll
index 751f447077be..e114e6970a32 100644
--- a/test/CodeGen/ARM/vldm-liveness.ll
+++ b/test/CodeGen/ARM/vldm-liveness.ll
@@ -22,14 +22,14 @@ define arm_aapcs_vfpcc <4 x float> @foo(float* %ptr) {
 ; CHECK: vldr s3, [r0, #8]
 ; CHECK: vldmia r0, {s0, s1}
 ; CHECK: vldr s2, [r0, #16]
-   %off0 = getelementptr float* %ptr, i32 0
-   %val0 = load float* %off0
-   %off1 = getelementptr float* %ptr, i32 1
-   %val1 = load float* %off1
-   %off4 = getelementptr float* %ptr, i32 4
-   %val4 = load float* %off4
-   %off2 = getelementptr float* %ptr, i32 2
-   %val2 = load float* %off2
+   %off0 = getelementptr float, float* %ptr, i32 0
+   %val0 = load float, float* %off0
+   %off1 = getelementptr float, float* %ptr, i32 1
+   %val1 = load float, float* %off1
+   %off4 = getelementptr float, float* %ptr, i32 4
+   %val4 = load float, float* %off4
+   %off2 = getelementptr float, float* %ptr, i32 2
+   %val2 = load float, float* %off2
 
    %vec1 = insertelement <4 x float> undef, float %val0, i32 0
    %vec2 = insertelement <4 x float> %vec1, float %val1, i32 1
diff --git a/test/CodeGen/ARM/vldm-sched-a9.ll b/test/CodeGen/ARM/vldm-sched-a9.ll
index e5e7bc08fa4a..0e0cf97d4365 100644
--- a/test/CodeGen/ARM/vldm-sched-a9.ll
+++ b/test/CodeGen/ARM/vldm-sched-a9.ll
@@ -10,12 +10,12 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; CHECK: vldmia
 define void @test(i64* %src) #0 {
 entry:
-  %arrayidx39 = getelementptr inbounds i64* %src, i32 13
+  %arrayidx39 = getelementptr inbounds i64, i64* %src, i32 13
   %vecinit285 = shufflevector <16 x i64> undef, <16 x i64> <i64 15, i64 16, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 16, i32 17>
   store <16 x i64> %vecinit285, <16 x i64>* undef, align 128
-  %0 = load i64* undef, align 8
+  %0 = load i64, i64* undef, align 8
   %vecinit379 = insertelement <16 x i64> undef, i64 %0, i32 9
-  %1 = load i64* undef, align 8
+  %1 = load i64, i64* undef, align 8
   %vecinit419 = insertelement <16 x i64> undef, i64 %1, i32 15
   store <16 x i64> %vecinit419, <16 x i64>* undef, align 128
   %vecinit579 = insertelement <16 x i64> undef, i64 0, i32 4
@@ -23,14 +23,14 @@ entry:
   %vecinit584 = insertelement <16 x i64> %vecinit582, i64 undef, i32 9
   %vecinit586 = insertelement <16 x i64> %vecinit584, i64 0, i32 10
   %vecinit589 = shufflevector <16 x i64> %vecinit586, <16 x i64> <i64 12, i64 13, i64 14, i64 15, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 16, i32 17, i32 18, i32 19, i32 undef>
-  %2 = load i64* undef, align 8
+  %2 = load i64, i64* undef, align 8
   %vecinit591 = insertelement <16 x i64> %vecinit589, i64 %2, i32 15
   store <16 x i64> %vecinit591, <16 x i64>* undef, align 128
   %vecinit694 = shufflevector <16 x i64> undef, <16 x i64> <i64 13, i64 14, i64 15, i64 16, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
   store <16 x i64> %vecinit694, <16 x i64>* undef, align 128
-  %3 = load i64* undef, align 8
+  %3 = load i64, i64* undef, align 8
   %vecinit1331 = insertelement <16 x i64> undef, i64 %3, i32 14
-  %4 = load i64* undef, align 8
+  %4 = load i64, i64* undef, align 8
   %vecinit1468 = insertelement <16 x i64> undef, i64 %4, i32 11
   %vecinit1471 = shufflevector <16 x i64> %vecinit1468, <16 x i64> <i64 13, i64 14, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 undef, i32 undef>
   %vecinit1474 = shufflevector <16 x i64> %vecinit1471, <16 x i64> <i64 15, i64 16, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 16, i32 17>
@@ -45,14 +45,14 @@ entry:
   %vecinit1599 = insertelement <16 x i64> %vecinit1597, i64 undef, i32 8
   %vecinit1601 = insertelement <16 x i64> %vecinit1599, i64 undef, i32 9
   %vecinit1603 = insertelement <16 x i64> %vecinit1601, i64 undef, i32 10
-  %5 = load i64* undef, align 8
+  %5 = load i64, i64* undef, align 8
   %vecinit1605 = insertelement <16 x i64> %vecinit1603, i64 %5, i32 11
   %vecinit1608 = shufflevector <16 x i64> %vecinit1605, <16 x i64> <i64 13, i64 14, i64 15, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 undef>
-  %6 = load i64* undef, align 8
+  %6 = load i64, i64* undef, align 8
   %vecinit1610 = insertelement <16 x i64> %vecinit1608, i64 %6, i32 15
   store <16 x i64> %vecinit1610, <16 x i64>* undef, align 128
   %vecinit2226 = shufflevector <16 x i64> undef, <16 x i64> <i64 6, i64 7, i64 8, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 16, i32 17, i32 18, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
-  %7 = load i64* undef, align 8
+  %7 = load i64, i64* undef, align 8
   %vecinit2228 = insertelement <16 x i64> %vecinit2226, i64 %7, i32 8
   %vecinit2230 = insertelement <16 x i64> %vecinit2228, i64 undef, i32 9
   %vecinit2233 = shufflevector <16 x i64> %vecinit2230, <16 x i64> <i64 11, i64 12, i64 13, i64 14, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 16, i32 17, i32 18, i32 19, i32 undef, i32 undef>
@@ -62,7 +62,7 @@ entry:
   %vecinit2249 = shufflevector <16 x i64> %vecinit2246, <16 x i64> <i64 7, i64 8, i64 9, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 17, i32 18, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %vecinit2252 = shufflevector <16 x i64> %vecinit2249, <16 x i64> <i64 10, i64 11, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 16, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %vecinit2255 = shufflevector <16 x i64> %vecinit2252, <16 x i64> <i64 12, i64 13, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 16, i32 17, i32 undef, i32 undef, i32 undef>
-  %8 = load i64* %arrayidx39, align 8
+  %8 = load i64, i64* %arrayidx39, align 8
   %vecinit2257 = insertelement <16 x i64> %vecinit2255, i64 %8, i32 13
   %vecinit2260 = shufflevector <16 x i64> %vecinit2257, <16 x i64> <i64 15, i64 16, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 16, i32 17>
   store <16 x i64> %vecinit2260, <16 x i64>* null, align 128
diff --git a/test/CodeGen/ARM/vminmax.ll b/test/CodeGen/ARM/vminmax.ll
index 1167ebe06717..011bfd7ff88e 100644
--- a/test/CodeGen/ARM/vminmax.ll
+++ b/test/CodeGen/ARM/vminmax.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vmins8:
 ;CHECK: vmin.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vmins16:
 ;CHECK: vmin.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vmins32:
 ;CHECK: vmin.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vminu8:
 ;CHECK: vmin.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -39,8 +39,8 @@ define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vminu16:
 ;CHECK: vmin.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -48,8 +48,8 @@ define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vminu32:
 ;CHECK: vmin.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -57,8 +57,8 @@ define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vminf32:
 ;CHECK: vmin.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
@@ -66,8 +66,8 @@ define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vminQs8:
 ;CHECK: vmin.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -75,8 +75,8 @@ define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vminQs16:
 ;CHECK: vmin.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -84,8 +84,8 @@ define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vminQs32:
 ;CHECK: vmin.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -93,8 +93,8 @@ define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vminQu8:
 ;CHECK: vmin.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -102,8 +102,8 @@ define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vminQu16:
 ;CHECK: vmin.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -111,8 +111,8 @@ define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vminQu32:
 ;CHECK: vmin.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -120,8 +120,8 @@ define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <4 x float> @vminQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vminQf32:
 ;CHECK: vmin.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x float> %tmp3
 }
@@ -149,8 +149,8 @@ declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwin
 define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vmaxs8:
 ;CHECK: vmax.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -158,8 +158,8 @@ define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vmaxs16:
 ;CHECK: vmax.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -167,8 +167,8 @@ define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vmaxs32:
 ;CHECK: vmax.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -176,8 +176,8 @@ define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vmaxu8:
 ;CHECK: vmax.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -185,8 +185,8 @@ define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vmaxu16:
 ;CHECK: vmax.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -194,8 +194,8 @@ define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vmaxu32:
 ;CHECK: vmax.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -203,8 +203,8 @@ define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vmaxf32:
 ;CHECK: vmax.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
@@ -212,8 +212,8 @@ define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vmaxQs8:
 ;CHECK: vmax.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -221,8 +221,8 @@ define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vmaxQs16:
 ;CHECK: vmax.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -230,8 +230,8 @@ define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vmaxQs32:
 ;CHECK: vmax.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -239,8 +239,8 @@ define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vmaxQu8:
 ;CHECK: vmax.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -248,8 +248,8 @@ define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vmaxQu16:
 ;CHECK: vmax.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -257,8 +257,8 @@ define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vmaxQu32:
 ;CHECK: vmax.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -266,8 +266,8 @@ define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <4 x float> @vmaxQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vmaxQf32:
 ;CHECK: vmax.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x float> %tmp3
 }
diff --git a/test/CodeGen/ARM/vminmaxnm.ll b/test/CodeGen/ARM/vminmaxnm.ll
index 39289a0bafb3..3632ffd00213 100644
--- a/test/CodeGen/ARM/vminmaxnm.ll
+++ b/test/CodeGen/ARM/vminmaxnm.ll
@@ -1,11 +1,14 @@
-; RUN: llc < %s -mtriple armv8 -mattr=+neon | FileCheck %s
-; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-FAST
+; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 | FileCheck %s
+; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 \
+; RUN:          -enable-no-nans-fp-math -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-FAST
+
+; vectors
 
 define <4 x float> @vmaxnmq(<4 x float>* %A, <4 x float>* %B) nounwind {
 ; CHECK-LABEL: vmaxnmq:
 ; CHECK: vmaxnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
-  %tmp1 = load <4 x float>* %A
-  %tmp2 = load <4 x float>* %B
+  %tmp1 = load <4 x float>, <4 x float>* %A
+  %tmp2 = load <4 x float>, <4 x float>* %B
   %tmp3 = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
   ret <4 x float> %tmp3
 }
@@ -13,8 +16,8 @@ define <4 x float> @vmaxnmq(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x float> @vmaxnmd(<2 x float>* %A, <2 x float>* %B) nounwind {
 ; CHECK-LABEL: vmaxnmd:
 ; CHECK: vmaxnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
-  %tmp1 = load <2 x float>* %A
-  %tmp2 = load <2 x float>* %B
+  %tmp1 = load <2 x float>, <2 x float>* %A
+  %tmp2 = load <2 x float>, <2 x float>* %B
   %tmp3 = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
   ret <2 x float> %tmp3
 }
@@ -22,8 +25,8 @@ define <2 x float> @vmaxnmd(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x float> @vminnmq(<4 x float>* %A, <4 x float>* %B) nounwind {
 ; CHECK-LABEL: vminnmq:
 ; CHECK: vminnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
-  %tmp1 = load <4 x float>* %A
-  %tmp2 = load <4 x float>* %B
+  %tmp1 = load <4 x float>, <4 x float>* %A
+  %tmp2 = load <4 x float>, <4 x float>* %B
   %tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
   ret <4 x float> %tmp3
 }
@@ -31,12 +34,14 @@ define <4 x float> @vminnmq(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <2 x float> @vminnmd(<2 x float>* %A, <2 x float>* %B) nounwind {
 ; CHECK-LABEL: vminnmd:
 ; CHECK: vminnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
-  %tmp1 = load <2 x float>* %A
-  %tmp2 = load <2 x float>* %B
+  %tmp1 = load <2 x float>, <2 x float>* %A
+  %tmp2 = load <2 x float>, <2 x float>* %B
   %tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
   ret <2 x float> %tmp3
 }
 
+; scalars
+
 define float @fp-armv8_vminnm_o(float %a, float %b) {
 ; CHECK-FAST-LABEL: "fp-armv8_vminnm_o":
 ; CHECK-FAST-NOT: vcmp
@@ -48,6 +53,17 @@ define float @fp-armv8_vminnm_o(float %a, float %b) {
   ret float %cond
 }
 
+define double @fp-armv8_vminnm_ole(double %a, double %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vminnm_ole":
+; CHECK-FAST-NOT: vcmp
+; CHECK-FAST: vminnm.f64
+; CHECK-LABEL: "fp-armv8_vminnm_ole":
+; CHECK-NOT: vminnm.f64
+  %cmp = fcmp ole double %a, %b
+  %cond = select i1 %cmp, double %a, double %b
+  ret double %cond
+}
+
 define float @fp-armv8_vminnm_o_rev(float %a, float %b) {
 ; CHECK-FAST-LABEL: "fp-armv8_vminnm_o_rev":
 ; CHECK-FAST-NOT: vcmp
@@ -59,6 +75,17 @@ define float @fp-armv8_vminnm_o_rev(float %a, float %b) {
   ret float %cond
 }
 
+define double @fp-armv8_vminnm_oge_rev(double %a, double %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vminnm_oge_rev":
+; CHECK-FAST-NOT: vcmp
+; CHECK-FAST: vminnm.f64
+; CHECK-LABEL: "fp-armv8_vminnm_oge_rev":
+; CHECK-NOT: vminnm.f64
+  %cmp = fcmp oge double %a, %b
+  %cond = select i1 %cmp, double %b, double %a
+  ret double %cond
+}
+
 define float @fp-armv8_vminnm_u(float %a, float %b) {
 ; CHECK-FAST-LABEL: "fp-armv8_vminnm_u":
 ; CHECK-FAST-NOT: vcmp
@@ -70,6 +97,17 @@ define float @fp-armv8_vminnm_u(float %a, float %b) {
   ret float %cond
 }
 
+define float @fp-armv8_vminnm_ule(float %a, float %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vminnm_ule":
+; CHECK-FAST-NOT: vcmp
+; CHECK-FAST: vminnm.f32
+; CHECK-LABEL: "fp-armv8_vminnm_ule":
+; CHECK-NOT: vminnm.f32
+  %cmp = fcmp ule float %a, %b
+  %cond = select i1 %cmp, float %a, float %b
+  ret float %cond
+}
+
 define float @fp-armv8_vminnm_u_rev(float %a, float %b) {
 ; CHECK-FAST-LABEL: "fp-armv8_vminnm_u_rev":
 ; CHECK-FAST-NOT: vcmp
@@ -81,6 +119,17 @@ define float @fp-armv8_vminnm_u_rev(float %a, float %b) {
   ret float %cond
 }
 
+define double @fp-armv8_vminnm_uge_rev(double %a, double %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vminnm_uge_rev":
+; CHECK-FAST-NOT: vcmp
+; CHECK-FAST: vminnm.f64
+; CHECK-LABEL: "fp-armv8_vminnm_uge_rev":
+; CHECK-NOT: vminnm.f64
+  %cmp = fcmp uge double %a, %b
+  %cond = select i1 %cmp, double %b, double %a
+  ret double %cond
+}
+
 define float @fp-armv8_vmaxnm_o(float %a, float %b) {
 ; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_o":
 ; CHECK-FAST-NOT: vcmp
@@ -92,6 +141,17 @@ define float @fp-armv8_vmaxnm_o(float %a, float %b) {
   ret float %cond
 }
 
+define float @fp-armv8_vmaxnm_oge(float %a, float %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_oge":
+; CHECK-FAST-NOT: vcmp
+; CHECK-FAST: vmaxnm.f32
+; CHECK-LABEL: "fp-armv8_vmaxnm_oge":
+; CHECK-NOT: vmaxnm.f32
+  %cmp = fcmp oge float %a, %b
+  %cond = select i1 %cmp, float %a, float %b
+  ret float %cond
+}
+
 define float @fp-armv8_vmaxnm_o_rev(float %a, float %b) {
 ; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_o_rev":
 ; CHECK-FAST-NOT: vcmp
@@ -103,6 +163,17 @@ define float @fp-armv8_vmaxnm_o_rev(float %a, float %b) {
   ret float %cond
 }
 
+define float @fp-armv8_vmaxnm_ole_rev(float %a, float %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_ole_rev":
+; CHECK-FAST-NOT: vcmp
+; CHECK-FAST: vmaxnm.f32
+; CHECK-LABEL: "fp-armv8_vmaxnm_ole_rev":
+; CHECK-NOT: vmaxnm.f32
+  %cmp = fcmp ole float %a, %b
+  %cond = select i1 %cmp, float %b, float %a
+  ret float %cond
+}
+
 define float @fp-armv8_vmaxnm_u(float %a, float %b) {
 ; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_u":
 ; CHECK-FAST-NOT: vcmp
@@ -114,6 +185,17 @@ define float @fp-armv8_vmaxnm_u(float %a, float %b) {
   ret float %cond
 }
 
+define float @fp-armv8_vmaxnm_uge(float %a, float %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_uge":
+; CHECK-FAST-NOT: vcmp
+; CHECK-FAST: vmaxnm.f32
+; CHECK-LABEL: "fp-armv8_vmaxnm_uge":
+; CHECK-NOT: vmaxnm.f32
+  %cmp = fcmp uge float %a, %b
+  %cond = select i1 %cmp, float %a, float %b
+  ret float %cond
+}
+
 define float @fp-armv8_vmaxnm_u_rev(float %a, float %b) {
 ; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_u_rev":
 ; CHECK-FAST-NOT: vcmp
@@ -125,6 +207,302 @@ define float @fp-armv8_vmaxnm_u_rev(float %a, float %b) {
   ret float %cond
 }
 
+define double @fp-armv8_vmaxnm_ule_rev(double %a, double %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_ule_rev":
+; CHECK-FAST-NOT: vcmp
+; CHECK-FAST: vmaxnm.f64
+; CHECK-LABEL: "fp-armv8_vmaxnm_ule_rev":
+; CHECK-NOT: vmaxnm.f64
+  %cmp = fcmp ule double %a, %b
+  %cond = select i1 %cmp, double %b, double %a
+  ret double %cond
+}
+
+; known non-NaNs
+
+define float @fp-armv8_vminnm_NNNo(float %a) {
+; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNo":
+; CHECK-FAST: vminnm.f32
+; CHECK-FAST: vminnm.f32
+; CHECK-LABEL: "fp-armv8_vminnm_NNNo":
+; CHECK: vminnm.f32
+; CHECK-NOT: vminnm.f32
+  %cmp1 = fcmp olt float %a, 12.
+  %cond1 = select i1 %cmp1, float %a, float 12.
+  %cmp2 = fcmp olt float 34., %cond1
+  %cond2 = select i1 %cmp2, float 34., float %cond1
+  ret float %cond2
+}
+
+define double @fp-armv8_vminnm_NNNole(double %a) {
+; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNole":
+; CHECK-FAST: vminnm.f64
+; CHECK-FAST: vminnm.f64
+; CHECK-LABEL: "fp-armv8_vminnm_NNNole":
+; CHECK: vminnm.f64
+; CHECK-NOT: vminnm.f64
+  %cmp1 = fcmp ole double %a, 34.
+  %cond1 = select i1 %cmp1, double %a, double 34.
+  %cmp2 = fcmp ole double 56., %cond1
+  %cond2 = select i1 %cmp2, double 56., double %cond1
+  ret double %cond2
+}
+
+define float @fp-armv8_vminnm_NNNo_rev(float %a) {
+; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNo_rev":
+; CHECK-FAST: vminnm.f32
+; CHECK-FAST: vminnm.f32
+; CHECK-LABEL: "fp-armv8_vminnm_NNNo_rev":
+; CHECK: vminnm.f32
+; CHECK-NOT: vminnm.f32
+  %cmp1 = fcmp ogt float %a, 56.
+  %cond1 = select i1 %cmp1, float 56., float %a
+  %cmp2 = fcmp ogt float 78., %cond1
+  %cond2 = select i1 %cmp2, float %cond1, float 78.
+  ret float %cond2
+}
+
+define double @fp-armv8_vminnm_NNNoge_rev(double %a) {
+; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNoge_rev":
+; CHECK-FAST: vminnm.f64
+; CHECK-FAST: vminnm.f64
+; CHECK-LABEL: "fp-armv8_vminnm_NNNoge_rev":
+; CHECK: vminnm.f64
+; CHECK-NOT: vminnm.f64
+  %cmp1 = fcmp oge double %a, 78.
+  %cond1 = select i1 %cmp1, double 78., double %a
+  %cmp2 = fcmp oge double 90., %cond1
+  %cond2 = select i1 %cmp2, double %cond1, double 90.
+  ret double %cond2
+}
+
+define float @fp-armv8_vminnm_NNNu(float %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNu":
+; CHECK-FAST: vminnm.f32
+; CHECK-FAST: vminnm.f32
+; CHECK-LABEL: "fp-armv8_vminnm_NNNu":
+; CHECK: vminnm.f32
+; CHECK-NOT: vminnm.f32
+  %cmp1 = fcmp ult float 12., %b
+  %cond1 = select i1 %cmp1, float 12., float %b
+  %cmp2 = fcmp ult float %cond1, 34.
+  %cond2 = select i1 %cmp2, float %cond1, float 34.
+  ret float %cond2
+}
+
+define float @fp-armv8_vminnm_NNNule(float %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNule":
+; CHECK-FAST: vminnm.f32
+; CHECK-FAST: vminnm.f32
+; CHECK-LABEL: "fp-armv8_vminnm_NNNule":
+; CHECK: vminnm.f32
+; CHECK-NOT: vminnm.f32
+  %cmp1 = fcmp ule float 34., %b
+  %cond1 = select i1 %cmp1, float 34., float %b
+  %cmp2 = fcmp ule float %cond1, 56.
+  %cond2 = select i1 %cmp2, float %cond1, float 56.
+  ret float %cond2
+}
+
+define float @fp-armv8_vminnm_NNNu_rev(float %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNu_rev":
+; CHECK-FAST: vminnm.f32
+; CHECK-FAST: vminnm.f32
+; CHECK-LABEL: "fp-armv8_vminnm_NNNu_rev":
+; CHECK: vminnm.f32
+; CHECK-NOT: vminnm.f32
+  %cmp1 = fcmp ugt float 56., %b
+  %cond1 = select i1 %cmp1, float %b, float 56.
+  %cmp2 = fcmp ugt float %cond1, 78.
+  %cond2 = select i1 %cmp2, float 78., float %cond1
+  ret float %cond2
+}
+
+define double @fp-armv8_vminnm_NNNuge_rev(double %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNuge_rev":
+; CHECK-FAST: vminnm.f64
+; CHECK-FAST: vminnm.f64
+; CHECK-LABEL: "fp-armv8_vminnm_NNNuge_rev":
+; CHECK: vminnm.f64
+; CHECK-NOT: vminnm.f64
+  %cmp1 = fcmp uge double 78., %b
+  %cond1 = select i1 %cmp1, double %b, double 78.
+  %cmp2 = fcmp uge double %cond1, 90.
+  %cond2 = select i1 %cmp2, double 90., double %cond1
+  ret double %cond2
+}
+
+define float @fp-armv8_vmaxnm_NNNo(float %a) {
+; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNo":
+; CHECK-FAST: vmaxnm.f32
+; CHECK-FAST: vmaxnm.f32
+; CHECK-LABEL: "fp-armv8_vmaxnm_NNNo":
+; CHECK: vmaxnm.f32
+; CHECK-NOT: vmaxnm.f32
+  %cmp1 = fcmp ogt float %a, 12.
+  %cond1 = select i1 %cmp1, float %a, float 12.
+  %cmp2 = fcmp ogt float 34., %cond1
+  %cond2 = select i1 %cmp2, float 34., float %cond1
+  ret float %cond2
+}
+
+define float @fp-armv8_vmaxnm_NNNoge(float %a) {
+; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNoge":
+; CHECK-FAST: vmaxnm.f32
+; CHECK-FAST: vmaxnm.f32
+; CHECK-LABEL: "fp-armv8_vmaxnm_NNNoge":
+; CHECK: vmaxnm.f32
+; CHECK-NOT: vmaxnm.f32
+  %cmp1 = fcmp oge float %a, 34.
+  %cond1 = select i1 %cmp1, float %a, float 34.
+  %cmp2 = fcmp oge float 56., %cond1
+  %cond2 = select i1 %cmp2, float 56., float %cond1
+  ret float %cond2
+}
+
+define float @fp-armv8_vmaxnm_NNNo_rev(float %a) {
+; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNo_rev":
+; CHECK-FAST: vmaxnm.f32
+; CHECK-FAST: vmaxnm.f32
+; CHECK-LABEL: "fp-armv8_vmaxnm_NNNo_rev":
+; CHECK: vmaxnm.f32
+; CHECK-NOT: vmaxnm.f32
+  %cmp1 = fcmp olt float %a, 56.
+  %cond1 = select i1 %cmp1, float 56., float %a
+  %cmp2 = fcmp olt float 78., %cond1
+  %cond2 = select i1 %cmp2, float %cond1, float 78.
+  ret float %cond2
+}
+
+define float @fp-armv8_vmaxnm_NNNole_rev(float %a) {
+; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNole_rev":
+; CHECK-FAST: vmaxnm.f32
+; CHECK-FAST: vmaxnm.f32
+; CHECK-LABEL: "fp-armv8_vmaxnm_NNNole_rev":
+; CHECK: vmaxnm.f32
+; CHECK-NOT: vmaxnm.f32
+  %cmp1 = fcmp ole float %a, 78.
+  %cond1 = select i1 %cmp1, float 78., float %a
+  %cmp2 = fcmp ole float 90., %cond1
+  %cond2 = select i1 %cmp2, float %cond1, float 90.
+  ret float %cond2
+}
+
+define float @fp-armv8_vmaxnm_NNNu(float %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNu":
+; CHECK-FAST: vmaxnm.f32
+; CHECK-FAST: vmaxnm.f32
+; CHECK-LABEL: "fp-armv8_vmaxnm_NNNu":
+; CHECK: vmaxnm.f32
+; CHEC-NOT: vmaxnm.f32
+  %cmp1 = fcmp ugt float 12., %b
+  %cond1 = select i1 %cmp1, float 12., float %b
+  %cmp2 = fcmp ugt float %cond1, 34.
+  %cond2 = select i1 %cmp2, float %cond1, float 34.
+  ret float %cond2
+}
+
+define float @fp-armv8_vmaxnm_NNNuge(float %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNuge":
+; CHECK-FAST: vmaxnm.f32
+; CHECK-FAST: vmaxnm.f32
+; CHECK-LABEL: "fp-armv8_vmaxnm_NNNuge":
+; CHECK: vmaxnm.f32
+; CHECK-NOT: vmaxnm.f32
+  %cmp1 = fcmp uge float 34., %b
+  %cond1 = select i1 %cmp1, float 34., float %b
+  %cmp2 = fcmp uge float %cond1, 56.
+  %cond2 = select i1 %cmp2, float %cond1, float 56.
+  ret float %cond2
+}
+
+define float @fp-armv8_vmaxnm_NNNu_rev(float %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNu_rev":
+; CHECK-FAST: vmaxnm.f32
+; CHECK-FAST: vmaxnm.f32
+; CHECK-LABEL: "fp-armv8_vmaxnm_NNNu_rev":
+; CHECK: vmaxnm.f32
+; CHECK-NOT: vmaxnm.f32
+  %cmp1 = fcmp ult float 56., %b
+  %cond1 = select i1 %cmp1, float %b, float 56.
+  %cmp2 = fcmp ult float %cond1, 78.
+  %cond2 = select i1 %cmp2, float 78., float %cond1
+  ret float %cond2
+}
+
+define double @fp-armv8_vmaxnm_NNNule_rev( double %b) {
+; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNule_rev":
+; CHECK-FAST: vmaxnm.f64
+; CHECK-FAST: vmaxnm.f64
+; CHECK-LABEL: "fp-armv8_vmaxnm_NNNule_rev":
+; CHECK: vmaxnm.f64
+; CHECK-NOT: vmaxnm.f64
+  %cmp1 = fcmp ule double 78., %b
+  %cond1 = select i1 %cmp1, double %b, double 78.
+  %cmp2 = fcmp ule double %cond1, 90.
+  %cond2 = select i1 %cmp2, double 90., double %cond1
+  ret double %cond2
+}
+
+define float @fp-armv8_vminmaxnm_0(float %a) {
+; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_0":
+; CHECK-FAST-NOT: vcmp
+; CHECK-FAST: vminnm.f32
+; CHECK-FAST: vmaxnm.f32
+; CHECK-LABEL: "fp-armv8_vminmaxnm_0":
+; CHECK-NOT: vminnm.f32
+; CHECK: vmaxnm.f32
+  %cmp1 = fcmp olt float %a, 0.
+  %cond1 = select i1 %cmp1, float %a, float 0.
+  %cmp2 = fcmp ogt float %cond1, 0.
+  %cond2 = select i1 %cmp2, float %cond1, float 0.
+  ret float %cond2
+}
+
+define float @fp-armv8_vminmaxnm_neg0(float %a) {
+; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_neg0":
+; CHECK-FAST-NOT: vcmp
+; CHECK-FAST: vminnm.f32
+; CHECK-FAST: vmaxnm.f32
+; CHECK-LABEL: "fp-armv8_vminmaxnm_neg0":
+; CHECK: vminnm.f32
+; CHECK-NOT: vmaxnm.f32
+  %cmp1 = fcmp olt float %a, -0.
+  %cond1 = select i1 %cmp1, float %a, float -0.
+  %cmp2 = fcmp ogt float %cond1, -0.
+  %cond2 = select i1 %cmp2, float %cond1, float -0.
+  ret float %cond2
+}
+
+define float @fp-armv8_vminmaxnm_e_0(float %a) {
+; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_e_0":
+; CHECK-FAST-NOT: vcmp
+; CHECK-FAST: vminnm.f32
+; CHECK-FAST: vmaxnm.f32
+; CHECK-LABEL: "fp-armv8_vminmaxnm_e_0":
+; CHECK-NOT: vminnm.f32
+; CHECK: vmaxnm.f32
+  %cmp1 = fcmp ule float 0., %a
+  %cond1 = select i1 %cmp1, float 0., float %a
+  %cmp2 = fcmp uge float 0., %cond1
+  %cond2 = select i1 %cmp2, float 0., float %cond1
+  ret float %cond2
+}
+
+define float @fp-armv8_vminmaxnm_e_neg0(float %a) {
+; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_e_neg0":
+; CHECK-FAST-NOT: vcmp
+; CHECK-FAST: vminnm.f32
+; CHECK-FAST: vmaxnm.f32
+; CHECK-LABEL: "fp-armv8_vminmaxnm_e_neg0":
+; CHECK: vminnm.f32
+; CHECK-NOT: vmaxnm.f32
+  %cmp1 = fcmp ule float -0., %a
+  %cond1 = select i1 %cmp1, float -0., float %a
+  %cmp2 = fcmp uge float -0., %cond1
+  %cond2 = select i1 %cmp2, float -0., float %cond1
+  ret float %cond2
+}
 
 declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
 declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
diff --git a/test/CodeGen/ARM/vmla.ll b/test/CodeGen/ARM/vmla.ll
index 6073fc5566fd..8ca33a9eecac 100644
--- a/test/CodeGen/ARM/vmla.ll
+++ b/test/CodeGen/ARM/vmla.ll
@@ -3,9 +3,9 @@
 define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
 ;CHECK-LABEL: vmlai8:
 ;CHECK: vmla.i8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
-	%tmp3 = load <8 x i8>* %C
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
+	%tmp3 = load <8 x i8>, <8 x i8>* %C
 	%tmp4 = mul <8 x i8> %tmp2, %tmp3
 	%tmp5 = add <8 x i8> %tmp1, %tmp4
 	ret <8 x i8> %tmp5
@@ -14,9 +14,9 @@ define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
 define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK-LABEL: vmlai16:
 ;CHECK: vmla.i16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
-	%tmp3 = load <4 x i16>* %C
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
+	%tmp3 = load <4 x i16>, <4 x i16>* %C
 	%tmp4 = mul <4 x i16> %tmp2, %tmp3
 	%tmp5 = add <4 x i16> %tmp1, %tmp4
 	ret <4 x i16> %tmp5
@@ -25,9 +25,9 @@ define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK-LABEL: vmlai32:
 ;CHECK: vmla.i32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
-	%tmp3 = load <2 x i32>* %C
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
+	%tmp3 = load <2 x i32>, <2 x i32>* %C
 	%tmp4 = mul <2 x i32> %tmp2, %tmp3
 	%tmp5 = add <2 x i32> %tmp1, %tmp4
 	ret <2 x i32> %tmp5
@@ -36,9 +36,9 @@ define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
 ;CHECK-LABEL: vmlaf32:
 ;CHECK: vmla.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
-	%tmp3 = load <2 x float>* %C
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
+	%tmp3 = load <2 x float>, <2 x float>* %C
 	%tmp4 = fmul <2 x float> %tmp2, %tmp3
 	%tmp5 = fadd <2 x float> %tmp1, %tmp4
 	ret <2 x float> %tmp5
@@ -47,9 +47,9 @@ define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n
 define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
 ;CHECK-LABEL: vmlaQi8:
 ;CHECK: vmla.i8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
-	%tmp3 = load <16 x i8>* %C
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
+	%tmp3 = load <16 x i8>, <16 x i8>* %C
 	%tmp4 = mul <16 x i8> %tmp2, %tmp3
 	%tmp5 = add <16 x i8> %tmp1, %tmp4
 	ret <16 x i8> %tmp5
@@ -58,9 +58,9 @@ define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind
 define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
 ;CHECK-LABEL: vmlaQi16:
 ;CHECK: vmla.i16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
-	%tmp3 = load <8 x i16>* %C
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
+	%tmp3 = load <8 x i16>, <8 x i16>* %C
 	%tmp4 = mul <8 x i16> %tmp2, %tmp3
 	%tmp5 = add <8 x i16> %tmp1, %tmp4
 	ret <8 x i16> %tmp5
@@ -69,9 +69,9 @@ define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
 define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: vmlaQi32:
 ;CHECK: vmla.i32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
-	%tmp3 = load <4 x i32>* %C
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
+	%tmp3 = load <4 x i32>, <4 x i32>* %C
 	%tmp4 = mul <4 x i32> %tmp2, %tmp3
 	%tmp5 = add <4 x i32> %tmp1, %tmp4
 	ret <4 x i32> %tmp5
@@ -80,9 +80,9 @@ define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind
 define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
 ;CHECK-LABEL: vmlaQf32:
 ;CHECK: vmla.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
-	%tmp3 = load <4 x float>* %C
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
+	%tmp3 = load <4 x float>, <4 x float>* %C
 	%tmp4 = fmul <4 x float> %tmp2, %tmp3
 	%tmp5 = fadd <4 x float> %tmp1, %tmp4
 	ret <4 x float> %tmp5
@@ -91,9 +91,9 @@ define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C)
 define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ;CHECK-LABEL: vmlals8:
 ;CHECK: vmlal.s8
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i8>* %B
-	%tmp3 = load <8 x i8>* %C
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
+	%tmp3 = load <8 x i8>, <8 x i8>* %C
 	%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
 	%tmp5 = sext <8 x i8> %tmp3 to <8 x i16>
 	%tmp6 = mul <8 x i16> %tmp4, %tmp5
@@ -104,9 +104,9 @@ define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK-LABEL: vmlals16:
 ;CHECK: vmlal.s16
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i16>* %B
-	%tmp3 = load <4 x i16>* %C
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
+	%tmp3 = load <4 x i16>, <4 x i16>* %C
 	%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
 	%tmp5 = sext <4 x i16> %tmp3 to <4 x i32>
 	%tmp6 = mul <4 x i32> %tmp4, %tmp5
@@ -117,9 +117,9 @@ define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK-LABEL: vmlals32:
 ;CHECK: vmlal.s32
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i32>* %B
-	%tmp3 = load <2 x i32>* %C
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
+	%tmp3 = load <2 x i32>, <2 x i32>* %C
 	%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
 	%tmp5 = sext <2 x i32> %tmp3 to <2 x i64>
 	%tmp6 = mul <2 x i64> %tmp4, %tmp5
@@ -130,9 +130,9 @@ define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ;CHECK-LABEL: vmlalu8:
 ;CHECK: vmlal.u8
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i8>* %B
-	%tmp3 = load <8 x i8>* %C
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
+	%tmp3 = load <8 x i8>, <8 x i8>* %C
 	%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
 	%tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
 	%tmp6 = mul <8 x i16> %tmp4, %tmp5
@@ -143,9 +143,9 @@ define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK-LABEL: vmlalu16:
 ;CHECK: vmlal.u16
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i16>* %B
-	%tmp3 = load <4 x i16>* %C
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
+	%tmp3 = load <4 x i16>, <4 x i16>* %C
 	%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
 	%tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
 	%tmp6 = mul <4 x i32> %tmp4, %tmp5
@@ -156,9 +156,9 @@ define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 define <2 x i64> @vmlalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK-LABEL: vmlalu32:
 ;CHECK: vmlal.u32
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i32>* %B
-	%tmp3 = load <2 x i32>* %C
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
+	%tmp3 = load <2 x i32>, <2 x i32>* %C
 	%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
 	%tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
 	%tmp6 = mul <2 x i64> %tmp4, %tmp5
diff --git a/test/CodeGen/ARM/vmls.ll b/test/CodeGen/ARM/vmls.ll
index f86739cea3f1..d14928147a36 100644
--- a/test/CodeGen/ARM/vmls.ll
+++ b/test/CodeGen/ARM/vmls.ll
@@ -3,9 +3,9 @@
 define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
 ;CHECK-LABEL: vmlsi8:
 ;CHECK: vmls.i8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
-	%tmp3 = load <8 x i8>* %C
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
+	%tmp3 = load <8 x i8>, <8 x i8>* %C
 	%tmp4 = mul <8 x i8> %tmp2, %tmp3
 	%tmp5 = sub <8 x i8> %tmp1, %tmp4
 	ret <8 x i8> %tmp5
@@ -14,9 +14,9 @@ define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
 define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK-LABEL: vmlsi16:
 ;CHECK: vmls.i16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
-	%tmp3 = load <4 x i16>* %C
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
+	%tmp3 = load <4 x i16>, <4 x i16>* %C
 	%tmp4 = mul <4 x i16> %tmp2, %tmp3
 	%tmp5 = sub <4 x i16> %tmp1, %tmp4
 	ret <4 x i16> %tmp5
@@ -25,9 +25,9 @@ define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK-LABEL: vmlsi32:
 ;CHECK: vmls.i32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
-	%tmp3 = load <2 x i32>* %C
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
+	%tmp3 = load <2 x i32>, <2 x i32>* %C
 	%tmp4 = mul <2 x i32> %tmp2, %tmp3
 	%tmp5 = sub <2 x i32> %tmp1, %tmp4
 	ret <2 x i32> %tmp5
@@ -36,9 +36,9 @@ define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
 ;CHECK-LABEL: vmlsf32:
 ;CHECK: vmls.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
-	%tmp3 = load <2 x float>* %C
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
+	%tmp3 = load <2 x float>, <2 x float>* %C
 	%tmp4 = fmul <2 x float> %tmp2, %tmp3
 	%tmp5 = fsub <2 x float> %tmp1, %tmp4
 	ret <2 x float> %tmp5
@@ -47,9 +47,9 @@ define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n
 define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
 ;CHECK-LABEL: vmlsQi8:
 ;CHECK: vmls.i8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
-	%tmp3 = load <16 x i8>* %C
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
+	%tmp3 = load <16 x i8>, <16 x i8>* %C
 	%tmp4 = mul <16 x i8> %tmp2, %tmp3
 	%tmp5 = sub <16 x i8> %tmp1, %tmp4
 	ret <16 x i8> %tmp5
@@ -58,9 +58,9 @@ define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind
 define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
 ;CHECK-LABEL: vmlsQi16:
 ;CHECK: vmls.i16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
-	%tmp3 = load <8 x i16>* %C
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
+	%tmp3 = load <8 x i16>, <8 x i16>* %C
 	%tmp4 = mul <8 x i16> %tmp2, %tmp3
 	%tmp5 = sub <8 x i16> %tmp1, %tmp4
 	ret <8 x i16> %tmp5
@@ -69,9 +69,9 @@ define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
 define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
 ;CHECK-LABEL: vmlsQi32:
 ;CHECK: vmls.i32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
-	%tmp3 = load <4 x i32>* %C
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
+	%tmp3 = load <4 x i32>, <4 x i32>* %C
 	%tmp4 = mul <4 x i32> %tmp2, %tmp3
 	%tmp5 = sub <4 x i32> %tmp1, %tmp4
 	ret <4 x i32> %tmp5
@@ -80,9 +80,9 @@ define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind
 define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
 ;CHECK-LABEL: vmlsQf32:
 ;CHECK: vmls.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
-	%tmp3 = load <4 x float>* %C
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
+	%tmp3 = load <4 x float>, <4 x float>* %C
 	%tmp4 = fmul <4 x float> %tmp2, %tmp3
 	%tmp5 = fsub <4 x float> %tmp1, %tmp4
 	ret <4 x float> %tmp5
@@ -91,9 +91,9 @@ define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C)
 define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ;CHECK-LABEL: vmlsls8:
 ;CHECK: vmlsl.s8
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i8>* %B
-	%tmp3 = load <8 x i8>* %C
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
+	%tmp3 = load <8 x i8>, <8 x i8>* %C
 	%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
 	%tmp5 = sext <8 x i8> %tmp3 to <8 x i16>
 	%tmp6 = mul <8 x i16> %tmp4, %tmp5
@@ -104,9 +104,9 @@ define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK-LABEL: vmlsls16:
 ;CHECK: vmlsl.s16
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i16>* %B
-	%tmp3 = load <4 x i16>* %C
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
+	%tmp3 = load <4 x i16>, <4 x i16>* %C
 	%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
 	%tmp5 = sext <4 x i16> %tmp3 to <4 x i32>
 	%tmp6 = mul <4 x i32> %tmp4, %tmp5
@@ -117,9 +117,9 @@ define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK-LABEL: vmlsls32:
 ;CHECK: vmlsl.s32
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i32>* %B
-	%tmp3 = load <2 x i32>* %C
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
+	%tmp3 = load <2 x i32>, <2 x i32>* %C
 	%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
 	%tmp5 = sext <2 x i32> %tmp3 to <2 x i64>
 	%tmp6 = mul <2 x i64> %tmp4, %tmp5
@@ -130,9 +130,9 @@ define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ;CHECK-LABEL: vmlslu8:
 ;CHECK: vmlsl.u8
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i8>* %B
-	%tmp3 = load <8 x i8>* %C
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
+	%tmp3 = load <8 x i8>, <8 x i8>* %C
 	%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
 	%tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
 	%tmp6 = mul <8 x i16> %tmp4, %tmp5
@@ -143,9 +143,9 @@ define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK-LABEL: vmlslu16:
 ;CHECK: vmlsl.u16
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i16>* %B
-	%tmp3 = load <4 x i16>* %C
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
+	%tmp3 = load <4 x i16>, <4 x i16>* %C
 	%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
 	%tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
 	%tmp6 = mul <4 x i32> %tmp4, %tmp5
@@ -156,9 +156,9 @@ define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 define <2 x i64> @vmlslu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK-LABEL: vmlslu32:
 ;CHECK: vmlsl.u32
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i32>* %B
-	%tmp3 = load <2 x i32>* %C
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
+	%tmp3 = load <2 x i32>, <2 x i32>* %C
 	%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
 	%tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
 	%tmp6 = mul <2 x i64> %tmp4, %tmp5
diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll
index 7900af44ef08..b7a23b7bb59c 100644
--- a/test/CodeGen/ARM/vmov.ll
+++ b/test/CodeGen/ARM/vmov.ll
@@ -174,7 +174,7 @@ define void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) noun
 entry:
 ;CHECK-LABEL: vdupn128:
 ;CHECK: vmov.i8 d{{.*}}, #0x80
-  %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
+  %0 = getelementptr inbounds %struct.int8x8_t, %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
   store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, <8 x i8>* %0, align 8
   ret void
 }
@@ -183,7 +183,7 @@ define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) no
 entry:
 ;CHECK-LABEL: vdupnneg75:
 ;CHECK: vmov.i8 d{{.*}}, #0xb5
-  %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
+  %0 = getelementptr inbounds %struct.int8x8_t, %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
   store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, <8 x i8>* %0, align 8
   ret void
 }
@@ -191,7 +191,7 @@ entry:
 define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vmovls8:
 ;CHECK: vmovl.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
 	ret <8 x i16> %tmp2
 }
@@ -199,7 +199,7 @@ define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
 define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vmovls16:
 ;CHECK: vmovl.s16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
 	ret <4 x i32> %tmp2
 }
@@ -207,7 +207,7 @@ define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
 define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vmovls32:
 ;CHECK: vmovl.s32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
 	ret <2 x i64> %tmp2
 }
@@ -215,7 +215,7 @@ define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
 define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vmovlu8:
 ;CHECK: vmovl.u8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
 	ret <8 x i16> %tmp2
 }
@@ -223,7 +223,7 @@ define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
 define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vmovlu16:
 ;CHECK: vmovl.u16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
 	ret <4 x i32> %tmp2
 }
@@ -231,7 +231,7 @@ define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
 define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vmovlu32:
 ;CHECK: vmovl.u32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
 	ret <2 x i64> %tmp2
 }
@@ -239,7 +239,7 @@ define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
 define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vmovni16:
 ;CHECK: vmovn.i16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = trunc <8 x i16> %tmp1 to <8 x i8>
 	ret <8 x i8> %tmp2
 }
@@ -247,7 +247,7 @@ define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
 define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vmovni32:
 ;CHECK: vmovn.i32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
 	ret <4 x i16> %tmp2
 }
@@ -255,7 +255,7 @@ define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
 define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vmovni64:
 ;CHECK: vmovn.i64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>
 	ret <2 x i32> %tmp2
 }
@@ -263,7 +263,7 @@ define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
 define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqmovns16:
 ;CHECK: vqmovn.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
 	ret <8 x i8> %tmp2
 }
@@ -271,7 +271,7 @@ define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
 define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqmovns32:
 ;CHECK: vqmovn.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
 	ret <4 x i16> %tmp2
 }
@@ -279,7 +279,7 @@ define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
 define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqmovns64:
 ;CHECK: vqmovn.s64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
 	ret <2 x i32> %tmp2
 }
@@ -287,7 +287,7 @@ define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
 define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqmovnu16:
 ;CHECK: vqmovn.u16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
 	ret <8 x i8> %tmp2
 }
@@ -295,7 +295,7 @@ define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
 define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqmovnu32:
 ;CHECK: vqmovn.u32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
 	ret <4 x i16> %tmp2
 }
@@ -303,7 +303,7 @@ define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
 define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqmovnu64:
 ;CHECK: vqmovn.u64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
 	ret <2 x i32> %tmp2
 }
@@ -311,7 +311,7 @@ define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
 define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqmovuns16:
 ;CHECK: vqmovun.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
 	ret <8 x i8> %tmp2
 }
@@ -319,7 +319,7 @@ define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
 define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqmovuns32:
 ;CHECK: vqmovun.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
 	ret <4 x i16> %tmp2
 }
@@ -327,7 +327,7 @@ define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
 define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqmovuns64:
 ;CHECK: vqmovun.s64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
 	ret <2 x i32> %tmp2
 }
@@ -348,7 +348,7 @@ declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone
 ; Radar 8598391.
 define void @noTruncStore(<4 x i32>* %a, <4 x i16>* %b) nounwind {
 ;CHECK: vmovn
-  %tmp1 = load <4 x i32>* %a, align 16
+  %tmp1 = load <4 x i32>, <4 x i32>* %a, align 16
   %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
   store <4 x i16> %tmp2, <4 x i16>* %b, align 8
   ret void
@@ -376,7 +376,7 @@ define void @v_mov_v4f32_undef(<4 x float> * nocapture %p) nounwind {
 entry:
 ;CHECK-LABEL: v_mov_v4f32_undef:
 ;CHECK: vmov.f32 q{{.*}}, #1.000000e+00
-  %a = load <4 x float> *%p
+  %a = load <4 x float> , <4 x float> *%p
   %b = fadd <4 x float> %a, <float undef, float 1.0, float 1.0, float 1.0>
   store <4 x float> %b, <4 x float> *%p
   ret void
diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll
index 0fa43d801bbe..c3e41cacde4c 100644
--- a/test/CodeGen/ARM/vmul.ll
+++ b/test/CodeGen/ARM/vmul.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vmuli8:
 ;CHECK: vmul.i8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = mul <8 x i8> %tmp1, %tmp2
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vmuli16:
 ;CHECK: vmul.i16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = mul <4 x i16> %tmp1, %tmp2
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vmuli32:
 ;CHECK: vmul.i32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = mul <2 x i32> %tmp1, %tmp2
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vmulf32:
 ;CHECK: vmul.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fmul <2 x float> %tmp1, %tmp2
 	ret <2 x float> %tmp3
 }
@@ -39,8 +39,8 @@ define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vmulp8:
 ;CHECK: vmul.p8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -48,8 +48,8 @@ define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vmulQi8:
 ;CHECK: vmul.i8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = mul <16 x i8> %tmp1, %tmp2
 	ret <16 x i8> %tmp3
 }
@@ -57,8 +57,8 @@ define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vmulQi16:
 ;CHECK: vmul.i16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = mul <8 x i16> %tmp1, %tmp2
 	ret <8 x i16> %tmp3
 }
@@ -66,8 +66,8 @@ define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vmulQi32:
 ;CHECK: vmul.i32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = mul <4 x i32> %tmp1, %tmp2
 	ret <4 x i32> %tmp3
 }
@@ -75,8 +75,8 @@ define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vmulQf32:
 ;CHECK: vmul.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = fmul <4 x float> %tmp1, %tmp2
 	ret <4 x float> %tmp3
 }
@@ -84,8 +84,8 @@ define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 define <16 x i8> @vmulQp8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vmulQp8:
 ;CHECK: vmul.p8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -150,8 +150,8 @@ entry:
 define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vmulls8:
 ;CHECK: vmull.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
 	%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
 	%tmp5 = mul <8 x i16> %tmp3, %tmp4
@@ -161,8 +161,8 @@ define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <8 x i16> @vmulls8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vmulls8_int:
 ;CHECK: vmull.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -170,8 +170,8 @@ define <8 x i16> @vmulls8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vmulls16:
 ;CHECK: vmull.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
 	%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
 	%tmp5 = mul <4 x i32> %tmp3, %tmp4
@@ -181,8 +181,8 @@ define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <4 x i32> @vmulls16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vmulls16_int:
 ;CHECK: vmull.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -190,8 +190,8 @@ define <4 x i32> @vmulls16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vmulls32:
 ;CHECK: vmull.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
 	%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
 	%tmp5 = mul <2 x i64> %tmp3, %tmp4
@@ -201,8 +201,8 @@ define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <2 x i64> @vmulls32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vmulls32_int:
 ;CHECK: vmull.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -210,8 +210,8 @@ define <2 x i64> @vmulls32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vmullu8:
 ;CHECK: vmull.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
 	%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
 	%tmp5 = mul <8 x i16> %tmp3, %tmp4
@@ -221,8 +221,8 @@ define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <8 x i16> @vmullu8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vmullu8_int:
 ;CHECK: vmull.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -230,8 +230,8 @@ define <8 x i16> @vmullu8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vmullu16:
 ;CHECK: vmull.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
 	%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
 	%tmp5 = mul <4 x i32> %tmp3, %tmp4
@@ -241,8 +241,8 @@ define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <4 x i32> @vmullu16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vmullu16_int:
 ;CHECK: vmull.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -250,8 +250,8 @@ define <4 x i32> @vmullu16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vmullu32:
 ;CHECK: vmull.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
 	%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
 	%tmp5 = mul <2 x i64> %tmp3, %tmp4
@@ -261,8 +261,8 @@ define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <2 x i64> @vmullu32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vmullu32_int:
 ;CHECK: vmull.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -270,8 +270,8 @@ define <2 x i64> @vmullu32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vmullp8:
 ;CHECK: vmull.p8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -488,7 +488,7 @@ entry:
   %8 = bitcast double %7 to <8 x i8>
   %9 = add <8 x i8> %6, %8
   %10 = mul <8 x i8> %9, %2
-  %11 = getelementptr inbounds %struct.uint8x8_t* %dst, i32 0, i32 0
+  %11 = getelementptr inbounds %struct.uint8x8_t, %struct.uint8x8_t* %dst, i32 0, i32 0
   store <8 x i8> %10, <8 x i8>* %11, align 8
   ret void
 }
@@ -510,7 +510,7 @@ entry:
   %8 = bitcast double %7 to <8 x i8>
   %9 = add <8 x i8> %6, %8
   %10 = mul <8 x i8> %2, %9
-  %11 = getelementptr inbounds %struct.uint8x8_t* %dst, i32 0, i32 0
+  %11 = getelementptr inbounds %struct.uint8x8_t, %struct.uint8x8_t* %dst, i32 0, i32 0
   store <8 x i8> %10, <8 x i8>* %11, align 8
   ret void
 }
@@ -560,7 +560,7 @@ for.body33.lr.ph:                                 ; preds = %for.body
 for.body33:                                       ; preds = %for.body33, %for.body33.lr.ph
   %add45 = add i32 undef, undef
   %vld155 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* undef, i32 1)
-  %0 = load i32** undef, align 4
+  %0 = load i32*, i32** undef, align 4
   %shuffle.i250 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer
   %1 = bitcast <1 x i64> %shuffle.i250 to <8 x i8>
   %vmovl.i249 = zext <8 x i8> %1 to <8 x i16>
@@ -616,7 +616,7 @@ declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone
 ; PR15970
 define void @no_illegal_types_vmull_sext(<4 x i32> %a) {
 entry:
-  %wide.load283.i = load <4 x i8>* undef, align 1
+  %wide.load283.i = load <4 x i8>, <4 x i8>* undef, align 1
   %0 = sext <4 x i8> %wide.load283.i to <4 x i32>
   %1 = sub nsw <4 x i32> %0, %a
   %2 = mul nsw <4 x i32> %1, %1
@@ -626,7 +626,7 @@ entry:
 }
 define void @no_illegal_types_vmull_zext(<4 x i32> %a) {
 entry:
-  %wide.load283.i = load <4 x i8>* undef, align 1
+  %wide.load283.i = load <4 x i8>, <4 x i8>* undef, align 1
   %0 = zext <4 x i8> %wide.load283.i to <4 x i32>
   %1 = sub nsw <4 x i32> %0, %a
   %2 = mul nsw <4 x i32> %1, %1
@@ -642,8 +642,8 @@ define void @foo(<4 x float> * %a, <4 x float>* nocapture %dst, float* nocapture
 ;   and used a vector * scalar instruction.
 ; CHECK: vldr  {{s[0-9]+}}, [r2]
 ; CHECK: vmul.f32  q8, q8, d0[0]
-  %tmp = load float* %src, align 4
-  %tmp5 = load <4 x float>* %a, align 4
+  %tmp = load float, float* %src, align 4
+  %tmp5 = load <4 x float>, <4 x float>* %a, align 4
   %tmp6 = insertelement <4 x float> undef, float %tmp, i32 0
   %tmp7 = insertelement <4 x float> %tmp6, float %tmp, i32 1
   %tmp8 = insertelement <4 x float> %tmp7, float %tmp, i32 2
diff --git a/test/CodeGen/ARM/vneg.ll b/test/CodeGen/ARM/vneg.ll
index 4d548ddf8141..24a585f65a4b 100644
--- a/test/CodeGen/ARM/vneg.ll
+++ b/test/CodeGen/ARM/vneg.ll
@@ -3,7 +3,7 @@
 define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vnegs8:
 ;CHECK: vneg.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = sub <8 x i8> zeroinitializer, %tmp1
 	ret <8 x i8> %tmp2
 }
@@ -11,7 +11,7 @@ define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vnegs16:
 ;CHECK: vneg.s16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = sub <4 x i16> zeroinitializer, %tmp1
 	ret <4 x i16> %tmp2
 }
@@ -19,7 +19,7 @@ define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vnegs32:
 ;CHECK: vneg.s32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = sub <2 x i32> zeroinitializer, %tmp1
 	ret <2 x i32> %tmp2
 }
@@ -27,7 +27,7 @@ define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
 define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vnegf32:
 ;CHECK: vneg.f32
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp2 = fsub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1
 	ret <2 x float> %tmp2
 }
@@ -35,7 +35,7 @@ define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
 define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vnegQs8:
 ;CHECK: vneg.s8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = sub <16 x i8> zeroinitializer, %tmp1
 	ret <16 x i8> %tmp2
 }
@@ -43,7 +43,7 @@ define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vnegQs16:
 ;CHECK: vneg.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = sub <8 x i16> zeroinitializer, %tmp1
 	ret <8 x i16> %tmp2
 }
@@ -51,7 +51,7 @@ define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vnegQs32:
 ;CHECK: vneg.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = sub <4 x i32> zeroinitializer, %tmp1
 	ret <4 x i32> %tmp2
 }
@@ -59,7 +59,7 @@ define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
 define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: vnegQf32:
 ;CHECK: vneg.f32
-	%tmp1 = load <4 x float>* %A
+	%tmp1 = load <4 x float>, <4 x float>* %A
 	%tmp2 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1
 	ret <4 x float> %tmp2
 }
@@ -67,7 +67,7 @@ define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
 define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vqnegs8:
 ;CHECK: vqneg.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1)
 	ret <8 x i8> %tmp2
 }
@@ -75,7 +75,7 @@ define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqnegs16:
 ;CHECK: vqneg.s16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)
 	ret <4 x i16> %tmp2
 }
@@ -83,7 +83,7 @@ define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqnegs32:
 ;CHECK: vqneg.s32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1)
 	ret <2 x i32> %tmp2
 }
@@ -91,7 +91,7 @@ define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind {
 define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vqnegQs8:
 ;CHECK: vqneg.s8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1)
 	ret <16 x i8> %tmp2
 }
@@ -99,7 +99,7 @@ define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqnegQs16:
 ;CHECK: vqneg.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)
 	ret <8 x i16> %tmp2
 }
@@ -107,7 +107,7 @@ define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqnegQs32:
 ;CHECK: vqneg.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1)
 	ret <4 x i32> %tmp2
 }
diff --git a/test/CodeGen/ARM/vpadal.ll b/test/CodeGen/ARM/vpadal.ll
index ffeac737fa36..ffb69243b884 100644
--- a/test/CodeGen/ARM/vpadal.ll
+++ b/test/CodeGen/ARM/vpadal.ll
@@ -3,8 +3,8 @@
 define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vpadals8:
 ;CHECK: vpadal.s8
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -12,8 +12,8 @@ define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
 define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vpadals16:
 ;CHECK: vpadal.s16
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -21,8 +21,8 @@ define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
 define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vpadals32:
 ;CHECK: vpadal.s32
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
 	ret <1 x i64> %tmp3
 }
@@ -30,8 +30,8 @@ define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
 define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vpadalu8:
 ;CHECK: vpadal.u8
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -39,8 +39,8 @@ define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
 define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vpadalu16:
 ;CHECK: vpadal.u16
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -48,8 +48,8 @@ define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
 define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vpadalu32:
 ;CHECK: vpadal.u32
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
 	ret <1 x i64> %tmp3
 }
@@ -57,8 +57,8 @@ define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vpadalQs8:
 ;CHECK: vpadal.s8
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -66,8 +66,8 @@ define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vpadalQs16:
 ;CHECK: vpadal.s16
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -75,8 +75,8 @@ define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vpadalQs32:
 ;CHECK: vpadal.s32
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -84,8 +84,8 @@ define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
 define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vpadalQu8:
 ;CHECK: vpadal.u8
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -93,8 +93,8 @@ define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vpadalQu16:
 ;CHECK: vpadal.u16
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -102,8 +102,8 @@ define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vpadalQu32:
 ;CHECK: vpadal.u32
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
 	ret <2 x i64> %tmp3
 }
diff --git a/test/CodeGen/ARM/vpadd.ll b/test/CodeGen/ARM/vpadd.ll
index 01cb1c74e38e..e362ce36f8ba 100644
--- a/test/CodeGen/ARM/vpadd.ll
+++ b/test/CodeGen/ARM/vpadd.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vpaddi8:
 ;CHECK: vpadd.i8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vpaddi16:
 ;CHECK: vpadd.i16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vpaddi32:
 ;CHECK: vpadd.i32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vpaddf32:
 ;CHECK: vpadd.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
@@ -45,7 +45,7 @@ declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwin
 define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vpaddls8:
 ;CHECK: vpaddl.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1)
 	ret <4 x i16> %tmp2
 }
@@ -53,7 +53,7 @@ define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
 define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vpaddls16:
 ;CHECK: vpaddl.s16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1)
 	ret <2 x i32> %tmp2
 }
@@ -61,7 +61,7 @@ define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
 define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vpaddls32:
 ;CHECK: vpaddl.s32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1)
 	ret <1 x i64> %tmp2
 }
@@ -69,7 +69,7 @@ define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
 define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vpaddlu8:
 ;CHECK: vpaddl.u8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1)
 	ret <4 x i16> %tmp2
 }
@@ -77,7 +77,7 @@ define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
 define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vpaddlu16:
 ;CHECK: vpaddl.u16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1)
 	ret <2 x i32> %tmp2
 }
@@ -85,7 +85,7 @@ define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
 define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vpaddlu32:
 ;CHECK: vpaddl.u32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1)
 	ret <1 x i64> %tmp2
 }
@@ -93,7 +93,7 @@ define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
 define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vpaddlQs8:
 ;CHECK: vpaddl.s8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1)
 	ret <8 x i16> %tmp2
 }
@@ -101,7 +101,7 @@ define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
 define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vpaddlQs16:
 ;CHECK: vpaddl.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1)
 	ret <4 x i32> %tmp2
 }
@@ -109,7 +109,7 @@ define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
 define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vpaddlQs32:
 ;CHECK: vpaddl.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1)
 	ret <2 x i64> %tmp2
 }
@@ -117,7 +117,7 @@ define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
 define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vpaddlQu8:
 ;CHECK: vpaddl.u8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1)
 	ret <8 x i16> %tmp2
 }
@@ -125,7 +125,7 @@ define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
 define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vpaddlQu16:
 ;CHECK: vpaddl.u16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1)
 	ret <4 x i32> %tmp2
 }
@@ -133,7 +133,7 @@ define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
 define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vpaddlQu32:
 ;CHECK: vpaddl.u32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)
 	ret <2 x i64> %tmp2
 }
@@ -143,9 +143,9 @@ define void @addCombineToVPADDL() nounwind ssp {
 ; CHECK: vpaddl.s8
   %cbcr = alloca <16 x i8>, align 16
   %X = alloca <8 x i8>, align 8
-  %tmp = load <16 x i8>* %cbcr
+  %tmp = load <16 x i8>, <16 x i8>* %cbcr
   %tmp1 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
-  %tmp2 = load <16 x i8>* %cbcr
+  %tmp2 = load <16 x i8>, <16 x i8>* %cbcr
   %tmp3 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
   %add = add <8 x i8> %tmp3, %tmp1
   store <8 x i8> %add, <8 x i8>* %X, align 8
diff --git a/test/CodeGen/ARM/vpminmax.ll b/test/CodeGen/ARM/vpminmax.ll
index 0b893e5bc892..9ea8c69612c5 100644
--- a/test/CodeGen/ARM/vpminmax.ll
+++ b/test/CodeGen/ARM/vpminmax.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vpmins8:
 ;CHECK: vpmin.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vpmins16:
 ;CHECK: vpmin.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vpmins32:
 ;CHECK: vpmin.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vpminu8:
 ;CHECK: vpmin.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -39,8 +39,8 @@ define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vpminu16:
 ;CHECK: vpmin.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -48,8 +48,8 @@ define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vpminu32:
 ;CHECK: vpmin.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -57,8 +57,8 @@ define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <2 x float> @vpminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vpminf32:
 ;CHECK: vpmin.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
@@ -76,8 +76,8 @@ declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>) nounwi
 define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vpmaxs8:
 ;CHECK: vpmax.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -85,8 +85,8 @@ define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vpmaxs16:
 ;CHECK: vpmax.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -94,8 +94,8 @@ define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vpmaxs32:
 ;CHECK: vpmax.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -103,8 +103,8 @@ define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vpmaxu8:
 ;CHECK: vpmax.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -112,8 +112,8 @@ define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vpmaxu16:
 ;CHECK: vpmax.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -121,8 +121,8 @@ define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vpmaxu32:
 ;CHECK: vpmax.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -130,8 +130,8 @@ define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <2 x float> @vpmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vpmaxf32:
 ;CHECK: vpmax.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
diff --git a/test/CodeGen/ARM/vqadd.ll b/test/CodeGen/ARM/vqadd.ll
index 81acc8bc5abb..d1e90cb20944 100644
--- a/test/CodeGen/ARM/vqadd.ll
+++ b/test/CodeGen/ARM/vqadd.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqadds8:
 ;CHECK: vqadd.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqadds16:
 ;CHECK: vqadd.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqadds32:
 ;CHECK: vqadd.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqadds64:
 ;CHECK: vqadd.s64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
 	ret <1 x i64> %tmp3
 }
@@ -39,8 +39,8 @@ define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqaddu8:
 ;CHECK: vqadd.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -48,8 +48,8 @@ define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqaddu16:
 ;CHECK: vqadd.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -57,8 +57,8 @@ define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqaddu32:
 ;CHECK: vqadd.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -66,8 +66,8 @@ define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqaddu64:
 ;CHECK: vqadd.u64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
 	ret <1 x i64> %tmp3
 }
@@ -75,8 +75,8 @@ define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqaddQs8:
 ;CHECK: vqadd.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -84,8 +84,8 @@ define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqaddQs16:
 ;CHECK: vqadd.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -93,8 +93,8 @@ define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqaddQs32:
 ;CHECK: vqadd.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -102,8 +102,8 @@ define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqaddQs64:
 ;CHECK: vqadd.s64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -111,8 +111,8 @@ define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqaddQu8:
 ;CHECK: vqadd.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -120,8 +120,8 @@ define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqaddQu16:
 ;CHECK: vqadd.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -129,8 +129,8 @@ define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqaddQu32:
 ;CHECK: vqadd.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -138,8 +138,8 @@ define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vqaddQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqaddQu64:
 ;CHECK: vqadd.u64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
diff --git a/test/CodeGen/ARM/vqdmul.ll b/test/CodeGen/ARM/vqdmul.ll
index d298167d3a91..6da080012a1e 100644
--- a/test/CodeGen/ARM/vqdmul.ll
+++ b/test/CodeGen/ARM/vqdmul.ll
@@ -5,8 +5,8 @@ target triple = "thumbv7-elf"
 define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqdmulhs16:
 ;CHECK: vqdmulh.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -14,8 +14,8 @@ define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqdmulhs32:
 ;CHECK: vqdmulh.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -23,8 +23,8 @@ define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqdmulhQs16:
 ;CHECK: vqdmulh.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -32,8 +32,8 @@ define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vqdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqdmulhQs32:
 ;CHECK: vqdmulh.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -83,8 +83,8 @@ declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind re
 define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqrdmulhs16:
 ;CHECK: vqrdmulh.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -92,8 +92,8 @@ define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqrdmulhs32:
 ;CHECK: vqrdmulh.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -101,8 +101,8 @@ define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqrdmulhQs16:
 ;CHECK: vqrdmulh.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -110,8 +110,8 @@ define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vqrdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqrdmulhQs32:
 ;CHECK: vqrdmulh.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -161,8 +161,8 @@ declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind r
 define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqdmulls16:
 ;CHECK: vqdmull.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -170,8 +170,8 @@ define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @vqdmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqdmulls32:
 ;CHECK: vqdmull.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -200,9 +200,9 @@ declare <2 x i64>  @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind r
 define <4 x i32> @vqdmlals16_natural(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK-LABEL: vqdmlals16_natural:
 ;CHECK: vqdmlal.s16
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i16>* %B
-        %tmp3 = load <4 x i16>* %C
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
+        %tmp3 = load <4 x i16>, <4 x i16>* %C
         %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp2, <4 x i16> %tmp3)
         %tmp5 = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp4)
         ret <4 x i32> %tmp5
@@ -211,9 +211,9 @@ define <4 x i32> @vqdmlals16_natural(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C
 define <2 x i64> @vqdmlals32_natural(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK-LABEL: vqdmlals32_natural:
 ;CHECK: vqdmlal.s32
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i32>* %B
-        %tmp3 = load <2 x i32>* %C
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
+        %tmp3 = load <2 x i32>, <2 x i32>* %C
         %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp2, <2 x i32> %tmp3)
         %tmp5 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp4)
         ret <2 x i64> %tmp5
@@ -245,9 +245,9 @@ declare <2 x i64>  @llvm.arm.neon.vqadds.v2i64(<2 x i64>, <2 x i64>) nounwind re
 define <4 x i32> @vqdmlsls16_natural(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK-LABEL: vqdmlsls16_natural:
 ;CHECK: vqdmlsl.s16
-        %tmp1 = load <4 x i32>* %A
-        %tmp2 = load <4 x i16>* %B
-        %tmp3 = load <4 x i16>* %C
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
+        %tmp2 = load <4 x i16>, <4 x i16>* %B
+        %tmp3 = load <4 x i16>, <4 x i16>* %C
         %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp2, <4 x i16> %tmp3)
         %tmp5 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp4)
         ret <4 x i32> %tmp5
@@ -256,9 +256,9 @@ define <4 x i32> @vqdmlsls16_natural(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C
 define <2 x i64> @vqdmlsls32_natural(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK-LABEL: vqdmlsls32_natural:
 ;CHECK: vqdmlsl.s32
-        %tmp1 = load <2 x i64>* %A
-        %tmp2 = load <2 x i32>* %B
-        %tmp3 = load <2 x i32>* %C
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = load <2 x i32>, <2 x i32>* %B
+        %tmp3 = load <2 x i32>, <2 x i32>* %C
         %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp2, <2 x i32> %tmp3)
         %tmp5 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp4)
         ret <2 x i64> %tmp5
diff --git a/test/CodeGen/ARM/vqshl.ll b/test/CodeGen/ARM/vqshl.ll
index 4afef6dbd658..6a6d9af7a2b3 100644
--- a/test/CodeGen/ARM/vqshl.ll
+++ b/test/CodeGen/ARM/vqshl.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqshls8:
 ;CHECK: vqshl.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqshls16:
 ;CHECK: vqshl.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqshls32:
 ;CHECK: vqshl.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqshls64:
 ;CHECK: vqshl.s64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
 	ret <1 x i64> %tmp3
 }
@@ -39,8 +39,8 @@ define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqshlu8:
 ;CHECK: vqshl.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -48,8 +48,8 @@ define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqshlu16:
 ;CHECK: vqshl.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -57,8 +57,8 @@ define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqshlu32:
 ;CHECK: vqshl.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -66,8 +66,8 @@ define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqshlu64:
 ;CHECK: vqshl.u64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
 	ret <1 x i64> %tmp3
 }
@@ -75,8 +75,8 @@ define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqshlQs8:
 ;CHECK: vqshl.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -84,8 +84,8 @@ define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqshlQs16:
 ;CHECK: vqshl.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -93,8 +93,8 @@ define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqshlQs32:
 ;CHECK: vqshl.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -102,8 +102,8 @@ define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqshlQs64:
 ;CHECK: vqshl.s64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -111,8 +111,8 @@ define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqshlQu8:
 ;CHECK: vqshl.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -120,8 +120,8 @@ define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqshlQu16:
 ;CHECK: vqshl.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -129,8 +129,8 @@ define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqshlQu32:
 ;CHECK: vqshl.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -138,8 +138,8 @@ define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqshlQu64:
 ;CHECK: vqshl.u64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -147,7 +147,7 @@ define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vqshls_n8:
 ;CHECK: vqshl.s8{{.*#7}}
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
 	ret <8 x i8> %tmp2
 }
@@ -155,7 +155,7 @@ define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqshls_n16:
 ;CHECK: vqshl.s16{{.*#15}}
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
 	ret <4 x i16> %tmp2
 }
@@ -163,7 +163,7 @@ define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqshls_n32:
 ;CHECK: vqshl.s32{{.*#31}}
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
 	ret <2 x i32> %tmp2
 }
@@ -171,7 +171,7 @@ define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind {
 define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqshls_n64:
 ;CHECK: vqshl.s64{{.*#63}}
-	%tmp1 = load <1 x i64>* %A
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
 	ret <1 x i64> %tmp2
 }
@@ -179,7 +179,7 @@ define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind {
 define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vqshlu_n8:
 ;CHECK: vqshl.u8{{.*#7}}
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
 	ret <8 x i8> %tmp2
 }
@@ -187,7 +187,7 @@ define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqshlu_n16:
 ;CHECK: vqshl.u16{{.*#15}}
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
 	ret <4 x i16> %tmp2
 }
@@ -195,7 +195,7 @@ define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqshlu_n32:
 ;CHECK: vqshl.u32{{.*#31}}
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
 	ret <2 x i32> %tmp2
 }
@@ -203,7 +203,7 @@ define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind {
 define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqshlu_n64:
 ;CHECK: vqshl.u64{{.*#63}}
-	%tmp1 = load <1 x i64>* %A
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
 	ret <1 x i64> %tmp2
 }
@@ -211,7 +211,7 @@ define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind {
 define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vqshlsu_n8:
 ;CHECK: vqshlu.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
 	ret <8 x i8> %tmp2
 }
@@ -219,7 +219,7 @@ define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqshlsu_n16:
 ;CHECK: vqshlu.s16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
 	ret <4 x i16> %tmp2
 }
@@ -227,7 +227,7 @@ define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqshlsu_n32:
 ;CHECK: vqshlu.s32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
 	ret <2 x i32> %tmp2
 }
@@ -235,7 +235,7 @@ define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind {
 define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqshlsu_n64:
 ;CHECK: vqshlu.s64
-	%tmp1 = load <1 x i64>* %A
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
 	ret <1 x i64> %tmp2
 }
@@ -243,7 +243,7 @@ define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind {
 define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vqshlQs_n8:
 ;CHECK: vqshl.s8{{.*#7}}
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
 	ret <16 x i8> %tmp2
 }
@@ -251,7 +251,7 @@ define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqshlQs_n16:
 ;CHECK: vqshl.s16{{.*#15}}
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
 	ret <8 x i16> %tmp2
 }
@@ -259,7 +259,7 @@ define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqshlQs_n32:
 ;CHECK: vqshl.s32{{.*#31}}
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
 	ret <4 x i32> %tmp2
 }
@@ -267,7 +267,7 @@ define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind {
 define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqshlQs_n64:
 ;CHECK: vqshl.s64{{.*#63}}
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
 	ret <2 x i64> %tmp2
 }
@@ -275,7 +275,7 @@ define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind {
 define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vqshlQu_n8:
 ;CHECK: vqshl.u8{{.*#7}}
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
 	ret <16 x i8> %tmp2
 }
@@ -283,7 +283,7 @@ define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqshlQu_n16:
 ;CHECK: vqshl.u16{{.*#15}}
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
 	ret <8 x i16> %tmp2
 }
@@ -291,7 +291,7 @@ define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqshlQu_n32:
 ;CHECK: vqshl.u32{{.*#31}}
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
 	ret <4 x i32> %tmp2
 }
@@ -299,7 +299,7 @@ define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind {
 define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqshlQu_n64:
 ;CHECK: vqshl.u64{{.*#63}}
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
 	ret <2 x i64> %tmp2
 }
@@ -307,7 +307,7 @@ define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind {
 define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vqshlQsu_n8:
 ;CHECK: vqshlu.s8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
 	ret <16 x i8> %tmp2
 }
@@ -315,7 +315,7 @@ define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqshlQsu_n16:
 ;CHECK: vqshlu.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
 	ret <8 x i16> %tmp2
 }
@@ -323,7 +323,7 @@ define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqshlQsu_n32:
 ;CHECK: vqshlu.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
 	ret <4 x i32> %tmp2
 }
@@ -331,7 +331,7 @@ define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind {
 define <2 x i64> @vqshlQsu_n64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqshlQsu_n64:
 ;CHECK: vqshlu.s64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
 	ret <2 x i64> %tmp2
 }
@@ -369,8 +369,8 @@ declare <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64>, <2 x i64>) nounwind
 define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqrshls8:
 ;CHECK: vqrshl.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -378,8 +378,8 @@ define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqrshls16:
 ;CHECK: vqrshl.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -387,8 +387,8 @@ define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqrshls32:
 ;CHECK: vqrshl.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vqrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -396,8 +396,8 @@ define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqrshls64:
 ;CHECK: vqrshl.s64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
 	ret <1 x i64> %tmp3
 }
@@ -405,8 +405,8 @@ define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqrshlu8:
 ;CHECK: vqrshl.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -414,8 +414,8 @@ define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqrshlu16:
 ;CHECK: vqrshl.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -423,8 +423,8 @@ define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqrshlu32:
 ;CHECK: vqrshl.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vqrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -432,8 +432,8 @@ define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqrshlu64:
 ;CHECK: vqrshl.u64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
 	ret <1 x i64> %tmp3
 }
@@ -441,8 +441,8 @@ define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqrshlQs8:
 ;CHECK: vqrshl.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -450,8 +450,8 @@ define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqrshlQs16:
 ;CHECK: vqrshl.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vqrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -459,8 +459,8 @@ define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqrshlQs32:
 ;CHECK: vqrshl.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vqrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -468,8 +468,8 @@ define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqrshlQs64:
 ;CHECK: vqrshl.s64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vqrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -477,8 +477,8 @@ define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqrshlQu8:
 ;CHECK: vqrshl.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -486,8 +486,8 @@ define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqrshlQu16:
 ;CHECK: vqrshl.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vqrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -495,8 +495,8 @@ define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqrshlQu32:
 ;CHECK: vqrshl.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vqrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -504,8 +504,8 @@ define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vqrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqrshlQu64:
 ;CHECK: vqrshl.u64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vqrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
diff --git a/test/CodeGen/ARM/vqshrn.ll b/test/CodeGen/ARM/vqshrn.ll
index f02482c0f77c..b4b5e96d4579 100644
--- a/test/CodeGen/ARM/vqshrn.ll
+++ b/test/CodeGen/ARM/vqshrn.ll
@@ -3,7 +3,7 @@
 define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqshrns8:
 ;CHECK: vqshrn.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
 	ret <8 x i8> %tmp2
 }
@@ -11,7 +11,7 @@ define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
 define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqshrns16:
 ;CHECK: vqshrn.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
 	ret <4 x i16> %tmp2
 }
@@ -19,7 +19,7 @@ define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
 define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqshrns32:
 ;CHECK: vqshrn.s64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
 	ret <2 x i32> %tmp2
 }
@@ -27,7 +27,7 @@ define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
 define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqshrnu8:
 ;CHECK: vqshrn.u16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
 	ret <8 x i8> %tmp2
 }
@@ -35,7 +35,7 @@ define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
 define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqshrnu16:
 ;CHECK: vqshrn.u32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
 	ret <4 x i16> %tmp2
 }
@@ -43,7 +43,7 @@ define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
 define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqshrnu32:
 ;CHECK: vqshrn.u64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
 	ret <2 x i32> %tmp2
 }
@@ -51,7 +51,7 @@ define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
 define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqshruns8:
 ;CHECK: vqshrun.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
 	ret <8 x i8> %tmp2
 }
@@ -59,7 +59,7 @@ define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
 define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqshruns16:
 ;CHECK: vqshrun.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
 	ret <4 x i16> %tmp2
 }
@@ -67,7 +67,7 @@ define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
 define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqshruns32:
 ;CHECK: vqshrun.s64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
 	ret <2 x i32> %tmp2
 }
@@ -87,7 +87,7 @@ declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind
 define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqrshrns8:
 ;CHECK: vqrshrn.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
 	ret <8 x i8> %tmp2
 }
@@ -95,7 +95,7 @@ define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
 define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqrshrns16:
 ;CHECK: vqrshrn.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
 	ret <4 x i16> %tmp2
 }
@@ -103,7 +103,7 @@ define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
 define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqrshrns32:
 ;CHECK: vqrshrn.s64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
 	ret <2 x i32> %tmp2
 }
@@ -111,7 +111,7 @@ define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
 define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqrshrnu8:
 ;CHECK: vqrshrn.u16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
 	ret <8 x i8> %tmp2
 }
@@ -119,7 +119,7 @@ define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
 define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqrshrnu16:
 ;CHECK: vqrshrn.u32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
 	ret <4 x i16> %tmp2
 }
@@ -127,7 +127,7 @@ define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
 define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqrshrnu32:
 ;CHECK: vqrshrn.u64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
 	ret <2 x i32> %tmp2
 }
@@ -135,7 +135,7 @@ define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
 define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqrshruns8:
 ;CHECK: vqrshrun.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
 	ret <8 x i8> %tmp2
 }
@@ -143,7 +143,7 @@ define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
 define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqrshruns16:
 ;CHECK: vqrshrun.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
 	ret <4 x i16> %tmp2
 }
@@ -151,7 +151,7 @@ define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
 define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqrshruns32:
 ;CHECK: vqrshrun.s64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
 	ret <2 x i32> %tmp2
 }
diff --git a/test/CodeGen/ARM/vqsub.ll b/test/CodeGen/ARM/vqsub.ll
index 4af438019208..40963ce82486 100644
--- a/test/CodeGen/ARM/vqsub.ll
+++ b/test/CodeGen/ARM/vqsub.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqsubs8:
 ;CHECK: vqsub.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqsubs16:
 ;CHECK: vqsub.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqsubs32:
 ;CHECK: vqsub.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqsubs64:
 ;CHECK: vqsub.s64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
 	ret <1 x i64> %tmp3
 }
@@ -39,8 +39,8 @@ define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqsubu8:
 ;CHECK: vqsub.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -48,8 +48,8 @@ define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqsubu16:
 ;CHECK: vqsub.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -57,8 +57,8 @@ define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqsubu32:
 ;CHECK: vqsub.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -66,8 +66,8 @@ define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqsubu64:
 ;CHECK: vqsub.u64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
 	ret <1 x i64> %tmp3
 }
@@ -75,8 +75,8 @@ define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqsubQs8:
 ;CHECK: vqsub.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -84,8 +84,8 @@ define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqsubQs16:
 ;CHECK: vqsub.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -93,8 +93,8 @@ define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqsubQs32:
 ;CHECK: vqsub.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -102,8 +102,8 @@ define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqsubQs64:
 ;CHECK: vqsub.s64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -111,8 +111,8 @@ define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vqsubQu8:
 ;CHECK: vqsub.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -120,8 +120,8 @@ define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vqsubQu16:
 ;CHECK: vqsub.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -129,8 +129,8 @@ define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vqsubQu32:
 ;CHECK: vqsub.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -138,8 +138,8 @@ define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vqsubQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vqsubQu64:
 ;CHECK: vqsub.u64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
diff --git a/test/CodeGen/ARM/vrec.ll b/test/CodeGen/ARM/vrec.ll
index 91979e5a3343..a7ebd79289d8 100644
--- a/test/CodeGen/ARM/vrec.ll
+++ b/test/CodeGen/ARM/vrec.ll
@@ -3,7 +3,7 @@
 define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vrecpei32:
 ;CHECK: vrecpe.u32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
 	ret <2 x i32> %tmp2
 }
@@ -11,7 +11,7 @@ define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind {
 define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vrecpeQi32:
 ;CHECK: vrecpe.u32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
 	ret <4 x i32> %tmp2
 }
@@ -19,7 +19,7 @@ define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind {
 define <2 x float> @vrecpef32(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vrecpef32:
 ;CHECK: vrecpe.f32
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
 	ret <2 x float> %tmp2
 }
@@ -27,7 +27,7 @@ define <2 x float> @vrecpef32(<2 x float>* %A) nounwind {
 define <4 x float> @vrecpeQf32(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: vrecpeQf32:
 ;CHECK: vrecpe.f32
-	%tmp1 = load <4 x float>* %A
+	%tmp1 = load <4 x float>, <4 x float>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
 	ret <4 x float> %tmp2
 }
@@ -41,8 +41,8 @@ declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
 define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vrecpsf32:
 ;CHECK: vrecps.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
@@ -50,8 +50,8 @@ define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x float> @vrecpsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vrecpsQf32:
 ;CHECK: vrecps.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x float> %tmp3
 }
@@ -62,7 +62,7 @@ declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwi
 define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vrsqrtei32:
 ;CHECK: vrsqrte.u32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
 	ret <2 x i32> %tmp2
 }
@@ -70,7 +70,7 @@ define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind {
 define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vrsqrteQi32:
 ;CHECK: vrsqrte.u32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
 	ret <4 x i32> %tmp2
 }
@@ -78,7 +78,7 @@ define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind {
 define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vrsqrtef32:
 ;CHECK: vrsqrte.f32
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
 	ret <2 x float> %tmp2
 }
@@ -86,7 +86,7 @@ define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind {
 define <4 x float> @vrsqrteQf32(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: vrsqrteQf32:
 ;CHECK: vrsqrte.f32
-	%tmp1 = load <4 x float>* %A
+	%tmp1 = load <4 x float>, <4 x float>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
 	ret <4 x float> %tmp2
 }
@@ -100,8 +100,8 @@ declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
 define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vrsqrtsf32:
 ;CHECK: vrsqrts.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
 	ret <2 x float> %tmp3
 }
@@ -109,8 +109,8 @@ define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <4 x float> @vrsqrtsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vrsqrtsQf32:
 ;CHECK: vrsqrts.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x float> %tmp3
 }
diff --git a/test/CodeGen/ARM/vrev.ll b/test/CodeGen/ARM/vrev.ll
index 7215ad615e81..a20d4b6baf29 100644
--- a/test/CodeGen/ARM/vrev.ll
+++ b/test/CodeGen/ARM/vrev.ll
@@ -3,7 +3,7 @@
 define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64D8:
 ;CHECK: vrev64.8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
 	ret <8 x i8> %tmp2
 }
@@ -11,7 +11,7 @@ define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
 define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64D16:
 ;CHECK: vrev64.16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
 	ret <4 x i16> %tmp2
 }
@@ -19,7 +19,7 @@ define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
 define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64D32:
 ;CHECK: vrev64.32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
 	ret <2 x i32> %tmp2
 }
@@ -27,7 +27,7 @@ define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
 define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64Df:
 ;CHECK: vrev64.32
-	%tmp1 = load <2 x float>* %A
+	%tmp1 = load <2 x float>, <2 x float>* %A
 	%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
 	ret <2 x float> %tmp2
 }
@@ -35,7 +35,7 @@ define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
 define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64Q8:
 ;CHECK: vrev64.8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
 	ret <16 x i8> %tmp2
 }
@@ -43,7 +43,7 @@ define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
 define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64Q16:
 ;CHECK: vrev64.16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
 	ret <8 x i16> %tmp2
 }
@@ -51,7 +51,7 @@ define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
 define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64Q32:
 ;CHECK: vrev64.32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
 	ret <4 x i32> %tmp2
 }
@@ -59,7 +59,7 @@ define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
 define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64Qf:
 ;CHECK: vrev64.32
-	%tmp1 = load <4 x float>* %A
+	%tmp1 = load <4 x float>, <4 x float>* %A
 	%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
 	ret <4 x float> %tmp2
 }
@@ -67,7 +67,7 @@ define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
 define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: test_vrev32D8:
 ;CHECK: vrev32.8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
 	ret <8 x i8> %tmp2
 }
@@ -75,7 +75,7 @@ define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
 define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: test_vrev32D16:
 ;CHECK: vrev32.16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
 	ret <4 x i16> %tmp2
 }
@@ -83,7 +83,7 @@ define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
 define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: test_vrev32Q8:
 ;CHECK: vrev32.8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
 	ret <16 x i8> %tmp2
 }
@@ -91,7 +91,7 @@ define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
 define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: test_vrev32Q16:
 ;CHECK: vrev32.16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
 	ret <8 x i16> %tmp2
 }
@@ -99,7 +99,7 @@ define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
 define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: test_vrev16D8:
 ;CHECK: vrev16.8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
 	ret <8 x i8> %tmp2
 }
@@ -107,7 +107,7 @@ define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
 define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: test_vrev16Q8:
 ;CHECK: vrev16.8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
 	ret <16 x i8> %tmp2
 }
@@ -117,7 +117,7 @@ define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
 define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: test_vrev64D8_undef:
 ;CHECK: vrev64.8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
 	ret <8 x i8> %tmp2
 }
@@ -125,7 +125,7 @@ define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
 define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: test_vrev32Q16_undef:
 ;CHECK: vrev32.16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
 	ret <8 x i16> %tmp2
 }
@@ -136,7 +136,7 @@ define void @test_with_vcombine(<4 x float>* %v) nounwind {
 ;CHECK-LABEL: test_with_vcombine:
 ;CHECK-NOT: vext
 ;CHECK: vrev64.32
-  %tmp1 = load <4 x float>* %v, align 16
+  %tmp1 = load <4 x float>, <4 x float>* %v, align 16
   %tmp2 = bitcast <4 x float> %tmp1 to <2 x double>
   %tmp3 = extractelement <2 x double> %tmp2, i32 0
   %tmp4 = bitcast double %tmp3 to <2 x float>
@@ -155,7 +155,7 @@ define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst
 ; CHECK: vst1.32
 entry:
   %0 = bitcast <4 x i16>* %source to <8 x i16>*
-  %tmp2 = load <8 x i16>* %0, align 4
+  %tmp2 = load <8 x i16>, <8 x i16>* %0, align 4
   %tmp3 = extractelement <8 x i16> %tmp2, i32 6
   %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0
   %tmp9 = extractelement <8 x i16> %tmp2, i32 5
@@ -171,9 +171,9 @@ define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest
 ; CHECK: vrev64.32
 entry:
   %0 = bitcast float* %source to <4 x float>*
-  %tmp2 = load <4 x float>* %0, align 4
+  %tmp2 = load <4 x float>, <4 x float>* %0, align 4
   %tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0>
-  %arrayidx8 = getelementptr inbounds <4 x float>* %dest, i32 11
+  %arrayidx8 = getelementptr inbounds <4 x float>, <4 x float>* %dest, i32 11
   store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4
   ret void
 }
diff --git a/test/CodeGen/ARM/vselect_imax.ll b/test/CodeGen/ARM/vselect_imax.ll
index e999034fa47e..0eb051036d99 100644
--- a/test/CodeGen/ARM/vselect_imax.ll
+++ b/test/CodeGen/ARM/vselect_imax.ll
@@ -18,8 +18,8 @@ define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: func_blend10:
 define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2,
                            %T1_10* %blend, %T0_10* %storeaddr) {
-  %v0 = load %T0_10* %loadaddr
-  %v1 = load %T0_10* %loadaddr2
+  %v0 = load %T0_10, %T0_10* %loadaddr
+  %v1 = load %T0_10, %T0_10* %loadaddr2
   %c = icmp slt %T0_10 %v0, %v1
 ; CHECK: vbsl
 ; CHECK: vbsl
@@ -34,8 +34,8 @@ define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2,
 ; CHECK-LABEL: func_blend14:
 define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2,
                            %T1_14* %blend, %T0_14* %storeaddr) {
-  %v0 = load %T0_14* %loadaddr
-  %v1 = load %T0_14* %loadaddr2
+  %v0 = load %T0_14, %T0_14* %loadaddr
+  %v1 = load %T0_14, %T0_14* %loadaddr2
   %c = icmp slt %T0_14 %v0, %v1
 ; CHECK: vbsl
 ; CHECK: vbsl
@@ -52,8 +52,8 @@ define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2,
                            %T1_15* %blend, %T0_15* %storeaddr) {
 ; CHECK: vbsl
 ; CHECK: vbsl
-  %v0 = load %T0_15* %loadaddr
-  %v1 = load %T0_15* %loadaddr2
+  %v0 = load %T0_15, %T0_15* %loadaddr
+  %v1 = load %T0_15, %T0_15* %loadaddr2
   %c = icmp slt %T0_15 %v0, %v1
 ; COST: func_blend15
 ; COST: cost of 82 {{.*}} select
@@ -68,8 +68,8 @@ define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2,
                            %T1_18* %blend, %T0_18* %storeaddr) {
 ; CHECK: vbsl
 ; CHECK: vbsl
-  %v0 = load %T0_18* %loadaddr
-  %v1 = load %T0_18* %loadaddr2
+  %v0 = load %T0_18, %T0_18* %loadaddr
+  %v1 = load %T0_18, %T0_18* %loadaddr2
   %c = icmp slt %T0_18 %v0, %v1
 ; COST: func_blend18
 ; COST: cost of 19 {{.*}} select
@@ -86,8 +86,8 @@ define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2,
 ; CHECK: vbsl
 ; CHECK: vbsl
 ; CHECK: vbsl
-  %v0 = load %T0_19* %loadaddr
-  %v1 = load %T0_19* %loadaddr2
+  %v0 = load %T0_19, %T0_19* %loadaddr
+  %v1 = load %T0_19, %T0_19* %loadaddr2
   %c = icmp slt %T0_19 %v0, %v1
 ; COST: func_blend19
 ; COST: cost of 50 {{.*}} select
@@ -108,8 +108,8 @@ define void @func_blend20(%T0_20* %loadaddr, %T0_20* %loadaddr2,
 ; CHECK: vbsl
 ; CHECK: vbsl
 ; CHECK: vbsl
-  %v0 = load %T0_20* %loadaddr
-  %v1 = load %T0_20* %loadaddr2
+  %v0 = load %T0_20, %T0_20* %loadaddr
+  %v1 = load %T0_20, %T0_20* %loadaddr2
   %c = icmp slt %T0_20 %v0, %v1
 ; COST: func_blend20
 ; COST: cost of 100 {{.*}} select
diff --git a/test/CodeGen/ARM/vshift.ll b/test/CodeGen/ARM/vshift.ll
index 618a137b5b05..31e4cb05dd20 100644
--- a/test/CodeGen/ARM/vshift.ll
+++ b/test/CodeGen/ARM/vshift.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vshls8:
 ;CHECK: vshl.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shl <8 x i8> %tmp1, %tmp2
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vshls16:
 ;CHECK: vshl.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = shl <4 x i16> %tmp1, %tmp2
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vshls32:
 ;CHECK: vshl.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = shl <2 x i32> %tmp1, %tmp2
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vshls64:
 ;CHECK: vshl.u64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = shl <1 x i64> %tmp1, %tmp2
 	ret <1 x i64> %tmp3
 }
@@ -39,7 +39,7 @@ define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vshli8:
 ;CHECK: vshl.i8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
 	ret <8 x i8> %tmp2
 }
@@ -47,7 +47,7 @@ define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vshli16:
 ;CHECK: vshl.i16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = shl <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >
 	ret <4 x i16> %tmp2
 }
@@ -55,7 +55,7 @@ define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vshli32:
 ;CHECK: vshl.i32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = shl <2 x i32> %tmp1, < i32 31, i32 31 >
 	ret <2 x i32> %tmp2
 }
@@ -63,7 +63,7 @@ define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
 define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
 ;CHECK-LABEL: vshli64:
 ;CHECK: vshl.i64
-	%tmp1 = load <1 x i64>* %A
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
 	%tmp2 = shl <1 x i64> %tmp1, < i64 63 >
 	ret <1 x i64> %tmp2
 }
@@ -71,8 +71,8 @@ define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
 define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vshlQs8:
 ;CHECK: vshl.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = shl <16 x i8> %tmp1, %tmp2
 	ret <16 x i8> %tmp3
 }
@@ -80,8 +80,8 @@ define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vshlQs16:
 ;CHECK: vshl.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = shl <8 x i16> %tmp1, %tmp2
 	ret <8 x i16> %tmp3
 }
@@ -89,8 +89,8 @@ define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vshlQs32:
 ;CHECK: vshl.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = shl <4 x i32> %tmp1, %tmp2
 	ret <4 x i32> %tmp3
 }
@@ -98,8 +98,8 @@ define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vshlQs64:
 ;CHECK: vshl.u64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = shl <2 x i64> %tmp1, %tmp2
 	ret <2 x i64> %tmp3
 }
@@ -107,7 +107,7 @@ define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vshlQi8:
 ;CHECK: vshl.i8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = shl <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
 	ret <16 x i8> %tmp2
 }
@@ -115,7 +115,7 @@ define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vshlQi16:
 ;CHECK: vshl.i16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = shl <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
 	ret <8 x i16> %tmp2
 }
@@ -123,7 +123,7 @@ define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vshlQi32:
 ;CHECK: vshl.i32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = shl <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >
 	ret <4 x i32> %tmp2
 }
@@ -131,7 +131,7 @@ define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
 define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vshlQi64:
 ;CHECK: vshl.i64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 >
 	ret <2 x i64> %tmp2
 }
@@ -140,8 +140,8 @@ define <8 x i8> @vlshru8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vlshru8:
 ;CHECK: vneg.s8
 ;CHECK: vshl.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = lshr <8 x i8> %tmp1, %tmp2
 	ret <8 x i8> %tmp3
 }
@@ -150,8 +150,8 @@ define <4 x i16> @vlshru16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vlshru16:
 ;CHECK: vneg.s16
 ;CHECK: vshl.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = lshr <4 x i16> %tmp1, %tmp2
 	ret <4 x i16> %tmp3
 }
@@ -160,8 +160,8 @@ define <2 x i32> @vlshru32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vlshru32:
 ;CHECK: vneg.s32
 ;CHECK: vshl.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = lshr <2 x i32> %tmp1, %tmp2
 	ret <2 x i32> %tmp3
 }
@@ -170,8 +170,8 @@ define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vlshru64:
 ;CHECK: vsub.i64
 ;CHECK: vshl.u64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = lshr <1 x i64> %tmp1, %tmp2
 	ret <1 x i64> %tmp3
 }
@@ -179,7 +179,7 @@ define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vlshri8:
 ;CHECK: vshr.u8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = lshr <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
 	ret <8 x i8> %tmp2
 }
@@ -187,7 +187,7 @@ define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vlshri16:
 ;CHECK: vshr.u16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = lshr <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >
 	ret <4 x i16> %tmp2
 }
@@ -195,7 +195,7 @@ define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vlshri32:
 ;CHECK: vshr.u32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = lshr <2 x i32> %tmp1, < i32 31, i32 31 >
 	ret <2 x i32> %tmp2
 }
@@ -203,7 +203,7 @@ define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind {
 define <1 x i64> @vlshri64(<1 x i64>* %A) nounwind {
 ;CHECK-LABEL: vlshri64:
 ;CHECK: vshr.u64
-	%tmp1 = load <1 x i64>* %A
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
 	%tmp2 = lshr <1 x i64> %tmp1, < i64 63 >
 	ret <1 x i64> %tmp2
 }
@@ -212,8 +212,8 @@ define <16 x i8> @vlshrQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vlshrQu8:
 ;CHECK: vneg.s8
 ;CHECK: vshl.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = lshr <16 x i8> %tmp1, %tmp2
 	ret <16 x i8> %tmp3
 }
@@ -222,8 +222,8 @@ define <8 x i16> @vlshrQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vlshrQu16:
 ;CHECK: vneg.s16
 ;CHECK: vshl.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = lshr <8 x i16> %tmp1, %tmp2
 	ret <8 x i16> %tmp3
 }
@@ -232,8 +232,8 @@ define <4 x i32> @vlshrQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vlshrQu32:
 ;CHECK: vneg.s32
 ;CHECK: vshl.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = lshr <4 x i32> %tmp1, %tmp2
 	ret <4 x i32> %tmp3
 }
@@ -242,8 +242,8 @@ define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vlshrQu64:
 ;CHECK: vsub.i64
 ;CHECK: vshl.u64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = lshr <2 x i64> %tmp1, %tmp2
 	ret <2 x i64> %tmp3
 }
@@ -251,7 +251,7 @@ define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vlshrQi8:
 ;CHECK: vshr.u8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = lshr <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
 	ret <16 x i8> %tmp2
 }
@@ -259,7 +259,7 @@ define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vlshrQi16:
 ;CHECK: vshr.u16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = lshr <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
 	ret <8 x i16> %tmp2
 }
@@ -267,7 +267,7 @@ define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vlshrQi32:
 ;CHECK: vshr.u32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = lshr <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >
 	ret <4 x i32> %tmp2
 }
@@ -275,7 +275,7 @@ define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind {
 define <2 x i64> @vlshrQi64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vlshrQi64:
 ;CHECK: vshr.u64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = lshr <2 x i64> %tmp1, < i64 63, i64 63 >
 	ret <2 x i64> %tmp2
 }
@@ -291,8 +291,8 @@ define <8 x i8> @vashrs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vashrs8:
 ;CHECK: vneg.s8
 ;CHECK: vshl.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = ashr <8 x i8> %tmp1, %tmp2
 	ret <8 x i8> %tmp3
 }
@@ -301,8 +301,8 @@ define <4 x i16> @vashrs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vashrs16:
 ;CHECK: vneg.s16
 ;CHECK: vshl.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = ashr <4 x i16> %tmp1, %tmp2
 	ret <4 x i16> %tmp3
 }
@@ -311,8 +311,8 @@ define <2 x i32> @vashrs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vashrs32:
 ;CHECK: vneg.s32
 ;CHECK: vshl.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = ashr <2 x i32> %tmp1, %tmp2
 	ret <2 x i32> %tmp3
 }
@@ -321,8 +321,8 @@ define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vashrs64:
 ;CHECK: vsub.i64
 ;CHECK: vshl.s64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = ashr <1 x i64> %tmp1, %tmp2
 	ret <1 x i64> %tmp3
 }
@@ -330,7 +330,7 @@ define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <8 x i8> @vashri8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vashri8:
 ;CHECK: vshr.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = ashr <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
 	ret <8 x i8> %tmp2
 }
@@ -338,7 +338,7 @@ define <8 x i8> @vashri8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vashri16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vashri16:
 ;CHECK: vshr.s16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = ashr <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >
 	ret <4 x i16> %tmp2
 }
@@ -346,7 +346,7 @@ define <4 x i16> @vashri16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vashri32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vashri32:
 ;CHECK: vshr.s32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = ashr <2 x i32> %tmp1, < i32 31, i32 31 >
 	ret <2 x i32> %tmp2
 }
@@ -354,7 +354,7 @@ define <2 x i32> @vashri32(<2 x i32>* %A) nounwind {
 define <1 x i64> @vashri64(<1 x i64>* %A) nounwind {
 ;CHECK-LABEL: vashri64:
 ;CHECK: vshr.s64
-	%tmp1 = load <1 x i64>* %A
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
 	%tmp2 = ashr <1 x i64> %tmp1, < i64 63 >
 	ret <1 x i64> %tmp2
 }
@@ -363,8 +363,8 @@ define <16 x i8> @vashrQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vashrQs8:
 ;CHECK: vneg.s8
 ;CHECK: vshl.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = ashr <16 x i8> %tmp1, %tmp2
 	ret <16 x i8> %tmp3
 }
@@ -373,8 +373,8 @@ define <8 x i16> @vashrQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vashrQs16:
 ;CHECK: vneg.s16
 ;CHECK: vshl.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = ashr <8 x i16> %tmp1, %tmp2
 	ret <8 x i16> %tmp3
 }
@@ -383,8 +383,8 @@ define <4 x i32> @vashrQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vashrQs32:
 ;CHECK: vneg.s32
 ;CHECK: vshl.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = ashr <4 x i32> %tmp1, %tmp2
 	ret <4 x i32> %tmp3
 }
@@ -393,8 +393,8 @@ define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vashrQs64:
 ;CHECK: vsub.i64
 ;CHECK: vshl.s64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = ashr <2 x i64> %tmp1, %tmp2
 	ret <2 x i64> %tmp3
 }
@@ -402,7 +402,7 @@ define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vashrQi8:
 ;CHECK: vshr.s8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = ashr <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
 	ret <16 x i8> %tmp2
 }
@@ -410,7 +410,7 @@ define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vashrQi16:
 ;CHECK: vshr.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = ashr <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
 	ret <8 x i16> %tmp2
 }
@@ -418,7 +418,7 @@ define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vashrQi32:
 ;CHECK: vshr.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = ashr <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >
 	ret <4 x i32> %tmp2
 }
@@ -426,7 +426,7 @@ define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind {
 define <2 x i64> @vashrQi64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vashrQi64:
 ;CHECK: vshr.s64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = ashr <2 x i64> %tmp1, < i64 63, i64 63 >
 	ret <2 x i64> %tmp2
 }
diff --git a/test/CodeGen/ARM/vshiftins.ll b/test/CodeGen/ARM/vshiftins.ll
index 9526c3222017..29487378317d 100644
--- a/test/CodeGen/ARM/vshiftins.ll
+++ b/test/CodeGen/ARM/vshiftins.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsli8:
 ;CHECK: vsli.8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsli16:
 ;CHECK: vsli.16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsli32:
 ;CHECK: vsli.32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 31, i32 31 >)
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vsli64:
 ;CHECK: vsli.64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 63 >)
 	ret <1 x i64> %tmp3
 }
@@ -39,8 +39,8 @@ define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsliQ8:
 ;CHECK: vsli.8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
 	ret <16 x i8> %tmp3
 }
@@ -48,8 +48,8 @@ define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsliQ16:
 ;CHECK: vsli.16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
 	ret <8 x i16> %tmp3
 }
@@ -57,8 +57,8 @@ define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsliQ32:
 ;CHECK: vsli.32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
 	ret <4 x i32> %tmp3
 }
@@ -66,8 +66,8 @@ define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vsliQ64:
 ;CHECK: vsli.64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 63, i64 63 >)
 	ret <2 x i64> %tmp3
 }
@@ -75,8 +75,8 @@ define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsri8:
 ;CHECK: vsri.8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
 	ret <8 x i8> %tmp3
 }
@@ -84,8 +84,8 @@ define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsri16:
 ;CHECK: vsri.16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
 	ret <4 x i16> %tmp3
 }
@@ -93,8 +93,8 @@ define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsri32:
 ;CHECK: vsri.32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
 	ret <2 x i32> %tmp3
 }
@@ -102,8 +102,8 @@ define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vsri64:
 ;CHECK: vsri.64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 -64 >)
 	ret <1 x i64> %tmp3
 }
@@ -111,8 +111,8 @@ define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsriQ8:
 ;CHECK: vsri.8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
 	ret <16 x i8> %tmp3
 }
@@ -120,8 +120,8 @@ define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsriQ16:
 ;CHECK: vsri.16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
 	ret <8 x i16> %tmp3
 }
@@ -129,8 +129,8 @@ define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsriQ32:
 ;CHECK: vsri.32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
 	ret <4 x i32> %tmp3
 }
@@ -138,8 +138,8 @@ define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vsriQ64:
 ;CHECK: vsri.64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
 	ret <2 x i64> %tmp3
 }
diff --git a/test/CodeGen/ARM/vshl.ll b/test/CodeGen/ARM/vshl.ll
index 6228652fc715..ef76e3d9a36c 100644
--- a/test/CodeGen/ARM/vshl.ll
+++ b/test/CodeGen/ARM/vshl.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vshls8:
 ;CHECK: vshl.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vshls16:
 ;CHECK: vshl.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vshls32:
 ;CHECK: vshl.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vshls64:
 ;CHECK: vshl.s64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
 	ret <1 x i64> %tmp3
 }
@@ -39,8 +39,8 @@ define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vshlu8:
 ;CHECK: vshl.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -48,8 +48,8 @@ define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vshlu16:
 ;CHECK: vshl.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -57,8 +57,8 @@ define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vshlu32:
 ;CHECK: vshl.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -66,8 +66,8 @@ define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vshlu64:
 ;CHECK: vshl.u64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
 	ret <1 x i64> %tmp3
 }
@@ -75,8 +75,8 @@ define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vshlQs8:
 ;CHECK: vshl.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -84,8 +84,8 @@ define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vshlQs16:
 ;CHECK: vshl.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -93,8 +93,8 @@ define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vshlQs32:
 ;CHECK: vshl.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -102,8 +102,8 @@ define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vshlQs64:
 ;CHECK: vshl.s64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -111,8 +111,8 @@ define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vshlQu8:
 ;CHECK: vshl.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -120,8 +120,8 @@ define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vshlQu16:
 ;CHECK: vshl.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -129,8 +129,8 @@ define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vshlQu32:
 ;CHECK: vshl.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -138,8 +138,8 @@ define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vshlQu64:
 ;CHECK: vshl.u64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -150,7 +150,7 @@ define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vshli8:
 ;CHECK: vshl.i8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
 	ret <8 x i8> %tmp2
 }
@@ -158,7 +158,7 @@ define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vshli16:
 ;CHECK: vshl.i16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
 	ret <4 x i16> %tmp2
 }
@@ -166,7 +166,7 @@ define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vshli32:
 ;CHECK: vshl.i32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
 	ret <2 x i32> %tmp2
 }
@@ -174,7 +174,7 @@ define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
 define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
 ;CHECK-LABEL: vshli64:
 ;CHECK: vshl.i64
-	%tmp1 = load <1 x i64>* %A
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
 	ret <1 x i64> %tmp2
 }
@@ -182,7 +182,7 @@ define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
 define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vshlQi8:
 ;CHECK: vshl.i8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
 	ret <16 x i8> %tmp2
 }
@@ -190,7 +190,7 @@ define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vshlQi16:
 ;CHECK: vshl.i16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
 	ret <8 x i16> %tmp2
 }
@@ -198,7 +198,7 @@ define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vshlQi32:
 ;CHECK: vshl.i32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
 	ret <4 x i32> %tmp2
 }
@@ -206,7 +206,7 @@ define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
 define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vshlQi64:
 ;CHECK: vshl.i64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
 	ret <2 x i64> %tmp2
 }
@@ -216,7 +216,7 @@ define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
 define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vshrs8:
 ;CHECK: vshr.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
 	ret <8 x i8> %tmp2
 }
@@ -224,7 +224,7 @@ define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vshrs16:
 ;CHECK: vshr.s16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
 	ret <4 x i16> %tmp2
 }
@@ -232,7 +232,7 @@ define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vshrs32:
 ;CHECK: vshr.s32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
 	ret <2 x i32> %tmp2
 }
@@ -240,7 +240,7 @@ define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind {
 define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind {
 ;CHECK-LABEL: vshrs64:
 ;CHECK: vshr.s64
-	%tmp1 = load <1 x i64>* %A
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
 	ret <1 x i64> %tmp2
 }
@@ -248,7 +248,7 @@ define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind {
 define <8 x i8> @vshru8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vshru8:
 ;CHECK: vshr.u8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
 	ret <8 x i8> %tmp2
 }
@@ -256,7 +256,7 @@ define <8 x i8> @vshru8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vshru16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vshru16:
 ;CHECK: vshr.u16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
 	ret <4 x i16> %tmp2
 }
@@ -264,7 +264,7 @@ define <4 x i16> @vshru16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vshru32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vshru32:
 ;CHECK: vshr.u32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
 	ret <2 x i32> %tmp2
 }
@@ -272,7 +272,7 @@ define <2 x i32> @vshru32(<2 x i32>* %A) nounwind {
 define <1 x i64> @vshru64(<1 x i64>* %A) nounwind {
 ;CHECK-LABEL: vshru64:
 ;CHECK: vshr.u64
-	%tmp1 = load <1 x i64>* %A
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
 	ret <1 x i64> %tmp2
 }
@@ -280,7 +280,7 @@ define <1 x i64> @vshru64(<1 x i64>* %A) nounwind {
 define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vshrQs8:
 ;CHECK: vshr.s8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
 	ret <16 x i8> %tmp2
 }
@@ -288,7 +288,7 @@ define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vshrQs16:
 ;CHECK: vshr.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
 	ret <8 x i16> %tmp2
 }
@@ -296,7 +296,7 @@ define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vshrQs32:
 ;CHECK: vshr.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
 	ret <4 x i32> %tmp2
 }
@@ -304,7 +304,7 @@ define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind {
 define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vshrQs64:
 ;CHECK: vshr.s64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
 	ret <2 x i64> %tmp2
 }
@@ -312,7 +312,7 @@ define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind {
 define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vshrQu8:
 ;CHECK: vshr.u8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
 	ret <16 x i8> %tmp2
 }
@@ -320,7 +320,7 @@ define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vshrQu16:
 ;CHECK: vshr.u16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
 	ret <8 x i16> %tmp2
 }
@@ -328,7 +328,7 @@ define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vshrQu32:
 ;CHECK: vshr.u32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
 	ret <4 x i32> %tmp2
 }
@@ -336,7 +336,7 @@ define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind {
 define <2 x i64> @vshrQu64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vshrQu64:
 ;CHECK: vshr.u64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
 	ret <2 x i64> %tmp2
 }
@@ -364,8 +364,8 @@ declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind re
 define <8 x i8> @vrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vrshls8:
 ;CHECK: vrshl.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -373,8 +373,8 @@ define <8 x i8> @vrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vrshls16:
 ;CHECK: vrshl.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -382,8 +382,8 @@ define <4 x i16> @vrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vrshls32:
 ;CHECK: vrshl.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -391,8 +391,8 @@ define <2 x i32> @vrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vrshls64:
 ;CHECK: vrshl.s64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
 	ret <1 x i64> %tmp3
 }
@@ -400,8 +400,8 @@ define <1 x i64> @vrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <8 x i8> @vrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vrshlu8:
 ;CHECK: vrshl.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -409,8 +409,8 @@ define <8 x i8> @vrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vrshlu16:
 ;CHECK: vrshl.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -418,8 +418,8 @@ define <4 x i16> @vrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vrshlu32:
 ;CHECK: vrshl.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -427,8 +427,8 @@ define <2 x i32> @vrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vrshlu64:
 ;CHECK: vrshl.u64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
 	ret <1 x i64> %tmp3
 }
@@ -436,8 +436,8 @@ define <1 x i64> @vrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @vrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vrshlQs8:
 ;CHECK: vrshl.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -445,8 +445,8 @@ define <16 x i8> @vrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vrshlQs16:
 ;CHECK: vrshl.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -454,8 +454,8 @@ define <8 x i16> @vrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vrshlQs32:
 ;CHECK: vrshl.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -463,8 +463,8 @@ define <4 x i32> @vrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vrshlQs64:
 ;CHECK: vrshl.s64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -472,8 +472,8 @@ define <2 x i64> @vrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @vrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vrshlQu8:
 ;CHECK: vrshl.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
 	ret <16 x i8> %tmp3
 }
@@ -481,8 +481,8 @@ define <16 x i8> @vrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vrshlQu16:
 ;CHECK: vrshl.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i16> %tmp3
 }
@@ -490,8 +490,8 @@ define <8 x i16> @vrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vrshlQu32:
 ;CHECK: vrshl.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i32> %tmp3
 }
@@ -499,8 +499,8 @@ define <4 x i32> @vrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vrshlQu64:
 ;CHECK: vrshl.u64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
@@ -508,7 +508,7 @@ define <2 x i64> @vrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @vrshrs8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vrshrs8:
 ;CHECK: vrshr.s8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
 	ret <8 x i8> %tmp2
 }
@@ -516,7 +516,7 @@ define <8 x i8> @vrshrs8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vrshrs16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vrshrs16:
 ;CHECK: vrshr.s16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
 	ret <4 x i16> %tmp2
 }
@@ -524,7 +524,7 @@ define <4 x i16> @vrshrs16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vrshrs32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vrshrs32:
 ;CHECK: vrshr.s32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
 	ret <2 x i32> %tmp2
 }
@@ -532,7 +532,7 @@ define <2 x i32> @vrshrs32(<2 x i32>* %A) nounwind {
 define <1 x i64> @vrshrs64(<1 x i64>* %A) nounwind {
 ;CHECK-LABEL: vrshrs64:
 ;CHECK: vrshr.s64
-	%tmp1 = load <1 x i64>* %A
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
 	ret <1 x i64> %tmp2
 }
@@ -540,7 +540,7 @@ define <1 x i64> @vrshrs64(<1 x i64>* %A) nounwind {
 define <8 x i8> @vrshru8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vrshru8:
 ;CHECK: vrshr.u8
-	%tmp1 = load <8 x i8>* %A
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
 	ret <8 x i8> %tmp2
 }
@@ -548,7 +548,7 @@ define <8 x i8> @vrshru8(<8 x i8>* %A) nounwind {
 define <4 x i16> @vrshru16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vrshru16:
 ;CHECK: vrshr.u16
-	%tmp1 = load <4 x i16>* %A
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
 	ret <4 x i16> %tmp2
 }
@@ -556,7 +556,7 @@ define <4 x i16> @vrshru16(<4 x i16>* %A) nounwind {
 define <2 x i32> @vrshru32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vrshru32:
 ;CHECK: vrshr.u32
-	%tmp1 = load <2 x i32>* %A
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
 	ret <2 x i32> %tmp2
 }
@@ -564,7 +564,7 @@ define <2 x i32> @vrshru32(<2 x i32>* %A) nounwind {
 define <1 x i64> @vrshru64(<1 x i64>* %A) nounwind {
 ;CHECK-LABEL: vrshru64:
 ;CHECK: vrshr.u64
-	%tmp1 = load <1 x i64>* %A
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
 	ret <1 x i64> %tmp2
 }
@@ -572,7 +572,7 @@ define <1 x i64> @vrshru64(<1 x i64>* %A) nounwind {
 define <16 x i8> @vrshrQs8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vrshrQs8:
 ;CHECK: vrshr.s8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
 	ret <16 x i8> %tmp2
 }
@@ -580,7 +580,7 @@ define <16 x i8> @vrshrQs8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vrshrQs16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vrshrQs16:
 ;CHECK: vrshr.s16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
 	ret <8 x i16> %tmp2
 }
@@ -588,7 +588,7 @@ define <8 x i16> @vrshrQs16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vrshrQs32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vrshrQs32:
 ;CHECK: vrshr.s32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
 	ret <4 x i32> %tmp2
 }
@@ -596,7 +596,7 @@ define <4 x i32> @vrshrQs32(<4 x i32>* %A) nounwind {
 define <2 x i64> @vrshrQs64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vrshrQs64:
 ;CHECK: vrshr.s64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
 	ret <2 x i64> %tmp2
 }
@@ -604,7 +604,7 @@ define <2 x i64> @vrshrQs64(<2 x i64>* %A) nounwind {
 define <16 x i8> @vrshrQu8(<16 x i8>* %A) nounwind {
 ;CHECK-LABEL: vrshrQu8:
 ;CHECK: vrshr.u8
-	%tmp1 = load <16 x i8>* %A
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
 	ret <16 x i8> %tmp2
 }
@@ -612,7 +612,7 @@ define <16 x i8> @vrshrQu8(<16 x i8>* %A) nounwind {
 define <8 x i16> @vrshrQu16(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vrshrQu16:
 ;CHECK: vrshr.u16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
 	ret <8 x i16> %tmp2
 }
@@ -620,7 +620,7 @@ define <8 x i16> @vrshrQu16(<8 x i16>* %A) nounwind {
 define <4 x i32> @vrshrQu32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vrshrQu32:
 ;CHECK: vrshr.u32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
 	ret <4 x i32> %tmp2
 }
@@ -628,7 +628,7 @@ define <4 x i32> @vrshrQu32(<4 x i32>* %A) nounwind {
 define <2 x i64> @vrshrQu64(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vrshrQu64:
 ;CHECK: vrshr.u64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
 	ret <2 x i64> %tmp2
 }
diff --git a/test/CodeGen/ARM/vshll.ll b/test/CodeGen/ARM/vshll.ll
index 27873eb72753..a8230134d91f 100644
--- a/test/CodeGen/ARM/vshll.ll
+++ b/test/CodeGen/ARM/vshll.ll
@@ -3,7 +3,7 @@
 define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vshlls8:
 ;CHECK: vshll.s8
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %sext = sext <8 x i8> %tmp1 to <8 x i16>
         %shift = shl <8 x i16> %sext, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
         ret <8 x i16> %shift
@@ -12,7 +12,7 @@ define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind {
 define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vshlls16:
 ;CHECK: vshll.s16
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %sext = sext <4 x i16> %tmp1 to <4 x i32>
         %shift = shl <4 x i32> %sext, <i32 15, i32 15, i32 15, i32 15>
         ret <4 x i32> %shift
@@ -21,7 +21,7 @@ define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind {
 define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vshlls32:
 ;CHECK: vshll.s32
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %sext = sext <2 x i32> %tmp1 to <2 x i64>
         %shift = shl <2 x i64> %sext, <i64 31, i64 31>
         ret <2 x i64> %shift
@@ -30,7 +30,7 @@ define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind {
 define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vshllu8:
 ;CHECK: vshll.u8
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %zext = zext <8 x i8> %tmp1 to <8 x i16>
         %shift = shl <8 x i16> %zext, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
         ret <8 x i16> %shift
@@ -39,7 +39,7 @@ define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind {
 define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vshllu16:
 ;CHECK: vshll.u16
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %zext = zext <4 x i16> %tmp1 to <4 x i32>
         %shift = shl <4 x i32> %zext, <i32 15, i32 15, i32 15, i32 15>
         ret <4 x i32> %shift
@@ -48,7 +48,7 @@ define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind {
 define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vshllu32:
 ;CHECK: vshll.u32
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %zext = zext <2 x i32> %tmp1 to <2 x i64>
         %shift = shl <2 x i64> %zext, <i64 31, i64 31>
         ret <2 x i64> %shift
@@ -59,7 +59,7 @@ define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind {
 define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vshlli8:
 ;CHECK: vshll.i8
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %sext = sext <8 x i8> %tmp1 to <8 x i16>
         %shift = shl <8 x i16> %sext, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
         ret <8 x i16> %shift
@@ -68,7 +68,7 @@ define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind {
 define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vshlli16:
 ;CHECK: vshll.i16
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %zext = zext <4 x i16> %tmp1 to <4 x i32>
         %shift = shl <4 x i32> %zext, <i32 16, i32 16, i32 16, i32 16>
         ret <4 x i32> %shift
@@ -77,7 +77,7 @@ define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind {
 define <2 x i64> @vshlli32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vshlli32:
 ;CHECK: vshll.i32
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %zext = zext <2 x i32> %tmp1 to <2 x i64>
         %shift = shl <2 x i64> %zext, <i64 32, i64 32>
         ret <2 x i64> %shift
@@ -89,7 +89,7 @@ define <8 x i16> @vshllu8_bad(<8 x i8>* %A) nounwind {
 ; CHECK-LABEL: vshllu8_bad:
 ; CHECK: vmovl.u8
 ; CHECK: vshl.i16
-        %tmp1 = load <8 x i8>* %A
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
         %zext = zext <8 x i8> %tmp1 to <8 x i16>
         %shift = shl <8 x i16> %zext, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
         ret <8 x i16> %shift
@@ -99,7 +99,7 @@ define <4 x i32> @vshlls16_bad(<4 x i16>* %A) nounwind {
 ; CHECK-LABEL: vshlls16_bad:
 ; CHECK: vmovl.s16
 ; CHECK: vshl.i32
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %sext = sext <4 x i16> %tmp1 to <4 x i32>
         %shift = shl <4 x i32> %sext, <i32 17, i32 17, i32 17, i32 17>
         ret <4 x i32> %shift
@@ -109,7 +109,7 @@ define <2 x i64> @vshllu32_bad(<2 x i32>* %A) nounwind {
 ; CHECK-LABEL: vshllu32_bad:
 ; CHECK: vmovl.u32
 ; CHECK: vshl.i64
-        %tmp1 = load <2 x i32>* %A
+        %tmp1 = load <2 x i32>, <2 x i32>* %A
         %zext = zext <2 x i32> %tmp1 to <2 x i64>
         %shift = shl <2 x i64> %zext, <i64 33, i64 33>
         ret <2 x i64> %shift
diff --git a/test/CodeGen/ARM/vshrn.ll b/test/CodeGen/ARM/vshrn.ll
index 8aa009ab823e..e033486562c6 100644
--- a/test/CodeGen/ARM/vshrn.ll
+++ b/test/CodeGen/ARM/vshrn.ll
@@ -3,7 +3,7 @@
 define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vshrns8:
 ;CHECK: vshrn.i16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp2 = lshr <8 x i16> %tmp1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
         %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>
 	ret <8 x i8> %tmp3
@@ -12,7 +12,7 @@ define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind {
 define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vshrns16:
 ;CHECK: vshrn.i32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp2 = ashr <4 x i32> %tmp1, <i32 16, i32 16, i32 16, i32 16>
         %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>
 	ret <4 x i16> %tmp3
@@ -21,7 +21,7 @@ define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind {
 define <2 x i32> @vshrns32(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vshrns32:
 ;CHECK: vshrn.i64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp2 = ashr <2 x i64> %tmp1, <i64 32, i64 32>
         %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>
 	ret <2 x i32> %tmp3
@@ -31,7 +31,7 @@ define <8 x i8> @vshrns8_bad(<8 x i16>* %A) nounwind {
 ; CHECK-LABEL: vshrns8_bad:
 ; CHECK: vshr.s16
 ; CHECK: vmovn.i16
-        %tmp1 = load <8 x i16>* %A
+        %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp2 = ashr <8 x i16> %tmp1, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
         %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>
         ret <8 x i8> %tmp3
@@ -41,7 +41,7 @@ define <4 x i16> @vshrns16_bad(<4 x i32>* %A) nounwind {
 ; CHECK-LABEL: vshrns16_bad:
 ; CHECK: vshr.u32
 ; CHECK: vmovn.i32
-        %tmp1 = load <4 x i32>* %A
+        %tmp1 = load <4 x i32>, <4 x i32>* %A
         %tmp2 = lshr <4 x i32> %tmp1, <i32 17, i32 17, i32 17, i32 17>
         %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>
         ret <4 x i16> %tmp3
@@ -51,7 +51,7 @@ define <2 x i32> @vshrns32_bad(<2 x i64>* %A) nounwind {
 ; CHECK-LABEL: vshrns32_bad:
 ; CHECK: vshr.u64
 ; CHECK: vmovn.i64
-        %tmp1 = load <2 x i64>* %A
+        %tmp1 = load <2 x i64>, <2 x i64>* %A
         %tmp2 = lshr <2 x i64> %tmp1, <i64 33, i64 33>
         %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>
         ret <2 x i32> %tmp3
@@ -60,7 +60,7 @@ define <2 x i32> @vshrns32_bad(<2 x i64>* %A) nounwind {
 define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vrshrns8:
 ;CHECK: vrshrn.i16
-	%tmp1 = load <8 x i16>* %A
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
 	ret <8 x i8> %tmp2
 }
@@ -68,7 +68,7 @@ define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind {
 define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vrshrns16:
 ;CHECK: vrshrn.i32
-	%tmp1 = load <4 x i32>* %A
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
 	ret <4 x i16> %tmp2
 }
@@ -76,7 +76,7 @@ define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind {
 define <2 x i32> @vrshrns32(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vrshrns32:
 ;CHECK: vrshrn.i64
-	%tmp1 = load <2 x i64>* %A
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
 	ret <2 x i32> %tmp2
 }
diff --git a/test/CodeGen/ARM/vsra.ll b/test/CodeGen/ARM/vsra.ll
index fa5985a330c4..cb758fa2f386 100644
--- a/test/CodeGen/ARM/vsra.ll
+++ b/test/CodeGen/ARM/vsra.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsras8:
 ;CHECK: vsra.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = ashr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
     %tmp4 = add <8 x i8> %tmp1, %tmp3
 	ret <8 x i8> %tmp4
@@ -13,8 +13,8 @@ define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsras16:
 ;CHECK: vsra.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = ashr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
         %tmp4 = add <4 x i16> %tmp1, %tmp3
 	ret <4 x i16> %tmp4
@@ -23,8 +23,8 @@ define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsras32:
 ;CHECK: vsra.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = ashr <2 x i32> %tmp2, < i32 31, i32 31 >
         %tmp4 = add <2 x i32> %tmp1, %tmp3
 	ret <2 x i32> %tmp4
@@ -33,8 +33,8 @@ define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vsras64:
 ;CHECK: vsra.s64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = ashr <1 x i64> %tmp2, < i64 63 >
         %tmp4 = add <1 x i64> %tmp1, %tmp3
 	ret <1 x i64> %tmp4
@@ -43,8 +43,8 @@ define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsraQs8:
 ;CHECK: vsra.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = ashr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
         %tmp4 = add <16 x i8> %tmp1, %tmp3
 	ret <16 x i8> %tmp4
@@ -53,8 +53,8 @@ define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsraQs16:
 ;CHECK: vsra.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = ashr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
         %tmp4 = add <8 x i16> %tmp1, %tmp3
 	ret <8 x i16> %tmp4
@@ -63,8 +63,8 @@ define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsraQs32:
 ;CHECK: vsra.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = ashr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
         %tmp4 = add <4 x i32> %tmp1, %tmp3
 	ret <4 x i32> %tmp4
@@ -73,8 +73,8 @@ define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vsraQs64:
 ;CHECK: vsra.s64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = ashr <2 x i64> %tmp2, < i64 63, i64 63 >
         %tmp4 = add <2 x i64> %tmp1, %tmp3
 	ret <2 x i64> %tmp4
@@ -83,8 +83,8 @@ define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsrau8:
 ;CHECK: vsra.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = lshr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
         %tmp4 = add <8 x i8> %tmp1, %tmp3
 	ret <8 x i8> %tmp4
@@ -93,8 +93,8 @@ define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsrau16:
 ;CHECK: vsra.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = lshr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
         %tmp4 = add <4 x i16> %tmp1, %tmp3
 	ret <4 x i16> %tmp4
@@ -103,8 +103,8 @@ define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsrau32:
 ;CHECK: vsra.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = lshr <2 x i32> %tmp2, < i32 31, i32 31 >
         %tmp4 = add <2 x i32> %tmp1, %tmp3
 	ret <2 x i32> %tmp4
@@ -113,8 +113,8 @@ define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vsrau64:
 ;CHECK: vsra.u64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = lshr <1 x i64> %tmp2, < i64 63 >
         %tmp4 = add <1 x i64> %tmp1, %tmp3
 	ret <1 x i64> %tmp4
@@ -123,8 +123,8 @@ define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsraQu8:
 ;CHECK: vsra.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = lshr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
         %tmp4 = add <16 x i8> %tmp1, %tmp3
 	ret <16 x i8> %tmp4
@@ -133,8 +133,8 @@ define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsraQu16:
 ;CHECK: vsra.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = lshr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
         %tmp4 = add <8 x i16> %tmp1, %tmp3
 	ret <8 x i16> %tmp4
@@ -143,8 +143,8 @@ define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsraQu32:
 ;CHECK: vsra.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = lshr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
         %tmp4 = add <4 x i32> %tmp1, %tmp3
 	ret <4 x i32> %tmp4
@@ -153,8 +153,8 @@ define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vsraQu64:
 ;CHECK: vsra.u64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = lshr <2 x i64> %tmp2, < i64 63, i64 63 >
         %tmp4 = add <2 x i64> %tmp1, %tmp3
 	ret <2 x i64> %tmp4
@@ -163,8 +163,8 @@ define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vrsras8:
 ;CHECK: vrsra.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
         %tmp4 = add <8 x i8> %tmp1, %tmp3
 	ret <8 x i8> %tmp4
@@ -173,8 +173,8 @@ define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vrsras16:
 ;CHECK: vrsra.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
         %tmp4 = add <4 x i16> %tmp1, %tmp3
 	ret <4 x i16> %tmp4
@@ -183,8 +183,8 @@ define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vrsras32:
 ;CHECK: vrsra.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
         %tmp4 = add <2 x i32> %tmp1, %tmp3
 	ret <2 x i32> %tmp4
@@ -193,8 +193,8 @@ define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vrsras64:
 ;CHECK: vrsra.s64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
         %tmp4 = add <1 x i64> %tmp1, %tmp3
 	ret <1 x i64> %tmp4
@@ -203,8 +203,8 @@ define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vrsrau8:
 ;CHECK: vrsra.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
         %tmp4 = add <8 x i8> %tmp1, %tmp3
 	ret <8 x i8> %tmp4
@@ -213,8 +213,8 @@ define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vrsrau16:
 ;CHECK: vrsra.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
         %tmp4 = add <4 x i16> %tmp1, %tmp3
 	ret <4 x i16> %tmp4
@@ -223,8 +223,8 @@ define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vrsrau32:
 ;CHECK: vrsra.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
         %tmp4 = add <2 x i32> %tmp1, %tmp3
 	ret <2 x i32> %tmp4
@@ -233,8 +233,8 @@ define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vrsrau64:
 ;CHECK: vrsra.u64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
         %tmp4 = add <1 x i64> %tmp1, %tmp3
 	ret <1 x i64> %tmp4
@@ -243,8 +243,8 @@ define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vrsraQs8:
 ;CHECK: vrsra.s8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
         %tmp4 = add <16 x i8> %tmp1, %tmp3
 	ret <16 x i8> %tmp4
@@ -253,8 +253,8 @@ define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vrsraQs16:
 ;CHECK: vrsra.s16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
         %tmp4 = add <8 x i16> %tmp1, %tmp3
 	ret <8 x i16> %tmp4
@@ -263,8 +263,8 @@ define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vrsraQs32:
 ;CHECK: vrsra.s32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
         %tmp4 = add <4 x i32> %tmp1, %tmp3
 	ret <4 x i32> %tmp4
@@ -273,8 +273,8 @@ define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vrsraQs64:
 ;CHECK: vrsra.s64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
         %tmp4 = add <2 x i64> %tmp1, %tmp3
 	ret <2 x i64> %tmp4
@@ -283,8 +283,8 @@ define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vrsraQu8:
 ;CHECK: vrsra.u8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
         %tmp4 = add <16 x i8> %tmp1, %tmp3
 	ret <16 x i8> %tmp4
@@ -293,8 +293,8 @@ define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vrsraQu16:
 ;CHECK: vrsra.u16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
         %tmp4 = add <8 x i16> %tmp1, %tmp3
 	ret <8 x i16> %tmp4
@@ -303,8 +303,8 @@ define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vrsraQu32:
 ;CHECK: vrsra.u32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
         %tmp4 = add <4 x i32> %tmp1, %tmp3
 	ret <4 x i32> %tmp4
@@ -313,8 +313,8 @@ define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vrsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vrsraQu64:
 ;CHECK: vrsra.u64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
         %tmp4 = add <2 x i64> %tmp1, %tmp3
 	ret <2 x i64> %tmp4
diff --git a/test/CodeGen/ARM/vst1.ll b/test/CodeGen/ARM/vst1.ll
index a6bcf7d8ead3..f605fa4d6003 100644
--- a/test/CodeGen/ARM/vst1.ll
+++ b/test/CodeGen/ARM/vst1.ll
@@ -4,7 +4,7 @@ define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vst1i8:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vst1.8 {d16}, [r0:64]
-	%tmp1 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
 	call void @llvm.arm.neon.vst1.v8i8(i8* %A, <8 x i8> %tmp1, i32 16)
 	ret void
 }
@@ -13,7 +13,7 @@ define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vst1i16:
 ;CHECK: vst1.16
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %B
 	call void @llvm.arm.neon.vst1.v4i16(i8* %tmp0, <4 x i16> %tmp1, i32 1)
 	ret void
 }
@@ -22,7 +22,7 @@ define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vst1i32:
 ;CHECK: vst1.32
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %B
 	call void @llvm.arm.neon.vst1.v2i32(i8* %tmp0, <2 x i32> %tmp1, i32 1)
 	ret void
 }
@@ -31,7 +31,7 @@ define void @vst1f(float* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vst1f:
 ;CHECK: vst1.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %B
 	call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1)
 	ret void
 }
@@ -40,11 +40,11 @@ define void @vst1f(float* %A, <2 x float>* %B) nounwind {
 define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vst1f_update:
 ;CHECK: vst1.32 {d16}, [r1]!
-	%A = load float** %ptr
+	%A = load float*, float** %ptr
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %B
 	call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1)
-	%tmp2 = getelementptr float* %A, i32 2
+	%tmp2 = getelementptr float, float* %A, i32 2
 	store float* %tmp2, float** %ptr
 	ret void
 }
@@ -53,7 +53,7 @@ define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vst1i64:
 ;CHECK: vst1.64
 	%tmp0 = bitcast i64* %A to i8*
-	%tmp1 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %B
 	call void @llvm.arm.neon.vst1.v1i64(i8* %tmp0, <1 x i64> %tmp1, i32 1)
 	ret void
 }
@@ -62,7 +62,7 @@ define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vst1Qi8:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst1.8 {d16, d17}, [r0:64]
-	%tmp1 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %B
 	call void @llvm.arm.neon.vst1.v16i8(i8* %A, <16 x i8> %tmp1, i32 8)
 	ret void
 }
@@ -72,7 +72,7 @@ define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst1.16 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %B
 	call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 32)
 	ret void
 }
@@ -81,11 +81,11 @@ define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
 define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
 ;CHECK-LABEL: vst1Qi16_update:
 ;CHECK: vst1.16 {d16, d17}, [r1:64], r2
-	%A = load i16** %ptr
+	%A = load i16*, i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %B
 	call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 8)
-	%tmp2 = getelementptr i16* %A, i32 %inc
+	%tmp2 = getelementptr i16, i16* %A, i32 %inc
 	store i16* %tmp2, i16** %ptr
 	ret void
 }
@@ -94,7 +94,7 @@ define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vst1Qi32:
 ;CHECK: vst1.32
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %B
 	call void @llvm.arm.neon.vst1.v4i32(i8* %tmp0, <4 x i32> %tmp1, i32 1)
 	ret void
 }
@@ -103,7 +103,7 @@ define void @vst1Qf(float* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vst1Qf:
 ;CHECK: vst1.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %B
 	call void @llvm.arm.neon.vst1.v4f32(i8* %tmp0, <4 x float> %tmp1, i32 1)
 	ret void
 }
@@ -112,7 +112,7 @@ define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vst1Qi64:
 ;CHECK: vst1.64
 	%tmp0 = bitcast i64* %A to i8*
-	%tmp1 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %B
 	call void @llvm.arm.neon.vst1.v2i64(i8* %tmp0, <2 x i64> %tmp1, i32 1)
 	ret void
 }
@@ -121,7 +121,7 @@ define void @vst1Qf64(double* %A, <2 x double>* %B) nounwind {
 ;CHECK-LABEL: vst1Qf64:
 ;CHECK: vst1.64
 	%tmp0 = bitcast double* %A to i8*
-	%tmp1 = load <2 x double>* %B
+	%tmp1 = load <2 x double>, <2 x double>* %B
 	call void @llvm.arm.neon.vst1.v2f64(i8* %tmp0, <2 x double> %tmp1, i32 1)
 	ret void
 }
diff --git a/test/CodeGen/ARM/vst2.ll b/test/CodeGen/ARM/vst2.ll
index 2180259d57f7..17c8a4bdad9b 100644
--- a/test/CodeGen/ARM/vst2.ll
+++ b/test/CodeGen/ARM/vst2.ll
@@ -4,7 +4,7 @@ define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vst2i8:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst2.8 {d16, d17}, [r0:64]
-	%tmp1 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
 	call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8)
 	ret void
 }
@@ -13,10 +13,10 @@ define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
 define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
 ;CHECK-LABEL: vst2i8_update:
 ;CHECK: vst2.8 {d16, d17}, [r1], r2
-	%A = load i8** %ptr
-	%tmp1 = load <8 x i8>* %B
+	%A = load i8*, i8** %ptr
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
 	call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 4)
-	%tmp2 = getelementptr i8* %A, i32 %inc
+	%tmp2 = getelementptr i8, i8* %A, i32 %inc
 	store i8* %tmp2, i8** %ptr
 	ret void
 }
@@ -26,7 +26,7 @@ define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst2.16 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %B
 	call void @llvm.arm.neon.vst2.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 32)
 	ret void
 }
@@ -35,7 +35,7 @@ define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vst2i32:
 ;CHECK: vst2.32
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %B
 	call void @llvm.arm.neon.vst2.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
 	ret void
 }
@@ -44,7 +44,7 @@ define void @vst2f(float* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vst2f:
 ;CHECK: vst2.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %B
 	call void @llvm.arm.neon.vst2.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
 	ret void
 }
@@ -54,7 +54,7 @@ define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst1.64 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i64* %A to i8*
-	%tmp1 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %B
 	call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 32)
 	ret void
 }
@@ -63,11 +63,11 @@ define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind {
 define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vst2i64_update:
 ;CHECK: vst1.64 {d16, d17}, [r1:64]!
-	%A = load i64** %ptr
+	%A = load i64*, i64** %ptr
 	%tmp0 = bitcast i64* %A to i8*
-	%tmp1 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %B
 	call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 8)
-	%tmp2 = getelementptr i64* %A, i32 2
+	%tmp2 = getelementptr i64, i64* %A, i32 2
 	store i64* %tmp2, i64** %ptr
 	ret void
 }
@@ -76,7 +76,7 @@ define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vst2Qi8:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64]
-	%tmp1 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %B
 	call void @llvm.arm.neon.vst2.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 8)
 	ret void
 }
@@ -86,7 +86,7 @@ define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %B
 	call void @llvm.arm.neon.vst2.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 16)
 	ret void
 }
@@ -96,7 +96,7 @@ define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256]
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %B
 	call void @llvm.arm.neon.vst2.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 64)
 	ret void
 }
@@ -105,7 +105,7 @@ define void @vst2Qf(float* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vst2Qf:
 ;CHECK: vst2.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %B
 	call void @llvm.arm.neon.vst2.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
 	ret void
 }
@@ -113,18 +113,18 @@ define void @vst2Qf(float* %A, <4 x float>* %B) nounwind {
 define i8* @vst2update(i8* %out, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vst2update:
 ;CHECK: vst2.16 {d16, d17}, [r0]!
-	%tmp1 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %B
 	tail call void @llvm.arm.neon.vst2.v4i16(i8* %out, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 2)
-	%t5 = getelementptr inbounds i8* %out, i32 16
+	%t5 = getelementptr inbounds i8, i8* %out, i32 16
 	ret i8* %t5
 }
 
 define i8* @vst2update2(i8 * %out, <4 x float> * %this) nounwind optsize ssp align 2 {
 ;CHECK-LABEL: vst2update2:
 ;CHECK: vst2.32 {d16, d17, d18, d19}, [r0]!
-  %tmp1 = load <4 x float>* %this
+  %tmp1 = load <4 x float>, <4 x float>* %this
   call void @llvm.arm.neon.vst2.v4f32(i8* %out, <4 x float> %tmp1, <4 x float> %tmp1, i32 4) nounwind
-  %tmp2 = getelementptr inbounds i8* %out, i32  32
+  %tmp2 = getelementptr inbounds i8, i8* %out, i32  32
   ret i8* %tmp2
 }
 
diff --git a/test/CodeGen/ARM/vst3.ll b/test/CodeGen/ARM/vst3.ll
index 5f150edf31da..691ee3bd28f3 100644
--- a/test/CodeGen/ARM/vst3.ll
+++ b/test/CodeGen/ARM/vst3.ll
@@ -5,7 +5,7 @@ define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;This test runs at -O0 so do not check for specific register numbers.
 ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
-	%tmp1 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
 	call void @llvm.arm.neon.vst3.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 32)
 	ret void
 }
@@ -14,7 +14,7 @@ define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vst3i16:
 ;CHECK: vst3.16
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %B
 	call void @llvm.arm.neon.vst3.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
 	ret void
 }
@@ -23,7 +23,7 @@ define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vst3i32:
 ;CHECK: vst3.32
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %B
 	call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
 	ret void
 }
@@ -32,11 +32,11 @@ define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind {
 define void @vst3i32_update(i32** %ptr, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vst3i32_update:
 ;CHECK: vst3.32 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
-	%A = load i32** %ptr
+	%A = load i32*, i32** %ptr
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %B
 	call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
-	%tmp2 = getelementptr i32* %A, i32 6
+	%tmp2 = getelementptr i32, i32* %A, i32 6
 	store i32* %tmp2, i32** %ptr
 	ret void
 }
@@ -45,7 +45,7 @@ define void @vst3f(float* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vst3f:
 ;CHECK: vst3.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %B
 	call void @llvm.arm.neon.vst3.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
 	ret void
 }
@@ -56,7 +56,7 @@ define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind {
 ;This test runs at -O0 so do not check for specific register numbers.
 ;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
 	%tmp0 = bitcast i64* %A to i8*
-	%tmp1 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %B
 	call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 16)
 	ret void
 }
@@ -64,11 +64,11 @@ define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind {
 define void @vst3i64_update(i64** %ptr, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vst3i64_update
 ;CHECK: vst1.64	{d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
-        %A = load i64** %ptr
+        %A = load i64*, i64** %ptr
         %tmp0 = bitcast i64* %A to i8*
-        %tmp1 = load <1 x i64>* %B
+        %tmp1 = load <1 x i64>, <1 x i64>* %B
         call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1)
-        %tmp2 = getelementptr i64* %A, i32 3
+        %tmp2 = getelementptr i64, i64* %A, i32 3
         store i64* %tmp2, i64** %ptr
         ret void
 }
@@ -79,7 +79,7 @@ define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind {
 ;This test runs at -O0 so do not check for specific register numbers.
 ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]!
 ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
-	%tmp1 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %B
 	call void @llvm.arm.neon.vst3.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 32)
 	ret void
 }
@@ -89,7 +89,7 @@ define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind {
 ;CHECK: vst3.16
 ;CHECK: vst3.16
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %B
 	call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
 	ret void
 }
@@ -99,11 +99,11 @@ define void @vst3Qi16_update(i16** %ptr, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vst3Qi16_update:
 ;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
 ;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
-	%A = load i16** %ptr
+	%A = load i16*, i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %B
 	call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
-	%tmp2 = getelementptr i16* %A, i32 24
+	%tmp2 = getelementptr i16, i16* %A, i32 24
 	store i16* %tmp2, i16** %ptr
 	ret void
 }
@@ -113,7 +113,7 @@ define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind {
 ;CHECK: vst3.32
 ;CHECK: vst3.32
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %B
 	call void @llvm.arm.neon.vst3.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1)
 	ret void
 }
@@ -123,7 +123,7 @@ define void @vst3Qf(float* %A, <4 x float>* %B) nounwind {
 ;CHECK: vst3.32
 ;CHECK: vst3.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %B
 	call void @llvm.arm.neon.vst3.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
 	ret void
 }
diff --git a/test/CodeGen/ARM/vst4.ll b/test/CodeGen/ARM/vst4.ll
index 44c76b5ed189..c343c6c86959 100644
--- a/test/CodeGen/ARM/vst4.ll
+++ b/test/CodeGen/ARM/vst4.ll
@@ -4,7 +4,7 @@ define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vst4i8:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64]
-	%tmp1 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
 	call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8)
 	ret void
 }
@@ -13,10 +13,10 @@ define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
 define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
 ;CHECK-LABEL: vst4i8_update:
 ;CHECK: vst4.8 {d16, d17, d18, d19}, [r1:128], r2
-	%A = load i8** %ptr
-	%tmp1 = load <8 x i8>* %B
+	%A = load i8*, i8** %ptr
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
 	call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 16)
-	%tmp2 = getelementptr i8* %A, i32 %inc
+	%tmp2 = getelementptr i8, i8* %A, i32 %inc
 	store i8* %tmp2, i8** %ptr
 	ret void
 }
@@ -26,7 +26,7 @@ define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %B
 	call void @llvm.arm.neon.vst4.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 16)
 	ret void
 }
@@ -36,7 +36,7 @@ define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst4.32 {d16, d17, d18, d19}, [r0:256]
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %B
 	call void @llvm.arm.neon.vst4.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 32)
 	ret void
 }
@@ -45,7 +45,7 @@ define void @vst4f(float* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vst4f:
 ;CHECK: vst4.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %B
 	call void @llvm.arm.neon.vst4.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
 	ret void
 }
@@ -55,7 +55,7 @@ define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst1.64 {d16, d17, d18, d19}, [r0:256]
 	%tmp0 = bitcast i64* %A to i8*
-	%tmp1 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %B
 	call void @llvm.arm.neon.vst4.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 64)
 	ret void
 }
@@ -63,11 +63,11 @@ define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind {
 define void @vst4i64_update(i64** %ptr, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vst4i64_update:
 ;CHECK: vst1.64	{d16, d17, d18, d19}, [r1]!
-        %A = load i64** %ptr
+        %A = load i64*, i64** %ptr
         %tmp0 = bitcast i64* %A to i8*
-        %tmp1 = load <1 x i64>* %B
+        %tmp1 = load <1 x i64>, <1 x i64>* %B
         call void @llvm.arm.neon.vst4.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1)
-        %tmp2 = getelementptr i64* %A, i32 4
+        %tmp2 = getelementptr i64, i64* %A, i32 4
         store i64* %tmp2, i64** %ptr
         ret void
 }
@@ -77,7 +77,7 @@ define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]!
 ;CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]
-	%tmp1 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %B
 	call void @llvm.arm.neon.vst4.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 64)
 	ret void
 }
@@ -88,7 +88,7 @@ define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind {
 ;CHECK: vst4.16 {d16, d18, d20, d22}, [r0]!
 ;CHECK: vst4.16 {d17, d19, d21, d23}, [r0]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %B
 	call void @llvm.arm.neon.vst4.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
 	ret void
 }
@@ -98,7 +98,7 @@ define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind {
 ;CHECK: vst4.32
 ;CHECK: vst4.32
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %B
 	call void @llvm.arm.neon.vst4.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1)
 	ret void
 }
@@ -108,7 +108,7 @@ define void @vst4Qf(float* %A, <4 x float>* %B) nounwind {
 ;CHECK: vst4.32
 ;CHECK: vst4.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %B
 	call void @llvm.arm.neon.vst4.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
 	ret void
 }
@@ -118,11 +118,11 @@ define void @vst4Qf_update(float** %ptr, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vst4Qf_update:
 ;CHECK: vst4.32 {d16, d18, d20, d22}, [r1]!
 ;CHECK: vst4.32 {d17, d19, d21, d23}, [r1]!
-	%A = load float** %ptr
+	%A = load float*, float** %ptr
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %B
 	call void @llvm.arm.neon.vst4.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
-	%tmp2 = getelementptr float* %A, i32 16
+	%tmp2 = getelementptr float, float* %A, i32 16
 	store float* %tmp2, float** %ptr
 	ret void
 }
diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll
index 7dd6e7b439ea..a4575417bce5 100644
--- a/test/CodeGen/ARM/vstlane.ll
+++ b/test/CodeGen/ARM/vstlane.ll
@@ -4,7 +4,7 @@ define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vst1lanei8:
 ;Check the (default) alignment.
 ;CHECK: vst1.8 {d16[3]}, [r0]
-	%tmp1 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
         %tmp2 = extractelement <8 x i8> %tmp1, i32 3
         store i8 %tmp2, i8* %A, align 8
 	ret void
@@ -14,11 +14,11 @@ define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
 define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vst1lanei8_update:
 ;CHECK: vst1.8 {d16[3]}, [{{r[0-9]}}]!
-	%A = load i8** %ptr
-	%tmp1 = load <8 x i8>* %B
+	%A = load i8*, i8** %ptr
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
 	%tmp2 = extractelement <8 x i8> %tmp1, i32 3
 	store i8 %tmp2, i8* %A, align 8
-	%tmp3 = getelementptr i8* %A, i32 1
+	%tmp3 = getelementptr i8, i8* %A, i32 1
 	store i8* %tmp3, i8** %ptr
 	ret void
 }
@@ -27,7 +27,7 @@ define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vst1lanei16:
 ;Check the alignment value.  Max for this instruction is 16 bits:
 ;CHECK: vst1.16 {d16[2]}, [r0:16]
-	%tmp1 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %B
         %tmp2 = extractelement <4 x i16> %tmp1, i32 2
         store i16 %tmp2, i16* %A, align 8
 	ret void
@@ -37,7 +37,7 @@ define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vst1lanei32:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vst1.32 {d16[1]}, [r0:32]
-	%tmp1 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %B
         %tmp2 = extractelement <2 x i32> %tmp1, i32 1
         store i32 %tmp2, i32* %A, align 8
 	ret void
@@ -46,7 +46,7 @@ define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind {
 define void @vst1lanef(float* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vst1lanef:
 ;CHECK: vst1.32 {d16[1]}, [r0:32]
-	%tmp1 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %B
         %tmp2 = extractelement <2 x float> %tmp1, i32 1
         store float %tmp2, float* %A
 	ret void
@@ -56,7 +56,7 @@ define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vst1laneQi8:
 ; // Can use scalar load. No need to use vectors.
 ; // CHE-CK: vst1.8 {d17[1]}, [r0]
-	%tmp1 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %B
         %tmp2 = extractelement <16 x i8> %tmp1, i32 9
         store i8 %tmp2, i8* %A, align 8
 	ret void
@@ -65,7 +65,7 @@ define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
 define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vst1laneQi16:
 ;CHECK: vst1.16 {d17[1]}, [r0:16]
-	%tmp1 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %B
         %tmp2 = extractelement <8 x i16> %tmp1, i32 5
         store i16 %tmp2, i16* %A, align 8
 	ret void
@@ -75,7 +75,7 @@ define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vst1laneQi32:
 ; // Can use scalar load. No need to use vectors.
 ; // CHE-CK: vst1.32 {d17[1]}, [r0:32]
-	%tmp1 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %B
         %tmp2 = extractelement <4 x i32> %tmp1, i32 3
         store i32 %tmp2, i32* %A, align 8
 	ret void
@@ -86,11 +86,11 @@ define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vst1laneQi32_update:
 ; // Can use scalar load. No need to use vectors.
 ; // CHE-CK: vst1.32 {d17[1]}, [r1:32]!
-	%A = load i32** %ptr
-	%tmp1 = load <4 x i32>* %B
+	%A = load i32*, i32** %ptr
+	%tmp1 = load <4 x i32>, <4 x i32>* %B
 	%tmp2 = extractelement <4 x i32> %tmp1, i32 3
 	store i32 %tmp2, i32* %A, align 8
-	%tmp3 = getelementptr i32* %A, i32 1
+	%tmp3 = getelementptr i32, i32* %A, i32 1
 	store i32* %tmp3, i32** %ptr
 	ret void
 }
@@ -99,7 +99,7 @@ define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vst1laneQf:
 ; // Can use scalar load. No need to use vectors.
 ; // CHE-CK: vst1.32 {d17[1]}, [r0]
-	%tmp1 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %B
         %tmp2 = extractelement <4 x float> %tmp1, i32 3
         store float %tmp2, float* %A
 	ret void
@@ -109,7 +109,7 @@ define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vst2lanei8:
 ;Check the alignment value.  Max for this instruction is 16 bits:
 ;CHECK: vst2.8 {d16[1], d17[1]}, [r0:16]
-	%tmp1 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
 	call void @llvm.arm.neon.vst2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
 	ret void
 }
@@ -119,7 +119,7 @@ define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vst2.16 {d16[1], d17[1]}, [r0:32]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %B
 	call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
 	ret void
 }
@@ -128,11 +128,11 @@ define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
 define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind {
 ;CHECK-LABEL: vst2lanei16_update:
 ;CHECK: vst2.16 {d16[1], d17[1]}, [r1], r2
-	%A = load i16** %ptr
+	%A = load i16*, i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %B
 	call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 2)
-	%tmp2 = getelementptr i16* %A, i32 %inc
+	%tmp2 = getelementptr i16, i16* %A, i32 %inc
 	store i16* %tmp2, i16** %ptr
 	ret void
 }
@@ -141,7 +141,7 @@ define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vst2lanei32:
 ;CHECK: vst2.32
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %B
 	call void @llvm.arm.neon.vst2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
 	ret void
 }
@@ -150,7 +150,7 @@ define void @vst2lanef(float* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vst2lanef:
 ;CHECK: vst2.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %B
 	call void @llvm.arm.neon.vst2lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
 	ret void
 }
@@ -160,7 +160,7 @@ define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 ;Check the (default) alignment.
 ;CHECK: vst2.16 {d17[1], d19[1]}, [r0]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %B
 	call void @llvm.arm.neon.vst2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1)
 	ret void
 }
@@ -170,7 +170,7 @@ define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vst2.32 {d17[0], d19[0]}, [r0:64]
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %B
 	call void @llvm.arm.neon.vst2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16)
 	ret void
 }
@@ -179,7 +179,7 @@ define void @vst2laneQf(float* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vst2laneQf:
 ;CHECK: vst2.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %B
 	call void @llvm.arm.neon.vst2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 3, i32 1)
 	ret void
 }
@@ -196,7 +196,7 @@ declare void @llvm.arm.neon.vst2lane.v4f32(i8*, <4 x float>, <4 x float>, i32, i
 define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vst3lanei8:
 ;CHECK: vst3.8
-	%tmp1 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
 	call void @llvm.arm.neon.vst3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
 	ret void
 }
@@ -206,7 +206,7 @@ define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind {
 ;Check the (default) alignment value.  VST3 does not support alignment.
 ;CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %B
 	call void @llvm.arm.neon.vst3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
 	ret void
 }
@@ -215,7 +215,7 @@ define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vst3lanei32:
 ;CHECK: vst3.32
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %B
 	call void @llvm.arm.neon.vst3lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
 	ret void
 }
@@ -224,7 +224,7 @@ define void @vst3lanef(float* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vst3lanef:
 ;CHECK: vst3.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %B
 	call void @llvm.arm.neon.vst3lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
 	ret void
 }
@@ -234,7 +234,7 @@ define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 ;Check the (default) alignment value.  VST3 does not support alignment.
 ;CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %B
 	call void @llvm.arm.neon.vst3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6, i32 8)
 	ret void
 }
@@ -243,7 +243,7 @@ define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vst3laneQi32:
 ;CHECK: vst3.32
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %B
 	call void @llvm.arm.neon.vst3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1)
 	ret void
 }
@@ -252,11 +252,11 @@ define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vst3laneQi32_update:
 ;CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r1]!
-	%A = load i32** %ptr
+	%A = load i32*, i32** %ptr
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %B
 	call void @llvm.arm.neon.vst3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1)
-	%tmp2 = getelementptr i32* %A, i32 3
+	%tmp2 = getelementptr i32, i32* %A, i32 3
 	store i32* %tmp2, i32** %ptr
 	ret void
 }
@@ -265,7 +265,7 @@ define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vst3laneQf:
 ;CHECK: vst3.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %B
 	call void @llvm.arm.neon.vst3lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
 	ret void
 }
@@ -284,7 +284,7 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vst4lanei8:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]
-	%tmp1 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
 	call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
 	ret void
 }
@@ -293,10 +293,10 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
 define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vst4lanei8_update:
 ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!
-	%A = load i8** %ptr
-	%tmp1 = load <8 x i8>* %B
+	%A = load i8*, i8** %ptr
+	%tmp1 = load <8 x i8>, <8 x i8>* %B
 	call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
-	%tmp2 = getelementptr i8* %A, i32 4
+	%tmp2 = getelementptr i8, i8* %A, i32 4
 	store i8* %tmp2, i8** %ptr
 	ret void
 }
@@ -305,7 +305,7 @@ define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vst4lanei16:
 ;CHECK: vst4.16
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %B
 	call void @llvm.arm.neon.vst4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 1)
 	ret void
 }
@@ -315,7 +315,7 @@ define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %B
 	call void @llvm.arm.neon.vst4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 16)
 	ret void
 }
@@ -324,7 +324,7 @@ define void @vst4lanef(float* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vst4lanef:
 ;CHECK: vst4.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %B
 	call void @llvm.arm.neon.vst4lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
 	ret void
 }
@@ -334,7 +334,7 @@ define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %B
 	call void @llvm.arm.neon.vst4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7, i32 16)
 	ret void
 }
@@ -344,7 +344,7 @@ define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 ;Check the (default) alignment.
 ;CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %B
 	call void @llvm.arm.neon.vst4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1)
 	ret void
 }
@@ -353,7 +353,7 @@ define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vst4laneQf:
 ;CHECK: vst4.32
 	%tmp0 = bitcast float* %A to i8*
-	%tmp1 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %B
 	call void @llvm.arm.neon.vst4lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
 	ret void
 }
diff --git a/test/CodeGen/ARM/vsub.ll b/test/CodeGen/ARM/vsub.ll
index d1a094b92755..75fb7d493a59 100644
--- a/test/CodeGen/ARM/vsub.ll
+++ b/test/CodeGen/ARM/vsub.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsubi8:
 ;CHECK: vsub.i8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = sub <8 x i8> %tmp1, %tmp2
 	ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsubi16:
 ;CHECK: vsub.i16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = sub <4 x i16> %tmp1, %tmp2
 	ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsubi32:
 ;CHECK: vsub.i32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = sub <2 x i32> %tmp1, %tmp2
 	ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 ;CHECK-LABEL: vsubi64:
 ;CHECK: vsub.i64
-	%tmp1 = load <1 x i64>* %A
-	%tmp2 = load <1 x i64>* %B
+	%tmp1 = load <1 x i64>, <1 x i64>* %A
+	%tmp2 = load <1 x i64>, <1 x i64>* %B
 	%tmp3 = sub <1 x i64> %tmp1, %tmp2
 	ret <1 x i64> %tmp3
 }
@@ -39,8 +39,8 @@ define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vsubf32:
 ;CHECK: vsub.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = fsub <2 x float> %tmp1, %tmp2
 	ret <2 x float> %tmp3
 }
@@ -48,8 +48,8 @@ define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsubQi8:
 ;CHECK: vsub.i8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = sub <16 x i8> %tmp1, %tmp2
 	ret <16 x i8> %tmp3
 }
@@ -57,8 +57,8 @@ define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsubQi16:
 ;CHECK: vsub.i16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = sub <8 x i16> %tmp1, %tmp2
 	ret <8 x i16> %tmp3
 }
@@ -66,8 +66,8 @@ define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsubQi32:
 ;CHECK: vsub.i32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = sub <4 x i32> %tmp1, %tmp2
 	ret <4 x i32> %tmp3
 }
@@ -75,8 +75,8 @@ define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vsubQi64:
 ;CHECK: vsub.i64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = sub <2 x i64> %tmp1, %tmp2
 	ret <2 x i64> %tmp3
 }
@@ -84,8 +84,8 @@ define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vsubQf32:
 ;CHECK: vsub.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = fsub <4 x float> %tmp1, %tmp2
 	ret <4 x float> %tmp3
 }
@@ -120,8 +120,8 @@ define <2 x i32> @vsubhni64_natural(<2 x i64> %A, <2 x i64> %B) nounwind {
 define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vrsubhni16:
 ;CHECK: vrsubhn.i16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -129,8 +129,8 @@ define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vrsubhni32:
 ;CHECK: vrsubhn.i32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
 	ret <4 x i16> %tmp3
 }
@@ -138,8 +138,8 @@ define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i32> @vrsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: vrsubhni64:
 ;CHECK: vrsubhn.i64
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i64>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i64>, <2 x i64>* %B
 	%tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i32> %tmp3
 }
@@ -151,8 +151,8 @@ declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind re
 define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsubls8:
 ;CHECK: vsubl.s8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
 	%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
 	%tmp5 = sub <8 x i16> %tmp3, %tmp4
@@ -162,8 +162,8 @@ define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsubls16:
 ;CHECK: vsubl.s16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
 	%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
 	%tmp5 = sub <4 x i32> %tmp3, %tmp4
@@ -173,8 +173,8 @@ define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsubls32:
 ;CHECK: vsubl.s32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
 	%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
 	%tmp5 = sub <2 x i64> %tmp3, %tmp4
@@ -184,8 +184,8 @@ define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsublu8:
 ;CHECK: vsubl.u8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
 	%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
 	%tmp5 = sub <8 x i16> %tmp3, %tmp4
@@ -195,8 +195,8 @@ define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsublu16:
 ;CHECK: vsubl.u16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
 	%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
 	%tmp5 = sub <4 x i32> %tmp3, %tmp4
@@ -206,8 +206,8 @@ define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsublu32:
 ;CHECK: vsubl.u32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
 	%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
 	%tmp5 = sub <2 x i64> %tmp3, %tmp4
@@ -217,8 +217,8 @@ define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsubws8:
 ;CHECK: vsubw.s8
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
 	%tmp4 = sub <8 x i16> %tmp1, %tmp3
 	ret <8 x i16> %tmp4
@@ -227,8 +227,8 @@ define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsubws16:
 ;CHECK: vsubw.s16
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
 	%tmp4 = sub <4 x i32> %tmp1, %tmp3
 	ret <4 x i32> %tmp4
@@ -237,8 +237,8 @@ define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsubws32:
 ;CHECK: vsubw.s32
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
 	%tmp4 = sub <2 x i64> %tmp1, %tmp3
 	ret <2 x i64> %tmp4
@@ -247,8 +247,8 @@ define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vsubwu8:
 ;CHECK: vsubw.u8
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
 	%tmp4 = sub <8 x i16> %tmp1, %tmp3
 	ret <8 x i16> %tmp4
@@ -257,8 +257,8 @@ define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vsubwu16:
 ;CHECK: vsubw.u16
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
 	%tmp4 = sub <4 x i32> %tmp1, %tmp3
 	ret <4 x i32> %tmp4
@@ -267,8 +267,8 @@ define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vsubwu32:
 ;CHECK: vsubw.u32
-	%tmp1 = load <2 x i64>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
 	%tmp4 = sub <2 x i64> %tmp1, %tmp3
 	ret <2 x i64> %tmp4
diff --git a/test/CodeGen/ARM/vtbl.ll b/test/CodeGen/ARM/vtbl.ll
index 32258a30da96..e4dd572a41b4 100644
--- a/test/CodeGen/ARM/vtbl.ll
+++ b/test/CodeGen/ARM/vtbl.ll
@@ -7,8 +7,8 @@
 define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vtbl1:
 ;CHECK: vtbl.8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = call <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8> %tmp1, <8 x i8> %tmp2)
 	ret <8 x i8> %tmp3
 }
@@ -16,8 +16,8 @@ define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind {
 ;CHECK-LABEL: vtbl2:
 ;CHECK: vtbl.8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load %struct.__neon_int8x8x2_t* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load %struct.__neon_int8x8x2_t, %struct.__neon_int8x8x2_t* %B
         %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1
 	%tmp5 = call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4)
@@ -27,8 +27,8 @@ define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind {
 define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind {
 ;CHECK-LABEL: vtbl3:
 ;CHECK: vtbl.8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load %struct.__neon_int8x8x3_t* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load %struct.__neon_int8x8x3_t, %struct.__neon_int8x8x3_t* %B
         %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1
         %tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2
@@ -39,8 +39,8 @@ define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind {
 define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind {
 ;CHECK-LABEL: vtbl4:
 ;CHECK: vtbl.8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load %struct.__neon_int8x8x4_t* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B
         %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
         %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
@@ -52,9 +52,9 @@ define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind {
 define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ;CHECK-LABEL: vtbx1:
 ;CHECK: vtbx.8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
-	%tmp3 = load <8 x i8>* %C
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
+	%tmp3 = load <8 x i8>, <8 x i8>* %C
 	%tmp4 = call <8 x i8> @llvm.arm.neon.vtbx1(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
 	ret <8 x i8> %tmp4
 }
@@ -62,11 +62,11 @@ define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C) nounwind {
 ;CHECK-LABEL: vtbx2:
 ;CHECK: vtbx.8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load %struct.__neon_int8x8x2_t* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load %struct.__neon_int8x8x2_t, %struct.__neon_int8x8x2_t* %B
         %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1
-	%tmp5 = load <8 x i8>* %C
+	%tmp5 = load <8 x i8>, <8 x i8>* %C
 	%tmp6 = call <8 x i8> @llvm.arm.neon.vtbx2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5)
 	ret <8 x i8> %tmp6
 }
@@ -74,12 +74,12 @@ define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C
 define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C) nounwind {
 ;CHECK-LABEL: vtbx3:
 ;CHECK: vtbx.8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load %struct.__neon_int8x8x3_t* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load %struct.__neon_int8x8x3_t, %struct.__neon_int8x8x3_t* %B
         %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1
         %tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2
-	%tmp6 = load <8 x i8>* %C
+	%tmp6 = load <8 x i8>, <8 x i8>* %C
 	%tmp7 = call <8 x i8> @llvm.arm.neon.vtbx3(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6)
 	ret <8 x i8> %tmp7
 }
@@ -87,13 +87,13 @@ define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C
 define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
 ;CHECK-LABEL: vtbx4:
 ;CHECK: vtbx.8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load %struct.__neon_int8x8x4_t* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B
         %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
         %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
         %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
-	%tmp7 = load <8 x i8>* %C
+	%tmp7 = load <8 x i8>, <8 x i8>* %C
 	%tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
 	ret <8 x i8> %tmp8
 }
diff --git a/test/CodeGen/ARM/vtrn.ll b/test/CodeGen/ARM/vtrn.ll
index cdae7f8ec370..caa5becac1d9 100644
--- a/test/CodeGen/ARM/vtrn.ll
+++ b/test/CodeGen/ARM/vtrn.ll
@@ -4,8 +4,8 @@ define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vtrni8:
 ;CHECK: vtrn.8
 ;CHECK-NEXT: vadd.i8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
 	%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
         %tmp5 = add <8 x i8> %tmp3, %tmp4
@@ -16,8 +16,8 @@ define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vtrni16:
 ;CHECK: vtrn.16
 ;CHECK-NEXT: vadd.i16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
 	%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
         %tmp5 = add <4 x i16> %tmp3, %tmp4
@@ -28,8 +28,8 @@ define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: vtrni32:
 ;CHECK: vtrn.32
 ;CHECK-NEXT: vadd.i32
-	%tmp1 = load <2 x i32>* %A
-	%tmp2 = load <2 x i32>* %B
+	%tmp1 = load <2 x i32>, <2 x i32>* %A
+	%tmp2 = load <2 x i32>, <2 x i32>* %B
 	%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>
 	%tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>
         %tmp5 = add <2 x i32> %tmp3, %tmp4
@@ -40,8 +40,8 @@ define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK-LABEL: vtrnf:
 ;CHECK: vtrn.32
 ;CHECK-NEXT: vadd.f32
-	%tmp1 = load <2 x float>* %A
-	%tmp2 = load <2 x float>* %B
+	%tmp1 = load <2 x float>, <2 x float>* %A
+	%tmp2 = load <2 x float>, <2 x float>* %B
 	%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2>
 	%tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3>
         %tmp5 = fadd <2 x float> %tmp3, %tmp4
@@ -52,8 +52,8 @@ define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vtrnQi8:
 ;CHECK: vtrn.8
 ;CHECK-NEXT: vadd.i8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
 	%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
         %tmp5 = add <16 x i8> %tmp3, %tmp4
@@ -64,8 +64,8 @@ define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vtrnQi16:
 ;CHECK: vtrn.16
 ;CHECK-NEXT: vadd.i16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
 	%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
         %tmp5 = add <8 x i16> %tmp3, %tmp4
@@ -76,8 +76,8 @@ define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vtrnQi32:
 ;CHECK: vtrn.32
 ;CHECK-NEXT: vadd.i32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
 	%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
         %tmp5 = add <4 x i32> %tmp3, %tmp4
@@ -88,8 +88,8 @@ define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vtrnQf:
 ;CHECK: vtrn.32
 ;CHECK-NEXT: vadd.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
 	%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
         %tmp5 = fadd <4 x float> %tmp3, %tmp4
@@ -102,8 +102,8 @@ define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vtrni8_undef:
 ;CHECK: vtrn.8
 ;CHECK-NEXT: vadd.i8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14>
 	%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
         %tmp5 = add <8 x i8> %tmp3, %tmp4
@@ -114,8 +114,8 @@ define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vtrnQi16_undef:
 ;CHECK: vtrn.16
 ;CHECK-NEXT: vadd.i16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14>
 	%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
         %tmp5 = add <8 x i16> %tmp3, %tmp4
diff --git a/test/CodeGen/ARM/vuzp.ll b/test/CodeGen/ARM/vuzp.ll
index 832be6c3daf1..7a7306a26593 100644
--- a/test/CodeGen/ARM/vuzp.ll
+++ b/test/CodeGen/ARM/vuzp.ll
@@ -4,8 +4,8 @@ define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vuzpi8:
 ;CHECK: vuzp.8
 ;CHECK-NEXT: vadd.i8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
 	%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
         %tmp5 = add <8 x i8> %tmp3, %tmp4
@@ -16,8 +16,8 @@ define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vuzpi16:
 ;CHECK: vuzp.16
 ;CHECK-NEXT: vadd.i16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
 	%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
         %tmp5 = add <4 x i16> %tmp3, %tmp4
@@ -30,8 +30,8 @@ define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vuzpQi8:
 ;CHECK: vuzp.8
 ;CHECK-NEXT: vadd.i8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
 	%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
         %tmp5 = add <16 x i8> %tmp3, %tmp4
@@ -42,8 +42,8 @@ define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vuzpQi16:
 ;CHECK: vuzp.16
 ;CHECK-NEXT: vadd.i16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
 	%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
         %tmp5 = add <8 x i16> %tmp3, %tmp4
@@ -54,8 +54,8 @@ define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vuzpQi32:
 ;CHECK: vuzp.32
 ;CHECK-NEXT: vadd.i32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
 	%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
         %tmp5 = add <4 x i32> %tmp3, %tmp4
@@ -66,8 +66,8 @@ define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vuzpQf:
 ;CHECK: vuzp.32
 ;CHECK-NEXT: vadd.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
 	%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
         %tmp5 = fadd <4 x float> %tmp3, %tmp4
@@ -80,8 +80,8 @@ define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vuzpi8_undef:
 ;CHECK: vuzp.8
 ;CHECK-NEXT: vadd.i8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14>
 	%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15>
         %tmp5 = add <8 x i8> %tmp3, %tmp4
@@ -92,8 +92,8 @@ define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vuzpQi16_undef:
 ;CHECK: vuzp.16
 ;CHECK-NEXT: vadd.i16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14>
 	%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>
         %tmp5 = add <8 x i16> %tmp3, %tmp4
diff --git a/test/CodeGen/ARM/vzip.ll b/test/CodeGen/ARM/vzip.ll
index f74dc62599cf..a1b5b4549ac2 100644
--- a/test/CodeGen/ARM/vzip.ll
+++ b/test/CodeGen/ARM/vzip.ll
@@ -4,8 +4,8 @@ define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vzipi8:
 ;CHECK: vzip.8
 ;CHECK-NEXT: vadd.i8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
 	%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
         %tmp5 = add <8 x i8> %tmp3, %tmp4
@@ -16,8 +16,8 @@ define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: vzipi16:
 ;CHECK: vzip.16
 ;CHECK-NEXT: vadd.i16
-	%tmp1 = load <4 x i16>* %A
-	%tmp2 = load <4 x i16>* %B
+	%tmp1 = load <4 x i16>, <4 x i16>* %A
+	%tmp2 = load <4 x i16>, <4 x i16>* %B
 	%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
 	%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
         %tmp5 = add <4 x i16> %tmp3, %tmp4
@@ -30,8 +30,8 @@ define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vzipQi8:
 ;CHECK: vzip.8
 ;CHECK-NEXT: vadd.i8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
 	%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
         %tmp5 = add <16 x i8> %tmp3, %tmp4
@@ -42,8 +42,8 @@ define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: vzipQi16:
 ;CHECK: vzip.16
 ;CHECK-NEXT: vadd.i16
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
 	%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
         %tmp5 = add <8 x i16> %tmp3, %tmp4
@@ -54,8 +54,8 @@ define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: vzipQi32:
 ;CHECK: vzip.32
 ;CHECK-NEXT: vadd.i32
-	%tmp1 = load <4 x i32>* %A
-	%tmp2 = load <4 x i32>* %B
+	%tmp1 = load <4 x i32>, <4 x i32>* %A
+	%tmp2 = load <4 x i32>, <4 x i32>* %B
 	%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
 	%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
         %tmp5 = add <4 x i32> %tmp3, %tmp4
@@ -66,8 +66,8 @@ define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK-LABEL: vzipQf:
 ;CHECK: vzip.32
 ;CHECK-NEXT: vadd.f32
-	%tmp1 = load <4 x float>* %A
-	%tmp2 = load <4 x float>* %B
+	%tmp1 = load <4 x float>, <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %B
 	%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
 	%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
         %tmp5 = fadd <4 x float> %tmp3, %tmp4
@@ -80,8 +80,8 @@ define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vzipi8_undef:
 ;CHECK: vzip.8
 ;CHECK-NEXT: vadd.i8
-	%tmp1 = load <8 x i8>* %A
-	%tmp2 = load <8 x i8>* %B
+	%tmp1 = load <8 x i8>, <8 x i8>* %A
+	%tmp2 = load <8 x i8>, <8 x i8>* %B
 	%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11>
 	%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15>
         %tmp5 = add <8 x i8> %tmp3, %tmp4
@@ -92,8 +92,8 @@ define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: vzipQi8_undef:
 ;CHECK: vzip.8
 ;CHECK-NEXT: vadd.i8
-	%tmp1 = load <16 x i8>* %A
-	%tmp2 = load <16 x i8>* %B
+	%tmp1 = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
 	%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
 	%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31>
         %tmp5 = add <16 x i8> %tmp3, %tmp4
diff --git a/test/CodeGen/ARM/warn-stack.ll b/test/CodeGen/ARM/warn-stack.ll
index 90a3e1f798ed..474dc1dfb447 100644
--- a/test/CodeGen/ARM/warn-stack.ll
+++ b/test/CodeGen/ARM/warn-stack.ll
@@ -7,7 +7,7 @@
 define void @nowarn() nounwind ssp {
 entry:
   %buffer = alloca [12 x i8], align 1
-  %arraydecay = getelementptr inbounds [12 x i8]* %buffer, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [12 x i8], [12 x i8]* %buffer, i64 0, i64 0
   call void @doit(i8* %arraydecay) nounwind
   ret void
 }
@@ -16,7 +16,7 @@ entry:
 define void @warn() nounwind ssp {
 entry:
   %buffer = alloca [80 x i8], align 1
-  %arraydecay = getelementptr inbounds [80 x i8]* %buffer, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [80 x i8], [80 x i8]* %buffer, i64 0, i64 0
   call void @doit(i8* %arraydecay) nounwind
   ret void
 }
diff --git a/test/CodeGen/ARM/weak2.ll b/test/CodeGen/ARM/weak2.ll
index 82ab90efb118..a2911d780fef 100644
--- a/test/CodeGen/ARM/weak2.ll
+++ b/test/CodeGen/ARM/weak2.ll
@@ -8,7 +8,7 @@ entry:
 	br i1 %tmp5, label %UnifiedReturnBlock, label %cond_true8
 
 cond_true8:		; preds = %entry
-	%tmp10 = tail call i32 (...)* %t.0( )		; <i32> [#uses=1]
+	%tmp10 = tail call i32 (...) %t.0( )		; <i32> [#uses=1]
 	ret i32 %tmp10
 
 UnifiedReturnBlock:		; preds = %entry
diff --git a/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll b/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll
index 7ecd25283108..4b274d2aedc2 100644
--- a/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll
+++ b/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll
@@ -7,11 +7,11 @@ declare i8* @llvm.returnaddress(i32)
 
 define i32* @wrong-t2stmia-size-reduction(i32* %addr, i32 %val0) minsize {
   store i32 %val0, i32* %addr
-  %addr1 = getelementptr i32* %addr, i32 1
+  %addr1 = getelementptr i32, i32* %addr, i32 1
   %lr = call i8* @llvm.returnaddress(i32 0)
   %lr32 = ptrtoint i8* %lr to i32
   store i32 %lr32, i32* %addr1
-  %addr2 = getelementptr i32* %addr1, i32 1
+  %addr2 = getelementptr i32, i32* %addr1, i32 1
   ret i32* %addr2
 }
 
diff --git a/test/CodeGen/ARM/zextload_demandedbits.ll b/test/CodeGen/ARM/zextload_demandedbits.ll
index 6b6ce97ed9e2..ba7393c2dc20 100644
--- a/test/CodeGen/ARM/zextload_demandedbits.ll
+++ b/test/CodeGen/ARM/zextload_demandedbits.ll
@@ -14,8 +14,8 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-
 ; CHECK: pop
 define void @quux(%struct.eggs* %arg) {
 bb:
-  %tmp1 = getelementptr inbounds %struct.eggs* %arg, i32 0, i32 1
-  %0 = load i16* %tmp1, align 2
+  %tmp1 = getelementptr inbounds %struct.eggs, %struct.eggs* %arg, i32 0, i32 1
+  %0 = load i16, i16* %tmp1, align 2
   %tobool = icmp eq i16 %0, 0
   br i1 %tobool, label %bb16, label %bb3
 
@@ -24,7 +24,7 @@ bb3:                                              ; preds = %bb
   %tmp5 = ptrtoint i16* %tmp1 to i32
   %tmp6 = shl i32 %tmp5, 20
   %tmp7 = ashr exact i32 %tmp6, 20
-  %tmp14 = getelementptr inbounds %struct.barney* undef, i32 %tmp7
+  %tmp14 = getelementptr inbounds %struct.barney, %struct.barney* undef, i32 %tmp7
   %tmp15 = tail call i32 @widget(%struct.barney* %tmp14, i8* %tmp4, i32 %tmp7)
   br label %bb16
 
diff --git a/test/CodeGen/BPF/alu8.ll b/test/CodeGen/BPF/alu8.ll
new file mode 100644
index 000000000000..0233225f81b5
--- /dev/null
+++ b/test/CodeGen/BPF/alu8.ll
@@ -0,0 +1,46 @@
+; RUN: llc -march=bpf -show-mc-encoding < %s | FileCheck %s
+; test little endian only for now
+
+define i8 @mov(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: mov:
+; CHECK: mov r0, r2 # encoding: [0xbf,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: ret # encoding: [0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+  ret i8 %b
+}
+
+define i8 @add(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: add:
+; CHECK: add r1, r2 # encoding: [0x0f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: mov r0, r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00]
+  %1 = add i8 %a, %b
+  ret i8 %1
+}
+
+define i8 @and(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: and:
+; CHECK: and r1, r2 # encoding: [0x5f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+  %1 = and i8 %a, %b
+  ret i8 %1
+}
+
+define i8 @bis(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: bis:
+; CHECK: or r1, r2 # encoding: [0x4f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+  %1 = or i8 %a, %b
+  ret i8 %1
+}
+
+define i8 @xorand(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: xorand:
+; CHECK: xori r2, -1 # encoding: [0xa7,0x02,0x00,0x00,0xff,0xff,0xff,0xff]
+  %1 = xor i8 %b, -1
+  %2 = and i8 %a, %1
+  ret i8 %2
+}
+
+define i8 @xor(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: xor:
+; CHECK: xor r1, r2 # encoding: [0xaf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+  %1 = xor i8 %a, %b
+  ret i8 %1
+}
diff --git a/test/CodeGen/BPF/atomics.ll b/test/CodeGen/BPF/atomics.ll
new file mode 100644
index 000000000000..2f9730ddddef
--- /dev/null
+++ b/test/CodeGen/BPF/atomics.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=bpf -verify-machineinstrs -show-mc-encoding | FileCheck %s
+; test little endian only for now
+
+; CHECK-LABEL: test_load_add_32
+; CHECK: xadd32
+; CHECK: encoding: [0xc3
+define void @test_load_add_32(i32* %p, i32 zeroext %v) {
+entry:
+  atomicrmw add i32* %p, i32 %v seq_cst
+  ret void
+}
+
+; CHECK-LABEL: test_load_add_64
+; CHECK: xadd64
+; CHECK: encoding: [0xdb
+define void @test_load_add_64(i64* %p, i64 zeroext %v) {
+entry:
+  atomicrmw add i64* %p, i64 %v seq_cst
+  ret void
+}
diff --git a/test/CodeGen/BPF/basictest.ll b/test/CodeGen/BPF/basictest.ll
new file mode 100644
index 000000000000..2a2d49878a63
--- /dev/null
+++ b/test/CodeGen/BPF/basictest.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=bpf | FileCheck %s
+
+define i32 @test0(i32 %X) {
+  %tmp.1 = add i32 %X, 1
+  ret i32 %tmp.1
+; CHECK-LABEL: test0:
+; CHECK: addi r1, 1
+}
+
+; CHECK-LABEL: store_imm:
+; CHECK: stw  0(r1), r{{[03]}}
+; CHECK: stw  4(r2), r{{[03]}}
+define i32 @store_imm(i32* %a, i32* %b) {
+entry:
+  store i32 0, i32* %a, align 4
+  %0 = getelementptr inbounds i32, i32* %b, i32 1
+  store i32 0, i32* %0, align 4
+  ret i32 0
+}
+
+@G = external global i8
+define zeroext i8 @loadG() {
+  %tmp = load i8, i8* @G
+  ret i8 %tmp
+; CHECK-LABEL: loadG:
+; CHECK: ld_64 r1
+; CHECK: ldb  r0, 0(r1)
+}
diff --git a/test/CodeGen/BPF/byval.ll b/test/CodeGen/BPF/byval.ll
new file mode 100644
index 000000000000..25ba909d9cd7
--- /dev/null
+++ b/test/CodeGen/BPF/byval.ll
@@ -0,0 +1,27 @@
+; RUN: not llc -march=bpf < %s 2> %t1
+; RUN: FileCheck %s < %t1
+; CHECK: by value not supported
+
+%struct.S = type { [10 x i32] }
+
+; Function Attrs: nounwind uwtable
+define void @bar(i32 %a) #0 {
+entry:
+  %.compoundliteral = alloca %struct.S, align 8
+  %arrayinit.begin = getelementptr inbounds %struct.S, %struct.S* %.compoundliteral, i64 0, i32 0, i64 0
+  store i32 1, i32* %arrayinit.begin, align 8
+  %arrayinit.element = getelementptr inbounds %struct.S, %struct.S* %.compoundliteral, i64 0, i32 0, i64 1
+  store i32 2, i32* %arrayinit.element, align 4
+  %arrayinit.element2 = getelementptr inbounds %struct.S, %struct.S* %.compoundliteral, i64 0, i32 0, i64 2
+  store i32 3, i32* %arrayinit.element2, align 8
+  %arrayinit.start = getelementptr inbounds %struct.S, %struct.S* %.compoundliteral, i64 0, i32 0, i64 3
+  %scevgep4 = bitcast i32* %arrayinit.start to i8*
+  call void @llvm.memset.p0i8.i64(i8* %scevgep4, i8 0, i64 28, i32 4, i1 false)
+  call void @foo(i32 %a, %struct.S* byval align 8 %.compoundliteral) #3
+  ret void
+}
+
+declare void @foo(i32, %struct.S* byval align 8) #1
+
+; Function Attrs: nounwind
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #3
diff --git a/test/CodeGen/BPF/cc_args.ll b/test/CodeGen/BPF/cc_args.ll
new file mode 100644
index 000000000000..5085fe5684eb
--- /dev/null
+++ b/test/CodeGen/BPF/cc_args.ll
@@ -0,0 +1,96 @@
+; RUN: llc < %s -march=bpf -show-mc-encoding | FileCheck %s
+; test little endian only for now
+
+define void @test() #0 {
+entry:
+; CHECK: test:
+
+; CHECK: mov  r1, 123 # encoding: [0xb7,0x01,0x00,0x00,0x7b,0x00,0x00,0x00]
+; CHECK: call f_i16
+  call void @f_i16(i16 123)
+
+; CHECK: mov  r1, 12345678 # encoding: [0xb7,0x01,0x00,0x00,0x4e,0x61,0xbc,0x00]
+; CHECK: call f_i32
+  call void @f_i32(i32 12345678)
+
+; CHECK: ld_64 r1, 72623859790382856 # encoding: [0x18,0x01,0x00,0x00,0x08,0x07,0x06,0x05,0x00,0x00,0x00,0x00,0x04,0x03,0x02,0x01]
+; CHECK: call f_i64
+  call void @f_i64(i64 72623859790382856)
+
+; CHECK: mov  r1, 1234
+; CHECK: mov  r2, 5678
+; CHECK: call f_i32_i32
+  call void @f_i32_i32(i32 1234, i32 5678)
+
+; CHECK: mov  r1, 2
+; CHECK: mov  r2, 3
+; CHECK: mov  r3, 4
+; CHECK: call f_i16_i32_i16
+  call void @f_i16_i32_i16(i16 2, i32 3, i16 4)
+
+; CHECK: mov  r1, 5
+; CHECK: ld_64 r2, 7262385979038285
+; CHECK: mov  r3, 6
+; CHECK: call f_i16_i64_i16
+  call void @f_i16_i64_i16(i16 5, i64 7262385979038285, i16 6)
+
+  ret void
+}
+
+@g_i16 = common global i16 0, align 2
+@g_i32 = common global i32 0, align 2
+@g_i64 = common global i64 0, align 4
+
+define void @f_i16(i16 %a) #0 {
+; CHECK: f_i16:
+; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
+  store volatile i16 %a, i16* @g_i16, align 2
+  ret void
+}
+
+define void @f_i32(i32 %a) #0 {
+; CHECK: f_i32:
+; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: sth 2(r2), r1 # encoding: [0x6b,0x12,0x02,0x00,0x00,0x00,0x00,0x00]
+  store volatile i32 %a, i32* @g_i32, align 2
+  ret void
+}
+
+define void @f_i64(i64 %a) #0 {
+; CHECK: f_i64:
+; CHECK: stw 0(r2), r1
+; CHECK: stw 4(r2), r1 # encoding: [0x63,0x12,0x04,0x00,0x00,0x00,0x00,0x00]
+  store volatile i64 %a, i64* @g_i64, align 2
+  ret void
+}
+
+define void @f_i32_i32(i32 %a, i32 %b) #0 {
+; CHECK: f_i32_i32:
+; CHECK: stw 0(r3), r1
+  store volatile i32 %a, i32* @g_i32, align 4
+; CHECK: stw 0(r3), r2
+  store volatile i32 %b, i32* @g_i32, align 4
+  ret void
+}
+
+define void @f_i16_i32_i16(i16 %a, i32 %b, i16 %c) #0 {
+; CHECK: f_i16_i32_i16:
+; CHECK: sth 0(r4), r1
+  store volatile i16 %a, i16* @g_i16, align 2
+; CHECK: stw 0(r1), r2
+  store volatile i32 %b, i32* @g_i32, align 4
+; CHECK: sth 0(r4), r3
+  store volatile i16 %c, i16* @g_i16, align 2
+  ret void
+}
+
+define void @f_i16_i64_i16(i16 %a, i64 %b, i16 %c) #0 {
+; CHECK: f_i16_i64_i16:
+; CHECK: sth 0(r4), r1
+  store volatile i16 %a, i16* @g_i16, align 2
+; CHECK: std 0(r1), r2 # encoding: [0x7b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+  store volatile i64 %b, i64* @g_i64, align 8
+; CHECK: sth 0(r4), r3
+  store volatile i16 %c, i16* @g_i16, align 2
+  ret void
+}
diff --git a/test/CodeGen/BPF/cc_ret.ll b/test/CodeGen/BPF/cc_ret.ll
new file mode 100644
index 000000000000..e32b17bcc61c
--- /dev/null
+++ b/test/CodeGen/BPF/cc_ret.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -march=bpf | FileCheck %s
+
+define void @test() #0 {
+entry:
+; CHECK: test:
+
+; CHECK: call f_i16
+; CHECK: sth 0(r1), r0
+  %0 = call i16 @f_i16()
+  store volatile i16 %0, i16* @g_i16
+
+; CHECK: call f_i32
+; CHECK: stw 0(r1), r0
+  %1 = call i32 @f_i32()
+  store volatile i32 %1, i32* @g_i32
+
+; CHECK: call f_i64
+; CHECK: std 0(r1), r0
+  %2 = call i64 @f_i64()
+  store volatile i64 %2, i64* @g_i64
+
+  ret void
+}
+
+@g_i16 = common global i16 0, align 2
+@g_i32 = common global i32 0, align 2
+@g_i64 = common global i64 0, align 2
+
+define i16 @f_i16() #0 {
+; CHECK: f_i16:
+; CHECK: mov r0, 1
+; CHECK: ret
+  ret i16 1
+}
+
+define i32 @f_i32() #0 {
+; CHECK: f_i32:
+; CHECK: mov r0, 16909060
+; CHECK: ret
+  ret i32 16909060
+}
+
+define i64 @f_i64() #0 {
+; CHECK: f_i64:
+; CHECK: ld_64 r0, 72623859790382856
+; CHECK: ret
+  ret i64 72623859790382856
+}
diff --git a/test/CodeGen/BPF/cmp.ll b/test/CodeGen/BPF/cmp.ll
new file mode 100644
index 000000000000..b353f90ab566
--- /dev/null
+++ b/test/CodeGen/BPF/cmp.ll
@@ -0,0 +1,119 @@
+; RUN: llc < %s -march=bpf | FileCheck %s
+
+; Function Attrs: nounwind readnone uwtable
+define signext i8 @foo_cmp1(i8 signext %a, i8 signext %b) #0 {
+  %1 = icmp sgt i8 %a, %b
+  br i1 %1, label %2, label %4
+
+; <label>:2                                       ; preds = %0
+  %3 = mul i8 %b, %a
+  br label %6
+
+; <label>:4                                       ; preds = %0
+  %5 = shl i8 %b, 3
+  br label %6
+
+; <label>:6                                       ; preds = %4, %2
+  %.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
+  ret i8 %.0
+; CHECK-LABEL:foo_cmp1:
+; CHECK: jsge r2, r1
+}
+
+; Function Attrs: nounwind readnone uwtable
+define signext i8 @foo_cmp2(i8 signext %a, i8 signext %b) #0 {
+  %1 = icmp slt i8 %a, %b
+  br i1 %1, label %4, label %2
+
+; <label>:2                                       ; preds = %0
+  %3 = mul i8 %b, %a
+  br label %6
+
+; <label>:4                                       ; preds = %0
+  %5 = shl i8 %b, 3
+  br label %6
+
+; <label>:6                                       ; preds = %4, %2
+  %.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
+  ret i8 %.0
+; CHECK-LABEL:foo_cmp2:
+; CHECK: jsgt r2, r1
+}
+
+; Function Attrs: nounwind readnone uwtable
+define signext i8 @foo_cmp3(i8 signext %a, i8 signext %b) #0 {
+  %1 = icmp slt i8 %a, %b
+  br i1 %1, label %2, label %4
+
+; <label>:2                                       ; preds = %0
+  %3 = mul i8 %b, %a
+  br label %6
+
+; <label>:4                                       ; preds = %0
+  %5 = shl i8 %b, 3
+  br label %6
+
+; <label>:6                                       ; preds = %4, %2
+  %.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
+  ret i8 %.0
+; CHECK-LABEL:foo_cmp3:
+; CHECK: jsge r1, r2
+}
+
+; Function Attrs: nounwind readnone uwtable
+define signext i8 @foo_cmp4(i8 signext %a, i8 signext %b) #0 {
+  %1 = icmp sgt i8 %a, %b
+  br i1 %1, label %4, label %2
+
+; <label>:2                                       ; preds = %0
+  %3 = mul i8 %b, %a
+  br label %6
+
+; <label>:4                                       ; preds = %0
+  %5 = shl i8 %b, 3
+  br label %6
+
+; <label>:6                                       ; preds = %4, %2
+  %.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
+  ret i8 %.0
+; CHECK-LABEL:foo_cmp4:
+; CHECK: jsgt r1, r2
+}
+
+; Function Attrs: nounwind readnone uwtable
+define signext i8 @min(i8 signext %a, i8 signext %b) #0 {
+  %1 = icmp slt i8 %a, %b
+  %a.b = select i1 %1, i8 %a, i8 %b
+  ret i8 %a.b
+; CHECK-LABEL:min:
+; CHECK: jsgt r2, r1
+; CHECK: mov r1, r2
+; CHECK: mov r0, r1
+}
+
+; Function Attrs: nounwind readnone uwtable
+define zeroext i8 @minu(i8 zeroext %a, i8 zeroext %b) #0 {
+  %1 = icmp ult i8 %a, 100
+  %a.b = select i1 %1, i8 %a, i8 %b
+  ret i8 %a.b
+; CHECK-LABEL:minu:
+; CHECK: jgt r3, r1
+}
+
+; Function Attrs: nounwind readnone uwtable
+define signext i8 @max(i8 signext %a, i8 signext %b) #0 {
+  %1 = icmp sgt i8 %a, %b
+  %a.b = select i1 %1, i8 %a, i8 %b
+  ret i8 %a.b
+; CHECK-LABEL:max:
+; CHECK: jsgt r1, r2
+}
+
+; Function Attrs: nounwind readnone uwtable
+define signext i8 @meq(i8 signext %a, i8 signext %b, i8 signext %c) #0 {
+  %1 = icmp eq i8 %a, %b
+  %c.a = select i1 %1, i8 %c, i8 %a
+  ret i8 %c.a
+; CHECK-LABEL:meq:
+; CHECK: jeq r1, r2
+}
diff --git a/test/CodeGen/BPF/ex1.ll b/test/CodeGen/BPF/ex1.ll
new file mode 100644
index 000000000000..be038e9a3d8c
--- /dev/null
+++ b/test/CodeGen/BPF/ex1.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s -march=bpf | FileCheck %s
+
+%struct.bpf_context = type { i64, i64, i64, i64, i64, i64, i64 }
+%struct.sk_buff = type { i64, i64, i64, i64, i64, i64, i64 }
+%struct.net_device = type { i64, i64, i64, i64, i64, i64, i64 }
+
+@bpf_prog1.devname = private unnamed_addr constant [3 x i8] c"lo\00", align 1
+@bpf_prog1.fmt = private unnamed_addr constant [15 x i8] c"skb %x dev %x\0A\00", align 1
+
+; Function Attrs: nounwind uwtable
+define i32 @bpf_prog1(%struct.bpf_context* nocapture %ctx) #0 section "events/net/netif_receive_skb" {
+  %devname = alloca [3 x i8], align 1
+  %fmt = alloca [15 x i8], align 1
+  %1 = getelementptr inbounds [3 x i8], [3 x i8]* %devname, i64 0, i64 0
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @bpf_prog1.devname, i64 0, i64 0), i64 3, i32 1, i1 false)
+  %2 = getelementptr inbounds %struct.bpf_context, %struct.bpf_context* %ctx, i64 0, i32 0
+  %3 = load i64, i64* %2, align 8
+  %4 = inttoptr i64 %3 to %struct.sk_buff*
+  %5 = getelementptr inbounds %struct.sk_buff, %struct.sk_buff* %4, i64 0, i32 2
+  %6 = bitcast i64* %5 to i8*
+  %7 = call i8* inttoptr (i64 4 to i8* (i8*)*)(i8* %6) #1
+  %8 = call i32 inttoptr (i64 9 to i32 (i8*, i8*, i32)*)(i8* %7, i8* %1, i32 2) #1
+  %9 = icmp eq i32 %8, 0
+  br i1 %9, label %10, label %13
+
+; <label>:10                                      ; preds = %0
+  %11 = getelementptr inbounds [15 x i8], [15 x i8]* %fmt, i64 0, i64 0
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %11, i8* getelementptr inbounds ([15 x i8], [15 x i8]* @bpf_prog1.fmt, i64 0, i64 0), i64 15, i32 1, i1 false)
+  %12 = call i32 (i8*, i32, ...) inttoptr (i64 11 to i32 (i8*, i32, ...)*)(i8* %11, i32 15, %struct.sk_buff* %4, i8* %7) #1
+; CHECK-LABEL: bpf_prog1:
+; CHECK: call 4
+; CHECK: call 9
+; CHECK: jnei r0, 0
+; CHECK: mov r1, 622884453
+; CHECK: ld_64 r1, 7214898703899978611
+; CHECK: call 11
+; CHECK: mov r0, 0
+; CHECK: ret
+  br label %13
+
+; <label>:13                                      ; preds = %10, %0
+  ret i32 0
+}
+
+; Function Attrs: nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) #1
diff --git a/test/CodeGen/BPF/intrinsics.ll b/test/CodeGen/BPF/intrinsics.ll
new file mode 100644
index 000000000000..98b57deb7c8d
--- /dev/null
+++ b/test/CodeGen/BPF/intrinsics.ll
@@ -0,0 +1,88 @@
+; RUN: llc < %s -march=bpf -show-mc-encoding | FileCheck %s
+
+; Function Attrs: nounwind uwtable
+define i32 @ld_b(i64 %foo, i64* nocapture %bar, i8* %ctx, i8* %ctx2) #0 {
+  %1 = tail call i64 @llvm.bpf.load.byte(i8* %ctx, i64 123) #2
+  %2 = add i64 %1, %foo
+  %3 = load volatile i64, i64* %bar, align 8
+  %4 = add i64 %2, %3
+  %5 = tail call i64 @llvm.bpf.load.byte(i8* %ctx2, i64 %foo) #2
+  %6 = add i64 %4, %5
+  %7 = load volatile i64, i64* %bar, align 8
+  %8 = add i64 %6, %7
+  %9 = trunc i64 %8 to i32
+  ret i32 %9
+; CHECK-LABEL: ld_b:
+; CHECK: ldabs_b r0, r6.data + 123
+; CHECK: ldind_b r0, r6.data
+}
+
+declare i64 @llvm.bpf.load.byte(i8*, i64) #1
+
+; Function Attrs: nounwind uwtable
+define i32 @ld_h(i8* %ctx, i8* %ctx2, i32 %foo) #0 {
+  %1 = tail call i64 @llvm.bpf.load.half(i8* %ctx, i64 123) #2
+  %2 = sext i32 %foo to i64
+  %3 = tail call i64 @llvm.bpf.load.half(i8* %ctx2, i64 %2) #2
+  %4 = add i64 %3, %1
+  %5 = trunc i64 %4 to i32
+  ret i32 %5
+; CHECK-LABEL: ld_h:
+; CHECK: ldind_h r0, r6.data
+; CHECK: ldabs_h r0, r6.data + 123
+}
+
+declare i64 @llvm.bpf.load.half(i8*, i64) #1
+
+; Function Attrs: nounwind uwtable
+define i32 @ld_w(i8* %ctx, i8* %ctx2, i32 %foo) #0 {
+  %1 = tail call i64 @llvm.bpf.load.word(i8* %ctx, i64 123) #2
+  %2 = sext i32 %foo to i64
+  %3 = tail call i64 @llvm.bpf.load.word(i8* %ctx2, i64 %2) #2
+  %4 = add i64 %3, %1
+  %5 = trunc i64 %4 to i32
+  ret i32 %5
+; CHECK-LABEL: ld_w:
+; CHECK: ldind_w r0, r6.data
+; CHECK: ldabs_w r0, r6.data + 123
+}
+
+declare i64 @llvm.bpf.load.word(i8*, i64) #1
+
+define i32 @ld_pseudo() #0 {
+entry:
+  %call = tail call i64 @llvm.bpf.pseudo(i64 2, i64 3)
+  tail call void @bar(i64 %call, i32 4) #2
+  ret i32 0
+; CHECK-LABEL: ld_pseudo:
+; CHECK: ld_pseudo r1, 2, 3 # encoding: [0x18,0x21,0x00,0x00,0x03,0x00
+}
+
+declare void @bar(i64, i32) #1
+
+declare i64 @llvm.bpf.pseudo(i64, i64) #2
+
+define i32 @bswap(i64 %a, i64 %b, i64 %c) #0 {
+entry:
+  %0 = tail call i64 @llvm.bswap.i64(i64 %a)
+  %conv = trunc i64 %b to i32
+  %1 = tail call i32 @llvm.bswap.i32(i32 %conv)
+  %conv1 = zext i32 %1 to i64
+  %add = add i64 %conv1, %0
+  %conv2 = trunc i64 %c to i16
+  %2 = tail call i16 @llvm.bswap.i16(i16 %conv2)
+  %conv3 = zext i16 %2 to i64
+  %add4 = add i64 %add, %conv3
+  %conv5 = trunc i64 %add4 to i32
+  ret i32 %conv5
+; CHECK-LABEL: bswap:
+; CHECK: bswap64 r1     # encoding: [0xdc,0x01,0x00,0x00,0x40,0x00,0x00,0x00]
+; CHECK: bswap32 r2     # encoding: [0xdc,0x02,0x00,0x00,0x20,0x00,0x00,0x00]
+; CHECK: add     r2, r1 # encoding: [0x0f,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: bswap16 r3     # encoding: [0xdc,0x03,0x00,0x00,0x10,0x00,0x00,0x00]
+; CHECK: add     r2, r3 # encoding: [0x0f,0x32,0x00,0x00,0x00,0x00,0x00,0x00]
+}
+
+declare i64 @llvm.bswap.i64(i64) #1
+declare i32 @llvm.bswap.i32(i32) #1
+declare i16 @llvm.bswap.i16(i16) #1
diff --git a/test/CodeGen/BPF/lit.local.cfg b/test/CodeGen/BPF/lit.local.cfg
new file mode 100644
index 000000000000..a4ab2624af61
--- /dev/null
+++ b/test/CodeGen/BPF/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'BPF' in config.root.targets:
+    config.unsupported = True
diff --git a/test/CodeGen/BPF/load.ll b/test/CodeGen/BPF/load.ll
new file mode 100644
index 000000000000..03fb17c965b5
--- /dev/null
+++ b/test/CodeGen/BPF/load.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -march=bpf | FileCheck %s
+
+define i16 @am1(i16* %a) nounwind {
+  %1 = load i16, i16* %a
+  ret i16 %1
+}
+; CHECK-LABEL: am1:
+; CHECK: ldh r0, 0(r1)
+
+@foo = external global i16
+
+define i16 @am2() nounwind {
+  %1 = load i16, i16* @foo
+  ret i16 %1
+}
+; CHECK-LABEL: am2:
+; CHECK: ldh r0, 0(r1)
+
+define i16 @am4() nounwind {
+  %1 = load volatile i16, i16* inttoptr(i16 32 to i16*)
+  ret i16 %1
+}
+; CHECK-LABEL: am4:
+; CHECK: mov r1, 32
+; CHECK: ldh r0, 0(r1)
+
+define i16 @am5(i16* %a) nounwind {
+  %1 = getelementptr i16, i16* %a, i16 2
+  %2 = load i16, i16* %1
+  ret i16 %2
+}
+; CHECK-LABEL: am5:
+; CHECK: ldh r0, 4(r1)
+
+%S = type { i16, i16 }
+@baz = common global %S zeroinitializer, align 1
+
+define i16 @am6() nounwind {
+  %1 = load i16, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
+  ret i16 %1
+}
+; CHECK-LABEL: am6:
+; CHECK: ldh r0, 2(r1)
diff --git a/test/CodeGen/BPF/loops.ll b/test/CodeGen/BPF/loops.ll
new file mode 100644
index 000000000000..4798d78842ca
--- /dev/null
+++ b/test/CodeGen/BPF/loops.ll
@@ -0,0 +1,111 @@
+; RUN: llc < %s -march=bpf | FileCheck %s
+
+define zeroext i16 @add(i16* nocapture %a, i16 zeroext %n) nounwind readonly {
+entry:
+  %cmp8 = icmp eq i16 %n, 0                       ; <i1> [#uses=1]
+  br i1 %cmp8, label %for.end, label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
+  %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+  %arrayidx = getelementptr i16, i16* %a, i16 %i.010   ; <i16*> [#uses=1]
+; CHECK-LABEL: add:
+; CHECK: add r{{[0-9]+}}, r{{[0-9]+}}
+  %tmp4 = load i16, i16* %arrayidx                     ; <i16> [#uses=1]
+  %add = add i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
+  %inc = add i16 %i.010, 1                        ; <i16> [#uses=2]
+  %exitcond = icmp eq i16 %inc, %n                ; <i1> [#uses=1]
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  %sum.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+  ret i16 %sum.0.lcssa
+}
+
+define zeroext i16 @sub(i16* nocapture %a, i16 zeroext %n) nounwind readonly {
+entry:
+  %cmp8 = icmp eq i16 %n, 0                       ; <i1> [#uses=1]
+  br i1 %cmp8, label %for.end, label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
+  %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+  %arrayidx = getelementptr i16, i16* %a, i16 %i.010   ; <i16*> [#uses=1]
+; CHECK-LABEL: sub:
+; CHECK: sub r{{[0-9]+}}, r{{[0-9]+}}
+  %tmp4 = load i16, i16* %arrayidx                     ; <i16> [#uses=1]
+  %add = sub i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
+  %inc = add i16 %i.010, 1                        ; <i16> [#uses=2]
+  %exitcond = icmp eq i16 %inc, %n                ; <i1> [#uses=1]
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  %sum.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+  ret i16 %sum.0.lcssa
+}
+
+define zeroext i16 @or(i16* nocapture %a, i16 zeroext %n) nounwind readonly {
+entry:
+  %cmp8 = icmp eq i16 %n, 0                       ; <i1> [#uses=1]
+  br i1 %cmp8, label %for.end, label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
+  %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+  %arrayidx = getelementptr i16, i16* %a, i16 %i.010   ; <i16*> [#uses=1]
+; CHECK-LABEL: or:
+; CHECK: or r{{[0-9]+}}, r{{[0-9]+}}
+  %tmp4 = load i16, i16* %arrayidx                     ; <i16> [#uses=1]
+  %add = or i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
+  %inc = add i16 %i.010, 1                        ; <i16> [#uses=2]
+  %exitcond = icmp eq i16 %inc, %n                ; <i1> [#uses=1]
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  %sum.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+  ret i16 %sum.0.lcssa
+}
+
+define zeroext i16 @xor(i16* nocapture %a, i16 zeroext %n) nounwind readonly {
+entry:
+  %cmp8 = icmp eq i16 %n, 0                       ; <i1> [#uses=1]
+  br i1 %cmp8, label %for.end, label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
+  %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+  %arrayidx = getelementptr i16, i16* %a, i16 %i.010   ; <i16*> [#uses=1]
+; CHECK-LABEL: xor:
+; CHECK: xor r{{[0-9]+}}, r{{[0-9]+}}
+  %tmp4 = load i16, i16* %arrayidx                     ; <i16> [#uses=1]
+  %add = xor i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
+  %inc = add i16 %i.010, 1                        ; <i16> [#uses=2]
+  %exitcond = icmp eq i16 %inc, %n                ; <i1> [#uses=1]
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  %sum.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+  ret i16 %sum.0.lcssa
+}
+
+define zeroext i16 @and(i16* nocapture %a, i16 zeroext %n) nounwind readonly {
+entry:
+  %cmp8 = icmp eq i16 %n, 0                       ; <i1> [#uses=1]
+  br i1 %cmp8, label %for.end, label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
+  %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+  %arrayidx = getelementptr i16, i16* %a, i16 %i.010   ; <i16*> [#uses=1]
+; CHECK-LABEL: and:
+; CHECK: and r{{[0-9]+}}, r{{[0-9]+}}
+  %tmp4 = load i16, i16* %arrayidx                     ; <i16> [#uses=1]
+  %add = and i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
+  %inc = add i16 %i.010, 1                        ; <i16> [#uses=2]
+  %exitcond = icmp eq i16 %inc, %n                ; <i1> [#uses=1]
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  %sum.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+  ret i16 %sum.0.lcssa
+}
diff --git a/test/CodeGen/BPF/many_args1.ll b/test/CodeGen/BPF/many_args1.ll
new file mode 100644
index 000000000000..08218f452d06
--- /dev/null
+++ b/test/CodeGen/BPF/many_args1.ll
@@ -0,0 +1,12 @@
+; RUN: not llc -march=bpf < %s 2> %t1
+; RUN: FileCheck %s < %t1
+; CHECK: too many args
+
+; Function Attrs: nounwind uwtable
+define i32 @foo(i32 %a, i32 %b, i32 %c) #0 {
+entry:
+  %call = tail call i32 @bar(i32 %a, i32 %b, i32 %c, i32 1, i32 2, i32 3) #3
+  ret i32 %call
+}
+
+declare i32 @bar(i32, i32, i32, i32, i32, i32) #1
diff --git a/test/CodeGen/BPF/many_args2.ll b/test/CodeGen/BPF/many_args2.ll
new file mode 100644
index 000000000000..a69886c2b208
--- /dev/null
+++ b/test/CodeGen/BPF/many_args2.ll
@@ -0,0 +1,15 @@
+; RUN: not llc -march=bpf < %s 2> %t1
+; RUN: FileCheck %s < %t1
+; CHECK: too many args
+
+; Function Attrs: nounwind readnone uwtable
+define i32 @bar(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) #0 {
+entry:
+  ret i32 1
+}
+
+; Function Attrs: nounwind readnone uwtable
+define i32 @foo(i32 %a, i32 %b, i32 %c) #0 {
+entry:
+  ret i32 1
+}
diff --git a/test/CodeGen/BPF/sanity.ll b/test/CodeGen/BPF/sanity.ll
new file mode 100644
index 000000000000..09a6b65d0854
--- /dev/null
+++ b/test/CodeGen/BPF/sanity.ll
@@ -0,0 +1,117 @@
+; RUN: llc < %s -march=bpf | FileCheck %s
+
+@foo_printf.fmt = private unnamed_addr constant [9 x i8] c"hello  \0A\00", align 1
+
+; Function Attrs: nounwind readnone uwtable
+define i32 @foo_int(i32 %a, i32 %b) #0 {
+  %1 = add nsw i32 %b, %a
+  ret i32 %1
+; CHECK-LABEL: foo_int:
+; CHECK: add  r2, r1
+}
+
+; Function Attrs: nounwind readnone uwtable
+define signext i8 @foo_char(i8 signext %a, i8 signext %b) #0 {
+  %1 = add i8 %b, %a
+  ret i8 %1
+; CHECK-LABEL: foo_char:
+; CHECK: add  r2, r1
+; CHECK: slli  r2, 56
+; CHECK: srai  r2, 56
+}
+
+; Function Attrs: nounwind readnone uwtable
+define i64 @foo_ll(i64 %a, i64 %b, i64 %c) #0 {
+  %1 = add nsw i64 %b, %a
+  %2 = sub i64 %1, %c
+  ret i64 %2
+; CHECK-LABEL: foo_ll:
+; CHECK: add  r2, r1
+; CHECK: sub  r2, r3
+; CHECK: mov  r0, r2
+}
+
+; Function Attrs: nounwind uwtable
+define void @foo_call2(i32 %a, i32 %b) #1 {
+  %1 = trunc i32 %b to i8
+  tail call void @foo_2arg(i8 signext %1, i32 %a) #3
+  ret void
+; CHECK-LABEL: foo_call2:
+; CHECK: slli  r2, 56
+; CHECK: srai  r2, 56
+; CHECK: mov  r1, r2
+}
+
+declare void @foo_2arg(i8 signext, i32) #2
+
+; Function Attrs: nounwind uwtable
+define i32 @foo_call5(i8 signext %a, i16 signext %b, i32 %c, i64 %d) #1 {
+  %1 = tail call i32 @bar(i8 signext %a, i16 signext %b, i32 %c, i64 %d) #3
+  ret i32 0
+; CHECK-LABEL: foo_call5:
+; CHECK: call bar
+}
+
+declare i32 @bar(i8 signext, i16 signext, i32, i64) #2
+
+; Function Attrs: nounwind readnone uwtable
+define signext i8 @foo_cmp(i8 signext %a, i8 signext %b) #0 {
+  %1 = icmp slt i8 %a, %b
+  %a.b = select i1 %1, i8 %a, i8 %b
+  ret i8 %a.b
+; CHECK-LABEL: foo_cmp:
+; CHECK: jsgt  r2, r1
+}
+
+; Function Attrs: nounwind readnone uwtable
+define i32 @foo_muldiv(i8 signext %a, i16 signext %b, i32 %c, i64 %d) #0 {
+  %1 = icmp eq i8 %a, 0
+  br i1 %1, label %5, label %2
+
+; <label>:2                                       ; preds = %0
+  %3 = sext i16 %b to i32
+  %4 = mul nsw i32 %3, %c
+  br label %8
+
+; <label>:5                                       ; preds = %0
+  %6 = trunc i64 %d to i32
+  %7 = udiv i32 %6, %c
+  br label %8
+
+; <label>:8                                       ; preds = %5, %2
+  %.0 = phi i32 [ %4, %2 ], [ %7, %5 ]
+  ret i32 %.0
+; CHECK-LABEL: foo_muldiv:
+; CHECK: mul r2, r3
+}
+
+; Function Attrs: nounwind uwtable
+define i32 @foo_optimized() #1 {
+  %1 = tail call i32 @manyarg(i32 1, i32 2, i32 3, i32 4, i32 5) #3
+  ret i32 %1
+; CHECK-LABEL: foo_optimized:
+; CHECK: mov r1, 1
+; CHECK: mov r2, 2
+; CHECK: mov r3, 3
+; CHECK: mov r4, 4
+; CHECK: mov r5, 5
+}
+
+declare i32 @manyarg(i32, i32, i32, i32, i32) #2
+
+; Function Attrs: nounwind uwtable
+define void @foo_printf() #1 {
+  %fmt = alloca [9 x i8], align 1
+  %1 = getelementptr inbounds [9 x i8], [9 x i8]* %fmt, i64 0, i64 0
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @foo_printf.fmt, i64 0, i64 0), i64 9, i32 1, i1 false)
+; CHECK-LABEL: foo_printf:
+; CHECK: ld_64 r1, 729618802566522216
+  %2 = call i32 (i8*, ...) @printf(i8* %1) #3
+  ret void
+}
+
+; Function Attrs: nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) #3
+
+; Function Attrs: nounwind
+declare i32 @printf(i8* nocapture, ...) #4
diff --git a/test/CodeGen/BPF/setcc.ll b/test/CodeGen/BPF/setcc.ll
new file mode 100644
index 000000000000..eabb6c9bf2d6
--- /dev/null
+++ b/test/CodeGen/BPF/setcc.ll
@@ -0,0 +1,99 @@
+; RUN: llc -march=bpf < %s | FileCheck %s
+
+define i16 @sccweqand(i16 %a, i16 %b) nounwind {
+  %t1 = and i16 %a, %b
+  %t2 = icmp eq i16 %t1, 0
+  %t3 = zext i1 %t2 to i16
+  ret i16 %t3
+}
+; CHECK-LABEL: sccweqand:
+; CHECK: jeq  r1, r2
+
+define i16 @sccwneand(i16 %a, i16 %b) nounwind {
+  %t1 = and i16 %a, %b
+  %t2 = icmp ne i16 %t1, 0
+  %t3 = zext i1 %t2 to i16
+  ret i16 %t3
+}
+; CHECK-LABEL: sccwneand:
+; CHECK: jne  r1, r2
+
+define i16 @sccwne(i16 %a, i16 %b) nounwind {
+  %t1 = icmp ne i16 %a, %b
+  %t2 = zext i1 %t1 to i16
+  ret i16 %t2
+}
+; CHECK-LABEL:sccwne:
+; CHECK: jne  r1, r2
+
+define i16 @sccweq(i16 %a, i16 %b) nounwind {
+  %t1 = icmp eq i16 %a, %b
+  %t2 = zext i1 %t1 to i16
+  ret i16 %t2
+}
+; CHECK-LABEL:sccweq:
+; CHECK: jeq  r1, r2
+
+define i16 @sccwugt(i16 %a, i16 %b) nounwind {
+  %t1 = icmp ugt i16 %a, %b
+  %t2 = zext i1 %t1 to i16
+  ret i16 %t2
+}
+; CHECK-LABEL:sccwugt:
+; CHECK: jgt  r1, r2
+
+define i16 @sccwuge(i16 %a, i16 %b) nounwind {
+  %t1 = icmp uge i16 %a, %b
+  %t2 = zext i1 %t1 to i16
+  ret i16 %t2
+}
+; CHECK-LABEL:sccwuge:
+; CHECK: jge  r1, r2
+
+define i16 @sccwult(i16 %a, i16 %b) nounwind {
+  %t1 = icmp ult i16 %a, %b
+  %t2 = zext i1 %t1 to i16
+  ret i16 %t2
+}
+; CHECK-LABEL:sccwult:
+; CHECK: jgt  r2, r1
+
+define i16 @sccwule(i16 %a, i16 %b) nounwind {
+  %t1 = icmp ule i16 %a, %b
+  %t2 = zext i1 %t1 to i16
+  ret i16 %t2
+}
+; CHECK-LABEL:sccwule:
+; CHECK: jge  r2, r1
+
+define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
+  %t1 = icmp sgt i16 %a, %b
+  %t2 = zext i1 %t1 to i16
+  ret i16 %t2
+}
+; CHECK-LABEL:sccwsgt:
+; CHECK: jsgt  r1, r2
+
+define i16 @sccwsge(i16 %a, i16 %b) nounwind {
+  %t1 = icmp sge i16 %a, %b
+  %t2 = zext i1 %t1 to i16
+  ret i16 %t2
+}
+; CHECK-LABEL:sccwsge:
+; CHECK: jsge  r1, r2
+
+define i16 @sccwslt(i16 %a, i16 %b) nounwind {
+  %t1 = icmp slt i16 %a, %b
+  %t2 = zext i1 %t1 to i16
+  ret i16 %t2
+}
+; CHECK-LABEL:sccwslt:
+; CHECK: jsgt  r2, r1
+
+define i16 @sccwsle(i16 %a, i16 %b) nounwind {
+  %t1 = icmp sle i16 %a, %b
+  %t2 = zext i1 %t1 to i16
+  ret i16 %t2
+}
+; CHECK-LABEL:sccwsle:
+; CHECK: jsge  r2, r1
diff --git a/test/CodeGen/BPF/shifts.ll b/test/CodeGen/BPF/shifts.ll
new file mode 100644
index 000000000000..898ae2d46123
--- /dev/null
+++ b/test/CodeGen/BPF/shifts.ll
@@ -0,0 +1,101 @@
+; RUN: llc < %s -march=bpf -show-mc-encoding | FileCheck %s
+; test little endian only for now
+
+define zeroext i8 @lshr8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK-LABEL: lshr8:
+; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+  %shr = lshr i8 %a, %cnt
+  ret i8 %shr
+}
+
+define signext i8 @ashr8(i8 signext %a, i8 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK-LABEL: ashr8:
+; CHECK: sra r1, r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+  %shr = ashr i8 %a, %cnt
+  ret i8 %shr
+}
+
+define zeroext i8 @shl8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK: shl8
+; CHECK: sll r1, r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+  %shl = shl i8 %a, %cnt
+  ret i8 %shl
+}
+
+define zeroext i16 @lshr16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK-LABEL: lshr16:
+; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+  %shr = lshr i16 %a, %cnt
+  ret i16 %shr
+}
+
+define signext i16 @ashr16(i16 signext %a, i16 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK-LABEL: ashr16:
+; CHECK: sra r1, r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+  %shr = ashr i16 %a, %cnt
+  ret i16 %shr
+}
+
+define zeroext i16 @shl16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK-LABEL: shl16:
+; CHECK: sll r1, r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+  %shl = shl i16 %a, %cnt
+  ret i16 %shl
+}
+
+define zeroext i32 @lshr32(i32 zeroext %a, i32 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK-LABEL: lshr32:
+; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: slli r1, 32 # encoding: [0x67,0x01,0x00,0x00,0x20,0x00,0x00,0x00]
+  %shr = lshr i32 %a, %cnt
+  ret i32 %shr
+}
+
+define signext i32 @ashr32(i32 signext %a, i32 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK-LABEL: ashr32:
+; CHECK: sra r1, r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+  %shr = ashr i32 %a, %cnt
+  ret i32 %shr
+}
+
+define zeroext i32 @shl32(i32 zeroext %a, i32 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK-LABEL: shl32:
+; CHECK: sll r1, r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+  %shl = shl i32 %a, %cnt
+  ret i32 %shl
+}
+
+define zeroext i64 @lshr64(i64 zeroext %a, i64 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK-LABEL: lshr64:
+; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+  %shr = lshr i64 %a, %cnt
+  ret i64 %shr
+}
+
+define signext i64 @ashr64(i64 signext %a, i64 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK-LABEL: ashr64:
+; CHECK: sra r1, r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+  %shr = ashr i64 %a, %cnt
+  ret i64 %shr
+}
+
+define zeroext i64 @shl64(i64 zeroext %a, i64 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK-LABEL: shl64:
+; CHECK: sll r1, r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: mov r0, r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: ret # encoding: [0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+  %shl = shl i64 %a, %cnt
+  ret i64 %shl
+}
diff --git a/test/CodeGen/BPF/sockex2.ll b/test/CodeGen/BPF/sockex2.ll
new file mode 100644
index 000000000000..6ae5e1c8d6bf
--- /dev/null
+++ b/test/CodeGen/BPF/sockex2.ll
@@ -0,0 +1,326 @@
+; RUN: llc < %s -march=bpf -show-mc-encoding | FileCheck %s
+; test little endian only for now
+
+%struct.bpf_map_def = type { i32, i32, i32, i32 }
+%struct.sk_buff = type opaque
+
+@hash_map = global %struct.bpf_map_def { i32 1, i32 4, i32 8, i32 1024 }, section "maps", align 4
+
+; Function Attrs: nounwind uwtable
+define i32 @bpf_prog2(%struct.sk_buff* %skb) #0 section "socket2" {
+  %key = alloca i32, align 4
+  %val = alloca i64, align 8
+  %1 = bitcast %struct.sk_buff* %skb to i8*
+  %2 = call i64 @llvm.bpf.load.half(i8* %1, i64 12) #2
+  %3 = icmp eq i64 %2, 34984
+  br i1 %3, label %4, label %6
+
+; <label>:4                                       ; preds = %0
+  %5 = call i64 @llvm.bpf.load.half(i8* %1, i64 16) #2
+  br label %6
+
+; <label>:6                                       ; preds = %4, %0
+  %proto.0.i = phi i64 [ %5, %4 ], [ %2, %0 ]
+  %nhoff.0.i = phi i64 [ 18, %4 ], [ 14, %0 ]
+  %7 = icmp eq i64 %proto.0.i, 33024
+  br i1 %7, label %8, label %12
+
+; <label>:8                                       ; preds = %6
+  %9 = add i64 %nhoff.0.i, 2
+  %10 = call i64 @llvm.bpf.load.half(i8* %1, i64 %9) #2
+  %11 = add i64 %nhoff.0.i, 4
+  br label %12
+
+; <label>:12                                      ; preds = %8, %6
+  %proto.1.i = phi i64 [ %10, %8 ], [ %proto.0.i, %6 ]
+  %nhoff.1.i = phi i64 [ %11, %8 ], [ %nhoff.0.i, %6 ]
+  switch i64 %proto.1.i, label %flow_dissector.exit.thread [
+    i64 2048, label %13
+    i64 34525, label %39
+  ]
+
+; <label>:13                                      ; preds = %12
+  %14 = add i64 %nhoff.1.i, 6
+  %15 = call i64 @llvm.bpf.load.half(i8* %1, i64 %14) #2
+  %16 = and i64 %15, 16383
+  %17 = icmp eq i64 %16, 0
+  br i1 %17, label %18, label %.thread.i.i
+
+; <label>:18                                      ; preds = %13
+  %19 = add i64 %nhoff.1.i, 9
+  %20 = call i64 @llvm.bpf.load.byte(i8* %1, i64 %19) #2
+  %21 = icmp eq i64 %20, 47
+  br i1 %21, label %28, label %.thread.i.i
+
+.thread.i.i:                                      ; preds = %18, %13
+  %22 = phi i64 [ %20, %18 ], [ 0, %13 ]
+  %23 = add i64 %nhoff.1.i, 12
+  %24 = call i64 @llvm.bpf.load.word(i8* %1, i64 %23) #2
+  %25 = add i64 %nhoff.1.i, 16
+  %26 = call i64 @llvm.bpf.load.word(i8* %1, i64 %25) #2
+  %27 = trunc i64 %26 to i32
+  br label %28
+
+; <label>:28                                      ; preds = %.thread.i.i, %18
+  %29 = phi i32 [ %27, %.thread.i.i ], [ undef, %18 ]
+  %30 = phi i64 [ %22, %.thread.i.i ], [ 47, %18 ]
+  %31 = call i64 @llvm.bpf.load.byte(i8* %1, i64 %nhoff.1.i) #2
+  %32 = icmp eq i64 %31, 69
+  br i1 %32, label %33, label %35
+
+; <label>:33                                      ; preds = %28
+  %34 = add i64 %nhoff.1.i, 20
+  br label %parse_ip.exit.i
+
+; <label>:35                                      ; preds = %28
+  %36 = shl i64 %31, 2
+  %37 = and i64 %36, 60
+  %38 = add i64 %37, %nhoff.1.i
+  br label %parse_ip.exit.i
+
+; <label>:39                                      ; preds = %12
+  %40 = add i64 %nhoff.1.i, 6
+  %41 = call i64 @llvm.bpf.load.byte(i8* %1, i64 %40) #2
+  %42 = add i64 %nhoff.1.i, 8
+  %43 = call i64 @llvm.bpf.load.word(i8* %1, i64 %42) #2
+  %44 = add i64 %nhoff.1.i, 12
+  %45 = call i64 @llvm.bpf.load.word(i8* %1, i64 %44) #2
+  %46 = add i64 %nhoff.1.i, 16
+  %47 = call i64 @llvm.bpf.load.word(i8* %1, i64 %46) #2
+  %48 = add i64 %nhoff.1.i, 20
+  %49 = call i64 @llvm.bpf.load.word(i8* %1, i64 %48) #2
+  %50 = add i64 %nhoff.1.i, 24
+  %51 = call i64 @llvm.bpf.load.word(i8* %1, i64 %50) #2
+  %52 = add i64 %nhoff.1.i, 28
+  %53 = call i64 @llvm.bpf.load.word(i8* %1, i64 %52) #2
+  %54 = add i64 %nhoff.1.i, 32
+  %55 = call i64 @llvm.bpf.load.word(i8* %1, i64 %54) #2
+  %56 = add i64 %nhoff.1.i, 36
+  %57 = call i64 @llvm.bpf.load.word(i8* %1, i64 %56) #2
+  %58 = xor i64 %53, %51
+  %59 = xor i64 %58, %55
+  %60 = xor i64 %59, %57
+  %61 = trunc i64 %60 to i32
+  %62 = add i64 %nhoff.1.i, 40
+  br label %parse_ip.exit.i
+
+parse_ip.exit.i:                                  ; preds = %39, %35, %33
+  %63 = phi i32 [ %61, %39 ], [ %29, %33 ], [ %29, %35 ]
+  %64 = phi i64 [ %41, %39 ], [ %30, %33 ], [ %30, %35 ]
+  %nhoff.2.i = phi i64 [ %62, %39 ], [ %34, %33 ], [ %38, %35 ]
+  switch i64 %64, label %187 [
+    i64 47, label %65
+    i64 4, label %137
+    i64 41, label %163
+  ]
+
+; <label>:65                                      ; preds = %parse_ip.exit.i
+  %66 = call i64 @llvm.bpf.load.half(i8* %1, i64 %nhoff.2.i) #2
+  %67 = add i64 %nhoff.2.i, 2
+  %68 = call i64 @llvm.bpf.load.half(i8* %1, i64 %67) #2
+  %69 = and i64 %66, 1856
+  %70 = icmp eq i64 %69, 0
+  br i1 %70, label %71, label %187
+
+; <label>:71                                      ; preds = %65
+  %72 = lshr i64 %66, 5
+  %73 = and i64 %72, 4
+  %74 = add i64 %nhoff.2.i, 4
+  %..i = add i64 %74, %73
+  %75 = and i64 %66, 32
+  %76 = icmp eq i64 %75, 0
+  %77 = add i64 %..i, 4
+  %nhoff.4.i = select i1 %76, i64 %..i, i64 %77
+  %78 = and i64 %66, 16
+  %79 = icmp eq i64 %78, 0
+  %80 = add i64 %nhoff.4.i, 4
+  %nhoff.4..i = select i1 %79, i64 %nhoff.4.i, i64 %80
+  %81 = icmp eq i64 %68, 33024
+  br i1 %81, label %82, label %86
+
+; <label>:82                                      ; preds = %71
+  %83 = add i64 %nhoff.4..i, 2
+  %84 = call i64 @llvm.bpf.load.half(i8* %1, i64 %83) #2
+  %85 = add i64 %nhoff.4..i, 4
+  br label %86
+
+; <label>:86                                      ; preds = %82, %71
+  %proto.2.i = phi i64 [ %84, %82 ], [ %68, %71 ]
+  %nhoff.6.i = phi i64 [ %85, %82 ], [ %nhoff.4..i, %71 ]
+  switch i64 %proto.2.i, label %flow_dissector.exit.thread [
+    i64 2048, label %87
+    i64 34525, label %113
+  ]
+
+; <label>:87                                      ; preds = %86
+  %88 = add i64 %nhoff.6.i, 6
+  %89 = call i64 @llvm.bpf.load.half(i8* %1, i64 %88) #2
+  %90 = and i64 %89, 16383
+  %91 = icmp eq i64 %90, 0
+  br i1 %91, label %92, label %.thread.i4.i
+
+; <label>:92                                      ; preds = %87
+  %93 = add i64 %nhoff.6.i, 9
+  %94 = call i64 @llvm.bpf.load.byte(i8* %1, i64 %93) #2
+  %95 = icmp eq i64 %94, 47
+  br i1 %95, label %102, label %.thread.i4.i
+
+.thread.i4.i:                                     ; preds = %92, %87
+  %96 = phi i64 [ %94, %92 ], [ 0, %87 ]
+  %97 = add i64 %nhoff.6.i, 12
+  %98 = call i64 @llvm.bpf.load.word(i8* %1, i64 %97) #2
+  %99 = add i64 %nhoff.6.i, 16
+  %100 = call i64 @llvm.bpf.load.word(i8* %1, i64 %99) #2
+  %101 = trunc i64 %100 to i32
+  br label %102
+
+; <label>:102                                     ; preds = %.thread.i4.i, %92
+  %103 = phi i32 [ %101, %.thread.i4.i ], [ %63, %92 ]
+  %104 = phi i64 [ %96, %.thread.i4.i ], [ 47, %92 ]
+  %105 = call i64 @llvm.bpf.load.byte(i8* %1, i64 %nhoff.6.i) #2
+  %106 = icmp eq i64 %105, 69
+  br i1 %106, label %107, label %109
+
+; <label>:107                                     ; preds = %102
+  %108 = add i64 %nhoff.6.i, 20
+  br label %187
+
+; <label>:109                                     ; preds = %102
+  %110 = shl i64 %105, 2
+  %111 = and i64 %110, 60
+  %112 = add i64 %111, %nhoff.6.i
+  br label %187
+
+; <label>:113                                     ; preds = %86
+  %114 = add i64 %nhoff.6.i, 6
+  %115 = call i64 @llvm.bpf.load.byte(i8* %1, i64 %114) #2
+  %116 = add i64 %nhoff.6.i, 8
+  %117 = call i64 @llvm.bpf.load.word(i8* %1, i64 %116) #2
+  %118 = add i64 %nhoff.6.i, 12
+  %119 = call i64 @llvm.bpf.load.word(i8* %1, i64 %118) #2
+  %120 = add i64 %nhoff.6.i, 16
+  %121 = call i64 @llvm.bpf.load.word(i8* %1, i64 %120) #2
+  %122 = add i64 %nhoff.6.i, 20
+  %123 = call i64 @llvm.bpf.load.word(i8* %1, i64 %122) #2
+  %124 = add i64 %nhoff.6.i, 24
+  %125 = call i64 @llvm.bpf.load.word(i8* %1, i64 %124) #2
+  %126 = add i64 %nhoff.6.i, 28
+  %127 = call i64 @llvm.bpf.load.word(i8* %1, i64 %126) #2
+  %128 = add i64 %nhoff.6.i, 32
+  %129 = call i64 @llvm.bpf.load.word(i8* %1, i64 %128) #2
+  %130 = add i64 %nhoff.6.i, 36
+  %131 = call i64 @llvm.bpf.load.word(i8* %1, i64 %130) #2
+  %132 = xor i64 %127, %125
+  %133 = xor i64 %132, %129
+  %134 = xor i64 %133, %131
+  %135 = trunc i64 %134 to i32
+  %136 = add i64 %nhoff.6.i, 40
+  br label %187
+
+; <label>:137                                     ; preds = %parse_ip.exit.i
+  %138 = add i64 %nhoff.2.i, 6
+  %139 = call i64 @llvm.bpf.load.half(i8* %1, i64 %138) #2
+  %140 = and i64 %139, 16383
+  %141 = icmp eq i64 %140, 0
+  br i1 %141, label %142, label %.thread.i1.i
+
+; <label>:142                                     ; preds = %137
+  %143 = add i64 %nhoff.2.i, 9
+  %144 = call i64 @llvm.bpf.load.byte(i8* %1, i64 %143) #2
+  %145 = icmp eq i64 %144, 47
+  br i1 %145, label %152, label %.thread.i1.i
+
+.thread.i1.i:                                     ; preds = %142, %137
+  %146 = phi i64 [ %144, %142 ], [ 0, %137 ]
+  %147 = add i64 %nhoff.2.i, 12
+  %148 = call i64 @llvm.bpf.load.word(i8* %1, i64 %147) #2
+  %149 = add i64 %nhoff.2.i, 16
+  %150 = call i64 @llvm.bpf.load.word(i8* %1, i64 %149) #2
+  %151 = trunc i64 %150 to i32
+  br label %152
+
+; <label>:152                                     ; preds = %.thread.i1.i, %142
+  %153 = phi i32 [ %151, %.thread.i1.i ], [ %63, %142 ]
+  %154 = phi i64 [ %146, %.thread.i1.i ], [ 47, %142 ]
+  %155 = call i64 @llvm.bpf.load.byte(i8* %1, i64 %nhoff.2.i) #2
+  %156 = icmp eq i64 %155, 69
+  br i1 %156, label %157, label %159
+
+; <label>:157                                     ; preds = %152
+  %158 = add i64 %nhoff.2.i, 20
+  br label %187
+
+; <label>:159                                     ; preds = %152
+  %160 = shl i64 %155, 2
+  %161 = and i64 %160, 60
+  %162 = add i64 %161, %nhoff.2.i
+  br label %187
+
+; <label>:163                                     ; preds = %parse_ip.exit.i
+  %164 = add i64 %nhoff.2.i, 6
+  %165 = call i64 @llvm.bpf.load.byte(i8* %1, i64 %164) #2
+  %166 = add i64 %nhoff.2.i, 8
+  %167 = call i64 @llvm.bpf.load.word(i8* %1, i64 %166) #2
+  %168 = add i64 %nhoff.2.i, 12
+  %169 = call i64 @llvm.bpf.load.word(i8* %1, i64 %168) #2
+  %170 = add i64 %nhoff.2.i, 16
+  %171 = call i64 @llvm.bpf.load.word(i8* %1, i64 %170) #2
+  %172 = add i64 %nhoff.2.i, 20
+  %173 = call i64 @llvm.bpf.load.word(i8* %1, i64 %172) #2
+  %174 = add i64 %nhoff.2.i, 24
+  %175 = call i64 @llvm.bpf.load.word(i8* %1, i64 %174) #2
+  %176 = add i64 %nhoff.2.i, 28
+  %177 = call i64 @llvm.bpf.load.word(i8* %1, i64 %176) #2
+  %178 = add i64 %nhoff.2.i, 32
+  %179 = call i64 @llvm.bpf.load.word(i8* %1, i64 %178) #2
+  %180 = add i64 %nhoff.2.i, 36
+  %181 = call i64 @llvm.bpf.load.word(i8* %1, i64 %180) #2
+  %182 = xor i64 %177, %175
+  %183 = xor i64 %182, %179
+  %184 = xor i64 %183, %181
+  %185 = trunc i64 %184 to i32
+  %186 = add i64 %nhoff.2.i, 40
+  br label %187
+
+; <label>:187                                     ; preds = %163, %159, %157, %113, %109, %107, %65, %parse_ip.exit.i
+  %188 = phi i32 [ %63, %parse_ip.exit.i ], [ %185, %163 ], [ %63, %65 ], [ %135, %113 ], [ %103, %107 ], [ %103, %109 ], [ %153, %157 ], [ %153, %159 ]
+  %189 = phi i64 [ %64, %parse_ip.exit.i ], [ %165, %163 ], [ 47, %65 ], [ %115, %113 ], [ %104, %107 ], [ %104, %109 ], [ %154, %157 ], [ %154, %159 ]
+  %nhoff.7.i = phi i64 [ %nhoff.2.i, %parse_ip.exit.i ], [ %186, %163 ], [ %nhoff.2.i, %65 ], [ %136, %113 ], [ %108, %107 ], [ %112, %109 ], [ %158, %157 ], [ %162, %159 ]
+  %cond.i.i = icmp eq i64 %189, 51
+  %190 = select i1 %cond.i.i, i64 4, i64 0
+  %191 = add i64 %190, %nhoff.7.i
+  %192 = call i64 @llvm.bpf.load.word(i8* %1, i64 %191) #2
+  store i32 %188, i32* %key, align 4
+  %193 = bitcast i32* %key to i8*
+  %194 = call i8* inttoptr (i64 1 to i8* (i8*, i8*)*)(i8* bitcast (%struct.bpf_map_def* @hash_map to i8*), i8* %193) #2
+  %195 = icmp eq i8* %194, null
+  br i1 %195, label %199, label %196
+
+; <label>:196                                     ; preds = %187
+  %197 = bitcast i8* %194 to i64*
+  %198 = atomicrmw add i64* %197, i64 1 seq_cst
+  br label %flow_dissector.exit.thread
+
+; <label>:199                                     ; preds = %187
+  store i64 1, i64* %val, align 8
+  %200 = bitcast i64* %val to i8*
+  %201 = call i32 inttoptr (i64 2 to i32 (i8*, i8*, i8*, i64)*)(i8* bitcast (%struct.bpf_map_def* @hash_map to i8*), i8* %193, i8* %200, i64 0) #2
+  br label %flow_dissector.exit.thread
+
+flow_dissector.exit.thread:                       ; preds = %86, %12, %196, %199
+  ret i32 0
+; CHECK-LABEL: bpf_prog2:
+; CHECK: ldabs_h r0, r6.data + 12 # encoding: [0x28,0x00,0x00,0x00,0x0c,0x00,0x00,0x00]
+; CHECK: ldabs_h r0, r6.data + 16 # encoding: [0x28,0x00,0x00,0x00,0x10,0x00,0x00,0x00]
+; CHECK-NOT: implicit
+; CHECK: ld_64   r1
+; CHECK-NOT: ori
+; CHECK: call 1 # encoding: [0x85,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
+; CHECK: call 2 # encoding: [0x85,0x00,0x00,0x00,0x02,0x00,0x00,0x00]
+}
+
+declare i64 @llvm.bpf.load.half(i8*, i64) #1
+
+declare i64 @llvm.bpf.load.word(i8*, i64) #1
+
+declare i64 @llvm.bpf.load.byte(i8*, i64) #1
diff --git a/test/CodeGen/BPF/struct_ret1.ll b/test/CodeGen/BPF/struct_ret1.ll
new file mode 100644
index 000000000000..29486b56a272
--- /dev/null
+++ b/test/CodeGen/BPF/struct_ret1.ll
@@ -0,0 +1,17 @@
+; RUN: not llc -march=bpf < %s 2> %t1
+; RUN: FileCheck %s < %t1
+; CHECK: only integer returns
+
+%struct.S = type { i32, i32, i32 }
+
+@s = common global %struct.S zeroinitializer, align 4
+
+; Function Attrs: nounwind readonly uwtable
+define { i64, i32 } @bar(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) #0 {
+entry:
+  %retval.sroa.0.0.copyload = load i64, i64* bitcast (%struct.S* @s to i64*), align 4
+  %retval.sroa.2.0.copyload = load i32, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i64 0, i32 2), align 4
+  %.fca.0.insert = insertvalue { i64, i32 } undef, i64 %retval.sroa.0.0.copyload, 0
+  %.fca.1.insert = insertvalue { i64, i32 } %.fca.0.insert, i32 %retval.sroa.2.0.copyload, 1
+  ret { i64, i32 } %.fca.1.insert
+}
diff --git a/test/CodeGen/BPF/struct_ret2.ll b/test/CodeGen/BPF/struct_ret2.ll
new file mode 100644
index 000000000000..90461205f7cf
--- /dev/null
+++ b/test/CodeGen/BPF/struct_ret2.ll
@@ -0,0 +1,12 @@
+; RUN: not llc -march=bpf < %s 2> %t1
+; RUN: FileCheck %s < %t1
+; CHECK: only small returns
+
+; Function Attrs: nounwind uwtable
+define { i64, i32 } @foo(i32 %a, i32 %b, i32 %c) #0 {
+entry:
+  %call = tail call { i64, i32 } @bar(i32 %a, i32 %b, i32 %c, i32 1, i32 2) #3
+  ret { i64, i32 } %call
+}
+
+declare { i64, i32 } @bar(i32, i32, i32, i32, i32) #1
diff --git a/test/CodeGen/BPF/vararg1.ll b/test/CodeGen/BPF/vararg1.ll
new file mode 100644
index 000000000000..4a22db65e692
--- /dev/null
+++ b/test/CodeGen/BPF/vararg1.ll
@@ -0,0 +1,9 @@
+; RUN: not llc -march=bpf < %s 2> %t1
+; RUN: FileCheck %s < %t1
+; CHECK: with VarArgs
+
+; Function Attrs: nounwind readnone uwtable
+define void @foo(i32 %a, ...) #0 {
+entry:
+  ret void
+}
diff --git a/test/CodeGen/CPP/2009-05-01-Long-Double.ll b/test/CodeGen/CPP/2009-05-01-Long-Double.ll
index 0b2d882971a3..470303d6bb05 100644
--- a/test/CodeGen/CPP/2009-05-01-Long-Double.ll
+++ b/test/CodeGen/CPP/2009-05-01-Long-Double.ll
@@ -3,10 +3,10 @@
 define x86_fp80 @some_func() nounwind {
 entry:
 	%retval = alloca x86_fp80		; <x86_fp80*> [#uses=2]
-	%call = call i32 (...)* @other_func()		; <i32> [#uses=1]
+	%call = call i32 (...) @other_func()		; <i32> [#uses=1]
 	%conv = sitofp i32 %call to x86_fp80		; <x86_fp80> [#uses=1]
 	store x86_fp80 %conv, x86_fp80* %retval
-	%0 = load x86_fp80* %retval		; <x86_fp80> [#uses=1]
+	%0 = load x86_fp80, x86_fp80* %retval		; <x86_fp80> [#uses=1]
 	ret x86_fp80 %0
 }
 
diff --git a/test/CodeGen/CPP/2009-05-04-CondBr.ll b/test/CodeGen/CPP/2009-05-04-CondBr.ll
index feb2cf765e7d..9ce1e5f02042 100644
--- a/test/CodeGen/CPP/2009-05-04-CondBr.ll
+++ b/test/CodeGen/CPP/2009-05-04-CondBr.ll
@@ -6,10 +6,10 @@ entry:
 	%retval = alloca i32		; <i32*> [#uses=2]
 	%a.addr = alloca i32		; <i32*> [#uses=8]
 	store i32 %a, i32* %a.addr
-	%tmp = load i32* %a.addr		; <i32> [#uses=1]
+	%tmp = load i32, i32* %a.addr		; <i32> [#uses=1]
 	%inc = add i32 %tmp, 1		; <i32> [#uses=1]
 	store i32 %inc, i32* %a.addr
-	%tmp1 = load i32* %a.addr		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* %a.addr		; <i32> [#uses=1]
 	%cmp = icmp slt i32 %tmp1, 3		; <i1> [#uses=1]
 	br i1 %cmp, label %if.then, label %if.end
 
@@ -18,11 +18,11 @@ if.then:		; preds = %entry
 	br label %if.end
 
 if.end:		; preds = %if.then, %entry
-	%tmp2 = load i32* %a.addr		; <i32> [#uses=1]
+	%tmp2 = load i32, i32* %a.addr		; <i32> [#uses=1]
 	%inc3 = add i32 %tmp2, 1		; <i32> [#uses=1]
 	store i32 %inc3, i32* %a.addr
-	%tmp4 = load i32* %a.addr		; <i32> [#uses=1]
+	%tmp4 = load i32, i32* %a.addr		; <i32> [#uses=1]
 	store i32 %tmp4, i32* %retval
-	%0 = load i32* %retval		; <i32> [#uses=1]
+	%0 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %0
 }
diff --git a/test/CodeGen/Generic/2003-05-28-ManyArgs.ll b/test/CodeGen/Generic/2003-05-28-ManyArgs.ll
index c6fbdaef8293..c2ffc7933572 100644
--- a/test/CodeGen/Generic/2003-05-28-ManyArgs.ll
+++ b/test/CodeGen/Generic/2003-05-28-ManyArgs.ll
@@ -42,102 +42,102 @@ entry:
 	%det_routing_arch = alloca %struct..s_det_routing_arch		; <%struct..s_det_routing_arch*> [#uses=11]
 	%segment_inf = alloca %struct..s_segment_inf*		; <%struct..s_segment_inf**> [#uses=1]
 	%timing_inf = alloca { i32, float, float, float, float, float, float, float, float, float, float }		; <{ i32, float, float, float, float, float, float, float, float, float, float }*> [#uses=11]
-	%tmp.101 = getelementptr %struct..s_placer_opts* %placer_opts, i64 0, i32 4		; <i8**> [#uses=1]
-	%tmp.105 = getelementptr [300 x i8]* %net_file, i64 0, i64 0		; <i8*> [#uses=1]
-	%tmp.106 = getelementptr [300 x i8]* %arch_file, i64 0, i64 0		; <i8*> [#uses=1]
-	%tmp.107 = getelementptr [300 x i8]* %place_file, i64 0, i64 0		; <i8*> [#uses=1]
-	%tmp.108 = getelementptr [300 x i8]* %route_file, i64 0, i64 0		; <i8*> [#uses=1]
-	%tmp.109 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 0		; <i32*> [#uses=1]
-	%tmp.112 = getelementptr %struct..s_placer_opts* %placer_opts, i64 0, i32 0		; <i32*> [#uses=1]
-	%tmp.114 = getelementptr %struct..s_placer_opts* %placer_opts, i64 0, i32 6		; <i32*> [#uses=1]
-	%tmp.118 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 7		; <i32*> [#uses=1]
-	%tmp.135 = load i32* %operation		; <i32> [#uses=1]
-	%tmp.137 = load i32* %tmp.112		; <i32> [#uses=1]
-	%tmp.138 = getelementptr %struct..s_placer_opts* %placer_opts, i64 0, i32 1		; <float*> [#uses=1]
-	%tmp.139 = load float* %tmp.138		; <float> [#uses=1]
-	%tmp.140 = getelementptr %struct..s_placer_opts* %placer_opts, i64 0, i32 2		; <i32*> [#uses=1]
-	%tmp.141 = load i32* %tmp.140		; <i32> [#uses=1]
-	%tmp.142 = getelementptr %struct..s_placer_opts* %placer_opts, i64 0, i32 3		; <i32*> [#uses=1]
-	%tmp.143 = load i32* %tmp.142		; <i32> [#uses=1]
-	%tmp.145 = load i8** %tmp.101		; <i8*> [#uses=1]
-	%tmp.146 = getelementptr %struct..s_placer_opts* %placer_opts, i64 0, i32 5		; <i32*> [#uses=1]
-	%tmp.147 = load i32* %tmp.146		; <i32> [#uses=1]
-	%tmp.149 = load i32* %tmp.114		; <i32> [#uses=1]
-	%tmp.154 = load i32* %full_stats		; <i32> [#uses=1]
-	%tmp.155 = load i32* %verify_binary_search		; <i32> [#uses=1]
-	%tmp.156 = getelementptr %struct..s_annealing_sched* %annealing_sched, i64 0, i32 0		; <i32*> [#uses=1]
-	%tmp.157 = load i32* %tmp.156		; <i32> [#uses=1]
-	%tmp.158 = getelementptr %struct..s_annealing_sched* %annealing_sched, i64 0, i32 1		; <float*> [#uses=1]
-	%tmp.159 = load float* %tmp.158		; <float> [#uses=1]
-	%tmp.160 = getelementptr %struct..s_annealing_sched* %annealing_sched, i64 0, i32 2		; <float*> [#uses=1]
-	%tmp.161 = load float* %tmp.160		; <float> [#uses=1]
-	%tmp.162 = getelementptr %struct..s_annealing_sched* %annealing_sched, i64 0, i32 3		; <float*> [#uses=1]
-	%tmp.163 = load float* %tmp.162		; <float> [#uses=1]
-	%tmp.164 = getelementptr %struct..s_annealing_sched* %annealing_sched, i64 0, i32 4		; <float*> [#uses=1]
-	%tmp.165 = load float* %tmp.164		; <float> [#uses=1]
-	%tmp.166 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 0		; <float*> [#uses=1]
-	%tmp.167 = load float* %tmp.166		; <float> [#uses=1]
-	%tmp.168 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 1		; <float*> [#uses=1]
-	%tmp.169 = load float* %tmp.168		; <float> [#uses=1]
-	%tmp.170 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 2		; <float*> [#uses=1]
-	%tmp.171 = load float* %tmp.170		; <float> [#uses=1]
-	%tmp.172 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 3		; <float*> [#uses=1]
-	%tmp.173 = load float* %tmp.172		; <float> [#uses=1]
-	%tmp.174 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 4		; <float*> [#uses=1]
-	%tmp.175 = load float* %tmp.174		; <float> [#uses=1]
-	%tmp.176 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 5		; <i32*> [#uses=1]
-	%tmp.177 = load i32* %tmp.176		; <i32> [#uses=1]
-	%tmp.178 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 6		; <i32*> [#uses=1]
-	%tmp.179 = load i32* %tmp.178		; <i32> [#uses=1]
-	%tmp.181 = load i32* %tmp.118		; <i32> [#uses=1]
-	%tmp.182 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 8		; <i32*> [#uses=1]
-	%tmp.183 = load i32* %tmp.182		; <i32> [#uses=1]
-	%tmp.184 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 0		; <i32*> [#uses=1]
-	%tmp.185 = load i32* %tmp.184		; <i32> [#uses=1]
-	%tmp.186 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 1		; <float*> [#uses=1]
-	%tmp.187 = load float* %tmp.186		; <float> [#uses=1]
-	%tmp.188 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 2		; <float*> [#uses=1]
-	%tmp.189 = load float* %tmp.188		; <float> [#uses=1]
-	%tmp.190 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 3		; <float*> [#uses=1]
-	%tmp.191 = load float* %tmp.190		; <float> [#uses=1]
-	%tmp.192 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 4		; <i32*> [#uses=1]
-	%tmp.193 = load i32* %tmp.192		; <i32> [#uses=1]
-	%tmp.194 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 5		; <i32*> [#uses=1]
-	%tmp.195 = load i32* %tmp.194		; <i32> [#uses=1]
-	%tmp.196 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 6		; <i16*> [#uses=1]
-	%tmp.197 = load i16* %tmp.196		; <i16> [#uses=1]
-	%tmp.198 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 7		; <i16*> [#uses=1]
-	%tmp.199 = load i16* %tmp.198		; <i16> [#uses=1]
-	%tmp.200 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 8		; <i16*> [#uses=1]
-	%tmp.201 = load i16* %tmp.200		; <i16> [#uses=1]
-	%tmp.202 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 9		; <float*> [#uses=1]
-	%tmp.203 = load float* %tmp.202		; <float> [#uses=1]
-	%tmp.204 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 10		; <float*> [#uses=1]
-	%tmp.205 = load float* %tmp.204		; <float> [#uses=1]
-	%tmp.206 = load %struct..s_segment_inf** %segment_inf		; <%struct..s_segment_inf*> [#uses=1]
-	%tmp.208 = load i32* %tmp.109		; <i32> [#uses=1]
-	%tmp.209 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 1		; <float*> [#uses=1]
-	%tmp.210 = load float* %tmp.209		; <float> [#uses=1]
-	%tmp.211 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 2		; <float*> [#uses=1]
-	%tmp.212 = load float* %tmp.211		; <float> [#uses=1]
-	%tmp.213 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 3		; <float*> [#uses=1]
-	%tmp.214 = load float* %tmp.213		; <float> [#uses=1]
-	%tmp.215 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 4		; <float*> [#uses=1]
-	%tmp.216 = load float* %tmp.215		; <float> [#uses=1]
-	%tmp.217 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 5		; <float*> [#uses=1]
-	%tmp.218 = load float* %tmp.217		; <float> [#uses=1]
-	%tmp.219 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 6		; <float*> [#uses=1]
-	%tmp.220 = load float* %tmp.219		; <float> [#uses=1]
-	%tmp.221 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 7		; <float*> [#uses=1]
-	%tmp.222 = load float* %tmp.221		; <float> [#uses=1]
-	%tmp.223 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 8		; <float*> [#uses=1]
-	%tmp.224 = load float* %tmp.223		; <float> [#uses=1]
-	%tmp.225 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 9		; <float*> [#uses=1]
-	%tmp.226 = load float* %tmp.225		; <float> [#uses=1]
-	%tmp.227 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 10		; <float*> [#uses=1]
-	%tmp.228 = load float* %tmp.227		; <float> [#uses=1]
+	%tmp.101 = getelementptr %struct..s_placer_opts, %struct..s_placer_opts* %placer_opts, i64 0, i32 4		; <i8**> [#uses=1]
+	%tmp.105 = getelementptr [300 x i8], [300 x i8]* %net_file, i64 0, i64 0		; <i8*> [#uses=1]
+	%tmp.106 = getelementptr [300 x i8], [300 x i8]* %arch_file, i64 0, i64 0		; <i8*> [#uses=1]
+	%tmp.107 = getelementptr [300 x i8], [300 x i8]* %place_file, i64 0, i64 0		; <i8*> [#uses=1]
+	%tmp.108 = getelementptr [300 x i8], [300 x i8]* %route_file, i64 0, i64 0		; <i8*> [#uses=1]
+	%tmp.109 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 0		; <i32*> [#uses=1]
+	%tmp.112 = getelementptr %struct..s_placer_opts, %struct..s_placer_opts* %placer_opts, i64 0, i32 0		; <i32*> [#uses=1]
+	%tmp.114 = getelementptr %struct..s_placer_opts, %struct..s_placer_opts* %placer_opts, i64 0, i32 6		; <i32*> [#uses=1]
+	%tmp.118 = getelementptr %struct..s_router_opts, %struct..s_router_opts* %router_opts, i64 0, i32 7		; <i32*> [#uses=1]
+	%tmp.135 = load i32, i32* %operation		; <i32> [#uses=1]
+	%tmp.137 = load i32, i32* %tmp.112		; <i32> [#uses=1]
+	%tmp.138 = getelementptr %struct..s_placer_opts, %struct..s_placer_opts* %placer_opts, i64 0, i32 1		; <float*> [#uses=1]
+	%tmp.139 = load float, float* %tmp.138		; <float> [#uses=1]
+	%tmp.140 = getelementptr %struct..s_placer_opts, %struct..s_placer_opts* %placer_opts, i64 0, i32 2		; <i32*> [#uses=1]
+	%tmp.141 = load i32, i32* %tmp.140		; <i32> [#uses=1]
+	%tmp.142 = getelementptr %struct..s_placer_opts, %struct..s_placer_opts* %placer_opts, i64 0, i32 3		; <i32*> [#uses=1]
+	%tmp.143 = load i32, i32* %tmp.142		; <i32> [#uses=1]
+	%tmp.145 = load i8*, i8** %tmp.101		; <i8*> [#uses=1]
+	%tmp.146 = getelementptr %struct..s_placer_opts, %struct..s_placer_opts* %placer_opts, i64 0, i32 5		; <i32*> [#uses=1]
+	%tmp.147 = load i32, i32* %tmp.146		; <i32> [#uses=1]
+	%tmp.149 = load i32, i32* %tmp.114		; <i32> [#uses=1]
+	%tmp.154 = load i32, i32* %full_stats		; <i32> [#uses=1]
+	%tmp.155 = load i32, i32* %verify_binary_search		; <i32> [#uses=1]
+	%tmp.156 = getelementptr %struct..s_annealing_sched, %struct..s_annealing_sched* %annealing_sched, i64 0, i32 0		; <i32*> [#uses=1]
+	%tmp.157 = load i32, i32* %tmp.156		; <i32> [#uses=1]
+	%tmp.158 = getelementptr %struct..s_annealing_sched, %struct..s_annealing_sched* %annealing_sched, i64 0, i32 1		; <float*> [#uses=1]
+	%tmp.159 = load float, float* %tmp.158		; <float> [#uses=1]
+	%tmp.160 = getelementptr %struct..s_annealing_sched, %struct..s_annealing_sched* %annealing_sched, i64 0, i32 2		; <float*> [#uses=1]
+	%tmp.161 = load float, float* %tmp.160		; <float> [#uses=1]
+	%tmp.162 = getelementptr %struct..s_annealing_sched, %struct..s_annealing_sched* %annealing_sched, i64 0, i32 3		; <float*> [#uses=1]
+	%tmp.163 = load float, float* %tmp.162		; <float> [#uses=1]
+	%tmp.164 = getelementptr %struct..s_annealing_sched, %struct..s_annealing_sched* %annealing_sched, i64 0, i32 4		; <float*> [#uses=1]
+	%tmp.165 = load float, float* %tmp.164		; <float> [#uses=1]
+	%tmp.166 = getelementptr %struct..s_router_opts, %struct..s_router_opts* %router_opts, i64 0, i32 0		; <float*> [#uses=1]
+	%tmp.167 = load float, float* %tmp.166		; <float> [#uses=1]
+	%tmp.168 = getelementptr %struct..s_router_opts, %struct..s_router_opts* %router_opts, i64 0, i32 1		; <float*> [#uses=1]
+	%tmp.169 = load float, float* %tmp.168		; <float> [#uses=1]
+	%tmp.170 = getelementptr %struct..s_router_opts, %struct..s_router_opts* %router_opts, i64 0, i32 2		; <float*> [#uses=1]
+	%tmp.171 = load float, float* %tmp.170		; <float> [#uses=1]
+	%tmp.172 = getelementptr %struct..s_router_opts, %struct..s_router_opts* %router_opts, i64 0, i32 3		; <float*> [#uses=1]
+	%tmp.173 = load float, float* %tmp.172		; <float> [#uses=1]
+	%tmp.174 = getelementptr %struct..s_router_opts, %struct..s_router_opts* %router_opts, i64 0, i32 4		; <float*> [#uses=1]
+	%tmp.175 = load float, float* %tmp.174		; <float> [#uses=1]
+	%tmp.176 = getelementptr %struct..s_router_opts, %struct..s_router_opts* %router_opts, i64 0, i32 5		; <i32*> [#uses=1]
+	%tmp.177 = load i32, i32* %tmp.176		; <i32> [#uses=1]
+	%tmp.178 = getelementptr %struct..s_router_opts, %struct..s_router_opts* %router_opts, i64 0, i32 6		; <i32*> [#uses=1]
+	%tmp.179 = load i32, i32* %tmp.178		; <i32> [#uses=1]
+	%tmp.181 = load i32, i32* %tmp.118		; <i32> [#uses=1]
+	%tmp.182 = getelementptr %struct..s_router_opts, %struct..s_router_opts* %router_opts, i64 0, i32 8		; <i32*> [#uses=1]
+	%tmp.183 = load i32, i32* %tmp.182		; <i32> [#uses=1]
+	%tmp.184 = getelementptr %struct..s_det_routing_arch, %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 0		; <i32*> [#uses=1]
+	%tmp.185 = load i32, i32* %tmp.184		; <i32> [#uses=1]
+	%tmp.186 = getelementptr %struct..s_det_routing_arch, %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 1		; <float*> [#uses=1]
+	%tmp.187 = load float, float* %tmp.186		; <float> [#uses=1]
+	%tmp.188 = getelementptr %struct..s_det_routing_arch, %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 2		; <float*> [#uses=1]
+	%tmp.189 = load float, float* %tmp.188		; <float> [#uses=1]
+	%tmp.190 = getelementptr %struct..s_det_routing_arch, %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 3		; <float*> [#uses=1]
+	%tmp.191 = load float, float* %tmp.190		; <float> [#uses=1]
+	%tmp.192 = getelementptr %struct..s_det_routing_arch, %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 4		; <i32*> [#uses=1]
+	%tmp.193 = load i32, i32* %tmp.192		; <i32> [#uses=1]
+	%tmp.194 = getelementptr %struct..s_det_routing_arch, %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 5		; <i32*> [#uses=1]
+	%tmp.195 = load i32, i32* %tmp.194		; <i32> [#uses=1]
+	%tmp.196 = getelementptr %struct..s_det_routing_arch, %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 6		; <i16*> [#uses=1]
+	%tmp.197 = load i16, i16* %tmp.196		; <i16> [#uses=1]
+	%tmp.198 = getelementptr %struct..s_det_routing_arch, %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 7		; <i16*> [#uses=1]
+	%tmp.199 = load i16, i16* %tmp.198		; <i16> [#uses=1]
+	%tmp.200 = getelementptr %struct..s_det_routing_arch, %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 8		; <i16*> [#uses=1]
+	%tmp.201 = load i16, i16* %tmp.200		; <i16> [#uses=1]
+	%tmp.202 = getelementptr %struct..s_det_routing_arch, %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 9		; <float*> [#uses=1]
+	%tmp.203 = load float, float* %tmp.202		; <float> [#uses=1]
+	%tmp.204 = getelementptr %struct..s_det_routing_arch, %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 10		; <float*> [#uses=1]
+	%tmp.205 = load float, float* %tmp.204		; <float> [#uses=1]
+	%tmp.206 = load %struct..s_segment_inf*, %struct..s_segment_inf** %segment_inf		; <%struct..s_segment_inf*> [#uses=1]
+	%tmp.208 = load i32, i32* %tmp.109		; <i32> [#uses=1]
+	%tmp.209 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 1		; <float*> [#uses=1]
+	%tmp.210 = load float, float* %tmp.209		; <float> [#uses=1]
+	%tmp.211 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 2		; <float*> [#uses=1]
+	%tmp.212 = load float, float* %tmp.211		; <float> [#uses=1]
+	%tmp.213 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 3		; <float*> [#uses=1]
+	%tmp.214 = load float, float* %tmp.213		; <float> [#uses=1]
+	%tmp.215 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 4		; <float*> [#uses=1]
+	%tmp.216 = load float, float* %tmp.215		; <float> [#uses=1]
+	%tmp.217 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 5		; <float*> [#uses=1]
+	%tmp.218 = load float, float* %tmp.217		; <float> [#uses=1]
+	%tmp.219 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 6		; <float*> [#uses=1]
+	%tmp.220 = load float, float* %tmp.219		; <float> [#uses=1]
+	%tmp.221 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 7		; <float*> [#uses=1]
+	%tmp.222 = load float, float* %tmp.221		; <float> [#uses=1]
+	%tmp.223 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 8		; <float*> [#uses=1]
+	%tmp.224 = load float, float* %tmp.223		; <float> [#uses=1]
+	%tmp.225 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 9		; <float*> [#uses=1]
+	%tmp.226 = load float, float* %tmp.225		; <float> [#uses=1]
+	%tmp.227 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 10		; <float*> [#uses=1]
+	%tmp.228 = load float, float* %tmp.227		; <float> [#uses=1]
 	call void @place_and_route( i32 %tmp.135, i32 %tmp.137, float %tmp.139, i32 %tmp.141, i32 %tmp.143, i8* %tmp.145, i32 %tmp.147, i32 %tmp.149, i8* %tmp.107, i8* %tmp.105, i8* %tmp.106, i8* %tmp.108, i32 %tmp.154, i32 %tmp.155, i32 %tmp.157, float %tmp.159, float %tmp.161, float %tmp.163, float %tmp.165, float %tmp.167, float %tmp.169, float %tmp.171, float %tmp.173, float %tmp.175, i32 %tmp.177, i32 %tmp.179, i32 %tmp.181, i32 %tmp.183, i32 %tmp.185, float %tmp.187, float %tmp.189, float %tmp.191, i32 %tmp.193, i32 %tmp.195, i16 %tmp.197, i16 %tmp.199, i16 %tmp.201, float %tmp.203, float %tmp.205, %struct..s_segment_inf* %tmp.206, i32 %tmp.208, float %tmp.210, float %tmp.212, float %tmp.214, float %tmp.216, float %tmp.218, float %tmp.220, float %tmp.222, float %tmp.224, float %tmp.226, float %tmp.228 )
-	%tmp.231 = load i32* %show_graphics		; <i32> [#uses=1]
+	%tmp.231 = load i32, i32* %show_graphics		; <i32> [#uses=1]
 	%tmp.232 = icmp ne i32 %tmp.231, 0		; <i1> [#uses=1]
 	br i1 %tmp.232, label %then.2, label %endif.2
 
diff --git a/test/CodeGen/Generic/2003-05-30-BadFoldGEP.ll b/test/CodeGen/Generic/2003-05-30-BadFoldGEP.ll
index 10d3a11a5190..9e3d254264a5 100644
--- a/test/CodeGen/Generic/2003-05-30-BadFoldGEP.ll
+++ b/test/CodeGen/Generic/2003-05-30-BadFoldGEP.ll
@@ -22,11 +22,11 @@
 
 define internal i32 @OpenOutput(i8* %filename.1) {
 entry:
-        %tmp.0 = load %FileType** @Output               ; <%FileType*> [#uses=1]
-        %tmp.4 = getelementptr %FileType* %tmp.0, i64 1         ; <%FileType*> [#uses=1]
-        %addrOfGlobal = getelementptr [16 x %FileType]* @OutputFiles, i64 0             ; <[16 x %FileType]*> [#uses=1]
-        %constantGEP = getelementptr [16 x %FileType]* %addrOfGlobal, i64 1             ; <[16 x %FileType]*> [#uses=1]
-        %constantGEP.upgrd.1 = getelementptr [16 x %FileType]* %constantGEP, i64 0, i64 0               ; <%FileType*> [#uses=1]
+        %tmp.0 = load %FileType*, %FileType** @Output               ; <%FileType*> [#uses=1]
+        %tmp.4 = getelementptr %FileType, %FileType* %tmp.0, i64 1         ; <%FileType*> [#uses=1]
+        %addrOfGlobal = getelementptr [16 x %FileType], [16 x %FileType]* @OutputFiles, i64 0             ; <[16 x %FileType]*> [#uses=1]
+        %constantGEP = getelementptr [16 x %FileType], [16 x %FileType]* %addrOfGlobal, i64 1             ; <[16 x %FileType]*> [#uses=1]
+        %constantGEP.upgrd.1 = getelementptr [16 x %FileType], [16 x %FileType]* %constantGEP, i64 0, i64 0               ; <%FileType*> [#uses=1]
         %tmp.10 = icmp eq %FileType* %tmp.4, %constantGEP.upgrd.1               ; <i1> [#uses=1]
         br i1 %tmp.10, label %return, label %endif.0
 
diff --git a/test/CodeGen/Generic/2003-07-06-BadIntCmp.ll b/test/CodeGen/Generic/2003-07-06-BadIntCmp.ll
index 1d1aad5f27e2..7e402f595809 100644
--- a/test/CodeGen/Generic/2003-07-06-BadIntCmp.ll
+++ b/test/CodeGen/Generic/2003-07-06-BadIntCmp.ll
@@ -31,11 +31,11 @@ entry:
         br i1 %tmp.8, label %then, label %else
 
 then:           ; preds = %entry
-        %tmp.11 = call i32 (i8*, ...)* @printf( i8* getelementptr ([6 x i8]* @.str_1, i64 0, i64 0) )           ; <i32> [#uses=0]
+        %tmp.11 = call i32 (i8*, ...) @printf( i8* getelementptr ([6 x i8], [6 x i8]* @.str_1, i64 0, i64 0) )           ; <i32> [#uses=0]
         br label %UnifiedExitNode
 
 else:           ; preds = %entry
-        %tmp.13 = call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8]* @.str_2, i64 0, i64 0) )           ; <i32> [#uses=0]
+        %tmp.13 = call i32 (i8*, ...) @printf( i8* getelementptr ([7 x i8], [7 x i8]* @.str_2, i64 0, i64 0) )           ; <i32> [#uses=0]
         br label %UnifiedExitNode
 
 UnifiedExitNode:                ; preds = %else, %then
diff --git a/test/CodeGen/Generic/2003-07-07-BadLongConst.ll b/test/CodeGen/Generic/2003-07-07-BadLongConst.ll
index 64312ba09a50..928b57efda16 100644
--- a/test/CodeGen/Generic/2003-07-07-BadLongConst.ll
+++ b/test/CodeGen/Generic/2003-07-07-BadLongConst.ll
@@ -14,7 +14,7 @@ entry:
         %tmp.11 = call i64 @getL( )             ; <i64> [#uses=2]
         %tmp.5 = trunc i64 %tmp.11 to i32               ; <i32> [#uses=2]
         %tmp.23 = and i64 %tmp.11, -4294967296          ; <i64> [#uses=2]
-        %tmp.16 = call i32 (i8*, ...)* @printf( i8* getelementptr ([42 x i8]* @.str_1, i64 0, i64 0), i32 %tmp.5, i32 %tmp.5, i64 %tmp.23, i64 %tmp.23 )              ; <i32> [#uses=0]
+        %tmp.16 = call i32 (i8*, ...) @printf( i8* getelementptr ([42 x i8], [42 x i8]* @.str_1, i64 0, i64 0), i32 %tmp.5, i32 %tmp.5, i64 %tmp.23, i64 %tmp.23 )              ; <i32> [#uses=0]
         ret i32 0
 }
 
diff --git a/test/CodeGen/Generic/2003-07-08-BadCastToBool.ll b/test/CodeGen/Generic/2003-07-08-BadCastToBool.ll
index 8019caa832d7..73ad186be551 100644
--- a/test/CodeGen/Generic/2003-07-08-BadCastToBool.ll
+++ b/test/CodeGen/Generic/2003-07-08-BadCastToBool.ll
@@ -28,7 +28,7 @@ entry:
 define i32 @main() {
 entry:
         %result = call i32 @adj( i32 3, i32 2 )         ; <i32> [#uses=1]
-        %tmp.0 = call i32 (i8*, ...)* @printf( i8* getelementptr ([30 x i8]* @.str_1, i64 0, i64 0), i32 3, i32 2, i32 %result )              ; <i32> [#uses=0]
+        %tmp.0 = call i32 (i8*, ...) @printf( i8* getelementptr ([30 x i8], [30 x i8]* @.str_1, i64 0, i64 0), i32 3, i32 2, i32 %result )              ; <i32> [#uses=0]
         ret i32 0
 }
 
diff --git a/test/CodeGen/Generic/2003-07-29-BadConstSbyte.ll b/test/CodeGen/Generic/2003-07-29-BadConstSbyte.ll
index 4e6fe1cf8bf5..010c0c553638 100644
--- a/test/CodeGen/Generic/2003-07-29-BadConstSbyte.ll
+++ b/test/CodeGen/Generic/2003-07-29-BadConstSbyte.ll
@@ -26,10 +26,10 @@ entry:
 
 loopentry:              ; preds = %loopentry, %entry
         %i = phi i64 [ 0, %entry ], [ %inc.i, %loopentry ]              ; <i64> [#uses=3]
-        %cptr = getelementptr [6 x i8]* @yy_ec, i64 0, i64 %i           ; <i8*> [#uses=1]
-        %c = load i8* %cptr             ; <i8> [#uses=1]
-        %ignore = call i32 (i8*, ...)* @printf( i8* getelementptr ([8 x i8]* @.str_3, i64 0, i64 0), i64 %i )        ; <i32> [#uses=0]
-        %ignore2 = call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @.str_4, i64 0, i64 0), i8 %c )        ; <i32> [#uses=0]
+        %cptr = getelementptr [6 x i8], [6 x i8]* @yy_ec, i64 0, i64 %i           ; <i8*> [#uses=1]
+        %c = load i8, i8* %cptr             ; <i8> [#uses=1]
+        %ignore = call i32 (i8*, ...) @printf( i8* getelementptr ([8 x i8], [8 x i8]* @.str_3, i64 0, i64 0), i64 %i )        ; <i32> [#uses=0]
+        %ignore2 = call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @.str_4, i64 0, i64 0), i8 %c )        ; <i32> [#uses=0]
         %inc.i = add i64 %i, 1          ; <i64> [#uses=2]
         %done = icmp sle i64 %inc.i, 5          ; <i1> [#uses=1]
         br i1 %done, label %loopentry, label %exit.1
diff --git a/test/CodeGen/Generic/2004-05-09-LiveVarPartialRegister.ll b/test/CodeGen/Generic/2004-05-09-LiveVarPartialRegister.ll
index d4a4cf88ce0c..8dfdd0172c29 100644
--- a/test/CodeGen/Generic/2004-05-09-LiveVarPartialRegister.ll
+++ b/test/CodeGen/Generic/2004-05-09-LiveVarPartialRegister.ll
@@ -3,8 +3,8 @@
 @global_long_2 = linkonce global i64 49         ; <i64*> [#uses=1]
 
 define i32 @main() {
-        %l1 = load i64* @global_long_1          ; <i64> [#uses=1]
-        %l2 = load i64* @global_long_2          ; <i64> [#uses=1]
+        %l1 = load i64, i64* @global_long_1          ; <i64> [#uses=1]
+        %l2 = load i64, i64* @global_long_2          ; <i64> [#uses=1]
         %cond = icmp sle i64 %l1, %l2           ; <i1> [#uses=1]
         %cast2 = zext i1 %cond to i32           ; <i32> [#uses=1]
         %RV = sub i32 1, %cast2         ; <i32> [#uses=1]
diff --git a/test/CodeGen/Generic/2005-04-09-GlobalInPHI.ll b/test/CodeGen/Generic/2005-04-09-GlobalInPHI.ll
index 353e411b0887..b54f737b90aa 100644
--- a/test/CodeGen/Generic/2005-04-09-GlobalInPHI.ll
+++ b/test/CodeGen/Generic/2005-04-09-GlobalInPHI.ll
@@ -12,7 +12,7 @@ cond_true:              ; preds = %entry
 
 else.0:         ; preds = %cond_true, %entry
         %tmp.167.1 = phi i32 [ ptrtoint ([17 x i8]* @.str_87 to i32), %entry ], [ 0, %cond_true ]               ; <i32> [#uses=0]
-        call void @Pr( i8* getelementptr ([4 x i8]* @.str_67, i32 0, i32 0), i32 0, i32 0 )
+        call void @Pr( i8* getelementptr ([4 x i8], [4 x i8]* @.str_67, i32 0, i32 0), i32 0, i32 0 )
         ret void
 }
 
diff --git a/test/CodeGen/Generic/2005-12-01-Crash.ll b/test/CodeGen/Generic/2005-12-01-Crash.ll
index a9eeddedc54d..e6ab9d280c73 100644
--- a/test/CodeGen/Generic/2005-12-01-Crash.ll
+++ b/test/CodeGen/Generic/2005-12-01-Crash.ll
@@ -11,7 +11,7 @@
 define void @printArgsNoRet(i32 %a1, float %a2, i8 %a3, double %a4, i8* %a5, i32 %a6, float %a7, i8 %a8, double %a9, i8* %a10, i32 %a11, float %a12, i8 %a13, double %a14, i8* %a15) {
 entry:
 	%tmp17 = sext i8 %a13 to i32		; <i32> [#uses=1]
-	%tmp23 = call i32 (i8*, ...)* @printf( i8* getelementptr ([29 x i8]* @str2, i32 0, i64 0), i32 %a11, double 0.000000e+00, i32 %tmp17, double %a14, i32 0 )		; <i32> [#uses=0]
+	%tmp23 = call i32 (i8*, ...) @printf( i8* getelementptr ([29 x i8], [29 x i8]* @str2, i32 0, i64 0), i32 %a11, double 0.000000e+00, i32 %tmp17, double %a14, i32 0 )		; <i32> [#uses=0]
 	ret void
 }
 
diff --git a/test/CodeGen/Generic/2006-02-12-InsertLibcall.ll b/test/CodeGen/Generic/2006-02-12-InsertLibcall.ll
index 5508272b5551..8a43b6ab2aa5 100644
--- a/test/CodeGen/Generic/2006-02-12-InsertLibcall.ll
+++ b/test/CodeGen/Generic/2006-02-12-InsertLibcall.ll
@@ -42,7 +42,7 @@ then.1.i52:		; preds = %then.0.i40
 	ret void
 
 else.1.i56:		; preds = %then.0.i40
-	%tmp.28.i = load i32* @G		; <i32> [#uses=1]
+	%tmp.28.i = load i32, i32* @G		; <i32> [#uses=1]
 	%tmp.29.i = icmp eq i32 %tmp.28.i, 1		; <i1> [#uses=1]
 	br i1 %tmp.29.i, label %shortcirc_next.i, label %shortcirc_done.i
 
diff --git a/test/CodeGen/Generic/2006-03-01-dagcombineinfloop.ll b/test/CodeGen/Generic/2006-03-01-dagcombineinfloop.ll
index 2a6cc0c9cdd2..554cd2eef581 100644
--- a/test/CodeGen/Generic/2006-03-01-dagcombineinfloop.ll
+++ b/test/CodeGen/Generic/2006-03-01-dagcombineinfloop.ll
@@ -36,16 +36,16 @@ cond_next12:		; preds = %cond_true92
 
 cond_next18:		; preds = %cond_next12, %cond_true
 	%tmp20 = bitcast %struct.tree_node* %tmp2 to %struct.tree_type*		; <%struct.tree_type*> [#uses=1]
-	%tmp21 = getelementptr %struct.tree_type* %tmp20, i32 0, i32 17		; <%struct.tree_node**> [#uses=1]
-	%tmp22 = load %struct.tree_node** %tmp21		; <%struct.tree_node*> [#uses=6]
+	%tmp21 = getelementptr %struct.tree_type, %struct.tree_type* %tmp20, i32 0, i32 17		; <%struct.tree_node**> [#uses=1]
+	%tmp22 = load %struct.tree_node*, %struct.tree_node** %tmp21		; <%struct.tree_node*> [#uses=6]
 	%tmp24 = icmp eq %struct.tree_node* %tmp22, %tmp23		; <i1> [#uses=1]
 	br i1 %tmp24, label %return, label %cond_next28
 
 cond_next28:		; preds = %cond_next18
 	%tmp30 = bitcast %struct.tree_node* %tmp2 to %struct.tree_common*		; <%struct.tree_common*> [#uses=1]
-	%tmp = getelementptr %struct.tree_common* %tmp30, i32 0, i32 2		; <i8*> [#uses=1]
+	%tmp = getelementptr %struct.tree_common, %struct.tree_common* %tmp30, i32 0, i32 2		; <i8*> [#uses=1]
 	%tmp.upgrd.1 = bitcast i8* %tmp to i32*		; <i32*> [#uses=1]
-	%tmp.upgrd.2 = load i32* %tmp.upgrd.1		; <i32> [#uses=1]
+	%tmp.upgrd.2 = load i32, i32* %tmp.upgrd.1		; <i32> [#uses=1]
 	%tmp32 = trunc i32 %tmp.upgrd.2 to i8		; <i8> [#uses=1]
 	%tmp33 = icmp eq i8 %tmp32, 7		; <i1> [#uses=1]
 	br i1 %tmp33, label %cond_true34, label %cond_next84
@@ -69,23 +69,23 @@ cond_next84:		; preds = %cond_next28
 	br i1 %tmp.upgrd.6, label %return, label %cond_true92
 
 cond_true92.preheader:		; preds = %entry
-	%tmp7 = load %struct.tree_node** @void_type_node		; <%struct.tree_node*> [#uses=1]
-	%tmp23 = load %struct.tree_node** @float_type_node		; <%struct.tree_node*> [#uses=1]
-	%tmp39 = load %struct.tree_node** @char_type_node		; <%struct.tree_node*> [#uses=1]
-	%tmp48 = load %struct.tree_node** @signed_char_type_node		; <%struct.tree_node*> [#uses=1]
-	%tmp57 = load %struct.tree_node** @unsigned_char_type_node		; <%struct.tree_node*> [#uses=1]
-	%tmp66 = load %struct.tree_node** @short_integer_type_node		; <%struct.tree_node*> [#uses=1]
-	%tmp75 = load %struct.tree_node** @short_unsigned_type_node		; <%struct.tree_node*> [#uses=1]
+	%tmp7 = load %struct.tree_node*, %struct.tree_node** @void_type_node		; <%struct.tree_node*> [#uses=1]
+	%tmp23 = load %struct.tree_node*, %struct.tree_node** @float_type_node		; <%struct.tree_node*> [#uses=1]
+	%tmp39 = load %struct.tree_node*, %struct.tree_node** @char_type_node		; <%struct.tree_node*> [#uses=1]
+	%tmp48 = load %struct.tree_node*, %struct.tree_node** @signed_char_type_node		; <%struct.tree_node*> [#uses=1]
+	%tmp57 = load %struct.tree_node*, %struct.tree_node** @unsigned_char_type_node		; <%struct.tree_node*> [#uses=1]
+	%tmp66 = load %struct.tree_node*, %struct.tree_node** @short_integer_type_node		; <%struct.tree_node*> [#uses=1]
+	%tmp75 = load %struct.tree_node*, %struct.tree_node** @short_unsigned_type_node		; <%struct.tree_node*> [#uses=1]
 	br label %cond_true92
 
 cond_true92:		; preds = %cond_true92.preheader, %cond_next84, %cond_true34
 	%t.0.0 = phi %struct.tree_node* [ %parms, %cond_true92.preheader ], [ %tmp6, %cond_true34 ], [ %tmp6, %cond_next84 ]		; <%struct.tree_node*> [#uses=2]
 	%tmp.upgrd.4 = bitcast %struct.tree_node* %t.0.0 to %struct.tree_list*		; <%struct.tree_list*> [#uses=1]
-	%tmp.upgrd.5 = getelementptr %struct.tree_list* %tmp.upgrd.4, i32 0, i32 2		; <%struct.tree_node**> [#uses=1]
-	%tmp2 = load %struct.tree_node** %tmp.upgrd.5		; <%struct.tree_node*> [#uses=5]
+	%tmp.upgrd.5 = getelementptr %struct.tree_list, %struct.tree_list* %tmp.upgrd.4, i32 0, i32 2		; <%struct.tree_node**> [#uses=1]
+	%tmp2 = load %struct.tree_node*, %struct.tree_node** %tmp.upgrd.5		; <%struct.tree_node*> [#uses=5]
 	%tmp4 = bitcast %struct.tree_node* %t.0.0 to %struct.tree_common*		; <%struct.tree_common*> [#uses=1]
-	%tmp5 = getelementptr %struct.tree_common* %tmp4, i32 0, i32 0		; <%struct.tree_node**> [#uses=1]
-	%tmp6 = load %struct.tree_node** %tmp5		; <%struct.tree_node*> [#uses=3]
+	%tmp5 = getelementptr %struct.tree_common, %struct.tree_common* %tmp4, i32 0, i32 0		; <%struct.tree_node**> [#uses=1]
+	%tmp6 = load %struct.tree_node*, %struct.tree_node** %tmp5		; <%struct.tree_node*> [#uses=3]
 	%tmp.upgrd.6 = icmp eq %struct.tree_node* %tmp6, null		; <i1> [#uses=3]
 	br i1 %tmp.upgrd.6, label %cond_true, label %cond_next12
 
diff --git a/test/CodeGen/Generic/2006-04-26-SetCCAnd.ll b/test/CodeGen/Generic/2006-04-26-SetCCAnd.ll
index 8465b829e29f..f68dc32c5eb5 100644
--- a/test/CodeGen/Generic/2006-04-26-SetCCAnd.ll
+++ b/test/CodeGen/Generic/2006-04-26-SetCCAnd.ll
@@ -22,8 +22,8 @@ else.3:		; preds = %endif.4
 	]
 
 then.10:		; preds = %else.3, %else.3
-	%tmp.112 = load i16* null		; <i16> [#uses=2]
-	%tmp.113 = load i16* @G		; <i16> [#uses=2]
+	%tmp.112 = load i16, i16* null		; <i16> [#uses=2]
+	%tmp.113 = load i16, i16* @G		; <i16> [#uses=2]
 	%tmp.114 = icmp ugt i16 %tmp.112, %tmp.113		; <i1> [#uses=1]
 	%tmp.120 = icmp ult i16 %tmp.112, %tmp.113		; <i1> [#uses=1]
 	%bothcond = and i1 %tmp.114, %tmp.120		; <i1> [#uses=1]
diff --git a/test/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll b/test/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
index 1a9fa9f5de6b..12a40116c59b 100644
--- a/test/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
+++ b/test/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
@@ -9,7 +9,7 @@ declare void @fprintf(i32, ...)
 
 define void @OUTPUT_TABLE(%struct.SYMBOL_TABLE_ENTRY* %SYM_TAB) {
 entry:
-	%tmp11 = getelementptr %struct.SYMBOL_TABLE_ENTRY* %SYM_TAB, i32 0, i32 1, i32 0		; <i8*> [#uses=2]
+	%tmp11 = getelementptr %struct.SYMBOL_TABLE_ENTRY, %struct.SYMBOL_TABLE_ENTRY* %SYM_TAB, i32 0, i32 1, i32 0		; <i8*> [#uses=2]
 	%tmp.i = bitcast i8* %tmp11 to i8*		; <i8*> [#uses=1]
 	br label %bb.i
 
@@ -18,7 +18,7 @@ bb.i:		; preds = %cond_next.i, %entry
 	br i1 false, label %cond_true.i31, label %cond_next.i
 
 cond_true.i31:		; preds = %bb.i
-	call void (i32, ...)* @fprintf( i32 0, i8* %tmp11, i8* null )
+	call void (i32, ...) @fprintf( i32 0, i8* %tmp11, i8* null )
 	ret void
 
 cond_next.i:		; preds = %bb.i
diff --git a/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll b/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll
index bd922b3aa851..80be64c7cf91 100644
--- a/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll
+++ b/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll
@@ -9,17 +9,17 @@ entry:
 	br i1 %tmp22, label %cond_true23, label %cond_next159
 
 cond_true23:		; preds = %entry
-	%tmp138 = getelementptr %struct.cl_perfunc_opts* @cl_pf_opts, i32 0, i32 8		; <i8*> [#uses=1]
+	%tmp138 = getelementptr %struct.cl_perfunc_opts, %struct.cl_perfunc_opts* @cl_pf_opts, i32 0, i32 8		; <i8*> [#uses=1]
 	%tmp138.upgrd.1 = bitcast i8* %tmp138 to i32*		; <i32*> [#uses=2]
-	%tmp139 = load i32* %tmp138.upgrd.1		; <i32> [#uses=1]
+	%tmp139 = load i32, i32* %tmp138.upgrd.1		; <i32> [#uses=1]
 	%tmp140 = shl i32 1, 27		; <i32> [#uses=1]
 	%tmp141 = and i32 %tmp140, 134217728		; <i32> [#uses=1]
 	%tmp142 = and i32 %tmp139, -134217729		; <i32> [#uses=1]
 	%tmp143 = or i32 %tmp142, %tmp141		; <i32> [#uses=1]
 	store i32 %tmp143, i32* %tmp138.upgrd.1
-	%tmp144 = getelementptr %struct.cl_perfunc_opts* @cl_pf_opts, i32 0, i32 8		; <i8*> [#uses=1]
+	%tmp144 = getelementptr %struct.cl_perfunc_opts, %struct.cl_perfunc_opts* @cl_pf_opts, i32 0, i32 8		; <i8*> [#uses=1]
 	%tmp144.upgrd.2 = bitcast i8* %tmp144 to i32*		; <i32*> [#uses=1]
-	%tmp145 = load i32* %tmp144.upgrd.2		; <i32> [#uses=1]
+	%tmp145 = load i32, i32* %tmp144.upgrd.2		; <i32> [#uses=1]
 	%tmp146 = shl i32 %tmp145, 22		; <i32> [#uses=1]
 	%tmp147 = lshr i32 %tmp146, 31		; <i32> [#uses=1]
 	%tmp147.upgrd.3 = trunc i32 %tmp147 to i8		; <i8> [#uses=1]
diff --git a/test/CodeGen/Generic/2006-06-28-SimplifySetCCCrash.ll b/test/CodeGen/Generic/2006-06-28-SimplifySetCCCrash.ll
index c4f2fb0c4726..bdd9787c6ab3 100644
--- a/test/CodeGen/Generic/2006-06-28-SimplifySetCCCrash.ll
+++ b/test/CodeGen/Generic/2006-06-28-SimplifySetCCCrash.ll
@@ -169,7 +169,7 @@ cond_next778:		; preds = %cond_next6.i119
 	br i1 %tmp781, label %cond_next784, label %bb790
 
 cond_next784:		; preds = %cond_next778
-	%tmp785 = load i32* @ix86_cpu		; <i32> [#uses=1]
+	%tmp785 = load i32, i32* @ix86_cpu		; <i32> [#uses=1]
 	%tmp786 = icmp eq i32 %tmp785, 5		; <i1> [#uses=1]
 	br i1 %tmp786, label %UnifiedReturnBlock, label %bb790
 
@@ -208,7 +208,7 @@ bb1419:		; preds = %cond_true.i
 	ret void
 
 bb1648:		; preds = %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i
-	%tmp1650 = load i32* @which_alternative		; <i32> [#uses=1]
+	%tmp1650 = load i32, i32* @which_alternative		; <i32> [#uses=1]
 	switch i32 %tmp1650, label %bb1701 [
 		 i32 0, label %cond_next1675
 		 i32 1, label %cond_next1675
@@ -219,7 +219,7 @@ cond_next1675:		; preds = %bb1648, %bb1648, %bb1648
 	ret void
 
 bb1701:		; preds = %bb1648
-	%tmp1702 = load i32* @which_alternative		; <i32> [#uses=1]
+	%tmp1702 = load i32, i32* @which_alternative		; <i32> [#uses=1]
 	switch i32 %tmp1702, label %bb1808 [
 		 i32 0, label %cond_next1727
 		 i32 1, label %cond_next1727
@@ -237,7 +237,7 @@ cond_next1834:		; preds = %bb1808
 	ret void
 
 bb1876:		; preds = %bb1808
-	%tmp1877signed = load i32* @which_alternative		; <i32> [#uses=4]
+	%tmp1877signed = load i32, i32* @which_alternative		; <i32> [#uses=4]
 	%tmp1877 = bitcast i32 %tmp1877signed to i32		; <i32> [#uses=1]
 	%bothcond699 = icmp ult i32 %tmp1877, 2		; <i1> [#uses=1]
 	%tmp1888 = icmp eq i32 %tmp1877signed, 2		; <i1> [#uses=1]
diff --git a/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll b/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll
index 2dc5c162cd96..0c4a9c452cd9 100644
--- a/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll
+++ b/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll
@@ -78,33 +78,33 @@ cond_true1369.preheader:		; preds = %cond_true1254
 	ret void
 
 bb1567:		; preds = %cond_true1254
-	%tmp1580 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 3)		; <i64> [#uses=1]
-	%tmp1591 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 4)		; <i64> [#uses=1]
+	%tmp1580 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 3)		; <i64> [#uses=1]
+	%tmp1591 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 4)		; <i64> [#uses=1]
 	%tmp1572 = tail call fastcc i32 @FirstOne( )		; <i32> [#uses=5]
-	%tmp1582 = getelementptr [64 x i32]* @bishop_shift_rl45, i32 0, i32 %tmp1572		; <i32*> [#uses=1]
-	%tmp1583 = load i32* %tmp1582		; <i32> [#uses=1]
+	%tmp1582 = getelementptr [64 x i32], [64 x i32]* @bishop_shift_rl45, i32 0, i32 %tmp1572		; <i32*> [#uses=1]
+	%tmp1583 = load i32, i32* %tmp1582		; <i32> [#uses=1]
 	%tmp1583.upgrd.1 = trunc i32 %tmp1583 to i8		; <i8> [#uses=1]
 	%shift.upgrd.2 = zext i8 %tmp1583.upgrd.1 to i64		; <i64> [#uses=1]
 	%tmp1584 = lshr i64 %tmp1580, %shift.upgrd.2		; <i64> [#uses=1]
 	%tmp1584.upgrd.3 = trunc i64 %tmp1584 to i32		; <i32> [#uses=1]
 	%tmp1585 = and i32 %tmp1584.upgrd.3, 255		; <i32> [#uses=1]
 	%gep.upgrd.4 = zext i32 %tmp1585 to i64		; <i64> [#uses=1]
-	%tmp1587 = getelementptr [64 x [256 x i32]]* @bishop_mobility_rl45, i32 0, i32 %tmp1572, i64 %gep.upgrd.4		; <i32*> [#uses=1]
-	%tmp1588 = load i32* %tmp1587		; <i32> [#uses=1]
-	%tmp1593 = getelementptr [64 x i32]* @bishop_shift_rr45, i32 0, i32 %tmp1572		; <i32*> [#uses=1]
-	%tmp1594 = load i32* %tmp1593		; <i32> [#uses=1]
+	%tmp1587 = getelementptr [64 x [256 x i32]], [64 x [256 x i32]]* @bishop_mobility_rl45, i32 0, i32 %tmp1572, i64 %gep.upgrd.4		; <i32*> [#uses=1]
+	%tmp1588 = load i32, i32* %tmp1587		; <i32> [#uses=1]
+	%tmp1593 = getelementptr [64 x i32], [64 x i32]* @bishop_shift_rr45, i32 0, i32 %tmp1572		; <i32*> [#uses=1]
+	%tmp1594 = load i32, i32* %tmp1593		; <i32> [#uses=1]
 	%tmp1594.upgrd.5 = trunc i32 %tmp1594 to i8		; <i8> [#uses=1]
 	%shift.upgrd.6 = zext i8 %tmp1594.upgrd.5 to i64		; <i64> [#uses=1]
 	%tmp1595 = lshr i64 %tmp1591, %shift.upgrd.6		; <i64> [#uses=1]
 	%tmp1595.upgrd.7 = trunc i64 %tmp1595 to i32		; <i32> [#uses=1]
 	%tmp1596 = and i32 %tmp1595.upgrd.7, 255		; <i32> [#uses=1]
 	%gep.upgrd.8 = zext i32 %tmp1596 to i64		; <i64> [#uses=1]
-	%tmp1598 = getelementptr [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8		; <i32*> [#uses=1]
-	%tmp1599 = load i32* %tmp1598		; <i32> [#uses=1]
+	%tmp1598 = getelementptr [64 x [256 x i32]], [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8		; <i32*> [#uses=1]
+	%tmp1599 = load i32, i32* %tmp1598		; <i32> [#uses=1]
 	%tmp1600.neg = sub i32 0, %tmp1588		; <i32> [#uses=1]
 	%tmp1602 = sub i32 %tmp1600.neg, %tmp1599		; <i32> [#uses=1]
-	%tmp1604 = getelementptr [64 x i8]* @black_outpost, i32 0, i32 %tmp1572		; <i8*> [#uses=1]
-	%tmp1605 = load i8* %tmp1604		; <i8> [#uses=1]
+	%tmp1604 = getelementptr [64 x i8], [64 x i8]* @black_outpost, i32 0, i32 %tmp1572		; <i8*> [#uses=1]
+	%tmp1605 = load i8, i8* %tmp1604		; <i8> [#uses=1]
 	%tmp1606 = icmp eq i8 %tmp1605, 0		; <i1> [#uses=1]
 	br i1 %tmp1606, label %cond_next1637, label %cond_true1607
 
diff --git a/test/CodeGen/Generic/2006-11-20-DAGCombineCrash.ll b/test/CodeGen/Generic/2006-11-20-DAGCombineCrash.ll
index 26d0f4f96ae8..40f91b235ab5 100644
--- a/test/CodeGen/Generic/2006-11-20-DAGCombineCrash.ll
+++ b/test/CodeGen/Generic/2006-11-20-DAGCombineCrash.ll
@@ -10,9 +10,9 @@ bb.preheader:		; preds = %entry
 	br i1 false, label %cond_true48, label %cond_next80
 
 cond_true48:		; preds = %bb.preheader
-	%tmp = load i8* null		; <i8> [#uses=1]
+	%tmp = load i8, i8* null		; <i8> [#uses=1]
 	%tmp51 = zext i8 %tmp to i16		; <i16> [#uses=1]
-	%tmp99 = load i8* null		; <i8> [#uses=1]
+	%tmp99 = load i8, i8* null		; <i8> [#uses=1]
 	%tmp54 = bitcast i8 %tmp99 to i8		; <i8> [#uses=1]
 	%tmp54.upgrd.1 = zext i8 %tmp54 to i32		; <i32> [#uses=1]
 	%tmp55 = lshr i32 %tmp54.upgrd.1, 3		; <i32> [#uses=1]
diff --git a/test/CodeGen/Generic/2007-01-15-LoadSelectCycle.ll b/test/CodeGen/Generic/2007-01-15-LoadSelectCycle.ll
index 255b12092a77..aa6793b9c688 100644
--- a/test/CodeGen/Generic/2007-01-15-LoadSelectCycle.ll
+++ b/test/CodeGen/Generic/2007-01-15-LoadSelectCycle.ll
@@ -4,8 +4,8 @@
 declare i1 @foo()
 
 define i32 @test(i32* %A, i32* %B) {
-	%a = load i32* %A
-	%b = load i32* %B
+	%a = load i32, i32* %A
+	%b = load i32, i32* %B
 	%cond = call i1 @foo()
 	%c = select i1 %cond, i32 %a, i32 %b
 	ret i32 %c
diff --git a/test/CodeGen/Generic/2007-05-03-EHTypeInfo.ll b/test/CodeGen/Generic/2007-05-03-EHTypeInfo.ll
index 81347a23b864..7d77a2eed3b3 100644
--- a/test/CodeGen/Generic/2007-05-03-EHTypeInfo.ll
+++ b/test/CodeGen/Generic/2007-05-03-EHTypeInfo.ll
@@ -5,8 +5,8 @@
 
 define void @typeinfo() {
 entry:
-	%eh_typeid = tail call i32 @llvm.eh.typeid.for.i32( i8* getelementptr (%struct.exception* @program_error, i32 0, i32 0) )		; <i32> [#uses=0]
+	%eh_typeid = tail call i32 @llvm.eh.typeid.for( i8* getelementptr (%struct.exception, %struct.exception* @program_error, i32 0, i32 0) )		; <i32> [#uses=0]
 	ret void
 }
 
-declare i32 @llvm.eh.typeid.for.i32(i8*)
+declare i32 @llvm.eh.typeid.for(i8*)
diff --git a/test/CodeGen/Generic/2008-01-25-dag-combine-mul.ll b/test/CodeGen/Generic/2008-01-25-dag-combine-mul.ll
index 314bb05c6784..4558f09c4b96 100644
--- a/test/CodeGen/Generic/2008-01-25-dag-combine-mul.ll
+++ b/test/CodeGen/Generic/2008-01-25-dag-combine-mul.ll
@@ -4,24 +4,24 @@
 define i32 @f(i16* %pc) {
 entry:
 	%acc = alloca i64, align 8		; <i64*> [#uses=4]
-	%tmp97 = load i64* %acc, align 8		; <i64> [#uses=1]
+	%tmp97 = load i64, i64* %acc, align 8		; <i64> [#uses=1]
 	%tmp98 = and i64 %tmp97, 4294967295		; <i64> [#uses=1]
-	%tmp99 = load i64* null, align 8		; <i64> [#uses=1]
+	%tmp99 = load i64, i64* null, align 8		; <i64> [#uses=1]
 	%tmp100 = and i64 %tmp99, 4294967295		; <i64> [#uses=1]
 	%tmp101 = mul i64 %tmp98, %tmp100		; <i64> [#uses=1]
 	%tmp103 = lshr i64 %tmp101, 0		; <i64> [#uses=1]
-	%tmp104 = load i64* %acc, align 8		; <i64> [#uses=1]
+	%tmp104 = load i64, i64* %acc, align 8		; <i64> [#uses=1]
 	%.cast105 = zext i32 32 to i64		; <i64> [#uses=1]
 	%tmp106 = lshr i64 %tmp104, %.cast105		; <i64> [#uses=1]
-	%tmp107 = load i64* null, align 8		; <i64> [#uses=1]
+	%tmp107 = load i64, i64* null, align 8		; <i64> [#uses=1]
 	%tmp108 = and i64 %tmp107, 4294967295		; <i64> [#uses=1]
 	%tmp109 = mul i64 %tmp106, %tmp108		; <i64> [#uses=1]
 	%tmp112 = add i64 %tmp109, 0		; <i64> [#uses=1]
 	%tmp116 = add i64 %tmp112, 0		; <i64> [#uses=1]
 	%tmp117 = add i64 %tmp103, %tmp116		; <i64> [#uses=1]
-	%tmp118 = load i64* %acc, align 8		; <i64> [#uses=1]
+	%tmp118 = load i64, i64* %acc, align 8		; <i64> [#uses=1]
 	%tmp120 = lshr i64 %tmp118, 0		; <i64> [#uses=1]
-	%tmp121 = load i64* null, align 8		; <i64> [#uses=1]
+	%tmp121 = load i64, i64* null, align 8		; <i64> [#uses=1]
 	%tmp123 = lshr i64 %tmp121, 0		; <i64> [#uses=1]
 	%tmp124 = mul i64 %tmp120, %tmp123		; <i64> [#uses=1]
 	%tmp126 = shl i64 %tmp124, 0		; <i64> [#uses=1]
diff --git a/test/CodeGen/Generic/2008-01-30-LoadCrash.ll b/test/CodeGen/Generic/2008-01-30-LoadCrash.ll
index 70c3aaabedc1..f24d1bcad5f7 100644
--- a/test/CodeGen/Generic/2008-01-30-LoadCrash.ll
+++ b/test/CodeGen/Generic/2008-01-30-LoadCrash.ll
@@ -8,12 +8,12 @@ bb20:
 
 bb41:		; preds = %bb20
 	%tmp8182 = trunc i64 %tmp42.rle to i32		; <i32> [#uses=1]
-	%tmp83 = getelementptr [63 x i8]* @letters.3100, i32 0, i32 %tmp8182		; <i8*> [#uses=1]
-	%tmp84 = load i8* %tmp83, align 1		; <i8> [#uses=1]
+	%tmp83 = getelementptr [63 x i8], [63 x i8]* @letters.3100, i32 0, i32 %tmp8182		; <i8*> [#uses=1]
+	%tmp84 = load i8, i8* %tmp83, align 1		; <i8> [#uses=1]
 	store i8 %tmp84, i8* null, align 1
 	%tmp90 = urem i64 %tmp42.rle, 62		; <i64> [#uses=1]
 	%tmp9091 = trunc i64 %tmp90 to i32		; <i32> [#uses=1]
-	%tmp92 = getelementptr [63 x i8]* @letters.3100, i32 0, i32 %tmp9091		; <i8*> [#uses=1]
+	%tmp92 = getelementptr [63 x i8], [63 x i8]* @letters.3100, i32 0, i32 %tmp9091		; <i8*> [#uses=1]
 	store i8* %tmp92, i8** null, align 1
 	ret i32 -1
 }
diff --git a/test/CodeGen/Generic/2008-02-04-Ctlz.ll b/test/CodeGen/Generic/2008-02-04-Ctlz.ll
index 9f102066f2bb..3244e5c6f4ce 100644
--- a/test/CodeGen/Generic/2008-02-04-Ctlz.ll
+++ b/test/CodeGen/Generic/2008-02-04-Ctlz.ll
@@ -10,7 +10,7 @@ entry:
 	%tmp38 = trunc i64 %tmp37 to i32		; <i32>:0 [#uses=1]
 	%tmp48 = trunc i64 %tmp47 to i32		; <i32>:0 [#uses=1]
 	%tmp58 = trunc i64 %tmp57 to i32		; <i32>:0 [#uses=1]
-	%tmp40 = tail call i32 (i8*, ...)* @printf( i8* noalias  getelementptr ([14 x i8]* @.str, i32 0, i32 0), i64 %arg, i32 %tmp38, i32 %tmp48, i32 %tmp58 ) nounwind 		; <i32> [#uses=0]
+	%tmp40 = tail call i32 (i8*, ...) @printf( i8* noalias  getelementptr ([14 x i8], [14 x i8]* @.str, i32 0, i32 0), i64 %arg, i32 %tmp38, i32 %tmp48, i32 %tmp58 ) nounwind 		; <i32> [#uses=0]
 	ret i32 0
 }
 
diff --git a/test/CodeGen/Generic/2008-02-20-MatchingMem.ll b/test/CodeGen/Generic/2008-02-20-MatchingMem.ll
index 5ddb515bb75a..20f3dcc2971d 100644
--- a/test/CodeGen/Generic/2008-02-20-MatchingMem.ll
+++ b/test/CodeGen/Generic/2008-02-20-MatchingMem.ll
@@ -1,9 +1,8 @@
 ; RUN: llc -no-integrated-as < %s
 ; PR1133
-; XFAIL: hexagon
 define void @test(i32* %X) nounwind  {
 entry:
-	%tmp1 = getelementptr i32* %X, i32 10		; <i32*> [#uses=2]
+	%tmp1 = getelementptr i32, i32* %X, i32 10		; <i32*> [#uses=2]
 	tail call void asm sideeffect " $0 $1 ", "=*im,*im,~{memory}"( i32* %tmp1, i32* %tmp1 ) nounwind 
 	ret void
 }
diff --git a/test/CodeGen/Generic/2008-02-25-NegateZero.ll b/test/CodeGen/Generic/2008-02-25-NegateZero.ll
index 97db667dc13a..14800ce5b458 100644
--- a/test/CodeGen/Generic/2008-02-25-NegateZero.ll
+++ b/test/CodeGen/Generic/2008-02-25-NegateZero.ll
@@ -3,11 +3,11 @@
 
 define void @test() {
 entry:
-	%tmp98 = load float* null, align 4		; <float> [#uses=1]
-	%tmp106 = load float* null, align 4		; <float> [#uses=1]
+	%tmp98 = load float, float* null, align 4		; <float> [#uses=1]
+	%tmp106 = load float, float* null, align 4		; <float> [#uses=1]
 	%tmp113 = fadd float %tmp98, %tmp106		; <float> [#uses=1]
 	%tmp119 = fsub float %tmp113, 0.000000e+00		; <float> [#uses=1]
-	call void (i32, ...)* @foo( i32 0, float 0.000000e+00, float %tmp119 ) nounwind 
+	call void (i32, ...) @foo( i32 0, float 0.000000e+00, float %tmp119 ) nounwind 
 	ret void
 }
 
diff --git a/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll b/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll
index 00ca8c756b42..01923dde2874 100644
--- a/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll
+++ b/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll
@@ -2,4 +2,4 @@
 ; PR2603
         %struct.A = type { i8 }
         %struct.B = type { i8, [1 x i8] }
-@Foo = constant %struct.A { i8 ptrtoint (i8* getelementptr ([1 x i8]* inttoptr (i32 17 to [1 x i8]*), i32 0, i32 -16) to i8) }          ; <%struct.A*> [#uses=0]
+@Foo = constant %struct.A { i8 ptrtoint (i8* getelementptr ([1 x i8], [1 x i8]* inttoptr (i32 17 to [1 x i8]*), i32 0, i32 -16) to i8) }          ; <%struct.A*> [#uses=0]
diff --git a/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll b/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll
index 45b561affffa..f614db00da48 100644
--- a/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll
+++ b/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll
@@ -1,10 +1,14 @@
-; RUN: llc < %s -soft-float
+; RUN: llc < %s
 ; PR3899
 
 @m = external global <2 x double>
 
-define double @vector_ex() nounwind {
-       %v = load <2 x double>* @m
+define double @vector_ex() nounwind #0 {
+       %v = load <2 x double>, <2 x double>* @m
        %x = extractelement <2 x double> %v, i32 1
        ret double %x
 }
+
+; Soft-float attribute so that targets that pay attention to soft float will
+; make floating point types illegal and we'll exercise the legalizer code.
+attributes #0 = { "use-soft-float" = "true" }
diff --git a/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll b/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
index b62f811e8d16..78f97eea77d0 100644
--- a/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
+++ b/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
@@ -5,7 +5,7 @@
 
 define i32 @test(i128* %P) nounwind {
 entry:
-	%tmp48 = load i128* %P
+	%tmp48 = load i128, i128* %P
 	%and49 = and i128 %tmp48, 18446744073709551616		; <i128> [#uses=1]
 	%tobool = icmp ne i128 %and49, 0		; <i1> [#uses=1]
 	br i1 %tobool, label %if.then50, label %if.end61
@@ -19,7 +19,7 @@ if.end61:		; preds = %if.then50, %if.then20, %entry
 
 define i32 @test2(i320* %P) nounwind {
 entry:
-	%tmp48 = load i320* %P
+	%tmp48 = load i320, i320* %P
 	%and49 = and i320 %tmp48, 25108406941546723055343157692830665664409421777856138051584
 	%tobool = icmp ne i320 %and49, 0		; <i1> [#uses=1]
 	br i1 %tobool, label %if.then50, label %if.end61
diff --git a/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll b/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll
index cd446d57d8a5..5cc48c212c40 100644
--- a/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll
+++ b/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll
@@ -5,8 +5,8 @@
 
 define void @f(i256* nocapture %a, i256* nocapture %b, i256* nocapture %cc, i256* nocapture %dd) nounwind uwtable noinline ssp {
 entry:
-  %c = load i256* %cc
-  %d = load i256* %dd
+  %c = load i256, i256* %cc
+  %d = load i256, i256* %dd
   %add = add nsw i256 %c, %d
   store i256 %add, i256* %a, align 8
   %or = or i256 %c, 1606938044258990275541962092341162602522202993782792835301376
diff --git a/test/CodeGen/Generic/2012-06-08-APIntCrash.ll b/test/CodeGen/Generic/2012-06-08-APIntCrash.ll
index 2c096bf42182..88ca9369ea46 100644
--- a/test/CodeGen/Generic/2012-06-08-APIntCrash.ll
+++ b/test/CodeGen/Generic/2012-06-08-APIntCrash.ll
@@ -2,7 +2,7 @@
 
 define void @test1(<8 x i32>* %ptr)
 {
-	%1 = load <8 x i32>* %ptr, align 32
+	%1 = load <8 x i32>, <8 x i32>* %ptr, align 32
 	%2 = and <8 x i32> %1, <i32 0, i32 0, i32 0, i32 -1, i32 0, i32 0, i32 0, i32 -1>
 	store <8 x i32> %2, <8 x i32>* %ptr, align 16
 	ret void
diff --git a/test/CodeGen/Generic/2014-02-05-OpaqueConstants.ll b/test/CodeGen/Generic/2014-02-05-OpaqueConstants.ll
index 5c1cd0532511..1497bbb0c970 100644
--- a/test/CodeGen/Generic/2014-02-05-OpaqueConstants.ll
+++ b/test/CodeGen/Generic/2014-02-05-OpaqueConstants.ll
@@ -9,11 +9,11 @@
 ; Function Attrs: nounwind ssp uwtable
 define void @fn() {
   store i32* inttoptr (i64 68719476735 to i32*), i32** @a, align 8
-  %1 = load i32* @c, align 4
+  %1 = load i32, i32* @c, align 4
   %2 = sext i32 %1 to i64
   %3 = lshr i64 %2, 12
   %4 = and i64 %3, 68719476735
-  %5 = getelementptr inbounds i32* null, i64 %4
+  %5 = getelementptr inbounds i32, i32* null, i64 %4
   store i32* %5, i32** @b, align 8
   ret void
 }
diff --git a/test/CodeGen/Generic/APIntLoadStore.ll b/test/CodeGen/Generic/APIntLoadStore.ll
index 7c71a33fc3fd..f8d22f5b9122 100644
--- a/test/CodeGen/Generic/APIntLoadStore.ll
+++ b/test/CodeGen/Generic/APIntLoadStore.ll
@@ -513,1537 +513,1537 @@
 @i256_s = external global i256		; <i256*> [#uses=1]
 
 define void @i1_ls() nounwind  {
-	%tmp = load i1* @i1_l		; <i1> [#uses=1]
+	%tmp = load i1, i1* @i1_l		; <i1> [#uses=1]
 	store i1 %tmp, i1* @i1_s
 	ret void
 }
 
 define void @i2_ls() nounwind  {
-	%tmp = load i2* @i2_l		; <i2> [#uses=1]
+	%tmp = load i2, i2* @i2_l		; <i2> [#uses=1]
 	store i2 %tmp, i2* @i2_s
 	ret void
 }
 
 define void @i3_ls() nounwind  {
-	%tmp = load i3* @i3_l		; <i3> [#uses=1]
+	%tmp = load i3, i3* @i3_l		; <i3> [#uses=1]
 	store i3 %tmp, i3* @i3_s
 	ret void
 }
 
 define void @i4_ls() nounwind  {
-	%tmp = load i4* @i4_l		; <i4> [#uses=1]
+	%tmp = load i4, i4* @i4_l		; <i4> [#uses=1]
 	store i4 %tmp, i4* @i4_s
 	ret void
 }
 
 define void @i5_ls() nounwind  {
-	%tmp = load i5* @i5_l		; <i5> [#uses=1]
+	%tmp = load i5, i5* @i5_l		; <i5> [#uses=1]
 	store i5 %tmp, i5* @i5_s
 	ret void
 }
 
 define void @i6_ls() nounwind  {
-	%tmp = load i6* @i6_l		; <i6> [#uses=1]
+	%tmp = load i6, i6* @i6_l		; <i6> [#uses=1]
 	store i6 %tmp, i6* @i6_s
 	ret void
 }
 
 define void @i7_ls() nounwind  {
-	%tmp = load i7* @i7_l		; <i7> [#uses=1]
+	%tmp = load i7, i7* @i7_l		; <i7> [#uses=1]
 	store i7 %tmp, i7* @i7_s
 	ret void
 }
 
 define void @i8_ls() nounwind  {
-	%tmp = load i8* @i8_l		; <i8> [#uses=1]
+	%tmp = load i8, i8* @i8_l		; <i8> [#uses=1]
 	store i8 %tmp, i8* @i8_s
 	ret void
 }
 
 define void @i9_ls() nounwind  {
-	%tmp = load i9* @i9_l		; <i9> [#uses=1]
+	%tmp = load i9, i9* @i9_l		; <i9> [#uses=1]
 	store i9 %tmp, i9* @i9_s
 	ret void
 }
 
 define void @i10_ls() nounwind  {
-	%tmp = load i10* @i10_l		; <i10> [#uses=1]
+	%tmp = load i10, i10* @i10_l		; <i10> [#uses=1]
 	store i10 %tmp, i10* @i10_s
 	ret void
 }
 
 define void @i11_ls() nounwind  {
-	%tmp = load i11* @i11_l		; <i11> [#uses=1]
+	%tmp = load i11, i11* @i11_l		; <i11> [#uses=1]
 	store i11 %tmp, i11* @i11_s
 	ret void
 }
 
 define void @i12_ls() nounwind  {
-	%tmp = load i12* @i12_l		; <i12> [#uses=1]
+	%tmp = load i12, i12* @i12_l		; <i12> [#uses=1]
 	store i12 %tmp, i12* @i12_s
 	ret void
 }
 
 define void @i13_ls() nounwind  {
-	%tmp = load i13* @i13_l		; <i13> [#uses=1]
+	%tmp = load i13, i13* @i13_l		; <i13> [#uses=1]
 	store i13 %tmp, i13* @i13_s
 	ret void
 }
 
 define void @i14_ls() nounwind  {
-	%tmp = load i14* @i14_l		; <i14> [#uses=1]
+	%tmp = load i14, i14* @i14_l		; <i14> [#uses=1]
 	store i14 %tmp, i14* @i14_s
 	ret void
 }
 
 define void @i15_ls() nounwind  {
-	%tmp = load i15* @i15_l		; <i15> [#uses=1]
+	%tmp = load i15, i15* @i15_l		; <i15> [#uses=1]
 	store i15 %tmp, i15* @i15_s
 	ret void
 }
 
 define void @i16_ls() nounwind  {
-	%tmp = load i16* @i16_l		; <i16> [#uses=1]
+	%tmp = load i16, i16* @i16_l		; <i16> [#uses=1]
 	store i16 %tmp, i16* @i16_s
 	ret void
 }
 
 define void @i17_ls() nounwind  {
-	%tmp = load i17* @i17_l		; <i17> [#uses=1]
+	%tmp = load i17, i17* @i17_l		; <i17> [#uses=1]
 	store i17 %tmp, i17* @i17_s
 	ret void
 }
 
 define void @i18_ls() nounwind  {
-	%tmp = load i18* @i18_l		; <i18> [#uses=1]
+	%tmp = load i18, i18* @i18_l		; <i18> [#uses=1]
 	store i18 %tmp, i18* @i18_s
 	ret void
 }
 
 define void @i19_ls() nounwind  {
-	%tmp = load i19* @i19_l		; <i19> [#uses=1]
+	%tmp = load i19, i19* @i19_l		; <i19> [#uses=1]
 	store i19 %tmp, i19* @i19_s
 	ret void
 }
 
 define void @i20_ls() nounwind  {
-	%tmp = load i20* @i20_l		; <i20> [#uses=1]
+	%tmp = load i20, i20* @i20_l		; <i20> [#uses=1]
 	store i20 %tmp, i20* @i20_s
 	ret void
 }
 
 define void @i21_ls() nounwind  {
-	%tmp = load i21* @i21_l		; <i21> [#uses=1]
+	%tmp = load i21, i21* @i21_l		; <i21> [#uses=1]
 	store i21 %tmp, i21* @i21_s
 	ret void
 }
 
 define void @i22_ls() nounwind  {
-	%tmp = load i22* @i22_l		; <i22> [#uses=1]
+	%tmp = load i22, i22* @i22_l		; <i22> [#uses=1]
 	store i22 %tmp, i22* @i22_s
 	ret void
 }
 
 define void @i23_ls() nounwind  {
-	%tmp = load i23* @i23_l		; <i23> [#uses=1]
+	%tmp = load i23, i23* @i23_l		; <i23> [#uses=1]
 	store i23 %tmp, i23* @i23_s
 	ret void
 }
 
 define void @i24_ls() nounwind  {
-	%tmp = load i24* @i24_l		; <i24> [#uses=1]
+	%tmp = load i24, i24* @i24_l		; <i24> [#uses=1]
 	store i24 %tmp, i24* @i24_s
 	ret void
 }
 
 define void @i25_ls() nounwind  {
-	%tmp = load i25* @i25_l		; <i25> [#uses=1]
+	%tmp = load i25, i25* @i25_l		; <i25> [#uses=1]
 	store i25 %tmp, i25* @i25_s
 	ret void
 }
 
 define void @i26_ls() nounwind  {
-	%tmp = load i26* @i26_l		; <i26> [#uses=1]
+	%tmp = load i26, i26* @i26_l		; <i26> [#uses=1]
 	store i26 %tmp, i26* @i26_s
 	ret void
 }
 
 define void @i27_ls() nounwind  {
-	%tmp = load i27* @i27_l		; <i27> [#uses=1]
+	%tmp = load i27, i27* @i27_l		; <i27> [#uses=1]
 	store i27 %tmp, i27* @i27_s
 	ret void
 }
 
 define void @i28_ls() nounwind  {
-	%tmp = load i28* @i28_l		; <i28> [#uses=1]
+	%tmp = load i28, i28* @i28_l		; <i28> [#uses=1]
 	store i28 %tmp, i28* @i28_s
 	ret void
 }
 
 define void @i29_ls() nounwind  {
-	%tmp = load i29* @i29_l		; <i29> [#uses=1]
+	%tmp = load i29, i29* @i29_l		; <i29> [#uses=1]
 	store i29 %tmp, i29* @i29_s
 	ret void
 }
 
 define void @i30_ls() nounwind  {
-	%tmp = load i30* @i30_l		; <i30> [#uses=1]
+	%tmp = load i30, i30* @i30_l		; <i30> [#uses=1]
 	store i30 %tmp, i30* @i30_s
 	ret void
 }
 
 define void @i31_ls() nounwind  {
-	%tmp = load i31* @i31_l		; <i31> [#uses=1]
+	%tmp = load i31, i31* @i31_l		; <i31> [#uses=1]
 	store i31 %tmp, i31* @i31_s
 	ret void
 }
 
 define void @i32_ls() nounwind  {
-	%tmp = load i32* @i32_l		; <i32> [#uses=1]
+	%tmp = load i32, i32* @i32_l		; <i32> [#uses=1]
 	store i32 %tmp, i32* @i32_s
 	ret void
 }
 
 define void @i33_ls() nounwind  {
-	%tmp = load i33* @i33_l		; <i33> [#uses=1]
+	%tmp = load i33, i33* @i33_l		; <i33> [#uses=1]
 	store i33 %tmp, i33* @i33_s
 	ret void
 }
 
 define void @i34_ls() nounwind  {
-	%tmp = load i34* @i34_l		; <i34> [#uses=1]
+	%tmp = load i34, i34* @i34_l		; <i34> [#uses=1]
 	store i34 %tmp, i34* @i34_s
 	ret void
 }
 
 define void @i35_ls() nounwind  {
-	%tmp = load i35* @i35_l		; <i35> [#uses=1]
+	%tmp = load i35, i35* @i35_l		; <i35> [#uses=1]
 	store i35 %tmp, i35* @i35_s
 	ret void
 }
 
 define void @i36_ls() nounwind  {
-	%tmp = load i36* @i36_l		; <i36> [#uses=1]
+	%tmp = load i36, i36* @i36_l		; <i36> [#uses=1]
 	store i36 %tmp, i36* @i36_s
 	ret void
 }
 
 define void @i37_ls() nounwind  {
-	%tmp = load i37* @i37_l		; <i37> [#uses=1]
+	%tmp = load i37, i37* @i37_l		; <i37> [#uses=1]
 	store i37 %tmp, i37* @i37_s
 	ret void
 }
 
 define void @i38_ls() nounwind  {
-	%tmp = load i38* @i38_l		; <i38> [#uses=1]
+	%tmp = load i38, i38* @i38_l		; <i38> [#uses=1]
 	store i38 %tmp, i38* @i38_s
 	ret void
 }
 
 define void @i39_ls() nounwind  {
-	%tmp = load i39* @i39_l		; <i39> [#uses=1]
+	%tmp = load i39, i39* @i39_l		; <i39> [#uses=1]
 	store i39 %tmp, i39* @i39_s
 	ret void
 }
 
 define void @i40_ls() nounwind  {
-	%tmp = load i40* @i40_l		; <i40> [#uses=1]
+	%tmp = load i40, i40* @i40_l		; <i40> [#uses=1]
 	store i40 %tmp, i40* @i40_s
 	ret void
 }
 
 define void @i41_ls() nounwind  {
-	%tmp = load i41* @i41_l		; <i41> [#uses=1]
+	%tmp = load i41, i41* @i41_l		; <i41> [#uses=1]
 	store i41 %tmp, i41* @i41_s
 	ret void
 }
 
 define void @i42_ls() nounwind  {
-	%tmp = load i42* @i42_l		; <i42> [#uses=1]
+	%tmp = load i42, i42* @i42_l		; <i42> [#uses=1]
 	store i42 %tmp, i42* @i42_s
 	ret void
 }
 
 define void @i43_ls() nounwind  {
-	%tmp = load i43* @i43_l		; <i43> [#uses=1]
+	%tmp = load i43, i43* @i43_l		; <i43> [#uses=1]
 	store i43 %tmp, i43* @i43_s
 	ret void
 }
 
 define void @i44_ls() nounwind  {
-	%tmp = load i44* @i44_l		; <i44> [#uses=1]
+	%tmp = load i44, i44* @i44_l		; <i44> [#uses=1]
 	store i44 %tmp, i44* @i44_s
 	ret void
 }
 
 define void @i45_ls() nounwind  {
-	%tmp = load i45* @i45_l		; <i45> [#uses=1]
+	%tmp = load i45, i45* @i45_l		; <i45> [#uses=1]
 	store i45 %tmp, i45* @i45_s
 	ret void
 }
 
 define void @i46_ls() nounwind  {
-	%tmp = load i46* @i46_l		; <i46> [#uses=1]
+	%tmp = load i46, i46* @i46_l		; <i46> [#uses=1]
 	store i46 %tmp, i46* @i46_s
 	ret void
 }
 
 define void @i47_ls() nounwind  {
-	%tmp = load i47* @i47_l		; <i47> [#uses=1]
+	%tmp = load i47, i47* @i47_l		; <i47> [#uses=1]
 	store i47 %tmp, i47* @i47_s
 	ret void
 }
 
 define void @i48_ls() nounwind  {
-	%tmp = load i48* @i48_l		; <i48> [#uses=1]
+	%tmp = load i48, i48* @i48_l		; <i48> [#uses=1]
 	store i48 %tmp, i48* @i48_s
 	ret void
 }
 
 define void @i49_ls() nounwind  {
-	%tmp = load i49* @i49_l		; <i49> [#uses=1]
+	%tmp = load i49, i49* @i49_l		; <i49> [#uses=1]
 	store i49 %tmp, i49* @i49_s
 	ret void
 }
 
 define void @i50_ls() nounwind  {
-	%tmp = load i50* @i50_l		; <i50> [#uses=1]
+	%tmp = load i50, i50* @i50_l		; <i50> [#uses=1]
 	store i50 %tmp, i50* @i50_s
 	ret void
 }
 
 define void @i51_ls() nounwind  {
-	%tmp = load i51* @i51_l		; <i51> [#uses=1]
+	%tmp = load i51, i51* @i51_l		; <i51> [#uses=1]
 	store i51 %tmp, i51* @i51_s
 	ret void
 }
 
 define void @i52_ls() nounwind  {
-	%tmp = load i52* @i52_l		; <i52> [#uses=1]
+	%tmp = load i52, i52* @i52_l		; <i52> [#uses=1]
 	store i52 %tmp, i52* @i52_s
 	ret void
 }
 
 define void @i53_ls() nounwind  {
-	%tmp = load i53* @i53_l		; <i53> [#uses=1]
+	%tmp = load i53, i53* @i53_l		; <i53> [#uses=1]
 	store i53 %tmp, i53* @i53_s
 	ret void
 }
 
 define void @i54_ls() nounwind  {
-	%tmp = load i54* @i54_l		; <i54> [#uses=1]
+	%tmp = load i54, i54* @i54_l		; <i54> [#uses=1]
 	store i54 %tmp, i54* @i54_s
 	ret void
 }
 
 define void @i55_ls() nounwind  {
-	%tmp = load i55* @i55_l		; <i55> [#uses=1]
+	%tmp = load i55, i55* @i55_l		; <i55> [#uses=1]
 	store i55 %tmp, i55* @i55_s
 	ret void
 }
 
 define void @i56_ls() nounwind  {
-	%tmp = load i56* @i56_l		; <i56> [#uses=1]
+	%tmp = load i56, i56* @i56_l		; <i56> [#uses=1]
 	store i56 %tmp, i56* @i56_s
 	ret void
 }
 
 define void @i57_ls() nounwind  {
-	%tmp = load i57* @i57_l		; <i57> [#uses=1]
+	%tmp = load i57, i57* @i57_l		; <i57> [#uses=1]
 	store i57 %tmp, i57* @i57_s
 	ret void
 }
 
 define void @i58_ls() nounwind  {
-	%tmp = load i58* @i58_l		; <i58> [#uses=1]
+	%tmp = load i58, i58* @i58_l		; <i58> [#uses=1]
 	store i58 %tmp, i58* @i58_s
 	ret void
 }
 
 define void @i59_ls() nounwind  {
-	%tmp = load i59* @i59_l		; <i59> [#uses=1]
+	%tmp = load i59, i59* @i59_l		; <i59> [#uses=1]
 	store i59 %tmp, i59* @i59_s
 	ret void
 }
 
 define void @i60_ls() nounwind  {
-	%tmp = load i60* @i60_l		; <i60> [#uses=1]
+	%tmp = load i60, i60* @i60_l		; <i60> [#uses=1]
 	store i60 %tmp, i60* @i60_s
 	ret void
 }
 
 define void @i61_ls() nounwind  {
-	%tmp = load i61* @i61_l		; <i61> [#uses=1]
+	%tmp = load i61, i61* @i61_l		; <i61> [#uses=1]
 	store i61 %tmp, i61* @i61_s
 	ret void
 }
 
 define void @i62_ls() nounwind  {
-	%tmp = load i62* @i62_l		; <i62> [#uses=1]
+	%tmp = load i62, i62* @i62_l		; <i62> [#uses=1]
 	store i62 %tmp, i62* @i62_s
 	ret void
 }
 
 define void @i63_ls() nounwind  {
-	%tmp = load i63* @i63_l		; <i63> [#uses=1]
+	%tmp = load i63, i63* @i63_l		; <i63> [#uses=1]
 	store i63 %tmp, i63* @i63_s
 	ret void
 }
 
 define void @i64_ls() nounwind  {
-	%tmp = load i64* @i64_l		; <i64> [#uses=1]
+	%tmp = load i64, i64* @i64_l		; <i64> [#uses=1]
 	store i64 %tmp, i64* @i64_s
 	ret void
 }
 
 define void @i65_ls() nounwind  {
-	%tmp = load i65* @i65_l		; <i65> [#uses=1]
+	%tmp = load i65, i65* @i65_l		; <i65> [#uses=1]
 	store i65 %tmp, i65* @i65_s
 	ret void
 }
 
 define void @i66_ls() nounwind  {
-	%tmp = load i66* @i66_l		; <i66> [#uses=1]
+	%tmp = load i66, i66* @i66_l		; <i66> [#uses=1]
 	store i66 %tmp, i66* @i66_s
 	ret void
 }
 
 define void @i67_ls() nounwind  {
-	%tmp = load i67* @i67_l		; <i67> [#uses=1]
+	%tmp = load i67, i67* @i67_l		; <i67> [#uses=1]
 	store i67 %tmp, i67* @i67_s
 	ret void
 }
 
 define void @i68_ls() nounwind  {
-	%tmp = load i68* @i68_l		; <i68> [#uses=1]
+	%tmp = load i68, i68* @i68_l		; <i68> [#uses=1]
 	store i68 %tmp, i68* @i68_s
 	ret void
 }
 
 define void @i69_ls() nounwind  {
-	%tmp = load i69* @i69_l		; <i69> [#uses=1]
+	%tmp = load i69, i69* @i69_l		; <i69> [#uses=1]
 	store i69 %tmp, i69* @i69_s
 	ret void
 }
 
 define void @i70_ls() nounwind  {
-	%tmp = load i70* @i70_l		; <i70> [#uses=1]
+	%tmp = load i70, i70* @i70_l		; <i70> [#uses=1]
 	store i70 %tmp, i70* @i70_s
 	ret void
 }
 
 define void @i71_ls() nounwind  {
-	%tmp = load i71* @i71_l		; <i71> [#uses=1]
+	%tmp = load i71, i71* @i71_l		; <i71> [#uses=1]
 	store i71 %tmp, i71* @i71_s
 	ret void
 }
 
 define void @i72_ls() nounwind  {
-	%tmp = load i72* @i72_l		; <i72> [#uses=1]
+	%tmp = load i72, i72* @i72_l		; <i72> [#uses=1]
 	store i72 %tmp, i72* @i72_s
 	ret void
 }
 
 define void @i73_ls() nounwind  {
-	%tmp = load i73* @i73_l		; <i73> [#uses=1]
+	%tmp = load i73, i73* @i73_l		; <i73> [#uses=1]
 	store i73 %tmp, i73* @i73_s
 	ret void
 }
 
 define void @i74_ls() nounwind  {
-	%tmp = load i74* @i74_l		; <i74> [#uses=1]
+	%tmp = load i74, i74* @i74_l		; <i74> [#uses=1]
 	store i74 %tmp, i74* @i74_s
 	ret void
 }
 
 define void @i75_ls() nounwind  {
-	%tmp = load i75* @i75_l		; <i75> [#uses=1]
+	%tmp = load i75, i75* @i75_l		; <i75> [#uses=1]
 	store i75 %tmp, i75* @i75_s
 	ret void
 }
 
 define void @i76_ls() nounwind  {
-	%tmp = load i76* @i76_l		; <i76> [#uses=1]
+	%tmp = load i76, i76* @i76_l		; <i76> [#uses=1]
 	store i76 %tmp, i76* @i76_s
 	ret void
 }
 
 define void @i77_ls() nounwind  {
-	%tmp = load i77* @i77_l		; <i77> [#uses=1]
+	%tmp = load i77, i77* @i77_l		; <i77> [#uses=1]
 	store i77 %tmp, i77* @i77_s
 	ret void
 }
 
 define void @i78_ls() nounwind  {
-	%tmp = load i78* @i78_l		; <i78> [#uses=1]
+	%tmp = load i78, i78* @i78_l		; <i78> [#uses=1]
 	store i78 %tmp, i78* @i78_s
 	ret void
 }
 
 define void @i79_ls() nounwind  {
-	%tmp = load i79* @i79_l		; <i79> [#uses=1]
+	%tmp = load i79, i79* @i79_l		; <i79> [#uses=1]
 	store i79 %tmp, i79* @i79_s
 	ret void
 }
 
 define void @i80_ls() nounwind  {
-	%tmp = load i80* @i80_l		; <i80> [#uses=1]
+	%tmp = load i80, i80* @i80_l		; <i80> [#uses=1]
 	store i80 %tmp, i80* @i80_s
 	ret void
 }
 
 define void @i81_ls() nounwind  {
-	%tmp = load i81* @i81_l		; <i81> [#uses=1]
+	%tmp = load i81, i81* @i81_l		; <i81> [#uses=1]
 	store i81 %tmp, i81* @i81_s
 	ret void
 }
 
 define void @i82_ls() nounwind  {
-	%tmp = load i82* @i82_l		; <i82> [#uses=1]
+	%tmp = load i82, i82* @i82_l		; <i82> [#uses=1]
 	store i82 %tmp, i82* @i82_s
 	ret void
 }
 
 define void @i83_ls() nounwind  {
-	%tmp = load i83* @i83_l		; <i83> [#uses=1]
+	%tmp = load i83, i83* @i83_l		; <i83> [#uses=1]
 	store i83 %tmp, i83* @i83_s
 	ret void
 }
 
 define void @i84_ls() nounwind  {
-	%tmp = load i84* @i84_l		; <i84> [#uses=1]
+	%tmp = load i84, i84* @i84_l		; <i84> [#uses=1]
 	store i84 %tmp, i84* @i84_s
 	ret void
 }
 
 define void @i85_ls() nounwind  {
-	%tmp = load i85* @i85_l		; <i85> [#uses=1]
+	%tmp = load i85, i85* @i85_l		; <i85> [#uses=1]
 	store i85 %tmp, i85* @i85_s
 	ret void
 }
 
 define void @i86_ls() nounwind  {
-	%tmp = load i86* @i86_l		; <i86> [#uses=1]
+	%tmp = load i86, i86* @i86_l		; <i86> [#uses=1]
 	store i86 %tmp, i86* @i86_s
 	ret void
 }
 
 define void @i87_ls() nounwind  {
-	%tmp = load i87* @i87_l		; <i87> [#uses=1]
+	%tmp = load i87, i87* @i87_l		; <i87> [#uses=1]
 	store i87 %tmp, i87* @i87_s
 	ret void
 }
 
 define void @i88_ls() nounwind  {
-	%tmp = load i88* @i88_l		; <i88> [#uses=1]
+	%tmp = load i88, i88* @i88_l		; <i88> [#uses=1]
 	store i88 %tmp, i88* @i88_s
 	ret void
 }
 
 define void @i89_ls() nounwind  {
-	%tmp = load i89* @i89_l		; <i89> [#uses=1]
+	%tmp = load i89, i89* @i89_l		; <i89> [#uses=1]
 	store i89 %tmp, i89* @i89_s
 	ret void
 }
 
 define void @i90_ls() nounwind  {
-	%tmp = load i90* @i90_l		; <i90> [#uses=1]
+	%tmp = load i90, i90* @i90_l		; <i90> [#uses=1]
 	store i90 %tmp, i90* @i90_s
 	ret void
 }
 
 define void @i91_ls() nounwind  {
-	%tmp = load i91* @i91_l		; <i91> [#uses=1]
+	%tmp = load i91, i91* @i91_l		; <i91> [#uses=1]
 	store i91 %tmp, i91* @i91_s
 	ret void
 }
 
 define void @i92_ls() nounwind  {
-	%tmp = load i92* @i92_l		; <i92> [#uses=1]
+	%tmp = load i92, i92* @i92_l		; <i92> [#uses=1]
 	store i92 %tmp, i92* @i92_s
 	ret void
 }
 
 define void @i93_ls() nounwind  {
-	%tmp = load i93* @i93_l		; <i93> [#uses=1]
+	%tmp = load i93, i93* @i93_l		; <i93> [#uses=1]
 	store i93 %tmp, i93* @i93_s
 	ret void
 }
 
 define void @i94_ls() nounwind  {
-	%tmp = load i94* @i94_l		; <i94> [#uses=1]
+	%tmp = load i94, i94* @i94_l		; <i94> [#uses=1]
 	store i94 %tmp, i94* @i94_s
 	ret void
 }
 
 define void @i95_ls() nounwind  {
-	%tmp = load i95* @i95_l		; <i95> [#uses=1]
+	%tmp = load i95, i95* @i95_l		; <i95> [#uses=1]
 	store i95 %tmp, i95* @i95_s
 	ret void
 }
 
 define void @i96_ls() nounwind  {
-	%tmp = load i96* @i96_l		; <i96> [#uses=1]
+	%tmp = load i96, i96* @i96_l		; <i96> [#uses=1]
 	store i96 %tmp, i96* @i96_s
 	ret void
 }
 
 define void @i97_ls() nounwind  {
-	%tmp = load i97* @i97_l		; <i97> [#uses=1]
+	%tmp = load i97, i97* @i97_l		; <i97> [#uses=1]
 	store i97 %tmp, i97* @i97_s
 	ret void
 }
 
 define void @i98_ls() nounwind  {
-	%tmp = load i98* @i98_l		; <i98> [#uses=1]
+	%tmp = load i98, i98* @i98_l		; <i98> [#uses=1]
 	store i98 %tmp, i98* @i98_s
 	ret void
 }
 
 define void @i99_ls() nounwind  {
-	%tmp = load i99* @i99_l		; <i99> [#uses=1]
+	%tmp = load i99, i99* @i99_l		; <i99> [#uses=1]
 	store i99 %tmp, i99* @i99_s
 	ret void
 }
 
 define void @i100_ls() nounwind  {
-	%tmp = load i100* @i100_l		; <i100> [#uses=1]
+	%tmp = load i100, i100* @i100_l		; <i100> [#uses=1]
 	store i100 %tmp, i100* @i100_s
 	ret void
 }
 
 define void @i101_ls() nounwind  {
-	%tmp = load i101* @i101_l		; <i101> [#uses=1]
+	%tmp = load i101, i101* @i101_l		; <i101> [#uses=1]
 	store i101 %tmp, i101* @i101_s
 	ret void
 }
 
 define void @i102_ls() nounwind  {
-	%tmp = load i102* @i102_l		; <i102> [#uses=1]
+	%tmp = load i102, i102* @i102_l		; <i102> [#uses=1]
 	store i102 %tmp, i102* @i102_s
 	ret void
 }
 
 define void @i103_ls() nounwind  {
-	%tmp = load i103* @i103_l		; <i103> [#uses=1]
+	%tmp = load i103, i103* @i103_l		; <i103> [#uses=1]
 	store i103 %tmp, i103* @i103_s
 	ret void
 }
 
 define void @i104_ls() nounwind  {
-	%tmp = load i104* @i104_l		; <i104> [#uses=1]
+	%tmp = load i104, i104* @i104_l		; <i104> [#uses=1]
 	store i104 %tmp, i104* @i104_s
 	ret void
 }
 
 define void @i105_ls() nounwind  {
-	%tmp = load i105* @i105_l		; <i105> [#uses=1]
+	%tmp = load i105, i105* @i105_l		; <i105> [#uses=1]
 	store i105 %tmp, i105* @i105_s
 	ret void
 }
 
 define void @i106_ls() nounwind  {
-	%tmp = load i106* @i106_l		; <i106> [#uses=1]
+	%tmp = load i106, i106* @i106_l		; <i106> [#uses=1]
 	store i106 %tmp, i106* @i106_s
 	ret void
 }
 
 define void @i107_ls() nounwind  {
-	%tmp = load i107* @i107_l		; <i107> [#uses=1]
+	%tmp = load i107, i107* @i107_l		; <i107> [#uses=1]
 	store i107 %tmp, i107* @i107_s
 	ret void
 }
 
 define void @i108_ls() nounwind  {
-	%tmp = load i108* @i108_l		; <i108> [#uses=1]
+	%tmp = load i108, i108* @i108_l		; <i108> [#uses=1]
 	store i108 %tmp, i108* @i108_s
 	ret void
 }
 
 define void @i109_ls() nounwind  {
-	%tmp = load i109* @i109_l		; <i109> [#uses=1]
+	%tmp = load i109, i109* @i109_l		; <i109> [#uses=1]
 	store i109 %tmp, i109* @i109_s
 	ret void
 }
 
 define void @i110_ls() nounwind  {
-	%tmp = load i110* @i110_l		; <i110> [#uses=1]
+	%tmp = load i110, i110* @i110_l		; <i110> [#uses=1]
 	store i110 %tmp, i110* @i110_s
 	ret void
 }
 
 define void @i111_ls() nounwind  {
-	%tmp = load i111* @i111_l		; <i111> [#uses=1]
+	%tmp = load i111, i111* @i111_l		; <i111> [#uses=1]
 	store i111 %tmp, i111* @i111_s
 	ret void
 }
 
 define void @i112_ls() nounwind  {
-	%tmp = load i112* @i112_l		; <i112> [#uses=1]
+	%tmp = load i112, i112* @i112_l		; <i112> [#uses=1]
 	store i112 %tmp, i112* @i112_s
 	ret void
 }
 
 define void @i113_ls() nounwind  {
-	%tmp = load i113* @i113_l		; <i113> [#uses=1]
+	%tmp = load i113, i113* @i113_l		; <i113> [#uses=1]
 	store i113 %tmp, i113* @i113_s
 	ret void
 }
 
 define void @i114_ls() nounwind  {
-	%tmp = load i114* @i114_l		; <i114> [#uses=1]
+	%tmp = load i114, i114* @i114_l		; <i114> [#uses=1]
 	store i114 %tmp, i114* @i114_s
 	ret void
 }
 
 define void @i115_ls() nounwind  {
-	%tmp = load i115* @i115_l		; <i115> [#uses=1]
+	%tmp = load i115, i115* @i115_l		; <i115> [#uses=1]
 	store i115 %tmp, i115* @i115_s
 	ret void
 }
 
 define void @i116_ls() nounwind  {
-	%tmp = load i116* @i116_l		; <i116> [#uses=1]
+	%tmp = load i116, i116* @i116_l		; <i116> [#uses=1]
 	store i116 %tmp, i116* @i116_s
 	ret void
 }
 
 define void @i117_ls() nounwind  {
-	%tmp = load i117* @i117_l		; <i117> [#uses=1]
+	%tmp = load i117, i117* @i117_l		; <i117> [#uses=1]
 	store i117 %tmp, i117* @i117_s
 	ret void
 }
 
 define void @i118_ls() nounwind  {
-	%tmp = load i118* @i118_l		; <i118> [#uses=1]
+	%tmp = load i118, i118* @i118_l		; <i118> [#uses=1]
 	store i118 %tmp, i118* @i118_s
 	ret void
 }
 
 define void @i119_ls() nounwind  {
-	%tmp = load i119* @i119_l		; <i119> [#uses=1]
+	%tmp = load i119, i119* @i119_l		; <i119> [#uses=1]
 	store i119 %tmp, i119* @i119_s
 	ret void
 }
 
 define void @i120_ls() nounwind  {
-	%tmp = load i120* @i120_l		; <i120> [#uses=1]
+	%tmp = load i120, i120* @i120_l		; <i120> [#uses=1]
 	store i120 %tmp, i120* @i120_s
 	ret void
 }
 
 define void @i121_ls() nounwind  {
-	%tmp = load i121* @i121_l		; <i121> [#uses=1]
+	%tmp = load i121, i121* @i121_l		; <i121> [#uses=1]
 	store i121 %tmp, i121* @i121_s
 	ret void
 }
 
 define void @i122_ls() nounwind  {
-	%tmp = load i122* @i122_l		; <i122> [#uses=1]
+	%tmp = load i122, i122* @i122_l		; <i122> [#uses=1]
 	store i122 %tmp, i122* @i122_s
 	ret void
 }
 
 define void @i123_ls() nounwind  {
-	%tmp = load i123* @i123_l		; <i123> [#uses=1]
+	%tmp = load i123, i123* @i123_l		; <i123> [#uses=1]
 	store i123 %tmp, i123* @i123_s
 	ret void
 }
 
 define void @i124_ls() nounwind  {
-	%tmp = load i124* @i124_l		; <i124> [#uses=1]
+	%tmp = load i124, i124* @i124_l		; <i124> [#uses=1]
 	store i124 %tmp, i124* @i124_s
 	ret void
 }
 
 define void @i125_ls() nounwind  {
-	%tmp = load i125* @i125_l		; <i125> [#uses=1]
+	%tmp = load i125, i125* @i125_l		; <i125> [#uses=1]
 	store i125 %tmp, i125* @i125_s
 	ret void
 }
 
 define void @i126_ls() nounwind  {
-	%tmp = load i126* @i126_l		; <i126> [#uses=1]
+	%tmp = load i126, i126* @i126_l		; <i126> [#uses=1]
 	store i126 %tmp, i126* @i126_s
 	ret void
 }
 
 define void @i127_ls() nounwind  {
-	%tmp = load i127* @i127_l		; <i127> [#uses=1]
+	%tmp = load i127, i127* @i127_l		; <i127> [#uses=1]
 	store i127 %tmp, i127* @i127_s
 	ret void
 }
 
 define void @i128_ls() nounwind  {
-	%tmp = load i128* @i128_l		; <i128> [#uses=1]
+	%tmp = load i128, i128* @i128_l		; <i128> [#uses=1]
 	store i128 %tmp, i128* @i128_s
 	ret void
 }
 
 define void @i129_ls() nounwind  {
-	%tmp = load i129* @i129_l		; <i129> [#uses=1]
+	%tmp = load i129, i129* @i129_l		; <i129> [#uses=1]
 	store i129 %tmp, i129* @i129_s
 	ret void
 }
 
 define void @i130_ls() nounwind  {
-	%tmp = load i130* @i130_l		; <i130> [#uses=1]
+	%tmp = load i130, i130* @i130_l		; <i130> [#uses=1]
 	store i130 %tmp, i130* @i130_s
 	ret void
 }
 
 define void @i131_ls() nounwind  {
-	%tmp = load i131* @i131_l		; <i131> [#uses=1]
+	%tmp = load i131, i131* @i131_l		; <i131> [#uses=1]
 	store i131 %tmp, i131* @i131_s
 	ret void
 }
 
 define void @i132_ls() nounwind  {
-	%tmp = load i132* @i132_l		; <i132> [#uses=1]
+	%tmp = load i132, i132* @i132_l		; <i132> [#uses=1]
 	store i132 %tmp, i132* @i132_s
 	ret void
 }
 
 define void @i133_ls() nounwind  {
-	%tmp = load i133* @i133_l		; <i133> [#uses=1]
+	%tmp = load i133, i133* @i133_l		; <i133> [#uses=1]
 	store i133 %tmp, i133* @i133_s
 	ret void
 }
 
 define void @i134_ls() nounwind  {
-	%tmp = load i134* @i134_l		; <i134> [#uses=1]
+	%tmp = load i134, i134* @i134_l		; <i134> [#uses=1]
 	store i134 %tmp, i134* @i134_s
 	ret void
 }
 
 define void @i135_ls() nounwind  {
-	%tmp = load i135* @i135_l		; <i135> [#uses=1]
+	%tmp = load i135, i135* @i135_l		; <i135> [#uses=1]
 	store i135 %tmp, i135* @i135_s
 	ret void
 }
 
 define void @i136_ls() nounwind  {
-	%tmp = load i136* @i136_l		; <i136> [#uses=1]
+	%tmp = load i136, i136* @i136_l		; <i136> [#uses=1]
 	store i136 %tmp, i136* @i136_s
 	ret void
 }
 
 define void @i137_ls() nounwind  {
-	%tmp = load i137* @i137_l		; <i137> [#uses=1]
+	%tmp = load i137, i137* @i137_l		; <i137> [#uses=1]
 	store i137 %tmp, i137* @i137_s
 	ret void
 }
 
 define void @i138_ls() nounwind  {
-	%tmp = load i138* @i138_l		; <i138> [#uses=1]
+	%tmp = load i138, i138* @i138_l		; <i138> [#uses=1]
 	store i138 %tmp, i138* @i138_s
 	ret void
 }
 
 define void @i139_ls() nounwind  {
-	%tmp = load i139* @i139_l		; <i139> [#uses=1]
+	%tmp = load i139, i139* @i139_l		; <i139> [#uses=1]
 	store i139 %tmp, i139* @i139_s
 	ret void
 }
 
 define void @i140_ls() nounwind  {
-	%tmp = load i140* @i140_l		; <i140> [#uses=1]
+	%tmp = load i140, i140* @i140_l		; <i140> [#uses=1]
 	store i140 %tmp, i140* @i140_s
 	ret void
 }
 
 define void @i141_ls() nounwind  {
-	%tmp = load i141* @i141_l		; <i141> [#uses=1]
+	%tmp = load i141, i141* @i141_l		; <i141> [#uses=1]
 	store i141 %tmp, i141* @i141_s
 	ret void
 }
 
 define void @i142_ls() nounwind  {
-	%tmp = load i142* @i142_l		; <i142> [#uses=1]
+	%tmp = load i142, i142* @i142_l		; <i142> [#uses=1]
 	store i142 %tmp, i142* @i142_s
 	ret void
 }
 
 define void @i143_ls() nounwind  {
-	%tmp = load i143* @i143_l		; <i143> [#uses=1]
+	%tmp = load i143, i143* @i143_l		; <i143> [#uses=1]
 	store i143 %tmp, i143* @i143_s
 	ret void
 }
 
 define void @i144_ls() nounwind  {
-	%tmp = load i144* @i144_l		; <i144> [#uses=1]
+	%tmp = load i144, i144* @i144_l		; <i144> [#uses=1]
 	store i144 %tmp, i144* @i144_s
 	ret void
 }
 
 define void @i145_ls() nounwind  {
-	%tmp = load i145* @i145_l		; <i145> [#uses=1]
+	%tmp = load i145, i145* @i145_l		; <i145> [#uses=1]
 	store i145 %tmp, i145* @i145_s
 	ret void
 }
 
 define void @i146_ls() nounwind  {
-	%tmp = load i146* @i146_l		; <i146> [#uses=1]
+	%tmp = load i146, i146* @i146_l		; <i146> [#uses=1]
 	store i146 %tmp, i146* @i146_s
 	ret void
 }
 
 define void @i147_ls() nounwind  {
-	%tmp = load i147* @i147_l		; <i147> [#uses=1]
+	%tmp = load i147, i147* @i147_l		; <i147> [#uses=1]
 	store i147 %tmp, i147* @i147_s
 	ret void
 }
 
 define void @i148_ls() nounwind  {
-	%tmp = load i148* @i148_l		; <i148> [#uses=1]
+	%tmp = load i148, i148* @i148_l		; <i148> [#uses=1]
 	store i148 %tmp, i148* @i148_s
 	ret void
 }
 
 define void @i149_ls() nounwind  {
-	%tmp = load i149* @i149_l		; <i149> [#uses=1]
+	%tmp = load i149, i149* @i149_l		; <i149> [#uses=1]
 	store i149 %tmp, i149* @i149_s
 	ret void
 }
 
 define void @i150_ls() nounwind  {
-	%tmp = load i150* @i150_l		; <i150> [#uses=1]
+	%tmp = load i150, i150* @i150_l		; <i150> [#uses=1]
 	store i150 %tmp, i150* @i150_s
 	ret void
 }
 
 define void @i151_ls() nounwind  {
-	%tmp = load i151* @i151_l		; <i151> [#uses=1]
+	%tmp = load i151, i151* @i151_l		; <i151> [#uses=1]
 	store i151 %tmp, i151* @i151_s
 	ret void
 }
 
 define void @i152_ls() nounwind  {
-	%tmp = load i152* @i152_l		; <i152> [#uses=1]
+	%tmp = load i152, i152* @i152_l		; <i152> [#uses=1]
 	store i152 %tmp, i152* @i152_s
 	ret void
 }
 
 define void @i153_ls() nounwind  {
-	%tmp = load i153* @i153_l		; <i153> [#uses=1]
+	%tmp = load i153, i153* @i153_l		; <i153> [#uses=1]
 	store i153 %tmp, i153* @i153_s
 	ret void
 }
 
 define void @i154_ls() nounwind  {
-	%tmp = load i154* @i154_l		; <i154> [#uses=1]
+	%tmp = load i154, i154* @i154_l		; <i154> [#uses=1]
 	store i154 %tmp, i154* @i154_s
 	ret void
 }
 
 define void @i155_ls() nounwind  {
-	%tmp = load i155* @i155_l		; <i155> [#uses=1]
+	%tmp = load i155, i155* @i155_l		; <i155> [#uses=1]
 	store i155 %tmp, i155* @i155_s
 	ret void
 }
 
 define void @i156_ls() nounwind  {
-	%tmp = load i156* @i156_l		; <i156> [#uses=1]
+	%tmp = load i156, i156* @i156_l		; <i156> [#uses=1]
 	store i156 %tmp, i156* @i156_s
 	ret void
 }
 
 define void @i157_ls() nounwind  {
-	%tmp = load i157* @i157_l		; <i157> [#uses=1]
+	%tmp = load i157, i157* @i157_l		; <i157> [#uses=1]
 	store i157 %tmp, i157* @i157_s
 	ret void
 }
 
 define void @i158_ls() nounwind  {
-	%tmp = load i158* @i158_l		; <i158> [#uses=1]
+	%tmp = load i158, i158* @i158_l		; <i158> [#uses=1]
 	store i158 %tmp, i158* @i158_s
 	ret void
 }
 
 define void @i159_ls() nounwind  {
-	%tmp = load i159* @i159_l		; <i159> [#uses=1]
+	%tmp = load i159, i159* @i159_l		; <i159> [#uses=1]
 	store i159 %tmp, i159* @i159_s
 	ret void
 }
 
 define void @i160_ls() nounwind  {
-	%tmp = load i160* @i160_l		; <i160> [#uses=1]
+	%tmp = load i160, i160* @i160_l		; <i160> [#uses=1]
 	store i160 %tmp, i160* @i160_s
 	ret void
 }
 
 define void @i161_ls() nounwind  {
-	%tmp = load i161* @i161_l		; <i161> [#uses=1]
+	%tmp = load i161, i161* @i161_l		; <i161> [#uses=1]
 	store i161 %tmp, i161* @i161_s
 	ret void
 }
 
 define void @i162_ls() nounwind  {
-	%tmp = load i162* @i162_l		; <i162> [#uses=1]
+	%tmp = load i162, i162* @i162_l		; <i162> [#uses=1]
 	store i162 %tmp, i162* @i162_s
 	ret void
 }
 
 define void @i163_ls() nounwind  {
-	%tmp = load i163* @i163_l		; <i163> [#uses=1]
+	%tmp = load i163, i163* @i163_l		; <i163> [#uses=1]
 	store i163 %tmp, i163* @i163_s
 	ret void
 }
 
 define void @i164_ls() nounwind  {
-	%tmp = load i164* @i164_l		; <i164> [#uses=1]
+	%tmp = load i164, i164* @i164_l		; <i164> [#uses=1]
 	store i164 %tmp, i164* @i164_s
 	ret void
 }
 
 define void @i165_ls() nounwind  {
-	%tmp = load i165* @i165_l		; <i165> [#uses=1]
+	%tmp = load i165, i165* @i165_l		; <i165> [#uses=1]
 	store i165 %tmp, i165* @i165_s
 	ret void
 }
 
 define void @i166_ls() nounwind  {
-	%tmp = load i166* @i166_l		; <i166> [#uses=1]
+	%tmp = load i166, i166* @i166_l		; <i166> [#uses=1]
 	store i166 %tmp, i166* @i166_s
 	ret void
 }
 
 define void @i167_ls() nounwind  {
-	%tmp = load i167* @i167_l		; <i167> [#uses=1]
+	%tmp = load i167, i167* @i167_l		; <i167> [#uses=1]
 	store i167 %tmp, i167* @i167_s
 	ret void
 }
 
 define void @i168_ls() nounwind  {
-	%tmp = load i168* @i168_l		; <i168> [#uses=1]
+	%tmp = load i168, i168* @i168_l		; <i168> [#uses=1]
 	store i168 %tmp, i168* @i168_s
 	ret void
 }
 
 define void @i169_ls() nounwind  {
-	%tmp = load i169* @i169_l		; <i169> [#uses=1]
+	%tmp = load i169, i169* @i169_l		; <i169> [#uses=1]
 	store i169 %tmp, i169* @i169_s
 	ret void
 }
 
 define void @i170_ls() nounwind  {
-	%tmp = load i170* @i170_l		; <i170> [#uses=1]
+	%tmp = load i170, i170* @i170_l		; <i170> [#uses=1]
 	store i170 %tmp, i170* @i170_s
 	ret void
 }
 
 define void @i171_ls() nounwind  {
-	%tmp = load i171* @i171_l		; <i171> [#uses=1]
+	%tmp = load i171, i171* @i171_l		; <i171> [#uses=1]
 	store i171 %tmp, i171* @i171_s
 	ret void
 }
 
 define void @i172_ls() nounwind  {
-	%tmp = load i172* @i172_l		; <i172> [#uses=1]
+	%tmp = load i172, i172* @i172_l		; <i172> [#uses=1]
 	store i172 %tmp, i172* @i172_s
 	ret void
 }
 
 define void @i173_ls() nounwind  {
-	%tmp = load i173* @i173_l		; <i173> [#uses=1]
+	%tmp = load i173, i173* @i173_l		; <i173> [#uses=1]
 	store i173 %tmp, i173* @i173_s
 	ret void
 }
 
 define void @i174_ls() nounwind  {
-	%tmp = load i174* @i174_l		; <i174> [#uses=1]
+	%tmp = load i174, i174* @i174_l		; <i174> [#uses=1]
 	store i174 %tmp, i174* @i174_s
 	ret void
 }
 
 define void @i175_ls() nounwind  {
-	%tmp = load i175* @i175_l		; <i175> [#uses=1]
+	%tmp = load i175, i175* @i175_l		; <i175> [#uses=1]
 	store i175 %tmp, i175* @i175_s
 	ret void
 }
 
 define void @i176_ls() nounwind  {
-	%tmp = load i176* @i176_l		; <i176> [#uses=1]
+	%tmp = load i176, i176* @i176_l		; <i176> [#uses=1]
 	store i176 %tmp, i176* @i176_s
 	ret void
 }
 
 define void @i177_ls() nounwind  {
-	%tmp = load i177* @i177_l		; <i177> [#uses=1]
+	%tmp = load i177, i177* @i177_l		; <i177> [#uses=1]
 	store i177 %tmp, i177* @i177_s
 	ret void
 }
 
 define void @i178_ls() nounwind  {
-	%tmp = load i178* @i178_l		; <i178> [#uses=1]
+	%tmp = load i178, i178* @i178_l		; <i178> [#uses=1]
 	store i178 %tmp, i178* @i178_s
 	ret void
 }
 
 define void @i179_ls() nounwind  {
-	%tmp = load i179* @i179_l		; <i179> [#uses=1]
+	%tmp = load i179, i179* @i179_l		; <i179> [#uses=1]
 	store i179 %tmp, i179* @i179_s
 	ret void
 }
 
 define void @i180_ls() nounwind  {
-	%tmp = load i180* @i180_l		; <i180> [#uses=1]
+	%tmp = load i180, i180* @i180_l		; <i180> [#uses=1]
 	store i180 %tmp, i180* @i180_s
 	ret void
 }
 
 define void @i181_ls() nounwind  {
-	%tmp = load i181* @i181_l		; <i181> [#uses=1]
+	%tmp = load i181, i181* @i181_l		; <i181> [#uses=1]
 	store i181 %tmp, i181* @i181_s
 	ret void
 }
 
 define void @i182_ls() nounwind  {
-	%tmp = load i182* @i182_l		; <i182> [#uses=1]
+	%tmp = load i182, i182* @i182_l		; <i182> [#uses=1]
 	store i182 %tmp, i182* @i182_s
 	ret void
 }
 
 define void @i183_ls() nounwind  {
-	%tmp = load i183* @i183_l		; <i183> [#uses=1]
+	%tmp = load i183, i183* @i183_l		; <i183> [#uses=1]
 	store i183 %tmp, i183* @i183_s
 	ret void
 }
 
 define void @i184_ls() nounwind  {
-	%tmp = load i184* @i184_l		; <i184> [#uses=1]
+	%tmp = load i184, i184* @i184_l		; <i184> [#uses=1]
 	store i184 %tmp, i184* @i184_s
 	ret void
 }
 
 define void @i185_ls() nounwind  {
-	%tmp = load i185* @i185_l		; <i185> [#uses=1]
+	%tmp = load i185, i185* @i185_l		; <i185> [#uses=1]
 	store i185 %tmp, i185* @i185_s
 	ret void
 }
 
 define void @i186_ls() nounwind  {
-	%tmp = load i186* @i186_l		; <i186> [#uses=1]
+	%tmp = load i186, i186* @i186_l		; <i186> [#uses=1]
 	store i186 %tmp, i186* @i186_s
 	ret void
 }
 
 define void @i187_ls() nounwind  {
-	%tmp = load i187* @i187_l		; <i187> [#uses=1]
+	%tmp = load i187, i187* @i187_l		; <i187> [#uses=1]
 	store i187 %tmp, i187* @i187_s
 	ret void
 }
 
 define void @i188_ls() nounwind  {
-	%tmp = load i188* @i188_l		; <i188> [#uses=1]
+	%tmp = load i188, i188* @i188_l		; <i188> [#uses=1]
 	store i188 %tmp, i188* @i188_s
 	ret void
 }
 
 define void @i189_ls() nounwind  {
-	%tmp = load i189* @i189_l		; <i189> [#uses=1]
+	%tmp = load i189, i189* @i189_l		; <i189> [#uses=1]
 	store i189 %tmp, i189* @i189_s
 	ret void
 }
 
 define void @i190_ls() nounwind  {
-	%tmp = load i190* @i190_l		; <i190> [#uses=1]
+	%tmp = load i190, i190* @i190_l		; <i190> [#uses=1]
 	store i190 %tmp, i190* @i190_s
 	ret void
 }
 
 define void @i191_ls() nounwind  {
-	%tmp = load i191* @i191_l		; <i191> [#uses=1]
+	%tmp = load i191, i191* @i191_l		; <i191> [#uses=1]
 	store i191 %tmp, i191* @i191_s
 	ret void
 }
 
 define void @i192_ls() nounwind  {
-	%tmp = load i192* @i192_l		; <i192> [#uses=1]
+	%tmp = load i192, i192* @i192_l		; <i192> [#uses=1]
 	store i192 %tmp, i192* @i192_s
 	ret void
 }
 
 define void @i193_ls() nounwind  {
-	%tmp = load i193* @i193_l		; <i193> [#uses=1]
+	%tmp = load i193, i193* @i193_l		; <i193> [#uses=1]
 	store i193 %tmp, i193* @i193_s
 	ret void
 }
 
 define void @i194_ls() nounwind  {
-	%tmp = load i194* @i194_l		; <i194> [#uses=1]
+	%tmp = load i194, i194* @i194_l		; <i194> [#uses=1]
 	store i194 %tmp, i194* @i194_s
 	ret void
 }
 
 define void @i195_ls() nounwind  {
-	%tmp = load i195* @i195_l		; <i195> [#uses=1]
+	%tmp = load i195, i195* @i195_l		; <i195> [#uses=1]
 	store i195 %tmp, i195* @i195_s
 	ret void
 }
 
 define void @i196_ls() nounwind  {
-	%tmp = load i196* @i196_l		; <i196> [#uses=1]
+	%tmp = load i196, i196* @i196_l		; <i196> [#uses=1]
 	store i196 %tmp, i196* @i196_s
 	ret void
 }
 
 define void @i197_ls() nounwind  {
-	%tmp = load i197* @i197_l		; <i197> [#uses=1]
+	%tmp = load i197, i197* @i197_l		; <i197> [#uses=1]
 	store i197 %tmp, i197* @i197_s
 	ret void
 }
 
 define void @i198_ls() nounwind  {
-	%tmp = load i198* @i198_l		; <i198> [#uses=1]
+	%tmp = load i198, i198* @i198_l		; <i198> [#uses=1]
 	store i198 %tmp, i198* @i198_s
 	ret void
 }
 
 define void @i199_ls() nounwind  {
-	%tmp = load i199* @i199_l		; <i199> [#uses=1]
+	%tmp = load i199, i199* @i199_l		; <i199> [#uses=1]
 	store i199 %tmp, i199* @i199_s
 	ret void
 }
 
 define void @i200_ls() nounwind  {
-	%tmp = load i200* @i200_l		; <i200> [#uses=1]
+	%tmp = load i200, i200* @i200_l		; <i200> [#uses=1]
 	store i200 %tmp, i200* @i200_s
 	ret void
 }
 
 define void @i201_ls() nounwind  {
-	%tmp = load i201* @i201_l		; <i201> [#uses=1]
+	%tmp = load i201, i201* @i201_l		; <i201> [#uses=1]
 	store i201 %tmp, i201* @i201_s
 	ret void
 }
 
 define void @i202_ls() nounwind  {
-	%tmp = load i202* @i202_l		; <i202> [#uses=1]
+	%tmp = load i202, i202* @i202_l		; <i202> [#uses=1]
 	store i202 %tmp, i202* @i202_s
 	ret void
 }
 
 define void @i203_ls() nounwind  {
-	%tmp = load i203* @i203_l		; <i203> [#uses=1]
+	%tmp = load i203, i203* @i203_l		; <i203> [#uses=1]
 	store i203 %tmp, i203* @i203_s
 	ret void
 }
 
 define void @i204_ls() nounwind  {
-	%tmp = load i204* @i204_l		; <i204> [#uses=1]
+	%tmp = load i204, i204* @i204_l		; <i204> [#uses=1]
 	store i204 %tmp, i204* @i204_s
 	ret void
 }
 
 define void @i205_ls() nounwind  {
-	%tmp = load i205* @i205_l		; <i205> [#uses=1]
+	%tmp = load i205, i205* @i205_l		; <i205> [#uses=1]
 	store i205 %tmp, i205* @i205_s
 	ret void
 }
 
 define void @i206_ls() nounwind  {
-	%tmp = load i206* @i206_l		; <i206> [#uses=1]
+	%tmp = load i206, i206* @i206_l		; <i206> [#uses=1]
 	store i206 %tmp, i206* @i206_s
 	ret void
 }
 
 define void @i207_ls() nounwind  {
-	%tmp = load i207* @i207_l		; <i207> [#uses=1]
+	%tmp = load i207, i207* @i207_l		; <i207> [#uses=1]
 	store i207 %tmp, i207* @i207_s
 	ret void
 }
 
 define void @i208_ls() nounwind  {
-	%tmp = load i208* @i208_l		; <i208> [#uses=1]
+	%tmp = load i208, i208* @i208_l		; <i208> [#uses=1]
 	store i208 %tmp, i208* @i208_s
 	ret void
 }
 
 define void @i209_ls() nounwind  {
-	%tmp = load i209* @i209_l		; <i209> [#uses=1]
+	%tmp = load i209, i209* @i209_l		; <i209> [#uses=1]
 	store i209 %tmp, i209* @i209_s
 	ret void
 }
 
 define void @i210_ls() nounwind  {
-	%tmp = load i210* @i210_l		; <i210> [#uses=1]
+	%tmp = load i210, i210* @i210_l		; <i210> [#uses=1]
 	store i210 %tmp, i210* @i210_s
 	ret void
 }
 
 define void @i211_ls() nounwind  {
-	%tmp = load i211* @i211_l		; <i211> [#uses=1]
+	%tmp = load i211, i211* @i211_l		; <i211> [#uses=1]
 	store i211 %tmp, i211* @i211_s
 	ret void
 }
 
 define void @i212_ls() nounwind  {
-	%tmp = load i212* @i212_l		; <i212> [#uses=1]
+	%tmp = load i212, i212* @i212_l		; <i212> [#uses=1]
 	store i212 %tmp, i212* @i212_s
 	ret void
 }
 
 define void @i213_ls() nounwind  {
-	%tmp = load i213* @i213_l		; <i213> [#uses=1]
+	%tmp = load i213, i213* @i213_l		; <i213> [#uses=1]
 	store i213 %tmp, i213* @i213_s
 	ret void
 }
 
 define void @i214_ls() nounwind  {
-	%tmp = load i214* @i214_l		; <i214> [#uses=1]
+	%tmp = load i214, i214* @i214_l		; <i214> [#uses=1]
 	store i214 %tmp, i214* @i214_s
 	ret void
 }
 
 define void @i215_ls() nounwind  {
-	%tmp = load i215* @i215_l		; <i215> [#uses=1]
+	%tmp = load i215, i215* @i215_l		; <i215> [#uses=1]
 	store i215 %tmp, i215* @i215_s
 	ret void
 }
 
 define void @i216_ls() nounwind  {
-	%tmp = load i216* @i216_l		; <i216> [#uses=1]
+	%tmp = load i216, i216* @i216_l		; <i216> [#uses=1]
 	store i216 %tmp, i216* @i216_s
 	ret void
 }
 
 define void @i217_ls() nounwind  {
-	%tmp = load i217* @i217_l		; <i217> [#uses=1]
+	%tmp = load i217, i217* @i217_l		; <i217> [#uses=1]
 	store i217 %tmp, i217* @i217_s
 	ret void
 }
 
 define void @i218_ls() nounwind  {
-	%tmp = load i218* @i218_l		; <i218> [#uses=1]
+	%tmp = load i218, i218* @i218_l		; <i218> [#uses=1]
 	store i218 %tmp, i218* @i218_s
 	ret void
 }
 
 define void @i219_ls() nounwind  {
-	%tmp = load i219* @i219_l		; <i219> [#uses=1]
+	%tmp = load i219, i219* @i219_l		; <i219> [#uses=1]
 	store i219 %tmp, i219* @i219_s
 	ret void
 }
 
 define void @i220_ls() nounwind  {
-	%tmp = load i220* @i220_l		; <i220> [#uses=1]
+	%tmp = load i220, i220* @i220_l		; <i220> [#uses=1]
 	store i220 %tmp, i220* @i220_s
 	ret void
 }
 
 define void @i221_ls() nounwind  {
-	%tmp = load i221* @i221_l		; <i221> [#uses=1]
+	%tmp = load i221, i221* @i221_l		; <i221> [#uses=1]
 	store i221 %tmp, i221* @i221_s
 	ret void
 }
 
 define void @i222_ls() nounwind  {
-	%tmp = load i222* @i222_l		; <i222> [#uses=1]
+	%tmp = load i222, i222* @i222_l		; <i222> [#uses=1]
 	store i222 %tmp, i222* @i222_s
 	ret void
 }
 
 define void @i223_ls() nounwind  {
-	%tmp = load i223* @i223_l		; <i223> [#uses=1]
+	%tmp = load i223, i223* @i223_l		; <i223> [#uses=1]
 	store i223 %tmp, i223* @i223_s
 	ret void
 }
 
 define void @i224_ls() nounwind  {
-	%tmp = load i224* @i224_l		; <i224> [#uses=1]
+	%tmp = load i224, i224* @i224_l		; <i224> [#uses=1]
 	store i224 %tmp, i224* @i224_s
 	ret void
 }
 
 define void @i225_ls() nounwind  {
-	%tmp = load i225* @i225_l		; <i225> [#uses=1]
+	%tmp = load i225, i225* @i225_l		; <i225> [#uses=1]
 	store i225 %tmp, i225* @i225_s
 	ret void
 }
 
 define void @i226_ls() nounwind  {
-	%tmp = load i226* @i226_l		; <i226> [#uses=1]
+	%tmp = load i226, i226* @i226_l		; <i226> [#uses=1]
 	store i226 %tmp, i226* @i226_s
 	ret void
 }
 
 define void @i227_ls() nounwind  {
-	%tmp = load i227* @i227_l		; <i227> [#uses=1]
+	%tmp = load i227, i227* @i227_l		; <i227> [#uses=1]
 	store i227 %tmp, i227* @i227_s
 	ret void
 }
 
 define void @i228_ls() nounwind  {
-	%tmp = load i228* @i228_l		; <i228> [#uses=1]
+	%tmp = load i228, i228* @i228_l		; <i228> [#uses=1]
 	store i228 %tmp, i228* @i228_s
 	ret void
 }
 
 define void @i229_ls() nounwind  {
-	%tmp = load i229* @i229_l		; <i229> [#uses=1]
+	%tmp = load i229, i229* @i229_l		; <i229> [#uses=1]
 	store i229 %tmp, i229* @i229_s
 	ret void
 }
 
 define void @i230_ls() nounwind  {
-	%tmp = load i230* @i230_l		; <i230> [#uses=1]
+	%tmp = load i230, i230* @i230_l		; <i230> [#uses=1]
 	store i230 %tmp, i230* @i230_s
 	ret void
 }
 
 define void @i231_ls() nounwind  {
-	%tmp = load i231* @i231_l		; <i231> [#uses=1]
+	%tmp = load i231, i231* @i231_l		; <i231> [#uses=1]
 	store i231 %tmp, i231* @i231_s
 	ret void
 }
 
 define void @i232_ls() nounwind  {
-	%tmp = load i232* @i232_l		; <i232> [#uses=1]
+	%tmp = load i232, i232* @i232_l		; <i232> [#uses=1]
 	store i232 %tmp, i232* @i232_s
 	ret void
 }
 
 define void @i233_ls() nounwind  {
-	%tmp = load i233* @i233_l		; <i233> [#uses=1]
+	%tmp = load i233, i233* @i233_l		; <i233> [#uses=1]
 	store i233 %tmp, i233* @i233_s
 	ret void
 }
 
 define void @i234_ls() nounwind  {
-	%tmp = load i234* @i234_l		; <i234> [#uses=1]
+	%tmp = load i234, i234* @i234_l		; <i234> [#uses=1]
 	store i234 %tmp, i234* @i234_s
 	ret void
 }
 
 define void @i235_ls() nounwind  {
-	%tmp = load i235* @i235_l		; <i235> [#uses=1]
+	%tmp = load i235, i235* @i235_l		; <i235> [#uses=1]
 	store i235 %tmp, i235* @i235_s
 	ret void
 }
 
 define void @i236_ls() nounwind  {
-	%tmp = load i236* @i236_l		; <i236> [#uses=1]
+	%tmp = load i236, i236* @i236_l		; <i236> [#uses=1]
 	store i236 %tmp, i236* @i236_s
 	ret void
 }
 
 define void @i237_ls() nounwind  {
-	%tmp = load i237* @i237_l		; <i237> [#uses=1]
+	%tmp = load i237, i237* @i237_l		; <i237> [#uses=1]
 	store i237 %tmp, i237* @i237_s
 	ret void
 }
 
 define void @i238_ls() nounwind  {
-	%tmp = load i238* @i238_l		; <i238> [#uses=1]
+	%tmp = load i238, i238* @i238_l		; <i238> [#uses=1]
 	store i238 %tmp, i238* @i238_s
 	ret void
 }
 
 define void @i239_ls() nounwind  {
-	%tmp = load i239* @i239_l		; <i239> [#uses=1]
+	%tmp = load i239, i239* @i239_l		; <i239> [#uses=1]
 	store i239 %tmp, i239* @i239_s
 	ret void
 }
 
 define void @i240_ls() nounwind  {
-	%tmp = load i240* @i240_l		; <i240> [#uses=1]
+	%tmp = load i240, i240* @i240_l		; <i240> [#uses=1]
 	store i240 %tmp, i240* @i240_s
 	ret void
 }
 
 define void @i241_ls() nounwind  {
-	%tmp = load i241* @i241_l		; <i241> [#uses=1]
+	%tmp = load i241, i241* @i241_l		; <i241> [#uses=1]
 	store i241 %tmp, i241* @i241_s
 	ret void
 }
 
 define void @i242_ls() nounwind  {
-	%tmp = load i242* @i242_l		; <i242> [#uses=1]
+	%tmp = load i242, i242* @i242_l		; <i242> [#uses=1]
 	store i242 %tmp, i242* @i242_s
 	ret void
 }
 
 define void @i243_ls() nounwind  {
-	%tmp = load i243* @i243_l		; <i243> [#uses=1]
+	%tmp = load i243, i243* @i243_l		; <i243> [#uses=1]
 	store i243 %tmp, i243* @i243_s
 	ret void
 }
 
 define void @i244_ls() nounwind  {
-	%tmp = load i244* @i244_l		; <i244> [#uses=1]
+	%tmp = load i244, i244* @i244_l		; <i244> [#uses=1]
 	store i244 %tmp, i244* @i244_s
 	ret void
 }
 
 define void @i245_ls() nounwind  {
-	%tmp = load i245* @i245_l		; <i245> [#uses=1]
+	%tmp = load i245, i245* @i245_l		; <i245> [#uses=1]
 	store i245 %tmp, i245* @i245_s
 	ret void
 }
 
 define void @i246_ls() nounwind  {
-	%tmp = load i246* @i246_l		; <i246> [#uses=1]
+	%tmp = load i246, i246* @i246_l		; <i246> [#uses=1]
 	store i246 %tmp, i246* @i246_s
 	ret void
 }
 
 define void @i247_ls() nounwind  {
-	%tmp = load i247* @i247_l		; <i247> [#uses=1]
+	%tmp = load i247, i247* @i247_l		; <i247> [#uses=1]
 	store i247 %tmp, i247* @i247_s
 	ret void
 }
 
 define void @i248_ls() nounwind  {
-	%tmp = load i248* @i248_l		; <i248> [#uses=1]
+	%tmp = load i248, i248* @i248_l		; <i248> [#uses=1]
 	store i248 %tmp, i248* @i248_s
 	ret void
 }
 
 define void @i249_ls() nounwind  {
-	%tmp = load i249* @i249_l		; <i249> [#uses=1]
+	%tmp = load i249, i249* @i249_l		; <i249> [#uses=1]
 	store i249 %tmp, i249* @i249_s
 	ret void
 }
 
 define void @i250_ls() nounwind  {
-	%tmp = load i250* @i250_l		; <i250> [#uses=1]
+	%tmp = load i250, i250* @i250_l		; <i250> [#uses=1]
 	store i250 %tmp, i250* @i250_s
 	ret void
 }
 
 define void @i251_ls() nounwind  {
-	%tmp = load i251* @i251_l		; <i251> [#uses=1]
+	%tmp = load i251, i251* @i251_l		; <i251> [#uses=1]
 	store i251 %tmp, i251* @i251_s
 	ret void
 }
 
 define void @i252_ls() nounwind  {
-	%tmp = load i252* @i252_l		; <i252> [#uses=1]
+	%tmp = load i252, i252* @i252_l		; <i252> [#uses=1]
 	store i252 %tmp, i252* @i252_s
 	ret void
 }
 
 define void @i253_ls() nounwind  {
-	%tmp = load i253* @i253_l		; <i253> [#uses=1]
+	%tmp = load i253, i253* @i253_l		; <i253> [#uses=1]
 	store i253 %tmp, i253* @i253_s
 	ret void
 }
 
 define void @i254_ls() nounwind  {
-	%tmp = load i254* @i254_l		; <i254> [#uses=1]
+	%tmp = load i254, i254* @i254_l		; <i254> [#uses=1]
 	store i254 %tmp, i254* @i254_s
 	ret void
 }
 
 define void @i255_ls() nounwind  {
-	%tmp = load i255* @i255_l		; <i255> [#uses=1]
+	%tmp = load i255, i255* @i255_l		; <i255> [#uses=1]
 	store i255 %tmp, i255* @i255_s
 	ret void
 }
 
 define void @i256_ls() nounwind  {
-	%tmp = load i256* @i256_l		; <i256> [#uses=1]
+	%tmp = load i256, i256* @i256_l		; <i256> [#uses=1]
 	store i256 %tmp, i256* @i256_s
 	ret void
 }
diff --git a/test/CodeGen/Generic/ConstantExprLowering.ll b/test/CodeGen/Generic/ConstantExprLowering.ll
index 428d712462d6..3119dfae0aa0 100644
--- a/test/CodeGen/Generic/ConstantExprLowering.ll
+++ b/test/CodeGen/Generic/ConstantExprLowering.ll
@@ -16,7 +16,7 @@ less:           ; preds = %entry
 
 not_less:               ; preds = %less, %entry
         %t2 = phi i32 [ sub (i32 ptrtoint (i32* @XA to i32), i32 ptrtoint (i32* @XB to i32)), %less ], [ sub (i32 ptrtoint (i32* @XA to i32), i32 ptrtoint (i32* @XB to i32)), %entry ]               ; <i32> [#uses=1]
-        %tmp.39 = call i32 (i8*, ...)* @printf( i8* getelementptr ([16 x i8]* @.str_1, i64 0, i64 0), i32 %t2 )      ; <i32> [#uses=0]
+        %tmp.39 = call i32 (i8*, ...) @printf( i8* getelementptr ([16 x i8], [16 x i8]* @.str_1, i64 0, i64 0), i32 %t2 )      ; <i32> [#uses=0]
         ret void
 }
 
diff --git a/test/CodeGen/Generic/MachineBranchProb.ll b/test/CodeGen/Generic/MachineBranchProb.ll
index 83277c98989d..8288e45ee509 100644
--- a/test/CodeGen/Generic/MachineBranchProb.ll
+++ b/test/CodeGen/Generic/MachineBranchProb.ll
@@ -1,11 +1,12 @@
 ; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s
 
 ; ARM & AArch64 run an extra SimplifyCFG which disrupts this test.
-; XFAIL: arm,aarch64
+; Hexagon crashes (PR23377)
+; XFAIL: arm,aarch64,hexagon
 
 ; Make sure we have the correct weight attached to each successor.
 define i32 @test2(i32 %x) nounwind uwtable readnone ssp {
-; CHECK: Machine code for function test2:
+; CHECK-LABEL: Machine code for function test2:
 entry:
   %conv = sext i32 %x to i64
   switch i64 %conv, label %return [
@@ -33,3 +34,41 @@ return:
 }
 
 !0 = !{!"branch_weights", i32 7, i32 6, i32 4, i32 4, i32 64}
+
+
+declare void @g(i32)
+define void @left_leaning_weight_balanced_tree(i32 %x) {
+entry:
+  switch i32 %x, label %return [
+    i32 0,  label %bb0
+    i32 10, label %bb1
+    i32 20, label %bb2
+    i32 30, label %bb3
+    i32 40, label %bb4
+    i32 50, label %bb5
+  ], !prof !1
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+bb2: tail call void @g(i32 2) br label %return
+bb3: tail call void @g(i32 3) br label %return
+bb4: tail call void @g(i32 4) br label %return
+bb5: tail call void @g(i32 5) br label %return
+return: ret void
+
+; Check that we set branch weights on the pivot cmp instruction correctly.
+; Cases {0,10,20,30} go on the left with weight 13; cases {40,50} go on the
+; right with weight 20.
+;
+; CHECK-LABEL: Machine code for function left_leaning_weight_balanced_tree:
+; CHECK: BB#0: derived from LLVM BB %entry
+; CHECK-NOT: Successors
+; CHECK: Successors according to CFG: BB#8(13) BB#9(20)
+}
+
+!1 = !{!"branch_weights",
+  ; Default:
+  i32 1,
+  ; Case 0, 10, 20:
+  i32 10, i32 1, i32 1,
+  ; Case 30, 40, 50:
+  i32 1, i32 10, i32 10}
diff --git a/test/CodeGen/Generic/PBQP.ll b/test/CodeGen/Generic/PBQP.ll
index 91fcfba1a905..31fc4e653d7b 100644
--- a/test/CodeGen/Generic/PBQP.ll
+++ b/test/CodeGen/Generic/PBQP.ll
@@ -2,23 +2,23 @@
 
 define i32 @foo() {
 entry:
-  %call = tail call i32 (...)* @baz()
-  %call1 = tail call i32 (...)* @baz()
-  %call2 = tail call i32 (...)* @baz()
-  %call3 = tail call i32 (...)* @baz()
-  %call4 = tail call i32 (...)* @baz()
-  %call5 = tail call i32 (...)* @baz()
-  %call6 = tail call i32 (...)* @baz()
-  %call7 = tail call i32 (...)* @baz()
-  %call8 = tail call i32 (...)* @baz()
-  %call9 = tail call i32 (...)* @baz()
-  %call10 = tail call i32 (...)* @baz()
-  %call11 = tail call i32 (...)* @baz()
-  %call12 = tail call i32 (...)* @baz()
-  %call13 = tail call i32 (...)* @baz()
-  %call14 = tail call i32 (...)* @baz()
-  %call15 = tail call i32 (...)* @baz()
-  %call16 = tail call i32 (...)* @baz()
+  %call = tail call i32 (...) @baz()
+  %call1 = tail call i32 (...) @baz()
+  %call2 = tail call i32 (...) @baz()
+  %call3 = tail call i32 (...) @baz()
+  %call4 = tail call i32 (...) @baz()
+  %call5 = tail call i32 (...) @baz()
+  %call6 = tail call i32 (...) @baz()
+  %call7 = tail call i32 (...) @baz()
+  %call8 = tail call i32 (...) @baz()
+  %call9 = tail call i32 (...) @baz()
+  %call10 = tail call i32 (...) @baz()
+  %call11 = tail call i32 (...) @baz()
+  %call12 = tail call i32 (...) @baz()
+  %call13 = tail call i32 (...) @baz()
+  %call14 = tail call i32 (...) @baz()
+  %call15 = tail call i32 (...) @baz()
+  %call16 = tail call i32 (...) @baz()
   %call17 = tail call i32 @bar(i32 %call, i32 %call1, i32 %call2, i32 %call3, i32 %call4, i32 %call5, i32 %call6, i32 %call7, i32 %call8, i32 %call9, i32 %call10, i32 %call11, i32 %call12, i32 %call13, i32 %call14, i32 %call15, i32 %call16)
   ret i32 %call17
 }
diff --git a/test/CodeGen/Generic/add-with-overflow-128.ll b/test/CodeGen/Generic/add-with-overflow-128.ll
index 33f44d6e4436..2a7456cbc211 100644
--- a/test/CodeGen/Generic/add-with-overflow-128.ll
+++ b/test/CodeGen/Generic/add-with-overflow-128.ll
@@ -14,11 +14,11 @@ entry:
   br i1 %obit, label %carry, label %normal
 
 normal:
-  %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum32 ) nounwind
+  %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum32 ) nounwind
   ret i1 true
 
 carry:
-  %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+  %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
 }
 
diff --git a/test/CodeGen/Generic/add-with-overflow-24.ll b/test/CodeGen/Generic/add-with-overflow-24.ll
index 63f5a222a003..6f06ae6b2afe 100644
--- a/test/CodeGen/Generic/add-with-overflow-24.ll
+++ b/test/CodeGen/Generic/add-with-overflow-24.ll
@@ -12,11 +12,11 @@ entry:
   br i1 %obit, label %overflow, label %normal
 
 normal:
-  %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum32 ) nounwind
+  %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum32 ) nounwind
   ret i1 true
 
 overflow:
-  %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+  %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
 }
 
@@ -29,11 +29,11 @@ entry:
   br i1 %obit, label %carry, label %normal
 
 normal:
-  %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum32 ) nounwind
+  %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum32 ) nounwind
   ret i1 true
 
 carry:
-  %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+  %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
 }
 
diff --git a/test/CodeGen/Generic/add-with-overflow.ll b/test/CodeGen/Generic/add-with-overflow.ll
index 0c2c9608deb9..b6bbaa1dc963 100644
--- a/test/CodeGen/Generic/add-with-overflow.ll
+++ b/test/CodeGen/Generic/add-with-overflow.ll
@@ -12,11 +12,11 @@ entry:
   br i1 %obit, label %overflow, label %normal
 
 normal:
-  %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
+  %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
   ret i1 true
 
 overflow:
-  %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+  %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
 }
 
@@ -28,11 +28,11 @@ entry:
   br i1 %obit, label %overflow, label %normal
 
 normal:
-  %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
+  %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
   ret i1 true
 
 overflow:
-  %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+  %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
 }
 
diff --git a/test/CodeGen/Generic/annotate.ll b/test/CodeGen/Generic/annotate.ll
index c617eb09258c..8dcf67edfb7d 100644
--- a/test/CodeGen/Generic/annotate.ll
+++ b/test/CodeGen/Generic/annotate.ll
@@ -8,7 +8,7 @@
 
 define i32 @foo(i32 %a) {
 entry:
-  %0 = call i32 @llvm.annotation.i32(i32 %a, i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @.str1, i32 0, i32 0), i32 2)
+  %0 = call i32 @llvm.annotation.i32(i32 %a, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str1, i32 0, i32 0), i32 2)
   ret i32 %0
 }
 
diff --git a/test/CodeGen/Generic/badFoldGEP.ll b/test/CodeGen/Generic/badFoldGEP.ll
index 2d4474bdf930..8150390d7752 100644
--- a/test/CodeGen/Generic/badFoldGEP.ll
+++ b/test/CodeGen/Generic/badFoldGEP.ll
@@ -19,9 +19,9 @@ define i32 @main(i32 %argc, i8** %argv) {
 bb0:
         call void @opaque( [497 x %Domain]* @domain_array )
         %cann-indvar-idxcast = sext i32 %argc to i64            ; <i64> [#uses=1]
-        %reg841 = getelementptr [497 x %Domain]* @domain_array, i64 0, i64 %cann-indvar-idxcast, i32 3          ; <i32*> [#uses=1]
-        %reg846 = getelementptr i32* %reg841, i64 1             ; <i32*> [#uses=1]
-        %reg820 = load i32* %reg846             ; <i32> [#uses=1]
+        %reg841 = getelementptr [497 x %Domain], [497 x %Domain]* @domain_array, i64 0, i64 %cann-indvar-idxcast, i32 3          ; <i32*> [#uses=1]
+        %reg846 = getelementptr i32, i32* %reg841, i64 1             ; <i32*> [#uses=1]
+        %reg820 = load i32, i32* %reg846             ; <i32> [#uses=1]
         ret i32 %reg820
 }
 
diff --git a/test/CodeGen/Generic/badarg6.ll b/test/CodeGen/Generic/badarg6.ll
index d6e5ac5791e4..34736ec0b5f5 100644
--- a/test/CodeGen/Generic/badarg6.ll
+++ b/test/CodeGen/Generic/badarg6.ll
@@ -27,6 +27,6 @@ bb43:		; preds = %bb42, %bb25
 	%reg323 = phi double [ -1.000000e+00, %bb25 ], [ %reg317, %bb42 ]		; <double> [#uses=1]
 	%reg324 = phi double [ -1.000000e+00, %bb25 ], [ %reg318, %bb42 ]		; <double> [#uses=1]
 	%reg325 = phi double [ 1.000000e+00, %bb25 ], [ %reg319, %bb42 ]		; <double> [#uses=1]
-	%reg609 = call i32 (i8*, ...)* @printf( i8* getelementptr ([44 x i8]* @.LC12, i64 0, i64 0), double %reg325, double %reg324, double %reg323, double %reg322, double %reg321 )		; <i32> [#uses=0]
+	%reg609 = call i32 (i8*, ...) @printf( i8* getelementptr ([44 x i8], [44 x i8]* @.LC12, i64 0, i64 0), double %reg325, double %reg324, double %reg323, double %reg322, double %reg321 )		; <i32> [#uses=0]
 	ret i32 0
 }
diff --git a/test/CodeGen/Generic/builtin-expect.ll b/test/CodeGen/Generic/builtin-expect.ll
index e8cd07badf0c..def687ed183f 100644
--- a/test/CodeGen/Generic/builtin-expect.ll
+++ b/test/CodeGen/Generic/builtin-expect.ll
@@ -5,7 +5,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %cmp = icmp sgt i32 %tmp, 1
   %conv = zext i1 %cmp to i32
   %conv1 = sext i32 %conv to i64
@@ -14,7 +14,7 @@ entry:
   br i1 %tobool, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %call = call i32 (...)* @f()
+  %call = call i32 (...) @f()
   store i32 %call, i32* %retval
   br label %return
 
@@ -23,7 +23,7 @@ if.end:                                           ; preds = %entry
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -36,14 +36,14 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %conv = sext i32 %tmp to i64
   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
   %tobool = icmp ne i64 %expval, 0
   br i1 %tobool, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %call = call i32 (...)* @f()
+  %call = call i32 (...) @f()
   store i32 %call, i32* %retval
   br label %return
 
@@ -52,7 +52,7 @@ if.end:                                           ; preds = %entry
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -61,7 +61,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %tobool = icmp ne i32 %tmp, 0
   %lnot = xor i1 %tobool, true
   %lnot.ext = zext i1 %lnot to i32
@@ -71,7 +71,7 @@ entry:
   br i1 %tobool1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %call = call i32 (...)* @f()
+  %call = call i32 (...) @f()
   store i32 %call, i32* %retval
   br label %return
 
@@ -80,7 +80,7 @@ if.end:                                           ; preds = %entry
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -89,7 +89,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %tobool = icmp ne i32 %tmp, 0
   %lnot = xor i1 %tobool, true
   %lnot1 = xor i1 %lnot, true
@@ -100,7 +100,7 @@ entry:
   br i1 %tobool2, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %call = call i32 (...)* @f()
+  %call = call i32 (...) @f()
   store i32 %call, i32* %retval
   br label %return
 
@@ -109,7 +109,7 @@ if.end:                                           ; preds = %entry
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -118,7 +118,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %cmp = icmp slt i32 %tmp, 0
   %conv = zext i1 %cmp to i32
   %conv1 = sext i32 %conv to i64
@@ -127,7 +127,7 @@ entry:
   br i1 %tobool, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %call = call i32 (...)* @f()
+  %call = call i32 (...) @f()
   store i32 %call, i32* %retval
   br label %return
 
@@ -136,7 +136,7 @@ if.end:                                           ; preds = %entry
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -145,7 +145,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %conv = sext i32 %tmp to i64
   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
   switch i64 %expval, label %sw.epilog [
@@ -162,7 +162,7 @@ sw.epilog:                                        ; preds = %entry
   br label %return
 
 return:                                           ; preds = %sw.epilog, %sw.bb
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -171,7 +171,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %conv = sext i32 %tmp to i64
   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
   switch i64 %expval, label %sw.epilog [
@@ -180,7 +180,7 @@ entry:
   ]
 
 sw.bb:                                            ; preds = %entry, %entry
-  %tmp1 = load i32* %x.addr, align 4
+  %tmp1 = load i32, i32* %x.addr, align 4
   store i32 %tmp1, i32* %retval
   br label %return
 
@@ -189,7 +189,7 @@ sw.epilog:                                        ; preds = %entry
   br label %return
 
 return:                                           ; preds = %sw.epilog, %sw.bb
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -198,7 +198,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %cmp = icmp sgt i32 %tmp, 1
   %conv = zext i1 %cmp to i32
   %expval = call i32 @llvm.expect.i32(i32 %conv, i32 1)
@@ -206,7 +206,7 @@ entry:
   br i1 %tobool, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %call = call i32 (...)* @f()
+  %call = call i32 (...) @f()
   store i32 %call, i32* %retval
   br label %return
 
@@ -215,7 +215,7 @@ if.end:                                           ; preds = %entry
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
diff --git a/test/CodeGen/Generic/cast-fp.ll b/test/CodeGen/Generic/cast-fp.ll
index 590b7ceee4bf..a2611f55dbdf 100644
--- a/test/CodeGen/Generic/cast-fp.ll
+++ b/test/CodeGen/Generic/cast-fp.ll
@@ -10,24 +10,24 @@
 declare i32 @printf(i8*, ...)
 
 define i32 @main() {
-	%a = load double* @A		; <double> [#uses=4]
-	%a_fs = getelementptr [8 x i8]* @a_fstr, i64 0, i64 0		; <i8*> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %a_fs, double %a )		; <i32>:1 [#uses=0]
+	%a = load double, double* @A		; <double> [#uses=4]
+	%a_fs = getelementptr [8 x i8], [8 x i8]* @a_fstr, i64 0, i64 0		; <i8*> [#uses=1]
+	call i32 (i8*, ...) @printf( i8* %a_fs, double %a )		; <i32>:1 [#uses=0]
 	%a_d2l = fptosi double %a to i64		; <i64> [#uses=1]
-	%a_ls = getelementptr [10 x i8]* @a_lstr, i64 0, i64 0		; <i8*> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %a_ls, i64 %a_d2l )		; <i32>:2 [#uses=0]
+	%a_ls = getelementptr [10 x i8], [10 x i8]* @a_lstr, i64 0, i64 0		; <i8*> [#uses=1]
+	call i32 (i8*, ...) @printf( i8* %a_ls, i64 %a_d2l )		; <i32>:2 [#uses=0]
 	%a_d2i = fptosi double %a to i32		; <i32> [#uses=2]
-	%a_ds = getelementptr [8 x i8]* @a_dstr, i64 0, i64 0		; <i8*> [#uses=3]
-	call i32 (i8*, ...)* @printf( i8* %a_ds, i32 %a_d2i )		; <i32>:3 [#uses=0]
+	%a_ds = getelementptr [8 x i8], [8 x i8]* @a_dstr, i64 0, i64 0		; <i8*> [#uses=3]
+	call i32 (i8*, ...) @printf( i8* %a_ds, i32 %a_d2i )		; <i32>:3 [#uses=0]
 	%a_d2sb = fptosi double %a to i8		; <i8> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %a_ds, i8 %a_d2sb )		; <i32>:4 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_ds, i8 %a_d2sb )		; <i32>:4 [#uses=0]
 	%a_d2i2sb = trunc i32 %a_d2i to i8		; <i8> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %a_ds, i8 %a_d2i2sb )		; <i32>:5 [#uses=0]
-	%b = load i32* @B		; <i32> [#uses=2]
-	%b_ds = getelementptr [8 x i8]* @b_dstr, i64 0, i64 0		; <i8*> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %b_ds, i32 %b )		; <i32>:6 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_ds, i8 %a_d2i2sb )		; <i32>:5 [#uses=0]
+	%b = load i32, i32* @B		; <i32> [#uses=2]
+	%b_ds = getelementptr [8 x i8], [8 x i8]* @b_dstr, i64 0, i64 0		; <i8*> [#uses=1]
+	call i32 (i8*, ...) @printf( i8* %b_ds, i32 %b )		; <i32>:6 [#uses=0]
 	%b_i2d = sitofp i32 %b to double		; <double> [#uses=1]
-	%b_fs = getelementptr [8 x i8]* @b_fstr, i64 0, i64 0		; <i8*> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %b_fs, double %b_i2d )		; <i32>:7 [#uses=0]
+	%b_fs = getelementptr [8 x i8], [8 x i8]* @b_fstr, i64 0, i64 0		; <i8*> [#uses=1]
+	call i32 (i8*, ...) @printf( i8* %b_fs, double %b_i2d )		; <i32>:7 [#uses=0]
 	ret i32 0
 }
diff --git a/test/CodeGen/Generic/constindices.ll b/test/CodeGen/Generic/constindices.ll
index 7deb30f43d12..837836fb29ca 100644
--- a/test/CodeGen/Generic/constindices.ll
+++ b/test/CodeGen/Generic/constindices.ll
@@ -14,31 +14,31 @@ define i32 @main() {
         %ScalarB = alloca %MixedB               ; <%MixedB*> [#uses=1]
         %ArrayA = alloca %MixedA, i32 4         ; <%MixedA*> [#uses=3]
         %ArrayB = alloca %MixedB, i32 3         ; <%MixedB*> [#uses=2]
-        %I1 = getelementptr %MixedA* %ScalarA, i64 0, i32 0             ; <float*> [#uses=2]
+        %I1 = getelementptr %MixedA, %MixedA* %ScalarA, i64 0, i32 0             ; <float*> [#uses=2]
         store float 0x3FF6A09020000000, float* %I1
-        %I2 = getelementptr %MixedB* %ScalarB, i64 0, i32 1, i32 0              ; <float*> [#uses=2]
+        %I2 = getelementptr %MixedB, %MixedB* %ScalarB, i64 0, i32 1, i32 0              ; <float*> [#uses=2]
         store float 0x4005BF1420000000, float* %I2
-        %fptrA = getelementptr %MixedA* %ArrayA, i64 1, i32 0           ; <float*> [#uses=1]
-        %fptrB = getelementptr %MixedB* %ArrayB, i64 2, i32 1, i32 0            ; <float*> [#uses=1]
+        %fptrA = getelementptr %MixedA, %MixedA* %ArrayA, i64 1, i32 0           ; <float*> [#uses=1]
+        %fptrB = getelementptr %MixedB, %MixedB* %ArrayB, i64 2, i32 1, i32 0            ; <float*> [#uses=1]
         store float 0x400921CAC0000000, float* %fptrA
         store float 5.000000e+00, float* %fptrB
 
         ;; Test that a sequence of GEPs with constant indices are folded right
-        %fptrA1 = getelementptr %MixedA* %ArrayA, i64 3         ; <%MixedA*> [#uses=1]
-        %fptrA2 = getelementptr %MixedA* %fptrA1, i64 0, i32 1          ; <[15 x i32]*> [#uses=1]
-        %fptrA3 = getelementptr [15 x i32]* %fptrA2, i64 0, i64 8               ; <i32*> [#uses=1]
+        %fptrA1 = getelementptr %MixedA, %MixedA* %ArrayA, i64 3         ; <%MixedA*> [#uses=1]
+        %fptrA2 = getelementptr %MixedA, %MixedA* %fptrA1, i64 0, i32 1          ; <[15 x i32]*> [#uses=1]
+        %fptrA3 = getelementptr [15 x i32], [15 x i32]* %fptrA2, i64 0, i64 8               ; <i32*> [#uses=1]
         store i32 5, i32* %fptrA3
-        %sqrtTwo = load float* %I1              ; <float> [#uses=1]
-        %exp = load float* %I2          ; <float> [#uses=1]
-        %I3 = getelementptr %MixedA* %ArrayA, i64 1, i32 0              ; <float*> [#uses=1]
-        %pi = load float* %I3           ; <float> [#uses=1]
-        %I4 = getelementptr %MixedB* %ArrayB, i64 2, i32 1, i32 0               ; <float*> [#uses=1]
-        %five = load float* %I4         ; <float> [#uses=1]
+        %sqrtTwo = load float, float* %I1              ; <float> [#uses=1]
+        %exp = load float, float* %I2          ; <float> [#uses=1]
+        %I3 = getelementptr %MixedA, %MixedA* %ArrayA, i64 1, i32 0              ; <float*> [#uses=1]
+        %pi = load float, float* %I3           ; <float> [#uses=1]
+        %I4 = getelementptr %MixedB, %MixedB* %ArrayB, i64 2, i32 1, i32 0               ; <float*> [#uses=1]
+        %five = load float, float* %I4         ; <float> [#uses=1]
         %dsqrtTwo = fpext float %sqrtTwo to double              ; <double> [#uses=1]
         %dexp = fpext float %exp to double              ; <double> [#uses=1]
         %dpi = fpext float %pi to double                ; <double> [#uses=1]
         %dfive = fpext float %five to double            ; <double> [#uses=1]
-        %castFmt = getelementptr [44 x i8]* @fmtArg, i64 0, i64 0               ; <i8*> [#uses=1]
-        call i32 (i8*, ...)* @printf( i8* %castFmt, double %dsqrtTwo, double %dexp, double %dpi, double %dfive )     ; <i32>:1 [#uses=0]
+        %castFmt = getelementptr [44 x i8], [44 x i8]* @fmtArg, i64 0, i64 0               ; <i8*> [#uses=1]
+        call i32 (i8*, ...) @printf( i8* %castFmt, double %dsqrtTwo, double %dexp, double %dpi, double %dfive )     ; <i32>:1 [#uses=0]
         ret i32 0
 }
diff --git a/test/CodeGen/Generic/crash.ll b/test/CodeGen/Generic/crash.ll
index 8de6b0d4bd31..81de762ba8c0 100644
--- a/test/CodeGen/Generic/crash.ll
+++ b/test/CodeGen/Generic/crash.ll
@@ -4,7 +4,7 @@
 %struct.AVCodecTag = type {}
 @ff_codec_bmp_tags = external global [0 x %struct.AVCodecTag]
 @tags = global [1 x %struct.AVCodecTag*] [%struct.AVCodecTag* getelementptr
-inbounds ([0 x %struct.AVCodecTag]* @ff_codec_bmp_tags, i32 0, i32 0)]
+inbounds ([0 x %struct.AVCodecTag], [0 x %struct.AVCodecTag]* @ff_codec_bmp_tags, i32 0, i32 0)]
 
 
 ; rdar://8878965
@@ -13,15 +13,15 @@ inbounds ([0 x %struct.AVCodecTag]* @ff_codec_bmp_tags, i32 0, i32 0)]
 
 define void @Parse_Camera(%struct.CAMERA** nocapture %Camera_Ptr) nounwind {
 entry:
-%.pre = load %struct.CAMERA** %Camera_Ptr, align 4
-%0 = getelementptr inbounds %struct.CAMERA* %.pre, i32 0, i32 1, i32 0
-%1 = getelementptr inbounds %struct.CAMERA* %.pre, i32 0, i32 1, i32 2
+%.pre = load %struct.CAMERA*, %struct.CAMERA** %Camera_Ptr, align 4
+%0 = getelementptr inbounds %struct.CAMERA, %struct.CAMERA* %.pre, i32 0, i32 1, i32 0
+%1 = getelementptr inbounds %struct.CAMERA, %struct.CAMERA* %.pre, i32 0, i32 1, i32 2
 br label %bb32
 
 bb32:                                             ; preds = %bb6
-%2 = load double* %0, align 4
-%3 = load double* %1, align 4
-%4 = load double* %0, align 4
+%2 = load double, double* %0, align 4
+%3 = load double, double* %1, align 4
+%4 = load double, double* %0, align 4
 call void @Parse_Vector(double* %0) nounwind
 %5 = call i32 @llvm.objectsize.i32.p0i8(i8* undef, i1 false)
 %6 = icmp eq i32 %5, -1
@@ -50,14 +50,14 @@ for.body.i:                                       ; preds = %for.body.i, %entry
   br i1 undef, label %func_74.exit.for.cond29.thread_crit_edge, label %for.body.i
 
 func_74.exit.for.cond29.thread_crit_edge:         ; preds = %for.body.i
-  %f13576.pre = getelementptr inbounds %struct.S0* undef, i64 0, i32 1
+  %f13576.pre = getelementptr inbounds %struct.S0, %struct.S0* undef, i64 0, i32 1
   store i8 0, i8* %f13576.pre, align 4
   br label %lbl_468
 
 lbl_468:                                          ; preds = %lbl_468, %func_74.exit.for.cond29.thread_crit_edge
   %f13577.ph = phi i8* [ %f13576.pre, %func_74.exit.for.cond29.thread_crit_edge ], [ %f135.pre, %lbl_468 ]
   store i8 1, i8* %f13577.ph, align 1
-  %f135.pre = getelementptr inbounds %struct.S0* undef, i64 0, i32 1
+  %f135.pre = getelementptr inbounds %struct.S0, %struct.S0* undef, i64 0, i32 1
   br i1 undef, label %lbl_468, label %for.end74
 
 for.end74:                                        ; preds = %lbl_468
diff --git a/test/CodeGen/Generic/dag-combine-crash.ll b/test/CodeGen/Generic/dag-combine-crash.ll
index a7810b5c05e2..45abd1d92edc 100644
--- a/test/CodeGen/Generic/dag-combine-crash.ll
+++ b/test/CodeGen/Generic/dag-combine-crash.ll
@@ -5,7 +5,7 @@ if.end:
   br label %block.i.i
 
 block.i.i:
-  %tmpbb = load i8* undef
+  %tmpbb = load i8, i8* undef
   %tmp54 = zext i8 %tmpbb to i64
   %tmp59 = and i64 %tmp54, 8
   %tmp60 = add i64 %tmp59, 3691045929300498764
diff --git a/test/CodeGen/Generic/dbg_value.ll b/test/CodeGen/Generic/dbg_value.ll
index ed7bdbad1822..4038086cbb4e 100644
--- a/test/CodeGen/Generic/dbg_value.ll
+++ b/test/CodeGen/Generic/dbg_value.ll
@@ -4,11 +4,11 @@
 %0 = type { i32, i32 }
 
 define void @t(%0*, i32, i32, i32, i32) nounwind {
-  tail call void @llvm.dbg.value(metadata %0* %0, i64 0, metadata !0, metadata !{!"0x102"})
+  tail call void @llvm.dbg.value(metadata %0* %0, i64 0, metadata !0, metadata !DIExpression()), !dbg !DILocation(scope: !DISubprogram())
   unreachable
 }
 
 declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone
 
 ; !0 should conform to the format of DIVariable.
-!0 = !{!"0x101\00a\000\000", null, null, null} ; [ DW_TAG_arg_variable ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", arg: 0, scope: !DISubprogram())
diff --git a/test/CodeGen/Generic/empty-load-store.ll b/test/CodeGen/Generic/empty-load-store.ll
index bca73054447c..32ece8b9f07b 100644
--- a/test/CodeGen/Generic/empty-load-store.ll
+++ b/test/CodeGen/Generic/empty-load-store.ll
@@ -8,11 +8,11 @@ entry:
         %retval = alloca i32
         store i32 0, i32* %retval
         %local_foo = alloca {  }
-        load {  }* @current_foo
+        load {  }, {  }* @current_foo
         store {  } %0, {  }* %local_foo
         br label %return
 
 return:
-        load i32* %retval
+        load i32, i32* %retval
         ret i32 %1
 }
diff --git a/test/CodeGen/Generic/empty-phi.ll b/test/CodeGen/Generic/empty-phi.ll
index 8d5f3b96941c..f9191b95f42e 100644
--- a/test/CodeGen/Generic/empty-phi.ll
+++ b/test/CodeGen/Generic/empty-phi.ll
@@ -11,7 +11,7 @@ bb1:
   br i1 %1, label %bb2, label %bb3
 
 bb2:
-  %load = load [0 x { i8*, i64, i64 }]* undef, align 8
+  %load = load [0 x { i8*, i64, i64 }], [0 x { i8*, i64, i64 }]* undef, align 8
   br label %bb1
 
 bb3:
diff --git a/test/CodeGen/Generic/fastcall.ll b/test/CodeGen/Generic/fastcall.ll
index 35e04f1863a3..b78bb1940c2b 100644
--- a/test/CodeGen/Generic/fastcall.ll
+++ b/test/CodeGen/Generic/fastcall.ll
@@ -7,7 +7,7 @@
 
 define fastcc void @gcov_read_words(i32 %words) {
 entry:
-        store i32 %words, i32* getelementptr (%struct.__gcov_var* 
+        store i32 %words, i32* getelementptr (%struct.__gcov_var, %struct.__gcov_var* 
 @__gcov_var,
 i32 0, i32 0)
         ret void
diff --git a/test/CodeGen/Generic/fp-to-int-invalid.ll b/test/CodeGen/Generic/fp-to-int-invalid.ll
index cdcc3a277b6e..6a37660d68dc 100644
--- a/test/CodeGen/Generic/fp-to-int-invalid.ll
+++ b/test/CodeGen/Generic/fp-to-int-invalid.ll
@@ -7,9 +7,9 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store i8* %result, i8** %result_addr
 	store float 0x40B2AFA160000000, float* %test, align 4
-	%0 = load float* %test, align 4		; <float> [#uses=1]
+	%0 = load float, float* %test, align 4		; <float> [#uses=1]
 	%1 = fptosi float %0 to i8		; <i8> [#uses=1]
-	%2 = load i8** %result_addr, align 4		; <i8*> [#uses=1]
+	%2 = load i8*, i8** %result_addr, align 4		; <i8*> [#uses=1]
 	store i8 %1, i8* %2, align 1
 	br label %return
 
diff --git a/test/CodeGen/Generic/fwdtwice.ll b/test/CodeGen/Generic/fwdtwice.ll
index 6b38f04673de..0c0bfad7d4c7 100644
--- a/test/CodeGen/Generic/fwdtwice.ll
+++ b/test/CodeGen/Generic/fwdtwice.ll
@@ -18,7 +18,7 @@ define i32 @SumArray(i32 %Num) {
 
 Top:            ; preds = %Top, %0
         store i32 %Num, i32* %Num.upgrd.1
-        %reg108 = load i32* %Num.upgrd.1                ; <i32> [#uses=1]
+        %reg108 = load i32, i32* %Num.upgrd.1                ; <i32> [#uses=1]
         %cast1006 = bitcast i32 %reg108 to i32          ; <i32> [#uses=1]
         %cond1001 = icmp ule i32 %cast1006, 0           ; <i1> [#uses=1]
         br i1 %cond1001, label %bb6, label %Top
diff --git a/test/CodeGen/Generic/global-ret0.ll b/test/CodeGen/Generic/global-ret0.ll
index 74bff876f882..a2a24b06127b 100644
--- a/test/CodeGen/Generic/global-ret0.ll
+++ b/test/CodeGen/Generic/global-ret0.ll
@@ -3,6 +3,6 @@
 @g = global i32 0               ; <i32*> [#uses=1]
 
 define i32 @main() {
-        %h = load i32* @g               ; <i32> [#uses=1]
+        %h = load i32, i32* @g               ; <i32> [#uses=1]
         ret i32 %h
 }
diff --git a/test/CodeGen/Generic/hello.ll b/test/CodeGen/Generic/hello.ll
index 705945cf1983..a8147da744d6 100644
--- a/test/CodeGen/Generic/hello.ll
+++ b/test/CodeGen/Generic/hello.ll
@@ -5,7 +5,7 @@
 declare i32 @printf(i8*, ...)
 
 define i32 @main() {
-        %s = getelementptr [7 x i8]* @.str_1, i64 0, i64 0              ; <i8*> [#uses=1]
-        call i32 (i8*, ...)* @printf( i8* %s )          ; <i32>:1 [#uses=0]
+        %s = getelementptr [7 x i8], [7 x i8]* @.str_1, i64 0, i64 0              ; <i8*> [#uses=1]
+        call i32 (i8*, ...) @printf( i8* %s )          ; <i32>:1 [#uses=0]
         ret i32 0
 }
diff --git a/test/CodeGen/Generic/icmp-illegal.ll b/test/CodeGen/Generic/icmp-illegal.ll
new file mode 100644
index 000000000000..23d20c04652f
--- /dev/null
+++ b/test/CodeGen/Generic/icmp-illegal.ll
@@ -0,0 +1,50 @@
+
+; RUN: llc < %s | FileCheck %s
+
+; CHECK-LABEL: test_ult
+define i1 @test_ult(i256 %a) nounwind {
+  %1 = icmp ult i256 %a, -6432394258550908438
+  ret i1 %1
+}
+
+; CHECK-LABEL: test_ule
+define i1 @test_ule(i256 %a) nounwind {
+  %1 = icmp ule i256 %a, -6432394258550908438
+  ret i1 %1
+}
+
+; CHECK-LABEL: test_ugt
+define i1 @test_ugt(i256 %a) nounwind {
+  %1 = icmp ugt i256 %a, -6432394258550908438
+  ret i1 %1
+}
+
+; CHECK-LABEL: test_uge
+define i1 @test_uge(i256 %a) nounwind {
+  %1 = icmp uge i256 %a, -6432394258550908438
+  ret i1 %1
+}
+
+; CHECK-LABEL: test_slt
+define i1 @test_slt(i256 %a) nounwind {
+  %1 = icmp slt i256 %a, -6432394258550908438
+  ret i1 %1
+}
+
+; CHECK-LABEL: test_sle
+define i1 @test_sle(i256 %a) nounwind {
+  %1 = icmp sle i256 %a, -6432394258550908438
+  ret i1 %1
+}
+
+; CHECK-LABEL: test_sgt
+define i1 @test_sgt(i256 %a) nounwind {
+  %1 = icmp sgt i256 %a, -6432394258550908438
+  ret i1 %1
+}
+
+; CHECK-LABEL: test_sge
+define i1 @test_sge(i256 %a) nounwind {
+  %1 = icmp sge i256 %a, -6432394258550908438
+  ret i1 %1
+}
diff --git a/test/CodeGen/Generic/inline-asm-mem-clobber.ll b/test/CodeGen/Generic/inline-asm-mem-clobber.ll
index 5aa827a0ab88..be1e0a39b3b0 100644
--- a/test/CodeGen/Generic/inline-asm-mem-clobber.ll
+++ b/test/CodeGen/Generic/inline-asm-mem-clobber.ll
@@ -8,13 +8,13 @@ entry:
   %rv = alloca i32, align 4
   store i8* %p, i8** %p.addr, align 8
   store i32 0, i32* @G, align 4
-  %0 = load i8** %p.addr, align 8
+  %0 = load i8*, i8** %p.addr, align 8
 ; CHECK: blah
   %1 = call i32 asm "blah", "=r,r,~{memory}"(i8* %0) nounwind
 ; CHECK: @G
   store i32 %1, i32* %rv, align 4
-  %2 = load i32* %rv, align 4
-  %3 = load i32* @G, align 4
+  %2 = load i32, i32* %rv, align 4
+  %3 = load i32, i32* @G, align 4
   %add = add nsw i32 %2, %3
   ret i32 %add
 }
diff --git a/test/CodeGen/Generic/invalid-memcpy.ll b/test/CodeGen/Generic/invalid-memcpy.ll
index 2dfa28bac482..d4252bc9d988 100644
--- a/test/CodeGen/Generic/invalid-memcpy.ll
+++ b/test/CodeGen/Generic/invalid-memcpy.ll
@@ -10,7 +10,7 @@ define void @Bork() {
 entry:
   %Qux = alloca [33 x i8]
   %Qux1 = bitcast [33 x i8]* %Qux to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %Qux1, i8* getelementptr inbounds ([33 x i8]* @C.0.1173, i32 0, i32 0), i64 33, i32 8, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %Qux1, i8* getelementptr inbounds ([33 x i8], [33 x i8]* @C.0.1173, i32 0, i32 0), i64 33, i32 8, i1 false)
   ret void
 }
 
diff --git a/test/CodeGen/Generic/negintconst.ll b/test/CodeGen/Generic/negintconst.ll
index 67d775e16882..4c0a654a87c2 100644
--- a/test/CodeGen/Generic/negintconst.ll
+++ b/test/CodeGen/Generic/negintconst.ll
@@ -39,9 +39,9 @@ define i32 @main() {
         %iscale = mul i32 %i, -1                ; <i32> [#uses=1]
         %ioff = add i32 %iscale, 3              ; <i32> [#uses=2]
         %ioff.upgrd.1 = zext i32 %ioff to i64           ; <i64> [#uses=1]
-        %fptr = getelementptr %Results* %fval, i64 %ioff.upgrd.1                ; <%Results*> [#uses=1]
-        %castFmt = getelementptr [39 x i8]* @fmtArg, i64 0, i64 0               ; <i8*> [#uses=1]
-        call i32 (i8*, ...)* @printf( i8* %castFmt, i32 %ioff, %Results* %fval, %Results* %fptr )               ; <i32>:1 [#uses=0]
+        %fptr = getelementptr %Results, %Results* %fval, i64 %ioff.upgrd.1                ; <%Results*> [#uses=1]
+        %castFmt = getelementptr [39 x i8], [39 x i8]* @fmtArg, i64 0, i64 0               ; <i8*> [#uses=1]
+        call i32 (i8*, ...) @printf( i8* %castFmt, i32 %ioff, %Results* %fval, %Results* %fptr )               ; <i32>:1 [#uses=0]
         ret i32 0
 }
 
diff --git a/test/CodeGen/Generic/overloaded-intrinsic-name.ll b/test/CodeGen/Generic/overloaded-intrinsic-name.ll
new file mode 100644
index 000000000000..979bc772f75f
--- /dev/null
+++ b/test/CodeGen/Generic/overloaded-intrinsic-name.ll
@@ -0,0 +1,57 @@
+; RUN: opt -verify -S < %s
+
+; Tests the name mangling performed by the codepath following
+; getMangledTypeStr(). Only tests that code with the various manglings
+; run fine: doesn't actually test the mangling with the type of the
+; arguments. Meant to serve as an example-document on how the user
+; should do name manglings.
+
+; Exercise the most general case, llvm_anyptr_type, using gc.relocate
+; and gc.statepoint. Note that it has nothing to do with gc.*
+; functions specifically: any function that accepts llvm_anyptr_type
+; will serve the purpose.
+
+; function and integer
+define i32* @test_iAny(i32* %v) gc "statepoint-example" {
+       %tok = call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, i32* %v)
+       %v-new = call i32* @llvm.experimental.gc.relocate.p0i32(i32 %tok,  i32 7, i32 7)
+       ret i32* %v-new
+}
+
+; float
+define float* @test_fAny(float* %v) gc "statepoint-example" {
+       %tok = call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, float* %v)
+       %v-new = call float* @llvm.experimental.gc.relocate.p0f32(i32 %tok,  i32 7, i32 7)
+       ret float* %v-new
+}
+
+; array of integers
+define [3 x i32]* @test_aAny([3 x i32]* %v) gc "statepoint-example" {
+       %tok = call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, [3 x i32]* %v)
+       %v-new = call [3 x i32]* @llvm.experimental.gc.relocate.p0a3i32(i32 %tok,  i32 7, i32 7)
+       ret [3 x i32]* %v-new
+}
+
+; vector of integers
+define <3 x i32>* @test_vAny(<3 x i32>* %v) gc "statepoint-example" {
+       %tok = call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, <3 x i32>* %v)
+       %v-new = call <3 x i32>* @llvm.experimental.gc.relocate.p0v3i32(i32 %tok,  i32 7, i32 7)
+       ret <3 x i32>* %v-new
+}
+
+%struct.test = type { i32, i1 }
+
+; struct
+define %struct.test* @test_struct(%struct.test* %v) gc "statepoint-example" {
+       %tok = call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, %struct.test* %v)
+       %v-new = call %struct.test* @llvm.experimental.gc.relocate.p0struct.test(i32 %tok,  i32 7, i32 7)
+       ret %struct.test* %v-new
+}
+
+declare zeroext i1 @return_i1()
+declare i32 @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i32, ...)
+declare i32* @llvm.experimental.gc.relocate.p0i32(i32, i32, i32)
+declare float* @llvm.experimental.gc.relocate.p0f32(i32, i32, i32)
+declare [3 x i32]* @llvm.experimental.gc.relocate.p0a3i32(i32, i32, i32)
+declare <3 x i32>* @llvm.experimental.gc.relocate.p0v3i32(i32, i32, i32)
+declare %struct.test* @llvm.experimental.gc.relocate.p0struct.test(i32, i32, i32)
diff --git a/test/CodeGen/Generic/pr2625.ll b/test/CodeGen/Generic/pr2625.ll
index 3e3dc4b2d2bc..c745603c08a2 100644
--- a/test/CodeGen/Generic/pr2625.ll
+++ b/test/CodeGen/Generic/pr2625.ll
@@ -7,11 +7,11 @@ entry:
         store { i32, { i32 } }* %0, { i32, { i32 } }** %state
         %retval = alloca i32            ; <i32*> [#uses=2]
         store i32 0, i32* %retval
-        load { i32, { i32 } }** %state          ; <{ i32, { i32 } }*>:1 [#uses=1]
+        load { i32, { i32 } }*, { i32, { i32 } }** %state          ; <{ i32, { i32 } }*>:1 [#uses=1]
         store { i32, { i32 } } zeroinitializer, { i32, { i32 } }* %1
         br label %return
 
 return:         ; preds = %entry
-        load i32* %retval               ; <i32>:2 [#uses=1]
+        load i32, i32* %retval               ; <i32>:2 [#uses=1]
         ret i32 %2
 }
diff --git a/test/CodeGen/Generic/print-add.ll b/test/CodeGen/Generic/print-add.ll
index 95608dc60b50..0507aba317b5 100644
--- a/test/CodeGen/Generic/print-add.ll
+++ b/test/CodeGen/Generic/print-add.ll
@@ -5,14 +5,14 @@
 declare i32 @printf(i8*, ...)
 
 define i32 @main() {
-        %f = getelementptr [4 x i8]* @.str_1, i64 0, i64 0              ; <i8*> [#uses=3]
+        %f = getelementptr [4 x i8], [4 x i8]* @.str_1, i64 0, i64 0              ; <i8*> [#uses=3]
         %d = add i32 1, 0               ; <i32> [#uses=3]
-        call i32 (i8*, ...)* @printf( i8* %f, i32 %d )          ; <i32>:1 [#uses=0]
+        call i32 (i8*, ...) @printf( i8* %f, i32 %d )          ; <i32>:1 [#uses=0]
         %e = add i32 38, 2              ; <i32> [#uses=2]
-        call i32 (i8*, ...)* @printf( i8* %f, i32 %e )          ; <i32>:2 [#uses=0]
+        call i32 (i8*, ...) @printf( i8* %f, i32 %e )          ; <i32>:2 [#uses=0]
         %g = add i32 %d, %d             ; <i32> [#uses=1]
         %h = add i32 %e, %g             ; <i32> [#uses=1]
-        call i32 (i8*, ...)* @printf( i8* %f, i32 %h )          ; <i32>:3 [#uses=0]
+        call i32 (i8*, ...) @printf( i8* %f, i32 %h )          ; <i32>:3 [#uses=0]
         ret i32 0
 }
 
diff --git a/test/CodeGen/Generic/print-arith-fp.ll b/test/CodeGen/Generic/print-arith-fp.ll
index d129ff85870e..93b158e10343 100644
--- a/test/CodeGen/Generic/print-arith-fp.ll
+++ b/test/CodeGen/Generic/print-arith-fp.ll
@@ -18,44 +18,44 @@
 declare i32 @printf(i8*, ...)
 
 define i32 @main() {
-	%a = load double* @A		; <double> [#uses=12]
-	%b = load double* @B		; <double> [#uses=12]
-	%a_s = getelementptr [8 x i8]* @a_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%b_s = getelementptr [8 x i8]* @b_str, i64 0, i64 0		; <i8*> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %a_s, double %a )		; <i32>:1 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %b_s, double %b )		; <i32>:2 [#uses=0]
+	%a = load double, double* @A		; <double> [#uses=12]
+	%b = load double, double* @B		; <double> [#uses=12]
+	%a_s = getelementptr [8 x i8], [8 x i8]* @a_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%b_s = getelementptr [8 x i8], [8 x i8]* @b_str, i64 0, i64 0		; <i8*> [#uses=1]
+	call i32 (i8*, ...) @printf( i8* %a_s, double %a )		; <i32>:1 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %b_s, double %b )		; <i32>:2 [#uses=0]
 	%add_r = fadd double %a, %b		; <double> [#uses=1]
 	%sub_r = fsub double %a, %b		; <double> [#uses=1]
 	%mul_r = fmul double %a, %b		; <double> [#uses=1]
 	%div_r = fdiv double %b, %a		; <double> [#uses=1]
 	%rem_r = frem double %b, %a		; <double> [#uses=1]
-	%add_s = getelementptr [12 x i8]* @add_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%sub_s = getelementptr [12 x i8]* @sub_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%mul_s = getelementptr [12 x i8]* @mul_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%div_s = getelementptr [12 x i8]* @div_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%rem_s = getelementptr [13 x i8]* @rem_str, i64 0, i64 0		; <i8*> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %add_s, double %add_r )		; <i32>:3 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %sub_s, double %sub_r )		; <i32>:4 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %mul_s, double %mul_r )		; <i32>:5 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %div_s, double %div_r )		; <i32>:6 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %rem_s, double %rem_r )		; <i32>:7 [#uses=0]
+	%add_s = getelementptr [12 x i8], [12 x i8]* @add_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%sub_s = getelementptr [12 x i8], [12 x i8]* @sub_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%mul_s = getelementptr [12 x i8], [12 x i8]* @mul_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%div_s = getelementptr [12 x i8], [12 x i8]* @div_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%rem_s = getelementptr [13 x i8], [13 x i8]* @rem_str, i64 0, i64 0		; <i8*> [#uses=1]
+	call i32 (i8*, ...) @printf( i8* %add_s, double %add_r )		; <i32>:3 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %sub_s, double %sub_r )		; <i32>:4 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %mul_s, double %mul_r )		; <i32>:5 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %div_s, double %div_r )		; <i32>:6 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %rem_s, double %rem_r )		; <i32>:7 [#uses=0]
 	%lt_r = fcmp olt double %a, %b		; <i1> [#uses=1]
 	%le_r = fcmp ole double %a, %b		; <i1> [#uses=1]
 	%gt_r = fcmp ogt double %a, %b		; <i1> [#uses=1]
 	%ge_r = fcmp oge double %a, %b		; <i1> [#uses=1]
 	%eq_r = fcmp oeq double %a, %b		; <i1> [#uses=1]
 	%ne_r = fcmp une double %a, %b		; <i1> [#uses=1]
-	%lt_s = getelementptr [12 x i8]* @lt_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%le_s = getelementptr [13 x i8]* @le_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%gt_s = getelementptr [12 x i8]* @gt_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%ge_s = getelementptr [13 x i8]* @ge_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%eq_s = getelementptr [13 x i8]* @eq_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0		; <i8*> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %lt_s, i1 %lt_r )		; <i32>:8 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %le_s, i1 %le_r )		; <i32>:9 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %gt_s, i1 %gt_r )		; <i32>:10 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %ge_s, i1 %ge_r )		; <i32>:11 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %eq_s, i1 %eq_r )		; <i32>:12 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %ne_s, i1 %ne_r )		; <i32>:13 [#uses=0]
+	%lt_s = getelementptr [12 x i8], [12 x i8]* @lt_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%le_s = getelementptr [13 x i8], [13 x i8]* @le_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%gt_s = getelementptr [12 x i8], [12 x i8]* @gt_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%ge_s = getelementptr [13 x i8], [13 x i8]* @ge_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%eq_s = getelementptr [13 x i8], [13 x i8]* @eq_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%ne_s = getelementptr [13 x i8], [13 x i8]* @ne_str, i64 0, i64 0		; <i8*> [#uses=1]
+	call i32 (i8*, ...) @printf( i8* %lt_s, i1 %lt_r )		; <i32>:8 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %le_s, i1 %le_r )		; <i32>:9 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %gt_s, i1 %gt_r )		; <i32>:10 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %ge_s, i1 %ge_r )		; <i32>:11 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %eq_s, i1 %eq_r )		; <i32>:12 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %ne_s, i1 %ne_r )		; <i32>:13 [#uses=0]
 	ret i32 0
 }
diff --git a/test/CodeGen/Generic/print-arith-int.ll b/test/CodeGen/Generic/print-arith-int.ll
index ce938cf05b98..a5c519c0c7fc 100644
--- a/test/CodeGen/Generic/print-arith-int.ll
+++ b/test/CodeGen/Generic/print-arith-int.ll
@@ -23,45 +23,45 @@
 declare i32 @printf(i8*, ...)
 
 define i32 @main() {
-	%a = load i32* @A		; <i32> [#uses=16]
-	%b = load i32* @B		; <i32> [#uses=17]
-	%a_s = getelementptr [8 x i8]* @a_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%b_s = getelementptr [8 x i8]* @b_str, i64 0, i64 0		; <i8*> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %a_s, i32 %a )		; <i32>:1 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %b_s, i32 %b )		; <i32>:2 [#uses=0]
+	%a = load i32, i32* @A		; <i32> [#uses=16]
+	%b = load i32, i32* @B		; <i32> [#uses=17]
+	%a_s = getelementptr [8 x i8], [8 x i8]* @a_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%b_s = getelementptr [8 x i8], [8 x i8]* @b_str, i64 0, i64 0		; <i8*> [#uses=1]
+	call i32 (i8*, ...) @printf( i8* %a_s, i32 %a )		; <i32>:1 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %b_s, i32 %b )		; <i32>:2 [#uses=0]
 	%add_r = add i32 %a, %b		; <i32> [#uses=1]
 	%sub_r = sub i32 %a, %b		; <i32> [#uses=1]
 	%mul_r = mul i32 %a, %b		; <i32> [#uses=1]
 	%div_r = sdiv i32 %b, %a		; <i32> [#uses=1]
 	%rem_r = srem i32 %b, %a		; <i32> [#uses=1]
-	%add_s = getelementptr [12 x i8]* @add_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%sub_s = getelementptr [12 x i8]* @sub_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%mul_s = getelementptr [12 x i8]* @mul_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%div_s = getelementptr [12 x i8]* @div_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%rem_s = getelementptr [13 x i8]* @rem_str, i64 0, i64 0		; <i8*> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %add_s, i32 %add_r )		; <i32>:3 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %sub_s, i32 %sub_r )		; <i32>:4 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %mul_s, i32 %mul_r )		; <i32>:5 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %div_s, i32 %div_r )		; <i32>:6 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %rem_s, i32 %rem_r )		; <i32>:7 [#uses=0]
+	%add_s = getelementptr [12 x i8], [12 x i8]* @add_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%sub_s = getelementptr [12 x i8], [12 x i8]* @sub_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%mul_s = getelementptr [12 x i8], [12 x i8]* @mul_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%div_s = getelementptr [12 x i8], [12 x i8]* @div_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%rem_s = getelementptr [13 x i8], [13 x i8]* @rem_str, i64 0, i64 0		; <i8*> [#uses=1]
+	call i32 (i8*, ...) @printf( i8* %add_s, i32 %add_r )		; <i32>:3 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %sub_s, i32 %sub_r )		; <i32>:4 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %mul_s, i32 %mul_r )		; <i32>:5 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %div_s, i32 %div_r )		; <i32>:6 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %rem_s, i32 %rem_r )		; <i32>:7 [#uses=0]
 	%lt_r = icmp slt i32 %a, %b		; <i1> [#uses=1]
 	%le_r = icmp sle i32 %a, %b		; <i1> [#uses=1]
 	%gt_r = icmp sgt i32 %a, %b		; <i1> [#uses=1]
 	%ge_r = icmp sge i32 %a, %b		; <i1> [#uses=1]
 	%eq_r = icmp eq i32 %a, %b		; <i1> [#uses=1]
 	%ne_r = icmp ne i32 %a, %b		; <i1> [#uses=1]
-	%lt_s = getelementptr [12 x i8]* @lt_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%le_s = getelementptr [13 x i8]* @le_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%gt_s = getelementptr [12 x i8]* @gt_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%ge_s = getelementptr [13 x i8]* @ge_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%eq_s = getelementptr [13 x i8]* @eq_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0		; <i8*> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %lt_s, i1 %lt_r )		; <i32>:8 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %le_s, i1 %le_r )		; <i32>:9 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %gt_s, i1 %gt_r )		; <i32>:10 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %ge_s, i1 %ge_r )		; <i32>:11 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %eq_s, i1 %eq_r )		; <i32>:12 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %ne_s, i1 %ne_r )		; <i32>:13 [#uses=0]
+	%lt_s = getelementptr [12 x i8], [12 x i8]* @lt_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%le_s = getelementptr [13 x i8], [13 x i8]* @le_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%gt_s = getelementptr [12 x i8], [12 x i8]* @gt_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%ge_s = getelementptr [13 x i8], [13 x i8]* @ge_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%eq_s = getelementptr [13 x i8], [13 x i8]* @eq_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%ne_s = getelementptr [13 x i8], [13 x i8]* @ne_str, i64 0, i64 0		; <i8*> [#uses=1]
+	call i32 (i8*, ...) @printf( i8* %lt_s, i1 %lt_r )		; <i32>:8 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %le_s, i1 %le_r )		; <i32>:9 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %gt_s, i1 %gt_r )		; <i32>:10 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %ge_s, i1 %ge_r )		; <i32>:11 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %eq_s, i1 %eq_r )		; <i32>:12 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %ne_s, i1 %ne_r )		; <i32>:13 [#uses=0]
 	%and_r = and i32 %a, %b		; <i32> [#uses=1]
 	%or_r = or i32 %a, %b		; <i32> [#uses=1]
 	%xor_r = xor i32 %a, %b		; <i32> [#uses=1]
@@ -70,15 +70,15 @@ define i32 @main() {
 	%shl_r = shl i32 %b, %shift.upgrd.1		; <i32> [#uses=1]
 	%shift.upgrd.2 = zext i8 %u to i32		; <i32> [#uses=1]
 	%shr_r = ashr i32 %b, %shift.upgrd.2		; <i32> [#uses=1]
-	%and_s = getelementptr [12 x i8]* @and_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%or_s = getelementptr [12 x i8]* @or_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%xor_s = getelementptr [12 x i8]* @xor_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%shl_s = getelementptr [13 x i8]* @shl_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%shr_s = getelementptr [13 x i8]* @shr_str, i64 0, i64 0		; <i8*> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %and_s, i32 %and_r )		; <i32>:14 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %or_s, i32 %or_r )		; <i32>:15 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %xor_s, i32 %xor_r )		; <i32>:16 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %shl_s, i32 %shl_r )		; <i32>:17 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %shr_s, i32 %shr_r )		; <i32>:18 [#uses=0]
+	%and_s = getelementptr [12 x i8], [12 x i8]* @and_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%or_s = getelementptr [12 x i8], [12 x i8]* @or_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%xor_s = getelementptr [12 x i8], [12 x i8]* @xor_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%shl_s = getelementptr [13 x i8], [13 x i8]* @shl_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%shr_s = getelementptr [13 x i8], [13 x i8]* @shr_str, i64 0, i64 0		; <i8*> [#uses=1]
+	call i32 (i8*, ...) @printf( i8* %and_s, i32 %and_r )		; <i32>:14 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %or_s, i32 %or_r )		; <i32>:15 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %xor_s, i32 %xor_r )		; <i32>:16 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %shl_s, i32 %shl_r )		; <i32>:17 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %shr_s, i32 %shr_r )		; <i32>:18 [#uses=0]
 	ret i32 0
 }
diff --git a/test/CodeGen/Generic/print-int.ll b/test/CodeGen/Generic/print-int.ll
index 7ca4b3de48a3..85b40c0e24f7 100644
--- a/test/CodeGen/Generic/print-int.ll
+++ b/test/CodeGen/Generic/print-int.ll
@@ -5,9 +5,9 @@
 declare i32 @printf(i8*, ...)
 
 define i32 @main() {
-        %f = getelementptr [4 x i8]* @.str_1, i64 0, i64 0              ; <i8*> [#uses=1]
+        %f = getelementptr [4 x i8], [4 x i8]* @.str_1, i64 0, i64 0              ; <i8*> [#uses=1]
         %d = add i32 0, 0               ; <i32> [#uses=1]
-        %tmp.0 = call i32 (i8*, ...)* @printf( i8* %f, i32 %d )         ; <i32> [#uses=0]
+        %tmp.0 = call i32 (i8*, ...) @printf( i8* %f, i32 %d )         ; <i32> [#uses=0]
         ret i32 0
 }
 
diff --git a/test/CodeGen/Generic/print-mul-exp.ll b/test/CodeGen/Generic/print-mul-exp.ll
index 90fc55b25838..91c8147aaad9 100644
--- a/test/CodeGen/Generic/print-mul-exp.ll
+++ b/test/CodeGen/Generic/print-mul-exp.ll
@@ -7,10 +7,10 @@
 declare i32 @printf(i8*, ...)
 
 define i32 @main() {
-	%a = load i32* @A		; <i32> [#uses=21]
-	%a_s = getelementptr [8 x i8]* @a_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%a_mul_s = getelementptr [13 x i8]* @a_mul_str, i64 0, i64 0		; <i8*> [#uses=20]
-	call i32 (i8*, ...)* @printf( i8* %a_s, i32 %a )		; <i32>:1 [#uses=0]
+	%a = load i32, i32* @A		; <i32> [#uses=21]
+	%a_s = getelementptr [8 x i8], [8 x i8]* @a_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%a_mul_s = getelementptr [13 x i8], [13 x i8]* @a_mul_str, i64 0, i64 0		; <i8*> [#uses=20]
+	call i32 (i8*, ...) @printf( i8* %a_s, i32 %a )		; <i32>:1 [#uses=0]
 	%r_0 = mul i32 %a, 0		; <i32> [#uses=1]
 	%r_1 = mul i32 %a, 1		; <i32> [#uses=1]
 	%r_2 = mul i32 %a, 2		; <i32> [#uses=1]
@@ -31,25 +31,25 @@ define i32 @main() {
 	%r_17 = mul i32 %a, 17		; <i32> [#uses=1]
 	%r_18 = mul i32 %a, 18		; <i32> [#uses=1]
 	%r_19 = mul i32 %a, 19		; <i32> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 0, i32 %r_0 )		; <i32>:2 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 1, i32 %r_1 )		; <i32>:3 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 2, i32 %r_2 )		; <i32>:4 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 3, i32 %r_3 )		; <i32>:5 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 4, i32 %r_4 )		; <i32>:6 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 5, i32 %r_5 )		; <i32>:7 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 6, i32 %r_6 )		; <i32>:8 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 7, i32 %r_7 )		; <i32>:9 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 8, i32 %r_8 )		; <i32>:10 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 9, i32 %r_9 )		; <i32>:11 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 10, i32 %r_10 )		; <i32>:12 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 11, i32 %r_11 )		; <i32>:13 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 12, i32 %r_12 )		; <i32>:14 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 13, i32 %r_13 )		; <i32>:15 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 14, i32 %r_14 )		; <i32>:16 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 15, i32 %r_15 )		; <i32>:17 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 16, i32 %r_16 )		; <i32>:18 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 17, i32 %r_17 )		; <i32>:19 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 18, i32 %r_18 )		; <i32>:20 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 19, i32 %r_19 )		; <i32>:21 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 0, i32 %r_0 )		; <i32>:2 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 1, i32 %r_1 )		; <i32>:3 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 2, i32 %r_2 )		; <i32>:4 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 3, i32 %r_3 )		; <i32>:5 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 4, i32 %r_4 )		; <i32>:6 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 5, i32 %r_5 )		; <i32>:7 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 6, i32 %r_6 )		; <i32>:8 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 7, i32 %r_7 )		; <i32>:9 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 8, i32 %r_8 )		; <i32>:10 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 9, i32 %r_9 )		; <i32>:11 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 10, i32 %r_10 )		; <i32>:12 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 11, i32 %r_11 )		; <i32>:13 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 12, i32 %r_12 )		; <i32>:14 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 13, i32 %r_13 )		; <i32>:15 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 14, i32 %r_14 )		; <i32>:16 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 15, i32 %r_15 )		; <i32>:17 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 16, i32 %r_16 )		; <i32>:18 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 17, i32 %r_17 )		; <i32>:19 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 18, i32 %r_18 )		; <i32>:20 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 19, i32 %r_19 )		; <i32>:21 [#uses=0]
 	ret i32 0
 }
diff --git a/test/CodeGen/Generic/print-mul.ll b/test/CodeGen/Generic/print-mul.ll
index 0707f3c2318c..4b60d759278a 100644
--- a/test/CodeGen/Generic/print-mul.ll
+++ b/test/CodeGen/Generic/print-mul.ll
@@ -10,19 +10,19 @@ declare i32 @printf(i8*, ...)
 
 define i32 @main() {
 entry:
-	%a = load i32* @A		; <i32> [#uses=2]
-	%b = load i32* @B		; <i32> [#uses=1]
-	%a_s = getelementptr [8 x i8]* @a_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%b_s = getelementptr [8 x i8]* @b_str, i64 0, i64 0		; <i8*> [#uses=1]
-	%a_mul_s = getelementptr [13 x i8]* @a_mul_str, i64 0, i64 0		; <i8*> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %a_s, i32 %a )		; <i32>:0 [#uses=0]
-	call i32 (i8*, ...)* @printf( i8* %b_s, i32 %b )		; <i32>:1 [#uses=0]
+	%a = load i32, i32* @A		; <i32> [#uses=2]
+	%b = load i32, i32* @B		; <i32> [#uses=1]
+	%a_s = getelementptr [8 x i8], [8 x i8]* @a_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%b_s = getelementptr [8 x i8], [8 x i8]* @b_str, i64 0, i64 0		; <i8*> [#uses=1]
+	%a_mul_s = getelementptr [13 x i8], [13 x i8]* @a_mul_str, i64 0, i64 0		; <i8*> [#uses=1]
+	call i32 (i8*, ...) @printf( i8* %a_s, i32 %a )		; <i32>:0 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %b_s, i32 %b )		; <i32>:1 [#uses=0]
 	br label %shl_test
 
 shl_test:		; preds = %shl_test, %entry
 	%s = phi i32 [ 0, %entry ], [ %s_inc, %shl_test ]		; <i32> [#uses=4]
 	%result = mul i32 %a, %s		; <i32> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 %s, i32 %result )		; <i32>:2 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* %a_mul_s, i32 %s, i32 %result )		; <i32>:2 [#uses=0]
 	%s_inc = add i32 %s, 1		; <i32> [#uses=1]
 	%done = icmp eq i32 %s, 256		; <i1> [#uses=1]
 	br i1 %done, label %fini, label %shl_test
diff --git a/test/CodeGen/Generic/print-shift.ll b/test/CodeGen/Generic/print-shift.ll
index 6c5d222209be..56b3ec1df760 100644
--- a/test/CodeGen/Generic/print-shift.ll
+++ b/test/CodeGen/Generic/print-shift.ll
@@ -10,20 +10,20 @@ declare i32 @printf(i8*, ...)
 
 define i32 @main() {
 entry:
-        %a = load i32* @A               ; <i32> [#uses=2]
-        %b = load i32* @B               ; <i32> [#uses=1]
-        %a_s = getelementptr [8 x i8]* @a_str, i64 0, i64 0             ; <i8*> [#uses=1]
-        %b_s = getelementptr [8 x i8]* @b_str, i64 0, i64 0             ; <i8*> [#uses=1]
-        %a_shl_s = getelementptr [14 x i8]* @a_shl_str, i64 0, i64 0            ; <i8*> [#uses=1]
-        call i32 (i8*, ...)* @printf( i8* %a_s, i32 %a )                ; <i32>:0 [#uses=0]
-        call i32 (i8*, ...)* @printf( i8* %b_s, i32 %b )                ; <i32>:1 [#uses=0]
+        %a = load i32, i32* @A               ; <i32> [#uses=2]
+        %b = load i32, i32* @B               ; <i32> [#uses=1]
+        %a_s = getelementptr [8 x i8], [8 x i8]* @a_str, i64 0, i64 0             ; <i8*> [#uses=1]
+        %b_s = getelementptr [8 x i8], [8 x i8]* @b_str, i64 0, i64 0             ; <i8*> [#uses=1]
+        %a_shl_s = getelementptr [14 x i8], [14 x i8]* @a_shl_str, i64 0, i64 0            ; <i8*> [#uses=1]
+        call i32 (i8*, ...) @printf( i8* %a_s, i32 %a )                ; <i32>:0 [#uses=0]
+        call i32 (i8*, ...) @printf( i8* %b_s, i32 %b )                ; <i32>:1 [#uses=0]
         br label %shl_test
 
 shl_test:               ; preds = %shl_test, %entry
         %s = phi i8 [ 0, %entry ], [ %s_inc, %shl_test ]                ; <i8> [#uses=4]
         %shift.upgrd.1 = zext i8 %s to i32              ; <i32> [#uses=1]
         %result = shl i32 %a, %shift.upgrd.1            ; <i32> [#uses=1]
-        call i32 (i8*, ...)* @printf( i8* %a_shl_s, i8 %s, i32 %result )                ; <i32>:2 [#uses=0]
+        call i32 (i8*, ...) @printf( i8* %a_shl_s, i8 %s, i32 %result )                ; <i32>:2 [#uses=0]
         %s_inc = add i8 %s, 1           ; <i8> [#uses=1]
         %done = icmp eq i8 %s, 32               ; <i1> [#uses=1]
         br i1 %done, label %fini, label %shl_test
diff --git a/test/CodeGen/Generic/ptr-annotate.ll b/test/CodeGen/Generic/ptr-annotate.ll
index ac5bd5533e9e..4c10daa8223f 100644
--- a/test/CodeGen/Generic/ptr-annotate.ll
+++ b/test/CodeGen/Generic/ptr-annotate.ll
@@ -10,7 +10,7 @@
 define void @foo() {
 entry:
   %m = alloca i8, align 4
-  %0 = call i8* @llvm.ptr.annotation.p0i8(i8* %m, i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @.str1, i32 0, i32 0), i32 2)
+  %0 = call i8* @llvm.ptr.annotation.p0i8(i8* %m, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str1, i32 0, i32 0), i32 2)
   store i8 1, i8* %0, align 4
   ret void
 }
diff --git a/test/CodeGen/Generic/select.ll b/test/CodeGen/Generic/select.ll
index c4841b79acb6..1958cd9d71cb 100644
--- a/test/CodeGen/Generic/select.ll
+++ b/test/CodeGen/Generic/select.ll
@@ -70,7 +70,7 @@ define i32* @castconst(float) {
         %castsmall = trunc i64 1 to i32         ; <i32> [#uses=1]
         %usebig = add i32 %castbig, %castsmall          ; <i32> [#uses=0]
         %castglob = bitcast i32* @AConst to i64*                ; <i64*> [#uses=1]
-        %dummyl = load i64* %castglob           ; <i64> [#uses=0]
+        %dummyl = load i64, i64* %castglob           ; <i64> [#uses=0]
         %castnull = inttoptr i64 0 to i32*              ; <i32*> [#uses=1]
         ret i32* %castnull
 }
@@ -155,7 +155,7 @@ bb2:
         %cast116 = ptrtoint i32* %A to i64              ; <i64> [#uses=1]
         %reg116 = add i64 %cast116, %cast115            ; <i64> [#uses=1]
         %castPtr = inttoptr i64 %reg116 to i32*         ; <i32*> [#uses=1]
-        %reg118 = load i32* %castPtr            ; <i32> [#uses=1]
+        %reg118 = load i32, i32* %castPtr            ; <i32> [#uses=1]
         %cast117 = sext i32 %reg118 to i64              ; <i64> [#uses=2]
         %reg159 = add i64 1234567, %cast117             ; <i64> [#uses=0]
         %reg160 = add i64 7654321, %cast117             ; <i64> [#uses=0]
@@ -180,8 +180,8 @@ define void @checkNot(i1 %b, i32 %i) {
 ; Test case for folding getelementptr into a load/store
 ;
 define i32 @checkFoldGEP(%Domain* %D, i64 %idx) {
-        %reg841 = getelementptr %Domain* %D, i64 0, i32 1               ; <i32*> [#uses=1]
-        %reg820 = load i32* %reg841             ; <i32> [#uses=1]
+        %reg841 = getelementptr %Domain, %Domain* %D, i64 0, i32 1               ; <i32*> [#uses=1]
+        %reg820 = load i32, i32* %reg841             ; <i32> [#uses=1]
         ret i32 %reg820
 }
 
diff --git a/test/CodeGen/Generic/stop-after.ll b/test/CodeGen/Generic/stop-after.ll
index 5e0e350bc7fe..557e097840af 100644
--- a/test/CodeGen/Generic/stop-after.ll
+++ b/test/CodeGen/Generic/stop-after.ll
@@ -5,6 +5,6 @@
 ; STOP: Loop Strength Reduction
 ; STOP-NEXT: Machine Function Analysis
 
-; START: -machine-branch-prob -jump-instr-tables -gc-lowering
+; START: -machine-branch-prob -gc-lowering
 ; START: FunctionPass Manager
 ; START-NEXT: Lower Garbage Collection Instructions
diff --git a/test/CodeGen/Generic/undef-phi.ll b/test/CodeGen/Generic/undef-phi.ll
index 10899f9fa2db..03f3a6a2d1ba 100644
--- a/test/CodeGen/Generic/undef-phi.ll
+++ b/test/CodeGen/Generic/undef-phi.ll
@@ -13,14 +13,14 @@ entry:
 
 for.body:
   %stack.addr.02 = phi %struct.xx_stack* [ %0, %for.body ], [ %stack, %entry ]
-  %next = getelementptr inbounds %struct.xx_stack* %stack.addr.02, i64 0, i32 1
-  %0 = load %struct.xx_stack** %next, align 8
+  %next = getelementptr inbounds %struct.xx_stack, %struct.xx_stack* %stack.addr.02, i64 0, i32 1
+  %0 = load %struct.xx_stack*, %struct.xx_stack** %next, align 8
   %tobool = icmp eq %struct.xx_stack* %0, null
   br i1 %tobool, label %for.end, label %for.body
 
 for.end:
   %top.0.lcssa = phi %struct.xx_stack* [ undef, %entry ], [ %stack.addr.02, %for.body ]
-  %first = getelementptr inbounds %struct.xx_stack* %top.0.lcssa, i64 0, i32 0
-  %1 = load i32* %first, align 4
+  %first = getelementptr inbounds %struct.xx_stack, %struct.xx_stack* %top.0.lcssa, i64 0, i32 0
+  %1 = load i32, i32* %first, align 4
   ret i32 %1
 }
diff --git a/test/CodeGen/Generic/v-split.ll b/test/CodeGen/Generic/v-split.ll
index 634b5621aa99..00c62f389520 100644
--- a/test/CodeGen/Generic/v-split.ll
+++ b/test/CodeGen/Generic/v-split.ll
@@ -2,8 +2,8 @@
 %f8 = type <8 x float>
 
 define void @test_f8(%f8 *%P, %f8* %Q, %f8 *%S) {
-  %p = load %f8* %P
-  %q = load %f8* %Q
+  %p = load %f8, %f8* %P
+  %q = load %f8, %f8* %Q
   %R = fadd %f8 %p, %q
   store %f8 %R, %f8 *%S
   ret void
diff --git a/test/CodeGen/Generic/vector-casts.ll b/test/CodeGen/Generic/vector-casts.ll
index a26918b8f242..fee72b6b6585 100644
--- a/test/CodeGen/Generic/vector-casts.ll
+++ b/test/CodeGen/Generic/vector-casts.ll
@@ -2,43 +2,43 @@
 ; PR2671
 
 define void @a(<2 x double>* %p, <2 x i8>* %q) {
-        %t = load <2 x double>* %p
+        %t = load <2 x double>, <2 x double>* %p
 	%r = fptosi <2 x double> %t to <2 x i8>
         store <2 x i8> %r, <2 x i8>* %q
 	ret void
 }
 define void @b(<2 x double>* %p, <2 x i8>* %q) {
-        %t = load <2 x double>* %p
+        %t = load <2 x double>, <2 x double>* %p
 	%r = fptoui <2 x double> %t to <2 x i8>
         store <2 x i8> %r, <2 x i8>* %q
 	ret void
 }
 define void @c(<2 x i8>* %p, <2 x double>* %q) {
-        %t = load <2 x i8>* %p
+        %t = load <2 x i8>, <2 x i8>* %p
 	%r = sitofp <2 x i8> %t to <2 x double>
         store <2 x double> %r, <2 x double>* %q
 	ret void
 }
 define void @d(<2 x i8>* %p, <2 x double>* %q) {
-        %t = load <2 x i8>* %p
+        %t = load <2 x i8>, <2 x i8>* %p
 	%r = uitofp <2 x i8> %t to <2 x double>
         store <2 x double> %r, <2 x double>* %q
 	ret void
 }
 define void @e(<2 x i8>* %p, <2 x i16>* %q) {
-        %t = load <2 x i8>* %p
+        %t = load <2 x i8>, <2 x i8>* %p
 	%r = sext <2 x i8> %t to <2 x i16>
         store <2 x i16> %r, <2 x i16>* %q
 	ret void
 }
 define void @f(<2 x i8>* %p, <2 x i16>* %q) {
-        %t = load <2 x i8>* %p
+        %t = load <2 x i8>, <2 x i8>* %p
 	%r = zext <2 x i8> %t to <2 x i16>
         store <2 x i16> %r, <2 x i16>* %q
 	ret void
 }
 define void @g(<2 x i16>* %p, <2 x i8>* %q) {
-        %t = load <2 x i16>* %p
+        %t = load <2 x i16>, <2 x i16>* %p
 	%r = trunc <2 x i16> %t to <2 x i8>
         store <2 x i8> %r, <2 x i8>* %q
 	ret void
diff --git a/test/CodeGen/Generic/vector-identity-shuffle.ll b/test/CodeGen/Generic/vector-identity-shuffle.ll
index 332d6d8c2536..d933f222320d 100644
--- a/test/CodeGen/Generic/vector-identity-shuffle.ll
+++ b/test/CodeGen/Generic/vector-identity-shuffle.ll
@@ -2,7 +2,7 @@
 
 
 define void @test(<4 x float>* %tmp2.i) {
-        %tmp2.i.upgrd.1 = load <4 x float>* %tmp2.i             ; <<4 x float>> [#uses=4]
+        %tmp2.i.upgrd.1 = load <4 x float>, <4 x float>* %tmp2.i             ; <<4 x float>> [#uses=4]
         %xFloat0.48 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 0         ; <float> [#uses=1]
         %inFloat0.49 = insertelement <4 x float> undef, float %xFloat0.48, i32 0                ; <<4 x float>> [#uses=1]
         %xFloat1.50 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 1         ; <float> [#uses=1]
diff --git a/test/CodeGen/Generic/vector.ll b/test/CodeGen/Generic/vector.ll
index bc7c7d00a11c..962b1295b5de 100644
--- a/test/CodeGen/Generic/vector.ll
+++ b/test/CodeGen/Generic/vector.ll
@@ -1,6 +1,5 @@
 ; Test that vectors are scalarized/lowered correctly.
 ; RUN: llc < %s
-; XFAIL: hexagon
 
 %d8 = type <8 x double>
 %f1 = type <1 x float>
@@ -12,48 +11,48 @@
 ;;; TEST HANDLING OF VARIOUS VECTOR SIZES
 
 define void @test_f1(%f1* %P, %f1* %Q, %f1* %S) {
-	%p = load %f1* %P		; <%f1> [#uses=1]
-	%q = load %f1* %Q		; <%f1> [#uses=1]
+	%p = load %f1, %f1* %P		; <%f1> [#uses=1]
+	%q = load %f1, %f1* %Q		; <%f1> [#uses=1]
 	%R = fadd %f1 %p, %q		; <%f1> [#uses=1]
 	store %f1 %R, %f1* %S
 	ret void
 }
 
 define void @test_f2(%f2* %P, %f2* %Q, %f2* %S) {
-	%p = load %f2* %P		; <%f2> [#uses=1]
-	%q = load %f2* %Q		; <%f2> [#uses=1]
+	%p = load %f2, %f2* %P		; <%f2> [#uses=1]
+	%q = load %f2, %f2* %Q		; <%f2> [#uses=1]
 	%R = fadd %f2 %p, %q		; <%f2> [#uses=1]
 	store %f2 %R, %f2* %S
 	ret void
 }
 
 define void @test_f4(%f4* %P, %f4* %Q, %f4* %S) {
-	%p = load %f4* %P		; <%f4> [#uses=1]
-	%q = load %f4* %Q		; <%f4> [#uses=1]
+	%p = load %f4, %f4* %P		; <%f4> [#uses=1]
+	%q = load %f4, %f4* %Q		; <%f4> [#uses=1]
 	%R = fadd %f4 %p, %q		; <%f4> [#uses=1]
 	store %f4 %R, %f4* %S
 	ret void
 }
 
 define void @test_f8(%f8* %P, %f8* %Q, %f8* %S) {
-	%p = load %f8* %P		; <%f8> [#uses=1]
-	%q = load %f8* %Q		; <%f8> [#uses=1]
+	%p = load %f8, %f8* %P		; <%f8> [#uses=1]
+	%q = load %f8, %f8* %Q		; <%f8> [#uses=1]
 	%R = fadd %f8 %p, %q		; <%f8> [#uses=1]
 	store %f8 %R, %f8* %S
 	ret void
 }
 
 define void @test_fmul(%f8* %P, %f8* %Q, %f8* %S) {
-	%p = load %f8* %P		; <%f8> [#uses=1]
-	%q = load %f8* %Q		; <%f8> [#uses=1]
+	%p = load %f8, %f8* %P		; <%f8> [#uses=1]
+	%q = load %f8, %f8* %Q		; <%f8> [#uses=1]
 	%R = fmul %f8 %p, %q		; <%f8> [#uses=1]
 	store %f8 %R, %f8* %S
 	ret void
 }
 
 define void @test_div(%f8* %P, %f8* %Q, %f8* %S) {
-	%p = load %f8* %P		; <%f8> [#uses=1]
-	%q = load %f8* %Q		; <%f8> [#uses=1]
+	%p = load %f8, %f8* %P		; <%f8> [#uses=1]
+	%q = load %f8, %f8* %Q		; <%f8> [#uses=1]
 	%R = fdiv %f8 %p, %q		; <%f8> [#uses=1]
 	store %f8 %R, %f8* %S
 	ret void
@@ -63,21 +62,21 @@ define void @test_div(%f8* %P, %f8* %Q, %f8* %S) {
 
 
 define void @test_cst(%f4* %P, %f4* %S) {
-	%p = load %f4* %P		; <%f4> [#uses=1]
+	%p = load %f4, %f4* %P		; <%f4> [#uses=1]
 	%R = fadd %f4 %p, < float 0x3FB99999A0000000, float 1.000000e+00, float 2.000000e+00, float 4.500000e+00 >		; <%f4> [#uses=1]
 	store %f4 %R, %f4* %S
 	ret void
 }
 
 define void @test_zero(%f4* %P, %f4* %S) {
-	%p = load %f4* %P		; <%f4> [#uses=1]
+	%p = load %f4, %f4* %P		; <%f4> [#uses=1]
 	%R = fadd %f4 %p, zeroinitializer		; <%f4> [#uses=1]
 	store %f4 %R, %f4* %S
 	ret void
 }
 
 define void @test_undef(%f4* %P, %f4* %S) {
-	%p = load %f4* %P		; <%f4> [#uses=1]
+	%p = load %f4, %f4* %P		; <%f4> [#uses=1]
 	%R = fadd %f4 %p, undef		; <%f4> [#uses=1]
 	store %f4 %R, %f4* %S
 	ret void
@@ -102,19 +101,19 @@ define void @test_scalar_to_vector(float %F, %f4* %S) {
 }
 
 define float @test_extract_elt(%f8* %P) {
-	%p = load %f8* %P		; <%f8> [#uses=1]
+	%p = load %f8, %f8* %P		; <%f8> [#uses=1]
 	%R = extractelement %f8 %p, i32 3		; <float> [#uses=1]
 	ret float %R
 }
 
 define double @test_extract_elt2(%d8* %P) {
-	%p = load %d8* %P		; <%d8> [#uses=1]
+	%p = load %d8, %d8* %P		; <%d8> [#uses=1]
 	%R = extractelement %d8 %p, i32 3		; <double> [#uses=1]
 	ret double %R
 }
 
 define void @test_cast_1(%f4* %b, %i4* %a) {
-	%tmp = load %f4* %b		; <%f4> [#uses=1]
+	%tmp = load %f4, %f4* %b		; <%f4> [#uses=1]
 	%tmp2 = fadd %f4 %tmp, < float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00 >		; <%f4> [#uses=1]
 	%tmp3 = bitcast %f4 %tmp2 to %i4		; <%i4> [#uses=1]
 	%tmp4 = add %i4 %tmp3, < i32 1, i32 2, i32 3, i32 4 >		; <%i4> [#uses=1]
@@ -123,7 +122,7 @@ define void @test_cast_1(%f4* %b, %i4* %a) {
 }
 
 define void @test_cast_2(%f8* %a, <8 x i32>* %b) {
-	%T = load %f8* %a		; <%f8> [#uses=1]
+	%T = load %f8, %f8* %a		; <%f8> [#uses=1]
 	%T2 = bitcast %f8 %T to <8 x i32>		; <<8 x i32>> [#uses=1]
 	store <8 x i32> %T2, <8 x i32>* %b
 	ret void
@@ -136,7 +135,7 @@ define void @splat(%f4* %P, %f4* %Q, float %X) {
 	%tmp2 = insertelement %f4 %tmp, float %X, i32 1		; <%f4> [#uses=1]
 	%tmp4 = insertelement %f4 %tmp2, float %X, i32 2		; <%f4> [#uses=1]
 	%tmp6 = insertelement %f4 %tmp4, float %X, i32 3		; <%f4> [#uses=1]
-	%q = load %f4* %Q		; <%f4> [#uses=1]
+	%q = load %f4, %f4* %Q		; <%f4> [#uses=1]
 	%R = fadd %f4 %q, %tmp6		; <%f4> [#uses=1]
 	store %f4 %R, %f4* %P
 	ret void
@@ -147,13 +146,13 @@ define void @splat_i4(%i4* %P, %i4* %Q, i32 %X) {
 	%tmp2 = insertelement %i4 %tmp, i32 %X, i32 1		; <%i4> [#uses=1]
 	%tmp4 = insertelement %i4 %tmp2, i32 %X, i32 2		; <%i4> [#uses=1]
 	%tmp6 = insertelement %i4 %tmp4, i32 %X, i32 3		; <%i4> [#uses=1]
-	%q = load %i4* %Q		; <%i4> [#uses=1]
+	%q = load %i4, %i4* %Q		; <%i4> [#uses=1]
 	%R = add %i4 %q, %tmp6		; <%i4> [#uses=1]
 	store %i4 %R, %i4* %P
 	ret void
 }
 
 define <2 x i32*> @vector_gep(<2 x [3 x {i32, i32}]*> %a) {
-    %w = getelementptr <2 x [3 x {i32, i32}]*> %a, <2 x i32> <i32 1, i32 2>, <2 x i32> <i32 2, i32 3>, <2 x i32> <i32 1, i32 1>
+    %w = getelementptr [3 x {i32, i32}], <2 x [3 x {i32, i32}]*> %a, <2 x i32> <i32 1, i32 2>, <2 x i32> <i32 2, i32 3>, <2 x i32> <i32 1, i32 1>
       ret <2 x i32*> %w
 }
diff --git a/test/CodeGen/Hexagon/BranchPredict.ll b/test/CodeGen/Hexagon/BranchPredict.ll
index 5d564493e507..17d169974e5a 100644
--- a/test/CodeGen/Hexagon/BranchPredict.ll
+++ b/test/CodeGen/Hexagon/BranchPredict.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon -ifcvt-limit=0 < %s | FileCheck %s
 
 ; Check if the branch probabilities are reflected in the instructions:
 ; The basic block placement pass should place the more probable successor
@@ -53,7 +53,7 @@ return:                                           ; preds = %if.else, %if.then
 define i32 @foo_bar(i32 %a, i16 signext %b) nounwind {
 ; CHECK: if{{ *}}(!cmp.eq(r{{[0-9]*}}.new, #0)) jump:nt
 entry:
-  %0 = load i32* @j, align 4
+  %0 = load i32, i32* @j, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %if.else, label %if.then, !prof !0
 
diff --git a/test/CodeGen/Hexagon/absaddr-store.ll b/test/CodeGen/Hexagon/absaddr-store.ll
index 5c2554df8aeb..3be4b1cc2614 100644
--- a/test/CodeGen/Hexagon/absaddr-store.ll
+++ b/test/CodeGen/Hexagon/absaddr-store.ll
@@ -9,7 +9,7 @@
 define zeroext i8 @absStoreByte() nounwind {
 ; CHECK: memb(##b){{ *}}={{ *}}r{{[0-9]+}}
 entry:
-  %0 = load i8* @b, align 1
+  %0 = load i8, i8* @b, align 1
   %conv = zext i8 %0 to i32
   %mul = mul nsw i32 100, %conv
   %conv1 = trunc i32 %mul to i8
@@ -20,7 +20,7 @@ entry:
 define signext i16 @absStoreHalf() nounwind {
 ; CHECK: memh(##c){{ *}}={{ *}}r{{[0-9]+}}
 entry:
-  %0 = load i16* @c, align 2
+  %0 = load i16, i16* @c, align 2
   %conv = sext i16 %0 to i32
   %mul = mul nsw i32 100, %conv
   %conv1 = trunc i32 %mul to i16
@@ -31,7 +31,7 @@ entry:
 define i32 @absStoreWord() nounwind {
 ; CHECK: memw(##a){{ *}}={{ *}}r{{[0-9]+}}
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %mul = mul nsw i32 100, %0
   store i32 %mul, i32* @a, align 4
   ret i32 %mul
diff --git a/test/CodeGen/Hexagon/absimm.ll b/test/CodeGen/Hexagon/absimm.ll
index b8f5edc26470..07adb3fe49d5 100644
--- a/test/CodeGen/Hexagon/absimm.ll
+++ b/test/CodeGen/Hexagon/absimm.ll
@@ -12,7 +12,7 @@ entry:
 define i32* @f2(i32* nocapture %i) nounwind {
 entry:
 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(##786432)
-  %0 = load volatile i32* inttoptr (i32 786432 to i32*), align 262144
+  %0 = load volatile i32, i32* inttoptr (i32 786432 to i32*), align 262144
   %1 = inttoptr i32 %0 to i32*
   ret i32* %1
   }
diff --git a/test/CodeGen/Hexagon/adde.ll b/test/CodeGen/Hexagon/adde.ll
index 6d060c1b9e26..7b29e7ad8a0f 100644
--- a/test/CodeGen/Hexagon/adde.ll
+++ b/test/CodeGen/Hexagon/adde.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
 
-; CHECK: r{{[0-9]+:[0-9]+}} = #0
 ; CHECK: r{{[0-9]+:[0-9]+}} = #1
+; CHECK: r{{[0-9]+:[0-9]+}} = #0
 ; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
 ; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
 ; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
diff --git a/test/CodeGen/Hexagon/alu64.ll b/test/CodeGen/Hexagon/alu64.ll
new file mode 100644
index 000000000000..d0824a4ecadc
--- /dev/null
+++ b/test/CodeGen/Hexagon/alu64.ll
@@ -0,0 +1,599 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: @test00
+; CHECK: p0 = cmp.eq(r1:0, r3:2)
+define i32 @test00(i64 %Rs, i64 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.C2.cmpeqp(i64 %Rs, i64 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test01
+; CHECK: p0 = cmp.gt(r1:0, r3:2)
+define i32 @test01(i64 %Rs, i64 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.C2.cmpgtp(i64 %Rs, i64 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test02
+; CHECK: p0 = cmp.gtu(r1:0, r3:2)
+define i32 @test02(i64 %Rs, i64 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.C2.cmpgtup(i64 %Rs, i64 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test10
+; CHECK: r0 = cmp.eq(r0, r1)
+define i32 @test10(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.rcmpeq(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test11
+; CHECK: r0 = !cmp.eq(r0, r1)
+define i32 @test11(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.rcmpneq(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test12
+; CHECK: r0 = cmp.eq(r0, #23)
+define i32 @test12(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.rcmpeqi(i32 %Rs, i32 23)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test13
+; CHECK: r0 = !cmp.eq(r0, #47)
+define i32 @test13(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.rcmpneqi(i32 %Rs, i32 47)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test20
+; CHECK: p0 = cmpb.eq(r0, r1)
+define i32 @test20(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.cmpbeq(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test21
+; CHECK: p0 = cmpb.gt(r0, r1)
+define i32 @test21(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.cmpbgt(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test22
+; CHECK: p0 = cmpb.gtu(r0, r1)
+define i32 @test22(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.cmpbgtu(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test23
+; CHECK: p0 = cmpb.eq(r0, #56)
+define i32 @test23(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.cmpbeqi(i32 %Rs, i32 56)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test24
+; CHECK: p0 = cmpb.gt(r0, #29)
+define i32 @test24(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.cmpbgti(i32 %Rs, i32 29)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test25
+; CHECK: p0 = cmpb.gtu(r0, #111)
+define i32 @test25(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.cmpbgtui(i32 %Rs, i32 111)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test30
+; CHECK: p0 = cmph.eq(r0, r1)
+define i32 @test30(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.cmpheq(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test31
+; CHECK: p0 = cmph.gt(r0, r1)
+define i32 @test31(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.cmphgt(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test32
+; CHECK: p0 = cmph.gtu(r0, r1)
+define i32 @test32(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.cmphgtu(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test33
+; CHECK: p0 = cmph.eq(r0, #-123)
+define i32 @test33(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.cmpheqi(i32 %Rs, i32 -123)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test34
+; CHECK: p0 = cmph.gt(r0, #-3)
+define i32 @test34(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.cmphgti(i32 %Rs, i32 -3)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test35
+; CHECK: p0 = cmph.gtu(r0, #13)
+define i32 @test35(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.cmphgtui(i32 %Rs, i32 13)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test40
+; CHECK: r1:0 = vmux(p0, r3:2, r5:4)
+define i64 @test40(i32 %Pu, i64 %Rs, i64 %Rt) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.C2.vmux(i32 %Pu, i64 %Rs, i64 %Rt)
+  ret i64 %0
+}
+
+; CHECK-LABEL: @test41
+; CHECK: p0 = any8(vcmpb.eq(r1:0, r3:2))
+define i32 @test41(i64 %Rs, i64 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.vcmpbeq.any(i64 %Rs, i64 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test50
+; CHECK: r1:0 = add(r1:0, r3:2)
+define i64 @test50(i64 %Rs, i64 %Rt) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.A2.addp(i64 %Rs, i64 %Rt)
+  ret i64 %0
+}
+
+; CHECK-LABEL: @test51
+; CHECK: r1:0 = add(r1:0, r3:2):sat
+define i64 @test51(i64 %Rs, i64 %Rt) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.A2.addpsat(i64 %Rs, i64 %Rt)
+  ret i64 %0
+}
+
+; CHECK-LABEL: @test52
+; CHECK: r1:0 = sub(r1:0, r3:2)
+define i64 @test52(i64 %Rs, i64 %Rt) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.A2.subp(i64 %Rs, i64 %Rt)
+  ret i64 %0
+}
+
+; CHECK-LABEL: @test53
+; CHECK: r1:0 = add(r0, r3:2)
+define i64 @test53(i32 %Rs, i64 %Rt) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.A2.addsp(i32 %Rs, i64 %Rt)
+  ret i64 %0
+}
+
+; CHECK-LABEL: @test54
+; CHECK: r1:0 = and(r1:0, r3:2)
+define i64 @test54(i64 %Rs, i64 %Rt) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.A2.andp(i64 %Rs, i64 %Rt)
+  ret i64 %0
+}
+
+; CHECK-LABEL: @test55
+; CHECK: r1:0 = or(r1:0, r3:2)
+define i64 @test55(i64 %Rs, i64 %Rt) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.A2.orp(i64 %Rs, i64 %Rt)
+  ret i64 %0
+}
+
+; CHECK-LABEL: @test56
+; CHECK: r1:0 = xor(r1:0, r3:2)
+define i64 @test56(i64 %Rs, i64 %Rt) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.A2.xorp(i64 %Rs, i64 %Rt)
+  ret i64 %0
+}
+
+; CHECK-LABEL: @test57
+; CHECK: r1:0 = and(r1:0, ~r3:2)
+define i64 @test57(i64 %Rs, i64 %Rt) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.A4.andnp(i64 %Rs, i64 %Rt)
+  ret i64 %0
+}
+
+; CHECK-LABEL: @test58
+; CHECK: r1:0 = or(r1:0, ~r3:2)
+define i64 @test58(i64 %Rs, i64 %Rt) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.A4.ornp(i64 %Rs, i64 %Rt)
+  ret i64 %0
+}
+
+; CHECK-LABEL: @test60
+; CHECK: r0 = add(r0.l, r1.l)
+define i32 @test60(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.addh.l16.ll(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test61
+; CHECK: r0 = add(r0.l, r1.h)
+define i32 @test61(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.addh.l16.hl(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test62
+; CHECK: r0 = add(r0.l, r1.l):sat
+define i32 @test62(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test63
+; CHECK: r0 = add(r0.l, r1.h):sat
+define i32 @test63(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test64
+; CHECK: r0 = add(r0.l, r1.l):<<16
+define i32 @test64(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test65
+; CHECK: r0 = add(r0.l, r1.h):<<16
+define i32 @test65(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test66
+; CHECK: r0 = add(r0.h, r1.l):<<16
+define i32 @test66(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test67
+; CHECK: r0 = add(r0.h, r1.h):<<16
+define i32 @test67(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test68
+; CHECK: r0 = add(r0.l, r1.l):sat:<<16
+define i32 @test68(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test69
+; CHECK: r0 = add(r0.l, r1.h):sat:<<16
+define i32 @test69(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test6A
+; CHECK: r0 = add(r0.h, r1.l):sat:<<16
+define i32 @test6A(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test6B
+; CHECK: r0 = add(r0.h, r1.h):sat:<<16
+define i32 @test6B(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test70
+; CHECK: r0 = sub(r0.l, r1.l)
+define i32 @test70(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.subh.l16.ll(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test71
+; CHECK: r0 = sub(r0.l, r1.h)
+define i32 @test71(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.subh.l16.hl(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test72
+; CHECK: r0 = sub(r0.l, r1.l):sat
+define i32 @test72(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test73
+; CHECK: r0 = sub(r0.l, r1.h):sat
+define i32 @test73(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test74
+; CHECK: r0 = sub(r0.l, r1.l):<<16
+define i32 @test74(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.subh.h16.ll(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test75
+; CHECK: r0 = sub(r0.l, r1.h):<<16
+define i32 @test75(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.subh.h16.lh(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test76
+; CHECK: r0 = sub(r0.h, r1.l):<<16
+define i32 @test76(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.subh.h16.hl(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test77
+; CHECK: r0 = sub(r0.h, r1.h):<<16
+define i32 @test77(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.subh.h16.hh(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test78
+; CHECK: r0 = sub(r0.l, r1.l):sat:<<16
+define i32 @test78(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test79
+; CHECK: r0 = sub(r0.l, r1.h):sat:<<16
+define i32 @test79(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test7A
+; CHECK: r0 = sub(r0.h, r1.l):sat:<<16
+define i32 @test7A(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test7B
+; CHECK: r0 = sub(r0.h, r1.h):sat:<<16
+define i32 @test7B(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test90
+; CHECK: r0 = and(#1, asl(r0, #2))
+define i32 @test90(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.S4.andi.asl.ri(i32 1, i32 %Rs, i32 2)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test91
+; CHECK: r0 = or(#1, asl(r0, #2))
+define i32 @test91(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.S4.ori.asl.ri(i32 1, i32 %Rs, i32 2)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test92
+; CHECK: r0 = add(#1, asl(r0, #2))
+define i32 @test92(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.S4.addi.asl.ri(i32 1, i32 %Rs, i32 2)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test93
+; CHECK: r0 = sub(#1, asl(r0, #2))
+define i32 @test93(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.S4.subi.asl.ri(i32 1, i32 %Rs, i32 2)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test94
+; CHECK: r0 = and(#1, lsr(r0, #2))
+define i32 @test94(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.S4.andi.lsr.ri(i32 1, i32 %Rs, i32 2)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test95
+; CHECK: r0 = or(#1, lsr(r0, #2))
+define i32 @test95(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.S4.ori.lsr.ri(i32 1, i32 %Rs, i32 2)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test96
+; CHECK: r0 = add(#1, lsr(r0, #2))
+define i32 @test96(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.S4.addi.lsr.ri(i32 1, i32 %Rs, i32 2)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test97
+; CHECK: r0 = sub(#1, lsr(r0, #2))
+define i32 @test97(i32 %Rs) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.S4.subi.lsr.ri(i32 1, i32 %Rs, i32 2)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test100
+; CHECK: r1:0 = bitsplit(r0, r1)
+define i64 @test100(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.A4.bitsplit(i32 %Rs, i32 %Rt)
+  ret i64 %0
+}
+
+; CHECK-LABEL: @test101
+; CHECK: r0 = modwrap(r0, r1)
+define i32 @test101(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.A4.modwrapu(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test102
+; CHECK: r0 = parity(r1:0, r3:2)
+define i32 @test102(i64 %Rs, i64 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.S2.parityp(i64 %Rs, i64 %Rt)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @test103
+; CHECK: r0 = parity(r0, r1)
+define i32 @test103(i32 %Rs, i32 %Rt) #0 {
+entry:
+  %0 = tail call i32 @llvm.hexagon.S4.parity(i32 %Rs, i32 %Rt)
+  ret i32 %0
+}
+
+declare i32 @llvm.hexagon.C2.cmpeqp(i64, i64) #1
+declare i32 @llvm.hexagon.C2.cmpgtp(i64, i64) #1
+declare i32 @llvm.hexagon.C2.cmpgtup(i64, i64) #1
+declare i32 @llvm.hexagon.A4.rcmpeq(i32, i32) #1
+declare i32 @llvm.hexagon.A4.rcmpneq(i32, i32) #1
+declare i32 @llvm.hexagon.A4.rcmpeqi(i32, i32) #1
+declare i32 @llvm.hexagon.A4.rcmpneqi(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpbeq(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpbgt(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpbgtu(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpbeqi(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpbgti(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpbgtui(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpheq(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmphgt(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmphgtu(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpheqi(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmphgti(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmphgtui(i32, i32) #1
+declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64) #1
+declare i32 @llvm.hexagon.A4.vcmpbeq.any(i64, i64) #1
+declare i64 @llvm.hexagon.A2.addp(i64, i64) #1
+declare i64 @llvm.hexagon.A2.addpsat(i64, i64) #1
+declare i64 @llvm.hexagon.A2.subp(i64, i64) #1
+declare i64 @llvm.hexagon.A2.addsp(i32, i64) #1
+declare i64 @llvm.hexagon.A2.andp(i64, i64) #1
+declare i64 @llvm.hexagon.A2.orp(i64, i64) #1
+declare i64 @llvm.hexagon.A2.xorp(i64, i64) #1
+declare i64 @llvm.hexagon.A4.ornp(i64, i64) #1
+declare i64 @llvm.hexagon.A4.andnp(i64, i64) #1
+declare i32 @llvm.hexagon.A2.addh.l16.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.l16.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.lh(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.hh(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.l16.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.l16.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.lh(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.hh(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32, i32) #1
+declare i64 @llvm.hexagon.A4.bitsplit(i32, i32) #1
+declare i32 @llvm.hexagon.A4.modwrapu(i32, i32) #1
+declare i32 @llvm.hexagon.S2.parityp(i64, i64) #1
+declare i32 @llvm.hexagon.S4.parity(i32, i32) #1
+declare i32 @llvm.hexagon.S4.andi.asl.ri(i32, i32, i32) #1
+declare i32 @llvm.hexagon.S4.ori.asl.ri(i32, i32, i32) #1
+declare i32 @llvm.hexagon.S4.addi.asl.ri(i32, i32, i32) #1
+declare i32 @llvm.hexagon.S4.subi.asl.ri(i32, i32, i32) #1
+declare i32 @llvm.hexagon.S4.andi.lsr.ri(i32, i32, i32) #1
+declare i32 @llvm.hexagon.S4.ori.lsr.ri(i32, i32, i32) #1
+declare i32 @llvm.hexagon.S4.addi.lsr.ri(i32, i32, i32) #1
+declare i32 @llvm.hexagon.S4.subi.lsr.ri(i32, i32, i32) #1
+
+attributes #0 = { nounwind readnone "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
diff --git a/test/CodeGen/Hexagon/always-ext.ll b/test/CodeGen/Hexagon/always-ext.ll
index 9c8d708ba877..8b4b2f5bf4f2 100644
--- a/test/CodeGen/Hexagon/always-ext.ll
+++ b/test/CodeGen/Hexagon/always-ext.ll
@@ -1,3 +1,4 @@
+; XFAIL:
 ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
 
 ; Check that we don't generate an invalid packet with too many instructions
@@ -7,7 +8,7 @@
 ; CHECK: {
 ; CHECK-NOT: call abort
 ; CHECK: memw(##0)
-; CHECK: memw(r{{[0-9+]}}<<#2+##4)
+; CHECK: memw(r{{[0-9+]}}<<#2 + ##4)
 ; CHECK: }
 
 %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111 = type { i8*, void (%struct.CuTest.1.28.31.37.40.43.52.55.67.85.111*)*, i32, i32, i8*, [23 x i32]* }
@@ -23,8 +24,8 @@ entry:
   br i1 undef, label %for.body.us, label %for.end
 
 for.body.us:                                      ; preds = %entry
-  %0 = load %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111** null, align 4
-  %1 = load i32* undef, align 4
+  %0 = load %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111*, %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111** null, align 4
+  %1 = load i32, i32* undef, align 4
   %cmp.i.us = icmp slt i32 %1, 1024
   br i1 %cmp.i.us, label %CuSuiteAdd.exit.us, label %cond.false6.i.us
 
@@ -33,7 +34,7 @@ cond.false6.i.us:                                 ; preds = %for.body.us
   unreachable
 
 CuSuiteAdd.exit.us:                               ; preds = %for.body.us
-  %arrayidx.i.us = getelementptr inbounds %struct.CuSuite.2.29.32.38.41.44.53.56.68.86.112* null, i32 0, i32 1, i32 %1
+  %arrayidx.i.us = getelementptr inbounds %struct.CuSuite.2.29.32.38.41.44.53.56.68.86.112, %struct.CuSuite.2.29.32.38.41.44.53.56.68.86.112* null, i32 0, i32 1, i32 %1
   store %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111* %0, %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111** %arrayidx.i.us, align 4
   call void @llvm.trap()
   unreachable
diff --git a/test/CodeGen/Hexagon/block-addr.ll b/test/CodeGen/Hexagon/block-addr.ll
index dc0d6e60fd28..eda167a67f28 100644
--- a/test/CodeGen/Hexagon/block-addr.ll
+++ b/test/CodeGen/Hexagon/block-addr.ll
@@ -1,7 +1,8 @@
 ; RUN: llc -march=hexagon < %s | FileCheck %s
 
-; CHECK: r{{[0-9]+}} = CONST32(#.LJTI{{[0-9]+_[0-9]+}})
-; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}} + r{{[0-9]+<<#[0-9]+}})
+; Allow combine(..##JTI..):
+; CHECK: r{{[0-9]+}}{{.*}} = {{.*}}#.LJTI
+; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+<<#[0-9]+}})
 ; CHECK: jumpr r{{[0-9]+}}
 
 define void @main() #0 {
@@ -10,7 +11,7 @@ entry:
   br label %while.body
 
 while.body:
-  %ret.0.load17 = load volatile i32* %ret, align 4
+  %ret.0.load17 = load volatile i32, i32* %ret, align 4
   switch i32 %ret.0.load17, label %label6 [
     i32 0, label %label0
     i32 1, label %label1
@@ -21,37 +22,37 @@ while.body:
   ]
 
 label0:
-  %ret.0.load18 = load volatile i32* %ret, align 4
+  %ret.0.load18 = load volatile i32, i32* %ret, align 4
   %inc = add nsw i32 %ret.0.load18, 1
   store volatile i32 %inc, i32* %ret, align 4
   br label %while.body
 
 label1:
-  %ret.0.load19 = load volatile i32* %ret, align 4
+  %ret.0.load19 = load volatile i32, i32* %ret, align 4
   %inc2 = add nsw i32 %ret.0.load19, 1
   store volatile i32 %inc2, i32* %ret, align 4
   br label %while.body
 
 label2:
-  %ret.0.load20 = load volatile i32* %ret, align 4
+  %ret.0.load20 = load volatile i32, i32* %ret, align 4
   %inc4 = add nsw i32 %ret.0.load20, 1
   store volatile i32 %inc4, i32* %ret, align 4
   br label %while.body
 
 label3:
-  %ret.0.load21 = load volatile i32* %ret, align 4
+  %ret.0.load21 = load volatile i32, i32* %ret, align 4
   %inc6 = add nsw i32 %ret.0.load21, 1
   store volatile i32 %inc6, i32* %ret, align 4
   br label %while.body
 
 label4:
-  %ret.0.load22 = load volatile i32* %ret, align 4
+  %ret.0.load22 = load volatile i32, i32* %ret, align 4
   %inc8 = add nsw i32 %ret.0.load22, 1
   store volatile i32 %inc8, i32* %ret, align 4
   br label %while.body
 
 label5:
-  %ret.0.load23 = load volatile i32* %ret, align 4
+  %ret.0.load23 = load volatile i32, i32* %ret, align 4
   %inc10 = add nsw i32 %ret.0.load23, 1
   store volatile i32 %inc10, i32* %ret, align 4
   br label %while.body
diff --git a/test/CodeGen/Hexagon/brev_ld.ll b/test/CodeGen/Hexagon/brev_ld.ll
new file mode 100644
index 000000000000..12edb4c2b8f7
--- /dev/null
+++ b/test/CodeGen/Hexagon/brev_ld.ll
@@ -0,0 +1,140 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s
+; Testing bitreverse load intrinsics:
+;   Q6_bitrev_load_update_D(inputLR, pDelay, nConvLength);
+;   Q6_bitrev_load_update_W(inputLR, pDelay, nConvLength);
+;   Q6_bitrev_load_update_H(inputLR, pDelay, nConvLength);
+;   Q6_bitrev_load_update_UH(inputLR, pDelay, nConvLength);
+;   Q6_bitrev_load_update_UB(inputLR, pDelay, nConvLength);
+;   Q6_bitrev_load_update_B(inputLR, pDelay, nConvLength);
+; producing these instructions:
+;   r3:2 = memd(r0++m0:brev)
+;   r1 = memw(r0++m0:brev)
+;   r1 = memh(r0++m0:brev)
+;   r1 = memuh(r0++m0:brev)
+;   r1 = memub(r0++m0:brev)
+;   r1 = memb(r0++m0:brev)
+
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+define i64 @foo(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %inputLR = alloca i64, align 8
+  %conv = zext i16 %filtMemLen to i32
+  %shr1 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %1 = bitcast i64* %inputLR to i8*
+  %sub = sub i32 13, %shr1
+  %shl = shl i32 1, %sub
+; CHECK: memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+  %2 = call i8* @llvm.hexagon.brev.ldd(i8* %0, i8* %1, i32 %shl)
+  %3 = bitcast i8* %2 to i64*
+  %4 = load i64, i64* %3, align 8, !tbaa !0
+  ret i64 %4
+}
+
+declare i8* @llvm.hexagon.brev.ldd(i8*, i8*, i32) nounwind
+
+define i32 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %inputLR = alloca i32, align 4
+  %conv = zext i16 %filtMemLen to i32
+  %shr1 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %1 = bitcast i32* %inputLR to i8*
+  %sub = sub i32 14, %shr1
+  %shl = shl i32 1, %sub
+; CHECK: memw(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+  %2 = call i8* @llvm.hexagon.brev.ldw(i8* %0, i8* %1, i32 %shl)
+  %3 = bitcast i8* %2 to i32*
+  %4 = load i32, i32* %3, align 4, !tbaa !2
+  ret i32 %4
+}
+
+declare i8* @llvm.hexagon.brev.ldw(i8*, i8*, i32) nounwind
+
+define signext i16 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %inputLR = alloca i16, align 2
+  %conv = zext i16 %filtMemLen to i32
+  %shr1 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %1 = bitcast i16* %inputLR to i8*
+  %sub = sub i32 15, %shr1
+  %shl = shl i32 1, %sub
+; CHECK: memh(r{{[0-9]*}} ++ m0:brev)
+  %2 = call i8* @llvm.hexagon.brev.ldh(i8* %0, i8* %1, i32 %shl)
+  %3 = bitcast i8* %2 to i16*
+  %4 = load i16, i16* %3, align 2, !tbaa !3
+  ret i16 %4
+}
+
+declare i8* @llvm.hexagon.brev.ldh(i8*, i8*, i32) nounwind
+
+define zeroext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %inputLR = alloca i16, align 2
+  %conv = zext i16 %filtMemLen to i32
+  %shr1 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %1 = bitcast i16* %inputLR to i8*
+  %sub = sub i32 15, %shr1
+  %shl = shl i32 1, %sub
+; CHECK: memuh(r{{[0-9]*}} ++ m0:brev)
+  %2 = call i8* @llvm.hexagon.brev.lduh(i8* %0, i8* %1, i32 %shl)
+  %3 = bitcast i8* %2 to i16*
+  %4 = load i16, i16* %3, align 2, !tbaa !3
+  ret i16 %4
+}
+
+declare i8* @llvm.hexagon.brev.lduh(i8*, i8*, i32) nounwind
+
+define zeroext i8 @foo4(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %inputLR = alloca i8, align 1
+  %conv = zext i16 %filtMemLen to i32
+  %shr1 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %sub = sub nsw i32 16, %shr1
+  %shl = shl i32 1, %sub
+; CHECK: memub(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+  %1 = call i8* @llvm.hexagon.brev.ldub(i8* %0, i8* %inputLR, i32 %shl)
+  %2 = load i8, i8* %1, align 1, !tbaa !0
+  ret i8 %2
+}
+
+declare i8* @llvm.hexagon.brev.ldub(i8*, i8*, i32) nounwind
+
+define zeroext i8 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %inputLR = alloca i8, align 1
+  %conv = zext i16 %filtMemLen to i32
+  %shr1 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %sub = sub nsw i32 16, %shr1
+  %shl = shl i32 1, %sub
+; CHECK: memb(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+  %1 = call i8* @llvm.hexagon.brev.ldb(i8* %0, i8* %inputLR, i32 %shl)
+  %2 = load i8, i8* %1, align 1, !tbaa !0
+  ret i8 %2
+}
+
+declare i8* @llvm.hexagon.brev.ldb(i8*, i8*, i32) nounwind
+
+!0 = !{!"omnipotent char", !1}
+!1 = !{!"Simple C/C++ TBAA"}
+!2 = !{!"int", !0}
+!3 = !{!"short", !0}
diff --git a/test/CodeGen/Hexagon/brev_st.ll b/test/CodeGen/Hexagon/brev_st.ll
new file mode 100644
index 000000000000..b80579185317
--- /dev/null
+++ b/test/CodeGen/Hexagon/brev_st.ll
@@ -0,0 +1,112 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s
+; Test these 5 bitreverse store intrinsics:
+;   Q6_bitrev_store_update_D(inputLR, pDelay, nConvLength);
+;   Q6_bitrev_store_update_W(inputLR, pDelay, nConvLength);
+;   Q6_bitrev_store_update_HL(inputLR, pDelay, nConvLength);
+;   Q6_bitrev_store_update_HH(inputLR, pDelay, nConvLength);
+;   Q6_bitrev_store_update_B(inputLR, pDelay, nConvLength);
+; producing these instructions:
+;   memd(r0++m0:brev) = r1:0
+;   memw(r0++m0:brev) = r0
+;   memh(r0++m0:brev) = r3
+;   memh(r0++m0:brev) = r3.h
+;   memb(r0++m0:brev) = r3
+
+; ModuleID = 'brev_st.i'
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+define i64 @foo(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %conv = zext i16 %filtMemLen to i32
+  %shr2 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %sub = sub i32 13, %shr2
+  %shl = shl i32 1, %sub
+; CHECK: memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+  %1 = tail call i8* @llvm.hexagon.brev.std(i8* %0, i64 undef, i32 %shl)
+  %2 = bitcast i8* %1 to i64*
+  %3 = load i64, i64* %2, align 8, !tbaa !0
+  ret i64 %3
+}
+
+declare i8* @llvm.hexagon.brev.std(i8*, i64, i32) nounwind
+
+define i32 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %conv = zext i16 %filtMemLen to i32
+  %shr1 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %sub = sub i32 14, %shr1
+  %shl = shl i32 1, %sub
+; CHECK: memw(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+  %1 = tail call i8* @llvm.hexagon.brev.stw(i8* %0, i32 undef, i32 %shl)
+  %2 = bitcast i8* %1 to i32*
+  %3 = load i32, i32* %2, align 4, !tbaa !2
+  ret i32 %3
+}
+
+declare i8* @llvm.hexagon.brev.stw(i8*, i32, i32) nounwind
+
+define signext i16 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %conv = zext i16 %filtMemLen to i32
+  %shr2 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %sub = sub i32 15, %shr2
+  %shl = shl i32 1, %sub
+; CHECK: memh(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+  %1 = tail call i8* @llvm.hexagon.brev.sth(i8* %0, i32 0, i32 %shl)
+  %2 = bitcast i8* %1 to i16*
+  %3 = load i16, i16* %2, align 2, !tbaa !3
+  ret i16 %3
+}
+
+declare i8* @llvm.hexagon.brev.sth(i8*, i32, i32) nounwind
+
+define signext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %conv = zext i16 %filtMemLen to i32
+  %shr2 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %sub = sub i32 15, %shr2
+  %shl = shl i32 1, %sub
+; CHECK: memh(r{{[0-9]*}} ++ m{{[0-1]}}:brev){{ *}}={{ *}}r{{[0-9]*}}.h
+  %1 = tail call i8* @llvm.hexagon.brev.sthhi(i8* %0, i32 0, i32 %shl)
+  %2 = bitcast i8* %1 to i16*
+  %3 = load i16, i16* %2, align 2, !tbaa !3
+  ret i16 %3
+}
+
+declare i8* @llvm.hexagon.brev.sthhi(i8*, i32, i32) nounwind
+
+define zeroext i8 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %conv = zext i16 %filtMemLen to i32
+  %shr2 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %sub = sub nsw i32 16, %shr2
+  ; CHECK: memb(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+  %shl = shl i32 1, %sub
+  %1 = tail call i8* @llvm.hexagon.brev.stb(i8* %0, i32 0, i32 %shl)
+  %2 = load i8, i8* %1, align 1, !tbaa !0
+  ret i8 %2
+}
+
+declare i8* @llvm.hexagon.brev.stb(i8*, i32, i32) nounwind
+
+!0 = !{!"omnipotent char", !1}
+!1 = !{!"Simple C/C++ TBAA"}
+!2 = !{!"int", !0}
+!3 = !{!"short", !0}
diff --git a/test/CodeGen/Hexagon/calling-conv-2.ll b/test/CodeGen/Hexagon/calling-conv-2.ll
new file mode 100644
index 000000000000..3c68c88bd711
--- /dev/null
+++ b/test/CodeGen/Hexagon/calling-conv-2.ll
@@ -0,0 +1,13 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 <%s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-ONE
+
+%struct.test_struct = type { i32, i8, i64 }
+
+; CHECK-ONE:    r1 = #45
+define void @foo(%struct.test_struct* noalias nocapture sret %agg.result, i32 %a) #0 {
+entry:
+  call void @bar(%struct.test_struct* sret %agg.result, i32 45) #2
+  ret void
+}
+
+declare void @bar(%struct.test_struct* sret, i32) #1
diff --git a/test/CodeGen/Hexagon/calling-conv.ll b/test/CodeGen/Hexagon/calling-conv.ll
new file mode 100644
index 000000000000..7133c1ae7aad
--- /dev/null
+++ b/test/CodeGen/Hexagon/calling-conv.ll
@@ -0,0 +1,73 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 <%s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-ONE
+; RUN: llc -march=hexagon -mcpu=hexagonv5 <%s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-TWO
+; RUN: llc -march=hexagon -mcpu=hexagonv5 <%s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-THREE
+
+%struct.test_struct = type { i32, i8, i64 }
+%struct.test_struct_long = type { i8, i64 }
+
+@mystruct = external global %struct.test_struct*, align 4
+
+; CHECK-ONE:    memw(r29+#48) = r2
+; CHECK-TWO:    memw(r29+#52) = r2
+; CHECK-THREE:  memw(r29+#56) = r2
+; Function Attrs: nounwind
+define void @foo(%struct.test_struct* noalias sret %agg.result, i32 %a, i8 zeroext %c, %struct.test_struct* byval %s, %struct.test_struct_long* byval %t) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  %c.addr = alloca i8, align 1
+  %z = alloca i32, align 4
+  %ret = alloca %struct.test_struct, align 8
+  store i32 %a, i32* %a.addr, align 4
+  store i8 %c, i8* %c.addr, align 1
+  %0 = bitcast i32* %z to i8*
+  call void @llvm.lifetime.start(i64 4, i8* %0) #1
+  store i32 45, i32* %z, align 4
+  %1 = bitcast %struct.test_struct* %ret to i8*
+  call void @llvm.lifetime.start(i64 16, i8* %1) #1
+  %2 = load i32, i32* %z, align 4
+  %3 = load %struct.test_struct*, %struct.test_struct** @mystruct, align 4
+  %4 = load %struct.test_struct*, %struct.test_struct** @mystruct, align 4
+  %5 = load i8, i8* %c.addr, align 1
+  %6 = load i32, i32* %a.addr, align 4
+  %conv = sext i32 %6 to i64
+  %add = add nsw i64 %conv, 1
+  %7 = load i32, i32* %a.addr, align 4
+  %add1 = add nsw i32 %7, 2
+  %8 = load i32, i32* %a.addr, align 4
+  %conv2 = sext i32 %8 to i64
+  %add3 = add nsw i64 %conv2, 3
+  %9 = load i8, i8* %c.addr, align 1
+  %10 = load i8, i8* %c.addr, align 1
+  %11 = load i8, i8* %c.addr, align 1
+  %12 = load i32, i32* %z, align 4
+  call void @bar(%struct.test_struct* sret %ret, i32 %2, %struct.test_struct* byval %3, %struct.test_struct* byval %4, i8 zeroext %5, i64 %add, i32 %add1, i64 %add3, i8 zeroext %9, i8 zeroext %10, i8 zeroext %11, i32 %12)
+  %x = getelementptr inbounds %struct.test_struct, %struct.test_struct* %ret, i32 0, i32 0
+  store i32 20, i32* %x, align 4
+  %13 = bitcast %struct.test_struct* %agg.result to i8*
+  %14 = bitcast %struct.test_struct* %ret to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %13, i8* %14, i32 16, i32 8, i1 false)
+  %15 = bitcast %struct.test_struct* %ret to i8*
+  call void @llvm.lifetime.end(i64 16, i8* %15) #1
+  %16 = bitcast i32* %z to i8*
+  call void @llvm.lifetime.end(i64 4, i8* %16) #1
+  ret void
+}
+
+; Function Attrs: nounwind
+declare void @llvm.lifetime.start(i64, i8* nocapture) #1
+
+declare void @bar(%struct.test_struct* sret, i32, %struct.test_struct* byval, %struct.test_struct* byval, i8 zeroext, i64, i32, i64, i8 zeroext, i8 zeroext, i8 zeroext, i32) #2
+
+; Function Attrs: nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #1
+
+; Function Attrs: nounwind
+declare void @llvm.lifetime.end(i64, i8* nocapture) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv4" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind }
+attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv4" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
diff --git a/test/CodeGen/Hexagon/cext-check.ll b/test/CodeGen/Hexagon/cext-check.ll
index b7181d803f71..19b91c5245b2 100644
--- a/test/CodeGen/Hexagon/cext-check.ll
+++ b/test/CodeGen/Hexagon/cext-check.ll
@@ -7,19 +7,19 @@ define i32 @cext_test1(i32* %a) nounwind {
 ; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}##4092)
 ; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300)
 entry:
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %tobool = icmp ne i32 %0, 0
   br i1 %tobool, label %if.then, label %if.end
 
 if.then:
-  %arrayidx1 = getelementptr inbounds i32* %a, i32 2000
-  %1 = load i32* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %a, i32 2000
+  %1 = load i32, i32* %arrayidx1, align 4
   %add = add nsw i32 %1, 300000
   br label %return
 
 if.end:
-  %arrayidx2 = getelementptr inbounds i32* %a, i32 1023
-  %2 = load i32* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 1023
+  %2 = load i32, i32* %arrayidx2, align 4
   %add3 = add nsw i32 %2, 300
   br label %return
 
@@ -38,15 +38,15 @@ entry:
   br i1 %tobool, label %if.then, label %if.end
 
 if.then:
-  %arrayidx = getelementptr inbounds i8* %a, i32 1023
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %a, i32 1023
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 300000
   br label %return
 
 if.end:
-  %arrayidx1 = getelementptr inbounds i8* %a, i32 1024
-  %1 = load i8* %arrayidx1, align 1
+  %arrayidx1 = getelementptr inbounds i8, i8* %a, i32 1024
+  %1 = load i8, i8* %arrayidx1, align 1
   %conv2 = zext i8 %1 to i32
   %add3 = add nsw i32 %conv2, 6000
   br label %return
diff --git a/test/CodeGen/Hexagon/cext-valid-packet2.ll b/test/CodeGen/Hexagon/cext-valid-packet2.ll
index 2788a6b1c865..2eba74329960 100644
--- a/test/CodeGen/Hexagon/cext-valid-packet2.ll
+++ b/test/CodeGen/Hexagon/cext-valid-packet2.ll
@@ -10,31 +10,31 @@
 define i32 @test(i32* nocapture %a, i32* nocapture %b, i32 %c) nounwind {
 entry:
   %add = add nsw i32 %c, 200002
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %add1 = add nsw i32 %0, 200000
-  %arrayidx2 = getelementptr inbounds i32* %a, i32 3000
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 3000
   store i32 %add1, i32* %arrayidx2, align 4
-  %1 = load i32* %b, align 4
+  %1 = load i32, i32* %b, align 4
   %add4 = add nsw i32 %1, 200001
-  %arrayidx5 = getelementptr inbounds i32* %a, i32 1
+  %arrayidx5 = getelementptr inbounds i32, i32* %a, i32 1
   store i32 %add4, i32* %arrayidx5, align 4
-  %arrayidx7 = getelementptr inbounds i32* %b, i32 1
-  %2 = load i32* %arrayidx7, align 4
+  %arrayidx7 = getelementptr inbounds i32, i32* %b, i32 1
+  %2 = load i32, i32* %arrayidx7, align 4
   %cmp = icmp sgt i32 %add4, %2
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  %arrayidx8 = getelementptr inbounds i32* %a, i32 2
-  %3 = load i32* %arrayidx8, align 4
-  %arrayidx9 = getelementptr inbounds i32* %b, i32 2000
-  %4 = load i32* %arrayidx9, align 4
+  %arrayidx8 = getelementptr inbounds i32, i32* %a, i32 2
+  %3 = load i32, i32* %arrayidx8, align 4
+  %arrayidx9 = getelementptr inbounds i32, i32* %b, i32 2000
+  %4 = load i32, i32* %arrayidx9, align 4
   %sub = sub nsw i32 %3, %4
-  %arrayidx10 = getelementptr inbounds i32* %a, i32 4000
+  %arrayidx10 = getelementptr inbounds i32, i32* %a, i32 4000
   store i32 %sub, i32* %arrayidx10, align 4
   br label %if.end
 
 if.else:                                          ; preds = %entry
-  %arrayidx11 = getelementptr inbounds i32* %b, i32 3200
+  %arrayidx11 = getelementptr inbounds i32, i32* %b, i32 3200
   store i32 %add, i32* %arrayidx11, align 4
   br label %if.end
 
diff --git a/test/CodeGen/Hexagon/circ_ld.ll b/test/CodeGen/Hexagon/circ_ld.ll
new file mode 100644
index 000000000000..6d372403ca7a
--- /dev/null
+++ b/test/CodeGen/Hexagon/circ_ld.ll
@@ -0,0 +1,135 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; Testing for these 6 variants of circular load:
+;   Q6_circ_load_update_B(inputLR, pDelay, -1, nConvLength, 4);
+;   Q6_circ_load_update_D(inputLR, pDelay, -1, nConvLength, 4);
+;   Q6_circ_load_update_H(inputLR, pDelay, -1, nConvLength, 4);
+;   Q6_circ_load_update_UB(inputLR, pDelay, -1, nConvLength, 4);
+;   Q6_circ_load_update_UH(inputLR, pDelay, -1, nConvLength, 4);
+;   Q6_circ_load_update_W(inputLR, pDelay, -1, nConvLength, 4);
+; producing these:
+;   r0 = memb(r1++#-1:circ(m0))
+;   r3:2 = memd(r1++#-8:circ(m0))
+;   r0 = memh(r1++#-2:circ(m0))
+;   r0 = memub(r1++#-1:circ(m0))
+;   r0 = memuh(r1++#-2:circ(m0))
+;   r0 = memw(r1++#-4:circ(m0))
+
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+define zeroext i8 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %inputLR = alloca i8, align 1
+  %conv = zext i16 %filtMemLen to i32
+  %shr1 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %or = or i32 %shr1, 33554432
+; CHECK: memb(r{{[0-9]*.}}++{{.}}#-1:circ(m{{[0-1]}}))
+  %1 = call i8* @llvm.hexagon.circ.ldb(i8* %0, i8* %inputLR, i32 %or, i32 -1)
+  %2 = load i8, i8* %1, align 1, !tbaa !0
+  ret i8 %2
+}
+
+declare i8* @llvm.hexagon.circ.ldb(i8*, i8*, i32, i32) nounwind
+
+define i64 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %inputLR = alloca i64, align 8
+  %conv = zext i16 %filtMemLen to i32
+  %shr1 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %1 = bitcast i64* %inputLR to i8*
+  %shl = shl nuw nsw i32 %shr1, 3
+  %or = or i32 %shl, 83886080
+; CHECK: memd(r{{[0-9]*.}}++{{.}}#-8:circ(m{{[0-1]}}))
+  %2 = call i8* @llvm.hexagon.circ.ldd(i8* %0, i8* %1, i32 %or, i32 -8)
+  %3 = bitcast i8* %2 to i64*
+  %4 = load i64, i64* %3, align 8, !tbaa !0
+  ret i64 %4
+}
+
+declare i8* @llvm.hexagon.circ.ldd(i8*, i8*, i32, i32) nounwind
+
+define signext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %inputLR = alloca i16, align 2
+  %conv = zext i16 %filtMemLen to i32
+  %shr1 = and i32 %conv, 65534
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %1 = bitcast i16* %inputLR to i8*
+  %or = or i32 %shr1, 50331648
+; CHECK: memh(r{{[0-9]*.}}++{{.}}#-2:circ(m{{[0-1]}}))
+  %2 = call i8* @llvm.hexagon.circ.ldh(i8* %0, i8* %1, i32 %or, i32 -2)
+  %3 = bitcast i8* %2 to i16*
+  %4 = load i16, i16* %3, align 2, !tbaa !2
+  ret i16 %4
+}
+
+declare i8* @llvm.hexagon.circ.ldh(i8*, i8*, i32, i32) nounwind
+
+define zeroext i8 @foo4(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %inputLR = alloca i8, align 1
+  %conv = zext i16 %filtMemLen to i32
+  %shr1 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %or = or i32 %shr1, 33554432
+; CHECK: memub(r{{[0-9]*.}}++{{.}}#-1:circ(m{{[0-1]}}))
+  %1 = call i8* @llvm.hexagon.circ.ldub(i8* %0, i8* %inputLR, i32 %or, i32 -1)
+  %2 = load i8, i8* %1, align 1, !tbaa !0
+  ret i8 %2
+}
+
+declare i8* @llvm.hexagon.circ.ldub(i8*, i8*, i32, i32) nounwind
+
+define zeroext i16 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %inputLR = alloca i16, align 2
+  %conv = zext i16 %filtMemLen to i32
+  %shr1 = and i32 %conv, 65534
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %1 = bitcast i16* %inputLR to i8*
+  %or = or i32 %shr1, 50331648
+; CHECK: memuh(r{{[0-9]*.}}++{{.}}#-2:circ(m{{[0-1]}}))
+  %2 = call i8* @llvm.hexagon.circ.lduh(i8* %0, i8* %1, i32 %or, i32 -2)
+  %3 = bitcast i8* %2 to i16*
+  %4 = load i16, i16* %3, align 2, !tbaa !2
+  ret i16 %4
+}
+
+declare i8* @llvm.hexagon.circ.lduh(i8*, i8*, i32, i32) nounwind
+
+define i32 @foo6(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %inputLR = alloca i32, align 4
+  %conv = zext i16 %filtMemLen to i32
+  %shr1 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %1 = bitcast i32* %inputLR to i8*
+  %shl = shl nuw nsw i32 %shr1, 2
+  %or = or i32 %shl, 67108864
+; CHECK: memw(r{{[0-9]*.}}++{{.}}#-4:circ(m{{[0-1]}}))
+  %2 = call i8* @llvm.hexagon.circ.ldw(i8* %0, i8* %1, i32 %or, i32 -4)
+  %3 = bitcast i8* %2 to i32*
+  %4 = load i32, i32* %3, align 4, !tbaa !3
+  ret i32 %4
+}
+
+declare i8* @llvm.hexagon.circ.ldw(i8*, i8*, i32, i32) nounwind
+
+!0 = !{!"omnipotent char", !1}
+!1 = !{!"Simple C/C++ TBAA"}
+!2 = !{!"short", !0}
+!3 = !{!"int", !0}
diff --git a/test/CodeGen/Hexagon/circ_ldd_bug.ll b/test/CodeGen/Hexagon/circ_ldd_bug.ll
new file mode 100644
index 000000000000..d15b5c964eb7
--- /dev/null
+++ b/test/CodeGen/Hexagon/circ_ldd_bug.ll
@@ -0,0 +1,255 @@
+; RUN: llc -O2 < %s
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+; We would fail on this file with:
+; Unimplemented
+; UNREACHABLE executed at llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp:615!
+; This happened because after unrolling a loop with a ldd_circ instruction we
+; would have several TFCR and ldd_circ instruction sequences.
+; %vreg0 (CRRegs) = TFCR %vreg0 (IntRegs)
+;                 = ldd_circ( , , vreg0)
+; %vreg1 (CRRegs) = TFCR %vreg1 (IntRegs)
+;                 = ldd_circ( , , vreg0)
+; The scheduler would move the CRRegs to the top of the loop. The allocator
+; would try to spill the CRRegs after running out of them. We don't have code to
+; spill CRRegs and the above assertion would be triggered.
+declare i8* @llvm.hexagon.circ.ldd(i8*, i8*, i32, i32) nounwind
+
+define i32 @test(i16 zeroext %var0, i16* %var1, i16 signext %var2, i16* nocapture %var3) nounwind {
+entry:
+  %var4 = alloca i64, align 8
+  %conv = zext i16 %var0 to i32
+  %shr5 = lshr i32 %conv, 1
+  %idxprom = sext i16 %var2 to i32
+  %arrayidx = getelementptr inbounds i16, i16* %var1, i32 %idxprom
+  %0 = bitcast i16* %var3 to i64*
+  %1 = load i64, i64* %0, align 8, !tbaa !1
+  %2 = bitcast i16* %arrayidx to i8*
+  %3 = bitcast i64* %var4 to i8*
+  %shl = shl nuw nsw i32 %shr5, 3
+  %or = or i32 %shl, 83886080
+  %4 = call i8* @llvm.hexagon.circ.ldd(i8* %2, i8* %3, i32 %or, i32 -8)
+  %sub = add nsw i32 %shr5, -1
+  %cmp6 = icmp sgt i32 %sub, 0
+  %5 = load i64, i64* %var4, align 8, !tbaa !1
+  %6 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 0, i64 %1, i64 %5)
+  br i1 %cmp6, label %for.body.lr.ph, label %for.end
+
+for.body.lr.ph:                                   ; preds = %entry
+  %incdec.ptr = getelementptr inbounds i16, i16* %var3, i32 4
+  %7 = bitcast i16* %incdec.ptr to i64*
+  %8 = zext i16 %var0 to i32
+  %9 = lshr i32 %8, 1
+  %10 = add i32 %9, -1
+  %xtraiter = urem i32 %10, 8
+  %lcmp = icmp ne i32 %xtraiter, 0
+  br i1 %lcmp, label %unr.cmp60, label %for.body.lr.ph.split.split
+
+unr.cmp60:                                        ; preds = %for.body.lr.ph
+  %un.tmp61 = icmp eq i32 %xtraiter, 1
+  br i1 %un.tmp61, label %for.body.unr53, label %unr.cmp51
+
+unr.cmp51:                                        ; preds = %unr.cmp60
+  %un.tmp52 = icmp eq i32 %xtraiter, 2
+  br i1 %un.tmp52, label %for.body.unr44, label %unr.cmp42
+
+unr.cmp42:                                        ; preds = %unr.cmp51
+  %un.tmp43 = icmp eq i32 %xtraiter, 3
+  br i1 %un.tmp43, label %for.body.unr35, label %unr.cmp33
+
+unr.cmp33:                                        ; preds = %unr.cmp42
+  %un.tmp34 = icmp eq i32 %xtraiter, 4
+  br i1 %un.tmp34, label %for.body.unr26, label %unr.cmp24
+
+unr.cmp24:                                        ; preds = %unr.cmp33
+  %un.tmp25 = icmp eq i32 %xtraiter, 5
+  br i1 %un.tmp25, label %for.body.unr17, label %unr.cmp
+
+unr.cmp:                                          ; preds = %unr.cmp24
+  %un.tmp = icmp eq i32 %xtraiter, 6
+  br i1 %un.tmp, label %for.body.unr13, label %for.body.unr
+
+for.body.unr:                                     ; preds = %unr.cmp
+  %11 = call i8* @llvm.hexagon.circ.ldd(i8* %4, i8* %3, i32 %or, i32 -8)
+  %12 = load i64, i64* %7, align 8, !tbaa !1
+  %inc.unr = add nsw i32 0, 1
+  %incdec.ptr4.unr = getelementptr inbounds i64, i64* %7, i32 1
+  %cmp.unr = icmp slt i32 %inc.unr, %sub
+  %13 = load i64, i64* %var4, align 8, !tbaa !1
+  %14 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %6, i64 %12, i64 %13)
+  br label %for.body.unr13
+
+for.body.unr13:                                   ; preds = %for.body.unr, %unr.cmp
+  %15 = phi i64 [ %6, %unr.cmp ], [ %14, %for.body.unr ]
+  %pvar6.09.unr = phi i64* [ %7, %unr.cmp ], [ %incdec.ptr4.unr, %for.body.unr ]
+  %var8.0.in8.unr = phi i8* [ %4, %unr.cmp ], [ %11, %for.body.unr ]
+  %i.07.unr = phi i32 [ 0, %unr.cmp ], [ %inc.unr, %for.body.unr ]
+  %16 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr, i8* %3, i32 %or, i32 -8)
+  %17 = load i64, i64* %pvar6.09.unr, align 8, !tbaa !1
+  %inc.unr14 = add nsw i32 %i.07.unr, 1
+  %incdec.ptr4.unr15 = getelementptr inbounds i64, i64* %pvar6.09.unr, i32 1
+  %cmp.unr16 = icmp slt i32 %inc.unr14, %sub
+  %18 = load i64, i64* %var4, align 8, !tbaa !1
+  %19 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %15, i64 %17, i64 %18)
+  br label %for.body.unr17
+
+for.body.unr17:                                   ; preds = %for.body.unr13, %unr.cmp24
+  %20 = phi i64 [ %6, %unr.cmp24 ], [ %19, %for.body.unr13 ]
+  %pvar6.09.unr18 = phi i64* [ %7, %unr.cmp24 ], [ %incdec.ptr4.unr15, %for.body.unr13 ]
+  %var8.0.in8.unr19 = phi i8* [ %4, %unr.cmp24 ], [ %16, %for.body.unr13 ]
+  %i.07.unr20 = phi i32 [ 0, %unr.cmp24 ], [ %inc.unr14, %for.body.unr13 ]
+  %21 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr19, i8* %3, i32 %or, i32 -8)
+  %22 = load i64, i64* %pvar6.09.unr18, align 8, !tbaa !1
+  %inc.unr21 = add nsw i32 %i.07.unr20, 1
+  %incdec.ptr4.unr22 = getelementptr inbounds i64, i64* %pvar6.09.unr18, i32 1
+  %cmp.unr23 = icmp slt i32 %inc.unr21, %sub
+  %23 = load i64, i64* %var4, align 8, !tbaa !1
+  %24 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %20, i64 %22, i64 %23)
+  br label %for.body.unr26
+
+for.body.unr26:                                   ; preds = %for.body.unr17, %unr.cmp33
+  %25 = phi i64 [ %6, %unr.cmp33 ], [ %24, %for.body.unr17 ]
+  %pvar6.09.unr27 = phi i64* [ %7, %unr.cmp33 ], [ %incdec.ptr4.unr22, %for.body.unr17 ]
+  %var8.0.in8.unr28 = phi i8* [ %4, %unr.cmp33 ], [ %21, %for.body.unr17 ]
+  %i.07.unr29 = phi i32 [ 0, %unr.cmp33 ], [ %inc.unr21, %for.body.unr17 ]
+  %26 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr28, i8* %3, i32 %or, i32 -8)
+  %27 = load i64, i64* %pvar6.09.unr27, align 8, !tbaa !1
+  %inc.unr30 = add nsw i32 %i.07.unr29, 1
+  %incdec.ptr4.unr31 = getelementptr inbounds i64, i64* %pvar6.09.unr27, i32 1
+  %cmp.unr32 = icmp slt i32 %inc.unr30, %sub
+  %28 = load i64, i64* %var4, align 8, !tbaa !1
+  %29 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %25, i64 %27, i64 %28)
+  br label %for.body.unr35
+
+for.body.unr35:                                   ; preds = %for.body.unr26, %unr.cmp42
+  %30 = phi i64 [ %6, %unr.cmp42 ], [ %29, %for.body.unr26 ]
+  %pvar6.09.unr36 = phi i64* [ %7, %unr.cmp42 ], [ %incdec.ptr4.unr31, %for.body.unr26 ]
+  %var8.0.in8.unr37 = phi i8* [ %4, %unr.cmp42 ], [ %26, %for.body.unr26 ]
+  %i.07.unr38 = phi i32 [ 0, %unr.cmp42 ], [ %inc.unr30, %for.body.unr26 ]
+  %31 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr37, i8* %3, i32 %or, i32 -8)
+  %32 = load i64, i64* %pvar6.09.unr36, align 8, !tbaa !1
+  %inc.unr39 = add nsw i32 %i.07.unr38, 1
+  %incdec.ptr4.unr40 = getelementptr inbounds i64, i64* %pvar6.09.unr36, i32 1
+  %cmp.unr41 = icmp slt i32 %inc.unr39, %sub
+  %33 = load i64, i64* %var4, align 8, !tbaa !1
+  %34 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %30, i64 %32, i64 %33)
+  br label %for.body.unr44
+
+for.body.unr44:                                   ; preds = %for.body.unr35, %unr.cmp51
+  %35 = phi i64 [ %6, %unr.cmp51 ], [ %34, %for.body.unr35 ]
+  %pvar6.09.unr45 = phi i64* [ %7, %unr.cmp51 ], [ %incdec.ptr4.unr40, %for.body.unr35 ]
+  %var8.0.in8.unr46 = phi i8* [ %4, %unr.cmp51 ], [ %31, %for.body.unr35 ]
+  %i.07.unr47 = phi i32 [ 0, %unr.cmp51 ], [ %inc.unr39, %for.body.unr35 ]
+  %36 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr46, i8* %3, i32 %or, i32 -8)
+  %37 = load i64, i64* %pvar6.09.unr45, align 8, !tbaa !1
+  %inc.unr48 = add nsw i32 %i.07.unr47, 1
+  %incdec.ptr4.unr49 = getelementptr inbounds i64, i64* %pvar6.09.unr45, i32 1
+  %cmp.unr50 = icmp slt i32 %inc.unr48, %sub
+  %38 = load i64, i64* %var4, align 8, !tbaa !1
+  %39 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %35, i64 %37, i64 %38)
+  br label %for.body.unr53
+
+for.body.unr53:                                   ; preds = %for.body.unr44, %unr.cmp60
+  %40 = phi i64 [ %6, %unr.cmp60 ], [ %39, %for.body.unr44 ]
+  %pvar6.09.unr54 = phi i64* [ %7, %unr.cmp60 ], [ %incdec.ptr4.unr49, %for.body.unr44 ]
+  %var8.0.in8.unr55 = phi i8* [ %4, %unr.cmp60 ], [ %36, %for.body.unr44 ]
+  %i.07.unr56 = phi i32 [ 0, %unr.cmp60 ], [ %inc.unr48, %for.body.unr44 ]
+  %41 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr55, i8* %3, i32 %or, i32 -8)
+  %42 = load i64, i64* %pvar6.09.unr54, align 8, !tbaa !1
+  %inc.unr57 = add nsw i32 %i.07.unr56, 1
+  %incdec.ptr4.unr58 = getelementptr inbounds i64, i64* %pvar6.09.unr54, i32 1
+  %cmp.unr59 = icmp slt i32 %inc.unr57, %sub
+  %43 = load i64, i64* %var4, align 8, !tbaa !1
+  %44 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %40, i64 %42, i64 %43)
+  br label %for.body.lr.ph.split
+
+for.body.lr.ph.split:                             ; preds = %for.body.unr53
+  %45 = icmp ult i32 %10, 8
+  br i1 %45, label %for.end.loopexit, label %for.body.lr.ph.split.split
+
+for.body.lr.ph.split.split:                       ; preds = %for.body.lr.ph.split, %for.body.lr.ph
+  %.unr = phi i64 [ %44, %for.body.lr.ph.split ], [ %6, %for.body.lr.ph ]
+  %pvar6.09.unr62 = phi i64* [ %incdec.ptr4.unr58, %for.body.lr.ph.split ], [ %7, %for.body.lr.ph ]
+  %var8.0.in8.unr63 = phi i8* [ %41, %for.body.lr.ph.split ], [ %4, %for.body.lr.ph ]
+  %i.07.unr64 = phi i32 [ %inc.unr57, %for.body.lr.ph.split ], [ 0, %for.body.lr.ph ]
+  %.lcssa12.unr = phi i64 [ %44, %for.body.lr.ph.split ], [ 0, %for.body.lr.ph ]
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %for.body.lr.ph.split.split
+  %46 = phi i64 [ %.unr, %for.body.lr.ph.split.split ], [ %78, %for.body ]
+  %pvar6.09 = phi i64* [ %pvar6.09.unr62, %for.body.lr.ph.split.split ], [ %scevgep71, %for.body ]
+  %var8.0.in8 = phi i8* [ %var8.0.in8.unr63, %for.body.lr.ph.split.split ], [ %75, %for.body ]
+  %i.07 = phi i32 [ %i.07.unr64, %for.body.lr.ph.split.split ], [ %inc.7, %for.body ]
+  %47 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8, i8* %3, i32 %or, i32 -8)
+  %48 = load i64, i64* %pvar6.09, align 8, !tbaa !1
+  %inc = add nsw i32 %i.07, 1
+  %49 = load i64, i64* %var4, align 8, !tbaa !1
+  %50 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %46, i64 %48, i64 %49)
+  %51 = call i8* @llvm.hexagon.circ.ldd(i8* %47, i8* %3, i32 %or, i32 -8)
+  %scevgep = getelementptr i64, i64* %pvar6.09, i32 1
+  %52 = load i64, i64* %scevgep, align 8, !tbaa !1
+  %inc.1 = add nsw i32 %inc, 1
+  %53 = load i64, i64* %var4, align 8, !tbaa !1
+  %54 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %50, i64 %52, i64 %53)
+  %55 = call i8* @llvm.hexagon.circ.ldd(i8* %51, i8* %3, i32 %or, i32 -8)
+  %scevgep65 = getelementptr i64, i64* %scevgep, i32 1
+  %56 = load i64, i64* %scevgep65, align 8, !tbaa !1
+  %inc.2 = add nsw i32 %inc.1, 1
+  %57 = load i64, i64* %var4, align 8, !tbaa !1
+  %58 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %54, i64 %56, i64 %57)
+  %59 = call i8* @llvm.hexagon.circ.ldd(i8* %55, i8* %3, i32 %or, i32 -8)
+  %scevgep66 = getelementptr i64, i64* %scevgep65, i32 1
+  %60 = load i64, i64* %scevgep66, align 8, !tbaa !1
+  %inc.3 = add nsw i32 %inc.2, 1
+  %61 = load i64, i64* %var4, align 8, !tbaa !1
+  %62 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %58, i64 %60, i64 %61)
+  %63 = call i8* @llvm.hexagon.circ.ldd(i8* %59, i8* %3, i32 %or, i32 -8)
+  %scevgep67 = getelementptr i64, i64* %scevgep66, i32 1
+  %64 = load i64, i64* %scevgep67, align 8, !tbaa !1
+  %inc.4 = add nsw i32 %inc.3, 1
+  %65 = load i64, i64* %var4, align 8, !tbaa !1
+  %66 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %62, i64 %64, i64 %65)
+  %67 = call i8* @llvm.hexagon.circ.ldd(i8* %63, i8* %3, i32 %or, i32 -8)
+  %scevgep68 = getelementptr i64, i64* %scevgep67, i32 1
+  %68 = load i64, i64* %scevgep68, align 8, !tbaa !1
+  %inc.5 = add nsw i32 %inc.4, 1
+  %69 = load i64, i64* %var4, align 8, !tbaa !1
+  %70 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %66, i64 %68, i64 %69)
+  %71 = call i8* @llvm.hexagon.circ.ldd(i8* %67, i8* %3, i32 %or, i32 -8)
+  %scevgep69 = getelementptr i64, i64* %scevgep68, i32 1
+  %72 = load i64, i64* %scevgep69, align 8, !tbaa !1
+  %inc.6 = add nsw i32 %inc.5, 1
+  %73 = load i64, i64* %var4, align 8, !tbaa !1
+  %74 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %70, i64 %72, i64 %73)
+  %75 = call i8* @llvm.hexagon.circ.ldd(i8* %71, i8* %3, i32 %or, i32 -8)
+  %scevgep70 = getelementptr i64, i64* %scevgep69, i32 1
+  %76 = load i64, i64* %scevgep70, align 8, !tbaa !1
+  %inc.7 = add nsw i32 %inc.6, 1
+  %77 = load i64, i64* %var4, align 8, !tbaa !1
+  %78 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %74, i64 %76, i64 %77)
+  %cmp.7 = icmp slt i32 %inc.7, %sub
+  %scevgep71 = getelementptr i64, i64* %scevgep70, i32 1
+  br i1 %cmp.7, label %for.body, label %for.end.loopexit.unr-lcssa
+
+for.end.loopexit.unr-lcssa:                       ; preds = %for.body
+  %.lcssa12.ph = phi i64 [ %78, %for.body ]
+  br label %for.end.loopexit
+
+for.end.loopexit:                                 ; preds = %for.end.loopexit.unr-lcssa, %for.body.lr.ph.split
+  %.lcssa12 = phi i64 [ %44, %for.body.lr.ph.split ], [ %.lcssa12.ph, %for.end.loopexit.unr-lcssa ]
+  br label %for.end
+
+for.end:                                          ; preds = %for.end.loopexit, %entry
+  %.lcssa = phi i64 [ %6, %entry ], [ %.lcssa12, %for.end.loopexit ]
+  %79 = call i32 @llvm.hexagon.S2.vrndpackwhs(i64 %.lcssa)
+  ret i32 %79
+}
+
+declare i64 @llvm.hexagon.M2.vdmacs.s1(i64, i64, i64) nounwind readnone
+
+declare i32 @llvm.hexagon.S2.vrndpackwhs(i64) nounwind readnone
+
+!0 = !{!"long long", !1}
+!1 = !{!"omnipotent char", !2}
+!2 = !{!"Simple C/C++ TBAA"}
diff --git a/test/CodeGen/Hexagon/circ_ldw.ll b/test/CodeGen/Hexagon/circ_ldw.ll
new file mode 100644
index 000000000000..4511a9cf69da
--- /dev/null
+++ b/test/CodeGen/Hexagon/circ_ldw.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; CHECK:  r{{[0-9]*}} = memw(r{{[0-9]*.}}++{{.}}#-4:circ(m0))
+
+
+%union.vect64 = type { i64 }
+%union.vect32 = type { i32 }
+
+define i32* @HallowedBeThyName(%union.vect64* nocapture %pRx, %union.vect32* %pLut, %union.vect64* nocapture %pOut, i64 %dc.coerce, i32 %shift, i32 %numSamples) nounwind {
+entry:
+  %vLutNext = alloca i32, align 4
+  %0 = bitcast %union.vect32* %pLut to i8*
+  %1 = bitcast i32* %vLutNext to i8*
+  %2 = call i8* @llvm.hexagon.circ.ldw(i8* %0, i8* %1, i32 83886144, i32 -4)
+  %3 = bitcast i8* %2 to i32*
+  ret i32* %3
+}
+
+declare i8* @llvm.hexagon.circ.ldw(i8*, i8*, i32, i32) nounwind
diff --git a/test/CodeGen/Hexagon/circ_st.ll b/test/CodeGen/Hexagon/circ_st.ll
new file mode 100644
index 000000000000..244ca3bae714
--- /dev/null
+++ b/test/CodeGen/Hexagon/circ_st.ll
@@ -0,0 +1,108 @@
+; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s
+; Testing for these 5 variants of circular store:
+;   Q6_circ_store_update_B(inputLR, pDelay, -1, nConvLength, 4);
+;   Q6_circ_store_update_D(inputLR, pDelay, -1, nConvLength, 4);
+;   Q6_circ_store_update_HL(inputLR, pDelay, -1, nConvLength, 4);
+;   Q6_circ_store_update_HH(inputLR, pDelay, -1, nConvLength, 4);
+;   Q6_circ_store_update_W(inputLR, pDelay, -1, nConvLength, 4);
+; producing these
+;   memb(r1++#-1:circ(m0)) = r3
+;   memd(r1++#-8:circ(m0)) = r1:0
+;   memh(r1++#-2:circ(m0)) = r3
+;   memh(r1++#-2:circ(m0)) = r3.h
+;   memw(r1++#-4:circ(m0)) = r0
+
+; ModuleID = 'circ_st.i'
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+define zeroext i8 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %conv = zext i16 %filtMemLen to i32
+  %shr2 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %or = or i32 %shr2, 33554432
+; CHECK: memb(r{{[0-9]*}}{{.}}++{{.}}#-1:circ(m{{[0-1]}}))
+  %1 = tail call i8* @llvm.hexagon.circ.stb(i8* %0, i32 0, i32 %or, i32 -1)
+  %2 = load i8, i8* %1, align 1, !tbaa !0
+  ret i8 %2
+}
+
+declare i8* @llvm.hexagon.circ.stb(i8*, i32, i32, i32) nounwind
+
+define i64 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %conv = zext i16 %filtMemLen to i32
+  %shr1 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %shl = shl nuw nsw i32 %shr1, 3
+  %or = or i32 %shl, 83886080
+; CHECK: memd(r{{[0-9]*}}{{.}}++{{.}}#-8:circ(m{{[0-1]}}))
+  %1 = tail call i8* @llvm.hexagon.circ.std(i8* %0, i64 undef, i32 %or, i32 -8)
+  %2 = bitcast i8* %1 to i64*
+  %3 = load i64, i64* %2, align 8, !tbaa !0
+  ret i64 %3
+}
+
+declare i8* @llvm.hexagon.circ.std(i8*, i64, i32, i32) nounwind
+
+define signext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %conv = zext i16 %filtMemLen to i32
+  %shr2 = and i32 %conv, 65534
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %or = or i32 %shr2, 50331648
+; CHECK: memh(r{{[0-9]*}}{{.}}++{{.}}#-2:circ(m{{[0-1]}}))
+  %1 = tail call i8* @llvm.hexagon.circ.sth(i8* %0, i32 0, i32 %or, i32 -2)
+  %2 = bitcast i8* %1 to i16*
+  %3 = load i16, i16* %2, align 2, !tbaa !2
+  ret i16 %3
+}
+
+declare i8* @llvm.hexagon.circ.sth(i8*, i32, i32, i32) nounwind
+
+define signext i16 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %conv = zext i16 %filtMemLen to i32
+  %shr2 = and i32 %conv, 65534
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %or = or i32 %shr2, 50331648
+; CHECK: memh(r{{[0-9]*}}{{.}}++{{.}}#-2:circ(m{{[0-1]}})){{ *}}={{ *}}r{{[0-9]*}}.h
+  %1 = tail call i8* @llvm.hexagon.circ.sthhi(i8* %0, i32 0, i32 %or, i32 -2)
+  %2 = bitcast i8* %1 to i16*
+  %3 = load i16, i16* %2, align 2, !tbaa !2
+  ret i16 %3
+}
+
+declare i8* @llvm.hexagon.circ.sthhi(i8*, i32, i32, i32) nounwind
+
+define i32 @foo6(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
+entry:
+  %conv = zext i16 %filtMemLen to i32
+  %shr1 = lshr i32 %conv, 1
+  %idxprom = sext i16 %filtMemIndex to i32
+  %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
+  %0 = bitcast i16* %arrayidx to i8*
+  %shl = shl nuw nsw i32 %shr1, 2
+  %or = or i32 %shl, 67108864
+; CHECK: memw(r{{[0-9]*}}{{.}}++{{.}}#-4:circ(m{{[0-1]}}))
+  %1 = tail call i8* @llvm.hexagon.circ.stw(i8* %0, i32 undef, i32 %or, i32 -4)
+  %2 = bitcast i8* %1 to i32*
+  %3 = load i32, i32* %2, align 4, !tbaa !3
+  ret i32 %3
+}
+
+declare i8* @llvm.hexagon.circ.stw(i8*, i32, i32, i32) nounwind
+
+!0 = !{!"omnipotent char", !1}
+!1 = !{!"Simple C/C++ TBAA"}
+!2 = !{!"short", !0}
+!3 = !{!"int", !0}
diff --git a/test/CodeGen/Hexagon/clr_set_toggle.ll b/test/CodeGen/Hexagon/clr_set_toggle.ll
new file mode 100644
index 000000000000..87c52956129e
--- /dev/null
+++ b/test/CodeGen/Hexagon/clr_set_toggle.ll
@@ -0,0 +1,160 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5  < %s | FileCheck %s
+; Optimized bitwise operations.
+
+define i32 @my_clrbit(i32 %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
+  %x.addr = alloca i32, align 4
+  store i32 %x, i32* %x.addr, align 4
+  %0 = load i32, i32* %x.addr, align 4
+  %and = and i32 %0, 2147483647
+  ret i32 %and
+}
+
+define i64 @my_clrbit2(i64 %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
+  %x.addr = alloca i64, align 8
+  store i64 %x, i64* %x.addr, align 8
+  %0 = load i64, i64* %x.addr, align 8
+  %and = and i64 %0, -2147483649
+  ret i64 %and
+}
+
+define i64 @my_clrbit3(i64 %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
+  %x.addr = alloca i64, align 8
+  store i64 %x, i64* %x.addr, align 8
+  %0 = load i64, i64* %x.addr, align 8
+  %and = and i64 %0, 9223372036854775807
+  ret i64 %and
+}
+
+define i32 @my_clrbit4(i32 %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13)
+  %x.addr = alloca i32, align 4
+  store i32 %x, i32* %x.addr, align 4
+  %0 = load i32, i32* %x.addr, align 4
+  %and = and i32 %0, -8193
+  ret i32 %and
+}
+
+define i64 @my_clrbit5(i64 %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13)
+  %x.addr = alloca i64, align 8
+  store i64 %x, i64* %x.addr, align 8
+  %0 = load i64, i64* %x.addr, align 8
+  %and = and i64 %0, -8193
+  ret i64 %and
+}
+
+define i64 @my_clrbit6(i64 %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #27)
+  %x.addr = alloca i64, align 8
+  store i64 %x, i64* %x.addr, align 8
+  %0 = load i64, i64* %x.addr, align 8
+  %and = and i64 %0, -576460752303423489
+  ret i64 %and
+}
+
+define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind {
+entry:
+; CHECK: memh(r{{[0-9]+}}+#0){{ *}}={{ *}}setbit(#15)
+  %crc.addr = alloca i16, align 2
+  store i16 %crc, i16* %crc.addr, align 2
+  %0 = load i16, i16* %crc.addr, align 2
+  %conv = zext i16 %0 to i32
+  %or = or i32 %conv, 32768
+  %conv1 = trunc i32 %or to i16
+  store i16 %conv1, i16* %crc.addr, align 2
+  %1 = load i16, i16* %crc.addr, align 2
+  ret i16 %1
+}
+
+define i32 @my_setbit2(i32 %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15)
+  %x.addr = alloca i32, align 4
+  store i32 %x, i32* %x.addr, align 4
+  %0 = load i32, i32* %x.addr, align 4
+  %or = or i32 %0, 32768
+  ret i32 %or
+}
+
+define i64 @my_setbit3(i64 %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15)
+  %x.addr = alloca i64, align 8
+  store i64 %x, i64* %x.addr, align 8
+  %0 = load i64, i64* %x.addr, align 8
+  %or = or i64 %0, 32768
+  ret i64 %or
+}
+
+define i32 @my_setbit4(i32 %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #31)
+  %x.addr = alloca i32, align 4
+  store i32 %x, i32* %x.addr, align 4
+  %0 = load i32, i32* %x.addr, align 4
+  %or = or i32 %0, -2147483648
+  ret i32 %or
+}
+
+define i64 @my_setbit5(i64 %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #13)
+  %x.addr = alloca i64, align 8
+  store i64 %x, i64* %x.addr, align 8
+  %0 = load i64, i64* %x.addr, align 8
+  %or = or i64 %0, 35184372088832
+  ret i64 %or
+}
+
+define zeroext i16 @my_togglebit(i16 zeroext %crc) nounwind {
+entry:
+; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
+  %crc.addr = alloca i16, align 2
+  store i16 %crc, i16* %crc.addr, align 2
+  %0 = load i16, i16* %crc.addr, align 2
+  %conv = zext i16 %0 to i32
+  %xor = xor i32 %conv, 32768
+  %conv1 = trunc i32 %xor to i16
+  store i16 %conv1, i16* %crc.addr, align 2
+  %1 = load i16, i16* %crc.addr, align 2
+  ret i16 %1
+}
+
+define i32 @my_togglebit2(i32 %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
+  %x.addr = alloca i32, align 4
+  store i32 %x, i32* %x.addr, align 4
+  %0 = load i32, i32* %x.addr, align 4
+  %xor = xor i32 %0, 32768
+  ret i32 %xor
+}
+
+define i64 @my_togglebit3(i64 %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
+  %x.addr = alloca i64, align 8
+  store i64 %x, i64* %x.addr, align 8
+  %0 = load i64, i64* %x.addr, align 8
+  %xor = xor i64 %0, 32768
+  ret i64 %xor
+}
+
+define i64 @my_togglebit4(i64 %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #20)
+  %x.addr = alloca i64, align 8
+  store i64 %x, i64* %x.addr, align 8
+  %0 = load i64, i64* %x.addr, align 8
+  %xor = xor i64 %0, 4503599627370496
+  ret i64 %xor
+}
diff --git a/test/CodeGen/Hexagon/cmp-not.ll b/test/CodeGen/Hexagon/cmp-not.ll
deleted file mode 100644
index abcddc38b23b..000000000000
--- a/test/CodeGen/Hexagon/cmp-not.ll
+++ /dev/null
@@ -1,50 +0,0 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
-; Check that we generate matching compare insn.
-
-; Function Attrs: nounwind
-define i32 @neqi(i32 %argc) #0 {
-entry:
-  %p = alloca i8, align 1
-  %0 = tail call i1 @llvm.hexagon.C4.cmpneqi(i32 %argc, i32 512)
-  %conv = zext i1 %0 to i8
-  store volatile i8 %conv, i8* %p, align 1
-  %p.0.p.0. = load volatile i8* %p, align 1
-  %conv1 = zext i8 %p.0.p.0. to i32
-  ret i32 %conv1
-}
-; CHECK:	p{{[0-3]}}{{ *}} = !cmp.eq(r{{[0-9]+}}, ##512)
-
-; Function Attrs: nounwind readnone
-declare i1 @llvm.hexagon.C4.cmpneqi(i32, i32) #1
-
-; Function Attrs: nounwind
-define i32 @ngti(i32 %argc) #0 {
-entry:
-  %p = alloca i8, align 1
-  %0 = tail call i1 @llvm.hexagon.C4.cmpltei(i32 %argc, i32 4)
-  %conv = zext i1 %0 to i8
-  store volatile i8 %conv, i8* %p, align 1
-  %p.0.p.0. = load volatile i8* %p, align 1
-  %conv1 = zext i8 %p.0.p.0. to i32
-  ret i32 %conv1
-}
-; CHECK:	p{{[0-3]}}{{ *}} = !cmp.gt(r{{[0-9]+}}, #4)
-
-; Function Attrs: nounwind readnone
-declare i1 @llvm.hexagon.C4.cmpltei(i32, i32) #1
-
-; Function Attrs: nounwind
-define i32 @ngtui(i32 %argc) #0 {
-entry:
-  %p = alloca i8, align 1
-  %0 = tail call i1 @llvm.hexagon.C4.cmplteui(i32 %argc, i32 4)
-  %conv = zext i1 %0 to i8
-  store volatile i8 %conv, i8* %p, align 1
-  %p.0.p.0. = load volatile i8* %p, align 1
-  %conv1 = zext i8 %p.0.p.0. to i32
-  ret i32 %conv1
-}
-; CHECK: 	p{{[0-3]}}{{ *}} = !cmp.gtu(r{{[0-9]+}}, #4)
-
-; Function Attrs: nounwind readnone
-declare i1 @llvm.hexagon.C4.cmplteui(i32, i32) #1
diff --git a/test/CodeGen/Hexagon/cmp-to-predreg.ll b/test/CodeGen/Hexagon/cmp-to-predreg.ll
index d430b901866d..2b65343ab2cf 100644
--- a/test/CodeGen/Hexagon/cmp-to-predreg.ll
+++ b/test/CodeGen/Hexagon/cmp-to-predreg.ll
@@ -2,7 +2,7 @@
 ; Check that we generate compare to predicate register.
 
 define i32 @compare1(i32 %a, i32 %b) nounwind {
-; CHECK: p{{[0-3]}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
+; CHECK: p{{[0-3]}}{{ *}}={{ *[!]?}}cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
 entry:
   %cmp = icmp ne i32 %a, %b
   %add = add nsw i32 %a, %b
@@ -12,7 +12,7 @@ entry:
 }
 
 define i32 @compare2(i32 %a) nounwind {
-; CHECK: p{{[0-3]}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}#10)
+; CHECK: p{{[0-3]}}{{ *}}={{ *[!]?}}cmp.eq(r{{[0-9]+}},{{ *}}#10)
 entry:
   %cmp = icmp ne i32 %a, 10
   %add = add nsw i32 %a, 10
diff --git a/test/CodeGen/Hexagon/cmp_pred.ll b/test/CodeGen/Hexagon/cmp_pred.ll
index 37db3b499f63..39549a1f2d54 100644
--- a/test/CodeGen/Hexagon/cmp_pred.ll
+++ b/test/CodeGen/Hexagon/cmp_pred.ll
@@ -1,3 +1,4 @@
+; XFAIL:
 ; RUN: llc -march=hexagon -mcpu=hexagonv5  < %s | FileCheck %s
 ; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
 target triple = "hexagon"
diff --git a/test/CodeGen/Hexagon/cmp_pred2.ll b/test/CodeGen/Hexagon/cmp_pred2.ll
index a20b9f09b6e0..28f3e1bac8d1 100644
--- a/test/CodeGen/Hexagon/cmp_pred2.ll
+++ b/test/CodeGen/Hexagon/cmp_pred2.ll
@@ -11,7 +11,7 @@ entry:
   br i1 %cmp, label %if.then, label %entry.if.end_crit_edge
 
 entry.if.end_crit_edge:
-  %.pre = load i32* @c, align 4
+  %.pre = load i32, i32* @c, align 4
   br label %if.end
 
 if.then:
@@ -32,7 +32,7 @@ entry:
   br i1 %cmp, label %entry.if.end_crit_edge, label %if.then
 
 entry.if.end_crit_edge:
-  %.pre = load i32* @c, align 4
+  %.pre = load i32, i32* @c, align 4
   br label %if.end
 
 if.then:
@@ -53,7 +53,7 @@ entry:
   br i1 %cmp, label %entry.if.end_crit_edge, label %if.then
 
 entry.if.end_crit_edge:
-  %.pre = load i32* @c, align 4
+  %.pre = load i32, i32* @c, align 4
   br label %if.end
 
 if.then:
@@ -73,7 +73,7 @@ entry:
   br i1 %cmp, label %if.then, label %entry.if.end_crit_edge
 
 entry.if.end_crit_edge:
-  %.pre = load i32* @c, align 4
+  %.pre = load i32, i32* @c, align 4
   br label %if.end
 
 if.then:
diff --git a/test/CodeGen/Hexagon/cmp_pred_reg.ll b/test/CodeGen/Hexagon/cmp_pred_reg.ll
index 37db3b499f63..39549a1f2d54 100644
--- a/test/CodeGen/Hexagon/cmp_pred_reg.ll
+++ b/test/CodeGen/Hexagon/cmp_pred_reg.ll
@@ -1,3 +1,4 @@
+; XFAIL:
 ; RUN: llc -march=hexagon -mcpu=hexagonv5  < %s | FileCheck %s
 ; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
 target triple = "hexagon"
diff --git a/test/CodeGen/Hexagon/cmpb_pred.ll b/test/CodeGen/Hexagon/cmpb_pred.ll
index 0960da1fa060..1a43e6291696 100644
--- a/test/CodeGen/Hexagon/cmpb_pred.ll
+++ b/test/CodeGen/Hexagon/cmpb_pred.ll
@@ -1,3 +1,4 @@
+; XFAIL:
 ; RUN: llc -march=hexagon -mcpu=hexagonv5  < %s | FileCheck %s
 ; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
 target triple = "hexagon"
@@ -16,7 +17,7 @@ entry:
 define i32 @Func_3b(i32) nounwind readonly {
 entry:
 ; CHECK-NOT: mux
-  %1 = load i8* @Enum_global, align 1
+  %1 = load i8, i8* @Enum_global, align 1
   %2 = trunc i32 %0 to i8
   %cmp = icmp ne i8 %1, %2
   %selv = zext i1 %cmp to i32
@@ -35,7 +36,7 @@ entry:
 define i32 @Func_3d(i32) nounwind readonly {
 entry:
 ; CHECK-NOT: mux
-  %1 = load i8* @Enum_global, align 1
+  %1 = load i8, i8* @Enum_global, align 1
   %2 = trunc i32 %0 to i8
   %cmp = icmp eq i8 %1, %2
   %selv = zext i1 %cmp to i32
@@ -45,7 +46,7 @@ entry:
 define i32 @Func_3e(i32) nounwind readonly {
 entry:
 ; CHECK-NOT: mux
-  %1 = load i8* @Enum_global, align 1
+  %1 = load i8, i8* @Enum_global, align 1
   %2 = trunc i32 %0 to i8
   %cmp = icmp eq i8 %1, %2
   %selv = zext i1 %cmp to i32
diff --git a/test/CodeGen/Hexagon/combine.ll b/test/CodeGen/Hexagon/combine.ll
index 721998596c81..2e320d977d62 100644
--- a/test/CodeGen/Hexagon/combine.ll
+++ b/test/CodeGen/Hexagon/combine.ll
@@ -6,8 +6,8 @@
 
 define void @foo() nounwind {
 entry:
-  %0 = load i32* @j, align 4
-  %1 = load i64* @k, align 8
+  %0 = load i32, i32* @j, align 4
+  %1 = load i64, i64* @k, align 8
   %conv = trunc i64 %1 to i32
   %2 = call i64 @llvm.hexagon.A2.combinew(i32 %0, i32 %conv)
   store i64 %2, i64* @k, align 8
diff --git a/test/CodeGen/Hexagon/combine_ir.ll b/test/CodeGen/Hexagon/combine_ir.ll
index e100cf7196f1..634a5c82a916 100644
--- a/test/CodeGen/Hexagon/combine_ir.ll
+++ b/test/CodeGen/Hexagon/combine_ir.ll
@@ -4,7 +4,7 @@
 
 define void @word(i32* nocapture %a) nounwind {
 entry:
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %1 = zext i32 %0 to i64
   tail call void @bar(i64 %1) nounwind
   ret void
@@ -17,10 +17,10 @@ declare void @bar(i64)
 
 define void @halfword(i16* nocapture %a) nounwind {
 entry:
-  %0 = load i16* %a, align 2
+  %0 = load i16, i16* %a, align 2
   %1 = zext i16 %0 to i64
-  %add.ptr = getelementptr inbounds i16* %a, i32 1
-  %2 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %a, i32 1
+  %2 = load i16, i16* %add.ptr, align 2
   %3 = zext i16 %2 to i64
   %4 = shl nuw nsw i64 %3, 16
   %ins = or i64 %4, %1
@@ -33,10 +33,10 @@ entry:
 
 define void @byte(i8* nocapture %a) nounwind {
 entry:
-  %0 = load i8* %a, align 1
+  %0 = load i8, i8* %a, align 1
   %1 = zext i8 %0 to i64
-  %add.ptr = getelementptr inbounds i8* %a, i32 1
-  %2 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %a, i32 1
+  %2 = load i8, i8* %add.ptr, align 1
   %3 = zext i8 %2 to i64
   %4 = shl nuw nsw i64 %3, 8
   %ins = or i64 %4, %1
diff --git a/test/CodeGen/Hexagon/convertdptoint.ll b/test/CodeGen/Hexagon/convertdptoint.ll
index fa068c4c8a51..a09c2fd14b12 100644
--- a/test/CodeGen/Hexagon/convertdptoint.ll
+++ b/test/CodeGen/Hexagon/convertdptoint.ll
@@ -14,13 +14,13 @@ entry:
   store i32 0, i32* %retval
   store double 1.540000e+01, double* %a, align 8
   store double 9.100000e+00, double* %b, align 8
-  %0 = load double* %a, align 8
-  %1 = load double* %b, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
   %add = fadd double %0, %1
   store double %add, double* %c, align 8
-  %2 = load double* %c, align 8
+  %2 = load double, double* %c, align 8
   %conv = fptosi double %2 to i32
   store i32 %conv, i32* %i, align 4
-  %3 = load i32* %i, align 4
+  %3 = load i32, i32* %i, align 4
   ret i32 %3
 }
diff --git a/test/CodeGen/Hexagon/convertdptoll.ll b/test/CodeGen/Hexagon/convertdptoll.ll
index 1b4dd86bd01b..f46d46cf76b1 100644
--- a/test/CodeGen/Hexagon/convertdptoll.ll
+++ b/test/CodeGen/Hexagon/convertdptoll.ll
@@ -14,14 +14,14 @@ entry:
   store i32 0, i32* %retval
   store double 1.540000e+01, double* %a, align 8
   store double 9.100000e+00, double* %b, align 8
-  %0 = load double* %a, align 8
-  %1 = load double* %b, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
   %add = fadd double %0, %1
   store double %add, double* %c, align 8
-  %2 = load double* %c, align 8
+  %2 = load double, double* %c, align 8
   %conv = fptosi double %2 to i64
   store i64 %conv, i64* %i, align 8
-  %3 = load i64* %i, align 8
+  %3 = load i64, i64* %i, align 8
   %conv1 = trunc i64 %3 to i32
   ret i32 %conv1
 }
diff --git a/test/CodeGen/Hexagon/convertsptoint.ll b/test/CodeGen/Hexagon/convertsptoint.ll
index b8a9d6c8083c..7593e57d852f 100644
--- a/test/CodeGen/Hexagon/convertsptoint.ll
+++ b/test/CodeGen/Hexagon/convertsptoint.ll
@@ -14,13 +14,13 @@ entry:
   store i32 0, i32* %retval
   store float 0x402ECCCCC0000000, float* %a, align 4
   store float 0x4022333340000000, float* %b, align 4
-  %0 = load float* %a, align 4
-  %1 = load float* %b, align 4
+  %0 = load float, float* %a, align 4
+  %1 = load float, float* %b, align 4
   %add = fadd float %0, %1
   store float %add, float* %c, align 4
-  %2 = load float* %c, align 4
+  %2 = load float, float* %c, align 4
   %conv = fptosi float %2 to i32
   store i32 %conv, i32* %i, align 4
-  %3 = load i32* %i, align 4
+  %3 = load i32, i32* %i, align 4
   ret i32 %3
 }
diff --git a/test/CodeGen/Hexagon/convertsptoll.ll b/test/CodeGen/Hexagon/convertsptoll.ll
index 1c4df94784aa..d8432cbc812b 100644
--- a/test/CodeGen/Hexagon/convertsptoll.ll
+++ b/test/CodeGen/Hexagon/convertsptoll.ll
@@ -14,14 +14,14 @@ entry:
   store i32 0, i32* %retval
   store float 0x402ECCCCC0000000, float* %a, align 4
   store float 0x4022333340000000, float* %b, align 4
-  %0 = load float* %a, align 4
-  %1 = load float* %b, align 4
+  %0 = load float, float* %a, align 4
+  %1 = load float, float* %b, align 4
   %add = fadd float %0, %1
   store float %add, float* %c, align 4
-  %2 = load float* %c, align 4
+  %2 = load float, float* %c, align 4
   %conv = fptosi float %2 to i64
   store i64 %conv, i64* %i, align 8
-  %3 = load i64* %i, align 8
+  %3 = load i64, i64* %i, align 8
   %conv1 = trunc i64 %3 to i32
   ret i32 %conv1
 }
diff --git a/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll b/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll
index e942f8d0c5dd..b8f483298f8c 100644
--- a/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll
+++ b/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll
@@ -1,8 +1,10 @@
 ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
 
-; CHECK: r{{[0-9]+}}:{{[0-9]+}} |= lsr(r{{[0-9]+}}:{{[0-9]+}}, #4)
-; CHECK: r{{[0-9]+}}:{{[0-9]+}} &= lsr(r{{[0-9]+}}:{{[0-9]+}}, #2)
-; CHECK: r{{[0-9]+}} += lsr(r{{[0-9]+}}, #4)
+; CHECK-DAG: ct0({{r[0-9]*:[0-9]*}})
+; CHECK-DAG: cl0({{r[0-9]*:[0-9]*}})
+; CHECK-DAG: ct0({{r[0-9]*}})
+; CHECK-DAG: cl0({{r[0-9]*}})
+; CHECK-DAG: r{{[0-9]+}} += lsr(r{{[0-9]+}}, #4)
 
 define i32 @foo(i64 %a, i32 %b) nounwind  {
 entry:
diff --git a/test/CodeGen/Hexagon/dadd.ll b/test/CodeGen/Hexagon/dadd.ll
index 602978ac01d3..5fcd705bab23 100644
--- a/test/CodeGen/Hexagon/dadd.ll
+++ b/test/CodeGen/Hexagon/dadd.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -march=hexagon -mcpu=hexagonv5  < %s | FileCheck %s
 ; Check that we generate double precision floating point add in V5.
 
-; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfadd(r{{[0-9]+}}:{{[0-9]+}}, r{{[0-9]+}}:{{[0-9]+}})
+; CHECK: call __hexagon_adddf3
 
 
 define i32 @main() nounwind {
@@ -11,8 +11,8 @@ entry:
   %c = alloca double, align 8
   store double 1.540000e+01, double* %a, align 8
   store double 9.100000e+00, double* %b, align 8
-  %0 = load double* %a, align 8
-  %1 = load double* %b, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
   %add = fadd double %0, %1
   store double %add, double* %c, align 8
   ret i32 0
diff --git a/test/CodeGen/Hexagon/dmul.ll b/test/CodeGen/Hexagon/dmul.ll
index d7437739ee90..1b79e0aa7d70 100644
--- a/test/CodeGen/Hexagon/dmul.ll
+++ b/test/CodeGen/Hexagon/dmul.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -march=hexagon -mcpu=hexagonv5  < %s | FileCheck %s
 ; Check that we generate double precision floating point multiply in V5.
 
-; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfmpy(r{{[0-9]+}}:{{[0-9]+}}, r{{[0-9]+}}:{{[0-9]+}})
+; CHECK: call __hexagon_muldf3
 
 define i32 @main() nounwind {
 entry:
@@ -10,8 +10,8 @@ entry:
   %c = alloca double, align 8
   store double 1.540000e+01, double* %a, align 8
   store double 9.100000e+00, double* %b, align 8
-  %0 = load double* %b, align 8
-  %1 = load double* %a, align 8
+  %0 = load double, double* %b, align 8
+  %1 = load double, double* %a, align 8
   %mul = fmul double %0, %1
   store double %mul, double* %c, align 8
   ret i32 0
diff --git a/test/CodeGen/Hexagon/double.ll b/test/CodeGen/Hexagon/double.ll
index c3b6f378ec8a..b4d025cd7fd0 100644
--- a/test/CodeGen/Hexagon/double.ll
+++ b/test/CodeGen/Hexagon/double.ll
@@ -10,13 +10,13 @@ entry:
   store double* %acc, double** %acc.addr, align 4
   store double %num, double* %num.addr, align 8
   store double %num2, double* %num2.addr, align 8
-  %0 = load double** %acc.addr, align 4
-  %1 = load double* %0
-  %2 = load double* %num.addr, align 8
+  %0 = load double*, double** %acc.addr, align 4
+  %1 = load double, double* %0
+  %2 = load double, double* %num.addr, align 8
   %add = fadd double %1, %2
-  %3 = load double* %num2.addr, align 8
+  %3 = load double, double* %num2.addr, align 8
   %sub = fsub double %add, %3
-  %4 = load double** %acc.addr, align 4
+  %4 = load double*, double** %acc.addr, align 4
   store double %sub, double* %4
   ret void
 }
diff --git a/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll b/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll
index 54e7ce3bcdd3..6bf8224904ec 100644
--- a/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll
+++ b/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll
@@ -14,13 +14,13 @@ entry:
   store i32 0, i32* %retval
   store double 1.540000e+01, double* %a, align 8
   store double 9.100000e+00, double* %b, align 8
-  %0 = load double* %a, align 8
-  %1 = load double* %b, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
   %add = fadd double %0, %1
   store double %add, double* %c, align 8
-  %2 = load double* %c, align 8
+  %2 = load double, double* %c, align 8
   %conv = fptosi double %2 to i32
   store i32 %conv, i32* %i, align 4
-  %3 = load i32* %i, align 4
+  %3 = load i32, i32* %i, align 4
   ret i32 %3
 }
diff --git a/test/CodeGen/Hexagon/dsub.ll b/test/CodeGen/Hexagon/dsub.ll
index 4f9d39ed0b24..8b37301d84fb 100644
--- a/test/CodeGen/Hexagon/dsub.ll
+++ b/test/CodeGen/Hexagon/dsub.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -march=hexagon -mcpu=hexagonv5  < %s | FileCheck %s
 ; Check that we generate double precision floating point subtract in V5.
 
-; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfsub(r{{[0-9]+}}:{{[0-9]+}}, r{{[0-9]+}}:{{[0-9]+}})
+; CHECK: call __hexagon_subdf3
 
 define i32 @main() nounwind {
 entry:
@@ -10,8 +10,8 @@ entry:
   %c = alloca double, align 8
   store double 1.540000e+01, double* %a, align 8
   store double 9.100000e+00, double* %b, align 8
-  %0 = load double* %b, align 8
-  %1 = load double* %a, align 8
+  %0 = load double, double* %b, align 8
+  %1 = load double, double* %a, align 8
   %sub = fsub double %0, %1
   store double %sub, double* %c, align 8
   ret i32 0
diff --git a/test/CodeGen/Hexagon/dualstore.ll b/test/CodeGen/Hexagon/dualstore.ll
index f7d7e8bbe75d..33d9ce9b9351 100644
--- a/test/CodeGen/Hexagon/dualstore.ll
+++ b/test/CodeGen/Hexagon/dualstore.ll
@@ -1,17 +1,12 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hexagon-misched < %s | FileCheck %s
+; RUN: llc -march=hexagon -disable-hexagon-misched < %s | FileCheck %s
 ; Check that we generate dual stores in one packet in V4
 
-; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##500000
-; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##100000
-; CHECK-NEXT: }
+; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}=
+; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}=
 
-@Reg = global i32 0, align 4
-define i32 @main() nounwind {
+define i32 @main(i32 %v, i32* %p1, i32* %p2) nounwind {
 entry:
-  %number= alloca i32, align 4
-  store i32 500000, i32* %number, align 4
-  %number1= alloca i32, align 4
-  store i32 100000, i32* %number1, align 4
+  store i32 %v, i32* %p1, align 4
+  store i32 %v, i32* %p2, align 4
   ret i32 0
 }
-
diff --git a/test/CodeGen/Hexagon/expand-condsets-basic.ll b/test/CodeGen/Hexagon/expand-condsets-basic.ll
new file mode 100644
index 000000000000..16fe8af47b13
--- /dev/null
+++ b/test/CodeGen/Hexagon/expand-condsets-basic.ll
@@ -0,0 +1,11 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: if{{.*}}add
+; CHECK: if{{.*}}sub
+
+define i32 @foo (i1 %a, i32 %b, i32 %c, i32 %d) nounwind {
+  %1 = add i32 %b, %d
+  %2 = sub i32 %c, %d
+  %3 = select i1 %a, i32 %1, i32 %2
+  ret i32 %3
+}
+
diff --git a/test/CodeGen/Hexagon/expand-condsets-rm-segment.ll b/test/CodeGen/Hexagon/expand-condsets-rm-segment.ll
new file mode 100644
index 000000000000..cde7e6a09e1d
--- /dev/null
+++ b/test/CodeGen/Hexagon/expand-condsets-rm-segment.ll
@@ -0,0 +1,131 @@
+; RUN: llc -O2 < %s
+; REQUIRES: asserts
+
+target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
+target triple = "hexagon-unknown--elf"
+
+%struct.cpumask = type { [1 x i32] }
+%struct.load_weight = type { i32, i32 }
+
+@sysctl_sched_latency = global i32 6000000, align 4
+@normalized_sysctl_sched_latency = global i32 6000000, align 4
+@sysctl_sched_tunable_scaling = global i8 1, align 1
+@sysctl_sched_min_granularity = global i32 750000, align 4
+@normalized_sysctl_sched_min_granularity = global i32 750000, align 4
+@sysctl_sched_wakeup_granularity = global i32 1000000, align 4
+@normalized_sysctl_sched_wakeup_granularity = global i32 1000000, align 4
+@sysctl_sched_migration_cost = constant i32 500000, align 4
+@sysctl_sched_shares_window = global i32 10000000, align 4
+@sysctl_sched_child_runs_first = common global i32 0, align 4
+@cpu_online_mask = external constant %struct.cpumask*
+
+; Function Attrs: noinline nounwind
+define void @sched_init_granularity() #0 {
+entry:
+  tail call fastcc void @update_sysctl()
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define internal fastcc void @update_sysctl() #0 {
+entry:
+  %call = tail call i32 @get_update_sysctl_factor()
+  %0 = load i32, i32* @normalized_sysctl_sched_min_granularity, align 4, !tbaa !1
+  %mul = mul i32 %0, %call
+  store i32 %mul, i32* @sysctl_sched_min_granularity, align 4, !tbaa !1
+  %1 = load i32, i32* @normalized_sysctl_sched_latency, align 4, !tbaa !1
+  %mul1 = mul i32 %1, %call
+  store i32 %mul1, i32* @sysctl_sched_latency, align 4, !tbaa !1
+  %2 = load i32, i32* @normalized_sysctl_sched_wakeup_granularity, align 4, !tbaa !1
+  %mul2 = mul i32 %2, %call
+  store i32 %mul2, i32* @sysctl_sched_wakeup_granularity, align 4, !tbaa !1
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define i32 @calc_delta_mine(i32 %delta_exec, i32 %weight, %struct.load_weight* nocapture %lw) #0 {
+entry:
+  %cmp = icmp ugt i32 %weight, 1
+  %conv = zext i32 %delta_exec to i64
+  br i1 %cmp, label %if.then, label %if.end, !prof !5
+
+if.then:                                          ; preds = %entry
+  %conv2 = zext i32 %weight to i64
+  %mul = mul i64 %conv2, %conv
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+  %tmp.0 = phi i64 [ %mul, %if.then ], [ %conv, %entry ]
+  %inv_weight = getelementptr inbounds %struct.load_weight, %struct.load_weight* %lw, i32 0, i32 1
+  %0 = load i32, i32* %inv_weight, align 4, !tbaa !6
+  %tobool4 = icmp eq i32 %0, 0
+  br i1 %tobool4, label %if.then5, label %if.end22
+
+if.then5:                                         ; preds = %if.end
+  %weight7 = getelementptr inbounds %struct.load_weight, %struct.load_weight* %lw, i32 0, i32 0
+  %1 = load i32, i32* %weight7, align 4, !tbaa !9
+  %lnot9 = icmp eq i32 %1, 0
+  br i1 %lnot9, label %if.then17, label %if.else19, !prof !10
+
+if.then17:                                        ; preds = %if.then5
+  store i32 -1, i32* %inv_weight, align 4, !tbaa !6
+  br label %if.end22
+
+if.else19:                                        ; preds = %if.then5
+  %div = udiv i32 -1, %1
+  store i32 %div, i32* %inv_weight, align 4, !tbaa !6
+  br label %if.end22
+
+if.end22:                                         ; preds = %if.end, %if.then17, %if.else19
+  %2 = phi i32 [ %0, %if.end ], [ -1, %if.then17 ], [ %div, %if.else19 ]
+  %cmp23 = icmp ugt i64 %tmp.0, 4294967295
+  br i1 %cmp23, label %if.then31, label %if.else37, !prof !10
+
+if.then31:                                        ; preds = %if.end22
+  %add = add i64 %tmp.0, 32768
+  %shr = lshr i64 %add, 16
+  %conv33 = zext i32 %2 to i64
+  %mul34 = mul i64 %conv33, %shr
+  %add35 = add i64 %mul34, 32768
+  %shr36 = lshr i64 %add35, 16
+  br label %if.end43
+
+if.else37:                                        ; preds = %if.end22
+  %conv39 = zext i32 %2 to i64
+  %mul40 = mul i64 %conv39, %tmp.0
+  %add41 = add i64 %mul40, 2147483648
+  %shr42 = lshr i64 %add41, 32
+  br label %if.end43
+
+if.end43:                                         ; preds = %if.else37, %if.then31
+  %tmp.1 = phi i64 [ %shr36, %if.then31 ], [ %shr42, %if.else37 ]
+  %cmp49 = icmp ult i64 %tmp.1, 2147483647
+  %3 = trunc i64 %tmp.1 to i32
+  %conv51 = select i1 %cmp49, i32 %3, i32 2147483647
+  ret i32 %conv51
+}
+
+declare i32 @get_update_sysctl_factor() #0
+declare i32 @__bitmap_weight(i32*, i32) #1
+
+attributes #0 = { noinline nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"Clang 3.1"}
+!1 = !{!2, !2, i64 0}
+!2 = !{!"int", !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C/C++ TBAA"}
+!5 = !{!"branch_weights", i32 64, i32 4}
+!6 = !{!7, !8, i64 4}
+!7 = !{!"load_weight", !8, i64 0, !8, i64 4}
+!8 = !{!"long", !3, i64 0}
+!9 = !{!7, !8, i64 0}
+!10 = !{!"branch_weights", i32 4, i32 64}
+!11 = !{!12, !12, i64 0}
+!12 = !{!"any pointer", !3, i64 0}
+!13 = !{!3, !3, i64 0}
+!14 = !{i32 45854, i32 45878}
diff --git a/test/CodeGen/Hexagon/expand-condsets-undef.ll b/test/CodeGen/Hexagon/expand-condsets-undef.ll
new file mode 100644
index 000000000000..85e72aa22f0a
--- /dev/null
+++ b/test/CodeGen/Hexagon/expand-condsets-undef.ll
@@ -0,0 +1,28 @@
+; RUN: llc -O2 < %s
+; REQUIRES: asserts
+
+target datalayout = "e-m:e-p:32:32-i64:64-a:0-v32:32-n16:32"
+target triple = "hexagon"
+
+; Function Attrs: nounwind optsize ssp
+define internal fastcc void @foo() nounwind {
+if.else473:
+  %0 = load i64, i64* undef, align 8
+  %sub = sub nsw i64 undef, %0
+  %conv476 = sitofp i64 %sub to double
+  %mul477 = fmul double %conv476, 0x3F50624DE0000000
+  br i1 undef, label %cond.true540, label %cond.end548
+
+cond.true540:
+  %1 = fptrunc double %mul477 to float
+  %2 = fptosi float %1 to i32
+  br label %cond.end548
+
+cond.end548:
+  %cond549 = phi i32 [ %2, %cond.true540 ], [ undef, %if.else473 ]
+  call void @bar(i32 %cond549) nounwind
+  unreachable
+}
+
+declare void @bar(i32) nounwind
+
diff --git a/test/CodeGen/Hexagon/extload-combine.ll b/test/CodeGen/Hexagon/extload-combine.ll
index b3b8bf07032a..519177fc75fc 100644
--- a/test/CodeGen/Hexagon/extload-combine.ll
+++ b/test/CodeGen/Hexagon/extload-combine.ll
@@ -19,7 +19,7 @@ define i64 @short_test1() #0 {
 ; CHECK: combine(#0, [[VAR]])
 entry:
   store i16 0, i16* @a, align 2
-  %0 = load i16* @b, align 2
+  %0 = load i16, i16* @b, align 2
   %conv2 = zext i16 %0 to i64
   ret i64 %conv2
 }
@@ -30,7 +30,7 @@ define i64 @short_test2() #0 {
 ; CHECK: sxtw([[VAR1]])
 entry:
   store i16 0, i16* @a, align 2
-  %0 = load i16* @c, align 2
+  %0 = load i16, i16* @c, align 2
   %conv2 = sext i16 %0 to i64
   ret i64 %conv2
 }
@@ -41,7 +41,7 @@ define i64 @char_test1() #0 {
 ; CHECK: combine(#0, [[VAR2]])
 entry:
   store i8 0, i8* @char_a, align 1
-  %0 = load i8* @char_b, align 1
+  %0 = load i8, i8* @char_b, align 1
   %conv2 = zext i8 %0 to i64
   ret i64 %conv2
 }
@@ -52,7 +52,7 @@ define i64 @char_test2() #0 {
 ; CHECK: sxtw([[VAR3]])
 entry:
   store i8 0, i8* @char_a, align 1
-  %0 = load i8* @char_c, align 1
+  %0 = load i8, i8* @char_c, align 1
   %conv2 = sext i8 %0 to i64
   ret i64 %conv2
 }
@@ -63,7 +63,7 @@ define i64 @int_test1() #0 {
 ; CHECK: combine(#0, [[VAR4]])
 entry:
   store i32 0, i32* @int_a, align 4
-  %0 = load i32* @int_b, align 4
+  %0 = load i32, i32* @int_b, align 4
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
@@ -74,7 +74,7 @@ define i64 @int_test2() #0 {
 ; CHECK: sxtw([[VAR5]])
 entry:
   store i32 0, i32* @int_a, align 4
-  %0 = load i32* @int_c, align 4
+  %0 = load i32, i32* @int_c, align 4
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
diff --git a/test/CodeGen/Hexagon/fadd.ll b/test/CodeGen/Hexagon/fadd.ll
index b95e1475ff73..6cf0fbbccf73 100644
--- a/test/CodeGen/Hexagon/fadd.ll
+++ b/test/CodeGen/Hexagon/fadd.ll
@@ -10,8 +10,8 @@ entry:
   %c = alloca float, align 4
   store float 0x402ECCCCC0000000, float* %a, align 4
   store float 0x4022333340000000, float* %b, align 4
-  %0 = load float* %a, align 4
-  %1 = load float* %b, align 4
+  %0 = load float, float* %a, align 4
+  %1 = load float, float* %b, align 4
   %add = fadd float %0, %1
   store float %add, float* %c, align 4
   ret i32 0
diff --git a/test/CodeGen/Hexagon/fcmp.ll b/test/CodeGen/Hexagon/fcmp.ll
index e7b649e2b8c0..5cf3c57b5e9c 100644
--- a/test/CodeGen/Hexagon/fcmp.ll
+++ b/test/CodeGen/Hexagon/fcmp.ll
@@ -8,7 +8,7 @@ entry:
   %retval = alloca i32, align 4
   %y.addr = alloca float, align 4
   store float %y, float* %y.addr, align 4
-  %0 = load float* %y.addr, align 4
+  %0 = load float, float* %y.addr, align 4
   %cmp = fcmp ogt float %0, 0x406AD7EFA0000000
   br i1 %cmp, label %if.then, label %if.else
 
@@ -21,7 +21,7 @@ if.else:                                          ; preds = %entry
   br label %return
 
 return:                                           ; preds = %if.else, %if.then
-  %1 = load i32* %retval
+  %1 = load i32, i32* %retval
   ret i32 %1
 }
 
@@ -31,7 +31,7 @@ entry:
   %a = alloca float, align 4
   store i32 0, i32* %retval
   store float 0x40012E0A00000000, float* %a, align 4
-  %0 = load float* %a, align 4
+  %0 = load float, float* %a, align 4
   %call = call i32 @foo(float %0)
   ret i32 %call
 }
diff --git a/test/CodeGen/Hexagon/float.ll b/test/CodeGen/Hexagon/float.ll
index bec9f5852e3c..03d1fbf44cb6 100644
--- a/test/CodeGen/Hexagon/float.ll
+++ b/test/CodeGen/Hexagon/float.ll
@@ -10,13 +10,13 @@ entry:
   store float* %acc, float** %acc.addr, align 4
   store float %num, float* %num.addr, align 4
   store float %num2, float* %num2.addr, align 4
-  %0 = load float** %acc.addr, align 4
-  %1 = load float* %0
-  %2 = load float* %num.addr, align 4
+  %0 = load float*, float** %acc.addr, align 4
+  %1 = load float, float* %0
+  %2 = load float, float* %num.addr, align 4
   %add = fadd float %1, %2
-  %3 = load float* %num2.addr, align 4
+  %3 = load float, float* %num2.addr, align 4
   %sub = fsub float %add, %3
-  %4 = load float** %acc.addr, align 4
+  %4 = load float*, float** %acc.addr, align 4
   store float %sub, float* %4
   ret void
 }
diff --git a/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll b/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll
index bec9f5852e3c..03d1fbf44cb6 100644
--- a/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll
+++ b/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll
@@ -10,13 +10,13 @@ entry:
   store float* %acc, float** %acc.addr, align 4
   store float %num, float* %num.addr, align 4
   store float %num2, float* %num2.addr, align 4
-  %0 = load float** %acc.addr, align 4
-  %1 = load float* %0
-  %2 = load float* %num.addr, align 4
+  %0 = load float*, float** %acc.addr, align 4
+  %1 = load float, float* %0
+  %2 = load float, float* %num.addr, align 4
   %add = fadd float %1, %2
-  %3 = load float* %num2.addr, align 4
+  %3 = load float, float* %num2.addr, align 4
   %sub = fsub float %add, %3
-  %4 = load float** %acc.addr, align 4
+  %4 = load float*, float** %acc.addr, align 4
   store float %sub, float* %4
   ret void
 }
diff --git a/test/CodeGen/Hexagon/fmul.ll b/test/CodeGen/Hexagon/fmul.ll
index 4766845b1143..4f55d0bec471 100644
--- a/test/CodeGen/Hexagon/fmul.ll
+++ b/test/CodeGen/Hexagon/fmul.ll
@@ -11,8 +11,8 @@ entry:
   %c = alloca float, align 4
   store float 0x402ECCCCC0000000, float* %a, align 4
   store float 0x4022333340000000, float* %b, align 4
-  %0 = load float* %b, align 4
-  %1 = load float* %a, align 4
+  %0 = load float, float* %b, align 4
+  %1 = load float, float* %a, align 4
   %mul = fmul float %0, %1
   store float %mul, float* %c, align 4
   ret i32 0
diff --git a/test/CodeGen/Hexagon/frame.ll b/test/CodeGen/Hexagon/frame.ll
index dc87c732d6fe..e87acb8cd796 100644
--- a/test/CodeGen/Hexagon/frame.ll
+++ b/test/CodeGen/Hexagon/frame.ll
@@ -10,14 +10,14 @@
 define i32 @foo() nounwind {
 entry:
   %i = alloca i32, align 4
-  %0 = load i32* @num, align 4
+  %0 = load i32, i32* @num, align 4
   store i32 %0, i32* %i, align 4
-  %1 = load i32* %i, align 4
-  %2 = load i32* @acc, align 4
+  %1 = load i32, i32* %i, align 4
+  %2 = load i32, i32* @acc, align 4
   %mul = mul nsw i32 %1, %2
-  %3 = load i32* @num2, align 4
+  %3 = load i32, i32* @num2, align 4
   %add = add nsw i32 %mul, %3
   store i32 %add, i32* %i, align 4
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   ret i32 %4
 }
diff --git a/test/CodeGen/Hexagon/fsub.ll b/test/CodeGen/Hexagon/fsub.ll
index 07c866f4c2e2..ca7bdc4d0b38 100644
--- a/test/CodeGen/Hexagon/fsub.ll
+++ b/test/CodeGen/Hexagon/fsub.ll
@@ -10,8 +10,8 @@ entry:
   %c = alloca float, align 4
   store float 0x402ECCCCC0000000, float* %a, align 4
   store float 0x4022333340000000, float* %b, align 4
-  %0 = load float* %b, align 4
-  %1 = load float* %a, align 4
+  %0 = load float, float* %b, align 4
+  %1 = load float, float* %a, align 4
   %sub = fsub float %0, %1
   store float %sub, float* %c, align 4
   ret i32 0
diff --git a/test/CodeGen/Hexagon/fusedandshift.ll b/test/CodeGen/Hexagon/fusedandshift.ll
index 022b3c673458..59a1e1d84fcc 100644
--- a/test/CodeGen/Hexagon/fusedandshift.ll
+++ b/test/CodeGen/Hexagon/fusedandshift.ll
@@ -5,7 +5,7 @@
 
 define i32 @main(i16* %a, i16* %b) nounwind {
   entry:
-  %0 = load i16* %a, align 2
+  %0 = load i16, i16* %a, align 2
   %conv1 = sext i16 %0 to i32
   %shr1 = ashr i32 %conv1, 3
   %and1 = and i32 %shr1, 15
diff --git a/test/CodeGen/Hexagon/gp-plus-offset-load.ll b/test/CodeGen/Hexagon/gp-plus-offset-load.ll
index a1b80a65f82a..cd1aacc2318a 100644
--- a/test/CodeGen/Hexagon/gp-plus-offset-load.ll
+++ b/test/CodeGen/Hexagon/gp-plus-offset-load.ll
@@ -12,7 +12,7 @@ entry:
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %0 = load i32* getelementptr inbounds (%struct.struc* @foo, i32 0, i32 3), align 4
+  %0 = load i32, i32* getelementptr inbounds (%struct.struc, %struct.struc* @foo, i32 0, i32 3), align 4
   store i32 %0, i32* %ival, align 4
   br label %if.end
 
@@ -27,7 +27,7 @@ entry:
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %0 = load i8* getelementptr inbounds (%struct.struc* @foo, i32 0, i32 1), align 1
+  %0 = load i8, i8* getelementptr inbounds (%struct.struc, %struct.struc* @foo, i32 0, i32 1), align 1
   store i8 %0, i8* %ival, align 1
   br label %if.end
 
@@ -42,7 +42,7 @@ entry:
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %0 = load i16* getelementptr inbounds (%struct.struc* @foo, i32 0, i32 2), align 2
+  %0 = load i16, i16* getelementptr inbounds (%struct.struc, %struct.struc* @foo, i32 0, i32 2), align 2
   store i16 %0, i16* %ival, align 2
   br label %if.end
 
diff --git a/test/CodeGen/Hexagon/gp-plus-offset-store.ll b/test/CodeGen/Hexagon/gp-plus-offset-store.ll
index c782b30920ea..6b181cabe475 100644
--- a/test/CodeGen/Hexagon/gp-plus-offset-store.ll
+++ b/test/CodeGen/Hexagon/gp-plus-offset-store.ll
@@ -12,7 +12,7 @@ entry:
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  store i8 %ival, i8* getelementptr inbounds (%struct.struc* @foo, i32 0, i32 1), align 1
+  store i8 %ival, i8* getelementptr inbounds (%struct.struc, %struct.struc* @foo, i32 0, i32 1), align 1
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
@@ -26,7 +26,7 @@ entry:
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  store i16 %ival, i16* getelementptr inbounds (%struct.struc* @foo, i32 0, i32 2), align 2
+  store i16 %ival, i16* getelementptr inbounds (%struct.struc, %struct.struc* @foo, i32 0, i32 2), align 2
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
diff --git a/test/CodeGen/Hexagon/gp-rel.ll b/test/CodeGen/Hexagon/gp-rel.ll
index 561869e8ef35..bb7cb182bf1b 100644
--- a/test/CodeGen/Hexagon/gp-rel.ll
+++ b/test/CodeGen/Hexagon/gp-rel.ll
@@ -10,14 +10,14 @@ entry:
 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(#a)
 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(#b)
 ; CHECK: if{{ *}}(p{{[0-3]}}) memw(##c){{ *}}={{ *}}r{{[0-9]+}}
-  %0 = load i32* @a, align 4
-  %1 = load i32* @b, align 4
+  %0 = load i32, i32* @a, align 4
+  %1 = load i32, i32* @b, align 4
   %add = add nsw i32 %1, %0
   %cmp = icmp eq i32 %0, %1
   br i1 %cmp, label %if.then, label %entry.if.end_crit_edge
 
 entry.if.end_crit_edge:
-  %.pre = load i32* @c, align 4
+  %.pre = load i32, i32* @c, align 4
   br label %if.end
 
 if.then:
diff --git a/test/CodeGen/Hexagon/hwloop-cleanup.ll b/test/CodeGen/Hexagon/hwloop-cleanup.ll
index 6456ebff16d3..c04966a5a4b2 100644
--- a/test/CodeGen/Hexagon/hwloop-cleanup.ll
+++ b/test/CodeGen/Hexagon/hwloop-cleanup.ll
@@ -1,4 +1,5 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon -mcpu=hexagonv4 -no-phi-elim-live-out-early-exit \
+; RUN:    < %s | FileCheck %s
 ; Check that we remove the compare and induction variable instructions
 ; after generating hardware loops.
 ; Bug 6685.
@@ -20,11 +21,11 @@ for.body:                                         ; preds = %for.body.preheader,
   %sum.03 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
   %arrayidx.phi = phi i32* [ %arrayidx.inc, %for.body ], [ %b, %for.body.preheader ]
   %i.02 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
-  %0 = load i32* %arrayidx.phi, align 4
+  %0 = load i32, i32* %arrayidx.phi, align 4
   %add = add nsw i32 %0, %sum.03
   %inc = add nsw i32 %i.02, 1
   %exitcond = icmp eq i32 %inc, %n
-  %arrayidx.inc = getelementptr i32* %arrayidx.phi, i32 1
+  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
   br i1 %exitcond, label %for.end.loopexit, label %for.body
 
 for.end.loopexit:
@@ -50,11 +51,11 @@ for.body:
   %sum.02 = phi i32 [ 0, %entry ], [ %add, %for.body ]
   %arrayidx.phi = phi i32* [ %b, %entry ], [ %arrayidx.inc, %for.body ]
   %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
-  %0 = load i32* %arrayidx.phi, align 4
+  %0 = load i32, i32* %arrayidx.phi, align 4
   %add = add nsw i32 %0, %sum.02
   %inc = add nsw i32 %i.01, 1
   %exitcond = icmp eq i32 %inc, 40
-  %arrayidx.inc = getelementptr i32* %arrayidx.phi, i32 1
+  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
@@ -76,7 +77,7 @@ for.body:
   store i32 %i.01, i32* %arrayidx.phi, align 4
   %inc = add nsw i32 %i.01, 1
   %exitcond = icmp eq i32 %inc, 40
-  %arrayidx.inc = getelementptr i32* %arrayidx.phi, i32 1
+  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
diff --git a/test/CodeGen/Hexagon/hwloop-const.ll b/test/CodeGen/Hexagon/hwloop-const.ll
index 8204ddea3490..d549c1fef8c0 100644
--- a/test/CodeGen/Hexagon/hwloop-const.ll
+++ b/test/CodeGen/Hexagon/hwloop-const.ll
@@ -14,9 +14,9 @@ entry:
 ; CHECK: endloop
 for.body:                                         ; preds = %for.body, %entry
   %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds [25000 x i32]* @b, i32 0, i32 %i.02
+  %arrayidx = getelementptr inbounds [25000 x i32], [25000 x i32]* @b, i32 0, i32 %i.02
   store i32 %i.02, i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds [25000 x i32]* @a, i32 0, i32 %i.02
+  %arrayidx1 = getelementptr inbounds [25000 x i32], [25000 x i32]* @a, i32 0, i32 %i.02
   store i32 %i.02, i32* %arrayidx1, align 4
   %inc = add nsw i32 %i.02, 1
   %exitcond = icmp eq i32 %inc, 25000
diff --git a/test/CodeGen/Hexagon/hwloop-crit-edge.ll b/test/CodeGen/Hexagon/hwloop-crit-edge.ll
new file mode 100644
index 000000000000..4de4540c142e
--- /dev/null
+++ b/test/CodeGen/Hexagon/hwloop-crit-edge.ll
@@ -0,0 +1,58 @@
+; RUN: llc -O3 -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+;
+; Generate hardware loop when loop 'latch' block is different
+; from the loop 'exiting' block.
+
+; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}})
+; CHECK: endloop0
+
+define void @test(i32* nocapture %pFL, i16 signext %nBS, i16* nocapture readonly %pHT) #0 {
+entry:
+  %0 = load i32, i32* %pFL, align 4
+  %1 = tail call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %0, i32 246)
+  %2 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %1, i32 -13)
+  %3 = tail call i32 @llvm.hexagon.A2.sat(i64 %2)
+  store i32 %3, i32* %pFL, align 4
+  %cmp16 = icmp sgt i16 %nBS, 0
+  br i1 %cmp16, label %for.body.lr.ph, label %for.end
+
+for.body.lr.ph:
+  %4 = sext i16 %nBS to i32
+  br label %for.body
+
+for.body:
+  %5 = phi i32 [ %3, %for.body.lr.ph ], [ %.pre, %for.body.for.body_crit_edge ]
+  %arrayidx3.phi = phi i32* [ %pFL, %for.body.lr.ph ], [ %arrayidx3.inc, %for.body.for.body_crit_edge ]
+  %arrayidx5.phi = phi i16* [ %pHT, %for.body.lr.ph ], [ %arrayidx5.inc, %for.body.for.body_crit_edge ]
+  %i.017.pmt = phi i32 [ 1, %for.body.lr.ph ], [ %phitmp, %for.body.for.body_crit_edge ]
+  %6 = load i16, i16* %arrayidx5.phi, align 2
+  %conv6 = sext i16 %6 to i32
+  %7 = tail call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %5, i32 %conv6)
+  %8 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %7, i32 -13)
+  %9 = tail call i32 @llvm.hexagon.A2.sat(i64 %8)
+  store i32 %9, i32* %arrayidx3.phi, align 4
+  %exitcond = icmp eq i32 %i.017.pmt, %4
+  %arrayidx3.inc = getelementptr i32, i32* %arrayidx3.phi, i32 1
+  br i1 %exitcond, label %for.end.loopexit, label %for.body.for.body_crit_edge
+
+for.body.for.body_crit_edge:
+  %arrayidx5.inc = getelementptr i16, i16* %arrayidx5.phi, i32 1
+  %.pre = load i32, i32* %arrayidx3.inc, align 4
+  %phitmp = add i32 %i.017.pmt, 1
+  br label %for.body
+
+for.end.loopexit:
+  br label %for.end
+
+for.end:
+  ret void
+}
+
+declare i32 @llvm.hexagon.A2.sat(i64) #1
+
+declare i64 @llvm.hexagon.S2.asl.r.p(i64, i32) #1
+
+declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "ssp-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
diff --git a/test/CodeGen/Hexagon/hwloop-dbg.ll b/test/CodeGen/Hexagon/hwloop-dbg.ll
index 3c05884f6a7d..66c6662f735a 100644
--- a/test/CodeGen/Hexagon/hwloop-dbg.ll
+++ b/test/CodeGen/Hexagon/hwloop-dbg.ll
@@ -5,9 +5,9 @@ target triple = "hexagon"
 
 define void @foo(i32* nocapture %a, i32* nocapture %b) nounwind {
 entry:
-  tail call void @llvm.dbg.value(metadata i32* %a, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !17
-  tail call void @llvm.dbg.value(metadata i32* %b, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !18
-  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !19
+  tail call void @llvm.dbg.value(metadata i32* %a, i64 0, metadata !13, metadata !DIExpression()), !dbg !17
+  tail call void @llvm.dbg.value(metadata i32* %b, i64 0, metadata !14, metadata !DIExpression()), !dbg !18
+  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !15, metadata !DIExpression()), !dbg !19
   br label %for.body, !dbg !19
 
 for.body:                                         ; preds = %for.body, %entry
@@ -17,14 +17,14 @@ for.body:                                         ; preds = %for.body, %entry
   %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ]
   %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %b.addr.01 = phi i32* [ %b, %entry ], [ %incdec.ptr, %for.body ]
-  %incdec.ptr = getelementptr inbounds i32* %b.addr.01, i32 1, !dbg !21
-  tail call void @llvm.dbg.value(metadata i32* %incdec.ptr, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !21
-  %0 = load i32* %b.addr.01, align 4, !dbg !21
+  %incdec.ptr = getelementptr inbounds i32, i32* %b.addr.01, i32 1, !dbg !21
+  tail call void @llvm.dbg.value(metadata i32* %incdec.ptr, i64 0, metadata !14, metadata !DIExpression()), !dbg !21
+  %0 = load i32, i32* %b.addr.01, align 4, !dbg !21
   store i32 %0, i32* %arrayidx.phi, align 4, !dbg !21
   %inc = add nsw i32 %i.02, 1, !dbg !26
-  tail call void @llvm.dbg.value(metadata i32 %inc, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !26
+  tail call void @llvm.dbg.value(metadata i32 %inc, i64 0, metadata !15, metadata !DIExpression()), !dbg !26
   %exitcond = icmp eq i32 %inc, 10, !dbg !19
-  %arrayidx.inc = getelementptr i32* %arrayidx.phi, i32 1
+  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
   br i1 %exitcond, label %for.end, label %for.body, !dbg !19
 
 for.end:                                          ; preds = %for.body
@@ -37,28 +37,28 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!29}
 
-!0 = !{!"0x11\0012\00QuIC LLVM Hexagon Clang version 6.1-pre-unknown, (git://git-hexagon-aus.quicinc.com/llvm/clang-mainline.git e9382867661454cdf44addb39430741578e9765c) (llvm/llvm-mainline.git 36412bb1fcf03ed426d4437b41198bae066675ac)\001\00\000\00\001", !28, !2, !2, !3, !2, null} ; [ DW_TAG_compile_unit ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c] [DW_LANG_C99]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "QuIC LLVM Hexagon Clang version 6.1-pre-unknown, (git://git-hexagon-aus.quicinc.com/llvm/clang-mainline.git e9382867661454cdf44addb39430741578e9765c) (llvm/llvm-mainline.git 36412bb1fcf03ed426d4437b41198bae066675ac)", isOptimized: true, emissionKind: 1, file: !28, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2)
 !2 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\001\001", !28, null, !7, null, void (i32*, i32*)* @foo, null, null, !11} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!6 = !{!"0x29", !28} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !28, scope: null, type: !7, function: void (i32*, i32*)* @foo, variables: !11)
+!6 = !DIFile(filename: "hwloop-dbg.c", directory: "/usr2/kparzysz/s.hex/t")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9, !9}
-!9 = !{!"0xf\00\000\0032\0032\000\000", null, null, !10} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from int]
-!10 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !10)
+!10 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !11 = !{!13, !14, !15}
-!13 = !{!"0x101\00a\0016777217\000", !5, !6, !9} ; [ DW_TAG_arg_variable ] [a] [line 1]
-!14 = !{!"0x101\00b\0033554433\000", !5, !6, !9} ; [ DW_TAG_arg_variable ] [b] [line 1]
-!15 = !{!"0x100\00i\002\000", !16, !6, !10} ; [ DW_TAG_auto_variable ] [i] [line 2]
-!16 = !{!"0xb\001\0026\000", !28, !5} ; [ DW_TAG_lexical_block ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c]
-!17 = !MDLocation(line: 1, column: 15, scope: !5)
-!18 = !MDLocation(line: 1, column: 23, scope: !5)
-!19 = !MDLocation(line: 3, column: 8, scope: !20)
-!20 = !{!"0xb\003\003\001", !28, !16} ; [ DW_TAG_lexical_block ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c]
-!21 = !MDLocation(line: 4, column: 5, scope: !22)
-!22 = !{!"0xb\003\0028\002", !28, !20} ; [ DW_TAG_lexical_block ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c]
-!26 = !MDLocation(line: 3, column: 23, scope: !20)
-!27 = !MDLocation(line: 6, column: 1, scope: !16)
-!28 = !{!"hwloop-dbg.c", !"/usr2/kparzysz/s.hex/t"}
-!29 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 1, arg: 1, scope: !5, file: !6, type: !9)
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 1, arg: 2, scope: !5, file: !6, type: !9)
+!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 2, scope: !16, file: !6, type: !10)
+!16 = distinct !DILexicalBlock(line: 1, column: 26, file: !28, scope: !5)
+!17 = !DILocation(line: 1, column: 15, scope: !5)
+!18 = !DILocation(line: 1, column: 23, scope: !5)
+!19 = !DILocation(line: 3, column: 8, scope: !20)
+!20 = distinct !DILexicalBlock(line: 3, column: 3, file: !28, scope: !16)
+!21 = !DILocation(line: 4, column: 5, scope: !22)
+!22 = distinct !DILexicalBlock(line: 3, column: 28, file: !28, scope: !20)
+!26 = !DILocation(line: 3, column: 23, scope: !20)
+!27 = !DILocation(line: 6, column: 1, scope: !16)
+!28 = !DIFile(filename: "hwloop-dbg.c", directory: "/usr2/kparzysz/s.hex/t")
+!29 = !{i32 1, !"Debug Info Version", i32 3}
 !30 = !{i32 0}
diff --git a/test/CodeGen/Hexagon/hwloop-le.ll b/test/CodeGen/Hexagon/hwloop-le.ll
index 9c8cec7c2a1b..85a1b3db673b 100644
--- a/test/CodeGen/Hexagon/hwloop-le.ll
+++ b/test/CodeGen/Hexagon/hwloop-le.ll
@@ -14,8 +14,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 28395, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -43,8 +43,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 9073, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -72,8 +72,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 21956, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -101,8 +101,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 16782, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -130,8 +130,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 19097, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -159,8 +159,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -188,8 +188,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -217,8 +217,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -246,8 +246,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -275,8 +275,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -304,8 +304,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -333,8 +333,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -362,8 +362,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -391,8 +391,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -420,8 +420,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
diff --git a/test/CodeGen/Hexagon/hwloop-loop1.ll b/test/CodeGen/Hexagon/hwloop-loop1.ll
new file mode 100644
index 000000000000..8b02736e0374
--- /dev/null
+++ b/test/CodeGen/Hexagon/hwloop-loop1.ll
@@ -0,0 +1,68 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+;
+; Generate loop1 instruction for double loop sequence.
+
+; CHECK: loop0(.LBB{{.}}_{{.}}, #100)
+; CHECK: endloop0
+; CHECK: loop1(.LBB{{.}}_{{.}}, #100)
+; CHECK: loop0(.LBB{{.}}_{{.}}, #100)
+; CHECK: endloop0
+; CHECK: endloop1
+
+define i32 @main() #0 {
+entry:
+  %array = alloca [100 x i32], align 8
+  %doublearray = alloca [100 x [100 x i32]], align 8
+  %0 = bitcast [100 x i32]* %array to i8*
+  call void @llvm.lifetime.start(i64 400, i8* %0) #1
+  %1 = bitcast [100 x [100 x i32]]* %doublearray to i8*
+  call void @llvm.lifetime.start(i64 40000, i8* %1) #1
+  %arrayidx1 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %doublearray, i32 0, i32 10, i32 10
+  %arrayidx2.gep = getelementptr [100 x i32], [100 x i32]* %array, i32 0, i32 0
+  br label %for.body
+
+for.body:
+  %2 = phi i32 [ undef, %entry ], [ %.pre, %for.body.for.body_crit_edge ]
+  %sum.031 = phi i32 [ undef, %entry ], [ %add, %for.body.for.body_crit_edge ]
+  %arrayidx2.phi = phi i32* [ %arrayidx2.gep, %entry ], [ %arrayidx2.inc, %for.body.for.body_crit_edge ]
+  %i.030 = phi i32 [ 1, %entry ], [ %phitmp, %for.body.for.body_crit_edge ]
+  %add = add nsw i32 %2, %sum.031
+  %exitcond33 = icmp eq i32 %i.030, 100
+  %arrayidx2.inc = getelementptr i32, i32* %arrayidx2.phi, i32 1
+  br i1 %exitcond33, label %for.cond7.preheader.preheader, label %for.body.for.body_crit_edge
+
+for.cond7.preheader.preheader:
+  br label %for.cond7.preheader
+
+for.body.for.body_crit_edge:
+  %.pre = load i32, i32* %arrayidx2.inc, align 4
+  %phitmp = add i32 %i.030, 1
+  br label %for.body
+
+for.cond7.preheader:
+  %i.129 = phi i32 [ %inc16, %for.inc15 ], [ 0, %for.cond7.preheader.preheader ]
+  br label %for.body9
+
+for.body9:
+  %j.028 = phi i32 [ 0, %for.cond7.preheader ], [ %inc13, %for.body9 ]
+  %arrayidx11 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %doublearray, i32 0, i32 %i.129, i32 %j.028
+  store i32 %add, i32* %arrayidx11, align 4
+  %inc13 = add nsw i32 %j.028, 1
+  %exitcond = icmp eq i32 %inc13, 100
+  br i1 %exitcond, label %for.inc15, label %for.body9
+
+for.inc15:
+  %inc16 = add nsw i32 %i.129, 1
+  %exitcond32 = icmp eq i32 %inc16, 100
+  br i1 %exitcond32, label %for.end17, label %for.cond7.preheader
+
+for.end17:
+  %3 = load i32, i32* %arrayidx1, align 8
+  call void @llvm.lifetime.end(i64 40000, i8* %1) #1
+  call void @llvm.lifetime.end(i64 400, i8* %0) #1
+  ret i32 %3
+}
+
+declare void @llvm.lifetime.start(i64, i8* nocapture) #1
+
+declare void @llvm.lifetime.end(i64, i8* nocapture) #1
diff --git a/test/CodeGen/Hexagon/hwloop-lt.ll b/test/CodeGen/Hexagon/hwloop-lt.ll
index 7e43733da2a6..7e2ad2a4678e 100644
--- a/test/CodeGen/Hexagon/hwloop-lt.ll
+++ b/test/CodeGen/Hexagon/hwloop-lt.ll
@@ -1,7 +1,6 @@
 ; RUN: llc -march=hexagon -mcpu=hexagonv4 -O3 < %s | FileCheck %s
 
-
-; CHECK: test_pos1_ir_slt
+; CHECK-LABEL: @test_pos1_ir_slt
 ; CHECK: loop0
 ; a < b
 define void @test_pos1_ir_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
@@ -9,13 +8,13 @@ entry:
   %cmp3 = icmp slt i32 8531, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
-for.body.lr.ph:                                   ; preds = %entry
+for.body.lr.ph:
   br label %for.body
 
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
+for.body:
   %i.04 = phi i32 [ 8531, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -24,13 +23,11 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %cmp = icmp slt i32 %inc, %b
   br i1 %cmp, label %for.body, label %for.end
 
-for.end:                                          ; preds = %for.body, %entry
+for.end:
   ret void
 }
 
-
-
-; CHECK: test_pos2_ir_slt
+; CHECK-LABEL: @test_pos2_ir_slt
 ; CHECK: loop0
 ; a < b
 define void @test_pos2_ir_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
@@ -38,13 +35,13 @@ entry:
   %cmp3 = icmp slt i32 9152, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
-for.body.lr.ph:                                   ; preds = %entry
+for.body.lr.ph:
   br label %for.body
 
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
+for.body:
   %i.04 = phi i32 [ 9152, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -53,13 +50,11 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %cmp = icmp slt i32 %inc, %b
   br i1 %cmp, label %for.body, label %for.end
 
-for.end:                                          ; preds = %for.body, %entry
+for.end:
   ret void
 }
 
-
-
-; CHECK: test_pos4_ir_slt
+; CHECK-LABEL: @test_pos4_ir_slt
 ; CHECK: loop0
 ; a < b
 define void @test_pos4_ir_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
@@ -67,13 +62,13 @@ entry:
   %cmp3 = icmp slt i32 18851, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
-for.body.lr.ph:                                   ; preds = %entry
+for.body.lr.ph:
   br label %for.body
 
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
+for.body:
   %i.04 = phi i32 [ 18851, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -82,13 +77,11 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %cmp = icmp slt i32 %inc, %b
   br i1 %cmp, label %for.body, label %for.end
 
-for.end:                                          ; preds = %for.body, %entry
+for.end:
   ret void
 }
 
-
-
-; CHECK: test_pos8_ir_slt
+; CHECK-LABEL: @test_pos8_ir_slt
 ; CHECK: loop0
 ; a < b
 define void @test_pos8_ir_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
@@ -96,13 +89,13 @@ entry:
   %cmp3 = icmp slt i32 25466, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
-for.body.lr.ph:                                   ; preds = %entry
+for.body.lr.ph:
   br label %for.body
 
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
+for.body:
   %i.04 = phi i32 [ 25466, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -111,13 +104,11 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %cmp = icmp slt i32 %inc, %b
   br i1 %cmp, label %for.body, label %for.end
 
-for.end:                                          ; preds = %for.body, %entry
+for.end:
   ret void
 }
 
-
-
-; CHECK: test_pos16_ir_slt
+; CHECK-LABEL: @test_pos16_ir_slt
 ; CHECK: loop0
 ; a < b
 define void @test_pos16_ir_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
@@ -125,13 +116,13 @@ entry:
   %cmp3 = icmp slt i32 9295, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
-for.body.lr.ph:                                   ; preds = %entry
+for.body.lr.ph:
   br label %for.body
 
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
+for.body:
   %i.04 = phi i32 [ 9295, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -140,13 +131,11 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %cmp = icmp slt i32 %inc, %b
   br i1 %cmp, label %for.body, label %for.end
 
-for.end:                                          ; preds = %for.body, %entry
+for.end:
   ret void
 }
 
-
-
-; CHECK: test_pos1_ri_slt
+; CHECK-LABEL: @test_pos1_ri_slt
 ; CHECK: loop0
 ; a < b
 define void @test_pos1_ri_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
@@ -154,13 +143,13 @@ entry:
   %cmp3 = icmp slt i32 %a, 31236
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
-for.body.lr.ph:                                   ; preds = %entry
+for.body.lr.ph:
   br label %for.body
 
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
+for.body:
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -169,13 +158,11 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %cmp = icmp slt i32 %inc, 31236
   br i1 %cmp, label %for.body, label %for.end
 
-for.end:                                          ; preds = %for.body, %entry
+for.end:
   ret void
 }
 
-
-
-; CHECK: test_pos2_ri_slt
+; CHECK-LABEL: @test_pos2_ri_slt
 ; CHECK: loop0
 ; a < b
 define void @test_pos2_ri_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
@@ -183,13 +170,13 @@ entry:
   %cmp3 = icmp slt i32 %a, 22653
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
-for.body.lr.ph:                                   ; preds = %entry
+for.body.lr.ph:
   br label %for.body
 
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
+for.body:
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -198,13 +185,11 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %cmp = icmp slt i32 %inc, 22653
   br i1 %cmp, label %for.body, label %for.end
 
-for.end:                                          ; preds = %for.body, %entry
+for.end:
   ret void
 }
 
-
-
-; CHECK: test_pos4_ri_slt
+; CHECK-LABEL: @test_pos4_ri_slt
 ; CHECK: loop0
 ; a < b
 define void @test_pos4_ri_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
@@ -212,13 +197,13 @@ entry:
   %cmp3 = icmp slt i32 %a, 1431
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
-for.body.lr.ph:                                   ; preds = %entry
+for.body.lr.ph:
   br label %for.body
 
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
+for.body:
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -227,13 +212,11 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %cmp = icmp slt i32 %inc, 1431
   br i1 %cmp, label %for.body, label %for.end
 
-for.end:                                          ; preds = %for.body, %entry
+for.end:
   ret void
 }
 
-
-
-; CHECK: test_pos8_ri_slt
+; CHECK-LABEL: @test_pos8_ri_slt
 ; CHECK: loop0
 ; a < b
 define void @test_pos8_ri_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
@@ -241,13 +224,13 @@ entry:
   %cmp3 = icmp slt i32 %a, 22403
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
-for.body.lr.ph:                                   ; preds = %entry
+for.body.lr.ph:
   br label %for.body
 
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
+for.body:
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -256,13 +239,11 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %cmp = icmp slt i32 %inc, 22403
   br i1 %cmp, label %for.body, label %for.end
 
-for.end:                                          ; preds = %for.body, %entry
+for.end:
   ret void
 }
 
-
-
-; CHECK: test_pos16_ri_slt
+; CHECK-LABEL: @test_pos16_ri_slt
 ; CHECK: loop0
 ; a < b
 define void @test_pos16_ri_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
@@ -270,13 +251,13 @@ entry:
   %cmp3 = icmp slt i32 %a, 21715
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
-for.body.lr.ph:                                   ; preds = %entry
+for.body.lr.ph:
   br label %for.body
 
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
+for.body:
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -285,13 +266,11 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %cmp = icmp slt i32 %inc, 21715
   br i1 %cmp, label %for.body, label %for.end
 
-for.end:                                          ; preds = %for.body, %entry
+for.end:
   ret void
 }
 
-
-
-; CHECK: test_pos1_rr_slt
+; CHECK-LABEL: @test_pos1_rr_slt
 ; CHECK: loop0
 ; a < b
 define void @test_pos1_rr_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
@@ -299,13 +278,13 @@ entry:
   %cmp3 = icmp slt i32 %a, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
-for.body.lr.ph:                                   ; preds = %entry
+for.body.lr.ph:
   br label %for.body
 
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
+for.body:
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -314,13 +293,11 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %cmp = icmp slt i32 %inc, %b
   br i1 %cmp, label %for.body, label %for.end
 
-for.end:                                          ; preds = %for.body, %entry
+for.end:
   ret void
 }
 
-
-
-; CHECK: test_pos2_rr_slt
+; CHECK-LABEL: @test_pos2_rr_slt
 ; CHECK: loop0
 ; a < b
 define void @test_pos2_rr_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
@@ -328,13 +305,13 @@ entry:
   %cmp3 = icmp slt i32 %a, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
-for.body.lr.ph:                                   ; preds = %entry
+for.body.lr.ph:
   br label %for.body
 
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
+for.body:
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -343,13 +320,11 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %cmp = icmp slt i32 %inc, %b
   br i1 %cmp, label %for.body, label %for.end
 
-for.end:                                          ; preds = %for.body, %entry
+for.end:
   ret void
 }
 
-
-
-; CHECK: test_pos4_rr_slt
+; CHECK-LABEL: @test_pos4_rr_slt
 ; CHECK: loop0
 ; a < b
 define void @test_pos4_rr_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
@@ -357,13 +332,13 @@ entry:
   %cmp3 = icmp slt i32 %a, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
-for.body.lr.ph:                                   ; preds = %entry
+for.body.lr.ph:
   br label %for.body
 
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
+for.body:
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -372,13 +347,11 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %cmp = icmp slt i32 %inc, %b
   br i1 %cmp, label %for.body, label %for.end
 
-for.end:                                          ; preds = %for.body, %entry
+for.end:
   ret void
 }
 
-
-
-; CHECK: test_pos8_rr_slt
+; CHECK-LABEL: @test_pos8_rr_slt
 ; CHECK: loop0
 ; a < b
 define void @test_pos8_rr_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
@@ -386,13 +359,13 @@ entry:
   %cmp3 = icmp slt i32 %a, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
-for.body.lr.ph:                                   ; preds = %entry
+for.body.lr.ph:
   br label %for.body
 
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
+for.body:
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -401,13 +374,11 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %cmp = icmp slt i32 %inc, %b
   br i1 %cmp, label %for.body, label %for.end
 
-for.end:                                          ; preds = %for.body, %entry
+for.end:
   ret void
 }
 
-
-
-; CHECK: test_pos16_rr_slt
+; CHECK-LABEL: @test_pos16_rr_slt
 ; CHECK: loop0
 ; a < b
 define void @test_pos16_rr_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
@@ -415,13 +386,13 @@ entry:
   %cmp3 = icmp slt i32 %a, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
-for.body.lr.ph:                                   ; preds = %entry
+for.body.lr.ph:
   br label %for.body
 
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
+for.body:
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -430,7 +401,7 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %cmp = icmp slt i32 %inc, %b
   br i1 %cmp, label %for.body, label %for.end
 
-for.end:                                          ; preds = %for.body, %entry
+for.end:
   ret void
 }
 
diff --git a/test/CodeGen/Hexagon/hwloop-lt1.ll b/test/CodeGen/Hexagon/hwloop-lt1.ll
index cf5874011ee0..16fe728fa7bc 100644
--- a/test/CodeGen/Hexagon/hwloop-lt1.ll
+++ b/test/CodeGen/Hexagon/hwloop-lt1.ll
@@ -19,10 +19,10 @@ polly.loop_body:                                  ; preds = %entry, %polly.loop_
   %p_vector_iv14 = or i32 %polly.loopiv16, 1
   %p_vector_iv3 = add i32 %p_vector_iv14, 1
   %p_vector_iv415 = or i32 %polly.loopiv16, 3
-  %p_arrayidx = getelementptr [400 x i8]* @A, i32 0, i32 %polly.loopiv16
-  %p_arrayidx5 = getelementptr [400 x i8]* @A, i32 0, i32 %p_vector_iv14
-  %p_arrayidx6 = getelementptr [400 x i8]* @A, i32 0, i32 %p_vector_iv3
-  %p_arrayidx7 = getelementptr [400 x i8]* @A, i32 0, i32 %p_vector_iv415
+  %p_arrayidx = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %polly.loopiv16
+  %p_arrayidx5 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %p_vector_iv14
+  %p_arrayidx6 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %p_vector_iv3
+  %p_arrayidx7 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %p_vector_iv415
   store i8 123, i8* %p_arrayidx, align 1
   store i8 123, i8* %p_arrayidx5, align 1
   store i8 123, i8* %p_arrayidx6, align 1
diff --git a/test/CodeGen/Hexagon/hwloop-missed.ll b/test/CodeGen/Hexagon/hwloop-missed.ll
new file mode 100644
index 000000000000..bcc800652294
--- /dev/null
+++ b/test/CodeGen/Hexagon/hwloop-missed.ll
@@ -0,0 +1,49 @@
+; RUN: llc -march=hexagon -hexagon-hwloop-preheader < %s | FileCheck %s
+
+; Generate hardware loops when we also need to add a new preheader.
+; we should generate two hardware loops for this test case.
+
+; CHECK: loop0
+; CHECK: endloop0
+; CHECK: loop0
+; CHECK: endloop0
+
+@g = external global i32
+
+define void @test(i32* nocapture %a, i32* nocapture %b, i32 %n) nounwind {
+entry:
+  %tobool = icmp eq i32 %n, 0
+  br i1 %tobool, label %for.body4.preheader, label %for.body.preheader
+
+for.body.preheader:
+  br label %for.body
+
+for.body:
+  %arrayidx.phi = phi i32* [ %arrayidx.inc, %for.body ], [ %a, %for.body.preheader ]
+  %i.014 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
+  %0 = load i32, i32* @g, align 4
+  store i32 %0, i32* %arrayidx.phi, align 4
+  %inc = add nsw i32 %i.014, 1
+  %exitcond15 = icmp eq i32 %inc, 3
+  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
+  br i1 %exitcond15, label %for.body4.preheader.loopexit, label %for.body
+
+for.body4.preheader.loopexit:
+  br label %for.body4.preheader
+
+for.body4.preheader:
+  br label %for.body4
+
+for.body4:
+  %arrayidx5.phi = phi i32* [ %arrayidx5.inc, %for.body4 ], [ %b, %for.body4.preheader ]
+  %i1.013 = phi i32 [ %inc7, %for.body4 ], [ 0, %for.body4.preheader ]
+  %1 = load i32, i32* @g, align 4
+  store i32 %1, i32* %arrayidx5.phi, align 4
+  %inc7 = add nsw i32 %i1.013, 1
+  %exitcond = icmp eq i32 %inc7, 3
+  %arrayidx5.inc = getelementptr i32, i32* %arrayidx5.phi, i32 1
+  br i1 %exitcond, label %for.end8, label %for.body4
+
+for.end8:
+  ret void
+}
diff --git a/test/CodeGen/Hexagon/hwloop-ne.ll b/test/CodeGen/Hexagon/hwloop-ne.ll
index bceef2a16955..12ef3b5dd0bc 100644
--- a/test/CodeGen/Hexagon/hwloop-ne.ll
+++ b/test/CodeGen/Hexagon/hwloop-ne.ll
@@ -14,8 +14,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 32623, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -43,8 +43,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 29554, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -72,8 +72,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 15692, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -101,8 +101,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 10449, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -130,8 +130,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 32087, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -159,8 +159,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -188,8 +188,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -217,8 +217,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -246,8 +246,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -275,8 +275,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -304,8 +304,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -333,8 +333,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -362,8 +362,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -391,8 +391,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -420,8 +420,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
diff --git a/test/CodeGen/Hexagon/hwloop-ph-deadcode.ll b/test/CodeGen/Hexagon/hwloop-ph-deadcode.ll
new file mode 100644
index 000000000000..06e6db420f8f
--- /dev/null
+++ b/test/CodeGen/Hexagon/hwloop-ph-deadcode.ll
@@ -0,0 +1,23 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -O2 -disable-block-placement=0 < %s | FileCheck %s
+
+; Test that there is no redundant register assignment in the hardware loop
+; preheader.
+
+; CHECK-NOT: r{{.*}} = #5
+
+@g = external global i32
+
+define void @foo() #0 {
+entry:
+  br i1 undef, label %if.end38, label %for.body
+
+for.body:
+  %loopIdx.051 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
+  store i32 1, i32* @g, align 4
+  %inc = add i32 %loopIdx.051, 1
+  %cmp9 = icmp ult i32 %inc, 5
+  br i1 %cmp9, label %for.body, label %if.end38
+
+if.end38:
+  ret void
+}
diff --git a/test/CodeGen/Hexagon/hwloop-pos-ivbump1.ll b/test/CodeGen/Hexagon/hwloop-pos-ivbump1.ll
new file mode 100644
index 000000000000..7c5ea031ffae
--- /dev/null
+++ b/test/CodeGen/Hexagon/hwloop-pos-ivbump1.ll
@@ -0,0 +1,45 @@
+;RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Test that a hardware loop is not generaetd due to a potential
+; underflow.
+
+; CHECK-NOT: loop0
+
+define i32 @main() #0 {
+entry:
+  br label %while.cond.outer
+
+while.cond.outer.loopexit:
+  %.lcssa = phi i32 [ %0, %for.body.preheader ]
+  br label %while.cond.outer
+
+while.cond.outer:
+  %i.0.ph = phi i32 [ 0, %entry ], [ 3, %while.cond.outer.loopexit ]
+  %j.0.ph = phi i32 [ 0, %entry ], [ %.lcssa, %while.cond.outer.loopexit ]
+  %k.0.ph = phi i32 [ 0, %entry ], [ 1, %while.cond.outer.loopexit ]
+  br label %while.cond
+
+while.cond:
+  %i.0 = phi i32 [ %i.0.ph, %while.cond.outer ], [ %inc, %for.body.preheader ]
+  %j.0 = phi i32 [ %j.0.ph, %while.cond.outer ], [ %0, %for.body.preheader ]
+  %inc = add nsw i32 %i.0, 1
+  %cmp = icmp slt i32 %i.0, 4
+  br i1 %cmp, label %for.body.preheader, label %while.end
+
+for.body.preheader:
+  %0 = add i32 %j.0, 3
+  %cmp5 = icmp eq i32 %inc, 3
+  br i1 %cmp5, label %while.cond.outer.loopexit, label %while.cond
+
+while.end:
+  %k.0.ph.lcssa = phi i32 [ %k.0.ph, %while.cond ]
+  %inc.lcssa = phi i32 [ %inc, %while.cond ]
+  %j.0.lcssa = phi i32 [ %j.0, %while.cond ]
+  %cmp6 = icmp ne i32 %inc.lcssa, 5
+  %cmp7 = icmp ne i32 %j.0.lcssa, 12
+  %or.cond = or i1 %cmp6, %cmp7
+  %cmp9 = icmp ne i32 %k.0.ph.lcssa, 1
+  %or.cond12 = or i1 %or.cond, %cmp9
+  %locflg.0 = zext i1 %or.cond12 to i32
+  ret i32 %locflg.0
+}
diff --git a/test/CodeGen/Hexagon/hwloop-preheader.ll b/test/CodeGen/Hexagon/hwloop-preheader.ll
new file mode 100644
index 000000000000..66efd2089fce
--- /dev/null
+++ b/test/CodeGen/Hexagon/hwloop-preheader.ll
@@ -0,0 +1,40 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-hwloop-preheader < %s
+; REQUIRES: asserts
+
+; Test that the preheader is added to the parent loop, otherwise
+; we generate an invalid hardware loop.
+
+; Function Attrs: nounwind readonly
+define void @test(i16 signext %n) #0 {
+entry:
+  br i1 undef, label %for.cond4.preheader.preheader.split.us, label %for.end22
+
+for.cond4.preheader.preheader.split.us:
+  %0 = sext i16 %n to i32
+  br label %for.body9.preheader.us
+
+for.body9.us:
+  %indvars.iv = phi i32 [ %indvars.iv.next.7, %for.body9.us ], [ 0, %for.body9.preheader.us ]
+  %indvars.iv.next.7 = add i32 %indvars.iv, 8
+  %lftr.wideiv.7 = trunc i32 %indvars.iv.next.7 to i16
+  %exitcond.7 = icmp slt i16 %lftr.wideiv.7, 0
+  br i1 %exitcond.7, label %for.body9.us, label %for.body9.us.ur
+
+for.body9.preheader.us:
+  %i.030.us.pmt = phi i32 [ %inc21.us.pmt, %for.end.loopexit.us ], [ 0, %for.cond4.preheader.preheader.split.us ]
+  br i1 undef, label %for.body9.us, label %for.body9.us.ur
+
+for.body9.us.ur:
+  %exitcond.ur.old = icmp eq i16 undef, %n
+  br i1 %exitcond.ur.old, label %for.end.loopexit.us, label %for.body9.us.ur
+
+for.end.loopexit.us:
+  %inc21.us.pmt = add i32 %i.030.us.pmt, 1
+  %exitcond33 = icmp eq i32 %inc21.us.pmt, %0
+  br i1 %exitcond33, label %for.end22, label %for.body9.preheader.us
+
+for.end22:
+  ret void
+}
+
+attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/CodeGen/Hexagon/hwloop-range.ll b/test/CodeGen/Hexagon/hwloop-range.ll
new file mode 100644
index 000000000000..5e6fe78d0e0b
--- /dev/null
+++ b/test/CodeGen/Hexagon/hwloop-range.ll
@@ -0,0 +1,36 @@
+; RUN: llc -march=hexagon -hexagon-loop-range=0 < %s | FileCheck %s
+
+; Test that the loop start address operand uses a constant extender
+; if the offset is out of range.
+
+; CHECK: loop0(##.LBB
+; CHECK: endloop0
+
+@g = external global i32, align 4
+
+define void @test(i32* nocapture %a, i32* nocapture readonly %b, i32 %n) #0 {
+entry:
+  %cmp6 = icmp slt i32 %n, 1
+  br i1 %cmp6, label %for.end, label %for.body.preheader
+
+for.body.preheader:
+  br label %for.body
+
+for.body:
+  %i.07 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
+  %arrayidx = getelementptr inbounds i32, i32* %b, i32 %i.07
+  %0 = load i32, i32* %arrayidx, align 4
+  %1 = load i32, i32* @g, align 4
+  %mul = mul nsw i32 %1, %0
+  %arrayidx1 = getelementptr inbounds i32, i32* %a, i32 %i.07
+  store i32 %mul, i32* %arrayidx1, align 4
+  %inc = add nuw nsw i32 %i.07, 1
+  %exitcond = icmp eq i32 %inc, %n
+  br i1 %exitcond, label %for.end.loopexit, label %for.body
+
+for.end.loopexit:
+  br label %for.end
+
+for.end:
+  ret void
+}
diff --git a/test/CodeGen/Hexagon/hwloop-recursion.ll b/test/CodeGen/Hexagon/hwloop-recursion.ll
new file mode 100644
index 000000000000..8ab2dc37d021
--- /dev/null
+++ b/test/CodeGen/Hexagon/hwloop-recursion.ll
@@ -0,0 +1,64 @@
+; RUN: llc -O2 -march=hexagon -mcpu=hexagonv5 < %s
+; REQUIRES: asserts
+; Check for successful compilation.
+
+@c = common global i32 0, align 4
+@e = common global i32 0, align 4
+@g = common global i32* null, align 4
+@a = common global i32 0, align 4
+@b = common global i32 0, align 4
+@h = common global i32* null, align 4
+@d = common global i32 0, align 4
+@f = common global i32 0, align 4
+
+define i32 @fn1([0 x i32]* nocapture readnone %p1) #0 {
+entry:
+  %0 = load i32*, i32** @h, align 4
+  %1 = load i32*, i32** @g, align 4
+  %.pre = load i32, i32* @c, align 4
+  br label %for.cond
+
+for.cond:
+  %2 = phi i32 [ %10, %if.end ], [ %.pre, %entry ]
+  store i32 %2, i32* @e, align 4
+  %tobool5 = icmp eq i32 %2, 0
+  br i1 %tobool5, label %for.end, label %for.body.lr.ph
+
+for.body.lr.ph:
+  %3 = sub i32 -5, %2
+  %4 = urem i32 %3, 5
+  %5 = sub i32 %3, %4
+  br label %for.body
+
+for.body:
+  %add6 = phi i32 [ %2, %for.body.lr.ph ], [ %add, %for.body ]
+  %6 = load i32, i32* %1, align 4
+  store i32 %6, i32* @a, align 4
+  %add = add nsw i32 %add6, 5
+  %tobool = icmp eq i32 %add, 0
+  br i1 %tobool, label %for.cond1.for.end_crit_edge, label %for.body
+
+for.cond1.for.end_crit_edge:
+  %7 = add i32 %2, 5
+  %8 = add i32 %7, %5
+  store i32 %8, i32* @e, align 4
+  br label %for.end
+
+for.end:
+  %9 = load i32, i32* @b, align 4
+  %tobool2 = icmp eq i32 %9, 0
+  br i1 %tobool2, label %if.end, label %if.then
+
+if.then:
+  store i32 0, i32* %0, align 4
+  %.pre7 = load i32, i32* @c, align 4
+  br label %if.end
+
+if.end:
+  %10 = phi i32 [ %2, %for.end ], [ %.pre7, %if.then ]
+  store i32 %10, i32* @d, align 4
+  %11 = load i32, i32* @f, align 4
+  %inc = add nsw i32 %11, 1
+  store i32 %inc, i32* @f, align 4
+  br label %for.cond
+}
diff --git a/test/CodeGen/Hexagon/hwloop-wrap.ll b/test/CodeGen/Hexagon/hwloop-wrap.ll
new file mode 100644
index 000000000000..e0f6a87fd2e4
--- /dev/null
+++ b/test/CodeGen/Hexagon/hwloop-wrap.ll
@@ -0,0 +1,22 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+
+; We shouldn't generate a hardware loop in this case because the initial
+; value may be zero, which means the endloop instruction will not decrement
+; the loop counter, and the loop will execute only once.
+
+; CHECK-NOT: loop0
+
+define void @foo(i32 %count, i32 %v) #0 {
+entry:
+  br label %do.body
+
+do.body:
+  %count.addr.0 = phi i32 [ %count, %entry ], [ %dec, %do.body ]
+  tail call void asm sideeffect "nop", ""() #1
+  %dec = add i32 %count.addr.0, -1
+  %cmp = icmp eq i32 %dec, 0
+  br i1 %cmp, label %do.end, label %do.body
+
+do.end:
+  ret void
+}
diff --git a/test/CodeGen/Hexagon/hwloop-wrap2.ll b/test/CodeGen/Hexagon/hwloop-wrap2.ll
new file mode 100644
index 000000000000..50675d6b681b
--- /dev/null
+++ b/test/CodeGen/Hexagon/hwloop-wrap2.ll
@@ -0,0 +1,67 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s
+
+; Test that we do not generate a hardware loop due to a potential underflow.
+
+; CHECK-NOT: loop0
+
+%struct.3 = type { i8*, i8, i8, i32, i32, i16, i16, i16, i16, i16, i16, i16, %struct.2* }
+%struct.2 = type { i16, i16, i16, i16, %struct.1* }
+%struct.1 = type { %struct.1*, %struct.0*, i32, i32, i16, [2 x i16], [2 x i16], i16 }
+%struct.0 = type { %struct.0*, i32, i32, i32, i32, i32, i32, i16, i16, i16, i8, i8, i8, i8 }
+
+@pairArray = external global i32**
+@carray = external global %struct.3**
+
+define void @test() #0 {
+entry:
+  %0 = load i32**, i32*** @pairArray, align 4
+  %1 = load %struct.3**, %struct.3*** @carray, align 4
+  br i1 undef, label %for.end110, label %for.body
+
+for.body:
+  %row.0199 = phi i32 [ %inc109, %for.inc108 ], [ 1, %entry ]
+  %arrayidx = getelementptr inbounds i32*, i32** %0, i32 %row.0199
+  %2 = load i32*, i32** %arrayidx, align 4
+  br i1 undef, label %for.body48, label %for.inc108
+
+for.cond45:
+  %cmp46 = icmp sgt i32 %dec58, 0
+  br i1 %cmp46, label %for.body48, label %for.inc108
+
+for.body48:
+  %i.1190 = phi i32 [ %dec58, %for.cond45 ], [ 0, %for.body ]
+  %arrayidx50 = getelementptr inbounds i32, i32* %2, i32 %i.1190
+  %3 = load i32, i32* %arrayidx50, align 4
+  %cmp53 = icmp slt i32 %3, 0
+  %dec58 = add nsw i32 %i.1190, -1
+  br i1 %cmp53, label %for.end59, label %for.cond45
+
+for.end59:
+  %cmp60 = icmp slt i32 %i.1190, 0
+  br i1 %cmp60, label %if.then65, label %for.inc108
+
+if.then65:
+  br label %for.body80
+
+for.body80:
+  %j.1196.in = phi i32 [ %j.1196, %for.body80 ], [ %i.1190, %if.then65 ]
+  %j.1196 = add nsw i32 %j.1196.in, 1
+  %arrayidx81 = getelementptr inbounds i32, i32* %2, i32 %j.1196
+  %4 = load i32, i32* %arrayidx81, align 4
+  %arrayidx82 = getelementptr inbounds %struct.3*, %struct.3** %1, i32 %4
+  %5 = load %struct.3*, %struct.3** %arrayidx82, align 4
+  %cxcenter83 = getelementptr inbounds %struct.3, %struct.3* %5, i32 0, i32 3
+  store i32 0, i32* %cxcenter83, align 4
+  %6 = load i32, i32* %arrayidx81, align 4
+  %arrayidx87 = getelementptr inbounds i32, i32* %2, i32 %j.1196.in
+  store i32 %6, i32* %arrayidx87, align 4
+  %exitcond = icmp eq i32 %j.1196, 0
+  br i1 %exitcond, label %for.inc108, label %for.body80
+
+for.inc108:
+  %inc109 = add nsw i32 %row.0199, 1
+  br i1 undef, label %for.body, label %for.end110
+
+for.end110:
+  ret void
+}
diff --git a/test/CodeGen/Hexagon/hwloop1.ll b/test/CodeGen/Hexagon/hwloop1.ll
new file mode 100644
index 000000000000..97b779cf9628
--- /dev/null
+++ b/test/CodeGen/Hexagon/hwloop1.ll
@@ -0,0 +1,161 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; Check that we generate hardware loop instructions.
+
+; Case 1 : Loop with a constant number of iterations.
+; CHECK-LABEL: @hwloop1
+; CHECK: loop0(.LBB{{.}}_{{.}}, #10)
+; CHECK: endloop0
+
+@a = common global [10 x i32] zeroinitializer, align 4
+define i32 @hwloop1() nounwind {
+entry:
+  br label %for.body
+for.body:
+  %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* @a, i32 0, i32 %i.01
+  store i32 %i.01, i32* %arrayidx, align 4
+  %inc = add nsw i32 %i.01, 1
+  %exitcond = icmp eq i32 %inc, 10
+  br i1 %exitcond, label %for.end, label %for.body
+for.end:
+  ret i32 0
+}
+
+; Case 2 : Loop with a run-time number of iterations.
+; CHECK-LABEL: @hwloop2
+; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}})
+; CHECK: endloop0
+
+define i32 @hwloop2(i32 %n, i32* nocapture %b) nounwind {
+entry:
+  %cmp1 = icmp sgt i32 %n, 0
+  br i1 %cmp1, label %for.body.preheader, label %for.end
+
+for.body.preheader:
+  br label %for.body
+
+for.body:
+  %a.03 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
+  %i.02 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
+  %arrayidx = getelementptr inbounds i32, i32* %b, i32 %i.02
+  %0 = load i32, i32* %arrayidx, align 4
+  %add = add nsw i32 %0, %a.03
+  %inc = add nsw i32 %i.02, 1
+  %exitcond = icmp eq i32 %inc, %n
+  br i1 %exitcond, label %for.end.loopexit, label %for.body
+
+for.end.loopexit:
+  br label %for.end
+
+for.end:
+  %a.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.end.loopexit ]
+  ret i32 %a.0.lcssa
+}
+
+; Case 3 : Induction variable increment more than 1.
+; CHECK-LABEL: @hwloop3
+; CHECK: lsr(r{{[0-9]+}}, #2)
+; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}})
+; CHECK: endloop0
+
+define i32 @hwloop3(i32 %n, i32* nocapture %b) nounwind {
+entry:
+  %cmp1 = icmp sgt i32 %n, 0
+  br i1 %cmp1, label %for.body.preheader, label %for.end
+
+for.body.preheader:
+  br label %for.body
+
+for.body:
+  %a.03 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
+  %i.02 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
+  %arrayidx = getelementptr inbounds i32, i32* %b, i32 %i.02
+  %0 = load i32, i32* %arrayidx, align 4
+  %add = add nsw i32 %0, %a.03
+  %inc = add nsw i32 %i.02, 4
+  %exitcond = icmp eq i32 %inc, %n
+  br i1 %exitcond, label %for.end.loopexit, label %for.body
+
+for.end.loopexit:
+  br label %for.end
+
+for.end:
+  %a.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.end.loopexit ]
+  ret i32 %a.0.lcssa
+}
+
+; Case 4 : Loop exit compare uses register instead of immediate value.
+; CHECK-LABEL: @hwloop4
+; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}})
+; CHECK: endloop0
+
+define i32 @hwloop4(i32 %n, i32* nocapture %b) nounwind {
+entry:
+  %cmp1 = icmp sgt i32 %n, 0
+  br i1 %cmp1, label %for.body.preheader, label %for.end
+
+for.body.preheader:
+  br label %for.body
+
+for.body:
+  %i.02 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
+  %arrayidx = getelementptr inbounds i32, i32* %b, i32 %i.02
+  store i32 %i.02, i32* %arrayidx, align 4
+  %inc = add nsw i32 %i.02, 1
+  %exitcond = icmp eq i32 %inc, %n
+  br i1 %exitcond, label %for.end.loopexit, label %for.body
+
+for.end.loopexit:
+  br label %for.end
+
+for.end:
+  ret i32 0
+}
+
+; Case 5: After LSR, the initial value is 100 and the iv decrements to 0.
+; CHECK-LABEL: @hwloop5
+; CHECK: loop0(.LBB{{.}}_{{.}}, #100)
+; CHECK: endloop0
+
+define void @hwloop5(i32* nocapture %a, i32* nocapture %res) nounwind {
+entry:
+  br label %for.body
+
+for.body:
+  %i.03 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %i.03
+  %0 = load i32, i32* %arrayidx, align 4
+  %mul = mul nsw i32 %0, %0
+  %arrayidx2 = getelementptr inbounds i32, i32* %res, i32 %i.03
+  store i32 %mul, i32* %arrayidx2, align 4
+  %inc = add nsw i32 %i.03, 1
+  %exitcond = icmp eq i32 %inc, 100
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
+; Case 6: Large immediate offset
+; CHECK-LABEL: @hwloop6
+; CHECK-NOT: loop0(.LBB{{.}}_{{.}}, #1024)
+; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}})
+; CHECK: endloop0
+
+define void @hwloop6(i32* nocapture %a, i32* nocapture %res) nounwind {
+entry:
+  br label %for.body
+
+for.body:
+  %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %i.02
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %res, i32 %i.02
+  store i32 %0, i32* %arrayidx1, align 4
+  %inc = add nsw i32 %i.02, 1
+  %exitcond = icmp eq i32 %inc, 1024
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
diff --git a/test/CodeGen/Hexagon/hwloop2.ll b/test/CodeGen/Hexagon/hwloop2.ll
new file mode 100644
index 000000000000..d411d979904e
--- /dev/null
+++ b/test/CodeGen/Hexagon/hwloop2.ll
@@ -0,0 +1,37 @@
+; RUN: llc -disable-lsr -march=hexagon < %s | FileCheck %s
+
+; Test for multiple phis with induction variables.
+
+; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}})
+; CHECK: endloop0
+
+define i32 @hwloop4(i32* nocapture %s, i32* nocapture %a, i32 %n) {
+entry:
+  %cmp3 = icmp eq i32 %n, 0
+  br i1 %cmp3, label %for.end, label %for.body.lr.ph
+
+for.body.lr.ph:
+  %.pre = load i32, i32* %s, align 4
+  br label %for.body
+
+for.body:
+  %0 = phi i32 [ %.pre, %for.body.lr.ph ], [ %add1, %for.body ]
+  %j.05 = phi i32 [ 0, %for.body.lr.ph ], [ %add2, %for.body ]
+  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ %n, %for.body.lr.ph ]
+  %lsr.iv1 = phi i32* [ %scevgep, %for.body ], [ %a, %for.body.lr.ph ]
+  %1 = load i32, i32* %lsr.iv1, align 4
+  %add1 = add nsw i32 %0, %1
+  store i32 %add1, i32* %s, align 4
+  %add2 = add nsw i32 %j.05, 1
+  %lsr.iv.next = add i32 %lsr.iv, -1
+  %scevgep = getelementptr i32, i32* %lsr.iv1, i32 1
+  %cmp = icmp eq i32 %lsr.iv.next, 0
+  br i1 %cmp, label %for.end.loopexit, label %for.body
+
+for.end.loopexit:
+  br label %for.end
+
+for.end:
+  %j.0.lcssa = phi i32 [ 0, %entry ], [ %add2, %for.end.loopexit ]
+  ret i32 %j.0.lcssa
+}
diff --git a/test/CodeGen/Hexagon/hwloop3.ll b/test/CodeGen/Hexagon/hwloop3.ll
new file mode 100644
index 000000000000..1135e06a0c43
--- /dev/null
+++ b/test/CodeGen/Hexagon/hwloop3.ll
@@ -0,0 +1,27 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+;
+; Remove the unconditional jump to following instruction.
+
+; CHECK: endloop0
+; CHECK-NOT: jump [[L1:.]]
+; CHECK-NOT: [[L1]]
+
+define void @test(i32* nocapture %a, i32 %n) nounwind {
+entry:
+  br label %for.body
+
+for.body:
+  %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ]
+  %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %0 = load i32, i32* %arrayidx.phi, align 4
+  %add = add nsw i32 %0, 1
+  store i32 %add, i32* %arrayidx.phi, align 4
+  %inc = add nsw i32 %i.02, 1
+  %exitcond = icmp eq i32 %inc, 100
+  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
diff --git a/test/CodeGen/Hexagon/hwloop4.ll b/test/CodeGen/Hexagon/hwloop4.ll
new file mode 100644
index 000000000000..d159c45e3fb8
--- /dev/null
+++ b/test/CodeGen/Hexagon/hwloop4.ll
@@ -0,0 +1,76 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+;
+; Remove the unnecessary 'add' instruction used for the hardware loop setup.
+
+; CHECK: [[OP0:r[0-9]+]] = add([[OP1:r[0-9]+]], #-[[OP2:[0-9]+]]
+; CHECK-NOT: add([[OP0]], #[[OP2]])
+; CHECK: lsr([[OP1]], #{{[0-9]+}})
+; CHECK: loop0
+
+define void @matrix_mul_matrix(i32 %N, i32* nocapture %C, i16* nocapture readnone %A, i16* nocapture readnone %B) #0 {
+entry:
+  %cmp4 = icmp eq i32 %N, 0
+  br i1 %cmp4, label %for.end, label %for.body.preheader
+
+for.body.preheader:
+  %maxval = add i32 %N, -7
+  %0 = icmp sgt i32 %maxval, 0
+  br i1 %0, label %for.body.preheader9, label %for.body.ur.preheader
+
+for.body.preheader9:
+  br label %for.body
+
+for.body:
+  %arrayidx.phi = phi i32* [ %arrayidx.inc.7, %for.body ], [ %C, %for.body.preheader9 ]
+  %i.05 = phi i32 [ %inc.7, %for.body ], [ 0, %for.body.preheader9 ]
+  store i32 %i.05, i32* %arrayidx.phi, align 4
+  %inc = add i32 %i.05, 1
+  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
+  store i32 %inc, i32* %arrayidx.inc, align 4
+  %inc.1 = add i32 %i.05, 2
+  %arrayidx.inc.1 = getelementptr i32, i32* %arrayidx.phi, i32 2
+  store i32 %inc.1, i32* %arrayidx.inc.1, align 4
+  %inc.2 = add i32 %i.05, 3
+  %arrayidx.inc.2 = getelementptr i32, i32* %arrayidx.phi, i32 3
+  store i32 %inc.2, i32* %arrayidx.inc.2, align 4
+  %inc.3 = add i32 %i.05, 4
+  %arrayidx.inc.3 = getelementptr i32, i32* %arrayidx.phi, i32 4
+  store i32 %inc.3, i32* %arrayidx.inc.3, align 4
+  %inc.4 = add i32 %i.05, 5
+  %arrayidx.inc.4 = getelementptr i32, i32* %arrayidx.phi, i32 5
+  store i32 %inc.4, i32* %arrayidx.inc.4, align 4
+  %inc.5 = add i32 %i.05, 6
+  %arrayidx.inc.5 = getelementptr i32, i32* %arrayidx.phi, i32 6
+  store i32 %inc.5, i32* %arrayidx.inc.5, align 4
+  %inc.6 = add i32 %i.05, 7
+  %arrayidx.inc.6 = getelementptr i32, i32* %arrayidx.phi, i32 7
+  store i32 %inc.6, i32* %arrayidx.inc.6, align 4
+  %inc.7 = add i32 %i.05, 8
+  %exitcond.7 = icmp slt i32 %inc.7, %maxval
+  %arrayidx.inc.7 = getelementptr i32, i32* %arrayidx.phi, i32 8
+  br i1 %exitcond.7, label %for.body, label %for.end.loopexit.ur-lcssa
+
+for.end.loopexit.ur-lcssa:
+  %1 = icmp eq i32 %inc.7, %N
+  br i1 %1, label %for.end, label %for.body.ur.preheader
+
+for.body.ur.preheader:
+  %arrayidx.phi.ur.ph = phi i32* [ %C, %for.body.preheader ], [ %arrayidx.inc.7, %for.end.loopexit.ur-lcssa ]
+  %i.05.ur.ph = phi i32 [ 0, %for.body.preheader ], [ %inc.7, %for.end.loopexit.ur-lcssa ]
+  br label %for.body.ur
+
+for.body.ur:
+  %arrayidx.phi.ur = phi i32* [ %arrayidx.inc.ur, %for.body.ur ], [ %arrayidx.phi.ur.ph, %for.body.ur.preheader ]
+  %i.05.ur = phi i32 [ %inc.ur, %for.body.ur ], [ %i.05.ur.ph, %for.body.ur.preheader ]
+  store i32 %i.05.ur, i32* %arrayidx.phi.ur, align 4
+  %inc.ur = add i32 %i.05.ur, 1
+  %exitcond.ur = icmp eq i32 %inc.ur, %N
+  %arrayidx.inc.ur = getelementptr i32, i32* %arrayidx.phi.ur, i32 1
+  br i1 %exitcond.ur, label %for.end.loopexit, label %for.body.ur
+
+for.end.loopexit:
+  br label %for.end
+
+for.end:
+  ret void
+}
diff --git a/test/CodeGen/Hexagon/hwloop5.ll b/test/CodeGen/Hexagon/hwloop5.ll
new file mode 100644
index 000000000000..0886b03cc754
--- /dev/null
+++ b/test/CodeGen/Hexagon/hwloop5.ll
@@ -0,0 +1,93 @@
+; RUN: llc -O3 -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+;
+; Generate hardware loop when unknown trip count loop is vectorized.
+
+; CHECK: loop0(.LBB{{[0-9]*}}_{{[0-9]*}}, r{{[0-9]+}})
+; CHECK: endloop0
+; CHECK: loop0(.LBB{{[0-9]*}}_{{[0-9]*}}, r{{[0-9]+}})
+; CHECK: endloop0
+
+@A = common global [1000 x i32] zeroinitializer, align 8
+@B = common global [1000 x i32] zeroinitializer, align 8
+
+define i32 @dotprod2(i32 %count) #0 {
+entry.split:
+  %cmp6 = icmp sgt i32 %count, 0
+  br i1 %cmp6, label %polly.cond, label %for.end
+
+for.end.loopexit:
+  br label %for.end
+
+for.end:
+  %sum.0.lcssa.reg2mem.0.load37 = phi i32 [ 0, %entry.split ], [ %p_add34, %polly.loop_if13 ], [ %p_add, %for.end.loopexit ]
+  ret i32 %sum.0.lcssa.reg2mem.0.load37
+
+polly.cond:
+  %0 = icmp sgt i32 %count, 1
+  br i1 %0, label %polly.loop_if, label %polly.loop_if13
+
+polly.loop_exit.loopexit:
+  br label %polly.loop_exit
+
+polly.loop_exit:
+  %1 = phi <2 x i32> [ zeroinitializer, %polly.loop_if ], [ %addp_vec, %polly.loop_exit.loopexit ]
+  %2 = extractelement <2 x i32> %1, i32 0
+  %3 = extractelement <2 x i32> %1, i32 1
+  %add_sum = add i32 %2, %3
+  br label %polly.loop_if13
+
+polly.loop_if:
+  %4 = add i32 %count, -1
+  %leftover_lb = and i32 %4, -2
+  %polly.loop_guard = icmp eq i32 %leftover_lb, 0
+  br i1 %polly.loop_guard, label %polly.loop_exit, label %polly.loop_preheader
+
+polly.stmt.for.body:
+  %addp_vec28 = phi <2 x i32> [ zeroinitializer, %polly.loop_preheader ], [ %addp_vec, %polly.stmt.for.body ]
+  %scevgep.phi = phi i32* [ getelementptr inbounds ([1000 x i32], [1000 x i32]* @A, i32 0, i32 0), %polly.loop_preheader ], [ %scevgep.inc, %polly.stmt.for.body ]
+  %scevgep9.phi = phi i32* [ getelementptr inbounds ([1000 x i32], [1000 x i32]* @B, i32 0, i32 0), %polly.loop_preheader ], [ %scevgep9.inc, %polly.stmt.for.body ]
+  %polly.indvar = phi i32 [ 0, %polly.loop_preheader ], [ %polly.indvar_next, %polly.stmt.for.body ]
+  %vector_ptr = bitcast i32* %scevgep.phi to <2 x i32>*
+  %_p_vec_full = load <2 x i32>, <2 x i32>* %vector_ptr, align 8
+  %vector_ptr10 = bitcast i32* %scevgep9.phi to <2 x i32>*
+  %_p_vec_full11 = load <2 x i32>, <2 x i32>* %vector_ptr10, align 8
+  %mulp_vec = mul <2 x i32> %_p_vec_full11, %_p_vec_full
+  %addp_vec = add <2 x i32> %mulp_vec, %addp_vec28
+  %polly.indvar_next = add nsw i32 %polly.indvar, 2
+  %polly.loop_cond = icmp eq i32 %polly.indvar, %polly.adjust_ub
+  %scevgep.inc = getelementptr i32, i32* %scevgep.phi, i32 2
+  %scevgep9.inc = getelementptr i32, i32* %scevgep9.phi, i32 2
+  br i1 %polly.loop_cond, label %polly.loop_exit.loopexit, label %polly.stmt.for.body
+
+polly.loop_preheader:
+  %polly.adjust_ub = add i32 %leftover_lb, -2
+  br label %polly.stmt.for.body
+
+polly.loop_if13:
+  %p_add34 = phi i32 [ 0, %polly.cond ], [ %add_sum, %polly.loop_exit ]
+  %merge.lb = phi i32 [ 0, %polly.cond ], [ %leftover_lb, %polly.loop_exit ]
+  %polly.loop_guard17 = icmp slt i32 %merge.lb, %count
+  br i1 %polly.loop_guard17, label %polly.loop_preheader15, label %for.end
+
+polly.stmt.for.body22:
+  %p_add30 = phi i32 [ %p_add34, %polly.loop_preheader15 ], [ %p_add, %polly.stmt.for.body22 ]
+  %polly.indvar18 = phi i32 [ %merge.lb, %polly.loop_preheader15 ], [ %polly.indvar_next19, %polly.stmt.for.body22 ]
+  %5 = tail call i32 @llvm.annotation.i32(i32 %polly.indvar18, i8* null, i8* null, i32 0), !polly.loop.smallTripCount !0
+  %scevgep23 = getelementptr [1000 x i32], [1000 x i32]* @A, i32 0, i32 %polly.indvar18
+  %_p_scalar_ = load i32, i32* %scevgep23, align 4
+  %scevgep24 = getelementptr [1000 x i32], [1000 x i32]* @B, i32 0, i32 %polly.indvar18
+  %_p_scalar_25 = load i32, i32* %scevgep24, align 4
+  %p_mul = mul nsw i32 %_p_scalar_25, %_p_scalar_
+  %p_add = add nsw i32 %p_mul, %p_add30
+  %polly.indvar_next19 = add nsw i32 %polly.indvar18, 1
+  %polly.loop_cond21 = icmp slt i32 %polly.indvar18, %polly.adjust_ub20
+  br i1 %polly.loop_cond21, label %polly.stmt.for.body22, label %for.end.loopexit
+
+polly.loop_preheader15:
+  %polly.adjust_ub20 = add i32 %count, -1
+  br label %polly.stmt.for.body22
+}
+
+declare i32 @llvm.annotation.i32(i32, i8*, i8*, i32) #1
+
+!0 = !{}
diff --git a/test/CodeGen/Hexagon/i16_VarArg.ll b/test/CodeGen/Hexagon/i16_VarArg.ll
index c5d05a5e6ed8..ba98f6226683 100644
--- a/test/CodeGen/Hexagon/i16_VarArg.ll
+++ b/test/CodeGen/Hexagon/i16_VarArg.ll
@@ -20,8 +20,8 @@
 declare i32 @printf(i8*, ...)
 
 define i32 @main() {
-        %a = load double* @A
-        %b = load double* @B
+        %a = load double, double* @A
+        %b = load double, double* @B
         %lt_r = fcmp olt double %a, %b
         %le_r = fcmp ole double %a, %b
         %gt_r = fcmp ogt double %a, %b
@@ -29,12 +29,12 @@ define i32 @main() {
         %eq_r = fcmp oeq double %a, %b
         %ne_r = fcmp une double %a, %b
         %val1 = zext i1 %lt_r to i16
-        %lt_s = getelementptr [12 x i8]* @lt_str, i64 0, i64 0
-        %le_s = getelementptr [13 x i8]* @le_str, i64 0, i64 0
-        %gt_s = getelementptr [12 x i8]* @gt_str, i64 0, i64 0
-        %ge_s = getelementptr [13 x i8]* @ge_str, i64 0, i64 0
-        %eq_s = getelementptr [13 x i8]* @eq_str, i64 0, i64 0
-        %ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0
-        call i32 (i8*, ...)* @printf( i8* %lt_s, i16 %val1 )
+        %lt_s = getelementptr [12 x i8], [12 x i8]* @lt_str, i64 0, i64 0
+        %le_s = getelementptr [13 x i8], [13 x i8]* @le_str, i64 0, i64 0
+        %gt_s = getelementptr [12 x i8], [12 x i8]* @gt_str, i64 0, i64 0
+        %ge_s = getelementptr [13 x i8], [13 x i8]* @ge_str, i64 0, i64 0
+        %eq_s = getelementptr [13 x i8], [13 x i8]* @eq_str, i64 0, i64 0
+        %ne_s = getelementptr [13 x i8], [13 x i8]* @ne_str, i64 0, i64 0
+        call i32 (i8*, ...) @printf( i8* %lt_s, i16 %val1 )
         ret i32 0
 }
diff --git a/test/CodeGen/Hexagon/i1_VarArg.ll b/test/CodeGen/Hexagon/i1_VarArg.ll
index 37f27787c186..1908b3c71f3f 100644
--- a/test/CodeGen/Hexagon/i1_VarArg.ll
+++ b/test/CodeGen/Hexagon/i1_VarArg.ll
@@ -20,25 +20,25 @@
 declare i32 @printf(i8*, ...)
 
 define i32 @main() {
-        %a = load double* @A
-        %b = load double* @B
+        %a = load double, double* @A
+        %b = load double, double* @B
         %lt_r = fcmp olt double %a, %b
         %le_r = fcmp ole double %a, %b
         %gt_r = fcmp ogt double %a, %b
         %ge_r = fcmp oge double %a, %b
         %eq_r = fcmp oeq double %a, %b
         %ne_r = fcmp une double %a, %b
-        %lt_s = getelementptr [12 x i8]* @lt_str, i64 0, i64 0
-        %le_s = getelementptr [13 x i8]* @le_str, i64 0, i64 0
-        %gt_s = getelementptr [12 x i8]* @gt_str, i64 0, i64 0
-        %ge_s = getelementptr [13 x i8]* @ge_str, i64 0, i64 0
-        %eq_s = getelementptr [13 x i8]* @eq_str, i64 0, i64 0
-        %ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0
-        call i32 (i8*, ...)* @printf( i8* %lt_s, i1 %lt_r )
-        call i32 (i8*, ...)* @printf( i8* %le_s, i1 %le_r )
-        call i32 (i8*, ...)* @printf( i8* %gt_s, i1 %gt_r )
-        call i32 (i8*, ...)* @printf( i8* %ge_s, i1 %ge_r )
-        call i32 (i8*, ...)* @printf( i8* %eq_s, i1 %eq_r )
-        call i32 (i8*, ...)* @printf( i8* %ne_s, i1 %ne_r )
+        %lt_s = getelementptr [12 x i8], [12 x i8]* @lt_str, i64 0, i64 0
+        %le_s = getelementptr [13 x i8], [13 x i8]* @le_str, i64 0, i64 0
+        %gt_s = getelementptr [12 x i8], [12 x i8]* @gt_str, i64 0, i64 0
+        %ge_s = getelementptr [13 x i8], [13 x i8]* @ge_str, i64 0, i64 0
+        %eq_s = getelementptr [13 x i8], [13 x i8]* @eq_str, i64 0, i64 0
+        %ne_s = getelementptr [13 x i8], [13 x i8]* @ne_str, i64 0, i64 0
+        call i32 (i8*, ...) @printf( i8* %lt_s, i1 %lt_r )
+        call i32 (i8*, ...) @printf( i8* %le_s, i1 %le_r )
+        call i32 (i8*, ...) @printf( i8* %gt_s, i1 %gt_r )
+        call i32 (i8*, ...) @printf( i8* %ge_s, i1 %ge_r )
+        call i32 (i8*, ...) @printf( i8* %eq_s, i1 %eq_r )
+        call i32 (i8*, ...) @printf( i8* %ne_s, i1 %ne_r )
         ret i32 0
 }
diff --git a/test/CodeGen/Hexagon/i8_VarArg.ll b/test/CodeGen/Hexagon/i8_VarArg.ll
index 6f056ff417af..c40a6a957270 100644
--- a/test/CodeGen/Hexagon/i8_VarArg.ll
+++ b/test/CodeGen/Hexagon/i8_VarArg.ll
@@ -20,8 +20,8 @@
 declare i32 @printf(i8*, ...)
 
 define i32 @main() {
-        %a = load double* @A
-        %b = load double* @B
+        %a = load double, double* @A
+        %b = load double, double* @B
         %lt_r = fcmp olt double %a, %b
         %le_r = fcmp ole double %a, %b
         %gt_r = fcmp ogt double %a, %b
@@ -29,12 +29,12 @@ define i32 @main() {
         %eq_r = fcmp oeq double %a, %b
         %ne_r = fcmp une double %a, %b
         %val1 = zext i1 %lt_r to i8
-        %lt_s = getelementptr [12 x i8]* @lt_str, i64 0, i64 0
-        %le_s = getelementptr [13 x i8]* @le_str, i64 0, i64 0
-        %gt_s = getelementptr [12 x i8]* @gt_str, i64 0, i64 0
-        %ge_s = getelementptr [13 x i8]* @ge_str, i64 0, i64 0
-        %eq_s = getelementptr [13 x i8]* @eq_str, i64 0, i64 0
-        %ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0
-        call i32 (i8*, ...)* @printf( i8* %lt_s, i8 %val1 )
+        %lt_s = getelementptr [12 x i8], [12 x i8]* @lt_str, i64 0, i64 0
+        %le_s = getelementptr [13 x i8], [13 x i8]* @le_str, i64 0, i64 0
+        %gt_s = getelementptr [12 x i8], [12 x i8]* @gt_str, i64 0, i64 0
+        %ge_s = getelementptr [13 x i8], [13 x i8]* @ge_str, i64 0, i64 0
+        %eq_s = getelementptr [13 x i8], [13 x i8]* @eq_str, i64 0, i64 0
+        %ne_s = getelementptr [13 x i8], [13 x i8]* @ne_str, i64 0, i64 0
+        call i32 (i8*, ...) @printf( i8* %lt_s, i8 %val1 )
         ret i32 0
 }
diff --git a/test/CodeGen/Hexagon/idxload-with-zero-offset.ll b/test/CodeGen/Hexagon/idxload-with-zero-offset.ll
index 729d79f55a6e..f1a9d38f1b1c 100644
--- a/test/CodeGen/Hexagon/idxload-with-zero-offset.ll
+++ b/test/CodeGen/Hexagon/idxload-with-zero-offset.ll
@@ -1,70 +1,70 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
-; Check that we generate load instruction with (base + register offset << 0)
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; Check that we generate load instruction with (base + register offset << x)
 
 ; load word
 
-define i32 @load_w(i32* nocapture %a, i32 %n) nounwind {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
+define i32 @load_w(i32* nocapture %a, i32 %n, i32 %m) nounwind {
+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#2)
 entry:
-  %tmp = shl i32 %n, 4
-  %scevgep9 = getelementptr i32* %a, i32 %tmp
-  %val = load i32* %scevgep9, align 4
+  %tmp = add i32 %n, %m
+  %scevgep9 = getelementptr i32, i32* %a, i32 %tmp
+  %val = load i32, i32* %scevgep9, align 4
   ret i32 %val
 }
 
 ; load unsigned half word
 
-define i16 @load_uh(i16* nocapture %a, i32 %n) nounwind {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
+define i16 @load_uh(i16* nocapture %a, i32 %n, i32 %m) nounwind {
+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1)
 entry:
-  %tmp = shl i32 %n, 4
-  %scevgep9 = getelementptr i16* %a, i32 %tmp
-  %val = load i16* %scevgep9, align 2
+  %tmp = add i32 %n, %m
+  %scevgep9 = getelementptr i16, i16* %a, i32 %tmp
+  %val = load i16, i16* %scevgep9, align 2
   ret i16 %val
 }
 
 ; load signed half word
 
-define i32 @load_h(i16* nocapture %a, i32 %n) nounwind {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
+define i32 @load_h(i16* nocapture %a, i32 %n, i32 %m) nounwind {
+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1)
 entry:
-  %tmp = shl i32 %n, 4
-  %scevgep9 = getelementptr i16* %a, i32 %tmp
-  %val = load i16* %scevgep9, align 2
+  %tmp = add i32 %n, %m
+  %scevgep9 = getelementptr i16, i16* %a, i32 %tmp
+  %val = load i16, i16* %scevgep9, align 2
   %conv = sext i16 %val to i32
   ret i32 %conv
 }
 
 ; load unsigned byte
 
-define i8 @load_ub(i8* nocapture %a, i32 %n) nounwind {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
+define i8 @load_ub(i8* nocapture %a, i32 %n, i32 %m) nounwind {
+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#0)
 entry:
-  %tmp = shl i32 %n, 4
-  %scevgep9 = getelementptr i8* %a, i32 %tmp
-  %val = load i8* %scevgep9, align 1
+  %tmp = add i32 %n, %m
+  %scevgep9 = getelementptr i8, i8* %a, i32 %tmp
+  %val = load i8, i8* %scevgep9, align 1
   ret i8 %val
 }
 
 ; load signed byte
 
-define i32 @foo_2(i8* nocapture %a, i32 %n) nounwind {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
+define i32 @foo_2(i8* nocapture %a, i32 %n, i32 %m) nounwind {
+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#0)
 entry:
-  %tmp = shl i32 %n, 4
-  %scevgep9 = getelementptr i8* %a, i32 %tmp
-  %val = load i8* %scevgep9, align 1
+  %tmp = add i32 %n, %m
+  %scevgep9 = getelementptr i8, i8* %a, i32 %tmp
+  %val = load i8, i8* %scevgep9, align 1
   %conv = sext i8 %val to i32
   ret i32 %conv
 }
 
 ; load doubleword
 
-define i64 @load_d(i64* nocapture %a, i32 %n) nounwind {
-; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
+define i64 @load_d(i64* nocapture %a, i32 %n, i32 %m) nounwind {
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#3)
 entry:
-  %tmp = shl i32 %n, 4
-  %scevgep9 = getelementptr i64* %a, i32 %tmp
-  %val = load i64* %scevgep9, align 8
+  %tmp = add i32 %n, %m
+  %scevgep9 = getelementptr i64, i64* %a, i32 %tmp
+  %val = load i64, i64* %scevgep9, align 8
   ret i64 %val
 }
diff --git a/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll b/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll
new file mode 100644
index 000000000000..37f9f4007b67
--- /dev/null
+++ b/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll
@@ -0,0 +1,202 @@
+; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
+; Hexagon Programmer's Reference Manual 11.1.1 ALU32/ALU
+
+; Add
+declare i32 @llvm.hexagon.A2.addi(i32, i32)
+define i32 @A2_addi(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.addi(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0, #0)
+
+declare i32 @llvm.hexagon.A2.add(i32, i32)
+define i32 @A2_add(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.add(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0, r1)
+
+declare i32 @llvm.hexagon.A2.addsat(i32, i32)
+define i32 @A2_addsat(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.addsat(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0, r1):sat
+
+; Logical operations
+declare i32 @llvm.hexagon.A2.and(i32, i32)
+define i32 @A2_and(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.and(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = and(r0, r1)
+
+declare i32 @llvm.hexagon.A2.or(i32, i32)
+define i32 @A2_or(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.or(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = or(r0, r1)
+
+declare i32 @llvm.hexagon.A2.xor(i32, i32)
+define i32 @A2_xor(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.xor(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = xor(r0, r1)
+
+declare i32 @llvm.hexagon.A4.andn(i32, i32)
+define i32 @A4_andn(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A4.andn(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = and(r0, ~r1)
+
+declare i32 @llvm.hexagon.A4.orn(i32, i32)
+define i32 @A4_orn(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A4.orn(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = or(r0, ~r1)
+
+; Nop
+declare void @llvm.hexagon.A2.nop()
+define void @A2_nop(i32 %a, i32 %b) {
+  call void @llvm.hexagon.A2.nop()
+  ret void
+}
+; CHECK: nop
+
+; Subtract
+declare i32 @llvm.hexagon.A2.sub(i32, i32)
+define i32 @A2_sub(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.sub(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = sub(r0, r1)
+
+declare i32 @llvm.hexagon.A2.subsat(i32, i32)
+define i32 @A2_subsat(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.subsat(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = sub(r0, r1):sat
+
+; Sign extend
+declare i32 @llvm.hexagon.A2.sxtb(i32)
+define i32 @A2_sxtb(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.sxtb(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = sxtb(r0)
+
+declare i32 @llvm.hexagon.A2.sxth(i32)
+define i32 @A2_sxth(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.sxth(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = sxth(r0)
+
+; Transfer immediate
+declare i32 @llvm.hexagon.A2.tfril(i32, i32)
+define i32 @A2_tfril(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.tfril(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0.l = #0
+
+declare i32 @llvm.hexagon.A2.tfrih(i32, i32)
+define i32 @A2_tfrih(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.tfrih(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0.h = #0
+
+declare i32 @llvm.hexagon.A2.tfrsi(i32)
+define i32 @A2_tfrsi() {
+  %z = call i32 @llvm.hexagon.A2.tfrsi(i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = #0
+
+; Transfer register
+declare i32 @llvm.hexagon.A2.tfr(i32)
+define i32 @A2_tfr(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.tfr(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = r0
+
+; Vector add halfwords
+declare i32 @llvm.hexagon.A2.svaddh(i32, i32)
+define i32 @A2_svaddh(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.svaddh(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = vaddh(r0, r1)
+
+declare i32 @llvm.hexagon.A2.svaddhs(i32, i32)
+define i32 @A2_svaddhs(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.svaddhs(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = vaddh(r0, r1):sat
+
+declare i32 @llvm.hexagon.A2.svadduhs(i32, i32)
+define i32 @A2_svadduhs(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.svadduhs(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = vadduh(r0, r1):sat
+
+; Vector average halfwords
+declare i32 @llvm.hexagon.A2.svavgh(i32, i32)
+define i32 @A2_svavgh(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.svavgh(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = vavgh(r0, r1)
+
+declare i32 @llvm.hexagon.A2.svavghs(i32, i32)
+define i32 @A2_svavghs(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.svavghs(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = vavgh(r0, r1):rnd
+
+declare i32 @llvm.hexagon.A2.svnavgh(i32, i32)
+define i32 @A2_svnavgh(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.svnavgh(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = vnavgh(r0, r1)
+
+; Vector subtract halfwords
+declare i32 @llvm.hexagon.A2.svsubh(i32, i32)
+define i32 @A2_svsubh(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.svsubh(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = vsubh(r0, r1)
+
+declare i32 @llvm.hexagon.A2.svsubhs(i32, i32)
+define i32 @A2_svsubhs(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.svsubhs(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = vsubh(r0, r1):sat
+
+declare i32 @llvm.hexagon.A2.svsubuhs(i32, i32)
+define i32 @A2_svsubuhs(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.svsubuhs(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = vsubuh(r0, r1):sat
+
+; Zero extend
+declare i32 @llvm.hexagon.A2.zxth(i32)
+define i32 @A2_zxth(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.zxth(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = zxth(r0)
diff --git a/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll b/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll
new file mode 100644
index 000000000000..a9cc01c5dcb0
--- /dev/null
+++ b/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll
@@ -0,0 +1,104 @@
+; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
+; Hexagon Programmer's Reference Manual 11.1.2 ALU32/PERM
+
+; Combine words into doubleword
+declare i64 @llvm.hexagon.A4.combineri(i32, i32)
+define i64 @A4_combineri(i32 %a) {
+  %z = call i64 @llvm.hexagon.A4.combineri(i32 %a, i32 0)
+  ret i64 %z
+}
+; CHECK:  = combine(r0, #0)
+
+declare i64 @llvm.hexagon.A4.combineir(i32, i32)
+define i64 @A4_combineir(i32 %a) {
+  %z = call i64 @llvm.hexagon.A4.combineir(i32 0, i32 %a)
+  ret i64 %z
+}
+; CHECK:  = combine(#0, r0)
+
+declare i64 @llvm.hexagon.A2.combineii(i32, i32)
+define i64 @A2_combineii() {
+  %z = call i64 @llvm.hexagon.A2.combineii(i32 0, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = combine(#0, #0)
+
+declare i32 @llvm.hexagon.A2.combine.hh(i32, i32)
+define i32 @A2_combine_hh(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.combine.hh(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = combine(r0.h, r1.h)
+
+declare i32 @llvm.hexagon.A2.combine.hl(i32, i32)
+define i32 @A2_combine_hl(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.combine.hl(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = combine(r0.h, r1.l)
+
+declare i32 @llvm.hexagon.A2.combine.lh(i32, i32)
+define i32 @A2_combine_lh(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.combine.lh(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = combine(r0.l, r1.h)
+
+declare i32 @llvm.hexagon.A2.combine.ll(i32, i32)
+define i32 @A2_combine_ll(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.combine.ll(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = combine(r0.l, r1.l)
+
+declare i64 @llvm.hexagon.A2.combinew(i32, i32)
+define i64 @A2_combinew(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.A2.combinew(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = combine(r0, r1)
+
+; Mux
+declare i32 @llvm.hexagon.C2.muxri(i32, i32, i32)
+define i32 @C2_muxri(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.C2.muxri(i32 %a, i32 0, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mux(p0, #0, r1)
+
+declare i32 @llvm.hexagon.C2.muxir(i32, i32, i32)
+define i32 @C2_muxir(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.C2.muxir(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = mux(p0, r1, #0)
+
+declare i32 @llvm.hexagon.C2.mux(i32, i32, i32)
+define i32 @C2_mux(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.C2.mux(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 = mux(p0, r1, r2)
+
+; Shift word by 16
+declare i32 @llvm.hexagon.A2.aslh(i32)
+define i32 @A2_aslh(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.aslh(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = aslh(r0)
+
+declare i32 @llvm.hexagon.A2.asrh(i32)
+define i32 @A2_asrh(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.asrh(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = asrh(r0)
+
+; Pack high and low halfwords
+declare i64 @llvm.hexagon.S2.packhl(i32, i32)
+define i64 @S2_packhl(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.S2.packhl(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = packhl(r0, r1)
diff --git a/test/CodeGen/Hexagon/intrinsics/cr.ll b/test/CodeGen/Hexagon/intrinsics/cr.ll
new file mode 100644
index 000000000000..9bdcb253fe2f
--- /dev/null
+++ b/test/CodeGen/Hexagon/intrinsics/cr.ll
@@ -0,0 +1,132 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; Hexagon Programmer's Reference Manual 11.2 CR
+
+; Corner detection acceleration
+declare i32 @llvm.hexagon.C4.fastcorner9(i32, i32)
+define i32 @C4_fastcorner9(i32 %a, i32 %b) {
+  %z = call i32@llvm.hexagon.C4.fastcorner9(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = fastcorner9(p0, p1)
+
+declare i32 @llvm.hexagon.C4.fastcorner9.not(i32, i32)
+define i32 @C4_fastcorner9_not(i32 %a, i32 %b) {
+  %z = call i32@llvm.hexagon.C4.fastcorner9.not(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = !fastcorner9(p0, p1)
+
+; Logical reductions on predicates
+declare i32 @llvm.hexagon.C2.any8(i32)
+define i32 @C2_any8(i32 %a) {
+  %z = call i32@llvm.hexagon.C2.any8(i32 %a)
+  ret i32 %z
+}
+; CHECK: p0 = any8(p0)
+
+declare i32 @llvm.hexagon.C2.all8(i32)
+define i32 @C2_all8(i32 %a) {
+  %z = call i32@llvm.hexagon.C2.all8(i32 %a)
+  ret i32 %z
+}
+
+; CHECK: p0 = all8(p0)
+
+; Logical operations on predicates
+declare i32 @llvm.hexagon.C2.and(i32, i32)
+define i32 @C2_and(i32 %a, i32 %b) {
+  %z = call i32@llvm.hexagon.C2.and(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = and(p0, p1)
+
+declare i32 @llvm.hexagon.C4.and.and(i32, i32, i32)
+define i32 @C4_and_and(i32 %a, i32 %b, i32 %c) {
+  %z = call i32@llvm.hexagon.C4.and.and(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: p0 = and(p0, and(p1, p2))
+
+declare i32 @llvm.hexagon.C2.or(i32, i32)
+define i32 @C2_or(i32 %a, i32 %b) {
+  %z = call i32@llvm.hexagon.C2.or(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = or(p0, p1)
+
+declare i32 @llvm.hexagon.C4.and.or(i32, i32, i32)
+define i32 @C4_and_or(i32 %a, i32 %b, i32 %c) {
+  %z = call i32@llvm.hexagon.C4.and.or(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: p0 = and(p0, or(p1, p2))
+
+declare i32 @llvm.hexagon.C2.xor(i32, i32)
+define i32 @C2_xor(i32 %a, i32 %b) {
+  %z = call i32@llvm.hexagon.C2.xor(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = xor(p0, p1)
+
+declare i32 @llvm.hexagon.C4.or.and(i32, i32, i32)
+define i32 @C4_or_and(i32 %a, i32 %b, i32 %c) {
+  %z = call i32@llvm.hexagon.C4.or.and(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: p0 = or(p0, and(p1, p2))
+
+declare i32 @llvm.hexagon.C2.andn(i32, i32)
+define i32 @C2_andn(i32 %a, i32 %b) {
+  %z = call i32@llvm.hexagon.C2.andn(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = and(p0, !p1)
+
+declare i32 @llvm.hexagon.C4.or.or(i32, i32, i32)
+define i32 @C4_or_or(i32 %a, i32 %b, i32 %c) {
+  %z = call i32@llvm.hexagon.C4.or.or(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: p0 = or(p0, or(p1, p2))
+
+declare i32 @llvm.hexagon.C4.and.andn(i32, i32, i32)
+define i32 @C4_and_andn(i32 %a, i32 %b, i32 %c) {
+  %z = call i32@llvm.hexagon.C4.and.andn(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: p0 = and(p0, and(p1, !p2))
+
+declare i32 @llvm.hexagon.C4.and.orn(i32, i32, i32)
+define i32 @C4_and_orn(i32 %a, i32 %b, i32 %c) {
+  %z = call i32@llvm.hexagon.C4.and.orn(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: p0 = and(p0, or(p1, !p2))
+
+declare i32 @llvm.hexagon.C2.not(i32)
+define i32 @C2_not(i32 %a) {
+  %z = call i32@llvm.hexagon.C2.not(i32 %a)
+  ret i32 %z
+}
+; CHECK: p0 = not(p0)
+
+declare i32 @llvm.hexagon.C4.or.andn(i32, i32, i32)
+define i32 @C4_or_andn(i32 %a, i32 %b, i32 %c) {
+  %z = call i32@llvm.hexagon.C4.or.andn(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: p0 = or(p0, and(p1, !p2))
+
+declare i32 @llvm.hexagon.C2.orn(i32, i32)
+define i32 @C2_orn(i32 %a, i32 %b) {
+  %z = call i32@llvm.hexagon.C2.orn(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = or(p0, !p1)
+
+declare i32 @llvm.hexagon.C4.or.orn(i32, i32, i32)
+define i32 @C4_or_orn(i32 %a, i32 %b, i32 %c) {
+  %z = call i32@llvm.hexagon.C4.or.orn(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: p0 = or(p0, or(p1, !p2))
diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll b/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll
new file mode 100644
index 000000000000..4a11112d73a9
--- /dev/null
+++ b/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll
@@ -0,0 +1,1020 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s
+; Hexagon Programmer's Reference Manual 11.10.1 XTYPE/ALU
+
+; Absolute value doubleword
+declare i64 @llvm.hexagon.A2.absp(i64)
+define i64 @A2_absp(i64 %a) {
+  %z = call i64 @llvm.hexagon.A2.absp(i64 %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = abs(r1:0)
+
+; Absolute value word
+declare i32 @llvm.hexagon.A2.abs(i32)
+define i32 @A2_abs(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.abs(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = abs(r0)
+
+declare i32 @llvm.hexagon.A2.abssat(i32)
+define i32 @A2_abssat(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.abssat(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = abs(r0):sat
+
+; Add and accumulate
+declare i32 @llvm.hexagon.S4.addaddi(i32, i32, i32)
+define i32 @S4_addaddi(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S4.addaddi(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0, add(r1, #0))
+
+declare i32 @llvm.hexagon.S4.subaddi(i32, i32, i32)
+define i32 @S4_subaddi(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S4.subaddi(i32 %a, i32 0, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0, sub(#0, r1))
+
+declare i32 @llvm.hexagon.M2.accii(i32, i32, i32)
+define i32 @M2_accii(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.accii(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 += add(r1, #0)
+
+declare i32 @llvm.hexagon.M2.naccii(i32, i32, i32)
+define i32 @M2_naccii(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.naccii(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 -= add(r1, #0)
+
+declare i32 @llvm.hexagon.M2.acci(i32, i32, i32)
+define i32 @M2_acci(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.acci(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += add(r1, r2)
+
+declare i32 @llvm.hexagon.M2.nacci(i32, i32, i32)
+define i32 @M2_nacci(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.nacci(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= add(r1, r2)
+
+; Add doublewords
+declare i64 @llvm.hexagon.A2.addp(i64, i64)
+define i64 @A2_addp(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.addp(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = add(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.addpsat(i64, i64)
+define i64 @A2_addpsat(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.addpsat(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = add(r1:0, r3:2):sat
+
+; Add halfword
+declare i32 @llvm.hexagon.A2.addh.l16.ll(i32, i32)
+define i32 @A2_addh_l16_ll(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.addh.l16.ll(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0.l, r1.l)
+
+declare i32 @llvm.hexagon.A2.addh.l16.hl(i32, i32)
+define i32 @A2_addh_l16_hl(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.addh.l16.hl(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0.l, r1.h)
+
+declare i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32, i32)
+define i32 @A2_addh_l16_sat.ll(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0.l, r1.l):sat
+
+declare i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32, i32)
+define i32 @A2_addh_l16_sat.hl(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0.l, r1.h):sat
+
+declare i32 @llvm.hexagon.A2.addh.h16.ll(i32, i32)
+define i32 @A2_addh_h16_ll(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0.l, r1.l):<<16
+
+declare i32 @llvm.hexagon.A2.addh.h16.lh(i32, i32)
+define i32 @A2_addh_h16_lh(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0.l, r1.h):<<16
+
+declare i32 @llvm.hexagon.A2.addh.h16.hl(i32, i32)
+define i32 @A2_addh_h16_hl(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0.h, r1.l):<<16
+
+declare i32 @llvm.hexagon.A2.addh.h16.hh(i32, i32)
+define i32 @A2_addh_h16_hh(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0.h, r1.h):<<16
+
+declare i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32, i32)
+define i32 @A2_addh_h16_sat_ll(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0.l, r1.l):sat:<<16
+
+declare i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32, i32)
+define i32 @A2_addh_h16_sat_lh(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0.l, r1.h):sat:<<16
+
+declare i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32, i32)
+define i32 @A2_addh_h16_sat_hl(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0.h, r1.l):sat:<<16
+
+declare i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32, i32)
+define i32 @A2_addh_h16_sat_hh(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0.h, r1.h):sat:<<16
+
+; Logical doublewords
+declare i64 @llvm.hexagon.A2.notp(i64)
+define i64 @A2_notp(i64 %a) {
+  %z = call i64 @llvm.hexagon.A2.notp(i64 %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = not(r1:0)
+
+declare i64 @llvm.hexagon.A2.andp(i64, i64)
+define i64 @A2_andp(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.andp(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = and(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A4.andnp(i64, i64)
+define i64 @A2_andnp(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A4.andnp(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = and(r1:0, ~r3:2)
+
+declare i64 @llvm.hexagon.A2.orp(i64, i64)
+define i64 @A2_orp(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.orp(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = or(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A4.ornp(i64, i64)
+define i64 @A2_ornp(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A4.ornp(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = or(r1:0, ~r3:2)
+
+declare i64 @llvm.hexagon.A2.xorp(i64, i64)
+define i64 @A2_xorp(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.xorp(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = xor(r1:0, r3:2)
+
+; Logical-logical doublewords
+declare i64 @llvm.hexagon.M4.xor.xacc(i64, i64, i64)
+define i64 @M4_xor_xacc(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M4.xor.xacc(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 ^= xor(r3:2, r5:4)
+
+; Logical-logical words
+declare i32 @llvm.hexagon.S4.or.andi(i32, i32, i32)
+define i32 @S4_or_andi(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S4.or.andi(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 |= and(r1, #0)
+
+declare i32 @llvm.hexagon.S4.or.andix(i32, i32, i32)
+define i32 @S4_or_andix(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S4.or.andix(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r1 = or(r0, and(r1, #0))
+
+declare i32 @llvm.hexagon.M4.or.andn(i32, i32, i32)
+define i32 @M4_or_andn(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M4.or.andn(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 |= and(r1, ~r2)
+
+declare i32 @llvm.hexagon.M4.and.andn(i32, i32, i32)
+define i32 @M4_and_andn(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M4.and.andn(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 &= and(r1, ~r2)
+
+declare i32 @llvm.hexagon.M4.xor.andn(i32, i32, i32)
+define i32 @M4_xor_andn(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M4.xor.andn(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 ^= and(r1, ~r2)
+
+declare i32 @llvm.hexagon.M4.and.and(i32, i32, i32)
+define i32 @M4_and_and(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M4.and.and(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 &= and(r1, r2)
+
+declare i32 @llvm.hexagon.M4.and.or(i32, i32, i32)
+define i32 @M4_and_or(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M4.and.or(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 &= or(r1, r2)
+
+declare i32 @llvm.hexagon.M4.and.xor(i32, i32, i32)
+define i32 @M4_and_xor(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M4.and.xor(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 &= xor(r1, r2)
+
+declare i32 @llvm.hexagon.M4.or.and(i32, i32, i32)
+define i32 @M4_or_and(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M4.or.and(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 |= and(r1, r2)
+
+declare i32 @llvm.hexagon.M4.or.or(i32, i32, i32)
+define i32 @M4_or_or(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M4.or.or(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 |= or(r1, r2)
+
+declare i32 @llvm.hexagon.M4.or.xor(i32, i32, i32)
+define i32 @M4_or_xor(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M4.or.xor(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 |= xor(r1, r2)
+
+declare i32 @llvm.hexagon.M4.xor.and(i32, i32, i32)
+define i32 @M4_xor_and(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M4.xor.and(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 ^= and(r1, r2)
+
+declare i32 @llvm.hexagon.M4.xor.or(i32, i32, i32)
+define i32 @M4_xor_or(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M4.xor.or(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 ^= or(r1, r2)
+
+; Maximum words
+declare i32 @llvm.hexagon.A2.max(i32, i32)
+define i32 @A2_max(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.max(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = max(r0, r1)
+
+declare i32 @llvm.hexagon.A2.maxu(i32, i32)
+define i32 @A2_maxu(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.maxu(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = maxu(r0, r1)
+
+; Maximum doublewords
+declare i64 @llvm.hexagon.A2.maxp(i64, i64)
+define i64 @A2_maxp(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.maxp(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = max(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.maxup(i64, i64)
+define i64 @A2_maxup(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.maxup(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = maxu(r1:0, r3:2)
+
+; Minimum words
+declare i32 @llvm.hexagon.A2.min(i32, i32)
+define i32 @A2_min(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.min(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = min(r0, r1)
+
+declare i32 @llvm.hexagon.A2.minu(i32, i32)
+define i32 @A2_minu(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.minu(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = minu(r0, r1)
+
+; Minimum doublewords
+declare i64 @llvm.hexagon.A2.minp(i64, i64)
+define i64 @A2_minp(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.minp(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = min(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.minup(i64, i64)
+define i64 @A2_minup(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.minup(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = minu(r1:0, r3:2)
+
+; Module wrap
+declare i32 @llvm.hexagon.A4.modwrapu(i32, i32)
+define i32 @A4_modwrapu(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A4.modwrapu(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = modwrap(r0, r1)
+
+; Negate
+declare i64 @llvm.hexagon.A2.negp(i64)
+define i64 @A2_negp(i64 %a) {
+  %z = call i64 @llvm.hexagon.A2.negp(i64 %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = neg(r1:0)
+
+declare i32 @llvm.hexagon.A2.negsat(i32)
+define i32 @A2_negsat(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.negsat(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = neg(r0):sat
+
+; Round
+declare i32 @llvm.hexagon.A2.roundsat(i64)
+define i32 @A2_roundsat(i64 %a) {
+  %z = call i32 @llvm.hexagon.A2.roundsat(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = round(r1:0):sat
+
+declare i32 @llvm.hexagon.A4.cround.ri(i32, i32)
+define i32 @A4_cround_ri(i32 %a) {
+  %z = call i32 @llvm.hexagon.A4.cround.ri(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = cround(r0, #0)
+
+declare i32 @llvm.hexagon.A4.round.ri(i32, i32)
+define i32 @A4_round_ri(i32 %a) {
+  %z = call i32 @llvm.hexagon.A4.round.ri(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = round(r0, #0)
+
+declare i32 @llvm.hexagon.A4.round.ri.sat(i32, i32)
+define i32 @A4_round_ri_sat(i32 %a) {
+  %z = call i32 @llvm.hexagon.A4.round.ri.sat(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = round(r0, #0):sat
+
+declare i32 @llvm.hexagon.A4.cround.rr(i32, i32)
+define i32 @A4_cround_rr(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A4.cround.rr(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = cround(r0, r1)
+
+declare i32 @llvm.hexagon.A4.round.rr(i32, i32)
+define i32 @A4_round_rr(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A4.round.rr(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = round(r0, r1)
+
+declare i32 @llvm.hexagon.A4.round.rr.sat(i32, i32)
+define i32 @A4_round_rr_sat(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A4.round.rr.sat(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = round(r0, r1):sat
+
+; Subtract doublewords
+declare i64 @llvm.hexagon.A2.subp(i64, i64)
+define i64 @A2_subp(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.subp(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = sub(r1:0, r3:2)
+
+; Subtract and accumulate
+declare i32 @llvm.hexagon.M2.subacc(i32, i32, i32)
+define i32 @M2_subacc(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.subacc(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += sub(r1, r2)
+
+; Subtract halfwords
+declare i32 @llvm.hexagon.A2.subh.l16.ll(i32, i32)
+define i32 @A2_subh_l16_ll(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.subh.l16.ll(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = sub(r0.l, r1.l)
+
+declare i32 @llvm.hexagon.A2.subh.l16.hl(i32, i32)
+define i32 @A2_subh_l16_hl(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.subh.l16.hl(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = sub(r0.l, r1.h)
+
+declare i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32, i32)
+define i32 @A2_subh_l16_sat.ll(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = sub(r0.l, r1.l):sat
+
+declare i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32, i32)
+define i32 @A2_subh_l16_sat.hl(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = sub(r0.l, r1.h):sat
+
+declare i32 @llvm.hexagon.A2.subh.h16.ll(i32, i32)
+define i32 @A2_subh_h16_ll(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.subh.h16.ll(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = sub(r0.l, r1.l):<<16
+
+declare i32 @llvm.hexagon.A2.subh.h16.lh(i32, i32)
+define i32 @A2_subh_h16_lh(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.subh.h16.lh(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = sub(r0.l, r1.h):<<16
+
+declare i32 @llvm.hexagon.A2.subh.h16.hl(i32, i32)
+define i32 @A2_subh_h16_hl(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.subh.h16.hl(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = sub(r0.h, r1.l):<<16
+
+declare i32 @llvm.hexagon.A2.subh.h16.hh(i32, i32)
+define i32 @A2_subh_h16_hh(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.subh.h16.hh(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = sub(r0.h, r1.h):<<16
+
+declare i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32, i32)
+define i32 @A2_subh_h16_sat_ll(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = sub(r0.l, r1.l):sat:<<16
+
+declare i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32, i32)
+define i32 @A2_subh_h16_sat_lh(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = sub(r0.l, r1.h):sat:<<16
+
+declare i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32, i32)
+define i32 @A2_subh_h16_sat_hl(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = sub(r0.h, r1.l):sat:<<16
+
+declare i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32, i32)
+define i32 @A2_subh_h16_sat_hh(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = sub(r0.h, r1.h):sat:<<16
+
+; Sign extend word to doubleword
+declare i64 @llvm.hexagon.A2.sxtw(i32)
+define i64 @A2_sxtw(i32 %a) {
+  %z = call i64 @llvm.hexagon.A2.sxtw(i32 %a)
+  ret i64 %z
+}
+; CHECK:  = sxtw(r0)
+
+; Vector absolute value halfwords
+declare i64 @llvm.hexagon.A2.vabsh(i64)
+define i64 @A2_vabsh(i64 %a) {
+  %z = call i64 @llvm.hexagon.A2.vabsh(i64 %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = vabsh(r1:0)
+
+declare i64 @llvm.hexagon.A2.vabshsat(i64)
+define i64 @A2_vabshsat(i64 %a) {
+  %z = call i64 @llvm.hexagon.A2.vabshsat(i64 %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = vabsh(r1:0):sat
+
+; Vector absolute value words
+declare i64 @llvm.hexagon.A2.vabsw(i64)
+define i64 @A2_vabsw(i64 %a) {
+  %z = call i64 @llvm.hexagon.A2.vabsw(i64 %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = vabsw(r1:0)
+
+declare i64 @llvm.hexagon.A2.vabswsat(i64)
+define i64 @A2_vabswsat(i64 %a) {
+  %z = call i64 @llvm.hexagon.A2.vabswsat(i64 %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = vabsw(r1:0):sat
+
+; Vector absolute difference halfwords
+declare i64 @llvm.hexagon.M2.vabsdiffh(i64, i64)
+define i64 @M2_vabsdiffh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.vabsdiffh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vabsdiffh(r1:0, r3:2)
+
+; Vector absolute difference words
+declare i64 @llvm.hexagon.M2.vabsdiffw(i64, i64)
+define i64 @M2_vabsdiffw(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.vabsdiffw(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vabsdiffw(r1:0, r3:2)
+
+; Vector add halfwords
+declare i64 @llvm.hexagon.A2.vaddh(i64, i64)
+define i64 @A2_vaddh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vaddh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vaddh(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vaddhs(i64, i64)
+define i64 @A2_vaddhs(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vaddhs(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vaddh(r1:0, r3:2):sat
+
+declare i64 @llvm.hexagon.A2.vadduhs(i64, i64)
+define i64 @A2_vadduhs(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vadduhs(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vadduh(r1:0, r3:2):sat
+
+; Vector add halfwords with saturate and pack to unsigned bytes
+declare i32 @llvm.hexagon.A5.vaddhubs(i64, i64)
+define i32 @A5_vaddhubs(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.A5.vaddhubs(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: r0 = vaddhub(r1:0, r3:2):sat
+
+; Vector reduce add unsigned bytes
+declare i64 @llvm.hexagon.A2.vraddub(i64, i64)
+define i64 @A2_vraddub(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vraddub(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vraddub(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vraddub.acc(i64, i64, i64)
+define i64 @A2_vraddub_acc(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.A2.vraddub.acc(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vraddub(r3:2, r5:4)
+
+; Vector reduce add halfwords
+declare i32 @llvm.hexagon.M2.vradduh(i64, i64)
+define i32 @M2_vradduh(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.M2.vradduh(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: r0 = vradduh(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.M2.vraddh(i64, i64)
+define i32 @M2_vraddh(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.M2.vraddh(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: r0 = vraddh(r1:0, r3:2)
+
+; Vector add bytes
+declare i64 @llvm.hexagon.A2.vaddub(i64, i64)
+define i64 @A2_vaddub(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vaddub(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vaddub(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vaddubs(i64, i64)
+define i64 @A2_vaddubs(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vaddubs(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vaddub(r1:0, r3:2):sat
+
+; Vector add words
+declare i64 @llvm.hexagon.A2.vaddw(i64, i64)
+define i64 @A2_vaddw(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vaddw(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vaddw(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vaddws(i64, i64)
+define i64 @A2_vaddws(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vaddws(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vaddw(r1:0, r3:2):sat
+
+; Vector average halfwords
+declare i64 @llvm.hexagon.A2.vavgh(i64, i64)
+define i64 @A2_vavgh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vavgh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vavgh(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vavghr(i64, i64)
+define i64 @A2_vavghr(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vavghr(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vavgh(r1:0, r3:2):rnd
+
+declare i64 @llvm.hexagon.A2.vavghcr(i64, i64)
+define i64 @A2_vavghcr(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vavghcr(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vavgh(r1:0, r3:2):crnd
+
+declare i64 @llvm.hexagon.A2.vavguh(i64, i64)
+define i64 @A2_vavguh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vavguh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vavguh(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vavguhr(i64, i64)
+define i64 @A2_vavguhr(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vavguhr(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vavguh(r1:0, r3:2):rnd
+
+declare i64 @llvm.hexagon.A2.vnavgh(i64, i64)
+define i64 @A2_vnavgh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vnavgh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vnavgh(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vnavghr(i64, i64)
+define i64 @A2_vnavghr(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vnavghr(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vnavgh(r1:0, r3:2):rnd
+
+declare i64 @llvm.hexagon.A2.vnavghcr(i64, i64)
+define i64 @A2_vnavghcr(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vnavghcr(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vnavgh(r1:0, r3:2):crnd
+
+; Vector average unsigned bytes
+declare i64 @llvm.hexagon.A2.vavgub(i64, i64)
+define i64 @A2_vavgub(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vavgub(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vavgub(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vavgubr(i64, i64)
+define i64 @A2_vavgubr(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vavgubr(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vavgub(r1:0, r3:2):rnd
+
+; Vector average words
+declare i64 @llvm.hexagon.A2.vavgw(i64, i64)
+define i64 @A2_vavgw(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vavgw(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vavgw(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vavgwr(i64, i64)
+define i64 @A2_vavgwr(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vavgwr(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vavgw(r1:0, r3:2):rnd
+
+declare i64 @llvm.hexagon.A2.vavgwcr(i64, i64)
+define i64 @A2_vavgwcr(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vavgwcr(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vavgw(r1:0, r3:2):crnd
+
+declare i64 @llvm.hexagon.A2.vavguw(i64, i64)
+define i64 @A2_vavguw(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vavguw(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vavguw(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vavguwr(i64, i64)
+define i64 @A2_vavguwr(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vavguwr(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vavguw(r1:0, r3:2):rnd
+
+declare i64 @llvm.hexagon.A2.vnavgw(i64, i64)
+define i64 @A2_vnavgw(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vnavgw(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vnavgw(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vnavgwr(i64, i64)
+define i64 @A2_vnavgwr(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vnavgwr(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vnavgw(r1:0, r3:2):rnd
+
+declare i64 @llvm.hexagon.A2.vnavgwcr(i64, i64)
+define i64 @A2_vnavgwcr(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vnavgwcr(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vnavgw(r1:0, r3:2):crnd
+
+; Vector conditional negate
+declare i64 @llvm.hexagon.S2.vcnegh(i64, i32)
+define i64 @S2_vcnegh(i64 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.S2.vcnegh(i64 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vcnegh(r1:0, r2)
+
+declare i64 @llvm.hexagon.S2.vrcnegh(i64, i64, i32)
+define i64 @S2_vrcnegh(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.vrcnegh(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vrcnegh(r3:2, r4)
+
+; Vector maximum bytes
+declare i64 @llvm.hexagon.A2.vmaxub(i64, i64)
+define i64 @A2_vmaxub(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vmaxub(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmaxub(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vmaxb(i64, i64)
+define i64 @A2_vmaxb(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vmaxb(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmaxb(r1:0, r3:2)
+
+; Vector maximum halfwords
+declare i64 @llvm.hexagon.A2.vmaxh(i64, i64)
+define i64 @A2_vmaxh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vmaxh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmaxh(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vmaxuh(i64, i64)
+define i64 @A2_vmaxuh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vmaxuh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmaxuh(r1:0, r3:2)
+
+; Vector reduce maximum halfwords
+declare i64 @llvm.hexagon.A4.vrmaxh(i64, i64, i32)
+define i64 @A4_vrmaxh(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.A4.vrmaxh(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrmaxh(r3:2, r4)
+
+declare i64 @llvm.hexagon.A4.vrmaxuh(i64, i64, i32)
+define i64 @A4_vrmaxuh(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.A4.vrmaxuh(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrmaxuh(r3:2, r4)
+
+; Vector reduce maximum words
+declare i64 @llvm.hexagon.A4.vrmaxw(i64, i64, i32)
+define i64 @A4_vrmaxw(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.A4.vrmaxw(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrmaxw(r3:2, r4)
+
+declare i64 @llvm.hexagon.A4.vrmaxuw(i64, i64, i32)
+define i64 @A4_vrmaxuw(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.A4.vrmaxuw(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrmaxuw(r3:2, r4)
+
+; Vector minimum bytes
+declare i64 @llvm.hexagon.A2.vminub(i64, i64)
+define i64 @A2_vminub(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vminub(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vminub(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vminb(i64, i64)
+define i64 @A2_vminb(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vminb(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vminb(r1:0, r3:2)
+
+; Vector minimum halfwords
+declare i64 @llvm.hexagon.A2.vminh(i64, i64)
+define i64 @A2_vminh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vminh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vminh(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vminuh(i64, i64)
+define i64 @A2_vminuh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vminuh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vminuh(r1:0, r3:2)
+
+; Vector reduce minimum halfwords
+declare i64 @llvm.hexagon.A4.vrminh(i64, i64, i32)
+define i64 @A4_vrminh(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.A4.vrminh(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrminh(r3:2, r4)
+
+declare i64 @llvm.hexagon.A4.vrminuh(i64, i64, i32)
+define i64 @A4_vrminuh(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.A4.vrminuh(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrminuh(r3:2, r4)
+
+; Vector reduce minimum words
+declare i64 @llvm.hexagon.A4.vrminw(i64, i64, i32)
+define i64 @A4_vrminw(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.A4.vrminw(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrminw(r3:2, r4)
+
+declare i64 @llvm.hexagon.A4.vrminuw(i64, i64, i32)
+define i64 @A4_vrminuw(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.A4.vrminuw(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrminuw(r3:2, r4)
+
+; Vector sum of absolute differences unsigned bytes
+declare i64 @llvm.hexagon.A2.vrsadub(i64, i64)
+define i64 @A2_vrsadub(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vrsadub(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrsadub(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vrsadub.acc(i64, i64, i64)
+define i64 @A2_vrsadub_acc(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.A2.vrsadub.acc(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vrsadub(r3:2, r5:4)
+
+; Vector subtract halfwords
+declare i64 @llvm.hexagon.A2.vsubh(i64, i64)
+define i64 @A2_vsubh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vsubh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vsubh(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vsubhs(i64, i64)
+define i64 @A2_vsubhs(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vsubhs(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vsubh(r1:0, r3:2):sat
+
+declare i64 @llvm.hexagon.A2.vsubuhs(i64, i64)
+define i64 @A2_vsubuhs(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vsubuhs(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vsubuh(r1:0, r3:2):sat
+
+; Vector subtract bytes
+declare i64 @llvm.hexagon.A2.vsubub(i64, i64)
+define i64 @A2_vsubub(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vsubub(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vsubub(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vsububs(i64, i64)
+define i64 @A2_vsububs(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vsububs(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vsubub(r1:0, r3:2):sat
+
+; Vector subtract words
+declare i64 @llvm.hexagon.A2.vsubw(i64, i64)
+define i64 @A2_vsubw(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vsubw(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vsubw(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.A2.vsubws(i64, i64)
+define i64 @A2_vsubws(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.A2.vsubws(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vsubw(r1:0, r3:2):sat
diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll b/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll
new file mode 100644
index 000000000000..8531b2f9334b
--- /dev/null
+++ b/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll
@@ -0,0 +1,329 @@
+; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
+; Hexagon Programmer's Reference Manual 11.10.2 XTYPE/BIT
+
+; Count leading
+declare i32 @llvm.hexagon.S2.clbp(i64)
+define i32 @S2_clbp(i64 %a) {
+  %z = call i32 @llvm.hexagon.S2.clbp(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = clb(r1:0)
+
+declare i32 @llvm.hexagon.S2.cl0p(i64)
+define i32 @S2_cl0p(i64 %a) {
+  %z = call i32 @llvm.hexagon.S2.cl0p(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = cl0(r1:0)
+
+declare i32 @llvm.hexagon.S2.cl1p(i64)
+define i32 @S2_cl1p(i64 %a) {
+  %z = call i32 @llvm.hexagon.S2.cl1p(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = cl1(r1:0)
+
+declare i32 @llvm.hexagon.S4.clbpnorm(i64)
+define i32 @S4_clbpnorm(i64 %a) {
+  %z = call i32 @llvm.hexagon.S4.clbpnorm(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = normamt(r1:0)
+
+declare i32 @llvm.hexagon.S4.clbpaddi(i64, i32)
+define i32 @S4_clbpaddi(i64 %a) {
+  %z = call i32 @llvm.hexagon.S4.clbpaddi(i64 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = add(clb(r1:0), #0)
+
+declare i32 @llvm.hexagon.S4.clbaddi(i32, i32)
+define i32 @S4_clbaddi(i32 %a) {
+  %z = call i32 @llvm.hexagon.S4.clbaddi(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = add(clb(r0), #0)
+
+declare i32 @llvm.hexagon.S2.cl0(i32)
+define i32 @S2_cl0(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.cl0(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = cl0(r0)
+
+declare i32 @llvm.hexagon.S2.cl1(i32)
+define i32 @S2_cl1(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.cl1(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = cl1(r0)
+
+declare i32 @llvm.hexagon.S2.clbnorm(i32)
+define i32 @S4_clbnorm(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.clbnorm(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = normamt(r0)
+
+; Count population
+declare i32 @llvm.hexagon.S5.popcountp(i64)
+define i32 @S5_popcountp(i64 %a) {
+  %z = call i32 @llvm.hexagon.S5.popcountp(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = popcount(r1:0)
+
+; Count trailing
+declare i32 @llvm.hexagon.S2.ct0p(i64)
+define i32 @S2_ct0p(i64 %a) {
+  %z = call i32 @llvm.hexagon.S2.ct0p(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = ct0(r1:0)
+
+declare i32 @llvm.hexagon.S2.ct1p(i64)
+define i32 @S2_ct1p(i64 %a) {
+  %z = call i32 @llvm.hexagon.S2.ct1p(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = ct1(r1:0)
+
+declare i32 @llvm.hexagon.S2.ct0(i32)
+define i32 @S2_ct0(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.ct0(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = ct0(r0)
+
+declare i32 @llvm.hexagon.S2.ct1(i32)
+define i32 @S2_ct1(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.ct1(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = ct1(r0)
+
+; Extract bitfield
+declare i64 @llvm.hexagon.S2.extractup(i64, i32, i32)
+define i64 @S2_extractup(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.extractup(i64 %a, i32 0, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = extractu(r1:0, #0, #0)
+
+declare i64 @llvm.hexagon.S4.extractp(i64, i32, i32)
+define i64 @S2_extractp(i64 %a) {
+  %z = call i64 @llvm.hexagon.S4.extractp(i64 %a, i32 0, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = extract(r1:0, #0, #0)
+
+declare i32 @llvm.hexagon.S2.extractu(i32, i32, i32)
+define i32 @S2_extractu(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.extractu(i32 %a, i32 0, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = extractu(r0, #0, #0)
+
+declare i32 @llvm.hexagon.S4.extract(i32, i32, i32)
+define i32 @S2_extract(i32 %a) {
+  %z = call i32 @llvm.hexagon.S4.extract(i32 %a, i32 0, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = extract(r0, #0, #0)
+
+declare i64 @llvm.hexagon.S2.extractup.rp(i64, i64)
+define i64 @S2_extractup_rp(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.extractup.rp(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = extractu(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.S4.extractp.rp(i64, i64)
+define i64 @S4_extractp_rp(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S4.extractp.rp(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = extract(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.S2.extractu.rp(i32, i64)
+define i32 @S2_extractu_rp(i32 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.S2.extractu.rp(i32 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: r0 = extractu(r0, r3:2)
+
+declare i32 @llvm.hexagon.S4.extract.rp(i32, i64)
+define i32 @S4_extract_rp(i32 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.S4.extract.rp(i32 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: r0 = extract(r0, r3:2)
+
+; Insert bitfield
+declare i64 @llvm.hexagon.S2.insertp(i64, i64, i32, i32)
+define i64 @S2_insertp(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.insertp(i64 %a, i64 %b, i32 0, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = insert(r3:2, #0, #0)
+
+declare i32 @llvm.hexagon.S2.insert(i32, i32, i32, i32)
+define i32 @S2_insert(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.insert(i32 %a, i32 %b, i32 0, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = insert(r1, #0, #0)
+
+declare i32 @llvm.hexagon.S2.insert.rp(i32, i32, i64)
+define i32 @S2_insert_rp(i32 %a, i32 %b, i64 %c) {
+  %z = call i32 @llvm.hexagon.S2.insert.rp(i32 %a, i32 %b, i64 %c)
+  ret i32 %z
+}
+; CHECK: r0 = insert(r1, r3:2)
+
+declare i64 @llvm.hexagon.S2.insertp.rp(i64, i64, i64)
+define i64 @S2_insertp_rp(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.S2.insertp.rp(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 = insert(r3:2, r5:4)
+
+; Interleave/deinterleave
+declare i64 @llvm.hexagon.S2.deinterleave(i64)
+define i64 @S2_deinterleave(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.deinterleave(i64 %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = deinterleave(r1:0)
+
+declare i64 @llvm.hexagon.S2.interleave(i64)
+define i64 @S2_interleave(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.interleave(i64 %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = interleave(r1:0)
+
+; Linear feedback-shift operation
+declare i64 @llvm.hexagon.S2.lfsp(i64, i64)
+define i64 @S2_lfsp(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.lfsp(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = lfs(r1:0, r3:2)
+
+; Masked parity
+declare i32 @llvm.hexagon.S2.parityp(i64, i64)
+define i32 @S2_parityp(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.S2.parityp(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: r0 = parity(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.S4.parity(i32, i32)
+define i32 @S4_parity(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S4.parity(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = parity(r0, r1)
+
+; Bit reverse
+declare i64 @llvm.hexagon.S2.brevp(i64)
+define i64 @S2_brevp(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.brevp(i64 %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = brev(r1:0)
+
+declare i32 @llvm.hexagon.S2.brev(i32)
+define i32 @S2_brev(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.brev(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = brev(r0)
+
+; Set/clear/toggle bit
+declare i32 @llvm.hexagon.S2.setbit.i(i32, i32)
+define i32 @S2_setbit_i(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.setbit.i(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = setbit(r0, #0)
+
+declare i32 @llvm.hexagon.S2.clrbit.i(i32, i32)
+define i32 @S2_clrbit_i(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.clrbit.i(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = clrbit(r0, #0)
+
+declare i32 @llvm.hexagon.S2.togglebit.i(i32, i32)
+define i32 @S2_togglebit_i(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.togglebit.i(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = togglebit(r0, #0)
+
+declare i32 @llvm.hexagon.S2.setbit.r(i32, i32)
+define i32 @S2_setbit_r(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.setbit.r(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = setbit(r0, r1)
+
+declare i32 @llvm.hexagon.S2.clrbit.r(i32, i32)
+define i32 @S2_clrbit_r(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.clrbit.r(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = clrbit(r0, r1)
+
+declare i32 @llvm.hexagon.S2.togglebit.r(i32, i32)
+define i32 @S2_togglebit_r(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.togglebit.r(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = togglebit(r0, r1)
+
+; Split bitfield
+declare i64 @llvm.hexagon.A4.bitspliti(i32, i32)
+define i64 @A4_bitspliti(i32 %a) {
+  %z = call i64 @llvm.hexagon.A4.bitspliti(i32 %a, i32 0)
+  ret i64 %z
+}
+; CHECK:  = bitsplit(r0, #0)
+
+declare i64 @llvm.hexagon.A4.bitsplit(i32, i32)
+define i64 @A4_bitsplit(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.A4.bitsplit(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = bitsplit(r0, r1)
+
+; Table index
+declare i32 @llvm.hexagon.S2.tableidxb.goodsyntax(i32, i32, i32, i32)
+define i32 @S2_tableidxb_goodsyntax(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.tableidxb.goodsyntax(i32 %a, i32 %b, i32 0, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = tableidxb(r1, #0, #0)
+
+declare i32 @llvm.hexagon.S2.tableidxh.goodsyntax(i32, i32, i32, i32)
+define i32 @S2_tableidxh_goodsyntax(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.tableidxh.goodsyntax(i32 %a, i32 %b, i32 0, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = tableidxh(r1, #0, #-1)
+
+declare i32 @llvm.hexagon.S2.tableidxw.goodsyntax(i32, i32, i32, i32)
+define i32 @S2_tableidxw_goodsyntax(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.tableidxw.goodsyntax(i32 %a, i32 %b, i32 0, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = tableidxw(r1, #0, #-2)
+
+declare i32 @llvm.hexagon.S2.tableidxd.goodsyntax(i32, i32, i32, i32)
+define i32 @S2_tableidxd_goodsyntax(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.tableidxd.goodsyntax(i32 %a, i32 %b, i32 0, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = tableidxd(r1, #0, #-3)
diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll b/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll
new file mode 100644
index 000000000000..57b0c5b6db56
--- /dev/null
+++ b/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll
@@ -0,0 +1,349 @@
+; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
+; Hexagon Programmer's Reference Manual 11.10.3 XTYPE/COMPLEX
+
+; Complex add/sub halfwords
+declare i64 @llvm.hexagon.S4.vxaddsubh(i64, i64)
+define i64 @S4_vxaddsubh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S4.vxaddsubh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vxaddsubh(r1:0, r3:2):sat
+
+declare i64 @llvm.hexagon.S4.vxsubaddh(i64, i64)
+define i64 @S4_vxsubaddh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S4.vxsubaddh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vxsubaddh(r1:0, r3:2):sat
+
+declare i64 @llvm.hexagon.S4.vxaddsubhr(i64, i64)
+define i64 @S4_vxaddsubhr(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S4.vxaddsubhr(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vxaddsubh(r1:0, r3:2):rnd:>>1:sat
+
+declare i64 @llvm.hexagon.S4.vxsubaddhr(i64, i64)
+define i64 @S4_vxsubaddhr(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S4.vxsubaddhr(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vxsubaddh(r1:0, r3:2):rnd:>>1:sat
+
+; Complex add/sub words
+declare i64 @llvm.hexagon.S4.vxaddsubw(i64, i64)
+define i64 @S4_vxaddsubw(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S4.vxaddsubw(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vxaddsubw(r1:0, r3:2):sat
+
+declare i64 @llvm.hexagon.S4.vxsubaddw(i64, i64)
+define i64 @S4_vxsubaddw(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S4.vxsubaddw(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vxsubaddw(r1:0, r3:2):sat
+
+; Complex multiply
+declare i64 @llvm.hexagon.M2.cmpys.s0(i32, i32)
+define i64 @M2_cmpys_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.cmpys.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = cmpy(r0, r1):sat
+
+declare i64 @llvm.hexagon.M2.cmpys.s1(i32, i32)
+define i64 @M2_cmpys_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.cmpys.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = cmpy(r0, r1):<<1:sat
+
+declare i64 @llvm.hexagon.M2.cmpysc.s0(i32, i32)
+define i64 @M2_cmpysc_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.cmpysc.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = cmpy(r0, r1*):sat
+
+declare i64 @llvm.hexagon.M2.cmpysc.s1(i32, i32)
+define i64 @M2_cmpysc_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.cmpysc.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = cmpy(r0, r1*):<<1:sat
+
+declare i64 @llvm.hexagon.M2.cmacs.s0(i64, i32, i32)
+define i64 @M2_cmacs_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.cmacs.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += cmpy(r2, r3):sat
+
+declare i64 @llvm.hexagon.M2.cmacs.s1(i64, i32, i32)
+define i64 @M2_cmacs_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.cmacs.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += cmpy(r2, r3):<<1:sat
+
+declare i64 @llvm.hexagon.M2.cnacs.s0(i64, i32, i32)
+define i64 @M2_cnacs_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.cnacs.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= cmpy(r2, r3):sat
+
+declare i64 @llvm.hexagon.M2.cnacs.s1(i64, i32, i32)
+define i64 @M2_cnacs_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.cnacs.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= cmpy(r2, r3):<<1:sat
+
+declare i64 @llvm.hexagon.M2.cmacsc.s0(i64, i32, i32)
+define i64 @M2_cmacsc_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.cmacsc.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += cmpy(r2, r3*):sat
+
+declare i64 @llvm.hexagon.M2.cmacsc.s1(i64, i32, i32)
+define i64 @M2_cmacsc_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.cmacsc.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += cmpy(r2, r3*):<<1:sat
+
+declare i64 @llvm.hexagon.M2.cnacsc.s0(i64, i32, i32)
+define i64 @M2_cnacsc_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.cnacsc.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= cmpy(r2, r3*):sat
+
+declare i64 @llvm.hexagon.M2.cnacsc.s1(i64, i32, i32)
+define i64 @M2_cnacsc_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.cnacsc.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= cmpy(r2, r3*):<<1:sat
+
+; Complex multiply real or imaginary
+declare i64 @llvm.hexagon.M2.cmpyi.s0(i32, i32)
+define i64 @M2_cmpyi_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.cmpyi.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = cmpyi(r0, r1)
+
+declare i64 @llvm.hexagon.M2.cmpyr.s0(i32, i32)
+define i64 @M2_cmpyr_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.cmpyr.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = cmpyr(r0, r1)
+
+declare i64 @llvm.hexagon.M2.cmaci.s0(i64, i32, i32)
+define i64 @M2_cmaci_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.cmaci.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += cmpyi(r2, r3)
+
+declare i64 @llvm.hexagon.M2.cmacr.s0(i64, i32, i32)
+define i64 @M2_cmacr_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.cmacr.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += cmpyr(r2, r3)
+
+; Complex multiply with round and pack
+declare i32 @llvm.hexagon.M2.cmpyrs.s0(i32, i32)
+define i32 @M2_cmpyrs_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.cmpyrs.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = cmpy(r0, r1):rnd:sat
+
+declare i32 @llvm.hexagon.M2.cmpyrs.s1(i32, i32)
+define i32 @M2_cmpyrs_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.cmpyrs.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = cmpy(r0, r1):<<1:rnd:sat
+
+declare i32 @llvm.hexagon.M2.cmpyrsc.s0(i32, i32)
+define i32 @M2_cmpyrsc_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.cmpyrsc.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = cmpy(r0, r1*):rnd:sat
+
+declare i32 @llvm.hexagon.M2.cmpyrsc.s1(i32, i32)
+define i32 @M2_cmpyrsc_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.cmpyrsc.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = cmpy(r0, r1*):<<1:rnd:sat
+
+; Complex multiply 32x16
+declare i32 @llvm.hexagon.M4.cmpyi.wh(i64, i32)
+define i32 @M4_cmpyi_wh(i64 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M4.cmpyi.wh(i64 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = cmpyiwh(r1:0, r2):<<1:rnd:sat
+
+declare i32 @llvm.hexagon.M4.cmpyi.whc(i64, i32)
+define i32 @M4_cmpyi_whc(i64 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M4.cmpyi.whc(i64 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = cmpyiwh(r1:0, r2*):<<1:rnd:sat
+
+declare i32 @llvm.hexagon.M4.cmpyr.wh(i64, i32)
+define i32 @M4_cmpyr_wh(i64 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M4.cmpyr.wh(i64 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = cmpyrwh(r1:0, r2):<<1:rnd:sat
+
+declare i32 @llvm.hexagon.M4.cmpyr.whc(i64, i32)
+define i32 @M4_cmpyr_whc(i64 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M4.cmpyr.whc(i64 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = cmpyrwh(r1:0, r2*):<<1:rnd:sat
+
+; Vector complex multiply real or imaginary
+declare i64 @llvm.hexagon.M2.vcmpy.s0.sat.r(i64, i64)
+define i64 @M2_vcmpy_s0_sat_r(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.vcmpy.s0.sat.r(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vcmpyr(r1:0, r3:2):sat
+
+declare i64 @llvm.hexagon.M2.vcmpy.s1.sat.r(i64, i64)
+define i64 @M2_vcmpy_s1_sat_r(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.vcmpy.s1.sat.r(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vcmpyr(r1:0, r3:2):<<1:sat
+
+declare i64 @llvm.hexagon.M2.vcmpy.s0.sat.i(i64, i64)
+define i64 @M2_vcmpy_s0_sat_i(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.vcmpy.s0.sat.i(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vcmpyi(r1:0, r3:2):sat
+
+declare i64 @llvm.hexagon.M2.vcmpy.s1.sat.i(i64, i64)
+define i64 @M2_vcmpy_s1_sat_i(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.vcmpy.s1.sat.i(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vcmpyi(r1:0, r3:2):<<1:sat
+
+declare i64 @llvm.hexagon.M2.vcmac.s0.sat.r(i64, i64, i64)
+define i64 @M2_vcmac_s0_sat_r(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M2.vcmac.s0.sat.r(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vcmpyr(r3:2, r5:4):sat
+
+declare i64 @llvm.hexagon.M2.vcmac.s0.sat.i(i64, i64, i64)
+define i64 @M2_vcmac_s0_sat_i(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M2.vcmac.s0.sat.i(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vcmpyi(r3:2, r5:4):sat
+
+; Vector complex conjugate
+declare i64 @llvm.hexagon.A2.vconj(i64)
+define i64 @A2_vconj(i64 %a) {
+  %z = call i64 @llvm.hexagon.A2.vconj(i64 %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = vconj(r1:0):sat
+
+; Vector complex rotate
+declare i64 @llvm.hexagon.S2.vcrotate(i64, i32)
+define i64 @S2_vcrotate(i64 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.S2.vcrotate(i64 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vcrotate(r1:0, r2)
+
+; Vector reduce complex multiply real or imaginary
+declare i64 @llvm.hexagon.M2.vrcmpyi.s0(i64, i64)
+define i64 @M2_vrcmpyi_s0(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.vrcmpyi.s0(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrcmpyi(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.M2.vrcmpyr.s0(i64, i64)
+define i64 @M2_vrcmpyr_s0(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.vrcmpyr.s0(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrcmpyr(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.M2.vrcmpyi.s0c(i64, i64)
+define i64 @M2_vrcmpyi_s0c(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.vrcmpyi.s0c(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrcmpyi(r1:0, r3:2*)
+
+declare i64 @llvm.hexagon.M2.vrcmpyr.s0c(i64, i64)
+define i64 @M2_vrcmpyr_s0c(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.vrcmpyr.s0c(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrcmpyr(r1:0, r3:2*)
+
+declare i64 @llvm.hexagon.M2.vrcmaci.s0(i64, i64, i64)
+define i64 @M2_vrcmaci_s0(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M2.vrcmaci.s0(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vrcmpyi(r3:2, r5:4)
+
+declare i64 @llvm.hexagon.M2.vrcmacr.s0(i64, i64, i64)
+define i64 @M2_vrcmacr_s0(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M2.vrcmacr.s0(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vrcmpyr(r3:2, r5:4)
+
+declare i64 @llvm.hexagon.M2.vrcmaci.s0c(i64, i64, i64)
+define i64 @M2_vrcmaci_s0c(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M2.vrcmaci.s0c(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vrcmpyi(r3:2, r5:4*)
+
+declare i64 @llvm.hexagon.M2.vrcmacr.s0c(i64, i64, i64)
+define i64 @M2_vrcmacr_s0c(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M2.vrcmacr.s0c(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vrcmpyr(r3:2, r5:4*)
+
+; Vector reduce complex rotate
+declare i64 @llvm.hexagon.S4.vrcrotate(i64, i32, i32)
+define i64 @S4_vrcrotate(i64 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.S4.vrcrotate(i64 %a, i32 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrcrotate(r1:0, r2, #0)
+
+declare i64 @llvm.hexagon.S4.vrcrotate.acc(i64, i64, i32, i32)
+define i64 @S4_vrcrotate_acc(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S4.vrcrotate.acc(i64 %a, i64 %b, i32 %c, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 += vrcrotate(r3:2, r4, #0)
diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll b/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll
new file mode 100644
index 000000000000..aef8127d668c
--- /dev/null
+++ b/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll
@@ -0,0 +1,388 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s
+; Hexagon Programmer's Reference Manual 11.10.4 XTYPE/FP
+
+; Floating point addition
+declare float @llvm.hexagon.F2.sfadd(float, float)
+define float @F2_sfadd(float %a, float %b) {
+  %z = call float @llvm.hexagon.F2.sfadd(float %a, float %b)
+  ret float %z
+}
+; CHECK: r0 = sfadd(r0, r1)
+
+; Classify floating-point value
+declare i32 @llvm.hexagon.F2.sfclass(float, i32)
+define i32 @F2_sfclass(float %a) {
+  %z = call i32 @llvm.hexagon.F2.sfclass(float %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = sfclass(r0, #0)
+
+declare i32 @llvm.hexagon.F2.dfclass(double, i32)
+define i32 @F2_dfclass(double %a) {
+  %z = call i32 @llvm.hexagon.F2.dfclass(double %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = dfclass(r1:0, #0)
+
+; Compare floating-point value
+declare i32 @llvm.hexagon.F2.sfcmpge(float, float)
+define i32 @F2_sfcmpge(float %a, float %b) {
+  %z = call i32 @llvm.hexagon.F2.sfcmpge(float %a, float %b)
+  ret i32 %z
+}
+; CHECK: p0 = sfcmp.ge(r0, r1)
+
+declare i32 @llvm.hexagon.F2.sfcmpuo(float, float)
+define i32 @F2_sfcmpuo(float %a, float %b) {
+  %z = call i32 @llvm.hexagon.F2.sfcmpuo(float %a, float %b)
+  ret i32 %z
+}
+; CHECK: p0 = sfcmp.uo(r0, r1)
+
+declare i32 @llvm.hexagon.F2.sfcmpeq(float, float)
+define i32 @F2_sfcmpeq(float %a, float %b) {
+  %z = call i32 @llvm.hexagon.F2.sfcmpeq(float %a, float %b)
+  ret i32 %z
+}
+; CHECK: p0 = sfcmp.eq(r0, r1)
+
+declare i32 @llvm.hexagon.F2.sfcmpgt(float, float)
+define i32 @F2_sfcmpgt(float %a, float %b) {
+  %z = call i32 @llvm.hexagon.F2.sfcmpgt(float %a, float %b)
+  ret i32 %z
+}
+; CHECK: p0 = sfcmp.gt(r0, r1)
+
+declare i32 @llvm.hexagon.F2.dfcmpge(double, double)
+define i32 @F2_dfcmpge(double %a, double %b) {
+  %z = call i32 @llvm.hexagon.F2.dfcmpge(double %a, double %b)
+  ret i32 %z
+}
+; CHECK: p0 = dfcmp.ge(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.F2.dfcmpuo(double, double)
+define i32 @F2_dfcmpuo(double %a, double %b) {
+  %z = call i32 @llvm.hexagon.F2.dfcmpuo(double %a, double %b)
+  ret i32 %z
+}
+; CHECK: p0 = dfcmp.uo(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.F2.dfcmpeq(double, double)
+define i32 @F2_dfcmpeq(double %a, double %b) {
+  %z = call i32 @llvm.hexagon.F2.dfcmpeq(double %a, double %b)
+  ret i32 %z
+}
+; CHECK: p0 = dfcmp.eq(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.F2.dfcmpgt(double, double)
+define i32 @F2_dfcmpgt(double %a, double %b) {
+  %z = call i32 @llvm.hexagon.F2.dfcmpgt(double %a, double %b)
+  ret i32 %z
+}
+; CHECK: p0 = dfcmp.gt(r1:0, r3:2)
+
+; Convert floating-point value to other format
+declare double @llvm.hexagon.F2.conv.sf2df(float)
+define double @F2_conv_sf2df(float %a) {
+  %z = call double @llvm.hexagon.F2.conv.sf2df(float %a)
+  ret double %z
+}
+; CHECK:  = convert_sf2df(r0)
+
+declare float @llvm.hexagon.F2.conv.df2sf(double)
+define float @F2_conv_df2sf(double %a) {
+  %z = call float @llvm.hexagon.F2.conv.df2sf(double %a)
+  ret float %z
+}
+; CHECK: r0 = convert_df2sf(r1:0)
+
+; Convert integer to floating-point value
+declare double @llvm.hexagon.F2.conv.ud2df(i64)
+define double @F2_conv_ud2df(i64 %a) {
+  %z = call double @llvm.hexagon.F2.conv.ud2df(i64 %a)
+  ret double %z
+}
+; CHECK: r1:0 = convert_ud2df(r1:0)
+
+declare double @llvm.hexagon.F2.conv.d2df(i64)
+define double @F2_conv_d2df(i64 %a) {
+  %z = call double @llvm.hexagon.F2.conv.d2df(i64 %a)
+  ret double %z
+}
+; CHECK: r1:0 = convert_d2df(r1:0)
+
+declare double @llvm.hexagon.F2.conv.uw2df(i32)
+define double @F2_conv_uw2df(i32 %a) {
+  %z = call double @llvm.hexagon.F2.conv.uw2df(i32 %a)
+  ret double %z
+}
+; CHECK:  = convert_uw2df(r0)
+
+declare double @llvm.hexagon.F2.conv.w2df(i32)
+define double @F2_conv_w2df(i32 %a) {
+  %z = call double @llvm.hexagon.F2.conv.w2df(i32 %a)
+  ret double %z
+}
+; CHECK:  = convert_w2df(r0)
+
+declare float @llvm.hexagon.F2.conv.ud2sf(i64)
+define float @F2_conv_ud2sf(i64 %a) {
+  %z = call float @llvm.hexagon.F2.conv.ud2sf(i64 %a)
+  ret float %z
+}
+; CHECK: r0 = convert_ud2sf(r1:0)
+
+declare float @llvm.hexagon.F2.conv.d2sf(i64)
+define float @F2_conv_d2sf(i64 %a) {
+  %z = call float @llvm.hexagon.F2.conv.d2sf(i64 %a)
+  ret float %z
+}
+; CHECK: r0 = convert_d2sf(r1:0)
+
+declare float @llvm.hexagon.F2.conv.uw2sf(i32)
+define float @F2_conv_uw2sf(i32 %a) {
+  %z = call float @llvm.hexagon.F2.conv.uw2sf(i32 %a)
+  ret float %z
+}
+; CHECK: r0 = convert_uw2sf(r0)
+
+declare float @llvm.hexagon.F2.conv.w2sf(i32)
+define float @F2_conv_w2sf(i32 %a) {
+  %z = call float @llvm.hexagon.F2.conv.w2sf(i32 %a)
+  ret float %z
+}
+; CHECK: r0 = convert_w2sf(r0)
+
+; Convert floating-point value to integer
+declare i64 @llvm.hexagon.F2.conv.df2d(double)
+define i64 @F2_conv_df2d(double %a) {
+  %z = call i64 @llvm.hexagon.F2.conv.df2d(double %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = convert_df2d(r1:0)
+
+declare i64 @llvm.hexagon.F2.conv.df2ud(double)
+define i64 @F2_conv_df2ud(double %a) {
+  %z = call i64 @llvm.hexagon.F2.conv.df2ud(double %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = convert_df2ud(r1:0)
+
+declare i64 @llvm.hexagon.F2.conv.df2d.chop(double)
+define i64 @F2_conv_df2d_chop(double %a) {
+  %z = call i64 @llvm.hexagon.F2.conv.df2d.chop(double %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = convert_df2d(r1:0):chop
+
+declare i64 @llvm.hexagon.F2.conv.df2ud.chop(double)
+define i64 @F2_conv_df2ud_chop(double %a) {
+  %z = call i64 @llvm.hexagon.F2.conv.df2ud.chop(double %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = convert_df2ud(r1:0):chop
+
+declare i64 @llvm.hexagon.F2.conv.sf2ud(float)
+define i64 @F2_conv_sf2ud(float %a) {
+  %z = call i64 @llvm.hexagon.F2.conv.sf2ud(float %a)
+  ret i64 %z
+}
+; CHECK:  = convert_sf2ud(r0)
+
+declare i64 @llvm.hexagon.F2.conv.sf2d(float)
+define i64 @F2_conv_sf2d(float %a) {
+  %z = call i64 @llvm.hexagon.F2.conv.sf2d(float %a)
+  ret i64 %z
+}
+; CHECK:  = convert_sf2d(r0)
+
+declare i64 @llvm.hexagon.F2.conv.sf2d.chop(float)
+define i64 @F2_conv_sf2d_chop(float %a) {
+  %z = call i64 @llvm.hexagon.F2.conv.sf2d.chop(float %a)
+  ret i64 %z
+}
+; CHECK:  = convert_sf2d(r0):chop
+
+declare i64 @llvm.hexagon.F2.conv.sf2ud.chop(float)
+define i64 @F2_conv_sf2ud_chop(float %a) {
+  %z = call i64 @llvm.hexagon.F2.conv.sf2ud.chop(float %a)
+  ret i64 %z
+}
+; CHECK:  = convert_sf2ud(r0):chop
+
+declare i32 @llvm.hexagon.F2.conv.df2uw(double)
+define i32 @F2_conv_df2uw(double %a) {
+  %z = call i32 @llvm.hexagon.F2.conv.df2uw(double %a)
+  ret i32 %z
+}
+; CHECK: r0 = convert_df2uw(r1:0)
+
+declare i32 @llvm.hexagon.F2.conv.df2w(double)
+define i32 @F2_conv_df2w(double %a) {
+  %z = call i32 @llvm.hexagon.F2.conv.df2w(double %a)
+  ret i32 %z
+}
+; CHECK: r0 = convert_df2w(r1:0)
+
+declare i32 @llvm.hexagon.F2.conv.df2w.chop(double)
+define i32 @F2_conv_df2w_chop(double %a) {
+  %z = call i32 @llvm.hexagon.F2.conv.df2w.chop(double %a)
+  ret i32 %z
+}
+; CHECK: r0 = convert_df2w(r1:0):chop
+
+declare i32 @llvm.hexagon.F2.conv.df2uw.chop(double)
+define i32 @F2_conv_df2uw_chop(double %a) {
+  %z = call i32 @llvm.hexagon.F2.conv.df2uw.chop(double %a)
+  ret i32 %z
+}
+; CHECK: r0 = convert_df2uw(r1:0):chop
+
+declare i32 @llvm.hexagon.F2.conv.sf2uw(float)
+define i32 @F2_conv_sf2uw(float %a) {
+  %z = call i32 @llvm.hexagon.F2.conv.sf2uw(float %a)
+  ret i32 %z
+}
+; CHECK: r0 = convert_sf2uw(r0)
+
+declare i32 @llvm.hexagon.F2.conv.sf2uw.chop(float)
+define i32 @F2_conv_sf2uw_chop(float %a) {
+  %z = call i32 @llvm.hexagon.F2.conv.sf2uw.chop(float %a)
+  ret i32 %z
+}
+; CHECK: r0 = convert_sf2uw(r0):chop
+
+declare i32 @llvm.hexagon.F2.conv.sf2w(float)
+define i32 @F2_conv_sf2w(float %a) {
+  %z = call i32 @llvm.hexagon.F2.conv.sf2w(float %a)
+  ret i32 %z
+}
+; CHECK: r0 = convert_sf2w(r0)
+
+declare i32 @llvm.hexagon.F2.conv.sf2w.chop(float)
+define i32 @F2_conv_sf2w_chop(float %a) {
+  %z = call i32 @llvm.hexagon.F2.conv.sf2w.chop(float %a)
+  ret i32 %z
+}
+; CHECK: r0 = convert_sf2w(r0):chop
+
+; Floating point extreme value assistance
+declare float @llvm.hexagon.F2.sffixupr(float)
+define float @F2_sffixupr(float %a) {
+  %z = call float @llvm.hexagon.F2.sffixupr(float %a)
+  ret float %z
+}
+; CHECK: r0 = sffixupr(r0)
+
+declare float @llvm.hexagon.F2.sffixupn(float, float)
+define float @F2_sffixupn(float %a, float %b) {
+  %z = call float @llvm.hexagon.F2.sffixupn(float %a, float %b)
+  ret float %z
+}
+; CHECK: r0 = sffixupn(r0, r1)
+
+declare float @llvm.hexagon.F2.sffixupd(float, float)
+define float @F2_sffixupd(float %a, float %b) {
+  %z = call float @llvm.hexagon.F2.sffixupd(float %a, float %b)
+  ret float %z
+}
+; CHECK: r0 = sffixupd(r0, r1)
+
+; Floating point fused multiply-add
+declare float @llvm.hexagon.F2.sffma(float, float, float)
+define float @F2_sffma(float %a, float %b, float %c) {
+  %z = call float @llvm.hexagon.F2.sffma(float %a, float %b, float %c)
+  ret float %z
+}
+; CHECK: r0 += sfmpy(r1, r2)
+
+declare float @llvm.hexagon.F2.sffms(float, float, float)
+define float @F2_sffms(float %a, float %b, float %c) {
+  %z = call float @llvm.hexagon.F2.sffms(float %a, float %b, float %c)
+  ret float %z
+}
+; CHECK: r0 -= sfmpy(r1, r2)
+
+; Floating point fused multiply-add with scaling
+declare float @llvm.hexagon.F2.sffma.sc(float, float, float, i32)
+define float @F2_sffma_sc(float %a, float %b, float %c, i32 %d) {
+  %z = call float @llvm.hexagon.F2.sffma.sc(float %a, float %b, float %c, i32 %d)
+  ret float %z
+}
+; CHECK: r0 += sfmpy(r1, r2, p0):scale
+
+; Floating point fused multiply-add for library routines
+declare float @llvm.hexagon.F2.sffma.lib(float, float, float)
+define float @F2_sffma_lib(float %a, float %b, float %c) {
+  %z = call float @llvm.hexagon.F2.sffma.lib(float %a, float %b, float %c)
+  ret float %z
+}
+; CHECK: r0 += sfmpy(r1, r2):lib
+
+declare float @llvm.hexagon.F2.sffms.lib(float, float, float)
+define float @F2_sffms_lib(float %a, float %b, float %c) {
+  %z = call float @llvm.hexagon.F2.sffms.lib(float %a, float %b, float %c)
+  ret float %z
+}
+; CHECK: r0 -= sfmpy(r1, r2):lib
+
+; Create floating-point constant
+declare float @llvm.hexagon.F2.sfimm.p(i32)
+define float @F2_sfimm_p() {
+  %z = call float @llvm.hexagon.F2.sfimm.p(i32 0)
+  ret float %z
+}
+; CHECK: r0 = sfmake(#0):pos
+
+declare float @llvm.hexagon.F2.sfimm.n(i32)
+define float @F2_sfimm_n() {
+  %z = call float @llvm.hexagon.F2.sfimm.n(i32 0)
+  ret float %z
+} 
+; CHECK: r0 = sfmake(#0):neg
+
+declare double @llvm.hexagon.F2.dfimm.p(i32)
+define double @F2_dfimm_p() {
+  %z = call double @llvm.hexagon.F2.dfimm.p(i32 0)
+  ret double %z
+}
+; CHECK: r1:0 = dfmake(#0):pos
+
+declare double @llvm.hexagon.F2.dfimm.n(i32)
+define double @F2_dfimm_n() {
+  %z = call double @llvm.hexagon.F2.dfimm.n(i32 0)
+  ret double %z
+}
+; CHECK: r1:0 = dfmake(#0):neg
+
+; Floating point maximum
+declare float @llvm.hexagon.F2.sfmax(float, float)
+define float @F2_sfmax(float %a, float %b) {
+  %z = call float @llvm.hexagon.F2.sfmax(float %a, float %b)
+  ret float %z
+}
+; CHECK: r0 = sfmax(r0, r1)
+
+; Floating point minimum
+declare float @llvm.hexagon.F2.sfmin(float, float)
+define float @F2_sfmin(float %a, float %b) {
+  %z = call float @llvm.hexagon.F2.sfmin(float %a, float %b)
+  ret float %z
+}
+; CHECK: r0 = sfmin(r0, r1)
+
+; Floating point multiply
+declare float @llvm.hexagon.F2.sfmpy(float, float)
+define float @F2_sfmpy(float %a, float %b) {
+  %z = call float @llvm.hexagon.F2.sfmpy(float %a, float %b)
+  ret float %z
+}
+; CHECK: r0 = sfmpy(r0, r1)
+
+; Floating point subtraction
+declare float @llvm.hexagon.F2.sfsub(float, float)
+define float @F2_sfsub(float %a, float %b) {
+  %z = call float @llvm.hexagon.F2.sfsub(float %a, float %b)
+  ret float %z
+}
+; CHECK: r0 = sfsub(r0, r1)
diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll b/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll
new file mode 100644
index 000000000000..6409e4e10ca2
--- /dev/null
+++ b/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll
@@ -0,0 +1,1525 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s
+; Hexagon Programmer's Reference Manual 11.10.5 XTYPE/MPY
+
+; Multiply and use lower result
+declare i32 @llvm.hexagon.M4.mpyrr.addi(i32, i32, i32)
+define i32 @M4_mpyrr_addi(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M4.mpyrr.addi(i32 0, i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(#0, mpyi(r0, r1))
+
+declare i32 @llvm.hexagon.M4.mpyri.addi(i32, i32, i32)
+define i32 @M4_mpyri_addi(i32 %a) {
+  %z = call i32 @llvm.hexagon.M4.mpyri.addi(i32 0, i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = add(#0, mpyi(r0, #0))
+
+declare i32 @llvm.hexagon.M4.mpyri.addr.u2(i32, i32, i32)
+define i32 @M4_mpyri_addr_u2(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M4.mpyri.addr.u2(i32 %a, i32 0, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0, mpyi(#0, r1))
+
+declare i32 @llvm.hexagon.M4.mpyri.addr(i32, i32, i32)
+define i32 @M4_mpyri_addr(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M4.mpyri.addr(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = add(r0, mpyi(r1, #0))
+
+declare i32 @llvm.hexagon.M4.mpyrr.addr(i32, i32, i32)
+define i32 @M4_mpyrr_addr(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M4.mpyrr.addr(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r1 = add(r0, mpyi(r1, r2))
+
+; Vector multiply word by signed half (32x16)
+declare i64 @llvm.hexagon.M2.mmpyl.s0(i64, i64)
+define i64 @M2_mmpyl_s0(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyl.s0(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpyweh(r1:0, r3:2):sat
+
+declare i64 @llvm.hexagon.M2.mmpyl.s1(i64, i64)
+define i64 @M2_mmpyl_s1(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyl.s1(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpyweh(r1:0, r3:2):<<1:sat
+
+declare i64 @llvm.hexagon.M2.mmpyh.s0(i64, i64)
+define i64 @M2_mmpyh_s0(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyh.s0(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpywoh(r1:0, r3:2):sat
+
+declare i64 @llvm.hexagon.M2.mmpyh.s1(i64, i64)
+define i64 @M2_mmpyh_s1(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyh.s1(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpywoh(r1:0, r3:2):<<1:sat
+
+declare i64 @llvm.hexagon.M2.mmpyl.rs0(i64, i64)
+define i64 @M2_mmpyl_rs0(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyl.rs0(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpyweh(r1:0, r3:2):rnd:sat
+
+declare i64 @llvm.hexagon.M2.mmpyl.rs1(i64, i64)
+define i64 @M2_mmpyl_rs1(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyl.rs1(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpyweh(r1:0, r3:2):<<1:rnd:sat
+
+declare i64 @llvm.hexagon.M2.mmpyh.rs0(i64, i64)
+define i64 @M2_mmpyh_rs0(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyh.rs0(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpywoh(r1:0, r3:2):rnd:sat
+
+declare i64 @llvm.hexagon.M2.mmpyh.rs1(i64, i64)
+define i64 @M2_mmpyh_rs1(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyh.rs1(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpywoh(r1:0, r3:2):<<1:rnd:sat
+
+; Vector multiply word by unsigned half (32x16)
+declare i64 @llvm.hexagon.M2.mmpyul.s0(i64, i64)
+define i64 @M2_mmpyul_s0(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyul.s0(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpyweuh(r1:0, r3:2):sat
+
+declare i64 @llvm.hexagon.M2.mmpyul.s1(i64, i64)
+define i64 @M2_mmpyul_s1(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyul.s1(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpyweuh(r1:0, r3:2):<<1:sat
+
+declare i64 @llvm.hexagon.M2.mmpyuh.s0(i64, i64)
+define i64 @M2_mmpyuh_s0(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyuh.s0(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpywouh(r1:0, r3:2):sat
+
+declare i64 @llvm.hexagon.M2.mmpyuh.s1(i64, i64)
+define i64 @M2_mmpyuh_s1(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyuh.s1(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpywouh(r1:0, r3:2):<<1:sat
+
+declare i64 @llvm.hexagon.M2.mmpyul.rs0(i64, i64)
+define i64 @M2_mmpyul_rs0(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyul.rs0(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpyweuh(r1:0, r3:2):rnd:sat
+
+declare i64 @llvm.hexagon.M2.mmpyul.rs1(i64, i64)
+define i64 @M2_mmpyul_rs1(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyul.rs1(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpyweuh(r1:0, r3:2):<<1:rnd:sat
+
+declare i64 @llvm.hexagon.M2.mmpyuh.rs0(i64, i64)
+define i64 @M2_mmpyuh_rs0(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyuh.rs0(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpywouh(r1:0, r3:2):rnd:sat
+
+declare i64 @llvm.hexagon.M2.mmpyuh.rs1(i64, i64)
+define i64 @M2_mmpyuh_rs1(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.mmpyuh.rs1(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpywouh(r1:0, r3:2):<<1:rnd:sat
+
+; Multiply signed halfwords
+declare i64 @llvm.hexagon.M2.mpyd.ll.s0(i32, i32)
+define i64 @M2_mpyd_ll_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.ll.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.l, r1.l)
+
+declare i64 @llvm.hexagon.M2.mpyd.ll.s1(i32, i32)
+define i64 @M2_mpyd_ll_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.ll.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.l, r1.l):<<1
+
+declare i64 @llvm.hexagon.M2.mpyd.lh.s0(i32, i32)
+define i64 @M2_mpyd_lh_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.lh.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.l, r1.h)
+
+declare i64 @llvm.hexagon.M2.mpyd.lh.s1(i32, i32)
+define i64 @M2_mpyd_lh_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.lh.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.l, r1.h):<<1
+
+declare i64 @llvm.hexagon.M2.mpyd.hl.s0(i32, i32)
+define i64 @M2_mpyd_hl_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.hl.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.h, r1.l)
+
+declare i64 @llvm.hexagon.M2.mpyd.hl.s1(i32, i32)
+define i64 @M2_mpyd_hl_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.hl.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.h, r1.l):<<1
+
+declare i64 @llvm.hexagon.M2.mpyd.hh.s0(i32, i32)
+define i64 @M2_mpyd_hh_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.hh.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.h, r1.h)
+
+declare i64 @llvm.hexagon.M2.mpyd.hh.s1(i32, i32)
+define i64 @M2_mpyd_hh_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.hh.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.h, r1.h):<<1
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.ll.s0(i32, i32)
+define i64 @M2_mpyd_rnd_ll_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.rnd.ll.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.l, r1.l):rnd
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.ll.s1(i32, i32)
+define i64 @M2_mpyd_rnd_ll_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.rnd.ll.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.l, r1.l):<<1:rnd
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.lh.s0(i32, i32)
+define i64 @M2_mpyd_rnd_lh_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.rnd.lh.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.l, r1.h):rnd
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.lh.s1(i32, i32)
+define i64 @M2_mpyd_rnd_lh_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.rnd.lh.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.l, r1.h):<<1:rnd
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.hl.s0(i32, i32)
+define i64 @M2_mpyd_rnd_hl_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.rnd.hl.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.h, r1.l):rnd
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.hl.s1(i32, i32)
+define i64 @M2_mpyd_rnd_hl_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.rnd.hl.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.h, r1.l):<<1:rnd
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.hh.s0(i32, i32)
+define i64 @M2_mpyd_rnd_hh_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.rnd.hh.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.h, r1.h):rnd
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.hh.s1(i32, i32)
+define i64 @M2_mpyd_rnd_hh_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.rnd.hh.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0.h, r1.h):<<1:rnd
+
+declare i64 @llvm.hexagon.M2.mpyd.acc.ll.s0(i64, i32, i32)
+define i64 @M2_mpyd_acc_ll_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.acc.ll.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpy(r2.l, r3.l)
+
+declare i64 @llvm.hexagon.M2.mpyd.acc.ll.s1(i64, i32, i32)
+define i64 @M2_mpyd_acc_ll_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.acc.ll.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpy(r2.l, r3.l):<<1
+
+declare i64 @llvm.hexagon.M2.mpyd.acc.lh.s0(i64, i32, i32)
+define i64 @M2_mpyd_acc_lh_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.acc.lh.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpy(r2.l, r3.h)
+
+declare i64 @llvm.hexagon.M2.mpyd.acc.lh.s1(i64, i32, i32)
+define i64 @M2_mpyd_acc_lh_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.acc.lh.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpy(r2.l, r3.h):<<1
+
+declare i64 @llvm.hexagon.M2.mpyd.acc.hl.s0(i64, i32, i32)
+define i64 @M2_mpyd_acc_hl_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.acc.hl.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpy(r2.h, r3.l)
+
+declare i64 @llvm.hexagon.M2.mpyd.acc.hl.s1(i64, i32, i32)
+define i64 @M2_mpyd_acc_hl_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.acc.hl.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpy(r2.h, r3.l):<<1
+
+declare i64 @llvm.hexagon.M2.mpyd.acc.hh.s0(i64, i32, i32)
+define i64 @M2_mpyd_acc_hh_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.acc.hh.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpy(r2.h, r3.h)
+
+declare i64 @llvm.hexagon.M2.mpyd.acc.hh.s1(i64, i32, i32)
+define i64 @M2_mpyd_acc_hh_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.acc.hh.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpy(r2.h, r3.h):<<1
+
+declare i64 @llvm.hexagon.M2.mpyd.nac.ll.s0(i64, i32, i32)
+define i64 @M2_mpyd_nac_ll_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.nac.ll.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpy(r2.l, r3.l)
+
+declare i64 @llvm.hexagon.M2.mpyd.nac.ll.s1(i64, i32, i32)
+define i64 @M2_mpyd_nac_ll_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.nac.ll.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpy(r2.l, r3.l):<<1
+
+declare i64 @llvm.hexagon.M2.mpyd.nac.lh.s0(i64, i32, i32)
+define i64 @M2_mpyd_nac_lh_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.nac.lh.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpy(r2.l, r3.h)
+
+declare i64 @llvm.hexagon.M2.mpyd.nac.lh.s1(i64, i32, i32)
+define i64 @M2_mpyd_nac_lh_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.nac.lh.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpy(r2.l, r3.h):<<1
+
+declare i64 @llvm.hexagon.M2.mpyd.nac.hl.s0(i64, i32, i32)
+define i64 @M2_mpyd_nac_hl_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.nac.hl.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpy(r2.h, r3.l)
+
+declare i64 @llvm.hexagon.M2.mpyd.nac.hl.s1(i64, i32, i32)
+define i64 @M2_mpyd_nac_hl_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.nac.hl.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpy(r2.h, r3.l):<<1
+
+declare i64 @llvm.hexagon.M2.mpyd.nac.hh.s0(i64, i32, i32)
+define i64 @M2_mpyd_nac_hh_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.nac.hh.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpy(r2.h, r3.h)
+
+declare i64 @llvm.hexagon.M2.mpyd.nac.hh.s1(i64, i32, i32)
+define i64 @M2_mpyd_nac_hh_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyd.nac.hh.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpy(r2.h, r3.h):<<1
+
+declare i32 @llvm.hexagon.M2.mpy.ll.s0(i32, i32)
+define i32 @M2_mpy_ll_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.ll.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.l, r1.l)
+
+declare i32 @llvm.hexagon.M2.mpy.ll.s1(i32, i32)
+define i32 @M2_mpy_ll_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.ll.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.l, r1.l):<<1
+
+declare i32 @llvm.hexagon.M2.mpy.lh.s0(i32, i32)
+define i32 @M2_mpy_lh_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.lh.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.l, r1.h)
+
+declare i32 @llvm.hexagon.M2.mpy.lh.s1(i32, i32)
+define i32 @M2_mpy_lh_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.lh.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.l, r1.h):<<1
+
+declare i32 @llvm.hexagon.M2.mpy.hl.s0(i32, i32)
+define i32 @M2_mpy_hl_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.hl.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.h, r1.l)
+
+declare i32 @llvm.hexagon.M2.mpy.hl.s1(i32, i32)
+define i32 @M2_mpy_hl_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.hl.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.h, r1.l):<<1
+
+declare i32 @llvm.hexagon.M2.mpy.hh.s0(i32, i32)
+define i32 @M2_mpy_hh_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.hh.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.h, r1.h)
+
+declare i32 @llvm.hexagon.M2.mpy.hh.s1(i32, i32)
+define i32 @M2_mpy_hh_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.hh.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.h, r1.h):<<1
+
+declare i32 @llvm.hexagon.M2.mpy.sat.ll.s0(i32, i32)
+define i32 @M2_mpy_sat_ll_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.ll.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.l, r1.l):sat
+
+declare i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32, i32)
+define i32 @M2_mpy_sat_ll_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.l, r1.l):<<1:sat
+
+declare i32 @llvm.hexagon.M2.mpy.sat.lh.s0(i32, i32)
+define i32 @M2_mpy_sat_lh_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.lh.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.l, r1.h):sat
+
+declare i32 @llvm.hexagon.M2.mpy.sat.lh.s1(i32, i32)
+define i32 @M2_mpy_sat_lh_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.lh.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.l, r1.h):<<1:sat
+
+declare i32 @llvm.hexagon.M2.mpy.sat.hl.s0(i32, i32)
+define i32 @M2_mpy_sat_hl_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.hl.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.h, r1.l):sat
+
+declare i32 @llvm.hexagon.M2.mpy.sat.hl.s1(i32, i32)
+define i32 @M2_mpy_sat_hl_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.hl.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.h, r1.l):<<1:sat
+
+declare i32 @llvm.hexagon.M2.mpy.sat.hh.s0(i32, i32)
+define i32 @M2_mpy_sat_hh_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.hh.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.h, r1.h):sat
+
+declare i32 @llvm.hexagon.M2.mpy.sat.hh.s1(i32, i32)
+define i32 @M2_mpy_sat_hh_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.hh.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.h, r1.h):<<1:sat
+
+declare i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s0(i32, i32)
+define i32 @M2_mpy_sat_rnd_ll_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.l, r1.l):rnd:sat
+
+declare i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s1(i32, i32)
+define i32 @M2_mpy_sat_rnd_ll_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.l, r1.l):<<1:rnd:sat
+
+declare i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s0(i32, i32)
+define i32 @M2_mpy_sat_rnd_lh_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.l, r1.h):rnd:sat
+
+declare i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s1(i32, i32)
+define i32 @M2_mpy_sat_rnd_lh_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.l, r1.h):<<1:rnd:sat
+
+declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s0(i32, i32)
+define i32 @M2_mpy_sat_rnd_hl_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.h, r1.l):rnd:sat
+
+declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s1(i32, i32)
+define i32 @M2_mpy_sat_rnd_hl_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.h, r1.l):<<1:rnd:sat
+
+declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s0(i32, i32)
+define i32 @M2_mpy_sat_rnd_hh_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.h, r1.h):rnd:sat
+
+declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s1(i32, i32)
+define i32 @M2_mpy_sat_rnd_hh_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0.h, r1.h):<<1:rnd:sat
+
+declare i32 @llvm.hexagon.M2.mpy.acc.ll.s0(i32, i32, i32)
+define i32 @M2_mpy_acc_ll_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.ll.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.l, r2.l)
+
+declare i32 @llvm.hexagon.M2.mpy.acc.ll.s1(i32, i32, i32)
+define i32 @M2_mpy_acc_ll_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.ll.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.l, r2.l):<<1
+
+declare i32 @llvm.hexagon.M2.mpy.acc.lh.s0(i32, i32, i32)
+define i32 @M2_mpy_acc_lh_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.lh.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.l, r2.h)
+
+declare i32 @llvm.hexagon.M2.mpy.acc.lh.s1(i32, i32, i32)
+define i32 @M2_mpy_acc_lh_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.lh.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.l, r2.h):<<1
+
+declare i32 @llvm.hexagon.M2.mpy.acc.hl.s0(i32, i32, i32)
+define i32 @M2_mpy_acc_hl_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.hl.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.h, r2.l)
+
+declare i32 @llvm.hexagon.M2.mpy.acc.hl.s1(i32, i32, i32)
+define i32 @M2_mpy_acc_hl_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.hl.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.h, r2.l):<<1
+
+declare i32 @llvm.hexagon.M2.mpy.acc.hh.s0(i32, i32, i32)
+define i32 @M2_mpy_acc_hh_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.hh.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.h, r2.h)
+
+declare i32 @llvm.hexagon.M2.mpy.acc.hh.s1(i32, i32, i32)
+define i32 @M2_mpy_acc_hh_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.hh.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.h, r2.h):<<1
+
+declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32, i32, i32)
+define i32 @M2_mpy_acc_sat_ll_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.l, r2.l):sat
+
+declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32, i32, i32)
+define i32 @M2_mpy_acc_sat_ll_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.l, r2.l):<<1:sat
+
+declare i32 @llvm.hexagon.M2.mpy.acc.sat.lh.s0(i32, i32, i32)
+define i32 @M2_mpy_acc_sat_lh_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.lh.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.l, r2.h):sat
+
+declare i32 @llvm.hexagon.M2.mpy.acc.sat.lh.s1(i32, i32, i32)
+define i32 @M2_mpy_acc_sat_lh_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.lh.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.l, r2.h):<<1:sat
+
+declare i32 @llvm.hexagon.M2.mpy.acc.sat.hl.s0(i32, i32, i32)
+define i32 @M2_mpy_acc_sat_hl_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.hl.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.h, r2.l):sat
+
+declare i32 @llvm.hexagon.M2.mpy.acc.sat.hl.s1(i32, i32, i32)
+define i32 @M2_mpy_acc_sat_hl_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.hl.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.h, r2.l):<<1:sat
+
+declare i32 @llvm.hexagon.M2.mpy.acc.sat.hh.s0(i32, i32, i32)
+define i32 @M2_mpy_acc_sat_hh_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.hh.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.h, r2.h):sat
+
+declare i32 @llvm.hexagon.M2.mpy.acc.sat.hh.s1(i32, i32, i32)
+define i32 @M2_mpy_acc_sat_hh_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.hh.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1.h, r2.h):<<1:sat
+
+declare i32 @llvm.hexagon.M2.mpy.nac.ll.s0(i32, i32, i32)
+define i32 @M2_mpy_nac_ll_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.ll.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.l, r2.l)
+
+declare i32 @llvm.hexagon.M2.mpy.nac.ll.s1(i32, i32, i32)
+define i32 @M2_mpy_nac_ll_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.ll.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.l, r2.l):<<1
+
+declare i32 @llvm.hexagon.M2.mpy.nac.lh.s0(i32, i32, i32)
+define i32 @M2_mpy_nac_lh_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.lh.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.l, r2.h)
+
+declare i32 @llvm.hexagon.M2.mpy.nac.lh.s1(i32, i32, i32)
+define i32 @M2_mpy_nac_lh_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.lh.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.l, r2.h):<<1
+
+declare i32 @llvm.hexagon.M2.mpy.nac.hl.s0(i32, i32, i32)
+define i32 @M2_mpy_nac_hl_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.hl.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.h, r2.l)
+
+declare i32 @llvm.hexagon.M2.mpy.nac.hl.s1(i32, i32, i32)
+define i32 @M2_mpy_nac_hl_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.hl.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.h, r2.l):<<1
+
+declare i32 @llvm.hexagon.M2.mpy.nac.hh.s0(i32, i32, i32)
+define i32 @M2_mpy_nac_hh_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.hh.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.h, r2.h)
+
+declare i32 @llvm.hexagon.M2.mpy.nac.hh.s1(i32, i32, i32)
+define i32 @M2_mpy_nac_hh_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.hh.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.h, r2.h):<<1
+
+declare i32 @llvm.hexagon.M2.mpy.nac.sat.ll.s0(i32, i32, i32)
+define i32 @M2_mpy_nac_sat_ll_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.ll.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.l, r2.l):sat
+
+declare i32 @llvm.hexagon.M2.mpy.nac.sat.ll.s1(i32, i32, i32)
+define i32 @M2_mpy_nac_sat_ll_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.ll.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.l, r2.l):<<1:sat
+
+declare i32 @llvm.hexagon.M2.mpy.nac.sat.lh.s0(i32, i32, i32)
+define i32 @M2_mpy_nac_sat_lh_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.lh.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.l, r2.h):sat
+
+declare i32 @llvm.hexagon.M2.mpy.nac.sat.lh.s1(i32, i32, i32)
+define i32 @M2_mpy_nac_sat_lh_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.lh.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.l, r2.h):<<1:sat
+
+declare i32 @llvm.hexagon.M2.mpy.nac.sat.hl.s0(i32, i32, i32)
+define i32 @M2_mpy_nac_sat_hl_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.hl.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.h, r2.l):sat
+
+declare i32 @llvm.hexagon.M2.mpy.nac.sat.hl.s1(i32, i32, i32)
+define i32 @M2_mpy_nac_sat_hl_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.hl.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.h, r2.l):<<1:sat
+
+declare i32 @llvm.hexagon.M2.mpy.nac.sat.hh.s0(i32, i32, i32)
+define i32 @M2_mpy_nac_sat_hh_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.hh.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.h, r2.h):sat
+
+declare i32 @llvm.hexagon.M2.mpy.nac.sat.hh.s1(i32, i32, i32)
+define i32 @M2_mpy_nac_sat_hh_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.hh.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1.h, r2.h):<<1:sat
+
+; Multiply unsigned halfwords
+declare i64 @llvm.hexagon.M2.mpyud.ll.s0(i32, i32)
+define i64 @M2_mpyud_ll_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.ll.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpyu(r0.l, r1.l)
+
+declare i64 @llvm.hexagon.M2.mpyud.ll.s1(i32, i32)
+define i64 @M2_mpyud_ll_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.ll.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpyu(r0.l, r1.l):<<1
+
+declare i64 @llvm.hexagon.M2.mpyud.lh.s0(i32, i32)
+define i64 @M2_mpyud_lh_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.lh.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpyu(r0.l, r1.h)
+
+declare i64 @llvm.hexagon.M2.mpyud.lh.s1(i32, i32)
+define i64 @M2_mpyud_lh_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.lh.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpyu(r0.l, r1.h):<<1
+
+declare i64 @llvm.hexagon.M2.mpyud.hl.s0(i32, i32)
+define i64 @M2_mpyud_hl_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.hl.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpyu(r0.h, r1.l)
+
+declare i64 @llvm.hexagon.M2.mpyud.hl.s1(i32, i32)
+define i64 @M2_mpyud_hl_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.hl.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpyu(r0.h, r1.l):<<1
+
+declare i64 @llvm.hexagon.M2.mpyud.hh.s0(i32, i32)
+define i64 @M2_mpyud_hh_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.hh.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpyu(r0.h, r1.h)
+
+declare i64 @llvm.hexagon.M2.mpyud.hh.s1(i32, i32)
+define i64 @M2_mpyud_hh_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.hh.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpyu(r0.h, r1.h):<<1
+
+declare i64 @llvm.hexagon.M2.mpyud.acc.ll.s0(i64, i32, i32)
+define i64 @M2_mpyud_acc_ll_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.acc.ll.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpyu(r2.l, r3.l)
+
+declare i64 @llvm.hexagon.M2.mpyud.acc.ll.s1(i64, i32, i32)
+define i64 @M2_mpyud_acc_ll_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.acc.ll.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpyu(r2.l, r3.l):<<1
+
+declare i64 @llvm.hexagon.M2.mpyud.acc.lh.s0(i64, i32, i32)
+define i64 @M2_mpyud_acc_lh_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.acc.lh.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpyu(r2.l, r3.h)
+
+declare i64 @llvm.hexagon.M2.mpyud.acc.lh.s1(i64, i32, i32)
+define i64 @M2_mpyud_acc_lh_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.acc.lh.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpyu(r2.l, r3.h):<<1
+
+declare i64 @llvm.hexagon.M2.mpyud.acc.hl.s0(i64, i32, i32)
+define i64 @M2_mpyud_acc_hl_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.acc.hl.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpyu(r2.h, r3.l)
+
+declare i64 @llvm.hexagon.M2.mpyud.acc.hl.s1(i64, i32, i32)
+define i64 @M2_mpyud_acc_hl_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.acc.hl.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpyu(r2.h, r3.l):<<1
+
+declare i64 @llvm.hexagon.M2.mpyud.acc.hh.s0(i64, i32, i32)
+define i64 @M2_mpyud_acc_hh_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.acc.hh.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpyu(r2.h, r3.h)
+
+declare i64 @llvm.hexagon.M2.mpyud.acc.hh.s1(i64, i32, i32)
+define i64 @M2_mpyud_acc_hh_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.acc.hh.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpyu(r2.h, r3.h):<<1
+
+declare i64 @llvm.hexagon.M2.mpyud.nac.ll.s0(i64, i32, i32)
+define i64 @M2_mpyud_nac_ll_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.nac.ll.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpyu(r2.l, r3.l)
+
+declare i64 @llvm.hexagon.M2.mpyud.nac.ll.s1(i64, i32, i32)
+define i64 @M2_mpyud_nac_ll_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.nac.ll.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpyu(r2.l, r3.l):<<1
+
+declare i64 @llvm.hexagon.M2.mpyud.nac.lh.s0(i64, i32, i32)
+define i64 @M2_mpyud_nac_lh_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.nac.lh.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpyu(r2.l, r3.h)
+
+declare i64 @llvm.hexagon.M2.mpyud.nac.lh.s1(i64, i32, i32)
+define i64 @M2_mpyud_nac_lh_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.nac.lh.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpyu(r2.l, r3.h):<<1
+
+declare i64 @llvm.hexagon.M2.mpyud.nac.hl.s0(i64, i32, i32)
+define i64 @M2_mpyud_nac_hl_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.nac.hl.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpyu(r2.h, r3.l)
+
+declare i64 @llvm.hexagon.M2.mpyud.nac.hl.s1(i64, i32, i32)
+define i64 @M2_mpyud_nac_hl_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.nac.hl.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpyu(r2.h, r3.l):<<1
+
+declare i64 @llvm.hexagon.M2.mpyud.nac.hh.s0(i64, i32, i32)
+define i64 @M2_mpyud_nac_hh_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.nac.hh.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpyu(r2.h, r3.h)
+
+declare i64 @llvm.hexagon.M2.mpyud.nac.hh.s1(i64, i32, i32)
+define i64 @M2_mpyud_nac_hh_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.mpyud.nac.hh.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpyu(r2.h, r3.h):<<1
+
+declare i32 @llvm.hexagon.M2.mpyu.ll.s0(i32, i32)
+define i32 @M2_mpyu_ll_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.ll.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpyu(r0.l, r1.l)
+
+declare i32 @llvm.hexagon.M2.mpyu.ll.s1(i32, i32)
+define i32 @M2_mpyu_ll_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.ll.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpyu(r0.l, r1.l):<<1
+
+declare i32 @llvm.hexagon.M2.mpyu.lh.s0(i32, i32)
+define i32 @M2_mpyu_lh_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.lh.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpyu(r0.l, r1.h)
+
+declare i32 @llvm.hexagon.M2.mpyu.lh.s1(i32, i32)
+define i32 @M2_mpyu_lh_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.lh.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpyu(r0.l, r1.h):<<1
+
+declare i32 @llvm.hexagon.M2.mpyu.hl.s0(i32, i32)
+define i32 @M2_mpyu_hl_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.hl.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpyu(r0.h, r1.l)
+
+declare i32 @llvm.hexagon.M2.mpyu.hl.s1(i32, i32)
+define i32 @M2_mpyu_hl_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.hl.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpyu(r0.h, r1.l):<<1
+
+declare i32 @llvm.hexagon.M2.mpyu.hh.s0(i32, i32)
+define i32 @M2_mpyu_hh_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.hh.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpyu(r0.h, r1.h)
+
+declare i32 @llvm.hexagon.M2.mpyu.hh.s1(i32, i32)
+define i32 @M2_mpyu_hh_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.hh.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpyu(r0.h, r1.h):<<1
+
+declare i32 @llvm.hexagon.M2.mpyu.acc.ll.s0(i32, i32, i32)
+define i32 @M2_mpyu_acc_ll_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.acc.ll.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpyu(r1.l, r2.l)
+
+declare i32 @llvm.hexagon.M2.mpyu.acc.ll.s1(i32, i32, i32)
+define i32 @M2_mpyu_acc_ll_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.acc.ll.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpyu(r1.l, r2.l):<<1
+
+declare i32 @llvm.hexagon.M2.mpyu.acc.lh.s0(i32, i32, i32)
+define i32 @M2_mpyu_acc_lh_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.acc.lh.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpyu(r1.l, r2.h)
+
+declare i32 @llvm.hexagon.M2.mpyu.acc.lh.s1(i32, i32, i32)
+define i32 @M2_mpyu_acc_lh_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.acc.lh.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpyu(r1.l, r2.h):<<1
+
+declare i32 @llvm.hexagon.M2.mpyu.acc.hl.s0(i32, i32, i32)
+define i32 @M2_mpyu_acc_hl_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.acc.hl.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpyu(r1.h, r2.l)
+
+declare i32 @llvm.hexagon.M2.mpyu.acc.hl.s1(i32, i32, i32)
+define i32 @M2_mpyu_acc_hl_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.acc.hl.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpyu(r1.h, r2.l):<<1
+
+declare i32 @llvm.hexagon.M2.mpyu.acc.hh.s0(i32, i32, i32)
+define i32 @M2_mpyu_acc_hh_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.acc.hh.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpyu(r1.h, r2.h)
+
+declare i32 @llvm.hexagon.M2.mpyu.acc.hh.s1(i32, i32, i32)
+define i32 @M2_mpyu_acc_hh_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.acc.hh.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpyu(r1.h, r2.h):<<1
+
+declare i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32, i32, i32)
+define i32 @M2_mpyu_nac_ll_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpyu(r1.l, r2.l)
+
+declare i32 @llvm.hexagon.M2.mpyu.nac.ll.s1(i32, i32, i32)
+define i32 @M2_mpyu_nac_ll_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.nac.ll.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpyu(r1.l, r2.l):<<1
+
+declare i32 @llvm.hexagon.M2.mpyu.nac.lh.s0(i32, i32, i32)
+define i32 @M2_mpyu_nac_lh_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.nac.lh.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpyu(r1.l, r2.h)
+
+declare i32 @llvm.hexagon.M2.mpyu.nac.lh.s1(i32, i32, i32)
+define i32 @M2_mpyu_nac_lh_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.nac.lh.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpyu(r1.l, r2.h):<<1
+
+declare i32 @llvm.hexagon.M2.mpyu.nac.hl.s0(i32, i32, i32)
+define i32 @M2_mpyu_nac_hl_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.nac.hl.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpyu(r1.h, r2.l)
+
+declare i32 @llvm.hexagon.M2.mpyu.nac.hl.s1(i32, i32, i32)
+define i32 @M2_mpyu_nac_hl_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.nac.hl.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpyu(r1.h, r2.l):<<1
+
+declare i32 @llvm.hexagon.M2.mpyu.nac.hh.s0(i32, i32, i32)
+define i32 @M2_mpyu_nac_hh_s0(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.nac.hh.s0(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpyu(r1.h, r2.h)
+
+declare i32 @llvm.hexagon.M2.mpyu.nac.hh.s1(i32, i32, i32)
+define i32 @M2_mpyu_nac_hh_s1(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.nac.hh.s1(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpyu(r1.h, r2.h):<<1
+
+; Polynomial multiply words
+declare i64 @llvm.hexagon.M4.pmpyw(i32, i32)
+define i64 @M4_pmpyw(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M4.pmpyw(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = pmpyw(r0, r1)
+
+declare i64 @llvm.hexagon.M4.pmpyw.acc(i64, i32, i32)
+define i64 @M4_pmpyw_acc(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M4.pmpyw.acc(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 ^= pmpyw(r2, r3)
+
+; Vector reduce multiply word by signed half
+declare i64 @llvm.hexagon.M4.vrmpyoh.s0(i64, i64)
+define i64 @M4_vrmpyoh_s0(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M4.vrmpyoh.s0(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrmpywoh(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.M4.vrmpyoh.s1(i64, i64)
+define i64 @M4_vrmpyoh_s1(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M4.vrmpyoh.s1(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrmpywoh(r1:0, r3:2):<<1
+
+declare i64 @llvm.hexagon.M4.vrmpyeh.s0(i64, i64)
+define i64 @M4_vrmpyeh_s0(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M4.vrmpyeh.s0(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrmpyweh(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.M4.vrmpyeh.s1(i64, i64)
+define i64 @M4_vrmpyeh_s1(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M4.vrmpyeh.s1(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrmpyweh(r1:0, r3:2):<<1
+
+declare i64 @llvm.hexagon.M4.vrmpyoh.acc.s0(i64, i64, i64)
+define i64 @M4_vrmpyoh_acc_s0(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M4.vrmpyoh.acc.s0(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vrmpywoh(r3:2, r5:4)
+
+declare i64 @llvm.hexagon.M4.vrmpyoh.acc.s1(i64, i64, i64)
+define i64 @M4_vrmpyoh_acc_s1(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M4.vrmpyoh.acc.s1(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vrmpywoh(r3:2, r5:4):<<1
+
+declare i64 @llvm.hexagon.M4.vrmpyeh.acc.s0(i64, i64, i64)
+define i64 @M4_vrmpyeh_acc_s0(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M4.vrmpyeh.acc.s0(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vrmpyweh(r3:2, r5:4)
+
+declare i64 @llvm.hexagon.M4.vrmpyeh.acc.s1(i64, i64, i64)
+define i64 @M4_vrmpyeh_acc_s1(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M4.vrmpyeh.acc.s1(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vrmpyweh(r3:2, r5:4):<<1
+
+; Multiply and use upper result
+declare i32 @llvm.hexagon.M2.dpmpyss.rnd.s0(i32, i32)
+define i32 @M2_dpmpyss_rnd_s0(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.dpmpyss.rnd.s0(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0, r1):rnd
+
+declare i32 @llvm.hexagon.M2.mpyu.up(i32, i32)
+define i32 @M2_mpyu_up(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpyu.up(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpyu(r0, r1)
+
+declare i32 @llvm.hexagon.M2.mpysu.up(i32, i32)
+define i32 @M2_mpysu_up(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpysu.up(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpysu(r0, r1)
+
+declare i32 @llvm.hexagon.M2.hmmpyh.s1(i32, i32)
+define i32 @M2_hmmpyh_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.hmmpyh.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0, r1.h):<<1:sat
+
+declare i32 @llvm.hexagon.M2.hmmpyl.s1(i32, i32)
+define i32 @M2_hmmpyl_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.hmmpyl.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0, r1.l):<<1:sat
+
+declare i32 @llvm.hexagon.M2.hmmpyh.rs1(i32, i32)
+define i32 @M2_hmmpyh_rs1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.hmmpyh.rs1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0, r1.h):<<1:rnd:sat
+
+declare i32 @llvm.hexagon.M2.mpy.up.s1.sat(i32, i32)
+define i32 @M2_mpy_up_s1_sat(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.up.s1.sat(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0, r1):<<1:sat
+
+declare i32 @llvm.hexagon.M2.hmmpyl.rs1(i32, i32)
+define i32 @M2_hmmpyl_rs1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.hmmpyl.rs1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0, r1.l):<<1:rnd:sat
+
+declare i32 @llvm.hexagon.M2.mpy.up(i32, i32)
+define i32 @M2_mpy_up(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.up(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0, r1)
+
+declare i32 @llvm.hexagon.M2.mpy.up.s1(i32, i32)
+define i32 @M2_mpy_up_s1(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.M2.mpy.up.s1(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = mpy(r0, r1):<<1
+
+declare i32 @llvm.hexagon.M4.mac.up.s1.sat(i32, i32, i32)
+define i32 @M4_mac_up_s1_sat(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M4.mac.up.s1.sat(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += mpy(r1, r2):<<1:sat
+
+declare i32 @llvm.hexagon.M4.nac.up.s1.sat(i32, i32, i32)
+define i32 @M4_nac_up_s1_sat(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.M4.nac.up.s1.sat(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= mpy(r1, r2):<<1:sat
+
+; Multiply and use full result
+declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32)
+define i64 @M2_dpmpyss_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpy(r0, r1)
+
+declare i64 @llvm.hexagon.M2.dpmpyuu.s0(i32, i32)
+define i64 @M2_dpmpyuu_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.dpmpyuu.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = mpyu(r0, r1)
+
+declare i64 @llvm.hexagon.M2.dpmpyss.acc.s0(i64, i32, i32)
+define i64 @M2_dpmpyss_acc_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.dpmpyss.acc.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpy(r2, r3)
+
+declare i64 @llvm.hexagon.M2.dpmpyss.nac.s0(i64, i32, i32)
+define i64 @M2_dpmpyss_nac_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.dpmpyss.nac.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpy(r2, r3)
+
+declare i64 @llvm.hexagon.M2.dpmpyuu.acc.s0(i64, i32, i32)
+define i64 @M2_dpmpyuu_acc_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.dpmpyuu.acc.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += mpyu(r2, r3)
+
+declare i64 @llvm.hexagon.M2.dpmpyuu.nac.s0(i64, i32, i32)
+define i64 @M2_dpmpyuu_nac_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.dpmpyuu.nac.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= mpyu(r2, r3)
+
+; Vector dual multiply
+declare i64 @llvm.hexagon.M2.vdmpys.s0(i64, i64)
+define i64 @M2_vdmpys_s0(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.vdmpys.s0(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vdmpy(r1:0, r3:2):sat
+
+declare i64 @llvm.hexagon.M2.vdmpys.s1(i64, i64)
+define i64 @M2_vdmpys_s1(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.vdmpys.s1(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vdmpy(r1:0, r3:2):<<1:sat
+
+; Vector reduce multiply bytes
+declare i64 @llvm.hexagon.M5.vrmpybuu(i64, i64)
+define i64 @M5_vrmpybuu(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M5.vrmpybuu(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrmpybu(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.M5.vrmpybsu(i64, i64)
+define i64 @M5_vrmpybsu(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M5.vrmpybsu(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrmpybsu(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.M5.vrmacbuu(i64, i64, i64)
+define i64 @M5_vrmacbuu(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M5.vrmacbuu(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vrmpybu(r3:2, r5:4)
+
+declare i64 @llvm.hexagon.M5.vrmacbsu(i64, i64, i64)
+define i64 @M5_vrmacbsu(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M5.vrmacbsu(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vrmpybsu(r3:2, r5:4)
+
+; Vector dual multiply signed by unsigned bytes
+declare i64 @llvm.hexagon.M5.vdmpybsu(i64, i64)
+define i64 @M5_vdmpybsu(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M5.vdmpybsu(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vdmpybsu(r1:0, r3:2):sat
+
+declare i64 @llvm.hexagon.M5.vdmacbsu(i64, i64, i64)
+define i64 @M5_vdmacbsu(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M5.vdmacbsu(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vdmpybsu(r3:2, r5:4):sat
+
+; Vector multiply even halfwords
+declare i64 @llvm.hexagon.M2.vmpy2es.s0(i64, i64)
+define i64 @M2_vmpy2es_s0(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.vmpy2es.s0(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpyeh(r1:0, r3:2):sat
+
+declare i64 @llvm.hexagon.M2.vmpy2es.s1(i64, i64)
+define i64 @M2_vmpy2es_s1(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.vmpy2es.s1(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpyeh(r1:0, r3:2):<<1:sat
+
+declare i64 @llvm.hexagon.M2.vmac2es(i64, i64, i64)
+define i64 @M2_vmac2es(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M2.vmac2es(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vmpyeh(r3:2, r5:4)
+
+declare i64 @llvm.hexagon.M2.vmac2es.s0(i64, i64, i64)
+define i64 @M2_vmac2es_s0(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M2.vmac2es.s0(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vmpyeh(r3:2, r5:4):sat
+
+declare i64 @llvm.hexagon.M2.vmac2es.s1(i64, i64, i64)
+define i64 @M2_vmac2es_s1(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M2.vmac2es.s1(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vmpyeh(r3:2, r5:4):<<1:sat
+
+; Vector multiply halfwords
+declare i64 @llvm.hexagon.M2.vmpy2s.s0(i32, i32)
+define i64 @M2_vmpy2s_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.vmpy2s.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpyh(r0, r1):sat
+
+declare i64 @llvm.hexagon.M2.vmpy2s.s1(i32, i32)
+define i64 @M2_vmpy2s_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.vmpy2s.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpyh(r0, r1):<<1:sat
+
+declare i64 @llvm.hexagon.M2.vmac2(i64, i32, i32)
+define i64 @M2_vmac2(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.vmac2(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vmpyh(r2, r3)
+
+declare i64 @llvm.hexagon.M2.vmac2s.s0(i64, i32, i32)
+define i64 @M2_vmac2s_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.vmac2s.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vmpyh(r2, r3):sat
+
+declare i64 @llvm.hexagon.M2.vmac2s.s1(i64, i32, i32)
+define i64 @M2_vmac2s_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.vmac2s.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vmpyh(r2, r3):<<1:sat
+
+; Vector multiply halfwords signed by unsigned
+declare i64 @llvm.hexagon.M2.vmpy2su.s0(i32, i32)
+define i64 @M2_vmpy2su_s0(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.vmpy2su.s0(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpyhsu(r0, r1):sat
+
+declare i64 @llvm.hexagon.M2.vmpy2su.s1(i32, i32)
+define i64 @M2_vmpy2su_s1(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M2.vmpy2su.s1(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpyhsu(r0, r1):<<1:sat
+
+declare i64 @llvm.hexagon.M2.vmac2su.s0(i64, i32, i32)
+define i64 @M2_vmac2su_s0(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.vmac2su.s0(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vmpyhsu(r2, r3):sat
+
+declare i64 @llvm.hexagon.M2.vmac2su.s1(i64, i32, i32)
+define i64 @M2_vmac2su_s1(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M2.vmac2su.s1(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vmpyhsu(r2, r3):<<1:sat
+
+; Vector reduce multiply halfwords
+declare i64 @llvm.hexagon.M2.vrmpy.s0(i64, i64)
+define i64 @M2_vrmpy_s0(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.M2.vrmpy.s0(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vrmpyh(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.M2.vrmac.s0(i64, i64, i64)
+define i64 @M2_vrmac_s0(i64 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.M2.vrmac.s0(i64 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vrmpyh(r3:2, r5:4)
+
+; Vector multiply bytes
+declare i64 @llvm.hexagon.M5.vmpybsu(i32, i32)
+define i64 @M2_vmpybsu(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M5.vmpybsu(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpybsu(r0, r1)
+
+declare i64 @llvm.hexagon.M5.vmpybuu(i32, i32)
+define i64 @M2_vmpybuu(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M5.vmpybuu(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vmpybu(r0, r1)
+
+declare i64 @llvm.hexagon.M5.vmacbuu(i64, i32, i32)
+define i64 @M2_vmacbuu(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M5.vmacbuu(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vmpybu(r2, r3)
+
+declare i64 @llvm.hexagon.M5.vmacbsu(i64, i32, i32)
+define i64 @M2_vmacbsu(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M5.vmacbsu(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += vmpybsu(r2, r3)
+
+; Vector polynomial multiply halfwords
+declare i64 @llvm.hexagon.M4.vpmpyh(i32, i32)
+define i64 @M4_vpmpyh(i32 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.M4.vpmpyh(i32 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vpmpyh(r0, r1)
+
+declare i64 @llvm.hexagon.M4.vpmpyh.acc(i64, i32, i32)
+define i64 @M4_vpmpyh_acc(i64 %a, i32 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.M4.vpmpyh.acc(i64 %a, i32 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 ^= vpmpyh(r2, r3)
diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll b/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll
new file mode 100644
index 000000000000..0b761323e31e
--- /dev/null
+++ b/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll
@@ -0,0 +1,252 @@
+; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
+; Hexagon Programmer's Reference Manual 11.10.6 XTYPE/PERM
+
+; Saturate
+declare i32 @llvm.hexagon.A2.sat(i64)
+define i32 @A2_sat(i64 %a) {
+  %z = call i32 @llvm.hexagon.A2.sat(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = sat(r1:0)
+
+declare i32 @llvm.hexagon.A2.sath(i32)
+define i32 @A2_sath(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.sath(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = sath(r0)
+
+declare i32 @llvm.hexagon.A2.satuh(i32)
+define i32 @A2_satuh(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.satuh(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = satuh(r0)
+
+declare i32 @llvm.hexagon.A2.satub(i32)
+define i32 @A2_satub(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.satub(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = satub(r0)
+
+declare i32 @llvm.hexagon.A2.satb(i32)
+define i32 @A2_satb(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.satb(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = satb(r0)
+
+; Swizzle bytes
+declare i32 @llvm.hexagon.A2.swiz(i32)
+define i32 @A2_swiz(i32 %a) {
+  %z = call i32 @llvm.hexagon.A2.swiz(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = swiz(r0)
+
+; Vector round and pack
+declare i32 @llvm.hexagon.S2.vrndpackwh(i64)
+define i32 @S2_vrndpackwh(i64 %a) {
+  %z = call i32 @llvm.hexagon.S2.vrndpackwh(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = vrndwh(r1:0)
+
+declare i32 @llvm.hexagon.S2.vrndpackwhs(i64)
+define i32 @S2_vrndpackwhs(i64 %a) {
+  %z = call i32 @llvm.hexagon.S2.vrndpackwhs(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = vrndwh(r1:0):sat
+
+; Vector saturate and pack
+declare i32 @llvm.hexagon.S2.vsathub(i64)
+define i32 @S2_vsathub(i64 %a) {
+  %z = call i32 @llvm.hexagon.S2.vsathub(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = vsathub(r1:0)
+
+declare i32 @llvm.hexagon.S2.vsatwh(i64)
+define i32 @S2_vsatwh(i64 %a) {
+  %z = call i32 @llvm.hexagon.S2.vsatwh(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = vsatwh(r1:0)
+
+declare i32 @llvm.hexagon.S2.vsatwuh(i64)
+define i32 @S2_vsatwuh(i64 %a) {
+  %z = call i32 @llvm.hexagon.S2.vsatwuh(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = vsatwuh(r1:0)
+
+declare i32 @llvm.hexagon.S2.vsathb(i64)
+define i32 @S2_vsathb(i64 %a) {
+  %z = call i32 @llvm.hexagon.S2.vsathb(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = vsathb(r1:0)
+
+declare i32 @llvm.hexagon.S2.svsathb(i32)
+define i32 @S2_svsathb(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.svsathb(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = vsathb(r0)
+
+declare i32 @llvm.hexagon.S2.svsathub(i32)
+define i32 @S2_svsathub(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.svsathub(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = vsathub(r0)
+
+; Vector saturate without pack
+declare i64 @llvm.hexagon.S2.vsathub.nopack(i64)
+define i64 @S2_vsathub_nopack(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.vsathub.nopack(i64 %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = vsathub(r1:0)
+
+declare i64 @llvm.hexagon.S2.vsatwuh.nopack(i64)
+define i64 @S2_vsatwuh_nopack(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.vsatwuh.nopack(i64 %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = vsatwuh(r1:0)
+
+declare i64 @llvm.hexagon.S2.vsatwh.nopack(i64)
+define i64 @S2_vsatwh_nopack(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.vsatwh.nopack(i64 %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = vsatwh(r1:0)
+
+declare i64 @llvm.hexagon.S2.vsathb.nopack(i64)
+define i64 @S2_vsathb_nopack(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.vsathb.nopack(i64 %a)
+  ret i64 %z
+}
+; CHECK: r1:0 = vsathb(r1:0)
+
+; Vector shuffle
+declare i64 @llvm.hexagon.S2.shuffeb(i64, i64)
+define i64 @S2_shuffeb(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.shuffeb(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = shuffeb(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.S2.shuffob(i64, i64)
+define i64 @S2_shuffob(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.shuffob(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = shuffob(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.S2.shuffeh(i64, i64)
+define i64 @S2_shuffeh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.shuffeh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = shuffeh(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.S2.shuffoh(i64, i64)
+define i64 @S2_shuffoh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.shuffoh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = shuffoh(r1:0, r3:2)
+
+; Vector splat bytes
+declare i32 @llvm.hexagon.S2.vsplatrb(i32)
+define i32 @S2_vsplatrb(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.vsplatrb(i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = vsplatb(r0)
+
+; Vector splat halfwords
+declare i64 @llvm.hexagon.S2.vsplatrh(i32)
+define i64 @S2_vsplatrh(i32 %a) {
+  %z = call i64 @llvm.hexagon.S2.vsplatrh(i32 %a)
+  ret i64 %z
+}
+; CHECK:  = vsplath(r0)
+
+; Vector splice
+declare i64 @llvm.hexagon.S2.vspliceib(i64, i64, i32)
+define i64 @S2_vspliceib(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.vspliceib(i64 %a, i64 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = vspliceb(r1:0, r3:2, #0)
+
+declare i64 @llvm.hexagon.S2.vsplicerb(i64, i64, i32)
+define i64 @S2_vsplicerb(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.vsplicerb(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 = vspliceb(r1:0, r3:2, p0)
+
+; Vector sign extend
+declare i64 @llvm.hexagon.S2.vsxtbh(i32)
+define i64 @S2_vsxtbh(i32 %a) {
+  %z = call i64 @llvm.hexagon.S2.vsxtbh(i32 %a)
+  ret i64 %z
+}
+; CHECK:  = vsxtbh(r0)
+
+declare i64 @llvm.hexagon.S2.vsxthw(i32)
+define i64 @S2_vsxthw(i32 %a) {
+  %z = call i64 @llvm.hexagon.S2.vsxthw(i32 %a)
+  ret i64 %z
+}
+; CHECK:  = vsxthw(r0)
+
+; Vector truncate
+declare i32 @llvm.hexagon.S2.vtrunohb(i64)
+define i32 @S2_vtrunohb(i64 %a) {
+  %z = call i32 @llvm.hexagon.S2.vtrunohb(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = vtrunohb(r1:0)
+
+declare i32 @llvm.hexagon.S2.vtrunehb(i64)
+define i32 @S2_vtrunehb(i64 %a) {
+  %z = call i32 @llvm.hexagon.S2.vtrunehb(i64 %a)
+  ret i32 %z
+}
+; CHECK: r0 = vtrunehb(r1:0)
+
+declare i64 @llvm.hexagon.S2.vtrunowh(i64, i64)
+define i64 @S2_vtrunowh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.vtrunowh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vtrunowh(r1:0, r3:2)
+
+declare i64 @llvm.hexagon.S2.vtrunewh(i64, i64)
+define i64 @S2_vtrunewh(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.vtrunewh(i64 %a, i64 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vtrunewh(r1:0, r3:2)
+
+; Vector zero extend
+declare i64 @llvm.hexagon.S2.vzxtbh(i32)
+define i64 @S2_vzxtbh(i32 %a) {
+  %z = call i64 @llvm.hexagon.S2.vzxtbh(i32 %a)
+  ret i64 %z
+}
+; CHECK:  = vzxtbh(r0)
+
+declare i64 @llvm.hexagon.S2.vzxthw(i32)
+define i64 @S2_vzxthw(i32 %a) {
+  %z = call i64 @llvm.hexagon.S2.vzxthw(i32 %a)
+  ret i64 %z
+}
+; CHECK:  = vzxthw(r0)
diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll b/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll
new file mode 100644
index 000000000000..96e63d8d7790
--- /dev/null
+++ b/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll
@@ -0,0 +1,351 @@
+; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
+; Hexagon Programmer's Reference Manual 11.10.7 XTYPE/PRED
+
+; Compare byte
+declare i32 @llvm.hexagon.A4.cmpbgt(i32, i32)
+define i32 @A4_cmpbgt(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A4.cmpbgt(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = cmpb.gt(r0, r1)
+
+declare i32 @llvm.hexagon.A4.cmpbeq(i32, i32)
+define i32 @A4_cmpbeq(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A4.cmpbeq(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = cmpb.eq(r0, r1)
+
+declare i32 @llvm.hexagon.A4.cmpbgtu(i32, i32)
+define i32 @A4_cmpbgtu(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A4.cmpbgtu(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = cmpb.gtu(r0, r1)
+
+declare i32 @llvm.hexagon.A4.cmpbgti(i32, i32)
+define i32 @A4_cmpbgti(i32 %a) {
+  %z = call i32 @llvm.hexagon.A4.cmpbgti(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = cmpb.gt(r0, #0)
+
+declare i32 @llvm.hexagon.A4.cmpbeqi(i32, i32)
+define i32 @A4_cmpbeqi(i32 %a) {
+  %z = call i32 @llvm.hexagon.A4.cmpbeqi(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = cmpb.eq(r0, #0)
+
+declare i32 @llvm.hexagon.A4.cmpbgtui(i32, i32)
+define i32 @A4_cmpbgtui(i32 %a) {
+  %z = call i32 @llvm.hexagon.A4.cmpbgtui(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = cmpb.gtu(r0, #0)
+
+; Compare half
+declare i32 @llvm.hexagon.A4.cmphgt(i32, i32)
+define i32 @A4_cmphgt(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A4.cmphgt(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = cmph.gt(r0, r1)
+
+declare i32 @llvm.hexagon.A4.cmpheq(i32, i32)
+define i32 @A4_cmpheq(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A4.cmpheq(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = cmph.eq(r0, r1)
+
+declare i32 @llvm.hexagon.A4.cmphgtu(i32, i32)
+define i32 @A4_cmphgtu(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A4.cmphgtu(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = cmph.gtu(r0, r1)
+
+declare i32 @llvm.hexagon.A4.cmphgti(i32, i32)
+define i32 @A4_cmphgti(i32 %a) {
+  %z = call i32 @llvm.hexagon.A4.cmphgti(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = cmph.gt(r0, #0)
+
+declare i32 @llvm.hexagon.A4.cmpheqi(i32, i32)
+define i32 @A4_cmpheqi(i32 %a) {
+  %z = call i32 @llvm.hexagon.A4.cmpheqi(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = cmph.eq(r0, #0)
+
+declare i32 @llvm.hexagon.A4.cmphgtui(i32, i32)
+define i32 @A4_cmphgtui(i32 %a) {
+  %z = call i32 @llvm.hexagon.A4.cmphgtui(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = cmph.gtu(r0, #0)
+
+; Compare doublewords
+declare i32 @llvm.hexagon.C2.cmpgtp(i64, i64)
+define i32 @C2_cmpgtp(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.C2.cmpgtp(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: p0 = cmp.gt(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.C2.cmpeqp(i64, i64)
+define i32 @C2_cmpeqp(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.C2.cmpeqp(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: p0 = cmp.eq(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.C2.cmpgtup(i64, i64)
+define i32 @C2_cmpgtup(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.C2.cmpgtup(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: p0 = cmp.gtu(r1:0, r3:2)
+
+; Compare bitmask
+declare i32 @llvm.hexagon.C2.bitsclri(i32, i32)
+define i32 @C2_bitsclri(i32 %a) {
+  %z = call i32 @llvm.hexagon.C2.bitsclri(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = bitsclr(r0, #0)
+
+declare i32 @llvm.hexagon.C4.nbitsclri(i32, i32)
+define i32 @C4_nbitsclri(i32 %a) {
+  %z = call i32 @llvm.hexagon.C4.nbitsclri(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = !bitsclr(r0, #0)
+
+declare i32 @llvm.hexagon.C2.bitsset(i32, i32)
+define i32 @C2_bitsset(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.C2.bitsset(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = bitsset(r0, r1)
+
+declare i32 @llvm.hexagon.C4.nbitsset(i32, i32)
+define i32 @C4_nbitsset(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.C4.nbitsset(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = !bitsset(r0, r1)
+
+declare i32 @llvm.hexagon.C2.bitsclr(i32, i32)
+define i32 @C2_bitsclr(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.C2.bitsclr(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = bitsclr(r0, r1)
+
+declare i32 @llvm.hexagon.C4.nbitsclr(i32, i32)
+define i32 @C4_nbitsclr(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.C4.nbitsclr(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = !bitsclr(r0, r1)
+
+; Mask generate from predicate
+declare i64 @llvm.hexagon.C2.mask(i32)
+define i64 @C2_mask(i32 %a) {
+  %z = call i64 @llvm.hexagon.C2.mask(i32 %a)
+  ret i64 %z
+}
+; CHECK:  = mask(p0)
+
+; Check for TLB match
+declare i32 @llvm.hexagon.A4.tlbmatch(i64, i32)
+define i32 @A4_tlbmatch(i64 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.A4.tlbmatch(i64 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = tlbmatch(r1:0, r2)
+
+; Test bit
+declare i32 @llvm.hexagon.S2.tstbit.i(i32, i32)
+define i32 @S2_tstbit_i(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.tstbit.i(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = tstbit(r0, #0)
+
+declare i32 @llvm.hexagon.S4.ntstbit.i(i32, i32)
+define i32 @S4_ntstbit_i(i32 %a) {
+  %z = call i32 @llvm.hexagon.S4.ntstbit.i(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = !tstbit(r0, #0)
+
+declare i32 @llvm.hexagon.S2.tstbit.r(i32, i32)
+define i32 @S2_tstbit_r(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.tstbit.r(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = tstbit(r0, r1)
+
+declare i32 @llvm.hexagon.S4.ntstbit.r(i32, i32)
+define i32 @S4_ntstbit_r(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S4.ntstbit.r(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = !tstbit(r0, r1)
+
+; Vector compare halfwords
+declare i32 @llvm.hexagon.A2.vcmpheq(i64, i64)
+define i32 @A2_vcmpheq(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.A2.vcmpheq(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: p0 = vcmph.eq(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A2.vcmphgt(i64, i64)
+define i32 @A2_vcmphgt(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.A2.vcmphgt(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: p0 = vcmph.gt(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A2.vcmphgtu(i64, i64)
+define i32 @A2_vcmphgtu(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.A2.vcmphgtu(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: p0 = vcmph.gtu(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A4.vcmpheqi(i64, i32)
+define i32 @A4_vcmpheqi(i64 %a) {
+  %z = call i32 @llvm.hexagon.A4.vcmpheqi(i64 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = vcmph.eq(r1:0, #0)
+
+declare i32 @llvm.hexagon.A4.vcmphgti(i64, i32)
+define i32 @A4_vcmphgti(i64 %a) {
+  %z = call i32 @llvm.hexagon.A4.vcmphgti(i64 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = vcmph.gt(r1:0, #0)
+
+declare i32 @llvm.hexagon.A4.vcmphgtui(i64, i32)
+define i32 @A4_vcmphgtui(i64 %a) {
+  %z = call i32 @llvm.hexagon.A4.vcmphgtui(i64 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = vcmph.gtu(r1:0, #0)
+
+; Vector compare bytes for any match
+declare i32 @llvm.hexagon.A4.vcmpbeq.any(i64, i64)
+define i32 @A4_vcmpbeq_any(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.A4.vcmpbeq.any(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: p0 = any8(vcmpb.eq(r1:0, r3:2))
+
+; Vector compare bytes
+declare i32 @llvm.hexagon.A2.vcmpbeq(i64, i64)
+define i32 @A2_vcmpbeq(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.A2.vcmpbeq(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: p0 = vcmpb.eq(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A2.vcmpbgtu(i64, i64)
+define i32 @A2_vcmpbgtu(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.A2.vcmpbgtu(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: p0 = vcmpb.gtu(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A4.vcmpbgt(i64, i64)
+define i32 @A4_vcmpbgt(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.A4.vcmpbgt(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: p0 = vcmpb.gt(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A4.vcmpbeqi(i64, i32)
+define i32 @A4_vcmpbeqi(i64 %a) {
+  %z = call i32 @llvm.hexagon.A4.vcmpbeqi(i64 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = vcmpb.eq(r1:0, #0)
+
+declare i32 @llvm.hexagon.A4.vcmpbgti(i64, i32)
+define i32 @A4_vcmpbgti(i64 %a) {
+  %z = call i32 @llvm.hexagon.A4.vcmpbgti(i64 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = vcmpb.gt(r1:0, #0)
+
+declare i32 @llvm.hexagon.A4.vcmpbgtui(i64, i32)
+define i32 @A4_vcmpbgtui(i64 %a) {
+  %z = call i32 @llvm.hexagon.A4.vcmpbgtui(i64 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = vcmpb.gtu(r1:0, #0)
+
+; Vector compare words
+declare i32 @llvm.hexagon.A2.vcmpweq(i64, i64)
+define i32 @A2_vcmpweq(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.A2.vcmpweq(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: p0 = vcmpw.eq(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A2.vcmpwgt(i64, i64)
+define i32 @A2_vcmpwgt(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.A2.vcmpwgt(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: p0 = vcmpw.gt(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A2.vcmpwgtu(i64, i64)
+define i32 @A2_vcmpwgtu(i64 %a, i64 %b) {
+  %z = call i32 @llvm.hexagon.A2.vcmpwgtu(i64 %a, i64 %b)
+  ret i32 %z
+}
+; CHECK: p0 = vcmpw.gtu(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A4.vcmpweqi(i64, i32)
+define i32 @A4_vcmpweqi(i64 %a) {
+  %z = call i32 @llvm.hexagon.A4.vcmpweqi(i64 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = vcmpw.eq(r1:0, #0)
+
+declare i32 @llvm.hexagon.A4.vcmpwgti(i64, i32)
+define i32 @A4_vcmpwgti(i64 %a) {
+  %z = call i32 @llvm.hexagon.A4.vcmpwgti(i64 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = vcmpw.gt(r1:0, #0)
+
+declare i32 @llvm.hexagon.A4.vcmpwgtui(i64, i32)
+define i32 @A4_vcmpwgtui(i64 %a) {
+  %z = call i32 @llvm.hexagon.A4.vcmpwgtui(i64 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: p0 = vcmpw.gtu(r1:0, #0)
+
+; Viterbi pack even and odd predicate bitsclr
+declare i32 @llvm.hexagon.C2.vitpack(i32, i32)
+define i32 @C2_vitpack(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.C2.vitpack(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = vitpack(p1, p0)
+
+; Vector mux
+declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64)
+define i64 @C2_vmux(i32 %a, i64 %b, i64 %c) {
+  %z = call i64 @llvm.hexagon.C2.vmux(i32 %a, i64 %b, i64 %c)
+  ret i64 %z
+}
+; CHECK:  = vmux(p0, r3:2, r5:4)
diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll b/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll
new file mode 100644
index 000000000000..c84999bf94fd
--- /dev/null
+++ b/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll
@@ -0,0 +1,723 @@
+; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
+; Hexagon Programmer's Reference Manual 11.10.8 XTYPE/SHIFT
+
+; Shift by immediate
+declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32)
+define i64 @S2_asr_i_p(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.asr.i.p(i64 %a, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = asr(r1:0, #0)
+
+declare i64 @llvm.hexagon.S2.lsr.i.p(i64, i32)
+define i64 @S2_lsr_i_p(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.lsr.i.p(i64 %a, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = lsr(r1:0, #0)
+
+declare i64 @llvm.hexagon.S2.asl.i.p(i64, i32)
+define i64 @S2_asl_i_p(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.asl.i.p(i64 %a, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = asl(r1:0, #0)
+
+declare i32 @llvm.hexagon.S2.asr.i.r(i32, i32)
+define i32 @S2_asr_i_r(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.asr.i.r(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = asr(r0, #0)
+
+declare i32 @llvm.hexagon.S2.lsr.i.r(i32, i32)
+define i32 @S2_lsr_i_r(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.lsr.i.r(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = lsr(r0, #0)
+
+declare i32 @llvm.hexagon.S2.asl.i.r(i32, i32)
+define i32 @S2_asl_i_r(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.asl.i.r(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = asl(r0, #0)
+
+; Shift by immediate and accumulate
+declare i64 @llvm.hexagon.S2.asr.i.p.nac(i64, i64, i32)
+define i64 @S2_asr_i_p_nac(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.asr.i.p.nac(i64 %a, i64 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 -= asr(r3:2, #0)
+
+declare i64 @llvm.hexagon.S2.lsr.i.p.nac(i64, i64, i32)
+define i64 @S2_lsr_i_p_nac(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.lsr.i.p.nac(i64 %a, i64 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 -= lsr(r3:2, #0)
+
+declare i64 @llvm.hexagon.S2.asl.i.p.nac(i64, i64, i32)
+define i64 @S2_asl_i_p_nac(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.asl.i.p.nac(i64 %a, i64 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 -= asl(r3:2, #0)
+
+declare i64 @llvm.hexagon.S2.asr.i.p.acc(i64, i64, i32)
+define i64 @S2_asr_i_p_acc(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.asr.i.p.acc(i64 %a, i64 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 += asr(r3:2, #0)
+
+declare i64 @llvm.hexagon.S2.lsr.i.p.acc(i64, i64, i32)
+define i64 @S2_lsr_i_p_acc(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.lsr.i.p.acc(i64 %a, i64 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 += lsr(r3:2, #0)
+
+declare i64 @llvm.hexagon.S2.asl.i.p.acc(i64, i64, i32)
+define i64 @S2_asl_i_p_acc(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.asl.i.p.acc(i64 %a, i64 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 += asl(r3:2, #0)
+
+declare i32 @llvm.hexagon.S2.asr.i.r.nac(i32, i32, i32)
+define i32 @S2_asr_i_r_nac(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.asr.i.r.nac(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 -= asr(r1, #0)
+
+declare i32 @llvm.hexagon.S2.lsr.i.r.nac(i32, i32, i32)
+define i32 @S2_lsr_i_r_nac(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.lsr.i.r.nac(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 -= lsr(r1, #0)
+
+declare i32 @llvm.hexagon.S2.asl.i.r.nac(i32, i32, i32)
+define i32 @S2_asl_i_r_nac(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.asl.i.r.nac(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 -= asl(r1, #0)
+
+declare i32 @llvm.hexagon.S2.asr.i.r.acc(i32, i32, i32)
+define i32 @S2_asr_i_r_acc(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.asr.i.r.acc(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 += asr(r1, #0)
+
+declare i32 @llvm.hexagon.S2.lsr.i.r.acc(i32, i32, i32)
+define i32 @S2_lsr_i_r_acc(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.lsr.i.r.acc(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 += lsr(r1, #0)
+
+declare i32 @llvm.hexagon.S2.asl.i.r.acc(i32, i32, i32)
+define i32 @S2_asl_i_r_acc(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.asl.i.r.acc(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 += asl(r1, #0)
+
+; Shift by immediate and add
+declare i32 @llvm.hexagon.S4.addi.asl.ri(i32, i32, i32)
+define i32 @S4_addi_asl_ri(i32 %a) {
+  %z = call i32 @llvm.hexagon.S4.addi.asl.ri(i32 0, i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = add(#0, asl(r0, #0))
+
+declare i32 @llvm.hexagon.S4.subi.asl.ri(i32, i32, i32)
+define i32 @S4_subi_asl_ri(i32 %a) {
+  %z = call i32 @llvm.hexagon.S4.subi.asl.ri(i32 0, i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = sub(#0, asl(r0, #0))
+
+declare i32 @llvm.hexagon.S4.addi.lsr.ri(i32, i32, i32)
+define i32 @S4_addi_lsr_ri(i32 %a) {
+  %z = call i32 @llvm.hexagon.S4.addi.lsr.ri(i32 0, i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = add(#0, lsr(r0, #0))
+
+declare i32 @llvm.hexagon.S4.subi.lsr.ri(i32, i32, i32)
+define i32 @S4_subi_lsr_ri(i32 %a) {
+  %z = call i32 @llvm.hexagon.S4.subi.lsr.ri(i32 0, i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = sub(#0, lsr(r0, #0))
+
+declare i32 @llvm.hexagon.S2.addasl.rrri(i32, i32, i32)
+define i32 @S2_addasl_rrri(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.addasl.rrri(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = addasl(r0, r1, #0)
+
+; Shift by immediate and logical
+declare i64 @llvm.hexagon.S2.asr.i.p.and(i64, i64, i32)
+define i64 @S2_asr_i_p_and(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.asr.i.p.and(i64 %a, i64 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 &= asr(r3:2, #0)
+
+declare i64 @llvm.hexagon.S2.lsr.i.p.and(i64, i64, i32)
+define i64 @S2_lsr_i_p_and(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.lsr.i.p.and(i64 %a, i64 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 &= lsr(r3:2, #0)
+
+declare i64 @llvm.hexagon.S2.asl.i.p.and(i64, i64, i32)
+define i64 @S2_asl_i_p_and(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.asl.i.p.and(i64 %a, i64 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 &= asl(r3:2, #0)
+
+declare i64 @llvm.hexagon.S2.asr.i.p.or(i64, i64, i32)
+define i64 @S2_asr_i_p_or(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.asr.i.p.or(i64 %a, i64 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 |= asr(r3:2, #0)
+
+declare i64 @llvm.hexagon.S2.lsr.i.p.or(i64, i64, i32)
+define i64 @S2_lsr_i_p_or(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.lsr.i.p.or(i64 %a, i64 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 |= lsr(r3:2, #0)
+
+declare i64 @llvm.hexagon.S2.asl.i.p.or(i64, i64, i32)
+define i64 @S2_asl_i_p_or(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.asl.i.p.or(i64 %a, i64 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 |= asl(r3:2, #0)
+
+declare i64 @llvm.hexagon.S2.lsr.i.p.xacc(i64, i64, i32)
+define i64 @S2_lsr_i_p_xacc(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.lsr.i.p.xacc(i64 %a, i64 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 ^= lsr(r3:2, #0)
+
+declare i64 @llvm.hexagon.S2.asl.i.p.xacc(i64, i64, i32)
+define i64 @S2_asl_i_p_xacc(i64 %a, i64 %b) {
+  %z = call i64 @llvm.hexagon.S2.asl.i.p.xacc(i64 %a, i64 %b, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 ^= asl(r3:2, #0)
+
+declare i32 @llvm.hexagon.S2.asr.i.r.and(i32, i32, i32)
+define i32 @S2_asr_i_r_and(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.asr.i.r.and(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 &= asr(r1, #0)
+
+declare i32 @llvm.hexagon.S2.lsr.i.r.and(i32, i32, i32)
+define i32 @S2_lsr_i_r_and(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.lsr.i.r.and(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 &= lsr(r1, #0)
+
+declare i32 @llvm.hexagon.S2.asl.i.r.and(i32, i32, i32)
+define i32 @S2_asl_i_r_and(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.asl.i.r.and(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 &= asl(r1, #0)
+
+declare i32 @llvm.hexagon.S2.asr.i.r.or(i32, i32, i32)
+define i32 @S2_asr_i_r_or(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.asr.i.r.or(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 |= asr(r1, #0)
+
+declare i32 @llvm.hexagon.S2.lsr.i.r.or(i32, i32, i32)
+define i32 @S2_lsr_i_r_or(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.lsr.i.r.or(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 |= lsr(r1, #0)
+
+declare i32 @llvm.hexagon.S2.asl.i.r.or(i32, i32, i32)
+define i32 @S2_asl_i_r_or(i32%a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.asl.i.r.or(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 |= asl(r1, #0)
+
+declare i32 @llvm.hexagon.S2.lsr.i.r.xacc(i32, i32, i32)
+define i32 @S2_lsr_i_r_xacc(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.lsr.i.r.xacc(i32%a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 ^= lsr(r1, #0)
+
+declare i32 @llvm.hexagon.S2.asl.i.r.xacc(i32, i32, i32)
+define i32 @S2_asl_i_r_xacc(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.asl.i.r.xacc(i32 %a, i32 %b, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 ^= asl(r1, #0)
+
+declare i32 @llvm.hexagon.S4.andi.asl.ri(i32, i32, i32)
+define i32 @S4_andi_asl_ri(i32 %a) {
+  %z = call i32 @llvm.hexagon.S4.andi.asl.ri(i32 0, i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = and(#0, asl(r0, #0))
+
+declare i32 @llvm.hexagon.S4.ori.asl.ri(i32, i32, i32)
+define i32 @S4_ori_asl_ri(i32 %a) {
+  %z = call i32 @llvm.hexagon.S4.ori.asl.ri(i32 0, i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = or(#0, asl(r0, #0))
+
+declare i32 @llvm.hexagon.S4.andi.lsr.ri(i32, i32, i32)
+define i32 @S4_andi_lsr_ri(i32 %a) {
+  %z = call i32 @llvm.hexagon.S4.andi.lsr.ri(i32 0, i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = and(#0, lsr(r0, #0))
+
+declare i32 @llvm.hexagon.S4.ori.lsr.ri(i32, i32, i32)
+define i32 @S4_ori_lsr_ri(i32 %a) {
+  %z = call i32 @llvm.hexagon.S4.ori.lsr.ri(i32 0, i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = or(#0, lsr(r0, #0))
+
+; Shift right by immediate with rounding
+declare i64 @llvm.hexagon.S2.asr.i.p.rnd(i64, i32)
+define i64 @S2_asr_i_p_rnd(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.asr.i.p.rnd(i64 %a, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = asr(r1:0, #0):rnd
+
+declare i32 @llvm.hexagon.S2.asr.i.r.rnd(i32, i32)
+define i32 @S2_asr_i_r_rnd(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.asr.i.r.rnd(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = asr(r0, #0):rnd
+
+; Shift left by immediate with saturation
+declare i32 @llvm.hexagon.S2.asl.i.r.sat(i32, i32)
+define i32 @S2_asl_i_r_sat(i32 %a) {
+  %z = call i32 @llvm.hexagon.S2.asl.i.r.sat(i32 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = asl(r0, #0):sat
+
+; Shift by register
+declare i64 @llvm.hexagon.S2.asr.r.p(i64, i32)
+define i64 @S2_asr_r_p(i64 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.S2.asr.r.p(i64 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = asr(r1:0, r2)
+
+declare i64 @llvm.hexagon.S2.lsr.r.p(i64, i32)
+define i64 @S2_lsr_r_p(i64 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.S2.lsr.r.p(i64 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = lsr(r1:0, r2)
+
+declare i64 @llvm.hexagon.S2.asl.r.p(i64, i32)
+define i64 @S2_asl_r_p(i64 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.S2.asl.r.p(i64 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = asl(r1:0, r2)
+
+declare i64 @llvm.hexagon.S2.lsl.r.p(i64, i32)
+define i64 @S2_lsl_r_p(i64 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.S2.lsl.r.p(i64 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = lsl(r1:0, r2)
+
+declare i32 @llvm.hexagon.S2.asr.r.r(i32, i32)
+define i32 @S2_asr_r_r(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.asr.r.r(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = asr(r0, r1)
+
+declare i32 @llvm.hexagon.S2.lsr.r.r(i32, i32)
+define i32 @S2_lsr_r_r(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.lsr.r.r(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = lsr(r0, r1)
+
+declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32)
+define i32 @S2_asl_r_r(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.asl.r.r(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = asl(r0, r1)
+
+declare i32 @llvm.hexagon.S2.lsl.r.r(i32, i32)
+define i32 @S2_lsl_r_r(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.lsl.r.r(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = lsl(r0, r1)
+
+declare i32 @llvm.hexagon.S4.lsli(i32, i32)
+define i32 @S4_lsli(i32 %a) {
+  %z = call i32 @llvm.hexagon.S4.lsli(i32 0, i32 %a)
+  ret i32 %z
+}
+; CHECK: r0 = lsl(#0, r0)
+
+; Shift by register and accumulate
+declare i64 @llvm.hexagon.S2.asr.r.p.nac(i64, i64, i32)
+define i64 @S2_asr_r_p_nac(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.asr.r.p.nac(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= asr(r3:2, r4)
+
+declare i64 @llvm.hexagon.S2.lsr.r.p.nac(i64, i64, i32)
+define i64 @S2_lsr_r_p_nac(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.lsr.r.p.nac(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= lsr(r3:2, r4)
+
+declare i64 @llvm.hexagon.S2.asl.r.p.nac(i64, i64, i32)
+define i64 @S2_asl_r_p_nac(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.asl.r.p.nac(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= asl(r3:2, r4)
+
+declare i64 @llvm.hexagon.S2.lsl.r.p.nac(i64, i64, i32)
+define i64 @S2_lsl_r_p_nac(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.lsl.r.p.nac(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 -= lsl(r3:2, r4)
+
+declare i64 @llvm.hexagon.S2.asr.r.p.acc(i64, i64, i32)
+define i64 @S2_asr_r_p_acc(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.asr.r.p.acc(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += asr(r3:2, r4)
+
+declare i64 @llvm.hexagon.S2.lsr.r.p.acc(i64, i64, i32)
+define i64 @S2_lsr_r_p_acc(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.lsr.r.p.acc(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += lsr(r3:2, r4)
+
+declare i64 @llvm.hexagon.S2.asl.r.p.acc(i64, i64, i32)
+define i64 @S2_asl_r_p_acc(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.asl.r.p.acc(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += asl(r3:2, r4)
+
+declare i64 @llvm.hexagon.S2.lsl.r.p.acc(i64, i64, i32)
+define i64 @S2_lsl_r_p_acc(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.lsl.r.p.acc(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 += lsl(r3:2, r4)
+
+declare i32 @llvm.hexagon.S2.asr.r.r.nac(i32, i32, i32)
+define i32 @S2_asr_r_r_nac(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.asr.r.r.nac(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= asr(r1, r2)
+
+declare i32 @llvm.hexagon.S2.lsr.r.r.nac(i32, i32, i32)
+define i32 @S2_lsr_r_r_nac(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.lsr.r.r.nac(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= lsr(r1, r2)
+
+declare i32 @llvm.hexagon.S2.asl.r.r.nac(i32, i32, i32)
+define i32 @S2_asl_r_r_nac(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.asl.r.r.nac(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= asl(r1, r2)
+
+declare i32 @llvm.hexagon.S2.lsl.r.r.nac(i32, i32, i32)
+define i32 @S2_lsl_r_r_nac(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.lsl.r.r.nac(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 -= lsl(r1, r2)
+
+declare i32 @llvm.hexagon.S2.asr.r.r.acc(i32, i32, i32)
+define i32 @S2_asr_r_r_acc(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.asr.r.r.acc(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += asr(r1, r2)
+
+declare i32 @llvm.hexagon.S2.lsr.r.r.acc(i32, i32, i32)
+define i32 @S2_lsr_r_r_acc(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.lsr.r.r.acc(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += lsr(r1, r2)
+
+declare i32 @llvm.hexagon.S2.asl.r.r.acc(i32, i32, i32)
+define i32 @S2_asl_r_r_acc(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.asl.r.r.acc(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += asl(r1, r2)
+
+declare i32 @llvm.hexagon.S2.lsl.r.r.acc(i32, i32, i32)
+define i32 @S2_lsl_r_r_acc(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.lsl.r.r.acc(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 += lsl(r1, r2)
+
+; Shift by register and logical
+declare i64 @llvm.hexagon.S2.asr.r.p.or(i64, i64, i32)
+define i64 @S2_asr_r_p_or(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.asr.r.p.or(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 |= asr(r3:2, r4)
+
+declare i64 @llvm.hexagon.S2.lsr.r.p.or(i64, i64, i32)
+define i64 @S2_lsr_r_p_or(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.lsr.r.p.or(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 |= lsr(r3:2, r4)
+
+declare i64 @llvm.hexagon.S2.asl.r.p.or(i64, i64, i32)
+define i64 @S2_asl_r_p_or(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.asl.r.p.or(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 |= asl(r3:2, r4)
+
+declare i64 @llvm.hexagon.S2.lsl.r.p.or(i64, i64, i32)
+define i64 @S2_lsl_r_p_or(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.lsl.r.p.or(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 |= lsl(r3:2, r4)
+
+declare i64 @llvm.hexagon.S2.asr.r.p.and(i64, i64, i32)
+define i64 @S2_asr_r_p_and(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.asr.r.p.and(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 &= asr(r3:2, r4)
+
+declare i64 @llvm.hexagon.S2.lsr.r.p.and(i64, i64, i32)
+define i64 @S2_lsr_r_p_and(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.lsr.r.p.and(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 &= lsr(r3:2, r4)
+
+declare i64 @llvm.hexagon.S2.asl.r.p.and(i64, i64, i32)
+define i64 @S2_asl_r_p_and(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.asl.r.p.and(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 &= asl(r3:2, r4)
+
+declare i64 @llvm.hexagon.S2.lsl.r.p.and(i64, i64, i32)
+define i64 @S2_lsl_r_p_and(i64 %a, i64 %b, i32 %c) {
+  %z = call i64 @llvm.hexagon.S2.lsl.r.p.and(i64 %a, i64 %b, i32 %c)
+  ret i64 %z
+}
+; CHECK: r1:0 &= lsl(r3:2, r4)
+
+declare i32 @llvm.hexagon.S2.asr.r.r.or(i32, i32, i32)
+define i32 @S2_asr_r_r_or(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.asr.r.r.or(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 |= asr(r1, r2)
+
+declare i32 @llvm.hexagon.S2.lsr.r.r.or(i32, i32, i32)
+define i32 @S2_lsr_r_r_or(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.lsr.r.r.or(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 |= lsr(r1, r2)
+
+declare i32 @llvm.hexagon.S2.asl.r.r.or(i32, i32, i32)
+define i32 @S2_asl_r_r_or(i32%a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.asl.r.r.or(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 |= asl(r1, r2)
+
+declare i32 @llvm.hexagon.S2.lsl.r.r.or(i32, i32, i32)
+define i32 @S2_lsl_r_r_or(i32%a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.lsl.r.r.or(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 |= lsl(r1, r2)
+
+declare i32 @llvm.hexagon.S2.asr.r.r.and(i32, i32, i32)
+define i32 @S2_asr_r_r_and(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.asr.r.r.and(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 &= asr(r1, r2)
+
+declare i32 @llvm.hexagon.S2.lsr.r.r.and(i32, i32, i32)
+define i32 @S2_lsr_r_r_and(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.lsr.r.r.and(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 &= lsr(r1, r2)
+
+declare i32 @llvm.hexagon.S2.asl.r.r.and(i32, i32, i32)
+define i32 @S2_asl_r_r_and(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.asl.r.r.and(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 &= asl(r1, r2)
+
+declare i32 @llvm.hexagon.S2.lsl.r.r.and(i32, i32, i32)
+define i32 @S2_lsl_r_r_and(i32 %a, i32 %b, i32 %c) {
+  %z = call i32 @llvm.hexagon.S2.lsl.r.r.and(i32 %a, i32 %b, i32 %c)
+  ret i32 %z
+}
+; CHECK: r0 &= lsl(r1, r2)
+
+; Shift by register with saturation
+declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32)
+define i32 @S2_asr_r_r_sat(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = asr(r0, r1):sat
+
+declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32)
+define i32 @S2_asl_r_r_sat(i32 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.asl.r.r.sat(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = asl(r0, r1):sat
+
+; Vector shift halfwords by immediate
+declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32)
+define i64 @S2_asr_i_vh(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.asr.i.vh(i64 %a, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = vasrh(r1:0, #0)
+
+declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32)
+define i64 @S2_lsr_i_vh(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.lsr.i.vh(i64 %a, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = vlsrh(r1:0, #0)
+
+declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32)
+define i64 @S2_asl_i_vh(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.asl.i.vh(i64 %a, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = vaslh(r1:0, #0)
+
+; Vector shift halfwords by register
+declare i64 @llvm.hexagon.S2.asr.r.vh(i64, i32)
+define i64 @S2_asr_r_vh(i64 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.S2.asr.r.vh(i64 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vasrh(r1:0, r2)
+
+declare i64 @llvm.hexagon.S2.lsr.r.vh(i64, i32)
+define i64 @S2_lsr_r_vh(i64 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.S2.lsr.r.vh(i64 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vlsrh(r1:0, r2)
+
+declare i64 @llvm.hexagon.S2.asl.r.vh(i64, i32)
+define i64 @S2_asl_r_vh(i64 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.S2.asl.r.vh(i64 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vaslh(r1:0, r2)
+
+declare i64 @llvm.hexagon.S2.lsl.r.vh(i64, i32)
+define i64 @S2_lsl_r_vh(i64 %a, i32 %b) {
+  %z = call i64 @llvm.hexagon.S2.lsl.r.vh(i64 %a, i32 %b)
+  ret i64 %z
+}
+; CHECK: r1:0 = vlslh(r1:0, r2)
+
+; Vector shift words by immediate
+declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32)
+define i64 @S2_asr_i_vw(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.asr.i.vw(i64 %a, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = vasrw(r1:0, #0)
+
+declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32)
+define i64 @S2_lsr_i_vw(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %a, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = vlsrw(r1:0, #0)
+
+declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32)
+define i64 @S2_asl_i_vw(i64 %a) {
+  %z = call i64 @llvm.hexagon.S2.asl.i.vw(i64 %a, i32 0)
+  ret i64 %z
+}
+; CHECK: r1:0 = vaslw(r1:0, #0)
+
+; Vector shift words by with truncate and pack
+declare i32 @llvm.hexagon.S2.asr.i.svw.trun(i64, i32)
+define i32 @S2_asr_i_svw_trun(i64 %a) {
+  %z = call i32 @llvm.hexagon.S2.asr.i.svw.trun(i64 %a, i32 0)
+  ret i32 %z
+}
+; CHECK: r0 = vasrw(r1:0, #0)
+
+declare i32 @llvm.hexagon.S2.asr.r.svw.trun(i64, i32)
+define i32 @S2_asr_r_svw_trun(i64 %a, i32 %b) {
+  %z = call i32 @llvm.hexagon.S2.asr.r.svw.trun(i64 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: r0 = vasrw(r1:0, r2)
diff --git a/test/CodeGen/Hexagon/macint.ll b/test/CodeGen/Hexagon/macint.ll
index b3b9d0ee7a01..514ba5b91308 100644
--- a/test/CodeGen/Hexagon/macint.ll
+++ b/test/CodeGen/Hexagon/macint.ll
@@ -1,11 +1,11 @@
 ; RUN: llc -march=hexagon -mcpu=hexagonv4  < %s | FileCheck %s
 ; Check that we generate integer multiply accumulate.
 
-; CHECK: r{{[0-9]+}} += mpyi(r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} {{\+|\-}}= mpyi(r{{[0-9]+}},
 
 define i32 @main(i32* %a, i32* %b) nounwind {
   entry:
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %div = udiv i32 %0, 10000
   %rem = urem i32 %div, 10
   store i32 %rem, i32* %b, align 4
diff --git a/test/CodeGen/Hexagon/mem-fi-add.ll b/test/CodeGen/Hexagon/mem-fi-add.ll
new file mode 100644
index 000000000000..a46029fdb5ec
--- /dev/null
+++ b/test/CodeGen/Hexagon/mem-fi-add.ll
@@ -0,0 +1,29 @@
+; RUN: llc -O2 < %s | FileCheck %s
+; Look for four stores directly via r29.
+; CHECK: memd(r29
+; CHECK: memd(r29
+; CHECK: memd(r29
+; CHECK: memd(r29
+
+target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
+target triple = "hexagon"
+
+; Function Attrs: nounwind
+define void @foo() #0 {
+entry:
+  %t = alloca [4 x [2 x i32]], align 8
+  %0 = bitcast [4 x [2 x i32]]* %t to i8*
+  call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 32, i32 8, i1 false)
+  %arraydecay = getelementptr inbounds [4 x [2 x i32]], [4 x [2 x i32]]* %t, i32 0, i32 0
+  call void @bar([2 x i32]* %arraydecay) #1
+  ret void
+}
+
+; Function Attrs: nounwind
+declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) #1
+
+declare void @bar([2 x i32]*) #2
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind }
+attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/CodeGen/Hexagon/memops.ll b/test/CodeGen/Hexagon/memops.ll
index fca1a73811a9..e4a8bf7c95e9 100644
--- a/test/CodeGen/Hexagon/memops.ll
+++ b/test/CodeGen/Hexagon/memops.ll
@@ -4,7 +4,7 @@
 define void @memop_unsigned_char_add5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
-  %0 = load i8* %p, align 1
+  %0 = load i8, i8* %p, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 5
   %conv1 = trunc i32 %add to i8
@@ -16,7 +16,7 @@ define void @memop_unsigned_char_add(i8* nocapture %p, i8 zeroext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
   %conv = zext i8 %x to i32
-  %0 = load i8* %p, align 1
+  %0 = load i8, i8* %p, align 1
   %conv1 = zext i8 %0 to i32
   %add = add nsw i32 %conv1, %conv
   %conv2 = trunc i32 %add to i8
@@ -28,7 +28,7 @@ define void @memop_unsigned_char_sub(i8* nocapture %p, i8 zeroext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
   %conv = zext i8 %x to i32
-  %0 = load i8* %p, align 1
+  %0 = load i8, i8* %p, align 1
   %conv1 = zext i8 %0 to i32
   %sub = sub nsw i32 %conv1, %conv
   %conv2 = trunc i32 %sub to i8
@@ -39,7 +39,7 @@ entry:
 define void @memop_unsigned_char_or(i8* nocapture %p, i8 zeroext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
-  %0 = load i8* %p, align 1
+  %0 = load i8, i8* %p, align 1
   %or3 = or i8 %0, %x
   store i8 %or3, i8* %p, align 1
   ret void
@@ -48,7 +48,7 @@ entry:
 define void @memop_unsigned_char_and(i8* nocapture %p, i8 zeroext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
-  %0 = load i8* %p, align 1
+  %0 = load i8, i8* %p, align 1
   %and3 = and i8 %0, %x
   store i8 %and3, i8* %p, align 1
   ret void
@@ -57,7 +57,7 @@ entry:
 define void @memop_unsigned_char_clrbit(i8* nocapture %p) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %0 = load i8* %p, align 1
+  %0 = load i8, i8* %p, align 1
   %conv = zext i8 %0 to i32
   %and = and i32 %conv, 223
   %conv1 = trunc i32 %and to i8
@@ -68,7 +68,7 @@ entry:
 define void @memop_unsigned_char_setbit(i8* nocapture %p) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %0 = load i8* %p, align 1
+  %0 = load i8, i8* %p, align 1
   %conv = zext i8 %0 to i32
   %or = or i32 %conv, 128
   %conv1 = trunc i32 %or to i8
@@ -79,8 +79,8 @@ entry:
 define void @memop_unsigned_char_add5_index(i8* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
-  %add.ptr = getelementptr inbounds i8* %p, i32 %i
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
+  %0 = load i8, i8* %add.ptr, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 5
   %conv1 = trunc i32 %add to i8
@@ -92,8 +92,8 @@ define void @memop_unsigned_char_add_index(i8* nocapture %p, i32 %i, i8 zeroext
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
   %conv = zext i8 %x to i32
-  %add.ptr = getelementptr inbounds i8* %p, i32 %i
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
+  %0 = load i8, i8* %add.ptr, align 1
   %conv1 = zext i8 %0 to i32
   %add = add nsw i32 %conv1, %conv
   %conv2 = trunc i32 %add to i8
@@ -105,8 +105,8 @@ define void @memop_unsigned_char_sub_index(i8* nocapture %p, i32 %i, i8 zeroext
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
   %conv = zext i8 %x to i32
-  %add.ptr = getelementptr inbounds i8* %p, i32 %i
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
+  %0 = load i8, i8* %add.ptr, align 1
   %conv1 = zext i8 %0 to i32
   %sub = sub nsw i32 %conv1, %conv
   %conv2 = trunc i32 %sub to i8
@@ -117,8 +117,8 @@ entry:
 define void @memop_unsigned_char_or_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i8* %p, i32 %i
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
+  %0 = load i8, i8* %add.ptr, align 1
   %or3 = or i8 %0, %x
   store i8 %or3, i8* %add.ptr, align 1
   ret void
@@ -127,8 +127,8 @@ entry:
 define void @memop_unsigned_char_and_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i8* %p, i32 %i
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
+  %0 = load i8, i8* %add.ptr, align 1
   %and3 = and i8 %0, %x
   store i8 %and3, i8* %add.ptr, align 1
   ret void
@@ -137,8 +137,8 @@ entry:
 define void @memop_unsigned_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %add.ptr = getelementptr inbounds i8* %p, i32 %i
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
+  %0 = load i8, i8* %add.ptr, align 1
   %conv = zext i8 %0 to i32
   %and = and i32 %conv, 223
   %conv1 = trunc i32 %and to i8
@@ -149,8 +149,8 @@ entry:
 define void @memop_unsigned_char_setbit_index(i8* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %add.ptr = getelementptr inbounds i8* %p, i32 %i
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
+  %0 = load i8, i8* %add.ptr, align 1
   %conv = zext i8 %0 to i32
   %or = or i32 %conv, 128
   %conv1 = trunc i32 %or to i8
@@ -161,8 +161,8 @@ entry:
 define void @memop_unsigned_char_add5_index5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5
-  %add.ptr = getelementptr inbounds i8* %p, i32 5
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
+  %0 = load i8, i8* %add.ptr, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 5
   %conv1 = trunc i32 %add to i8
@@ -174,8 +174,8 @@ define void @memop_unsigned_char_add_index5(i8* nocapture %p, i8 zeroext %x) nou
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}}
   %conv = zext i8 %x to i32
-  %add.ptr = getelementptr inbounds i8* %p, i32 5
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
+  %0 = load i8, i8* %add.ptr, align 1
   %conv1 = zext i8 %0 to i32
   %add = add nsw i32 %conv1, %conv
   %conv2 = trunc i32 %add to i8
@@ -187,8 +187,8 @@ define void @memop_unsigned_char_sub_index5(i8* nocapture %p, i8 zeroext %x) nou
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}}
   %conv = zext i8 %x to i32
-  %add.ptr = getelementptr inbounds i8* %p, i32 5
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
+  %0 = load i8, i8* %add.ptr, align 1
   %conv1 = zext i8 %0 to i32
   %sub = sub nsw i32 %conv1, %conv
   %conv2 = trunc i32 %sub to i8
@@ -199,8 +199,8 @@ entry:
 define void @memop_unsigned_char_or_index5(i8* nocapture %p, i8 zeroext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i8* %p, i32 5
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
+  %0 = load i8, i8* %add.ptr, align 1
   %or3 = or i8 %0, %x
   store i8 %or3, i8* %add.ptr, align 1
   ret void
@@ -209,8 +209,8 @@ entry:
 define void @memop_unsigned_char_and_index5(i8* nocapture %p, i8 zeroext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i8* %p, i32 5
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
+  %0 = load i8, i8* %add.ptr, align 1
   %and3 = and i8 %0, %x
   store i8 %and3, i8* %add.ptr, align 1
   ret void
@@ -219,8 +219,8 @@ entry:
 define void @memop_unsigned_char_clrbit_index5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %add.ptr = getelementptr inbounds i8* %p, i32 5
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
+  %0 = load i8, i8* %add.ptr, align 1
   %conv = zext i8 %0 to i32
   %and = and i32 %conv, 223
   %conv1 = trunc i32 %and to i8
@@ -231,8 +231,8 @@ entry:
 define void @memop_unsigned_char_setbit_index5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %add.ptr = getelementptr inbounds i8* %p, i32 5
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
+  %0 = load i8, i8* %add.ptr, align 1
   %conv = zext i8 %0 to i32
   %or = or i32 %conv, 128
   %conv1 = trunc i32 %or to i8
@@ -243,7 +243,7 @@ entry:
 define void @memop_signed_char_add5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
-  %0 = load i8* %p, align 1
+  %0 = load i8, i8* %p, align 1
   %conv2 = zext i8 %0 to i32
   %add = add nsw i32 %conv2, 5
   %conv1 = trunc i32 %add to i8
@@ -255,7 +255,7 @@ define void @memop_signed_char_add(i8* nocapture %p, i8 signext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
   %conv4 = zext i8 %x to i32
-  %0 = load i8* %p, align 1
+  %0 = load i8, i8* %p, align 1
   %conv13 = zext i8 %0 to i32
   %add = add nsw i32 %conv13, %conv4
   %conv2 = trunc i32 %add to i8
@@ -267,7 +267,7 @@ define void @memop_signed_char_sub(i8* nocapture %p, i8 signext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
   %conv4 = zext i8 %x to i32
-  %0 = load i8* %p, align 1
+  %0 = load i8, i8* %p, align 1
   %conv13 = zext i8 %0 to i32
   %sub = sub nsw i32 %conv13, %conv4
   %conv2 = trunc i32 %sub to i8
@@ -278,7 +278,7 @@ entry:
 define void @memop_signed_char_or(i8* nocapture %p, i8 signext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
-  %0 = load i8* %p, align 1
+  %0 = load i8, i8* %p, align 1
   %or3 = or i8 %0, %x
   store i8 %or3, i8* %p, align 1
   ret void
@@ -287,7 +287,7 @@ entry:
 define void @memop_signed_char_and(i8* nocapture %p, i8 signext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
-  %0 = load i8* %p, align 1
+  %0 = load i8, i8* %p, align 1
   %and3 = and i8 %0, %x
   store i8 %and3, i8* %p, align 1
   ret void
@@ -296,7 +296,7 @@ entry:
 define void @memop_signed_char_clrbit(i8* nocapture %p) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %0 = load i8* %p, align 1
+  %0 = load i8, i8* %p, align 1
   %conv2 = zext i8 %0 to i32
   %and = and i32 %conv2, 223
   %conv1 = trunc i32 %and to i8
@@ -307,7 +307,7 @@ entry:
 define void @memop_signed_char_setbit(i8* nocapture %p) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %0 = load i8* %p, align 1
+  %0 = load i8, i8* %p, align 1
   %conv2 = zext i8 %0 to i32
   %or = or i32 %conv2, 128
   %conv1 = trunc i32 %or to i8
@@ -318,8 +318,8 @@ entry:
 define void @memop_signed_char_add5_index(i8* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
-  %add.ptr = getelementptr inbounds i8* %p, i32 %i
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
+  %0 = load i8, i8* %add.ptr, align 1
   %conv2 = zext i8 %0 to i32
   %add = add nsw i32 %conv2, 5
   %conv1 = trunc i32 %add to i8
@@ -331,8 +331,8 @@ define void @memop_signed_char_add_index(i8* nocapture %p, i32 %i, i8 signext %x
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
   %conv4 = zext i8 %x to i32
-  %add.ptr = getelementptr inbounds i8* %p, i32 %i
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
+  %0 = load i8, i8* %add.ptr, align 1
   %conv13 = zext i8 %0 to i32
   %add = add nsw i32 %conv13, %conv4
   %conv2 = trunc i32 %add to i8
@@ -344,8 +344,8 @@ define void @memop_signed_char_sub_index(i8* nocapture %p, i32 %i, i8 signext %x
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
   %conv4 = zext i8 %x to i32
-  %add.ptr = getelementptr inbounds i8* %p, i32 %i
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
+  %0 = load i8, i8* %add.ptr, align 1
   %conv13 = zext i8 %0 to i32
   %sub = sub nsw i32 %conv13, %conv4
   %conv2 = trunc i32 %sub to i8
@@ -356,8 +356,8 @@ entry:
 define void @memop_signed_char_or_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i8* %p, i32 %i
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
+  %0 = load i8, i8* %add.ptr, align 1
   %or3 = or i8 %0, %x
   store i8 %or3, i8* %add.ptr, align 1
   ret void
@@ -366,8 +366,8 @@ entry:
 define void @memop_signed_char_and_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i8* %p, i32 %i
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
+  %0 = load i8, i8* %add.ptr, align 1
   %and3 = and i8 %0, %x
   store i8 %and3, i8* %add.ptr, align 1
   ret void
@@ -376,8 +376,8 @@ entry:
 define void @memop_signed_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %add.ptr = getelementptr inbounds i8* %p, i32 %i
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
+  %0 = load i8, i8* %add.ptr, align 1
   %conv2 = zext i8 %0 to i32
   %and = and i32 %conv2, 223
   %conv1 = trunc i32 %and to i8
@@ -388,8 +388,8 @@ entry:
 define void @memop_signed_char_setbit_index(i8* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %add.ptr = getelementptr inbounds i8* %p, i32 %i
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
+  %0 = load i8, i8* %add.ptr, align 1
   %conv2 = zext i8 %0 to i32
   %or = or i32 %conv2, 128
   %conv1 = trunc i32 %or to i8
@@ -400,8 +400,8 @@ entry:
 define void @memop_signed_char_add5_index5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5
-  %add.ptr = getelementptr inbounds i8* %p, i32 5
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
+  %0 = load i8, i8* %add.ptr, align 1
   %conv2 = zext i8 %0 to i32
   %add = add nsw i32 %conv2, 5
   %conv1 = trunc i32 %add to i8
@@ -413,8 +413,8 @@ define void @memop_signed_char_add_index5(i8* nocapture %p, i8 signext %x) nounw
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}}
   %conv4 = zext i8 %x to i32
-  %add.ptr = getelementptr inbounds i8* %p, i32 5
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
+  %0 = load i8, i8* %add.ptr, align 1
   %conv13 = zext i8 %0 to i32
   %add = add nsw i32 %conv13, %conv4
   %conv2 = trunc i32 %add to i8
@@ -426,8 +426,8 @@ define void @memop_signed_char_sub_index5(i8* nocapture %p, i8 signext %x) nounw
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}}
   %conv4 = zext i8 %x to i32
-  %add.ptr = getelementptr inbounds i8* %p, i32 5
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
+  %0 = load i8, i8* %add.ptr, align 1
   %conv13 = zext i8 %0 to i32
   %sub = sub nsw i32 %conv13, %conv4
   %conv2 = trunc i32 %sub to i8
@@ -438,8 +438,8 @@ entry:
 define void @memop_signed_char_or_index5(i8* nocapture %p, i8 signext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i8* %p, i32 5
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
+  %0 = load i8, i8* %add.ptr, align 1
   %or3 = or i8 %0, %x
   store i8 %or3, i8* %add.ptr, align 1
   ret void
@@ -448,8 +448,8 @@ entry:
 define void @memop_signed_char_and_index5(i8* nocapture %p, i8 signext %x) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i8* %p, i32 5
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
+  %0 = load i8, i8* %add.ptr, align 1
   %and3 = and i8 %0, %x
   store i8 %and3, i8* %add.ptr, align 1
   ret void
@@ -458,8 +458,8 @@ entry:
 define void @memop_signed_char_clrbit_index5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %add.ptr = getelementptr inbounds i8* %p, i32 5
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
+  %0 = load i8, i8* %add.ptr, align 1
   %conv2 = zext i8 %0 to i32
   %and = and i32 %conv2, 223
   %conv1 = trunc i32 %and to i8
@@ -470,8 +470,8 @@ entry:
 define void @memop_signed_char_setbit_index5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %add.ptr = getelementptr inbounds i8* %p, i32 5
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
+  %0 = load i8, i8* %add.ptr, align 1
   %conv2 = zext i8 %0 to i32
   %or = or i32 %conv2, 128
   %conv1 = trunc i32 %or to i8
@@ -482,7 +482,7 @@ entry:
 define void @memop_unsigned_short_add5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
-  %0 = load i16* %p, align 2
+  %0 = load i16, i16* %p, align 2
   %conv = zext i16 %0 to i32
   %add = add nsw i32 %conv, 5
   %conv1 = trunc i32 %add to i16
@@ -494,7 +494,7 @@ define void @memop_unsigned_short_add(i16* nocapture %p, i16 zeroext %x) nounwin
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
   %conv = zext i16 %x to i32
-  %0 = load i16* %p, align 2
+  %0 = load i16, i16* %p, align 2
   %conv1 = zext i16 %0 to i32
   %add = add nsw i32 %conv1, %conv
   %conv2 = trunc i32 %add to i16
@@ -506,7 +506,7 @@ define void @memop_unsigned_short_sub(i16* nocapture %p, i16 zeroext %x) nounwin
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
   %conv = zext i16 %x to i32
-  %0 = load i16* %p, align 2
+  %0 = load i16, i16* %p, align 2
   %conv1 = zext i16 %0 to i32
   %sub = sub nsw i32 %conv1, %conv
   %conv2 = trunc i32 %sub to i16
@@ -517,7 +517,7 @@ entry:
 define void @memop_unsigned_short_or(i16* nocapture %p, i16 zeroext %x) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
-  %0 = load i16* %p, align 2
+  %0 = load i16, i16* %p, align 2
   %or3 = or i16 %0, %x
   store i16 %or3, i16* %p, align 2
   ret void
@@ -526,7 +526,7 @@ entry:
 define void @memop_unsigned_short_and(i16* nocapture %p, i16 zeroext %x) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
-  %0 = load i16* %p, align 2
+  %0 = load i16, i16* %p, align 2
   %and3 = and i16 %0, %x
   store i16 %and3, i16* %p, align 2
   ret void
@@ -535,7 +535,7 @@ entry:
 define void @memop_unsigned_short_clrbit(i16* nocapture %p) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %0 = load i16* %p, align 2
+  %0 = load i16, i16* %p, align 2
   %conv = zext i16 %0 to i32
   %and = and i32 %conv, 65503
   %conv1 = trunc i32 %and to i16
@@ -546,7 +546,7 @@ entry:
 define void @memop_unsigned_short_setbit(i16* nocapture %p) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %0 = load i16* %p, align 2
+  %0 = load i16, i16* %p, align 2
   %conv = zext i16 %0 to i32
   %or = or i32 %conv, 128
   %conv1 = trunc i32 %or to i16
@@ -557,8 +557,8 @@ entry:
 define void @memop_unsigned_short_add5_index(i16* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
-  %add.ptr = getelementptr inbounds i16* %p, i32 %i
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
+  %0 = load i16, i16* %add.ptr, align 2
   %conv = zext i16 %0 to i32
   %add = add nsw i32 %conv, 5
   %conv1 = trunc i32 %add to i16
@@ -570,8 +570,8 @@ define void @memop_unsigned_short_add_index(i16* nocapture %p, i32 %i, i16 zeroe
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
   %conv = zext i16 %x to i32
-  %add.ptr = getelementptr inbounds i16* %p, i32 %i
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
+  %0 = load i16, i16* %add.ptr, align 2
   %conv1 = zext i16 %0 to i32
   %add = add nsw i32 %conv1, %conv
   %conv2 = trunc i32 %add to i16
@@ -583,8 +583,8 @@ define void @memop_unsigned_short_sub_index(i16* nocapture %p, i32 %i, i16 zeroe
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
   %conv = zext i16 %x to i32
-  %add.ptr = getelementptr inbounds i16* %p, i32 %i
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
+  %0 = load i16, i16* %add.ptr, align 2
   %conv1 = zext i16 %0 to i32
   %sub = sub nsw i32 %conv1, %conv
   %conv2 = trunc i32 %sub to i16
@@ -595,8 +595,8 @@ entry:
 define void @memop_unsigned_short_or_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i16* %p, i32 %i
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
+  %0 = load i16, i16* %add.ptr, align 2
   %or3 = or i16 %0, %x
   store i16 %or3, i16* %add.ptr, align 2
   ret void
@@ -605,8 +605,8 @@ entry:
 define void @memop_unsigned_short_and_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i16* %p, i32 %i
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
+  %0 = load i16, i16* %add.ptr, align 2
   %and3 = and i16 %0, %x
   store i16 %and3, i16* %add.ptr, align 2
   ret void
@@ -615,8 +615,8 @@ entry:
 define void @memop_unsigned_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %add.ptr = getelementptr inbounds i16* %p, i32 %i
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
+  %0 = load i16, i16* %add.ptr, align 2
   %conv = zext i16 %0 to i32
   %and = and i32 %conv, 65503
   %conv1 = trunc i32 %and to i16
@@ -627,8 +627,8 @@ entry:
 define void @memop_unsigned_short_setbit_index(i16* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %add.ptr = getelementptr inbounds i16* %p, i32 %i
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
+  %0 = load i16, i16* %add.ptr, align 2
   %conv = zext i16 %0 to i32
   %or = or i32 %conv, 128
   %conv1 = trunc i32 %or to i16
@@ -639,8 +639,8 @@ entry:
 define void @memop_unsigned_short_add5_index5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5
-  %add.ptr = getelementptr inbounds i16* %p, i32 5
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
+  %0 = load i16, i16* %add.ptr, align 2
   %conv = zext i16 %0 to i32
   %add = add nsw i32 %conv, 5
   %conv1 = trunc i32 %add to i16
@@ -652,8 +652,8 @@ define void @memop_unsigned_short_add_index5(i16* nocapture %p, i16 zeroext %x)
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}}
   %conv = zext i16 %x to i32
-  %add.ptr = getelementptr inbounds i16* %p, i32 5
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
+  %0 = load i16, i16* %add.ptr, align 2
   %conv1 = zext i16 %0 to i32
   %add = add nsw i32 %conv1, %conv
   %conv2 = trunc i32 %add to i16
@@ -665,8 +665,8 @@ define void @memop_unsigned_short_sub_index5(i16* nocapture %p, i16 zeroext %x)
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}}
   %conv = zext i16 %x to i32
-  %add.ptr = getelementptr inbounds i16* %p, i32 5
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
+  %0 = load i16, i16* %add.ptr, align 2
   %conv1 = zext i16 %0 to i32
   %sub = sub nsw i32 %conv1, %conv
   %conv2 = trunc i32 %sub to i16
@@ -677,8 +677,8 @@ entry:
 define void @memop_unsigned_short_or_index5(i16* nocapture %p, i16 zeroext %x) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i16* %p, i32 5
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
+  %0 = load i16, i16* %add.ptr, align 2
   %or3 = or i16 %0, %x
   store i16 %or3, i16* %add.ptr, align 2
   ret void
@@ -687,8 +687,8 @@ entry:
 define void @memop_unsigned_short_and_index5(i16* nocapture %p, i16 zeroext %x) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i16* %p, i32 5
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
+  %0 = load i16, i16* %add.ptr, align 2
   %and3 = and i16 %0, %x
   store i16 %and3, i16* %add.ptr, align 2
   ret void
@@ -697,8 +697,8 @@ entry:
 define void @memop_unsigned_short_clrbit_index5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %add.ptr = getelementptr inbounds i16* %p, i32 5
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
+  %0 = load i16, i16* %add.ptr, align 2
   %conv = zext i16 %0 to i32
   %and = and i32 %conv, 65503
   %conv1 = trunc i32 %and to i16
@@ -709,8 +709,8 @@ entry:
 define void @memop_unsigned_short_setbit_index5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %add.ptr = getelementptr inbounds i16* %p, i32 5
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
+  %0 = load i16, i16* %add.ptr, align 2
   %conv = zext i16 %0 to i32
   %or = or i32 %conv, 128
   %conv1 = trunc i32 %or to i16
@@ -721,7 +721,7 @@ entry:
 define void @memop_signed_short_add5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
-  %0 = load i16* %p, align 2
+  %0 = load i16, i16* %p, align 2
   %conv2 = zext i16 %0 to i32
   %add = add nsw i32 %conv2, 5
   %conv1 = trunc i32 %add to i16
@@ -733,7 +733,7 @@ define void @memop_signed_short_add(i16* nocapture %p, i16 signext %x) nounwind
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
   %conv4 = zext i16 %x to i32
-  %0 = load i16* %p, align 2
+  %0 = load i16, i16* %p, align 2
   %conv13 = zext i16 %0 to i32
   %add = add nsw i32 %conv13, %conv4
   %conv2 = trunc i32 %add to i16
@@ -745,7 +745,7 @@ define void @memop_signed_short_sub(i16* nocapture %p, i16 signext %x) nounwind
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
   %conv4 = zext i16 %x to i32
-  %0 = load i16* %p, align 2
+  %0 = load i16, i16* %p, align 2
   %conv13 = zext i16 %0 to i32
   %sub = sub nsw i32 %conv13, %conv4
   %conv2 = trunc i32 %sub to i16
@@ -756,7 +756,7 @@ entry:
 define void @memop_signed_short_or(i16* nocapture %p, i16 signext %x) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
-  %0 = load i16* %p, align 2
+  %0 = load i16, i16* %p, align 2
   %or3 = or i16 %0, %x
   store i16 %or3, i16* %p, align 2
   ret void
@@ -765,7 +765,7 @@ entry:
 define void @memop_signed_short_and(i16* nocapture %p, i16 signext %x) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
-  %0 = load i16* %p, align 2
+  %0 = load i16, i16* %p, align 2
   %and3 = and i16 %0, %x
   store i16 %and3, i16* %p, align 2
   ret void
@@ -774,7 +774,7 @@ entry:
 define void @memop_signed_short_clrbit(i16* nocapture %p) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %0 = load i16* %p, align 2
+  %0 = load i16, i16* %p, align 2
   %conv2 = zext i16 %0 to i32
   %and = and i32 %conv2, 65503
   %conv1 = trunc i32 %and to i16
@@ -785,7 +785,7 @@ entry:
 define void @memop_signed_short_setbit(i16* nocapture %p) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %0 = load i16* %p, align 2
+  %0 = load i16, i16* %p, align 2
   %conv2 = zext i16 %0 to i32
   %or = or i32 %conv2, 128
   %conv1 = trunc i32 %or to i16
@@ -796,8 +796,8 @@ entry:
 define void @memop_signed_short_add5_index(i16* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
-  %add.ptr = getelementptr inbounds i16* %p, i32 %i
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
+  %0 = load i16, i16* %add.ptr, align 2
   %conv2 = zext i16 %0 to i32
   %add = add nsw i32 %conv2, 5
   %conv1 = trunc i32 %add to i16
@@ -809,8 +809,8 @@ define void @memop_signed_short_add_index(i16* nocapture %p, i32 %i, i16 signext
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
   %conv4 = zext i16 %x to i32
-  %add.ptr = getelementptr inbounds i16* %p, i32 %i
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
+  %0 = load i16, i16* %add.ptr, align 2
   %conv13 = zext i16 %0 to i32
   %add = add nsw i32 %conv13, %conv4
   %conv2 = trunc i32 %add to i16
@@ -822,8 +822,8 @@ define void @memop_signed_short_sub_index(i16* nocapture %p, i32 %i, i16 signext
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
   %conv4 = zext i16 %x to i32
-  %add.ptr = getelementptr inbounds i16* %p, i32 %i
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
+  %0 = load i16, i16* %add.ptr, align 2
   %conv13 = zext i16 %0 to i32
   %sub = sub nsw i32 %conv13, %conv4
   %conv2 = trunc i32 %sub to i16
@@ -834,8 +834,8 @@ entry:
 define void @memop_signed_short_or_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i16* %p, i32 %i
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
+  %0 = load i16, i16* %add.ptr, align 2
   %or3 = or i16 %0, %x
   store i16 %or3, i16* %add.ptr, align 2
   ret void
@@ -844,8 +844,8 @@ entry:
 define void @memop_signed_short_and_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i16* %p, i32 %i
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
+  %0 = load i16, i16* %add.ptr, align 2
   %and3 = and i16 %0, %x
   store i16 %and3, i16* %add.ptr, align 2
   ret void
@@ -854,8 +854,8 @@ entry:
 define void @memop_signed_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %add.ptr = getelementptr inbounds i16* %p, i32 %i
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
+  %0 = load i16, i16* %add.ptr, align 2
   %conv2 = zext i16 %0 to i32
   %and = and i32 %conv2, 65503
   %conv1 = trunc i32 %and to i16
@@ -866,8 +866,8 @@ entry:
 define void @memop_signed_short_setbit_index(i16* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %add.ptr = getelementptr inbounds i16* %p, i32 %i
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
+  %0 = load i16, i16* %add.ptr, align 2
   %conv2 = zext i16 %0 to i32
   %or = or i32 %conv2, 128
   %conv1 = trunc i32 %or to i16
@@ -878,8 +878,8 @@ entry:
 define void @memop_signed_short_add5_index5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5
-  %add.ptr = getelementptr inbounds i16* %p, i32 5
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
+  %0 = load i16, i16* %add.ptr, align 2
   %conv2 = zext i16 %0 to i32
   %add = add nsw i32 %conv2, 5
   %conv1 = trunc i32 %add to i16
@@ -891,8 +891,8 @@ define void @memop_signed_short_add_index5(i16* nocapture %p, i16 signext %x) no
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}}
   %conv4 = zext i16 %x to i32
-  %add.ptr = getelementptr inbounds i16* %p, i32 5
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
+  %0 = load i16, i16* %add.ptr, align 2
   %conv13 = zext i16 %0 to i32
   %add = add nsw i32 %conv13, %conv4
   %conv2 = trunc i32 %add to i16
@@ -904,8 +904,8 @@ define void @memop_signed_short_sub_index5(i16* nocapture %p, i16 signext %x) no
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}}
   %conv4 = zext i16 %x to i32
-  %add.ptr = getelementptr inbounds i16* %p, i32 5
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
+  %0 = load i16, i16* %add.ptr, align 2
   %conv13 = zext i16 %0 to i32
   %sub = sub nsw i32 %conv13, %conv4
   %conv2 = trunc i32 %sub to i16
@@ -916,8 +916,8 @@ entry:
 define void @memop_signed_short_or_index5(i16* nocapture %p, i16 signext %x) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i16* %p, i32 5
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
+  %0 = load i16, i16* %add.ptr, align 2
   %or3 = or i16 %0, %x
   store i16 %or3, i16* %add.ptr, align 2
   ret void
@@ -926,8 +926,8 @@ entry:
 define void @memop_signed_short_and_index5(i16* nocapture %p, i16 signext %x) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i16* %p, i32 5
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
+  %0 = load i16, i16* %add.ptr, align 2
   %and3 = and i16 %0, %x
   store i16 %and3, i16* %add.ptr, align 2
   ret void
@@ -936,8 +936,8 @@ entry:
 define void @memop_signed_short_clrbit_index5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %add.ptr = getelementptr inbounds i16* %p, i32 5
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
+  %0 = load i16, i16* %add.ptr, align 2
   %conv2 = zext i16 %0 to i32
   %and = and i32 %conv2, 65503
   %conv1 = trunc i32 %and to i16
@@ -948,8 +948,8 @@ entry:
 define void @memop_signed_short_setbit_index5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %add.ptr = getelementptr inbounds i16* %p, i32 5
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
+  %0 = load i16, i16* %add.ptr, align 2
   %conv2 = zext i16 %0 to i32
   %or = or i32 %conv2, 128
   %conv1 = trunc i32 %or to i16
@@ -960,7 +960,7 @@ entry:
 define void @memop_signed_int_add5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   %add = add i32 %0, 5
   store i32 %add, i32* %p, align 4
   ret void
@@ -969,7 +969,7 @@ entry:
 define void @memop_signed_int_add(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   %add = add i32 %0, %x
   store i32 %add, i32* %p, align 4
   ret void
@@ -978,7 +978,7 @@ entry:
 define void @memop_signed_int_sub(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   %sub = sub i32 %0, %x
   store i32 %sub, i32* %p, align 4
   ret void
@@ -987,7 +987,7 @@ entry:
 define void @memop_signed_int_or(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   %or = or i32 %0, %x
   store i32 %or, i32* %p, align 4
   ret void
@@ -996,7 +996,7 @@ entry:
 define void @memop_signed_int_and(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   %and = and i32 %0, %x
   store i32 %and, i32* %p, align 4
   ret void
@@ -1005,7 +1005,7 @@ entry:
 define void @memop_signed_int_clrbit(i32* nocapture %p) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   %and = and i32 %0, -33
   store i32 %and, i32* %p, align 4
   ret void
@@ -1014,7 +1014,7 @@ entry:
 define void @memop_signed_int_setbit(i32* nocapture %p) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   %or = or i32 %0, 128
   store i32 %or, i32* %p, align 4
   ret void
@@ -1023,8 +1023,8 @@ entry:
 define void @memop_signed_int_add5_index(i32* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
-  %add.ptr = getelementptr inbounds i32* %p, i32 %i
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
+  %0 = load i32, i32* %add.ptr, align 4
   %add = add i32 %0, 5
   store i32 %add, i32* %add.ptr, align 4
   ret void
@@ -1033,8 +1033,8 @@ entry:
 define void @memop_signed_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 %i
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
+  %0 = load i32, i32* %add.ptr, align 4
   %add = add i32 %0, %x
   store i32 %add, i32* %add.ptr, align 4
   ret void
@@ -1043,8 +1043,8 @@ entry:
 define void @memop_signed_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 %i
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
+  %0 = load i32, i32* %add.ptr, align 4
   %sub = sub i32 %0, %x
   store i32 %sub, i32* %add.ptr, align 4
   ret void
@@ -1053,8 +1053,8 @@ entry:
 define void @memop_signed_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 %i
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
+  %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, %x
   store i32 %or, i32* %add.ptr, align 4
   ret void
@@ -1063,8 +1063,8 @@ entry:
 define void @memop_signed_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 %i
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
+  %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, %x
   store i32 %and, i32* %add.ptr, align 4
   ret void
@@ -1073,8 +1073,8 @@ entry:
 define void @memop_signed_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %add.ptr = getelementptr inbounds i32* %p, i32 %i
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
+  %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, -33
   store i32 %and, i32* %add.ptr, align 4
   ret void
@@ -1083,8 +1083,8 @@ entry:
 define void @memop_signed_int_setbit_index(i32* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %add.ptr = getelementptr inbounds i32* %p, i32 %i
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
+  %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, 128
   store i32 %or, i32* %add.ptr, align 4
   ret void
@@ -1093,8 +1093,8 @@ entry:
 define void @memop_signed_int_add5_index5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5
-  %add.ptr = getelementptr inbounds i32* %p, i32 5
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
+  %0 = load i32, i32* %add.ptr, align 4
   %add = add i32 %0, 5
   store i32 %add, i32* %add.ptr, align 4
   ret void
@@ -1103,8 +1103,8 @@ entry:
 define void @memop_signed_int_add_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 5
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
+  %0 = load i32, i32* %add.ptr, align 4
   %add = add i32 %0, %x
   store i32 %add, i32* %add.ptr, align 4
   ret void
@@ -1113,8 +1113,8 @@ entry:
 define void @memop_signed_int_sub_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 5
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
+  %0 = load i32, i32* %add.ptr, align 4
   %sub = sub i32 %0, %x
   store i32 %sub, i32* %add.ptr, align 4
   ret void
@@ -1123,8 +1123,8 @@ entry:
 define void @memop_signed_int_or_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 5
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
+  %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, %x
   store i32 %or, i32* %add.ptr, align 4
   ret void
@@ -1133,8 +1133,8 @@ entry:
 define void @memop_signed_int_and_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 5
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
+  %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, %x
   store i32 %and, i32* %add.ptr, align 4
   ret void
@@ -1143,8 +1143,8 @@ entry:
 define void @memop_signed_int_clrbit_index5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %add.ptr = getelementptr inbounds i32* %p, i32 5
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
+  %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, -33
   store i32 %and, i32* %add.ptr, align 4
   ret void
@@ -1153,8 +1153,8 @@ entry:
 define void @memop_signed_int_setbit_index5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %add.ptr = getelementptr inbounds i32* %p, i32 5
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
+  %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, 128
   store i32 %or, i32* %add.ptr, align 4
   ret void
@@ -1163,7 +1163,7 @@ entry:
 define void @memop_unsigned_int_add5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   %add = add nsw i32 %0, 5
   store i32 %add, i32* %p, align 4
   ret void
@@ -1172,7 +1172,7 @@ entry:
 define void @memop_unsigned_int_add(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   %add = add nsw i32 %0, %x
   store i32 %add, i32* %p, align 4
   ret void
@@ -1181,7 +1181,7 @@ entry:
 define void @memop_unsigned_int_sub(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   %sub = sub nsw i32 %0, %x
   store i32 %sub, i32* %p, align 4
   ret void
@@ -1190,7 +1190,7 @@ entry:
 define void @memop_unsigned_int_or(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   %or = or i32 %0, %x
   store i32 %or, i32* %p, align 4
   ret void
@@ -1199,7 +1199,7 @@ entry:
 define void @memop_unsigned_int_and(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   %and = and i32 %0, %x
   store i32 %and, i32* %p, align 4
   ret void
@@ -1208,7 +1208,7 @@ entry:
 define void @memop_unsigned_int_clrbit(i32* nocapture %p) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   %and = and i32 %0, -33
   store i32 %and, i32* %p, align 4
   ret void
@@ -1217,7 +1217,7 @@ entry:
 define void @memop_unsigned_int_setbit(i32* nocapture %p) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   %or = or i32 %0, 128
   store i32 %or, i32* %p, align 4
   ret void
@@ -1226,8 +1226,8 @@ entry:
 define void @memop_unsigned_int_add5_index(i32* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
-  %add.ptr = getelementptr inbounds i32* %p, i32 %i
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
+  %0 = load i32, i32* %add.ptr, align 4
   %add = add nsw i32 %0, 5
   store i32 %add, i32* %add.ptr, align 4
   ret void
@@ -1236,8 +1236,8 @@ entry:
 define void @memop_unsigned_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 %i
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
+  %0 = load i32, i32* %add.ptr, align 4
   %add = add nsw i32 %0, %x
   store i32 %add, i32* %add.ptr, align 4
   ret void
@@ -1246,8 +1246,8 @@ entry:
 define void @memop_unsigned_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 %i
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
+  %0 = load i32, i32* %add.ptr, align 4
   %sub = sub nsw i32 %0, %x
   store i32 %sub, i32* %add.ptr, align 4
   ret void
@@ -1256,8 +1256,8 @@ entry:
 define void @memop_unsigned_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 %i
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
+  %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, %x
   store i32 %or, i32* %add.ptr, align 4
   ret void
@@ -1266,8 +1266,8 @@ entry:
 define void @memop_unsigned_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 %i
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
+  %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, %x
   store i32 %and, i32* %add.ptr, align 4
   ret void
@@ -1276,8 +1276,8 @@ entry:
 define void @memop_unsigned_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %add.ptr = getelementptr inbounds i32* %p, i32 %i
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
+  %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, -33
   store i32 %and, i32* %add.ptr, align 4
   ret void
@@ -1286,8 +1286,8 @@ entry:
 define void @memop_unsigned_int_setbit_index(i32* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %add.ptr = getelementptr inbounds i32* %p, i32 %i
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
+  %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, 128
   store i32 %or, i32* %add.ptr, align 4
   ret void
@@ -1296,8 +1296,8 @@ entry:
 define void @memop_unsigned_int_add5_index5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5
-  %add.ptr = getelementptr inbounds i32* %p, i32 5
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
+  %0 = load i32, i32* %add.ptr, align 4
   %add = add nsw i32 %0, 5
   store i32 %add, i32* %add.ptr, align 4
   ret void
@@ -1306,8 +1306,8 @@ entry:
 define void @memop_unsigned_int_add_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 5
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
+  %0 = load i32, i32* %add.ptr, align 4
   %add = add nsw i32 %0, %x
   store i32 %add, i32* %add.ptr, align 4
   ret void
@@ -1316,8 +1316,8 @@ entry:
 define void @memop_unsigned_int_sub_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 5
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
+  %0 = load i32, i32* %add.ptr, align 4
   %sub = sub nsw i32 %0, %x
   store i32 %sub, i32* %add.ptr, align 4
   ret void
@@ -1326,8 +1326,8 @@ entry:
 define void @memop_unsigned_int_or_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 5
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
+  %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, %x
   store i32 %or, i32* %add.ptr, align 4
   ret void
@@ -1336,8 +1336,8 @@ entry:
 define void @memop_unsigned_int_and_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}}
-  %add.ptr = getelementptr inbounds i32* %p, i32 5
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
+  %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, %x
   store i32 %and, i32* %add.ptr, align 4
   ret void
@@ -1346,8 +1346,8 @@ entry:
 define void @memop_unsigned_int_clrbit_index5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
-  %add.ptr = getelementptr inbounds i32* %p, i32 5
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
+  %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, -33
   store i32 %and, i32* %add.ptr, align 4
   ret void
@@ -1356,8 +1356,8 @@ entry:
 define void @memop_unsigned_int_setbit_index5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
-  %add.ptr = getelementptr inbounds i32* %p, i32 5
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
+  %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, 128
   store i32 %or, i32* %add.ptr, align 4
   ret void
diff --git a/test/CodeGen/Hexagon/memops1.ll b/test/CodeGen/Hexagon/memops1.ll
index 2babdc848ddc..37e885b6e0cb 100644
--- a/test/CodeGen/Hexagon/memops1.ll
+++ b/test/CodeGen/Hexagon/memops1.ll
@@ -7,9 +7,9 @@ entry:
 ; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#40){{ *}}-={{ *}}#1
   %p.addr = alloca i32*, align 4
   store i32* %p, i32** %p.addr, align 4
-  %0 = load i32** %p.addr, align 4
-  %add.ptr = getelementptr inbounds i32* %0, i32 10
-  %1 = load i32* %add.ptr, align 4
+  %0 = load i32*, i32** %p.addr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %0, i32 10
+  %1 = load i32, i32* %add.ptr, align 4
   %sub = sub nsw i32 %1, 1
   store i32 %sub, i32* %add.ptr, align 4
   ret void
@@ -22,11 +22,11 @@ entry:
   %i.addr = alloca i32, align 4
   store i32* %p, i32** %p.addr, align 4
   store i32 %i, i32* %i.addr, align 4
-  %0 = load i32** %p.addr, align 4
-  %1 = load i32* %i.addr, align 4
-  %add.ptr = getelementptr inbounds i32* %0, i32 %1
-  %add.ptr1 = getelementptr inbounds i32* %add.ptr, i32 10
-  %2 = load i32* %add.ptr1, align 4
+  %0 = load i32*, i32** %p.addr, align 4
+  %1 = load i32, i32* %i.addr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %0, i32 %1
+  %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10
+  %2 = load i32, i32* %add.ptr1, align 4
   %sub = sub nsw i32 %2, 1
   store i32 %sub, i32* %add.ptr1, align 4
   ret void
diff --git a/test/CodeGen/Hexagon/memops2.ll b/test/CodeGen/Hexagon/memops2.ll
index d6d1a50bcefa..f9f8a2478119 100644
--- a/test/CodeGen/Hexagon/memops2.ll
+++ b/test/CodeGen/Hexagon/memops2.ll
@@ -5,8 +5,8 @@
 define void @f(i16* nocapture %p) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}#1
-  %add.ptr = getelementptr inbounds i16* %p, i32 10
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %p, i32 10
+  %0 = load i16, i16* %add.ptr, align 2
   %conv2 = zext i16 %0 to i32
   %sub = add nsw i32 %conv2, 65535
   %conv1 = trunc i32 %sub to i16
@@ -18,8 +18,8 @@ define void @g(i16* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}#1
   %add.ptr.sum = add i32 %i, 10
-  %add.ptr1 = getelementptr inbounds i16* %p, i32 %add.ptr.sum
-  %0 = load i16* %add.ptr1, align 2
+  %add.ptr1 = getelementptr inbounds i16, i16* %p, i32 %add.ptr.sum
+  %0 = load i16, i16* %add.ptr1, align 2
   %conv3 = zext i16 %0 to i32
   %sub = add nsw i32 %conv3, 65535
   %conv2 = trunc i32 %sub to i16
diff --git a/test/CodeGen/Hexagon/memops3.ll b/test/CodeGen/Hexagon/memops3.ll
index d9e4e8f53709..6cd7fdc48617 100644
--- a/test/CodeGen/Hexagon/memops3.ll
+++ b/test/CodeGen/Hexagon/memops3.ll
@@ -5,8 +5,8 @@
 define void @f(i8* nocapture %p) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}#1
-  %add.ptr = getelementptr inbounds i8* %p, i32 10
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %p, i32 10
+  %0 = load i8, i8* %add.ptr, align 1
   %conv = zext i8 %0 to i32
   %sub = add nsw i32 %conv, 255
   %conv1 = trunc i32 %sub to i8
@@ -18,8 +18,8 @@ define void @g(i8* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}#1
   %add.ptr.sum = add i32 %i, 10
-  %add.ptr1 = getelementptr inbounds i8* %p, i32 %add.ptr.sum
-  %0 = load i8* %add.ptr1, align 1
+  %add.ptr1 = getelementptr inbounds i8, i8* %p, i32 %add.ptr.sum
+  %0 = load i8, i8* %add.ptr1, align 1
   %conv = zext i8 %0 to i32
   %sub = add nsw i32 %conv, 255
   %conv2 = trunc i32 %sub to i8
diff --git a/test/CodeGen/Hexagon/misaligned-access.ll b/test/CodeGen/Hexagon/misaligned-access.ll
index 4dafb44cc3ef..f4b0cb9cb1e3 100644
--- a/test/CodeGen/Hexagon/misaligned-access.ll
+++ b/test/CodeGen/Hexagon/misaligned-access.ll
@@ -7,10 +7,10 @@ declare i32 @_hi(i64) #1
 define i32 @CSDRSEARCH_executeSearchManager() #0 {
 entry:
   %temp = alloca i32, align 4
-  %0 = load i32* @temp1, align 4
+  %0 = load i32, i32* @temp1, align 4
   store i32 %0, i32* %temp, align 4
   %1 = bitcast i32* %temp to i64*
-  %2 = load i64* %1, align 8
+  %2 = load i64, i64* %1, align 8
   %call = call i32 @_hi(i64 %2)
   ret i32 %call
 }
diff --git a/test/CodeGen/Hexagon/mpy.ll b/test/CodeGen/Hexagon/mpy.ll
index d5c5ae345352..3ecf7d46ccb0 100644
--- a/test/CodeGen/Hexagon/mpy.ll
+++ b/test/CodeGen/Hexagon/mpy.ll
@@ -9,10 +9,10 @@ entry:
   store i32 %acc, i32* %acc.addr, align 4
   store i32 %num, i32* %num.addr, align 4
   store i32 %num2, i32* %num2.addr, align 4
-  %0 = load i32* %num.addr, align 4
-  %1 = load i32* %acc.addr, align 4
+  %0 = load i32, i32* %num.addr, align 4
+  %1 = load i32, i32* %acc.addr, align 4
   %mul = mul nsw i32 %0, %1
-  %2 = load i32* %num2.addr, align 4
+  %2 = load i32, i32* %num2.addr, align 4
   %add = add nsw i32 %mul, %2
   store i32 %add, i32* %num.addr, align 4
   ret void
diff --git a/test/CodeGen/Hexagon/newvaluejump.ll b/test/CodeGen/Hexagon/newvaluejump.ll
index 9c7ca55cb8f6..3e1ee179573a 100644
--- a/test/CodeGen/Hexagon/newvaluejump.ll
+++ b/test/CodeGen/Hexagon/newvaluejump.ll
@@ -9,10 +9,10 @@ entry:
 ; CHECK: if (cmp.eq(r{{[0-9]+}}.new, #0)) jump{{.}}
   %addr1 = alloca i32, align 4
   %addr2 = alloca i32, align 4
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   store i32 %0, i32* %addr1, align 4
   call void @bar(i32 1, i32 2)
-  %1 = load i32* @j, align 4
+  %1 = load i32, i32* @j, align 4
   %tobool = icmp ne i32 %1, 0
   br i1 %tobool, label %if.then, label %if.else
 
diff --git a/test/CodeGen/Hexagon/newvaluejump2.ll b/test/CodeGen/Hexagon/newvaluejump2.ll
index 3d50ea5422c7..a812a7d96659 100644
--- a/test/CodeGen/Hexagon/newvaluejump2.ll
+++ b/test/CodeGen/Hexagon/newvaluejump2.ll
@@ -1,17 +1,16 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hexagon-misched < %s \
+; RUN:    | FileCheck %s
 ; Check that we generate new value jump, both registers, with one 
 ; of the registers as new.
 
-@Reg = common global i8 0, align 1
+@Reg = common global i32 0, align 4
 define i32 @main() nounwind {
 entry:
-; CHECK: if (cmp.gt(r{{[0-9]+}}.new, r{{[0-9]+}})) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}}
-  %Reg2 = alloca i8, align 1
-  %0 = load i8* %Reg2, align 1
-  %conv0 = zext i8 %0 to i32
-  %1 = load i8* @Reg, align 1
-  %conv1 = zext i8 %1 to i32
-  %tobool = icmp sle i32 %conv0, %conv1
+; CHECK: if (cmp.gt(r{{[0-9]+}}, r{{[0-9]+}}.new)) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}}
+  %Reg2 = alloca i32, align 4
+  %0 = load i32, i32* %Reg2, align 4
+  %1 = load i32, i32* @Reg, align 4
+  %tobool = icmp sle i32 %0, %1
   br i1 %tobool, label %if.then, label %if.else
 
 if.then:
diff --git a/test/CodeGen/Hexagon/newvaluestore.ll b/test/CodeGen/Hexagon/newvaluestore.ll
index 93cf3479ab5e..13cbba2d08e1 100644
--- a/test/CodeGen/Hexagon/newvaluestore.ll
+++ b/test/CodeGen/Hexagon/newvaluestore.ll
@@ -11,11 +11,11 @@ entry:
   %number1 = alloca i32, align 4
   %number2 = alloca i32, align 4
   %number3 = alloca i32, align 4
-  %0 = load i32 * @i, align 4
+  %0 = load i32 , i32 * @i, align 4
   store i32 %0, i32* %number1, align 4
-  %1 = load i32 * @j, align 4
+  %1 = load i32 , i32 * @j, align 4
   store i32 %1, i32* %number2, align 4
-  %2 = load i32 * @k, align 4
+  %2 = load i32 , i32 * @k, align 4
   store i32 %2, i32* %number3, align 4
   ret i32 %0
 }
diff --git a/test/CodeGen/Hexagon/opt-fabs.ll b/test/CodeGen/Hexagon/opt-fabs.ll
index 31b56fd6e982..da657e4b1b8f 100644
--- a/test/CodeGen/Hexagon/opt-fabs.ll
+++ b/test/CodeGen/Hexagon/opt-fabs.ll
@@ -7,7 +7,7 @@ define float @my_fabsf(float %x) nounwind {
 entry:
   %x.addr = alloca float, align 4
   store float %x, float* %x.addr, align 4
-  %0 = load float* %x.addr, align 4
+  %0 = load float, float* %x.addr, align 4
   %call = call float @fabsf(float %0) readnone
   ret float %call
 }
diff --git a/test/CodeGen/Hexagon/opt-fneg.ll b/test/CodeGen/Hexagon/opt-fneg.ll
index 479b4b64069a..978957865863 100644
--- a/test/CodeGen/Hexagon/opt-fneg.ll
+++ b/test/CodeGen/Hexagon/opt-fneg.ll
@@ -6,7 +6,7 @@ entry:
 ; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
   %x.addr = alloca float, align 4
   store float %x, float* %x.addr, align 4
-  %0 = load float* %x.addr, align 4
+  %0 = load float, float* %x.addr, align 4
   %sub = fsub float -0.000000e+00, %0
   ret float %sub
 }
diff --git a/test/CodeGen/Hexagon/postinc-load.ll b/test/CodeGen/Hexagon/postinc-load.ll
index 855a347d74f5..a9d987981d65 100644
--- a/test/CodeGen/Hexagon/postinc-load.ll
+++ b/test/CodeGen/Hexagon/postinc-load.ll
@@ -12,13 +12,13 @@ for.body:
   %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ]
   %arrayidx1.phi = phi i16* [ %b, %entry ], [ %arrayidx1.inc, %for.body ]
   %sum.03 = phi i32 [ 0, %entry ], [ %add2, %for.body ]
-  %0 = load i32* %arrayidx.phi, align 4
-  %1 = load i16* %arrayidx1.phi, align 2
+  %0 = load i32, i32* %arrayidx.phi, align 4
+  %1 = load i16, i16* %arrayidx1.phi, align 2
   %conv = sext i16 %1 to i32
   %add = add i32 %0, %sum.03
   %add2 = add i32 %add, %conv
-  %arrayidx.inc = getelementptr i32* %arrayidx.phi, i32 1
-  %arrayidx1.inc = getelementptr i16* %arrayidx1.phi, i32 1
+  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
+  %arrayidx1.inc = getelementptr i16, i16* %arrayidx1.phi, i32 1
   %lsr.iv.next = add i32 %lsr.iv, -1
   %exitcond = icmp eq i32 %lsr.iv.next, 0
   br i1 %exitcond, label %for.end, label %for.body
diff --git a/test/CodeGen/Hexagon/postinc-store.ll b/test/CodeGen/Hexagon/postinc-store.ll
index 99a3a58ad39c..6315ca14a952 100644
--- a/test/CodeGen/Hexagon/postinc-store.ll
+++ b/test/CodeGen/Hexagon/postinc-store.ll
@@ -11,15 +11,15 @@ for.body:                                         ; preds = %for.body, %entry
   %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ 10, %entry ]
   %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ]
   %arrayidx1.phi = phi i16* [ %b, %entry ], [ %arrayidx1.inc, %for.body ]
-  %0 = load i32* %arrayidx.phi, align 4
-  %1 = load i16* %arrayidx1.phi, align 2
+  %0 = load i32, i32* %arrayidx.phi, align 4
+  %1 = load i16, i16* %arrayidx1.phi, align 2
   %conv = sext i16 %1 to i32
   %factor = mul i32 %0, 2
   %add3 = add i32 %factor, %conv
   store i32 %add3, i32* %arrayidx.phi, align 4
 
-  %arrayidx.inc = getelementptr i32* %arrayidx.phi, i32 1
-  %arrayidx1.inc = getelementptr i16* %arrayidx1.phi, i32 1
+  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
+  %arrayidx1.inc = getelementptr i16, i16* %arrayidx1.phi, i32 1
   %lsr.iv.next = add i32 %lsr.iv, -1
   %exitcond = icmp eq i32 %lsr.iv.next, 0
   br i1 %exitcond, label %for.end, label %for.body
diff --git a/test/CodeGen/Hexagon/pred-absolute-store.ll b/test/CodeGen/Hexagon/pred-absolute-store.ll
index 64635b176daf..3e5e98270d53 100644
--- a/test/CodeGen/Hexagon/pred-absolute-store.ll
+++ b/test/CodeGen/Hexagon/pred-absolute-store.ll
@@ -1,8 +1,7 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 ; Check that we are able to predicate instructions with abosolute
 ; addressing mode.
-
-; CHECK: if{{ *}}(p{{[0-3]+}}.new){{ *}}memw(##gvar){{ *}}={{ *}}r{{[0-9]+}}
+; CHECK: if ({{!*}}p{{[0-2]}}.new) memw(##gvar) = r{{[0-9]+}}
 
 @gvar = external global i32
 define i32 @test2(i32 %a, i32 %b) nounwind {
diff --git a/test/CodeGen/Hexagon/pred-gp.ll b/test/CodeGen/Hexagon/pred-gp.ll
index 299bd8679dad..3868e098007f 100644
--- a/test/CodeGen/Hexagon/pred-gp.ll
+++ b/test/CodeGen/Hexagon/pred-gp.ll
@@ -14,11 +14,11 @@ entry:
   br i1 %cmp, label %if.then, label %entry.if.end_crit_edge
 
 entry.if.end_crit_edge:
-  %.pre = load i32* @c, align 4
+  %.pre = load i32, i32* @c, align 4
   br label %if.end
 
 if.then:
-  %0 = load i32* @d, align 4
+  %0 = load i32, i32* @d, align 4
   store i32 %0, i32* @c, align 4
   br label %if.end
 
diff --git a/test/CodeGen/Hexagon/pred-instrs.ll b/test/CodeGen/Hexagon/pred-instrs.ll
index 800073e49b03..e0a75f13dfa8 100644
--- a/test/CodeGen/Hexagon/pred-instrs.ll
+++ b/test/CodeGen/Hexagon/pred-instrs.ll
@@ -25,6 +25,6 @@ if.else:                                          ; preds = %entry
 if.end:                                           ; preds = %if.else, %if.then
   %storemerge = phi i32 [ %and, %if.else ], [ %shl, %if.then ]
   store i32 %storemerge, i32* @a, align 4
-  %0 = load i32* @d, align 4
+  %0 = load i32, i32* @d, align 4
   ret i32 %0
 }
diff --git a/test/CodeGen/Hexagon/remove-endloop.ll b/test/CodeGen/Hexagon/remove-endloop.ll
new file mode 100644
index 000000000000..73e1ad02cd80
--- /dev/null
+++ b/test/CodeGen/Hexagon/remove-endloop.ll
@@ -0,0 +1,56 @@
+; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
+
+define void @foo(i32 %n, i32* nocapture %A, i32* nocapture %B) nounwind optsize {
+entry:
+  %cmp = icmp sgt i32 %n, 100
+  br i1 %cmp, label %for.body.preheader, label %for.cond4.preheader
+
+; CHECK: endloop0
+; CHECK: endloop0
+; CHECK-NOT: endloop0
+
+for.body.preheader:
+  br label %for.body
+
+for.cond4.preheader:
+  %cmp113 = icmp sgt i32 %n, 0
+  br i1 %cmp113, label %for.body7.preheader, label %if.end
+
+for.body7.preheader:
+  br label %for.body7
+
+for.body:
+  %arrayidx.phi = phi i32* [ %arrayidx.inc, %for.body ], [ %B, %for.body.preheader ]
+  %arrayidx3.phi = phi i32* [ %arrayidx3.inc, %for.body ], [ %A, %for.body.preheader ]
+  %i.014 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
+  %0 = load i32, i32* %arrayidx.phi, align 4
+  %sub = add nsw i32 %0, -1
+  store i32 %sub, i32* %arrayidx3.phi, align 4
+  %inc = add nsw i32 %i.014, 1
+  %exitcond = icmp eq i32 %inc, %n
+  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
+  %arrayidx3.inc = getelementptr i32, i32* %arrayidx3.phi, i32 1
+  br i1 %exitcond, label %if.end.loopexit, label %for.body
+
+for.body7:
+  %arrayidx8.phi = phi i32* [ %arrayidx8.inc, %for.body7 ], [ %B, %for.body7.preheader ]
+  %arrayidx9.phi = phi i32* [ %arrayidx9.inc, %for.body7 ], [ %A, %for.body7.preheader ]
+  %i.117 = phi i32 [ %inc11, %for.body7 ], [ 0, %for.body7.preheader ]
+  %1 = load i32, i32* %arrayidx8.phi, align 4
+  %add = add nsw i32 %1, 1
+  store i32 %add, i32* %arrayidx9.phi, align 4
+  %inc11 = add nsw i32 %i.117, 1
+  %exitcond18 = icmp eq i32 %inc11, %n
+  %arrayidx8.inc = getelementptr i32, i32* %arrayidx8.phi, i32 1
+  %arrayidx9.inc = getelementptr i32, i32* %arrayidx9.phi, i32 1
+  br i1 %exitcond18, label %if.end.loopexit21, label %for.body7
+
+if.end.loopexit:
+  br label %if.end
+
+if.end.loopexit21:
+  br label %if.end
+
+if.end:
+  ret void
+}
diff --git a/test/CodeGen/Hexagon/remove_lsr.ll b/test/CodeGen/Hexagon/remove_lsr.ll
index 3128dbb8b21b..3b85c486348d 100644
--- a/test/CodeGen/Hexagon/remove_lsr.ll
+++ b/test/CodeGen/Hexagon/remove_lsr.ll
@@ -21,11 +21,11 @@ define void @foo(%union.vect64* nocapture %sss_extracted_bit_rx_data_ptr,
  i8* nocapture %scr_s_even_code_ptr, i8* nocapture %scr_s_odd_code_ptr)
  nounwind {
 entry:
-  %scevgep = getelementptr %union.vect64* %sss_extracted_bit_rx_data_ptr, i32 1
-  %scevgep28 = getelementptr %union.vect32* %s_odd, i32 1
-  %scevgep32 = getelementptr %union.vect32* %s_even, i32 1
-  %scevgep36 = getelementptr i8* %scr_s_odd_code_ptr, i32 1
-  %scevgep39 = getelementptr i8* %scr_s_even_code_ptr, i32 1
+  %scevgep = getelementptr %union.vect64, %union.vect64* %sss_extracted_bit_rx_data_ptr, i32 1
+  %scevgep28 = getelementptr %union.vect32, %union.vect32* %s_odd, i32 1
+  %scevgep32 = getelementptr %union.vect32, %union.vect32* %s_even, i32 1
+  %scevgep36 = getelementptr i8, i8* %scr_s_odd_code_ptr, i32 1
+  %scevgep39 = getelementptr i8, i8* %scr_s_even_code_ptr, i32 1
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
@@ -54,16 +54,16 @@ for.body:                                         ; preds = %for.body, %entry
   %7 = trunc i64 %6 to i32
   %8 = tail call i32 @llvm.hexagon.C2.mux(i32 %conv8, i32 %5, i32 %7)
   store i32 %8, i32* %lsr.iv2931, align 4
-  %srcval = load i64* %lsr.iv27, align 8
-  %9 = load i8* %lsr.iv40, align 1
-  %10 = load i8* %lsr.iv37, align 1
+  %srcval = load i64, i64* %lsr.iv27, align 8
+  %9 = load i8, i8* %lsr.iv40, align 1
+  %10 = load i8, i8* %lsr.iv37, align 1
   %lftr.wideiv = trunc i32 %lsr.iv42 to i8
   %exitcond = icmp eq i8 %lftr.wideiv, 32
-  %scevgep26 = getelementptr %union.vect64* %lsr.iv, i32 1
-  %scevgep30 = getelementptr %union.vect32* %lsr.iv29, i32 1
-  %scevgep34 = getelementptr %union.vect32* %lsr.iv33, i32 1
-  %scevgep38 = getelementptr i8* %lsr.iv37, i32 1
-  %scevgep41 = getelementptr i8* %lsr.iv40, i32 1
+  %scevgep26 = getelementptr %union.vect64, %union.vect64* %lsr.iv, i32 1
+  %scevgep30 = getelementptr %union.vect32, %union.vect32* %lsr.iv29, i32 1
+  %scevgep34 = getelementptr %union.vect32, %union.vect32* %lsr.iv33, i32 1
+  %scevgep38 = getelementptr i8, i8* %lsr.iv37, i32 1
+  %scevgep41 = getelementptr i8, i8* %lsr.iv40, i32 1
   %lsr.iv.next = add i32 %lsr.iv42, 1
   br i1 %exitcond, label %for.end, label %for.body
 
diff --git a/test/CodeGen/Hexagon/shrink-frame-basic.ll b/test/CodeGen/Hexagon/shrink-frame-basic.ll
new file mode 100644
index 000000000000..50b37885eda4
--- /dev/null
+++ b/test/CodeGen/Hexagon/shrink-frame-basic.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s | FileCheck %s
+; Check for allocframe in a non-entry block LBB0_n.
+; CHECK: LBB0_{{[0-9]+}}:
+; CHECK:   allocframe
+; Deallocframe may be in a different block, but must follow.
+; CHECK: deallocframe
+
+target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
+target triple = "hexagon"
+
+; Function Attrs: nounwind
+define i32 @foo(i32 %n, i32* %p) #0 {
+entry:
+  %cmp = icmp eq i32* %p, null
+  br i1 %cmp, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  %0 = load i32, i32* %p, align 4
+  %inc = add nsw i32 %0, 1
+  store i32 %inc, i32* %p, align 4
+  br label %return
+
+if.end:                                           ; preds = %entry
+  %call = tail call i32 bitcast (i32 (...)* @bar to i32 (i32)*)(i32 %n) #0
+  %add = add nsw i32 %call, 1
+  br label %return
+
+return:                                           ; preds = %if.end, %if.then
+  %retval.0 = phi i32 [ %0, %if.then ], [ %add, %if.end ]
+  ret i32 %retval.0
+}
+
+declare i32 @bar(...) #0
+
+attributes #0 = { nounwind }
+
diff --git a/test/CodeGen/Hexagon/stack-align1.ll b/test/CodeGen/Hexagon/stack-align1.ll
new file mode 100644
index 000000000000..4efa70f59854
--- /dev/null
+++ b/test/CodeGen/Hexagon/stack-align1.ll
@@ -0,0 +1,21 @@
+; RUN: llc -O0 -march=hexagon < %s | FileCheck %s
+; CHECK: and(r29, #-32)
+; CHECK-DAG: add(r29, #0)
+; CHECK-DAG: add(r29, #28)
+
+target triple = "hexagon-unknown-unknown"
+
+; Function Attrs: nounwind uwtable
+define void @foo() #0 {
+entry:
+  %x = alloca i32, align 4
+  %y = alloca i32, align 32
+  %0 = bitcast i32* %x to i8*
+  %1 = bitcast i32* %y to i8*
+  call void @bar(i8* %0, i8* %1)
+  ret void
+}
+
+declare void @bar(i8*, i8*) #0
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/Hexagon/stack-align2.ll b/test/CodeGen/Hexagon/stack-align2.ll
new file mode 100644
index 000000000000..1bbd57820325
--- /dev/null
+++ b/test/CodeGen/Hexagon/stack-align2.ll
@@ -0,0 +1,27 @@
+; RUN: llc -O0 -march=hexagon < %s | FileCheck %s
+; CHECK: and(r29, #-128)
+; CHECK-DAG: add(r29, #0)
+; CHECK-DAG: add(r29, #64)
+; CHECK-DAG: add(r29, #96)
+; CHECK-DAG: add(r29, #124)
+
+target triple = "hexagon-unknown-unknown"
+
+; Function Attrs: nounwind uwtable
+define void @foo() #0 {
+entry:
+  %x = alloca i32, align 4
+  %y = alloca i32, align 32
+  %z = alloca i32, align 64
+  %w = alloca i32, align 128
+  %0 = bitcast i32* %x to i8*
+  %1 = bitcast i32* %y to i8*
+  %2 = bitcast i32* %z to i8*
+  %3 = bitcast i32* %w to i8*
+  call void @bar(i8* %0, i8* %1, i8* %2, i8* %3)
+  ret void
+}
+
+declare void @bar(i8*, i8*, i8*, i8*) #0
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/Hexagon/stack-alloca1.ll b/test/CodeGen/Hexagon/stack-alloca1.ll
new file mode 100644
index 000000000000..00e9e051aebb
--- /dev/null
+++ b/test/CodeGen/Hexagon/stack-alloca1.ll
@@ -0,0 +1,18 @@
+; RUN: llc -O0 -march=hexagon < %s | FileCheck %s
+; CHECK: sub(r29, r[[REG:[0-9]+]])
+; CHECK: r29 = r[[REG]]
+
+target triple = "hexagon-unknown-unknown"
+
+; Function Attrs: nounwind uwtable
+define void @foo(i32 %n) #0 {
+entry:
+  %x = alloca i32, i32 %n
+  %0 = bitcast i32* %x to i8*
+  call void @bar(i8* %0)
+  ret void
+}
+
+declare void @bar(i8*) #0
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/Hexagon/stack-alloca2.ll b/test/CodeGen/Hexagon/stack-alloca2.ll
new file mode 100644
index 000000000000..ad5e13166aa2
--- /dev/null
+++ b/test/CodeGen/Hexagon/stack-alloca2.ll
@@ -0,0 +1,23 @@
+; RUN: llc -O0 -march=hexagon < %s | FileCheck %s
+; CHECK-DAG: r[[AP:[0-9]+]] = and(r30, #-32)
+; CHECK-DAG: r1 = add(r[[AP]], #-32)
+
+; CHECK-DAG: sub(r29, r[[SP:[0-9]+]])
+; CHECK-DAG: r29 = r[[SP]]
+
+target triple = "hexagon-unknown-unknown"
+
+; Function Attrs: nounwind uwtable
+define void @foo(i32 %n) #0 {
+entry:
+  %x = alloca i32, i32 %n
+  %y = alloca i32, align 32
+  %0 = bitcast i32* %x to i8*
+  %1 = bitcast i32* %y to i8*
+  call void @bar(i8* %0, i8* %1)
+  ret void
+}
+
+declare void @bar(i8*, i8* %y) #0
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/Hexagon/static.ll b/test/CodeGen/Hexagon/static.ll
index 683a4c21bcb8..760b8b559725 100644
--- a/test/CodeGen/Hexagon/static.ll
+++ b/test/CodeGen/Hexagon/static.ll
@@ -10,10 +10,10 @@
 
 define void @foo() nounwind {
 entry:
-  %0 = load i32* @num, align 4
-  %1 = load i32* @acc, align 4
+  %0 = load i32, i32* @num, align 4
+  %1 = load i32, i32* @acc, align 4
   %mul = mul nsw i32 %0, %1
-  %2 = load i32* @val, align 4
+  %2 = load i32, i32* @val, align 4
   %add = add nsw i32 %mul, %2
   store i32 %add, i32* @num, align 4
   ret void
diff --git a/test/CodeGen/Hexagon/struct_args.ll b/test/CodeGen/Hexagon/struct_args.ll
index f91300b5067e..95b76c7999d4 100644
--- a/test/CodeGen/Hexagon/struct_args.ll
+++ b/test/CodeGen/Hexagon/struct_args.ll
@@ -8,7 +8,7 @@
 
 define void @foo() nounwind {
 entry:
-  %0 = load i64* bitcast (%struct.small* @s1 to i64*), align 1
+  %0 = load i64, i64* bitcast (%struct.small* @s1 to i64*), align 1
   call void @bar(i64 %0)
   ret void
 }
diff --git a/test/CodeGen/Hexagon/struct_args_large.ll b/test/CodeGen/Hexagon/struct_args_large.ll
index db87d9e81db1..1438d73eacf7 100644
--- a/test/CodeGen/Hexagon/struct_args_large.ll
+++ b/test/CodeGen/Hexagon/struct_args_large.ll
@@ -1,4 +1,5 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; XFAIL:
+; RUN: llc -march=hexagon < %s | FileCheck %s
 ; CHECK: r[[T0:[0-9]+]] = CONST32(#s2)
 ; CHECK: memw(r29+#0) = r{{.}}
 ; CHECK: memw(r29+#8) = r{{.}}
diff --git a/test/CodeGen/Hexagon/sube.ll b/test/CodeGen/Hexagon/sube.ll
index 735ac9eb82e4..873f52b2d5df 100644
--- a/test/CodeGen/Hexagon/sube.ll
+++ b/test/CodeGen/Hexagon/sube.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
 
-; CHECK: r{{[0-9]+:[0-9]+}} = #0
 ; CHECK: r{{[0-9]+:[0-9]+}} = #1
+; CHECK: r{{[0-9]+:[0-9]+}} = #0
 ; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
 ; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
 ; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
diff --git a/test/CodeGen/Hexagon/tail-call-mem-intrinsics.ll b/test/CodeGen/Hexagon/tail-call-mem-intrinsics.ll
new file mode 100644
index 000000000000..90fb75e5be06
--- /dev/null
+++ b/test/CodeGen/Hexagon/tail-call-mem-intrinsics.ll
@@ -0,0 +1,31 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: tail_memcpy:
+; CHECK: jump memcpy
+define void @tail_memcpy(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 {
+entry:
+  tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: tail_memmove:
+; CHECK: jump memmove
+define void @tail_memmove(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 {
+entry:
+  tail call void @llvm.memmove.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: tail_memset:
+; CHECK: jump memset
+define void @tail_memset(i8* nocapture %p, i8 %c, i32 %n) #0 {
+entry:
+  tail call void @llvm.memset.p0i8.i32(i8* %p, i8 %c, i32 %n, i32 1, i1 false)
+  ret void
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0
+declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0
+declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) #0
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/Hexagon/tfr-to-combine.ll b/test/CodeGen/Hexagon/tfr-to-combine.ll
index e3057cd1611d..a257acfeb49b 100644
--- a/test/CodeGen/Hexagon/tfr-to-combine.ll
+++ b/test/CodeGen/Hexagon/tfr-to-combine.ll
@@ -20,14 +20,14 @@ define i64 @test2() #0 {
 ; CHECK: combine(#0, r{{[0-9]+}})
 entry:
   store i16 0, i16* @a, align 2
-  %0 = load i16* @c, align 2
+  %0 = load i16, i16* @c, align 2
   %conv2 = zext i16 %0 to i64
   ret i64 %conv2
 }
 
 ; Function Attrs: nounwind
 define i64 @test4() #0 {
-; CHECK: combine(#0, ##100)
+; CHECK: combine(#0, #100)
 entry:
   store i16 100, i16* @b, align 2
   store i16 0, i16* @a, align 2
diff --git a/test/CodeGen/Hexagon/union-1.ll b/test/CodeGen/Hexagon/union-1.ll
index fe79f9510fe8..1d93797db858 100644
--- a/test/CodeGen/Hexagon/union-1.ll
+++ b/test/CodeGen/Hexagon/union-1.ll
@@ -2,13 +2,15 @@
 ; CHECK: word
 ; CHECK-NOT: combine(#0
 ; CHECK: jump bar
+; XFAIL: *
+; Disable this test temporarily.
 
 define void @word(i32* nocapture %a) nounwind {
 entry:
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %1 = zext i32 %0 to i64
-  %add.ptr = getelementptr inbounds i32* %a, i32 1
-  %2 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %a, i32 1
+  %2 = load i32, i32* %add.ptr, align 4
   %3 = zext i32 %2 to i64
   %4 = shl nuw i64 %3, 32
   %ins = or i64 %4, %1
diff --git a/test/CodeGen/Hexagon/vaddh.ll b/test/CodeGen/Hexagon/vaddh.ll
index 01d20410978e..88194b750ad5 100644
--- a/test/CodeGen/Hexagon/vaddh.ll
+++ b/test/CodeGen/Hexagon/vaddh.ll
@@ -6,8 +6,8 @@
 
 define void @foo() nounwind {
 entry:
-  %0 = load i32* @j, align 4
-  %1 = load i32* @k, align 4
+  %0 = load i32, i32* @j, align 4
+  %1 = load i32, i32* @k, align 4
   %2 = call i32 @llvm.hexagon.A2.svaddh(i32 %0, i32 %1)
   store i32 %2, i32* @k, align 4
   ret void
diff --git a/test/CodeGen/Hexagon/validate-offset.ll b/test/CodeGen/Hexagon/validate-offset.ll
index 9e7d0aa07832..8de006c80b11 100644
--- a/test/CodeGen/Hexagon/validate-offset.ll
+++ b/test/CodeGen/Hexagon/validate-offset.ll
@@ -11,26 +11,26 @@ entry:
   %b.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
   store i32 %b, i32* %b.addr, align 4
-  %0 = load i32* %a.addr, align 4
-  %1 = load i32* %b.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4
+  %1 = load i32, i32* %b.addr, align 4
   %cmp = icmp sgt i32 %0, %1
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:
-  %2 = load i32* %a.addr, align 4
-  %3 = load i32* %b.addr, align 4
+  %2 = load i32, i32* %a.addr, align 4
+  %3 = load i32, i32* %b.addr, align 4
   %add = add nsw i32 %2, %3
   store i32 %add, i32* %retval
   br label %return
 
 if.else:
-  %4 = load i32* %a.addr, align 4
-  %5 = load i32* %b.addr, align 4
+  %4 = load i32, i32* %a.addr, align 4
+  %5 = load i32, i32* %b.addr, align 4
   %sub = sub nsw i32 %4, %5
   store i32 %sub, i32* %retval
   br label %return
 
 return:
-  %6 = load i32* %retval
+  %6 = load i32, i32* %retval
   ret i32 %6
 }
diff --git a/test/CodeGen/Hexagon/vect/vect-anyextend.ll b/test/CodeGen/Hexagon/vect/vect-anyextend.ll
new file mode 100644
index 000000000000..fe5fe84fc37d
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-anyextend.ll
@@ -0,0 +1,15 @@
+; RUN: llc -march=hexagon < %s
+; Used to fail with "Cannot select: 0x17300f0: v2i32 = any_extend"
+
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout =
+"e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
+target triple = "hexagon-unknown-linux-gnu"
+
+define void @foo() nounwind {
+entry:
+  %_p_vec_full48 = load <4 x i8>, <4 x i8>* undef, align 8
+  %0 = zext <4 x i8> %_p_vec_full48 to <4 x i32>
+  store <4 x i32> %0, <4 x i32>* undef, align 8
+  unreachable
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-apint-truncate.ll b/test/CodeGen/Hexagon/vect/vect-apint-truncate.ll
new file mode 100644
index 000000000000..eb94ddfe2961
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-apint-truncate.ll
@@ -0,0 +1,27 @@
+; RUN: llc -march=hexagon < %s
+; Used to fail with "Invalid APInt Truncate request".
+; Used to fail with "Cannot select: 0x596010: v2i32 = sign_extend_inreg".
+
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
+target triple = "hexagon-unknown-linux-gnu"
+
+define void @foo() nounwind {
+entry:
+  br label %polly.loop_header
+
+polly.loop_after:                                 ; preds = %polly.loop_header
+  unreachable
+
+polly.loop_header:                                ; preds = %polly.loop_body, %entry
+  %0 = icmp sle i32 undef, 63
+  br i1 %0, label %polly.loop_body, label %polly.loop_after
+
+polly.loop_body:                                  ; preds = %polly.loop_header
+  %_p_vec_full = load <4 x i8>, <4 x i8>* undef, align 8
+  %1 = sext <4 x i8> %_p_vec_full to <4 x i32>
+  %p_vec = mul <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
+  %mulp_vec = add <4 x i32> %p_vec, <i32 21, i32 21, i32 21, i32 21>
+  store <4 x i32> %mulp_vec, <4 x i32>* undef, align 8
+  br label %polly.loop_header
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-bad-bitcast.ll b/test/CodeGen/Hexagon/vect/vect-bad-bitcast.ll
new file mode 100644
index 000000000000..1672a789a26d
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-bad-bitcast.ll
@@ -0,0 +1,61 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s
+; REQUIRES: asserts
+; Check for successful compilation.
+
+target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
+target triple = "hexagon"
+
+@input_buf = internal unnamed_addr constant [256 x i16] [i16 0, i16 0, i16 0, i16 1280, i16 2560, i16 4864, i16 7168, i16 9472, i16 11776, i16 12672, i16 13568, i16 14080, i16 15360, i16 15360, i16 15360, i16 15360, i16 15360, i16 15104, i16 14848, i16 14592, i16 14336, i16 14080, i16 14080, i16 13952, i16 13824, i16 13696, i16 13568, i16 13440, i16 13312, i16 13184, i16 13056, i16 12928, i16 12800, i16 12800, i16 12800, i16 12800, i16 12800, i16 12672, i16 12544, i16 12544, i16 12544, i16 12544, i16 12672, i16 12800, i16 12800, i16 12928, i16 13056, i16 13184, i16 13312, i16 13440, i16 13568, i16 13696, i16 13824, i16 14208, i16 14592, i16 14976, i16 15104, i16 15360, i16 15616, i16 15872, i16 16128, i16 16512, i16 16896, i16 17152, i16 17408, i16 17536, i16 17664, i16 17792, i16 17920, i16 18304, i16 18688, i16 19072, i16 19456, i16 19712, i16 19968, i16 20224, i16 20480, i16 20608, i16 20864, i16 20992, i16 21248, i16 21248, i16 21248, i16 21248, i16 21248, i16 21248, i16 21376, i16 21504, i16 21760, i16 21760, i16 21632, i16 21504, i16 21504, i16 21632, i16 21632, i16 21504, i16 21504, i16 21376, i16 21248, i16 21120, i16 20992, i16 20992, i16 20864, i16 20736, i16 20736, i16 20736, i16 20480, i16 20352, i16 20224, i16 20224, i16 20224, i16 20224, i16 20352, i16 20352, i16 20480, i16 20352, i16 20352, i16 20352, i16 20352, i16 20224, i16 20224, i16 20224, i16 20096, i16 20096, i16 19968, i16 19840, i16 19712, i16 19584, i16 19456, i16 19584, i16 19584, i16 19456, i16 19456, i16 19328, i16 19328, i16 19456, i16 19456, i16 19328, i16 19328, i16 19200, i16 19200, i16 19200, i16 19072, i16 19072, i16 18944, i16 18816, i16 18688, i16 18560, i16 18432, i16 18304, i16 18304, i16 18176, i16 18176, i16 18176, i16 18304, i16 18304, i16 18432, i16 18560, i16 18432, i16 18176, i16 17920, i16 17920, i16 17792, i16 17792, i16 17664, i16 17664, i16 17536, i16 17536, i16 17408, i16 17408, i16 17280, i16 17280, i16 17280, i16 17152, i16 17152, i16 17152, i16 17152, i16 17024, i16 17024, i16 16896, i16 16896, i16 16896, i16 16768, i16 16768, i16 16640, i16 16640, i16 16512, i16 16512, i16 16384, i16 16256, i16 16128, i16 16000, i16 15872, i16 15744, i16 15616, i16 15488, i16 15360, i16 15488, i16 15360, i16 15232, i16 15360, i16 15232, i16 15104, i16 14976, i16 14336, i16 14336, i16 14592, i16 14464, i16 13824, i16 13824, i16 13568, i16 13568, i16 13440, i16 13312, i16 13184, i16 13056, i16 13056, i16 13056, i16 12928, i16 12800, i16 12672, i16 12672, i16 12544, i16 12416, i16 12288, i16 12160, i16 11904, i16 11776, i16 11571, i16 11520, i16 11392, i16 11136, i16 10905, i16 10752, i16 10624, i16 10444, i16 10240, i16 9984, i16 9728, i16 9472, i16 9216, i16 8960, i16 8704, i16 8448, i16 8192, i16 7936, i16 7680, i16 7424, i16 7168, i16 6400, i16 5632, i16 4864, i16 3584, i16 1536, i16 0, i16 0], align 8
+
+; Function Attrs: nounwind
+define i32 @t_run_test() #0 {
+entry:
+  %WaterLeveldB_out = alloca i16, align 2
+  br label %polly.stmt.for.body
+
+for.body8:                                        ; preds = %for.body8, %polly.loop_exit.loopexit
+  %i.120 = phi i32 [ 0, %polly.loop_exit.loopexit ], [ %inc11.24, %for.body8 ]
+  %call = call i32 bitcast (i32 (...)* @fxpBitAllocation to i32 (i32, i32, i32, i32, i16*, i32, i32, i32)*)(i32 0, i32 0, i32 256, i32 %conv9, i16* %WaterLeveldB_out, i32 0, i32 1920, i32 %i.120) #2
+  %inc11.24 = add i32 %i.120, 25
+  %exitcond.24 = icmp eq i32 %inc11.24, 500
+  br i1 %exitcond.24, label %for.end12, label %for.body8
+
+for.end12:                                        ; preds = %for.body8
+  ret i32 0
+
+polly.loop_exit.loopexit:                         ; preds = %polly.stmt.for.body
+  %WaterLeveldB.1p_vsel.lcssa = phi <4 x i16> [ %WaterLeveldB.1p_vsel, %polly.stmt.for.body ]
+  %_low_half = shufflevector <4 x i16> %WaterLeveldB.1p_vsel.lcssa, <4 x i16> undef, <2 x i32> <i32 0, i32 1>
+  %_high_half = shufflevector <4 x i16> %WaterLeveldB.1p_vsel.lcssa, <4 x i16> undef, <2 x i32> <i32 2, i32 3>
+  %0 = icmp sgt <2 x i16> %_low_half, %_high_half
+  %1 = select <2 x i1> %0, <2 x i16> %_low_half, <2 x i16> %_high_half
+  %2 = extractelement <2 x i16> %1, i32 0
+  %3 = extractelement <2 x i16> %1, i32 1
+  %4 = icmp sgt i16 %2, %3
+  %5 = select i1 %4, i16 %2, i16 %3
+  %conv9 = sext i16 %5 to i32
+  br label %for.body8
+
+polly.stmt.for.body:                              ; preds = %entry, %polly.stmt.for.body
+  %WaterLeveldB.1p_vsel35 = phi <4 x i16> [ <i16 -32768, i16 -32768, i16 -32768, i16 -32768>, %entry ], [ %WaterLeveldB.1p_vsel, %polly.stmt.for.body ]
+  %scevgep.phi = phi i16* [ getelementptr inbounds ([256 x i16], [256 x i16]* @input_buf, i32 0, i32 0), %entry ], [ %scevgep.inc, %polly.stmt.for.body ]
+  %polly.indvar = phi i32 [ 0, %entry ], [ %polly.indvar_next, %polly.stmt.for.body ]
+  %vector_ptr = bitcast i16* %scevgep.phi to <4 x i16>*
+  %_p_vec_full = load <4 x i16>, <4 x i16>* %vector_ptr, align 8
+  %cmp2p_vicmp = icmp sgt <4 x i16> %_p_vec_full, %WaterLeveldB.1p_vsel35
+  %WaterLeveldB.1p_vsel = select <4 x i1> %cmp2p_vicmp, <4 x i16> %_p_vec_full, <4 x i16> %WaterLeveldB.1p_vsel35
+  %polly.indvar_next = add nsw i32 %polly.indvar, 4
+  %polly.loop_cond = icmp slt i32 %polly.indvar, 252
+  %scevgep.inc = getelementptr i16, i16* %scevgep.phi, i32 4
+  br i1 %polly.loop_cond, label %polly.stmt.for.body, label %polly.loop_exit.loopexit
+}
+
+declare i32 @fxpBitAllocation(...) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"QuIC LLVM Hexagon Clang version 3.1"}
diff --git a/test/CodeGen/Hexagon/vect/vect-bitcast-1.ll b/test/CodeGen/Hexagon/vect/vect-bitcast-1.ll
new file mode 100644
index 000000000000..b834744d9b12
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-bitcast-1.ll
@@ -0,0 +1,68 @@
+; RUN: llc -march=hexagon < %s
+; REQUIRES: asserts
+; Used to fail with: Assertion `VT.getSizeInBits() == Operand.getValueType().getSizeInBits() && "Cannot BITCAST between types of different sizes!"' failed.
+
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
+target triple = "hexagon-unknown-linux-gnu"
+
+define void @foo() nounwind {
+entry:
+  br label %while.body
+
+while.body:                                       ; preds = %if.then155, %if.then12, %entry
+  %cmp.i = icmp eq i8* undef, null
+  br i1 %cmp.i, label %lab_ci.exit, label %if.end.i
+
+if.end.i:                                         ; preds = %while.body
+  unreachable
+
+lab_ci.exit:      ; preds = %while.body
+  br i1 false, label %if.then, label %if.else
+
+if.then:                                          ; preds = %lab_ci.exit
+  unreachable
+
+if.else:                                          ; preds = %lab_ci.exit
+  br i1 undef, label %if.then12, label %if.else17
+
+if.then12:                                        ; preds = %if.else
+  br label %while.body
+
+if.else17:                                        ; preds = %if.else
+  br i1 false, label %if.then22, label %if.else35
+
+if.then22:                                        ; preds = %if.else17
+  unreachable
+
+if.else35:                                        ; preds = %if.else17
+  br i1 false, label %if.then40, label %if.else83
+
+if.then40:                                        ; preds = %if.else35
+  unreachable
+
+if.else83:                                        ; preds = %if.else35
+  br i1 false, label %if.then88, label %if.else150
+
+if.then88:                                        ; preds = %if.else83
+  unreachable
+
+if.else150:                                       ; preds = %if.else83
+  %cmp154 = icmp eq i32 undef, 0
+  br i1 %cmp154, label %if.then155, label %if.else208
+
+if.then155:                                       ; preds = %if.else150
+  %call191 = call i32 @strtol() nounwind
+  %conv192 = trunc i32 %call191 to i16
+  %_p_splat_one = insertelement <1 x i16> undef, i16 %conv192, i32 0
+  %_p_splat = shufflevector <1 x i16> %_p_splat_one, <1 x i16> undef, <2 x i32> zeroinitializer
+  %0 = sext <2 x i16> %_p_splat to <2 x i32>
+  %mul198p_vec = shl <2 x i32> %0, <i32 2, i32 2>
+  %1 = extractelement <2 x i32> %mul198p_vec, i32 0
+  store i32 %1, i32* null, align 4
+  br label %while.body
+
+if.else208:                                       ; preds = %if.else150
+  unreachable
+}
+
+declare i32 @strtol() nounwind
diff --git a/test/CodeGen/Hexagon/vect/vect-bitcast.ll b/test/CodeGen/Hexagon/vect/vect-bitcast.ll
new file mode 100644
index 000000000000..2d6b0b827397
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-bitcast.ll
@@ -0,0 +1,56 @@
+; RUN: llc -march=hexagon < %s
+; REQUIRES: asserts
+; Used to fail with "Cannot BITCAST between types of different sizes!"
+
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+define void @foo() nounwind {
+entry:
+  br label %while.body
+
+while.body:                                       ; preds = %if.then155, %if.then12, %if.then, %entry
+  br i1 undef, label %if.then, label %if.else
+
+if.then:                                          ; preds = %while.body
+  br label %while.body
+
+if.else:                                          ; preds = %while.body
+  br i1 undef, label %if.then12, label %if.else17
+
+if.then12:                                        ; preds = %if.else
+  br label %while.body
+
+if.else17:                                        ; preds = %if.else
+  br i1 false, label %if.then22, label %if.else35
+
+if.then22:                                        ; preds = %if.else17
+  unreachable
+
+if.else35:                                        ; preds = %if.else17
+  br i1 false, label %if.then40, label %if.else83
+
+if.then40:                                        ; preds = %if.else35
+  unreachable
+
+if.else83:                                        ; preds = %if.else35
+  br i1 false, label %if.then88, label %if.else150
+
+if.then88:                                        ; preds = %if.else83
+  unreachable
+
+if.else150:                                       ; preds = %if.else83
+  %cmp154 = icmp eq i32 undef, 0
+  br i1 %cmp154, label %if.then155, label %if.else208
+
+if.then155:                                       ; preds = %if.else150
+  %_p_splat.1 = shufflevector <1 x i16> zeroinitializer, <1 x i16> undef, <2 x i32> zeroinitializer
+  %0 = sext <2 x i16> %_p_splat.1 to <2 x i32>
+  %mul198p_vec.1 = mul <2 x i32> %0, <i32 4, i32 4>
+  %1 = extractelement <2 x i32> %mul198p_vec.1, i32 0
+  store i32 %1, i32* undef, align 4
+  br label %while.body
+
+if.else208:                                       ; preds = %if.else150
+  unreachable
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll b/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll
new file mode 100644
index 000000000000..f5ee5d001510
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll
@@ -0,0 +1,29 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; This one should generate a combine with two immediates.
+; CHECK: combine(#7, #7)
+@B = common global [400 x i32] zeroinitializer, align 8
+@A = common global [400 x i32] zeroinitializer, align 8
+@C = common global [400 x i32] zeroinitializer, align 8
+
+define void @run() nounwind {
+entry:
+  br label %polly.loop_body
+
+polly.loop_after:                                 ; preds = %polly.loop_body
+  ret void
+
+polly.loop_body:                                  ; preds = %entry, %polly.loop_body
+  %polly.loopiv23 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ]
+  %polly.next_loopiv = add nsw i32 %polly.loopiv23, 4
+  %p_arrayidx1 = getelementptr [400 x i32], [400 x i32]* @A, i32 0, i32 %polly.loopiv23
+  %p_arrayidx = getelementptr [400 x i32], [400 x i32]* @B, i32 0, i32 %polly.loopiv23
+  %vector_ptr = bitcast i32* %p_arrayidx to <4 x i32>*
+  %_p_vec_full = load <4 x i32>, <4 x i32>* %vector_ptr, align 8
+  %mulp_vec = mul <4 x i32> %_p_vec_full, <i32 7, i32 7, i32 7, i32 7>
+  %vector_ptr12 = bitcast i32* %p_arrayidx1 to <4 x i32>*
+  %_p_vec_full13 = load <4 x i32>, <4 x i32>* %vector_ptr12, align 8
+  %addp_vec = add <4 x i32> %_p_vec_full13, %mulp_vec
+  store <4 x i32> %addp_vec, <4 x i32>* %vector_ptr12, align 8
+  %0 = icmp slt i32 %polly.next_loopiv, 400
+  br i1 %0, label %polly.loop_body, label %polly.loop_after
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-cst-v4i8.ll b/test/CodeGen/Hexagon/vect/vect-cst-v4i8.ll
new file mode 100644
index 000000000000..de3e14e2e91c
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-cst-v4i8.ll
@@ -0,0 +1,30 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; Make sure we can build the constant vector <1, 2, 3, 4>
+; CHECK-DAG: ##B
+; CHECK-DAG: ##A
+@B = common global [400 x i8] zeroinitializer, align 8
+@A = common global [400 x i8] zeroinitializer, align 8
+@C = common global [400 x i8] zeroinitializer, align 8
+
+define void @run() nounwind {
+entry:
+  br label %polly.loop_body
+
+polly.loop_after:                                 ; preds = %polly.loop_body
+  ret void
+
+polly.loop_body:                                  ; preds = %entry, %polly.loop_body
+  %polly.loopiv25 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ]
+  %polly.next_loopiv = add i32 %polly.loopiv25, 4
+  %p_arrayidx1 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %polly.loopiv25
+  %p_arrayidx = getelementptr [400 x i8], [400 x i8]* @B, i32 0, i32 %polly.loopiv25
+  %vector_ptr = bitcast i8* %p_arrayidx to <4 x i8>*
+  %_p_vec_full = load <4 x i8>, <4 x i8>* %vector_ptr, align 8
+  %mulp_vec = mul <4 x i8> %_p_vec_full, <i8 1, i8 2, i8 3, i8 4>
+  %vector_ptr14 = bitcast i8* %p_arrayidx1 to <4 x i8>*
+  %_p_vec_full15 = load <4 x i8>, <4 x i8>* %vector_ptr14, align 8
+  %addp_vec = add <4 x i8> %_p_vec_full15, %mulp_vec
+  store <4 x i8> %addp_vec, <4 x i8>* %vector_ptr14, align 8
+  %0 = icmp slt i32 %polly.next_loopiv, 400
+  br i1 %0, label %polly.loop_body, label %polly.loop_after
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-cst.ll b/test/CodeGen/Hexagon/vect/vect-cst.ll
new file mode 100644
index 000000000000..370fa5c7539e
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-cst.ll
@@ -0,0 +1,29 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; Make sure we can build the constant vector <7, 7, 7, 7>
+; CHECK: vaddub
+@B = common global [400 x i8] zeroinitializer, align 8
+@A = common global [400 x i8] zeroinitializer, align 8
+@C = common global [400 x i8] zeroinitializer, align 8
+
+define void @run() nounwind {
+entry:
+  br label %polly.loop_body
+
+polly.loop_after:                                 ; preds = %polly.loop_body
+  ret void
+
+polly.loop_body:                                  ; preds = %entry, %polly.loop_body
+  %polly.loopiv25 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ]
+  %polly.next_loopiv = add i32 %polly.loopiv25, 4
+  %p_arrayidx1 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %polly.loopiv25
+  %p_arrayidx = getelementptr [400 x i8], [400 x i8]* @B, i32 0, i32 %polly.loopiv25
+  %vector_ptr = bitcast i8* %p_arrayidx to <4 x i8>*
+  %_p_vec_full = load <4 x i8>, <4 x i8>* %vector_ptr, align 8
+  %mulp_vec = mul <4 x i8> %_p_vec_full, <i8 7, i8 7, i8 7, i8 7>
+  %vector_ptr14 = bitcast i8* %p_arrayidx1 to <4 x i8>*
+  %_p_vec_full15 = load <4 x i8>, <4 x i8>* %vector_ptr14, align 8
+  %addp_vec = add <4 x i8> %_p_vec_full15, %mulp_vec
+  store <4 x i8> %addp_vec, <4 x i8>* %vector_ptr14, align 8
+  %0 = icmp slt i32 %polly.next_loopiv, 400
+  br i1 %0, label %polly.loop_body, label %polly.loop_after
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-extract.ll b/test/CodeGen/Hexagon/vect/vect-extract.ll
new file mode 100644
index 000000000000..75dc6850f181
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-extract.ll
@@ -0,0 +1,96 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+
+; Check that we do not generate extract.
+; CHECK-NOT: extractu
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+define void @foo(i32 %N, i32* nocapture %C, i16* nocapture %A, i16 signext %val) #0 {
+entry:
+  %cmp14 = icmp eq i32 %N, 0
+  br i1 %cmp14, label %for.end11, label %for.cond1.preheader.single_entry.preheader
+
+for.cond1.preheader.single_entry.preheader:       ; preds = %entry
+  %0 = add i32 %N, -1
+  %leftover_lb = and i32 %0, -2
+  %p_conv4 = sext i16 %val to i32
+  br label %for.cond1.preheader.single_entry
+
+for.cond1.preheader.single_entry:                 ; preds = %for.inc9, %for.cond1.preheader.single_entry.preheader
+  %indvar = phi i32 [ %indvar.next, %for.inc9 ], [ 0, %for.cond1.preheader.single_entry.preheader ]
+  %1 = mul i32 %indvar, %N
+  %.not = icmp slt i32 %N, 2
+  %.not41 = icmp slt i32 %leftover_lb, 1
+  %brmerge = or i1 %.not, %.not41
+  %.mux = select i1 %.not, i32 0, i32 %leftover_lb
+  br i1 %brmerge, label %polly.loop_header26.preheader, label %polly.loop_body.lr.ph
+
+for.inc9.loopexit:                                ; preds = %polly.stmt.for.body331
+  br label %for.inc9
+
+for.inc9:                                         ; preds = %for.inc9.loopexit, %polly.loop_header26.preheader
+  %indvar.next = add i32 %indvar, 1
+  %exitcond40 = icmp eq i32 %indvar.next, %N
+  br i1 %exitcond40, label %for.end11.loopexit, label %for.cond1.preheader.single_entry
+
+for.end11.loopexit:                               ; preds = %for.inc9
+  br label %for.end11
+
+for.end11:                                        ; preds = %for.end11.loopexit, %entry
+  ret void
+
+polly.loop_body.lr.ph:                            ; preds = %for.cond1.preheader.single_entry
+  %2 = call i64 @llvm.hexagon.A2.combinew(i32 %1, i32 %1)
+  %3 = bitcast i64 %2 to <2 x i32>
+  %4 = extractelement <2 x i32> %3, i32 0
+  %5 = call i64 @llvm.hexagon.A2.combinew(i32 %p_conv4, i32 %p_conv4)
+  %6 = bitcast i64 %5 to <2 x i32>
+  %p_arrayidx8.gep = getelementptr i32, i32* %C, i32 %4
+  %p_arrayidx.gep = getelementptr i16, i16* %A, i32 %4
+  br label %polly.loop_body
+
+polly.loop_body:                                  ; preds = %polly.loop_body.lr.ph, %polly.loop_body
+  %p_arrayidx8.phi = phi i32* [ %p_arrayidx8.gep, %polly.loop_body.lr.ph ], [ %p_arrayidx8.inc, %polly.loop_body ]
+  %p_arrayidx.phi = phi i16* [ %p_arrayidx.gep, %polly.loop_body.lr.ph ], [ %p_arrayidx.inc, %polly.loop_body ]
+  %polly.loopiv38 = phi i32 [ 0, %polly.loop_body.lr.ph ], [ %polly.next_loopiv, %polly.loop_body ]
+  %polly.next_loopiv = add nsw i32 %polly.loopiv38, 2
+  %vector_ptr = bitcast i16* %p_arrayidx.phi to <2 x i16>*
+  %_p_vec_full = load <2 x i16>, <2 x i16>* %vector_ptr, align 2
+  %7 = sext <2 x i16> %_p_vec_full to <2 x i32>
+  %mul5p_vec = mul <2 x i32> %7, %6
+  %vector_ptr21 = bitcast i32* %p_arrayidx8.phi to <2 x i32>*
+  store <2 x i32> %mul5p_vec, <2 x i32>* %vector_ptr21, align 4
+  %8 = icmp slt i32 %polly.next_loopiv, %leftover_lb
+  %p_arrayidx8.inc = getelementptr i32, i32* %p_arrayidx8.phi, i32 2
+  %p_arrayidx.inc = getelementptr i16, i16* %p_arrayidx.phi, i32 2
+  br i1 %8, label %polly.loop_body, label %polly.loop_header26.preheader.loopexit
+
+polly.loop_header26.preheader.loopexit:           ; preds = %polly.loop_body
+  br label %polly.loop_header26.preheader
+
+polly.loop_header26.preheader:                    ; preds = %polly.loop_header26.preheader.loopexit, %for.cond1.preheader.single_entry
+  %polly.loopiv29.ph = phi i32 [ %.mux, %for.cond1.preheader.single_entry ], [ %leftover_lb, %polly.loop_header26.preheader.loopexit ]
+  %9 = icmp slt i32 %polly.loopiv29.ph, %N
+  br i1 %9, label %polly.stmt.for.body331.preheader, label %for.inc9
+
+polly.stmt.for.body331.preheader:                 ; preds = %polly.loop_header26.preheader
+  br label %polly.stmt.for.body331
+
+polly.stmt.for.body331:                           ; preds = %polly.stmt.for.body331.preheader, %polly.stmt.for.body331
+  %polly.loopiv2939 = phi i32 [ %polly.next_loopiv30, %polly.stmt.for.body331 ], [ %polly.loopiv29.ph, %polly.stmt.for.body331.preheader ]
+  %polly.next_loopiv30 = add nsw i32 %polly.loopiv2939, 1
+  %p_32 = add i32 %polly.loopiv2939, %1
+  %p_arrayidx833 = getelementptr i32, i32* %C, i32 %p_32
+  %p_arrayidx34 = getelementptr i16, i16* %A, i32 %p_32
+  %_p_scalar_ = load i16, i16* %p_arrayidx34, align 2
+  %p_conv = sext i16 %_p_scalar_ to i32
+  %p_mul5 = mul nsw i32 %p_conv, %p_conv4
+  store i32 %p_mul5, i32* %p_arrayidx833, align 4
+  %exitcond = icmp eq i32 %polly.next_loopiv30, %N
+  br i1 %exitcond, label %for.inc9.loopexit, label %polly.stmt.for.body331
+}
+
+declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
diff --git a/test/CodeGen/Hexagon/vect/vect-fma.ll b/test/CodeGen/Hexagon/vect/vect-fma.ll
new file mode 100644
index 000000000000..c35e0159df70
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-fma.ll
@@ -0,0 +1,26 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s
+; REQUIRES: asserts
+; Used to fail with "SplitVectorResult #0: 0x16cbe60: v4f64 = fma"
+
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
+target triple = "hexagon-unknown-linux-gnu"
+
+define void @run() nounwind {
+entry:
+  br label %polly.loop_header
+
+polly.loop_after:                                 ; preds = %polly.loop_header
+  ret void
+
+polly.loop_header:                                ; preds = %polly.loop_body, %entry
+  %0 = icmp sle i32 undef, 399
+  br i1 %0, label %polly.loop_body, label %polly.loop_after
+
+polly.loop_body:                                  ; preds = %polly.loop_header
+  %_p_vec_full = load <4 x double>, <4 x double>* undef, align 8
+  %mulp_vec = fmul <4 x double> %_p_vec_full, <double 7.000000e+00, double 7.000000e+00, double 7.000000e+00, double 7.000000e+00>
+  %addp_vec = fadd <4 x double> undef, %mulp_vec
+  store <4 x double> %addp_vec, <4 x double>* undef, align 8
+  br label %polly.loop_header
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-illegal-type.ll b/test/CodeGen/Hexagon/vect/vect-illegal-type.ll
new file mode 100644
index 000000000000..3d3bf88b64d3
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-illegal-type.ll
@@ -0,0 +1,50 @@
+; RUN: llc -march=hexagon < %s
+; REQUIRES: asserts
+; Used to fail with "Unexpected illegal type!"
+; Used to fail with "Cannot select: ch = store x,x,x,<ST4[undef](align=8), trunc to v4i8>"
+
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
+target triple = "hexagon-unknown-linux-gnu"
+
+define void @foo() nounwind {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  br i1 undef, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  br label %for.body71
+
+for.body71:                                       ; preds = %for.body71, %for.end
+  br i1 undef, label %for.end96, label %for.body71
+
+for.end96:                                        ; preds = %for.body71
+  switch i32 undef, label %sw.epilog [
+    i32 1, label %for.cond375.preheader
+    i32 8, label %for.cond591
+  ]
+
+for.cond375.preheader:                            ; preds = %for.end96
+  br label %polly.loop_header228
+
+for.cond591:                                      ; preds = %for.end96
+  br label %for.body664
+
+for.body664:                                      ; preds = %for.body664, %for.cond591
+  br i1 undef, label %for.end670, label %for.body664
+
+for.end670:                                       ; preds = %for.body664
+  br label %sw.epilog
+
+sw.epilog:                                        ; preds = %for.end670, %for.end96
+  ret void
+
+polly.loop_header228:                             ; preds = %polly.loop_header228, %for.cond375.preheader
+  %_p_splat_one = load <1 x i16>, <1 x i16>* undef, align 8
+  %_p_splat = shufflevector <1 x i16> %_p_splat_one, <1 x i16> %_p_splat_one, <4 x i32> zeroinitializer
+  %0 = trunc <4 x i16> %_p_splat to <4 x i8>
+  store <4 x i8> %0, <4 x i8>* undef, align 8
+  br label %polly.loop_header228
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-insert-extract-elt.ll b/test/CodeGen/Hexagon/vect/vect-insert-extract-elt.ll
new file mode 100644
index 000000000000..baf0cd748f7f
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-insert-extract-elt.ll
@@ -0,0 +1,71 @@
+; RUN: llc -march=hexagon < %s
+; Used to fail with an infinite recursion in the insn selection.
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon-unknown-linux-gnu"
+
+%struct.elt = type { [2 x [4 x %struct.block]] }
+%struct.block = type { [2 x i16] }
+
+define void @foo(%struct.elt* noalias nocapture %p0, %struct.elt* noalias nocapture %p1) nounwind {
+entry:
+  %arrayidx1 = getelementptr inbounds %struct.elt, %struct.elt* %p1, i32 0, i32 0, i32 0, i32 3
+  %arrayidx4 = getelementptr inbounds %struct.elt, %struct.elt* %p1, i32 0, i32 0, i32 0, i32 2
+  %arrayidx7 = getelementptr inbounds %struct.elt, %struct.elt* %p0, i32 0, i32 0, i32 0, i32 3
+  %0 = bitcast %struct.block* %arrayidx7 to i32*
+  %1 = bitcast %struct.block* %arrayidx4 to i32*
+  %2 = load i32, i32* %0, align 4
+  store i32 %2, i32* %1, align 4
+  %3 = bitcast %struct.block* %arrayidx1 to i32*
+  store i32 %2, i32* %3, align 4
+  %arrayidx10 = getelementptr inbounds %struct.elt, %struct.elt* %p1, i32 0, i32 0, i32 0, i32 1
+  %arrayidx16 = getelementptr inbounds %struct.elt, %struct.elt* %p0, i32 0, i32 0, i32 0, i32 2
+  %4 = bitcast %struct.block* %arrayidx16 to i32*
+  %5 = bitcast %struct.elt* %p1 to i32*
+  %6 = load i32, i32* %4, align 4
+  store i32 %6, i32* %5, align 4
+  %7 = bitcast %struct.block* %arrayidx10 to i32*
+  store i32 %6, i32* %7, align 4
+  %p_arrayidx26 = getelementptr %struct.elt, %struct.elt* %p0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1
+  %p_arrayidx2632 = getelementptr %struct.elt, %struct.elt* %p0, i32 0, i32 0, i32 0, i32 1, i32 0, i32 1
+  %p_arrayidx2633 = getelementptr %struct.elt, %struct.elt* %p0, i32 0, i32 0, i32 0, i32 2, i32 0, i32 1
+  %p_arrayidx2634 = getelementptr %struct.elt, %struct.elt* %p0, i32 0, i32 0, i32 0, i32 3, i32 0, i32 1
+  %p_arrayidx20 = getelementptr %struct.elt, %struct.elt* %p1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1
+  %p_arrayidx2035 = getelementptr %struct.elt, %struct.elt* %p1, i32 0, i32 0, i32 0, i32 1, i32 0, i32 1
+  %p_arrayidx2036 = getelementptr %struct.elt, %struct.elt* %p1, i32 0, i32 0, i32 0, i32 2, i32 0, i32 1
+  %p_arrayidx2037 = getelementptr %struct.elt, %struct.elt* %p1, i32 0, i32 0, i32 0, i32 3, i32 0, i32 1
+  %8 = lshr i32 %6, 16
+  %9 = trunc i32 %8 to i16
+  %_p_vec_ = insertelement <4 x i16> undef, i16 %9, i32 0
+  %_p_vec_39 = insertelement <4 x i16> %_p_vec_, i16 %9, i32 1
+  %10 = lshr i32 %2, 16
+  %11 = trunc i32 %10 to i16
+  %_p_vec_41 = insertelement <4 x i16> %_p_vec_39, i16 %11, i32 2
+  %_p_vec_43 = insertelement <4 x i16> %_p_vec_41, i16 %11, i32 3
+  %shlp_vec = shl <4 x i16> %_p_vec_43, <i16 1, i16 1, i16 1, i16 1>
+  %12 = extractelement <4 x i16> %shlp_vec, i32 0
+  store i16 %12, i16* %p_arrayidx20, align 2
+  %13 = extractelement <4 x i16> %shlp_vec, i32 1
+  store i16 %13, i16* %p_arrayidx2035, align 2
+  %14 = extractelement <4 x i16> %shlp_vec, i32 2
+  store i16 %14, i16* %p_arrayidx2036, align 2
+  %15 = extractelement <4 x i16> %shlp_vec, i32 3
+  store i16 %15, i16* %p_arrayidx2037, align 2
+  %_p_scalar_44 = load i16, i16* %p_arrayidx26, align 2
+  %_p_vec_45 = insertelement <4 x i16> undef, i16 %_p_scalar_44, i32 0
+  %_p_scalar_46 = load i16, i16* %p_arrayidx2632, align 2
+  %_p_vec_47 = insertelement <4 x i16> %_p_vec_45, i16 %_p_scalar_46, i32 1
+  %_p_scalar_48 = load i16, i16* %p_arrayidx2633, align 2
+  %_p_vec_49 = insertelement <4 x i16> %_p_vec_47, i16 %_p_scalar_48, i32 2
+  %_p_scalar_50 = load i16, i16* %p_arrayidx2634, align 2
+  %_p_vec_51 = insertelement <4 x i16> %_p_vec_49, i16 %_p_scalar_50, i32 3
+  %shl28p_vec = shl <4 x i16> %_p_vec_51, <i16 1, i16 1, i16 1, i16 1>
+  %16 = extractelement <4 x i16> %shl28p_vec, i32 0
+  store i16 %16, i16* %p_arrayidx26, align 2
+  %17 = extractelement <4 x i16> %shl28p_vec, i32 1
+  store i16 %17, i16* %p_arrayidx2632, align 2
+  %18 = extractelement <4 x i16> %shl28p_vec, i32 2
+  store i16 %18, i16* %p_arrayidx2633, align 2
+  %19 = extractelement <4 x i16> %shl28p_vec, i32 3
+  store i16 %19, i16* %p_arrayidx2634, align 2
+  ret void
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-load-1.ll b/test/CodeGen/Hexagon/vect/vect-load-1.ll
new file mode 100644
index 000000000000..fbaf61d545da
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-load-1.ll
@@ -0,0 +1,26 @@
+; RUN: llc -march=hexagon < %s
+; Used to fail with "Cannot select: v2i32,ch = load 0x16c5890, 0x16f76e0, 0x16f76e0<LD2[undef](align=8), sext from v2i8>", 0x16c5890, 0x16f76e0, 0x16f76e0<LD2[undef](align=8), sext from v2i8>"
+
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
+target triple = "hexagon-unknown-linux-gnu"
+
+define void @foo() nounwind {
+entry:
+  br label %polly.loop_header
+
+polly.loop_after:                                 ; preds = %polly.loop_header
+  unreachable
+
+polly.loop_header:                                ; preds = %polly.loop_body, %entry
+  %0 = icmp sle i32 undef, 63
+  br i1 %0, label %polly.loop_body, label %polly.loop_after
+
+polly.loop_body:                                  ; preds = %polly.loop_header
+  %_p_vec_full = load <2 x i8>, <2 x i8>* undef, align 8
+  %1 = sext <2 x i8> %_p_vec_full to <2 x i32>
+  %p_vec = mul <2 x i32> %1, <i32 3, i32 3>
+  %mulp_vec = add <2 x i32> %p_vec, <i32 21, i32 21>
+  store <2 x i32> %mulp_vec, <2 x i32>* undef, align 8
+  br label %polly.loop_header
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-load.ll b/test/CodeGen/Hexagon/vect/vect-load.ll
new file mode 100644
index 000000000000..6bdcc6d3de61
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-load.ll
@@ -0,0 +1,76 @@
+; RUN: llc -march=hexagon < %s
+; Used to fail with "Cannot select: 0x16cf370: v2i16,ch = load"
+
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
+target triple = "hexagon-unknown-linux-gnu"
+
+%struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958 = type { i8, i8, i8, i8, i8, i8, i16, i32, [8 x %struct.hcdc_ext_vec.9.64.141.273.306.317.328.680.691.702.713.724.735.757.790.801.845.856.867.878.889.900.944.955.957] }
+%struct.hcdc_ext_vec.9.64.141.273.306.317.328.680.691.702.713.724.735.757.790.801.845.856.867.878.889.900.944.955.957 = type { i8, i8, i16 }
+
+define void @foo(%struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958* %hc_ext_info) nounwind {
+entry:
+  br i1 undef, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  unreachable
+
+if.end:                                           ; preds = %entry
+  br i1 undef, label %if.end5, label %if.then3
+
+if.then3:                                         ; preds = %if.end
+  br label %if.end5
+
+if.end5:                                          ; preds = %if.then3, %if.end
+  %add.ptr = getelementptr inbounds %struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958, %struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958* %hc_ext_info, i32 0, i32 8, i32 0
+  %add.ptr22 = getelementptr inbounds %struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958, %struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958* null, i32 0, i32 8, i32 undef
+  br label %while.cond
+
+while.cond:                                       ; preds = %if.end419, %if.end5
+  %gre_chksum.0 = phi <2 x i8> [ undef, %if.end5 ], [ %gre_chksum.2, %if.end419 ]
+  %cmp23 = icmp ult %struct.hcdc_ext_vec.9.64.141.273.306.317.328.680.691.702.713.724.735.757.790.801.845.856.867.878.889.900.944.955.957* null, %add.ptr
+  %cmp25 = icmp ult %struct.hcdc_ext_vec.9.64.141.273.306.317.328.680.691.702.713.724.735.757.790.801.845.856.867.878.889.900.944.955.957* null, %add.ptr22
+  %sel1 = and i1 %cmp23, %cmp25
+  br i1 %sel1, label %while.body, label %while.end422
+
+while.body:                                       ; preds = %while.cond
+  switch i8 undef, label %if.end419 [
+    i8 5, label %if.then70
+    i8 3, label %if.then70
+    i8 2, label %if.then70
+    i8 1, label %if.then70
+    i8 0, label %if.then70
+    i8 4, label %if.then93
+    i8 6, label %if.then195
+  ]
+
+if.then70:                                        ; preds = %while.body, %while.body, %while.body, %while.body, %while.body
+  unreachable
+
+if.then93:                                        ; preds = %while.body
+  unreachable
+
+if.then195:                                       ; preds = %while.body
+  br i1 undef, label %if.end274, label %if.then202
+
+if.then202:                                       ; preds = %if.then195
+  br label %while.body222
+
+while.body222:                                    ; preds = %while.body222, %if.then202
+  br i1 undef, label %if.end240, label %while.body222
+
+if.end240:                                        ; preds = %while.body222
+  %_p_vec_full100 = load <2 x i8>, <2 x i8>* undef, align 8
+  br label %if.end274
+
+if.end274:                                        ; preds = %if.end240, %if.then195
+  %gre_chksum.1 = phi <2 x i8> [ %gre_chksum.0, %if.then195 ], [ %_p_vec_full100, %if.end240 ]
+  br label %if.end419
+
+if.end419:                                        ; preds = %if.end274, %while.body
+  %gre_chksum.2 = phi <2 x i8> [ %gre_chksum.0, %while.body ], [ %gre_chksum.1, %if.end274 ]
+  br label %while.cond
+
+while.end422:                                     ; preds = %while.cond
+  ret void
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-loadv4i16.ll b/test/CodeGen/Hexagon/vect/vect-loadv4i16.ll
new file mode 100644
index 000000000000..16591ef68536
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-loadv4i16.ll
@@ -0,0 +1,73 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+
+; Check that store is post-incremented.
+; CHECK: memuh(r{{[0-9]+}} + {{ *}}#6{{ *}})
+; CHECK: combine(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}{{ *}})
+; CHECK: vaddh
+
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+define void @matrix_add_const(i32 %N, i16* nocapture %A, i16 signext %val) #0 {
+entry:
+  %cmp5 = icmp eq i32 %N, 0
+  br i1 %cmp5, label %for.end, label %polly.cond
+
+for.end.loopexit:                                 ; preds = %polly.stmt.for.body29
+  br label %for.end
+
+for.end:                                          ; preds = %for.end.loopexit, %polly.loop_header24.preheader, %entry
+  ret void
+
+polly.cond:                                       ; preds = %entry
+  %0 = icmp sgt i32 %N, 3
+  br i1 %0, label %polly.then, label %polly.loop_header24.preheader
+
+polly.then:                                       ; preds = %polly.cond
+  %1 = add i32 %N, -1
+  %leftover_lb = and i32 %1, -4
+  %2 = icmp sgt i32 %leftover_lb, 0
+  br i1 %2, label %polly.loop_body.lr.ph, label %polly.loop_header24.preheader
+
+polly.loop_body.lr.ph:                            ; preds = %polly.then
+  %3 = insertelement <4 x i16> undef, i16 %val, i32 0
+  %4 = insertelement <4 x i16> %3, i16 %val, i32 1
+  %5 = insertelement <4 x i16> %4, i16 %val, i32 2
+  %6 = insertelement <4 x i16> %5, i16 %val, i32 3
+  br label %polly.loop_body
+
+polly.loop_header24.preheader.loopexit:           ; preds = %polly.loop_body
+  br label %polly.loop_header24.preheader
+
+polly.loop_header24.preheader:                    ; preds = %polly.loop_header24.preheader.loopexit, %polly.then, %polly.cond
+  %polly.loopiv27.ph = phi i32 [ 0, %polly.cond ], [ %leftover_lb, %polly.then ], [ %leftover_lb, %polly.loop_header24.preheader.loopexit ]
+  %7 = icmp slt i32 %polly.loopiv27.ph, %N
+  br i1 %7, label %polly.stmt.for.body29.preheader, label %for.end
+
+polly.stmt.for.body29.preheader:                  ; preds = %polly.loop_header24.preheader
+  br label %polly.stmt.for.body29
+
+polly.loop_body:                                  ; preds = %polly.loop_body.lr.ph, %polly.loop_body
+  %p_arrayidx.phi = phi i16* [ %A, %polly.loop_body.lr.ph ], [ %p_arrayidx.inc, %polly.loop_body ]
+  %polly.loopiv34 = phi i32 [ 0, %polly.loop_body.lr.ph ], [ %polly.next_loopiv, %polly.loop_body ]
+  %polly.next_loopiv = add nsw i32 %polly.loopiv34, 4
+  %vector_ptr = bitcast i16* %p_arrayidx.phi to <4 x i16>*
+  %_p_vec_full = load <4 x i16>, <4 x i16>* %vector_ptr, align 2
+  %addp_vec = add <4 x i16> %_p_vec_full, %6
+  store <4 x i16> %addp_vec, <4 x i16>* %vector_ptr, align 2
+  %8 = icmp slt i32 %polly.next_loopiv, %leftover_lb
+  %p_arrayidx.inc = getelementptr i16, i16* %p_arrayidx.phi, i32 4
+  br i1 %8, label %polly.loop_body, label %polly.loop_header24.preheader.loopexit
+
+polly.stmt.for.body29:                            ; preds = %polly.stmt.for.body29.preheader, %polly.stmt.for.body29
+  %polly.loopiv2733 = phi i32 [ %polly.next_loopiv28, %polly.stmt.for.body29 ], [ %polly.loopiv27.ph, %polly.stmt.for.body29.preheader ]
+  %polly.next_loopiv28 = add nsw i32 %polly.loopiv2733, 1
+  %p_arrayidx30 = getelementptr i16, i16* %A, i32 %polly.loopiv2733
+  %_p_scalar_ = load i16, i16* %p_arrayidx30, align 2
+  %p_add = add i16 %_p_scalar_, %val
+  store i16 %p_add, i16* %p_arrayidx30, align 2
+  %exitcond = icmp eq i32 %polly.next_loopiv28, %N
+  br i1 %exitcond, label %for.end.loopexit, label %polly.stmt.for.body29
+}
+
+attributes #0 = { nounwind "fp-contract-model"="standard" "no-frame-pointer-elim-non-leaf" "realign-stack" "relocation-model"="static" "ssp-buffers-size"="8" }
diff --git a/test/CodeGen/Hexagon/vect/vect-mul-v2i16.ll b/test/CodeGen/Hexagon/vect/vect-mul-v2i16.ll
new file mode 100644
index 000000000000..f1a80115cb61
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-mul-v2i16.ll
@@ -0,0 +1,9 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: vmpyh
+; CHECK: vtrunewh
+
+define <2 x i16> @t_i2x16(<2 x i16> %a, <2 x i16> %b) nounwind {
+entry:
+	%0 = mul <2 x i16> %a, %b
+	ret <2 x i16> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-mul-v2i32.ll b/test/CodeGen/Hexagon/vect/vect-mul-v2i32.ll
new file mode 100644
index 000000000000..1d439dd37e14
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-mul-v2i32.ll
@@ -0,0 +1,9 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: mpyi
+; CHECK: mpyi
+
+define <2 x i32> @t_i2x32(<2 x i32> %a, <2 x i32> %b) nounwind {
+entry:
+	%0 = mul <2 x i32> %a, %b
+	ret <2 x i32> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-mul-v4i16.ll b/test/CodeGen/Hexagon/vect/vect-mul-v4i16.ll
new file mode 100644
index 000000000000..a50d7f8adc17
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-mul-v4i16.ll
@@ -0,0 +1,10 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: vmpyh
+; CHECK: vmpyh
+; CHECK: vtrunewh
+
+define <4 x i16> @t_i4x16(<4 x i16> %a, <4 x i16> %b) nounwind {
+entry:
+	%0 = mul <4 x i16> %a, %b
+	ret <4 x i16> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-mul-v4i8.ll b/test/CodeGen/Hexagon/vect/vect-mul-v4i8.ll
new file mode 100644
index 000000000000..d60d01460785
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-mul-v4i8.ll
@@ -0,0 +1,9 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; CHECK: vmpybsu
+; CHECK: vtrunehb
+
+define <4 x i8> @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind {
+entry:
+	%0 = mul <4 x i8> %a, %b
+	ret <4 x i8> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-mul-v8i8.ll b/test/CodeGen/Hexagon/vect/vect-mul-v8i8.ll
new file mode 100644
index 000000000000..a84cd00234ea
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-mul-v8i8.ll
@@ -0,0 +1,9 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; CHECK: vmpybsu
+; CHECK: vmpybsu
+
+define <8 x i8> @t_i8x8(<8 x i8> %a, <8 x i8> %b) nounwind {
+entry:
+	%0 = mul <8 x i8> %a, %b
+	ret <8 x i8> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-no-tfrs-1.ll b/test/CodeGen/Hexagon/vect/vect-no-tfrs-1.ll
new file mode 100644
index 000000000000..550b0f81d33a
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-no-tfrs-1.ll
@@ -0,0 +1,8 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK-NOT: r1:0 = r1:0
+
+define <4 x i16> @t_i4x16(<4 x i16> %a, <4 x i16> %b) nounwind {
+entry:
+	%0 = mul <4 x i16> %a, %b
+	ret <4 x i16> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-no-tfrs.ll b/test/CodeGen/Hexagon/vect/vect-no-tfrs.ll
new file mode 100644
index 000000000000..9081f18b3c27
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-no-tfrs.ll
@@ -0,0 +1,8 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK-NOT: r1:0 = combine(r1, r0)
+
+define <4 x i8> @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind {
+entry:
+	%0 = mul <4 x i8> %a, %b
+	ret <4 x i8> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-packhl.ll b/test/CodeGen/Hexagon/vect/vect-packhl.ll
new file mode 100644
index 000000000000..dfdb019b677c
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-packhl.ll
@@ -0,0 +1,10 @@
+; Extracted from test/CodeGen/Generic/vector-casts.ll: used to loop indefinitely.
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: packhl
+
+define void @a(<2 x double>* %p, <2 x i8>* %q) {
+        %t = load <2 x double>, <2 x double>* %p
+	%r = fptosi <2 x double> %t to <2 x i8>
+        store <2 x i8> %r, <2 x i8>* %q
+	ret void
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-shift-imm.ll b/test/CodeGen/Hexagon/vect/vect-shift-imm.ll
new file mode 100644
index 000000000000..4861181d4125
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-shift-imm.ll
@@ -0,0 +1,41 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLW
+; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRW
+; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRW
+; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLH
+; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRH
+; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRH
+;
+; Make sure that the instructions with immediate operands are generated.
+; CHECK-ASLW: vaslw({{.*}}, #9)
+; CHECK-ASRW: vasrw({{.*}}, #8)
+; CHECK-LSRW: vlsrw({{.*}}, #7)
+; CHECK-ASLH: vaslh({{.*}}, #6)
+; CHECK-ASRH: vasrh({{.*}}, #5)
+; CHECK-LSRH: vlsrh({{.*}}, #4)
+
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+define i64 @foo(i64 %x) nounwind readnone {
+entry:
+  %0 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %x, i32 9)
+  %1 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %x, i32 8)
+  %2 = tail call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %x, i32 7)
+  %3 = tail call i64 @llvm.hexagon.S2.asl.i.vh(i64 %x, i32 6)
+  %4 = tail call i64 @llvm.hexagon.S2.asr.i.vh(i64 %x, i32 5)
+  %5 = tail call i64 @llvm.hexagon.S2.lsr.i.vh(i64 %x, i32 4)
+  %add = add i64 %1, %0
+  %add1 = add i64 %add, %2
+  %add2 = add i64 %add1, %3
+  %add3 = add i64 %add2, %4
+  %add4 = add i64 %add3, %5
+  ret i64 %add4
+}
+
+declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) nounwind readnone
+declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) nounwind readnone
+declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32) nounwind readnone
+declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) nounwind readnone
+declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32) nounwind readnone
+declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32) nounwind readnone
+
diff --git a/test/CodeGen/Hexagon/vect/vect-shuffle.ll b/test/CodeGen/Hexagon/vect/vect-shuffle.ll
new file mode 100644
index 000000000000..9d80df2e0887
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-shuffle.ll
@@ -0,0 +1,47 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+
+; Check that store is post-incremented.
+; CHECK-NOT: extractu
+; CHECK-NOT: insert
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+define i32 @foo(i16* noalias nocapture %src, i16* noalias nocapture %dstImg, i32 %width, i32 %idx, i32 %flush) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.A2.combinew(i32 %flush, i32 %flush)
+  %1 = bitcast i64 %0 to <2 x i32>
+  br label %polly.loop_body
+
+polly.loop_after:                                 ; preds = %polly.loop_body
+  ret i32 0
+
+polly.loop_body:                                  ; preds = %entry, %polly.loop_body
+  %p_arrayidx35.phi = phi i16* [ %dstImg, %entry ], [ %p_arrayidx35.inc, %polly.loop_body ]
+  %p_arrayidx.phi = phi i16* [ %src, %entry ], [ %p_arrayidx.inc, %polly.loop_body ]
+  %polly.loopiv56 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ]
+  %polly.next_loopiv = add nsw i32 %polly.loopiv56, 4
+  %vector_ptr = bitcast i16* %p_arrayidx.phi to <4 x i16>*
+  %_p_vec_full = load <4 x i16>, <4 x i16>* %vector_ptr, align 2
+  %_high_half = shufflevector <4 x i16> %_p_vec_full, <4 x i16> undef, <2 x i32> <i32 2, i32 3>
+  %_low_half = shufflevector <4 x i16> %_p_vec_full, <4 x i16> undef, <2 x i32> <i32 0, i32 1>
+  %2 = zext <2 x i16> %_low_half to <2 x i32>
+  %3 = zext <2 x i16> %_high_half to <2 x i32>
+  %add33p_vec = add <2 x i32> %2, %1
+  %add33p_vec48 = add <2 x i32> %3, %1
+  %4 = trunc <2 x i32> %add33p_vec to <2 x i16>
+  %5 = trunc <2 x i32> %add33p_vec48 to <2 x i16>
+  %_combined_vec = shufflevector <2 x i16> %4, <2 x i16> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %vector_ptr49 = bitcast i16* %p_arrayidx35.phi to <4 x i16>*
+  store <4 x i16> %_combined_vec, <4 x i16>* %vector_ptr49, align 2
+  %6 = icmp slt i32 %polly.next_loopiv, 1024
+  %p_arrayidx35.inc = getelementptr i16, i16* %p_arrayidx35.phi, i32 4
+  %p_arrayidx.inc = getelementptr i16, i16* %p_arrayidx.phi, i32 4
+  br i1 %6, label %polly.loop_body, label %polly.loop_after
+}
+
+declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+
diff --git a/test/CodeGen/Hexagon/vect/vect-splat.ll b/test/CodeGen/Hexagon/vect/vect-splat.ll
new file mode 100644
index 000000000000..3613dbf6fdd1
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-splat.ll
@@ -0,0 +1,16 @@
+; Extracted from test/CodeGen/Generic/vector.ll: used to loop indefinitely.
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; CHECK: combine
+
+%i4 = type <4 x i32>
+
+define void @splat_i4(%i4* %P, %i4* %Q, i32 %X) {
+	%tmp = insertelement %i4 undef, i32 %X, i32 0		; <%i4> [#uses=1]
+	%tmp2 = insertelement %i4 %tmp, i32 %X, i32 1		; <%i4> [#uses=1]
+	%tmp4 = insertelement %i4 %tmp2, i32 %X, i32 2		; <%i4> [#uses=1]
+	%tmp6 = insertelement %i4 %tmp4, i32 %X, i32 3		; <%i4> [#uses=1]
+	%q = load %i4, %i4* %Q		; <%i4> [#uses=1]
+	%R = add %i4 %q, %tmp6		; <%i4> [#uses=1]
+	store %i4 %R, %i4* %P
+	ret void
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-store-v2i16.ll b/test/CodeGen/Hexagon/vect/vect-store-v2i16.ll
new file mode 100644
index 000000000000..1de3058e68a6
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-store-v2i16.ll
@@ -0,0 +1,51 @@
+; RUN: llc -march=hexagon < %s
+; Used to fail with: "Cannot select: 0x3bab680: ch = store <ST4[%lsr.iv522525], trunc to v2i16>
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
+target triple = "hexagon-unknown-linux-gnu"
+
+define void @foobar() nounwind {
+entry:
+  br label %for.cond7.preheader.single_entry.i
+
+for.cond7.preheader.single_entry.i:               ; preds = %for.cond7.preheader.single_entry.i, %entry
+  %exitcond72.i = icmp eq i32 undef, 64
+  br i1 %exitcond72.i, label %foo_32.exit, label %for.cond7.preheader.single_entry.i
+
+foo_32.exit:                         ; preds = %for.cond7.preheader.single_entry.i
+  br label %for.body.i428
+
+for.body.i428:                                    ; preds = %for.body.i428, %foo_32.exit
+  br i1 undef, label %foo_12.exit, label %for.body.i428
+
+foo_12.exit:                            ; preds = %for.body.i428
+  br label %for.body.i.i
+
+for.body.i.i:                                     ; preds = %for.body.i.i, %foo_12.exit
+  br i1 undef, label %foo_14.exit, label %for.body.i.i
+
+foo_14.exit:                         ; preds = %for.body.i.i
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %foo_14.exit
+  br i1 undef, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  %storemerge294 = select i1 undef, i32 32767, i32 undef
+  %_p_splat_one386 = insertelement <1 x i32> undef, i32 %storemerge294, i32 0
+  %_p_splat387 = shufflevector <1 x i32> %_p_splat_one386, <1 x i32> undef, <2 x i32> zeroinitializer
+  br label %polly.loop_body377
+
+polly.loop_after378:                              ; preds = %polly.loop_body377
+  unreachable
+
+polly.loop_body377:                               ; preds = %polly.loop_body377, %for.end
+  %_p_vec_full384 = load <2 x i16>, <2 x i16>* undef, align 4
+  %0 = sext <2 x i16> %_p_vec_full384 to <2 x i32>
+  %mulp_vec = mul <2 x i32> %0, %_p_splat387
+  %shr100293p_vec = lshr <2 x i32> %mulp_vec, <i32 15, i32 15>
+  %1 = trunc <2 x i32> %shr100293p_vec to <2 x i16>
+  store <2 x i16> %1, <2 x i16>* undef, align 4
+  br i1 undef, label %polly.loop_body377, label %polly.loop_after378
+}
+
diff --git a/test/CodeGen/Hexagon/vect/vect-truncate.ll b/test/CodeGen/Hexagon/vect/vect-truncate.ll
new file mode 100644
index 000000000000..fd75bbd58e36
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-truncate.ll
@@ -0,0 +1,42 @@
+; RUN: llc -march=hexagon < %s
+; Used to fail with "Cannot select: 0x16cb7f0: v2i16 = truncate"
+
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
+target triple = "hexagon-unknown-linux-gnu"
+
+define void @Autocorr() nounwind {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  br i1 undef, label %polly.loop_header43, label %for.body
+
+do.cond:                                          ; preds = %polly.loop_header
+  unreachable
+
+do.end:                                           ; preds = %polly.loop_after45
+  ret void
+
+polly.loop_header:                                ; preds = %polly.loop_after45, %polly.loop_body
+  %0 = icmp sle i32 undef, 239
+  br i1 %0, label %polly.loop_body, label %do.cond
+
+polly.loop_body:                                  ; preds = %polly.loop_header
+  %p_25 = call i32 @llvm.hexagon.SI.to.SXTHI.asrh(i32 undef)
+  %1 = insertelement <4 x i32> undef, i32 %p_25, i32 3
+  %2 = trunc <4 x i32> %1 to <4 x i16>
+  store <4 x i16> %2, <4 x i16>* undef, align 8
+  br label %polly.loop_header
+
+polly.loop_after45:                               ; preds = %polly.loop_header43
+  br i1 undef, label %polly.loop_header, label %do.end
+
+polly.loop_header43:                              ; preds = %polly.loop_body44, %for.body
+  br i1 undef, label %polly.loop_body44, label %polly.loop_after45
+
+polly.loop_body44:                                ; preds = %polly.loop_header43
+  br label %polly.loop_header43
+}
+
+declare i32 @llvm.hexagon.SI.to.SXTHI.asrh(i32) nounwind readnone
diff --git a/test/CodeGen/Hexagon/vect/vect-vaddb-1.ll b/test/CodeGen/Hexagon/vect/vect-vaddb-1.ll
new file mode 100644
index 000000000000..e646f8efdd5e
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-vaddb-1.ll
@@ -0,0 +1,8 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: vaddub
+
+define <4 x i8> @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind {
+entry:
+	%0 = add <4 x i8> %a, %b
+	ret <4 x i8> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-vaddb.ll b/test/CodeGen/Hexagon/vect/vect-vaddb.ll
new file mode 100644
index 000000000000..459546991903
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-vaddb.ll
@@ -0,0 +1,8 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: vaddub
+
+define <8 x i8> @t_i8x8(<8 x i8> %a, <8 x i8> %b) nounwind {
+entry:
+	%0 = add <8 x i8> %a, %b
+	ret <8 x i8> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-vaddh-1.ll b/test/CodeGen/Hexagon/vect/vect-vaddh-1.ll
new file mode 100644
index 000000000000..1b43d4fb6cc8
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-vaddh-1.ll
@@ -0,0 +1,8 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: vaddh
+
+define <4 x i16> @t_i4x16(<4 x i16> %a, <4 x i16> %b) nounwind {
+entry:
+	%0 = add <4 x i16> %a, %b
+	ret <4 x i16> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-vaddh.ll b/test/CodeGen/Hexagon/vect/vect-vaddh.ll
new file mode 100644
index 000000000000..32bf3cadacdc
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-vaddh.ll
@@ -0,0 +1,8 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: vaddh
+
+define <2 x i16> @t_i2x16(<2 x i16> %a, <2 x i16> %b) nounwind {
+entry:
+	%0 = add <2 x i16> %a, %b
+	ret <2 x i16> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-vaddw.ll b/test/CodeGen/Hexagon/vect/vect-vaddw.ll
new file mode 100644
index 000000000000..a8401345ab26
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-vaddw.ll
@@ -0,0 +1,8 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: vaddw
+
+define <2 x i32> @t_i2x32(<2 x i32> %a, <2 x i32> %b) nounwind {
+entry:
+	%0 = add <2 x i32> %a, %b
+	ret <2 x i32> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-vaslw.ll b/test/CodeGen/Hexagon/vect/vect-vaslw.ll
new file mode 100644
index 000000000000..c662b0bd3de2
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-vaslw.ll
@@ -0,0 +1,33 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: vaslw
+
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon-unknown-linux-gnu"
+
+define void @foo(i16* nocapture %v) nounwind {
+entry:
+  %p_arrayidx = getelementptr i16, i16* %v, i32 4
+  %vector_ptr = bitcast i16* %p_arrayidx to <4 x i16>*
+  %_p_vec_full = load <4 x i16>, <4 x i16>* %vector_ptr, align 2
+  %_high_half = shufflevector <4 x i16> %_p_vec_full, <4 x i16> undef, <2 x i32> <i32 2, i32 3>
+  %_low_half = shufflevector <4 x i16> %_p_vec_full, <4 x i16> undef, <2 x i32> <i32 0, i32 1>
+  %0 = sext <2 x i16> %_low_half to <2 x i32>
+  %1 = sext <2 x i16> %_high_half to <2 x i32>
+  %shr6p_vec = shl <2 x i32> %0, <i32 2, i32 2>
+  %shr6p_vec19 = shl <2 x i32> %1, <i32 2, i32 2>
+  %addp_vec = add <2 x i32> %shr6p_vec, <i32 34, i32 34>
+  %addp_vec20 = add <2 x i32> %shr6p_vec19, <i32 34, i32 34>
+  %vector_ptr21 = bitcast i16* %v to <4 x i16>*
+  %_p_vec_full22 = load <4 x i16>, <4 x i16>* %vector_ptr21, align 2
+  %_high_half23 = shufflevector <4 x i16> %_p_vec_full22, <4 x i16> undef, <2 x i32> <i32 2, i32 3>
+  %_low_half24 = shufflevector <4 x i16> %_p_vec_full22, <4 x i16> undef, <2 x i32> <i32 0, i32 1>
+  %2 = zext <2 x i16> %_low_half24 to <2 x i32>
+  %3 = zext <2 x i16> %_high_half23 to <2 x i32>
+  %add3p_vec = add <2 x i32> %addp_vec, %2
+  %add3p_vec25 = add <2 x i32> %addp_vec20, %3
+  %4 = trunc <2 x i32> %add3p_vec to <2 x i16>
+  %5 = trunc <2 x i32> %add3p_vec25 to <2 x i16>
+  %_combined_vec = shufflevector <2 x i16> %4, <2 x i16> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  store <4 x i16> %_combined_vec, <4 x i16>* %vector_ptr21, align 2
+  ret void
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-vshifts.ll b/test/CodeGen/Hexagon/vect/vect-vshifts.ll
new file mode 100644
index 000000000000..49ff812601ae
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-vshifts.ll
@@ -0,0 +1,279 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+
+; Check that store is post-incremented.
+; CHECK: r{{[0-9]+:[0-9]+}} = vasrw(r{{[0-9]+:[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = vaslw(r{{[0-9]+:[0-9]+}}, r{{[0-9]+}})
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+define void @foo(i32* nocapture %buf, i32* nocapture %dest, i32 %offset, i32 %oddBlock, i32 %gb) #0 {
+entry:
+  %0 = load i32, i32* %buf, align 4, !tbaa !0
+  %shr = ashr i32 %0, %gb
+  store i32 %shr, i32* %buf, align 4, !tbaa !0
+  %not.tobool = icmp eq i32 %oddBlock, 0
+  %1 = sub i32 %offset, %oddBlock
+  %2 = zext i1 %not.tobool to i32
+  %3 = and i32 %1, 7
+  %4 = add i32 %2, %3
+  %5 = add i32 %4, 8
+  %p_sub8 = sub nsw i32 31, %gb
+  %6 = insertelement <2 x i32> undef, i32 %p_sub8, i32 0
+  %7 = insertelement <2 x i32> %6, i32 %p_sub8, i32 1
+  %8 = bitcast <2 x i32> %7 to i64
+  %9 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %8, i32 1)
+  %10 = bitcast i64 %9 to <2 x i32>
+  %11 = tail call i64 @llvm.hexagon.A2.combinew(i32 -1, i32 -1)
+  %12 = bitcast i64 %11 to <2 x i32>
+  %sub12p_vec = add <2 x i32> %10, %12
+  %p_22 = add i32 %4, 64
+  %p_d.018 = getelementptr i32, i32* %dest, i32 %4
+  %p_d.01823 = getelementptr i32, i32* %dest, i32 %p_22
+  %p_25 = add i32 %4, 72
+  %p_arrayidx14 = getelementptr i32, i32* %dest, i32 %5
+  %p_arrayidx1426 = getelementptr i32, i32* %dest, i32 %p_25
+  %_p_scalar_ = load i32, i32* %p_d.018, align 4
+  %_p_vec_ = insertelement <2 x i32> undef, i32 %_p_scalar_, i32 0
+  %_p_scalar_27 = load i32, i32* %p_d.01823, align 4
+  %_p_vec_28 = insertelement <2 x i32> %_p_vec_, i32 %_p_scalar_27, i32 1
+  %13 = bitcast <2 x i32> %_p_vec_28 to i64
+  %14 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %13, i32 31)
+  %15 = bitcast i64 %14 to <2 x i32>
+  %shr9p_vec = ashr <2 x i32> %_p_vec_28, %7
+  %xorp_vec = xor <2 x i32> %15, %sub12p_vec
+  %16 = bitcast <2 x i32> %shr9p_vec to i64
+  %17 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %14, i64 %16)
+  %18 = bitcast <2 x i32> %xorp_vec to i64
+  %19 = tail call i64 @llvm.hexagon.C2.vmux(i32 %17, i64 %13, i64 %18)
+  %20 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %19, i32 %gb)
+  %21 = bitcast i64 %20 to <2 x i32>
+  %22 = extractelement <2 x i32> %21, i32 0
+  store i32 %22, i32* %p_arrayidx14, align 4
+  %23 = extractelement <2 x i32> %21, i32 1
+  store i32 %23, i32* %p_arrayidx1426, align 4
+  store i32 %22, i32* %p_d.018, align 4
+  store i32 %23, i32* %p_d.01823, align 4
+  %p_21.1 = add i32 %4, 128
+  %p_22.1 = add i32 %4, 192
+  %p_d.018.1 = getelementptr i32, i32* %dest, i32 %p_21.1
+  %p_d.01823.1 = getelementptr i32, i32* %dest, i32 %p_22.1
+  %p_24.1 = add i32 %4, 136
+  %p_25.1 = add i32 %4, 200
+  %p_arrayidx14.1 = getelementptr i32, i32* %dest, i32 %p_24.1
+  %p_arrayidx1426.1 = getelementptr i32, i32* %dest, i32 %p_25.1
+  %_p_scalar_.1 = load i32, i32* %p_d.018.1, align 4
+  %_p_vec_.1 = insertelement <2 x i32> undef, i32 %_p_scalar_.1, i32 0
+  %_p_scalar_27.1 = load i32, i32* %p_d.01823.1, align 4
+  %_p_vec_28.1 = insertelement <2 x i32> %_p_vec_.1, i32 %_p_scalar_27.1, i32 1
+  %24 = bitcast <2 x i32> %_p_vec_28.1 to i64
+  %25 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %24, i32 31)
+  %26 = bitcast i64 %25 to <2 x i32>
+  %shr9p_vec.1 = ashr <2 x i32> %_p_vec_28.1, %7
+  %xorp_vec.1 = xor <2 x i32> %26, %sub12p_vec
+  %27 = bitcast <2 x i32> %shr9p_vec.1 to i64
+  %28 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %25, i64 %27)
+  %29 = bitcast <2 x i32> %xorp_vec.1 to i64
+  %30 = tail call i64 @llvm.hexagon.C2.vmux(i32 %28, i64 %24, i64 %29)
+  %31 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %30, i32 %gb)
+  %32 = bitcast i64 %31 to <2 x i32>
+  %33 = extractelement <2 x i32> %32, i32 0
+  store i32 %33, i32* %p_arrayidx14.1, align 4
+  %34 = extractelement <2 x i32> %32, i32 1
+  store i32 %34, i32* %p_arrayidx1426.1, align 4
+  store i32 %33, i32* %p_d.018.1, align 4
+  store i32 %34, i32* %p_d.01823.1, align 4
+  %p_21.2 = add i32 %4, 256
+  %p_22.2 = add i32 %4, 320
+  %p_d.018.2 = getelementptr i32, i32* %dest, i32 %p_21.2
+  %p_d.01823.2 = getelementptr i32, i32* %dest, i32 %p_22.2
+  %p_24.2 = add i32 %4, 264
+  %p_25.2 = add i32 %4, 328
+  %p_arrayidx14.2 = getelementptr i32, i32* %dest, i32 %p_24.2
+  %p_arrayidx1426.2 = getelementptr i32, i32* %dest, i32 %p_25.2
+  %_p_scalar_.2 = load i32, i32* %p_d.018.2, align 4
+  %_p_vec_.2 = insertelement <2 x i32> undef, i32 %_p_scalar_.2, i32 0
+  %_p_scalar_27.2 = load i32, i32* %p_d.01823.2, align 4
+  %_p_vec_28.2 = insertelement <2 x i32> %_p_vec_.2, i32 %_p_scalar_27.2, i32 1
+  %35 = bitcast <2 x i32> %_p_vec_28.2 to i64
+  %36 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %35, i32 31)
+  %37 = bitcast i64 %36 to <2 x i32>
+  %shr9p_vec.2 = ashr <2 x i32> %_p_vec_28.2, %7
+  %xorp_vec.2 = xor <2 x i32> %37, %sub12p_vec
+  %38 = bitcast <2 x i32> %shr9p_vec.2 to i64
+  %39 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %36, i64 %38)
+  %40 = bitcast <2 x i32> %xorp_vec.2 to i64
+  %41 = tail call i64 @llvm.hexagon.C2.vmux(i32 %39, i64 %35, i64 %40)
+  %42 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %41, i32 %gb)
+  %43 = bitcast i64 %42 to <2 x i32>
+  %44 = extractelement <2 x i32> %43, i32 0
+  store i32 %44, i32* %p_arrayidx14.2, align 4
+  %45 = extractelement <2 x i32> %43, i32 1
+  store i32 %45, i32* %p_arrayidx1426.2, align 4
+  store i32 %44, i32* %p_d.018.2, align 4
+  store i32 %45, i32* %p_d.01823.2, align 4
+  %p_21.3 = add i32 %4, 384
+  %p_22.3 = add i32 %4, 448
+  %p_d.018.3 = getelementptr i32, i32* %dest, i32 %p_21.3
+  %p_d.01823.3 = getelementptr i32, i32* %dest, i32 %p_22.3
+  %p_24.3 = add i32 %4, 392
+  %p_25.3 = add i32 %4, 456
+  %p_arrayidx14.3 = getelementptr i32, i32* %dest, i32 %p_24.3
+  %p_arrayidx1426.3 = getelementptr i32, i32* %dest, i32 %p_25.3
+  %_p_scalar_.3 = load i32, i32* %p_d.018.3, align 4
+  %_p_vec_.3 = insertelement <2 x i32> undef, i32 %_p_scalar_.3, i32 0
+  %_p_scalar_27.3 = load i32, i32* %p_d.01823.3, align 4
+  %_p_vec_28.3 = insertelement <2 x i32> %_p_vec_.3, i32 %_p_scalar_27.3, i32 1
+  %46 = bitcast <2 x i32> %_p_vec_28.3 to i64
+  %47 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %46, i32 31)
+  %48 = bitcast i64 %47 to <2 x i32>
+  %shr9p_vec.3 = ashr <2 x i32> %_p_vec_28.3, %7
+  %xorp_vec.3 = xor <2 x i32> %48, %sub12p_vec
+  %49 = bitcast <2 x i32> %shr9p_vec.3 to i64
+  %50 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %47, i64 %49)
+  %51 = bitcast <2 x i32> %xorp_vec.3 to i64
+  %52 = tail call i64 @llvm.hexagon.C2.vmux(i32 %50, i64 %46, i64 %51)
+  %53 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %52, i32 %gb)
+  %54 = bitcast i64 %53 to <2 x i32>
+  %55 = extractelement <2 x i32> %54, i32 0
+  store i32 %55, i32* %p_arrayidx14.3, align 4
+  %56 = extractelement <2 x i32> %54, i32 1
+  store i32 %56, i32* %p_arrayidx1426.3, align 4
+  store i32 %55, i32* %p_d.018.3, align 4
+  store i32 %56, i32* %p_d.01823.3, align 4
+  %p_21.4 = add i32 %4, 512
+  %p_22.4 = add i32 %4, 576
+  %p_d.018.4 = getelementptr i32, i32* %dest, i32 %p_21.4
+  %p_d.01823.4 = getelementptr i32, i32* %dest, i32 %p_22.4
+  %p_24.4 = add i32 %4, 520
+  %p_25.4 = add i32 %4, 584
+  %p_arrayidx14.4 = getelementptr i32, i32* %dest, i32 %p_24.4
+  %p_arrayidx1426.4 = getelementptr i32, i32* %dest, i32 %p_25.4
+  %_p_scalar_.4 = load i32, i32* %p_d.018.4, align 4
+  %_p_vec_.4 = insertelement <2 x i32> undef, i32 %_p_scalar_.4, i32 0
+  %_p_scalar_27.4 = load i32, i32* %p_d.01823.4, align 4
+  %_p_vec_28.4 = insertelement <2 x i32> %_p_vec_.4, i32 %_p_scalar_27.4, i32 1
+  %57 = bitcast <2 x i32> %_p_vec_28.4 to i64
+  %58 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %57, i32 31)
+  %59 = bitcast i64 %58 to <2 x i32>
+  %shr9p_vec.4 = ashr <2 x i32> %_p_vec_28.4, %7
+  %xorp_vec.4 = xor <2 x i32> %59, %sub12p_vec
+  %60 = bitcast <2 x i32> %shr9p_vec.4 to i64
+  %61 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %58, i64 %60)
+  %62 = bitcast <2 x i32> %xorp_vec.4 to i64
+  %63 = tail call i64 @llvm.hexagon.C2.vmux(i32 %61, i64 %57, i64 %62)
+  %64 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %63, i32 %gb)
+  %65 = bitcast i64 %64 to <2 x i32>
+  %66 = extractelement <2 x i32> %65, i32 0
+  store i32 %66, i32* %p_arrayidx14.4, align 4
+  %67 = extractelement <2 x i32> %65, i32 1
+  store i32 %67, i32* %p_arrayidx1426.4, align 4
+  store i32 %66, i32* %p_d.018.4, align 4
+  store i32 %67, i32* %p_d.01823.4, align 4
+  %p_21.5 = add i32 %4, 640
+  %p_22.5 = add i32 %4, 704
+  %p_d.018.5 = getelementptr i32, i32* %dest, i32 %p_21.5
+  %p_d.01823.5 = getelementptr i32, i32* %dest, i32 %p_22.5
+  %p_24.5 = add i32 %4, 648
+  %p_25.5 = add i32 %4, 712
+  %p_arrayidx14.5 = getelementptr i32, i32* %dest, i32 %p_24.5
+  %p_arrayidx1426.5 = getelementptr i32, i32* %dest, i32 %p_25.5
+  %_p_scalar_.5 = load i32, i32* %p_d.018.5, align 4
+  %_p_vec_.5 = insertelement <2 x i32> undef, i32 %_p_scalar_.5, i32 0
+  %_p_scalar_27.5 = load i32, i32* %p_d.01823.5, align 4
+  %_p_vec_28.5 = insertelement <2 x i32> %_p_vec_.5, i32 %_p_scalar_27.5, i32 1
+  %68 = bitcast <2 x i32> %_p_vec_28.5 to i64
+  %69 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %68, i32 31)
+  %70 = bitcast i64 %69 to <2 x i32>
+  %shr9p_vec.5 = ashr <2 x i32> %_p_vec_28.5, %7
+  %xorp_vec.5 = xor <2 x i32> %70, %sub12p_vec
+  %71 = bitcast <2 x i32> %shr9p_vec.5 to i64
+  %72 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %69, i64 %71)
+  %73 = bitcast <2 x i32> %xorp_vec.5 to i64
+  %74 = tail call i64 @llvm.hexagon.C2.vmux(i32 %72, i64 %68, i64 %73)
+  %75 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %74, i32 %gb)
+  %76 = bitcast i64 %75 to <2 x i32>
+  %77 = extractelement <2 x i32> %76, i32 0
+  store i32 %77, i32* %p_arrayidx14.5, align 4
+  %78 = extractelement <2 x i32> %76, i32 1
+  store i32 %78, i32* %p_arrayidx1426.5, align 4
+  store i32 %77, i32* %p_d.018.5, align 4
+  store i32 %78, i32* %p_d.01823.5, align 4
+  %p_21.6 = add i32 %4, 768
+  %p_22.6 = add i32 %4, 832
+  %p_d.018.6 = getelementptr i32, i32* %dest, i32 %p_21.6
+  %p_d.01823.6 = getelementptr i32, i32* %dest, i32 %p_22.6
+  %p_24.6 = add i32 %4, 776
+  %p_25.6 = add i32 %4, 840
+  %p_arrayidx14.6 = getelementptr i32, i32* %dest, i32 %p_24.6
+  %p_arrayidx1426.6 = getelementptr i32, i32* %dest, i32 %p_25.6
+  %_p_scalar_.6 = load i32, i32* %p_d.018.6, align 4
+  %_p_vec_.6 = insertelement <2 x i32> undef, i32 %_p_scalar_.6, i32 0
+  %_p_scalar_27.6 = load i32, i32* %p_d.01823.6, align 4
+  %_p_vec_28.6 = insertelement <2 x i32> %_p_vec_.6, i32 %_p_scalar_27.6, i32 1
+  %79 = bitcast <2 x i32> %_p_vec_28.6 to i64
+  %80 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %79, i32 31)
+  %81 = bitcast i64 %80 to <2 x i32>
+  %shr9p_vec.6 = ashr <2 x i32> %_p_vec_28.6, %7
+  %xorp_vec.6 = xor <2 x i32> %81, %sub12p_vec
+  %82 = bitcast <2 x i32> %shr9p_vec.6 to i64
+  %83 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %80, i64 %82)
+  %84 = bitcast <2 x i32> %xorp_vec.6 to i64
+  %85 = tail call i64 @llvm.hexagon.C2.vmux(i32 %83, i64 %79, i64 %84)
+  %86 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %85, i32 %gb)
+  %87 = bitcast i64 %86 to <2 x i32>
+  %88 = extractelement <2 x i32> %87, i32 0
+  store i32 %88, i32* %p_arrayidx14.6, align 4
+  %89 = extractelement <2 x i32> %87, i32 1
+  store i32 %89, i32* %p_arrayidx1426.6, align 4
+  store i32 %88, i32* %p_d.018.6, align 4
+  store i32 %89, i32* %p_d.01823.6, align 4
+  %p_21.7 = add i32 %4, 896
+  %p_22.7 = add i32 %4, 960
+  %p_d.018.7 = getelementptr i32, i32* %dest, i32 %p_21.7
+  %p_d.01823.7 = getelementptr i32, i32* %dest, i32 %p_22.7
+  %p_24.7 = add i32 %4, 904
+  %p_25.7 = add i32 %4, 968
+  %p_arrayidx14.7 = getelementptr i32, i32* %dest, i32 %p_24.7
+  %p_arrayidx1426.7 = getelementptr i32, i32* %dest, i32 %p_25.7
+  %_p_scalar_.7 = load i32, i32* %p_d.018.7, align 4
+  %_p_vec_.7 = insertelement <2 x i32> undef, i32 %_p_scalar_.7, i32 0
+  %_p_scalar_27.7 = load i32, i32* %p_d.01823.7, align 4
+  %_p_vec_28.7 = insertelement <2 x i32> %_p_vec_.7, i32 %_p_scalar_27.7, i32 1
+  %90 = bitcast <2 x i32> %_p_vec_28.7 to i64
+  %91 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %90, i32 31)
+  %92 = bitcast i64 %91 to <2 x i32>
+  %shr9p_vec.7 = ashr <2 x i32> %_p_vec_28.7, %7
+  %xorp_vec.7 = xor <2 x i32> %92, %sub12p_vec
+  %93 = bitcast <2 x i32> %shr9p_vec.7 to i64
+  %94 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %91, i64 %93)
+  %95 = bitcast <2 x i32> %xorp_vec.7 to i64
+  %96 = tail call i64 @llvm.hexagon.C2.vmux(i32 %94, i64 %90, i64 %95)
+  %97 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %96, i32 %gb)
+  %98 = bitcast i64 %97 to <2 x i32>
+  %99 = extractelement <2 x i32> %98, i32 0
+  store i32 %99, i32* %p_arrayidx14.7, align 4
+  %100 = extractelement <2 x i32> %98, i32 1
+  store i32 %100, i32* %p_arrayidx1426.7, align 4
+  store i32 %99, i32* %p_d.018.7, align 4
+  store i32 %100, i32* %p_d.01823.7, align 4
+  ret void
+}
+
+declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) #1
+
+declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) #1
+
+declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
+
+declare i32 @llvm.hexagon.A2.vcmpweq(i64, i64) #1
+
+declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64) #1
+
+declare i64 @llvm.hexagon.S2.asl.r.vw(i64, i32) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+!0 = !{!"int", !1}
+!1 = !{!"omnipotent char", !2}
+!2 = !{!"Simple C/C++ TBAA"}
diff --git a/test/CodeGen/Hexagon/vect/vect-vsplatb.ll b/test/CodeGen/Hexagon/vect/vect-vsplatb.ll
new file mode 100644
index 000000000000..6996dd144eba
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-vsplatb.ll
@@ -0,0 +1,29 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; Make sure we build the constant vector <7, 7, 7, 7> with a vsplatb.
+; CHECK: vsplatb
+@B = common global [400 x i8] zeroinitializer, align 8
+@A = common global [400 x i8] zeroinitializer, align 8
+@C = common global [400 x i8] zeroinitializer, align 8
+
+define void @run() nounwind {
+entry:
+  br label %polly.loop_body
+
+polly.loop_after:                                 ; preds = %polly.loop_body
+  ret void
+
+polly.loop_body:                                  ; preds = %entry, %polly.loop_body
+  %polly.loopiv25 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ]
+  %polly.next_loopiv = add i32 %polly.loopiv25, 4
+  %p_arrayidx1 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %polly.loopiv25
+  %p_arrayidx = getelementptr [400 x i8], [400 x i8]* @B, i32 0, i32 %polly.loopiv25
+  %vector_ptr = bitcast i8* %p_arrayidx to <4 x i8>*
+  %_p_vec_full = load <4 x i8>, <4 x i8>* %vector_ptr, align 8
+  %mulp_vec = mul <4 x i8> %_p_vec_full, <i8 7, i8 7, i8 7, i8 7>
+  %vector_ptr14 = bitcast i8* %p_arrayidx1 to <4 x i8>*
+  %_p_vec_full15 = load <4 x i8>, <4 x i8>* %vector_ptr14, align 8
+  %addp_vec = add <4 x i8> %_p_vec_full15, %mulp_vec
+  store <4 x i8> %addp_vec, <4 x i8>* %vector_ptr14, align 8
+  %0 = icmp slt i32 %polly.next_loopiv, 400
+  br i1 %0, label %polly.loop_body, label %polly.loop_after
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-vsplath.ll b/test/CodeGen/Hexagon/vect/vect-vsplath.ll
new file mode 100644
index 000000000000..f5207109773e
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-vsplath.ll
@@ -0,0 +1,29 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; Make sure we build the constant vector <7, 7, 7, 7> with a vsplath.
+; CHECK: vsplath
+@B = common global [400 x i16] zeroinitializer, align 8
+@A = common global [400 x i16] zeroinitializer, align 8
+@C = common global [400 x i16] zeroinitializer, align 8
+
+define void @run() nounwind {
+entry:
+  br label %polly.loop_body
+
+polly.loop_after:                                 ; preds = %polly.loop_body
+  ret void
+
+polly.loop_body:                                  ; preds = %entry, %polly.loop_body
+  %polly.loopiv26 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ]
+  %polly.next_loopiv = add nsw i32 %polly.loopiv26, 4
+  %p_arrayidx1 = getelementptr [400 x i16], [400 x i16]* @A, i32 0, i32 %polly.loopiv26
+  %p_arrayidx = getelementptr [400 x i16], [400 x i16]* @B, i32 0, i32 %polly.loopiv26
+  %vector_ptr = bitcast i16* %p_arrayidx to <4 x i16>*
+  %_p_vec_full = load <4 x i16>, <4 x i16>* %vector_ptr, align 8
+  %mulp_vec = mul <4 x i16> %_p_vec_full, <i16 7, i16 7, i16 7, i16 7>
+  %vector_ptr15 = bitcast i16* %p_arrayidx1 to <4 x i16>*
+  %_p_vec_full16 = load <4 x i16>, <4 x i16>* %vector_ptr15, align 8
+  %addp_vec = add <4 x i16> %_p_vec_full16, %mulp_vec
+  store <4 x i16> %addp_vec, <4 x i16>* %vector_ptr15, align 8
+  %0 = icmp slt i32 %polly.next_loopiv, 400
+  br i1 %0, label %polly.loop_body, label %polly.loop_after
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-vsubb-1.ll b/test/CodeGen/Hexagon/vect/vect-vsubb-1.ll
new file mode 100644
index 000000000000..8ac76a0bf13c
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-vsubb-1.ll
@@ -0,0 +1,8 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: vsubub
+
+define <4 x i8> @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind {
+entry:
+	%0 = sub <4 x i8> %a, %b
+	ret <4 x i8> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-vsubb.ll b/test/CodeGen/Hexagon/vect/vect-vsubb.ll
new file mode 100644
index 000000000000..73cfc74074ad
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-vsubb.ll
@@ -0,0 +1,8 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: vsubub
+
+define <8 x i8> @t_i8x8(<8 x i8> %a, <8 x i8> %b) nounwind {
+entry:
+	%0 = sub <8 x i8> %a, %b
+	ret <8 x i8> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-vsubh-1.ll b/test/CodeGen/Hexagon/vect/vect-vsubh-1.ll
new file mode 100644
index 000000000000..c1f87bf090d6
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-vsubh-1.ll
@@ -0,0 +1,8 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: vsubh
+
+define <4 x i16> @t_i4x16(<4 x i16> %a, <4 x i16> %b) nounwind {
+entry:
+	%0 = sub <4 x i16> %a, %b
+	ret <4 x i16> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-vsubh.ll b/test/CodeGen/Hexagon/vect/vect-vsubh.ll
new file mode 100644
index 000000000000..cc7e595644d2
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-vsubh.ll
@@ -0,0 +1,8 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: vsubh
+
+define <2 x i16> @t_i2x16(<2 x i16> %a, <2 x i16> %b) nounwind {
+entry:
+	%0 = sub <2 x i16> %a, %b
+	ret <2 x i16> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-vsubw.ll b/test/CodeGen/Hexagon/vect/vect-vsubw.ll
new file mode 100644
index 000000000000..ba326a33109b
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-vsubw.ll
@@ -0,0 +1,8 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: vsubw
+
+define <2 x i32> @t_i2x32(<2 x i32> %a, <2 x i32> %b) nounwind {
+entry:
+	%0 = sub <2 x i32> %a, %b
+	ret <2 x i32> %0
+}
diff --git a/test/CodeGen/Hexagon/vect/vect-xor.ll b/test/CodeGen/Hexagon/vect/vect-xor.ll
new file mode 100644
index 000000000000..961185581128
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-xor.ll
@@ -0,0 +1,38 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+
+; Check that the parsing succeeded.
+; CHECK: r{{[0-9]+:[0-9]+}} = xor(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+@window_size = global i32 65536, align 4
+@prev = external global [0 x i16], align 8
+@block_start = common global i32 0, align 4
+@prev_length = common global i32 0, align 4
+@strstart = common global i32 0, align 4
+@match_start = common global i32 0, align 4
+@max_chain_length = common global i32 0, align 4
+@good_match = common global i32 0, align 4
+
+define void @fill_window() #0 {
+entry:
+  br label %polly.loop_body
+
+polly.loop_after:                                 ; preds = %polly.loop_body
+  ret void
+
+polly.loop_body:                                  ; preds = %entry, %polly.loop_body
+  %polly.loopiv36 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ]
+  %polly.next_loopiv = add nsw i32 %polly.loopiv36, 4
+  %p_arrayidx4 = getelementptr [0 x i16], [0 x i16]* @prev, i32 0, i32 %polly.loopiv36
+  %vector_ptr = bitcast i16* %p_arrayidx4 to <4 x i16>*
+  %_p_vec_full = load <4 x i16>, <4 x i16>* %vector_ptr, align 2
+  %cmp1p_vicmp = icmp slt <4 x i16> %_p_vec_full, zeroinitializer
+  %subp_vec = xor <4 x i16> %_p_vec_full, <i16 -32768, i16 -32768, i16 -32768, i16 -32768>
+  %sel1p_vsel = select <4 x i1> %cmp1p_vicmp, <4 x i16> %subp_vec, <4 x i16> zeroinitializer
+  store <4 x i16> %sel1p_vsel, <4 x i16>* %vector_ptr, align 2
+  %0 = icmp slt i32 %polly.next_loopiv, 32768
+  br i1 %0, label %polly.loop_body, label %polly.loop_after
+}
+
+attributes #0 = { nounwind "fp-contract-model"="standard" "no-frame-pointer-elim-non-leaf" "realign-stack" "relocation-model"="static" "ssp-buffers-size"="8" }
diff --git a/test/CodeGen/Hexagon/vect/vect-zeroextend.ll b/test/CodeGen/Hexagon/vect/vect-zeroextend.ll
new file mode 100644
index 000000000000..3d0b7946f77a
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-zeroextend.ll
@@ -0,0 +1,23 @@
+; RUN: llc -march=hexagon < %s
+; Used to fail with "Cannot select: 0x16cb2d0: v4i16 = zero_extend"
+
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
+target triple = "hexagon-unknown-linux-gnu"
+
+define void @foo() nounwind {
+entry:
+  br i1 undef, label %for.cond30.preheader.lr.ph, label %for.end425
+
+for.cond30.preheader.lr.ph:                       ; preds = %entry
+  br label %for.cond37.preheader
+
+for.cond37.preheader:                             ; preds = %for.cond37.preheader, %for.cond30.preheader.lr.ph
+  %_p_vec_full = load <3 x i8>, <3 x i8>* undef, align 8
+  %0 = zext <3 x i8> %_p_vec_full to <3 x i16>
+  store <3 x i16> %0, <3 x i16>* undef, align 8
+  br label %for.cond37.preheader
+
+for.end425:                                       ; preds = %entry
+  ret void
+}
diff --git a/test/CodeGen/Hexagon/zextloadi1.ll b/test/CodeGen/Hexagon/zextloadi1.ll
index b58d9332695d..9ce7bea9fce6 100644
--- a/test/CodeGen/Hexagon/zextloadi1.ll
+++ b/test/CodeGen/Hexagon/zextloadi1.ll
@@ -13,13 +13,13 @@
 @i129_s = external global i129
 
 define void @i129_ls() nounwind  {
-        %tmp = load i129* @i129_l
+        %tmp = load i129, i129* @i129_l
         store i129 %tmp, i129* @i129_s
         ret void
 }
 
 define void @i65_ls() nounwind  {
-        %tmp = load i65* @i65_l
+        %tmp = load i65, i65* @i65_l
         store i65 %tmp, i65* @i65_s
         ret void
 }
diff --git a/test/CodeGen/Inputs/DbgValueOtherTargets.ll b/test/CodeGen/Inputs/DbgValueOtherTargets.ll
index d21a4eebe247..efa1a0849a8e 100644
--- a/test/CodeGen/Inputs/DbgValueOtherTargets.ll
+++ b/test/CodeGen/Inputs/DbgValueOtherTargets.ll
@@ -3,7 +3,7 @@
 define i32 @main() nounwind ssp {
 entry:
 ; CHECK: DEBUG_VALUE
-  call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !{!"0x102"}), !dbg !9
+  call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !DIExpression()), !dbg !9
   ret i32 0, !dbg !10
 }
 
@@ -14,17 +14,17 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!13}
 
-!0 = !{!"0x2e\00main\00main\00\002\000\001\000\006\000\000\000", !12, !1, !3, null, i32 ()* @main, null, null, null} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !12} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 2.9 (trunk 120996)\000\00\000\00\000", !12, !6, !6, !11, null, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !12, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "main", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !12, scope: !1, type: !3, function: i32 ()* @main)
+!1 = !DIFile(filename: "/tmp/x.c", directory: "/Users/manav")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 2.9 (trunk 120996)", isOptimized: false, emissionKind: 0, file: !12, enums: !6, retainedTypes: !6, subprograms: !11)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", !12, !2} ; [ DW_TAG_base_type ]
-!6 = !{i32 0}
-!7 = !{!"0x100\00i\003\000", !8, !1, !5} ; [ DW_TAG_auto_variable ]
-!8 = !{!"0xb\002\0012\000", !12, !0} ; [ DW_TAG_lexical_block ]
-!9 = !MDLocation(line: 3, column: 11, scope: !8)
-!10 = !MDLocation(line: 4, column: 2, scope: !8)
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !{}
+!7 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 3, scope: !8, file: !1, type: !5)
+!8 = distinct !DILexicalBlock(line: 2, column: 12, file: !12, scope: !0)
+!9 = !DILocation(line: 3, column: 11, scope: !8)
+!10 = !DILocation(line: 4, column: 2, scope: !8)
 !11 = !{!0}
-!12 = !{!"/tmp/x.c", !"/Users/manav"}
-!13 = !{i32 1, !"Debug Info Version", i32 2}
+!12 = !DIFile(filename: "/tmp/x.c", directory: "/Users/manav")
+!13 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/MSP430/2009-05-10-CyclicDAG.ll b/test/CodeGen/MSP430/2009-05-10-CyclicDAG.ll
index 4c7d2d092564..38e9832f526d 100644
--- a/test/CodeGen/MSP430/2009-05-10-CyclicDAG.ll
+++ b/test/CodeGen/MSP430/2009-05-10-CyclicDAG.ll
@@ -7,7 +7,7 @@ target triple = "msp430-unknown-linux-gnu"
 
 define void @uip_arp_arpin() nounwind {
 entry:
-	%tmp = load volatile i16* @uip_len		; <i16> [#uses=1]
+	%tmp = load volatile i16, i16* @uip_len		; <i16> [#uses=1]
 	%cmp = icmp ult i16 %tmp, 42		; <i1> [#uses=1]
 	store volatile i16 0, i16* @uip_len
 	br i1 %cmp, label %if.then, label %if.end
diff --git a/test/CodeGen/MSP430/2009-05-17-Rot.ll b/test/CodeGen/MSP430/2009-05-17-Rot.ll
index d622aa71164b..30b373990a75 100644
--- a/test/CodeGen/MSP430/2009-05-17-Rot.ll
+++ b/test/CodeGen/MSP430/2009-05-17-Rot.ll
@@ -4,14 +4,14 @@ define i16 @rol1u16(i16 %x.arg) nounwind {
         %retval = alloca i16
         %x = alloca i16
         store i16 %x.arg, i16* %x
-        %1 = load i16* %x
+        %1 = load i16, i16* %x
         %2 = shl i16 %1, 1
-        %3 = load i16* %x
+        %3 = load i16, i16* %x
         %4 = lshr i16 %3, 15
         %5 = or i16 %2, %4
         store i16 %5, i16* %retval
         br label %return
 return:
-        %6 = load i16* %retval
+        %6 = load i16, i16* %retval
         ret i16 %6
 }
diff --git a/test/CodeGen/MSP430/2009-05-17-Shift.ll b/test/CodeGen/MSP430/2009-05-17-Shift.ll
index e23df7851666..2e3dd5593ff0 100644
--- a/test/CodeGen/MSP430/2009-05-17-Shift.ll
+++ b/test/CodeGen/MSP430/2009-05-17-Shift.ll
@@ -4,12 +4,12 @@ define i16 @lsr2u16(i16 %x.arg) nounwind {
         %retval = alloca i16
         %x = alloca i16
         store i16 %x.arg, i16* %x
-        %1 = load i16* %x
+        %1 = load i16, i16* %x
         %2 = lshr i16 %1, 2
         store i16 %2, i16* %retval
         br label %return
 return:
-        %3 = load i16* %retval
+        %3 = load i16, i16* %retval
         ret i16 %3
 
 }
diff --git a/test/CodeGen/MSP430/2009-08-25-DynamicStackAlloc.ll b/test/CodeGen/MSP430/2009-08-25-DynamicStackAlloc.ll
index e8c0d14afd21..ca54ff0c3b48 100644
--- a/test/CodeGen/MSP430/2009-08-25-DynamicStackAlloc.ll
+++ b/test/CodeGen/MSP430/2009-08-25-DynamicStackAlloc.ll
@@ -7,7 +7,7 @@ define i16 @foo() nounwind readnone {
 entry:
   %result = alloca i16, align 1                   ; <i16*> [#uses=2]
   store volatile i16 0, i16* %result
-  %tmp = load volatile i16* %result               ; <i16> [#uses=1]
+  %tmp = load volatile i16, i16* %result               ; <i16> [#uses=1]
   ret i16 %tmp
 }
 
@@ -23,7 +23,7 @@ while.cond:                                       ; preds = %while.cond, %entry
 while.end:                                        ; preds = %while.cond
   %result.i = alloca i16, align 1                 ; <i16*> [#uses=2]
   store volatile i16 0, i16* %result.i
-  %tmp.i = load volatile i16* %result.i           ; <i16> [#uses=0]
+  %tmp.i = load volatile i16, i16* %result.i           ; <i16> [#uses=0]
   ret i16 0
 }
 
diff --git a/test/CodeGen/MSP430/2009-09-18-AbsoluteAddr.ll b/test/CodeGen/MSP430/2009-09-18-AbsoluteAddr.ll
index 9fab4826e085..72ba335b54e1 100644
--- a/test/CodeGen/MSP430/2009-09-18-AbsoluteAddr.ll
+++ b/test/CodeGen/MSP430/2009-09-18-AbsoluteAddr.ll
@@ -11,12 +11,12 @@ entry:
   %x.addr = alloca i8                             ; <i8*> [#uses=2]
   %tmp = alloca i8, align 1                       ; <i8*> [#uses=2]
   store i8 %x, i8* %x.addr
-  %tmp1 = load volatile i8* @"\010x0021"          ; <i8> [#uses=1]
+  %tmp1 = load volatile i8, i8* @"\010x0021"          ; <i8> [#uses=1]
   store i8 %tmp1, i8* %tmp
-  %tmp2 = load i8* %x.addr                        ; <i8> [#uses=1]
+  %tmp2 = load i8, i8* %x.addr                        ; <i8> [#uses=1]
   store volatile i8 %tmp2, i8* @"\010x0021"
-  %tmp3 = load i8* %tmp                           ; <i8> [#uses=1]
+  %tmp3 = load i8, i8* %tmp                           ; <i8> [#uses=1]
   store i8 %tmp3, i8* %retval
-  %0 = load i8* %retval                           ; <i8> [#uses=1]
+  %0 = load i8, i8* %retval                           ; <i8> [#uses=1]
   ret i8 %0
 }
diff --git a/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll b/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll
index c1a186a637cf..6dfbbfc03e90 100644
--- a/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll
+++ b/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll
@@ -4,7 +4,7 @@ define void @foo() nounwind {
 entry:
 	%r = alloca i8		; <i8*> [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
-	load volatile i8* %r, align 1		; <i8>:0 [#uses=1]
+	load volatile i8, i8* %r, align 1		; <i8>:0 [#uses=1]
 	or i8 %0, 1		; <i8>:1 [#uses=1]
 	store volatile i8 %1, i8* %r, align 1
 	br label %return
diff --git a/test/CodeGen/MSP430/2009-11-08-InvalidResNo.ll b/test/CodeGen/MSP430/2009-11-08-InvalidResNo.ll
index d232aeae5b51..04b087e95363 100644
--- a/test/CodeGen/MSP430/2009-11-08-InvalidResNo.ll
+++ b/test/CodeGen/MSP430/2009-11-08-InvalidResNo.ll
@@ -46,9 +46,9 @@ while.cond36.i:                                   ; preds = %while.body41.i, %wh
   br i1 undef, label %do.body, label %while.body41.i
 
 while.body41.i:                                   ; preds = %while.cond36.i
-  %tmp43.i = load i8** @foo                      ; <i8*> [#uses=2]
-  %tmp44.i = load i8* %tmp43.i                    ; <i8> [#uses=1]
-  %ptrincdec50.i = getelementptr inbounds i8* %tmp43.i, i16 1 ; <i8*> [#uses=1]
+  %tmp43.i = load i8*, i8** @foo                      ; <i8*> [#uses=2]
+  %tmp44.i = load i8, i8* %tmp43.i                    ; <i8> [#uses=1]
+  %ptrincdec50.i = getelementptr inbounds i8, i8* %tmp43.i, i16 1 ; <i8*> [#uses=1]
   store i8* %ptrincdec50.i, i8** @foo
   %cmp55.i = icmp eq i8 %tmp44.i, %c              ; <i1> [#uses=1]
   br i1 %cmp55.i, label %do.end41, label %while.cond36.i
diff --git a/test/CodeGen/MSP430/2009-12-22-InlineAsm.ll b/test/CodeGen/MSP430/2009-12-22-InlineAsm.ll
index a9df1a3e9743..fa9d0c8e46cb 100644
--- a/test/CodeGen/MSP430/2009-12-22-InlineAsm.ll
+++ b/test/CodeGen/MSP430/2009-12-22-InlineAsm.ll
@@ -8,8 +8,8 @@ target triple = "msp430-unknown-unknown"
 
 define i16 @main() noreturn nounwind {
 entry:
-  %0 = tail call i8* asm "", "=r,0"(i8* getelementptr inbounds ([10 x i8]* @buf, i16 0, i16 0)) nounwind ; <i8*> [#uses=1]
-  %sub.ptr = getelementptr inbounds i8* %0, i16 1 ; <i8*> [#uses=1]
+  %0 = tail call i8* asm "", "=r,0"(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @buf, i16 0, i16 0)) nounwind ; <i8*> [#uses=1]
+  %sub.ptr = getelementptr inbounds i8, i8* %0, i16 1 ; <i8*> [#uses=1]
   %sub.ptr.lhs.cast = ptrtoint i8* %sub.ptr to i16 ; <i16> [#uses=1]
   %sub.ptr.sub = sub i16 %sub.ptr.lhs.cast, ptrtoint ([10 x i8]* @buf to i16) ; <i16> [#uses=1]
   %cmp = icmp eq i16 %sub.ptr.sub, 1              ; <i1> [#uses=1]
diff --git a/test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll b/test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll
index 99100377034b..907d6abe9921 100644
--- a/test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll
+++ b/test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll
@@ -19,7 +19,7 @@ land.end:                                         ; preds = %land.rhs, %while.co
   br i1 %0, label %while.body, label %while.end
 
 while.body:                                       ; preds = %land.end
-  %tmp4 = load i16* undef                         ; <i16> [#uses=0]
+  %tmp4 = load i16, i16* undef                         ; <i16> [#uses=0]
   br label %while.cond
 
 while.end:                                        ; preds = %land.end
diff --git a/test/CodeGen/MSP430/AddrMode-bis-rx.ll b/test/CodeGen/MSP430/AddrMode-bis-rx.ll
index 44c92ebc82cc..941ee2dc2ce9 100644
--- a/test/CodeGen/MSP430/AddrMode-bis-rx.ll
+++ b/test/CodeGen/MSP430/AddrMode-bis-rx.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
 target triple = "msp430-generic-generic"
 
 define i16 @am1(i16 %x, i16* %a) nounwind {
-	%1 = load i16* %a
+	%1 = load i16, i16* %a
 	%2 = or i16 %1,%x
 	ret i16 %2
 }
@@ -13,7 +13,7 @@ define i16 @am1(i16 %x, i16* %a) nounwind {
 @foo = external global i16
 
 define i16 @am2(i16 %x) nounwind {
-	%1 = load i16* @foo
+	%1 = load i16, i16* @foo
 	%2 = or i16 %1,%x
 	ret i16 %2
 }
@@ -23,8 +23,8 @@ define i16 @am2(i16 %x) nounwind {
 @bar = internal constant [2 x i8] [ i8 32, i8 64 ]
 
 define i8 @am3(i8 %x, i16 %n) nounwind {
-	%1 = getelementptr [2 x i8]* @bar, i16 0, i16 %n
-	%2 = load i8* %1
+	%1 = getelementptr [2 x i8], [2 x i8]* @bar, i16 0, i16 %n
+	%2 = load i8, i8* %1
 	%3 = or i8 %2,%x
 	ret i8 %3
 }
@@ -32,7 +32,7 @@ define i8 @am3(i8 %x, i16 %n) nounwind {
 ; CHECK:		bis.b	bar(r14), r15
 
 define i16 @am4(i16 %x) nounwind {
-	%1 = load volatile i16* inttoptr(i16 32 to i16*)
+	%1 = load volatile i16, i16* inttoptr(i16 32 to i16*)
 	%2 = or i16 %1,%x
 	ret i16 %2
 }
@@ -40,8 +40,8 @@ define i16 @am4(i16 %x) nounwind {
 ; CHECK:		bis.w	&32, r15
 
 define i16 @am5(i16 %x, i16* %a) nounwind {
-	%1 = getelementptr i16* %a, i16 2
-	%2 = load i16* %1
+	%1 = getelementptr i16, i16* %a, i16 2
+	%2 = load i16, i16* %1
 	%3 = or i16 %2,%x
 	ret i16 %3
 }
@@ -52,7 +52,7 @@ define i16 @am5(i16 %x, i16* %a) nounwind {
 @baz = common global %S zeroinitializer, align 1
 
 define i16 @am6(i16 %x) nounwind {
-	%1 = load i16* getelementptr (%S* @baz, i32 0, i32 1)
+	%1 = load i16, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
 	%2 = or i16 %1,%x
 	ret i16 %2
 }
@@ -63,9 +63,9 @@ define i16 @am6(i16 %x) nounwind {
 @duh = internal constant %T { i16 16, [2 x i8][i8 32, i8 64 ] }
 
 define i8 @am7(i8 %x, i16 %n) nounwind {
-	%1 = getelementptr %T* @duh, i32 0, i32 1
-	%2 = getelementptr [2 x i8]* %1, i16 0, i16 %n
-	%3= load i8* %2
+	%1 = getelementptr %T, %T* @duh, i32 0, i32 1
+	%2 = getelementptr [2 x i8], [2 x i8]* %1, i16 0, i16 %n
+	%3= load i8, i8* %2
 	%4 = or i8 %3,%x
 	ret i8 %4
 }
diff --git a/test/CodeGen/MSP430/AddrMode-bis-xr.ll b/test/CodeGen/MSP430/AddrMode-bis-xr.ll
index 06a3d32d8aa4..4b8f367a8880 100644
--- a/test/CodeGen/MSP430/AddrMode-bis-xr.ll
+++ b/test/CodeGen/MSP430/AddrMode-bis-xr.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:16"
 target triple = "msp430-generic-generic"
 
 define void @am1(i16* %a, i16 %x) nounwind {
-	%1 = load i16* %a
+	%1 = load i16, i16* %a
 	%2 = or i16 %x, %1
 	store i16 %2, i16* %a
 	ret void
@@ -14,7 +14,7 @@ define void @am1(i16* %a, i16 %x) nounwind {
 @foo = external global i16
 
 define void @am2(i16 %x) nounwind {
-	%1 = load i16* @foo
+	%1 = load i16, i16* @foo
 	%2 = or i16 %x, %1
 	store i16 %2, i16* @foo
 	ret void
@@ -25,8 +25,8 @@ define void @am2(i16 %x) nounwind {
 @bar = external global [2 x i8]
 
 define void @am3(i16 %i, i8 %x) nounwind {
-	%1 = getelementptr [2 x i8]* @bar, i16 0, i16 %i
-	%2 = load i8* %1
+	%1 = getelementptr [2 x i8], [2 x i8]* @bar, i16 0, i16 %i
+	%2 = load i8, i8* %1
 	%3 = or i8 %x, %2
 	store i8 %3, i8* %1
 	ret void
@@ -35,7 +35,7 @@ define void @am3(i16 %i, i8 %x) nounwind {
 ; CHECK:		bis.b	r14, bar(r15)
 
 define void @am4(i16 %x) nounwind {
-	%1 = load volatile i16* inttoptr(i16 32 to i16*)
+	%1 = load volatile i16, i16* inttoptr(i16 32 to i16*)
 	%2 = or i16 %x, %1
 	store volatile i16 %2, i16* inttoptr(i16 32 to i16*)
 	ret void
@@ -44,8 +44,8 @@ define void @am4(i16 %x) nounwind {
 ; CHECK:		bis.w	r15, &32
 
 define void @am5(i16* %a, i16 %x) readonly {
-	%1 = getelementptr inbounds i16* %a, i16 2
-	%2 = load i16* %1
+	%1 = getelementptr inbounds i16, i16* %a, i16 2
+	%2 = load i16, i16* %1
 	%3 = or i16 %x, %2
 	store i16 %3, i16* %1
 	ret void
@@ -57,9 +57,9 @@ define void @am5(i16* %a, i16 %x) readonly {
 @baz = common global %S zeroinitializer
 
 define void @am6(i16 %x) nounwind {
-	%1 = load i16* getelementptr (%S* @baz, i32 0, i32 1)
+	%1 = load i16, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
 	%2 = or i16 %x, %1
-	store i16 %2, i16* getelementptr (%S* @baz, i32 0, i32 1)
+	store i16 %2, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
 	ret void
 }
 ; CHECK-LABEL: am6:
@@ -69,9 +69,9 @@ define void @am6(i16 %x) nounwind {
 @duh = external global %T
 
 define void @am7(i16 %n, i8 %x) nounwind {
-	%1 = getelementptr %T* @duh, i32 0, i32 1
-	%2 = getelementptr [2 x i8]* %1, i16 0, i16 %n
-	%3 = load i8* %2
+	%1 = getelementptr %T, %T* @duh, i32 0, i32 1
+	%2 = getelementptr [2 x i8], [2 x i8]* %1, i16 0, i16 %n
+	%3 = load i8, i8* %2
 	%4 = or i8 %x, %3
 	store i8 %4, i8* %2
 	ret void
diff --git a/test/CodeGen/MSP430/AddrMode-mov-rx.ll b/test/CodeGen/MSP430/AddrMode-mov-rx.ll
index 378b7ae58ff6..cdee931bf96d 100644
--- a/test/CodeGen/MSP430/AddrMode-mov-rx.ll
+++ b/test/CodeGen/MSP430/AddrMode-mov-rx.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
 target triple = "msp430-generic-generic"
 
 define i16 @am1(i16* %a) nounwind {
-	%1 = load i16* %a
+	%1 = load i16, i16* %a
 	ret i16 %1
 }
 ; CHECK-LABEL: am1:
@@ -12,7 +12,7 @@ define i16 @am1(i16* %a) nounwind {
 @foo = external global i16
 
 define i16 @am2() nounwind {
-	%1 = load i16* @foo
+	%1 = load i16, i16* @foo
 	ret i16 %1
 }
 ; CHECK-LABEL: am2:
@@ -21,23 +21,23 @@ define i16 @am2() nounwind {
 @bar = internal constant [2 x i8] [ i8 32, i8 64 ]
 
 define i8 @am3(i16 %n) nounwind {
-	%1 = getelementptr [2 x i8]* @bar, i16 0, i16 %n
-	%2 = load i8* %1
+	%1 = getelementptr [2 x i8], [2 x i8]* @bar, i16 0, i16 %n
+	%2 = load i8, i8* %1
 	ret i8 %2
 }
 ; CHECK-LABEL: am3:
 ; CHECK:		mov.b	bar(r15), r15
 
 define i16 @am4() nounwind {
-	%1 = load volatile i16* inttoptr(i16 32 to i16*)
+	%1 = load volatile i16, i16* inttoptr(i16 32 to i16*)
 	ret i16 %1
 }
 ; CHECK-LABEL: am4:
 ; CHECK:		mov.w	&32, r15
 
 define i16 @am5(i16* %a) nounwind {
-	%1 = getelementptr i16* %a, i16 2
-	%2 = load i16* %1
+	%1 = getelementptr i16, i16* %a, i16 2
+	%2 = load i16, i16* %1
 	ret i16 %2
 }
 ; CHECK-LABEL: am5:
@@ -47,7 +47,7 @@ define i16 @am5(i16* %a) nounwind {
 @baz = common global %S zeroinitializer, align 1
 
 define i16 @am6() nounwind {
-	%1 = load i16* getelementptr (%S* @baz, i32 0, i32 1)
+	%1 = load i16, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
 	ret i16 %1
 }
 ; CHECK-LABEL: am6:
@@ -57,9 +57,9 @@ define i16 @am6() nounwind {
 @duh = internal constant %T { i16 16, [2 x i8][i8 32, i8 64 ] }
 
 define i8 @am7(i16 %n) nounwind {
-	%1 = getelementptr %T* @duh, i32 0, i32 1
-	%2 = getelementptr [2 x i8]* %1, i16 0, i16 %n
-	%3= load i8* %2
+	%1 = getelementptr %T, %T* @duh, i32 0, i32 1
+	%2 = getelementptr [2 x i8], [2 x i8]* %1, i16 0, i16 %n
+	%3= load i8, i8* %2
 	ret i8 %3
 }
 ; CHECK-LABEL: am7:
diff --git a/test/CodeGen/MSP430/AddrMode-mov-xr.ll b/test/CodeGen/MSP430/AddrMode-mov-xr.ll
index f55fd542645c..ccb42886e9b4 100644
--- a/test/CodeGen/MSP430/AddrMode-mov-xr.ll
+++ b/test/CodeGen/MSP430/AddrMode-mov-xr.ll
@@ -21,7 +21,7 @@ define void @am2(i16 %a) nounwind {
 @bar = external global [2 x i8]
 
 define void @am3(i16 %i, i8 %a) nounwind {
-	%1 = getelementptr [2 x i8]* @bar, i16 0, i16 %i
+	%1 = getelementptr [2 x i8], [2 x i8]* @bar, i16 0, i16 %i
 	store i8 %a, i8* %1
 	ret void
 }
@@ -36,7 +36,7 @@ define void @am4(i16 %a) nounwind {
 ; CHECK:		mov.w	r15, &32
 
 define void @am5(i16* nocapture %p, i16 %a) nounwind readonly {
-	%1 = getelementptr inbounds i16* %p, i16 2
+	%1 = getelementptr inbounds i16, i16* %p, i16 2
 	store i16 %a, i16* %1
 	ret void
 }
@@ -47,7 +47,7 @@ define void @am5(i16* nocapture %p, i16 %a) nounwind readonly {
 @baz = common global %S zeroinitializer, align 1
 
 define void @am6(i16 %a) nounwind {
-	store i16 %a, i16* getelementptr (%S* @baz, i32 0, i32 1)
+	store i16 %a, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
 	ret void
 }
 ; CHECK-LABEL: am6:
@@ -57,8 +57,8 @@ define void @am6(i16 %a) nounwind {
 @duh = external global %T
 
 define void @am7(i16 %n, i8 %a) nounwind {
-	%1 = getelementptr %T* @duh, i32 0, i32 1
-	%2 = getelementptr [2 x i8]* %1, i16 0, i16 %n
+	%1 = getelementptr %T, %T* @duh, i32 0, i32 1
+	%2 = getelementptr [2 x i8], [2 x i8]* %1, i16 0, i16 %n
 	store i8 %a, i8* %2
 	ret void
 }
diff --git a/test/CodeGen/MSP430/Inst16mi.ll b/test/CodeGen/MSP430/Inst16mi.ll
index e9ab75cc80bc..38c16f2ba235 100644
--- a/test/CodeGen/MSP430/Inst16mi.ll
+++ b/test/CodeGen/MSP430/Inst16mi.ll
@@ -14,7 +14,7 @@ define void @mov() nounwind {
 define void @add() nounwind {
 ; CHECK-LABEL: add:
 ; CHECK: add.w	#2, &foo
-	%1 = load i16* @foo
+	%1 = load i16, i16* @foo
 	%2 = add i16 %1, 2
 	store i16 %2, i16 * @foo
 	ret void
@@ -23,7 +23,7 @@ define void @add() nounwind {
 define void @and() nounwind {
 ; CHECK-LABEL: and:
 ; CHECK: and.w	#2, &foo
-	%1 = load i16* @foo
+	%1 = load i16, i16* @foo
 	%2 = and i16 %1, 2
 	store i16 %2, i16 * @foo
 	ret void
@@ -32,7 +32,7 @@ define void @and() nounwind {
 define void @bis() nounwind {
 ; CHECK-LABEL: bis:
 ; CHECK: bis.w	#2, &foo
-	%1 = load i16* @foo
+	%1 = load i16, i16* @foo
 	%2 = or i16 %1, 2
 	store i16 %2, i16 * @foo
 	ret void
@@ -41,7 +41,7 @@ define void @bis() nounwind {
 define void @xor() nounwind {
 ; CHECK-LABEL: xor:
 ; CHECK: xor.w	#2, &foo
-	%1 = load i16* @foo
+	%1 = load i16, i16* @foo
 	%2 = xor i16 %1, 2
 	store i16 %2, i16 * @foo
 	ret void
diff --git a/test/CodeGen/MSP430/Inst16mm.ll b/test/CodeGen/MSP430/Inst16mm.ll
index 5c93e37bfa96..c75e1beb2356 100644
--- a/test/CodeGen/MSP430/Inst16mm.ll
+++ b/test/CodeGen/MSP430/Inst16mm.ll
@@ -7,7 +7,7 @@ target triple = "msp430-generic-generic"
 define void @mov() nounwind {
 ; CHECK-LABEL: mov:
 ; CHECK: mov.w	&bar, &foo
-        %1 = load i16* @bar
+        %1 = load i16, i16* @bar
         store i16 %1, i16* @foo
         ret void
 }
@@ -15,8 +15,8 @@ define void @mov() nounwind {
 define void @add() nounwind {
 ; CHECK-LABEL: add:
 ; CHECK: add.w	&bar, &foo
-	%1 = load i16* @bar
-	%2 = load i16* @foo
+	%1 = load i16, i16* @bar
+	%2 = load i16, i16* @foo
 	%3 = add i16 %2, %1
 	store i16 %3, i16* @foo
 	ret void
@@ -25,8 +25,8 @@ define void @add() nounwind {
 define void @and() nounwind {
 ; CHECK-LABEL: and:
 ; CHECK: and.w	&bar, &foo
-	%1 = load i16* @bar
-	%2 = load i16* @foo
+	%1 = load i16, i16* @bar
+	%2 = load i16, i16* @foo
 	%3 = and i16 %2, %1
 	store i16 %3, i16* @foo
 	ret void
@@ -35,8 +35,8 @@ define void @and() nounwind {
 define void @bis() nounwind {
 ; CHECK-LABEL: bis:
 ; CHECK: bis.w	&bar, &foo
-	%1 = load i16* @bar
-	%2 = load i16* @foo
+	%1 = load i16, i16* @bar
+	%2 = load i16, i16* @foo
 	%3 = or i16 %2, %1
 	store i16 %3, i16* @foo
 	ret void
@@ -45,8 +45,8 @@ define void @bis() nounwind {
 define void @xor() nounwind {
 ; CHECK-LABEL: xor:
 ; CHECK: xor.w	&bar, &foo
-	%1 = load i16* @bar
-	%2 = load i16* @foo
+	%1 = load i16, i16* @bar
+	%2 = load i16, i16* @foo
 	%3 = xor i16 %2, %1
 	store i16 %3, i16* @foo
 	ret void
@@ -58,10 +58,10 @@ entry:
  %x = alloca i32, align 2                        ; <i32*> [#uses=1]
  %y = alloca i32, align 2                        ; <i32*> [#uses=1]
  store i16 0, i16* %retval
- %tmp = load i32* %y                             ; <i32> [#uses=1]
+ %tmp = load i32, i32* %y                             ; <i32> [#uses=1]
  store i32 %tmp, i32* %x
  store i16 0, i16* %retval
- %0 = load i16* %retval                          ; <i16> [#uses=1]
+ %0 = load i16, i16* %retval                          ; <i16> [#uses=1]
  ret i16 %0
 ; CHECK-LABEL: mov2:
 ; CHECK:	mov.w	2(r1), 6(r1)
diff --git a/test/CodeGen/MSP430/Inst16mr.ll b/test/CodeGen/MSP430/Inst16mr.ll
index 201004893684..50dc4c0b6731 100644
--- a/test/CodeGen/MSP430/Inst16mr.ll
+++ b/test/CodeGen/MSP430/Inst16mr.ll
@@ -13,7 +13,7 @@ define void @mov(i16 %a) nounwind {
 define void @add(i16 %a) nounwind {
 ; CHECK-LABEL: add:
 ; CHECK: add.w	r15, &foo
-	%1 = load i16* @foo
+	%1 = load i16, i16* @foo
 	%2 = add i16 %a, %1
 	store i16 %2, i16* @foo
 	ret void
@@ -22,7 +22,7 @@ define void @add(i16 %a) nounwind {
 define void @and(i16 %a) nounwind {
 ; CHECK-LABEL: and:
 ; CHECK: and.w	r15, &foo
-	%1 = load i16* @foo
+	%1 = load i16, i16* @foo
 	%2 = and i16 %a, %1
 	store i16 %2, i16* @foo
 	ret void
@@ -31,7 +31,7 @@ define void @and(i16 %a) nounwind {
 define void @bis(i16 %a) nounwind {
 ; CHECK-LABEL: bis:
 ; CHECK: bis.w	r15, &foo
-	%1 = load i16* @foo
+	%1 = load i16, i16* @foo
 	%2 = or i16 %a, %1
 	store i16 %2, i16* @foo
 	ret void
@@ -41,7 +41,7 @@ define void @bic(i16 zeroext %m) nounwind {
 ; CHECK-LABEL: bic:
 ; CHECK: bic.w   r15, &foo
         %1 = xor i16 %m, -1
-        %2 = load i16* @foo
+        %2 = load i16, i16* @foo
         %3 = and i16 %2, %1
         store i16 %3, i16* @foo
         ret void
@@ -50,7 +50,7 @@ define void @bic(i16 zeroext %m) nounwind {
 define void @xor(i16 %a) nounwind {
 ; CHECK-LABEL: xor:
 ; CHECK: xor.w	r15, &foo
-	%1 = load i16* @foo
+	%1 = load i16, i16* @foo
 	%2 = xor i16 %a, %1
 	store i16 %2, i16* @foo
 	ret void
diff --git a/test/CodeGen/MSP430/Inst16rm.ll b/test/CodeGen/MSP430/Inst16rm.ll
index e6c52616c8f6..4f6998ee68df 100644
--- a/test/CodeGen/MSP430/Inst16rm.ll
+++ b/test/CodeGen/MSP430/Inst16rm.ll
@@ -6,7 +6,7 @@ target triple = "msp430-generic-generic"
 define i16 @add(i16 %a) nounwind {
 ; CHECK-LABEL: add:
 ; CHECK: add.w	&foo, r15
-	%1 = load i16* @foo
+	%1 = load i16, i16* @foo
 	%2 = add i16 %a, %1
 	ret i16 %2
 }
@@ -14,7 +14,7 @@ define i16 @add(i16 %a) nounwind {
 define i16 @and(i16 %a) nounwind {
 ; CHECK-LABEL: and:
 ; CHECK: and.w	&foo, r15
-	%1 = load i16* @foo
+	%1 = load i16, i16* @foo
 	%2 = and i16 %a, %1
 	ret i16 %2
 }
@@ -22,7 +22,7 @@ define i16 @and(i16 %a) nounwind {
 define i16 @bis(i16 %a) nounwind {
 ; CHECK-LABEL: bis:
 ; CHECK: bis.w	&foo, r15
-	%1 = load i16* @foo
+	%1 = load i16, i16* @foo
 	%2 = or i16 %a, %1
 	ret i16 %2
 }
@@ -30,7 +30,7 @@ define i16 @bis(i16 %a) nounwind {
 define i16  @bic(i16 %a) nounwind {
 ; CHECK-LABEL: bic:
 ; CHECK: bic.w	&foo, r15
-        %1 = load i16* @foo
+        %1 = load i16, i16* @foo
         %2 = xor i16 %1, -1
         %3 = and i16 %a, %2
         ret i16 %3
@@ -39,7 +39,7 @@ define i16  @bic(i16 %a) nounwind {
 define i16 @xor(i16 %a) nounwind {
 ; CHECK-LABEL: xor:
 ; CHECK: xor.w	&foo, r15
-	%1 = load i16* @foo
+	%1 = load i16, i16* @foo
 	%2 = xor i16 %a, %1
 	ret i16 %2
 }
diff --git a/test/CodeGen/MSP430/Inst8mi.ll b/test/CodeGen/MSP430/Inst8mi.ll
index a2c7b71d66dc..ff22d7e1eb3d 100644
--- a/test/CodeGen/MSP430/Inst8mi.ll
+++ b/test/CodeGen/MSP430/Inst8mi.ll
@@ -13,7 +13,7 @@ define void @mov() nounwind {
 define void @add() nounwind {
 ; CHECK-LABEL: add:
 ; CHECK: add.b	#2, &foo
-	%1 = load i8* @foo
+	%1 = load i8, i8* @foo
 	%2 = add i8 %1, 2
 	store i8 %2, i8 * @foo
 	ret void
@@ -22,7 +22,7 @@ define void @add() nounwind {
 define void @and() nounwind {
 ; CHECK-LABEL: and:
 ; CHECK: and.b	#2, &foo
-	%1 = load i8* @foo
+	%1 = load i8, i8* @foo
 	%2 = and i8 %1, 2
 	store i8 %2, i8 * @foo
 	ret void
@@ -31,7 +31,7 @@ define void @and() nounwind {
 define void @bis() nounwind {
 ; CHECK-LABEL: bis:
 ; CHECK: bis.b	#2, &foo
-	%1 = load i8* @foo
+	%1 = load i8, i8* @foo
 	%2 = or i8 %1, 2
 	store i8 %2, i8 * @foo
 	ret void
@@ -40,7 +40,7 @@ define void @bis() nounwind {
 define void @xor() nounwind {
 ; CHECK-LABEL: xor:
 ; CHECK: xor.b	#2, &foo
-	%1 = load i8* @foo
+	%1 = load i8, i8* @foo
 	%2 = xor i8 %1, 2
 	store i8 %2, i8 * @foo
 	ret void
diff --git a/test/CodeGen/MSP430/Inst8mm.ll b/test/CodeGen/MSP430/Inst8mm.ll
index d1ce8bc66b93..b9848dc12303 100644
--- a/test/CodeGen/MSP430/Inst8mm.ll
+++ b/test/CodeGen/MSP430/Inst8mm.ll
@@ -8,7 +8,7 @@ target triple = "msp430-generic-generic"
 define void @mov() nounwind {
 ; CHECK-LABEL: mov:
 ; CHECK: mov.b	&bar, &foo
-        %1 = load i8* @bar
+        %1 = load i8, i8* @bar
         store i8 %1, i8* @foo
         ret void
 }
@@ -16,8 +16,8 @@ define void @mov() nounwind {
 define void @add() nounwind {
 ; CHECK-LABEL: add:
 ; CHECK: add.b	&bar, &foo
-	%1 = load i8* @bar
-	%2 = load i8* @foo
+	%1 = load i8, i8* @bar
+	%2 = load i8, i8* @foo
 	%3 = add i8 %2, %1
 	store i8 %3, i8* @foo
 	ret void
@@ -26,8 +26,8 @@ define void @add() nounwind {
 define void @and() nounwind {
 ; CHECK-LABEL: and:
 ; CHECK: and.b	&bar, &foo
-	%1 = load i8* @bar
-	%2 = load i8* @foo
+	%1 = load i8, i8* @bar
+	%2 = load i8, i8* @foo
 	%3 = and i8 %2, %1
 	store i8 %3, i8* @foo
 	ret void
@@ -36,8 +36,8 @@ define void @and() nounwind {
 define void @bis() nounwind {
 ; CHECK-LABEL: bis:
 ; CHECK: bis.b	&bar, &foo
-	%1 = load i8* @bar
-	%2 = load i8* @foo
+	%1 = load i8, i8* @bar
+	%2 = load i8, i8* @foo
 	%3 = or i8 %2, %1
 	store i8 %3, i8* @foo
 	ret void
@@ -46,8 +46,8 @@ define void @bis() nounwind {
 define void @xor() nounwind {
 ; CHECK-LABEL: xor:
 ; CHECK: xor.b	&bar, &foo
-	%1 = load i8* @bar
-	%2 = load i8* @foo
+	%1 = load i8, i8* @bar
+	%2 = load i8, i8* @foo
 	%3 = xor i8 %2, %1
 	store i8 %3, i8* @foo
 	ret void
diff --git a/test/CodeGen/MSP430/Inst8mr.ll b/test/CodeGen/MSP430/Inst8mr.ll
index 0b3566770cf0..f03c7e1a659b 100644
--- a/test/CodeGen/MSP430/Inst8mr.ll
+++ b/test/CodeGen/MSP430/Inst8mr.ll
@@ -13,7 +13,7 @@ define void @mov(i8 %a) nounwind {
 define void @and(i8 %a) nounwind {
 ; CHECK-LABEL: and:
 ; CHECK: and.b	r15, &foo
-	%1 = load i8* @foo
+	%1 = load i8, i8* @foo
 	%2 = and i8 %a, %1
 	store i8 %2, i8* @foo
 	ret void
@@ -22,7 +22,7 @@ define void @and(i8 %a) nounwind {
 define void @add(i8 %a) nounwind {
 ; CHECK-LABEL: add:
 ; CHECK: add.b	r15, &foo
-	%1 = load i8* @foo
+	%1 = load i8, i8* @foo
 	%2 = add i8 %a, %1
 	store i8 %2, i8* @foo
 	ret void
@@ -31,7 +31,7 @@ define void @add(i8 %a) nounwind {
 define void @bis(i8 %a) nounwind {
 ; CHECK-LABEL: bis:
 ; CHECK: bis.b	r15, &foo
-	%1 = load i8* @foo
+	%1 = load i8, i8* @foo
 	%2 = or i8 %a, %1
 	store i8 %2, i8* @foo
 	ret void
@@ -41,7 +41,7 @@ define void @bic(i8 zeroext %m) nounwind {
 ; CHECK-LABEL: bic:
 ; CHECK: bic.b   r15, &foo
         %1 = xor i8 %m, -1
-        %2 = load i8* @foo
+        %2 = load i8, i8* @foo
         %3 = and i8 %2, %1
         store i8 %3, i8* @foo
         ret void
@@ -50,7 +50,7 @@ define void @bic(i8 zeroext %m) nounwind {
 define void @xor(i8 %a) nounwind {
 ; CHECK-LABEL: xor:
 ; CHECK: xor.b	r15, &foo
-	%1 = load i8* @foo
+	%1 = load i8, i8* @foo
 	%2 = xor i8 %a, %1
 	store i8 %2, i8* @foo
 	ret void
diff --git a/test/CodeGen/MSP430/Inst8rm.ll b/test/CodeGen/MSP430/Inst8rm.ll
index 308163ed7307..e1a970395578 100644
--- a/test/CodeGen/MSP430/Inst8rm.ll
+++ b/test/CodeGen/MSP430/Inst8rm.ll
@@ -6,7 +6,7 @@ target triple = "msp430-generic-generic"
 define i8 @add(i8 %a) nounwind {
 ; CHECK-LABEL: add:
 ; CHECK: add.b	&foo, r15
-	%1 = load i8* @foo
+	%1 = load i8, i8* @foo
 	%2 = add i8 %a, %1
 	ret i8 %2
 }
@@ -14,7 +14,7 @@ define i8 @add(i8 %a) nounwind {
 define i8 @and(i8 %a) nounwind {
 ; CHECK-LABEL: and:
 ; CHECK: and.b	&foo, r15
-	%1 = load i8* @foo
+	%1 = load i8, i8* @foo
 	%2 = and i8 %a, %1
 	ret i8 %2
 }
@@ -22,7 +22,7 @@ define i8 @and(i8 %a) nounwind {
 define i8 @bis(i8 %a) nounwind {
 ; CHECK-LABEL: bis:
 ; CHECK: bis.b	&foo, r15
-	%1 = load i8* @foo
+	%1 = load i8, i8* @foo
 	%2 = or i8 %a, %1
 	ret i8 %2
 }
@@ -30,7 +30,7 @@ define i8 @bis(i8 %a) nounwind {
 define i8  @bic(i8 %a) nounwind {
 ; CHECK-LABEL: bic:
 ; CHECK: bic.b  &foo, r15
-        %1 = load i8* @foo
+        %1 = load i8, i8* @foo
         %2 = xor i8 %1, -1
         %3 = and i8 %a, %2
         ret i8 %3
@@ -39,7 +39,7 @@ define i8  @bic(i8 %a) nounwind {
 define i8 @xor(i8 %a) nounwind {
 ; CHECK-LABEL: xor:
 ; CHECK: xor.b	&foo, r15
-	%1 = load i8* @foo
+	%1 = load i8, i8* @foo
 	%2 = xor i8 %a, %1
 	ret i8 %2
 }
diff --git a/test/CodeGen/MSP430/bit.ll b/test/CodeGen/MSP430/bit.ll
index 2ffc191695f0..45964f97f1bf 100644
--- a/test/CodeGen/MSP430/bit.ll
+++ b/test/CodeGen/MSP430/bit.ll
@@ -33,7 +33,7 @@ define i8 @bitbir(i8 %a) nounwind {
 ; CHECK: bit.b	#15, r15
 
 define i8 @bitbmi() nounwind {
-	%t1 = load i8* @foo8
+	%t1 = load i8, i8* @foo8
 	%t2 = and i8 %t1, 15
 	%t3 = icmp ne i8 %t2, 0
 	%t4 = zext i1 %t3 to i8
@@ -43,7 +43,7 @@ define i8 @bitbmi() nounwind {
 ; CHECK: bit.b	#15, &foo8
 
 define i8 @bitbim() nounwind {
-	%t1 = load i8* @foo8
+	%t1 = load i8, i8* @foo8
 	%t2 = and i8 15, %t1
 	%t3 = icmp ne i8 %t2, 0
 	%t4 = zext i1 %t3 to i8
@@ -53,7 +53,7 @@ define i8 @bitbim() nounwind {
 ; CHECK: bit.b	#15, &foo8
 
 define i8 @bitbrm(i8 %a) nounwind {
-	%t1 = load i8* @foo8
+	%t1 = load i8, i8* @foo8
 	%t2 = and i8 %a, %t1
 	%t3 = icmp ne i8 %t2, 0
 	%t4 = zext i1 %t3 to i8
@@ -63,7 +63,7 @@ define i8 @bitbrm(i8 %a) nounwind {
 ; CHECK: bit.b	&foo8, r15
 
 define i8 @bitbmr(i8 %a) nounwind {
-	%t1 = load i8* @foo8
+	%t1 = load i8, i8* @foo8
 	%t2 = and i8 %t1, %a
 	%t3 = icmp ne i8 %t2, 0
 	%t4 = zext i1 %t3 to i8
@@ -73,8 +73,8 @@ define i8 @bitbmr(i8 %a) nounwind {
 ; CHECK: bit.b	r15, &foo8
 
 define i8 @bitbmm() nounwind {
-	%t1 = load i8* @foo8
-	%t2 = load i8* @bar8
+	%t1 = load i8, i8* @foo8
+	%t2 = load i8, i8* @bar8
 	%t3 = and i8 %t1, %t2
 	%t4 = icmp ne i8 %t3, 0
 	%t5 = zext i1 %t4 to i8
@@ -114,7 +114,7 @@ define i16 @bitwir(i16 %a) nounwind {
 ; CHECK: bit.w	#4080, r15
 
 define i16 @bitwmi() nounwind {
-	%t1 = load i16* @foo16
+	%t1 = load i16, i16* @foo16
 	%t2 = and i16 %t1, 4080
 	%t3 = icmp ne i16 %t2, 0
 	%t4 = zext i1 %t3 to i16
@@ -124,7 +124,7 @@ define i16 @bitwmi() nounwind {
 ; CHECK: bit.w	#4080, &foo16
 
 define i16 @bitwim() nounwind {
-	%t1 = load i16* @foo16
+	%t1 = load i16, i16* @foo16
 	%t2 = and i16 4080, %t1
 	%t3 = icmp ne i16 %t2, 0
 	%t4 = zext i1 %t3 to i16
@@ -134,7 +134,7 @@ define i16 @bitwim() nounwind {
 ; CHECK: bit.w	#4080, &foo16
 
 define i16 @bitwrm(i16 %a) nounwind {
-	%t1 = load i16* @foo16
+	%t1 = load i16, i16* @foo16
 	%t2 = and i16 %a, %t1
 	%t3 = icmp ne i16 %t2, 0
 	%t4 = zext i1 %t3 to i16
@@ -144,7 +144,7 @@ define i16 @bitwrm(i16 %a) nounwind {
 ; CHECK: bit.w	&foo16, r15
 
 define i16 @bitwmr(i16 %a) nounwind {
-	%t1 = load i16* @foo16
+	%t1 = load i16, i16* @foo16
 	%t2 = and i16 %t1, %a
 	%t3 = icmp ne i16 %t2, 0
 	%t4 = zext i1 %t3 to i16
@@ -154,8 +154,8 @@ define i16 @bitwmr(i16 %a) nounwind {
 ; CHECK: bit.w	r15, &foo16
 
 define i16 @bitwmm() nounwind {
-	%t1 = load i16* @foo16
-	%t2 = load i16* @bar16
+	%t1 = load i16, i16* @foo16
+	%t2 = load i16, i16* @bar16
 	%t3 = and i16 %t1, %t2
 	%t4 = icmp ne i16 %t3, 0
 	%t5 = zext i1 %t4 to i16
diff --git a/test/CodeGen/MSP430/byval.ll b/test/CodeGen/MSP430/byval.ll
index bd38e95554df..410a6b047b6e 100644
--- a/test/CodeGen/MSP430/byval.ll
+++ b/test/CodeGen/MSP430/byval.ll
@@ -10,8 +10,8 @@ define i16 @callee(%struct.Foo* byval %f) nounwind {
 entry:
 ; CHECK-LABEL: callee:
 ; CHECK: mov.w 2(r1), r15
-  %0 = getelementptr inbounds %struct.Foo* %f, i32 0, i32 0
-  %1 = load i16* %0, align 2
+  %0 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i32 0, i32 0
+  %1 = load i16, i16* %0, align 2
   ret i16 %1
 }
 
diff --git a/test/CodeGen/MSP430/indirectbr.ll b/test/CodeGen/MSP430/indirectbr.ll
index 2a62c9135c6a..af1a466b3c78 100644
--- a/test/CodeGen/MSP430/indirectbr.ll
+++ b/test/CodeGen/MSP430/indirectbr.ll
@@ -5,7 +5,7 @@
 
 define internal i16 @foo(i16 %i) nounwind {
 entry:
-  %0 = load i8** @nextaddr, align 4               ; <i8*> [#uses=2]
+  %0 = load i8*, i8** @nextaddr, align 4               ; <i8*> [#uses=2]
   %1 = icmp eq i8* %0, null                       ; <i1> [#uses=1]
   br i1 %1, label %bb3, label %bb2
 
@@ -14,8 +14,8 @@ bb2:                                              ; preds = %bb3, %entry
   indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
 
 bb3:                                              ; preds = %entry
-  %2 = getelementptr inbounds [5 x i8*]* @C.0.2070, i16 0, i16 %i ; <i8**> [#uses=1]
-  %gotovar.4.0.pre = load i8** %2, align 4        ; <i8*> [#uses=1]
+  %2 = getelementptr inbounds [5 x i8*], [5 x i8*]* @C.0.2070, i16 0, i16 %i ; <i8**> [#uses=1]
+  %gotovar.4.0.pre = load i8*, i8** %2, align 4        ; <i8*> [#uses=1]
   br label %bb2
 
 L5:                                               ; preds = %bb2
diff --git a/test/CodeGen/MSP430/indirectbr2.ll b/test/CodeGen/MSP430/indirectbr2.ll
index 93788b696553..b0b4f1cbfd24 100644
--- a/test/CodeGen/MSP430/indirectbr2.ll
+++ b/test/CodeGen/MSP430/indirectbr2.ll
@@ -3,8 +3,8 @@
 
 define internal i16 @foo(i16 %i) nounwind {
 entry:
-  %tmp1 = getelementptr inbounds [5 x i8*]* @C.0.2070, i16 0, i16 %i ; <i8**> [#uses=1]
-  %gotovar.4.0 = load i8** %tmp1, align 4        ; <i8*> [#uses=1]
+  %tmp1 = getelementptr inbounds [5 x i8*], [5 x i8*]* @C.0.2070, i16 0, i16 %i ; <i8**> [#uses=1]
+  %gotovar.4.0 = load i8*, i8** %tmp1, align 4        ; <i8*> [#uses=1]
 ; CHECK: br .LC.0.2070(r12)
   indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
 
diff --git a/test/CodeGen/MSP430/inline-asm.ll b/test/CodeGen/MSP430/inline-asm.ll
index 0e7886a4721b..a2f13235b1d3 100644
--- a/test/CodeGen/MSP430/inline-asm.ll
+++ b/test/CodeGen/MSP430/inline-asm.ll
@@ -15,12 +15,12 @@ define void @reg(i16 %a) nounwind {
 @foo = global i16 0, align 2
 
 define void @immmem() nounwind {
-        call void asm sideeffect "bic\09$0,r2", "i"(i16* getelementptr(i16* @foo, i32 1)) nounwind
+        call void asm sideeffect "bic\09$0,r2", "i"(i16* getelementptr(i16, i16* @foo, i32 1)) nounwind
         ret void
 }
 
 define void @mem() nounwind {
-        %fooval = load i16* @foo
+        %fooval = load i16, i16* @foo
         call void asm sideeffect "bic\09$0,r2", "m"(i16 %fooval) nounwind
         ret void
 }
diff --git a/test/CodeGen/MSP430/jumptable.ll b/test/CodeGen/MSP430/jumptable.ll
index 239d79ed9cba..4ba930b04e39 100644
--- a/test/CodeGen/MSP430/jumptable.ll
+++ b/test/CodeGen/MSP430/jumptable.ll
@@ -10,7 +10,7 @@ entry:
   %retval = alloca i16, align 2
   %i.addr = alloca i16, align 2
   store i16 %i, i16* %i.addr, align 2
-  %0 = load i16* %i.addr, align 2
+  %0 = load i16, i16* %i.addr, align 2
 ; CHECK: mov.w #2, r14
 ; CHECK: call #__mulhi3hw_noint
 ; CHECK: br .LJTI0_0(r15)
@@ -42,7 +42,7 @@ sw.default:                                       ; preds = %entry
   br label %return
 
 return:                                           ; preds = %sw.default, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb
-  %1 = load i16* %retval
+  %1 = load i16, i16* %retval
   ret i16 %1
 ; CHECK: ret
 }
diff --git a/test/CodeGen/MSP430/memset.ll b/test/CodeGen/MSP430/memset.ll
index bf105446f52d..76cfb29586d7 100644
--- a/test/CodeGen/MSP430/memset.ll
+++ b/test/CodeGen/MSP430/memset.ll
@@ -8,7 +8,7 @@ target triple = "msp430---elf"
 define void @test() nounwind {
 entry:
 ; CHECK-LABEL: test:
-  %0 = load i8** @buf, align 2
+  %0 = load i8*, i8** @buf, align 2
 ; CHECK: mov.w &buf, r15
 ; CHECK-NEXT: mov.w #5, r14
 ; CHECK-NEXT: mov.w #128, r13
diff --git a/test/CodeGen/MSP430/misched-msp430.ll b/test/CodeGen/MSP430/misched-msp430.ll
index c8541eff5836..3d18fa005a6b 100644
--- a/test/CodeGen/MSP430/misched-msp430.ll
+++ b/test/CodeGen/MSP430/misched-msp430.ll
@@ -14,7 +14,7 @@ target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
 ; CHECK: ret
 define void @f() {
 entry:
-  %0 = load i16* @y, align 2
+  %0 = load i16, i16* @y, align 2
   store i16 %0, i16* @x, align 2
   ret void
 }
diff --git a/test/CodeGen/MSP430/mult-alt-generic-msp430.ll b/test/CodeGen/MSP430/mult-alt-generic-msp430.ll
index 342afed66053..8cf83879b090 100644
--- a/test/CodeGen/MSP430/mult-alt-generic-msp430.ll
+++ b/test/CodeGen/MSP430/mult-alt-generic-msp430.ll
@@ -33,10 +33,10 @@ entry:
   %in1 = alloca i16, align 2
   store i16 0, i16* %out0, align 2
   store i16 1, i16* %in1, align 2
-  %tmp = load i16* %in1, align 2
+  %tmp = load i16, i16* %in1, align 2
   %0 = call i16 asm "foo $1,$0", "=r,<r"(i16 %tmp) nounwind
   store i16 %0, i16* %out0, align 2
-  %tmp1 = load i16* %in1, align 2
+  %tmp1 = load i16, i16* %in1, align 2
   %1 = call i16 asm "foo $1,$0", "=r,r<"(i16 %tmp1) nounwind
   store i16 %1, i16* %out0, align 2
   ret void
@@ -48,10 +48,10 @@ entry:
   %in1 = alloca i16, align 2
   store i16 0, i16* %out0, align 2
   store i16 1, i16* %in1, align 2
-  %tmp = load i16* %in1, align 2
+  %tmp = load i16, i16* %in1, align 2
   %0 = call i16 asm "foo $1,$0", "=r,>r"(i16 %tmp) nounwind
   store i16 %0, i16* %out0, align 2
-  %tmp1 = load i16* %in1, align 2
+  %tmp1 = load i16, i16* %in1, align 2
   %1 = call i16 asm "foo $1,$0", "=r,r>"(i16 %tmp1) nounwind
   store i16 %1, i16* %out0, align 2
   ret void
@@ -63,7 +63,7 @@ entry:
   %in1 = alloca i16, align 2
   store i16 0, i16* %out0, align 2
   store i16 1, i16* %in1, align 2
-  %tmp = load i16* %in1, align 2
+  %tmp = load i16, i16* %in1, align 2
   %0 = call i16 asm "foo $1,$0", "=r,r"(i16 %tmp) nounwind
   store i16 %0, i16* %out0, align 2
   ret void
@@ -120,10 +120,10 @@ entry:
   %in1 = alloca i16, align 2
   store i16 0, i16* %out0, align 2
   store i16 1, i16* %in1, align 2
-  %tmp = load i16* %in1, align 2
+  %tmp = load i16, i16* %in1, align 2
   %0 = call i16 asm "foo $1,$0", "=r,imr"(i16 %tmp) nounwind
   store i16 %0, i16* %out0, align 2
-  %tmp1 = load i16* @min1, align 2
+  %tmp1 = load i16, i16* @min1, align 2
   %1 = call i16 asm "foo $1,$0", "=r,imr"(i16 %tmp1) nounwind
   store i16 %1, i16* %out0, align 2
   %2 = call i16 asm "foo $1,$0", "=r,imr"(i16 1) nounwind
@@ -137,15 +137,15 @@ entry:
   %in1 = alloca i16, align 2
   store i16 0, i16* %out0, align 2
   store i16 1, i16* %in1, align 2
-  %tmp = load i16* %in1, align 2
+  %tmp = load i16, i16* %in1, align 2
   %0 = call i16 asm "foo $1,$0", "=r,X"(i16 %tmp) nounwind
   store i16 %0, i16* %out0, align 2
-  %tmp1 = load i16* @min1, align 2
+  %tmp1 = load i16, i16* @min1, align 2
   %1 = call i16 asm "foo $1,$0", "=r,X"(i16 %tmp1) nounwind
   store i16 %1, i16* %out0, align 2
   %2 = call i16 asm "foo $1,$0", "=r,X"(i16 1) nounwind
   store i16 %2, i16* %out0, align 2
-  %3 = call i16 asm "foo $1,$0", "=r,X"(i16* getelementptr inbounds ([2 x i16]* @marray, i32 0, i32 0)) nounwind
+  %3 = call i16 asm "foo $1,$0", "=r,X"(i16* getelementptr inbounds ([2 x i16], [2 x i16]* @marray, i32 0, i32 0)) nounwind
   store i16 %3, i16* %out0, align 2
 ; No lowering support.
 ;  %4 = call i16 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind
@@ -159,14 +159,14 @@ define void @single_p() nounwind {
 entry:
   %out0 = alloca i16, align 2
   store i16 0, i16* %out0, align 2
-  %0 = call i16 asm "foo $1,$0", "=r,r"(i16* getelementptr inbounds ([2 x i16]* @marray, i32 0, i32 0)) nounwind
+  %0 = call i16 asm "foo $1,$0", "=r,r"(i16* getelementptr inbounds ([2 x i16], [2 x i16]* @marray, i32 0, i32 0)) nounwind
   store i16 %0, i16* %out0, align 2
   ret void
 }
 
 define void @multi_m() nounwind {
 entry:
-  %tmp = load i16* @min1, align 2
+  %tmp = load i16, i16* @min1, align 2
   call void asm "foo $1,$0", "=*m|r,m|r"(i16* @mout0, i16 %tmp) nounwind
   ret void
 }
@@ -191,10 +191,10 @@ entry:
   %in1 = alloca i16, align 2
   store i16 0, i16* %out0, align 2
   store i16 1, i16* %in1, align 2
-  %tmp = load i16* %in1, align 2
+  %tmp = load i16, i16* %in1, align 2
   %0 = call i16 asm "foo $1,$0", "=r|r,r|<r"(i16 %tmp) nounwind
   store i16 %0, i16* %out0, align 2
-  %tmp1 = load i16* %in1, align 2
+  %tmp1 = load i16, i16* %in1, align 2
   %1 = call i16 asm "foo $1,$0", "=r|r,r|r<"(i16 %tmp1) nounwind
   store i16 %1, i16* %out0, align 2
   ret void
@@ -206,10 +206,10 @@ entry:
   %in1 = alloca i16, align 2
   store i16 0, i16* %out0, align 2
   store i16 1, i16* %in1, align 2
-  %tmp = load i16* %in1, align 2
+  %tmp = load i16, i16* %in1, align 2
   %0 = call i16 asm "foo $1,$0", "=r|r,r|>r"(i16 %tmp) nounwind
   store i16 %0, i16* %out0, align 2
-  %tmp1 = load i16* %in1, align 2
+  %tmp1 = load i16, i16* %in1, align 2
   %1 = call i16 asm "foo $1,$0", "=r|r,r|r>"(i16 %tmp1) nounwind
   store i16 %1, i16* %out0, align 2
   ret void
@@ -221,7 +221,7 @@ entry:
   %in1 = alloca i16, align 2
   store i16 0, i16* %out0, align 2
   store i16 1, i16* %in1, align 2
-  %tmp = load i16* %in1, align 2
+  %tmp = load i16, i16* %in1, align 2
   %0 = call i16 asm "foo $1,$0", "=r|r,r|m"(i16 %tmp) nounwind
   store i16 %0, i16* %out0, align 2
   ret void
@@ -278,10 +278,10 @@ entry:
   %in1 = alloca i16, align 2
   store i16 0, i16* %out0, align 2
   store i16 1, i16* %in1, align 2
-  %tmp = load i16* %in1, align 2
+  %tmp = load i16, i16* %in1, align 2
   %0 = call i16 asm "foo $1,$0", "=r|r,r|imr"(i16 %tmp) nounwind
   store i16 %0, i16* %out0, align 2
-  %tmp1 = load i16* @min1, align 2
+  %tmp1 = load i16, i16* @min1, align 2
   %1 = call i16 asm "foo $1,$0", "=r|r,r|imr"(i16 %tmp1) nounwind
   store i16 %1, i16* %out0, align 2
   %2 = call i16 asm "foo $1,$0", "=r|r,r|imr"(i16 1) nounwind
@@ -295,15 +295,15 @@ entry:
   %in1 = alloca i16, align 2
   store i16 0, i16* %out0, align 2
   store i16 1, i16* %in1, align 2
-  %tmp = load i16* %in1, align 2
+  %tmp = load i16, i16* %in1, align 2
   %0 = call i16 asm "foo $1,$0", "=r|r,r|X"(i16 %tmp) nounwind
   store i16 %0, i16* %out0, align 2
-  %tmp1 = load i16* @min1, align 2
+  %tmp1 = load i16, i16* @min1, align 2
   %1 = call i16 asm "foo $1,$0", "=r|r,r|X"(i16 %tmp1) nounwind
   store i16 %1, i16* %out0, align 2
   %2 = call i16 asm "foo $1,$0", "=r|r,r|X"(i16 1) nounwind
   store i16 %2, i16* %out0, align 2
-  %3 = call i16 asm "foo $1,$0", "=r|r,r|X"(i16* getelementptr inbounds ([2 x i16]* @marray, i32 0, i32 0)) nounwind
+  %3 = call i16 asm "foo $1,$0", "=r|r,r|X"(i16* getelementptr inbounds ([2 x i16], [2 x i16]* @marray, i32 0, i32 0)) nounwind
   store i16 %3, i16* %out0, align 2
 ; No lowering support.
 ;  %4 = call i16 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind
@@ -317,7 +317,7 @@ define void @multi_p() nounwind {
 entry:
   %out0 = alloca i16, align 2
   store i16 0, i16* %out0, align 2
-  %0 = call i16 asm "foo $1,$0", "=r|r,r|r"(i16* getelementptr inbounds ([2 x i16]* @marray, i32 0, i32 0)) nounwind
+  %0 = call i16 asm "foo $1,$0", "=r|r,r|r"(i16* getelementptr inbounds ([2 x i16], [2 x i16]* @marray, i32 0, i32 0)) nounwind
   store i16 %0, i16* %out0, align 2
   ret void
 }
diff --git a/test/CodeGen/MSP430/postinc.ll b/test/CodeGen/MSP430/postinc.ll
index 8d55fd3f8031..75a927f33fce 100644
--- a/test/CodeGen/MSP430/postinc.ll
+++ b/test/CodeGen/MSP430/postinc.ll
@@ -10,10 +10,10 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
-  %arrayidx = getelementptr i16* %a, i16 %i.010   ; <i16*> [#uses=1]
+  %arrayidx = getelementptr i16, i16* %a, i16 %i.010   ; <i16*> [#uses=1]
 ; CHECK-LABEL: add:
 ; CHECK: add.w @r{{[0-9]+}}+, r{{[0-9]+}}
-  %tmp4 = load i16* %arrayidx                     ; <i16> [#uses=1]
+  %tmp4 = load i16, i16* %arrayidx                     ; <i16> [#uses=1]
   %add = add i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
   %inc = add i16 %i.010, 1                        ; <i16> [#uses=2]
   %exitcond = icmp eq i16 %inc, %n                ; <i1> [#uses=1]
@@ -32,10 +32,10 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
-  %arrayidx = getelementptr i16* %a, i16 %i.010   ; <i16*> [#uses=1]
+  %arrayidx = getelementptr i16, i16* %a, i16 %i.010   ; <i16*> [#uses=1]
 ; CHECK-LABEL: sub:
 ; CHECK: sub.w @r{{[0-9]+}}+, r{{[0-9]+}}
-  %tmp4 = load i16* %arrayidx                     ; <i16> [#uses=1]
+  %tmp4 = load i16, i16* %arrayidx                     ; <i16> [#uses=1]
   %add = sub i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
   %inc = add i16 %i.010, 1                        ; <i16> [#uses=2]
   %exitcond = icmp eq i16 %inc, %n                ; <i1> [#uses=1]
@@ -54,10 +54,10 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
-  %arrayidx = getelementptr i16* %a, i16 %i.010   ; <i16*> [#uses=1]
+  %arrayidx = getelementptr i16, i16* %a, i16 %i.010   ; <i16*> [#uses=1]
 ; CHECK-LABEL: or:
 ; CHECK: bis.w @r{{[0-9]+}}+, r{{[0-9]+}}
-  %tmp4 = load i16* %arrayidx                     ; <i16> [#uses=1]
+  %tmp4 = load i16, i16* %arrayidx                     ; <i16> [#uses=1]
   %add = or i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
   %inc = add i16 %i.010, 1                        ; <i16> [#uses=2]
   %exitcond = icmp eq i16 %inc, %n                ; <i1> [#uses=1]
@@ -76,10 +76,10 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
-  %arrayidx = getelementptr i16* %a, i16 %i.010   ; <i16*> [#uses=1]
+  %arrayidx = getelementptr i16, i16* %a, i16 %i.010   ; <i16*> [#uses=1]
 ; CHECK-LABEL: xor:
 ; CHECK: xor.w @r{{[0-9]+}}+, r{{[0-9]+}}
-  %tmp4 = load i16* %arrayidx                     ; <i16> [#uses=1]
+  %tmp4 = load i16, i16* %arrayidx                     ; <i16> [#uses=1]
   %add = xor i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
   %inc = add i16 %i.010, 1                        ; <i16> [#uses=2]
   %exitcond = icmp eq i16 %inc, %n                ; <i1> [#uses=1]
@@ -98,10 +98,10 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
-  %arrayidx = getelementptr i16* %a, i16 %i.010   ; <i16*> [#uses=1]
+  %arrayidx = getelementptr i16, i16* %a, i16 %i.010   ; <i16*> [#uses=1]
 ; CHECK-LABEL: and:
 ; CHECK: and.w @r{{[0-9]+}}+, r{{[0-9]+}}
-  %tmp4 = load i16* %arrayidx                     ; <i16> [#uses=1]
+  %tmp4 = load i16, i16* %arrayidx                     ; <i16> [#uses=1]
   %add = and i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
   %inc = add i16 %i.010, 1                        ; <i16> [#uses=2]
   %exitcond = icmp eq i16 %inc, %n                ; <i1> [#uses=1]
diff --git a/test/CodeGen/Mips/2008-07-03-SRet.ll b/test/CodeGen/Mips/2008-07-03-SRet.ll
index afec7f65d607..6313ec4af356 100644
--- a/test/CodeGen/Mips/2008-07-03-SRet.ll
+++ b/test/CodeGen/Mips/2008-07-03-SRet.ll
@@ -7,11 +7,11 @@ entry:
 ; CHECK: sw ${{[0-9]+}}, {{[0-9]+}}($4)
 ; CHECK: sw ${{[0-9]+}}, {{[0-9]+}}($4)
 ; CHECK: sw ${{[0-9]+}}, {{[0-9]+}}($4)
-  getelementptr %struct.sret0* %agg.result, i32 0, i32 0    ; <i32*>:0 [#uses=1]
+  getelementptr %struct.sret0, %struct.sret0* %agg.result, i32 0, i32 0    ; <i32*>:0 [#uses=1]
   store i32 %dummy, i32* %0, align 4
-  getelementptr %struct.sret0* %agg.result, i32 0, i32 1    ; <i32*>:1 [#uses=1]
+  getelementptr %struct.sret0, %struct.sret0* %agg.result, i32 0, i32 1    ; <i32*>:1 [#uses=1]
   store i32 %dummy, i32* %1, align 4
-  getelementptr %struct.sret0* %agg.result, i32 0, i32 2    ; <i32*>:2 [#uses=1]
+  getelementptr %struct.sret0, %struct.sret0* %agg.result, i32 0, i32 2    ; <i32*>:2 [#uses=1]
   store i32 %dummy, i32* %2, align 4
   ret void
 }
diff --git a/test/CodeGen/Mips/2008-07-15-InternalConstant.ll b/test/CodeGen/Mips/2008-07-15-InternalConstant.ll
index 29a7b5c3761a..d7e8f5c2d03f 100644
--- a/test/CodeGen/Mips/2008-07-15-InternalConstant.ll
+++ b/test/CodeGen/Mips/2008-07-15-InternalConstant.ll
@@ -8,7 +8,7 @@ entry:
 ; CHECK: foo
 ; CHECK: %hi(.str)
 ; CHECK: %lo(.str)
-	ret i8* getelementptr ([10 x i8]* @.str, i32 0, i32 0)
+	ret i8* getelementptr ([10 x i8], [10 x i8]* @.str, i32 0, i32 0)
 }
 
 define i32* @bar() nounwind  {
@@ -16,7 +16,7 @@ entry:
 ; CHECK: bar
 ; CHECK: %hi(i0)
 ; CHECK: %lo(i0)
-  ret i32* getelementptr ([5 x i32]* @i0, i32 0, i32 0)
+  ret i32* getelementptr ([5 x i32], [5 x i32]* @i0, i32 0, i32 0)
 }
 
 ; CHECK: rodata.str1.4,"aMS",@progbits
diff --git a/test/CodeGen/Mips/2008-07-15-SmallSection.ll b/test/CodeGen/Mips/2008-07-15-SmallSection.ll
index cbc3ecf5edc8..08d99d899103 100644
--- a/test/CodeGen/Mips/2008-07-15-SmallSection.ll
+++ b/test/CodeGen/Mips/2008-07-15-SmallSection.ll
@@ -22,13 +22,13 @@ target triple = "mipsallegrexel-unknown-psp-elf"
 
 define i8* @A0() nounwind {
 entry:
-	ret i8* getelementptr ([8 x i8]* @s0, i32 0, i32 0)
+	ret i8* getelementptr ([8 x i8], [8 x i8]* @s0, i32 0, i32 0)
 }
 
 define i32 @A1() nounwind {
 entry:
-  load i32* getelementptr (%struct.anon* @foo, i32 0, i32 0), align 8 
-  load i32* getelementptr (%struct.anon* @foo, i32 0, i32 1), align 4 
+  load i32, i32* getelementptr (%struct.anon, %struct.anon* @foo, i32 0, i32 0), align 8 
+  load i32, i32* getelementptr (%struct.anon, %struct.anon* @foo, i32 0, i32 1), align 4 
   add i32 %1, %0
   ret i32 %2
 }
diff --git a/test/CodeGen/Mips/2008-08-01-AsmInline.ll b/test/CodeGen/Mips/2008-08-01-AsmInline.ll
index 3c1bb39b4340..5edba029502a 100644
--- a/test/CodeGen/Mips/2008-08-01-AsmInline.ll
+++ b/test/CodeGen/Mips/2008-08-01-AsmInline.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s
 
 %struct.DWstruct = type { i32, i32 }
 
@@ -26,8 +26,8 @@ entry:
 define void @foo0() nounwind {
 entry:
 ; CHECK: addu
-  %0 = load i32* @gi1, align 4
-  %1 = load i32* @gi0, align 4
+  %0 = load i32, i32* @gi1, align 4
+  %1 = load i32, i32* @gi0, align 4
   %2 = tail call i32 asm "addu $0, $1, $2", "=r,r,r"(i32 %0, i32 %1) nounwind
   store i32 %2, i32* @gi2, align 4
   ret void
@@ -36,7 +36,7 @@ entry:
 define void @foo2() nounwind {
 entry:
 ; CHECK: neg.s
-  %0 = load float* @gf1, align 4
+  %0 = load float, float* @gf1, align 4
   %1 = tail call float asm "neg.s $0, $1", "=f,f"(float %0) nounwind
   store float %1, float* @gf0, align 4
   ret void
@@ -45,7 +45,7 @@ entry:
 define void @foo3() nounwind {
 entry:
 ; CHECK: neg.d
-  %0 = load double* @gd1, align 8
+  %0 = load double, double* @gd1, align 8
   %1 = tail call double asm "neg.d $0, $1", "=f,f"(double %0) nounwind
   store double %1, double* @gd0, align 8
   ret void
@@ -64,7 +64,7 @@ define void @foo4() {
 entry:
   %0 = tail call i32 asm sideeffect "ulh $0,16($$sp)\0A\09", "=r,~{$2}"()
   store i32 %0, i32* @gi2, align 4
-  %1 = load float* @gf0, align 4
+  %1 = load float, float* @gf0, align 4
   %2 = tail call double asm sideeffect "cvt.d.s $0, $1\0A\09", "=f,f,~{$f0}"(float %1)
   store double %2, double* @gd0, align 8
   ret void
diff --git a/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll b/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll
index c41d5213c178..592e574a3622 100644
--- a/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll
+++ b/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll
@@ -7,12 +7,12 @@ entry:
         %retval = alloca double         ; <double*> [#uses=3]
         store double 0.000000e+00, double* %retval
         %r = alloca double              ; <double*> [#uses=1]
-        load double* %r         ; <double>:0 [#uses=1]
+        load double, double* %r         ; <double>:0 [#uses=1]
         store double %0, double* %retval
         br label %return
 
 return:         ; preds = %entry
-        load double* %retval            ; <double>:1 [#uses=1]
+        load double, double* %retval            ; <double>:1 [#uses=1]
         ret double %1
 }
 
diff --git a/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll b/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll
index 18f5b3d7ff7b..eaf6ddc911e3 100644
--- a/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll
+++ b/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll
@@ -7,8 +7,8 @@ entry:
 
 continue.outer:         ; preds = %case4, %entry
         %p.0.ph.rec = phi i32 [ 0, %entry ], [ %indvar.next, %case4 ]          ; <i32> [#uses=2]
-        %p.0.ph = getelementptr i8* %0, i32 %p.0.ph.rec         ; <i8*> [#uses=1]
-        %1 = load i8* %p.0.ph           ; <i8> [#uses=1]
+        %p.0.ph = getelementptr i8, i8* %0, i32 %p.0.ph.rec         ; <i8*> [#uses=1]
+        %1 = load i8, i8* %p.0.ph           ; <i8> [#uses=1]
         switch i8 %1, label %infloop [
                 i8 0, label %return.split
                 i8 76, label %case4
diff --git a/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll b/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll
index 9c4838a87e51..789f7ee3d4b4 100644
--- a/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll
+++ b/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -soft-float < %s
+; RUN: llc -march=mips -mattr=+soft-float < %s
 ; PR2667
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 	%struct._Bigint = type { %struct._Bigint*, i32, i32, i32, i32, [1 x i32] }
@@ -13,16 +13,16 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f
 define double @_erand48_r(%struct._reent* %r, i16* %xseed) nounwind {
 entry:
 	tail call void @__dorand48( %struct._reent* %r, i16* %xseed ) nounwind
-	load i16* %xseed, align 2		; <i16>:0 [#uses=1]
+	load i16, i16* %xseed, align 2		; <i16>:0 [#uses=1]
 	uitofp i16 %0 to double		; <double>:1 [#uses=1]
 	tail call double @ldexp( double %1, i32 -48 ) nounwind		; <double>:2 [#uses=1]
-	getelementptr i16* %xseed, i32 1		; <i16*>:3 [#uses=1]
-	load i16* %3, align 2		; <i16>:4 [#uses=1]
+	getelementptr i16, i16* %xseed, i32 1		; <i16*>:3 [#uses=1]
+	load i16, i16* %3, align 2		; <i16>:4 [#uses=1]
 	uitofp i16 %4 to double		; <double>:5 [#uses=1]
 	tail call double @ldexp( double %5, i32 -32 ) nounwind		; <double>:6 [#uses=1]
 	fadd double %2, %6		; <double>:7 [#uses=1]
-	getelementptr i16* %xseed, i32 2		; <i16*>:8 [#uses=1]
-	load i16* %8, align 2		; <i16>:9 [#uses=1]
+	getelementptr i16, i16* %xseed, i32 2		; <i16*>:8 [#uses=1]
+	load i16, i16* %8, align 2		; <i16>:9 [#uses=1]
 	uitofp i16 %9 to double		; <double>:10 [#uses=1]
 	tail call double @ldexp( double %10, i32 -16 ) nounwind		; <double>:11 [#uses=1]
 	fadd double %7, %11		; <double>:12 [#uses=1]
@@ -35,18 +35,18 @@ declare double @ldexp(double, i32)
 
 define double @erand48(i16* %xseed) nounwind {
 entry:
-	load %struct._reent** @_impure_ptr, align 4		; <%struct._reent*>:0 [#uses=1]
+	load %struct._reent*, %struct._reent** @_impure_ptr, align 4		; <%struct._reent*>:0 [#uses=1]
 	tail call void @__dorand48( %struct._reent* %0, i16* %xseed ) nounwind
-	load i16* %xseed, align 2		; <i16>:1 [#uses=1]
+	load i16, i16* %xseed, align 2		; <i16>:1 [#uses=1]
 	uitofp i16 %1 to double		; <double>:2 [#uses=1]
 	tail call double @ldexp( double %2, i32 -48 ) nounwind		; <double>:3 [#uses=1]
-	getelementptr i16* %xseed, i32 1		; <i16*>:4 [#uses=1]
-	load i16* %4, align 2		; <i16>:5 [#uses=1]
+	getelementptr i16, i16* %xseed, i32 1		; <i16*>:4 [#uses=1]
+	load i16, i16* %4, align 2		; <i16>:5 [#uses=1]
 	uitofp i16 %5 to double		; <double>:6 [#uses=1]
 	tail call double @ldexp( double %6, i32 -32 ) nounwind		; <double>:7 [#uses=1]
 	fadd double %3, %7		; <double>:8 [#uses=1]
-	getelementptr i16* %xseed, i32 2		; <i16*>:9 [#uses=1]
-	load i16* %9, align 2		; <i16>:10 [#uses=1]
+	getelementptr i16, i16* %xseed, i32 2		; <i16*>:9 [#uses=1]
+	load i16, i16* %9, align 2		; <i16>:10 [#uses=1]
 	uitofp i16 %10 to double		; <double>:11 [#uses=1]
 	tail call double @ldexp( double %11, i32 -16 ) nounwind		; <double>:12 [#uses=1]
 	fadd double %8, %12		; <double>:13 [#uses=1]
diff --git a/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll b/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll
index c3791dfc7ce6..f736ddd0def6 100644
--- a/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll
+++ b/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll
@@ -1,9 +1,9 @@
 ; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-O32
 ; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-O32
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n32 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N32
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n32 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N32
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n64 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N64
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n64 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N64
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n32 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N32
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n32 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N32
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n64 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N64
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n64 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N64
 
 define float @h() nounwind readnone {
 entry:
diff --git a/test/CodeGen/Mips/2010-07-20-Switch.ll b/test/CodeGen/Mips/2010-07-20-Switch.ll
index 5c840775cf9e..fd0254e9f5ec 100644
--- a/test/CodeGen/Mips/2010-07-20-Switch.ll
+++ b/test/CodeGen/Mips/2010-07-20-Switch.ll
@@ -15,7 +15,7 @@ define i32 @main() nounwind readnone {
 entry:
   %x = alloca i32, align 4                        ; <i32*> [#uses=2]
   store volatile i32 2, i32* %x, align 4
-  %0 = load volatile i32* %x, align 4             ; <i32> [#uses=1]
+  %0 = load volatile i32, i32* %x, align 4             ; <i32> [#uses=1]
 ; STATIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2
 ; STATIC-O32: lui $[[R1:[0-9]+]], %hi($JTI0_0)
 ; STATIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]]
diff --git a/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll b/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll
index 9d4daee696db..24bcfaee8bad 100644
--- a/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll
+++ b/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll
@@ -4,7 +4,7 @@
 
 define void @t(i8* %ptr) {
 entry:
-  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %ptr, i8* getelementptr inbounds ([7 x i8]* @.str, i64 0, i64 0), i64 7, i32 1, i1 false)
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %ptr, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i64 0, i64 0), i64 7, i32 1, i1 false)
   ret void
 }
 
diff --git a/test/CodeGen/Mips/Fast-ISel/br1.ll b/test/CodeGen/Mips/Fast-ISel/br1.ll
index 579a77f88fef..11842ddc4188 100644
--- a/test/CodeGen/Mips/Fast-ISel/br1.ll
+++ b/test/CodeGen/Mips/Fast-ISel/br1.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @b = global i32 1, align 4
@@ -10,7 +10,7 @@
 ; Function Attrs: nounwind
 define void @br() #0 {
 entry:
-  %0 = load i32* @b, align 4
+  %0 = load i32, i32* @b, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %if.end, label %if.then
 
diff --git a/test/CodeGen/Mips/Fast-ISel/callabi.ll b/test/CodeGen/Mips/Fast-ISel/callabi.ll
index e76d7a74bd0e..8f5d68b41f66 100644
--- a/test/CodeGen/Mips/Fast-ISel/callabi.ll
+++ b/test/CodeGen/Mips/Fast-ISel/callabi.ll
@@ -1,477 +1,538 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
-; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
-; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
-; RUN:     < %s | FileCheck %s -check-prefix=mips32r2
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
-; RUN:     < %s | FileCheck %s -check-prefix=mips32
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
-; RUN:     < %s | FileCheck %s -check-prefix=CHECK2
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
-; RUN:     < %s | FileCheck %s -check-prefix=CHECK2
+; RUN: llc -march=mipsel -mcpu=mips32 -O0 \
+; RUN:     -mips-fast-isel -relocation-model=pic -fast-isel-abort=1 < %s | \
+; RUN:     FileCheck %s -check-prefix=ALL -check-prefix=32R1
+; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 \
+; RUN:     -mips-fast-isel -relocation-model=pic -fast-isel-abort=1 < %s | \
+; RUN:     FileCheck %s -check-prefix=ALL -check-prefix=32R2
 
+declare void @xb(i8)
 
-@c1 = global i8 -45, align 1
-@uc1 = global i8 27, align 1
-@s1 = global i16 -1789, align 2
-@us1 = global i16 1256, align 2
+define void @cxb() {
+  ; ALL-LABEL:    cxb:
 
-; Function Attrs: nounwind
-define void @cxi() #0 {
-entry:
-; CHECK-LABEL:  cxi
-  call void @xi(i32 10)
-; CHECK-DAG:    addiu   $4, $zero, 10
-; CHECK-DAG:    lw      $25, %got(xi)(${{[0-9]+}})
-; CHECK:        jalr    $25
+  ; ALL:            addiu   $[[T0:[0-9]+]], $zero, 10
 
+  ; 32R1:           sll     $[[T1:[0-9]+]], $[[T0]], 24
+  ; 32R1:           sra     $4, $[[T1]], 24
+
+  ; 32R2:           seb     $4, $[[T0]]
+  call void @xb(i8 10)
   ret void
 }
 
-declare void @xi(i32) #1
+declare void @xh(i16)
 
-; Function Attrs: nounwind
-define void @cxii() #0 {
-entry:
-; CHECK-LABEL:  cxii
-  call void @xii(i32 746, i32 892)
-; CHECK-DAG:    addiu   $4, $zero, 746
-; CHECK-DAG:    addiu   $5, $zero, 892
-; CHECK-DAG:    lw      $25, %got(xii)(${{[0-9]+}})
-; CHECK:        jalr    $25
+define void @cxh() {
+  ; ALL-LABEL:    cxh:
+
+  ; ALL:            addiu   $[[T0:[0-9]+]], $zero, 10
 
+  ; 32R1:           sll     $[[T1:[0-9]+]], $[[T0]], 16
+  ; 32R1:           sra     $4, $[[T1]], 16
+
+  ; 32R2:           seh     $4, $[[T0]]
+  call void @xh(i16 10)
   ret void
 }
 
-declare void @xii(i32, i32) #1
+declare void @xi(i32)
 
-; Function Attrs: nounwind
-define void @cxiii() #0 {
-entry:
-; CHECK-LABEL:  cxiii
-  call void @xiii(i32 88, i32 44, i32 11)
-; CHECK-DAG:    addiu   $4, $zero, 88
-; CHECK-DAG:    addiu   $5, $zero, 44
-; CHECK-DAG:    addiu   $6, $zero, 11
-; CHECK-DAG:    lw      $25, %got(xiii)(${{[0-9]+}})
-; CHECK:        jalr    $25
+define void @cxi() {
+  ; ALL-LABEL:    cxi:
+
+  ; ALL-DAG:        addiu   $4, $zero, 10
+  ; ALL-DAG:        lw      $25, %got(xi)(${{[0-9]+}})
+  ; ALL:            jalr    $25
+  call void @xi(i32 10)
   ret void
 }
 
-declare void @xiii(i32, i32, i32) #1
+declare void @xbb(i8, i8)
 
-; Function Attrs: nounwind
-define void @cxiiii() #0 {
-entry:
-; CHECK-LABEL:  cxiiii
-  call void @xiiii(i32 167, i32 320, i32 97, i32 14)
-; CHECK-DAG:    addiu   $4, $zero, 167
-; CHECK-DAG:    addiu   $5, $zero, 320
-; CHECK-DAG:    addiu   $6, $zero, 97
-; CHECK-DAG:    addiu   $7, $zero, 14
-; CHECK-DAG:    lw      $25, %got(xiiii)(${{[0-9]+}})
-; CHECK:        jalr    $25
+define void @cxbb() {
+  ; ALL-LABEL:    cxbb:
+
+  ; ALL-DAG:        addiu   $[[T0:[0-9]+]], $zero, 76
+  ; ALL-DAG:        addiu   $[[T1:[0-9]+]], $zero, 101
+
+  ; 32R1-DAG:       sll     $[[T2:[0-9]+]], $[[T0]], 24
+  ; 32R1-DAG:       sra     $[[T3:[0-9]+]], $[[T2]], 24
+  ; 32R1-DAG:       sll     $[[T4:[0-9]+]], $[[T1]], 24
+  ; 32R1-DAG:       sra     $[[T5:[0-9]+]], $[[T4]], 24
 
+  ; 32R2-DAG:       seb     $4, $[[T0]]
+  ; 32R2-DAG:       seb     $5, $[[T1]]
+  call void @xbb(i8 76, i8 101)
   ret void
 }
 
-declare void @xiiii(i32, i32, i32, i32) #1
-
-; Function Attrs: nounwind
-define void @cxiiiiconv() #0 {
-entry:
-; CHECK-LABEL: cxiiiiconv
-; mips32r2-LABEL:  cxiiiiconv
-; mips32-LABEL:  cxiiiiconv
-  %0 = load i8* @c1, align 1
-  %conv = sext i8 %0 to i32
-  %1 = load i8* @uc1, align 1
-  %conv1 = zext i8 %1 to i32
-  %2 = load i16* @s1, align 2
-  %conv2 = sext i16 %2 to i32
-  %3 = load i16* @us1, align 2
-  %conv3 = zext i16 %3 to i32
-  call void @xiiii(i32 %conv, i32 %conv1, i32 %conv2, i32 %conv3)
-; CHECK:        addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; mips32r2:     addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; mips32:       addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; mips32r2-DAG:         lw      $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])
-; mips32r2-DAG: lbu     $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])
-; mips32r2-DAG  seb     $3, $[[REG_C1]]
-; mips32-DAG:   lw      $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])
-; mips32-DAG:   lbu     $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])
-; mips32-DAG:   sll     $[[REG_C1_1:[0-9]+]], $[[REG_C1]], 24
-; mips32-DAG:   sra     $4, $[[REG_C1_1]], 24
-; CHECK-DAG:    lw      $[[REG_UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
-; CHECK-DAG:    lbu     $[[REG_UC1:[0-9]+]], 0($[[REG_UC1_ADDR]])
-; FIXME andi is superfulous
-; CHECK-DAG:    andi    $5, $[[REG_UC1]], 255
-; mips32r2-DAG:         lw      $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
-; mips32r2-DAG: lhu     $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])
-; mips32r2-DAG: seh     $6, $[[REG_S1]]
-; mips32-DAG:   lw      $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
-; mips32-DAG:   lhu     $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])
-; mips32-DAG:   sll     $[[REG_S1_1:[0-9]+]], $[[REG_S1]], 16
-; mips32-DAG:   sra     $6, $[[REG_S1_1]], 16
-; CHECK-DAG:    lw      $[[REG_US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
-; CHECK-DAG:    lhu     $[[REG_US1:[0-9]+]], 0($[[REG_US1_ADDR]])
-; FIXME andi is superfulous
-; CHECK-DAG:    andi    $7, $[[REG_US1]], 65535
-; mips32r2:     jalr    $25
-; mips32r2:     jalr    $25
-; CHECK:        jalr    $25
+declare void @xhh(i16, i16)
+
+define void @cxhh() {
+  ; ALL-LABEL:    cxhh:
+
+  ; ALL-DAG:        addiu   $[[T0:[0-9]+]], $zero, 76
+  ; ALL-DAG:        addiu   $[[T1:[0-9]+]], $zero, 101
+
+  ; 32R1-DAG:       sll     $[[T2:[0-9]+]], $[[T0]], 16
+  ; 32R1-DAG:       sra     $[[T3:[0-9]+]], $[[T2]], 16
+  ; 32R1-DAG:       sll     $[[T4:[0-9]+]], $[[T1]], 16
+  ; 32R1-DAG:       sra     $[[T5:[0-9]+]], $[[T4]], 16
+
+  ; 32R2-DAG:       seh     $4, $[[T0]]
+  ; 32R2-DAG:       seh     $5, $[[T1]]
+  call void @xhh(i16 76, i16 101)
   ret void
 }
 
-; Function Attrs: nounwind
-define void @cxf() #0 {
-entry:
-; CHECK-LABEL:  cxf
-  call void @xf(float 0x40BBC85560000000)
-; CHECK:        addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; CHECK:        lui     $[[REG_FPCONST_1:[0-9]+]], 17886
-; CHECK:        ori     $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 17067
-; CHECK: mtc1   $[[REG_FPCONST]], $f12
-; CHECK:        lw      $25, %got(xf)($[[REG_GP]])
-; CHECK:        jalr    $25
+declare void @xii(i32, i32)
+
+define void @cxii() {
+  ; ALL-LABEL:    cxii:
+
+  ; ALL-DAG:        addiu   $4, $zero, 746
+  ; ALL-DAG:        addiu   $5, $zero, 892
+  ; ALL-DAG:        lw      $25, %got(xii)(${{[0-9]+}})
+  ; ALL:            jalr    $25
+  call void @xii(i32 746, i32 892)
   ret void
 }
 
-declare void @xf(float) #1
+declare void @xccc(i8, i8, i8)
 
-; Function Attrs: nounwind
-define void @cxff() #0 {
-entry:
-; CHECK-LABEL:  cxff
-  call void @xff(float 0x3FF74A6CA0000000, float 0x401A2C0840000000)
-; CHECK:        addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; CHECK-DAG:    lui     $[[REG_FPCONST_1:[0-9]+]], 16314
-; CHECK-DAG:    ori     $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 21349
-; CHECK-DAG: mtc1       $[[REG_FPCONST]], $f12
-; CHECK-DAG:    lui     $[[REG_FPCONST_2:[0-9]+]], 16593
-; CHECK-DAG:    ori     $[[REG_FPCONST_3:[0-9]+]], $[[REG_FPCONST_2]], 24642
-; CHECK-DAG: mtc1       $[[REG_FPCONST_3]], $f14
-; CHECK:        lw      $25, %got(xff)($[[REG_GP]])
-; CHECK:        jalr    $25
+define void @cxccc() {
+  ; ALL-LABEL:    cxccc:
+
+  ; ALL-DAG:        addiu   $[[T0:[0-9]+]], $zero, 88
+  ; ALL-DAG:        addiu   $[[T1:[0-9]+]], $zero, 44
+  ; ALL-DAG:        addiu   $[[T2:[0-9]+]], $zero, 11
+
+  ; 32R1-DAG:       sll     $[[T3:[0-9]+]], $[[T0]], 24
+  ; 32R1-DAG:       sra     $4, $[[T3]], 24
+  ; 32R1-DAG:       sll     $[[T4:[0-9]+]], $[[T1]], 24
+  ; 32R1-DAG:       sra     $5, $[[T4]], 24
+  ; 32R1-DAG:       sll     $[[T5:[0-9]+]], $[[T2]], 24
+  ; 32R1-DAG:       sra     $6, $[[T5]], 24
+
+  ; 32R2-DAG:       seb     $4, $[[T0]]
+  ; 32R2-DAG:       seb     $5, $[[T1]]
+  ; 32R2-DAG:       seb     $6, $[[T2]]
+  call void @xccc(i8 88, i8 44, i8 11)
   ret void
 }
 
-declare void @xff(float, float) #1
+declare void @xhhh(i16, i16, i16)
 
-; Function Attrs: nounwind
-define void @cxfi() #0 {
-entry:
-; CHECK-LABEL: cxfi
-  call void @xfi(float 0x4013906240000000, i32 102)
-; CHECK:        addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; CHECK-DAG:    lui     $[[REG_FPCONST_1:[0-9]+]], 16540
-; CHECK-DAG:    ori     $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 33554
-; CHECK-DAG: mtc1       $[[REG_FPCONST]], $f12
-; CHECK-DAG:    addiu   $5, $zero, 102
-; CHECK:        lw      $25, %got(xfi)($[[REG_GP]])
-; CHECK:        jalr    $25
+define void @cxhhh() {
+  ; ALL-LABEL:    cxhhh:
+
+  ; ALL-DAG:        addiu   $[[T0:[0-9]+]], $zero, 88
+  ; ALL-DAG:        addiu   $[[T1:[0-9]+]], $zero, 44
+  ; ALL-DAG:        addiu   $[[T2:[0-9]+]], $zero, 11
 
+  ; 32R1-DAG:       sll     $[[T3:[0-9]+]], $[[T0]], 16
+  ; 32R1-DAG:       sra     $4, $[[T3]], 16
+  ; 32R1-DAG:       sll     $[[T4:[0-9]+]], $[[T1]], 16
+  ; 32R1-DAG:       sra     $5, $[[T4]], 16
+  ; 32R1-DAG:       sll     $[[T5:[0-9]+]], $[[T2]], 16
+  ; 32R1-DAG:       sra     $6, $[[T5]], 16
+
+  ; 32R2-DAG:       seh     $4, $[[T0]]
+  ; 32R2-DAG:       seh     $5, $[[T1]]
+  ; 32R2-DAG:       seh     $6, $[[T2]]
+  call void @xhhh(i16 88, i16 44, i16 11)
   ret void
 }
 
-declare void @xfi(float, i32) #1
+declare void @xiii(i32, i32, i32)
 
-; Function Attrs: nounwind
-define void @cxfii() #0 {
-entry:
-; CHECK-LABEL: cxfii
-  call void @xfii(float 0x405EC7EE00000000, i32 9993, i32 10922)
-; CHECK:        addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; CHECK-DAG:    lui     $[[REG_FPCONST_1:[0-9]+]], 17142
-; CHECK-DAG:    ori     $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 16240
-; CHECK-DAG: mtc1       $[[REG_FPCONST]], $f12
-; CHECK-DAG:    addiu   $5, $zero, 9993
-; CHECK-DAG:    addiu   $6, $zero, 10922
-; CHECK:        lw      $25, %got(xfii)($[[REG_GP]])
-; CHECK:        jalr    $25
+define void @cxiii() {
+  ; ALL-LABEL:    cxiii:
+
+  ; ALL-DAG:        addiu   $4, $zero, 88
+  ; ALL-DAG:        addiu   $5, $zero, 44
+  ; ALL-DAG:        addiu   $6, $zero, 11
+  ; ALL-DAG:        lw      $25, %got(xiii)(${{[0-9]+}})
+  ; ALL:            jalr    $25
+  call void @xiii(i32 88, i32 44, i32 11)
   ret void
 }
 
-declare void @xfii(float, i32, i32) #1
+declare void @xcccc(i8, i8, i8, i8)
+
+define void @cxcccc() {
+  ; ALL-LABEL:    cxcccc:
+
+  ; ALL-DAG:        addiu   $[[T0:[0-9]+]], $zero, 88
+  ; ALL-DAG:        addiu   $[[T1:[0-9]+]], $zero, 44
+  ; ALL-DAG:        addiu   $[[T2:[0-9]+]], $zero, 11
+  ; ALL-DAG:        addiu   $[[T3:[0-9]+]], $zero, 33
+
+  ; FIXME: We should avoid the unnecessary spill/reload here.
+
+  ; 32R1-DAG:       sll     $[[T4:[0-9]+]], $[[T0]], 24
+  ; 32R1-DAG:       sra     $[[T5:[0-9]+]], $[[T4]], 24
+  ; 32R1-DAG:       sw      $4, 16($sp)
+  ; 32R1-DAG:       move    $4, $[[T5]]
+  ; 32R1-DAG:       sll     $[[T6:[0-9]+]], $[[T1]], 24
+  ; 32R1-DAG:       sra     $5, $[[T6]], 24
+  ; 32R1-DAG:       sll     $[[T7:[0-9]+]], $[[T2]], 24
+  ; 32R1-DAG:       sra     $6, $[[T7]], 24
+  ; 32R1:           lw      $[[T8:[0-9]+]], 16($sp)
+  ; 32R1:           sll     $[[T9:[0-9]+]], $[[T8]], 24
+  ; 32R1:           sra     $7, $[[T9]], 24
+
+  ; 32R2-DAG:       seb     $[[T4:[0-9]+]], $[[T0]]
+  ; 32R2-DAG:       sw      $4, 16($sp)
+  ; 32R2-DAG:       move    $4, $[[T4]]
+  ; 32R2-DAG:       seb     $5, $[[T1]]
+  ; 32R2-DAG:       seb     $6, $[[T2]]
+  ; 32R2-DAG:       lw      $[[T5:[0-9]+]], 16($sp)
+  ; 32R2:           seb     $7, $[[T5]]
+  call void @xcccc(i8 88, i8 44, i8 11, i8 33)
+  ret void
+}
 
-; Function Attrs: nounwind
-define void @cxfiii() #0 {
-entry:
-; CHECK-LABEL: cxfiii
-  call void @xfiii(float 0x405C072B20000000, i32 3948, i32 89011, i32 111222)
-; CHECK:        addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; CHECK-DAG:    lui     $[[REG_FPCONST_1:[0-9]+]], 17120
-; CHECK-DAG:    ori     $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 14681
-; CHECK-DAG: mtc1       $[[REG_FPCONST]], $f12
-; CHECK-DAG:    addiu   $5, $zero, 3948
-; CHECK-DAG:    lui     $[[REG_I_1:[0-9]+]], 1
-; CHECK-DAG:    ori     $6, $[[REG_I_1]], 23475
-; CHECK-DAG:    lui     $[[REG_I_2:[0-9]+]], 1
-; CHECK-DAG:    ori     $7, $[[REG_I_2]], 45686
-; CHECK:        lw      $25, %got(xfiii)($[[REG_GP]])
-; CHECK:        jalr    $25
+declare void @xhhhh(i16, i16, i16, i16)
+
+define void @cxhhhh() {
+  ; ALL-LABEL:    cxhhhh:
+
+  ; ALL-DAG:        addiu   $[[T0:[0-9]+]], $zero, 88
+  ; ALL-DAG:        addiu   $[[T1:[0-9]+]], $zero, 44
+  ; ALL-DAG:        addiu   $[[T2:[0-9]+]], $zero, 11
+  ; ALL-DAG:        addiu   $[[T3:[0-9]+]], $zero, 33
+
+  ; FIXME: We should avoid the unnecessary spill/reload here.
+
+  ; 32R1-DAG:       sll     $[[T4:[0-9]+]], $[[T0]], 16
+  ; 32R1-DAG:       sra     $[[T5:[0-9]+]], $[[T4]], 16
+  ; 32R1-DAG:       sw      $4, 16($sp)
+  ; 32R1-DAG:       move    $4, $[[T5]]
+  ; 32R1-DAG:       sll     $[[T6:[0-9]+]], $[[T1]], 16
+  ; 32R1-DAG:       sra     $5, $[[T6]], 16
+  ; 32R1-DAG:       sll     $[[T7:[0-9]+]], $[[T2]], 16
+  ; 32R1-DAG:       sra     $6, $[[T7]], 16
+  ; 32R1:           lw      $[[T8:[0-9]+]], 16($sp)
+  ; 32R1:           sll     $[[T9:[0-9]+]], $[[T8]], 16
+  ; 32R1:           sra     $7, $[[T9]], 16
+
+  ; 32R2-DAG:       seh     $[[T4:[0-9]+]], $[[T0]]
+  ; 32R2-DAG:       sw      $4, 16($sp)
+  ; 32R2-DAG:       move    $4, $[[T4]]
+  ; 32R2-DAG:       seh     $5, $[[T1]]
+  ; 32R2-DAG:       seh     $6, $[[T2]]
+  ; 32R2-DAG:       lw      $[[T5:[0-9]+]], 16($sp)
+  ; 32R2:           seh     $7, $[[T5]]
+  call void @xhhhh(i16 88, i16 44, i16 11, i16 33)
   ret void
 }
 
-declare void @xfiii(float, i32, i32, i32) #1
+declare void @xiiii(i32, i32, i32, i32)
 
-; Function Attrs: nounwind
-define void @cxd() #0 {
-entry:
-; mips32r2-LABEL: cxd:
-; mips32-LABEL: cxd:
-  call void @xd(double 5.994560e+02)
-; mips32:       addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; mips32-DAG:   lui     $[[REG_FPCONST_1:[0-9]+]], 16514
-; mips32-DAG:   ori     $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037
-; mips32-DAG:   lui     $[[REG_FPCONST_3:[0-9]+]], 58195
-; mips32-DAG:   ori     $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439
-; mips32-DAG:    mtc1   $[[REG_FPCONST_4]], $f12
-; mips32-DAG:       mtc1        $[[REG_FPCONST_2]], $f13
-; mips32-DAG:   lw      $25, %got(xd)($[[REG_GP]])
-; mips32:       jalr    $25
-; mips32r2:     addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; mips32r2-DAG: lui     $[[REG_FPCONST_1:[0-9]+]], 16514
-; mips32r2-DAG: ori     $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037
-; mips32r2-DAG: lui     $[[REG_FPCONST_3:[0-9]+]], 58195
-; mips32r2-DAG: ori     $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439
-; mips32r2-DAG: mtc1    $[[REG_FPCONST_4]], $f12
-; mips32r2-DAG: mthc1   $[[REG_FPCONST_2]], $f12
-; mips32r2-DAG: lw      $25, %got(xd)($[[REG_GP]])
-; mips32r2 :    jalr    $25
+define void @cxiiii() {
+  ; ALL-LABEL:    cxiiii:
+
+  ; ALL-DAG:        addiu   $4, $zero, 167
+  ; ALL-DAG:        addiu   $5, $zero, 320
+  ; ALL-DAG:        addiu   $6, $zero, 97
+  ; ALL-DAG:        addiu   $7, $zero, 14
+  ; ALL-DAG:        lw      $25, %got(xiiii)(${{[0-9]+}})
+  ; ALL:            jalr    $25
+  call void @xiiii(i32 167, i32 320, i32 97, i32 14)
   ret void
 }
 
-declare void @xd(double) #1
+@c1 = global i8 -45, align 1
+@uc1 = global i8 27, align 1
+@s1 = global i16 -1789, align 2
+@us1 = global i16 1256, align 2
 
-; Function Attrs: nounwind
-define void @cxdd() #0 {
-; mips32r2-LABEL: cxdd:
-; mips32-LABEL: cxdd:
-entry:
-  call void @xdd(double 1.234980e+03, double 0x40F5B331F7CED917)
-; mips32:       addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; mips32-DAG:   lui     $[[REG_FPCONST_1:[0-9]+]], 16531
-; mips32-DAG:   ori     $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435
-; mips32-DAG:   lui     $[[REG_FPCONST_3:[0-9]+]], 34078
-; mips32-DAG:   ori     $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186
-; mips32-DAG:   mtc1    $[[REG_FPCONST_4]], $f12
-; mips32-DAG:   mtc1    $[[REG_FPCONST_2]], $f13
-; mips32-DAG:   lui     $[[REG_FPCONST_1:[0-9]+]], 16629
-; mips32-DAG:   ori     $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873
-; mips32-DAG:   lui     $[[REG_FPCONST_3:[0-9]+]], 63438
-; mips32-DAG:   ori     $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575
-; mips32-DAG:   mtc1    $[[REG_FPCONST_4]], $f14
-; mips32-DAG:   mtc1    $[[REG_FPCONST_2]], $f15
-; mips32-DAG:   lw      $25, %got(xdd)($[[REG_GP]])
-; mips32:       jalr    $25
-; mips32r2:     addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; mips32r2-DAG: lui     $[[REG_FPCONST_1:[0-9]+]], 16531
-; mips32r2-DAG: ori     $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435
-; mips32r2-DAG: lui     $[[REG_FPCONST_3:[0-9]+]], 34078
-; mips32r2-DAG: ori     $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186
-; mips32r2-DAG: mtc1    $[[REG_FPCONST_4]], $f12
-; mips32r2-DAG: mthc1   $[[REG_FPCONST_2]], $f12
-; mips32r2-DAG: lui     $[[REG_FPCONST_1:[0-9]+]], 16629
-; mips32r2-DAG: ori     $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873
-; mips32r2-DAG: lui     $[[REG_FPCONST_3:[0-9]+]], 63438
-; mips32r2-DAG: ori     $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575
-; mips32r2-DAG: mtc1    $[[REG_FPCONST_4]], $f14
-; mips32r2-DAG: mthc1   $[[REG_FPCONST_2]], $f14
-; mips32r2-DAG: lw      $25, %got(xdd)($[[REG_GP]])
-; mips32r2 :    jalr    $25
+define void @cxiiiiconv() {
+  ; ALL-LABEL:    cxiiiiconv:
+
+  ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL-DAG:        lw      $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])
+  ; ALL-DAG:        lbu     $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])
+  ; 32R1-DAG:       sll     $[[REG_C1_1:[0-9]+]], $[[REG_C1]], 24
+  ; 32R1-DAG:       sra     $4, $[[REG_C1_1]], 24
+  ; 32R2-DAG:       seb     $4, $[[REG_C1]]
+  ; FIXME: andi is superfulous
+  ; ALL-DAG:        lw      $[[REG_UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
+  ; ALL-DAG:        lbu     $[[REG_UC1:[0-9]+]], 0($[[REG_UC1_ADDR]])
+  ; ALL-DAG:        andi    $5, $[[REG_UC1]], 255
+  ; ALL-DAG:        lw      $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
+  ; ALL-DAG:        lhu     $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])
+  ; 32R1-DAG:       sll     $[[REG_S1_1:[0-9]+]], $[[REG_S1]], 16
+  ; 32R1-DAG:       sra     $6, $[[REG_S1_1]], 16
+  ; 32R2-DAG:       seh     $6, $[[REG_S1]]
+  ; FIXME andi is superfulous
+  ; ALL-DAG:        lw      $[[REG_US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
+  ; ALL-DAG:        lhu     $[[REG_US1:[0-9]+]], 0($[[REG_US1_ADDR]])
+  ; ALL-DAG:        andi    $7, $[[REG_US1]], 65535
+  ; ALL:            jalr    $25
+  %1 = load i8, i8* @c1, align 1
+  %conv = sext i8 %1 to i32
+  %2 = load i8, i8* @uc1, align 1
+  %conv1 = zext i8 %2 to i32
+  %3 = load i16, i16* @s1, align 2
+  %conv2 = sext i16 %3 to i32
+  %4 = load i16, i16* @us1, align 2
+  %conv3 = zext i16 %4 to i32
+  call void @xiiii(i32 %conv, i32 %conv1, i32 %conv2, i32 %conv3)
   ret void
 }
 
-declare void @xdd(double, double) #1
+declare void @xf(float)
 
-; Function Attrs: nounwind
-define void @cxif() #0 {
-entry:
-; CHECK-LABEL: cxif:
-  call void @xif(i32 345, float 0x407BCE5A20000000)
-; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; CHECK-DAG:    addiu   $4, $zero, 345
-; CHECK-DAG:    lui     $[[REGF_1:[0-9]+]], 17374
-; CHECK-DAG:    ori     $[[REGF_2:[0-9]+]], $[[REGF_1]], 29393
-; CHECK-DAG:    mtc1    $[[REGF_2]], $f[[REGF_3:[0-9]+]]
-; CHECK-DAG:    mfc1    $5, $f[[REGF_3]]
-; CHECK-DAG:    lw      $25, %got(xif)($[[REG_GP]])
-; CHECK:        jalr    $25
+define void @cxf() {
+  ; ALL-LABEL:    cxf:
 
+  ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL:            lui     $[[REG_FPCONST_1:[0-9]+]], 17886
+  ; ALL:            ori     $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 17067
+  ; ALL:            mtc1    $[[REG_FPCONST]], $f12
+  ; ALL:            lw      $25, %got(xf)($[[REG_GP]])
+  ; ALL:            jalr    $25
+  call void @xf(float 0x40BBC85560000000)
   ret void
 }
 
-declare void @xif(i32, float) #1
+declare void @xff(float, float)
 
-; Function Attrs: nounwind
-define void @cxiff() #0 {
-entry:
-; CHECK-LABEL: cxiff:
-; CHECK2-LABEL: cxiff:
-  call void @xiff(i32 12239, float 0x408EDB3340000000, float 0x4013FFE5C0000000)
-; We need to do the two floating point parameters in a separate
-; check because we can't control the ordering of parts of the sequence
-;;
-; CHECK:        addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; CHECK:        addiu   $4, $zero, 12239
-; CHECK2:       addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; CHECK2:       addiu   $4, $zero, 12239
-; CHECK:        lui     $[[REGF_1:[0-9]+]], 17526
-; CHECK:        ori     $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706
-; CHECK:        mtc1    $[[REGF_2]], $f[[REGF_3:[0-9]+]]
-; CHECK:        mfc1    $5, $f[[REGF_3]]
-; CHECK2:       lui     $[[REGF2_1:[0-9]+]], 16543
-; CHECK2:       ori     $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 65326
-; CHECK2:       mtc1    $[[REGF2_2]], $f[[REGF2_3:[0-9]+]]
-; CHECK2:       mfc1    $6, $f[[REGF2_3]]
-; CHECK:        lw      $25, %got(xiff)($[[REG_GP]])
-; CHECK2:       lw      $25, %got(xiff)($[[REG_GP]])
-; CHECK:        jalr    $25
-; CHECK2:       jalr    $25
+define void @cxff() {
+  ; ALL-LABEL:    cxff:
+
+  ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL-DAG:        lui     $[[REG_FPCONST_1:[0-9]+]], 16314
+  ; ALL-DAG:        ori     $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 21349
+  ; ALL-DAG:        mtc1    $[[REG_FPCONST]], $f12
+  ; ALL-DAG:        lui     $[[REG_FPCONST_2:[0-9]+]], 16593
+  ; ALL-DAG:        ori     $[[REG_FPCONST_3:[0-9]+]], $[[REG_FPCONST_2]], 24642
+  ; ALL-DAG:        mtc1    $[[REG_FPCONST_3]], $f14
+  ; ALL-DAG:        lw      $25, %got(xff)($[[REG_GP]])
+  ; ALL:            jalr    $25
+  call void @xff(float 0x3FF74A6CA0000000, float 0x401A2C0840000000)
   ret void
 }
 
-declare void @xiff(i32, float, float) #1
+declare void @xfi(float, i32)
 
-; Function Attrs: nounwind
-define void @cxifi() #0 {
-entry:
-; CHECK: cxifi:
-  call void @xifi(i32 887, float 0x402277CEE0000000, i32 888)
-; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; CHECK-DAG:    addiu   $4, $zero, 887
-; CHECK-DAG:    lui     $[[REGF_1:[0-9]+]], 16659
-; CHECK-DAG:    ori     $[[REGF_2:[0-9]+]], $[[REGF_1]], 48759
-; CHECK-DAG:    mtc1    $[[REGF_2]], $f[[REGF_3:[0-9]+]]
-; CHECK-DAG:    mfc1    $5, $f[[REGF_3]]
-; CHECk-DAG:    addiu   $6, $zero, 888
-; CHECK-DAG:    lw      $25, %got(xifi)($[[REG_GP]])
-; CHECK:        jalr    $25
+define void @cxfi() {
+  ; ALL-LABEL:    cxfi:
 
+  ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL-DAG:        lui     $[[REG_FPCONST_1:[0-9]+]], 16540
+  ; ALL-DAG:        ori     $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 33554
+  ; ALL-DAG:        mtc1    $[[REG_FPCONST]], $f12
+  ; ALL-DAG:        addiu   $5, $zero, 102
+  ; ALL-DAG:        lw      $25, %got(xfi)($[[REG_GP]])
+  ; ALL:            jalr    $25
+  call void @xfi(float 0x4013906240000000, i32 102)
   ret void
 }
 
-declare void @xifi(i32, float, i32) #1
-
-; Function Attrs: nounwind
-define void @cxifif() #0 {
-entry:
-; CHECK: cxifif:
-; CHECK2: cxifif:
-  call void @xifif(i32 67774, float 0x408EE0FBE0000000, i32 9991, float 0x40B15C8CC0000000)
-; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; CHECK-DAG:    lui     $[[REGI:[0-9]+]], 1
-; CHECK-DAG:    ori     $4, $[[REGI]], 2238
-; CHECK-DAG:    lui     $[[REGF_1:[0-9]+]], 17527
-; CHECK-DAG:    ori     $[[REGF_2:[0-9]+]], $[[REGF_1]], 2015
-; CHECK-DAG:    mtc1    $[[REGF_2]], $f[[REGF_3:[0-9]+]]
-; CHECK-DAG:    mfc1    $5, $f[[REGF_3]]
-; CHECk-DAG:    addiu   $6, $zero, 888
-; CHECK2:       lui     $[[REGF2_1:[0-9]+]], 17802
-; CHECK2:       ori     $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 58470
-; CHECK2:       mtc1    $[[REGF2_2]], $f[[REGF2_3:[0-9]+]]
-; CHECK2:       mfc1    $7, $f[[REGF2_3]]
-; CHECK:        lw      $25, %got(xifif)($[[REG_GP]])
-; CHECK2:       lw      $25, %got(xifif)($[[REG_GP]])
-; CHECK2:       jalr    $25
-; CHECK:        jalr    $25
+declare void @xfii(float, i32, i32)
 
+define void @cxfii() {
+  ; ALL-LABEL:    cxfii:
+
+  ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL-DAG:        lui     $[[REG_FPCONST_1:[0-9]+]], 17142
+  ; ALL-DAG:        ori     $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 16240
+  ; ALL-DAG:        mtc1    $[[REG_FPCONST]], $f12
+  ; ALL-DAG:        addiu   $5, $zero, 9993
+  ; ALL-DAG:        addiu   $6, $zero, 10922
+  ; ALL-DAG:        lw      $25, %got(xfii)($[[REG_GP]])
+  ; ALL:            jalr    $25
+  call void @xfii(float 0x405EC7EE00000000, i32 9993, i32 10922)
   ret void
 }
 
-declare void @xifif(i32, float, i32, float) #1
-
-; Function Attrs: nounwind
-define void @cxiffi() #0 {
-entry:
-; CHECK-label: cxiffi:
-; CHECK2-label: cxiffi:
-  call void @xiffi(i32 45, float 0x3FF6666660000000, float 0x408F333340000000, i32 234)
-; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; CHECK-DAG:    addiu   $4, $zero, 45
-; CHECK2-DAG:   addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; CHECK2-DAG:   addiu   $4, $zero, 45
-; CHECK-DAG:    lui     $[[REGF_1:[0-9]+]], 16307
-; CHECK-DAG:    ori     $[[REGF_2:[0-9]+]], $[[REGF_1]], 13107
-; CHECK-DAG:    mtc1    $[[REGF_2]], $f[[REGF_3:[0-9]+]]
-; CHECK-DAG:    mfc1    $5, $f[[REGF_3]]
-; CHECK2:       lui     $[[REGF2_1:[0-9]+]], 17529
-; CHECK2:       ori     $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 39322
-; CHECK2:       mtc1    $[[REGF2_2]], $f[[REGF2_3:[0-9]+]]
-; CHECK2:       mfc1    $6, $f[[REGF2_3]]
-; CHECK-DAG:    lw      $25, %got(xiffi)($[[REG_GP]])
-; CHECK-DAG:    addiu   $7, $zero, 234
-; CHECK2-DAG:   lw      $25, %got(xiffi)($[[REG_GP]])
-; CHECK:        jalr    $25
-; CHECK2:       jalr    $25
+declare void @xfiii(float, i32, i32, i32)
+
+define void @cxfiii() {
+  ; ALL-LABEL:    cxfiii:
+
+  ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL-DAG:        lui     $[[REG_FPCONST_1:[0-9]+]], 17120
+  ; ALL-DAG:        ori     $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 14681
+  ; ALL-DAG:        mtc1    $[[REG_FPCONST]], $f12
+  ; ALL-DAG:        addiu   $5, $zero, 3948
+  ; ALL-DAG:        lui     $[[REG_I_1:[0-9]+]], 1
+  ; ALL-DAG:        ori     $6, $[[REG_I_1]], 23475
+  ; ALL-DAG:        lui     $[[REG_I_2:[0-9]+]], 1
+  ; ALL-DAG:        ori     $7, $[[REG_I_2]], 45686
+  ; ALL-DAG:        lw      $25, %got(xfiii)($[[REG_GP]])
+  ; ALL:            jalr    $25
+  call void @xfiii(float 0x405C072B20000000, i32 3948, i32 89011, i32 111222)
+  ret void
+}
 
+declare void @xd(double)
+
+define void @cxd() {
+  ; ALL-LABEL:    cxd:
+
+  ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL-DAG:        lui     $[[REG_FPCONST_1:[0-9]+]], 16514
+  ; ALL-DAG:        ori     $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037
+  ; ALL-DAG:        lui     $[[REG_FPCONST_3:[0-9]+]], 58195
+  ; ALL-DAG:        ori     $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439
+  ; ALL-DAG:        mtc1    $[[REG_FPCONST_4]], $f12
+  ; 32R1-DAG:       mtc1    $[[REG_FPCONST_2]], $f13
+  ; 32R2-DAG:       mthc1   $[[REG_FPCONST_2]], $f12
+  ; ALL-DAG:        lw      $25, %got(xd)($[[REG_GP]])
+  ; ALL:            jalr    $25
+  call void @xd(double 5.994560e+02)
   ret void
 }
 
-declare void @xiffi(i32, float, float, i32) #1
+declare void @xdd(double, double)
+
+define void @cxdd() {
+  ; ALL-LABEL:    cxdd:
+
+  ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL-DAG:        lui     $[[REG_FPCONST_1:[0-9]+]], 16531
+  ; ALL-DAG:        ori     $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435
+  ; ALL-DAG:        lui     $[[REG_FPCONST_3:[0-9]+]], 34078
+  ; ALL-DAG:        ori     $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186
+  ; ALL-DAG:        mtc1    $[[REG_FPCONST_4]], $f12
+  ; 32R1-DAG:       mtc1    $[[REG_FPCONST_2]], $f13
+  ; 32R2-DAG:       mthc1   $[[REG_FPCONST_2]], $f12
+  ; ALL-DAG:        lui     $[[REG_FPCONST_1:[0-9]+]], 16629
+  ; ALL-DAG:        ori     $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873
+  ; ALL-DAG:        lui     $[[REG_FPCONST_3:[0-9]+]], 63438
+  ; ALL-DAG:        ori     $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575
+  ; ALL-DAG:        mtc1    $[[REG_FPCONST_4]], $f14
+  ; 32R1-DAG:       mtc1    $[[REG_FPCONST_2]], $f15
+  ; 32R2-DAG:       mthc1   $[[REG_FPCONST_2]], $f14
+  ; ALL-DAG:        lw      $25, %got(xdd)($[[REG_GP]])
+  ; ALL:            jalr    $25
+  call void @xdd(double 1.234980e+03, double 0x40F5B331F7CED917)
+  ret void
+}
 
-; Function Attrs: nounwind
-define void @cxifii() #0 {
-entry:
-; CHECK-DAG:    cxifii:
-  call void @xifii(i32 12239, float 0x408EDB3340000000, i32 998877, i32 1234)
-; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
-; CHECK-DAG:    addiu   $4, $zero, 12239
-; CHECK-DAG:    lui     $[[REGF_1:[0-9]+]], 17526
-; CHECK-DAG:    ori     $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706
-; CHECK-DAG:    mtc1    $[[REGF_2]], $f[[REGF_3:[0-9]+]]
-; CHECK-DAG:    mfc1    $5, $f[[REGF_3]]
-; CHECK-DAG:    lui     $[[REGI2:[0-9]+]], 15
-; CHECK-DAG:    ori     $6, $[[REGI2]], 15837
-; CHECk-DAG:    addiu   $7, $zero, 1234
-; CHECK-DAG:    lw      $25, %got(xifii)($[[REG_GP]])
-; CHECK:        jalr    $25
+declare void @xif(i32, float)
+
+define void @cxif() {
+  ; ALL-LABEL:    cxif:
+
+  ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL-DAG:        addiu   $4, $zero, 345
+  ; ALL-DAG:        lui     $[[REGF_1:[0-9]+]], 17374
+  ; ALL-DAG:        ori     $[[REGF_2:[0-9]+]], $[[REGF_1]], 29393
+  ; ALL-DAG:        mtc1    $[[REGF_2]], $f[[REGF_3:[0-9]+]]
+  ; ALL-DAG:        mfc1    $5, $f[[REGF_3]]
+  ; ALL-DAG:        lw      $25, %got(xif)($[[REG_GP]])
+  ; ALL:            jalr    $25
+  call void @xif(i32 345, float 0x407BCE5A20000000)
   ret void
 }
 
-declare void @xifii(i32, float, i32, i32) #1
-
-; FIXME: this function will not pass yet. 
-; Function Attrs: nounwind
-; define void @cxfid() #0 {
-;entry:
-;  call void @xfid(float 0x4013B851E0000000, i32 811123, double 0x40934BFF487FCB92)
-;  ret void
-;}
-
-declare void @xfid(float, i32, double) #1
-
-; Function Attrs: nounwind
-define void @g() #0 {
-entry:
-  call void @cxi()
-  call void @cxii()
-  call void @cxiii()
-  call void @cxiiii()
-  call void @cxiiiiconv()
-  call void @cxf()
-  call void @cxff()
-  call void @cxd()
-  call void @cxfi()
-  call void @cxfii()
-  call void @cxfiii()
-  call void @cxdd()
-  call void @cxif()
-  call void @cxiff()
-  call void @cxifi()
-  call void @cxifii()
-  call void @cxifif()
-  call void @cxiffi()
+declare void @xiff(i32, float, float)
+
+define void @cxiff() {
+  ; ALL-LABEL:    cxiff:
+
+  ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL-DAG:        addiu   $4, $zero, 12239
+  ; ALL-DAG:        lui     $[[REGF0_1:[0-9]+]], 17526
+  ; ALL-DAG:        ori     $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 55706
+  ; ALL-DAG:        mtc1    $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]
+  ; ALL-DAG:        lui     $[[REGF1_1:[0-9]+]], 16543
+  ; ALL-DAG:        ori     $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 65326
+  ; ALL:            mtc1    $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]
+  ; ALL-DAG:        mfc1    $5, $f[[REGF0_3]]
+  ; ALL-DAG:        mfc1    $6, $f[[REGF1_3]]
+  ; ALL-DAG:        lw      $25, %got(xiff)($[[REG_GP]])
+  ; ALL:            jalr    $25
+  call void @xiff(i32 12239, float 0x408EDB3340000000, float 0x4013FFE5C0000000)
   ret void
 }
 
+declare void @xifi(i32, float, i32)
 
-attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
-attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+define void @cxifi() {
+  ; ALL-LABEL:    cxifi:
 
-!llvm.ident = !{!0}
+  ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL-DAG:        addiu   $4, $zero, 887
+  ; ALL-DAG:        lui     $[[REGF_1:[0-9]+]], 16659
+  ; ALL-DAG:        ori     $[[REGF_2:[0-9]+]], $[[REGF_1]], 48759
+  ; ALL-DAG:        mtc1    $[[REGF_2]], $f[[REGF_3:[0-9]+]]
+  ; ALL-DAG:        mfc1    $5, $f[[REGF_3]]
+  ; ALL-DAG:        addiu   $6, $zero, 888
+  ; ALL-DAG:        lw      $25, %got(xifi)($[[REG_GP]])
+  ; ALL:            jalr    $25
+  call void @xifi(i32 887, float 0x402277CEE0000000, i32 888)
+  ret void
+}
 
-!0 = !{!"clang version 3.6.0 (gitosis@dmz-portal.mips.com:clang 43992fe7b17de5553ac06d323cb80cc6723a9ae3) (gitosis@dmz-portal.mips.com:llvm.git 0834e6839eb170197c81bb02e916258d1527e312)"}
+declare void @xifif(i32, float, i32, float)
+
+define void @cxifif() {
+  ; ALL-LABEL:    cxifif:
+
+  ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL-DAG:        lui     $[[REGI:[0-9]+]], 1
+  ; ALL-DAG:        ori     $4, $[[REGI]], 2238
+  ; ALL-DAG:        lui     $[[REGF0_1:[0-9]+]], 17527
+  ; ALL-DAG:        ori     $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 2015
+  ; ALL-DAG:        mtc1    $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]
+  ; ALL-DAG:        addiu   $6, $zero, 9991
+  ; ALL-DAG:        lui     $[[REGF1_1:[0-9]+]], 17802
+  ; ALL-DAG:        ori     $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 58470
+  ; ALL:            mtc1    $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]
+  ; ALL-DAG:        mfc1    $5, $f[[REGF0_3]]
+  ; ALL-DAG:        mfc1    $7, $f[[REGF1_3]]
+  ; ALL-DAG:        lw      $25, %got(xifif)($[[REG_GP]])
+  ; ALL:            jalr    $25
+  call void @xifif(i32 67774, float 0x408EE0FBE0000000,
+                   i32 9991, float 0x40B15C8CC0000000)
+  ret void
+}
+
+declare void @xiffi(i32, float, float, i32)
+
+define void @cxiffi() {
+  ; ALL-LABEL:    cxiffi:
+
+  ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL-DAG:        addiu   $4, $zero, 45
+  ; ALL-DAG:        lui     $[[REGF0_1:[0-9]+]], 16307
+  ; ALL-DAG:        ori     $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 13107
+  ; ALL-DAG:        mtc1    $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]
+  ; ALL-DAG:        lui     $[[REGF1_1:[0-9]+]], 17529
+  ; ALL-DAG:        ori     $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 39322
+  ; ALL:            mtc1    $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]
+  ; ALL-DAG:        addiu   $7, $zero, 234
+  ; ALL-DAG:        mfc1    $5, $f[[REGF0_3]]
+  ; ALL-DAG:        mfc1    $6, $f[[REGF1_3]]
+  ; ALL-DAG:        lw      $25, %got(xiffi)($[[REG_GP]])
+  ; ALL:            jalr    $25
+  call void @xiffi(i32 45, float 0x3FF6666660000000,
+                   float 0x408F333340000000, i32 234)
+  ret void
+}
+
+declare void @xifii(i32, float, i32, i32)
+
+define void @cxifii() {
+  ; ALL-LABEL:    cxifii:
+
+  ; ALL-DAG:    addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+  ; ALL-DAG:    addiu   $4, $zero, 12239
+  ; ALL-DAG:    lui     $[[REGF_1:[0-9]+]], 17526
+  ; ALL-DAG:    ori     $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706
+  ; ALL-DAG:    mtc1    $[[REGF_2]], $f[[REGF_3:[0-9]+]]
+  ; ALL-DAG:    mfc1    $5, $f[[REGF_3]]
+  ; ALL-DAG:    lui     $[[REGI2:[0-9]+]], 15
+  ; ALL-DAG:    ori     $6, $[[REGI2]], 15837
+  ; ALL-DAG:    addiu   $7, $zero, 1234
+  ; ALL-DAG:    lw      $25, %got(xifii)($[[REG_GP]])
+  ; ALL:        jalr    $25
+  call void @xifii(i32 12239, float 0x408EDB3340000000, i32 998877, i32 1234)
+  ret void
+}
diff --git a/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll b/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll
new file mode 100644
index 000000000000..df60d8071836
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic \
+; RUN:     -fast-isel=true -mips-fast-isel -fast-isel-abort=1 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic \
+; RUN:     -fast-isel=true -mips-fast-isel -fast-isel-abort=1 < %s | FileCheck %s
+
+@ARR = external global [10 x i32], align 4
+
+define void @foo() {
+; CHECK-LABEL: foo
+
+; CHECK-DAG:    lw      $[[ARR:[0-9]+]], %got(ARR)({{.*}})
+; CHECK-DAG:    addiu   $[[T0:[0-9]+]], $zero, 12345
+; CHECK:        sw      $[[T0]], 8($[[ARR]])
+
+entry:
+  store i32 12345, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ARR, i32 0, i32 2), align 4
+  ret void
+}
diff --git a/test/CodeGen/Mips/Fast-ISel/fastalloca.ll b/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
new file mode 100644
index 000000000000..b4a9f1ce7ab0
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
@@ -0,0 +1,32 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN:     < %s | FileCheck %s
+
+%struct.x = type { i32 }
+
+@i = common global i32 0, align 4
+
+define i32 @foobar(i32 signext %x) {
+entry:
+; CHECK-LABEL: foobar:
+  %retval = alloca i32, align 4
+  %x.addr = alloca i32, align 4
+  %a = alloca %struct.x, align 4
+  %c = alloca %struct.x*, align 4
+  store i32 %x, i32* %x.addr, align 4
+  %x1 = getelementptr inbounds %struct.x, %struct.x* %a, i32 0, i32 0
+  %0 = load i32, i32* %x.addr, align 4
+  store i32 %0, i32* %x1, align 4
+  store %struct.x* %a, %struct.x** %c, align 4
+  %1 = load %struct.x*, %struct.x** %c, align 4
+  %x2 = getelementptr inbounds %struct.x, %struct.x* %1, i32 0, i32 0
+  %2 = load i32, i32* %x2, align 4
+  store i32 %2, i32* @i, align 4
+  %3 = load i32, i32* %retval
+; CHECK-DAG:    lw      $[[I_ADDR:[0-9]+]], %got(i)($[[REG_GP:[0-9]+]])
+; CHECK-DAG:    addiu   $[[A_ADDR:[0-9]+]], $sp, 8
+; CHECK-DAG:    sw      $[[A_ADDR]], [[A_ADDR_FI:[0-9]+]]($sp)
+; CHECK-DAG:    lw      $[[A_ADDR2:[0-9]+]], [[A_ADDR_FI]]($sp)
+; CHECK-DAG:    lw      $[[A_X:[0-9]+]], 0($[[A_ADDR2]])
+; CHECK-DAG:    sw      $[[A_X]], 0($[[I_ADDR]])
+  ret i32 %3
+}
diff --git a/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll b/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
index c72b1e70c718..72de888b26e0 100644
--- a/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
+++ b/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @f1 = common global float 0.000000e+00, align 4
@@ -12,8 +12,8 @@
 ; Function Attrs: nounwind
 define void @feq1()  {
 entry:
-  %0 = load float* @f1, align 4
-  %1 = load float* @f2, align 4
+  %0 = load float, float* @f1, align 4
+  %1 = load float, float* @f2, align 4
   %cmp = fcmp oeq float %0, %1
 ; CHECK-LABEL:  feq1:
 ; CHECK-DAG:    lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
@@ -33,8 +33,8 @@ entry:
 ; Function Attrs: nounwind
 define void @fne1()  {
 entry:
-  %0 = load float* @f1, align 4
-  %1 = load float* @f2, align 4
+  %0 = load float, float* @f1, align 4
+  %1 = load float, float* @f2, align 4
   %cmp = fcmp une float %0, %1
 ; CHECK-LABEL:  fne1:
 ; CHECK-DAG:    lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
@@ -53,8 +53,8 @@ entry:
 ; Function Attrs: nounwind
 define void @flt1()  {
 entry:
-  %0 = load float* @f1, align 4
-  %1 = load float* @f2, align 4
+  %0 = load float, float* @f1, align 4
+  %1 = load float, float* @f2, align 4
   %cmp = fcmp olt float %0, %1
 ; CHECK-LABEL:  flt1:
 ; CHECK-DAG:    lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
@@ -74,8 +74,8 @@ entry:
 ; Function Attrs: nounwind
 define void @fgt1()  {
 entry:
-  %0 = load float* @f1, align 4
-  %1 = load float* @f2, align 4
+  %0 = load float, float* @f1, align 4
+  %1 = load float, float* @f2, align 4
   %cmp = fcmp ogt float %0, %1
 ; CHECK-LABEL: fgt1:
 ; CHECK-DAG:    lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
@@ -94,8 +94,8 @@ entry:
 ; Function Attrs: nounwind
 define void @fle1()  {
 entry:
-  %0 = load float* @f1, align 4
-  %1 = load float* @f2, align 4
+  %0 = load float, float* @f1, align 4
+  %1 = load float, float* @f2, align 4
   %cmp = fcmp ole float %0, %1
 ; CHECK-LABEL:  fle1:
 ; CHECK-DAG:    lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
@@ -114,8 +114,8 @@ entry:
 ; Function Attrs: nounwind
 define void @fge1()  {
 entry:
-  %0 = load float* @f1, align 4
-  %1 = load float* @f2, align 4
+  %0 = load float, float* @f1, align 4
+  %1 = load float, float* @f2, align 4
   %cmp = fcmp oge float %0, %1
 ; CHECK-LABEL:  fge1:
 ; CHECK-DAG:    lw      $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
@@ -134,8 +134,8 @@ entry:
 ; Function Attrs: nounwind
 define void @deq1()  {
 entry:
-  %0 = load double* @d1, align 8
-  %1 = load double* @d2, align 8
+  %0 = load double, double* @d1, align 8
+  %1 = load double, double* @d2, align 8
   %cmp = fcmp oeq double %0, %1
 ; CHECK-LABEL:  deq1:
 ; CHECK-DAG:    lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
@@ -154,8 +154,8 @@ entry:
 ; Function Attrs: nounwind
 define void @dne1()  {
 entry:
-  %0 = load double* @d1, align 8
-  %1 = load double* @d2, align 8
+  %0 = load double, double* @d1, align 8
+  %1 = load double, double* @d2, align 8
   %cmp = fcmp une double %0, %1
 ; CHECK-LABEL:  dne1:
 ; CHECK-DAG:    lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
@@ -174,8 +174,8 @@ entry:
 ; Function Attrs: nounwind
 define void @dlt1()  {
 entry:
-  %0 = load double* @d1, align 8
-  %1 = load double* @d2, align 8
+  %0 = load double, double* @d1, align 8
+  %1 = load double, double* @d2, align 8
   %cmp = fcmp olt double %0, %1
 ; CHECK-LABEL:  dlt1:
 ; CHECK-DAG:    lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
@@ -194,8 +194,8 @@ entry:
 ; Function Attrs: nounwind
 define void @dgt1()  {
 entry:
-  %0 = load double* @d1, align 8
-  %1 = load double* @d2, align 8
+  %0 = load double, double* @d1, align 8
+  %1 = load double, double* @d2, align 8
   %cmp = fcmp ogt double %0, %1
 ; CHECK-LABEL:  dgt1:
 ; CHECK-DAG:    lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
@@ -214,8 +214,8 @@ entry:
 ; Function Attrs: nounwind
 define void @dle1()  {
 entry:
-  %0 = load double* @d1, align 8
-  %1 = load double* @d2, align 8
+  %0 = load double, double* @d1, align 8
+  %1 = load double, double* @d2, align 8
   %cmp = fcmp ole double %0, %1
 ; CHECK-LABEL:  dle1:
 ; CHECK-DAG:    lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
@@ -234,8 +234,8 @@ entry:
 ; Function Attrs: nounwind
 define void @dge1()  {
 entry:
-  %0 = load double* @d1, align 8
-  %1 = load double* @d2, align 8
+  %0 = load double, double* @d1, align 8
+  %1 = load double, double* @d2, align 8
   %cmp = fcmp oge double %0, %1
 ; CHECK-LABEL:  dge1:
 ; CHECK-DAG:    lw      $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
diff --git a/test/CodeGen/Mips/Fast-ISel/fpext.ll b/test/CodeGen/Mips/Fast-ISel/fpext.ll
index 98aca756c58f..5ac22490ff02 100644
--- a/test/CodeGen/Mips/Fast-ISel/fpext.ll
+++ b/test/CodeGen/Mips/Fast-ISel/fpext.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @f = global float 0x40147E6B80000000, align 4
@@ -10,7 +10,7 @@
 ; Function Attrs: nounwind
 define void @dv() #0 {
 entry:
-  %0 = load float* @f, align 4
+  %0 = load float, float* @f, align 4
   %conv = fpext float %0 to double
 ; CHECK: cvt.d.s  $f{{[0-9]+}}, $f{{[0-9]+}}
   store double %conv, double* @d_f, align 8
diff --git a/test/CodeGen/Mips/Fast-ISel/fpintconv.ll b/test/CodeGen/Mips/Fast-ISel/fpintconv.ll
index 846726a868b3..a94ef5081539 100644
--- a/test/CodeGen/Mips/Fast-ISel/fpintconv.ll
+++ b/test/CodeGen/Mips/Fast-ISel/fpintconv.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 
@@ -14,7 +14,7 @@
 define void @ifv() {
 entry:
 ; CHECK-LABEL:   .ent  ifv
-  %0 = load float* @f, align 4
+  %0 = load float, float* @f, align 4
   %conv = fptosi float %0 to i32
 ; CHECK:   trunc.w.s  $f[[REG:[0-9]+]], $f{{[0-9]+}}
 ; CHECK:   mfc1	${{[0-9]+}}, $f[[REG]]
@@ -26,7 +26,7 @@ entry:
 define void @idv() {
 entry:
 ; CHECK-LABEL:   .ent  idv
-  %0 = load double* @d, align 8
+  %0 = load double, double* @d, align 8
   %conv = fptosi double %0 to i32
 ; CHECK:   trunc.w.d  $f[[REG:[0-9]+]], $f{{[0-9]+}}
 ; CHECK:   mfc1	${{[0-9]+}}, $f[[REG]]
diff --git a/test/CodeGen/Mips/Fast-ISel/fptrunc.ll b/test/CodeGen/Mips/Fast-ISel/fptrunc.ll
index d843dee5a8c9..2eec4c3ef547 100644
--- a/test/CodeGen/Mips/Fast-ISel/fptrunc.ll
+++ b/test/CodeGen/Mips/Fast-ISel/fptrunc.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @d = global double 0x40147E6B74DF0446, align 8
@@ -10,7 +10,7 @@
 ; Function Attrs: nounwind
 define void @fv() #0 {
 entry:
-  %0 = load double* @d, align 8
+  %0 = load double, double* @d, align 8
   %conv = fptrunc double %0 to float
 ; CHECK: cvt.s.d  $f{{[0-9]+}}, $f{{[0-9]+}}
   store float %conv, float* @f, align 4
diff --git a/test/CodeGen/Mips/Fast-ISel/icmpa.ll b/test/CodeGen/Mips/Fast-ISel/icmpa.ll
index bd41a2911dc4..670a8d5cfb4e 100644
--- a/test/CodeGen/Mips/Fast-ISel/icmpa.ll
+++ b/test/CodeGen/Mips/Fast-ISel/icmpa.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @c = global i32 4, align 4
@@ -14,8 +14,8 @@ define void @eq()  {
 entry:
 ; CHECK-LABEL:  .ent  eq
 
-  %0 = load i32* @c, align 4
-  %1 = load i32* @d, align 4
+  %0 = load i32, i32* @c, align 4
+  %1 = load i32, i32* @d, align 4
   %cmp = icmp eq i32 %0, %1
   %conv = zext i1 %cmp to i32
 ; CHECK-DAG:  lw	$[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
@@ -35,8 +35,8 @@ entry:
 define void @ne()  {
 entry:
 ; CHECK-LABEL:  .ent  ne
-  %0 = load i32* @c, align 4
-  %1 = load i32* @d, align 4
+  %0 = load i32, i32* @c, align 4
+  %1 = load i32, i32* @d, align 4
   %cmp = icmp ne i32 %0, %1
   %conv = zext i1 %cmp to i32
 ; CHECK-DAG:  lw	$[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
@@ -56,8 +56,8 @@ entry:
 define void @ugt()  {
 entry:
 ; CHECK-LABEL:  .ent  ugt
-  %0 = load i32* @uc, align 4
-  %1 = load i32* @ud, align 4
+  %0 = load i32, i32* @uc, align 4
+  %1 = load i32, i32* @ud, align 4
   %cmp = icmp ugt i32 %0, %1
   %conv = zext i1 %cmp to i32
 ; CHECK-DAG:  lw	$[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
@@ -76,8 +76,8 @@ entry:
 define void @ult()  {
 entry:
 ; CHECK-LABEL:  .ent  ult
-  %0 = load i32* @uc, align 4
-  %1 = load i32* @ud, align 4
+  %0 = load i32, i32* @uc, align 4
+  %1 = load i32, i32* @ud, align 4
   %cmp = icmp ult i32 %0, %1
   %conv = zext i1 %cmp to i32
 ; CHECK-DAG:  lw	$[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
@@ -95,8 +95,8 @@ entry:
 define void @uge()  {
 entry:
 ; CHECK-LABEL:  .ent  uge
-  %0 = load i32* @uc, align 4
-  %1 = load i32* @ud, align 4
+  %0 = load i32, i32* @uc, align 4
+  %1 = load i32, i32* @ud, align 4
   %cmp = icmp uge i32 %0, %1
   %conv = zext i1 %cmp to i32
 ; CHECK-DAG:  lw	$[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
@@ -115,8 +115,8 @@ entry:
 define void @ule()  {
 entry:
 ; CHECK-LABEL:  .ent  ule
-  %0 = load i32* @uc, align 4
-  %1 = load i32* @ud, align 4
+  %0 = load i32, i32* @uc, align 4
+  %1 = load i32, i32* @ud, align 4
   %cmp = icmp ule i32 %0, %1
   %conv = zext i1 %cmp to i32
 ; CHECK-DAG:  lw	$[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
@@ -135,8 +135,8 @@ entry:
 define void @sgt()  {
 entry:
 ; CHECK-LABEL:  .ent sgt
-  %0 = load i32* @c, align 4
-  %1 = load i32* @d, align 4
+  %0 = load i32, i32* @c, align 4
+  %1 = load i32, i32* @d, align 4
   %cmp = icmp sgt i32 %0, %1
   %conv = zext i1 %cmp to i32
 ; CHECK-DAG:  lw	$[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
@@ -154,8 +154,8 @@ entry:
 define void @slt()  {
 entry:
 ; CHECK-LABEL:  .ent slt
-  %0 = load i32* @c, align 4
-  %1 = load i32* @d, align 4
+  %0 = load i32, i32* @c, align 4
+  %1 = load i32, i32* @d, align 4
   %cmp = icmp slt i32 %0, %1
   %conv = zext i1 %cmp to i32
 ; CHECK-DAG:  lw	$[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
@@ -173,8 +173,8 @@ entry:
 define void @sge()  {
 entry:
 ; CHECK-LABEL:  .ent sge
-  %0 = load i32* @c, align 4
-  %1 = load i32* @d, align 4
+  %0 = load i32, i32* @c, align 4
+  %1 = load i32, i32* @d, align 4
   %cmp = icmp sge i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @b1, align 4
@@ -193,8 +193,8 @@ entry:
 define void @sle()  {
 entry:
 ; CHECK-LABEL:  .ent sle
-  %0 = load i32* @c, align 4
-  %1 = load i32* @d, align 4
+  %0 = load i32, i32* @c, align 4
+  %1 = load i32, i32* @d, align 4
   %cmp = icmp sle i32 %0, %1
   %conv = zext i1 %cmp to i32
 ; CHECK-DAG:  lw	$[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
diff --git a/test/CodeGen/Mips/Fast-ISel/loadstore2.ll b/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
index d84478b9c5a9..3daf03d681cb 100644
--- a/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
+++ b/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
@@ -4,9 +4,9 @@ target triple = "mips--linux-gnu"
 
 @c2 = common global i8 0, align 1
 @c1 = common global i8 0, align 1
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @s2 = common global i16 0, align 2
@@ -21,7 +21,7 @@ target triple = "mips--linux-gnu"
 ; Function Attrs: nounwind
 define void @cfoo() #0 {
 entry:
-  %0 = load i8* @c2, align 1
+  %0 = load i8, i8* @c2, align 1
   store i8 %0, i8* @c1, align 1
 ; CHECK-LABEL:	cfoo:
 ; CHECK:	lbu	$[[REGc:[0-9]+]], 0(${{[0-9]+}})
@@ -34,7 +34,7 @@ entry:
 ; Function Attrs: nounwind
 define void @sfoo() #0 {
 entry:
-  %0 = load i16* @s2, align 2
+  %0 = load i16, i16* @s2, align 2
   store i16 %0, i16* @s1, align 2
 ; CHECK-LABEL:	sfoo:
 ; CHECK:	lhu	$[[REGs:[0-9]+]], 0(${{[0-9]+}})
@@ -46,7 +46,7 @@ entry:
 ; Function Attrs: nounwind
 define void @ifoo() #0 {
 entry:
-  %0 = load i32* @i2, align 4
+  %0 = load i32, i32* @i2, align 4
   store i32 %0, i32* @i1, align 4
 ; CHECK-LABEL:	ifoo:
 ; CHECK:	lw	$[[REGi:[0-9]+]], 0(${{[0-9]+}})
@@ -58,7 +58,7 @@ entry:
 ; Function Attrs: nounwind
 define void @ffoo() #0 {
 entry:
-  %0 = load float* @f2, align 4
+  %0 = load float, float* @f2, align 4
   store float %0, float* @f1, align 4
 ; CHECK-LABEL:	ffoo:
 ; CHECK:	lwc1	$f[[REGf:[0-9]+]], 0(${{[0-9]+}})
@@ -71,7 +71,7 @@ entry:
 ; Function Attrs: nounwind
 define void @dfoo() #0 {
 entry:
-  %0 = load double* @d2, align 8
+  %0 = load double, double* @d2, align 8
   store double %0, double* @d1, align 8
 ; CHECK-LABEL:        dfoo:
 ; CHECK:        ldc1    $f[[REGd:[0-9]+]], 0(${{[0-9]+}})
diff --git a/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll b/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
index f7f2c6481b3c..acba132b28e1 100644
--- a/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
+++ b/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
@@ -1,10 +1,10 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s -check-prefix=mips32r2
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s -check-prefix=mips32
 
 @b2 = global i8 0, align 1
@@ -28,11 +28,11 @@
 define void @_Z3b_iv()  {
 entry:
 ; CHECK-LABEL:   .ent  _Z3b_iv
-  %0 = load i8* @b1, align 1
+  %0 = load i8, i8* @b1, align 1
   %tobool = trunc i8 %0 to i1
   %frombool = zext i1 %tobool to i8
   store i8 %frombool, i8* @b2, align 1
-  %1 = load i8* @b2, align 1
+  %1 = load i8, i8* @b2, align 1
   %tobool1 = trunc i8 %1 to i1
   %conv = zext i1 %tobool1 to i32
   store i32 %conv, i32* @i, align 4
@@ -51,10 +51,10 @@ define void @_Z4uc_iv()  {
 entry:
 ; CHECK-LABEL:  .ent  _Z4uc_iv
 
-  %0 = load i8* @uc1, align 1
+  %0 = load i8, i8* @uc1, align 1
   %conv = zext i8 %0 to i32
   store i32 %conv, i32* @i, align 4
-  %1 = load i8* @uc2, align 1
+  %1 = load i8, i8* @uc2, align 1
   %conv1 = zext i8 %1 to i32
 ; CHECK:   lbu  $[[REG1:[0-9]+]], 0(${{[0-9]+}})
 ; CHECK:  andi  ${{[0-9]+}}, $[[REG1]], 255
@@ -71,10 +71,10 @@ entry:
 ; mips32r2-LABEL:  .ent  _Z4sc_iv
 ; mips32-LABEL:  .ent  _Z4sc_iv
 
-  %0 = load i8* @sc1, align 1
+  %0 = load i8, i8* @sc1, align 1
   %conv = sext i8 %0 to i32
   store i32 %conv, i32* @i, align 4
-  %1 = load i8* @sc2, align 1
+  %1 = load i8, i8* @sc2, align 1
   %conv1 = sext i8 %1 to i32
   store i32 %conv1, i32* @j, align 4
 ; mips32r2:  lbu  $[[REG1:[0-9]+]], 0(${{[0-9]+}})
@@ -91,10 +91,10 @@ entry:
 define void @_Z4us_iv()  {
 entry:
 ; CHECK-LABEL:  .ent  _Z4us_iv
-  %0 = load i16* @us1, align 2
+  %0 = load i16, i16* @us1, align 2
   %conv = zext i16 %0 to i32
   store i32 %conv, i32* @i, align 4
-  %1 = load i16* @us2, align 2
+  %1 = load i16, i16* @us2, align 2
   %conv1 = zext i16 %1 to i32
   store i32 %conv1, i32* @j, align 4
   ret void
@@ -109,10 +109,10 @@ entry:
 ; mips32r2-LABEL:  .ent  _Z4ss_iv
 ; mips32=LABEL:  .ent  _Z4ss_iv
 
-  %0 = load i16* @ss1, align 2
+  %0 = load i16, i16* @ss1, align 2
   %conv = sext i16 %0 to i32
   store i32 %conv, i32* @i, align 4
-  %1 = load i16* @ss2, align 2
+  %1 = load i16, i16* @ss2, align 2
   %conv1 = sext i16 %1 to i32
   store i32 %conv1, i32* @j, align 4
 ; mips32r2:  lhu  $[[REG1:[0-9]+]], 0(${{[0-9]+}})
@@ -129,7 +129,7 @@ entry:
 define void @_Z4b_ssv()  {
 entry:
 ; CHECK-LABEL:  .ent  _Z4b_ssv
-  %0 = load i8* @b2, align 1
+  %0 = load i8, i8* @b2, align 1
   %tobool = trunc i8 %0 to i1
   %conv = zext i1 %tobool to i16
   store i16 %conv, i16* @ssi, align 2
@@ -143,10 +143,10 @@ entry:
 define void @_Z5uc_ssv()  {
 entry:
 ; CHECK-LABEL:  .ent  _Z5uc_ssv
-  %0 = load i8* @uc1, align 1
+  %0 = load i8, i8* @uc1, align 1
   %conv = zext i8 %0 to i16
   store i16 %conv, i16* @ssi, align 2
-  %1 = load i8* @uc2, align 1
+  %1 = load i8, i8* @uc2, align 1
   %conv1 = zext i8 %1 to i16
 ; CHECK:   lbu  $[[REG1:[0-9]+]], 0(${{[0-9]+}})
 ; CHECK:  andi  ${{[0-9]+}}, $[[REG1]], 255
@@ -161,10 +161,10 @@ define void @_Z5sc_ssv()  {
 entry:
 ; mips32r2-LABEL:  .ent  _Z5sc_ssv
 ; mips32-LABEL:  .ent  _Z5sc_ssv
-  %0 = load i8* @sc1, align 1
+  %0 = load i8, i8* @sc1, align 1
   %conv = sext i8 %0 to i16
   store i16 %conv, i16* @ssi, align 2
-  %1 = load i8* @sc2, align 1
+  %1 = load i8, i8* @sc2, align 1
   %conv1 = sext i8 %1 to i16
   store i16 %conv1, i16* @ssj, align 2
 ; mips32r2:  lbu  $[[REG1:[0-9]+]], 0(${{[0-9]+}})
diff --git a/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll b/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
index 93cf4c15a2f5..9f644ecd1875 100644
--- a/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
+++ b/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1
@@ -9,7 +9,7 @@
 ; Function Attrs: nounwind
 define void @foo() #0 {
 entry:
-  store i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), i8** @s, align 4
+  store i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), i8** @s, align 4
   ret void
 ; CHECK:        .ent    foo
 ; CHECK:        lw      $[[REG1:[0-9]+]], %got($.str)(${{[0-9]+}})
diff --git a/test/CodeGen/Mips/Fast-ISel/logopm.ll b/test/CodeGen/Mips/Fast-ISel/logopm.ll
new file mode 100644
index 000000000000..0f0c3bf9e1dc
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/logopm.ll
@@ -0,0 +1,606 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s
+
+@ub1 = common global i8 0, align 1
+@ub2 = common global i8 0, align 1
+@ub3 = common global i8 0, align 1
+@uc1 = common global i8 0, align 1
+@uc2 = common global i8 0, align 1
+@uc3 = common global i8 0, align 1
+@us1 = common global i16 0, align 2
+@us2 = common global i16 0, align 2
+@us3 = common global i16 0, align 2
+@ub = common global i8 0, align 1
+@uc = common global i8 0, align 1
+@us = common global i16 0, align 2
+@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1
+@ui = common global i32 0, align 4
+@ui1 = common global i32 0, align 4
+@ui2 = common global i32 0, align 4
+@ui3 = common global i32 0, align 4
+
+; Function Attrs: noinline nounwind
+define void @andUb() #0 {
+entry:
+  %0 = load i8, i8* @ub1, align 1
+  %1 = load i8, i8* @ub2, align 1
+  %conv0 = trunc i8 %0 to i1
+  %conv1 = trunc i8 %1 to i1
+  %and0 = and i1 %conv1, %conv0
+  %conv3 = zext i1 %and0 to i8
+  store i8 %conv3, i8* @ub, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    andUb
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
+; CHECK-DAG:    lbu     $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
+; CHECK-DAG:    and     $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
+; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @andUb0() #0 {
+entry:
+  %0 = load i8, i8* @ub1, align 1, !tbaa !2
+  %conv = trunc i8 %0 to i1
+  %and = and i1 %conv, 0
+  %conv1 = zext i1 %and to i8
+  store i8 %conv1, i8* @ub, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    andUb0
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
+; CHECK-DAG:    and     $[[RES1:[0-9]+]], $[[UB1]], $zero
+; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
+; CHECK:        .end    andUb0
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @andUb1() #0 {
+; clang uses i8 constants for booleans, so we test with an i8 1.
+entry:
+  %x = load i8, i8* @ub1, align 1, !tbaa !2
+  %and = and i8 %x, 1
+  %conv = trunc i8 %and to i1
+  %conv1 = zext i1 %conv to i8
+  store i8 %conv1, i8* @ub, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    andUb1
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
+; CHECK-DAG:    addiu   $[[CONST:[0-9]+]], $zero, 1
+; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
+; CHECK-DAG:    and     $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
+; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
+; CHECK:        .end    andUb1
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @orUb() #0 {
+entry:
+  %0 = load i8, i8* @ub1, align 1
+  %1 = load i8, i8* @ub2, align 1
+  %conv0 = trunc i8 %0 to i1
+  %conv1 = trunc i8 %1 to i1
+  %or0 = or i1 %conv1, %conv0
+  %conv3 = zext i1 %or0 to i8
+  store i8 %conv3, i8* @ub, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    orUb
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
+; CHECK-DAG:    lbu     $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
+; CHECK-DAG:    or      $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
+; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @orUb0() #0 {
+entry:
+  %0 = load i8, i8* @ub1, align 1, !tbaa !2
+  %conv = trunc i8 %0 to i1
+  %or = or i1 %conv, 0
+  %conv1 = zext i1 %or to i8
+  store i8 %conv1, i8* @ub, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    orUb0
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
+; CHECK:        andi    $[[RES:[0-9]+]], $[[UB1]], 1
+; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
+; CHECK:        .end    orUb0
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @orUb1() #0 {
+entry:
+  %x = load i8, i8* @ub1, align 1, !tbaa !2
+  %or = or i8 %x, 1
+  %conv = trunc i8 %or to i1
+  %conv1 = zext i1 %conv to i8
+  store i8 %conv1, i8* @ub, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    orUb1
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
+; CHECK-DAG:    addiu   $[[CONST:[0-9]+]], $zero, 1
+; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
+; CHECK-DAG:    or      $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
+; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
+; CHECK:        .end    orUb1
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @xorUb() #0 {
+entry:
+  %0 = load i8, i8* @ub1, align 1
+  %1 = load i8, i8* @ub2, align 1
+  %conv0 = trunc i8 %0 to i1
+  %conv1 = trunc i8 %1 to i1
+  %xor0 = xor i1 %conv1, %conv0
+  %conv3 = zext i1 %xor0 to i8
+  store i8 %conv3, i8* @ub, align 1, !tbaa !2
+; CHECK-LABEL: .ent    xorUb
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
+; CHECK-DAG:    lbu     $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
+; CHECK-DAG:    xor     $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
+; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @xorUb0() #0 {
+entry:
+  %0 = load i8, i8* @ub1, align 1, !tbaa !2
+  %conv = trunc i8 %0 to i1
+  %xor = xor i1 %conv, 0
+  %conv1 = zext i1 %xor to i8
+  store i8 %conv1, i8* @ub, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    xorUb0
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
+; CHECK-DAG:    xor     $[[RES1:[0-9]+]], $[[UB1]], $zero
+; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
+; CHECK:        .end    xorUb0
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @xorUb1() #0 {
+entry:
+  %x = load i8, i8* @ub1, align 1, !tbaa !2
+  %xor = xor i8 1, %x
+  %conv = trunc i8 %xor to i1
+  %conv1 = zext i1 %conv to i8
+  store i8 %conv1, i8* @ub, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    xorUb1
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
+; CHECK-DAG:    addiu   $[[CONST:[0-9]+]], $zero, 1
+; CHECK-DAG:    lw      $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
+; CHECK-DAG:    xor     $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
+; CHECK:        andi    $[[RES:[0-9]+]], $[[RES1]], 1
+; CHECK:        sb      $[[RES]], 0($[[UB_ADDR]])
+; CHECK:        .end    xorUb1
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @andUc() #0 {
+entry:
+  %0 = load i8, i8* @uc1, align 1, !tbaa !2
+  %1 = load i8, i8* @uc2, align 1, !tbaa !2
+  %and3 = and i8 %1, %0
+  store i8 %and3, i8* @uc, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    andUc
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
+; CHECK-DAG:    lbu     $[[UC2:[0-9]+]], 0($[[UC2_ADDR]])
+; CHECK-DAG:    and     $[[RES:[0-9]+]], $[[UC2]], $[[UB1]]
+; CHECK:        sb      $[[RES]], 0($[[UC_ADDR]])
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @andUc0() #0 {
+entry:
+  %0 = load i8, i8* @uc1, align 1, !tbaa !2
+  %and = and i8 %0, 67
+  store i8 %and, i8* @uc, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    andUc0
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
+; CHECK-DAG:    addiu   $[[CONST_67:[0-9]+]], $zero, 67
+; CHECK-DAG:    and     $[[RES:[0-9]+]], $[[UC1]], $[[CONST_67]]
+; CHECK:        sb      $[[RES]], 0($[[UC_ADDR]])
+; CHECK:        .end    andUc0
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @andUc1() #0 {
+entry:
+  %0 = load i8, i8* @uc1, align 1, !tbaa !2
+  %and = and i8 %0, 167
+  store i8 %and, i8* @uc, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    andUc1
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
+; CHECK-DAG:    addiu   $[[CONST_Neg89:[0-9]+]], $zero, -89
+; CHECK-DAG:    and     $[[RES:[0-9]+]], $[[UC1]], $[[CONST_Neg89]]
+; CHECK:        sb      $[[RES]], 0($[[UC_ADDR]])
+; CHECK:        .end    andUc1
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @orUc() #0 {
+entry:
+  %0 = load i8, i8* @uc1, align 1, !tbaa !2
+  %1 = load i8, i8* @uc2, align 1, !tbaa !2
+  %or3 = or i8 %1, %0
+  store i8 %or3, i8* @uc, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    orUc
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
+; CHECK-DAG:    lbu     $[[UC2:[0-9]+]], 0($[[UC2_ADDR]])
+; CHECK-DAG:    or      $[[RES:[0-9]+]], $[[UC2]], $[[UC1]]
+; CHECK:        sb      $[[RES]], 0($[[UC_ADDR]])
+; CHECK:        .end    orUc
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @orUc0() #0 {
+entry:
+  %0 = load i8, i8* @uc1, align 1, !tbaa !2
+   %or = or i8 %0, 69
+  store i8 %or, i8* @uc, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    orUc0
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
+; CHECK-DAG:    addiu   $[[CONST_69:[0-9]+]], $zero, 69
+; CHECK-DAG:    or      $[[RES:[0-9]+]], $[[UC1]], $[[CONST_69]]
+; CHECK:        sb      $[[RES]], 0($[[UC_ADDR]])
+; CHECK:        .end    orUc0
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @orUc1() #0 {
+entry:
+  %0 = load i8, i8* @uc1, align 1, !tbaa !2
+  %or = or i8 %0, 238
+  store i8 %or, i8* @uc, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    orUc1
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
+; CHECK-DAG:    addiu   $[[CONST_neg18:[0-9]+]], $zero, -18
+; CHECK-DAG:    or      $[[RES:[0-9]+]], $[[UC1]], $[[CONST_neg18]]
+; CHECK:        sb      $[[RES]], 0($[[UC_ADDR]])
+; CHECK:        .end    orUc1
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @xorUc() #0 {
+entry:
+  %0 = load i8, i8* @uc1, align 1, !tbaa !2
+  %1 = load i8, i8* @uc2, align 1, !tbaa !2
+  %xor3 = xor i8 %1, %0
+  store i8 %xor3, i8* @uc, align 1, !tbaa !2
+; CHECK-LABEL: .ent    xorUc
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
+; CHECK-DAG:    lbu     $[[UC2:[0-9]+]], 0($[[UC2_ADDR]])
+; CHECK-DAG:    xor     $[[RES:[0-9]+]], $[[UC2]], $[[UC1]]
+; CHECK:        sb      $[[RES]], 0($[[UC_ADDR]])
+; CHECK:        .end    xorUc
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @xorUc0() #0 {
+entry:
+  %0 = load i8, i8* @uc1, align 1, !tbaa !2
+  %xor = xor i8 %0, 23
+  store i8 %xor, i8* @uc, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    xorUc0
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
+; CHECK-DAG:    addiu   $[[CONST_23:[0-9]+]], $zero, 23
+; CHECK-DAG:    xor     $[[RES:[0-9]+]], $[[UC1]], $[[CONST_23]]
+; CHECK:        sb      $[[RES]], 0($[[UC_ADDR]])
+; CHECK:        .end    xorUc0
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @xorUc1() #0 {
+entry:
+  %0 = load i8, i8* @uc1, align 1, !tbaa !2
+  %xor = xor i8 %0, 120
+  store i8 %xor, i8* @uc, align 1, !tbaa !2
+; CHECK-LABEL:  .ent    xorUc1
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
+; CHECK-DAG:    lbu     $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
+; CHECK-DAG:    addiu   $[[CONST_120:[0-9]+]], $zero, 120
+; CHECK-DAG:    xor     $[[RES:[0-9]+]], $[[UC1]], $[[CONST_120]]
+; CHECK:        sb      $[[RES]], 0($[[UC_ADDR]])
+; CHECK:        .end    xorUc1
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @andUs() #0 {
+entry:
+  %0 = load i16, i16* @us1, align 2, !tbaa !5
+  %1 = load i16, i16* @us2, align 2, !tbaa !5
+  %and3 = and i16 %1, %0
+  store i16 %and3, i16* @us, align 2, !tbaa !5
+; CHECK-LABEL:  .ent    andUs
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
+; CHECK-DAG:    lhu     $[[US1:[0-9]+]], 0($[[US1_ADDR]])
+; CHECK-DAG:    lhu     $[[US2:[0-9]+]], 0($[[US2_ADDR]])
+; CHECK-DAG:    and     $[[RES:[0-9]+]], $[[US2]], $[[UB1]]
+; CHECK:        sh      $[[RES]], 0($[[US_ADDR]])
+; CHECK:        .end andUs
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @andUs0() #0 {
+entry:
+  %0 = load i16, i16* @us1, align 2, !tbaa !5
+  %and = and i16 %0, 4660
+  store i16 %and, i16* @us, align 2, !tbaa !5
+; CHECK-LABEL: .ent    andUs0
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
+; CHECK-DAG:    lhu     $[[US1:[0-9]+]], 0($[[US1_ADDR]])
+; CHECK-DAG:    addiu   $[[CONST_4660:[0-9]+]], $zero, 4660
+; CHECK-DAG:    and     $[[RES:[0-9]+]], $[[US1]], $[[CONST_4660]]
+; CHECK:        sh      $[[RES]], 0($[[US_ADDR]])
+; CHECK:        .end    andUs0
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @andUs1() #0 {
+entry:
+  %0 = load i16, i16* @us1, align 2, !tbaa !5
+  %and = and i16 %0, 61351
+  store i16 %and, i16* @us, align 2, !tbaa !5
+; CHECK-LABEL:  .ent    andUs1
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
+; CHECK-DAG:    lhu     $[[US1:[0-9]+]], 0($[[US1_ADDR]])
+; CHECK-DAG:    addiu   $[[CONST_Neg4185:[0-9]+]], $zero, -4185
+; CHECK-DAG:    and     $[[RES:[0-9]+]], $[[US1]], $[[CONST_Neg4185]]
+; CHECK:        sh      $[[RES]], 0($[[US_ADDR]])
+; CHECK:        .end    andUs1
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @orUs() #0 {
+entry:
+  %0 = load i16, i16* @us1, align 2, !tbaa !5
+  %1 = load i16, i16* @us2, align 2, !tbaa !5
+  %or3 = or i16 %1, %0
+  store i16 %or3, i16* @us, align 2, !tbaa !5
+; CHECK-LABEL:  .ent    orUs
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
+; CHECK-DAG:    lhu     $[[US1:[0-9]+]], 0($[[US1_ADDR]])
+; CHECK-DAG:    lhu     $[[US2:[0-9]+]], 0($[[US2_ADDR]])
+; CHECK-DAG:    or      $[[RES:[0-9]+]], $[[US2]], $[[US1]]
+; CHECK:        sh      $[[RES]], 0($[[US_ADDR]])
+; CHECK:        .end    orUs
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @orUs0() #0 {
+entry:
+  %0 = load i16, i16* @us1, align 2, !tbaa !5
+  %or = or i16 %0, 17666
+  store i16 %or, i16* @us, align 2, !tbaa !5
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @orUs1() #0 {
+entry:
+  %0 = load i16, i16* @us1, align 2, !tbaa !5
+  %or = or i16 %0, 60945
+  store i16 %or, i16* @us, align 2, !tbaa !5
+; CHECK-LABEL:  .ent    orUs1
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
+; CHECK-DAG:    lhu     $[[US1:[0-9]+]], 0($[[US1_ADDR]])
+; CHECK-DAG:    addiu   $[[CONST_neg4591:[0-9]+]], $zero, -4591
+; CHECK-DAG:    or      $[[RES:[0-9]+]], $[[US1]], $[[CONST_neg4591]]
+; CHECK:        sh      $[[RES]], 0($[[US_ADDR]])
+; CHECK:        .end    orUs1
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @xorUs() #0 {
+entry:
+  %0 = load i16, i16* @us1, align 2, !tbaa !5
+  %1 = load i16, i16* @us2, align 2, !tbaa !5
+  %xor3 = xor i16 %1, %0
+  store i16 %xor3, i16* @us, align 2, !tbaa !5
+; CHECK-LABEL:  .ent    xorUs
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
+; CHECK-DAG:    lhu     $[[US1:[0-9]+]], 0($[[US1_ADDR]])
+; CHECK-DAG:    lhu     $[[US2:[0-9]+]], 0($[[US2_ADDR]])
+; CHECK-DAG:    xor     $[[RES:[0-9]+]], $[[US2]], $[[US1]]
+; CHECK:        sh      $[[RES]], 0($[[US_ADDR]])
+; CHECK:        .end    xorUs
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @xorUs0() #0 {
+entry:
+  %0 = load i16, i16* @us1, align 2, !tbaa !5
+  %xor = xor i16 %0, 6062
+  store i16 %xor, i16* @us, align 2, !tbaa !5
+; CHECK-LABEL:  .ent    xorUs0
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
+; CHECK-DAG:    lhu     $[[US1:[0-9]+]], 0($[[US1_ADDR]])
+; CHECK-DAG:    addiu   $[[CONST_6062:[0-9]+]], $zero, 6062
+; CHECK-DAG:    xor     $[[RES:[0-9]+]], $[[US1]], $[[CONST_6062]]
+; CHECK:        sh      $[[RES]], 0($[[US_ADDR]])
+; CHECK:        .end    xorUs0
+
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @xorUs1() #0 {
+entry:
+  %0 = load i16, i16* @us1, align 2, !tbaa !5
+  %xor = xor i16 %0, 60024
+  store i16 %xor, i16* @us, align 2, !tbaa !5
+; CHECK-LABEL:  .ent    xorUs1
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
+; CHECK-DAG:    lhu     $[[US1:[0-9]+]], 0($[[US1_ADDR]])
+; CHECK-DAG:    addiu   $[[CONST_Neg5512:[0-9]+]], $zero, -5512
+; CHECK-DAG:    xor     $[[RES:[0-9]+]], $[[US1]], $[[CONST_Neg5512]]
+; CHECK:        sh      $[[RES]], 0($[[US_ADDR]])
+; CHECK:        .end    xorUs1
+  ret void
+}
+
+attributes #0 = { noinline nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 (trunk)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C/C++ TBAA"}
+!5 = !{!6, !6, i64 0}
+!6 = !{!"short", !3, i64 0}
diff --git a/test/CodeGen/Mips/Fast-ISel/nullvoid.ll b/test/CodeGen/Mips/Fast-ISel/nullvoid.ll
index c847561d0278..5fa3f13ace4c 100644
--- a/test/CodeGen/Mips/Fast-ISel/nullvoid.ll
+++ b/test/CodeGen/Mips/Fast-ISel/nullvoid.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 ; Function Attrs: nounwind
diff --git a/test/CodeGen/Mips/Fast-ISel/overflt.ll b/test/CodeGen/Mips/Fast-ISel/overflt.ll
new file mode 100644
index 000000000000..57f991e23d95
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/overflt.ll
@@ -0,0 +1,64 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN:     < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
+; RUN:     < %s | FileCheck %s
+
+@x = common global [128000 x float] zeroinitializer, align 4
+@y = global float* getelementptr inbounds ([128000 x float], [128000 x float]* @x, i32 0, i32 0), align 4
+@result = common global float 0.000000e+00, align 4
+@.str = private unnamed_addr constant [5 x i8] c"%f \0A\00", align 1
+
+; Function Attrs: nounwind
+define void @foo() {
+entry:
+; CHECK-LABEL:   .ent  foo
+  %0 = load float*, float** @y, align 4
+  %arrayidx = getelementptr inbounds float, float* %0, i32 64000
+  store float 5.500000e+00, float* %arrayidx, align 4
+; CHECK:        lui     $[[REG_FPCONST_INT:[0-9]+]], 16560
+; CHECK:        mtc1    $[[REG_FPCONST_INT]], $f[[REG_FPCONST:[0-9]+]]
+; CHECK:        lw      $[[REG_Y_GOT:[0-9]+]], %got(y)(${{[0-9]+}})
+; CHECK:        lw      $[[REG_Y:[0-9]+]], 0($[[REG_Y_GOT]])
+; CHECK:        lui     $[[REG_IDX_UPPER:[0-9]+]], 3
+; CHECK:        ori     $[[REG_IDX:[0-9]+]], $[[REG_IDX_UPPER]], 59392
+; CHECK:        addu    $[[REG_Y_IDX:[0-9]+]], $[[REG_IDX]], $[[REG_Y]]
+; CHECK:        swc1    $f[[REG_FPCONST]], 0($[[REG_Y_IDX]])
+  ret void
+; CHECK-LABEL:   .end  foo
+}
+
+; Function Attrs: nounwind
+define void @goo() {
+entry:
+; CHECK-LABEL:   .ent  goo
+  %0 = load float*, float** @y, align 4
+  %arrayidx = getelementptr inbounds float, float* %0, i32 64000
+  %1 = load float, float* %arrayidx, align 4
+  store float %1, float* @result, align 4
+; CHECK-DAG:    lw      $[[REG_RESULT:[0-9]+]], %got(result)(${{[0-9]+}})
+; CHECK-DAG:    lw      $[[REG_Y_GOT:[0-9]+]], %got(y)(${{[0-9]+}})
+; CHECK-DAG:    lw      $[[REG_Y:[0-9]+]], 0($[[REG_Y_GOT]])
+; CHECK-DAG:    lui     $[[REG_IDX_UPPER:[0-9]+]], 3
+; CHECK-DAG:    ori     $[[REG_IDX:[0-9]+]], $[[REG_IDX_UPPER]], 59392
+; CHECK-DAG:    addu    $[[REG_Y_IDX:[0-9]+]], $[[REG_IDX]], $[[REG_Y]]
+; CHECK-DAG:    lwc1    $f[[Y_IDX:[0-9]+]], 0($[[REG_Y_IDX]])
+; CHECK-DAG:    swc1    $f[[Y_IDX]], 0($[[REG_RESULT]])
+; CHECK-LABEL:   .end  goo
+  ret void
+}
+
+; 
+; Original C code for test.
+;
+;float x[128000];
+;float *y = x;
+;float result;
+
+
+;void foo() {
+;  y[64000] = 5.5;
+;}
+
+;void goo() {
+;  result = y[64000];
+;}
diff --git a/test/CodeGen/Mips/Fast-ISel/retabi.ll b/test/CodeGen/Mips/Fast-ISel/retabi.ll
new file mode 100644
index 000000000000..03119b827eb6
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/retabi.ll
@@ -0,0 +1,108 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN:     < %s | FileCheck %s
+
+@i = global i32 75, align 4
+@s = global i16 -345, align 2
+@c = global i8 118, align 1
+@f = global float 0x40BE623360000000, align 4
+@d = global double 1.298330e+03, align 8
+
+; Function Attrs: nounwind
+define i32 @reti() {
+entry:
+; CHECK-LABEL: reti:
+  %0 = load i32, i32* @i, align 4
+  ret i32 %0
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK:        lw      $[[REG_I_ADDR:[0-9]+]], %got(i)($[[REG_GP]])
+; CHECK:        lw      $2, 0($[[REG_I_ADDR]])
+; CHECK:        jr      $ra
+}
+
+; Function Attrs: nounwind
+define i16 @retus() {
+entry:
+; CHECK-LABEL: retus:
+  %0 = load i16, i16* @s, align 2
+  ret i16 %0
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK:        lw      $[[REG_S_ADDR:[0-9]+]], %got(s)($[[REG_GP]])
+; CHECK:        lhu     $2, 0($[[REG_S_ADDR]])
+; CHECK:        jr      $ra
+}
+
+; Function Attrs: nounwind
+define signext i16 @rets() {
+entry:
+; CHECK-LABEL: rets:
+  %0 = load i16, i16* @s, align 2
+  ret i16 %0
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK:        lw      $[[REG_S_ADDR:[0-9]+]], %got(s)($[[REG_GP]])
+; CHECK:        lhu     $[[REG_S:[0-9]+]], 0($[[REG_S_ADDR]])
+; CHECK:        seh     $2, $[[REG_S]]
+; CHECK:        jr      $ra
+}
+
+; Function Attrs: nounwind
+define i8 @retuc() {
+entry:
+; CHECK-LABEL: retuc:
+  %0 = load i8, i8* @c, align 1
+  ret i8 %0
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK:        lw      $[[REG_C_ADDR:[0-9]+]], %got(c)($[[REG_GP]])
+; CHECK:        lbu     $2, 0($[[REG_C_ADDR]])
+; CHECK:        jr      $ra
+}
+
+; Function Attrs: nounwind
+define signext i8 @retc() {
+entry:
+; CHECK-LABEL: retc:
+  %0 = load i8, i8* @c, align 1
+  ret i8 %0
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK:        lw      $[[REG_C_ADDR:[0-9]+]], %got(c)($[[REG_GP]])
+; CHECK:        lbu     $[[REG_C:[0-9]+]], 0($[[REG_C_ADDR]])
+; CHECK:        seb     $2, $[[REG_C]]
+; CHECK:        jr      $ra
+}
+
+; Function Attrs: nounwind
+define float @retf() {
+entry:
+; CHECK-LABEL: retf:
+  %0 = load float, float* @f, align 4
+  ret float %0
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK:        lw      $[[REG_F_ADDR:[0-9]+]], %got(f)($[[REG_GP]])
+; CHECK:        lwc1    $f0, 0($[[REG_F_ADDR]])
+; CHECK:        jr      $ra
+}
+
+; Function Attrs: nounwind
+define double @retd() {
+entry:
+; CHECK-LABEL: retd:
+  %0 = load double, double* @d, align 8
+  ret double %0
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK:        lw      $[[REG_D_ADDR:[0-9]+]], %got(d)($[[REG_GP]])
+; CHECK:        ldc1    $f0, 0($[[REG_D_ADDR]])
+; CHECK:        jr      $ra
+}
diff --git a/test/CodeGen/Mips/Fast-ISel/shftopm.ll b/test/CodeGen/Mips/Fast-ISel/shftopm.ll
new file mode 100644
index 000000000000..90ddd190be13
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/shftopm.ll
@@ -0,0 +1,122 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel \
+; RUN:     -fast-isel-abort=1 -mcpu=mips32r2  < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel \
+; RUN:     -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s
+
+@s1 = global i16 -89, align 2
+@s2 = global i16 4, align 2
+@us1 = global i16 -503, align 2
+@us2 = global i16 5, align 2
+@s3 = common global i16 0, align 2
+@us3 = common global i16 0, align 2
+
+define void @sll() {
+entry:
+  %0 = load i16, i16* @s1, align 2
+  %1 = load i16, i16* @s2, align 2
+  %shl = shl i16 %0, %1
+  store i16 %shl, i16* @s3, align 2
+; CHECK-LABEL:  sll:
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK-DAG:    addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[S2_ADDR:[0-9]+]], %got(s2)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
+; CHECK-DAG:    lhu     $[[S1:[0-9]+]], 0($[[S1_ADDR]])
+; CHECK-DAG:    lhu     $[[S2:[0-9]+]], 0($[[S2_ADDR]])
+; CHECK:        sllv    $[[RES:[0-9]+]], $[[S1]], $[[S2]]
+; CHECK:        sh      $[[RES]], 0($[[S3_ADDR]])
+  ret void
+}
+
+define void @slli() {
+entry:
+  %0 = load i16, i16* @s1, align 2
+  %shl = shl i16 %0, 5
+  store i16 %shl, i16* @s3, align 2
+; CHECK-LABEL:  slli:
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK-DAG:    addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
+; CHECK-DAG:    lhu     $[[S1:[0-9]+]], 0($[[S1_ADDR]])
+; CHECK:        sll     $[[RES:[0-9]+]], $[[S1]],  5
+; CHECK:        sh      $[[RES]], 0($[[S3_ADDR]])
+  ret void
+}
+
+define void @srl() {
+entry:
+  %0 = load i16, i16* @us1, align 2
+  %1 = load i16, i16* @us2, align 2
+  %shr = lshr i16 %0, %1
+  store i16 %shr, i16* @us3, align 2
+  ret void
+; CHECK-LABEL:  srl:
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK-DAG:    addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
+; CHECK-DAG:    lhu     $[[US1:[0-9]+]], 0($[[US1_ADDR]])
+; CHECK-DAG:    lhu     $[[US2:[0-9]+]], 0($[[US2_ADDR]])
+; CHECK:        srlv    $[[RES:[0-9]+]], $[[US1]], $[[US2]]
+; CHECK:        sh      $[[RES]], 0($[[S3_ADDR]])
+}
+
+define void @srli() {
+entry:
+  %0 = load i16, i16* @us1, align 2
+  %shr = lshr i16 %0, 4
+  store i16 %shr, i16* @us3, align 2
+; CHECK-LABEL:  srli:
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK-DAG:    addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
+; CHECK-DAG:    lhu     $[[US1:[0-9]+]], 0($[[US1_ADDR]])
+; CHECK:        srl     $[[RES:[0-9]+]], $[[US1]], 4
+; CHECK:        sh      $[[RES]], 0($[[S3_ADDR]])
+  ret void
+}
+
+define void @sra() {
+entry:
+  %0 = load i16, i16* @s1, align 2
+  %1 = load i16, i16* @s2, align 2
+  %shr = ashr i16 %0, %1
+  store i16 %shr, i16* @s3, align 2
+; CHECK-LABEL:  sra:
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK-DAG:    addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[S2_ADDR:[0-9]+]], %got(s2)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
+; CHECK-DAG:    lhu     $[[S1:[0-9]+]], 0($[[S1_ADDR]])
+; CHECK-DAG:    lhu     $[[S2:[0-9]+]], 0($[[S2_ADDR]])
+; CHECK:        srav    $[[RES:[0-9]+]], $[[S1]], $[[S2]]
+; CHECK:        sh      $[[RES]], 0($[[S3_ADDR]])
+  ret void
+}
+
+define void @srai() {
+entry:
+  %0 = load i16, i16* @s1, align 2
+  %shr = ashr i16 %0, 2
+  store i16 %shr, i16* @s3, align 2
+; CHECK-LABEL:  srai:
+; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
+; CHECK-DAG:    addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
+; CHECK-DAG:    addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
+; CHECK-DAG:    lhu     $[[S1:[0-9]+]], 0($[[S1_ADDR]])
+; CHECK:        sra     $[[RES:[0-9]+]], $[[S1]], 2
+; CHECK:        sh      $[[RES]], 0($[[S3_ADDR]])
+  ret void
+}
diff --git a/test/CodeGen/Mips/Fast-ISel/shift.ll b/test/CodeGen/Mips/Fast-ISel/shift.ll
index 18fd5ac32d22..df1c82700d59 100644
--- a/test/CodeGen/Mips/Fast-ISel/shift.ll
+++ b/test/CodeGen/Mips/Fast-ISel/shift.ll
@@ -9,7 +9,7 @@ define i32 @main() nounwind uwtable {
 entry:
   %foo = alloca %struct.s, align 4
   %0 = bitcast %struct.s* %foo to i32*
-  %bf.load = load i32* %0, align 4
+  %bf.load = load i32, i32* %0, align 4
   %bf.lshr = lshr i32 %bf.load, 2
   %cmp = icmp ne i32 %bf.lshr, 2
   br i1 %cmp, label %if.then, label %if.end
diff --git a/test/CodeGen/Mips/Fast-ISel/simplestore.ll b/test/CodeGen/Mips/Fast-ISel/simplestore.ll
index 83e3f3f24274..bcb198b1a823 100644
--- a/test/CodeGen/Mips/Fast-ISel/simplestore.ll
+++ b/test/CodeGen/Mips/Fast-ISel/simplestore.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @abcd = external global i32
diff --git a/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll b/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
index 74723ae1beeb..f4b91d850255 100644
--- a/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
+++ b/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
@@ -1,10 +1,10 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s 
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s -check-prefix=mips32r2 
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s -check-prefix=mips32
 
 @f = common global float 0.000000e+00, align 4
diff --git a/test/CodeGen/Mips/Fast-ISel/simplestorei.ll b/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
index 128e1de9cad0..83ccae0b1de5 100644
--- a/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
+++ b/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @ijk = external global i32
diff --git a/test/CodeGen/Mips/abiflags32.ll b/test/CodeGen/Mips/abiflags32.ll
index e32d4a586ee3..39e2a90151e3 100644
--- a/test/CodeGen/Mips/abiflags32.ll
+++ b/test/CodeGen/Mips/abiflags32.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 %s -o - | FileCheck %s
 ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -mattr=fp64 %s -o - | FileCheck  -check-prefix=CHECK-64 %s
-; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips64 -mattr=-n64,n32 %s -o - | FileCheck  -check-prefix=CHECK-64n %s
+; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips64 -target-abi n32 %s -o - | FileCheck  -check-prefix=CHECK-64n %s
 
 ; CHECK: .nan    legacy
 ; We don't emit '.module fp=32' for compatibility with binutils 2.24 which
diff --git a/test/CodeGen/Mips/addi.ll b/test/CodeGen/Mips/addi.ll
index 01d409e521d7..b6af2ee45687 100644
--- a/test/CodeGen/Mips/addi.ll
+++ b/test/CodeGen/Mips/addi.ll
@@ -8,16 +8,16 @@
 
 define void @foo() nounwind {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %add = add nsw i32 %0, 5
   store i32 %add, i32* @i, align 4
-  %1 = load i32* @j, align 4
+  %1 = load i32, i32* @j, align 4
   %sub = sub nsw i32 %1, 5
   store i32 %sub, i32* @j, align 4
-  %2 = load i32* @k, align 4
+  %2 = load i32, i32* @k, align 4
   %add1 = add nsw i32 %2, 10000
   store i32 %add1, i32* @k, align 4
-  %3 = load i32* @l, align 4
+  %3 = load i32, i32* @l, align 4
   %sub2 = sub nsw i32 %3, 10000
   store i32 %sub2, i32* @l, align 4
 ; 16: 	addiu	${{[0-9]+}}, 5	# 16 bit inst
diff --git a/test/CodeGen/Mips/addressing-mode.ll b/test/CodeGen/Mips/addressing-mode.ll
index ea76dde82dc3..81e062062ecf 100644
--- a/test/CodeGen/Mips/addressing-mode.ll
+++ b/test/CodeGen/Mips/addressing-mode.ll
@@ -20,10 +20,10 @@ for.cond1.preheader:
 for.body3:
   %s.120 = phi i32 [ %s.022, %for.cond1.preheader ], [ %add7, %for.body3 ]
   %j.019 = phi i32 [ 0, %for.cond1.preheader ], [ %add8, %for.body3 ]
-  %arrayidx4 = getelementptr inbounds [256 x i32]* %a, i32 %i.021, i32 %j.019
-  %0 = load i32* %arrayidx4, align 4
-  %arrayidx6 = getelementptr inbounds [256 x i32]* %b, i32 %i.021, i32 %j.019
-  %1 = load i32* %arrayidx6, align 4
+  %arrayidx4 = getelementptr inbounds [256 x i32], [256 x i32]* %a, i32 %i.021, i32 %j.019
+  %0 = load i32, i32* %arrayidx4, align 4
+  %arrayidx6 = getelementptr inbounds [256 x i32], [256 x i32]* %b, i32 %i.021, i32 %j.019
+  %1 = load i32, i32* %arrayidx6, align 4
   %add = add i32 %0, %s.120
   %add7 = add i32 %add, %1
   %add8 = add nsw i32 %j.019, %m
diff --git a/test/CodeGen/Mips/align16.ll b/test/CodeGen/Mips/align16.ll
index 689ae8307f57..f385adfaa04c 100644
--- a/test/CodeGen/Mips/align16.ll
+++ b/test/CodeGen/Mips/align16.ll
@@ -15,13 +15,13 @@ entry:
   %x = alloca i32, align 8
   %zz = alloca i32, align 4
   %z = alloca i32, align 4
-  %0 = load i32* @i, align 4
-  %arrayidx = getelementptr inbounds [512 x i32]* %y, i32 0, i32 10
+  %0 = load i32, i32* @i, align 4
+  %arrayidx = getelementptr inbounds [512 x i32], [512 x i32]* %y, i32 0, i32 10
   store i32 %0, i32* %arrayidx, align 4
-  %1 = load i32* @i, align 4
+  %1 = load i32, i32* @i, align 4
   store i32 %1, i32* %x, align 8
   call void @p(i32* %x)
-  %arrayidx1 = getelementptr inbounds [512 x i32]* %y, i32 0, i32 10
+  %arrayidx1 = getelementptr inbounds [512 x i32], [512 x i32]* %y, i32 0, i32 10
   call void @p(i32* %arrayidx1)
   ret void
 }
diff --git a/test/CodeGen/Mips/alloca.ll b/test/CodeGen/Mips/alloca.ll
index fc7ef862a328..747a1362161d 100644
--- a/test/CodeGen/Mips/alloca.ll
+++ b/test/CodeGen/Mips/alloca.ll
@@ -9,7 +9,7 @@ entry:
 ; CHECK: move  $4, $[[T0]]
 ; CHECK: move  $4, $[[T2]]
   %tmp1 = alloca i8, i32 %size, align 4
-  %add.ptr = getelementptr inbounds i8* %tmp1, i32 5
+  %add.ptr = getelementptr inbounds i8, i8* %tmp1, i32 5
   store i8 97, i8* %add.ptr, align 1
   %tmp4 = alloca i8, i32 %size, align 4
   call void @foo2(double 1.000000e+00, double 2.000000e+00, i32 3) nounwind
@@ -39,17 +39,17 @@ entry:
 if.then:                                          ; preds = %entry
 ; CHECK: addiu $4, $[[T0]], 40
 
-  %add.ptr = getelementptr inbounds i8* %tmp1, i32 40
+  %add.ptr = getelementptr inbounds i8, i8* %tmp1, i32 40
   %1 = bitcast i8* %add.ptr to i32*
   call void @foo3(i32* %1) nounwind
-  %arrayidx15.pre = getelementptr inbounds i8* %tmp1, i32 12
+  %arrayidx15.pre = getelementptr inbounds i8, i8* %tmp1, i32 12
   %.pre = bitcast i8* %arrayidx15.pre to i32*
   br label %if.end
 
 if.else:                                          ; preds = %entry
 ; CHECK: addiu $4, $[[T0]], 12
 
-  %add.ptr5 = getelementptr inbounds i8* %tmp1, i32 12
+  %add.ptr5 = getelementptr inbounds i8, i8* %tmp1, i32 12
   %2 = bitcast i8* %add.ptr5 to i32*
   call void @foo3(i32* %2) nounwind
   br label %if.end
@@ -59,24 +59,24 @@ if.end:                                           ; preds = %if.else, %if.then
 ; CHECK: lw  $25, %call16(printf)
 
   %.pre-phi = phi i32* [ %2, %if.else ], [ %.pre, %if.then ]
-  %tmp7 = load i32* %0, align 4
-  %arrayidx9 = getelementptr inbounds i8* %tmp1, i32 4
+  %tmp7 = load i32, i32* %0, align 4
+  %arrayidx9 = getelementptr inbounds i8, i8* %tmp1, i32 4
   %3 = bitcast i8* %arrayidx9 to i32*
-  %tmp10 = load i32* %3, align 4
-  %arrayidx12 = getelementptr inbounds i8* %tmp1, i32 8
+  %tmp10 = load i32, i32* %3, align 4
+  %arrayidx12 = getelementptr inbounds i8, i8* %tmp1, i32 8
   %4 = bitcast i8* %arrayidx12 to i32*
-  %tmp13 = load i32* %4, align 4
-  %tmp16 = load i32* %.pre-phi, align 4
-  %arrayidx18 = getelementptr inbounds i8* %tmp1, i32 16
+  %tmp13 = load i32, i32* %4, align 4
+  %tmp16 = load i32, i32* %.pre-phi, align 4
+  %arrayidx18 = getelementptr inbounds i8, i8* %tmp1, i32 16
   %5 = bitcast i8* %arrayidx18 to i32*
-  %tmp19 = load i32* %5, align 4
-  %arrayidx21 = getelementptr inbounds i8* %tmp1, i32 20
+  %tmp19 = load i32, i32* %5, align 4
+  %arrayidx21 = getelementptr inbounds i8, i8* %tmp1, i32 20
   %6 = bitcast i8* %arrayidx21 to i32*
-  %tmp22 = load i32* %6, align 4
-  %arrayidx24 = getelementptr inbounds i8* %tmp1, i32 24
+  %tmp22 = load i32, i32* %6, align 4
+  %arrayidx24 = getelementptr inbounds i8, i8* %tmp1, i32 24
   %7 = bitcast i8* %arrayidx24 to i32*
-  %tmp25 = load i32* %7, align 4
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str, i32 0, i32 0), i32 %tmp7, i32 %tmp10, i32 %tmp13, i32 %tmp16, i32 %tmp19, i32 %tmp22, i32 %tmp25) nounwind
+  %tmp25 = load i32, i32* %7, align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([22 x i8], [22 x i8]* @.str, i32 0, i32 0), i32 %tmp7, i32 %tmp10, i32 %tmp13, i32 %tmp16, i32 %tmp19, i32 %tmp22, i32 %tmp25) nounwind
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/alloca16.ll b/test/CodeGen/Mips/alloca16.ll
index 4f6059878c3b..be8cc740310b 100644
--- a/test/CodeGen/Mips/alloca16.ll
+++ b/test/CodeGen/Mips/alloca16.ll
@@ -12,7 +12,7 @@ define void @temp(i32 %foo) nounwind {
 entry:
   %foo.addr = alloca i32, align 4
   store i32 %foo, i32* %foo.addr, align 4
-  %0 = load i32* %foo.addr, align 4
+  %0 = load i32, i32* %foo.addr, align 4
   store i32 %0, i32* @t, align 4
   ret void
 }
@@ -28,46 +28,46 @@ entry:
   %sssi = alloca i32, align 4
   %ip = alloca i32*, align 4
   %sssj = alloca i32, align 4
-  %0 = load i32* @iiii, align 4
+  %0 = load i32, i32* @iiii, align 4
   store i32 %0, i32* %sssi, align 4
-  %1 = load i32* @kkkk, align 4
+  %1 = load i32, i32* @kkkk, align 4
   %mul = mul nsw i32 %1, 100
   %2 = alloca i8, i32 %mul
   %3 = bitcast i8* %2 to i32*
   store i32* %3, i32** %ip, align 4
-  %4 = load i32* @jjjj, align 4
+  %4 = load i32, i32* @jjjj, align 4
   store i32 %4, i32* %sssj, align 4
-  %5 = load i32* @jjjj, align 4
-  %6 = load i32* @iiii, align 4
-  %7 = load i32** %ip, align 4
-  %arrayidx = getelementptr inbounds i32* %7, i32 %6
+  %5 = load i32, i32* @jjjj, align 4
+  %6 = load i32, i32* @iiii, align 4
+  %7 = load i32*, i32** %ip, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %7, i32 %6
   store i32 %5, i32* %arrayidx, align 4
-  %8 = load i32* @kkkk, align 4
-  %9 = load i32* @jjjj, align 4
-  %10 = load i32** %ip, align 4
-  %arrayidx1 = getelementptr inbounds i32* %10, i32 %9
+  %8 = load i32, i32* @kkkk, align 4
+  %9 = load i32, i32* @jjjj, align 4
+  %10 = load i32*, i32** %ip, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %10, i32 %9
   store i32 %8, i32* %arrayidx1, align 4
-  %11 = load i32* @iiii, align 4
-  %12 = load i32* @kkkk, align 4
-  %13 = load i32** %ip, align 4
-  %arrayidx2 = getelementptr inbounds i32* %13, i32 %12
+  %11 = load i32, i32* @iiii, align 4
+  %12 = load i32, i32* @kkkk, align 4
+  %13 = load i32*, i32** %ip, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %13, i32 %12
   store i32 %11, i32* %arrayidx2, align 4
-  %14 = load i32** %ip, align 4
-  %arrayidx3 = getelementptr inbounds i32* %14, i32 25
-  %15 = load i32* %arrayidx3, align 4
+  %14 = load i32*, i32** %ip, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %14, i32 25
+  %15 = load i32, i32* %arrayidx3, align 4
   store i32 %15, i32* @riii, align 4
-  %16 = load i32** %ip, align 4
-  %arrayidx4 = getelementptr inbounds i32* %16, i32 35
-  %17 = load i32* %arrayidx4, align 4
+  %16 = load i32*, i32** %ip, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %16, i32 35
+  %17 = load i32, i32* %arrayidx4, align 4
   store i32 %17, i32* @rjjj, align 4
-  %18 = load i32** %ip, align 4
-  %arrayidx5 = getelementptr inbounds i32* %18, i32 100
-  %19 = load i32* %arrayidx5, align 4
+  %18 = load i32*, i32** %ip, align 4
+  %arrayidx5 = getelementptr inbounds i32, i32* %18, i32 100
+  %19 = load i32, i32* %arrayidx5, align 4
   store i32 %19, i32* @rkkk, align 4
-  %20 = load i32* @t, align 4
-  %21 = load i32** %ip, align 4
-  %arrayidx6 = getelementptr inbounds i32* %21, i32 %20
-  %22 = load i32* %arrayidx6, align 4
+  %20 = load i32, i32* @t, align 4
+  %21 = load i32*, i32** %ip, align 4
+  %arrayidx6 = getelementptr inbounds i32, i32* %21, i32 %20
+  %22 = load i32, i32* %arrayidx6, align 4
 ; 16: 	addiu $sp, -16
   call void @temp(i32 %22)
 ; 16: 	addiu $sp, 16
diff --git a/test/CodeGen/Mips/analyzebranch.ll b/test/CodeGen/Mips/analyzebranch.ll
index 4b5d09778d79..d5ecaaeddc33 100644
--- a/test/CodeGen/Mips/analyzebranch.ll
+++ b/test/CodeGen/Mips/analyzebranch.ll
@@ -60,7 +60,7 @@ if.then:                                          ; preds = %entry
   unreachable
 
 if.end:                                           ; preds = %entry
-  tail call void (...)* @f2() nounwind
+  tail call void (...) @f2() nounwind
   ret void
 }
 
diff --git a/test/CodeGen/Mips/and1.ll b/test/CodeGen/Mips/and1.ll
index 4ff1204fe7ae..57076a4d4fcf 100644
--- a/test/CodeGen/Mips/and1.ll
+++ b/test/CodeGen/Mips/and1.ll
@@ -6,11 +6,11 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @x, align 4
-  %1 = load i32* @y, align 4
+  %0 = load i32, i32* @x, align 4
+  %1 = load i32, i32* @y, align 4
   %and = and i32 %0, %1
 ; 16:	and	${{[0-9]+}}, ${{[0-9]+}}
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), i32 %and)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll
index ccfeb00967e3..031cce0b6074 100644
--- a/test/CodeGen/Mips/atomic.ll
+++ b/test/CodeGen/Mips/atomic.ll
@@ -54,7 +54,7 @@ define i32 @AtomicSwap32(i32 signext %newval) nounwind {
 entry:
   %newval.addr = alloca i32, align 4
   store i32 %newval, i32* %newval.addr, align 4
-  %tmp = load i32* %newval.addr, align 4
+  %tmp = load i32, i32* %newval.addr, align 4
   %0 = atomicrmw xchg i32* @x, i32 %tmp monotonic
   ret i32 %0
 
@@ -74,7 +74,7 @@ define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind {
 entry:
   %newval.addr = alloca i32, align 4
   store i32 %newval, i32* %newval.addr, align 4
-  %tmp = load i32* %newval.addr, align 4
+  %tmp = load i32, i32* %newval.addr, align 4
   %0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic monotonic
   %1 = extractvalue { i32, i1 } %0, 0
   ret i32 %1
@@ -429,7 +429,7 @@ entry:
 ; FIXME: At the moment, we don't seem to do addr+offset for any atomic load/store.
 define i32 @AtomicLoadAdd32_OffGt9Bit(i32 signext %incr) nounwind {
 entry:
-  %0 = atomicrmw add i32* getelementptr(i32* @x, i32 256), i32 %incr monotonic
+  %0 = atomicrmw add i32* getelementptr(i32, i32* @x, i32 256), i32 %incr monotonic
   ret i32 %0
 
 ; ALL-LABEL: AtomicLoadAdd32_OffGt9Bit:
diff --git a/test/CodeGen/Mips/atomicops.ll b/test/CodeGen/Mips/atomicops.ll
index c26415233d0b..0ff9f5c22a84 100644
--- a/test/CodeGen/Mips/atomicops.ll
+++ b/test/CodeGen/Mips/atomicops.ll
@@ -18,15 +18,15 @@ entry:
   store volatile i32 0, i32* %x, align 4
   %0 = atomicrmw add i32* %x, i32 1 seq_cst
   %add.i = add nsw i32 %0, 2
-  %1 = load volatile i32* %x, align 4
-  %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %add.i, i32 %1) nounwind
+  %1 = load volatile i32, i32* %x, align 4
+  %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0), i32 %add.i, i32 %1) nounwind
   %pair = cmpxchg i32* %x, i32 1, i32 2 seq_cst seq_cst
   %2 = extractvalue { i32, i1 } %pair, 0
-  %3 = load volatile i32* %x, align 4
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %2, i32 %3) nounwind
+  %3 = load volatile i32, i32* %x, align 4
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0), i32 %2, i32 %3) nounwind
   %4 = atomicrmw xchg i32* %x, i32 1 seq_cst
-  %5 = load volatile i32* %x, align 4
-  %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %4, i32 %5) nounwind
+  %5 = load volatile i32, i32* %x, align 4
+  %call3 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0), i32 %4, i32 %5) nounwind
 ; 16-LABEL: main:
 ; 16:	lw	${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
 ; 16: 	lw	${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
diff --git a/test/CodeGen/Mips/beqzc.ll b/test/CodeGen/Mips/beqzc.ll
index 4a294c2d817e..37bece884212 100644
--- a/test/CodeGen/Mips/beqzc.ll
+++ b/test/CodeGen/Mips/beqzc.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=cond-b-short
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=cond-b-short
 
 @i = global i32 0, align 4
 @j = common global i32 0, align 4
@@ -6,7 +6,7 @@
 ; Function Attrs: nounwind optsize
 define i32 @main() #0 {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %cmp = icmp eq i32 %0, 0
   %. = select i1 %cmp, i32 10, i32 55
   store i32 %., i32* @j, align 4
diff --git a/test/CodeGen/Mips/beqzc1.ll b/test/CodeGen/Mips/beqzc1.ll
index 8f929a8e3541..1f5575f099fa 100644
--- a/test/CodeGen/Mips/beqzc1.ll
+++ b/test/CodeGen/Mips/beqzc1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=cond-b-short
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=cond-b-short
 
 @i = global i32 0, align 4
 @j = common global i32 0, align 4
@@ -6,7 +6,7 @@
 ; Function Attrs: nounwind optsize
 define i32 @main() #0 {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %cmp = icmp eq i32 %0, 0
   br i1 %cmp, label %if.then, label %if.end
 
diff --git a/test/CodeGen/Mips/biggot.ll b/test/CodeGen/Mips/biggot.ll
index da287eea6fd1..b56ce6ba87b1 100644
--- a/test/CodeGen/Mips/biggot.ll
+++ b/test/CodeGen/Mips/biggot.ll
@@ -20,7 +20,7 @@ entry:
 ; N64: daddu  $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
 ; N64: ld  ${{[0-9]+}}, %call_lo(foo0)($[[R3]])
 
-  %0 = load i32* @v0, align 4
+  %0 = load i32, i32* @v0, align 4
   tail call void @foo0(i32 %0) nounwind
   ret void
 }
diff --git a/test/CodeGen/Mips/blockaddr.ll b/test/CodeGen/Mips/blockaddr.ll
index d6dc7e7b24b0..f74363702af5 100644
--- a/test/CodeGen/Mips/blockaddr.ll
+++ b/test/CodeGen/Mips/blockaddr.ll
@@ -1,9 +1,9 @@
 ; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-O32
 ; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-O32
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n32 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N32
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n32 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N32
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n64 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N64
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n64 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N64
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n32 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N32
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n32 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N32
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n64 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N64
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n64 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N64
 ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -mattr=+mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-MIPS16-1
 ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -mattr=+mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-MIPS16-2
 
diff --git a/test/CodeGen/Mips/brconeq.ll b/test/CodeGen/Mips/brconeq.ll
index 613391557efd..f555528bbb64 100644
--- a/test/CodeGen/Mips/brconeq.ll
+++ b/test/CodeGen/Mips/brconeq.ll
@@ -6,8 +6,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @i, align 4
-  %1 = load i32* @j, align 4
+  %0 = load i32, i32* @i, align 4
+  %1 = load i32, i32* @j, align 4
   %cmp = icmp eq i32 %0, %1
 ; 16:	cmp	${{[0-9]+}}, ${{[0-9]+}}
 ; 16:	bteqz	$[[LABEL:[0-9A-Ba-b_]+]]
diff --git a/test/CodeGen/Mips/brconeqk.ll b/test/CodeGen/Mips/brconeqk.ll
index 2c0e72dabd29..59edae82e5ad 100644
--- a/test/CodeGen/Mips/brconeqk.ll
+++ b/test/CodeGen/Mips/brconeqk.ll
@@ -5,7 +5,7 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %cmp = icmp eq i32 %0, 10
   br i1 %cmp, label %if.end, label %if.then
 ; 16:	cmpi	${{[0-9]+}}, {{[0-9]+}}
diff --git a/test/CodeGen/Mips/brconeqz.ll b/test/CodeGen/Mips/brconeqz.ll
index 5586e7b976da..22c566407528 100644
--- a/test/CodeGen/Mips/brconeqz.ll
+++ b/test/CodeGen/Mips/brconeqz.ll
@@ -5,7 +5,7 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %cmp = icmp eq i32 %0, 0
   br i1 %cmp, label %if.end, label %if.then
 ; 16:	beqz	${{[0-9]+}}, $[[LABEL:[0-9A-Ba-b_]+]]
diff --git a/test/CodeGen/Mips/brconge.ll b/test/CodeGen/Mips/brconge.ll
index 02f0a633b313..46d19847d9bc 100644
--- a/test/CodeGen/Mips/brconge.ll
+++ b/test/CodeGen/Mips/brconge.ll
@@ -8,8 +8,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @i, align 4
-  %1 = load i32* @j, align 4
+  %0 = load i32, i32* @i, align 4
+  %1 = load i32, i32* @j, align 4
   %cmp = icmp slt i32 %0, %1
   br i1 %cmp, label %if.then, label %if.end
 
@@ -22,7 +22,7 @@ if.then:                                          ; preds = %entry
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
-  %2 = load i32* @k, align 4
+  %2 = load i32, i32* @k, align 4
   %cmp1 = icmp slt i32 %0, %2
   br i1 %cmp1, label %if.then2, label %if.end3
 
diff --git a/test/CodeGen/Mips/brcongt.ll b/test/CodeGen/Mips/brcongt.ll
index 767b51b21b91..cefacb8318b0 100644
--- a/test/CodeGen/Mips/brcongt.ll
+++ b/test/CodeGen/Mips/brcongt.ll
@@ -7,8 +7,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @i, align 4
-  %1 = load i32* @j, align 4
+  %0 = load i32, i32* @i, align 4
+  %1 = load i32, i32* @j, align 4
   %cmp = icmp sgt i32 %0, %1
   br i1 %cmp, label %if.end, label %if.then
 ; 16:	slt	${{[0-9]+}}, ${{[0-9]+}}
diff --git a/test/CodeGen/Mips/brconle.ll b/test/CodeGen/Mips/brconle.ll
index 854b2481c6e6..e1f15ecb6b92 100644
--- a/test/CodeGen/Mips/brconle.ll
+++ b/test/CodeGen/Mips/brconle.ll
@@ -8,8 +8,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @j, align 4
-  %1 = load i32* @i, align 4
+  %0 = load i32, i32* @j, align 4
+  %1 = load i32, i32* @i, align 4
   %cmp = icmp sgt i32 %0, %1
   br i1 %cmp, label %if.then, label %if.end
 
@@ -22,7 +22,7 @@ if.then:                                          ; preds = %entry
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
-  %2 = load i32* @k, align 4
+  %2 = load i32, i32* @k, align 4
   %cmp1 = icmp sgt i32 %1, %2
   br i1 %cmp1, label %if.then2, label %if.end3
 
diff --git a/test/CodeGen/Mips/brconlt.ll b/test/CodeGen/Mips/brconlt.ll
index 931a3e8c7ba4..049f35c393fe 100644
--- a/test/CodeGen/Mips/brconlt.ll
+++ b/test/CodeGen/Mips/brconlt.ll
@@ -7,8 +7,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @j, align 4
-  %1 = load i32* @i, align 4
+  %0 = load i32, i32* @j, align 4
+  %1 = load i32, i32* @i, align 4
   %cmp = icmp slt i32 %0, %1
   br i1 %cmp, label %if.end, label %if.then
 
diff --git a/test/CodeGen/Mips/brconne.ll b/test/CodeGen/Mips/brconne.ll
index 5d5bde3fcf91..b260320b94e1 100644
--- a/test/CodeGen/Mips/brconne.ll
+++ b/test/CodeGen/Mips/brconne.ll
@@ -6,8 +6,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @j, align 4
-  %1 = load i32* @i, align 4
+  %0 = load i32, i32* @j, align 4
+  %1 = load i32, i32* @i, align 4
   %cmp = icmp eq i32 %0, %1
   br i1 %cmp, label %if.then, label %if.end
 ; 16:	cmp	${{[0-9]+}}, ${{[0-9]+}}
diff --git a/test/CodeGen/Mips/brconnek.ll b/test/CodeGen/Mips/brconnek.ll
index 6208d7c5a04b..778a5cce72b3 100644
--- a/test/CodeGen/Mips/brconnek.ll
+++ b/test/CodeGen/Mips/brconnek.ll
@@ -5,7 +5,7 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @j, align 4
+  %0 = load i32, i32* @j, align 4
   %cmp = icmp eq i32 %0, 5
   br i1 %cmp, label %if.then, label %if.end
 
diff --git a/test/CodeGen/Mips/brconnez.ll b/test/CodeGen/Mips/brconnez.ll
index 47db7901b517..754714b21daf 100644
--- a/test/CodeGen/Mips/brconnez.ll
+++ b/test/CodeGen/Mips/brconnez.ll
@@ -5,7 +5,7 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @j, align 4
+  %0 = load i32, i32* @j, align 4
   %cmp = icmp eq i32 %0, 0
   br i1 %cmp, label %if.then, label %if.end
 
diff --git a/test/CodeGen/Mips/brdelayslot.ll b/test/CodeGen/Mips/brdelayslot.ll
index 68341c1ba25b..0f46619b8272 100644
--- a/test/CodeGen/Mips/brdelayslot.ll
+++ b/test/CodeGen/Mips/brdelayslot.ll
@@ -54,18 +54,18 @@ declare void @foo4(double)
 
 define void @foo5(i32 %a) nounwind {
 entry:
-  %0 = load i32* @g2, align 4
+  %0 = load i32, i32* @g2, align 4
   %tobool = icmp eq i32 %a, 0
   br i1 %tobool, label %if.else, label %if.then
 
 if.then:
-  %1 = load i32* @g1, align 4
+  %1 = load i32, i32* @g1, align 4
   %add = add nsw i32 %1, %0
   store i32 %add, i32* @g1, align 4
   br label %if.end
 
 if.else:
-  %2 = load i32* @g3, align 4
+  %2 = load i32, i32* @g3, align 4
   %sub = sub nsw i32 %2, %0
   store i32 %sub, i32* @g3, align 4
   br label %if.end
@@ -99,9 +99,9 @@ declare void @foo7(double, float)
 define i32 @foo8(i32 %a) nounwind {
 entry:
   store i32 %a, i32* @g1, align 4
-  %0 = load void ()** @foo9, align 4
+  %0 = load void ()*, void ()** @foo9, align 4
   tail call void %0() nounwind
-  %1 = load i32* @g1, align 4
+  %1 = load i32, i32* @g1, align 4
   %add = add nsw i32 %1, %a
   ret i32 %add
 }
@@ -144,8 +144,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %s.06 = phi i32 [ %add, %for.body ], [ 0, %entry ]
   %i.05 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i32 %i.05
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %i.05
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %s.06
   %inc = add nsw i32 %i.05, 1
   %exitcond = icmp eq i32 %inc, %n
diff --git a/test/CodeGen/Mips/brind.ll b/test/CodeGen/Mips/brind.ll
index 4c591fa1bba1..a3e9b8011a2b 100644
--- a/test/CodeGen/Mips/brind.ll
+++ b/test/CodeGen/Mips/brind.ll
@@ -9,29 +9,29 @@
 
 define i32 @main() nounwind {
 entry:
-  %puts = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str, i32 0, i32 0))
+  %puts = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str, i32 0, i32 0))
   br label %L1
 
 L1:                                               ; preds = %entry, %L3
   %i.0 = phi i32 [ 0, %entry ], [ %inc, %L3 ]
-  %puts5 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str5, i32 0, i32 0))
+  %puts5 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str5, i32 0, i32 0))
   br label %L2
 
 L2:                                               ; preds = %L1, %L3
   %i.1 = phi i32 [ %i.0, %L1 ], [ %inc, %L3 ]
-  %puts6 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str6, i32 0, i32 0))
+  %puts6 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str6, i32 0, i32 0))
   br label %L3
 
 L3:                                               ; preds = %L2, %L3
   %i.2 = phi i32 [ %i.1, %L2 ], [ %inc, %L3 ]
-  %puts7 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str7, i32 0, i32 0))
+  %puts7 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str7, i32 0, i32 0))
   %inc = add i32 %i.2, 1
-  %arrayidx = getelementptr inbounds [5 x i8*]* @main.L, i32 0, i32 %i.2
-  %0 = load i8** %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [5 x i8*], [5 x i8*]* @main.L, i32 0, i32 %i.2
+  %0 = load i8*, i8** %arrayidx, align 4
   indirectbr i8* %0, [label %L1, label %L2, label %L3, label %L4]
 ; 16: 	jrc	 ${{[0-9]+}}
 L4:                                               ; preds = %L3
-  %puts8 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str8, i32 0, i32 0))
+  %puts8 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str8, i32 0, i32 0))
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/brsize3.ll b/test/CodeGen/Mips/brsize3.ll
index 3620868bb2f6..dad0d841d4c6 100644
--- a/test/CodeGen/Mips/brsize3.ll
+++ b/test/CodeGen/Mips/brsize3.ll
@@ -1,6 +1,6 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=b-no-short
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=b-no-short
 
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=b-long
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=b-long
 
 ; ModuleID = 'brsize3.c'
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"
diff --git a/test/CodeGen/Mips/brsize3a.ll b/test/CodeGen/Mips/brsize3a.ll
index f05e21191925..e1cd5893ceda 100644
--- a/test/CodeGen/Mips/brsize3a.ll
+++ b/test/CodeGen/Mips/brsize3a.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=b-short
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=b-short
 
 ; ModuleID = 'brsize3.c'
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"
diff --git a/test/CodeGen/Mips/cache-intrinsic.ll b/test/CodeGen/Mips/cache-intrinsic.ll
index 2fa411589596..987032eaeb89 100644
--- a/test/CodeGen/Mips/cache-intrinsic.ll
+++ b/test/CodeGen/Mips/cache-intrinsic.ll
@@ -10,10 +10,10 @@ define i32 @main() {
 entry:
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0))
-  %call1 = call i8* @strcpy(i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds ([25 x i8]* @.str1, i32 0, i32 0)) #3
-  call void @llvm.clear_cache(i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds (i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0), i32 32)) #3
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0))
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0))
+  %call1 = call i8* @strcpy(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str1, i32 0, i32 0)) #3
+  call void @llvm.clear_cache(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds (i8, i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i32 32)) #3
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0))
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/cconv/arguments-float.ll b/test/CodeGen/Mips/cconv/arguments-float.ll
index 14a3baa7f539..c81c7215e164 100644
--- a/test/CodeGen/Mips/cconv/arguments-float.ll
+++ b/test/CodeGen/Mips/cconv/arguments-float.ll
@@ -1,14 +1,14 @@
-; RUN: llc -march=mips -relocation-model=static -soft-float < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32BE %s
-; RUN: llc -march=mipsel -relocation-model=static -soft-float < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32LE %s
+; RUN: llc -march=mips -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32BE %s
+; RUN: llc -march=mipsel -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32LE %s
 
-; RUN-TODO: llc -march=mips64 -relocation-model=static -soft-float -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
-; RUN-TODO: llc -march=mips64el -relocation-model=static -soft-float -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
 
-; RUN: llc -march=mips64 -relocation-model=static -soft-float -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s
-; RUN: llc -march=mips64el -relocation-model=static -soft-float -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s
+; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s
+; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s
 
-; RUN: llc -march=mips64 -relocation-model=static -soft-float -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s
-; RUN: llc -march=mips64el -relocation-model=static -soft-float -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s
+; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s
+; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s
 
 ; Test the floating point arguments for all ABI's and byte orders as specified
 ; by section 5 of MD00305 (MIPS ABIs Described).
@@ -24,23 +24,23 @@
 define void @double_args(double %a, double %b, double %c, double %d, double %e,
                          double %f, double %g, double %h, double %i) nounwind {
 entry:
-        %0 = getelementptr [11 x double]* @doubles, i32 0, i32 1
+        %0 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 1
         store volatile double %a, double* %0
-        %1 = getelementptr [11 x double]* @doubles, i32 0, i32 2
+        %1 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 2
         store volatile double %b, double* %1
-        %2 = getelementptr [11 x double]* @doubles, i32 0, i32 3
+        %2 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 3
         store volatile double %c, double* %2
-        %3 = getelementptr [11 x double]* @doubles, i32 0, i32 4
+        %3 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 4
         store volatile double %d, double* %3
-        %4 = getelementptr [11 x double]* @doubles, i32 0, i32 5
+        %4 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 5
         store volatile double %e, double* %4
-        %5 = getelementptr [11 x double]* @doubles, i32 0, i32 6
+        %5 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 6
         store volatile double %f, double* %5
-        %6 = getelementptr [11 x double]* @doubles, i32 0, i32 7
+        %6 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 7
         store volatile double %g, double* %6
-        %7 = getelementptr [11 x double]* @doubles, i32 0, i32 8
+        %7 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 8
         store volatile double %h, double* %7
-        %8 = getelementptr [11 x double]* @doubles, i32 0, i32 9
+        %8 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 9
         store volatile double %i, double* %8
         ret void
 }
@@ -105,25 +105,25 @@ define void @float_args(float %a, float %b, float %c, float %d, float %e,
                         float %f, float %g, float %h, float %i, float %j)
                        nounwind {
 entry:
-        %0 = getelementptr [11 x float]* @floats, i32 0, i32 1
+        %0 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 1
         store volatile float %a, float* %0
-        %1 = getelementptr [11 x float]* @floats, i32 0, i32 2
+        %1 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 2
         store volatile float %b, float* %1
-        %2 = getelementptr [11 x float]* @floats, i32 0, i32 3
+        %2 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 3
         store volatile float %c, float* %2
-        %3 = getelementptr [11 x float]* @floats, i32 0, i32 4
+        %3 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 4
         store volatile float %d, float* %3
-        %4 = getelementptr [11 x float]* @floats, i32 0, i32 5
+        %4 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 5
         store volatile float %e, float* %4
-        %5 = getelementptr [11 x float]* @floats, i32 0, i32 6
+        %5 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 6
         store volatile float %f, float* %5
-        %6 = getelementptr [11 x float]* @floats, i32 0, i32 7
+        %6 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 7
         store volatile float %g, float* %6
-        %7 = getelementptr [11 x float]* @floats, i32 0, i32 8
+        %7 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 8
         store volatile float %h, float* %7
-        %8 = getelementptr [11 x float]* @floats, i32 0, i32 9
+        %8 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 9
         store volatile float %i, float* %8
-        %9 = getelementptr [11 x float]* @floats, i32 0, i32 10
+        %9 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 10
         store volatile float %j, float* %9
         ret void
 }
@@ -170,9 +170,9 @@ entry:
 
 define void @double_arg2(i8 %a, double %b) nounwind {
 entry:
-        %0 = getelementptr [11 x i8]* @bytes, i32 0, i32 1
+        %0 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 1
         store volatile i8 %a, i8* %0
-        %1 = getelementptr [11 x double]* @doubles, i32 0, i32 1
+        %1 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 1
         store volatile double %b, double* %1
         ret void
 }
@@ -197,9 +197,9 @@ entry:
 
 define void @float_arg2(i8 signext %a, float %b) nounwind {
 entry:
-        %0 = getelementptr [11 x i8]* @bytes, i32 0, i32 1
+        %0 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 1
         store volatile i8 %a, i8* %0
-        %1 = getelementptr [11 x float]* @floats, i32 0, i32 1
+        %1 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 1
         store volatile float %b, float* %1
         ret void
 }
diff --git a/test/CodeGen/Mips/cconv/arguments-fp128.ll b/test/CodeGen/Mips/cconv/arguments-fp128.ll
index c8cd8fd11e50..6c62609396c5 100644
--- a/test/CodeGen/Mips/cconv/arguments-fp128.ll
+++ b/test/CodeGen/Mips/cconv/arguments-fp128.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=mips64 -relocation-model=static -soft-float -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s
-; RUN: llc -march=mips64el -relocation-model=static -soft-float -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s
+; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s
+; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s
 
-; RUN: llc -march=mips64 -relocation-model=static -soft-float -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s
-; RUN: llc -march=mips64el -relocation-model=static -soft-float -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s
+; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s
+; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s
 
 ; Test the fp128 arguments for all ABI's and byte orders as specified
 ; by section 2 of the MIPSpro N32 Handbook.
@@ -13,15 +13,15 @@
 
 define void @ldouble_args(fp128 %a, fp128 %b, fp128 %c, fp128 %d, fp128 %e) nounwind {
 entry:
-        %0 = getelementptr [11 x fp128]* @ldoubles, i32 0, i32 1
+        %0 = getelementptr [11 x fp128], [11 x fp128]* @ldoubles, i32 0, i32 1
         store volatile fp128 %a, fp128* %0
-        %1 = getelementptr [11 x fp128]* @ldoubles, i32 0, i32 2
+        %1 = getelementptr [11 x fp128], [11 x fp128]* @ldoubles, i32 0, i32 2
         store volatile fp128 %b, fp128* %1
-        %2 = getelementptr [11 x fp128]* @ldoubles, i32 0, i32 3
+        %2 = getelementptr [11 x fp128], [11 x fp128]* @ldoubles, i32 0, i32 3
         store volatile fp128 %c, fp128* %2
-        %3 = getelementptr [11 x fp128]* @ldoubles, i32 0, i32 4
+        %3 = getelementptr [11 x fp128], [11 x fp128]* @ldoubles, i32 0, i32 4
         store volatile fp128 %d, fp128* %3
-        %4 = getelementptr [11 x fp128]* @ldoubles, i32 0, i32 5
+        %4 = getelementptr [11 x fp128], [11 x fp128]* @ldoubles, i32 0, i32 5
         store volatile fp128 %e, fp128* %4
         ret void
 }
diff --git a/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll b/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
index 70ccf14c5450..9f1fe91ec172 100644
--- a/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
+++ b/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
@@ -1,14 +1,14 @@
 ; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32BE %s
 ; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32LE %s
 
-; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
-; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
 
-; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW --check-prefix=NEWBE %s
-; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW --check-prefix=NEWLE %s
+; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW --check-prefix=NEWBE %s
+; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW --check-prefix=NEWLE %s
 
-; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW --check-prefix=NEWBE %s
-; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW --check-prefix=NEWLE %s
+; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW --check-prefix=NEWBE %s
+; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW --check-prefix=NEWLE %s
 
 ; Test the effect of varargs on floating point types in the non-variable part
 ; of the argument list as specified by section 2 of the MIPSpro N32 Handbook.
@@ -25,14 +25,14 @@
 define void @double_args(double %a, ...)
                          nounwind {
 entry:
-        %0 = getelementptr [11 x double]* @doubles, i32 0, i32 1
+        %0 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 1
         store volatile double %a, double* %0
 
         %ap = alloca i8*
         %ap2 = bitcast i8** %ap to i8*
         call void @llvm.va_start(i8* %ap2)
         %b = va_arg i8** %ap, double
-        %1 = getelementptr [11 x double]* @doubles, i32 0, i32 2
+        %1 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 2
         store volatile double %b, double* %1
         call void @llvm.va_end(i8* %ap2)
         ret void
@@ -90,14 +90,14 @@ entry:
 
 define void @float_args(float %a, ...) nounwind {
 entry:
-        %0 = getelementptr [11 x float]* @floats, i32 0, i32 1
+        %0 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 1
         store volatile float %a, float* %0
 
         %ap = alloca i8*
         %ap2 = bitcast i8** %ap to i8*
         call void @llvm.va_start(i8* %ap2)
         %b = va_arg i8** %ap, float
-        %1 = getelementptr [11 x float]* @floats, i32 0, i32 2
+        %1 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 2
         store volatile float %b, float* %1
         call void @llvm.va_end(i8* %ap2)
         ret void
diff --git a/test/CodeGen/Mips/cconv/arguments-hard-float.ll b/test/CodeGen/Mips/cconv/arguments-hard-float.ll
index 9837f7ee5586..24148ed176db 100644
--- a/test/CodeGen/Mips/cconv/arguments-hard-float.ll
+++ b/test/CodeGen/Mips/cconv/arguments-hard-float.ll
@@ -1,14 +1,14 @@
 ; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32BE %s
 ; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32LE %s
 
-; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
-; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
 
-; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s
-; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s
+; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s
+; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s
 
-; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s
-; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s
+; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s
+; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s
 
 ; Test the floating point arguments for all ABI's and byte orders as specified
 ; by section 5 of MD00305 (MIPS ABIs Described).
@@ -24,23 +24,23 @@
 define void @double_args(double %a, double %b, double %c, double %d, double %e,
                          double %f, double %g, double %h, double %i) nounwind {
 entry:
-        %0 = getelementptr [11 x double]* @doubles, i32 0, i32 1
+        %0 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 1
         store volatile double %a, double* %0
-        %1 = getelementptr [11 x double]* @doubles, i32 0, i32 2
+        %1 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 2
         store volatile double %b, double* %1
-        %2 = getelementptr [11 x double]* @doubles, i32 0, i32 3
+        %2 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 3
         store volatile double %c, double* %2
-        %3 = getelementptr [11 x double]* @doubles, i32 0, i32 4
+        %3 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 4
         store volatile double %d, double* %3
-        %4 = getelementptr [11 x double]* @doubles, i32 0, i32 5
+        %4 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 5
         store volatile double %e, double* %4
-        %5 = getelementptr [11 x double]* @doubles, i32 0, i32 6
+        %5 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 6
         store volatile double %f, double* %5
-        %6 = getelementptr [11 x double]* @doubles, i32 0, i32 7
+        %6 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 7
         store volatile double %g, double* %6
-        %7 = getelementptr [11 x double]* @doubles, i32 0, i32 8
+        %7 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 8
         store volatile double %h, double* %7
-        %8 = getelementptr [11 x double]* @doubles, i32 0, i32 9
+        %8 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 9
         store volatile double %i, double* %8
         ret void
 }
@@ -87,23 +87,23 @@ entry:
 define void @float_args(float %a, float %b, float %c, float %d, float %e,
                         float %f, float %g, float %h, float %i) nounwind {
 entry:
-        %0 = getelementptr [11 x float]* @floats, i32 0, i32 1
+        %0 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 1
         store volatile float %a, float* %0
-        %1 = getelementptr [11 x float]* @floats, i32 0, i32 2
+        %1 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 2
         store volatile float %b, float* %1
-        %2 = getelementptr [11 x float]* @floats, i32 0, i32 3
+        %2 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 3
         store volatile float %c, float* %2
-        %3 = getelementptr [11 x float]* @floats, i32 0, i32 4
+        %3 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 4
         store volatile float %d, float* %3
-        %4 = getelementptr [11 x float]* @floats, i32 0, i32 5
+        %4 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 5
         store volatile float %e, float* %4
-        %5 = getelementptr [11 x float]* @floats, i32 0, i32 6
+        %5 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 6
         store volatile float %f, float* %5
-        %6 = getelementptr [11 x float]* @floats, i32 0, i32 7
+        %6 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 7
         store volatile float %g, float* %6
-        %7 = getelementptr [11 x float]* @floats, i32 0, i32 8
+        %7 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 8
         store volatile float %h, float* %7
-        %8 = getelementptr [11 x float]* @floats, i32 0, i32 9
+        %8 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 9
         store volatile float %i, float* %8
         ret void
 }
@@ -153,9 +153,9 @@ entry:
 
 define void @double_arg2(i8 %a, double %b) nounwind {
 entry:
-        %0 = getelementptr [11 x i8]* @bytes, i32 0, i32 1
+        %0 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 1
         store volatile i8 %a, i8* %0
-        %1 = getelementptr [11 x double]* @doubles, i32 0, i32 1
+        %1 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 1
         store volatile double %b, double* %1
         ret void
 }
@@ -184,9 +184,9 @@ entry:
 
 define void @float_arg2(i8 %a, float %b) nounwind {
 entry:
-        %0 = getelementptr [11 x i8]* @bytes, i32 0, i32 1
+        %0 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 1
         store volatile i8 %a, i8* %0
-        %1 = getelementptr [11 x float]* @floats, i32 0, i32 1
+        %1 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 1
         store volatile float %b, float* %1
         ret void
 }
diff --git a/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll b/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll
index 5e3f403495f5..26eb569f865d 100644
--- a/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll
+++ b/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s
-; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s
+; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s
+; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s
 
-; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s
-; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s
+; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s
+; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s
 
 ; Test the fp128 arguments for all ABI's and byte orders as specified
 ; by section 2 of the MIPSpro N32 Handbook.
@@ -13,15 +13,15 @@
 
 define void @ldouble_args(fp128 %a, fp128 %b, fp128 %c, fp128 %d, fp128 %e) nounwind {
 entry:
-        %0 = getelementptr [11 x fp128]* @ldoubles, i32 0, i32 1
+        %0 = getelementptr [11 x fp128], [11 x fp128]* @ldoubles, i32 0, i32 1
         store volatile fp128 %a, fp128* %0
-        %1 = getelementptr [11 x fp128]* @ldoubles, i32 0, i32 2
+        %1 = getelementptr [11 x fp128], [11 x fp128]* @ldoubles, i32 0, i32 2
         store volatile fp128 %b, fp128* %1
-        %2 = getelementptr [11 x fp128]* @ldoubles, i32 0, i32 3
+        %2 = getelementptr [11 x fp128], [11 x fp128]* @ldoubles, i32 0, i32 3
         store volatile fp128 %c, fp128* %2
-        %3 = getelementptr [11 x fp128]* @ldoubles, i32 0, i32 4
+        %3 = getelementptr [11 x fp128], [11 x fp128]* @ldoubles, i32 0, i32 4
         store volatile fp128 %d, fp128* %3
-        %4 = getelementptr [11 x fp128]* @ldoubles, i32 0, i32 5
+        %4 = getelementptr [11 x fp128], [11 x fp128]* @ldoubles, i32 0, i32 5
         store volatile fp128 %e, fp128* %4
         ret void
 }
diff --git a/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll b/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll
index d17290e552e0..087a0515f379 100644
--- a/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll
+++ b/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll
@@ -52,8 +52,8 @@ entry:
   %0 = bitcast { i48 }* %s1_1.coerce to i8*
   %1 = bitcast %struct.S1* %s1_1 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 6, i32 0, i1 false)
-  %2 = getelementptr { i48 }* %s1_1.coerce, i32 0, i32 0
-  %3 = load i48* %2, align 1
+  %2 = getelementptr { i48 }, { i48 }* %s1_1.coerce, i32 0, i32 0
+  %3 = load i48, i48* %2, align 1
   call void @fS1(i48 inreg %3)
   ret void
  ; ALL-LABEL: f1:
@@ -69,8 +69,8 @@ entry:
   %0 = bitcast { i40 }* %s2_1.coerce to i8*
   %1 = bitcast %struct.S2* %s2_1 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 5, i32 0, i1 false)
-  %2 = getelementptr { i40 }* %s2_1.coerce, i32 0, i32 0
-  %3 = load i40* %2, align 1
+  %2 = getelementptr { i40 }, { i40 }* %s2_1.coerce, i32 0, i32 0
+  %3 = load i40, i40* %2, align 1
   call void @fS2(i40 inreg %3)
   ret void
  ; ALL-LABEL: f2:
diff --git a/test/CodeGen/Mips/cconv/arguments-struct.ll b/test/CodeGen/Mips/cconv/arguments-struct.ll
index c1bc84ee7a04..ee6bfaeb9537 100644
--- a/test/CodeGen/Mips/cconv/arguments-struct.ll
+++ b/test/CodeGen/Mips/cconv/arguments-struct.ll
@@ -1,14 +1,14 @@
 ; RUN: llc -mtriple=mips-unknown-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32-BE %s
 ; RUN: llc -mtriple=mipsel-unknown-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32-LE %s
 
-; RUN-TODO: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32-BE %s
-; RUN-TODO: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32-LE %s
+; RUN-TODO: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32-BE %s
+; RUN-TODO: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32-LE %s
 
-; RUN: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW-BE %s
-; RUN: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW-LE %s
+; RUN: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW-BE %s
+; RUN: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW-LE %s
 
-; RUN: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW-BE %s
-; RUN: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW-LE %s
+; RUN: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW-BE %s
+; RUN: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW-LE %s
 
 ; Test small structures for all ABI's and byte orders.
 ;
@@ -19,7 +19,7 @@
 
 define void @s_i8(i8 inreg %a) nounwind {
 entry:
-	store i8 %a, i8* getelementptr inbounds ([2 x i8]* @bytes, i32 0, i32 1)
+	store i8 %a, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @bytes, i32 0, i32 1)
         ret void
 }
 
diff --git a/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll
index 458b124c9927..ba3aeb598f50 100644
--- a/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll
+++ b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll
@@ -140,11 +140,11 @@ define void @smallStruct_1b(%struct.SmallStruct_1b* %ss) #0 {
 entry:
   %ss.addr = alloca %struct.SmallStruct_1b*, align 8
   store %struct.SmallStruct_1b* %ss, %struct.SmallStruct_1b** %ss.addr, align 8
-  %0 = load %struct.SmallStruct_1b** %ss.addr, align 8
+  %0 = load %struct.SmallStruct_1b*, %struct.SmallStruct_1b** %ss.addr, align 8
   %1 = bitcast %struct.SmallStruct_1b* %0 to { i8 }*
-  %2 = getelementptr { i8 }* %1, i32 0, i32 0
-  %3 = load i8* %2, align 1
-  call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i8 inreg %3)
+  %2 = getelementptr { i8 }, { i8 }* %1, i32 0, i32 0
+  %3 = load i8, i8* %2, align 1
+  call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i8 inreg %3)
   ret void
  ; CHECK-LABEL: smallStruct_1b: 
  ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 56
@@ -154,11 +154,11 @@ define void @smallStruct_2b(%struct.SmallStruct_2b* %ss) #0 {
 entry:
   %ss.addr = alloca %struct.SmallStruct_2b*, align 8
   store %struct.SmallStruct_2b* %ss, %struct.SmallStruct_2b** %ss.addr, align 8
-  %0 = load %struct.SmallStruct_2b** %ss.addr, align 8
+  %0 = load %struct.SmallStruct_2b*, %struct.SmallStruct_2b** %ss.addr, align 8
   %1 = bitcast %struct.SmallStruct_2b* %0 to { i16 }*
-  %2 = getelementptr { i16 }* %1, i32 0, i32 0
-  %3 = load i16* %2, align 1
-  call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i16 inreg %3)
+  %2 = getelementptr { i16 }, { i16 }* %1, i32 0, i32 0
+  %3 = load i16, i16* %2, align 1
+  call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i16 inreg %3)
   ret void
  ; CHECK-LABEL: smallStruct_2b:
  ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 48
@@ -169,13 +169,13 @@ entry:
   %ss.addr = alloca %struct.SmallStruct_3b*, align 8
   %.coerce = alloca { i24 }
   store %struct.SmallStruct_3b* %ss, %struct.SmallStruct_3b** %ss.addr, align 8
-  %0 = load %struct.SmallStruct_3b** %ss.addr, align 8
+  %0 = load %struct.SmallStruct_3b*, %struct.SmallStruct_3b** %ss.addr, align 8
   %1 = bitcast { i24 }* %.coerce to i8*
   %2 = bitcast %struct.SmallStruct_3b* %0 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 3, i32 0, i1 false)
-  %3 = getelementptr { i24 }* %.coerce, i32 0, i32 0
-  %4 = load i24* %3, align 1
-  call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i24 inreg %4)
+  %3 = getelementptr { i24 }, { i24 }* %.coerce, i32 0, i32 0
+  %4 = load i24, i24* %3, align 1
+  call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i24 inreg %4)
   ret void
  ; CHECK-LABEL: smallStruct_3b:
  ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 40
@@ -187,11 +187,11 @@ define void @smallStruct_4b(%struct.SmallStruct_4b* %ss) #0 {
 entry:
   %ss.addr = alloca %struct.SmallStruct_4b*, align 8
   store %struct.SmallStruct_4b* %ss, %struct.SmallStruct_4b** %ss.addr, align 8
-  %0 = load %struct.SmallStruct_4b** %ss.addr, align 8
+  %0 = load %struct.SmallStruct_4b*, %struct.SmallStruct_4b** %ss.addr, align 8
   %1 = bitcast %struct.SmallStruct_4b* %0 to { i32 }*
-  %2 = getelementptr { i32 }* %1, i32 0, i32 0
-  %3 = load i32* %2, align 1
-  call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i32 inreg %3)
+  %2 = getelementptr { i32 }, { i32 }* %1, i32 0, i32 0
+  %3 = load i32, i32* %2, align 1
+  call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i32 inreg %3)
   ret void
  ; CHECK-LABEL: smallStruct_4b:
  ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 32
@@ -202,13 +202,13 @@ entry:
   %ss.addr = alloca %struct.SmallStruct_5b*, align 8
   %.coerce = alloca { i40 }
   store %struct.SmallStruct_5b* %ss, %struct.SmallStruct_5b** %ss.addr, align 8
-  %0 = load %struct.SmallStruct_5b** %ss.addr, align 8
+  %0 = load %struct.SmallStruct_5b*, %struct.SmallStruct_5b** %ss.addr, align 8
   %1 = bitcast { i40 }* %.coerce to i8*
   %2 = bitcast %struct.SmallStruct_5b* %0 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 5, i32 0, i1 false)
-  %3 = getelementptr { i40 }* %.coerce, i32 0, i32 0
-  %4 = load i40* %3, align 1
-  call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i40 inreg %4)
+  %3 = getelementptr { i40 }, { i40 }* %.coerce, i32 0, i32 0
+  %4 = load i40, i40* %3, align 1
+  call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i40 inreg %4)
   ret void
  ; CHECK-LABEL: smallStruct_5b:
  ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 24
@@ -219,13 +219,13 @@ entry:
   %ss.addr = alloca %struct.SmallStruct_6b*, align 8
   %.coerce = alloca { i48 }
   store %struct.SmallStruct_6b* %ss, %struct.SmallStruct_6b** %ss.addr, align 8
-  %0 = load %struct.SmallStruct_6b** %ss.addr, align 8
+  %0 = load %struct.SmallStruct_6b*, %struct.SmallStruct_6b** %ss.addr, align 8
   %1 = bitcast { i48 }* %.coerce to i8*
   %2 = bitcast %struct.SmallStruct_6b* %0 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 6, i32 0, i1 false)
-  %3 = getelementptr { i48 }* %.coerce, i32 0, i32 0
-  %4 = load i48* %3, align 1
-  call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i48 inreg %4)
+  %3 = getelementptr { i48 }, { i48 }* %.coerce, i32 0, i32 0
+  %4 = load i48, i48* %3, align 1
+  call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i48 inreg %4)
   ret void
  ; CHECK-LABEL: smallStruct_6b:
  ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 16
@@ -236,13 +236,13 @@ entry:
   %ss.addr = alloca %struct.SmallStruct_7b*, align 8
   %.coerce = alloca { i56 }
   store %struct.SmallStruct_7b* %ss, %struct.SmallStruct_7b** %ss.addr, align 8
-  %0 = load %struct.SmallStruct_7b** %ss.addr, align 8
+  %0 = load %struct.SmallStruct_7b*, %struct.SmallStruct_7b** %ss.addr, align 8
   %1 = bitcast { i56 }* %.coerce to i8*
   %2 = bitcast %struct.SmallStruct_7b* %0 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 7, i32 0, i1 false)
-  %3 = getelementptr { i56 }* %.coerce, i32 0, i32 0
-  %4 = load i56* %3, align 1
-  call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i56 inreg %4)
+  %3 = getelementptr { i56 }, { i56 }* %.coerce, i32 0, i32 0
+  %4 = load i56, i56* %3, align 1
+  call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i56 inreg %4)
   ret void
  ; CHECK-LABEL: smallStruct_7b:
  ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 8
@@ -252,11 +252,11 @@ define void @smallStruct_8b(%struct.SmallStruct_8b* %ss) #0 {
 entry:
   %ss.addr = alloca %struct.SmallStruct_8b*, align 8
   store %struct.SmallStruct_8b* %ss, %struct.SmallStruct_8b** %ss.addr, align 8
-  %0 = load %struct.SmallStruct_8b** %ss.addr, align 8
+  %0 = load %struct.SmallStruct_8b*, %struct.SmallStruct_8b** %ss.addr, align 8
   %1 = bitcast %struct.SmallStruct_8b* %0 to { i64 }*
-  %2 = getelementptr { i64 }* %1, i32 0, i32 0
-  %3 = load i64* %2, align 1
-  call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i64 inreg %3)
+  %2 = getelementptr { i64 }, { i64 }* %1, i32 0, i32 0
+  %3 = load i64, i64* %2, align 1
+  call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i64 inreg %3)
   ret void
  ; CHECK-LABEL: smallStruct_8b:
  ; CHECK-NOT: dsll
@@ -267,15 +267,15 @@ entry:
   %ss.addr = alloca %struct.SmallStruct_9b*, align 8
   %.coerce = alloca { i64, i8 }
   store %struct.SmallStruct_9b* %ss, %struct.SmallStruct_9b** %ss.addr, align 8
-  %0 = load %struct.SmallStruct_9b** %ss.addr, align 8
+  %0 = load %struct.SmallStruct_9b*, %struct.SmallStruct_9b** %ss.addr, align 8
   %1 = bitcast { i64, i8 }* %.coerce to i8*
   %2 = bitcast %struct.SmallStruct_9b* %0 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 9, i32 0, i1 false)
-  %3 = getelementptr { i64, i8 }* %.coerce, i32 0, i32 0
-  %4 = load i64* %3, align 1
-  %5 = getelementptr { i64, i8 }* %.coerce, i32 0, i32 1
-  %6 = load i8* %5, align 1
-  call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i64 inreg %4, i8 inreg %6)
+  %3 = getelementptr { i64, i8 }, { i64, i8 }* %.coerce, i32 0, i32 0
+  %4 = load i64, i64* %3, align 1
+  %5 = getelementptr { i64, i8 }, { i64, i8 }* %.coerce, i32 0, i32 1
+  %6 = load i8, i8* %5, align 1
+  call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i64 inreg %4, i8 inreg %6)
   ret void
  ; CHECK-LABEL: smallStruct_9b:
  ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 56
diff --git a/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll
index 899a3e8ff0a1..74d3d859ed75 100644
--- a/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll
+++ b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll
@@ -74,11 +74,11 @@ define void @smallStruct_1b1s(%struct.SmallStruct_1b1s* %ss) #0 {
 entry:
   %ss.addr = alloca %struct.SmallStruct_1b1s*, align 8
   store %struct.SmallStruct_1b1s* %ss, %struct.SmallStruct_1b1s** %ss.addr, align 8
-  %0 = load %struct.SmallStruct_1b1s** %ss.addr, align 8
+  %0 = load %struct.SmallStruct_1b1s*, %struct.SmallStruct_1b1s** %ss.addr, align 8
   %1 = bitcast %struct.SmallStruct_1b1s* %0 to { i32 }*
-  %2 = getelementptr { i32 }* %1, i32 0, i32 0
-  %3 = load i32* %2, align 1
-  call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i32 inreg %3)
+  %2 = getelementptr { i32 }, { i32 }* %1, i32 0, i32 0
+  %3 = load i32, i32* %2, align 1
+  call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i32 inreg %3)
   ret void
  ; CHECK-LABEL: smallStruct_1b1s:
  ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 32
@@ -88,11 +88,11 @@ define void @smallStruct_1b1i(%struct.SmallStruct_1b1i* %ss) #0 {
 entry:
   %ss.addr = alloca %struct.SmallStruct_1b1i*, align 8
   store %struct.SmallStruct_1b1i* %ss, %struct.SmallStruct_1b1i** %ss.addr, align 8
-  %0 = load %struct.SmallStruct_1b1i** %ss.addr, align 8
+  %0 = load %struct.SmallStruct_1b1i*, %struct.SmallStruct_1b1i** %ss.addr, align 8
   %1 = bitcast %struct.SmallStruct_1b1i* %0 to { i64 }*
-  %2 = getelementptr { i64 }* %1, i32 0, i32 0
-  %3 = load i64* %2, align 1
-  call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i64 inreg %3)
+  %2 = getelementptr { i64 }, { i64 }* %1, i32 0, i32 0
+  %3 = load i64, i64* %2, align 1
+  call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i64 inreg %3)
   ret void
  ; CHECK-LABEL: smallStruct_1b1i:
  ; CHECK-NOT: dsll
@@ -103,13 +103,13 @@ entry:
   %ss.addr = alloca %struct.SmallStruct_1b1s1b*, align 8
   %.coerce = alloca { i48 }
   store %struct.SmallStruct_1b1s1b* %ss, %struct.SmallStruct_1b1s1b** %ss.addr, align 8
-  %0 = load %struct.SmallStruct_1b1s1b** %ss.addr, align 8
+  %0 = load %struct.SmallStruct_1b1s1b*, %struct.SmallStruct_1b1s1b** %ss.addr, align 8
   %1 = bitcast { i48 }* %.coerce to i8*
   %2 = bitcast %struct.SmallStruct_1b1s1b* %0 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 6, i32 0, i1 false)
-  %3 = getelementptr { i48 }* %.coerce, i32 0, i32 0
-  %4 = load i48* %3, align 1
-  call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i48 inreg %4)
+  %3 = getelementptr { i48 }, { i48 }* %.coerce, i32 0, i32 0
+  %4 = load i48, i48* %3, align 1
+  call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i48 inreg %4)
   ret void
  ; CHECK-LABEL: smallStruct_1b1s1b:
  ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 16
@@ -121,11 +121,11 @@ define void @smallStruct_1s1i(%struct.SmallStruct_1s1i* %ss) #0 {
 entry:
   %ss.addr = alloca %struct.SmallStruct_1s1i*, align 8
   store %struct.SmallStruct_1s1i* %ss, %struct.SmallStruct_1s1i** %ss.addr, align 8
-  %0 = load %struct.SmallStruct_1s1i** %ss.addr, align 8
+  %0 = load %struct.SmallStruct_1s1i*, %struct.SmallStruct_1s1i** %ss.addr, align 8
   %1 = bitcast %struct.SmallStruct_1s1i* %0 to { i64 }*
-  %2 = getelementptr { i64 }* %1, i32 0, i32 0
-  %3 = load i64* %2, align 1
-  call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i64 inreg %3)
+  %2 = getelementptr { i64 }, { i64 }* %1, i32 0, i32 0
+  %3 = load i64, i64* %2, align 1
+  call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i64 inreg %3)
   ret void
  ; CHECK-LABEL: smallStruct_1s1i:
  ; CHECK-NOT: dsll
@@ -136,13 +136,13 @@ entry:
   %ss.addr = alloca %struct.SmallStruct_3b1s*, align 8
   %.coerce = alloca { i48 }
   store %struct.SmallStruct_3b1s* %ss, %struct.SmallStruct_3b1s** %ss.addr, align 8
-  %0 = load %struct.SmallStruct_3b1s** %ss.addr, align 8
+  %0 = load %struct.SmallStruct_3b1s*, %struct.SmallStruct_3b1s** %ss.addr, align 8
   %1 = bitcast { i48 }* %.coerce to i8*
   %2 = bitcast %struct.SmallStruct_3b1s* %0 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 6, i32 0, i1 false)
-  %3 = getelementptr { i48 }* %.coerce, i32 0, i32 0
-  %4 = load i48* %3, align 1
-  call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i48 inreg %4)
+  %3 = getelementptr { i48 }, { i48 }* %.coerce, i32 0, i32 0
+  %4 = load i48, i48* %3, align 1
+  call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i48 inreg %4)
   ret void
  ; CHECK-LABEL: smallStruct_3b1s:
  ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 16
diff --git a/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll
index 1f7362523346..a4ac5e7bd8a6 100644
--- a/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll
+++ b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll
@@ -110,43 +110,43 @@ entry:
   store %struct.SmallStruct_1b* %ss7, %struct.SmallStruct_1b** %ss7.addr, align 8
   store %struct.SmallStruct_1b* %ss8, %struct.SmallStruct_1b** %ss8.addr, align 8
   store %struct.SmallStruct_1b* %ss9, %struct.SmallStruct_1b** %ss9.addr, align 8
-  %0 = load %struct.SmallStruct_1b** %ss1.addr, align 8
-  %1 = load %struct.SmallStruct_1b** %ss2.addr, align 8
-  %2 = load %struct.SmallStruct_1b** %ss3.addr, align 8
-  %3 = load %struct.SmallStruct_1b** %ss4.addr, align 8
-  %4 = load %struct.SmallStruct_1b** %ss5.addr, align 8
-  %5 = load %struct.SmallStruct_1b** %ss6.addr, align 8
-  %6 = load %struct.SmallStruct_1b** %ss7.addr, align 8
-  %7 = load %struct.SmallStruct_1b** %ss8.addr, align 8
-  %8 = load %struct.SmallStruct_1b** %ss9.addr, align 8
+  %0 = load %struct.SmallStruct_1b*, %struct.SmallStruct_1b** %ss1.addr, align 8
+  %1 = load %struct.SmallStruct_1b*, %struct.SmallStruct_1b** %ss2.addr, align 8
+  %2 = load %struct.SmallStruct_1b*, %struct.SmallStruct_1b** %ss3.addr, align 8
+  %3 = load %struct.SmallStruct_1b*, %struct.SmallStruct_1b** %ss4.addr, align 8
+  %4 = load %struct.SmallStruct_1b*, %struct.SmallStruct_1b** %ss5.addr, align 8
+  %5 = load %struct.SmallStruct_1b*, %struct.SmallStruct_1b** %ss6.addr, align 8
+  %6 = load %struct.SmallStruct_1b*, %struct.SmallStruct_1b** %ss7.addr, align 8
+  %7 = load %struct.SmallStruct_1b*, %struct.SmallStruct_1b** %ss8.addr, align 8
+  %8 = load %struct.SmallStruct_1b*, %struct.SmallStruct_1b** %ss9.addr, align 8
   %9 = bitcast %struct.SmallStruct_1b* %0 to { i8 }*
-  %10 = getelementptr { i8 }* %9, i32 0, i32 0
-  %11 = load i8* %10, align 1
+  %10 = getelementptr { i8 }, { i8 }* %9, i32 0, i32 0
+  %11 = load i8, i8* %10, align 1
   %12 = bitcast %struct.SmallStruct_1b* %1 to { i8 }*
-  %13 = getelementptr { i8 }* %12, i32 0, i32 0
-  %14 = load i8* %13, align 1
+  %13 = getelementptr { i8 }, { i8 }* %12, i32 0, i32 0
+  %14 = load i8, i8* %13, align 1
   %15 = bitcast %struct.SmallStruct_1b* %2 to { i8 }*
-  %16 = getelementptr { i8 }* %15, i32 0, i32 0
-  %17 = load i8* %16, align 1
+  %16 = getelementptr { i8 }, { i8 }* %15, i32 0, i32 0
+  %17 = load i8, i8* %16, align 1
   %18 = bitcast %struct.SmallStruct_1b* %3 to { i8 }*
-  %19 = getelementptr { i8 }* %18, i32 0, i32 0
-  %20 = load i8* %19, align 1
+  %19 = getelementptr { i8 }, { i8 }* %18, i32 0, i32 0
+  %20 = load i8, i8* %19, align 1
   %21 = bitcast %struct.SmallStruct_1b* %4 to { i8 }*
-  %22 = getelementptr { i8 }* %21, i32 0, i32 0
-  %23 = load i8* %22, align 1
+  %22 = getelementptr { i8 }, { i8 }* %21, i32 0, i32 0
+  %23 = load i8, i8* %22, align 1
   %24 = bitcast %struct.SmallStruct_1b* %5 to { i8 }*
-  %25 = getelementptr { i8 }* %24, i32 0, i32 0
-  %26 = load i8* %25, align 1
+  %25 = getelementptr { i8 }, { i8 }* %24, i32 0, i32 0
+  %26 = load i8, i8* %25, align 1
   %27 = bitcast %struct.SmallStruct_1b* %6 to { i8 }*
-  %28 = getelementptr { i8 }* %27, i32 0, i32 0
-  %29 = load i8* %28, align 1
+  %28 = getelementptr { i8 }, { i8 }* %27, i32 0, i32 0
+  %29 = load i8, i8* %28, align 1
   %30 = bitcast %struct.SmallStruct_1b* %7 to { i8 }*
-  %31 = getelementptr { i8 }* %30, i32 0, i32 0
-  %32 = load i8* %31, align 1
+  %31 = getelementptr { i8 }, { i8 }* %30, i32 0, i32 0
+  %32 = load i8, i8* %31, align 1
   %33 = bitcast %struct.SmallStruct_1b* %8 to { i8 }*
-  %34 = getelementptr { i8 }* %33, i32 0, i32 0
-  %35 = load i8* %34, align 1
-  call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i8 inreg %11, i8 inreg %14, i8 inreg %17, i8 inreg %20, i8 inreg %23, i8 inreg %26, i8 inreg %29, i8 inreg %32, i8 inreg %35)
+  %34 = getelementptr { i8 }, { i8 }* %33, i32 0, i32 0
+  %35 = load i8, i8* %34, align 1
+  call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i8 inreg %11, i8 inreg %14, i8 inreg %17, i8 inreg %20, i8 inreg %23, i8 inreg %26, i8 inreg %29, i8 inreg %32, i8 inreg %35)
   ret void
  ; CHECK-LABEL: smallStruct_1b_x9:
  ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 56
diff --git a/test/CodeGen/Mips/cconv/arguments-varargs.ll b/test/CodeGen/Mips/cconv/arguments-varargs.ll
index adacda5bc420..af217c92dab8 100644
--- a/test/CodeGen/Mips/cconv/arguments-varargs.ll
+++ b/test/CodeGen/Mips/cconv/arguments-varargs.ll
@@ -1,14 +1,14 @@
 ; RUN: llc -mtriple=mips-linux -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 --check-prefix=O32-BE %s
 ; RUN: llc -mtriple=mipsel-linux -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 --check-prefix=O32-LE %s
 
-; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
-; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 
-; RUN: llc -mtriple=mips64-linux -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N32 --check-prefix=NEW-BE %s
-; RUN: llc -mtriple=mips64el-linux -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N32 --check-prefix=NEW-LE %s
+; RUN: llc -mtriple=mips64-linux -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N32 --check-prefix=NEW-BE %s
+; RUN: llc -mtriple=mips64el-linux -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N32 --check-prefix=NEW-LE %s
 
-; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N64 --check-prefix=NEW-BE %s
-; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N64 --check-prefix=NEW-LE %s
+; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N64 --check-prefix=NEW-BE %s
+; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N64 --check-prefix=NEW-LE %s
 
 @hwords = global [3 x i16] zeroinitializer, align 1
 @words  = global [3 x i32] zeroinitializer, align 1
@@ -119,12 +119,12 @@ entry:
 
   call void asm sideeffect "# ANCHOR1", ""()
   %arg1 = va_arg i8** %ap, i16
-  %e1 = getelementptr [3 x i16]* @hwords, i32 0, i32 1
+  %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1
   store volatile i16 %arg1, i16* %e1, align 2
 
   call void asm sideeffect "# ANCHOR2", ""()
   %arg2 = va_arg i8** %ap, i16
-  %e2 = getelementptr [3 x i16]* @hwords, i32 0, i32 2
+  %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2
   store volatile i16 %arg2, i16* %e2, align 2
 
   call void @llvm.va_end(i8* %ap2)
@@ -237,12 +237,12 @@ entry:
 
   call void asm sideeffect "# ANCHOR1", ""()
   %arg1 = va_arg i8** %ap, i32
-  %e1 = getelementptr [3 x i32]* @words, i32 0, i32 1
+  %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1
   store volatile i32 %arg1, i32* %e1, align 4
 
   call void asm sideeffect "# ANCHOR2", ""()
   %arg2 = va_arg i8** %ap, i32
-  %e2 = getelementptr [3 x i32]* @words, i32 0, i32 2
+  %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2
   store volatile i32 %arg2, i32* %e2, align 4
 
   call void @llvm.va_end(i8* %ap2)
@@ -364,12 +364,12 @@ entry:
 
   call void asm sideeffect "# ANCHOR1", ""()
   %arg1 = va_arg i8** %ap, i64
-  %e1 = getelementptr [3 x i64]* @dwords, i32 0, i32 1
+  %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1
   store volatile i64 %arg1, i64* %e1, align 8
 
   call void asm sideeffect "# ANCHOR2", ""()
   %arg2 = va_arg i8** %ap, i64
-  %e2 = getelementptr [3 x i64]* @dwords, i32 0, i32 2
+  %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2
   store volatile i64 %arg2, i64* %e2, align 8
 
   call void @llvm.va_end(i8* %ap2)
@@ -482,12 +482,12 @@ entry:
 
   call void asm sideeffect "# ANCHOR1", ""()
   %arg1 = va_arg i8** %ap, i16
-  %e1 = getelementptr [3 x i16]* @hwords, i32 0, i32 1
+  %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1
   store volatile i16 %arg1, i16* %e1, align 2
 
   call void asm sideeffect "# ANCHOR2", ""()
   %arg2 = va_arg i8** %ap, i16
-  %e2 = getelementptr [3 x i16]* @hwords, i32 0, i32 2
+  %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2
   store volatile i16 %arg2, i16* %e2, align 2
 
   call void @llvm.va_end(i8* %ap2)
@@ -600,12 +600,12 @@ entry:
 
   call void asm sideeffect "# ANCHOR1", ""()
   %arg1 = va_arg i8** %ap, i32
-  %e1 = getelementptr [3 x i32]* @words, i32 0, i32 1
+  %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1
   store volatile i32 %arg1, i32* %e1, align 4
 
   call void asm sideeffect "# ANCHOR2", ""()
   %arg2 = va_arg i8** %ap, i32
-  %e2 = getelementptr [3 x i32]* @words, i32 0, i32 2
+  %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2
   store volatile i32 %arg2, i32* %e2, align 4
 
   call void @llvm.va_end(i8* %ap2)
@@ -727,12 +727,12 @@ entry:
 
   call void asm sideeffect "# ANCHOR1", ""()
   %arg1 = va_arg i8** %ap, i64
-  %e1 = getelementptr [3 x i64]* @dwords, i32 0, i32 1
+  %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1
   store volatile i64 %arg1, i64* %e1, align 8
 
   call void asm sideeffect "# ANCHOR2", ""()
   %arg2 = va_arg i8** %ap, i64
-  %e2 = getelementptr [3 x i64]* @dwords, i32 0, i32 2
+  %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2
   store volatile i64 %arg2, i64* %e2, align 8
 
   call void @llvm.va_end(i8* %ap2)
@@ -844,12 +844,12 @@ entry:
 
   call void asm sideeffect "# ANCHOR1", ""()
   %arg1 = va_arg i8** %ap, i16
-  %e1 = getelementptr [3 x i16]* @hwords, i32 0, i32 1
+  %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1
   store volatile i16 %arg1, i16* %e1, align 2
 
   call void asm sideeffect "# ANCHOR2", ""()
   %arg2 = va_arg i8** %ap, i16
-  %e2 = getelementptr [3 x i16]* @hwords, i32 0, i32 2
+  %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2
   store volatile i16 %arg2, i16* %e2, align 2
 
   call void @llvm.va_end(i8* %ap2)
@@ -961,12 +961,12 @@ entry:
 
   call void asm sideeffect "# ANCHOR1", ""()
   %arg1 = va_arg i8** %ap, i32
-  %e1 = getelementptr [3 x i32]* @words, i32 0, i32 1
+  %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1
   store volatile i32 %arg1, i32* %e1, align 4
 
   call void asm sideeffect "# ANCHOR2", ""()
   %arg2 = va_arg i8** %ap, i32
-  %e2 = getelementptr [3 x i32]* @words, i32 0, i32 2
+  %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2
   store volatile i32 %arg2, i32* %e2, align 4
 
   call void @llvm.va_end(i8* %ap2)
@@ -1087,12 +1087,12 @@ entry:
 
   call void asm sideeffect "# ANCHOR1", ""()
   %arg1 = va_arg i8** %ap, i64
-  %e1 = getelementptr [3 x i64]* @dwords, i32 0, i32 1
+  %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1
   store volatile i64 %arg1, i64* %e1, align 8
 
   call void asm sideeffect "# ANCHOR2", ""()
   %arg2 = va_arg i8** %ap, i64
-  %e2 = getelementptr [3 x i64]* @dwords, i32 0, i32 2
+  %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2
   store volatile i64 %arg2, i64* %e2, align 8
 
   call void @llvm.va_end(i8* %ap2)
diff --git a/test/CodeGen/Mips/cconv/arguments.ll b/test/CodeGen/Mips/cconv/arguments.ll
index 43da6044408b..430705f8d418 100644
--- a/test/CodeGen/Mips/cconv/arguments.ll
+++ b/test/CodeGen/Mips/cconv/arguments.ll
@@ -1,14 +1,14 @@
 ; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
 ; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
 
-; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
-; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
 
-; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s
-; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s
+; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s
+; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s
 
-; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s
-; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s
+; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s
+; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s
 
 ; Test the integer arguments for all ABI's and byte orders as specified by
 ; section 5 of MD00305 (MIPS ABIs Described).
@@ -28,25 +28,25 @@ define void @align_to_arg_slots(i8 signext %a, i8 signext %b, i8 signext %c,
                                 i8 signext %g, i8 signext %h, i8 signext %i,
                                 i8 signext %j) nounwind {
 entry:
-        %0 = getelementptr [11 x i8]* @bytes, i32 0, i32 1
+        %0 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 1
         store volatile i8 %a, i8* %0
-        %1 = getelementptr [11 x i8]* @bytes, i32 0, i32 2
+        %1 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 2
         store volatile i8 %b, i8* %1
-        %2 = getelementptr [11 x i8]* @bytes, i32 0, i32 3
+        %2 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 3
         store volatile i8 %c, i8* %2
-        %3 = getelementptr [11 x i8]* @bytes, i32 0, i32 4
+        %3 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 4
         store volatile i8 %d, i8* %3
-        %4 = getelementptr [11 x i8]* @bytes, i32 0, i32 5
+        %4 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 5
         store volatile i8 %e, i8* %4
-        %5 = getelementptr [11 x i8]* @bytes, i32 0, i32 6
+        %5 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 6
         store volatile i8 %f, i8* %5
-        %6 = getelementptr [11 x i8]* @bytes, i32 0, i32 7
+        %6 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 7
         store volatile i8 %g, i8* %6
-        %7 = getelementptr [11 x i8]* @bytes, i32 0, i32 8
+        %7 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 8
         store volatile i8 %h, i8* %7
-        %8 = getelementptr [11 x i8]* @bytes, i32 0, i32 9
+        %8 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 9
         store volatile i8 %i, i8* %8
-        %9 = getelementptr [11 x i8]* @bytes, i32 0, i32 10
+        %9 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 10
         store volatile i8 %j, i8* %9
         ret void
 }
@@ -95,23 +95,23 @@ define void @slot_skipping(i8 signext %a, i64 signext %b, i8 signext %c,
                            i8 signext %d, i8 signext %e, i8 signext %f,
                            i8 signext %g, i64 signext %i, i8 signext %j) nounwind {
 entry:
-        %0 = getelementptr [11 x i8]* @bytes, i32 0, i32 1
+        %0 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 1
         store volatile i8 %a, i8* %0
-        %1 = getelementptr [11 x i64]* @dwords, i32 0, i32 1
+        %1 = getelementptr [11 x i64], [11 x i64]* @dwords, i32 0, i32 1
         store volatile i64 %b, i64* %1
-        %2 = getelementptr [11 x i8]* @bytes, i32 0, i32 2
+        %2 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 2
         store volatile i8 %c, i8* %2
-        %3 = getelementptr [11 x i8]* @bytes, i32 0, i32 3
+        %3 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 3
         store volatile i8 %d, i8* %3
-        %4 = getelementptr [11 x i8]* @bytes, i32 0, i32 4
+        %4 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 4
         store volatile i8 %e, i8* %4
-        %5 = getelementptr [11 x i8]* @bytes, i32 0, i32 5
+        %5 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 5
         store volatile i8 %f, i8* %5
-        %6 = getelementptr [11 x i8]* @bytes, i32 0, i32 6
+        %6 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 6
         store volatile i8 %g, i8* %6
-        %7 = getelementptr [11 x i64]* @dwords, i32 0, i32 2
+        %7 = getelementptr [11 x i64], [11 x i64]* @dwords, i32 0, i32 2
         store volatile i64 %i, i64* %7
-        %8 = getelementptr [11 x i8]* @bytes, i32 0, i32 7
+        %8 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 7
         store volatile i8 %j, i8* %8
         ret void
 }
diff --git a/test/CodeGen/Mips/cconv/callee-saved-float.ll b/test/CodeGen/Mips/cconv/callee-saved-float.ll
index de4d9171aec4..c84f0f439c26 100644
--- a/test/CodeGen/Mips/cconv/callee-saved-float.ll
+++ b/test/CodeGen/Mips/cconv/callee-saved-float.ll
@@ -3,20 +3,20 @@
 ; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s
 ; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s
 
-; RUN-TODO: llc -march=mips64 -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
-; RUN-TODO: llc -march=mips64el -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
-; RUN-TODO: llc -march=mips64 -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=O32-INV %s
-; RUN-TODO: llc -march=mips64el -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=O32-INV %s
+; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=O32-INV %s
+; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=O32-INV %s
 
-; RUN: llc -march=mips64 -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
-; RUN: llc -march=mips64el -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
-; RUN: llc -march=mips64 -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N32-INV %s
-; RUN: llc -march=mips64el -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N32-INV %s
+; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N32-INV %s
+; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N32-INV %s
 
-; RUN: llc -march=mips64 -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
-; RUN: llc -march=mips64el -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
-; RUN: llc -march=mips64 -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N64-INV %s
-; RUN: llc -march=mips64el -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N64-INV %s
+; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N64-INV %s
+; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N64-INV %s
 
 ; Test the the callee-saved registers are callee-saved as specified by section
 ; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec.
diff --git a/test/CodeGen/Mips/cconv/callee-saved.ll b/test/CodeGen/Mips/cconv/callee-saved.ll
index 293e99f0c8e6..d0b1e64cdeea 100644
--- a/test/CodeGen/Mips/cconv/callee-saved.ll
+++ b/test/CodeGen/Mips/cconv/callee-saved.ll
@@ -3,20 +3,20 @@
 ; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s
 ; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s
 
-; RUN-TODO: llc -march=mips64 -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
-; RUN-TODO: llc -march=mips64el -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
-; RUN-TODO: llc -march=mips64 -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s
-; RUN-TODO: llc -march=mips64el -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s
+; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s
+; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s
 
-; RUN: llc -march=mips64 -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
-; RUN: llc -march=mips64el -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
-; RUN: llc -march=mips64 -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32-INV %s
-; RUN: llc -march=mips64el -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32-INV %s
+; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32-INV %s
+; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32-INV %s
 
-; RUN: llc -march=mips64 -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
-; RUN: llc -march=mips64el -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
-; RUN: llc -march=mips64 -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64-INV %s
-; RUN: llc -march=mips64el -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64-INV %s
+; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64-INV %s
+; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64-INV %s
 
 ; Test the the callee-saved registers are callee-saved as specified by section
 ; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec.
diff --git a/test/CodeGen/Mips/cconv/memory-layout.ll b/test/CodeGen/Mips/cconv/memory-layout.ll
index 0c3cc9ecedfe..33a68da157f6 100644
--- a/test/CodeGen/Mips/cconv/memory-layout.ll
+++ b/test/CodeGen/Mips/cconv/memory-layout.ll
@@ -1,14 +1,14 @@
 ; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 ; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 
-; RUN-TODO: llc -march=mips64 -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
-; RUN-TODO: llc -march=mips64el -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 
-; RUN: llc -march=mips64 -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
-; RUN: llc -march=mips64el -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
 
-; RUN: llc -march=mips64 -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
-; RUN: llc -march=mips64el -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
 
 ; Test the memory layout for all ABI's and byte orders as specified by section
 ; 4 of MD00305 (MIPS ABIs Described).
diff --git a/test/CodeGen/Mips/cconv/reserved-space.ll b/test/CodeGen/Mips/cconv/reserved-space.ll
index b36f89ecc115..23190c2790cc 100644
--- a/test/CodeGen/Mips/cconv/reserved-space.ll
+++ b/test/CodeGen/Mips/cconv/reserved-space.ll
@@ -1,14 +1,14 @@
 ; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 ; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 
-; RUN-TODO: llc -march=mips64 -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
-; RUN-TODO: llc -march=mips64el -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 
-; RUN: llc -march=mips64 -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
-; RUN: llc -march=mips64el -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
 
-; RUN: llc -march=mips64 -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
-; RUN: llc -march=mips64el -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
 
 ; Test that O32 correctly reserved space for the four arguments, even when
 ; there aren't any as per section 5 of MD00305 (MIPS ABIs Described).
diff --git a/test/CodeGen/Mips/cconv/return-float.ll b/test/CodeGen/Mips/cconv/return-float.ll
index d1a5e4f2fa9d..8eb8c411e081 100644
--- a/test/CodeGen/Mips/cconv/return-float.ll
+++ b/test/CodeGen/Mips/cconv/return-float.ll
@@ -1,14 +1,14 @@
-; RUN: llc -mtriple=mips-linux-gnu -soft-float -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
-; RUN: llc -mtriple=mipsel-linux-gnu -soft-float -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN: llc -mtriple=mips-linux-gnu -mattr=+soft-float -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN: llc -mtriple=mipsel-linux-gnu -mattr=+soft-float -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 
-; RUN-TODO: llc -mtriple=mips64-linux-gnu -soft-float -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
-; RUN-TODO: llc -mtriple=mips64el-linux-gnu -soft-float -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -mtriple=mips64-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -mtriple=mips64el-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 
-; RUN: llc -mtriple=mips64-linux-gnu -soft-float -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
-; RUN: llc -mtriple=mips64el-linux-gnu -soft-float -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -mtriple=mips64-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -mtriple=mips64el-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
 
-; RUN: llc -mtriple=mips64-linux-gnu -soft-float -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
-; RUN: llc -mtriple=mips64el-linux-gnu -soft-float -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -mtriple=mips64-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -mtriple=mips64el-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
 
 ; Test the float returns for all ABI's and byte orders as specified by
 ; section 5 of MD00305 (MIPS ABIs Described).
@@ -21,7 +21,7 @@
 
 define float @retfloat() nounwind {
 entry:
-        %0 = load volatile float* @float
+        %0 = load volatile float, float* @float
         ret float %0
 }
 
@@ -35,7 +35,7 @@ entry:
 
 define double @retdouble() nounwind {
 entry:
-        %0 = load volatile double* @double
+        %0 = load volatile double, double* @double
         ret double %0
 }
 
diff --git a/test/CodeGen/Mips/cconv/return-hard-float.ll b/test/CodeGen/Mips/cconv/return-hard-float.ll
index 123b499185a9..14853c8ca6f7 100644
--- a/test/CodeGen/Mips/cconv/return-hard-float.ll
+++ b/test/CodeGen/Mips/cconv/return-hard-float.ll
@@ -1,14 +1,14 @@
 ; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 ; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 
-; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
-; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 
-; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
-; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
 
-; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
-; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
 
 ; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=ALL --check-prefix=032FP64 %s
 ; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=ALL --check-prefix=032FP64 %s
@@ -24,7 +24,7 @@
 
 define float @retfloat() nounwind {
 entry:
-        %0 = load volatile float* @float
+        %0 = load volatile float, float* @float
         ret float %0
 }
 
@@ -38,7 +38,7 @@ entry:
 
 define double @retdouble() nounwind {
 entry:
-        %0 = load volatile double* @double
+        %0 = load volatile double, double* @double
         ret double %0
 }
 
@@ -50,7 +50,7 @@ entry:
 
 define { double, double } @retComplexDouble() #0 {
   %retval = alloca { double, double }, align 8
-  %1 = load { double, double }* %retval
+  %1 = load { double, double }, { double, double }* %retval
   ret { double, double } %1
 }
 
diff --git a/test/CodeGen/Mips/cconv/return-hard-fp128.ll b/test/CodeGen/Mips/cconv/return-hard-fp128.ll
index 0da59efddd6c..34e9647acddd 100644
--- a/test/CodeGen/Mips/cconv/return-hard-fp128.ll
+++ b/test/CodeGen/Mips/cconv/return-hard-fp128.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
-; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
 
-; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
-; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
 
 ; Test the fp128 returns for N32/N64 and all byte orders as specified by
 ; section 5 of MD00305 (MIPS ABIs Described).
@@ -13,7 +13,7 @@
 
 define fp128 @retldouble() nounwind {
 entry:
-        %0 = load volatile fp128* @fp128
+        %0 = load volatile fp128, fp128* @fp128
         ret fp128 %0
 }
 
diff --git a/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll b/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll
index 2e8447710281..c4c8f10ca3b4 100644
--- a/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll
+++ b/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll
@@ -1,8 +1,8 @@
-; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
-; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
 
-; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
-; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
 
 ; Test return of {fp128} agrees with de-facto N32/N64 ABI.
 
@@ -10,7 +10,7 @@
 
 define inreg {fp128} @ret_struct_fp128() nounwind {
 entry:
-        %0 = load volatile {fp128}* @struct_fp128
+        %0 = load volatile {fp128}, {fp128}* @struct_fp128
         ret {fp128} %0
 }
 
diff --git a/test/CodeGen/Mips/cconv/return-struct.ll b/test/CodeGen/Mips/cconv/return-struct.ll
index 11a8cf032148..8decd04f089b 100644
--- a/test/CodeGen/Mips/cconv/return-struct.ll
+++ b/test/CodeGen/Mips/cconv/return-struct.ll
@@ -1,14 +1,14 @@
 ; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 --check-prefix=O32-BE %s
 ; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 --check-prefix=O32-LE %s
 
-; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
-; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 
-; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 --check-prefix=N32-BE %s
-; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 --check-prefix=N32-LE %s
+; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 --check-prefix=N32-BE %s
+; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 --check-prefix=N32-LE %s
 
-; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 --check-prefix=N64-BE %s
-; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 --check-prefix=N64-LE %s
+; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 --check-prefix=N64-BE %s
+; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 --check-prefix=N64-LE %s
 
 ; Test struct returns for all ABI's and byte orders.
 
@@ -22,7 +22,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i
 
 define inreg {i8} @ret_struct_i8() nounwind {
 entry:
-        %0 = load volatile {i8}* @struct_byte
+        %0 = load volatile {i8}, {i8}* @struct_byte
         ret {i8} %0
 }
 
@@ -52,9 +52,9 @@ define inreg {i16} @ret_struct_i16() nounwind {
 entry:
         %retval = alloca {i8,i8}, align 1
         %0 = bitcast {i8,i8}* %retval to i8*
-        call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* getelementptr inbounds ({i8,i8}* @struct_2byte, i32 0, i32 0), i64 2, i32 1, i1 false)
+        call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* getelementptr inbounds ({i8,i8}, {i8,i8}* @struct_2byte, i32 0, i32 0), i64 2, i32 1, i1 false)
         %1 = bitcast {i8,i8}* %retval to {i16}*
-        %2 = load volatile {i16}* %1
+        %2 = load volatile {i16}, {i16}* %1
         ret {i16} %2
 }
 
@@ -91,7 +91,7 @@ entry:
 ; missed by the CCPromoteToType and the shift didn't happen.
 define inreg {i48} @ret_struct_3xi16() nounwind {
 entry:
-        %0 = load volatile i48* bitcast ({[3 x i16]}* @struct_3xi16 to i48*), align 2
+        %0 = load volatile i48, i48* bitcast ({[3 x i16]}* @struct_3xi16 to i48*), align 2
         %1 = insertvalue {i48} undef, i48 %0, 0
         ret {i48} %1
 }
@@ -174,7 +174,7 @@ entry:
 ; This time we let the backend lower the sret argument.
 define {[6 x i32]} @ret_struct_6xi32() {
 entry:
-        %0 = load volatile {[6 x i32]}* @struct_6xi32, align 2
+        %0 = load volatile {[6 x i32]}, {[6 x i32]}* @struct_6xi32, align 2
         ret {[6 x i32]} %0
 }
 
diff --git a/test/CodeGen/Mips/cconv/return.ll b/test/CodeGen/Mips/cconv/return.ll
index 63f9b5f45a18..a53767275434 100644
--- a/test/CodeGen/Mips/cconv/return.ll
+++ b/test/CodeGen/Mips/cconv/return.ll
@@ -1,14 +1,14 @@
 ; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 ; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 
-; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
-; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 
-; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
-; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
 
-; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
-; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
 
 ; Test the integer returns for all ABI's and byte orders as specified by
 ; section 5 of MD00305 (MIPS ABIs Described).
@@ -24,7 +24,7 @@
 
 define i8 @reti8() nounwind {
 entry:
-        %0 = load volatile i8* @byte
+        %0 = load volatile i8, i8* @byte
         ret i8 %0
 }
 
@@ -38,7 +38,7 @@ entry:
 
 define i32 @reti32() nounwind {
 entry:
-        %0 = load volatile i32* @word
+        %0 = load volatile i32, i32* @word
         ret i32 %0
 }
 
@@ -52,7 +52,7 @@ entry:
 
 define i64 @reti64() nounwind {
 entry:
-        %0 = load volatile i64* @dword
+        %0 = load volatile i64, i64* @dword
         ret i64 %0
 }
 
diff --git a/test/CodeGen/Mips/cconv/stack-alignment.ll b/test/CodeGen/Mips/cconv/stack-alignment.ll
index 834033bc8da5..f21bc3066f72 100644
--- a/test/CodeGen/Mips/cconv/stack-alignment.ll
+++ b/test/CodeGen/Mips/cconv/stack-alignment.ll
@@ -1,14 +1,14 @@
 ; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 ; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 
-; RUN-TODO: llc -march=mips64 -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
-; RUN-TODO: llc -march=mips64el -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
+; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s
 
-; RUN: llc -march=mips64 -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
-; RUN: llc -march=mips64el -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
+; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s
 
-; RUN: llc -march=mips64 -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
-; RUN: llc -march=mips64el -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
+; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
 
 ; Test the stack alignment for all ABI's and byte orders as specified by
 ; section 5 of MD00305 (MIPS ABIs Described).
diff --git a/test/CodeGen/Mips/cfi_offset.ll b/test/CodeGen/Mips/cfi_offset.ll
index e23855bd65d2..97233328fd55 100644
--- a/test/CodeGen/Mips/cfi_offset.ll
+++ b/test/CodeGen/Mips/cfi_offset.ll
@@ -32,9 +32,9 @@ define void @bar() {
 ; CHECK:  .cfi_offset 31, -20
 ; CHECK:  .cfi_offset 16, -24
 
-    %val1 = load volatile double* @var
-    %val2 = load volatile double* @var
-    call void (...)* @foo() nounwind
+    %val1 = load volatile double, double* @var
+    %val2 = load volatile double, double* @var
+    call void (...) @foo() nounwind
     store volatile double %val1, double* @var
     store volatile double %val2, double* @var
     ret void
diff --git a/test/CodeGen/Mips/check-adde-redundant-moves.ll b/test/CodeGen/Mips/check-adde-redundant-moves.ll
index 527c21770263..7bc63a494ac7 100644
--- a/test/CodeGen/Mips/check-adde-redundant-moves.ll
+++ b/test/CodeGen/Mips/check-adde-redundant-moves.ll
@@ -4,12 +4,18 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefix=ALL
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL
 
 define i64 @add_i64(i64 %a) {
diff --git a/test/CodeGen/Mips/ci2.ll b/test/CodeGen/Mips/ci2.ll
index e2068fdf14e1..4687748879ac 100644
--- a/test/CodeGen/Mips/ci2.ll
+++ b/test/CodeGen/Mips/ci2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands   < %s | FileCheck %s -check-prefix=constisle
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands   < %s | FileCheck %s -check-prefix=constisle
 
 @i = common global i32 0, align 4
 @b = common global i32 0, align 4
@@ -8,7 +8,7 @@
 define void @foo() #0 {
 entry:
   store i32 305419896, i32* @i, align 4
-  %0 = load i32* @b, align 4
+  %0 = load i32, i32* @b, align 4
   %tobool = icmp ne i32 %0, 0
   br i1 %tobool, label %if.then, label %if.else
 
diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll
index b12c2df97c19..a8008a2cb29f 100755
--- a/test/CodeGen/Mips/cmov.ll
+++ b/test/CodeGen/Mips/cmov.ll
@@ -41,8 +41,8 @@
 define i32* @cmov1(i32 signext %s) nounwind readonly {
 entry:
   %tobool = icmp ne i32 %s, 0
-  %tmp1 = load i32** @i3, align 4
-  %cond = select i1 %tobool, i32* getelementptr inbounds ([3 x i32]* @i1, i32 0, i32 0), i32* %tmp1
+  %tmp1 = load i32*, i32** @i3, align 4
+  %cond = select i1 %tobool, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @i1, i32 0, i32 0), i32* %tmp1
   ret i32* %cond
 }
 
@@ -81,8 +81,8 @@ entry:
 define i32 @cmov2(i32 signext %s) nounwind readonly {
 entry:
   %tobool = icmp ne i32 %s, 0
-  %tmp1 = load i32* @c, align 4
-  %tmp2 = load i32* @d, align 4
+  %tmp1 = load i32, i32* @c, align 4
+  %tmp2 = load i32, i32* @d, align 4
   %cond = select i1 %tobool, i32 %tmp1, i32 %tmp2
   ret i32 %cond
 }
diff --git a/test/CodeGen/Mips/cmplarge.ll b/test/CodeGen/Mips/cmplarge.ll
index 2a3d30a95492..79019065a905 100644
--- a/test/CodeGen/Mips/cmplarge.ll
+++ b/test/CodeGen/Mips/cmplarge.ll
@@ -9,8 +9,8 @@ target triple = "mipsel--linux-gnu"
 
 define void @getSubImagesLuma(%struct.StorablePicture* nocapture %s) #0 {
 entry:
-  %size_y = getelementptr inbounds %struct.StorablePicture* %s, i32 0, i32 1
-  %0 = load i32* %size_y, align 4
+  %size_y = getelementptr inbounds %struct.StorablePicture, %struct.StorablePicture* %s, i32 0, i32 1
+  %0 = load i32, i32* %size_y, align 4
   %sub = add nsw i32 %0, -1
   %add5 = add nsw i32 %0, 20
   %cmp6 = icmp sgt i32 %add5, -20
@@ -20,7 +20,7 @@ for.body:                                         ; preds = %entry, %for.body
   %j.07 = phi i32 [ %inc, %for.body ], [ -20, %entry ]
   %call = tail call i32 bitcast (i32 (...)* @iClip3 to i32 (i32, i32, i32)*)(i32 0, i32 %sub, i32 %j.07) #2
   %inc = add nsw i32 %j.07, 1
-  %1 = load i32* %size_y, align 4
+  %1 = load i32, i32* %size_y, align 4
   %add = add nsw i32 %1, 20
   %cmp = icmp slt i32 %inc, %add
   br i1 %cmp, label %for.body, label %for.end
diff --git a/test/CodeGen/Mips/const1.ll b/test/CodeGen/Mips/const1.ll
index f32ce244cf40..1a5d58bd3f95 100644
--- a/test/CodeGen/Mips/const1.ll
+++ b/test/CodeGen/Mips/const1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s 
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s 
 
 ; ModuleID = 'const1.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"
diff --git a/test/CodeGen/Mips/const4a.ll b/test/CodeGen/Mips/const4a.ll
index ac6795b2c833..c31e54a01036 100644
--- a/test/CodeGen/Mips/const4a.ll
+++ b/test/CodeGen/Mips/const4a.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands -mips-constant-islands-no-load-relaxation  < %s | FileCheck %s -check-prefix=no-load-relax
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands -mips-constant-islands-no-load-relaxation  < %s | FileCheck %s -check-prefix=no-load-relax
 
 ; ModuleID = 'const4.c'
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"
@@ -14,7 +14,7 @@ target triple = "mips--linux-gnu"
 define void @t() #0 {
 entry:
   store i32 -559023410, i32* @i, align 4
-  %0 = load i32* @b, align 4
+  %0 = load i32, i32* @b, align 4
 ; no-load-relax:	lw	${{[0-9]+}}, $CPI0_1	# 16 bit inst
   %tobool = icmp ne i32 %0, 0
   br i1 %tobool, label %if.then, label %if.else
diff --git a/test/CodeGen/Mips/const6.ll b/test/CodeGen/Mips/const6.ll
index c26e02f2ebba..49e98ea78703 100644
--- a/test/CodeGen/Mips/const6.ll
+++ b/test/CodeGen/Mips/const6.ll
@@ -1,6 +1,6 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=load-relax
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=load-relax
 
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands -mips-constant-islands-no-load-relaxation  < %s | FileCheck %s -check-prefix=no-load-relax
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands -mips-constant-islands-no-load-relaxation  < %s | FileCheck %s -check-prefix=no-load-relax
 
 ; ModuleID = 'const6.c'
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"
diff --git a/test/CodeGen/Mips/const6a.ll b/test/CodeGen/Mips/const6a.ll
index aff1357c3a8f..54a3f2234dc2 100644
--- a/test/CodeGen/Mips/const6a.ll
+++ b/test/CodeGen/Mips/const6a.ll
@@ -1,6 +1,6 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=load-relax1
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=load-relax1
 
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=load-relax
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=load-relax
 
 ; ModuleID = 'const6a.c'
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"
diff --git a/test/CodeGen/Mips/ctlz.ll b/test/CodeGen/Mips/ctlz.ll
index 1f871664a6cf..96af1973b196 100644
--- a/test/CodeGen/Mips/ctlz.ll
+++ b/test/CodeGen/Mips/ctlz.ll
@@ -9,7 +9,7 @@ define i32 @main() #0 {
 entry:
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
-  %0 = load i32* @x, align 4
+  %0 = load i32, i32* @x, align 4
   %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 true)
   store i32 %1, i32* @y, align 4
   ret i32 0
diff --git a/test/CodeGen/Mips/dagcombine_crash.ll b/test/CodeGen/Mips/dagcombine_crash.ll
new file mode 100644
index 000000000000..6fcf2b4e68b4
--- /dev/null
+++ b/test/CodeGen/Mips/dagcombine_crash.ll
@@ -0,0 +1,25 @@
+; RUN: llc -o - %s | FileCheck %s
+; The selection DAG select(select()) normalisation crashed for different types
+; on the condition inputs.
+target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
+target triple = "mips--"
+
+; CHECK-LABEL: foobar
+; CHECK: sltiu ${{[0-9]*}}, ${{[0-9]*}}, 42
+; CHECK: sltiu ${{[0-9]*}}, ${{[0-9]*}}, 23
+; CHECK: and ${{[0-9]*}}, ${{[0-9]*}}, ${{[0-9]*}}
+; CHECK: sltu ${{[0-9]*}}, ${{[0-9]*}}, ${{[0-9]*}}
+; CHECK: addiu ${{[0-9]*}}, ${{[0-9]*}}, -1
+; CHECK: movn ${{[0-9]*}}, ${{[0-9]*}}, ${{[0-9]*}}
+; CHECK: jr $ra
+; CHECK: move ${{[0-9]*}}, ${{[0-9]*}}
+define i64 @foobar(i32 %arg) #0 {
+entry:
+  %cmp0 = icmp ult i32 %arg, 23
+  %cmp1 = icmp ult i32 %arg, 42
+  %and = and i1 %cmp0, %cmp1
+  %cmp2 = icmp ugt i32 %arg, 0
+  %sext = sext i1 %cmp1 to i64
+  %retval.0 = select i1 %and, i64 %sext, i64 0
+  ret i64 %retval.0
+}
diff --git a/test/CodeGen/Mips/delay-slot-fill-forward.ll b/test/CodeGen/Mips/delay-slot-fill-forward.ll
new file mode 100644
index 000000000000..7fc011da92db
--- /dev/null
+++ b/test/CodeGen/Mips/delay-slot-fill-forward.ll
@@ -0,0 +1,183 @@
+; RUN: llc < %s -march=mips -mcpu=mips32r2 -O2 \
+; RUN:     -disable-mips-df-forward-search=false \
+; RUN:     -disable-mips-df-succbb-search=false \
+; RUN:     -relocation-model=static | FileCheck %s
+
+; This test was generated with bugpoint from
+; MultiSource/Applications/JM/lencod/me_fullsearch.c
+
+%struct.SubImageContainer = type { i16****, [2 x i16****] }
+%struct.storable_picture = type { i32, i32, i32, i32, i32, i32,
+  [6 x [33 x i64]], [6 x [33 x i64]], [6 x [33 x i64]], [6 x [33 x i64]],
+  i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
+  i32, i32, i32, i32, i32, i16**, i16****, i16****, i16*****, i16***,
+  i8*, i8***, i64***, i64***, i16****, i8**, i8**, %struct.storable_picture*,
+  %struct.storable_picture*, %struct.storable_picture*,
+  i32, i32, i32, i32, i32, i32, i32 }
+
+@img_height = external global i16, align 2
+@width_pad = external global i32, align 4
+@height_pad = external global i32, align 4
+@mvbits = external global i32*, align 4
+@ref_pic1_sub = external global %struct.SubImageContainer, align 4
+@ref_pic2_sub = external global %struct.SubImageContainer, align 4
+@wbp_weight = external global i32****, align 4
+@weight1 = external global i16, align 2
+@weight2 = external global i16, align 2
+@offsetBi = external global i16, align 2
+@computeBiPred2 = external global [3 x i32 (i16*, i32, i32, i32, i32, i32, i32, i32)*], align 4
+@computeBiPred = external global i32 (i16*, i32, i32, i32, i32, i32, i32, i32)*, align 4
+@bipred2_access_method = external global i32, align 4
+@start_me_refinement_hp = external global i32, align 4
+
+declare i32 @foobar(i16*, i32 signext , i32 signext , i32 signext ,
+                    i32 signext , i32 signext , i32 signext , i32 signext ) #1
+
+define void @SubPelBlockSearchBiPred(i16* %orig_pic, i16 signext %ref,
+    i32 signext %pic_pix_x, i32 signext %pic_pix_y, i16 signext %pred_mv_y,
+    i16* nocapture %mv_x, i16* nocapture %mv_y, i16* nocapture readonly %s_mv_x,
+    i32 signext %search_pos2, i32 signext %min_mcost) #0 {
+; CHECK-LABEL: SubPelBlockSearchBiPred:
+entry:
+  %add40 = shl i32 %pic_pix_x, 2
+  %shl = add i32 %add40, 80
+  %add41 = shl i32 %pic_pix_y, 2
+  %0 = load i32, i32* @start_me_refinement_hp, align 4, !tbaa !1
+  %cond47 = select i1 undef, i32 1, i32 %search_pos2
+  %1 = load i16, i16* %s_mv_x, align 2, !tbaa !5
+  %conv48 = sext i16 %1 to i32
+  %add49 = add nsw i32 %conv48, %shl
+  %idxprom52 = sext i16 %ref to i32
+  %2 = load i32, i32* null, align 4, !tbaa !1
+  store i32 undef, i32* bitcast (%struct.SubImageContainer* @ref_pic1_sub to i32*), align 4, !tbaa !7
+  %3 = load i32, i32* undef, align 4, !tbaa !10
+  store i32 %3, i32* bitcast (%struct.SubImageContainer* @ref_pic2_sub to i32*), align 4, !tbaa !7
+  store i16 0, i16* @img_height, align 2, !tbaa !5
+  %size_x_pad = getelementptr inbounds %struct.storable_picture, %struct.storable_picture* null, i32 0, i32 22
+  %4 = load i32, i32* %size_x_pad, align 4, !tbaa !12
+  store i32 %4, i32* @width_pad, align 4, !tbaa !1
+  %5 = load i32, i32* undef, align 4, !tbaa !13
+  store i32 %5, i32* @height_pad, align 4, !tbaa !1
+  %6 = load i32****, i32***** @wbp_weight, align 4, !tbaa !14
+  %arrayidx75 = getelementptr inbounds i32***, i32**** %6, i32 undef
+  %7 = load i32***, i32**** %arrayidx75, align 4, !tbaa !14
+  %arrayidx76 = getelementptr inbounds i32**, i32*** %7, i32 %idxprom52
+  %8 = load i32**, i32*** %arrayidx76, align 4, !tbaa !14
+  %cond87.in671 = load i32*, i32** %8, align 4
+  %cond87672 = load i32, i32* %cond87.in671, align 4
+  %conv88673 = trunc i32 %cond87672 to i16
+  store i16 %conv88673, i16* @weight1, align 2, !tbaa !5
+  %cond105 = load i32, i32* undef, align 4
+  %conv106 = trunc i32 %cond105 to i16
+  store i16 %conv106, i16* @weight2, align 2, !tbaa !5
+  store i16 0, i16* @offsetBi, align 2, !tbaa !5
+  %storemerge655 = load i32, i32* bitcast (i32 (i16*, i32, i32, i32, i32, i32, i32, i32)** getelementptr inbounds ([3 x i32 (i16*, i32, i32, i32, i32, i32, i32, i32)*], [3 x i32 (i16*, i32, i32, i32, i32, i32, i32, i32)*]* @computeBiPred2, i32 0, i32 1) to i32*), align 4
+  store i32 %storemerge655, i32* bitcast (i32 (i16*, i32, i32, i32, i32, i32, i32, i32)** @computeBiPred to i32*), align 4, !tbaa !14
+  %9 = load i16, i16* %mv_x, align 2, !tbaa !5
+  %cmp270 = icmp sgt i32 undef, 1
+  %or.cond = and i1 %cmp270, false
+  br i1 %or.cond, label %land.lhs.true277, label %if.else289
+
+land.lhs.true277:                                 ; preds = %entry
+  %10 = load i16, i16* %mv_y, align 2, !tbaa !5
+  %conv278 = sext i16 %10 to i32
+  %add279 = add nsw i32 %conv278, 0
+  %cmp280 = icmp sgt i32 %add279, 1
+  %or.cond660 = and i1 %cmp280, undef
+  br i1 %or.cond660, label %if.end290, label %if.else289
+
+if.else289:                                       ; preds = %land.lhs.true277, %entry
+  br label %if.end290
+
+if.end290:                                        ; preds = %if.else289, %land.lhs.true277
+  %storemerge = phi i32 [ 1, %if.else289 ], [ 0, %land.lhs.true277 ]
+  store i32 %storemerge, i32* @bipred2_access_method, align 4, !tbaa !1
+  %cmp315698 = icmp slt i32 %0, %cond47
+  br i1 %cmp315698, label %for.body.lr.ph, label %if.end358
+
+for.body.lr.ph:                                   ; preds = %if.end290
+  %conv328 = sext i16 %pred_mv_y to i32
+  br label %for.body
+
+for.body:                                         ; preds = %for.inc, %for.body.lr.ph
+  %11 = phi i16 [ %9, %for.body.lr.ph ], [ %.pre, %for.inc ]
+  %min_mcost.addr.0701 = phi i32 [ %min_mcost, %for.body.lr.ph ], [ undef, %for.inc ]
+  %pos.0700 = phi i32 [ %0, %for.body.lr.ph ], [ undef, %for.inc ]
+  %best_pos.0699 = phi i32 [ 0, %for.body.lr.ph ], [ %best_pos.1, %for.inc ]
+  %conv317 = sext i16 %11 to i32
+  %add320 = add nsw i32 0, %conv317
+  %12 = load i16, i16* %mv_y, align 2, !tbaa !5
+  %conv321 = sext i16 %12 to i32
+  %add324 = add nsw i32 0, %conv321
+  %13 = load i32*, i32** @mvbits, align 4, !tbaa !14
+  %14 = load i32, i32* undef, align 4, !tbaa !1
+  %sub329 = sub nsw i32 %add324, %conv328
+  %arrayidx330 = getelementptr inbounds i32, i32* %13, i32 %sub329
+  %15 = load i32, i32* %arrayidx330, align 4, !tbaa !1
+  %add331 = add nsw i32 %15, %14
+  %mul = mul nsw i32 %add331, %2
+  %shr332 = ashr i32 %mul, 16
+  %cmp333 = icmp sgt i32 %min_mcost.addr.0701, %shr332
+  br i1 %cmp333, label %if.end336, label %for.inc
+
+if.end336:                                        ; preds = %for.body
+  ; CHECK:      jalr  $25
+  ; CHECK-NOT:  move  $ra, {{.*}}
+  ; CHECK:      j     $BB{{.*}}
+  %add337 = add nsw i32 %add320, %shl
+  %add338 = add nsw i32 %add324, 0
+  %call340 = tail call i32 undef(i16* %orig_pic, i32 signext undef, i32 signext
+                                 undef, i32 signext 0, i32 signext %add49,
+                                 i32 signext undef, i32 signext %add337,
+                                 i32 signext %add338) #1
+  %cmp342 = icmp slt i32 0, %min_mcost.addr.0701
+  %pos.0.best_pos.0 = select i1 %cmp342, i32 %pos.0700, i32 %best_pos.0699
+  br label %for.inc
+
+for.inc:                                          ; preds = %if.end336, %for.body
+  %best_pos.1 = phi i32 [ %best_pos.0699, %for.body ], [ %pos.0.best_pos.0, %if.end336 ]
+  %.pre = load i16, i16* %mv_x, align 2, !tbaa !5
+  br label %for.body
+
+if.end358:                                        ; preds = %if.end290
+  %.min_mcost.addr.0 = select i1 false, i32 2147483647, i32 %min_mcost
+  br i1 undef, label %for.body415.lr.ph, label %if.end461
+
+for.body415.lr.ph:                                ; preds = %if.end358
+  %16 = load i16, i16* %mv_y, align 2, !tbaa !5
+  %conv420 = sext i16 %16 to i32
+  %add423 = add nsw i32 0, %conv420
+  %cmp433 = icmp sgt i32 %.min_mcost.addr.0, 0
+  br i1 %cmp433, label %if.end436, label %if.end461
+
+if.end436:                                        ; preds = %for.body415.lr.ph
+  %add438 = add nsw i32 %add423, 0
+  %call440 = tail call i32 @foobar(i16* %orig_pic, i32 signext undef, i32 signext undef,
+                                 i32 signext 0, i32 signext %add49, i32 signext undef,
+                                 i32 signext undef, i32 signext %add438) #1
+  br label %if.end461
+
+if.end461:                                        ; preds = %if.end436, %for.body415.lr.ph, %if.end358
+  ret void
+}
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="mips32r2" "target-features"="+mips32r2,+nooddspreg,+fpxx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 236218) (llvm/trunk 236237)"}
+!1 = !{!2, !2, i64 0}
+!2 = !{!"int", !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C/C++ TBAA"}
+!5 = !{!6, !6, i64 0}
+!6 = !{!"short", !3, i64 0}
+!7 = !{!8, !9, i64 0}
+!8 = !{!"", !9, i64 0, !3, i64 4}
+!9 = !{!"any pointer", !3, i64 0}
+!10 = !{!11, !9, i64 6440}
+!11 = !{!"storable_picture", !3, i64 0, !2, i64 4, !2, i64 8, !2, i64 12, !2, i64 16, !2, i64 20, !3, i64 24, !3, i64 1608, !3, i64 3192, !3, i64 4776, !2, i64 6360, !2, i64 6364, !2, i64 6368, !2, i64 6372, !2, i64 6376, !2, i64 6380, !2, i64 6384, !2, i64 6388, !2, i64 6392, !2, i64 6396, !2, i64 6400, !2, i64 6404, !2, i64 6408, !2, i64 6412, !2, i64 6416, !2, i64 6420, !2, i64 6424, !2, i64 6428, !2, i64 6432, !9, i64 6436, !9, i64 6440, !9, i64 6444, !9, i64 6448, !9, i64 6452, !9, i64 6456, !9, i64 6460, !9, i64 6464, !9, i64 6468, !9, i64 6472, !9, i64 6476, !9, i64 6480, !9, i64 6484, !9, i64 6488, !9, i64 6492, !2, i64 6496, !2, i64 6500, !2, i64 6504, !2, i64 6508, !2, i64 6512, !2, i64 6516, !2, i64 6520}
+!12 = !{!11, !2, i64 6408}
+!13 = !{!11, !2, i64 6412}
+!14 = !{!9, !9, i64 0}
diff --git a/test/CodeGen/Mips/delay-slot-kill.ll b/test/CodeGen/Mips/delay-slot-kill.ll
new file mode 100644
index 000000000000..57b630303c26
--- /dev/null
+++ b/test/CodeGen/Mips/delay-slot-kill.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s
+
+; Currently, the following IR assembly generates a KILL instruction between
+; the bitwise-and instruction and the return instruction. We verify that the
+; delay slot filler ignores such KILL instructions by filling the slot of the
+; return instruction properly.
+define signext i32 @f1(i32 signext %a, i32 signext %b) {
+entry:
+  ; CHECK:          jr      $ra
+  ; CHECK-NEXT:     and     $2, $4, $5
+
+  %r = and i32 %a, %b
+  ret i32 %r
+}
diff --git a/test/CodeGen/Mips/disable-tail-merge.ll b/test/CodeGen/Mips/disable-tail-merge.ll
index b4c093aa8528..9396db7be7f6 100644
--- a/test/CodeGen/Mips/disable-tail-merge.ll
+++ b/test/CodeGen/Mips/disable-tail-merge.ll
@@ -9,20 +9,20 @@
 define i32 @test1(i32 %a) {
 entry:
   %tobool = icmp eq i32 %a, 0
-  %0 = load i32* @g0, align 4
+  %0 = load i32, i32* @g0, align 4
   br i1 %tobool, label %if.else, label %if.then
 
 if.then:
   %add = add nsw i32 %0, 1
   store i32 %add, i32* @g0, align 4
-  %1 = load i32* @g1, align 4
+  %1 = load i32, i32* @g1, align 4
   %add1 = add nsw i32 %1, 23
   br label %if.end
 
 if.else:
   %add2 = add nsw i32 %0, 11
   store i32 %add2, i32* @g0, align 4
-  %2 = load i32* @g1, align 4
+  %2 = load i32, i32* @g1, align 4
   %add3 = add nsw i32 %2, 23
   br label %if.end
 
diff --git a/test/CodeGen/Mips/div.ll b/test/CodeGen/Mips/div.ll
index 00e2c1927459..731841c554fa 100644
--- a/test/CodeGen/Mips/div.ll
+++ b/test/CodeGen/Mips/div.ll
@@ -6,8 +6,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @iiii, align 4
-  %1 = load i32* @jjjj, align 4
+  %0 = load i32, i32* @iiii, align 4
+  %1 = load i32, i32* @jjjj, align 4
   %div = sdiv i32 %0, %1
 ; 16:	div	$zero, ${{[0-9]+}}, ${{[0-9]+}}
 ; 16: 	mflo	${{[0-9]+}}
diff --git a/test/CodeGen/Mips/div_rem.ll b/test/CodeGen/Mips/div_rem.ll
index 950192eee169..e64529cee841 100644
--- a/test/CodeGen/Mips/div_rem.ll
+++ b/test/CodeGen/Mips/div_rem.ll
@@ -7,8 +7,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @iiii, align 4
-  %1 = load i32* @jjjj, align 4
+  %0 = load i32, i32* @iiii, align 4
+  %1 = load i32, i32* @jjjj, align 4
   %div = sdiv i32 %0, %1
   store i32 %div, i32* @kkkk, align 4
   %rem = srem i32 %0, %1
diff --git a/test/CodeGen/Mips/divrem.ll b/test/CodeGen/Mips/divrem.ll
index a9cfe0fa1523..918db053f5b6 100644
--- a/test/CodeGen/Mips/divrem.ll
+++ b/test/CodeGen/Mips/divrem.ll
@@ -220,8 +220,8 @@ entry:
 ; FIXME: It's not clear what this is supposed to test.
 define i32 @killFlags() {
 entry:
-  %0 = load i32* @g0, align 4
-  %1 = load i32* @g1, align 4
+  %0 = load i32, i32* @g0, align 4
+  %1 = load i32, i32* @g1, align 4
   %div = sdiv i32 %0, %1
   ret i32 %div
 }
diff --git a/test/CodeGen/Mips/divu.ll b/test/CodeGen/Mips/divu.ll
index b96a439390ca..5bc765a71eb9 100644
--- a/test/CodeGen/Mips/divu.ll
+++ b/test/CodeGen/Mips/divu.ll
@@ -6,8 +6,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @iiii, align 4
-  %1 = load i32* @jjjj, align 4
+  %0 = load i32, i32* @iiii, align 4
+  %1 = load i32, i32* @jjjj, align 4
   %div = udiv i32 %0, %1
 ; 16:	divu	$zero, ${{[0-9]+}}, ${{[0-9]+}}
 ; 16: 	mflo	${{[0-9]+}}
diff --git a/test/CodeGen/Mips/divu_remu.ll b/test/CodeGen/Mips/divu_remu.ll
index a6c1563ac195..a079440b913f 100644
--- a/test/CodeGen/Mips/divu_remu.ll
+++ b/test/CodeGen/Mips/divu_remu.ll
@@ -8,8 +8,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @iiii, align 4
-  %1 = load i32* @jjjj, align 4
+  %0 = load i32, i32* @iiii, align 4
+  %1 = load i32, i32* @jjjj, align 4
   %div = udiv i32 %0, %1
   store i32 %div, i32* @kkkk, align 4
   %rem = urem i32 %0, %1
diff --git a/test/CodeGen/Mips/dsp-patterns.ll b/test/CodeGen/Mips/dsp-patterns.ll
index f5bb3abed90e..837c0d8bfc52 100644
--- a/test/CodeGen/Mips/dsp-patterns.ll
+++ b/test/CodeGen/Mips/dsp-patterns.ll
@@ -6,8 +6,8 @@
 
 define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) {
 entry:
-  %add.ptr = getelementptr inbounds i8* %b, i32 %i
-  %0 = load i8* %add.ptr, align 1
+  %add.ptr = getelementptr inbounds i8, i8* %b, i32 %i
+  %0 = load i8, i8* %add.ptr, align 1
   ret i8 %0
 }
 
@@ -16,8 +16,8 @@ entry:
 
 define signext i16 @test_lhx(i16* nocapture %b, i32 %i) {
 entry:
-  %add.ptr = getelementptr inbounds i16* %b, i32 %i
-  %0 = load i16* %add.ptr, align 2
+  %add.ptr = getelementptr inbounds i16, i16* %b, i32 %i
+  %0 = load i16, i16* %add.ptr, align 2
   ret i16 %0
 }
 
@@ -26,8 +26,8 @@ entry:
 
 define i32 @test_lwx(i32* nocapture %b, i32 %i) {
 entry:
-  %add.ptr = getelementptr inbounds i32* %b, i32 %i
-  %0 = load i32* %add.ptr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %b, i32 %i
+  %0 = load i32, i32* %add.ptr, align 4
   ret i32 %0
 }
 
diff --git a/test/CodeGen/Mips/dsp-vec-load-store.ll b/test/CodeGen/Mips/dsp-vec-load-store.ll
index 7e4a8fedaa8c..f9251807d000 100644
--- a/test/CodeGen/Mips/dsp-vec-load-store.ll
+++ b/test/CodeGen/Mips/dsp-vec-load-store.ll
@@ -5,7 +5,7 @@
 
 define void @extend_load_trunc_store_v2i8() {
 entry:
-  %0 = load <2 x i8>* @g1, align 2
+  %0 = load <2 x i8>, <2 x i8>* @g1, align 2
   store <2 x i8> %0, <2 x i8>* @g0, align 2
   ret void
 }
diff --git a/test/CodeGen/Mips/eh-return32.ll b/test/CodeGen/Mips/eh-return32.ll
index 748050c4d34b..542c5bf4462e 100644
--- a/test/CodeGen/Mips/eh-return32.ll
+++ b/test/CodeGen/Mips/eh-return32.ll
@@ -7,7 +7,7 @@ declare void @foo(...)
 
 define i8* @f1(i32 %offset, i8* %handler) {
 entry:
-  call void (...)* @foo()
+  call void (...) @foo()
   call void @llvm.eh.return.i32(i32 %offset, i8* %handler)
   unreachable
 
diff --git a/test/CodeGen/Mips/eh-return64.ll b/test/CodeGen/Mips/eh-return64.ll
index 74a43231598c..2f8203d77c84 100644
--- a/test/CodeGen/Mips/eh-return64.ll
+++ b/test/CodeGen/Mips/eh-return64.ll
@@ -8,7 +8,7 @@ declare void @foo(...)
 
 define void @f1(i64 %offset, i8* %handler) {
 entry:
-  call void (...)* @foo()
+  call void (...) @foo()
   call void @llvm.eh.return.i64(i64 %offset, i8* %handler)
   unreachable
 
diff --git a/test/CodeGen/Mips/eh.ll b/test/CodeGen/Mips/eh.ll
index fc9e2ef21a8b..fcbd99ef737b 100644
--- a/test/CodeGen/Mips/eh.ll
+++ b/test/CodeGen/Mips/eh.ll
@@ -27,6 +27,7 @@ lpad:                                             ; preds = %entry
 ; CHECK-EL:  bne $5
 
   %exn.val = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
+           cleanup
            catch i8* bitcast (i8** @_ZTId to i8*)
   %exn = extractvalue { i8*, i32 } %exn.val, 0
   %sel = extractvalue { i8*, i32 } %exn.val, 1
@@ -37,7 +38,7 @@ lpad:                                             ; preds = %entry
 catch:                                            ; preds = %lpad
   %3 = tail call i8* @__cxa_begin_catch(i8* %exn) nounwind
   %4 = bitcast i8* %3 to double*
-  %exn.scalar = load double* %4, align 8
+  %exn.scalar = load double, double* %4, align 8
   %add = fadd double %exn.scalar, %i2
   store double %add, double* @g1, align 8
   tail call void @__cxa_end_catch() nounwind
diff --git a/test/CodeGen/Mips/ehframe-indirect.ll b/test/CodeGen/Mips/ehframe-indirect.ll
index b4efb40b6422..f124881a472f 100644
--- a/test/CodeGen/Mips/ehframe-indirect.ll
+++ b/test/CodeGen/Mips/ehframe-indirect.ll
@@ -1,16 +1,18 @@
-; RUN: llc -mtriple=mipsel-linux-gnu < %s | FileCheck  -check-prefix=CHECK32 %s
-; RUN: llc -mtriple=mipsel-linux-android < %s | FileCheck -check-prefix=CHECK32 %s
-; RUN: llc -mtriple=mips64el-linux-gnu < %s | FileCheck  -check-prefix=CHECK64 %s
-; RUN: llc -mtriple=mips64el-linux-android < %s | FileCheck -check-prefix=CHECK64 %s
+; RUN: llc -mtriple=mipsel-linux-gnu < %s | FileCheck -check-prefix=ALL -check-prefix=O32 %s
+; RUN: llc -mtriple=mipsel-linux-android < %s | FileCheck -check-prefix=ALL -check-prefix=O32 %s
+; RUN: llc -mtriple=mips64el-linux-gnu -target-abi=n32 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 %s
+; RUN: llc -mtriple=mips64el-linux-android -target-abi=n32 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 %s
+; RUN: llc -mtriple=mips64el-linux-gnu < %s | FileCheck -check-prefix=ALL -check-prefix=N64 %s
+; RUN: llc -mtriple=mips64el-linux-android < %s | FileCheck -check-prefix=ALL -check-prefix=N64 %s
 
 define i32 @main() {
-; CHECK: .cfi_startproc
-; CHECK: .cfi_personality 128, DW.ref.__gxx_personality_v0
+; ALL: .cfi_startproc
+; ALL: .cfi_personality 128, DW.ref.__gxx_personality_v0
 
 entry:
   invoke void @foo() to label %cont unwind label %lpad
-; CHECK: foo
-; CHECK: jalr
+; ALL: foo
+; ALL: jalr
 
 lpad:
   %0 = landingpad { i8*, i32 } personality i8*
@@ -20,20 +22,23 @@ lpad:
 cont:
   ret i32 0
 }
-; CHECK: .cfi_endproc
+; ALL: .cfi_endproc
 
 declare i32 @__gxx_personality_v0(...)
 
 declare void @foo()
 
-; CHECK: .hidden DW.ref.__gxx_personality_v0
-; CHECK: .weak DW.ref.__gxx_personality_v0
-; CHECK: .section .data.DW.ref.__gxx_personality_v0,"aGw",@progbits,DW.ref.__gxx_personality_v0,comdat
-; CHECK32: .align 2
-; CHECK64: .align 3
-; CHECK: .type DW.ref.__gxx_personality_v0,@object
-; CHECK32: .size DW.ref.__gxx_personality_v0, 4
-; CHECK64: .size DW.ref.__gxx_personality_v0, 8
-; CHECK: DW.ref.__gxx_personality_v0:
-; CHECK32: .4byte __gxx_personality_v0
-; CHECK64: .8byte __gxx_personality_v0
+; ALL: .hidden DW.ref.__gxx_personality_v0
+; ALL: .weak DW.ref.__gxx_personality_v0
+; ALL: .section .data.DW.ref.__gxx_personality_v0,"aGw",@progbits,DW.ref.__gxx_personality_v0,comdat
+; O32: .align 2
+; N32: .align 2
+; N64: .align 3
+; ALL: .type DW.ref.__gxx_personality_v0,@object
+; O32: .size DW.ref.__gxx_personality_v0, 4
+; N32: .size DW.ref.__gxx_personality_v0, 4
+; N64: .size DW.ref.__gxx_personality_v0, 8
+; ALL: DW.ref.__gxx_personality_v0:
+; O32: .4byte __gxx_personality_v0
+; N32: .4byte __gxx_personality_v0
+; N64: .8byte __gxx_personality_v0
diff --git a/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll b/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll
new file mode 100644
index 000000000000..3dc1cde77095
--- /dev/null
+++ b/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll
@@ -0,0 +1,32 @@
+; Check that register scavenging spill slot is close to $fp.
+; RUN: llc -march=mipsel -O0 < %s | FileCheck %s
+
+; CHECK: sw ${{.*}}, 4($fp)
+; CHECK: lw ${{.*}}, 4($fp)
+
+define i32 @main(i32 signext %argc, i8** %argv) "no-frame-pointer-elim"="true" {
+entry:
+  %retval = alloca i32, align 4
+  %argc.addr = alloca i32, align 4
+  %argv.addr = alloca i8**, align 4
+  %v0 = alloca <16 x i8>, align 16
+  %.compoundliteral = alloca <16 x i8>, align 16
+  %v1 = alloca <16 x i8>, align 16
+  %.compoundliteral1 = alloca <16 x i8>, align 16
+  %unused_variable = alloca [16384 x i32], align 4
+  %result = alloca <16 x i8>, align 16
+  store i32 0, i32* %retval
+  store i32 %argc, i32* %argc.addr, align 4
+  store i8** %argv, i8*** %argv.addr, align 4
+  store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %.compoundliteral
+  %0 = load <16 x i8>, <16 x i8>* %.compoundliteral
+  store <16 x i8> %0, <16 x i8>* %v0, align 16
+  store <16 x i8> zeroinitializer, <16 x i8>* %.compoundliteral1
+  %1 = load <16 x i8>, <16 x i8>* %.compoundliteral1
+  store <16 x i8> %1, <16 x i8>* %v1, align 16
+  %2 = load <16 x i8>, <16 x i8>* %v0, align 16
+  %3 = load <16 x i8>, <16 x i8>* %v1, align 16
+  %mul = mul <16 x i8> %2, %3
+  store <16 x i8> %mul, <16 x i8>* %result, align 16
+  ret i32 0
+}
diff --git a/test/CodeGen/Mips/emit-big-cst.ll b/test/CodeGen/Mips/emit-big-cst.ll
index a168743859a3..9bc96c89307d 100644
--- a/test/CodeGen/Mips/emit-big-cst.ll
+++ b/test/CodeGen/Mips/emit-big-cst.ll
@@ -10,7 +10,7 @@
 
 define void @accessBig(i64* %storage) {
   %addr = bitcast i64* %storage to i82*
-  %bigLoadedCst = load volatile i82* @bigCst
+  %bigLoadedCst = load volatile i82, i82* @bigCst
   %tmp = add i82 %bigLoadedCst, 1
   store i82 %tmp, i82* %addr
   ret void
diff --git a/test/CodeGen/Mips/ex2.ll b/test/CodeGen/Mips/ex2.ll
index 6d024c209c26..7547fdf81e35 100644
--- a/test/CodeGen/Mips/ex2.ll
+++ b/test/CodeGen/Mips/ex2.ll
@@ -17,12 +17,12 @@ entry:
   store i32 0, i32* %retval
   %exception = call i8* @__cxa_allocate_exception(i32 4) nounwind
   %0 = bitcast i8* %exception to i8**
-  store i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), i8** %0
+  store i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), i8** %0
   call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIPKc to i8*), i8* null) noreturn
   unreachable
 
 return:                                           ; No predecessors!
-  %1 = load i32* %retval
+  %1 = load i32, i32* %retval
   ret i32 %1
 }
 
diff --git a/test/CodeGen/Mips/extins.ll b/test/CodeGen/Mips/extins.ll
index efaeeea96a5e..6604f89b1843 100644
--- a/test/CodeGen/Mips/extins.ll
+++ b/test/CodeGen/Mips/extins.ll
@@ -16,7 +16,7 @@ entry:
 ; 16-NOT: ins ${{[0-9]+}}
   %and = shl i32 %s, 5
   %shl = and i32 %and, 16352
-  %tmp3 = load i32* %d, align 4
+  %tmp3 = load i32, i32* %d, align 4
   %and5 = and i32 %tmp3, -16353
   %or = or i32 %and5, %shl
   store i32 %or, i32* %d, align 4
diff --git a/test/CodeGen/Mips/f16abs.ll b/test/CodeGen/Mips/f16abs.ll
index 0fba9c4fd08a..838983274e9b 100644
--- a/test/CodeGen/Mips/f16abs.ll
+++ b/test/CodeGen/Mips/f16abs.ll
@@ -11,12 +11,12 @@
 ; Function Attrs: nounwind optsize
 define i32 @main() #0 {
 entry:
-  %0 = load double* @y, align 8
+  %0 = load double, double* @y, align 8
   %call = tail call double @fabs(double %0) #2
   store double %call, double* @x, align 8
 ; static-NOT: 	.ent	__call_stub_fp_fabs
 ; static-NOT: 	jal fabs
-  %1 = load float* @y1, align 4
+  %1 = load float, float* @y1, align 4
   %call2 = tail call float @fabsf(float %1) #2
   store float %call2, float* @x1, align 4
 ; static-NOT: 	.ent	__call_stub_fp_fabsf
diff --git a/test/CodeGen/Mips/fastcc.ll b/test/CodeGen/Mips/fastcc.ll
index 6b022c5e36d9..299e0d696cbb 100644
--- a/test/CodeGen/Mips/fastcc.ll
+++ b/test/CodeGen/Mips/fastcc.ll
@@ -108,23 +108,23 @@ entry:
 ; CHECK-NACL-NOT: lw  $15
 ; CHECK-NACL-NOT: lw  $24
 
-  %0 = load i32* @gi0, align 4
-  %1 = load i32* @gi1, align 4
-  %2 = load i32* @gi2, align 4
-  %3 = load i32* @gi3, align 4
-  %4 = load i32* @gi4, align 4
-  %5 = load i32* @gi5, align 4
-  %6 = load i32* @gi6, align 4
-  %7 = load i32* @gi7, align 4
-  %8 = load i32* @gi8, align 4
-  %9 = load i32* @gi9, align 4
-  %10 = load i32* @gi10, align 4
-  %11 = load i32* @gi11, align 4
-  %12 = load i32* @gi12, align 4
-  %13 = load i32* @gi13, align 4
-  %14 = load i32* @gi14, align 4
-  %15 = load i32* @gi15, align 4
-  %16 = load i32* @gi16, align 4
+  %0 = load i32, i32* @gi0, align 4
+  %1 = load i32, i32* @gi1, align 4
+  %2 = load i32, i32* @gi2, align 4
+  %3 = load i32, i32* @gi3, align 4
+  %4 = load i32, i32* @gi4, align 4
+  %5 = load i32, i32* @gi5, align 4
+  %6 = load i32, i32* @gi6, align 4
+  %7 = load i32, i32* @gi7, align 4
+  %8 = load i32, i32* @gi8, align 4
+  %9 = load i32, i32* @gi9, align 4
+  %10 = load i32, i32* @gi10, align 4
+  %11 = load i32, i32* @gi11, align 4
+  %12 = load i32, i32* @gi12, align 4
+  %13 = load i32, i32* @gi13, align 4
+  %14 = load i32, i32* @gi14, align 4
+  %15 = load i32, i32* @gi15, align 4
+  %16 = load i32, i32* @gi16, align 4
   tail call fastcc void @callee0(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, i32 %14, i32 %15, i32 %16)
   ret void
 }
@@ -196,27 +196,27 @@ entry:
 ; CHECK: lwc1  $f1
 ; CHECK: lwc1  $f0
 
-  %0 = load float* @gfa0, align 4
-  %1 = load float* @gfa1, align 4
-  %2 = load float* @gfa2, align 4
-  %3 = load float* @gfa3, align 4
-  %4 = load float* @gfa4, align 4
-  %5 = load float* @gfa5, align 4
-  %6 = load float* @gfa6, align 4
-  %7 = load float* @gfa7, align 4
-  %8 = load float* @gfa8, align 4
-  %9 = load float* @gfa9, align 4
-  %10 = load float* @gfa10, align 4
-  %11 = load float* @gfa11, align 4
-  %12 = load float* @gfa12, align 4
-  %13 = load float* @gfa13, align 4
-  %14 = load float* @gfa14, align 4
-  %15 = load float* @gfa15, align 4
-  %16 = load float* @gfa16, align 4
-  %17 = load float* @gfa17, align 4
-  %18 = load float* @gfa18, align 4
-  %19 = load float* @gfa19, align 4
-  %20 = load float* @gfa20, align 4
+  %0 = load float, float* @gfa0, align 4
+  %1 = load float, float* @gfa1, align 4
+  %2 = load float, float* @gfa2, align 4
+  %3 = load float, float* @gfa3, align 4
+  %4 = load float, float* @gfa4, align 4
+  %5 = load float, float* @gfa5, align 4
+  %6 = load float, float* @gfa6, align 4
+  %7 = load float, float* @gfa7, align 4
+  %8 = load float, float* @gfa8, align 4
+  %9 = load float, float* @gfa9, align 4
+  %10 = load float, float* @gfa10, align 4
+  %11 = load float, float* @gfa11, align 4
+  %12 = load float, float* @gfa12, align 4
+  %13 = load float, float* @gfa13, align 4
+  %14 = load float, float* @gfa14, align 4
+  %15 = load float, float* @gfa15, align 4
+  %16 = load float, float* @gfa16, align 4
+  %17 = load float, float* @gfa17, align 4
+  %18 = load float, float* @gfa18, align 4
+  %19 = load float, float* @gfa19, align 4
+  %20 = load float, float* @gfa20, align 4
   tail call fastcc void @callee1(float %0, float %1, float %2, float %3, float %4, float %5, float %6, float %7, float %8, float %9, float %10, float %11, float %12, float %13, float %14, float %15, float %16, float %17, float %18, float %19, float %20)
   ret void
 }
@@ -292,17 +292,17 @@ entry:
 ; NOODDSPREG-DAG:    lwc1    $[[F0:f[0-9]*[02468]]], 40($[[R0]])
 ; NOODDSPREG-DAG:    swc1    $[[F0]], 0($sp)
 
-  %0 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 0), align 4
-  %1 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 1), align 4
-  %2 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 2), align 4
-  %3 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 3), align 4
-  %4 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 4), align 4
-  %5 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 5), align 4
-  %6 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 6), align 4
-  %7 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 7), align 4
-  %8 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 8), align 4
-  %9 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 9), align 4
-  %10 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 10), align 4
+  %0 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 0), align 4
+  %1 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 1), align 4
+  %2 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 2), align 4
+  %3 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 3), align 4
+  %4 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 4), align 4
+  %5 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 5), align 4
+  %6 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 6), align 4
+  %7 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 7), align 4
+  %8 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 8), align 4
+  %9 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 9), align 4
+  %10 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 10), align 4
   tail call fastcc void @callee2(float %0, float %1, float %2, float %3,
                                  float %4, float %5, float %6, float %7,
                                  float %8, float %9, float %10)
@@ -336,17 +336,17 @@ entry:
 ; NOODDSPREG-DAG:    lwc1    $[[F0:f[0-9]*[02468]]], [[OFFSET]]($sp)
 ; NOODDSPREG-DAG:    swc1    $[[F0]], 40($[[R0]])
 
-  store float %a0, float* getelementptr ([11 x float]* @fa, i32 0, i32 0), align 4
-  store float %a1, float* getelementptr ([11 x float]* @fa, i32 0, i32 1), align 4
-  store float %a2, float* getelementptr ([11 x float]* @fa, i32 0, i32 2), align 4
-  store float %a3, float* getelementptr ([11 x float]* @fa, i32 0, i32 3), align 4
-  store float %a4, float* getelementptr ([11 x float]* @fa, i32 0, i32 4), align 4
-  store float %a5, float* getelementptr ([11 x float]* @fa, i32 0, i32 5), align 4
-  store float %a6, float* getelementptr ([11 x float]* @fa, i32 0, i32 6), align 4
-  store float %a7, float* getelementptr ([11 x float]* @fa, i32 0, i32 7), align 4
-  store float %a8, float* getelementptr ([11 x float]* @fa, i32 0, i32 8), align 4
-  store float %a9, float* getelementptr ([11 x float]* @fa, i32 0, i32 9), align 4
-  store float %a10, float* getelementptr ([11 x float]* @fa, i32 0, i32 10), align 4
+  store float %a0, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 0), align 4
+  store float %a1, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 1), align 4
+  store float %a2, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 2), align 4
+  store float %a3, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 3), align 4
+  store float %a4, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 4), align 4
+  store float %a5, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 5), align 4
+  store float %a6, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 6), align 4
+  store float %a7, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 7), align 4
+  store float %a8, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 8), align 4
+  store float %a9, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 9), align 4
+  store float %a10, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 10), align 4
   ret void
 }
 
@@ -373,17 +373,17 @@ entry:
 ; FP64-NOODDSPREG-DAG:    ldc1    $[[F0:f[0-9]*[02468]]], 80($[[R0]])
 ; FP64-NOODDSPREG-DAG:    sdc1    $[[F0]], 0($sp)
 
-  %0 = load double* getelementptr ([11 x double]* @da, i32 0, i32 0), align 8
-  %1 = load double* getelementptr ([11 x double]* @da, i32 0, i32 1), align 8
-  %2 = load double* getelementptr ([11 x double]* @da, i32 0, i32 2), align 8
-  %3 = load double* getelementptr ([11 x double]* @da, i32 0, i32 3), align 8
-  %4 = load double* getelementptr ([11 x double]* @da, i32 0, i32 4), align 8
-  %5 = load double* getelementptr ([11 x double]* @da, i32 0, i32 5), align 8
-  %6 = load double* getelementptr ([11 x double]* @da, i32 0, i32 6), align 8
-  %7 = load double* getelementptr ([11 x double]* @da, i32 0, i32 7), align 8
-  %8 = load double* getelementptr ([11 x double]* @da, i32 0, i32 8), align 8
-  %9 = load double* getelementptr ([11 x double]* @da, i32 0, i32 9), align 8
-  %10 = load double* getelementptr ([11 x double]* @da, i32 0, i32 10), align 8
+  %0 = load double, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 0), align 8
+  %1 = load double, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 1), align 8
+  %2 = load double, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 2), align 8
+  %3 = load double, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 3), align 8
+  %4 = load double, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 4), align 8
+  %5 = load double, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 5), align 8
+  %6 = load double, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 6), align 8
+  %7 = load double, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 7), align 8
+  %8 = load double, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 8), align 8
+  %9 = load double, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 9), align 8
+  %10 = load double, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 10), align 8
   tail call fastcc void @callee3(double %0, double %1, double %2, double %3,
                                  double %4, double %5, double %6, double %7,
                                  double %8, double %9, double %10)
@@ -417,16 +417,16 @@ entry:
 ; FP64-NOODDSPREG-DAG:    ldc1    $[[F0:f[0-9]*[02468]]], [[OFFSET]]($sp)
 ; FP64-NOODDSPREG-DAG:    sdc1    $[[F0]], 80($[[R0]])
 
-  store double %a0, double* getelementptr ([11 x double]* @da, i32 0, i32 0), align 8
-  store double %a1, double* getelementptr ([11 x double]* @da, i32 0, i32 1), align 8
-  store double %a2, double* getelementptr ([11 x double]* @da, i32 0, i32 2), align 8
-  store double %a3, double* getelementptr ([11 x double]* @da, i32 0, i32 3), align 8
-  store double %a4, double* getelementptr ([11 x double]* @da, i32 0, i32 4), align 8
-  store double %a5, double* getelementptr ([11 x double]* @da, i32 0, i32 5), align 8
-  store double %a6, double* getelementptr ([11 x double]* @da, i32 0, i32 6), align 8
-  store double %a7, double* getelementptr ([11 x double]* @da, i32 0, i32 7), align 8
-  store double %a8, double* getelementptr ([11 x double]* @da, i32 0, i32 8), align 8
-  store double %a9, double* getelementptr ([11 x double]* @da, i32 0, i32 9), align 8
-  store double %a10, double* getelementptr ([11 x double]* @da, i32 0, i32 10), align 8
+  store double %a0, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 0), align 8
+  store double %a1, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 1), align 8
+  store double %a2, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 2), align 8
+  store double %a3, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 3), align 8
+  store double %a4, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 4), align 8
+  store double %a5, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 5), align 8
+  store double %a6, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 6), align 8
+  store double %a7, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 7), align 8
+  store double %a8, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 8), align 8
+  store double %a9, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 9), align 8
+  store double %a10, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 10), align 8
   ret void
 }
diff --git a/test/CodeGen/Mips/fcopysign-f32-f64.ll b/test/CodeGen/Mips/fcopysign-f32-f64.ll
index 148a780fb930..860bc79956fc 100644
--- a/test/CodeGen/Mips/fcopysign-f32-f64.ll
+++ b/test/CodeGen/Mips/fcopysign-f32-f64.ll
@@ -1,6 +1,6 @@
-; RUN: llc  < %s -march=mips64el -mcpu=mips4 -mattr=n64 | FileCheck %s -check-prefix=64
-; RUN: llc  < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64
-; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2
+; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s -check-prefix=64
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefix=64
+; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefix=64R2
 
 declare double @copysign(double, double) nounwind readnone
 
diff --git a/test/CodeGen/Mips/fcopysign.ll b/test/CodeGen/Mips/fcopysign.ll
index 3a9d9c73b279..6928f2fe507f 100644
--- a/test/CodeGen/Mips/fcopysign.ll
+++ b/test/CodeGen/Mips/fcopysign.ll
@@ -1,8 +1,8 @@
 ; RUN: llc  < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=32
 ; RUN: llc  < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2
-; RUN: llc  < %s -march=mips64el -mcpu=mips4 -mattr=n64 | FileCheck %s -check-prefix=64
-; RUN: llc  < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64
-; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2
+; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s -check-prefix=64
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefix=64
+; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefix=64R2
 
 define double @func0(double %d0, double %d1) nounwind readnone {
 entry:
diff --git a/test/CodeGen/Mips/fixdfsf.ll b/test/CodeGen/Mips/fixdfsf.ll
index 4271ac222edb..869579922d51 100644
--- a/test/CodeGen/Mips/fixdfsf.ll
+++ b/test/CodeGen/Mips/fixdfsf.ll
@@ -7,7 +7,7 @@
 ; Function Attrs: nounwind optsize
 define void @foo()  {
 entry:
-  %0 = load double* @x, align 8
+  %0 = load double, double* @x, align 8
   %conv = fptoui double %0 to i32
   store i32 %conv, i32* @y, align 4
 ; pic1:	lw	${{[0-9]+}}, %call16(__fixunsdfsi)(${{[0-9]+}})
diff --git a/test/CodeGen/Mips/fmadd1.ll b/test/CodeGen/Mips/fmadd1.ll
index f0667eec3b33..99d99fada1cf 100644
--- a/test/CodeGen/Mips/fmadd1.ll
+++ b/test/CodeGen/Mips/fmadd1.ll
@@ -8,15 +8,15 @@
 ; RUN: llc < %s -march=mipsel   -mcpu=mips32              -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32   -check-prefix=32-NONAN
 ; RUN: llc < %s -march=mipsel   -mcpu=mips32r2            -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -check-prefix=32R2-NONAN
 ; RUN: llc < %s -march=mipsel   -mcpu=mips32r6            -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -check-prefix=32R6-NONAN
-; RUN: llc < %s -march=mips64el -mcpu=mips64   -mattr=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64   -check-prefix=64-NONAN
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NONAN
-; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -mattr=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NONAN
+; RUN: llc < %s -march=mips64el -mcpu=mips64   -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64   -check-prefix=64-NONAN
+; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NONAN
+; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NONAN
 ; RUN: llc < %s -march=mipsel   -mcpu=mips32              | FileCheck %s -check-prefix=ALL -check-prefix=32 -check-prefix=32-NAN
 ; RUN: llc < %s -march=mipsel   -mcpu=mips32r2            | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -check-prefix=32R2-NAN
 ; RUN: llc < %s -march=mipsel   -mcpu=mips32r6            | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -check-prefix=32R6-NAN
-; RUN: llc < %s -march=mips64el -mcpu=mips64   -mattr=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64   -check-prefix=64-NAN
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NAN
-; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -mattr=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NAN
+; RUN: llc < %s -march=mips64el -mcpu=mips64   -target-abi=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64   -check-prefix=64-NAN
+; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NAN
+; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NAN
 
 define float @FOO0float(float %a, float %b, float %c) nounwind readnone {
 entry:
diff --git a/test/CodeGen/Mips/fp-indexed-ls.ll b/test/CodeGen/Mips/fp-indexed-ls.ll
index 787e131f6ec5..219ca99d3f94 100644
--- a/test/CodeGen/Mips/fp-indexed-ls.ll
+++ b/test/CodeGen/Mips/fp-indexed-ls.ll
@@ -1,10 +1,10 @@
 ; RUN: llc -march=mipsel   -mcpu=mips32   < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R1
 ; RUN: llc -march=mipsel   -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R2
 ; RUN: llc -march=mipsel   -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R6
-; RUN: llc -march=mips64el -mcpu=mips4    -mattr=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4
-; RUN: llc -march=mips64el -mcpu=mips64   -mattr=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4
-; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64R6
+; RUN: llc -march=mips64el -mcpu=mips4    -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4
+; RUN: llc -march=mips64el -mcpu=mips64   -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4
+; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64R6
 
 ; Check that [ls][dwu]xc1 are not emitted for nacl.
 ; RUN: llc -mtriple=mipsel-none-nacl-gnu -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=CHECK-NACL
@@ -45,8 +45,8 @@ entry:
 
 ; CHECK-NACL-NOT: lwxc1
 
-  %arrayidx = getelementptr inbounds float* %b, i32 %o
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %b, i32 %o
+  %0 = load float, float* %arrayidx, align 4
   ret float %0
 }
 
@@ -76,8 +76,8 @@ entry:
 
 ; CHECK-NACL-NOT: ldxc1
 
-  %arrayidx = getelementptr inbounds double* %b, i32 %o
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %b, i32 %o
+  %0 = load double, double* %arrayidx, align 8
   ret double %0
 }
 
@@ -100,8 +100,8 @@ entry:
 ; luxc1 was removed in MIPS64r6
 ; MIPS64R6-NOT:  luxc1
 
-  %arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
-  %0 = load float* %arrayidx1, align 1
+  %arrayidx1 = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
+  %0 = load float, float* %arrayidx1, align 1
   ret float %0
 }
 
@@ -129,8 +129,8 @@ entry:
 
 ; CHECK-NACL-NOT: swxc1
 
-  %0 = load float* @gf, align 4
-  %arrayidx = getelementptr inbounds float* %b, i32 %o
+  %0 = load float, float* @gf, align 4
+  %arrayidx = getelementptr inbounds float, float* %b, i32 %o
   store float %0, float* %arrayidx, align 4
   ret void
 }
@@ -159,8 +159,8 @@ entry:
 
 ; CHECK-NACL-NOT: sdxc1
 
-  %0 = load double* @gd, align 8
-  %arrayidx = getelementptr inbounds double* %b, i32 %o
+  %0 = load double, double* @gd, align 8
+  %arrayidx = getelementptr inbounds double, double* %b, i32 %o
   store double %0, double* %arrayidx, align 8
   ret void
 }
@@ -179,8 +179,8 @@ entry:
 
 ; MIPS64R6-NOT:  suxc1
 
-  %0 = load float* @gf, align 4
-  %arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
+  %0 = load float, float* @gf, align 4
+  %arrayidx1 = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
   store float %0, float* %arrayidx1, align 1
   ret void
 }
@@ -199,8 +199,8 @@ entry:
 
 ; MIPS64R6-NOT:  luxc1
 
-  %arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
-  %0 = load double* %arrayidx1, align 1
+  %arrayidx1 = getelementptr inbounds [4 x %struct.S2], [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
+  %0 = load double, double* %arrayidx1, align 1
   ret double %0
 }
 
@@ -218,8 +218,8 @@ entry:
 
 ; MIPS64R6-NOT:  suxc1
 
-  %0 = load double* @gd, align 8
-  %arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
+  %0 = load double, double* @gd, align 8
+  %arrayidx1 = getelementptr inbounds [4 x %struct.S2], [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
   store double %0, double* %arrayidx1, align 1
   ret void
 }
@@ -238,7 +238,7 @@ entry:
 
 ; MIPS64R6-NOT:  luxc1
 
-  %0 = load float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1
+  %0 = load float, float* getelementptr inbounds (%struct.S3, %struct.S3* @s3, i32 0, i32 1), align 1
   ret float %0
 }
 
@@ -256,7 +256,7 @@ entry:
 
 ; MIPS64R6-NOT:  suxc1
 
-  store float %f, float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1
+  store float %f, float* getelementptr inbounds (%struct.S3, %struct.S3* @s3, i32 0, i32 1), align 1
   ret void
 }
 
diff --git a/test/CodeGen/Mips/fp-spill-reload.ll b/test/CodeGen/Mips/fp-spill-reload.ll
index f9887a55827f..4a53ad8c8e13 100644
--- a/test/CodeGen/Mips/fp-spill-reload.ll
+++ b/test/CodeGen/Mips/fp-spill-reload.ll
@@ -5,27 +5,27 @@ define void @foo0(i32* nocapture %b) nounwind {
 entry:
 ; CHECK: sw  $fp
 ; CHECK: lw  $fp
-  %0 = load i32* %b, align 4
-  %arrayidx.1 = getelementptr inbounds i32* %b, i32 1
-  %1 = load i32* %arrayidx.1, align 4
+  %0 = load i32, i32* %b, align 4
+  %arrayidx.1 = getelementptr inbounds i32, i32* %b, i32 1
+  %1 = load i32, i32* %arrayidx.1, align 4
   %add.1 = add nsw i32 %1, 1
-  %arrayidx.2 = getelementptr inbounds i32* %b, i32 2
-  %2 = load i32* %arrayidx.2, align 4
+  %arrayidx.2 = getelementptr inbounds i32, i32* %b, i32 2
+  %2 = load i32, i32* %arrayidx.2, align 4
   %add.2 = add nsw i32 %2, 2
-  %arrayidx.3 = getelementptr inbounds i32* %b, i32 3
-  %3 = load i32* %arrayidx.3, align 4
+  %arrayidx.3 = getelementptr inbounds i32, i32* %b, i32 3
+  %3 = load i32, i32* %arrayidx.3, align 4
   %add.3 = add nsw i32 %3, 3
-  %arrayidx.4 = getelementptr inbounds i32* %b, i32 4
-  %4 = load i32* %arrayidx.4, align 4
+  %arrayidx.4 = getelementptr inbounds i32, i32* %b, i32 4
+  %4 = load i32, i32* %arrayidx.4, align 4
   %add.4 = add nsw i32 %4, 4
-  %arrayidx.5 = getelementptr inbounds i32* %b, i32 5
-  %5 = load i32* %arrayidx.5, align 4
+  %arrayidx.5 = getelementptr inbounds i32, i32* %b, i32 5
+  %5 = load i32, i32* %arrayidx.5, align 4
   %add.5 = add nsw i32 %5, 5
-  %arrayidx.6 = getelementptr inbounds i32* %b, i32 6
-  %6 = load i32* %arrayidx.6, align 4
+  %arrayidx.6 = getelementptr inbounds i32, i32* %b, i32 6
+  %6 = load i32, i32* %arrayidx.6, align 4
   %add.6 = add nsw i32 %6, 6
-  %arrayidx.7 = getelementptr inbounds i32* %b, i32 7
-  %7 = load i32* %arrayidx.7, align 4
+  %arrayidx.7 = getelementptr inbounds i32, i32* %b, i32 7
+  %7 = load i32, i32* %arrayidx.7, align 4
   %add.7 = add nsw i32 %7, 7
   call void @foo2(i32 %0, i32 %add.1, i32 %add.2, i32 %add.3, i32 %add.4, i32 %add.5, i32 %add.6, i32 %add.7) nounwind
   call void bitcast (void (...)* @foo1 to void ()*)() nounwind
diff --git a/test/CodeGen/Mips/fp16-promote.ll b/test/CodeGen/Mips/fp16-promote.ll
new file mode 100644
index 000000000000..2ac46e028072
--- /dev/null
+++ b/test/CodeGen/Mips/fp16-promote.ll
@@ -0,0 +1,98 @@
+; RUN: llc -asm-verbose=false -mtriple=mipsel-linux-gnueabi < %s | FileCheck %s -check-prefix=CHECK-LIBCALL
+
+; CHECK-LIBCALL-LABEL: test_fadd:
+; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
+; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
+; CHECK-LIBCALL-DAG: add.s
+; CHECK-LIBCALL-DAG: %call16(__gnu_f2h_ieee)
+define void @test_fadd(half* %p, half* %q) #0 {
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %r = fadd half %a, %b
+  store half %r, half* %p
+  ret void
+}
+
+; CHECK-LIBCALL-LABEL: test_fpext_float:
+; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
+define float @test_fpext_float(half* %p) {
+  %a = load half, half* %p, align 2
+  %r = fpext half %a to float
+  ret float %r
+}
+
+; CHECK-LIBCALL-LABEL: test_fpext_double:
+; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
+; CHECK-LIBCALL: cvt.d.s
+define double @test_fpext_double(half* %p) {
+  %a = load half, half* %p, align 2
+  %r = fpext half %a to double
+  ret double %r
+}
+
+; CHECK-LIBCALL-LABEL: test_fptrunc_float:
+; CHECK-LIBCALL: %call16(__gnu_f2h_ieee)
+define void @test_fptrunc_float(float %f, half* %p) #0 {
+  %a = fptrunc float %f to half
+  store half %a, half* %p
+  ret void
+}
+
+; CHECK-LIBCALL-LABEL: test_fptrunc_double:
+; CHECK-LIBCALL: %call16(__truncdfhf2)
+define void @test_fptrunc_double(double %d, half* %p) #0 {
+  %a = fptrunc double %d to half
+  store half %a, half* %p
+  ret void
+}
+
+; CHECK-LIBCALL-LABEL: test_vec_fpext_float:
+; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
+; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
+; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
+; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
+define <4 x float> @test_vec_fpext_float(<4 x half>* %p) #0 {
+  %a = load <4 x half>, <4 x half>* %p, align 8
+  %b = fpext <4 x half> %a to <4 x float>
+  ret <4 x float> %b
+}
+
+; This test is not robust against variations in instruction scheduling.
+; See the discussion in http://reviews.llvm.org/D8804
+; CHECK-LIBCALL-LABEL: test_vec_fpext_double:
+; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
+; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
+; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
+; CHECK-LIBCALL: cvt.d.s
+; CHECK-LIBCALL: cvt.d.s
+; CHECK-LIBCALL: cvt.d.s
+; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
+; CHECK-LIBCALL: cvt.d.s
+define <4 x double> @test_vec_fpext_double(<4 x half>* %p) #0 {
+  %a = load <4 x half>, <4 x half>* %p, align 8
+  %b = fpext <4 x half> %a to <4 x double>
+  ret <4 x double> %b
+}
+
+; CHECK-LIBCALL-LABEL: test_vec_fptrunc_float:
+; CHECK-LIBCALL: %call16(__gnu_f2h_ieee)
+; CHECK-LIBCALL: %call16(__gnu_f2h_ieee)
+; CHECK-LIBCALL: %call16(__gnu_f2h_ieee)
+; CHECK-LIBCALL: %call16(__gnu_f2h_ieee)
+define void @test_vec_fptrunc_float(<4 x float> %a, <4 x half>* %p) #0 {
+  %b = fptrunc <4 x float> %a to <4 x half>
+  store <4 x half> %b, <4 x half>* %p, align 8
+  ret void
+}
+
+; CHECK-LIBCALL-LABEL: test_vec_fptrunc_double:
+; CHECK-LIBCALL: %call16(__truncdfhf2)
+; CHECK-LIBCALL: %call16(__truncdfhf2)
+; CHECK-LIBCALL: %call16(__truncdfhf2)
+; CHECK-LIBCALL: %call16(__truncdfhf2)
+define void @test_vec_fptrunc_double(<4 x double> %a, <4 x half>* %p) #0 {
+  %b = fptrunc <4 x double> %a to <4 x half>
+  store <4 x half> %b, <4 x half>* %p, align 8
+  ret void
+}
+
diff --git a/test/CodeGen/Mips/fp16instrinsmc.ll b/test/CodeGen/Mips/fp16instrinsmc.ll
index 84d3814ee8b8..797be2668d40 100644
--- a/test/CodeGen/Mips/fp16instrinsmc.ll
+++ b/test/CodeGen/Mips/fp16instrinsmc.ll
@@ -23,8 +23,8 @@ define void @foo1() #0 {
 ; fmask: .set	reorder
 ; fmask: .end	foo1
 entry:
-  %0 = load float* @x, align 4
-  %1 = load float* @one, align 4
+  %0 = load float, float* @x, align 4
+  %1 = load float, float* @one, align 4
   %call = call float @copysignf(float %0, float %1) #2
   store float %call, float* @y, align 4
   ret void
@@ -39,8 +39,8 @@ define void @foo2() #0 {
 ; fmask:	save	{{.*}}
 ; fmask:	.end	foo2
 entry:
-  %0 = load float* @x, align 4
-  %1 = load float* @negone, align 4
+  %0 = load float, float* @x, align 4
+  %1 = load float, float* @negone, align 4
   %call = call float @copysignf(float %0, float %1) #2
   store float %call, float* @y, align 4
   ret void
@@ -57,8 +57,8 @@ entry:
 ; fmask: .set	macro
 ; fmask: .set	reorder
 ; fmask: .end	foo3
-  %0 = load double* @xd, align 8
-  %1 = load float* @oned, align 4
+  %0 = load double, double* @xd, align 8
+  %1 = load float, float* @oned, align 4
   %conv = fpext float %1 to double
   %call = call double @copysign(double %0, double %conv) #2
   store double %call, double* @yd, align 8
@@ -74,8 +74,8 @@ entry:
 ; fmask:	.ent	foo4
 ; fmask:	save	{{.*}}
 ; fmask:	.end	foo4
-  %0 = load double* @xd, align 8
-  %1 = load double* @negoned, align 8
+  %0 = load double, double* @xd, align 8
+  %1 = load double, double* @negoned, align 8
   %call = call double @copysign(double %0, double %1) #2
   store double %call, double* @yd, align 8
   ret void
@@ -84,7 +84,7 @@ entry:
 ; Function Attrs: nounwind
 define void @foo5() #0 {
 entry:
-  %0 = load float* @xn, align 4
+  %0 = load float, float* @xn, align 4
   %call = call float @fabsf(float %0) #2
   store float %call, float* @y, align 4
   ret void
@@ -96,7 +96,7 @@ declare float @fabsf(float) #1
 ; Function Attrs: nounwind
 define void @foo6() #0 {
 entry:
-  %0 = load double* @xdn, align 8
+  %0 = load double, double* @xdn, align 8
   %call = call double @fabs(double %0) #2
   store double %call, double* @yd, align 8
   ret void
@@ -108,7 +108,7 @@ declare double @fabs(double) #1
 ; Function Attrs: nounwind
 define void @foo7() #0 {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   %call = call float @sinf(float %0) #3
 ;pic:	lw	${{[0-9]+}}, %call16(sinf)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
@@ -122,7 +122,7 @@ declare float @sinf(float) #0
 ; Function Attrs: nounwind
 define void @foo8() #0 {
 entry:
-  %0 = load double* @xd, align 8
+  %0 = load double, double* @xd, align 8
   %call = call double @sin(double %0) #3
 ;pic:	lw	${{[0-9]+}}, %call16(sin)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
@@ -136,7 +136,7 @@ declare double @sin(double) #0
 ; Function Attrs: nounwind
 define void @foo9() #0 {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   %call = call float @cosf(float %0) #3
 ;pic:	lw	${{[0-9]+}}, %call16(cosf)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
@@ -150,7 +150,7 @@ declare float @cosf(float) #0
 ; Function Attrs: nounwind
 define void @foo10() #0 {
 entry:
-  %0 = load double* @xd, align 8
+  %0 = load double, double* @xd, align 8
   %call = call double @cos(double %0) #3
 ;pic:	lw	${{[0-9]+}}, %call16(cos)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
@@ -164,7 +164,7 @@ declare double @cos(double) #0
 ; Function Attrs: nounwind
 define void @foo11() #0 {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   %call = call float @sqrtf(float %0) #3
 ;pic:	lw	${{[0-9]+}}, %call16(sqrtf)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
@@ -178,7 +178,7 @@ declare float @sqrtf(float) #0
 ; Function Attrs: nounwind
 define void @foo12() #0 {
 entry:
-  %0 = load double* @xd, align 8
+  %0 = load double, double* @xd, align 8
   %call = call double @sqrt(double %0) #3
 ;pic:	lw	${{[0-9]+}}, %call16(sqrt)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
@@ -192,7 +192,7 @@ declare double @sqrt(double) #0
 ; Function Attrs: nounwind
 define void @foo13() #0 {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   %call = call float @floorf(float %0) #2
 ;pic:	lw	${{[0-9]+}}, %call16(floorf)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
@@ -206,7 +206,7 @@ declare float @floorf(float) #1
 ; Function Attrs: nounwind
 define void @foo14() #0 {
 entry:
-  %0 = load double* @xd, align 8
+  %0 = load double, double* @xd, align 8
   %call = call double @floor(double %0) #2
 ;pic:	lw	${{[0-9]+}}, %call16(floor)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
@@ -220,7 +220,7 @@ declare double @floor(double) #1
 ; Function Attrs: nounwind
 define void @foo15() #0 {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   %call = call float @nearbyintf(float %0) #2
 ;pic:	lw	${{[0-9]+}}, %call16(nearbyintf)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
@@ -234,7 +234,7 @@ declare float @nearbyintf(float) #1
 ; Function Attrs: nounwind
 define void @foo16() #0 {
 entry:
-  %0 = load double* @xd, align 8
+  %0 = load double, double* @xd, align 8
   %call = call double @nearbyint(double %0) #2
 ;pic:	lw	${{[0-9]+}}, %call16(nearbyint)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
@@ -248,7 +248,7 @@ declare double @nearbyint(double) #1
 ; Function Attrs: nounwind
 define void @foo17() #0 {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   %call = call float @ceilf(float %0) #2
 ;pic:	lw	${{[0-9]+}}, %call16(ceilf)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
@@ -262,7 +262,7 @@ declare float @ceilf(float) #1
 ; Function Attrs: nounwind
 define void @foo18() #0 {
 entry:
-  %0 = load double* @xd, align 8
+  %0 = load double, double* @xd, align 8
   %call = call double @ceil(double %0) #2
 ;pic:	lw	${{[0-9]+}}, %call16(ceil)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
@@ -276,7 +276,7 @@ declare double @ceil(double) #1
 ; Function Attrs: nounwind
 define void @foo19() #0 {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   %call = call float @rintf(float %0) #2
 ;pic:	lw	${{[0-9]+}}, %call16(rintf)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
@@ -290,7 +290,7 @@ declare float @rintf(float) #1
 ; Function Attrs: nounwind
 define void @foo20() #0 {
 entry:
-  %0 = load double* @xd, align 8
+  %0 = load double, double* @xd, align 8
   %call = call double @rint(double %0) #2
 ;pic:	lw	${{[0-9]+}}, %call16(rint)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
@@ -304,7 +304,7 @@ declare double @rint(double) #1
 ; Function Attrs: nounwind
 define void @foo21() #0 {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   %call = call float @truncf(float %0) #2
 ;pic:	lw	${{[0-9]+}}, %call16(truncf)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
@@ -318,7 +318,7 @@ declare float @truncf(float) #1
 ; Function Attrs: nounwind
 define void @foo22() #0 {
 entry:
-  %0 = load double* @xd, align 8
+  %0 = load double, double* @xd, align 8
   %call = call double @trunc(double %0) #2
 ;pic:	lw	${{[0-9]+}}, %call16(trunc)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
@@ -332,7 +332,7 @@ declare double @trunc(double) #1
 ; Function Attrs: nounwind
 define void @foo23() #0 {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   %call = call float @log2f(float %0) #3
 ;pic:	lw	${{[0-9]+}}, %call16(log2f)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
@@ -346,7 +346,7 @@ declare float @log2f(float) #0
 ; Function Attrs: nounwind
 define void @foo24() #0 {
 entry:
-  %0 = load double* @xd, align 8
+  %0 = load double, double* @xd, align 8
   %call = call double @log2(double %0) #3
 ;pic:	lw	${{[0-9]+}}, %call16(log2)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
@@ -360,7 +360,7 @@ declare double @log2(double) #0
 ; Function Attrs: nounwind
 define void @foo25() #0 {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   %call = call float @exp2f(float %0) #3
 ;pic:	lw	${{[0-9]+}}, %call16(exp2f)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
@@ -374,7 +374,7 @@ declare float @exp2f(float) #0
 ; Function Attrs: nounwind
 define void @foo26() #0 {
 entry:
-  %0 = load double* @xd, align 8
+  %0 = load double, double* @xd, align 8
   %call = call double @exp2(double %0) #3
 ;pic:	lw	${{[0-9]+}}, %call16(exp2)(${{[0-9]+}})
 ;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
diff --git a/test/CodeGen/Mips/fp16static.ll b/test/CodeGen/Mips/fp16static.ll
index beb063db15ca..4e5059ed39e9 100644
--- a/test/CodeGen/Mips/fp16static.ll
+++ b/test/CodeGen/Mips/fp16static.ll
@@ -4,8 +4,8 @@
 
 define void @foo() nounwind {
 entry:
-  %0 = load float* @x, align 4
-  %1 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
+  %1 = load float, float* @x, align 4
   %mul = fmul float %0, %1
   store float %mul, float* @x, align 4
 ; CHECK-STATIC16: jal	__mips16_mulsf3
diff --git a/test/CodeGen/Mips/fpbr.ll b/test/CodeGen/Mips/fpbr.ll
index 311b83015a56..27d7094376e6 100644
--- a/test/CodeGen/Mips/fpbr.ll
+++ b/test/CodeGen/Mips/fpbr.ll
@@ -24,11 +24,11 @@ entry:
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  tail call void (...)* @g0() nounwind
+  tail call void (...) @g0() nounwind
   br label %if.end
 
 if.else:                                          ; preds = %entry
-  tail call void (...)* @g1() nounwind
+  tail call void (...) @g1() nounwind
   br label %if.end
 
 if.end:                                           ; preds = %if.else, %if.then
@@ -57,11 +57,11 @@ entry:
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  tail call void (...)* @g0() nounwind
+  tail call void (...) @g0() nounwind
   br label %if.end
 
 if.else:                                          ; preds = %entry
-  tail call void (...)* @g1() nounwind
+  tail call void (...) @g1() nounwind
   br label %if.end
 
 if.end:                                           ; preds = %if.else, %if.then
@@ -86,11 +86,11 @@ entry:
   br i1 %cmp, label %if.else, label %if.then
 
 if.then:                                          ; preds = %entry
-  tail call void (...)* @g0() nounwind
+  tail call void (...) @g0() nounwind
   br label %if.end
 
 if.else:                                          ; preds = %entry
-  tail call void (...)* @g1() nounwind
+  tail call void (...) @g1() nounwind
   br label %if.end
 
 if.end:                                           ; preds = %if.else, %if.then
@@ -116,11 +116,11 @@ entry:
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  tail call void (...)* @g0() nounwind
+  tail call void (...) @g0() nounwind
   br label %if.end
 
 if.else:                                          ; preds = %entry
-  tail call void (...)* @g1() nounwind
+  tail call void (...) @g1() nounwind
   br label %if.end
 
 if.end:                                           ; preds = %if.else, %if.then
@@ -145,11 +145,11 @@ entry:
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  tail call void (...)* @g0() nounwind
+  tail call void (...) @g0() nounwind
   br label %if.end
 
 if.else:                                          ; preds = %entry
-  tail call void (...)* @g1() nounwind
+  tail call void (...) @g1() nounwind
   br label %if.end
 
 if.end:                                           ; preds = %if.else, %if.then
@@ -174,11 +174,11 @@ entry:
   br i1 %cmp, label %if.else, label %if.then
 
 if.then:                                          ; preds = %entry
-  tail call void (...)* @g0() nounwind
+  tail call void (...) @g0() nounwind
   br label %if.end
 
 if.else:                                          ; preds = %entry
-  tail call void (...)* @g1() nounwind
+  tail call void (...) @g1() nounwind
   br label %if.end
 
 if.end:                                           ; preds = %if.else, %if.then
diff --git a/test/CodeGen/Mips/fpneeded.ll b/test/CodeGen/Mips/fpneeded.ll
index fdd8e8f707ef..a89e2a593a4d 100644
--- a/test/CodeGen/Mips/fpneeded.ll
+++ b/test/CodeGen/Mips/fpneeded.ll
@@ -76,8 +76,8 @@ entry:
 define void @foo1() #0 {
 entry:
   store float 1.000000e+00, float* @zz, align 4
-  %0 = load float* @y, align 4
-  %1 = load float* @x, align 4
+  %0 = load float, float* @y, align 4
+  %1 = load float, float* @x, align 4
   %add = fadd float %0, %1
   store float %add, float* @z, align 4
   ret void
@@ -96,7 +96,7 @@ entry:
 
 define void @foo2() #0 {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   call void @vf(float %0)
   ret void
 }
diff --git a/test/CodeGen/Mips/fpnotneeded.ll b/test/CodeGen/Mips/fpnotneeded.ll
index e12d7baacdbb..02b8e8a345db 100644
--- a/test/CodeGen/Mips/fpnotneeded.ll
+++ b/test/CodeGen/Mips/fpnotneeded.ll
@@ -19,7 +19,7 @@ entry:
 
 define i32 @iv() #0 {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   ret i32 %0
 }
 
diff --git a/test/CodeGen/Mips/fpxx.ll b/test/CodeGen/Mips/fpxx.ll
index 7e2ed22e2d80..5b42ecec53e8 100644
--- a/test/CodeGen/Mips/fpxx.ll
+++ b/test/CodeGen/Mips/fpxx.ll
@@ -10,11 +10,11 @@
 ; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-NOFPXX
 ; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=64-FPXX
 
-; RUN-TODO: llc -march=mips64 -mcpu=mips4 -mattr=-n64,+o32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-O32-NOFPXX
-; RUN-TODO: llc -march=mips64 -mcpu=mips4 -mattr=-n64,+o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-O32-FPXX
+; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-O32-NOFPXX
+; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-O32-FPXX
 
-; RUN-TODO: llc -march=mips64 -mcpu=mips64 -mattr=-n64,+o32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-O32-NOFPXX
-; RUN-TODO: llc -march=mips64 -mcpu=mips64 -mattr=-n64,+o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-O32-FPXX
+; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-O32-NOFPXX
+; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-O32-FPXX
 
 declare double @dbl();
 
diff --git a/test/CodeGen/Mips/global-address.ll b/test/CodeGen/Mips/global-address.ll
index 0785cfcc0515..ecf5e563a577 100644
--- a/test/CodeGen/Mips/global-address.ll
+++ b/test/CodeGen/Mips/global-address.ll
@@ -1,9 +1,9 @@
 ; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-O32
 ; RUN: llc -march=mipsel -relocation-model=static -mtriple=mipsel-linux-gnu < %s | FileCheck %s -check-prefix=STATIC-O32
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n32 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N32
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n32 -relocation-model=static  -mtriple=mipsel-linux-gnu < %s | FileCheck %s -check-prefix=STATIC-N32
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n64 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N64
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n64 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N64
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n32 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N32
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n32 -relocation-model=static  -mtriple=mipsel-linux-gnu < %s | FileCheck %s -check-prefix=STATIC-N32
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n64 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N64
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n64 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N64
 
 @s1 = internal unnamed_addr global i32 8, align 4
 @g1 = external global i32
@@ -33,9 +33,9 @@ entry:
 ; STATIC-N64: lw  ${{[0-9]+}}, %got_ofst(s1)($[[R1]])
 ; STATIC-N64: ld  ${{[0-9]+}}, %got_disp(g1)
 
-  %0 = load i32* @s1, align 4
+  %0 = load i32, i32* @s1, align 4
   tail call void @foo1(i32 %0) nounwind
-  %1 = load i32* @g1, align 4
+  %1 = load i32, i32* @g1, align 4
   store i32 %1, i32* @s1, align 4
   %add = add nsw i32 %1, 2
   store i32 %add, i32* @g1, align 4
diff --git a/test/CodeGen/Mips/gpreg-lazy-binding.ll b/test/CodeGen/Mips/gpreg-lazy-binding.ll
index 3a636d82533f..800a74f5358f 100644
--- a/test/CodeGen/Mips/gpreg-lazy-binding.ll
+++ b/test/CodeGen/Mips/gpreg-lazy-binding.ll
@@ -19,7 +19,7 @@ declare void @externalFunc()
 
 define internal fastcc void @internalFunc() nounwind noinline {
 entry:
-  %0 = load i32* @g, align 4
+  %0 = load i32, i32* @g, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @g, align 4
   ret void
diff --git a/test/CodeGen/Mips/gprestore.ll b/test/CodeGen/Mips/gprestore.ll
index cbcf0c93491c..b1c2ad1d2756 100644
--- a/test/CodeGen/Mips/gprestore.ll
+++ b/test/CodeGen/Mips/gprestore.ll
@@ -17,11 +17,11 @@ entry:
 ; CHECK: jalr
 ; CHECK-NOT: got({{.*}})($gp)
 ; CHECK: lw $gp
-  tail call void (...)* @f1() nounwind
-  %tmp = load i32* @p, align 4
+  tail call void (...) @f1() nounwind
+  %tmp = load i32, i32* @p, align 4
   tail call void @f2(i32 %tmp) nounwind
-  %tmp1 = load i32* @q, align 4
-  %tmp2 = load i32* @r, align 4
+  %tmp1 = load i32, i32* @q, align 4
+  %tmp2 = load i32, i32* @r, align 4
   tail call void @f3(i32 %tmp1, i32 %tmp2) nounwind
   ret void
 }
diff --git a/test/CodeGen/Mips/helloworld.ll b/test/CodeGen/Mips/helloworld.ll
index 36f4ad6b55c0..a0dbdf3afd47 100644
--- a/test/CodeGen/Mips/helloworld.ll
+++ b/test/CodeGen/Mips/helloworld.ll
@@ -12,7 +12,7 @@
 
 define i32 @main() nounwind {
 entry:
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0))
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0))
   ret i32 0
 
 ; SR: 	.set	mips16
diff --git a/test/CodeGen/Mips/hf16_1.ll b/test/CodeGen/Mips/hf16_1.ll
index 9879cd523af3..103fd2d7fd63 100644
--- a/test/CodeGen/Mips/hf16_1.ll
+++ b/test/CodeGen/Mips/hf16_1.ll
@@ -11,96 +11,96 @@
 
 define void @foo() nounwind {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   call void @v_sf(float %0)
-  %1 = load double* @xd, align 8
+  %1 = load double, double* @xd, align 8
   call void @v_df(double %1)
-  %2 = load float* @x, align 4
-  %3 = load float* @y, align 4
+  %2 = load float, float* @x, align 4
+  %3 = load float, float* @y, align 4
   call void @v_sf_sf(float %2, float %3)
-  %4 = load double* @xd, align 8
-  %5 = load float* @x, align 4
+  %4 = load double, double* @xd, align 8
+  %5 = load float, float* @x, align 4
   call void @v_df_sf(double %4, float %5)
-  %6 = load double* @xd, align 8
-  %7 = load double* @yd, align 8
+  %6 = load double, double* @xd, align 8
+  %7 = load double, double* @yd, align 8
   call void @v_df_df(double %6, double %7)
   %call = call float @sf_v()
-  %8 = load float* @x, align 4
+  %8 = load float, float* @x, align 4
   %call1 = call float @sf_sf(float %8)
-  %9 = load double* @xd, align 8
+  %9 = load double, double* @xd, align 8
   %call2 = call float @sf_df(double %9)
-  %10 = load float* @x, align 4
-  %11 = load float* @y, align 4
+  %10 = load float, float* @x, align 4
+  %11 = load float, float* @y, align 4
   %call3 = call float @sf_sf_sf(float %10, float %11)
-  %12 = load double* @xd, align 8
-  %13 = load float* @x, align 4
+  %12 = load double, double* @xd, align 8
+  %13 = load float, float* @x, align 4
   %call4 = call float @sf_df_sf(double %12, float %13)
-  %14 = load double* @xd, align 8
-  %15 = load double* @yd, align 8
+  %14 = load double, double* @xd, align 8
+  %15 = load double, double* @yd, align 8
   %call5 = call float @sf_df_df(double %14, double %15)
   %call6 = call double @df_v()
-  %16 = load float* @x, align 4
+  %16 = load float, float* @x, align 4
   %call7 = call double @df_sf(float %16)
-  %17 = load double* @xd, align 8
+  %17 = load double, double* @xd, align 8
   %call8 = call double @df_df(double %17)
-  %18 = load float* @x, align 4
-  %19 = load float* @y, align 4
+  %18 = load float, float* @x, align 4
+  %19 = load float, float* @y, align 4
   %call9 = call double @df_sf_sf(float %18, float %19)
-  %20 = load double* @xd, align 8
-  %21 = load float* @x, align 4
+  %20 = load double, double* @xd, align 8
+  %21 = load float, float* @x, align 4
   %call10 = call double @df_df_sf(double %20, float %21)
-  %22 = load double* @xd, align 8
-  %23 = load double* @yd, align 8
+  %22 = load double, double* @xd, align 8
+  %23 = load double, double* @yd, align 8
   %call11 = call double @df_df_df(double %22, double %23)
   %call12 = call { float, float } @sc_v()
   %24 = extractvalue { float, float } %call12, 0
   %25 = extractvalue { float, float } %call12, 1
-  %26 = load float* @x, align 4
+  %26 = load float, float* @x, align 4
   %call13 = call { float, float } @sc_sf(float %26)
   %27 = extractvalue { float, float } %call13, 0
   %28 = extractvalue { float, float } %call13, 1
-  %29 = load double* @xd, align 8
+  %29 = load double, double* @xd, align 8
   %call14 = call { float, float } @sc_df(double %29)
   %30 = extractvalue { float, float } %call14, 0
   %31 = extractvalue { float, float } %call14, 1
-  %32 = load float* @x, align 4
-  %33 = load float* @y, align 4
+  %32 = load float, float* @x, align 4
+  %33 = load float, float* @y, align 4
   %call15 = call { float, float } @sc_sf_sf(float %32, float %33)
   %34 = extractvalue { float, float } %call15, 0
   %35 = extractvalue { float, float } %call15, 1
-  %36 = load double* @xd, align 8
-  %37 = load float* @x, align 4
+  %36 = load double, double* @xd, align 8
+  %37 = load float, float* @x, align 4
   %call16 = call { float, float } @sc_df_sf(double %36, float %37)
   %38 = extractvalue { float, float } %call16, 0
   %39 = extractvalue { float, float } %call16, 1
-  %40 = load double* @xd, align 8
-  %41 = load double* @yd, align 8
+  %40 = load double, double* @xd, align 8
+  %41 = load double, double* @yd, align 8
   %call17 = call { float, float } @sc_df_df(double %40, double %41)
   %42 = extractvalue { float, float } %call17, 0
   %43 = extractvalue { float, float } %call17, 1
   %call18 = call { double, double } @dc_v()
   %44 = extractvalue { double, double } %call18, 0
   %45 = extractvalue { double, double } %call18, 1
-  %46 = load float* @x, align 4
+  %46 = load float, float* @x, align 4
   %call19 = call { double, double } @dc_sf(float %46)
   %47 = extractvalue { double, double } %call19, 0
   %48 = extractvalue { double, double } %call19, 1
-  %49 = load double* @xd, align 8
+  %49 = load double, double* @xd, align 8
   %call20 = call { double, double } @dc_df(double %49)
   %50 = extractvalue { double, double } %call20, 0
   %51 = extractvalue { double, double } %call20, 1
-  %52 = load float* @x, align 4
-  %53 = load float* @y, align 4
+  %52 = load float, float* @x, align 4
+  %53 = load float, float* @y, align 4
   %call21 = call { double, double } @dc_sf_sf(float %52, float %53)
   %54 = extractvalue { double, double } %call21, 0
   %55 = extractvalue { double, double } %call21, 1
-  %56 = load double* @xd, align 8
-  %57 = load float* @x, align 4
+  %56 = load double, double* @xd, align 8
+  %57 = load float, float* @x, align 4
   %call22 = call { double, double } @dc_df_sf(double %56, float %57)
   %58 = extractvalue { double, double } %call22, 0
   %59 = extractvalue { double, double } %call22, 1
-  %60 = load double* @xd, align 8
-  %61 = load double* @yd, align 8
+  %60 = load double, double* @xd, align 8
+  %61 = load double, double* @yd, align 8
   %call23 = call { double, double } @dc_df_df(double %60, double %61)
   %62 = extractvalue { double, double } %call23, 0
   %63 = extractvalue { double, double } %call23, 1
diff --git a/test/CodeGen/Mips/hf16call32.ll b/test/CodeGen/Mips/hf16call32.ll
index aec9c71c485b..3b3f8f799111 100644
--- a/test/CodeGen/Mips/hf16call32.ll
+++ b/test/CodeGen/Mips/hf16call32.ll
@@ -33,30 +33,30 @@ entry:
   store float 1.000000e+00, float* @y, align 4
   store double 1.000000e+00, double* @xd, align 8
   store double 1.000000e+00, double* @yd, align 8
-  store float 1.000000e+00, float* getelementptr inbounds ({ float, float }* @xy, i32 0, i32 0)
-  store float 0.000000e+00, float* getelementptr inbounds ({ float, float }* @xy, i32 0, i32 1)
-  store double 1.000000e+00, double* getelementptr inbounds ({ double, double }* @xyd, i32 0, i32 0)
-  store double 0.000000e+00, double* getelementptr inbounds ({ double, double }* @xyd, i32 0, i32 1)
+  store float 1.000000e+00, float* getelementptr inbounds ({ float, float }, { float, float }* @xy, i32 0, i32 0)
+  store float 0.000000e+00, float* getelementptr inbounds ({ float, float }, { float, float }* @xy, i32 0, i32 1)
+  store double 1.000000e+00, double* getelementptr inbounds ({ double, double }, { double, double }* @xyd, i32 0, i32 0)
+  store double 0.000000e+00, double* getelementptr inbounds ({ double, double }, { double, double }* @xyd, i32 0, i32 1)
   store float 1.000000e+00, float* @ret_sf, align 4
   store double 1.000000e+00, double* @ret_df, align 8
-  store float 1.000000e+00, float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0)
-  store float 0.000000e+00, float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1)
-  store double 1.000000e+00, double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0)
-  store double 0.000000e+00, double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1)
+  store float 1.000000e+00, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 0)
+  store float 0.000000e+00, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 1)
+  store double 1.000000e+00, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 0)
+  store double 0.000000e+00, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 1)
   store float 0.000000e+00, float* @lx, align 4
   store float 0.000000e+00, float* @ly, align 4
   store double 0.000000e+00, double* @lxd, align 8
   store double 0.000000e+00, double* @lyd, align 8
-  store float 0.000000e+00, float* getelementptr inbounds ({ float, float }* @lxy, i32 0, i32 0)
-  store float 0.000000e+00, float* getelementptr inbounds ({ float, float }* @lxy, i32 0, i32 1)
-  store double 0.000000e+00, double* getelementptr inbounds ({ double, double }* @lxyd, i32 0, i32 0)
-  store double 0.000000e+00, double* getelementptr inbounds ({ double, double }* @lxyd, i32 0, i32 1)
+  store float 0.000000e+00, float* getelementptr inbounds ({ float, float }, { float, float }* @lxy, i32 0, i32 0)
+  store float 0.000000e+00, float* getelementptr inbounds ({ float, float }, { float, float }* @lxy, i32 0, i32 1)
+  store double 0.000000e+00, double* getelementptr inbounds ({ double, double }, { double, double }* @lxyd, i32 0, i32 0)
+  store double 0.000000e+00, double* getelementptr inbounds ({ double, double }, { double, double }* @lxyd, i32 0, i32 1)
   store float 0.000000e+00, float* @lret_sf, align 4
   store double 0.000000e+00, double* @lret_df, align 8
-  store float 0.000000e+00, float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0)
-  store float 0.000000e+00, float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1)
-  store double 0.000000e+00, double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0)
-  store double 0.000000e+00, double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1)
+  store float 0.000000e+00, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 0)
+  store float 0.000000e+00, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 1)
+  store double 0.000000e+00, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 0)
+  store double 0.000000e+00, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 1)
   ret void
 }
 
@@ -67,686 +67,686 @@ entry:
   store i32 0, i32* %retval
   call void @clear()
   store float 1.500000e+00, float* @lx, align 4
-  %0 = load float* @lx, align 4
+  %0 = load float, float* @lx, align 4
   call void @v_sf(float %0)
-  %1 = load float* @x, align 4
+  %1 = load float, float* @x, align 4
   %conv = fpext float %1 to double
-  %2 = load float* @lx, align 4
+  %2 = load float, float* @lx, align 4
   %conv1 = fpext float %2 to double
-  %3 = load float* @x, align 4
-  %4 = load float* @lx, align 4
+  %3 = load float, float* @x, align 4
+  %4 = load float, float* @lx, align 4
   %cmp = fcmp oeq float %3, %4
   %conv2 = zext i1 %cmp to i32
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i32 0, i32 0), double %conv, double %conv1, i32 %conv2)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str, i32 0, i32 0), double %conv, double %conv1, i32 %conv2)
   call void @clear()
   store double 0x41678C29C0000000, double* @lxd, align 8
-  %5 = load double* @lxd, align 8
+  %5 = load double, double* @lxd, align 8
   call void @v_df(double %5)
-  %6 = load double* @xd, align 8
-  %7 = load double* @lxd, align 8
-  %8 = load double* @xd, align 8
-  %9 = load double* @lxd, align 8
+  %6 = load double, double* @xd, align 8
+  %7 = load double, double* @lxd, align 8
+  %8 = load double, double* @xd, align 8
+  %9 = load double, double* @lxd, align 8
   %cmp3 = fcmp oeq double %8, %9
   %conv4 = zext i1 %cmp3 to i32
-  %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i32 0, i32 0), double %6, double %7, i32 %conv4)
+  %call5 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str, i32 0, i32 0), double %6, double %7, i32 %conv4)
   call void @clear()
   store float 9.000000e+00, float* @lx, align 4
   store float 1.000000e+01, float* @ly, align 4
-  %10 = load float* @lx, align 4
-  %11 = load float* @ly, align 4
+  %10 = load float, float* @lx, align 4
+  %11 = load float, float* @ly, align 4
   call void @v_sf_sf(float %10, float %11)
-  %12 = load float* @x, align 4
+  %12 = load float, float* @x, align 4
   %conv6 = fpext float %12 to double
-  %13 = load float* @lx, align 4
+  %13 = load float, float* @lx, align 4
   %conv7 = fpext float %13 to double
-  %14 = load float* @y, align 4
+  %14 = load float, float* @y, align 4
   %conv8 = fpext float %14 to double
-  %15 = load float* @ly, align 4
+  %15 = load float, float* @ly, align 4
   %conv9 = fpext float %15 to double
-  %16 = load float* @x, align 4
-  %17 = load float* @lx, align 4
+  %16 = load float, float* @x, align 4
+  %17 = load float, float* @lx, align 4
   %cmp10 = fcmp oeq float %16, %17
   br i1 %cmp10, label %land.rhs, label %land.end
 
 land.rhs:                                         ; preds = %entry
-  %18 = load float* @y, align 4
-  %19 = load float* @ly, align 4
+  %18 = load float, float* @y, align 4
+  %19 = load float, float* @ly, align 4
   %cmp12 = fcmp oeq float %18, %19
   br label %land.end
 
 land.end:                                         ; preds = %land.rhs, %entry
   %20 = phi i1 [ false, %entry ], [ %cmp12, %land.rhs ]
   %land.ext = zext i1 %20 to i32
-  %call14 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %conv6, double %conv7, double %conv8, double %conv9, i32 %land.ext)
+  %call14 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str1, i32 0, i32 0), double %conv6, double %conv7, double %conv8, double %conv9, i32 %land.ext)
   call void @clear()
   store float 0x3FFE666660000000, float* @lx, align 4
   store double 0x4007E613249FF279, double* @lyd, align 8
-  %21 = load float* @lx, align 4
-  %22 = load double* @lyd, align 8
+  %21 = load float, float* @lx, align 4
+  %22 = load double, double* @lyd, align 8
   call void @v_sf_df(float %21, double %22)
-  %23 = load float* @x, align 4
+  %23 = load float, float* @x, align 4
   %conv15 = fpext float %23 to double
-  %24 = load float* @lx, align 4
+  %24 = load float, float* @lx, align 4
   %conv16 = fpext float %24 to double
-  %25 = load double* @yd, align 8
-  %26 = load double* @lyd, align 8
-  %27 = load float* @x, align 4
-  %28 = load float* @lx, align 4
+  %25 = load double, double* @yd, align 8
+  %26 = load double, double* @lyd, align 8
+  %27 = load float, float* @x, align 4
+  %28 = load float, float* @lx, align 4
   %cmp17 = fcmp oeq float %27, %28
   %conv18 = zext i1 %cmp17 to i32
-  %29 = load double* @yd, align 8
-  %30 = load double* @lyd, align 8
+  %29 = load double, double* @yd, align 8
+  %30 = load double, double* @lyd, align 8
   %cmp19 = fcmp oeq double %29, %30
   %conv20 = zext i1 %cmp19 to i32
   %and = and i32 %conv18, %conv20
-  %call21 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %conv15, double %conv16, double %25, double %26, i32 %and)
+  %call21 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str1, i32 0, i32 0), double %conv15, double %conv16, double %25, double %26, i32 %and)
   call void @clear()
   store double 0x4194E54F94000000, double* @lxd, align 8
   store float 7.600000e+01, float* @ly, align 4
-  %31 = load double* @lxd, align 8
-  %32 = load float* @ly, align 4
+  %31 = load double, double* @lxd, align 8
+  %32 = load float, float* @ly, align 4
   call void @v_df_sf(double %31, float %32)
-  %33 = load double* @xd, align 8
-  %34 = load double* @lxd, align 8
-  %35 = load float* @y, align 4
+  %33 = load double, double* @xd, align 8
+  %34 = load double, double* @lxd, align 8
+  %35 = load float, float* @y, align 4
   %conv22 = fpext float %35 to double
-  %36 = load float* @ly, align 4
+  %36 = load float, float* @ly, align 4
   %conv23 = fpext float %36 to double
-  %37 = load double* @xd, align 8
-  %38 = load double* @lxd, align 8
+  %37 = load double, double* @xd, align 8
+  %38 = load double, double* @lxd, align 8
   %cmp24 = fcmp oeq double %37, %38
   %conv25 = zext i1 %cmp24 to i32
-  %39 = load float* @y, align 4
-  %40 = load float* @ly, align 4
+  %39 = load float, float* @y, align 4
+  %40 = load float, float* @ly, align 4
   %cmp26 = fcmp oeq float %39, %40
   %conv27 = zext i1 %cmp26 to i32
   %and28 = and i32 %conv25, %conv27
-  %call29 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %33, double %34, double %conv22, double %conv23, i32 %and28)
+  %call29 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str1, i32 0, i32 0), double %33, double %34, double %conv22, double %conv23, i32 %and28)
   call void @clear()
   store double 7.365198e+07, double* @lxd, align 8
   store double 0x416536CD80000000, double* @lyd, align 8
-  %41 = load double* @lxd, align 8
-  %42 = load double* @lyd, align 8
+  %41 = load double, double* @lxd, align 8
+  %42 = load double, double* @lyd, align 8
   call void @v_df_df(double %41, double %42)
-  %43 = load double* @xd, align 8
-  %44 = load double* @lxd, align 8
-  %45 = load double* @yd, align 8
-  %46 = load double* @lyd, align 8
-  %47 = load double* @xd, align 8
-  %48 = load double* @lxd, align 8
+  %43 = load double, double* @xd, align 8
+  %44 = load double, double* @lxd, align 8
+  %45 = load double, double* @yd, align 8
+  %46 = load double, double* @lyd, align 8
+  %47 = load double, double* @xd, align 8
+  %48 = load double, double* @lxd, align 8
   %cmp30 = fcmp oeq double %47, %48
   %conv31 = zext i1 %cmp30 to i32
-  %49 = load double* @yd, align 8
-  %50 = load double* @lyd, align 8
+  %49 = load double, double* @yd, align 8
+  %50 = load double, double* @lyd, align 8
   %cmp32 = fcmp oeq double %49, %50
   %conv33 = zext i1 %cmp32 to i32
   %and34 = and i32 %conv31, %conv33
-  %call35 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %43, double %44, double %45, double %46, i32 %and34)
+  %call35 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str1, i32 0, i32 0), double %43, double %44, double %45, double %46, i32 %and34)
   call void @clear()
   store float 0x4016666660000000, float* @ret_sf, align 4
   %call36 = call float @sf_v()
   store float %call36, float* @lret_sf, align 4
-  %51 = load float* @ret_sf, align 4
+  %51 = load float, float* @ret_sf, align 4
   %conv37 = fpext float %51 to double
-  %52 = load float* @lret_sf, align 4
+  %52 = load float, float* @lret_sf, align 4
   %conv38 = fpext float %52 to double
-  %53 = load float* @ret_sf, align 4
-  %54 = load float* @lret_sf, align 4
+  %53 = load float, float* @ret_sf, align 4
+  %54 = load float, float* @lret_sf, align 4
   %cmp39 = fcmp oeq float %53, %54
   %conv40 = zext i1 %cmp39 to i32
-  %call41 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i32 0, i32 0), double %conv37, double %conv38, i32 %conv40)
+  %call41 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str, i32 0, i32 0), double %conv37, double %conv38, i32 %conv40)
   call void @clear()
   store float 4.587300e+06, float* @ret_sf, align 4
   store float 3.420000e+02, float* @lx, align 4
-  %55 = load float* @lx, align 4
+  %55 = load float, float* @lx, align 4
   %call42 = call float @sf_sf(float %55)
   store float %call42, float* @lret_sf, align 4
-  %56 = load float* @ret_sf, align 4
+  %56 = load float, float* @ret_sf, align 4
   %conv43 = fpext float %56 to double
-  %57 = load float* @lret_sf, align 4
+  %57 = load float, float* @lret_sf, align 4
   %conv44 = fpext float %57 to double
-  %58 = load float* @x, align 4
+  %58 = load float, float* @x, align 4
   %conv45 = fpext float %58 to double
-  %59 = load float* @lx, align 4
+  %59 = load float, float* @lx, align 4
   %conv46 = fpext float %59 to double
-  %60 = load float* @ret_sf, align 4
-  %61 = load float* @lret_sf, align 4
+  %60 = load float, float* @ret_sf, align 4
+  %61 = load float, float* @lret_sf, align 4
   %cmp47 = fcmp oeq float %60, %61
   %conv48 = zext i1 %cmp47 to i32
-  %62 = load float* @x, align 4
-  %63 = load float* @lx, align 4
+  %62 = load float, float* @x, align 4
+  %63 = load float, float* @lx, align 4
   %cmp49 = fcmp oeq float %62, %63
   %conv50 = zext i1 %cmp49 to i32
   %and51 = and i32 %conv48, %conv50
-  %call52 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %conv43, double %conv44, double %conv45, double %conv46, i32 %and51)
+  %call52 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str1, i32 0, i32 0), double %conv43, double %conv44, double %conv45, double %conv46, i32 %and51)
   call void @clear()
   store float 4.445910e+06, float* @ret_sf, align 4
   store double 0x419A7DB294000000, double* @lxd, align 8
-  %64 = load double* @lxd, align 8
+  %64 = load double, double* @lxd, align 8
   %call53 = call float @sf_df(double %64)
   store float %call53, float* @lret_sf, align 4
-  %65 = load float* @ret_sf, align 4
+  %65 = load float, float* @ret_sf, align 4
   %conv54 = fpext float %65 to double
-  %66 = load float* @lret_sf, align 4
+  %66 = load float, float* @lret_sf, align 4
   %conv55 = fpext float %66 to double
-  %67 = load double* @xd, align 8
-  %68 = load double* @lxd, align 8
-  %69 = load float* @ret_sf, align 4
-  %70 = load float* @lret_sf, align 4
+  %67 = load double, double* @xd, align 8
+  %68 = load double, double* @lxd, align 8
+  %69 = load float, float* @ret_sf, align 4
+  %70 = load float, float* @lret_sf, align 4
   %cmp56 = fcmp oeq float %69, %70
   %conv57 = zext i1 %cmp56 to i32
-  %71 = load double* @xd, align 8
-  %72 = load double* @lxd, align 8
+  %71 = load double, double* @xd, align 8
+  %72 = load double, double* @lxd, align 8
   %cmp58 = fcmp oeq double %71, %72
   %conv59 = zext i1 %cmp58 to i32
   %and60 = and i32 %conv57, %conv59
-  %call61 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %conv54, double %conv55, double %67, double %68, i32 %and60)
+  %call61 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str1, i32 0, i32 0), double %conv54, double %conv55, double %67, double %68, i32 %and60)
   call void @clear()
   store float 0x3FFF4BC6A0000000, float* @ret_sf, align 4
   store float 4.445500e+03, float* @lx, align 4
   store float 0x4068ACCCC0000000, float* @ly, align 4
-  %73 = load float* @lx, align 4
-  %74 = load float* @ly, align 4
+  %73 = load float, float* @lx, align 4
+  %74 = load float, float* @ly, align 4
   %call62 = call float @sf_sf_sf(float %73, float %74)
   store float %call62, float* @lret_sf, align 4
-  %75 = load float* @ret_sf, align 4
+  %75 = load float, float* @ret_sf, align 4
   %conv63 = fpext float %75 to double
-  %76 = load float* @lret_sf, align 4
+  %76 = load float, float* @lret_sf, align 4
   %conv64 = fpext float %76 to double
-  %77 = load float* @x, align 4
+  %77 = load float, float* @x, align 4
   %conv65 = fpext float %77 to double
-  %78 = load float* @lx, align 4
+  %78 = load float, float* @lx, align 4
   %conv66 = fpext float %78 to double
-  %79 = load float* @y, align 4
+  %79 = load float, float* @y, align 4
   %conv67 = fpext float %79 to double
-  %80 = load float* @ly, align 4
+  %80 = load float, float* @ly, align 4
   %conv68 = fpext float %80 to double
-  %81 = load float* @ret_sf, align 4
-  %82 = load float* @lret_sf, align 4
+  %81 = load float, float* @ret_sf, align 4
+  %82 = load float, float* @lret_sf, align 4
   %cmp69 = fcmp oeq float %81, %82
   br i1 %cmp69, label %land.lhs.true, label %land.end76
 
 land.lhs.true:                                    ; preds = %land.end
-  %83 = load float* @x, align 4
-  %84 = load float* @lx, align 4
+  %83 = load float, float* @x, align 4
+  %84 = load float, float* @lx, align 4
   %cmp71 = fcmp oeq float %83, %84
   br i1 %cmp71, label %land.rhs73, label %land.end76
 
 land.rhs73:                                       ; preds = %land.lhs.true
-  %85 = load float* @y, align 4
-  %86 = load float* @ly, align 4
+  %85 = load float, float* @y, align 4
+  %86 = load float, float* @ly, align 4
   %cmp74 = fcmp oeq float %85, %86
   br label %land.end76
 
 land.end76:                                       ; preds = %land.rhs73, %land.lhs.true, %land.end
   %87 = phi i1 [ false, %land.lhs.true ], [ false, %land.end ], [ %cmp74, %land.rhs73 ]
   %land.ext77 = zext i1 %87 to i32
-  %call78 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %conv63, double %conv64, double %conv65, double %conv66, double %conv67, double %conv68, i32 %land.ext77)
+  %call78 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([22 x i8], [22 x i8]* @.str2, i32 0, i32 0), double %conv63, double %conv64, double %conv65, double %conv66, double %conv67, double %conv68, i32 %land.ext77)
   call void @clear()
   store float 9.991300e+04, float* @ret_sf, align 4
   store float 1.114500e+04, float* @lx, align 4
   store double 9.994445e+07, double* @lyd, align 8
-  %88 = load float* @lx, align 4
-  %89 = load double* @lyd, align 8
+  %88 = load float, float* @lx, align 4
+  %89 = load double, double* @lyd, align 8
   %call79 = call float @sf_sf_df(float %88, double %89)
   store float %call79, float* @lret_sf, align 4
-  %90 = load float* @ret_sf, align 4
+  %90 = load float, float* @ret_sf, align 4
   %conv80 = fpext float %90 to double
-  %91 = load float* @lret_sf, align 4
+  %91 = load float, float* @lret_sf, align 4
   %conv81 = fpext float %91 to double
-  %92 = load float* @x, align 4
+  %92 = load float, float* @x, align 4
   %conv82 = fpext float %92 to double
-  %93 = load float* @lx, align 4
+  %93 = load float, float* @lx, align 4
   %conv83 = fpext float %93 to double
-  %94 = load double* @yd, align 8
-  %95 = load double* @lyd, align 8
-  %96 = load float* @ret_sf, align 4
-  %97 = load float* @lret_sf, align 4
+  %94 = load double, double* @yd, align 8
+  %95 = load double, double* @lyd, align 8
+  %96 = load float, float* @ret_sf, align 4
+  %97 = load float, float* @lret_sf, align 4
   %cmp84 = fcmp oeq float %96, %97
   br i1 %cmp84, label %land.lhs.true86, label %land.end92
 
 land.lhs.true86:                                  ; preds = %land.end76
-  %98 = load float* @x, align 4
-  %99 = load float* @lx, align 4
+  %98 = load float, float* @x, align 4
+  %99 = load float, float* @lx, align 4
   %cmp87 = fcmp oeq float %98, %99
   br i1 %cmp87, label %land.rhs89, label %land.end92
 
 land.rhs89:                                       ; preds = %land.lhs.true86
-  %100 = load double* @yd, align 8
-  %101 = load double* @lyd, align 8
+  %100 = load double, double* @yd, align 8
+  %101 = load double, double* @lyd, align 8
   %cmp90 = fcmp oeq double %100, %101
   br label %land.end92
 
 land.end92:                                       ; preds = %land.rhs89, %land.lhs.true86, %land.end76
   %102 = phi i1 [ false, %land.lhs.true86 ], [ false, %land.end76 ], [ %cmp90, %land.rhs89 ]
   %land.ext93 = zext i1 %102 to i32
-  %call94 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %conv80, double %conv81, double %conv82, double %conv83, double %94, double %95, i32 %land.ext93)
+  %call94 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([22 x i8], [22 x i8]* @.str2, i32 0, i32 0), double %conv80, double %conv81, double %conv82, double %conv83, double %94, double %95, i32 %land.ext93)
   call void @clear()
   store float 0x417CCC7A00000000, float* @ret_sf, align 4
   store double 0x4172034530000000, double* @lxd, align 8
   store float 4.456200e+04, float* @ly, align 4
-  %103 = load double* @lxd, align 8
-  %104 = load float* @ly, align 4
+  %103 = load double, double* @lxd, align 8
+  %104 = load float, float* @ly, align 4
   %call95 = call float @sf_df_sf(double %103, float %104)
   store float %call95, float* @lret_sf, align 4
-  %105 = load float* @ret_sf, align 4
+  %105 = load float, float* @ret_sf, align 4
   %conv96 = fpext float %105 to double
-  %106 = load float* @lret_sf, align 4
+  %106 = load float, float* @lret_sf, align 4
   %conv97 = fpext float %106 to double
-  %107 = load double* @xd, align 8
-  %108 = load double* @lxd, align 8
-  %109 = load float* @y, align 4
+  %107 = load double, double* @xd, align 8
+  %108 = load double, double* @lxd, align 8
+  %109 = load float, float* @y, align 4
   %conv98 = fpext float %109 to double
-  %110 = load float* @ly, align 4
+  %110 = load float, float* @ly, align 4
   %conv99 = fpext float %110 to double
-  %111 = load float* @ret_sf, align 4
-  %112 = load float* @lret_sf, align 4
+  %111 = load float, float* @ret_sf, align 4
+  %112 = load float, float* @lret_sf, align 4
   %cmp100 = fcmp oeq float %111, %112
   br i1 %cmp100, label %land.lhs.true102, label %land.end108
 
 land.lhs.true102:                                 ; preds = %land.end92
-  %113 = load double* @xd, align 8
-  %114 = load double* @lxd, align 8
+  %113 = load double, double* @xd, align 8
+  %114 = load double, double* @lxd, align 8
   %cmp103 = fcmp oeq double %113, %114
   br i1 %cmp103, label %land.rhs105, label %land.end108
 
 land.rhs105:                                      ; preds = %land.lhs.true102
-  %115 = load float* @y, align 4
-  %116 = load float* @ly, align 4
+  %115 = load float, float* @y, align 4
+  %116 = load float, float* @ly, align 4
   %cmp106 = fcmp oeq float %115, %116
   br label %land.end108
 
 land.end108:                                      ; preds = %land.rhs105, %land.lhs.true102, %land.end92
   %117 = phi i1 [ false, %land.lhs.true102 ], [ false, %land.end92 ], [ %cmp106, %land.rhs105 ]
   %land.ext109 = zext i1 %117 to i32
-  %call110 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %conv96, double %conv97, double %107, double %108, double %conv98, double %conv99, i32 %land.ext109)
+  %call110 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([22 x i8], [22 x i8]* @.str2, i32 0, i32 0), double %conv96, double %conv97, double %107, double %108, double %conv98, double %conv99, i32 %land.ext109)
   call void @clear()
   store float 3.987721e+06, float* @ret_sf, align 4
   store double 0x3FF1F49F6DDDC2D8, double* @lxd, align 8
   store double 0x409129F306A2B170, double* @lyd, align 8
-  %118 = load double* @lxd, align 8
-  %119 = load double* @lyd, align 8
+  %118 = load double, double* @lxd, align 8
+  %119 = load double, double* @lyd, align 8
   %call111 = call float @sf_df_df(double %118, double %119)
   store float %call111, float* @lret_sf, align 4
-  %120 = load float* @ret_sf, align 4
+  %120 = load float, float* @ret_sf, align 4
   %conv112 = fpext float %120 to double
-  %121 = load float* @lret_sf, align 4
+  %121 = load float, float* @lret_sf, align 4
   %conv113 = fpext float %121 to double
-  %122 = load double* @xd, align 8
-  %123 = load double* @lxd, align 8
-  %124 = load double* @yd, align 8
-  %125 = load double* @lyd, align 8
-  %126 = load float* @ret_sf, align 4
-  %127 = load float* @lret_sf, align 4
+  %122 = load double, double* @xd, align 8
+  %123 = load double, double* @lxd, align 8
+  %124 = load double, double* @yd, align 8
+  %125 = load double, double* @lyd, align 8
+  %126 = load float, float* @ret_sf, align 4
+  %127 = load float, float* @lret_sf, align 4
   %cmp114 = fcmp oeq float %126, %127
   br i1 %cmp114, label %land.lhs.true116, label %land.end122
 
 land.lhs.true116:                                 ; preds = %land.end108
-  %128 = load double* @xd, align 8
-  %129 = load double* @lxd, align 8
+  %128 = load double, double* @xd, align 8
+  %129 = load double, double* @lxd, align 8
   %cmp117 = fcmp oeq double %128, %129
   br i1 %cmp117, label %land.rhs119, label %land.end122
 
 land.rhs119:                                      ; preds = %land.lhs.true116
-  %130 = load double* @yd, align 8
-  %131 = load double* @lyd, align 8
+  %130 = load double, double* @yd, align 8
+  %131 = load double, double* @lyd, align 8
   %cmp120 = fcmp oeq double %130, %131
   br label %land.end122
 
 land.end122:                                      ; preds = %land.rhs119, %land.lhs.true116, %land.end108
   %132 = phi i1 [ false, %land.lhs.true116 ], [ false, %land.end108 ], [ %cmp120, %land.rhs119 ]
   %land.ext123 = zext i1 %132 to i32
-  %call124 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %conv112, double %conv113, double %122, double %123, double %124, double %125, i32 %land.ext123)
+  %call124 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([22 x i8], [22 x i8]* @.str2, i32 0, i32 0), double %conv112, double %conv113, double %122, double %123, double %124, double %125, i32 %land.ext123)
   call void @clear()
   store double 1.561234e+01, double* @ret_df, align 8
   %call125 = call double @df_v()
   store double %call125, double* @lret_df, align 8
-  %133 = load double* @ret_df, align 8
-  %134 = load double* @lret_df, align 8
-  %135 = load double* @ret_df, align 8
-  %136 = load double* @lret_df, align 8
+  %133 = load double, double* @ret_df, align 8
+  %134 = load double, double* @lret_df, align 8
+  %135 = load double, double* @ret_df, align 8
+  %136 = load double, double* @lret_df, align 8
   %cmp126 = fcmp oeq double %135, %136
   %conv127 = zext i1 %cmp126 to i32
-  %call128 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i32 0, i32 0), double %133, double %134, i32 %conv127)
+  %call128 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str, i32 0, i32 0), double %133, double %134, i32 %conv127)
   call void @clear()
   store double 1.345873e+01, double* @ret_df, align 8
   store float 3.434520e+05, float* @lx, align 4
-  %137 = load float* @lx, align 4
+  %137 = load float, float* @lx, align 4
   %call129 = call double @df_sf(float %137)
   store double %call129, double* @lret_df, align 8
-  %138 = load double* @ret_df, align 8
-  %139 = load double* @lret_df, align 8
-  %140 = load float* @x, align 4
+  %138 = load double, double* @ret_df, align 8
+  %139 = load double, double* @lret_df, align 8
+  %140 = load float, float* @x, align 4
   %conv130 = fpext float %140 to double
-  %141 = load float* @lx, align 4
+  %141 = load float, float* @lx, align 4
   %conv131 = fpext float %141 to double
-  %142 = load double* @ret_df, align 8
-  %143 = load double* @lret_df, align 8
+  %142 = load double, double* @ret_df, align 8
+  %143 = load double, double* @lret_df, align 8
   %cmp132 = fcmp oeq double %142, %143
   %conv133 = zext i1 %cmp132 to i32
-  %144 = load float* @x, align 4
-  %145 = load float* @lx, align 4
+  %144 = load float, float* @x, align 4
+  %145 = load float, float* @lx, align 4
   %cmp134 = fcmp oeq float %144, %145
   %conv135 = zext i1 %cmp134 to i32
   %and136 = and i32 %conv133, %conv135
-  %call137 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %138, double %139, double %conv130, double %conv131, i32 %and136)
+  %call137 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str1, i32 0, i32 0), double %138, double %139, double %conv130, double %conv131, i32 %and136)
   call void @clear()
   store double 0x4084F3AB7AA25D8D, double* @ret_df, align 8
   store double 0x4114F671D2F1A9FC, double* @lxd, align 8
-  %146 = load double* @lxd, align 8
+  %146 = load double, double* @lxd, align 8
   %call138 = call double @df_df(double %146)
   store double %call138, double* @lret_df, align 8
-  %147 = load double* @ret_df, align 8
-  %148 = load double* @lret_df, align 8
-  %149 = load double* @xd, align 8
-  %150 = load double* @lxd, align 8
-  %151 = load double* @ret_df, align 8
-  %152 = load double* @lret_df, align 8
+  %147 = load double, double* @ret_df, align 8
+  %148 = load double, double* @lret_df, align 8
+  %149 = load double, double* @xd, align 8
+  %150 = load double, double* @lxd, align 8
+  %151 = load double, double* @ret_df, align 8
+  %152 = load double, double* @lret_df, align 8
   %cmp139 = fcmp oeq double %151, %152
   %conv140 = zext i1 %cmp139 to i32
-  %153 = load double* @xd, align 8
-  %154 = load double* @lxd, align 8
+  %153 = load double, double* @xd, align 8
+  %154 = load double, double* @lxd, align 8
   %cmp141 = fcmp oeq double %153, %154
   %conv142 = zext i1 %cmp141 to i32
   %and143 = and i32 %conv140, %conv142
-  %call144 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str1, i32 0, i32 0), double %147, double %148, double %149, double %150, i32 %and143)
+  %call144 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str1, i32 0, i32 0), double %147, double %148, double %149, double %150, i32 %and143)
   call void @clear()
   store double 6.781956e+03, double* @ret_df, align 8
   store float 4.445500e+03, float* @lx, align 4
   store float 0x4068ACCCC0000000, float* @ly, align 4
-  %155 = load float* @lx, align 4
-  %156 = load float* @ly, align 4
+  %155 = load float, float* @lx, align 4
+  %156 = load float, float* @ly, align 4
   %call145 = call double @df_sf_sf(float %155, float %156)
   store double %call145, double* @lret_df, align 8
-  %157 = load double* @ret_df, align 8
-  %158 = load double* @lret_df, align 8
-  %159 = load float* @x, align 4
+  %157 = load double, double* @ret_df, align 8
+  %158 = load double, double* @lret_df, align 8
+  %159 = load float, float* @x, align 4
   %conv146 = fpext float %159 to double
-  %160 = load float* @lx, align 4
+  %160 = load float, float* @lx, align 4
   %conv147 = fpext float %160 to double
-  %161 = load float* @y, align 4
+  %161 = load float, float* @y, align 4
   %conv148 = fpext float %161 to double
-  %162 = load float* @ly, align 4
+  %162 = load float, float* @ly, align 4
   %conv149 = fpext float %162 to double
-  %163 = load double* @ret_df, align 8
-  %164 = load double* @lret_df, align 8
+  %163 = load double, double* @ret_df, align 8
+  %164 = load double, double* @lret_df, align 8
   %cmp150 = fcmp oeq double %163, %164
   br i1 %cmp150, label %land.lhs.true152, label %land.end158
 
 land.lhs.true152:                                 ; preds = %land.end122
-  %165 = load float* @x, align 4
-  %166 = load float* @lx, align 4
+  %165 = load float, float* @x, align 4
+  %166 = load float, float* @lx, align 4
   %cmp153 = fcmp oeq float %165, %166
   br i1 %cmp153, label %land.rhs155, label %land.end158
 
 land.rhs155:                                      ; preds = %land.lhs.true152
-  %167 = load float* @y, align 4
-  %168 = load float* @ly, align 4
+  %167 = load float, float* @y, align 4
+  %168 = load float, float* @ly, align 4
   %cmp156 = fcmp oeq float %167, %168
   br label %land.end158
 
 land.end158:                                      ; preds = %land.rhs155, %land.lhs.true152, %land.end122
   %169 = phi i1 [ false, %land.lhs.true152 ], [ false, %land.end122 ], [ %cmp156, %land.rhs155 ]
   %land.ext159 = zext i1 %169 to i32
-  %call160 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %157, double %158, double %conv146, double %conv147, double %conv148, double %conv149, i32 %land.ext159)
+  %call160 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([22 x i8], [22 x i8]* @.str2, i32 0, i32 0), double %157, double %158, double %conv146, double %conv147, double %conv148, double %conv149, i32 %land.ext159)
   call void @clear()
   store double 1.889130e+05, double* @ret_df, align 8
   store float 9.111450e+05, float* @lx, align 4
   store double 0x4185320A58000000, double* @lyd, align 8
-  %170 = load float* @lx, align 4
-  %171 = load double* @lyd, align 8
+  %170 = load float, float* @lx, align 4
+  %171 = load double, double* @lyd, align 8
   %call161 = call double @df_sf_df(float %170, double %171)
   store double %call161, double* @lret_df, align 8
-  %172 = load double* @ret_df, align 8
-  %173 = load double* @lret_df, align 8
-  %174 = load float* @x, align 4
+  %172 = load double, double* @ret_df, align 8
+  %173 = load double, double* @lret_df, align 8
+  %174 = load float, float* @x, align 4
   %conv162 = fpext float %174 to double
-  %175 = load float* @lx, align 4
+  %175 = load float, float* @lx, align 4
   %conv163 = fpext float %175 to double
-  %176 = load double* @yd, align 8
-  %177 = load double* @lyd, align 8
-  %178 = load double* @ret_df, align 8
-  %179 = load double* @lret_df, align 8
+  %176 = load double, double* @yd, align 8
+  %177 = load double, double* @lyd, align 8
+  %178 = load double, double* @ret_df, align 8
+  %179 = load double, double* @lret_df, align 8
   %cmp164 = fcmp oeq double %178, %179
   br i1 %cmp164, label %land.lhs.true166, label %land.end172
 
 land.lhs.true166:                                 ; preds = %land.end158
-  %180 = load float* @x, align 4
-  %181 = load float* @lx, align 4
+  %180 = load float, float* @x, align 4
+  %181 = load float, float* @lx, align 4
   %cmp167 = fcmp oeq float %180, %181
   br i1 %cmp167, label %land.rhs169, label %land.end172
 
 land.rhs169:                                      ; preds = %land.lhs.true166
-  %182 = load double* @yd, align 8
-  %183 = load double* @lyd, align 8
+  %182 = load double, double* @yd, align 8
+  %183 = load double, double* @lyd, align 8
   %cmp170 = fcmp oeq double %182, %183
   br label %land.end172
 
 land.end172:                                      ; preds = %land.rhs169, %land.lhs.true166, %land.end158
   %184 = phi i1 [ false, %land.lhs.true166 ], [ false, %land.end158 ], [ %cmp170, %land.rhs169 ]
   %land.ext173 = zext i1 %184 to i32
-  %call174 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %172, double %173, double %conv162, double %conv163, double %176, double %177, i32 %land.ext173)
+  %call174 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([22 x i8], [22 x i8]* @.str2, i32 0, i32 0), double %172, double %173, double %conv162, double %conv163, double %176, double %177, i32 %land.ext173)
   call void @clear()
   store double 0x418B2DB900000000, double* @ret_df, align 8
   store double 0x41B1EF2ED3000000, double* @lxd, align 8
   store float 1.244562e+06, float* @ly, align 4
-  %185 = load double* @lxd, align 8
-  %186 = load float* @ly, align 4
+  %185 = load double, double* @lxd, align 8
+  %186 = load float, float* @ly, align 4
   %call175 = call double @df_df_sf(double %185, float %186)
   store double %call175, double* @lret_df, align 8
-  %187 = load double* @ret_df, align 8
-  %188 = load double* @lret_df, align 8
-  %189 = load double* @xd, align 8
-  %190 = load double* @lxd, align 8
-  %191 = load float* @y, align 4
+  %187 = load double, double* @ret_df, align 8
+  %188 = load double, double* @lret_df, align 8
+  %189 = load double, double* @xd, align 8
+  %190 = load double, double* @lxd, align 8
+  %191 = load float, float* @y, align 4
   %conv176 = fpext float %191 to double
-  %192 = load float* @ly, align 4
+  %192 = load float, float* @ly, align 4
   %conv177 = fpext float %192 to double
-  %193 = load double* @ret_df, align 8
-  %194 = load double* @lret_df, align 8
+  %193 = load double, double* @ret_df, align 8
+  %194 = load double, double* @lret_df, align 8
   %cmp178 = fcmp oeq double %193, %194
   br i1 %cmp178, label %land.lhs.true180, label %land.end186
 
 land.lhs.true180:                                 ; preds = %land.end172
-  %195 = load double* @xd, align 8
-  %196 = load double* @lxd, align 8
+  %195 = load double, double* @xd, align 8
+  %196 = load double, double* @lxd, align 8
   %cmp181 = fcmp oeq double %195, %196
   br i1 %cmp181, label %land.rhs183, label %land.end186
 
 land.rhs183:                                      ; preds = %land.lhs.true180
-  %197 = load float* @y, align 4
-  %198 = load float* @ly, align 4
+  %197 = load float, float* @y, align 4
+  %198 = load float, float* @ly, align 4
   %cmp184 = fcmp oeq float %197, %198
   br label %land.end186
 
 land.end186:                                      ; preds = %land.rhs183, %land.lhs.true180, %land.end172
   %199 = phi i1 [ false, %land.lhs.true180 ], [ false, %land.end172 ], [ %cmp184, %land.rhs183 ]
   %land.ext187 = zext i1 %199 to i32
-  %call188 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %187, double %188, double %189, double %190, double %conv176, double %conv177, i32 %land.ext187)
+  %call188 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([22 x i8], [22 x i8]* @.str2, i32 0, i32 0), double %187, double %188, double %189, double %190, double %conv176, double %conv177, i32 %land.ext187)
   call void @clear()
   store double 3.987721e+06, double* @ret_df, align 8
   store double 5.223560e+00, double* @lxd, align 8
   store double 0x40B7D37CC1A8AC5C, double* @lyd, align 8
-  %200 = load double* @lxd, align 8
-  %201 = load double* @lyd, align 8
+  %200 = load double, double* @lxd, align 8
+  %201 = load double, double* @lyd, align 8
   %call189 = call double @df_df_df(double %200, double %201)
   store double %call189, double* @lret_df, align 8
-  %202 = load double* @ret_df, align 8
-  %203 = load double* @lret_df, align 8
-  %204 = load double* @xd, align 8
-  %205 = load double* @lxd, align 8
-  %206 = load double* @yd, align 8
-  %207 = load double* @lyd, align 8
-  %208 = load double* @ret_df, align 8
-  %209 = load double* @lret_df, align 8
+  %202 = load double, double* @ret_df, align 8
+  %203 = load double, double* @lret_df, align 8
+  %204 = load double, double* @xd, align 8
+  %205 = load double, double* @lxd, align 8
+  %206 = load double, double* @yd, align 8
+  %207 = load double, double* @lyd, align 8
+  %208 = load double, double* @ret_df, align 8
+  %209 = load double, double* @lret_df, align 8
   %cmp190 = fcmp oeq double %208, %209
   br i1 %cmp190, label %land.lhs.true192, label %land.end198
 
 land.lhs.true192:                                 ; preds = %land.end186
-  %210 = load double* @xd, align 8
-  %211 = load double* @lxd, align 8
+  %210 = load double, double* @xd, align 8
+  %211 = load double, double* @lxd, align 8
   %cmp193 = fcmp oeq double %210, %211
   br i1 %cmp193, label %land.rhs195, label %land.end198
 
 land.rhs195:                                      ; preds = %land.lhs.true192
-  %212 = load double* @yd, align 8
-  %213 = load double* @lyd, align 8
+  %212 = load double, double* @yd, align 8
+  %213 = load double, double* @lyd, align 8
   %cmp196 = fcmp oeq double %212, %213
   br label %land.end198
 
 land.end198:                                      ; preds = %land.rhs195, %land.lhs.true192, %land.end186
   %214 = phi i1 [ false, %land.lhs.true192 ], [ false, %land.end186 ], [ %cmp196, %land.rhs195 ]
   %land.ext199 = zext i1 %214 to i32
-  %call200 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str2, i32 0, i32 0), double %202, double %203, double %204, double %205, double %206, double %207, i32 %land.ext199)
+  %call200 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([22 x i8], [22 x i8]* @.str2, i32 0, i32 0), double %202, double %203, double %204, double %205, double %206, double %207, i32 %land.ext199)
   call void @clear()
-  store float 4.500000e+00, float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0)
-  store float 7.000000e+00, float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1)
+  store float 4.500000e+00, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 0)
+  store float 7.000000e+00, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 1)
   %call201 = call { float, float } @sc_v()
   %215 = extractvalue { float, float } %call201, 0
   %216 = extractvalue { float, float } %call201, 1
-  store float %215, float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0)
-  store float %216, float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1)
-  %ret_sc.real = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0)
-  %ret_sc.imag = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1)
+  store float %215, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 0)
+  store float %216, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 1)
+  %ret_sc.real = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 0)
+  %ret_sc.imag = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 1)
   %conv202 = fpext float %ret_sc.real to double
   %conv203 = fpext float %ret_sc.imag to double
-  %ret_sc.real204 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0)
-  %ret_sc.imag205 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1)
+  %ret_sc.real204 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 0)
+  %ret_sc.imag205 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 1)
   %conv206 = fpext float %ret_sc.real204 to double
   %conv207 = fpext float %ret_sc.imag205 to double
-  %lret_sc.real = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0)
-  %lret_sc.imag = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1)
+  %lret_sc.real = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 0)
+  %lret_sc.imag = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 1)
   %conv208 = fpext float %lret_sc.real to double
   %conv209 = fpext float %lret_sc.imag to double
-  %lret_sc.real210 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0)
-  %lret_sc.imag211 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1)
+  %lret_sc.real210 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 0)
+  %lret_sc.imag211 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 1)
   %conv212 = fpext float %lret_sc.real210 to double
   %conv213 = fpext float %lret_sc.imag211 to double
-  %ret_sc.real214 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0)
-  %ret_sc.imag215 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1)
-  %lret_sc.real216 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0)
-  %lret_sc.imag217 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1)
+  %ret_sc.real214 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 0)
+  %ret_sc.imag215 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 1)
+  %lret_sc.real216 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 0)
+  %lret_sc.imag217 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 1)
   %cmp.r = fcmp oeq float %ret_sc.real214, %lret_sc.real216
   %cmp.i = fcmp oeq float %ret_sc.imag215, %lret_sc.imag217
   %and.ri = and i1 %cmp.r, %cmp.i
   %conv218 = zext i1 %and.ri to i32
-  %call219 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([18 x i8]* @.str3, i32 0, i32 0), double %conv202, double %conv207, double %conv208, double %conv213, i32 %conv218)
+  %call219 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str3, i32 0, i32 0), double %conv202, double %conv207, double %conv208, double %conv213, i32 %conv218)
   call void @clear()
   store float 0x3FF7A99300000000, float* @lx, align 4
-  store float 4.500000e+00, float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0)
-  store float 7.000000e+00, float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1)
-  %217 = load float* @lx, align 4
+  store float 4.500000e+00, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 0)
+  store float 7.000000e+00, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 1)
+  %217 = load float, float* @lx, align 4
   %call220 = call { float, float } @sc_sf(float %217)
   %218 = extractvalue { float, float } %call220, 0
   %219 = extractvalue { float, float } %call220, 1
-  store float %218, float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0)
-  store float %219, float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1)
-  %ret_sc.real221 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0)
-  %ret_sc.imag222 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1)
+  store float %218, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 0)
+  store float %219, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 1)
+  %ret_sc.real221 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 0)
+  %ret_sc.imag222 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 1)
   %conv223 = fpext float %ret_sc.real221 to double
   %conv224 = fpext float %ret_sc.imag222 to double
-  %ret_sc.real225 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0)
-  %ret_sc.imag226 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1)
+  %ret_sc.real225 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 0)
+  %ret_sc.imag226 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 1)
   %conv227 = fpext float %ret_sc.real225 to double
   %conv228 = fpext float %ret_sc.imag226 to double
-  %lret_sc.real229 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0)
-  %lret_sc.imag230 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1)
+  %lret_sc.real229 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 0)
+  %lret_sc.imag230 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 1)
   %conv231 = fpext float %lret_sc.real229 to double
   %conv232 = fpext float %lret_sc.imag230 to double
-  %lret_sc.real233 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0)
-  %lret_sc.imag234 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1)
+  %lret_sc.real233 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 0)
+  %lret_sc.imag234 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 1)
   %conv235 = fpext float %lret_sc.real233 to double
   %conv236 = fpext float %lret_sc.imag234 to double
-  %220 = load float* @x, align 4
+  %220 = load float, float* @x, align 4
   %conv237 = fpext float %220 to double
-  %221 = load float* @lx, align 4
+  %221 = load float, float* @lx, align 4
   %conv238 = fpext float %221 to double
-  %ret_sc.real239 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 0)
-  %ret_sc.imag240 = load float* getelementptr inbounds ({ float, float }* @ret_sc, i32 0, i32 1)
-  %lret_sc.real241 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 0)
-  %lret_sc.imag242 = load float* getelementptr inbounds ({ float, float }* @lret_sc, i32 0, i32 1)
+  %ret_sc.real239 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 0)
+  %ret_sc.imag240 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @ret_sc, i32 0, i32 1)
+  %lret_sc.real241 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 0)
+  %lret_sc.imag242 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @lret_sc, i32 0, i32 1)
   %cmp.r243 = fcmp oeq float %ret_sc.real239, %lret_sc.real241
   %cmp.i244 = fcmp oeq float %ret_sc.imag240, %lret_sc.imag242
   %and.ri245 = and i1 %cmp.r243, %cmp.i244
   br i1 %and.ri245, label %land.rhs247, label %land.end250
 
 land.rhs247:                                      ; preds = %land.end198
-  %222 = load float* @x, align 4
-  %223 = load float* @lx, align 4
+  %222 = load float, float* @x, align 4
+  %223 = load float, float* @lx, align 4
   %cmp248 = fcmp oeq float %222, %223
   br label %land.end250
 
 land.end250:                                      ; preds = %land.rhs247, %land.end198
   %224 = phi i1 [ false, %land.end198 ], [ %cmp248, %land.rhs247 ]
   %land.ext251 = zext i1 %224 to i32
-  %call252 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([24 x i8]* @.str4, i32 0, i32 0), double %conv223, double %conv228, double %conv231, double %conv236, double %conv237, double %conv238, i32 %land.ext251)
+  %call252 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str4, i32 0, i32 0), double %conv223, double %conv228, double %conv231, double %conv236, double %conv237, double %conv238, i32 %land.ext251)
   call void @clear()
-  store double 1.234500e+03, double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0)
-  store double 7.677000e+03, double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1)
+  store double 1.234500e+03, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 0)
+  store double 7.677000e+03, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 1)
   %call253 = call { double, double } @dc_v()
   %225 = extractvalue { double, double } %call253, 0
   %226 = extractvalue { double, double } %call253, 1
-  store double %225, double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0)
-  store double %226, double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1)
-  %ret_dc.real = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0)
-  %ret_dc.imag = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1)
-  %ret_dc.real254 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0)
-  %ret_dc.imag255 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1)
-  %lret_dc.real = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0)
-  %lret_dc.imag = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1)
-  %lret_dc.real256 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0)
-  %lret_dc.imag257 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1)
-  %ret_dc.real258 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0)
-  %ret_dc.imag259 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1)
-  %lret_dc.real260 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0)
-  %lret_dc.imag261 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1)
+  store double %225, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 0)
+  store double %226, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 1)
+  %ret_dc.real = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 0)
+  %ret_dc.imag = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 1)
+  %ret_dc.real254 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 0)
+  %ret_dc.imag255 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 1)
+  %lret_dc.real = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 0)
+  %lret_dc.imag = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 1)
+  %lret_dc.real256 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 0)
+  %lret_dc.imag257 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 1)
+  %ret_dc.real258 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 0)
+  %ret_dc.imag259 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 1)
+  %lret_dc.real260 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 0)
+  %lret_dc.imag261 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 1)
   %cmp.r262 = fcmp oeq double %ret_dc.real258, %lret_dc.real260
   %cmp.i263 = fcmp oeq double %ret_dc.imag259, %lret_dc.imag261
   %and.ri264 = and i1 %cmp.r262, %cmp.i263
   %conv265 = zext i1 %and.ri264 to i32
-  %call266 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([18 x i8]* @.str3, i32 0, i32 0), double %ret_dc.real, double %ret_dc.imag255, double %lret_dc.real, double %lret_dc.imag257, i32 %conv265)
+  %call266 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str3, i32 0, i32 0), double %ret_dc.real, double %ret_dc.imag255, double %lret_dc.real, double %lret_dc.imag257, i32 %conv265)
   call void @clear()
   store double 0x40AAF6F532617C1C, double* @lxd, align 8
-  store double 4.444500e+03, double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0)
-  store double 7.888000e+03, double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1)
-  %227 = load float* @lx, align 4
+  store double 4.444500e+03, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 0)
+  store double 7.888000e+03, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 1)
+  %227 = load float, float* @lx, align 4
   %call267 = call { double, double } @dc_sf(float %227)
   %228 = extractvalue { double, double } %call267, 0
   %229 = extractvalue { double, double } %call267, 1
-  store double %228, double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0)
-  store double %229, double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1)
-  %ret_dc.real268 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0)
-  %ret_dc.imag269 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1)
-  %ret_dc.real270 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0)
-  %ret_dc.imag271 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1)
-  %lret_dc.real272 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0)
-  %lret_dc.imag273 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1)
-  %lret_dc.real274 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0)
-  %lret_dc.imag275 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1)
-  %230 = load float* @x, align 4
+  store double %228, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 0)
+  store double %229, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 1)
+  %ret_dc.real268 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 0)
+  %ret_dc.imag269 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 1)
+  %ret_dc.real270 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 0)
+  %ret_dc.imag271 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 1)
+  %lret_dc.real272 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 0)
+  %lret_dc.imag273 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 1)
+  %lret_dc.real274 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 0)
+  %lret_dc.imag275 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 1)
+  %230 = load float, float* @x, align 4
   %conv276 = fpext float %230 to double
-  %231 = load float* @lx, align 4
+  %231 = load float, float* @lx, align 4
   %conv277 = fpext float %231 to double
-  %ret_dc.real278 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 0)
-  %ret_dc.imag279 = load double* getelementptr inbounds ({ double, double }* @ret_dc, i32 0, i32 1)
-  %lret_dc.real280 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 0)
-  %lret_dc.imag281 = load double* getelementptr inbounds ({ double, double }* @lret_dc, i32 0, i32 1)
+  %ret_dc.real278 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 0)
+  %ret_dc.imag279 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @ret_dc, i32 0, i32 1)
+  %lret_dc.real280 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 0)
+  %lret_dc.imag281 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @lret_dc, i32 0, i32 1)
   %cmp.r282 = fcmp oeq double %ret_dc.real278, %lret_dc.real280
   %cmp.i283 = fcmp oeq double %ret_dc.imag279, %lret_dc.imag281
   %and.ri284 = and i1 %cmp.r282, %cmp.i283
   br i1 %and.ri284, label %land.rhs286, label %land.end289
 
 land.rhs286:                                      ; preds = %land.end250
-  %232 = load float* @x, align 4
-  %233 = load float* @lx, align 4
+  %232 = load float, float* @x, align 4
+  %233 = load float, float* @lx, align 4
   %cmp287 = fcmp oeq float %232, %233
   br label %land.end289
 
 land.end289:                                      ; preds = %land.rhs286, %land.end250
   %234 = phi i1 [ false, %land.end250 ], [ %cmp287, %land.rhs286 ]
   %land.ext290 = zext i1 %234 to i32
-  %call291 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([24 x i8]* @.str4, i32 0, i32 0), double %ret_dc.real268, double %ret_dc.imag271, double %lret_dc.real272, double %lret_dc.imag275, double %conv276, double %conv277, i32 %land.ext290)
-  %235 = load i32* %retval
+  %call291 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str4, i32 0, i32 0), double %ret_dc.real268, double %ret_dc.imag271, double %lret_dc.real272, double %lret_dc.imag275, double %conv276, double %conv277, i32 %land.ext290)
+  %235 = load i32, i32* %retval
   ret i32 %235
 }
 
diff --git a/test/CodeGen/Mips/hf16call32_body.ll b/test/CodeGen/Mips/hf16call32_body.ll
index adac31460c44..d06256cc564f 100644
--- a/test/CodeGen/Mips/hf16call32_body.ll
+++ b/test/CodeGen/Mips/hf16call32_body.ll
@@ -14,7 +14,7 @@ define void @v_sf(float %p) #0 {
 entry:
   %p.addr = alloca float, align 4
   store float %p, float* %p.addr, align 4
-  %0 = load float* %p.addr, align 4
+  %0 = load float, float* %p.addr, align 4
   store float %0, float* @x, align 4
   ret void
 }
@@ -33,7 +33,7 @@ define void @v_df(double %p) #0 {
 entry:
   %p.addr = alloca double, align 8
   store double %p, double* %p.addr, align 8
-  %0 = load double* %p.addr, align 8
+  %0 = load double, double* %p.addr, align 8
   store double %0, double* @xd, align 8
   ret void
 }
@@ -54,9 +54,9 @@ entry:
   %p2.addr = alloca float, align 4
   store float %p1, float* %p1.addr, align 4
   store float %p2, float* %p2.addr, align 4
-  %0 = load float* %p1.addr, align 4
+  %0 = load float, float* %p1.addr, align 4
   store float %0, float* @x, align 4
-  %1 = load float* %p2.addr, align 4
+  %1 = load float, float* %p2.addr, align 4
   store float %1, float* @y, align 4
   ret void
 }
@@ -77,9 +77,9 @@ entry:
   %p2.addr = alloca double, align 8
   store float %p1, float* %p1.addr, align 4
   store double %p2, double* %p2.addr, align 8
-  %0 = load float* %p1.addr, align 4
+  %0 = load float, float* %p1.addr, align 4
   store float %0, float* @x, align 4
-  %1 = load double* %p2.addr, align 8
+  %1 = load double, double* %p2.addr, align 8
   store double %1, double* @yd, align 8
   ret void
 }
@@ -101,9 +101,9 @@ entry:
   %p2.addr = alloca float, align 4
   store double %p1, double* %p1.addr, align 8
   store float %p2, float* %p2.addr, align 4
-  %0 = load double* %p1.addr, align 8
+  %0 = load double, double* %p1.addr, align 8
   store double %0, double* @xd, align 8
-  %1 = load float* %p2.addr, align 4
+  %1 = load float, float* %p2.addr, align 4
   store float %1, float* @y, align 4
   ret void
 }
@@ -125,9 +125,9 @@ entry:
   %p2.addr = alloca double, align 8
   store double %p1, double* %p1.addr, align 8
   store double %p2, double* %p2.addr, align 8
-  %0 = load double* %p1.addr, align 8
+  %0 = load double, double* %p1.addr, align 8
   store double %0, double* @xd, align 8
-  %1 = load double* %p2.addr, align 8
+  %1 = load double, double* %p2.addr, align 8
   store double %1, double* @yd, align 8
   ret void
 }
@@ -146,7 +146,7 @@ entry:
 ; Function Attrs: nounwind
 define float @sf_v() #0 {
 entry:
-  %0 = load float* @ret_sf, align 4
+  %0 = load float, float* @ret_sf, align 4
   ret float %0
 }
 
@@ -155,9 +155,9 @@ define float @sf_sf(float %p) #0 {
 entry:
   %p.addr = alloca float, align 4
   store float %p, float* %p.addr, align 4
-  %0 = load float* %p.addr, align 4
+  %0 = load float, float* %p.addr, align 4
   store float %0, float* @x, align 4
-  %1 = load float* @ret_sf, align 4
+  %1 = load float, float* @ret_sf, align 4
   ret float %1
 }
 
@@ -176,9 +176,9 @@ define float @sf_df(double %p) #0 {
 entry:
   %p.addr = alloca double, align 8
   store double %p, double* %p.addr, align 8
-  %0 = load double* %p.addr, align 8
+  %0 = load double, double* %p.addr, align 8
   store double %0, double* @xd, align 8
-  %1 = load float* @ret_sf, align 4
+  %1 = load float, float* @ret_sf, align 4
   ret float %1
 }
 
@@ -198,11 +198,11 @@ entry:
   %p2.addr = alloca float, align 4
   store float %p1, float* %p1.addr, align 4
   store float %p2, float* %p2.addr, align 4
-  %0 = load float* %p1.addr, align 4
+  %0 = load float, float* %p1.addr, align 4
   store float %0, float* @x, align 4
-  %1 = load float* %p2.addr, align 4
+  %1 = load float, float* %p2.addr, align 4
   store float %1, float* @y, align 4
-  %2 = load float* @ret_sf, align 4
+  %2 = load float, float* @ret_sf, align 4
   ret float %2
 }
 
@@ -222,11 +222,11 @@ entry:
   %p2.addr = alloca double, align 8
   store float %p1, float* %p1.addr, align 4
   store double %p2, double* %p2.addr, align 8
-  %0 = load float* %p1.addr, align 4
+  %0 = load float, float* %p1.addr, align 4
   store float %0, float* @x, align 4
-  %1 = load double* %p2.addr, align 8
+  %1 = load double, double* %p2.addr, align 8
   store double %1, double* @yd, align 8
-  %2 = load float* @ret_sf, align 4
+  %2 = load float, float* @ret_sf, align 4
   ret float %2
 }
 
@@ -247,11 +247,11 @@ entry:
   %p2.addr = alloca float, align 4
   store double %p1, double* %p1.addr, align 8
   store float %p2, float* %p2.addr, align 4
-  %0 = load double* %p1.addr, align 8
+  %0 = load double, double* %p1.addr, align 8
   store double %0, double* @xd, align 8
-  %1 = load float* %p2.addr, align 4
+  %1 = load float, float* %p2.addr, align 4
   store float %1, float* @y, align 4
-  %2 = load float* @ret_sf, align 4
+  %2 = load float, float* @ret_sf, align 4
   ret float %2
 }
 
@@ -272,11 +272,11 @@ entry:
   %p2.addr = alloca double, align 8
   store double %p1, double* %p1.addr, align 8
   store double %p2, double* %p2.addr, align 8
-  %0 = load double* %p1.addr, align 8
+  %0 = load double, double* %p1.addr, align 8
   store double %0, double* @xd, align 8
-  %1 = load double* %p2.addr, align 8
+  %1 = load double, double* %p2.addr, align 8
   store double %1, double* @yd, align 8
-  %2 = load float* @ret_sf, align 4
+  %2 = load float, float* @ret_sf, align 4
   ret float %2
 }
 
diff --git a/test/CodeGen/Mips/hf1_body.ll b/test/CodeGen/Mips/hf1_body.ll
index 5acfe86373d9..71a1b960c5b3 100644
--- a/test/CodeGen/Mips/hf1_body.ll
+++ b/test/CodeGen/Mips/hf1_body.ll
@@ -7,7 +7,7 @@ define void @v_sf(float %p) #0 {
 entry:
   %p.addr = alloca float, align 4
   store float %p, float* %p.addr, align 4
-  %0 = load float* %p.addr, align 4
+  %0 = load float, float* %p.addr, align 4
   store float %0, float* @x, align 4
   ret void
 }
diff --git a/test/CodeGen/Mips/hfptrcall.ll b/test/CodeGen/Mips/hfptrcall.ll
index 683952d0e4ec..c9f1fe973796 100644
--- a/test/CodeGen/Mips/hfptrcall.ll
+++ b/test/CodeGen/Mips/hfptrcall.ll
@@ -34,11 +34,11 @@ entry:
 define { float, float } @scv() #0 {
 entry:
   %retval = alloca { float, float }, align 4
-  %real = getelementptr inbounds { float, float }* %retval, i32 0, i32 0
-  %imag = getelementptr inbounds { float, float }* %retval, i32 0, i32 1
+  %real = getelementptr inbounds { float, float }, { float, float }* %retval, i32 0, i32 0
+  %imag = getelementptr inbounds { float, float }, { float, float }* %retval, i32 0, i32 1
   store float 5.000000e+00, float* %real
   store float 9.900000e+01, float* %imag
-  %0 = load { float, float }* %retval
+  %0 = load { float, float }, { float, float }* %retval
   ret { float, float } %0
 }
 
@@ -50,11 +50,11 @@ entry:
 define { double, double } @dcv() #0 {
 entry:
   %retval = alloca { double, double }, align 8
-  %real = getelementptr inbounds { double, double }* %retval, i32 0, i32 0
-  %imag = getelementptr inbounds { double, double }* %retval, i32 0, i32 1
+  %real = getelementptr inbounds { double, double }, { double, double }* %retval, i32 0, i32 0
+  %imag = getelementptr inbounds { double, double }, { double, double }* %retval, i32 0, i32 1
   store double 0x416BC8B0A0000000, double* %real
   store double 0x41CDCCB763800000, double* %imag
-  %0 = load { double, double }* %retval
+  %0 = load { double, double }, { double, double }* %retval
   ret { double, double } %0
 }
 
@@ -65,43 +65,43 @@ entry:
 ; Function Attrs: nounwind
 define i32 @main() #0 {
 entry:
-  %0 = load float ()** @ptrsv, align 4
+  %0 = load float ()*, float ()** @ptrsv, align 4
   %call = call float %0()
   store float %call, float* @x, align 4
-  %1 = load float* @x, align 4
+  %1 = load float, float* @x, align 4
   %conv = fpext float %1 to double
-  %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), double %conv)
-  %2 = load double ()** @ptrdv, align 4
+  %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), double %conv)
+  %2 = load double ()*, double ()** @ptrdv, align 4
   %call2 = call double %2()
   store double %call2, double* @xd, align 8
-  %3 = load double* @xd, align 8
-  %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), double %3)
-  %4 = load { float, float } ()** @ptrscv, align 4
+  %3 = load double, double* @xd, align 8
+  %call3 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), double %3)
+  %4 = load { float, float } ()*, { float, float } ()** @ptrscv, align 4
   %call4 = call { float, float } %4()
   %5 = extractvalue { float, float } %call4, 0
   %6 = extractvalue { float, float } %call4, 1
-  store float %5, float* getelementptr inbounds ({ float, float }* @xy, i32 0, i32 0)
-  store float %6, float* getelementptr inbounds ({ float, float }* @xy, i32 0, i32 1)
-  %xy.real = load float* getelementptr inbounds ({ float, float }* @xy, i32 0, i32 0)
-  %xy.imag = load float* getelementptr inbounds ({ float, float }* @xy, i32 0, i32 1)
+  store float %5, float* getelementptr inbounds ({ float, float }, { float, float }* @xy, i32 0, i32 0)
+  store float %6, float* getelementptr inbounds ({ float, float }, { float, float }* @xy, i32 0, i32 1)
+  %xy.real = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @xy, i32 0, i32 0)
+  %xy.imag = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @xy, i32 0, i32 1)
   %conv5 = fpext float %xy.real to double
   %conv6 = fpext float %xy.imag to double
-  %xy.real7 = load float* getelementptr inbounds ({ float, float }* @xy, i32 0, i32 0)
-  %xy.imag8 = load float* getelementptr inbounds ({ float, float }* @xy, i32 0, i32 1)
+  %xy.real7 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @xy, i32 0, i32 0)
+  %xy.imag8 = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @xy, i32 0, i32 1)
   %conv9 = fpext float %xy.real7 to double
   %conv10 = fpext float %xy.imag8 to double
-  %call11 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str1, i32 0, i32 0), double %conv5, double %conv10)
-  %7 = load { double, double } ()** @ptrdcv, align 4
+  %call11 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str1, i32 0, i32 0), double %conv5, double %conv10)
+  %7 = load { double, double } ()*, { double, double } ()** @ptrdcv, align 4
   %call12 = call { double, double } %7()
   %8 = extractvalue { double, double } %call12, 0
   %9 = extractvalue { double, double } %call12, 1
-  store double %8, double* getelementptr inbounds ({ double, double }* @xyd, i32 0, i32 0)
-  store double %9, double* getelementptr inbounds ({ double, double }* @xyd, i32 0, i32 1)
-  %xyd.real = load double* getelementptr inbounds ({ double, double }* @xyd, i32 0, i32 0)
-  %xyd.imag = load double* getelementptr inbounds ({ double, double }* @xyd, i32 0, i32 1)
-  %xyd.real13 = load double* getelementptr inbounds ({ double, double }* @xyd, i32 0, i32 0)
-  %xyd.imag14 = load double* getelementptr inbounds ({ double, double }* @xyd, i32 0, i32 1)
-  %call15 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str1, i32 0, i32 0), double %xyd.real, double %xyd.imag14)
+  store double %8, double* getelementptr inbounds ({ double, double }, { double, double }* @xyd, i32 0, i32 0)
+  store double %9, double* getelementptr inbounds ({ double, double }, { double, double }* @xyd, i32 0, i32 1)
+  %xyd.real = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @xyd, i32 0, i32 0)
+  %xyd.imag = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @xyd, i32 0, i32 1)
+  %xyd.real13 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @xyd, i32 0, i32 0)
+  %xyd.imag14 = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @xyd, i32 0, i32 1)
+  %call15 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str1, i32 0, i32 0), double %xyd.real, double %xyd.imag14)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/i32k.ll b/test/CodeGen/Mips/i32k.ll
index 73f1302beec0..ba9cf7342308 100644
--- a/test/CodeGen/Mips/i32k.ll
+++ b/test/CodeGen/Mips/i32k.ll
@@ -4,14 +4,14 @@
 
 define i32 @main() nounwind {
 entry:
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 1075344593) nounwind
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 1075344593) nounwind
 ; 16:	lw	${{[0-9]+}}, 1f
 ; 16:	b	2f
 ; 16:	.align	2
 ; 16: 1: 	.word	1075344593
 ; 16: 2:
 
-  %call1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 -1075344593) nounwind
+  %call1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 -1075344593) nounwind
 
 ; 16:	lw	${{[0-9]+}}, 1f
 ; 16:	b	2f
diff --git a/test/CodeGen/Mips/inlineasm-assembler-directives.ll b/test/CodeGen/Mips/inlineasm-assembler-directives.ll
index e4a6d1e26c69..88ceed4114c2 100644
--- a/test/CodeGen/Mips/inlineasm-assembler-directives.ll
+++ b/test/CodeGen/Mips/inlineasm-assembler-directives.ll
@@ -16,7 +16,7 @@ entry:
   %a = alloca i32, align 4
   %b = alloca i32, align 4
   store i32 20, i32* %a, align 4
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %1 = call i32 asm sideeffect "addi $$9, $1, 8\0A\09subi $0, $$9, 6", "=r,r,~{$1}"(i32 %0)
   store i32 %1, i32* %b, align 4
   ret void
diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll
index a7ba762b1064..acce63203812 100644
--- a/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll
+++ b/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll
@@ -3,7 +3,7 @@
 ; The target is 64 bit.
 ;
 ;
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s
 
 
 define i32 @main() nounwind {
diff --git a/test/CodeGen/Mips/inlineasm-operand-code.ll b/test/CodeGen/Mips/inlineasm-operand-code.ll
index 3d9dec76fb37..b9415ee90cdb 100644
--- a/test/CodeGen/Mips/inlineasm-operand-code.ll
+++ b/test/CodeGen/Mips/inlineasm-operand-code.ll
@@ -125,7 +125,7 @@ entry:
 ;CHECK_BIG_32:       #APP
 ;CHECK_BIG_32:       or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
 ;CHECK_BIG_32:       #NO_APP
-  %bosco = load i64* getelementptr inbounds (%union.u_tag* @uval, i32 0, i32 0), align 8
+  %bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
   %trunc1 = trunc i64 %bosco to i32
   tail call i32 asm sideeffect "or $0,${1:D},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
   ret i32 0
@@ -149,7 +149,7 @@ entry:
 ;CHECK_BIG_32:       #APP
 ;CHECK_BIG_32:       or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
 ;CHECK_BIG_32:       #NO_APP
-  %bosco = load i64* getelementptr inbounds (%union.u_tag* @uval, i32 0, i32 0), align 8
+  %bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
   %trunc1 = trunc i64 %bosco to i32
   tail call i32 asm sideeffect "or $0,${1:L},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
   ret i32 0
@@ -173,7 +173,7 @@ entry:
 ;CHECK_BIG_32:       #APP
 ;CHECK_BIG_32:       or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
 ;CHECK_BIG_32:       #NO_APP
-  %bosco = load i64* getelementptr inbounds (%union.u_tag* @uval, i32 0, i32 0), align 8
+  %bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
   %trunc1 = trunc i64 %bosco to i32
   tail call i32 asm sideeffect "or $0,${1:M},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
   ret i32 0
diff --git a/test/CodeGen/Mips/inlineasm64.ll b/test/CodeGen/Mips/inlineasm64.ll
index dbce3c394e96..82abdf82a3ed 100644
--- a/test/CodeGen/Mips/inlineasm64.ll
+++ b/test/CodeGen/Mips/inlineasm64.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s
 
 @gl2 = external global i64
 @gl1 = external global i64
@@ -8,8 +8,8 @@ define void @foo1() nounwind {
 entry:
 ; CHECK: foo1
 ; CHECK: daddu
-  %0 = load i64* @gl1, align 8
-  %1 = load i64* @gl0, align 8
+  %0 = load i64, i64* @gl1, align 8
+  %1 = load i64, i64* @gl0, align 8
   %2 = tail call i64 asm "daddu $0, $1, $2", "=r,r,r"(i64 %0, i64 %1) nounwind
   store i64 %2, i64* @gl2, align 8
   ret void
diff --git a/test/CodeGen/Mips/inlineasm_constraint.ll b/test/CodeGen/Mips/inlineasm_constraint.ll
index 76b73dc276ae..868433e0941f 100644
--- a/test/CodeGen/Mips/inlineasm_constraint.ll
+++ b/test/CodeGen/Mips/inlineasm_constraint.ll
@@ -51,14 +51,5 @@ entry:
 ; CHECK: #NO_APP	
   tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,P"(i32 7, i32 65535) nounwind
 
-; Now R Which takes the address of c
-  %c = alloca i32, align 4
-  store i32 -4469539, i32* %c, align 4
-  %8 = call i32 asm sideeffect "lw $0, 1 + $1\0A\09lw $0, 2 + $1\0A\09", "=r,*R"(i32* %c) #1
-; CHECK: #APP
-; CHECK: lw ${{[0-9]+}}, 1 + 0(${{[0-9]+}})
-; CHECK: lw ${{[0-9]+}}, 2 + 0(${{[0-9]+}})
-; CHECK: #NO_APP	
-
   ret i32 0
 }
diff --git a/test/CodeGen/Mips/inlineasm_constraint_R.ll b/test/CodeGen/Mips/inlineasm_constraint_R.ll
new file mode 100644
index 000000000000..c4105ae6b22c
--- /dev/null
+++ b/test/CodeGen/Mips/inlineasm_constraint_R.ll
@@ -0,0 +1,60 @@
+; RUN: llc -march=mipsel < %s | FileCheck %s
+
+@data = global [8193 x i32] zeroinitializer
+
+define void @R(i32 *%p) nounwind {
+entry:
+  ; CHECK-LABEL: R:
+
+  call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 0))
+
+  ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
+  ; CHECK: #APP
+  ; CHECK: lw $1, 0($[[BASEPTR]])
+  ; CHECK: #NO_APP
+
+  ret void
+}
+
+define void @R_offset_4(i32 *%p) nounwind {
+entry:
+  ; CHECK-LABEL: R_offset_4:
+
+  call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 1))
+
+  ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
+  ; CHECK: #APP
+  ; CHECK: lw $1, 4($[[BASEPTR]])
+  ; CHECK: #NO_APP
+
+  ret void
+}
+
+define void @R_offset_254(i32 *%p) nounwind {
+entry:
+  ; CHECK-LABEL: R_offset_254:
+
+  call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 63))
+
+  ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+  ; CHECK: #APP
+  ; CHECK: lw $1, 252($[[BASEPTR]])
+  ; CHECK: #NO_APP
+
+  ret void
+}
+
+define void @R_offset_256(i32 *%p) nounwind {
+entry:
+  ; CHECK-LABEL: R_offset_256:
+
+  call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 64))
+
+  ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+  ; CHECK: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
+  ; CHECK: #APP
+  ; CHECK: lw $1, 0($[[BASEPTR2]])
+  ; CHECK: #NO_APP
+
+  ret void
+}
diff --git a/test/CodeGen/Mips/inlineasm_constraint_ZC.ll b/test/CodeGen/Mips/inlineasm_constraint_ZC.ll
new file mode 100644
index 000000000000..c1746a67564f
--- /dev/null
+++ b/test/CodeGen/Mips/inlineasm_constraint_ZC.ll
@@ -0,0 +1,167 @@
+; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=09BIT
+; RUN: llc -march=mipsel -mattr=+micromips < %s | FileCheck %s -check-prefix=ALL -check-prefix=12BIT
+; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=ALL -check-prefix=16BIT
+
+@data = global [8193 x i32] zeroinitializer
+
+define void @ZC(i32 *%p) nounwind {
+entry:
+  ; ALL-LABEL: ZC:
+
+  call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 0))
+
+  ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
+  ; ALL: #APP
+  ; ALL: lw $1, 0($[[BASEPTR]])
+  ; ALL: #NO_APP
+
+  ret void
+}
+
+define void @ZC_offset_n4(i32 *%p) nounwind {
+entry:
+  ; ALL-LABEL: ZC_offset_n4:
+
+  call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 -1))
+
+  ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
+  ; ALL: #APP
+  ; ALL: lw $1, -4($[[BASEPTR]])
+  ; ALL: #NO_APP
+
+  ret void
+}
+
+define void @ZC_offset_4(i32 *%p) nounwind {
+entry:
+  ; ALL-LABEL: ZC_offset_4:
+
+  call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 1))
+
+  ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
+  ; ALL: #APP
+  ; ALL: lw $1, 4($[[BASEPTR]])
+  ; ALL: #NO_APP
+
+  ret void
+}
+
+define void @ZC_offset_252(i32 *%p) nounwind {
+entry:
+  ; ALL-LABEL: ZC_offset_252:
+
+  call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 63))
+
+  ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
+  ; ALL: #APP
+  ; ALL: lw $1, 252($[[BASEPTR]])
+  ; ALL: #NO_APP
+
+  ret void
+}
+
+define void @ZC_offset_256(i32 *%p) nounwind {
+entry:
+  ; ALL-LABEL: ZC_offset_256:
+
+  call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 64))
+
+  ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
+
+  ; 09BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
+
+  ; ALL: #APP
+
+  ; 09BIT: lw $1, 0($[[BASEPTR2]])
+  ; 12BIT: lw $1, 256($[[BASEPTR]])
+  ; 16BIT: lw $1, 256($[[BASEPTR]])
+
+  ; ALL: #NO_APP
+
+  ret void
+}
+
+define void @ZC_offset_2044(i32 *%p) nounwind {
+entry:
+  ; ALL-LABEL: ZC_offset_2044:
+
+  call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 511))
+
+  ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
+
+  ; 09BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 2044
+
+  ; ALL: #APP
+
+  ; 09BIT: lw $1, 0($[[BASEPTR2]])
+  ; 12BIT: lw $1, 2044($[[BASEPTR]])
+  ; 16BIT: lw $1, 2044($[[BASEPTR]])
+
+  ; ALL: #NO_APP
+
+  ret void
+}
+
+define void @ZC_offset_2048(i32 *%p) nounwind {
+entry:
+  ; ALL-LABEL: ZC_offset_2048:
+
+  call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 512))
+
+  ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
+
+  ; 09BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 2048
+  ; 12BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 2048
+
+  ; ALL: #APP
+
+  ; 09BIT: lw $1, 0($[[BASEPTR2]])
+  ; 12BIT: lw $1, 0($[[BASEPTR2]])
+  ; 16BIT: lw $1, 2048($[[BASEPTR]])
+
+  ; ALL: #NO_APP
+
+  ret void
+}
+
+define void @ZC_offset_32764(i32 *%p) nounwind {
+entry:
+  ; ALL-LABEL: ZC_offset_32764:
+
+  call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8191))
+
+  ; ALL-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+
+  ; 09BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 32764
+  ; 12BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 32764
+
+  ; ALL: #APP
+
+  ; 09BIT: lw $1, 0($[[BASEPTR2]])
+  ; 12BIT: lw $1, 0($[[BASEPTR2]])
+  ; 16BIT: lw $1, 32764($[[BASEPTR]])
+
+  ; ALL: #NO_APP
+
+  ret void
+}
+
+define void @ZC_offset_32768(i32 *%p) nounwind {
+entry:
+  ; ALL-LABEL: ZC_offset_32768:
+
+  call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8192))
+
+  ; ALL-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+  ; ALL-DAG: ori $[[T0:[0-9]+]], $zero, 32768
+
+  ; 09BIT: addu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
+  ; 12BIT: addu16 $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
+  ; 16BIT: addu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
+
+  ; ALL: #APP
+  ; ALL: lw $1, 0($[[BASEPTR2]])
+  ; ALL: #NO_APP
+
+  ret void
+}
diff --git a/test/CodeGen/Mips/inlineasm_constraint_m.ll b/test/CodeGen/Mips/inlineasm_constraint_m.ll
new file mode 100644
index 000000000000..00053ad3c105
--- /dev/null
+++ b/test/CodeGen/Mips/inlineasm_constraint_m.ll
@@ -0,0 +1,61 @@
+; RUN: llc -march=mipsel < %s | FileCheck %s
+
+@data = global [8193 x i32] zeroinitializer
+
+define void @m(i32 *%p) nounwind {
+entry:
+  ; CHECK-LABEL: m:
+
+  call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 0))
+
+  ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
+  ; CHECK: #APP
+  ; CHECK: lw $1, 0($[[BASEPTR]])
+  ; CHECK: #NO_APP
+
+  ret void
+}
+
+define void @m_offset_4(i32 *%p) nounwind {
+entry:
+  ; CHECK-LABEL: m_offset_4:
+
+  call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 1))
+
+  ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
+  ; CHECK: #APP
+  ; CHECK: lw $1, 4($[[BASEPTR]])
+  ; CHECK: #NO_APP
+
+  ret void
+}
+
+define void @m_offset_32764(i32 *%p) nounwind {
+entry:
+  ; CHECK-LABEL: m_offset_32764:
+
+  call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8191))
+
+  ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+  ; CHECK: #APP
+  ; CHECK: lw $1, 32764($[[BASEPTR]])
+  ; CHECK: #NO_APP
+
+  ret void
+}
+
+define void @m_offset_32768(i32 *%p) nounwind {
+entry:
+  ; CHECK-LABEL: m_offset_32768:
+
+  call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8192))
+
+  ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+  ; CHECK-DAG: ori $[[T0:[0-9]+]], $zero, 32768
+  ; CHECK: addu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
+  ; CHECK: #APP
+  ; CHECK: lw $1, 0($[[BASEPTR2]])
+  ; CHECK: #NO_APP
+
+  ret void
+}
diff --git a/test/CodeGen/Mips/inlineasmmemop.ll b/test/CodeGen/Mips/inlineasmmemop.ll
index 5518520c5491..9e9b6cd089ea 100644
--- a/test/CodeGen/Mips/inlineasmmemop.ll
+++ b/test/CodeGen/Mips/inlineasmmemop.ll
@@ -6,14 +6,13 @@
 define i32 @f1(i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: f1:
-; CHECK: addiu $[[T0:[0-9]+]], $sp
 ; CHECK: #APP
-; CHECK: sw $4, 0($[[T0]])
+; CHECK: sw $4, [[OFFSET:[0-9]+]]($sp)
 ; CHECK: #NO_APP
+; CHECK: lw  $[[T1:[0-9]+]], %got(g1)
 ; CHECK: #APP
-; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]])
+; CHECK: lw $[[T3:[0-9]+]], [[OFFSET]]($sp)
 ; CHECK: #NO_APP
-; CHECK: lw  $[[T1:[0-9]+]], %got(g1)
 ; CHECK: sw  $[[T3]], 0($[[T1]])
 
   %l1 = alloca i32, align 4
@@ -27,13 +26,13 @@ entry:
 ; "D": Second word of a double word. This works for any memory element
 ; double or single.
 ; CHECK: #APP
-; CHECK: lw ${{[0-9]+}},4(${{[0-9]+}});
+; CHECK: lw ${{[0-9]+}}, 16(${{[0-9]+}});
 ; CHECK: #NO_APP
 
 ; No "D": First word of a double word. This works for any memory element
 ; double or single.
 ; CHECK: #APP
-; CHECK: lw ${{[0-9]+}},0(${{[0-9]+}});
+; CHECK: lw ${{[0-9]+}}, 12(${{[0-9]+}});
 ; CHECK: #NO_APP
 
 @b = common global [20 x i32] zeroinitializer, align 4
@@ -41,8 +40,8 @@ entry:
 define void @main() {
 entry:
 ; Second word:
-  tail call void asm sideeffect "    lw    $0,${1:D};", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32]* @b, i32 0, i32 3))
+  tail call void asm sideeffect "    lw    $0, ${1:D};", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
 ; First word. Notice, no 'D':
-  tail call void asm sideeffect "    lw    $0,${1};", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32]* @b, i32 0, i32 3))
+  tail call void asm sideeffect "    lw    $0, ${1};", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
   ret void
 }
diff --git a/test/CodeGen/Mips/insn-zero-size-bb.ll b/test/CodeGen/Mips/insn-zero-size-bb.ll
new file mode 100644
index 000000000000..9739c6f17fab
--- /dev/null
+++ b/test/CodeGen/Mips/insn-zero-size-bb.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s
+; RUN: llc < %s -march=mips -mcpu=mips16 | FileCheck %s
+
+; Verify that we emit the .insn directive for zero-sized (empty) basic blocks.
+; This only really matters for microMIPS and MIPS16.
+
+declare i32 @foo(...)
+declare void @bar()
+
+define void @main() {
+entry:
+  invoke void @bar() #0
+          to label %unreachable unwind label %return
+
+unreachable:
+; CHECK:          ${{.*}}: # %unreachable
+; CHECK-NEXT:         .insn
+  unreachable
+
+return:
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @foo to i8*)
+          catch i8* null
+  ret void
+}
+
+attributes #0 = { noreturn }
diff --git a/test/CodeGen/Mips/internalfunc.ll b/test/CodeGen/Mips/internalfunc.ll
index 863375ad4d4a..2b4a0397f45f 100644
--- a/test/CodeGen/Mips/internalfunc.ll
+++ b/test/CodeGen/Mips/internalfunc.ll
@@ -20,8 +20,8 @@ entry:
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry
-  %tmp1 = load void (...)** @caller.sf1, align 4
-  tail call void (...)* %tmp1() nounwind
+  %tmp1 = load void (...)*, void (...)** @caller.sf1, align 4
+  tail call void (...) %tmp1() nounwind
   br label %if.end
 
 if.end:                                           ; preds = %entry, %if.then
@@ -30,7 +30,7 @@ if.end:                                           ; preds = %entry, %if.then
 ; CHECK: lw  $[[R3:[0-9]+]], %got(caller.sf1)
 ; CHECK: sw  ${{[0-9]+}}, %lo(caller.sf1)($[[R3]])
   %tobool3 = icmp ne i32 %a0, 0
-  %tmp4 = load void (...)** @gf1, align 4
+  %tmp4 = load void (...)*, void (...)** @gf1, align 4
   %cond = select i1 %tobool3, void (...)* %tmp4, void (...)* bitcast (void ()* @sf2 to void (...)*)
   store void (...)* %cond, void (...)** @caller.sf1, align 4
   ret void
@@ -38,7 +38,7 @@ if.end:                                           ; preds = %entry, %if.then
 
 define internal void @sf2() nounwind {
 entry:
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0)) nounwind
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0)) nounwind
   ret void
 }
 
@@ -46,7 +46,7 @@ declare i32 @printf(i8* nocapture, ...) nounwind
 
 define internal fastcc void @f2() nounwind noinline {
 entry:
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0)) nounwind
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0)) nounwind
   ret void
 }
 
diff --git a/test/CodeGen/Mips/jtstat.ll b/test/CodeGen/Mips/jtstat.ll
index 01afc080c2ed..35f71cf2dc85 100644
--- a/test/CodeGen/Mips/jtstat.ll
+++ b/test/CodeGen/Mips/jtstat.ll
@@ -8,7 +8,7 @@ define void @test(i32 %i) nounwind {
 entry:
   %i.addr = alloca i32, align 4
   store i32 %i, i32* %i.addr, align 4
-  %0 = load i32* %i.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
   switch i32 %0, label %sw.epilog [
     i32 115, label %sw.bb
     i32 105, label %sw.bb1
diff --git a/test/CodeGen/Mips/l3mc.ll b/test/CodeGen/Mips/l3mc.ll
index 3bfb389ba05d..c1bff11595c9 100644
--- a/test/CodeGen/Mips/l3mc.ll
+++ b/test/CodeGen/Mips/l3mc.ll
@@ -1,22 +1,22 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck  %s -check-prefix=__call_stub_fp___fixunsdfsi 
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck  %s -check-prefix=__call_stub_fp___fixunsdfsi 
 
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___floatdidf 
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___floatdidf 
 
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___floatdisf 
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___floatdisf 
 
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___floatundidf
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___floatundidf
 
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___fixsfdi 
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___fixsfdi 
 
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunsdfdi 
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunsdfdi 
 
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___fixdfdi
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___fixdfdi
 
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunssfsi 
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunssfsi 
 
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunssfdi 
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunssfdi 
 
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___floatundisf 
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static  < %s | FileCheck %s -check-prefix=__call_stub_fp___floatundisf 
 
 @ll1 = global i64 0, align 8
 @ll2 = global i64 0, align 8
@@ -42,28 +42,28 @@
 ; Function Attrs: nounwind
 define void @_Z3foov() #0 {
 entry:
-  %0 = load double* @d1, align 8
+  %0 = load double, double* @d1, align 8
   %conv = fptosi double %0 to i64
   store i64 %conv, i64* @ll1, align 8
-  %1 = load double* @d2, align 8
+  %1 = load double, double* @d2, align 8
   %conv1 = fptoui double %1 to i64
   store i64 %conv1, i64* @ull1, align 8
-  %2 = load float* @f1, align 4
+  %2 = load float, float* @f1, align 4
   %conv2 = fptosi float %2 to i64
   store i64 %conv2, i64* @ll2, align 8
-  %3 = load float* @f2, align 4
+  %3 = load float, float* @f2, align 4
   %conv3 = fptoui float %3 to i64
   store i64 %conv3, i64* @ull2, align 8
-  %4 = load double* @d3, align 8
+  %4 = load double, double* @d3, align 8
   %conv4 = fptosi double %4 to i32
   store i32 %conv4, i32* @l1, align 4
-  %5 = load double* @d4, align 8
+  %5 = load double, double* @d4, align 8
   %conv5 = fptoui double %5 to i32
   store i32 %conv5, i32* @ul1, align 4
-  %6 = load float* @f3, align 4
+  %6 = load float, float* @f3, align 4
   %conv6 = fptosi float %6 to i32
   store i32 %conv6, i32* @l2, align 4
-  %7 = load float* @f4, align 4
+  %7 = load float, float* @f4, align 4
   %conv7 = fptoui float %7 to i32
   store i32 %conv7, i32* @ul2, align 4
   ret void
@@ -72,28 +72,28 @@ entry:
 ; Function Attrs: nounwind
 define void @_Z3goov() #0 {
 entry:
-  %0 = load i64* @ll1, align 8
+  %0 = load i64, i64* @ll1, align 8
   %conv = sitofp i64 %0 to double
   store double %conv, double* @d1, align 8
-  %1 = load i64* @ull1, align 8
+  %1 = load i64, i64* @ull1, align 8
   %conv1 = uitofp i64 %1 to double
   store double %conv1, double* @d2, align 8
-  %2 = load i64* @ll2, align 8
+  %2 = load i64, i64* @ll2, align 8
   %conv2 = sitofp i64 %2 to float
   store float %conv2, float* @f1, align 4
-  %3 = load i64* @ull2, align 8
+  %3 = load i64, i64* @ull2, align 8
   %conv3 = uitofp i64 %3 to float
   store float %conv3, float* @f2, align 4
-  %4 = load i32* @l1, align 4
+  %4 = load i32, i32* @l1, align 4
   %conv4 = sitofp i32 %4 to double
   store double %conv4, double* @d3, align 8
-  %5 = load i32* @ul1, align 4
+  %5 = load i32, i32* @ul1, align 4
   %conv5 = uitofp i32 %5 to double
   store double %conv5, double* @d4, align 8
-  %6 = load i32* @l2, align 4
+  %6 = load i32, i32* @l2, align 4
   %conv6 = sitofp i32 %6 to float
   store float %conv6, float* @f3, align 4
-  %7 = load i32* @ul2, align 4
+  %7 = load i32, i32* @ul2, align 4
   %conv7 = uitofp i32 %7 to float
   store float %conv7, float* @f4, align 4
   ret void
diff --git a/test/CodeGen/Mips/largeimm1.ll b/test/CodeGen/Mips/largeimm1.ll
index 1c0f69c59011..06c4d6bd9603 100644
--- a/test/CodeGen/Mips/largeimm1.ll
+++ b/test/CodeGen/Mips/largeimm1.ll
@@ -5,7 +5,7 @@
 define void @f() nounwind {
 entry:
   %a1 = alloca [1073741824 x i8], align 1
-  %arrayidx = getelementptr inbounds [1073741824 x i8]* %a1, i32 0, i32 1048676
+  %arrayidx = getelementptr inbounds [1073741824 x i8], [1073741824 x i8]* %a1, i32 0, i32 1048676
   call void @f2(i8* %arrayidx) nounwind
   ret void
 }
diff --git a/test/CodeGen/Mips/largeimmprinting.ll b/test/CodeGen/Mips/largeimmprinting.ll
index 0e9c91fb46df..a53a953a7883 100644
--- a/test/CodeGen/Mips/largeimmprinting.ll
+++ b/test/CodeGen/Mips/largeimmprinting.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
-; RUN: llc -march=mips64el -mcpu=mips4 -mattr=n64 < %s | \
+; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 < %s | \
 ; RUN:     FileCheck %s -check-prefix=64
-; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | \
+; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 < %s | \
 ; RUN:     FileCheck %s -check-prefix=64
 
 %struct.S1 = type { [65536 x i8] }
@@ -27,8 +27,8 @@ entry:
 ; 64:  sd  $ra, 24($[[R1]])
 
   %agg.tmp = alloca %struct.S1, align 1
-  %tmp = getelementptr inbounds %struct.S1* %agg.tmp, i32 0, i32 0, i32 0
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp, i8* getelementptr inbounds (%struct.S1* @s1, i32 0, i32 0, i32 0), i32 65536, i32 1, i1 false)
+  %tmp = getelementptr inbounds %struct.S1, %struct.S1* %agg.tmp, i32 0, i32 0, i32 0
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp, i8* getelementptr inbounds (%struct.S1, %struct.S1* @s1, i32 0, i32 0, i32 0), i32 65536, i32 1, i1 false)
   call void @f2(%struct.S1* byval %agg.tmp) nounwind
   ret void
 }
diff --git a/test/CodeGen/Mips/lb1.ll b/test/CodeGen/Mips/lb1.ll
index aac2767a4e40..21648d7572a5 100644
--- a/test/CodeGen/Mips/lb1.ll
+++ b/test/CodeGen/Mips/lb1.ll
@@ -6,12 +6,12 @@
 define i32 @main() nounwind {
 entry:
   %i = alloca i32, align 4
-  %0 = load i8* @c, align 1
+  %0 = load i8, i8* @c, align 1
 ; 16:	lb	${{[0-9]+}}, 0(${{[0-9]+}})
   %conv = sext i8 %0 to i32
   store i32 %conv, i32* %i, align 4
-  %1 = load i32* %i, align 4
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %1)
+  %1 = load i32, i32* %i, align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %1)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/lbu1.ll b/test/CodeGen/Mips/lbu1.ll
index 63e0cca1684d..28ca27132467 100644
--- a/test/CodeGen/Mips/lbu1.ll
+++ b/test/CodeGen/Mips/lbu1.ll
@@ -6,13 +6,13 @@
 define i32 @main() nounwind {
 entry:
   %i = alloca i32, align 4
-  %0 = load i8* @c, align 1
+  %0 = load i8, i8* @c, align 1
   %conv = zext i8 %0 to i32
 ; 16:	lbu	${{[0-9]+}}, 0(${{[0-9]+}})
   store i32 %conv, i32* %i, align 4
-  %1 = load i8* @c, align 1
+  %1 = load i8, i8* @c, align 1
   %conv1 = zext i8 %1 to i32
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %conv1)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %conv1)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/lcb2.ll b/test/CodeGen/Mips/lcb2.ll
index 59b96e64e95e..a6f4968e6d23 100644
--- a/test/CodeGen/Mips/lcb2.ll
+++ b/test/CodeGen/Mips/lcb2.ll
@@ -1,6 +1,6 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands=true   < %s | FileCheck %s -check-prefix=lcb
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands=true   < %s | FileCheck %s -check-prefix=lcb
 
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands=true   < %s | FileCheck %s -check-prefix=lcbn
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands=true   < %s | FileCheck %s -check-prefix=lcbn
 
 @i = global i32 0, align 4
 @j = common global i32 0, align 4
@@ -9,7 +9,7 @@
 ; Function Attrs: nounwind optsize
 define i32 @bnez() #0 {
 entry:
-  %0 = load i32* @i, align 4, !tbaa !1
+  %0 = load i32, i32* @i, align 4, !tbaa !1
   %cmp = icmp eq i32 %0, 0
   br i1 %cmp, label %if.then, label %if.end
 
@@ -31,7 +31,7 @@ if.end:                                           ; preds = %if.then, %entry
 ; Function Attrs: nounwind optsize
 define i32 @beqz() #0 {
 entry:
-  %0 = load i32* @i, align 4, !tbaa !1
+  %0 = load i32, i32* @i, align 4, !tbaa !1
   %cmp = icmp eq i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
@@ -60,8 +60,8 @@ if.end:                                           ; preds = %if.else, %if.then
 ; Function Attrs: nounwind optsize
 define void @bteqz() #0 {
 entry:
-  %0 = load i32* @i, align 4, !tbaa !1
-  %1 = load i32* @j, align 4, !tbaa !1
+  %0 = load i32, i32* @i, align 4, !tbaa !1
+  %1 = load i32, i32* @j, align 4, !tbaa !1
   %cmp = icmp eq i32 %0, %1
   br i1 %cmp, label %if.then, label %if.else
 
@@ -90,15 +90,15 @@ if.end:                                           ; preds = %if.else, %if.then
 ; Function Attrs: nounwind optsize
 define void @btz() #0 {
 entry:
-  %0 = load i32* @i, align 4, !tbaa !1
-  %1 = load i32* @j, align 4, !tbaa !1
+  %0 = load i32, i32* @i, align 4, !tbaa !1
+  %1 = load i32, i32* @j, align 4, !tbaa !1
   %cmp1 = icmp sgt i32 %0, %1
   br i1 %cmp1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry, %if.then
   tail call void asm sideeffect ".space 60000", ""() #1, !srcloc !10
-  %2 = load i32* @i, align 4, !tbaa !1
-  %3 = load i32* @j, align 4, !tbaa !1
+  %2 = load i32, i32* @i, align 4, !tbaa !1
+  %3 = load i32, i32* @j, align 4, !tbaa !1
   %cmp = icmp sgt i32 %2, %3
   br i1 %cmp, label %if.then, label %if.end
 
diff --git a/test/CodeGen/Mips/lcb3c.ll b/test/CodeGen/Mips/lcb3c.ll
index eb8329145421..4c6f2c036a0b 100644
--- a/test/CodeGen/Mips/lcb3c.ll
+++ b/test/CodeGen/Mips/lcb3c.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static -O0    < %s | FileCheck %s -check-prefix=lcb
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -O0    < %s | FileCheck %s -check-prefix=lcb
 
 @i = global i32 0, align 4
 @j = common global i32 0, align 4
@@ -7,7 +7,7 @@
 ; Function Attrs: nounwind
 define i32 @s() #0 {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %cmp = icmp eq i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
@@ -30,7 +30,7 @@ if.end:                                           ; preds = %if.else, %if.then
 ; Function Attrs: nounwind
 define i32 @b() #0 {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %cmp = icmp eq i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
diff --git a/test/CodeGen/Mips/lcb4a.ll b/test/CodeGen/Mips/lcb4a.ll
index fbcadd2552f8..9e97b5bf1433 100644
--- a/test/CodeGen/Mips/lcb4a.ll
+++ b/test/CodeGen/Mips/lcb4a.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static     < %s | FileCheck %s -check-prefix=ci
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static     < %s | FileCheck %s -check-prefix=ci
 
 @i = global i32 0, align 4
 @j = common global i32 0, align 4
@@ -7,7 +7,7 @@
 ; Function Attrs: nounwind optsize
 define i32 @foo() #0 {
 entry:
-  %0 = load i32* @i, align 4, !tbaa !1
+  %0 = load i32, i32* @i, align 4, !tbaa !1
   %cmp = icmp eq i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
@@ -32,7 +32,7 @@ if.end:                                           ; preds = %if.else, %if.then
 ; Function Attrs: nounwind optsize
 define i32 @goo() #0 {
 entry:
-  %0 = load i32* @i, align 4, !tbaa !1
+  %0 = load i32, i32* @i, align 4, !tbaa !1
   %cmp = icmp eq i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
diff --git a/test/CodeGen/Mips/lcb5.ll b/test/CodeGen/Mips/lcb5.ll
index b2a8d1d33ef6..41878d5f8817 100644
--- a/test/CodeGen/Mips/lcb5.ll
+++ b/test/CodeGen/Mips/lcb5.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static     < %s | FileCheck %s -check-prefix=ci
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static     < %s | FileCheck %s -check-prefix=ci
 
 @i = global i32 0, align 4
 @j = common global i32 0, align 4
@@ -7,7 +7,7 @@
 ; Function Attrs: nounwind optsize
 define i32 @x0() #0 {
 entry:
-  %0 = load i32* @i, align 4, !tbaa !1
+  %0 = load i32, i32* @i, align 4, !tbaa !1
   %cmp = icmp eq i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
@@ -33,7 +33,7 @@ if.end:                                           ; preds = %if.else, %if.then
 ; Function Attrs: nounwind optsize
 define i32 @x1() #0 {
 entry:
-  %0 = load i32* @i, align 4, !tbaa !1
+  %0 = load i32, i32* @i, align 4, !tbaa !1
   %cmp = icmp eq i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
@@ -61,7 +61,7 @@ if.end:                                           ; preds = %if.else, %if.then
 ; Function Attrs: nounwind optsize
 define i32 @y0() #0 {
 entry:
-  %0 = load i32* @i, align 4, !tbaa !1
+  %0 = load i32, i32* @i, align 4, !tbaa !1
   %cmp = icmp eq i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
@@ -86,7 +86,7 @@ if.end:                                           ; preds = %if.else, %if.then
 ; Function Attrs: nounwind optsize
 define i32 @y1() #0 {
 entry:
-  %0 = load i32* @i, align 4, !tbaa !1
+  %0 = load i32, i32* @i, align 4, !tbaa !1
   %cmp = icmp eq i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
@@ -114,8 +114,8 @@ if.end:                                           ; preds = %if.else, %if.then
 ; Function Attrs: nounwind optsize
 define void @z0() #0 {
 entry:
-  %0 = load i32* @i, align 4, !tbaa !1
-  %1 = load i32* @j, align 4, !tbaa !1
+  %0 = load i32, i32* @i, align 4, !tbaa !1
+  %1 = load i32, i32* @j, align 4, !tbaa !1
   %cmp = icmp eq i32 %0, %1
   br i1 %cmp, label %if.then, label %if.else
 
@@ -140,8 +140,8 @@ if.end:                                           ; preds = %if.else, %if.then
 ; Function Attrs: nounwind optsize
 define void @z1() #0 {
 entry:
-  %0 = load i32* @i, align 4, !tbaa !1
-  %1 = load i32* @j, align 4, !tbaa !1
+  %0 = load i32, i32* @i, align 4, !tbaa !1
+  %1 = load i32, i32* @j, align 4, !tbaa !1
   %cmp = icmp eq i32 %0, %1
   br i1 %cmp, label %if.then, label %if.else
 
@@ -169,15 +169,15 @@ if.end:                                           ; preds = %if.else, %if.then
 ; Function Attrs: nounwind optsize
 define void @z3() #0 {
 entry:
-  %0 = load i32* @i, align 4, !tbaa !1
-  %1 = load i32* @j, align 4, !tbaa !1
+  %0 = load i32, i32* @i, align 4, !tbaa !1
+  %1 = load i32, i32* @j, align 4, !tbaa !1
   %cmp1 = icmp sgt i32 %0, %1
   br i1 %cmp1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry, %if.then
   tail call void asm sideeffect ".space 10000", ""() #1, !srcloc !17
-  %2 = load i32* @i, align 4, !tbaa !1
-  %3 = load i32* @j, align 4, !tbaa !1
+  %2 = load i32, i32* @i, align 4, !tbaa !1
+  %3 = load i32, i32* @j, align 4, !tbaa !1
   %cmp = icmp sgt i32 %2, %3
   br i1 %cmp, label %if.then, label %if.end
 
@@ -192,15 +192,15 @@ if.end:                                           ; preds = %if.then, %entry
 ; Function Attrs: nounwind optsize
 define void @z4() #0 {
 entry:
-  %0 = load i32* @i, align 4, !tbaa !1
-  %1 = load i32* @j, align 4, !tbaa !1
+  %0 = load i32, i32* @i, align 4, !tbaa !1
+  %1 = load i32, i32* @j, align 4, !tbaa !1
   %cmp1 = icmp sgt i32 %0, %1
   br i1 %cmp1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry, %if.then
   tail call void asm sideeffect ".space 10000000", ""() #1, !srcloc !18
-  %2 = load i32* @i, align 4, !tbaa !1
-  %3 = load i32* @j, align 4, !tbaa !1
+  %2 = load i32, i32* @i, align 4, !tbaa !1
+  %3 = load i32, i32* @j, align 4, !tbaa !1
   %cmp = icmp sgt i32 %2, %3
   br i1 %cmp, label %if.then, label %if.end
 
diff --git a/test/CodeGen/Mips/lh1.ll b/test/CodeGen/Mips/lh1.ll
index 1f95b0903466..31967e5a5379 100644
--- a/test/CodeGen/Mips/lh1.ll
+++ b/test/CodeGen/Mips/lh1.ll
@@ -6,12 +6,12 @@
 define i32 @main() nounwind {
 entry:
   %i = alloca i32, align 4
-  %0 = load i16* @s, align 2
+  %0 = load i16, i16* @s, align 2
   %conv = sext i16 %0 to i32
 ; 16:	lh	${{[0-9]+}}, 0(${{[0-9]+}})
   store i32 %conv, i32* %i, align 4
-  %1 = load i32* %i, align 4
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %1)
+  %1 = load i32, i32* %i, align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %1)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/lhu1.ll b/test/CodeGen/Mips/lhu1.ll
index 0cfcede669e0..413da46d4a31 100644
--- a/test/CodeGen/Mips/lhu1.ll
+++ b/test/CodeGen/Mips/lhu1.ll
@@ -7,12 +7,12 @@
 define i32 @main() nounwind {
 entry:
   %i = alloca i32, align 4
-  %0 = load i16* @s, align 2
+  %0 = load i16, i16* @s, align 2
   %conv = zext i16 %0 to i32
 ; 16:	lhu	${{[0-9]+}}, 0(${{[0-9]+}})
   store i32 %conv, i32* %i, align 4
-  %1 = load i32* %i, align 4
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %1)
+  %1 = load i32, i32* %i, align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %1)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/llcarry.ll b/test/CodeGen/Mips/llcarry.ll
index 7763daec3b32..f4120ecec175 100644
--- a/test/CodeGen/Mips/llcarry.ll
+++ b/test/CodeGen/Mips/llcarry.ll
@@ -9,8 +9,8 @@
 
 define void @test1() nounwind {
 entry:
-  %0 = load i64* @i, align 8
-  %1 = load i64* @j, align 8
+  %0 = load i64, i64* @i, align 8
+  %1 = load i64, i64* @j, align 8
   %add = add nsw i64 %1, %0
   store i64 %add, i64* @k, align 8
 ; 16:	addu	${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
@@ -23,8 +23,8 @@ entry:
 
 define void @test2() nounwind {
 entry:
-  %0 = load i64* @i, align 8
-  %1 = load i64* @j, align 8
+  %0 = load i64, i64* @i, align 8
+  %1 = load i64, i64* @j, align 8
   %sub = sub nsw i64 %0, %1
 ; 16:	subu	${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
 ; 16:	sltu	${{[0-9]+}}, ${{[0-9]+}}
@@ -37,7 +37,7 @@ entry:
 
 define void @test3() nounwind {
 entry:
-  %0 = load i64* @ii, align 8
+  %0 = load i64, i64* @ii, align 8
   %add = add nsw i64 %0, 15
 ; 16:	addiu	${{[0-9]+}}, 15
 ; 16:	sltu	${{[0-9]+}}, ${{[0-9]+}}
diff --git a/test/CodeGen/Mips/llvm-ir/add.ll b/test/CodeGen/Mips/llvm-ir/add.ll
index 83774eda634f..6cccc7df19f9 100644
--- a/test/CodeGen/Mips/llvm-ir/add.ll
+++ b/test/CodeGen/Mips/llvm-ir/add.ll
@@ -4,6 +4,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 
diff --git a/test/CodeGen/Mips/llvm-ir/and.ll b/test/CodeGen/Mips/llvm-ir/and.ll
index 09d0ef9238af..8ebcfe4a3f64 100644
--- a/test/CodeGen/Mips/llvm-ir/and.ll
+++ b/test/CodeGen/Mips/llvm-ir/and.ll
@@ -4,6 +4,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 
@@ -51,10 +59,7 @@ define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: and_i32:
 
-  ; GP32:         and     $2, $4, $5
-
-  ; GP64:         and     $[[T0:[0-9]+]], $4, $5
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          and     $2, $4, $5
 
   %r = and i32 %a, %b
   ret i32 %r
diff --git a/test/CodeGen/Mips/llvm-ir/ashr.ll b/test/CodeGen/Mips/llvm-ir/ashr.ll
index 415998929aa0..cad4a39d7743 100644
--- a/test/CodeGen/Mips/llvm-ir/ashr.ll
+++ b/test/CodeGen/Mips/llvm-ir/ashr.ll
@@ -1,30 +1,42 @@
 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=M2 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=M2
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \
-; RUN:    -check-prefix=32R1-R2
+; RUN:    -check-prefix=ALL -check-prefix=GP32 \
+; RUN:    -check-prefix=32R1-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R1-R2 -check-prefix=R2-R6
+; RUN:    -check-prefix=32R1-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32 \
+; RUN:    -check-prefix=32R1-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32 \
+; RUN:    -check-prefix=32R1-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R6 -check-prefix=R2-R6
+; RUN:    -check-prefix=32R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=M3 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=M3
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
+; RUN:    -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64 \
+; RUN:    -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64 \
+; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=64R6 -check-prefix=R2-R6
+; RUN:    -check-prefix=64R6
 
 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) {
 entry:
@@ -91,17 +103,17 @@ entry:
   ; M2:         jr        $ra
   ; M2:         nop
 
-  ; 32R1-R2:    srlv      $[[T0:[0-9]+]], $5, $7
-  ; 32R1-R2:    not       $[[T1:[0-9]+]], $7
-  ; 32R1-R2:    sll       $[[T2:[0-9]+]], $4, 1
-  ; 32R1-R2:    sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
-  ; 32R1-R2:    or        $3, $[[T3]], $[[T0]]
-  ; 32R1-R2:    srav      $[[T4:[0-9]+]], $4, $7
-  ; 32R1-R2:    andi      $[[T5:[0-9]+]], $7, 32
-  ; 32R1-R2:    movn      $3, $[[T4]], $[[T5]]
-  ; 32R1-R2:    sra       $4, $4, 31
-  ; 32R1-R2:    jr        $ra
-  ; 32R1-R2:    movn      $2, $4, $[[T5]]
+  ; 32R1-R5:    srlv      $[[T0:[0-9]+]], $5, $7
+  ; 32R1-R5:    not       $[[T1:[0-9]+]], $7
+  ; 32R1-R5:    sll       $[[T2:[0-9]+]], $4, 1
+  ; 32R1-R5:    sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; 32R1-R5:    or        $3, $[[T3]], $[[T0]]
+  ; 32R1-R5:    srav      $[[T4:[0-9]+]], $4, $7
+  ; 32R1-R5:    andi      $[[T5:[0-9]+]], $7, 32
+  ; 32R1-R5:    movn      $3, $[[T4]], $[[T5]]
+  ; 32R1-R5:    sra       $4, $4, 31
+  ; 32R1-R5:    jr        $ra
+  ; 32R1-R5:    movn      $2, $4, $[[T5]]
 
   ; 32R6:       srav      $[[T0:[0-9]+]], $4, $7
   ; 32R6:       andi      $[[T1:[0-9]+]], $7, 32
@@ -119,9 +131,7 @@ entry:
   ; 32R6:       jr        $ra
   ; 32R6:       or        $3, $[[T0]], $[[T11]]
 
-  ; FIXME: The sll instruction below is redundant.
-  ; GP64:       sll       $[[T0:[0-9]+]], $5, 0
-  ; GP64:       dsrav     $2, $4, $[[T0]]
+  ; GP64:       dsrav     $2, $4, $5
 
   %r = ashr i64 %a, %b
   ret i64 %r
@@ -134,11 +144,11 @@ entry:
   ; GP32:           lw        $25, %call16(__ashrti3)($gp)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
-  ; M3:             dsrav     $[[T1:[0-9]+]], $4, $[[T0]]
+  ; M3:             dsrav     $[[T1:[0-9]+]], $4, $7
   ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
   ; M3:             bnez      $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
   ; M3:             move      $3, $[[T1]]
-  ; M3:             dsrlv     $[[T4:[0-9]+]], $5, $[[T0]]
+  ; M3:             dsrlv     $[[T4:[0-9]+]], $5, $7
   ; M3:             dsll      $[[T5:[0-9]+]], $4, 1
   ; M3:             not       $[[T6:[0-9]+]], $[[T0]]
   ; M3:             dsllv     $[[T7:[0-9]+]], $[[T5]], $[[T6]]
@@ -151,35 +161,34 @@ entry:
   ; M3:             jr        $ra
   ; M3:             nop
 
-  ; GP64-NOT-R6:    sll       $[[T0:[0-9]+]], $7, 0
-  ; GP64-NOT-R6:    dsrlv     $[[T1:[0-9]+]], $5, $[[T0]]
-  ; GP64-NOT-R6:    dsll      $[[T2:[0-9]+]], $4, 1
-  ; GP64-NOT-R6:    not       $[[T3:[0-9]+]], $[[T0]]
-  ; GP64-NOT-R6:    dsllv     $[[T4:[0-9]+]], $[[T2]], $[[T3]]
-  ; GP64-NOT-R6:    or        $3, $[[T4]], $[[T1]]
-  ; GP64-NOT-R6:    dsrav     $2, $4, $[[T0]]
-  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T0]], 64
-
+  ; GP64-NOT-R6:    dsrlv     $[[T0:[0-9]+]], $5, $7
+  ; GP64-NOT-R6:    dsll      $[[T1:[0-9]+]], $4, 1
+  ; GP64-NOT-R6:    sll       $[[T2:[0-9]+]], $7, 0
+  ; GP64-NOT-R6:    not       $[[T3:[0-9]+]], $[[T2]]
+  ; GP64-NOT-R6:    dsllv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+  ; GP64-NOT-R6:    or        $3, $[[T4]], $[[T0]]
+  ; GP64-NOT-R6:    dsrav     $2, $4, $7
+  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T2]], 64
   ; GP64-NOT-R6:    movn      $3, $2, $[[T5]]
   ; GP64-NOT-R6:    dsra      $[[T6:[0-9]+]], $4, 63
   ; GP64-NOT-R6:    jr        $ra
   ; GP64-NOT-R6:    movn      $2, $[[T6]], $[[T5]]
 
-  ; 64R6:           sll       $[[T0:[0-9]+]], $7, 0
-  ; 64R6:           dsrav     $[[T1:[0-9]+]], $4, $[[T0]]
-  ; 64R6:           andi      $[[T2:[0-9]+]], $[[T0]], 64
+  ; 64R6:           dsrav     $[[T0:[0-9]+]], $4, $7
+  ; 64R6:           sll       $[[T1:[0-9]+]], $7, 0
+  ; 64R6:           andi      $[[T2:[0-9]+]], $[[T1]], 64
   ; 64R6:           sll       $[[T3:[0-9]+]], $[[T2]], 0
-  ; 64R6:           seleqz    $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+  ; 64R6:           seleqz    $[[T4:[0-9]+]], $[[T0]], $[[T3]]
   ; 64R6:           dsra      $[[T5:[0-9]+]], $4, 63
   ; 64R6:           selnez    $[[T6:[0-9]+]], $[[T5]], $[[T3]]
   ; 64R6:           or        $2, $[[T6]], $[[T4]]
-  ; 64R6:           dsrlv     $[[T7:[0-9]+]], $5, $[[T0]]
+  ; 64R6:           dsrlv     $[[T7:[0-9]+]], $5, $7
   ; 64R6:           dsll      $[[T8:[0-9]+]], $4, 1
-  ; 64R6:           not       $[[T9:[0-9]+]], $[[T0]]
+  ; 64R6:           not       $[[T9:[0-9]+]], $[[T1]]
   ; 64R6:           dsllv     $[[T10:[0-9]+]], $[[T8]], $[[T9]]
   ; 64R6:           or        $[[T11:[0-9]+]], $[[T10]], $[[T7]]
   ; 64R6:           seleqz    $[[T12:[0-9]+]], $[[T11]], $[[T3]]
-  ; 64R6:           selnez    $[[T13:[0-9]+]], $[[T1]], $[[T3]]
+  ; 64R6:           selnez    $[[T13:[0-9]+]], $[[T0]], $[[T3]]
   ; 64R6:           jr        $ra
   ; 64R6:           or        $3, $[[T13]], $[[T12]]
 
diff --git a/test/CodeGen/Mips/llvm-ir/call.ll b/test/CodeGen/Mips/llvm-ir/call.ll
index 4cbf43cae28e..112ab8ee8c7f 100644
--- a/test/CodeGen/Mips/llvm-ir/call.ll
+++ b/test/CodeGen/Mips/llvm-ir/call.ll
@@ -3,10 +3,14 @@
 ; FIXME: We should remove the need for -enable-mips-tail-calls
 ; RUN: llc -march=mips   -mcpu=mips32   -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
 ; RUN: llc -march=mips   -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
+; RUN: llc -march=mips   -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
+; RUN: llc -march=mips   -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
 ; RUN: llc -march=mips   -mcpu=mips32r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
 ; RUN: llc -march=mips64 -mcpu=mips4    -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
 ; RUN: llc -march=mips64 -mcpu=mips64   -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
 ; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
+; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
+; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
 ; RUN: llc -march=mips64 -mcpu=mips64r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
 
 declare void @extern_void_void()
diff --git a/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/test/CodeGen/Mips/llvm-ir/indirectbr.ll
index d8fd78774553..debfeb35b213 100644
--- a/test/CodeGen/Mips/llvm-ir/indirectbr.ll
+++ b/test/CodeGen/Mips/llvm-ir/indirectbr.ll
@@ -2,10 +2,14 @@
 
 ; RUN: llc -march=mips   -mcpu=mips32   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
+; RUN: llc -march=mips   -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
+; RUN: llc -march=mips   -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6
 ; RUN: llc -march=mips64 -mcpu=mips4    -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6
 
 define i32 @br(i8 *%addr) {
diff --git a/test/CodeGen/Mips/llvm-ir/lshr.ll b/test/CodeGen/Mips/llvm-ir/lshr.ll
index 59f4330dde6c..3a7029fa5b7a 100644
--- a/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -1,30 +1,42 @@
 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=M2 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=M2
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \
-; RUN:    -check-prefix=32R1-R2
+; RUN:    -check-prefix=ALL -check-prefix=GP32 \
+; RUN:    -check-prefix=32R1-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R1-R2 -check-prefix=R2-R6
+; RUN:    -check-prefix=32R1-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32 \
+; RUN:    -check-prefix=32R1-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32 \
+; RUN:    -check-prefix=32R1-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R6 -check-prefix=R2-R6
+; RUN:    -check-prefix=32R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=M3 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=M3
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
+; RUN:    -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64 \
+; RUN:    -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64 \
+; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=64R6 -check-prefix=R2-R6
+; RUN:    -check-prefix=64R6
 
 define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) {
 entry:
@@ -89,16 +101,16 @@ entry:
   ; M2:         jr        $ra
   ; M2:         nop
 
-  ; 32R1-R2:    srlv      $[[T0:[0-9]+]], $5, $7
-  ; 32R1-R2:    not       $[[T1:[0-9]+]], $7
-  ; 32R1-R2:    sll       $[[T2:[0-9]+]], $4, 1
-  ; 32R1-R2:    sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
-  ; 32R1-R2:    or        $3, $[[T3]], $[[T0]]
-  ; 32R1-R2:    srlv      $[[T4:[0-9]+]], $4, $7
-  ; 32R1-R2:    andi      $[[T5:[0-9]+]], $7, 32
-  ; 32R1-R2:    movn      $3, $[[T4]], $[[T5]]
-  ; 32R1-R2:    jr        $ra
-  ; 32R1-R2:    movn      $2, $zero, $[[T5]]
+  ; 32R1-R5:    srlv      $[[T0:[0-9]+]], $5, $7
+  ; 32R1-R5:    not       $[[T1:[0-9]+]], $7
+  ; 32R1-R5:    sll       $[[T2:[0-9]+]], $4, 1
+  ; 32R1-R5:    sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; 32R1-R5:    or        $3, $[[T3]], $[[T0]]
+  ; 32R1-R5:    srlv      $[[T4:[0-9]+]], $4, $7
+  ; 32R1-R5:    andi      $[[T5:[0-9]+]], $7, 32
+  ; 32R1-R5:    movn      $3, $[[T4]], $[[T5]]
+  ; 32R1-R5:    jr        $ra
+  ; 32R1-R5:    movn      $2, $zero, $[[T5]]
 
   ; 32R6:       srlv      $[[T0:[0-9]+]], $5, $7
   ; 32R6:       not       $[[T1:[0-9]+]], $7
@@ -113,8 +125,7 @@ entry:
   ; 32R6:       jr        $ra
   ; 32R6:       seleqz    $2, $[[T7]], $[[T5]]
 
-  ; GP64:         sll     $[[T0:[0-9]+]], $5, 0
-  ; GP64:         dsrlv   $2, $4, $[[T0]]
+  ; GP64:         dsrlv   $2, $4, $5
 
   %r = lshr i64 %a, %b
   ret i64 %r
@@ -127,11 +138,11 @@ entry:
   ; GP32:         lw      $25, %call16(__lshrti3)($gp)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
-  ; M3:             dsrlv     $[[T1:[0-9]+]], $4, $[[T0]]
+  ; M3:             dsrlv     $[[T1:[0-9]+]], $4, $7
   ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
   ; M3:             bnez      $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
   ; M3:             move      $3, $[[T1]]
-  ; M3:             dsrlv     $[[T4:[0-9]+]], $5, $[[T0]]
+  ; M3:             dsrlv     $[[T4:[0-9]+]], $5, $7
   ; M3:             dsll      $[[T5:[0-9]+]], $4, 1
   ; M3:             not       $[[T6:[0-9]+]], $[[T0]]
   ; M3:             dsllv     $[[T7:[0-9]+]], $[[T5]], $[[T6]]
@@ -144,32 +155,32 @@ entry:
   ; M3:             jr        $ra
   ; M3:             nop
 
-  ; GP64-NOT-R6:    sll       $[[T0:[0-9]+]], $7, 0
-  ; GP64-NOT-R6:    dsrlv     $[[T1:[0-9]+]], $5, $[[T0]]
-  ; GP64-NOT-R6:    dsll      $[[T2:[0-9]+]], $4, 1
-  ; GP64-NOT-R6:    not       $[[T3:[0-9]+]], $[[T0]]
-  ; GP64-NOT-R6:    dsllv     $[[T4:[0-9]+]], $[[T2]], $[[T3]]
-  ; GP64-NOT-R6:    or        $3, $[[T4]], $[[T1]]
-  ; GP64-NOT-R6:    dsrlv     $2, $4, $[[T0]]
-  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T0]], 64
+  ; GP64-NOT-R6:    dsrlv     $[[T0:[0-9]+]], $5, $7
+  ; GP64-NOT-R6:    dsll      $[[T1:[0-9]+]], $4, 1
+  ; GP64-NOT-R6:    sll       $[[T2:[0-9]+]], $7, 0
+  ; GP64-NOT-R6:    not       $[[T3:[0-9]+]], $[[T2]]
+  ; GP64-NOT-R6:    dsllv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+  ; GP64-NOT-R6:    or        $3, $[[T4]], $[[T0]]
+  ; GP64-NOT-R6:    dsrlv     $2, $4, $7
+  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T2]], 64
   ; GP64-NOT-R6:    movn      $3, $2, $[[T5]]
   ; GP64-NOT-R6:    jr        $ra
   ; GP64-NOT-R6:    movn      $2, $zero, $1
 
-  ; 64R6:           sll       $[[T0:[0-9]+]], $7, 0
-  ; 64R6:           dsrlv     $[[T1:[0-9]+]], $5, $[[T0]]
-  ; 64R6:           dsll      $[[T2:[0-9]+]], $4, 1
-  ; 64R6:           not       $[[T3:[0-9]+]], $[[T0]]
-  ; 64R6:           dsllv     $[[T4:[0-9]+]], $[[T2]], $[[T3]]
-  ; 64R6:           or        $[[T5:[0-9]+]], $[[T4]], $[[T1]]
-  ; 64R6:           andi      $[[T6:[0-9]+]], $[[T0]], 64
+  ; 64R6:           dsrlv     $[[T0:[0-9]+]], $5, $7
+  ; 64R6:           dsll      $[[T1:[0-9]+]], $4, 1
+  ; 64R6:           sll       $[[T2:[0-9]+]], $7, 0
+  ; 64R6:           not       $[[T3:[0-9]+]], $[[T2]]
+  ; 64R6:           dsllv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+  ; 64R6:           or        $[[T5:[0-9]+]], $[[T4]], $[[T0]]
+  ; 64R6:           andi      $[[T6:[0-9]+]], $[[T2]], 64
   ; 64R6:           sll       $[[T7:[0-9]+]], $[[T6]], 0
   ; 64R6:           seleqz    $[[T8:[0-9]+]], $[[T5]], $[[T7]]
-  ; 64R6:           dsrlv     $[[T9:[0-9]+]], $4, $[[T0]]
+  ; 64R6:           dsrlv     $[[T9:[0-9]+]], $4, $7
   ; 64R6:           selnez    $[[T10:[0-9]+]], $[[T9]], $[[T7]]
   ; 64R6:           or        $3, $[[T10]], $[[T8]]
   ; 64R6:           jr        $ra
-  ; 64R6:           seleqz    $2, $[[T0]], $[[T7]]
+  ; 64R6:           seleqz    $2, $[[T9]], $[[T7]]
 
   %r = lshr i128 %a, %b
   ret i128 %r
diff --git a/test/CodeGen/Mips/llvm-ir/mul.ll b/test/CodeGen/Mips/llvm-ir/mul.ll
index 5f7f338c7789..a7582805dd74 100644
--- a/test/CodeGen/Mips/llvm-ir/mul.ll
+++ b/test/CodeGen/Mips/llvm-ir/mul.ll
@@ -1,17 +1,25 @@
 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=M2 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \
-; RUN:    -check-prefix=32R1-R2 -check-prefix=GP32
+; RUN:    -check-prefix=32R1-R5 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \
-; RUN:    -check-prefix=32R1-R2 -check-prefix=32R2 -check-prefix=GP32
+; RUN:    -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=32R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=M4 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \
-; RUN:    -check-prefix=64R1-R2 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \
-; RUN:    -check-prefix=64R1-R2 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=64R6
 
@@ -24,9 +32,9 @@ entry:
   ; M2:         sll     $[[T0]], $[[T0]], 31
   ; M2:         sra     $2, $[[T0]], 31
 
-  ; 32R1-R2:    mul     $[[T0:[0-9]+]], $4, $5
-  ; 32R1-R2:    sll     $[[T0]], $[[T0]], 31
-  ; 32R1-R2:    sra     $2, $[[T0]], 31
+  ; 32R1-R5:    mul     $[[T0:[0-9]+]], $4, $5
+  ; 32R1-R5:    sll     $[[T0]], $[[T0]], 31
+  ; 32R1-R5:    sra     $2, $[[T0]], 31
 
   ; 32R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 32R6:       sll     $[[T0]], $[[T0]], 31
@@ -37,9 +45,9 @@ entry:
   ; M4:         sll     $[[T0]], $[[T0]], 31
   ; M4:         sra     $2, $[[T0]], 31
 
-  ; 64R1-R2:    mul     $[[T0:[0-9]+]], $4, $5
-  ; 64R1-R2:    sll     $[[T0]], $[[T0]], 31
-  ; 64R1-R2:    sra     $2, $[[T0]], 31
+  ; 64R1-R5:    mul     $[[T0:[0-9]+]], $4, $5
+  ; 64R1-R5:    sll     $[[T0]], $[[T0]], 31
+  ; 64R1-R5:    sra     $2, $[[T0]], 31
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       sll     $[[T0]], $[[T0]], 31
@@ -62,8 +70,8 @@ entry:
   ; 32R1:       sll     $[[T0]], $[[T0]], 24
   ; 32R1:       sra     $2, $[[T0]], 24
 
-  ; 32R2:       mul     $[[T0:[0-9]+]], $4, $5
-  ; 32R2:       seb     $2, $[[T0]]
+  ; 32R2-R5:    mul     $[[T0:[0-9]+]], $4, $5
+  ; 32R2-R5:    seb     $2, $[[T0]]
 
   ; 32R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 32R6:       seb     $2, $[[T0]]
@@ -99,8 +107,8 @@ entry:
   ; 32R1:       sll     $[[T0]], $[[T0]], 16
   ; 32R1:       sra     $2, $[[T0]], 16
 
-  ; 32R2:       mul     $[[T0:[0-9]+]], $4, $5
-  ; 32R2:       seh     $2, $[[T0]]
+  ; 32R2-R5:    mul     $[[T0:[0-9]+]], $4, $5
+  ; 32R2-R5:    seh     $2, $[[T0]]
 
   ; 32R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 32R6:       seh     $2, $[[T0]]
@@ -130,10 +138,10 @@ entry:
   ; M2:         mult    $4, $5
   ; M2:         mflo    $2
 
-  ; 32R1-R2:    mul     $2, $4, $5
+  ; 32R1-R5:    mul     $2, $4, $5
   ; 32R6:       mul     $2, $4, $5
 
-  ; 64R1-R2:    mul     $2, $4, $5
+  ; 64R1-R5:    mul     $2, $4, $5
   ; 64R6:       mul     $2, $4, $5
   %r = mul i32 %a, %b
   ret i32 %r
@@ -153,13 +161,13 @@ entry:
   ; M2:         addu    $[[T2:[0-9]+]], $4, $[[T1]]
   ; M2:         addu    $2, $[[T2]], $[[T0]]
 
-  ; 32R1-R2:    multu   $5, $7
-  ; 32R1-R2:    mflo    $3
-  ; 32R1-R2:    mfhi    $[[T0:[0-9]+]]
-  ; 32R1-R2:    mul     $[[T1:[0-9]+]], $4, $7
-  ; 32R1-R2:    mul     $[[T2:[0-9]+]], $5, $6
-  ; 32R1-R2:    addu    $[[T0]], $[[T0]], $[[T2:[0-9]+]]
-  ; 32R1-R2:    addu    $2, $[[T0]], $[[T1]]
+  ; 32R1-R5:    multu   $5, $7
+  ; 32R1-R5:    mflo    $3
+  ; 32R1-R5:    mfhi    $[[T0:[0-9]+]]
+  ; 32R1-R5:    mul     $[[T1:[0-9]+]], $4, $7
+  ; 32R1-R5:    mul     $[[T2:[0-9]+]], $5, $6
+  ; 32R1-R5:    addu    $[[T0]], $[[T0]], $[[T2:[0-9]+]]
+  ; 32R1-R5:    addu    $2, $[[T0]], $[[T1]]
 
   ; 32R6:       mul     $[[T0:[0-9]+]], $5, $6
   ; 32R6:       muhu    $[[T1:[0-9]+]], $5, $7
@@ -171,8 +179,8 @@ entry:
   ; M4:         dmult   $4, $5
   ; M4:         mflo    $2
 
-  ; 64R1-R2:    dmult   $4, $5
-  ; 64R1-R2:    mflo    $2
+  ; 64R1-R5:    dmult   $4, $5
+  ; 64R1-R5:    mflo    $2
 
   ; 64R6:       dmul    $2, $4, $5
 
diff --git a/test/CodeGen/Mips/llvm-ir/or.ll b/test/CodeGen/Mips/llvm-ir/or.ll
index 21d1d4fca2a3..6215e4036325 100644
--- a/test/CodeGen/Mips/llvm-ir/or.ll
+++ b/test/CodeGen/Mips/llvm-ir/or.ll
@@ -4,6 +4,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 
@@ -51,11 +59,7 @@ define signext i32 @or_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: or_i32:
 
-  ; GP32:         or     $2, $4, $5
-
-  ; GP64:         or     $[[T0:[0-9]+]], $4, $5
-  ; FIXME: The sll instruction below is redundant.
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          or     $2, $4, $5
 
   %r = or i32 %a, %b
   ret i32 %r
diff --git a/test/CodeGen/Mips/llvm-ir/ret.ll b/test/CodeGen/Mips/llvm-ir/ret.ll
index 8f5b1159760c..0561c24219ce 100644
--- a/test/CodeGen/Mips/llvm-ir/ret.ll
+++ b/test/CodeGen/Mips/llvm-ir/ret.ll
@@ -9,10 +9,14 @@
 
 ; RUN: llc -march=mips   -mcpu=mips32   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips   -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips   -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6
 ; RUN: llc -march=mips64 -mcpu=mips4    -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=R6
 
 define void @ret_void() {
diff --git a/test/CodeGen/Mips/llvm-ir/sdiv.ll b/test/CodeGen/Mips/llvm-ir/sdiv.ll
index 54b7f70b1dac..929ee88bb7f7 100644
--- a/test/CodeGen/Mips/llvm-ir/sdiv.ll
+++ b/test/CodeGen/Mips/llvm-ir/sdiv.ll
@@ -3,7 +3,11 @@
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=R2 -check-prefix=GP32
+; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -13,7 +17,11 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=R2 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=R6 -check-prefix=64R6
 
@@ -49,11 +57,11 @@ entry:
   ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 24
   ; NOT-R2-R6:    sra     $2, $[[T1]], 24
 
-  ; R2:           div     $zero, $4, $5
-  ; R2:           teq     $5, $zero, 7
-  ; R2:           mflo    $[[T0:[0-9]+]]
+  ; R2-R5:        div     $zero, $4, $5
+  ; R2-R5:        teq     $5, $zero, 7
+  ; R2-R5:        mflo    $[[T0:[0-9]+]]
   ; FIXME: This instruction is redundant.
-  ; R2:           seb     $2, $[[T0]]
+  ; R2-R5:        seb     $2, $[[T0]]
 
   ; R6:           div     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
@@ -75,11 +83,11 @@ entry:
   ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 16
   ; NOT-R2-R6:    sra     $2, $[[T1]], 16
 
-  ; R2:           div     $zero, $4, $5
-  ; R2:           teq     $5, $zero, 7
-  ; R2:           mflo    $[[T0:[0-9]+]]
+  ; R2-R5:        div     $zero, $4, $5
+  ; R2-R5:        teq     $5, $zero, 7
+  ; R2-R5:        mflo    $[[T0:[0-9]+]]
   ; FIXME: This is instruction is redundant since div is signed.
-  ; R2:           seh     $2, $[[T0]]
+  ; R2-R5:        seh     $2, $[[T0]]
 
   ; R6:           div     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
diff --git a/test/CodeGen/Mips/llvm-ir/select.ll b/test/CodeGen/Mips/llvm-ir/select.ll
index 736bc579088d..f17670adca33 100644
--- a/test/CodeGen/Mips/llvm-ir/select.ll
+++ b/test/CodeGen/Mips/llvm-ir/select.ll
@@ -5,7 +5,13 @@
 ; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV \
-; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2
+; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=CMOV \
+; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=CMOV \
+; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -16,6 +22,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
 
@@ -232,12 +242,12 @@ entry:
   ; M2:         jr      $ra
   ; M2:         mtc1    $6, $f1
 
-  ; CMOV-32:    mtc1    $7, $[[F0:f[0-9]+]]
-  ; CMOV-32R1:  mtc1    $6, $f{{[0-9]+}}
-  ; CMOV-32R2   mthc1   $6, $[[F0]]
-  ; CMOV-32:    andi    $[[T0:[0-9]+]], $4, 1
-  ; CMOV-32:    ldc1    $f0, 16($sp)
-  ; CMOV-32:    movn.d  $f0, $[[F0]], $[[T0]]
+  ; CMOV-32:      mtc1    $7, $[[F0:f[0-9]+]]
+  ; CMOV-32R1:    mtc1    $6, $f{{[0-9]+}}
+  ; CMOV-32R2-R5: mthc1   $6, $[[F0]]
+  ; CMOV-32:      andi    $[[T0:[0-9]+]], $4, 1
+  ; CMOV-32:      ldc1    $f0, 16($sp)
+  ; CMOV-32:      movn.d  $f0, $[[F0]], $[[T0]]
 
   ; SEL-32:     mtc1    $7, $[[F0:f[0-9]+]]
   ; SEL-32:     mthc1   $6, $[[F0]]
diff --git a/test/CodeGen/Mips/llvm-ir/shl.ll b/test/CodeGen/Mips/llvm-ir/shl.ll
index fc5243cc97f2..bba34c47ea82 100644
--- a/test/CodeGen/Mips/llvm-ir/shl.ll
+++ b/test/CodeGen/Mips/llvm-ir/shl.ll
@@ -3,10 +3,16 @@
 ; RUN:    -check-prefix=M2 -check-prefix=NOT-R2-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \
-; RUN:    -check-prefix=32R1-R2
+; RUN:    -check-prefix=32R1-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R1-R2 -check-prefix=R2-R6
+; RUN:    -check-prefix=32R1-R5 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32 \
+; RUN:    -check-prefix=32R1-R5 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32 \
+; RUN:    -check-prefix=32R1-R5 -check-prefix=R2-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
 ; RUN:    -check-prefix=32R6 -check-prefix=R2-R6
@@ -22,6 +28,12 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64 \
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64 \
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=64R6 -check-prefix=R2-R6
@@ -101,16 +113,16 @@ entry:
   ; M2:         jr        $ra
   ; M2:         nop
 
-  ; 32R1-R2:    sllv      $[[T0:[0-9]+]], $4, $7
-  ; 32R1-R2:    not       $[[T1:[0-9]+]], $7
-  ; 32R1-R2:    srl       $[[T2:[0-9]+]], $5, 1
-  ; 32R1-R2:    srlv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
-  ; 32R1-R2:    or        $2, $[[T0]], $[[T3]]
-  ; 32R1-R2:    sllv      $[[T4:[0-9]+]], $5, $7
-  ; 32R1-R2:    andi      $[[T5:[0-9]+]], $7, 32
-  ; 32R1-R2:    movn      $2, $[[T4]], $[[T5]]
-  ; 32R1-R2:    jr        $ra
-  ; 32R1-R2:    movn      $3, $zero, $[[T5]]
+  ; 32R1-R5:    sllv      $[[T0:[0-9]+]], $4, $7
+  ; 32R1-R5:    not       $[[T1:[0-9]+]], $7
+  ; 32R1-R5:    srl       $[[T2:[0-9]+]], $5, 1
+  ; 32R1-R5:    srlv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; 32R1-R5:    or        $2, $[[T0]], $[[T3]]
+  ; 32R1-R5:    sllv      $[[T4:[0-9]+]], $5, $7
+  ; 32R1-R5:    andi      $[[T5:[0-9]+]], $7, 32
+  ; 32R1-R5:    movn      $2, $[[T4]], $[[T5]]
+  ; 32R1-R5:    jr        $ra
+  ; 32R1-R5:    movn      $3, $zero, $[[T5]]
 
   ; 32R6:       sllv      $[[T0:[0-9]+]], $4, $7
   ; 32R6:       not       $[[T1:[0-9]+]], $7
@@ -125,8 +137,7 @@ entry:
   ; 32R6:       jr        $ra
   ; 32R6:       seleqz    $3, $[[T7]], $[[T5]]
 
-  ; GP64:       sll       $[[T0:[0-9]+]], $5, 0
-  ; GP64:       dsllv     $2, $4, $1
+  ; GP64:       dsllv     $2, $4, $5
 
   %r = shl i64 %a, %b
   ret i64 %r
@@ -139,11 +150,11 @@ entry:
   ; GP32:           lw        $25, %call16(__ashlti3)($gp)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
-  ; M3:             dsllv     $[[T1:[0-9]+]], $5, $[[T0]]
+  ; M3:             dsllv     $[[T1:[0-9]+]], $5, $7
   ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
   ; M3:             bnez      $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
   ; M3:             move      $2, $[[T1]]
-  ; M3:             dsllv     $[[T4:[0-9]+]], $4, $[[T0]]
+  ; M3:             dsllv     $[[T4:[0-9]+]], $4, $7
   ; M3:             dsrl      $[[T5:[0-9]+]], $5, 1
   ; M3:             not       $[[T6:[0-9]+]], $[[T0]]
   ; M3:             dsrlv     $[[T7:[0-9]+]], $[[T5]], $[[T6]]
@@ -156,32 +167,32 @@ entry:
   ; M3:             jr        $ra
   ; M3:             nop
 
-  ; GP64-NOT-R6:    sll       $[[T0:[0-9]+]], $7, 0
-  ; GP64-NOT-R6:    dsllv     $[[T1:[0-9]+]], $4, $[[T0]]
-  ; GP64-NOT-R6:    dsrl      $[[T2:[0-9]+]], $5, 1
-  ; GP64-NOT-R6:    not       $[[T3:[0-9]+]], $[[T0]]
-  ; GP64-NOT-R6:    dsrlv     $[[T4:[0-9]+]], $[[T2]], $[[T3]]
-  ; GP64-NOT-R6:    or        $2, $[[T1]], $[[T4]]
-  ; GP64-NOT-R6:    dsllv     $3, $5, $[[T0]]
-  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T0]], 64
+  ; GP64-NOT-R6:    dsllv     $[[T0:[0-9]+]], $4, $7
+  ; GP64-NOT-R6:    dsrl      $[[T1:[0-9]+]], $5, 1
+  ; GP64-NOT-R6:    sll       $[[T2:[0-9]+]], $7, 0
+  ; GP64-NOT-R6:    not       $[[T3:[0-9]+]], $[[T2]]
+  ; GP64-NOT-R6:    dsrlv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+  ; GP64-NOT-R6:    or        $2, $[[T0]], $[[T4]]
+  ; GP64-NOT-R6:    dsllv     $3, $5, $7
+  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T2]], 64
   ; GP64-NOT-R6:    movn      $2, $3, $[[T5]]
   ; GP64-NOT-R6:    jr        $ra
   ; GP64-NOT-R6:    movn      $3, $zero, $1
 
-  ; 64R6:           sll       $[[T0:[0-9]+]], $7, 0
-  ; 64R6:           dsllv     $[[T1:[0-9]+]], $4, $[[T0]]
-  ; 64R6:           dsrl      $[[T2:[0-9]+]], $5, 1
-  ; 64R6:           not       $[[T3:[0-9]+]], $[[T0]]
-  ; 64R6:           dsrlv     $[[T4:[0-9]+]], $[[T2]], $[[T3]]
-  ; 64R6:           or        $[[T5:[0-9]+]], $[[T1]], $[[T4]]
-  ; 64R6:           andi      $[[T6:[0-9]+]], $[[T0]], 64
+  ; 64R6:           dsllv     $[[T0:[0-9]+]], $4, $7
+  ; 64R6:           dsrl      $[[T1:[0-9]+]], $5, 1
+  ; 64R6:           sll       $[[T2:[0-9]+]], $7, 0
+  ; 64R6:           not       $[[T3:[0-9]+]], $[[T2]]
+  ; 64R6:           dsrlv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+  ; 64R6:           or        $[[T5:[0-9]+]], $[[T0]], $[[T4]]
+  ; 64R6:           andi      $[[T6:[0-9]+]], $[[T2]], 64
   ; 64R6:           sll       $[[T7:[0-9]+]], $[[T6]], 0
   ; 64R6:           seleqz    $[[T8:[0-9]+]], $[[T5]], $[[T7]]
-  ; 64R6:           dsllv     $[[T9:[0-9]+]], $5, $[[T0]]
+  ; 64R6:           dsllv     $[[T9:[0-9]+]], $5, $7
   ; 64R6:           selnez    $[[T10:[0-9]+]], $[[T9]], $[[T7]]
   ; 64R6:           or        $2, $[[T10]], $[[T8]]
   ; 64R6:           jr        $ra
-  ; 64R6:           seleqz    $3, $[[T0]], $[[T7]]
+  ; 64R6:           seleqz    $3, $[[T9]], $[[T7]]
 
   %r = shl i128 %a, %b
   ret i128 %r
diff --git a/test/CodeGen/Mips/llvm-ir/srem.ll b/test/CodeGen/Mips/llvm-ir/srem.ll
index 1e949d24678b..ceb53ee7033a 100644
--- a/test/CodeGen/Mips/llvm-ir/srem.ll
+++ b/test/CodeGen/Mips/llvm-ir/srem.ll
@@ -3,7 +3,11 @@
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
 ; RUN:  -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \
-; RUN:  -check-prefix=R2 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:   -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -13,7 +17,13 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
 ; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN:  -check-prefix=R2 -check-prefix=R2-R6 \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
+; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
+; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
 ; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:  -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
@@ -47,10 +57,10 @@ entry:
   ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 24
   ; NOT-R2-R6:    sra     $2, $[[T1]], 24
 
-  ; R2:           div     $zero, $4, $5
-  ; R2:           teq     $5, $zero, 7
-  ; R2:           mfhi    $[[T0:[0-9]+]]
-  ; R2:           seb     $2, $[[T0]]
+  ; R2-R5:        div     $zero, $4, $5
+  ; R2-R5:        teq     $5, $zero, 7
+  ; R2-R5:        mfhi    $[[T0:[0-9]+]]
+  ; R2-R5:        seb     $2, $[[T0]]
 
   ; R6:           mod     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
@@ -70,10 +80,10 @@ entry:
   ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 16
   ; NOT-R2-R6:    sra     $2, $[[T1]], 16
 
-  ; R2:           div     $zero, $4, $5
-  ; R2:           teq     $5, $zero, 7
-  ; R2:           mfhi    $[[T0:[0-9]+]]
-  ; R2:           seh     $2, $[[T1]]
+  ; R2-R5:        div     $zero, $4, $5
+  ; R2-R5:        teq     $5, $zero, 7
+  ; R2-R5:        mfhi    $[[T0:[0-9]+]]
+  ; R2-R5:        seh     $2, $[[T1]]
 
   ; R6:           mod     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
diff --git a/test/CodeGen/Mips/llvm-ir/sub.ll b/test/CodeGen/Mips/llvm-ir/sub.ll
index 6d592be38211..164975844d73 100644
--- a/test/CodeGen/Mips/llvm-ir/sub.ll
+++ b/test/CodeGen/Mips/llvm-ir/sub.ll
@@ -4,6 +4,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 
diff --git a/test/CodeGen/Mips/llvm-ir/udiv.ll b/test/CodeGen/Mips/llvm-ir/udiv.ll
index 1f7aa0d5f4ce..a7cafe52d1ac 100644
--- a/test/CodeGen/Mips/llvm-ir/udiv.ll
+++ b/test/CodeGen/Mips/llvm-ir/udiv.ll
@@ -4,6 +4,10 @@
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=R6 -check-prefix=64R6
 
diff --git a/test/CodeGen/Mips/llvm-ir/urem.ll b/test/CodeGen/Mips/llvm-ir/urem.ll
index 73235341a42f..d5a231c8dfca 100644
--- a/test/CodeGen/Mips/llvm-ir/urem.ll
+++ b/test/CodeGen/Mips/llvm-ir/urem.ll
@@ -3,7 +3,11 @@
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
 ; RUN:  -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \
-; RUN:  -check-prefix=R2 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:   -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -13,7 +17,13 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
 ; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN:  -check-prefix=R2 -check-prefix=R2-R6 \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
+; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
+; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
 ; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:  -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
@@ -53,12 +63,12 @@ entry:
   ; NOT-R2-R6:    sll     $[[T3:[0-9]+]], $[[T2]], 24
   ; NOT-R2-R6:    sra     $2, $[[T3]], 24
 
-  ; R2:           andi    $[[T0:[0-9]+]], $5, 255
-  ; R2:           andi    $[[T1:[0-9]+]], $4, 255
-  ; R2:           divu    $zero, $[[T1]], $[[T0]]
-  ; R2:           teq     $[[T0]], $zero, 7
-  ; R2:           mfhi    $[[T2:[0-9]+]]
-  ; R2:           seb     $2, $[[T2]]
+  ; R2-R5:        andi    $[[T0:[0-9]+]], $5, 255
+  ; R2-R5:        andi    $[[T1:[0-9]+]], $4, 255
+  ; R2-R5:        divu    $zero, $[[T1]], $[[T0]]
+  ; R2-R5:        teq     $[[T0]], $zero, 7
+  ; R2-R5:        mfhi    $[[T2:[0-9]+]]
+  ; R2-R5:        seb     $2, $[[T2]]
 
   ; R6:           andi    $[[T0:[0-9]+]], $5, 255
   ; R6:           andi    $[[T1:[0-9]+]], $4, 255
@@ -82,12 +92,12 @@ entry:
   ; NOT-R2-R6:    sll     $[[T3:[0-9]+]], $[[T2]], 16
   ; NOT-R2-R6:    sra     $2, $[[T3]], 16
 
-  ; R2:           andi    $[[T0:[0-9]+]], $5, 65535
-  ; R2:           andi    $[[T1:[0-9]+]], $4, 65535
-  ; R2:           divu    $zero, $[[T1]], $[[T0]]
-  ; R2:           teq     $[[T0]], $zero, 7
-  ; R2:           mfhi    $[[T3:[0-9]+]]
-  ; R2:           seh     $2, $[[T2]]
+  ; R2-R5:        andi    $[[T0:[0-9]+]], $5, 65535
+  ; R2-R5:        andi    $[[T1:[0-9]+]], $4, 65535
+  ; R2-R5:        divu    $zero, $[[T1]], $[[T0]]
+  ; R2-R5:        teq     $[[T0]], $zero, 7
+  ; R2-R5:        mfhi    $[[T3:[0-9]+]]
+  ; R2-R5:        seh     $2, $[[T2]]
 
   ; R6:           andi    $[[T0:[0-9]+]], $5, 65535
   ; R6:           andi    $[[T1:[0-9]+]], $4, 65535
diff --git a/test/CodeGen/Mips/llvm-ir/xor.ll b/test/CodeGen/Mips/llvm-ir/xor.ll
index 94dead1eff41..89af99981a3c 100644
--- a/test/CodeGen/Mips/llvm-ir/xor.ll
+++ b/test/CodeGen/Mips/llvm-ir/xor.ll
@@ -4,6 +4,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 
@@ -51,10 +59,7 @@ define signext i32 @xor_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: xor_i32:
 
-  ; GP32:         xor     $2, $4, $5
-
-  ; GP64:         xor     $[[T0:[0-9]+]], $4, $5
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          xor     $2, $4, $5
 
   %r = xor i32 %a, %b
   ret i32 %r
diff --git a/test/CodeGen/Mips/load-store-left-right.ll b/test/CodeGen/Mips/load-store-left-right.ll
index f6d0e8debb36..a01d246ae460 100644
--- a/test/CodeGen/Mips/load-store-left-right.ll
+++ b/test/CodeGen/Mips/load-store-left-right.ll
@@ -4,14 +4,14 @@
 ; RUN: llc -march=mips     -mcpu=mips32r2            < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32 -check-prefix=MIPS32-EB %s
 ; RUN: llc -march=mipsel   -mcpu=mips32r6            < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32R6 -check-prefix=MIPS32R6-EL %s
 ; RUN: llc -march=mips     -mcpu=mips32r6            < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32R6 -check-prefix=MIPS32R6-EB %s
-; RUN: llc -march=mips64el -mcpu=mips4    -mattr=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EL %s
-; RUN: llc -march=mips64   -mcpu=mips4    -mattr=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EB %s
-; RUN: llc -march=mips64el -mcpu=mips64   -mattr=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EL %s
-; RUN: llc -march=mips64   -mcpu=mips64   -mattr=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EB %s
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EL %s
-; RUN: llc -march=mips64   -mcpu=mips64r2 -mattr=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EB %s
-; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64R6 -check-prefix=MIPS64R6-EL %s
-; RUN: llc -march=mips64   -mcpu=mips64r6 -mattr=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64R6 -check-prefix=MIPS64R6-EB %s
+; RUN: llc -march=mips64el -mcpu=mips4    -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EL %s
+; RUN: llc -march=mips64   -mcpu=mips4    -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EB %s
+; RUN: llc -march=mips64el -mcpu=mips64   -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EL %s
+; RUN: llc -march=mips64   -mcpu=mips64   -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EB %s
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EL %s
+; RUN: llc -march=mips64   -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EB %s
+; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64R6 -check-prefix=MIPS64R6-EL %s
+; RUN: llc -march=mips64   -mcpu=mips64r6 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64R6 -check-prefix=MIPS64R6-EB %s
 
 %struct.SLL = type { i64 }
 %struct.SI = type { i32 }
@@ -43,7 +43,7 @@ entry:
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(si)(
 ; MIPS64R6:      lw $2, 0($[[PTR]])
 
-  %0 = load i32* getelementptr inbounds (%struct.SI* @si, i32 0, i32 0), align 1
+  %0 = load i32, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i32 0, i32 0), align 1
   ret i32 %0
 }
 
@@ -69,7 +69,7 @@ entry:
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(si)(
 ; MIPS64R6:      sw $4, 0($[[PTR]])
 
-  store i32 %a, i32* getelementptr inbounds (%struct.SI* @si, i32 0, i32 0), align 1
+  store i32 %a, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i32 0, i32 0), align 1
   ret void
 }
 
@@ -100,7 +100,7 @@ entry:
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(sll)(
 ; MIPS64R6:      ld $2, 0($[[PTR]])
 
-  %0 = load i64* getelementptr inbounds (%struct.SLL* @sll, i64 0, i32 0), align 1
+  %0 = load i64, i64* getelementptr inbounds (%struct.SLL, %struct.SLL* @sll, i64 0, i32 0), align 1
   ret i64 %0
 }
 
@@ -129,7 +129,7 @@ entry:
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(si)(
 ; MIPS64R6:      lw $2, 0($[[PTR]])
 
-  %0 = load i32* getelementptr inbounds (%struct.SI* @si, i64 0, i32 0), align 1
+  %0 = load i32, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i64 0, i32 0), align 1
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
@@ -165,7 +165,7 @@ entry:
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(sui)(
 ; MIPS64R6:      lwu $2, 0($[[PTR]])
 
-  %0 = load i32* getelementptr inbounds (%struct.SUI* @sui, i64 0, i32 0), align 1
+  %0 = load i32, i32* getelementptr inbounds (%struct.SUI, %struct.SUI* @sui, i64 0, i32 0), align 1
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
@@ -197,7 +197,7 @@ entry:
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(sll)(
 ; MIPS64R6:      sd $4, 0($[[PTR]])
 
-  store i64 %a, i64* getelementptr inbounds (%struct.SLL* @sll, i64 0, i32 0), align 1
+  store i64 %a, i64* getelementptr inbounds (%struct.SLL, %struct.SLL* @sll, i64 0, i32 0), align 1
   ret void
 }
 
@@ -223,7 +223,7 @@ entry:
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(si)(
 ; MIPS64R6:      sw $4, 0($[[PTR]])
 
-  store i32 %a, i32* getelementptr inbounds (%struct.SI* @si, i64 0, i32 0), align 1
+  store i32 %a, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i64 0, i32 0), align 1
   ret void
 }
 
@@ -257,8 +257,8 @@ entry:
 ; ALL-DAG:       lbu $[[R1:[0-9]+]], 1($[[PTR]])
 ; ALL-DAG:       sb $[[R1]], 3($[[PTR]])
 
-  %0 = load %struct.S0* getelementptr inbounds (%struct.S0* @struct_s0, i32 0), align 1
-  store %struct.S0 %0, %struct.S0* getelementptr inbounds (%struct.S0* @struct_s0, i32 1), align 1
+  %0 = load %struct.S0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 0), align 1
+  store %struct.S0 %0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 1), align 1
   ret void
 }
 
@@ -300,8 +300,8 @@ entry:
 ; MIPS64R6-DAG:  lhu $[[R1:[0-9]+]], 2($[[PTR]])
 ; MIPS64R6-DAG:  sh $[[R1]], 6($[[PTR]])
 
-  %0 = load %struct.S1* getelementptr inbounds (%struct.S1* @struct_s1, i32 0), align 1
-  store %struct.S1 %0, %struct.S1* getelementptr inbounds (%struct.S1* @struct_s1, i32 1), align 1
+  %0 = load %struct.S1, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 0), align 1
+  store %struct.S1 %0, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 1), align 1
   ret void
 }
 
@@ -361,8 +361,8 @@ entry:
 ; MIPS64R6-DAG:  lw $[[R1:[0-9]+]], 4($[[PTR]])
 ; MIPS64R6-DAG:  sw $[[R1]],       12($[[PTR]])
 
-  %0 = load %struct.S2* getelementptr inbounds (%struct.S2* @struct_s2, i32 0), align 1
-  store %struct.S2 %0, %struct.S2* getelementptr inbounds (%struct.S2* @struct_s2, i32 1), align 1
+  %0 = load %struct.S2, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 0), align 1
+  store %struct.S2 %0, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 1), align 1
   ret void
 }
 
diff --git a/test/CodeGen/Mips/longbranch.ll b/test/CodeGen/Mips/longbranch.ll
index ad0235eb0af4..9f5b7417b859 100644
--- a/test/CodeGen/Mips/longbranch.ll
+++ b/test/CodeGen/Mips/longbranch.ll
@@ -1,9 +1,9 @@
 ; RUN: llc -march=mipsel < %s | FileCheck %s
 ; RUN: llc -march=mipsel -force-mips-long-branch -O3 < %s \
 ; RUN:   | FileCheck %s -check-prefix=O32
-; RUN: llc -march=mips64el -mcpu=mips4 -mattr=n64 -force-mips-long-branch -O3 \
+; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -force-mips-long-branch -O3 \
 ; RUN:   < %s | FileCheck %s -check-prefix=N64
-; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 -force-mips-long-branch -O3 \
+; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -force-mips-long-branch -O3 \
 ; RUN:   < %s | FileCheck %s -check-prefix=N64
 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=micromips \
 ; RUN:   -force-mips-long-branch -O3 < %s | FileCheck %s -check-prefix=MICROMIPS
@@ -124,10 +124,9 @@ end:
 ; MICROMIPS:   $[[BB0]]:
 ; MICROMIPS:        lw      $[[R1:[0-9]+]], %got(x)($[[GP]])
 ; MICROMIPS:        li16    $[[R2:[0-9]+]], 1
-; MICROMIPS:        sw      $[[R2]], 0($[[R1]])
+; MICROMIPS:        sw16    $[[R2]], 0($[[R1]])
 ; MICROMIPS:   $[[BB2]]:
-; MICROMIPS:        jr      $ra
-; MICROMIPS:        nop
+; MICROMIPS:        jrc      $ra
 
 
 ; Check the NaCl version.  Check that sp change is not in the branch delay slot
diff --git a/test/CodeGen/Mips/machineverifier.ll b/test/CodeGen/Mips/machineverifier.ll
index c673fe557e6b..d496b833a6c6 100644
--- a/test/CodeGen/Mips/machineverifier.ll
+++ b/test/CodeGen/Mips/machineverifier.ll
@@ -6,7 +6,7 @@
 
 define void @foo() nounwind {
 entry:
-  %0 = load i32* @g, align 4
+  %0 = load i32, i32* @g, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %if.end, label %if.then
 
diff --git a/test/CodeGen/Mips/mbrsize4a.ll b/test/CodeGen/Mips/mbrsize4a.ll
index 15e1f47ce29e..264d2284afc9 100644
--- a/test/CodeGen/Mips/mbrsize4a.ll
+++ b/test/CodeGen/Mips/mbrsize4a.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands   < %s | FileCheck %s -check-prefix=jal16
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands   < %s | FileCheck %s -check-prefix=jal16
 
 @j = global i32 10, align 4
 @.str = private unnamed_addr constant [11 x i8] c"at bottom\0A\00", align 1
@@ -17,11 +17,11 @@ z:                                                ; preds = %y, %entry
   br label %y
 
 y:                                                ; preds = %z
-  %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0))
+  %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0))
   br label %z
 
 return:                                           ; No predecessors!
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 ; jal16: 	jal	$BB{{[0-9]+}}_{{[0-9]+}}
 }
diff --git a/test/CodeGen/Mips/memcpy.ll b/test/CodeGen/Mips/memcpy.ll
index 39764a936381..5c4ebb27dde4 100644
--- a/test/CodeGen/Mips/memcpy.ll
+++ b/test/CodeGen/Mips/memcpy.ll
@@ -8,9 +8,9 @@ define void @foo1(%struct.S1* %s1, i8 signext %n) nounwind {
 entry:
 ; CHECK-NOT: call16(memcpy
 
-  %arraydecay = getelementptr inbounds %struct.S1* %s1, i32 0, i32 1, i32 0
-  tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %arraydecay, i8* getelementptr inbounds ([31 x i8]* @.str, i32 0, i32 0), i32 31, i32 1, i1 false)
-  %arrayidx = getelementptr inbounds %struct.S1* %s1, i32 0, i32 1, i32 40
+  %arraydecay = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 1, i32 0
+  tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %arraydecay, i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str, i32 0, i32 0), i32 31, i32 1, i1 false)
+  %arrayidx = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 1, i32 40
   store i8 %n, i8* %arrayidx, align 1
   ret void
 }
diff --git a/test/CodeGen/Mips/micromips-addiu.ll b/test/CodeGen/Mips/micromips-addiu.ll
index c5bee34028c8..e0743c9c088b 100644
--- a/test/CodeGen/Mips/micromips-addiu.ll
+++ b/test/CodeGen/Mips/micromips-addiu.ll
@@ -8,20 +8,20 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @x, align 4
+  %0 = load i32, i32* @x, align 4
   %addiu1 = add i32 %0, -7
-  %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
-                                  ([7 x i8]* @.str, i32 0, i32 0), i32 %addiu1)
+  %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds
+                                  ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %addiu1)
 
-  %1 = load i32* @y, align 4
+  %1 = load i32, i32* @y, align 4
   %addiu2 = add i32 %1, 55
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
-                                  ([7 x i8]* @.str, i32 0, i32 0), i32 %addiu2)
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds
+                                  ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %addiu2)
 
-  %2 = load i32* @z, align 4
+  %2 = load i32, i32* @z, align 4
   %addiu3 = add i32 %2, 24
-  %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
-                                  ([7 x i8]* @.str, i32 0, i32 0), i32 %addiu3)
+  %call3 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds
+                                  ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %addiu3)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/micromips-addu16.ll b/test/CodeGen/Mips/micromips-addu16.ll
new file mode 100644
index 000000000000..3ecdf2488d2c
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-addu16.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32, i32* %b, align 4
+  %1 = load i32, i32* %c, align 4
+  %add = add nsw i32 %0, %1
+  store i32 %add, i32* %a, align 4
+  ret i32 0
+}
+
+; CHECK: addu16
diff --git a/test/CodeGen/Mips/micromips-and16.ll b/test/CodeGen/Mips/micromips-and16.ll
new file mode 100644
index 000000000000..d0a16ac28a09
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-and16.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32, i32* %b, align 4
+  %1 = load i32, i32* %c, align 4
+  %and = and i32 %0, %1
+  store i32 %and, i32* %a, align 4
+  ret i32 0
+}
+
+; CHECK: and16
diff --git a/test/CodeGen/Mips/micromips-andi.ll b/test/CodeGen/Mips/micromips-andi.ll
index b82d2b09eae4..cd7a794cd1be 100644
--- a/test/CodeGen/Mips/micromips-andi.ll
+++ b/test/CodeGen/Mips/micromips-andi.ll
@@ -7,15 +7,15 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @x, align 4
+  %0 = load i32, i32* @x, align 4
   %and1 = and i32 %0, 4
-  %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
-                                  ([7 x i8]* @.str, i32 0, i32 0), i32 %and1)
+  %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds
+                                  ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and1)
 
-  %1 = load i32* @y, align 4
+  %1 = load i32, i32* @y, align 4
   %and2 = and i32 %1, 5
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
-                                  ([7 x i8]* @.str, i32 0, i32 0), i32 %and2)
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds
+                                  ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and2)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/micromips-compact-branches.ll b/test/CodeGen/Mips/micromips-compact-branches.ll
index 670f9a05064f..c689944d386b 100644
--- a/test/CodeGen/Mips/micromips-compact-branches.ll
+++ b/test/CodeGen/Mips/micromips-compact-branches.ll
@@ -4,7 +4,7 @@
 define void @main() nounwind uwtable {
 entry:
   %x = alloca i32, align 4
-  %0 = load i32* %x, align 4
+  %0 = load i32, i32* %x, align 4
   %cmp = icmp eq i32 %0, 0
   br i1 %cmp, label %if.then, label %if.end
 
diff --git a/test/CodeGen/Mips/micromips-compact-jump.ll b/test/CodeGen/Mips/micromips-compact-jump.ll
new file mode 100644
index 000000000000..70cff84e967f
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-compact-jump.ll
@@ -0,0 +1,11 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -disable-mips-delay-filler -O3 < %s | FileCheck %s
+
+define i32 @foo(i32 signext %a) #0 {
+entry:
+  ret i32 0
+}
+
+declare i32 @bar(i32 signext) #1
+
+; CHECK:      jrc
diff --git a/test/CodeGen/Mips/micromips-delay-slot-jr.ll b/test/CodeGen/Mips/micromips-delay-slot-jr.ll
index df593b35e2a6..c6636ff5b4c7 100644
--- a/test/CodeGen/Mips/micromips-delay-slot-jr.ll
+++ b/test/CodeGen/Mips/micromips-delay-slot-jr.ll
@@ -11,14 +11,14 @@ entry:
 
 L1:                                               ; preds = %entry, %L1
   %i.0 = phi i32 [ 0, %entry ], [ %inc, %L1 ]
-  %puts = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str, i32 0, i32 0))
+  %puts = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str, i32 0, i32 0))
   %inc = add i32 %i.0, 1
-  %arrayidx = getelementptr inbounds [3 x i8*]* @main.L, i32 0, i32 %i.0
-  %0 = load i8** %arrayidx, align 4, !tbaa !1
+  %arrayidx = getelementptr inbounds [3 x i8*], [3 x i8*]* @main.L, i32 0, i32 %i.0
+  %0 = load i8*, i8** %arrayidx, align 4, !tbaa !1
   indirectbr i8* %0, [label %L1, label %L2]
 
 L2:                                               ; preds = %L1
-  %puts2 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str2, i32 0, i32 0))
+  %puts2 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str2, i32 0, i32 0))
   ret i32 0
 }
 
@@ -29,20 +29,18 @@ declare i32 @puts(i8* nocapture readonly) #1
 !3 = !{!"omnipotent char", !4, i64 0}
 !4 = !{!"Simple C/C++ TBAA"}
 
-; CHECK:      jr
-; CHECK-NEXT: nop
+; CHECK:      jrc
 
 %struct.foostruct = type { [3 x float] }
 %struct.barstruct = type { %struct.foostruct, float }
 @bar_ary = common global [4 x %struct.barstruct] zeroinitializer, align 4
 define float* @spooky(i32 signext %i) #0 {
 
-  %safe = getelementptr inbounds [4 x %struct.barstruct]* @bar_ary, i32 0, i32 %i, i32 1
+  %safe = getelementptr inbounds [4 x %struct.barstruct], [4 x %struct.barstruct]* @bar_ary, i32 0, i32 %i, i32 1
   store float 1.420000e+02, float* %safe, align 4, !tbaa !1
   ret float* %safe
 }
 
 ; CHECK:      spooky:
-; CHECK:      jr $ra
-; CHECK-NEXT: nop
+; CHECK:      jrc $ra
 
diff --git a/test/CodeGen/Mips/micromips-delay-slot.ll b/test/CodeGen/Mips/micromips-delay-slot.ll
index b5f6c56235bc..ef6546232835 100644
--- a/test/CodeGen/Mips/micromips-delay-slot.ll
+++ b/test/CodeGen/Mips/micromips-delay-slot.ll
@@ -6,7 +6,7 @@ define i32 @foo(i32 signext %a) #0 {
 entry:
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
-  %0 = load i32* %a.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4
   %shl = shl i32 %0, 2
   %call = call i32 @bar(i32 signext %shl)
   ret i32 %call
diff --git a/test/CodeGen/Mips/micromips-gp-rc.ll b/test/CodeGen/Mips/micromips-gp-rc.ll
new file mode 100644
index 000000000000..f139f7a8486d
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-gp-rc.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+
+@g = external global i32
+
+; Function Attrs: noreturn nounwind
+define void @foo() #0 {
+entry:
+  %0 = load i32, i32* @g, align 4
+  tail call void @exit(i32 signext %0)
+  unreachable
+}
+
+; Function Attrs: noreturn
+declare void @exit(i32 signext)
+
+; CHECK: move $gp, ${{[0-9]+}}
+
diff --git a/test/CodeGen/Mips/micromips-jal.ll b/test/CodeGen/Mips/micromips-jal.ll
index fccc22919728..51832fe333dc 100644
--- a/test/CodeGen/Mips/micromips-jal.ll
+++ b/test/CodeGen/Mips/micromips-jal.ll
@@ -7,8 +7,8 @@ entry:
   %b.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
   store i32 %b, i32* %b.addr, align 4
-  %0 = load i32* %a.addr, align 4
-  %1 = load i32* %b.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4
+  %1 = load i32, i32* %b.addr, align 4
   %add = add nsw i32 %0, %1
   ret i32 %add
 }
@@ -20,11 +20,11 @@ entry:
   %y = alloca i32, align 4
   %z = alloca i32, align 4
   store i32 0, i32* %retval
-  %0 = load i32* %y, align 4
-  %1 = load i32* %z, align 4
+  %0 = load i32, i32* %y, align 4
+  %1 = load i32, i32* %z, align 4
   %call = call i32 @sum(i32 %0, i32 %1)
   store i32 %call, i32* %x, align 4
-  %2 = load i32* %x, align 4
+  %2 = load i32, i32* %x, align 4
   ret i32 %2
 }
 
diff --git a/test/CodeGen/Mips/micromips-load-effective-address.ll b/test/CodeGen/Mips/micromips-load-effective-address.ll
index afba760f0e62..470458098212 100644
--- a/test/CodeGen/Mips/micromips-load-effective-address.ll
+++ b/test/CodeGen/Mips/micromips-load-effective-address.ll
@@ -7,10 +7,10 @@ entry:
   %y.addr = alloca i32*, align 8
   store i32* %x, i32** %x.addr, align 8
   store i32* %y, i32** %y.addr, align 8
-  %0 = load i32** %x.addr, align 8
-  %1 = load i32* %0, align 4
-  %2 = load i32** %y.addr, align 8
-  %3 = load i32* %2, align 4
+  %0 = load i32*, i32** %x.addr, align 8
+  %1 = load i32, i32* %0, align 4
+  %2 = load i32*, i32** %y.addr, align 8
+  %3 = load i32, i32* %2, align 4
   %add = add nsw i32 %1, %3
   ret i32 %add
 }
diff --git a/test/CodeGen/Mips/micromips-not16.ll b/test/CodeGen/Mips/micromips-not16.ll
new file mode 100644
index 000000000000..d31aefae6f0d
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-not16.ll
@@ -0,0 +1,26 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %x = alloca i64, align 8
+  store i32 0, i32* %retval
+  %0 = load i64, i64* %x, align 8
+  %cmp = icmp ne i64 %0, 9223372036854775807
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  store i32 1, i32* %retval
+  br label %return
+
+if.end:
+  store i32 0, i32* %retval
+  br label %return
+
+return:
+  %1 = load i32, i32* %retval
+  ret i32 %1
+}
+
+; CHECK: not16
diff --git a/test/CodeGen/Mips/micromips-or16.ll b/test/CodeGen/Mips/micromips-or16.ll
new file mode 100644
index 000000000000..82ea9c687df4
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-or16.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32, i32* %b, align 4
+  %1 = load i32, i32* %c, align 4
+  %or = or i32 %0, %1
+  store i32 %or, i32* %a, align 4
+  ret i32 0
+}
+
+; CHECK: or16
diff --git a/test/CodeGen/Mips/micromips-rdhwr-directives.ll b/test/CodeGen/Mips/micromips-rdhwr-directives.ll
index af40a8796824..ebe4dddd0124 100644
--- a/test/CodeGen/Mips/micromips-rdhwr-directives.ll
+++ b/test/CodeGen/Mips/micromips-rdhwr-directives.ll
@@ -10,6 +10,6 @@ entry:
 ; CHECK: rdhwr
 ; CHECK: .set  pop
 
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   ret i32 %0
 }
diff --git a/test/CodeGen/Mips/micromips-shift.ll b/test/CodeGen/Mips/micromips-shift.ll
index 8215010bfc78..ed1bcbbf0831 100644
--- a/test/CodeGen/Mips/micromips-shift.ll
+++ b/test/CodeGen/Mips/micromips-shift.ll
@@ -8,11 +8,11 @@
 
 define i32 @shift_left() nounwind {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %shl = shl i32 %0, 4
   store i32 %shl, i32* @b, align 4
 
-  %1 = load i32* @c, align 4
+  %1 = load i32, i32* @c, align 4
   %shl1 = shl i32 %1, 10
   store i32 %shl1, i32* @d, align 4
 
@@ -29,11 +29,11 @@ entry:
 
 define i32 @shift_right() nounwind {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %shr = lshr i32 %0, 4
   store i32 %shr, i32* @j, align 4
 
-  %1 = load i32* @m, align 4
+  %1 = load i32, i32* @m, align 4
   %shr1 = lshr i32 %1, 10
   store i32 %shr1, i32* @n, align 4
 
diff --git a/test/CodeGen/Mips/micromips-subu16.ll b/test/CodeGen/Mips/micromips-subu16.ll
new file mode 100644
index 000000000000..d415574f443a
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-subu16.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32, i32* %b, align 4
+  %1 = load i32, i32* %c, align 4
+  %sub = sub nsw i32 %0, %1
+  store i32 %sub, i32* %a, align 4
+  ret i32 0
+}
+
+; CHECK: subu16
diff --git a/test/CodeGen/Mips/micromips-sw-lw-16.ll b/test/CodeGen/Mips/micromips-sw-lw-16.ll
new file mode 100644
index 000000000000..358372649b5d
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-sw-lw-16.ll
@@ -0,0 +1,27 @@
+; RUN: llc %s -march=mipsel -mattr=micromips -filetype=asm \
+; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
+
+; Function Attrs: noinline nounwind
+define void @bar(i32* %p) #0 {
+entry:
+  %p.addr = alloca i32*, align 4
+  store i32* %p, i32** %p.addr, align 4
+  %0 = load i32*, i32** %p.addr, align 4
+  %1 = load i32, i32* %0, align 4
+  %add = add nsw i32 7, %1
+  %2 = load i32*, i32** %p.addr, align 4
+  store i32 %add, i32* %2, align 4
+  %3 = load i32*, i32** %p.addr, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %3, i32 1
+  %4 = load i32, i32* %add.ptr, align 4
+  %add1 = add nsw i32 7, %4
+  %5 = load i32*, i32** %p.addr, align 4
+  %add.ptr2 = getelementptr inbounds i32, i32* %5, i32 1
+  store i32 %add1, i32* %add.ptr2, align 4
+  ret void
+}
+
+; CHECK: lw16 ${{[0-9]+}}, 0($4)
+; CHECK: sw16 ${{[0-9]+}}, 0($4)
+; CHECK: lw16 ${{[0-9]+}}, 4(${{[0-9]+}})
+; CHECK: sw16 ${{[0-9]+}}, 4(${{[0-9]+}})
diff --git a/test/CodeGen/Mips/micromips-xor16.ll b/test/CodeGen/Mips/micromips-xor16.ll
new file mode 100644
index 000000000000..53c75acd4d3b
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-xor16.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32, i32* %b, align 4
+  %1 = load i32, i32* %c, align 4
+  %xor = xor i32 %0, %1
+  store i32 %xor, i32* %a, align 4
+  ret i32 0
+}
+
+; CHECK: xor16
diff --git a/test/CodeGen/Mips/mips16_32_8.ll b/test/CodeGen/Mips/mips16_32_8.ll
index 2f5bc219cf35..5e03928a11f1 100644
--- a/test/CodeGen/Mips/mips16_32_8.ll
+++ b/test/CodeGen/Mips/mips16_32_8.ll
@@ -22,13 +22,13 @@ entry:
 define void @nofoo() #1 {
 entry:
   store i32 20, i32* @i, align 4
-  %0 = load float* @x, align 4
-  %1 = load float* @y, align 4
+  %0 = load float, float* @x, align 4
+  %1 = load float, float* @y, align 4
   %add = fadd float %0, %1
   store float %add, float* @f, align 4
-  %2 = load float* @f, align 4
+  %2 = load float, float* @f, align 4
   %conv = fpext float %2 to double
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), double %conv)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0), double %conv)
   ret void
 }
 
@@ -48,11 +48,11 @@ declare i32 @printf(i8*, ...) #2
 define i32 @main() #3 {
 entry:
   call void @foo()
-  %0 = load i32* @i, align 4
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str1, i32 0, i32 0), i32 %0)
+  %0 = load i32, i32* @i, align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str1, i32 0, i32 0), i32 %0)
   call void @nofoo()
-  %1 = load i32* @i, align 4
-  %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str2, i32 0, i32 0), i32 %1)
+  %1 = load i32, i32* @i, align 4
+  %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str2, i32 0, i32 0), i32 %1)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/mips16_fpret.ll b/test/CodeGen/Mips/mips16_fpret.ll
index fe87604d6107..0f09c4105a17 100644
--- a/test/CodeGen/Mips/mips16_fpret.ll
+++ b/test/CodeGen/Mips/mips16_fpret.ll
@@ -11,7 +11,7 @@
 
 define float @foox()  {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   ret float %0
 ; 1: 	.ent	foox
 ; 1:	lw	$2, %lo(x)(${{[0-9]+}})
@@ -20,7 +20,7 @@ entry:
 
 define double @foodx()  {
 entry:
-  %0 = load double* @dx, align 8
+  %0 = load double, double* @dx, align 8
   ret double %0
 ; 1: 	.ent	foodx
 ; 1: 	lw	$2, %lo(dx)(${{[0-9]+}})
@@ -34,13 +34,13 @@ entry:
 define { float, float } @foocx()  {
 entry:
   %retval = alloca { float, float }, align 4
-  %cx.real = load float* getelementptr inbounds ({ float, float }* @cx, i32 0, i32 0)
-  %cx.imag = load float* getelementptr inbounds ({ float, float }* @cx, i32 0, i32 1)
-  %real = getelementptr inbounds { float, float }* %retval, i32 0, i32 0
-  %imag = getelementptr inbounds { float, float }* %retval, i32 0, i32 1
+  %cx.real = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @cx, i32 0, i32 0)
+  %cx.imag = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @cx, i32 0, i32 1)
+  %real = getelementptr inbounds { float, float }, { float, float }* %retval, i32 0, i32 0
+  %imag = getelementptr inbounds { float, float }, { float, float }* %retval, i32 0, i32 1
   store float %cx.real, float* %real
   store float %cx.imag, float* %imag
-  %0 = load { float, float }* %retval
+  %0 = load { float, float }, { float, float }* %retval
   ret { float, float } %0
 ; 1: 	.ent	foocx
 ; 1: 	lw	$2, %lo(cx)(${{[0-9]+}})
@@ -53,13 +53,13 @@ entry:
 define { double, double } @foodcx()  {
 entry:
   %retval = alloca { double, double }, align 8
-  %dcx.real = load double* getelementptr inbounds ({ double, double }* @dcx, i32 0, i32 0)
-  %dcx.imag = load double* getelementptr inbounds ({ double, double }* @dcx, i32 0, i32 1)
-  %real = getelementptr inbounds { double, double }* %retval, i32 0, i32 0
-  %imag = getelementptr inbounds { double, double }* %retval, i32 0, i32 1
+  %dcx.real = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @dcx, i32 0, i32 0)
+  %dcx.imag = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @dcx, i32 0, i32 1)
+  %real = getelementptr inbounds { double, double }, { double, double }* %retval, i32 0, i32 0
+  %imag = getelementptr inbounds { double, double }, { double, double }* %retval, i32 0, i32 1
   store double %dcx.real, double* %real
   store double %dcx.imag, double* %imag
-  %0 = load { double, double }* %retval
+  %0 = load { double, double }, { double, double }* %retval
   ret { double, double } %0
 ; 1: 	.ent	foodcx
 ; 1: 	lw	${{[0-9]}}, %lo(dcx)(${{[0-9]+}})
diff --git a/test/CodeGen/Mips/mips16ex.ll b/test/CodeGen/Mips/mips16ex.ll
index a1a99191595d..68b584604b27 100644
--- a/test/CodeGen/Mips/mips16ex.ll
+++ b/test/CodeGen/Mips/mips16ex.ll
@@ -1,8 +1,10 @@
 ; RUN: llc  -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
 
-;16: .cfi_personality
+;16: main:
 ;16-NEXT: [[TMP:.*]]:
-;16-NEXT: $eh_func_begin0 = ([[TMP]])
+;16-NEXT: $func_begin0 = ([[TMP]])
+;16-NEXT: .cfi_startproc
+;16-NEXT: .cfi_personality
 @.str = private unnamed_addr constant [7 x i8] c"hello\0A\00", align 1
 @_ZTIi = external constant i8*
 @.str1 = private unnamed_addr constant [15 x i8] c"exception %i \0A\00", align 1
@@ -14,7 +16,7 @@ entry:
   %ehselector.slot = alloca i32
   %e = alloca i32, align 4
   store i32 0, i32* %retval
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0))
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0))
   %exception = call i8* @__cxa_allocate_exception(i32 4) nounwind
   %0 = bitcast i8* %exception to i32*
   store i32 20, i32* %0
@@ -31,19 +33,19 @@ lpad:                                             ; preds = %entry
   br label %catch.dispatch
 
 catch.dispatch:                                   ; preds = %lpad
-  %sel = load i32* %ehselector.slot
+  %sel = load i32, i32* %ehselector.slot
   %4 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) nounwind
   %matches = icmp eq i32 %sel, %4
   br i1 %matches, label %catch, label %eh.resume
 
 catch:                                            ; preds = %catch.dispatch
-  %exn = load i8** %exn.slot
+  %exn = load i8*, i8** %exn.slot
   %5 = call i8* @__cxa_begin_catch(i8* %exn) nounwind
   %6 = bitcast i8* %5 to i32*
-  %exn.scalar = load i32* %6
+  %exn.scalar = load i32, i32* %6
   store i32 %exn.scalar, i32* %e, align 4
-  %7 = load i32* %e, align 4
-  %call2 = invoke i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([15 x i8]* @.str1, i32 0, i32 0), i32 %7)
+  %7 = load i32, i32* %e, align 4
+  %call2 = invoke i32 (i8*, ...) @printf(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @.str1, i32 0, i32 0), i32 %7)
           to label %invoke.cont unwind label %lpad1
 
 invoke.cont:                                      ; preds = %catch
@@ -64,8 +66,8 @@ lpad1:                                            ; preds = %catch
   br label %eh.resume
 
 eh.resume:                                        ; preds = %lpad1, %catch.dispatch
-  %exn3 = load i8** %exn.slot
-  %sel4 = load i32* %ehselector.slot
+  %exn3 = load i8*, i8** %exn.slot
+  %sel4 = load i32, i32* %ehselector.slot
   %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn3, 0
   %lpad.val5 = insertvalue { i8*, i32 } %lpad.val, i32 %sel4, 1
   resume { i8*, i32 } %lpad.val5
diff --git a/test/CodeGen/Mips/mips16fpe.ll b/test/CodeGen/Mips/mips16fpe.ll
index 987980e080ff..f8b916da3a49 100644
--- a/test/CodeGen/Mips/mips16fpe.ll
+++ b/test/CodeGen/Mips/mips16fpe.ll
@@ -42,8 +42,8 @@
 define void @test_addsf3() nounwind {
 entry:
 ;16hf-LABEL: test_addsf3:
-  %0 = load float* @x, align 4
-  %1 = load float* @y, align 4
+  %0 = load float, float* @x, align 4
+  %1 = load float, float* @y, align 4
   %add = fadd float %0, %1
   store float %add, float* @addsf3_result, align 4
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_addsf3)(${{[0-9]+}})
@@ -53,8 +53,8 @@ entry:
 define void @test_adddf3() nounwind {
 entry:
 ;16hf-LABEL: test_adddf3:
-  %0 = load double* @xd, align 8
-  %1 = load double* @yd, align 8
+  %0 = load double, double* @xd, align 8
+  %1 = load double, double* @yd, align 8
   %add = fadd double %0, %1
   store double %add, double* @adddf3_result, align 8
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_adddf3)(${{[0-9]+}})
@@ -64,8 +64,8 @@ entry:
 define void @test_subsf3() nounwind {
 entry:
 ;16hf-LABEL: test_subsf3:
-  %0 = load float* @x, align 4
-  %1 = load float* @y, align 4
+  %0 = load float, float* @x, align 4
+  %1 = load float, float* @y, align 4
   %sub = fsub float %0, %1
   store float %sub, float* @subsf3_result, align 4
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_subsf3)(${{[0-9]+}})
@@ -75,8 +75,8 @@ entry:
 define void @test_subdf3() nounwind {
 entry:
 ;16hf-LABEL: test_subdf3:
-  %0 = load double* @xd, align 8
-  %1 = load double* @yd, align 8
+  %0 = load double, double* @xd, align 8
+  %1 = load double, double* @yd, align 8
   %sub = fsub double %0, %1
   store double %sub, double* @subdf3_result, align 8
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_subdf3)(${{[0-9]+}})
@@ -86,8 +86,8 @@ entry:
 define void @test_mulsf3() nounwind {
 entry:
 ;16hf-LABEL: test_mulsf3:
-  %0 = load float* @x, align 4
-  %1 = load float* @y, align 4
+  %0 = load float, float* @x, align 4
+  %1 = load float, float* @y, align 4
   %mul = fmul float %0, %1
   store float %mul, float* @mulsf3_result, align 4
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_mulsf3)(${{[0-9]+}})
@@ -97,8 +97,8 @@ entry:
 define void @test_muldf3() nounwind {
 entry:
 ;16hf-LABEL: test_muldf3:
-  %0 = load double* @xd, align 8
-  %1 = load double* @yd, align 8
+  %0 = load double, double* @xd, align 8
+  %1 = load double, double* @yd, align 8
   %mul = fmul double %0, %1
   store double %mul, double* @muldf3_result, align 8
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_muldf3)(${{[0-9]+}})
@@ -108,8 +108,8 @@ entry:
 define void @test_divsf3() nounwind {
 entry:
 ;16hf-LABEL: test_divsf3:
-  %0 = load float* @y, align 4
-  %1 = load float* @x, align 4
+  %0 = load float, float* @y, align 4
+  %1 = load float, float* @x, align 4
   %div = fdiv float %0, %1
   store float %div, float* @divsf3_result, align 4
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_divsf3)(${{[0-9]+}})
@@ -119,9 +119,9 @@ entry:
 define void @test_divdf3() nounwind {
 entry:
 ;16hf-LABEL: test_divdf3:
-  %0 = load double* @yd, align 8
+  %0 = load double, double* @yd, align 8
   %mul = fmul double %0, 2.000000e+00
-  %1 = load double* @xd, align 8
+  %1 = load double, double* @xd, align 8
   %div = fdiv double %mul, %1
   store double %div, double* @divdf3_result, align 8
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_divdf3)(${{[0-9]+}})
@@ -131,7 +131,7 @@ entry:
 define void @test_extendsfdf2() nounwind {
 entry:
 ;16hf-LABEL: test_extendsfdf2:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   %conv = fpext float %0 to double
   store double %conv, double* @extendsfdf2_result, align 8
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_extendsfdf2)(${{[0-9]+}})
@@ -141,7 +141,7 @@ entry:
 define void @test_truncdfsf2() nounwind {
 entry:
 ;16hf-LABEL: test_truncdfsf2:
-  %0 = load double* @xd2, align 8
+  %0 = load double, double* @xd2, align 8
   %conv = fptrunc double %0 to float
   store float %conv, float* @truncdfsf2_result, align 4
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_truncdfsf2)(${{[0-9]+}})
@@ -151,7 +151,7 @@ entry:
 define void @test_fix_truncsfsi() nounwind {
 entry:
 ;16hf-LABEL: test_fix_truncsfsi:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   %conv = fptosi float %0 to i32
   store i32 %conv, i32* @fix_truncsfsi_result, align 4
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_fix_truncsfsi)(${{[0-9]+}})
@@ -161,7 +161,7 @@ entry:
 define void @test_fix_truncdfsi() nounwind {
 entry:
 ;16hf-LABEL: test_fix_truncdfsi:
-  %0 = load double* @xd, align 8
+  %0 = load double, double* @xd, align 8
   %conv = fptosi double %0 to i32
   store i32 %conv, i32* @fix_truncdfsi_result, align 4
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_fix_truncdfsi)(${{[0-9]+}})
@@ -171,7 +171,7 @@ entry:
 define void @test_floatsisf() nounwind {
 entry:
 ;16hf-LABEL: test_floatsisf:
-  %0 = load i32* @si, align 4
+  %0 = load i32, i32* @si, align 4
   %conv = sitofp i32 %0 to float
   store float %conv, float* @floatsisf_result, align 4
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_floatsisf)(${{[0-9]+}})
@@ -181,7 +181,7 @@ entry:
 define void @test_floatsidf() nounwind {
 entry:
 ;16hf-LABEL: test_floatsidf:
-  %0 = load i32* @si, align 4
+  %0 = load i32, i32* @si, align 4
   %conv = sitofp i32 %0 to double
   store double %conv, double* @floatsidf_result, align 8
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_floatsidf)(${{[0-9]+}})
@@ -191,7 +191,7 @@ entry:
 define void @test_floatunsisf() nounwind {
 entry:
 ;16hf-LABEL: test_floatunsisf:
-  %0 = load i32* @ui, align 4
+  %0 = load i32, i32* @ui, align 4
   %conv = uitofp i32 %0 to float
   store float %conv, float* @floatunsisf_result, align 4
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_floatunsisf)(${{[0-9]+}})
@@ -201,7 +201,7 @@ entry:
 define void @test_floatunsidf() nounwind {
 entry:
 ;16hf-LABEL: test_floatunsidf:
-  %0 = load i32* @ui, align 4
+  %0 = load i32, i32* @ui, align 4
   %conv = uitofp i32 %0 to double
   store double %conv, double* @floatunsidf_result, align 8
 ;16hf:  lw	${{[0-9]+}}, %call16(__mips16_floatunsidf)(${{[0-9]+}})
@@ -211,8 +211,8 @@ entry:
 define void @test_eqsf2() nounwind {
 entry:
 ;16hf-LABEL: test_eqsf2:
-  %0 = load float* @x, align 4
-  %1 = load float* @xx, align 4
+  %0 = load float, float* @x, align 4
+  %1 = load float, float* @xx, align 4
   %cmp = fcmp oeq float %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @eqsf2_result, align 4
@@ -223,8 +223,8 @@ entry:
 define void @test_eqdf2() nounwind {
 entry:
 ;16hf-LABEL: test_eqdf2:
-  %0 = load double* @xd, align 8
-  %1 = load double* @xxd, align 8
+  %0 = load double, double* @xd, align 8
+  %1 = load double, double* @xxd, align 8
   %cmp = fcmp oeq double %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @eqdf2_result, align 4
@@ -235,8 +235,8 @@ entry:
 define void @test_nesf2() nounwind {
 entry:
 ;16hf-LABEL: test_nesf2:
-  %0 = load float* @x, align 4
-  %1 = load float* @y, align 4
+  %0 = load float, float* @x, align 4
+  %1 = load float, float* @y, align 4
   %cmp = fcmp une float %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @nesf2_result, align 4
@@ -247,8 +247,8 @@ entry:
 define void @test_nedf2() nounwind {
 entry:
 ;16hf-LABEL: test_nedf2:
-  %0 = load double* @xd, align 8
-  %1 = load double* @yd, align 8
+  %0 = load double, double* @xd, align 8
+  %1 = load double, double* @yd, align 8
   %cmp = fcmp une double %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @nedf2_result, align 4
@@ -259,10 +259,10 @@ entry:
 define void @test_gesf2() nounwind {
 entry:
 ;16hf-LABEL: test_gesf2:
-  %0 = load float* @x, align 4
-  %1 = load float* @xx, align 4
+  %0 = load float, float* @x, align 4
+  %1 = load float, float* @xx, align 4
   %cmp = fcmp oge float %0, %1
-  %2 = load float* @y, align 4
+  %2 = load float, float* @y, align 4
   %cmp1 = fcmp oge float %2, %0
   %and3 = and i1 %cmp, %cmp1
   %and = zext i1 %and3 to i32
@@ -274,10 +274,10 @@ entry:
 define void @test_gedf2() nounwind {
 entry:
 ;16hf-LABEL: test_gedf2:
-  %0 = load double* @xd, align 8
-  %1 = load double* @xxd, align 8
+  %0 = load double, double* @xd, align 8
+  %1 = load double, double* @xxd, align 8
   %cmp = fcmp oge double %0, %1
-  %2 = load double* @yd, align 8
+  %2 = load double, double* @yd, align 8
   %cmp1 = fcmp oge double %2, %0
   %and3 = and i1 %cmp, %cmp1
   %and = zext i1 %and3 to i32
@@ -289,10 +289,10 @@ entry:
 define void @test_ltsf2() nounwind {
 entry:
 ;16hf-LABEL: test_ltsf2:
-  %0 = load float* @x, align 4
-  %1 = load float* @xx, align 4
+  %0 = load float, float* @x, align 4
+  %1 = load float, float* @xx, align 4
   %lnot = fcmp uge float %0, %1
-  %2 = load float* @y, align 4
+  %2 = load float, float* @y, align 4
   %cmp1 = fcmp olt float %0, %2
   %and2 = and i1 %lnot, %cmp1
   %and = zext i1 %and2 to i32
@@ -305,10 +305,10 @@ entry:
 define void @test_ltdf2() nounwind {
 entry:
 ;16hf-LABEL: test_ltdf2:
-  %0 = load double* @xd, align 8
-  %1 = load double* @xxd, align 8
+  %0 = load double, double* @xd, align 8
+  %1 = load double, double* @xxd, align 8
   %lnot = fcmp uge double %0, %1
-  %2 = load double* @yd, align 8
+  %2 = load double, double* @yd, align 8
   %cmp1 = fcmp olt double %0, %2
   %and2 = and i1 %lnot, %cmp1
   %and = zext i1 %and2 to i32
@@ -321,10 +321,10 @@ entry:
 define void @test_lesf2() nounwind {
 entry:
 ;16hf-LABEL: test_lesf2:
-  %0 = load float* @x, align 4
-  %1 = load float* @xx, align 4
+  %0 = load float, float* @x, align 4
+  %1 = load float, float* @xx, align 4
   %cmp = fcmp ole float %0, %1
-  %2 = load float* @y, align 4
+  %2 = load float, float* @y, align 4
   %cmp1 = fcmp ole float %0, %2
   %and3 = and i1 %cmp, %cmp1
   %and = zext i1 %and3 to i32
@@ -336,10 +336,10 @@ entry:
 define void @test_ledf2() nounwind {
 entry:
 ;16hf-LABEL: test_ledf2:
-  %0 = load double* @xd, align 8
-  %1 = load double* @xxd, align 8
+  %0 = load double, double* @xd, align 8
+  %1 = load double, double* @xxd, align 8
   %cmp = fcmp ole double %0, %1
-  %2 = load double* @yd, align 8
+  %2 = load double, double* @yd, align 8
   %cmp1 = fcmp ole double %0, %2
   %and3 = and i1 %cmp, %cmp1
   %and = zext i1 %and3 to i32
@@ -351,10 +351,10 @@ entry:
 define void @test_gtsf2() nounwind {
 entry:
 ;16hf-LABEL: test_gtsf2:
-  %0 = load float* @x, align 4
-  %1 = load float* @xx, align 4
+  %0 = load float, float* @x, align 4
+  %1 = load float, float* @xx, align 4
   %lnot = fcmp ule float %0, %1
-  %2 = load float* @y, align 4
+  %2 = load float, float* @y, align 4
   %cmp1 = fcmp ogt float %2, %0
   %and2 = and i1 %lnot, %cmp1
   %and = zext i1 %and2 to i32
@@ -366,10 +366,10 @@ entry:
 define void @test_gtdf2() nounwind {
 entry:
 ;16hf-LABEL: test_gtdf2:
-  %0 = load double* @xd, align 8
-  %1 = load double* @xxd, align 8
+  %0 = load double, double* @xd, align 8
+  %1 = load double, double* @xxd, align 8
   %lnot = fcmp ule double %0, %1
-  %2 = load double* @yd, align 8
+  %2 = load double, double* @yd, align 8
   %cmp1 = fcmp ogt double %2, %0
   %and2 = and i1 %lnot, %cmp1
   %and = zext i1 %and2 to i32
diff --git a/test/CodeGen/Mips/mips64-f128-call.ll b/test/CodeGen/Mips/mips64-f128-call.ll
index 455e540e5df1..9a093e6f9825 100644
--- a/test/CodeGen/Mips/mips64-f128-call.ll
+++ b/test/CodeGen/Mips/mips64-f128-call.ll
@@ -19,7 +19,7 @@ entry:
 
 define void @foo1() {
 entry:
-  %0 = load fp128* @gld0, align 16
+  %0 = load fp128, fp128* @gld0, align 16
   tail call void @foo2(fp128 %0)
   ret void
 }
@@ -38,7 +38,7 @@ define fp128 @foo3() {
 entry:
   %call = tail call fp128 @foo4()
   store fp128 %call, fp128* @gld0, align 16
-  %0 = load fp128* @gld1, align 16
+  %0 = load fp128, fp128* @gld1, align 16
   ret fp128 %0
 }
 
diff --git a/test/CodeGen/Mips/mips64-f128.ll b/test/CodeGen/Mips/mips64-f128.ll
index f0cbbd08d79a..d9c93810438f 100644
--- a/test/CodeGen/Mips/mips64-f128.ll
+++ b/test/CodeGen/Mips/mips64-f128.ll
@@ -1,10 +1,10 @@
-; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips4 -soft-float -O1 \
+; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips4 -mattr=+soft-float -O1 \
 ; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT
-; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64 -soft-float -O1 \
+; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64 -mattr=+soft-float -O1 \
 ; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT
-; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r2 -soft-float -O1 \
+; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r2 -mattr=+soft-float -O1 \
 ; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT
-; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r6 -soft-float -O1 \
+; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r6 -mattr=+soft-float -O1 \
 ; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=CMP_CC_FMT
 
 @gld0 = external global fp128
@@ -18,8 +18,8 @@
 
 define fp128 @addLD() {
 entry:
-  %0 = load fp128* @gld0, align 16
-  %1 = load fp128* @gld1, align 16
+  %0 = load fp128, fp128* @gld0, align 16
+  %1 = load fp128, fp128* @gld1, align 16
   %add = fadd fp128 %0, %1
   ret fp128 %add
 }
@@ -29,8 +29,8 @@ entry:
 
 define fp128 @subLD() {
 entry:
-  %0 = load fp128* @gld0, align 16
-  %1 = load fp128* @gld1, align 16
+  %0 = load fp128, fp128* @gld0, align 16
+  %1 = load fp128, fp128* @gld1, align 16
   %sub = fsub fp128 %0, %1
   ret fp128 %sub
 }
@@ -40,8 +40,8 @@ entry:
 
 define fp128 @mulLD() {
 entry:
-  %0 = load fp128* @gld0, align 16
-  %1 = load fp128* @gld1, align 16
+  %0 = load fp128, fp128* @gld0, align 16
+  %1 = load fp128, fp128* @gld1, align 16
   %mul = fmul fp128 %0, %1
   ret fp128 %mul
 }
@@ -51,8 +51,8 @@ entry:
 
 define fp128 @divLD() {
 entry:
-  %0 = load fp128* @gld0, align 16
-  %1 = load fp128* @gld1, align 16
+  %0 = load fp128, fp128* @gld0, align 16
+  %1 = load fp128, fp128* @gld1, align 16
   %div = fdiv fp128 %0, %1
   ret fp128 %div
 }
@@ -247,7 +247,7 @@ entry:
 
 define fp128 @libcall1_fabsl() {
 entry:
-  %0 = load fp128* @gld0, align 16
+  %0 = load fp128, fp128* @gld0, align 16
   %call = tail call fp128 @fabsl(fp128 %0) nounwind readnone
   ret fp128 %call
 }
@@ -259,7 +259,7 @@ declare fp128 @fabsl(fp128) #1
 
 define fp128 @libcall1_ceill() {
 entry:
-  %0 = load fp128* @gld0, align 16
+  %0 = load fp128, fp128* @gld0, align 16
   %call = tail call fp128 @ceill(fp128 %0) nounwind readnone
   ret fp128 %call
 }
@@ -271,7 +271,7 @@ declare fp128 @ceill(fp128) #1
 
 define fp128 @libcall1_sinl() {
 entry:
-  %0 = load fp128* @gld0, align 16
+  %0 = load fp128, fp128* @gld0, align 16
   %call = tail call fp128 @sinl(fp128 %0) nounwind
   ret fp128 %call
 }
@@ -283,7 +283,7 @@ declare fp128 @sinl(fp128) #2
 
 define fp128 @libcall1_cosl() {
 entry:
-  %0 = load fp128* @gld0, align 16
+  %0 = load fp128, fp128* @gld0, align 16
   %call = tail call fp128 @cosl(fp128 %0) nounwind
   ret fp128 %call
 }
@@ -295,7 +295,7 @@ declare fp128 @cosl(fp128) #2
 
 define fp128 @libcall1_expl() {
 entry:
-  %0 = load fp128* @gld0, align 16
+  %0 = load fp128, fp128* @gld0, align 16
   %call = tail call fp128 @expl(fp128 %0) nounwind
   ret fp128 %call
 }
@@ -307,7 +307,7 @@ declare fp128 @expl(fp128) #2
 
 define fp128 @libcall1_exp2l() {
 entry:
-  %0 = load fp128* @gld0, align 16
+  %0 = load fp128, fp128* @gld0, align 16
   %call = tail call fp128 @exp2l(fp128 %0) nounwind
   ret fp128 %call
 }
@@ -319,7 +319,7 @@ declare fp128 @exp2l(fp128) #2
 
 define fp128 @libcall1_logl() {
 entry:
-  %0 = load fp128* @gld0, align 16
+  %0 = load fp128, fp128* @gld0, align 16
   %call = tail call fp128 @logl(fp128 %0) nounwind
   ret fp128 %call
 }
@@ -331,7 +331,7 @@ declare fp128 @logl(fp128) #2
 
 define fp128 @libcall1_log2l() {
 entry:
-  %0 = load fp128* @gld0, align 16
+  %0 = load fp128, fp128* @gld0, align 16
   %call = tail call fp128 @log2l(fp128 %0) nounwind
   ret fp128 %call
 }
@@ -343,7 +343,7 @@ declare fp128 @log2l(fp128) #2
 
 define fp128 @libcall1_log10l() {
 entry:
-  %0 = load fp128* @gld0, align 16
+  %0 = load fp128, fp128* @gld0, align 16
   %call = tail call fp128 @log10l(fp128 %0) nounwind
   ret fp128 %call
 }
@@ -355,7 +355,7 @@ declare fp128 @log10l(fp128) #2
 
 define fp128 @libcall1_nearbyintl() {
 entry:
-  %0 = load fp128* @gld0, align 16
+  %0 = load fp128, fp128* @gld0, align 16
   %call = tail call fp128 @nearbyintl(fp128 %0) nounwind readnone
   ret fp128 %call
 }
@@ -367,7 +367,7 @@ declare fp128 @nearbyintl(fp128) #1
 
 define fp128 @libcall1_floorl() {
 entry:
-  %0 = load fp128* @gld0, align 16
+  %0 = load fp128, fp128* @gld0, align 16
   %call = tail call fp128 @floorl(fp128 %0) nounwind readnone
   ret fp128 %call
 }
@@ -379,7 +379,7 @@ declare fp128 @floorl(fp128) #1
 
 define fp128 @libcall1_sqrtl() {
 entry:
-  %0 = load fp128* @gld0, align 16
+  %0 = load fp128, fp128* @gld0, align 16
   %call = tail call fp128 @sqrtl(fp128 %0) nounwind
   ret fp128 %call
 }
@@ -391,7 +391,7 @@ declare fp128 @sqrtl(fp128) #2
 
 define fp128 @libcall1_rintl() {
 entry:
-  %0 = load fp128* @gld0, align 16
+  %0 = load fp128, fp128* @gld0, align 16
   %call = tail call fp128 @rintl(fp128 %0) nounwind readnone
   ret fp128 %call
 }
@@ -424,8 +424,8 @@ declare fp128 @llvm.powi.f128(fp128, i32) #3
 
 define fp128 @libcall2_copysignl() {
 entry:
-  %0 = load fp128* @gld0, align 16
-  %1 = load fp128* @gld1, align 16
+  %0 = load fp128, fp128* @gld0, align 16
+  %1 = load fp128, fp128* @gld1, align 16
   %call = tail call fp128 @copysignl(fp128 %0, fp128 %1) nounwind readnone
   ret fp128 %call
 }
@@ -437,8 +437,8 @@ declare fp128 @copysignl(fp128, fp128) #1
 
 define fp128 @libcall2_powl() {
 entry:
-  %0 = load fp128* @gld0, align 16
-  %1 = load fp128* @gld1, align 16
+  %0 = load fp128, fp128* @gld0, align 16
+  %1 = load fp128, fp128* @gld1, align 16
   %call = tail call fp128 @powl(fp128 %0, fp128 %1) nounwind
   ret fp128 %call
 }
@@ -450,8 +450,8 @@ declare fp128 @powl(fp128, fp128) #2
 
 define fp128 @libcall2_fmodl() {
 entry:
-  %0 = load fp128* @gld0, align 16
-  %1 = load fp128* @gld1, align 16
+  %0 = load fp128, fp128* @gld0, align 16
+  %1 = load fp128, fp128* @gld1, align 16
   %call = tail call fp128 @fmodl(fp128 %0, fp128 %1) nounwind
   ret fp128 %call
 }
@@ -463,9 +463,9 @@ declare fp128 @fmodl(fp128, fp128) #2
 
 define fp128 @libcall3_fmal() {
 entry:
-  %0 = load fp128* @gld0, align 16
-  %1 = load fp128* @gld2, align 16
-  %2 = load fp128* @gld1, align 16
+  %0 = load fp128, fp128* @gld0, align 16
+  %1 = load fp128, fp128* @gld2, align 16
+  %2 = load fp128, fp128* @gld1, align 16
   %3 = tail call fp128 @llvm.fma.f128(fp128 %0, fp128 %2, fp128 %1)
   ret fp128 %3
 }
@@ -539,7 +539,7 @@ entry:
 
 define fp128 @load_LD_LD() {
 entry:
-  %0 = load fp128* @gld1, align 16
+  %0 = load fp128, fp128* @gld1, align 16
   ret fp128 %0
 }
 
@@ -551,7 +551,7 @@ entry:
 
 define fp128 @load_LD_float() {
 entry:
-  %0 = load float* @gf1, align 4
+  %0 = load float, float* @gf1, align 4
   %conv = fpext float %0 to fp128
   ret fp128 %conv
 }
@@ -564,7 +564,7 @@ entry:
 
 define fp128 @load_LD_double() {
 entry:
-  %0 = load double* @gd1, align 8
+  %0 = load double, double* @gd1, align 8
   %conv = fpext double %0 to fp128
   ret fp128 %conv
 }
@@ -579,7 +579,7 @@ entry:
 
 define void @store_LD_LD() {
 entry:
-  %0 = load fp128* @gld1, align 16
+  %0 = load fp128, fp128* @gld1, align 16
   store fp128 %0, fp128* @gld0, align 16
   ret void
 }
@@ -595,7 +595,7 @@ entry:
 
 define void @store_LD_float() {
 entry:
-  %0 = load fp128* @gld1, align 16
+  %0 = load fp128, fp128* @gld1, align 16
   %conv = fptrunc fp128 %0 to float
   store float %conv, float* @gf1, align 4
   ret void
@@ -612,7 +612,7 @@ entry:
 
 define void @store_LD_double() {
 entry:
-  %0 = load fp128* @gld1, align 16
+  %0 = load fp128, fp128* @gld1, align 16
   %conv = fptrunc fp128 %0 to double
   store double %conv, double* @gd1, align 8
   ret void
diff --git a/test/CodeGen/Mips/mips64-libcall.ll b/test/CodeGen/Mips/mips64-libcall.ll
index 290baafd18b9..8512e9fcb72e 100644
--- a/test/CodeGen/Mips/mips64-libcall.ll
+++ b/test/CodeGen/Mips/mips64-libcall.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=mips64el -mcpu=mips64r2 -O3 < %s |\
 ; RUN: FileCheck %s -check-prefix=HARD
-; RUN: llc -march=mips64el -mcpu=mips64r2 -soft-float < %s |\
+; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+soft-float < %s |\
 ; RUN: FileCheck %s -check-prefix=SOFT
 
 ; Check that %add is not passed in an integer register.
diff --git a/test/CodeGen/Mips/mips64-sret.ll b/test/CodeGen/Mips/mips64-sret.ll
index ed494e965b7d..0559747f62cc 100644
--- a/test/CodeGen/Mips/mips64-sret.ll
+++ b/test/CodeGen/Mips/mips64-sret.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s
 
 define void @foo(i32* noalias sret %agg.result) nounwind {
 entry:
diff --git a/test/CodeGen/Mips/mips64directive.ll b/test/CodeGen/Mips/mips64directive.ll
index 3d95f519bc64..b1052f77f5a8 100644
--- a/test/CodeGen/Mips/mips64directive.ll
+++ b/test/CodeGen/Mips/mips64directive.ll
@@ -1,12 +1,12 @@
-; RUN: llc  < %s -march=mips64el -mcpu=mips4 -mattr=n64 | FileCheck %s
-; RUN: llc  < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s
+; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s
 
 @gl = global i64 1250999896321, align 8
 
 ; CHECK: 8byte
 define i64 @foo1() nounwind readonly {
 entry:
-  %0 = load i64* @gl, align 8
+  %0 = load i64, i64* @gl, align 8
   ret i64 %0
 }
 
diff --git a/test/CodeGen/Mips/mips64ext.ll b/test/CodeGen/Mips/mips64ext.ll
index 22ea0eb7769c..9c1243b8f18c 100644
--- a/test/CodeGen/Mips/mips64ext.ll
+++ b/test/CodeGen/Mips/mips64ext.ll
@@ -1,5 +1,5 @@
-; RUN: llc  < %s -march=mips64el -mcpu=mips4 -mattr=n64 | FileCheck %s
-; RUN: llc  < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s
+; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s
 
 define i64 @zext64_32(i32 %a) nounwind readnone {
 entry:
diff --git a/test/CodeGen/Mips/mips64extins.ll b/test/CodeGen/Mips/mips64extins.ll
index 14f92ca86947..211cd5f8e7fd 100644
--- a/test/CodeGen/Mips/mips64extins.ll
+++ b/test/CodeGen/Mips/mips64extins.ll
@@ -1,4 +1,4 @@
-; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s 
+; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s 
 
 define i64 @dext(i64 %i) nounwind readnone {
 entry:
diff --git a/test/CodeGen/Mips/mips64fpimm0.ll b/test/CodeGen/Mips/mips64fpimm0.ll
index 19e076d1ecda..0296cb523f98 100644
--- a/test/CodeGen/Mips/mips64fpimm0.ll
+++ b/test/CodeGen/Mips/mips64fpimm0.ll
@@ -1,5 +1,5 @@
-; RUN: llc  < %s -march=mips64el -mcpu=mips4 -mattr=n64 | FileCheck %s
-; RUN: llc  < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s
+; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s
 
 define double @foo1() nounwind readnone {
 entry:
diff --git a/test/CodeGen/Mips/mips64fpldst.ll b/test/CodeGen/Mips/mips64fpldst.ll
index 2f42270b645d..55d5c775cbba 100644
--- a/test/CodeGen/Mips/mips64fpldst.ll
+++ b/test/CodeGen/Mips/mips64fpldst.ll
@@ -1,7 +1,7 @@
-; RUN: llc  < %s -march=mips64el -mcpu=mips4 -mattr=-n64,n64 | FileCheck %s -check-prefix=CHECK-N64
-; RUN: llc  < %s -march=mips64el -mcpu=mips4 -mattr=-n64,n32 | FileCheck %s -check-prefix=CHECK-N32
-; RUN: llc  < %s -march=mips64el -mcpu=mips64 -mattr=-n64,n64 | FileCheck %s -check-prefix=CHECK-N64
-; RUN: llc  < %s -march=mips64el -mcpu=mips64 -mattr=-n64,n32 | FileCheck %s -check-prefix=CHECK-N32
+; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi n64 | FileCheck %s -check-prefix=CHECK-N64
+; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi n32 | FileCheck %s -check-prefix=CHECK-N32
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi n64 | FileCheck %s -check-prefix=CHECK-N64
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi n32 | FileCheck %s -check-prefix=CHECK-N32
 
 @f0 = common global float 0.000000e+00, align 4
 @d0 = common global double 0.000000e+00, align 8
@@ -16,7 +16,7 @@ entry:
 ; CHECK-N32: funcfl1
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0)
 ; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]]) 
-  %0 = load float* @f0, align 4
+  %0 = load float, float* @f0, align 4
   ret float %0
 }
 
@@ -28,7 +28,7 @@ entry:
 ; CHECK-N32: funcfl2
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0)
 ; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]]) 
-  %0 = load double* @d0, align 8 
+  %0 = load double, double* @d0, align 8 
   ret double %0
 }
 
@@ -40,7 +40,7 @@ entry:
 ; CHECK-N32: funcfs1
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0)
 ; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]]) 
-  %0 = load float* @f1, align 4 
+  %0 = load float, float* @f1, align 4 
   store float %0, float* @f0, align 4 
   ret void
 }
@@ -53,7 +53,7 @@ entry:
 ; CHECK-N32: funcfs2
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0)
 ; CHECK-N32: sdc1 $f{{[0-9]+}}, 0($[[R0]]) 
-  %0 = load double* @d1, align 8 
+  %0 = load double, double* @d1, align 8 
   store double %0, double* @d0, align 8 
   ret void
 }
diff --git a/test/CodeGen/Mips/mips64instrs.ll b/test/CodeGen/Mips/mips64instrs.ll
index ed617be6532e..d64cdceb6b81 100644
--- a/test/CodeGen/Mips/mips64instrs.ll
+++ b/test/CodeGen/Mips/mips64instrs.ll
@@ -123,8 +123,8 @@ entry:
 ; GPRMULDIV:     ddiv $2, $[[T0]], $[[T1]]
 ; GPRMULDIV:     teq $[[T1]], $zero, 7
 
-  %0 = load i64* @gll0, align 8
-  %1 = load i64* @gll1, align 8
+  %0 = load i64, i64* @gll0, align 8
+  %1 = load i64, i64* @gll1, align 8
   %div = sdiv i64 %0, %1
   ret i64 %div
 }
@@ -144,8 +144,8 @@ entry:
 ; GPRMULDIV:     ddivu $2, $[[T0]], $[[T1]]
 ; GPRMULDIV:     teq $[[T1]], $zero, 7
 
-  %0 = load i64* @gll0, align 8
-  %1 = load i64* @gll1, align 8
+  %0 = load i64, i64* @gll0, align 8
+  %1 = load i64, i64* @gll1, align 8
   %div = udiv i64 %0, %1
   ret i64 %div
 }
diff --git a/test/CodeGen/Mips/mips64intldst.ll b/test/CodeGen/Mips/mips64intldst.ll
index c3607baeefeb..658ab88481c4 100644
--- a/test/CodeGen/Mips/mips64intldst.ll
+++ b/test/CodeGen/Mips/mips64intldst.ll
@@ -1,7 +1,7 @@
-; RUN: llc  < %s -march=mips64el -mcpu=mips4 -mattr=-n64,n64 | FileCheck %s -check-prefix=CHECK-N64
-; RUN: llc  < %s -march=mips64el -mcpu=mips4 -mattr=-n64,n32 | FileCheck %s -check-prefix=CHECK-N32
-; RUN: llc  < %s -march=mips64el -mcpu=mips64 -mattr=-n64,n64 | FileCheck %s -check-prefix=CHECK-N64
-; RUN: llc  < %s -march=mips64el -mcpu=mips64 -mattr=-n64,n32 | FileCheck %s -check-prefix=CHECK-N32
+; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi n64 | FileCheck %s -check-prefix=CHECK-N64
+; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi n32 | FileCheck %s -check-prefix=CHECK-N32
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi n64 | FileCheck %s -check-prefix=CHECK-N64
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi n32 | FileCheck %s -check-prefix=CHECK-N32
 
 @c = common global i8 0, align 4
 @s = common global i16 0, align 4
@@ -20,7 +20,7 @@ entry:
 ; CHECK-N32: func1
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(c)
 ; CHECK-N32: lb ${{[0-9]+}}, 0($[[R0]])
-  %0 = load i8* @c, align 4
+  %0 = load i8, i8* @c, align 4
   %conv = sext i8 %0 to i64
   ret i64 %conv
 }
@@ -33,7 +33,7 @@ entry:
 ; CHECK-N32: func2
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(s)
 ; CHECK-N32: lh ${{[0-9]+}}, 0($[[R0]])
-  %0 = load i16* @s, align 4
+  %0 = load i16, i16* @s, align 4
   %conv = sext i16 %0 to i64
   ret i64 %conv
 }
@@ -46,7 +46,7 @@ entry:
 ; CHECK-N32: func3
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(i)
 ; CHECK-N32: lw ${{[0-9]+}}, 0($[[R0]])
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
@@ -59,7 +59,7 @@ entry:
 ; CHECK-N32: func4
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(l)
 ; CHECK-N32: ld ${{[0-9]+}}, 0($[[R0]])
-  %0 = load i64* @l, align 8
+  %0 = load i64, i64* @l, align 8
   ret i64 %0
 }
 
@@ -71,7 +71,7 @@ entry:
 ; CHECK-N32: ufunc1
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(uc)
 ; CHECK-N32: lbu ${{[0-9]+}}, 0($[[R0]])
-  %0 = load i8* @uc, align 4
+  %0 = load i8, i8* @uc, align 4
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
@@ -84,7 +84,7 @@ entry:
 ; CHECK-N32: ufunc2
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(us)
 ; CHECK-N32: lhu ${{[0-9]+}}, 0($[[R0]])
-  %0 = load i16* @us, align 4
+  %0 = load i16, i16* @us, align 4
   %conv = zext i16 %0 to i64
   ret i64 %conv
 }
@@ -97,7 +97,7 @@ entry:
 ; CHECK-N32: ufunc3
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(ui)
 ; CHECK-N32: lwu ${{[0-9]+}}, 0($[[R0]])
-  %0 = load i32* @ui, align 4
+  %0 = load i32, i32* @ui, align 4
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
@@ -110,7 +110,7 @@ entry:
 ; CHECK-N32: sfunc1
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(c)
 ; CHECK-N32: sb ${{[0-9]+}}, 0($[[R0]])
-  %0 = load i64* @l1, align 8
+  %0 = load i64, i64* @l1, align 8
   %conv = trunc i64 %0 to i8
   store i8 %conv, i8* @c, align 4
   ret void
@@ -124,7 +124,7 @@ entry:
 ; CHECK-N32: sfunc2
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(s)
 ; CHECK-N32: sh ${{[0-9]+}}, 0($[[R0]])
-  %0 = load i64* @l1, align 8
+  %0 = load i64, i64* @l1, align 8
   %conv = trunc i64 %0 to i16
   store i16 %conv, i16* @s, align 4
   ret void
@@ -138,7 +138,7 @@ entry:
 ; CHECK-N32: sfunc3
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(i)
 ; CHECK-N32: sw ${{[0-9]+}}, 0($[[R0]])
-  %0 = load i64* @l1, align 8
+  %0 = load i64, i64* @l1, align 8
   %conv = trunc i64 %0 to i32
   store i32 %conv, i32* @i, align 4
   ret void
@@ -152,7 +152,7 @@ entry:
 ; CHECK-N32: sfunc4
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(l)
 ; CHECK-N32: sd ${{[0-9]+}}, 0($[[R0]])
-  %0 = load i64* @l1, align 8
+  %0 = load i64, i64* @l1, align 8
   store i64 %0, i64* @l, align 8
   ret void
 }
diff --git a/test/CodeGen/Mips/mips64shift.ll b/test/CodeGen/Mips/mips64shift.ll
index 45d1c9532276..52c6f9066392 100644
--- a/test/CodeGen/Mips/mips64shift.ll
+++ b/test/CodeGen/Mips/mips64shift.ll
@@ -65,7 +65,8 @@ entry:
 
 define i64 @f9(i64 %a0, i64 %a1) nounwind readnone {
 entry:
-; CHECK: drotrv
+; CHECK-NOT:  sll
+; CHECK:      drotrv
   %shr = lshr i64 %a0, %a1
   %sub = sub i64 64, %a1
   %shl = shl i64 %a0, %sub
@@ -75,7 +76,8 @@ entry:
 
 define i64 @f10(i64 %a0, i64 %a1) nounwind readnone {
 entry:
-; CHECK: drotrv
+; CHECK-NOT:  sll
+; CHECK:      drotrv
   %shl = shl i64 %a0, %a1
   %sub = sub i64 64, %a1
   %shr = lshr i64 %a0, %sub
diff --git a/test/CodeGen/Mips/mips64signextendsesf.ll b/test/CodeGen/Mips/mips64signextendsesf.ll
index dec83b80afea..d0ce1b86bf56 100644
--- a/test/CodeGen/Mips/mips64signextendsesf.ll
+++ b/test/CodeGen/Mips/mips64signextendsesf.ll
@@ -1,11 +1,11 @@
-; RUN: llc -march=mips64 -mcpu=mips64r2 -soft-float -O2 < %s | FileCheck %s
+; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+soft-float -O2 < %s | FileCheck %s
 
 define void @foosf() #0 {
 entry:
   %in = alloca float, align 4
   %out = alloca float, align 4
   store volatile float 0xBFD59E1380000000, float* %in, align 4
-  %in.0.in.0. = load volatile float* %in, align 4
+  %in.0.in.0. = load volatile float, float* %in, align 4
   %rintf = tail call float @rintf(float %in.0.in.0.) #1
   store volatile float %rintf, float* %out, align 4
   ret void
@@ -20,7 +20,7 @@ declare float @rintf(float)
 
 define float @foosf1(float* nocapture readonly %a) #0 {
 entry:
-  %0 = load float* %a, align 4
+  %0 = load float, float* %a, align 4
   %call = tail call float @roundf(float %0) #2
   ret float %call
 
@@ -34,7 +34,7 @@ declare float @roundf(float) #1
 
 define float @foosf2(float* nocapture readonly %a) #0 {
 entry:
-  %0 = load float* %a, align 4
+  %0 = load float, float* %a, align 4
   %call = tail call float @truncf(float %0) #2
   ret float %call
 
@@ -48,7 +48,7 @@ declare float @truncf(float) #1
 
 define float @foosf3(float* nocapture readonly %a) #0 {
 entry:
-  %0 = load float* %a, align 4
+  %0 = load float, float* %a, align 4
   %call = tail call float @floorf(float %0) #2
   ret float %call
 
@@ -62,7 +62,7 @@ declare float @floorf(float) #1
 
 define float @foosf4(float* nocapture readonly %a) #0 {
 entry:
-  %0 = load float* %a, align 4
+  %0 = load float, float* %a, align 4
   %call = tail call float @nearbyintf(float %0) #2
   ret float %call
 
@@ -76,7 +76,7 @@ declare float @nearbyintf(float) #1
 
 define float @foosf5(float* nocapture readonly %a) #0 {
 entry:
-  %0 = load float* %a, align 4
+  %0 = load float, float* %a, align 4
   %mul = fmul float %0, undef
   ret float %mul
 
@@ -88,7 +88,7 @@ entry:
 
 define float @foosf6(float* nocapture readonly %a) #0 {
 entry:
-  %0 = load float* %a, align 4
+  %0 = load float, float* %a, align 4
   %sub = fsub float %0, undef
   ret float %sub
 
@@ -100,7 +100,7 @@ entry:
 
 define float @foosf7(float* nocapture readonly %a) #0 {
 entry:
-  %0 = load float* %a, align 4
+  %0 = load float, float* %a, align 4
   %add = fadd float %0, undef
   ret float %add
 
@@ -113,8 +113,8 @@ entry:
 define float @foosf8(float* nocapture readonly %a) #0 {
 entry:
   %b = alloca float, align 4
-  %b.0.b.0. = load volatile float* %b, align 4
-  %0 = load float* %a, align 4
+  %b.0.b.0. = load volatile float, float* %b, align 4
+  %0 = load float, float* %a, align 4
   %div = fdiv float %b.0.b.0., %0
   ret float %div
 
@@ -127,9 +127,9 @@ entry:
 define float @foosf9() #0 {
 entry:
   %b = alloca float, align 4
-  %b.0.b.0. = load volatile float* %b, align 4
+  %b.0.b.0. = load volatile float, float* %b, align 4
   %conv = fpext float %b.0.b.0. to double
-  %b.0.b.0.3 = load volatile float* %b, align 4
+  %b.0.b.0.3 = load volatile float, float* %b, align 4
   %conv1 = fpext float %b.0.b.0.3 to double
   %call = tail call double @pow(double %conv, double %conv1) #1
   %conv2 = fptrunc double %call to float
@@ -146,7 +146,7 @@ declare double @pow(double, double) #0
 define float @foosf10() #0 {
 entry:
   %a = alloca float, align 4
-  %a.0.a.0. = load volatile float* %a, align 4
+  %a.0.a.0. = load volatile float, float* %a, align 4
   %conv = fpext float %a.0.a.0. to double
   %call = tail call double @sin(double %conv) #1
   %conv1 = fptrunc double %call to float
@@ -163,7 +163,7 @@ declare double @sin(double) #0
 define float @foosf11() #0 {
 entry:
   %b = alloca float, align 4
-  %b.0.b.0. = load volatile float* %b, align 4
+  %b.0.b.0. = load volatile float, float* %b, align 4
   %call = tail call float @ceilf(float %b.0.b.0.) #2
   ret float %call
 
@@ -179,8 +179,8 @@ define float @foosf12() #0 {
 entry:
   %b = alloca float, align 4
   %a = alloca float, align 4
-  %b.0.b.0. = load volatile float* %b, align 4
-  %a.0.a.0. = load volatile float* %a, align 4
+  %b.0.b.0. = load volatile float, float* %b, align 4
+  %a.0.a.0. = load volatile float, float* %a, align 4
   %call = tail call float @fmaxf(float %b.0.b.0., float %a.0.a.0.) #2
   ret float %call
 
@@ -196,8 +196,8 @@ define float @foosf13() #0 {
 entry:
   %b = alloca float, align 4
   %a = alloca float, align 4
-  %b.0.b.0. = load volatile float* %b, align 4
-  %a.0.a.0. = load volatile float* %a, align 4
+  %b.0.b.0. = load volatile float, float* %b, align 4
+  %a.0.a.0. = load volatile float, float* %a, align 4
   %call = tail call float @fminf(float %b.0.b.0., float %a.0.a.0.) #2
   ret float %call
 
@@ -211,4 +211,4 @@ declare float @fminf(float, float) #1
 
 
 attributes #0 = { nounwind "use-soft-float"="true" }
-attributes #1 = { nounwind readnone "use-soft-float"="true" }
+attributes #1 = { nounwind readnone "use-soft-float"="true" }
\ No newline at end of file
diff --git a/test/CodeGen/Mips/mips64sinttofpsf.ll b/test/CodeGen/Mips/mips64sinttofpsf.ll
index d3d46036f7da..87f803ecf552 100644
--- a/test/CodeGen/Mips/mips64sinttofpsf.ll
+++ b/test/CodeGen/Mips/mips64sinttofpsf.ll
@@ -1,11 +1,11 @@
-; RUN: llc -march=mips64 -mcpu=mips64r2 -soft-float -O0 < %s | FileCheck %s
+; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+soft-float -O0 < %s | FileCheck %s
 
 
 define double @foo() #0 {
 entry:
   %x = alloca i32, align 4
   store volatile i32 -32, i32* %x, align 4
-  %0 = load volatile i32* %x, align 4
+  %0 = load volatile i32, i32* %x, align 4
   %conv = sitofp i32 %0 to double
   ret double %conv
 
diff --git a/test/CodeGen/Mips/mipslopat.ll b/test/CodeGen/Mips/mipslopat.ll
index 1f433b9870ce..63b68c1762b2 100644
--- a/test/CodeGen/Mips/mipslopat.ll
+++ b/test/CodeGen/Mips/mipslopat.ll
@@ -6,10 +6,10 @@
 
 define void @simple_vol_file() nounwind {
 entry:
-  %tmp = load volatile i32** @stat_vol_ptr_int, align 4
+  %tmp = load volatile i32*, i32** @stat_vol_ptr_int, align 4
   %0 = bitcast i32* %tmp to i8*
   call void @llvm.prefetch(i8* %0, i32 0, i32 0, i32 1)
-  %tmp1 = load i32** @stat_ptr_vol_int, align 4
+  %tmp1 = load i32*, i32** @stat_ptr_vol_int, align 4
   %1 = bitcast i32* %tmp1 to i8*
   call void @llvm.prefetch(i8* %1, i32 0, i32 0, i32 1)
   ret void
diff --git a/test/CodeGen/Mips/misha.ll b/test/CodeGen/Mips/misha.ll
index 65d3b7b5d874..23ad7f6057af 100644
--- a/test/CodeGen/Mips/misha.ll
+++ b/test/CodeGen/Mips/misha.ll
@@ -8,15 +8,15 @@ entry:
   br i1 %cmp8, label %for.end, label %for.body.lr.ph
 
 for.body.lr.ph:                                   ; preds = %entry
-  %.pre = load i8* %to, align 1
+  %.pre = load i8, i8* %to, align 1
   br label %for.body
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %1 = phi i8 [ %.pre, %for.body.lr.ph ], [ %conv4, %for.body ]
   %i.010 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %from.addr.09 = phi i8* [ %from, %for.body.lr.ph ], [ %incdec.ptr, %for.body ]
-  %incdec.ptr = getelementptr inbounds i8* %from.addr.09, i32 1
-  %2 = load i8* %from.addr.09, align 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %from.addr.09, i32 1
+  %2 = load i8, i8* %from.addr.09, align 1
   %conv27 = zext i8 %2 to i32
   %conv36 = zext i8 %1 to i32
   %add = add nsw i32 %conv36, %conv27
@@ -44,15 +44,15 @@ entry:
   br i1 %cmp8, label %for.end, label %for.body.lr.ph
 
 for.body.lr.ph:                                   ; preds = %entry
-  %.pre = load i16* %to, align 2
+  %.pre = load i16, i16* %to, align 2
   br label %for.body
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %1 = phi i16 [ %.pre, %for.body.lr.ph ], [ %conv4, %for.body ]
   %i.010 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %from.addr.09 = phi i16* [ %from, %for.body.lr.ph ], [ %incdec.ptr, %for.body ]
-  %incdec.ptr = getelementptr inbounds i16* %from.addr.09, i32 1
-  %2 = load i16* %from.addr.09, align 2
+  %incdec.ptr = getelementptr inbounds i16, i16* %from.addr.09, i32 1
+  %2 = load i16, i16* %from.addr.09, align 2
   %conv27 = zext i16 %2 to i32
   %conv36 = zext i16 %1 to i32
   %add = add nsw i32 %conv36, %conv27
diff --git a/test/CodeGen/Mips/mno-ldc1-sdc1.ll b/test/CodeGen/Mips/mno-ldc1-sdc1.ll
index db653eadf2f7..c7eda3320bc6 100644
--- a/test/CodeGen/Mips/mno-ldc1-sdc1.ll
+++ b/test/CodeGen/Mips/mno-ldc1-sdc1.ll
@@ -111,7 +111,7 @@
 
 define double @test_ldc1() {
 entry:
-  %0 = load double* @g0, align 8
+  %0 = load double, double* @g0, align 8
   ret double %0
 }
 
@@ -212,8 +212,8 @@ entry:
 
 define double @test_ldxc1(double* nocapture readonly %a, i32 %i) {
 entry:
-  %arrayidx = getelementptr inbounds double* %a, i32 %i
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %a, i32 %i
+  %0 = load double, double* %arrayidx, align 8
   ret double %0
 }
 
@@ -243,7 +243,7 @@ entry:
 
 define void @test_sdxc1(double %b, double* nocapture %a, i32 %i) {
 entry:
-  %arrayidx = getelementptr inbounds double* %a, i32 %i
+  %arrayidx = getelementptr inbounds double, double* %a, i32 %i
   store double %b, double* %arrayidx, align 8
   ret void
 }
diff --git a/test/CodeGen/Mips/msa/2r.ll b/test/CodeGen/Mips/msa/2r.ll
index da35ad82cad1..501936c76e73 100644
--- a/test/CodeGen/Mips/msa/2r.ll
+++ b/test/CodeGen/Mips/msa/2r.ll
@@ -8,7 +8,7 @@
 
 define void @llvm_mips_nloc_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_nloc_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_nloc_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.nloc.b(<16 x i8> %0)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_nloc_b_RES
   ret void
@@ -29,7 +29,7 @@ declare <16 x i8> @llvm.mips.nloc.b(<16 x i8>) nounwind
 
 define void @llvm_mips_nloc_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_nloc_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_nloc_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.nloc.h(<8 x i16> %0)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_nloc_h_RES
   ret void
@@ -50,7 +50,7 @@ declare <8 x i16> @llvm.mips.nloc.h(<8 x i16>) nounwind
 
 define void @llvm_mips_nloc_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_nloc_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_nloc_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.nloc.w(<4 x i32> %0)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_nloc_w_RES
   ret void
@@ -71,7 +71,7 @@ declare <4 x i32> @llvm.mips.nloc.w(<4 x i32>) nounwind
 
 define void @llvm_mips_nloc_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_nloc_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_nloc_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.nloc.d(<2 x i64> %0)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_nloc_d_RES
   ret void
@@ -92,7 +92,7 @@ declare <2 x i64> @llvm.mips.nloc.d(<2 x i64>) nounwind
 
 define void @llvm_mips_nlzc_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_nlzc_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_nlzc_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.nlzc.b(<16 x i8> %0)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_nlzc_b_RES
   ret void
@@ -113,7 +113,7 @@ declare <16 x i8> @llvm.mips.nlzc.b(<16 x i8>) nounwind
 
 define void @llvm_mips_nlzc_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_nlzc_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_nlzc_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.nlzc.h(<8 x i16> %0)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_nlzc_h_RES
   ret void
@@ -134,7 +134,7 @@ declare <8 x i16> @llvm.mips.nlzc.h(<8 x i16>) nounwind
 
 define void @llvm_mips_nlzc_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_nlzc_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_nlzc_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.nlzc.w(<4 x i32> %0)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_nlzc_w_RES
   ret void
@@ -155,7 +155,7 @@ declare <4 x i32> @llvm.mips.nlzc.w(<4 x i32>) nounwind
 
 define void @llvm_mips_nlzc_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_nlzc_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_nlzc_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.nlzc.d(<2 x i64> %0)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_nlzc_d_RES
   ret void
@@ -176,7 +176,7 @@ declare <2 x i64> @llvm.mips.nlzc.d(<2 x i64>) nounwind
 
 define void @llvm_mips_pcnt_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_pcnt_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_pcnt_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.pcnt.b(<16 x i8> %0)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_pcnt_b_RES
   ret void
@@ -197,7 +197,7 @@ declare <16 x i8> @llvm.mips.pcnt.b(<16 x i8>) nounwind
 
 define void @llvm_mips_pcnt_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_pcnt_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_pcnt_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.pcnt.h(<8 x i16> %0)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_pcnt_h_RES
   ret void
@@ -218,7 +218,7 @@ declare <8 x i16> @llvm.mips.pcnt.h(<8 x i16>) nounwind
 
 define void @llvm_mips_pcnt_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_pcnt_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_pcnt_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.pcnt.w(<4 x i32> %0)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_pcnt_w_RES
   ret void
@@ -239,7 +239,7 @@ declare <4 x i32> @llvm.mips.pcnt.w(<4 x i32>) nounwind
 
 define void @llvm_mips_pcnt_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_pcnt_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_pcnt_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.pcnt.d(<2 x i64> %0)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_pcnt_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/test/CodeGen/Mips/msa/2r_vector_scalar.ll
index 64e459e4d9a9..ddcd3cf757d9 100644
--- a/test/CodeGen/Mips/msa/2r_vector_scalar.ll
+++ b/test/CodeGen/Mips/msa/2r_vector_scalar.ll
@@ -15,7 +15,7 @@
 
 define void @llvm_mips_fill_b_test() nounwind {
 entry:
-  %0 = load i32* @llvm_mips_fill_b_ARG1
+  %0 = load i32, i32* @llvm_mips_fill_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.fill.b(i32 %0)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_fill_b_RES
   ret void
@@ -35,7 +35,7 @@ declare <16 x i8> @llvm.mips.fill.b(i32) nounwind
 
 define void @llvm_mips_fill_h_test() nounwind {
 entry:
-  %0 = load i32* @llvm_mips_fill_h_ARG1
+  %0 = load i32, i32* @llvm_mips_fill_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.fill.h(i32 %0)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_fill_h_RES
   ret void
@@ -55,7 +55,7 @@ declare <8 x i16> @llvm.mips.fill.h(i32) nounwind
 
 define void @llvm_mips_fill_w_test() nounwind {
 entry:
-  %0 = load i32* @llvm_mips_fill_w_ARG1
+  %0 = load i32, i32* @llvm_mips_fill_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.fill.w(i32 %0)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_fill_w_RES
   ret void
@@ -75,7 +75,7 @@ declare <4 x i32> @llvm.mips.fill.w(i32) nounwind
 
 define void @llvm_mips_fill_d_test() nounwind {
 entry:
-  %0 = load i64* @llvm_mips_fill_d_ARG1
+  %0 = load i64, i64* @llvm_mips_fill_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.fill.d(i64 %0)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_fill_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/2rf.ll b/test/CodeGen/Mips/msa/2rf.ll
index b361ef5eae21..1dbfbda1b612 100644
--- a/test/CodeGen/Mips/msa/2rf.ll
+++ b/test/CodeGen/Mips/msa/2rf.ll
@@ -8,7 +8,7 @@
 
 define void @llvm_mips_flog2_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_flog2_w_ARG1
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_flog2_w_ARG1
   %1 = tail call <4 x float> @llvm.mips.flog2.w(<4 x float> %0)
   store <4 x float> %1, <4 x float>* @llvm_mips_flog2_w_RES
   ret void
@@ -29,7 +29,7 @@ declare <4 x float> @llvm.mips.flog2.w(<4 x float>) nounwind
 
 define void @llvm_mips_flog2_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_flog2_d_ARG1
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_flog2_d_ARG1
   %1 = tail call <2 x double> @llvm.mips.flog2.d(<2 x double> %0)
   store <2 x double> %1, <2 x double>* @llvm_mips_flog2_d_RES
   ret void
@@ -47,7 +47,7 @@ declare <2 x double> @llvm.mips.flog2.d(<2 x double>) nounwind
 
 define void @flog2_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_flog2_w_ARG1
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_flog2_w_ARG1
   %1 = tail call <4 x float> @llvm.log2.v4f32(<4 x float> %0)
   store <4 x float> %1, <4 x float>* @llvm_mips_flog2_w_RES
   ret void
@@ -65,7 +65,7 @@ declare <4 x float> @llvm.log2.v4f32(<4 x float> %val)
 
 define void @flog2_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_flog2_d_ARG1
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_flog2_d_ARG1
   %1 = tail call <2 x double> @llvm.log2.v2f64(<2 x double> %0)
   store <2 x double> %1, <2 x double>* @llvm_mips_flog2_d_RES
   ret void
@@ -86,7 +86,7 @@ declare <2 x double> @llvm.log2.v2f64(<2 x double> %val)
 
 define void @llvm_mips_frint_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_frint_w_ARG1
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_frint_w_ARG1
   %1 = tail call <4 x float> @llvm.mips.frint.w(<4 x float> %0)
   store <4 x float> %1, <4 x float>* @llvm_mips_frint_w_RES
   ret void
@@ -107,7 +107,7 @@ declare <4 x float> @llvm.mips.frint.w(<4 x float>) nounwind
 
 define void @llvm_mips_frint_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_frint_d_ARG1
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_frint_d_ARG1
   %1 = tail call <2 x double> @llvm.mips.frint.d(<2 x double> %0)
   store <2 x double> %1, <2 x double>* @llvm_mips_frint_d_RES
   ret void
@@ -125,7 +125,7 @@ declare <2 x double> @llvm.mips.frint.d(<2 x double>) nounwind
 
 define void @frint_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_frint_w_ARG1
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_frint_w_ARG1
   %1 = tail call <4 x float> @llvm.rint.v4f32(<4 x float> %0)
   store <4 x float> %1, <4 x float>* @llvm_mips_frint_w_RES
   ret void
@@ -143,7 +143,7 @@ declare <4 x float> @llvm.rint.v4f32(<4 x float>) nounwind
 
 define void @frint_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_frint_d_ARG1
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_frint_d_ARG1
   %1 = tail call <2 x double> @llvm.rint.v2f64(<2 x double> %0)
   store <2 x double> %1, <2 x double>* @llvm_mips_frint_d_RES
   ret void
@@ -164,7 +164,7 @@ declare <2 x double> @llvm.rint.v2f64(<2 x double>) nounwind
 
 define void @llvm_mips_frcp_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_frcp_w_ARG1
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_frcp_w_ARG1
   %1 = tail call <4 x float> @llvm.mips.frcp.w(<4 x float> %0)
   store <4 x float> %1, <4 x float>* @llvm_mips_frcp_w_RES
   ret void
@@ -185,7 +185,7 @@ declare <4 x float> @llvm.mips.frcp.w(<4 x float>) nounwind
 
 define void @llvm_mips_frcp_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_frcp_d_ARG1
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_frcp_d_ARG1
   %1 = tail call <2 x double> @llvm.mips.frcp.d(<2 x double> %0)
   store <2 x double> %1, <2 x double>* @llvm_mips_frcp_d_RES
   ret void
@@ -206,7 +206,7 @@ declare <2 x double> @llvm.mips.frcp.d(<2 x double>) nounwind
 
 define void @llvm_mips_frsqrt_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_frsqrt_w_ARG1
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_frsqrt_w_ARG1
   %1 = tail call <4 x float> @llvm.mips.frsqrt.w(<4 x float> %0)
   store <4 x float> %1, <4 x float>* @llvm_mips_frsqrt_w_RES
   ret void
@@ -227,7 +227,7 @@ declare <4 x float> @llvm.mips.frsqrt.w(<4 x float>) nounwind
 
 define void @llvm_mips_frsqrt_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_frsqrt_d_ARG1
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_frsqrt_d_ARG1
   %1 = tail call <2 x double> @llvm.mips.frsqrt.d(<2 x double> %0)
   store <2 x double> %1, <2 x double>* @llvm_mips_frsqrt_d_RES
   ret void
@@ -248,7 +248,7 @@ declare <2 x double> @llvm.mips.frsqrt.d(<2 x double>) nounwind
 
 define void @llvm_mips_fsqrt_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fsqrt_w_ARG1
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fsqrt_w_ARG1
   %1 = tail call <4 x float> @llvm.mips.fsqrt.w(<4 x float> %0)
   store <4 x float> %1, <4 x float>* @llvm_mips_fsqrt_w_RES
   ret void
@@ -269,7 +269,7 @@ declare <4 x float> @llvm.mips.fsqrt.w(<4 x float>) nounwind
 
 define void @llvm_mips_fsqrt_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fsqrt_d_ARG1
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fsqrt_d_ARG1
   %1 = tail call <2 x double> @llvm.mips.fsqrt.d(<2 x double> %0)
   store <2 x double> %1, <2 x double>* @llvm_mips_fsqrt_d_RES
   ret void
@@ -287,7 +287,7 @@ declare <2 x double> @llvm.mips.fsqrt.d(<2 x double>) nounwind
 
 define void @fsqrt_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fsqrt_w_ARG1
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fsqrt_w_ARG1
   %1 = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0)
   store <4 x float> %1, <4 x float>* @llvm_mips_fsqrt_w_RES
   ret void
@@ -305,7 +305,7 @@ declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind
 
 define void @fsqrt_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fsqrt_d_ARG1
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fsqrt_d_ARG1
   %1 = tail call <2 x double> @llvm.sqrt.v2f64(<2 x double> %0)
   store <2 x double> %1, <2 x double>* @llvm_mips_fsqrt_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/2rf_exup.ll b/test/CodeGen/Mips/msa/2rf_exup.ll
index 8d7cc367040a..fd81ff6d112b 100644
--- a/test/CodeGen/Mips/msa/2rf_exup.ll
+++ b/test/CodeGen/Mips/msa/2rf_exup.ll
@@ -9,7 +9,7 @@
 
 define void @llvm_mips_fexupl_w_test() nounwind {
 entry:
-  %0 = load <8 x half>* @llvm_mips_fexupl_w_ARG1
+  %0 = load <8 x half>, <8 x half>* @llvm_mips_fexupl_w_ARG1
   %1 = tail call <4 x float> @llvm.mips.fexupl.w(<8 x half> %0)
   store <4 x float> %1, <4 x float>* @llvm_mips_fexupl_w_RES
   ret void
@@ -28,7 +28,7 @@ declare <4 x float> @llvm.mips.fexupl.w(<8 x half>) nounwind
 
 define void @llvm_mips_fexupl_d_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fexupl_d_ARG1
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fexupl_d_ARG1
   %1 = tail call <2 x double> @llvm.mips.fexupl.d(<4 x float> %0)
   store <2 x double> %1, <2 x double>* @llvm_mips_fexupl_d_RES
   ret void
@@ -47,7 +47,7 @@ declare <2 x double> @llvm.mips.fexupl.d(<4 x float>) nounwind
 
 define void @llvm_mips_fexupr_w_test() nounwind {
 entry:
-  %0 = load <8 x half>* @llvm_mips_fexupr_w_ARG1
+  %0 = load <8 x half>, <8 x half>* @llvm_mips_fexupr_w_ARG1
   %1 = tail call <4 x float> @llvm.mips.fexupr.w(<8 x half> %0)
   store <4 x float> %1, <4 x float>* @llvm_mips_fexupr_w_RES
   ret void
@@ -66,7 +66,7 @@ declare <4 x float> @llvm.mips.fexupr.w(<8 x half>) nounwind
 
 define void @llvm_mips_fexupr_d_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fexupr_d_ARG1
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fexupr_d_ARG1
   %1 = tail call <2 x double> @llvm.mips.fexupr.d(<4 x float> %0)
   store <2 x double> %1, <2 x double>* @llvm_mips_fexupr_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/2rf_float_int.ll b/test/CodeGen/Mips/msa/2rf_float_int.ll
index 3b5dfda2d1e6..369015814b0e 100644
--- a/test/CodeGen/Mips/msa/2rf_float_int.ll
+++ b/test/CodeGen/Mips/msa/2rf_float_int.ll
@@ -9,7 +9,7 @@
 
 define void @llvm_mips_ffint_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_ffint_s_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ffint_s_w_ARG1
   %1 = tail call <4 x float> @llvm.mips.ffint.s.w(<4 x i32> %0)
   store <4 x float> %1, <4 x float>* @llvm_mips_ffint_s_w_RES
   ret void
@@ -30,7 +30,7 @@ declare <4 x float> @llvm.mips.ffint.s.w(<4 x i32>) nounwind
 
 define void @llvm_mips_ffint_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_ffint_s_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ffint_s_d_ARG1
   %1 = tail call <2 x double> @llvm.mips.ffint.s.d(<2 x i64> %0)
   store <2 x double> %1, <2 x double>* @llvm_mips_ffint_s_d_RES
   ret void
@@ -51,7 +51,7 @@ declare <2 x double> @llvm.mips.ffint.s.d(<2 x i64>) nounwind
 
 define void @llvm_mips_ffint_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_ffint_u_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ffint_u_w_ARG1
   %1 = tail call <4 x float> @llvm.mips.ffint.u.w(<4 x i32> %0)
   store <4 x float> %1, <4 x float>* @llvm_mips_ffint_u_w_RES
   ret void
@@ -72,7 +72,7 @@ declare <4 x float> @llvm.mips.ffint.u.w(<4 x i32>) nounwind
 
 define void @llvm_mips_ffint_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_ffint_u_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ffint_u_d_ARG1
   %1 = tail call <2 x double> @llvm.mips.ffint.u.d(<2 x i64> %0)
   store <2 x double> %1, <2 x double>* @llvm_mips_ffint_u_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/2rf_fq.ll b/test/CodeGen/Mips/msa/2rf_fq.ll
index 021dd937fad3..05c649ee918a 100644
--- a/test/CodeGen/Mips/msa/2rf_fq.ll
+++ b/test/CodeGen/Mips/msa/2rf_fq.ll
@@ -9,7 +9,7 @@
 
 define void @llvm_mips_ffql_w_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_ffql_w_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ffql_w_ARG1
   %1 = tail call <4 x float> @llvm.mips.ffql.w(<8 x i16> %0)
   store <4 x float> %1, <4 x float>* @llvm_mips_ffql_w_RES
   ret void
@@ -28,7 +28,7 @@ declare <4 x float> @llvm.mips.ffql.w(<8 x i16>) nounwind
 
 define void @llvm_mips_ffql_d_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_ffql_d_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ffql_d_ARG1
   %1 = tail call <2 x double> @llvm.mips.ffql.d(<4 x i32> %0)
   store <2 x double> %1, <2 x double>* @llvm_mips_ffql_d_RES
   ret void
@@ -47,7 +47,7 @@ declare <2 x double> @llvm.mips.ffql.d(<4 x i32>) nounwind
 
 define void @llvm_mips_ffqr_w_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_ffqr_w_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ffqr_w_ARG1
   %1 = tail call <4 x float> @llvm.mips.ffqr.w(<8 x i16> %0)
   store <4 x float> %1, <4 x float>* @llvm_mips_ffqr_w_RES
   ret void
@@ -66,7 +66,7 @@ declare <4 x float> @llvm.mips.ffqr.w(<8 x i16>) nounwind
 
 define void @llvm_mips_ffqr_d_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_ffqr_d_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ffqr_d_ARG1
   %1 = tail call <2 x double> @llvm.mips.ffqr.d(<4 x i32> %0)
   store <2 x double> %1, <2 x double>* @llvm_mips_ffqr_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/2rf_int_float.ll b/test/CodeGen/Mips/msa/2rf_int_float.ll
index 4665ae066a4f..77d1404f9cfa 100644
--- a/test/CodeGen/Mips/msa/2rf_int_float.ll
+++ b/test/CodeGen/Mips/msa/2rf_int_float.ll
@@ -10,7 +10,7 @@
 
 define void @llvm_mips_fclass_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fclass_w_ARG1
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fclass_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.fclass.w(<4 x float> %0)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_fclass_w_RES
   ret void
@@ -31,7 +31,7 @@ declare <4 x i32> @llvm.mips.fclass.w(<4 x float>) nounwind
 
 define void @llvm_mips_fclass_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fclass_d_ARG1
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fclass_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.fclass.d(<2 x double> %0)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_fclass_d_RES
   ret void
@@ -52,7 +52,7 @@ declare <2 x i64> @llvm.mips.fclass.d(<2 x double>) nounwind
 
 define void @llvm_mips_ftrunc_s_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_ftrunc_s_w_ARG1
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_ftrunc_s_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.ftrunc.s.w(<4 x float> %0)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_ftrunc_s_w_RES
   ret void
@@ -73,7 +73,7 @@ declare <4 x i32> @llvm.mips.ftrunc.s.w(<4 x float>) nounwind
 
 define void @llvm_mips_ftrunc_s_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_ftrunc_s_d_ARG1
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_ftrunc_s_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.ftrunc.s.d(<2 x double> %0)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_ftrunc_s_d_RES
   ret void
@@ -94,7 +94,7 @@ declare <2 x i64> @llvm.mips.ftrunc.s.d(<2 x double>) nounwind
 
 define void @llvm_mips_ftrunc_u_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_ftrunc_u_w_ARG1
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_ftrunc_u_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.ftrunc.u.w(<4 x float> %0)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_ftrunc_u_w_RES
   ret void
@@ -115,7 +115,7 @@ declare <4 x i32> @llvm.mips.ftrunc.u.w(<4 x float>) nounwind
 
 define void @llvm_mips_ftrunc_u_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_ftrunc_u_d_ARG1
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_ftrunc_u_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.ftrunc.u.d(<2 x double> %0)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_ftrunc_u_d_RES
   ret void
@@ -136,7 +136,7 @@ declare <2 x i64> @llvm.mips.ftrunc.u.d(<2 x double>) nounwind
 
 define void @llvm_mips_ftint_s_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_ftint_s_w_ARG1
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_ftint_s_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.ftint.s.w(<4 x float> %0)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_ftint_s_w_RES
   ret void
@@ -157,7 +157,7 @@ declare <4 x i32> @llvm.mips.ftint.s.w(<4 x float>) nounwind
 
 define void @llvm_mips_ftint_s_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_ftint_s_d_ARG1
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_ftint_s_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.ftint.s.d(<2 x double> %0)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_ftint_s_d_RES
   ret void
@@ -178,7 +178,7 @@ declare <2 x i64> @llvm.mips.ftint.s.d(<2 x double>) nounwind
 
 define void @llvm_mips_ftint_u_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_ftint_u_w_ARG1
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_ftint_u_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.ftint.u.w(<4 x float> %0)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_ftint_u_w_RES
   ret void
@@ -199,7 +199,7 @@ declare <4 x i32> @llvm.mips.ftint.u.w(<4 x float>) nounwind
 
 define void @llvm_mips_ftint_u_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_ftint_u_d_ARG1
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_ftint_u_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.ftint.u.d(<2 x double> %0)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_ftint_u_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/2rf_tq.ll b/test/CodeGen/Mips/msa/2rf_tq.ll
index 6f3c508f5b8c..9b7f02a5ef33 100644
--- a/test/CodeGen/Mips/msa/2rf_tq.ll
+++ b/test/CodeGen/Mips/msa/2rf_tq.ll
@@ -10,8 +10,8 @@
 
 define void @llvm_mips_ftq_h_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_ftq_h_ARG1
-  %1 = load <4 x float>* @llvm_mips_ftq_h_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_ftq_h_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_ftq_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.ftq.h(<4 x float> %0, <4 x float> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_ftq_h_RES
   ret void
@@ -32,8 +32,8 @@ declare <8 x i16> @llvm.mips.ftq.h(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_ftq_w_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_ftq_w_ARG1
-  %1 = load <2 x double>* @llvm_mips_ftq_w_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_ftq_w_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_ftq_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.ftq.w(<2 x double> %0, <2 x double> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_ftq_w_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3r-a.ll b/test/CodeGen/Mips/msa/3r-a.ll
index dab15b66b7ce..db772f918614 100644
--- a/test/CodeGen/Mips/msa/3r-a.ll
+++ b/test/CodeGen/Mips/msa/3r-a.ll
@@ -15,8 +15,8 @@
 
 define void @llvm_mips_add_a_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_add_a_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_add_a_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_add_a_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_add_a_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.add.a.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_add_a_b_RES
   ret void
@@ -40,8 +40,8 @@ declare <16 x i8> @llvm.mips.add.a.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_add_a_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_add_a_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_add_a_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_add_a_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_add_a_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.add.a.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_add_a_h_RES
   ret void
@@ -65,8 +65,8 @@ declare <8 x i16> @llvm.mips.add.a.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_add_a_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_add_a_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_add_a_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_add_a_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_add_a_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.add.a.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_add_a_w_RES
   ret void
@@ -90,8 +90,8 @@ declare <4 x i32> @llvm.mips.add.a.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_add_a_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_add_a_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_add_a_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_add_a_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_add_a_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.add.a.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_add_a_d_RES
   ret void
@@ -115,8 +115,8 @@ declare <2 x i64> @llvm.mips.add.a.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_adds_a_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_adds_a_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_adds_a_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_adds_a_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_adds_a_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.adds.a.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_adds_a_b_RES
   ret void
@@ -140,8 +140,8 @@ declare <16 x i8> @llvm.mips.adds.a.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_adds_a_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_adds_a_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_adds_a_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_adds_a_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_adds_a_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.adds.a.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_adds_a_h_RES
   ret void
@@ -165,8 +165,8 @@ declare <8 x i16> @llvm.mips.adds.a.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_adds_a_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_adds_a_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_adds_a_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_adds_a_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_adds_a_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.adds.a.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_adds_a_w_RES
   ret void
@@ -190,8 +190,8 @@ declare <4 x i32> @llvm.mips.adds.a.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_adds_a_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_adds_a_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_adds_a_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_adds_a_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_adds_a_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.adds.a.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_adds_a_d_RES
   ret void
@@ -215,8 +215,8 @@ declare <2 x i64> @llvm.mips.adds.a.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_adds_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_adds_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_adds_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_adds_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_adds_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.adds.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_adds_s_b_RES
   ret void
@@ -240,8 +240,8 @@ declare <16 x i8> @llvm.mips.adds.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_adds_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_adds_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_adds_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_adds_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_adds_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.adds.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_adds_s_h_RES
   ret void
@@ -265,8 +265,8 @@ declare <8 x i16> @llvm.mips.adds.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_adds_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_adds_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_adds_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_adds_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_adds_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.adds.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_adds_s_w_RES
   ret void
@@ -290,8 +290,8 @@ declare <4 x i32> @llvm.mips.adds.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_adds_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_adds_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_adds_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_adds_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_adds_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.adds.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_adds_s_d_RES
   ret void
@@ -315,8 +315,8 @@ declare <2 x i64> @llvm.mips.adds.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_adds_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_adds_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_adds_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_adds_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_adds_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.adds.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_adds_u_b_RES
   ret void
@@ -340,8 +340,8 @@ declare <16 x i8> @llvm.mips.adds.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_adds_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_adds_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_adds_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_adds_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_adds_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.adds.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_adds_u_h_RES
   ret void
@@ -365,8 +365,8 @@ declare <8 x i16> @llvm.mips.adds.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_adds_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_adds_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_adds_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_adds_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_adds_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.adds.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_adds_u_w_RES
   ret void
@@ -390,8 +390,8 @@ declare <4 x i32> @llvm.mips.adds.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_adds_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_adds_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_adds_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_adds_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_adds_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.adds.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_adds_u_d_RES
   ret void
@@ -415,8 +415,8 @@ declare <2 x i64> @llvm.mips.adds.u.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_addv_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_addv_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_addv_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_addv_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_addv_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_addv_b_RES
   ret void
@@ -440,8 +440,8 @@ declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_addv_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_addv_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_addv_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_addv_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_addv_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_addv_h_RES
   ret void
@@ -465,8 +465,8 @@ declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_addv_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_addv_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_addv_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_addv_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_addv_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_addv_w_RES
   ret void
@@ -490,8 +490,8 @@ declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_addv_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_addv_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_addv_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_addv_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_addv_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_addv_d_RES
   ret void
@@ -512,8 +512,8 @@ declare <2 x i64> @llvm.mips.addv.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @addv_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_addv_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_addv_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_addv_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_addv_b_ARG2
   %2 = add <16 x i8> %0, %1
   store <16 x i8> %2, <16 x i8>* @llvm_mips_addv_b_RES
   ret void
@@ -532,8 +532,8 @@ entry:
 
 define void @addv_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_addv_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_addv_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_addv_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_addv_h_ARG2
   %2 = add <8 x i16> %0, %1
   store <8 x i16> %2, <8 x i16>* @llvm_mips_addv_h_RES
   ret void
@@ -552,8 +552,8 @@ entry:
 
 define void @addv_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_addv_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_addv_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_addv_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_addv_w_ARG2
   %2 = add <4 x i32> %0, %1
   store <4 x i32> %2, <4 x i32>* @llvm_mips_addv_w_RES
   ret void
@@ -572,8 +572,8 @@ entry:
 
 define void @addv_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_addv_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_addv_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_addv_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_addv_d_ARG2
   %2 = add <2 x i64> %0, %1
   store <2 x i64> %2, <2 x i64>* @llvm_mips_addv_d_RES
   ret void
@@ -595,8 +595,8 @@ entry:
 
 define void @llvm_mips_asub_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_asub_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_asub_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_asub_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_asub_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.asub.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_asub_s_b_RES
   ret void
@@ -620,8 +620,8 @@ declare <16 x i8> @llvm.mips.asub.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_asub_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_asub_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_asub_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_asub_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_asub_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.asub.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_asub_s_h_RES
   ret void
@@ -645,8 +645,8 @@ declare <8 x i16> @llvm.mips.asub.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_asub_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_asub_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_asub_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_asub_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_asub_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.asub.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_asub_s_w_RES
   ret void
@@ -670,8 +670,8 @@ declare <4 x i32> @llvm.mips.asub.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_asub_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_asub_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_asub_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_asub_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_asub_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.asub.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_asub_s_d_RES
   ret void
@@ -695,8 +695,8 @@ declare <2 x i64> @llvm.mips.asub.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_asub_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_asub_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_asub_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_asub_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_asub_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.asub.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_asub_u_b_RES
   ret void
@@ -720,8 +720,8 @@ declare <16 x i8> @llvm.mips.asub.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_asub_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_asub_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_asub_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_asub_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_asub_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.asub.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_asub_u_h_RES
   ret void
@@ -745,8 +745,8 @@ declare <8 x i16> @llvm.mips.asub.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_asub_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_asub_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_asub_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_asub_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_asub_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.asub.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_asub_u_w_RES
   ret void
@@ -770,8 +770,8 @@ declare <4 x i32> @llvm.mips.asub.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_asub_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_asub_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_asub_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_asub_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_asub_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.asub.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_asub_u_d_RES
   ret void
@@ -795,8 +795,8 @@ declare <2 x i64> @llvm.mips.asub.u.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_ave_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_ave_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_ave_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_ave_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_ave_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.ave.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_ave_s_b_RES
   ret void
@@ -820,8 +820,8 @@ declare <16 x i8> @llvm.mips.ave.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_ave_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_ave_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_ave_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ave_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_ave_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.ave.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_ave_s_h_RES
   ret void
@@ -845,8 +845,8 @@ declare <8 x i16> @llvm.mips.ave.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_ave_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_ave_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_ave_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ave_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_ave_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.ave.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_ave_s_w_RES
   ret void
@@ -870,8 +870,8 @@ declare <4 x i32> @llvm.mips.ave.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_ave_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_ave_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_ave_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ave_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_ave_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.ave.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_ave_s_d_RES
   ret void
@@ -895,8 +895,8 @@ declare <2 x i64> @llvm.mips.ave.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_ave_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_ave_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_ave_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_ave_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_ave_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.ave.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_ave_u_b_RES
   ret void
@@ -920,8 +920,8 @@ declare <16 x i8> @llvm.mips.ave.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_ave_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_ave_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_ave_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ave_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_ave_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.ave.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_ave_u_h_RES
   ret void
@@ -945,8 +945,8 @@ declare <8 x i16> @llvm.mips.ave.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_ave_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_ave_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_ave_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ave_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_ave_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.ave.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_ave_u_w_RES
   ret void
@@ -970,8 +970,8 @@ declare <4 x i32> @llvm.mips.ave.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_ave_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_ave_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_ave_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ave_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_ave_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.ave.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_ave_u_d_RES
   ret void
@@ -995,8 +995,8 @@ declare <2 x i64> @llvm.mips.ave.u.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_aver_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_aver_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_aver_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_aver_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_aver_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.aver.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_aver_s_b_RES
   ret void
@@ -1020,8 +1020,8 @@ declare <16 x i8> @llvm.mips.aver.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_aver_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_aver_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_aver_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_aver_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_aver_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.aver.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_aver_s_h_RES
   ret void
@@ -1045,8 +1045,8 @@ declare <8 x i16> @llvm.mips.aver.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_aver_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_aver_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_aver_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_aver_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_aver_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.aver.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_aver_s_w_RES
   ret void
@@ -1070,8 +1070,8 @@ declare <4 x i32> @llvm.mips.aver.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_aver_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_aver_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_aver_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_aver_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_aver_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.aver.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_aver_s_d_RES
   ret void
@@ -1095,8 +1095,8 @@ declare <2 x i64> @llvm.mips.aver.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_aver_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_aver_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_aver_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_aver_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_aver_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.aver.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_aver_u_b_RES
   ret void
@@ -1120,8 +1120,8 @@ declare <16 x i8> @llvm.mips.aver.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_aver_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_aver_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_aver_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_aver_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_aver_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.aver.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_aver_u_h_RES
   ret void
@@ -1145,8 +1145,8 @@ declare <8 x i16> @llvm.mips.aver.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_aver_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_aver_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_aver_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_aver_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_aver_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.aver.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_aver_u_w_RES
   ret void
@@ -1170,8 +1170,8 @@ declare <4 x i32> @llvm.mips.aver.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_aver_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_aver_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_aver_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_aver_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_aver_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.aver.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_aver_u_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3r-b.ll b/test/CodeGen/Mips/msa/3r-b.ll
index a05d19b4d490..2ecdc4290067 100644
--- a/test/CodeGen/Mips/msa/3r-b.ll
+++ b/test/CodeGen/Mips/msa/3r-b.ll
@@ -10,8 +10,8 @@
 
 define void @llvm_mips_bclr_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bclr_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_bclr_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bclr_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bclr_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.bclr.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_bclr_b_RES
   ret void
@@ -32,8 +32,8 @@ declare <16 x i8> @llvm.mips.bclr.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_bclr_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_bclr_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_bclr_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bclr_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_bclr_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.bclr.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_bclr_h_RES
   ret void
@@ -54,8 +54,8 @@ declare <8 x i16> @llvm.mips.bclr.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_bclr_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_bclr_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_bclr_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bclr_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_bclr_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.bclr.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_bclr_w_RES
   ret void
@@ -76,8 +76,8 @@ declare <4 x i32> @llvm.mips.bclr.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_bclr_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_bclr_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_bclr_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bclr_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_bclr_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.bclr.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_bclr_d_RES
   ret void
@@ -99,9 +99,9 @@ declare <2 x i64> @llvm.mips.bclr.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_binsl_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_binsl_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_binsl_b_ARG2
-  %2 = load <16 x i8>* @llvm_mips_binsl_b_ARG3
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_binsl_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_binsl_b_ARG2
+  %2 = load <16 x i8>, <16 x i8>* @llvm_mips_binsl_b_ARG3
   %3 = tail call <16 x i8> @llvm.mips.binsl.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)
   store <16 x i8> %3, <16 x i8>* @llvm_mips_binsl_b_RES
   ret void
@@ -127,9 +127,9 @@ declare <16 x i8> @llvm.mips.binsl.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_binsl_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_binsl_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_binsl_h_ARG2
-  %2 = load <8 x i16>* @llvm_mips_binsl_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_binsl_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_binsl_h_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_binsl_h_ARG3
   %3 = tail call <8 x i16> @llvm.mips.binsl.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
   store <8 x i16> %3, <8 x i16>* @llvm_mips_binsl_h_RES
   ret void
@@ -155,9 +155,9 @@ declare <8 x i16> @llvm.mips.binsl.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_binsl_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_binsl_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_binsl_w_ARG2
-  %2 = load <4 x i32>* @llvm_mips_binsl_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_binsl_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_binsl_w_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_binsl_w_ARG3
   %3 = tail call <4 x i32> @llvm.mips.binsl.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
   store <4 x i32> %3, <4 x i32>* @llvm_mips_binsl_w_RES
   ret void
@@ -183,9 +183,9 @@ declare <4 x i32> @llvm.mips.binsl.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_binsl_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_binsl_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_binsl_d_ARG2
-  %2 = load <2 x i64>* @llvm_mips_binsl_d_ARG3
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_binsl_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_binsl_d_ARG2
+  %2 = load <2 x i64>, <2 x i64>* @llvm_mips_binsl_d_ARG3
   %3 = tail call <2 x i64> @llvm.mips.binsl.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2)
   store <2 x i64> %3, <2 x i64>* @llvm_mips_binsl_d_RES
   ret void
@@ -211,9 +211,9 @@ declare <2 x i64> @llvm.mips.binsl.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_binsr_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_binsr_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_binsr_b_ARG2
-  %2 = load <16 x i8>* @llvm_mips_binsr_b_ARG3
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_binsr_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_binsr_b_ARG2
+  %2 = load <16 x i8>, <16 x i8>* @llvm_mips_binsr_b_ARG3
   %3 = tail call <16 x i8> @llvm.mips.binsr.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)
   store <16 x i8> %3, <16 x i8>* @llvm_mips_binsr_b_RES
   ret void
@@ -239,9 +239,9 @@ declare <16 x i8> @llvm.mips.binsr.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_binsr_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_binsr_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_binsr_h_ARG2
-  %2 = load <8 x i16>* @llvm_mips_binsr_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_binsr_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_binsr_h_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_binsr_h_ARG3
   %3 = tail call <8 x i16> @llvm.mips.binsr.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
   store <8 x i16> %3, <8 x i16>* @llvm_mips_binsr_h_RES
   ret void
@@ -267,9 +267,9 @@ declare <8 x i16> @llvm.mips.binsr.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_binsr_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_binsr_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_binsr_w_ARG2
-  %2 = load <4 x i32>* @llvm_mips_binsr_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_binsr_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_binsr_w_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_binsr_w_ARG3
   %3 = tail call <4 x i32> @llvm.mips.binsr.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
   store <4 x i32> %3, <4 x i32>* @llvm_mips_binsr_w_RES
   ret void
@@ -295,9 +295,9 @@ declare <4 x i32> @llvm.mips.binsr.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_binsr_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_binsr_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_binsr_d_ARG2
-  %2 = load <2 x i64>* @llvm_mips_binsr_d_ARG3
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_binsr_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_binsr_d_ARG2
+  %2 = load <2 x i64>, <2 x i64>* @llvm_mips_binsr_d_ARG3
   %3 = tail call <2 x i64> @llvm.mips.binsr.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2)
   store <2 x i64> %3, <2 x i64>* @llvm_mips_binsr_d_RES
   ret void
@@ -322,8 +322,8 @@ declare <2 x i64> @llvm.mips.binsr.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_bneg_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bneg_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_bneg_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bneg_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bneg_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.bneg.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_bneg_b_RES
   ret void
@@ -344,8 +344,8 @@ declare <16 x i8> @llvm.mips.bneg.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_bneg_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_bneg_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_bneg_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bneg_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_bneg_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.bneg.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_bneg_h_RES
   ret void
@@ -366,8 +366,8 @@ declare <8 x i16> @llvm.mips.bneg.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_bneg_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_bneg_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_bneg_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bneg_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_bneg_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_bneg_w_RES
   ret void
@@ -388,8 +388,8 @@ declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_bneg_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_bneg_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_bneg_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bneg_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_bneg_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.bneg.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_bneg_d_RES
   ret void
@@ -410,8 +410,8 @@ declare <2 x i64> @llvm.mips.bneg.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_bset_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bset_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_bset_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bset_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bset_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.bset.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_bset_b_RES
   ret void
@@ -432,8 +432,8 @@ declare <16 x i8> @llvm.mips.bset.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_bset_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_bset_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_bset_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bset_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_bset_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.bset.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_bset_h_RES
   ret void
@@ -454,8 +454,8 @@ declare <8 x i16> @llvm.mips.bset.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_bset_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_bset_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_bset_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bset_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_bset_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.bset.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_bset_w_RES
   ret void
@@ -476,8 +476,8 @@ declare <4 x i32> @llvm.mips.bset.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_bset_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_bset_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_bset_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bset_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_bset_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.bset.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_bset_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3r-c.ll b/test/CodeGen/Mips/msa/3r-c.ll
index 6ec92c284fec..a3913e0a27fd 100644
--- a/test/CodeGen/Mips/msa/3r-c.ll
+++ b/test/CodeGen/Mips/msa/3r-c.ll
@@ -10,8 +10,8 @@
 
 define void @llvm_mips_ceq_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_ceq_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_ceq_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_ceq_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_ceq_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.ceq.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_ceq_b_RES
   ret void
@@ -32,8 +32,8 @@ declare <16 x i8> @llvm.mips.ceq.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_ceq_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_ceq_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_ceq_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ceq_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_ceq_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.ceq.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_ceq_h_RES
   ret void
@@ -54,8 +54,8 @@ declare <8 x i16> @llvm.mips.ceq.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_ceq_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_ceq_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_ceq_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ceq_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_ceq_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.ceq.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_ceq_w_RES
   ret void
@@ -76,8 +76,8 @@ declare <4 x i32> @llvm.mips.ceq.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_ceq_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_ceq_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_ceq_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ceq_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_ceq_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.ceq.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_ceq_d_RES
   ret void
@@ -98,8 +98,8 @@ declare <2 x i64> @llvm.mips.ceq.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_cle_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_cle_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_cle_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_cle_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_cle_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.cle.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_cle_s_b_RES
   ret void
@@ -120,8 +120,8 @@ declare <16 x i8> @llvm.mips.cle.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_cle_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_cle_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_cle_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_cle_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_cle_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.cle.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_cle_s_h_RES
   ret void
@@ -142,8 +142,8 @@ declare <8 x i16> @llvm.mips.cle.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_cle_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_cle_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_cle_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_cle_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_cle_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.cle.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_cle_s_w_RES
   ret void
@@ -164,8 +164,8 @@ declare <4 x i32> @llvm.mips.cle.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_cle_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_cle_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_cle_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_cle_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_cle_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.cle.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_cle_s_d_RES
   ret void
@@ -186,8 +186,8 @@ declare <2 x i64> @llvm.mips.cle.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_cle_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_cle_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_cle_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_cle_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_cle_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.cle.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_cle_u_b_RES
   ret void
@@ -208,8 +208,8 @@ declare <16 x i8> @llvm.mips.cle.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_cle_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_cle_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_cle_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_cle_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_cle_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.cle.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_cle_u_h_RES
   ret void
@@ -230,8 +230,8 @@ declare <8 x i16> @llvm.mips.cle.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_cle_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_cle_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_cle_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_cle_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_cle_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.cle.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_cle_u_w_RES
   ret void
@@ -252,8 +252,8 @@ declare <4 x i32> @llvm.mips.cle.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_cle_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_cle_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_cle_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_cle_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_cle_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.cle.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_cle_u_d_RES
   ret void
@@ -274,8 +274,8 @@ declare <2 x i64> @llvm.mips.cle.u.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_clt_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_clt_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_clt_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clt_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_clt_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.clt.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_clt_s_b_RES
   ret void
@@ -296,8 +296,8 @@ declare <16 x i8> @llvm.mips.clt.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_clt_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_clt_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_clt_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clt_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_clt_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.clt.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_clt_s_h_RES
   ret void
@@ -318,8 +318,8 @@ declare <8 x i16> @llvm.mips.clt.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_clt_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_clt_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_clt_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clt_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_clt_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.clt.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_clt_s_w_RES
   ret void
@@ -340,8 +340,8 @@ declare <4 x i32> @llvm.mips.clt.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_clt_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_clt_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_clt_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clt_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_clt_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.clt.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_clt_s_d_RES
   ret void
@@ -362,8 +362,8 @@ declare <2 x i64> @llvm.mips.clt.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_clt_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_clt_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_clt_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clt_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_clt_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.clt.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_clt_u_b_RES
   ret void
@@ -384,8 +384,8 @@ declare <16 x i8> @llvm.mips.clt.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_clt_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_clt_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_clt_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clt_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_clt_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.clt.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_clt_u_h_RES
   ret void
@@ -406,8 +406,8 @@ declare <8 x i16> @llvm.mips.clt.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_clt_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_clt_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_clt_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clt_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_clt_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.clt.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_clt_u_w_RES
   ret void
@@ -428,8 +428,8 @@ declare <4 x i32> @llvm.mips.clt.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_clt_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_clt_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_clt_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clt_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_clt_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.clt.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_clt_u_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3r-d.ll b/test/CodeGen/Mips/msa/3r-d.ll
index 0099554a8eea..4fc32b76a7b2 100644
--- a/test/CodeGen/Mips/msa/3r-d.ll
+++ b/test/CodeGen/Mips/msa/3r-d.ll
@@ -10,8 +10,8 @@
 
 define void @llvm_mips_div_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_div_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_div_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_div_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_div_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.div.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_div_s_b_RES
   ret void
@@ -32,8 +32,8 @@ declare <16 x i8> @llvm.mips.div.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_div_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_div_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_div_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_div_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_div_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.div.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_div_s_h_RES
   ret void
@@ -54,8 +54,8 @@ declare <8 x i16> @llvm.mips.div.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_div_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_div_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_div_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_div_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_div_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.div.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_div_s_w_RES
   ret void
@@ -76,8 +76,8 @@ declare <4 x i32> @llvm.mips.div.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_div_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_div_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_div_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_div_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_div_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.div.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_div_s_d_RES
   ret void
@@ -95,8 +95,8 @@ declare <2 x i64> @llvm.mips.div.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @div_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_div_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_div_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_div_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_div_s_b_ARG2
   %2 = sdiv <16 x i8> %0, %1
   store <16 x i8> %2, <16 x i8>* @llvm_mips_div_s_b_RES
   ret void
@@ -111,8 +111,8 @@ entry:
 
 define void @div_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_div_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_div_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_div_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_div_s_h_ARG2
   %2 = sdiv <8 x i16> %0, %1
   store <8 x i16> %2, <8 x i16>* @llvm_mips_div_s_h_RES
   ret void
@@ -127,8 +127,8 @@ entry:
 
 define void @div_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_div_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_div_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_div_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_div_s_w_ARG2
   %2 = sdiv <4 x i32> %0, %1
   store <4 x i32> %2, <4 x i32>* @llvm_mips_div_s_w_RES
   ret void
@@ -143,8 +143,8 @@ entry:
 
 define void @div_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_div_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_div_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_div_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_div_s_d_ARG2
   %2 = sdiv <2 x i64> %0, %1
   store <2 x i64> %2, <2 x i64>* @llvm_mips_div_s_d_RES
   ret void
@@ -163,8 +163,8 @@ entry:
 
 define void @llvm_mips_div_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_div_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_div_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_div_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_div_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.div.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_div_u_b_RES
   ret void
@@ -185,8 +185,8 @@ declare <16 x i8> @llvm.mips.div.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_div_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_div_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_div_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_div_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_div_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.div.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_div_u_h_RES
   ret void
@@ -207,8 +207,8 @@ declare <8 x i16> @llvm.mips.div.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_div_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_div_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_div_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_div_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_div_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.div.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_div_u_w_RES
   ret void
@@ -229,8 +229,8 @@ declare <4 x i32> @llvm.mips.div.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_div_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_div_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_div_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_div_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_div_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.div.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_div_u_d_RES
   ret void
@@ -248,8 +248,8 @@ declare <2 x i64> @llvm.mips.div.u.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @div_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_div_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_div_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_div_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_div_u_b_ARG2
   %2 = udiv <16 x i8> %0, %1
   store <16 x i8> %2, <16 x i8>* @llvm_mips_div_u_b_RES
   ret void
@@ -264,8 +264,8 @@ entry:
 
 define void @div_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_div_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_div_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_div_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_div_u_h_ARG2
   %2 = udiv <8 x i16> %0, %1
   store <8 x i16> %2, <8 x i16>* @llvm_mips_div_u_h_RES
   ret void
@@ -280,8 +280,8 @@ entry:
 
 define void @div_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_div_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_div_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_div_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_div_u_w_ARG2
   %2 = udiv <4 x i32> %0, %1
   store <4 x i32> %2, <4 x i32>* @llvm_mips_div_u_w_RES
   ret void
@@ -296,8 +296,8 @@ entry:
 
 define void @div_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_div_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_div_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_div_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_div_u_d_ARG2
   %2 = udiv <2 x i64> %0, %1
   store <2 x i64> %2, <2 x i64>* @llvm_mips_div_u_d_RES
   ret void
@@ -326,8 +326,8 @@ entry:
 
 define void @llvm_mips_dotp_s_h_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_dotp_s_h_ARG1
-  %1 = load <16 x i8>* @llvm_mips_dotp_s_h_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_dotp_s_h_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_dotp_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.dotp.s.h(<16 x i8> %0, <16 x i8> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_dotp_s_h_RES
   ret void
@@ -353,8 +353,8 @@ declare <8 x i16> @llvm.mips.dotp.s.h(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_dotp_s_w_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_dotp_s_w_ARG1
-  %1 = load <8 x i16>* @llvm_mips_dotp_s_w_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_dotp_s_w_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_dotp_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.dotp.s.w(<8 x i16> %0, <8 x i16> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_dotp_s_w_RES
   ret void
@@ -377,8 +377,8 @@ declare <4 x i32> @llvm.mips.dotp.s.w(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_dotp_s_d_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_dotp_s_d_ARG1
-  %1 = load <4 x i32>* @llvm_mips_dotp_s_d_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_dotp_s_d_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_dotp_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.dotp.s.d(<4 x i32> %0, <4 x i32> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_dotp_s_d_RES
   ret void
@@ -409,8 +409,8 @@ declare <2 x i64> @llvm.mips.dotp.s.d(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_dotp_u_h_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_dotp_u_h_ARG1
-  %1 = load <16 x i8>* @llvm_mips_dotp_u_h_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_dotp_u_h_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_dotp_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.dotp.u.h(<16 x i8> %0, <16 x i8> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_dotp_u_h_RES
   ret void
@@ -436,8 +436,8 @@ declare <8 x i16> @llvm.mips.dotp.u.h(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_dotp_u_w_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_dotp_u_w_ARG1
-  %1 = load <8 x i16>* @llvm_mips_dotp_u_w_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_dotp_u_w_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_dotp_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.dotp.u.w(<8 x i16> %0, <8 x i16> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_dotp_u_w_RES
   ret void
@@ -460,8 +460,8 @@ declare <4 x i32> @llvm.mips.dotp.u.w(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_dotp_u_d_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_dotp_u_d_ARG1
-  %1 = load <4 x i32>* @llvm_mips_dotp_u_d_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_dotp_u_d_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_dotp_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.dotp.u.d(<4 x i32> %0, <4 x i32> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_dotp_u_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3r-i.ll b/test/CodeGen/Mips/msa/3r-i.ll
index 2ef30471b026..7147b756b15f 100644
--- a/test/CodeGen/Mips/msa/3r-i.ll
+++ b/test/CodeGen/Mips/msa/3r-i.ll
@@ -10,8 +10,8 @@
 
 define void @llvm_mips_ilvev_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_ilvev_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_ilvev_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_ilvev_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_ilvev_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.ilvev.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_ilvev_b_RES
   ret void
@@ -32,8 +32,8 @@ declare <16 x i8> @llvm.mips.ilvev.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_ilvev_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_ilvev_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_ilvev_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ilvev_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_ilvev_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.ilvev.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_ilvev_h_RES
   ret void
@@ -54,8 +54,8 @@ declare <8 x i16> @llvm.mips.ilvev.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_ilvev_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_ilvev_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_ilvev_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ilvev_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_ilvev_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.ilvev.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_ilvev_w_RES
   ret void
@@ -76,8 +76,8 @@ declare <4 x i32> @llvm.mips.ilvev.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_ilvev_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_ilvev_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_ilvev_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ilvev_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_ilvev_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.ilvev.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_ilvev_d_RES
   ret void
@@ -98,8 +98,8 @@ declare <2 x i64> @llvm.mips.ilvev.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_ilvl_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_ilvl_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_ilvl_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_ilvl_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_ilvl_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.ilvl.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_ilvl_b_RES
   ret void
@@ -120,8 +120,8 @@ declare <16 x i8> @llvm.mips.ilvl.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_ilvl_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_ilvl_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_ilvl_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ilvl_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_ilvl_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.ilvl.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_ilvl_h_RES
   ret void
@@ -142,8 +142,8 @@ declare <8 x i16> @llvm.mips.ilvl.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_ilvl_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_ilvl_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_ilvl_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ilvl_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_ilvl_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.ilvl.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_ilvl_w_RES
   ret void
@@ -164,8 +164,8 @@ declare <4 x i32> @llvm.mips.ilvl.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_ilvl_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_ilvl_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_ilvl_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ilvl_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_ilvl_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.ilvl.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_ilvl_d_RES
   ret void
@@ -186,8 +186,8 @@ declare <2 x i64> @llvm.mips.ilvl.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_ilvod_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_ilvod_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_ilvod_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_ilvod_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_ilvod_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.ilvod.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_ilvod_b_RES
   ret void
@@ -208,8 +208,8 @@ declare <16 x i8> @llvm.mips.ilvod.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_ilvod_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_ilvod_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_ilvod_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ilvod_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_ilvod_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.ilvod.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_ilvod_h_RES
   ret void
@@ -230,8 +230,8 @@ declare <8 x i16> @llvm.mips.ilvod.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_ilvod_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_ilvod_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_ilvod_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ilvod_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_ilvod_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.ilvod.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_ilvod_w_RES
   ret void
@@ -252,8 +252,8 @@ declare <4 x i32> @llvm.mips.ilvod.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_ilvod_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_ilvod_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_ilvod_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ilvod_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_ilvod_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.ilvod.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_ilvod_d_RES
   ret void
@@ -274,8 +274,8 @@ declare <2 x i64> @llvm.mips.ilvod.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_ilvr_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_ilvr_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_ilvr_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_ilvr_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_ilvr_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.ilvr.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_ilvr_b_RES
   ret void
@@ -296,8 +296,8 @@ declare <16 x i8> @llvm.mips.ilvr.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_ilvr_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_ilvr_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_ilvr_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ilvr_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_ilvr_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.ilvr.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_ilvr_h_RES
   ret void
@@ -318,8 +318,8 @@ declare <8 x i16> @llvm.mips.ilvr.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_ilvr_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_ilvr_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_ilvr_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ilvr_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_ilvr_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.ilvr.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_ilvr_w_RES
   ret void
@@ -340,8 +340,8 @@ declare <4 x i32> @llvm.mips.ilvr.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_ilvr_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_ilvr_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_ilvr_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ilvr_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_ilvr_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.ilvr.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_ilvr_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3r-m.ll b/test/CodeGen/Mips/msa/3r-m.ll
index ddfd720a2f84..39b4f7db3a48 100644
--- a/test/CodeGen/Mips/msa/3r-m.ll
+++ b/test/CodeGen/Mips/msa/3r-m.ll
@@ -10,8 +10,8 @@
 
 define void @llvm_mips_max_a_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_max_a_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_max_a_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_max_a_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_max_a_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.max.a.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_max_a_b_RES
   ret void
@@ -32,8 +32,8 @@ declare <16 x i8> @llvm.mips.max.a.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_max_a_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_max_a_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_max_a_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_max_a_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_max_a_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.max.a.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_max_a_h_RES
   ret void
@@ -54,8 +54,8 @@ declare <8 x i16> @llvm.mips.max.a.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_max_a_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_max_a_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_max_a_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_max_a_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_max_a_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.max.a.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_max_a_w_RES
   ret void
@@ -76,8 +76,8 @@ declare <4 x i32> @llvm.mips.max.a.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_max_a_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_max_a_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_max_a_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_max_a_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_max_a_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.max.a.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_max_a_d_RES
   ret void
@@ -98,8 +98,8 @@ declare <2 x i64> @llvm.mips.max.a.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_max_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_max_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_max_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_max_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_max_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.max.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_max_s_b_RES
   ret void
@@ -120,8 +120,8 @@ declare <16 x i8> @llvm.mips.max.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_max_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_max_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_max_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_max_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_max_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.max.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_max_s_h_RES
   ret void
@@ -142,8 +142,8 @@ declare <8 x i16> @llvm.mips.max.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_max_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_max_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_max_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_max_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_max_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.max.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_max_s_w_RES
   ret void
@@ -164,8 +164,8 @@ declare <4 x i32> @llvm.mips.max.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_max_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_max_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_max_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_max_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_max_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.max.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_max_s_d_RES
   ret void
@@ -186,8 +186,8 @@ declare <2 x i64> @llvm.mips.max.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_max_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_max_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_max_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_max_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_max_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.max.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_max_u_b_RES
   ret void
@@ -208,8 +208,8 @@ declare <16 x i8> @llvm.mips.max.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_max_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_max_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_max_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_max_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_max_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.max.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_max_u_h_RES
   ret void
@@ -230,8 +230,8 @@ declare <8 x i16> @llvm.mips.max.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_max_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_max_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_max_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_max_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_max_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.max.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_max_u_w_RES
   ret void
@@ -252,8 +252,8 @@ declare <4 x i32> @llvm.mips.max.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_max_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_max_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_max_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_max_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_max_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.max.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_max_u_d_RES
   ret void
@@ -274,8 +274,8 @@ declare <2 x i64> @llvm.mips.max.u.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_min_a_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_min_a_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_min_a_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_min_a_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_min_a_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.min.a.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_min_a_b_RES
   ret void
@@ -296,8 +296,8 @@ declare <16 x i8> @llvm.mips.min.a.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_min_a_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_min_a_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_min_a_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_min_a_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_min_a_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.min.a.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_min_a_h_RES
   ret void
@@ -318,8 +318,8 @@ declare <8 x i16> @llvm.mips.min.a.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_min_a_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_min_a_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_min_a_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_min_a_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_min_a_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.min.a.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_min_a_w_RES
   ret void
@@ -340,8 +340,8 @@ declare <4 x i32> @llvm.mips.min.a.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_min_a_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_min_a_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_min_a_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_min_a_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_min_a_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.min.a.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_min_a_d_RES
   ret void
@@ -362,8 +362,8 @@ declare <2 x i64> @llvm.mips.min.a.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_min_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_min_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_min_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_min_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_min_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.min.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_min_s_b_RES
   ret void
@@ -384,8 +384,8 @@ declare <16 x i8> @llvm.mips.min.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_min_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_min_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_min_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_min_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_min_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.min.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_min_s_h_RES
   ret void
@@ -406,8 +406,8 @@ declare <8 x i16> @llvm.mips.min.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_min_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_min_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_min_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_min_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_min_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.min.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_min_s_w_RES
   ret void
@@ -428,8 +428,8 @@ declare <4 x i32> @llvm.mips.min.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_min_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_min_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_min_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_min_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_min_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.min.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_min_s_d_RES
   ret void
@@ -450,8 +450,8 @@ declare <2 x i64> @llvm.mips.min.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_min_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_min_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_min_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_min_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_min_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.min.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_min_u_b_RES
   ret void
@@ -472,8 +472,8 @@ declare <16 x i8> @llvm.mips.min.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_min_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_min_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_min_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_min_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_min_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.min.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_min_u_h_RES
   ret void
@@ -494,8 +494,8 @@ declare <8 x i16> @llvm.mips.min.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_min_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_min_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_min_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_min_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_min_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.min.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_min_u_w_RES
   ret void
@@ -516,8 +516,8 @@ declare <4 x i32> @llvm.mips.min.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_min_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_min_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_min_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_min_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_min_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.min.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_min_u_d_RES
   ret void
@@ -538,8 +538,8 @@ declare <2 x i64> @llvm.mips.min.u.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_mod_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_mod_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_mod_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_mod_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_mod_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.mod.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_mod_s_b_RES
   ret void
@@ -560,8 +560,8 @@ declare <16 x i8> @llvm.mips.mod.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_mod_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_mod_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_mod_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_mod_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_mod_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.mod.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_mod_s_h_RES
   ret void
@@ -582,8 +582,8 @@ declare <8 x i16> @llvm.mips.mod.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_mod_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_mod_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_mod_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_mod_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_mod_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.mod.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_mod_s_w_RES
   ret void
@@ -604,8 +604,8 @@ declare <4 x i32> @llvm.mips.mod.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_mod_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_mod_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_mod_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_mod_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_mod_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.mod.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_mod_s_d_RES
   ret void
@@ -626,8 +626,8 @@ declare <2 x i64> @llvm.mips.mod.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_mod_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_mod_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_mod_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_mod_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_mod_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.mod.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_mod_u_b_RES
   ret void
@@ -648,8 +648,8 @@ declare <16 x i8> @llvm.mips.mod.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_mod_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_mod_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_mod_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_mod_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_mod_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.mod.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_mod_u_h_RES
   ret void
@@ -670,8 +670,8 @@ declare <8 x i16> @llvm.mips.mod.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_mod_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_mod_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_mod_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_mod_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_mod_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.mod.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_mod_u_w_RES
   ret void
@@ -692,8 +692,8 @@ declare <4 x i32> @llvm.mips.mod.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_mod_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_mod_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_mod_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_mod_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_mod_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.mod.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_mod_u_d_RES
   ret void
@@ -714,8 +714,8 @@ declare <2 x i64> @llvm.mips.mod.u.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_mulv_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_mulv_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_mulv_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_mulv_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_mulv_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.mulv.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_mulv_b_RES
   ret void
@@ -736,8 +736,8 @@ declare <16 x i8> @llvm.mips.mulv.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_mulv_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_mulv_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_mulv_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_mulv_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_mulv_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.mulv.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_mulv_h_RES
   ret void
@@ -758,8 +758,8 @@ declare <8 x i16> @llvm.mips.mulv.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_mulv_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_mulv_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_mulv_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_mulv_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_mulv_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.mulv.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_mulv_w_RES
   ret void
@@ -780,8 +780,8 @@ declare <4 x i32> @llvm.mips.mulv.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_mulv_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_mulv_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_mulv_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_mulv_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_mulv_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.mulv.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_mulv_d_RES
   ret void
@@ -798,8 +798,8 @@ declare <2 x i64> @llvm.mips.mulv.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @mulv_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_mulv_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_mulv_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_mulv_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_mulv_b_ARG2
   %2 = mul <16 x i8> %0, %1
   store <16 x i8> %2, <16 x i8>* @llvm_mips_mulv_b_RES
   ret void
@@ -814,8 +814,8 @@ entry:
 
 define void @mulv_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_mulv_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_mulv_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_mulv_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_mulv_h_ARG2
   %2 = mul <8 x i16> %0, %1
   store <8 x i16> %2, <8 x i16>* @llvm_mips_mulv_h_RES
   ret void
@@ -830,8 +830,8 @@ entry:
 
 define void @mulv_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_mulv_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_mulv_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_mulv_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_mulv_w_ARG2
   %2 = mul <4 x i32> %0, %1
   store <4 x i32> %2, <4 x i32>* @llvm_mips_mulv_w_RES
   ret void
@@ -846,8 +846,8 @@ entry:
 
 define void @mulv_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_mulv_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_mulv_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_mulv_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_mulv_d_ARG2
   %2 = mul <2 x i64> %0, %1
   store <2 x i64> %2, <2 x i64>* @llvm_mips_mulv_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3r-p.ll b/test/CodeGen/Mips/msa/3r-p.ll
index 852023b0824a..70b98aa8f9a1 100644
--- a/test/CodeGen/Mips/msa/3r-p.ll
+++ b/test/CodeGen/Mips/msa/3r-p.ll
@@ -10,8 +10,8 @@
 
 define void @llvm_mips_pckev_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_pckev_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_pckev_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_pckev_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_pckev_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.pckev.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_pckev_b_RES
   ret void
@@ -32,8 +32,8 @@ declare <16 x i8> @llvm.mips.pckev.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_pckev_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_pckev_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_pckev_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_pckev_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_pckev_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.pckev.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_pckev_h_RES
   ret void
@@ -54,8 +54,8 @@ declare <8 x i16> @llvm.mips.pckev.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_pckev_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_pckev_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_pckev_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_pckev_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_pckev_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.pckev.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_pckev_w_RES
   ret void
@@ -76,8 +76,8 @@ declare <4 x i32> @llvm.mips.pckev.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_pckev_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_pckev_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_pckev_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_pckev_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_pckev_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.pckev.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_pckev_d_RES
   ret void
@@ -98,8 +98,8 @@ declare <2 x i64> @llvm.mips.pckev.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_pckod_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_pckod_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_pckod_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_pckod_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_pckod_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.pckod.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_pckod_b_RES
   ret void
@@ -120,8 +120,8 @@ declare <16 x i8> @llvm.mips.pckod.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_pckod_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_pckod_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_pckod_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_pckod_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_pckod_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.pckod.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_pckod_h_RES
   ret void
@@ -142,8 +142,8 @@ declare <8 x i16> @llvm.mips.pckod.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_pckod_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_pckod_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_pckod_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_pckod_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_pckod_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.pckod.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_pckod_w_RES
   ret void
@@ -164,8 +164,8 @@ declare <4 x i32> @llvm.mips.pckod.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_pckod_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_pckod_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_pckod_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_pckod_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_pckod_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.pckod.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_pckod_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3r-s.ll b/test/CodeGen/Mips/msa/3r-s.ll
index 581c3bfd78af..d04c5ff165f2 100644
--- a/test/CodeGen/Mips/msa/3r-s.ll
+++ b/test/CodeGen/Mips/msa/3r-s.ll
@@ -11,9 +11,9 @@
 
 define void @llvm_mips_sld_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_sld_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_sld_b_ARG2
-  %2 = load i32* @llvm_mips_sld_b_ARG3
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sld_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_sld_b_ARG2
+  %2 = load i32, i32* @llvm_mips_sld_b_ARG3
   %3 = tail call <16 x i8> @llvm.mips.sld.b(<16 x i8> %0, <16 x i8> %1, i32 %2)
   store <16 x i8> %3, <16 x i8>* @llvm_mips_sld_b_RES
   ret void
@@ -39,9 +39,9 @@ declare <16 x i8> @llvm.mips.sld.b(<16 x i8>, <16 x i8>, i32) nounwind
 
 define void @llvm_mips_sld_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_sld_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_sld_h_ARG2
-  %2 = load i32* @llvm_mips_sld_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sld_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_sld_h_ARG2
+  %2 = load i32, i32* @llvm_mips_sld_h_ARG3
   %3 = tail call <8 x i16> @llvm.mips.sld.h(<8 x i16> %0, <8 x i16> %1, i32 %2)
   store <8 x i16> %3, <8 x i16>* @llvm_mips_sld_h_RES
   ret void
@@ -67,9 +67,9 @@ declare <8 x i16> @llvm.mips.sld.h(<8 x i16>, <8 x i16>, i32) nounwind
 
 define void @llvm_mips_sld_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_sld_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_sld_w_ARG2
-  %2 = load i32* @llvm_mips_sld_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sld_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_sld_w_ARG2
+  %2 = load i32, i32* @llvm_mips_sld_w_ARG3
   %3 = tail call <4 x i32> @llvm.mips.sld.w(<4 x i32> %0, <4 x i32> %1, i32 %2)
   store <4 x i32> %3, <4 x i32>* @llvm_mips_sld_w_RES
   ret void
@@ -95,9 +95,9 @@ declare <4 x i32> @llvm.mips.sld.w(<4 x i32>, <4 x i32>, i32) nounwind
 
 define void @llvm_mips_sld_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_sld_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_sld_d_ARG2
-  %2 = load i32* @llvm_mips_sld_d_ARG3
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sld_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_sld_d_ARG2
+  %2 = load i32, i32* @llvm_mips_sld_d_ARG3
   %3 = tail call <2 x i64> @llvm.mips.sld.d(<2 x i64> %0, <2 x i64> %1, i32 %2)
   store <2 x i64> %3, <2 x i64>* @llvm_mips_sld_d_RES
   ret void
@@ -122,8 +122,8 @@ declare <2 x i64> @llvm.mips.sld.d(<2 x i64>, <2 x i64>, i32) nounwind
 
 define void @llvm_mips_sll_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_sll_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_sll_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sll_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_sll_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.sll.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_sll_b_RES
   ret void
@@ -146,8 +146,8 @@ declare <16 x i8> @llvm.mips.sll.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_sll_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_sll_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_sll_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sll_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_sll_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.sll.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_sll_h_RES
   ret void
@@ -170,8 +170,8 @@ declare <8 x i16> @llvm.mips.sll.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_sll_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_sll_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_sll_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sll_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_sll_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.sll.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_sll_w_RES
   ret void
@@ -194,8 +194,8 @@ declare <4 x i32> @llvm.mips.sll.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_sll_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_sll_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_sll_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sll_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_sll_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.sll.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_sll_d_RES
   ret void
@@ -214,8 +214,8 @@ declare <2 x i64> @llvm.mips.sll.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @sll_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_sll_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_sll_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sll_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_sll_b_ARG2
   %2 = shl <16 x i8> %0, %1
   store <16 x i8> %2, <16 x i8>* @llvm_mips_sll_b_RES
   ret void
@@ -232,8 +232,8 @@ entry:
 
 define void @sll_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_sll_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_sll_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sll_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_sll_h_ARG2
   %2 = shl <8 x i16> %0, %1
   store <8 x i16> %2, <8 x i16>* @llvm_mips_sll_h_RES
   ret void
@@ -250,8 +250,8 @@ entry:
 
 define void @sll_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_sll_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_sll_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sll_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_sll_w_ARG2
   %2 = shl <4 x i32> %0, %1
   store <4 x i32> %2, <4 x i32>* @llvm_mips_sll_w_RES
   ret void
@@ -268,8 +268,8 @@ entry:
 
 define void @sll_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_sll_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_sll_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sll_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_sll_d_ARG2
   %2 = shl <2 x i64> %0, %1
   store <2 x i64> %2, <2 x i64>* @llvm_mips_sll_d_RES
   ret void
@@ -290,8 +290,8 @@ entry:
 
 define void @llvm_mips_sra_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_sra_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_sra_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sra_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_sra_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.sra.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_sra_b_RES
   ret void
@@ -314,8 +314,8 @@ declare <16 x i8> @llvm.mips.sra.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_sra_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_sra_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_sra_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sra_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_sra_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.sra.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_sra_h_RES
   ret void
@@ -338,8 +338,8 @@ declare <8 x i16> @llvm.mips.sra.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_sra_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_sra_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_sra_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sra_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_sra_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.sra.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_sra_w_RES
   ret void
@@ -362,8 +362,8 @@ declare <4 x i32> @llvm.mips.sra.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_sra_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_sra_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_sra_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sra_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_sra_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.sra.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_sra_d_RES
   ret void
@@ -383,8 +383,8 @@ declare <2 x i64> @llvm.mips.sra.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @sra_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_sra_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_sra_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sra_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_sra_b_ARG2
   %2 = ashr <16 x i8> %0, %1
   store <16 x i8> %2, <16 x i8>* @llvm_mips_sra_b_RES
   ret void
@@ -401,8 +401,8 @@ entry:
 
 define void @sra_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_sra_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_sra_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sra_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_sra_h_ARG2
   %2 = ashr <8 x i16> %0, %1
   store <8 x i16> %2, <8 x i16>* @llvm_mips_sra_h_RES
   ret void
@@ -419,8 +419,8 @@ entry:
 
 define void @sra_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_sra_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_sra_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sra_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_sra_w_ARG2
   %2 = ashr <4 x i32> %0, %1
   store <4 x i32> %2, <4 x i32>* @llvm_mips_sra_w_RES
   ret void
@@ -437,8 +437,8 @@ entry:
 
 define void @sra_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_sra_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_sra_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sra_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_sra_d_ARG2
   %2 = ashr <2 x i64> %0, %1
   store <2 x i64> %2, <2 x i64>* @llvm_mips_sra_d_RES
   ret void
@@ -459,8 +459,8 @@ entry:
 
 define void @llvm_mips_srar_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_srar_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_srar_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_srar_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_srar_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.srar.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_srar_b_RES
   ret void
@@ -483,8 +483,8 @@ declare <16 x i8> @llvm.mips.srar.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_srar_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_srar_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_srar_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_srar_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_srar_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.srar.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_srar_h_RES
   ret void
@@ -507,8 +507,8 @@ declare <8 x i16> @llvm.mips.srar.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_srar_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_srar_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_srar_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_srar_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_srar_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.srar.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_srar_w_RES
   ret void
@@ -531,8 +531,8 @@ declare <4 x i32> @llvm.mips.srar.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_srar_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_srar_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_srar_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_srar_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_srar_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.srar.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_srar_d_RES
   ret void
@@ -555,8 +555,8 @@ declare <2 x i64> @llvm.mips.srar.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_srl_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_srl_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_srl_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_srl_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_srl_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.srl.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_srl_b_RES
   ret void
@@ -579,8 +579,8 @@ declare <16 x i8> @llvm.mips.srl.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_srl_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_srl_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_srl_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_srl_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_srl_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.srl.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_srl_h_RES
   ret void
@@ -603,8 +603,8 @@ declare <8 x i16> @llvm.mips.srl.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_srl_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_srl_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_srl_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_srl_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_srl_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.srl.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_srl_w_RES
   ret void
@@ -627,8 +627,8 @@ declare <4 x i32> @llvm.mips.srl.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_srl_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_srl_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_srl_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_srl_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_srl_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.srl.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_srl_d_RES
   ret void
@@ -651,8 +651,8 @@ declare <2 x i64> @llvm.mips.srl.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_srlr_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_srlr_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_srlr_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_srlr_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_srlr_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.srlr.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_srlr_b_RES
   ret void
@@ -675,8 +675,8 @@ declare <16 x i8> @llvm.mips.srlr.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_srlr_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_srlr_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_srlr_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_srlr_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_srlr_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.srlr.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_srlr_h_RES
   ret void
@@ -699,8 +699,8 @@ declare <8 x i16> @llvm.mips.srlr.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_srlr_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_srlr_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_srlr_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_srlr_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_srlr_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.srlr.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_srlr_w_RES
   ret void
@@ -723,8 +723,8 @@ declare <4 x i32> @llvm.mips.srlr.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_srlr_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_srlr_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_srlr_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_srlr_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_srlr_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.srlr.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_srlr_d_RES
   ret void
@@ -744,8 +744,8 @@ declare <2 x i64> @llvm.mips.srlr.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @srl_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_srl_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_srl_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_srl_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_srl_b_ARG2
   %2 = lshr <16 x i8> %0, %1
   store <16 x i8> %2, <16 x i8>* @llvm_mips_srl_b_RES
   ret void
@@ -762,8 +762,8 @@ entry:
 
 define void @srl_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_srl_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_srl_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_srl_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_srl_h_ARG2
   %2 = lshr <8 x i16> %0, %1
   store <8 x i16> %2, <8 x i16>* @llvm_mips_srl_h_RES
   ret void
@@ -780,8 +780,8 @@ entry:
 
 define void @srl_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_srl_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_srl_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_srl_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_srl_w_ARG2
   %2 = lshr <4 x i32> %0, %1
   store <4 x i32> %2, <4 x i32>* @llvm_mips_srl_w_RES
   ret void
@@ -798,8 +798,8 @@ entry:
 
 define void @srl_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_srl_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_srl_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_srl_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_srl_d_ARG2
   %2 = lshr <2 x i64> %0, %1
   store <2 x i64> %2, <2 x i64>* @llvm_mips_srl_d_RES
   ret void
@@ -820,8 +820,8 @@ entry:
 
 define void @llvm_mips_subs_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_subs_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_subs_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_subs_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_subs_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.subs.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_subs_s_b_RES
   ret void
@@ -844,8 +844,8 @@ declare <16 x i8> @llvm.mips.subs.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_subs_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_subs_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_subs_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_subs_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_subs_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.subs.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_subs_s_h_RES
   ret void
@@ -868,8 +868,8 @@ declare <8 x i16> @llvm.mips.subs.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_subs_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_subs_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_subs_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_subs_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_subs_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.subs.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_subs_s_w_RES
   ret void
@@ -892,8 +892,8 @@ declare <4 x i32> @llvm.mips.subs.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_subs_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_subs_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_subs_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_subs_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_subs_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.subs.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_subs_s_d_RES
   ret void
@@ -916,8 +916,8 @@ declare <2 x i64> @llvm.mips.subs.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_subs_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_subs_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_subs_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_subs_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_subs_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.subs.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_subs_u_b_RES
   ret void
@@ -940,8 +940,8 @@ declare <16 x i8> @llvm.mips.subs.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_subs_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_subs_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_subs_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_subs_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_subs_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.subs.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_subs_u_h_RES
   ret void
@@ -964,8 +964,8 @@ declare <8 x i16> @llvm.mips.subs.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_subs_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_subs_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_subs_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_subs_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_subs_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.subs.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_subs_u_w_RES
   ret void
@@ -988,8 +988,8 @@ declare <4 x i32> @llvm.mips.subs.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_subs_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_subs_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_subs_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_subs_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_subs_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.subs.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_subs_u_d_RES
   ret void
@@ -1012,8 +1012,8 @@ declare <2 x i64> @llvm.mips.subs.u.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_subsus_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_subsus_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_subsus_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_subsus_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_subsus_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.subsus.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_subsus_u_b_RES
   ret void
@@ -1036,8 +1036,8 @@ declare <16 x i8> @llvm.mips.subsus.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_subsus_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_subsus_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_subsus_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_subsus_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_subsus_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.subsus.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_subsus_u_h_RES
   ret void
@@ -1060,8 +1060,8 @@ declare <8 x i16> @llvm.mips.subsus.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_subsus_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_subsus_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_subsus_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_subsus_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_subsus_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.subsus.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_subsus_u_w_RES
   ret void
@@ -1084,8 +1084,8 @@ declare <4 x i32> @llvm.mips.subsus.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_subsus_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_subsus_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_subsus_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_subsus_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_subsus_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.subsus.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_subsus_u_d_RES
   ret void
@@ -1108,8 +1108,8 @@ declare <2 x i64> @llvm.mips.subsus.u.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_subsuu_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_subsuu_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_subsuu_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_subsuu_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_subsuu_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.subsuu.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_subsuu_s_b_RES
   ret void
@@ -1132,8 +1132,8 @@ declare <16 x i8> @llvm.mips.subsuu.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_subsuu_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_subsuu_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_subsuu_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_subsuu_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_subsuu_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.subsuu.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_subsuu_s_h_RES
   ret void
@@ -1156,8 +1156,8 @@ declare <8 x i16> @llvm.mips.subsuu.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_subsuu_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_subsuu_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_subsuu_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_subsuu_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_subsuu_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.subsuu.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_subsuu_s_w_RES
   ret void
@@ -1180,8 +1180,8 @@ declare <4 x i32> @llvm.mips.subsuu.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_subsuu_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_subsuu_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_subsuu_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_subsuu_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_subsuu_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.subsuu.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_subsuu_s_d_RES
   ret void
@@ -1204,8 +1204,8 @@ declare <2 x i64> @llvm.mips.subsuu.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_subv_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_subv_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_subv_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_subv_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_subv_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.subv.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_subv_b_RES
   ret void
@@ -1228,8 +1228,8 @@ declare <16 x i8> @llvm.mips.subv.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_subv_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_subv_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_subv_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_subv_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_subv_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.subv.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_subv_h_RES
   ret void
@@ -1252,8 +1252,8 @@ declare <8 x i16> @llvm.mips.subv.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_subv_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_subv_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_subv_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_subv_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_subv_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.subv.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_subv_w_RES
   ret void
@@ -1276,8 +1276,8 @@ declare <4 x i32> @llvm.mips.subv.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_subv_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_subv_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_subv_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_subv_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_subv_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.subv.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_subv_d_RES
   ret void
@@ -1297,8 +1297,8 @@ declare <2 x i64> @llvm.mips.subv.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @subv_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_subv_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_subv_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_subv_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_subv_b_ARG2
   %2 = sub <16 x i8> %0, %1
   store <16 x i8> %2, <16 x i8>* @llvm_mips_subv_b_RES
   ret void
@@ -1315,8 +1315,8 @@ entry:
 
 define void @subv_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_subv_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_subv_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_subv_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_subv_h_ARG2
   %2 = sub <8 x i16> %0, %1
   store <8 x i16> %2, <8 x i16>* @llvm_mips_subv_h_RES
   ret void
@@ -1333,8 +1333,8 @@ entry:
 
 define void @subv_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_subv_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_subv_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_subv_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_subv_w_ARG2
   %2 = sub <4 x i32> %0, %1
   store <4 x i32> %2, <4 x i32>* @llvm_mips_subv_w_RES
   ret void
@@ -1351,8 +1351,8 @@ entry:
 
 define void @subv_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_subv_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_subv_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_subv_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_subv_d_ARG2
   %2 = sub <2 x i64> %0, %1
   store <2 x i64> %2, <2 x i64>* @llvm_mips_subv_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3r-v.ll b/test/CodeGen/Mips/msa/3r-v.ll
index c9693f90d556..2d36da40d2b1 100644
--- a/test/CodeGen/Mips/msa/3r-v.ll
+++ b/test/CodeGen/Mips/msa/3r-v.ll
@@ -11,9 +11,9 @@
 
 define void @llvm_mips_vshf_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_vshf_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_vshf_b_ARG2
-  %2 = load <16 x i8>* @llvm_mips_vshf_b_ARG3
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_vshf_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_vshf_b_ARG2
+  %2 = load <16 x i8>, <16 x i8>* @llvm_mips_vshf_b_ARG3
   %3 = tail call <16 x i8> @llvm.mips.vshf.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)
   store <16 x i8> %3, <16 x i8>* @llvm_mips_vshf_b_RES
   ret void
@@ -36,9 +36,9 @@ declare <16 x i8> @llvm.mips.vshf.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_vshf_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_vshf_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_vshf_h_ARG2
-  %2 = load <8 x i16>* @llvm_mips_vshf_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_vshf_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_vshf_h_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_vshf_h_ARG3
   %3 = tail call <8 x i16> @llvm.mips.vshf.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
   store <8 x i16> %3, <8 x i16>* @llvm_mips_vshf_h_RES
   ret void
@@ -61,9 +61,9 @@ declare <8 x i16> @llvm.mips.vshf.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_vshf_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_vshf_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_vshf_w_ARG2
-  %2 = load <4 x i32>* @llvm_mips_vshf_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_vshf_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_vshf_w_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_vshf_w_ARG3
   %3 = tail call <4 x i32> @llvm.mips.vshf.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
   store <4 x i32> %3, <4 x i32>* @llvm_mips_vshf_w_RES
   ret void
@@ -86,9 +86,9 @@ declare <4 x i32> @llvm.mips.vshf.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_vshf_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_vshf_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_vshf_d_ARG2
-  %2 = load <2 x i64>* @llvm_mips_vshf_d_ARG3
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_vshf_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_vshf_d_ARG2
+  %2 = load <2 x i64>, <2 x i64>* @llvm_mips_vshf_d_ARG3
   %3 = tail call <2 x i64> @llvm.mips.vshf.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2)
   store <2 x i64> %3, <2 x i64>* @llvm_mips_vshf_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3r_4r.ll b/test/CodeGen/Mips/msa/3r_4r.ll
index b7fd7283788c..73d104c68c53 100644
--- a/test/CodeGen/Mips/msa/3r_4r.ll
+++ b/test/CodeGen/Mips/msa/3r_4r.ll
@@ -11,9 +11,9 @@
 
 define void @llvm_mips_maddv_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_maddv_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_maddv_b_ARG2
-  %2 = load <16 x i8>* @llvm_mips_maddv_b_ARG3
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_maddv_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_maddv_b_ARG2
+  %2 = load <16 x i8>, <16 x i8>* @llvm_mips_maddv_b_ARG3
   %3 = tail call <16 x i8> @llvm.mips.maddv.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)
   store <16 x i8> %3, <16 x i8>* @llvm_mips_maddv_b_RES
   ret void
@@ -36,9 +36,9 @@ declare <16 x i8> @llvm.mips.maddv.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_maddv_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_maddv_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_maddv_h_ARG2
-  %2 = load <8 x i16>* @llvm_mips_maddv_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_maddv_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_maddv_h_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_maddv_h_ARG3
   %3 = tail call <8 x i16> @llvm.mips.maddv.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
   store <8 x i16> %3, <8 x i16>* @llvm_mips_maddv_h_RES
   ret void
@@ -61,9 +61,9 @@ declare <8 x i16> @llvm.mips.maddv.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_maddv_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_maddv_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_maddv_w_ARG2
-  %2 = load <4 x i32>* @llvm_mips_maddv_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_maddv_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_maddv_w_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_maddv_w_ARG3
   %3 = tail call <4 x i32> @llvm.mips.maddv.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
   store <4 x i32> %3, <4 x i32>* @llvm_mips_maddv_w_RES
   ret void
@@ -86,9 +86,9 @@ declare <4 x i32> @llvm.mips.maddv.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_maddv_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_maddv_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_maddv_d_ARG2
-  %2 = load <2 x i64>* @llvm_mips_maddv_d_ARG3
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_maddv_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_maddv_d_ARG2
+  %2 = load <2 x i64>, <2 x i64>* @llvm_mips_maddv_d_ARG3
   %3 = tail call <2 x i64> @llvm.mips.maddv.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2)
   store <2 x i64> %3, <2 x i64>* @llvm_mips_maddv_d_RES
   ret void
@@ -111,9 +111,9 @@ declare <2 x i64> @llvm.mips.maddv.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_msubv_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_msubv_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_msubv_b_ARG2
-  %2 = load <16 x i8>* @llvm_mips_msubv_b_ARG3
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_msubv_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_msubv_b_ARG2
+  %2 = load <16 x i8>, <16 x i8>* @llvm_mips_msubv_b_ARG3
   %3 = tail call <16 x i8> @llvm.mips.msubv.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)
   store <16 x i8> %3, <16 x i8>* @llvm_mips_msubv_b_RES
   ret void
@@ -136,9 +136,9 @@ declare <16 x i8> @llvm.mips.msubv.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_msubv_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_msubv_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_msubv_h_ARG2
-  %2 = load <8 x i16>* @llvm_mips_msubv_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_msubv_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_msubv_h_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_msubv_h_ARG3
   %3 = tail call <8 x i16> @llvm.mips.msubv.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
   store <8 x i16> %3, <8 x i16>* @llvm_mips_msubv_h_RES
   ret void
@@ -161,9 +161,9 @@ declare <8 x i16> @llvm.mips.msubv.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_msubv_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_msubv_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_msubv_w_ARG2
-  %2 = load <4 x i32>* @llvm_mips_msubv_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_msubv_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_msubv_w_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_msubv_w_ARG3
   %3 = tail call <4 x i32> @llvm.mips.msubv.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
   store <4 x i32> %3, <4 x i32>* @llvm_mips_msubv_w_RES
   ret void
@@ -186,9 +186,9 @@ declare <4 x i32> @llvm.mips.msubv.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_msubv_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_msubv_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_msubv_d_ARG2
-  %2 = load <2 x i64>* @llvm_mips_msubv_d_ARG3
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_msubv_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_msubv_d_ARG2
+  %2 = load <2 x i64>, <2 x i64>* @llvm_mips_msubv_d_ARG3
   %3 = tail call <2 x i64> @llvm.mips.msubv.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2)
   store <2 x i64> %3, <2 x i64>* @llvm_mips_msubv_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3r_4r_widen.ll b/test/CodeGen/Mips/msa/3r_4r_widen.ll
index 7063e4566a78..fe248eeb566b 100644
--- a/test/CodeGen/Mips/msa/3r_4r_widen.ll
+++ b/test/CodeGen/Mips/msa/3r_4r_widen.ll
@@ -12,9 +12,9 @@
 
 define void @llvm_mips_dpadd_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_dpadd_s_h_ARG1
-  %1 = load <16 x i8>* @llvm_mips_dpadd_s_h_ARG2
-  %2 = load <16 x i8>* @llvm_mips_dpadd_s_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_s_h_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_dpadd_s_h_ARG2
+  %2 = load <16 x i8>, <16 x i8>* @llvm_mips_dpadd_s_h_ARG3
   %3 = tail call <8 x i16> @llvm.mips.dpadd.s.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2)
   store <8 x i16> %3, <8 x i16>* @llvm_mips_dpadd_s_h_RES
   ret void
@@ -37,9 +37,9 @@ declare <8 x i16> @llvm.mips.dpadd.s.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_dpadd_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_dpadd_s_w_ARG1
-  %1 = load <8 x i16>* @llvm_mips_dpadd_s_w_ARG2
-  %2 = load <8 x i16>* @llvm_mips_dpadd_s_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_s_w_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_s_w_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_s_w_ARG3
   %3 = tail call <4 x i32> @llvm.mips.dpadd.s.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2)
   store <4 x i32> %3, <4 x i32>* @llvm_mips_dpadd_s_w_RES
   ret void
@@ -62,9 +62,9 @@ declare <4 x i32> @llvm.mips.dpadd.s.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_dpadd_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_dpadd_s_d_ARG1
-  %1 = load <4 x i32>* @llvm_mips_dpadd_s_d_ARG2
-  %2 = load <4 x i32>* @llvm_mips_dpadd_s_d_ARG3
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_dpadd_s_d_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_s_d_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_s_d_ARG3
   %3 = tail call <2 x i64> @llvm.mips.dpadd.s.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2)
   store <2 x i64> %3, <2 x i64>* @llvm_mips_dpadd_s_d_RES
   ret void
@@ -87,9 +87,9 @@ declare <2 x i64> @llvm.mips.dpadd.s.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_dpadd_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_dpadd_u_h_ARG1
-  %1 = load <16 x i8>* @llvm_mips_dpadd_u_h_ARG2
-  %2 = load <16 x i8>* @llvm_mips_dpadd_u_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_u_h_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_dpadd_u_h_ARG2
+  %2 = load <16 x i8>, <16 x i8>* @llvm_mips_dpadd_u_h_ARG3
   %3 = tail call <8 x i16> @llvm.mips.dpadd.u.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2)
   store <8 x i16> %3, <8 x i16>* @llvm_mips_dpadd_u_h_RES
   ret void
@@ -112,9 +112,9 @@ declare <8 x i16> @llvm.mips.dpadd.u.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_dpadd_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_dpadd_u_w_ARG1
-  %1 = load <8 x i16>* @llvm_mips_dpadd_u_w_ARG2
-  %2 = load <8 x i16>* @llvm_mips_dpadd_u_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_u_w_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_u_w_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_u_w_ARG3
   %3 = tail call <4 x i32> @llvm.mips.dpadd.u.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2)
   store <4 x i32> %3, <4 x i32>* @llvm_mips_dpadd_u_w_RES
   ret void
@@ -137,9 +137,9 @@ declare <4 x i32> @llvm.mips.dpadd.u.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_dpadd_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_dpadd_u_d_ARG1
-  %1 = load <4 x i32>* @llvm_mips_dpadd_u_d_ARG2
-  %2 = load <4 x i32>* @llvm_mips_dpadd_u_d_ARG3
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_dpadd_u_d_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_u_d_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_u_d_ARG3
   %3 = tail call <2 x i64> @llvm.mips.dpadd.u.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2)
   store <2 x i64> %3, <2 x i64>* @llvm_mips_dpadd_u_d_RES
   ret void
@@ -162,9 +162,9 @@ declare <2 x i64> @llvm.mips.dpadd.u.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_dpsub_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_dpsub_s_h_ARG1
-  %1 = load <16 x i8>* @llvm_mips_dpsub_s_h_ARG2
-  %2 = load <16 x i8>* @llvm_mips_dpsub_s_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_dpsub_s_h_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_dpsub_s_h_ARG2
+  %2 = load <16 x i8>, <16 x i8>* @llvm_mips_dpsub_s_h_ARG3
   %3 = tail call <8 x i16> @llvm.mips.dpsub.s.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2)
   store <8 x i16> %3, <8 x i16>* @llvm_mips_dpsub_s_h_RES
   ret void
@@ -187,9 +187,9 @@ declare <8 x i16> @llvm.mips.dpsub.s.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_dpsub_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_dpsub_s_w_ARG1
-  %1 = load <8 x i16>* @llvm_mips_dpsub_s_w_ARG2
-  %2 = load <8 x i16>* @llvm_mips_dpsub_s_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_dpsub_s_w_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_dpsub_s_w_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_dpsub_s_w_ARG3
   %3 = tail call <4 x i32> @llvm.mips.dpsub.s.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2)
   store <4 x i32> %3, <4 x i32>* @llvm_mips_dpsub_s_w_RES
   ret void
@@ -212,9 +212,9 @@ declare <4 x i32> @llvm.mips.dpsub.s.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_dpsub_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_dpsub_s_d_ARG1
-  %1 = load <4 x i32>* @llvm_mips_dpsub_s_d_ARG2
-  %2 = load <4 x i32>* @llvm_mips_dpsub_s_d_ARG3
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_dpsub_s_d_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_dpsub_s_d_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_dpsub_s_d_ARG3
   %3 = tail call <2 x i64> @llvm.mips.dpsub.s.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2)
   store <2 x i64> %3, <2 x i64>* @llvm_mips_dpsub_s_d_RES
   ret void
@@ -237,9 +237,9 @@ declare <2 x i64> @llvm.mips.dpsub.s.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_dpsub_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_dpsub_u_h_ARG1
-  %1 = load <16 x i8>* @llvm_mips_dpsub_u_h_ARG2
-  %2 = load <16 x i8>* @llvm_mips_dpsub_u_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_dpsub_u_h_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_dpsub_u_h_ARG2
+  %2 = load <16 x i8>, <16 x i8>* @llvm_mips_dpsub_u_h_ARG3
   %3 = tail call <8 x i16> @llvm.mips.dpsub.u.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2)
   store <8 x i16> %3, <8 x i16>* @llvm_mips_dpsub_u_h_RES
   ret void
@@ -262,9 +262,9 @@ declare <8 x i16> @llvm.mips.dpsub.u.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_dpsub_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_dpsub_u_w_ARG1
-  %1 = load <8 x i16>* @llvm_mips_dpsub_u_w_ARG2
-  %2 = load <8 x i16>* @llvm_mips_dpsub_u_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_dpsub_u_w_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_dpsub_u_w_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_dpsub_u_w_ARG3
   %3 = tail call <4 x i32> @llvm.mips.dpsub.u.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2)
   store <4 x i32> %3, <4 x i32>* @llvm_mips_dpsub_u_w_RES
   ret void
@@ -287,9 +287,9 @@ declare <4 x i32> @llvm.mips.dpsub.u.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_dpsub_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_dpsub_u_d_ARG1
-  %1 = load <4 x i32>* @llvm_mips_dpsub_u_d_ARG2
-  %2 = load <4 x i32>* @llvm_mips_dpsub_u_d_ARG3
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_dpsub_u_d_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_dpsub_u_d_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_dpsub_u_d_ARG3
   %3 = tail call <2 x i64> @llvm.mips.dpsub.u.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2)
   store <2 x i64> %3, <2 x i64>* @llvm_mips_dpsub_u_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3r_splat.ll b/test/CodeGen/Mips/msa/3r_splat.ll
index 6b0cb26f8c81..56d26b030de9 100644
--- a/test/CodeGen/Mips/msa/3r_splat.ll
+++ b/test/CodeGen/Mips/msa/3r_splat.ll
@@ -11,7 +11,7 @@
 
 define void @llvm_mips_splat_b_test(i32 %a) nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_splat_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_splat_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.splat.b(<16 x i8> %0, i32 %a)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_splat_b_RES
   ret void
@@ -32,7 +32,7 @@ declare <16 x i8> @llvm.mips.splat.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_splat_h_test(i32 %a) nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_splat_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_splat_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.splat.h(<8 x i16> %0, i32 %a)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_splat_h_RES
   ret void
@@ -53,7 +53,7 @@ declare <8 x i16> @llvm.mips.splat.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_splat_w_test(i32 %a) nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_splat_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_splat_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.splat.w(<4 x i32> %0, i32 %a)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_splat_w_RES
   ret void
@@ -74,7 +74,7 @@ declare <4 x i32> @llvm.mips.splat.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_splat_d_test(i32 %a) nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_splat_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_splat_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.splat.d(<2 x i64> %0, i32 %a)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_splat_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3rf.ll b/test/CodeGen/Mips/msa/3rf.ll
index ae665afcc950..dce0c275e8da 100644
--- a/test/CodeGen/Mips/msa/3rf.ll
+++ b/test/CodeGen/Mips/msa/3rf.ll
@@ -9,8 +9,8 @@
 
 define void @llvm_mips_fadd_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fadd_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fadd_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fadd_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fadd_w_ARG2
   %2 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %1)
   store <4 x float> %2, <4 x float>* @llvm_mips_fadd_w_RES
   ret void
@@ -31,8 +31,8 @@ declare <4 x float> @llvm.mips.fadd.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fadd_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fadd_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fadd_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fadd_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fadd_d_ARG2
   %2 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %1)
   store <2 x double> %2, <2 x double>* @llvm_mips_fadd_d_RES
   ret void
@@ -49,8 +49,8 @@ declare <2 x double> @llvm.mips.fadd.d(<2 x double>, <2 x double>) nounwind
 
 define void @fadd_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fadd_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fadd_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fadd_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fadd_w_ARG2
   %2 = fadd <4 x float> %0, %1
   store <4 x float> %2, <4 x float>* @llvm_mips_fadd_w_RES
   ret void
@@ -65,8 +65,8 @@ entry:
 
 define void @fadd_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fadd_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fadd_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fadd_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fadd_d_ARG2
   %2 = fadd <2 x double> %0, %1
   store <2 x double> %2, <2 x double>* @llvm_mips_fadd_d_RES
   ret void
@@ -85,8 +85,8 @@ entry:
 
 define void @llvm_mips_fdiv_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fdiv_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fdiv_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fdiv_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fdiv_w_ARG2
   %2 = tail call <4 x float> @llvm.mips.fdiv.w(<4 x float> %0, <4 x float> %1)
   store <4 x float> %2, <4 x float>* @llvm_mips_fdiv_w_RES
   ret void
@@ -107,8 +107,8 @@ declare <4 x float> @llvm.mips.fdiv.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fdiv_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fdiv_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fdiv_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fdiv_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fdiv_d_ARG2
   %2 = tail call <2 x double> @llvm.mips.fdiv.d(<2 x double> %0, <2 x double> %1)
   store <2 x double> %2, <2 x double>* @llvm_mips_fdiv_d_RES
   ret void
@@ -125,8 +125,8 @@ declare <2 x double> @llvm.mips.fdiv.d(<2 x double>, <2 x double>) nounwind
 
 define void @fdiv_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fdiv_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fdiv_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fdiv_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fdiv_w_ARG2
   %2 = fdiv <4 x float> %0, %1
   store <4 x float> %2, <4 x float>* @llvm_mips_fdiv_w_RES
   ret void
@@ -141,8 +141,8 @@ entry:
 
 define void @fdiv_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fdiv_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fdiv_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fdiv_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fdiv_d_ARG2
   %2 = fdiv <2 x double> %0, %1
   store <2 x double> %2, <2 x double>* @llvm_mips_fdiv_d_RES
   ret void
@@ -161,8 +161,8 @@ entry:
 
 define void @llvm_mips_fmin_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fmin_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fmin_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fmin_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fmin_w_ARG2
   %2 = tail call <4 x float> @llvm.mips.fmin.w(<4 x float> %0, <4 x float> %1)
   store <4 x float> %2, <4 x float>* @llvm_mips_fmin_w_RES
   ret void
@@ -183,8 +183,8 @@ declare <4 x float> @llvm.mips.fmin.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fmin_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fmin_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fmin_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fmin_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fmin_d_ARG2
   %2 = tail call <2 x double> @llvm.mips.fmin.d(<2 x double> %0, <2 x double> %1)
   store <2 x double> %2, <2 x double>* @llvm_mips_fmin_d_RES
   ret void
@@ -205,8 +205,8 @@ declare <2 x double> @llvm.mips.fmin.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fmin_a_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fmin_a_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fmin_a_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fmin_a_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fmin_a_w_ARG2
   %2 = tail call <4 x float> @llvm.mips.fmin.a.w(<4 x float> %0, <4 x float> %1)
   store <4 x float> %2, <4 x float>* @llvm_mips_fmin_a_w_RES
   ret void
@@ -227,8 +227,8 @@ declare <4 x float> @llvm.mips.fmin.a.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fmin_a_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fmin_a_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fmin_a_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fmin_a_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fmin_a_d_ARG2
   %2 = tail call <2 x double> @llvm.mips.fmin.a.d(<2 x double> %0, <2 x double> %1)
   store <2 x double> %2, <2 x double>* @llvm_mips_fmin_a_d_RES
   ret void
@@ -249,8 +249,8 @@ declare <2 x double> @llvm.mips.fmin.a.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fmax_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fmax_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fmax_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fmax_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fmax_w_ARG2
   %2 = tail call <4 x float> @llvm.mips.fmax.w(<4 x float> %0, <4 x float> %1)
   store <4 x float> %2, <4 x float>* @llvm_mips_fmax_w_RES
   ret void
@@ -271,8 +271,8 @@ declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fmax_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fmax_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fmax_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fmax_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fmax_d_ARG2
   %2 = tail call <2 x double> @llvm.mips.fmax.d(<2 x double> %0, <2 x double> %1)
   store <2 x double> %2, <2 x double>* @llvm_mips_fmax_d_RES
   ret void
@@ -293,8 +293,8 @@ declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fmax_a_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fmax_a_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fmax_a_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fmax_a_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fmax_a_w_ARG2
   %2 = tail call <4 x float> @llvm.mips.fmax.a.w(<4 x float> %0, <4 x float> %1)
   store <4 x float> %2, <4 x float>* @llvm_mips_fmax_a_w_RES
   ret void
@@ -315,8 +315,8 @@ declare <4 x float> @llvm.mips.fmax.a.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fmax_a_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fmax_a_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fmax_a_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fmax_a_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fmax_a_d_ARG2
   %2 = tail call <2 x double> @llvm.mips.fmax.a.d(<2 x double> %0, <2 x double> %1)
   store <2 x double> %2, <2 x double>* @llvm_mips_fmax_a_d_RES
   ret void
@@ -337,8 +337,8 @@ declare <2 x double> @llvm.mips.fmax.a.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fmul_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fmul_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fmul_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fmul_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fmul_w_ARG2
   %2 = tail call <4 x float> @llvm.mips.fmul.w(<4 x float> %0, <4 x float> %1)
   store <4 x float> %2, <4 x float>* @llvm_mips_fmul_w_RES
   ret void
@@ -359,8 +359,8 @@ declare <4 x float> @llvm.mips.fmul.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fmul_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fmul_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fmul_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fmul_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fmul_d_ARG2
   %2 = tail call <2 x double> @llvm.mips.fmul.d(<2 x double> %0, <2 x double> %1)
   store <2 x double> %2, <2 x double>* @llvm_mips_fmul_d_RES
   ret void
@@ -377,8 +377,8 @@ declare <2 x double> @llvm.mips.fmul.d(<2 x double>, <2 x double>) nounwind
 
 define void @fmul_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fmul_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fmul_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fmul_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fmul_w_ARG2
   %2 = fmul <4 x float> %0, %1
   store <4 x float> %2, <4 x float>* @llvm_mips_fmul_w_RES
   ret void
@@ -393,8 +393,8 @@ entry:
 
 define void @fmul_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fmul_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fmul_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fmul_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fmul_d_ARG2
   %2 = fmul <2 x double> %0, %1
   store <2 x double> %2, <2 x double>* @llvm_mips_fmul_d_RES
   ret void
@@ -413,8 +413,8 @@ entry:
 
 define void @llvm_mips_fsub_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fsub_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fsub_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fsub_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fsub_w_ARG2
   %2 = tail call <4 x float> @llvm.mips.fsub.w(<4 x float> %0, <4 x float> %1)
   store <4 x float> %2, <4 x float>* @llvm_mips_fsub_w_RES
   ret void
@@ -435,8 +435,8 @@ declare <4 x float> @llvm.mips.fsub.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fsub_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fsub_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fsub_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fsub_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fsub_d_ARG2
   %2 = tail call <2 x double> @llvm.mips.fsub.d(<2 x double> %0, <2 x double> %1)
   store <2 x double> %2, <2 x double>* @llvm_mips_fsub_d_RES
   ret void
@@ -454,8 +454,8 @@ declare <2 x double> @llvm.mips.fsub.d(<2 x double>, <2 x double>) nounwind
 
 define void @fsub_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fsub_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fsub_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fsub_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fsub_w_ARG2
   %2 = fsub <4 x float> %0, %1
   store <4 x float> %2, <4 x float>* @llvm_mips_fsub_w_RES
   ret void
@@ -470,8 +470,8 @@ entry:
 
 define void @fsub_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fsub_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fsub_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fsub_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fsub_d_ARG2
   %2 = fsub <2 x double> %0, %1
   store <2 x double> %2, <2 x double>* @llvm_mips_fsub_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3rf_4rf.ll b/test/CodeGen/Mips/msa/3rf_4rf.ll
index 67ef7fd2bae1..f1a3002e8179 100644
--- a/test/CodeGen/Mips/msa/3rf_4rf.ll
+++ b/test/CodeGen/Mips/msa/3rf_4rf.ll
@@ -11,9 +11,9 @@
 
 define void @llvm_mips_fmadd_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fmadd_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fmadd_w_ARG2
-  %2 = load <4 x float>* @llvm_mips_fmadd_w_ARG3
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fmadd_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fmadd_w_ARG2
+  %2 = load <4 x float>, <4 x float>* @llvm_mips_fmadd_w_ARG3
   %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
   store <4 x float> %3, <4 x float>* @llvm_mips_fmadd_w_RES
   ret void
@@ -36,9 +36,9 @@ declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) no
 
 define void @llvm_mips_fmadd_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fmadd_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fmadd_d_ARG2
-  %2 = load <2 x double>* @llvm_mips_fmadd_d_ARG3
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fmadd_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fmadd_d_ARG2
+  %2 = load <2 x double>, <2 x double>* @llvm_mips_fmadd_d_ARG3
   %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
   store <2 x double> %3, <2 x double>* @llvm_mips_fmadd_d_RES
   ret void
@@ -61,9 +61,9 @@ declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>
 
 define void @llvm_mips_fmsub_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fmsub_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fmsub_w_ARG2
-  %2 = load <4 x float>* @llvm_mips_fmsub_w_ARG3
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fmsub_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fmsub_w_ARG2
+  %2 = load <4 x float>, <4 x float>* @llvm_mips_fmsub_w_ARG3
   %3 = tail call <4 x float> @llvm.mips.fmsub.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
   store <4 x float> %3, <4 x float>* @llvm_mips_fmsub_w_RES
   ret void
@@ -86,9 +86,9 @@ declare <4 x float> @llvm.mips.fmsub.w(<4 x float>, <4 x float>, <4 x float>) no
 
 define void @llvm_mips_fmsub_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fmsub_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fmsub_d_ARG2
-  %2 = load <2 x double>* @llvm_mips_fmsub_d_ARG3
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fmsub_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fmsub_d_ARG2
+  %2 = load <2 x double>, <2 x double>* @llvm_mips_fmsub_d_ARG3
   %3 = tail call <2 x double> @llvm.mips.fmsub.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
   store <2 x double> %3, <2 x double>* @llvm_mips_fmsub_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3rf_4rf_q.ll b/test/CodeGen/Mips/msa/3rf_4rf_q.ll
index de28be0b1c22..704c4b7e7cbc 100644
--- a/test/CodeGen/Mips/msa/3rf_4rf_q.ll
+++ b/test/CodeGen/Mips/msa/3rf_4rf_q.ll
@@ -11,9 +11,9 @@
 
 define void @llvm_mips_madd_q_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_madd_q_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_madd_q_h_ARG2
-  %2 = load <8 x i16>* @llvm_mips_madd_q_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_madd_q_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_madd_q_h_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_madd_q_h_ARG3
   %3 = tail call <8 x i16> @llvm.mips.madd.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
   store <8 x i16> %3, <8 x i16>* @llvm_mips_madd_q_h_RES
   ret void
@@ -36,9 +36,9 @@ declare <8 x i16> @llvm.mips.madd.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_madd_q_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_madd_q_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_madd_q_w_ARG2
-  %2 = load <4 x i32>* @llvm_mips_madd_q_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_madd_q_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_madd_q_w_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_madd_q_w_ARG3
   %3 = tail call <4 x i32> @llvm.mips.madd.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
   store <4 x i32> %3, <4 x i32>* @llvm_mips_madd_q_w_RES
   ret void
@@ -61,9 +61,9 @@ declare <4 x i32> @llvm.mips.madd.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_maddr_q_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_maddr_q_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_maddr_q_h_ARG2
-  %2 = load <8 x i16>* @llvm_mips_maddr_q_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_maddr_q_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_maddr_q_h_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_maddr_q_h_ARG3
   %3 = tail call <8 x i16> @llvm.mips.maddr.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
   store <8 x i16> %3, <8 x i16>* @llvm_mips_maddr_q_h_RES
   ret void
@@ -86,9 +86,9 @@ declare <8 x i16> @llvm.mips.maddr.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_maddr_q_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_maddr_q_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_maddr_q_w_ARG2
-  %2 = load <4 x i32>* @llvm_mips_maddr_q_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_maddr_q_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_maddr_q_w_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_maddr_q_w_ARG3
   %3 = tail call <4 x i32> @llvm.mips.maddr.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
   store <4 x i32> %3, <4 x i32>* @llvm_mips_maddr_q_w_RES
   ret void
@@ -111,9 +111,9 @@ declare <4 x i32> @llvm.mips.maddr.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_msub_q_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_msub_q_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_msub_q_h_ARG2
-  %2 = load <8 x i16>* @llvm_mips_msub_q_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_msub_q_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_msub_q_h_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_msub_q_h_ARG3
   %3 = tail call <8 x i16> @llvm.mips.msub.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
   store <8 x i16> %3, <8 x i16>* @llvm_mips_msub_q_h_RES
   ret void
@@ -136,9 +136,9 @@ declare <8 x i16> @llvm.mips.msub.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_msub_q_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_msub_q_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_msub_q_w_ARG2
-  %2 = load <4 x i32>* @llvm_mips_msub_q_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_msub_q_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_msub_q_w_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_msub_q_w_ARG3
   %3 = tail call <4 x i32> @llvm.mips.msub.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
   store <4 x i32> %3, <4 x i32>* @llvm_mips_msub_q_w_RES
   ret void
@@ -161,9 +161,9 @@ declare <4 x i32> @llvm.mips.msub.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_msubr_q_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_msubr_q_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_msubr_q_h_ARG2
-  %2 = load <8 x i16>* @llvm_mips_msubr_q_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_msubr_q_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_msubr_q_h_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_msubr_q_h_ARG3
   %3 = tail call <8 x i16> @llvm.mips.msubr.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
   store <8 x i16> %3, <8 x i16>* @llvm_mips_msubr_q_h_RES
   ret void
@@ -186,9 +186,9 @@ declare <8 x i16> @llvm.mips.msubr.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_msubr_q_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_msubr_q_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_msubr_q_w_ARG2
-  %2 = load <4 x i32>* @llvm_mips_msubr_q_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_msubr_q_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_msubr_q_w_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_msubr_q_w_ARG3
   %3 = tail call <4 x i32> @llvm.mips.msubr.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
   store <4 x i32> %3, <4 x i32>* @llvm_mips_msubr_q_w_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3rf_exdo.ll b/test/CodeGen/Mips/msa/3rf_exdo.ll
index 8a7f268a5069..1b1b2e9243ec 100644
--- a/test/CodeGen/Mips/msa/3rf_exdo.ll
+++ b/test/CodeGen/Mips/msa/3rf_exdo.ll
@@ -10,8 +10,8 @@
 
 define void @llvm_mips_fexdo_h_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fexdo_h_ARG1
-  %1 = load <4 x float>* @llvm_mips_fexdo_h_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fexdo_h_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fexdo_h_ARG2
   %2 = tail call <8 x half> @llvm.mips.fexdo.h(<4 x float> %0, <4 x float> %1)
   store <8 x half> %2, <8 x half>* @llvm_mips_fexdo_h_RES
   ret void
@@ -32,8 +32,8 @@ declare <8 x half> @llvm.mips.fexdo.h(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fexdo_w_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fexdo_w_ARG1
-  %1 = load <2 x double>* @llvm_mips_fexdo_w_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fexdo_w_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fexdo_w_ARG2
   %2 = tail call <4 x float> @llvm.mips.fexdo.w(<2 x double> %0, <2 x double> %1)
   store <4 x float> %2, <4 x float>* @llvm_mips_fexdo_w_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3rf_float_int.ll b/test/CodeGen/Mips/msa/3rf_float_int.ll
index 7b01e1721db9..2bd056d3cc8d 100644
--- a/test/CodeGen/Mips/msa/3rf_float_int.ll
+++ b/test/CodeGen/Mips/msa/3rf_float_int.ll
@@ -10,8 +10,8 @@
 
 define void @llvm_mips_fexp2_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fexp2_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_fexp2_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fexp2_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_fexp2_w_ARG2
   %2 = tail call <4 x float> @llvm.mips.fexp2.w(<4 x float> %0, <4 x i32> %1)
   store <4 x float> %2, <4 x float>* @llvm_mips_fexp2_w_RES
   ret void
@@ -32,8 +32,8 @@ declare <4 x float> @llvm.mips.fexp2.w(<4 x float>, <4 x i32>) nounwind
 
 define void @llvm_mips_fexp2_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fexp2_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_fexp2_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fexp2_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_fexp2_d_ARG2
   %2 = tail call <2 x double> @llvm.mips.fexp2.d(<2 x double> %0, <2 x i64> %1)
   store <2 x double> %2, <2 x double>* @llvm_mips_fexp2_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3rf_int_float.ll b/test/CodeGen/Mips/msa/3rf_int_float.ll
index 5624771b8357..545e5435d643 100644
--- a/test/CodeGen/Mips/msa/3rf_int_float.ll
+++ b/test/CodeGen/Mips/msa/3rf_int_float.ll
@@ -10,8 +10,8 @@
 
 define void @llvm_mips_fcaf_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fcaf_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fcaf_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fcaf_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fcaf_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fcaf.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fcaf_w_RES
   ret void
@@ -32,8 +32,8 @@ declare <4 x i32> @llvm.mips.fcaf.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fcaf_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fcaf_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fcaf_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fcaf_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fcaf_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fcaf.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fcaf_d_RES
   ret void
@@ -54,8 +54,8 @@ declare <2 x i64> @llvm.mips.fcaf.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fceq_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fceq_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fceq_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fceq_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fceq_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fceq.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fceq_w_RES
   ret void
@@ -76,8 +76,8 @@ declare <4 x i32> @llvm.mips.fceq.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fceq_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fceq_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fceq_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fceq_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fceq_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fceq.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fceq_d_RES
   ret void
@@ -98,8 +98,8 @@ declare <2 x i64> @llvm.mips.fceq.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fcle_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fcle_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fcle_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fcle_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fcle_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fcle.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fcle_w_RES
   ret void
@@ -120,8 +120,8 @@ declare <4 x i32> @llvm.mips.fcle.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fcle_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fcle_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fcle_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fcle_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fcle_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fcle.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fcle_d_RES
   ret void
@@ -142,8 +142,8 @@ declare <2 x i64> @llvm.mips.fcle.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fclt_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fclt_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fclt_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fclt_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fclt_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fclt.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fclt_w_RES
   ret void
@@ -164,8 +164,8 @@ declare <4 x i32> @llvm.mips.fclt.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fclt_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fclt_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fclt_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fclt_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fclt_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fclt.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fclt_d_RES
   ret void
@@ -186,8 +186,8 @@ declare <2 x i64> @llvm.mips.fclt.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fcor_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fcor_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fcor_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fcor_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fcor_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fcor.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fcor_w_RES
   ret void
@@ -208,8 +208,8 @@ declare <4 x i32> @llvm.mips.fcor.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fcor_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fcor_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fcor_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fcor_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fcor_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fcor.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fcor_d_RES
   ret void
@@ -230,8 +230,8 @@ declare <2 x i64> @llvm.mips.fcor.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fcne_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fcne_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fcne_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fcne_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fcne_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fcne.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fcne_w_RES
   ret void
@@ -252,8 +252,8 @@ declare <4 x i32> @llvm.mips.fcne.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fcne_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fcne_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fcne_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fcne_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fcne_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fcne.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fcne_d_RES
   ret void
@@ -274,8 +274,8 @@ declare <2 x i64> @llvm.mips.fcne.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fcueq_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fcueq_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fcueq_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fcueq_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fcueq_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fcueq.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fcueq_w_RES
   ret void
@@ -296,8 +296,8 @@ declare <4 x i32> @llvm.mips.fcueq.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fcueq_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fcueq_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fcueq_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fcueq_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fcueq_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fcueq.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fcueq_d_RES
   ret void
@@ -318,8 +318,8 @@ declare <2 x i64> @llvm.mips.fcueq.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fcult_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fcult_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fcult_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fcult_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fcult_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fcult.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fcult_w_RES
   ret void
@@ -340,8 +340,8 @@ declare <4 x i32> @llvm.mips.fcult.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fcult_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fcult_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fcult_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fcult_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fcult_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fcult.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fcult_d_RES
   ret void
@@ -362,8 +362,8 @@ declare <2 x i64> @llvm.mips.fcult.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fcule_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fcule_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fcule_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fcule_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fcule_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fcule.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fcule_w_RES
   ret void
@@ -384,8 +384,8 @@ declare <4 x i32> @llvm.mips.fcule.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fcule_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fcule_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fcule_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fcule_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fcule_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fcule.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fcule_d_RES
   ret void
@@ -406,8 +406,8 @@ declare <2 x i64> @llvm.mips.fcule.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fcun_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fcun_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fcun_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fcun_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fcun_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fcun.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fcun_w_RES
   ret void
@@ -428,8 +428,8 @@ declare <4 x i32> @llvm.mips.fcun.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fcun_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fcun_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fcun_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fcun_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fcun_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fcun.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fcun_d_RES
   ret void
@@ -450,8 +450,8 @@ declare <2 x i64> @llvm.mips.fcun.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fcune_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fcune_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fcune_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fcune_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fcune_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fcune.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fcune_w_RES
   ret void
@@ -472,8 +472,8 @@ declare <4 x i32> @llvm.mips.fcune.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fcune_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fcune_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fcune_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fcune_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fcune_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fcune.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fcune_d_RES
   ret void
@@ -494,8 +494,8 @@ declare <2 x i64> @llvm.mips.fcune.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fsaf_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fsaf_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fsaf_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fsaf_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fsaf_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fsaf.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fsaf_w_RES
   ret void
@@ -516,8 +516,8 @@ declare <4 x i32> @llvm.mips.fsaf.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fsaf_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fsaf_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fsaf_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fsaf_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fsaf_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fsaf.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fsaf_d_RES
   ret void
@@ -538,8 +538,8 @@ declare <2 x i64> @llvm.mips.fsaf.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fseq_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fseq_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fseq_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fseq_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fseq_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fseq.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fseq_w_RES
   ret void
@@ -560,8 +560,8 @@ declare <4 x i32> @llvm.mips.fseq.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fseq_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fseq_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fseq_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fseq_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fseq_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fseq.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fseq_d_RES
   ret void
@@ -582,8 +582,8 @@ declare <2 x i64> @llvm.mips.fseq.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fsle_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fsle_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fsle_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fsle_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fsle_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fsle.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fsle_w_RES
   ret void
@@ -604,8 +604,8 @@ declare <4 x i32> @llvm.mips.fsle.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fsle_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fsle_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fsle_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fsle_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fsle_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fsle.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fsle_d_RES
   ret void
@@ -626,8 +626,8 @@ declare <2 x i64> @llvm.mips.fsle.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fslt_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fslt_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fslt_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fslt_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fslt_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fslt.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fslt_w_RES
   ret void
@@ -648,8 +648,8 @@ declare <4 x i32> @llvm.mips.fslt.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fslt_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fslt_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fslt_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fslt_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fslt_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fslt.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fslt_d_RES
   ret void
@@ -670,8 +670,8 @@ declare <2 x i64> @llvm.mips.fslt.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fsor_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fsor_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fsor_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fsor_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fsor_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fsor.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fsor_w_RES
   ret void
@@ -692,8 +692,8 @@ declare <4 x i32> @llvm.mips.fsor.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fsor_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fsor_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fsor_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fsor_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fsor_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fsor.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fsor_d_RES
   ret void
@@ -714,8 +714,8 @@ declare <2 x i64> @llvm.mips.fsor.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fsne_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fsne_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fsne_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fsne_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fsne_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fsne.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fsne_w_RES
   ret void
@@ -736,8 +736,8 @@ declare <4 x i32> @llvm.mips.fsne.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fsne_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fsne_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fsne_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fsne_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fsne_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fsne.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fsne_d_RES
   ret void
@@ -758,8 +758,8 @@ declare <2 x i64> @llvm.mips.fsne.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fsueq_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fsueq_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fsueq_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fsueq_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fsueq_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fsueq.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fsueq_w_RES
   ret void
@@ -780,8 +780,8 @@ declare <4 x i32> @llvm.mips.fsueq.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fsueq_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fsueq_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fsueq_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fsueq_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fsueq_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fsueq.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fsueq_d_RES
   ret void
@@ -802,8 +802,8 @@ declare <2 x i64> @llvm.mips.fsueq.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fsult_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fsult_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fsult_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fsult_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fsult_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fsult.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fsult_w_RES
   ret void
@@ -824,8 +824,8 @@ declare <4 x i32> @llvm.mips.fsult.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fsult_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fsult_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fsult_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fsult_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fsult_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fsult.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fsult_d_RES
   ret void
@@ -846,8 +846,8 @@ declare <2 x i64> @llvm.mips.fsult.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fsule_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fsule_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fsule_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fsule_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fsule_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fsule.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fsule_w_RES
   ret void
@@ -868,8 +868,8 @@ declare <4 x i32> @llvm.mips.fsule.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fsule_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fsule_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fsule_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fsule_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fsule_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fsule.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fsule_d_RES
   ret void
@@ -890,8 +890,8 @@ declare <2 x i64> @llvm.mips.fsule.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fsun_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fsun_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fsun_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fsun_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fsun_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fsun.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fsun_w_RES
   ret void
@@ -912,8 +912,8 @@ declare <4 x i32> @llvm.mips.fsun.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fsun_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fsun_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fsun_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fsun_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fsun_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fsun.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fsun_d_RES
   ret void
@@ -934,8 +934,8 @@ declare <2 x i64> @llvm.mips.fsun.d(<2 x double>, <2 x double>) nounwind
 
 define void @llvm_mips_fsune_w_test() nounwind {
 entry:
-  %0 = load <4 x float>* @llvm_mips_fsune_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fsune_w_ARG2
+  %0 = load <4 x float>, <4 x float>* @llvm_mips_fsune_w_ARG1
+  %1 = load <4 x float>, <4 x float>* @llvm_mips_fsune_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.fsune.w(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_fsune_w_RES
   ret void
@@ -956,8 +956,8 @@ declare <4 x i32> @llvm.mips.fsune.w(<4 x float>, <4 x float>) nounwind
 
 define void @llvm_mips_fsune_d_test() nounwind {
 entry:
-  %0 = load <2 x double>* @llvm_mips_fsune_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fsune_d_ARG2
+  %0 = load <2 x double>, <2 x double>* @llvm_mips_fsune_d_ARG1
+  %1 = load <2 x double>, <2 x double>* @llvm_mips_fsune_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.fsune.d(<2 x double> %0, <2 x double> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_fsune_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/3rf_q.ll b/test/CodeGen/Mips/msa/3rf_q.ll
index f7000ee913a6..c8b0a5000021 100644
--- a/test/CodeGen/Mips/msa/3rf_q.ll
+++ b/test/CodeGen/Mips/msa/3rf_q.ll
@@ -10,8 +10,8 @@
 
 define void @llvm_mips_mul_q_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_mul_q_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_mul_q_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_mul_q_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_mul_q_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.mul.q.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_mul_q_h_RES
   ret void
@@ -32,8 +32,8 @@ declare <8 x i16> @llvm.mips.mul.q.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_mul_q_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_mul_q_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_mul_q_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_mul_q_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_mul_q_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.mul.q.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_mul_q_w_RES
   ret void
@@ -54,8 +54,8 @@ declare <4 x i32> @llvm.mips.mul.q.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_mulr_q_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_mulr_q_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_mulr_q_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_mulr_q_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_mulr_q_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.mulr.q.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_mulr_q_h_RES
   ret void
@@ -76,8 +76,8 @@ declare <8 x i16> @llvm.mips.mulr.q.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_mulr_q_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_mulr_q_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_mulr_q_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_mulr_q_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_mulr_q_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.mulr.q.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_mulr_q_w_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/arithmetic.ll b/test/CodeGen/Mips/msa/arithmetic.ll
index 09ee5023c7b1..3ecd0e43589f 100644
--- a/test/CodeGen/Mips/msa/arithmetic.ll
+++ b/test/CodeGen/Mips/msa/arithmetic.ll
@@ -4,9 +4,9 @@
 define void @add_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: add_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = add <16 x i8> %1, %2
   ; CHECK-DAG: addv.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -20,9 +20,9 @@ define void @add_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @add_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: add_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = add <8 x i16> %1, %2
   ; CHECK-DAG: addv.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -36,9 +36,9 @@ define void @add_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @add_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: add_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = add <4 x i32> %1, %2
   ; CHECK-DAG: addv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -52,9 +52,9 @@ define void @add_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @add_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: add_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = add <2 x i64> %1, %2
   ; CHECK-DAG: addv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -68,7 +68,7 @@ define void @add_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @add_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: add_v16i8_i:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = add <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,
                           i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -83,7 +83,7 @@ define void @add_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @add_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: add_v8i16_i:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = add <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1,
                           i16 1, i16 1, i16 1, i16 1>
@@ -98,7 +98,7 @@ define void @add_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @add_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: add_v4i32_i:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = add <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   ; CHECK-DAG: addvi.w [[R3:\$w[0-9]+]], [[R1]], 1
@@ -112,7 +112,7 @@ define void @add_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @add_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: add_v2i64_i:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = add <2 x i64> %1, <i64 1, i64 1>
   ; CHECK-DAG: addvi.d [[R3:\$w[0-9]+]], [[R1]], 1
@@ -126,9 +126,9 @@ define void @add_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @sub_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: sub_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = sub <16 x i8> %1, %2
   ; CHECK-DAG: subv.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -142,9 +142,9 @@ define void @sub_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @sub_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: sub_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = sub <8 x i16> %1, %2
   ; CHECK-DAG: subv.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -158,9 +158,9 @@ define void @sub_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @sub_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: sub_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = sub <4 x i32> %1, %2
   ; CHECK-DAG: subv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -174,9 +174,9 @@ define void @sub_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @sub_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: sub_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = sub <2 x i64> %1, %2
   ; CHECK-DAG: subv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -190,7 +190,7 @@ define void @sub_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @sub_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: sub_v16i8_i:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = sub <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,
                           i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -205,7 +205,7 @@ define void @sub_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @sub_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: sub_v8i16_i:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = sub <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1,
                           i16 1, i16 1, i16 1, i16 1>
@@ -220,7 +220,7 @@ define void @sub_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @sub_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: sub_v4i32_i:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = sub <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   ; CHECK-DAG: subvi.w [[R3:\$w[0-9]+]], [[R1]], 1
@@ -234,7 +234,7 @@ define void @sub_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @sub_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: sub_v2i64_i:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = sub <2 x i64> %1, <i64 1, i64 1>
   ; CHECK-DAG: subvi.d [[R3:\$w[0-9]+]], [[R1]], 1
@@ -248,9 +248,9 @@ define void @sub_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @mul_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: mul_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = mul <16 x i8> %1, %2
   ; CHECK-DAG: mulv.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -264,9 +264,9 @@ define void @mul_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @mul_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: mul_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = mul <8 x i16> %1, %2
   ; CHECK-DAG: mulv.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -280,9 +280,9 @@ define void @mul_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @mul_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: mul_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = mul <4 x i32> %1, %2
   ; CHECK-DAG: mulv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -296,9 +296,9 @@ define void @mul_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @mul_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: mul_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = mul <2 x i64> %1, %2
   ; CHECK-DAG: mulv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -313,11 +313,11 @@ define void @maddv_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
                          <16 x i8>* %c) nounwind {
   ; CHECK: maddv_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <16 x i8>* %c
+  %3 = load <16 x i8>, <16 x i8>* %c
   ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
   %4 = mul <16 x i8> %2, %3
   %5 = add <16 x i8> %4, %1
@@ -333,11 +333,11 @@ define void @maddv_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
                          <8 x i16>* %c) nounwind {
   ; CHECK: maddv_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <8 x i16>* %c
+  %3 = load <8 x i16>, <8 x i16>* %c
   ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
   %4 = mul <8 x i16> %2, %3
   %5 = add <8 x i16> %4, %1
@@ -353,11 +353,11 @@ define void @maddv_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
                          <4 x i32>* %c) nounwind {
   ; CHECK: maddv_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <4 x i32>* %c
+  %3 = load <4 x i32>, <4 x i32>* %c
   ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
   %4 = mul <4 x i32> %2, %3
   %5 = add <4 x i32> %4, %1
@@ -373,11 +373,11 @@ define void @maddv_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
                          <2 x i64>* %c) nounwind {
   ; CHECK: maddv_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <2 x i64>* %c
+  %3 = load <2 x i64>, <2 x i64>* %c
   ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
   %4 = mul <2 x i64> %2, %3
   %5 = add <2 x i64> %4, %1
@@ -393,11 +393,11 @@ define void @msubv_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
                          <16 x i8>* %c) nounwind {
   ; CHECK: msubv_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <16 x i8>* %c
+  %3 = load <16 x i8>, <16 x i8>* %c
   ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
   %4 = mul <16 x i8> %2, %3
   %5 = sub <16 x i8> %1, %4
@@ -413,11 +413,11 @@ define void @msubv_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
                          <8 x i16>* %c) nounwind {
   ; CHECK: msubv_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <8 x i16>* %c
+  %3 = load <8 x i16>, <8 x i16>* %c
   ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
   %4 = mul <8 x i16> %2, %3
   %5 = sub <8 x i16> %1, %4
@@ -433,11 +433,11 @@ define void @msubv_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
                          <4 x i32>* %c) nounwind {
   ; CHECK: msubv_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <4 x i32>* %c
+  %3 = load <4 x i32>, <4 x i32>* %c
   ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
   %4 = mul <4 x i32> %2, %3
   %5 = sub <4 x i32> %1, %4
@@ -453,11 +453,11 @@ define void @msubv_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
                          <2 x i64>* %c) nounwind {
   ; CHECK: msubv_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <2 x i64>* %c
+  %3 = load <2 x i64>, <2 x i64>* %c
   ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
   %4 = mul <2 x i64> %2, %3
   %5 = sub <2 x i64> %1, %4
@@ -472,9 +472,9 @@ define void @msubv_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
 define void @div_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: div_s_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = sdiv <16 x i8> %1, %2
   ; CHECK-DAG: div_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -488,9 +488,9 @@ define void @div_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @div_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: div_s_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = sdiv <8 x i16> %1, %2
   ; CHECK-DAG: div_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -504,9 +504,9 @@ define void @div_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @div_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: div_s_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = sdiv <4 x i32> %1, %2
   ; CHECK-DAG: div_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -520,9 +520,9 @@ define void @div_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @div_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: div_s_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = sdiv <2 x i64> %1, %2
   ; CHECK-DAG: div_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -536,9 +536,9 @@ define void @div_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @div_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: div_u_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = udiv <16 x i8> %1, %2
   ; CHECK-DAG: div_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -552,9 +552,9 @@ define void @div_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @div_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: div_u_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = udiv <8 x i16> %1, %2
   ; CHECK-DAG: div_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -568,9 +568,9 @@ define void @div_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @div_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: div_u_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = udiv <4 x i32> %1, %2
   ; CHECK-DAG: div_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -584,9 +584,9 @@ define void @div_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @div_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: div_u_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = udiv <2 x i64> %1, %2
   ; CHECK-DAG: div_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -600,9 +600,9 @@ define void @div_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @mod_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: mod_s_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = srem <16 x i8> %1, %2
   ; CHECK-DAG: mod_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -616,9 +616,9 @@ define void @mod_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @mod_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: mod_s_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = srem <8 x i16> %1, %2
   ; CHECK-DAG: mod_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -632,9 +632,9 @@ define void @mod_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @mod_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: mod_s_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = srem <4 x i32> %1, %2
   ; CHECK-DAG: mod_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -648,9 +648,9 @@ define void @mod_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @mod_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: mod_s_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = srem <2 x i64> %1, %2
   ; CHECK-DAG: mod_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -664,9 +664,9 @@ define void @mod_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @mod_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: mod_u_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = urem <16 x i8> %1, %2
   ; CHECK-DAG: mod_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -680,9 +680,9 @@ define void @mod_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @mod_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: mod_u_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = urem <8 x i16> %1, %2
   ; CHECK-DAG: mod_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -696,9 +696,9 @@ define void @mod_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @mod_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: mod_u_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = urem <4 x i32> %1, %2
   ; CHECK-DAG: mod_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -712,9 +712,9 @@ define void @mod_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @mod_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: mod_u_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = urem <2 x i64> %1, %2
   ; CHECK-DAG: mod_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
diff --git a/test/CodeGen/Mips/msa/arithmetic_float.ll b/test/CodeGen/Mips/msa/arithmetic_float.ll
index 9aae284fe535..d2ead536804a 100644
--- a/test/CodeGen/Mips/msa/arithmetic_float.ll
+++ b/test/CodeGen/Mips/msa/arithmetic_float.ll
@@ -4,9 +4,9 @@
 define void @add_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: add_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fadd <4 x float> %1, %2
   ; CHECK-DAG: fadd.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -20,9 +20,9 @@ define void @add_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwi
 define void @add_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: add_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fadd <2 x double> %1, %2
   ; CHECK-DAG: fadd.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -36,9 +36,9 @@ define void @add_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nou
 define void @sub_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: sub_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fsub <4 x float> %1, %2
   ; CHECK-DAG: fsub.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -52,9 +52,9 @@ define void @sub_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwi
 define void @sub_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: sub_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fsub <2 x double> %1, %2
   ; CHECK-DAG: fsub.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -68,9 +68,9 @@ define void @sub_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nou
 define void @mul_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: mul_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fmul <4 x float> %1, %2
   ; CHECK-DAG: fmul.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -84,9 +84,9 @@ define void @mul_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwi
 define void @mul_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: mul_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fmul <2 x double> %1, %2
   ; CHECK-DAG: fmul.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -101,11 +101,11 @@ define void @fma_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b,
                        <4 x float>* %c) nounwind {
   ; CHECK: fma_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <4 x float>* %c
+  %3 = load <4 x float>, <4 x float>* %c
   ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
   %4 = tail call <4 x float> @llvm.fma.v4f32 (<4 x float> %1, <4 x float> %2,
                                               <4 x float> %3)
@@ -121,11 +121,11 @@ define void @fma_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b,
                        <2 x double>* %c) nounwind {
   ; CHECK: fma_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <2 x double>* %c
+  %3 = load <2 x double>, <2 x double>* %c
   ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
   %4 = tail call <2 x double> @llvm.fma.v2f64 (<2 x double> %1, <2 x double> %2,
                                                <2 x double> %3)
@@ -141,11 +141,11 @@ define void @fmsub_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b,
                        <4 x float>* %c) nounwind {
   ; CHECK: fmsub_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <4 x float>* %c
+  %3 = load <4 x float>, <4 x float>* %c
   ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
   %4 = fmul <4 x float> %2, %3
   %5 = fsub <4 x float> %1, %4
@@ -161,11 +161,11 @@ define void @fmsub_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b,
                        <2 x double>* %c) nounwind {
   ; CHECK: fmsub_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <2 x double>* %c
+  %3 = load <2 x double>, <2 x double>* %c
   ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
   %4 = fmul <2 x double> %2, %3
   %5 = fsub <2 x double> %1, %4
@@ -180,9 +180,9 @@ define void @fmsub_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b,
 define void @fdiv_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: fdiv_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fdiv <4 x float> %1, %2
   ; CHECK-DAG: fdiv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -196,9 +196,9 @@ define void @fdiv_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounw
 define void @fdiv_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: fdiv_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fdiv <2 x double> %1, %2
   ; CHECK-DAG: fdiv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -212,7 +212,7 @@ define void @fdiv_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) no
 define void @fabs_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
   ; CHECK: fabs_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <4 x float> @llvm.fabs.v4f32 (<4 x float> %1)
   ; CHECK-DAG: fmax_a.w [[R3:\$w[0-9]+]], [[R1]], [[R1]]
@@ -226,7 +226,7 @@ define void @fabs_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
 define void @fabs_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
   ; CHECK: fabs_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <2 x double> @llvm.fabs.v2f64 (<2 x double> %1)
   ; CHECK-DAG: fmax_a.d [[R3:\$w[0-9]+]], [[R1]], [[R1]]
@@ -240,7 +240,7 @@ define void @fabs_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
 define void @fexp2_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
   ; CHECK: fexp2_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <4 x float> @llvm.exp2.v4f32 (<4 x float> %1)
   ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
@@ -256,7 +256,7 @@ define void @fexp2_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
 define void @fexp2_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
   ; CHECK: fexp2_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <2 x double> @llvm.exp2.v2f64 (<2 x double> %1)
   ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
@@ -272,7 +272,7 @@ define void @fexp2_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
 define void @fexp2_v4f32_2(<4 x float>* %c, <4 x float>* %a) nounwind {
   ; CHECK: fexp2_v4f32_2:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <4 x float> @llvm.exp2.v4f32 (<4 x float> %1)
   %3 = fmul <4 x float> <float 2.0, float 2.0, float 2.0, float 2.0>, %2
@@ -289,7 +289,7 @@ define void @fexp2_v4f32_2(<4 x float>* %c, <4 x float>* %a) nounwind {
 define void @fexp2_v2f64_2(<2 x double>* %c, <2 x double>* %a) nounwind {
   ; CHECK: fexp2_v2f64_2:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <2 x double> @llvm.exp2.v2f64 (<2 x double> %1)
   %3 = fmul <2 x double> <double 2.0, double 2.0>, %2
@@ -306,7 +306,7 @@ define void @fexp2_v2f64_2(<2 x double>* %c, <2 x double>* %a) nounwind {
 define void @fsqrt_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
   ; CHECK: fsqrt_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %1)
   ; CHECK-DAG: fsqrt.w [[R3:\$w[0-9]+]], [[R1]]
@@ -320,7 +320,7 @@ define void @fsqrt_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
 define void @fsqrt_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
   ; CHECK: fsqrt_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %1)
   ; CHECK-DAG: fsqrt.d [[R3:\$w[0-9]+]], [[R1]]
@@ -334,7 +334,7 @@ define void @fsqrt_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
 define void @ffint_u_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: ffint_u_v4f32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = uitofp <4 x i32> %1 to <4 x float>
   ; CHECK-DAG: ffint_u.w [[R3:\$w[0-9]+]], [[R1]]
@@ -348,7 +348,7 @@ define void @ffint_u_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind {
 define void @ffint_u_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: ffint_u_v2f64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = uitofp <2 x i64> %1 to <2 x double>
   ; CHECK-DAG: ffint_u.d [[R3:\$w[0-9]+]], [[R1]]
@@ -362,7 +362,7 @@ define void @ffint_u_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind {
 define void @ffint_s_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: ffint_s_v4f32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = sitofp <4 x i32> %1 to <4 x float>
   ; CHECK-DAG: ffint_s.w [[R3:\$w[0-9]+]], [[R1]]
@@ -376,7 +376,7 @@ define void @ffint_s_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind {
 define void @ffint_s_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: ffint_s_v2f64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = sitofp <2 x i64> %1 to <2 x double>
   ; CHECK-DAG: ffint_s.d [[R3:\$w[0-9]+]], [[R1]]
@@ -390,7 +390,7 @@ define void @ffint_s_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind {
 define void @ftrunc_u_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind {
   ; CHECK: ftrunc_u_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = fptoui <4 x float> %1 to <4 x i32>
   ; CHECK-DAG: ftrunc_u.w [[R3:\$w[0-9]+]], [[R1]]
@@ -404,7 +404,7 @@ define void @ftrunc_u_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind {
 define void @ftrunc_u_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind {
   ; CHECK: ftrunc_u_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = fptoui <2 x double> %1 to <2 x i64>
   ; CHECK-DAG: ftrunc_u.d [[R3:\$w[0-9]+]], [[R1]]
@@ -418,7 +418,7 @@ define void @ftrunc_u_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind {
 define void @ftrunc_s_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind {
   ; CHECK: ftrunc_s_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = fptosi <4 x float> %1 to <4 x i32>
   ; CHECK-DAG: ftrunc_s.w [[R3:\$w[0-9]+]], [[R1]]
@@ -432,7 +432,7 @@ define void @ftrunc_s_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind {
 define void @ftrunc_s_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind {
   ; CHECK: ftrunc_s_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = fptosi <2 x double> %1 to <2 x i64>
   ; CHECK-DAG: ftrunc_s.d [[R3:\$w[0-9]+]], [[R1]]
diff --git a/test/CodeGen/Mips/msa/basic_operations.ll b/test/CodeGen/Mips/msa/basic_operations.ll
index dbdf42be49ca..2efec2911935 100644
--- a/test/CodeGen/Mips/msa/basic_operations.ll
+++ b/test/CodeGen/Mips/msa/basic_operations.ll
@@ -1,5 +1,9 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32-AE -check-prefix=MIPS32-BE %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32-AE -check-prefix=MIPS32-LE %s
+; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 -check-prefix=MIPS32 -check-prefix=ALL-BE %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 -check-prefix=MIPS32 -check-prefix=ALL-LE %s
+; RUN: llc -march=mips64 -target-abi n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 -check-prefix=MIPS64 -check-prefix=ALL-BE %s
+; RUN: llc -march=mips64el -target-abi n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 -check-prefix=MIPS64 -check-prefix=ALL-LE %s
+; RUN: llc -march=mips64 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 -check-prefix=MIPS64 -check-prefix=ALL-BE %s
+; RUN: llc -march=mips64el -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 -check-prefix=MIPS64 -check-prefix=ALL-LE %s
 
 @v4i8 = global <4 x i8> <i8 0, i8 0, i8 0, i8 0>
 @v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
@@ -10,135 +14,153 @@
 @i64 = global i64 0
 
 define void @const_v16i8() nounwind {
-  ; MIPS32-AE-LABEL: const_v16i8:
+  ; ALL-LABEL: const_v16i8:
 
   store volatile <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8>*@v16i8
-  ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0
+  ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
 
   store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8>*@v16i8
-  ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 1
+  ; ALL: ldi.b [[R1:\$w[0-9]+]], 1
 
   store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 31>, <16 x i8>*@v16i8
-  ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32-AE: ld.b  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.b  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6>, <16 x i8>*@v16i8
-  ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32-AE: ld.b  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.b  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0>, <16 x i8>*@v16i8
-  ; MIPS32-BE: ldi.h [[R1:\$w[0-9]+]], 256
-  ; MIPS32-LE: ldi.h [[R1:\$w[0-9]+]], 1
+  ; ALL-BE: ldi.h [[R1:\$w[0-9]+]], 256
+  ; ALL-LE: ldi.h [[R1:\$w[0-9]+]], 1
 
   store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>, <16 x i8>*@v16i8
-  ; MIPS32-BE-DAG: lui [[R2:\$[0-9]+]], 258
-  ; MIPS32-LE-DAG: lui [[R2:\$[0-9]+]], 1027
-  ; MIPS32-BE-DAG: ori [[R2]], [[R2]], 772
-  ; MIPS32-LE-DAG: ori [[R2]], [[R2]], 513
-  ; MIPS32-AE-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
+  ; ALL-BE-DAG: lui [[R2:\$[0-9]+]], 258
+  ; ALL-LE-DAG: lui [[R2:\$[0-9]+]], 1027
+  ; ALL-BE-DAG: ori [[R2]], [[R2]], 772
+  ; ALL-LE-DAG: ori [[R2]], [[R2]], 513
+  ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
 
   store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>*@v16i8
-  ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32-AE: ld.b  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.b  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   ret void
-  ; MIPS32-AE: .size const_v16i8
 }
 
 define void @const_v8i16() nounwind {
-  ; MIPS32-AE-LABEL: const_v8i16:
+  ; ALL-LABEL: const_v8i16:
 
   store volatile <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16>*@v8i16
-  ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0
+  ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
 
   store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16>*@v8i16
-  ; MIPS32-AE: ldi.h [[R1:\$w[0-9]+]], 1
+  ; ALL: ldi.h [[R1:\$w[0-9]+]], 1
 
   store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 2, i16 1, i16 1, i16 1, i16 31>, <8 x i16>*@v8i16
-  ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32-AE: ld.h  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.h  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <8 x i16> <i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028>, <8 x i16>*@v8i16
-  ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 4
+  ; ALL: ldi.b [[R1:\$w[0-9]+]], 4
 
   store volatile <8 x i16> <i16 1, i16 2, i16 1, i16 2, i16 1, i16 2, i16 1, i16 2>, <8 x i16>*@v8i16
-  ; MIPS32-BE-DAG: lui [[R2:\$[0-9]+]], 1
-  ; MIPS32-LE-DAG: lui [[R2:\$[0-9]+]], 2
-  ; MIPS32-BE-DAG: ori [[R2]], [[R2]], 2
-  ; MIPS32-LE-DAG: ori [[R2]], [[R2]], 1
-  ; MIPS32-AE-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
+  ; ALL-BE-DAG: lui [[R2:\$[0-9]+]], 1
+  ; ALL-LE-DAG: lui [[R2:\$[0-9]+]], 2
+  ; ALL-BE-DAG: ori [[R2]], [[R2]], 2
+  ; ALL-LE-DAG: ori [[R2]], [[R2]], 1
+  ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
 
   store volatile <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>, <8 x i16>*@v8i16
-  ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32-AE: ld.h  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.h  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   ret void
-  ; MIPS32-AE: .size const_v8i16
 }
 
 define void @const_v4i32() nounwind {
-  ; MIPS32-AE-LABEL: const_v4i32:
+  ; ALL-LABEL: const_v4i32:
 
   store volatile <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32>*@v4i32
-  ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0
+  ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
 
   store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32>*@v4i32
-  ; MIPS32-AE: ldi.w [[R1:\$w[0-9]+]], 1
+  ; ALL: ldi.w [[R1:\$w[0-9]+]], 1
 
   store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 31>, <4 x i32>*@v4i32
-  ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32-AE: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <4 x i32> <i32 16843009, i32 16843009, i32 16843009, i32 16843009>, <4 x i32>*@v4i32
-  ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 1
+  ; ALL: ldi.b [[R1:\$w[0-9]+]], 1
 
   store volatile <4 x i32> <i32 65537, i32 65537, i32 65537, i32 65537>, <4 x i32>*@v4i32
-  ; MIPS32-AE: ldi.h [[R1:\$w[0-9]+]], 1
+  ; ALL: ldi.h [[R1:\$w[0-9]+]], 1
 
   store volatile <4 x i32> <i32 1, i32 2, i32 1, i32 2>, <4 x i32>*@v4i32
-  ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32-AE: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <4 x i32> <i32 3, i32 4, i32 5, i32 6>, <4 x i32>*@v4i32
-  ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32-AE: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   ret void
-  ; MIPS32-AE: .size const_v4i32
 }
 
 define void @const_v2i64() nounwind {
-  ; MIPS32-AE-LABEL: const_v2i64:
+  ; ALL-LABEL: const_v2i64:
 
   store volatile <2 x i64> <i64 0, i64 0>, <2 x i64>*@v2i64
-  ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 0
+  ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
 
   store volatile <2 x i64> <i64 72340172838076673, i64 72340172838076673>, <2 x i64>*@v2i64
-  ; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 1
+  ; ALL: ldi.b [[R1:\$w[0-9]+]], 1
 
   store volatile <2 x i64> <i64 281479271743489, i64 281479271743489>, <2 x i64>*@v2i64
-  ; MIPS32-AE: ldi.h [[R1:\$w[0-9]+]], 1
+  ; ALL: ldi.h [[R1:\$w[0-9]+]], 1
 
   store volatile <2 x i64> <i64 4294967297, i64 4294967297>, <2 x i64>*@v2i64
-  ; MIPS32-AE: ldi.w [[R1:\$w[0-9]+]], 1
+  ; ALL: ldi.w [[R1:\$w[0-9]+]], 1
 
   store volatile <2 x i64> <i64 1, i64 1>, <2 x i64>*@v2i64
-  ; MIPS32-AE: ldi.d [[R1:\$w[0-9]+]], 1
+  ; ALL: ldi.d [[R1:\$w[0-9]+]], 1
 
   store volatile <2 x i64> <i64 1, i64 31>, <2 x i64>*@v2i64
-  ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32-AE: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; MIPS64: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <2 x i64> <i64 3, i64 4>, <2 x i64>*@v2i64
-  ; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32-AE: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; MIPS32: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; MIPS64: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   ret void
-  ; MIPS32-AE: .size const_v2i64
 }
 
-define void @nonconst_v16i8(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g, i8 %h) nounwind {
-  ; MIPS32-AE-LABEL: nonconst_v16i8:
+define void @nonconst_v16i8(i8 signext %a, i8 signext %b, i8 signext %c, i8 signext %d, i8 signext %e, i8 signext %f, i8 signext %g, i8 signext %h) nounwind {
+  ; ALL-LABEL: nonconst_v16i8:
 
   %1 = insertelement <16 x i8> undef, i8 %a, i32 0
   %2 = insertelement <16 x i8> %1, i8 %b, i32 1
@@ -156,39 +178,38 @@ define void @nonconst_v16i8(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g, i8
   %14 = insertelement <16 x i8> %13, i8 %h, i32 13
   %15 = insertelement <16 x i8> %14, i8 %h, i32 14
   %16 = insertelement <16 x i8> %15, i8 %h, i32 15
-  ; MIPS32-AE-DAG: insert.b [[R1:\$w[0-9]+]][0], $4
-  ; MIPS32-AE-DAG: insert.b [[R1]][1], $5
-  ; MIPS32-AE-DAG: insert.b [[R1]][2], $6
-  ; MIPS32-AE-DAG: insert.b [[R1]][3], $7
-  ; MIPS32-BE-DAG: lbu [[R2:\$[0-9]+]], 19($sp)
-  ; MIPS32-LE-DAG: lbu [[R2:\$[0-9]+]], 16($sp)
-  ; MIPS32-AE-DAG: insert.b [[R1]][4], [[R2]]
-  ; MIPS32-BE-DAG: lbu [[R3:\$[0-9]+]], 23($sp)
-  ; MIPS32-LE-DAG: lbu [[R3:\$[0-9]+]], 20($sp)
-  ; MIPS32-AE-DAG: insert.b [[R1]][5], [[R3]]
-  ; MIPS32-BE-DAG: lbu [[R4:\$[0-9]+]], 27($sp)
-  ; MIPS32-LE-DAG: lbu [[R4:\$[0-9]+]], 24($sp)
-  ; MIPS32-AE-DAG: insert.b [[R1]][6], [[R4]]
-  ; MIPS32-BE-DAG: lbu [[R5:\$[0-9]+]], 31($sp)
-  ; MIPS32-LE-DAG: lbu [[R5:\$[0-9]+]], 28($sp)
-  ; MIPS32-AE-DAG: insert.b [[R1]][7], [[R5]]
-  ; MIPS32-AE-DAG: insert.b [[R1]][8], [[R5]]
-  ; MIPS32-AE-DAG: insert.b [[R1]][9], [[R5]]
-  ; MIPS32-AE-DAG: insert.b [[R1]][10], [[R5]]
-  ; MIPS32-AE-DAG: insert.b [[R1]][11], [[R5]]
-  ; MIPS32-AE-DAG: insert.b [[R1]][12], [[R5]]
-  ; MIPS32-AE-DAG: insert.b [[R1]][13], [[R5]]
-  ; MIPS32-AE-DAG: insert.b [[R1]][14], [[R5]]
-  ; MIPS32-AE-DAG: insert.b [[R1]][15], [[R5]]
+  ; ALL-DAG: insert.b [[R1:\$w[0-9]+]][0], $4
+  ; ALL-DAG: insert.b [[R1]][1], $5
+  ; ALL-DAG: insert.b [[R1]][2], $6
+  ; ALL-DAG: insert.b [[R1]][3], $7
+  ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 16($sp)
+  ; MIPS32-DAG: insert.b [[R1]][4], [[R2]]
+  ; MIPS64-DAG: insert.b [[R1]][4], $8
+  ; MIPS32-DAG: lw [[R3:\$[0-9]+]], 20($sp)
+  ; MIPS32-DAG: insert.b [[R1]][5], [[R3]]
+  ; MIPS64-DAG: insert.b [[R1]][5], $9
+  ; MIPS32-DAG: lw [[R4:\$[0-9]+]], 24($sp)
+  ; MIPS32-DAG: insert.b [[R1]][6], [[R4]]
+  ; MIPS64-DAG: insert.b [[R1]][6], $10
+  ; MIPS32-DAG: lw [[R5:\$[0-9]+]], 28($sp)
+  ; MIPS32-DAG: insert.b [[R1]][7], [[R5]]
+  ; MIPS64-DAG: insert.b [[R1]][7], [[R5:\$11]]
+  ; ALL-DAG: insert.b [[R1]][8], [[R5]]
+  ; ALL-DAG: insert.b [[R1]][9], [[R5]]
+  ; ALL-DAG: insert.b [[R1]][10], [[R5]]
+  ; ALL-DAG: insert.b [[R1]][11], [[R5]]
+  ; ALL-DAG: insert.b [[R1]][12], [[R5]]
+  ; ALL-DAG: insert.b [[R1]][13], [[R5]]
+  ; ALL-DAG: insert.b [[R1]][14], [[R5]]
+  ; ALL-DAG: insert.b [[R1]][15], [[R5]]
 
   store volatile <16 x i8> %16, <16 x i8>*@v16i8
 
   ret void
-  ; MIPS32-AE: .size nonconst_v16i8
 }
 
-define void @nonconst_v8i16(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h) nounwind {
-  ; MIPS32-AE-LABEL: nonconst_v8i16:
+define void @nonconst_v8i16(i16 signext %a, i16 signext %b, i16 signext %c, i16 signext %d, i16 signext %e, i16 signext %f, i16 signext %g, i16 signext %h) nounwind {
+  ; ALL-LABEL: nonconst_v8i16:
 
   %1 = insertelement <8 x i16> undef, i16 %a, i32 0
   %2 = insertelement <8 x i16> %1, i16 %b, i32 1
@@ -198,610 +219,648 @@ define void @nonconst_v8i16(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16
   %6 = insertelement <8 x i16> %5, i16 %f, i32 5
   %7 = insertelement <8 x i16> %6, i16 %g, i32 6
   %8 = insertelement <8 x i16> %7, i16 %h, i32 7
-  ; MIPS32-AE-DAG: insert.h [[R1:\$w[0-9]+]][0], $4
-  ; MIPS32-AE-DAG: insert.h [[R1]][1], $5
-  ; MIPS32-AE-DAG: insert.h [[R1]][2], $6
-  ; MIPS32-AE-DAG: insert.h [[R1]][3], $7
-  ; MIPS32-BE-DAG: lhu [[R2:\$[0-9]+]], 18($sp)
-  ; MIPS32-LE-DAG: lhu [[R2:\$[0-9]+]], 16($sp)
-  ; MIPS32-AE-DAG: insert.h [[R1]][4], [[R2]]
-  ; MIPS32-BE-DAG: lhu [[R2:\$[0-9]+]], 22($sp)
-  ; MIPS32-LE-DAG: lhu [[R2:\$[0-9]+]], 20($sp)
-  ; MIPS32-AE-DAG: insert.h [[R1]][5], [[R2]]
-  ; MIPS32-BE-DAG: lhu [[R2:\$[0-9]+]], 26($sp)
-  ; MIPS32-LE-DAG: lhu [[R2:\$[0-9]+]], 24($sp)
-  ; MIPS32-AE-DAG: insert.h [[R1]][6], [[R2]]
-  ; MIPS32-BE-DAG: lhu [[R2:\$[0-9]+]], 30($sp)
-  ; MIPS32-LE-DAG: lhu [[R2:\$[0-9]+]], 28($sp)
-  ; MIPS32-AE-DAG: insert.h [[R1]][7], [[R2]]
+  ; ALL-DAG: insert.h [[R1:\$w[0-9]+]][0], $4
+  ; ALL-DAG: insert.h [[R1]][1], $5
+  ; ALL-DAG: insert.h [[R1]][2], $6
+  ; ALL-DAG: insert.h [[R1]][3], $7
+  ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 16($sp)
+  ; MIPS32-DAG: insert.h [[R1]][4], [[R2]]
+  ; MIPS64-DAG: insert.h [[R1]][4], $8
+  ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 20($sp)
+  ; MIPS32-DAG: insert.h [[R1]][5], [[R2]]
+  ; MIPS64-DAG: insert.h [[R1]][5], $9
+  ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 24($sp)
+  ; MIPS32-DAG: insert.h [[R1]][6], [[R2]]
+  ; MIPS64-DAG: insert.h [[R1]][6], $10
+  ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 28($sp)
+  ; MIPS32-DAG: insert.h [[R1]][7], [[R2]]
+  ; MIPS64-DAG: insert.h [[R1]][7], $11
 
   store volatile <8 x i16> %8, <8 x i16>*@v8i16
 
   ret void
-  ; MIPS32-AE: .size nonconst_v8i16
 }
 
-define void @nonconst_v4i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-  ; MIPS32-AE-LABEL: nonconst_v4i32:
+define void @nonconst_v4i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
+  ; ALL-LABEL: nonconst_v4i32:
 
   %1 = insertelement <4 x i32> undef, i32 %a, i32 0
   %2 = insertelement <4 x i32> %1, i32 %b, i32 1
   %3 = insertelement <4 x i32> %2, i32 %c, i32 2
   %4 = insertelement <4 x i32> %3, i32 %d, i32 3
-  ; MIPS32-AE: insert.w [[R1:\$w[0-9]+]][0], $4
-  ; MIPS32-AE: insert.w [[R1]][1], $5
-  ; MIPS32-AE: insert.w [[R1]][2], $6
-  ; MIPS32-AE: insert.w [[R1]][3], $7
+  ; ALL: insert.w [[R1:\$w[0-9]+]][0], $4
+  ; ALL: insert.w [[R1]][1], $5
+  ; ALL: insert.w [[R1]][2], $6
+  ; ALL: insert.w [[R1]][3], $7
 
   store volatile <4 x i32> %4, <4 x i32>*@v4i32
 
   ret void
-  ; MIPS32-AE: .size nonconst_v4i32
 }
 
-define void @nonconst_v2i64(i64 %a, i64 %b) nounwind {
-  ; MIPS32-AE-LABEL: nonconst_v2i64:
+define void @nonconst_v2i64(i64 signext %a, i64 signext %b) nounwind {
+  ; ALL-LABEL: nonconst_v2i64:
 
   %1 = insertelement <2 x i64> undef, i64 %a, i32 0
   %2 = insertelement <2 x i64> %1, i64 %b, i32 1
-  ; MIPS32-AE: insert.w [[R1:\$w[0-9]+]][0], $4
-  ; MIPS32-AE: insert.w [[R1]][1], $5
-  ; MIPS32-AE: insert.w [[R1]][2], $6
-  ; MIPS32-AE: insert.w [[R1]][3], $7
+  ; MIPS32: insert.w [[R1:\$w[0-9]+]][0], $4
+  ; MIPS32: insert.w [[R1]][1], $5
+  ; MIPS32: insert.w [[R1]][2], $6
+  ; MIPS32: insert.w [[R1]][3], $7
+  ; MIPS64: insert.d [[R1:\$w[0-9]+]][0], $4
+  ; MIPS64: insert.d [[R1]][1], $5
 
   store volatile <2 x i64> %2, <2 x i64>*@v2i64
 
   ret void
-  ; MIPS32-AE: .size nonconst_v2i64
 }
 
 define i32 @extract_sext_v16i8() nounwind {
-  ; MIPS32-AE-LABEL: extract_sext_v16i8:
+  ; ALL-LABEL: extract_sext_v16i8:
 
-  %1 = load <16 x i8>* @v16i8
-  ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]],
+  %1 = load <16 x i8>, <16 x i8>* @v16i8
+  ; ALL-DAG: ld.b [[R1:\$w[0-9]+]],
 
   %2 = add <16 x i8> %1, %1
-  ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <16 x i8> %2, i32 1
   %4 = sext i8 %3 to i32
-  ; MIPS32-AE-DAG: copy_s.b [[R3:\$[0-9]+]], [[R1]][1]
-  ; MIPS32-AE-NOT: sll
-  ; MIPS32-AE-NOT: sra
+  ; ALL-DAG: copy_s.b [[R3:\$[0-9]+]], [[R1]][1]
+  ; ALL-NOT: sll
+  ; ALL-NOT: sra
 
   ret i32 %4
-  ; MIPS32-AE: .size extract_sext_v16i8
 }
 
 define i32 @extract_sext_v8i16() nounwind {
-  ; MIPS32-AE-LABEL: extract_sext_v8i16:
+  ; ALL-LABEL: extract_sext_v8i16:
 
-  %1 = load <8 x i16>* @v8i16
-  ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]],
+  %1 = load <8 x i16>, <8 x i16>* @v8i16
+  ; ALL-DAG: ld.h [[R1:\$w[0-9]+]],
 
   %2 = add <8 x i16> %1, %1
-  ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <8 x i16> %2, i32 1
   %4 = sext i16 %3 to i32
-  ; MIPS32-AE-DAG: copy_s.h [[R3:\$[0-9]+]], [[R1]][1]
-  ; MIPS32-AE-NOT: sll
-  ; MIPS32-AE-NOT: sra
+  ; ALL-DAG: copy_s.h [[R3:\$[0-9]+]], [[R1]][1]
+  ; ALL-NOT: sll
+  ; ALL-NOT: sra
 
   ret i32 %4
-  ; MIPS32-AE: .size extract_sext_v8i16
 }
 
 define i32 @extract_sext_v4i32() nounwind {
-  ; MIPS32-AE-LABEL: extract_sext_v4i32:
+  ; ALL-LABEL: extract_sext_v4i32:
 
-  %1 = load <4 x i32>* @v4i32
-  ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
+  %1 = load <4 x i32>, <4 x i32>* @v4i32
+  ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
 
   %2 = add <4 x i32> %1, %1
-  ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <4 x i32> %2, i32 1
-  ; MIPS32-AE-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][1]
+  ; ALL-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][1]
 
   ret i32 %3
-  ; MIPS32-AE: .size extract_sext_v4i32
 }
 
 define i64 @extract_sext_v2i64() nounwind {
-  ; MIPS32-AE-LABEL: extract_sext_v2i64:
+  ; ALL-LABEL: extract_sext_v2i64:
 
-  %1 = load <2 x i64>* @v2i64
-  ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]],
+  %1 = load <2 x i64>, <2 x i64>* @v2i64
+  ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],
 
   %2 = add <2 x i64> %1, %1
-  ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <2 x i64> %2, i32 1
-  ; MIPS32-AE-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][2]
-  ; MIPS32-AE-DAG: copy_s.w [[R4:\$[0-9]+]], [[R1]][3]
-  ; MIPS32-AE-NOT: sll
-  ; MIPS32-AE-NOT: sra
+  ; MIPS32-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][2]
+  ; MIPS32-DAG: copy_s.w [[R4:\$[0-9]+]], [[R1]][3]
+  ; MIPS64-DAG: copy_s.d [[R3:\$[0-9]+]], [[R1]][1]
+  ; ALL-NOT: sll
+  ; ALL-NOT: sra
 
   ret i64 %3
-  ; MIPS32-AE: .size extract_sext_v2i64
 }
 
 define i32 @extract_zext_v16i8() nounwind {
-  ; MIPS32-AE-LABEL: extract_zext_v16i8:
+  ; ALL-LABEL: extract_zext_v16i8:
 
-  %1 = load <16 x i8>* @v16i8
-  ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]],
+  %1 = load <16 x i8>, <16 x i8>* @v16i8
+  ; ALL-DAG: ld.b [[R1:\$w[0-9]+]],
 
   %2 = add <16 x i8> %1, %1
-  ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <16 x i8> %2, i32 1
   %4 = zext i8 %3 to i32
-  ; MIPS32-AE-DAG: copy_u.b [[R3:\$[0-9]+]], [[R1]][1]
-  ; MIPS32-AE-NOT: andi
+  ; ALL-DAG: copy_u.b [[R3:\$[0-9]+]], [[R1]][1]
+  ; ALL-NOT: andi
 
   ret i32 %4
-  ; MIPS32-AE: .size extract_zext_v16i8
 }
 
 define i32 @extract_zext_v8i16() nounwind {
-  ; MIPS32-AE-LABEL: extract_zext_v8i16:
+  ; ALL-LABEL: extract_zext_v8i16:
 
-  %1 = load <8 x i16>* @v8i16
-  ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]],
+  %1 = load <8 x i16>, <8 x i16>* @v8i16
+  ; ALL-DAG: ld.h [[R1:\$w[0-9]+]],
 
   %2 = add <8 x i16> %1, %1
-  ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <8 x i16> %2, i32 1
   %4 = zext i16 %3 to i32
-  ; MIPS32-AE-DAG: copy_u.h [[R3:\$[0-9]+]], [[R1]][1]
-  ; MIPS32-AE-NOT: andi
+  ; ALL-DAG: copy_u.h [[R3:\$[0-9]+]], [[R1]][1]
+  ; ALL-NOT: andi
 
   ret i32 %4
-  ; MIPS32-AE: .size extract_zext_v8i16
 }
 
 define i32 @extract_zext_v4i32() nounwind {
-  ; MIPS32-AE-LABEL: extract_zext_v4i32:
+  ; ALL-LABEL: extract_zext_v4i32:
 
-  %1 = load <4 x i32>* @v4i32
-  ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
+  %1 = load <4 x i32>, <4 x i32>* @v4i32
+  ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
 
   %2 = add <4 x i32> %1, %1
-  ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <4 x i32> %2, i32 1
-  ; MIPS32-AE-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][1]
+  ; ALL-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][1]
 
   ret i32 %3
-  ; MIPS32-AE: .size extract_zext_v4i32
 }
 
 define i64 @extract_zext_v2i64() nounwind {
-  ; MIPS32-AE-LABEL: extract_zext_v2i64:
+  ; ALL-LABEL: extract_zext_v2i64:
 
-  %1 = load <2 x i64>* @v2i64
-  ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]],
+  %1 = load <2 x i64>, <2 x i64>* @v2i64
+  ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],
 
   %2 = add <2 x i64> %1, %1
-  ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <2 x i64> %2, i32 1
-  ; MIPS32-AE-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][2]
-  ; MIPS32-AE-DAG: copy_{{[su]}}.w [[R4:\$[0-9]+]], [[R1]][3]
-  ; MIPS32-AE-NOT: andi
+  ; MIPS32-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][2]
+  ; MIPS32-DAG: copy_{{[su]}}.w [[R4:\$[0-9]+]], [[R1]][3]
+  ; MIPS64-DAG: copy_{{[su]}}.d [[R3:\$[0-9]+]], [[R1]][1]
+  ; ALL-NOT: andi
 
   ret i64 %3
-  ; MIPS32-AE: .size extract_zext_v2i64
 }
 
 define i32 @extract_sext_v16i8_vidx() nounwind {
-  ; MIPS32-AE-LABEL: extract_sext_v16i8_vidx:
+  ; ALL-LABEL: extract_sext_v16i8_vidx:
 
-  %1 = load <16 x i8>* @v16i8
-  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
-  ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]])
+  %1 = load <16 x i8>, <16 x i8>* @v16i8
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v16i8)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v16i8)(
+  ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <16 x i8> %1, %1
-  ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
-  %3 = load i32* @i32
-  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %3 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <16 x i8> %2, i32 %3
   %5 = sext i8 %4 to i32
-  ; MIPS32-AE-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
-  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
-  ; MIPS32-AE-DAG: sra [[R6:\$[0-9]+]], [[R5]], 24
+  ; ALL-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; ALL-DAG: sra [[R6:\$[0-9]+]], [[R5]], 24
 
   ret i32 %5
-  ; MIPS32-AE: .size extract_sext_v16i8_vidx
 }
 
 define i32 @extract_sext_v8i16_vidx() nounwind {
-  ; MIPS32-AE-LABEL: extract_sext_v8i16_vidx:
+  ; ALL-LABEL: extract_sext_v8i16_vidx:
 
-  %1 = load <8 x i16>* @v8i16
-  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
-  ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]])
+  %1 = load <8 x i16>, <8 x i16>* @v8i16
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v8i16)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v8i16)(
+  ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <8 x i16> %1, %1
-  ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
-  %3 = load i32* @i32
-  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %3 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <8 x i16> %2, i32 %3
   %5 = sext i16 %4 to i32
-  ; MIPS32-AE-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
-  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
-  ; MIPS32-AE-DAG: sra [[R6:\$[0-9]+]], [[R5]], 16
+  ; ALL-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; ALL-DAG: sra [[R6:\$[0-9]+]], [[R5]], 16
 
   ret i32 %5
-  ; MIPS32-AE: .size extract_sext_v8i16_vidx
 }
 
 define i32 @extract_sext_v4i32_vidx() nounwind {
-  ; MIPS32-AE-LABEL: extract_sext_v4i32_vidx:
+  ; ALL-LABEL: extract_sext_v4i32_vidx:
 
-  %1 = load <4 x i32>* @v4i32
-  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
-  ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
+  %1 = load <4 x i32>, <4 x i32>* @v4i32
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4i32)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4i32)(
+  ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <4 x i32> %1, %1
-  ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
-  %3 = load i32* @i32
-  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %3 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <4 x i32> %2, i32 %3
-  ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
-  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
-  ; MIPS32-AE-NOT: sra
+  ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; ALL-NOT: sra
 
   ret i32 %4
-  ; MIPS32-AE: .size extract_sext_v4i32_vidx
 }
 
 define i64 @extract_sext_v2i64_vidx() nounwind {
-  ; MIPS32-AE-LABEL: extract_sext_v2i64_vidx:
+  ; ALL-LABEL: extract_sext_v2i64_vidx:
 
-  %1 = load <2 x i64>* @v2i64
-  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
-  ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
+  %1 = load <2 x i64>, <2 x i64>* @v2i64
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2i64)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2i64)(
+  ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <2 x i64> %1, %1
-  ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
-  %3 = load i32* @i32
-  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %3 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <2 x i64> %2, i32 %3
-  ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
-  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
-  ; MIPS32-AE-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
-  ; MIPS32-AE-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
-  ; MIPS32-AE-NOT: sra
+  ; MIPS32-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; MIPS32-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
+  ; MIPS64-DAG: splat.d $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS64-DAG: dmfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; ALL-NOT: sra
 
   ret i64 %4
-  ; MIPS32-AE: .size extract_sext_v2i64_vidx
 }
 
 define i32 @extract_zext_v16i8_vidx() nounwind {
-  ; MIPS32-AE-LABEL: extract_zext_v16i8_vidx:
+  ; ALL-LABEL: extract_zext_v16i8_vidx:
 
-  %1 = load <16 x i8>* @v16i8
-  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
-  ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]])
+  %1 = load <16 x i8>, <16 x i8>* @v16i8
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v16i8)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v16i8)(
+  ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <16 x i8> %1, %1
-  ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
-  %3 = load i32* @i32
-  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %3 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <16 x i8> %2, i32 %3
   %5 = zext i8 %4 to i32
-  ; MIPS32-AE-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
-  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
-  ; MIPS32-AE-DAG: srl [[R6:\$[0-9]+]], [[R5]], 24
+  ; ALL-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; ALL-DAG: srl [[R6:\$[0-9]+]], [[R5]], 24
 
   ret i32 %5
-  ; MIPS32-AE: .size extract_zext_v16i8_vidx
 }
 
 define i32 @extract_zext_v8i16_vidx() nounwind {
-  ; MIPS32-AE-LABEL: extract_zext_v8i16_vidx:
+  ; ALL-LABEL: extract_zext_v8i16_vidx:
 
-  %1 = load <8 x i16>* @v8i16
-  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
-  ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]])
+  %1 = load <8 x i16>, <8 x i16>* @v8i16
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v8i16)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v8i16)(
+  ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <8 x i16> %1, %1
-  ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
-  %3 = load i32* @i32
-  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %3 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <8 x i16> %2, i32 %3
   %5 = zext i16 %4 to i32
-  ; MIPS32-AE-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
-  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
-  ; MIPS32-AE-DAG: srl [[R6:\$[0-9]+]], [[R5]], 16
+  ; ALL-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; ALL-DAG: srl [[R6:\$[0-9]+]], [[R5]], 16
 
   ret i32 %5
-  ; MIPS32-AE: .size extract_zext_v8i16_vidx
 }
 
 define i32 @extract_zext_v4i32_vidx() nounwind {
-  ; MIPS32-AE-LABEL: extract_zext_v4i32_vidx:
+  ; ALL-LABEL: extract_zext_v4i32_vidx:
 
-  %1 = load <4 x i32>* @v4i32
-  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
-  ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
+  %1 = load <4 x i32>, <4 x i32>* @v4i32
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4i32)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4i32)(
+  ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <4 x i32> %1, %1
-  ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
-  %3 = load i32* @i32
-  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %3 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <4 x i32> %2, i32 %3
-  ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
-  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
-  ; MIPS32-AE-NOT: srl
+  ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; ALL-NOT: srl
 
   ret i32 %4
-  ; MIPS32-AE: .size extract_zext_v4i32_vidx
 }
 
 define i64 @extract_zext_v2i64_vidx() nounwind {
-  ; MIPS32-AE-LABEL: extract_zext_v2i64_vidx:
+  ; ALL-LABEL: extract_zext_v2i64_vidx:
 
-  %1 = load <2 x i64>* @v2i64
-  ; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
-  ; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
+  %1 = load <2 x i64>, <2 x i64>* @v2i64
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2i64)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2i64)(
+  ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <2 x i64> %1, %1
-  ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
-  %3 = load i32* @i32
-  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %3 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <2 x i64> %2, i32 %3
-  ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
-  ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
-  ; MIPS32-AE-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
-  ; MIPS32-AE-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
-  ; MIPS32-AE-NOT: srl
+  ; MIPS32-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; MIPS32-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
+  ; MIPS64-DAG: splat.d $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS64-DAG: dmfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; ALL-NOT: srl
 
   ret i64 %4
-  ; MIPS32-AE: .size extract_zext_v2i64_vidx
 }
 
-define void @insert_v16i8(i32 %a) nounwind {
-  ; MIPS32-AE-LABEL: insert_v16i8:
+define void @insert_v16i8(i32 signext %a) nounwind {
+  ; ALL-LABEL: insert_v16i8:
 
-  %1 = load <16 x i8>* @v16i8
-  ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]],
+  %1 = load <16 x i8>, <16 x i8>* @v16i8
+  ; ALL-DAG: ld.b [[R1:\$w[0-9]+]],
 
   %a2 = trunc i32 %a to i8
   %a3 = sext i8 %a2 to i32
   %a4 = trunc i32 %a3 to i8
-  ; MIPS32-AE-NOT: andi
-  ; MIPS32-AE-NOT: sra
+  ; ALL-NOT: andi
+  ; ALL-NOT: sra
 
   %2 = insertelement <16 x i8> %1, i8 %a4, i32 1
-  ; MIPS32-AE-DAG: insert.b [[R1]][1], $4
+  ; ALL-DAG: insert.b [[R1]][1], $4
 
   store <16 x i8> %2, <16 x i8>* @v16i8
-  ; MIPS32-AE-DAG: st.b [[R1]]
+  ; ALL-DAG: st.b [[R1]]
 
   ret void
-  ; MIPS32-AE: .size insert_v16i8
 }
 
-define void @insert_v8i16(i32 %a) nounwind {
-  ; MIPS32-AE-LABEL: insert_v8i16:
+define void @insert_v8i16(i32 signext %a) nounwind {
+  ; ALL-LABEL: insert_v8i16:
 
-  %1 = load <8 x i16>* @v8i16
-  ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]],
+  %1 = load <8 x i16>, <8 x i16>* @v8i16
+  ; ALL-DAG: ld.h [[R1:\$w[0-9]+]],
 
   %a2 = trunc i32 %a to i16
   %a3 = sext i16 %a2 to i32
   %a4 = trunc i32 %a3 to i16
-  ; MIPS32-AE-NOT: andi
-  ; MIPS32-AE-NOT: sra
+  ; ALL-NOT: andi
+  ; ALL-NOT: sra
 
   %2 = insertelement <8 x i16> %1, i16 %a4, i32 1
-  ; MIPS32-AE-DAG: insert.h [[R1]][1], $4
+  ; ALL-DAG: insert.h [[R1]][1], $4
 
   store <8 x i16> %2, <8 x i16>* @v8i16
-  ; MIPS32-AE-DAG: st.h [[R1]]
+  ; ALL-DAG: st.h [[R1]]
 
   ret void
-  ; MIPS32-AE: .size insert_v8i16
 }
 
-define void @insert_v4i32(i32 %a) nounwind {
-  ; MIPS32-AE-LABEL: insert_v4i32:
+define void @insert_v4i32(i32 signext %a) nounwind {
+  ; ALL-LABEL: insert_v4i32:
 
-  %1 = load <4 x i32>* @v4i32
-  ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
+  %1 = load <4 x i32>, <4 x i32>* @v4i32
+  ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
 
-  ; MIPS32-AE-NOT: andi
-  ; MIPS32-AE-NOT: sra
+  ; ALL-NOT: andi
+  ; ALL-NOT: sra
 
   %2 = insertelement <4 x i32> %1, i32 %a, i32 1
-  ; MIPS32-AE-DAG: insert.w [[R1]][1], $4
+  ; ALL-DAG: insert.w [[R1]][1], $4
 
   store <4 x i32> %2, <4 x i32>* @v4i32
-  ; MIPS32-AE-DAG: st.w [[R1]]
+  ; ALL-DAG: st.w [[R1]]
 
   ret void
-  ; MIPS32-AE: .size insert_v4i32
 }
 
-define void @insert_v2i64(i64 %a) nounwind {
-  ; MIPS32-AE-LABEL: insert_v2i64:
+define void @insert_v2i64(i64 signext %a) nounwind {
+  ; ALL-LABEL: insert_v2i64:
 
-  %1 = load <2 x i64>* @v2i64
-  ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
+  %1 = load <2 x i64>, <2 x i64>* @v2i64
+  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
+  ; MIPS64-DAG: ld.d [[R1:\$w[0-9]+]],
 
-  ; MIPS32-AE-NOT: andi
-  ; MIPS32-AE-NOT: sra
+  ; ALL-NOT: andi
+  ; ALL-NOT: sra
 
   %2 = insertelement <2 x i64> %1, i64 %a, i32 1
-  ; MIPS32-AE-DAG: insert.w [[R1]][2], $4
-  ; MIPS32-AE-DAG: insert.w [[R1]][3], $5
+  ; MIPS32-DAG: insert.w [[R1]][2], $4
+  ; MIPS32-DAG: insert.w [[R1]][3], $5
+  ; MIPS64-DAG: insert.d [[R1]][1], $4
 
   store <2 x i64> %2, <2 x i64>* @v2i64
-  ; MIPS32-AE-DAG: st.w [[R1]]
+  ; MIPS32-DAG: st.w [[R1]]
+  ; MIPS64-DAG: st.d [[R1]]
 
   ret void
-  ; MIPS32-AE: .size insert_v2i64
 }
 
-define void @insert_v16i8_vidx(i32 %a) nounwind {
-  ; MIPS32-AE: insert_v16i8_vidx:
+define void @insert_v16i8_vidx(i32 signext %a) nounwind {
+  ; ALL-LABEL: insert_v16i8_vidx:
 
-  %1 = load <16 x i8>* @v16i8
-  ; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]],
+  %1 = load <16 x i8>, <16 x i8>* @v16i8
+  ; ALL-DAG: ld.b [[R1:\$w[0-9]+]],
 
-  %2 = load i32* @i32
-  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %2 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %a2 = trunc i32 %a to i8
   %a3 = sext i8 %a2 to i32
   %a4 = trunc i32 %a3 to i8
-  ; MIPS32-AE-NOT: andi
-  ; MIPS32-AE-NOT: sra
+  ; ALL-NOT: andi
+  ; ALL-NOT: sra
 
   %3 = insertelement <16 x i8> %1, i8 %a4, i32 %2
-  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[IDX]]]
-  ; MIPS32-AE-DAG: insert.b [[R1]][0], $4
-  ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]]
-  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+  ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[IDX]]]
+  ; ALL-DAG: insert.b [[R1]][0], $4
+  ; O32-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]]
+  ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]]
+  ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[IDX]]
+  ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
 
   store <16 x i8> %3, <16 x i8>* @v16i8
-  ; MIPS32-AE-DAG: st.b [[R1]]
+  ; ALL-DAG: st.b [[R1]]
 
   ret void
-  ; MIPS32-AE: .size insert_v16i8_vidx
 }
 
-define void @insert_v8i16_vidx(i32 %a) nounwind {
-  ; MIPS32-AE: insert_v8i16_vidx:
+define void @insert_v8i16_vidx(i32 signext %a) nounwind {
+  ; ALL-LABEL: insert_v8i16_vidx:
 
-  %1 = load <8 x i16>* @v8i16
-  ; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]],
+  %1 = load <8 x i16>, <8 x i16>* @v8i16
+  ; ALL-DAG: ld.h [[R1:\$w[0-9]+]],
 
-  %2 = load i32* @i32
-  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %2 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %a2 = trunc i32 %a to i16
   %a3 = sext i16 %a2 to i32
   %a4 = trunc i32 %a3 to i16
-  ; MIPS32-AE-NOT: andi
-  ; MIPS32-AE-NOT: sra
+  ; ALL-NOT: andi
+  ; ALL-NOT: sra
 
   %3 = insertelement <8 x i16> %1, i16 %a4, i32 %2
-  ; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 1
-  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
-  ; MIPS32-AE-DAG: insert.h [[R1]][0], $4
-  ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
-  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+  ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 1
+  ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; ALL-DAG: insert.h [[R1]][0], $4
+  ; O32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
 
   store <8 x i16> %3, <8 x i16>* @v8i16
-  ; MIPS32-AE-DAG: st.h [[R1]]
+  ; ALL-DAG: st.h [[R1]]
 
   ret void
-  ; MIPS32-AE: .size insert_v8i16_vidx
 }
 
-define void @insert_v4i32_vidx(i32 %a) nounwind {
-  ; MIPS32-AE: insert_v4i32_vidx:
+define void @insert_v4i32_vidx(i32 signext %a) nounwind {
+  ; ALL-LABEL: insert_v4i32_vidx:
 
-  %1 = load <4 x i32>* @v4i32
-  ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
+  %1 = load <4 x i32>, <4 x i32>* @v4i32
+  ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
 
-  %2 = load i32* @i32
-  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %2 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
-  ; MIPS32-AE-NOT: andi
-  ; MIPS32-AE-NOT: sra
+  ; ALL-NOT: andi
+  ; ALL-NOT: sra
 
   %3 = insertelement <4 x i32> %1, i32 %a, i32 %2
-  ; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
-  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
-  ; MIPS32-AE-DAG: insert.w [[R1]][0], $4
-  ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
-  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+  ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
+  ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; ALL-DAG: insert.w [[R1]][0], $4
+  ; O32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
 
   store <4 x i32> %3, <4 x i32>* @v4i32
-  ; MIPS32-AE-DAG: st.w [[R1]]
+  ; ALL-DAG: st.w [[R1]]
 
   ret void
-  ; MIPS32-AE: .size insert_v4i32_vidx
 }
 
-define void @insert_v2i64_vidx(i64 %a) nounwind {
-  ; MIPS32-AE: insert_v2i64_vidx:
+define void @insert_v2i64_vidx(i64 signext %a) nounwind {
+  ; ALL-LABEL: insert_v2i64_vidx:
 
-  %1 = load <2 x i64>* @v2i64
-  ; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
+  %1 = load <2 x i64>, <2 x i64>* @v2i64
+  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
+  ; MIPS64-DAG: ld.d [[R1:\$w[0-9]+]],
 
-  %2 = load i32* @i32
-  ; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %2 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
-  ; MIPS32-AE-NOT: andi
-  ; MIPS32-AE-NOT: sra
+  ; ALL-NOT: andi
+  ; ALL-NOT: sra
 
   %3 = insertelement <2 x i64> %1, i64 %a, i32 %2
   ; TODO: This code could be a lot better but it works. The legalizer splits
   ; 64-bit inserts into two 32-bit inserts because there is no i64 type on
   ; MIPS32. The obvious optimisation is to perform both insert.w's at once while
   ; the vector is rotated.
-  ; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
-  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
-  ; MIPS32-AE-DAG: insert.w [[R1]][0], $4
-  ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
-  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
-  ; MIPS32-AE-DAG: addiu [[IDX2:\$[0-9]+]], [[IDX]], 1
-  ; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX2]], 2
-  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
-  ; MIPS32-AE-DAG: insert.w [[R1]][0], $5
-  ; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
-  ; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+  ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
+  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; MIPS32-DAG: insert.w [[R1]][0], $4
+  ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+  ; MIPS32-DAG: addiu [[IDX2:\$[0-9]+]], [[IDX]], 1
+  ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX2]], 2
+  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; MIPS32-DAG: insert.w [[R1]][0], $5
+  ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+
+  ; MIPS64-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3
+  ; MIPS64-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; MIPS64-DAG: insert.d [[R1]][0], $4
+  ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; MIPS64-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
 
   store <2 x i64> %3, <2 x i64>* @v2i64
-  ; MIPS32-AE-DAG: st.w [[R1]]
+  ; MIPS32-DAG: st.w [[R1]]
+  ; MIPS64-DAG: st.d [[R1]]
 
   ret void
-  ; MIPS32-AE: .size insert_v2i64_vidx
 }
 
 define void @truncstore() nounwind {
-  ; MIPS32-AE-LABEL: truncstore:
+  ; ALL-LABEL: truncstore:
 
   store volatile <4 x i8> <i8 -1, i8 -1, i8 -1, i8 -1>, <4 x i8>*@v4i8
   ; TODO: What code should be emitted?
 
   ret void
-  ; MIPS32-AE: .size truncstore
 }
diff --git a/test/CodeGen/Mips/msa/basic_operations_float.ll b/test/CodeGen/Mips/msa/basic_operations_float.ll
index a0c9d29e231a..f19cb9b7c2e5 100644
--- a/test/CodeGen/Mips/msa/basic_operations_float.ll
+++ b/test/CodeGen/Mips/msa/basic_operations_float.ll
@@ -1,5 +1,9 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
+; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 %s
+; RUN: llc -march=mips64 -target-abi=n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 %s
+; RUN: llc -march=mips64el -target-abi=n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 %s
+; RUN: llc -march=mips64 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 %s
+; RUN: llc -march=mips64el -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 %s
 
 @v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
 @v2f64 = global <2 x double> <double 0.0, double 0.0>
@@ -8,322 +12,341 @@
 @f64 = global double 0.0
 
 define void @const_v4f32() nounwind {
-  ; MIPS32-LABEL: const_v4f32:
+  ; ALL-LABEL: const_v4f32:
 
   store volatile <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>*@v4f32
-  ; MIPS32: ldi.b  [[R1:\$w[0-9]+]], 0
+  ; ALL: ldi.b  [[R1:\$w[0-9]+]], 0
 
   store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float>*@v4f32
-  ; MIPS32: lui     [[R1:\$[0-9]+]], 16256
-  ; MIPS32: fill.w  [[R2:\$w[0-9]+]], [[R1]]
+  ; ALL: lui     [[R1:\$[0-9]+]], 16256
+  ; ALL: fill.w  [[R2:\$w[0-9]+]], [[R1]]
 
   store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
-  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
-  ; MIPS32: lui     [[R1:\$[0-9]+]], 18304
-  ; MIPS32: ori     [[R2:\$[0-9]+]], [[R1]], 128
-  ; MIPS32: fill.w  [[R3:\$w[0-9]+]], [[R2]]
+  ; ALL: lui     [[R1:\$[0-9]+]], 18304
+  ; ALL: ori     [[R2:\$[0-9]+]], [[R1]], 128
+  ; ALL: fill.w  [[R3:\$w[0-9]+]], [[R2]]
 
   store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
-  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
-  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   ret void
-  ; MIPS32: .size const_v4f32
 }
 
 define void @const_v2f64() nounwind {
-  ; MIPS32-LABEL: const_v2f64:
+  ; ALL-LABEL: const_v2f64:
 
   store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64
-  ; MIPS32: ldi.b  [[R1:\$w[0-9]+]], 0
+  ; ALL: ldi.b  [[R1:\$w[0-9]+]], 0
 
   store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
-  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
-  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
-  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
-  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
-  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
-  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; ALL: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   ret void
-  ; MIPS32: .size const_v2f64
 }
 
 define void @nonconst_v4f32() nounwind {
-  ; MIPS32-LABEL: nonconst_v4f32:
+  ; ALL-LABEL: nonconst_v4f32:
 
-  %1 = load float *@f32
+  %1 = load float , float *@f32
   %2 = insertelement <4 x float> undef, float %1, i32 0
   %3 = insertelement <4 x float> %2, float %1, i32 1
   %4 = insertelement <4 x float> %3, float %1, i32 2
   %5 = insertelement <4 x float> %4, float %1, i32 3
   store volatile <4 x float> %5, <4 x float>*@v4f32
-  ; MIPS32: lwc1 $f[[R1:[0-9]+]], 0(
-  ; MIPS32: splati.w [[R2:\$w[0-9]+]], $w[[R1]]
+  ; ALL: lwc1 $f[[R1:[0-9]+]], 0(
+  ; ALL: splati.w [[R2:\$w[0-9]+]], $w[[R1]]
 
   ret void
-  ; MIPS32: .size nonconst_v4f32
 }
 
 define void @nonconst_v2f64() nounwind {
-  ; MIPS32-LABEL: nonconst_v2f64:
+  ; ALL-LABEL: nonconst_v2f64:
 
-  %1 = load double *@f64
+  %1 = load double , double *@f64
   %2 = insertelement <2 x double> undef, double %1, i32 0
   %3 = insertelement <2 x double> %2, double %1, i32 1
   store volatile <2 x double> %3, <2 x double>*@v2f64
-  ; MIPS32: ldc1 $f[[R1:[0-9]+]], 0(
-  ; MIPS32: splati.d [[R2:\$w[0-9]+]], $w[[R1]]
+  ; ALL: ldc1 $f[[R1:[0-9]+]], 0(
+  ; ALL: splati.d [[R2:\$w[0-9]+]], $w[[R1]]
 
   ret void
-  ; MIPS32: .size nonconst_v2f64
 }
 
 define float @extract_v4f32() nounwind {
-  ; MIPS32-LABEL: extract_v4f32:
+  ; ALL-LABEL: extract_v4f32:
 
-  %1 = load <4 x float>* @v4f32
-  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
+  %1 = load <4 x float>, <4 x float>* @v4f32
+  ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
 
   %2 = fadd <4 x float> %1, %1
-  ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <4 x float> %2, i32 1
   ; Element 1 can be obtained by splatting it across the vector and extracting
   ; $w0:sub_lo
-  ; MIPS32-DAG: splati.w $w0, [[R1]][1]
+  ; ALL-DAG: splati.w $w0, [[R1]][1]
 
   ret float %3
-  ; MIPS32: .size extract_v4f32
 }
 
 define float @extract_v4f32_elt0() nounwind {
-  ; MIPS32-LABEL: extract_v4f32_elt0:
+  ; ALL-LABEL: extract_v4f32_elt0:
 
-  %1 = load <4 x float>* @v4f32
-  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
+  %1 = load <4 x float>, <4 x float>* @v4f32
+  ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
 
   %2 = fadd <4 x float> %1, %1
-  ; MIPS32-DAG: fadd.w $w0, [[R1]], [[R1]]
+  ; ALL-DAG: fadd.w $w0, [[R1]], [[R1]]
 
   %3 = extractelement <4 x float> %2, i32 0
   ; Element 0 can be obtained by extracting $w0:sub_lo ($f0)
-  ; MIPS32-NOT: copy_u.w
-  ; MIPS32-NOT: mtc1
+  ; ALL-NOT: copy_u.w
+  ; ALL-NOT: mtc1
 
   ret float %3
-  ; MIPS32: .size extract_v4f32_elt0
 }
 
 define float @extract_v4f32_elt2() nounwind {
-  ; MIPS32-LABEL: extract_v4f32_elt2:
+  ; ALL-LABEL: extract_v4f32_elt2:
 
-  %1 = load <4 x float>* @v4f32
-  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
+  %1 = load <4 x float>, <4 x float>* @v4f32
+  ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
 
   %2 = fadd <4 x float> %1, %1
-  ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <4 x float> %2, i32 2
   ; Element 2 can be obtained by splatting it across the vector and extracting
   ; $w0:sub_lo
-  ; MIPS32-DAG: splati.w $w0, [[R1]][2]
+  ; ALL-DAG: splati.w $w0, [[R1]][2]
 
   ret float %3
-  ; MIPS32: .size extract_v4f32_elt2
 }
 
 define float @extract_v4f32_vidx() nounwind {
-  ; MIPS32-LABEL: extract_v4f32_vidx:
+  ; ALL-LABEL: extract_v4f32_vidx:
 
-  %1 = load <4 x float>* @v4f32
-  ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
-  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
+  %1 = load <4 x float>, <4 x float>* @v4f32
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(
+  ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = fadd <4 x float> %1, %1
-  ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
-  %3 = load i32* @i32
-  ; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %3 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <4 x float> %2, i32 %3
-  ; MIPS32-DAG: splat.w $w0, [[R1]]{{\[}}[[IDX]]]
+  ; ALL-DAG: splat.w $w0, [[R1]]{{\[}}[[IDX]]]
 
   ret float %4
-  ; MIPS32: .size extract_v4f32_vidx
 }
 
 define double @extract_v2f64() nounwind {
-  ; MIPS32-LABEL: extract_v2f64:
+  ; ALL-LABEL: extract_v2f64:
 
-  %1 = load <2 x double>* @v2f64
-  ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
+  %1 = load <2 x double>, <2 x double>* @v2f64
+  ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],
 
   %2 = fadd <2 x double> %1, %1
-  ; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <2 x double> %2, i32 1
   ; Element 1 can be obtained by splatting it across the vector and extracting
   ; $w0:sub_64
-  ; MIPS32-DAG: splati.d $w0, [[R1]][1]
-  ; MIPS32-NOT: copy_u.w
-  ; MIPS32-NOT: mtc1
-  ; MIPS32-NOT: mthc1
-  ; MIPS32-NOT: sll
-  ; MIPS32-NOT: sra
+  ; ALL-DAG: splati.d $w0, [[R1]][1]
+  ; ALL-NOT: copy_u.w
+  ; ALL-NOT: mtc1
+  ; ALL-NOT: mthc1
+  ; ALL-NOT: sll
+  ; ALL-NOT: sra
 
   ret double %3
-  ; MIPS32: .size extract_v2f64
 }
 
 define double @extract_v2f64_elt0() nounwind {
-  ; MIPS32-LABEL: extract_v2f64_elt0:
+  ; ALL-LABEL: extract_v2f64_elt0:
 
-  %1 = load <2 x double>* @v2f64
-  ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
+  %1 = load <2 x double>, <2 x double>* @v2f64
+  ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],
 
   %2 = fadd <2 x double> %1, %1
-  ; MIPS32-DAG: fadd.d $w0, [[R1]], [[R1]]
+  ; ALL-DAG: fadd.d $w0, [[R1]], [[R1]]
 
   %3 = extractelement <2 x double> %2, i32 0
   ; Element 0 can be obtained by extracting $w0:sub_64 ($f0)
-  ; MIPS32-NOT: copy_u.w
-  ; MIPS32-NOT: mtc1
-  ; MIPS32-NOT: mthc1
-  ; MIPS32-NOT: sll
-  ; MIPS32-NOT: sra
+  ; ALL-NOT: copy_u.w
+  ; ALL-NOT: mtc1
+  ; ALL-NOT: mthc1
+  ; ALL-NOT: sll
+  ; ALL-NOT: sra
 
   ret double %3
-  ; MIPS32: .size extract_v2f64_elt0
 }
 
 define double @extract_v2f64_vidx() nounwind {
-  ; MIPS32-LABEL: extract_v2f64_vidx:
+  ; ALL-LABEL: extract_v2f64_vidx:
 
-  %1 = load <2 x double>* @v2f64
-  ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
-  ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
+  %1 = load <2 x double>, <2 x double>* @v2f64
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(
+  ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = fadd <2 x double> %1, %1
-  ; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+  ; ALL-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
-  %3 = load i32* @i32
-  ; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %3 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <2 x double> %2, i32 %3
-  ; MIPS32-DAG: splat.d $w0, [[R1]]{{\[}}[[IDX]]]
+  ; ALL-DAG: splat.d $w0, [[R1]]{{\[}}[[IDX]]]
 
   ret double %4
-  ; MIPS32: .size extract_v2f64_vidx
 }
 
 define void @insert_v4f32(float %a) nounwind {
-  ; MIPS32-LABEL: insert_v4f32:
+  ; ALL-LABEL: insert_v4f32:
 
-  %1 = load <4 x float>* @v4f32
-  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
+  %1 = load <4 x float>, <4 x float>* @v4f32
+  ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
 
   %2 = insertelement <4 x float> %1, float %a, i32 1
   ; float argument passed in $f12
-  ; MIPS32-DAG: insve.w [[R1]][1], $w12[0]
+  ; ALL-DAG: insve.w [[R1]][1], $w12[0]
 
   store <4 x float> %2, <4 x float>* @v4f32
-  ; MIPS32-DAG: st.w [[R1]]
+  ; ALL-DAG: st.w [[R1]]
 
   ret void
-  ; MIPS32: .size insert_v4f32
 }
 
 define void @insert_v2f64(double %a) nounwind {
-  ; MIPS32-LABEL: insert_v2f64:
+  ; ALL-LABEL: insert_v2f64:
 
-  %1 = load <2 x double>* @v2f64
-  ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
+  %1 = load <2 x double>, <2 x double>* @v2f64
+  ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],
 
   %2 = insertelement <2 x double> %1, double %a, i32 1
   ; double argument passed in $f12
-  ; MIPS32-DAG: insve.d [[R1]][1], $w12[0]
+  ; ALL-DAG: insve.d [[R1]][1], $w12[0]
 
   store <2 x double> %2, <2 x double>* @v2f64
-  ; MIPS32-DAG: st.d [[R1]]
+  ; ALL-DAG: st.d [[R1]]
 
   ret void
-  ; MIPS32: .size insert_v2f64
 }
 
 define void @insert_v4f32_vidx(float %a) nounwind {
-  ; MIPS32-LABEL: insert_v4f32_vidx:
+  ; ALL-LABEL: insert_v4f32_vidx:
 
-  %1 = load <4 x float>* @v4f32
-  ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
-  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
+  %1 = load <4 x float>, <4 x float>* @v4f32
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(
+  ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
-  %2 = load i32* @i32
-  ; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %2 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %3 = insertelement <4 x float> %1, float %a, i32 %2
   ; float argument passed in $f12
-  ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
-  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
-  ; MIPS32-DAG: insve.w [[R1]][0], $w12[0]
-  ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
-  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+  ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
+  ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; ALL-DAG: insve.w [[R1]][0], $w12[0]
+  ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
 
   store <4 x float> %3, <4 x float>* @v4f32
-  ; MIPS32-DAG: st.w [[R1]]
+  ; ALL-DAG: st.w [[R1]]
 
   ret void
-  ; MIPS32: .size insert_v4f32_vidx
 }
 
 define void @insert_v2f64_vidx(double %a) nounwind {
-  ; MIPS32-LABEL: insert_v2f64_vidx:
+  ; ALL-LABEL: insert_v2f64_vidx:
 
-  %1 = load <2 x double>* @v2f64
-  ; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
-  ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
+  %1 = load <2 x double>, <2 x double>* @v2f64
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(
+  ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
-  %2 = load i32* @i32
-  ; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
-  ; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
+  %2 = load i32, i32* @i32
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %3 = insertelement <2 x double> %1, double %a, i32 %2
   ; double argument passed in $f12
-  ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3
-  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
-  ; MIPS32-DAG: insve.d [[R1]][0], $w12[0]
-  ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
-  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+  ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3
+  ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; ALL-DAG: insve.d [[R1]][0], $w12[0]
+  ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
 
   store <2 x double> %3, <2 x double>* @v2f64
-  ; MIPS32-DAG: st.d [[R1]]
+  ; ALL-DAG: st.d [[R1]]
 
   ret void
-  ; MIPS32: .size insert_v2f64_vidx
 }
diff --git a/test/CodeGen/Mips/msa/bit.ll b/test/CodeGen/Mips/msa/bit.ll
index 59ddbe17a33f..f0057307bbf7 100644
--- a/test/CodeGen/Mips/msa/bit.ll
+++ b/test/CodeGen/Mips/msa/bit.ll
@@ -8,7 +8,7 @@
 
 define void @llvm_mips_sat_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_sat_s_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sat_s_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.sat.s.b(<16 x i8> %0, i32 7)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_sat_s_b_RES
   ret void
@@ -27,7 +27,7 @@ declare <16 x i8> @llvm.mips.sat.s.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_sat_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_sat_s_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sat_s_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.sat.s.h(<8 x i16> %0, i32 7)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_sat_s_h_RES
   ret void
@@ -46,7 +46,7 @@ declare <8 x i16> @llvm.mips.sat.s.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_sat_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_sat_s_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sat_s_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.sat.s.w(<4 x i32> %0, i32 7)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_sat_s_w_RES
   ret void
@@ -65,7 +65,7 @@ declare <4 x i32> @llvm.mips.sat.s.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_sat_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_sat_s_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sat_s_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.sat.s.d(<2 x i64> %0, i32 7)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_sat_s_d_RES
   ret void
@@ -84,7 +84,7 @@ declare <2 x i64> @llvm.mips.sat.s.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_sat_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_sat_u_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sat_u_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.sat.u.b(<16 x i8> %0, i32 7)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_sat_u_b_RES
   ret void
@@ -103,7 +103,7 @@ declare <16 x i8> @llvm.mips.sat.u.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_sat_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_sat_u_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sat_u_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.sat.u.h(<8 x i16> %0, i32 7)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_sat_u_h_RES
   ret void
@@ -122,7 +122,7 @@ declare <8 x i16> @llvm.mips.sat.u.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_sat_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_sat_u_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sat_u_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.sat.u.w(<4 x i32> %0, i32 7)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_sat_u_w_RES
   ret void
@@ -141,7 +141,7 @@ declare <4 x i32> @llvm.mips.sat.u.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_sat_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_sat_u_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sat_u_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.sat.u.d(<2 x i64> %0, i32 7)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_sat_u_d_RES
   ret void
@@ -160,7 +160,7 @@ declare <2 x i64> @llvm.mips.sat.u.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_slli_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_slli_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_slli_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.slli.b(<16 x i8> %0, i32 7)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_slli_b_RES
   ret void
@@ -179,7 +179,7 @@ declare <16 x i8> @llvm.mips.slli.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_slli_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_slli_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_slli_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.slli.h(<8 x i16> %0, i32 7)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_slli_h_RES
   ret void
@@ -198,7 +198,7 @@ declare <8 x i16> @llvm.mips.slli.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_slli_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_slli_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_slli_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.slli.w(<4 x i32> %0, i32 7)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_slli_w_RES
   ret void
@@ -217,7 +217,7 @@ declare <4 x i32> @llvm.mips.slli.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_slli_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_slli_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_slli_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.slli.d(<2 x i64> %0, i32 7)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_slli_d_RES
   ret void
@@ -236,7 +236,7 @@ declare <2 x i64> @llvm.mips.slli.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_srai_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_srai_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_srai_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.srai.b(<16 x i8> %0, i32 7)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_srai_b_RES
   ret void
@@ -255,7 +255,7 @@ declare <16 x i8> @llvm.mips.srai.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_srai_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_srai_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_srai_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.srai.h(<8 x i16> %0, i32 7)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_srai_h_RES
   ret void
@@ -274,7 +274,7 @@ declare <8 x i16> @llvm.mips.srai.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_srai_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_srai_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_srai_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.srai.w(<4 x i32> %0, i32 7)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_srai_w_RES
   ret void
@@ -293,7 +293,7 @@ declare <4 x i32> @llvm.mips.srai.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_srai_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_srai_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_srai_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.srai.d(<2 x i64> %0, i32 7)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_srai_d_RES
   ret void
@@ -312,7 +312,7 @@ declare <2 x i64> @llvm.mips.srai.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_srari_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_srari_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_srari_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.srari.b(<16 x i8> %0, i32 7)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_srari_b_RES
   ret void
@@ -331,7 +331,7 @@ declare <16 x i8> @llvm.mips.srari.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_srari_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_srari_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_srari_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.srari.h(<8 x i16> %0, i32 7)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_srari_h_RES
   ret void
@@ -350,7 +350,7 @@ declare <8 x i16> @llvm.mips.srari.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_srari_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_srari_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_srari_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.srari.w(<4 x i32> %0, i32 7)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_srari_w_RES
   ret void
@@ -369,7 +369,7 @@ declare <4 x i32> @llvm.mips.srari.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_srari_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_srari_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_srari_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.srari.d(<2 x i64> %0, i32 7)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_srari_d_RES
   ret void
@@ -388,7 +388,7 @@ declare <2 x i64> @llvm.mips.srari.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_srli_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_srli_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_srli_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.srli.b(<16 x i8> %0, i32 7)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_srli_b_RES
   ret void
@@ -407,7 +407,7 @@ declare <16 x i8> @llvm.mips.srli.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_srli_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_srli_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_srli_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.srli.h(<8 x i16> %0, i32 7)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_srli_h_RES
   ret void
@@ -426,7 +426,7 @@ declare <8 x i16> @llvm.mips.srli.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_srli_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_srli_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_srli_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.srli.w(<4 x i32> %0, i32 7)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_srli_w_RES
   ret void
@@ -445,7 +445,7 @@ declare <4 x i32> @llvm.mips.srli.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_srli_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_srli_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_srli_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.srli.d(<2 x i64> %0, i32 7)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_srli_d_RES
   ret void
@@ -464,7 +464,7 @@ declare <2 x i64> @llvm.mips.srli.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_srlri_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_srlri_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_srlri_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.srlri.b(<16 x i8> %0, i32 7)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_srlri_b_RES
   ret void
@@ -483,7 +483,7 @@ declare <16 x i8> @llvm.mips.srlri.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_srlri_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_srlri_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_srlri_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.srlri.h(<8 x i16> %0, i32 7)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_srlri_h_RES
   ret void
@@ -502,7 +502,7 @@ declare <8 x i16> @llvm.mips.srlri.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_srlri_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_srlri_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_srlri_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.srlri.w(<4 x i32> %0, i32 7)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_srlri_w_RES
   ret void
@@ -521,7 +521,7 @@ declare <4 x i32> @llvm.mips.srlri.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_srlri_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_srlri_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_srlri_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.srlri.d(<2 x i64> %0, i32 7)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_srlri_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/bitcast.ll b/test/CodeGen/Mips/msa/bitcast.ll
index 8e880ecd9afb..837cc28aa82d 100644
--- a/test/CodeGen/Mips/msa/bitcast.ll
+++ b/test/CodeGen/Mips/msa/bitcast.ll
@@ -5,7 +5,7 @@
 
 define void @v16i8_to_v16i8(<16 x i8>* %src, <16 x i8>* %dst) nounwind {
 entry:
-  %0 = load volatile <16 x i8>* %src
+  %0 = load volatile <16 x i8>, <16 x i8>* %src
   %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)
   %2 = bitcast <16 x i8> %1 to <16 x i8>
   %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2)
@@ -29,7 +29,7 @@ entry:
 
 define void @v16i8_to_v8i16(<16 x i8>* %src, <8 x i16>* %dst) nounwind {
 entry:
-  %0 = load volatile <16 x i8>* %src
+  %0 = load volatile <16 x i8>, <16 x i8>* %src
   %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)
   %2 = bitcast <16 x i8> %1 to <8 x i16>
   %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2)
@@ -56,7 +56,7 @@ entry:
 ; are no operations for v8f16 to put in the way.
 define void @v16i8_to_v8f16(<16 x i8>* %src, <8 x half>* %dst) nounwind {
 entry:
-  %0 = load volatile <16 x i8>* %src
+  %0 = load volatile <16 x i8>, <16 x i8>* %src
   %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)
   %2 = bitcast <16 x i8> %1 to <8 x half>
   store <8 x half> %2, <8 x half>* %dst
@@ -77,7 +77,7 @@ entry:
 
 define void @v16i8_to_v4i32(<16 x i8>* %src, <4 x i32>* %dst) nounwind {
 entry:
-  %0 = load volatile <16 x i8>* %src
+  %0 = load volatile <16 x i8>, <16 x i8>* %src
   %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)
   %2 = bitcast <16 x i8> %1 to <4 x i32>
   %3 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %2, <4 x i32> %2)
@@ -102,7 +102,7 @@ entry:
 
 define void @v16i8_to_v4f32(<16 x i8>* %src, <4 x float>* %dst) nounwind {
 entry:
-  %0 = load volatile <16 x i8>* %src
+  %0 = load volatile <16 x i8>, <16 x i8>* %src
   %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)
   %2 = bitcast <16 x i8> %1 to <4 x float>
   %3 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %2, <4 x float> %2)
@@ -127,7 +127,7 @@ entry:
 
 define void @v16i8_to_v2i64(<16 x i8>* %src, <2 x i64>* %dst) nounwind {
 entry:
-  %0 = load volatile <16 x i8>* %src
+  %0 = load volatile <16 x i8>, <16 x i8>* %src
   %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)
   %2 = bitcast <16 x i8> %1 to <2 x i64>
   %3 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %2, <2 x i64> %2)
@@ -153,7 +153,7 @@ entry:
 
 define void @v16i8_to_v2f64(<16 x i8>* %src, <2 x double>* %dst) nounwind {
 entry:
-  %0 = load volatile <16 x i8>* %src
+  %0 = load volatile <16 x i8>, <16 x i8>* %src
   %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)
   %2 = bitcast <16 x i8> %1 to <2 x double>
   %3 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %2, <2 x double> %2)
@@ -179,7 +179,7 @@ entry:
 
 define void @v8i16_to_v16i8(<8 x i16>* %src, <16 x i8>* %dst) nounwind {
 entry:
-  %0 = load volatile <8 x i16>* %src
+  %0 = load volatile <8 x i16>, <8 x i16>* %src
   %1 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %0)
   %2 = bitcast <8 x i16> %1 to <16 x i8>
   %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2)
@@ -204,7 +204,7 @@ entry:
 
 define void @v8i16_to_v8i16(<8 x i16>* %src, <8 x i16>* %dst) nounwind {
 entry:
-  %0 = load volatile <8 x i16>* %src
+  %0 = load volatile <8 x i16>, <8 x i16>* %src
   %1 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %0)
   %2 = bitcast <8 x i16> %1 to <8 x i16>
   %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2)
@@ -230,7 +230,7 @@ entry:
 ; are no operations for v8f16 to put in the way.
 define void @v8i16_to_v8f16(<8 x i16>* %src, <8 x half>* %dst) nounwind {
 entry:
-  %0 = load volatile <8 x i16>* %src
+  %0 = load volatile <8 x i16>, <8 x i16>* %src
   %1 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %0)
   %2 = bitcast <8 x i16> %1 to <8 x half>
   store <8 x half> %2, <8 x half>* %dst
@@ -251,7 +251,7 @@ entry:
 
 define void @v8i16_to_v4i32(<8 x i16>* %src, <4 x i32>* %dst) nounwind {
 entry:
-  %0 = load volatile <8 x i16>* %src
+  %0 = load volatile <8 x i16>, <8 x i16>* %src
   %1 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %0)
   %2 = bitcast <8 x i16> %1 to <4 x i32>
   %3 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %2, <4 x i32> %2)
@@ -276,7 +276,7 @@ entry:
 
 define void @v8i16_to_v4f32(<8 x i16>* %src, <4 x float>* %dst) nounwind {
 entry:
-  %0 = load volatile <8 x i16>* %src
+  %0 = load volatile <8 x i16>, <8 x i16>* %src
   %1 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %0)
   %2 = bitcast <8 x i16> %1 to <4 x float>
   %3 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %2, <4 x float> %2)
@@ -301,7 +301,7 @@ entry:
 
 define void @v8i16_to_v2i64(<8 x i16>* %src, <2 x i64>* %dst) nounwind {
 entry:
-  %0 = load volatile <8 x i16>* %src
+  %0 = load volatile <8 x i16>, <8 x i16>* %src
   %1 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %0)
   %2 = bitcast <8 x i16> %1 to <2 x i64>
   %3 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %2, <2 x i64> %2)
@@ -326,7 +326,7 @@ entry:
 
 define void @v8i16_to_v2f64(<8 x i16>* %src, <2 x double>* %dst) nounwind {
 entry:
-  %0 = load volatile <8 x i16>* %src
+  %0 = load volatile <8 x i16>, <8 x i16>* %src
   %1 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %0)
   %2 = bitcast <8 x i16> %1 to <2 x double>
   %3 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %2, <2 x double> %2)
@@ -354,7 +354,7 @@ entry:
 ; are no operations for v8f16 to put in the way.
 define void @v8f16_to_v16i8(<8 x half>* %src, <16 x i8>* %dst) nounwind {
 entry:
-  %0 = load volatile <8 x half>* %src
+  %0 = load volatile <8 x half>, <8 x half>* %src
   %1 = bitcast <8 x half> %0 to <16 x i8>
   %2 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %1, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* %dst
@@ -378,7 +378,7 @@ entry:
 ; are no operations for v8f16 to put in the way.
 define void @v8f16_to_v8i16(<8 x half>* %src, <8 x i16>* %dst) nounwind {
 entry:
-  %0 = load volatile <8 x half>* %src
+  %0 = load volatile <8 x half>, <8 x half>* %src
   %1 = bitcast <8 x half> %0 to <8 x i16>
   %2 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %1, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* %dst
@@ -403,7 +403,7 @@ entry:
 ; are no operations for v8f16 to put in the way.
 define void @v8f16_to_v8f16(<8 x half>* %src, <8 x half>* %dst) nounwind {
 entry:
-  %0 = load volatile <8 x half>* %src
+  %0 = load volatile <8 x half>, <8 x half>* %src
   %1 = bitcast <8 x half> %0 to <8 x half>
   store <8 x half> %1, <8 x half>* %dst
   ret void
@@ -423,7 +423,7 @@ entry:
 ; are no operations for v8f16 to put in the way.
 define void @v8f16_to_v4i32(<8 x half>* %src, <4 x i32>* %dst) nounwind {
 entry:
-  %0 = load volatile <8 x half>* %src
+  %0 = load volatile <8 x half>, <8 x half>* %src
   %1 = bitcast <8 x half> %0 to <4 x i32>
   %2 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %1, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* %dst
@@ -447,7 +447,7 @@ entry:
 ; are no operations for v8f16 to put in the way.
 define void @v8f16_to_v4f32(<8 x half>* %src, <4 x float>* %dst) nounwind {
 entry:
-  %0 = load volatile <8 x half>* %src
+  %0 = load volatile <8 x half>, <8 x half>* %src
   %1 = bitcast <8 x half> %0 to <4 x float>
   %2 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %1, <4 x float> %1)
   store <4 x float> %2, <4 x float>* %dst
@@ -471,7 +471,7 @@ entry:
 ; are no operations for v8f16 to put in the way.
 define void @v8f16_to_v2i64(<8 x half>* %src, <2 x i64>* %dst) nounwind {
 entry:
-  %0 = load volatile <8 x half>* %src
+  %0 = load volatile <8 x half>, <8 x half>* %src
   %1 = bitcast <8 x half> %0 to <2 x i64>
   %2 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %1, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* %dst
@@ -495,7 +495,7 @@ entry:
 ; are no operations for v8f16 to put in the way.
 define void @v8f16_to_v2f64(<8 x half>* %src, <2 x double>* %dst) nounwind {
 entry:
-  %0 = load volatile <8 x half>* %src
+  %0 = load volatile <8 x half>, <8 x half>* %src
   %1 = bitcast <8 x half> %0 to <2 x double>
   %2 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %1, <2 x double> %1)
   store <2 x double> %2, <2 x double>* %dst
@@ -518,7 +518,7 @@ entry:
 
 define void @v4i32_to_v16i8(<4 x i32>* %src, <16 x i8>* %dst) nounwind {
 entry:
-  %0 = load volatile <4 x i32>* %src
+  %0 = load volatile <4 x i32>, <4 x i32>* %src
   %1 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %0)
   %2 = bitcast <4 x i32> %1 to <16 x i8>
   %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2)
@@ -543,7 +543,7 @@ entry:
 
 define void @v4i32_to_v8i16(<4 x i32>* %src, <8 x i16>* %dst) nounwind {
 entry:
-  %0 = load volatile <4 x i32>* %src
+  %0 = load volatile <4 x i32>, <4 x i32>* %src
   %1 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %0)
   %2 = bitcast <4 x i32> %1 to <8 x i16>
   %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2)
@@ -570,7 +570,7 @@ entry:
 ; are no operations for v8f16 to put in the way.
 define void @v4i32_to_v8f16(<4 x i32>* %src, <8 x half>* %dst) nounwind {
 entry:
-  %0 = load volatile <4 x i32>* %src
+  %0 = load volatile <4 x i32>, <4 x i32>* %src
   %1 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %0)
   %2 = bitcast <4 x i32> %1 to <8 x half>
   store <8 x half> %2, <8 x half>* %dst
@@ -591,7 +591,7 @@ entry:
 
 define void @v4i32_to_v4i32(<4 x i32>* %src, <4 x i32>* %dst) nounwind {
 entry:
-  %0 = load volatile <4 x i32>* %src
+  %0 = load volatile <4 x i32>, <4 x i32>* %src
   %1 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %0)
   %2 = bitcast <4 x i32> %1 to <4 x i32>
   %3 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %2, <4 x i32> %2)
@@ -615,7 +615,7 @@ entry:
 
 define void @v4i32_to_v4f32(<4 x i32>* %src, <4 x float>* %dst) nounwind {
 entry:
-  %0 = load volatile <4 x i32>* %src
+  %0 = load volatile <4 x i32>, <4 x i32>* %src
   %1 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %0)
   %2 = bitcast <4 x i32> %1 to <4 x float>
   %3 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %2, <4 x float> %2)
@@ -639,7 +639,7 @@ entry:
 
 define void @v4i32_to_v2i64(<4 x i32>* %src, <2 x i64>* %dst) nounwind {
 entry:
-  %0 = load volatile <4 x i32>* %src
+  %0 = load volatile <4 x i32>, <4 x i32>* %src
   %1 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %0)
   %2 = bitcast <4 x i32> %1 to <2 x i64>
   %3 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %2, <2 x i64> %2)
@@ -664,7 +664,7 @@ entry:
 
 define void @v4i32_to_v2f64(<4 x i32>* %src, <2 x double>* %dst) nounwind {
 entry:
-  %0 = load volatile <4 x i32>* %src
+  %0 = load volatile <4 x i32>, <4 x i32>* %src
   %1 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %0)
   %2 = bitcast <4 x i32> %1 to <2 x double>
   %3 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %2, <2 x double> %2)
@@ -689,7 +689,7 @@ entry:
 
 define void @v4f32_to_v16i8(<4 x float>* %src, <16 x i8>* %dst) nounwind {
 entry:
-  %0 = load volatile <4 x float>* %src
+  %0 = load volatile <4 x float>, <4 x float>* %src
   %1 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %0)
   %2 = bitcast <4 x float> %1 to <16 x i8>
   %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2)
@@ -714,7 +714,7 @@ entry:
 
 define void @v4f32_to_v8i16(<4 x float>* %src, <8 x i16>* %dst) nounwind {
 entry:
-  %0 = load volatile <4 x float>* %src
+  %0 = load volatile <4 x float>, <4 x float>* %src
   %1 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %0)
   %2 = bitcast <4 x float> %1 to <8 x i16>
   %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2)
@@ -741,7 +741,7 @@ entry:
 ; are no operations for v8f16 to put in the way.
 define void @v4f32_to_v8f16(<4 x float>* %src, <8 x half>* %dst) nounwind {
 entry:
-  %0 = load volatile <4 x float>* %src
+  %0 = load volatile <4 x float>, <4 x float>* %src
   %1 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %0)
   %2 = bitcast <4 x float> %1 to <8 x half>
   store <8 x half> %2, <8 x half>* %dst
@@ -762,7 +762,7 @@ entry:
 
 define void @v4f32_to_v4i32(<4 x float>* %src, <4 x i32>* %dst) nounwind {
 entry:
-  %0 = load volatile <4 x float>* %src
+  %0 = load volatile <4 x float>, <4 x float>* %src
   %1 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %0)
   %2 = bitcast <4 x float> %1 to <4 x i32>
   %3 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %2, <4 x i32> %2)
@@ -786,7 +786,7 @@ entry:
 
 define void @v4f32_to_v4f32(<4 x float>* %src, <4 x float>* %dst) nounwind {
 entry:
-  %0 = load volatile <4 x float>* %src
+  %0 = load volatile <4 x float>, <4 x float>* %src
   %1 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %0)
   %2 = bitcast <4 x float> %1 to <4 x float>
   %3 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %2, <4 x float> %2)
@@ -810,7 +810,7 @@ entry:
 
 define void @v4f32_to_v2i64(<4 x float>* %src, <2 x i64>* %dst) nounwind {
 entry:
-  %0 = load volatile <4 x float>* %src
+  %0 = load volatile <4 x float>, <4 x float>* %src
   %1 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %0)
   %2 = bitcast <4 x float> %1 to <2 x i64>
   %3 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %2, <2 x i64> %2)
@@ -835,7 +835,7 @@ entry:
 
 define void @v4f32_to_v2f64(<4 x float>* %src, <2 x double>* %dst) nounwind {
 entry:
-  %0 = load volatile <4 x float>* %src
+  %0 = load volatile <4 x float>, <4 x float>* %src
   %1 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %0)
   %2 = bitcast <4 x float> %1 to <2 x double>
   %3 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %2, <2 x double> %2)
@@ -860,7 +860,7 @@ entry:
 
 define void @v2i64_to_v16i8(<2 x i64>* %src, <16 x i8>* %dst) nounwind {
 entry:
-  %0 = load volatile <2 x i64>* %src
+  %0 = load volatile <2 x i64>, <2 x i64>* %src
   %1 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %0)
   %2 = bitcast <2 x i64> %1 to <16 x i8>
   %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2)
@@ -886,7 +886,7 @@ entry:
 
 define void @v2i64_to_v8i16(<2 x i64>* %src, <8 x i16>* %dst) nounwind {
 entry:
-  %0 = load volatile <2 x i64>* %src
+  %0 = load volatile <2 x i64>, <2 x i64>* %src
   %1 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %0)
   %2 = bitcast <2 x i64> %1 to <8 x i16>
   %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2)
@@ -913,7 +913,7 @@ entry:
 ; are no operations for v8f16 to put in the way.
 define void @v2i64_to_v8f16(<2 x i64>* %src, <8 x half>* %dst) nounwind {
 entry:
-  %0 = load volatile <2 x i64>* %src
+  %0 = load volatile <2 x i64>, <2 x i64>* %src
   %1 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %0)
   %2 = bitcast <2 x i64> %1 to <8 x half>
   store <8 x half> %2, <8 x half>* %dst
@@ -934,7 +934,7 @@ entry:
 
 define void @v2i64_to_v4i32(<2 x i64>* %src, <4 x i32>* %dst) nounwind {
 entry:
-  %0 = load volatile <2 x i64>* %src
+  %0 = load volatile <2 x i64>, <2 x i64>* %src
   %1 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %0)
   %2 = bitcast <2 x i64> %1 to <4 x i32>
   %3 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %2, <4 x i32> %2)
@@ -959,7 +959,7 @@ entry:
 
 define void @v2i64_to_v4f32(<2 x i64>* %src, <4 x float>* %dst) nounwind {
 entry:
-  %0 = load volatile <2 x i64>* %src
+  %0 = load volatile <2 x i64>, <2 x i64>* %src
   %1 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %0)
   %2 = bitcast <2 x i64> %1 to <4 x float>
   %3 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %2, <4 x float> %2)
@@ -984,7 +984,7 @@ entry:
 
 define void @v2i64_to_v2i64(<2 x i64>* %src, <2 x i64>* %dst) nounwind {
 entry:
-  %0 = load volatile <2 x i64>* %src
+  %0 = load volatile <2 x i64>, <2 x i64>* %src
   %1 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %0)
   %2 = bitcast <2 x i64> %1 to <2 x i64>
   %3 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %2, <2 x i64> %2)
@@ -1008,7 +1008,7 @@ entry:
 
 define void @v2i64_to_v2f64(<2 x i64>* %src, <2 x double>* %dst) nounwind {
 entry:
-  %0 = load volatile <2 x i64>* %src
+  %0 = load volatile <2 x i64>, <2 x i64>* %src
   %1 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %0)
   %2 = bitcast <2 x i64> %1 to <2 x double>
   %3 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %2, <2 x double> %2)
@@ -1032,7 +1032,7 @@ entry:
 
 define void @v2f64_to_v16i8(<2 x double>* %src, <16 x i8>* %dst) nounwind {
 entry:
-  %0 = load volatile <2 x double>* %src
+  %0 = load volatile <2 x double>, <2 x double>* %src
   %1 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %0)
   %2 = bitcast <2 x double> %1 to <16 x i8>
   %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2)
@@ -1058,7 +1058,7 @@ entry:
 
 define void @v2f64_to_v8i16(<2 x double>* %src, <8 x i16>* %dst) nounwind {
 entry:
-  %0 = load volatile <2 x double>* %src
+  %0 = load volatile <2 x double>, <2 x double>* %src
   %1 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %0)
   %2 = bitcast <2 x double> %1 to <8 x i16>
   %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2)
@@ -1085,7 +1085,7 @@ entry:
 ; are no operations for v8f16 to put in the way.
 define void @v2f64_to_v8f16(<2 x double>* %src, <8 x half>* %dst) nounwind {
 entry:
-  %0 = load volatile <2 x double>* %src
+  %0 = load volatile <2 x double>, <2 x double>* %src
   %1 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %0)
   %2 = bitcast <2 x double> %1 to <8 x half>
   store <8 x half> %2, <8 x half>* %dst
@@ -1106,7 +1106,7 @@ entry:
 
 define void @v2f64_to_v4i32(<2 x double>* %src, <4 x i32>* %dst) nounwind {
 entry:
-  %0 = load volatile <2 x double>* %src
+  %0 = load volatile <2 x double>, <2 x double>* %src
   %1 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %0)
   %2 = bitcast <2 x double> %1 to <4 x i32>
   %3 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %2, <4 x i32> %2)
@@ -1131,7 +1131,7 @@ entry:
 
 define void @v2f64_to_v4f32(<2 x double>* %src, <4 x float>* %dst) nounwind {
 entry:
-  %0 = load volatile <2 x double>* %src
+  %0 = load volatile <2 x double>, <2 x double>* %src
   %1 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %0)
   %2 = bitcast <2 x double> %1 to <4 x float>
   %3 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %2, <4 x float> %2)
@@ -1156,7 +1156,7 @@ entry:
 
 define void @v2f64_to_v2i64(<2 x double>* %src, <2 x i64>* %dst) nounwind {
 entry:
-  %0 = load volatile <2 x double>* %src
+  %0 = load volatile <2 x double>, <2 x double>* %src
   %1 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %0)
   %2 = bitcast <2 x double> %1 to <2 x i64>
   %3 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %2, <2 x i64> %2)
@@ -1180,7 +1180,7 @@ entry:
 
 define void @v2f64_to_v2f64(<2 x double>* %src, <2 x double>* %dst) nounwind {
 entry:
-  %0 = load volatile <2 x double>* %src
+  %0 = load volatile <2 x double>, <2 x double>* %src
   %1 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %0)
   %2 = bitcast <2 x double> %1 to <2 x double>
   %3 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %2, <2 x double> %2)
diff --git a/test/CodeGen/Mips/msa/bitwise.ll b/test/CodeGen/Mips/msa/bitwise.ll
index 5d57198a9355..2a260b2c5733 100644
--- a/test/CodeGen/Mips/msa/bitwise.ll
+++ b/test/CodeGen/Mips/msa/bitwise.ll
@@ -4,9 +4,9 @@
 define void @and_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: and_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = and <16 x i8> %1, %2
   ; CHECK-DAG: and.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -20,9 +20,9 @@ define void @and_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @and_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: and_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = and <8 x i16> %1, %2
   ; CHECK-DAG: and.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -36,9 +36,9 @@ define void @and_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @and_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: and_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = and <4 x i32> %1, %2
   ; CHECK-DAG: and.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -52,9 +52,9 @@ define void @and_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @and_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: and_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = and <2 x i64> %1, %2
   ; CHECK-DAG: and.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -68,7 +68,7 @@ define void @and_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @and_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: and_v16i8_i:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = and <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   ; CHECK-DAG: andi.b [[R4:\$w[0-9]+]], [[R1]], 1
@@ -82,7 +82,7 @@ define void @and_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @and_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: and_v8i16_i:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = and <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
@@ -97,7 +97,7 @@ define void @and_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @and_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: and_v4i32_i:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = and <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
@@ -112,7 +112,7 @@ define void @and_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @and_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: and_v2i64_i:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = and <2 x i64> %1, <i64 1, i64 1>
   ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
@@ -127,9 +127,9 @@ define void @and_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @or_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: or_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = or <16 x i8> %1, %2
   ; CHECK-DAG: or.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -143,9 +143,9 @@ define void @or_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @or_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: or_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = or <8 x i16> %1, %2
   ; CHECK-DAG: or.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -159,9 +159,9 @@ define void @or_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @or_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: or_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = or <4 x i32> %1, %2
   ; CHECK-DAG: or.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -175,9 +175,9 @@ define void @or_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @or_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: or_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = or <2 x i64> %1, %2
   ; CHECK-DAG: or.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -191,7 +191,7 @@ define void @or_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @or_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: or_v16i8_i:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = or <16 x i8> %1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ; CHECK-DAG: ori.b [[R4:\$w[0-9]+]], [[R1]], 3
@@ -205,7 +205,7 @@ define void @or_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @or_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: or_v8i16_i:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = or <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
   ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 3
@@ -220,7 +220,7 @@ define void @or_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @or_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: or_v4i32_i:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = or <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
   ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 3
@@ -235,7 +235,7 @@ define void @or_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @or_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: or_v2i64_i:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = or <2 x i64> %1, <i64 3, i64 3>
   ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 3
@@ -250,9 +250,9 @@ define void @or_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @nor_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: nor_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = or <16 x i8> %1, %2
   %4 = xor <16 x i8> %3, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
@@ -267,9 +267,9 @@ define void @nor_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @nor_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: nor_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = or <8 x i16> %1, %2
   %4 = xor <8 x i16> %3, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
@@ -284,9 +284,9 @@ define void @nor_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @nor_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: nor_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = or <4 x i32> %1, %2
   %4 = xor <4 x i32> %3, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -301,9 +301,9 @@ define void @nor_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @nor_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: nor_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = or <2 x i64> %1, %2
   %4 = xor <2 x i64> %3, <i64 -1, i64 -1>
@@ -318,7 +318,7 @@ define void @nor_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @nor_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: nor_v16i8_i:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = or <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %3 = xor <16 x i8> %2, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
@@ -333,7 +333,7 @@ define void @nor_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @nor_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: nor_v8i16_i:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = or <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %3 = xor <8 x i16> %2, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
@@ -349,7 +349,7 @@ define void @nor_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @nor_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: nor_v4i32_i:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = or <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   %3 = xor <4 x i32> %2, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -365,7 +365,7 @@ define void @nor_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @nor_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: nor_v2i64_i:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = or <2 x i64> %1, <i64 1, i64 1>
   %3 = xor <2 x i64> %2, <i64 -1, i64 -1>
@@ -381,9 +381,9 @@ define void @nor_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @xor_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: xor_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = xor <16 x i8> %1, %2
   ; CHECK-DAG: xor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -397,9 +397,9 @@ define void @xor_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @xor_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: xor_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = xor <8 x i16> %1, %2
   ; CHECK-DAG: xor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -413,9 +413,9 @@ define void @xor_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @xor_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: xor_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = xor <4 x i32> %1, %2
   ; CHECK-DAG: xor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -429,9 +429,9 @@ define void @xor_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @xor_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: xor_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = xor <2 x i64> %1, %2
   ; CHECK-DAG: xor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -445,7 +445,7 @@ define void @xor_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @xor_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: xor_v16i8_i:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = xor <16 x i8> %1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ; CHECK-DAG: xori.b [[R4:\$w[0-9]+]], [[R1]], 3
@@ -459,7 +459,7 @@ define void @xor_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @xor_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: xor_v8i16_i:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = xor <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
   ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 3
@@ -474,7 +474,7 @@ define void @xor_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @xor_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: xor_v4i32_i:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = xor <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
   ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 3
@@ -489,7 +489,7 @@ define void @xor_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @xor_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: xor_v2i64_i:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = xor <2 x i64> %1, <i64 3, i64 3>
   ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 3
@@ -504,9 +504,9 @@ define void @xor_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @sll_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: sll_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <16 x i8> %1, %2
   ; CHECK-DAG: sll.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -520,9 +520,9 @@ define void @sll_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @sll_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: sll_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <8 x i16> %1, %2
   ; CHECK-DAG: sll.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -536,9 +536,9 @@ define void @sll_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @sll_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: sll_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <4 x i32> %1, %2
   ; CHECK-DAG: sll.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -552,9 +552,9 @@ define void @sll_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @sll_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: sll_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <2 x i64> %1, %2
   ; CHECK-DAG: sll.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -568,7 +568,7 @@ define void @sll_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @sll_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: sll_v16i8_i:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = shl <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   ; CHECK-DAG: slli.b [[R4:\$w[0-9]+]], [[R1]], 1
@@ -582,7 +582,7 @@ define void @sll_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @sll_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: sll_v8i16_i:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = shl <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   ; CHECK-DAG: slli.h [[R4:\$w[0-9]+]], [[R1]], 1
@@ -596,7 +596,7 @@ define void @sll_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @sll_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: sll_v4i32_i:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = shl <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   ; CHECK-DAG: slli.w [[R4:\$w[0-9]+]], [[R1]], 1
@@ -610,7 +610,7 @@ define void @sll_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @sll_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: sll_v2i64_i:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = shl <2 x i64> %1, <i64 1, i64 1>
   ; CHECK-DAG: slli.d [[R4:\$w[0-9]+]], [[R1]], 1
@@ -624,9 +624,9 @@ define void @sll_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @sra_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: sra_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = ashr <16 x i8> %1, %2
   ; CHECK-DAG: sra.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -640,9 +640,9 @@ define void @sra_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @sra_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: sra_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = ashr <8 x i16> %1, %2
   ; CHECK-DAG: sra.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -656,9 +656,9 @@ define void @sra_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @sra_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: sra_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = ashr <4 x i32> %1, %2
   ; CHECK-DAG: sra.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -672,9 +672,9 @@ define void @sra_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @sra_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: sra_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = ashr <2 x i64> %1, %2
   ; CHECK-DAG: sra.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -688,7 +688,7 @@ define void @sra_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @sra_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: sra_v16i8_i:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = ashr <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   ; CHECK-DAG: srai.b [[R4:\$w[0-9]+]], [[R1]], 1
@@ -702,7 +702,7 @@ define void @sra_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @sra_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: sra_v8i16_i:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = ashr <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   ; CHECK-DAG: srai.h [[R4:\$w[0-9]+]], [[R1]], 1
@@ -716,7 +716,7 @@ define void @sra_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @sra_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: sra_v4i32_i:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = ashr <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   ; CHECK-DAG: srai.w [[R4:\$w[0-9]+]], [[R1]], 1
@@ -730,7 +730,7 @@ define void @sra_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @sra_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: sra_v2i64_i:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = ashr <2 x i64> %1, <i64 1, i64 1>
   ; CHECK-DAG: srai.d [[R4:\$w[0-9]+]], [[R1]], 1
@@ -744,9 +744,9 @@ define void @sra_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @srl_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: srl_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = lshr <16 x i8> %1, %2
   ; CHECK-DAG: srl.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -760,9 +760,9 @@ define void @srl_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @srl_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: srl_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = lshr <8 x i16> %1, %2
   ; CHECK-DAG: srl.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -776,9 +776,9 @@ define void @srl_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @srl_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: srl_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = lshr <4 x i32> %1, %2
   ; CHECK-DAG: srl.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -792,9 +792,9 @@ define void @srl_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @srl_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: srl_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = lshr <2 x i64> %1, %2
   ; CHECK-DAG: srl.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -808,7 +808,7 @@ define void @srl_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @srl_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: srl_v16i8_i:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = lshr <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   ; CHECK-DAG: srli.b [[R4:\$w[0-9]+]], [[R1]], 1
@@ -822,7 +822,7 @@ define void @srl_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @srl_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: srl_v8i16_i:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = lshr <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   ; CHECK-DAG: srli.h [[R4:\$w[0-9]+]], [[R1]], 1
@@ -836,7 +836,7 @@ define void @srl_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @srl_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: srl_v4i32_i:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = lshr <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   ; CHECK-DAG: srli.w [[R4:\$w[0-9]+]], [[R1]], 1
@@ -850,7 +850,7 @@ define void @srl_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @srl_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: srl_v2i64_i:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = lshr <2 x i64> %1, <i64 1, i64 1>
   ; CHECK-DAG: srli.d [[R4:\$w[0-9]+]], [[R1]], 1
@@ -864,7 +864,7 @@ define void @srl_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @ctpop_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: ctpop_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <16 x i8> @llvm.ctpop.v16i8 (<16 x i8> %1)
   ; CHECK-DAG: pcnt.b [[R3:\$w[0-9]+]], [[R1]]
@@ -878,7 +878,7 @@ define void @ctpop_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @ctpop_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: ctpop_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <8 x i16> @llvm.ctpop.v8i16 (<8 x i16> %1)
   ; CHECK-DAG: pcnt.h [[R3:\$w[0-9]+]], [[R1]]
@@ -892,7 +892,7 @@ define void @ctpop_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @ctpop_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: ctpop_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <4 x i32> @llvm.ctpop.v4i32 (<4 x i32> %1)
   ; CHECK-DAG: pcnt.w [[R3:\$w[0-9]+]], [[R1]]
@@ -906,7 +906,7 @@ define void @ctpop_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @ctpop_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: ctpop_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <2 x i64> @llvm.ctpop.v2i64 (<2 x i64> %1)
   ; CHECK-DAG: pcnt.d [[R3:\$w[0-9]+]], [[R1]]
@@ -920,7 +920,7 @@ define void @ctpop_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @ctlz_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: ctlz_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <16 x i8> @llvm.ctlz.v16i8 (<16 x i8> %1)
   ; CHECK-DAG: nlzc.b [[R3:\$w[0-9]+]], [[R1]]
@@ -934,7 +934,7 @@ define void @ctlz_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @ctlz_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: ctlz_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <8 x i16> @llvm.ctlz.v8i16 (<8 x i16> %1)
   ; CHECK-DAG: nlzc.h [[R3:\$w[0-9]+]], [[R1]]
@@ -948,7 +948,7 @@ define void @ctlz_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @ctlz_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: ctlz_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <4 x i32> @llvm.ctlz.v4i32 (<4 x i32> %1)
   ; CHECK-DAG: nlzc.w [[R3:\$w[0-9]+]], [[R1]]
@@ -962,7 +962,7 @@ define void @ctlz_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @ctlz_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: ctlz_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = tail call <2 x i64> @llvm.ctlz.v2i64 (<2 x i64> %1)
   ; CHECK-DAG: nlzc.d [[R3:\$w[0-9]+]], [[R1]]
@@ -976,11 +976,11 @@ define void @ctlz_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @bsel_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %m) nounwind {
   ; CHECK: bsel_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <16 x i8>* %m
+  %3 = load <16 x i8>, <16 x i8>* %m
   ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
   %4 = xor <16 x i8> %3, <i8 -1, i8 -1, i8 -1, i8 -1,
                           i8 -1, i8 -1, i8 -1, i8 -1,
@@ -1002,9 +1002,9 @@ define void @bsel_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b, <16 x i8>*
 define void @bsel_v16i8_i(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %m) nounwind {
   ; CHECK: bsel_v16i8_i:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %m
+  %2 = load <16 x i8>, <16 x i8>* %m
   ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($6)
   %3 = xor <16 x i8> %2, <i8 -1, i8 -1, i8 -1, i8 -1,
                           i8 -1, i8 -1, i8 -1, i8 -1,
@@ -1027,9 +1027,9 @@ define void @bsel_v16i8_i(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %m) nounwind
 define void @bsel_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: bsel_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = and <8 x i16> %1, <i16 6, i16 6, i16 6, i16 6,
                           i16 6, i16 6, i16 6, i16 6>
@@ -1048,9 +1048,9 @@ define void @bsel_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @bsel_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: bsel_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = and <4 x i32> %1, <i32 6, i32 6, i32 6, i32 6>
   %4 = and <4 x i32> %2, <i32 4294967289, i32 4294967289, i32 4294967289, i32 4294967289>
@@ -1067,9 +1067,9 @@ define void @bsel_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @bsel_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: bsel_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = and <2 x i64> %1, <i64 6, i64 6>
   %4 = and <2 x i64> %2, <i64 18446744073709551609, i64 18446744073709551609>
@@ -1086,9 +1086,9 @@ define void @bsel_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @binsl_v16i8_i(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: binsl_v16i8_i:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = and <16 x i8> %1, <i8 192, i8 192, i8 192, i8 192,
                           i8 192, i8 192, i8 192, i8 192,
@@ -1110,9 +1110,9 @@ define void @binsl_v16i8_i(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind
 define void @binsl_v8i16_i(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: binsl_v8i16_i:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = and <8 x i16> %1, <i16 49152, i16 49152, i16 49152, i16 49152,
                           i16 49152, i16 49152, i16 49152, i16 49152>
@@ -1130,9 +1130,9 @@ define void @binsl_v8i16_i(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind
 define void @binsl_v4i32_i(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: binsl_v4i32_i:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = and <4 x i32> %1, <i32 3221225472, i32 3221225472, i32 3221225472, i32 3221225472>
   %4 = and <4 x i32> %2, <i32 1073741823, i32 1073741823, i32 1073741823, i32 1073741823>
@@ -1148,9 +1148,9 @@ define void @binsl_v4i32_i(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind
 define void @binsl_v2i64_i(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: binsl_v2i64_i:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = and <2 x i64> %1, <i64 18446744073709551608, i64 18446744073709551608>
   %4 = and <2 x i64> %2, <i64 7, i64 7>
@@ -1170,9 +1170,9 @@ define void @binsl_v2i64_i(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
 define void @binsr_v16i8_i(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: binsr_v16i8_i:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = and <16 x i8> %1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3,
                           i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
@@ -1192,9 +1192,9 @@ define void @binsr_v16i8_i(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind
 define void @binsr_v8i16_i(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: binsr_v8i16_i:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = and <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3,
                           i16 3, i16 3, i16 3, i16 3>
@@ -1212,9 +1212,9 @@ define void @binsr_v8i16_i(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind
 define void @binsr_v4i32_i(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: binsr_v4i32_i:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = and <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
   %4 = and <4 x i32> %2, <i32 4294967292, i32 4294967292, i32 4294967292, i32 4294967292>
@@ -1230,9 +1230,9 @@ define void @binsr_v4i32_i(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind
 define void @binsr_v2i64_i(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: binsr_v2i64_i:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = and <2 x i64> %1, <i64 3, i64 3>
   %4 = and <2 x i64> %2, <i64 18446744073709551612, i64 18446744073709551612>
@@ -1248,9 +1248,9 @@ define void @binsr_v2i64_i(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
 define void @bclr_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: bclr_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, %2
   %4 = xor <16 x i8> %3, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
@@ -1266,9 +1266,9 @@ define void @bclr_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @bclr_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: bclr_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, %2
   %4 = xor <8 x i16> %3, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
@@ -1284,9 +1284,9 @@ define void @bclr_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @bclr_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: bclr_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %2
   %4 = xor <4 x i32> %3, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -1302,9 +1302,9 @@ define void @bclr_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @bclr_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: bclr_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <2 x i64> <i64 1, i64 1>, %2
   %4 = xor <2 x i64> %3, <i64 -1, i64 -1>
@@ -1320,9 +1320,9 @@ define void @bclr_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @bset_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: bset_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, %2
   %4 = or <16 x i8> %1, %3
@@ -1337,9 +1337,9 @@ define void @bset_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @bset_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: bset_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, %2
   %4 = or <8 x i16> %1, %3
@@ -1354,9 +1354,9 @@ define void @bset_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @bset_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: bset_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %2
   %4 = or <4 x i32> %1, %3
@@ -1371,9 +1371,9 @@ define void @bset_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @bset_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: bset_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <2 x i64> <i64 1, i64 1>, %2
   %4 = or <2 x i64> %1, %3
@@ -1388,9 +1388,9 @@ define void @bset_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @bneg_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: bneg_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, %2
   %4 = xor <16 x i8> %1, %3
@@ -1405,9 +1405,9 @@ define void @bneg_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @bneg_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: bneg_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, %2
   %4 = xor <8 x i16> %1, %3
@@ -1422,9 +1422,9 @@ define void @bneg_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @bneg_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: bneg_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %2
   %4 = xor <4 x i32> %1, %3
@@ -1439,9 +1439,9 @@ define void @bneg_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @bneg_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: bneg_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = shl <2 x i64> <i64 1, i64 1>, %2
   %4 = xor <2 x i64> %1, %3
@@ -1456,7 +1456,7 @@ define void @bneg_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @bclri_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: bclri_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = xor <16 x i8> <i8  8, i8  8, i8  8, i8  8, i8  8, i8  8, i8  8, i8  8, i8  8, i8  8, i8  8, i8  8, i8  8, i8  8, i8  8, i8  8>,
                      <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
@@ -1473,7 +1473,7 @@ define void @bclri_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @bclri_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: bclri_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = xor <8 x i16> <i16  8, i16  8, i16  8, i16  8, i16  8, i16  8, i16  8, i16  8>,
                      <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
@@ -1489,7 +1489,7 @@ define void @bclri_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @bclri_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: bclri_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = xor <4 x i32> <i32  8, i32  8, i32  8, i32  8>,
                      <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -1505,7 +1505,7 @@ define void @bclri_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @bclri_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: bclri_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = xor <2 x i64> <i64  8, i64  8>,
                      <i64 -1, i64 -1>
@@ -1521,7 +1521,7 @@ define void @bclri_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @bseti_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: bseti_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = or <16 x i8> %1, <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>
   ; CHECK-DAG: bseti.b [[R3:\$w[0-9]+]], [[R1]], 3
@@ -1535,7 +1535,7 @@ define void @bseti_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @bseti_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: bseti_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = or <8 x i16> %1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
   ; CHECK-DAG: bseti.h [[R3:\$w[0-9]+]], [[R1]], 3
@@ -1549,7 +1549,7 @@ define void @bseti_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @bseti_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: bseti_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = or <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>
   ; CHECK-DAG: bseti.w [[R3:\$w[0-9]+]], [[R1]], 3
@@ -1563,7 +1563,7 @@ define void @bseti_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @bseti_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: bseti_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = or <2 x i64> %1, <i64 8, i64 8>
   ; CHECK-DAG: bseti.d [[R3:\$w[0-9]+]], [[R1]], 3
@@ -1577,7 +1577,7 @@ define void @bseti_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @bnegi_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: bnegi_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = xor <16 x i8> %1, <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>
   ; CHECK-DAG: bnegi.b [[R3:\$w[0-9]+]], [[R1]], 3
@@ -1591,7 +1591,7 @@ define void @bnegi_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @bnegi_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: bnegi_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = xor <8 x i16> %1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
   ; CHECK-DAG: bnegi.h [[R3:\$w[0-9]+]], [[R1]], 3
@@ -1605,7 +1605,7 @@ define void @bnegi_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @bnegi_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: bnegi_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = xor <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>
   ; CHECK-DAG: bnegi.w [[R3:\$w[0-9]+]], [[R1]], 3
@@ -1619,7 +1619,7 @@ define void @bnegi_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @bnegi_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: bnegi_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = xor <2 x i64> %1, <i64 8, i64 8>
   ; CHECK-DAG: bnegi.d [[R3:\$w[0-9]+]], [[R1]], 3
diff --git a/test/CodeGen/Mips/msa/compare.ll b/test/CodeGen/Mips/msa/compare.ll
index 87ca1482da81..bc4f6e7e3946 100644
--- a/test/CodeGen/Mips/msa/compare.ll
+++ b/test/CodeGen/Mips/msa/compare.ll
@@ -4,9 +4,9 @@
 define void @ceq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: ceq_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp eq <16 x i8> %1, %2
   %4 = sext <16 x i1> %3 to <16 x i8>
@@ -21,9 +21,9 @@ define void @ceq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @ceq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: ceq_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp eq <8 x i16> %1, %2
   %4 = sext <8 x i1> %3 to <8 x i16>
@@ -38,9 +38,9 @@ define void @ceq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @ceq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: ceq_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp eq <4 x i32> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -55,9 +55,9 @@ define void @ceq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @ceq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: ceq_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp eq <2 x i64> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -72,9 +72,9 @@ define void @ceq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @cle_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: cle_s_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sle <16 x i8> %1, %2
   %4 = sext <16 x i1> %3 to <16 x i8>
@@ -89,9 +89,9 @@ define void @cle_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @cle_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: cle_s_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sle <8 x i16> %1, %2
   %4 = sext <8 x i1> %3 to <8 x i16>
@@ -106,9 +106,9 @@ define void @cle_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @cle_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: cle_s_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sle <4 x i32> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -123,9 +123,9 @@ define void @cle_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @cle_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: cle_s_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sle <2 x i64> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -140,9 +140,9 @@ define void @cle_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @cle_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: cle_u_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ule <16 x i8> %1, %2
   %4 = sext <16 x i1> %3 to <16 x i8>
@@ -157,9 +157,9 @@ define void @cle_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @cle_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: cle_u_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ule <8 x i16> %1, %2
   %4 = sext <8 x i1> %3 to <8 x i16>
@@ -174,9 +174,9 @@ define void @cle_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @cle_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: cle_u_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ule <4 x i32> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -191,9 +191,9 @@ define void @cle_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @cle_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: cle_u_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ule <2 x i64> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -208,9 +208,9 @@ define void @cle_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @clt_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: clt_s_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp slt <16 x i8> %1, %2
   %4 = sext <16 x i1> %3 to <16 x i8>
@@ -225,9 +225,9 @@ define void @clt_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @clt_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: clt_s_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp slt <8 x i16> %1, %2
   %4 = sext <8 x i1> %3 to <8 x i16>
@@ -242,9 +242,9 @@ define void @clt_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @clt_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: clt_s_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp slt <4 x i32> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -259,9 +259,9 @@ define void @clt_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @clt_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: clt_s_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp slt <2 x i64> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -276,9 +276,9 @@ define void @clt_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @clt_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: clt_u_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ult <16 x i8> %1, %2
   %4 = sext <16 x i1> %3 to <16 x i8>
@@ -293,9 +293,9 @@ define void @clt_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @clt_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: clt_u_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ult <8 x i16> %1, %2
   %4 = sext <8 x i1> %3 to <8 x i16>
@@ -310,9 +310,9 @@ define void @clt_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @clt_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: clt_u_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ult <4 x i32> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -327,9 +327,9 @@ define void @clt_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @clt_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: clt_u_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ult <2 x i64> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -345,9 +345,9 @@ define void @clt_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 ; issues in this area.
 define void @cne_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: cne_v16i8:
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ne <16 x i8> %1, %2
   %4 = sext <16 x i1> %3 to <16 x i8>
@@ -365,9 +365,9 @@ define void @cne_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @cne_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: cne_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ne <8 x i16> %1, %2
   %4 = sext <8 x i1> %3 to <8 x i16>
@@ -387,9 +387,9 @@ define void @cne_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @cne_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: cne_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ne <4 x i32> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -409,9 +409,9 @@ define void @cne_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @cne_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: cne_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ne <2 x i64> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -429,7 +429,7 @@ define void @cne_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @ceqi_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: ceqi_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp eq <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %3 = sext <16 x i1> %2 to <16 x i8>
@@ -444,7 +444,7 @@ define void @ceqi_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @ceqi_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: ceqi_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp eq <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %3 = sext <8 x i1> %2 to <8 x i16>
@@ -459,7 +459,7 @@ define void @ceqi_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @ceqi_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: ceqi_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp eq <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   %3 = sext <4 x i1> %2 to <4 x i32>
@@ -474,7 +474,7 @@ define void @ceqi_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @ceqi_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: ceqi_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp eq <2 x i64> %1, <i64 1, i64 1>
   %3 = sext <2 x i1> %2 to <2 x i64>
@@ -489,7 +489,7 @@ define void @ceqi_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @clei_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: clei_s_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sle <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %3 = sext <16 x i1> %2 to <16 x i8>
@@ -504,7 +504,7 @@ define void @clei_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @clei_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: clei_s_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sle <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %3 = sext <8 x i1> %2 to <8 x i16>
@@ -519,7 +519,7 @@ define void @clei_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @clei_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: clei_s_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sle <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   %3 = sext <4 x i1> %2 to <4 x i32>
@@ -534,7 +534,7 @@ define void @clei_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @clei_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: clei_s_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sle <2 x i64> %1, <i64 1, i64 1>
   %3 = sext <2 x i1> %2 to <2 x i64>
@@ -549,7 +549,7 @@ define void @clei_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @clei_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: clei_u_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ule <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %3 = sext <16 x i1> %2 to <16 x i8>
@@ -564,7 +564,7 @@ define void @clei_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @clei_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: clei_u_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ule <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %3 = sext <8 x i1> %2 to <8 x i16>
@@ -579,7 +579,7 @@ define void @clei_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @clei_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: clei_u_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ule <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   %3 = sext <4 x i1> %2 to <4 x i32>
@@ -594,7 +594,7 @@ define void @clei_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @clei_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: clei_u_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ule <2 x i64> %1, <i64 1, i64 1>
   %3 = sext <2 x i1> %2 to <2 x i64>
@@ -609,7 +609,7 @@ define void @clei_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @clti_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: clti_s_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp slt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %3 = sext <16 x i1> %2 to <16 x i8>
@@ -624,7 +624,7 @@ define void @clti_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @clti_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: clti_s_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp slt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %3 = sext <8 x i1> %2 to <8 x i16>
@@ -639,7 +639,7 @@ define void @clti_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @clti_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: clti_s_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp slt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   %3 = sext <4 x i1> %2 to <4 x i32>
@@ -654,7 +654,7 @@ define void @clti_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @clti_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: clti_s_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp slt <2 x i64> %1, <i64 1, i64 1>
   %3 = sext <2 x i1> %2 to <2 x i64>
@@ -669,7 +669,7 @@ define void @clti_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @clti_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: clti_u_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ult <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %3 = sext <16 x i1> %2 to <16 x i8>
@@ -684,7 +684,7 @@ define void @clti_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @clti_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: clti_u_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ult <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %3 = sext <8 x i1> %2 to <8 x i16>
@@ -699,7 +699,7 @@ define void @clti_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @clti_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: clti_u_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ult <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   %3 = sext <4 x i1> %2 to <4 x i32>
@@ -714,7 +714,7 @@ define void @clti_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @clti_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: clti_u_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ult <2 x i64> %1, <i64 1, i64 1>
   %3 = sext <2 x i1> %2 to <2 x i64>
@@ -730,11 +730,11 @@ define void @bsel_s_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
                         <16 x i8>* %c) nounwind {
   ; CHECK: bsel_s_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <16 x i8>* %c
+  %3 = load <16 x i8>, <16 x i8>* %c
   ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
   %4 = icmp sgt <16 x i8> %1, %2
   ; CHECK-DAG: clt_s.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -752,11 +752,11 @@ define void @bsel_s_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
                         <8 x i16>* %c) nounwind {
   ; CHECK: bsel_s_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <8 x i16>* %c
+  %3 = load <8 x i16>, <8 x i16>* %c
   ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
   %4 = icmp sgt <8 x i16> %1, %2
   ; CHECK-DAG: clt_s.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -774,11 +774,11 @@ define void @bsel_s_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
                         <4 x i32>* %c) nounwind {
   ; CHECK: bsel_s_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <4 x i32>* %c
+  %3 = load <4 x i32>, <4 x i32>* %c
   ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
   %4 = icmp sgt <4 x i32> %1, %2
   ; CHECK-DAG: clt_s.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -796,11 +796,11 @@ define void @bsel_s_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
                         <2 x i64>* %c) nounwind {
   ; CHECK: bsel_s_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <2 x i64>* %c
+  %3 = load <2 x i64>, <2 x i64>* %c
   ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
   %4 = icmp sgt <2 x i64> %1, %2
   ; CHECK-DAG: clt_s.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -818,11 +818,11 @@ define void @bsel_u_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
                         <16 x i8>* %c) nounwind {
   ; CHECK: bsel_u_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <16 x i8>* %c
+  %3 = load <16 x i8>, <16 x i8>* %c
   ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
   %4 = icmp ugt <16 x i8> %1, %2
   ; CHECK-DAG: clt_u.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -840,11 +840,11 @@ define void @bsel_u_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
                         <8 x i16>* %c) nounwind {
   ; CHECK: bsel_u_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <8 x i16>* %c
+  %3 = load <8 x i16>, <8 x i16>* %c
   ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
   %4 = icmp ugt <8 x i16> %1, %2
   ; CHECK-DAG: clt_u.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -862,11 +862,11 @@ define void @bsel_u_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
                         <4 x i32>* %c) nounwind {
   ; CHECK: bsel_u_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <4 x i32>* %c
+  %3 = load <4 x i32>, <4 x i32>* %c
   ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
   %4 = icmp ugt <4 x i32> %1, %2
   ; CHECK-DAG: clt_u.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -884,11 +884,11 @@ define void @bsel_u_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
                         <2 x i64>* %c) nounwind {
   ; CHECK: bsel_u_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <2 x i64>* %c
+  %3 = load <2 x i64>, <2 x i64>* %c
   ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
   %4 = icmp ugt <2 x i64> %1, %2
   ; CHECK-DAG: clt_u.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -906,9 +906,9 @@ define void @bseli_s_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
                         <16 x i8>* %c) nounwind {
   ; CHECK: bseli_s_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sgt <16 x i8> %1, %2
   ; CHECK-DAG: clt_s.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -925,9 +925,9 @@ define void @bseli_s_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
                         <8 x i16>* %c) nounwind {
   ; CHECK: bseli_s_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sgt <8 x i16> %1, %2
   ; CHECK-DAG: clt_s.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -945,9 +945,9 @@ define void @bseli_s_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
                         <4 x i32>* %c) nounwind {
   ; CHECK: bseli_s_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sgt <4 x i32> %1, %2
   ; CHECK-DAG: clt_s.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -965,9 +965,9 @@ define void @bseli_s_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
                         <2 x i64>* %c) nounwind {
   ; CHECK: bseli_s_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sgt <2 x i64> %1, %2
   ; CHECK-DAG: clt_s.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -985,9 +985,9 @@ define void @bseli_u_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
                         <16 x i8>* %c) nounwind {
   ; CHECK: bseli_u_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ugt <16 x i8> %1, %2
   ; CHECK-DAG: clt_u.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -1004,9 +1004,9 @@ define void @bseli_u_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
                         <8 x i16>* %c) nounwind {
   ; CHECK: bseli_u_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ugt <8 x i16> %1, %2
   ; CHECK-DAG: clt_u.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -1024,9 +1024,9 @@ define void @bseli_u_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
                         <4 x i32>* %c) nounwind {
   ; CHECK: bseli_u_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ugt <4 x i32> %1, %2
   ; CHECK-DAG: clt_u.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -1044,9 +1044,9 @@ define void @bseli_u_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
                         <2 x i64>* %c) nounwind {
   ; CHECK: bseli_u_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ugt <2 x i64> %1, %2
   ; CHECK-DAG: clt_u.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -1063,9 +1063,9 @@ define void @bseli_u_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
 define void @max_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: max_s_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sgt <16 x i8> %1, %2
   %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
@@ -1080,9 +1080,9 @@ define void @max_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @max_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: max_s_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sgt <8 x i16> %1, %2
   %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
@@ -1097,9 +1097,9 @@ define void @max_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @max_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: max_s_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sgt <4 x i32> %1, %2
   %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
@@ -1114,9 +1114,9 @@ define void @max_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @max_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: max_s_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sgt <2 x i64> %1, %2
   %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
@@ -1131,9 +1131,9 @@ define void @max_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @max_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: max_u_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ugt <16 x i8> %1, %2
   %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
@@ -1148,9 +1148,9 @@ define void @max_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @max_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: max_u_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ugt <8 x i16> %1, %2
   %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
@@ -1165,9 +1165,9 @@ define void @max_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @max_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: max_u_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ugt <4 x i32> %1, %2
   %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
@@ -1182,9 +1182,9 @@ define void @max_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @max_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: max_u_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ugt <2 x i64> %1, %2
   %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
@@ -1199,9 +1199,9 @@ define void @max_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @max_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: max_s_eq_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sge <16 x i8> %1, %2
   %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
@@ -1216,9 +1216,9 @@ define void @max_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwin
 define void @max_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: max_s_eq_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sge <8 x i16> %1, %2
   %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
@@ -1233,9 +1233,9 @@ define void @max_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwin
 define void @max_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: max_s_eq_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sge <4 x i32> %1, %2
   %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
@@ -1250,9 +1250,9 @@ define void @max_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwin
 define void @max_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: max_s_eq_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sge <2 x i64> %1, %2
   %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
@@ -1267,9 +1267,9 @@ define void @max_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwin
 define void @max_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: max_u_eq_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp uge <16 x i8> %1, %2
   %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
@@ -1284,9 +1284,9 @@ define void @max_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwin
 define void @max_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: max_u_eq_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp uge <8 x i16> %1, %2
   %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
@@ -1301,9 +1301,9 @@ define void @max_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwin
 define void @max_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: max_u_eq_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp uge <4 x i32> %1, %2
   %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
@@ -1318,9 +1318,9 @@ define void @max_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwin
 define void @max_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: max_u_eq_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp uge <2 x i64> %1, %2
   %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
@@ -1335,7 +1335,7 @@ define void @max_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwin
 define void @maxi_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: maxi_s_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sgt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -1350,7 +1350,7 @@ define void @maxi_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @maxi_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: maxi_s_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sgt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1365,7 +1365,7 @@ define void @maxi_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @maxi_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: maxi_s_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sgt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -1380,7 +1380,7 @@ define void @maxi_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @maxi_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: maxi_s_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sgt <2 x i64> %1, <i64 1, i64 1>
   %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
@@ -1395,7 +1395,7 @@ define void @maxi_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @maxi_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: maxi_u_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ugt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -1410,7 +1410,7 @@ define void @maxi_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @maxi_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: maxi_u_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ugt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1425,7 +1425,7 @@ define void @maxi_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @maxi_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: maxi_u_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ugt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -1440,7 +1440,7 @@ define void @maxi_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @maxi_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: maxi_u_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ugt <2 x i64> %1, <i64 1, i64 1>
   %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
@@ -1455,7 +1455,7 @@ define void @maxi_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @maxi_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: maxi_s_eq_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sge <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -1470,7 +1470,7 @@ define void @maxi_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @maxi_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: maxi_s_eq_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sge <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1485,7 +1485,7 @@ define void @maxi_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @maxi_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: maxi_s_eq_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sge <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -1500,7 +1500,7 @@ define void @maxi_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @maxi_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: maxi_s_eq_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sge <2 x i64> %1, <i64 1, i64 1>
   %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
@@ -1515,7 +1515,7 @@ define void @maxi_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @maxi_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: maxi_u_eq_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp uge <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -1530,7 +1530,7 @@ define void @maxi_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @maxi_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: maxi_u_eq_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp uge <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1545,7 +1545,7 @@ define void @maxi_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @maxi_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: maxi_u_eq_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp uge <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -1560,7 +1560,7 @@ define void @maxi_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @maxi_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: maxi_u_eq_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp uge <2 x i64> %1, <i64 1, i64 1>
   %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
@@ -1575,9 +1575,9 @@ define void @maxi_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @min_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: min_s_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sle <16 x i8> %1, %2
   %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
@@ -1592,9 +1592,9 @@ define void @min_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @min_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: min_s_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp slt <8 x i16> %1, %2
   %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
@@ -1609,9 +1609,9 @@ define void @min_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @min_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: min_s_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp slt <4 x i32> %1, %2
   %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
@@ -1626,9 +1626,9 @@ define void @min_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @min_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: min_s_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp slt <2 x i64> %1, %2
   %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
@@ -1643,9 +1643,9 @@ define void @min_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @min_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: min_u_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ult <16 x i8> %1, %2
   %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
@@ -1660,9 +1660,9 @@ define void @min_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
 define void @min_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: min_u_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ult <8 x i16> %1, %2
   %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
@@ -1677,9 +1677,9 @@ define void @min_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
 define void @min_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: min_u_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ult <4 x i32> %1, %2
   %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
@@ -1694,9 +1694,9 @@ define void @min_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
 define void @min_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: min_u_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ult <2 x i64> %1, %2
   %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
@@ -1711,9 +1711,9 @@ define void @min_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
 define void @min_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: min_s_eq_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sle <16 x i8> %1, %2
   %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
@@ -1728,9 +1728,9 @@ define void @min_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwin
 define void @min_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: min_s_eq_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sle <8 x i16> %1, %2
   %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
@@ -1745,9 +1745,9 @@ define void @min_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwin
 define void @min_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: min_s_eq_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sle <4 x i32> %1, %2
   %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
@@ -1762,9 +1762,9 @@ define void @min_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwin
 define void @min_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: min_s_eq_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp sle <2 x i64> %1, %2
   %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
@@ -1779,9 +1779,9 @@ define void @min_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwin
 define void @min_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: min_u_eq_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ule <16 x i8> %1, %2
   %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
@@ -1796,9 +1796,9 @@ define void @min_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwin
 define void @min_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK: min_u_eq_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ule <8 x i16> %1, %2
   %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
@@ -1813,9 +1813,9 @@ define void @min_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwin
 define void @min_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK: min_u_eq_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ule <4 x i32> %1, %2
   %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
@@ -1830,9 +1830,9 @@ define void @min_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwin
 define void @min_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
   ; CHECK: min_u_eq_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = icmp ule <2 x i64> %1, %2
   %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
@@ -1847,7 +1847,7 @@ define void @min_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwin
 define void @mini_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: mini_s_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp slt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -1862,7 +1862,7 @@ define void @mini_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @mini_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: mini_s_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp slt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1877,7 +1877,7 @@ define void @mini_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @mini_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: mini_s_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp slt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -1892,7 +1892,7 @@ define void @mini_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @mini_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: mini_s_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp slt <2 x i64> %1, <i64 1, i64 1>
   %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
@@ -1907,7 +1907,7 @@ define void @mini_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @mini_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: mini_u_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ult <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -1922,7 +1922,7 @@ define void @mini_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @mini_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: mini_u_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ult <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1937,7 +1937,7 @@ define void @mini_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @mini_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: mini_u_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ult <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -1952,7 +1952,7 @@ define void @mini_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @mini_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: mini_u_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ult <2 x i64> %1, <i64 1, i64 1>
   %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
@@ -1967,7 +1967,7 @@ define void @mini_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @mini_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: mini_s_eq_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sle <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -1982,7 +1982,7 @@ define void @mini_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @mini_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: mini_s_eq_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sle <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1997,7 +1997,7 @@ define void @mini_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @mini_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: mini_s_eq_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sle <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -2012,7 +2012,7 @@ define void @mini_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @mini_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: mini_s_eq_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp sle <2 x i64> %1, <i64 1, i64 1>
   %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
@@ -2027,7 +2027,7 @@ define void @mini_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 define void @mini_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK: mini_u_eq_v16i8:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ule <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -2042,7 +2042,7 @@ define void @mini_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 define void @mini_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK: mini_u_eq_v8i16:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ule <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -2057,7 +2057,7 @@ define void @mini_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 define void @mini_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
   ; CHECK: mini_u_eq_v4i32:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ule <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
   %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -2072,7 +2072,7 @@ define void @mini_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 define void @mini_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK: mini_u_eq_v2i64:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = icmp ule <2 x i64> %1, <i64 1, i64 1>
   %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
diff --git a/test/CodeGen/Mips/msa/compare_float.ll b/test/CodeGen/Mips/msa/compare_float.ll
index e93221b93612..3229d027d95d 100644
--- a/test/CodeGen/Mips/msa/compare_float.ll
+++ b/test/CodeGen/Mips/msa/compare_float.ll
@@ -9,8 +9,8 @@ declare <2 x double> @llvm.mips.fmin.d(<2 x double>, <2 x double>) nounwind
 define void @false_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: false_v4f32:
 
-  %1 = load <4 x float>* %a
-  %2 = load <4 x float>* %b
+  %1 = load <4 x float>, <4 x float>* %a
+  %2 = load <4 x float>, <4 x float>* %b
   %3 = fcmp false <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
   store <4 x i32> %4, <4 x i32>* %c
@@ -25,8 +25,8 @@ define void @false_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwi
 define void @false_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: false_v2f64:
 
-  %1 = load <2 x double>* %a
-  %2 = load <2 x double>* %b
+  %1 = load <2 x double>, <2 x double>* %a
+  %2 = load <2 x double>, <2 x double>* %b
   %3 = fcmp false <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
   store <2 x i64> %4, <2 x i64>* %c
@@ -41,9 +41,9 @@ define void @false_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) noun
 define void @oeq_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: oeq_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp oeq <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -58,9 +58,9 @@ define void @oeq_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind
 define void @oeq_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: oeq_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp oeq <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -75,9 +75,9 @@ define void @oeq_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwi
 define void @oge_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: oge_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp oge <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -92,9 +92,9 @@ define void @oge_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind
 define void @oge_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: oge_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp oge <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -109,9 +109,9 @@ define void @oge_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwi
 define void @ogt_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: ogt_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ogt <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -126,9 +126,9 @@ define void @ogt_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind
 define void @ogt_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: ogt_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ogt <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -143,9 +143,9 @@ define void @ogt_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwi
 define void @ole_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: ole_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ole <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -160,9 +160,9 @@ define void @ole_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind
 define void @ole_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: ole_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ole <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -177,9 +177,9 @@ define void @ole_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwi
 define void @olt_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: olt_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp olt <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -194,9 +194,9 @@ define void @olt_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind
 define void @olt_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: olt_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp olt <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -211,9 +211,9 @@ define void @olt_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwi
 define void @one_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: one_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp one <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -228,9 +228,9 @@ define void @one_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind
 define void @one_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: one_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp one <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -245,9 +245,9 @@ define void @one_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwi
 define void @ord_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: ord_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ord <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -262,9 +262,9 @@ define void @ord_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind
 define void @ord_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: ord_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ord <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -279,9 +279,9 @@ define void @ord_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwi
 define void @ueq_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: ueq_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ueq <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -296,9 +296,9 @@ define void @ueq_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind
 define void @ueq_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: ueq_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ueq <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -313,9 +313,9 @@ define void @ueq_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwi
 define void @uge_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: uge_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp uge <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -330,9 +330,9 @@ define void @uge_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind
 define void @uge_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: uge_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp uge <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -347,9 +347,9 @@ define void @uge_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwi
 define void @ugt_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: ugt_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ugt <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -364,9 +364,9 @@ define void @ugt_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind
 define void @ugt_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: ugt_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ugt <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -381,9 +381,9 @@ define void @ugt_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwi
 define void @ule_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: ule_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ule <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -398,9 +398,9 @@ define void @ule_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind
 define void @ule_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: ule_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ule <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -415,9 +415,9 @@ define void @ule_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwi
 define void @ult_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: ult_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ult <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -432,9 +432,9 @@ define void @ult_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind
 define void @ult_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: ult_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ult <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -449,9 +449,9 @@ define void @ult_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwi
 define void @uno_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: uno_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp uno <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
@@ -466,9 +466,9 @@ define void @uno_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind
 define void @uno_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: uno_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp uno <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
@@ -483,8 +483,8 @@ define void @uno_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwi
 define void @true_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: true_v4f32:
 
-  %1 = load <4 x float>* %a
-  %2 = load <4 x float>* %b
+  %1 = load <4 x float>, <4 x float>* %a
+  %2 = load <4 x float>, <4 x float>* %b
   %3 = fcmp true <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
   store <4 x i32> %4, <4 x i32>* %c
@@ -499,8 +499,8 @@ define void @true_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwin
 define void @true_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: true_v2f64:
 
-  %1 = load <2 x double>* %a
-  %2 = load <2 x double>* %b
+  %1 = load <2 x double>, <2 x double>* %a
+  %2 = load <2 x double>, <2 x double>* %b
   %3 = fcmp true <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
   store <2 x i64> %4, <2 x i64>* %c
@@ -516,11 +516,11 @@ define void @bsel_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b,
                           <4 x float>* %c) nounwind {
   ; CHECK: bsel_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <4 x float>* %c
+  %3 = load <4 x float>, <4 x float>* %c
   ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
   %4 = fcmp ogt <4 x float> %1, %2
   ; CHECK-DAG: fclt.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -538,11 +538,11 @@ define void @bsel_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b,
                           <2 x double>* %c) nounwind {
   ; CHECK: bsel_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
-  %3 = load <2 x double>* %c
+  %3 = load <2 x double>, <2 x double>* %c
   ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
   %4 = fcmp ogt <2 x double> %1, %2
   ; CHECK-DAG: fclt.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -560,9 +560,9 @@ define void @bseli_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b,
                           <4 x float>* %c) nounwind {
   ; CHECK: bseli_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ogt <4 x float> %1, %2
   ; CHECK-DAG: fclt.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -580,9 +580,9 @@ define void @bseli_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b,
                           <2 x double>* %c) nounwind {
   ; CHECK: bseli_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = fcmp ogt <2 x double> %1, %2
   ; CHECK-DAG: fclt.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
@@ -599,9 +599,9 @@ define void @bseli_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b,
 define void @max_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: max_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = tail call <4 x float> @llvm.mips.fmax.w(<4 x float> %1, <4 x float> %2)
   ; CHECK-DAG: fmax.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -615,9 +615,9 @@ define void @max_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwi
 define void @max_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: max_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = tail call <2 x double> @llvm.mips.fmax.d(<2 x double> %1, <2 x double> %2)
   ; CHECK-DAG: fmax.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -631,9 +631,9 @@ define void @max_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nou
 define void @min_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
   ; CHECK: min_v4f32:
 
-  %1 = load <4 x float>* %a
+  %1 = load <4 x float>, <4 x float>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x float>* %b
+  %2 = load <4 x float>, <4 x float>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = tail call <4 x float> @llvm.mips.fmin.w(<4 x float> %1, <4 x float> %2)
   ; CHECK-DAG: fmin.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -647,9 +647,9 @@ define void @min_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwi
 define void @min_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
   ; CHECK: min_v2f64:
 
-  %1 = load <2 x double>* %a
+  %1 = load <2 x double>, <2 x double>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x double>* %b
+  %2 = load <2 x double>, <2 x double>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = tail call <2 x double> @llvm.mips.fmin.d(<2 x double> %1, <2 x double> %2)
   ; CHECK-DAG: fmin.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
diff --git a/test/CodeGen/Mips/msa/elm_copy.ll b/test/CodeGen/Mips/msa/elm_copy.ll
index 0dd75fa3db12..2a0d74f44524 100644
--- a/test/CodeGen/Mips/msa/elm_copy.ll
+++ b/test/CodeGen/Mips/msa/elm_copy.ll
@@ -15,7 +15,7 @@
 
 define void @llvm_mips_copy_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_copy_s_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_copy_s_b_ARG1
   %1 = tail call i32 @llvm.mips.copy.s.b(<16 x i8> %0, i32 1)
   store i32 %1, i32* @llvm_mips_copy_s_b_RES
   ret void
@@ -38,7 +38,7 @@ declare i32 @llvm.mips.copy.s.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_copy_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_copy_s_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_copy_s_h_ARG1
   %1 = tail call i32 @llvm.mips.copy.s.h(<8 x i16> %0, i32 1)
   store i32 %1, i32* @llvm_mips_copy_s_h_RES
   ret void
@@ -61,7 +61,7 @@ declare i32 @llvm.mips.copy.s.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_copy_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_copy_s_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_copy_s_w_ARG1
   %1 = tail call i32 @llvm.mips.copy.s.w(<4 x i32> %0, i32 1)
   store i32 %1, i32* @llvm_mips_copy_s_w_RES
   ret void
@@ -84,7 +84,7 @@ declare i32 @llvm.mips.copy.s.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_copy_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_copy_s_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_copy_s_d_ARG1
   %1 = tail call i64 @llvm.mips.copy.s.d(<2 x i64> %0, i32 1)
   store i64 %1, i64* @llvm_mips_copy_s_d_RES
   ret void
@@ -112,7 +112,7 @@ declare i64 @llvm.mips.copy.s.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_copy_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_copy_u_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_copy_u_b_ARG1
   %1 = tail call i32 @llvm.mips.copy.u.b(<16 x i8> %0, i32 1)
   store i32 %1, i32* @llvm_mips_copy_u_b_RES
   ret void
@@ -135,7 +135,7 @@ declare i32 @llvm.mips.copy.u.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_copy_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_copy_u_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_copy_u_h_ARG1
   %1 = tail call i32 @llvm.mips.copy.u.h(<8 x i16> %0, i32 1)
   store i32 %1, i32* @llvm_mips_copy_u_h_RES
   ret void
@@ -158,7 +158,7 @@ declare i32 @llvm.mips.copy.u.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_copy_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_copy_u_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_copy_u_w_ARG1
   %1 = tail call i32 @llvm.mips.copy.u.w(<4 x i32> %0, i32 1)
   store i32 %1, i32* @llvm_mips_copy_u_w_RES
   ret void
@@ -181,7 +181,7 @@ declare i32 @llvm.mips.copy.u.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_copy_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_copy_u_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_copy_u_d_ARG1
   %1 = tail call i64 @llvm.mips.copy.u.d(<2 x i64> %0, i32 1)
   store i64 %1, i64* @llvm_mips_copy_u_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/elm_insv.ll b/test/CodeGen/Mips/msa/elm_insv.ll
index c746e523def6..46e6289189df 100644
--- a/test/CodeGen/Mips/msa/elm_insv.ll
+++ b/test/CodeGen/Mips/msa/elm_insv.ll
@@ -16,8 +16,8 @@
 
 define void @llvm_mips_insert_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_insert_b_ARG1
-  %1 = load i32* @llvm_mips_insert_b_ARG3
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_insert_b_ARG1
+  %1 = load i32, i32* @llvm_mips_insert_b_ARG3
   %2 = tail call <16 x i8> @llvm.mips.insert.b(<16 x i8> %0, i32 1, i32 %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_insert_b_RES
   ret void
@@ -38,8 +38,8 @@ declare <16 x i8> @llvm.mips.insert.b(<16 x i8>, i32, i32) nounwind
 
 define void @llvm_mips_insert_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_insert_h_ARG1
-  %1 = load i32* @llvm_mips_insert_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_insert_h_ARG1
+  %1 = load i32, i32* @llvm_mips_insert_h_ARG3
   %2 = tail call <8 x i16> @llvm.mips.insert.h(<8 x i16> %0, i32 1, i32 %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_insert_h_RES
   ret void
@@ -60,8 +60,8 @@ declare <8 x i16> @llvm.mips.insert.h(<8 x i16>, i32, i32) nounwind
 
 define void @llvm_mips_insert_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_insert_w_ARG1
-  %1 = load i32* @llvm_mips_insert_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_insert_w_ARG1
+  %1 = load i32, i32* @llvm_mips_insert_w_ARG3
   %2 = tail call <4 x i32> @llvm.mips.insert.w(<4 x i32> %0, i32 1, i32 %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_insert_w_RES
   ret void
@@ -82,8 +82,8 @@ declare <4 x i32> @llvm.mips.insert.w(<4 x i32>, i32, i32) nounwind
 
 define void @llvm_mips_insert_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_insert_d_ARG1
-  %1 = load i64* @llvm_mips_insert_d_ARG3
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_insert_d_ARG1
+  %1 = load i64, i64* @llvm_mips_insert_d_ARG3
   %2 = tail call <2 x i64> @llvm.mips.insert.d(<2 x i64> %0, i32 1, i64 %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_insert_d_RES
   ret void
@@ -110,8 +110,8 @@ declare <2 x i64> @llvm.mips.insert.d(<2 x i64>, i32, i64) nounwind
 
 define void @llvm_mips_insve_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_insve_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_insve_b_ARG3
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_insve_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_insve_b_ARG3
   %2 = tail call <16 x i8> @llvm.mips.insve.b(<16 x i8> %0, i32 1, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_insve_b_RES
   ret void
@@ -136,8 +136,8 @@ declare <16 x i8> @llvm.mips.insve.b(<16 x i8>, i32, <16 x i8>) nounwind
 
 define void @llvm_mips_insve_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_insve_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_insve_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_insve_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_insve_h_ARG3
   %2 = tail call <8 x i16> @llvm.mips.insve.h(<8 x i16> %0, i32 1, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_insve_h_RES
   ret void
@@ -162,8 +162,8 @@ declare <8 x i16> @llvm.mips.insve.h(<8 x i16>, i32, <8 x i16>) nounwind
 
 define void @llvm_mips_insve_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_insve_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_insve_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_insve_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_insve_w_ARG3
   %2 = tail call <4 x i32> @llvm.mips.insve.w(<4 x i32> %0, i32 1, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_insve_w_RES
   ret void
@@ -188,8 +188,8 @@ declare <4 x i32> @llvm.mips.insve.w(<4 x i32>, i32, <4 x i32>) nounwind
 
 define void @llvm_mips_insve_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_insve_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_insve_d_ARG3
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_insve_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_insve_d_ARG3
   %2 = tail call <2 x i64> @llvm.mips.insve.d(<2 x i64> %0, i32 1, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_insve_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/elm_move.ll b/test/CodeGen/Mips/msa/elm_move.ll
index 98c06c732c36..9665b6d688f3 100644
--- a/test/CodeGen/Mips/msa/elm_move.ll
+++ b/test/CodeGen/Mips/msa/elm_move.ll
@@ -9,7 +9,7 @@
 
 define void @llvm_mips_move_vb_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_move_vb_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_move_vb_ARG1
   %1 = tail call <16 x i8> @llvm.mips.move.v(<16 x i8> %0)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_move_vb_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/elm_shift_slide.ll b/test/CodeGen/Mips/msa/elm_shift_slide.ll
index 00a6544b1207..87f15f1a8c92 100644
--- a/test/CodeGen/Mips/msa/elm_shift_slide.ll
+++ b/test/CodeGen/Mips/msa/elm_shift_slide.ll
@@ -10,8 +10,8 @@
 
 define void @llvm_mips_sldi_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_sldi_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_sldi_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sldi_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_sldi_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.sldi.b(<16 x i8> %0, <16 x i8> %1, i32 1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_sldi_b_RES
   ret void
@@ -31,8 +31,8 @@ declare <16 x i8> @llvm.mips.sldi.b(<16 x i8>, <16 x i8>, i32) nounwind
 
 define void @llvm_mips_sldi_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_sldi_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_sldi_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sldi_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_sldi_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.sldi.h(<8 x i16> %0, <8 x i16> %1, i32 1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_sldi_h_RES
   ret void
@@ -52,8 +52,8 @@ declare <8 x i16> @llvm.mips.sldi.h(<8 x i16>, <8 x i16>, i32) nounwind
 
 define void @llvm_mips_sldi_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_sldi_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_sldi_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sldi_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_sldi_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.sldi.w(<4 x i32> %0, <4 x i32> %1, i32 1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_sldi_w_RES
   ret void
@@ -73,8 +73,8 @@ declare <4 x i32> @llvm.mips.sldi.w(<4 x i32>, <4 x i32>, i32) nounwind
 
 define void @llvm_mips_sldi_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_sldi_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_sldi_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sldi_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_sldi_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.sldi.d(<2 x i64> %0, <2 x i64> %1, i32 1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_sldi_d_RES
   ret void
@@ -93,7 +93,7 @@ declare <2 x i64> @llvm.mips.sldi.d(<2 x i64>, <2 x i64>, i32) nounwind
 
 define void @llvm_mips_splati_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_splati_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_splati_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.splati.b(<16 x i8> %0, i32 1)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_splati_b_RES
   ret void
@@ -112,7 +112,7 @@ declare <16 x i8> @llvm.mips.splati.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_splati_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_splati_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_splati_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.splati.h(<8 x i16> %0, i32 1)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_splati_h_RES
   ret void
@@ -131,7 +131,7 @@ declare <8 x i16> @llvm.mips.splati.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_splati_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_splati_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_splati_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.splati.w(<4 x i32> %0, i32 1)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_splati_w_RES
   ret void
@@ -150,7 +150,7 @@ declare <4 x i32> @llvm.mips.splati.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_splati_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_splati_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_splati_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.splati.d(<2 x i64> %0, i32 1)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_splati_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/frameindex.ll b/test/CodeGen/Mips/msa/frameindex.ll
index ebec465a3e33..afd28ae184dd 100644
--- a/test/CodeGen/Mips/msa/frameindex.ll
+++ b/test/CodeGen/Mips/msa/frameindex.ll
@@ -5,7 +5,7 @@ define void @loadstore_v16i8_near() nounwind {
   ; MIPS32-AE: loadstore_v16i8_near:
 
   %1 = alloca <16 x i8>
-  %2 = load volatile <16 x i8>* %1
+  %2 = load volatile <16 x i8>, <16 x i8>* %1
   ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0($sp)
   store volatile <16 x i8> %2, <16 x i8>* %1
   ; MIPS32-AE: st.b [[R1]], 0($sp)
@@ -20,7 +20,7 @@ define void @loadstore_v16i8_just_under_simm10() nounwind {
   %1 = alloca <16 x i8>
   %2 = alloca [496 x i8] ; Push the frame right up to 512 bytes
 
-  %3 = load volatile <16 x i8>* %1
+  %3 = load volatile <16 x i8>, <16 x i8>* %1
   ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 496($sp)
   store volatile <16 x i8> %3, <16 x i8>* %1
   ; MIPS32-AE: st.b [[R1]], 496($sp)
@@ -35,7 +35,7 @@ define void @loadstore_v16i8_just_over_simm10() nounwind {
   %1 = alloca <16 x i8>
   %2 = alloca [497 x i8] ; Push the frame just over 512 bytes
 
-  %3 = load volatile <16 x i8>* %1
+  %3 = load volatile <16 x i8>, <16 x i8>* %1
   ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512
   ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
   store volatile <16 x i8> %3, <16 x i8>* %1
@@ -52,7 +52,7 @@ define void @loadstore_v16i8_just_under_simm16() nounwind {
   %1 = alloca <16 x i8>
   %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
 
-  %3 = load volatile <16 x i8>* %1
+  %3 = load volatile <16 x i8>, <16 x i8>* %1
   ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
   ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
   ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
@@ -71,7 +71,7 @@ define void @loadstore_v16i8_just_over_simm16() nounwind {
   %1 = alloca <16 x i8>
   %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
 
-  %3 = load volatile <16 x i8>* %1
+  %3 = load volatile <16 x i8>, <16 x i8>* %1
   ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
   ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
   ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
@@ -88,7 +88,7 @@ define void @loadstore_v8i16_near() nounwind {
   ; MIPS32-AE: loadstore_v8i16_near:
 
   %1 = alloca <8 x i16>
-  %2 = load volatile <8 x i16>* %1
+  %2 = load volatile <8 x i16>, <8 x i16>* %1
   ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0($sp)
   store volatile <8 x i16> %2, <8 x i16>* %1
   ; MIPS32-AE: st.h [[R1]], 0($sp)
@@ -102,11 +102,11 @@ define void @loadstore_v8i16_unaligned() nounwind {
 
   %1 = alloca [2 x <8 x i16>]
   %2 = bitcast [2 x <8 x i16>]* %1 to i8*
-  %3 = getelementptr i8* %2, i32 1
+  %3 = getelementptr i8, i8* %2, i32 1
   %4 = bitcast i8* %3 to [2 x <8 x i16>]*
-  %5 = getelementptr [2 x <8 x i16>]* %4, i32 0, i32 0
+  %5 = getelementptr [2 x <8 x i16>], [2 x <8 x i16>]* %4, i32 0, i32 0
 
-  %6 = load volatile <8 x i16>* %5
+  %6 = load volatile <8 x i16>, <8 x i16>* %5
   ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
   ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
   store volatile <8 x i16> %6, <8 x i16>* %5
@@ -123,7 +123,7 @@ define void @loadstore_v8i16_just_under_simm10() nounwind {
   %1 = alloca <8 x i16>
   %2 = alloca [1008 x i8] ; Push the frame right up to 1024 bytes
 
-  %3 = load volatile <8 x i16>* %1
+  %3 = load volatile <8 x i16>, <8 x i16>* %1
   ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 1008($sp)
   store volatile <8 x i16> %3, <8 x i16>* %1
   ; MIPS32-AE: st.h [[R1]], 1008($sp)
@@ -138,7 +138,7 @@ define void @loadstore_v8i16_just_over_simm10() nounwind {
   %1 = alloca <8 x i16>
   %2 = alloca [1009 x i8] ; Push the frame just over 1024 bytes
 
-  %3 = load volatile <8 x i16>* %1
+  %3 = load volatile <8 x i16>, <8 x i16>* %1
   ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024
   ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
   store volatile <8 x i16> %3, <8 x i16>* %1
@@ -155,7 +155,7 @@ define void @loadstore_v8i16_just_under_simm16() nounwind {
   %1 = alloca <8 x i16>
   %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
 
-  %3 = load volatile <8 x i16>* %1
+  %3 = load volatile <8 x i16>, <8 x i16>* %1
   ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
   ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
   ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
@@ -174,7 +174,7 @@ define void @loadstore_v8i16_just_over_simm16() nounwind {
   %1 = alloca <8 x i16>
   %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
 
-  %3 = load volatile <8 x i16>* %1
+  %3 = load volatile <8 x i16>, <8 x i16>* %1
   ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
   ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
   ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
@@ -191,7 +191,7 @@ define void @loadstore_v4i32_near() nounwind {
   ; MIPS32-AE: loadstore_v4i32_near:
 
   %1 = alloca <4 x i32>
-  %2 = load volatile <4 x i32>* %1
+  %2 = load volatile <4 x i32>, <4 x i32>* %1
   ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0($sp)
   store volatile <4 x i32> %2, <4 x i32>* %1
   ; MIPS32-AE: st.w [[R1]], 0($sp)
@@ -205,11 +205,11 @@ define void @loadstore_v4i32_unaligned() nounwind {
 
   %1 = alloca [2 x <4 x i32>]
   %2 = bitcast [2 x <4 x i32>]* %1 to i8*
-  %3 = getelementptr i8* %2, i32 1
+  %3 = getelementptr i8, i8* %2, i32 1
   %4 = bitcast i8* %3 to [2 x <4 x i32>]*
-  %5 = getelementptr [2 x <4 x i32>]* %4, i32 0, i32 0
+  %5 = getelementptr [2 x <4 x i32>], [2 x <4 x i32>]* %4, i32 0, i32 0
 
-  %6 = load volatile <4 x i32>* %5
+  %6 = load volatile <4 x i32>, <4 x i32>* %5
   ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
   ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
   store volatile <4 x i32> %6, <4 x i32>* %5
@@ -226,7 +226,7 @@ define void @loadstore_v4i32_just_under_simm10() nounwind {
   %1 = alloca <4 x i32>
   %2 = alloca [2032 x i8] ; Push the frame right up to 2048 bytes
 
-  %3 = load volatile <4 x i32>* %1
+  %3 = load volatile <4 x i32>, <4 x i32>* %1
   ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 2032($sp)
   store volatile <4 x i32> %3, <4 x i32>* %1
   ; MIPS32-AE: st.w [[R1]], 2032($sp)
@@ -241,7 +241,7 @@ define void @loadstore_v4i32_just_over_simm10() nounwind {
   %1 = alloca <4 x i32>
   %2 = alloca [2033 x i8] ; Push the frame just over 2048 bytes
 
-  %3 = load volatile <4 x i32>* %1
+  %3 = load volatile <4 x i32>, <4 x i32>* %1
   ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048
   ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
   store volatile <4 x i32> %3, <4 x i32>* %1
@@ -258,7 +258,7 @@ define void @loadstore_v4i32_just_under_simm16() nounwind {
   %1 = alloca <4 x i32>
   %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
 
-  %3 = load volatile <4 x i32>* %1
+  %3 = load volatile <4 x i32>, <4 x i32>* %1
   ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
   ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
   ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
@@ -277,7 +277,7 @@ define void @loadstore_v4i32_just_over_simm16() nounwind {
   %1 = alloca <4 x i32>
   %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
 
-  %3 = load volatile <4 x i32>* %1
+  %3 = load volatile <4 x i32>, <4 x i32>* %1
   ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
   ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
   ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
@@ -294,7 +294,7 @@ define void @loadstore_v2i64_near() nounwind {
   ; MIPS32-AE: loadstore_v2i64_near:
 
   %1 = alloca <2 x i64>
-  %2 = load volatile <2 x i64>* %1
+  %2 = load volatile <2 x i64>, <2 x i64>* %1
   ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0($sp)
   store volatile <2 x i64> %2, <2 x i64>* %1
   ; MIPS32-AE: st.d [[R1]], 0($sp)
@@ -308,11 +308,11 @@ define void @loadstore_v2i64_unaligned() nounwind {
 
   %1 = alloca [2 x <2 x i64>]
   %2 = bitcast [2 x <2 x i64>]* %1 to i8*
-  %3 = getelementptr i8* %2, i32 1
+  %3 = getelementptr i8, i8* %2, i32 1
   %4 = bitcast i8* %3 to [2 x <2 x i64>]*
-  %5 = getelementptr [2 x <2 x i64>]* %4, i32 0, i32 0
+  %5 = getelementptr [2 x <2 x i64>], [2 x <2 x i64>]* %4, i32 0, i32 0
 
-  %6 = load volatile <2 x i64>* %5
+  %6 = load volatile <2 x i64>, <2 x i64>* %5
   ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
   ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
   store volatile <2 x i64> %6, <2 x i64>* %5
@@ -329,7 +329,7 @@ define void @loadstore_v2i64_just_under_simm10() nounwind {
   %1 = alloca <2 x i64>
   %2 = alloca [4080 x i8] ; Push the frame right up to 4096 bytes
 
-  %3 = load volatile <2 x i64>* %1
+  %3 = load volatile <2 x i64>, <2 x i64>* %1
   ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 4080($sp)
   store volatile <2 x i64> %3, <2 x i64>* %1
   ; MIPS32-AE: st.d [[R1]], 4080($sp)
@@ -344,7 +344,7 @@ define void @loadstore_v2i64_just_over_simm10() nounwind {
   %1 = alloca <2 x i64>
   %2 = alloca [4081 x i8] ; Push the frame just over 4096 bytes
 
-  %3 = load volatile <2 x i64>* %1
+  %3 = load volatile <2 x i64>, <2 x i64>* %1
   ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096
   ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
   store volatile <2 x i64> %3, <2 x i64>* %1
@@ -361,7 +361,7 @@ define void @loadstore_v2i64_just_under_simm16() nounwind {
   %1 = alloca <2 x i64>
   %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
 
-  %3 = load volatile <2 x i64>* %1
+  %3 = load volatile <2 x i64>, <2 x i64>* %1
   ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
   ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
   ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
@@ -380,7 +380,7 @@ define void @loadstore_v2i64_just_over_simm16() nounwind {
   %1 = alloca <2 x i64>
   %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
 
-  %3 = load volatile <2 x i64>* %1
+  %3 = load volatile <2 x i64>, <2 x i64>* %1
   ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
   ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
   ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
diff --git a/test/CodeGen/Mips/msa/i10.ll b/test/CodeGen/Mips/msa/i10.ll
index c5a96174a734..204884bbf025 100644
--- a/test/CodeGen/Mips/msa/i10.ll
+++ b/test/CodeGen/Mips/msa/i10.ll
@@ -7,7 +7,7 @@
 
 define i32 @llvm_mips_bnz_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bnz_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bnz_b_ARG1
   %1 = tail call i32 @llvm.mips.bnz.b(<16 x i8> %0)
   %2 = icmp eq i32 %1, 0
   br i1 %2, label %true, label %false
@@ -28,7 +28,7 @@ declare i32 @llvm.mips.bnz.b(<16 x i8>) nounwind
 
 define i32 @llvm_mips_bnz_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_bnz_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bnz_h_ARG1
   %1 = tail call i32 @llvm.mips.bnz.h(<8 x i16> %0)
   %2 = icmp eq i32 %1, 0
   br i1 %2, label %true, label %false
@@ -49,7 +49,7 @@ declare i32 @llvm.mips.bnz.h(<8 x i16>) nounwind
 
 define i32 @llvm_mips_bnz_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_bnz_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bnz_w_ARG1
   %1 = tail call i32 @llvm.mips.bnz.w(<4 x i32> %0)
   %2 = icmp eq i32 %1, 0
   br i1 %2, label %true, label %false
@@ -70,7 +70,7 @@ declare i32 @llvm.mips.bnz.w(<4 x i32>) nounwind
 
 define i32 @llvm_mips_bnz_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_bnz_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bnz_d_ARG1
   %1 = tail call i32 @llvm.mips.bnz.d(<2 x i64> %0)
   %2 = icmp eq i32 %1, 0
   br i1 %2, label %true, label %false
diff --git a/test/CodeGen/Mips/msa/i5-a.ll b/test/CodeGen/Mips/msa/i5-a.ll
index 0b507208f429..f9486b17e0ad 100644
--- a/test/CodeGen/Mips/msa/i5-a.ll
+++ b/test/CodeGen/Mips/msa/i5-a.ll
@@ -9,7 +9,7 @@
 
 define void @llvm_mips_addvi_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_addvi_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_addvi_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.addvi.b(<16 x i8> %0, i32 14)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_addvi_b_RES
   ret void
@@ -28,7 +28,7 @@ declare <16 x i8> @llvm.mips.addvi.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_addvi_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_addvi_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_addvi_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.addvi.h(<8 x i16> %0, i32 14)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_addvi_h_RES
   ret void
@@ -47,7 +47,7 @@ declare <8 x i16> @llvm.mips.addvi.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_addvi_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_addvi_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_addvi_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %0, i32 14)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_addvi_w_RES
   ret void
@@ -66,7 +66,7 @@ declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_addvi_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_addvi_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_addvi_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.addvi.d(<2 x i64> %0, i32 14)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_addvi_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/i5-b.ll b/test/CodeGen/Mips/msa/i5-b.ll
index da6be669f0dd..40ab095f6809 100644
--- a/test/CodeGen/Mips/msa/i5-b.ll
+++ b/test/CodeGen/Mips/msa/i5-b.ll
@@ -9,7 +9,7 @@
 
 define void @llvm_mips_bclri_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bclri_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bclri_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.bclri.b(<16 x i8> %0, i32 7)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_bclri_b_RES
   ret void
@@ -29,7 +29,7 @@ declare <16 x i8> @llvm.mips.bclri.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_bclri_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_bclri_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bclri_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.bclri.h(<8 x i16> %0, i32 7)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_bclri_h_RES
   ret void
@@ -48,7 +48,7 @@ declare <8 x i16> @llvm.mips.bclri.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_bclri_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_bclri_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bclri_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.bclri.w(<4 x i32> %0, i32 7)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_bclri_w_RES
   ret void
@@ -67,7 +67,7 @@ declare <4 x i32> @llvm.mips.bclri.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_bclri_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_bclri_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bclri_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.bclri.d(<2 x i64> %0, i32 7)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_bclri_d_RES
   ret void
@@ -87,8 +87,8 @@ declare <2 x i64> @llvm.mips.bclri.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_binsli_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_binsli_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_binsli_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_binsli_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_binsli_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.binsli.b(<16 x i8> %0, <16 x i8> %1, i32 7)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_binsli_b_RES
   ret void
@@ -112,8 +112,8 @@ declare <16 x i8> @llvm.mips.binsli.b(<16 x i8>, <16 x i8>, i32) nounwind
 
 define void @llvm_mips_binsli_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_binsli_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_binsli_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_binsli_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_binsli_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.binsli.h(<8 x i16> %0, <8 x i16> %1, i32 7)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_binsli_h_RES
   ret void
@@ -137,8 +137,8 @@ declare <8 x i16> @llvm.mips.binsli.h(<8 x i16>, <8 x i16>, i32) nounwind
 
 define void @llvm_mips_binsli_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_binsli_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_binsli_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_binsli_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_binsli_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.binsli.w(<4 x i32> %0, <4 x i32> %1, i32 7)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_binsli_w_RES
   ret void
@@ -162,8 +162,8 @@ declare <4 x i32> @llvm.mips.binsli.w(<4 x i32>, <4 x i32>, i32) nounwind
 
 define void @llvm_mips_binsli_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_binsli_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_binsli_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_binsli_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_binsli_d_ARG2
   ; TODO: We use a particularly wide mask here to work around a legalization
   ;       issue. If the mask doesn't fit within a 10-bit immediate, it gets
   ;       legalized into a constant pool. We should add a test to cover the
@@ -191,8 +191,8 @@ declare <2 x i64> @llvm.mips.binsli.d(<2 x i64>, <2 x i64>, i32) nounwind
 
 define void @llvm_mips_binsri_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_binsri_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_binsri_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_binsri_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_binsri_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.binsri.b(<16 x i8> %0, <16 x i8> %1, i32 7)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_binsri_b_RES
   ret void
@@ -216,8 +216,8 @@ declare <16 x i8> @llvm.mips.binsri.b(<16 x i8>, <16 x i8>, i32) nounwind
 
 define void @llvm_mips_binsri_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_binsri_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_binsri_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_binsri_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_binsri_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.binsri.h(<8 x i16> %0, <8 x i16> %1, i32 7)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_binsri_h_RES
   ret void
@@ -241,8 +241,8 @@ declare <8 x i16> @llvm.mips.binsri.h(<8 x i16>, <8 x i16>, i32) nounwind
 
 define void @llvm_mips_binsri_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_binsri_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_binsri_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_binsri_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_binsri_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.binsri.w(<4 x i32> %0, <4 x i32> %1, i32 7)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_binsri_w_RES
   ret void
@@ -266,8 +266,8 @@ declare <4 x i32> @llvm.mips.binsri.w(<4 x i32>, <4 x i32>, i32) nounwind
 
 define void @llvm_mips_binsri_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_binsri_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_binsri_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_binsri_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_binsri_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.binsri.d(<2 x i64> %0, <2 x i64> %1, i32 7)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_binsri_d_RES
   ret void
@@ -290,7 +290,7 @@ declare <2 x i64> @llvm.mips.binsri.d(<2 x i64>, <2 x i64>, i32) nounwind
 
 define void @llvm_mips_bnegi_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bnegi_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bnegi_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.bnegi.b(<16 x i8> %0, i32 7)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_bnegi_b_RES
   ret void
@@ -309,7 +309,7 @@ declare <16 x i8> @llvm.mips.bnegi.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_bnegi_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_bnegi_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bnegi_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.bnegi.h(<8 x i16> %0, i32 7)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_bnegi_h_RES
   ret void
@@ -328,7 +328,7 @@ declare <8 x i16> @llvm.mips.bnegi.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_bnegi_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_bnegi_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bnegi_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.bnegi.w(<4 x i32> %0, i32 7)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_bnegi_w_RES
   ret void
@@ -347,7 +347,7 @@ declare <4 x i32> @llvm.mips.bnegi.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_bnegi_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_bnegi_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bnegi_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.bnegi.d(<2 x i64> %0, i32 7)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_bnegi_d_RES
   ret void
@@ -366,7 +366,7 @@ declare <2 x i64> @llvm.mips.bnegi.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_bseti_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bseti_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bseti_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.bseti.b(<16 x i8> %0, i32 7)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_bseti_b_RES
   ret void
@@ -385,7 +385,7 @@ declare <16 x i8> @llvm.mips.bseti.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_bseti_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_bseti_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bseti_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.bseti.h(<8 x i16> %0, i32 7)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_bseti_h_RES
   ret void
@@ -404,7 +404,7 @@ declare <8 x i16> @llvm.mips.bseti.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_bseti_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_bseti_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bseti_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.bseti.w(<4 x i32> %0, i32 7)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_bseti_w_RES
   ret void
@@ -423,7 +423,7 @@ declare <4 x i32> @llvm.mips.bseti.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_bseti_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_bseti_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bseti_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.bseti.d(<2 x i64> %0, i32 7)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_bseti_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/i5-c.ll b/test/CodeGen/Mips/msa/i5-c.ll
index bf1578f30f32..815825013ea1 100644
--- a/test/CodeGen/Mips/msa/i5-c.ll
+++ b/test/CodeGen/Mips/msa/i5-c.ll
@@ -9,7 +9,7 @@
 
 define void @llvm_mips_ceqi_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_ceqi_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_ceqi_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.ceqi.b(<16 x i8> %0, i32 14)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_ceqi_b_RES
   ret void
@@ -28,7 +28,7 @@ declare <16 x i8> @llvm.mips.ceqi.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_ceqi_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_ceqi_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ceqi_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.ceqi.h(<8 x i16> %0, i32 14)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_ceqi_h_RES
   ret void
@@ -47,7 +47,7 @@ declare <8 x i16> @llvm.mips.ceqi.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_ceqi_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_ceqi_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ceqi_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.ceqi.w(<4 x i32> %0, i32 14)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_ceqi_w_RES
   ret void
@@ -66,7 +66,7 @@ declare <4 x i32> @llvm.mips.ceqi.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_ceqi_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_ceqi_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ceqi_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.ceqi.d(<2 x i64> %0, i32 14)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_ceqi_d_RES
   ret void
@@ -85,7 +85,7 @@ declare <2 x i64> @llvm.mips.ceqi.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_clei_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_clei_s_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clei_s_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.clei.s.b(<16 x i8> %0, i32 14)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_clei_s_b_RES
   ret void
@@ -104,7 +104,7 @@ declare <16 x i8> @llvm.mips.clei.s.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_clei_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_clei_s_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clei_s_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.clei.s.h(<8 x i16> %0, i32 14)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_clei_s_h_RES
   ret void
@@ -123,7 +123,7 @@ declare <8 x i16> @llvm.mips.clei.s.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_clei_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_clei_s_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clei_s_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.clei.s.w(<4 x i32> %0, i32 14)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_clei_s_w_RES
   ret void
@@ -142,7 +142,7 @@ declare <4 x i32> @llvm.mips.clei.s.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_clei_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_clei_s_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clei_s_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.clei.s.d(<2 x i64> %0, i32 14)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_clei_s_d_RES
   ret void
@@ -161,7 +161,7 @@ declare <2 x i64> @llvm.mips.clei.s.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_clei_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_clei_u_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clei_u_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.clei.u.b(<16 x i8> %0, i32 14)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_clei_u_b_RES
   ret void
@@ -180,7 +180,7 @@ declare <16 x i8> @llvm.mips.clei.u.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_clei_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_clei_u_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clei_u_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.clei.u.h(<8 x i16> %0, i32 14)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_clei_u_h_RES
   ret void
@@ -199,7 +199,7 @@ declare <8 x i16> @llvm.mips.clei.u.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_clei_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_clei_u_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clei_u_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.clei.u.w(<4 x i32> %0, i32 14)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_clei_u_w_RES
   ret void
@@ -218,7 +218,7 @@ declare <4 x i32> @llvm.mips.clei.u.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_clei_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_clei_u_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clei_u_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.clei.u.d(<2 x i64> %0, i32 14)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_clei_u_d_RES
   ret void
@@ -237,7 +237,7 @@ declare <2 x i64> @llvm.mips.clei.u.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_clti_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_clti_s_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clti_s_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.clti.s.b(<16 x i8> %0, i32 14)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_clti_s_b_RES
   ret void
@@ -256,7 +256,7 @@ declare <16 x i8> @llvm.mips.clti.s.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_clti_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_clti_s_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clti_s_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.clti.s.h(<8 x i16> %0, i32 14)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_clti_s_h_RES
   ret void
@@ -275,7 +275,7 @@ declare <8 x i16> @llvm.mips.clti.s.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_clti_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_clti_s_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clti_s_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.clti.s.w(<4 x i32> %0, i32 14)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_clti_s_w_RES
   ret void
@@ -294,7 +294,7 @@ declare <4 x i32> @llvm.mips.clti.s.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_clti_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_clti_s_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clti_s_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.clti.s.d(<2 x i64> %0, i32 14)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_clti_s_d_RES
   ret void
@@ -313,7 +313,7 @@ declare <2 x i64> @llvm.mips.clti.s.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_clti_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_clti_u_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clti_u_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.clti.u.b(<16 x i8> %0, i32 14)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_clti_u_b_RES
   ret void
@@ -332,7 +332,7 @@ declare <16 x i8> @llvm.mips.clti.u.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_clti_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_clti_u_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clti_u_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.clti.u.h(<8 x i16> %0, i32 14)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_clti_u_h_RES
   ret void
@@ -351,7 +351,7 @@ declare <8 x i16> @llvm.mips.clti.u.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_clti_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_clti_u_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clti_u_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.clti.u.w(<4 x i32> %0, i32 14)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_clti_u_w_RES
   ret void
@@ -370,7 +370,7 @@ declare <4 x i32> @llvm.mips.clti.u.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_clti_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_clti_u_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clti_u_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.clti.u.d(<2 x i64> %0, i32 14)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_clti_u_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/i5-m.ll b/test/CodeGen/Mips/msa/i5-m.ll
index 27663494324d..ba6e9d2384a7 100644
--- a/test/CodeGen/Mips/msa/i5-m.ll
+++ b/test/CodeGen/Mips/msa/i5-m.ll
@@ -9,7 +9,7 @@
 
 define void @llvm_mips_maxi_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_maxi_s_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_maxi_s_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.maxi.s.b(<16 x i8> %0, i32 14)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_maxi_s_b_RES
   ret void
@@ -28,7 +28,7 @@ declare <16 x i8> @llvm.mips.maxi.s.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_maxi_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_maxi_s_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_maxi_s_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.maxi.s.h(<8 x i16> %0, i32 14)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_maxi_s_h_RES
   ret void
@@ -47,7 +47,7 @@ declare <8 x i16> @llvm.mips.maxi.s.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_maxi_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_maxi_s_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_maxi_s_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.maxi.s.w(<4 x i32> %0, i32 14)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_maxi_s_w_RES
   ret void
@@ -66,7 +66,7 @@ declare <4 x i32> @llvm.mips.maxi.s.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_maxi_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_maxi_s_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_maxi_s_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.maxi.s.d(<2 x i64> %0, i32 14)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_maxi_s_d_RES
   ret void
@@ -85,7 +85,7 @@ declare <2 x i64> @llvm.mips.maxi.s.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_maxi_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_maxi_u_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_maxi_u_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.maxi.u.b(<16 x i8> %0, i32 14)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_maxi_u_b_RES
   ret void
@@ -104,7 +104,7 @@ declare <16 x i8> @llvm.mips.maxi.u.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_maxi_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_maxi_u_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_maxi_u_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.maxi.u.h(<8 x i16> %0, i32 14)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_maxi_u_h_RES
   ret void
@@ -123,7 +123,7 @@ declare <8 x i16> @llvm.mips.maxi.u.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_maxi_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_maxi_u_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_maxi_u_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.maxi.u.w(<4 x i32> %0, i32 14)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_maxi_u_w_RES
   ret void
@@ -142,7 +142,7 @@ declare <4 x i32> @llvm.mips.maxi.u.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_maxi_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_maxi_u_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_maxi_u_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.maxi.u.d(<2 x i64> %0, i32 14)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_maxi_u_d_RES
   ret void
@@ -161,7 +161,7 @@ declare <2 x i64> @llvm.mips.maxi.u.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_mini_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_mini_s_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_mini_s_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.mini.s.b(<16 x i8> %0, i32 14)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_mini_s_b_RES
   ret void
@@ -180,7 +180,7 @@ declare <16 x i8> @llvm.mips.mini.s.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_mini_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_mini_s_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_mini_s_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.mini.s.h(<8 x i16> %0, i32 14)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_mini_s_h_RES
   ret void
@@ -199,7 +199,7 @@ declare <8 x i16> @llvm.mips.mini.s.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_mini_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_mini_s_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_mini_s_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.mini.s.w(<4 x i32> %0, i32 14)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_mini_s_w_RES
   ret void
@@ -218,7 +218,7 @@ declare <4 x i32> @llvm.mips.mini.s.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_mini_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_mini_s_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_mini_s_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.mini.s.d(<2 x i64> %0, i32 14)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_mini_s_d_RES
   ret void
@@ -237,7 +237,7 @@ declare <2 x i64> @llvm.mips.mini.s.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_mini_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_mini_u_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_mini_u_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.mini.u.b(<16 x i8> %0, i32 14)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_mini_u_b_RES
   ret void
@@ -256,7 +256,7 @@ declare <16 x i8> @llvm.mips.mini.u.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_mini_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_mini_u_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_mini_u_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.mini.u.h(<8 x i16> %0, i32 14)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_mini_u_h_RES
   ret void
@@ -275,7 +275,7 @@ declare <8 x i16> @llvm.mips.mini.u.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_mini_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_mini_u_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_mini_u_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.mini.u.w(<4 x i32> %0, i32 14)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_mini_u_w_RES
   ret void
@@ -294,7 +294,7 @@ declare <4 x i32> @llvm.mips.mini.u.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_mini_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_mini_u_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_mini_u_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.mini.u.d(<2 x i64> %0, i32 14)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_mini_u_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/i5-s.ll b/test/CodeGen/Mips/msa/i5-s.ll
index 184172f63b85..db331b1476ce 100644
--- a/test/CodeGen/Mips/msa/i5-s.ll
+++ b/test/CodeGen/Mips/msa/i5-s.ll
@@ -9,7 +9,7 @@
 
 define void @llvm_mips_subvi_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_subvi_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_subvi_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.subvi.b(<16 x i8> %0, i32 14)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_subvi_b_RES
   ret void
@@ -28,7 +28,7 @@ declare <16 x i8> @llvm.mips.subvi.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_subvi_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_subvi_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_subvi_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.subvi.h(<8 x i16> %0, i32 14)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_subvi_h_RES
   ret void
@@ -47,7 +47,7 @@ declare <8 x i16> @llvm.mips.subvi.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_subvi_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_subvi_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_subvi_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.subvi.w(<4 x i32> %0, i32 14)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_subvi_w_RES
   ret void
@@ -66,7 +66,7 @@ declare <4 x i32> @llvm.mips.subvi.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_subvi_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_subvi_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_subvi_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.subvi.d(<2 x i64> %0, i32 14)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_subvi_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/i5_ld_st.ll b/test/CodeGen/Mips/msa/i5_ld_st.ll
index 7cc55f2904be..991bb8436b33 100644
--- a/test/CodeGen/Mips/msa/i5_ld_st.ll
+++ b/test/CodeGen/Mips/msa/i5_ld_st.ll
@@ -81,7 +81,7 @@ declare <2 x i64> @llvm.mips.ld.d(i8*, i32) nounwind
 
 define void @llvm_mips_st_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_st_b_ARG
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_st_b_ARG
   %1 = bitcast <16 x i8>* @llvm_mips_st_b_RES to i8*
   tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 16)
   ret void
@@ -99,7 +99,7 @@ declare void @llvm.mips.st.b(<16 x i8>, i8*, i32) nounwind
 
 define void @llvm_mips_st_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_st_h_ARG
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_st_h_ARG
   %1 = bitcast <8 x i16>* @llvm_mips_st_h_RES to i8*
   tail call void @llvm.mips.st.h(<8 x i16> %0, i8* %1, i32 16)
   ret void
@@ -117,7 +117,7 @@ declare void @llvm.mips.st.h(<8 x i16>, i8*, i32) nounwind
 
 define void @llvm_mips_st_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_st_w_ARG
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_st_w_ARG
   %1 = bitcast <4 x i32>* @llvm_mips_st_w_RES to i8*
   tail call void @llvm.mips.st.w(<4 x i32> %0, i8* %1, i32 16)
   ret void
@@ -135,7 +135,7 @@ declare void @llvm.mips.st.w(<4 x i32>, i8*, i32) nounwind
 
 define void @llvm_mips_st_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_st_d_ARG
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_st_d_ARG
   %1 = bitcast <2 x i64>* @llvm_mips_st_d_RES to i8*
   tail call void @llvm.mips.st.d(<2 x i64> %0, i8* %1, i32 16)
   ret void
diff --git a/test/CodeGen/Mips/msa/i8.ll b/test/CodeGen/Mips/msa/i8.ll
index d2931a72feaa..4af9c588fdef 100644
--- a/test/CodeGen/Mips/msa/i8.ll
+++ b/test/CodeGen/Mips/msa/i8.ll
@@ -8,7 +8,7 @@
 
 define void @llvm_mips_andi_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_andi_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_andi_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.andi.b(<16 x i8> %0, i32 25)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_andi_b_RES
   ret void
@@ -28,8 +28,8 @@ declare <16 x i8> @llvm.mips.andi.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_bmnzi_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bmnzi_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_bmnzi_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnzi_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnzi_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 25)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_bmnzi_b_RES
   ret void
@@ -52,8 +52,8 @@ declare <16 x i8> @llvm.mips.bmnzi.b(<16 x i8>, <16 x i8>, i32) nounwind
 
 define void @llvm_mips_bmzi_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bmzi_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_bmzi_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bmzi_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bmzi_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 25)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_bmzi_b_RES
   ret void
@@ -77,8 +77,8 @@ declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, <16 x i8>, i32) nounwind
 
 define void @llvm_mips_bseli_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bseli_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_bseli_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bseli_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bseli_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %0, <16 x i8> %1, i32 25)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_bseli_b_RES
   ret void
@@ -100,7 +100,7 @@ declare <16 x i8> @llvm.mips.bseli.b(<16 x i8>, <16 x i8>, i32) nounwind
 
 define void @llvm_mips_nori_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_nori_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_nori_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.nori.b(<16 x i8> %0, i32 25)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_nori_b_RES
   ret void
@@ -119,7 +119,7 @@ declare <16 x i8> @llvm.mips.nori.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_ori_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_ori_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_ori_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.ori.b(<16 x i8> %0, i32 25)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_ori_b_RES
   ret void
@@ -138,7 +138,7 @@ declare <16 x i8> @llvm.mips.ori.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_shf_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_shf_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_shf_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.shf.b(<16 x i8> %0, i32 25)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_shf_b_RES
   ret void
@@ -157,7 +157,7 @@ declare <16 x i8> @llvm.mips.shf.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_shf_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_shf_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_shf_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.shf.h(<8 x i16> %0, i32 25)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_shf_h_RES
   ret void
@@ -176,7 +176,7 @@ declare <8 x i16> @llvm.mips.shf.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_shf_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_shf_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_shf_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.shf.w(<4 x i32> %0, i32 25)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_shf_w_RES
   ret void
@@ -195,7 +195,7 @@ declare <4 x i32> @llvm.mips.shf.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_xori_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_xori_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_xori_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.xori.b(<16 x i8> %0, i32 25)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_xori_b_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/inline-asm.ll b/test/CodeGen/Mips/msa/inline-asm.ll
index 4a34273f3c00..85da87b6f8a7 100644
--- a/test/CodeGen/Mips/msa/inline-asm.ll
+++ b/test/CodeGen/Mips/msa/inline-asm.ll
@@ -16,7 +16,7 @@ entry:
 define void @test2() nounwind {
 entry:
   ; CHECK-LABEL: test2:
-  %0 = load <4 x i32>* @v4i32_r
+  %0 = load <4 x i32>, <4 x i32>* @v4i32_r
   %1 = call <4 x i32> asm "addvi.w ${0:w}, ${1:w}, 1", "=f,f"(<4 x i32> %0)
   ; CHECK: addvi.w $w{{[1-3]?[0-9]}}, $w{{[1-3]?[0-9]}}, 1
   store <4 x i32> %1, <4 x i32>* @v4i32_r
@@ -26,7 +26,7 @@ entry:
 define void @test3() nounwind {
 entry:
   ; CHECK-LABEL: test3:
-  %0 = load <4 x i32>* @v4i32_r
+  %0 = load <4 x i32>, <4 x i32>* @v4i32_r
   %1 = call <4 x i32> asm sideeffect "addvi.w ${0:w}, ${1:w}, 1", "=f,f,~{$w0}"(<4 x i32> %0)
   ; CHECK: addvi.w $w{{([1-9]|[1-3][0-9])}}, $w{{([1-9]|[1-3][0-9])}}, 1
   store <4 x i32> %1, <4 x i32>* @v4i32_r
diff --git a/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll b/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll
index 4beaaa9c1841..beb361bc9f3d 100644
--- a/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll
+++ b/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll
@@ -14,7 +14,7 @@ BB:
   %A2 = alloca <1 x double>
   %A1 = alloca double
   %A = alloca i32
-  %L = load i8* %0
+  %L = load i8, i8* %0
   store i8 77, i8* %0
   %E = extractelement <8 x i64> zeroinitializer, i32 2
   %Shuff = shufflevector <8 x i64> zeroinitializer, <8 x i64> zeroinitializer, <8 x i32> <i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15, i32 1, i32 3>
@@ -24,7 +24,7 @@ BB:
   br label %CF
 
 CF:                                               ; preds = %CF, %CF78, %BB
-  %L5 = load i8* %Sl
+  %L5 = load i8, i8* %Sl
   store i8 %L, i8* %Sl
   %E6 = extractelement <8 x i32> zeroinitializer, i32 2
   %Shuff7 = shufflevector <8 x i64> zeroinitializer, <8 x i64> %Shuff, <8 x i32> <i32 13, i32 15, i32 1, i32 3, i32 5, i32 7, i32 9, i32 undef>
@@ -33,7 +33,7 @@ CF:                                               ; preds = %CF, %CF78, %BB
   %FC = sitofp <8 x i64> zeroinitializer to <8 x float>
   %Sl9 = select i1 %Cmp, i8 77, i8 77
   %Cmp10 = icmp uge <8 x i64> %Shuff, zeroinitializer
-  %L11 = load i8* %0
+  %L11 = load i8, i8* %0
   store i8 %Sl9, i8* %0
   %E12 = extractelement <1 x i16> zeroinitializer, i32 0
   %Shuff13 = shufflevector <8 x i64> zeroinitializer, <8 x i64> %Shuff, <8 x i32> <i32 9, i32 11, i32 13, i32 15, i32 undef, i32 3, i32 5, i32 7>
@@ -42,7 +42,7 @@ CF:                                               ; preds = %CF, %CF78, %BB
   %Tr = trunc <8 x i64> %Shuff to <8 x i32>
   %Sl16 = select i1 %Cmp, i8 77, i8 %5
   %Cmp17 = icmp ult <8 x i1> %Cmp10, %Cmp10
-  %L18 = load i8* %Sl
+  %L18 = load i8, i8* %Sl
   store i8 -1, i8* %Sl
   %E19 = extractelement <8 x i32> zeroinitializer, i32 3
   %Shuff20 = shufflevector <8 x float> %FC, <8 x float> %FC, <8 x i32> <i32 6, i32 8, i32 undef, i32 12, i32 14, i32 0, i32 2, i32 undef>
@@ -54,7 +54,7 @@ CF:                                               ; preds = %CF, %CF78, %BB
   br i1 %Cmp25, label %CF, label %CF78
 
 CF78:                                             ; preds = %CF
-  %L26 = load i8* %Sl
+  %L26 = load i8, i8* %Sl
   store i32 50347, i32* %A
   %E27 = extractelement <8 x i1> %Cmp10, i32 2
   br i1 %E27, label %CF, label %CF77
@@ -65,7 +65,7 @@ CF77:                                             ; preds = %CF77, %CF81, %CF78
   %B30 = urem <8 x i32> %Tr, zeroinitializer
   %Tr31 = trunc i32 0 to i16
   %Sl32 = select i1 %Cmp, <2 x i1> zeroinitializer, <2 x i1> zeroinitializer
-  %L33 = load i8* %Sl
+  %L33 = load i8, i8* %Sl
   store i8 %L26, i8* %Sl
   %E34 = extractelement <4 x i32> zeroinitializer, i32 0
   %Shuff35 = shufflevector <1 x i16> zeroinitializer, <1 x i16> %B, <1 x i32> undef
@@ -73,7 +73,7 @@ CF77:                                             ; preds = %CF77, %CF81, %CF78
   %B37 = srem <1 x i16> %I29, zeroinitializer
   %FC38 = sitofp <8 x i32> %B30 to <8 x double>
   %Sl39 = select i1 %Cmp, double 0.000000e+00, double %Sl24
-  %L40 = load i8* %Sl
+  %L40 = load i8, i8* %Sl
   store i8 %Sl16, i8* %Sl
   %E41 = extractelement <1 x i16> zeroinitializer, i32 0
   %Shuff42 = shufflevector <8 x i1> %Cmp17, <8 x i1> %Cmp10, <8 x i32> <i32 14, i32 undef, i32 2, i32 4, i32 undef, i32 8, i32 10, i32 12>
@@ -85,7 +85,7 @@ CF77:                                             ; preds = %CF77, %CF81, %CF78
   br i1 %Cmp46, label %CF77, label %CF80
 
 CF80:                                             ; preds = %CF80, %CF77
-  %L47 = load i64* %PC
+  %L47 = load i64, i64* %PC
   store i8 77, i8* %Sl
   %E48 = extractelement <8 x i64> zeroinitializer, i32 2
   %Shuff49 = shufflevector <8 x i64> zeroinitializer, <8 x i64> %Shuff7, <8 x i32> <i32 5, i32 7, i32 9, i32 undef, i32 undef, i32 undef, i32 undef, i32 3>
@@ -97,7 +97,7 @@ CF80:                                             ; preds = %CF80, %CF77
   br i1 %Cmp54, label %CF80, label %CF81
 
 CF81:                                             ; preds = %CF80
-  %L55 = load i8* %Sl
+  %L55 = load i8, i8* %Sl
   store i8 %Sl16, i8* %Sl
   %E56 = extractelement <1 x i16> %B, i32 0
   %Shuff57 = shufflevector <1 x i16> zeroinitializer, <1 x i16> zeroinitializer, <1 x i32> <i32 1>
@@ -105,7 +105,7 @@ CF81:                                             ; preds = %CF80
   %B59 = srem i32 %E19, %E19
   %Sl60 = select i1 %Cmp, i8 77, i8 77
   %Cmp61 = icmp ult <1 x i16> zeroinitializer, %B
-  %L62 = load i8* %Sl
+  %L62 = load i8, i8* %Sl
   store i64 %L47, i64* %PC52
   %E63 = extractelement <4 x i32> %I43, i32 2
   %Shuff64 = shufflevector <4 x i1> zeroinitializer, <4 x i1> zeroinitializer, <4 x i32> <i32 undef, i32 undef, i32 1, i32 3>
@@ -117,7 +117,7 @@ CF81:                                             ; preds = %CF80
   br i1 %Cmp69, label %CF77, label %CF79
 
 CF79:                                             ; preds = %CF81
-  %L70 = load i32* %A
+  %L70 = load i32, i32* %A
   store i64 %4, i64* %PC
   %E71 = extractelement <4 x i32> zeroinitializer, i32 0
   %Shuff72 = shufflevector <8 x i32> zeroinitializer, <8 x i32> %B44, <8 x i32> <i32 11, i32 undef, i32 15, i32 1, i32 3, i32 undef, i32 7, i32 9>
diff --git a/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll b/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll
index f9cab037e7cc..bdf6eafdf4ef 100644
--- a/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll
+++ b/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll
@@ -14,7 +14,7 @@ BB:
   %A2 = alloca i64
   %A1 = alloca i32
   %A = alloca <2 x i64>
-  %L = load i8* %0
+  %L = load i8, i8* %0
   store i8 -1, i8* %0
   %E = extractelement <2 x i32> zeroinitializer, i32 0
   %Shuff = shufflevector <2 x i32> zeroinitializer, <2 x i32> zeroinitializer, <2 x i32> <i32 1, i32 3>
@@ -22,7 +22,7 @@ BB:
   %B = lshr i8 %L, -69
   %ZE = fpext float 0xBF2AA5FE80000000 to double
   %Sl = select i1 true, <1 x i64> <i64 -1>, <1 x i64> <i64 -1>
-  %L5 = load i8* %0
+  %L5 = load i8, i8* %0
   store i8 -69, i8* %0
   %E6 = extractelement <16 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, i32 14
   %Shuff7 = shufflevector <2 x i32> zeroinitializer, <2 x i32> zeroinitializer, <2 x i32> <i32 1, i32 3>
@@ -31,7 +31,7 @@ BB:
   %FC = uitofp i32 %3 to double
   %Sl10 = select i1 true, <1 x i1> zeroinitializer, <1 x i1> zeroinitializer
   %Cmp = icmp ne <1 x i64> %I, <i64 -1>
-  %L11 = load i8* %0
+  %L11 = load i8, i8* %0
   store i8 %L11, i8* %0
   %E12 = extractelement <1 x i64> <i64 -1>, i32 0
   %Shuff13 = shufflevector <1 x i64> %Sl, <1 x i64> <i64 -1>, <1 x i32> <i32 1>
@@ -42,7 +42,7 @@ BB:
   br label %CF74
 
 CF74:                                             ; preds = %CF74, %CF80, %CF76, %BB
-  %L18 = load i8* %0
+  %L18 = load i8, i8* %0
   store i8 -69, i8* %0
   %E19 = extractelement <1 x i64> %Sl, i32 0
   %Shuff20 = shufflevector <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <8 x i32> <i32 12, i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10>
@@ -50,7 +50,7 @@ CF74:                                             ; preds = %CF74, %CF80, %CF76,
   %B22 = urem i32 135673, %3
   %FC23 = sitofp i8 %L to float
   %Sl24 = select i1 true, i8 %B, i8 %L18
-  %L25 = load i8* %0
+  %L25 = load i8, i8* %0
   store i8 %L, i8* %0
   %E26 = extractelement <2 x i32> %Shuff, i32 1
   %Shuff27 = shufflevector <2 x i32> zeroinitializer, <2 x i32> zeroinitializer, <2 x i32> <i32 2, i32 0>
@@ -62,7 +62,7 @@ CF74:                                             ; preds = %CF74, %CF80, %CF76,
   br i1 %Cmp31, label %CF74, label %CF80
 
 CF80:                                             ; preds = %CF74
-  %L32 = load i8* %0
+  %L32 = load i8, i8* %0
   store i8 -1, i8* %0
   %E33 = extractelement <2 x i32> zeroinitializer, i32 1
   %Shuff34 = shufflevector <1 x i64> %Shuff13, <1 x i64> <i64 -1>, <1 x i32> zeroinitializer
@@ -70,7 +70,7 @@ CF80:                                             ; preds = %CF74
   %FC36 = sitofp <1 x i1> %Cmp to <1 x float>
   %Sl37 = select i1 true, <8 x i8> %Shuff20, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   %Cmp38 = icmp sgt <2 x i32> %I21, %Shuff27
-  %L39 = load i8* %0
+  %L39 = load i8, i8* %0
   store i8 %Sl24, i8* %0
   %E40 = extractelement <8 x i64> zeroinitializer, i32 1
   %Shuff41 = shufflevector <2 x i1> zeroinitializer, <2 x i1> %Cmp38, <2 x i32> <i32 0, i32 2>
@@ -81,7 +81,7 @@ CF80:                                             ; preds = %CF74
   br i1 %Cmp45, label %CF74, label %CF76
 
 CF76:                                             ; preds = %CF80
-  %L46 = load i8* %0
+  %L46 = load i8, i8* %0
   store i8 %L39, i8* %0
   %E47 = extractelement <2 x i32> %Shuff27, i32 0
   %Shuff48 = shufflevector <1 x i1> %Sl10, <1 x i1> %Sl10, <1 x i32> <i32 1>
@@ -92,7 +92,7 @@ CF76:                                             ; preds = %CF80
   br i1 %Cmp52, label %CF74, label %CF75
 
 CF75:                                             ; preds = %CF75, %CF76
-  %L53 = load i8* %0
+  %L53 = load i8, i8* %0
   store i8 %L18, i8* %0
   %E54 = extractelement <8 x i8> %Shuff20, i32 5
   %Shuff55 = shufflevector <2 x i32> %Shuff, <2 x i32> zeroinitializer, <2 x i32> <i32 0, i32 2>
@@ -103,7 +103,7 @@ CF75:                                             ; preds = %CF75, %CF76
   br i1 %Cmp59, label %CF75, label %CF78
 
 CF78:                                             ; preds = %CF75
-  %L60 = load i8* %0
+  %L60 = load i8, i8* %0
   store i8 -69, i8* %0
   %E61 = extractelement <2 x i32> zeroinitializer, i32 0
   %Shuff62 = shufflevector <2 x i32> %Shuff7, <2 x i32> %I21, <2 x i32> <i32 1, i32 3>
@@ -115,7 +115,7 @@ CF78:                                             ; preds = %CF75
   br label %CF
 
 CF:                                               ; preds = %CF, %CF78
-  %L68 = load i8* %0
+  %L68 = load i8, i8* %0
   store i64 %B57, i64* %2
   %E69 = extractelement <2 x i1> %Shuff41, i32 1
   br i1 %E69, label %CF, label %CF77
diff --git a/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll b/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll
index e14f405320cb..8f23a8ca5177 100644
--- a/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll
+++ b/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll
@@ -13,7 +13,7 @@ BB:
   %A2 = alloca i8
   %A1 = alloca i32
   %A = alloca i8
-  %L = load i8* %0
+  %L = load i8, i8* %0
   store i8 %5, i8* %0
   %E = extractelement <2 x i16> zeroinitializer, i32 0
   %Shuff = shufflevector <1 x i8> <i8 -1>, <1 x i8> <i8 -1>, <1 x i32> undef
@@ -25,7 +25,7 @@ BB:
   br label %CF83
 
 CF83:                                             ; preds = %BB
-  %L5 = load i8* %0
+  %L5 = load i8, i8* %0
   store i8 85, i8* %0
   %E6 = extractelement <1 x i8> <i8 -1>, i32 0
   %Shuff7 = shufflevector <2 x i16> zeroinitializer, <2 x i16> zeroinitializer, <2 x i32> <i32 1, i32 3>
@@ -37,7 +37,7 @@ CF83:                                             ; preds = %BB
   br label %CF
 
 CF:                                               ; preds = %CF, %CF81, %CF83
-  %L13 = load i8* %0
+  %L13 = load i8, i8* %0
   store i8 0, i8* %0
   %E14 = extractelement <2 x i64> zeroinitializer, i32 0
   %Shuff15 = shufflevector <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, <4 x i32> <i32 3, i32 5, i32 7, i32 undef>
@@ -52,7 +52,7 @@ CF80:                                             ; preds = %CF80, %CF
   br i1 %Cmp19, label %CF80, label %CF81
 
 CF81:                                             ; preds = %CF80
-  %L20 = load i8* %0
+  %L20 = load i8, i8* %0
   store i8 85, i8* %0
   %E21 = extractelement <1 x i8> <i8 -1>, i32 0
   %Shuff22 = shufflevector <1 x i8> <i8 -1>, <1 x i8> %Shuff, <1 x i32> zeroinitializer
@@ -60,7 +60,7 @@ CF81:                                             ; preds = %CF80
   %FC24 = fptoui <4 x float> %FC to <4 x i16>
   %Sl25 = select i1 %Cmp, <2 x i32> zeroinitializer, <2 x i32> <i32 -1, i32 -1>
   %Cmp26 = icmp ult <4 x i64> %I16, %Shuff15
-  %L27 = load i8* %0
+  %L27 = load i8, i8* %0
   store i8 %L, i8* %0
   %E28 = extractelement <1 x i8> <i8 -1>, i32 0
   %Shuff29 = shufflevector <8 x i16> zeroinitializer, <8 x i16> zeroinitializer, <8 x i32> <i32 11, i32 undef, i32 15, i32 1, i32 3, i32 5, i32 undef, i32 9>
@@ -68,7 +68,7 @@ CF81:                                             ; preds = %CF80
   %B31 = mul i8 %E28, 85
   %PC = bitcast i32* %A3 to i32*
   %Sl32 = select i1 %Cmp12, float %FC10, float 0x4712BFE680000000
-  %L33 = load i32* %PC
+  %L33 = load i32, i32* %PC
   store i32 %L33, i32* %PC
   %E34 = extractelement <2 x i16> zeroinitializer, i32 1
   %Shuff35 = shufflevector <1 x i8> %Shuff, <1 x i8> <i8 -1>, <1 x i32> zeroinitializer
@@ -79,7 +79,7 @@ CF81:                                             ; preds = %CF80
   br i1 %Cmp39, label %CF, label %CF77
 
 CF77:                                             ; preds = %CF77, %CF81
-  %L40 = load i32* %PC
+  %L40 = load i32, i32* %PC
   store i32 %3, i32* %PC
   %E41 = extractelement <2 x i32> zeroinitializer, i32 0
   %Shuff42 = shufflevector <2 x i32> <i32 -1, i32 -1>, <2 x i32> zeroinitializer, <2 x i32> <i32 1, i32 3>
@@ -88,7 +88,7 @@ CF77:                                             ; preds = %CF77, %CF81
   %Se = sext i32 %3 to i64
   %Sl45 = select i1 true, <1 x i8> %Shuff, <1 x i8> %I43
   %Cmp46 = icmp sge <1 x i8> %I36, %Shuff
-  %L47 = load i32* %PC
+  %L47 = load i32, i32* %PC
   store i32 %L33, i32* %PC
   %E48 = extractelement <2 x i16> zeroinitializer, i32 0
   %Shuff49 = shufflevector <1 x i8> <i8 -1>, <1 x i8> <i8 -1>, <1 x i32> <i32 1>
@@ -100,7 +100,7 @@ CF77:                                             ; preds = %CF77, %CF81
   br i1 %Cmp54, label %CF77, label %CF78
 
 CF78:                                             ; preds = %CF78, %CF77
-  %L55 = load i32* %PC
+  %L55 = load i32, i32* %PC
   store i32 %L33, i32* %PC
   %E56 = extractelement <8 x i16> %Shuff29, i32 4
   %Shuff57 = shufflevector <1 x i8> <i8 -1>, <1 x i8> <i8 -1>, <1 x i32> <i32 1>
@@ -111,7 +111,7 @@ CF78:                                             ; preds = %CF78, %CF77
   br i1 %Cmp60, label %CF78, label %CF79
 
 CF79:                                             ; preds = %CF79, %CF78
-  %L61 = load i32* %PC
+  %L61 = load i32, i32* %PC
   store i32 %L33, i32* %A3
   %E62 = extractelement <4 x i64> %Shuff15, i32 1
   %Shuff63 = shufflevector <8 x i16> %Shuff29, <8 x i16> %Shuff29, <8 x i32> <i32 undef, i32 10, i32 12, i32 undef, i32 undef, i32 undef, i32 4, i32 6>
@@ -123,7 +123,7 @@ CF79:                                             ; preds = %CF79, %CF78
   br i1 %Cmp68, label %CF79, label %CF82
 
 CF82:                                             ; preds = %CF79
-  %L69 = load i32* %PC
+  %L69 = load i32, i32* %PC
   store i32 %L33, i32* %PC
   %E70 = extractelement <8 x i16> zeroinitializer, i32 3
   %Shuff71 = shufflevector <4 x i64> %Shuff15, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, <4 x i32> <i32 6, i32 undef, i32 2, i32 4>
diff --git a/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll b/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll
index 1a03e55d9d54..e3cf7964497f 100644
--- a/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll
+++ b/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll
@@ -14,7 +14,7 @@ BB:
   %A2 = alloca i64
   %A1 = alloca i64
   %A = alloca double
-  %L = load i8* %0
+  %L = load i8, i8* %0
   store i8 -101, i8* %0
   %E = extractelement <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, i32 0
   %Shuff = shufflevector <8 x i64> zeroinitializer, <8 x i64> zeroinitializer, <8 x i32> <i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 undef, i32 1>
@@ -22,7 +22,7 @@ BB:
   %B = and i64 116376, 57247
   %FC = uitofp i8 7 to double
   %Sl = select i1 false, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
-  %L5 = load i8* %0
+  %L5 = load i8, i8* %0
   store i8 %L, i8* %0
   %E6 = extractelement <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, i32 3
   %Shuff7 = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 2, i32 4, i32 6, i32 0>
@@ -33,7 +33,7 @@ BB:
   br label %CF
 
 CF:                                               ; preds = %CF, %BB
-  %L11 = load i8* %0
+  %L11 = load i8, i8* %0
   store i8 -87, i8* %0
   %E12 = extractelement <4 x i64> zeroinitializer, i32 0
   %Shuff13 = shufflevector <8 x i64> zeroinitializer, <8 x i64> zeroinitializer, <8 x i32> <i32 7, i32 9, i32 11, i32 13, i32 undef, i32 1, i32 3, i32 5>
@@ -45,7 +45,7 @@ CF:                                               ; preds = %CF, %BB
   br i1 %Cmp18, label %CF, label %CF80
 
 CF80:                                             ; preds = %CF80, %CF88, %CF
-  %L19 = load i8* %0
+  %L19 = load i8, i8* %0
   store i8 -101, i8* %0
   %E20 = extractelement <4 x i64> zeroinitializer, i32 0
   %Shuff21 = shufflevector <4 x i64> zeroinitializer, <4 x i64> %Shuff7, <4 x i32> <i32 7, i32 1, i32 3, i32 5>
@@ -56,7 +56,7 @@ CF80:                                             ; preds = %CF80, %CF88, %CF
   br i1 %Cmp25, label %CF80, label %CF83
 
 CF83:                                             ; preds = %CF83, %CF80
-  %L26 = load i8* %0
+  %L26 = load i8, i8* %0
   store i8 -87, i8* %0
   %E27 = extractelement <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, i32 0
   %Shuff28 = shufflevector <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 7, i32 1, i32 3, i32 5>
@@ -68,7 +68,7 @@ CF83:                                             ; preds = %CF83, %CF80
   br i1 %Cmp33, label %CF83, label %CF88
 
 CF88:                                             ; preds = %CF83
-  %L34 = load i8* %0
+  %L34 = load i8, i8* %0
   store i8 -87, i8* %0
   %E35 = extractelement <8 x i64> %Shuff, i32 7
   %Shuff36 = shufflevector <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %Shuff28, <4 x i32> <i32 2, i32 undef, i32 undef, i32 0>
@@ -80,7 +80,7 @@ CF88:                                             ; preds = %CF83
   br i1 %Cmp40, label %CF80, label %CF81
 
 CF81:                                             ; preds = %CF81, %CF85, %CF87, %CF88
-  %L41 = load i8* %0
+  %L41 = load i8, i8* %0
   store i8 %L34, i8* %0
   %E42 = extractelement <8 x i64> %Shuff13, i32 6
   %Shuff43 = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 7>
@@ -92,7 +92,7 @@ CF81:                                             ; preds = %CF81, %CF85, %CF87,
   br i1 %Cmp47, label %CF81, label %CF85
 
 CF85:                                             ; preds = %CF81
-  %L48 = load i8* %0
+  %L48 = load i8, i8* %0
   store i8 -101, i8* %0
   %E49 = extractelement <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, i32 2
   %Shuff50 = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 5, i32 7, i32 1, i32 3>
@@ -101,7 +101,7 @@ CF85:                                             ; preds = %CF81
   %FC53 = uitofp i8 %L48 to double
   %Sl54 = select i1 %Cmp47, i32 %3, i32 %Sl24
   %Cmp55 = icmp ne <8 x i64> %Shuff13, zeroinitializer
-  %L56 = load i8* %0
+  %L56 = load i8, i8* %0
   store i8 %L11, i8* %0
   %E57 = extractelement <4 x i64> %Shuff21, i32 1
   %Shuff58 = shufflevector <8 x i64> %Shuff, <8 x i64> zeroinitializer, <8 x i32> <i32 4, i32 6, i32 undef, i32 10, i32 12, i32 undef, i32 0, i32 2>
@@ -113,7 +113,7 @@ CF85:                                             ; preds = %CF81
 CF84:                                             ; preds = %CF84, %CF85
   %Sl62 = select i1 false, i8 %L, i8 %L48
   %Cmp63 = icmp ne <8 x i64> %I, zeroinitializer
-  %L64 = load i8* %0
+  %L64 = load i8, i8* %0
   store i8 %5, i8* %0
   %E65 = extractelement <8 x i1> %Cmp55, i32 0
   br i1 %E65, label %CF84, label %CF87
@@ -125,7 +125,7 @@ CF87:                                             ; preds = %CF84
   %ZE69 = zext <8 x i8> %Sl32 to <8 x i64>
   %Sl70 = select i1 %Tr61, i64 %E20, i64 %E12
   %Cmp71 = icmp slt <8 x i64> %I, %Shuff
-  %L72 = load i8* %0
+  %L72 = load i8, i8* %0
   store i8 %L72, i8* %0
   %E73 = extractelement <8 x i1> %Cmp55, i32 6
   br i1 %E73, label %CF81, label %CF82
diff --git a/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll b/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll
index 96547d90cb40..6f338107825e 100644
--- a/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll
+++ b/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll
@@ -14,7 +14,7 @@ BB:
   %A2 = alloca double
   %A1 = alloca float
   %A = alloca double
-  %L = load i8* %0
+  %L = load i8, i8* %0
   store i8 -123, i8* %0
   %E = extractelement <4 x i64> zeroinitializer, i32 1
   %Shuff = shufflevector <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -22,7 +22,7 @@ BB:
   %BC = bitcast i64 181325 to double
   %Sl = select i1 false, <2 x i32> zeroinitializer, <2 x i32> zeroinitializer
   %Cmp = icmp ne <4 x i64> zeroinitializer, zeroinitializer
-  %L5 = load i8* %0
+  %L5 = load i8, i8* %0
   store i8 %L, i8* %0
   %E6 = extractelement <4 x i64> zeroinitializer, i32 3
   %Shuff7 = shufflevector <2 x i16> zeroinitializer, <2 x i16> zeroinitializer, <2 x i32> <i32 2, i32 0>
@@ -33,7 +33,7 @@ BB:
   br label %CF80
 
 CF80:                                             ; preds = %BB
-  %L11 = load i8* %0
+  %L11 = load i8, i8* %0
   store i8 -123, i8* %0
   %E12 = extractelement <2 x i16> zeroinitializer, i32 1
   %Shuff13 = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -42,7 +42,7 @@ CF80:                                             ; preds = %BB
   %PC = bitcast i1* %A4 to i64*
   %Sl16 = select i1 %Cmp10, <4 x i32> zeroinitializer, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
   %Cmp17 = icmp ule <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %Sl16
-  %L18 = load double* %A2
+  %L18 = load double, double* %A2
   store i64 498254, i64* %PC
   %E19 = extractelement <4 x i64> zeroinitializer, i32 0
   %Shuff20 = shufflevector <2 x i1> zeroinitializer, <2 x i1> %I, <2 x i32> <i32 3, i32 1>
@@ -51,7 +51,7 @@ CF80:                                             ; preds = %BB
   %ZE = zext <2 x i1> %Shuff20 to <2 x i32>
   %Sl23 = select i1 %Cmp10, <2 x i1> %Shuff20, <2 x i1> zeroinitializer
   %Cmp24 = icmp ult <2 x i32> zeroinitializer, zeroinitializer
-  %L25 = load i8* %0
+  %L25 = load i8, i8* %0
   store i8 %L25, i8* %0
   %E26 = extractelement <4 x i8> <i8 -1, i8 -1, i8 -1, i8 -1>, i32 3
   %Shuff27 = shufflevector <4 x i32> %Shuff, <4 x i32> %I14, <4 x i32> <i32 6, i32 0, i32 undef, i32 4>
@@ -63,7 +63,7 @@ CF80:                                             ; preds = %BB
 CF79:                                             ; preds = %CF80
   %Sl30 = select i1 false, i8 %B29, i8 -123
   %Cmp31 = icmp sge <2 x i1> %I, %I
-  %L32 = load i64* %PC
+  %L32 = load i64, i64* %PC
   store i8 -123, i8* %0
   %E33 = extractelement <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, i32 2
   %Shuff34 = shufflevector <4 x i64> zeroinitializer, <4 x i64> %Shuff13, <4 x i32> <i32 5, i32 7, i32 1, i32 3>
@@ -75,7 +75,7 @@ CF79:                                             ; preds = %CF80
   br label %CF
 
 CF:                                               ; preds = %CF, %CF79
-  %L40 = load double* %A
+  %L40 = load double, double* %A
   store i1 %Cmp39, i1* %PC37
   %E41 = extractelement <4 x i64> zeroinitializer, i32 3
   %Shuff42 = shufflevector <2 x i32> zeroinitializer, <2 x i32> %ZE, <2 x i32> <i32 2, i32 undef>
@@ -90,7 +90,7 @@ CF77:                                             ; preds = %CF77, %CF
   br i1 %Cmp46, label %CF77, label %CF78
 
 CF78:                                             ; preds = %CF78, %CF83, %CF82, %CF77
-  %L47 = load i64* %PC
+  %L47 = load i64, i64* %PC
   store i8 -123, i8* %0
   %E48 = extractelement <4 x i64> zeroinitializer, i32 3
   %Shuff49 = shufflevector <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> zeroinitializer, <4 x i32> <i32 2, i32 4, i32 6, i32 undef>
@@ -105,7 +105,7 @@ CF83:                                             ; preds = %CF78
   br i1 %Cmp54, label %CF78, label %CF82
 
 CF82:                                             ; preds = %CF83
-  %L55 = load i64* %PC
+  %L55 = load i64, i64* %PC
   store i64 %L32, i64* %PC
   %E56 = extractelement <2 x i16> %Shuff7, i32 1
   %Shuff57 = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 2, i32 4, i32 6, i32 0>
@@ -114,7 +114,7 @@ CF82:                                             ; preds = %CF83
   %FC = sitofp i64 498254 to double
   %Sl60 = select i1 false, i64 %E6, i64 -1
   %Cmp61 = icmp sgt <4 x i32> %Shuff27, %I43
-  %L62 = load i64* %PC
+  %L62 = load i64, i64* %PC
   store i64 %Sl9, i64* %PC
   %E63 = extractelement <2 x i32> %ZE, i32 0
   %Shuff64 = shufflevector <4 x i64> zeroinitializer, <4 x i64> %Shuff13, <4 x i32> <i32 1, i32 3, i32 undef, i32 7>
@@ -126,7 +126,7 @@ CF82:                                             ; preds = %CF83
 
 CF81:                                             ; preds = %CF82
   %Cmp69 = icmp ne <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, %B36
-  %L70 = load i8* %0
+  %L70 = load i8, i8* %0
   store i64 %L55, i64* %PC
   %E71 = extractelement <4 x i32> %Shuff49, i32 1
   %Shuff72 = shufflevector <4 x i64> zeroinitializer, <4 x i64> %Shuff34, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
diff --git a/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll b/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll
index bef75f3645c8..181f72abd378 100644
--- a/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll
+++ b/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll
@@ -14,7 +14,7 @@ BB:
   %A2 = alloca float
   %A1 = alloca double
   %A = alloca double
-  %L = load i8* %0
+  %L = load i8, i8* %0
   store i8 97, i8* %0
   %E = extractelement <16 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, i32 14
   %Shuff = shufflevector <2 x i1> zeroinitializer, <2 x i1> zeroinitializer, <2 x i32> <i32 1, i32 3>
@@ -22,7 +22,7 @@ BB:
   %Tr = trunc <1 x i64> zeroinitializer to <1 x i8>
   %Sl = select i1 false, double* %A1, double* %A
   %Cmp = icmp ne <2 x i64> zeroinitializer, zeroinitializer
-  %L5 = load double* %Sl
+  %L5 = load double, double* %Sl
   store float -4.374162e+06, float* %A2
   %E6 = extractelement <4 x i64> zeroinitializer, i32 3
   %Shuff7 = shufflevector <4 x i64> zeroinitializer, <4 x i64> %I, <4 x i32> <i32 2, i32 4, i32 6, i32 undef>
@@ -34,7 +34,7 @@ BB:
   br label %CF72
 
 CF72:                                             ; preds = %CF72, %CF80, %CF78, %BB
-  %L11 = load double* %Sl
+  %L11 = load double, double* %Sl
   store double 0.000000e+00, double* %Sl
   %E12 = extractelement <2 x i1> zeroinitializer, i32 0
   br i1 %E12, label %CF72, label %CF80
@@ -49,7 +49,7 @@ CF80:                                             ; preds = %CF72
   br i1 %Cmp17, label %CF72, label %CF77
 
 CF77:                                             ; preds = %CF77, %CF80
-  %L18 = load double* %Sl
+  %L18 = load double, double* %Sl
   store double 0.000000e+00, double* %Sl
   %E19 = extractelement <2 x i1> zeroinitializer, i32 0
   br i1 %E19, label %CF77, label %CF78
@@ -60,7 +60,7 @@ CF78:                                             ; preds = %CF77
   %B22 = sdiv <4 x i64> %Shuff7, zeroinitializer
   %FC = uitofp i8 97 to double
   %Sl23 = select i1 %Cmp10, <2 x i1> zeroinitializer, <2 x i1> zeroinitializer
-  %L24 = load double* %Sl
+  %L24 = load double, double* %Sl
   store float %Sl16, float* %PC
   %E25 = extractelement <2 x i1> %Shuff, i32 1
   br i1 %E25, label %CF72, label %CF76
@@ -71,7 +71,7 @@ CF76:                                             ; preds = %CF78
   %B28 = mul <4 x i64> %I27, zeroinitializer
   %ZE = zext <8 x i1> zeroinitializer to <8 x i64>
   %Sl29 = select i1 %Cmp17, float -4.374162e+06, float -4.374162e+06
-  %L30 = load i8* %0
+  %L30 = load i8, i8* %0
   store double %L5, double* %Sl
   %E31 = extractelement <8 x i1> zeroinitializer, i32 5
   br label %CF
@@ -85,7 +85,7 @@ CF:                                               ; preds = %CF, %CF81, %CF76
   br i1 %Cmp36, label %CF, label %CF74
 
 CF74:                                             ; preds = %CF74, %CF
-  %L37 = load float* %PC
+  %L37 = load float, float* %PC
   store double 0.000000e+00, double* %Sl
   %E38 = extractelement <2 x i1> %Sl23, i32 1
   br i1 %E38, label %CF74, label %CF75
@@ -95,7 +95,7 @@ CF75:                                             ; preds = %CF75, %CF82, %CF74
   %I40 = insertelement <4 x i64> zeroinitializer, i64 %4, i32 2
   %Sl41 = select i1 %Cmp10, i32 0, i32 %3
   %Cmp42 = icmp ne <1 x i64> zeroinitializer, zeroinitializer
-  %L43 = load double* %Sl
+  %L43 = load double, double* %Sl
   store i64 %4, i64* %2
   %E44 = extractelement <2 x i1> %Shuff20, i32 1
   br i1 %E44, label %CF75, label %CF82
@@ -109,7 +109,7 @@ CF82:                                             ; preds = %CF75
   br i1 %Cmp49, label %CF75, label %CF81
 
 CF81:                                             ; preds = %CF82
-  %L50 = load i8* %0
+  %L50 = load i8, i8* %0
   store double %L43, double* %Sl
   %E51 = extractelement <4 x i64> %Shuff7, i32 3
   %Shuff52 = shufflevector <4 x float> %BC34, <4 x float> %BC34, <4 x i32> <i32 2, i32 4, i32 6, i32 0>
@@ -117,7 +117,7 @@ CF81:                                             ; preds = %CF82
   %B54 = fdiv double %L24, %L43
   %BC55 = bitcast <4 x i64> zeroinitializer to <4 x double>
   %Sl56 = select i1 false, i8 %5, i8 97
-  %L57 = load i8* %0
+  %L57 = load i8, i8* %0
   store i8 %L50, i8* %0
   %E58 = extractelement <2 x i1> %Shuff20, i32 1
   br i1 %E58, label %CF, label %CF73
@@ -129,7 +129,7 @@ CF73:                                             ; preds = %CF73, %CF81
   %PC62 = bitcast double* %A3 to float*
   %Sl63 = select i1 %Cmp10, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer
   %Cmp64 = icmp ne <2 x i1> %Cmp, %Shuff
-  %L65 = load double* %A1
+  %L65 = load double, double* %A1
   store float -4.374162e+06, float* %PC62
   %E66 = extractelement <8 x i1> %I21, i32 3
   br i1 %E66, label %CF73, label %CF79
diff --git a/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll b/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
index 697871df797d..c0bc90563484 100644
--- a/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
+++ b/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
@@ -14,7 +14,7 @@ BB:
   %A2 = alloca <1 x double>
   %A1 = alloca <8 x double>
   %A = alloca i64
-  %L = load i8* %0
+  %L = load i8, i8* %0
   store i64 33695, i64* %A
   %E = extractelement <4 x i32> zeroinitializer, i32 3
   %Shuff = shufflevector <2 x i32> <i32 -1, i32 -1>, <2 x i32> <i32 -1, i32 -1>, <2 x i32> <i32 2, i32 0>
@@ -22,7 +22,7 @@ BB:
   %B = lshr <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
   %ZE = fpext float 0x3B64A2B880000000 to double
   %Sl = select i1 true, i16 -1, i16 -11642
-  %L5 = load i8* %0
+  %L5 = load i8, i8* %0
   store i8 0, i8* %0
   %E6 = extractelement <4 x i32> zeroinitializer, i32 2
   %Shuff7 = shufflevector <8 x i1> zeroinitializer, <8 x i1> zeroinitializer, <8 x i32> <i32 undef, i32 7, i32 9, i32 11, i32 13, i32 15, i32 1, i32 undef>
@@ -31,7 +31,7 @@ BB:
   %BC = bitcast <2 x i32> <i32 -1, i32 -1> to <2 x float>
   %Sl10 = select i1 true, i32* %1, i32* %1
   %Cmp = icmp sge <8 x i64> zeroinitializer, zeroinitializer
-  %L11 = load i32* %Sl10
+  %L11 = load i32, i32* %Sl10
   store <1 x double> zeroinitializer, <1 x double>* %A2
   %E12 = extractelement <4 x i16> zeroinitializer, i32 0
   %Shuff13 = shufflevector <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, <1 x i32> undef
@@ -43,7 +43,7 @@ BB:
   br label %CF75
 
 CF75:                                             ; preds = %CF75, %BB
-  %L19 = load i32* %Sl10
+  %L19 = load i32, i32* %Sl10
   store i32 %L11, i32* %Sl10
   %E20 = extractelement <4 x i32> zeroinitializer, i32 1
   %Shuff21 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %I8, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
@@ -55,7 +55,7 @@ CF75:                                             ; preds = %CF75, %BB
   br i1 %Cmp26, label %CF75, label %CF76
 
 CF76:                                             ; preds = %CF75
-  %L27 = load i32* %Sl10
+  %L27 = load i32, i32* %Sl10
   store i32 439732, i32* %Sl10
   %E28 = extractelement <4 x i32> %Shuff21, i32 3
   %Shuff29 = shufflevector <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <8 x i32> <i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0>
@@ -65,7 +65,7 @@ CF76:                                             ; preds = %CF75
   br label %CF74
 
 CF74:                                             ; preds = %CF74, %CF80, %CF78, %CF76
-  %L33 = load i64* %2
+  %L33 = load i64, i64* %2
   store i32 71140, i32* %Sl10
   %E34 = extractelement <4 x i32> zeroinitializer, i32 1
   %Shuff35 = shufflevector <1 x i16> zeroinitializer, <1 x i16> zeroinitializer, <1 x i32> undef
@@ -76,7 +76,7 @@ CF74:                                             ; preds = %CF74, %CF80, %CF78,
   br i1 %Cmp39, label %CF74, label %CF80
 
 CF80:                                             ; preds = %CF74
-  %L40 = load i8* %0
+  %L40 = load i8, i8* %0
   store i32 0, i32* %Sl10
   %E41 = extractelement <8 x i64> zeroinitializer, i32 1
   %Shuff42 = shufflevector <1 x i16> %I14, <1 x i16> %I14, <1 x i32> undef
@@ -86,7 +86,7 @@ CF80:                                             ; preds = %CF74
   br i1 %Sl44, label %CF74, label %CF78
 
 CF78:                                             ; preds = %CF80
-  %L45 = load i32* %Sl10
+  %L45 = load i32, i32* %Sl10
   store i8 %L5, i8* %0
   %E46 = extractelement <8 x i1> %Shuff7, i32 2
   br i1 %E46, label %CF74, label %CF77
@@ -101,7 +101,7 @@ CF77:                                             ; preds = %CF77, %CF78
   br i1 %Cmp52, label %CF77, label %CF79
 
 CF79:                                             ; preds = %CF77
-  %L53 = load i32* %Sl10
+  %L53 = load i32, i32* %Sl10
   store i8 %L40, i8* %0
   %E54 = extractelement <4 x i32> zeroinitializer, i32 1
   %Shuff55 = shufflevector <4 x i32> %Shuff21, <4 x i32> %I8, <4 x i32> <i32 4, i32 6, i32 undef, i32 2>
@@ -109,7 +109,7 @@ CF79:                                             ; preds = %CF77
   %Tr = trunc <1 x i64> %Shuff13 to <1 x i16>
   %Sl57 = select i1 %Cmp18, <2 x i32> <i32 -1, i32 -1>, <2 x i32> <i32 -1, i32 -1>
   %Cmp58 = icmp uge <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %I56
-  %L59 = load i8* %0
+  %L59 = load i8, i8* %0
   store <1 x double> zeroinitializer, <1 x double>* %A2
   %E60 = extractelement <4 x i32> zeroinitializer, i32 0
   %Shuff61 = shufflevector <4 x i32> %I8, <4 x i32> %I8, <4 x i32> <i32 undef, i32 1, i32 undef, i32 undef>
@@ -121,7 +121,7 @@ CF79:                                             ; preds = %CF77
   br label %CF
 
 CF:                                               ; preds = %CF79
-  %L66 = load i32* %Sl10
+  %L66 = load i32, i32* %Sl10
   store i32 %E6, i32* %PC
   %E67 = extractelement <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, i32 2
   %Shuff68 = shufflevector <4 x i32> %Sl64, <4 x i32> %I8, <4 x i32> <i32 5, i32 undef, i32 1, i32 undef>
diff --git a/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll b/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
index dc4200ad4285..a3150e9a67d5 100644
--- a/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
+++ b/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
@@ -14,14 +14,14 @@ BB:
   %A2 = alloca <4 x i1>
   %A1 = alloca <4 x i16>
   %A = alloca <2 x i32>
-  %L = load i8* %0
+  %L = load i8, i8* %0
   store i8 %L, i8* %0
   %E = extractelement <4 x i32> zeroinitializer, i32 0
   %Shuff = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 undef, i32 1, i32 3, i32 5>
   %I = insertelement <2 x i1> zeroinitializer, i1 false, i32 1
   %FC = sitofp <4 x i32> zeroinitializer to <4 x double>
   %Sl = select i1 false, <4 x i64> %Shuff, <4 x i64> %Shuff
-  %L5 = load i8* %0
+  %L5 = load i8, i8* %0
   store i8 %5, i8* %0
   %E6 = extractelement <1 x i16> zeroinitializer, i32 0
   %Shuff7 = shufflevector <2 x i1> %I, <2 x i1> %I, <2 x i32> <i32 1, i32 undef>
@@ -30,7 +30,7 @@ BB:
   %FC9 = fptoui float 0x406DB70180000000 to i64
   %Sl10 = select i1 false, <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
   %Cmp = icmp ult <4 x i64> zeroinitializer, zeroinitializer
-  %L11 = load i8* %0
+  %L11 = load i8, i8* %0
   store i8 %L, i8* %0
   %E12 = extractelement <4 x i64> zeroinitializer, i32 2
   %Shuff13 = shufflevector <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <4 x i32> <i32 5, i32 7, i32 undef, i32 3>
@@ -42,7 +42,7 @@ BB:
   br label %CF
 
 CF:                                               ; preds = %CF, %CF79, %CF84, %BB
-  %L18 = load i8* %0
+  %L18 = load i8, i8* %0
   store i8 %L, i8* %0
   %E19 = extractelement <4 x i64> %Sl, i32 3
   %Shuff20 = shufflevector <2 x i1> %Shuff7, <2 x i1> %I, <2 x i32> <i32 2, i32 0>
@@ -54,7 +54,7 @@ CF:                                               ; preds = %CF, %CF79, %CF84, %
   br i1 %Cmp25, label %CF, label %CF79
 
 CF79:                                             ; preds = %CF
-  %L26 = load i8* %0
+  %L26 = load i8, i8* %0
   store i8 %L26, i8* %0
   %E27 = extractelement <1 x i16> zeroinitializer, i32 0
   %Shuff28 = shufflevector <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11>
@@ -65,7 +65,7 @@ CF79:                                             ; preds = %CF
   br i1 %Cmp32, label %CF, label %CF78
 
 CF78:                                             ; preds = %CF78, %CF79
-  %L33 = load i8* %0
+  %L33 = load i8, i8* %0
   store i8 %L, i8* %0
   %E34 = extractelement <16 x i32> %Shuff28, i32 1
   %Shuff35 = shufflevector <4 x i64> zeroinitializer, <4 x i64> %I21, <4 x i32> <i32 undef, i32 6, i32 0, i32 2>
@@ -76,7 +76,7 @@ CF78:                                             ; preds = %CF78, %CF79
   br i1 %Cmp38, label %CF78, label %CF80
 
 CF80:                                             ; preds = %CF80, %CF82, %CF78
-  %L39 = load i8* %0
+  %L39 = load i8, i8* %0
   store i8 %L, i8* %0
   %E40 = extractelement <2 x i1> %Shuff20, i32 1
   br i1 %E40, label %CF80, label %CF82
@@ -87,7 +87,7 @@ CF82:                                             ; preds = %CF80
   %B43 = sub i32 %E, 0
   %Sl44 = select i1 %Cmp32, <16 x i32> %Shuff28, <16 x i32> %Shuff28
   %Cmp45 = icmp sgt <4 x i64> zeroinitializer, %I21
-  %L46 = load i8* %0
+  %L46 = load i8, i8* %0
   store i8 %L11, i8* %0
   %E47 = extractelement <8 x i32> %Sl16, i32 4
   %Shuff48 = shufflevector <2 x i1> zeroinitializer, <2 x i1> %Shuff7, <2 x i32> <i32 undef, i32 1>
@@ -99,7 +99,7 @@ CF82:                                             ; preds = %CF80
 CF81:                                             ; preds = %CF81, %CF82
   %Sl52 = select i1 false, float -6.749110e+06, float 0x406DB70180000000
   %Cmp53 = icmp uge <2 x i32> <i32 -1, i32 -1>, <i32 -1, i32 -1>
-  %L54 = load i8* %0
+  %L54 = load i8, i8* %0
   store i8 %L5, i8* %0
   %E55 = extractelement <8 x i32> zeroinitializer, i32 7
   %Shuff56 = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 undef, i32 4, i32 6, i32 0>
@@ -108,7 +108,7 @@ CF81:                                             ; preds = %CF81, %CF82
   %FC59 = fptoui <4 x double> %I36 to <4 x i16>
   %Sl60 = select i1 %Cmp17, <2 x i1> %I, <2 x i1> %I57
   %Cmp61 = icmp ule <8 x i32> %B50, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
-  %L62 = load i8* %0
+  %L62 = load i8, i8* %0
   store i8 %L33, i8* %0
   %E63 = extractelement <4 x i64> %Shuff, i32 2
   %Shuff64 = shufflevector <4 x i64> %Shuff56, <4 x i64> %Shuff56, <4 x i32> <i32 5, i32 7, i32 1, i32 undef>
@@ -126,7 +126,7 @@ CF84:                                             ; preds = %CF83
   br i1 %Cmp69, label %CF, label %CF77
 
 CF77:                                             ; preds = %CF84
-  %L70 = load i8* %0
+  %L70 = load i8, i8* %0
   store i8 %L, i8* %0
   %E71 = extractelement <4 x i64> %Shuff, i32 0
   %Shuff72 = shufflevector <2 x i1> zeroinitializer, <2 x i1> %I, <2 x i32> <i32 3, i32 1>
diff --git a/test/CodeGen/Mips/msa/shuffle.ll b/test/CodeGen/Mips/msa/shuffle.ll
index faeec5d58dd4..aadff7d5a5c8 100644
--- a/test/CodeGen/Mips/msa/shuffle.ll
+++ b/test/CodeGen/Mips/msa/shuffle.ll
@@ -2,9 +2,9 @@
 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
 
 define void @vshf_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
-  ; CHECK: vshf_v16i8_0:
+  ; CHECK-LABEL: vshf_v16i8_0:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
@@ -14,13 +14,12 @@ define void @vshf_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind
   ; CHECK-DAG: st.b [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v16i8_0
 }
 
 define void @vshf_v16i8_1(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
-  ; CHECK: vshf_v16i8_1:
+  ; CHECK-LABEL: vshf_v16i8_1:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
   ; CHECK-DAG: splati.b [[R3:\$w[0-9]+]], [[R1]][1]
@@ -28,14 +27,13 @@ define void @vshf_v16i8_1(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind
   ; CHECK-DAG: st.b [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v16i8_1
 }
 
 define void @vshf_v16i8_2(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
-  ; CHECK: vshf_v16i8_2:
+  ; CHECK-LABEL: vshf_v16i8_2:
 
-  %1 = load <16 x i8>* %a
-  %2 = load <16 x i8>* %b
+  %1 = load <16 x i8>, <16 x i8>* %a
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <16 x i8> %1, <16 x i8> %2, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 16>
   ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
@@ -45,15 +43,14 @@ define void @vshf_v16i8_2(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind
   ; CHECK-DAG: st.b [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v16i8_2
 }
 
 define void @vshf_v16i8_3(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
-  ; CHECK: vshf_v16i8_3:
+  ; CHECK-LABEL: vshf_v16i8_3:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <16 x i8> %1, <16 x i8> %2, <16 x i32> <i32 17, i32 24, i32 25, i32 18, i32 19, i32 20, i32 28, i32 19, i32 1, i32 8, i32 9, i32 2, i32 3, i32 4, i32 12, i32 3>
   ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
@@ -65,13 +62,12 @@ define void @vshf_v16i8_3(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind
   ; CHECK-DAG: st.b [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v16i8_3
 }
 
 define void @vshf_v16i8_4(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
-  ; CHECK: vshf_v16i8_4:
+  ; CHECK-LABEL: vshf_v16i8_4:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <16 x i8> %1, <16 x i8> %1, <16 x i32> <i32 1, i32 17, i32 1, i32 17, i32 1, i32 17, i32 1, i32 17, i32 1, i32 17, i32 1, i32 17, i32 1, i32 17, i32 1, i32 17>
   ; CHECK-DAG: splati.b [[R3:\$w[0-9]+]], [[R1]][1]
@@ -79,13 +75,12 @@ define void @vshf_v16i8_4(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind
   ; CHECK-DAG: st.b [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v16i8_4
 }
 
 define void @vshf_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
-  ; CHECK: vshf_v8i16_0:
+  ; CHECK-LABEL: vshf_v8i16_0:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
@@ -95,13 +90,12 @@ define void @vshf_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind
   ; CHECK-DAG: st.h [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v8i16_0
 }
 
 define void @vshf_v8i16_1(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
-  ; CHECK: vshf_v8i16_1:
+  ; CHECK-LABEL: vshf_v8i16_1:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
   ; CHECK-DAG: splati.h [[R3:\$w[0-9]+]], [[R1]][1]
@@ -109,14 +103,13 @@ define void @vshf_v8i16_1(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind
   ; CHECK-DAG: st.h [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v8i16_1
 }
 
 define void @vshf_v8i16_2(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
-  ; CHECK: vshf_v8i16_2:
+  ; CHECK-LABEL: vshf_v8i16_2:
 
-  %1 = load <8 x i16>* %a
-  %2 = load <8 x i16>* %b
+  %1 = load <8 x i16>, <8 x i16>* %a
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8>
   ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
@@ -126,15 +119,14 @@ define void @vshf_v8i16_2(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind
   ; CHECK-DAG: st.h [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v8i16_2
 }
 
 define void @vshf_v8i16_3(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
-  ; CHECK: vshf_v8i16_3:
+  ; CHECK-LABEL: vshf_v8i16_3:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 1, i32 8, i32 9, i32 2, i32 3, i32 4, i32 12, i32 3>
   ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
@@ -146,13 +138,12 @@ define void @vshf_v8i16_3(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind
   ; CHECK-DAG: st.h [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v8i16_3
 }
 
 define void @vshf_v8i16_4(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
-  ; CHECK: vshf_v8i16_4:
+  ; CHECK-LABEL: vshf_v8i16_4:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <8 x i16> %1, <8 x i16> %1, <8 x i32> <i32 1, i32 9, i32 1, i32 9, i32 1, i32 9, i32 1, i32 9>
   ; CHECK-DAG: splati.h [[R3:\$w[0-9]+]], [[R1]][1]
@@ -160,16 +151,15 @@ define void @vshf_v8i16_4(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind
   ; CHECK-DAG: st.h [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v8i16_4
 }
 
 ; Note: v4i32 only has one 4-element set so it's impossible to get a vshf.w
 ; instruction when using a single vector.
 
 define void @vshf_v4i32_0(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
-  ; CHECK: vshf_v4i32_0:
+  ; CHECK-LABEL: vshf_v4i32_0:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   ; CHECK-DAG: shf.w [[R3:\$w[0-9]+]], [[R1]], 27
@@ -177,28 +167,26 @@ define void @vshf_v4i32_0(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind
   ; CHECK-DAG: st.w [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v4i32_0
 }
 
 define void @vshf_v4i32_1(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
-  ; CHECK: vshf_v4i32_1:
+  ; CHECK-LABEL: vshf_v4i32_1:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
-  ; CHECK-DAG: shf.w [[R3:\$w[0-9]+]], [[R1]], 85
+  ; CHECK-DAG: splati.w [[R3:\$w[0-9]+]], [[R1]][1]
   store <4 x i32> %2, <4 x i32>* %c
   ; CHECK-DAG: st.w [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v4i32_1
 }
 
 define void @vshf_v4i32_2(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
-  ; CHECK: vshf_v4i32_2:
+  ; CHECK-LABEL: vshf_v4i32_2:
 
-  %1 = load <4 x i32>* %a
-  %2 = load <4 x i32>* %b
+  %1 = load <4 x i32>, <4 x i32>* %a
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 4>
   ; CHECK-DAG: shf.w [[R3:\$w[0-9]+]], [[R2]], 36
@@ -206,15 +194,14 @@ define void @vshf_v4i32_2(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind
   ; CHECK-DAG: st.w [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v4i32_2
 }
 
 define void @vshf_v4i32_3(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
-  ; CHECK: vshf_v4i32_3:
+  ; CHECK-LABEL: vshf_v4i32_3:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 1, i32 5, i32 6, i32 4>
   ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
@@ -226,27 +213,26 @@ define void @vshf_v4i32_3(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind
   ; CHECK-DAG: st.w [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v4i32_3
 }
 
 define void @vshf_v4i32_4(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
-  ; CHECK: vshf_v4i32_4:
+  ; CHECK-LABEL: vshf_v4i32_4:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <4 x i32> %1, <4 x i32> %1, <4 x i32> <i32 1, i32 5, i32 5, i32 1>
-  ; CHECK-DAG: shf.w [[R3:\$w[0-9]+]], [[R1]], 85
+  ; The two operand vectors are the same so element 1 and 5 are equivalent.
+  ; CHECK-DAG: splati.w [[R3:\$w[0-9]+]], [[R1]][1]
   store <4 x i32> %2, <4 x i32>* %c
   ; CHECK-DAG: st.w [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v4i32_4
 }
 
 define void @vshf_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
-  ; CHECK: vshf_v2i64_0:
+  ; CHECK-LABEL: vshf_v2i64_0:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
   ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
@@ -256,13 +242,12 @@ define void @vshf_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
   ; CHECK-DAG: st.d [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v2i64_0
 }
 
 define void @vshf_v2i64_1(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
-  ; CHECK: vshf_v2i64_1:
+  ; CHECK-LABEL: vshf_v2i64_1:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
   ; CHECK-DAG: splati.d [[R3:\$w[0-9]+]], [[R1]][1]
@@ -270,14 +255,13 @@ define void @vshf_v2i64_1(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
   ; CHECK-DAG: st.d [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v2i64_1
 }
 
 define void @vshf_v2i64_2(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
-  ; CHECK: vshf_v2i64_2:
+  ; CHECK-LABEL: vshf_v2i64_2:
 
-  %1 = load <2 x i64>* %a
-  %2 = load <2 x i64>* %b
+  %1 = load <2 x i64>, <2 x i64>* %a
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 3, i32 2>
   ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
@@ -287,15 +271,14 @@ define void @vshf_v2i64_2(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
   ; CHECK-DAG: st.d [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v2i64_2
 }
 
 define void @vshf_v2i64_3(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
-  ; CHECK: vshf_v2i64_3:
+  ; CHECK-LABEL: vshf_v2i64_3:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 1, i32 2>
   ; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
@@ -307,13 +290,12 @@ define void @vshf_v2i64_3(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
   ; CHECK-DAG: st.d [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v2i64_3
 }
 
 define void @vshf_v2i64_4(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
-  ; CHECK: vshf_v2i64_4:
+  ; CHECK-LABEL: vshf_v2i64_4:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <2 x i64> %1, <2 x i64> %1, <2 x i32> <i32 1, i32 3>
   ; CHECK-DAG: splati.d [[R3:\$w[0-9]+]], [[R1]][1]
@@ -321,13 +303,12 @@ define void @vshf_v2i64_4(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
   ; CHECK-DAG: st.d [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size vshf_v2i64_4
 }
 
 define void @shf_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
-  ; CHECK: shf_v16i8_0:
+  ; CHECK-LABEL: shf_v16i8_0:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> <i32 1, i32 3, i32 2, i32 0, i32 5, i32 7, i32 6, i32 4, i32 9, i32 11, i32 10, i32 8, i32 13, i32 15, i32 14, i32 12>
   ; CHECK-DAG: shf.b [[R3:\$w[0-9]+]], [[R1]], 45
@@ -335,13 +316,12 @@ define void @shf_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK-DAG: st.b [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size shf_v16i8_0
 }
 
 define void @shf_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
-  ; CHECK: shf_v8i16_0:
+  ; CHECK-LABEL: shf_v8i16_0:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
   ; CHECK-DAG: shf.h [[R3:\$w[0-9]+]], [[R1]], 27
@@ -349,13 +329,12 @@ define void @shf_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
   ; CHECK-DAG: st.h [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size shf_v8i16_0
 }
 
 define void @shf_v4i32_0(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
-  ; CHECK: shf_v4i32_0:
+  ; CHECK-LABEL: shf_v4i32_0:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   ; CHECK-DAG: shf.w [[R3:\$w[0-9]+]], [[R1]], 27
@@ -363,82 +342,194 @@ define void @shf_v4i32_0(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
   ; CHECK-DAG: st.w [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size shf_v4i32_0
 }
 
 ; shf.d does not exist
 
 define void @ilvev_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
-  ; CHECK: ilvev_v16i8_0:
+  ; CHECK-LABEL: ilvev_v16i8_0:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
                      <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
-  ; CHECK-DAG: ilvev.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: ilvev.b [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <16 x i8> %3, <16 x i8>* %c
   ; CHECK-DAG: st.b [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvev_v16i8_0
 }
 
 define void @ilvev_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
-  ; CHECK: ilvev_v8i16_0:
+  ; CHECK-LABEL: ilvev_v8i16_0:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
-  ; CHECK-DAG: ilvev.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: ilvev.h [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <8 x i16> %3, <8 x i16>* %c
   ; CHECK-DAG: st.h [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvev_v8i16_0
 }
 
 define void @ilvev_v4i32_0(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
-  ; CHECK: ilvev_v4i32_0:
+  ; CHECK-LABEL: ilvev_v4i32_0:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-  ; CHECK-DAG: ilvev.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: ilvev.w [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <4 x i32> %3, <4 x i32>* %c
   ; CHECK-DAG: st.w [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvev_v4i32_0
 }
 
 define void @ilvev_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
-  ; CHECK: ilvev_v2i64_0:
+  ; CHECK-LABEL: ilvev_v2i64_0:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 2>
-  ; CHECK-DAG: ilvev.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: ilvev.d [[R3:\$w[0-9]+]], [[R2]], [[R1]]
+  store <2 x i64> %3, <2 x i64>* %c
+  ; CHECK-DAG: st.d [[R3]], 0($4)
+
+  ret void
+}
+
+; Interleaving one operand with itself.
+define void @ilvev_v16i8_1(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+  ; CHECK-LABEL: ilvev_v16i8_1:
+
+  %1 = load <16 x i8>, <16 x i8>* %a
+  ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <16 x i8>, <16 x i8>* %b
+  %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
+                     <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
+  ; CHECK-DAG: ilvev.b [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <16 x i8> %3, <16 x i8>* %c
+  ; CHECK-DAG: st.b [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvev_v8i16_1(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+  ; CHECK-LABEL: ilvev_v8i16_1:
+
+  %1 = load <8 x i16>, <8 x i16>* %a
+  ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <8 x i16>, <8 x i16>* %b
+  %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
+  ; CHECK-DAG: ilvev.h [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <8 x i16> %3, <8 x i16>* %c
+  ; CHECK-DAG: st.h [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvev_v4i32_1(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+  ; CHECK-LABEL: ilvev_v4i32_1:
+
+  %1 = load <4 x i32>, <4 x i32>* %a
+  ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <4 x i32>, <4 x i32>* %b
+  %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
+  ; CHECK-DAG: ilvev.w [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <4 x i32> %3, <4 x i32>* %c
+  ; CHECK-DAG: st.w [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvev_v2i64_1(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+  ; CHECK-LABEL: ilvev_v2i64_1:
+
+  %1 = load <2 x i64>, <2 x i64>* %a
+  ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <2 x i64>, <2 x i64>* %b
+  %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 0>
+  ; ilvev.d with two identical operands is equivalent to splati.d
+  ; CHECK-DAG: splati.d [[R3:\$w[0-9]+]], [[R1]][0]
+  store <2 x i64> %3, <2 x i64>* %c
+  ; CHECK-DAG: st.d [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvev_v16i8_2(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+  ; CHECK-LABEL: ilvev_v16i8_2:
+
+  %1 = load <16 x i8>, <16 x i8>* %a
+  %2 = load <16 x i8>, <16 x i8>* %b
+  ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
+                     <16 x i32> <i32 16, i32 16, i32 18, i32 18, i32 20, i32 20, i32 22, i32 22, i32 24, i32 24, i32 26, i32 26, i32 28, i32 28, i32 30, i32 30>
+  ; CHECK-DAG: ilvev.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <16 x i8> %3, <16 x i8>* %c
+  ; CHECK-DAG: st.b [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvev_v8i16_2(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+  ; CHECK-LABEL: ilvev_v8i16_2:
+
+  %1 = load <8 x i16>, <8 x i16>* %a
+  %2 = load <8 x i16>, <8 x i16>* %b
+  ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
+  ; CHECK-DAG: ilvev.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <8 x i16> %3, <8 x i16>* %c
+  ; CHECK-DAG: st.h [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvev_v4i32_2(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+  ; CHECK-LABEL: ilvev_v4i32_2:
+
+  %1 = load <4 x i32>, <4 x i32>* %a
+  %2 = load <4 x i32>, <4 x i32>* %b
+  ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 4, i32 4, i32 6, i32 6>
+  ; CHECK-DAG: ilvev.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <4 x i32> %3, <4 x i32>* %c
+  ; CHECK-DAG: st.w [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvev_v2i64_2(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+  ; CHECK-LABEL: ilvev_v2i64_2:
+
+  %1 = load <2 x i64>, <2 x i64>* %a
+  %2 = load <2 x i64>, <2 x i64>* %b
+  ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 2, i32 2>
+  ; ilvev.d with two identical operands is equivalent to splati.d
+  ; CHECK-DAG: splati.d [[R3:\$w[0-9]+]], [[R2]][0]
   store <2 x i64> %3, <2 x i64>* %c
   ; CHECK-DAG: st.d [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvev_v2i64_0
 }
 
 define void @ilvod_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
-  ; CHECK: ilvod_v16i8_0:
+  ; CHECK-LABEL: ilvod_v16i8_0:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
                      <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
@@ -447,15 +538,14 @@ define void @ilvod_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind
   ; CHECK-DAG: st.b [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvod_v16i8_0
 }
 
 define void @ilvod_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
-  ; CHECK: ilvod_v8i16_0:
+  ; CHECK-LABEL: ilvod_v8i16_0:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
   ; CHECK-DAG: ilvod.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -463,15 +553,14 @@ define void @ilvod_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind
   ; CHECK-DAG: st.h [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvod_v8i16_0
 }
 
 define void @ilvod_v4i32_0(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
-  ; CHECK: ilvod_v4i32_0:
+  ; CHECK-LABEL: ilvod_v4i32_0:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
   ; CHECK-DAG: ilvod.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -479,15 +568,14 @@ define void @ilvod_v4i32_0(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind
   ; CHECK-DAG: st.w [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvod_v4i32_0
 }
 
 define void @ilvod_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
-  ; CHECK: ilvod_v2i64_0:
+  ; CHECK-LABEL: ilvod_v2i64_0:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 1, i32 3>
   ; CHECK-DAG: ilvod.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -495,262 +583,710 @@ define void @ilvod_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
   ; CHECK-DAG: st.d [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvod_v2i64_0
 }
 
-define void @ilvl_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
-  ; CHECK: ilvl_v16i8_0:
+define void @ilvod_v16i8_1(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+  ; CHECK-LABEL: ilvod_v16i8_1:
+
+  %1 = load <16 x i8>, <16 x i8>* %a
+  ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <16 x i8>, <16 x i8>* %b
+  %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
+                     <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
+  ; CHECK-DAG: ilvod.b [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <16 x i8> %3, <16 x i8>* %c
+  ; CHECK-DAG: st.b [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvod_v8i16_1(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+  ; CHECK-LABEL: ilvod_v8i16_1:
+
+  %1 = load <8 x i16>, <8 x i16>* %a
+  ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <8 x i16>, <8 x i16>* %b
+  %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
+  ; CHECK-DAG: ilvod.h [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <8 x i16> %3, <8 x i16>* %c
+  ; CHECK-DAG: st.h [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvod_v4i32_1(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+  ; CHECK-LABEL: ilvod_v4i32_1:
+
+  %1 = load <4 x i32>, <4 x i32>* %a
+  ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <4 x i32>, <4 x i32>* %b
+  %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
+  ; CHECK-DAG: ilvod.w [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <4 x i32> %3, <4 x i32>* %c
+  ; CHECK-DAG: st.w [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvod_v2i64_1(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+  ; CHECK-LABEL: ilvod_v2i64_1:
+
+  %1 = load <2 x i64>, <2 x i64>* %a
+  ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <2 x i64>, <2 x i64>* %b
+  %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 1, i32 1>
+  ; ilvod.d with two identical operands is equivalent to splati.d
+  ; CHECK-DAG: splati.d [[R3:\$w[0-9]+]], [[R1]][1]
+  store <2 x i64> %3, <2 x i64>* %c
+  ; CHECK-DAG: st.d [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvod_v16i8_2(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+  ; CHECK-LABEL: ilvod_v16i8_2:
+
+  %1 = load <16 x i8>, <16 x i8>* %a
+  %2 = load <16 x i8>, <16 x i8>* %b
+  ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
+                     <16 x i32> <i32 17, i32 17, i32 19, i32 19, i32 21, i32 21, i32 23, i32 23, i32 25, i32 25, i32 27, i32 27, i32 29, i32 29, i32 31, i32 31>
+  ; CHECK-DAG: ilvod.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <16 x i8> %3, <16 x i8>* %c
+  ; CHECK-DAG: st.b [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvod_v8i16_2(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+  ; CHECK-LABEL: ilvod_v8i16_2:
+
+  %1 = load <8 x i16>, <8 x i16>* %a
+  %2 = load <8 x i16>, <8 x i16>* %b
+  ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
+  ; CHECK-DAG: ilvod.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <8 x i16> %3, <8 x i16>* %c
+  ; CHECK-DAG: st.h [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvod_v4i32_2(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+  ; CHECK-LABEL: ilvod_v4i32_2:
+
+  %1 = load <4 x i32>, <4 x i32>* %a
+  %2 = load <4 x i32>, <4 x i32>* %b
+  ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 5, i32 5, i32 7, i32 7>
+  ; CHECK-DAG: ilvod.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <4 x i32> %3, <4 x i32>* %c
+  ; CHECK-DAG: st.w [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvod_v2i64_2(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+  ; CHECK-LABEL: ilvod_v2i64_2:
+
+  %1 = load <2 x i64>, <2 x i64>* %a
+  %2 = load <2 x i64>, <2 x i64>* %b
+  ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 3, i32 3>
+  ; ilvod.d with two identical operands is equivalent to splati.d
+  ; CHECK-DAG: splati.d [[R3:\$w[0-9]+]], [[R2]][1]
+  store <2 x i64> %3, <2 x i64>* %c
+  ; CHECK-DAG: st.d [[R3]], 0($4)
 
-  %1 = load <16 x i8>* %a
+  ret void
+}
+
+define void @ilvr_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+  ; CHECK-LABEL: ilvr_v16i8_0:
+
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
                      <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
-  ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: ilvr.b [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <16 x i8> %3, <16 x i8>* %c
   ; CHECK-DAG: st.b [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvl_v16i8_0
 }
 
-define void @ilvl_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
-  ; CHECK: ilvl_v8i16_0:
+define void @ilvr_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+  ; CHECK-LABEL: ilvr_v8i16_0:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
-  ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: ilvr.h [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <8 x i16> %3, <8 x i16>* %c
   ; CHECK-DAG: st.h [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvl_v8i16_0
 }
 
-define void @ilvl_v4i32_0(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
-  ; CHECK: ilvl_v4i32_0:
+define void @ilvr_v4i32_0(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+  ; CHECK-LABEL: ilvr_v4i32_0:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
-  ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: ilvr.w [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <4 x i32> %3, <4 x i32>* %c
   ; CHECK-DAG: st.w [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvl_v4i32_0
 }
 
-define void @ilvl_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
-  ; CHECK: ilvl_v2i64_0:
+define void @ilvr_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+  ; CHECK-LABEL: ilvr_v2i64_0:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 2>
-  ; ilvl.d and ilvev.d are equivalent for v2i64
-  ; CHECK-DAG: ilvev.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; ilvr.d and ilvev.d are equivalent for v2i64
+  ; CHECK-DAG: ilvev.d [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <2 x i64> %3, <2 x i64>* %c
   ; CHECK-DAG: st.d [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvl_v2i64_0
 }
 
-define void @ilvr_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
-  ; CHECK: ilvr_v16i8_0:
+define void @ilvr_v16i8_1(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+  ; CHECK-LABEL: ilvr_v16i8_1:
+
+  %1 = load <16 x i8>, <16 x i8>* %a
+  %2 = load <16 x i8>, <16 x i8>* %b
+  ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
+                     <16 x i32> <i32 16, i32 16, i32 17, i32 17, i32 18, i32 18, i32 19, i32 19, i32 20, i32 20, i32 21, i32 21, i32 22, i32 22, i32 23, i32 23>
+  ; CHECK-DAG: ilvr.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <16 x i8> %3, <16 x i8>* %c
+  ; CHECK-DAG: st.b [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvr_v8i16_1(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+  ; CHECK-LABEL: ilvr_v8i16_1:
+
+  %1 = load <8 x i16>, <8 x i16>* %a
+  %2 = load <8 x i16>, <8 x i16>* %b
+  ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 8, i32 8, i32 9, i32 9, i32 10, i32 10, i32 11, i32 11>
+  ; CHECK-DAG: ilvr.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <8 x i16> %3, <8 x i16>* %c
+  ; CHECK-DAG: st.h [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvr_v4i32_1(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+  ; CHECK-LABEL: ilvr_v4i32_1:
+
+  %1 = load <4 x i32>, <4 x i32>* %a
+  %2 = load <4 x i32>, <4 x i32>* %b
+  ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 4, i32 4, i32 5, i32 5>
+  ; CHECK-DAG: ilvr.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <4 x i32> %3, <4 x i32>* %c
+  ; CHECK-DAG: st.w [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvr_v2i64_1(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+  ; CHECK-LABEL: ilvr_v2i64_1:
+
+  %1 = load <2 x i64>, <2 x i64>* %a
+  %2 = load <2 x i64>, <2 x i64>* %b
+  ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 2, i32 2>
+  ; ilvr.d and splati.d are equivalent for v2i64
+  ; CHECK-DAG: splati.d [[R3:\$w[0-9]+]], [[R2]][0]
+  store <2 x i64> %3, <2 x i64>* %c
+  ; CHECK-DAG: st.d [[R3]], 0($4)
 
-  %1 = load <16 x i8>* %a
+  ret void
+}
+
+define void @ilvr_v16i8_2(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+  ; CHECK-LABEL: ilvr_v16i8_2:
+
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
+  %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
+                     <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>
+  ; CHECK-DAG: ilvr.b [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <16 x i8> %3, <16 x i8>* %c
+  ; CHECK-DAG: st.b [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvr_v8i16_2(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+  ; CHECK-LABEL: ilvr_v8i16_2:
+
+  %1 = load <8 x i16>, <8 x i16>* %a
+  ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <8 x i16>, <8 x i16>* %b
+  %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3>
+  ; CHECK-DAG: ilvr.h [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <8 x i16> %3, <8 x i16>* %c
+  ; CHECK-DAG: st.h [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvr_v4i32_2(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+  ; CHECK-LABEL: ilvr_v4i32_2:
+
+  %1 = load <4 x i32>, <4 x i32>* %a
+  ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <4 x i32>, <4 x i32>* %b
+  %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
+  ; CHECK-DAG: ilvr.w [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <4 x i32> %3, <4 x i32>* %c
+  ; CHECK-DAG: st.w [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvr_v2i64_2(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+  ; CHECK-LABEL: ilvr_v2i64_2:
+
+  %1 = load <2 x i64>, <2 x i64>* %a
+  ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <2 x i64>, <2 x i64>* %b
+  %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 0>
+  ; ilvr.d and splati.d are equivalent for v2i64
+  ; CHECK-DAG: splati.d [[R3:\$w[0-9]+]], [[R1]][0]
+  store <2 x i64> %3, <2 x i64>* %c
+  ; CHECK-DAG: st.d [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvl_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+  ; CHECK-LABEL: ilvl_v16i8_0:
+
+  %1 = load <16 x i8>, <16 x i8>* %a
+  ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
                      <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
-  ; CHECK-DAG: ilvr.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <16 x i8> %3, <16 x i8>* %c
   ; CHECK-DAG: st.b [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvr_v16i8_0
 }
 
-define void @ilvr_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
-  ; CHECK: ilvr_v8i16_0:
+define void @ilvl_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+  ; CHECK-LABEL: ilvl_v8i16_0:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
-  ; CHECK-DAG: ilvr.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <8 x i16> %3, <8 x i16>* %c
   ; CHECK-DAG: st.h [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvr_v8i16_0
 }
 
-define void @ilvr_v4i32_0(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
-  ; CHECK: ilvr_v4i32_0:
+define void @ilvl_v4i32_0(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+  ; CHECK-LABEL: ilvl_v4i32_0:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
-  ; CHECK-DAG: ilvr.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <4 x i32> %3, <4 x i32>* %c
   ; CHECK-DAG: st.w [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvr_v4i32_0
 }
 
-define void @ilvr_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
-  ; CHECK: ilvr_v2i64_0:
+define void @ilvl_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+  ; CHECK-LABEL: ilvl_v2i64_0:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 1, i32 3>
-  ; ilvr.d and ilvod.d are equivalent for v2i64
+  ; ilvl.d and ilvod.d are equivalent for v2i64
   ; CHECK-DAG: ilvod.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
   store <2 x i64> %3, <2 x i64>* %c
   ; CHECK-DAG: st.d [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size ilvr_v2i64_0
+}
+
+define void @ilvl_v16i8_1(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+  ; CHECK-LABEL: ilvl_v16i8_1:
+
+  %1 = load <16 x i8>, <16 x i8>* %a
+  %2 = load <16 x i8>, <16 x i8>* %b
+  ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
+                     <16 x i32> <i32 24, i32 24, i32 25, i32 25, i32 26, i32 26, i32 27, i32 27, i32 28, i32 28, i32 29, i32 29, i32 30, i32 30, i32 31, i32 31>
+  ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <16 x i8> %3, <16 x i8>* %c
+  ; CHECK-DAG: st.b [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvl_v8i16_1(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+  ; CHECK-LABEL: ilvl_v8i16_1:
+
+  %1 = load <8 x i16>, <8 x i16>* %a
+  %2 = load <8 x i16>, <8 x i16>* %b
+  ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 12, i32 12, i32 13, i32 13, i32 14, i32 14, i32 15, i32 15>
+  ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <8 x i16> %3, <8 x i16>* %c
+  ; CHECK-DAG: st.h [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvl_v4i32_1(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+  ; CHECK-LABEL: ilvl_v4i32_1:
+
+  %1 = load <4 x i32>, <4 x i32>* %a
+  %2 = load <4 x i32>, <4 x i32>* %b
+  ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 6, i32 6, i32 7, i32 7>
+  ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <4 x i32> %3, <4 x i32>* %c
+  ; CHECK-DAG: st.w [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvl_v2i64_1(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+  ; CHECK-LABEL: ilvl_v2i64_1:
+
+  %1 = load <2 x i64>, <2 x i64>* %a
+  %2 = load <2 x i64>, <2 x i64>* %b
+  ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 3, i32 3>
+  ; ilvl.d and splati.d are equivalent for v2i64
+  ; CHECK-DAG: splati.d [[R3:\$w[0-9]+]], [[R2]][1]
+  store <2 x i64> %3, <2 x i64>* %c
+  ; CHECK-DAG: st.d [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvl_v16i8_2(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+  ; CHECK-LABEL: ilvl_v16i8_2:
+
+  %1 = load <16 x i8>, <16 x i8>* %a
+  ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <16 x i8>, <16 x i8>* %b
+  %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
+                     <16 x i32> <i32 8, i32 8, i32 9, i32 9, i32 10, i32 10, i32 11, i32 11, i32 12, i32 12, i32 13, i32 13, i32 14, i32 14, i32 15, i32 15>
+  ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <16 x i8> %3, <16 x i8>* %c
+  ; CHECK-DAG: st.b [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvl_v8i16_2(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+  ; CHECK-LABEL: ilvl_v8i16_2:
+
+  %1 = load <8 x i16>, <8 x i16>* %a
+  ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <8 x i16>, <8 x i16>* %b
+  %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>
+  ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <8 x i16> %3, <8 x i16>* %c
+  ; CHECK-DAG: st.h [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvl_v4i32_2(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+  ; CHECK-LABEL: ilvl_v4i32_2:
+
+  %1 = load <4 x i32>, <4 x i32>* %a
+  ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <4 x i32>, <4 x i32>* %b
+  %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
+  ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <4 x i32> %3, <4 x i32>* %c
+  ; CHECK-DAG: st.w [[R3]], 0($4)
+
+  ret void
+}
+
+define void @ilvl_v2i64_2(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+  ; CHECK-LABEL: ilvl_v2i64_2:
+
+  %1 = load <2 x i64>, <2 x i64>* %a
+  ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <2 x i64>, <2 x i64>* %b
+  %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 1, i32 1>
+  ; ilvl.d and splati.d are equivalent for v2i64
+  ; CHECK-DAG: splati.d [[R3:\$w[0-9]+]], [[R1]][1]
+  store <2 x i64> %3, <2 x i64>* %c
+  ; CHECK-DAG: st.d [[R3]], 0($4)
+
+  ret void
 }
 
 define void @pckev_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
-  ; CHECK: pckev_v16i8_0:
+  ; CHECK-LABEL: pckev_v16i8_0:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
                      <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
-  ; CHECK-DAG: pckev.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: pckev.b [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <16 x i8> %3, <16 x i8>* %c
   ; CHECK-DAG: st.b [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size pckev_v16i8_0
 }
 
 define void @pckev_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
-  ; CHECK: pckev_v8i16_0:
+  ; CHECK-LABEL: pckev_v8i16_0:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
-  ; CHECK-DAG: pckev.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: pckev.h [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <8 x i16> %3, <8 x i16>* %c
   ; CHECK-DAG: st.h [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size pckev_v8i16_0
 }
 
 define void @pckev_v4i32_0(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
-  ; CHECK: pckev_v4i32_0:
+  ; CHECK-LABEL: pckev_v4i32_0:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
-  ; CHECK-DAG: pckev.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: pckev.w [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <4 x i32> %3, <4 x i32>* %c
   ; CHECK-DAG: st.w [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size pckev_v4i32_0
 }
 
 define void @pckev_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
-  ; CHECK: pckev_v2i64_0:
+  ; CHECK-LABEL: pckev_v2i64_0:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 2>
   ; pckev.d and ilvev.d are equivalent for v2i64
-  ; CHECK-DAG: ilvev.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: ilvev.d [[R3:\$w[0-9]+]], [[R2]], [[R1]]
+  store <2 x i64> %3, <2 x i64>* %c
+  ; CHECK-DAG: st.d [[R3]], 0($4)
+
+  ret void
+}
+
+define void @pckev_v16i8_1(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+  ; CHECK-LABEL: pckev_v16i8_1:
+
+  %1 = load <16 x i8>, <16 x i8>* %a
+  %2 = load <16 x i8>, <16 x i8>* %b
+  ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
+                     <16 x i32> <i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
+  ; CHECK-DAG: pckev.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <16 x i8> %3, <16 x i8>* %c
+  ; CHECK-DAG: st.b [[R3]], 0($4)
+
+  ret void
+}
+
+define void @pckev_v8i16_1(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+  ; CHECK-LABEL: pckev_v8i16_1:
+
+  %1 = load <8 x i16>, <8 x i16>* %a
+  %2 = load <8 x i16>, <8 x i16>* %b
+  ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 8, i32 10, i32 12, i32 14, i32 8, i32 10, i32 12, i32 14>
+  ; CHECK-DAG: pckev.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <8 x i16> %3, <8 x i16>* %c
+  ; CHECK-DAG: st.h [[R3]], 0($4)
+
+  ret void
+}
+
+define void @pckev_v4i32_1(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+  ; CHECK-LABEL: pckev_v4i32_1:
+
+  %1 = load <4 x i32>, <4 x i32>* %a
+  %2 = load <4 x i32>, <4 x i32>* %b
+  ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 4, i32 6, i32 4, i32 6>
+  ; CHECK-DAG: pckev.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <4 x i32> %3, <4 x i32>* %c
+  ; CHECK-DAG: st.w [[R3]], 0($4)
+
+  ret void
+}
+
+define void @pckev_v2i64_1(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+  ; CHECK-LABEL: pckev_v2i64_1:
+
+  %1 = load <2 x i64>, <2 x i64>* %a
+  %2 = load <2 x i64>, <2 x i64>* %b
+  ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 2, i32 2>
+  ; pckev.d and splati.d are equivalent for v2i64
+  ; CHECK-DAG: splati.d [[R3:\$w[0-9]+]], [[R2]][0]
+  store <2 x i64> %3, <2 x i64>* %c
+  ; CHECK-DAG: st.d [[R3]], 0($4)
+
+  ret void
+}
+
+define void @pckev_v16i8_2(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+  ; CHECK-LABEL: pckev_v16i8_2:
+
+  %1 = load <16 x i8>, <16 x i8>* %a
+  ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <16 x i8>, <16 x i8>* %b
+  %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
+                     <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+  ; CHECK-DAG: pckev.b [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <16 x i8> %3, <16 x i8>* %c
+  ; CHECK-DAG: st.b [[R3]], 0($4)
+
+  ret void
+}
+
+define void @pckev_v8i16_2(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+  ; CHECK-LABEL: pckev_v8i16_2:
+
+  %1 = load <8 x i16>, <8 x i16>* %a
+  ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <8 x i16>, <8 x i16>* %b
+  %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 0, i32 2, i32 4, i32 6>
+  ; CHECK-DAG: pckev.h [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <8 x i16> %3, <8 x i16>* %c
+  ; CHECK-DAG: st.h [[R3]], 0($4)
+
+  ret void
+}
+
+define void @pckev_v4i32_2(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+  ; CHECK-LABEL: pckev_v4i32_2:
+
+  %1 = load <4 x i32>, <4 x i32>* %a
+  ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <4 x i32>, <4 x i32>* %b
+  %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
+  ; CHECK-DAG: pckev.w [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <4 x i32> %3, <4 x i32>* %c
+  ; CHECK-DAG: st.w [[R3]], 0($4)
+
+  ret void
+}
+
+define void @pckev_v2i64_2(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+  ; CHECK-LABEL: pckev_v2i64_2:
+
+  %1 = load <2 x i64>, <2 x i64>* %a
+  ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <2 x i64>, <2 x i64>* %b
+  %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 0>
+  ; pckev.d and splati.d are equivalent for v2i64
+  ; CHECK-DAG: splati.d [[R3:\$w[0-9]+]], [[R1]][0]
   store <2 x i64> %3, <2 x i64>* %c
   ; CHECK-DAG: st.d [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size pckev_v2i64_0
 }
 
 define void @pckod_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
-  ; CHECK: pckod_v16i8_0:
+  ; CHECK-LABEL: pckod_v16i8_0:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <16 x i8>* %b
+  %2 = load <16 x i8>, <16 x i8>* %b
   ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
                      <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
-  ; CHECK-DAG: pckod.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: pckod.b [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <16 x i8> %3, <16 x i8>* %c
   ; CHECK-DAG: st.b [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size pckod_v16i8_0
 }
 
 define void @pckod_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
-  ; CHECK: pckod_v8i16_0:
+  ; CHECK-LABEL: pckod_v8i16_0:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <8 x i16>* %b
+  %2 = load <8 x i16>, <8 x i16>* %b
   ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
-  ; CHECK-DAG: pckod.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: pckod.h [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <8 x i16> %3, <8 x i16>* %c
   ; CHECK-DAG: st.h [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size pckod_v8i16_0
 }
 
 define void @pckod_v4i32_0(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
-  ; CHECK: pckod_v4i32_0:
+  ; CHECK-LABEL: pckod_v4i32_0:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <4 x i32>* %b
+  %2 = load <4 x i32>, <4 x i32>* %b
   ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
-  ; CHECK-DAG: pckod.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+  ; CHECK-DAG: pckod.w [[R3:\$w[0-9]+]], [[R2]], [[R1]]
   store <4 x i32> %3, <4 x i32>* %c
   ; CHECK-DAG: st.w [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size pckod_v4i32_0
 }
 
 define void @pckod_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
-  ; CHECK: pckod_v2i64_0:
+  ; CHECK-LABEL: pckod_v2i64_0:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = load <2 x i64>* %b
+  %2 = load <2 x i64>, <2 x i64>* %b
   ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
   %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 1, i32 3>
   ; pckod.d and ilvod.d are equivalent for v2i64
@@ -759,13 +1295,128 @@ define void @pckod_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
   ; CHECK-DAG: st.d [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size pckod_v2i64_0
+}
+
+define void @pckod_v16i8_1(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+  ; CHECK-LABEL: pckod_v16i8_1:
+
+  %1 = load <16 x i8>, <16 x i8>* %a
+  %2 = load <16 x i8>, <16 x i8>* %b
+  ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
+                     <16 x i32> <i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
+  ; CHECK-DAG: pckod.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <16 x i8> %3, <16 x i8>* %c
+  ; CHECK-DAG: st.b [[R3]], 0($4)
+
+  ret void
+}
+
+define void @pckod_v8i16_1(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+  ; CHECK-LABEL: pckod_v8i16_1:
+
+  %1 = load <8 x i16>, <8 x i16>* %a
+  %2 = load <8 x i16>, <8 x i16>* %b
+  ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 9, i32 11, i32 13, i32 15, i32 9, i32 11, i32 13, i32 15>
+  ; CHECK-DAG: pckod.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <8 x i16> %3, <8 x i16>* %c
+  ; CHECK-DAG: st.h [[R3]], 0($4)
+
+  ret void
+}
+
+define void @pckod_v4i32_1(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+  ; CHECK-LABEL: pckod_v4i32_1:
+
+  %1 = load <4 x i32>, <4 x i32>* %a
+  %2 = load <4 x i32>, <4 x i32>* %b
+  ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 5, i32 7, i32 5, i32 7>
+  ; CHECK-DAG: pckod.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]
+  store <4 x i32> %3, <4 x i32>* %c
+  ; CHECK-DAG: st.w [[R3]], 0($4)
+
+  ret void
+}
+
+define void @pckod_v2i64_1(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+  ; CHECK-LABEL: pckod_v2i64_1:
+
+  %1 = load <2 x i64>, <2 x i64>* %a
+  %2 = load <2 x i64>, <2 x i64>* %b
+  ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
+  %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 3, i32 3>
+  ; pckod.d and splati.d are equivalent for v2i64
+  ; CHECK-DAG: splati.d [[R3:\$w[0-9]+]], [[R2]][1]
+  store <2 x i64> %3, <2 x i64>* %c
+  ; CHECK-DAG: st.d [[R3]], 0($4)
+
+  ret void
+}
+
+define void @pckod_v16i8_2(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+  ; CHECK-LABEL: pckod_v16i8_2:
+
+  %1 = load <16 x i8>, <16 x i8>* %a
+  ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <16 x i8>, <16 x i8>* %b
+  %3 = shufflevector <16 x i8> %1, <16 x i8> %2,
+                     <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+  ; CHECK-DAG: pckod.b [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <16 x i8> %3, <16 x i8>* %c
+  ; CHECK-DAG: st.b [[R3]], 0($4)
+
+  ret void
+}
+
+define void @pckod_v8i16_2(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+  ; CHECK-LABEL: pckod_v8i16_2:
+
+  %1 = load <8 x i16>, <8 x i16>* %a
+  ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <8 x i16>, <8 x i16>* %b
+  %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 1, i32 3, i32 5, i32 7>
+  ; CHECK-DAG: pckod.h [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <8 x i16> %3, <8 x i16>* %c
+  ; CHECK-DAG: st.h [[R3]], 0($4)
+
+  ret void
+}
+
+define void @pckod_v4i32_2(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+  ; CHECK-LABEL: pckod_v4i32_2:
+
+  %1 = load <4 x i32>, <4 x i32>* %a
+  ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <4 x i32>, <4 x i32>* %b
+  %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 1, i32 3, i32 1, i32 3>
+  ; CHECK-DAG: pckod.w [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+  store <4 x i32> %3, <4 x i32>* %c
+  ; CHECK-DAG: st.w [[R3]], 0($4)
+
+  ret void
+}
+
+define void @pckod_v2i64_2(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+  ; CHECK-LABEL: pckod_v2i64_2:
+
+  %1 = load <2 x i64>, <2 x i64>* %a
+  ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+  %2 = load <2 x i64>, <2 x i64>* %b
+  %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 1, i32 1>
+  ; pckod.d and splati.d are equivalent for v2i64
+  ; CHECK-DAG: splati.d [[R3:\$w[0-9]+]], [[R1]][1]
+  store <2 x i64> %3, <2 x i64>* %c
+  ; CHECK-DAG: st.d [[R3]], 0($4)
+
+  ret void
 }
 
 define void @splati_v16i8_0(<16 x i8>* %c, <16 x i8>* %a) nounwind {
-  ; CHECK: splati_v16i8_0:
+  ; CHECK-LABEL: splati_v16i8_0:
 
-  %1 = load <16 x i8>* %a
+  %1 = load <16 x i8>, <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <16 x i8> %1, <16 x i8> undef,
                      <16 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
@@ -774,13 +1425,12 @@ define void @splati_v16i8_0(<16 x i8>* %c, <16 x i8>* %a) nounwind {
   ; CHECK-DAG: st.b [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size splati_v16i8_0
 }
 
 define void @splati_v8i16_0(<8 x i16>* %c, <8 x i16>* %a) nounwind {
-  ; CHECK: splati_v8i16_0:
+  ; CHECK-LABEL: splati_v8i16_0:
 
-  %1 = load <8 x i16>* %a
+  %1 = load <8 x i16>, <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
   ; CHECK-DAG: splati.h [[R3:\$w[0-9]+]], [[R1]][4]
@@ -788,28 +1438,25 @@ define void @splati_v8i16_0(<8 x i16>* %c, <8 x i16>* %a) nounwind {
   ; CHECK-DAG: st.h [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size splati_v8i16_0
 }
 
 define void @splati_v4i32_0(<4 x i32>* %c, <4 x i32>* %a) nounwind {
-  ; CHECK: splati_v4i32_0:
+  ; CHECK-LABEL: splati_v4i32_0:
 
-  %1 = load <4 x i32>* %a
+  %1 = load <4 x i32>, <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
-  ; shf.w and splati.w are equivalent
-  ; CHECK-DAG: shf.w [[R3:\$w[0-9]+]], [[R1]], 255
+  ; CHECK-DAG: splati.w [[R3:\$w[0-9]+]], [[R1]][3]
   store <4 x i32> %2, <4 x i32>* %c
   ; CHECK-DAG: st.w [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size splati_v4i32_0
 }
 
 define void @splati_v2i64_0(<2 x i64>* %c, <2 x i64>* %a) nounwind {
-  ; CHECK: splati_v2i64_0:
+  ; CHECK-LABEL: splati_v2i64_0:
 
-  %1 = load <2 x i64>* %a
+  %1 = load <2 x i64>, <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
   %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
   ; CHECK-DAG: splati.d [[R3:\$w[0-9]+]], [[R1]][1]
@@ -817,5 +1464,4 @@ define void @splati_v2i64_0(<2 x i64>* %c, <2 x i64>* %a) nounwind {
   ; CHECK-DAG: st.d [[R3]], 0($4)
 
   ret void
-  ; CHECK: .size splati_v2i64_0
 }
diff --git a/test/CodeGen/Mips/msa/spill.ll b/test/CodeGen/Mips/msa/spill.ll
index 66f896ac4684..8c9a79912351 100644
--- a/test/CodeGen/Mips/msa/spill.ll
+++ b/test/CodeGen/Mips/msa/spill.ll
@@ -6,73 +6,73 @@
 
 define i32 @test_i8(<16 x i8>* %p0, <16 x i8>* %q1) nounwind {
 entry:
-  %p1  = getelementptr <16 x i8>* %p0, i32 1
-  %p2  = getelementptr <16 x i8>* %p0, i32 2
-  %p3  = getelementptr <16 x i8>* %p0, i32 3
-  %p4  = getelementptr <16 x i8>* %p0, i32 4
-  %p5  = getelementptr <16 x i8>* %p0, i32 5
-  %p6  = getelementptr <16 x i8>* %p0, i32 6
-  %p7  = getelementptr <16 x i8>* %p0, i32 7
-  %p8  = getelementptr <16 x i8>* %p0, i32 8
-  %p9  = getelementptr <16 x i8>* %p0, i32 9
-  %p10 = getelementptr <16 x i8>* %p0, i32 10
-  %p11 = getelementptr <16 x i8>* %p0, i32 11
-  %p12 = getelementptr <16 x i8>* %p0, i32 12
-  %p13 = getelementptr <16 x i8>* %p0, i32 13
-  %p14 = getelementptr <16 x i8>* %p0, i32 14
-  %p15 = getelementptr <16 x i8>* %p0, i32 15
-  %p16 = getelementptr <16 x i8>* %p0, i32 16
-  %p17 = getelementptr <16 x i8>* %p0, i32 17
-  %p18 = getelementptr <16 x i8>* %p0, i32 18
-  %p19 = getelementptr <16 x i8>* %p0, i32 19
-  %p20 = getelementptr <16 x i8>* %p0, i32 20
-  %p21 = getelementptr <16 x i8>* %p0, i32 21
-  %p22 = getelementptr <16 x i8>* %p0, i32 22
-  %p23 = getelementptr <16 x i8>* %p0, i32 23
-  %p24 = getelementptr <16 x i8>* %p0, i32 24
-  %p25 = getelementptr <16 x i8>* %p0, i32 25
-  %p26 = getelementptr <16 x i8>* %p0, i32 26
-  %p27 = getelementptr <16 x i8>* %p0, i32 27
-  %p28 = getelementptr <16 x i8>* %p0, i32 28
-  %p29 = getelementptr <16 x i8>* %p0, i32 29
-  %p30 = getelementptr <16 x i8>* %p0, i32 30
-  %p31 = getelementptr <16 x i8>* %p0, i32 31
-  %p32 = getelementptr <16 x i8>* %p0, i32 32
-  %p33 = getelementptr <16 x i8>* %p0, i32 33
-  %0  = load <16 x i8>* %p0, align 16
-  %1  = load <16 x i8>* %p1, align 16
-  %2  = load <16 x i8>* %p2, align 16
-  %3  = load <16 x i8>* %p3, align 16
-  %4  = load <16 x i8>* %p4, align 16
-  %5  = load <16 x i8>* %p5, align 16
-  %6  = load <16 x i8>* %p6, align 16
-  %7  = load <16 x i8>* %p7, align 16
-  %8  = load <16 x i8>* %p8, align 16
-  %9  = load <16 x i8>* %p9, align 16
-  %10 = load <16 x i8>* %p10, align 16
-  %11 = load <16 x i8>* %p11, align 16
-  %12 = load <16 x i8>* %p12, align 16
-  %13 = load <16 x i8>* %p13, align 16
-  %14 = load <16 x i8>* %p14, align 16
-  %15 = load <16 x i8>* %p15, align 16
-  %16 = load <16 x i8>* %p16, align 16
-  %17 = load <16 x i8>* %p17, align 16
-  %18 = load <16 x i8>* %p18, align 16
-  %19 = load <16 x i8>* %p19, align 16
-  %20 = load <16 x i8>* %p20, align 16
-  %21 = load <16 x i8>* %p21, align 16
-  %22 = load <16 x i8>* %p22, align 16
-  %23 = load <16 x i8>* %p23, align 16
-  %24 = load <16 x i8>* %p24, align 16
-  %25 = load <16 x i8>* %p25, align 16
-  %26 = load <16 x i8>* %p26, align 16
-  %27 = load <16 x i8>* %p27, align 16
-  %28 = load <16 x i8>* %p28, align 16
-  %29 = load <16 x i8>* %p29, align 16
-  %30 = load <16 x i8>* %p30, align 16
-  %31 = load <16 x i8>* %p31, align 16
-  %32 = load <16 x i8>* %p32, align 16
-  %33 = load <16 x i8>* %p33, align 16
+  %p1  = getelementptr <16 x i8>, <16 x i8>* %p0, i32 1
+  %p2  = getelementptr <16 x i8>, <16 x i8>* %p0, i32 2
+  %p3  = getelementptr <16 x i8>, <16 x i8>* %p0, i32 3
+  %p4  = getelementptr <16 x i8>, <16 x i8>* %p0, i32 4
+  %p5  = getelementptr <16 x i8>, <16 x i8>* %p0, i32 5
+  %p6  = getelementptr <16 x i8>, <16 x i8>* %p0, i32 6
+  %p7  = getelementptr <16 x i8>, <16 x i8>* %p0, i32 7
+  %p8  = getelementptr <16 x i8>, <16 x i8>* %p0, i32 8
+  %p9  = getelementptr <16 x i8>, <16 x i8>* %p0, i32 9
+  %p10 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 10
+  %p11 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 11
+  %p12 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 12
+  %p13 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 13
+  %p14 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 14
+  %p15 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 15
+  %p16 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 16
+  %p17 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 17
+  %p18 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 18
+  %p19 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 19
+  %p20 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 20
+  %p21 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 21
+  %p22 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 22
+  %p23 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 23
+  %p24 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 24
+  %p25 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 25
+  %p26 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 26
+  %p27 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 27
+  %p28 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 28
+  %p29 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 29
+  %p30 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 30
+  %p31 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 31
+  %p32 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 32
+  %p33 = getelementptr <16 x i8>, <16 x i8>* %p0, i32 33
+  %0  = load <16 x i8>, <16 x i8>* %p0, align 16
+  %1  = load <16 x i8>, <16 x i8>* %p1, align 16
+  %2  = load <16 x i8>, <16 x i8>* %p2, align 16
+  %3  = load <16 x i8>, <16 x i8>* %p3, align 16
+  %4  = load <16 x i8>, <16 x i8>* %p4, align 16
+  %5  = load <16 x i8>, <16 x i8>* %p5, align 16
+  %6  = load <16 x i8>, <16 x i8>* %p6, align 16
+  %7  = load <16 x i8>, <16 x i8>* %p7, align 16
+  %8  = load <16 x i8>, <16 x i8>* %p8, align 16
+  %9  = load <16 x i8>, <16 x i8>* %p9, align 16
+  %10 = load <16 x i8>, <16 x i8>* %p10, align 16
+  %11 = load <16 x i8>, <16 x i8>* %p11, align 16
+  %12 = load <16 x i8>, <16 x i8>* %p12, align 16
+  %13 = load <16 x i8>, <16 x i8>* %p13, align 16
+  %14 = load <16 x i8>, <16 x i8>* %p14, align 16
+  %15 = load <16 x i8>, <16 x i8>* %p15, align 16
+  %16 = load <16 x i8>, <16 x i8>* %p16, align 16
+  %17 = load <16 x i8>, <16 x i8>* %p17, align 16
+  %18 = load <16 x i8>, <16 x i8>* %p18, align 16
+  %19 = load <16 x i8>, <16 x i8>* %p19, align 16
+  %20 = load <16 x i8>, <16 x i8>* %p20, align 16
+  %21 = load <16 x i8>, <16 x i8>* %p21, align 16
+  %22 = load <16 x i8>, <16 x i8>* %p22, align 16
+  %23 = load <16 x i8>, <16 x i8>* %p23, align 16
+  %24 = load <16 x i8>, <16 x i8>* %p24, align 16
+  %25 = load <16 x i8>, <16 x i8>* %p25, align 16
+  %26 = load <16 x i8>, <16 x i8>* %p26, align 16
+  %27 = load <16 x i8>, <16 x i8>* %p27, align 16
+  %28 = load <16 x i8>, <16 x i8>* %p28, align 16
+  %29 = load <16 x i8>, <16 x i8>* %p29, align 16
+  %30 = load <16 x i8>, <16 x i8>* %p30, align 16
+  %31 = load <16 x i8>, <16 x i8>* %p31, align 16
+  %32 = load <16 x i8>, <16 x i8>* %p32, align 16
+  %33 = load <16 x i8>, <16 x i8>* %p33, align 16
   %r1  = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0,   <16 x i8> %1)
   %r2  = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r1,  <16 x i8> %2)
   %r3  = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r2,  <16 x i8> %3)
@@ -155,73 +155,73 @@ declare i32       @llvm.mips.copy.s.b(<16 x i8>, i32) nounwind
 
 define i32 @test_i16(<8 x i16>* %p0, <8 x i16>* %q1) nounwind {
 entry:
-  %p1  = getelementptr <8 x i16>* %p0, i32 1
-  %p2  = getelementptr <8 x i16>* %p0, i32 2
-  %p3  = getelementptr <8 x i16>* %p0, i32 3
-  %p4  = getelementptr <8 x i16>* %p0, i32 4
-  %p5  = getelementptr <8 x i16>* %p0, i32 5
-  %p6  = getelementptr <8 x i16>* %p0, i32 6
-  %p7  = getelementptr <8 x i16>* %p0, i32 7
-  %p8  = getelementptr <8 x i16>* %p0, i32 8
-  %p9  = getelementptr <8 x i16>* %p0, i32 9
-  %p10 = getelementptr <8 x i16>* %p0, i32 10
-  %p11 = getelementptr <8 x i16>* %p0, i32 11
-  %p12 = getelementptr <8 x i16>* %p0, i32 12
-  %p13 = getelementptr <8 x i16>* %p0, i32 13
-  %p14 = getelementptr <8 x i16>* %p0, i32 14
-  %p15 = getelementptr <8 x i16>* %p0, i32 15
-  %p16 = getelementptr <8 x i16>* %p0, i32 16
-  %p17 = getelementptr <8 x i16>* %p0, i32 17
-  %p18 = getelementptr <8 x i16>* %p0, i32 18
-  %p19 = getelementptr <8 x i16>* %p0, i32 19
-  %p20 = getelementptr <8 x i16>* %p0, i32 20
-  %p21 = getelementptr <8 x i16>* %p0, i32 21
-  %p22 = getelementptr <8 x i16>* %p0, i32 22
-  %p23 = getelementptr <8 x i16>* %p0, i32 23
-  %p24 = getelementptr <8 x i16>* %p0, i32 24
-  %p25 = getelementptr <8 x i16>* %p0, i32 25
-  %p26 = getelementptr <8 x i16>* %p0, i32 26
-  %p27 = getelementptr <8 x i16>* %p0, i32 27
-  %p28 = getelementptr <8 x i16>* %p0, i32 28
-  %p29 = getelementptr <8 x i16>* %p0, i32 29
-  %p30 = getelementptr <8 x i16>* %p0, i32 30
-  %p31 = getelementptr <8 x i16>* %p0, i32 31
-  %p32 = getelementptr <8 x i16>* %p0, i32 32
-  %p33 = getelementptr <8 x i16>* %p0, i32 33
-  %0  = load <8 x i16>* %p0, align 16
-  %1  = load <8 x i16>* %p1, align 16
-  %2  = load <8 x i16>* %p2, align 16
-  %3  = load <8 x i16>* %p3, align 16
-  %4  = load <8 x i16>* %p4, align 16
-  %5  = load <8 x i16>* %p5, align 16
-  %6  = load <8 x i16>* %p6, align 16
-  %7  = load <8 x i16>* %p7, align 16
-  %8  = load <8 x i16>* %p8, align 16
-  %9  = load <8 x i16>* %p9, align 16
-  %10 = load <8 x i16>* %p10, align 16
-  %11 = load <8 x i16>* %p11, align 16
-  %12 = load <8 x i16>* %p12, align 16
-  %13 = load <8 x i16>* %p13, align 16
-  %14 = load <8 x i16>* %p14, align 16
-  %15 = load <8 x i16>* %p15, align 16
-  %16 = load <8 x i16>* %p16, align 16
-  %17 = load <8 x i16>* %p17, align 16
-  %18 = load <8 x i16>* %p18, align 16
-  %19 = load <8 x i16>* %p19, align 16
-  %20 = load <8 x i16>* %p20, align 16
-  %21 = load <8 x i16>* %p21, align 16
-  %22 = load <8 x i16>* %p22, align 16
-  %23 = load <8 x i16>* %p23, align 16
-  %24 = load <8 x i16>* %p24, align 16
-  %25 = load <8 x i16>* %p25, align 16
-  %26 = load <8 x i16>* %p26, align 16
-  %27 = load <8 x i16>* %p27, align 16
-  %28 = load <8 x i16>* %p28, align 16
-  %29 = load <8 x i16>* %p29, align 16
-  %30 = load <8 x i16>* %p30, align 16
-  %31 = load <8 x i16>* %p31, align 16
-  %32 = load <8 x i16>* %p32, align 16
-  %33 = load <8 x i16>* %p33, align 16
+  %p1  = getelementptr <8 x i16>, <8 x i16>* %p0, i32 1
+  %p2  = getelementptr <8 x i16>, <8 x i16>* %p0, i32 2
+  %p3  = getelementptr <8 x i16>, <8 x i16>* %p0, i32 3
+  %p4  = getelementptr <8 x i16>, <8 x i16>* %p0, i32 4
+  %p5  = getelementptr <8 x i16>, <8 x i16>* %p0, i32 5
+  %p6  = getelementptr <8 x i16>, <8 x i16>* %p0, i32 6
+  %p7  = getelementptr <8 x i16>, <8 x i16>* %p0, i32 7
+  %p8  = getelementptr <8 x i16>, <8 x i16>* %p0, i32 8
+  %p9  = getelementptr <8 x i16>, <8 x i16>* %p0, i32 9
+  %p10 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 10
+  %p11 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 11
+  %p12 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 12
+  %p13 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 13
+  %p14 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 14
+  %p15 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 15
+  %p16 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 16
+  %p17 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 17
+  %p18 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 18
+  %p19 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 19
+  %p20 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 20
+  %p21 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 21
+  %p22 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 22
+  %p23 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 23
+  %p24 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 24
+  %p25 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 25
+  %p26 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 26
+  %p27 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 27
+  %p28 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 28
+  %p29 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 29
+  %p30 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 30
+  %p31 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 31
+  %p32 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 32
+  %p33 = getelementptr <8 x i16>, <8 x i16>* %p0, i32 33
+  %0  = load <8 x i16>, <8 x i16>* %p0, align 16
+  %1  = load <8 x i16>, <8 x i16>* %p1, align 16
+  %2  = load <8 x i16>, <8 x i16>* %p2, align 16
+  %3  = load <8 x i16>, <8 x i16>* %p3, align 16
+  %4  = load <8 x i16>, <8 x i16>* %p4, align 16
+  %5  = load <8 x i16>, <8 x i16>* %p5, align 16
+  %6  = load <8 x i16>, <8 x i16>* %p6, align 16
+  %7  = load <8 x i16>, <8 x i16>* %p7, align 16
+  %8  = load <8 x i16>, <8 x i16>* %p8, align 16
+  %9  = load <8 x i16>, <8 x i16>* %p9, align 16
+  %10 = load <8 x i16>, <8 x i16>* %p10, align 16
+  %11 = load <8 x i16>, <8 x i16>* %p11, align 16
+  %12 = load <8 x i16>, <8 x i16>* %p12, align 16
+  %13 = load <8 x i16>, <8 x i16>* %p13, align 16
+  %14 = load <8 x i16>, <8 x i16>* %p14, align 16
+  %15 = load <8 x i16>, <8 x i16>* %p15, align 16
+  %16 = load <8 x i16>, <8 x i16>* %p16, align 16
+  %17 = load <8 x i16>, <8 x i16>* %p17, align 16
+  %18 = load <8 x i16>, <8 x i16>* %p18, align 16
+  %19 = load <8 x i16>, <8 x i16>* %p19, align 16
+  %20 = load <8 x i16>, <8 x i16>* %p20, align 16
+  %21 = load <8 x i16>, <8 x i16>* %p21, align 16
+  %22 = load <8 x i16>, <8 x i16>* %p22, align 16
+  %23 = load <8 x i16>, <8 x i16>* %p23, align 16
+  %24 = load <8 x i16>, <8 x i16>* %p24, align 16
+  %25 = load <8 x i16>, <8 x i16>* %p25, align 16
+  %26 = load <8 x i16>, <8 x i16>* %p26, align 16
+  %27 = load <8 x i16>, <8 x i16>* %p27, align 16
+  %28 = load <8 x i16>, <8 x i16>* %p28, align 16
+  %29 = load <8 x i16>, <8 x i16>* %p29, align 16
+  %30 = load <8 x i16>, <8 x i16>* %p30, align 16
+  %31 = load <8 x i16>, <8 x i16>* %p31, align 16
+  %32 = load <8 x i16>, <8 x i16>* %p32, align 16
+  %33 = load <8 x i16>, <8 x i16>* %p33, align 16
   %r1  = call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0,   <8 x i16> %1)
   %r2  = call <8 x i16> @llvm.mips.addv.h(<8 x i16> %r1,  <8 x i16> %2)
   %r3  = call <8 x i16> @llvm.mips.addv.h(<8 x i16> %r2,  <8 x i16> %3)
@@ -304,73 +304,73 @@ declare i32       @llvm.mips.copy.s.h(<8 x i16>, i32) nounwind
 
 define i32 @test_i32(<4 x i32>* %p0, <4 x i32>* %q1) nounwind {
 entry:
-  %p1  = getelementptr <4 x i32>* %p0, i32 1
-  %p2  = getelementptr <4 x i32>* %p0, i32 2
-  %p3  = getelementptr <4 x i32>* %p0, i32 3
-  %p4  = getelementptr <4 x i32>* %p0, i32 4
-  %p5  = getelementptr <4 x i32>* %p0, i32 5
-  %p6  = getelementptr <4 x i32>* %p0, i32 6
-  %p7  = getelementptr <4 x i32>* %p0, i32 7
-  %p8  = getelementptr <4 x i32>* %p0, i32 8
-  %p9  = getelementptr <4 x i32>* %p0, i32 9
-  %p10 = getelementptr <4 x i32>* %p0, i32 10
-  %p11 = getelementptr <4 x i32>* %p0, i32 11
-  %p12 = getelementptr <4 x i32>* %p0, i32 12
-  %p13 = getelementptr <4 x i32>* %p0, i32 13
-  %p14 = getelementptr <4 x i32>* %p0, i32 14
-  %p15 = getelementptr <4 x i32>* %p0, i32 15
-  %p16 = getelementptr <4 x i32>* %p0, i32 16
-  %p17 = getelementptr <4 x i32>* %p0, i32 17
-  %p18 = getelementptr <4 x i32>* %p0, i32 18
-  %p19 = getelementptr <4 x i32>* %p0, i32 19
-  %p20 = getelementptr <4 x i32>* %p0, i32 20
-  %p21 = getelementptr <4 x i32>* %p0, i32 21
-  %p22 = getelementptr <4 x i32>* %p0, i32 22
-  %p23 = getelementptr <4 x i32>* %p0, i32 23
-  %p24 = getelementptr <4 x i32>* %p0, i32 24
-  %p25 = getelementptr <4 x i32>* %p0, i32 25
-  %p26 = getelementptr <4 x i32>* %p0, i32 26
-  %p27 = getelementptr <4 x i32>* %p0, i32 27
-  %p28 = getelementptr <4 x i32>* %p0, i32 28
-  %p29 = getelementptr <4 x i32>* %p0, i32 29
-  %p30 = getelementptr <4 x i32>* %p0, i32 30
-  %p31 = getelementptr <4 x i32>* %p0, i32 31
-  %p32 = getelementptr <4 x i32>* %p0, i32 32
-  %p33 = getelementptr <4 x i32>* %p0, i32 33
-  %0  = load <4 x i32>* %p0, align 16
-  %1  = load <4 x i32>* %p1, align 16
-  %2  = load <4 x i32>* %p2, align 16
-  %3  = load <4 x i32>* %p3, align 16
-  %4  = load <4 x i32>* %p4, align 16
-  %5  = load <4 x i32>* %p5, align 16
-  %6  = load <4 x i32>* %p6, align 16
-  %7  = load <4 x i32>* %p7, align 16
-  %8  = load <4 x i32>* %p8, align 16
-  %9  = load <4 x i32>* %p9, align 16
-  %10 = load <4 x i32>* %p10, align 16
-  %11 = load <4 x i32>* %p11, align 16
-  %12 = load <4 x i32>* %p12, align 16
-  %13 = load <4 x i32>* %p13, align 16
-  %14 = load <4 x i32>* %p14, align 16
-  %15 = load <4 x i32>* %p15, align 16
-  %16 = load <4 x i32>* %p16, align 16
-  %17 = load <4 x i32>* %p17, align 16
-  %18 = load <4 x i32>* %p18, align 16
-  %19 = load <4 x i32>* %p19, align 16
-  %20 = load <4 x i32>* %p20, align 16
-  %21 = load <4 x i32>* %p21, align 16
-  %22 = load <4 x i32>* %p22, align 16
-  %23 = load <4 x i32>* %p23, align 16
-  %24 = load <4 x i32>* %p24, align 16
-  %25 = load <4 x i32>* %p25, align 16
-  %26 = load <4 x i32>* %p26, align 16
-  %27 = load <4 x i32>* %p27, align 16
-  %28 = load <4 x i32>* %p28, align 16
-  %29 = load <4 x i32>* %p29, align 16
-  %30 = load <4 x i32>* %p30, align 16
-  %31 = load <4 x i32>* %p31, align 16
-  %32 = load <4 x i32>* %p32, align 16
-  %33 = load <4 x i32>* %p33, align 16
+  %p1  = getelementptr <4 x i32>, <4 x i32>* %p0, i32 1
+  %p2  = getelementptr <4 x i32>, <4 x i32>* %p0, i32 2
+  %p3  = getelementptr <4 x i32>, <4 x i32>* %p0, i32 3
+  %p4  = getelementptr <4 x i32>, <4 x i32>* %p0, i32 4
+  %p5  = getelementptr <4 x i32>, <4 x i32>* %p0, i32 5
+  %p6  = getelementptr <4 x i32>, <4 x i32>* %p0, i32 6
+  %p7  = getelementptr <4 x i32>, <4 x i32>* %p0, i32 7
+  %p8  = getelementptr <4 x i32>, <4 x i32>* %p0, i32 8
+  %p9  = getelementptr <4 x i32>, <4 x i32>* %p0, i32 9
+  %p10 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 10
+  %p11 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 11
+  %p12 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 12
+  %p13 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 13
+  %p14 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 14
+  %p15 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 15
+  %p16 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 16
+  %p17 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 17
+  %p18 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 18
+  %p19 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 19
+  %p20 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 20
+  %p21 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 21
+  %p22 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 22
+  %p23 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 23
+  %p24 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 24
+  %p25 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 25
+  %p26 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 26
+  %p27 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 27
+  %p28 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 28
+  %p29 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 29
+  %p30 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 30
+  %p31 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 31
+  %p32 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 32
+  %p33 = getelementptr <4 x i32>, <4 x i32>* %p0, i32 33
+  %0  = load <4 x i32>, <4 x i32>* %p0, align 16
+  %1  = load <4 x i32>, <4 x i32>* %p1, align 16
+  %2  = load <4 x i32>, <4 x i32>* %p2, align 16
+  %3  = load <4 x i32>, <4 x i32>* %p3, align 16
+  %4  = load <4 x i32>, <4 x i32>* %p4, align 16
+  %5  = load <4 x i32>, <4 x i32>* %p5, align 16
+  %6  = load <4 x i32>, <4 x i32>* %p6, align 16
+  %7  = load <4 x i32>, <4 x i32>* %p7, align 16
+  %8  = load <4 x i32>, <4 x i32>* %p8, align 16
+  %9  = load <4 x i32>, <4 x i32>* %p9, align 16
+  %10 = load <4 x i32>, <4 x i32>* %p10, align 16
+  %11 = load <4 x i32>, <4 x i32>* %p11, align 16
+  %12 = load <4 x i32>, <4 x i32>* %p12, align 16
+  %13 = load <4 x i32>, <4 x i32>* %p13, align 16
+  %14 = load <4 x i32>, <4 x i32>* %p14, align 16
+  %15 = load <4 x i32>, <4 x i32>* %p15, align 16
+  %16 = load <4 x i32>, <4 x i32>* %p16, align 16
+  %17 = load <4 x i32>, <4 x i32>* %p17, align 16
+  %18 = load <4 x i32>, <4 x i32>* %p18, align 16
+  %19 = load <4 x i32>, <4 x i32>* %p19, align 16
+  %20 = load <4 x i32>, <4 x i32>* %p20, align 16
+  %21 = load <4 x i32>, <4 x i32>* %p21, align 16
+  %22 = load <4 x i32>, <4 x i32>* %p22, align 16
+  %23 = load <4 x i32>, <4 x i32>* %p23, align 16
+  %24 = load <4 x i32>, <4 x i32>* %p24, align 16
+  %25 = load <4 x i32>, <4 x i32>* %p25, align 16
+  %26 = load <4 x i32>, <4 x i32>* %p26, align 16
+  %27 = load <4 x i32>, <4 x i32>* %p27, align 16
+  %28 = load <4 x i32>, <4 x i32>* %p28, align 16
+  %29 = load <4 x i32>, <4 x i32>* %p29, align 16
+  %30 = load <4 x i32>, <4 x i32>* %p30, align 16
+  %31 = load <4 x i32>, <4 x i32>* %p31, align 16
+  %32 = load <4 x i32>, <4 x i32>* %p32, align 16
+  %33 = load <4 x i32>, <4 x i32>* %p33, align 16
   %r1 = call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %1)
   %r2 = call <4 x i32> @llvm.mips.addv.w(<4 x i32> %r1, <4 x i32> %2)
   %r3 = call <4 x i32> @llvm.mips.addv.w(<4 x i32> %r2, <4 x i32> %3)
@@ -453,73 +453,73 @@ declare i32       @llvm.mips.copy.s.w(<4 x i32>, i32) nounwind
 
 define i32 @test_i64(<2 x i64>* %p0, <2 x i64>* %q1) nounwind {
 entry:
-  %p1  = getelementptr <2 x i64>* %p0, i32 1
-  %p2  = getelementptr <2 x i64>* %p0, i32 2
-  %p3  = getelementptr <2 x i64>* %p0, i32 3
-  %p4  = getelementptr <2 x i64>* %p0, i32 4
-  %p5  = getelementptr <2 x i64>* %p0, i32 5
-  %p6  = getelementptr <2 x i64>* %p0, i32 6
-  %p7  = getelementptr <2 x i64>* %p0, i32 7
-  %p8  = getelementptr <2 x i64>* %p0, i32 8
-  %p9  = getelementptr <2 x i64>* %p0, i32 9
-  %p10 = getelementptr <2 x i64>* %p0, i32 10
-  %p11 = getelementptr <2 x i64>* %p0, i32 11
-  %p12 = getelementptr <2 x i64>* %p0, i32 12
-  %p13 = getelementptr <2 x i64>* %p0, i32 13
-  %p14 = getelementptr <2 x i64>* %p0, i32 14
-  %p15 = getelementptr <2 x i64>* %p0, i32 15
-  %p16 = getelementptr <2 x i64>* %p0, i32 16
-  %p17 = getelementptr <2 x i64>* %p0, i32 17
-  %p18 = getelementptr <2 x i64>* %p0, i32 18
-  %p19 = getelementptr <2 x i64>* %p0, i32 19
-  %p20 = getelementptr <2 x i64>* %p0, i32 20
-  %p21 = getelementptr <2 x i64>* %p0, i32 21
-  %p22 = getelementptr <2 x i64>* %p0, i32 22
-  %p23 = getelementptr <2 x i64>* %p0, i32 23
-  %p24 = getelementptr <2 x i64>* %p0, i32 24
-  %p25 = getelementptr <2 x i64>* %p0, i32 25
-  %p26 = getelementptr <2 x i64>* %p0, i32 26
-  %p27 = getelementptr <2 x i64>* %p0, i32 27
-  %p28 = getelementptr <2 x i64>* %p0, i32 28
-  %p29 = getelementptr <2 x i64>* %p0, i32 29
-  %p30 = getelementptr <2 x i64>* %p0, i32 30
-  %p31 = getelementptr <2 x i64>* %p0, i32 31
-  %p32 = getelementptr <2 x i64>* %p0, i32 32
-  %p33 = getelementptr <2 x i64>* %p0, i32 33
-  %0  = load <2 x i64>* %p0, align 16
-  %1  = load <2 x i64>* %p1, align 16
-  %2  = load <2 x i64>* %p2, align 16
-  %3  = load <2 x i64>* %p3, align 16
-  %4  = load <2 x i64>* %p4, align 16
-  %5  = load <2 x i64>* %p5, align 16
-  %6  = load <2 x i64>* %p6, align 16
-  %7  = load <2 x i64>* %p7, align 16
-  %8  = load <2 x i64>* %p8, align 16
-  %9  = load <2 x i64>* %p9, align 16
-  %10 = load <2 x i64>* %p10, align 16
-  %11 = load <2 x i64>* %p11, align 16
-  %12 = load <2 x i64>* %p12, align 16
-  %13 = load <2 x i64>* %p13, align 16
-  %14 = load <2 x i64>* %p14, align 16
-  %15 = load <2 x i64>* %p15, align 16
-  %16 = load <2 x i64>* %p16, align 16
-  %17 = load <2 x i64>* %p17, align 16
-  %18 = load <2 x i64>* %p18, align 16
-  %19 = load <2 x i64>* %p19, align 16
-  %20 = load <2 x i64>* %p20, align 16
-  %21 = load <2 x i64>* %p21, align 16
-  %22 = load <2 x i64>* %p22, align 16
-  %23 = load <2 x i64>* %p23, align 16
-  %24 = load <2 x i64>* %p24, align 16
-  %25 = load <2 x i64>* %p25, align 16
-  %26 = load <2 x i64>* %p26, align 16
-  %27 = load <2 x i64>* %p27, align 16
-  %28 = load <2 x i64>* %p28, align 16
-  %29 = load <2 x i64>* %p29, align 16
-  %30 = load <2 x i64>* %p30, align 16
-  %31 = load <2 x i64>* %p31, align 16
-  %32 = load <2 x i64>* %p32, align 16
-  %33 = load <2 x i64>* %p33, align 16
+  %p1  = getelementptr <2 x i64>, <2 x i64>* %p0, i32 1
+  %p2  = getelementptr <2 x i64>, <2 x i64>* %p0, i32 2
+  %p3  = getelementptr <2 x i64>, <2 x i64>* %p0, i32 3
+  %p4  = getelementptr <2 x i64>, <2 x i64>* %p0, i32 4
+  %p5  = getelementptr <2 x i64>, <2 x i64>* %p0, i32 5
+  %p6  = getelementptr <2 x i64>, <2 x i64>* %p0, i32 6
+  %p7  = getelementptr <2 x i64>, <2 x i64>* %p0, i32 7
+  %p8  = getelementptr <2 x i64>, <2 x i64>* %p0, i32 8
+  %p9  = getelementptr <2 x i64>, <2 x i64>* %p0, i32 9
+  %p10 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 10
+  %p11 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 11
+  %p12 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 12
+  %p13 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 13
+  %p14 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 14
+  %p15 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 15
+  %p16 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 16
+  %p17 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 17
+  %p18 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 18
+  %p19 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 19
+  %p20 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 20
+  %p21 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 21
+  %p22 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 22
+  %p23 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 23
+  %p24 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 24
+  %p25 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 25
+  %p26 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 26
+  %p27 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 27
+  %p28 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 28
+  %p29 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 29
+  %p30 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 30
+  %p31 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 31
+  %p32 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 32
+  %p33 = getelementptr <2 x i64>, <2 x i64>* %p0, i32 33
+  %0  = load <2 x i64>, <2 x i64>* %p0, align 16
+  %1  = load <2 x i64>, <2 x i64>* %p1, align 16
+  %2  = load <2 x i64>, <2 x i64>* %p2, align 16
+  %3  = load <2 x i64>, <2 x i64>* %p3, align 16
+  %4  = load <2 x i64>, <2 x i64>* %p4, align 16
+  %5  = load <2 x i64>, <2 x i64>* %p5, align 16
+  %6  = load <2 x i64>, <2 x i64>* %p6, align 16
+  %7  = load <2 x i64>, <2 x i64>* %p7, align 16
+  %8  = load <2 x i64>, <2 x i64>* %p8, align 16
+  %9  = load <2 x i64>, <2 x i64>* %p9, align 16
+  %10 = load <2 x i64>, <2 x i64>* %p10, align 16
+  %11 = load <2 x i64>, <2 x i64>* %p11, align 16
+  %12 = load <2 x i64>, <2 x i64>* %p12, align 16
+  %13 = load <2 x i64>, <2 x i64>* %p13, align 16
+  %14 = load <2 x i64>, <2 x i64>* %p14, align 16
+  %15 = load <2 x i64>, <2 x i64>* %p15, align 16
+  %16 = load <2 x i64>, <2 x i64>* %p16, align 16
+  %17 = load <2 x i64>, <2 x i64>* %p17, align 16
+  %18 = load <2 x i64>, <2 x i64>* %p18, align 16
+  %19 = load <2 x i64>, <2 x i64>* %p19, align 16
+  %20 = load <2 x i64>, <2 x i64>* %p20, align 16
+  %21 = load <2 x i64>, <2 x i64>* %p21, align 16
+  %22 = load <2 x i64>, <2 x i64>* %p22, align 16
+  %23 = load <2 x i64>, <2 x i64>* %p23, align 16
+  %24 = load <2 x i64>, <2 x i64>* %p24, align 16
+  %25 = load <2 x i64>, <2 x i64>* %p25, align 16
+  %26 = load <2 x i64>, <2 x i64>* %p26, align 16
+  %27 = load <2 x i64>, <2 x i64>* %p27, align 16
+  %28 = load <2 x i64>, <2 x i64>* %p28, align 16
+  %29 = load <2 x i64>, <2 x i64>* %p29, align 16
+  %30 = load <2 x i64>, <2 x i64>* %p30, align 16
+  %31 = load <2 x i64>, <2 x i64>* %p31, align 16
+  %32 = load <2 x i64>, <2 x i64>* %p32, align 16
+  %33 = load <2 x i64>, <2 x i64>* %p33, align 16
   %r1  = call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0,   <2 x i64> %1)
   %r2  = call <2 x i64> @llvm.mips.addv.d(<2 x i64> %r1,  <2 x i64> %2)
   %r3  = call <2 x i64> @llvm.mips.addv.d(<2 x i64> %r2,  <2 x i64> %3)
diff --git a/test/CodeGen/Mips/msa/vec.ll b/test/CodeGen/Mips/msa/vec.ll
index d5b97f52fb83..8790923ce727 100644
--- a/test/CodeGen/Mips/msa/vec.ll
+++ b/test/CodeGen/Mips/msa/vec.ll
@@ -9,8 +9,8 @@
 
 define void @llvm_mips_and_v_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_and_v_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_and_v_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_and_v_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_and_v_b_ARG2
   %2 = bitcast <16 x i8> %0 to <16 x i8>
   %3 = bitcast <16 x i8> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.and.v(<16 x i8> %2, <16 x i8> %3)
@@ -32,8 +32,8 @@ entry:
 
 define void @llvm_mips_and_v_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_and_v_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_and_v_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_and_v_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_and_v_h_ARG2
   %2 = bitcast <8 x i16> %0 to <16 x i8>
   %3 = bitcast <8 x i16> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.and.v(<16 x i8> %2, <16 x i8> %3)
@@ -55,8 +55,8 @@ entry:
 
 define void @llvm_mips_and_v_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_and_v_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_and_v_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_and_v_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_and_v_w_ARG2
   %2 = bitcast <4 x i32> %0 to <16 x i8>
   %3 = bitcast <4 x i32> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.and.v(<16 x i8> %2, <16 x i8> %3)
@@ -78,8 +78,8 @@ entry:
 
 define void @llvm_mips_and_v_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_and_v_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_and_v_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_and_v_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_and_v_d_ARG2
   %2 = bitcast <2 x i64> %0 to <16 x i8>
   %3 = bitcast <2 x i64> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.and.v(<16 x i8> %2, <16 x i8> %3)
@@ -97,8 +97,8 @@ entry:
 ;
 define void @and_v_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_and_v_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_and_v_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_and_v_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_and_v_b_ARG2
   %2 = and <16 x i8> %0, %1
   store <16 x i8> %2, <16 x i8>* @llvm_mips_and_v_b_RES
   ret void
@@ -113,8 +113,8 @@ entry:
 ;
 define void @and_v_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_and_v_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_and_v_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_and_v_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_and_v_h_ARG2
   %2 = and <8 x i16> %0, %1
   store <8 x i16> %2, <8 x i16>* @llvm_mips_and_v_h_RES
   ret void
@@ -130,8 +130,8 @@ entry:
 
 define void @and_v_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_and_v_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_and_v_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_and_v_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_and_v_w_ARG2
   %2 = and <4 x i32> %0, %1
   store <4 x i32> %2, <4 x i32>* @llvm_mips_and_v_w_RES
   ret void
@@ -147,8 +147,8 @@ entry:
 
 define void @and_v_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_and_v_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_and_v_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_and_v_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_and_v_d_ARG2
   %2 = and <2 x i64> %0, %1
   store <2 x i64> %2, <2 x i64>* @llvm_mips_and_v_d_RES
   ret void
@@ -168,9 +168,9 @@ entry:
 
 define void @llvm_mips_bmnz_v_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bmnz_v_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_bmnz_v_b_ARG2
-  %2 = load <16 x i8>* @llvm_mips_bmnz_v_b_ARG3
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnz_v_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnz_v_b_ARG2
+  %2 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnz_v_b_ARG3
   %3 = bitcast <16 x i8> %0 to <16 x i8>
   %4 = bitcast <16 x i8> %1 to <16 x i8>
   %5 = bitcast <16 x i8> %2 to <16 x i8>
@@ -198,9 +198,9 @@ entry:
 
 define void @llvm_mips_bmnz_v_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_bmnz_v_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_bmnz_v_h_ARG2
-  %2 = load <8 x i16>* @llvm_mips_bmnz_v_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bmnz_v_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_bmnz_v_h_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_bmnz_v_h_ARG3
   %3 = bitcast <8 x i16> %0 to <16 x i8>
   %4 = bitcast <8 x i16> %1 to <16 x i8>
   %5 = bitcast <8 x i16> %2 to <16 x i8>
@@ -228,9 +228,9 @@ entry:
 
 define void @llvm_mips_bmnz_v_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_bmnz_v_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_bmnz_v_w_ARG2
-  %2 = load <4 x i32>* @llvm_mips_bmnz_v_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bmnz_v_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_bmnz_v_w_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_bmnz_v_w_ARG3
   %3 = bitcast <4 x i32> %0 to <16 x i8>
   %4 = bitcast <4 x i32> %1 to <16 x i8>
   %5 = bitcast <4 x i32> %2 to <16 x i8>
@@ -258,9 +258,9 @@ entry:
 
 define void @llvm_mips_bmnz_v_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_bmnz_v_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_bmnz_v_d_ARG2
-  %2 = load <2 x i64>* @llvm_mips_bmnz_v_d_ARG3
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bmnz_v_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_bmnz_v_d_ARG2
+  %2 = load <2 x i64>, <2 x i64>* @llvm_mips_bmnz_v_d_ARG3
   %3 = bitcast <2 x i64> %0 to <16 x i8>
   %4 = bitcast <2 x i64> %1 to <16 x i8>
   %5 = bitcast <2 x i64> %2 to <16 x i8>
@@ -288,9 +288,9 @@ entry:
 
 define void @llvm_mips_bmz_v_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bmz_v_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_bmz_v_b_ARG2
-  %2 = load <16 x i8>* @llvm_mips_bmz_v_b_ARG3
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bmz_v_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bmz_v_b_ARG2
+  %2 = load <16 x i8>, <16 x i8>* @llvm_mips_bmz_v_b_ARG3
   %3 = bitcast <16 x i8> %0 to <16 x i8>
   %4 = bitcast <16 x i8> %1 to <16 x i8>
   %5 = bitcast <16 x i8> %2 to <16 x i8>
@@ -319,9 +319,9 @@ entry:
 
 define void @llvm_mips_bmz_v_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_bmz_v_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_bmz_v_h_ARG2
-  %2 = load <8 x i16>* @llvm_mips_bmz_v_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bmz_v_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_bmz_v_h_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_bmz_v_h_ARG3
   %3 = bitcast <8 x i16> %0 to <16 x i8>
   %4 = bitcast <8 x i16> %1 to <16 x i8>
   %5 = bitcast <8 x i16> %2 to <16 x i8>
@@ -350,9 +350,9 @@ entry:
 
 define void @llvm_mips_bmz_v_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_bmz_v_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_bmz_v_w_ARG2
-  %2 = load <4 x i32>* @llvm_mips_bmz_v_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bmz_v_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_bmz_v_w_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_bmz_v_w_ARG3
   %3 = bitcast <4 x i32> %0 to <16 x i8>
   %4 = bitcast <4 x i32> %1 to <16 x i8>
   %5 = bitcast <4 x i32> %2 to <16 x i8>
@@ -381,9 +381,9 @@ entry:
 
 define void @llvm_mips_bmz_v_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_bmz_v_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_bmz_v_d_ARG2
-  %2 = load <2 x i64>* @llvm_mips_bmz_v_d_ARG3
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bmz_v_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_bmz_v_d_ARG2
+  %2 = load <2 x i64>, <2 x i64>* @llvm_mips_bmz_v_d_ARG3
   %3 = bitcast <2 x i64> %0 to <16 x i8>
   %4 = bitcast <2 x i64> %1 to <16 x i8>
   %5 = bitcast <2 x i64> %2 to <16 x i8>
@@ -412,9 +412,9 @@ entry:
 
 define void @llvm_mips_bsel_v_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bsel_v_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_bsel_v_b_ARG2
-  %2 = load <16 x i8>* @llvm_mips_bsel_v_b_ARG3
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bsel_v_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bsel_v_b_ARG2
+  %2 = load <16 x i8>, <16 x i8>* @llvm_mips_bsel_v_b_ARG3
   %3 = bitcast <16 x i8> %0 to <16 x i8>
   %4 = bitcast <16 x i8> %1 to <16 x i8>
   %5 = bitcast <16 x i8> %2 to <16 x i8>
@@ -443,9 +443,9 @@ entry:
 
 define void @llvm_mips_bsel_v_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_bsel_v_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_bsel_v_h_ARG2
-  %2 = load <8 x i16>* @llvm_mips_bsel_v_h_ARG3
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bsel_v_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_bsel_v_h_ARG2
+  %2 = load <8 x i16>, <8 x i16>* @llvm_mips_bsel_v_h_ARG3
   %3 = bitcast <8 x i16> %0 to <16 x i8>
   %4 = bitcast <8 x i16> %1 to <16 x i8>
   %5 = bitcast <8 x i16> %2 to <16 x i8>
@@ -474,9 +474,9 @@ entry:
 
 define void @llvm_mips_bsel_v_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_bsel_v_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_bsel_v_w_ARG2
-  %2 = load <4 x i32>* @llvm_mips_bsel_v_w_ARG3
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bsel_v_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_bsel_v_w_ARG2
+  %2 = load <4 x i32>, <4 x i32>* @llvm_mips_bsel_v_w_ARG3
   %3 = bitcast <4 x i32> %0 to <16 x i8>
   %4 = bitcast <4 x i32> %1 to <16 x i8>
   %5 = bitcast <4 x i32> %2 to <16 x i8>
@@ -505,9 +505,9 @@ entry:
 
 define void @llvm_mips_bsel_v_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_bsel_v_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_bsel_v_d_ARG2
-  %2 = load <2 x i64>* @llvm_mips_bsel_v_d_ARG3
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bsel_v_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_bsel_v_d_ARG2
+  %2 = load <2 x i64>, <2 x i64>* @llvm_mips_bsel_v_d_ARG3
   %3 = bitcast <2 x i64> %0 to <16 x i8>
   %4 = bitcast <2 x i64> %1 to <16 x i8>
   %5 = bitcast <2 x i64> %2 to <16 x i8>
@@ -535,8 +535,8 @@ entry:
 
 define void @llvm_mips_nor_v_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_nor_v_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_nor_v_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_nor_v_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_nor_v_b_ARG2
   %2 = bitcast <16 x i8> %0 to <16 x i8>
   %3 = bitcast <16 x i8> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.nor.v(<16 x i8> %2, <16 x i8> %3)
@@ -558,8 +558,8 @@ entry:
 
 define void @llvm_mips_nor_v_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_nor_v_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_nor_v_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_nor_v_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_nor_v_h_ARG2
   %2 = bitcast <8 x i16> %0 to <16 x i8>
   %3 = bitcast <8 x i16> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.nor.v(<16 x i8> %2, <16 x i8> %3)
@@ -581,8 +581,8 @@ entry:
 
 define void @llvm_mips_nor_v_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_nor_v_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_nor_v_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_nor_v_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_nor_v_w_ARG2
   %2 = bitcast <4 x i32> %0 to <16 x i8>
   %3 = bitcast <4 x i32> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.nor.v(<16 x i8> %2, <16 x i8> %3)
@@ -604,8 +604,8 @@ entry:
 
 define void @llvm_mips_nor_v_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_nor_v_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_nor_v_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_nor_v_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_nor_v_d_ARG2
   %2 = bitcast <2 x i64> %0 to <16 x i8>
   %3 = bitcast <2 x i64> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.nor.v(<16 x i8> %2, <16 x i8> %3)
@@ -627,8 +627,8 @@ entry:
 
 define void @llvm_mips_or_v_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_or_v_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_or_v_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_or_v_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_or_v_b_ARG2
   %2 = bitcast <16 x i8> %0 to <16 x i8>
   %3 = bitcast <16 x i8> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.or.v(<16 x i8> %2, <16 x i8> %3)
@@ -650,8 +650,8 @@ entry:
 
 define void @llvm_mips_or_v_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_or_v_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_or_v_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_or_v_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_or_v_h_ARG2
   %2 = bitcast <8 x i16> %0 to <16 x i8>
   %3 = bitcast <8 x i16> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.or.v(<16 x i8> %2, <16 x i8> %3)
@@ -673,8 +673,8 @@ entry:
 
 define void @llvm_mips_or_v_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_or_v_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_or_v_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_or_v_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_or_v_w_ARG2
   %2 = bitcast <4 x i32> %0 to <16 x i8>
   %3 = bitcast <4 x i32> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.or.v(<16 x i8> %2, <16 x i8> %3)
@@ -696,8 +696,8 @@ entry:
 
 define void @llvm_mips_or_v_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_or_v_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_or_v_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_or_v_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_or_v_d_ARG2
   %2 = bitcast <2 x i64> %0 to <16 x i8>
   %3 = bitcast <2 x i64> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.or.v(<16 x i8> %2, <16 x i8> %3)
@@ -715,8 +715,8 @@ entry:
 ;
 define void @or_v_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_or_v_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_or_v_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_or_v_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_or_v_b_ARG2
   %2 = or <16 x i8> %0, %1
   store <16 x i8> %2, <16 x i8>* @llvm_mips_or_v_b_RES
   ret void
@@ -731,8 +731,8 @@ entry:
 ;
 define void @or_v_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_or_v_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_or_v_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_or_v_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_or_v_h_ARG2
   %2 = or <8 x i16> %0, %1
   store <8 x i16> %2, <8 x i16>* @llvm_mips_or_v_h_RES
   ret void
@@ -748,8 +748,8 @@ entry:
 
 define void @or_v_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_or_v_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_or_v_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_or_v_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_or_v_w_ARG2
   %2 = or <4 x i32> %0, %1
   store <4 x i32> %2, <4 x i32>* @llvm_mips_or_v_w_RES
   ret void
@@ -765,8 +765,8 @@ entry:
 
 define void @or_v_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_or_v_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_or_v_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_or_v_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_or_v_d_ARG2
   %2 = or <2 x i64> %0, %1
   store <2 x i64> %2, <2 x i64>* @llvm_mips_or_v_d_RES
   ret void
@@ -785,8 +785,8 @@ entry:
 
 define void @llvm_mips_xor_v_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_xor_v_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_xor_v_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_xor_v_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_xor_v_b_ARG2
   %2 = bitcast <16 x i8> %0 to <16 x i8>
   %3 = bitcast <16 x i8> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.xor.v(<16 x i8> %2, <16 x i8> %3)
@@ -808,8 +808,8 @@ entry:
 
 define void @llvm_mips_xor_v_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_xor_v_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_xor_v_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_xor_v_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_xor_v_h_ARG2
   %2 = bitcast <8 x i16> %0 to <16 x i8>
   %3 = bitcast <8 x i16> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.xor.v(<16 x i8> %2, <16 x i8> %3)
@@ -831,8 +831,8 @@ entry:
 
 define void @llvm_mips_xor_v_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_xor_v_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_xor_v_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_xor_v_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_xor_v_w_ARG2
   %2 = bitcast <4 x i32> %0 to <16 x i8>
   %3 = bitcast <4 x i32> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.xor.v(<16 x i8> %2, <16 x i8> %3)
@@ -854,8 +854,8 @@ entry:
 
 define void @llvm_mips_xor_v_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_xor_v_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_xor_v_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_xor_v_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_xor_v_d_ARG2
   %2 = bitcast <2 x i64> %0 to <16 x i8>
   %3 = bitcast <2 x i64> %1 to <16 x i8>
   %4 = tail call <16 x i8> @llvm.mips.xor.v(<16 x i8> %2, <16 x i8> %3)
@@ -873,8 +873,8 @@ entry:
 ;
 define void @xor_v_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_xor_v_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_xor_v_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_xor_v_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_xor_v_b_ARG2
   %2 = xor <16 x i8> %0, %1
   store <16 x i8> %2, <16 x i8>* @llvm_mips_xor_v_b_RES
   ret void
@@ -889,8 +889,8 @@ entry:
 ;
 define void @xor_v_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_xor_v_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_xor_v_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_xor_v_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_xor_v_h_ARG2
   %2 = xor <8 x i16> %0, %1
   store <8 x i16> %2, <8 x i16>* @llvm_mips_xor_v_h_RES
   ret void
@@ -906,8 +906,8 @@ entry:
 
 define void @xor_v_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_xor_v_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_xor_v_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_xor_v_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_xor_v_w_ARG2
   %2 = xor <4 x i32> %0, %1
   store <4 x i32> %2, <4 x i32>* @llvm_mips_xor_v_w_RES
   ret void
@@ -923,8 +923,8 @@ entry:
 
 define void @xor_v_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_xor_v_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_xor_v_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_xor_v_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_xor_v_d_ARG2
   %2 = xor <2 x i64> %0, %1
   store <2 x i64> %2, <2 x i64>* @llvm_mips_xor_v_d_RES
   ret void
diff --git a/test/CodeGen/Mips/msa/vecs10.ll b/test/CodeGen/Mips/msa/vecs10.ll
index e22e0755ef00..f442f7727447 100644
--- a/test/CodeGen/Mips/msa/vecs10.ll
+++ b/test/CodeGen/Mips/msa/vecs10.ll
@@ -7,7 +7,7 @@
 
 define i32 @llvm_mips_bnz_v_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bnz_v_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bnz_v_ARG1
   %1 = tail call i32 @llvm.mips.bnz.v(<16 x i8> %0)
   %2 = icmp eq i32 %1, 0
   br i1 %2, label %true, label %false
@@ -28,7 +28,7 @@ declare i32 @llvm.mips.bnz.v(<16 x i8>) nounwind
 
 define i32 @llvm_mips_bz_v_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bz_v_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bz_v_ARG1
   %1 = tail call i32 @llvm.mips.bz.v(<16 x i8> %0)
   %2 = icmp eq i32 %1, 0
   br i1 %2, label %true, label %false
diff --git a/test/CodeGen/Mips/mul.ll b/test/CodeGen/Mips/mul.ll
index 4ce801b1c9f4..3231f9cac38e 100644
--- a/test/CodeGen/Mips/mul.ll
+++ b/test/CodeGen/Mips/mul.ll
@@ -6,8 +6,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @iiii, align 4
-  %1 = load i32* @jjjj, align 4
+  %0 = load i32, i32* @iiii, align 4
+  %1 = load i32, i32* @jjjj, align 4
   %mul = mul nsw i32 %1, %0
 ; 16:	mult	${{[0-9]+}}, ${{[0-9]+}}
 ; 16: 	mflo	${{[0-9]+}}
diff --git a/test/CodeGen/Mips/mulll.ll b/test/CodeGen/Mips/mulll.ll
index e37b9197df82..6e5ba647b8bf 100644
--- a/test/CodeGen/Mips/mulll.ll
+++ b/test/CodeGen/Mips/mulll.ll
@@ -6,8 +6,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i64* @iiii, align 8
-  %1 = load i64* @jjjj, align 8
+  %0 = load i64, i64* @iiii, align 8
+  %1 = load i64, i64* @jjjj, align 8
   %mul = mul nsw i64 %1, %0
   store i64 %mul, i64* @kkkk, align 8
 ; 16:	multu	${{[0-9]+}}, ${{[0-9]+}}
diff --git a/test/CodeGen/Mips/mulull.ll b/test/CodeGen/Mips/mulull.ll
index 4d23c693184b..c1334484fb66 100644
--- a/test/CodeGen/Mips/mulull.ll
+++ b/test/CodeGen/Mips/mulull.ll
@@ -7,8 +7,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i64* @iiii, align 8
-  %1 = load i64* @jjjj, align 8
+  %0 = load i64, i64* @iiii, align 8
+  %1 = load i64, i64* @jjjj, align 8
   %mul = mul nsw i64 %1, %0
   store i64 %mul, i64* @kkkk, align 8
 ; 16:	multu	${{[0-9]+}}, ${{[0-9]+}}
diff --git a/test/CodeGen/Mips/nacl-align.ll b/test/CodeGen/Mips/nacl-align.ll
index e61b8347760e..ec8f3f06afdf 100644
--- a/test/CodeGen/Mips/nacl-align.ll
+++ b/test/CodeGen/Mips/nacl-align.ll
@@ -67,8 +67,8 @@ default:
 
 define i32 @test2(i32 %i) {
 entry:
-  %elementptr = getelementptr inbounds [2 x i8*]* @bb_array, i32 0, i32 %i
-  %0 = load i8** %elementptr, align 4
+  %elementptr = getelementptr inbounds [2 x i8*], [2 x i8*]* @bb_array, i32 0, i32 %i
+  %0 = load i8*, i8** %elementptr, align 4
   indirectbr i8* %0, [label %bb1, label %bb2]
 
 bb1:
diff --git a/test/CodeGen/Mips/nacl-branch-delay.ll b/test/CodeGen/Mips/nacl-branch-delay.ll
index d251eee07526..2927f39a416c 100644
--- a/test/CodeGen/Mips/nacl-branch-delay.ll
+++ b/test/CodeGen/Mips/nacl-branch-delay.ll
@@ -10,7 +10,7 @@ declare void @f2()
 
 
 define void @test1() {
-  %1 = load i32* @x, align 4
+  %1 = load i32, i32* @x, align 4
   call void @f1(i32 %1)
   ret void
 
diff --git a/test/CodeGen/Mips/nacl-reserved-regs.ll b/test/CodeGen/Mips/nacl-reserved-regs.ll
index ae21283b1fb7..efe2a663a3c5 100644
--- a/test/CodeGen/Mips/nacl-reserved-regs.ll
+++ b/test/CodeGen/Mips/nacl-reserved-regs.ll
@@ -5,22 +5,22 @@
 @var = external global i32
 
 define void @f() {
-  %val1 = load volatile i32* @var
-  %val2 = load volatile i32* @var
-  %val3 = load volatile i32* @var
-  %val4 = load volatile i32* @var
-  %val5 = load volatile i32* @var
-  %val6 = load volatile i32* @var
-  %val7 = load volatile i32* @var
-  %val8 = load volatile i32* @var
-  %val9 = load volatile i32* @var
-  %val10 = load volatile i32* @var
-  %val11 = load volatile i32* @var
-  %val12 = load volatile i32* @var
-  %val13 = load volatile i32* @var
-  %val14 = load volatile i32* @var
-  %val15 = load volatile i32* @var
-  %val16 = load volatile i32* @var
+  %val1 = load volatile i32, i32* @var
+  %val2 = load volatile i32, i32* @var
+  %val3 = load volatile i32, i32* @var
+  %val4 = load volatile i32, i32* @var
+  %val5 = load volatile i32, i32* @var
+  %val6 = load volatile i32, i32* @var
+  %val7 = load volatile i32, i32* @var
+  %val8 = load volatile i32, i32* @var
+  %val9 = load volatile i32, i32* @var
+  %val10 = load volatile i32, i32* @var
+  %val11 = load volatile i32, i32* @var
+  %val12 = load volatile i32, i32* @var
+  %val13 = load volatile i32, i32* @var
+  %val14 = load volatile i32, i32* @var
+  %val15 = load volatile i32, i32* @var
+  %val16 = load volatile i32, i32* @var
   store volatile i32 %val1, i32* @var
   store volatile i32 %val2, i32* @var
   store volatile i32 %val3, i32* @var
diff --git a/test/CodeGen/Mips/named-register-n32.ll b/test/CodeGen/Mips/named-register-n32.ll
index 1e5f53ac5c9c..b15e9283fc43 100644
--- a/test/CodeGen/Mips/named-register-n32.ll
+++ b/test/CodeGen/Mips/named-register-n32.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64 -relocation-model=static -mattr=+noabicalls,-n64,+n32 < %s | FileCheck %s
+; RUN: llc -march=mips64 -relocation-model=static -mattr=+noabicalls -target-abi n32 < %s | FileCheck %s
 
 define i32* @get_gp() {
 entry:
diff --git a/test/CodeGen/Mips/neg1.ll b/test/CodeGen/Mips/neg1.ll
index 281e62621565..36275a2991f6 100644
--- a/test/CodeGen/Mips/neg1.ll
+++ b/test/CodeGen/Mips/neg1.ll
@@ -5,10 +5,10 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %sub = sub nsw i32 0, %0
 ; 16:	neg	${{[0-9]+}}, ${{[0-9]+}}
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %sub)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %sub)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/no-odd-spreg-msa.ll b/test/CodeGen/Mips/no-odd-spreg-msa.ll
index 30dd1ff82d73..cf79557cc97f 100644
--- a/test/CodeGen/Mips/no-odd-spreg-msa.ll
+++ b/test/CodeGen/Mips/no-odd-spreg-msa.ll
@@ -8,7 +8,7 @@ entry:
   ; Force the float into an odd-numbered register using named registers and
   ; load the vector.
   %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
-  %0 = load volatile <4 x float>* @v4f32
+  %0 = load volatile <4 x float>, <4 x float>* @v4f32
 
   ; Clobber all except $f12/$w12 and $f13
   ;
@@ -42,7 +42,7 @@ entry:
   ; Force the float into an odd-numbered register using named registers and
   ; load the vector.
   %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
-  %0 = load volatile <4 x float>* @v4f32
+  %0 = load volatile <4 x float>, <4 x float>* @v4f32
 
   ; Clobber all except $f12/$w12 and $f13
   ;
@@ -73,7 +73,7 @@ entry:
 
 define float @msa_extract_0() {
 entry:
-  %0 = load volatile <4 x float>* @v4f32
+  %0 = load volatile <4 x float>, <4 x float>* @v4f32
   %1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0)
 
   ; Clobber all except $f12, and $f13
@@ -101,7 +101,7 @@ entry:
 
 define float @msa_extract_1() {
 entry:
-  %0 = load volatile <4 x float>* @v4f32
+  %0 = load volatile <4 x float>, <4 x float>* @v4f32
   %1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0)
 
   ; Clobber all except $f13
diff --git a/test/CodeGen/Mips/nomips16.ll b/test/CodeGen/Mips/nomips16.ll
index 5f7d74e41979..418d8ead2c39 100644
--- a/test/CodeGen/Mips/nomips16.ll
+++ b/test/CodeGen/Mips/nomips16.ll
@@ -6,7 +6,7 @@
 ; Function Attrs: nounwind
 define void @foo() #0 {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   %conv = fpext float %0 to double
   %add = fadd double %conv, 1.500000e+00
   %conv1 = fptrunc double %add to float
@@ -20,7 +20,7 @@ entry:
 ; Function Attrs: nounwind
 define void @nofoo() #1 {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   %conv = fpext float %0 to double
   %add = fadd double %conv, 3.900000e+00
   %conv1 = fptrunc double %add to float
diff --git a/test/CodeGen/Mips/not1.ll b/test/CodeGen/Mips/not1.ll
index 2163b236c56f..f5ec5b60e421 100644
--- a/test/CodeGen/Mips/not1.ll
+++ b/test/CodeGen/Mips/not1.ll
@@ -6,10 +6,10 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @x, align 4
+  %0 = load i32, i32* @x, align 4
   %neg = xor i32 %0, -1
 ; 16:	not	${{[0-9]+}}, ${{[0-9]+}}
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), i32 %neg)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %neg)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll
index 5db47acc5a85..108c663ab1cd 100644
--- a/test/CodeGen/Mips/o32_cc_byval.ll
+++ b/test/CodeGen/Mips/o32_cc_byval.ll
@@ -30,7 +30,7 @@ entry:
   %agg.tmp10 = alloca %struct.S3, align 4
   call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
   call void @callee2(%struct.S2* byval @f1.s2) nounwind
-  %tmp11 = getelementptr inbounds %struct.S3* %agg.tmp10, i32 0, i32 0
+  %tmp11 = getelementptr inbounds %struct.S3, %struct.S3* %agg.tmp10, i32 0, i32 0
   store i8 11, i8* %tmp11, align 4
   call void @callee3(float 2.100000e+01, %struct.S3* byval %agg.tmp10, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
   ret void
@@ -61,18 +61,18 @@ entry:
 ; CHECK: sw  $[[R3]], 16($sp)
 ; CHECK: mfc1 $6, $f[[F0]]
 
-  %i2 = getelementptr inbounds %struct.S1* %s1, i32 0, i32 5
-  %tmp = load i32* %i2, align 4
-  %d = getelementptr inbounds %struct.S1* %s1, i32 0, i32 4
-  %tmp1 = load double* %d, align 8
-  %ll = getelementptr inbounds %struct.S1* %s1, i32 0, i32 3
-  %tmp2 = load i64* %ll, align 8
-  %i = getelementptr inbounds %struct.S1* %s1, i32 0, i32 2
-  %tmp3 = load i32* %i, align 4
-  %s = getelementptr inbounds %struct.S1* %s1, i32 0, i32 1
-  %tmp4 = load i16* %s, align 2
-  %c = getelementptr inbounds %struct.S1* %s1, i32 0, i32 0
-  %tmp5 = load i8* %c, align 1
+  %i2 = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 5
+  %tmp = load i32, i32* %i2, align 4
+  %d = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 4
+  %tmp1 = load double, double* %d, align 8
+  %ll = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 3
+  %tmp2 = load i64, i64* %ll, align 8
+  %i = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 2
+  %tmp3 = load i32, i32* %i, align 4
+  %s = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 1
+  %tmp4 = load i16, i16* %s, align 2
+  %c = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 0
+  %tmp5 = load i8, i8* %c, align 1
   tail call void @callee4(i32 %tmp, double %tmp1, i64 %tmp2, i32 %tmp3, i16 signext %tmp4, i8 signext %tmp5, float %f) nounwind
   ret void
 }
@@ -90,10 +90,10 @@ entry:
 ; CHECK: lw  $[[R0:[0-9]+]], 60($sp)
 ; CHECK: sw  $[[R0]], 24($sp)
 
-  %arrayidx = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 0
-  %tmp = load i32* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 3
-  %tmp3 = load i32* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds %struct.S2, %struct.S2* %s2, i32 0, i32 0, i32 0
+  %tmp = load i32, i32* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds %struct.S2, %struct.S2* %s2, i32 0, i32 0, i32 3
+  %tmp3 = load i32, i32* %arrayidx2, align 4
   tail call void @callee4(i32 %tmp, double 2.000000e+00, i64 3, i32 %tmp3, i16 signext 4, i8 signext 5, float 6.000000e+00) nounwind
   ret void
 }
@@ -110,12 +110,12 @@ entry:
 ; CHECK: sw  $[[R0]], 32($sp)
 ; CHECK: sw  $[[R1]], 24($sp)
 
-  %i = getelementptr inbounds %struct.S1* %s1, i32 0, i32 2
-  %tmp = load i32* %i, align 4
-  %i2 = getelementptr inbounds %struct.S1* %s1, i32 0, i32 5
-  %tmp1 = load i32* %i2, align 4
-  %c = getelementptr inbounds %struct.S3* %s3, i32 0, i32 0
-  %tmp2 = load i8* %c, align 1
+  %i = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 2
+  %tmp = load i32, i32* %i, align 4
+  %i2 = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 5
+  %tmp1 = load i32, i32* %i2, align 4
+  %c = getelementptr inbounds %struct.S3, %struct.S3* %s3, i32 0, i32 0
+  %tmp2 = load i8, i8* %c, align 1
   tail call void @callee4(i32 %tmp, double 2.000000e+00, i64 3, i32 %tmp1, i16 signext 4, i8 signext %tmp2, float 6.000000e+00) nounwind
   ret void
 }
diff --git a/test/CodeGen/Mips/o32_cc_vararg.ll b/test/CodeGen/Mips/o32_cc_vararg.ll
index 10972e884ac3..b4597a3214e2 100644
--- a/test/CodeGen/Mips/o32_cc_vararg.ll
+++ b/test/CodeGen/Mips/o32_cc_vararg.ll
@@ -24,7 +24,7 @@ entry:
   store i32 %0, i32* %b, align 4
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_end(i8* %ap2)
-  %tmp = load i32* %b, align 4
+  %tmp = load i32, i32* %b, align 4
   ret i32 %tmp
 
 ; CHECK-LABEL: va1:
@@ -50,7 +50,7 @@ entry:
   store double %0, double* %b, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_end(i8* %ap2)
-  %tmp = load double* %b, align 8
+  %tmp = load double, double* %b, align 8
   ret double %tmp
 
 ; CHECK-LABEL: va2:
@@ -78,7 +78,7 @@ entry:
   store i32 %0, i32* %b, align 4
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_end(i8* %ap2)
-  %tmp = load i32* %b, align 4
+  %tmp = load i32, i32* %b, align 4
   ret i32 %tmp
 
 ; CHECK-LABEL: va3:
@@ -101,7 +101,7 @@ entry:
   store double %0, double* %b, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_end(i8* %ap2)
-  %tmp = load double* %b, align 8
+  %tmp = load double, double* %b, align 8
   ret double %tmp
 
 ; CHECK-LABEL: va4:
@@ -129,7 +129,7 @@ entry:
   store i32 %0, i32* %d, align 4
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_end(i8* %ap2)
-  %tmp = load i32* %d, align 4
+  %tmp = load i32, i32* %d, align 4
   ret i32 %tmp
 
 ; CHECK-LABEL: va5:
@@ -155,7 +155,7 @@ entry:
   store double %0, double* %d, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_end(i8* %ap2)
-  %tmp = load double* %d, align 8
+  %tmp = load double, double* %d, align 8
   ret double %tmp
 
 ; CHECK-LABEL: va6:
@@ -183,7 +183,7 @@ entry:
   store i32 %0, i32* %c, align 4
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_end(i8* %ap2)
-  %tmp = load i32* %c, align 4
+  %tmp = load i32, i32* %c, align 4
   ret i32 %tmp
 
 ; CHECK-LABEL: va7:
@@ -206,7 +206,7 @@ entry:
   store double %0, double* %c, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_end(i8* %ap2)
-  %tmp = load double* %c, align 8
+  %tmp = load double, double* %c, align 8
   ret double %tmp
 
 ; CHECK-LABEL: va8:
@@ -232,7 +232,7 @@ entry:
   store i32 %0, i32* %d, align 4
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_end(i8* %ap2)
-  %tmp = load i32* %d, align 4
+  %tmp = load i32, i32* %d, align 4
   ret i32 %tmp
 
 ; CHECK-LABEL: va9:
@@ -257,7 +257,7 @@ entry:
   store double %0, double* %d, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_end(i8* %ap2)
-  %tmp = load double* %d, align 8
+  %tmp = load double, double* %d, align 8
   ret double %tmp
 
 ; CHECK-LABEL: va10:
diff --git a/test/CodeGen/Mips/octeon.ll b/test/CodeGen/Mips/octeon.ll
index 9d82b74f5b7e..499ce3c1ddbf 100644
--- a/test/CodeGen/Mips/octeon.ll
+++ b/test/CodeGen/Mips/octeon.ll
@@ -1,15 +1,14 @@
-; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefix=OCTEON
-; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=MIPS64
+; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefix=ALL -check-prefix=OCTEON
+; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64
 
 define i64 @addi64(i64 %a, i64 %b) nounwind {
 entry:
-; OCTEON-LABEL: addi64:
+; ALL-LABEL: addi64:
 ; OCTEON: jr      $ra
 ; OCTEON: baddu   $2, $4, $5
-; MIPS64-LABEL: addi64:
-; MIPS64: daddu
-; MIPS64: jr
-; MIPS64: andi
+; MIPS64: daddu   $[[T0:[0-9]+]], $4, $5
+; MIPS64: jr      $ra
+; MIPS64: andi    $2, $[[T0]], 255
   %add = add i64 %a, %b
   %and = and i64 %add, 255
   ret i64 %and
@@ -17,28 +16,26 @@ entry:
 
 define i64 @mul(i64 %a, i64 %b) nounwind {
 entry:
-; OCTEON-LABEL: mul:
+; ALL-LABEL: mul:
 ; OCTEON: jr    $ra
 ; OCTEON: dmul  $2, $4, $5
-; MIPS64-LABEL: mul:
-; MIPS64: dmult
-; MIPS64: jr
-; MIPS64: mflo
+; MIPS64: dmult $4, $5
+; MIPS64: jr    $ra
+; MIPS64: mflo  $2
   %res = mul i64 %a, %b
   ret i64 %res
 }
 
 define i64 @cmpeq(i64 %a, i64 %b) nounwind {
 entry:
-; OCTEON-LABEL: cmpeq:
+; ALL-LABEL: cmpeq:
 ; OCTEON: jr     $ra
 ; OCTEON: seq    $2, $4, $5
-; MIPS64-LABEL: cmpeq:
-; MIPS64: xor    $1, $4, $5
-; MIPS64: sltiu  $1, $1, 1
-; MIPS64: dsll   $1, $1, 32
+; MIPS64: xor    $[[T0:[0-9]+]], $4, $5
+; MIPS64: sltiu  $[[T1:[0-9]+]], $[[T0]], 1
+; MIPS64: dsll   $[[T2:[0-9]+]], $[[T1]], 32
 ; MIPS64: jr     $ra
-; MIPS64: dsrl   $2, $1, 32
+; MIPS64: dsrl   $2, $[[T2]], 32
   %res = icmp eq i64 %a, %b
   %res2 = zext i1 %res to i64
   ret i64 %res2
@@ -46,16 +43,15 @@ entry:
 
 define i64 @cmpeqi(i64 %a) nounwind {
 entry:
-; OCTEON-LABEL: cmpeqi:
+; ALL-LABEL: cmpeqi:
 ; OCTEON: jr     $ra
 ; OCTEON: seqi   $2, $4, 42
-; MIPS64-LABEL: cmpeqi:
-; MIPS64: daddiu $1, $zero, 42
-; MIPS64: xor    $1, $4, $1
-; MIPS64: sltiu  $1, $1, 1
-; MIPS64: dsll   $1, $1, 32
+; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42
+; MIPS64: xor    $[[T1:[0-9]+]], $4, $[[T0]]
+; MIPS64: sltiu  $[[T2:[0-9]+]], $[[T1]], 1
+; MIPS64: dsll   $[[T3:[0-9]+]], $[[T2]], 32
 ; MIPS64: jr     $ra
-; MIPS64: dsrl   $2, $1, 32
+; MIPS64: dsrl   $2, $[[T3]], 32
   %res = icmp eq i64 %a, 42
   %res2 = zext i1 %res to i64
   ret i64 %res2
@@ -63,15 +59,14 @@ entry:
 
 define i64 @cmpne(i64 %a, i64 %b) nounwind {
 entry:
-; OCTEON-LABEL: cmpne:
+; ALL-LABEL: cmpne:
 ; OCTEON: jr     $ra
 ; OCTEON: sne    $2, $4, $5
-; MIPS64-LABEL: cmpne:
-; MIPS64: xor    $1, $4, $5
-; MIPS64: sltu   $1, $zero, $1
-; MIPS64: dsll   $1, $1, 32
+; MIPS64: xor    $[[T0:[0-9]+]], $4, $5
+; MIPS64: sltu   $[[T1:[0-9]+]], $zero, $[[T0]]
+; MIPS64: dsll   $[[T2:[0-9]+]], $[[T1]], 32
 ; MIPS64: jr     $ra
-; MIPS64: dsrl   $2, $1, 32
+; MIPS64: dsrl   $2, $[[T2]], 32
   %res = icmp ne i64 %a, %b
   %res2 = zext i1 %res to i64
   ret i64 %res2
@@ -79,17 +74,84 @@ entry:
 
 define i64 @cmpnei(i64 %a) nounwind {
 entry:
-; OCTEON-LABEL: cmpnei:
+; ALL-LABEL: cmpnei:
 ; OCTEON: jr     $ra
 ; OCTEON: snei   $2, $4, 42
-; MIPS64-LABEL: cmpnei:
-; MIPS64: daddiu $1, $zero, 42
-; MIPS64: xor    $1, $4, $1
-; MIPS64: sltu   $1, $zero, $1
-; MIPS64: dsll   $1, $1, 32
+; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42
+; MIPS64: xor    $[[T1:[0-9]+]], $4, $[[T0]]
+; MIPS64: sltu   $[[T2:[0-9]+]], $zero, $[[T1]]
+; MIPS64: dsll   $[[T3:[0-9]+]], $[[T2]], 32
 ; MIPS64: jr     $ra
-; MIPS64: dsrl   $2, $1, 32
+; MIPS64: dsrl   $2, $[[T3]], 32
   %res = icmp ne i64 %a, 42
   %res2 = zext i1 %res to i64
   ret i64 %res2
 }
+
+define i64 @bbit0(i64 %a) nounwind {
+entry:
+; ALL-LABEL: bbit0:
+; OCTEON: bbit0   $4, 3, $[[BB0:BB[0-9_]+]]
+; MIPS64: andi  $[[T0:[0-9]+]], $4, 8
+; MIPS64: bnez  $[[T0]], $[[BB0:BB[0-9_]+]]
+  %bit = and i64 %a, 8
+  %res = icmp eq i64 %bit, 0
+  br i1 %res, label %endif, label %if
+if:
+  ret i64 48
+
+endif:
+  ret i64 12
+}
+
+define i64 @bbit032(i64 %a) nounwind {
+entry:
+; ALL-LABEL: bbit032:
+; OCTEON: bbit032 $4, 3, $[[BB0:BB[0-9_]+]]
+; MIPS64: daddiu  $[[T0:[0-9]+]], $zero, 1
+; MIPS64: dsll    $[[T1:[0-9]+]], $[[T0]], 35
+; MIPS64: and     $[[T2:[0-9]+]], $4, $[[T1]]
+; MIPS64: bnez    $[[T2]], $[[BB0:BB[0-9_]+]]
+  %bit = and i64 %a, 34359738368
+  %res = icmp eq i64 %bit, 0
+  br i1 %res, label %endif, label %if
+if:
+  ret i64 48
+
+endif:
+  ret i64 12
+}
+
+define i64 @bbit1(i64 %a) nounwind {
+entry:
+; ALL-LABEL: bbit1:
+; OCTEON: bbit1 $4, 3, $[[BB0:BB[0-9_]+]]
+; MIPS64: andi  $[[T0:[0-9]+]], $4, 8
+; MIPS64: beqz  $[[T0]], $[[BB0:BB[0-9_]+]]
+  %bit = and i64 %a, 8
+  %res = icmp ne i64 %bit, 0
+  br i1 %res, label %endif, label %if
+if:
+  ret i64 48
+
+endif:
+  ret i64 12
+}
+
+define i64 @bbit132(i64 %a) nounwind {
+entry:
+; ALL-LABEL: bbit132:
+; OCTEON: bbit132 $4, 3, $[[BB0:BB[0-9_]+]]
+; MIPS64: daddiu  $[[T0:[0-9]+]], $zero, 1
+; MIPS64: dsll    $[[T1:[0-9]+]], $[[T0]], 35
+; MIPS64: and     $[[T2:[0-9]+]], $4, $[[T1]]
+; MIPS64: beqz    $[[T2]], $[[BB0:BB[0-9_]+]]
+  %bit = and i64 %a, 34359738368
+  %res = icmp ne i64 %bit, 0
+  br i1 %res, label %endif, label %if
+if:
+  ret i64 48
+
+endif:
+  ret i64 12
+}
diff --git a/test/CodeGen/Mips/optimize-pic-o0.ll b/test/CodeGen/Mips/optimize-pic-o0.ll
index 554d49e728c7..454bc851484d 100644
--- a/test/CodeGen/Mips/optimize-pic-o0.ll
+++ b/test/CodeGen/Mips/optimize-pic-o0.ll
@@ -10,7 +10,7 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 10
   br i1 %cmp, label %for.body, label %for.end
 
@@ -20,13 +20,13 @@ for.body:                                         ; preds = %for.cond
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %inc = add nsw i32 %1, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %2 = load i32* %retval
+  %2 = load i32, i32* %retval
   ret i32 %2
 }
 
diff --git a/test/CodeGen/Mips/or1.ll b/test/CodeGen/Mips/or1.ll
index b1c36961f92b..51b6ebfe8e3b 100644
--- a/test/CodeGen/Mips/or1.ll
+++ b/test/CodeGen/Mips/or1.ll
@@ -6,11 +6,11 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @x, align 4
-  %1 = load i32* @y, align 4
+  %0 = load i32, i32* @x, align 4
+  %1 = load i32, i32* @y, align 4
   %or = or i32 %0, %1
 ; 16:	or	${{[0-9]+}}, ${{[0-9]+}}
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), i32 %or)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %or)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/prevent-hoisting.ll b/test/CodeGen/Mips/prevent-hoisting.ll
index 210fe3b0f6d8..81b14d7441b3 100644
--- a/test/CodeGen/Mips/prevent-hoisting.ll
+++ b/test/CodeGen/Mips/prevent-hoisting.ll
@@ -46,7 +46,7 @@
 
 define void @readLumaCoeff8x8_CABAC(%struct.img_par* %img, i32 %b8) {
 
-  %1 = load i32* undef, align 4
+  %1 = load i32, i32* undef, align 4
   br i1 false, label %2, label %3
 
 ; <label>:2                                       ; preds = %0
@@ -65,7 +65,7 @@ switch.lookup:                                    ; preds = %3
   br label %6
 
 ; <label>:6                                       ; preds = %5, %4
-  %7 = phi [2 x i8]* [ getelementptr inbounds ([64 x [2 x i8]]* @FIELD_SCAN8x8, i32 0, i32 0), %4 ], [ null, %5 ]
+  %7 = phi [2 x i8]* [ getelementptr inbounds ([64 x [2 x i8]], [64 x [2 x i8]]* @FIELD_SCAN8x8, i32 0, i32 0), %4 ], [ null, %5 ]
   br i1 undef, label %switch.lookup6, label %8
 
 switch.lookup6:                                   ; preds = %6
@@ -77,7 +77,7 @@ switch.lookup6:                                   ; preds = %6
 ; <label>:9                                       ; preds = %8
   %10 = and i32 %b8, 1
   %11 = shl nuw nsw i32 %10, 3
-  %12 = getelementptr inbounds %struct.Slice* null, i32 0, i32 9
+  %12 = getelementptr inbounds %struct.Slice, %struct.Slice* null, i32 0, i32 9
   br i1 undef, label %.preheader, label %.preheader11
 
 .preheader11:                                     ; preds = %21, %9
@@ -92,19 +92,19 @@ switch.lookup6:                                   ; preds = %6
   br label %15
 
 ; <label>:15                                      ; preds = %14, %13
-  %16 = getelementptr inbounds [0 x [20 x i32]]* @assignSE2partition, i32 0, i32 %1, i32 undef
-  %17 = load i32* %16, align 4
-  %18 = getelementptr inbounds %struct.datapartition* null, i32 %17, i32 2
-  %19 = load i32 (%struct.syntaxelement*, %struct.img_par*, %struct.datapartition*)** %18, align 4
+  %16 = getelementptr inbounds [0 x [20 x i32]], [0 x [20 x i32]]* @assignSE2partition, i32 0, i32 %1, i32 undef
+  %17 = load i32, i32* %16, align 4
+  %18 = getelementptr inbounds %struct.datapartition, %struct.datapartition* null, i32 %17, i32 2
+  %19 = load i32 (%struct.syntaxelement*, %struct.img_par*, %struct.datapartition*)*, i32 (%struct.syntaxelement*, %struct.img_par*, %struct.datapartition*)** %18, align 4
   %20 = call i32 %19(%struct.syntaxelement* undef, %struct.img_par* %img, %struct.datapartition* undef)
   br i1 false, label %.loopexit, label %21
 
 ; <label>:21                                      ; preds = %15
   %22 = add i32 %coef_ctr.013, 1
   %23 = add i32 %22, 0
-  %24 = getelementptr inbounds [2 x i8]* %7, i32 %23, i32 0
+  %24 = getelementptr inbounds [2 x i8], [2 x i8]* %7, i32 %23, i32 0
   %25 = add nsw i32 0, %11
-  %26 = getelementptr inbounds %struct.img_par* %img, i32 0, i32 27, i32 undef, i32 %25
+  %26 = getelementptr inbounds %struct.img_par, %struct.img_par* %img, i32 0, i32 27, i32 undef, i32 %25
   store i32 0, i32* %26, align 4
   %27 = add nsw i32 %k.014, 1
   %28 = icmp slt i32 %27, 65
@@ -122,21 +122,21 @@ switch.lookup6:                                   ; preds = %6
   br label %31
 
 ; <label>:31                                      ; preds = %30, %29
-  %32 = getelementptr inbounds [0 x [20 x i32]]* @assignSE2partition, i32 0, i32 %1, i32 undef
-  %33 = load i32* %32, align 4
-  %34 = getelementptr inbounds %struct.datapartition* null, i32 %33
+  %32 = getelementptr inbounds [0 x [20 x i32]], [0 x [20 x i32]]* @assignSE2partition, i32 0, i32 %1, i32 undef
+  %33 = load i32, i32* %32, align 4
+  %34 = getelementptr inbounds %struct.datapartition, %struct.datapartition* null, i32 %33
   %35 = call i32 undef(%struct.syntaxelement* undef, %struct.img_par* %img, %struct.datapartition* %34)
   br i1 false, label %.loopexit, label %36
 
 ; <label>:36                                      ; preds = %31
-  %37 = load i32* undef, align 4
+  %37 = load i32, i32* undef, align 4
   %38 = add i32 %coef_ctr.29, 1
   %39 = add i32 %38, %37
-  %40 = getelementptr inbounds [2 x i8]* %7, i32 %39, i32 0
-  %41 = load i8* %40, align 1
+  %40 = getelementptr inbounds [2 x i8], [2 x i8]* %7, i32 %39, i32 0
+  %41 = load i8, i8* %40, align 1
   %42 = zext i8 %41 to i32
   %43 = add nsw i32 %42, %11
-  %44 = getelementptr inbounds %struct.img_par* %img, i32 0, i32 27, i32 undef, i32 %43
+  %44 = getelementptr inbounds %struct.img_par, %struct.img_par* %img, i32 0, i32 27, i32 undef, i32 %43
   store i32 0, i32* %44, align 4
   %45 = add nsw i32 %k.110, 1
   %46 = icmp slt i32 %45, 65
diff --git a/test/CodeGen/Mips/private.ll b/test/CodeGen/Mips/private.ll
index 058db0bb977a..5907dbd644ae 100644
--- a/test/CodeGen/Mips/private.ll
+++ b/test/CodeGen/Mips/private.ll
@@ -15,6 +15,6 @@ define i32 @bar() {
 ; CHECK: lw $[[R0:[0-9]+]], %got($baz)($
 ; CHECK: lw ${{[0-9]+}}, %lo($baz)($[[R0]])
   call void @foo()
-  %1 = load i32* @baz, align 4
+  %1 = load i32, i32* @baz, align 4
   ret i32 %1
 }
diff --git a/test/CodeGen/Mips/ra-allocatable.ll b/test/CodeGen/Mips/ra-allocatable.ll
index afc5cb0c2556..048d4325a411 100644
--- a/test/CodeGen/Mips/ra-allocatable.ll
+++ b/test/CodeGen/Mips/ra-allocatable.ll
@@ -98,186 +98,186 @@ entry:
 ; CHECK: lw  $ra, {{[0-9]+}}($sp)            # 4-byte Folded Reload
 ; CHECK: jr  $ra
 
-  %0 = load i32* @a0, align 4
-  %1 = load i32** @b0, align 4
+  %0 = load i32, i32* @a0, align 4
+  %1 = load i32*, i32** @b0, align 4
   store i32 %0, i32* %1, align 4
-  %2 = load i32* @a1, align 4
-  %3 = load i32** @b1, align 4
+  %2 = load i32, i32* @a1, align 4
+  %3 = load i32*, i32** @b1, align 4
   store i32 %2, i32* %3, align 4
-  %4 = load i32* @a2, align 4
-  %5 = load i32** @b2, align 4
+  %4 = load i32, i32* @a2, align 4
+  %5 = load i32*, i32** @b2, align 4
   store i32 %4, i32* %5, align 4
-  %6 = load i32* @a3, align 4
-  %7 = load i32** @b3, align 4
+  %6 = load i32, i32* @a3, align 4
+  %7 = load i32*, i32** @b3, align 4
   store i32 %6, i32* %7, align 4
-  %8 = load i32* @a4, align 4
-  %9 = load i32** @b4, align 4
+  %8 = load i32, i32* @a4, align 4
+  %9 = load i32*, i32** @b4, align 4
   store i32 %8, i32* %9, align 4
-  %10 = load i32* @a5, align 4
-  %11 = load i32** @b5, align 4
+  %10 = load i32, i32* @a5, align 4
+  %11 = load i32*, i32** @b5, align 4
   store i32 %10, i32* %11, align 4
-  %12 = load i32* @a6, align 4
-  %13 = load i32** @b6, align 4
+  %12 = load i32, i32* @a6, align 4
+  %13 = load i32*, i32** @b6, align 4
   store i32 %12, i32* %13, align 4
-  %14 = load i32* @a7, align 4
-  %15 = load i32** @b7, align 4
+  %14 = load i32, i32* @a7, align 4
+  %15 = load i32*, i32** @b7, align 4
   store i32 %14, i32* %15, align 4
-  %16 = load i32* @a8, align 4
-  %17 = load i32** @b8, align 4
+  %16 = load i32, i32* @a8, align 4
+  %17 = load i32*, i32** @b8, align 4
   store i32 %16, i32* %17, align 4
-  %18 = load i32* @a9, align 4
-  %19 = load i32** @b9, align 4
+  %18 = load i32, i32* @a9, align 4
+  %19 = load i32*, i32** @b9, align 4
   store i32 %18, i32* %19, align 4
-  %20 = load i32* @a10, align 4
-  %21 = load i32** @b10, align 4
+  %20 = load i32, i32* @a10, align 4
+  %21 = load i32*, i32** @b10, align 4
   store i32 %20, i32* %21, align 4
-  %22 = load i32* @a11, align 4
-  %23 = load i32** @b11, align 4
+  %22 = load i32, i32* @a11, align 4
+  %23 = load i32*, i32** @b11, align 4
   store i32 %22, i32* %23, align 4
-  %24 = load i32* @a12, align 4
-  %25 = load i32** @b12, align 4
+  %24 = load i32, i32* @a12, align 4
+  %25 = load i32*, i32** @b12, align 4
   store i32 %24, i32* %25, align 4
-  %26 = load i32* @a13, align 4
-  %27 = load i32** @b13, align 4
+  %26 = load i32, i32* @a13, align 4
+  %27 = load i32*, i32** @b13, align 4
   store i32 %26, i32* %27, align 4
-  %28 = load i32* @a14, align 4
-  %29 = load i32** @b14, align 4
+  %28 = load i32, i32* @a14, align 4
+  %29 = load i32*, i32** @b14, align 4
   store i32 %28, i32* %29, align 4
-  %30 = load i32* @a15, align 4
-  %31 = load i32** @b15, align 4
+  %30 = load i32, i32* @a15, align 4
+  %31 = load i32*, i32** @b15, align 4
   store i32 %30, i32* %31, align 4
-  %32 = load i32* @a16, align 4
-  %33 = load i32** @b16, align 4
+  %32 = load i32, i32* @a16, align 4
+  %33 = load i32*, i32** @b16, align 4
   store i32 %32, i32* %33, align 4
-  %34 = load i32* @a17, align 4
-  %35 = load i32** @b17, align 4
+  %34 = load i32, i32* @a17, align 4
+  %35 = load i32*, i32** @b17, align 4
   store i32 %34, i32* %35, align 4
-  %36 = load i32* @a18, align 4
-  %37 = load i32** @b18, align 4
+  %36 = load i32, i32* @a18, align 4
+  %37 = load i32*, i32** @b18, align 4
   store i32 %36, i32* %37, align 4
-  %38 = load i32* @a19, align 4
-  %39 = load i32** @b19, align 4
+  %38 = load i32, i32* @a19, align 4
+  %39 = load i32*, i32** @b19, align 4
   store i32 %38, i32* %39, align 4
-  %40 = load i32* @a20, align 4
-  %41 = load i32** @b20, align 4
+  %40 = load i32, i32* @a20, align 4
+  %41 = load i32*, i32** @b20, align 4
   store i32 %40, i32* %41, align 4
-  %42 = load i32* @a21, align 4
-  %43 = load i32** @b21, align 4
+  %42 = load i32, i32* @a21, align 4
+  %43 = load i32*, i32** @b21, align 4
   store i32 %42, i32* %43, align 4
-  %44 = load i32* @a22, align 4
-  %45 = load i32** @b22, align 4
+  %44 = load i32, i32* @a22, align 4
+  %45 = load i32*, i32** @b22, align 4
   store i32 %44, i32* %45, align 4
-  %46 = load i32* @a23, align 4
-  %47 = load i32** @b23, align 4
+  %46 = load i32, i32* @a23, align 4
+  %47 = load i32*, i32** @b23, align 4
   store i32 %46, i32* %47, align 4
-  %48 = load i32* @a24, align 4
-  %49 = load i32** @b24, align 4
+  %48 = load i32, i32* @a24, align 4
+  %49 = load i32*, i32** @b24, align 4
   store i32 %48, i32* %49, align 4
-  %50 = load i32* @a25, align 4
-  %51 = load i32** @b25, align 4
+  %50 = load i32, i32* @a25, align 4
+  %51 = load i32*, i32** @b25, align 4
   store i32 %50, i32* %51, align 4
-  %52 = load i32* @a26, align 4
-  %53 = load i32** @b26, align 4
+  %52 = load i32, i32* @a26, align 4
+  %53 = load i32*, i32** @b26, align 4
   store i32 %52, i32* %53, align 4
-  %54 = load i32* @a27, align 4
-  %55 = load i32** @b27, align 4
+  %54 = load i32, i32* @a27, align 4
+  %55 = load i32*, i32** @b27, align 4
   store i32 %54, i32* %55, align 4
-  %56 = load i32* @a28, align 4
-  %57 = load i32** @b28, align 4
+  %56 = load i32, i32* @a28, align 4
+  %57 = load i32*, i32** @b28, align 4
   store i32 %56, i32* %57, align 4
-  %58 = load i32* @a29, align 4
-  %59 = load i32** @b29, align 4
+  %58 = load i32, i32* @a29, align 4
+  %59 = load i32*, i32** @b29, align 4
   store i32 %58, i32* %59, align 4
-  %60 = load i32* @a0, align 4
-  %61 = load i32** @c0, align 4
+  %60 = load i32, i32* @a0, align 4
+  %61 = load i32*, i32** @c0, align 4
   store i32 %60, i32* %61, align 4
-  %62 = load i32* @a1, align 4
-  %63 = load i32** @c1, align 4
+  %62 = load i32, i32* @a1, align 4
+  %63 = load i32*, i32** @c1, align 4
   store i32 %62, i32* %63, align 4
-  %64 = load i32* @a2, align 4
-  %65 = load i32** @c2, align 4
+  %64 = load i32, i32* @a2, align 4
+  %65 = load i32*, i32** @c2, align 4
   store i32 %64, i32* %65, align 4
-  %66 = load i32* @a3, align 4
-  %67 = load i32** @c3, align 4
+  %66 = load i32, i32* @a3, align 4
+  %67 = load i32*, i32** @c3, align 4
   store i32 %66, i32* %67, align 4
-  %68 = load i32* @a4, align 4
-  %69 = load i32** @c4, align 4
+  %68 = load i32, i32* @a4, align 4
+  %69 = load i32*, i32** @c4, align 4
   store i32 %68, i32* %69, align 4
-  %70 = load i32* @a5, align 4
-  %71 = load i32** @c5, align 4
+  %70 = load i32, i32* @a5, align 4
+  %71 = load i32*, i32** @c5, align 4
   store i32 %70, i32* %71, align 4
-  %72 = load i32* @a6, align 4
-  %73 = load i32** @c6, align 4
+  %72 = load i32, i32* @a6, align 4
+  %73 = load i32*, i32** @c6, align 4
   store i32 %72, i32* %73, align 4
-  %74 = load i32* @a7, align 4
-  %75 = load i32** @c7, align 4
+  %74 = load i32, i32* @a7, align 4
+  %75 = load i32*, i32** @c7, align 4
   store i32 %74, i32* %75, align 4
-  %76 = load i32* @a8, align 4
-  %77 = load i32** @c8, align 4
+  %76 = load i32, i32* @a8, align 4
+  %77 = load i32*, i32** @c8, align 4
   store i32 %76, i32* %77, align 4
-  %78 = load i32* @a9, align 4
-  %79 = load i32** @c9, align 4
+  %78 = load i32, i32* @a9, align 4
+  %79 = load i32*, i32** @c9, align 4
   store i32 %78, i32* %79, align 4
-  %80 = load i32* @a10, align 4
-  %81 = load i32** @c10, align 4
+  %80 = load i32, i32* @a10, align 4
+  %81 = load i32*, i32** @c10, align 4
   store i32 %80, i32* %81, align 4
-  %82 = load i32* @a11, align 4
-  %83 = load i32** @c11, align 4
+  %82 = load i32, i32* @a11, align 4
+  %83 = load i32*, i32** @c11, align 4
   store i32 %82, i32* %83, align 4
-  %84 = load i32* @a12, align 4
-  %85 = load i32** @c12, align 4
+  %84 = load i32, i32* @a12, align 4
+  %85 = load i32*, i32** @c12, align 4
   store i32 %84, i32* %85, align 4
-  %86 = load i32* @a13, align 4
-  %87 = load i32** @c13, align 4
+  %86 = load i32, i32* @a13, align 4
+  %87 = load i32*, i32** @c13, align 4
   store i32 %86, i32* %87, align 4
-  %88 = load i32* @a14, align 4
-  %89 = load i32** @c14, align 4
+  %88 = load i32, i32* @a14, align 4
+  %89 = load i32*, i32** @c14, align 4
   store i32 %88, i32* %89, align 4
-  %90 = load i32* @a15, align 4
-  %91 = load i32** @c15, align 4
+  %90 = load i32, i32* @a15, align 4
+  %91 = load i32*, i32** @c15, align 4
   store i32 %90, i32* %91, align 4
-  %92 = load i32* @a16, align 4
-  %93 = load i32** @c16, align 4
+  %92 = load i32, i32* @a16, align 4
+  %93 = load i32*, i32** @c16, align 4
   store i32 %92, i32* %93, align 4
-  %94 = load i32* @a17, align 4
-  %95 = load i32** @c17, align 4
+  %94 = load i32, i32* @a17, align 4
+  %95 = load i32*, i32** @c17, align 4
   store i32 %94, i32* %95, align 4
-  %96 = load i32* @a18, align 4
-  %97 = load i32** @c18, align 4
+  %96 = load i32, i32* @a18, align 4
+  %97 = load i32*, i32** @c18, align 4
   store i32 %96, i32* %97, align 4
-  %98 = load i32* @a19, align 4
-  %99 = load i32** @c19, align 4
+  %98 = load i32, i32* @a19, align 4
+  %99 = load i32*, i32** @c19, align 4
   store i32 %98, i32* %99, align 4
-  %100 = load i32* @a20, align 4
-  %101 = load i32** @c20, align 4
+  %100 = load i32, i32* @a20, align 4
+  %101 = load i32*, i32** @c20, align 4
   store i32 %100, i32* %101, align 4
-  %102 = load i32* @a21, align 4
-  %103 = load i32** @c21, align 4
+  %102 = load i32, i32* @a21, align 4
+  %103 = load i32*, i32** @c21, align 4
   store i32 %102, i32* %103, align 4
-  %104 = load i32* @a22, align 4
-  %105 = load i32** @c22, align 4
+  %104 = load i32, i32* @a22, align 4
+  %105 = load i32*, i32** @c22, align 4
   store i32 %104, i32* %105, align 4
-  %106 = load i32* @a23, align 4
-  %107 = load i32** @c23, align 4
+  %106 = load i32, i32* @a23, align 4
+  %107 = load i32*, i32** @c23, align 4
   store i32 %106, i32* %107, align 4
-  %108 = load i32* @a24, align 4
-  %109 = load i32** @c24, align 4
+  %108 = load i32, i32* @a24, align 4
+  %109 = load i32*, i32** @c24, align 4
   store i32 %108, i32* %109, align 4
-  %110 = load i32* @a25, align 4
-  %111 = load i32** @c25, align 4
+  %110 = load i32, i32* @a25, align 4
+  %111 = load i32*, i32** @c25, align 4
   store i32 %110, i32* %111, align 4
-  %112 = load i32* @a26, align 4
-  %113 = load i32** @c26, align 4
+  %112 = load i32, i32* @a26, align 4
+  %113 = load i32*, i32** @c26, align 4
   store i32 %112, i32* %113, align 4
-  %114 = load i32* @a27, align 4
-  %115 = load i32** @c27, align 4
+  %114 = load i32, i32* @a27, align 4
+  %115 = load i32*, i32** @c27, align 4
   store i32 %114, i32* %115, align 4
-  %116 = load i32* @a28, align 4
-  %117 = load i32** @c28, align 4
+  %116 = load i32, i32* @a28, align 4
+  %117 = load i32*, i32** @c28, align 4
   store i32 %116, i32* %117, align 4
-  %118 = load i32* @a29, align 4
-  %119 = load i32** @c29, align 4
+  %118 = load i32, i32* @a29, align 4
+  %119 = load i32*, i32** @c29, align 4
   store i32 %118, i32* %119, align 4
-  %120 = load i32* @a0, align 4
+  %120 = load i32, i32* @a0, align 4
   ret i32 %120
 }
diff --git a/test/CodeGen/Mips/rdhwr-directives.ll b/test/CodeGen/Mips/rdhwr-directives.ll
index 27010d4d3699..ebc91ea4459e 100644
--- a/test/CodeGen/Mips/rdhwr-directives.ll
+++ b/test/CodeGen/Mips/rdhwr-directives.ll
@@ -9,7 +9,7 @@ entry:
 ; CHECK: rdhwr 
 ; CHECK: .set  pop
 
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   ret i32 %0
 }
 
diff --git a/test/CodeGen/Mips/rem.ll b/test/CodeGen/Mips/rem.ll
index b18f85dcbecf..70f957ce15f6 100644
--- a/test/CodeGen/Mips/rem.ll
+++ b/test/CodeGen/Mips/rem.ll
@@ -7,8 +7,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @iiii, align 4
-  %1 = load i32* @jjjj, align 4
+  %0 = load i32, i32* @iiii, align 4
+  %1 = load i32, i32* @jjjj, align 4
   %rem = srem i32 %0, %1
 ; 16:	div	$zero, ${{[0-9]+}}, ${{[0-9]+}}
 ; 16: 	mfhi	${{[0-9]+}}
diff --git a/test/CodeGen/Mips/remat-immed-load.ll b/test/CodeGen/Mips/remat-immed-load.ll
index b53b156e9eec..3d37b43bbc63 100644
--- a/test/CodeGen/Mips/remat-immed-load.ll
+++ b/test/CodeGen/Mips/remat-immed-load.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
-; RUN: llc -march=mips64el -mcpu=mips4 -mattr=n64 < %s | FileCheck %s -check-prefix=64
-; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | FileCheck %s -check-prefix=64
+; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 < %s | FileCheck %s -check-prefix=64
+; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s -check-prefix=64
 
 define void @f0() nounwind {
 entry:
diff --git a/test/CodeGen/Mips/remu.ll b/test/CodeGen/Mips/remu.ll
index 472503c38403..12679727952f 100644
--- a/test/CodeGen/Mips/remu.ll
+++ b/test/CodeGen/Mips/remu.ll
@@ -7,8 +7,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @iiii, align 4
-  %1 = load i32* @jjjj, align 4
+  %0 = load i32, i32* @iiii, align 4
+  %1 = load i32, i32* @jjjj, align 4
   %rem = urem i32 %0, %1
 ; 16:	divu	$zero, ${{[0-9]+}}, ${{[0-9]+}}
 ; 16: 	mfhi	${{[0-9]+}}
diff --git a/test/CodeGen/Mips/return-vector.ll b/test/CodeGen/Mips/return-vector.ll
index 0e0d51587541..3870fe092156 100644
--- a/test/CodeGen/Mips/return-vector.ll
+++ b/test/CodeGen/Mips/return-vector.ll
@@ -12,7 +12,7 @@ declare <4 x double> @d4(...)
 
 define i32 @call_i8() {
 entry:
-  %call = call <8 x i32> (...)* @i8()
+  %call = call <8 x i32> (...) @i8()
   %v0 = extractelement <8 x i32> %call, i32 0
   %v1 = extractelement <8 x i32> %call, i32 1
   %v2 = extractelement <8 x i32> %call, i32 2
@@ -46,7 +46,7 @@ entry:
 
 define float @call_f4() {
 entry:
-  %call = call <4 x float> (...)* @f4()
+  %call = call <4 x float> (...) @f4()
   %v0 = extractelement <4 x float> %call, i32 0
   %v1 = extractelement <4 x float> %call, i32 1
   %v2 = extractelement <4 x float> %call, i32 2
@@ -68,7 +68,7 @@ entry:
 
 define double @call_d4() {
 entry:
-  %call = call <4 x double> (...)* @d4()
+  %call = call <4 x double> (...) @d4()
   %v0 = extractelement <4 x double> %call, i32 0
   %v1 = extractelement <4 x double> %call, i32 1
   %v2 = extractelement <4 x double> %call, i32 2
@@ -99,7 +99,7 @@ declare <2 x double> @d2(...)
 
 define i32 @call_i4() {
 entry:
-  %call = call <4 x i32> (...)* @i4()
+  %call = call <4 x i32> (...) @i4()
   %v0 = extractelement <4 x i32> %call, i32 0
   %v1 = extractelement <4 x i32> %call, i32 1
   %v2 = extractelement <4 x i32> %call, i32 2
@@ -120,7 +120,7 @@ entry:
 
 define float @call_f2() {
 entry:
-  %call = call <2 x float> (...)* @f2()
+  %call = call <2 x float> (...) @f2()
   %v0 = extractelement <2 x float> %call, i32 0
   %v1 = extractelement <2 x float> %call, i32 1
   %add1 = fadd float %v0, %v1
@@ -135,7 +135,7 @@ entry:
 
 define double @call_d2() {
 entry:
-  %call = call <2 x double> (...)* @d2()
+  %call = call <2 x double> (...) @d2()
   %v0 = extractelement <2 x double> %call, i32 0
   %v1 = extractelement <2 x double> %call, i32 1
   %add1 = fadd double %v0, %v1
diff --git a/test/CodeGen/Mips/s2rem.ll b/test/CodeGen/Mips/s2rem.ll
index 9edb5be2771e..65e48fe57c92 100644
--- a/test/CodeGen/Mips/s2rem.ll
+++ b/test/CodeGen/Mips/s2rem.ll
@@ -56,7 +56,7 @@ declare double @d() #1
 ; Function Attrs: nounwind
 define void @fft() #0 {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   %call = call float @ff(float %0)
   store float %call, float* @x, align 4
   ret void
@@ -71,7 +71,7 @@ declare float @ff(float) #1
 ; Function Attrs: nounwind
 define void @vft() #0 {
 entry:
-  %0 = load float* @x, align 4
+  %0 = load float, float* @x, align 4
   call void @vf(float %0)
   ret void
 ; PIC: 	.ent	vft
diff --git a/test/CodeGen/Mips/sb1.ll b/test/CodeGen/Mips/sb1.ll
index e1a28d459548..d2e8510024e5 100644
--- a/test/CodeGen/Mips/sb1.ll
+++ b/test/CodeGen/Mips/sb1.ll
@@ -6,14 +6,14 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %conv = trunc i32 %0 to i8
   store i8 %conv, i8* @c, align 1
-  %1 = load i32* @i, align 4
-  %2 = load i8* @c, align 1
+  %1 = load i32, i32* @i, align 4
+  %2 = load i8, i8* @c, align 1
   %conv1 = sext i8 %2 to i32
 ; 16:	sb	${{[0-9]+}}, 0(${{[0-9]+}})
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %1, i32 %conv1)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0), i32 %1, i32 %conv1)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/sel1c.ll b/test/CodeGen/Mips/sel1c.ll
index edd2e3e43b79..6753af106e0f 100644
--- a/test/CodeGen/Mips/sel1c.ll
+++ b/test/CodeGen/Mips/sel1c.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=cond-b-short
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=cond-b-short
 
 @i = global i32 1, align 4
 @j = global i32 2, align 4
@@ -7,8 +7,8 @@
 ; Function Attrs: nounwind optsize
 define void @t() #0 {
 entry:
-  %0 = load i32* @i, align 4
-  %1 = load i32* @j, align 4
+  %0 = load i32, i32* @i, align 4
+  %1 = load i32, i32* @j, align 4
   %cmp = icmp eq i32 %0, %1
   %cond = select i1 %cmp, i32 1, i32 3
   store i32 %cond, i32* @k, align 4
diff --git a/test/CodeGen/Mips/sel2c.ll b/test/CodeGen/Mips/sel2c.ll
index 4b211245f46e..987cccad5bf4 100644
--- a/test/CodeGen/Mips/sel2c.ll
+++ b/test/CodeGen/Mips/sel2c.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=cond-b-short
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands   < %s | FileCheck %s -check-prefix=cond-b-short
 
 @i = global i32 1, align 4
 @j = global i32 2, align 4
@@ -7,8 +7,8 @@
 ; Function Attrs: nounwind optsize
 define void @t() #0 {
 entry:
-  %0 = load i32* @i, align 4
-  %1 = load i32* @j, align 4
+  %0 = load i32, i32* @i, align 4
+  %1 = load i32, i32* @j, align 4
   %cmp = icmp ne i32 %0, %1
   %cond = select i1 %cmp, i32 1, i32 3
   store i32 %cond, i32* @k, align 4
diff --git a/test/CodeGen/Mips/selTBteqzCmpi.ll b/test/CodeGen/Mips/selTBteqzCmpi.ll
index 9cb8227f9d2b..5a72ea01073c 100644
--- a/test/CodeGen/Mips/selTBteqzCmpi.ll
+++ b/test/CodeGen/Mips/selTBteqzCmpi.ll
@@ -8,10 +8,10 @@
 
 define void @t() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp eq i32 %0, 10
-  %1 = load i32* @i, align 4
-  %2 = load i32* @j, align 4
+  %1 = load i32, i32* @i, align 4
+  %2 = load i32, i32* @j, align 4
   %cond = select i1 %cmp, i32 %1, i32 %2
   store i32 %cond, i32* @i, align 4
   ret void
diff --git a/test/CodeGen/Mips/selTBtnezCmpi.ll b/test/CodeGen/Mips/selTBtnezCmpi.ll
index bd334f59d33b..b6407e67f27a 100644
--- a/test/CodeGen/Mips/selTBtnezCmpi.ll
+++ b/test/CodeGen/Mips/selTBtnezCmpi.ll
@@ -8,10 +8,10 @@
 
 define void @t() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp ne i32 %0, 10
-  %1 = load i32* @i, align 4
-  %2 = load i32* @j, align 4
+  %1 = load i32, i32* @i, align 4
+  %2 = load i32, i32* @j, align 4
   %cond = select i1 %cmp, i32 %1, i32 %2
   store i32 %cond, i32* @i, align 4
   ret void
diff --git a/test/CodeGen/Mips/selTBtnezSlti.ll b/test/CodeGen/Mips/selTBtnezSlti.ll
index 593f6f274eb3..2f1cdb866294 100644
--- a/test/CodeGen/Mips/selTBtnezSlti.ll
+++ b/test/CodeGen/Mips/selTBtnezSlti.ll
@@ -8,10 +8,10 @@
 
 define void @t() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp slt i32 %0, 10
-  %1 = load i32* @j, align 4
-  %2 = load i32* @i, align 4
+  %1 = load i32, i32* @j, align 4
+  %2 = load i32, i32* @i, align 4
   %cond = select i1 %cmp, i32 %1, i32 %2
   store i32 %cond, i32* @i, align 4
   ret void
diff --git a/test/CodeGen/Mips/select.ll b/test/CodeGen/Mips/select.ll
index d6e1826c30c8..96bd3782c058 100644
--- a/test/CodeGen/Mips/select.ll
+++ b/test/CodeGen/Mips/select.ll
@@ -700,8 +700,8 @@ entry:
 ; 64R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
 ; 64R6:          or $2, $[[NE]], $[[EQ]]
 
-  %tmp = load double* @d2, align 8
-  %tmp1 = load double* @d3, align 8
+  %tmp = load double, double* @d2, align 8
+  %tmp1 = load double, double* @d3, align 8
   %cmp = fcmp oeq double %tmp, %tmp1
   %cond = select i1 %cmp, i32 %f0, i32 %f1
   ret i32 %cond
@@ -777,8 +777,8 @@ entry:
 ; 64R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
 ; 64R6:          or $2, $[[NE]], $[[EQ]]
 
-  %tmp = load double* @d2, align 8
-  %tmp1 = load double* @d3, align 8
+  %tmp = load double, double* @d2, align 8
+  %tmp1 = load double, double* @d3, align 8
   %cmp = fcmp olt double %tmp, %tmp1
   %cond = select i1 %cmp, i32 %f0, i32 %f1
   ret i32 %cond
@@ -854,8 +854,8 @@ entry:
 ; 64R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
 ; 64R6:          or $2, $[[NE]], $[[EQ]]
 
-  %tmp = load double* @d2, align 8
-  %tmp1 = load double* @d3, align 8
+  %tmp = load double, double* @d2, align 8
+  %tmp1 = load double, double* @d3, align 8
   %cmp = fcmp ogt double %tmp, %tmp1
   %cond = select i1 %cmp, i32 %f0, i32 %f1
   ret i32 %cond
diff --git a/test/CodeGen/Mips/seleq.ll b/test/CodeGen/Mips/seleq.ll
index 9af422fa1bdb..bd25358fb9e6 100644
--- a/test/CodeGen/Mips/seleq.ll
+++ b/test/CodeGen/Mips/seleq.ll
@@ -12,65 +12,65 @@
 
 define void @calc_seleq() nounwind {
 entry:
-  %0 = load i32* @a, align 4
-  %1 = load i32* @b, align 4
+  %0 = load i32, i32* @a, align 4
+  %1 = load i32, i32* @b, align 4
   %cmp = icmp eq i32 %0, %1
   br i1 %cmp, label %cond.true, label %cond.false
 
 cond.true:                                        ; preds = %entry
-  %2 = load i32* @f, align 4
+  %2 = load i32, i32* @f, align 4
   br label %cond.end
 
 cond.false:                                       ; preds = %entry
-  %3 = load i32* @t, align 4
+  %3 = load i32, i32* @t, align 4
   br label %cond.end
 
 cond.end:                                         ; preds = %cond.false, %cond.true
   %cond = phi i32 [ %2, %cond.true ], [ %3, %cond.false ]
   store i32 %cond, i32* @z1, align 4
-  %4 = load i32* @b, align 4
-  %5 = load i32* @a, align 4
+  %4 = load i32, i32* @b, align 4
+  %5 = load i32, i32* @a, align 4
   %cmp1 = icmp eq i32 %4, %5
   br i1 %cmp1, label %cond.true2, label %cond.false3
 
 cond.true2:                                       ; preds = %cond.end
-  %6 = load i32* @f, align 4
+  %6 = load i32, i32* @f, align 4
   br label %cond.end4
 
 cond.false3:                                      ; preds = %cond.end
-  %7 = load i32* @t, align 4
+  %7 = load i32, i32* @t, align 4
   br label %cond.end4
 
 cond.end4:                                        ; preds = %cond.false3, %cond.true2
   %cond5 = phi i32 [ %6, %cond.true2 ], [ %7, %cond.false3 ]
   store i32 %cond5, i32* @z2, align 4
-  %8 = load i32* @c, align 4
-  %9 = load i32* @a, align 4
+  %8 = load i32, i32* @c, align 4
+  %9 = load i32, i32* @a, align 4
   %cmp6 = icmp eq i32 %8, %9
   br i1 %cmp6, label %cond.true7, label %cond.false8
 
 cond.true7:                                       ; preds = %cond.end4
-  %10 = load i32* @t, align 4
+  %10 = load i32, i32* @t, align 4
   br label %cond.end9
 
 cond.false8:                                      ; preds = %cond.end4
-  %11 = load i32* @f, align 4
+  %11 = load i32, i32* @f, align 4
   br label %cond.end9
 
 cond.end9:                                        ; preds = %cond.false8, %cond.true7
   %cond10 = phi i32 [ %10, %cond.true7 ], [ %11, %cond.false8 ]
   store i32 %cond10, i32* @z3, align 4
-  %12 = load i32* @a, align 4
-  %13 = load i32* @c, align 4
+  %12 = load i32, i32* @a, align 4
+  %13 = load i32, i32* @c, align 4
   %cmp11 = icmp eq i32 %12, %13
   br i1 %cmp11, label %cond.true12, label %cond.false13
 
 cond.true12:                                      ; preds = %cond.end9
-  %14 = load i32* @t, align 4
+  %14 = load i32, i32* @t, align 4
   br label %cond.end14
 
 cond.false13:                                     ; preds = %cond.end9
-  %15 = load i32* @f, align 4
+  %15 = load i32, i32* @f, align 4
   br label %cond.end14
 
 cond.end14:                                       ; preds = %cond.false13, %cond.true12
diff --git a/test/CodeGen/Mips/seleqk.ll b/test/CodeGen/Mips/seleqk.ll
index 3ca622d5d8fe..2eeaa9e33738 100644
--- a/test/CodeGen/Mips/seleqk.ll
+++ b/test/CodeGen/Mips/seleqk.ll
@@ -12,61 +12,61 @@
 
 define void @calc_seleqk() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp eq i32 %0, 1
   br i1 %cmp, label %cond.true, label %cond.false
 
 cond.true:                                        ; preds = %entry
-  %1 = load i32* @t, align 4
+  %1 = load i32, i32* @t, align 4
   br label %cond.end
 
 cond.false:                                       ; preds = %entry
-  %2 = load i32* @f, align 4
+  %2 = load i32, i32* @f, align 4
   br label %cond.end
 
 cond.end:                                         ; preds = %cond.false, %cond.true
   %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ]
   store i32 %cond, i32* @z1, align 4
-  %3 = load i32* @a, align 4
+  %3 = load i32, i32* @a, align 4
   %cmp1 = icmp eq i32 %3, 1000
   br i1 %cmp1, label %cond.true2, label %cond.false3
 
 cond.true2:                                       ; preds = %cond.end
-  %4 = load i32* @f, align 4
+  %4 = load i32, i32* @f, align 4
   br label %cond.end4
 
 cond.false3:                                      ; preds = %cond.end
-  %5 = load i32* @t, align 4
+  %5 = load i32, i32* @t, align 4
   br label %cond.end4
 
 cond.end4:                                        ; preds = %cond.false3, %cond.true2
   %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ]
   store i32 %cond5, i32* @z2, align 4
-  %6 = load i32* @b, align 4
+  %6 = load i32, i32* @b, align 4
   %cmp6 = icmp eq i32 %6, 3
   br i1 %cmp6, label %cond.true7, label %cond.false8
 
 cond.true7:                                       ; preds = %cond.end4
-  %7 = load i32* @f, align 4
+  %7 = load i32, i32* @f, align 4
   br label %cond.end9
 
 cond.false8:                                      ; preds = %cond.end4
-  %8 = load i32* @t, align 4
+  %8 = load i32, i32* @t, align 4
   br label %cond.end9
 
 cond.end9:                                        ; preds = %cond.false8, %cond.true7
   %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ]
   store i32 %cond10, i32* @z3, align 4
-  %9 = load i32* @b, align 4
+  %9 = load i32, i32* @b, align 4
   %cmp11 = icmp eq i32 %9, 1000
   br i1 %cmp11, label %cond.true12, label %cond.false13
 
 cond.true12:                                      ; preds = %cond.end9
-  %10 = load i32* @t, align 4
+  %10 = load i32, i32* @t, align 4
   br label %cond.end14
 
 cond.false13:                                     ; preds = %cond.end9
-  %11 = load i32* @f, align 4
+  %11 = load i32, i32* @f, align 4
   br label %cond.end14
 
 cond.end14:                                       ; preds = %cond.false13, %cond.true12
diff --git a/test/CodeGen/Mips/selgek.ll b/test/CodeGen/Mips/selgek.ll
index 8ab4046e92cb..38ad95ee01a9 100644
--- a/test/CodeGen/Mips/selgek.ll
+++ b/test/CodeGen/Mips/selgek.ll
@@ -13,61 +13,61 @@
 
 define void @calc_z() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp sge i32 %0, 1000
   br i1 %cmp, label %cond.true, label %cond.false
 
 cond.true:                                        ; preds = %entry
-  %1 = load i32* @f, align 4
+  %1 = load i32, i32* @f, align 4
   br label %cond.end
 
 cond.false:                                       ; preds = %entry
-  %2 = load i32* @t, align 4
+  %2 = load i32, i32* @t, align 4
   br label %cond.end
 
 cond.end:                                         ; preds = %cond.false, %cond.true
   %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ]
   store i32 %cond, i32* @z1, align 4
-  %3 = load i32* @b, align 4
+  %3 = load i32, i32* @b, align 4
   %cmp1 = icmp sge i32 %3, 1
   br i1 %cmp1, label %cond.true2, label %cond.false3
 
 cond.true2:                                       ; preds = %cond.end
-  %4 = load i32* @t, align 4
+  %4 = load i32, i32* @t, align 4
   br label %cond.end4
 
 cond.false3:                                      ; preds = %cond.end
-  %5 = load i32* @f, align 4
+  %5 = load i32, i32* @f, align 4
   br label %cond.end4
 
 cond.end4:                                        ; preds = %cond.false3, %cond.true2
   %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ]
   store i32 %cond5, i32* @z2, align 4
-  %6 = load i32* @c, align 4
+  %6 = load i32, i32* @c, align 4
   %cmp6 = icmp sge i32 %6, 2
   br i1 %cmp6, label %cond.true7, label %cond.false8
 
 cond.true7:                                       ; preds = %cond.end4
-  %7 = load i32* @t, align 4
+  %7 = load i32, i32* @t, align 4
   br label %cond.end9
 
 cond.false8:                                      ; preds = %cond.end4
-  %8 = load i32* @f, align 4
+  %8 = load i32, i32* @f, align 4
   br label %cond.end9
 
 cond.end9:                                        ; preds = %cond.false8, %cond.true7
   %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ]
   store i32 %cond10, i32* @z3, align 4
-  %9 = load i32* @a, align 4
+  %9 = load i32, i32* @a, align 4
   %cmp11 = icmp sge i32 %9, 2
   br i1 %cmp11, label %cond.true12, label %cond.false13
 
 cond.true12:                                      ; preds = %cond.end9
-  %10 = load i32* @t, align 4
+  %10 = load i32, i32* @t, align 4
   br label %cond.end14
 
 cond.false13:                                     ; preds = %cond.end9
-  %11 = load i32* @f, align 4
+  %11 = load i32, i32* @f, align 4
   br label %cond.end14
 
 cond.end14:                                       ; preds = %cond.false13, %cond.true12
diff --git a/test/CodeGen/Mips/selgt.ll b/test/CodeGen/Mips/selgt.ll
index 67b9b498709b..a2e1e39e742f 100644
--- a/test/CodeGen/Mips/selgt.ll
+++ b/test/CodeGen/Mips/selgt.ll
@@ -14,71 +14,71 @@
 define i32 @calc_z() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
 entry:
   %retval = alloca i32, align 4
-  %0 = load i32* @a, align 4
-  %1 = load i32* @b, align 4
+  %0 = load i32, i32* @a, align 4
+  %1 = load i32, i32* @b, align 4
   %cmp = icmp sgt i32 %0, %1
   br i1 %cmp, label %cond.true, label %cond.false
 
 cond.true:                                        ; preds = %entry
-  %2 = load i32* @f, align 4
+  %2 = load i32, i32* @f, align 4
   br label %cond.end
 
 cond.false:                                       ; preds = %entry
-  %3 = load i32* @t, align 4
+  %3 = load i32, i32* @t, align 4
   br label %cond.end
 
 cond.end:                                         ; preds = %cond.false, %cond.true
   %cond = phi i32 [ %2, %cond.true ], [ %3, %cond.false ]
   store i32 %cond, i32* @z1, align 4
-  %4 = load i32* @b, align 4
-  %5 = load i32* @a, align 4
+  %4 = load i32, i32* @b, align 4
+  %5 = load i32, i32* @a, align 4
   %cmp1 = icmp sgt i32 %4, %5
   br i1 %cmp1, label %cond.true2, label %cond.false3
 
 cond.true2:                                       ; preds = %cond.end
-  %6 = load i32* @t, align 4
+  %6 = load i32, i32* @t, align 4
   br label %cond.end4
 
 cond.false3:                                      ; preds = %cond.end
-  %7 = load i32* @f, align 4
+  %7 = load i32, i32* @f, align 4
   br label %cond.end4
 
 cond.end4:                                        ; preds = %cond.false3, %cond.true2
   %cond5 = phi i32 [ %6, %cond.true2 ], [ %7, %cond.false3 ]
   store i32 %cond5, i32* @z2, align 4
-  %8 = load i32* @c, align 4
-  %9 = load i32* @a, align 4
+  %8 = load i32, i32* @c, align 4
+  %9 = load i32, i32* @a, align 4
   %cmp6 = icmp sgt i32 %8, %9
   br i1 %cmp6, label %cond.true7, label %cond.false8
 
 cond.true7:                                       ; preds = %cond.end4
-  %10 = load i32* @f, align 4
+  %10 = load i32, i32* @f, align 4
   br label %cond.end9
 
 cond.false8:                                      ; preds = %cond.end4
-  %11 = load i32* @t, align 4
+  %11 = load i32, i32* @t, align 4
   br label %cond.end9
 
 cond.end9:                                        ; preds = %cond.false8, %cond.true7
   %cond10 = phi i32 [ %10, %cond.true7 ], [ %11, %cond.false8 ]
   store i32 %cond10, i32* @z3, align 4
-  %12 = load i32* @a, align 4
-  %13 = load i32* @c, align 4
+  %12 = load i32, i32* @a, align 4
+  %13 = load i32, i32* @c, align 4
   %cmp11 = icmp sgt i32 %12, %13
   br i1 %cmp11, label %cond.true12, label %cond.false13
 
 cond.true12:                                      ; preds = %cond.end9
-  %14 = load i32* @f, align 4
+  %14 = load i32, i32* @f, align 4
   br label %cond.end14
 
 cond.false13:                                     ; preds = %cond.end9
-  %15 = load i32* @t, align 4
+  %15 = load i32, i32* @t, align 4
   br label %cond.end14
 
 cond.end14:                                       ; preds = %cond.false13, %cond.true12
   %cond15 = phi i32 [ %14, %cond.true12 ], [ %15, %cond.false13 ]
   store i32 %cond15, i32* @z4, align 4
-  %16 = load i32* %retval
+  %16 = load i32, i32* %retval
   ret i32 %16
 }
 
diff --git a/test/CodeGen/Mips/selle.ll b/test/CodeGen/Mips/selle.ll
index b27df45e6739..1adefb7846e4 100644
--- a/test/CodeGen/Mips/selle.ll
+++ b/test/CodeGen/Mips/selle.ll
@@ -13,65 +13,65 @@
 
 define void @calc_z() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
 entry:
-  %0 = load i32* @a, align 4
-  %1 = load i32* @b, align 4
+  %0 = load i32, i32* @a, align 4
+  %1 = load i32, i32* @b, align 4
   %cmp = icmp sle i32 %0, %1
   br i1 %cmp, label %cond.true, label %cond.false
 
 cond.true:                                        ; preds = %entry
-  %2 = load i32* @t, align 4
+  %2 = load i32, i32* @t, align 4
   br label %cond.end
 
 cond.false:                                       ; preds = %entry
-  %3 = load i32* @f, align 4
+  %3 = load i32, i32* @f, align 4
   br label %cond.end
 
 cond.end:                                         ; preds = %cond.false, %cond.true
   %cond = phi i32 [ %2, %cond.true ], [ %3, %cond.false ]
   store i32 %cond, i32* @z1, align 4
-  %4 = load i32* @b, align 4
-  %5 = load i32* @a, align 4
+  %4 = load i32, i32* @b, align 4
+  %5 = load i32, i32* @a, align 4
   %cmp1 = icmp sle i32 %4, %5
   br i1 %cmp1, label %cond.true2, label %cond.false3
 
 cond.true2:                                       ; preds = %cond.end
-  %6 = load i32* @f, align 4
+  %6 = load i32, i32* @f, align 4
   br label %cond.end4
 
 cond.false3:                                      ; preds = %cond.end
-  %7 = load i32* @t, align 4
+  %7 = load i32, i32* @t, align 4
   br label %cond.end4
 
 cond.end4:                                        ; preds = %cond.false3, %cond.true2
   %cond5 = phi i32 [ %6, %cond.true2 ], [ %7, %cond.false3 ]
   store i32 %cond5, i32* @z2, align 4
-  %8 = load i32* @c, align 4
-  %9 = load i32* @a, align 4
+  %8 = load i32, i32* @c, align 4
+  %9 = load i32, i32* @a, align 4
   %cmp6 = icmp sle i32 %8, %9
   br i1 %cmp6, label %cond.true7, label %cond.false8
 
 cond.true7:                                       ; preds = %cond.end4
-  %10 = load i32* @t, align 4
+  %10 = load i32, i32* @t, align 4
   br label %cond.end9
 
 cond.false8:                                      ; preds = %cond.end4
-  %11 = load i32* @f, align 4
+  %11 = load i32, i32* @f, align 4
   br label %cond.end9
 
 cond.end9:                                        ; preds = %cond.false8, %cond.true7
   %cond10 = phi i32 [ %10, %cond.true7 ], [ %11, %cond.false8 ]
   store i32 %cond10, i32* @z3, align 4
-  %12 = load i32* @a, align 4
-  %13 = load i32* @c, align 4
+  %12 = load i32, i32* @a, align 4
+  %13 = load i32, i32* @c, align 4
   %cmp11 = icmp sle i32 %12, %13
   br i1 %cmp11, label %cond.true12, label %cond.false13
 
 cond.true12:                                      ; preds = %cond.end9
-  %14 = load i32* @t, align 4
+  %14 = load i32, i32* @t, align 4
   br label %cond.end14
 
 cond.false13:                                     ; preds = %cond.end9
-  %15 = load i32* @f, align 4
+  %15 = load i32, i32* @f, align 4
   br label %cond.end14
 
 cond.end14:                                       ; preds = %cond.false13, %cond.true12
diff --git a/test/CodeGen/Mips/selltk.ll b/test/CodeGen/Mips/selltk.ll
index 1471b892c92a..db9f8c171b78 100644
--- a/test/CodeGen/Mips/selltk.ll
+++ b/test/CodeGen/Mips/selltk.ll
@@ -13,61 +13,61 @@
 
 define void @calc_selltk() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp slt i32 %0, 1000
   br i1 %cmp, label %cond.true, label %cond.false
 
 cond.true:                                        ; preds = %entry
-  %1 = load i32* @t, align 4
+  %1 = load i32, i32* @t, align 4
   br label %cond.end
 
 cond.false:                                       ; preds = %entry
-  %2 = load i32* @f, align 4
+  %2 = load i32, i32* @f, align 4
   br label %cond.end
 
 cond.end:                                         ; preds = %cond.false, %cond.true
   %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ]
   store i32 %cond, i32* @z1, align 4
-  %3 = load i32* @b, align 4
+  %3 = load i32, i32* @b, align 4
   %cmp1 = icmp slt i32 %3, 2
   br i1 %cmp1, label %cond.true2, label %cond.false3
 
 cond.true2:                                       ; preds = %cond.end
-  %4 = load i32* @f, align 4
+  %4 = load i32, i32* @f, align 4
   br label %cond.end4
 
 cond.false3:                                      ; preds = %cond.end
-  %5 = load i32* @t, align 4
+  %5 = load i32, i32* @t, align 4
   br label %cond.end4
 
 cond.end4:                                        ; preds = %cond.false3, %cond.true2
   %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ]
   store i32 %cond5, i32* @z2, align 4
-  %6 = load i32* @c, align 4
+  %6 = load i32, i32* @c, align 4
   %cmp6 = icmp sgt i32 %6, 2
   br i1 %cmp6, label %cond.true7, label %cond.false8
 
 cond.true7:                                       ; preds = %cond.end4
-  %7 = load i32* @f, align 4
+  %7 = load i32, i32* @f, align 4
   br label %cond.end9
 
 cond.false8:                                      ; preds = %cond.end4
-  %8 = load i32* @t, align 4
+  %8 = load i32, i32* @t, align 4
   br label %cond.end9
 
 cond.end9:                                        ; preds = %cond.false8, %cond.true7
   %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ]
   store i32 %cond10, i32* @z3, align 4
-  %9 = load i32* @a, align 4
+  %9 = load i32, i32* @a, align 4
   %cmp11 = icmp sgt i32 %9, 2
   br i1 %cmp11, label %cond.true12, label %cond.false13
 
 cond.true12:                                      ; preds = %cond.end9
-  %10 = load i32* @f, align 4
+  %10 = load i32, i32* @f, align 4
   br label %cond.end14
 
 cond.false13:                                     ; preds = %cond.end9
-  %11 = load i32* @t, align 4
+  %11 = load i32, i32* @t, align 4
   br label %cond.end14
 
 cond.end14:                                       ; preds = %cond.false13, %cond.true12
diff --git a/test/CodeGen/Mips/selne.ll b/test/CodeGen/Mips/selne.ll
index e3d82b8cf5d0..9be99d669475 100644
--- a/test/CodeGen/Mips/selne.ll
+++ b/test/CodeGen/Mips/selne.ll
@@ -13,65 +13,65 @@
 
 define void @calc_seleq() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
 entry:
-  %0 = load i32* @a, align 4
-  %1 = load i32* @b, align 4
+  %0 = load i32, i32* @a, align 4
+  %1 = load i32, i32* @b, align 4
   %cmp = icmp ne i32 %0, %1
   br i1 %cmp, label %cond.true, label %cond.false
 
 cond.true:                                        ; preds = %entry
-  %2 = load i32* @f, align 4
+  %2 = load i32, i32* @f, align 4
   br label %cond.end
 
 cond.false:                                       ; preds = %entry
-  %3 = load i32* @t, align 4
+  %3 = load i32, i32* @t, align 4
   br label %cond.end
 
 cond.end:                                         ; preds = %cond.false, %cond.true
   %cond = phi i32 [ %2, %cond.true ], [ %3, %cond.false ]
   store i32 %cond, i32* @z1, align 4
-  %4 = load i32* @b, align 4
-  %5 = load i32* @a, align 4
+  %4 = load i32, i32* @b, align 4
+  %5 = load i32, i32* @a, align 4
   %cmp1 = icmp ne i32 %4, %5
   br i1 %cmp1, label %cond.true2, label %cond.false3
 
 cond.true2:                                       ; preds = %cond.end
-  %6 = load i32* @f, align 4
+  %6 = load i32, i32* @f, align 4
   br label %cond.end4
 
 cond.false3:                                      ; preds = %cond.end
-  %7 = load i32* @t, align 4
+  %7 = load i32, i32* @t, align 4
   br label %cond.end4
 
 cond.end4:                                        ; preds = %cond.false3, %cond.true2
   %cond5 = phi i32 [ %6, %cond.true2 ], [ %7, %cond.false3 ]
   store i32 %cond5, i32* @z2, align 4
-  %8 = load i32* @c, align 4
-  %9 = load i32* @a, align 4
+  %8 = load i32, i32* @c, align 4
+  %9 = load i32, i32* @a, align 4
   %cmp6 = icmp ne i32 %8, %9
   br i1 %cmp6, label %cond.true7, label %cond.false8
 
 cond.true7:                                       ; preds = %cond.end4
-  %10 = load i32* @t, align 4
+  %10 = load i32, i32* @t, align 4
   br label %cond.end9
 
 cond.false8:                                      ; preds = %cond.end4
-  %11 = load i32* @f, align 4
+  %11 = load i32, i32* @f, align 4
   br label %cond.end9
 
 cond.end9:                                        ; preds = %cond.false8, %cond.true7
   %cond10 = phi i32 [ %10, %cond.true7 ], [ %11, %cond.false8 ]
   store i32 %cond10, i32* @z3, align 4
-  %12 = load i32* @a, align 4
-  %13 = load i32* @c, align 4
+  %12 = load i32, i32* @a, align 4
+  %13 = load i32, i32* @c, align 4
   %cmp11 = icmp ne i32 %12, %13
   br i1 %cmp11, label %cond.true12, label %cond.false13
 
 cond.true12:                                      ; preds = %cond.end9
-  %14 = load i32* @t, align 4
+  %14 = load i32, i32* @t, align 4
   br label %cond.end14
 
 cond.false13:                                     ; preds = %cond.end9
-  %15 = load i32* @f, align 4
+  %15 = load i32, i32* @f, align 4
   br label %cond.end14
 
 cond.end14:                                       ; preds = %cond.false13, %cond.true12
diff --git a/test/CodeGen/Mips/selnek.ll b/test/CodeGen/Mips/selnek.ll
index 64834b256fe5..5b6aa2afa1af 100644
--- a/test/CodeGen/Mips/selnek.ll
+++ b/test/CodeGen/Mips/selnek.ll
@@ -12,61 +12,61 @@
 
 define void @calc_z() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp ne i32 %0, 1
   br i1 %cmp, label %cond.true, label %cond.false
 
 cond.true:                                        ; preds = %entry
-  %1 = load i32* @f, align 4
+  %1 = load i32, i32* @f, align 4
   br label %cond.end
 
 cond.false:                                       ; preds = %entry
-  %2 = load i32* @t, align 4
+  %2 = load i32, i32* @t, align 4
   br label %cond.end
 
 cond.end:                                         ; preds = %cond.false, %cond.true
   %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ]
   store i32 %cond, i32* @z1, align 4
-  %3 = load i32* @a, align 4
+  %3 = load i32, i32* @a, align 4
   %cmp1 = icmp ne i32 %3, 1000
   br i1 %cmp1, label %cond.true2, label %cond.false3
 
 cond.true2:                                       ; preds = %cond.end
-  %4 = load i32* @t, align 4
+  %4 = load i32, i32* @t, align 4
   br label %cond.end4
 
 cond.false3:                                      ; preds = %cond.end
-  %5 = load i32* @f, align 4
+  %5 = load i32, i32* @f, align 4
   br label %cond.end4
 
 cond.end4:                                        ; preds = %cond.false3, %cond.true2
   %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ]
   store i32 %cond5, i32* @z2, align 4
-  %6 = load i32* @b, align 4
+  %6 = load i32, i32* @b, align 4
   %cmp6 = icmp ne i32 %6, 3
   br i1 %cmp6, label %cond.true7, label %cond.false8
 
 cond.true7:                                       ; preds = %cond.end4
-  %7 = load i32* @t, align 4
+  %7 = load i32, i32* @t, align 4
   br label %cond.end9
 
 cond.false8:                                      ; preds = %cond.end4
-  %8 = load i32* @f, align 4
+  %8 = load i32, i32* @f, align 4
   br label %cond.end9
 
 cond.end9:                                        ; preds = %cond.false8, %cond.true7
   %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ]
   store i32 %cond10, i32* @z3, align 4
-  %9 = load i32* @b, align 4
+  %9 = load i32, i32* @b, align 4
   %cmp11 = icmp ne i32 %9, 1000
   br i1 %cmp11, label %cond.true12, label %cond.false13
 
 cond.true12:                                      ; preds = %cond.end9
-  %10 = load i32* @f, align 4
+  %10 = load i32, i32* @f, align 4
   br label %cond.end14
 
 cond.false13:                                     ; preds = %cond.end9
-  %11 = load i32* @t, align 4
+  %11 = load i32, i32* @t, align 4
   br label %cond.end14
 
 cond.end14:                                       ; preds = %cond.false13, %cond.true12
@@ -78,14 +78,14 @@ cond.end14:                                       ; preds = %cond.false13, %cond
 define i32 @main() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
 entry:
   call void @calc_z() "target-cpu"="mips16" "target-features"="+mips16,+o32"
-  %0 = load i32* @z1, align 4
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %0) "target-cpu"="mips16" "target-features"="+mips16,+o32"
-  %1 = load i32* @z2, align 4
-  %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %1) "target-cpu"="mips16" "target-features"="+mips16,+o32"
-  %2 = load i32* @z3, align 4
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %2) "target-cpu"="mips16" "target-features"="+mips16,+o32"
-  %3 = load i32* @z4, align 4
-  %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %3) "target-cpu"="mips16" "target-features"="+mips16,+o32"
+  %0 = load i32, i32* @z1, align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %0) "target-cpu"="mips16" "target-features"="+mips16,+o32"
+  %1 = load i32, i32* @z2, align 4
+  %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %1) "target-cpu"="mips16" "target-features"="+mips16,+o32"
+  %2 = load i32, i32* @z3, align 4
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %2) "target-cpu"="mips16" "target-features"="+mips16,+o32"
+  %3 = load i32, i32* @z4, align 4
+  %call3 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %3) "target-cpu"="mips16" "target-features"="+mips16,+o32"
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/selpat.ll b/test/CodeGen/Mips/selpat.ll
index 8eda8de45e08..c682d8182a46 100644
--- a/test/CodeGen/Mips/selpat.ll
+++ b/test/CodeGen/Mips/selpat.ll
@@ -12,18 +12,18 @@
 
 define void @calc_seleq() nounwind {
 entry:
-  %0 = load i32* @a, align 4
-  %1 = load i32* @b, align 4
+  %0 = load i32, i32* @a, align 4
+  %1 = load i32, i32* @b, align 4
   %cmp = icmp eq i32 %0, %1
-  %2 = load i32* @f, align 4
-  %3 = load i32* @t, align 4
+  %2 = load i32, i32* @f, align 4
+  %3 = load i32, i32* @t, align 4
   %cond = select i1 %cmp, i32 %2, i32 %3
   store i32 %cond, i32* @z1, align 4
 ; 16:	cmp	${{[0-9]+}}, ${{[0-9]+}}
 ; 16:	bteqz	$BB{{[0-9]+}}_{{[0-9]}}
 ; 16: 	move    ${{[0-9]+}}, ${{[0-9]+}}
   store i32 %cond, i32* @z2, align 4
-  %4 = load i32* @c, align 4
+  %4 = load i32, i32* @c, align 4
   %cmp6 = icmp eq i32 %4, %0
   %cond10 = select i1 %cmp6, i32 %3, i32 %2
   store i32 %cond10, i32* @z3, align 4
@@ -34,10 +34,10 @@ entry:
 
 define void @calc_seleqk() nounwind {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp eq i32 %0, 1
-  %1 = load i32* @t, align 4
-  %2 = load i32* @f, align 4
+  %1 = load i32, i32* @t, align 4
+  %2 = load i32, i32* @f, align 4
   %cond = select i1 %cmp, i32 %1, i32 %2
   store i32 %cond, i32* @z1, align 4
 ; 16:	cmpi	${{[0-9]+}}, 1
@@ -46,7 +46,7 @@ entry:
   %cmp1 = icmp eq i32 %0, 10
   %cond5 = select i1 %cmp1, i32 %2, i32 %1
   store i32 %cond5, i32* @z2, align 4
-  %3 = load i32* @b, align 4
+  %3 = load i32, i32* @b, align 4
   %cmp6 = icmp eq i32 %3, 3
   %cond10 = select i1 %cmp6, i32 %2, i32 %1
   store i32 %cond10, i32* @z3, align 4
@@ -61,19 +61,19 @@ entry:
 
 define void @calc_seleqz() nounwind {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp eq i32 %0, 0
-  %1 = load i32* @t, align 4
-  %2 = load i32* @f, align 4
+  %1 = load i32, i32* @t, align 4
+  %2 = load i32, i32* @f, align 4
   %cond = select i1 %cmp, i32 %1, i32 %2
   store i32 %cond, i32* @z1, align 4
 ; 16:	beqz	${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]}}
 ; 16: 	move    ${{[0-9]+}}, ${{[0-9]+}}
-  %3 = load i32* @b, align 4
+  %3 = load i32, i32* @b, align 4
   %cmp1 = icmp eq i32 %3, 0
   %cond5 = select i1 %cmp1, i32 %2, i32 %1
   store i32 %cond5, i32* @z2, align 4
-  %4 = load i32* @c, align 4
+  %4 = load i32, i32* @c, align 4
   %cmp6 = icmp eq i32 %4, 0
   %cond10 = select i1 %cmp6, i32 %1, i32 %2
   store i32 %cond10, i32* @z3, align 4
@@ -83,11 +83,11 @@ entry:
 
 define void @calc_selge() nounwind {
 entry:
-  %0 = load i32* @a, align 4
-  %1 = load i32* @b, align 4
+  %0 = load i32, i32* @a, align 4
+  %1 = load i32, i32* @b, align 4
   %cmp = icmp sge i32 %0, %1
-  %2 = load i32* @f, align 4
-  %3 = load i32* @t, align 4
+  %2 = load i32, i32* @f, align 4
+  %3 = load i32, i32* @t, align 4
   %cond = select i1 %cmp, i32 %2, i32 %3
   store i32 %cond, i32* @z1, align 4
 ; 16:	slt	${{[0-9]+}}, ${{[0-9]+}}
@@ -96,7 +96,7 @@ entry:
   %cmp1 = icmp sge i32 %1, %0
   %cond5 = select i1 %cmp1, i32 %3, i32 %2
   store i32 %cond5, i32* @z2, align 4
-  %4 = load i32* @c, align 4
+  %4 = load i32, i32* @c, align 4
   %cmp6 = icmp sge i32 %4, %0
   %cond10 = select i1 %cmp6, i32 %3, i32 %2
   store i32 %cond10, i32* @z3, align 4
@@ -108,20 +108,20 @@ entry:
 
 define i32 @calc_selgt() nounwind {
 entry:
-  %0 = load i32* @a, align 4
-  %1 = load i32* @b, align 4
+  %0 = load i32, i32* @a, align 4
+  %1 = load i32, i32* @b, align 4
   %cmp = icmp sgt i32 %0, %1
 ; 16:	slt	${{[0-9]+}}, ${{[0-9]+}}
 ; 16:	btnez	$BB{{[0-9]+}}_{{[0-9]}}
 ; 16: 	move    ${{[0-9]+}}, ${{[0-9]+}}
-  %2 = load i32* @f, align 4
-  %3 = load i32* @t, align 4
+  %2 = load i32, i32* @f, align 4
+  %3 = load i32, i32* @t, align 4
   %cond = select i1 %cmp, i32 %2, i32 %3
   store i32 %cond, i32* @z1, align 4
   %cmp1 = icmp sgt i32 %1, %0
   %cond5 = select i1 %cmp1, i32 %3, i32 %2
   store i32 %cond5, i32* @z2, align 4
-  %4 = load i32* @c, align 4
+  %4 = load i32, i32* @c, align 4
   %cmp6 = icmp sgt i32 %4, %0
   %cond10 = select i1 %cmp6, i32 %2, i32 %3
   store i32 %cond10, i32* @z3, align 4
@@ -133,11 +133,11 @@ entry:
 
 define void @calc_selle() nounwind {
 entry:
-  %0 = load i32* @a, align 4
-  %1 = load i32* @b, align 4
+  %0 = load i32, i32* @a, align 4
+  %1 = load i32, i32* @b, align 4
   %cmp = icmp sle i32 %0, %1
-  %2 = load i32* @t, align 4
-  %3 = load i32* @f, align 4
+  %2 = load i32, i32* @t, align 4
+  %3 = load i32, i32* @f, align 4
   %cond = select i1 %cmp, i32 %2, i32 %3
   store i32 %cond, i32* @z1, align 4
 ; 16:	slt	${{[0-9]+}}, ${{[0-9]+}}
@@ -146,7 +146,7 @@ entry:
   %cmp1 = icmp sle i32 %1, %0
   %cond5 = select i1 %cmp1, i32 %3, i32 %2
   store i32 %cond5, i32* @z2, align 4
-  %4 = load i32* @c, align 4
+  %4 = load i32, i32* @c, align 4
   %cmp6 = icmp sle i32 %4, %0
   %cond10 = select i1 %cmp6, i32 %2, i32 %3
   store i32 %cond10, i32* @z3, align 4
@@ -158,20 +158,20 @@ entry:
 
 define void @calc_selltk() nounwind {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp slt i32 %0, 10
-  %1 = load i32* @t, align 4
-  %2 = load i32* @f, align 4
+  %1 = load i32, i32* @t, align 4
+  %2 = load i32, i32* @f, align 4
   %cond = select i1 %cmp, i32 %1, i32 %2
   store i32 %cond, i32* @z1, align 4
 ; 16:	slti	${{[0-9]+}}, {{[0-9]+}}
 ; 16:	btnez	$BB{{[0-9]+}}_{{[0-9]}}
 ; 16: 	move    ${{[0-9]+}}, ${{[0-9]+}}
-  %3 = load i32* @b, align 4
+  %3 = load i32, i32* @b, align 4
   %cmp1 = icmp slt i32 %3, 2
   %cond5 = select i1 %cmp1, i32 %2, i32 %1
   store i32 %cond5, i32* @z2, align 4
-  %4 = load i32* @c, align 4
+  %4 = load i32, i32* @c, align 4
   %cmp6 = icmp sgt i32 %4, 2
   %cond10 = select i1 %cmp6, i32 %2, i32 %1
   store i32 %cond10, i32* @z3, align 4
@@ -184,18 +184,18 @@ entry:
 
 define void @calc_selne() nounwind {
 entry:
-  %0 = load i32* @a, align 4
-  %1 = load i32* @b, align 4
+  %0 = load i32, i32* @a, align 4
+  %1 = load i32, i32* @b, align 4
   %cmp = icmp ne i32 %0, %1
-  %2 = load i32* @t, align 4
-  %3 = load i32* @f, align 4
+  %2 = load i32, i32* @t, align 4
+  %3 = load i32, i32* @f, align 4
   %cond = select i1 %cmp, i32 %2, i32 %3
   store i32 %cond, i32* @z1, align 4
 ; 16:	cmp	${{[0-9]+}}, ${{[0-9]+}}
 ; 16:	btnez	$BB{{[0-9]+}}_{{[0-9]}}
 ; 16: 	move    ${{[0-9]+}}, ${{[0-9]+}}
   store i32 %cond, i32* @z2, align 4
-  %4 = load i32* @c, align 4
+  %4 = load i32, i32* @c, align 4
   %cmp6 = icmp ne i32 %4, %0
   %cond10 = select i1 %cmp6, i32 %3, i32 %2
   store i32 %cond10, i32* @z3, align 4
@@ -205,10 +205,10 @@ entry:
 
 define void @calc_selnek() nounwind {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp ne i32 %0, 1
-  %1 = load i32* @f, align 4
-  %2 = load i32* @t, align 4
+  %1 = load i32, i32* @f, align 4
+  %2 = load i32, i32* @t, align 4
   %cond = select i1 %cmp, i32 %1, i32 %2
   store i32 %cond, i32* @z1, align 4
 ; 16:	cmpi	${{[0-9]+}}, 1
@@ -217,7 +217,7 @@ entry:
   %cmp1 = icmp ne i32 %0, 10
   %cond5 = select i1 %cmp1, i32 %2, i32 %1
   store i32 %cond5, i32* @z2, align 4
-  %3 = load i32* @b, align 4
+  %3 = load i32, i32* @b, align 4
   %cmp6 = icmp ne i32 %3, 3
   %cond10 = select i1 %cmp6, i32 %2, i32 %1
   store i32 %cond10, i32* @z3, align 4
@@ -232,19 +232,19 @@ entry:
 
 define void @calc_selnez() nounwind {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp ne i32 %0, 0
-  %1 = load i32* @f, align 4
-  %2 = load i32* @t, align 4
+  %1 = load i32, i32* @f, align 4
+  %2 = load i32, i32* @t, align 4
   %cond = select i1 %cmp, i32 %1, i32 %2
   store i32 %cond, i32* @z1, align 4
 ; 16:	bnez	${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]}}
 ; 16: 	move    ${{[0-9]+}}, ${{[0-9]+}}
-  %3 = load i32* @b, align 4
+  %3 = load i32, i32* @b, align 4
   %cmp1 = icmp ne i32 %3, 0
   %cond5 = select i1 %cmp1, i32 %2, i32 %1
   store i32 %cond5, i32* @z2, align 4
-  %4 = load i32* @c, align 4
+  %4 = load i32, i32* @c, align 4
   %cmp6 = icmp ne i32 %4, 0
   %cond10 = select i1 %cmp6, i32 %1, i32 %2
   store i32 %cond10, i32* @z3, align 4
@@ -254,19 +254,19 @@ entry:
 
 define void @calc_selnez2() nounwind {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %tobool = icmp ne i32 %0, 0
-  %1 = load i32* @f, align 4
-  %2 = load i32* @t, align 4
+  %1 = load i32, i32* @f, align 4
+  %2 = load i32, i32* @t, align 4
   %cond = select i1 %tobool, i32 %1, i32 %2
   store i32 %cond, i32* @z1, align 4
 ; 16:	bnez	${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]}}
 ; 16: 	move    ${{[0-9]+}}, ${{[0-9]+}}
-  %3 = load i32* @b, align 4
+  %3 = load i32, i32* @b, align 4
   %tobool1 = icmp ne i32 %3, 0
   %cond5 = select i1 %tobool1, i32 %2, i32 %1
   store i32 %cond5, i32* @z2, align 4
-  %4 = load i32* @c, align 4
+  %4 = load i32, i32* @c, align 4
   %tobool6 = icmp ne i32 %4, 0
   %cond10 = select i1 %tobool6, i32 %1, i32 %2
   store i32 %cond10, i32* @z3, align 4
@@ -276,11 +276,11 @@ entry:
 
 define void @calc_seluge() nounwind {
 entry:
-  %0 = load i32* @a, align 4
-  %1 = load i32* @b, align 4
+  %0 = load i32, i32* @a, align 4
+  %1 = load i32, i32* @b, align 4
   %cmp = icmp uge i32 %0, %1
-  %2 = load i32* @f, align 4
-  %3 = load i32* @t, align 4
+  %2 = load i32, i32* @f, align 4
+  %3 = load i32, i32* @t, align 4
   %cond = select i1 %cmp, i32 %2, i32 %3
   store i32 %cond, i32* @z1, align 4
 ; 16:	sltu	${{[0-9]+}}, ${{[0-9]+}}
@@ -289,7 +289,7 @@ entry:
   %cmp1 = icmp uge i32 %1, %0
   %cond5 = select i1 %cmp1, i32 %3, i32 %2
   store i32 %cond5, i32* @z2, align 4
-  %4 = load i32* @c, align 4
+  %4 = load i32, i32* @c, align 4
   %cmp6 = icmp uge i32 %4, %0
   %cond10 = select i1 %cmp6, i32 %3, i32 %2
   store i32 %cond10, i32* @z3, align 4
@@ -301,11 +301,11 @@ entry:
 
 define void @calc_selugt() nounwind {
 entry:
-  %0 = load i32* @a, align 4
-  %1 = load i32* @b, align 4
+  %0 = load i32, i32* @a, align 4
+  %1 = load i32, i32* @b, align 4
   %cmp = icmp ugt i32 %0, %1
-  %2 = load i32* @f, align 4
-  %3 = load i32* @t, align 4
+  %2 = load i32, i32* @f, align 4
+  %3 = load i32, i32* @t, align 4
   %cond = select i1 %cmp, i32 %2, i32 %3
   store i32 %cond, i32* @z1, align 4
 ; 16:	sltu	${{[0-9]+}}, ${{[0-9]+}}
@@ -314,7 +314,7 @@ entry:
   %cmp1 = icmp ugt i32 %1, %0
   %cond5 = select i1 %cmp1, i32 %3, i32 %2
   store i32 %cond5, i32* @z2, align 4
-  %4 = load i32* @c, align 4
+  %4 = load i32, i32* @c, align 4
   %cmp6 = icmp ugt i32 %4, %0
   %cond10 = select i1 %cmp6, i32 %2, i32 %3
   store i32 %cond10, i32* @z3, align 4
@@ -326,11 +326,11 @@ entry:
 
 define void @calc_selule() nounwind {
 entry:
-  %0 = load i32* @a, align 4
-  %1 = load i32* @b, align 4
+  %0 = load i32, i32* @a, align 4
+  %1 = load i32, i32* @b, align 4
   %cmp = icmp ule i32 %0, %1
-  %2 = load i32* @t, align 4
-  %3 = load i32* @f, align 4
+  %2 = load i32, i32* @t, align 4
+  %3 = load i32, i32* @f, align 4
   %cond = select i1 %cmp, i32 %2, i32 %3
   store i32 %cond, i32* @z1, align 4
 ; 16:	sltu	${{[0-9]+}}, ${{[0-9]+}}
@@ -339,7 +339,7 @@ entry:
   %cmp1 = icmp ule i32 %1, %0
   %cond5 = select i1 %cmp1, i32 %3, i32 %2
   store i32 %cond5, i32* @z2, align 4
-  %4 = load i32* @c, align 4
+  %4 = load i32, i32* @c, align 4
   %cmp6 = icmp ule i32 %4, %0
   %cond10 = select i1 %cmp6, i32 %2, i32 %3
   store i32 %cond10, i32* @z3, align 4
diff --git a/test/CodeGen/Mips/seteq.ll b/test/CodeGen/Mips/seteq.ll
index 5fadf78d57a0..8fad6122bdbe 100644
--- a/test/CodeGen/Mips/seteq.ll
+++ b/test/CodeGen/Mips/seteq.ll
@@ -8,8 +8,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @i, align 4
-  %1 = load i32* @k, align 4
+  %0 = load i32, i32* @i, align 4
+  %1 = load i32, i32* @k, align 4
   %cmp = icmp eq i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
diff --git a/test/CodeGen/Mips/seteqz.ll b/test/CodeGen/Mips/seteqz.ll
index 80dc3120a6a1..8e9a4beac75b 100644
--- a/test/CodeGen/Mips/seteqz.ll
+++ b/test/CodeGen/Mips/seteqz.ll
@@ -7,13 +7,13 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %cmp = icmp eq i32 %0, 0
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
 ; 16:	sltiu	${{[0-9]+}}, 1
 ; 16:	move	${{[0-9]+}}, $24
-  %1 = load i32* @j, align 4
+  %1 = load i32, i32* @j, align 4
   %cmp1 = icmp eq i32 %1, 99
   %conv2 = zext i1 %cmp1 to i32
   store i32 %conv2, i32* @r2, align 4
diff --git a/test/CodeGen/Mips/setge.ll b/test/CodeGen/Mips/setge.ll
index 8869eb8fc547..8fb729964cf5 100644
--- a/test/CodeGen/Mips/setge.ll
+++ b/test/CodeGen/Mips/setge.ll
@@ -11,15 +11,15 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @k, align 4
-  %1 = load i32* @j, align 4
+  %0 = load i32, i32* @k, align 4
+  %1 = load i32, i32* @j, align 4
   %cmp = icmp sge i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
 ; 16:	slt	${{[0-9]+}}, ${{[0-9]+}}
 ; 16:	move	$[[REGISTER:[0-9]+]], $24
 ; 16:	xor	$[[REGISTER]], ${{[0-9]+}}
-  %2 = load i32* @m, align 4
+  %2 = load i32, i32* @m, align 4
   %cmp1 = icmp sge i32 %0, %2
   %conv2 = zext i1 %cmp1 to i32
   store i32 %conv2, i32* @r2, align 4
diff --git a/test/CodeGen/Mips/setgek.ll b/test/CodeGen/Mips/setgek.ll
index 18a0fcf62130..1148d1b67bda 100644
--- a/test/CodeGen/Mips/setgek.ll
+++ b/test/CodeGen/Mips/setgek.ll
@@ -7,7 +7,7 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @k, align 4
+  %0 = load i32, i32* @k, align 4
   %cmp = icmp sgt i32 %0, -32769
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
diff --git a/test/CodeGen/Mips/setle.ll b/test/CodeGen/Mips/setle.ll
index 2df6774c1fad..fe4a2c37eb54 100644
--- a/test/CodeGen/Mips/setle.ll
+++ b/test/CodeGen/Mips/setle.ll
@@ -10,15 +10,15 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @j, align 4
-  %1 = load i32* @k, align 4
+  %0 = load i32, i32* @j, align 4
+  %1 = load i32, i32* @k, align 4
   %cmp = icmp sle i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
 ; 16:	slt	${{[0-9]+}}, ${{[0-9]+}}
 ; 16:	move	$[[REGISTER:[0-9]+]], $24
 ; 16:	xor	$[[REGISTER]], ${{[0-9]+}}
-  %2 = load i32* @m, align 4
+  %2 = load i32, i32* @m, align 4
   %cmp1 = icmp sle i32 %2, %1
   %conv2 = zext i1 %cmp1 to i32
   store i32 %conv2, i32* @r2, align 4
diff --git a/test/CodeGen/Mips/setlt.ll b/test/CodeGen/Mips/setlt.ll
index 3dac74bf2e01..c4211e6dd696 100644
--- a/test/CodeGen/Mips/setlt.ll
+++ b/test/CodeGen/Mips/setlt.ll
@@ -10,8 +10,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @j, align 4
-  %1 = load i32* @k, align 4
+  %0 = load i32, i32* @j, align 4
+  %1 = load i32, i32* @k, align 4
   %cmp = icmp slt i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
diff --git a/test/CodeGen/Mips/setltk.ll b/test/CodeGen/Mips/setltk.ll
index ecebc7e578e1..8c0041111270 100644
--- a/test/CodeGen/Mips/setltk.ll
+++ b/test/CodeGen/Mips/setltk.ll
@@ -10,7 +10,7 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @j, align 4
+  %0 = load i32, i32* @j, align 4
   %cmp = icmp slt i32 %0, 10
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
diff --git a/test/CodeGen/Mips/setne.ll b/test/CodeGen/Mips/setne.ll
index 9e66901e32b5..484674e5da32 100644
--- a/test/CodeGen/Mips/setne.ll
+++ b/test/CodeGen/Mips/setne.ll
@@ -8,8 +8,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @i, align 4
-  %1 = load i32* @k, align 4
+  %0 = load i32, i32* @i, align 4
+  %1 = load i32, i32* @k, align 4
   %cmp = icmp ne i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
diff --git a/test/CodeGen/Mips/setuge.ll b/test/CodeGen/Mips/setuge.ll
index 1c9b5bbe8114..025b4dcefd76 100644
--- a/test/CodeGen/Mips/setuge.ll
+++ b/test/CodeGen/Mips/setuge.ll
@@ -10,15 +10,15 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @k, align 4
-  %1 = load i32* @j, align 4
+  %0 = load i32, i32* @k, align 4
+  %1 = load i32, i32* @j, align 4
   %cmp = icmp uge i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
 ; 16:	sltu	${{[0-9]+}}, ${{[0-9]+}}
 ; 16:	move    $[[REGISTER:[0-9]+]], $24
 ; 16:	xor	$[[REGISTER]], ${{[0-9]+}}
-  %2 = load i32* @m, align 4
+  %2 = load i32, i32* @m, align 4
   %cmp1 = icmp uge i32 %0, %2
   %conv2 = zext i1 %cmp1 to i32
   store i32 %conv2, i32* @r2, align 4
diff --git a/test/CodeGen/Mips/setugt.ll b/test/CodeGen/Mips/setugt.ll
index f10b47ae7178..0ce317e0df9e 100644
--- a/test/CodeGen/Mips/setugt.ll
+++ b/test/CodeGen/Mips/setugt.ll
@@ -10,8 +10,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @k, align 4
-  %1 = load i32* @j, align 4
+  %0 = load i32, i32* @k, align 4
+  %1 = load i32, i32* @j, align 4
   %cmp = icmp ugt i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
diff --git a/test/CodeGen/Mips/setule.ll b/test/CodeGen/Mips/setule.ll
index a6d6bf064052..4255fd27c5cd 100644
--- a/test/CodeGen/Mips/setule.ll
+++ b/test/CodeGen/Mips/setule.ll
@@ -10,15 +10,15 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @j, align 4
-  %1 = load i32* @k, align 4
+  %0 = load i32, i32* @j, align 4
+  %1 = load i32, i32* @k, align 4
   %cmp = icmp ule i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
 ; 16:	sltu	${{[0-9]+}}, ${{[0-9]+}}
 ; 16:	move	$[[REGISTER:[0-9]+]], $24
 ; 16:	xor	$[[REGISTER]], ${{[0-9]+}}
-  %2 = load i32* @m, align 4
+  %2 = load i32, i32* @m, align 4
   %cmp1 = icmp ule i32 %2, %1
   %conv2 = zext i1 %cmp1 to i32
   store i32 %conv2, i32* @r2, align 4
diff --git a/test/CodeGen/Mips/setult.ll b/test/CodeGen/Mips/setult.ll
index 00ee437a2ffe..d30107e54dd0 100644
--- a/test/CodeGen/Mips/setult.ll
+++ b/test/CodeGen/Mips/setult.ll
@@ -10,8 +10,8 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @j, align 4
-  %1 = load i32* @k, align 4
+  %0 = load i32, i32* @j, align 4
+  %1 = load i32, i32* @k, align 4
   %cmp = icmp ult i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
diff --git a/test/CodeGen/Mips/setultk.ll b/test/CodeGen/Mips/setultk.ll
index eb9edbaad7f8..1b79f103bed7 100644
--- a/test/CodeGen/Mips/setultk.ll
+++ b/test/CodeGen/Mips/setultk.ll
@@ -10,7 +10,7 @@
 
 define void @test() nounwind {
 entry:
-  %0 = load i32* @j, align 4
+  %0 = load i32, i32* @j, align 4
   %cmp = icmp ult i32 %0, 10
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
diff --git a/test/CodeGen/Mips/sh1.ll b/test/CodeGen/Mips/sh1.ll
index 1746ae284f2a..3f70b9bc6e68 100644
--- a/test/CodeGen/Mips/sh1.ll
+++ b/test/CodeGen/Mips/sh1.ll
@@ -6,14 +6,14 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %conv = trunc i32 %0 to i16
   store i16 %conv, i16* @s, align 2
-  %1 = load i32* @i, align 4
-  %2 = load i16* @s, align 2
+  %1 = load i32, i32* @i, align 4
+  %2 = load i16, i16* @s, align 2
   %conv1 = sext i16 %2 to i32
 ; 16:	sh	${{[0-9]+}}, 0(${{[0-9]+}})
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i32 %1, i32 %conv1)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 %1, i32 %conv1)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/simplebr.ll b/test/CodeGen/Mips/simplebr.ll
index a1d63671b4ee..2aeacc903fbe 100644
--- a/test/CodeGen/Mips/simplebr.ll
+++ b/test/CodeGen/Mips/simplebr.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mips16-hard-float -soft-float -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mips16-hard-float -mattr=+soft-float -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16
 
 ; ModuleID = 'simplebr.c'
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"
@@ -9,7 +9,7 @@ target triple = "mips--linux-gnu"
 ; Function Attrs: nounwind
 define void @foo() #0 {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %tobool = icmp ne i32 %0, 0
   br i1 %tobool, label %if.then, label %if.else
 
diff --git a/test/CodeGen/Mips/sitofp-selectcc-opt.ll b/test/CodeGen/Mips/sitofp-selectcc-opt.ll
index 576cbd8e9637..c60fceb1a04c 100644
--- a/test/CodeGen/Mips/sitofp-selectcc-opt.ll
+++ b/test/CodeGen/Mips/sitofp-selectcc-opt.ll
@@ -14,7 +14,7 @@ entry:
   %tobool1. = or i1 %tobool1, %not.tobool
   %lor.ext = zext i1 %tobool1. to i32
   %conv = sitofp i32 %lor.ext to double
-  %1 = load double* @foo12.d4, align 8
+  %1 = load double, double* @foo12.d4, align 8
   %add = fadd double %conv, %1
   store double %add, double* @foo12.d4, align 8
   ret double %add
diff --git a/test/CodeGen/Mips/sll1.ll b/test/CodeGen/Mips/sll1.ll
index fdcd38c84b3a..4d35b64e0b58 100644
--- a/test/CodeGen/Mips/sll1.ll
+++ b/test/CodeGen/Mips/sll1.ll
@@ -7,12 +7,12 @@
 define i32 @main() nounwind {
 entry:
 ; 16:	sll	${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}}
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %shl = shl i32 %0, 4
 ; 16:	sll	${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}}
   store i32 %shl, i32* @j, align 4
-  %1 = load i32* @j, align 4
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %1)
+  %1 = load i32, i32* @j, align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %1)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/sll2.ll b/test/CodeGen/Mips/sll2.ll
index c2af454cc853..dc2236b10ccf 100644
--- a/test/CodeGen/Mips/sll2.ll
+++ b/test/CodeGen/Mips/sll2.ll
@@ -6,13 +6,13 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @i, align 4
-  %1 = load i32* @j, align 4
+  %0 = load i32, i32* @i, align 4
+  %1 = load i32, i32* @j, align 4
   %shl = shl i32 %0, %1
 ; 16:	sllv	${{[0-9]+}}, ${{[0-9]+}}
   store i32 %shl, i32* @i, align 4
-  %2 = load i32* @j, align 4
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %2)
+  %2 = load i32, i32* @j, align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %2)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/small-section-reserve-gp.ll b/test/CodeGen/Mips/small-section-reserve-gp.ll
index cbf0681c78e5..c4e37665aaf6 100644
--- a/test/CodeGen/Mips/small-section-reserve-gp.ll
+++ b/test/CodeGen/Mips/small-section-reserve-gp.ll
@@ -6,7 +6,7 @@
 define i32 @geti() nounwind readonly {
 entry:
 ; CHECK: lw ${{[0-9]+}}, %gp_rel(i)($gp)
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   ret i32 %0
 }
 
diff --git a/test/CodeGen/Mips/spill-copy-acreg.ll b/test/CodeGen/Mips/spill-copy-acreg.ll
index 6563a5cffd91..fd160b67cf24 100644
--- a/test/CodeGen/Mips/spill-copy-acreg.ll
+++ b/test/CodeGen/Mips/spill-copy-acreg.ll
@@ -6,7 +6,7 @@
 
 define i64 @test_acreg_copy(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
 entry:
-  %0 = load i64* @g1, align 8
+  %0 = load i64, i64* @g1, align 8
   %1 = tail call i64 @llvm.mips.maddu(i64 %0, i32 %a0, i32 %a1)
   %2 = tail call i64 @llvm.mips.maddu(i64 %0, i32 %a2, i32 %a3)
   store i64 %1, i64* @g1, align 8
@@ -32,8 +32,8 @@ entry:
   %sext = sext <2 x i1> %cmp3 to <2 x i16>
   store <2 x i16> %sext, <2 x i16>* @g4, align 4
   tail call void @foo1()
-  %2 = load <2 x i16>* @g5, align 4
-  %3 = load <2 x i16>* @g6, align 4
+  %2 = load <2 x i16>, <2 x i16>* @g5, align 4
+  %3 = load <2 x i16>, <2 x i16>* @g6, align 4
   %or = select <2 x i1> %cmp3, <2 x i16> %2, <2 x i16> %3
   %4 = bitcast <2 x i16> %or to i32
   %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
diff --git a/test/CodeGen/Mips/sr1.ll b/test/CodeGen/Mips/sr1.ll
index 610693d58b3f..69655f7b842c 100644
--- a/test/CodeGen/Mips/sr1.ll
+++ b/test/CodeGen/Mips/sr1.ll
@@ -8,9 +8,9 @@
 define void @foo1() #0 {
 entry:
   %c = alloca [10 x i8], align 1
-  %arraydecay = getelementptr inbounds [10 x i8]* %c, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [10 x i8], [10 x i8]* %c, i32 0, i32 0
   call void @x(i8* %arraydecay)
-  %arraydecay1 = getelementptr inbounds [10 x i8]* %c, i32 0, i32 0
+  %arraydecay1 = getelementptr inbounds [10 x i8], [10 x i8]* %c, i32 0, i32 0
   call void @x(i8* %arraydecay1)
   ret void
 ; CHECK: 	.ent	foo1
@@ -25,9 +25,9 @@ declare void @x(i8*) #1
 define void @foo2() #0 {
 entry:
   %c = alloca [150 x i8], align 1
-  %arraydecay = getelementptr inbounds [150 x i8]* %c, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [150 x i8], [150 x i8]* %c, i32 0, i32 0
   call void @x(i8* %arraydecay)
-  %arraydecay1 = getelementptr inbounds [150 x i8]* %c, i32 0, i32 0
+  %arraydecay1 = getelementptr inbounds [150 x i8], [150 x i8]* %c, i32 0, i32 0
   call void @x(i8* %arraydecay1)
   ret void
 ; CHECK: 	.ent	foo2
diff --git a/test/CodeGen/Mips/sra1.ll b/test/CodeGen/Mips/sra1.ll
index 15bf8d644ea3..1c7d417cb13a 100644
--- a/test/CodeGen/Mips/sra1.ll
+++ b/test/CodeGen/Mips/sra1.ll
@@ -5,10 +5,10 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %shr = ashr i32 %0, 3
 ; 16:	sra	${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}}
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %shr)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %shr)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/sra2.ll b/test/CodeGen/Mips/sra2.ll
index 26bf19d44020..771d0f4a79e3 100644
--- a/test/CodeGen/Mips/sra2.ll
+++ b/test/CodeGen/Mips/sra2.ll
@@ -6,11 +6,11 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @i, align 4
-  %1 = load i32* @j, align 4
+  %0 = load i32, i32* @i, align 4
+  %1 = load i32, i32* @j, align 4
   %shr = ashr i32 %0, %1
 ; 16:	srav	${{[0-9]+}}, ${{[0-9]+}}
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %shr)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %shr)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/srl1.ll b/test/CodeGen/Mips/srl1.ll
index 3474283faef9..a748eabb066f 100644
--- a/test/CodeGen/Mips/srl1.ll
+++ b/test/CodeGen/Mips/srl1.ll
@@ -6,12 +6,12 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %shr = lshr i32 %0, 4
 ; 16:	srl	${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}}
   store i32 %shr, i32* @j, align 4
-  %1 = load i32* @j, align 4
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %1)
+  %1 = load i32, i32* @j, align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %1)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/srl2.ll b/test/CodeGen/Mips/srl2.ll
index 26ec0927a559..6e338b39350f 100644
--- a/test/CodeGen/Mips/srl2.ll
+++ b/test/CodeGen/Mips/srl2.ll
@@ -7,13 +7,13 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @i, align 4
-  %1 = load i32* @k, align 4
+  %0 = load i32, i32* @i, align 4
+  %1 = load i32, i32* @k, align 4
   %shr = lshr i32 %0, %1
 ; 16:	srlv	${{[0-9]+}}, ${{[0-9]+}}
   store i32 %shr, i32* @j, align 4
-  %2 = load i32* @j, align 4
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %2)
+  %2 = load i32, i32* @j, align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %2)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/stackcoloring.ll b/test/CodeGen/Mips/stackcoloring.ll
index 4987dad5338b..5516b5a3c023 100644
--- a/test/CodeGen/Mips/stackcoloring.ll
+++ b/test/CodeGen/Mips/stackcoloring.ll
@@ -12,15 +12,15 @@ entry:
   %b = alloca [16 x i32], align 4
   %0 = bitcast [16 x i32]* %b to i8*
   call void @llvm.lifetime.start(i64 64, i8* %0)
-  %arraydecay = getelementptr inbounds [16 x i32]* %b, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [16 x i32], [16 x i32]* %b, i32 0, i32 0
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
   %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %v.04 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-  %1 = load i32** @g1, align 4
-  %arrayidx = getelementptr inbounds i32* %1, i32 %i.05
-  %2 = load i32* %arrayidx, align 4
+  %1 = load i32*, i32** @g1, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %1, i32 %i.05
+  %2 = load i32, i32* %arrayidx, align 4
   %call = call i32 @foo2(i32 %2, i32* %arraydecay)
   %add = add nsw i32 %call, %v.04
   %inc = add nsw i32 %i.05, 1
diff --git a/test/CodeGen/Mips/start-asm-file.ll b/test/CodeGen/Mips/start-asm-file.ll
index 9dc501ce10b4..60c047a4e8cc 100644
--- a/test/CodeGen/Mips/start-asm-file.ll
+++ b/test/CodeGen/Mips/start-asm-file.ll
@@ -19,36 +19,36 @@
 
 ; ### N32 ABI ###
 ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \
-; RUN: -relocation-model=static -mattr=-n64,+n32 %s -o - | \
+; RUN: -relocation-model=static -target-abi n32 %s -o - | \
 ; RUN:   FileCheck -check-prefix=CHECK-STATIC-N32 -check-prefix=CHECK-STATIC-N32-NLEGACY %s
 
 ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \
-; RUN: -relocation-model=pic -mattr=-n64,+n32 %s -o - | \
+; RUN: -relocation-model=pic -target-abi n32 %s -o - | \
 ; RUN:   FileCheck -check-prefix=CHECK-PIC-N32 -check-prefix=CHECK-PIC-N32-NLEGACY %s
 
 ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \
-; RUN: -relocation-model=static -mattr=-n64,+n32,+nan2008 %s -o - | \
+; RUN: -relocation-model=static -target-abi n32 -mattr=+nan2008 %s -o - | \
 ; RUN:   FileCheck -check-prefix=CHECK-STATIC-N32 -check-prefix=CHECK-STATIC-N32-N2008 %s
 
 ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \
-; RUN: -relocation-model=pic -mattr=-n64,+n32,+nan2008 %s -o - | \
+; RUN: -relocation-model=pic -target-abi n32 -mattr=+nan2008 %s -o - | \
 ; RUN:   FileCheck -check-prefix=CHECK-PIC-N32 -check-prefix=CHECK-PIC-N32-N2008 %s
 
 ; ### N64 ABI ###
 ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \
-; RUN: -relocation-model=static -mattr=+n64 %s -o - | \
+; RUN: -relocation-model=static -target-abi n64 %s -o - | \
 ; RUN:   FileCheck -check-prefix=CHECK-STATIC-N64 -check-prefix=CHECK-STATIC-N64-NLEGACY %s
 
 ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \
-; RUN: -relocation-model=pic -mattr=+n64 %s -o - | \
+; RUN: -relocation-model=pic -target-abi n64 %s -o - | \
 ; RUN:   FileCheck -check-prefix=CHECK-PIC-N64 -check-prefix=CHECK-PIC-N64-NLEGACY %s
 
 ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \
-; RUN: -relocation-model=static -mattr=+n64,+nan2008 %s -o - | \
+; RUN: -relocation-model=static -target-abi n64 -mattr=+nan2008 %s -o - | \
 ; RUN:   FileCheck -check-prefix=CHECK-STATIC-N64 -check-prefix=CHECK-STATIC-N64-N2008 %s
 
 ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \
-; RUN: -relocation-model=pic -mattr=+n64,+nan2008 %s -o - | \
+; RUN: -relocation-model=pic -target-abi n64 -mattr=+nan2008 %s -o - | \
 ; RUN:   FileCheck -check-prefix=CHECK-PIC-N64 -check-prefix=CHECK-PIC-N64-N2008 %s
 
 ; CHECK-STATIC-O32: .abicalls
diff --git a/test/CodeGen/Mips/stchar.ll b/test/CodeGen/Mips/stchar.ll
index 12eae3487ff1..6bc4889931a7 100644
--- a/test/CodeGen/Mips/stchar.ll
+++ b/test/CodeGen/Mips/stchar.ll
@@ -9,7 +9,7 @@ define void @p1(i16 signext %s, i8 signext %c) nounwind {
 entry:
   %conv = sext i16 %s to i32
   %conv1 = sext i8 %c to i32
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i32 %conv, i32 %conv1) nounwind
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 %conv, i32 %conv1) nounwind
   ret void
 }
 
@@ -17,16 +17,16 @@ declare i32 @printf(i8* nocapture, ...) nounwind
 
 define void @p2() nounwind {
 entry:
-  %0 = load i16** @sp, align 4
-  %1 = load i16* %0, align 2
-  %2 = load i8** @cp, align 4
-  %3 = load i8* %2, align 1
+  %0 = load i16*, i16** @sp, align 4
+  %1 = load i16, i16* %0, align 2
+  %2 = load i8*, i8** @cp, align 4
+  %3 = load i8, i8* %2, align 1
   %conv.i = sext i16 %1 to i32
   %conv1.i = sext i8 %3 to i32
-  %call.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i32 %conv.i, i32 %conv1.i) nounwind
-  %4 = load i16** @sp, align 4
+  %call.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 %conv.i, i32 %conv1.i) nounwind
+  %4 = load i16*, i16** @sp, align 4
   store i16 32, i16* %4, align 2
-  %5 = load i8** @cp, align 4
+  %5 = load i8*, i8** @cp, align 4
   store i8 97, i8* %5, align 1
   ret void
 }
@@ -39,16 +39,16 @@ entry:
   store i8 99, i8* %c, align 4
   store i16* %s, i16** @sp, align 4
   store i8* %c, i8** @cp, align 4
-  %call.i.i = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i32 16, i32 99) nounwind
-  %0 = load i16** @sp, align 4
+  %call.i.i = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 16, i32 99) nounwind
+  %0 = load i16*, i16** @sp, align 4
   store i16 32, i16* %0, align 2
-  %1 = load i8** @cp, align 4
+  %1 = load i8*, i8** @cp, align 4
   store i8 97, i8* %1, align 1
-  %2 = load i16* %s, align 4
-  %3 = load i8* %c, align 4
+  %2 = load i16, i16* %s, align 4
+  %3 = load i8, i8* %c, align 4
   %conv.i = sext i16 %2 to i32
   %conv1.i = sext i8 %3 to i32
-  %call.i = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i32 %conv.i, i32 %conv1.i) nounwind
+  %call.i = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 %conv.i, i32 %conv1.i) nounwind
   ret void
 ; 16_b-LABEL: test:
 ; 16_h-LABEL: test:
@@ -69,16 +69,16 @@ entry:
   store i8 99, i8* %c.i, align 4
   store i16* %s.i, i16** @sp, align 4
   store i8* %c.i, i8** @cp, align 4
-  %call.i.i.i = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i32 16, i32 99) nounwind
-  %1 = load i16** @sp, align 4
+  %call.i.i.i = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 16, i32 99) nounwind
+  %1 = load i16*, i16** @sp, align 4
   store i16 32, i16* %1, align 2
-  %2 = load i8** @cp, align 4
+  %2 = load i8*, i8** @cp, align 4
   store i8 97, i8* %2, align 1
-  %3 = load i16* %s.i, align 4
-  %4 = load i8* %c.i, align 4
+  %3 = load i16, i16* %s.i, align 4
+  %4 = load i8, i8* %c.i, align 4
   %conv.i.i = sext i16 %3 to i32
   %conv1.i.i = sext i8 %4 to i32
-  %call.i.i = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i32 %conv.i.i, i32 %conv1.i.i) nounwind
+  %call.i.i = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 %conv.i.i, i32 %conv1.i.i) nounwind
   call void @llvm.lifetime.end(i64 -1, i8* %0) nounwind
   call void @llvm.lifetime.end(i64 -1, i8* %c.i) nounwind
   ret i32 0
diff --git a/test/CodeGen/Mips/stldst.ll b/test/CodeGen/Mips/stldst.ll
index 4182b9e76d63..4eef5ece0589 100644
--- a/test/CodeGen/Mips/stldst.ll
+++ b/test/CodeGen/Mips/stldst.ll
@@ -12,25 +12,25 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @kkkk, align 4
-  %1 = load i32* @llll, align 4
+  %0 = load i32, i32* @kkkk, align 4
+  %1 = load i32, i32* @llll, align 4
   %add = add nsw i32 %0, 10
   %add1 = add nsw i32 %1, 10
-  %2 = load i32* @mmmm, align 4
+  %2 = load i32, i32* @mmmm, align 4
   %sub = add nsw i32 %2, -3
-  %3 = load i32* @nnnn, align 4
+  %3 = load i32, i32* @nnnn, align 4
   %add2 = add nsw i32 %3, 10
-  %4 = load i32* @oooo, align 4
+  %4 = load i32, i32* @oooo, align 4
   %add3 = add nsw i32 %4, 4
-  %5 = load i32* @pppp, align 4
+  %5 = load i32, i32* @pppp, align 4
   %sub4 = add nsw i32 %5, -5
-  %6 = load i32* @qqqq, align 4
+  %6 = load i32, i32* @qqqq, align 4
   %sub5 = add nsw i32 %6, -10
-  %7 = load i32* @rrrr, align 4
+  %7 = load i32, i32* @rrrr, align 4
   %add6 = add nsw i32 %7, 6
 
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str, i32 0, i32 0), i32 %sub5, i32 %add6, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7) nounwind
-  %call7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str, i32 0, i32 0), i32 %0, i32 %1, i32 %add, i32 %add1, i32 %sub, i32 %add2, i32 %add3, i32 %sub4, i32 %sub5, i32 %add6) nounwind
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @.str, i32 0, i32 0), i32 %sub5, i32 %add6, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7) nounwind
+  %call7 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @.str, i32 0, i32 0), i32 %0, i32 %1, i32 %add, i32 %add1, i32 %sub, i32 %add2, i32 %add3, i32 %sub4, i32 %sub5, i32 %add6) nounwind
   ret i32 0
 }
 ; 16:	sw	${{[0-9]+}}, {{[0-9]+}} ( $sp );         # 4-byte Folded Spill
diff --git a/test/CodeGen/Mips/sub1.ll b/test/CodeGen/Mips/sub1.ll
index 195750b805d6..636ab8f2c5f3 100644
--- a/test/CodeGen/Mips/sub1.ll
+++ b/test/CodeGen/Mips/sub1.ll
@@ -5,10 +5,10 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %sub = sub nsw i32 %0, 5
 ; 16:	addiu	${{[0-9]+}}, -{{[0-9]+}}
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 %sub)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %sub)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/sub2.ll b/test/CodeGen/Mips/sub2.ll
index 4f6bfccec401..a97f5e947ca9 100644
--- a/test/CodeGen/Mips/sub2.ll
+++ b/test/CodeGen/Mips/sub2.ll
@@ -6,11 +6,11 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @j, align 4
-  %1 = load i32* @i, align 4
+  %0 = load i32, i32* @j, align 4
+  %1 = load i32, i32* @i, align 4
   %sub = sub nsw i32 %0, %1
 ; 16:	subu	${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 %sub)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %sub)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/swzero.ll b/test/CodeGen/Mips/swzero.ll
index 9f91a3902d7d..9aaee1509806 100644
--- a/test/CodeGen/Mips/swzero.ll
+++ b/test/CodeGen/Mips/swzero.ll
@@ -6,7 +6,7 @@ define void @zero_u(%struct.unaligned* nocapture %p) nounwind {
 entry:
 ; CHECK: swl $zero
 ; CHECK: swr $zero
-  %x = getelementptr inbounds %struct.unaligned* %p, i32 0, i32 0
+  %x = getelementptr inbounds %struct.unaligned, %struct.unaligned* %p, i32 0, i32 0
   store i32 0, i32* %x, align 1
   ret void
 }
diff --git a/test/CodeGen/Mips/tail16.ll b/test/CodeGen/Mips/tail16.ll
index 4e62e557478a..13f27fcc513b 100644
--- a/test/CodeGen/Mips/tail16.ll
+++ b/test/CodeGen/Mips/tail16.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic   < %s | FileCheck %s 
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic   < %s | FileCheck %s 
 
 ; Function Attrs: nounwind optsize
 define float @h()  {
diff --git a/test/CodeGen/Mips/tailcall.ll b/test/CodeGen/Mips/tailcall.ll
index 30f47abc06cb..6a0d64b7eed8 100644
--- a/test/CodeGen/Mips/tailcall.ll
+++ b/test/CodeGen/Mips/tailcall.ll
@@ -85,16 +85,16 @@ entry:
 ; PIC16: jalrc
 ; PIC16: .end caller5
 
-  %0 = load i32* @g0, align 4
-  %1 = load i32* @g1, align 4
-  %2 = load i32* @g2, align 4
-  %3 = load i32* @g3, align 4
-  %4 = load i32* @g4, align 4
-  %5 = load i32* @g5, align 4
-  %6 = load i32* @g6, align 4
-  %7 = load i32* @g7, align 4
-  %8 = load i32* @g8, align 4
-  %9 = load i32* @g9, align 4
+  %0 = load i32, i32* @g0, align 4
+  %1 = load i32, i32* @g1, align 4
+  %2 = load i32, i32* @g2, align 4
+  %3 = load i32, i32* @g3, align 4
+  %4 = load i32, i32* @g4, align 4
+  %5 = load i32, i32* @g5, align 4
+  %6 = load i32, i32* @g6, align 4
+  %7 = load i32, i32* @g7, align 4
+  %8 = load i32, i32* @g8, align 4
+  %9 = load i32, i32* @g9, align 4
   %call = tail call fastcc i32 @callee5(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9)
   ret i32 %call
 }
@@ -136,7 +136,7 @@ entry:
 ; PIC16: jalrc
 ; PIC16: .end caller8_1
 
-  %call = tail call i32 (i32, ...)* @callee8(i32 2, i32 1) nounwind
+  %call = tail call i32 (i32, ...) @callee8(i32 2, i32 1) nounwind
   ret i32 %call
 }
 
@@ -239,7 +239,7 @@ entry:
 ; PIC16: .ent caller13
 ; PIC16: jalrc
 
-  %call = tail call i32 (i32, ...)* @callee13(i32 1, i32 2) nounwind
+  %call = tail call i32 (i32, ...) @callee13(i32 1, i32 2) nounwind
   ret i32 %call
 }
 
diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll
index b14ad5ba452b..97e270fc59a6 100644
--- a/test/CodeGen/Mips/tls.ll
+++ b/test/CodeGen/Mips/tls.ll
@@ -10,7 +10,7 @@
 
 define i32 @f1() nounwind {
 entry:
-  %tmp = load i32* @t1, align 4
+  %tmp = load i32, i32* @t1, align 4
   ret i32 %tmp
 
 ; PIC-LABEL:       f1:
@@ -33,7 +33,7 @@ entry:
 
 define i32 @f2() nounwind {
 entry:
-  %tmp = load i32* @t2, align 4
+  %tmp = load i32, i32* @t2, align 4
   ret i32 %tmp
 
 ; PIC-LABEL:       f2:
@@ -69,7 +69,7 @@ entry:
 ; PIC:   addu    $[[R1:[0-9]+]], $[[R0]], $2
 ; PIC:   lw      ${{[0-9]+}}, %dtprel_lo(f3.i)($[[R1]])
 
-  %0 = load i32* @f3.i, align 4
+  %0 = load i32, i32* @f3.i, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @f3.i, align 4
   ret i32 %inc
diff --git a/test/CodeGen/Mips/tls16.ll b/test/CodeGen/Mips/tls16.ll
index 861864bcfe0f..3d324d7ed1e8 100644
--- a/test/CodeGen/Mips/tls16.ll
+++ b/test/CodeGen/Mips/tls16.ll
@@ -4,7 +4,7 @@
 
 define i32 @foo() nounwind readonly {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
 ; PIC16:	lw	${{[0-9]+}}, %call16(__tls_get_addr)(${{[0-9]+}})
 ; PIC16:	addiu	${{[0-9]+}}, %tlsgd(a)
   ret i32 %0
diff --git a/test/CodeGen/Mips/tls16_2.ll b/test/CodeGen/Mips/tls16_2.ll
index b33e3c3766b6..0a6a4123e116 100644
--- a/test/CodeGen/Mips/tls16_2.ll
+++ b/test/CodeGen/Mips/tls16_2.ll
@@ -4,7 +4,7 @@
 
 define i8* @f(i8* nocapture %a) nounwind {
 entry:
-  %0 = load i32* @f.i, align 4
+  %0 = load i32, i32* @f.i, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @f.i, align 4
   %1 = inttoptr i32 %inc to i8*
diff --git a/test/CodeGen/Mips/uitofp.ll b/test/CodeGen/Mips/uitofp.ll
index aff70c24f07c..83c2069f9661 100644
--- a/test/CodeGen/Mips/uitofp.ll
+++ b/test/CodeGen/Mips/uitofp.ll
@@ -5,7 +5,7 @@ entry:
   %b = alloca i32, align 4
   %a = alloca float, align 4
   store volatile i32 1, i32* %b, align 4
-  %0 = load volatile i32* %b, align 4
+  %0 = load volatile i32, i32* %b, align 4
   %conv = uitofp i32 %0 to float
   store float %conv, float* %a, align 4
   ret void
diff --git a/test/CodeGen/Mips/ul1.ll b/test/CodeGen/Mips/ul1.ll
index 7e64ff4d90fd..ad0992954631 100644
--- a/test/CodeGen/Mips/ul1.ll
+++ b/test/CodeGen/Mips/ul1.ll
@@ -5,7 +5,7 @@
 
 define i32 @main() nounwind {
 entry:
-  store i32 10, i32* getelementptr inbounds (%struct.ua* @foo, i32 0, i32 1), align 1
+  store i32 10, i32* getelementptr inbounds (%struct.ua, %struct.ua* @foo, i32 0, i32 1), align 1
 ; 16:   sb  ${{[0-9]+}}, {{[0-9]+}}(${{[0-9]+}})
 ; 16:   sb  ${{[0-9]+}}, {{[0-9]+}}(${{[0-9]+}})
 ; 16:   sb  ${{[0-9]+}}, {{[0-9]+}}(${{[0-9]+}})
diff --git a/test/CodeGen/Mips/unalignedload.ll b/test/CodeGen/Mips/unalignedload.ll
index 2002b1c60abe..9e453a6e794b 100644
--- a/test/CodeGen/Mips/unalignedload.ll
+++ b/test/CodeGen/Mips/unalignedload.ll
@@ -30,7 +30,7 @@ entry:
 
 ; MIPS32R6-DAG:  lhu $[[PART1:[0-9]+]], 2($[[R0]])
 
-  tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2* @s2, i32 0, i32 1)) nounwind
+  tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2, %struct.S2* @s2, i32 0, i32 1)) nounwind
   ret void
 }
 
diff --git a/test/CodeGen/Mips/vector-load-store.ll b/test/CodeGen/Mips/vector-load-store.ll
index d88996309908..61cbc5a6dee1 100644
--- a/test/CodeGen/Mips/vector-load-store.ll
+++ b/test/CodeGen/Mips/vector-load-store.ll
@@ -10,7 +10,7 @@ entry:
 ; CHECK: lw
 ; CHECK: sw
 
-  %0 = load <2 x i16>* @g1, align 4
+  %0 = load <2 x i16>, <2 x i16>* @g1, align 4
   store <2 x i16> %0, <2 x i16>* @g0, align 4
   ret void
 }
@@ -20,7 +20,7 @@ entry:
 ; CHECK: lw
 ; CHECK: sw
 
-  %0 = load <4 x i8>* @g3, align 4
+  %0 = load <4 x i8>, <4 x i8>* @g3, align 4
   store <4 x i8> %0, <4 x i8>* @g2, align 4
   ret void
 }
diff --git a/test/CodeGen/Mips/vector-setcc.ll b/test/CodeGen/Mips/vector-setcc.ll
index aeff4918c8bb..64b84e40513e 100644
--- a/test/CodeGen/Mips/vector-setcc.ll
+++ b/test/CodeGen/Mips/vector-setcc.ll
@@ -6,8 +6,8 @@
 
 define void @foo0() nounwind {
 entry:
-  %0 = load <4 x i32>* @a, align 16
-  %1 = load <4 x i32>* @b, align 16
+  %0 = load <4 x i32>, <4 x i32>* @a, align 16
+  %1 = load <4 x i32>, <4 x i32>* @b, align 16
   %cmp = icmp slt <4 x i32> %0, %1
   %sext = sext <4 x i1> %cmp to <4 x i32>
   store <4 x i32> %sext, <4 x i32>* @g0, align 16
diff --git a/test/CodeGen/Mips/xor1.ll b/test/CodeGen/Mips/xor1.ll
index f2c13169cf7a..dd51f143bb6c 100644
--- a/test/CodeGen/Mips/xor1.ll
+++ b/test/CodeGen/Mips/xor1.ll
@@ -6,11 +6,11 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @x, align 4
-  %1 = load i32* @y, align 4
+  %0 = load i32, i32* @x, align 4
+  %1 = load i32, i32* @y, align 4
   %xor = xor i32 %0, %1
 ; 16:	xor	${{[0-9]+}}, ${{[0-9]+}}
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), i32 %xor)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %xor)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Mips/zeroreg.ll b/test/CodeGen/Mips/zeroreg.ll
index c766d3b3cc2a..6baf9d4fbff2 100644
--- a/test/CodeGen/Mips/zeroreg.ll
+++ b/test/CodeGen/Mips/zeroreg.ll
@@ -25,7 +25,7 @@ entry:
 ; 64R6:          seleqz $2, $[[R0]], $4
 
   %tobool = icmp ne i32 %s, 0
-  %0 = load i32* @g1, align 4
+  %0 = load i32, i32* @g1, align 4
   %cond = select i1 %tobool, i32 0, i32 %0
   ret i32 %cond
 }
@@ -47,7 +47,7 @@ entry:
 ; 64R6:          selnez $2, $[[R0]], $4
 
   %tobool = icmp ne i32 %s, 0
-  %0 = load i32* @g1, align 4
+  %0 = load i32, i32* @g1, align 4
   %cond = select i1 %tobool, i32 %0, i32 0
   ret i32 %cond
 }
@@ -76,7 +76,7 @@ entry:
 ; 64R6:          seleqz $2, $[[R0]], $4
 
   %tobool = icmp ne i64 %s, 0
-  %0 = load i64* @g2, align 4
+  %0 = load i64, i64* @g2, align 4
   %cond = select i1 %tobool, i64 0, i64 %0
   ret i64 %cond
 }
@@ -103,7 +103,7 @@ entry:
 ; 64R6:          selnez $2, $[[R0]], $4
 
   %tobool = icmp ne i64 %s, 0
-  %0 = load i64* @g2, align 4
+  %0 = load i64, i64* @g2, align 4
   %cond = select i1 %tobool, i64 %0, i64 0
   ret i64 %cond
 }
diff --git a/test/CodeGen/NVPTX/access-non-generic.ll b/test/CodeGen/NVPTX/access-non-generic.ll
index c225abf0fd85..e709302918f5 100644
--- a/test/CodeGen/NVPTX/access-non-generic.ll
+++ b/test/CodeGen/NVPTX/access-non-generic.ll
@@ -18,7 +18,7 @@ define float @ld_st_shared_f32(i32 %i, float %v) {
 ; IR-NOT: addrspacecast
 ; PTX-LABEL: ld_st_shared_f32(
   ; load cast
-  %1 = load float* addrspacecast (float addrspace(3)* @scalar to float*), align 4
+  %1 = load float, float* addrspacecast (float addrspace(3)* @scalar to float*), align 4
 ; PTX: ld.shared.f32 %f{{[0-9]+}}, [scalar];
   ; store cast
   store float %v, float* addrspacecast (float addrspace(3)* @scalar to float*), align 4
@@ -29,7 +29,7 @@ define float @ld_st_shared_f32(i32 %i, float %v) {
 
   ; cast; load
   %2 = addrspacecast float addrspace(3)* @scalar to float*
-  %3 = load float* %2, align 4
+  %3 = load float, float* %2, align 4
 ; PTX: ld.shared.f32 %f{{[0-9]+}}, [scalar];
   ; cast; store
   store float %v, float* %2, align 4
@@ -38,17 +38,17 @@ define float @ld_st_shared_f32(i32 %i, float %v) {
 ; PTX: bar.sync 0;
 
   ; load gep cast
-  %4 = load float* getelementptr inbounds ([10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i32 0, i32 5), align 4
+  %4 = load float, float* getelementptr inbounds ([10 x float], [10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i32 0, i32 5), align 4
 ; PTX: ld.shared.f32 %f{{[0-9]+}}, [array+20];
   ; store gep cast
-  store float %v, float* getelementptr inbounds ([10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i32 0, i32 5), align 4
+  store float %v, float* getelementptr inbounds ([10 x float], [10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i32 0, i32 5), align 4
 ; PTX: st.shared.f32 [array+20], %f{{[0-9]+}};
   call void @llvm.cuda.syncthreads()
 ; PTX: bar.sync 0;
 
   ; gep cast; load
-  %5 = getelementptr inbounds [10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i32 0, i32 5
-  %6 = load float* %5, align 4
+  %5 = getelementptr inbounds [10 x float], [10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i32 0, i32 5
+  %6 = load float, float* %5, align 4
 ; PTX: ld.shared.f32 %f{{[0-9]+}}, [array+20];
   ; gep cast; store
   store float %v, float* %5, align 4
@@ -58,8 +58,8 @@ define float @ld_st_shared_f32(i32 %i, float %v) {
 
   ; cast; gep; load
   %7 = addrspacecast [10 x float] addrspace(3)* @array to [10 x float]*
-  %8 = getelementptr inbounds [10 x float]* %7, i32 0, i32 %i
-  %9 = load float* %8, align 4
+  %8 = getelementptr inbounds [10 x float], [10 x float]* %7, i32 0, i32 %i
+  %9 = load float, float* %8, align 4
 ; PTX: ld.shared.f32 %f{{[0-9]+}}, [%{{(r|rl|rd)[0-9]+}}];
   ; cast; gep; store
   store float %v, float* %8, align 4
@@ -78,10 +78,10 @@ define float @ld_st_shared_f32(i32 %i, float %v) {
 ; addrspacecast with a bitcast.
 define i32 @ld_int_from_float() {
 ; IR-LABEL: @ld_int_from_float
-; IR: load i32 addrspace(3)* bitcast (float addrspace(3)* @scalar to i32 addrspace(3)*)
+; IR: load i32, i32 addrspace(3)* bitcast (float addrspace(3)* @scalar to i32 addrspace(3)*)
 ; PTX-LABEL: ld_int_from_float(
 ; PTX: ld.shared.u{{(32|64)}}
-  %1 = load i32* addrspacecast(float addrspace(3)* @scalar to i32*), align 4
+  %1 = load i32, i32* addrspacecast(float addrspace(3)* @scalar to i32*), align 4
   ret i32 %1
 }
 
diff --git a/test/CodeGen/NVPTX/addrspacecast-gvar.ll b/test/CodeGen/NVPTX/addrspacecast-gvar.ll
index 6afbdb8a429f..1e2fde4b858a 100644
--- a/test/CodeGen/NVPTX/addrspacecast-gvar.ll
+++ b/test/CodeGen/NVPTX/addrspacecast-gvar.ll
@@ -3,7 +3,11 @@
 ; CHECK: .visible .global .align 4 .u32 g = 42;
 ; CHECK: .visible .global .align 4 .u32 g2 = generic(g);
 ; CHECK: .visible .global .align 4 .u32 g3 = g;
+; CHECK: .visible .global .align 8 .u32 g4[2] = {0, generic(g)};
+; CHECK: .visible .global .align 8 .u32 g5[2] = {0, generic(g)+8};
 
 @g = addrspace(1) global i32 42
 @g2 = addrspace(1) global i32* addrspacecast (i32 addrspace(1)* @g to i32*)
 @g3 = addrspace(1) global i32 addrspace(1)* @g
+@g4 = constant {i32*, i32*} {i32* null, i32* addrspacecast (i32 addrspace(1)* @g to i32*)}
+@g5 = constant {i32*, i32*} {i32* null, i32* addrspacecast (i32 addrspace(1)* getelementptr (i32, i32 addrspace(1)* @g, i32 2) to i32*)}
diff --git a/test/CodeGen/NVPTX/addrspacecast.ll b/test/CodeGen/NVPTX/addrspacecast.ll
index 03b9a9844752..42e67ca8ce9b 100644
--- a/test/CodeGen/NVPTX/addrspacecast.ll
+++ b/test/CodeGen/NVPTX/addrspacecast.ll
@@ -10,7 +10,7 @@ define i32 @conv1(i32 addrspace(1)* %ptr) {
 ; PTX64: cvta.global.u64
 ; PTX64: ld.u32
   %genptr = addrspacecast i32 addrspace(1)* %ptr to i32*
-  %val = load i32* %genptr
+  %val = load i32, i32* %genptr
   ret i32 %val
 }
 
@@ -22,7 +22,7 @@ define i32 @conv2(i32 addrspace(3)* %ptr) {
 ; PTX64: cvta.shared.u64
 ; PTX64: ld.u32
   %genptr = addrspacecast i32 addrspace(3)* %ptr to i32*
-  %val = load i32* %genptr
+  %val = load i32, i32* %genptr
   ret i32 %val
 }
 
@@ -34,7 +34,7 @@ define i32 @conv3(i32 addrspace(4)* %ptr) {
 ; PTX64: cvta.const.u64
 ; PTX64: ld.u32
   %genptr = addrspacecast i32 addrspace(4)* %ptr to i32*
-  %val = load i32* %genptr
+  %val = load i32, i32* %genptr
   ret i32 %val
 }
 
@@ -46,7 +46,7 @@ define i32 @conv4(i32 addrspace(5)* %ptr) {
 ; PTX64: cvta.local.u64
 ; PTX64: ld.u32
   %genptr = addrspacecast i32 addrspace(5)* %ptr to i32*
-  %val = load i32* %genptr
+  %val = load i32, i32* %genptr
   ret i32 %val
 }
 
@@ -58,7 +58,7 @@ define i32 @conv5(i32* %ptr) {
 ; PTX64: cvta.to.global.u64
 ; PTX64: ld.global.u32
   %specptr = addrspacecast i32* %ptr to i32 addrspace(1)*
-  %val = load i32 addrspace(1)* %specptr
+  %val = load i32, i32 addrspace(1)* %specptr
   ret i32 %val
 }
 
@@ -70,7 +70,7 @@ define i32 @conv6(i32* %ptr) {
 ; PTX64: cvta.to.shared.u64
 ; PTX64: ld.shared.u32
   %specptr = addrspacecast i32* %ptr to i32 addrspace(3)*
-  %val = load i32 addrspace(3)* %specptr
+  %val = load i32, i32 addrspace(3)* %specptr
   ret i32 %val
 }
 
@@ -82,7 +82,7 @@ define i32 @conv7(i32* %ptr) {
 ; PTX64: cvta.to.const.u64
 ; PTX64: ld.const.u32
   %specptr = addrspacecast i32* %ptr to i32 addrspace(4)*
-  %val = load i32 addrspace(4)* %specptr
+  %val = load i32, i32 addrspace(4)* %specptr
   ret i32 %val
 }
 
@@ -94,6 +94,6 @@ define i32 @conv8(i32* %ptr) {
 ; PTX64: cvta.to.local.u64
 ; PTX64: ld.local.u32
   %specptr = addrspacecast i32* %ptr to i32 addrspace(5)*
-  %val = load i32 addrspace(5)* %specptr
+  %val = load i32, i32 addrspace(5)* %specptr
   ret i32 %val
 }
diff --git a/test/CodeGen/NVPTX/bug21465.ll b/test/CodeGen/NVPTX/bug21465.ll
index cacffceac517..76af386c6516 100644
--- a/test/CodeGen/NVPTX/bug21465.ll
+++ b/test/CodeGen/NVPTX/bug21465.ll
@@ -11,8 +11,8 @@ entry:
 ; CHECK-LABEL @_Z22TakesStruct1SPi
 ; CHECK:   bitcast %struct.S* %input to i8*
 ; CHECK:   call i8 addrspace(101)* @llvm.nvvm.ptr.gen.to.param.p101i8.p0i8
-  %b = getelementptr inbounds %struct.S* %input, i64 0, i32 1
-  %0 = load i32* %b, align 4
+  %b = getelementptr inbounds %struct.S, %struct.S* %input, i64 0, i32 1
+  %0 = load i32, i32* %b, align 4
   store i32 %0, i32* %output, align 4
   ret void
 }
diff --git a/test/CodeGen/NVPTX/bug22246.ll b/test/CodeGen/NVPTX/bug22246.ll
new file mode 100644
index 000000000000..70e7e12336e7
--- /dev/null
+++ b/test/CodeGen/NVPTX/bug22246.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
+target triple = "nvptx64-nvidia-cuda"
+
+; CHECK-LABEL: _Z3foobbbPb
+define void @_Z3foobbbPb(i1 zeroext %p1, i1 zeroext %p2, i1 zeroext %p3, i8* nocapture %output) {
+entry:
+; CHECK: selp.b32       %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %p{{[0-9]+}}
+  %.sink.v = select i1 %p1, i1 %p2, i1 %p3
+  %frombool5 = zext i1 %.sink.v to i8
+  store i8 %frombool5, i8* %output, align 1
+  ret void
+}
diff --git a/test/CodeGen/NVPTX/bug22322.ll b/test/CodeGen/NVPTX/bug22322.ll
new file mode 100644
index 000000000000..97863b9ea546
--- /dev/null
+++ b/test/CodeGen/NVPTX/bug22322.ll
@@ -0,0 +1,62 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
+target triple = "nvptx64-nvidia-cuda"
+
+%class.float3 = type { float, float, float }
+
+; Function Attrs: nounwind
+; CHECK-LABEL: some_kernel
+define void @some_kernel(%class.float3* nocapture %dst) #0 {
+_ZL11compute_vecRK6float3jb.exit:
+  %ret_vec.sroa.8.i = alloca float, align 4
+  %0 = tail call i32 @llvm.ptx.read.ctaid.x()
+  %1 = tail call i32 @llvm.ptx.read.ntid.x()
+  %2 = mul nsw i32 %1, %0
+  %3 = tail call i32 @llvm.ptx.read.tid.x()
+  %4 = add nsw i32 %2, %3
+  %5 = zext i32 %4 to i64
+  %6 = bitcast float* %ret_vec.sroa.8.i to i8*
+  call void @llvm.lifetime.start(i64 4, i8* %6)
+  %7 = and i32 %4, 15
+  %8 = icmp eq i32 %7, 0
+  %9 = select i1 %8, float 0.000000e+00, float -1.000000e+00
+  store float %9, float* %ret_vec.sroa.8.i, align 4
+; CHECK: setp.lt.f32     %p{{[0-9]+}}, %f{{[0-9]+}}, 0f00000000
+  %10 = fcmp olt float %9, 0.000000e+00
+  %ret_vec.sroa.8.i.val = load float, float* %ret_vec.sroa.8.i, align 4
+  %11 = select i1 %10, float 0.000000e+00, float %ret_vec.sroa.8.i.val
+  call void @llvm.lifetime.end(i64 4, i8* %6)
+  %12 = getelementptr inbounds %class.float3, %class.float3* %dst, i64 %5, i32 0
+  store float 0.000000e+00, float* %12, align 4
+  %13 = getelementptr inbounds %class.float3, %class.float3* %dst, i64 %5, i32 1
+  store float %11, float* %13, align 4
+  %14 = getelementptr inbounds %class.float3, %class.float3* %dst, i64 %5, i32 2
+  store float 0.000000e+00, float* %14, align 4
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ptx.read.ctaid.x() #1
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ptx.read.ntid.x() #1
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ptx.read.tid.x() #1
+
+; Function Attrs: nounwind
+declare void @llvm.lifetime.start(i64, i8* nocapture) #2
+
+; Function Attrs: nounwind
+declare void @llvm.lifetime.end(i64, i8* nocapture) #2
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="true" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind }
+
+!nvvm.annotations = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{void (%class.float3*)* @some_kernel, !"kernel", i32 1}
+!1 = !{!"clang version 3.5.1 (tags/RELEASE_351/final)"}
diff --git a/test/CodeGen/NVPTX/call-with-alloca-buffer.ll b/test/CodeGen/NVPTX/call-with-alloca-buffer.ll
index 8483112381f1..58b191129917 100644
--- a/test/CodeGen/NVPTX/call-with-alloca-buffer.ll
+++ b/test/CodeGen/NVPTX/call-with-alloca-buffer.ll
@@ -27,22 +27,22 @@ entry:
 ; CHECK: ld.f32 %f[[A0_REG:[0-9]+]], [%rd[[A_REG]]]
 ; CHECK: st.f32 [%SP+0], %f[[A0_REG]]
 
-  %0 = load float* %a, align 4
+  %0 = load float, float* %a, align 4
   %1 = bitcast [16 x i8]* %buf to float*
   store float %0, float* %1, align 4
-  %arrayidx2 = getelementptr inbounds float* %a, i64 1
-  %2 = load float* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds [16 x i8]* %buf, i64 0, i64 1
+  %arrayidx2 = getelementptr inbounds float, float* %a, i64 1
+  %2 = load float, float* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i64 0, i64 1
   %3 = bitcast i8* %arrayidx3 to float*
   store float %2, float* %3, align 4
-  %arrayidx4 = getelementptr inbounds float* %a, i64 2
-  %4 = load float* %arrayidx4, align 4
-  %arrayidx5 = getelementptr inbounds [16 x i8]* %buf, i64 0, i64 2
+  %arrayidx4 = getelementptr inbounds float, float* %a, i64 2
+  %4 = load float, float* %arrayidx4, align 4
+  %arrayidx5 = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i64 0, i64 2
   %5 = bitcast i8* %arrayidx5 to float*
   store float %4, float* %5, align 4
-  %arrayidx6 = getelementptr inbounds float* %a, i64 3
-  %6 = load float* %arrayidx6, align 4
-  %arrayidx7 = getelementptr inbounds [16 x i8]* %buf, i64 0, i64 3
+  %arrayidx6 = getelementptr inbounds float, float* %a, i64 3
+  %6 = load float, float* %arrayidx6, align 4
+  %arrayidx7 = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i64 0, i64 3
   %7 = bitcast i8* %arrayidx7 to float*
   store float %6, float* %7, align 4
 
@@ -54,7 +54,7 @@ entry:
 ; CHECK-NEXT:   call.uni
 ; CHECK-NEXT:   callee,
 
-  %arraydecay = getelementptr inbounds [16 x i8]* %buf, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i64 0, i64 0
   call void @callee(float* %a, i8* %arraydecay) #2
   ret void
 }
diff --git a/test/CodeGen/NVPTX/fp16.ll b/test/CodeGen/NVPTX/fp16.ll
index 8770399f2ec9..b85eed0f6c7f 100644
--- a/test/CodeGen/NVPTX/fp16.ll
+++ b/test/CodeGen/NVPTX/fp16.ll
@@ -8,7 +8,7 @@ declare i16 @llvm.convert.to.fp16.f64(double) nounwind readnone
 ; CHECK-LABEL: @test_convert_fp16_to_fp32
 ; CHECK: cvt.f32.f16
 define void @test_convert_fp16_to_fp32(float addrspace(1)* noalias %out, i16 addrspace(1)* noalias %in) nounwind {
-  %val = load i16 addrspace(1)* %in, align 2
+  %val = load i16, i16 addrspace(1)* %in, align 2
   %cvt = call float @llvm.convert.from.fp16.f32(i16 %val) nounwind readnone
   store float %cvt, float addrspace(1)* %out, align 4
   ret void
@@ -18,7 +18,7 @@ define void @test_convert_fp16_to_fp32(float addrspace(1)* noalias %out, i16 add
 ; CHECK-LABEL: @test_convert_fp16_to_fp64
 ; CHECK: cvt.f64.f16
 define void @test_convert_fp16_to_fp64(double addrspace(1)* noalias %out, i16 addrspace(1)* noalias %in) nounwind {
-  %val = load i16 addrspace(1)* %in, align 2
+  %val = load i16, i16 addrspace(1)* %in, align 2
   %cvt = call double @llvm.convert.from.fp16.f64(i16 %val) nounwind readnone
   store double %cvt, double addrspace(1)* %out, align 4
   ret void
@@ -28,7 +28,7 @@ define void @test_convert_fp16_to_fp64(double addrspace(1)* noalias %out, i16 ad
 ; CHECK-LABEL: @test_convert_fp32_to_fp16
 ; CHECK: cvt.rn.f16.f32
 define void @test_convert_fp32_to_fp16(i16 addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
-  %val = load float addrspace(1)* %in, align 2
+  %val = load float, float addrspace(1)* %in, align 2
   %cvt = call i16 @llvm.convert.to.fp16.f32(float %val) nounwind readnone
   store i16 %cvt, i16 addrspace(1)* %out, align 4
   ret void
@@ -38,7 +38,7 @@ define void @test_convert_fp32_to_fp16(i16 addrspace(1)* noalias %out, float add
 ; CHECK-LABEL: @test_convert_fp64_to_fp16
 ; CHECK: cvt.rn.f16.f64
 define void @test_convert_fp64_to_fp16(i16 addrspace(1)* noalias %out, double addrspace(1)* noalias %in) nounwind {
-  %val = load double addrspace(1)* %in, align 2
+  %val = load double, double addrspace(1)* %in, align 2
   %cvt = call i16 @llvm.convert.to.fp16.f64(double %val) nounwind readnone
   store i16 %cvt, i16 addrspace(1)* %out, align 4
   ret void
diff --git a/test/CodeGen/NVPTX/function-align.ll b/test/CodeGen/NVPTX/function-align.ll
new file mode 100644
index 000000000000..e7abfb128f58
--- /dev/null
+++ b/test/CodeGen/NVPTX/function-align.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+; CHECK-NOT: .align 2
+define ptx_device void @foo() align 2 {
+; CHECK-LABEL: .func foo
+  ret void
+}
diff --git a/test/CodeGen/NVPTX/generic-to-nvvm.ll b/test/CodeGen/NVPTX/generic-to-nvvm.ll
index fb63d6ed575f..66917d5cb182 100644
--- a/test/CodeGen/NVPTX/generic-to-nvvm.ll
+++ b/test/CodeGen/NVPTX/generic-to-nvvm.ll
@@ -13,9 +13,9 @@ target triple = "nvptx-nvidia-cuda"
 
 define void @foo(i32* %a, i32* %b) {
 ; CHECK: cvta.global.u32
-  %ld1 = load i32* @myglobal
+  %ld1 = load i32, i32* @myglobal
 ; CHECK: cvta.global.u32
-  %ld2 = load i32* @myconst
+  %ld2 = load i32, i32* @myconst
   store i32 %ld1, i32* %a
   store i32 %ld2, i32* %b
   ret void
diff --git a/test/CodeGen/NVPTX/half.ll b/test/CodeGen/NVPTX/half.ll
index aa08cc78e91a..b99524162e65 100644
--- a/test/CodeGen/NVPTX/half.ll
+++ b/test/CodeGen/NVPTX/half.ll
@@ -4,7 +4,7 @@ define void @test_load_store(half addrspace(1)* %in, half addrspace(1)* %out) {
 ; CHECK-LABEL: @test_load_store
 ; CHECK: ld.global.u16 [[TMP:%rs[0-9]+]], [{{%r[0-9]+}}]
 ; CHECK: st.global.u16 [{{%r[0-9]+}}], [[TMP]]
-  %val = load half addrspace(1)* %in
+  %val = load half, half addrspace(1)* %in
   store half %val, half addrspace(1) * %out
   ret void
 }
@@ -13,7 +13,7 @@ define void @test_bitcast_from_half(half addrspace(1)* %in, i16 addrspace(1)* %o
 ; CHECK-LABEL: @test_bitcast_from_half
 ; CHECK: ld.global.u16 [[TMP:%rs[0-9]+]], [{{%r[0-9]+}}]
 ; CHECK: st.global.u16 [{{%r[0-9]+}}], [[TMP]]
-  %val = load half addrspace(1) * %in
+  %val = load half, half addrspace(1) * %in
   %val_int = bitcast half %val to i16
   store i16 %val_int, i16 addrspace(1)* %out
   ret void
@@ -23,7 +23,7 @@ define void @test_bitcast_to_half(half addrspace(1)* %out, i16 addrspace(1)* %in
 ; CHECK-LABEL: @test_bitcast_to_half
 ; CHECK: ld.global.u16 [[TMP:%rs[0-9]+]], [{{%r[0-9]+}}]
 ; CHECK: st.global.u16 [{{%r[0-9]+}}], [[TMP]]
-  %val = load i16 addrspace(1)* %in
+  %val = load i16, i16 addrspace(1)* %in
   %val_fp = bitcast i16 %val to half
   store half %val_fp, half addrspace(1)* %out
   ret void
@@ -33,7 +33,7 @@ define void @test_extend32(half addrspace(1)* %in, float addrspace(1)* %out) {
 ; CHECK-LABEL: @test_extend32
 ; CHECK: cvt.f32.f16
 
-  %val16 = load half addrspace(1)* %in
+  %val16 = load half, half addrspace(1)* %in
   %val32 = fpext half %val16 to float
   store float %val32, float addrspace(1)* %out
   ret void
@@ -43,7 +43,7 @@ define void @test_extend64(half addrspace(1)* %in, double addrspace(1)* %out) {
 ; CHECK-LABEL: @test_extend64
 ; CHECK: cvt.f64.f16
 
-  %val16 = load half addrspace(1)* %in
+  %val16 = load half, half addrspace(1)* %in
   %val64 = fpext half %val16 to double
   store double %val64, double addrspace(1)* %out
   ret void
@@ -53,7 +53,7 @@ define void @test_trunc32(float addrspace(1)* %in, half addrspace(1)* %out) {
 ; CHECK-LABEL: test_trunc32
 ; CHECK: cvt.rn.f16.f32
 
-  %val32 = load float addrspace(1)* %in
+  %val32 = load float, float addrspace(1)* %in
   %val16 = fptrunc float %val32 to half
   store half %val16, half addrspace(1)* %out
   ret void
@@ -63,7 +63,7 @@ define void @test_trunc64(double addrspace(1)* %in, half addrspace(1)* %out) {
 ; CHECK-LABEL: @test_trunc64
 ; CHECK: cvt.rn.f16.f64
 
-  %val32 = load double addrspace(1)* %in
+  %val32 = load double, double addrspace(1)* %in
   %val16 = fptrunc double %val32 to half
   store half %val16, half addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/NVPTX/i1-global.ll b/test/CodeGen/NVPTX/i1-global.ll
index e3fe08e5f874..35d77b4b44d2 100644
--- a/test/CodeGen/NVPTX/i1-global.ll
+++ b/test/CodeGen/NVPTX/i1-global.ll
@@ -8,7 +8,7 @@ target triple = "nvptx-nvidia-cuda"
 
 
 define void @foo(i1 %p, i32* %out) {
-  %ld = load i1 addrspace(1)* @mypred
+  %ld = load i1, i1 addrspace(1)* @mypred
   %val = zext i1 %ld to i32
   store i32 %val, i32* %out
   ret void
diff --git a/test/CodeGen/NVPTX/i8-param.ll b/test/CodeGen/NVPTX/i8-param.ll
index 84daa9f66316..6a1e3a0e1a0d 100644
--- a/test/CodeGen/NVPTX/i8-param.ll
+++ b/test/CodeGen/NVPTX/i8-param.ll
@@ -13,7 +13,7 @@ define i8 @callee(i8 %a) {
 ; CHECK: .visible .func caller
 define void @caller(i8* %a) {
 ; CHECK: ld.u8
-  %val = load i8* %a
+  %val = load i8, i8* %a
   %ret = tail call i8 @callee(i8 %val)
 ; CHECK: ld.param.b32
   store i8 %ret, i8* %a
diff --git a/test/CodeGen/NVPTX/ld-addrspace.ll b/test/CodeGen/NVPTX/ld-addrspace.ll
index f33659c92e84..0018e6177be8 100644
--- a/test/CodeGen/NVPTX/ld-addrspace.ll
+++ b/test/CodeGen/NVPTX/ld-addrspace.ll
@@ -8,7 +8,7 @@ define i8 @ld_global_i8(i8 addrspace(1)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.global.u8 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i8 addrspace(1)* %ptr
+  %a = load i8, i8 addrspace(1)* %ptr
   ret i8 %a
 }
 
@@ -17,7 +17,7 @@ define i8 @ld_shared_i8(i8 addrspace(3)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.shared.u8 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i8 addrspace(3)* %ptr
+  %a = load i8, i8 addrspace(3)* %ptr
   ret i8 %a
 }
 
@@ -26,7 +26,7 @@ define i8 @ld_local_i8(i8 addrspace(5)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.local.u8 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i8 addrspace(5)* %ptr
+  %a = load i8, i8 addrspace(5)* %ptr
   ret i8 %a
 }
 
@@ -36,7 +36,7 @@ define i16 @ld_global_i16(i16 addrspace(1)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.global.u16 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i16 addrspace(1)* %ptr
+  %a = load i16, i16 addrspace(1)* %ptr
   ret i16 %a
 }
 
@@ -45,7 +45,7 @@ define i16 @ld_shared_i16(i16 addrspace(3)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.shared.u16 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i16 addrspace(3)* %ptr
+  %a = load i16, i16 addrspace(3)* %ptr
   ret i16 %a
 }
 
@@ -54,7 +54,7 @@ define i16 @ld_local_i16(i16 addrspace(5)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.local.u16 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i16 addrspace(5)* %ptr
+  %a = load i16, i16 addrspace(5)* %ptr
   ret i16 %a
 }
 
@@ -64,7 +64,7 @@ define i32 @ld_global_i32(i32 addrspace(1)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.global.u32 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i32 addrspace(1)* %ptr
+  %a = load i32, i32 addrspace(1)* %ptr
   ret i32 %a
 }
 
@@ -73,7 +73,7 @@ define i32 @ld_shared_i32(i32 addrspace(3)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.shared.u32 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i32 addrspace(3)* %ptr
+  %a = load i32, i32 addrspace(3)* %ptr
   ret i32 %a
 }
 
@@ -82,7 +82,7 @@ define i32 @ld_local_i32(i32 addrspace(5)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.local.u32 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i32 addrspace(5)* %ptr
+  %a = load i32, i32 addrspace(5)* %ptr
   ret i32 %a
 }
 
@@ -92,7 +92,7 @@ define i64 @ld_global_i64(i64 addrspace(1)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.global.u64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i64 addrspace(1)* %ptr
+  %a = load i64, i64 addrspace(1)* %ptr
   ret i64 %a
 }
 
@@ -101,7 +101,7 @@ define i64 @ld_shared_i64(i64 addrspace(3)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.shared.u64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i64 addrspace(3)* %ptr
+  %a = load i64, i64 addrspace(3)* %ptr
   ret i64 %a
 }
 
@@ -110,7 +110,7 @@ define i64 @ld_local_i64(i64 addrspace(5)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.local.u64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i64 addrspace(5)* %ptr
+  %a = load i64, i64 addrspace(5)* %ptr
   ret i64 %a
 }
 
@@ -120,7 +120,7 @@ define float @ld_global_f32(float addrspace(1)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.global.f32 %f{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load float addrspace(1)* %ptr
+  %a = load float, float addrspace(1)* %ptr
   ret float %a
 }
 
@@ -129,7 +129,7 @@ define float @ld_shared_f32(float addrspace(3)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.shared.f32 %f{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load float addrspace(3)* %ptr
+  %a = load float, float addrspace(3)* %ptr
   ret float %a
 }
 
@@ -138,7 +138,7 @@ define float @ld_local_f32(float addrspace(5)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.local.f32 %f{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load float addrspace(5)* %ptr
+  %a = load float, float addrspace(5)* %ptr
   ret float %a
 }
 
@@ -148,7 +148,7 @@ define double @ld_global_f64(double addrspace(1)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.global.f64 %fd{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load double addrspace(1)* %ptr
+  %a = load double, double addrspace(1)* %ptr
   ret double %a
 }
 
@@ -157,7 +157,7 @@ define double @ld_shared_f64(double addrspace(3)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.shared.f64 %fd{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load double addrspace(3)* %ptr
+  %a = load double, double addrspace(3)* %ptr
   ret double %a
 }
 
@@ -166,6 +166,6 @@ define double @ld_local_f64(double addrspace(5)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.local.f64 %fd{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load double addrspace(5)* %ptr
+  %a = load double, double addrspace(5)* %ptr
   ret double %a
 }
diff --git a/test/CodeGen/NVPTX/ld-generic.ll b/test/CodeGen/NVPTX/ld-generic.ll
index d629e0ecc647..44cfe6551b99 100644
--- a/test/CodeGen/NVPTX/ld-generic.ll
+++ b/test/CodeGen/NVPTX/ld-generic.ll
@@ -8,7 +8,7 @@ define i8 @ld_global_i8(i8 addrspace(0)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.u8 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i8 addrspace(0)* %ptr
+  %a = load i8, i8 addrspace(0)* %ptr
   ret i8 %a
 }
 
@@ -18,7 +18,7 @@ define i16 @ld_global_i16(i16 addrspace(0)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.u16 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i16 addrspace(0)* %ptr
+  %a = load i16, i16 addrspace(0)* %ptr
   ret i16 %a
 }
 
@@ -28,7 +28,7 @@ define i32 @ld_global_i32(i32 addrspace(0)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.u32 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i32 addrspace(0)* %ptr
+  %a = load i32, i32 addrspace(0)* %ptr
   ret i32 %a
 }
 
@@ -38,7 +38,7 @@ define i64 @ld_global_i64(i64 addrspace(0)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.u64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load i64 addrspace(0)* %ptr
+  %a = load i64, i64 addrspace(0)* %ptr
   ret i64 %a
 }
 
@@ -48,7 +48,7 @@ define float @ld_global_f32(float addrspace(0)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.f32 %f{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load float addrspace(0)* %ptr
+  %a = load float, float addrspace(0)* %ptr
   ret float %a
 }
 
@@ -58,6 +58,6 @@ define double @ld_global_f64(double addrspace(0)* %ptr) {
 ; PTX32: ret
 ; PTX64: ld.f64 %fd{{[0-9]+}}, [%rd{{[0-9]+}}]
 ; PTX64: ret
-  %a = load double addrspace(0)* %ptr
+  %a = load double, double addrspace(0)* %ptr
   ret double %a
 }
diff --git a/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll b/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
index fd35a7503901..ec96a493021a 100644
--- a/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
+++ b/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
@@ -6,9 +6,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 define void @reg_plus_offset(i32* %a) {
 ; CHECK:        ldu.global.u32  %r{{[0-9]+}}, [%r{{[0-9]+}}+32];
 ; CHECK:        ldu.global.u32  %r{{[0-9]+}}, [%r{{[0-9]+}}+36];
-  %p2 = getelementptr i32* %a, i32 8
+  %p2 = getelementptr i32, i32* %a, i32 8
   %t1 = call i32 @llvm.nvvm.ldu.global.i.i32.p0i32(i32* %p2, i32 4)
-  %p3 = getelementptr i32* %a, i32 9
+  %p3 = getelementptr i32, i32* %a, i32 9
   %t2 = call i32 @llvm.nvvm.ldu.global.i.i32.p0i32(i32* %p3, i32 4)
   %t3 = mul i32 %t1, %t2
   store i32 %t3, i32* %a
diff --git a/test/CodeGen/NVPTX/load-sext-i1.ll b/test/CodeGen/NVPTX/load-sext-i1.ll
index d836740eed94..9fc98a45f59a 100644
--- a/test/CodeGen/NVPTX/load-sext-i1.ll
+++ b/test/CodeGen/NVPTX/load-sext-i1.ll
@@ -6,8 +6,8 @@ target triple = "nvptx-nvidia-cuda"
 define void @main(i1* %a1, i32 %a2, i32* %arg3) {
 ; CHECK: ld.u8
 ; CHECK-NOT: ld.u1
-  %t1 = getelementptr i1* %a1, i32 %a2
-  %t2 = load i1* %t1
+  %t1 = getelementptr i1, i1* %a1, i32 %a2
+  %t2 = load i1, i1* %t1
   %t3 = sext i1 %t2 to i32
   store i32 %t3, i32* %arg3
   ret void
diff --git a/test/CodeGen/NVPTX/machine-sink.ll b/test/CodeGen/NVPTX/machine-sink.ll
index 3614bea16534..65ba141c41d9 100644
--- a/test/CodeGen/NVPTX/machine-sink.ll
+++ b/test/CodeGen/NVPTX/machine-sink.ll
@@ -14,8 +14,8 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 define float @post_dominate(float %x, i1 %cond) {
 ; CHECK-LABEL: post_dominate(
 entry:
-  %0 = load float* addrspacecast (float addrspace(3)* @scalar1 to float*), align 4
-  %1 = load float* addrspacecast (float addrspace(3)* @scalar2 to float*), align 4
+  %0 = load float, float* addrspacecast (float addrspace(3)* @scalar1 to float*), align 4
+  %1 = load float, float* addrspacecast (float addrspace(3)* @scalar2 to float*), align 4
 ; CHECK: ld.shared.f32
 ; CHECK: ld.shared.f32
   %2 = fmul float %0, %0
diff --git a/test/CodeGen/NVPTX/misaligned-vector-ldst.ll b/test/CodeGen/NVPTX/misaligned-vector-ldst.ll
index 90c9c4306de7..2ad72b018851 100644
--- a/test/CodeGen/NVPTX/misaligned-vector-ldst.ll
+++ b/test/CodeGen/NVPTX/misaligned-vector-ldst.ll
@@ -10,7 +10,7 @@ define <4 x float> @t1(i8* %p1) {
 ; CHECK-NOT: ld.f32
 ; CHECK: ld.u8
   %cast = bitcast i8* %p1 to <4 x float>*
-  %r = load <4 x float>* %cast, align 1
+  %r = load <4 x float>, <4 x float>* %cast, align 1
   ret <4 x float> %r
 }
 
@@ -20,7 +20,7 @@ define <4 x float> @t2(i8* %p1) {
 ; CHECK-NOT: ld.v2
 ; CHECK: ld.f32
   %cast = bitcast i8* %p1 to <4 x float>*
-  %r = load <4 x float>* %cast, align 4
+  %r = load <4 x float>, <4 x float>* %cast, align 4
   ret <4 x float> %r
 }
 
@@ -29,7 +29,7 @@ define <4 x float> @t3(i8* %p1) {
 ; CHECK-NOT: ld.v4
 ; CHECK: ld.v2
   %cast = bitcast i8* %p1 to <4 x float>*
-  %r = load <4 x float>* %cast, align 8
+  %r = load <4 x float>, <4 x float>* %cast, align 8
   ret <4 x float> %r
 }
 
@@ -37,7 +37,7 @@ define <4 x float> @t3(i8* %p1) {
 define <4 x float> @t4(i8* %p1) {
 ; CHECK: ld.v4
   %cast = bitcast i8* %p1 to <4 x float>*
-  %r = load <4 x float>* %cast, align 16
+  %r = load <4 x float>, <4 x float>* %cast, align 16
   ret <4 x float> %r
 }
 
diff --git a/test/CodeGen/NVPTX/noduplicate-syncthreads.ll b/test/CodeGen/NVPTX/noduplicate-syncthreads.ll
index 841bbc3a517c..2fec31b3791d 100644
--- a/test/CodeGen/NVPTX/noduplicate-syncthreads.ll
+++ b/test/CodeGen/NVPTX/noduplicate-syncthreads.ll
@@ -11,16 +11,16 @@ define void @foo(float* %output) #1 {
 entry:
   %output.addr = alloca float*, align 8
   store float* %output, float** %output.addr, align 8
-  %0 = load float** %output.addr, align 8
-  %arrayidx = getelementptr inbounds float* %0, i64 0
-  %1 = load float* %arrayidx, align 4
+  %0 = load float*, float** %output.addr, align 8
+  %arrayidx = getelementptr inbounds float, float* %0, i64 0
+  %1 = load float, float* %arrayidx, align 4
   %conv = fpext float %1 to double
   %cmp = fcmp olt double %conv, 1.000000e+01
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  %2 = load float** %output.addr, align 8
-  %3 = load float* %2, align 4
+  %2 = load float*, float** %output.addr, align 8
+  %3 = load float, float* %2, align 4
   %conv1 = fpext float %3 to double
   %add = fadd double %conv1, 1.000000e+00
   %conv2 = fptrunc double %add to float
@@ -28,8 +28,8 @@ if.then:                                          ; preds = %entry
   br label %if.end
 
 if.else:                                          ; preds = %entry
-  %4 = load float** %output.addr, align 8
-  %5 = load float* %4, align 4
+  %4 = load float*, float** %output.addr, align 8
+  %5 = load float, float* %4, align 4
   %conv3 = fpext float %5 to double
   %add4 = fadd double %conv3, 2.000000e+00
   %conv5 = fptrunc double %add4 to float
@@ -38,16 +38,16 @@ if.else:                                          ; preds = %entry
 
 if.end:                                           ; preds = %if.else, %if.then
   call void @llvm.cuda.syncthreads()
-  %6 = load float** %output.addr, align 8
-  %arrayidx6 = getelementptr inbounds float* %6, i64 0
-  %7 = load float* %arrayidx6, align 4
+  %6 = load float*, float** %output.addr, align 8
+  %arrayidx6 = getelementptr inbounds float, float* %6, i64 0
+  %7 = load float, float* %arrayidx6, align 4
   %conv7 = fpext float %7 to double
   %cmp8 = fcmp olt double %conv7, 1.000000e+01
   br i1 %cmp8, label %if.then9, label %if.else13
 
 if.then9:                                         ; preds = %if.end
-  %8 = load float** %output.addr, align 8
-  %9 = load float* %8, align 4
+  %8 = load float*, float** %output.addr, align 8
+  %9 = load float, float* %8, align 4
   %conv10 = fpext float %9 to double
   %add11 = fadd double %conv10, 3.000000e+00
   %conv12 = fptrunc double %add11 to float
@@ -55,8 +55,8 @@ if.then9:                                         ; preds = %if.end
   br label %if.end17
 
 if.else13:                                        ; preds = %if.end
-  %10 = load float** %output.addr, align 8
-  %11 = load float* %10, align 4
+  %10 = load float*, float** %output.addr, align 8
+  %11 = load float, float* %10, align 4
   %conv14 = fpext float %11 to double
   %add15 = fadd double %conv14, 4.000000e+00
   %conv16 = fptrunc double %add15 to float
diff --git a/test/CodeGen/NVPTX/nounroll.ll b/test/CodeGen/NVPTX/nounroll.ll
new file mode 100644
index 000000000000..e80a4a21f161
--- /dev/null
+++ b/test/CodeGen/NVPTX/nounroll.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
+target triple = "nvptx64-unknown-unknown"
+
+; Compiled from the following CUDA code:
+;
+;   #pragma nounroll
+;   for (int i = 0; i < 2; ++i)
+;     output[i] = input[i];
+define void @nounroll(float* %input, float* %output) {
+; CHECK-LABEL: .visible .func nounroll(
+entry:
+  br label %for.body
+
+for.body:
+; CHECK: .pragma "nounroll"
+  %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %idxprom = sext i32 %i.06 to i64
+  %arrayidx = getelementptr inbounds float, float* %input, i64 %idxprom
+  %0 = load float, float* %arrayidx, align 4
+; CHECK: ld.f32
+  %arrayidx2 = getelementptr inbounds float, float* %output, i64 %idxprom
+  store float %0, float* %arrayidx2, align 4
+; CHECK: st.f32
+  %inc = add nuw nsw i32 %i.06, 1
+  %exitcond = icmp eq i32 %inc, 2
+  br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !0
+; CHECK-NOT: ld.f32
+; CHECK-NOT: st.f32
+
+for.end:
+  ret void
+}
+
+!0 = distinct !{!0, !1}
+!1 = !{!"llvm.loop.unroll.disable"}
diff --git a/test/CodeGen/NVPTX/nvvm-reflect.ll b/test/CodeGen/NVPTX/nvvm-reflect.ll
index 21e9c69e657a..8c75dfc30a56 100644
--- a/test/CodeGen/NVPTX/nvvm-reflect.ll
+++ b/test/CodeGen/NVPTX/nvvm-reflect.ll
@@ -11,7 +11,7 @@ define float @foo(float %a, float %b) {
 ; USE_MUL_0-NOT: call i32 @__nvvm_reflect
 ; USE_MUL_1: define float @foo
 ; USE_MUL_1-NOT: call i32 @__nvvm_reflect
-  %ptr = tail call i8* @llvm.nvvm.ptr.constant.to.gen.p0i8.p4i8(i8 addrspace(4)* getelementptr inbounds ([8 x i8] addrspace(4)* @str, i32 0, i32 0))
+  %ptr = tail call i8* @llvm.nvvm.ptr.constant.to.gen.p0i8.p4i8(i8 addrspace(4)* getelementptr inbounds ([8 x i8], [8 x i8] addrspace(4)* @str, i32 0, i32 0))
   %reflect = tail call i32 @__nvvm_reflect(i8* %ptr)
   %cmp = icmp ugt i32 %reflect, 0
   br i1 %cmp, label %use_mul, label %use_add
@@ -42,7 +42,38 @@ define i32 @intrinsic() {
 ; USE_MUL_0: ret i32 0
 ; USE_MUL_1-NOT: call i32 @llvm.nvvm.reflect
 ; USE_MUL_1: ret i32 1
-  %ptr = tail call i8* @llvm.nvvm.ptr.constant.to.gen.p0i8.p4i8(i8 addrspace(4)* getelementptr inbounds ([8 x i8] addrspace(4)* @str, i32 0, i32 0))
+  %ptr = tail call i8* @llvm.nvvm.ptr.constant.to.gen.p0i8.p4i8(i8 addrspace(4)* getelementptr inbounds ([8 x i8], [8 x i8] addrspace(4)* @str, i32 0, i32 0))
   %reflect = tail call i32 @llvm.nvvm.reflect.p0i8(i8* %ptr)
   ret i32 %reflect
 }
+
+; CUDA-7.0 passes __nvvm_reflect argument slightly differently.
+; Verify that it works, too
+
+@"$str" = private addrspace(1) constant [8 x i8] c"USE_MUL\00"
+
+define float @bar(float %a, float %b) {
+; USE_MUL_0: define float @bar
+; USE_MUL_0-NOT: call i32 @__nvvm_reflect
+; USE_MUL_1: define float @bar
+; USE_MUL_1-NOT: call i32 @__nvvm_reflect
+  %reflect = call i32 @__nvvm_reflect(i8* addrspacecast (i8 addrspace(1)* getelementptr inbounds ([8 x i8], [8 x i8] addrspace(1)* @"$str", i32 0, i32 0) to i8*))
+  %cmp = icmp ne i32 %reflect, 0
+  br i1 %cmp, label %use_mul, label %use_add
+
+use_mul:
+; USE_MUL_1: fmul float %a, %b
+; USE_MUL_0-NOT: fadd float %a, %b
+  %ret1 = fmul float %a, %b
+  br label %exit
+
+use_add:
+; USE_MUL_0: fadd float %a, %b
+; USE_MUL_1-NOT: fmul float %a, %b
+  %ret2 = fadd float %a, %b
+  br label %exit
+
+exit:
+  %ret = phi float [%ret1, %use_mul], [%ret2, %use_add]
+  ret float %ret
+}
diff --git a/test/CodeGen/NVPTX/pr13291-i1-store.ll b/test/CodeGen/NVPTX/pr13291-i1-store.ll
index cc67a6fff8e4..d4f7c3bd210a 100644
--- a/test/CodeGen/NVPTX/pr13291-i1-store.ll
+++ b/test/CodeGen/NVPTX/pr13291-i1-store.ll
@@ -19,7 +19,7 @@ define ptx_kernel void @t2(i1* %a, i8* %b) {
 ; PTX64: and.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, 1;
 ; PTX64: setp.eq.b16 %p{{[0-9]+}}, %rs{{[0-9]+}}, 1;
 
-  %t1 = load i1* %a
+  %t1 = load i1, i1* %a
   %t2 = select i1 %t1, i8 1, i8 2
   store i8 %t2, i8* %b
   ret void
diff --git a/test/CodeGen/NVPTX/pr16278.ll b/test/CodeGen/NVPTX/pr16278.ll
index 5432a848442c..a836eaf2e51f 100644
--- a/test/CodeGen/NVPTX/pr16278.ll
+++ b/test/CodeGen/NVPTX/pr16278.ll
@@ -5,6 +5,6 @@
 
 define float @foo() {
 ; CHECK: ld.const.f32
-  %val = load float addrspace(4)* @one_f
+  %val = load float, float addrspace(4)* @one_f
   ret float %val
 }
diff --git a/test/CodeGen/NVPTX/pr17529.ll b/test/CodeGen/NVPTX/pr17529.ll
index a16214225674..a7519776f526 100644
--- a/test/CodeGen/NVPTX/pr17529.ll
+++ b/test/CodeGen/NVPTX/pr17529.ll
@@ -11,7 +11,7 @@ entry:
 
 vector.body:                                      ; preds = %vector.body, %entry
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
-  %scevgep9 = getelementptr i8* %dst, i64 %index
+  %scevgep9 = getelementptr i8, i8* %dst, i64 %index
   %scevgep910 = bitcast i8* %scevgep9 to <4 x i8>*
   store <4 x i8> undef, <4 x i8>* %scevgep910, align 1
   %index.next = add i64 %index, 4
@@ -22,13 +22,13 @@ middle.block:                                     ; preds = %vector.body
   br i1 undef, label %for.end, label %for.body.preheader1
 
 for.body.preheader1:                              ; preds = %middle.block
-  %scevgep2 = getelementptr i8* %dst, i64 0
+  %scevgep2 = getelementptr i8, i8* %dst, i64 0
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %for.body.preheader1
   %lsr.iv3 = phi i8* [ %scevgep2, %for.body.preheader1 ], [ %scevgep4, %for.body ]
   store i8 undef, i8* %lsr.iv3, align 1
-  %scevgep4 = getelementptr i8* %lsr.iv3, i64 1
+  %scevgep4 = getelementptr i8, i8* %lsr.iv3, i64 1
   br label %for.body
 
 for.end:                                          ; preds = %middle.block, %entry
diff --git a/test/CodeGen/NVPTX/ptx-version-30.ll b/test/CodeGen/NVPTX/ptx-version-30.ll
deleted file mode 100644
index 0422b01f4ee3..000000000000
--- a/test/CodeGen/NVPTX/ptx-version-30.ll
+++ /dev/null
@@ -1,6 +0,0 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 -mattr=ptx30 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -mattr=ptx30 | FileCheck %s
-
-
-; CHECK: .version 3.0
-
diff --git a/test/CodeGen/NVPTX/ptx-version-31.ll b/test/CodeGen/NVPTX/ptx-version-31.ll
deleted file mode 100644
index d6e57301a371..000000000000
--- a/test/CodeGen/NVPTX/ptx-version-31.ll
+++ /dev/null
@@ -1,6 +0,0 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 -mattr=ptx31 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -mattr=ptx31 | FileCheck %s
-
-
-; CHECK: .version 3.1
-
diff --git a/test/CodeGen/NVPTX/refl1.ll b/test/CodeGen/NVPTX/refl1.ll
index e8782ea3aa27..0432b67535c0 100644
--- a/test/CodeGen/NVPTX/refl1.ll
+++ b/test/CodeGen/NVPTX/refl1.ll
@@ -5,7 +5,7 @@ target triple = "nvptx-nvidia-cuda"
 ; Function Attrs: nounwind
 ; CHECK: .entry foo
 define void @foo(float* nocapture %a) #0 {
-  %val = load float* %a
+  %val = load float, float* %a
   %tan = tail call fastcc float @__nv_fast_tanf(float %val)
   store float %tan, float* %a
   ret void
diff --git a/test/CodeGen/NVPTX/sched1.ll b/test/CodeGen/NVPTX/sched1.ll
index 03ab635e73b9..fb01eb262adc 100644
--- a/test/CodeGen/NVPTX/sched1.ll
+++ b/test/CodeGen/NVPTX/sched1.ll
@@ -11,14 +11,14 @@ define void @foo(i32* %a) {
 ; CHECK-NEXT: add.s32
 ; CHECK-NEXT: add.s32
 ; CHECK-NEXT: add.s32
-  %ptr0 = getelementptr i32* %a, i32 0
-  %val0 = load i32* %ptr0
-  %ptr1 = getelementptr i32* %a, i32 1
-  %val1 = load i32* %ptr1
-  %ptr2 = getelementptr i32* %a, i32 2
-  %val2 = load i32* %ptr2
-  %ptr3 = getelementptr i32* %a, i32 3
-  %val3 = load i32* %ptr3
+  %ptr0 = getelementptr i32, i32* %a, i32 0
+  %val0 = load i32, i32* %ptr0
+  %ptr1 = getelementptr i32, i32* %a, i32 1
+  %val1 = load i32, i32* %ptr1
+  %ptr2 = getelementptr i32, i32* %a, i32 2
+  %val2 = load i32, i32* %ptr2
+  %ptr3 = getelementptr i32, i32* %a, i32 3
+  %val3 = load i32, i32* %ptr3
 
   %t0 = add i32 %val0, %val1
   %t1 = add i32 %t0, %val2
diff --git a/test/CodeGen/NVPTX/sched2.ll b/test/CodeGen/NVPTX/sched2.ll
index 71a9a4963faf..91ed77878f81 100644
--- a/test/CodeGen/NVPTX/sched2.ll
+++ b/test/CodeGen/NVPTX/sched2.ll
@@ -12,14 +12,14 @@ define void @foo(<2 x i32>* %a) {
 ; CHECK-NEXT: add.s32
 ; CHECK-NEXT: add.s32
 ; CHECK-NEXT: add.s32
-  %ptr0 = getelementptr <2 x i32>* %a, i32 0
-  %val0 = load <2 x i32>* %ptr0
-  %ptr1 = getelementptr <2 x i32>* %a, i32 1
-  %val1 = load <2 x i32>* %ptr1
-  %ptr2 = getelementptr <2 x i32>* %a, i32 2
-  %val2 = load <2 x i32>* %ptr2
-  %ptr3 = getelementptr <2 x i32>* %a, i32 3
-  %val3 = load <2 x i32>* %ptr3
+  %ptr0 = getelementptr <2 x i32>, <2 x i32>* %a, i32 0
+  %val0 = load <2 x i32>, <2 x i32>* %ptr0
+  %ptr1 = getelementptr <2 x i32>, <2 x i32>* %a, i32 1
+  %val1 = load <2 x i32>, <2 x i32>* %ptr1
+  %ptr2 = getelementptr <2 x i32>, <2 x i32>* %a, i32 2
+  %val2 = load <2 x i32>, <2 x i32>* %ptr2
+  %ptr3 = getelementptr <2 x i32>, <2 x i32>* %a, i32 3
+  %val3 = load <2 x i32>, <2 x i32>* %ptr3
 
   %t0 = add <2 x i32> %val0, %val1
   %t1 = add <2 x i32> %t0, %val2
diff --git a/test/CodeGen/NVPTX/shift-parts.ll b/test/CodeGen/NVPTX/shift-parts.ll
index 748297caf339..b4d408ff5972 100644
--- a/test/CodeGen/NVPTX/shift-parts.ll
+++ b/test/CodeGen/NVPTX/shift-parts.ll
@@ -12,8 +12,8 @@ define void @shift_parts_left_128(i128* %val, i128* %amtptr) {
 ; CHECK: setp.gt.s32
 ; CHECK: selp.b64
 ; CHECK: shl.b64
-  %amt = load i128* %amtptr
-  %a = load i128* %val
+  %amt = load i128, i128* %amtptr
+  %a = load i128, i128* %val
   %val0 = shl i128 %a, %amt
   store i128 %val0, i128* %val
   ret void
@@ -30,8 +30,8 @@ define void @shift_parts_right_128(i128* %val, i128* %amtptr) {
 ; CHECK: setp.gt.s32
 ; CHECK: selp.b64
 ; CHECK: shr.s64
-  %amt = load i128* %amtptr
-  %a = load i128* %val
+  %amt = load i128, i128* %amtptr
+  %a = load i128, i128* %val
   %val0 = ashr i128 %a, %amt
   store i128 %val0, i128* %val
   ret void
diff --git a/test/CodeGen/NVPTX/simple-call.ll b/test/CodeGen/NVPTX/simple-call.ll
index 1b41361cf7ed..da6568685fe6 100644
--- a/test/CodeGen/NVPTX/simple-call.ll
+++ b/test/CodeGen/NVPTX/simple-call.ll
@@ -11,7 +11,7 @@ define float @device_func(float %a) noinline {
 
 ; CHECK: .entry kernel_func
 define void @kernel_func(float* %a) {
-  %val = load float* %a
+  %val = load float, float* %a
 ; CHECK: call.uni (retval0),
 ; CHECK: device_func,
   %mul = call float @device_func(float %val)
diff --git a/test/CodeGen/NVPTX/sm-version-30.ll b/test/CodeGen/NVPTX/sm-version-30.ll
index 692b49a0d6b3..4f35cf04c63b 100644
--- a/test/CodeGen/NVPTX/sm-version-30.ll
+++ b/test/CodeGen/NVPTX/sm-version-30.ll
@@ -2,5 +2,6 @@
 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_30 | FileCheck %s
 
 
+; CHECK: .version 3.2
 ; CHECK: .target sm_30
 
diff --git a/test/CodeGen/NVPTX/sm-version-32.ll b/test/CodeGen/NVPTX/sm-version-32.ll
new file mode 100644
index 000000000000..d6a5082c5267
--- /dev/null
+++ b/test/CodeGen/NVPTX/sm-version-32.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_32 | FileCheck %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_32 | FileCheck %s
+
+
+; CHECK: .version 4.0
+; CHECK: .target sm_32
+
diff --git a/test/CodeGen/NVPTX/sm-version-35.ll b/test/CodeGen/NVPTX/sm-version-35.ll
index 25368a01335e..8456c666677d 100644
--- a/test/CodeGen/NVPTX/sm-version-35.ll
+++ b/test/CodeGen/NVPTX/sm-version-35.ll
@@ -2,5 +2,6 @@
 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s
 
 
+; CHECK: .version 3.2
 ; CHECK: .target sm_35
 
diff --git a/test/CodeGen/NVPTX/sm-version-37.ll b/test/CodeGen/NVPTX/sm-version-37.ll
new file mode 100644
index 000000000000..fd51a9c7063f
--- /dev/null
+++ b/test/CodeGen/NVPTX/sm-version-37.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_37 | FileCheck %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_37 | FileCheck %s
+
+
+; CHECK: .version 4.1
+; CHECK: .target sm_37
+
diff --git a/test/CodeGen/NVPTX/sm-version-50.ll b/test/CodeGen/NVPTX/sm-version-50.ll
new file mode 100644
index 000000000000..374c6ea057ae
--- /dev/null
+++ b/test/CodeGen/NVPTX/sm-version-50.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_50 | FileCheck %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_50 | FileCheck %s
+
+
+; CHECK: .version 4.0
+; CHECK: .target sm_50
+
diff --git a/test/CodeGen/NVPTX/sm-version-52.ll b/test/CodeGen/NVPTX/sm-version-52.ll
new file mode 100644
index 000000000000..18881b2e98cc
--- /dev/null
+++ b/test/CodeGen/NVPTX/sm-version-52.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_52 | FileCheck %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_52 | FileCheck %s
+
+
+; CHECK: .version 4.1
+; CHECK: .target sm_52
+
diff --git a/test/CodeGen/NVPTX/sm-version-53.ll b/test/CodeGen/NVPTX/sm-version-53.ll
new file mode 100644
index 000000000000..50d2dec11bc5
--- /dev/null
+++ b/test/CodeGen/NVPTX/sm-version-53.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_53 | FileCheck %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_53 | FileCheck %s
+
+
+; CHECK: .version 4.2
+; CHECK: .target sm_53
+
diff --git a/test/CodeGen/NVPTX/symbol-naming.ll b/test/CodeGen/NVPTX/symbol-naming.ll
index bd1333f1c4e6..0f176934ca39 100644
--- a/test/CodeGen/NVPTX/symbol-naming.ll
+++ b/test/CodeGen/NVPTX/symbol-naming.ll
@@ -24,7 +24,7 @@ target triple = "nvptx64-unknown-unknown"
 ; Function Attrs: nounwind
 define void @foo(i32 %a, float %b, i8 signext %c, i32 %e) {
 entry:
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0))
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0))
   ret void
 }
 
diff --git a/test/CodeGen/NVPTX/vector-compare.ll b/test/CodeGen/NVPTX/vector-compare.ll
index 218049995233..2992b0e62c56 100644
--- a/test/CodeGen/NVPTX/vector-compare.ll
+++ b/test/CodeGen/NVPTX/vector-compare.ll
@@ -6,8 +6,8 @@
 ; tried to promote <2 x i1> to <2 x i8> and instruction selection failed.
 
 define void @foo(<2 x i32>* %a, <2 x i32>* %b, i32* %r1, i32* %r2) {
-  %aval = load <2 x i32>* %a
-  %bval = load <2 x i32>* %b
+  %aval = load <2 x i32>, <2 x i32>* %a
+  %bval = load <2 x i32>, <2 x i32>* %b
   %res = icmp slt <2 x i32> %aval, %bval
   %t1 = extractelement <2 x i1> %res, i32 0
   %t2 = extractelement <2 x i1> %res, i32 1
diff --git a/test/CodeGen/NVPTX/vector-loads.ll b/test/CodeGen/NVPTX/vector-loads.ll
index 58882bf16668..d70348942200 100644
--- a/test/CodeGen/NVPTX/vector-loads.ll
+++ b/test/CodeGen/NVPTX/vector-loads.ll
@@ -10,7 +10,7 @@
 define void @foo(<2 x float>* %a) {
 ; CHECK: .func foo
 ; CHECK: ld.v2.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}}
-  %t1 = load <2 x float>* %a
+  %t1 = load <2 x float>, <2 x float>* %a
   %t2 = fmul <2 x float> %t1, %t1
   store <2 x float> %t2, <2 x float>* %a
   ret void
@@ -19,7 +19,7 @@ define void @foo(<2 x float>* %a) {
 define void @foo2(<4 x float>* %a) {
 ; CHECK: .func foo2
 ; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
-  %t1 = load <4 x float>* %a
+  %t1 = load <4 x float>, <4 x float>* %a
   %t2 = fmul <4 x float> %t1, %t1
   store <4 x float> %t2, <4 x float>* %a
   ret void
@@ -29,7 +29,7 @@ define void @foo3(<8 x float>* %a) {
 ; CHECK: .func foo3
 ; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
 ; CHECK-NEXT: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
-  %t1 = load <8 x float>* %a
+  %t1 = load <8 x float>, <8 x float>* %a
   %t2 = fmul <8 x float> %t1, %t1
   store <8 x float> %t2, <8 x float>* %a
   ret void
@@ -40,7 +40,7 @@ define void @foo3(<8 x float>* %a) {
 define void @foo4(<2 x i32>* %a) {
 ; CHECK: .func foo4
 ; CHECK: ld.v2.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}}
-  %t1 = load <2 x i32>* %a
+  %t1 = load <2 x i32>, <2 x i32>* %a
   %t2 = mul <2 x i32> %t1, %t1
   store <2 x i32> %t2, <2 x i32>* %a
   ret void
@@ -49,7 +49,7 @@ define void @foo4(<2 x i32>* %a) {
 define void @foo5(<4 x i32>* %a) {
 ; CHECK: .func foo5
 ; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
-  %t1 = load <4 x i32>* %a
+  %t1 = load <4 x i32>, <4 x i32>* %a
   %t2 = mul <4 x i32> %t1, %t1
   store <4 x i32> %t2, <4 x i32>* %a
   ret void
@@ -59,7 +59,7 @@ define void @foo6(<8 x i32>* %a) {
 ; CHECK: .func foo6
 ; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
 ; CHECK-NEXT: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
-  %t1 = load <8 x i32>* %a
+  %t1 = load <8 x i32>, <8 x i32>* %a
   %t2 = mul <8 x i32> %t1, %t1
   store <8 x i32> %t2, <8 x i32>* %a
   ret void
diff --git a/test/CodeGen/NVPTX/vector-select.ll b/test/CodeGen/NVPTX/vector-select.ll
index 11893df10329..1e81031c685a 100644
--- a/test/CodeGen/NVPTX/vector-select.ll
+++ b/test/CodeGen/NVPTX/vector-select.ll
@@ -6,9 +6,9 @@
 
 define void @foo(<2 x i32> addrspace(1)* %def_a, <2 x i32> addrspace(1)* %def_b, <2 x i32> addrspace(1)* %def_c) {
 entry:
-  %tmp4 = load <2 x i32> addrspace(1)* %def_a
-  %tmp6 = load <2 x i32> addrspace(1)* %def_c
-  %tmp8 = load <2 x i32> addrspace(1)* %def_b
+  %tmp4 = load <2 x i32>, <2 x i32> addrspace(1)* %def_a
+  %tmp6 = load <2 x i32>, <2 x i32> addrspace(1)* %def_c
+  %tmp8 = load <2 x i32>, <2 x i32> addrspace(1)* %def_b
   %0 = icmp sge <2 x i32> %tmp4, zeroinitializer
   %cond = select <2 x i1> %0, <2 x i32> %tmp6, <2 x i32> %tmp8
   store <2 x i32> %cond, <2 x i32> addrspace(1)* %def_c
diff --git a/test/CodeGen/NVPTX/weak-global.ll b/test/CodeGen/NVPTX/weak-global.ll
index 2bef4c5228a9..a64f9f48b26f 100644
--- a/test/CodeGen/NVPTX/weak-global.ll
+++ b/test/CodeGen/NVPTX/weak-global.ll
@@ -4,6 +4,6 @@
 @g = common addrspace(1) global i32 zeroinitializer
 
 define i32 @func0() {
-  %val = load i32 addrspace(1)* @g
+  %val = load i32, i32 addrspace(1)* @g
   ret i32 %val
 }
diff --git a/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll b/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
index 047a12bedd81..0f56ac990bbe 100644
--- a/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
+++ b/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
@@ -7,7 +7,7 @@ define void @bar(i32 %G, i32 %E, i32 %F, i32 %A, i32 %B, i32 %C, i32 %D, i8* %fm
         %ap = alloca i8*                ; <i8**> [#uses=2]
         %va.upgrd.1 = bitcast i8** %ap to i8*           ; <i8*> [#uses=1]
         call void @llvm.va_start( i8* %va.upgrd.1 )
-        %tmp.1 = load i8** %ap          ; <i8*> [#uses=1]
+        %tmp.1 = load i8*, i8** %ap          ; <i8*> [#uses=1]
         %tmp.0 = call double @foo( i8* %tmp.1 )         ; <double> [#uses=0]
         ret void
 }
diff --git a/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll b/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
index fbf254082ee0..fde330321aa4 100644
--- a/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
+++ b/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
@@ -4,11 +4,11 @@ define void @iterative_hash_host_wide_int() {
         %zero = alloca i32              ; <i32*> [#uses=2]
         %b = alloca i32         ; <i32*> [#uses=1]
         store i32 0, i32* %zero
-        %tmp = load i32* %zero          ; <i32> [#uses=1]
+        %tmp = load i32, i32* %zero          ; <i32> [#uses=1]
         %tmp5 = bitcast i32 %tmp to i32         ; <i32> [#uses=1]
         %tmp6.u = add i32 %tmp5, 32             ; <i32> [#uses=1]
         %tmp6 = bitcast i32 %tmp6.u to i32              ; <i32> [#uses=1]
-        %tmp7 = load i64* null          ; <i64> [#uses=1]
+        %tmp7 = load i64, i64* null          ; <i64> [#uses=1]
         %tmp6.upgrd.1 = trunc i32 %tmp6 to i8           ; <i8> [#uses=1]
         %shift.upgrd.2 = zext i8 %tmp6.upgrd.1 to i64           ; <i64> [#uses=1]
         %tmp8 = ashr i64 %tmp7, %shift.upgrd.2          ; <i64> [#uses=1]
diff --git a/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll b/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll
index 7e845382a8e8..80827dc1505d 100644
--- a/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll
+++ b/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll
@@ -2,7 +2,7 @@
 ; RUN:   grep "vspltish v.*, 10"
 
 define void @test(<8 x i16>* %P) {
-        %tmp = load <8 x i16>* %P               ; <<8 x i16>> [#uses=1]
+        %tmp = load <8 x i16>, <8 x i16>* %P               ; <<8 x i16>> [#uses=1]
         %tmp1 = add <8 x i16> %tmp, < i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10 >          ; <<8 x i16>> [#uses=1]
         store <8 x i16> %tmp1, <8 x i16>* %P
         ret void
diff --git a/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll b/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll
index 0205d10a795c..50d64f46569a 100644
--- a/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll
+++ b/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll
@@ -20,32 +20,32 @@ bb30:		; preds = %entry
 cond_true68:		; preds = %bb30
 	ret void
 cond_next92:		; preds = %bb30
-	%tmp173 = getelementptr %struct.attr_desc* null, i32 0, i32 4		; <i32*> [#uses=2]
-	%tmp174 = load i32* %tmp173		; <i32> [#uses=1]
+	%tmp173 = getelementptr %struct.attr_desc, %struct.attr_desc* null, i32 0, i32 4		; <i32*> [#uses=2]
+	%tmp174 = load i32, i32* %tmp173		; <i32> [#uses=1]
 	%tmp177 = and i32 %tmp174, -9		; <i32> [#uses=1]
 	store i32 %tmp177, i32* %tmp173
-	%tmp180 = getelementptr %struct.attr_desc* null, i32 0, i32 4		; <i32*> [#uses=1]
-	%tmp181 = load i32* %tmp180		; <i32> [#uses=1]
-	%tmp185 = getelementptr %struct.attr_desc* null, i32 0, i32 4		; <i32*> [#uses=2]
-	%tmp186 = load i32* %tmp185		; <i32> [#uses=1]
+	%tmp180 = getelementptr %struct.attr_desc, %struct.attr_desc* null, i32 0, i32 4		; <i32*> [#uses=1]
+	%tmp181 = load i32, i32* %tmp180		; <i32> [#uses=1]
+	%tmp185 = getelementptr %struct.attr_desc, %struct.attr_desc* null, i32 0, i32 4		; <i32*> [#uses=2]
+	%tmp186 = load i32, i32* %tmp185		; <i32> [#uses=1]
 	%tmp183187 = shl i32 %tmp181, 1		; <i32> [#uses=1]
 	%tmp188 = and i32 %tmp183187, 16		; <i32> [#uses=1]
 	%tmp190 = and i32 %tmp186, -17		; <i32> [#uses=1]
 	%tmp191 = or i32 %tmp190, %tmp188		; <i32> [#uses=1]
 	store i32 %tmp191, i32* %tmp185
-	%tmp193 = getelementptr %struct.attr_desc* null, i32 0, i32 4		; <i32*> [#uses=1]
-	%tmp194 = load i32* %tmp193		; <i32> [#uses=1]
-	%tmp198 = getelementptr %struct.attr_desc* null, i32 0, i32 4		; <i32*> [#uses=2]
-	%tmp199 = load i32* %tmp198		; <i32> [#uses=1]
+	%tmp193 = getelementptr %struct.attr_desc, %struct.attr_desc* null, i32 0, i32 4		; <i32*> [#uses=1]
+	%tmp194 = load i32, i32* %tmp193		; <i32> [#uses=1]
+	%tmp198 = getelementptr %struct.attr_desc, %struct.attr_desc* null, i32 0, i32 4		; <i32*> [#uses=2]
+	%tmp199 = load i32, i32* %tmp198		; <i32> [#uses=1]
 	%tmp196200 = shl i32 %tmp194, 2		; <i32> [#uses=1]
 	%tmp201 = and i32 %tmp196200, 64		; <i32> [#uses=1]
 	%tmp203 = and i32 %tmp199, -65		; <i32> [#uses=1]
 	%tmp204 = or i32 %tmp203, %tmp201		; <i32> [#uses=1]
 	store i32 %tmp204, i32* %tmp198
-	%tmp206 = getelementptr %struct.attr_desc* null, i32 0, i32 4		; <i32*> [#uses=1]
-	%tmp207 = load i32* %tmp206		; <i32> [#uses=1]
-	%tmp211 = getelementptr %struct.attr_desc* null, i32 0, i32 4		; <i32*> [#uses=2]
-	%tmp212 = load i32* %tmp211		; <i32> [#uses=1]
+	%tmp206 = getelementptr %struct.attr_desc, %struct.attr_desc* null, i32 0, i32 4		; <i32*> [#uses=1]
+	%tmp207 = load i32, i32* %tmp206		; <i32> [#uses=1]
+	%tmp211 = getelementptr %struct.attr_desc, %struct.attr_desc* null, i32 0, i32 4		; <i32*> [#uses=2]
+	%tmp212 = load i32, i32* %tmp211		; <i32> [#uses=1]
 	%tmp209213 = shl i32 %tmp207, 1		; <i32> [#uses=1]
 	%tmp214 = and i32 %tmp209213, 128		; <i32> [#uses=1]
 	%tmp216 = and i32 %tmp212, -129		; <i32> [#uses=1]
diff --git a/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
index 1b8b064ee914..792c271d0c08 100644
--- a/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
+++ b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
@@ -4,14 +4,14 @@
 @vals = external global i32*            ; <i32**> [#uses=1]
 
 define i32 @test(i32 %i) {
-        %tmp = load i8** @lens          ; <i8*> [#uses=1]
-        %tmp1 = getelementptr i8* %tmp, i32 %i          ; <i8*> [#uses=1]
-        %tmp.upgrd.1 = load i8* %tmp1           ; <i8> [#uses=1]
+        %tmp = load i8*, i8** @lens          ; <i8*> [#uses=1]
+        %tmp1 = getelementptr i8, i8* %tmp, i32 %i          ; <i8*> [#uses=1]
+        %tmp.upgrd.1 = load i8, i8* %tmp1           ; <i8> [#uses=1]
         %tmp2 = zext i8 %tmp.upgrd.1 to i32             ; <i32> [#uses=1]
-        %tmp3 = load i32** @vals                ; <i32*> [#uses=1]
+        %tmp3 = load i32*, i32** @vals                ; <i32*> [#uses=1]
         %tmp5 = sub i32 1, %tmp2                ; <i32> [#uses=1]
-        %tmp6 = getelementptr i32* %tmp3, i32 %tmp5             ; <i32*> [#uses=1]
-        %tmp7 = load i32* %tmp6         ; <i32> [#uses=1]
+        %tmp6 = getelementptr i32, i32* %tmp3, i32 %tmp5             ; <i32*> [#uses=1]
+        %tmp7 = load i32, i32* %tmp6         ; <i32> [#uses=1]
         ret i32 %tmp7
 }
 
diff --git a/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll b/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll
index 65dd568b1ee3..4b287641d55f 100644
--- a/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll
+++ b/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=ppc32
 
 define void @img2buf(i32 %symbol_size_in_bytes, i16* %ui16) nounwind {
-        %tmp93 = load i16* null         ; <i16> [#uses=1]
+        %tmp93 = load i16, i16* null         ; <i16> [#uses=1]
         %tmp99 = call i16 @llvm.bswap.i16( i16 %tmp93 )         ; <i16> [#uses=1]
         store i16 %tmp99, i16* %ui16
         ret void
diff --git a/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll b/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll
index cb76b5c70cf0..c63fd9ae1700 100644
--- a/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll
+++ b/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll
@@ -5,7 +5,7 @@
 
 define fastcc void @immed_double_const(i32 %i0, i32 %i1) {
 entry:
-	%tmp1 = load i32* null		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* null		; <i32> [#uses=1]
 	switch i32 %tmp1, label %bb103 [
 		 i32 1, label %bb
 		 i32 3, label %bb
diff --git a/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll b/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll
index 002a0644183a..5992ad4481d3 100644
--- a/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll
+++ b/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll
@@ -6,7 +6,7 @@ entry:
         %tmp = icmp sgt i64 %tmp1, 2            ; <i1> [#uses=1]
         br i1 %tmp, label %UnifiedReturnBlock, label %cond_true
 cond_true:              ; preds = %entry
-        %tmp.upgrd.1 = tail call i32 (...)* @bar( )             ; <i32> [#uses=0]
+        %tmp.upgrd.1 = tail call i32 (...) @bar( )             ; <i32> [#uses=0]
         ret void
 UnifiedReturnBlock:             ; preds = %entry
         ret void
diff --git a/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll b/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll
index 3d462b4d1461..ab5f37d4babe 100644
--- a/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll
+++ b/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll
@@ -10,7 +10,7 @@ entry:
         %tmp = icmp eq i32 %tmp2, 0             ; <i1> [#uses=1]
         br i1 %tmp, label %UnifiedReturnBlock, label %cond_true
 cond_true:              ; preds = %entry
-        tail call i32 (...)* @bar( )            ; <i32>:0 [#uses=0]
+        tail call i32 (...) @bar( )            ; <i32>:0 [#uses=0]
         ret void
 UnifiedReturnBlock:             ; preds = %entry
         ret void
diff --git a/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll
index ba863047be99..0e7709857406 100644
--- a/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll
+++ b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll
@@ -14,7 +14,7 @@ bb19:           ; preds = %entry
 bb12.i:         ; preds = %bb12.i, %bb19
         %i.0.i = phi i32 [ %tmp11.i, %bb12.i ], [ 0, %bb19 ]            ; <i32> [#uses=2]
         %gep.upgrd.1 = zext i32 %i.0.i to i64           ; <i64> [#uses=1]
-        %tmp9.i = getelementptr [256 x i32]* %RMask.i, i32 0, i64 %gep.upgrd.1          ; <i32*> [#uses=1]
+        %tmp9.i = getelementptr [256 x i32], [256 x i32]* %RMask.i, i32 0, i64 %gep.upgrd.1          ; <i32*> [#uses=1]
         store i32 0, i32* %tmp9.i
         %tmp11.i = add i32 %i.0.i, 1            ; <i32> [#uses=1]
         br label %bb12.i
diff --git a/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll b/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll
index 6d9a3fa7b106..9660d450cb4c 100644
--- a/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll
+++ b/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll
@@ -10,7 +10,7 @@ entry:
 cond_true:              ; preds = %entry
         ret void
 cond_next71:            ; preds = %entry
-        %tmp73.b = load i1* @qsz.b              ; <i1> [#uses=1]
+        %tmp73.b = load i1, i1* @qsz.b              ; <i1> [#uses=1]
         %ii.4.ph = select i1 %tmp73.b, i64 4, i64 0             ; <i64> [#uses=1]
         br label %bb139
 bb82:           ; preds = %bb139
diff --git a/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll b/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll
index c7792884bb89..ca134fa9be4c 100644
--- a/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll
+++ b/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
-; RUN:    grep cntlzw
+; RUN:    grep cntlz
 
 define i32 @foo() nounwind {
 entry:
@@ -8,19 +8,19 @@ entry:
 	%ctz_x = alloca i32, align 4		; <i32*> [#uses=3]
 	%ctz_c = alloca i32, align 4		; <i32*> [#uses=2]
 	store i32 61440, i32* %ctz_x
-	%tmp = load i32* %ctz_x		; <i32> [#uses=1]
+	%tmp = load i32, i32* %ctz_x		; <i32> [#uses=1]
 	%tmp1 = sub i32 0, %tmp		; <i32> [#uses=1]
-	%tmp2 = load i32* %ctz_x		; <i32> [#uses=1]
+	%tmp2 = load i32, i32* %ctz_x		; <i32> [#uses=1]
 	%tmp3 = and i32 %tmp1, %tmp2		; <i32> [#uses=1]
 	%tmp4 = call i32 asm "$(cntlz$|cntlzw$) $0,$1", "=r,r,~{dirflag},~{fpsr},~{flags}"( i32 %tmp3 )		; <i32> [#uses=1]
 	store i32 %tmp4, i32* %ctz_c
-	%tmp5 = load i32* %ctz_c		; <i32> [#uses=1]
+	%tmp5 = load i32, i32* %ctz_c		; <i32> [#uses=1]
 	store i32 %tmp5, i32* %temp
-	%tmp6 = load i32* %temp		; <i32> [#uses=1]
+	%tmp6 = load i32, i32* %temp		; <i32> [#uses=1]
 	store i32 %tmp6, i32* %retval
 	br label %return
 
 return:		; preds = %entry
-	%retval2 = load i32* %retval		; <i32> [#uses=1]
+	%retval2 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval2
 }
diff --git a/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll b/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
index fe5145d15230..6ce32da2f740 100644
--- a/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
+++ b/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
@@ -10,7 +10,7 @@
 define void @test1() {
 entry:
 	%Out = alloca %struct.A, align 4		; <%struct.A*> [#uses=1]
-	%tmp2 = getelementptr %struct.A* %Out, i32 0, i32 1
+	%tmp2 = getelementptr %struct.A, %struct.A* %Out, i32 0, i32 1
 	%tmp5 = call i32 asm "lwbrx $0, $1", "=r,m"(i32* %tmp2 )
 	ret void
 }
@@ -18,7 +18,7 @@ entry:
 define void @test2() {
 entry:
 	%Out = alloca %struct.A, align 4		; <%struct.A*> [#uses=1]
-	%tmp2 = getelementptr %struct.A* %Out, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp2 = getelementptr %struct.A, %struct.A* %Out, i32 0, i32 0		; <i32*> [#uses=1]
 	%tmp5 = call i32 asm "lwbrx $0, $2, $1", "=r,r,bO,m"( i8* null, i32 0, i32* %tmp2 )		; <i32> [#uses=0]
 	ret void
 }
diff --git a/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll b/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll
index 0473857ae70f..5a6fbf01c1b8 100644
--- a/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll
+++ b/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll
@@ -7,7 +7,7 @@ target triple = "powerpc-apple-darwin8"
 
 define i32 @main() {
 entry:
-        %tmp = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([18 x i8]* @str, i32 0, i32 0) )                ; <i32> [#uses=0]
+        %tmp = tail call i32 (i8*, ...) @printf( i8* getelementptr ([18 x i8], [18 x i8]* @str, i32 0, i32 0) )                ; <i32> [#uses=0]
         ret i32 0
 }
 
diff --git a/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll b/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll
index 3624b5109301..2db87fcb1c88 100644
--- a/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll
+++ b/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll
@@ -3,7 +3,7 @@ target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define i32 @_ZNK4llvm5APInt17countLeadingZerosEv(i64 *%t) nounwind {
-        %tmp19 = load i64* %t
+        %tmp19 = load i64, i64* %t
         %tmp22 = tail call i64 @llvm.ctlz.i64( i64 %tmp19, i1 true )             ; <i64> [#uses=1]
         %tmp23 = trunc i64 %tmp22 to i32
         %tmp89 = add i32 %tmp23, -64          ; <i32> [#uses=1]
diff --git a/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll b/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll
index d43916d4f3c1..de445f4c034a 100644
--- a/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll
+++ b/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll
@@ -2,578 +2,578 @@
 
 define void @test(<4 x float>*, { { i16, i16, i32 } }*) {
 xOperationInitMasks.exit:
-	%.sub7896 = getelementptr [4 x <4 x i32>]* null, i32 0, i32 0		; <<4 x i32>*> [#uses=24]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 175, i32 3		; <<4 x float>*>:2 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 174, i32 2		; <<4 x float>*>:3 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 174, i32 3		; <<4 x float>*>:4 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 173, i32 1		; <<4 x float>*>:5 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 173, i32 2		; <<4 x float>*>:6 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 173, i32 3		; <<4 x float>*>:7 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 172, i32 1		; <<4 x float>*>:8 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 172, i32 2		; <<4 x float>*>:9 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 172, i32 3		; <<4 x float>*>:10 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 171, i32 1		; <<4 x float>*>:11 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 171, i32 2		; <<4 x float>*>:12 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 171, i32 3		; <<4 x float>*>:13 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 170, i32 1		; <<4 x float>*>:14 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 170, i32 2		; <<4 x float>*>:15 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 170, i32 3		; <<4 x float>*>:16 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 169, i32 1		; <<4 x float>*>:17 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 169, i32 2		; <<4 x float>*>:18 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 169, i32 3		; <<4 x float>*>:19 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 168, i32 1		; <<4 x float>*>:20 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 168, i32 2		; <<4 x float>*>:21 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 168, i32 3		; <<4 x float>*>:22 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 167, i32 1		; <<4 x float>*>:23 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 167, i32 2		; <<4 x float>*>:24 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 167, i32 3		; <<4 x float>*>:25 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 166, i32 1		; <<4 x float>*>:26 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 166, i32 2		; <<4 x float>*>:27 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 166, i32 3		; <<4 x float>*>:28 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 165, i32 1		; <<4 x float>*>:29 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 165, i32 2		; <<4 x float>*>:30 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 165, i32 3		; <<4 x float>*>:31 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 164, i32 1		; <<4 x float>*>:32 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 164, i32 2		; <<4 x float>*>:33 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 164, i32 3		; <<4 x float>*>:34 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 163, i32 1		; <<4 x float>*>:35 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 163, i32 2		; <<4 x float>*>:36 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 163, i32 3		; <<4 x float>*>:37 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 162, i32 1		; <<4 x float>*>:38 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 162, i32 2		; <<4 x float>*>:39 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 162, i32 3		; <<4 x float>*>:40 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 161, i32 1		; <<4 x float>*>:41 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 161, i32 2		; <<4 x float>*>:42 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 161, i32 3		; <<4 x float>*>:43 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 160, i32 1		; <<4 x float>*>:44 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 160, i32 2		; <<4 x float>*>:45 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 160, i32 3		; <<4 x float>*>:46 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 159, i32 1		; <<4 x float>*>:47 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 159, i32 2		; <<4 x float>*>:48 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 159, i32 3		; <<4 x float>*>:49 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 158, i32 1		; <<4 x float>*>:50 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 158, i32 2		; <<4 x float>*>:51 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 158, i32 3		; <<4 x float>*>:52 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 157, i32 1		; <<4 x float>*>:53 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 157, i32 2		; <<4 x float>*>:54 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 157, i32 3		; <<4 x float>*>:55 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 156, i32 1		; <<4 x float>*>:56 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 156, i32 2		; <<4 x float>*>:57 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 156, i32 3		; <<4 x float>*>:58 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 155, i32 1		; <<4 x float>*>:59 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 155, i32 2		; <<4 x float>*>:60 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 155, i32 3		; <<4 x float>*>:61 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 154, i32 1		; <<4 x float>*>:62 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 154, i32 2		; <<4 x float>*>:63 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 154, i32 3		; <<4 x float>*>:64 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 153, i32 1		; <<4 x float>*>:65 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 153, i32 2		; <<4 x float>*>:66 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 153, i32 3		; <<4 x float>*>:67 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 152, i32 1		; <<4 x float>*>:68 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 152, i32 2		; <<4 x float>*>:69 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 152, i32 3		; <<4 x float>*>:70 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 151, i32 1		; <<4 x float>*>:71 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 151, i32 2		; <<4 x float>*>:72 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 151, i32 3		; <<4 x float>*>:73 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 150, i32 1		; <<4 x float>*>:74 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 150, i32 2		; <<4 x float>*>:75 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 150, i32 3		; <<4 x float>*>:76 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 149, i32 1		; <<4 x float>*>:77 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 149, i32 2		; <<4 x float>*>:78 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 149, i32 3		; <<4 x float>*>:79 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 148, i32 1		; <<4 x float>*>:80 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 148, i32 2		; <<4 x float>*>:81 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 148, i32 3		; <<4 x float>*>:82 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 147, i32 1		; <<4 x float>*>:83 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 147, i32 2		; <<4 x float>*>:84 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 147, i32 3		; <<4 x float>*>:85 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 146, i32 1		; <<4 x float>*>:86 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 146, i32 2		; <<4 x float>*>:87 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 146, i32 3		; <<4 x float>*>:88 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 145, i32 1		; <<4 x float>*>:89 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 145, i32 2		; <<4 x float>*>:90 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 145, i32 3		; <<4 x float>*>:91 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 144, i32 1		; <<4 x float>*>:92 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 144, i32 2		; <<4 x float>*>:93 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 144, i32 3		; <<4 x float>*>:94 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 143, i32 1		; <<4 x float>*>:95 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 143, i32 2		; <<4 x float>*>:96 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 143, i32 3		; <<4 x float>*>:97 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 142, i32 1		; <<4 x float>*>:98 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 142, i32 2		; <<4 x float>*>:99 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 142, i32 3		; <<4 x float>*>:100 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 141, i32 1		; <<4 x float>*>:101 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 141, i32 2		; <<4 x float>*>:102 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 141, i32 3		; <<4 x float>*>:103 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 140, i32 1		; <<4 x float>*>:104 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 140, i32 2		; <<4 x float>*>:105 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 140, i32 3		; <<4 x float>*>:106 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 139, i32 1		; <<4 x float>*>:107 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 139, i32 2		; <<4 x float>*>:108 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 139, i32 3		; <<4 x float>*>:109 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 138, i32 1		; <<4 x float>*>:110 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 138, i32 2		; <<4 x float>*>:111 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 138, i32 3		; <<4 x float>*>:112 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 137, i32 1		; <<4 x float>*>:113 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 137, i32 2		; <<4 x float>*>:114 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 137, i32 3		; <<4 x float>*>:115 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 136, i32 1		; <<4 x float>*>:116 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 136, i32 2		; <<4 x float>*>:117 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 136, i32 3		; <<4 x float>*>:118 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 135, i32 1		; <<4 x float>*>:119 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 135, i32 2		; <<4 x float>*>:120 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 135, i32 3		; <<4 x float>*>:121 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 134, i32 1		; <<4 x float>*>:122 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 134, i32 2		; <<4 x float>*>:123 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 134, i32 3		; <<4 x float>*>:124 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 133, i32 1		; <<4 x float>*>:125 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 133, i32 2		; <<4 x float>*>:126 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 133, i32 3		; <<4 x float>*>:127 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 132, i32 1		; <<4 x float>*>:128 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 132, i32 2		; <<4 x float>*>:129 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 132, i32 3		; <<4 x float>*>:130 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 131, i32 1		; <<4 x float>*>:131 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 131, i32 2		; <<4 x float>*>:132 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 131, i32 3		; <<4 x float>*>:133 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 130, i32 1		; <<4 x float>*>:134 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 130, i32 2		; <<4 x float>*>:135 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 130, i32 3		; <<4 x float>*>:136 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 129, i32 1		; <<4 x float>*>:137 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 129, i32 2		; <<4 x float>*>:138 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 129, i32 3		; <<4 x float>*>:139 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 128, i32 1		; <<4 x float>*>:140 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 128, i32 2		; <<4 x float>*>:141 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 128, i32 3		; <<4 x float>*>:142 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 127, i32 1		; <<4 x float>*>:143 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 127, i32 2		; <<4 x float>*>:144 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 127, i32 3		; <<4 x float>*>:145 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 126, i32 1		; <<4 x float>*>:146 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 126, i32 2		; <<4 x float>*>:147 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 126, i32 3		; <<4 x float>*>:148 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 125, i32 1		; <<4 x float>*>:149 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 125, i32 2		; <<4 x float>*>:150 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 125, i32 3		; <<4 x float>*>:151 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 124, i32 1		; <<4 x float>*>:152 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 124, i32 2		; <<4 x float>*>:153 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 124, i32 3		; <<4 x float>*>:154 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 123, i32 1		; <<4 x float>*>:155 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 123, i32 2		; <<4 x float>*>:156 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 123, i32 3		; <<4 x float>*>:157 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 122, i32 1		; <<4 x float>*>:158 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 122, i32 2		; <<4 x float>*>:159 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 122, i32 3		; <<4 x float>*>:160 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 121, i32 1		; <<4 x float>*>:161 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 121, i32 2		; <<4 x float>*>:162 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 121, i32 3		; <<4 x float>*>:163 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 120, i32 1		; <<4 x float>*>:164 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 120, i32 2		; <<4 x float>*>:165 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 120, i32 3		; <<4 x float>*>:166 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 119, i32 1		; <<4 x float>*>:167 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 119, i32 2		; <<4 x float>*>:168 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 119, i32 3		; <<4 x float>*>:169 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 118, i32 1		; <<4 x float>*>:170 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 118, i32 2		; <<4 x float>*>:171 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 118, i32 3		; <<4 x float>*>:172 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 117, i32 1		; <<4 x float>*>:173 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 117, i32 2		; <<4 x float>*>:174 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 117, i32 3		; <<4 x float>*>:175 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 116, i32 1		; <<4 x float>*>:176 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 116, i32 2		; <<4 x float>*>:177 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 116, i32 3		; <<4 x float>*>:178 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 115, i32 1		; <<4 x float>*>:179 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 115, i32 2		; <<4 x float>*>:180 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 115, i32 3		; <<4 x float>*>:181 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 114, i32 1		; <<4 x float>*>:182 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 114, i32 2		; <<4 x float>*>:183 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 114, i32 3		; <<4 x float>*>:184 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 113, i32 1		; <<4 x float>*>:185 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 113, i32 2		; <<4 x float>*>:186 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 113, i32 3		; <<4 x float>*>:187 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 112, i32 1		; <<4 x float>*>:188 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 112, i32 2		; <<4 x float>*>:189 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 112, i32 3		; <<4 x float>*>:190 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 111, i32 1		; <<4 x float>*>:191 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 111, i32 2		; <<4 x float>*>:192 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 111, i32 3		; <<4 x float>*>:193 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 110, i32 1		; <<4 x float>*>:194 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 110, i32 2		; <<4 x float>*>:195 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 110, i32 3		; <<4 x float>*>:196 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 109, i32 1		; <<4 x float>*>:197 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 109, i32 2		; <<4 x float>*>:198 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 109, i32 3		; <<4 x float>*>:199 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 108, i32 1		; <<4 x float>*>:200 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 108, i32 2		; <<4 x float>*>:201 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 108, i32 3		; <<4 x float>*>:202 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 107, i32 1		; <<4 x float>*>:203 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 107, i32 2		; <<4 x float>*>:204 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 107, i32 3		; <<4 x float>*>:205 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 106, i32 1		; <<4 x float>*>:206 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 106, i32 2		; <<4 x float>*>:207 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 106, i32 3		; <<4 x float>*>:208 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 105, i32 1		; <<4 x float>*>:209 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 105, i32 2		; <<4 x float>*>:210 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 105, i32 3		; <<4 x float>*>:211 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 104, i32 1		; <<4 x float>*>:212 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 104, i32 2		; <<4 x float>*>:213 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 104, i32 3		; <<4 x float>*>:214 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 103, i32 1		; <<4 x float>*>:215 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 103, i32 2		; <<4 x float>*>:216 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 103, i32 3		; <<4 x float>*>:217 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 102, i32 1		; <<4 x float>*>:218 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 102, i32 2		; <<4 x float>*>:219 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 102, i32 3		; <<4 x float>*>:220 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 101, i32 1		; <<4 x float>*>:221 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 101, i32 2		; <<4 x float>*>:222 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 101, i32 3		; <<4 x float>*>:223 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 100, i32 1		; <<4 x float>*>:224 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 100, i32 2		; <<4 x float>*>:225 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 100, i32 3		; <<4 x float>*>:226 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 99, i32 1		; <<4 x float>*>:227 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 99, i32 2		; <<4 x float>*>:228 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 99, i32 3		; <<4 x float>*>:229 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 98, i32 1		; <<4 x float>*>:230 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 98, i32 2		; <<4 x float>*>:231 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 98, i32 3		; <<4 x float>*>:232 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 97, i32 1		; <<4 x float>*>:233 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 97, i32 2		; <<4 x float>*>:234 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 97, i32 3		; <<4 x float>*>:235 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 96, i32 1		; <<4 x float>*>:236 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 96, i32 2		; <<4 x float>*>:237 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 96, i32 3		; <<4 x float>*>:238 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 95, i32 1		; <<4 x float>*>:239 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 95, i32 2		; <<4 x float>*>:240 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 95, i32 3		; <<4 x float>*>:241 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 94, i32 1		; <<4 x float>*>:242 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 94, i32 2		; <<4 x float>*>:243 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 94, i32 3		; <<4 x float>*>:244 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 93, i32 1		; <<4 x float>*>:245 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 93, i32 2		; <<4 x float>*>:246 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 93, i32 3		; <<4 x float>*>:247 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 92, i32 1		; <<4 x float>*>:248 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 92, i32 2		; <<4 x float>*>:249 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 92, i32 3		; <<4 x float>*>:250 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 91, i32 1		; <<4 x float>*>:251 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 91, i32 2		; <<4 x float>*>:252 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 91, i32 3		; <<4 x float>*>:253 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 90, i32 1		; <<4 x float>*>:254 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 90, i32 2		; <<4 x float>*>:255 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 90, i32 3		; <<4 x float>*>:256 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 89, i32 1		; <<4 x float>*>:257 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 89, i32 2		; <<4 x float>*>:258 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 89, i32 3		; <<4 x float>*>:259 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 88, i32 1		; <<4 x float>*>:260 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 88, i32 2		; <<4 x float>*>:261 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 88, i32 3		; <<4 x float>*>:262 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 87, i32 1		; <<4 x float>*>:263 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 87, i32 2		; <<4 x float>*>:264 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 87, i32 3		; <<4 x float>*>:265 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 86, i32 1		; <<4 x float>*>:266 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 86, i32 2		; <<4 x float>*>:267 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 86, i32 3		; <<4 x float>*>:268 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 85, i32 1		; <<4 x float>*>:269 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 85, i32 2		; <<4 x float>*>:270 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 85, i32 3		; <<4 x float>*>:271 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 84, i32 1		; <<4 x float>*>:272 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 84, i32 2		; <<4 x float>*>:273 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 84, i32 3		; <<4 x float>*>:274 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 83, i32 1		; <<4 x float>*>:275 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 83, i32 2		; <<4 x float>*>:276 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 83, i32 3		; <<4 x float>*>:277 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 82, i32 1		; <<4 x float>*>:278 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 82, i32 2		; <<4 x float>*>:279 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 82, i32 3		; <<4 x float>*>:280 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 81, i32 1		; <<4 x float>*>:281 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 81, i32 2		; <<4 x float>*>:282 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 81, i32 3		; <<4 x float>*>:283 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 80, i32 1		; <<4 x float>*>:284 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 80, i32 2		; <<4 x float>*>:285 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 80, i32 3		; <<4 x float>*>:286 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 79, i32 1		; <<4 x float>*>:287 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 79, i32 2		; <<4 x float>*>:288 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 79, i32 3		; <<4 x float>*>:289 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 78, i32 1		; <<4 x float>*>:290 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 78, i32 2		; <<4 x float>*>:291 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 78, i32 3		; <<4 x float>*>:292 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 77, i32 1		; <<4 x float>*>:293 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 77, i32 2		; <<4 x float>*>:294 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 77, i32 3		; <<4 x float>*>:295 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 76, i32 1		; <<4 x float>*>:296 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 76, i32 2		; <<4 x float>*>:297 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 76, i32 3		; <<4 x float>*>:298 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 75, i32 1		; <<4 x float>*>:299 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 75, i32 2		; <<4 x float>*>:300 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 75, i32 3		; <<4 x float>*>:301 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 74, i32 1		; <<4 x float>*>:302 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 74, i32 2		; <<4 x float>*>:303 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 74, i32 3		; <<4 x float>*>:304 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 73, i32 1		; <<4 x float>*>:305 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 73, i32 2		; <<4 x float>*>:306 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 73, i32 3		; <<4 x float>*>:307 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 72, i32 1		; <<4 x float>*>:308 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 72, i32 2		; <<4 x float>*>:309 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 72, i32 3		; <<4 x float>*>:310 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 71, i32 1		; <<4 x float>*>:311 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 71, i32 2		; <<4 x float>*>:312 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 71, i32 3		; <<4 x float>*>:313 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 70, i32 1		; <<4 x float>*>:314 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 70, i32 2		; <<4 x float>*>:315 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 70, i32 3		; <<4 x float>*>:316 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 69, i32 1		; <<4 x float>*>:317 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 69, i32 2		; <<4 x float>*>:318 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 69, i32 3		; <<4 x float>*>:319 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 68, i32 1		; <<4 x float>*>:320 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 68, i32 2		; <<4 x float>*>:321 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 68, i32 3		; <<4 x float>*>:322 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 67, i32 1		; <<4 x float>*>:323 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 67, i32 2		; <<4 x float>*>:324 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 67, i32 3		; <<4 x float>*>:325 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 66, i32 1		; <<4 x float>*>:326 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 66, i32 2		; <<4 x float>*>:327 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 66, i32 3		; <<4 x float>*>:328 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 65, i32 1		; <<4 x float>*>:329 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 65, i32 2		; <<4 x float>*>:330 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 65, i32 3		; <<4 x float>*>:331 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 64, i32 1		; <<4 x float>*>:332 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 64, i32 2		; <<4 x float>*>:333 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 64, i32 3		; <<4 x float>*>:334 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 63, i32 1		; <<4 x float>*>:335 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 63, i32 2		; <<4 x float>*>:336 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 63, i32 3		; <<4 x float>*>:337 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 62, i32 1		; <<4 x float>*>:338 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 62, i32 2		; <<4 x float>*>:339 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 62, i32 3		; <<4 x float>*>:340 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 61, i32 1		; <<4 x float>*>:341 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 61, i32 2		; <<4 x float>*>:342 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 61, i32 3		; <<4 x float>*>:343 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 60, i32 1		; <<4 x float>*>:344 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 60, i32 2		; <<4 x float>*>:345 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 60, i32 3		; <<4 x float>*>:346 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 59, i32 1		; <<4 x float>*>:347 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 59, i32 2		; <<4 x float>*>:348 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 59, i32 3		; <<4 x float>*>:349 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 58, i32 1		; <<4 x float>*>:350 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 58, i32 2		; <<4 x float>*>:351 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 58, i32 3		; <<4 x float>*>:352 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 57, i32 1		; <<4 x float>*>:353 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 57, i32 2		; <<4 x float>*>:354 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 57, i32 3		; <<4 x float>*>:355 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 56, i32 1		; <<4 x float>*>:356 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 56, i32 2		; <<4 x float>*>:357 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 56, i32 3		; <<4 x float>*>:358 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 55, i32 1		; <<4 x float>*>:359 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 55, i32 2		; <<4 x float>*>:360 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 55, i32 3		; <<4 x float>*>:361 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 54, i32 1		; <<4 x float>*>:362 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 54, i32 2		; <<4 x float>*>:363 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 54, i32 3		; <<4 x float>*>:364 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 53, i32 1		; <<4 x float>*>:365 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 53, i32 2		; <<4 x float>*>:366 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 53, i32 3		; <<4 x float>*>:367 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 52, i32 1		; <<4 x float>*>:368 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 52, i32 2		; <<4 x float>*>:369 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 52, i32 3		; <<4 x float>*>:370 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 51, i32 1		; <<4 x float>*>:371 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 51, i32 2		; <<4 x float>*>:372 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 51, i32 3		; <<4 x float>*>:373 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 50, i32 1		; <<4 x float>*>:374 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 50, i32 2		; <<4 x float>*>:375 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 50, i32 3		; <<4 x float>*>:376 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 49, i32 1		; <<4 x float>*>:377 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 49, i32 2		; <<4 x float>*>:378 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 49, i32 3		; <<4 x float>*>:379 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 48, i32 1		; <<4 x float>*>:380 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 48, i32 2		; <<4 x float>*>:381 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 48, i32 3		; <<4 x float>*>:382 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 47, i32 1		; <<4 x float>*>:383 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 47, i32 2		; <<4 x float>*>:384 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 47, i32 3		; <<4 x float>*>:385 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 46, i32 1		; <<4 x float>*>:386 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 46, i32 2		; <<4 x float>*>:387 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 46, i32 3		; <<4 x float>*>:388 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 45, i32 1		; <<4 x float>*>:389 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 45, i32 2		; <<4 x float>*>:390 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 45, i32 3		; <<4 x float>*>:391 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 44, i32 1		; <<4 x float>*>:392 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 44, i32 2		; <<4 x float>*>:393 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 44, i32 3		; <<4 x float>*>:394 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 43, i32 1		; <<4 x float>*>:395 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 43, i32 2		; <<4 x float>*>:396 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 43, i32 3		; <<4 x float>*>:397 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 42, i32 1		; <<4 x float>*>:398 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 42, i32 2		; <<4 x float>*>:399 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 42, i32 3		; <<4 x float>*>:400 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 41, i32 1		; <<4 x float>*>:401 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 41, i32 2		; <<4 x float>*>:402 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 41, i32 3		; <<4 x float>*>:403 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 40, i32 1		; <<4 x float>*>:404 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 40, i32 2		; <<4 x float>*>:405 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 40, i32 3		; <<4 x float>*>:406 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 39, i32 1		; <<4 x float>*>:407 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 39, i32 2		; <<4 x float>*>:408 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 39, i32 3		; <<4 x float>*>:409 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 38, i32 1		; <<4 x float>*>:410 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 38, i32 2		; <<4 x float>*>:411 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 38, i32 3		; <<4 x float>*>:412 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 37, i32 1		; <<4 x float>*>:413 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 37, i32 2		; <<4 x float>*>:414 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 37, i32 3		; <<4 x float>*>:415 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 36, i32 1		; <<4 x float>*>:416 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 36, i32 2		; <<4 x float>*>:417 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 36, i32 3		; <<4 x float>*>:418 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 35, i32 1		; <<4 x float>*>:419 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 35, i32 2		; <<4 x float>*>:420 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 35, i32 3		; <<4 x float>*>:421 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 34, i32 1		; <<4 x float>*>:422 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 34, i32 2		; <<4 x float>*>:423 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 34, i32 3		; <<4 x float>*>:424 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 33, i32 1		; <<4 x float>*>:425 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 33, i32 2		; <<4 x float>*>:426 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 33, i32 3		; <<4 x float>*>:427 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 32, i32 1		; <<4 x float>*>:428 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 32, i32 2		; <<4 x float>*>:429 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 32, i32 3		; <<4 x float>*>:430 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 31, i32 1		; <<4 x float>*>:431 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 31, i32 2		; <<4 x float>*>:432 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 31, i32 3		; <<4 x float>*>:433 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 30, i32 1		; <<4 x float>*>:434 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 30, i32 2		; <<4 x float>*>:435 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 30, i32 3		; <<4 x float>*>:436 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 29, i32 1		; <<4 x float>*>:437 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 29, i32 2		; <<4 x float>*>:438 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 29, i32 3		; <<4 x float>*>:439 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 28, i32 1		; <<4 x float>*>:440 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 28, i32 2		; <<4 x float>*>:441 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 28, i32 3		; <<4 x float>*>:442 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 27, i32 1		; <<4 x float>*>:443 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 27, i32 2		; <<4 x float>*>:444 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 27, i32 3		; <<4 x float>*>:445 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 26, i32 1		; <<4 x float>*>:446 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 26, i32 2		; <<4 x float>*>:447 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 26, i32 3		; <<4 x float>*>:448 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 25, i32 1		; <<4 x float>*>:449 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 25, i32 2		; <<4 x float>*>:450 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 25, i32 3		; <<4 x float>*>:451 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 24, i32 1		; <<4 x float>*>:452 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 24, i32 2		; <<4 x float>*>:453 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 24, i32 3		; <<4 x float>*>:454 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 23, i32 1		; <<4 x float>*>:455 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 23, i32 2		; <<4 x float>*>:456 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 23, i32 3		; <<4 x float>*>:457 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 22, i32 1		; <<4 x float>*>:458 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 22, i32 2		; <<4 x float>*>:459 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 22, i32 3		; <<4 x float>*>:460 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 21, i32 1		; <<4 x float>*>:461 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 21, i32 2		; <<4 x float>*>:462 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 21, i32 3		; <<4 x float>*>:463 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 20, i32 1		; <<4 x float>*>:464 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 20, i32 2		; <<4 x float>*>:465 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 20, i32 3		; <<4 x float>*>:466 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 19, i32 1		; <<4 x float>*>:467 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 19, i32 2		; <<4 x float>*>:468 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 19, i32 3		; <<4 x float>*>:469 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 18, i32 1		; <<4 x float>*>:470 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 18, i32 2		; <<4 x float>*>:471 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 18, i32 3		; <<4 x float>*>:472 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 17, i32 1		; <<4 x float>*>:473 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 17, i32 2		; <<4 x float>*>:474 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 17, i32 3		; <<4 x float>*>:475 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 16, i32 1		; <<4 x float>*>:476 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 16, i32 2		; <<4 x float>*>:477 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 16, i32 3		; <<4 x float>*>:478 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 15, i32 1		; <<4 x float>*>:479 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 15, i32 2		; <<4 x float>*>:480 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 15, i32 3		; <<4 x float>*>:481 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 14, i32 1		; <<4 x float>*>:482 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 14, i32 2		; <<4 x float>*>:483 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 14, i32 3		; <<4 x float>*>:484 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1		; <<4 x float>*>:485 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:486 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:487 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 1		; <<4 x float>*>:488 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 2		; <<4 x float>*>:489 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 3		; <<4 x float>*>:490 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 180, i32 1		; <<4 x float>*>:491 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 180, i32 2		; <<4 x float>*>:492 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 180, i32 3		; <<4 x float>*>:493 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 181, i32 1		; <<4 x float>*>:494 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 181, i32 2		; <<4 x float>*>:495 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 181, i32 3		; <<4 x float>*>:496 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 182, i32 1		; <<4 x float>*>:497 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 182, i32 2		; <<4 x float>*>:498 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 182, i32 3		; <<4 x float>*>:499 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 183, i32 1		; <<4 x float>*>:500 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 183, i32 2		; <<4 x float>*>:501 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 183, i32 3		; <<4 x float>*>:502 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 184, i32 1		; <<4 x float>*>:503 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 184, i32 2		; <<4 x float>*>:504 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 184, i32 3		; <<4 x float>*>:505 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 185, i32 1		; <<4 x float>*>:506 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 185, i32 2		; <<4 x float>*>:507 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 185, i32 3		; <<4 x float>*>:508 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 190, i32 1		; <<4 x float>*>:509 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 190, i32 2		; <<4 x float>*>:510 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 190, i32 3		; <<4 x float>*>:511 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 9, i32 1		; <<4 x float>*>:512 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 9, i32 2		; <<4 x float>*>:513 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 9, i32 3		; <<4 x float>*>:514 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 10, i32 1		; <<4 x float>*>:515 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 10, i32 2		; <<4 x float>*>:516 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 10, i32 3		; <<4 x float>*>:517 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 11, i32 1		; <<4 x float>*>:518 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 11, i32 2		; <<4 x float>*>:519 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 11, i32 3		; <<4 x float>*>:520 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 12, i32 1		; <<4 x float>*>:521 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 12, i32 2		; <<4 x float>*>:522 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 12, i32 3		; <<4 x float>*>:523 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 13, i32 1		; <<4 x float>*>:524 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 13, i32 2		; <<4 x float>*>:525 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 13, i32 3		; <<4 x float>*>:526 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 1		; <<4 x float>*>:527 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2		; <<4 x float>*>:528 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3		; <<4 x float>*>:529 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1		; <<4 x float>*>:530 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2		; <<4 x float>*>:531 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3		; <<4 x float>*>:532 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 1		; <<4 x float>*>:533 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 2		; <<4 x float>*>:534 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 3		; <<4 x float>*>:535 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 6, i32 1		; <<4 x float>*>:536 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 6, i32 2		; <<4 x float>*>:537 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 6, i32 3		; <<4 x float>*>:538 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 7, i32 1		; <<4 x float>*>:539 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 7, i32 2		; <<4 x float>*>:540 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 7, i32 3		; <<4 x float>*>:541 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 1		; <<4 x float>*>:542 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2		; <<4 x float>*>:543 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3		; <<4 x float>*>:544 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 187, i32 1		; <<4 x float>*>:545 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 187, i32 2		; <<4 x float>*>:546 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 187, i32 3		; <<4 x float>*>:547 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 8, i32 1		; <<4 x float>*>:548 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 8, i32 2		; <<4 x float>*>:549 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 8, i32 3		; <<4 x float>*>:550 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:551 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 1		; <<4 x float>*>:552 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 2		; <<4 x float>*>:553 [#uses=1]
-	load <4 x float>* %553		; <<4 x float>>:554 [#uses=1]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 3		; <<4 x float>*>:555 [#uses=0]
+	%.sub7896 = getelementptr [4 x <4 x i32>], [4 x <4 x i32>]* null, i32 0, i32 0		; <<4 x i32>*> [#uses=24]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 175, i32 3		; <<4 x float>*>:2 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 174, i32 2		; <<4 x float>*>:3 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 174, i32 3		; <<4 x float>*>:4 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 173, i32 1		; <<4 x float>*>:5 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 173, i32 2		; <<4 x float>*>:6 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 173, i32 3		; <<4 x float>*>:7 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 172, i32 1		; <<4 x float>*>:8 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 172, i32 2		; <<4 x float>*>:9 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 172, i32 3		; <<4 x float>*>:10 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 171, i32 1		; <<4 x float>*>:11 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 171, i32 2		; <<4 x float>*>:12 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 171, i32 3		; <<4 x float>*>:13 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 170, i32 1		; <<4 x float>*>:14 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 170, i32 2		; <<4 x float>*>:15 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 170, i32 3		; <<4 x float>*>:16 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 169, i32 1		; <<4 x float>*>:17 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 169, i32 2		; <<4 x float>*>:18 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 169, i32 3		; <<4 x float>*>:19 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 168, i32 1		; <<4 x float>*>:20 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 168, i32 2		; <<4 x float>*>:21 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 168, i32 3		; <<4 x float>*>:22 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 167, i32 1		; <<4 x float>*>:23 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 167, i32 2		; <<4 x float>*>:24 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 167, i32 3		; <<4 x float>*>:25 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 166, i32 1		; <<4 x float>*>:26 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 166, i32 2		; <<4 x float>*>:27 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 166, i32 3		; <<4 x float>*>:28 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 165, i32 1		; <<4 x float>*>:29 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 165, i32 2		; <<4 x float>*>:30 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 165, i32 3		; <<4 x float>*>:31 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 164, i32 1		; <<4 x float>*>:32 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 164, i32 2		; <<4 x float>*>:33 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 164, i32 3		; <<4 x float>*>:34 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 163, i32 1		; <<4 x float>*>:35 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 163, i32 2		; <<4 x float>*>:36 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 163, i32 3		; <<4 x float>*>:37 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 162, i32 1		; <<4 x float>*>:38 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 162, i32 2		; <<4 x float>*>:39 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 162, i32 3		; <<4 x float>*>:40 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 161, i32 1		; <<4 x float>*>:41 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 161, i32 2		; <<4 x float>*>:42 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 161, i32 3		; <<4 x float>*>:43 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 160, i32 1		; <<4 x float>*>:44 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 160, i32 2		; <<4 x float>*>:45 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 160, i32 3		; <<4 x float>*>:46 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 159, i32 1		; <<4 x float>*>:47 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 159, i32 2		; <<4 x float>*>:48 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 159, i32 3		; <<4 x float>*>:49 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 158, i32 1		; <<4 x float>*>:50 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 158, i32 2		; <<4 x float>*>:51 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 158, i32 3		; <<4 x float>*>:52 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 157, i32 1		; <<4 x float>*>:53 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 157, i32 2		; <<4 x float>*>:54 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 157, i32 3		; <<4 x float>*>:55 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 156, i32 1		; <<4 x float>*>:56 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 156, i32 2		; <<4 x float>*>:57 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 156, i32 3		; <<4 x float>*>:58 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 155, i32 1		; <<4 x float>*>:59 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 155, i32 2		; <<4 x float>*>:60 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 155, i32 3		; <<4 x float>*>:61 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 154, i32 1		; <<4 x float>*>:62 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 154, i32 2		; <<4 x float>*>:63 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 154, i32 3		; <<4 x float>*>:64 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 153, i32 1		; <<4 x float>*>:65 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 153, i32 2		; <<4 x float>*>:66 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 153, i32 3		; <<4 x float>*>:67 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 152, i32 1		; <<4 x float>*>:68 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 152, i32 2		; <<4 x float>*>:69 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 152, i32 3		; <<4 x float>*>:70 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 151, i32 1		; <<4 x float>*>:71 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 151, i32 2		; <<4 x float>*>:72 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 151, i32 3		; <<4 x float>*>:73 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 150, i32 1		; <<4 x float>*>:74 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 150, i32 2		; <<4 x float>*>:75 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 150, i32 3		; <<4 x float>*>:76 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 149, i32 1		; <<4 x float>*>:77 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 149, i32 2		; <<4 x float>*>:78 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 149, i32 3		; <<4 x float>*>:79 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 148, i32 1		; <<4 x float>*>:80 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 148, i32 2		; <<4 x float>*>:81 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 148, i32 3		; <<4 x float>*>:82 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 147, i32 1		; <<4 x float>*>:83 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 147, i32 2		; <<4 x float>*>:84 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 147, i32 3		; <<4 x float>*>:85 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 146, i32 1		; <<4 x float>*>:86 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 146, i32 2		; <<4 x float>*>:87 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 146, i32 3		; <<4 x float>*>:88 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 145, i32 1		; <<4 x float>*>:89 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 145, i32 2		; <<4 x float>*>:90 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 145, i32 3		; <<4 x float>*>:91 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 144, i32 1		; <<4 x float>*>:92 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 144, i32 2		; <<4 x float>*>:93 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 144, i32 3		; <<4 x float>*>:94 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 143, i32 1		; <<4 x float>*>:95 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 143, i32 2		; <<4 x float>*>:96 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 143, i32 3		; <<4 x float>*>:97 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 142, i32 1		; <<4 x float>*>:98 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 142, i32 2		; <<4 x float>*>:99 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 142, i32 3		; <<4 x float>*>:100 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 141, i32 1		; <<4 x float>*>:101 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 141, i32 2		; <<4 x float>*>:102 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 141, i32 3		; <<4 x float>*>:103 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 140, i32 1		; <<4 x float>*>:104 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 140, i32 2		; <<4 x float>*>:105 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 140, i32 3		; <<4 x float>*>:106 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 139, i32 1		; <<4 x float>*>:107 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 139, i32 2		; <<4 x float>*>:108 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 139, i32 3		; <<4 x float>*>:109 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 138, i32 1		; <<4 x float>*>:110 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 138, i32 2		; <<4 x float>*>:111 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 138, i32 3		; <<4 x float>*>:112 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 137, i32 1		; <<4 x float>*>:113 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 137, i32 2		; <<4 x float>*>:114 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 137, i32 3		; <<4 x float>*>:115 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 136, i32 1		; <<4 x float>*>:116 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 136, i32 2		; <<4 x float>*>:117 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 136, i32 3		; <<4 x float>*>:118 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 135, i32 1		; <<4 x float>*>:119 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 135, i32 2		; <<4 x float>*>:120 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 135, i32 3		; <<4 x float>*>:121 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 134, i32 1		; <<4 x float>*>:122 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 134, i32 2		; <<4 x float>*>:123 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 134, i32 3		; <<4 x float>*>:124 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 133, i32 1		; <<4 x float>*>:125 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 133, i32 2		; <<4 x float>*>:126 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 133, i32 3		; <<4 x float>*>:127 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 132, i32 1		; <<4 x float>*>:128 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 132, i32 2		; <<4 x float>*>:129 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 132, i32 3		; <<4 x float>*>:130 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 131, i32 1		; <<4 x float>*>:131 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 131, i32 2		; <<4 x float>*>:132 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 131, i32 3		; <<4 x float>*>:133 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 130, i32 1		; <<4 x float>*>:134 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 130, i32 2		; <<4 x float>*>:135 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 130, i32 3		; <<4 x float>*>:136 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 129, i32 1		; <<4 x float>*>:137 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 129, i32 2		; <<4 x float>*>:138 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 129, i32 3		; <<4 x float>*>:139 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 128, i32 1		; <<4 x float>*>:140 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 128, i32 2		; <<4 x float>*>:141 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 128, i32 3		; <<4 x float>*>:142 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 127, i32 1		; <<4 x float>*>:143 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 127, i32 2		; <<4 x float>*>:144 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 127, i32 3		; <<4 x float>*>:145 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 126, i32 1		; <<4 x float>*>:146 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 126, i32 2		; <<4 x float>*>:147 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 126, i32 3		; <<4 x float>*>:148 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 125, i32 1		; <<4 x float>*>:149 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 125, i32 2		; <<4 x float>*>:150 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 125, i32 3		; <<4 x float>*>:151 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 124, i32 1		; <<4 x float>*>:152 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 124, i32 2		; <<4 x float>*>:153 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 124, i32 3		; <<4 x float>*>:154 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 123, i32 1		; <<4 x float>*>:155 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 123, i32 2		; <<4 x float>*>:156 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 123, i32 3		; <<4 x float>*>:157 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 122, i32 1		; <<4 x float>*>:158 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 122, i32 2		; <<4 x float>*>:159 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 122, i32 3		; <<4 x float>*>:160 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 121, i32 1		; <<4 x float>*>:161 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 121, i32 2		; <<4 x float>*>:162 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 121, i32 3		; <<4 x float>*>:163 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 120, i32 1		; <<4 x float>*>:164 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 120, i32 2		; <<4 x float>*>:165 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 120, i32 3		; <<4 x float>*>:166 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 119, i32 1		; <<4 x float>*>:167 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 119, i32 2		; <<4 x float>*>:168 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 119, i32 3		; <<4 x float>*>:169 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 118, i32 1		; <<4 x float>*>:170 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 118, i32 2		; <<4 x float>*>:171 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 118, i32 3		; <<4 x float>*>:172 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 117, i32 1		; <<4 x float>*>:173 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 117, i32 2		; <<4 x float>*>:174 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 117, i32 3		; <<4 x float>*>:175 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 116, i32 1		; <<4 x float>*>:176 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 116, i32 2		; <<4 x float>*>:177 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 116, i32 3		; <<4 x float>*>:178 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 115, i32 1		; <<4 x float>*>:179 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 115, i32 2		; <<4 x float>*>:180 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 115, i32 3		; <<4 x float>*>:181 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 114, i32 1		; <<4 x float>*>:182 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 114, i32 2		; <<4 x float>*>:183 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 114, i32 3		; <<4 x float>*>:184 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 113, i32 1		; <<4 x float>*>:185 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 113, i32 2		; <<4 x float>*>:186 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 113, i32 3		; <<4 x float>*>:187 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 112, i32 1		; <<4 x float>*>:188 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 112, i32 2		; <<4 x float>*>:189 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 112, i32 3		; <<4 x float>*>:190 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 111, i32 1		; <<4 x float>*>:191 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 111, i32 2		; <<4 x float>*>:192 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 111, i32 3		; <<4 x float>*>:193 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 110, i32 1		; <<4 x float>*>:194 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 110, i32 2		; <<4 x float>*>:195 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 110, i32 3		; <<4 x float>*>:196 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 109, i32 1		; <<4 x float>*>:197 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 109, i32 2		; <<4 x float>*>:198 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 109, i32 3		; <<4 x float>*>:199 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 108, i32 1		; <<4 x float>*>:200 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 108, i32 2		; <<4 x float>*>:201 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 108, i32 3		; <<4 x float>*>:202 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 107, i32 1		; <<4 x float>*>:203 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 107, i32 2		; <<4 x float>*>:204 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 107, i32 3		; <<4 x float>*>:205 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 106, i32 1		; <<4 x float>*>:206 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 106, i32 2		; <<4 x float>*>:207 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 106, i32 3		; <<4 x float>*>:208 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 105, i32 1		; <<4 x float>*>:209 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 105, i32 2		; <<4 x float>*>:210 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 105, i32 3		; <<4 x float>*>:211 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 104, i32 1		; <<4 x float>*>:212 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 104, i32 2		; <<4 x float>*>:213 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 104, i32 3		; <<4 x float>*>:214 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 103, i32 1		; <<4 x float>*>:215 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 103, i32 2		; <<4 x float>*>:216 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 103, i32 3		; <<4 x float>*>:217 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 102, i32 1		; <<4 x float>*>:218 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 102, i32 2		; <<4 x float>*>:219 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 102, i32 3		; <<4 x float>*>:220 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 101, i32 1		; <<4 x float>*>:221 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 101, i32 2		; <<4 x float>*>:222 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 101, i32 3		; <<4 x float>*>:223 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 100, i32 1		; <<4 x float>*>:224 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 100, i32 2		; <<4 x float>*>:225 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 100, i32 3		; <<4 x float>*>:226 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 99, i32 1		; <<4 x float>*>:227 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 99, i32 2		; <<4 x float>*>:228 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 99, i32 3		; <<4 x float>*>:229 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 98, i32 1		; <<4 x float>*>:230 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 98, i32 2		; <<4 x float>*>:231 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 98, i32 3		; <<4 x float>*>:232 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 97, i32 1		; <<4 x float>*>:233 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 97, i32 2		; <<4 x float>*>:234 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 97, i32 3		; <<4 x float>*>:235 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 96, i32 1		; <<4 x float>*>:236 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 96, i32 2		; <<4 x float>*>:237 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 96, i32 3		; <<4 x float>*>:238 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 95, i32 1		; <<4 x float>*>:239 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 95, i32 2		; <<4 x float>*>:240 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 95, i32 3		; <<4 x float>*>:241 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 94, i32 1		; <<4 x float>*>:242 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 94, i32 2		; <<4 x float>*>:243 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 94, i32 3		; <<4 x float>*>:244 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 93, i32 1		; <<4 x float>*>:245 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 93, i32 2		; <<4 x float>*>:246 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 93, i32 3		; <<4 x float>*>:247 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 92, i32 1		; <<4 x float>*>:248 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 92, i32 2		; <<4 x float>*>:249 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 92, i32 3		; <<4 x float>*>:250 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 91, i32 1		; <<4 x float>*>:251 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 91, i32 2		; <<4 x float>*>:252 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 91, i32 3		; <<4 x float>*>:253 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 90, i32 1		; <<4 x float>*>:254 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 90, i32 2		; <<4 x float>*>:255 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 90, i32 3		; <<4 x float>*>:256 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 89, i32 1		; <<4 x float>*>:257 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 89, i32 2		; <<4 x float>*>:258 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 89, i32 3		; <<4 x float>*>:259 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 88, i32 1		; <<4 x float>*>:260 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 88, i32 2		; <<4 x float>*>:261 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 88, i32 3		; <<4 x float>*>:262 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 87, i32 1		; <<4 x float>*>:263 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 87, i32 2		; <<4 x float>*>:264 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 87, i32 3		; <<4 x float>*>:265 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 86, i32 1		; <<4 x float>*>:266 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 86, i32 2		; <<4 x float>*>:267 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 86, i32 3		; <<4 x float>*>:268 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 85, i32 1		; <<4 x float>*>:269 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 85, i32 2		; <<4 x float>*>:270 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 85, i32 3		; <<4 x float>*>:271 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 84, i32 1		; <<4 x float>*>:272 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 84, i32 2		; <<4 x float>*>:273 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 84, i32 3		; <<4 x float>*>:274 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 83, i32 1		; <<4 x float>*>:275 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 83, i32 2		; <<4 x float>*>:276 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 83, i32 3		; <<4 x float>*>:277 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 82, i32 1		; <<4 x float>*>:278 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 82, i32 2		; <<4 x float>*>:279 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 82, i32 3		; <<4 x float>*>:280 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 81, i32 1		; <<4 x float>*>:281 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 81, i32 2		; <<4 x float>*>:282 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 81, i32 3		; <<4 x float>*>:283 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 80, i32 1		; <<4 x float>*>:284 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 80, i32 2		; <<4 x float>*>:285 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 80, i32 3		; <<4 x float>*>:286 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 79, i32 1		; <<4 x float>*>:287 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 79, i32 2		; <<4 x float>*>:288 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 79, i32 3		; <<4 x float>*>:289 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 78, i32 1		; <<4 x float>*>:290 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 78, i32 2		; <<4 x float>*>:291 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 78, i32 3		; <<4 x float>*>:292 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 77, i32 1		; <<4 x float>*>:293 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 77, i32 2		; <<4 x float>*>:294 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 77, i32 3		; <<4 x float>*>:295 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 76, i32 1		; <<4 x float>*>:296 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 76, i32 2		; <<4 x float>*>:297 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 76, i32 3		; <<4 x float>*>:298 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 75, i32 1		; <<4 x float>*>:299 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 75, i32 2		; <<4 x float>*>:300 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 75, i32 3		; <<4 x float>*>:301 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 74, i32 1		; <<4 x float>*>:302 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 74, i32 2		; <<4 x float>*>:303 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 74, i32 3		; <<4 x float>*>:304 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 73, i32 1		; <<4 x float>*>:305 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 73, i32 2		; <<4 x float>*>:306 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 73, i32 3		; <<4 x float>*>:307 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 72, i32 1		; <<4 x float>*>:308 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 72, i32 2		; <<4 x float>*>:309 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 72, i32 3		; <<4 x float>*>:310 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 71, i32 1		; <<4 x float>*>:311 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 71, i32 2		; <<4 x float>*>:312 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 71, i32 3		; <<4 x float>*>:313 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 70, i32 1		; <<4 x float>*>:314 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 70, i32 2		; <<4 x float>*>:315 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 70, i32 3		; <<4 x float>*>:316 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 69, i32 1		; <<4 x float>*>:317 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 69, i32 2		; <<4 x float>*>:318 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 69, i32 3		; <<4 x float>*>:319 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 68, i32 1		; <<4 x float>*>:320 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 68, i32 2		; <<4 x float>*>:321 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 68, i32 3		; <<4 x float>*>:322 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 67, i32 1		; <<4 x float>*>:323 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 67, i32 2		; <<4 x float>*>:324 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 67, i32 3		; <<4 x float>*>:325 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 66, i32 1		; <<4 x float>*>:326 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 66, i32 2		; <<4 x float>*>:327 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 66, i32 3		; <<4 x float>*>:328 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 65, i32 1		; <<4 x float>*>:329 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 65, i32 2		; <<4 x float>*>:330 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 65, i32 3		; <<4 x float>*>:331 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 64, i32 1		; <<4 x float>*>:332 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 64, i32 2		; <<4 x float>*>:333 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 64, i32 3		; <<4 x float>*>:334 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 63, i32 1		; <<4 x float>*>:335 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 63, i32 2		; <<4 x float>*>:336 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 63, i32 3		; <<4 x float>*>:337 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 62, i32 1		; <<4 x float>*>:338 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 62, i32 2		; <<4 x float>*>:339 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 62, i32 3		; <<4 x float>*>:340 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 61, i32 1		; <<4 x float>*>:341 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 61, i32 2		; <<4 x float>*>:342 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 61, i32 3		; <<4 x float>*>:343 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 60, i32 1		; <<4 x float>*>:344 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 60, i32 2		; <<4 x float>*>:345 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 60, i32 3		; <<4 x float>*>:346 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 59, i32 1		; <<4 x float>*>:347 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 59, i32 2		; <<4 x float>*>:348 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 59, i32 3		; <<4 x float>*>:349 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 58, i32 1		; <<4 x float>*>:350 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 58, i32 2		; <<4 x float>*>:351 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 58, i32 3		; <<4 x float>*>:352 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 57, i32 1		; <<4 x float>*>:353 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 57, i32 2		; <<4 x float>*>:354 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 57, i32 3		; <<4 x float>*>:355 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 56, i32 1		; <<4 x float>*>:356 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 56, i32 2		; <<4 x float>*>:357 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 56, i32 3		; <<4 x float>*>:358 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 55, i32 1		; <<4 x float>*>:359 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 55, i32 2		; <<4 x float>*>:360 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 55, i32 3		; <<4 x float>*>:361 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 54, i32 1		; <<4 x float>*>:362 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 54, i32 2		; <<4 x float>*>:363 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 54, i32 3		; <<4 x float>*>:364 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 53, i32 1		; <<4 x float>*>:365 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 53, i32 2		; <<4 x float>*>:366 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 53, i32 3		; <<4 x float>*>:367 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 52, i32 1		; <<4 x float>*>:368 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 52, i32 2		; <<4 x float>*>:369 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 52, i32 3		; <<4 x float>*>:370 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 51, i32 1		; <<4 x float>*>:371 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 51, i32 2		; <<4 x float>*>:372 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 51, i32 3		; <<4 x float>*>:373 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 50, i32 1		; <<4 x float>*>:374 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 50, i32 2		; <<4 x float>*>:375 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 50, i32 3		; <<4 x float>*>:376 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 49, i32 1		; <<4 x float>*>:377 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 49, i32 2		; <<4 x float>*>:378 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 49, i32 3		; <<4 x float>*>:379 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 48, i32 1		; <<4 x float>*>:380 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 48, i32 2		; <<4 x float>*>:381 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 48, i32 3		; <<4 x float>*>:382 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 47, i32 1		; <<4 x float>*>:383 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 47, i32 2		; <<4 x float>*>:384 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 47, i32 3		; <<4 x float>*>:385 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 46, i32 1		; <<4 x float>*>:386 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 46, i32 2		; <<4 x float>*>:387 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 46, i32 3		; <<4 x float>*>:388 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 45, i32 1		; <<4 x float>*>:389 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 45, i32 2		; <<4 x float>*>:390 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 45, i32 3		; <<4 x float>*>:391 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 44, i32 1		; <<4 x float>*>:392 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 44, i32 2		; <<4 x float>*>:393 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 44, i32 3		; <<4 x float>*>:394 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 43, i32 1		; <<4 x float>*>:395 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 43, i32 2		; <<4 x float>*>:396 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 43, i32 3		; <<4 x float>*>:397 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 42, i32 1		; <<4 x float>*>:398 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 42, i32 2		; <<4 x float>*>:399 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 42, i32 3		; <<4 x float>*>:400 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 41, i32 1		; <<4 x float>*>:401 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 41, i32 2		; <<4 x float>*>:402 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 41, i32 3		; <<4 x float>*>:403 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 40, i32 1		; <<4 x float>*>:404 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 40, i32 2		; <<4 x float>*>:405 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 40, i32 3		; <<4 x float>*>:406 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 39, i32 1		; <<4 x float>*>:407 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 39, i32 2		; <<4 x float>*>:408 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 39, i32 3		; <<4 x float>*>:409 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 38, i32 1		; <<4 x float>*>:410 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 38, i32 2		; <<4 x float>*>:411 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 38, i32 3		; <<4 x float>*>:412 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 37, i32 1		; <<4 x float>*>:413 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 37, i32 2		; <<4 x float>*>:414 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 37, i32 3		; <<4 x float>*>:415 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 36, i32 1		; <<4 x float>*>:416 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 36, i32 2		; <<4 x float>*>:417 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 36, i32 3		; <<4 x float>*>:418 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 35, i32 1		; <<4 x float>*>:419 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 35, i32 2		; <<4 x float>*>:420 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 35, i32 3		; <<4 x float>*>:421 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 34, i32 1		; <<4 x float>*>:422 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 34, i32 2		; <<4 x float>*>:423 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 34, i32 3		; <<4 x float>*>:424 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 33, i32 1		; <<4 x float>*>:425 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 33, i32 2		; <<4 x float>*>:426 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 33, i32 3		; <<4 x float>*>:427 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 32, i32 1		; <<4 x float>*>:428 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 32, i32 2		; <<4 x float>*>:429 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 32, i32 3		; <<4 x float>*>:430 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 31, i32 1		; <<4 x float>*>:431 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 31, i32 2		; <<4 x float>*>:432 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 31, i32 3		; <<4 x float>*>:433 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 30, i32 1		; <<4 x float>*>:434 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 30, i32 2		; <<4 x float>*>:435 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 30, i32 3		; <<4 x float>*>:436 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 29, i32 1		; <<4 x float>*>:437 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 29, i32 2		; <<4 x float>*>:438 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 29, i32 3		; <<4 x float>*>:439 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 28, i32 1		; <<4 x float>*>:440 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 28, i32 2		; <<4 x float>*>:441 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 28, i32 3		; <<4 x float>*>:442 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 27, i32 1		; <<4 x float>*>:443 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 27, i32 2		; <<4 x float>*>:444 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 27, i32 3		; <<4 x float>*>:445 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 26, i32 1		; <<4 x float>*>:446 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 26, i32 2		; <<4 x float>*>:447 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 26, i32 3		; <<4 x float>*>:448 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 25, i32 1		; <<4 x float>*>:449 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 25, i32 2		; <<4 x float>*>:450 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 25, i32 3		; <<4 x float>*>:451 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 24, i32 1		; <<4 x float>*>:452 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 24, i32 2		; <<4 x float>*>:453 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 24, i32 3		; <<4 x float>*>:454 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 23, i32 1		; <<4 x float>*>:455 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 23, i32 2		; <<4 x float>*>:456 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 23, i32 3		; <<4 x float>*>:457 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 22, i32 1		; <<4 x float>*>:458 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 22, i32 2		; <<4 x float>*>:459 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 22, i32 3		; <<4 x float>*>:460 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 21, i32 1		; <<4 x float>*>:461 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 21, i32 2		; <<4 x float>*>:462 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 21, i32 3		; <<4 x float>*>:463 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 20, i32 1		; <<4 x float>*>:464 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 20, i32 2		; <<4 x float>*>:465 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 20, i32 3		; <<4 x float>*>:466 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 19, i32 1		; <<4 x float>*>:467 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 19, i32 2		; <<4 x float>*>:468 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 19, i32 3		; <<4 x float>*>:469 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 18, i32 1		; <<4 x float>*>:470 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 18, i32 2		; <<4 x float>*>:471 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 18, i32 3		; <<4 x float>*>:472 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 17, i32 1		; <<4 x float>*>:473 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 17, i32 2		; <<4 x float>*>:474 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 17, i32 3		; <<4 x float>*>:475 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 16, i32 1		; <<4 x float>*>:476 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 16, i32 2		; <<4 x float>*>:477 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 16, i32 3		; <<4 x float>*>:478 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 15, i32 1		; <<4 x float>*>:479 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 15, i32 2		; <<4 x float>*>:480 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 15, i32 3		; <<4 x float>*>:481 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 14, i32 1		; <<4 x float>*>:482 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 14, i32 2		; <<4 x float>*>:483 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 14, i32 3		; <<4 x float>*>:484 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1		; <<4 x float>*>:485 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:486 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:487 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 1		; <<4 x float>*>:488 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 2		; <<4 x float>*>:489 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 3		; <<4 x float>*>:490 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 180, i32 1		; <<4 x float>*>:491 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 180, i32 2		; <<4 x float>*>:492 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 180, i32 3		; <<4 x float>*>:493 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 181, i32 1		; <<4 x float>*>:494 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 181, i32 2		; <<4 x float>*>:495 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 181, i32 3		; <<4 x float>*>:496 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 182, i32 1		; <<4 x float>*>:497 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 182, i32 2		; <<4 x float>*>:498 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 182, i32 3		; <<4 x float>*>:499 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 183, i32 1		; <<4 x float>*>:500 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 183, i32 2		; <<4 x float>*>:501 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 183, i32 3		; <<4 x float>*>:502 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 184, i32 1		; <<4 x float>*>:503 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 184, i32 2		; <<4 x float>*>:504 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 184, i32 3		; <<4 x float>*>:505 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 185, i32 1		; <<4 x float>*>:506 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 185, i32 2		; <<4 x float>*>:507 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 185, i32 3		; <<4 x float>*>:508 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 190, i32 1		; <<4 x float>*>:509 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 190, i32 2		; <<4 x float>*>:510 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 190, i32 3		; <<4 x float>*>:511 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 9, i32 1		; <<4 x float>*>:512 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 9, i32 2		; <<4 x float>*>:513 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 9, i32 3		; <<4 x float>*>:514 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 10, i32 1		; <<4 x float>*>:515 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 10, i32 2		; <<4 x float>*>:516 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 10, i32 3		; <<4 x float>*>:517 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 11, i32 1		; <<4 x float>*>:518 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 11, i32 2		; <<4 x float>*>:519 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 11, i32 3		; <<4 x float>*>:520 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 12, i32 1		; <<4 x float>*>:521 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 12, i32 2		; <<4 x float>*>:522 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 12, i32 3		; <<4 x float>*>:523 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 13, i32 1		; <<4 x float>*>:524 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 13, i32 2		; <<4 x float>*>:525 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 13, i32 3		; <<4 x float>*>:526 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 1		; <<4 x float>*>:527 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2		; <<4 x float>*>:528 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3		; <<4 x float>*>:529 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1		; <<4 x float>*>:530 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2		; <<4 x float>*>:531 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3		; <<4 x float>*>:532 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 1		; <<4 x float>*>:533 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 2		; <<4 x float>*>:534 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 3		; <<4 x float>*>:535 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 6, i32 1		; <<4 x float>*>:536 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 6, i32 2		; <<4 x float>*>:537 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 6, i32 3		; <<4 x float>*>:538 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 7, i32 1		; <<4 x float>*>:539 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 7, i32 2		; <<4 x float>*>:540 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 7, i32 3		; <<4 x float>*>:541 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 1		; <<4 x float>*>:542 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2		; <<4 x float>*>:543 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3		; <<4 x float>*>:544 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 187, i32 1		; <<4 x float>*>:545 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 187, i32 2		; <<4 x float>*>:546 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 187, i32 3		; <<4 x float>*>:547 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 8, i32 1		; <<4 x float>*>:548 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 8, i32 2		; <<4 x float>*>:549 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 8, i32 3		; <<4 x float>*>:550 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:551 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 1		; <<4 x float>*>:552 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 2		; <<4 x float>*>:553 [#uses=1]
+	load <4 x float>, <4 x float>* %553		; <<4 x float>>:554 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 3		; <<4 x float>*>:555 [#uses=0]
 	shufflevector <4 x float> %554, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:556 [#uses=1]
 	call <4 x i32> @llvm.ppc.altivec.vcmpgtfp( <4 x float> zeroinitializer, <4 x float> %556 )		; <<4 x i32>>:557 [#uses=0]
 	bitcast <4 x i32> zeroinitializer to <4 x float>		; <<4 x float>>:558 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0		; <<4 x float>*>:559 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 2		; <<4 x float>*>:560 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0		; <<4 x float>*>:559 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 2		; <<4 x float>*>:560 [#uses=1]
 	store <4 x float> zeroinitializer, <4 x float>* %560
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3		; <<4 x float>*>:561 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1		; <<4 x float>*>:562 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 2		; <<4 x float>*>:563 [#uses=0]
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:564 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3		; <<4 x float>*>:561 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1		; <<4 x float>*>:562 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 2		; <<4 x float>*>:563 [#uses=0]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:564 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:565 [#uses=1]
 	store <4 x float> %565, <4 x float>* null
 	icmp eq i32 0, 0		; <i1>:566 [#uses=1]
 	br i1 %566, label %.critedge, label %xPIF.exit
 
 .critedge:		; preds = %xOperationInitMasks.exit
-	getelementptr [4 x <4 x i32>]* null, i32 0, i32 3		; <<4 x i32>*>:567 [#uses=0]
+	getelementptr [4 x <4 x i32>], [4 x <4 x i32>]* null, i32 0, i32 3		; <<4 x i32>*>:567 [#uses=0]
 	and <4 x i32> zeroinitializer, zeroinitializer		; <<4 x i32>>:568 [#uses=0]
 	or <4 x i32> zeroinitializer, zeroinitializer		; <<4 x i32>>:569 [#uses=0]
 	icmp eq i32 0, 0		; <i1>:570 [#uses=1]
@@ -583,24 +583,24 @@ xOperationInitMasks.exit:
 	br label %xPIF.exit
 
 xPIF.exit:		; preds = %.critedge7898, %xOperationInitMasks.exit
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 1		; <<4 x float>*>:571 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:572 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 1		; <<4 x float>*>:571 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:572 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:573 [#uses=0]
 	icmp eq i32 0, 0		; <i1>:574 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 1		; <<4 x float>*>:575 [#uses=0]
-	load <4 x float>* %0		; <<4 x float>>:576 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 1		; <<4 x float>*>:575 [#uses=0]
+	load <4 x float>, <4 x float>* %0		; <<4 x float>>:576 [#uses=0]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer )		; <i32>:577 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 0		; <<4 x float>*>:578 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 1		; <<4 x float>*>:579 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 2		; <<4 x float>*>:580 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 3		; <<4 x float>*>:581 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3		; <<4 x float>*>:582 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:583 [#uses=1]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1		; <<4 x float>*>:584 [#uses=1]
-	load <4 x float>* %584		; <<4 x float>>:585 [#uses=1]
-	load <4 x float>* null		; <<4 x float>>:586 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:587 [#uses=1]
-	load <4 x float>* %587		; <<4 x float>>:588 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 0		; <<4 x float>*>:578 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 1		; <<4 x float>*>:579 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 2		; <<4 x float>*>:580 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 3		; <<4 x float>*>:581 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3		; <<4 x float>*>:582 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:583 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1		; <<4 x float>*>:584 [#uses=1]
+	load <4 x float>, <4 x float>* %584		; <<4 x float>>:585 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:586 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:587 [#uses=1]
+	load <4 x float>, <4 x float>* %587		; <<4 x float>>:588 [#uses=1]
 	shufflevector <4 x float> %583, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >		; <<4 x float>>:589 [#uses=1]
 	shufflevector <4 x float> %585, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >		; <<4 x float>>:590 [#uses=1]
 	shufflevector <4 x float> %588, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >		; <<4 x float>>:591 [#uses=1]
@@ -608,32 +608,32 @@ xPIF.exit:		; preds = %.critedge7898, %xOperationInitMasks.exit
 	fmul <4 x float> zeroinitializer, %590		; <<4 x float>>:593 [#uses=0]
 	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:594 [#uses=1]
 	fmul <4 x float> zeroinitializer, %591		; <<4 x float>>:595 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0		; <<4 x float>*>:596 [#uses=2]
-	load <4 x float>* %596		; <<4 x float>>:597 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0		; <<4 x float>*>:596 [#uses=2]
+	load <4 x float>, <4 x float>* %596		; <<4 x float>>:597 [#uses=0]
 	store <4 x float> zeroinitializer, <4 x float>* %596
-	load <4 x float>* null		; <<4 x float>>:598 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:599 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:598 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:599 [#uses=0]
 	shufflevector <4 x float> %594, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 >		; <<4 x float>>:600 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:601 [#uses=2]
-	load <4 x float>* %601		; <<4 x float>>:602 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:601 [#uses=2]
+	load <4 x float>, <4 x float>* %601		; <<4 x float>>:602 [#uses=0]
 	store <4 x float> zeroinitializer, <4 x float>* %601
-	load <4 x float>* null		; <<4 x float>>:603 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:604 [#uses=1]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:605 [#uses=1]
-	load <4 x float>* %605		; <<4 x float>>:606 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:603 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:604 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:605 [#uses=1]
+	load <4 x float>, <4 x float>* %605		; <<4 x float>>:606 [#uses=1]
 	fsub <4 x float> zeroinitializer, %604		; <<4 x float>>:607 [#uses=2]
 	fsub <4 x float> zeroinitializer, %606		; <<4 x float>>:608 [#uses=2]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer )		; <i32>:609 [#uses=0]
 	br i1 false, label %617, label %610
 
 ; <label>:610		; preds = %xPIF.exit
-	load <4 x float>* null		; <<4 x float>>:611 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1		; <<4 x float>*>:612 [#uses=2]
-	load <4 x float>* %612		; <<4 x float>>:613 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:611 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1		; <<4 x float>*>:612 [#uses=2]
+	load <4 x float>, <4 x float>* %612		; <<4 x float>>:613 [#uses=1]
 	shufflevector <4 x float> %607, <4 x float> %613, <4 x i32> < i32 0, i32 1, i32 2, i32 7 >		; <<4 x float>>:614 [#uses=1]
 	store <4 x float> %614, <4 x float>* %612
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:615 [#uses=2]
-	load <4 x float>* %615		; <<4 x float>>:616 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:615 [#uses=2]
+	load <4 x float>, <4 x float>* %615		; <<4 x float>>:616 [#uses=0]
 	store <4 x float> zeroinitializer, <4 x float>* %615
 	br label %xST.exit400
 
@@ -645,33 +645,33 @@ xPIF.exit:		; preds = %.critedge7898, %xOperationInitMasks.exit
 	br i1 %621, label %625, label %622
 
 ; <label>:622		; preds = %617
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1		; <<4 x float>*>:623 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1		; <<4 x float>*>:623 [#uses=0]
 	shufflevector <4 x float> %607, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 >		; <<4 x float>>:624 [#uses=0]
 	br label %625
 
 ; <label>:625		; preds = %622, %617
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:626 [#uses=0]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:626 [#uses=0]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer )		; <i32>:627 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:628 [#uses=1]
-	load <4 x float>* %628		; <<4 x float>>:629 [#uses=0]
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:630 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:628 [#uses=1]
+	load <4 x float>, <4 x float>* %628		; <<4 x float>>:629 [#uses=0]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:630 [#uses=0]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer )		; <i32>:631 [#uses=1]
 	icmp eq i32 %631, 0		; <i1>:632 [#uses=1]
 	br i1 %632, label %xST.exit400, label %633
 
 ; <label>:633		; preds = %625
-	load <4 x float>* null		; <<4 x float>>:634 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:634 [#uses=1]
 	shufflevector <4 x float> zeroinitializer, <4 x float> %634, <4 x i32> < i32 0, i32 1, i32 2, i32 7 >		; <<4 x float>>:635 [#uses=1]
 	store <4 x float> %635, <4 x float>* null
 	br label %xST.exit400
 
 xST.exit400:		; preds = %633, %625, %610
 	%.17218 = phi <4 x float> [ zeroinitializer, %610 ], [ %608, %633 ], [ %608, %625 ]		; <<4 x float>> [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 0		; <<4 x float>*>:636 [#uses=1]
-	load <4 x float>* %636		; <<4 x float>>:637 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:638 [#uses=2]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:639 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:640 [#uses=2]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 0		; <<4 x float>*>:636 [#uses=1]
+	load <4 x float>, <4 x float>* %636		; <<4 x float>>:637 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:638 [#uses=2]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:639 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:640 [#uses=2]
 	fmul <4 x float> %638, %638		; <<4 x float>>:641 [#uses=1]
 	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:642 [#uses=0]
 	fmul <4 x float> %640, %640		; <<4 x float>>:643 [#uses=2]
@@ -691,12 +691,12 @@ xST.exit400:		; preds = %633, %625, %610
 	br i1 %656, label %665, label %657
 
 ; <label>:657		; preds = %xST.exit400
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0		; <<4 x float>*>:658 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0		; <<4 x float>*>:658 [#uses=0]
 	shufflevector <4 x float> %653, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:659 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1		; <<4 x float>*>:660 [#uses=1]
-	load <4 x float>* %660		; <<4 x float>>:661 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:662 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:663 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1		; <<4 x float>*>:660 [#uses=1]
+	load <4 x float>, <4 x float>* %660		; <<4 x float>>:661 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:662 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:663 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:664 [#uses=0]
 	br label %xST.exit402
 
@@ -705,7 +705,7 @@ xST.exit400:		; preds = %633, %625, %610
 	br i1 false, label %669, label %667
 
 ; <label>:667		; preds = %665
-	load <4 x float>* null		; <<4 x float>>:668 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:668 [#uses=0]
 	br label %669
 
 ; <label>:669		; preds = %667, %665
@@ -713,12 +713,12 @@ xST.exit400:		; preds = %633, %625, %610
 	br label %xST.exit402
 
 xST.exit402:		; preds = %669, %657
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0		; <<4 x float>*>:671 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:672 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2		; <<4 x float>*>:673 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1		; <<4 x float>*>:674 [#uses=1]
-	load <4 x float>* %674		; <<4 x float>>:675 [#uses=1]
-	load <4 x float>* null		; <<4 x float>>:676 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0		; <<4 x float>*>:671 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:672 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2		; <<4 x float>*>:673 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1		; <<4 x float>*>:674 [#uses=1]
+	load <4 x float>, <4 x float>* %674		; <<4 x float>>:675 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:676 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:677 [#uses=1]
 	shufflevector <4 x float> %675, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:678 [#uses=1]
 	fmul <4 x float> zeroinitializer, %677		; <<4 x float>>:679 [#uses=0]
@@ -728,68 +728,68 @@ xST.exit402:		; preds = %669, %657
 	br i1 %682, label %689, label %683
 
 ; <label>:683		; preds = %xST.exit402
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 1		; <<4 x float>*>:684 [#uses=1]
-	load <4 x float>* %684		; <<4 x float>>:685 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2		; <<4 x float>*>:686 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3		; <<4 x float>*>:687 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 1		; <<4 x float>*>:684 [#uses=1]
+	load <4 x float>, <4 x float>* %684		; <<4 x float>>:685 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2		; <<4 x float>*>:686 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3		; <<4 x float>*>:687 [#uses=0]
 	shufflevector <4 x float> %681, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:688 [#uses=0]
 	br label %xST.exit405
 
 ; <label>:689		; preds = %xST.exit402
 	shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> zeroinitializer		; <<4 x i32>>:690 [#uses=0]
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:691 [#uses=1]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:691 [#uses=1]
 	shufflevector <4 x i32> %691, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >		; <<4 x i32>>:692 [#uses=1]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %692, <4 x i32> zeroinitializer )		; <i32>:693 [#uses=1]
 	icmp eq i32 %693, 0		; <i1>:694 [#uses=0]
 	br label %xST.exit405
 
 xST.exit405:		; preds = %689, %683
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3		; <<4 x float>*>:695 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3		; <<4 x float>*>:695 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:696 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:697 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:698 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2		; <<4 x float>*>:699 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:698 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2		; <<4 x float>*>:699 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:700 [#uses=1]
 	fadd <4 x float> zeroinitializer, %700		; <<4 x float>>:701 [#uses=0]
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:702 [#uses=1]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:702 [#uses=1]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %702, <4 x i32> zeroinitializer )		; <i32>:703 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1		; <<4 x float>*>:704 [#uses=2]
-	load <4 x float>* %704		; <<4 x float>>:705 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1		; <<4 x float>*>:704 [#uses=2]
+	load <4 x float>, <4 x float>* %704		; <<4 x float>>:705 [#uses=0]
 	store <4 x float> zeroinitializer, <4 x float>* %704
-	load <4 x float>* null		; <<4 x float>>:706 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:706 [#uses=0]
 	store <4 x float> zeroinitializer, <4 x float>* null
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3		; <<4 x float>*>:707 [#uses=2]
-	load <4 x float>* %707		; <<4 x float>>:708 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3		; <<4 x float>*>:707 [#uses=2]
+	load <4 x float>, <4 x float>* %707		; <<4 x float>>:708 [#uses=0]
 	store <4 x float> zeroinitializer, <4 x float>* %707
-	load <4 x float>* null		; <<4 x float>>:709 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:710 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:711 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:709 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:710 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:711 [#uses=1]
 	shufflevector <4 x float> %711, <4 x float> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 >		; <<4 x float>>:712 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1		; <<4 x float>*>:713 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:714 [#uses=1]
-	load <4 x float>* %714		; <<4 x float>>:715 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1		; <<4 x float>*>:713 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:714 [#uses=1]
+	load <4 x float>, <4 x float>* %714		; <<4 x float>>:715 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:716 [#uses=0]
 	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:717 [#uses=1]
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:718 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 0		; <<4 x float>*>:719 [#uses=1]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:718 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 0		; <<4 x float>*>:719 [#uses=1]
 	store <4 x float> zeroinitializer, <4 x float>* %719
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 1		; <<4 x float>*>:720 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 1		; <<4 x float>*>:720 [#uses=1]
 	shufflevector <4 x float> %717, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:721 [#uses=1]
 	store <4 x float> %721, <4 x float>* %720
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2		; <<4 x float>*>:722 [#uses=1]
-	load <4 x float>* %722		; <<4 x float>>:723 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2		; <<4 x float>*>:722 [#uses=1]
+	load <4 x float>, <4 x float>* %722		; <<4 x float>>:723 [#uses=1]
 	shufflevector <4 x float> zeroinitializer, <4 x float> %723, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:724 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3		; <<4 x float>*>:725 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3		; <<4 x float>*>:725 [#uses=1]
 	store <4 x float> zeroinitializer, <4 x float>* %725
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2		; <<4 x float>*>:726 [#uses=1]
-	load <4 x float>* %726		; <<4 x float>>:727 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3		; <<4 x float>*>:728 [#uses=1]
-	load <4 x float>* %728		; <<4 x float>>:729 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0		; <<4 x float>*>:730 [#uses=1]
-	load <4 x float>* %730		; <<4 x float>>:731 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1		; <<4 x float>*>:732 [#uses=1]
-	load <4 x float>* %732		; <<4 x float>>:733 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:734 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2		; <<4 x float>*>:726 [#uses=1]
+	load <4 x float>, <4 x float>* %726		; <<4 x float>>:727 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3		; <<4 x float>*>:728 [#uses=1]
+	load <4 x float>, <4 x float>* %728		; <<4 x float>>:729 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0		; <<4 x float>*>:730 [#uses=1]
+	load <4 x float>, <4 x float>* %730		; <<4 x float>>:731 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1		; <<4 x float>*>:732 [#uses=1]
+	load <4 x float>, <4 x float>* %732		; <<4 x float>>:733 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:734 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:735 [#uses=1]
 	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:736 [#uses=1]
 	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:737 [#uses=1]
@@ -797,28 +797,28 @@ xST.exit405:		; preds = %689, %683
 	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:739 [#uses=1]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer )		; <i32>:740 [#uses=1]
 	icmp eq i32 %740, 0		; <i1>:741 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0		; <<4 x float>*>:742 [#uses=2]
-	load <4 x float>* %742		; <<4 x float>>:743 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0		; <<4 x float>*>:742 [#uses=2]
+	load <4 x float>, <4 x float>* %742		; <<4 x float>>:743 [#uses=1]
 	shufflevector <4 x float> %736, <4 x float> %743, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:744 [#uses=1]
 	store <4 x float> %744, <4 x float>* %742
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1		; <<4 x float>*>:745 [#uses=1]
-	load <4 x float>* %745		; <<4 x float>>:746 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1		; <<4 x float>*>:745 [#uses=1]
+	load <4 x float>, <4 x float>* %745		; <<4 x float>>:746 [#uses=1]
 	shufflevector <4 x float> %737, <4 x float> %746, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:747 [#uses=0]
 	shufflevector <4 x float> %738, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:748 [#uses=1]
 	store <4 x float> %748, <4 x float>* null
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:749 [#uses=1]
-	load <4 x float>* %749		; <<4 x float>>:750 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:749 [#uses=1]
+	load <4 x float>, <4 x float>* %749		; <<4 x float>>:750 [#uses=1]
 	shufflevector <4 x float> %739, <4 x float> %750, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:751 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0		; <<4 x float>*>:752 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1		; <<4 x float>*>:753 [#uses=1]
-	load <4 x float>* %753		; <<4 x float>>:754 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2		; <<4 x float>*>:755 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:756 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0		; <<4 x float>*>:752 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1		; <<4 x float>*>:753 [#uses=1]
+	load <4 x float>, <4 x float>* %753		; <<4 x float>>:754 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2		; <<4 x float>*>:755 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:756 [#uses=1]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:757 [#uses=1]
 	shufflevector <4 x float> %756, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:758 [#uses=1]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:759 [#uses=1]
-	load <4 x float>* %759		; <<4 x float>>:760 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:761 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:759 [#uses=1]
+	load <4 x float>, <4 x float>* %759		; <<4 x float>>:760 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:761 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:762 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:763 [#uses=1]
 	fadd <4 x float> %757, zeroinitializer		; <<4 x float>>:764 [#uses=0]
@@ -827,12 +827,12 @@ xST.exit405:		; preds = %689, %683
 	br i1 false, label %773, label %767
 
 ; <label>:767		; preds = %xST.exit405
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1		; <<4 x float>*>:768 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:769 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1		; <<4 x float>*>:768 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:769 [#uses=1]
 	shufflevector <4 x float> zeroinitializer, <4 x float> %769, <4 x i32> < i32 0, i32 1, i32 2, i32 7 >		; <<4 x float>>:770 [#uses=1]
 	store <4 x float> %770, <4 x float>* null
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:771 [#uses=1]
-	load <4 x float>* %771		; <<4 x float>>:772 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:771 [#uses=1]
+	load <4 x float>, <4 x float>* %771		; <<4 x float>>:772 [#uses=0]
 	br label %xST.exit422
 
 ; <label>:773		; preds = %xST.exit405
@@ -840,30 +840,30 @@ xST.exit405:		; preds = %689, %683
 
 xST.exit422:		; preds = %773, %767
 	%.07267 = phi <4 x float> [ %766, %767 ], [ undef, %773 ]		; <<4 x float>> [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:774 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:774 [#uses=0]
 	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:775 [#uses=0]
 	icmp eq i32 0, 0		; <i1>:776 [#uses=1]
 	br i1 %776, label %780, label %777
 
 ; <label>:777		; preds = %xST.exit422
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:778 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:779 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:778 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:779 [#uses=0]
 	br label %xST.exit431
 
 ; <label>:780		; preds = %xST.exit422
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:781 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:782 [#uses=2]
-	load <4 x float>* %782		; <<4 x float>>:783 [#uses=0]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:781 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:782 [#uses=2]
+	load <4 x float>, <4 x float>* %782		; <<4 x float>>:783 [#uses=0]
 	store <4 x float> zeroinitializer, <4 x float>* %782
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:784 [#uses=1]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:784 [#uses=1]
 	shufflevector <4 x i32> %784, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >		; <<4 x i32>>:785 [#uses=0]
 	icmp eq i32 0, 0		; <i1>:786 [#uses=0]
 	br label %xST.exit431
 
 xST.exit431:		; preds = %780, %777
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:787 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:788 [#uses=0]
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:789 [#uses=2]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:787 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:788 [#uses=0]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:789 [#uses=2]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %789, <4 x i32> zeroinitializer )		; <i32>:790 [#uses=1]
 	icmp eq i32 %790, 0		; <i1>:791 [#uses=0]
 	shufflevector <4 x i32> %789, <4 x i32> undef, <4 x i32> zeroinitializer		; <<4 x i32>>:792 [#uses=1]
@@ -872,7 +872,7 @@ xST.exit431:		; preds = %780, %777
 	br i1 %794, label %797, label %795
 
 ; <label>:795		; preds = %xST.exit431
-	load <4 x float>* null		; <<4 x float>>:796 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:796 [#uses=0]
 	store <4 x float> zeroinitializer, <4 x float>* null
 	br label %797
 
@@ -882,38 +882,38 @@ xST.exit431:		; preds = %780, %777
 	br i1 false, label %xST.exit434, label %799
 
 ; <label>:799		; preds = %797
-	load <4 x float>* null		; <<4 x float>>:800 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:800 [#uses=0]
 	store <4 x float> zeroinitializer, <4 x float>* null
 	br label %xST.exit434
 
 xST.exit434:		; preds = %799, %797
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:801 [#uses=1]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:801 [#uses=1]
 	shufflevector <4 x i32> %801, <4 x i32> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 >		; <<4 x i32>>:802 [#uses=0]
 	shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >		; <<4 x i32>>:803 [#uses=0]
 	icmp eq i32 0, 0		; <i1>:804 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 0		; <<4 x float>*>:805 [#uses=1]
-	load <4 x float>* %805		; <<4 x float>>:806 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1		; <<4 x float>*>:807 [#uses=1]
-	load <4 x float>* %807		; <<4 x float>>:808 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:809 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:810 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0		; <<4 x float>*>:811 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2		; <<4 x float>*>:812 [#uses=1]
-	load <4 x float>* %812		; <<4 x float>>:813 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3		; <<4 x float>*>:814 [#uses=1]
-	load <4 x float>* %814		; <<4 x float>>:815 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 0		; <<4 x float>*>:805 [#uses=1]
+	load <4 x float>, <4 x float>* %805		; <<4 x float>>:806 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1		; <<4 x float>*>:807 [#uses=1]
+	load <4 x float>, <4 x float>* %807		; <<4 x float>>:808 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:809 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:810 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0		; <<4 x float>*>:811 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2		; <<4 x float>*>:812 [#uses=1]
+	load <4 x float>, <4 x float>* %812		; <<4 x float>>:813 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3		; <<4 x float>*>:814 [#uses=1]
+	load <4 x float>, <4 x float>* %814		; <<4 x float>>:815 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:816 [#uses=0]
 	unreachable
 
 xPBRK.exit:		; preds = %.critedge
 	store <4 x i32> < i32 -1, i32 -1, i32 -1, i32 -1 >, <4 x i32>* %.sub7896
 	store <4 x i32> zeroinitializer, <4 x i32>* null
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 1		; <<4 x float>*>:817 [#uses=1]
-	load <4 x float>* %817		; <<4 x float>>:818 [#uses=1]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2		; <<4 x float>*>:819 [#uses=1]
-	load <4 x float>* %819		; <<4 x float>>:820 [#uses=1]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3		; <<4 x float>*>:821 [#uses=1]
-	load <4 x float>* %821		; <<4 x float>>:822 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 1		; <<4 x float>*>:817 [#uses=1]
+	load <4 x float>, <4 x float>* %817		; <<4 x float>>:818 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2		; <<4 x float>*>:819 [#uses=1]
+	load <4 x float>, <4 x float>* %819		; <<4 x float>>:820 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3		; <<4 x float>*>:821 [#uses=1]
+	load <4 x float>, <4 x float>* %821		; <<4 x float>>:822 [#uses=1]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:823 [#uses=1]
 	shufflevector <4 x float> %818, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:824 [#uses=1]
 	shufflevector <4 x float> %820, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:825 [#uses=1]
@@ -921,10 +921,10 @@ xPBRK.exit:		; preds = %.critedge
 	shufflevector <4 x float> %823, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:827 [#uses=0]
 	shufflevector <4 x float> %824, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:828 [#uses=1]
 	store <4 x float> %828, <4 x float>* null
-	load <4 x float>* null		; <<4 x float>>:829 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:829 [#uses=1]
 	shufflevector <4 x float> %825, <4 x float> %829, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:830 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3		; <<4 x float>*>:831 [#uses=2]
-	load <4 x float>* %831		; <<4 x float>>:832 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3		; <<4 x float>*>:831 [#uses=2]
+	load <4 x float>, <4 x float>* %831		; <<4 x float>>:832 [#uses=1]
 	shufflevector <4 x float> %826, <4 x float> %832, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:833 [#uses=1]
 	store <4 x float> %833, <4 x float>* %831
 	br label %xLS.exit449
@@ -958,14 +958,14 @@ xLS.exit449:		; preds = %1215, %xPBRK.exit
 	%.17731 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07730, %1215 ]		; <<4 x float>> [#uses=2]
 	%.17735 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07734, %1215 ]		; <<4 x float>> [#uses=2]
 	%.17770 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07769, %1215 ]		; <<4 x float>> [#uses=2]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 0		; <<4 x float>*>:834 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:835 [#uses=1]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2		; <<4 x float>*>:836 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3		; <<4 x float>*>:837 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 0		; <<4 x float>*>:834 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:835 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2		; <<4 x float>*>:836 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3		; <<4 x float>*>:837 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:838 [#uses=0]
 	shufflevector <4 x float> %835, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:839 [#uses=1]
-	getelementptr <4 x float>* null, i32 878		; <<4 x float>*>:840 [#uses=1]
-	load <4 x float>* %840		; <<4 x float>>:841 [#uses=0]
+	getelementptr <4 x float>, <4 x float>* null, i32 878		; <<4 x float>*>:840 [#uses=1]
+	load <4 x float>, <4 x float>* %840		; <<4 x float>>:841 [#uses=0]
 	call <4 x float> @llvm.ppc.altivec.vcfsx( <4 x i32> zeroinitializer, i32 0 )		; <<4 x float>>:842 [#uses=1]
 	shufflevector <4 x float> %842, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:843 [#uses=2]
 	call <4 x i32> @llvm.ppc.altivec.vcmpgtfp( <4 x float> %843, <4 x float> %839 )		; <<4 x i32>>:844 [#uses=1]
@@ -977,7 +977,7 @@ xLS.exit449:		; preds = %1215, %xPBRK.exit
 
 ; <label>:849		; preds = %xLS.exit449
 	shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:850 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1		; <<4 x float>*>:851 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1		; <<4 x float>*>:851 [#uses=1]
 	store <4 x float> zeroinitializer, <4 x float>* %851
 	shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:852 [#uses=1]
 	store <4 x float> %852, <4 x float>* null
@@ -989,8 +989,8 @@ xLS.exit449:		; preds = %1215, %xPBRK.exit
 	br i1 false, label %859, label %856
 
 ; <label>:856		; preds = %854
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0		; <<4 x float>*>:857 [#uses=2]
-	load <4 x float>* %857		; <<4 x float>>:858 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0		; <<4 x float>*>:857 [#uses=2]
+	load <4 x float>, <4 x float>* %857		; <<4 x float>>:858 [#uses=0]
 	store <4 x float> zeroinitializer, <4 x float>* %857
 	br label %859
 
@@ -999,13 +999,13 @@ xLS.exit449:		; preds = %1215, %xPBRK.exit
 	br i1 false, label %864, label %861
 
 ; <label>:861		; preds = %859
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1		; <<4 x float>*>:862 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1		; <<4 x float>*>:862 [#uses=1]
 	shufflevector <4 x float> %845, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:863 [#uses=1]
 	store <4 x float> %863, <4 x float>* %862
 	br label %864
 
 ; <label>:864		; preds = %861, %859
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:865 [#uses=1]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:865 [#uses=1]
 	shufflevector <4 x i32> %865, <4 x i32> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 >		; <<4 x i32>>:866 [#uses=0]
 	br i1 false, label %868, label %867
 
@@ -1018,9 +1018,9 @@ xLS.exit449:		; preds = %1215, %xPBRK.exit
 	br label %xST.exit451
 
 xST.exit451:		; preds = %868, %849
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0		; <<4 x float>*>:870 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1		; <<4 x float>*>:871 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:872 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0		; <<4 x float>*>:870 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1		; <<4 x float>*>:871 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:872 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:873 [#uses=1]
 	bitcast <4 x float> zeroinitializer to <4 x i32>		; <<4 x i32>>:874 [#uses=1]
 	xor <4 x i32> %874, < i32 -1, i32 -1, i32 -1, i32 -1 >		; <<4 x i32>>:875 [#uses=0]
@@ -1029,16 +1029,16 @@ xST.exit451:		; preds = %868, %849
 	bitcast <4 x float> zeroinitializer to <4 x i32>		; <<4 x i32>>:878 [#uses=1]
 	xor <4 x i32> %878, < i32 -1, i32 -1, i32 -1, i32 -1 >		; <<4 x i32>>:879 [#uses=1]
 	bitcast <4 x i32> %879 to <4 x float>		; <<4 x float>>:880 [#uses=0]
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:881 [#uses=1]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:881 [#uses=1]
 	icmp eq i32 0, 0		; <i1>:882 [#uses=1]
 	br i1 %882, label %888, label %883
 
 ; <label>:883		; preds = %xST.exit451
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0		; <<4 x float>*>:884 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0		; <<4 x float>*>:884 [#uses=1]
 	store <4 x float> zeroinitializer, <4 x float>* %884
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1		; <<4 x float>*>:885 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1		; <<4 x float>*>:885 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:886 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3		; <<4 x float>*>:887 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3		; <<4 x float>*>:887 [#uses=0]
 	br label %xST.exit453
 
 ; <label>:888		; preds = %xST.exit451
@@ -1047,7 +1047,7 @@ xST.exit451:		; preds = %868, %849
 	br i1 false, label %894, label %891
 
 ; <label>:891		; preds = %888
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1		; <<4 x float>*>:892 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1		; <<4 x float>*>:892 [#uses=1]
 	shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:893 [#uses=1]
 	store <4 x float> %893, <4 x float>* %892
 	br label %894
@@ -1061,34 +1061,34 @@ xST.exit451:		; preds = %868, %849
 	br label %898
 
 ; <label>:898		; preds = %897, %894
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:899 [#uses=0]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:899 [#uses=0]
 	br i1 false, label %xST.exit453, label %900
 
 ; <label>:900		; preds = %898
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3		; <<4 x float>*>:901 [#uses=1]
-	load <4 x float>* %901		; <<4 x float>>:902 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3		; <<4 x float>*>:901 [#uses=1]
+	load <4 x float>, <4 x float>* %901		; <<4 x float>>:902 [#uses=1]
 	shufflevector <4 x float> zeroinitializer, <4 x float> %902, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:903 [#uses=0]
 	br label %xST.exit453
 
 xST.exit453:		; preds = %900, %898, %883
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1		; <<4 x float>*>:904 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:905 [#uses=1]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3		; <<4 x float>*>:906 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1		; <<4 x float>*>:904 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:905 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3		; <<4 x float>*>:906 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:907 [#uses=1]
 	shufflevector <4 x float> %905, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:908 [#uses=1]
 	bitcast <4 x float> zeroinitializer to <4 x i32>		; <<4 x i32>>:909 [#uses=0]
 	bitcast <4 x float> %908 to <4 x i32>		; <<4 x i32>>:910 [#uses=0]
 	bitcast <4 x float> %907 to <4 x i32>		; <<4 x i32>>:911 [#uses=0]
 	bitcast <4 x float> zeroinitializer to <4 x i32>		; <<4 x i32>>:912 [#uses=0]
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:913 [#uses=0]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:913 [#uses=0]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 2, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer )		; <i32>:914 [#uses=0]
 	br i1 false, label %915, label %xPIF.exit455
 
 ; <label>:915		; preds = %xST.exit453
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:916 [#uses=0]
-	getelementptr [4 x <4 x i32>]* null, i32 0, i32 3		; <<4 x i32>*>:917 [#uses=1]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:916 [#uses=0]
+	getelementptr [4 x <4 x i32>], [4 x <4 x i32>]* null, i32 0, i32 3		; <<4 x i32>*>:917 [#uses=1]
 	store <4 x i32> zeroinitializer, <4 x i32>* %917
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:918 [#uses=1]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:918 [#uses=1]
 	and <4 x i32> %918, zeroinitializer		; <<4 x i32>>:919 [#uses=0]
 	br label %.critedge7899
 
@@ -1101,16 +1101,16 @@ xPBRK.exit456:		; preds = %.critedge7899
 	unreachable
 
 xPIF.exit455:		; preds = %xST.exit453
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 0		; <<4 x float>*>:922 [#uses=1]
-	load <4 x float>* %922		; <<4 x float>>:923 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 1		; <<4 x float>*>:924 [#uses=1]
-	load <4 x float>* %924		; <<4 x float>>:925 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2		; <<4 x float>*>:926 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3		; <<4 x float>*>:927 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 0		; <<4 x float>*>:922 [#uses=1]
+	load <4 x float>, <4 x float>* %922		; <<4 x float>>:923 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 1		; <<4 x float>*>:924 [#uses=1]
+	load <4 x float>, <4 x float>* %924		; <<4 x float>>:925 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2		; <<4 x float>*>:926 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3		; <<4 x float>*>:927 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:928 [#uses=0]
 	bitcast { { i16, i16, i32 } }* %1 to <4 x float>*		; <<4 x float>*>:929 [#uses=0]
 	bitcast <4 x float> zeroinitializer to <4 x i32>		; <<4 x i32>>:930 [#uses=0]
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:931 [#uses=0]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:931 [#uses=0]
 	icmp eq i32 0, 0		; <i1>:932 [#uses=1]
 	br i1 %932, label %934, label %933
 
@@ -1129,13 +1129,13 @@ xPIF.exit455:		; preds = %xST.exit453
 xST.exit459:		; preds = %937, %934
 	shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 >		; <<4 x i32>>:938 [#uses=1]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %938, <4 x i32> zeroinitializer )		; <i32>:939 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 2		; <<4 x float>*>:940 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 2		; <<4 x float>*>:940 [#uses=1]
 	store <4 x float> zeroinitializer, <4 x float>* %940
-	load <4 x float>* null		; <<4 x float>>:941 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:941 [#uses=1]
 	shufflevector <4 x float> zeroinitializer, <4 x float> %941, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:942 [#uses=1]
 	store <4 x float> %942, <4 x float>* null
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:943 [#uses=0]
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:944 [#uses=0]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:944 [#uses=0]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer )		; <i32>:945 [#uses=0]
 	br i1 false, label %947, label %946
 
@@ -1156,7 +1156,7 @@ xST.exit459:		; preds = %937, %934
 	br i1 false, label %955, label %953
 
 ; <label>:953		; preds = %952
-	getelementptr [4 x <4 x i32>]* null, i32 0, i32 2		; <<4 x i32>*>:954 [#uses=0]
+	getelementptr [4 x <4 x i32>], [4 x <4 x i32>]* null, i32 0, i32 2		; <<4 x i32>*>:954 [#uses=0]
 	br label %955
 
 ; <label>:955		; preds = %953, %952
@@ -1170,16 +1170,16 @@ xST.exit459:		; preds = %937, %934
 	br label %xStoreDestAddressWithMask.exit461
 
 xStoreDestAddressWithMask.exit461:		; preds = %958, %955
-	load <4 x float>* %0		; <<4 x float>>:960 [#uses=0]
+	load <4 x float>, <4 x float>* %0		; <<4 x float>>:960 [#uses=0]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer )		; <i32>:961 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 0		; <<4 x float>*>:962 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 0		; <<4 x float>*>:962 [#uses=0]
 	br i1 false, label %968, label %xST.exit463
 
 xST.exit463:		; preds = %xStoreDestAddressWithMask.exit461
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 1		; <<4 x float>*>:963 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 2		; <<4 x float>*>:964 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 3		; <<4 x float>*>:965 [#uses=0]
-	load <4 x float>* %0		; <<4 x float>>:966 [#uses=3]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 1		; <<4 x float>*>:963 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 2		; <<4 x float>*>:964 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 3		; <<4 x float>*>:965 [#uses=0]
+	load <4 x float>, <4 x float>* %0		; <<4 x float>>:966 [#uses=3]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer )		; <i32>:967 [#uses=0]
 	br i1 false, label %972, label %969
 
@@ -1187,8 +1187,8 @@ xST.exit463:		; preds = %xStoreDestAddressWithMask.exit461
 	unreachable
 
 ; <label>:969		; preds = %xST.exit463
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 1		; <<4 x float>*>:970 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 2		; <<4 x float>*>:971 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 1		; <<4 x float>*>:970 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 2		; <<4 x float>*>:971 [#uses=1]
 	store <4 x float> %966, <4 x float>* %971
 	store <4 x float> %966, <4 x float>* null
 	br label %xST.exit465
@@ -1197,39 +1197,39 @@ xST.exit463:		; preds = %xStoreDestAddressWithMask.exit461
 	call <4 x i32> @llvm.ppc.altivec.vsel( <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer )		; <<4 x i32>>:973 [#uses=0]
 	store <4 x float> zeroinitializer, <4 x float>* null
 	store <4 x float> zeroinitializer, <4 x float>* null
-	load <4 x float>* null		; <<4 x float>>:974 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:974 [#uses=0]
 	bitcast <4 x float> %966 to <4 x i32>		; <<4 x i32>>:975 [#uses=1]
 	call <4 x i32> @llvm.ppc.altivec.vsel( <4 x i32> zeroinitializer, <4 x i32> %975, <4 x i32> zeroinitializer )		; <<4 x i32>>:976 [#uses=1]
 	bitcast <4 x i32> %976 to <4 x float>		; <<4 x float>>:977 [#uses=1]
 	store <4 x float> %977, <4 x float>* null
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 3		; <<4 x float>*>:978 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 3		; <<4 x float>*>:978 [#uses=0]
 	bitcast <4 x float> zeroinitializer to <4 x i32>		; <<4 x i32>>:979 [#uses=1]
 	call <4 x i32> @llvm.ppc.altivec.vsel( <4 x i32> %979, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer )		; <<4 x i32>>:980 [#uses=1]
 	bitcast <4 x i32> %980 to <4 x float>		; <<4 x float>>:981 [#uses=0]
 	br label %xST.exit465
 
 xST.exit465:		; preds = %972, %969
-	load <4 x float>* %0		; <<4 x float>>:982 [#uses=3]
+	load <4 x float>, <4 x float>* %0		; <<4 x float>>:982 [#uses=3]
 	icmp eq i32 0, 0		; <i1>:983 [#uses=1]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0		; <<4 x float>*>:984 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0		; <<4 x float>*>:984 [#uses=1]
 	br i1 %983, label %989, label %985
 
 ; <label>:985		; preds = %xST.exit465
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1		; <<4 x float>*>:986 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2		; <<4 x float>*>:987 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1		; <<4 x float>*>:986 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2		; <<4 x float>*>:987 [#uses=1]
 	store <4 x float> %982, <4 x float>* %987
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3		; <<4 x float>*>:988 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3		; <<4 x float>*>:988 [#uses=0]
 	br label %xST.exit467
 
 ; <label>:989		; preds = %xST.exit465
 	bitcast <4 x float> %982 to <4 x i32>		; <<4 x i32>>:990 [#uses=0]
 	shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> zeroinitializer		; <<4 x i32>>:991 [#uses=0]
 	store <4 x float> zeroinitializer, <4 x float>* %984
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1		; <<4 x float>*>:992 [#uses=0]
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:993 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2		; <<4 x float>*>:994 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1		; <<4 x float>*>:992 [#uses=0]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:993 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2		; <<4 x float>*>:994 [#uses=0]
 	bitcast <4 x i32> zeroinitializer to <4 x float>		; <<4 x float>>:995 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3		; <<4 x float>*>:996 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3		; <<4 x float>*>:996 [#uses=0]
 	bitcast <4 x float> zeroinitializer to <4 x i32>		; <<4 x i32>>:997 [#uses=1]
 	bitcast <4 x float> %982 to <4 x i32>		; <<4 x i32>>:998 [#uses=1]
 	shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >		; <<4 x i32>>:999 [#uses=1]
@@ -1238,17 +1238,17 @@ xST.exit465:		; preds = %972, %969
 	br label %xST.exit467
 
 xST.exit467:		; preds = %989, %985
-	load <4 x float>* %0		; <<4 x float>>:1002 [#uses=5]
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:1003 [#uses=2]
+	load <4 x float>, <4 x float>* %0		; <<4 x float>>:1002 [#uses=5]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:1003 [#uses=2]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %1003, <4 x i32> zeroinitializer )		; <i32>:1004 [#uses=0]
 	br i1 false, label %1011, label %1005
 
 ; <label>:1005		; preds = %xST.exit467
-	load <4 x float>* null		; <<4 x float>>:1006 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1		; <<4 x float>*>:1007 [#uses=1]
-	load <4 x float>* %1007		; <<4 x float>>:1008 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:1009 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:1010 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:1006 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1		; <<4 x float>*>:1007 [#uses=1]
+	load <4 x float>, <4 x float>* %1007		; <<4 x float>>:1008 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:1009 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:1010 [#uses=0]
 	br label %xST.exit469
 
 ; <label>:1011		; preds = %xST.exit467
@@ -1266,7 +1266,7 @@ xST.exit467:		; preds = %989, %985
 	br i1 %1017, label %1021, label %1018
 
 ; <label>:1018		; preds = %1015
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1		; <<4 x float>*>:1019 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1		; <<4 x float>*>:1019 [#uses=0]
 	shufflevector <4 x float> %1002, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 >		; <<4 x float>>:1020 [#uses=0]
 	br label %1021
 
@@ -1276,7 +1276,7 @@ xST.exit467:		; preds = %989, %985
 	br i1 %1022, label %1025, label %1023
 
 ; <label>:1023		; preds = %1021
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:1024 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:1024 [#uses=1]
 	store <4 x float> zeroinitializer, <4 x float>* %1024
 	br label %1025
 
@@ -1286,23 +1286,23 @@ xST.exit467:		; preds = %989, %985
 	br i1 %1026, label %xST.exit469, label %1027
 
 ; <label>:1027		; preds = %1025
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:1028 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:1028 [#uses=0]
 	br label %xST.exit469
 
 xST.exit469:		; preds = %1027, %1025, %1005
 	%.17463 = phi <4 x float> [ %.27464, %1005 ], [ %.07462, %1027 ], [ %.07462, %1025 ]		; <<4 x float>> [#uses=1]
 	%.17468 = phi <4 x float> [ %.27469, %1005 ], [ %.07467, %1027 ], [ %.07467, %1025 ]		; <<4 x float>> [#uses=1]
 	%.07489 = phi <4 x float> [ %1002, %1005 ], [ %.17490, %1027 ], [ %.17490, %1025 ]		; <<4 x float>> [#uses=1]
-	load <4 x float>* null		; <<4 x float>>:1029 [#uses=0]
-	load <4 x float>* null		; <<4 x float>>:1030 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:1029 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:1030 [#uses=0]
 	fsub <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:1031 [#uses=1]
 	br i1 false, label %1037, label %1032
 
 ; <label>:1032		; preds = %xST.exit469
-	load <4 x float>* null		; <<4 x float>>:1033 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:1034 [#uses=1]
-	load <4 x float>* %1034		; <<4 x float>>:1035 [#uses=0]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:1036 [#uses=0]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:1033 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:1034 [#uses=1]
+	load <4 x float>, <4 x float>* %1034		; <<4 x float>>:1035 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:1036 [#uses=0]
 	br label %xST.exit472
 
 ; <label>:1037		; preds = %xST.exit469
@@ -1318,8 +1318,8 @@ xST.exit469:		; preds = %1027, %1025, %1005
 	br i1 %1041, label %1045, label %1042
 
 ; <label>:1042		; preds = %1040
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1		; <<4 x float>*>:1043 [#uses=1]
-	load <4 x float>* %1043		; <<4 x float>>:1044 [#uses=0]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1		; <<4 x float>*>:1043 [#uses=1]
+	load <4 x float>, <4 x float>* %1043		; <<4 x float>>:1044 [#uses=0]
 	br label %1045
 
 ; <label>:1045		; preds = %1042, %1040
@@ -1367,7 +1367,7 @@ xST.exit472:		; preds = %1050, %1048, %1032
 	br label %xST.exit474
 
 xST.exit474:		; preds = %1059, %1058, %1051
-	load <4 x float>* null		; <<4 x float>>:1060 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:1060 [#uses=1]
 	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:1061 [#uses=1]
 	fmul <4 x float> %1060, zeroinitializer		; <<4 x float>>:1062 [#uses=2]
 	br i1 false, label %1065, label %1063
@@ -1555,7 +1555,7 @@ xST.exit489:		; preds = %1109, %1108, %1101
 	br label %xST.exit492
 
 xST.exit492:		; preds = %1118, %1117, %1110
-	load <4 x float>* null		; <<4 x float>>:1119 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:1119 [#uses=1]
 	fmul <4 x float> %1119, zeroinitializer		; <<4 x float>>:1120 [#uses=1]
 	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:1121 [#uses=1]
 	br i1 false, label %1123, label %1122
@@ -1590,7 +1590,7 @@ xST.exit492:		; preds = %1118, %1117, %1110
 xST.exit495:		; preds = %1130, %1129, %1122
 	%.07582 = phi <4 x float> [ %1121, %1122 ], [ %.17583, %1130 ], [ %.17583, %1129 ]		; <<4 x float>> [#uses=1]
 	%.07590 = phi <4 x float> [ %1120, %1122 ], [ %.17591, %1130 ], [ %.17591, %1129 ]		; <<4 x float>> [#uses=1]
-	load <4 x float>* null		; <<4 x float>>:1131 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:1131 [#uses=1]
 	fadd <4 x float> %1131, zeroinitializer		; <<4 x float>>:1132 [#uses=1]
 	fadd <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:1133 [#uses=1]
 	br i1 false, label %1135, label %1134
@@ -1625,11 +1625,11 @@ xST.exit495:		; preds = %1130, %1129, %1122
 xST.exit498:		; preds = %1142, %1141, %1134
 	%.07617 = phi <4 x float> [ %1133, %1134 ], [ %.17618, %1142 ], [ %.17618, %1141 ]		; <<4 x float>> [#uses=1]
 	%.07621 = phi <4 x float> [ %1132, %1134 ], [ %.17622, %1142 ], [ %.17622, %1141 ]		; <<4 x float>> [#uses=1]
-	load <4 x float>* null		; <<4 x float>>:1143 [#uses=1]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:1144 [#uses=1]
-	load <4 x float>* %1144		; <<4 x float>>:1145 [#uses=1]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:1146 [#uses=1]
-	load <4 x float>* %1146		; <<4 x float>>:1147 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:1143 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:1144 [#uses=1]
+	load <4 x float>, <4 x float>* %1144		; <<4 x float>>:1145 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:1146 [#uses=1]
+	load <4 x float>, <4 x float>* %1146		; <<4 x float>>:1147 [#uses=1]
 	shufflevector <4 x float> %1143, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:1148 [#uses=1]
 	shufflevector <4 x float> %1145, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:1149 [#uses=1]
 	shufflevector <4 x float> %1147, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:1150 [#uses=1]
@@ -1671,11 +1671,11 @@ xST.exit501:		; preds = %1163, %1162, %1155
 	%.07656 = phi <4 x float> [ %1153, %1155 ], [ %.17657, %1163 ], [ %.17657, %1162 ]		; <<4 x float>> [#uses=1]
 	%.07660 = phi <4 x float> [ %1152, %1155 ], [ %.17661, %1163 ], [ %.17661, %1162 ]		; <<4 x float>> [#uses=1]
 	%.07664 = phi <4 x float> [ %1151, %1155 ], [ %.17665, %1163 ], [ %.17665, %1162 ]		; <<4 x float>> [#uses=1]
-	load <4 x float>* null		; <<4 x float>>:1164 [#uses=1]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:1165 [#uses=1]
-	load <4 x float>* %1165		; <<4 x float>>:1166 [#uses=1]
-	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:1167 [#uses=1]
-	load <4 x float>* %1167		; <<4 x float>>:1168 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:1164 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:1165 [#uses=1]
+	load <4 x float>, <4 x float>* %1165		; <<4 x float>>:1166 [#uses=1]
+	getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3		; <<4 x float>*>:1167 [#uses=1]
+	load <4 x float>, <4 x float>* %1167		; <<4 x float>>:1168 [#uses=1]
 	fadd <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:1169 [#uses=1]
 	fadd <4 x float> zeroinitializer, %1164		; <<4 x float>>:1170 [#uses=1]
 	fadd <4 x float> zeroinitializer, %1166		; <<4 x float>>:1171 [#uses=1]
@@ -1734,21 +1734,21 @@ xST.exit504:		; preds = %1181, %1180, %1173
 	br label %1188
 
 ; <label>:1188		; preds = %1187, %1186
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:1189 [#uses=1]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:1189 [#uses=1]
 	shufflevector <4 x i32> %1189, <4 x i32> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 >		; <<4 x i32>>:1190 [#uses=1]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %1190, <4 x i32> zeroinitializer )		; <i32>:1191 [#uses=1]
 	icmp eq i32 %1191, 0		; <i1>:1192 [#uses=1]
 	br i1 %1192, label %1196, label %1193
 
 ; <label>:1193		; preds = %1188
-	load <4 x float>* null		; <<4 x float>>:1194 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:1194 [#uses=1]
 	shufflevector <4 x float> zeroinitializer, <4 x float> %1194, <4 x i32> < i32 0, i32 1, i32 2, i32 7 >		; <<4 x float>>:1195 [#uses=1]
 	store <4 x float> %1195, <4 x float>* null
 	br label %1196
 
 ; <label>:1196		; preds = %1193, %1188
 	%.07742 = phi <4 x float> [ zeroinitializer, %1193 ], [ zeroinitializer, %1188 ]		; <<4 x float>> [#uses=0]
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:1197 [#uses=1]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:1197 [#uses=1]
 	shufflevector <4 x i32> %1197, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >		; <<4 x i32>>:1198 [#uses=1]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %1198, <4 x i32> zeroinitializer )		; <i32>:1199 [#uses=1]
 	icmp eq i32 %1199, 0		; <i1>:1200 [#uses=1]
@@ -1765,20 +1765,20 @@ xST.exit507:		; preds = %1201, %1196, %1183
 	br i1 %1203, label %1207, label %1204
 
 ; <label>:1204		; preds = %xST.exit507
-	load <4 x float>* null		; <<4 x float>>:1205 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:1205 [#uses=1]
 	shufflevector <4 x float> zeroinitializer, <4 x float> %1205, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:1206 [#uses=1]
 	store <4 x float> %1206, <4 x float>* null
 	br label %1207
 
 ; <label>:1207		; preds = %1204, %xST.exit507
-	load <4 x i32>* %.sub7896		; <<4 x i32>>:1208 [#uses=1]
+	load <4 x i32>, <4 x i32>* %.sub7896		; <<4 x i32>>:1208 [#uses=1]
 	shufflevector <4 x i32> %1208, <4 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >		; <<4 x i32>>:1209 [#uses=1]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %1209, <4 x i32> zeroinitializer )		; <i32>:1210 [#uses=1]
 	icmp eq i32 %1210, 0		; <i1>:1211 [#uses=1]
 	br i1 %1211, label %1215, label %1212
 
 ; <label>:1212		; preds = %1207
-	load <4 x float>* null		; <<4 x float>>:1213 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:1213 [#uses=1]
 	shufflevector <4 x float> zeroinitializer, <4 x float> %1213, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >		; <<4 x float>>:1214 [#uses=1]
 	store <4 x float> %1214, <4 x float>* null
 	br label %1215
diff --git a/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll b/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
index 53231b4f435e..017775781f7d 100644
--- a/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
+++ b/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
@@ -22,7 +22,7 @@ define i64 @test(i32 %A, i32 %B, i32 %C) nounwind {
 entry:
 	%Y = alloca i32, align 4		; <i32*> [#uses=2]
 	%tmp4 = call i32 asm "subf${3:I}c $1,$4,$3\0A\09subfze $0,$2", "=r,=*&r,r,rI,r"( i32* %Y, i32 %A, i32 %B, i32 %C )		; <i32> [#uses=1]
-	%tmp5 = load i32* %Y		; <i32> [#uses=1]
+	%tmp5 = load i32, i32* %Y		; <i32> [#uses=1]
 	%tmp56 = zext i32 %tmp5 to i64		; <i64> [#uses=1]
 	%tmp7 = shl i64 %tmp56, 32		; <i64> [#uses=1]
 	%tmp89 = zext i32 %tmp4 to i64		; <i64> [#uses=1]
diff --git a/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll b/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll
index 490aa0c1442c..c5721560d382 100644
--- a/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll
+++ b/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll
@@ -7,6 +7,6 @@ target triple = "powerpc-apple-darwin8.8.0"
 
 define void @foo() {
 entry:
-	tail call void asm sideeffect "$0 $1", "s,i"( i8* bitcast (i32* getelementptr ([2 x i32]* @x, i32 0, i32 1) to i8*), i8* bitcast (i32* getelementptr ([2 x i32]* @x, i32 0, i32 1) to i8*) )
+	tail call void asm sideeffect "$0 $1", "s,i"( i8* bitcast (i32* getelementptr ([2 x i32], [2 x i32]* @x, i32 0, i32 1) to i8*), i8* bitcast (i32* getelementptr ([2 x i32], [2 x i32]* @x, i32 0, i32 1) to i8*) )
 	ret void
 }
diff --git a/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll b/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll
index e4e931492ac4..1305c42e9320 100644
--- a/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll
+++ b/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll
@@ -12,7 +12,7 @@ entry:
 
 bb:		; preds = %bb, %entry
 	%i.035.0 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]		; <i32> [#uses=2]
-	%tmp8 = getelementptr float* %tmp56, i32 %i.035.0		; <float*> [#uses=2]
+	%tmp8 = getelementptr float, float* %tmp56, i32 %i.035.0		; <float*> [#uses=2]
 	%tmp101112 = bitcast float* %tmp8 to i8*		; <i8*> [#uses=1]
 	%tmp1617 = bitcast float* %tmp8 to i32*		; <i32*> [#uses=1]
 	%tmp21 = tail call i32 asm "lwbrx $0, $2, $1", "=r,r,bO,*m"( i8* %tmp101112, i32 0, i32* %tmp1617 )		; <i32> [#uses=0]
diff --git a/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll b/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll
index 382ba1f6a82d..b3b73238420d 100644
--- a/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll
+++ b/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll
@@ -15,46 +15,46 @@ entry:
 	%retval = alloca i32, align 4		; <i32*> [#uses=1]
 	store i32 %i, i32* %i_addr
 	store i32 %q, i32* %q_addr
-	%tmp = load i32* %i_addr		; <i32> [#uses=1]
+	%tmp = load i32, i32* %i_addr		; <i32> [#uses=1]
 	%tmp1 = icmp ne i32 %tmp, 0		; <i1> [#uses=1]
 	%tmp12 = zext i1 %tmp1 to i8		; <i8> [#uses=1]
 	%toBool = icmp ne i8 %tmp12, 0		; <i1> [#uses=1]
 	br i1 %toBool, label %cond_true, label %cond_false
 
 cond_true:		; preds = %entry
-	%tmp3 = call i32 (...)* @bar( )		; <i32> [#uses=0]
-	%tmp4 = call i32 (...)* @baz( i32 5, i32 6 )		; <i32> [#uses=0]
-	%tmp7 = load i32* %q_addr		; <i32> [#uses=1]
+	%tmp3 = call i32 (...) @bar( )		; <i32> [#uses=0]
+	%tmp4 = call i32 (...) @baz( i32 5, i32 6 )		; <i32> [#uses=0]
+	%tmp7 = load i32, i32* %q_addr		; <i32> [#uses=1]
 	%tmp8 = icmp ne i32 %tmp7, 0		; <i1> [#uses=1]
 	%tmp89 = zext i1 %tmp8 to i8		; <i8> [#uses=1]
 	%toBool10 = icmp ne i8 %tmp89, 0		; <i1> [#uses=1]
 	br i1 %toBool10, label %cond_true11, label %cond_false15
 
 cond_false:		; preds = %entry
-	%tmp5 = call i32 (...)* @foo( )		; <i32> [#uses=0]
-	%tmp6 = call i32 (...)* @baz( i32 5, i32 6 )		; <i32> [#uses=0]
-	%tmp27 = load i32* %q_addr		; <i32> [#uses=1]
+	%tmp5 = call i32 (...) @foo( )		; <i32> [#uses=0]
+	%tmp6 = call i32 (...) @baz( i32 5, i32 6 )		; <i32> [#uses=0]
+	%tmp27 = load i32, i32* %q_addr		; <i32> [#uses=1]
 	%tmp28 = icmp ne i32 %tmp27, 0		; <i1> [#uses=1]
 	%tmp289 = zext i1 %tmp28 to i8		; <i8> [#uses=1]
 	%toBool210 = icmp ne i8 %tmp289, 0		; <i1> [#uses=1]
 	br i1 %toBool210, label %cond_true11, label %cond_false15
 
 cond_true11:		; preds = %cond_next
-	%tmp13 = call i32 (...)* @foo( )		; <i32> [#uses=0]
-	%tmp14 = call i32 (...)* @quux( i32 3, i32 4 )		; <i32> [#uses=0]
+	%tmp13 = call i32 (...) @foo( )		; <i32> [#uses=0]
+	%tmp14 = call i32 (...) @quux( i32 3, i32 4 )		; <i32> [#uses=0]
 	br label %cond_next18
 
 cond_false15:		; preds = %cond_next
-	%tmp16 = call i32 (...)* @bar( )		; <i32> [#uses=0]
-	%tmp17 = call i32 (...)* @quux( i32 3, i32 4 )		; <i32> [#uses=0]
+	%tmp16 = call i32 (...) @bar( )		; <i32> [#uses=0]
+	%tmp17 = call i32 (...) @quux( i32 3, i32 4 )		; <i32> [#uses=0]
 	br label %cond_next18
 
 cond_next18:		; preds = %cond_false15, %cond_true11
-	%tmp19 = call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp19 = call i32 (...) @bar( )		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %cond_next18
-	%retval20 = load i32* %retval		; <i32> [#uses=1]
+	%retval20 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval20
 }
 
diff --git a/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll b/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll
index 6de7a09128f0..7a8eb175a93a 100644
--- a/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll
+++ b/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll
@@ -70,7 +70,7 @@ declare i32 @llvm.ppc.altivec.vcmpequw.p(i32, <4 x i32>, <4 x i32>)
 
 define void @test(%struct.XState* %gldst, <4 x float>* %prgrm, <4 x float>** %buffs, %struct._GVMConstants* %cnstn, %struct.PPSToken* %pstrm, %struct.GVMFPContext* %vmctx, %struct.GVMTs* %txtrs, %struct.GVMFPStack* %fpstk, %struct.GVMFGAttrib* %start, %struct.GVMFGAttrib* %deriv, i32 %fragx, i32 %fragy) {
 bb58.i:
-	%tmp3405.i = getelementptr %struct.XTRec* null, i32 0, i32 1		; <float*> [#uses=1]
+	%tmp3405.i = getelementptr %struct.XTRec, %struct.XTRec* null, i32 0, i32 1		; <float*> [#uses=1]
 	%tmp34053406.i = bitcast float* %tmp3405.i to i8*		; <i8*> [#uses=1]
 	%tmp3407.i = call <4 x i32> @llvm.ppc.altivec.lvewx( i8* %tmp34053406.i )		; <<4 x i32>> [#uses=0]
 	%tmp4146.i = call i32 @llvm.ppc.altivec.vcmpequw.p( i32 3, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer )		; <i32> [#uses=1]
diff --git a/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll b/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll
index 06f40d98c68c..6b88b81681cb 100644
--- a/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll
+++ b/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll
@@ -22,7 +22,7 @@ cond_true28:		; preds = %cond_false, %cond_true
 
 cond_next30:		; preds = %cond_true28, %cond_false, %cond_true
 	%iftmp.0.043.1 = phi %struct._obstack_chunk* [ %iftmp.0.043.0, %cond_true28 ], [ null, %cond_true ], [ %tmp22, %cond_false ]		; <%struct._obstack_chunk*> [#uses=1]
-	%tmp41 = getelementptr %struct._obstack_chunk* %iftmp.0.043.1, i32 0, i32 0		; <i8**> [#uses=1]
+	%tmp41 = getelementptr %struct._obstack_chunk, %struct._obstack_chunk* %iftmp.0.043.1, i32 0, i32 0		; <i8**> [#uses=1]
 	store i8* null, i8** %tmp41, align 8
 	ret i32 undef
 }
diff --git a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll
index 40f46fda468d..aae914ecc435 100644
--- a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll
+++ b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll
@@ -8,8 +8,8 @@ define void @foo() {
 entry:
         %ttype = alloca i32, align 4            ; <i32*> [#uses=1]
         %regs = alloca [1024 x %struct.__db_region], align 16           ; <[1024 x %struct.__db_region]*> [#uses=0]
-        %tmp = load i32* %ttype, align 4                ; <i32> [#uses=1]
-        %tmp1 = call i32 (...)* @bork( i32 %tmp )               ; <i32> [#uses=0]
+        %tmp = load i32, i32* %ttype, align 4                ; <i32> [#uses=1]
+        %tmp1 = call i32 (...) @bork( i32 %tmp )               ; <i32> [#uses=0]
         ret void
 
 ; CHECK: @foo
diff --git a/test/CodeGen/PowerPC/2007-09-08-unaligned.ll b/test/CodeGen/PowerPC/2007-09-08-unaligned.ll
index bdd91f345718..ccbadb4255a0 100644
--- a/test/CodeGen/PowerPC/2007-09-08-unaligned.ll
+++ b/test/CodeGen/PowerPC/2007-09-08-unaligned.ll
@@ -16,18 +16,18 @@ define i32 @foo() {
 entry:
 	%retval = alloca i32, align 4		; <i32*> [#uses=1]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
-	%tmp = getelementptr %struct.anon* @s, i32 0, i32 1		; <float*> [#uses=1]
-	%tmp1 = load float* %tmp, align 1		; <float> [#uses=1]
-	%tmp2 = getelementptr %struct.anon* @t, i32 0, i32 1		; <float*> [#uses=1]
+	%tmp = getelementptr %struct.anon, %struct.anon* @s, i32 0, i32 1		; <float*> [#uses=1]
+	%tmp1 = load float, float* %tmp, align 1		; <float> [#uses=1]
+	%tmp2 = getelementptr %struct.anon, %struct.anon* @t, i32 0, i32 1		; <float*> [#uses=1]
 	store float %tmp1, float* %tmp2, align 1
-	%tmp3 = getelementptr <{ i8, double }>* @u, i32 0, i32 1		; <double*> [#uses=1]
-	%tmp4 = load double* %tmp3, align 1		; <double> [#uses=1]
-	%tmp5 = getelementptr <{ i8, double }>* @v, i32 0, i32 1		; <double*> [#uses=1]
+	%tmp3 = getelementptr <{ i8, double }>, <{ i8, double }>* @u, i32 0, i32 1		; <double*> [#uses=1]
+	%tmp4 = load double, double* %tmp3, align 1		; <double> [#uses=1]
+	%tmp5 = getelementptr <{ i8, double }>, <{ i8, double }>* @v, i32 0, i32 1		; <double*> [#uses=1]
 	store double %tmp4, double* %tmp5, align 1
 	br label %return
 
 return:		; preds = %entry
-	%retval6 = load i32* %retval		; <i32> [#uses=1]
+	%retval6 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval6
 }
 
@@ -36,17 +36,17 @@ entry:
 	%retval = alloca i32, align 4		; <i32*> [#uses=1]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	%tmp = call i32 @foo( )		; <i32> [#uses=0]
-	%tmp1 = getelementptr %struct.anon* @t, i32 0, i32 1		; <float*> [#uses=1]
-	%tmp2 = load float* %tmp1, align 1		; <float> [#uses=1]
+	%tmp1 = getelementptr %struct.anon, %struct.anon* @t, i32 0, i32 1		; <float*> [#uses=1]
+	%tmp2 = load float, float* %tmp1, align 1		; <float> [#uses=1]
 	%tmp23 = fpext float %tmp2 to double		; <double> [#uses=1]
-	%tmp4 = getelementptr <{ i8, double }>* @v, i32 0, i32 1		; <double*> [#uses=1]
-	%tmp5 = load double* %tmp4, align 1		; <double> [#uses=1]
-	%tmp6 = getelementptr [8 x i8]* @.str, i32 0, i32 0		; <i8*> [#uses=1]
-	%tmp7 = call i32 (i8*, ...)* @printf( i8* %tmp6, double %tmp23, double %tmp5 )		; <i32> [#uses=0]
+	%tmp4 = getelementptr <{ i8, double }>, <{ i8, double }>* @v, i32 0, i32 1		; <double*> [#uses=1]
+	%tmp5 = load double, double* %tmp4, align 1		; <double> [#uses=1]
+	%tmp6 = getelementptr [8 x i8], [8 x i8]* @.str, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp7 = call i32 (i8*, ...) @printf( i8* %tmp6, double %tmp23, double %tmp5 )		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
-	%retval8 = load i32* %retval		; <i32> [#uses=1]
+	%retval8 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval8
 }
 
diff --git a/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll b/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll
index 84fadd1b0461..07b1f8d7698a 100644
--- a/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll
+++ b/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll
@@ -10,9 +10,9 @@ entry:
 cond_true:		; preds = %entry
 	%tmp89 = bitcast float* %res to <4 x i32>*		; <<4 x i32>*> [#uses=1]
 	%tmp1011 = bitcast float* %argA to <4 x i32>*		; <<4 x i32>*> [#uses=1]
-	%tmp14 = load <4 x i32>* %tmp1011, align 16		; <<4 x i32>> [#uses=1]
+	%tmp14 = load <4 x i32>, <4 x i32>* %tmp1011, align 16		; <<4 x i32>> [#uses=1]
 	%tmp1516 = bitcast float* %argB to <4 x i32>*		; <<4 x i32>*> [#uses=1]
-	%tmp18 = load <4 x i32>* %tmp1516, align 16		; <<4 x i32>> [#uses=1]
+	%tmp18 = load <4 x i32>, <4 x i32>* %tmp1516, align 16		; <<4 x i32>> [#uses=1]
 	%tmp19 = sdiv <4 x i32> %tmp14, %tmp18		; <<4 x i32>> [#uses=1]
 	store <4 x i32> %tmp19, <4 x i32>* %tmp89, align 16
 	ret void
diff --git a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
index a60d11c85c55..13b9be31b69b 100644
--- a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
+++ b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
@@ -17,11 +17,11 @@
 define %struct.NSManagedObjectContext* @"+[ListGenerator(Private) managedObjectContextWithModelURL:storeURL:]"(%struct.objc_object* %self, %struct._message_ref_t* %_cmd, %struct.NSURL* %modelURL, %struct.NSURL* %storeURL) {
 entry:
 	%storeCoordinator = alloca %struct.NSPersistentStoreCoordinator*		; <%struct.NSPersistentStoreCoordinator**> [#uses=0]
-	%tmp29 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2" )		; <%struct.objc_object*> [#uses=0]
-	%tmp34 = load %struct.NSString** @NSXMLStoreType, align 8		; <%struct.NSString*> [#uses=1]
-	%tmp37 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_5", i32 0, i32 0), align 8		; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1]
-	%tmp42 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 1 )		; <%struct.objc_object*> [#uses=1]
-	%tmp45 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp37( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_5", %struct.objc_object* %tmp42, %struct.NSString* null )		; <%struct.objc_object*> [#uses=1]
-	%tmp48 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", %struct.NSString* %tmp34, i8* null, %struct.NSURL* null, %struct.objc_object* %tmp45, %struct.NSError** null )		; <%struct.objc_object*> [#uses=0]
+	%tmp29 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...) null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2" )		; <%struct.objc_object*> [#uses=0]
+	%tmp34 = load %struct.NSString*, %struct.NSString** @NSXMLStoreType, align 8		; <%struct.NSString*> [#uses=1]
+	%tmp37 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*, %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_5", i32 0, i32 0), align 8		; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1]
+	%tmp42 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...) null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 1 )		; <%struct.objc_object*> [#uses=1]
+	%tmp45 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...) %tmp37( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_5", %struct.objc_object* %tmp42, %struct.NSString* null )		; <%struct.objc_object*> [#uses=1]
+	%tmp48 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...) null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", %struct.NSString* %tmp34, i8* null, %struct.NSURL* null, %struct.objc_object* %tmp45, %struct.NSError** null )		; <%struct.objc_object*> [#uses=0]
 	unreachable
 }
diff --git a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
index 3d1a328ec3c1..ff5f835fd531 100644
--- a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
+++ b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
@@ -14,12 +14,12 @@
 
 define %struct.NSManagedObjectContext* @"+[ListGenerator(Private) managedObjectContextWithModelURL:storeURL:]"(%struct.objc_object* %self, %struct._message_ref_t* %_cmd, %struct.NSURL* %modelURL, %struct.NSURL* %storeURL) {
 entry:
-	%tmp27 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2", i32 0, i32 0), align 8		; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1]
-	%tmp29 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp27( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2" )		; <%struct.objc_object*> [#uses=0]
-	%tmp33 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", i32 0, i32 0), align 8		; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1]
-	%tmp34 = load %struct.NSString** @NSXMLStoreType, align 8		; <%struct.NSString*> [#uses=1]
-	%tmp40 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 0, i32 0), align 8		; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1]
-	%tmp42 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp40( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 1 )		; <%struct.objc_object*> [#uses=0]
-	%tmp48 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp33( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", %struct.NSString* %tmp34, i8* null, %struct.NSURL* null, %struct.objc_object* null, %struct.NSError** null )		; <%struct.objc_object*> [#uses=0]
+	%tmp27 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*, %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2", i32 0, i32 0), align 8		; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1]
+	%tmp29 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...) %tmp27( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2" )		; <%struct.objc_object*> [#uses=0]
+	%tmp33 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*, %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", i32 0, i32 0), align 8		; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1]
+	%tmp34 = load %struct.NSString*, %struct.NSString** @NSXMLStoreType, align 8		; <%struct.NSString*> [#uses=1]
+	%tmp40 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*, %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 0, i32 0), align 8		; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1]
+	%tmp42 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...) %tmp40( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 1 )		; <%struct.objc_object*> [#uses=0]
+	%tmp48 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...) %tmp33( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", %struct.NSString* %tmp34, i8* null, %struct.NSURL* null, %struct.objc_object* null, %struct.NSError** null )		; <%struct.objc_object*> [#uses=0]
 	unreachable
 }
diff --git a/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll b/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll
index df83f8b191c6..34122912349b 100644
--- a/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll
+++ b/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll
@@ -29,7 +29,7 @@ entry:
 			to label %bb30.preheader unwind label %unwind
 
 bb30.preheader:		; preds = %entry
-	%tmp26 = getelementptr %struct.Range* %effectiveRange, i64 0, i32 1		; <i64*> [#uses=1]
+	%tmp26 = getelementptr %struct.Range, %struct.Range* %effectiveRange, i64 0, i32 1		; <i64*> [#uses=1]
 	br label %bb30
 
 unwind:		; preds = %cond_true, %entry
@@ -39,7 +39,7 @@ unwind:		; preds = %cond_true, %entry
         resume { i8*, i32 } %exn
 
 invcont23:		; preds = %cond_true
-	%tmp27 = load i64* %tmp26, align 8		; <i64> [#uses=1]
+	%tmp27 = load i64, i64* %tmp26, align 8		; <i64> [#uses=1]
 	%tmp28 = sub i64 %range_addr.1.0, %tmp27		; <i64> [#uses=1]
 	br label %bb30
 
diff --git a/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
index d1f028586160..4830ca60f9ff 100644
--- a/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
+++ b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
@@ -6,7 +6,7 @@
 define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>*
 %CONST) {
 entry:
-        %input2 = load <4 x float>* null, align 16               ; <<4 x float>>
+        %input2 = load <4 x float>, <4 x float>* null, align 16               ; <<4 x float>>
        	%shuffle7 = shufflevector <4 x float> %input2, <4 x float> < float 0.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00 >, <4 x i32> < i32 2, i32 2, i32 2, i32 2 >		; <<4 x float>> [#uses=1]
 
         %mul1 = fmul <4 x float> %shuffle7, zeroinitializer              ; <<4 x
diff --git a/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll b/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll
index 791e9e610655..7ed7b9b36687 100644
--- a/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll
+++ b/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll
@@ -44,7 +44,7 @@ bb103.preheader:		; preds = %bb113
 
 bb113:		; preds = %bb113, %bb93, %bb82, %bb52, %entry
 	%fingerprint_addr.0.reg2mem.9 = phi i64 [ 0, %entry ], [ 0, %bb52 ], [ 0, %bb82 ], [ 0, %bb93 ], [ %tmp118, %bb113 ]		; <i64> [#uses=1]
-	tail call void @_Z28report_should_not_reach_herePKci( i8* getelementptr ([44 x i8]* @.str, i32 0, i32 0), i32 817 ) nounwind 
+	tail call void @_Z28report_should_not_reach_herePKci( i8* getelementptr ([44 x i8], [44 x i8]* @.str, i32 0, i32 0), i32 817 ) nounwind 
 	%tmp118 = lshr i64 %fingerprint_addr.0.reg2mem.9, 4		; <i64> [#uses=2]
 	%tmp21158 = and i64 %tmp118, 15		; <i64> [#uses=1]
 	switch i64 %tmp21158, label %bb113 [
diff --git a/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll b/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll
index e28a3e04cf1b..73a804bf02b2 100644
--- a/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll
+++ b/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll
@@ -2,7 +2,7 @@
 
 define i32 @bork(i64 %foo, i64 %bar) {
 entry:
-        %tmp = load i64* null, align 8          ; <i64> [#uses=2]
+        %tmp = load i64, i64* null, align 8          ; <i64> [#uses=2]
         %tmp2 = icmp ule i64 %tmp, 0            ; <i1> [#uses=1]
         %min = select i1 %tmp2, i64 %tmp, i64 0   ; <i64> [#uses=1]
         store i64 %min, i64* null, align 8
diff --git a/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll b/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll
index d10291e190b9..863b02528e1e 100644
--- a/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll
+++ b/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll
@@ -6,7 +6,7 @@ define void @foo(i8* %pp) nounwind  {
 entry:
 	%tmp2 = tail call i8* @bar( i32 14 ) nounwind 		; <i8*> [#uses=0]
 	%tmp28 = bitcast i8* %pp to void ()**		; <void ()**> [#uses=1]
-	%tmp38 = load void ()** %tmp28, align 4		; <void ()*> [#uses=2]
+	%tmp38 = load void ()*, void ()** %tmp28, align 4		; <void ()*> [#uses=2]
 	br i1 false, label %bb34, label %bb25
 bb25:		; preds = %entry
 	%tmp30 = bitcast void ()* %tmp38 to void (i8*)*		; <void (i8*)*> [#uses=1]
diff --git a/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll b/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
index fb8cdcea63aa..dc9734f2f734 100644
--- a/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
+++ b/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
@@ -7,7 +7,7 @@ declare fastcc void @emit_numeric_escape(i32, i32, %struct._cpp_strbuf*, i32) no
 
 define i32 @cpp_interpret_string(i32 %pfile, %struct.cpp_string* %from, i32 %wide) nounwind  {
 entry:
-	%tmp61 = load i32* null, align 4		; <i32> [#uses=1]
+	%tmp61 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	%toBool = icmp eq i32 %wide, 0		; <i1> [#uses=2]
 	%iftmp.87.0 = select i1 %toBool, i32 %tmp61, i32 0		; <i32> [#uses=2]
 	%tmp69 = icmp ult i32 %iftmp.87.0, 33		; <i1> [#uses=1]
@@ -23,7 +23,7 @@ bb94:		; preds = %bb79
 bb103:		; preds = %bb79
 	ret i32 0
 bb130.preheader:		; preds = %bb94
-	%tmp134 = getelementptr %struct.cpp_string* %from, i32 0, i32 1		; <i8**> [#uses=0]
+	%tmp134 = getelementptr %struct.cpp_string, %struct.cpp_string* %from, i32 0, i32 1		; <i8**> [#uses=0]
 	ret i32 0
 bb729:		; preds = %bb94
 	call fastcc void @emit_numeric_escape( i32 %pfile, i32 0, %struct._cpp_strbuf* null, i32 %wide ) nounwind 
diff --git a/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll b/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll
index a8fef05b1ad8..1191748b87d4 100644
--- a/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll
+++ b/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll
@@ -5,8 +5,8 @@ entry:
 	%tmp2627 = ptrtoint i8* %rec to i64		; <i64> [#uses=2]
 	%tmp28 = and i64 %tmp2627, -16384		; <i64> [#uses=2]
 	%tmp2829 = inttoptr i64 %tmp28 to i8*		; <i8*> [#uses=1]
-	%tmp37 = getelementptr i8* %tmp2829, i64 42		; <i8*> [#uses=1]
-	%tmp40 = load i8* %tmp37, align 1		; <i8> [#uses=1]
+	%tmp37 = getelementptr i8, i8* %tmp2829, i64 42		; <i8*> [#uses=1]
+	%tmp40 = load i8, i8* %tmp37, align 1		; <i8> [#uses=1]
 	%tmp4041 = zext i8 %tmp40 to i64		; <i64> [#uses=1]
 	%tmp42 = shl i64 %tmp4041, 8		; <i64> [#uses=1]
 	%tmp47 = add i64 %tmp42, 0		; <i64> [#uses=1]
diff --git a/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll
index 8e5bf567b126..908a2a803b2b 100644
--- a/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll
+++ b/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll
@@ -2,7 +2,7 @@
 
 define i32 @t(i64 %byteStart, i32 %activeIndex) nounwind  {
 entry:
-	%tmp50 = load i32* null, align 4		; <i32> [#uses=1]
+	%tmp50 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	%tmp5051 = zext i32 %tmp50 to i64		; <i64> [#uses=3]
 	%tmp53 = udiv i64 %byteStart, %tmp5051		; <i64> [#uses=1]
 	%tmp5354 = trunc i64 %tmp53 to i32		; <i32> [#uses=1]
diff --git a/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll b/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll
index e7a1cf69c693..45d43997fefb 100644
--- a/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll
+++ b/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll
@@ -24,7 +24,7 @@ bb:		; preds = %entry
 
 bb31:		; preds = %_Z24unlock_then_erase_sectory.exit, %bb
 	%Pos.0.reg2mem.0 = phi i64 [ %tmp93, %_Z24unlock_then_erase_sectory.exit ], [ %Offset, %bb ]		; <i64> [#uses=3]
-	%tmp35 = load i16* @_ZL10DeviceCode, align 2		; <i16> [#uses=1]
+	%tmp35 = load i16, i16* @_ZL10DeviceCode, align 2		; <i16> [#uses=1]
 	%tmp3536 = zext i16 %tmp35 to i32		; <i32> [#uses=2]
 	%tmp37 = and i32 %tmp3536, 65520		; <i32> [#uses=1]
 	%tmp38 = icmp eq i32 %tmp37, 35008		; <i1> [#uses=1]
@@ -39,11 +39,11 @@ bb41:		; preds = %bb31
 	ret i32 0
 
 bb68:		; preds = %bb31
-	tail call void (i8*, ...)* @IOLog( i8* getelementptr ([68 x i8]* @.str34, i32 0, i32 0), i64 %tmp34, i64 0, i32 131072 ) nounwind 
+	tail call void (i8*, ...) @IOLog( i8* getelementptr ([68 x i8], [68 x i8]* @.str34, i32 0, i32 0), i64 %tmp34, i64 0, i32 131072 ) nounwind 
 	%tmp2021.i = trunc i64 %Pos.0.reg2mem.0 to i32		; <i32> [#uses=1]
 	%tmp202122.i = inttoptr i32 %tmp2021.i to i8*		; <i8*> [#uses=1]
 	tail call void @IODelay( i32 500 ) nounwind 
-	%tmp53.i = load volatile i16* null, align 2		; <i16> [#uses=2]
+	%tmp53.i = load volatile i16, i16* null, align 2		; <i16> [#uses=2]
 	%tmp5455.i = zext i16 %tmp53.i to i32		; <i32> [#uses=1]
 	br i1 false, label %bb.i, label %bb65.i
 
@@ -55,7 +55,7 @@ bb65.i:		; preds = %bb68
 	br i1 %tmp67.i, label %_Z24unlock_then_erase_sectory.exit, label %bb70.i
 
 bb70.i:		; preds = %bb65.i
-	tail call void (i8*, ...)* @IOLog( i8* getelementptr ([64 x i8]* @.str19, i32 0, i32 0), i32 %tmp5455.i ) nounwind 
+	tail call void (i8*, ...) @IOLog( i8* getelementptr ([64 x i8], [64 x i8]* @.str19, i32 0, i32 0), i32 %tmp5455.i ) nounwind 
 	ret i32 0
 
 _Z24unlock_then_erase_sectory.exit:		; preds = %bb65.i
@@ -66,15 +66,15 @@ _Z24unlock_then_erase_sectory.exit:		; preds = %bb65.i
 	br i1 %tmp100, label %bb31, label %bb103
 
 bb103:		; preds = %_Z24unlock_then_erase_sectory.exit, %bb
-	tail call void (i8*, ...)* @IOLog( i8* getelementptr ([37 x i8]* @.str35, i32 0, i32 0) ) nounwind 
+	tail call void (i8*, ...) @IOLog( i8* getelementptr ([37 x i8], [37 x i8]* @.str35, i32 0, i32 0) ) nounwind 
 	ret i32 0
 
 bb107:		; preds = %entry
-	tail call void (i8*, ...)* @IOLog( i8* getelementptr ([48 x i8]* @.str36, i32 0, i32 0) ) nounwind 
+	tail call void (i8*, ...) @IOLog( i8* getelementptr ([48 x i8], [48 x i8]* @.str36, i32 0, i32 0) ) nounwind 
 	%tmp114115 = bitcast i8* %buffer to i16*		; <i16*> [#uses=1]
 	%tmp256 = lshr i64 %bufferSize, 1		; <i64> [#uses=1]
 	%tmp256257 = trunc i64 %tmp256 to i32		; <i32> [#uses=1]
-	%tmp258 = getelementptr i16* %tmp114115, i32 %tmp256257		; <i16*> [#uses=0]
+	%tmp258 = getelementptr i16, i16* %tmp114115, i32 %tmp256257		; <i16*> [#uses=0]
 	ret i32 0
 }
 
diff --git a/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll b/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll
index 862559b109cf..8ce1708acdbf 100644
--- a/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll
+++ b/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll
@@ -4,7 +4,7 @@
 @h = external global ppc_fp128
 
 define void @f() {
-	%tmp = load ppc_fp128* @g
+	%tmp = load ppc_fp128, ppc_fp128* @g
 	store ppc_fp128 %tmp, ppc_fp128* @h
 	ret void
 }
diff --git a/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll b/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll
index 83c5511878ca..db488ff36bfb 100644
--- a/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll
+++ b/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll
@@ -6,7 +6,7 @@ entry:
 	br i1 true, label %bb1, label %bb3
 
 bb1:
-	%tmp1 = load i8* null, align 1
+	%tmp1 = load i8, i8* null, align 1
 	%tmp2 = icmp eq i8 %tmp1, 0
 	br label %bb2
 
diff --git a/test/CodeGen/PowerPC/2008-07-15-Bswap.ll b/test/CodeGen/PowerPC/2008-07-15-Bswap.ll
index 4a834f93a205..b271048fd045 100644
--- a/test/CodeGen/PowerPC/2008-07-15-Bswap.ll
+++ b/test/CodeGen/PowerPC/2008-07-15-Bswap.ll
@@ -95,13 +95,13 @@ entry:
 
 bb16:		; preds = %entry
 	bitcast %struct.PerMacroblockBoundaryStrengths* null to i32*		; <i32*>:1 [#uses=3]
-	getelementptr i32* %1, i32 1		; <i32*>:2 [#uses=0]
-	getelementptr i32* %1, i32 2		; <i32*>:3 [#uses=0]
-	getelementptr i32* %1, i32 3		; <i32*>:4 [#uses=0]
+	getelementptr i32, i32* %1, i32 1		; <i32*>:2 [#uses=0]
+	getelementptr i32, i32* %1, i32 2		; <i32*>:3 [#uses=0]
+	getelementptr i32, i32* %1, i32 3		; <i32*>:4 [#uses=0]
 	bitcast [16 x i8]* null to i32*		; <i32*>:5 [#uses=3]
-	getelementptr i32* %5, i32 1		; <i32*>:6 [#uses=0]
-	getelementptr i32* %5, i32 2		; <i32*>:7 [#uses=0]
-	getelementptr i32* %5, i32 3		; <i32*>:8 [#uses=0]
+	getelementptr i32, i32* %5, i32 1		; <i32*>:6 [#uses=0]
+	getelementptr i32, i32* %5, i32 2		; <i32*>:7 [#uses=0]
+	getelementptr i32, i32* %5, i32 3		; <i32*>:8 [#uses=0]
 	icmp eq i32 0, 0		; <i1>:9 [#uses=0]
 	lshr i32 0, 30		; <i32>:10 [#uses=0]
 	and i32 0, 268435455		; <i32>:11 [#uses=0]
@@ -117,14 +117,14 @@ bb16:		; preds = %entry
 	%.not658 = icmp ne i32 0, 0		; <i1> [#uses=1]
 	and i32 0, 268369920		; <i32>:20 [#uses=1]
 	icmp eq i32 %20, 268369920		; <i1>:21 [#uses=2]
-	getelementptr %struct.PerMacroblockBoundaryStrengths* null, i32 0, i32 2		; <[4 x i8]*>:22 [#uses=1]
-	getelementptr %struct.PerMacroblockBoundaryStrengths* null, i32 0, i32 2, i32 0		; <i8*>:23 [#uses=0]
+	getelementptr %struct.PerMacroblockBoundaryStrengths, %struct.PerMacroblockBoundaryStrengths* null, i32 0, i32 2		; <[4 x i8]*>:22 [#uses=1]
+	getelementptr %struct.PerMacroblockBoundaryStrengths, %struct.PerMacroblockBoundaryStrengths* null, i32 0, i32 2, i32 0		; <i8*>:23 [#uses=0]
 	and i32 0, -2		; <i32>:24 [#uses=1]
 	add i32 %24, -1		; <i32>:25 [#uses=0]
 	bitcast [4 x i8]* %22 to i32*		; <i32*>:26 [#uses=3]
-	getelementptr i32* %26, i32 1		; <i32*>:27 [#uses=0]
-	getelementptr i32* %26, i32 2		; <i32*>:28 [#uses=0]
-	getelementptr i32* %26, i32 3		; <i32*>:29 [#uses=0]
+	getelementptr i32, i32* %26, i32 1		; <i32*>:27 [#uses=0]
+	getelementptr i32, i32* %26, i32 2		; <i32*>:28 [#uses=0]
+	getelementptr i32, i32* %26, i32 3		; <i32*>:29 [#uses=0]
 	br label %bb144
 
 bb144:		; preds = %bb395, %bb16
@@ -136,8 +136,8 @@ bb144:		; preds = %bb395, %bb16
 	%boundaryStrengthsV.1771 = phi i8* [ null, %bb16 ], [ %158, %bb395 ]		; <i8*> [#uses=2]
 	%numEdgesToTest.1770 = phi i32 [ 4, %bb16 ], [ %numEdgesToTest.2, %bb395 ]		; <i32> [#uses=1]
 	icmp eq i32 %idxEachField11.0773, 0		; <i1>:30 [#uses=0]
-	getelementptr %struct.BiPartSrcDescriptor** null, i32 %mbIndexLeft.2772		; <%struct.BiPartSrcDescriptor**>:31 [#uses=1]
-	load %struct.BiPartSrcDescriptor** %31, align 4		; <%struct.BiPartSrcDescriptor*>:32 [#uses=0]
+	getelementptr %struct.BiPartSrcDescriptor*, %struct.BiPartSrcDescriptor** null, i32 %mbIndexLeft.2772		; <%struct.BiPartSrcDescriptor**>:31 [#uses=1]
+	load %struct.BiPartSrcDescriptor*, %struct.BiPartSrcDescriptor** %31, align 4		; <%struct.BiPartSrcDescriptor*>:32 [#uses=0]
 	%fMacroblockHasNonZeroBS.4 = select i1 %21, i32 1, i32 0		; <i32> [#uses=1]
 	%numEdgesToTest.2 = select i1 %21, i32 1, i32 %numEdgesToTest.1770		; <i32> [#uses=2]
 	store i8 32, i8* %boundaryStrengthsV.1771, align 1
@@ -180,32 +180,32 @@ bb210.preheader:		; preds = %bb206
 	add i32 %52, %42		; <i32>:53 [#uses=1]
 	mul i32 %51, 0		; <i32>:54 [#uses=1]
 	add i32 %46, %54		; <i32>:55 [#uses=1]
-	getelementptr %struct.BiPartSrcDescriptor** null, i32 %53		; <%struct.BiPartSrcDescriptor**>:56 [#uses=1]
-	load %struct.BiPartSrcDescriptor** %56, align 4		; <%struct.BiPartSrcDescriptor*>:57 [#uses=7]
-	getelementptr %struct.BiPartSrcDescriptor** null, i32 %55		; <%struct.BiPartSrcDescriptor**>:58 [#uses=1]
-	load %struct.BiPartSrcDescriptor** %58, align 4		; <%struct.BiPartSrcDescriptor*>:59 [#uses=5]
+	getelementptr %struct.BiPartSrcDescriptor*, %struct.BiPartSrcDescriptor** null, i32 %53		; <%struct.BiPartSrcDescriptor**>:56 [#uses=1]
+	load %struct.BiPartSrcDescriptor*, %struct.BiPartSrcDescriptor** %56, align 4		; <%struct.BiPartSrcDescriptor*>:57 [#uses=7]
+	getelementptr %struct.BiPartSrcDescriptor*, %struct.BiPartSrcDescriptor** null, i32 %55		; <%struct.BiPartSrcDescriptor**>:58 [#uses=1]
+	load %struct.BiPartSrcDescriptor*, %struct.BiPartSrcDescriptor** %58, align 4		; <%struct.BiPartSrcDescriptor*>:59 [#uses=5]
 	icmp slt i32 %159, 0		; <i1>:60 [#uses=0]
 	icmp eq %struct.BiPartSrcDescriptor* %57, %59		; <i1>:61 [#uses=0]
 	bitcast %struct.BiPartSrcDescriptor* %57 to i16*		; <i16*>:62 [#uses=5]
-	load i16* %62, align 2		; <i16>:63 [#uses=2]
-	getelementptr i16* %62, i32 1		; <i16*>:64 [#uses=1]
-	load i16* %64, align 2		; <i16>:65 [#uses=2]
-	getelementptr i16* %62, i32 2		; <i16*>:66 [#uses=1]
-	load i16* %66, align 2		; <i16>:67 [#uses=2]
-	getelementptr i16* %62, i32 3		; <i16*>:68 [#uses=1]
-	load i16* %68, align 2		; <i16>:69 [#uses=2]
-	getelementptr i16* %62, i32 6		; <i16*>:70 [#uses=1]
-	load i16* %70, align 2		; <i16>:71 [#uses=2]
+	load i16, i16* %62, align 2		; <i16>:63 [#uses=2]
+	getelementptr i16, i16* %62, i32 1		; <i16*>:64 [#uses=1]
+	load i16, i16* %64, align 2		; <i16>:65 [#uses=2]
+	getelementptr i16, i16* %62, i32 2		; <i16*>:66 [#uses=1]
+	load i16, i16* %66, align 2		; <i16>:67 [#uses=2]
+	getelementptr i16, i16* %62, i32 3		; <i16*>:68 [#uses=1]
+	load i16, i16* %68, align 2		; <i16>:69 [#uses=2]
+	getelementptr i16, i16* %62, i32 6		; <i16*>:70 [#uses=1]
+	load i16, i16* %70, align 2		; <i16>:71 [#uses=2]
 	bitcast %struct.BiPartSrcDescriptor* %59 to i16*		; <i16*>:72 [#uses=5]
-	load i16* %72, align 2		; <i16>:73 [#uses=2]
-	getelementptr i16* %72, i32 1		; <i16*>:74 [#uses=1]
-	load i16* %74, align 2		; <i16>:75 [#uses=2]
-	getelementptr i16* %72, i32 2		; <i16*>:76 [#uses=1]
-	load i16* %76, align 2		; <i16>:77 [#uses=2]
-	getelementptr i16* %72, i32 3		; <i16*>:78 [#uses=1]
-	load i16* %78, align 2		; <i16>:79 [#uses=2]
-	getelementptr i16* %72, i32 6		; <i16*>:80 [#uses=1]
-	load i16* %80, align 2		; <i16>:81 [#uses=2]
+	load i16, i16* %72, align 2		; <i16>:73 [#uses=2]
+	getelementptr i16, i16* %72, i32 1		; <i16*>:74 [#uses=1]
+	load i16, i16* %74, align 2		; <i16>:75 [#uses=2]
+	getelementptr i16, i16* %72, i32 2		; <i16*>:76 [#uses=1]
+	load i16, i16* %76, align 2		; <i16>:77 [#uses=2]
+	getelementptr i16, i16* %72, i32 3		; <i16*>:78 [#uses=1]
+	load i16, i16* %78, align 2		; <i16>:79 [#uses=2]
+	getelementptr i16, i16* %72, i32 6		; <i16*>:80 [#uses=1]
+	load i16, i16* %80, align 2		; <i16>:81 [#uses=2]
 	sub i16 %63, %73		; <i16>:82 [#uses=3]
 	sub i16 %65, %75		; <i16>:83 [#uses=3]
 	sub i16 %67, %77		; <i16>:84 [#uses=3]
@@ -226,23 +226,23 @@ bb210.preheader:		; preds = %bb206
 	sub i16 0, %86		; <i16>:95 [#uses=1]
 	icmp slt i16 %86, 0		; <i1>:96 [#uses=1]
 	%.663 = select i1 %96, i16 %95, i16 %86		; <i16> [#uses=1]
-	getelementptr %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 1, i32 0		; <i8*>:97 [#uses=1]
-	load i8* %97, align 1		; <i8>:98 [#uses=1]
+	getelementptr %struct.BiPartSrcDescriptor, %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 1, i32 0		; <i8*>:97 [#uses=1]
+	load i8, i8* %97, align 1		; <i8>:98 [#uses=1]
 	zext i8 %98 to i32		; <i32>:99 [#uses=1]
-	getelementptr %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 1, i32 1		; <i8*>:100 [#uses=1]
-	load i8* %100, align 1		; <i8>:101 [#uses=1]
+	getelementptr %struct.BiPartSrcDescriptor, %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 1, i32 1		; <i8*>:100 [#uses=1]
+	load i8, i8* %100, align 1		; <i8>:101 [#uses=1]
 	zext i8 %101 to i32		; <i32>:102 [#uses=1]
-	getelementptr %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 3, i32 0		; <i8*>:103 [#uses=1]
-	load i8* %103, align 1		; <i8>:104 [#uses=2]
+	getelementptr %struct.BiPartSrcDescriptor, %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 3, i32 0		; <i8*>:103 [#uses=1]
+	load i8, i8* %103, align 1		; <i8>:104 [#uses=2]
 	zext i8 %104 to i32		; <i32>:105 [#uses=1]
-	getelementptr %struct.BiPartSrcDescriptor* %59, i32 0, i32 0, i32 0, i32 3, i32 0		; <i8*>:106 [#uses=1]
-	load i8* %106, align 1		; <i8>:107 [#uses=2]
+	getelementptr %struct.BiPartSrcDescriptor, %struct.BiPartSrcDescriptor* %59, i32 0, i32 0, i32 0, i32 3, i32 0		; <i8*>:106 [#uses=1]
+	load i8, i8* %106, align 1		; <i8>:107 [#uses=2]
 	zext i8 %107 to i32		; <i32>:108 [#uses=1]
-	getelementptr %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 3, i32 1		; <i8*>:109 [#uses=1]
-	load i8* %109, align 1		; <i8>:110 [#uses=1]
+	getelementptr %struct.BiPartSrcDescriptor, %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 3, i32 1		; <i8*>:109 [#uses=1]
+	load i8, i8* %109, align 1		; <i8>:110 [#uses=1]
 	zext i8 %110 to i32		; <i32>:111 [#uses=1]
-	getelementptr %struct.BiPartSrcDescriptor* %59, i32 0, i32 0, i32 0, i32 3, i32 1		; <i8*>:112 [#uses=1]
-	load i8* %112, align 1		; <i8>:113 [#uses=1]
+	getelementptr %struct.BiPartSrcDescriptor, %struct.BiPartSrcDescriptor* %59, i32 0, i32 0, i32 0, i32 3, i32 1		; <i8*>:112 [#uses=1]
+	load i8, i8* %112, align 1		; <i8>:113 [#uses=1]
 	zext i8 %113 to i32		; <i32>:114 [#uses=1]
 	lshr i32 %99, 4		; <i32>:115 [#uses=1]
 	and i32 %115, 2		; <i32>:116 [#uses=1]
@@ -322,13 +322,13 @@ labelContinueEdgesLoopV:		; preds = %bb206, %bb205, %bb144
 	%bfNZ12.2 = phi i32 [ %159, %bb205 ], [ 0, %bb144 ], [ %159, %bb206 ]		; <i32> [#uses=1]
 	%boundaryStrengthsV.3 = phi i8* [ %158, %bb205 ], [ %boundaryStrengthsV.1771, %bb144 ], [ %158, %bb206 ]		; <i8*> [#uses=3]
 	or i32 %fMacroblockHasNonZeroBS.6, %fEdgeHasNonZeroBS.0		; <i32>:152 [#uses=2]
-	load i8* %boundaryStrengthsV.3, align 1		; <i8>:153 [#uses=1]
+	load i8, i8* %boundaryStrengthsV.3, align 1		; <i8>:153 [#uses=1]
 	trunc i32 %fEdgeHasNonZeroBS.0 to i8		; <i8>:154 [#uses=1]
 	shl i8 %154, 5		; <i8>:155 [#uses=1]
 	xor i8 %155, 32		; <i8>:156 [#uses=1]
 	or i8 %153, %156		; <i8>:157 [#uses=1]
 	store i8 %157, i8* %boundaryStrengthsV.3, align 1
-	getelementptr i8* %boundaryStrengthsV.3, i32 4		; <i8*>:158 [#uses=4]
+	getelementptr i8, i8* %boundaryStrengthsV.3, i32 4		; <i8*>:158 [#uses=4]
 	shl i32 %bfNZ12.2, 4		; <i32>:159 [#uses=4]
 	add i32 %ixEdge.1, 1		; <i32>:160 [#uses=6]
 	icmp ult i32 %160, %numEdgesToTest.2		; <i1>:161 [#uses=1]
diff --git a/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
index 21b0c619e111..53639e7ceb04 100644
--- a/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
+++ b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
@@ -4,7 +4,7 @@ target triple = "powerpc-apple-darwin9"
 
 define signext i16 @t(i16* %dct)  nounwind  {
 entry:
-         load i16* null, align 2         ; <i16>:0 [#uses=2]
+         load i16, i16* null, align 2         ; <i16>:0 [#uses=2]
          lshr i16 %0, 11         ; <i16>:1 [#uses=0]
          trunc i16 %0 to i8              ; <i8>:2 [#uses=1]
          sext i8 %2 to i16               ; <i16>:3 [#uses=1]
diff --git a/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll b/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll
index c9c05e1cc363..ee3d0f4ea46c 100644
--- a/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll
+++ b/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll
@@ -4,7 +4,7 @@
 
 define void @llvm_static_func(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, i32 %a10, i32 %a11, i32 %a12, i32 %a13, i32 %a14, i32 %a15) nounwind  {
 entry:
-	tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i64 0), i32 %a8 ) nounwind 		; <i32>:0 [#uses=0]
+	tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i64 0), i32 %a8 ) nounwind 		; <i32>:0 [#uses=0]
 	ret void
 }
 
diff --git a/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll
index 97844dd7486a..b107600de135 100644
--- a/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll
+++ b/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll
@@ -10,25 +10,25 @@
 
 define void @lb(%struct.CGLSI* %src, i32 %n, %struct.CGLDI* %dst) nounwind {
 entry:
-	%0 = load i32* null, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	%1 = icmp sgt i32 %0, 0		; <i1> [#uses=1]
 	br i1 %1, label %bb.nph4945, label %return
 
 bb.nph4945:		; preds = %entry
 	%2 = bitcast [2 x %struct.vv_t]* null to i64*		; <i64*> [#uses=6]
-	%3 = getelementptr [2 x i64]* null, i32 0, i32 1		; <i64*> [#uses=6]
+	%3 = getelementptr [2 x i64], [2 x i64]* null, i32 0, i32 1		; <i64*> [#uses=6]
 	%4 = bitcast %struct.vv_t* null to i64*		; <i64*> [#uses=5]
-	%5 = getelementptr [2 x i64]* null, i32 0, i32 1		; <i64*> [#uses=3]
+	%5 = getelementptr [2 x i64], [2 x i64]* null, i32 0, i32 1		; <i64*> [#uses=3]
 	br label %bb2326
 
 bb2217:		; preds = %bb2326
 	%6 = or i64 0, 0		; <i64> [#uses=2]
 	%7 = fptosi float 0.000000e+00 to i32		; <i32> [#uses=1]
 	%8 = fptosi float 0.000000e+00 to i32		; <i32> [#uses=1]
-	%9 = getelementptr float* null, i32 2		; <float*> [#uses=1]
-	%10 = load float* %9, align 4		; <float> [#uses=1]
-	%11 = getelementptr float* null, i32 3		; <float*> [#uses=1]
-	%12 = load float* %11, align 4		; <float> [#uses=1]
+	%9 = getelementptr float, float* null, i32 2		; <float*> [#uses=1]
+	%10 = load float, float* %9, align 4		; <float> [#uses=1]
+	%11 = getelementptr float, float* null, i32 3		; <float*> [#uses=1]
+	%12 = load float, float* %11, align 4		; <float> [#uses=1]
 	%13 = fmul float %10, 6.553500e+04		; <float> [#uses=1]
 	%14 = fadd float %13, 5.000000e-01		; <float> [#uses=1]
 	%15 = fmul float %12, 6.553500e+04		; <float> [#uses=1]
@@ -63,11 +63,11 @@ bb2265:		; preds = %bb2264, %bb2262, %bb2217
 	%34 = and i64 %33, 281470681743360		; <i64> [#uses=1]
 	store i64 %6, i64* %2, align 16
 	store i64 %31, i64* %3, align 8
-	%35 = getelementptr i8* null, i32 0		; <i8*> [#uses=1]
+	%35 = getelementptr i8, i8* null, i32 0		; <i8*> [#uses=1]
 	%36 = bitcast i8* %35 to float*		; <float*> [#uses=4]
-	%37 = load float* %36, align 4		; <float> [#uses=1]
-	%38 = getelementptr float* %36, i32 1		; <float*> [#uses=1]
-	%39 = load float* %38, align 4		; <float> [#uses=1]
+	%37 = load float, float* %36, align 4		; <float> [#uses=1]
+	%38 = getelementptr float, float* %36, i32 1		; <float*> [#uses=1]
+	%39 = load float, float* %38, align 4		; <float> [#uses=1]
 	%40 = fmul float %37, 6.553500e+04		; <float> [#uses=1]
 	%41 = fadd float %40, 5.000000e-01		; <float> [#uses=1]
 	%42 = fmul float %39, 6.553500e+04		; <float> [#uses=1]
@@ -84,10 +84,10 @@ bb2277:		; preds = %bb2274, %bb2265
 	%f1582.0 = phi float [ 0.000000e+00, %bb2265 ], [ %43, %bb2274 ]		; <float> [#uses=1]
 	%47 = fptosi float 0.000000e+00 to i32		; <i32> [#uses=1]
 	%48 = fptosi float %f1582.0 to i32		; <i32> [#uses=1]
-	%49 = getelementptr float* %36, i32 2		; <float*> [#uses=1]
-	%50 = load float* %49, align 4		; <float> [#uses=1]
-	%51 = getelementptr float* %36, i32 3		; <float*> [#uses=1]
-	%52 = load float* %51, align 4		; <float> [#uses=1]
+	%49 = getelementptr float, float* %36, i32 2		; <float*> [#uses=1]
+	%50 = load float, float* %49, align 4		; <float> [#uses=1]
+	%51 = getelementptr float, float* %36, i32 3		; <float*> [#uses=1]
+	%52 = load float, float* %51, align 4		; <float> [#uses=1]
 	%53 = fmul float %50, 6.553500e+04		; <float> [#uses=1]
 	%54 = fadd float %53, 5.000000e-01		; <float> [#uses=1]
 	%55 = fmul float %52, 6.553500e+04		; <float> [#uses=1]
@@ -106,11 +106,11 @@ bb2277:		; preds = %bb2274, %bb2265
 	%68 = or i64 %64, %62		; <i64> [#uses=1]
 	%69 = or i64 %68, %66		; <i64> [#uses=1]
 	%70 = or i64 %69, %67		; <i64> [#uses=2]
-	%71 = getelementptr i8* null, i32 0		; <i8*> [#uses=1]
+	%71 = getelementptr i8, i8* null, i32 0		; <i8*> [#uses=1]
 	%72 = bitcast i8* %71 to float*		; <float*> [#uses=4]
-	%73 = load float* %72, align 4		; <float> [#uses=1]
-	%74 = getelementptr float* %72, i32 1		; <float*> [#uses=1]
-	%75 = load float* %74, align 4		; <float> [#uses=1]
+	%73 = load float, float* %72, align 4		; <float> [#uses=1]
+	%74 = getelementptr float, float* %72, i32 1		; <float*> [#uses=1]
+	%75 = load float, float* %74, align 4		; <float> [#uses=1]
 	%76 = fmul float %73, 6.553500e+04		; <float> [#uses=1]
 	%77 = fadd float %76, 5.000000e-01		; <float> [#uses=3]
 	%78 = fmul float %75, 6.553500e+04		; <float> [#uses=1]
@@ -130,10 +130,10 @@ bb2295:		; preds = %bb2294, %bb2292, %bb2277
 	%82 = fcmp olt float %79, 0.000000e+00		; <i1> [#uses=0]
 	%83 = fptosi float %f0569.0 to i32		; <i32> [#uses=1]
 	%84 = fptosi float 0.000000e+00 to i32		; <i32> [#uses=1]
-	%85 = getelementptr float* %72, i32 2		; <float*> [#uses=1]
-	%86 = load float* %85, align 4		; <float> [#uses=1]
-	%87 = getelementptr float* %72, i32 3		; <float*> [#uses=1]
-	%88 = load float* %87, align 4		; <float> [#uses=1]
+	%85 = getelementptr float, float* %72, i32 2		; <float*> [#uses=1]
+	%86 = load float, float* %85, align 4		; <float> [#uses=1]
+	%87 = getelementptr float, float* %72, i32 3		; <float*> [#uses=1]
+	%88 = load float, float* %87, align 4		; <float> [#uses=1]
 	%89 = fmul float %86, 6.553500e+04		; <float> [#uses=1]
 	%90 = fadd float %89, 5.000000e-01		; <float> [#uses=1]
 	%91 = fmul float %88, 6.553500e+04		; <float> [#uses=1]
@@ -168,62 +168,62 @@ bb2315:		; preds = %bb2295
 	br i1 %114, label %bb2318, label %bb2317
 
 bb2317:		; preds = %bb2315
-	%115 = load i64* %2, align 16		; <i64> [#uses=1]
-	%116 = call i32 (...)* @_u16a_cm( i64 %115, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind		; <i32> [#uses=1]
+	%115 = load i64, i64* %2, align 16		; <i64> [#uses=1]
+	%116 = call i32 (...) @_u16a_cm( i64 %115, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind		; <i32> [#uses=1]
 	%117 = sext i32 %116 to i64		; <i64> [#uses=1]
 	store i64 %117, i64* %2, align 16
-	%118 = load i64* %3, align 8		; <i64> [#uses=1]
-	%119 = call i32 (...)* @_u16a_cm( i64 %118, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind		; <i32> [#uses=1]
+	%118 = load i64, i64* %3, align 8		; <i64> [#uses=1]
+	%119 = call i32 (...) @_u16a_cm( i64 %118, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind		; <i32> [#uses=1]
 	%120 = sext i32 %119 to i64		; <i64> [#uses=1]
 	store i64 %120, i64* %3, align 8
-	%121 = load i64* %4, align 16		; <i64> [#uses=1]
-	%122 = call i32 (...)* @_u16a_cm( i64 %121, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind		; <i32> [#uses=1]
+	%121 = load i64, i64* %4, align 16		; <i64> [#uses=1]
+	%122 = call i32 (...) @_u16a_cm( i64 %121, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind		; <i32> [#uses=1]
 	%123 = sext i32 %122 to i64		; <i64> [#uses=1]
 	store i64 %123, i64* %4, align 16
-	%124 = load i64* %5, align 8		; <i64> [#uses=1]
-	%125 = call i32 (...)* @_u16a_cm( i64 %124, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind		; <i32> [#uses=0]
+	%124 = load i64, i64* %5, align 8		; <i64> [#uses=1]
+	%125 = call i32 (...) @_u16a_cm( i64 %124, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind		; <i32> [#uses=0]
 	unreachable
 
 bb2318:		; preds = %bb2315
-	%126 = getelementptr %struct.CGLSI* %src, i32 %indvar5021, i32 8		; <%struct.vv_t*> [#uses=1]
+	%126 = getelementptr %struct.CGLSI, %struct.CGLSI* %src, i32 %indvar5021, i32 8		; <%struct.vv_t*> [#uses=1]
 	%127 = bitcast %struct.vv_t* %126 to i64*		; <i64*> [#uses=1]
-	%128 = load i64* %127, align 8		; <i64> [#uses=1]
+	%128 = load i64, i64* %127, align 8		; <i64> [#uses=1]
 	%129 = trunc i64 %128 to i32		; <i32> [#uses=4]
-	%130 = load i64* %2, align 16		; <i64> [#uses=1]
-	%131 = call i32 (...)* @_u16_ff( i64 %130, i32 %129 ) nounwind		; <i32> [#uses=1]
+	%130 = load i64, i64* %2, align 16		; <i64> [#uses=1]
+	%131 = call i32 (...) @_u16_ff( i64 %130, i32 %129 ) nounwind		; <i32> [#uses=1]
 	%132 = sext i32 %131 to i64		; <i64> [#uses=1]
 	store i64 %132, i64* %2, align 16
-	%133 = load i64* %3, align 8		; <i64> [#uses=1]
-	%134 = call i32 (...)* @_u16_ff( i64 %133, i32 %129 ) nounwind		; <i32> [#uses=1]
+	%133 = load i64, i64* %3, align 8		; <i64> [#uses=1]
+	%134 = call i32 (...) @_u16_ff( i64 %133, i32 %129 ) nounwind		; <i32> [#uses=1]
 	%135 = sext i32 %134 to i64		; <i64> [#uses=1]
 	store i64 %135, i64* %3, align 8
-	%136 = load i64* %4, align 16		; <i64> [#uses=1]
-	%137 = call i32 (...)* @_u16_ff( i64 %136, i32 %129 ) nounwind		; <i32> [#uses=1]
+	%136 = load i64, i64* %4, align 16		; <i64> [#uses=1]
+	%137 = call i32 (...) @_u16_ff( i64 %136, i32 %129 ) nounwind		; <i32> [#uses=1]
 	%138 = sext i32 %137 to i64		; <i64> [#uses=1]
 	store i64 %138, i64* %4, align 16
-	%139 = load i64* %5, align 8		; <i64> [#uses=1]
-	%140 = call i32 (...)* @_u16_ff( i64 %139, i32 %129 ) nounwind		; <i32> [#uses=0]
+	%139 = load i64, i64* %5, align 8		; <i64> [#uses=1]
+	%140 = call i32 (...) @_u16_ff( i64 %139, i32 %129 ) nounwind		; <i32> [#uses=0]
 	unreachable
 
 bb2319:		; preds = %bb2326
-	%141 = getelementptr %struct.CGLSI* %src, i32 %indvar5021, i32 2		; <i8**> [#uses=1]
-	%142 = load i8** %141, align 4		; <i8*> [#uses=4]
-	%143 = getelementptr i8* %142, i32 0		; <i8*> [#uses=1]
-	%144 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %143 ) nounwind		; <i32> [#uses=1]
+	%141 = getelementptr %struct.CGLSI, %struct.CGLSI* %src, i32 %indvar5021, i32 2		; <i8**> [#uses=1]
+	%142 = load i8*, i8** %141, align 4		; <i8*> [#uses=4]
+	%143 = getelementptr i8, i8* %142, i32 0		; <i8*> [#uses=1]
+	%144 = call i32 (...) @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %143 ) nounwind		; <i32> [#uses=1]
 	%145 = sext i32 %144 to i64		; <i64> [#uses=2]
-	%146 = getelementptr i8* %142, i32 0		; <i8*> [#uses=1]
-	%147 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %146 ) nounwind		; <i32> [#uses=1]
+	%146 = getelementptr i8, i8* %142, i32 0		; <i8*> [#uses=1]
+	%147 = call i32 (...) @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %146 ) nounwind		; <i32> [#uses=1]
 	%148 = sext i32 %147 to i64		; <i64> [#uses=2]
 	%149 = shl i64 %145, 48		; <i64> [#uses=0]
 	%150 = shl i64 %148, 32		; <i64> [#uses=1]
 	%151 = and i64 %150, 281470681743360		; <i64> [#uses=0]
 	store i64 %145, i64* %2, align 16
 	store i64 %148, i64* %3, align 8
-	%152 = getelementptr i8* %142, i32 0		; <i8*> [#uses=1]
-	%153 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %152 ) nounwind		; <i32> [#uses=1]
+	%152 = getelementptr i8, i8* %142, i32 0		; <i8*> [#uses=1]
+	%153 = call i32 (...) @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %152 ) nounwind		; <i32> [#uses=1]
 	%154 = sext i32 %153 to i64		; <i64> [#uses=0]
-	%155 = getelementptr i8* %142, i32 0		; <i8*> [#uses=1]
-	%156 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %155 ) nounwind		; <i32> [#uses=0]
+	%155 = getelementptr i8, i8* %142, i32 0		; <i8*> [#uses=1]
+	%156 = call i32 (...) @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %155 ) nounwind		; <i32> [#uses=0]
 	unreachable
 
 bb2325:		; preds = %bb2326, %bb2295
@@ -233,10 +233,10 @@ bb2325:		; preds = %bb2326, %bb2295
 bb2326:		; preds = %bb2325, %bb.nph4945
 	%indvar5021 = phi i32 [ 0, %bb.nph4945 ], [ %indvar.next5145, %bb2325 ]		; <i32> [#uses=6]
 	%157 = icmp slt i32 %indvar5021, %n		; <i1> [#uses=0]
-	%158 = getelementptr %struct.CGLSI* %src, i32 %indvar5021, i32 10		; <%struct.xx_t**> [#uses=1]
-	%159 = load %struct.xx_t** %158, align 4		; <%struct.xx_t*> [#uses=5]
-	%160 = getelementptr %struct.CGLSI* %src, i32 %indvar5021, i32 1		; <i32*> [#uses=1]
-	%161 = load i32* %160, align 4		; <i32> [#uses=1]
+	%158 = getelementptr %struct.CGLSI, %struct.CGLSI* %src, i32 %indvar5021, i32 10		; <%struct.xx_t**> [#uses=1]
+	%159 = load %struct.xx_t*, %struct.xx_t** %158, align 4		; <%struct.xx_t*> [#uses=5]
+	%160 = getelementptr %struct.CGLSI, %struct.CGLSI* %src, i32 %indvar5021, i32 1		; <i32*> [#uses=1]
+	%161 = load i32, i32* %160, align 4		; <i32> [#uses=1]
 	%162 = and i32 %161, 255		; <i32> [#uses=1]
 	switch i32 %162, label %bb2325 [
 		 i32 59, label %bb2217
diff --git a/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll b/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll
index f474a6d7cc22..2372b2f0b9dd 100644
--- a/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll
+++ b/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll
@@ -2,7 +2,7 @@
 
 define void @__divtc3({ ppc_fp128, ppc_fp128 }* noalias sret %agg.result, ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind {
 entry:
-        %imag59 = load ppc_fp128* null, align 8         ; <ppc_fp128> [#uses=1]
+        %imag59 = load ppc_fp128, ppc_fp128* null, align 8         ; <ppc_fp128> [#uses=1]
         %0 = fmul ppc_fp128 0xM00000000000000000000000000000000, %imag59         ; <ppc_fp128> [#uses=1]
         %1 = fmul ppc_fp128 0xM00000000000000000000000000000000, 0xM00000000000000000000000000000000             ; <ppc_fp128> [#uses=1]
         %2 = fadd ppc_fp128 %0, %1               ; <ppc_fp128> [#uses=1]
diff --git a/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll b/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll
index 8322a8430815..fbe1287776f1 100644
--- a/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll
+++ b/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll
@@ -9,17 +9,17 @@ target triple = "powerpc-apple-darwin10.0"
 
 define void @foo() nounwind {
 entry:
-	%0 = load ppc_fp128* @a, align 16		; <ppc_fp128> [#uses=1]
+	%0 = load ppc_fp128, ppc_fp128* @a, align 16		; <ppc_fp128> [#uses=1]
 	%1 = call ppc_fp128 @llvm.sqrt.ppcf128(ppc_fp128 %0)		; <ppc_fp128> [#uses=1]
 	store ppc_fp128 %1, ppc_fp128* @a, align 16
-	%2 = load ppc_fp128* @b, align 16		; <ppc_fp128> [#uses=1]
+	%2 = load ppc_fp128, ppc_fp128* @b, align 16		; <ppc_fp128> [#uses=1]
 	%3 = call ppc_fp128 @"\01_sinl$LDBL128"(ppc_fp128 %2) nounwind readonly		; <ppc_fp128> [#uses=1]
 	store ppc_fp128 %3, ppc_fp128* @b, align 16
-	%4 = load ppc_fp128* @c, align 16		; <ppc_fp128> [#uses=1]
+	%4 = load ppc_fp128, ppc_fp128* @c, align 16		; <ppc_fp128> [#uses=1]
 	%5 = call ppc_fp128 @"\01_cosl$LDBL128"(ppc_fp128 %4) nounwind readonly		; <ppc_fp128> [#uses=1]
 	store ppc_fp128 %5, ppc_fp128* @c, align 16
-	%6 = load ppc_fp128* @d, align 16		; <ppc_fp128> [#uses=1]
-	%7 = load ppc_fp128* @c, align 16		; <ppc_fp128> [#uses=1]
+	%6 = load ppc_fp128, ppc_fp128* @d, align 16		; <ppc_fp128> [#uses=1]
+	%7 = load ppc_fp128, ppc_fp128* @c, align 16		; <ppc_fp128> [#uses=1]
 	%8 = call ppc_fp128 @llvm.pow.ppcf128(ppc_fp128 %6, ppc_fp128 %7)		; <ppc_fp128> [#uses=1]
 	store ppc_fp128 %8, ppc_fp128* @d, align 16
 	br label %return
diff --git a/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll b/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll
index ce8e72df2616..74356d38f8a2 100644
--- a/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll
+++ b/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll
@@ -5,7 +5,7 @@
 
 define i32 @main() nounwind {
 entry:
-	%0 = call i8* @fopen(i8* getelementptr ([13 x i8]* @"\01LC", i32 0, i32 0), i8* null) nounwind		; <i8*> [#uses=0]
+	%0 = call i8* @fopen(i8* getelementptr ([13 x i8], [13 x i8]* @"\01LC", i32 0, i32 0), i8* null) nounwind		; <i8*> [#uses=0]
 	unreachable
 }
 
diff --git a/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll b/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll
index 172531e5db49..f5a7bf8de4c3 100644
--- a/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll
+++ b/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll
@@ -9,7 +9,7 @@ bb20.loopexit:		; preds = %entry
 	ret void
 
 bb21:		; preds = %entry
-	%0 = getelementptr i8* %a, i32 0		; <i8*> [#uses=2]
+	%0 = getelementptr i8, i8* %a, i32 0		; <i8*> [#uses=2]
 	br label %bb35
 
 bb29:		; preds = %bb35
@@ -17,7 +17,7 @@ bb29:		; preds = %bb35
 
 bb7.i252:		; preds = %bb7.i252, %bb29
 	%pj.0.rec.i247 = phi i32 [ %indvar.next488, %bb7.i252 ], [ 0, %bb29 ]		; <i32> [#uses=2]
-	%pi.0.i248 = getelementptr i8* %pa.1, i32 %pj.0.rec.i247		; <i8*> [#uses=0]
+	%pi.0.i248 = getelementptr i8, i8* %pa.1, i32 %pj.0.rec.i247		; <i8*> [#uses=0]
 	%indvar.next488 = add i32 %pj.0.rec.i247, 1		; <i32> [#uses=1]
 	br i1 false, label %bb34, label %bb7.i252
 
@@ -45,7 +45,7 @@ bb7.i161:		; preds = %bb7.i161, %bb50
 	%pj.0.rec.i156 = phi i32 [ %indvar.next394, %bb7.i161 ], [ 0, %bb50 ]		; <i32> [#uses=2]
 	%.sum279 = sub i32 %pj.0.rec.i156, %min		; <i32> [#uses=1]
 	%pb.0.sum542 = add i32 %pb.0.rec, %.sum279		; <i32> [#uses=1]
-	%pj.0.i158 = getelementptr i8* %0, i32 %pb.0.sum542		; <i8*> [#uses=0]
+	%pj.0.i158 = getelementptr i8, i8* %0, i32 %pb.0.sum542		; <i8*> [#uses=0]
 	%indvar.next394 = add i32 %pj.0.rec.i156, 1		; <i32> [#uses=1]
 	br label %bb7.i161
 }
diff --git a/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll b/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
index 91253daae396..289e09b2dae2 100644
--- a/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
+++ b/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
@@ -15,8 +15,8 @@ entry:
   %y_addr = alloca i32                            ; <i32*> [#uses=2]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   store i32 %y, i32* %y_addr
-  %0 = load i32* %y_addr, align 4                 ; <i32> [#uses=1]
-  %1 = getelementptr inbounds [0 x i32]* @x, i32 0, i32 %0 ; <i32*> [#uses=1]
+  %0 = load i32, i32* %y_addr, align 4                 ; <i32> [#uses=1]
+  %1 = getelementptr inbounds [0 x i32], [0 x i32]* @x, i32 0, i32 %0 ; <i32*> [#uses=1]
   call void asm sideeffect "isync\0A\09eieio\0A\09stw $1, $0", "=*o,r,~{memory}"(i32* %1, i32 0) nounwind
   br label %return
 
diff --git a/test/CodeGen/PowerPC/2009-11-15-ProcImpDefsBug.ll b/test/CodeGen/PowerPC/2009-11-15-ProcImpDefsBug.ll
index 2d9d16ae6d83..61a9a4fbd4c0 100644
--- a/test/CodeGen/PowerPC/2009-11-15-ProcImpDefsBug.ll
+++ b/test/CodeGen/PowerPC/2009-11-15-ProcImpDefsBug.ll
@@ -100,6 +100,6 @@ bb48.3:                                           ; preds = %bb49.2
   br label %bb49.3
 
 bb48.4:                                           ; preds = %bb49.3
-  %0 = getelementptr inbounds [5 x i64*]* undef, i32 0, i32 %c_ix.0.3 ; <i64**> [#uses=0]
+  %0 = getelementptr inbounds [5 x i64*], [5 x i64*]* undef, i32 0, i32 %c_ix.0.3 ; <i64**> [#uses=0]
   br label %bb51
 }
diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
index b0c37b80ed2f..5932b6d75c0a 100644
--- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
+++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
@@ -9,13 +9,13 @@ entry:
 ; CHECK: mfcr [[T1:r[0-9]+]]                         ; cr2
 ; CHECK: lis [[T2:r[0-9]+]], 1
 ; CHECK: addi r3, r1, 72
-; CHECK: rlwinm [[T1]], [[T1]], 8, 0, 31
+; CHECK: rotlwi [[T1]], [[T1]], 8
 ; CHECK: ori [[T2]], [[T2]], 34540
 ; CHECK: stwx [[T1]], r1, [[T2]]
 ; CHECK: lis [[T3:r[0-9]+]], 1
 ; CHECK: mfcr [[T4:r[0-9]+]]                         ; cr3
 ; CHECK: ori [[T3]], [[T3]], 34536
-; CHECK: rlwinm [[T4]], [[T4]], 12, 0, 31
+; CHECK: rotlwi [[T4]], [[T4]], 12
 ; CHECK: stwx [[T4]], r1, [[T3]]
   %x = alloca [100000 x i8]                       ; <[100000 x i8]*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
@@ -28,12 +28,12 @@ return:                                           ; preds = %entry
 ; CHECK: lis [[T1:r[0-9]+]], 1
 ; CHECK: ori [[T1]], [[T1]], 34536
 ; CHECK: lwzx [[T1]], r1, [[T1]]
-; CHECK: rlwinm [[T1]], [[T1]], 20, 0, 31
+; CHECK: rotlwi [[T1]], [[T1]], 20
 ; CHECK: mtcrf 16, [[T1]]
 ; CHECK: lis [[T1]], 1
 ; CHECK: ori [[T1]], [[T1]], 34540
 ; CHECK: lwzx [[T1]], r1, [[T1]]
-; CHECK: rlwinm [[T1]], [[T1]], 24, 0, 31
+; CHECK: rotlwi [[T1]], [[T1]], 24
 ; CHECK: mtcrf 32, [[T1]]
   ret void
 }
diff --git a/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll b/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll
index b95ac6880758..0599b74a69f5 100644
--- a/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll
+++ b/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll
@@ -11,8 +11,8 @@ define void @foo() nounwind ssp {
 entry:
 ; CHECK: mtctr r12
 ; CHECK: bctrl
-  %0 = load void (...)** @p, align 4              ; <void (...)*> [#uses=1]
-  call void (...)* %0() nounwind
+  %0 = load void (...)*, void (...)** @p, align 4              ; <void (...)*> [#uses=1]
+  call void (...) %0() nounwind
   br label %return
 
 return:                                           ; preds = %entry
diff --git a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
index a25ce07e83bf..1f320a84a4e6 100644
--- a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
+++ b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
@@ -12,11 +12,11 @@ entry:
   %0 = alloca i32
   %"alloca point" = bitcast i32 0 to i32
   store i32 0, i32* %0, align 4
-  %1 = load i32* %0, align 4
+  %1 = load i32, i32* %0, align 4
   store i32 %1, i32* %retval, align 4
   br label %return
 
 return:                                           ; preds = %entry
-  %retval1 = load i32* %retval
+  %retval1 = load i32, i32* %retval
   ret i32 %retval1
 }
diff --git a/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll b/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll
index e7bc5bfa37ec..e5920911ee2f 100644
--- a/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll
+++ b/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll
@@ -28,7 +28,7 @@ declare void @check(i32 %name) nounwind
 
 define i32 @s122(i32 %n1, i32 %n3) nounwind {
 entry:
-  %call = tail call i32 @init(i8* getelementptr inbounds ([6 x i8]* @.str11, i64 0, i64 0))
+  %call = tail call i32 @init(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str11, i64 0, i64 0))
   %call1 = tail call i64 @clock() nounwind
   %sub = add nsw i32 %n1, -1
   %cmp316 = icmp slt i32 %sub, 32000
@@ -46,10 +46,10 @@ for.body4.us:                                     ; preds = %for.body4.lr.ph.us,
   %sub5.us = sub i64 31999, %indvars.iv20
   %sext = shl i64 %sub5.us, 32
   %idxprom.us = ashr exact i64 %sext, 32
-  %arrayidx.us = getelementptr inbounds [32000 x float]* @b, i64 0, i64 %idxprom.us
-  %2 = load float* %arrayidx.us, align 4
-  %arrayidx7.us = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv
-  %3 = load float* %arrayidx7.us, align 4
+  %arrayidx.us = getelementptr inbounds [32000 x float], [32000 x float]* @b, i64 0, i64 %idxprom.us
+  %2 = load float, float* %arrayidx.us, align 4
+  %arrayidx7.us = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %indvars.iv
+  %3 = load float, float* %arrayidx7.us, align 4
   %add8.us = fadd float %3, %2
   store float %add8.us, float* %arrayidx7.us, align 4
   %indvars.iv.next = add i64 %indvars.iv, %1
@@ -66,12 +66,12 @@ for.end12:                                        ; preds = %for.end.7, %for.end
   %sub14 = sub nsw i64 %call13, %call1
   %conv = sitofp i64 %sub14 to double
   %div = fdiv double %conv, 1.000000e+06
-  %call15 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str152, i64 0, i64 0), double %div) nounwind
+  %call15 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str152, i64 0, i64 0), double %div) nounwind
   tail call void @check(i32 1)
   ret i32 0
 
 for.body4.lr.ph.us.1:                             ; preds = %for.body4.us
-  %call10.us = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
+  %call10.us = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
   br label %for.body4.us.1
 
 for.body4.us.1:                                   ; preds = %for.body4.us.1, %for.body4.lr.ph.us.1
@@ -81,10 +81,10 @@ for.body4.us.1:                                   ; preds = %for.body4.us.1, %fo
   %sub5.us.1 = sub i64 31999, %indvars.iv20.1
   %sext23 = shl i64 %sub5.us.1, 32
   %idxprom.us.1 = ashr exact i64 %sext23, 32
-  %arrayidx.us.1 = getelementptr inbounds [32000 x float]* @b, i64 0, i64 %idxprom.us.1
-  %5 = load float* %arrayidx.us.1, align 4
-  %arrayidx7.us.1 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv.1
-  %6 = load float* %arrayidx7.us.1, align 4
+  %arrayidx.us.1 = getelementptr inbounds [32000 x float], [32000 x float]* @b, i64 0, i64 %idxprom.us.1
+  %5 = load float, float* %arrayidx.us.1, align 4
+  %arrayidx7.us.1 = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %indvars.iv.1
+  %6 = load float, float* %arrayidx7.us.1, align 4
   %add8.us.1 = fadd float %6, %5
   store float %add8.us.1, float* %arrayidx7.us.1, align 4
   %indvars.iv.next.1 = add i64 %indvars.iv.1, %1
@@ -93,7 +93,7 @@ for.body4.us.1:                                   ; preds = %for.body4.us.1, %fo
   br i1 %cmp3.us.1, label %for.body4.us.1, label %for.body4.lr.ph.us.2
 
 for.body4.lr.ph.us.2:                             ; preds = %for.body4.us.1
-  %call10.us.1 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
+  %call10.us.1 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
   br label %for.body4.us.2
 
 for.body4.us.2:                                   ; preds = %for.body4.us.2, %for.body4.lr.ph.us.2
@@ -103,10 +103,10 @@ for.body4.us.2:                                   ; preds = %for.body4.us.2, %fo
   %sub5.us.2 = sub i64 31999, %indvars.iv20.2
   %sext24 = shl i64 %sub5.us.2, 32
   %idxprom.us.2 = ashr exact i64 %sext24, 32
-  %arrayidx.us.2 = getelementptr inbounds [32000 x float]* @b, i64 0, i64 %idxprom.us.2
-  %8 = load float* %arrayidx.us.2, align 4
-  %arrayidx7.us.2 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv.2
-  %9 = load float* %arrayidx7.us.2, align 4
+  %arrayidx.us.2 = getelementptr inbounds [32000 x float], [32000 x float]* @b, i64 0, i64 %idxprom.us.2
+  %8 = load float, float* %arrayidx.us.2, align 4
+  %arrayidx7.us.2 = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %indvars.iv.2
+  %9 = load float, float* %arrayidx7.us.2, align 4
   %add8.us.2 = fadd float %9, %8
   store float %add8.us.2, float* %arrayidx7.us.2, align 4
   %indvars.iv.next.2 = add i64 %indvars.iv.2, %1
@@ -115,7 +115,7 @@ for.body4.us.2:                                   ; preds = %for.body4.us.2, %fo
   br i1 %cmp3.us.2, label %for.body4.us.2, label %for.body4.lr.ph.us.3
 
 for.body4.lr.ph.us.3:                             ; preds = %for.body4.us.2
-  %call10.us.2 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
+  %call10.us.2 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
   br label %for.body4.us.3
 
 for.body4.us.3:                                   ; preds = %for.body4.us.3, %for.body4.lr.ph.us.3
@@ -125,10 +125,10 @@ for.body4.us.3:                                   ; preds = %for.body4.us.3, %fo
   %sub5.us.3 = sub i64 31999, %indvars.iv20.3
   %sext25 = shl i64 %sub5.us.3, 32
   %idxprom.us.3 = ashr exact i64 %sext25, 32
-  %arrayidx.us.3 = getelementptr inbounds [32000 x float]* @b, i64 0, i64 %idxprom.us.3
-  %11 = load float* %arrayidx.us.3, align 4
-  %arrayidx7.us.3 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv.3
-  %12 = load float* %arrayidx7.us.3, align 4
+  %arrayidx.us.3 = getelementptr inbounds [32000 x float], [32000 x float]* @b, i64 0, i64 %idxprom.us.3
+  %11 = load float, float* %arrayidx.us.3, align 4
+  %arrayidx7.us.3 = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %indvars.iv.3
+  %12 = load float, float* %arrayidx7.us.3, align 4
   %add8.us.3 = fadd float %12, %11
   store float %add8.us.3, float* %arrayidx7.us.3, align 4
   %indvars.iv.next.3 = add i64 %indvars.iv.3, %1
@@ -137,7 +137,7 @@ for.body4.us.3:                                   ; preds = %for.body4.us.3, %fo
   br i1 %cmp3.us.3, label %for.body4.us.3, label %for.body4.lr.ph.us.4
 
 for.body4.lr.ph.us.4:                             ; preds = %for.body4.us.3
-  %call10.us.3 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
+  %call10.us.3 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
   br label %for.body4.us.4
 
 for.body4.us.4:                                   ; preds = %for.body4.us.4, %for.body4.lr.ph.us.4
@@ -147,10 +147,10 @@ for.body4.us.4:                                   ; preds = %for.body4.us.4, %fo
   %sub5.us.4 = sub i64 31999, %indvars.iv20.4
   %sext26 = shl i64 %sub5.us.4, 32
   %idxprom.us.4 = ashr exact i64 %sext26, 32
-  %arrayidx.us.4 = getelementptr inbounds [32000 x float]* @b, i64 0, i64 %idxprom.us.4
-  %14 = load float* %arrayidx.us.4, align 4
-  %arrayidx7.us.4 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv.4
-  %15 = load float* %arrayidx7.us.4, align 4
+  %arrayidx.us.4 = getelementptr inbounds [32000 x float], [32000 x float]* @b, i64 0, i64 %idxprom.us.4
+  %14 = load float, float* %arrayidx.us.4, align 4
+  %arrayidx7.us.4 = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %indvars.iv.4
+  %15 = load float, float* %arrayidx7.us.4, align 4
   %add8.us.4 = fadd float %15, %14
   store float %add8.us.4, float* %arrayidx7.us.4, align 4
   %indvars.iv.next.4 = add i64 %indvars.iv.4, %1
@@ -159,21 +159,21 @@ for.body4.us.4:                                   ; preds = %for.body4.us.4, %fo
   br i1 %cmp3.us.4, label %for.body4.us.4, label %for.end.us.4
 
 for.end.us.4:                                     ; preds = %for.body4.us.4
-  %call10.us.4 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
+  %call10.us.4 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
   %inc.us.4 = add nsw i32 %nl.019.us, 5
   %exitcond.4 = icmp eq i32 %inc.us.4, 200000
   br i1 %exitcond.4, label %for.end12, label %for.body4.lr.ph.us
 
 for.end.7:                                        ; preds = %entry, %for.end.7
   %nl.019 = phi i32 [ %inc.7, %for.end.7 ], [ 0, %entry ]
-  %call10 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %call10.1 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %call10.2 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %call10.3 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %call10.4 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %call10.5 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %call10.6 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %call10.7 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
+  %call10 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
+  %call10.1 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
+  %call10.2 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
+  %call10.3 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
+  %call10.4 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
+  %call10.5 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
+  %call10.6 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
+  %call10.7 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
   %inc.7 = add nsw i32 %nl.019, 8
   %exitcond.7 = icmp eq i32 %inc.7, 200000
   br i1 %exitcond.7, label %for.end12, label %for.end.7
diff --git a/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll b/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll
index a6223d41cc3f..93476827949f 100644
--- a/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll
+++ b/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll
@@ -29,13 +29,13 @@ declare void @check(i32 %name) nounwind
 
 define i32 @s3110() nounwind {
 entry:
-  %call = tail call i32 @init(i8* getelementptr inbounds ([6 x i8]* @.str81, i64 0, i64 0))
+  %call = tail call i32 @init(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str81, i64 0, i64 0))
   %call1 = tail call i64 @clock() nounwind
   br label %for.body
 
 for.body:                                         ; preds = %for.end17, %entry
   %nl.041 = phi i32 [ 0, %entry ], [ %inc22, %for.end17 ]
-  %0 = load float* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0, i64 0), align 16
+  %0 = load float, float* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0, i64 0), align 16
   br label %for.cond5.preheader
 
 for.cond5.preheader:                              ; preds = %for.inc15, %for.body
@@ -50,8 +50,8 @@ for.body7:                                        ; preds = %for.body7, %for.con
   %max.235 = phi float [ %max.139, %for.cond5.preheader ], [ %max.3.15, %for.body7 ]
   %xindex.234 = phi i32 [ %xindex.138, %for.cond5.preheader ], [ %xindex.3.15, %for.body7 ]
   %yindex.233 = phi i32 [ %yindex.137, %for.cond5.preheader ], [ %yindex.3.15, %for.body7 ]
-  %arrayidx9 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv
-  %1 = load float* %arrayidx9, align 16
+  %arrayidx9 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv
+  %1 = load float, float* %arrayidx9, align 16
   %cmp10 = fcmp ogt float %1, %max.235
   %2 = trunc i64 %indvars.iv to i32
   %yindex.3 = select i1 %cmp10, i32 %2, i32 %yindex.233
@@ -59,120 +59,120 @@ for.body7:                                        ; preds = %for.body7, %for.con
   %xindex.3 = select i1 %cmp10, i32 %3, i32 %xindex.234
   %max.3 = select i1 %cmp10, float %1, float %max.235
   %indvars.iv.next45 = or i64 %indvars.iv, 1
-  %arrayidx9.1 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next45
-  %4 = load float* %arrayidx9.1, align 4
+  %arrayidx9.1 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next45
+  %4 = load float, float* %arrayidx9.1, align 4
   %cmp10.1 = fcmp ogt float %4, %max.3
   %5 = trunc i64 %indvars.iv.next45 to i32
   %yindex.3.1 = select i1 %cmp10.1, i32 %5, i32 %yindex.3
   %xindex.3.1 = select i1 %cmp10.1, i32 %3, i32 %xindex.3
   %max.3.1 = select i1 %cmp10.1, float %4, float %max.3
   %indvars.iv.next.146 = or i64 %indvars.iv, 2
-  %arrayidx9.2 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.146
-  %6 = load float* %arrayidx9.2, align 8
+  %arrayidx9.2 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.146
+  %6 = load float, float* %arrayidx9.2, align 8
   %cmp10.2 = fcmp ogt float %6, %max.3.1
   %7 = trunc i64 %indvars.iv.next.146 to i32
   %yindex.3.2 = select i1 %cmp10.2, i32 %7, i32 %yindex.3.1
   %xindex.3.2 = select i1 %cmp10.2, i32 %3, i32 %xindex.3.1
   %max.3.2 = select i1 %cmp10.2, float %6, float %max.3.1
   %indvars.iv.next.247 = or i64 %indvars.iv, 3
-  %arrayidx9.3 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.247
-  %8 = load float* %arrayidx9.3, align 4
+  %arrayidx9.3 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.247
+  %8 = load float, float* %arrayidx9.3, align 4
   %cmp10.3 = fcmp ogt float %8, %max.3.2
   %9 = trunc i64 %indvars.iv.next.247 to i32
   %yindex.3.3 = select i1 %cmp10.3, i32 %9, i32 %yindex.3.2
   %xindex.3.3 = select i1 %cmp10.3, i32 %3, i32 %xindex.3.2
   %max.3.3 = select i1 %cmp10.3, float %8, float %max.3.2
   %indvars.iv.next.348 = or i64 %indvars.iv, 4
-  %arrayidx9.4 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.348
-  %10 = load float* %arrayidx9.4, align 16
+  %arrayidx9.4 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.348
+  %10 = load float, float* %arrayidx9.4, align 16
   %cmp10.4 = fcmp ogt float %10, %max.3.3
   %11 = trunc i64 %indvars.iv.next.348 to i32
   %yindex.3.4 = select i1 %cmp10.4, i32 %11, i32 %yindex.3.3
   %xindex.3.4 = select i1 %cmp10.4, i32 %3, i32 %xindex.3.3
   %max.3.4 = select i1 %cmp10.4, float %10, float %max.3.3
   %indvars.iv.next.449 = or i64 %indvars.iv, 5
-  %arrayidx9.5 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.449
-  %12 = load float* %arrayidx9.5, align 4
+  %arrayidx9.5 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.449
+  %12 = load float, float* %arrayidx9.5, align 4
   %cmp10.5 = fcmp ogt float %12, %max.3.4
   %13 = trunc i64 %indvars.iv.next.449 to i32
   %yindex.3.5 = select i1 %cmp10.5, i32 %13, i32 %yindex.3.4
   %xindex.3.5 = select i1 %cmp10.5, i32 %3, i32 %xindex.3.4
   %max.3.5 = select i1 %cmp10.5, float %12, float %max.3.4
   %indvars.iv.next.550 = or i64 %indvars.iv, 6
-  %arrayidx9.6 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.550
-  %14 = load float* %arrayidx9.6, align 8
+  %arrayidx9.6 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.550
+  %14 = load float, float* %arrayidx9.6, align 8
   %cmp10.6 = fcmp ogt float %14, %max.3.5
   %15 = trunc i64 %indvars.iv.next.550 to i32
   %yindex.3.6 = select i1 %cmp10.6, i32 %15, i32 %yindex.3.5
   %xindex.3.6 = select i1 %cmp10.6, i32 %3, i32 %xindex.3.5
   %max.3.6 = select i1 %cmp10.6, float %14, float %max.3.5
   %indvars.iv.next.651 = or i64 %indvars.iv, 7
-  %arrayidx9.7 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.651
-  %16 = load float* %arrayidx9.7, align 4
+  %arrayidx9.7 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.651
+  %16 = load float, float* %arrayidx9.7, align 4
   %cmp10.7 = fcmp ogt float %16, %max.3.6
   %17 = trunc i64 %indvars.iv.next.651 to i32
   %yindex.3.7 = select i1 %cmp10.7, i32 %17, i32 %yindex.3.6
   %xindex.3.7 = select i1 %cmp10.7, i32 %3, i32 %xindex.3.6
   %max.3.7 = select i1 %cmp10.7, float %16, float %max.3.6
   %indvars.iv.next.752 = or i64 %indvars.iv, 8
-  %arrayidx9.8 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.752
-  %18 = load float* %arrayidx9.8, align 16
+  %arrayidx9.8 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.752
+  %18 = load float, float* %arrayidx9.8, align 16
   %cmp10.8 = fcmp ogt float %18, %max.3.7
   %19 = trunc i64 %indvars.iv.next.752 to i32
   %yindex.3.8 = select i1 %cmp10.8, i32 %19, i32 %yindex.3.7
   %xindex.3.8 = select i1 %cmp10.8, i32 %3, i32 %xindex.3.7
   %max.3.8 = select i1 %cmp10.8, float %18, float %max.3.7
   %indvars.iv.next.853 = or i64 %indvars.iv, 9
-  %arrayidx9.9 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.853
-  %20 = load float* %arrayidx9.9, align 4
+  %arrayidx9.9 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.853
+  %20 = load float, float* %arrayidx9.9, align 4
   %cmp10.9 = fcmp ogt float %20, %max.3.8
   %21 = trunc i64 %indvars.iv.next.853 to i32
   %yindex.3.9 = select i1 %cmp10.9, i32 %21, i32 %yindex.3.8
   %xindex.3.9 = select i1 %cmp10.9, i32 %3, i32 %xindex.3.8
   %max.3.9 = select i1 %cmp10.9, float %20, float %max.3.8
   %indvars.iv.next.954 = or i64 %indvars.iv, 10
-  %arrayidx9.10 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.954
-  %22 = load float* %arrayidx9.10, align 8
+  %arrayidx9.10 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.954
+  %22 = load float, float* %arrayidx9.10, align 8
   %cmp10.10 = fcmp ogt float %22, %max.3.9
   %23 = trunc i64 %indvars.iv.next.954 to i32
   %yindex.3.10 = select i1 %cmp10.10, i32 %23, i32 %yindex.3.9
   %xindex.3.10 = select i1 %cmp10.10, i32 %3, i32 %xindex.3.9
   %max.3.10 = select i1 %cmp10.10, float %22, float %max.3.9
   %indvars.iv.next.1055 = or i64 %indvars.iv, 11
-  %arrayidx9.11 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1055
-  %24 = load float* %arrayidx9.11, align 4
+  %arrayidx9.11 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1055
+  %24 = load float, float* %arrayidx9.11, align 4
   %cmp10.11 = fcmp ogt float %24, %max.3.10
   %25 = trunc i64 %indvars.iv.next.1055 to i32
   %yindex.3.11 = select i1 %cmp10.11, i32 %25, i32 %yindex.3.10
   %xindex.3.11 = select i1 %cmp10.11, i32 %3, i32 %xindex.3.10
   %max.3.11 = select i1 %cmp10.11, float %24, float %max.3.10
   %indvars.iv.next.1156 = or i64 %indvars.iv, 12
-  %arrayidx9.12 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1156
-  %26 = load float* %arrayidx9.12, align 16
+  %arrayidx9.12 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1156
+  %26 = load float, float* %arrayidx9.12, align 16
   %cmp10.12 = fcmp ogt float %26, %max.3.11
   %27 = trunc i64 %indvars.iv.next.1156 to i32
   %yindex.3.12 = select i1 %cmp10.12, i32 %27, i32 %yindex.3.11
   %xindex.3.12 = select i1 %cmp10.12, i32 %3, i32 %xindex.3.11
   %max.3.12 = select i1 %cmp10.12, float %26, float %max.3.11
   %indvars.iv.next.1257 = or i64 %indvars.iv, 13
-  %arrayidx9.13 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1257
-  %28 = load float* %arrayidx9.13, align 4
+  %arrayidx9.13 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1257
+  %28 = load float, float* %arrayidx9.13, align 4
   %cmp10.13 = fcmp ogt float %28, %max.3.12
   %29 = trunc i64 %indvars.iv.next.1257 to i32
   %yindex.3.13 = select i1 %cmp10.13, i32 %29, i32 %yindex.3.12
   %xindex.3.13 = select i1 %cmp10.13, i32 %3, i32 %xindex.3.12
   %max.3.13 = select i1 %cmp10.13, float %28, float %max.3.12
   %indvars.iv.next.1358 = or i64 %indvars.iv, 14
-  %arrayidx9.14 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1358
-  %30 = load float* %arrayidx9.14, align 8
+  %arrayidx9.14 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1358
+  %30 = load float, float* %arrayidx9.14, align 8
   %cmp10.14 = fcmp ogt float %30, %max.3.13
   %31 = trunc i64 %indvars.iv.next.1358 to i32
   %yindex.3.14 = select i1 %cmp10.14, i32 %31, i32 %yindex.3.13
   %xindex.3.14 = select i1 %cmp10.14, i32 %3, i32 %xindex.3.13
   %max.3.14 = select i1 %cmp10.14, float %30, float %max.3.13
   %indvars.iv.next.1459 = or i64 %indvars.iv, 15
-  %arrayidx9.15 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1459
-  %32 = load float* %arrayidx9.15, align 4
+  %arrayidx9.15 = getelementptr inbounds [256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1459
+  %32 = load float, float* %arrayidx9.15, align 4
   %cmp10.15 = fcmp ogt float %32, %max.3.14
   %33 = trunc i64 %indvars.iv.next.1459 to i32
   %yindex.3.15 = select i1 %cmp10.15, i32 %33, i32 %yindex.3.14
@@ -194,7 +194,7 @@ for.end17:                                        ; preds = %for.inc15
   %add = fadd float %max.3.15, %conv
   %conv18 = sitofp i32 %yindex.3.15 to float
   %add19 = fadd float %add, %conv18
-  %call20 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float %add19) nounwind
+  %call20 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float %add19) nounwind
   %inc22 = add nsw i32 %nl.041, 1
   %exitcond44 = icmp eq i32 %inc22, 78100
   br i1 %exitcond44, label %for.end23, label %for.body
@@ -204,7 +204,7 @@ for.end23:                                        ; preds = %for.end17
   %sub = sub nsw i64 %call24, %call1
   %conv25 = sitofp i64 %sub to double
   %div = fdiv double %conv25, 1.000000e+06
-  %call26 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([15 x i8]* @.str235, i64 0, i64 0), double %div) nounwind
+  %call26 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @.str235, i64 0, i64 0), double %div) nounwind
   %add29 = fadd float %add, 1.000000e+00
   %add31 = fadd float %add29, %conv18
   %add32 = fadd float %add31, 1.000000e+00
diff --git a/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll b/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll
index b1cbb36fe041..05390cf8b92e 100644
--- a/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll
+++ b/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll
@@ -2,7 +2,7 @@
 
 define void @test(i32* nocapture %x, i64* %xx, i32* %yp) nounwind uwtable ssp {
 entry:
-  %yy = load i32* %yp
+  %yy = load i32, i32* %yp
   %y = add i32 %yy, 1
   %z = zext i32 %y to i64
   %z2 = shl i64 %z, 32 
diff --git a/test/CodeGen/PowerPC/2012-09-16-TOC-entry-check.ll b/test/CodeGen/PowerPC/2012-09-16-TOC-entry-check.ll
index 5bff58f2bbf5..1d45c2e73455 100644
--- a/test/CodeGen/PowerPC/2012-09-16-TOC-entry-check.ll
+++ b/test/CodeGen/PowerPC/2012-09-16-TOC-entry-check.ll
@@ -19,9 +19,9 @@ define i32 @foo(double %X, double %Y) nounwind readnone {
 }
 
 ; Check the creation of 2 .tc entries for both double constants. They
-; should be .LC1 and .LC3 to avoid name clash with global constants
-; .LC0 and .LC2
-; CHECK: .LC{{[13]}}:
+; avoid name clash with global constants .LC0 and .LC2
+; CHECK: .section	.toc,"aw",@progbits
+; CHECK: .LC{{.*}}:
 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
-; CHECK: .LC{{[13]}}:
+; CHECK: .LC{{.*}}:
 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
diff --git a/test/CodeGen/PowerPC/2013-05-15-preinc-fold.ll b/test/CodeGen/PowerPC/2013-05-15-preinc-fold.ll
index 542a766300ef..9fe88a85d15f 100644
--- a/test/CodeGen/PowerPC/2013-05-15-preinc-fold.ll
+++ b/test/CodeGen/PowerPC/2013-05-15-preinc-fold.ll
@@ -5,9 +5,9 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define i8* @test(i8* %base, i8 %val) {
 entry:
-  %arrayidx = getelementptr inbounds i8* %base, i32 -1
+  %arrayidx = getelementptr inbounds i8, i8* %base, i32 -1
   store i8 %val, i8* %arrayidx, align 1
-  %arrayidx2 = getelementptr inbounds i8* %base, i32 1
+  %arrayidx2 = getelementptr inbounds i8, i8* %base, i32 1
   store i8 %val, i8* %arrayidx2, align 1
   ret i8* %arrayidx
 }
@@ -19,9 +19,9 @@ entry:
 
 define i64* @test64(i64* %base, i64 %val) {
 entry:
-  %arrayidx = getelementptr inbounds i64* %base, i32 -1
+  %arrayidx = getelementptr inbounds i64, i64* %base, i32 -1
   store i64 %val, i64* %arrayidx, align 8
-  %arrayidx2 = getelementptr inbounds i64* %base, i32 1
+  %arrayidx2 = getelementptr inbounds i64, i64* %base, i32 1
   store i64 %val, i64* %arrayidx2, align 8
   ret i64* %arrayidx
 }
diff --git a/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.ll b/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.ll
index 9bf25c8ffe49..3c6f3ff32454 100644
--- a/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.ll
+++ b/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.ll
@@ -10,17 +10,17 @@ target triple = "powerpc64-unknown-linux-gnu"
 ; Function Attrs: nounwind
 define fastcc void @func_7() #0 {
 entry:
-  %arrayidx638 = getelementptr inbounds [3 x [1 x i32]]* undef, i64 0, i64 1, i64 0
+  %arrayidx638 = getelementptr inbounds [3 x [1 x i32]], [3 x [1 x i32]]* undef, i64 0, i64 1, i64 0
   br i1 undef, label %for.cond940, label %if.end1018
 
 for.cond940:                                      ; preds = %for.cond940, %if.else876
-  %l_655.1 = phi i32* [ getelementptr inbounds ([8 x i32]* @g_51, i64 0, i64 6), %entry ], [ %l_654.0, %for.cond940 ]
+  %l_655.1 = phi i32* [ getelementptr inbounds ([8 x i32], [8 x i32]* @g_51, i64 0, i64 6), %entry ], [ %l_654.0, %for.cond940 ]
   %l_654.0 = phi i32* [ null, %entry ], [ %arrayidx638, %for.cond940 ]
   %exitcond = icmp eq i32 undef, 20
   br i1 %exitcond, label %if.end1018, label %for.cond940
 
 if.end1018:                                       ; preds = %for.end957, %for.end834
-  %l_655.3.ph33 = phi i32* [ %l_655.1, %for.cond940 ], [ getelementptr inbounds ([8 x i32]* @g_51, i64 0, i64 6), %entry ]
+  %l_655.3.ph33 = phi i32* [ %l_655.1, %for.cond940 ], [ getelementptr inbounds ([8 x i32], [8 x i32]* @g_51, i64 0, i64 6), %entry ]
   store i32 0, i32* %l_655.3.ph33, align 4
   ret void
 }
diff --git a/test/CodeGen/PowerPC/Atomics-64.ll b/test/CodeGen/PowerPC/Atomics-64.ll
index 122b54e080ac..77066de25e78 100644
--- a/test/CodeGen/PowerPC/Atomics-64.ll
+++ b/test/CodeGen/PowerPC/Atomics-64.ll
@@ -254,272 +254,272 @@ return:                                           ; preds = %entry
 
 define void @test_op_and_fetch() nounwind {
 entry:
-  %0 = load i8* @uc, align 1
+  %0 = load i8, i8* @uc, align 1
   %1 = atomicrmw add i8* @sc, i8 %0 monotonic
   %2 = add i8 %1, %0
   store i8 %2, i8* @sc, align 1
-  %3 = load i8* @uc, align 1
+  %3 = load i8, i8* @uc, align 1
   %4 = atomicrmw add i8* @uc, i8 %3 monotonic
   %5 = add i8 %4, %3
   store i8 %5, i8* @uc, align 1
-  %6 = load i8* @uc, align 1
+  %6 = load i8, i8* @uc, align 1
   %7 = zext i8 %6 to i16
   %8 = bitcast i8* bitcast (i16* @ss to i8*) to i16*
   %9 = atomicrmw add i16* %8, i16 %7 monotonic
   %10 = add i16 %9, %7
   store i16 %10, i16* @ss, align 2
-  %11 = load i8* @uc, align 1
+  %11 = load i8, i8* @uc, align 1
   %12 = zext i8 %11 to i16
   %13 = bitcast i8* bitcast (i16* @us to i8*) to i16*
   %14 = atomicrmw add i16* %13, i16 %12 monotonic
   %15 = add i16 %14, %12
   store i16 %15, i16* @us, align 2
-  %16 = load i8* @uc, align 1
+  %16 = load i8, i8* @uc, align 1
   %17 = zext i8 %16 to i32
   %18 = bitcast i8* bitcast (i32* @si to i8*) to i32*
   %19 = atomicrmw add i32* %18, i32 %17 monotonic
   %20 = add i32 %19, %17
   store i32 %20, i32* @si, align 4
-  %21 = load i8* @uc, align 1
+  %21 = load i8, i8* @uc, align 1
   %22 = zext i8 %21 to i32
   %23 = bitcast i8* bitcast (i32* @ui to i8*) to i32*
   %24 = atomicrmw add i32* %23, i32 %22 monotonic
   %25 = add i32 %24, %22
   store i32 %25, i32* @ui, align 4
-  %26 = load i8* @uc, align 1
+  %26 = load i8, i8* @uc, align 1
   %27 = zext i8 %26 to i64
   %28 = bitcast i8* bitcast (i64* @sl to i8*) to i64*
   %29 = atomicrmw add i64* %28, i64 %27 monotonic
   %30 = add i64 %29, %27
   store i64 %30, i64* @sl, align 8
-  %31 = load i8* @uc, align 1
+  %31 = load i8, i8* @uc, align 1
   %32 = zext i8 %31 to i64
   %33 = bitcast i8* bitcast (i64* @ul to i8*) to i64*
   %34 = atomicrmw add i64* %33, i64 %32 monotonic
   %35 = add i64 %34, %32
   store i64 %35, i64* @ul, align 8
-  %36 = load i8* @uc, align 1
+  %36 = load i8, i8* @uc, align 1
   %37 = atomicrmw sub i8* @sc, i8 %36 monotonic
   %38 = sub i8 %37, %36
   store i8 %38, i8* @sc, align 1
-  %39 = load i8* @uc, align 1
+  %39 = load i8, i8* @uc, align 1
   %40 = atomicrmw sub i8* @uc, i8 %39 monotonic
   %41 = sub i8 %40, %39
   store i8 %41, i8* @uc, align 1
-  %42 = load i8* @uc, align 1
+  %42 = load i8, i8* @uc, align 1
   %43 = zext i8 %42 to i16
   %44 = bitcast i8* bitcast (i16* @ss to i8*) to i16*
   %45 = atomicrmw sub i16* %44, i16 %43 monotonic
   %46 = sub i16 %45, %43
   store i16 %46, i16* @ss, align 2
-  %47 = load i8* @uc, align 1
+  %47 = load i8, i8* @uc, align 1
   %48 = zext i8 %47 to i16
   %49 = bitcast i8* bitcast (i16* @us to i8*) to i16*
   %50 = atomicrmw sub i16* %49, i16 %48 monotonic
   %51 = sub i16 %50, %48
   store i16 %51, i16* @us, align 2
-  %52 = load i8* @uc, align 1
+  %52 = load i8, i8* @uc, align 1
   %53 = zext i8 %52 to i32
   %54 = bitcast i8* bitcast (i32* @si to i8*) to i32*
   %55 = atomicrmw sub i32* %54, i32 %53 monotonic
   %56 = sub i32 %55, %53
   store i32 %56, i32* @si, align 4
-  %57 = load i8* @uc, align 1
+  %57 = load i8, i8* @uc, align 1
   %58 = zext i8 %57 to i32
   %59 = bitcast i8* bitcast (i32* @ui to i8*) to i32*
   %60 = atomicrmw sub i32* %59, i32 %58 monotonic
   %61 = sub i32 %60, %58
   store i32 %61, i32* @ui, align 4
-  %62 = load i8* @uc, align 1
+  %62 = load i8, i8* @uc, align 1
   %63 = zext i8 %62 to i64
   %64 = bitcast i8* bitcast (i64* @sl to i8*) to i64*
   %65 = atomicrmw sub i64* %64, i64 %63 monotonic
   %66 = sub i64 %65, %63
   store i64 %66, i64* @sl, align 8
-  %67 = load i8* @uc, align 1
+  %67 = load i8, i8* @uc, align 1
   %68 = zext i8 %67 to i64
   %69 = bitcast i8* bitcast (i64* @ul to i8*) to i64*
   %70 = atomicrmw sub i64* %69, i64 %68 monotonic
   %71 = sub i64 %70, %68
   store i64 %71, i64* @ul, align 8
-  %72 = load i8* @uc, align 1
+  %72 = load i8, i8* @uc, align 1
   %73 = atomicrmw or i8* @sc, i8 %72 monotonic
   %74 = or i8 %73, %72
   store i8 %74, i8* @sc, align 1
-  %75 = load i8* @uc, align 1
+  %75 = load i8, i8* @uc, align 1
   %76 = atomicrmw or i8* @uc, i8 %75 monotonic
   %77 = or i8 %76, %75
   store i8 %77, i8* @uc, align 1
-  %78 = load i8* @uc, align 1
+  %78 = load i8, i8* @uc, align 1
   %79 = zext i8 %78 to i16
   %80 = bitcast i8* bitcast (i16* @ss to i8*) to i16*
   %81 = atomicrmw or i16* %80, i16 %79 monotonic
   %82 = or i16 %81, %79
   store i16 %82, i16* @ss, align 2
-  %83 = load i8* @uc, align 1
+  %83 = load i8, i8* @uc, align 1
   %84 = zext i8 %83 to i16
   %85 = bitcast i8* bitcast (i16* @us to i8*) to i16*
   %86 = atomicrmw or i16* %85, i16 %84 monotonic
   %87 = or i16 %86, %84
   store i16 %87, i16* @us, align 2
-  %88 = load i8* @uc, align 1
+  %88 = load i8, i8* @uc, align 1
   %89 = zext i8 %88 to i32
   %90 = bitcast i8* bitcast (i32* @si to i8*) to i32*
   %91 = atomicrmw or i32* %90, i32 %89 monotonic
   %92 = or i32 %91, %89
   store i32 %92, i32* @si, align 4
-  %93 = load i8* @uc, align 1
+  %93 = load i8, i8* @uc, align 1
   %94 = zext i8 %93 to i32
   %95 = bitcast i8* bitcast (i32* @ui to i8*) to i32*
   %96 = atomicrmw or i32* %95, i32 %94 monotonic
   %97 = or i32 %96, %94
   store i32 %97, i32* @ui, align 4
-  %98 = load i8* @uc, align 1
+  %98 = load i8, i8* @uc, align 1
   %99 = zext i8 %98 to i64
   %100 = bitcast i8* bitcast (i64* @sl to i8*) to i64*
   %101 = atomicrmw or i64* %100, i64 %99 monotonic
   %102 = or i64 %101, %99
   store i64 %102, i64* @sl, align 8
-  %103 = load i8* @uc, align 1
+  %103 = load i8, i8* @uc, align 1
   %104 = zext i8 %103 to i64
   %105 = bitcast i8* bitcast (i64* @ul to i8*) to i64*
   %106 = atomicrmw or i64* %105, i64 %104 monotonic
   %107 = or i64 %106, %104
   store i64 %107, i64* @ul, align 8
-  %108 = load i8* @uc, align 1
+  %108 = load i8, i8* @uc, align 1
   %109 = atomicrmw xor i8* @sc, i8 %108 monotonic
   %110 = xor i8 %109, %108
   store i8 %110, i8* @sc, align 1
-  %111 = load i8* @uc, align 1
+  %111 = load i8, i8* @uc, align 1
   %112 = atomicrmw xor i8* @uc, i8 %111 monotonic
   %113 = xor i8 %112, %111
   store i8 %113, i8* @uc, align 1
-  %114 = load i8* @uc, align 1
+  %114 = load i8, i8* @uc, align 1
   %115 = zext i8 %114 to i16
   %116 = bitcast i8* bitcast (i16* @ss to i8*) to i16*
   %117 = atomicrmw xor i16* %116, i16 %115 monotonic
   %118 = xor i16 %117, %115
   store i16 %118, i16* @ss, align 2
-  %119 = load i8* @uc, align 1
+  %119 = load i8, i8* @uc, align 1
   %120 = zext i8 %119 to i16
   %121 = bitcast i8* bitcast (i16* @us to i8*) to i16*
   %122 = atomicrmw xor i16* %121, i16 %120 monotonic
   %123 = xor i16 %122, %120
   store i16 %123, i16* @us, align 2
-  %124 = load i8* @uc, align 1
+  %124 = load i8, i8* @uc, align 1
   %125 = zext i8 %124 to i32
   %126 = bitcast i8* bitcast (i32* @si to i8*) to i32*
   %127 = atomicrmw xor i32* %126, i32 %125 monotonic
   %128 = xor i32 %127, %125
   store i32 %128, i32* @si, align 4
-  %129 = load i8* @uc, align 1
+  %129 = load i8, i8* @uc, align 1
   %130 = zext i8 %129 to i32
   %131 = bitcast i8* bitcast (i32* @ui to i8*) to i32*
   %132 = atomicrmw xor i32* %131, i32 %130 monotonic
   %133 = xor i32 %132, %130
   store i32 %133, i32* @ui, align 4
-  %134 = load i8* @uc, align 1
+  %134 = load i8, i8* @uc, align 1
   %135 = zext i8 %134 to i64
   %136 = bitcast i8* bitcast (i64* @sl to i8*) to i64*
   %137 = atomicrmw xor i64* %136, i64 %135 monotonic
   %138 = xor i64 %137, %135
   store i64 %138, i64* @sl, align 8
-  %139 = load i8* @uc, align 1
+  %139 = load i8, i8* @uc, align 1
   %140 = zext i8 %139 to i64
   %141 = bitcast i8* bitcast (i64* @ul to i8*) to i64*
   %142 = atomicrmw xor i64* %141, i64 %140 monotonic
   %143 = xor i64 %142, %140
   store i64 %143, i64* @ul, align 8
-  %144 = load i8* @uc, align 1
+  %144 = load i8, i8* @uc, align 1
   %145 = atomicrmw and i8* @sc, i8 %144 monotonic
   %146 = and i8 %145, %144
   store i8 %146, i8* @sc, align 1
-  %147 = load i8* @uc, align 1
+  %147 = load i8, i8* @uc, align 1
   %148 = atomicrmw and i8* @uc, i8 %147 monotonic
   %149 = and i8 %148, %147
   store i8 %149, i8* @uc, align 1
-  %150 = load i8* @uc, align 1
+  %150 = load i8, i8* @uc, align 1
   %151 = zext i8 %150 to i16
   %152 = bitcast i8* bitcast (i16* @ss to i8*) to i16*
   %153 = atomicrmw and i16* %152, i16 %151 monotonic
   %154 = and i16 %153, %151
   store i16 %154, i16* @ss, align 2
-  %155 = load i8* @uc, align 1
+  %155 = load i8, i8* @uc, align 1
   %156 = zext i8 %155 to i16
   %157 = bitcast i8* bitcast (i16* @us to i8*) to i16*
   %158 = atomicrmw and i16* %157, i16 %156 monotonic
   %159 = and i16 %158, %156
   store i16 %159, i16* @us, align 2
-  %160 = load i8* @uc, align 1
+  %160 = load i8, i8* @uc, align 1
   %161 = zext i8 %160 to i32
   %162 = bitcast i8* bitcast (i32* @si to i8*) to i32*
   %163 = atomicrmw and i32* %162, i32 %161 monotonic
   %164 = and i32 %163, %161
   store i32 %164, i32* @si, align 4
-  %165 = load i8* @uc, align 1
+  %165 = load i8, i8* @uc, align 1
   %166 = zext i8 %165 to i32
   %167 = bitcast i8* bitcast (i32* @ui to i8*) to i32*
   %168 = atomicrmw and i32* %167, i32 %166 monotonic
   %169 = and i32 %168, %166
   store i32 %169, i32* @ui, align 4
-  %170 = load i8* @uc, align 1
+  %170 = load i8, i8* @uc, align 1
   %171 = zext i8 %170 to i64
   %172 = bitcast i8* bitcast (i64* @sl to i8*) to i64*
   %173 = atomicrmw and i64* %172, i64 %171 monotonic
   %174 = and i64 %173, %171
   store i64 %174, i64* @sl, align 8
-  %175 = load i8* @uc, align 1
+  %175 = load i8, i8* @uc, align 1
   %176 = zext i8 %175 to i64
   %177 = bitcast i8* bitcast (i64* @ul to i8*) to i64*
   %178 = atomicrmw and i64* %177, i64 %176 monotonic
   %179 = and i64 %178, %176
   store i64 %179, i64* @ul, align 8
-  %180 = load i8* @uc, align 1
+  %180 = load i8, i8* @uc, align 1
   %181 = atomicrmw nand i8* @sc, i8 %180 monotonic
   %182 = xor i8 %181, -1
   %183 = and i8 %182, %180
   store i8 %183, i8* @sc, align 1
-  %184 = load i8* @uc, align 1
+  %184 = load i8, i8* @uc, align 1
   %185 = atomicrmw nand i8* @uc, i8 %184 monotonic
   %186 = xor i8 %185, -1
   %187 = and i8 %186, %184
   store i8 %187, i8* @uc, align 1
-  %188 = load i8* @uc, align 1
+  %188 = load i8, i8* @uc, align 1
   %189 = zext i8 %188 to i16
   %190 = bitcast i8* bitcast (i16* @ss to i8*) to i16*
   %191 = atomicrmw nand i16* %190, i16 %189 monotonic
   %192 = xor i16 %191, -1
   %193 = and i16 %192, %189
   store i16 %193, i16* @ss, align 2
-  %194 = load i8* @uc, align 1
+  %194 = load i8, i8* @uc, align 1
   %195 = zext i8 %194 to i16
   %196 = bitcast i8* bitcast (i16* @us to i8*) to i16*
   %197 = atomicrmw nand i16* %196, i16 %195 monotonic
   %198 = xor i16 %197, -1
   %199 = and i16 %198, %195
   store i16 %199, i16* @us, align 2
-  %200 = load i8* @uc, align 1
+  %200 = load i8, i8* @uc, align 1
   %201 = zext i8 %200 to i32
   %202 = bitcast i8* bitcast (i32* @si to i8*) to i32*
   %203 = atomicrmw nand i32* %202, i32 %201 monotonic
   %204 = xor i32 %203, -1
   %205 = and i32 %204, %201
   store i32 %205, i32* @si, align 4
-  %206 = load i8* @uc, align 1
+  %206 = load i8, i8* @uc, align 1
   %207 = zext i8 %206 to i32
   %208 = bitcast i8* bitcast (i32* @ui to i8*) to i32*
   %209 = atomicrmw nand i32* %208, i32 %207 monotonic
   %210 = xor i32 %209, -1
   %211 = and i32 %210, %207
   store i32 %211, i32* @ui, align 4
-  %212 = load i8* @uc, align 1
+  %212 = load i8, i8* @uc, align 1
   %213 = zext i8 %212 to i64
   %214 = bitcast i8* bitcast (i64* @sl to i8*) to i64*
   %215 = atomicrmw nand i64* %214, i64 %213 monotonic
   %216 = xor i64 %215, -1
   %217 = and i64 %216, %213
   store i64 %217, i64* @sl, align 8
-  %218 = load i8* @uc, align 1
+  %218 = load i8, i8* @uc, align 1
   %219 = zext i8 %218 to i64
   %220 = bitcast i8* bitcast (i64* @ul to i8*) to i64*
   %221 = atomicrmw nand i64* %220, i64 %219 monotonic
@@ -534,73 +534,73 @@ return:                                           ; preds = %entry
 
 define void @test_compare_and_swap() nounwind {
 entry:
-  %0 = load i8* @uc, align 1
-  %1 = load i8* @sc, align 1
+  %0 = load i8, i8* @uc, align 1
+  %1 = load i8, i8* @sc, align 1
   %2 = cmpxchg i8* @sc, i8 %0, i8 %1 monotonic monotonic
   store i8 %2, i8* @sc, align 1
-  %3 = load i8* @uc, align 1
-  %4 = load i8* @sc, align 1
+  %3 = load i8, i8* @uc, align 1
+  %4 = load i8, i8* @sc, align 1
   %5 = cmpxchg i8* @uc, i8 %3, i8 %4 monotonic monotonic
   store i8 %5, i8* @uc, align 1
-  %6 = load i8* @uc, align 1
+  %6 = load i8, i8* @uc, align 1
   %7 = zext i8 %6 to i16
-  %8 = load i8* @sc, align 1
+  %8 = load i8, i8* @sc, align 1
   %9 = sext i8 %8 to i16
   %10 = bitcast i8* bitcast (i16* @ss to i8*) to i16*
   %11 = cmpxchg i16* %10, i16 %7, i16 %9 monotonic monotonic
   store i16 %11, i16* @ss, align 2
-  %12 = load i8* @uc, align 1
+  %12 = load i8, i8* @uc, align 1
   %13 = zext i8 %12 to i16
-  %14 = load i8* @sc, align 1
+  %14 = load i8, i8* @sc, align 1
   %15 = sext i8 %14 to i16
   %16 = bitcast i8* bitcast (i16* @us to i8*) to i16*
   %17 = cmpxchg i16* %16, i16 %13, i16 %15 monotonic monotonic
   store i16 %17, i16* @us, align 2
-  %18 = load i8* @uc, align 1
+  %18 = load i8, i8* @uc, align 1
   %19 = zext i8 %18 to i32
-  %20 = load i8* @sc, align 1
+  %20 = load i8, i8* @sc, align 1
   %21 = sext i8 %20 to i32
   %22 = bitcast i8* bitcast (i32* @si to i8*) to i32*
   %23 = cmpxchg i32* %22, i32 %19, i32 %21 monotonic monotonic
   store i32 %23, i32* @si, align 4
-  %24 = load i8* @uc, align 1
+  %24 = load i8, i8* @uc, align 1
   %25 = zext i8 %24 to i32
-  %26 = load i8* @sc, align 1
+  %26 = load i8, i8* @sc, align 1
   %27 = sext i8 %26 to i32
   %28 = bitcast i8* bitcast (i32* @ui to i8*) to i32*
   %29 = cmpxchg i32* %28, i32 %25, i32 %27 monotonic monotonic
   store i32 %29, i32* @ui, align 4
-  %30 = load i8* @uc, align 1
+  %30 = load i8, i8* @uc, align 1
   %31 = zext i8 %30 to i64
-  %32 = load i8* @sc, align 1
+  %32 = load i8, i8* @sc, align 1
   %33 = sext i8 %32 to i64
   %34 = bitcast i8* bitcast (i64* @sl to i8*) to i64*
   %35 = cmpxchg i64* %34, i64 %31, i64 %33 monotonic monotonic
   store i64 %35, i64* @sl, align 8
-  %36 = load i8* @uc, align 1
+  %36 = load i8, i8* @uc, align 1
   %37 = zext i8 %36 to i64
-  %38 = load i8* @sc, align 1
+  %38 = load i8, i8* @sc, align 1
   %39 = sext i8 %38 to i64
   %40 = bitcast i8* bitcast (i64* @ul to i8*) to i64*
   %41 = cmpxchg i64* %40, i64 %37, i64 %39 monotonic monotonic
   store i64 %41, i64* @ul, align 8
-  %42 = load i8* @uc, align 1
-  %43 = load i8* @sc, align 1
+  %42 = load i8, i8* @uc, align 1
+  %43 = load i8, i8* @sc, align 1
   %44 = cmpxchg i8* @sc, i8 %42, i8 %43 monotonic monotonic
   %45 = icmp eq i8 %44, %42
   %46 = zext i1 %45 to i8
   %47 = zext i8 %46 to i32
   store i32 %47, i32* @ui, align 4
-  %48 = load i8* @uc, align 1
-  %49 = load i8* @sc, align 1
+  %48 = load i8, i8* @uc, align 1
+  %49 = load i8, i8* @sc, align 1
   %50 = cmpxchg i8* @uc, i8 %48, i8 %49 monotonic monotonic
   %51 = icmp eq i8 %50, %48
   %52 = zext i1 %51 to i8
   %53 = zext i8 %52 to i32
   store i32 %53, i32* @ui, align 4
-  %54 = load i8* @uc, align 1
+  %54 = load i8, i8* @uc, align 1
   %55 = zext i8 %54 to i16
-  %56 = load i8* @sc, align 1
+  %56 = load i8, i8* @sc, align 1
   %57 = sext i8 %56 to i16
   %58 = bitcast i8* bitcast (i16* @ss to i8*) to i16*
   %59 = cmpxchg i16* %58, i16 %55, i16 %57 monotonic monotonic
@@ -608,9 +608,9 @@ entry:
   %61 = zext i1 %60 to i8
   %62 = zext i8 %61 to i32
   store i32 %62, i32* @ui, align 4
-  %63 = load i8* @uc, align 1
+  %63 = load i8, i8* @uc, align 1
   %64 = zext i8 %63 to i16
-  %65 = load i8* @sc, align 1
+  %65 = load i8, i8* @sc, align 1
   %66 = sext i8 %65 to i16
   %67 = bitcast i8* bitcast (i16* @us to i8*) to i16*
   %68 = cmpxchg i16* %67, i16 %64, i16 %66 monotonic monotonic
@@ -618,9 +618,9 @@ entry:
   %70 = zext i1 %69 to i8
   %71 = zext i8 %70 to i32
   store i32 %71, i32* @ui, align 4
-  %72 = load i8* @uc, align 1
+  %72 = load i8, i8* @uc, align 1
   %73 = zext i8 %72 to i32
-  %74 = load i8* @sc, align 1
+  %74 = load i8, i8* @sc, align 1
   %75 = sext i8 %74 to i32
   %76 = bitcast i8* bitcast (i32* @si to i8*) to i32*
   %77 = cmpxchg i32* %76, i32 %73, i32 %75 monotonic monotonic
@@ -628,9 +628,9 @@ entry:
   %79 = zext i1 %78 to i8
   %80 = zext i8 %79 to i32
   store i32 %80, i32* @ui, align 4
-  %81 = load i8* @uc, align 1
+  %81 = load i8, i8* @uc, align 1
   %82 = zext i8 %81 to i32
-  %83 = load i8* @sc, align 1
+  %83 = load i8, i8* @sc, align 1
   %84 = sext i8 %83 to i32
   %85 = bitcast i8* bitcast (i32* @ui to i8*) to i32*
   %86 = cmpxchg i32* %85, i32 %82, i32 %84 monotonic monotonic
@@ -638,9 +638,9 @@ entry:
   %88 = zext i1 %87 to i8
   %89 = zext i8 %88 to i32
   store i32 %89, i32* @ui, align 4
-  %90 = load i8* @uc, align 1
+  %90 = load i8, i8* @uc, align 1
   %91 = zext i8 %90 to i64
-  %92 = load i8* @sc, align 1
+  %92 = load i8, i8* @sc, align 1
   %93 = sext i8 %92 to i64
   %94 = bitcast i8* bitcast (i64* @sl to i8*) to i64*
   %95 = cmpxchg i64* %94, i64 %91, i64 %93 monotonic monotonic
@@ -648,9 +648,9 @@ entry:
   %97 = zext i1 %96 to i8
   %98 = zext i8 %97 to i32
   store i32 %98, i32* @ui, align 4
-  %99 = load i8* @uc, align 1
+  %99 = load i8, i8* @uc, align 1
   %100 = zext i8 %99 to i64
-  %101 = load i8* @sc, align 1
+  %101 = load i8, i8* @sc, align 1
   %102 = sext i8 %101 to i64
   %103 = bitcast i8* bitcast (i64* @ul to i8*) to i64*
   %104 = cmpxchg i64* %103, i64 %100, i64 %102 monotonic monotonic
diff --git a/test/CodeGen/PowerPC/MergeConsecutiveStores.ll b/test/CodeGen/PowerPC/MergeConsecutiveStores.ll
new file mode 100644
index 000000000000..977b3b701cce
--- /dev/null
+++ b/test/CodeGen/PowerPC/MergeConsecutiveStores.ll
@@ -0,0 +1,68 @@
+; RUN: llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec < %s | FileCheck %s
+
+;; This test ensures that MergeConsecutiveStores does not attempt to
+;; merge stores or loads when doing so would result in unaligned
+;; memory operations (unless the target supports those, e.g. X86).
+
+;; This issue happen in other situations for other targets, but PPC
+;; with Altivec extensions was chosen for the test because it does not
+;; support unaligned access with AltiVec instructions. If the 4
+;; load/stores get merged to an v4i32 vector type severely bad code
+;; gets generated: it painstakingly copies the values to a temporary
+;; location on the stack, with vector ops, in order to then use
+;; integer ops to load from the temporary stack location and store to
+;; the final location. Yuck!
+
+%struct.X = type { i32, i32, i32, i32 }
+
+@fx = common global %struct.X zeroinitializer, align 4
+@fy = common global %struct.X zeroinitializer, align 4
+
+;; In this test case, lvx and stvx instructions should NOT be
+;; generated, as the alignment is not sufficient for it to be
+;; worthwhile.
+
+;; CHECK-LABEL: f:
+;; CHECK:      lwzu
+;; CHECK-NEXT: lwz
+;; CHECK-NEXT: lwz
+;; CHECK-NEXT: lwz
+;; CHECK-NEXT: stwu
+;; CHECK-NEXT: stw
+;; CHECK-NEXT: stw
+;; CHECK-NEXT: stw
+;; CHECK-NEXT: blr
+define void @f() {
+entry:
+  %0 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 0), align 4
+  %1 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 1), align 4
+  %2 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 2), align 4
+  %3 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 3), align 4
+  store i32 %0, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 0), align 4
+  store i32 %1, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 1), align 4
+  store i32 %2, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 2), align 4
+  store i32 %3, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 3), align 4
+  ret void
+}
+
+@gx = common global %struct.X zeroinitializer, align 16
+@gy = common global %struct.X zeroinitializer, align 16
+
+;; In this test, lvx and stvx instructions SHOULD be generated, as
+;; the 16-byte alignment of the new load/store is acceptable.
+;; CHECK-LABEL: g:
+;; CHECK: lvx
+;; CHECK: stvx
+;; CHECK: blr
+define void @g() {
+entry:
+  %0 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 0), align 16
+  %1 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 1), align 4
+  %2 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 2), align 4
+  %3 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 3), align 4
+  store i32 %0, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 0), align 16
+  store i32 %1, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 1), align 4
+  store i32 %2, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 2), align 4
+  store i32 %3, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 3), align 4
+  ret void
+}
diff --git a/test/CodeGen/PowerPC/a2-fp-basic.ll b/test/CodeGen/PowerPC/a2-fp-basic.ll
index de3aa7c31766..0324e38e1691 100644
--- a/test/CodeGen/PowerPC/a2-fp-basic.ll
+++ b/test/CodeGen/PowerPC/a2-fp-basic.ll
@@ -4,28 +4,28 @@
 
 define void @maybe_an_fma(%0* sret %agg.result, %0* byval %a, %0* byval %b, %0* byval %c) nounwind {
 entry:
-  %a.realp = getelementptr inbounds %0* %a, i32 0, i32 0
-  %a.real = load double* %a.realp
-  %a.imagp = getelementptr inbounds %0* %a, i32 0, i32 1
-  %a.imag = load double* %a.imagp
-  %b.realp = getelementptr inbounds %0* %b, i32 0, i32 0
-  %b.real = load double* %b.realp
-  %b.imagp = getelementptr inbounds %0* %b, i32 0, i32 1
-  %b.imag = load double* %b.imagp
+  %a.realp = getelementptr inbounds %0, %0* %a, i32 0, i32 0
+  %a.real = load double, double* %a.realp
+  %a.imagp = getelementptr inbounds %0, %0* %a, i32 0, i32 1
+  %a.imag = load double, double* %a.imagp
+  %b.realp = getelementptr inbounds %0, %0* %b, i32 0, i32 0
+  %b.real = load double, double* %b.realp
+  %b.imagp = getelementptr inbounds %0, %0* %b, i32 0, i32 1
+  %b.imag = load double, double* %b.imagp
   %mul.rl = fmul double %a.real, %b.real
   %mul.rr = fmul double %a.imag, %b.imag
   %mul.r = fsub double %mul.rl, %mul.rr
   %mul.il = fmul double %a.imag, %b.real
   %mul.ir = fmul double %a.real, %b.imag
   %mul.i = fadd double %mul.il, %mul.ir
-  %c.realp = getelementptr inbounds %0* %c, i32 0, i32 0
-  %c.real = load double* %c.realp
-  %c.imagp = getelementptr inbounds %0* %c, i32 0, i32 1
-  %c.imag = load double* %c.imagp
+  %c.realp = getelementptr inbounds %0, %0* %c, i32 0, i32 0
+  %c.real = load double, double* %c.realp
+  %c.imagp = getelementptr inbounds %0, %0* %c, i32 0, i32 1
+  %c.imag = load double, double* %c.imagp
   %add.r = fadd double %mul.r, %c.real
   %add.i = fadd double %mul.i, %c.imag
-  %real = getelementptr inbounds %0* %agg.result, i32 0, i32 0
-  %imag = getelementptr inbounds %0* %agg.result, i32 0, i32 1
+  %real = getelementptr inbounds %0, %0* %agg.result, i32 0, i32 0
+  %imag = getelementptr inbounds %0, %0* %agg.result, i32 0, i32 1
   store double %add.r, double* %real
   store double %add.i, double* %imag
   ret void
diff --git a/test/CodeGen/PowerPC/add-fi.ll b/test/CodeGen/PowerPC/add-fi.ll
index 18892c8cdf5e..010602e516a4 100644
--- a/test/CodeGen/PowerPC/add-fi.ll
+++ b/test/CodeGen/PowerPC/add-fi.ll
@@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define i32* @test1() {
         %X = alloca { i32, i32 }
-        %Y = getelementptr {i32,i32}* %X, i32 0, i32 1
+        %Y = getelementptr {i32,i32}, {i32,i32}* %X, i32 0, i32 1
         ret i32* %Y
 
 ; CHECK-LABEL: @test1
@@ -14,7 +14,7 @@ define i32* @test1() {
 
 define i32* @test2() {
         %X = alloca { i32, i32, i32, i32 }
-        %Y = getelementptr {i32,i32,i32,i32}* %X, i32 0, i32 3
+        %Y = getelementptr {i32,i32,i32,i32}, {i32,i32,i32,i32}* %X, i32 0, i32 3
         ret i32* %Y
 
 ; CHECK-LABEL: @test2
diff --git a/test/CodeGen/PowerPC/addi-licm.ll b/test/CodeGen/PowerPC/addi-licm.ll
index b52cb678a969..b6cfeec0e6f7 100644
--- a/test/CodeGen/PowerPC/addi-licm.ll
+++ b/test/CodeGen/PowerPC/addi-licm.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -disable-ppc-preinc-prep < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PIP
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -21,14 +22,22 @@ entry:
 ; CHECK-DAG: lfsx {{[0-9]+}}, [[REG2]],
 ; CHECK: blr
 
+; PIP-LABEL: @foo
+; PIP: addi [[REG1:[0-9]+]], 1,
+; PIP: addi [[REG2:[0-9]+]], 1,
+; PIP: %for.body.i
+; PIP-DAG: lfsu {{[0-9]+}}, 4([[REG1]])
+; PIP-DAG: lfsu {{[0-9]+}}, 4([[REG2]])
+; PIP: blr
+
 for.body.i:                                       ; preds = %for.body.i.preheader, %for.body.i
   %accumulator.09.i = phi double [ %add.i, %for.body.i ], [ 0.000000e+00, %entry ]
   %i.08.i = phi i64 [ %inc.i, %for.body.i ], [ 0, %entry ]
-  %arrayidx.i = getelementptr inbounds [2048 x float]* %x, i64 0, i64 %i.08.i
-  %v14 = load float* %arrayidx.i, align 4
+  %arrayidx.i = getelementptr inbounds [2048 x float], [2048 x float]* %x, i64 0, i64 %i.08.i
+  %v14 = load float, float* %arrayidx.i, align 4
   %conv.i = fpext float %v14 to double
-  %arrayidx1.i = getelementptr inbounds [2048 x float]* %y, i64 0, i64 %i.08.i
-  %v15 = load float* %arrayidx1.i, align 4
+  %arrayidx1.i = getelementptr inbounds [2048 x float], [2048 x float]* %y, i64 0, i64 %i.08.i
+  %v15 = load float, float* %arrayidx1.i, align 4
   %conv2.i = fpext float %v15 to double
   %mul.i = fmul double %conv.i, %conv2.i
   %add.i = fadd double %accumulator.09.i, %mul.i
diff --git a/test/CodeGen/PowerPC/addi-reassoc.ll b/test/CodeGen/PowerPC/addi-reassoc.ll
index 2b71ce65f6bc..3624ce638c7d 100644
--- a/test/CodeGen/PowerPC/addi-reassoc.ll
+++ b/test/CodeGen/PowerPC/addi-reassoc.ll
@@ -4,15 +4,15 @@
 
 define i32 @test1([4 x i32]* %P, i32 %i) {
         %tmp.2 = add i32 %i, 2          ; <i32> [#uses=1]
-        %tmp.4 = getelementptr [4 x i32]* %P, i32 %tmp.2, i32 1         ; <i32*> [#uses=1]
-        %tmp.5 = load i32* %tmp.4               ; <i32> [#uses=1]
+        %tmp.4 = getelementptr [4 x i32], [4 x i32]* %P, i32 %tmp.2, i32 1         ; <i32*> [#uses=1]
+        %tmp.5 = load i32, i32* %tmp.4               ; <i32> [#uses=1]
         ret i32 %tmp.5
 }
 
 define i32 @test2(%struct.X* %P, i32 %i) {
         %tmp.2 = add i32 %i, 2          ; <i32> [#uses=1]
-        %tmp.5 = getelementptr %struct.X* %P, i32 %tmp.2, i32 0, i32 1          ; <i8*> [#uses=1]
-        %tmp.6 = load i8* %tmp.5                ; <i8> [#uses=1]
+        %tmp.5 = getelementptr %struct.X, %struct.X* %P, i32 %tmp.2, i32 0, i32 1          ; <i8*> [#uses=1]
+        %tmp.6 = load i8, i8* %tmp.5                ; <i8> [#uses=1]
         %tmp.7 = sext i8 %tmp.6 to i32          ; <i32> [#uses=1]
         ret i32 %tmp.7
 }
diff --git a/test/CodeGen/PowerPC/alias.ll b/test/CodeGen/PowerPC/alias.ll
index 86e41148a0d7..524abd5da3ef 100644
--- a/test/CodeGen/PowerPC/alias.ll
+++ b/test/CodeGen/PowerPC/alias.ll
@@ -10,8 +10,8 @@
 ; CHECK-LABEL: bar:
 define i32 @bar() {
 ; MEDIUM: addis 3, 2, fooa@toc@ha
-; LARGE: addis 3, 2, .LC1@toc@ha
-  %a = load i32* @fooa
+; LARGE: addis 3, 2, .L[[L0:.*]]@toc@ha
+  %a = load i32, i32* @fooa
   ret i32 %a
 }
 
@@ -19,13 +19,13 @@ define i32 @bar() {
 define i64 @bar2() {
 ; MEDIUM: addis 3, 2, foo2a@toc@ha
 ; MEDIUM: addi 3, 3, foo2a@toc@l
-; LARGE: addis 3, 2, .LC3@toc@ha
-  %a = load i64* @foo2a
+; LARGE: addis 3, 2, .L[[L1:.*]]@toc@ha
+  %a = load i64, i64* @foo2a
   ret i64 %a
 }
 
-; LARGE: .LC1:
+; LARGE: .L[[L0]]:
 ; LARGE-NEXT: .tc fooa[TC],fooa
 
-; LARGE: .LC3:
+; LARGE: .L[[L1]]:
 ; LARGE-NEXT: .tc foo2a[TC],foo2a
diff --git a/test/CodeGen/PowerPC/and-branch.ll b/test/CodeGen/PowerPC/and-branch.ll
index 0484f882ec72..1543205f1a58 100644
--- a/test/CodeGen/PowerPC/and-branch.ll
+++ b/test/CodeGen/PowerPC/and-branch.ll
@@ -7,7 +7,7 @@ entry:
         %tmp4 = and i1 %tmp3, %tmp              ; <i1> [#uses=1]
         br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
 cond_true:              ; preds = %entry
-        %tmp5 = tail call i32 (...)* @bar( )            ; <i32> [#uses=0]
+        %tmp5 = tail call i32 (...) @bar( )            ; <i32> [#uses=0]
         ret void
 UnifiedReturnBlock:             ; preds = %entry
         ret void
diff --git a/test/CodeGen/PowerPC/and-elim.ll b/test/CodeGen/PowerPC/and-elim.ll
index a1ec29b16f14..f1738b2c1517 100644
--- a/test/CodeGen/PowerPC/and-elim.ll
+++ b/test/CodeGen/PowerPC/and-elim.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=ppc32 | not grep rlwin
 
 define void @test(i8* %P) {
-	%W = load i8* %P
+	%W = load i8, i8* %P
 	%X = shl i8 %W, 1
 	%Y = add i8 %X, 2
 	%Z = and i8 %Y, 254        ; dead and
diff --git a/test/CodeGen/PowerPC/anon_aggr.ll b/test/CodeGen/PowerPC/anon_aggr.ll
index 6c4f140de127..9f9eed019c15 100644
--- a/test/CodeGen/PowerPC/anon_aggr.ll
+++ b/test/CodeGen/PowerPC/anon_aggr.ll
@@ -21,7 +21,7 @@ unequal:
 }
 
 ; CHECK-LABEL: func1:
-; CHECK: cmpld {{[0-9]+}}, 4, 5
+; CHECK: cmpld {{([0-9]+,)?}}4, 5
 ; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]]
 ; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]]
 ; CHECK: ld 3, -[[OFFSET1]](1)
@@ -31,7 +31,7 @@ unequal:
 ; DARWIN32: mr
 ; DARWIN32: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]]
 ; DARWIN32: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
-; DARWIN32: cmplw cr{{[0-9]+}}, r[[REGA]], r[[REGB]]
+; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGA]], r[[REGB]]
 ; DARWIN32: stw r[[REG1]], -[[OFFSET1:[0-9]+]]
 ; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
 ; DARWIN32: lwz r3, -[[OFFSET1]]
@@ -41,7 +41,7 @@ unequal:
 ; DARWIN64: mr
 ; DARWIN64: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]]
 ; DARWIN64: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
-; DARWIN64: cmpld cr{{[0-9]+}}, r[[REGA]], r[[REGB]]
+; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REGB]]
 ; DARWIN64: std r[[REG1]], -[[OFFSET1:[0-9]+]]
 ; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]
 ; DARWIN64: ld r3, -[[OFFSET1]]
@@ -51,8 +51,8 @@ unequal:
 define i8* @func2({ i64, i8* } %array1, %tarray* byval %array2) {
 entry:
   %array1_ptr = extractvalue {i64, i8* } %array1, 1
-  %tmp = getelementptr inbounds %tarray* %array2, i32 0, i32 1
-  %array2_ptr = load i8** %tmp
+  %tmp = getelementptr inbounds %tarray, %tarray* %array2, i32 0, i32 1
+  %array2_ptr = load i8*, i8** %tmp
   %cond = icmp eq i8* %array1_ptr, %array2_ptr
   br i1 %cond, label %equal, label %unequal
 equal:
@@ -63,7 +63,7 @@ unequal:
 
 ; CHECK-LABEL: func2:
 ; CHECK: ld [[REG2:[0-9]+]], 72(1)
-; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]]
+; CHECK: cmpld {{([0-9]+,)?}}4, [[REG2]]
 ; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]]
 ; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]]
 ; CHECK: ld 3, -[[OFFSET2]](1)
@@ -74,7 +74,7 @@ unequal:
 ; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])
 ; DARWIN32: mr
 ; DARWIN32: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]]
-; DARWIN32: cmplw cr{{[0-9]+}}, r[[REGA]], r[[REG2]]
+; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]]
 ; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]
 ; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
 ; DARWIN32: lwz r3, -[[OFFSET1]]
@@ -84,7 +84,7 @@ unequal:
 ; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1)
 ; DARWIN64: mr
 ; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]]
-; DARWIN64: cmpld cr{{[0-9]+}}, r[[REGA]], r[[REG2]]
+; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]]
 ; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]]
 ; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]
 ; DARWIN64: ld r3, -[[OFFSET1]]
@@ -93,10 +93,10 @@ unequal:
 
 define i8* @func3({ i64, i8* }* byval %array1, %tarray* byval %array2) {
 entry:
-  %tmp1 = getelementptr inbounds { i64, i8* }* %array1, i32 0, i32 1
-  %array1_ptr = load i8** %tmp1
-  %tmp2 = getelementptr inbounds %tarray* %array2, i32 0, i32 1
-  %array2_ptr = load i8** %tmp2
+  %tmp1 = getelementptr inbounds { i64, i8* }, { i64, i8* }* %array1, i32 0, i32 1
+  %array1_ptr = load i8*, i8** %tmp1
+  %tmp2 = getelementptr inbounds %tarray, %tarray* %array2, i32 0, i32 1
+  %array2_ptr = load i8*, i8** %tmp2
   %cond = icmp eq i8* %array1_ptr, %array2_ptr
   br i1 %cond, label %equal, label %unequal
 equal:
@@ -108,7 +108,7 @@ unequal:
 ; CHECK-LABEL: func3:
 ; CHECK: ld [[REG3:[0-9]+]], 72(1)
 ; CHECK: ld [[REG4:[0-9]+]], 56(1)
-; CHECK: cmpld {{[0-9]+}}, [[REG4]], [[REG3]]
+; CHECK: cmpld {{([0-9]+,)?}}[[REG4]], [[REG3]]
 ; CHECK: std [[REG3]], -[[OFFSET1:[0-9]+]](1)
 ; CHECK: std [[REG4]], -[[OFFSET2:[0-9]+]](1)
 ; CHECK: ld 3, -[[OFFSET2]](1)
@@ -119,7 +119,7 @@ unequal:
 ; DARWIN32: addi r[[REG2:[0-9]+]], r[[REGSP]], 24
 ; DARWIN32: lwz r[[REG3:[0-9]+]], 44(r[[REGSP]])
 ; DARWIN32: lwz r[[REG4:[0-9]+]], 32(r[[REGSP]])
-; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
+; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]]
 ; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]
 ; DARWIN32: stw r[[REG4]], -[[OFFSET2:[0-9]+]]
 ; DARWIN32: lwz r3, -[[OFFSET2]]
@@ -128,7 +128,7 @@ unequal:
 ; DARWIN64: _func3:
 ; DARWIN64: ld r[[REG3:[0-9]+]], 72(r1)
 ; DARWIN64: ld r[[REG4:[0-9]+]], 56(r1)
-; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
+; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]]
 ; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]]
 ; DARWIN64: std r[[REG4]], -[[OFFSET2:[0-9]+]]
 ; DARWIN64: ld r3, -[[OFFSET2]]
@@ -140,8 +140,8 @@ define i8* @func4(i64 %p1, i64 %p2, i64 %p3, i64 %p4,
                   { i64, i8* } %array1, %tarray* byval %array2) {
 entry:
   %array1_ptr = extractvalue {i64, i8* } %array1, 1
-  %tmp = getelementptr inbounds %tarray* %array2, i32 0, i32 1
-  %array2_ptr = load i8** %tmp
+  %tmp = getelementptr inbounds %tarray, %tarray* %array2, i32 0, i32 1
+  %array2_ptr = load i8*, i8** %tmp
   %cond = icmp eq i8* %array1_ptr, %array2_ptr
   br i1 %cond, label %equal, label %unequal
 equal:
@@ -153,7 +153,7 @@ unequal:
 ; CHECK-LABEL: func4:
 ; CHECK: ld [[REG3:[0-9]+]], 136(1)
 ; CHECK: ld [[REG2:[0-9]+]], 120(1)
-; CHECK: cmpld {{[0-9]+}}, [[REG2]], [[REG3]]
+; CHECK: cmpld {{([0-9]+,)?}}[[REG2]], [[REG3]]
 ; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1)
 ; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]](1)
 ; CHECK: ld 3, -[[OFFSET1]](1)
@@ -164,8 +164,8 @@ unequal:
 ; DARWIN32: addi r[[REG1:[0-9]+]], r1, 100
 ; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1)
 ; DARWIN32: mr r[[REG2:[0-9]+]], r[[REG4]]
-; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
-; DARWIN32: stw r[[REG4]], -[[OFFSET1:[0-9]+]]
+; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]]
+; DARWIN32: stw r[[REG2]], -[[OFFSET1:[0-9]+]]
 ; DARWIN32: stw r[[REG3]], -[[OFFSET2:[0-9]+]]
 ; DARWIN32: lwz r[[REG1]], -[[OFFSET1]]
 ; DARWIN32: lwz r[[REG1]], -[[OFFSET2]]
@@ -174,7 +174,7 @@ unequal:
 ; DARWIN64: ld r[[REG2:[0-9]+]], 120(r1)
 ; DARWIN64: ld r[[REG3:[0-9]+]], 136(r1)
 ; DARWIN64: mr r[[REG4:[0-9]+]], r[[REG2]]
-; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG2]], r[[REG3]]
+; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REG2]], r[[REG3]]
 ; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]]
 ; DARWIN64: std r[[REG3]], -[[OFFSET2:[0-9]+]]
 ; DARWIN64: ld r3, -[[OFFSET1]]
diff --git a/test/CodeGen/PowerPC/asm-constraints.ll b/test/CodeGen/PowerPC/asm-constraints.ll
index 9bf8b75e0ace..2d9b0eb591d3 100644
--- a/test/CodeGen/PowerPC/asm-constraints.ll
+++ b/test/CodeGen/PowerPC/asm-constraints.ll
@@ -23,7 +23,7 @@ entry:
   %addr.addr = alloca i8*, align 8
   store i32 %result, i32* %result.addr, align 4
   store i8* %addr, i8** %addr.addr, align 8
-  %0 = load i8** %addr.addr, align 8
+  %0 = load i8*, i8** %addr.addr, align 8
   %1 = call i32 asm sideeffect "ld${1:U}${1:X} $0,$1\0Acmpw $0,$0\0Abne- 1f\0A1: isync\0A", "=r,*m,~{memory},~{cr0}"(i8* %0) #1, !srcloc !1
   store i32 %1, i32* %result.addr, align 4
   ret void
@@ -31,7 +31,7 @@ entry:
 
 ; CHECK-LABEL: @foo
 ; CHECK: ld [[REG:[0-9]+]], 0(4)
-; CHECK: cmpw 0, [[REG]], [[REG]]
+; CHECK: cmpw [[REG]], [[REG]]
 ; CHECK: bne- 0, .Ltmp[[TMP:[0-9]+]]
 ; CHECK: .Ltmp[[TMP]]:
 ; CHECK: isync
diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll
index 9cb0fa5be5c9..1857d5d697e6 100644
--- a/test/CodeGen/PowerPC/atomic-2.ll
+++ b/test/CodeGen/PowerPC/atomic-2.ll
@@ -1,4 +1,6 @@
 ; RUN: llc < %s -march=ppc64 | FileCheck %s
+; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s
+; RUN: llc < %s -march=ppc64 -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-P8U
 
 define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
 ; CHECK-LABEL: exchange_and_add:
@@ -8,6 +10,22 @@ define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
   ret i64 %tmp
 }
 
+define i8 @exchange_and_add8(i8* %mem, i8 %val) nounwind {
+; CHECK-LABEL: exchange_and_add8:
+; CHECK-P8U: lbarx
+  %tmp = atomicrmw add i8* %mem, i8 %val monotonic
+; CHECK-P8U: stbcx.
+  ret i8 %tmp
+}
+
+define i16 @exchange_and_add16(i16* %mem, i16 %val) nounwind {
+; CHECK-LABEL: exchange_and_add16:
+; CHECK-P8U: lharx
+  %tmp = atomicrmw add i16* %mem, i16 %val monotonic
+; CHECK-P8U: sthcx.
+  ret i16 %tmp
+}
+
 define i64 @exchange_and_cmp(i64* %mem) nounwind {
 ; CHECK-LABEL: exchange_and_cmp:
 ; CHECK: ldarx
@@ -18,6 +36,26 @@ define i64 @exchange_and_cmp(i64* %mem) nounwind {
   ret i64 %tmp
 }
 
+define i8 @exchange_and_cmp8(i8* %mem) nounwind {
+; CHECK-LABEL: exchange_and_cmp8:
+; CHECK-P8U: lbarx
+  %tmppair = cmpxchg i8* %mem, i8 0, i8 1 monotonic monotonic
+  %tmp = extractvalue { i8, i1 } %tmppair, 0
+; CHECK-P8U: stbcx.
+; CHECK-P8U: stbcx.
+  ret i8 %tmp
+}
+
+define i16 @exchange_and_cmp16(i16* %mem) nounwind {
+; CHECK-LABEL: exchange_and_cmp16:
+; CHECK-P8U: lharx
+  %tmppair = cmpxchg i16* %mem, i16 0, i16 1 monotonic monotonic
+  %tmp = extractvalue { i16, i1 } %tmppair, 0
+; CHECK-P8U: sthcx.
+; CHECK-P8U: sthcx.
+  ret i16 %tmp
+}
+
 define i64 @exchange(i64* %mem, i64 %val) nounwind {
 ; CHECK-LABEL: exchange:
 ; CHECK: ldarx
@@ -26,11 +64,27 @@ define i64 @exchange(i64* %mem, i64 %val) nounwind {
   ret i64 %tmp
 }
 
+define i8 @exchange8(i8* %mem, i8 %val) nounwind {
+; CHECK-LABEL: exchange8:
+; CHECK-P8U: lbarx
+  %tmp = atomicrmw xchg i8* %mem, i8 1 monotonic
+; CHECK-P8U: stbcx.
+  ret i8 %tmp
+}
+
+define i16 @exchange16(i16* %mem, i16 %val) nounwind {
+; CHECK-LABEL: exchange16:
+; CHECK-P8U: lharx
+  %tmp = atomicrmw xchg i16* %mem, i16 1 monotonic
+; CHECK-P8U: sthcx.
+  ret i16 %tmp
+}
+
 define void @atomic_store(i64* %mem, i64 %val) nounwind {
 entry:
 ; CHECK: @atomic_store
   store atomic i64 %val, i64* %mem release, align 64
-; CHECK: sync 1
+; CHECK: lwsync
 ; CHECK-NOT: stdcx
 ; CHECK: std
   ret void
@@ -39,10 +93,10 @@ entry:
 define i64 @atomic_load(i64* %mem) nounwind {
 entry:
 ; CHECK: @atomic_load
-  %tmp = load atomic i64* %mem acquire, align 64
+  %tmp = load atomic i64, i64* %mem acquire, align 64
 ; CHECK-NOT: ldarx
 ; CHECK: ld
-; CHECK: sync 1
+; CHECK: lwsync
   ret i64 %tmp
 }
 
diff --git a/test/CodeGen/PowerPC/atomics-fences.ll b/test/CodeGen/PowerPC/atomics-fences.ll
index 862bd173fdaf..c015fa6eefb0 100644
--- a/test/CodeGen/PowerPC/atomics-fences.ll
+++ b/test/CodeGen/PowerPC/atomics-fences.ll
@@ -5,24 +5,23 @@
 ; Fences
 define void @fence_acquire() {
 ; CHECK-LABEL: fence_acquire
-; CHECK: sync 1
-; PPC440-NOT: sync 1
+; CHECK: lwsync
+; PPC440-NOT: lwsync
 ; PPC440: msync
   fence acquire
   ret void
 }
 define void @fence_release() {
 ; CHECK-LABEL: fence_release
-; CHECK: sync 1
-; PPC440-NOT: sync 1
+; CHECK: lwsync
+; PPC440-NOT: lwsync
 ; PPC440: msync
   fence release
   ret void
 }
 define void @fence_seq_cst() {
 ; CHECK-LABEL: fence_seq_cst
-; CHECK: sync 0
-; PPC440-NOT: sync 0
+; CHECK: sync
 ; PPC440: msync
   fence seq_cst
   ret void
diff --git a/test/CodeGen/PowerPC/atomics-indexed.ll b/test/CodeGen/PowerPC/atomics-indexed.ll
index bb9ca0401966..7a0dde034d68 100644
--- a/test/CodeGen/PowerPC/atomics-indexed.ll
+++ b/test/CodeGen/PowerPC/atomics-indexed.ll
@@ -9,27 +9,27 @@
 ; Indexed version of loads
 define i8 @load_x_i8_seq_cst([100000 x i8]* %mem) {
 ; CHECK-LABEL: load_x_i8_seq_cst
-; CHECK: sync 0
+; CHECK: sync
 ; CHECK: lbzx
-; CHECK: sync 1
-  %ptr = getelementptr inbounds [100000 x i8]* %mem, i64 0, i64 90000
-  %val = load atomic i8* %ptr seq_cst, align 1
+; CHECK: lwsync
+  %ptr = getelementptr inbounds [100000 x i8], [100000 x i8]* %mem, i64 0, i64 90000
+  %val = load atomic i8, i8* %ptr seq_cst, align 1
   ret i8 %val
 }
 define i16 @load_x_i16_acquire([100000 x i16]* %mem) {
 ; CHECK-LABEL: load_x_i16_acquire
 ; CHECK: lhzx
-; CHECK: sync 1
-  %ptr = getelementptr inbounds [100000 x i16]* %mem, i64 0, i64 90000
-  %val = load atomic i16* %ptr acquire, align 2
+; CHECK: lwsync
+  %ptr = getelementptr inbounds [100000 x i16], [100000 x i16]* %mem, i64 0, i64 90000
+  %val = load atomic i16, i16* %ptr acquire, align 2
   ret i16 %val
 }
 define i32 @load_x_i32_monotonic([100000 x i32]* %mem) {
 ; CHECK-LABEL: load_x_i32_monotonic
 ; CHECK: lwzx
 ; CHECK-NOT: sync
-  %ptr = getelementptr inbounds [100000 x i32]* %mem, i64 0, i64 90000
-  %val = load atomic i32* %ptr monotonic, align 4
+  %ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %mem, i64 0, i64 90000
+  %val = load atomic i32, i32* %ptr monotonic, align 4
   ret i32 %val
 }
 define i64 @load_x_i64_unordered([100000 x i64]* %mem) {
@@ -38,25 +38,25 @@ define i64 @load_x_i64_unordered([100000 x i64]* %mem) {
 ; PPC64-NOT: __sync_
 ; PPC64: ldx
 ; CHECK-NOT: sync
-  %ptr = getelementptr inbounds [100000 x i64]* %mem, i64 0, i64 90000
-  %val = load atomic i64* %ptr unordered, align 8
+  %ptr = getelementptr inbounds [100000 x i64], [100000 x i64]* %mem, i64 0, i64 90000
+  %val = load atomic i64, i64* %ptr unordered, align 8
   ret i64 %val
 }
 
 ; Indexed version of stores
 define void @store_x_i8_seq_cst([100000 x i8]* %mem) {
 ; CHECK-LABEL: store_x_i8_seq_cst
-; CHECK: sync 0
+; CHECK: sync
 ; CHECK: stbx
-  %ptr = getelementptr inbounds [100000 x i8]* %mem, i64 0, i64 90000
+  %ptr = getelementptr inbounds [100000 x i8], [100000 x i8]* %mem, i64 0, i64 90000
   store atomic i8 42, i8* %ptr seq_cst, align 1
   ret void
 }
 define void @store_x_i16_release([100000 x i16]* %mem) {
 ; CHECK-LABEL: store_x_i16_release
-; CHECK: sync 1
+; CHECK: lwsync
 ; CHECK: sthx
-  %ptr = getelementptr inbounds [100000 x i16]* %mem, i64 0, i64 90000
+  %ptr = getelementptr inbounds [100000 x i16], [100000 x i16]* %mem, i64 0, i64 90000
   store atomic i16 42, i16* %ptr release, align 2
   ret void
 }
@@ -64,18 +64,17 @@ define void @store_x_i32_monotonic([100000 x i32]* %mem) {
 ; CHECK-LABEL: store_x_i32_monotonic
 ; CHECK-NOT: sync
 ; CHECK: stwx
-  %ptr = getelementptr inbounds [100000 x i32]* %mem, i64 0, i64 90000
+  %ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %mem, i64 0, i64 90000
   store atomic i32 42, i32* %ptr monotonic, align 4
   ret void
 }
 define void @store_x_i64_unordered([100000 x i64]* %mem) {
 ; CHECK-LABEL: store_x_i64_unordered
-; CHECK-NOT: sync 0
-; CHECK-NOT: sync 1
+; CHECK-NOT: sync
 ; PPC32: __sync_
 ; PPC64-NOT: __sync_
 ; PPC64: stdx
-  %ptr = getelementptr inbounds [100000 x i64]* %mem, i64 0, i64 90000
+  %ptr = getelementptr inbounds [100000 x i64], [100000 x i64]* %mem, i64 0, i64 90000
   store atomic i64 42, i64* %ptr unordered, align 8
   ret void
 }
diff --git a/test/CodeGen/PowerPC/atomics.ll b/test/CodeGen/PowerPC/atomics.ll
index 5f6a6a4dcdf1..2e1eff0f634d 100644
--- a/test/CodeGen/PowerPC/atomics.ll
+++ b/test/CodeGen/PowerPC/atomics.ll
@@ -13,31 +13,31 @@ define i8 @load_i8_unordered(i8* %mem) {
 ; CHECK-LABEL: load_i8_unordered
 ; CHECK: lbz
 ; CHECK-NOT: sync
-  %val = load atomic i8* %mem unordered, align 1
+  %val = load atomic i8, i8* %mem unordered, align 1
   ret i8 %val
 }
 define i16 @load_i16_monotonic(i16* %mem) {
 ; CHECK-LABEL: load_i16_monotonic
 ; CHECK: lhz
 ; CHECK-NOT: sync
-  %val = load atomic i16* %mem monotonic, align 2
+  %val = load atomic i16, i16* %mem monotonic, align 2
   ret i16 %val
 }
 define i32 @load_i32_acquire(i32* %mem) {
 ; CHECK-LABEL: load_i32_acquire
 ; CHECK: lwz
-  %val = load atomic i32* %mem acquire, align 4
-; CHECK: sync 1
+  %val = load atomic i32, i32* %mem acquire, align 4
+; CHECK: lwsync
   ret i32 %val
 }
 define i64 @load_i64_seq_cst(i64* %mem) {
 ; CHECK-LABEL: load_i64_seq_cst
-; CHECK: sync 0
+; CHECK: sync
 ; PPC32: __sync_
 ; PPC64-NOT: __sync_
 ; PPC64: ld
-  %val = load atomic i64* %mem seq_cst, align 8
-; CHECK: sync 1
+  %val = load atomic i64, i64* %mem seq_cst, align 8
+; CHECK: lwsync
   ret i64 %val
 }
 
@@ -58,14 +58,14 @@ define void @store_i16_monotonic(i16* %mem) {
 }
 define void @store_i32_release(i32* %mem) {
 ; CHECK-LABEL: store_i32_release
-; CHECK: sync 1
+; CHECK: lwsync
 ; CHECK: stw
   store atomic i32 42, i32* %mem release, align 4
   ret void
 }
 define void @store_i64_seq_cst(i64* %mem) {
 ; CHECK-LABEL: store_i64_seq_cst
-; CHECK: sync 0
+; CHECK: sync
 ; PPC32: __sync_
 ; PPC64-NOT: __sync_
 ; PPC64: std
@@ -76,9 +76,9 @@ define void @store_i64_seq_cst(i64* %mem) {
 ; Atomic CmpXchg
 define i8 @cas_strong_i8_sc_sc(i8* %mem) {
 ; CHECK-LABEL: cas_strong_i8_sc_sc
-; CHECK: sync 0
+; CHECK: sync
   %val = cmpxchg i8* %mem, i8 0, i8 1 seq_cst seq_cst
-; CHECK: sync 1
+; CHECK: lwsync
   %loaded = extractvalue { i8, i1} %val, 0
   ret i8 %loaded
 }
@@ -86,21 +86,21 @@ define i16 @cas_weak_i16_acquire_acquire(i16* %mem) {
 ; CHECK-LABEL: cas_weak_i16_acquire_acquire
 ;CHECK-NOT: sync
   %val = cmpxchg weak i16* %mem, i16 0, i16 1 acquire acquire
-; CHECK: sync 1
+; CHECK: lwsync
   %loaded = extractvalue { i16, i1} %val, 0
   ret i16 %loaded
 }
 define i32 @cas_strong_i32_acqrel_acquire(i32* %mem) {
 ; CHECK-LABEL: cas_strong_i32_acqrel_acquire
-; CHECK: sync 1
+; CHECK: lwsync
   %val = cmpxchg i32* %mem, i32 0, i32 1 acq_rel acquire
-; CHECK: sync 1
+; CHECK: lwsync
   %loaded = extractvalue { i32, i1} %val, 0
   ret i32 %loaded
 }
 define i64 @cas_weak_i64_release_monotonic(i64* %mem) {
 ; CHECK-LABEL: cas_weak_i64_release_monotonic
-; CHECK: sync 1
+; CHECK: lwsync
   %val = cmpxchg weak i64* %mem, i64 0, i64 1 release monotonic
 ; CHECK-NOT: [sync ]
   %loaded = extractvalue { i64, i1} %val, 0
@@ -116,21 +116,21 @@ define i8 @add_i8_monotonic(i8* %mem, i8 %operand) {
 }
 define i16 @xor_i16_seq_cst(i16* %mem, i16 %operand) {
 ; CHECK-LABEL: xor_i16_seq_cst
-; CHECK: sync 0
+; CHECK: sync
   %val = atomicrmw xor i16* %mem, i16 %operand seq_cst
-; CHECK: sync 1
+; CHECK: lwsync
   ret i16 %val
 }
 define i32 @xchg_i32_acq_rel(i32* %mem, i32 %operand) {
 ; CHECK-LABEL: xchg_i32_acq_rel
-; CHECK: sync 1
+; CHECK: lwsync
   %val = atomicrmw xchg i32* %mem, i32 %operand acq_rel
-; CHECK: sync 1
+; CHECK: lwsync
   ret i32 %val
 }
 define i64 @and_i64_release(i64* %mem, i64 %operand) {
 ; CHECK-LABEL: and_i64_release
-; CHECK: sync 1
+; CHECK: lwsync
   %val = atomicrmw and i64* %mem, i64 %operand release
 ; CHECK-NOT: [sync ]
   ret i64 %val
diff --git a/test/CodeGen/PowerPC/bdzlr.ll b/test/CodeGen/PowerPC/bdzlr.ll
index 29b74c6c8c66..d6506044868f 100644
--- a/test/CodeGen/PowerPC/bdzlr.ll
+++ b/test/CodeGen/PowerPC/bdzlr.ll
@@ -35,8 +35,8 @@ for.body.lr.ph:                                   ; preds = %if.end
 for.body:                                         ; preds = %for.body.for.body_crit_edge, %for.body.lr.ph
   %0 = phi %struct.lua_TValue.17.692* [ undef, %for.body.lr.ph ], [ %.pre, %for.body.for.body_crit_edge ]
   %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body.for.body_crit_edge ]
-  %tt = getelementptr inbounds %struct.lua_TValue.17.692* %0, i64 %indvars.iv, i32 1
-  %1 = load i32* %tt, align 4
+  %tt = getelementptr inbounds %struct.lua_TValue.17.692, %struct.lua_TValue.17.692* %0, i64 %indvars.iv, i32 1
+  %1 = load i32, i32* %tt, align 4
   store i32 %1, i32* undef, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -44,7 +44,7 @@ for.body:                                         ; preds = %for.body.for.body_c
   br i1 %exitcond, label %for.end, label %for.body.for.body_crit_edge
 
 for.body.for.body_crit_edge:                      ; preds = %for.body
-  %.pre = load %struct.lua_TValue.17.692** undef, align 8
+  %.pre = load %struct.lua_TValue.17.692*, %struct.lua_TValue.17.692** undef, align 8
   br label %for.body
 
 for.end:                                          ; preds = %for.body, %if.end, %entry
diff --git a/test/CodeGen/PowerPC/bperm.ll b/test/CodeGen/PowerPC/bperm.ll
index c489c1f90a8f..c5a728859a05 100644
--- a/test/CodeGen/PowerPC/bperm.ll
+++ b/test/CodeGen/PowerPC/bperm.ll
@@ -22,15 +22,15 @@ entry:
   ret i64 %0
 
 ; CHECK-LABEL: @bs8
-; CHECK-DAG: rldicl [[REG1:[0-9]+]], 3, 16, 0
-; CHECK-DAG: rldicl [[REG2:[0-9]+]], 3, 8, 0
-; CHECK-DAG: rldicl [[REG3:[0-9]+]], 3, 24, 0
+; CHECK-DAG: rotldi [[REG1:[0-9]+]], 3, 16
+; CHECK-DAG: rotldi [[REG2:[0-9]+]], 3, 8
+; CHECK-DAG: rotldi [[REG3:[0-9]+]], 3, 24
 ; CHECK-DAG: rldimi [[REG2]], [[REG1]], 8, 48
-; CHECK-DAG: rldicl [[REG4:[0-9]+]], 3, 32, 0
+; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 32
 ; CHECK-DAG: rldimi [[REG2]], [[REG3]], 16, 40
-; CHECK-DAG: rldicl [[REG5:[0-9]+]], 3, 48, 0
+; CHECK-DAG: rotldi [[REG5:[0-9]+]], 3, 48
 ; CHECK-DAG: rldimi [[REG2]], [[REG4]], 24, 32
-; CHECK-DAG: rldicl [[REG6:[0-9]+]], 3, 56, 0
+; CHECK-DAG: rotldi [[REG6:[0-9]+]], 3, 56
 ; CHECK-DAG: rldimi [[REG2]], [[REG5]], 40, 16
 ; CHECK-DAG: rldimi [[REG2]], [[REG6]], 48, 8
 ; CHECK-DAG: rldimi [[REG2]], 3, 56, 0
@@ -46,7 +46,7 @@ entry:
 
 ; CHECK-LABEL: @test1
 ; CHECK-DAG: li [[REG1:[0-9]+]], 11375
-; CHECK-DAG: rldicl [[REG3:[0-9]+]], 4, 56, 0
+; CHECK-DAG: rotldi [[REG3:[0-9]+]], 4, 56
 ; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 19
 ; CHECK: and 3, [[REG3]], [[REG2]]
 ; CHECK: blr
@@ -60,7 +60,7 @@ entry:
 
 ; CHECK-LABEL: @test2
 ; CHECK-DAG: lis [[REG1:[0-9]+]], 474
-; CHECK-DAG: rldicl [[REG5:[0-9]+]], 4, 58, 0
+; CHECK-DAG: rotldi [[REG5:[0-9]+]], 4, 58
 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 3648
 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
 ; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464
@@ -76,7 +76,7 @@ entry:
 
 ; CHECK-LABEL: @test3
 ; CHECK-DAG: lis [[REG1:[0-9]+]], 170
-; CHECK-DAG: rldicl [[REG4:[0-9]+]], 3, 34, 0
+; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 34
 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 22861
 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 34
 ; CHECK: and 3, [[REG4]], [[REG3]]
@@ -90,7 +90,7 @@ entry:
   ret i64 %and
 
 ; CHECK-LABEL: @test4
-; CHECK: rldicl [[REG1:[0-9]+]], 4, 49, 0
+; CHECK: rotldi [[REG1:[0-9]+]], 4, 49
 ; CHECK: andis. 3, [[REG1]], 888
 ; CHECK: blr
 }
@@ -103,7 +103,7 @@ entry:
 
 ; CHECK-LABEL: @test5
 ; CHECK-DAG: lis [[REG1:[0-9]+]], 3703
-; CHECK-DAG: rldicl [[REG4:[0-9]+]], 4, 12, 0
+; CHECK-DAG: rotldi [[REG4:[0-9]+]], 4, 12
 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 35951
 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19
 ; CHECK: and 3, [[REG4]], [[REG3]]
@@ -148,7 +148,7 @@ entry:
 
 ; CHECK-LABEL: @test8
 ; CHECK-DAG: lis [[REG1:[0-9]+]], 4
-; CHECK-DAG: rldicl [[REG4:[0-9]+]], 3, 63, 0
+; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 63
 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 60527
 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19
 ; CHECK: and 3, [[REG4]], [[REG3]]
@@ -166,8 +166,8 @@ entry:
 
 ; CHECK-LABEL: @test9
 ; CHECK-DAG: lis [[REG1:[0-9]+]], 1440
-; CHECK-DAG: rldicl [[REG5:[0-9]+]], 4, 62, 0
-; CHECK-DAG: rldicl [[REG6:[0-9]+]], 4, 50, 0
+; CHECK-DAG: rotldi [[REG5:[0-9]+]], 4, 62
+; CHECK-DAG: rotldi [[REG6:[0-9]+]], 4, 50
 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 4
 ; CHECK-DAG: rldimi [[REG6]], [[REG5]], 53, 0
 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
@@ -187,8 +187,8 @@ entry:
 
 ; CHECK-LABEL: @test10
 ; CHECK-DAG: lis [[REG1:[0-9]+]], 1
-; CHECK-DAG: rldicl [[REG6:[0-9]+]], 3, 25, 0
-; CHECK-DAG: rldicl [[REG7:[0-9]+]], 3, 37, 0
+; CHECK-DAG: rotldi [[REG6:[0-9]+]], 3, 25
+; CHECK-DAG: rotldi [[REG7:[0-9]+]], 3, 37
 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 8183
 ; CHECK-DAG: ori [[REG3:[0-9]+]], [[REG1]], 50017
 ; CHECK-DAG: sldi [[REG4:[0-9]+]], [[REG2]], 25
diff --git a/test/CodeGen/PowerPC/branch-opt.ll b/test/CodeGen/PowerPC/branch-opt.ll
index dda1538f1cdf..d6928dde2a7d 100644
--- a/test/CodeGen/PowerPC/branch-opt.ll
+++ b/test/CodeGen/PowerPC/branch-opt.ll
@@ -11,7 +11,7 @@ entry:
 	br i1 %tmp1.upgrd.1, label %cond_false, label %bb5
 bb:		; preds = %bb5, %bb
 	%indvar77 = phi i32 [ %indvar.next78, %bb ], [ 0, %bb5 ]		; <i32> [#uses=1]
-	%tmp2 = tail call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp2 = tail call i32 (...) @bar( )		; <i32> [#uses=0]
 	%indvar.next78 = add i32 %indvar77, 1		; <i32> [#uses=2]
 	%exitcond79 = icmp eq i32 %indvar.next78, %X		; <i1> [#uses=1]
 	br i1 %exitcond79, label %cond_next48, label %bb
@@ -24,7 +24,7 @@ cond_false:		; preds = %entry
 	br i1 %tmp10.upgrd.2, label %cond_false20, label %bb16
 bb12:		; preds = %bb16, %bb12
 	%indvar72 = phi i32 [ %indvar.next73, %bb12 ], [ 0, %bb16 ]		; <i32> [#uses=1]
-	%tmp13 = tail call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp13 = tail call i32 (...) @bar( )		; <i32> [#uses=0]
 	%indvar.next73 = add i32 %indvar72, 1		; <i32> [#uses=2]
 	%exitcond74 = icmp eq i32 %indvar.next73, %Y		; <i1> [#uses=1]
 	br i1 %exitcond74, label %cond_next48, label %bb12
@@ -37,7 +37,7 @@ cond_false20:		; preds = %cond_false
 	br i1 %tmp23.upgrd.3, label %cond_false33, label %bb29
 bb25:		; preds = %bb29, %bb25
 	%indvar67 = phi i32 [ %indvar.next68, %bb25 ], [ 0, %bb29 ]		; <i32> [#uses=1]
-	%tmp26 = tail call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp26 = tail call i32 (...) @bar( )		; <i32> [#uses=0]
 	%indvar.next68 = add i32 %indvar67, 1		; <i32> [#uses=2]
 	%exitcond69 = icmp eq i32 %indvar.next68, %Z		; <i1> [#uses=1]
 	br i1 %exitcond69, label %cond_next48, label %bb25
@@ -49,7 +49,7 @@ cond_false33:		; preds = %cond_false20
 	%tmp36.upgrd.4 = icmp eq i32 %tmp36, 0		; <i1> [#uses=1]
 	br i1 %tmp36.upgrd.4, label %cond_next48, label %bb42
 bb38:		; preds = %bb42
-	%tmp39 = tail call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp39 = tail call i32 (...) @bar( )		; <i32> [#uses=0]
 	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=1]
 	br label %bb42
 bb42:		; preds = %bb38, %cond_false33
@@ -62,7 +62,7 @@ cond_next48:		; preds = %bb42, %cond_false33, %bb29, %bb25, %bb16, %bb12, %bb5,
 	%tmp50 = icmp eq i32 %W_addr.1, 0		; <i1> [#uses=1]
 	br i1 %tmp50, label %UnifiedReturnBlock, label %cond_true51
 cond_true51:		; preds = %cond_next48
-	%tmp52 = tail call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp52 = tail call i32 (...) @bar( )		; <i32> [#uses=0]
 	ret void
 UnifiedReturnBlock:		; preds = %cond_next48
 	ret void
diff --git a/test/CodeGen/PowerPC/bswap-load-store.ll b/test/CodeGen/PowerPC/bswap-load-store.ll
index 53bbc52167c4..cee1f0cdaa99 100644
--- a/test/CodeGen/PowerPC/bswap-load-store.ll
+++ b/test/CodeGen/PowerPC/bswap-load-store.ll
@@ -5,7 +5,7 @@
 
 
 define void @STWBRX(i32 %i, i8* %ptr, i32 %off) {
-        %tmp1 = getelementptr i8* %ptr, i32 %off                ; <i8*> [#uses=1]
+        %tmp1 = getelementptr i8, i8* %ptr, i32 %off                ; <i8*> [#uses=1]
         %tmp1.upgrd.1 = bitcast i8* %tmp1 to i32*               ; <i32*> [#uses=1]
         %tmp13 = tail call i32 @llvm.bswap.i32( i32 %i )                ; <i32> [#uses=1]
         store i32 %tmp13, i32* %tmp1.upgrd.1
@@ -13,15 +13,15 @@ define void @STWBRX(i32 %i, i8* %ptr, i32 %off) {
 }
 
 define i32 @LWBRX(i8* %ptr, i32 %off) {
-        %tmp1 = getelementptr i8* %ptr, i32 %off                ; <i8*> [#uses=1]
+        %tmp1 = getelementptr i8, i8* %ptr, i32 %off                ; <i8*> [#uses=1]
         %tmp1.upgrd.2 = bitcast i8* %tmp1 to i32*               ; <i32*> [#uses=1]
-        %tmp = load i32* %tmp1.upgrd.2          ; <i32> [#uses=1]
+        %tmp = load i32, i32* %tmp1.upgrd.2          ; <i32> [#uses=1]
         %tmp14 = tail call i32 @llvm.bswap.i32( i32 %tmp )              ; <i32> [#uses=1]
         ret i32 %tmp14
 }
 
 define void @STHBRX(i16 %s, i8* %ptr, i32 %off) {
-        %tmp1 = getelementptr i8* %ptr, i32 %off                ; <i8*> [#uses=1]
+        %tmp1 = getelementptr i8, i8* %ptr, i32 %off                ; <i8*> [#uses=1]
         %tmp1.upgrd.3 = bitcast i8* %tmp1 to i16*               ; <i16*> [#uses=1]
         %tmp5 = call i16 @llvm.bswap.i16( i16 %s )              ; <i16> [#uses=1]
         store i16 %tmp5, i16* %tmp1.upgrd.3
@@ -29,15 +29,15 @@ define void @STHBRX(i16 %s, i8* %ptr, i32 %off) {
 }
 
 define i16 @LHBRX(i8* %ptr, i32 %off) {
-        %tmp1 = getelementptr i8* %ptr, i32 %off                ; <i8*> [#uses=1]
+        %tmp1 = getelementptr i8, i8* %ptr, i32 %off                ; <i8*> [#uses=1]
         %tmp1.upgrd.4 = bitcast i8* %tmp1 to i16*               ; <i16*> [#uses=1]
-        %tmp = load i16* %tmp1.upgrd.4          ; <i16> [#uses=1]
+        %tmp = load i16, i16* %tmp1.upgrd.4          ; <i16> [#uses=1]
         %tmp6 = call i16 @llvm.bswap.i16( i16 %tmp )            ; <i16> [#uses=1]
         ret i16 %tmp6
 }
 
 define void @STDBRX(i64 %i, i8* %ptr, i64 %off) {
-        %tmp1 = getelementptr i8* %ptr, i64 %off                ; <i8*> [#uses=1]
+        %tmp1 = getelementptr i8, i8* %ptr, i64 %off                ; <i8*> [#uses=1]
         %tmp1.upgrd.1 = bitcast i8* %tmp1 to i64*               ; <i64*> [#uses=1]
         %tmp13 = tail call i64 @llvm.bswap.i64( i64 %i )                ; <i64> [#uses=1]
         store i64 %tmp13, i64* %tmp1.upgrd.1
@@ -45,9 +45,9 @@ define void @STDBRX(i64 %i, i8* %ptr, i64 %off) {
 }
 
 define i64 @LDBRX(i8* %ptr, i64 %off) {
-        %tmp1 = getelementptr i8* %ptr, i64 %off                ; <i8*> [#uses=1]
+        %tmp1 = getelementptr i8, i8* %ptr, i64 %off                ; <i8*> [#uses=1]
         %tmp1.upgrd.2 = bitcast i8* %tmp1 to i64*               ; <i64*> [#uses=1]
-        %tmp = load i64* %tmp1.upgrd.2          ; <i64> [#uses=1]
+        %tmp = load i64, i64* %tmp1.upgrd.2          ; <i64> [#uses=1]
         %tmp14 = tail call i64 @llvm.bswap.i64( i64 %tmp )              ; <i64> [#uses=1]
         ret i64 %tmp14
 }
diff --git a/test/CodeGen/PowerPC/buildvec_canonicalize.ll b/test/CodeGen/PowerPC/buildvec_canonicalize.ll
index b70671bfd5cb..6c591912d9b2 100644
--- a/test/CodeGen/PowerPC/buildvec_canonicalize.ll
+++ b/test/CodeGen/PowerPC/buildvec_canonicalize.ll
@@ -1,8 +1,8 @@
 ; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math | FileCheck %s
 
 define void @VXOR(<4 x float>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {
-        %tmp = load <4 x float>* %P3            ; <<4 x float>> [#uses=1]
-        %tmp3 = load <4 x float>* %P1           ; <<4 x float>> [#uses=1]
+        %tmp = load <4 x float>, <4 x float>* %P3            ; <<4 x float>> [#uses=1]
+        %tmp3 = load <4 x float>, <4 x float>* %P1           ; <<4 x float>> [#uses=1]
         %tmp4 = fmul <4 x float> %tmp, %tmp3             ; <<4 x float>> [#uses=1]
         store <4 x float> %tmp4, <4 x float>* %P3
         store <4 x float> zeroinitializer, <4 x float>* %P1
diff --git a/test/CodeGen/PowerPC/byval-aliased.ll b/test/CodeGen/PowerPC/byval-aliased.ll
index 9ef2f02f036a..8668e64d4d51 100644
--- a/test/CodeGen/PowerPC/byval-aliased.ll
+++ b/test/CodeGen/PowerPC/byval-aliased.ll
@@ -7,8 +7,8 @@ target triple = "powerpc-apple-macosx10.5.0"
 ; Function Attrs: nounwind ssp
 define void @foo(%struct.sm* byval %s) #0 {
 entry:
-  %a = getelementptr inbounds %struct.sm* %s, i32 0, i32 0
-  %0 = load i8* %a, align 1
+  %a = getelementptr inbounds %struct.sm, %struct.sm* %s, i32 0, i32 0
+  %0 = load i8, i8* %a, align 1
   %conv2 = zext i8 %0 to i32
   %add = add nuw nsw i32 %conv2, 3
   %conv1 = trunc i32 %add to i8
diff --git a/test/CodeGen/PowerPC/cmpb-ppc32.ll b/test/CodeGen/PowerPC/cmpb-ppc32.ll
index 639ed887b978..b5cb0935d886 100644
--- a/test/CodeGen/PowerPC/cmpb-ppc32.ll
+++ b/test/CodeGen/PowerPC/cmpb-ppc32.ll
@@ -17,7 +17,7 @@ entry:
 
 ; CHECK-LABEL: @test16
 ; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
-; CHECK: rlwinm 3, [[REG1]], 0, 16, 31
+; CHECK: clrlwi 3, [[REG1]], 16
 ; CHECK: blr
 }
 
diff --git a/test/CodeGen/PowerPC/cmpb.ll b/test/CodeGen/PowerPC/cmpb.ll
index 7d0c0ab3316b..d1c951df962e 100644
--- a/test/CodeGen/PowerPC/cmpb.ll
+++ b/test/CodeGen/PowerPC/cmpb.ll
@@ -17,7 +17,7 @@ entry:
 
 ; CHECK-LABEL: @test16
 ; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
-; CHECK: rldicl 3, [[REG1]], 0, 48
+; CHECK: clrldi 3, [[REG1]], 48
 ; CHECK: blr
 }
 
@@ -73,7 +73,7 @@ entry:
 
 ; CHECK-LABEL: @test16p3
 ; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
-; CHECK: rldicl [[REG2:[0-9]+]], [[REG1]], 0, 55
+; CHECK: clrldi [[REG2:[0-9]+]], [[REG1]], 55
 ; CHECK: xori 3, [[REG2]], 1280
 ; CHECK: blr
 }
@@ -99,7 +99,7 @@ entry:
 
 ; CHECK-LABEL: @test32
 ; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
-; CHECK: rldicl 3, [[REG1]], 0, 32
+; CHECK: clrldi 3, [[REG1]], 32
 ; CHECK: blr
 }
 
diff --git a/test/CodeGen/PowerPC/code-align.ll b/test/CodeGen/PowerPC/code-align.ll
index 306230be5005..19d1b236ce0d 100644
--- a/test/CodeGen/PowerPC/code-align.ll
+++ b/test/CodeGen/PowerPC/code-align.ll
@@ -44,6 +44,9 @@ entry:
 ; GENERIC-NOT: .align
 ; BASIC: .align  4
 ; PWR: .align  4
+; GENERIC: lwzu
+; BASIC: lwzu
+; PWR: lwzu
 ; GENERIC: bdnz
 ; BASIC: bdnz
 ; PWR: bdnz
@@ -51,17 +54,19 @@ entry:
 vector.body:                                      ; preds = %vector.body, %entry
   %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
   %induction45 = or i64 %index, 1
-  %0 = getelementptr inbounds i32* %a, i64 %index
-  %1 = getelementptr inbounds i32* %a, i64 %induction45
-  %2 = load i32* %0, align 4
-  %3 = load i32* %1, align 4
+  %0 = getelementptr inbounds i32, i32* %a, i64 %index
+  %1 = getelementptr inbounds i32, i32* %a, i64 %induction45
+  %2 = load i32, i32* %0, align 4
+  %3 = load i32, i32* %1, align 4
   %4 = add nsw i32 %2, 4
   %5 = add nsw i32 %3, 4
-  store i32 %4, i32* %0, align 4
-  store i32 %5, i32* %1, align 4
+  %6 = mul nsw i32 %4, 3
+  %7 = mul nsw i32 %5, 3
+  store i32 %6, i32* %0, align 4
+  store i32 %7, i32* %1, align 4
   %index.next = add i64 %index, 2
-  %6 = icmp eq i64 %index.next, 2048
-  br i1 %6, label %for.end, label %vector.body
+  %8 = icmp eq i64 %index.next, 2048
+  br i1 %8, label %for.end, label %vector.body
 
 for.end:                                          ; preds = %vector.body
   ret void
@@ -87,10 +92,11 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, 4
-  store i32 %add, i32* %arrayidx, align 4
+  %mul = mul nsw i32 %add, 3
+  store i32 %mul, i32* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 2048
   br i1 %exitcond, label %for.end, label %for.body
diff --git a/test/CodeGen/PowerPC/compare-simm.ll b/test/CodeGen/PowerPC/compare-simm.ll
index 94c5c0290f58..12eff7bb1813 100644
--- a/test/CodeGen/PowerPC/compare-simm.ll
+++ b/test/CodeGen/PowerPC/compare-simm.ll
@@ -1,7 +1,9 @@
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
-; RUN:   grep "cmpwi cr0, r3, -1"
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s
 
 define i32 @test(i32 %x) nounwind {
+; CHECK-LABEL: @test
+; CHECK: cmpwi r3, -1
+
         %c = icmp eq i32 %x, -1
 	br i1 %c, label %T, label %F
 T:
diff --git a/test/CodeGen/PowerPC/complex-return.ll b/test/CodeGen/PowerPC/complex-return.ll
index 9d25e619d2e5..e419f0799522 100644
--- a/test/CodeGen/PowerPC/complex-return.ll
+++ b/test/CodeGen/PowerPC/complex-return.ll
@@ -7,19 +7,19 @@ define { ppc_fp128, ppc_fp128 } @foo() nounwind {
 entry:
   %retval = alloca { ppc_fp128, ppc_fp128 }, align 16
   %x = alloca { ppc_fp128, ppc_fp128 }, align 16
-  %real = getelementptr inbounds { ppc_fp128, ppc_fp128 }* %x, i32 0, i32 0
-  %imag = getelementptr inbounds { ppc_fp128, ppc_fp128 }* %x, i32 0, i32 1
+  %real = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %x, i32 0, i32 0
+  %imag = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %x, i32 0, i32 1
   store ppc_fp128 0xM400C0000000000000000000000000000, ppc_fp128* %real
   store ppc_fp128 0xMC00547AE147AE1483CA47AE147AE147A, ppc_fp128* %imag
-  %x.realp = getelementptr inbounds { ppc_fp128, ppc_fp128 }* %x, i32 0, i32 0
-  %x.real = load ppc_fp128* %x.realp
-  %x.imagp = getelementptr inbounds { ppc_fp128, ppc_fp128 }* %x, i32 0, i32 1
-  %x.imag = load ppc_fp128* %x.imagp
-  %real1 = getelementptr inbounds { ppc_fp128, ppc_fp128 }* %retval, i32 0, i32 0
-  %imag2 = getelementptr inbounds { ppc_fp128, ppc_fp128 }* %retval, i32 0, i32 1
+  %x.realp = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %x, i32 0, i32 0
+  %x.real = load ppc_fp128, ppc_fp128* %x.realp
+  %x.imagp = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %x, i32 0, i32 1
+  %x.imag = load ppc_fp128, ppc_fp128* %x.imagp
+  %real1 = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %retval, i32 0, i32 0
+  %imag2 = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %retval, i32 0, i32 1
   store ppc_fp128 %x.real, ppc_fp128* %real1
   store ppc_fp128 %x.imag, ppc_fp128* %imag2
-  %0 = load { ppc_fp128, ppc_fp128 }* %retval
+  %0 = load { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %retval
   ret { ppc_fp128, ppc_fp128 } %0
 }
 
@@ -33,19 +33,19 @@ define { float, float } @oof() nounwind {
 entry:
   %retval = alloca { float, float }, align 4
   %x = alloca { float, float }, align 4
-  %real = getelementptr inbounds { float, float }* %x, i32 0, i32 0
-  %imag = getelementptr inbounds { float, float }* %x, i32 0, i32 1
+  %real = getelementptr inbounds { float, float }, { float, float }* %x, i32 0, i32 0
+  %imag = getelementptr inbounds { float, float }, { float, float }* %x, i32 0, i32 1
   store float 3.500000e+00, float* %real
   store float 0xC00547AE20000000, float* %imag
-  %x.realp = getelementptr inbounds { float, float }* %x, i32 0, i32 0
-  %x.real = load float* %x.realp
-  %x.imagp = getelementptr inbounds { float, float }* %x, i32 0, i32 1
-  %x.imag = load float* %x.imagp
-  %real1 = getelementptr inbounds { float, float }* %retval, i32 0, i32 0
-  %imag2 = getelementptr inbounds { float, float }* %retval, i32 0, i32 1
+  %x.realp = getelementptr inbounds { float, float }, { float, float }* %x, i32 0, i32 0
+  %x.real = load float, float* %x.realp
+  %x.imagp = getelementptr inbounds { float, float }, { float, float }* %x, i32 0, i32 1
+  %x.imag = load float, float* %x.imagp
+  %real1 = getelementptr inbounds { float, float }, { float, float }* %retval, i32 0, i32 0
+  %imag2 = getelementptr inbounds { float, float }, { float, float }* %retval, i32 0, i32 1
   store float %x.real, float* %real1
   store float %x.imag, float* %imag2
-  %0 = load { float, float }* %retval
+  %0 = load { float, float }, { float, float }* %retval
   ret { float, float } %0
 }
 
diff --git a/test/CodeGen/PowerPC/cr-spills.ll b/test/CodeGen/PowerPC/cr-spills.ll
index be0dbad6289e..1a903115c0da 100644
--- a/test/CodeGen/PowerPC/cr-spills.ll
+++ b/test/CodeGen/PowerPC/cr-spills.ll
@@ -31,7 +31,7 @@ land.rhs:                                         ; preds = %land.lhs.true, %lan
 
 land.end:                                         ; preds = %land.rhs, %land.lhs.true, %entry
   %0 = phi i1 [ %tobool21, %land.rhs ], [ false, %land.lhs.true ], [ false, %entry ]
-  %cond = load i32** undef, align 8
+  %cond = load i32*, i32** undef, align 8
   br i1 undef, label %if.then95, label %for.body.lr.ph
 
 if.then95:                                        ; preds = %land.end
@@ -52,12 +52,12 @@ for.cond286.preheader:                            ; preds = %for.body252
   br label %for.cond290.preheader
 
 for.cond290.preheader:                            ; preds = %for.end520, %for.cond286.preheader
-  %srcptr.31595 = phi i16* [ getelementptr inbounds ([768 x i16]* @SetupFastFullPelSearch.orig_pels, i64 0, i64 0), %for.cond286.preheader ], [ null, %for.end520 ]
-  %1 = load i32* undef, align 4
-  %2 = load i32* @weight_luma, align 4
-  %3 = load i32* @wp_luma_round, align 4
-  %4 = load i32* @luma_log_weight_denom, align 4
-  %5 = load i32* @offset_luma, align 4
+  %srcptr.31595 = phi i16* [ getelementptr inbounds ([768 x i16], [768 x i16]* @SetupFastFullPelSearch.orig_pels, i64 0, i64 0), %for.cond286.preheader ], [ null, %for.end520 ]
+  %1 = load i32, i32* undef, align 4
+  %2 = load i32, i32* @weight_luma, align 4
+  %3 = load i32, i32* @wp_luma_round, align 4
+  %4 = load i32, i32* @luma_log_weight_denom, align 4
+  %5 = load i32, i32* @offset_luma, align 4
   %incdec.ptr502.sum = add i64 undef, 16
   br label %for.body293
 
@@ -68,7 +68,7 @@ for.body293:                                      ; preds = %for.body293, %for.c
   %LineSadBlk1.01587 = phi i32 [ 0, %for.cond290.preheader ], [ %add402, %for.body293 ]
   %LineSadBlk3.01586 = phi i32 [ 0, %for.cond290.preheader ], [ %add514, %for.body293 ]
   %LineSadBlk2.01585 = phi i32 [ 0, %for.cond290.preheader ], [ %add458, %for.body293 ]
-  %6 = load i16* %refptr.11590, align 2
+  %6 = load i16, i16* %refptr.11590, align 2
   %conv294 = zext i16 %6 to i32
   %mul295 = mul nsw i32 %conv294, %2
   %add296 = add nsw i32 %mul295, %3
@@ -78,16 +78,16 @@ for.body293:                                      ; preds = %for.body293, %for.c
   %cond.i.i1514 = select i1 %cmp.i.i1513, i32 %add297, i32 0
   %cmp.i4.i1515 = icmp slt i32 %cond.i.i1514, %1
   %cond.i5.i1516 = select i1 %cmp.i4.i1515, i32 %cond.i.i1514, i32 %1
-  %7 = load i16* %srcptr.41591, align 2
+  %7 = load i16, i16* %srcptr.41591, align 2
   %conv300 = zext i16 %7 to i32
   %sub301 = sub nsw i32 %cond.i5.i1516, %conv300
   %idxprom302 = sext i32 %sub301 to i64
-  %arrayidx303 = getelementptr inbounds i32* %cond, i64 %idxprom302
-  %8 = load i32* %arrayidx303, align 4
+  %arrayidx303 = getelementptr inbounds i32, i32* %cond, i64 %idxprom302
+  %8 = load i32, i32* %arrayidx303, align 4
   %add304 = add nsw i32 %8, %LineSadBlk0.01588
-  %9 = load i32* undef, align 4
+  %9 = load i32, i32* undef, align 4
   %add318 = add nsw i32 %add304, %9
-  %10 = load i16* undef, align 2
+  %10 = load i16, i16* undef, align 2
   %conv321 = zext i16 %10 to i32
   %mul322 = mul nsw i32 %conv321, %2
   %add323 = add nsw i32 %mul322, %3
@@ -99,23 +99,23 @@ for.body293:                                      ; preds = %for.body293, %for.c
   %cond.i5.i1508 = select i1 %cmp.i4.i1507, i32 %cond.i.i1506, i32 %1
   %sub329 = sub nsw i32 %cond.i5.i1508, 0
   %idxprom330 = sext i32 %sub329 to i64
-  %arrayidx331 = getelementptr inbounds i32* %cond, i64 %idxprom330
-  %11 = load i32* %arrayidx331, align 4
+  %arrayidx331 = getelementptr inbounds i32, i32* %cond, i64 %idxprom330
+  %11 = load i32, i32* %arrayidx331, align 4
   %add332 = add nsw i32 %add318, %11
   %cmp.i.i1501 = icmp sgt i32 undef, 0
   %cond.i.i1502 = select i1 %cmp.i.i1501, i32 undef, i32 0
   %cmp.i4.i1503 = icmp slt i32 %cond.i.i1502, %1
   %cond.i5.i1504 = select i1 %cmp.i4.i1503, i32 %cond.i.i1502, i32 %1
-  %incdec.ptr341 = getelementptr inbounds i16* %srcptr.41591, i64 4
-  %12 = load i16* null, align 2
+  %incdec.ptr341 = getelementptr inbounds i16, i16* %srcptr.41591, i64 4
+  %12 = load i16, i16* null, align 2
   %conv342 = zext i16 %12 to i32
   %sub343 = sub nsw i32 %cond.i5.i1504, %conv342
   %idxprom344 = sext i32 %sub343 to i64
-  %arrayidx345 = getelementptr inbounds i32* %cond, i64 %idxprom344
-  %13 = load i32* %arrayidx345, align 4
+  %arrayidx345 = getelementptr inbounds i32, i32* %cond, i64 %idxprom344
+  %13 = load i32, i32* %arrayidx345, align 4
   %add346 = add nsw i32 %add332, %13
-  %incdec.ptr348 = getelementptr inbounds i16* %refptr.11590, i64 5
-  %14 = load i16* null, align 2
+  %incdec.ptr348 = getelementptr inbounds i16, i16* %refptr.11590, i64 5
+  %14 = load i16, i16* null, align 2
   %conv349 = zext i16 %14 to i32
   %mul350 = mul nsw i32 %conv349, %2
   %add351 = add nsw i32 %mul350, %3
@@ -125,16 +125,16 @@ for.body293:                                      ; preds = %for.body293, %for.c
   %cond.i.i1498 = select i1 %cmp.i.i1497, i32 %add353, i32 0
   %cmp.i4.i1499 = icmp slt i32 %cond.i.i1498, %1
   %cond.i5.i1500 = select i1 %cmp.i4.i1499, i32 %cond.i.i1498, i32 %1
-  %incdec.ptr355 = getelementptr inbounds i16* %srcptr.41591, i64 5
-  %15 = load i16* %incdec.ptr341, align 2
+  %incdec.ptr355 = getelementptr inbounds i16, i16* %srcptr.41591, i64 5
+  %15 = load i16, i16* %incdec.ptr341, align 2
   %conv356 = zext i16 %15 to i32
   %sub357 = sub nsw i32 %cond.i5.i1500, %conv356
   %idxprom358 = sext i32 %sub357 to i64
-  %arrayidx359 = getelementptr inbounds i32* %cond, i64 %idxprom358
-  %16 = load i32* %arrayidx359, align 4
+  %arrayidx359 = getelementptr inbounds i32, i32* %cond, i64 %idxprom358
+  %16 = load i32, i32* %arrayidx359, align 4
   %add360 = add nsw i32 %16, %LineSadBlk1.01587
-  %incdec.ptr362 = getelementptr inbounds i16* %refptr.11590, i64 6
-  %17 = load i16* %incdec.ptr348, align 2
+  %incdec.ptr362 = getelementptr inbounds i16, i16* %refptr.11590, i64 6
+  %17 = load i16, i16* %incdec.ptr348, align 2
   %conv363 = zext i16 %17 to i32
   %mul364 = mul nsw i32 %conv363, %2
   %add365 = add nsw i32 %mul364, %3
@@ -144,16 +144,16 @@ for.body293:                                      ; preds = %for.body293, %for.c
   %cond.i.i1494 = select i1 %cmp.i.i1493, i32 %add367, i32 0
   %cmp.i4.i1495 = icmp slt i32 %cond.i.i1494, %1
   %cond.i5.i1496 = select i1 %cmp.i4.i1495, i32 %cond.i.i1494, i32 %1
-  %incdec.ptr369 = getelementptr inbounds i16* %srcptr.41591, i64 6
-  %18 = load i16* %incdec.ptr355, align 2
+  %incdec.ptr369 = getelementptr inbounds i16, i16* %srcptr.41591, i64 6
+  %18 = load i16, i16* %incdec.ptr355, align 2
   %conv370 = zext i16 %18 to i32
   %sub371 = sub nsw i32 %cond.i5.i1496, %conv370
   %idxprom372 = sext i32 %sub371 to i64
-  %arrayidx373 = getelementptr inbounds i32* %cond, i64 %idxprom372
-  %19 = load i32* %arrayidx373, align 4
+  %arrayidx373 = getelementptr inbounds i32, i32* %cond, i64 %idxprom372
+  %19 = load i32, i32* %arrayidx373, align 4
   %add374 = add nsw i32 %add360, %19
-  %incdec.ptr376 = getelementptr inbounds i16* %refptr.11590, i64 7
-  %20 = load i16* %incdec.ptr362, align 2
+  %incdec.ptr376 = getelementptr inbounds i16, i16* %refptr.11590, i64 7
+  %20 = load i16, i16* %incdec.ptr362, align 2
   %conv377 = zext i16 %20 to i32
   %mul378 = mul nsw i32 %conv377, %2
   %add379 = add nsw i32 %mul378, %3
@@ -163,15 +163,15 @@ for.body293:                                      ; preds = %for.body293, %for.c
   %cond.i.i1490 = select i1 %cmp.i.i1489, i32 %add381, i32 0
   %cmp.i4.i1491 = icmp slt i32 %cond.i.i1490, %1
   %cond.i5.i1492 = select i1 %cmp.i4.i1491, i32 %cond.i.i1490, i32 %1
-  %incdec.ptr383 = getelementptr inbounds i16* %srcptr.41591, i64 7
-  %21 = load i16* %incdec.ptr369, align 2
+  %incdec.ptr383 = getelementptr inbounds i16, i16* %srcptr.41591, i64 7
+  %21 = load i16, i16* %incdec.ptr369, align 2
   %conv384 = zext i16 %21 to i32
   %sub385 = sub nsw i32 %cond.i5.i1492, %conv384
   %idxprom386 = sext i32 %sub385 to i64
-  %arrayidx387 = getelementptr inbounds i32* %cond, i64 %idxprom386
-  %22 = load i32* %arrayidx387, align 4
+  %arrayidx387 = getelementptr inbounds i32, i32* %cond, i64 %idxprom386
+  %22 = load i32, i32* %arrayidx387, align 4
   %add388 = add nsw i32 %add374, %22
-  %23 = load i16* %incdec.ptr376, align 2
+  %23 = load i16, i16* %incdec.ptr376, align 2
   %conv391 = zext i16 %23 to i32
   %mul392 = mul nsw i32 %conv391, %2
   %add395 = add nsw i32 0, %5
@@ -179,26 +179,26 @@ for.body293:                                      ; preds = %for.body293, %for.c
   %cond.i.i1486 = select i1 %cmp.i.i1485, i32 %add395, i32 0
   %cmp.i4.i1487 = icmp slt i32 %cond.i.i1486, %1
   %cond.i5.i1488 = select i1 %cmp.i4.i1487, i32 %cond.i.i1486, i32 %1
-  %incdec.ptr397 = getelementptr inbounds i16* %srcptr.41591, i64 8
-  %24 = load i16* %incdec.ptr383, align 2
+  %incdec.ptr397 = getelementptr inbounds i16, i16* %srcptr.41591, i64 8
+  %24 = load i16, i16* %incdec.ptr383, align 2
   %conv398 = zext i16 %24 to i32
   %sub399 = sub nsw i32 %cond.i5.i1488, %conv398
   %idxprom400 = sext i32 %sub399 to i64
-  %arrayidx401 = getelementptr inbounds i32* %cond, i64 %idxprom400
-  %25 = load i32* %arrayidx401, align 4
+  %arrayidx401 = getelementptr inbounds i32, i32* %cond, i64 %idxprom400
+  %25 = load i32, i32* %arrayidx401, align 4
   %add402 = add nsw i32 %add388, %25
-  %incdec.ptr404 = getelementptr inbounds i16* %refptr.11590, i64 9
+  %incdec.ptr404 = getelementptr inbounds i16, i16* %refptr.11590, i64 9
   %cmp.i4.i1483 = icmp slt i32 undef, %1
   %cond.i5.i1484 = select i1 %cmp.i4.i1483, i32 undef, i32 %1
-  %26 = load i16* %incdec.ptr397, align 2
+  %26 = load i16, i16* %incdec.ptr397, align 2
   %conv412 = zext i16 %26 to i32
   %sub413 = sub nsw i32 %cond.i5.i1484, %conv412
   %idxprom414 = sext i32 %sub413 to i64
-  %arrayidx415 = getelementptr inbounds i32* %cond, i64 %idxprom414
-  %27 = load i32* %arrayidx415, align 4
+  %arrayidx415 = getelementptr inbounds i32, i32* %cond, i64 %idxprom414
+  %27 = load i32, i32* %arrayidx415, align 4
   %add416 = add nsw i32 %27, %LineSadBlk2.01585
-  %incdec.ptr418 = getelementptr inbounds i16* %refptr.11590, i64 10
-  %28 = load i16* %incdec.ptr404, align 2
+  %incdec.ptr418 = getelementptr inbounds i16, i16* %refptr.11590, i64 10
+  %28 = load i16, i16* %incdec.ptr404, align 2
   %conv419 = zext i16 %28 to i32
   %mul420 = mul nsw i32 %conv419, %2
   %add421 = add nsw i32 %mul420, %3
@@ -208,14 +208,14 @@ for.body293:                                      ; preds = %for.body293, %for.c
   %cond.i.i1478 = select i1 %cmp.i.i1477, i32 %add423, i32 0
   %cmp.i4.i1479 = icmp slt i32 %cond.i.i1478, %1
   %cond.i5.i1480 = select i1 %cmp.i4.i1479, i32 %cond.i.i1478, i32 %1
-  %incdec.ptr425 = getelementptr inbounds i16* %srcptr.41591, i64 10
+  %incdec.ptr425 = getelementptr inbounds i16, i16* %srcptr.41591, i64 10
   %sub427 = sub nsw i32 %cond.i5.i1480, 0
   %idxprom428 = sext i32 %sub427 to i64
-  %arrayidx429 = getelementptr inbounds i32* %cond, i64 %idxprom428
-  %29 = load i32* %arrayidx429, align 4
+  %arrayidx429 = getelementptr inbounds i32, i32* %cond, i64 %idxprom428
+  %29 = load i32, i32* %arrayidx429, align 4
   %add430 = add nsw i32 %add416, %29
-  %incdec.ptr432 = getelementptr inbounds i16* %refptr.11590, i64 11
-  %30 = load i16* %incdec.ptr418, align 2
+  %incdec.ptr432 = getelementptr inbounds i16, i16* %refptr.11590, i64 11
+  %30 = load i16, i16* %incdec.ptr418, align 2
   %conv433 = zext i16 %30 to i32
   %mul434 = mul nsw i32 %conv433, %2
   %add435 = add nsw i32 %mul434, %3
@@ -225,15 +225,15 @@ for.body293:                                      ; preds = %for.body293, %for.c
   %cond.i.i1474 = select i1 %cmp.i.i1473, i32 %add437, i32 0
   %cmp.i4.i1475 = icmp slt i32 %cond.i.i1474, %1
   %cond.i5.i1476 = select i1 %cmp.i4.i1475, i32 %cond.i.i1474, i32 %1
-  %31 = load i16* %incdec.ptr425, align 2
+  %31 = load i16, i16* %incdec.ptr425, align 2
   %conv440 = zext i16 %31 to i32
   %sub441 = sub nsw i32 %cond.i5.i1476, %conv440
   %idxprom442 = sext i32 %sub441 to i64
-  %arrayidx443 = getelementptr inbounds i32* %cond, i64 %idxprom442
-  %32 = load i32* %arrayidx443, align 4
+  %arrayidx443 = getelementptr inbounds i32, i32* %cond, i64 %idxprom442
+  %32 = load i32, i32* %arrayidx443, align 4
   %add444 = add nsw i32 %add430, %32
-  %incdec.ptr446 = getelementptr inbounds i16* %refptr.11590, i64 12
-  %33 = load i16* %incdec.ptr432, align 2
+  %incdec.ptr446 = getelementptr inbounds i16, i16* %refptr.11590, i64 12
+  %33 = load i16, i16* %incdec.ptr432, align 2
   %conv447 = zext i16 %33 to i32
   %mul448 = mul nsw i32 %conv447, %2
   %add449 = add nsw i32 %mul448, %3
@@ -243,16 +243,16 @@ for.body293:                                      ; preds = %for.body293, %for.c
   %cond.i.i1470 = select i1 %cmp.i.i1469, i32 %add451, i32 0
   %cmp.i4.i1471 = icmp slt i32 %cond.i.i1470, %1
   %cond.i5.i1472 = select i1 %cmp.i4.i1471, i32 %cond.i.i1470, i32 %1
-  %incdec.ptr453 = getelementptr inbounds i16* %srcptr.41591, i64 12
-  %34 = load i16* undef, align 2
+  %incdec.ptr453 = getelementptr inbounds i16, i16* %srcptr.41591, i64 12
+  %34 = load i16, i16* undef, align 2
   %conv454 = zext i16 %34 to i32
   %sub455 = sub nsw i32 %cond.i5.i1472, %conv454
   %idxprom456 = sext i32 %sub455 to i64
-  %arrayidx457 = getelementptr inbounds i32* %cond, i64 %idxprom456
-  %35 = load i32* %arrayidx457, align 4
+  %arrayidx457 = getelementptr inbounds i32, i32* %cond, i64 %idxprom456
+  %35 = load i32, i32* %arrayidx457, align 4
   %add458 = add nsw i32 %add444, %35
-  %incdec.ptr460 = getelementptr inbounds i16* %refptr.11590, i64 13
-  %36 = load i16* %incdec.ptr446, align 2
+  %incdec.ptr460 = getelementptr inbounds i16, i16* %refptr.11590, i64 13
+  %36 = load i16, i16* %incdec.ptr446, align 2
   %conv461 = zext i16 %36 to i32
   %mul462 = mul nsw i32 %conv461, %2
   %add463 = add nsw i32 %mul462, %3
@@ -262,15 +262,15 @@ for.body293:                                      ; preds = %for.body293, %for.c
   %cond.i.i1466 = select i1 %cmp.i.i1465, i32 %add465, i32 0
   %cmp.i4.i1467 = icmp slt i32 %cond.i.i1466, %1
   %cond.i5.i1468 = select i1 %cmp.i4.i1467, i32 %cond.i.i1466, i32 %1
-  %incdec.ptr467 = getelementptr inbounds i16* %srcptr.41591, i64 13
-  %37 = load i16* %incdec.ptr453, align 2
+  %incdec.ptr467 = getelementptr inbounds i16, i16* %srcptr.41591, i64 13
+  %37 = load i16, i16* %incdec.ptr453, align 2
   %conv468 = zext i16 %37 to i32
   %sub469 = sub nsw i32 %cond.i5.i1468, %conv468
   %idxprom470 = sext i32 %sub469 to i64
-  %arrayidx471 = getelementptr inbounds i32* %cond, i64 %idxprom470
-  %38 = load i32* %arrayidx471, align 4
+  %arrayidx471 = getelementptr inbounds i32, i32* %cond, i64 %idxprom470
+  %38 = load i32, i32* %arrayidx471, align 4
   %add472 = add nsw i32 %38, %LineSadBlk3.01586
-  %incdec.ptr474 = getelementptr inbounds i16* %refptr.11590, i64 14
+  %incdec.ptr474 = getelementptr inbounds i16, i16* %refptr.11590, i64 14
   %add477 = add nsw i32 0, %3
   %shr478 = ashr i32 %add477, %4
   %add479 = add nsw i32 %shr478, %5
@@ -278,16 +278,16 @@ for.body293:                                      ; preds = %for.body293, %for.c
   %cond.i.i1462 = select i1 %cmp.i.i1461, i32 %add479, i32 0
   %cmp.i4.i1463 = icmp slt i32 %cond.i.i1462, %1
   %cond.i5.i1464 = select i1 %cmp.i4.i1463, i32 %cond.i.i1462, i32 %1
-  %incdec.ptr481 = getelementptr inbounds i16* %srcptr.41591, i64 14
-  %39 = load i16* %incdec.ptr467, align 2
+  %incdec.ptr481 = getelementptr inbounds i16, i16* %srcptr.41591, i64 14
+  %39 = load i16, i16* %incdec.ptr467, align 2
   %conv482 = zext i16 %39 to i32
   %sub483 = sub nsw i32 %cond.i5.i1464, %conv482
   %idxprom484 = sext i32 %sub483 to i64
-  %arrayidx485 = getelementptr inbounds i32* %cond, i64 %idxprom484
-  %40 = load i32* %arrayidx485, align 4
+  %arrayidx485 = getelementptr inbounds i32, i32* %cond, i64 %idxprom484
+  %40 = load i32, i32* %arrayidx485, align 4
   %add486 = add nsw i32 %add472, %40
-  %incdec.ptr488 = getelementptr inbounds i16* %refptr.11590, i64 15
-  %41 = load i16* %incdec.ptr474, align 2
+  %incdec.ptr488 = getelementptr inbounds i16, i16* %refptr.11590, i64 15
+  %41 = load i16, i16* %incdec.ptr474, align 2
   %conv489 = zext i16 %41 to i32
   %mul490 = mul nsw i32 %conv489, %2
   %add491 = add nsw i32 %mul490, %3
@@ -297,15 +297,15 @@ for.body293:                                      ; preds = %for.body293, %for.c
   %cond.i.i1458 = select i1 %cmp.i.i1457, i32 %add493, i32 0
   %cmp.i4.i1459 = icmp slt i32 %cond.i.i1458, %1
   %cond.i5.i1460 = select i1 %cmp.i4.i1459, i32 %cond.i.i1458, i32 %1
-  %incdec.ptr495 = getelementptr inbounds i16* %srcptr.41591, i64 15
-  %42 = load i16* %incdec.ptr481, align 2
+  %incdec.ptr495 = getelementptr inbounds i16, i16* %srcptr.41591, i64 15
+  %42 = load i16, i16* %incdec.ptr481, align 2
   %conv496 = zext i16 %42 to i32
   %sub497 = sub nsw i32 %cond.i5.i1460, %conv496
   %idxprom498 = sext i32 %sub497 to i64
-  %arrayidx499 = getelementptr inbounds i32* %cond, i64 %idxprom498
-  %43 = load i32* %arrayidx499, align 4
+  %arrayidx499 = getelementptr inbounds i32, i32* %cond, i64 %idxprom498
+  %43 = load i32, i32* %arrayidx499, align 4
   %add500 = add nsw i32 %add486, %43
-  %44 = load i16* %incdec.ptr488, align 2
+  %44 = load i16, i16* %incdec.ptr488, align 2
   %conv503 = zext i16 %44 to i32
   %mul504 = mul nsw i32 %conv503, %2
   %add505 = add nsw i32 %mul504, %3
@@ -315,14 +315,14 @@ for.body293:                                      ; preds = %for.body293, %for.c
   %cond.i.i1454 = select i1 %cmp.i.i1453, i32 %add507, i32 0
   %cmp.i4.i1455 = icmp slt i32 %cond.i.i1454, %1
   %cond.i5.i1456 = select i1 %cmp.i4.i1455, i32 %cond.i.i1454, i32 %1
-  %45 = load i16* %incdec.ptr495, align 2
+  %45 = load i16, i16* %incdec.ptr495, align 2
   %conv510 = zext i16 %45 to i32
   %sub511 = sub nsw i32 %cond.i5.i1456, %conv510
   %idxprom512 = sext i32 %sub511 to i64
-  %arrayidx513 = getelementptr inbounds i32* %cond, i64 %idxprom512
-  %46 = load i32* %arrayidx513, align 4
+  %arrayidx513 = getelementptr inbounds i32, i32* %cond, i64 %idxprom512
+  %46 = load i32, i32* %arrayidx513, align 4
   %add514 = add nsw i32 %add500, %46
-  %add.ptr517 = getelementptr inbounds i16* %refptr.11590, i64 %incdec.ptr502.sum
+  %add.ptr517 = getelementptr inbounds i16, i16* %refptr.11590, i64 %incdec.ptr502.sum
   %exitcond1692 = icmp eq i32 undef, 4
   br i1 %exitcond1692, label %for.end520, label %for.body293
 
diff --git a/test/CodeGen/PowerPC/cr1eq-no-extra-moves.ll b/test/CodeGen/PowerPC/cr1eq-no-extra-moves.ll
index afa1ea8e75a1..2b3ab9bcceaa 100644
--- a/test/CodeGen/PowerPC/cr1eq-no-extra-moves.ll
+++ b/test/CodeGen/PowerPC/cr1eq-no-extra-moves.ll
@@ -7,14 +7,14 @@ target triple = "powerpc-unknown-linux"
 define void @test(i32 %count) nounwind {
 entry:
 ; CHECK: crxor 6, 6, 6
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i32 1) nounwind
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i32 1) nounwind
   %cmp2 = icmp sgt i32 %count, 0
   br i1 %cmp2, label %for.body, label %for.end
 
 for.body:                                         ; preds = %entry, %for.body
   %i.03 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
 ; CHECK: crxor 6, 6, 6
-  %call1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i32 1) nounwind
+  %call1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i32 1) nounwind
   %inc = add nsw i32 %i.03, 1
   %exitcond = icmp eq i32 %inc, %count
   br i1 %exitcond, label %for.end, label %for.body
diff --git a/test/CodeGen/PowerPC/cr1eq.ll b/test/CodeGen/PowerPC/cr1eq.ll
index fb9c9695d176..43cd4544424c 100644
--- a/test/CodeGen/PowerPC/cr1eq.ll
+++ b/test/CodeGen/PowerPC/cr1eq.ll
@@ -9,9 +9,9 @@ target triple = "powerpc-unknown-freebsd"
 define void @foo() nounwind {
 entry:
 ; CHECK: crxor 6, 6, 6
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 1)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 1)
 ; CHECK: creqv 6, 6, 6
-  %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str1, i32 0, i32 0), double 1.100000e+00)
+  %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str1, i32 0, i32 0), double 1.100000e+00)
   ret void
 }
 
diff --git a/test/CodeGen/PowerPC/cr_spilling.ll b/test/CodeGen/PowerPC/cr_spilling.ll
index 8bd809fe5948..8ac4e7271ac6 100644
--- a/test/CodeGen/PowerPC/cr_spilling.ll
+++ b/test/CodeGen/PowerPC/cr_spilling.ll
@@ -10,7 +10,7 @@ entry:
 	br i1 false, label %cond_true94, label %cond_next99
 
 cond_true94:		; preds = %entry
-	%tmp98 = call i32 (i8*, ...)* @printf(i8* getelementptr ([3 x i8]* @.str242, i32 0, i32 0), i8* null)		; <i32> [#uses=0]
+	%tmp98 = call i32 (i8*, ...) @printf(i8* getelementptr ([3 x i8], [3 x i8]* @.str242, i32 0, i32 0), i8* null)		; <i32> [#uses=0]
 	%tmp20971 = icmp sgt i32 %tmp86, 0		; <i1> [#uses=1]
 	br i1 %tmp20971, label %bb101, label %bb212
 
diff --git a/test/CodeGen/PowerPC/crbit-asm.ll b/test/CodeGen/PowerPC/crbit-asm.ll
index 373e334f02bd..36de3435a081 100644
--- a/test/CodeGen/PowerPC/crbit-asm.ll
+++ b/test/CodeGen/PowerPC/crbit-asm.ll
@@ -12,7 +12,7 @@ entry:
 ; CHECK-LABEL: @testi1
 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
 ; CHECK-DAG: li [[REG1:[0-9]+]], 0
-; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1
+; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
 ; CHECK-DAG: li [[REG4:[0-9]+]], 1
@@ -31,7 +31,7 @@ entry:
 ; CHECK-LABEL: @testi32
 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
 ; CHECK-DAG: li [[REG1:[0-9]+]], 0
-; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1
+; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
 ; CHECK-DAG: li [[REG4:[0-9]+]], -1
@@ -47,7 +47,7 @@ entry:
 ; CHECK-LABEL: @testi8
 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
 ; CHECK-DAG: li [[REG1:[0-9]+]], 0
-; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1
+; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
 ; CHECK-DAG: li [[REG4:[0-9]+]], 1
diff --git a/test/CodeGen/PowerPC/crbits.ll b/test/CodeGen/PowerPC/crbits.ll
index 06e90019db76..ab8655c5c8c6 100644
--- a/test/CodeGen/PowerPC/crbits.ll
+++ b/test/CodeGen/PowerPC/crbits.ll
@@ -107,7 +107,7 @@ entry:
 ; CHECK-LABEL: @test6
 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
 ; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2
-; CHECK-DAG: cror [[REG1:[0-9]+]], 1, 1
+; CHECK-DAG: crmove [[REG1:[0-9]+]], 1
 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
 ; CHECK-DAG: li [[REG2:[0-9]+]], 1
 ; CHECK-DAG: crorc [[REG4:[0-9]+]], 1,
@@ -145,7 +145,7 @@ entry:
 
 define zeroext i32 @exttest8() #0 {
 entry:
-  %v0 = load i64* undef, align 8
+  %v0 = load i64, i64* undef, align 8
   %sub = sub i64 80, %v0
   %div = lshr i64 %sub, 1
   %conv13 = trunc i64 %div to i32
diff --git a/test/CodeGen/PowerPC/crsave.ll b/test/CodeGen/PowerPC/crsave.ll
index 602ba94dc094..8121e1b6e639 100644
--- a/test/CodeGen/PowerPC/crsave.ll
+++ b/test/CodeGen/PowerPC/crsave.ll
@@ -9,7 +9,7 @@ entry:
   %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmpw 2,$2,$1\0A\09mfcr $0", "=r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind
   store i32 %0, i32* %ret, align 4
   call void @foo()
-  %1 = load i32* %ret, align 4
+  %1 = load i32, i32* %ret, align 4
   ret i32 %1
 }
 
@@ -38,7 +38,7 @@ entry:
   %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmpw 2,$2,$1\0A\09cmpw 3,$2,$2\0A\09cmpw 4,$2,$3\0A\09mfcr $0", "=r,r,r,r,r,~{cr2},~{cr3},~{cr4}"(i32 1, i32 2, i32 3, i32 0) nounwind
   store i32 %0, i32* %ret, align 4
   call void @foo()
-  %1 = load i32* %ret, align 4
+  %1 = load i32, i32* %ret, align 4
   ret i32 %1
 }
 
diff --git a/test/CodeGen/PowerPC/crypto_bifs.ll b/test/CodeGen/PowerPC/crypto_bifs.ll
new file mode 100644
index 000000000000..f58935b85b66
--- /dev/null
+++ b/test/CodeGen/PowerPC/crypto_bifs.ll
@@ -0,0 +1,275 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+crypto < %s | FileCheck %s
+; FIXME: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
+; FIXME: The original intent was to add a check-next for the blr after every check.
+; However, this currently fails since we don't eliminate stores of the unused
+; locals. These stores are sometimes scheduled after the crypto instruction
+
+; Function Attrs: nounwind
+define <16 x i8> @test_vpmsumb() #0 {
+entry:
+  %a = alloca <16 x i8>, align 16
+  %b = alloca <16 x i8>, align 16
+  store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %a, align 16
+  store <16 x i8> <i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 112>, <16 x i8>* %b, align 16
+  %0 = load <16 x i8>,  <16 x i8>* %a, align 16
+  %1 = load <16 x i8>,  <16 x i8>* %b, align 16
+  %2 = call <16 x i8> @llvm.ppc.altivec.crypto.vpmsumb(<16 x i8> %0, <16 x i8> %1)
+  ret <16 x i8> %2
+; CHECK: vpmsumb 2,
+}
+
+; Function Attrs: nounwind readnone
+declare <16 x i8> @llvm.ppc.altivec.crypto.vpmsumb(<16 x i8>, <16 x i8>) #1
+
+; Function Attrs: nounwind
+define <8 x i16> @test_vpmsumh() #0 {
+entry:
+  %a = alloca <8 x i16>, align 16
+  %b = alloca <8 x i16>, align 16
+  store <8 x i16> <i16 258, i16 772, i16 1286, i16 1800, i16 2314, i16 2828, i16 3342, i16 3856>, <8 x i16>* %a, align 16
+  store <8 x i16> <i16 29042, i16 29556, i16 30070, i16 30584, i16 31098, i16 31612, i16 32126, i16 32624>, <8 x i16>* %b, align 16
+  %0 = load <8 x i16>,  <8 x i16>* %a, align 16
+  %1 = load <8 x i16>,  <8 x i16>* %b, align 16
+  %2 = call <8 x i16> @llvm.ppc.altivec.crypto.vpmsumh(<8 x i16> %0, <8 x i16> %1)
+  ret <8 x i16> %2
+; CHECK: vpmsumh 2,
+}
+
+; Function Attrs: nounwind readnone
+declare <8 x i16> @llvm.ppc.altivec.crypto.vpmsumh(<8 x i16>, <8 x i16>) #1
+
+; Function Attrs: nounwind
+define <4 x i32> @test_vpmsumw() #0 {
+entry:
+  %a = alloca <4 x i32>, align 16
+  %b = alloca <4 x i32>, align 16
+  store <4 x i32> <i32 16909060, i32 84281096, i32 151653132, i32 219025168>, <4 x i32>* %a, align 16
+  store <4 x i32> <i32 1903326068, i32 1970698104, i32 2038070140, i32 2105442160>, <4 x i32>* %b, align 16
+  %0 = load <4 x i32>,  <4 x i32>* %a, align 16
+  %1 = load <4 x i32>,  <4 x i32>* %b, align 16
+  %2 = call <4 x i32> @llvm.ppc.altivec.crypto.vpmsumw(<4 x i32> %0, <4 x i32> %1)
+  ret <4 x i32> %2
+; CHECK: vpmsumw 2,
+}
+
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.altivec.crypto.vpmsumw(<4 x i32>, <4 x i32>) #1
+
+; Function Attrs: nounwind
+define <2 x i64> @test_vpmsumd() #0 {
+entry:
+  %a = alloca <2 x i64>, align 16
+  %b = alloca <2 x i64>, align 16
+  store <2 x i64> <i64 72623859790382856, i64 651345242494996240>, <2 x i64>* %a, align 16
+  store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %b, align 16
+  %0 = load <2 x i64>,  <2 x i64>* %a, align 16
+  %1 = load <2 x i64>,  <2 x i64>* %b, align 16
+  %2 = call <2 x i64> @llvm.ppc.altivec.crypto.vpmsumd(<2 x i64> %0, <2 x i64> %1)
+  ret <2 x i64> %2
+; CHECK: vpmsumd 2,
+}
+
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.crypto.vpmsumd(<2 x i64>, <2 x i64>) #1
+
+; Function Attrs: nounwind
+define <2 x i64> @test_vsbox() #0 {
+entry:
+  %a = alloca <2 x i64>, align 16
+  store <2 x i64> <i64 72623859790382856, i64 651345242494996240>, <2 x i64>* %a, align 16
+  %0 = load <2 x i64>,  <2 x i64>* %a, align 16
+  %1 = call <2 x i64> @llvm.ppc.altivec.crypto.vsbox(<2 x i64> %0)
+  ret <2 x i64> %1
+; CHECK: vsbox 2,
+}
+
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.crypto.vsbox(<2 x i64>) #1
+
+; Function Attrs: nounwind
+define <16 x i8> @test_vpermxorb() #0 {
+entry:
+  %a = alloca <16 x i8>, align 16
+  %b = alloca <16 x i8>, align 16
+  %c = alloca <16 x i8>, align 16
+  store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %a, align 16
+  store <16 x i8> <i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 112>, <16 x i8>* %b, align 16
+  store <16 x i8> <i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 112>, <16 x i8>* %c, align 16
+  %0 = load <16 x i8>,  <16 x i8>* %a, align 16
+  %1 = load <16 x i8>,  <16 x i8>* %b, align 16
+  %2 = load <16 x i8>,  <16 x i8>* %c, align 16
+  %3 = call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)
+  ret <16 x i8> %3
+; CHECK: vpermxor 2,
+}
+
+; Function Attrs: nounwind readnone
+declare <16 x i8> @llvm.ppc.altivec.crypto.vpermxor(<16 x i8>, <16 x i8>, <16 x i8>) #1
+
+; Function Attrs: nounwind
+define <8 x i16> @test_vpermxorh() #0 {
+entry:
+  %a = alloca <8 x i16>, align 16
+  %b = alloca <8 x i16>, align 16
+  %c = alloca <8 x i16>, align 16
+  store <8 x i16> <i16 258, i16 772, i16 1286, i16 1800, i16 2314, i16 2828, i16 3342, i16 3856>, <8 x i16>* %a, align 16
+  store <8 x i16> <i16 29042, i16 29556, i16 30070, i16 30584, i16 31098, i16 31612, i16 32126, i16 32624>, <8 x i16>* %b, align 16
+  store <8 x i16> <i16 29042, i16 29556, i16 30070, i16 30584, i16 31098, i16 31612, i16 32126, i16 32624>, <8 x i16>* %c, align 16
+  %0 = load <8 x i16>,  <8 x i16>* %a, align 16
+  %1 = bitcast <8 x i16> %0 to <16 x i8>
+  %2 = load <8 x i16>,  <8 x i16>* %b, align 16
+  %3 = bitcast <8 x i16> %2 to <16 x i8>
+  %4 = load <8 x i16>,  <8 x i16>* %c, align 16
+  %5 = bitcast <8 x i16> %4 to <16 x i8>
+  %6 = call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor(<16 x i8> %1, <16 x i8> %3, <16 x i8> %5)
+  %7 = bitcast <16 x i8> %6 to <8 x i16>
+  ret <8 x i16> %7
+; CHECK: vpermxor 2,
+}
+
+; Function Attrs: nounwind
+define <4 x i32> @test_vpermxorw() #0 {
+entry:
+  %a = alloca <4 x i32>, align 16
+  %b = alloca <4 x i32>, align 16
+  %c = alloca <4 x i32>, align 16
+  store <4 x i32> <i32 16909060, i32 84281096, i32 151653132, i32 219025168>, <4 x i32>* %a, align 16
+  store <4 x i32> <i32 1903326068, i32 1970698104, i32 2038070140, i32 2105442160>, <4 x i32>* %b, align 16
+  store <4 x i32> <i32 1903326068, i32 1970698104, i32 2038070140, i32 2105442160>, <4 x i32>* %c, align 16
+  %0 = load <4 x i32>,  <4 x i32>* %a, align 16
+  %1 = bitcast <4 x i32> %0 to <16 x i8>
+  %2 = load <4 x i32>,  <4 x i32>* %b, align 16
+  %3 = bitcast <4 x i32> %2 to <16 x i8>
+  %4 = load <4 x i32>,  <4 x i32>* %c, align 16
+  %5 = bitcast <4 x i32> %4 to <16 x i8>
+  %6 = call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor(<16 x i8> %1, <16 x i8> %3, <16 x i8> %5)
+  %7 = bitcast <16 x i8> %6 to <4 x i32>
+  ret <4 x i32> %7
+; CHECK: vpermxor 2,
+}
+
+; Function Attrs: nounwind
+define <2 x i64> @test_vpermxord() #0 {
+entry:
+  %a = alloca <2 x i64>, align 16
+  %b = alloca <2 x i64>, align 16
+  %c = alloca <2 x i64>, align 16
+  store <2 x i64> <i64 72623859790382856, i64 651345242494996240>, <2 x i64>* %a, align 16
+  store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %b, align 16
+  store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %c, align 16
+  %0 = load <2 x i64>,  <2 x i64>* %a, align 16
+  %1 = bitcast <2 x i64> %0 to <16 x i8>
+  %2 = load <2 x i64>,  <2 x i64>* %b, align 16
+  %3 = bitcast <2 x i64> %2 to <16 x i8>
+  %4 = load <2 x i64>,  <2 x i64>* %c, align 16
+  %5 = bitcast <2 x i64> %4 to <16 x i8>
+  %6 = call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor(<16 x i8> %1, <16 x i8> %3, <16 x i8> %5)
+  %7 = bitcast <16 x i8> %6 to <2 x i64>
+  ret <2 x i64> %7
+; CHECK: vpermxor 2,
+}
+
+; Function Attrs: nounwind
+define <2 x i64> @test_vcipher() #0 {
+entry:
+  %a = alloca <2 x i64>, align 16
+  %b = alloca <2 x i64>, align 16
+  store <2 x i64> <i64 72623859790382856, i64 651345242494996240>, <2 x i64>* %a, align 16
+  store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %b, align 16
+  %0 = load <2 x i64>,  <2 x i64>* %a, align 16
+  %1 = load <2 x i64>,  <2 x i64>* %b, align 16
+  %2 = call <2 x i64> @llvm.ppc.altivec.crypto.vcipher(<2 x i64> %0, <2 x i64> %1)
+  ret <2 x i64> %2
+; CHECK: vcipher 2,
+}
+
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.crypto.vcipher(<2 x i64>, <2 x i64>) #1
+
+; Function Attrs: nounwind
+define <2 x i64> @test_vcipherlast() #0 {
+entry:
+  %a = alloca <2 x i64>, align 16
+  %b = alloca <2 x i64>, align 16
+  store <2 x i64> <i64 72623859790382856, i64 651345242494996240>, <2 x i64>* %a, align 16
+  store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %b, align 16
+  %0 = load <2 x i64>,  <2 x i64>* %a, align 16
+  %1 = load <2 x i64>,  <2 x i64>* %b, align 16
+  %2 = call <2 x i64> @llvm.ppc.altivec.crypto.vcipherlast(<2 x i64> %0, <2 x i64> %1)
+  ret <2 x i64> %2
+; CHECK: vcipherlast 2,
+}
+
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.crypto.vcipherlast(<2 x i64>, <2 x i64>) #1
+
+; Function Attrs: nounwind
+define <2 x i64> @test_vncipher() #0 {
+entry:
+  %a = alloca <2 x i64>, align 16
+  %b = alloca <2 x i64>, align 16
+  store <2 x i64> <i64 72623859790382856, i64 651345242494996240>, <2 x i64>* %a, align 16
+  store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %b, align 16
+  %0 = load <2 x i64>,  <2 x i64>* %a, align 16
+  %1 = load <2 x i64>,  <2 x i64>* %b, align 16
+  %2 = call <2 x i64> @llvm.ppc.altivec.crypto.vncipher(<2 x i64> %0, <2 x i64> %1)
+  ret <2 x i64> %2
+; CHECK: vncipher 2,
+}
+
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.crypto.vncipher(<2 x i64>, <2 x i64>) #1
+
+; Function Attrs: nounwind
+define <2 x i64> @test_vncipherlast() #0 {
+entry:
+  %a = alloca <2 x i64>, align 16
+  %b = alloca <2 x i64>, align 16
+  store <2 x i64> <i64 72623859790382856, i64 651345242494996240>, <2 x i64>* %a, align 16
+  store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %b, align 16
+  %0 = load <2 x i64>,  <2 x i64>* %a, align 16
+  %1 = load <2 x i64>,  <2 x i64>* %b, align 16
+  %2 = call <2 x i64> @llvm.ppc.altivec.crypto.vncipherlast(<2 x i64> %0, <2 x i64> %1)
+  ret <2 x i64> %2
+; CHECK: vncipherlast 2,
+}
+
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.crypto.vncipherlast(<2 x i64>, <2 x i64>) #1
+
+; Function Attrs: nounwind
+define <4 x i32> @test_vshasigmaw() #0 {
+entry:
+  %a = alloca <4 x i32>, align 16
+  store <4 x i32> <i32 16909060, i32 84281096, i32 151653132, i32 219025168>, <4 x i32>* %a, align 16
+  %0 = load <4 x i32>,  <4 x i32>* %a, align 16
+  %1 = call <4 x i32> @llvm.ppc.altivec.crypto.vshasigmaw(<4 x i32> %0, i32 1, i32 15)
+  ret <4 x i32> %1
+; CHECK: vshasigmaw 2,
+}
+
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.altivec.crypto.vshasigmaw(<4 x i32>, i32, i32) #1
+
+; Function Attrs: nounwind
+define <2 x i64> @test_vshasigmad() #0 {
+entry:
+  %a = alloca <2 x i64>, align 16
+  store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %a, align 16
+  %0 = load <2 x i64>,  <2 x i64>* %a, align 16
+  %1 = call <2 x i64> @llvm.ppc.altivec.crypto.vshasigmad(<2 x i64> %0, i32 1, i32 15)
+  ret <2 x i64> %1
+; CHECK: vshasigmad 2,
+}
+
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.crypto.vshasigmad(<2 x i64>, i32, i32) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 230949) (llvm/trunk 230946)"}
diff --git a/test/CodeGen/PowerPC/ctrloop-cpsgn.ll b/test/CodeGen/PowerPC/ctrloop-cpsgn.ll
index 2f0440912cc9..fcfcf154ef58 100644
--- a/test/CodeGen/PowerPC/ctrloop-cpsgn.ll
+++ b/test/CodeGen/PowerPC/ctrloop-cpsgn.ll
@@ -10,8 +10,8 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %x.05 = phi ppc_fp128 [ %d, %entry ], [ %conv, %for.body ]
-  %arrayidx = getelementptr inbounds ppc_fp128* %n, i32 %i.06
-  %0 = load ppc_fp128* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds ppc_fp128, ppc_fp128* %n, i32 %i.06
+  %0 = load ppc_fp128, ppc_fp128* %arrayidx, align 8
   %conv = tail call ppc_fp128 @copysignl(ppc_fp128 %x.05, ppc_fp128 %d) nounwind readonly
   %inc = add nsw i32 %i.06, 1
   %exitcond = icmp eq i32 %inc, 2048
diff --git a/test/CodeGen/PowerPC/ctrloop-fp64.ll b/test/CodeGen/PowerPC/ctrloop-fp64.ll
index 77555ac58de2..6128d7cbdf6f 100644
--- a/test/CodeGen/PowerPC/ctrloop-fp64.ll
+++ b/test/CodeGen/PowerPC/ctrloop-fp64.ll
@@ -10,8 +10,8 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
-  %arrayidx = getelementptr inbounds double* %n, i32 %i.06
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %n, i32 %i.06
+  %0 = load double, double* %arrayidx, align 8
   %conv = sitofp i64 %x.05 to double
   %add = fadd double %conv, %0
   %conv1 = fptosi double %add to i64
@@ -31,7 +31,7 @@ for.end:                                          ; preds = %for.body
 
 define i32 @main(i32 %argc, i8** nocapture %argv) {
 entry:
-  %0 = load double* @init_value, align 8
+  %0 = load double, double* @init_value, align 8
   %conv = fptosi double %0 to i64
   %broadcast.splatinsert.i = insertelement <2 x i64> undef, i64 %conv, i32 0
   %broadcast.splat.i = shufflevector <2 x i64> %broadcast.splatinsert.i, <2 x i64> undef, <2 x i32> zeroinitializer
@@ -39,11 +39,11 @@ entry:
 
 vector.body.i:                                    ; preds = %vector.body.i, %entry
   %index.i = phi i32 [ 0, %entry ], [ %index.next.i, %vector.body.i ]
-  %next.gep.i = getelementptr [8000 x i64]* @data64, i32 0, i32 %index.i
+  %next.gep.i = getelementptr [8000 x i64], [8000 x i64]* @data64, i32 0, i32 %index.i
   %1 = bitcast i64* %next.gep.i to <2 x i64>*
   store <2 x i64> %broadcast.splat.i, <2 x i64>* %1, align 8
   %next.gep.sum24.i = or i32 %index.i, 2
-  %2 = getelementptr [8000 x i64]* @data64, i32 0, i32 %next.gep.sum24.i
+  %2 = getelementptr [8000 x i64], [8000 x i64]* @data64, i32 0, i32 %next.gep.sum24.i
   %3 = bitcast i64* %2 to <2 x i64>*
   store <2 x i64> %broadcast.splat.i, <2 x i64>* %3, align 8
   %index.next.i = add i32 %index.i, 4
diff --git a/test/CodeGen/PowerPC/ctrloop-i64.ll b/test/CodeGen/PowerPC/ctrloop-i64.ll
index 9e01392a458f..5c66a6865ae2 100644
--- a/test/CodeGen/PowerPC/ctrloop-i64.ll
+++ b/test/CodeGen/PowerPC/ctrloop-i64.ll
@@ -10,8 +10,8 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
-  %arrayidx = getelementptr inbounds i64* %n, i32 %i.06
-  %0 = load i64* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds i64, i64* %n, i32 %i.06
+  %0 = load i64, i64* %arrayidx, align 8
   %conv = udiv i64 %x.05, %d
   %conv1 = add i64 %conv, %0
   %inc = add nsw i32 %i.06, 1
@@ -32,8 +32,8 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
-  %arrayidx = getelementptr inbounds i64* %n, i32 %i.06
-  %0 = load i64* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds i64, i64* %n, i32 %i.06
+  %0 = load i64, i64* %arrayidx, align 8
   %conv = sdiv i64 %x.05, %d
   %conv1 = add i64 %conv, %0
   %inc = add nsw i32 %i.06, 1
@@ -54,8 +54,8 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
-  %arrayidx = getelementptr inbounds i64* %n, i32 %i.06
-  %0 = load i64* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds i64, i64* %n, i32 %i.06
+  %0 = load i64, i64* %arrayidx, align 8
   %conv = urem i64 %x.05, %d
   %conv1 = add i64 %conv, %0
   %inc = add nsw i32 %i.06, 1
@@ -76,8 +76,8 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
-  %arrayidx = getelementptr inbounds i64* %n, i32 %i.06
-  %0 = load i64* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds i64, i64* %n, i32 %i.06
+  %0 = load i64, i64* %arrayidx, align 8
   %conv = srem i64 %x.05, %d
   %conv1 = add i64 %conv, %0
   %inc = add nsw i32 %i.06, 1
diff --git a/test/CodeGen/PowerPC/ctrloop-le.ll b/test/CodeGen/PowerPC/ctrloop-le.ll
index 60b0536f9924..bef043703247 100644
--- a/test/CodeGen/PowerPC/ctrloop-le.ll
+++ b/test/CodeGen/PowerPC/ctrloop-le.ll
@@ -18,8 +18,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 28395, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -47,8 +47,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 9073, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -76,8 +76,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 21956, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -105,8 +105,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 16782, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -134,8 +134,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 19097, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -163,8 +163,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -192,8 +192,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -221,8 +221,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -250,8 +250,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -279,8 +279,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -309,8 +309,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -339,8 +339,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -369,8 +369,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -399,8 +399,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -429,8 +429,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
diff --git a/test/CodeGen/PowerPC/ctrloop-lt.ll b/test/CodeGen/PowerPC/ctrloop-lt.ll
index a9dc42c1c971..fa910aab4e0d 100644
--- a/test/CodeGen/PowerPC/ctrloop-lt.ll
+++ b/test/CodeGen/PowerPC/ctrloop-lt.ll
@@ -18,8 +18,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 8531, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -48,8 +48,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 9152, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -78,8 +78,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 18851, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -107,8 +107,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 25466, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -136,8 +136,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 9295, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -165,8 +165,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -194,8 +194,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -223,8 +223,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -252,8 +252,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -281,8 +281,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -310,8 +310,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -339,8 +339,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -368,8 +368,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -397,8 +397,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -426,8 +426,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
diff --git a/test/CodeGen/PowerPC/ctrloop-ne.ll b/test/CodeGen/PowerPC/ctrloop-ne.ll
index 636030a15dd2..13a9909c3d61 100644
--- a/test/CodeGen/PowerPC/ctrloop-ne.ll
+++ b/test/CodeGen/PowerPC/ctrloop-ne.ll
@@ -15,8 +15,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 32623, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -45,8 +45,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 29554, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -75,8 +75,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 15692, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -105,8 +105,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 10449, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -135,8 +135,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ 32087, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -164,8 +164,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -194,8 +194,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -224,8 +224,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -254,8 +254,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -284,8 +284,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -313,8 +313,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -343,8 +343,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -373,8 +373,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -403,8 +403,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
@@ -433,8 +433,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %p, i32 %i.04
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 1
   %conv1 = trunc i32 %add to i8
diff --git a/test/CodeGen/PowerPC/ctrloop-s000.ll b/test/CodeGen/PowerPC/ctrloop-s000.ll
index 4d8ef50501f2..344bbf3b341d 100644
--- a/test/CodeGen/PowerPC/ctrloop-s000.ll
+++ b/test/CodeGen/PowerPC/ctrloop-s000.ll
@@ -35,100 +35,100 @@ for.cond1.preheader:                              ; preds = %for.end, %entry
 
 for.body3:                                        ; preds = %for.body3, %for.cond1.preheader
   %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next.15, %for.body3 ]
-  %arrayidx = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 32
+  %arrayidx = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 32
   %add = fadd double %0, 1.000000e+00
-  %arrayidx5 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv
+  %arrayidx5 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv
   store double %add, double* %arrayidx5, align 32
   %indvars.iv.next11 = or i64 %indvars.iv, 1
-  %arrayidx.1 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next11
-  %1 = load double* %arrayidx.1, align 8
+  %arrayidx.1 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next11
+  %1 = load double, double* %arrayidx.1, align 8
   %add.1 = fadd double %1, 1.000000e+00
-  %arrayidx5.1 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next11
+  %arrayidx5.1 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next11
   store double %add.1, double* %arrayidx5.1, align 8
   %indvars.iv.next.112 = or i64 %indvars.iv, 2
-  %arrayidx.2 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.112
-  %2 = load double* %arrayidx.2, align 16
+  %arrayidx.2 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.112
+  %2 = load double, double* %arrayidx.2, align 16
   %add.2 = fadd double %2, 1.000000e+00
-  %arrayidx5.2 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.112
+  %arrayidx5.2 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.112
   store double %add.2, double* %arrayidx5.2, align 16
   %indvars.iv.next.213 = or i64 %indvars.iv, 3
-  %arrayidx.3 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.213
-  %3 = load double* %arrayidx.3, align 8
+  %arrayidx.3 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.213
+  %3 = load double, double* %arrayidx.3, align 8
   %add.3 = fadd double %3, 1.000000e+00
-  %arrayidx5.3 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.213
+  %arrayidx5.3 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.213
   store double %add.3, double* %arrayidx5.3, align 8
   %indvars.iv.next.314 = or i64 %indvars.iv, 4
-  %arrayidx.4 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.314
-  %4 = load double* %arrayidx.4, align 32
+  %arrayidx.4 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.314
+  %4 = load double, double* %arrayidx.4, align 32
   %add.4 = fadd double %4, 1.000000e+00
-  %arrayidx5.4 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.314
+  %arrayidx5.4 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.314
   store double %add.4, double* %arrayidx5.4, align 32
   %indvars.iv.next.415 = or i64 %indvars.iv, 5
-  %arrayidx.5 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.415
-  %5 = load double* %arrayidx.5, align 8
+  %arrayidx.5 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.415
+  %5 = load double, double* %arrayidx.5, align 8
   %add.5 = fadd double %5, 1.000000e+00
-  %arrayidx5.5 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.415
+  %arrayidx5.5 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.415
   store double %add.5, double* %arrayidx5.5, align 8
   %indvars.iv.next.516 = or i64 %indvars.iv, 6
-  %arrayidx.6 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.516
-  %6 = load double* %arrayidx.6, align 16
+  %arrayidx.6 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.516
+  %6 = load double, double* %arrayidx.6, align 16
   %add.6 = fadd double %6, 1.000000e+00
-  %arrayidx5.6 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.516
+  %arrayidx5.6 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.516
   store double %add.6, double* %arrayidx5.6, align 16
   %indvars.iv.next.617 = or i64 %indvars.iv, 7
-  %arrayidx.7 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.617
-  %7 = load double* %arrayidx.7, align 8
+  %arrayidx.7 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.617
+  %7 = load double, double* %arrayidx.7, align 8
   %add.7 = fadd double %7, 1.000000e+00
-  %arrayidx5.7 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.617
+  %arrayidx5.7 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.617
   store double %add.7, double* %arrayidx5.7, align 8
   %indvars.iv.next.718 = or i64 %indvars.iv, 8
-  %arrayidx.8 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.718
-  %8 = load double* %arrayidx.8, align 32
+  %arrayidx.8 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.718
+  %8 = load double, double* %arrayidx.8, align 32
   %add.8 = fadd double %8, 1.000000e+00
-  %arrayidx5.8 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.718
+  %arrayidx5.8 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.718
   store double %add.8, double* %arrayidx5.8, align 32
   %indvars.iv.next.819 = or i64 %indvars.iv, 9
-  %arrayidx.9 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.819
-  %9 = load double* %arrayidx.9, align 8
+  %arrayidx.9 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.819
+  %9 = load double, double* %arrayidx.9, align 8
   %add.9 = fadd double %9, 1.000000e+00
-  %arrayidx5.9 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.819
+  %arrayidx5.9 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.819
   store double %add.9, double* %arrayidx5.9, align 8
   %indvars.iv.next.920 = or i64 %indvars.iv, 10
-  %arrayidx.10 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.920
-  %10 = load double* %arrayidx.10, align 16
+  %arrayidx.10 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.920
+  %10 = load double, double* %arrayidx.10, align 16
   %add.10 = fadd double %10, 1.000000e+00
-  %arrayidx5.10 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.920
+  %arrayidx5.10 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.920
   store double %add.10, double* %arrayidx5.10, align 16
   %indvars.iv.next.1021 = or i64 %indvars.iv, 11
-  %arrayidx.11 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1021
-  %11 = load double* %arrayidx.11, align 8
+  %arrayidx.11 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1021
+  %11 = load double, double* %arrayidx.11, align 8
   %add.11 = fadd double %11, 1.000000e+00
-  %arrayidx5.11 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1021
+  %arrayidx5.11 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1021
   store double %add.11, double* %arrayidx5.11, align 8
   %indvars.iv.next.1122 = or i64 %indvars.iv, 12
-  %arrayidx.12 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1122
-  %12 = load double* %arrayidx.12, align 32
+  %arrayidx.12 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1122
+  %12 = load double, double* %arrayidx.12, align 32
   %add.12 = fadd double %12, 1.000000e+00
-  %arrayidx5.12 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1122
+  %arrayidx5.12 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1122
   store double %add.12, double* %arrayidx5.12, align 32
   %indvars.iv.next.1223 = or i64 %indvars.iv, 13
-  %arrayidx.13 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1223
-  %13 = load double* %arrayidx.13, align 8
+  %arrayidx.13 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1223
+  %13 = load double, double* %arrayidx.13, align 8
   %add.13 = fadd double %13, 1.000000e+00
-  %arrayidx5.13 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1223
+  %arrayidx5.13 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1223
   store double %add.13, double* %arrayidx5.13, align 8
   %indvars.iv.next.1324 = or i64 %indvars.iv, 14
-  %arrayidx.14 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1324
-  %14 = load double* %arrayidx.14, align 16
+  %arrayidx.14 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1324
+  %14 = load double, double* %arrayidx.14, align 16
   %add.14 = fadd double %14, 1.000000e+00
-  %arrayidx5.14 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1324
+  %arrayidx5.14 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1324
   store double %add.14, double* %arrayidx5.14, align 16
   %indvars.iv.next.1425 = or i64 %indvars.iv, 15
-  %arrayidx.15 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1425
-  %15 = load double* %arrayidx.15, align 8
+  %arrayidx.15 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1425
+  %15 = load double, double* %arrayidx.15, align 8
   %add.15 = fadd double %15, 1.000000e+00
-  %arrayidx5.15 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1425
+  %arrayidx5.15 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1425
   store double %add.15, double* %arrayidx5.15, align 8
   %indvars.iv.next.15 = add i64 %indvars.iv, 16
   %lftr.wideiv.15 = trunc i64 %indvars.iv.next.15 to i32
@@ -136,7 +136,7 @@ for.body3:                                        ; preds = %for.body3, %for.con
   br i1 %exitcond.15, label %for.end, label %for.body3
 
 for.end:                                          ; preds = %for.body3
-  %call = tail call i32 @dummy(double* getelementptr inbounds ([16000 x double]* @X, i64 0, i64 0), double* getelementptr inbounds ([16000 x double]* @Y, i64 0, i64 0), double* getelementptr inbounds ([16000 x double]* @Z, i64 0, i64 0), double* getelementptr inbounds ([16000 x double]* @U, i64 0, i64 0), double* getelementptr inbounds ([16000 x double]* @V, i64 0, i64 0), [256 x double]* getelementptr inbounds ([256 x [256 x double]]* @aa, i64 0, i64 0), [256 x double]* getelementptr inbounds ([256 x [256 x double]]* @bb, i64 0, i64 0), [256 x double]* getelementptr inbounds ([256 x [256 x double]]* @cc, i64 0, i64 0), double 0.000000e+00) nounwind
+  %call = tail call i32 @dummy(double* getelementptr inbounds ([16000 x double], [16000 x double]* @X, i64 0, i64 0), double* getelementptr inbounds ([16000 x double], [16000 x double]* @Y, i64 0, i64 0), double* getelementptr inbounds ([16000 x double], [16000 x double]* @Z, i64 0, i64 0), double* getelementptr inbounds ([16000 x double], [16000 x double]* @U, i64 0, i64 0), double* getelementptr inbounds ([16000 x double], [16000 x double]* @V, i64 0, i64 0), [256 x double]* getelementptr inbounds ([256 x [256 x double]], [256 x [256 x double]]* @aa, i64 0, i64 0), [256 x double]* getelementptr inbounds ([256 x [256 x double]], [256 x [256 x double]]* @bb, i64 0, i64 0), [256 x double]* getelementptr inbounds ([256 x [256 x double]], [256 x [256 x double]]* @cc, i64 0, i64 0), double 0.000000e+00) nounwind
   %inc7 = add nsw i32 %nl.010, 1
   %exitcond = icmp eq i32 %inc7, 400000
   br i1 %exitcond, label %for.end8, label %for.cond1.preheader
diff --git a/test/CodeGen/PowerPC/ctrloop-sh.ll b/test/CodeGen/PowerPC/ctrloop-sh.ll
index d8e6fc79a665..540f0d6b57e6 100644
--- a/test/CodeGen/PowerPC/ctrloop-sh.ll
+++ b/test/CodeGen/PowerPC/ctrloop-sh.ll
@@ -9,8 +9,8 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
-  %0 = load i128* %b, align 16
-  %1 = load i128* %c, align 16
+  %0 = load i128, i128* %b, align 16
+  %1 = load i128, i128* %c, align 16
   %shl = shl i128 %0, %1
   store i128 %shl, i128* %a, align 16
   %inc = add nsw i32 %i.02, 1
@@ -31,8 +31,8 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
-  %0 = load i128* %b, align 16
-  %1 = load i128* %c, align 16
+  %0 = load i128, i128* %b, align 16
+  %1 = load i128, i128* %c, align 16
   %shl = ashr i128 %0, %1
   store i128 %shl, i128* %a, align 16
   %inc = add nsw i32 %i.02, 1
@@ -53,8 +53,8 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
-  %0 = load i128* %b, align 16
-  %1 = load i128* %c, align 16
+  %0 = load i128, i128* %b, align 16
+  %1 = load i128, i128* %c, align 16
   %shl = lshr i128 %0, %1
   store i128 %shl, i128* %a, align 16
   %inc = add nsw i32 %i.02, 1
diff --git a/test/CodeGen/PowerPC/ctrloop-sums.ll b/test/CodeGen/PowerPC/ctrloop-sums.ll
index d9965f280e72..056ee3448c75 100644
--- a/test/CodeGen/PowerPC/ctrloop-sums.ll
+++ b/test/CodeGen/PowerPC/ctrloop-sums.ll
@@ -23,8 +23,8 @@ for.inc6.us:                                      ; preds = %for.body3.us
 for.body3.us:                                     ; preds = %for.body3.us, %for.body3.lr.ph.us
   %indvars.iv = phi i64 [ 0, %for.body3.lr.ph.us ], [ %indvars.iv.next, %for.body3.us ]
   %Result.111.us = phi i32 [ %Result.014.us, %for.body3.lr.ph.us ], [ %add.us, %for.body3.us ]
-  %arrayidx5.us = getelementptr inbounds [100 x i32]* %Array, i64 %indvars.iv16, i64 %indvars.iv
-  %0 = load i32* %arrayidx5.us, align 4
+  %arrayidx5.us = getelementptr inbounds [100 x i32], [100 x i32]* %Array, i64 %indvars.iv16, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx5.us, align 4
   %add.us = add nsw i32 %0, %Result.111.us
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -59,7 +59,7 @@ for.body:                                         ; preds = %for.body, %entry
   %indvars.iv33 = phi i64 [ 0, %entry ], [ %indvars.iv.next34, %for.body ]
   %0 = trunc i64 %indvars.iv33 to i32
   %sub = sub i32 0, %0
-  %arrayidx2 = getelementptr inbounds [100 x [100 x i32]]* %Array, i64 0, i64 %indvars.iv33, i64 %indvars.iv33
+  %arrayidx2 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %Array, i64 0, i64 %indvars.iv33, i64 %indvars.iv33
   store i32 %sub, i32* %arrayidx2, align 4
   %indvars.iv.next34 = add i64 %indvars.iv33, 1
   %lftr.wideiv35 = trunc i64 %indvars.iv.next34 to i32
@@ -79,7 +79,7 @@ for.body8:                                        ; preds = %for.inc14, %for.con
 
 if.then:                                          ; preds = %for.body8
   %3 = add i64 %indvars.iv, %indvars.iv29
-  %arrayidx13 = getelementptr inbounds [100 x [100 x i32]]* %Array, i64 0, i64 %indvars.iv29, i64 %indvars.iv
+  %arrayidx13 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %Array, i64 0, i64 %indvars.iv29, i64 %indvars.iv
   %4 = trunc i64 %3 to i32
   store i32 %4, i32* %arrayidx13, align 4
   br label %for.inc14
@@ -105,8 +105,8 @@ for.inc6.us.i:                                    ; preds = %for.body3.us.i
 for.body3.us.i:                                   ; preds = %for.body3.lr.ph.us.i, %for.body3.us.i
   %indvars.iv.i = phi i64 [ 0, %for.body3.lr.ph.us.i ], [ %indvars.iv.next.i, %for.body3.us.i ]
   %Result.111.us.i = phi i32 [ %Result.014.us.i, %for.body3.lr.ph.us.i ], [ %add.us.i, %for.body3.us.i ]
-  %arrayidx5.us.i = getelementptr inbounds [100 x [100 x i32]]* %Array, i64 0, i64 %indvars.iv16.i, i64 %indvars.iv.i
-  %5 = load i32* %arrayidx5.us.i, align 4
+  %arrayidx5.us.i = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* %Array, i64 0, i64 %indvars.iv16.i, i64 %indvars.iv.i
+  %5 = load i32, i32* %arrayidx5.us.i, align 4
   %add.us.i = add nsw i32 %5, %Result.111.us.i
   %indvars.iv.next.i = add i64 %indvars.iv.i, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next.i to i32
@@ -119,7 +119,7 @@ for.body3.lr.ph.us.i:                             ; preds = %for.inc17, %for.inc
   br label %for.body3.us.i
 
 SumArray.exit:                                    ; preds = %for.inc6.us.i
-  %call20 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([23 x i8]* @.str, i64 0, i64 0), i32 100, i32 100, i32 %add.us.i) nounwind
+  %call20 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([23 x i8], [23 x i8]* @.str, i64 0, i64 0), i32 100, i32 100, i32 %add.us.i) nounwind
   ret i32 0
 
 ; CHECK: @main
diff --git a/test/CodeGen/PowerPC/ctrloops.ll b/test/CodeGen/PowerPC/ctrloops.ll
index ccab7cb7a0ba..fff9e20d2626 100644
--- a/test/CodeGen/PowerPC/ctrloops.ll
+++ b/test/CodeGen/PowerPC/ctrloops.ll
@@ -10,7 +10,7 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
-  %0 = load volatile i32* @a, align 4
+  %0 = load volatile i32, i32* @a, align 4
   %add = add nsw i32 %0, %c
   store volatile i32 %add, i32* @a, align 4
   %inc = add nsw i32 %i.01, 1
@@ -34,7 +34,7 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
-  %0 = load volatile i32* @a, align 4
+  %0 = load volatile i32, i32* @a, align 4
   %add = add nsw i32 %0, %c
   store volatile i32 %add, i32* @a, align 4
   %inc = add nsw i32 %i.02, 1
@@ -58,7 +58,7 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
   %mul = mul nsw i32 %i.02, %c
-  %0 = load volatile i32* @a, align 4
+  %0 = load volatile i32, i32* @a, align 4
   %add = add nsw i32 %0, %mul
   store volatile i32 %add, i32* @a, align 4
   %inc = add nsw i32 %i.02, 1
diff --git a/test/CodeGen/PowerPC/cttz-ctlz-spec.ll b/test/CodeGen/PowerPC/cttz-ctlz-spec.ll
deleted file mode 100644
index 13b017a746ec..000000000000
--- a/test/CodeGen/PowerPC/cttz-ctlz-spec.ll
+++ /dev/null
@@ -1,41 +0,0 @@
-; RUN: opt -S -codegenprepare < %s | FileCheck %s
-target datalayout = "E-m:e-i64:64-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
-define i64 @test1(i64 %A) {
-; CHECK-LABEL: @test1(
-; CHECK: [[CTLZ:%[A-Za-z0-9]+]] = call i64 @llvm.ctlz.i64(i64 %A, i1 false)
-; CHECK-NEXT: ret i64 [[CTLZ]]
-entry:
-  %tobool = icmp eq i64 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i64 [ %0, %cond.true ], [ 64, %entry ]
-  ret i64 %cond
-}
-
-define i64 @test1b(i64 %A) {
-; CHECK-LABEL: @test1b(
-; CHECK: [[CTTZ:%[A-Za-z0-9]+]] = call i64 @llvm.cttz.i64(i64 %A, i1 false)
-; CHECK-NEXT: ret i64 [[CTTZ]]
-entry:
-  %tobool = icmp eq i64 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i64 [ %0, %cond.true ], [ 64, %entry ]
-  ret i64 %cond
-}
-
-declare i64 @llvm.ctlz.i64(i64, i1)
-declare i64 @llvm.cttz.i64(i64, i1)
-
diff --git a/test/CodeGen/PowerPC/cttz.ll b/test/CodeGen/PowerPC/cttz.ll
index 3757fa3e2f29..60de982d91a1 100644
--- a/test/CodeGen/PowerPC/cttz.ll
+++ b/test/CodeGen/PowerPC/cttz.ll
@@ -6,7 +6,7 @@ declare i32 @llvm.cttz.i32(i32, i1)
 define i32 @bar(i32 %x) {
 entry:
 ; CHECK: @bar
-; CHECK: cntlzw
+; CHECK: cntlz
         %tmp.1 = call i32 @llvm.cttz.i32( i32 %x, i1 true )              ; <i32> [#uses=1]
         ret i32 %tmp.1
 }
diff --git a/test/CodeGen/PowerPC/dbg.ll b/test/CodeGen/PowerPC/dbg.ll
index bd153674eab1..87914025b733 100644
--- a/test/CodeGen/PowerPC/dbg.ll
+++ b/test/CodeGen/PowerPC/dbg.ll
@@ -6,8 +6,8 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readnone {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !17
-  tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !18
+  tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !15, metadata !DIExpression()), !dbg !17
+  tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !16, metadata !DIExpression()), !dbg !18
   %add = add nsw i32 %argc, 1, !dbg !19
   ret i32 %add, !dbg !19
 }
@@ -17,23 +17,23 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!22}
 
-!0 = !{!"0x11\0012\00clang version 3.1\001\00\000\00\000", !21, !1, !1, !3, !1, !""} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.1", isOptimized: true, emissionKind: 0, file: !21, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports: !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00main\00main\00\001\000\001\000\006\00256\001\000", !21, null, !7, null, i32 (i32, i8**)* @main, null, null, !13} ; [ DW_TAG_subprogram ]
-!6 = !{!"0x29", !21} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "main", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !21, scope: null, type: !7, function: i32 (i32, i8**)* @main, variables: !13)
+!6 = !DIFile(filename: "dbg.c", directory: "/src")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !9, !10}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!10 = !{!"0xf\00\000\0064\0064\000\000", null, null, !11} ; [ DW_TAG_pointer_type ]
-!11 = !{!"0xf\00\000\0064\0064\000\000", null, null, !12} ; [ DW_TAG_pointer_type ]
-!12 = !{!"0x24\00char\000\008\008\000\000\008", null, null} ; [ DW_TAG_base_type ]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !11)
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !12)
+!12 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_unsigned_char)
 !13 = !{!15, !16}
-!15 = !{!"0x101\00argc\0016777217\000", !5, !6, !9} ; [ DW_TAG_arg_variable ]
-!16 = !{!"0x101\00argv\0033554433\000", !5, !6, !10} ; [ DW_TAG_arg_variable ]
-!17 = !MDLocation(line: 1, column: 14, scope: !5)
-!18 = !MDLocation(line: 1, column: 26, scope: !5)
-!19 = !MDLocation(line: 2, column: 3, scope: !20)
-!20 = !{!"0xb\001\0034\000", !21, !5} ; [ DW_TAG_lexical_block ]
-!21 = !{!"dbg.c", !"/src"}
-!22 = !{i32 1, !"Debug Info Version", i32 2}
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 1, arg: 1, scope: !5, file: !6, type: !9)
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 1, arg: 2, scope: !5, file: !6, type: !10)
+!17 = !DILocation(line: 1, column: 14, scope: !5)
+!18 = !DILocation(line: 1, column: 26, scope: !5)
+!19 = !DILocation(line: 2, column: 3, scope: !20)
+!20 = distinct !DILexicalBlock(line: 1, column: 34, file: !21, scope: !5)
+!21 = !DIFile(filename: "dbg.c", directory: "/src")
+!22 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/PowerPC/dcbt-sched.ll b/test/CodeGen/PowerPC/dcbt-sched.ll
index dfa1b75bd7db..51d58b47ee96 100644
--- a/test/CodeGen/PowerPC/dcbt-sched.ll
+++ b/test/CodeGen/PowerPC/dcbt-sched.ll
@@ -4,9 +4,9 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define i8 @test1(i8* noalias %a, i8* noalias %b, i8* noalias %c) nounwind {
 entry:
-  %q = load i8* %b
+  %q = load i8, i8* %b
   call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 1)
-  %r = load i8* %c
+  %r = load i8, i8* %c
   %s = add i8 %q, %r
   ret i8 %s
 }
diff --git a/test/CodeGen/PowerPC/delete-node.ll b/test/CodeGen/PowerPC/delete-node.ll
index a26c21154824..999af54a8a94 100644
--- a/test/CodeGen/PowerPC/delete-node.ll
+++ b/test/CodeGen/PowerPC/delete-node.ll
@@ -9,11 +9,11 @@ entry:
       	br label %bb1
 
 bb1:            ; preds = %bb1, %entry
-        %0 = load i16* null, align 2            ; <i16> [#uses=1]
+        %0 = load i16, i16* null, align 2            ; <i16> [#uses=1]
         %1 = ashr i16 %0, 4             ; <i16> [#uses=1]
         %2 = sext i16 %1 to i32         ; <i32> [#uses=1]
-        %3 = getelementptr i8* null, i32 %2             ; <i8*> [#uses=1]
-        %4 = load i8* %3, align 1               ; <i8> [#uses=1]
+        %3 = getelementptr i8, i8* null, i32 %2             ; <i8*> [#uses=1]
+        %4 = load i8, i8* %3, align 1               ; <i8> [#uses=1]
         %5 = zext i8 %4 to i32          ; <i32> [#uses=1]
         %6 = shl i32 %5, 24             ; <i32> [#uses=1]
         %7 = or i32 0, %6               ; <i32> [#uses=1]
diff --git a/test/CodeGen/PowerPC/div-e-32.ll b/test/CodeGen/PowerPC/div-e-32.ll
new file mode 100644
index 000000000000..588756bb8dd8
--- /dev/null
+++ b/test/CodeGen/PowerPC/div-e-32.ll
@@ -0,0 +1,31 @@
+; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+
+; Function Attrs: nounwind
+define signext i32 @test1() #0 {
+entry:
+  %0 = call i32 @llvm.ppc.divwe(i32 32, i32 16)
+  ret i32 %0
+; CHECK: divwe 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.divwe(i32, i32) #1
+
+; Function Attrs: nounwind
+define signext i32 @test2() #0 {
+entry:
+  %0 = call i32 @llvm.ppc.divweu(i32 32, i32 16)
+  ret i32 %0
+; CHECK: divweu 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.divweu(i32, i32) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 231831) (llvm/trunk 231828:231843M)"}
diff --git a/test/CodeGen/PowerPC/div-e-all.ll b/test/CodeGen/PowerPC/div-e-all.ll
new file mode 100644
index 000000000000..912deeb2b3e0
--- /dev/null
+++ b/test/CodeGen/PowerPC/div-e-all.ll
@@ -0,0 +1,54 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+
+; Function Attrs: nounwind
+define signext i32 @test1() #0 {
+entry:
+  %0 = call i32 @llvm.ppc.divwe(i32 32, i32 16)
+  ret i32 %0
+; CHECK: divwe 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.divwe(i32, i32) #1
+
+; Function Attrs: nounwind
+define signext i32 @test2() #0 {
+entry:
+  %0 = call i32 @llvm.ppc.divweu(i32 32, i32 16)
+  ret i32 %0
+; CHECK: divweu 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.divweu(i32, i32) #1
+
+; Function Attrs: nounwind
+define i64 @test3() #0 {
+entry:
+  %0 = call i64 @llvm.ppc.divde(i64 32, i64 16)
+  ret i64 %0
+; CHECK: divde 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.divde(i64, i64) #1
+
+; Function Attrs: nounwind
+define i64 @test4() #0 {
+entry:
+  %0 = call i64 @llvm.ppc.divdeu(i64 32, i64 16)
+  ret i64 %0
+; CHECK: divdeu 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.divdeu(i64, i64) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 231831) (llvm/trunk 231828:231843M)"}
diff --git a/test/CodeGen/PowerPC/dyn-alloca-aligned.ll b/test/CodeGen/PowerPC/dyn-alloca-aligned.ll
index a5d45b8e94a0..98b0a175f369 100644
--- a/test/CodeGen/PowerPC/dyn-alloca-aligned.ll
+++ b/test/CodeGen/PowerPC/dyn-alloca-aligned.ll
@@ -11,12 +11,12 @@ entry:
   %0 = zext i32 %n to i64
   %vla = alloca i32, i64 %0, align 128
   %vla1 = alloca i32, i64 %0, align 128
-  %a2 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
-  %1 = load i32* %a2, align 4
+  %a2 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0
+  %1 = load i32, i32* %a2, align 4
   store i32 %1, i32* %vla1, align 128
-  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
-  %2 = load i32* %b, align 4
-  %arrayidx3 = getelementptr inbounds i32* %vla1, i64 1
+  %b = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 1
+  %2 = load i32, i32* %b, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %vla1, i64 1
   store i32 %2, i32* %arrayidx3, align 4
   call void @bar(i32* %vla1, i32* %vla) #0
   ret void
diff --git a/test/CodeGen/PowerPC/early-ret.ll b/test/CodeGen/PowerPC/early-ret.ll
index 7d3e225a1e29..52cf464b9fd5 100644
--- a/test/CodeGen/PowerPC/early-ret.ll
+++ b/test/CodeGen/PowerPC/early-ret.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -45,4 +45,37 @@ if.end3:                                          ; preds = %if.then, %if.then2,
 ; CHECK: blr
 }
 
+
+@.str0 = private unnamed_addr constant [2 x i8] c"a\00"
+@.str1 = private unnamed_addr constant [2 x i8] c"b\00"
+@.str2 = private unnamed_addr constant [2 x i8] c"c\00"
+@.str3 = private unnamed_addr constant [2 x i8] c"d\00"
+@.str4 = private unnamed_addr constant [2 x i8] c"e\00"
+define i8* @dont_assert(i32 %x) {
+; LLVM would assert due to moving an early return into the jump table block and
+; removing one of its predecessors despite that block ending with an indirect
+; branch.
+entry:
+  switch i32 %x, label %sw.epilog [
+    i32 1, label %return
+    i32 2, label %sw.bb1
+    i32 3, label %sw.bb2
+    i32 4, label %sw.bb3
+    i32 255, label %sw.bb4
+  ]
+sw.bb1: br label %return
+sw.bb2: br label %return
+sw.bb3: br label %return
+sw.bb4: br label %return
+sw.epilog: br label %return
+return:
+  %retval.0 = phi i8* [ null, %sw.epilog ],
+                      [ getelementptr inbounds ([2 x i8], [2 x i8]* @.str4, i64 0, i64 0), %sw.bb4 ],
+                      [ getelementptr inbounds ([2 x i8], [2 x i8]* @.str3, i64 0, i64 0), %sw.bb3 ],
+                      [ getelementptr inbounds ([2 x i8], [2 x i8]* @.str2, i64 0, i64 0), %sw.bb2 ],
+                      [ getelementptr inbounds ([2 x i8], [2 x i8]* @.str1, i64 0, i64 0), %sw.bb1 ],
+                      [ getelementptr inbounds ([2 x i8], [2 x i8]* @.str0, i64 0, i64 0), %entry ]
+  ret i8* %retval.0
+}
+
 attributes #0 = { nounwind }
diff --git a/test/CodeGen/PowerPC/ec-input.ll b/test/CodeGen/PowerPC/ec-input.ll
new file mode 100644
index 000000000000..a57f69be12da
--- /dev/null
+++ b/test/CodeGen/PowerPC/ec-input.ll
@@ -0,0 +1,155 @@
+; RUN: llc -verify-machineinstrs < %s | FileCheck %s
+; This test case used to fail both with and without -verify-machineinstrs
+; (-verify-machineinstrs would catch the problem right after instruction
+; scheduling because the live intervals would not be right for the registers
+; that were both inputs to the inline asm and also early-clobber outputs).
+
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713 = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker.118.8248.32638.195238.200116.211498.218002.221254.222880.224506.226132.240766.244018.245644.248896.260278.271660.281416.283042.302554.304180.325318.326944.344712*, %struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713*, i32, i32, i64, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i64, i32, [20 x i8] }
+%struct._IO_marker.118.8248.32638.195238.200116.211498.218002.221254.222880.224506.226132.240766.244018.245644.248896.260278.271660.281416.283042.302554.304180.325318.326944.344712 = type { %struct._IO_marker.118.8248.32638.195238.200116.211498.218002.221254.222880.224506.226132.240766.244018.245644.248896.260278.271660.281416.283042.302554.304180.325318.326944.344712*, %struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713*, i32 }
+
+@.str236 = external unnamed_addr constant [121 x i8], align 1
+@.str294 = external unnamed_addr constant [49 x i8], align 1
+
+; Function Attrs: nounwind
+declare void @fprintf(%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713* nocapture, i8* nocapture readonly, ...) #0
+
+; Function Attrs: inlinehint nounwind
+define void @_ZN4PAMI6Device2MU15ResourceManager46calculatePerCoreMUResourcesBasedOnAvailabilityEv() #1 align 2 {
+; CHECK-LABEL: @_ZN4PAMI6Device2MU15ResourceManager46calculatePerCoreMUResourcesBasedOnAvailabilityEv
+; CHECK: sc
+
+entry:
+  %numFreeResourcesInSubgroup = alloca i32, align 4
+  %0 = ptrtoint i32* %numFreeResourcesInSubgroup to i64
+  br label %for.cond2.preheader
+
+for.cond2.preheader:                              ; preds = %if.end23.3, %entry
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end23.3 ]
+  %group.098 = phi i32 [ 0, %entry ], [ %inc37, %if.end23.3 ]
+  %minFreeBatIdsPerCore.097 = phi i64 [ 32, %entry ], [ %numFreeBatIdsInGroup.0.minFreeBatIdsPerCore.0, %if.end23.3 ]
+  %minFreeRecFifosPerCore.096 = phi i64 [ 16, %entry ], [ %minFreeRecFifosPerCore.1, %if.end23.3 ]
+  %minFreeInjFifosPerCore.095 = phi i64 [ 32, %entry ], [ %numFreeInjFifosInGroup.0.minFreeInjFifosPerCore.0, %if.end23.3 ]
+  %cmp5 = icmp eq i32 undef, 0
+  br i1 %cmp5, label %if.end, label %if.then
+
+if.then:                                          ; preds = %if.end23.2, %if.end23.1, %if.end23, %for.cond2.preheader
+  unreachable
+
+if.end:                                           ; preds = %for.cond2.preheader
+  %1 = load i32, i32* %numFreeResourcesInSubgroup, align 4
+  %conv = zext i32 %1 to i64
+  %2 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1034, i64 %indvars.iv, i64 %0, i64 undef) #2
+  %cmp10 = icmp eq i32 0, 0
+  br i1 %cmp10, label %if.end14, label %if.then11
+
+if.then11:                                        ; preds = %if.end.3, %if.end.2, %if.end.1, %if.end
+  unreachable
+
+if.end14:                                         ; preds = %if.end
+  %3 = load i32, i32* %numFreeResourcesInSubgroup, align 4
+  %cmp19 = icmp eq i32 undef, 0
+  br i1 %cmp19, label %if.end23, label %if.then20
+
+if.then20:                                        ; preds = %if.end14.3, %if.end14.2, %if.end14.1, %if.end14
+  %conv4.i65.lcssa = phi i32 [ undef, %if.end14 ], [ 0, %if.end14.1 ], [ %conv4.i65.2, %if.end14.2 ], [ %conv4.i65.3, %if.end14.3 ]
+  call void (%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713*, i8*, ...) @fprintf(%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713* undef, i8* getelementptr inbounds ([121 x i8], [121 x i8]* @.str236, i64 0, i64 0), i32 signext 2503) #3
+  call void (%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713*, i8*, ...) @fprintf(%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713* undef, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @.str294, i64 0, i64 0), i32 signext %conv4.i65.lcssa) #3
+  unreachable
+
+if.end23:                                         ; preds = %if.end14
+  %conv15 = zext i32 %3 to i64
+  %4 = load i32, i32* %numFreeResourcesInSubgroup, align 4
+  %conv24 = zext i32 %4 to i64
+  %5 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1033, i64 0, i64 %0, i64 undef) #2
+  %cmp5.1 = icmp eq i32 0, 0
+  br i1 %cmp5.1, label %if.end.1, label %if.then
+
+for.end38:                                        ; preds = %if.end23.3
+  ret void
+
+if.end.1:                                         ; preds = %if.end23
+  %6 = load i32, i32* %numFreeResourcesInSubgroup, align 4
+  %conv.1 = zext i32 %6 to i64
+  %add.1 = add nuw nsw i64 %conv.1, %conv
+  %7 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1034, i64 0, i64 %0, i64 undef) #2
+  %cmp10.1 = icmp eq i32 undef, 0
+  br i1 %cmp10.1, label %if.end14.1, label %if.then11
+
+if.end14.1:                                       ; preds = %if.end.1
+  %8 = load i32, i32* %numFreeResourcesInSubgroup, align 4
+  %cmp19.1 = icmp eq i32 0, 0
+  br i1 %cmp19.1, label %if.end23.1, label %if.then20
+
+if.end23.1:                                       ; preds = %if.end14.1
+  %conv15.1 = zext i32 %8 to i64
+  %add16.1 = add nuw nsw i64 %conv15.1, %conv15
+  %9 = load i32, i32* %numFreeResourcesInSubgroup, align 4
+  %conv24.1 = zext i32 %9 to i64
+  %add25.1 = add nuw nsw i64 %conv24.1, %conv24
+  %cmp5.2 = icmp eq i32 undef, 0
+  br i1 %cmp5.2, label %if.end.2, label %if.then
+
+if.end.2:                                         ; preds = %if.end23.1
+  %10 = load i32, i32* %numFreeResourcesInSubgroup, align 4
+  %conv.2 = zext i32 %10 to i64
+  %add.2 = add nuw nsw i64 %conv.2, %add.1
+  %11 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1034, i64 undef, i64 %0, i64 undef) #2
+  %cmp10.2 = icmp eq i32 0, 0
+  br i1 %cmp10.2, label %if.end14.2, label %if.then11
+
+if.end14.2:                                       ; preds = %if.end.2
+  %12 = load i32, i32* %numFreeResourcesInSubgroup, align 4
+  %13 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1035, i64 undef, i64 %0, i64 0) #2
+  %asmresult1.i64.2 = extractvalue { i64, i64, i64, i64 } %13, 1
+  %conv4.i65.2 = trunc i64 %asmresult1.i64.2 to i32
+  %cmp19.2 = icmp eq i32 %conv4.i65.2, 0
+  br i1 %cmp19.2, label %if.end23.2, label %if.then20
+
+if.end23.2:                                       ; preds = %if.end14.2
+  %conv15.2 = zext i32 %12 to i64
+  %add16.2 = add nuw nsw i64 %conv15.2, %add16.1
+  %14 = load i32, i32* %numFreeResourcesInSubgroup, align 4
+  %conv24.2 = zext i32 %14 to i64
+  %add25.2 = add nuw nsw i64 %conv24.2, %add25.1
+  %cmp5.3 = icmp eq i32 0, 0
+  br i1 %cmp5.3, label %if.end.3, label %if.then
+
+if.end.3:                                         ; preds = %if.end23.2
+  %15 = load i32, i32* %numFreeResourcesInSubgroup, align 4
+  %conv.3 = zext i32 %15 to i64
+  %add.3 = add nuw nsw i64 %conv.3, %add.2
+  %cmp10.3 = icmp eq i32 undef, 0
+  br i1 %cmp10.3, label %if.end14.3, label %if.then11
+
+if.end14.3:                                       ; preds = %if.end.3
+  %16 = load i32, i32* %numFreeResourcesInSubgroup, align 4
+  %17 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1035, i64 0, i64 %0, i64 0) #2
+  %asmresult1.i64.3 = extractvalue { i64, i64, i64, i64 } %17, 1
+  %conv4.i65.3 = trunc i64 %asmresult1.i64.3 to i32
+  %cmp19.3 = icmp eq i32 %conv4.i65.3, 0
+  br i1 %cmp19.3, label %if.end23.3, label %if.then20
+
+if.end23.3:                                       ; preds = %if.end14.3
+  %conv15.3 = zext i32 %16 to i64
+  %add16.3 = add nuw nsw i64 %conv15.3, %add16.2
+  %add25.3 = add nuw nsw i64 0, %add25.2
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 4
+  %cmp27 = icmp ult i64 %add.3, %minFreeInjFifosPerCore.095
+  %numFreeInjFifosInGroup.0.minFreeInjFifosPerCore.0 = select i1 %cmp27, i64 %add.3, i64 %minFreeInjFifosPerCore.095
+  %cmp30 = icmp ult i64 %add16.3, %minFreeRecFifosPerCore.096
+  %minFreeRecFifosPerCore.1 = select i1 %cmp30, i64 %add16.3, i64 %minFreeRecFifosPerCore.096
+  %cmp33 = icmp ult i64 %add25.3, %minFreeBatIdsPerCore.097
+  %numFreeBatIdsInGroup.0.minFreeBatIdsPerCore.0 = select i1 %cmp33, i64 %add25.3, i64 %minFreeBatIdsPerCore.097
+  %inc37 = add nuw nsw i32 %group.098, 1
+  %cmp = icmp ult i32 %inc37, 16
+  br i1 %cmp, label %for.cond2.preheader, label %for.end38
+}
+
+attributes #0 = { nounwind "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "target-cpu"="a2q" }
+attributes #1 = { inlinehint nounwind "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "target-cpu"="a2q" }
+attributes #2 = { nounwind }
+attributes #3 = { cold nounwind }
+
diff --git a/test/CodeGen/PowerPC/empty-functions.ll b/test/CodeGen/PowerPC/empty-functions.ll
index e32a8472b835..aa760d82b1c7 100644
--- a/test/CodeGen/PowerPC/empty-functions.ll
+++ b/test/CodeGen/PowerPC/empty-functions.ll
@@ -17,16 +17,18 @@ entry:
 
 ; An empty function is perfectly fine on ELF.
 ; LINUX-NO-FP: func:
+; LINUX-NO-FP-NEXT: {{^}}.L[[BEGIN:.*]]:{{$}}
 ; LINUX-NO-FP-NEXT: .cfi_startproc
 ; LINUX-NO-FP-NEXT: {{^}}#
-; LINUX-NO-FP-NEXT: {{^}}.L{{.*}}:{{$}}
-; LINUX-NO-FP-NEXT: .size   func, .L{{.*}}-func
+; LINUX-NO-FP-NEXT: {{^}}.L[[END:.*]]:{{$}}
+; LINUX-NO-FP-NEXT: .size   func, .L[[END]]-.L[[BEGIN]]
 ; LINUX-NO-FP-NEXT: .cfi_endproc
 
 ; A cfi directive can point to the end of a function. It (and in fact the
 ; entire body) could be optimized out because of the unreachable, but we
 ; don't do it right now.
 ; LINUX-FP: func:
+; LINUX-FP-NEXT: {{^}}.L[[BEGIN:.*]]:{{$}}
 ; LINUX-FP-NEXT: .cfi_startproc
 ; LINUX-FP-NEXT: {{^}}#
 ; LINUX-FP-NEXT: stw 31, -4(1)
@@ -38,6 +40,6 @@ entry:
 ; LINUX-FP-NEXT: mr 31, 1
 ; LINUX-FP-NEXT:{{^}}.L{{.*}}:{{$}}
 ; LINUX-FP-NEXT: .cfi_def_cfa_register r31
-; LINUX-FP-NEXT:{{^}}.L{{.*}}:{{$}}
-; LINUX-FP-NEXT: .size   func, .Ltmp3-func
+; LINUX-FP-NEXT: {{^}}.L[[END:.*]]:{{$}}
+; LINUX-FP-NEXT: .size   func, .L[[END]]-.L[[BEGIN]]
 ; LINUX-FP-NEXT: .cfi_endproc
diff --git a/test/CodeGen/PowerPC/emptystruct.ll b/test/CodeGen/PowerPC/emptystruct.ll
index 47cfadd0a7bb..66cada14f9d2 100644
--- a/test/CodeGen/PowerPC/emptystruct.ll
+++ b/test/CodeGen/PowerPC/emptystruct.ll
@@ -18,7 +18,7 @@ define void @callee(%struct.empty* noalias sret %agg.result, %struct.empty* byva
 entry:
   %a2.addr = alloca %struct.empty*, align 8
   store %struct.empty* %a2, %struct.empty** %a2.addr, align 8
-  %0 = load %struct.empty** %a2.addr, align 8
+  %0 = load %struct.empty*, %struct.empty** %a2.addr, align 8
   %1 = bitcast %struct.empty* %agg.result to i8*
   %2 = bitcast %struct.empty* %0 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 0, i32 1, i1 false)
diff --git a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
index f99089b3bb02..f90eccb359a8 100644
--- a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
+++ b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
@@ -69,9 +69,9 @@ define i32 @NAND1(i32 %X, i32 %Y) nounwind {
 }
 
 define void @VNOR(<4 x float>* %P, <4 x float>* %Q) nounwind {
-	%tmp = load <4 x float>* %P		; <<4 x float>> [#uses=1]
+	%tmp = load <4 x float>, <4 x float>* %P		; <<4 x float>> [#uses=1]
 	%tmp.upgrd.1 = bitcast <4 x float> %tmp to <4 x i32>		; <<4 x i32>> [#uses=1]
-	%tmp2 = load <4 x float>* %Q		; <<4 x float>> [#uses=1]
+	%tmp2 = load <4 x float>, <4 x float>* %Q		; <<4 x float>> [#uses=1]
 	%tmp2.upgrd.2 = bitcast <4 x float> %tmp2 to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp3 = or <4 x i32> %tmp.upgrd.1, %tmp2.upgrd.2		; <<4 x i32>> [#uses=1]
 	%tmp4 = xor <4 x i32> %tmp3, < i32 -1, i32 -1, i32 -1, i32 -1 >		; <<4 x i32>> [#uses=1]
@@ -81,9 +81,9 @@ define void @VNOR(<4 x float>* %P, <4 x float>* %Q) nounwind {
 }
 
 define void @VANDC(<4 x float>* %P, <4 x float>* %Q) nounwind {
-	%tmp = load <4 x float>* %P		; <<4 x float>> [#uses=1]
+	%tmp = load <4 x float>, <4 x float>* %P		; <<4 x float>> [#uses=1]
 	%tmp.upgrd.4 = bitcast <4 x float> %tmp to <4 x i32>		; <<4 x i32>> [#uses=1]
-	%tmp2 = load <4 x float>* %Q		; <<4 x float>> [#uses=1]
+	%tmp2 = load <4 x float>, <4 x float>* %Q		; <<4 x float>> [#uses=1]
 	%tmp2.upgrd.5 = bitcast <4 x float> %tmp2 to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp4 = xor <4 x i32> %tmp2.upgrd.5, < i32 -1, i32 -1, i32 -1, i32 -1 >		; <<4 x i32>> [#uses=1]
 	%tmp3 = and <4 x i32> %tmp.upgrd.4, %tmp4		; <<4 x i32>> [#uses=1]
diff --git a/test/CodeGen/PowerPC/extra-toc-reg-deps.ll b/test/CodeGen/PowerPC/extra-toc-reg-deps.ll
new file mode 100644
index 000000000000..1056c5a57aac
--- /dev/null
+++ b/test/CodeGen/PowerPC/extra-toc-reg-deps.ll
@@ -0,0 +1,430 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+%"class.Foam::messageStream.6" = type <{ %"class.Foam::string.5", i32, i32, i32, [4 x i8] }>
+%"class.Foam::string.5" = type { %"class.std::basic_string.4" }
+%"class.std::basic_string.4" = type { %"struct.std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_Alloc_hider.3" }
+%"struct.std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_Alloc_hider.3" = type { i8* }
+%"class.Foam::prefixOSstream.27" = type { %"class.Foam::OSstream.26", i8, %"class.Foam::string.5" }
+%"class.Foam::OSstream.26" = type { %"class.Foam::Ostream.base.9", %"class.Foam::fileName.10", %"class.std::basic_ostream.25"* }
+%"class.Foam::Ostream.base.9" = type <{ %"class.Foam::IOstream.8", i16 }>
+%"class.Foam::IOstream.8" = type { i32 (...)**, i32, [4 x i8], %"class.Foam::IOstream::versionNumber.7", i32, i32, i32, i32 }
+%"class.Foam::IOstream::versionNumber.7" = type <{ double, i32, [4 x i8] }>
+%"class.Foam::fileName.10" = type { %"class.Foam::string.5" }
+%"class.std::basic_ostream.25" = type { i32 (...)**, %"class.std::basic_ios.24" }
+%"class.std::basic_ios.24" = type { %"class.std::ios_base.16", %"class.std::basic_ostream.25"*, i8, i8, %"class.std::basic_streambuf.17"*, %"class.std::ctype.21"*, %"class.std::__gnu_cxx_ldbl128::num_put.22"*, %"class.std::__gnu_cxx_ldbl128::num_get.23"* }
+%"class.std::ios_base.16" = type { i32 (...)**, i64, i64, i32, i32, i32, %"struct.std::ios_base::_Callback_list.11"*, %"struct.std::ios_base::_Words.12", [8 x %"struct.std::ios_base::_Words.12"], i32, %"struct.std::ios_base::_Words.12"*, %"class.std::locale.15" }
+%"struct.std::ios_base::_Callback_list.11" = type { %"struct.std::ios_base::_Callback_list.11"*, void (i32, %"class.std::ios_base.16"*, i32)*, i32, i32 }
+%"struct.std::ios_base::_Words.12" = type { i8*, i64 }
+%"class.std::locale.15" = type { %"class.std::locale::_Impl.14"* }
+%"class.std::locale::_Impl.14" = type { i32, %"class.std::locale::facet.13"**, i64, %"class.std::locale::facet.13"**, i8** }
+%"class.std::locale::facet.13" = type <{ i32 (...)**, i32, [4 x i8] }>
+%"class.std::basic_streambuf.17" = type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %"class.std::locale.15" }
+%"class.std::ctype.21" = type <{ %"class.std::locale::facet.base.18", [4 x i8], %struct.__locale_struct.20*, i8, [7 x i8], i32*, i32*, i16*, i8, [256 x i8], [256 x i8], i8, [6 x i8] }>
+%"class.std::locale::facet.base.18" = type <{ i32 (...)**, i32 }>
+%struct.__locale_struct.20 = type { [13 x %struct.__locale_data.19*], i16*, i32*, i32*, [13 x i8*] }
+%struct.__locale_data.19 = type opaque
+%"class.std::__gnu_cxx_ldbl128::num_put.22" = type { %"class.std::locale::facet.base.18", [4 x i8] }
+%"class.std::__gnu_cxx_ldbl128::num_get.23" = type { %"class.std::locale::facet.base.18", [4 x i8] }
+%"class.Foam::primitiveMesh.135" = type { i32 (...)**, i32, i32, i32, i32, i32, i32, i32, i32, i32, %"class.Foam::List.116"*, %"class.Foam::List.0"*, %"class.Foam::List.1"*, %"class.Foam::List.1"*, %"class.Foam::List.1"*, %"class.Foam::List.5"*, %"class.Foam::List.1"*, %"class.Foam::List.1"*, %"class.Foam::List.1"*, %"class.Foam::List.1"*, %"class.Foam::List.1"*, %"class.Foam::List.1"*, %"class.Foam::List.1"*, %"class.Foam::DynamicList.40", %"class.Foam::HashSet.127", %"class.Foam::Field.131"*, %"class.Foam::Field.131"*, %"class.Foam::Field.11"*, %"class.Foam::Field.131"* }
+%"class.Foam::List.116" = type opaque
+%"class.Foam::List.0" = type { %"class.Foam::UList.119" }
+%"class.Foam::UList.119" = type { i32, %"class.Foam::edge.118"* }
+%"class.Foam::edge.118" = type { %"class.Foam::FixedList.117" }
+%"class.Foam::FixedList.117" = type { [2 x i32] }
+%"class.Foam::List.5" = type { %"class.Foam::UList.6" }
+%"class.Foam::UList.6" = type { i32, %"class.Foam::cell.121"* }
+%"class.Foam::cell.121" = type { %"class.Foam::List.3" }
+%"class.Foam::List.3" = type { %"class.Foam::UList.4" }
+%"class.Foam::UList.4" = type { i32, i32* }
+%"class.Foam::List.1" = type { %"class.Foam::UList.2" }
+%"class.Foam::UList.2" = type { i32, %"class.Foam::List.3"* }
+%"class.Foam::DynamicList.40" = type <{ %"class.Foam::List.3", i32, [4 x i8] }>
+%"class.Foam::HashSet.127" = type { %"class.Foam::HashTable.7" }
+%"class.Foam::HashTable.7" = type { i32, i32, %"struct.Foam::HashTable<Foam::nil, int, Foam::Hash<Foam::label> >::hashedEntry.125"** }
+%"struct.Foam::HashTable<Foam::nil, int, Foam::Hash<Foam::label> >::hashedEntry.125" = type <{ i32, [4 x i8], %"struct.Foam::HashTable<Foam::nil, int, Foam::Hash<Foam::label> >::hashedEntry.125"*, %"class.Foam::nil.124", [7 x i8] }>
+%"class.Foam::nil.124" = type { i8 }
+%"class.Foam::Field.11" = type { %"class.Foam::refCount.128", %"class.Foam::List.12" }
+%"class.Foam::refCount.128" = type { i32 }
+%"class.Foam::List.12" = type { %"class.Foam::UList.13" }
+%"class.Foam::UList.13" = type { i32, double* }
+%"class.Foam::Field.131" = type { %"class.Foam::refCount.128", %"class.Foam::List.8" }
+%"class.Foam::List.8" = type { %"class.Foam::UList.9" }
+%"class.Foam::UList.9" = type { i32, %"class.Foam::Vector.29"* }
+%"class.Foam::Vector.29" = type { %"class.Foam::VectorSpace.10" }
+%"class.Foam::VectorSpace.10" = type { [3 x double] }
+%"class.Foam::Ostream.189" = type <{ %"class.Foam::IOstream.8", i16, [6 x i8] }>
+
+@_ZN4Foam4InfoE = external global %"class.Foam::messageStream.6", align 8
+@.str27 = external unnamed_addr constant [24 x i8], align 1
+@.str28 = external unnamed_addr constant [7 x i8], align 1
+@_ZN4Foam4PoutE = external global %"class.Foam::prefixOSstream.27", align 8
+
+define void @_ZN4Foam13checkTopologyERKNS_8polyMeshEbb(i1 zeroext %allTopology) #0 {
+entry:
+  br i1 undef, label %for.body, label %for.cond.cleanup
+
+; CHECK-LABEL: @_ZN4Foam13checkTopologyERKNS_8polyMeshEbb
+
+; CHECK: addis [[REG1:[0-9]+]], 2, .LC0@toc@ha
+; CHECK: std 2, 40(1)
+; CHECK: ld {{[0-9]+}}, .LC0@toc@l([[REG1]])
+; CHECK: {{mr|ld}} 2,
+; CHECK: mtctr
+; CHECK: bctrl
+; CHECK: ld 2, 40(1)
+
+; CHECK: addis [[REG1:[0-9]+]], 2, .LC0@toc@ha
+; CHECK: std 2, 40(1)
+; CHECK: ld {{[0-9]+}}, .LC0@toc@l([[REG1]])
+; CHECK: {{mr|ld}} 2,
+; CHECK: mtctr
+; CHECK: bctrl
+; CHECK: ld 2, 40(1)
+
+for.cond.cleanup:                                 ; preds = %entry
+  br i1 undef, label %if.then.i, label %if.else.i
+
+if.then.i:                                        ; preds = %for.cond.cleanup
+  br i1 undef, label %if.then.i1435, label %if.else.i1436
+
+if.else.i:                                        ; preds = %for.cond.cleanup
+  unreachable
+
+if.then.i1435:                                    ; preds = %if.then.i
+  br label %_ZN4Foam12returnReduceIiNS_5sumOpIiEEEET_RKS3_RKT0_ii.exit
+
+if.else.i1436:                                    ; preds = %if.then.i
+  br label %_ZN4Foam12returnReduceIiNS_5sumOpIiEEEET_RKS3_RKT0_ii.exit
+
+_ZN4Foam12returnReduceIiNS_5sumOpIiEEEET_RKS3_RKT0_ii.exit: ; preds = %if.else.i1436, %if.then.i1435
+  br i1 undef, label %for.body.i, label %_ZNK4Foam8ZoneMeshINS_8cellZoneENS_8polyMeshEE15checkDefinitionEb.exit
+
+for.body:                                         ; preds = %entry
+  unreachable
+
+for.body.i:                                       ; preds = %_ZN4Foam12returnReduceIiNS_5sumOpIiEEEET_RKS3_RKT0_ii.exit
+  unreachable
+
+_ZNK4Foam8ZoneMeshINS_8cellZoneENS_8polyMeshEE15checkDefinitionEb.exit: ; preds = %_ZN4Foam12returnReduceIiNS_5sumOpIiEEEET_RKS3_RKT0_ii.exit
+  br i1 undef, label %for.body.i1480, label %_ZNK4Foam8ZoneMeshINS_8faceZoneENS_8polyMeshEE15checkDefinitionEb.exit
+
+for.body.i1480:                                   ; preds = %_ZNK4Foam8ZoneMeshINS_8cellZoneENS_8polyMeshEE15checkDefinitionEb.exit
+  unreachable
+
+_ZNK4Foam8ZoneMeshINS_8faceZoneENS_8polyMeshEE15checkDefinitionEb.exit: ; preds = %_ZNK4Foam8ZoneMeshINS_8cellZoneENS_8polyMeshEE15checkDefinitionEb.exit
+  br i1 undef, label %for.body.i1504, label %_ZNK4Foam8ZoneMeshINS_9pointZoneENS_8polyMeshEE15checkDefinitionEb.exit
+
+for.body.i1504:                                   ; preds = %_ZNK4Foam8ZoneMeshINS_8faceZoneENS_8polyMeshEE15checkDefinitionEb.exit
+  unreachable
+
+_ZNK4Foam8ZoneMeshINS_9pointZoneENS_8polyMeshEE15checkDefinitionEb.exit: ; preds = %_ZNK4Foam8ZoneMeshINS_8faceZoneENS_8polyMeshEE15checkDefinitionEb.exit
+  invoke void @_ZN4Foam4word12stripInvalidEv()
+          to label %_ZN4Foam4wordC2EPKcb.exit unwind label %lpad.i
+
+lpad.i:                                           ; preds = %_ZNK4Foam8ZoneMeshINS_9pointZoneENS_8polyMeshEE15checkDefinitionEb.exit
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  resume { i8*, i32 } %0
+
+_ZN4Foam4wordC2EPKcb.exit:                        ; preds = %_ZNK4Foam8ZoneMeshINS_9pointZoneENS_8polyMeshEE15checkDefinitionEb.exit
+  invoke void @_ZN4Foam7cellSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE()
+          to label %invoke.cont59 unwind label %lpad
+
+invoke.cont59:                                    ; preds = %_ZN4Foam4wordC2EPKcb.exit
+  br i1 undef, label %_ZNSsD2Ev.exit, label %if.then.i.i, !prof !1
+
+if.then.i.i:                                      ; preds = %invoke.cont59
+  br i1 true, label %if.then.i.i.i1508, label %if.else.i.i.i
+
+if.then.i.i.i1508:                                ; preds = %if.then.i.i
+  br label %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i
+
+if.else.i.i.i:                                    ; preds = %if.then.i.i
+  br label %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i
+
+_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i: ; preds = %if.else.i.i.i, %if.then.i.i.i1508
+  br i1 undef, label %if.then4.i.i, label %_ZNSsD2Ev.exit
+
+if.then4.i.i:                                     ; preds = %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i
+  br label %_ZNSsD2Ev.exit
+
+_ZNSsD2Ev.exit:                                   ; preds = %if.then4.i.i, %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i, %invoke.cont59
+  br i1 undef, label %for.body70, label %for.cond.cleanup69
+
+for.cond.cleanup69:                               ; preds = %_ZNSsD2Ev.exit
+  br i1 undef, label %if.then121, label %if.else
+
+lpad:                                             ; preds = %_ZN4Foam4wordC2EPKcb.exit
+  %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  br i1 undef, label %_ZNSsD2Ev.exit1578, label %if.then.i.i1570, !prof !1
+
+if.then.i.i1570:                                  ; preds = %lpad
+  br i1 undef, label %if.then4.i.i1577, label %_ZNSsD2Ev.exit1578
+
+if.then4.i.i1577:                                 ; preds = %if.then.i.i1570
+  unreachable
+
+_ZNSsD2Ev.exit1578:                               ; preds = %if.then.i.i1570, %lpad
+  unreachable
+
+for.body70:                                       ; preds = %_ZNSsD2Ev.exit
+  unreachable
+
+if.then121:                                       ; preds = %for.cond.cleanup69
+  unreachable
+
+if.else:                                          ; preds = %for.cond.cleanup69
+  invoke void @_ZN4Foam4word12stripInvalidEv()
+          to label %_ZN4Foam4wordC2EPKcb.exit1701 unwind label %lpad.i1689
+
+lpad.i1689:                                       ; preds = %if.else
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  unreachable
+
+_ZN4Foam4wordC2EPKcb.exit1701:                    ; preds = %if.else
+  invoke void @_ZN4Foam8pointSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE()
+          to label %invoke.cont169 unwind label %lpad165
+
+invoke.cont169:                                   ; preds = %_ZN4Foam4wordC2EPKcb.exit1701
+  %call177 = invoke zeroext i1 undef(%"class.Foam::primitiveMesh.135"* undef, i1 zeroext true, %"class.Foam::HashSet.127"* undef)
+          to label %invoke.cont176 unwind label %lpad175
+
+invoke.cont176:                                   ; preds = %invoke.cont169
+  br i1 %call177, label %if.then178, label %if.end213
+
+if.then178:                                       ; preds = %invoke.cont176
+  unreachable
+
+lpad165:                                          ; preds = %_ZN4Foam4wordC2EPKcb.exit1701
+  %3 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  unreachable
+
+lpad175:                                          ; preds = %invoke.cont169
+  %4 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  invoke void @_ZN4Foam8pointSetD1Ev()
+          to label %eh.resume unwind label %terminate.lpad
+
+if.end213:                                        ; preds = %invoke.cont176
+  invoke void @_ZN4Foam4word12stripInvalidEv()
+          to label %_ZN4Foam4wordC2EPKcb.exit1777 unwind label %lpad.i1765
+
+lpad.i1765:                                       ; preds = %if.end213
+  %5 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  br i1 undef, label %eh.resume.i1776, label %if.then.i.i.i1767, !prof !1
+
+if.then.i.i.i1767:                                ; preds = %lpad.i1765
+  unreachable
+
+eh.resume.i1776:                                  ; preds = %lpad.i1765
+  resume { i8*, i32 } %5
+
+_ZN4Foam4wordC2EPKcb.exit1777:                    ; preds = %if.end213
+  invoke void @_ZN4Foam7faceSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE()
+          to label %invoke.cont221 unwind label %lpad217
+
+invoke.cont221:                                   ; preds = %_ZN4Foam4wordC2EPKcb.exit1777
+  br i1 undef, label %_ZNSsD2Ev.exit1792, label %if.then.i.i1784, !prof !1
+
+if.then.i.i1784:                                  ; preds = %invoke.cont221
+  br i1 undef, label %if.then4.i.i1791, label %_ZNSsD2Ev.exit1792
+
+if.then4.i.i1791:                                 ; preds = %if.then.i.i1784
+  br label %_ZNSsD2Ev.exit1792
+
+_ZNSsD2Ev.exit1792:                               ; preds = %if.then4.i.i1791, %if.then.i.i1784, %invoke.cont221
+  %call232 = invoke zeroext i1 undef(%"class.Foam::primitiveMesh.135"* undef, i1 zeroext true, %"class.Foam::HashSet.127"* undef)
+          to label %invoke.cont231 unwind label %lpad230
+
+invoke.cont231:                                   ; preds = %_ZNSsD2Ev.exit1792
+  invoke void @_ZN4Foam6reduceIiNS_5sumOpIiEEEEvRKNS_4ListINS_8UPstream11commsStructEEERT_RKT0_ii()
+          to label %invoke.cont243 unwind label %lpad230
+
+lpad217:                                          ; preds = %_ZN4Foam4wordC2EPKcb.exit1777
+  %6 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  br label %eh.resume
+
+lpad230:                                          ; preds = %invoke.cont231, %_ZNSsD2Ev.exit1792
+  %7 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  invoke void @_ZN4Foam7faceSetD1Ev()
+          to label %eh.resume unwind label %terminate.lpad
+
+invoke.cont243:                                   ; preds = %invoke.cont231
+  invoke void @_ZN4Foam4word12stripInvalidEv()
+          to label %_ZN4Foam4wordC2EPKcb.exit1862 unwind label %lpad.i1850
+
+lpad.i1850:                                       ; preds = %invoke.cont243
+  %8 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  unreachable
+
+_ZN4Foam4wordC2EPKcb.exit1862:                    ; preds = %invoke.cont243
+  invoke void @_ZN4Foam7faceSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE()
+          to label %invoke.cont280 unwind label %lpad276
+
+invoke.cont280:                                   ; preds = %_ZN4Foam4wordC2EPKcb.exit1862
+  br i1 undef, label %_ZNSsD2Ev.exit1877, label %if.then.i.i1869, !prof !1
+
+if.then.i.i1869:                                  ; preds = %invoke.cont280
+  unreachable
+
+_ZNSsD2Ev.exit1877:                               ; preds = %invoke.cont280
+  br i1 undef, label %if.then292, label %if.end328
+
+if.then292:                                       ; preds = %_ZNSsD2Ev.exit1877
+  unreachable
+
+lpad276:                                          ; preds = %_ZN4Foam4wordC2EPKcb.exit1862
+  %9 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  unreachable
+
+if.end328:                                        ; preds = %_ZNSsD2Ev.exit1877
+  br i1 %allTopology, label %if.then331, label %if.end660
+
+if.then331:                                       ; preds = %if.end328
+  unreachable
+
+if.end660:                                        ; preds = %if.end328
+  invoke void @_ZN4Foam13messageStreamcvRNS_8OSstreamEEv()
+          to label %invoke.cont668 unwind label %lpad663
+
+invoke.cont668:                                   ; preds = %if.end660
+  %call671 = invoke dereferenceable(56) %"class.Foam::Ostream.189"* @_ZN4FoamlsERNS_7OstreamEPKc()
+          to label %invoke.cont670 unwind label %lpad663
+
+invoke.cont670:                                   ; preds = %invoke.cont668
+  invoke void @_ZN4FoamlsERNS_7OstreamEi()
+          to label %invoke.cont674 unwind label %lpad663
+
+invoke.cont674:                                   ; preds = %invoke.cont670
+  %call677 = invoke dereferenceable(56) %"class.Foam::Ostream.189"* @_ZN4FoamlsERNS_7OstreamEPKc()
+          to label %invoke.cont676 unwind label %lpad663
+
+invoke.cont676:                                   ; preds = %invoke.cont674
+  invoke void undef(%"class.Foam::Ostream.189"* %call677)
+          to label %if.end878 unwind label %lpad663
+
+lpad663:                                          ; preds = %invoke.cont670, %if.end660, %invoke.cont668, %invoke.cont674, %invoke.cont676
+  %10 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  br i1 undef, label %_ZN4Foam4ListIiED2Ev.exit.i3073, label %delete.notnull.i.i3071
+
+if.end878:                                        ; preds = %invoke.cont676
+  br i1 undef, label %_ZN4Foam11regionSplitD2Ev.exit, label %delete.notnull.i.i3056
+
+delete.notnull.i.i3056:                           ; preds = %if.end878
+  unreachable
+
+_ZN4Foam11regionSplitD2Ev.exit:                   ; preds = %if.end878
+  br i1 undef, label %if.then883, label %if.else888
+
+if.then883:                                       ; preds = %_ZN4Foam11regionSplitD2Ev.exit
+  unreachable
+
+delete.notnull.i.i3071:                           ; preds = %lpad663
+  unreachable
+
+_ZN4Foam4ListIiED2Ev.exit.i3073:                  ; preds = %lpad663
+  invoke void @_ZN4Foam11regIOobjectD2Ev()
+          to label %eh.resume unwind label %terminate.lpad
+
+if.else888:                                       ; preds = %_ZN4Foam11regionSplitD2Ev.exit
+  invoke void @_ZN4Foam4word12stripInvalidEv()
+          to label %_ZN4Foam4wordC2EPKcb.exit3098 unwind label %lpad.i3086
+
+lpad.i3086:                                       ; preds = %if.else888
+  %11 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  unreachable
+
+_ZN4Foam4wordC2EPKcb.exit3098:                    ; preds = %if.else888
+  invoke void @_ZN4Foam8pointSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE()
+          to label %invoke.cont902 unwind label %lpad898
+
+invoke.cont902:                                   ; preds = %_ZN4Foam4wordC2EPKcb.exit3098
+  br i1 undef, label %_ZNSsD2Ev.exit3113, label %if.then.i.i3105, !prof !1
+
+if.then.i.i3105:                                  ; preds = %invoke.cont902
+  br i1 undef, label %if.then4.i.i3112, label %_ZNSsD2Ev.exit3113
+
+if.then4.i.i3112:                                 ; preds = %if.then.i.i3105
+  unreachable
+
+_ZNSsD2Ev.exit3113:                               ; preds = %if.then.i.i3105, %invoke.cont902
+  %call.i31163117 = invoke zeroext i32 undef(%"class.Foam::IOstream.8"* getelementptr inbounds (%"class.Foam::prefixOSstream.27", %"class.Foam::prefixOSstream.27"* @_ZN4Foam4PoutE, i64 0, i32 0, i32 0, i32 0))
+          to label %call.i3116.noexc unwind label %lpad905.loopexit.split-lp
+
+call.i3116.noexc:                                 ; preds = %_ZNSsD2Ev.exit3113
+  %call5.i3118 = invoke zeroext i32 null(%"class.Foam::IOstream.8"* getelementptr inbounds (%"class.Foam::prefixOSstream.27", %"class.Foam::prefixOSstream.27"* @_ZN4Foam4PoutE, i64 0, i32 0, i32 0, i32 0), i32 zeroext undef)
+          to label %invoke.cont906 unwind label %lpad905.loopexit.split-lp
+
+invoke.cont906:                                   ; preds = %call.i3116.noexc
+  unreachable
+
+lpad898:                                          ; preds = %_ZN4Foam4wordC2EPKcb.exit3098
+  %12 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  br i1 undef, label %_ZNSsD2Ev.exit3204, label %if.then.i.i3196, !prof !1
+
+if.then.i.i3196:                                  ; preds = %lpad898
+  unreachable
+
+_ZNSsD2Ev.exit3204:                               ; preds = %lpad898
+  unreachable
+
+lpad905.loopexit.split-lp:                        ; preds = %call.i3116.noexc, %_ZNSsD2Ev.exit3113
+  %lpad.loopexit.split-lp = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  invoke void @_ZN4Foam8pointSetD1Ev()
+          to label %eh.resume unwind label %terminate.lpad
+
+eh.resume:                                        ; preds = %_ZN4Foam4ListIiED2Ev.exit.i3073, %lpad230, %lpad175, %lpad905.loopexit.split-lp, %lpad217
+  resume { i8*, i32 } undef
+
+terminate.lpad:                                   ; preds = %_ZN4Foam4ListIiED2Ev.exit.i3073, %lpad230, %lpad175, %lpad905.loopexit.split-lp
+  %13 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          catch i8* null
+  unreachable
+}
+
+declare dereferenceable(56) %"class.Foam::Ostream.189"* @_ZN4FoamlsERNS_7OstreamEPKc() #0
+
+declare void @_ZN4Foam13messageStreamcvRNS_8OSstreamEEv() #0
+
+declare i32 @__gxx_personality_v0(...)
+
+declare void @_ZN4Foam7cellSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE() #0
+
+declare void @_ZN4FoamlsERNS_7OstreamEi() #0
+
+declare void @_ZN4Foam8pointSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE() #0
+
+declare void @_ZN4Foam8pointSetD1Ev() #0
+
+declare void @_ZN4Foam7faceSetC1ERKNS_8polyMeshERKNS_4wordEiNS_8IOobject11writeOptionE() #0
+
+declare void @_ZN4Foam7faceSetD1Ev() #0
+
+; Function Attrs: inlinehint
+declare void @_ZN4Foam4word12stripInvalidEv() #1 align 2
+
+declare void @_ZN4Foam11regIOobjectD2Ev() #0
+
+declare void @_ZN4Foam6reduceIiNS_5sumOpIiEEEEvRKNS_4ListINS_8UPstream11commsStructEEERT_RKT0_ii() #0
+
+attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="a2q" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { inlinehint "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="a2q" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"branch_weights", i32 64, i32 4}
diff --git a/test/CodeGen/PowerPC/f32-to-i64.ll b/test/CodeGen/PowerPC/f32-to-i64.ll
new file mode 100644
index 000000000000..c1381880b757
--- /dev/null
+++ b/test/CodeGen/PowerPC/f32-to-i64.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-m:e-p:32:32-i64:64-n32"
+target triple = "powerpc-unknown-unknown"
+
+; Function Attrs: nounwind
+define i64 @testullf(float %arg) #0 {
+entry:
+  %arg.addr = alloca float, align 4
+  store float %arg, float* %arg.addr, align 4
+  %0 = load float, float* %arg.addr, align 4
+  %conv = fptoui float %0 to i64
+  ret i64 %conv
+
+; CHECK-LABEL: @testullf
+; CHECK: fctiduz [[REG1:[0-9]+]], 1
+; CHECK: stfd [[REG1]], [[OFF:[0-9]+]](1)
+; CHECK-DAG: lwz 3, [[OFF]](1)
+; CHECK-DAG: lwz 4, {{[0-9]+}}(1)
+; CHECK: blr
+}
+
+attributes #0 = { nounwind "target-cpu"="a2" }
+
diff --git a/test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll b/test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll
index 7bdda0494b8f..3e0e5250d2fb 100644
--- a/test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll
+++ b/test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
 
 %struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] }
 %struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] }
@@ -11,9 +11,9 @@ define i32* @t1() nounwind {
 entry:
 ; ELF64: t1
   %addr = alloca i32*, align 4
-  store i32* getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]]* @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), i32** %addr, align 4
+  store i32* getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]], [2 x [2 x [2 x [2 x [2 x i32]]]]]* @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), i32** %addr, align 4
 ; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 124
-  %0 = load i32** %addr, align 4
+  %0 = load i32*, i32** %addr, align 4
   ret i32* %0
 }
 
@@ -21,9 +21,9 @@ define i32* @t2() nounwind {
 entry:
 ; ELF64: t2
   %addr = alloca i32*, align 4
-  store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4
+  store i32* getelementptr inbounds ([3 x [3 x %struct.A]], [3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4
 ; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 1148
-  %0 = load i32** %addr, align 4
+  %0 = load i32*, i32** %addr, align 4
   ret i32* %0
 }
 
@@ -31,9 +31,9 @@ define i32* @t3() nounwind {
 entry:
 ; ELF64: t3
   %addr = alloca i32*, align 4
-  store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), i32** %addr, align 4
+  store i32* getelementptr inbounds ([3 x [3 x %struct.A]], [3 x [3 x %struct.A]]* @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), i32** %addr, align 4
 ; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 140
-  %0 = load i32** %addr, align 4
+  %0 = load i32*, i32** %addr, align 4
   ret i32* %0
 }
 
@@ -41,8 +41,8 @@ define i32* @t4() nounwind {
 entry:
 ; ELF64: t4
   %addr = alloca i32*, align 4
-  store i32* getelementptr inbounds ([2 x [2 x [2 x %struct.B]]]* @B, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 3, i32 1, i32 2, i32 1), i32** %addr, align 4
+  store i32* getelementptr inbounds ([2 x [2 x [2 x %struct.B]]], [2 x [2 x [2 x %struct.B]]]* @B, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 3, i32 1, i32 2, i32 1), i32** %addr, align 4
 ; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 1284
-  %0 = load i32** %addr, align 4
+  %0 = load i32*, i32** %addr, align 4
   ret i32* %0
 }
diff --git a/test/CodeGen/PowerPC/fast-isel-binary.ll b/test/CodeGen/PowerPC/fast-isel-binary.ll
index 43a6cd085055..2f1513f8aa11 100644
--- a/test/CodeGen/PowerPC/fast-isel-binary.ll
+++ b/test/CodeGen/PowerPC/fast-isel-binary.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
 
 ; Test add with non-legal types
 
diff --git a/test/CodeGen/PowerPC/fast-isel-br-const.ll b/test/CodeGen/PowerPC/fast-isel-br-const.ll
index 2cfb8a225745..6be7fbf9e02f 100644
--- a/test/CodeGen/PowerPC/fast-isel-br-const.ll
+++ b/test/CodeGen/PowerPC/fast-isel-br-const.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
 
 define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp {
 entry:
diff --git a/test/CodeGen/PowerPC/fast-isel-call.ll b/test/CodeGen/PowerPC/fast-isel-call.ll
index b2cc75e26114..64d8f6e79195 100644
--- a/test/CodeGen/PowerPC/fast-isel-call.ll
+++ b/test/CodeGen/PowerPC/fast-isel-call.ll
@@ -1,8 +1,8 @@
 ; FIXME: FastISel currently returns false if it hits code that uses VSX
-; registers and with -fast-isel-abort turned on the test case will then fail.
+; registers and with -fast-isel-abort=1 turned on the test case will then fail.
 ; When fastisel better supports VSX fix up this test case.
 ;
-; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
 
 define i32 @t1(i8 signext %a) nounwind {
   %1 = sext i8 %a to i32
@@ -85,7 +85,7 @@ define i32 @bar0(i32 %i) nounwind {
 ;define void @foo3() uwtable {
 ;  %fptr = alloca i32 (i32)*, align 8
 ;  store i32 (i32)* @bar0, i32 (i32)** %fptr, align 8
-;  %1 = load i32 (i32)** %fptr, align 8
+;  %1 = load i32 (i32)*, i32 (i32)** %fptr, align 8
 ;  %call = call i32 %1(i32 0)
 ;  ret void
 ;}
diff --git a/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll b/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
index c1f6b6327a44..5a9d15868b6b 100644
--- a/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
+++ b/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
@@ -1,8 +1,8 @@
 ; FIXME: FastISel currently returns false if it hits code that uses VSX
-; registers and with -fast-isel-abort turned on the test case will then fail.
+; registers and with -fast-isel-abort=1 turned on the test case will then fail.
 ; When fastisel better supports VSX fix up this test case.
 ;
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
 define void @t1a(float %a) uwtable ssp {
 entry:
 ; ELF64: t1a
@@ -201,7 +201,7 @@ define void @t12(i8 %a) uwtable ssp {
 entry:
 ; ELF64: t12
   %cmp = icmp ugt i8 %a, -113
-; ELF64: rlwinm
+; ELF64: clrlwi
 ; ELF64: cmplwi
   br i1 %cmp, label %if.then, label %if.end
 
diff --git a/test/CodeGen/PowerPC/fast-isel-const.ll b/test/CodeGen/PowerPC/fast-isel-const.ll
index 1057d0a0ce2b..a751a2be6c69 100644
--- a/test/CodeGen/PowerPC/fast-isel-const.ll
+++ b/test/CodeGen/PowerPC/fast-isel-const.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
 
 define zeroext i1 @testi1(i8 %in) nounwind uwtable ssp {
 entry:
diff --git a/test/CodeGen/PowerPC/fast-isel-conversion-p5.ll b/test/CodeGen/PowerPC/fast-isel-conversion-p5.ll
index ac41e8c27700..cfb934c6ab02 100644
--- a/test/CodeGen/PowerPC/fast-isel-conversion-p5.ll
+++ b/test/CodeGen/PowerPC/fast-isel-conversion-p5.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr5 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr5 | FileCheck %s --check-prefix=ELF64
 
 ; Test sitofp
 
diff --git a/test/CodeGen/PowerPC/fast-isel-conversion.ll b/test/CodeGen/PowerPC/fast-isel-conversion.ll
index b0e29c1274a2..f7557d456858 100644
--- a/test/CodeGen/PowerPC/fast-isel-conversion.ll
+++ b/test/CodeGen/PowerPC/fast-isel-conversion.ll
@@ -1,12 +1,12 @@
 ; FIXME: FastISel currently returns false if it hits code that uses VSX
-; registers and with -fast-isel-abort turned on the test case will then fail.
+; registers and with -fast-isel-abort=1 turned on the test case will then fail.
 ; When fastisel better supports VSX fix up this test case.
 ;
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s --check-prefix=ELF64LE
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s --check-prefix=ELF64LE
 ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970
 
-;; Tests for 970 don't use -fast-isel-abort because we intentionally punt
+;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt
 ;; to SelectionDAG in some cases.
 
 ; Test sitofp
@@ -253,7 +253,7 @@ entry:
 ; ELF64LE: std
 ; ELF64LE: lfd
 ; ELF64LE: fcfidus
-; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31
+; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
@@ -277,7 +277,7 @@ entry:
 ; ELF64LE: std
 ; ELF64LE: lfd
 ; ELF64LE: fcfidus
-; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
+; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
@@ -342,7 +342,7 @@ entry:
 ; ELF64LE: std
 ; ELF64LE: lfd
 ; ELF64LE: fcfidu
-; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31
+; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
@@ -365,7 +365,7 @@ entry:
 ; ELF64LE: std
 ; ELF64LE: lfd
 ; ELF64LE: fcfidu
-; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
+; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
diff --git a/test/CodeGen/PowerPC/fast-isel-crash.ll b/test/CodeGen/PowerPC/fast-isel-crash.ll
index 1813fc96acee..55e87effcd82 100644
--- a/test/CodeGen/PowerPC/fast-isel-crash.ll
+++ b/test/CodeGen/PowerPC/fast-isel-crash.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7
 
 ; Ensure this doesn't crash.
 
diff --git a/test/CodeGen/PowerPC/fast-isel-ext.ll b/test/CodeGen/PowerPC/fast-isel-ext.ll
index 753305a68dda..6fd3b4035122 100644
--- a/test/CodeGen/PowerPC/fast-isel-ext.ll
+++ b/test/CodeGen/PowerPC/fast-isel-ext.ll
@@ -1,18 +1,18 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
 
 ; zext
 
 define i32 @zext_8_32(i8 %a) nounwind ssp {
 ; ELF64: zext_8_32
   %r = zext i8 %a to i32
-; ELF64: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
+; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
   ret i32 %r
 }
 
 define i32 @zext_16_32(i16 %a) nounwind ssp {
 ; ELF64: zext_16_32
   %r = zext i16 %a to i32
-; ELF64: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31
+; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
   ret i32 %r
 }
 
diff --git a/test/CodeGen/PowerPC/fast-isel-fold.ll b/test/CodeGen/PowerPC/fast-isel-fold.ll
index 4de345f309af..e56101a28e2b 100644
--- a/test/CodeGen/PowerPC/fast-isel-fold.ll
+++ b/test/CodeGen/PowerPC/fast-isel-fold.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
 
 @a = global i8 1, align 1
 @b = global i16 2, align 2
@@ -6,7 +6,7 @@
 
 define void @t1() nounwind uwtable ssp {
 ; ELF64: t1
-  %1 = load i8* @a, align 1
+  %1 = load i8, i8* @a, align 1
   call void @foo1(i8 zeroext %1)
 ; ELF64: lbz
 ; ELF64-NOT: rldicl
@@ -16,7 +16,7 @@ define void @t1() nounwind uwtable ssp {
 
 define void @t2() nounwind uwtable ssp {
 ; ELF64: t2
-  %1 = load i16* @b, align 2
+  %1 = load i16, i16* @b, align 2
   call void @foo2(i16 zeroext %1)
 ; ELF64: lhz
 ; ELF64-NOT: rldicl
@@ -26,7 +26,7 @@ define void @t2() nounwind uwtable ssp {
 
 define void @t2a() nounwind uwtable ssp {
 ; ELF64: t2a
-  %1 = load i32* @c, align 4
+  %1 = load i32, i32* @c, align 4
   call void @foo3(i32 zeroext %1)
 ; ELF64: lwz
 ; ELF64-NOT: rldicl
@@ -40,7 +40,7 @@ declare void @foo3(i32 zeroext)
 
 define i32 @t3() nounwind uwtable ssp {
 ; ELF64: t3
-  %1 = load i8* @a, align 1
+  %1 = load i8, i8* @a, align 1
   %2 = zext i8 %1 to i32
 ; ELF64: lbz
 ; ELF64-NOT: rlwinm
@@ -49,7 +49,7 @@ define i32 @t3() nounwind uwtable ssp {
 
 define i32 @t4() nounwind uwtable ssp {
 ; ELF64: t4
-  %1 = load i16* @b, align 2
+  %1 = load i16, i16* @b, align 2
   %2 = zext i16 %1 to i32
 ; ELF64: lhz
 ; ELF64-NOT: rlwinm
@@ -58,7 +58,7 @@ define i32 @t4() nounwind uwtable ssp {
 
 define i32 @t5() nounwind uwtable ssp {
 ; ELF64: t5
-  %1 = load i16* @b, align 2
+  %1 = load i16, i16* @b, align 2
   %2 = sext i16 %1 to i32
 ; ELF64: lha
 ; ELF64-NOT: rlwinm
@@ -67,7 +67,7 @@ define i32 @t5() nounwind uwtable ssp {
 
 define i32 @t6() nounwind uwtable ssp {
 ; ELF64: t6
-  %1 = load i8* @a, align 2
+  %1 = load i8, i8* @a, align 2
   %2 = sext i8 %1 to i32
 ; ELF64: lbz
 ; ELF64-NOT: rlwinm
@@ -76,7 +76,7 @@ define i32 @t6() nounwind uwtable ssp {
 
 define i64 @t7() nounwind uwtable ssp {
 ; ELF64: t7
-  %1 = load i8* @a, align 1
+  %1 = load i8, i8* @a, align 1
   %2 = zext i8 %1 to i64
 ; ELF64: lbz
 ; ELF64-NOT: rldicl
@@ -85,7 +85,7 @@ define i64 @t7() nounwind uwtable ssp {
 
 define i64 @t8() nounwind uwtable ssp {
 ; ELF64: t8
-  %1 = load i16* @b, align 2
+  %1 = load i16, i16* @b, align 2
   %2 = zext i16 %1 to i64
 ; ELF64: lhz
 ; ELF64-NOT: rldicl
@@ -94,7 +94,7 @@ define i64 @t8() nounwind uwtable ssp {
 
 define i64 @t9() nounwind uwtable ssp {
 ; ELF64: t9
-  %1 = load i16* @b, align 2
+  %1 = load i16, i16* @b, align 2
   %2 = sext i16 %1 to i64
 ; ELF64: lha
 ; ELF64-NOT: extsh
@@ -103,7 +103,7 @@ define i64 @t9() nounwind uwtable ssp {
 
 define i64 @t10() nounwind uwtable ssp {
 ; ELF64: t10
-  %1 = load i8* @a, align 2
+  %1 = load i8, i8* @a, align 2
   %2 = sext i8 %1 to i64
 ; ELF64: lbz
 ; ELF64: extsb
@@ -112,7 +112,7 @@ define i64 @t10() nounwind uwtable ssp {
 
 define i64 @t11() nounwind uwtable ssp {
 ; ELF64: t11
-  %1 = load i32* @c, align 4
+  %1 = load i32, i32* @c, align 4
   %2 = zext i32 %1 to i64
 ; ELF64: lwz
 ; ELF64-NOT: rldicl
@@ -121,7 +121,7 @@ define i64 @t11() nounwind uwtable ssp {
 
 define i64 @t12() nounwind uwtable ssp {
 ; ELF64: t12
-  %1 = load i32* @c, align 4
+  %1 = load i32, i32* @c, align 4
   %2 = sext i32 %1 to i64
 ; ELF64: lwa
 ; ELF64-NOT: extsw
diff --git a/test/CodeGen/PowerPC/fast-isel-icmp-split.ll b/test/CodeGen/PowerPC/fast-isel-icmp-split.ll
new file mode 100644
index 000000000000..459616eb9698
--- /dev/null
+++ b/test/CodeGen/PowerPC/fast-isel-icmp-split.ll
@@ -0,0 +1,72 @@
+; RUN: llc -O0 -relocation-model=pic < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+%"class.std::__1::__tree_node.130.151" = type { %"class.std::__1::__tree_node_base.base.128.149", %"class.boost::serialization::extended_type_info.129.150"* }
+%"class.std::__1::__tree_node_base.base.128.149" = type <{ %"class.std::__1::__tree_end_node.127.148", %"class.std::__1::__tree_node_base.126.147"*, %"class.std::__1::__tree_node_base.126.147"*, i8 }>
+%"class.std::__1::__tree_end_node.127.148" = type { %"class.std::__1::__tree_node_base.126.147"* }
+%"class.std::__1::__tree_node_base.126.147" = type <{ %"class.std::__1::__tree_end_node.127.148", %"class.std::__1::__tree_node_base.126.147"*, %"class.std::__1::__tree_node_base.126.147"*, i8, [7 x i8] }>
+%"class.boost::serialization::extended_type_info.129.150" = type { i32 (...)**, i32, i8* }
+
+; Function Attrs: noinline
+define void @_ZN5boost13serialization18extended_type_info4findEPKc() #0 align 2 {
+entry:
+  br i1 undef, label %cond.true, label %cond.false
+
+; CHECK: @_ZN5boost13serialization18extended_type_info4findEPKc
+
+cond.true:                                        ; preds = %entry
+  br label %cond.end
+
+cond.false:                                       ; preds = %entry
+  unreachable
+                                                  ; No predecessors!
+  br label %cond.end
+
+cond.end:                                         ; preds = %0, %cond.true
+  invoke void @_ZNKSt3__16__treeIPKN5boost13serialization18extended_type_infoENS2_6detail11key_compareENS_9allocatorIS5_EEE4findIS5_EENS_21__tree_const_iteratorIS5_PNS_11__tree_nodeIS5_PvEElEERKT_()
+          to label %_ZNKSt3__18multisetIPKN5boost13serialization18extended_type_infoENS2_6detail11key_compareENS_9allocatorIS5_EEE4findERKS5_.exit unwind label %lpad
+
+_ZNKSt3__18multisetIPKN5boost13serialization18extended_type_infoENS2_6detail11key_compareENS_9allocatorIS5_EEE4findERKS5_.exit: ; preds = %cond.end
+  br label %invoke.cont
+
+invoke.cont:                                      ; preds = %_ZNKSt3__18multisetIPKN5boost13serialization18extended_type_infoENS2_6detail11key_compareENS_9allocatorIS5_EEE4findERKS5_.exit
+  %1 = load %"class.std::__1::__tree_node.130.151"*, %"class.std::__1::__tree_node.130.151"** undef, align 8
+  %cmp.i = icmp eq %"class.std::__1::__tree_node.130.151"* undef, %1
+  br label %invoke.cont.2
+
+invoke.cont.2:                                    ; preds = %invoke.cont
+  br i1 %cmp.i, label %if.then, label %if.end
+
+if.then:                                          ; preds = %invoke.cont.2
+  br label %cleanup
+
+lpad:                                             ; preds = %cond.end
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  br label %eh.resume
+
+if.end:                                           ; preds = %invoke.cont.2
+  br label %invoke.cont.4
+
+invoke.cont.4:                                    ; preds = %if.end
+  br label %cleanup
+
+cleanup:                                          ; preds = %invoke.cont.4, %if.then
+  ret void
+
+eh.resume:                                        ; preds = %lpad
+  resume { i8*, i32 } undef
+}
+
+declare i32 @__gxx_personality_v0(...)
+
+; Function Attrs: noinline
+declare void @_ZNKSt3__16__treeIPKN5boost13serialization18extended_type_infoENS2_6detail11key_compareENS_9allocatorIS5_EEE4findIS5_EENS_21__tree_const_iteratorIS5_PNS_11__tree_nodeIS5_PvEElEERKT_() #0 align 2
+
+attributes #0 = { noinline "target-cpu"="a2q" }
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+
diff --git a/test/CodeGen/PowerPC/fast-isel-indirectbr.ll b/test/CodeGen/PowerPC/fast-isel-indirectbr.ll
index 88ccf918ae96..b5477134c517 100644
--- a/test/CodeGen/PowerPC/fast-isel-indirectbr.ll
+++ b/test/CodeGen/PowerPC/fast-isel-indirectbr.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
 
 define void @t1(i8* %x) {
 entry:
diff --git a/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll b/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll
new file mode 100644
index 000000000000..8a873daa6c7a
--- /dev/null
+++ b/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -O0 -fast-isel -mattr=+vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64VSX
+
+;; The semantics of VSX stores for when R0 is used is different depending on
+;; whether it is used as base or offset. If used as base, the effective
+;; address computation will use zero regardless of the content of R0. If used as
+;; an offset the content will be used in the effective address. We observed that
+;; for some constructors, the initialization values were being stored without
+;; an offset register being specified which was causing R0 to be used as offset
+;; in regions where it contained the value in the link register. This test
+;; verifies that R0 is used as base in these situations.
+
+%SomeStruct = type { double }
+
+; ELF64VSX-LABEL: SomeStructCtor
+define linkonce_odr void @SomeStructCtor(%SomeStruct* %this, double %V) unnamed_addr align 2 {
+entry:
+  %this.addr = alloca %SomeStruct*, align 8
+  %V.addr = alloca double, align 8
+  store %SomeStruct* %this, %SomeStruct** %this.addr, align 8
+; ELF64VSX: stxsdx {{[0-9][0-9]?}}, 0, {{[1-9][0-9]?}}
+  store double %V, double* %V.addr, align 8
+  %this1 = load %SomeStruct*, %SomeStruct** %this.addr
+  %Val = getelementptr inbounds %SomeStruct, %SomeStruct* %this1, i32 0, i32 0
+; ELF64VSX: stxsdx {{[0-9][0-9]?}}, 0, {{[1-9][0-9]?}}
+  %0 = load double, double* %V.addr, align 8
+  store double %0, double* %Val, align 8
+  ret void
+ }
diff --git a/test/CodeGen/PowerPC/fast-isel-load-store.ll b/test/CodeGen/PowerPC/fast-isel-load-store.ll
index ef702e21d6a1..f6a55f06b2cb 100644
--- a/test/CodeGen/PowerPC/fast-isel-load-store.ll
+++ b/test/CodeGen/PowerPC/fast-isel-load-store.ll
@@ -1,8 +1,8 @@
 ; FIXME: FastISel currently returns false if it hits code that uses VSX
-; registers and with -fast-isel-abort turned on the test case will then fail.
+; registers and with -fast-isel-abort=1 turned on the test case will then fail.
 ; When fastisel better supports VSX fix up this test case.
 ;
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel -fast-isel-abort -mattr=-vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel -fast-isel-abort=1 -mattr=-vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
 
 ; This test verifies that load/store instructions are properly generated,
 ; and that they pass MI verification.
@@ -26,7 +26,7 @@
 
 define i8 @t1() nounwind uwtable ssp {
 ; ELF64: t1
-  %1 = load i8* @a, align 1
+  %1 = load i8, i8* @a, align 1
 ; ELF64: lbz
   %2 = add nsw i8 %1, 1
 ; ELF64: addi
@@ -35,7 +35,7 @@ define i8 @t1() nounwind uwtable ssp {
 
 define i16 @t2() nounwind uwtable ssp {
 ; ELF64: t2
-  %1 = load i16* @b, align 2
+  %1 = load i16, i16* @b, align 2
 ; ELF64: lhz
   %2 = add nsw i16 %1, 1
 ; ELF64: addi
@@ -44,7 +44,7 @@ define i16 @t2() nounwind uwtable ssp {
 
 define i32 @t3() nounwind uwtable ssp {
 ; ELF64: t3
-  %1 = load i32* @c, align 4
+  %1 = load i32, i32* @c, align 4
 ; ELF64: lwz
   %2 = add nsw i32 %1, 1
 ; ELF64: addi
@@ -53,7 +53,7 @@ define i32 @t3() nounwind uwtable ssp {
 
 define i64 @t4() nounwind uwtable ssp {
 ; ELF64: t4
-  %1 = load i64* @d, align 4
+  %1 = load i64, i64* @d, align 4
 ; ELF64: ld
   %2 = add nsw i64 %1, 1
 ; ELF64: addi
@@ -62,7 +62,7 @@ define i64 @t4() nounwind uwtable ssp {
 
 define float @t5() nounwind uwtable ssp {
 ; ELF64: t5
-  %1 = load float* @e, align 4
+  %1 = load float, float* @e, align 4
 ; ELF64: lfs
   %2 = fadd float %1, 1.0
 ; ELF64: fadds
@@ -71,7 +71,7 @@ define float @t5() nounwind uwtable ssp {
 
 define double @t6() nounwind uwtable ssp {
 ; ELF64: t6
-  %1 = load double* @f, align 8
+  %1 = load double, double* @f, align 8
 ; ELF64: lfd
   %2 = fadd double %1, 1.0
 ; ELF64: fadd
@@ -145,7 +145,7 @@ define void @t12(double %v) nounwind uwtable ssp {
 ;; lwa requires an offset divisible by 4, so we need lwax here.
 define i64 @t13() nounwind uwtable ssp {
 ; ELF64: t13
-  %1 = load i32* getelementptr inbounds (%struct.s* @g, i32 0, i32 1), align 1
+  %1 = load i32, i32* getelementptr inbounds (%struct.s, %struct.s* @g, i32 0, i32 1), align 1
   %2 = sext i32 %1 to i64
 ; ELF64: li
 ; ELF64: lwax
@@ -157,7 +157,7 @@ define i64 @t13() nounwind uwtable ssp {
 ;; ld requires an offset divisible by 4, so we need ldx here.
 define i64 @t14() nounwind uwtable ssp {
 ; ELF64: t14
-  %1 = load i64* getelementptr inbounds (%struct.t* @h, i32 0, i32 1), align 1
+  %1 = load i64, i64* getelementptr inbounds (%struct.t, %struct.t* @h, i32 0, i32 1), align 1
 ; ELF64: li
 ; ELF64: ldx
   %2 = add nsw i64 %1, 1
@@ -169,7 +169,7 @@ define i64 @t14() nounwind uwtable ssp {
 define void @t15(i64 %v) nounwind uwtable ssp {
 ; ELF64: t15
   %1 = add nsw i64 %v, 1
-  store i64 %1, i64* getelementptr inbounds (%struct.t* @h, i32 0, i32 1), align 1
+  store i64 %1, i64* getelementptr inbounds (%struct.t, %struct.t* @h, i32 0, i32 1), align 1
 ; ELF64: addis
 ; ELF64: addi
 ; ELF64: addi
@@ -181,7 +181,7 @@ define void @t15(i64 %v) nounwind uwtable ssp {
 ;; ld requires an offset that fits in 16 bits, so we need ldx here.
 define i64 @t16() nounwind uwtable ssp {
 ; ELF64: t16
-  %1 = load i64* getelementptr inbounds ([8192 x i64]* @i, i32 0, i64 5000), align 8
+  %1 = load i64, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8
 ; ELF64: lis
 ; ELF64: ori
 ; ELF64: ldx
@@ -194,7 +194,7 @@ define i64 @t16() nounwind uwtable ssp {
 define void @t17(i64 %v) nounwind uwtable ssp {
 ; ELF64: t17
   %1 = add nsw i64 %v, 1
-  store i64 %1, i64* getelementptr inbounds ([8192 x i64]* @i, i32 0, i64 5000), align 8
+  store i64 %1, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8
 ; ELF64: addis
 ; ELF64: ld
 ; ELF64: addi
diff --git a/test/CodeGen/PowerPC/fast-isel-redefinition.ll b/test/CodeGen/PowerPC/fast-isel-redefinition.ll
index 72422bda4433..60706a6e1438 100644
--- a/test/CodeGen/PowerPC/fast-isel-redefinition.ll
+++ b/test/CodeGen/PowerPC/fast-isel-redefinition.ll
@@ -1,10 +1,10 @@
-; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -optimize-regalloc -regalloc=basic -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
+; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -optimize-regalloc -regalloc=basic -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
 ; This isn't exactly a useful set of command-line options, but check that it
 ; doesn't crash.  (It crashed formerly on ARM, and proved useful in
 ; discovering a bug on PowerPC as well.)
 
 define i32 @f(i32* %x) nounwind ssp {
-  %y = getelementptr inbounds i32* %x, i32 5000
-  %tmp103 = load i32* %y, align 4
+  %y = getelementptr inbounds i32, i32* %x, i32 5000
+  %tmp103 = load i32, i32* %y, align 4
   ret i32 %tmp103
 }
diff --git a/test/CodeGen/PowerPC/fast-isel-ret.ll b/test/CodeGen/PowerPC/fast-isel-ret.ll
index ae34fbf7bfe1..1e4566d94dfd 100644
--- a/test/CodeGen/PowerPC/fast-isel-ret.ll
+++ b/test/CodeGen/PowerPC/fast-isel-ret.ll
@@ -1,8 +1,8 @@
 ; FIXME: FastISel currently returns false if it hits code that uses VSX
-; registers and with -fast-isel-abort turned on the test case will then fail.
+; registers and with -fast-isel-abort=1 turned on the test case will then fail.
 ; When fastisel better supports VSX fix up this test case.
 ;
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
 
 define zeroext i1 @rettrue() nounwind uwtable ssp {
 entry:
diff --git a/test/CodeGen/PowerPC/fast-isel-shifter.ll b/test/CodeGen/PowerPC/fast-isel-shifter.ll
index 198bfbecda63..c18f659dde13 100644
--- a/test/CodeGen/PowerPC/fast-isel-shifter.ll
+++ b/test/CodeGen/PowerPC/fast-isel-shifter.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
 
 define i32 @shl() nounwind ssp {
 entry:
diff --git a/test/CodeGen/PowerPC/fastisel-gep-promote-before-add.ll b/test/CodeGen/PowerPC/fastisel-gep-promote-before-add.ll
index 4bcacf009746..96cf67c869f9 100644
--- a/test/CodeGen/PowerPC/fastisel-gep-promote-before-add.ll
+++ b/test/CodeGen/PowerPC/fastisel-gep-promote-before-add.ll
@@ -6,12 +6,12 @@ define zeroext i8 @gep_promotion(i8* %ptr) nounwind uwtable ssp {
 entry:
   %ptr.addr = alloca i8*, align 8
   %add = add i8 64, 64 ; 0x40 + 0x40
-  %0 = load i8** %ptr.addr, align 8
+  %0 = load i8*, i8** %ptr.addr, align 8
 
   ; CHECK-LABEL: gep_promotion:
   ; CHECK: lbz {{[0-9]+}}, 0({{.*}})
-  %arrayidx = getelementptr inbounds i8* %0, i8 %add
+  %arrayidx = getelementptr inbounds i8, i8* %0, i8 %add
 
-  %1 = load i8* %arrayidx, align 1
+  %1 = load i8, i8* %arrayidx, align 1
   ret i8 %1
 }
diff --git a/test/CodeGen/PowerPC/floatPSA.ll b/test/CodeGen/PowerPC/floatPSA.ll
index f14c73630a6f..cff95d591c9a 100644
--- a/test/CodeGen/PowerPC/floatPSA.ll
+++ b/test/CodeGen/PowerPC/floatPSA.ll
@@ -37,7 +37,7 @@ entry:
   store float %l, float* %l.addr, align 4
   store float %m, float* %m.addr, align 4
   store float %n, float* %n.addr, align 4
-  %0 = load float* %n.addr, align 4
+  %0 = load float, float* %n.addr, align 4
   ret float %0
 }
 
@@ -73,20 +73,20 @@ entry:
   store float 1.200000e+01, float* %l, align 4
   store float 1.300000e+01, float* %m, align 4
   store float 1.400000e+01, float* %n, align 4
-  %0 = load float* %a, align 4
-  %1 = load float* %b, align 4
-  %2 = load float* %c, align 4
-  %3 = load float* %d, align 4
-  %4 = load float* %e, align 4
-  %5 = load float* %f, align 4
-  %6 = load float* %g, align 4
-  %7 = load float* %h, align 4
-  %8 = load float* %i, align 4
-  %9 = load float* %j, align 4
-  %10 = load float* %k, align 4
-  %11 = load float* %l, align 4
-  %12 = load float* %m, align 4
-  %13 = load float* %n, align 4
+  %0 = load float, float* %a, align 4
+  %1 = load float, float* %b, align 4
+  %2 = load float, float* %c, align 4
+  %3 = load float, float* %d, align 4
+  %4 = load float, float* %e, align 4
+  %5 = load float, float* %f, align 4
+  %6 = load float, float* %g, align 4
+  %7 = load float, float* %h, align 4
+  %8 = load float, float* %i, align 4
+  %9 = load float, float* %j, align 4
+  %10 = load float, float* %k, align 4
+  %11 = load float, float* %l, align 4
+  %12 = load float, float* %m, align 4
+  %13 = load float, float* %n, align 4
   %call = call float @bar(float %0, float %1, float %2, float %3, float %4, float %5, float %6, float %7, float %8, float %9, float %10, float %11, float %12, float %13)
   ret float %call
 }
diff --git a/test/CodeGen/PowerPC/flt-preinc.ll b/test/CodeGen/PowerPC/flt-preinc.ll
new file mode 100644
index 000000000000..c0e3d3a21e19
--- /dev/null
+++ b/test/CodeGen/PowerPC/flt-preinc.ll
@@ -0,0 +1,40 @@
+; RUN: llc -mcpu=ppc64 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind readonly
+define float @tf(float* nocapture readonly %i, i32 signext %o) #0 {
+entry:
+  %idx.ext = sext i32 %o to i64
+  %add.ptr = getelementptr inbounds float, float* %i, i64 %idx.ext
+  %0 = load float, float* %add.ptr, align 4
+  %add.ptr.sum = add nsw i64 %idx.ext, 1
+  %add.ptr3 = getelementptr inbounds float, float* %i, i64 %add.ptr.sum
+  %1 = load float, float* %add.ptr3, align 4
+  %add = fadd float %0, %1
+  ret float %add
+
+; CHECK-LABEL: @tf
+; CHECK: lfsux
+; CHECK: blr
+}
+
+; Function Attrs: nounwind readonly
+define double @td(double* nocapture readonly %i, i32 signext %o) #0 {
+entry:
+  %idx.ext = sext i32 %o to i64
+  %add.ptr = getelementptr inbounds double, double* %i, i64 %idx.ext
+  %0 = load double, double* %add.ptr, align 8
+  %add.ptr.sum = add nsw i64 %idx.ext, 1
+  %add.ptr3 = getelementptr inbounds double, double* %i, i64 %add.ptr.sum
+  %1 = load double, double* %add.ptr3, align 8
+  %add = fadd double %0, %1
+  ret double %add
+
+; CHECK-LABEL: @td
+; CHECK: lfdux
+; CHECK: blr
+}
+
+attributes #0 = { nounwind readonly }
+
diff --git a/test/CodeGen/PowerPC/fma-assoc.ll b/test/CodeGen/PowerPC/fma-assoc.ll
index dc1316e5e24f..3044dd09128c 100644
--- a/test/CodeGen/PowerPC/fma-assoc.ll
+++ b/test/CodeGen/PowerPC/fma-assoc.ll
@@ -3,11 +3,11 @@
 
 define double @test_FMADD_ASSOC1(double %A, double %B, double %C,
                                  double %D, double %E) {
-	%F = fmul double %A, %B         ; <double> [#uses=1]
-	%G = fmul double %C, %D         ; <double> [#uses=1]
-	%H = fadd double %F, %G         ; <double> [#uses=1]
-	%I = fadd double %H, %E         ; <double> [#uses=1]
-	ret double %I
+  %F = fmul double %A, %B         ; <double> [#uses=1]
+  %G = fmul double %C, %D         ; <double> [#uses=1]
+  %H = fadd double %F, %G         ; <double> [#uses=1]
+  %I = fadd double %H, %E         ; <double> [#uses=1]
+  ret double %I
 ; CHECK-LABEL: test_FMADD_ASSOC1:
 ; CHECK: fmadd
 ; CHECK-NEXT: fmadd
@@ -22,11 +22,11 @@ define double @test_FMADD_ASSOC1(double %A, double %B, double %C,
 
 define double @test_FMADD_ASSOC2(double %A, double %B, double %C,
                                  double %D, double %E) {
-	%F = fmul double %A, %B         ; <double> [#uses=1]
-	%G = fmul double %C, %D         ; <double> [#uses=1]
-	%H = fadd double %F, %G         ; <double> [#uses=1]
-	%I = fadd double %E, %H         ; <double> [#uses=1]
-	ret double %I
+  %F = fmul double %A, %B         ; <double> [#uses=1]
+  %G = fmul double %C, %D         ; <double> [#uses=1]
+  %H = fadd double %F, %G         ; <double> [#uses=1]
+  %I = fadd double %E, %H         ; <double> [#uses=1]
+  ret double %I
 ; CHECK-LABEL: test_FMADD_ASSOC2:
 ; CHECK: fmadd
 ; CHECK-NEXT: fmadd
@@ -41,11 +41,11 @@ define double @test_FMADD_ASSOC2(double %A, double %B, double %C,
 
 define double @test_FMSUB_ASSOC1(double %A, double %B, double %C,
                                  double %D, double %E) {
-	%F = fmul double %A, %B         ; <double> [#uses=1]
-	%G = fmul double %C, %D         ; <double> [#uses=1]
-	%H = fadd double %F, %G         ; <double> [#uses=1]
-	%I = fsub double %H, %E         ; <double> [#uses=1]
-	ret double %I
+  %F = fmul double %A, %B         ; <double> [#uses=1]
+  %G = fmul double %C, %D         ; <double> [#uses=1]
+  %H = fadd double %F, %G         ; <double> [#uses=1]
+  %I = fsub double %H, %E         ; <double> [#uses=1]
+  ret double %I
 ; CHECK-LABEL: test_FMSUB_ASSOC1:
 ; CHECK: fmsub
 ; CHECK-NEXT: fmadd
@@ -60,11 +60,11 @@ define double @test_FMSUB_ASSOC1(double %A, double %B, double %C,
 
 define double @test_FMSUB_ASSOC2(double %A, double %B, double %C,
                                  double %D, double %E) {
-	%F = fmul double %A, %B         ; <double> [#uses=1]
-	%G = fmul double %C, %D         ; <double> [#uses=1]
-	%H = fadd double %F, %G         ; <double> [#uses=1]
-	%I = fsub double %E, %H         ; <double> [#uses=1]
-	ret double %I
+  %F = fmul double %A, %B         ; <double> [#uses=1]
+  %G = fmul double %C, %D         ; <double> [#uses=1]
+  %H = fadd double %F, %G         ; <double> [#uses=1]
+  %I = fsub double %E, %H         ; <double> [#uses=1]
+  ret double %I
 ; CHECK-LABEL: test_FMSUB_ASSOC2:
 ; CHECK: fnmsub
 ; CHECK-NEXT: fnmsub
@@ -77,3 +77,159 @@ define double @test_FMSUB_ASSOC2(double %A, double %B, double %C,
 ; CHECK-VSX-NEXT: blr
 }
 
+define double @test_FMADD_ASSOC_EXT1(float %A, float %B, double %C,
+                                 double %D, double %E) {
+  %F = fmul float %A, %B         ; <float> [#uses=1]
+  %G = fpext float %F to double   ; <double> [#uses=1]
+  %H = fmul double %C, %D         ; <double> [#uses=1]
+  %I = fadd double %H, %G         ; <double> [#uses=1]
+  %J = fadd double %I, %E         ; <double> [#uses=1]
+  ret double %J
+; CHECK-LABEL: test_FMADD_ASSOC_EXT1:
+; CHECK: fmadd
+; CHECK-NEXT: fmadd
+; CHECK-NEXT: blr
+
+; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT1:
+; CHECK-VSX: xsmaddmdp
+; CHECK-VSX-NEXT: xsmaddadp
+; CHECK-VSX-NEXT: blr
+}
+
+define double @test_FMADD_ASSOC_EXT2(float %A, float %B, float %C,
+                                 float %D, double %E) {
+  %F = fmul float %A, %B         ; <float> [#uses=1]
+  %G = fmul float %C, %D         ; <float> [#uses=1]
+  %H = fadd float %F, %G         ; <float> [#uses=1]
+  %I = fpext float %H to double   ; <double> [#uses=1]
+  %J = fadd double %I, %E         ; <double> [#uses=1]
+  ret double %J
+; CHECK-LABEL: test_FMADD_ASSOC_EXT2:
+; CHECK: fmadd
+; CHECK-NEXT: fmadd
+; CHECK-NEXT: blr
+
+; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT2:
+; CHECK-VSX: xsmaddmdp
+; CHECK-VSX-NEXT: xsmaddadp
+; CHECK-VSX-NEXT: fmr
+; CHECK-VSX-NEXT: blr
+}
+
+define double @test_FMADD_ASSOC_EXT3(float %A, float %B, double %C,
+                                 double %D, double %E) {
+  %F = fmul float %A, %B          ; <float> [#uses=1]
+  %G = fpext float %F to double   ; <double> [#uses=1]
+  %H = fmul double %C, %D         ; <double> [#uses=1]
+  %I = fadd double %H, %G         ; <double> [#uses=1]
+  %J = fadd double %E, %I         ; <double> [#uses=1]
+  ret double %J
+; CHECK-LABEL: test_FMADD_ASSOC_EXT3:
+; CHECK: fmadd
+; CHECK-NEXT: fmadd
+; CHECK-NEXT: blr
+
+; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT3:
+; CHECK-VSX: xsmaddmdp
+; CHECK-VSX-NEXT: xsmaddadp
+; CHECK-VSX-NEXT: blr
+}
+
+define double @test_FMADD_ASSOC_EXT4(float %A, float %B, float %C,
+                                 float %D, double %E) {
+  %F = fmul float %A, %B          ; <float> [#uses=1]
+  %G = fmul float %C, %D          ; <float> [#uses=1]
+  %H = fadd float %F, %G          ; <float> [#uses=1]
+  %I = fpext float %H to double   ; <double> [#uses=1]
+  %J = fadd double %E, %I         ; <double> [#uses=1]
+  ret double %J
+; CHECK-LABEL: test_FMADD_ASSOC_EXT4:
+; CHECK: fmadd
+; CHECK-NEXT: fmadd
+; CHECK-NEXT: blr
+
+; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT4:
+; CHECK-VSX: xsmaddmdp
+; CHECK-VSX-NEXT: xsmaddadp
+; CHECK-VSX-NEXT: fmr
+; CHECK-VSX-NEXT: blr
+}
+
+define double @test_FMSUB_ASSOC_EXT1(float %A, float %B, double %C,
+                                 double %D, double %E) {
+  %F = fmul float %A, %B          ; <float> [#uses=1]
+  %G = fpext float %F to double   ; <double> [#uses=1]
+  %H = fmul double %C, %D         ; <double> [#uses=1]
+  %I = fadd double %H, %G         ; <double> [#uses=1]
+  %J = fsub double %I, %E         ; <double> [#uses=1]
+  ret double %J
+; CHECK-LABEL: test_FMSUB_ASSOC_EXT1:
+; CHECK: fmsub
+; CHECK-NEXT: fmadd
+; CHECK-NEXT: blr
+
+; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT1:
+; CHECK-VSX: xsmsubmdp
+; CHECK-VSX-NEXT: xsmaddadp
+; CHECK-VSX-NEXT: blr
+}
+
+define double @test_FMSUB_ASSOC_EXT2(float %A, float %B, float %C,
+                                 float %D, double %E) {
+  %F = fmul float %A, %B          ; <float> [#uses=1]
+  %G = fmul float %C, %D          ; <float> [#uses=1]
+  %H = fadd float %F, %G          ; <float> [#uses=1]
+  %I = fpext float %H to double   ; <double> [#uses=1]
+  %J = fsub double %I, %E         ; <double> [#uses=1]
+  ret double %J
+; CHECK-LABEL: test_FMSUB_ASSOC_EXT2:
+; CHECK: fmsub
+; CHECK-NEXT: fmadd
+; CHECK-NEXT: blr
+
+; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT2:
+; CHECK-VSX: xsmsubmdp
+; CHECK-VSX-NEXT: xsmaddadp
+; CHECK-VSX-NEXT: fmr
+; CHECK-VSX-NEXT: blr
+}
+
+define double @test_FMSUB_ASSOC_EXT3(float %A, float %B, double %C,
+                                 double %D, double %E) {
+  %F = fmul float %A, %B          ; <float> [#uses=1]
+  %G = fpext float %F to double   ; <double> [#uses=1]
+  %H = fmul double %C, %D         ; <double> [#uses=1]
+  %I = fadd double %H, %G         ; <double> [#uses=1]
+  %J = fsub double %E, %I         ; <double> [#uses=1]
+  ret double %J
+; CHECK-LABEL: test_FMSUB_ASSOC_EXT3:
+; CHECK: fnmsub
+; CHECK-NEXT: fnmsub
+; CHECK-NEXT: blr
+
+; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT3:
+; CHECK-VSX: xsnmsubmdp
+; CHECK-VSX-NEXT: xsnmsubadp
+; CHECK-VSX-NEXT: fmr
+; CHECK-VSX-NEXT: blr
+}
+
+define double @test_FMSUB_ASSOC_EXT4(float %A, float %B, float %C,
+                                 float %D, double %E) {
+  %F = fmul float %A, %B          ; <float> [#uses=1]
+  %G = fmul float %C, %D          ; <float> [#uses=1]
+  %H = fadd float %F, %G          ; <float> [#uses=1]
+  %I = fpext float %H to double   ; <double> [#uses=1]
+  %J = fsub double %E, %I         ; <double> [#uses=1]
+  ret double %J
+; CHECK-LABEL: test_FMSUB_ASSOC_EXT4:
+; CHECK: fnmsub
+; CHECK-NEXT: fnmsub
+; CHECK-NEXT: blr
+
+; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT4:
+; CHECK-VSX: xsnmsubmdp
+; CHECK-VSX-NEXT: xsnmsubadp
+; CHECK-VSX-NEXT: fmr
+; CHECK-VSX-NEXT: blr
+}
diff --git a/test/CodeGen/PowerPC/fma-ext.ll b/test/CodeGen/PowerPC/fma-ext.ll
index 56825ce8f227..da7c34ccb9d8 100644
--- a/test/CodeGen/PowerPC/fma-ext.ll
+++ b/test/CodeGen/PowerPC/fma-ext.ll
@@ -60,34 +60,34 @@ define double @test_FMSUB_EXT2(float %A, float %B, double %C) {
 
 define double @test_FMSUB_EXT3(float %A, float %B, double %C) {
     %D = fmul float %A, %B          ; <float> [#uses=1]
-    %E = fsub float -0.000000e+00, %D ;		<float> [#uses=1]
+    %E = fsub float -0.000000e+00, %D ;    <float> [#uses=1]
     %F = fpext float %E to double   ; <double> [#uses=1]
     %G = fsub double %F, %C         ; <double> [#uses=1]
     ret double %G
 ; CHECK-LABEL: test_FMSUB_EXT3:
-; CHECK: fneg
-; CHECK-NEXT: fmsub
+; CHECK: fnmadd
+
 ; CHECK-NEXT: blr
                                 
 ; CHECK-VSX-LABEL: test_FMSUB_EXT3:
-; CHECK-VSX: xsnegdp
-; CHECK-VSX-NEXT: xsmsubmdp
+; CHECK-VSX: xsnmaddmdp
+
 ; CHECK-VSX-NEXT: blr
 }
     
 define double @test_FMSUB_EXT4(float %A, float %B, double %C) {
     %D = fmul float %A, %B          ; <float> [#uses=1]
     %E = fpext float %D to double   ; <double> [#uses=1]
-    %F = fsub double -0.000000e+00, %E ;		<double> [#uses=1]
+    %F = fsub double -0.000000e+00, %E ;    <double> [#uses=1]
     %G = fsub double %F, %C         ; <double> [#uses=1]
     ret double %G
 ; CHECK-LABEL: test_FMSUB_EXT4:
-; CHECK: fneg
-; CHECK-NEXT: fmsub
+; CHECK: fnmadd
+
 ; CHECK-NEXT: blr
                                 
 ; CHECK-VSX-LABEL: test_FMSUB_EXT4:
-; CHECK-VSX: xsnegdp
-; CHECK-VSX-NEXT: xsmsubmdp
+; CHECK-VSX: xsnmaddmdp
+
 ; CHECK-VSX-NEXT: blr
-}  
\ No newline at end of file
+}  
diff --git a/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll b/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
new file mode 100644
index 000000000000..1d9b64823140
--- /dev/null
+++ b/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
@@ -0,0 +1,426 @@
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+
+; Function Attrs: nounwind
+define zeroext i8 @_Z6testcff(float %arg) {
+entry:
+  %arg.addr = alloca float, align 4
+  store float %arg, float* %arg.addr, align 4
+  %0 = load float, float* %arg.addr, align 4
+  %conv = fptoui float %0 to i8
+  ret i8 %conv
+; CHECK-LABEL: @_Z6testcff
+; CHECK: xscvdpsxws [[CONVREG01:[0-9]+]], 1
+; CHECK: mfvsrwz 3, [[CONVREG01]]
+}
+
+; Function Attrs: nounwind
+define float @_Z6testfcc(i8 zeroext %arg) {
+entry:
+  %arg.addr = alloca i8, align 1
+  store i8 %arg, i8* %arg.addr, align 1
+  %0 = load i8, i8* %arg.addr, align 1
+  %conv = uitofp i8 %0 to float
+  ret float %conv
+; CHECK-LABEL: @_Z6testfcc
+; CHECK: mtvsrwz [[MOVEREG01:[0-9]+]], 3
+; FIXME: Once we have XSCVUXDSP implemented, this will change
+; CHECK: fcfidus 1, [[MOVEREG01]]
+}
+
+; Function Attrs: nounwind
+define zeroext i8 @_Z6testcdd(double %arg) {
+entry:
+  %arg.addr = alloca double, align 8
+  store double %arg, double* %arg.addr, align 8
+  %0 = load double, double* %arg.addr, align 8
+  %conv = fptoui double %0 to i8
+  ret i8 %conv
+; CHECK-LABEL: @_Z6testcdd
+; CHECK: xscvdpsxws [[CONVREG02:[0-9]+]], 1
+; CHECK: mfvsrwz 3, [[CONVREG02]]
+}
+
+; Function Attrs: nounwind
+define double @_Z6testdcc(i8 zeroext %arg) {
+entry:
+  %arg.addr = alloca i8, align 1
+  store i8 %arg, i8* %arg.addr, align 1
+  %0 = load i8, i8* %arg.addr, align 1
+  %conv = uitofp i8 %0 to double
+  ret double %conv
+; CHECK-LABEL: @_Z6testdcc
+; CHECK: mtvsrwz [[MOVEREG02:[0-9]+]], 3
+; CHECK: xscvuxddp 1, [[MOVEREG02]]
+}
+
+; Function Attrs: nounwind
+define zeroext i8 @_Z7testucff(float %arg) {
+entry:
+  %arg.addr = alloca float, align 4
+  store float %arg, float* %arg.addr, align 4
+  %0 = load float, float* %arg.addr, align 4
+  %conv = fptoui float %0 to i8
+  ret i8 %conv
+; CHECK-LABEL: @_Z7testucff
+; CHECK: xscvdpsxws [[CONVREG03:[0-9]+]], 1
+; CHECK: mfvsrwz 3, [[CONVREG03]]
+}
+
+; Function Attrs: nounwind
+define float @_Z7testfuch(i8 zeroext %arg) {
+entry:
+  %arg.addr = alloca i8, align 1
+  store i8 %arg, i8* %arg.addr, align 1
+  %0 = load i8, i8* %arg.addr, align 1
+  %conv = uitofp i8 %0 to float
+  ret float %conv
+; CHECK-LABEL: @_Z7testfuch
+; CHECK: mtvsrwz [[MOVEREG03:[0-9]+]], 3
+; FIXME: Once we have XSCVUXDSP implemented, this will change
+; CHECK: fcfidus 1, [[MOVEREG03]]
+}
+
+; Function Attrs: nounwind
+define zeroext i8 @_Z7testucdd(double %arg) {
+entry:
+  %arg.addr = alloca double, align 8
+  store double %arg, double* %arg.addr, align 8
+  %0 = load double, double* %arg.addr, align 8
+  %conv = fptoui double %0 to i8
+  ret i8 %conv
+; CHECK-LABEL: @_Z7testucdd
+; CHECK: xscvdpsxws [[CONVREG04:[0-9]+]], 1
+; CHECK: mfvsrwz 3, [[CONVREG04]]
+}
+
+; Function Attrs: nounwind
+define double @_Z7testduch(i8 zeroext %arg) {
+entry:
+  %arg.addr = alloca i8, align 1
+  store i8 %arg, i8* %arg.addr, align 1
+  %0 = load i8, i8* %arg.addr, align 1
+  %conv = uitofp i8 %0 to double
+  ret double %conv
+; CHECK-LABEL: @_Z7testduch
+; CHECK: mtvsrwz [[MOVEREG04:[0-9]+]], 3
+; CHECK: xscvuxddp 1, [[MOVEREG04]]
+}
+
+; Function Attrs: nounwind
+define signext i16 @_Z6testsff(float %arg) {
+entry:
+  %arg.addr = alloca float, align 4
+  store float %arg, float* %arg.addr, align 4
+  %0 = load float, float* %arg.addr, align 4
+  %conv = fptosi float %0 to i16
+  ret i16 %conv
+; CHECK-LABEL: @_Z6testsff
+; CHECK: xscvdpsxws [[CONVREG05:[0-9]+]], 1
+; CHECK: mfvsrwz 3, [[CONVREG05]]
+}
+
+; Function Attrs: nounwind
+define float @_Z6testfss(i16 signext %arg) {
+entry:
+  %arg.addr = alloca i16, align 2
+  store i16 %arg, i16* %arg.addr, align 2
+  %0 = load i16, i16* %arg.addr, align 2
+  %conv = sitofp i16 %0 to float
+  ret float %conv
+; CHECK-LABEL: @_Z6testfss
+; CHECK: mtvsrwa [[MOVEREG05:[0-9]+]], 3
+; FIXME: Once we have XSCVSXDSP implemented, this will change
+; CHECK: fcfids 1, [[MOVEREG05]]
+}
+
+; Function Attrs: nounwind
+define signext i16 @_Z6testsdd(double %arg) {
+entry:
+  %arg.addr = alloca double, align 8
+  store double %arg, double* %arg.addr, align 8
+  %0 = load double, double* %arg.addr, align 8
+  %conv = fptosi double %0 to i16
+  ret i16 %conv
+; CHECK-LABEL: @_Z6testsdd
+; CHECK: xscvdpsxws [[CONVREG06:[0-9]+]], 1
+; CHECK: mfvsrwz 3, [[CONVREG06]]
+}
+
+; Function Attrs: nounwind
+define double @_Z6testdss(i16 signext %arg) {
+entry:
+  %arg.addr = alloca i16, align 2
+  store i16 %arg, i16* %arg.addr, align 2
+  %0 = load i16, i16* %arg.addr, align 2
+  %conv = sitofp i16 %0 to double
+  ret double %conv
+; CHECK-LABEL: @_Z6testdss
+; CHECK: mtvsrwa [[MOVEREG06:[0-9]+]], 3
+; CHECK: xscvsxddp 1, [[MOVEREG06]]
+}
+
+; Function Attrs: nounwind
+define zeroext i16 @_Z7testusff(float %arg) {
+entry:
+  %arg.addr = alloca float, align 4
+  store float %arg, float* %arg.addr, align 4
+  %0 = load float, float* %arg.addr, align 4
+  %conv = fptoui float %0 to i16
+  ret i16 %conv
+; CHECK-LABEL: @_Z7testusff
+; CHECK: xscvdpsxws [[CONVREG07:[0-9]+]], 1
+; CHECK: mfvsrwz 3, [[CONVREG07]]
+}
+
+; Function Attrs: nounwind
+define float @_Z7testfust(i16 zeroext %arg) {
+entry:
+  %arg.addr = alloca i16, align 2
+  store i16 %arg, i16* %arg.addr, align 2
+  %0 = load i16, i16* %arg.addr, align 2
+  %conv = uitofp i16 %0 to float
+  ret float %conv
+; CHECK-LABEL: @_Z7testfust
+; CHECK: mtvsrwz [[MOVEREG07:[0-9]+]], 3
+; FIXME: Once we have XSCVUXDSP implemented, this will change
+; CHECK: fcfidus 1, [[MOVEREG07]]
+}
+
+; Function Attrs: nounwind
+define zeroext i16 @_Z7testusdd(double %arg) {
+entry:
+  %arg.addr = alloca double, align 8
+  store double %arg, double* %arg.addr, align 8
+  %0 = load double, double* %arg.addr, align 8
+  %conv = fptoui double %0 to i16
+  ret i16 %conv
+; CHECK-LABEL: @_Z7testusdd
+; CHECK: xscvdpsxws [[CONVREG08:[0-9]+]], 1
+; CHECK: mfvsrwz 3, [[CONVREG08]]
+}
+
+; Function Attrs: nounwind
+define double @_Z7testdust(i16 zeroext %arg) {
+entry:
+  %arg.addr = alloca i16, align 2
+  store i16 %arg, i16* %arg.addr, align 2
+  %0 = load i16, i16* %arg.addr, align 2
+  %conv = uitofp i16 %0 to double
+  ret double %conv
+; CHECK-LABEL: @_Z7testdust
+; CHECK: mtvsrwz [[MOVEREG08:[0-9]+]], 3
+; CHECK: xscvuxddp 1, [[MOVEREG08]]
+}
+
+; Function Attrs: nounwind
+define signext i32 @_Z6testiff(float %arg) {
+entry:
+  %arg.addr = alloca float, align 4
+  store float %arg, float* %arg.addr, align 4
+  %0 = load float, float* %arg.addr, align 4
+  %conv = fptosi float %0 to i32
+  ret i32 %conv
+; CHECK-LABEL: @_Z6testiff
+; CHECK: xscvdpsxws [[CONVREG09:[0-9]+]], 1
+; CHECK: mfvsrwz 3, [[CONVREG09]]
+}
+
+; Function Attrs: nounwind
+define float @_Z6testfii(i32 signext %arg) {
+entry:
+  %arg.addr = alloca i32, align 4
+  store i32 %arg, i32* %arg.addr, align 4
+  %0 = load i32, i32* %arg.addr, align 4
+  %conv = sitofp i32 %0 to float
+  ret float %conv
+; CHECK-LABEL: @_Z6testfii
+; CHECK: mtvsrwa [[MOVEREG09:[0-9]+]], 3
+; FIXME: Once we have XSCVSXDSP implemented, this will change
+; CHECK: fcfids 1, [[MOVEREG09]]
+}
+
+; Function Attrs: nounwind
+define signext i32 @_Z6testidd(double %arg) {
+entry:
+  %arg.addr = alloca double, align 8
+  store double %arg, double* %arg.addr, align 8
+  %0 = load double, double* %arg.addr, align 8
+  %conv = fptosi double %0 to i32
+  ret i32 %conv
+; CHECK-LABEL: @_Z6testidd
+; CHECK: xscvdpsxws [[CONVREG10:[0-9]+]], 1
+; CHECK: mfvsrwz 3, [[CONVREG10]]
+}
+
+; Function Attrs: nounwind
+define double @_Z6testdii(i32 signext %arg) {
+entry:
+  %arg.addr = alloca i32, align 4
+  store i32 %arg, i32* %arg.addr, align 4
+  %0 = load i32, i32* %arg.addr, align 4
+  %conv = sitofp i32 %0 to double
+  ret double %conv
+; CHECK-LABEL: @_Z6testdii
+; CHECK: mtvsrwa [[MOVEREG10:[0-9]+]], 3
+; CHECK: xscvsxddp 1, [[MOVEREG10]]
+}
+
+; Function Attrs: nounwind
+define zeroext i32 @_Z7testuiff(float %arg) {
+entry:
+  %arg.addr = alloca float, align 4
+  store float %arg, float* %arg.addr, align 4
+  %0 = load float, float* %arg.addr, align 4
+  %conv = fptoui float %0 to i32
+  ret i32 %conv
+; CHECK-LABEL: @_Z7testuiff
+; CHECK: xscvdpuxws [[CONVREG11:[0-9]+]], 1
+; CHECK: mfvsrwz 3, [[CONVREG11]]
+}
+
+; Function Attrs: nounwind
+define float @_Z7testfuij(i32 zeroext %arg) {
+entry:
+  %arg.addr = alloca i32, align 4
+  store i32 %arg, i32* %arg.addr, align 4
+  %0 = load i32, i32* %arg.addr, align 4
+  %conv = uitofp i32 %0 to float
+  ret float %conv
+; CHECK-LABEL: @_Z7testfuij
+; CHECK: mtvsrwz [[MOVEREG11:[0-9]+]], 3
+; FIXME: Once we have XSCVUXDSP implemented, this will change
+; CHECK: fcfidus 1, [[MOVEREG11]]
+}
+
+; Function Attrs: nounwind
+define zeroext i32 @_Z7testuidd(double %arg) {
+entry:
+  %arg.addr = alloca double, align 8
+  store double %arg, double* %arg.addr, align 8
+  %0 = load double, double* %arg.addr, align 8
+  %conv = fptoui double %0 to i32
+  ret i32 %conv
+; CHECK-LABEL: @_Z7testuidd
+; CHECK: xscvdpuxws [[CONVREG12:[0-9]+]], 1
+; CHECK: mfvsrwz 3, [[CONVREG12]]
+}
+
+; Function Attrs: nounwind
+define double @_Z7testduij(i32 zeroext %arg) {
+entry:
+  %arg.addr = alloca i32, align 4
+  store i32 %arg, i32* %arg.addr, align 4
+  %0 = load i32, i32* %arg.addr, align 4
+  %conv = uitofp i32 %0 to double
+  ret double %conv
+; CHECK-LABEL: @_Z7testduij
+; CHECK: mtvsrwz [[MOVEREG12:[0-9]+]], 3
+; CHECK: xscvuxddp 1, [[MOVEREG12]]
+}
+
+; Function Attrs: nounwind
+define i64 @_Z7testllff(float %arg) {
+entry:
+  %arg.addr = alloca float, align 4
+  store float %arg, float* %arg.addr, align 4
+  %0 = load float, float* %arg.addr, align 4
+  %conv = fptosi float %0 to i64
+  ret i64 %conv
+; CHECK-LABEL: @_Z7testllff
+; CHECK: xscvdpsxds [[CONVREG13:[0-9]+]], 1
+; CHECK: mfvsrd 3, [[CONVREG13]]
+}
+
+; Function Attrs: nounwind
+define float @_Z7testfllx(i64 %arg) {
+entry:
+  %arg.addr = alloca i64, align 8
+  store i64 %arg, i64* %arg.addr, align 8
+  %0 = load i64, i64* %arg.addr, align 8
+  %conv = sitofp i64 %0 to float
+  ret float %conv
+; CHECK-LABEL:@_Z7testfllx
+; CHECK: mtvsrd [[MOVEREG13:[0-9]+]], 3
+; FIXME: Once we have XSCVSXDSP implemented, this will change
+; CHECK: fcfids 1, [[MOVEREG13]]
+}
+
+; Function Attrs: nounwind
+define i64 @_Z7testlldd(double %arg) {
+entry:
+  %arg.addr = alloca double, align 8
+  store double %arg, double* %arg.addr, align 8
+  %0 = load double, double* %arg.addr, align 8
+  %conv = fptosi double %0 to i64
+  ret i64 %conv
+; CHECK-LABEL: @_Z7testlldd
+; CHECK: xscvdpsxds [[CONVREG14:[0-9]+]], 1
+; CHECK: mfvsrd 3, [[CONVREG14]]
+}
+
+; Function Attrs: nounwind
+define double @_Z7testdllx(i64 %arg) {
+entry:
+  %arg.addr = alloca i64, align 8
+  store i64 %arg, i64* %arg.addr, align 8
+  %0 = load i64, i64* %arg.addr, align 8
+  %conv = sitofp i64 %0 to double
+  ret double %conv
+; CHECK-LABEL: @_Z7testdllx
+; CHECK: mtvsrd [[MOVEREG14:[0-9]+]], 3
+; CHECK: xscvsxddp 1, [[MOVEREG14]]
+}
+
+; Function Attrs: nounwind
+define i64 @_Z8testullff(float %arg) {
+entry:
+  %arg.addr = alloca float, align 4
+  store float %arg, float* %arg.addr, align 4
+  %0 = load float, float* %arg.addr, align 4
+  %conv = fptoui float %0 to i64
+  ret i64 %conv
+; CHECK-LABEL: @_Z8testullff
+; CHECK: xscvdpuxds [[CONVREG15:[0-9]+]], 1
+; CHECK: mfvsrd 3, [[CONVREG15]]
+}
+
+; Function Attrs: nounwind
+define float @_Z8testfully(i64 %arg) {
+entry:
+  %arg.addr = alloca i64, align 8
+  store i64 %arg, i64* %arg.addr, align 8
+  %0 = load i64, i64* %arg.addr, align 8
+  %conv = uitofp i64 %0 to float
+  ret float %conv
+; CHECK-LABEL: @_Z8testfully
+; CHECK: mtvsrd [[MOVEREG15:[0-9]+]], 3
+; FIXME: Once we have XSCVUXDSP implemented, this will change
+; CHECK: fcfidus 1, [[MOVEREG15]]
+}
+
+; Function Attrs: nounwind
+define i64 @_Z8testulldd(double %arg) {
+entry:
+  %arg.addr = alloca double, align 8
+  store double %arg, double* %arg.addr, align 8
+  %0 = load double, double* %arg.addr, align 8
+  %conv = fptoui double %0 to i64
+  ret i64 %conv
+; CHECK-LABEL: @_Z8testulldd
+; CHECK: xscvdpuxds [[CONVREG16:[0-9]+]], 1
+; CHECK: mfvsrd 3, [[CONVREG16]]
+}
+
+; Function Attrs: nounwind
+define double @_Z8testdully(i64 %arg) {
+entry:
+  %arg.addr = alloca i64, align 8
+  store i64 %arg, i64* %arg.addr, align 8
+  %0 = load i64, i64* %arg.addr, align 8
+  %conv = uitofp i64 %0 to double
+  ret double %conv
+; CHECK-LABEL: @_Z8testdully
+; CHECK: mtvsrd [[MOVEREG16:[0-9]+]], 3
+; CHECK: xscvuxddp 1, [[MOVEREG16]]
+}
diff --git a/test/CodeGen/PowerPC/fp-to-int-ext.ll b/test/CodeGen/PowerPC/fp-to-int-ext.ll
index bfacd89ca1a2..393fe04d41c6 100644
--- a/test/CodeGen/PowerPC/fp-to-int-ext.ll
+++ b/test/CodeGen/PowerPC/fp-to-int-ext.ll
@@ -5,7 +5,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 ; Function Attrs: nounwind
 define double @foo1(i32* %x) #0 {
 entry:
-  %0 = load i32* %x, align 4
+  %0 = load i32, i32* %x, align 4
   %conv = sext i32 %0 to i64
   %conv1 = sitofp i64 %conv to double
   ret double %conv1
@@ -18,7 +18,7 @@ entry:
 
 define double @foo2(i32* %x) #0 {
 entry:
-  %0 = load i32* %x, align 4
+  %0 = load i32, i32* %x, align 4
   %conv = zext i32 %0 to i64
   %conv1 = sitofp i64 %conv to double
   ret double %conv1
@@ -31,7 +31,7 @@ entry:
 
 define double @foo3(i32* %x) #0 {
 entry:
-  %0 = load i32* %x, align 4
+  %0 = load i32, i32* %x, align 4
   %1 = add i32 %0, 8
   %conv = zext i32 %1 to i64
   %conv1 = sitofp i64 %conv to double
@@ -49,7 +49,7 @@ entry:
 
 define double @foo4(i32* %x) #0 {
 entry:
-  %0 = load i32* %x, align 4
+  %0 = load i32, i32* %x, align 4
   %1 = add i32 %0, 8
   %conv = sext i32 %1 to i64
   %conv1 = sitofp i64 %conv to double
diff --git a/test/CodeGen/PowerPC/frounds.ll b/test/CodeGen/PowerPC/frounds.ll
index 8eeadc3a3469..49f3465e9e22 100644
--- a/test/CodeGen/PowerPC/frounds.ll
+++ b/test/CodeGen/PowerPC/frounds.ll
@@ -7,12 +7,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	%tmp1 = call i32 @llvm.flt.rounds( )		; <i32> [#uses=1]
 	store i32 %tmp1, i32* %tmp, align 4
-	%tmp2 = load i32* %tmp, align 4		; <i32> [#uses=1]
+	%tmp2 = load i32, i32* %tmp, align 4		; <i32> [#uses=1]
 	store i32 %tmp2, i32* %retval, align 4
 	br label %return
 
 return:		; preds = %entry
-	%retval3 = load i32* %retval		; <i32> [#uses=1]
+	%retval3 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval3
 }
 
diff --git a/test/CodeGen/PowerPC/glob-comp-aa-crash.ll b/test/CodeGen/PowerPC/glob-comp-aa-crash.ll
index 2ea036f83496..66df6bb8669d 100644
--- a/test/CodeGen/PowerPC/glob-comp-aa-crash.ll
+++ b/test/CodeGen/PowerPC/glob-comp-aa-crash.ll
@@ -23,17 +23,17 @@ entry:
   %ref.tmp = alloca %"class.std::__exception_ptr::exception_ptr", align 8
   %tmp = alloca { i64, i64 }, align 8
   %agg.tmp = alloca %"class.std::__exception_ptr::exception_ptr", align 8
-  %__mut_ = getelementptr inbounds %"class.std::__1::__assoc_sub_state"* %this, i64 0, i32 2
-  %__m_.i.i = getelementptr inbounds %"class.std::__1::unique_lock"* %__lk, i64 0, i32 0
+  %__mut_ = getelementptr inbounds %"class.std::__1::__assoc_sub_state", %"class.std::__1::__assoc_sub_state"* %this, i64 0, i32 2
+  %__m_.i.i = getelementptr inbounds %"class.std::__1::unique_lock", %"class.std::__1::unique_lock"* %__lk, i64 0, i32 0
   store %"class.std::__1::mutex"* %__mut_, %"class.std::__1::mutex"** %__m_.i.i, align 8, !tbaa !5
-  %__owns_.i.i = getelementptr inbounds %"class.std::__1::unique_lock"* %__lk, i64 0, i32 1
+  %__owns_.i.i = getelementptr inbounds %"class.std::__1::unique_lock", %"class.std::__1::unique_lock"* %__lk, i64 0, i32 1
   store i8 1, i8* %__owns_.i.i, align 8, !tbaa !6
   call void @_ZNSt3__15mutex4lockEv(%"class.std::__1::mutex"* %__mut_) #4
   invoke void @_ZNSt3__117__assoc_sub_state10__sub_waitERNS_11unique_lockINS_5mutexEEE(%"class.std::__1::__assoc_sub_state"* %this, %"class.std::__1::unique_lock"* %__lk) #4
           to label %invoke.cont unwind label %lpad
 
 invoke.cont:                                      ; preds = %entry
-  %__exception_ = getelementptr inbounds %"class.std::__1::__assoc_sub_state"* %this, i64 0, i32 1
+  %__exception_ = getelementptr inbounds %"class.std::__1::__assoc_sub_state", %"class.std::__1::__assoc_sub_state"* %this, i64 0, i32 1
   %0 = bitcast { i64, i64 }* %tmp to i8*
   call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 16, i32 8, i1 false)
   call void @_ZNSt15__exception_ptr13exception_ptrC1EMS0_FvvE(%"class.std::__exception_ptr::exception_ptr"* %ref.tmp, { i64, i64 }* byval %tmp) #5
@@ -65,12 +65,12 @@ lpad3:                                            ; preds = %if.then
   br label %ehcleanup
 
 if.end:                                           ; preds = %invoke.cont
-  %7 = load i8* %__owns_.i.i, align 8, !tbaa !6, !range !4
+  %7 = load i8, i8* %__owns_.i.i, align 8, !tbaa !6, !range !4
   %tobool.i.i = icmp eq i8 %7, 0
   br i1 %tobool.i.i, label %_ZNSt3__111unique_lockINS_5mutexEED1Ev.exit, label %if.then.i.i
 
 if.then.i.i:                                      ; preds = %if.end
-  %8 = load %"class.std::__1::mutex"** %__m_.i.i, align 8, !tbaa !5
+  %8 = load %"class.std::__1::mutex"*, %"class.std::__1::mutex"** %__m_.i.i, align 8, !tbaa !5
   call void @_ZNSt3__15mutex6unlockEv(%"class.std::__1::mutex"* %8) #5
   br label %_ZNSt3__111unique_lockINS_5mutexEED1Ev.exit
 
@@ -80,12 +80,12 @@ _ZNSt3__111unique_lockINS_5mutexEED1Ev.exit:      ; preds = %if.then.i.i, %if.en
 ehcleanup:                                        ; preds = %lpad3, %lpad
   %exn.slot.0 = phi i8* [ %5, %lpad3 ], [ %2, %lpad ]
   %ehselector.slot.0 = phi i32 [ %6, %lpad3 ], [ %3, %lpad ]
-  %9 = load i8* %__owns_.i.i, align 8, !tbaa !6, !range !4
+  %9 = load i8, i8* %__owns_.i.i, align 8, !tbaa !6, !range !4
   %tobool.i.i9 = icmp eq i8 %9, 0
   br i1 %tobool.i.i9, label %_ZNSt3__111unique_lockINS_5mutexEED1Ev.exit12, label %if.then.i.i11
 
 if.then.i.i11:                                    ; preds = %ehcleanup
-  %10 = load %"class.std::__1::mutex"** %__m_.i.i, align 8, !tbaa !5
+  %10 = load %"class.std::__1::mutex"*, %"class.std::__1::mutex"** %__m_.i.i, align 8, !tbaa !5
   call void @_ZNSt3__15mutex6unlockEv(%"class.std::__1::mutex"* %10) #5
   br label %_ZNSt3__111unique_lockINS_5mutexEED1Ev.exit12
 
diff --git a/test/CodeGen/PowerPC/hello.ll b/test/CodeGen/PowerPC/hello.ll
index ea27e9257a65..da7fb31526b9 100644
--- a/test/CodeGen/PowerPC/hello.ll
+++ b/test/CodeGen/PowerPC/hello.ll
@@ -5,7 +5,7 @@
 @.str = internal constant [13 x i8] c"Hello World!\00"
 
 define i32 @main() {
-	%tmp2 = tail call i32 @puts( i8* getelementptr ([13 x i8]* @.str, i32 0, i64 0) )
+	%tmp2 = tail call i32 @puts( i8* getelementptr ([13 x i8], [13 x i8]* @.str, i32 0, i64 0) )
 	ret i32 0
 }
 
diff --git a/test/CodeGen/PowerPC/hidden-vis-2.ll b/test/CodeGen/PowerPC/hidden-vis-2.ll
index e9e2c0a93a0d..3eb9dbd21ade 100644
--- a/test/CodeGen/PowerPC/hidden-vis-2.ll
+++ b/test/CodeGen/PowerPC/hidden-vis-2.ll
@@ -5,8 +5,8 @@
 
 define i32 @t() nounwind readonly {
 entry:
-	%0 = load i32* @x, align 4		; <i32> [#uses=1]
-	%1 = load i32* @y, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* @x, align 4		; <i32> [#uses=1]
+	%1 = load i32, i32* @y, align 4		; <i32> [#uses=1]
 	%2 = add i32 %1, %0		; <i32> [#uses=1]
 	ret i32 %2
 }
diff --git a/test/CodeGen/PowerPC/hidden-vis.ll b/test/CodeGen/PowerPC/hidden-vis.ll
index b2cc1431ebde..bcb6723402b0 100644
--- a/test/CodeGen/PowerPC/hidden-vis.ll
+++ b/test/CodeGen/PowerPC/hidden-vis.ll
@@ -4,6 +4,6 @@
 
 define i32 @t() nounwind readonly {
 entry:
-	%0 = load i32* @x, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* @x, align 4		; <i32> [#uses=1]
 	ret i32 %0
 }
diff --git a/test/CodeGen/PowerPC/htm.ll b/test/CodeGen/PowerPC/htm.ll
new file mode 100644
index 000000000000..0e4304dc163b
--- /dev/null
+++ b/test/CodeGen/PowerPC/htm.ll
@@ -0,0 +1,125 @@
+; RUN: llc -mcpu=pwr8 -mattr=+htm < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define zeroext i32 @test1() {
+entry:
+  %0 = tail call i32 @llvm.ppc.tbegin(i32 0)
+  ret i32 %0
+
+; CHECK-LABEL: @test1
+; CHECK: tbegin. 0
+; CHECK: mfocrf  [[REGISTER1:[0-9]+]], 128
+; CHECK: rlwinm  [[REGISTER2:[0-9]+]], [[REGISTER1]], 3, 31, 31
+; CHECK: xori    {{[0-9]+}}, [[REGISTER2]], 1
+}
+
+declare i32 @llvm.ppc.tbegin(i32) #1
+
+
+define zeroext i32 @test2() {
+entry:
+  %0 = tail call i32 @llvm.ppc.tend(i32 0)
+  ret i32 %0
+; CHECK-LABEL: @test2
+; CHECK: tend. 0
+; CHECK: mfocrf  {{[0-9]+}}, 128
+}
+
+declare i32 @llvm.ppc.tend(i32)
+
+
+define void @test3() {
+entry:
+  %0 = tail call i32 @llvm.ppc.tabort(i32 0)
+  %1 = tail call i32 @llvm.ppc.tabortdc(i32 0, i32 1, i32 2)
+  %2 = tail call i32 @llvm.ppc.tabortdci(i32 0, i32 1, i32 2)
+  %3 = tail call i32 @llvm.ppc.tabortwc(i32 0, i32 1, i32 2)
+  %4 = tail call i32 @llvm.ppc.tabortwci(i32 0, i32 1, i32 2)
+  ret void
+; CHECK-LABEL: @test3
+; CHECK: tabort.    {{[0-9]+}}
+; CHECK: tabortdc.  0, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: tabortdci. 0, {{[0-9]+}}, 2
+; CHECK: tabortwc.  0, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: tabortwci. 0, {{[0-9]+}}, 2
+}
+
+declare i32 @llvm.ppc.tabort(i32)
+declare i32 @llvm.ppc.tabortdc(i32, i32, i32)
+declare i32 @llvm.ppc.tabortdci(i32, i32, i32)
+declare i32 @llvm.ppc.tabortwc(i32, i32, i32)
+declare i32 @llvm.ppc.tabortwci(i32, i32, i32)
+
+
+define void @test4() {
+entry:
+  %0 = tail call i32 @llvm.ppc.tendall()
+  %1 = tail call i32 @llvm.ppc.tresume()
+  %2 = tail call i32 @llvm.ppc.tsuspend()
+  ret void
+; CHECK-LABEL: @test4
+; CHECK: tend. 1
+; CHECK: tsr.  1
+; CHECK: tsr.  0
+}
+
+declare i32 @llvm.ppc.tendall()
+declare i32 @llvm.ppc.tresume()
+declare i32 @llvm.ppc.tsuspend()
+
+
+define void @test5(i64 %v) {
+entry:
+  tail call void @llvm.ppc.set.texasr(i64 %v)
+  tail call void @llvm.ppc.set.texasru(i64 %v)
+  tail call void @llvm.ppc.set.tfhar(i64 %v)
+  tail call void @llvm.ppc.set.tfiar(i64 %v)
+  ret void
+; CHECK-LABEL: @test5
+; CHECK: mtspr 130, [[REG1:[0-9]+]]
+; CHECK: mtspr 131, [[REG2:[0-9]+]]
+; CHECK: mtspr 128, [[REG3:[0-9]+]]
+; CHECK: mtspr 129, [[REG4:[0-9]+]]
+}
+
+define i64 @test6() {
+entry:
+  %0 = tail call i64 @llvm.ppc.get.texasr()
+  ret i64 %0
+; CHECK-LABEL: @test6
+; CHECK: mfspr [[REG1:[0-9]+]], 130
+}
+
+define i64 @test7() {
+entry:
+  %0 = tail call i64 @llvm.ppc.get.texasru()
+  ret i64 %0
+; CHECK-LABEL: @test7
+; CHECK: mfspr [[REG1:[0-9]+]], 131
+}
+
+define i64 @test8() {
+entry:
+  %0 = tail call i64 @llvm.ppc.get.tfhar()
+  ret i64 %0
+; CHECK-LABEL: @test8
+; CHECK: mfspr [[REG1:[0-9]+]], 128
+}
+
+define i64 @test9() {
+entry:
+  %0 = tail call i64 @llvm.ppc.get.tfiar()
+  ret i64 %0
+; CHECK-LABEL: @test9
+; CHECK: mfspr [[REG1:[0-9]+]], 129
+}
+
+declare void @llvm.ppc.set.texasr(i64)
+declare void @llvm.ppc.set.texasru(i64)
+declare void @llvm.ppc.set.tfhar(i64)
+declare void @llvm.ppc.set.tfiar(i64)
+declare i64 @llvm.ppc.get.texasr()
+declare i64 @llvm.ppc.get.texasru()
+declare i64 @llvm.ppc.get.tfhar()
+declare i64 @llvm.ppc.get.tfiar()
diff --git a/test/CodeGen/PowerPC/i64_fp_round.ll b/test/CodeGen/PowerPC/i64_fp_round.ll
index 5770d788caf7..2530b8a92825 100644
--- a/test/CodeGen/PowerPC/i64_fp_round.ll
+++ b/test/CodeGen/PowerPC/i64_fp_round.ll
@@ -14,7 +14,7 @@ entry:
 
 ; CHECK: sradi [[REG1:[0-9]+]], 3, 53
 ; CHECK: addi [[REG2:[0-9]+]], [[REG1]], 1
-; CHECK: cmpldi 0, [[REG2]], 1
+; CHECK: cmpldi [[REG2]], 1
 ; CHECK: isel [[REG3:[0-9]+]], {{[0-9]+}}, 3, 1
 ; CHECK: std [[REG3]], -{{[0-9]+}}(1)
 
diff --git a/test/CodeGen/PowerPC/ia-mem-r0.ll b/test/CodeGen/PowerPC/ia-mem-r0.ll
index 4ab17edc5b10..a007fc1aa631 100644
--- a/test/CodeGen/PowerPC/ia-mem-r0.ll
+++ b/test/CodeGen/PowerPC/ia-mem-r0.ll
@@ -16,78 +16,78 @@ define void @test1({ i8*, void (i8*, i8*)* } %fn_arg) {
   %1 = bitcast [18 x i64]* %regs to i64*
   call void asm sideeffect "std  14, $0", "=*m"(i64* %1)
   %2 = bitcast [18 x i64]* %regs to i8*
-  %3 = getelementptr i8* %2, i32 8
+  %3 = getelementptr i8, i8* %2, i32 8
   %4 = bitcast i8* %3 to i64*
   call void asm sideeffect "std  15, $0", "=*m"(i64* %4)
   %5 = bitcast [18 x i64]* %regs to i8*
-  %6 = getelementptr i8* %5, i32 16
+  %6 = getelementptr i8, i8* %5, i32 16
   %7 = bitcast i8* %6 to i64*
   call void asm sideeffect "std  16, $0", "=*m"(i64* %7)
   %8 = bitcast [18 x i64]* %regs to i8*
-  %9 = getelementptr i8* %8, i32 24
+  %9 = getelementptr i8, i8* %8, i32 24
   %10 = bitcast i8* %9 to i64*
   call void asm sideeffect "std  17, $0", "=*m"(i64* %10)
   %11 = bitcast [18 x i64]* %regs to i8*
-  %12 = getelementptr i8* %11, i32 32
+  %12 = getelementptr i8, i8* %11, i32 32
   %13 = bitcast i8* %12 to i64*
   call void asm sideeffect "std  18, $0", "=*m"(i64* %13)
   %14 = bitcast [18 x i64]* %regs to i8*
-  %15 = getelementptr i8* %14, i32 40
+  %15 = getelementptr i8, i8* %14, i32 40
   %16 = bitcast i8* %15 to i64*
   call void asm sideeffect "std  19, $0", "=*m"(i64* %16)
   %17 = bitcast [18 x i64]* %regs to i8*
-  %18 = getelementptr i8* %17, i32 48
+  %18 = getelementptr i8, i8* %17, i32 48
   %19 = bitcast i8* %18 to i64*
   call void asm sideeffect "std  20, $0", "=*m"(i64* %19)
   %20 = bitcast [18 x i64]* %regs to i8*
-  %21 = getelementptr i8* %20, i32 56
+  %21 = getelementptr i8, i8* %20, i32 56
   %22 = bitcast i8* %21 to i64*
   call void asm sideeffect "std  21, $0", "=*m"(i64* %22)
   %23 = bitcast [18 x i64]* %regs to i8*
-  %24 = getelementptr i8* %23, i32 64
+  %24 = getelementptr i8, i8* %23, i32 64
   %25 = bitcast i8* %24 to i64*
   call void asm sideeffect "std  22, $0", "=*m"(i64* %25)
   %26 = bitcast [18 x i64]* %regs to i8*
-  %27 = getelementptr i8* %26, i32 72
+  %27 = getelementptr i8, i8* %26, i32 72
   %28 = bitcast i8* %27 to i64*
   call void asm sideeffect "std  23, $0", "=*m"(i64* %28)
   %29 = bitcast [18 x i64]* %regs to i8*
-  %30 = getelementptr i8* %29, i32 80
+  %30 = getelementptr i8, i8* %29, i32 80
   %31 = bitcast i8* %30 to i64*
   call void asm sideeffect "std  24, $0", "=*m"(i64* %31)
   %32 = bitcast [18 x i64]* %regs to i8*
-  %33 = getelementptr i8* %32, i32 88
+  %33 = getelementptr i8, i8* %32, i32 88
   %34 = bitcast i8* %33 to i64*
   call void asm sideeffect "std  25, $0", "=*m"(i64* %34)
   %35 = bitcast [18 x i64]* %regs to i8*
-  %36 = getelementptr i8* %35, i32 96
+  %36 = getelementptr i8, i8* %35, i32 96
   %37 = bitcast i8* %36 to i64*
   call void asm sideeffect "std  26, $0", "=*m"(i64* %37)
   %38 = bitcast [18 x i64]* %regs to i8*
-  %39 = getelementptr i8* %38, i32 104
+  %39 = getelementptr i8, i8* %38, i32 104
   %40 = bitcast i8* %39 to i64*
   call void asm sideeffect "std  27, $0", "=*m"(i64* %40)
   %41 = bitcast [18 x i64]* %regs to i8*
-  %42 = getelementptr i8* %41, i32 112
+  %42 = getelementptr i8, i8* %41, i32 112
   %43 = bitcast i8* %42 to i64*
   call void asm sideeffect "std  28, $0", "=*m"(i64* %43)
   %44 = bitcast [18 x i64]* %regs to i8*
-  %45 = getelementptr i8* %44, i32 120
+  %45 = getelementptr i8, i8* %44, i32 120
   %46 = bitcast i8* %45 to i64*
   call void asm sideeffect "std  29, $0", "=*m"(i64* %46)
   %47 = bitcast [18 x i64]* %regs to i8*
-  %48 = getelementptr i8* %47, i32 128
+  %48 = getelementptr i8, i8* %47, i32 128
   %49 = bitcast i8* %48 to i64*
   call void asm sideeffect "std  30, $0", "=*m"(i64* %49)
   %50 = bitcast [18 x i64]* %regs to i8*
-  %51 = getelementptr i8* %50, i32 136
+  %51 = getelementptr i8, i8* %50, i32 136
   %52 = bitcast i8* %51 to i64*
   call void asm sideeffect "std  31, $0", "=*m"(i64* %52)
-  %53 = getelementptr { i8*, void (i8*, i8*)* }* %fn, i32 0, i32 1
-  %.funcptr = load void (i8*, i8*)** %53
-  %54 = getelementptr { i8*, void (i8*, i8*)* }* %fn, i32 0, i32 0
-  %.ptr = load i8** %54
-  %55 = load i8** %sp
+  %53 = getelementptr { i8*, void (i8*, i8*)* }, { i8*, void (i8*, i8*)* }* %fn, i32 0, i32 1
+  %.funcptr = load void (i8*, i8*)*, void (i8*, i8*)** %53
+  %54 = getelementptr { i8*, void (i8*, i8*)* }, { i8*, void (i8*, i8*)* }* %fn, i32 0, i32 0
+  %.ptr = load i8*, i8** %54
+  %55 = load i8*, i8** %sp
   call void %.funcptr(i8* %.ptr, i8* %55)
   ret void
 }
diff --git a/test/CodeGen/PowerPC/indexed-load.ll b/test/CodeGen/PowerPC/indexed-load.ll
index 59fc058c9414..ce386d76cf17 100644
--- a/test/CodeGen/PowerPC/indexed-load.ll
+++ b/test/CodeGen/PowerPC/indexed-load.ll
@@ -13,9 +13,9 @@ target triple = "powerpc64le-unknown-linux-gnu"
 ; CHECK-NOT: stwx {{[0-9]+}}, {{[0-9]+}}, 64
 define void @f(%class.test* %this) {
 entry:
-  %Subminor.i.i = getelementptr inbounds %class.test* %this, i64 0, i32 1
+  %Subminor.i.i = getelementptr inbounds %class.test, %class.test* %this, i64 0, i32 1
   %0 = bitcast [5 x i8]* %Subminor.i.i to i40*
-  %bf.load2.i.i = load i40* %0, align 4
+  %bf.load2.i.i = load i40, i40* %0, align 4
   %bf.clear7.i.i = and i40 %bf.load2.i.i, -8589934592
   store i40 %bf.clear7.i.i, i40* %0, align 4
   ret void
diff --git a/test/CodeGen/PowerPC/indirectbr.ll b/test/CodeGen/PowerPC/indirectbr.ll
index fd06fd9b7f46..d1e03ca7773a 100644
--- a/test/CodeGen/PowerPC/indirectbr.ll
+++ b/test/CodeGen/PowerPC/indirectbr.ll
@@ -10,7 +10,7 @@ define internal i32 @foo(i32 %i) nounwind {
 ; STATIC-LABEL: foo:
 ; PPC64-LABEL: foo:
 entry:
-  %0 = load i8** @nextaddr, align 4               ; <i8*> [#uses=2]
+  %0 = load i8*, i8** @nextaddr, align 4               ; <i8*> [#uses=2]
   %1 = icmp eq i8* %0, null                       ; <i1> [#uses=1]
   br i1 %1, label %bb3, label %bb2
 
@@ -37,8 +37,8 @@ bb2:                                              ; preds = %entry, %bb3
   indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
 
 bb3:                                              ; preds = %entry
-  %2 = getelementptr inbounds [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1]
-  %gotovar.4.0.pre = load i8** %2, align 4        ; <i8*> [#uses=1]
+  %2 = getelementptr inbounds [5 x i8*], [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1]
+  %gotovar.4.0.pre = load i8*, i8** %2, align 4        ; <i8*> [#uses=1]
   br label %bb2
 
 L5:                                               ; preds = %bb2
diff --git a/test/CodeGen/PowerPC/inlineasm-i64-reg.ll b/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
index 4d8e704f07a0..05f2a197cd51 100644
--- a/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
+++ b/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
@@ -19,18 +19,18 @@ entry:
   store %struct.BG_CoordinateMapping_t* %map, %struct.BG_CoordinateMapping_t** %map.addr, align 8
   store i64* %numentries, i64** %numentries.addr, align 8
   store i64 1055, i64* %r0, align 8
-  %0 = load i64* %mapsize.addr, align 8
+  %0 = load i64, i64* %mapsize.addr, align 8
   store i64 %0, i64* %r3, align 8
-  %1 = load %struct.BG_CoordinateMapping_t** %map.addr, align 8
+  %1 = load %struct.BG_CoordinateMapping_t*, %struct.BG_CoordinateMapping_t** %map.addr, align 8
   %2 = ptrtoint %struct.BG_CoordinateMapping_t* %1 to i64
   store i64 %2, i64* %r4, align 8
-  %3 = load i64** %numentries.addr, align 8
+  %3 = load i64*, i64** %numentries.addr, align 8
   %4 = ptrtoint i64* %3 to i64
   store i64 %4, i64* %r5, align 8
-  %5 = load i64* %r0, align 8
-  %6 = load i64* %r3, align 8
-  %7 = load i64* %r4, align 8
-  %8 = load i64* %r5, align 8
+  %5 = load i64, i64* %r0, align 8
+  %6 = load i64, i64* %r3, align 8
+  %7 = load i64, i64* %r4, align 8
+  %8 = load i64, i64* %r5, align 8
   %9 = call { i64, i64, i64, i64 } asm sideeffect "sc", "={r0},={r3},={r4},={r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 %5, i64 %6, i64 %7, i64 %8) #1, !srcloc !0
 
 ; CHECK-LABEL: @Kernel_RanksToCoords
@@ -52,9 +52,9 @@ entry:
   store i64 %asmresult1, i64* %r3, align 8
   store i64 %asmresult2, i64* %r4, align 8
   store i64 %asmresult3, i64* %r5, align 8
-  %10 = load i64* %r3, align 8
+  %10 = load i64, i64* %r3, align 8
   store i64 %10, i64* %tmp
-  %11 = load i64* %tmp
+  %11 = load i64, i64* %tmp
   %conv = trunc i64 %11 to i32
   ret i32 %conv
 }
@@ -87,7 +87,7 @@ entry:
 
 if.then:                                          ; preds = %entry
   call void @mtrace()
-  %.pre = load i32* %argc.addr, align 4
+  %.pre = load i32, i32* %argc.addr, align 4
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
diff --git a/test/CodeGen/PowerPC/isel-rc-nox0.ll b/test/CodeGen/PowerPC/isel-rc-nox0.ll
index ac99aa408bdd..7475e12c4477 100644
--- a/test/CodeGen/PowerPC/isel-rc-nox0.ll
+++ b/test/CodeGen/PowerPC/isel-rc-nox0.ll
@@ -17,12 +17,12 @@ for.cond1.preheader.i:                            ; preds = %for.cond1.preheader
 
 crc32_gentab.exit:                                ; preds = %for.cond1.preheader.i
   %tobool.i19.i.i = icmp eq i32 undef, 0
-  %retval.0.i.i.i = select i1 %tobool.i19.i.i, i32* getelementptr inbounds ([1 x [9 x i32]]* @g_62, i64 0, i64 0, i64 6), i32* getelementptr inbounds ([1 x [9 x i32]]* @g_62, i64 0, i64 0, i64 8)
+  %retval.0.i.i.i = select i1 %tobool.i19.i.i, i32* getelementptr inbounds ([1 x [9 x i32]], [1 x [9 x i32]]* @g_62, i64 0, i64 0, i64 6), i32* getelementptr inbounds ([1 x [9 x i32]], [1 x [9 x i32]]* @g_62, i64 0, i64 0, i64 8)
   br label %for.cond1.preheader.i2961.i
 
 for.cond1.preheader.i2961.i:                      ; preds = %for.inc44.i2977.i, %crc32_gentab.exit
   call void @llvm.memset.p0i8.i64(i8* bitcast ([1 x [9 x i32]]* @g_62 to i8*), i8 -1, i64 36, i32 4, i1 false) #1
-  %0 = load i32* %retval.0.i.i.i, align 4
+  %0 = load i32, i32* %retval.0.i.i.i, align 4
   %tobool.i2967.i = icmp eq i32 %0, 0
   br label %for.body21.i2968.i
 
diff --git a/test/CodeGen/PowerPC/lbz-from-ld-shift.ll b/test/CodeGen/PowerPC/lbz-from-ld-shift.ll
index 3eacd6a45fb4..7696b84708d8 100644
--- a/test/CodeGen/PowerPC/lbz-from-ld-shift.ll
+++ b/test/CodeGen/PowerPC/lbz-from-ld-shift.ll
@@ -5,7 +5,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 ; Function Attrs: nounwind readonly
 define signext i32 @test(i32* nocapture readonly %P) #0 {
 entry:
-  %0 = load i32* %P, align 4
+  %0 = load i32, i32* %P, align 4
   %shr = lshr i32 %0, 24
   ret i32 %shr
 
diff --git a/test/CodeGen/PowerPC/lbzux.ll b/test/CodeGen/PowerPC/lbzux.ll
index f3158b32f390..4bd9cb6ab18a 100644
--- a/test/CodeGen/PowerPC/lbzux.ll
+++ b/test/CodeGen/PowerPC/lbzux.ll
@@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define fastcc void @allocateSpace(i1 %cond1, i1 %cond2) nounwind {
 entry:
-  %0 = load i8** undef, align 8
+  %0 = load i8*, i8** undef, align 8
   br i1 undef, label %return, label %lor.lhs.false
 
 lor.lhs.false:                                    ; preds = %entry
@@ -18,7 +18,7 @@ if.then15:                                        ; preds = %if.end7
 
 while.cond:                                       ; preds = %while.body, %if.then15
   %idxprom17 = sext i32 0 to i64
-  %arrayidx18 = getelementptr inbounds i8* %0, i64 %idxprom17
+  %arrayidx18 = getelementptr inbounds i8, i8* %0, i64 %idxprom17
   %or = or i32 undef, undef
   br i1 %cond1, label %if.end71, label %while.body
 
@@ -27,10 +27,10 @@ while.body:                                       ; preds = %while.cond
 
 if.then45:                                        ; preds = %while.body
   %idxprom48139 = zext i32 %or to i64
-  %arrayidx49 = getelementptr inbounds i8* %0, i64 %idxprom48139
+  %arrayidx49 = getelementptr inbounds i8, i8* %0, i64 %idxprom48139
   %1 = bitcast i8* %arrayidx49 to i16*
   %2 = bitcast i8* %arrayidx18 to i16*
-  %3 = load i16* %1, align 1
+  %3 = load i16, i16* %1, align 1
   store i16 %3, i16* %2, align 1
   br label %return
 
diff --git a/test/CodeGen/PowerPC/ld-st-upd.ll b/test/CodeGen/PowerPC/ld-st-upd.ll
index 24f31aca05ad..be0c94a54fe0 100644
--- a/test/CodeGen/PowerPC/ld-st-upd.ll
+++ b/test/CodeGen/PowerPC/ld-st-upd.ll
@@ -4,8 +4,8 @@ target triple = "powerpc-unknown-linux-gnu"
 
 ; Function Attrs: nounwind
 define i32* @test4(i32* readonly %X, i32* nocapture %dest) #0 {
-  %Y = getelementptr i32* %X, i64 4
-  %A = load i32* %Y, align 4
+  %Y = getelementptr i32, i32* %X, i64 4
+  %A = load i32, i32* %Y, align 4
   store i32 %A, i32* %dest, align 4
   ret i32* %Y
 
diff --git a/test/CodeGen/PowerPC/ldtoc-inv.ll b/test/CodeGen/PowerPC/ldtoc-inv.ll
new file mode 100644
index 000000000000..07a1686cc704
--- /dev/null
+++ b/test/CodeGen/PowerPC/ldtoc-inv.ll
@@ -0,0 +1,39 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+@phasor = external constant [4096 x i32]
+
+; Function Attrs: nounwind
+define void @test(i32* nocapture %out, i32 zeroext %step_size) #0 {
+entry:
+  %shl = shl i32 %step_size, 2
+  %idxprom = zext i32 %shl to i64
+  br label %for.body
+
+; Make sure that the TOC load has been hoisted out of the loop.
+; CHECK-LABEL: @test
+; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc@l
+; CHECK: %for.body
+; CHECK: blr
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %0 = trunc i64 %indvars.iv to i32
+  %shl1 = shl i32 %0, %step_size
+  %idxprom2 = sext i32 %shl1 to i64
+  %arrayidx.sum = add nsw i64 %idxprom2, %idxprom
+  %arrayidx3 = getelementptr inbounds [4096 x i32], [4096 x i32]* @phasor, i64 0, i64 %arrayidx.sum
+  %1 = load i32, i32* %arrayidx3, align 4
+  %arrayidx5 = getelementptr inbounds i32, i32* %out, i64 %indvars.iv
+  store i32 %1, i32* %arrayidx5, align 4
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 4
+  %cmp = icmp slt i64 %indvars.iv.next, 1020
+  br i1 %cmp, label %for.body, label %for.end
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
+
+attributes #0 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/lha.ll b/test/CodeGen/PowerPC/lha.ll
index 3a100c1aae6d..c5c5f5905f67 100644
--- a/test/CodeGen/PowerPC/lha.ll
+++ b/test/CodeGen/PowerPC/lha.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=ppc32 | grep lha
 
 define i32 @test(i16* %a) {
-        %tmp.1 = load i16* %a           ; <i16> [#uses=1]
+        %tmp.1 = load i16, i16* %a           ; <i16> [#uses=1]
         %tmp.2 = sext i16 %tmp.1 to i32         ; <i32> [#uses=1]
         ret i32 %tmp.2
 }
diff --git a/test/CodeGen/PowerPC/load-constant-addr.ll b/test/CodeGen/PowerPC/load-constant-addr.ll
index f1d061c1ad5a..783443008cae 100644
--- a/test/CodeGen/PowerPC/load-constant-addr.ll
+++ b/test/CodeGen/PowerPC/load-constant-addr.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -march=ppc32 | not grep ori
 
 define float @test() {
-        %tmp.i = load float* inttoptr (i32 186018016 to float*)         ; <float> [#uses=1]
+        %tmp.i = load float, float* inttoptr (i32 186018016 to float*)         ; <float> [#uses=1]
         ret float %tmp.i
 }
 
diff --git a/test/CodeGen/PowerPC/load-shift-combine.ll b/test/CodeGen/PowerPC/load-shift-combine.ll
index a5d1224864a6..8d1f8146db95 100644
--- a/test/CodeGen/PowerPC/load-shift-combine.ll
+++ b/test/CodeGen/PowerPC/load-shift-combine.ll
@@ -16,19 +16,19 @@
 define void @test1847() nounwind {
 entry:
   %j = alloca i32, align 4
-  %0 = load i64* getelementptr inbounds (%struct.Info* @info, i32 0, i32 8), align 8
-  %1 = load i32* @fails, align 4
-  %bf.load1 = load i96* bitcast (%struct.S1847* getelementptr inbounds ([5 x %struct.S1847]* @a1847, i32 0, i64 2) to i96*), align 8
+  %0 = load i64, i64* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 8), align 8
+  %1 = load i32, i32* @fails, align 4
+  %bf.load1 = load i96, i96* bitcast (%struct.S1847* getelementptr inbounds ([5 x %struct.S1847], [5 x %struct.S1847]* @a1847, i32 0, i64 2) to i96*), align 8
   %bf.clear2 = and i96 %bf.load1, 302231454903657293676543
   %bf.set3 = or i96 %bf.clear2, -38383394772764476296921088
-  store i96 %bf.set3, i96* bitcast (%struct.S1847* getelementptr inbounds ([5 x %struct.S1847]* @a1847, i32 0, i64 2) to i96*), align 8
-  %2 = load i32* %j, align 4
-  %3 = load i32* %j, align 4
+  store i96 %bf.set3, i96* bitcast (%struct.S1847* getelementptr inbounds ([5 x %struct.S1847], [5 x %struct.S1847]* @a1847, i32 0, i64 2) to i96*), align 8
+  %2 = load i32, i32* %j, align 4
+  %3 = load i32, i32* %j, align 4
   %inc11 = add nsw i32 %3, 1
   store i32 %inc11, i32* %j, align 4
-  %bf.load15 = load i96* bitcast (%struct.S1847* getelementptr inbounds ([5 x %struct.S1847]* @a1847, i32 0, i64 2) to i96*), align 8
+  %bf.load15 = load i96, i96* bitcast (%struct.S1847* getelementptr inbounds ([5 x %struct.S1847], [5 x %struct.S1847]* @a1847, i32 0, i64 2) to i96*), align 8
   %bf.clear16 = and i96 %bf.load15, -18446744069414584321
   %bf.set17 = or i96 %bf.clear16, 18446743532543672320
-  store i96 %bf.set17, i96* bitcast (%struct.S1847* getelementptr inbounds ([5 x %struct.S1847]* @a1847, i32 0, i64 2) to i96*), align 8
+  store i96 %bf.set17, i96* bitcast (%struct.S1847* getelementptr inbounds ([5 x %struct.S1847], [5 x %struct.S1847]* @a1847, i32 0, i64 2) to i96*), align 8
   ret void
 }
diff --git a/test/CodeGen/PowerPC/long-compare.ll b/test/CodeGen/PowerPC/long-compare.ll
index 915595f6dbac..e53356a5ddf2 100644
--- a/test/CodeGen/PowerPC/long-compare.ll
+++ b/test/CodeGen/PowerPC/long-compare.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ppc32 | grep cntlzw 
+; RUN: llc < %s -march=ppc32 | grep cntlz
 ; RUN: llc < %s -march=ppc32 | not grep xori 
 ; RUN: llc < %s -march=ppc32 | not grep "li "
 ; RUN: llc < %s -march=ppc32 | not grep "mr "
diff --git a/test/CodeGen/PowerPC/loop-data-prefetch-inner.ll b/test/CodeGen/PowerPC/loop-data-prefetch-inner.ll
new file mode 100644
index 000000000000..adcc7b90bc48
--- /dev/null
+++ b/test/CodeGen/PowerPC/loop-data-prefetch-inner.ll
@@ -0,0 +1,66 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+; Function Attrs: nounwind
+define void @foo(double* %x, double* nocapture readonly %y) #0 {
+entry:
+  %scevgep = getelementptr double, double* %x, i64 1599
+  %scevgep20 = getelementptr double, double* %y, i64 1599
+  br label %vector.memcheck
+
+vector.memcheck:                                  ; preds = %for.end, %entry
+  %j.015 = phi i32 [ 0, %entry ], [ %inc7, %for.end ]
+  %bound0 = icmp uge double* %scevgep20, %x
+  %bound1 = icmp uge double* %scevgep, %y
+  %memcheck.conflict = and i1 %bound0, %bound1
+  br i1 %memcheck.conflict, label %middle.block, label %vector.body
+
+vector.body:                                      ; preds = %vector.memcheck, %vector.body
+  %index = phi i64 [ %index.next, %vector.body ], [ 0, %vector.memcheck ]
+  %0 = getelementptr inbounds double, double* %y, i64 %index
+  %1 = bitcast double* %0 to <4 x double>*
+  %wide.load = load <4 x double>, <4 x double>* %1, align 8
+  %2 = fadd <4 x double> %wide.load, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>
+  %3 = getelementptr inbounds double, double* %x, i64 %index
+  %4 = bitcast double* %3 to <4 x double>*
+  store <4 x double> %2, <4 x double>* %4, align 8
+  %index.next = add i64 %index, 4
+  %5 = icmp eq i64 %index.next, 1600
+  br i1 %5, label %middle.block, label %vector.body
+
+middle.block:                                     ; preds = %vector.body, %vector.memcheck
+  %resume.val = phi i1 [ false, %vector.memcheck ], [ true, %vector.body ]
+  %trunc.resume.val = phi i64 [ 0, %vector.memcheck ], [ 1600, %vector.body ]
+  br i1 %resume.val, label %for.end, label %for.body3
+
+for.body3:                                        ; preds = %middle.block, %for.body3
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3 ], [ %trunc.resume.val, %middle.block ]
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %6 = load double, double* %arrayidx, align 8
+  %add = fadd double %6, 1.000000e+00
+  %arrayidx5 = getelementptr inbounds double, double* %x, i64 %indvars.iv
+  store double %add, double* %arrayidx5, align 8
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond = icmp eq i64 %indvars.iv.next, 1600
+  br i1 %exitcond, label %for.end, label %for.body3
+
+for.end:                                          ; preds = %middle.block, %for.body3
+  tail call void @bar(double* %x) #2
+  %inc7 = add nuw nsw i32 %j.015, 1
+  %exitcond16 = icmp eq i32 %inc7, 100
+  br i1 %exitcond16, label %for.end8, label %vector.memcheck
+
+for.end8:                                         ; preds = %for.end
+  ret void
+
+; CHECK-LABEL: @foo
+; CHECK: dcbt
+}
+
+declare void @bar(double*) #1
+
+attributes #0 = { nounwind "target-cpu"="a2q" }
+attributes #1 = { "target-cpu"="a2q" }
+attributes #2 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/loop-data-prefetch.ll b/test/CodeGen/PowerPC/loop-data-prefetch.ll
new file mode 100644
index 000000000000..59b74e67251b
--- /dev/null
+++ b/test/CodeGen/PowerPC/loop-data-prefetch.ll
@@ -0,0 +1,29 @@
+; RUN: llc -mcpu=a2 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+; Function Attrs: nounwind
+define void @foo(double* nocapture %a, double* nocapture readonly %b) #0 {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %arrayidx = getelementptr inbounds double, double* %b, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
+  %add = fadd double %0, 1.000000e+00
+  %arrayidx2 = getelementptr inbounds double, double* %a, i64 %indvars.iv
+  store double %add, double* %arrayidx2, align 8
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond = icmp eq i64 %indvars.iv.next, 1600
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret void
+
+; CHECK-LABEL: @foo
+; CHECK: dcbt
+}
+
+attributes #0 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/loop-prep-all.ll b/test/CodeGen/PowerPC/loop-prep-all.ll
new file mode 100644
index 000000000000..895daff63ad9
--- /dev/null
+++ b/test/CodeGen/PowerPC/loop-prep-all.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-bgq-linux < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BGQ
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define void @foo(double* nocapture %x, double* nocapture readonly %y) #0 {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
+  %add = fadd double %0, 1.000000e+00
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
+  store double %add, double* %arrayidx2, align 8
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond19 = icmp eq i64 %indvars.iv.next, 1600
+  br i1 %exitcond19, label %for.body7, label %for.body
+
+; CHECK-LABEL: @foo
+
+; CHECK-BGQ-DAG: dcbt 4, 5
+; CHECK-DAG: lfdu [[REG1:[0-9]+]], 8({{[0-9]+}})
+; CHECK-DAG: fadd [[REG2:[0-9]+]], [[REG1]], 0
+; CHECK-DAG: stfdu [[REG2]], 8({{[0-9]+}})
+; CHECK: bdnz
+
+; CHECK: blr
+
+for.cond.cleanup6:                                ; preds = %for.body7
+  ret void
+
+for.body7:                                        ; preds = %for.body, %for.body7
+  %i3.017 = phi i32 [ %inc9, %for.body7 ], [ 0, %for.body ]
+  tail call void bitcast (void (...)* @bar to void ()*)() #2
+  %inc9 = add nuw nsw i32 %i3.017, 1
+  %exitcond = icmp eq i32 %inc9, 1024
+  br i1 %exitcond, label %for.cond.cleanup6, label %for.body7
+}
+
+declare void @bar(...) #1
+
+attributes #0 = { nounwind "target-cpu"="a2q" }
+attributes #1 = { "target-cpu"="a2q" }
+attributes #2 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/lsa.ll b/test/CodeGen/PowerPC/lsa.ll
index a892a4cf4140..f4d61c014dd9 100644
--- a/test/CodeGen/PowerPC/lsa.ll
+++ b/test/CodeGen/PowerPC/lsa.ll
@@ -13,13 +13,13 @@ entry:
   call void @llvm.lifetime.start(i64 32800, i8* %1) #0
   %2 = bitcast [8200 x i32]* %q to i8*
   call void @llvm.lifetime.start(i64 32800, i8* %2) #0
-  %arraydecay = getelementptr inbounds [8200 x i32]* %q, i64 0, i64 0
-  %arraydecay1 = getelementptr inbounds [8200 x i32]* %v, i64 0, i64 0
-  %arraydecay2 = getelementptr inbounds [8200 x i32]* %w, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [8200 x i32], [8200 x i32]* %q, i64 0, i64 0
+  %arraydecay1 = getelementptr inbounds [8200 x i32], [8200 x i32]* %v, i64 0, i64 0
+  %arraydecay2 = getelementptr inbounds [8200 x i32], [8200 x i32]* %w, i64 0, i64 0
   call void @bar(i32* %arraydecay, i32* %arraydecay1, i32* %arraydecay2) #0
-  %3 = load i32* %arraydecay2, align 4
-  %arrayidx3 = getelementptr inbounds [8200 x i32]* %w, i64 0, i64 1
-  %4 = load i32* %arrayidx3, align 4
+  %3 = load i32, i32* %arraydecay2, align 4
+  %arrayidx3 = getelementptr inbounds [8200 x i32], [8200 x i32]* %w, i64 0, i64 1
+  %4 = load i32, i32* %arrayidx3, align 4
 
 ; CHECK: @foo
 ; CHECK-NOT: lwzx
diff --git a/test/CodeGen/PowerPC/lsr-postinc-pos.ll b/test/CodeGen/PowerPC/lsr-postinc-pos.ll
index 42472c58fe8b..7831df154606 100644
--- a/test/CodeGen/PowerPC/lsr-postinc-pos.ll
+++ b/test/CodeGen/PowerPC/lsr-postinc-pos.ll
@@ -3,8 +3,8 @@
 ; The icmp is a post-inc use, and the increment is in %bb11, but the
 ; scevgep needs to be inserted in %bb so that it is dominated by %t.
 
-; CHECK: %t = load i8** undef
-; CHECK: %scevgep = getelementptr i8* %t, i32 %lsr.iv.next
+; CHECK: %t = load i8*, i8** undef
+; CHECK: %scevgep = getelementptr i8, i8* %t, i32 %lsr.iv.next
 ; CHECK: %c1 = icmp ult i8* %scevgep, undef
 
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
@@ -21,8 +21,8 @@ bb11:
   br i1 %c0, label %bb13, label %bb
 
 bb:
-  %t = load i8** undef, align 16                ; <i8*> [#uses=1]
-  %p = getelementptr i8* %t, i32 %ii ; <i8*> [#uses=1]
+  %t = load i8*, i8** undef, align 16                ; <i8*> [#uses=1]
+  %p = getelementptr i8, i8* %t, i32 %ii ; <i8*> [#uses=1]
   %c1 = icmp ult i8* %p, undef          ; <i1> [#uses=1]
   %i.next = add i32 %i, 1                        ; <i32> [#uses=1]
   br i1 %c1, label %bb11, label %bb13
diff --git a/test/CodeGen/PowerPC/mask64.ll b/test/CodeGen/PowerPC/mask64.ll
index 139621af1f22..600cecd3fe7b 100644
--- a/test/CodeGen/PowerPC/mask64.ll
+++ b/test/CodeGen/PowerPC/mask64.ll
@@ -9,8 +9,8 @@ entry:
 	br i1 false, label %bb16, label %bb49
 
 bb16:		; preds = %entry
-	%tmp19 = load i8** null, align 1		; <i8*> [#uses=1]
-	%tmp21 = load i8* %tmp19, align 1		; <i8> [#uses=1]
+	%tmp19 = load i8*, i8** null, align 1		; <i8*> [#uses=1]
+	%tmp21 = load i8, i8* %tmp19, align 1		; <i8> [#uses=1]
 	switch i8 %tmp21, label %bb49 [
 		 i8 0, label %bb45
 		 i8 1, label %bb34
diff --git a/test/CodeGen/PowerPC/mature-mc-support.ll b/test/CodeGen/PowerPC/mature-mc-support.ll
index 7c83e184a6f8..aa387f6e2666 100644
--- a/test/CodeGen/PowerPC/mature-mc-support.ll
+++ b/test/CodeGen/PowerPC/mature-mc-support.ll
@@ -10,6 +10,10 @@
 ; RUN: not llc -march=ppc32 -filetype=obj < %s > /dev/null 2> %t2
 ; RUN: FileCheck %s < %t2
 
+; Test that we don't try to produce COFF for ppc.
+; RUN: not llc -mtriple=powerpc-mingw32 -filetype=obj < %s > /dev/null 2> %t2
+; RUN: FileCheck %s < %t2
+
 ; SKIP: not llc -march=ppc64 < %s > /dev/null 2> %t3
 ; SKIP: FileCheck %s < %t3
 
diff --git a/test/CodeGen/PowerPC/mcm-1.ll b/test/CodeGen/PowerPC/mcm-1.ll
index 4e31550c40d4..7ef4a8e957e6 100644
--- a/test/CodeGen/PowerPC/mcm-1.ll
+++ b/test/CodeGen/PowerPC/mcm-1.ll
@@ -11,7 +11,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i32 @test_external() nounwind {
 entry:
-  %0 = load i32* @ei, align 4
+  %0 = load i32, i32* @ei, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @ei, align 4
   ret i32 %0
diff --git a/test/CodeGen/PowerPC/mcm-10.ll b/test/CodeGen/PowerPC/mcm-10.ll
index 9565ebc780bf..affa249e32b5 100644
--- a/test/CodeGen/PowerPC/mcm-10.ll
+++ b/test/CodeGen/PowerPC/mcm-10.ll
@@ -10,7 +10,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i32 @test_fn_static() nounwind {
 entry:
-  %0 = load i32* @test_fn_static.si, align 4
+  %0 = load i32, i32* @test_fn_static.si, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @test_fn_static.si, align 4
   ret i32 %0
diff --git a/test/CodeGen/PowerPC/mcm-11.ll b/test/CodeGen/PowerPC/mcm-11.ll
index 033045c74c8a..457c60afb57e 100644
--- a/test/CodeGen/PowerPC/mcm-11.ll
+++ b/test/CodeGen/PowerPC/mcm-11.ll
@@ -10,7 +10,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i32 @test_file_static() nounwind {
 entry:
-  %0 = load i32* @gi, align 4
+  %0 = load i32, i32* @gi, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @gi, align 4
   ret i32 %0
diff --git a/test/CodeGen/PowerPC/mcm-2.ll b/test/CodeGen/PowerPC/mcm-2.ll
index 811600ecdbf6..03ce1c65851e 100644
--- a/test/CodeGen/PowerPC/mcm-2.ll
+++ b/test/CodeGen/PowerPC/mcm-2.ll
@@ -11,7 +11,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i32 @test_fn_static() nounwind {
 entry:
-  %0 = load i32* @test_fn_static.si, align 4
+  %0 = load i32, i32* @test_fn_static.si, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @test_fn_static.si, align 4
   ret i32 %0
diff --git a/test/CodeGen/PowerPC/mcm-3.ll b/test/CodeGen/PowerPC/mcm-3.ll
index b6d681d580ad..40188bcb5a0b 100644
--- a/test/CodeGen/PowerPC/mcm-3.ll
+++ b/test/CodeGen/PowerPC/mcm-3.ll
@@ -11,7 +11,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i32 @test_file_static() nounwind {
 entry:
-  %0 = load i32* @gi, align 4
+  %0 = load i32, i32* @gi, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @gi, align 4
   ret i32 %0
diff --git a/test/CodeGen/PowerPC/mcm-5.ll b/test/CodeGen/PowerPC/mcm-5.ll
index 92ddecaeb8c8..19adbe5b7d93 100644
--- a/test/CodeGen/PowerPC/mcm-5.ll
+++ b/test/CodeGen/PowerPC/mcm-5.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
-; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -code-model=medium <%s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -code-model=large <%s | FileCheck %s
 
 ; Test correct code generation for medium and large code model
 ; for loading the address of a jump table from the TOC.
@@ -11,7 +11,7 @@ define signext i32 @test_jump_table(i32 signext %i) nounwind {
 entry:
   %i.addr = alloca i32, align 4
   store i32 %i, i32* %i.addr, align 4
-  %0 = load i32* %i.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
   switch i32 %0, label %sw.default [
     i32 3, label %sw.bb
     i32 4, label %sw.bb1
@@ -23,31 +23,31 @@ sw.default:                                       ; preds = %entry
   br label %sw.epilog
 
 sw.bb:                                            ; preds = %entry
-  %1 = load i32* %i.addr, align 4
+  %1 = load i32, i32* %i.addr, align 4
   %mul = mul nsw i32 %1, 7
   store i32 %mul, i32* %i.addr, align 4
   br label %sw.bb1
 
 sw.bb1:                                           ; preds = %entry, %sw.bb
-  %2 = load i32* %i.addr, align 4
+  %2 = load i32, i32* %i.addr, align 4
   %dec = add nsw i32 %2, -1
   store i32 %dec, i32* %i.addr, align 4
   br label %sw.bb2
 
 sw.bb2:                                           ; preds = %entry, %sw.bb1
-  %3 = load i32* %i.addr, align 4
+  %3 = load i32, i32* %i.addr, align 4
   %add = add nsw i32 %3, 3
   store i32 %add, i32* %i.addr, align 4
   br label %sw.bb3
 
 sw.bb3:                                           ; preds = %entry, %sw.bb2
-  %4 = load i32* %i.addr, align 4
+  %4 = load i32, i32* %i.addr, align 4
   %shl = shl i32 %4, 1
   store i32 %shl, i32* %i.addr, align 4
   br label %sw.epilog
 
 sw.epilog:                                        ; preds = %sw.bb3, %sw.default
-  %5 = load i32* %i.addr, align 4
+  %5 = load i32, i32* %i.addr, align 4
   ret i32 %5
 }
 
diff --git a/test/CodeGen/PowerPC/mcm-6.ll b/test/CodeGen/PowerPC/mcm-6.ll
index f7838b4b2527..6a50d1264109 100644
--- a/test/CodeGen/PowerPC/mcm-6.ll
+++ b/test/CodeGen/PowerPC/mcm-6.ll
@@ -11,7 +11,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i32 @test_tentative() nounwind {
 entry:
-  %0 = load i32* @ti, align 4
+  %0 = load i32, i32* @ti, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @ti, align 4
   ret i32 %0
diff --git a/test/CodeGen/PowerPC/mcm-7.ll b/test/CodeGen/PowerPC/mcm-7.ll
index 7caa13bcdcf8..9c8158df77b3 100644
--- a/test/CodeGen/PowerPC/mcm-7.ll
+++ b/test/CodeGen/PowerPC/mcm-7.ll
@@ -11,7 +11,7 @@ define i8* @test_fnaddr() nounwind {
 entry:
   %func = alloca i32 (i32)*, align 8
   store i32 (i32)* @foo, i32 (i32)** %func, align 8
-  %0 = load i32 (i32)** %func, align 8
+  %0 = load i32 (i32)*, i32 (i32)** %func, align 8
   %1 = bitcast i32 (i32)* %0 to i8*
   ret i8* %1
 }
diff --git a/test/CodeGen/PowerPC/mcm-8.ll b/test/CodeGen/PowerPC/mcm-8.ll
index 643548f6b125..b265c77e2d31 100644
--- a/test/CodeGen/PowerPC/mcm-8.ll
+++ b/test/CodeGen/PowerPC/mcm-8.ll
@@ -11,8 +11,8 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i8 @test_avext() nounwind {
 entry:
-  %0 = getelementptr inbounds [13 x i8]* @x, i32 0, i32 0
-  %1 = load i8* %0, align 1
+  %0 = getelementptr inbounds [13 x i8], [13 x i8]* @x, i32 0, i32 0
+  %1 = load i8, i8* %0, align 1
   ret i8 %1
 }
 
diff --git a/test/CodeGen/PowerPC/mcm-9.ll b/test/CodeGen/PowerPC/mcm-9.ll
index 7906b6abea6a..45a4e699a3db 100644
--- a/test/CodeGen/PowerPC/mcm-9.ll
+++ b/test/CodeGen/PowerPC/mcm-9.ll
@@ -11,7 +11,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i32 @test_external() nounwind {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @a, align 4
   ret i32 %0
diff --git a/test/CodeGen/PowerPC/mcm-default.ll b/test/CodeGen/PowerPC/mcm-default.ll
index 8d4ff14118f3..49e6513a7c13 100644
--- a/test/CodeGen/PowerPC/mcm-default.ll
+++ b/test/CodeGen/PowerPC/mcm-default.ll
@@ -10,7 +10,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i32 @test_external() nounwind {
 entry:
-  %0 = load i32* @ei, align 4
+  %0 = load i32, i32* @ei, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @ei, align 4
   ret i32 %0
diff --git a/test/CodeGen/PowerPC/mcm-obj-2.ll b/test/CodeGen/PowerPC/mcm-obj-2.ll
index c42cf0c36ea8..36c58560ebff 100644
--- a/test/CodeGen/PowerPC/mcm-obj-2.ll
+++ b/test/CodeGen/PowerPC/mcm-obj-2.ll
@@ -10,7 +10,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i32 @test_fn_static() nounwind {
 entry:
-  %0 = load i32* @test_fn_static.si, align 4
+  %0 = load i32, i32* @test_fn_static.si, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @test_fn_static.si, align 4
   ret i32 %0
@@ -20,7 +20,7 @@ entry:
 ; accessing function-scoped variable si.
 ;
 ; CHECK: Relocations [
-; CHECK:   Section (2) .rela.text {
+; CHECK:   Section {{.*}} .rela.text {
 ; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]]
 ; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM2]]
 ; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]]
@@ -29,7 +29,7 @@ entry:
 
 define signext i32 @test_file_static() nounwind {
 entry:
-  %0 = load i32* @gi, align 4
+  %0 = load i32, i32* @gi, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @gi, align 4
   ret i32 %0
diff --git a/test/CodeGen/PowerPC/mcm-obj.ll b/test/CodeGen/PowerPC/mcm-obj.ll
index d3d05eb48d32..1ececf84926e 100644
--- a/test/CodeGen/PowerPC/mcm-obj.ll
+++ b/test/CodeGen/PowerPC/mcm-obj.ll
@@ -3,6 +3,12 @@
 ; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \
 ; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE %s
 
+; Run jump table test separately since jump tables aren't generated at -O0.
+; RUN: llc -mcpu=pwr7 -code-model=medium -filetype=obj -fast-isel=false %s -o - | \
+; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM-JT %s
+; RUN: llc -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \
+; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE-JT %s
+
 ; FIXME: When asm-parse is available, could make this an assembly test.
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
@@ -12,7 +18,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i32 @test_external() nounwind {
 entry:
-  %0 = load i32* @ei, align 4
+  %0 = load i32, i32* @ei, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @ei, align 4
   ret i32 %0
@@ -22,12 +28,12 @@ entry:
 ; accessing external variable ei.
 ;
 ; MEDIUM:      Relocations [
-; MEDIUM:        Section (2) .rela.text {
+; MEDIUM:        Section {{.*}} .rela.text {
 ; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]]
 ; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]]
 ;
 ; LARGE:       Relocations [
-; LARGE:         Section (2) .rela.text {
+; LARGE:         Section {{.*}} .rela.text {
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]]
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]]
 
@@ -35,7 +41,7 @@ entry:
 
 define signext i32 @test_fn_static() nounwind {
 entry:
-  %0 = load i32* @test_fn_static.si, align 4
+  %0 = load i32, i32* @test_fn_static.si, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @test_fn_static.si, align 4
   ret i32 %0
@@ -57,7 +63,7 @@ entry:
 
 define signext i32 @test_file_static() nounwind {
 entry:
-  %0 = load i32* @gi, align 4
+  %0 = load i32, i32* @gi, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @gi, align 4
   ret i32 %0
@@ -92,11 +98,51 @@ entry:
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM4]]
 
+@ti = common global i32 0, align 4
+
+define signext i32 @test_tentative() nounwind {
+entry:
+  %0 = load i32, i32* @ti, align 4
+  %inc = add nsw i32 %0, 1
+  store i32 %inc, i32* @ti, align 4
+  ret i32 %0
+}
+
+; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
+; accessing tentatively declared variable ti.
+;
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
+;
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
+
+define i8* @test_fnaddr() nounwind {
+entry:
+  %func = alloca i32 (i32)*, align 8
+  store i32 (i32)* @foo, i32 (i32)** %func, align 8
+  %0 = load i32 (i32)*, i32 (i32)** %func, align 8
+  %1 = bitcast i32 (i32)* %0 to i8*
+  ret i8* %1
+}
+
+declare signext i32 @foo(i32 signext)
+
+; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
+; accessing function address foo.
+;
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
+;
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
+; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
+
+
 define signext i32 @test_jump_table(i32 signext %i) nounwind {
 entry:
   %i.addr = alloca i32, align 4
   store i32 %i, i32* %i.addr, align 4
-  %0 = load i32* %i.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
   switch i32 %0, label %sw.default [
     i32 3, label %sw.bb
     i32 4, label %sw.bb1
@@ -108,78 +154,43 @@ sw.default:                                       ; preds = %entry
   br label %sw.epilog
 
 sw.bb:                                            ; preds = %entry
-  %1 = load i32* %i.addr, align 4
+  %1 = load i32, i32* %i.addr, align 4
   %mul = mul nsw i32 %1, 7
   store i32 %mul, i32* %i.addr, align 4
   br label %sw.bb1
 
 sw.bb1:                                           ; preds = %entry, %sw.bb
-  %2 = load i32* %i.addr, align 4
+  %2 = load i32, i32* %i.addr, align 4
   %dec = add nsw i32 %2, -1
   store i32 %dec, i32* %i.addr, align 4
   br label %sw.bb2
 
 sw.bb2:                                           ; preds = %entry, %sw.bb1
-  %3 = load i32* %i.addr, align 4
+  %3 = load i32, i32* %i.addr, align 4
   %add = add nsw i32 %3, 3
   store i32 %add, i32* %i.addr, align 4
   br label %sw.bb3
 
 sw.bb3:                                           ; preds = %entry, %sw.bb2
-  %4 = load i32* %i.addr, align 4
+  %4 = load i32, i32* %i.addr, align 4
   %shl = shl i32 %4, 1
   store i32 %shl, i32* %i.addr, align 4
   br label %sw.epilog
 
 sw.epilog:                                        ; preds = %sw.bb3, %sw.default
-  %5 = load i32* %i.addr, align 4
+  %5 = load i32, i32* %i.addr, align 4
   ret i32 %5
 }
 
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
 ; accessing a jump table address.
 ;
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM5:[^ ]+]]
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM5]]
-;
-; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM5:[^ ]+]]
-; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM5]]
-
-@ti = common global i32 0, align 4
-
-define signext i32 @test_tentative() nounwind {
-entry:
-  %0 = load i32* @ti, align 4
-  %inc = add nsw i32 %0, 1
-  store i32 %inc, i32* @ti, align 4
-  ret i32 %0
-}
-
-; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
-; accessing tentatively declared variable ti.
-;
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
-;
-; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
-; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
-
-define i8* @test_fnaddr() nounwind {
-entry:
-  %func = alloca i32 (i32)*, align 8
-  store i32 (i32)* @foo, i32 (i32)** %func, align 8
-  %0 = load i32 (i32)** %func, align 8
-  %1 = bitcast i32 (i32)* %0 to i8*
-  ret i8* %1
-}
-
-declare signext i32 @foo(i32 signext)
-
-; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
-; accessing function address foo.
-;
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
+; MEDIUM-JT:      Relocations [
+; MEDIUM-JT:        Section ({{.*}}) .rela.text {
+; MEDIUM-JT-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM:[^ ]+]]
+; MEDIUM-JT-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM]]
 ;
-; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
-; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
+; LARGE-JT:       Relocations [
+; LARGE-JT:         Section ({{.*}}) .rela.text {
+; LARGE-JT-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM:[^ ]+]]
+; LARGE-JT-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM]]
diff --git a/test/CodeGen/PowerPC/mem-rr-addr-mode.ll b/test/CodeGen/PowerPC/mem-rr-addr-mode.ll
index 5661ef9768d1..60a4bdba2296 100644
--- a/test/CodeGen/PowerPC/mem-rr-addr-mode.ll
+++ b/test/CodeGen/PowerPC/mem-rr-addr-mode.ll
@@ -5,12 +5,12 @@
 ; This shares the 16 between the two loads.
 
 define void @func(<4 x float>* %a, <4 x float>* %b) {
-        %tmp1 = getelementptr <4 x float>* %b, i32 1            ; <<4 x float>*> [#uses=1]
-        %tmp = load <4 x float>* %tmp1          ; <<4 x float>> [#uses=1]
-        %tmp3 = getelementptr <4 x float>* %a, i32 1            ; <<4 x float>*> [#uses=1]
-        %tmp4 = load <4 x float>* %tmp3         ; <<4 x float>> [#uses=1]
+        %tmp1 = getelementptr <4 x float>, <4 x float>* %b, i32 1            ; <<4 x float>*> [#uses=1]
+        %tmp = load <4 x float>, <4 x float>* %tmp1          ; <<4 x float>> [#uses=1]
+        %tmp3 = getelementptr <4 x float>, <4 x float>* %a, i32 1            ; <<4 x float>*> [#uses=1]
+        %tmp4 = load <4 x float>, <4 x float>* %tmp3         ; <<4 x float>> [#uses=1]
         %tmp5 = fmul <4 x float> %tmp, %tmp4             ; <<4 x float>> [#uses=1]
-        %tmp8 = load <4 x float>* %b            ; <<4 x float>> [#uses=1]
+        %tmp8 = load <4 x float>, <4 x float>* %b            ; <<4 x float>> [#uses=1]
         %tmp9 = fadd <4 x float> %tmp5, %tmp8            ; <<4 x float>> [#uses=1]
         store <4 x float> %tmp9, <4 x float>* %a
         ret void
diff --git a/test/CodeGen/PowerPC/mem_update.ll b/test/CodeGen/PowerPC/mem_update.ll
index fcf53da67fc2..2fa01402579a 100644
--- a/test/CodeGen/PowerPC/mem_update.ll
+++ b/test/CodeGen/PowerPC/mem_update.ll
@@ -6,58 +6,58 @@
 @Glob = global i64 4
 
 define i32* @test0(i32* %X, i32* %dest) nounwind {
-	%Y = getelementptr i32* %X, i32 4
-	%A = load i32* %Y
+	%Y = getelementptr i32, i32* %X, i32 4
+	%A = load i32, i32* %Y
 	store i32 %A, i32* %dest
 	ret i32* %Y
 }
 
 define i32* @test1(i32* %X, i32* %dest) nounwind {
-	%Y = getelementptr i32* %X, i32 4
-	%A = load i32* %Y
+	%Y = getelementptr i32, i32* %X, i32 4
+	%A = load i32, i32* %Y
 	store i32 %A, i32* %dest
 	ret i32* %Y
 }
 
 define i16* @test2(i16* %X, i32* %dest) nounwind {
-	%Y = getelementptr i16* %X, i32 4
-	%A = load i16* %Y
+	%Y = getelementptr i16, i16* %X, i32 4
+	%A = load i16, i16* %Y
 	%B = sext i16 %A to i32
 	store i32 %B, i32* %dest
 	ret i16* %Y
 }
 
 define i16* @test3(i16* %X, i32* %dest) nounwind {
-	%Y = getelementptr i16* %X, i32 4
-	%A = load i16* %Y
+	%Y = getelementptr i16, i16* %X, i32 4
+	%A = load i16, i16* %Y
 	%B = zext i16 %A to i32
 	store i32 %B, i32* %dest
 	ret i16* %Y
 }
 
 define i16* @test3a(i16* %X, i64* %dest) nounwind {
-	%Y = getelementptr i16* %X, i32 4
-	%A = load i16* %Y
+	%Y = getelementptr i16, i16* %X, i32 4
+	%A = load i16, i16* %Y
 	%B = sext i16 %A to i64
 	store i64 %B, i64* %dest
 	ret i16* %Y
 }
 
 define i64* @test4(i64* %X, i64* %dest) nounwind {
-	%Y = getelementptr i64* %X, i32 4
-	%A = load i64* %Y
+	%Y = getelementptr i64, i64* %X, i32 4
+	%A = load i64, i64* %Y
 	store i64 %A, i64* %dest
 	ret i64* %Y
 }
 
 define i16* @test5(i16* %X) nounwind {
-	%Y = getelementptr i16* %X, i32 4
+	%Y = getelementptr i16, i16* %X, i32 4
 	store i16 7, i16* %Y
 	ret i16* %Y
 }
 
 define i64* @test6(i64* %X, i64 %A) nounwind {
-	%Y = getelementptr i64* %X, i32 4
+	%Y = getelementptr i64, i64* %X, i32 4
 	store i64 %A, i64* %Y
 	ret i64* %Y
 }
diff --git a/test/CodeGen/PowerPC/memcpy-vec.ll b/test/CodeGen/PowerPC/memcpy-vec.ll
new file mode 100644
index 000000000000..70b8ea931a27
--- /dev/null
+++ b/test/CodeGen/PowerPC/memcpy-vec.ll
@@ -0,0 +1,110 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PWR7
+; RUN: llc -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PWR8
+; RUN: llc -mcpu=a2q < %s | FileCheck %s -check-prefix=A2Q
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define void @foo1(double* nocapture %x, double* nocapture readonly %y) #0 {
+entry:
+  %0 = bitcast double* %x to i8*
+  %1 = bitcast double* %y to i8*
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 32, i32 8, i1 false)
+  ret void
+
+; PWR7-LABEL: @foo1
+; PWR7-NOT: bl memcpy
+; PWR7: ld {{[0-9]+}}, {{[0-9]+}}(4)
+; PWR7: std {{[0-9]+}}, {{[0-9]+}}(3)
+; PWR7: blr
+
+; PWR8-LABEL: @foo1
+; PWR8: lxvw4x
+; PWR8: stxvw4x
+; PWR8: blr
+
+; A2Q-LABEL: @foo1
+; A2Q-NOT: bl memcpy
+; A2Q: ld {{[0-9]+}}, {{[0-9]+}}(4)
+; A2Q: std {{[0-9]+}}, {{[0-9]+}}(3)
+; A2Q: blr
+}
+
+; Function Attrs: nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #0
+
+; Function Attrs: nounwind
+define void @foo2(double* nocapture %x, double* nocapture readonly %y) #0 {
+entry:
+  %0 = bitcast double* %x to i8*
+  %1 = bitcast double* %y to i8*
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 128, i32 8, i1 false)
+  ret void
+
+; PWR7-LABEL: @foo2
+; PWR7: bl memcpy
+; PWR7: blr
+
+; PWR8-LABEL: @foo2
+; PWR8: lxvw4x
+; PWR8: stxvw4x
+; PWR8: blr
+
+; A2Q-LABEL: @foo2
+; A2Q-NOT: bl memcpy
+; A2Q: ld {{[0-9]+}}, {{[0-9]+}}(4)
+; A2Q: std {{[0-9]+}}, {{[0-9]+}}(3)
+; A2Q: blr
+}
+
+; Function Attrs: nounwind
+define void @bar1(double* nocapture %x) #0 {
+entry:
+  %0 = bitcast double* %x to i8*
+  tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 128, i32 8, i1 false)
+  ret void
+
+; PWR7-LABEL: @bar1
+; PWR7-NOT: bl memset
+; PWR7: stxvw4x
+; PWR7: blr
+
+; PWR8-LABEL: @bar1
+; PWR8-NOT: bl memset
+; PWR8: stxvw4x
+; PWR8: blr
+
+; A2Q-LABEL: @bar1
+; A2Q-NOT: bl memset
+; A2Q: std {{[0-9]+}}, {{[0-9]+}}(3)
+; A2Q: blr
+}
+
+; Function Attrs: nounwind
+define void @bar2(double* nocapture %x) #0 {
+entry:
+  %0 = bitcast double* %x to i8*
+  tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 128, i32 32, i1 false)
+  ret void
+
+; PWR7-LABEL: @bar2
+; PWR7-NOT: bl memset
+; PWR7: stxvw4x
+; PWR7: blr
+
+; PWR8-LABEL: @bar2
+; PWR8-NOT: bl memset
+; PWR8: stxvw4x
+; PWR8: blr
+
+; A2Q-LABEL: @bar2
+; A2Q-NOT: bl memset
+; A2Q: qvstfdx
+; A2Q: blr
+}
+
+; Function Attrs: nounwind
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #0
+
+attributes #0 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/memset-nc-le.ll b/test/CodeGen/PowerPC/memset-nc-le.ll
new file mode 100644
index 000000000000..af8e9c3fb4fd
--- /dev/null
+++ b/test/CodeGen/PowerPC/memset-nc-le.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le"
+
+; Function Attrs: nounwind
+define void @test_vsx() unnamed_addr #0 align 2 {
+entry:
+  %0 = load i32, i32* undef, align 4
+  %1 = trunc i32 %0 to i8
+  call void @llvm.memset.p0i8.i64(i8* null, i8 %1, i64 32, i32 1, i1 false)
+  ret void
+
+; CHECK-LABEL: @test_vsx
+; CHECK: stxvd2x
+; CHECK: stxvd2x
+; CHECK: blr
+}
+
+; Function Attrs: nounwind
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #1
+
+attributes #0 = { nounwind "target-cpu"="pwr8" }
+attributes #1 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/memset-nc.ll b/test/CodeGen/PowerPC/memset-nc.ll
new file mode 100644
index 000000000000..414a987a56fe
--- /dev/null
+++ b/test/CodeGen/PowerPC/memset-nc.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s | FileCheck %s
+; RUN: llc -O0 < %s | FileCheck %s -check-prefix=CHECK-O0
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+; Function Attrs: nounwind
+define void @test_qpx() unnamed_addr #0 align 2 {
+entry:
+  %0 = load i32, i32* undef, align 4
+  %1 = trunc i32 %0 to i8
+  call void @llvm.memset.p0i8.i64(i8* null, i8 %1, i64 64, i32 32, i1 false)
+  ret void
+
+; CHECK-LABEL: @test_qpx
+; CHECK: qvstfdx
+; CHECK: qvstfdx
+; CHECK: blr
+
+; CHECK-O0-LABEL: @test_qpx
+; CHECK-O0-NOT: qvstfdx
+; CHECK-O0: blr
+}
+
+; Function Attrs: nounwind
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #1
+
+; Function Attrs: nounwind
+define void @test_vsx() unnamed_addr #2 align 2 {
+entry:
+  %0 = load i32, i32* undef, align 4
+  %1 = trunc i32 %0 to i8
+  call void @llvm.memset.p0i8.i64(i8* null, i8 %1, i64 32, i32 1, i1 false)
+  ret void
+
+; CHECK-LABEL: @test_vsx
+; CHECK: stxvw4x
+; CHECK: stxvw4x
+; CHECK: blr
+
+; CHECK-O0-LABEL: @test_vsx
+; CHECK-O0-NOT: stxvw4x
+; CHECK-O0: blr
+}
+
+attributes #0 = { nounwind "target-cpu"="a2q" }
+attributes #1 = { nounwind }
+attributes #2 = { nounwind "target-cpu"="pwr7" }
+
diff --git a/test/CodeGen/PowerPC/misched-inorder-latency.ll b/test/CodeGen/PowerPC/misched-inorder-latency.ll
index b259ff182c0c..0f57e90abebd 100644
--- a/test/CodeGen/PowerPC/misched-inorder-latency.ll
+++ b/test/CodeGen/PowerPC/misched-inorder-latency.ll
@@ -15,13 +15,13 @@ target triple = "powerpc64-bgq-linux"
 define i32 @testload(i32 *%ptr, i32 %sumin) {
 entry:
   %sum1 = add i32 %sumin, 1
-  %val1 = load i32* %ptr
+  %val1 = load i32, i32* %ptr
   %p = icmp eq i32 %sumin, 0
   br i1 %p, label %true, label %end
 true:
   %sum2 = add i32 %sum1, 1
-  %ptr2 = getelementptr i32* %ptr, i32 1
-  %val = load i32* %ptr2
+  %ptr2 = getelementptr i32, i32* %ptr, i32 1
+  %val = load i32, i32* %ptr2
   %val2 = add i32 %val1, %val
   br label %end
 end:
diff --git a/test/CodeGen/PowerPC/misched.ll b/test/CodeGen/PowerPC/misched.ll
index d6fb3b30464f..1c868b3f171c 100644
--- a/test/CodeGen/PowerPC/misched.ll
+++ b/test/CodeGen/PowerPC/misched.ll
@@ -18,7 +18,7 @@ for.body24.i:                                     ; preds = %for.body24.i, %for.
   br i1 undef, label %for.body24.i58, label %for.body24.i
 
 for.body24.i58:                                   ; preds = %for.body24.i58, %for.body24.i
-  %arrayidx26.i55.1 = getelementptr inbounds [16000 x double]* @b, i64 0, i64 undef
+  %arrayidx26.i55.1 = getelementptr inbounds [16000 x double], [16000 x double]* @b, i64 0, i64 undef
   store double 1.000000e+00, double* %arrayidx26.i55.1, align 8
   br i1 undef, label %for.body24.i64, label %for.body24.i58
 
diff --git a/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll b/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll
index 743cc62ddba7..36aecf1806bd 100644
--- a/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll
+++ b/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll
@@ -33,10 +33,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,<r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,r<"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -48,10 +48,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,>r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,r>"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -63,7 +63,7 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
@@ -120,10 +120,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r,imr"(i32 1) nounwind
@@ -137,15 +137,15 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r,X"(i32 1) nounwind
   store i32 %2, i32* %out0, align 4
-  %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %3, i32* %out0, align 4
   %4 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind
   store i32 %4, i32* %out0, align 4
@@ -158,14 +158,14 @@ define void @single_p() nounwind {
 entry:
   %out0 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
-  %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
 }
 
 define void @multi_m() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*m|r,m|r"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
@@ -190,10 +190,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|<r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|r<"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -205,10 +205,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|>r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|r>"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -220,7 +220,7 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|m"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
@@ -277,10 +277,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 1) nounwind
@@ -294,15 +294,15 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 1) nounwind
   store i32 %2, i32* %out0, align 4
-  %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %3, i32* %out0, align 4
   %4 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind
   store i32 %4, i32* %out0, align 4
@@ -315,7 +315,7 @@ define void @multi_p() nounwind {
 entry:
   %out0 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
-  %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
 }
diff --git a/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll b/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll
index 29a57867f567..ab7e414ead55 100644
--- a/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll
+++ b/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll
@@ -33,10 +33,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,<r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,r<"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -48,10 +48,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,>r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,r>"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -63,7 +63,7 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
@@ -120,10 +120,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r,imr"(i32 1) nounwind
@@ -137,15 +137,15 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r,X"(i32 1) nounwind
   store i32 %2, i32* %out0, align 4
-  %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %3, i32* %out0, align 4
   %4 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind
   store i32 %4, i32* %out0, align 4
@@ -158,14 +158,14 @@ define void @single_p() nounwind {
 entry:
   %out0 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
-  %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
 }
 
 define void @multi_m() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*m|r,m|r"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
@@ -190,10 +190,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|<r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|r<"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -205,10 +205,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|>r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|r>"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -220,7 +220,7 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|m"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
@@ -277,10 +277,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 1) nounwind
@@ -294,15 +294,15 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 1) nounwind
   store i32 %2, i32* %out0, align 4
-  %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %3, i32* %out0, align 4
   %4 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind
   store i32 %4, i32* %out0, align 4
@@ -315,7 +315,7 @@ define void @multi_p() nounwind {
 entry:
   %out0 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
-  %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
 }
diff --git a/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll b/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll
index d4ed05b9e50a..834df8b4d91c 100644
--- a/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll
+++ b/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll
@@ -1,15 +1,12 @@
-; RUN: not llc < %s -mtriple=powerpc64-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-DARWIN
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: not llc < %s -mtriple=powerpc64-apple-darwin 2>&1 | FileCheck %s
+; RUN: not llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
 
 define i64 @get_reg() nounwind {
 entry:
 ; FIXME: Include an allocatable-specific error message
-; CHECK-DARWIN: Invalid register name global variable
+; CHECK: Invalid register name global variable
         %reg = call i64 @llvm.read_register.i64(metadata !0)
   ret i64 %reg
-
-; CHECK-LABEL: @get_reg
-; CHECK: mr 3, 2
 }
 
 declare i64 @llvm.read_register.i64(metadata) nounwind
diff --git a/test/CodeGen/PowerPC/named-reg-alloc-r2.ll b/test/CodeGen/PowerPC/named-reg-alloc-r2.ll
index 262d034e16bd..45d9816793c4 100644
--- a/test/CodeGen/PowerPC/named-reg-alloc-r2.ll
+++ b/test/CodeGen/PowerPC/named-reg-alloc-r2.ll
@@ -1,11 +1,11 @@
-; RUN: not llc < %s -mtriple=powerpc-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-DARWIN
+; RUN: not llc < %s -mtriple=powerpc-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-NOTPPC32
 ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: not llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s --check-prefix=CHECK-NOTPPC32
 
 define i32 @get_reg() nounwind {
 entry:
 ; FIXME: Include an allocatable-specific error message
-; CHECK-DARWIN: Invalid register name global variable
+; CHECK-NOTPPC32: Invalid register name global variable
         %reg = call i32 @llvm.read_register.i32(metadata !0)
   ret i32 %reg
 
diff --git a/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll b/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll
index 6beee253a2ec..26739bf958b5 100644
--- a/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll
+++ b/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll
@@ -5,7 +5,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 ; Function Attrs: nounwind readonly
 define double @test1(i64* nocapture readonly %x) #0 {
 entry:
-  %0 = load i64* %x, align 8
+  %0 = load i64, i64* %x, align 8
   %conv = sitofp i64 %0 to double
   ret double %conv
 
@@ -18,7 +18,7 @@ entry:
 ; Function Attrs: nounwind readonly
 define double @test2(i32* nocapture readonly %x) #0 {
 entry:
-  %0 = load i32* %x, align 4
+  %0 = load i32, i32* %x, align 4
   %conv = sitofp i32 %0 to double
   ret double %conv
 
diff --git a/test/CodeGen/PowerPC/no-pref-jumps.ll b/test/CodeGen/PowerPC/no-pref-jumps.ll
new file mode 100644
index 000000000000..d9490f16e8f9
--- /dev/null
+++ b/test/CodeGen/PowerPC/no-pref-jumps.ll
@@ -0,0 +1,36 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define void @foo(i32 signext %a, i32 signext %b) #0 {
+entry:
+  %cmp = icmp sgt i32 %a, 5
+  %cmp1 = icmp slt i32 %b, 3
+  %or.cond = or i1 %cmp, %cmp1
+  br i1 %or.cond, label %if.then, label %if.else
+
+; CHECK-LABEL: @foo
+; CHECK: cmpwi
+; CHECK: cmpwi
+; CHECK: cror
+; CHECK: blr
+
+if.then:                                          ; preds = %entry
+  tail call void bitcast (void (...)* @bar to void ()*)() #0
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  tail call void bitcast (void (...)* @car to void ()*)() #0
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  ret void
+}
+
+declare void @bar(...)
+
+declare void @car(...)
+
+attributes #0 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/novrsave.ll b/test/CodeGen/PowerPC/novrsave.ll
index a70576a291e9..50be2a162ed8 100644
--- a/test/CodeGen/PowerPC/novrsave.ll
+++ b/test/CodeGen/PowerPC/novrsave.ll
@@ -7,7 +7,7 @@ define <4 x float> @bar(<4 x float> %v) nounwind {
 entry:
   %v.addr = alloca <4 x float>, align 16
   store <4 x float> %v, <4 x float>* %v.addr, align 16
-  %0 = load <4 x float>* %v.addr, align 16
+  %0 = load <4 x float>, <4 x float>* %v.addr, align 16
   ret <4 x float> %0
 }
 
diff --git a/test/CodeGen/PowerPC/optnone-crbits-i1-ret.ll b/test/CodeGen/PowerPC/optnone-crbits-i1-ret.ll
new file mode 100644
index 000000000000..745a038d6ce0
--- /dev/null
+++ b/test/CodeGen/PowerPC/optnone-crbits-i1-ret.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+declare zeroext i1 @ri1()
+declare void @se1()
+declare void @se2()
+
+define void @test() #0 {
+entry:
+  %b = call zeroext i1 @ri1()
+  br label %next
+
+; CHECK-LABEL: @test
+; CHECK: bl ri1
+; CHECK-NEXT: nop
+; CHECK: andi. 3, 3, 1
+
+next:
+  br i1 %b, label %case1, label %case2
+
+case1:
+  call void @se1()
+  br label %end
+
+case2:
+  call void @se2()
+  br label %end
+
+end:
+  ret void
+
+; CHECK: blr
+}
+
+attributes #0 = { noinline optnone }
+
diff --git a/test/CodeGen/PowerPC/or-addressing-mode.ll b/test/CodeGen/PowerPC/or-addressing-mode.ll
index e50374e30696..f98b34cfdb6a 100644
--- a/test/CodeGen/PowerPC/or-addressing-mode.ll
+++ b/test/CodeGen/PowerPC/or-addressing-mode.ll
@@ -8,7 +8,7 @@ define i32 @test1(i8* %P) {
         %tmp.11.i = and i32 %tmp.10.i, 2040             ; <i32> [#uses=1]
         %tmp.13.i = or i32 %tmp.11.i, %tmp.4.i          ; <i32> [#uses=1]
         %tmp.14.i = inttoptr i32 %tmp.13.i to i32*              ; <i32*> [#uses=1]
-        %tmp.3 = load i32* %tmp.14.i            ; <i32> [#uses=1]
+        %tmp.3 = load i32, i32* %tmp.14.i            ; <i32> [#uses=1]
         ret i32 %tmp.3
 }
 
@@ -16,7 +16,7 @@ define i32 @test2(i32 %P) {
         %tmp.2 = shl i32 %P, 4          ; <i32> [#uses=1]
         %tmp.3 = or i32 %tmp.2, 2               ; <i32> [#uses=1]
         %tmp.4 = inttoptr i32 %tmp.3 to i32*            ; <i32*> [#uses=1]
-        %tmp.5 = load i32* %tmp.4               ; <i32> [#uses=1]
+        %tmp.5 = load i32, i32* %tmp.4               ; <i32> [#uses=1]
         ret i32 %tmp.5
 }
 
diff --git a/test/CodeGen/PowerPC/p8-isel-sched.ll b/test/CodeGen/PowerPC/p8-isel-sched.ll
new file mode 100644
index 000000000000..034fe3c5fcbf
--- /dev/null
+++ b/test/CodeGen/PowerPC/p8-isel-sched.ll
@@ -0,0 +1,33 @@
+; RUN: llc -mcpu=pwr8 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define void @foo(i32* nocapture %r1, i32* nocapture %r2, i32* nocapture %r3, i32* nocapture %r4, i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) #0 {
+entry:
+  %tobool = icmp ne i32 %a, 0
+  %cond = select i1 %tobool, i32 %b, i32 %c
+  store i32 %cond, i32* %r1, align 4
+  %cond5 = select i1 %tobool, i32 %b, i32 %d
+  store i32 %cond5, i32* %r2, align 4
+  %add = add nsw i32 %b, 1
+  %sub = add nsw i32 %d, -2
+  %cond10 = select i1 %tobool, i32 %add, i32 %sub
+  store i32 %cond10, i32* %r3, align 4
+  %add13 = add nsw i32 %b, 3
+  %sub15 = add nsw i32 %d, -5
+  %cond17 = select i1 %tobool, i32 %add13, i32 %sub15
+  store i32 %cond17, i32* %r4, align 4
+  ret void
+}
+
+; Make sure that we don't schedule all of the isels together, they should be
+; intermixed with the adds because each isel starts a new dispatch group.
+; CHECK-LABEL: @foo
+; CHECK: isel
+; CHECK: addi
+; CHECK: isel
+; CHECK: blr
+
+attributes #0 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/pip-inner.ll b/test/CodeGen/PowerPC/pip-inner.ll
new file mode 100644
index 000000000000..930f0d371472
--- /dev/null
+++ b/test/CodeGen/PowerPC/pip-inner.ll
@@ -0,0 +1,52 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define void @foo(double* %x, double* nocapture readonly %y) #0 {
+entry:
+  br label %for.cond1.preheader
+
+for.cond1.preheader:                              ; preds = %for.end, %entry
+  %i.015 = phi i32 [ 0, %entry ], [ %inc7, %for.end ]
+  br label %for.body3
+
+for.body3:                                        ; preds = %for.body3, %for.cond1.preheader
+  %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.body3 ]
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
+  %add = fadd double %0, 1.000000e+00
+  %arrayidx5 = getelementptr inbounds double, double* %x, i64 %indvars.iv
+  store double %add, double* %arrayidx5, align 8
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond = icmp eq i64 %indvars.iv.next, 16000
+  br i1 %exitcond, label %for.end, label %for.body3
+
+for.end:                                          ; preds = %for.body3
+  tail call void @bar(double* %x) #2
+  %inc7 = add nuw nsw i32 %i.015, 1
+  %exitcond16 = icmp eq i32 %inc7, 1000
+  br i1 %exitcond16, label %for.end8, label %for.cond1.preheader
+
+for.end8:                                         ; preds = %for.end
+  ret void
+
+; CHECK-LABEL: @foo
+
+; CHECK: lfdu [[REG1:[0-9]+]], 8({{[0-9]+}})
+; CHECK: fadd [[REG2:[0-9]+]], [[REG1]], {{[0-9]+}}
+; CHECK: stfdu [[REG2]], 8({{[0-9]+}})
+; CHECK: bdnz
+
+; CHECK: bl bar
+; CHECK-NEXT: nop
+
+; CHECK: blr
+}
+
+declare void @bar(double*) #1
+
+attributes #0 = { nounwind "target-cpu"="a2" }
+attributes #1 = { "target-cpu"="a2" }
+attributes #2 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/post-ra-ec.ll b/test/CodeGen/PowerPC/post-ra-ec.ll
index 9c61677650ba..e32441be90fd 100644
--- a/test/CodeGen/PowerPC/post-ra-ec.ll
+++ b/test/CodeGen/PowerPC/post-ra-ec.ll
@@ -16,12 +16,12 @@ entry:
   br i1 undef, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry
-  %0 = load i64* undef, align 8
+  %0 = load i64, i64* undef, align 8
   %conv.i = trunc i64 %0 to i32
-  %1 = load i32* null, align 4
+  %1 = load i32, i32* null, align 4
   %add = add i32 %1, %conv.i
   store i32 %add, i32* null, align 4
-  %counter.i.i = getelementptr inbounds %struct.task_struct.4.16.124* %call1.i, i64 0, i32 1, i32 0
+  %counter.i.i = getelementptr inbounds %struct.task_struct.4.16.124, %struct.task_struct.4.16.124* %call1.i, i64 0, i32 1, i32 0
   %2 = tail call i32 asm sideeffect "\09lwsync\0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0A\09sync\0A", "=&r,r,~{cr0},~{xer},~{memory}"(i32* %counter.i.i) #0
   %cmp.i = icmp eq i32 %2, 0
   br i1 %cmp.i, label %if.then.i, label %if.end
diff --git a/test/CodeGen/PowerPC/ppc-crbits-onoff.ll b/test/CodeGen/PowerPC/ppc-crbits-onoff.ll
new file mode 100644
index 000000000000..88648df5fa36
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc-crbits-onoff.ll
@@ -0,0 +1,43 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind readnone
+define signext i32 @crbitsoff(i32 signext %v1, i32 signext %v2) #0 {
+entry:
+  %tobool = icmp ne i32 %v1, 0
+  %lnot = icmp eq i32 %v2, 0
+  %and3 = and i1 %tobool, %lnot
+  %and = zext i1 %and3 to i32
+  ret i32 %and
+
+; CHECK-LABEL: @crbitsoff
+; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 0
+; CHECK-DAG: li [[REG2:[0-9]+]], 1
+; CHECK-DAG: cntlzw [[REG3:[0-9]+]],
+; CHECK: isel 3, 0, [[REG2]]
+; CHECK: and 3, 3, [[REG3]]
+; CHECK: blr
+}
+
+define signext i32 @crbitson(i32 signext %v1, i32 signext %v2) #1 {
+entry:
+  %tobool = icmp ne i32 %v1, 0
+  %lnot = icmp eq i32 %v2, 0
+  %and3 = and i1 %tobool, %lnot
+  %and = zext i1 %and3 to i32
+  ret i32 %and
+
+; CHECK-LABEL: @crbitson
+; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 0
+; CHECK-DAG: cmpwi {{[0-9]+}}, 4, 0
+; CHECK-DAG: li [[REG2:[0-9]+]], 1
+; CHECK-DAG: crorc [[REG3:[0-9]+]],
+; CHECK: isel 3, 0, [[REG2]], [[REG3]]
+; CHECK: blr
+}
+
+
+attributes #0 = { nounwind readnone "target-features"="-crbits" }
+attributes #1 = { nounwind readnone }
+
diff --git a/test/CodeGen/PowerPC/ppc-empty-fs.ll b/test/CodeGen/PowerPC/ppc-empty-fs.ll
new file mode 100644
index 000000000000..8c0a2fb1dc06
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc-empty-fs.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s | FileCheck %s
+; This guarantees that we add the default set of features to the current feature
+; string. We won't successfully legalize the types here without +64bit being
+; silently added.
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.fab = type { float, float }
+
+; Function Attrs: nounwind
+define void @func_fab(%struct.fab* noalias sret %agg.result, i64 %x.coerce) #0 {
+entry:
+  %x = alloca %struct.fab, align 8
+  %0 = bitcast %struct.fab* %x to i64*
+  store i64 %x.coerce, i64* %0, align 1
+  %1 = bitcast %struct.fab* %agg.result to i8*
+  %2 = bitcast %struct.fab* %x to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 8, i32 4, i1 false)
+  ret void
+}
+
+; CHECK: func_fab
+
+; Function Attrs: nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "target-features"="" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 233227) (llvm/trunk 233226)"}
diff --git a/test/CodeGen/PowerPC/ppc-prologue.ll b/test/CodeGen/PowerPC/ppc-prologue.ll
index 553837121a36..c84e6fbd4b60 100644
--- a/test/CodeGen/PowerPC/ppc-prologue.ll
+++ b/test/CodeGen/PowerPC/ppc-prologue.ll
@@ -14,12 +14,12 @@ entry:
   store i32 %a, i32* %a_addr
   %1 = call i32 @_Z3barPi(i32* %a_addr)           ; <i32> [#uses=1]
   store i32 %1, i32* %0, align 4
-  %2 = load i32* %0, align 4                      ; <i32> [#uses=1]
+  %2 = load i32, i32* %0, align 4                      ; <i32> [#uses=1]
   store i32 %2, i32* %retval, align 4
   br label %return
 
 return:                                           ; preds = %entry
-  %retval1 = load i32* %retval                    ; <i32> [#uses=1]
+  %retval1 = load i32, i32* %retval                    ; <i32> [#uses=1]
   ret i32 %retval1
 }
 
diff --git a/test/CodeGen/PowerPC/ppc32-cyclecounter.ll b/test/CodeGen/PowerPC/ppc32-cyclecounter.ll
index 9e2cd0b12880..ea50a1bdbdc1 100644
--- a/test/CodeGen/PowerPC/ppc32-cyclecounter.ll
+++ b/test/CodeGen/PowerPC/ppc32-cyclecounter.ll
@@ -13,8 +13,8 @@ entry:
 ; CHECK: mfspr 3, 269
 ; CHECK: mfspr 4, 268
 ; CHECK: mfspr [[REG:[0-9]+]], 269
-; CHECK: cmpw [[CR:[0-9]+]], 3, [[REG]]
-; CHECK: bne [[CR]], .LBB
+; CHECK: cmpw 3, [[REG]]
+; CHECK: bne 0, .LBB
 
 declare i64 @llvm.readcyclecounter()
 
diff --git a/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll b/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll
index 6e0aec27b7c1..ad8ed38da7fa 100644
--- a/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll
+++ b/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll
@@ -5,7 +5,7 @@ target triple = "powerpc-unknown-linux-gnu"
 declare void @printf(i8*, ...)
 
 define void @main() {
-  call void (i8*, ...)* @printf(i8* undef, i1 false)
+  call void (i8*, ...) @printf(i8* undef, i1 false)
   ret void
 }
 
diff --git a/test/CodeGen/PowerPC/ppc32-lshrti3.ll b/test/CodeGen/PowerPC/ppc32-lshrti3.ll
index f773cce81be3..a2a280f5168e 100644
--- a/test/CodeGen/PowerPC/ppc32-lshrti3.ll
+++ b/test/CodeGen/PowerPC/ppc32-lshrti3.ll
@@ -9,7 +9,7 @@ target triple = "powerpc--netbsd"
 ; Function Attrs: nounwind uwtable
 define i32 @fn1() #0 {
 entry:
-  %.promoted = load i72* inttoptr (i32 1 to i72*), align 4
+  %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
   br label %while.cond
 
 while.cond:                                       ; preds = %while.cond, %entry
diff --git a/test/CodeGen/PowerPC/ppc32-pic-large.ll b/test/CodeGen/PowerPC/ppc32-pic-large.ll
index bb906ec78d11..6a069451a410 100644
--- a/test/CodeGen/PowerPC/ppc32-pic-large.ll
+++ b/test/CodeGen/PowerPC/ppc32-pic-large.ll
@@ -5,8 +5,8 @@ declare i32 @call_foo(i32, ...)
 
 define i32 @foo() {
 entry:
-  %0 = load i32* @bar, align 4
-  %call = call i32 (i32, ...)* @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64)
+  %0 = load i32, i32* @bar, align 4
+  %call = call i32 (i32, ...) @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64)
   ret i32 %0
 }
 
diff --git a/test/CodeGen/PowerPC/ppc32-pic.ll b/test/CodeGen/PowerPC/ppc32-pic.ll
index abc136757177..63f521cbea38 100644
--- a/test/CodeGen/PowerPC/ppc32-pic.ll
+++ b/test/CodeGen/PowerPC/ppc32-pic.ll
@@ -5,8 +5,8 @@ declare i32 @call_foo(i32, ...)
 
 define i32 @foo() {
 entry:
-  %0 = load i32* @bar, align 4
-  %call = call i32 (i32, ...)* @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64)
+  %0 = load i32, i32* @bar, align 4
+  %call = call i32 (i32, ...) @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64)
   ret i32 0
 }
 
diff --git a/test/CodeGen/PowerPC/ppc440-fp-basic.ll b/test/CodeGen/PowerPC/ppc440-fp-basic.ll
index 77b726c5ae38..95773570d33c 100644
--- a/test/CodeGen/PowerPC/ppc440-fp-basic.ll
+++ b/test/CodeGen/PowerPC/ppc440-fp-basic.ll
@@ -4,28 +4,28 @@
 
 define void @maybe_an_fma(%0* sret %agg.result, %0* byval %a, %0* byval %b, %0* byval %c) nounwind {
 entry:
-  %a.realp = getelementptr inbounds %0* %a, i32 0, i32 0
-  %a.real = load double* %a.realp
-  %a.imagp = getelementptr inbounds %0* %a, i32 0, i32 1
-  %a.imag = load double* %a.imagp
-  %b.realp = getelementptr inbounds %0* %b, i32 0, i32 0
-  %b.real = load double* %b.realp
-  %b.imagp = getelementptr inbounds %0* %b, i32 0, i32 1
-  %b.imag = load double* %b.imagp
+  %a.realp = getelementptr inbounds %0, %0* %a, i32 0, i32 0
+  %a.real = load double, double* %a.realp
+  %a.imagp = getelementptr inbounds %0, %0* %a, i32 0, i32 1
+  %a.imag = load double, double* %a.imagp
+  %b.realp = getelementptr inbounds %0, %0* %b, i32 0, i32 0
+  %b.real = load double, double* %b.realp
+  %b.imagp = getelementptr inbounds %0, %0* %b, i32 0, i32 1
+  %b.imag = load double, double* %b.imagp
   %mul.rl = fmul double %a.real, %b.real
   %mul.rr = fmul double %a.imag, %b.imag
   %mul.r = fsub double %mul.rl, %mul.rr
   %mul.il = fmul double %a.imag, %b.real
   %mul.ir = fmul double %a.real, %b.imag
   %mul.i = fadd double %mul.il, %mul.ir
-  %c.realp = getelementptr inbounds %0* %c, i32 0, i32 0
-  %c.real = load double* %c.realp
-  %c.imagp = getelementptr inbounds %0* %c, i32 0, i32 1
-  %c.imag = load double* %c.imagp
+  %c.realp = getelementptr inbounds %0, %0* %c, i32 0, i32 0
+  %c.real = load double, double* %c.realp
+  %c.imagp = getelementptr inbounds %0, %0* %c, i32 0, i32 1
+  %c.imag = load double, double* %c.imagp
   %add.r = fadd double %mul.r, %c.real
   %add.i = fadd double %mul.i, %c.imag
-  %real = getelementptr inbounds %0* %agg.result, i32 0, i32 0
-  %imag = getelementptr inbounds %0* %agg.result, i32 0, i32 1
+  %real = getelementptr inbounds %0, %0* %agg.result, i32 0, i32 0
+  %imag = getelementptr inbounds %0, %0* %agg.result, i32 0, i32 1
   store double %add.r, double* %real
   store double %add.i, double* %imag
   ret void
diff --git a/test/CodeGen/PowerPC/ppc64-abi-extend.ll b/test/CodeGen/PowerPC/ppc64-abi-extend.ll
index 8baf1c613e78..f8e72e3a108e 100644
--- a/test/CodeGen/PowerPC/ppc64-abi-extend.ll
+++ b/test/CodeGen/PowerPC/ppc64-abi-extend.ll
@@ -15,7 +15,7 @@ declare zeroext i32 @ret_ui()
 
 define void @pass_arg_si() nounwind {
 entry:
-  %0 = load i32* @si, align 4
+  %0 = load i32, i32* @si, align 4
   tail call void @arg_si(i32 signext %0) nounwind
   ret void
 }
@@ -25,7 +25,7 @@ entry:
 
 define void @pass_arg_ui() nounwind {
 entry:
-  %0 = load i32* @ui, align 4
+  %0 = load i32, i32* @ui, align 4
   tail call void @arg_ui(i32 zeroext %0) nounwind
   ret void
 }
@@ -53,7 +53,7 @@ entry:
 
 define signext i32 @pass_ret_si() nounwind readonly {
 entry:
-  %0 = load i32* @si, align 4
+  %0 = load i32, i32* @si, align 4
   ret i32 %0
 }
 ; CHECK: @pass_ret_si
@@ -62,7 +62,7 @@ entry:
 
 define zeroext i32 @pass_ret_ui() nounwind readonly {
 entry:
-  %0 = load i32* @ui, align 4
+  %0 = load i32, i32* @ui, align 4
   ret i32 %0
 }
 ; CHECK: @pass_ret_ui
diff --git a/test/CodeGen/PowerPC/ppc64-align-long-double.ll b/test/CodeGen/PowerPC/ppc64-align-long-double.ll
index 5ed029cc9702..b9fd6707f041 100644
--- a/test/CodeGen/PowerPC/ppc64-align-long-double.ll
+++ b/test/CodeGen/PowerPC/ppc64-align-long-double.ll
@@ -13,8 +13,8 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define ppc_fp128 @test(%struct.S* byval %x) nounwind {
 entry:
-  %b = getelementptr inbounds %struct.S* %x, i32 0, i32 1
-  %0 = load ppc_fp128* %b, align 16
+  %b = getelementptr inbounds %struct.S, %struct.S* %x, i32 0, i32 1
+  %0 = load ppc_fp128, ppc_fp128* %b, align 16
   ret ppc_fp128 %0
 }
 
diff --git a/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll b/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll
index 479c7a7af25f..dfa6ec058b92 100644
--- a/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll
+++ b/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll
@@ -8,7 +8,7 @@ define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i6
                         i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24,
                         i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32) {
 entry:
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 32,
+  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 32,
                 i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
                 i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16,
                 i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24,
diff --git a/test/CodeGen/PowerPC/ppc64-anyregcc.ll b/test/CodeGen/PowerPC/ppc64-anyregcc.ll
index 7cd3c4b38200..66f6a2c790c6 100644
--- a/test/CodeGen/PowerPC/ppc64-anyregcc.ll
+++ b/test/CodeGen/PowerPC/ppc64-anyregcc.ll
@@ -2,6 +2,31 @@
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
+; CHECK-LABEL: test:
+; CHECK: {{^}}.L[[test_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: property_access1:
+; CHECK: {{^}}.L[[property_access1_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: property_access2:
+; CHECK: {{^}}.L[[property_access2_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: property_access3:
+; CHECK: {{^}}.L[[property_access3_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: anyreg_test1:
+; CHECK: {{^}}.L[[anyreg_test1_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: anyreg_test2:
+; CHECK: {{^}}.L[[anyreg_test2_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: patchpoint_spilldef:
+; CHECK: {{^}}.L[[patchpoint_spilldef_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: patchpoint_spillargs:
+; CHECK: {{^}}.L[[patchpoint_spillargs_BEGIN:.*]]:{{$}}
+
+
 ; Stackmap Header: no constants - 6 callsites
 ; CHECK-LABEL: .section	.llvm_stackmaps
 ; CHECK-NEXT:  __LLVM_StackMaps:
@@ -26,9 +51,9 @@ target triple = "powerpc64-unknown-linux-gnu"
 ; CHECK-NEXT:   .quad property_access3
 ; CHECK-NEXT:   .quad 128
 ; CHECK-NEXT:   .quad anyreg_test1
-; CHECK-NEXT:   .quad 160
+; CHECK-NEXT:   .quad 144
 ; CHECK-NEXT:   .quad anyreg_test2
-; CHECK-NEXT:   .quad 160
+; CHECK-NEXT:   .quad 144
 ; CHECK-NEXT:   .quad patchpoint_spilldef
 ; CHECK-NEXT:   .quad 256
 ; CHECK-NEXT:   .quad patchpoint_spillargs
@@ -36,7 +61,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 
 ; test
-; CHECK-LABEL:  .long   .L{{.*}}-.L.test
+; CHECK:  .long   .L{{.*}}-.L[[test_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; 3 locations
 ; CHECK-NEXT:   .short  3
@@ -57,12 +82,12 @@ target triple = "powerpc64-unknown-linux-gnu"
 ; CHECK-NEXT:   .long 3
 define i64 @test() nounwind ssp uwtable {
 entry:
-  call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 0, i32 24, i8* null, i32 2, i32 1, i32 2, i64 3)
+  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 24, i8* null, i32 2, i32 1, i32 2, i64 3)
   ret i64 0
 }
 
 ; property access 1 - %obj is an anyreg call argument and should therefore be in a register
-; CHECK-LABEL:  .long   .L{{.*}}-.L.property_access1
+; CHECK:  .long   .L{{.*}}-.L[[property_access1_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
@@ -79,12 +104,12 @@ entry:
 define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 1, i32 24, i8* %f, i32 1, i8* %obj)
+  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 24, i8* %f, i32 1, i8* %obj)
   ret i64 %ret
 }
 
 ; property access 2 - %obj is an anyreg call argument and should therefore be in a register
-; CHECK-LABEL:  .long   .L{{.*}}-.L.property_access2
+; CHECK:  .long   .L{{.*}}-.L[[property_access2_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
@@ -102,12 +127,12 @@ define i64 @property_access2() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
   %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 24, i8* %f, i32 1, i64* %obj)
+  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 24, i8* %f, i32 1, i64* %obj)
   ret i64 %ret
 }
 
 ; property access 3 - %obj is a frame index
-; CHECK-LABEL:  .long   .L{{.*}}-.L.property_access3
+; CHECK:  .long   .L{{.*}}-.L[[property_access3_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
@@ -125,12 +150,12 @@ define i64 @property_access3() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
   %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 24, i8* %f, i32 0, i64* %obj)
+  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 24, i8* %f, i32 0, i64* %obj)
   ret i64 %ret
 }
 
 ; anyreg_test1
-; CHECK-LABEL:  .long   .L{{.*}}-.L.anyreg_test1
+; CHECK:  .long   .L{{.*}}-.L[[anyreg_test1_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; 14 locations
 ; CHECK-NEXT:   .short  14
@@ -207,12 +232,12 @@ entry:
 define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 4, i32 24, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
+  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 24, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
   ret i64 %ret
 }
 
 ; anyreg_test2
-; CHECK-LABEL:  .long   .L{{.*}}-.L.anyreg_test2
+; CHECK:  .long   .L{{.*}}-.L[[anyreg_test2_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; 14 locations
 ; CHECK-NEXT:   .short  14
@@ -289,7 +314,7 @@ entry:
 define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 24, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
+  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 24, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
   ret i64 %ret
 }
 
@@ -297,7 +322,7 @@ entry:
 ;
 ; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
 ;
-; CHECK-LABEL: .long .L{{.*}}-.L.patchpoint_spilldef
+; CHECK: .long .L{{.*}}-.L[[patchpoint_spilldef_BEGIN]]
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .short 3
 ; Loc 0: Register (some register that will be spilled to the stack)
@@ -317,7 +342,7 @@ entry:
 ; CHECK-NEXT: .long  0
 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
+  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
   tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
 },~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
   ret i64 %result
@@ -327,7 +352,7 @@ entry:
 ;
 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
 ;
-; CHECK-LABEL: .long .L{{.*}}-.L.patchpoint_spillargs
+; CHECK: .long .L{{.*}}-.L[[patchpoint_spillargs_BEGIN]]
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .short 5
 ; Loc 0: Return a register
@@ -359,7 +384,7 @@ define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
   tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
 },~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 13, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
+  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
   ret i64 %result
 }
 
diff --git a/test/CodeGen/PowerPC/ppc64-byval-align.ll b/test/CodeGen/PowerPC/ppc64-byval-align.ll
index 0e73cf2b0e05..7170f5906581 100644
--- a/test/CodeGen/PowerPC/ppc64-byval-align.ll
+++ b/test/CodeGen/PowerPC/ppc64-byval-align.ll
@@ -30,8 +30,8 @@ entry:
 
 define i64 @callee2(%struct.pad* byval nocapture readnone %x, i32 signext %y, %struct.test* byval align 16 nocapture readonly %z) {
 entry:
-  %x1 = getelementptr inbounds %struct.test* %z, i64 0, i32 0
-  %0 = load i64* %x1, align 16
+  %x1 = getelementptr inbounds %struct.test, %struct.test* %z, i64 0, i32 0
+  %0 = load i64, i64* %x1, align 16
   ret i64 %0
 }
 ; CHECK-LABEL: @callee2
@@ -43,14 +43,16 @@ declare i64 @test2(%struct.pad* byval, i32 signext, %struct.test* byval align 16
 define void @caller2(i64 %z) {
 entry:
   %tmp = alloca %struct.test, align 16
-  %.compoundliteral.sroa.0.0..sroa_idx = getelementptr inbounds %struct.test* %tmp, i64 0, i32 0
+  %.compoundliteral.sroa.0.0..sroa_idx = getelementptr inbounds %struct.test, %struct.test* %tmp, i64 0, i32 0
   store i64 %z, i64* %.compoundliteral.sroa.0.0..sroa_idx, align 16
   %call = call i64 @test2(%struct.pad* byval @gp, i32 signext 0, %struct.test* byval align 16 %tmp)
   ret void
 }
 ; CHECK-LABEL: @caller2
 ; CHECK: std 3, [[OFF:[0-9]+]](1)
-; CHECK: ld [[REG:[0-9]+]], [[OFF]](1)
-; CHECK: std [[REG]], 128(1)
+; CHECK: addi [[REG1:[0-9]+]], 1, [[OFF]]
+; CHECK: lxvw4x [[REG2:[0-9]+]], 0, [[REG1]]
+; CHECK: li [[REG3:[0-9]+]], 128
+; CHECK: stxvw4x 0, 1, [[REG3]]
 ; CHECK: bl test2
 
diff --git a/test/CodeGen/PowerPC/ppc64-calls.ll b/test/CodeGen/PowerPC/ppc64-calls.ll
index 707ba95235f2..23a14e6687d6 100644
--- a/test/CodeGen/PowerPC/ppc64-calls.ll
+++ b/test/CodeGen/PowerPC/ppc64-calls.ll
@@ -73,7 +73,7 @@ define double @test_external(double %x) nounwind {
 @g = external global void ()*
 declare void @h(i64)
 define void @test_indir_toc_reload(i64 %x) {
-  %1 = load void ()** @g
+  %1 = load void ()*, void ()** @g
   call void %1()
   call void @h(i64 %x)
   ret void
diff --git a/test/CodeGen/PowerPC/ppc64-elf-abi.ll b/test/CodeGen/PowerPC/ppc64-elf-abi.ll
index d82122d58ee5..53443376e4d5 100644
--- a/test/CodeGen/PowerPC/ppc64-elf-abi.ll
+++ b/test/CodeGen/PowerPC/ppc64-elf-abi.ll
@@ -1,9 +1,9 @@
 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=CHECK-ELFv1
-; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mattr=+elfv1 < %s | FileCheck %s -check-prefix=CHECK-ELFv1
-; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mattr=+elfv2 < %s | FileCheck %s -check-prefix=CHECK-ELFv2
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -target-abi elfv1 < %s | FileCheck %s -check-prefix=CHECK-ELFv1
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -target-abi elfv2 < %s | FileCheck %s -check-prefix=CHECK-ELFv2
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=CHECK-ELFv2
-; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mattr=+elfv1 < %s | FileCheck %s -check-prefix=CHECK-ELFv1
-; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mattr=+elfv2 < %s | FileCheck %s -check-prefix=CHECK-ELFv2
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -target-abi elfv1 < %s | FileCheck %s -check-prefix=CHECK-ELFv1
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -target-abi elfv2 < %s | FileCheck %s -check-prefix=CHECK-ELFv2
 
 ; CHECK-ELFv2: .abiversion 2
 ; CHECK-ELFv1-NOT: .abiversion 2
diff --git a/test/CodeGen/PowerPC/ppc64-fastcc-fast-isel.ll b/test/CodeGen/PowerPC/ppc64-fastcc-fast-isel.ll
new file mode 100644
index 000000000000..f90519836c25
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc64-fastcc-fast-isel.ll
@@ -0,0 +1,56 @@
+; RUN: llc -mcpu=pwr7 -mattr=-vsx -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define fastcc i64 @g1(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 {
+  ret i64 %g1
+
+; CHECK-LABEL: @g1
+; CHECK-NOT: mr 3,
+; CHECK: blr
+}
+
+define fastcc i64 @g2(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 {
+  ret i64 %g2
+
+; CHECK-LABEL: @g2
+; CHECK: mr 3, 4
+; CHECK-NEXT: blr
+}
+
+define fastcc i64 @g3(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 {
+  ret i64 %g3
+
+; CHECK-LABEL: @g3
+; CHECK: mr 3, 5
+; CHECK-NEXT: blr
+}
+
+define fastcc double @f2(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 {
+  ret double %f2
+
+; CHECK-LABEL: @f2
+; CHECK: fmr 1, 2
+; CHECK-NEXT: blr
+}
+
+define void @cg2(i64 %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, i64 %v, double 0.0, i64 0, double 0.0, i64 0, double 0.0)
+  ret void
+
+; CHECK-LABEL: @cg2
+; CHECK: mr 4, 3
+; CHECK: blr
+}
+
+define void @cf2(double %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, i64 0, double %v, i64 0, double 0.0, i64 0, double 0.0)
+  ret void
+
+; CHECK-LABEL: @cf2
+; CHECK: mr 2, 1
+; CHECK: blr
+}
+
+attributes #0 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/ppc64-fastcc.ll b/test/CodeGen/PowerPC/ppc64-fastcc.ll
new file mode 100644
index 000000000000..bb1365a3b675
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc64-fastcc.ll
@@ -0,0 +1,540 @@
+; RUN: llc -mcpu=pwr7 -mattr=-vsx < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define fastcc i64 @g1(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret i64 %g1
+
+; CHECK-LABEL: @g1
+; CHECK-NOT: mr 3,
+; CHECK: blr
+}
+
+define fastcc i64 @g2(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret i64 %g2
+
+; CHECK-LABEL: @g2
+; CHECK: mr 3, 4
+; CHECK-NEXT: blr
+}
+
+define fastcc i64 @g3(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret i64 %g3
+
+; CHECK-LABEL: @g3
+; CHECK: mr 3, 5
+; CHECK-NEXT: blr
+}
+
+define fastcc i64 @g4(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret i64 %g4
+
+; CHECK-LABEL: @g4
+; CHECK: mr 3, 6
+; CHECK-NEXT: blr
+}
+
+define fastcc i64 @g5(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret i64 %g5
+
+; CHECK-LABEL: @g5
+; CHECK: mr 3, 7
+; CHECK-NEXT: blr
+}
+
+define fastcc i64 @g6(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret i64 %g6
+
+; CHECK-LABEL: @g6
+; CHECK: mr 3, 8
+; CHECK-NEXT: blr
+}
+
+define fastcc i64 @g7(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret i64 %g7
+
+; CHECK-LABEL: @g7
+; CHECK: mr 3, 9
+; CHECK-NEXT: blr
+}
+
+define fastcc i64 @g8(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret i64 %g8
+
+; CHECK-LABEL: @g8
+; CHECK: mr 3, 10
+; CHECK-NEXT: blr
+}
+
+define fastcc i64 @g9(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret i64 %g9
+
+; CHECK-LABEL: @g9
+; CHECK: ld 3, 48(1)
+; CHECK-NEXT: blr
+}
+
+define fastcc i64 @g10(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret i64 %g10
+
+; CHECK-LABEL: @g10
+; CHECK: ld 3, 56(1)
+; CHECK-NEXT: blr
+}
+
+define fastcc i64 @g11(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret i64 %g11
+
+; CHECK-LABEL: @g11
+; CHECK: ld 3, 64(1)
+; CHECK-NEXT: blr
+}
+
+define fastcc double @f1(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret double %f1
+
+; CHECK-LABEL: @f1
+; CHECK-NOT: fmr 1,
+; CHECK: blr
+}
+
+define fastcc double @f2(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret double %f2
+
+; CHECK-LABEL: @f2
+; CHECK: fmr 1, 2
+; CHECK-NEXT: blr
+}
+
+define fastcc double @f3(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret double %f3
+
+; CHECK-LABEL: @f3
+; CHECK: fmr 1, 3
+; CHECK-NEXT: blr
+}
+
+define fastcc double @f4(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret double %f4
+
+; CHECK-LABEL: @f4
+; CHECK: fmr 1, 4
+; CHECK-NEXT: blr
+}
+
+define fastcc double @f5(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret double %f5
+
+; CHECK-LABEL: @f5
+; CHECK: fmr 1, 5
+; CHECK-NEXT: blr
+}
+
+define fastcc double @f6(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret double %f6
+
+; CHECK-LABEL: @f6
+; CHECK: fmr 1, 6
+; CHECK-NEXT: blr
+}
+
+define fastcc double @f7(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret double %f7
+
+; CHECK-LABEL: @f7
+; CHECK: fmr 1, 7
+; CHECK-NEXT: blr
+}
+
+define fastcc double @f8(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret double %f8
+
+; CHECK-LABEL: @f8
+; CHECK: fmr 1, 8
+; CHECK-NEXT: blr
+}
+
+define fastcc double @f9(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret double %f9
+
+; CHECK-LABEL: @f9
+; CHECK: fmr 1, 9
+; CHECK-NEXT: blr
+}
+
+define fastcc double @f10(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret double %f10
+
+; CHECK-LABEL: @f10
+; CHECK: fmr 1, 10
+; CHECK-NEXT: blr
+}
+
+define fastcc double @f11(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret double %f11
+
+; CHECK-LABEL: @f11
+; CHECK: fmr 1, 11
+; CHECK-NEXT: blr
+}
+
+define fastcc double @f12(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret double %f12
+
+; CHECK-LABEL: @f12
+; CHECK: fmr 1, 12
+; CHECK-NEXT: blr
+}
+
+define fastcc double @f13(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret double %f13
+
+; CHECK-LABEL: @f13
+; CHECK: fmr 1, 13
+; CHECK-NEXT: blr
+}
+
+define fastcc double @f14(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret double %f14
+
+; CHECK-LABEL: @f14
+; CHECK: lfd 1, 120(1)
+; CHECK-NEXT: blr
+}
+
+define fastcc double @f15(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret double %f15
+
+; CHECK-LABEL: @f15
+; CHECK: lfd 1, 152(1)
+; CHECK-NEXT: blr
+}
+
+define fastcc <4 x i32> @v1(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret <4 x i32> %v1
+
+; CHECK-LABEL: @v1
+; CHECK-NOT: vor 2,
+; CHECK: blr
+}
+
+define fastcc <4 x i32> @v2(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret <4 x i32> %v2
+
+; CHECK-LABEL: @v2
+; CHECK: vor 2, 3, 3
+; CHECK-NEXT: blr
+}
+
+define fastcc <4 x i32> @v3(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret <4 x i32> %v3
+
+; CHECK-LABEL: @v3
+; CHECK: vor 2, 4, 4
+; CHECK-NEXT: blr
+}
+
+define fastcc <4 x i32> @v4(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret <4 x i32> %v4
+
+; CHECK-LABEL: @v4
+; CHECK: vor 2, 5, 5
+; CHECK-NEXT: blr
+}
+
+define fastcc <4 x i32> @v5(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret <4 x i32> %v5
+
+; CHECK-LABEL: @v5
+; CHECK: vor 2, 6, 6
+; CHECK-NEXT: blr
+}
+
+define fastcc <4 x i32> @v6(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret <4 x i32> %v6
+
+; CHECK-LABEL: @v6
+; CHECK: vor 2, 7, 7
+; CHECK-NEXT: blr
+}
+
+define fastcc <4 x i32> @v7(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret <4 x i32> %v7
+
+; CHECK-LABEL: @v7
+; CHECK: vor 2, 8, 8
+; CHECK-NEXT: blr
+}
+
+define fastcc <4 x i32> @v8(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret <4 x i32> %v8
+
+; CHECK-LABEL: @v8
+; CHECK: vor 2, 9, 9
+; CHECK-NEXT: blr
+}
+
+define fastcc <4 x i32> @v9(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret <4 x i32> %v9
+
+; CHECK-LABEL: @v9
+; CHECK: vor 2, 10, 10
+; CHECK-NEXT: blr
+}
+
+define fastcc <4 x i32> @v10(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret <4 x i32> %v10
+
+; CHECK-LABEL: @v10
+; CHECK: vor 2, 11, 11
+; CHECK-NEXT: blr
+}
+
+define fastcc <4 x i32> @v11(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret <4 x i32> %v11
+
+; CHECK-LABEL: @v11
+; CHECK: vor 2, 12, 12
+; CHECK-NEXT: blr
+}
+
+define fastcc <4 x i32> @v12(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret <4 x i32> %v12
+
+; CHECK-LABEL: @v12
+; CHECK: vor 2, 13, 13
+; CHECK-NEXT: blr
+}
+
+define fastcc <4 x i32> @v13(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret <4 x i32> %v13
+
+; CHECK-LABEL: @v13
+; CHECK: addi [[REG1:[0-9]+]], 1, 96
+; CHECK-NEXT: lvx 2, 0, [[REG1]]
+; CHECK-NEXT: blr
+}
+
+define fastcc <4 x i32> @v14(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret <4 x i32> %v14
+
+; CHECK-LABEL: @v14
+; CHECK: addi [[REG1:[0-9]+]], 1, 128
+; CHECK-NEXT: lvx 2, 0, [[REG1]]
+; CHECK-NEXT: blr
+}
+
+define fastcc <4 x i32> @v15(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 {
+  ret <4 x i32> %v15
+
+; CHECK-LABEL: @v15
+; CHECK: addi [[REG1:[0-9]+]], 1, 160
+; CHECK-NEXT: lvx 2, 0, [[REG1]]
+; CHECK-NEXT: blr
+}
+
+define void @cg1(i64 %v) #0 {
+  tail call fastcc i64 @g1(i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cg1
+; CHECK-NOT: {{^[ \t]*}}mr 3,
+; CHECK: blr
+}
+
+define void @cg2(i64 %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cg2
+; CHECK: mr 4, 3
+; CHECK: blr
+}
+
+define void @cg3(i64 %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cg3
+; CHECK: mr 5, 3
+; CHECK: blr
+}
+
+define void @cg4(i64 %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cg4
+; CHECK: mr 6, 3
+; CHECK: blr
+}
+
+define void @cg5(i64 %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cg5
+; CHECK: mr 7, 3
+; CHECK: blr
+}
+
+define void @cg6(i64 %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cg6
+; CHECK: mr 8, 3
+; CHECK: blr
+}
+
+define void @cg7(i64 %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cg7
+; CHECK: mr 9, 3
+; CHECK: blr
+}
+
+define void @cg8(i64 %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cg8
+; CHECK: mr 10, 3
+; CHECK: blr
+}
+
+define void @cg9(i64 %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cg9
+; CHECK: mr [[REG1:[0-9]+]], 3
+; CHECK: std [[REG1]], 48(1)
+; CHECK: blr
+}
+
+define void @cg10(i64 %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cg10
+; CHECK: mr [[REG1:[0-9]+]], 3
+; CHECK: std [[REG1]], 56(1)
+; CHECK: blr
+}
+
+define void @cg11(i64 %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cg11
+; CHECK: mr [[REG1:[0-9]+]], 3
+; CHECK: std [[REG1]], 64(1)
+; CHECK: blr
+}
+
+define void @cf1(double %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double %v, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cf1
+; CHECK-NOT: fmr 1,
+; CHECK: blr
+}
+
+define void @cf2(double %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double %v, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cf2
+; CHECK: fmr 2, 1
+; CHECK: blr
+}
+
+define void @cf3(double %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double %v, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cf3
+; CHECK: fmr 3, 1
+; CHECK: blr
+}
+
+define void @cf4(double %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double %v, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cf4
+; CHECK: fmr 4, 1
+; CHECK: blr
+}
+
+define void @cf5(double %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double %v, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cf5
+; CHECK: fmr 5, 1
+; CHECK: blr
+}
+
+define void @cf14(double %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double %v, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cf14
+; CHECK: stfd 1, 120(1)
+; CHECK: blr
+}
+
+define void @cf15(double %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double %v, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cf15
+; CHECK: stfd 1, 152(1)
+; CHECK: blr
+}
+
+define void @cv2(<4 x i32> %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> %v, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cv2
+; CHECK: vor 3, 2, 2
+; CHECK: blr
+}
+
+define void @cv3(<4 x i32> %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> %v, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cv3
+; CHECK: vor 4, 2, 2
+; CHECK: blr
+}
+
+define void @cv13(<4 x i32> %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> %v, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cv13
+; CHECK: li [[REG1:[0-9]+]], 96
+; CHECK: stvx 2, 1, [[REG1]]
+; CHECK: blr
+}
+
+define void @cv14(<4 x i32> %v) #0 {
+  tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> %v, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
+  ret void
+
+; CHECK-LABEL: @cv14
+; CHECK: li [[REG1:[0-9]+]], 128
+; CHECK: stvx 2, 1, [[REG1]]
+; CHECK: blr
+}
+
+attributes #0 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/ppc64-func-desc-hoist.ll b/test/CodeGen/PowerPC/ppc64-func-desc-hoist.ll
new file mode 100644
index 000000000000..57577f90109c
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc64-func-desc-hoist.ll
@@ -0,0 +1,47 @@
+; RUN: llc -mcpu=a2 < %s | FileCheck %s -check-prefix=INVFUNCDESC
+; RUN: llc -mcpu=a2 -mattr=-invariant-function-descriptors < %s | FileCheck %s -check-prefix=NONINVFUNCDESC
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define void @bar(void (...)* nocapture %x) #0 {
+entry:
+  %callee.knr.cast = bitcast void (...)* %x to void ()*
+  br label %for.body
+
+; INVFUNCDESC-LABEL: @bar
+; INVFUNCDESC-DAG: ld [[REG1:[0-9]+]], 8(3)
+; INVFUNCDESC-DAG: ld [[REG2:[0-9]+]], 16(3)
+; INVFUNCDESC-DAG: ld [[REG3:[0-9]+]], 0(3)
+
+; INVFUNCDESC: %for.body
+; INVFUNCDESC: std 2, 40(1)
+; INVFUNCDESC-DAG: mtctr [[REG3]]
+; INVFUNCDESC-DAG: mr 11, [[REG2]]
+; INVFUNCDESC-DAG: mr 2, [[REG1]]
+; INVFUNCDESC: bctrl
+; INVFUNCDESC-NEXT: ld 2, 40(1)
+
+; NONINVFUNCDESC-LABEL: @bar
+; NONINVFUNCDESC: %for.body
+; NONINVFUNCDESC: std 2, 40(1)
+; NONINVFUNCDESC-DAG: ld 3, 0(30)
+; NONINVFUNCDESC-DAG: ld 11, 16(30)
+; NONINVFUNCDESC-DAG: ld 2, 8(30)
+; NONINVFUNCDESC: mtctr 3
+; NONINVFUNCDESC: bctrl
+; NONINVFUNCDESC-NEXT: ld 2, 40(1)
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  tail call void %callee.knr.cast() #0
+  %inc = add nuw nsw i32 %i.02, 1
+  %exitcond = icmp eq i32 %inc, 1600000000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
+
+attributes #0 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/ppc64-gep-opt.ll b/test/CodeGen/PowerPC/ppc64-gep-opt.ll
index 14cf9a7e8382..f238908fcaf2 100644
--- a/test/CodeGen/PowerPC/ppc64-gep-opt.ll
+++ b/test/CodeGen/PowerPC/ppc64-gep-opt.ll
@@ -14,14 +14,14 @@ target triple = "powerpc64-unknown-linux-gnu"
 ; Check that when two complex GEPs are used in two basic blocks, LLVM can
 ; elimilate the common subexpression for the second use.
 define void @test_GEP_CSE([240 x %struct]* %string, i32* %adj, i32 %lib, i64 %idxprom) {
-  %liberties = getelementptr [240 x %struct]* %string, i64 1, i64 %idxprom, i32 3
-  %1 = load i32* %liberties, align 4
+  %liberties = getelementptr [240 x %struct], [240 x %struct]* %string, i64 1, i64 %idxprom, i32 3
+  %1 = load i32, i32* %liberties, align 4
   %cmp = icmp eq i32 %1, %lib
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %origin = getelementptr [240 x %struct]* %string, i64 1, i64 %idxprom, i32 2
-  %2 = load i32* %origin, align 4
+  %origin = getelementptr [240 x %struct], [240 x %struct]* %string, i64 1, i64 %idxprom, i32 2
+  %2 = load i32, i32* %origin, align 4
   store i32 %2, i32* %adj, align 4
   br label %if.end
 
@@ -44,11 +44,11 @@ if.end:                                           ; preds = %if.then, %entry
 ; CHECK-UseAA-LABEL: @test_GEP_CSE(
 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = bitcast [240 x %struct]* %string to i8*
 ; CHECK-UseAA: [[IDX:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96
-; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8* [[PTR0]], i64 [[IDX]]
-; CHECK-UseAA: getelementptr i8* [[PTR1]], i64 23052
+; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8, i8* [[PTR0]], i64 [[IDX]]
+; CHECK-UseAA: getelementptr i8, i8* [[PTR1]], i64 23052
 ; CHECK-UseAA: bitcast
 ; CHECK-UseAA: if.then:
-; CHECK-UseAA: getelementptr i8* [[PTR1]], i64 23048
+; CHECK-UseAA: getelementptr i8, i8* [[PTR1]], i64 23048
 ; CHECK-UseAA: bitcast
 
 %class.my = type { i32, [128 x i32], i32, [256 x %struct.pt]}
@@ -59,10 +59,10 @@ if.end:                                           ; preds = %if.then, %entry
 ; calculation and code gen can generate a better addressing mode for the second
 ; use.
 define void @test_GEP_across_BB(%class.my* %this, i64 %idx) {
-  %1 = getelementptr %class.my* %this, i64 0, i32 3, i64 %idx, i32 1
-  %2 = load i32* %1, align 4
-  %3 = getelementptr %class.my* %this, i64 0, i32 3, i64 %idx, i32 2
-  %4 = load i32* %3, align 4
+  %1 = getelementptr %class.my, %class.my* %this, i64 0, i32 3, i64 %idx, i32 1
+  %2 = load i32, i32* %1, align 4
+  %3 = getelementptr %class.my, %class.my* %this, i64 0, i32 3, i64 %idx, i32 2
+  %4 = load i32, i32* %3, align 4
   %5 = icmp eq i32 %2, %4
   br i1 %5, label %if.true, label %exit
 
@@ -90,12 +90,12 @@ exit:
 
 ; CHECK-UseAA-LABEL: test_GEP_across_BB(
 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = getelementptr
-; CHECK-UseAA: getelementptr i8* [[PTR0]], i64 528
-; CHECK-UseAA: getelementptr i8* [[PTR0]], i64 532
+; CHECK-UseAA: getelementptr i8, i8* [[PTR0]], i64 528
+; CHECK-UseAA: getelementptr i8, i8* [[PTR0]], i64 532
 ; CHECK-UseAA: if.true:
-; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8* [[PTR0]], i64 532
+; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, i8* [[PTR0]], i64 532
 ; CHECK-UseAA: exit:
-; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8* [[PTR0]], i64 528
+; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, i8* [[PTR0]], i64 528
 
 %struct.S = type { float, double }
 @struct_array = global [1024 x %struct.S] zeroinitializer, align 16
@@ -109,7 +109,7 @@ define double* @test-struct_1(i32 %i) {
 entry:
   %add = add nsw i32 %i, 5
   %idxprom = sext i32 %add to i64
-  %p = getelementptr [1024 x %struct.S]* @struct_array, i64 0, i64 %idxprom, i32 1
+  %p = getelementptr [1024 x %struct.S], [1024 x %struct.S]* @struct_array, i64 0, i64 %idxprom, i32 1
   ret double* %p
 }
 ; CHECK-NoAA-LABEL: @test-struct_1(
@@ -117,7 +117,7 @@ entry:
 ; CHECK-NoAA: add i64 %{{[a-zA-Z0-9]+}}, 88
 
 ; CHECK-UseAA-LABEL: @test-struct_1(
-; CHECK-UseAA: getelementptr i8* %{{[a-zA-Z0-9]+}}, i64 88
+; CHECK-UseAA: getelementptr i8, i8* %{{[a-zA-Z0-9]+}}, i64 88
 
 %struct3 = type { i64, i32 }
 %struct2 = type { %struct3, i32 }
@@ -131,7 +131,7 @@ entry:
 define %struct2* @test-struct_2(%struct0* %ptr, i64 %idx) {
 entry:
   %arrayidx = add nsw i64 %idx, -2
-  %ptr2 = getelementptr %struct0* %ptr, i64 0, i32 3, i64 %arrayidx, i32 1
+  %ptr2 = getelementptr %struct0, %struct0* %ptr, i64 0, i32 3, i64 %arrayidx, i32 1
   ret %struct2* %ptr2
 }
 ; CHECK-NoAA-LABEL: @test-struct_2(
@@ -139,14 +139,14 @@ entry:
 ; CHECK-NoAA: add i64 %{{[a-zA-Z0-9]+}}, -40
 
 ; CHECK-UseAA-LABEL: @test-struct_2(
-; CHECK-UseAA: getelementptr i8* %{{[a-zA-Z0-9]+}}, i64 -40
+; CHECK-UseAA: getelementptr i8, i8* %{{[a-zA-Z0-9]+}}, i64 -40
 
 ; Test that when a index is added from two constant, SeparateConstOffsetFromGEP
 ; pass does not generate incorrect result.
 define void @test_const_add([3 x i32]* %in) {
   %inc = add nsw i32 2, 1
   %idxprom = sext i32 %inc to i64
-  %arrayidx = getelementptr [3 x i32]* %in, i64 %idxprom, i64 2
+  %arrayidx = getelementptr [3 x i32], [3 x i32]* %in, i64 %idxprom, i64 2
   store i32 0, i32* %arrayidx, align 4
   ret void
 }
diff --git a/test/CodeGen/PowerPC/ppc64-i128-abi.ll b/test/CodeGen/PowerPC/ppc64-i128-abi.ll
new file mode 100644
index 000000000000..993aec24c8fb
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc64-i128-abi.ll
@@ -0,0 +1,274 @@
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-LE
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-BE
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-BE-NOVSX
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-LE-NOVSX
+
+@x = common global <1 x i128> zeroinitializer, align 16
+@y = common global <1 x i128> zeroinitializer, align 16
+@a = common global i128 zeroinitializer, align 16
+@b = common global i128 zeroinitializer, align 16
+
+; VSX:
+;   %a is passed in register 34
+;   The value of 1 is stored in the TOC.
+;   On LE, ensure the value of 1 is swapped before being used (using xxswapd).
+; VMX (no VSX): 
+;   %a is passed in register 2
+;   The value of 1 is stored in the TOC.
+;   No swaps are necessary when using P8 Vector instructions on LE
+define <1 x i128> @v1i128_increment_by_one(<1 x i128> %a) nounwind {
+       %tmp = add <1 x i128> %a, <i128 1>
+       ret <1 x i128> %tmp  
+
+; FIXME: Seems a 128-bit literal is materialized by loading from the TOC. There
+;        should be a better way of doing this.
+
+; CHECK-LE-LABEL: @v1i128_increment_by_one
+; CHECK-LE: lxvd2x [[VAL:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK-LE: xxswapd 35, [[VAL]]
+; CHECK-LE: vadduqm 2, 2, 3
+; CHECK-LE: blr
+
+; CHECK-BE-LABEL: @v1i128_increment_by_one
+; CHECK-BE: lxvd2x 35, {{[0-9]+}}, {{[0-9]+}}
+; CHECK-BE-NOT: xxswapd 
+; CHECK-BE: vadduqm 2, 2, 3 
+; CHECK-BE-NOT: xxswapd 34, {{[0-9]+}}
+; CHECK-BE: blr
+
+; CHECK-NOVSX-LABEL: @v1i128_increment_by_one
+; CHECK-NOVSX-NOT: xxswapd {{[0-9]+}}, {{[0-9]+}}
+; CHECK-NOVSX-NOT: stxvd2x {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK-NOVSX: lvx [[VAL:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK-NOVSX-NOT: lxvd2x {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK-NOVSX-NOT: xxswapd {{[0-9]+}}, {{[0-9]+}}
+; CHECK-NOVSX: vadduqm 2, 2, [[VAL]]
+; CHECK-NOVSX: blr
+}
+
+; VSX:
+;   %a is passed in register 34
+;   %b is passed in register 35
+;   No swaps are necessary when using P8 Vector instructions on LE
+; VMX (no VSX):
+;   %a is passewd in register 2
+;   %b is passed in register 3
+;   On LE, do not need to swap contents of 2 and 3 because the lvx/stvx 
+;   instructions no not swap elements
+define <1 x i128> @v1i128_increment_by_val(<1 x i128> %a, <1 x i128> %b) nounwind {
+       %tmp = add <1 x i128> %a, %b
+       ret <1 x i128> %tmp
+
+; CHECK-LE-LABEL: @v1i128_increment_by_val
+; CHECK-LE-NOT: xxswapd
+; CHECK-LE: adduqm 2, 2, 3
+; CHECK-LE: blr
+
+; CHECK-BE-LABEL: @v1i128_increment_by_val
+; CHECK-BE-NOT: xxswapd {{[0-9]+}}, 34
+; CHECK-BE-NOT: xxswapd {{[0-9]+}}, 35
+; CHECK-BE-NOT: xxswapd 34, [[RESULT]]
+; CHECK-BE: adduqm 2, 2, 3
+; CHECK-BE: blr
+
+; CHECK-NOVSX-LABEL: @v1i128_increment_by_val
+; CHECK-NOVSX-NOT: xxswapd 34, [[RESULT]]
+; CHECK-NOVSX: adduqm 2, 2, 3
+; CHECK-NOVSX: blr
+}
+
+; Little Endian (VSX and VMX):
+;   Lower 64-bits of %a are passed in register 3
+;   Upper 64-bits of %a are passed in register 4
+;   Increment lower 64-bits using addic (immediate value of 1)
+;   Increment upper 64-bits using add zero extended
+;   Results are placed in registers 3 and 4
+; Big Endian (VSX and VMX)
+;   Lower 64-bits of %a are passed in register 4
+;   Upper 64-bits of %a are passed in register 3
+;   Increment lower 64-bits using addic (immediate value of 1)
+;   Increment upper 64-bits using add zero extended
+;   Results are placed in registers 3 and 4
+define i128 @i128_increment_by_one(i128 %a) nounwind {
+       %tmp =  add i128 %a,  1
+       ret i128 %tmp
+; CHECK-LE-LABEL: @i128_increment_by_one
+; CHECK-LE: addic 3, 3, 1
+; CHECK-LE-NEXT: addze 4, 4
+; CHECK-LE: blr
+
+; CHECK-BE-LABEL: @i128_increment_by_one
+; CHECK-BE: addic 4, 4, 1
+; CHECK-BE-NEXT: addze 3, 3
+; CHECK-BE: blr
+
+; CHECK-LE-NOVSX-LABEL: @i128_increment_by_one
+; CHECK-LE-NOVSX: addic 3, 3, 1
+; CHECK-LE-NOVSX-NEXT: addze 4, 4
+; CHECK-LE-NOVSX: blr
+
+; CHECK-BE-NOVSX-LABEL: @i128_increment_by_one
+; CHECK-BE-NOVSX: addic 4, 4, 1
+; CHECK-BE-NOVSX-NEXT: addze 3, 3
+; CHECK-BE-NOVSX: blr
+}
+
+; Little Endian (VSX and VMX):
+;   Lower 64-bits of %a are passed in register 3
+;   Upper 64-bits of %a are passed in register 4
+;   Lower 64-bits of %b are passed in register 5
+;   Upper 64-bits of %b are passed in register 6
+;   Add the lower 64-bits using addc on registers 3 and 5
+;   Add the upper 64-bits using adde on registers 4 and 6
+;   Registers 3 and 4 should hold the result
+; Big Endian (VSX and VMX):
+;   Upper 64-bits of %a are passed in register 3
+;   Lower 64-bits of %a are passed in register 4
+;   Upper 64-bits of %b are passed in register 5
+;   Lower 64-bits of %b are passed in register 6
+;   Add the lower 64-bits using addc on registers 4 and 6
+;   Add the upper 64-bits using adde on registers 3 and 5
+;   Registers 3 and 4 should hold the result
+define i128 @i128_increment_by_val(i128 %a, i128 %b) nounwind {
+       %tmp =  add i128 %a, %b
+       ret i128 %tmp
+; CHECK-LE-LABEL: @i128_increment_by_val
+; CHECK-LE: addc 3, 3, 5
+; CHECK-LE-NEXT: adde 4, 4, 6
+; CHECK-LE: blr
+
+; CHECK-BE-LABEL: @i128_increment_by_val
+; CHECK-BE: addc 4, 4, 6
+; CHECK-BE-NEXT: adde 3, 3, 5
+; CHECK-BE: blr
+
+; CHECK-LE-NOVSX-LABEL: @i128_increment_by_val
+; CHECK-LE-NOVSX: addc 3, 3, 5
+; CHECK-LE-NOVSX-NEXT: adde 4, 4, 6
+; CHECK-LE-NOVSX: blr
+
+; CHECK-BE-NOVSX-LABEL: @i128_increment_by_val
+; CHECK-BE-NOVSX: addc 4, 4, 6
+; CHECK-BE-NOVSX-NEXT: adde 3, 3, 5
+; CHECK-BE-NOVSX: blr
+}
+
+
+; Callsites for the routines defined above. 
+; Ensure the parameters are loaded in the same order that is expected by the 
+; callee. See comments for individual functions above for details on registers
+; used for parameters.
+define <1 x i128> @call_v1i128_increment_by_one() nounwind {
+       %tmp = load <1 x i128>, <1 x i128>* @x, align 16
+       %ret = call <1 x i128> @v1i128_increment_by_one(<1 x i128> %tmp)
+       ret <1 x i128> %ret
+
+; CHECK-LE-LABEL: @call_v1i128_increment_by_one
+; CHECK-LE: lxvd2x [[PARAM:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK-LE: xxswapd 34, [[PARAM]]
+; CHECK-LE: bl v1i128_increment_by_one
+; CHECK-LE: blr
+
+; CHECK-BE-LABEL: @call_v1i128_increment_by_one
+; CHECK-BE: lxvw4x 34, {{[0-9]+}}, {{[0-9]+}}
+; CHECK-BE-NOT: xxswapd 34, {{[0-9]+}}
+; CHECK-BE: bl v1i128_increment_by_one
+; CHECK-BE: blr
+
+; CHECK-NOVSX-LABEL: @call_v1i128_increment_by_one
+; CHECK-NOVSX: lvx 2, {{[0-9]+}}, {{[0-9]+}}
+; CHECK-NOVSX-NOT: xxswapd {{[0-9]+}}, {{[0-9]+}}
+; CHECK-NOVSX: bl v1i128_increment_by_one
+; CHECK-NOVSX: blr
+}
+
+define <1 x i128> @call_v1i128_increment_by_val() nounwind {
+       %tmp = load <1 x i128>, <1 x i128>* @x, align 16
+       %tmp2 = load <1 x i128>, <1 x i128>* @y, align 16
+       %ret = call <1 x i128> @v1i128_increment_by_val(<1 x i128> %tmp, <1 x i128> %tmp2)
+       ret <1 x i128> %ret
+
+; CHECK-LE-LABEL: @call_v1i128_increment_by_val
+; CHECK-LE: lxvd2x [[PARAM1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK-LE: lxvd2x [[PARAM2:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK-LE-DAG: xxswapd 34, [[PARAM1]]
+; CHECK-LE-DAG: xxswapd 35, [[PARAM2]]
+; CHECK-LE: bl v1i128_increment_by_val
+; CHECK-LE: blr
+
+; CHECK-BE-LABEL: @call_v1i128_increment_by_val
+
+
+; CHECK-BE-DAG: lxvw4x 35, {{[0-9]+}}, {{[0-9]+}}
+; CHECK-BE-NOT: xxswapd 34, {{[0-9]+}}
+; CHECK-BE-NOT: xxswapd 35, {{[0-9]+}}
+; CHECK-BE: bl v1i128_increment_by_val
+; CHECK-BE: blr
+
+; CHECK-NOVSX-LABEL: @call_v1i128_increment_by_val
+; CHECK-NOVSX-DAG: lvx 2, {{[0-9]+}}, {{[0-9]+}}
+; CHECK-NOVSX-DAG: lvx 3, {{[0-9]+}}, {{[0-9]+}}
+; CHECK-NOVSX-NOT: xxswapd 34, {{[0-9]+}}
+; CHECK-NOVSX-NOT: xxswapd 35, {{[0-9]+}}
+; CHECK-NOVSX: bl v1i128_increment_by_val
+; CHECK-NOVSX: blr
+
+}
+
+define i128 @call_i128_increment_by_one() nounwind {
+       %tmp = load i128, i128* @a, align 16
+       %ret = call i128 @i128_increment_by_one(i128 %tmp)
+       ret i128 %ret
+;       %ret4 = call i128 @i128_increment_by_val(i128 %tmp2, i128 %tmp2)
+; CHECK-LE-LABEL: @call_i128_increment_by_one
+; CHECK-LE-DAG: ld 3, 0([[BASEREG:[0-9]+]])
+; CHECK-LE-DAG: ld 4, 8([[BASEREG]])
+; CHECK-LE: bl i128_increment_by_one
+; CHECK-LE: blr
+
+; CHECK-BE-LABEL: @call_i128_increment_by_one
+; CHECK-BE-DAG: ld 3, 0([[BASEREG:[0-9]+]])
+; CHECK-BE-DAG: ld 4, 8([[BASEREG]])
+; CHECK-BE: bl i128_increment_by_one
+; CHECK-BE: blr
+
+; CHECK-NOVSX-LABEL: @call_i128_increment_by_one
+; CHECK-NOVSX-DAG: ld 3, 0([[BASEREG:[0-9]+]])
+; CHECK-NOVSX-DAG: ld 4, 8([[BASEREG]])
+; CHECK-NOVSX: bl i128_increment_by_one
+; CHECK-NOVSX: blr
+}
+
+define i128 @call_i128_increment_by_val() nounwind {
+       %tmp = load i128, i128* @a, align 16
+       %tmp2 = load i128, i128* @b, align 16
+       %ret = call i128 @i128_increment_by_val(i128 %tmp, i128 %tmp2)
+       ret i128 %ret
+; CHECK-LE-LABEL: @call_i128_increment_by_val
+; CHECK-LE-DAG: ld 3, 0([[P1BASEREG:[0-9]+]])
+; CHECK-LE-DAG: ld 4, 8([[P1BASEREG]])
+; CHECK-LE-DAG: ld 5, 0([[P2BASEREG:[0-9]+]])
+; CHECK-LE-DAG: ld 6, 8([[P2BASEREG]])
+; CHECK-LE: bl i128_increment_by_val
+; CHECK-LE: blr
+
+; CHECK-BE-LABEL: @call_i128_increment_by_val
+; CHECK-BE-DAG: ld 3, 0([[P1BASEREG:[0-9]+]])
+; CHECK-BE-DAG: ld 4, 8([[P1BASEREG]])
+; CHECK-BE-DAG: ld 5, 0([[P2BASEREG:[0-9]+]])
+; CHECK-BE-DAG: ld 6, 8([[P2BASEREG]])
+; CHECK-BE: bl i128_increment_by_val
+; CHECK-BE: blr
+
+; CHECK-NOVSX-LABEL: @call_i128_increment_by_val
+; CHECK-NOVSX-DAG: ld 3, 0([[P1BASEREG:[0-9]+]])
+; CHECK-NOVSX-DAG: ld 4, 8([[P1BASEREG]])
+; CHECK-NOVSX-DAG: ld 5, 0([[P2BASEREG:[0-9]+]])
+; CHECK-NOVSX-DAG: ld 6, 8([[P2BASEREG]])
+; CHECK-NOVSX: bl i128_increment_by_val
+; CHECK-NOVSX: blr
+}
+
+
diff --git a/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll b/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll
new file mode 100644
index 000000000000..e8617ccfc8a5
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll
@@ -0,0 +1,19 @@
+; Test the ICBT instruction is not emitted on POWER7
+; Based on the ppc64-prefetch.ll test
+; RUN: not llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s 2>&1 | FileCheck %s
+ 
+declare void @llvm.prefetch(i8*, i32, i32, i32)
+
+define void @test(i8* %a, ...) nounwind {
+entry:
+  call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 0)
+  ret void
+
+; FIXME: Crashing is not really the correct behavior here, we really should just emit nothing
+; CHECK: Cannot select: 0x{{[0-9,a-f]+}}: ch = Prefetch 
+; CHECK: 0x{{[0-9,a-f]+}}: i32 = Constant<0> 
+; CHECK-NEXT: 0x{{[0-9,a-f]+}}: i32 = Constant<3>
+; CHECK-NEXT: 0x{{[0-9,a-f]+}}: i32 = Constant<0>
+
+}
+
diff --git a/test/CodeGen/PowerPC/ppc64-icbt-pwr8.ll b/test/CodeGen/PowerPC/ppc64-icbt-pwr8.ll
new file mode 100644
index 000000000000..a0f084a6bf96
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc64-icbt-pwr8.ll
@@ -0,0 +1,16 @@
+; Test the ICBT instruction on POWER8
+; Copied from the ppc64-prefetch.ll test
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+
+declare void @llvm.prefetch(i8*, i32, i32, i32)
+
+define void @test(i8* %a, ...) nounwind {
+entry:
+  call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 0)
+  ret void
+
+; CHECK-LABEL: @test
+; CHECK: icbt
+}
+
+
diff --git a/test/CodeGen/PowerPC/ppc64-linux-func-size.ll b/test/CodeGen/PowerPC/ppc64-linux-func-size.ll
index e1d50bac51a2..fb017bc224ba 100644
--- a/test/CodeGen/PowerPC/ppc64-linux-func-size.ll
+++ b/test/CodeGen/PowerPC/ppc64-linux-func-size.ll
@@ -3,11 +3,11 @@
 ; CHECK:      .section	.opd,"aw",@progbits
 ; CHECK-NEXT: test1:
 ; CHECK-NEXT:	.align 3
-; CHECK-NEXT:	.quad .L.test1
+; CHECK-NEXT:	.quad .L[[BEGIN:.*]]
 ; CHECK-NEXT:	.quad .TOC.@tocbase
 ; CHECK-NEXT:   .quad 0
 ; CHECK-NEXT:	.text
-; CHECK-NEXT: .L.test1:
+; CHECK-NEXT: .L[[BEGIN]]:
 
 define i32 @test1(i32 %a) nounwind {
 entry:
@@ -19,4 +19,4 @@ entry:
 ; however, using this directive with recent binutils will result in the error:
 ;  .size expression for XXX does not evaluate to a constant
 ; so we must use the label which actually tags the start of the function.
-; CHECK: .size	test1, .Ltmp0-.L.test1
+; CHECK: .size	test1, .Lfunc_end0-.L[[BEGIN]]
diff --git a/test/CodeGen/PowerPC/ppc64-nonfunc-calls.ll b/test/CodeGen/PowerPC/ppc64-nonfunc-calls.ll
index 9f56f0102b7c..b1d3f39e2f89 100644
--- a/test/CodeGen/PowerPC/ppc64-nonfunc-calls.ll
+++ b/test/CodeGen/PowerPC/ppc64-nonfunc-calls.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=ppc64 < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
diff --git a/test/CodeGen/PowerPC/ppc64-patchpoint.ll b/test/CodeGen/PowerPC/ppc64-patchpoint.ll
index 5e58fdab2168..67b26268a3a3 100644
--- a/test/CodeGen/PowerPC/ppc64-patchpoint.ll
+++ b/test/CodeGen/PowerPC/ppc64-patchpoint.ll
@@ -1,6 +1,8 @@
-; RUN: llc                             < %s | FileCheck %s
-; RUN: llc -fast-isel -fast-isel-abort < %s | FileCheck %s
-target datalayout = "E-m:e-i64:64-n32:64"
+; RUN: llc                             < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
+; RUN: llc -fast-isel -fast-isel-abort=1 < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu                             < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -fast-isel -fast-isel-abort=1 < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
+
 target triple = "powerpc64-unknown-linux-gnu"
 
 ; Trivial patchpoint codegen
@@ -9,26 +11,26 @@ define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
 ; CHECK-LABEL: trivial_patchpoint_codegen:
 
-; CHECK: li 11, -8531
-; CHECK-NEXT: rldic 11, 11, 32, 16
-; CHECK-NEXT: oris 11, 11, 48879
-; CHECK-NEXT: ori 11, 11, 51966
-; CHECK-NEXT: mtctr 11
+; CHECK: li 12, -8531
+; CHECK-NEXT: rldic 12, 12, 32, 16
+; CHECK-NEXT: oris 12, 12, 48879
+; CHECK-NEXT: ori 12, 12, 51966
+; CHECK-NEXT: mtctr 12
 ; CHECK-NEXT: bctrl
 
-; CHECK: li 11, -8531
-; CHECK-NEXT: rldic 11, 11, 32, 16
-; CHECK-NEXT: oris 11, 11, 48879
-; CHECK-NEXT: ori 11, 11, 51967
-; CHECK-NEXT: mtctr 11
+; CHECK: li 12, -8531
+; CHECK-NEXT: rldic 12, 12, 32, 16
+; CHECK-NEXT: oris 12, 12, 48879
+; CHECK-NEXT: ori 12, 12, 51967
+; CHECK-NEXT: mtctr 12
 ; CHECK-NEXT: bctrl
 
 ; CHECK: blr
 
   %resolveCall2 = inttoptr i64 244837814094590 to i8*
-  %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 24, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
+  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 24, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
   %resolveCall3 = inttoptr i64 244837814094591 to i8*
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 3, i32 24, i8* %resolveCall3, i32 2, i64 %p1, i64 %result)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 24, i8* %resolveCall3, i32 2, i64 %p1, i64 %result)
   ret i64 %result
 }
 
@@ -36,9 +38,11 @@ entry:
 ; as a leaf function.
 ;
 ; CHECK-LABEL: caller_meta_leaf
-; CHECK: stdu 1, -80(1)
+; CHECK-BE: stdu 1, -80(1)
+; CHECK-LE: stdu 1, -64(1)
 ; CHECK: Ltmp
-; CHECK: addi 1, 1, 80
+; CHECK-BE: addi 1, 1, 80
+; CHECK-LE: addi 1, 1, 64
 ; CHECK: blr
 
 define void @caller_meta_leaf() {
@@ -47,7 +51,7 @@ entry:
   store i64 11, i64* %metadata
   store i64 12, i64* %metadata
   store i64 13, i64* %metadata
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
   ret void
 }
 
@@ -59,15 +63,15 @@ define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, i64* %tmp33, i64
 entry:
   %tmp80 = add i64 %tmp79, -16
   %tmp81 = inttoptr i64 %tmp80 to i64*
-  %tmp82 = load i64* %tmp81, align 8
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 14, i32 8, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82)
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 15, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
-  %tmp83 = load i64* %tmp33, align 8
+  %tmp82 = load i64, i64* %tmp81, align 8
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 8, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 15, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
+  %tmp83 = load i64, i64* %tmp33, align 8
   %tmp84 = add i64 %tmp83, -24
   %tmp85 = inttoptr i64 %tmp84 to i64*
-  %tmp86 = load i64* %tmp85, align 8
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 17, i32 8, i64 %arg, i64 %tmp10, i64 %tmp86)
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 18, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
+  %tmp86 = load i64, i64* %tmp85, align 8
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 17, i32 8, i64 %arg, i64 %tmp10, i64 %tmp86)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 18, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
   ret i64 10
 }
 
@@ -83,7 +87,7 @@ entry:
 ; CHECK-NEXT: nop
 ; CHECK-NOT:  nop
 ; CHECK: blr
-  %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* null, i32 2, i64 %p1, i64 %p2)
+  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* null, i32 2, i64 %p1, i64 %p2)
   ret void
 }
 
diff --git a/test/CodeGen/PowerPC/ppc64-r2-alloc.ll b/test/CodeGen/PowerPC/ppc64-r2-alloc.ll
new file mode 100644
index 000000000000..87292d821294
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc64-r2-alloc.ll
@@ -0,0 +1,81 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define signext i32 @foo(i32 signext %a, i32 signext %d) #0 {
+entry:
+  %div = sdiv i32 %a, %d
+  %div1 = sdiv i32 %div, %d
+  %div2 = sdiv i32 %div1, %d
+  %div3 = sdiv i32 %div2, %d
+  %div4 = sdiv i32 %div3, %d
+  %div5 = sdiv i32 %div4, %d
+  %div6 = sdiv i32 %div5, %d
+  %div7 = sdiv i32 %div6, %d
+  %div8 = sdiv i32 %div7, %d
+  %div9 = sdiv i32 %div8, %d
+  %div10 = sdiv i32 %div9, %d
+  %div11 = sdiv i32 %div10, %d
+  %div12 = sdiv i32 %div11, %d
+  %div13 = sdiv i32 %div12, %d
+  %div14 = sdiv i32 %div13, %d
+  %div15 = sdiv i32 %div14, %d
+  %div16 = sdiv i32 %div15, %d
+  %div17 = sdiv i32 %div16, %d
+  %div18 = sdiv i32 %div17, %d
+  %div19 = sdiv i32 %div18, %d
+  %div20 = sdiv i32 %div19, %d
+  %div21 = sdiv i32 %div20, %d
+  %div22 = sdiv i32 %div21, %d
+  %div23 = sdiv i32 %div22, %d
+  %div24 = sdiv i32 %div23, %d
+  %div25 = sdiv i32 %div24, %d
+  %div26 = sdiv i32 %div25, %d
+  %div27 = sdiv i32 %div26, %d
+  %div28 = sdiv i32 %div27, %d
+  %div29 = sdiv i32 %div28, %d
+  %div30 = sdiv i32 %div29, %d
+  %div31 = sdiv i32 %div30, %d
+  %div32 = sdiv i32 %div31, %d
+  %div33 = sdiv i32 %div32, %div31
+  %div34 = sdiv i32 %div33, %div30
+  %div35 = sdiv i32 %div34, %div29
+  %div36 = sdiv i32 %div35, %div28
+  %div37 = sdiv i32 %div36, %div27
+  %div38 = sdiv i32 %div37, %div26
+  %div39 = sdiv i32 %div38, %div25
+  %div40 = sdiv i32 %div39, %div24
+  %div41 = sdiv i32 %div40, %div23
+  %div42 = sdiv i32 %div41, %div22
+  %div43 = sdiv i32 %div42, %div21
+  %div44 = sdiv i32 %div43, %div20
+  %div45 = sdiv i32 %div44, %div19
+  %div46 = sdiv i32 %div45, %div18
+  %div47 = sdiv i32 %div46, %div17
+  %div48 = sdiv i32 %div47, %div16
+  %div49 = sdiv i32 %div48, %div15
+  %div50 = sdiv i32 %div49, %div14
+  %div51 = sdiv i32 %div50, %div13
+  %div52 = sdiv i32 %div51, %div12
+  %div53 = sdiv i32 %div52, %div11
+  %div54 = sdiv i32 %div53, %div10
+  %div55 = sdiv i32 %div54, %div9
+  %div56 = sdiv i32 %div55, %div8
+  %div57 = sdiv i32 %div56, %div7
+  %div58 = sdiv i32 %div57, %div6
+  %div59 = sdiv i32 %div58, %div5
+  %div60 = sdiv i32 %div59, %div4
+  %div61 = sdiv i32 %div60, %div3
+  %div62 = sdiv i32 %div61, %div2
+  %div63 = sdiv i32 %div62, %div1
+  %div64 = sdiv i32 %div63, %div
+  ret i32 %div64
+}
+
+; This function will need to use all non-reserved GPRs (and then some), make
+; sure that r2 is among them.
+; CHECK-LABEL: @foo
+; CHECK: std 2,
+; CHECK: ld 2,
+; CHECK: blr
+
diff --git a/test/CodeGen/PowerPC/ppc64-smallarg.ll b/test/CodeGen/PowerPC/ppc64-smallarg.ll
index 0d5b078e217a..27aca1077cd6 100644
--- a/test/CodeGen/PowerPC/ppc64-smallarg.ll
+++ b/test/CodeGen/PowerPC/ppc64-smallarg.ll
@@ -17,7 +17,7 @@ define void @callee1(%struct.small_arg* noalias nocapture sret %agg.result, %str
 entry:
   %0 = bitcast %struct.small_arg* %x to i32*
   %1 = bitcast %struct.small_arg* %agg.result to i32*
-  %2 = load i32* %0, align 2
+  %2 = load i32, i32* %0, align 2
   store i32 %2, i32* %1, align 2
   ret void
 }
@@ -47,7 +47,7 @@ entry:
 
 define void @caller2() {
 entry:
-  %0 = load float* @gf, align 4
+  %0 = load float, float* @gf, align 4
   %call = tail call float @test2(float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float %0)
   ret void
 }
diff --git a/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll b/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll
index 368ddc5c8335..19d65b983b0a 100644
--- a/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll
+++ b/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll
@@ -16,7 +16,7 @@ entry:
 ; CHECK: mtlr [[REG1]]
 ; CHECK: blr
 
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  0, i32  32)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  0, i32  32)
   ret void
 }
 
diff --git a/test/CodeGen/PowerPC/ppc64-stackmap.ll b/test/CodeGen/PowerPC/ppc64-stackmap.ll
index 9be8d0c8ad44..917fa7422512 100644
--- a/test/CodeGen/PowerPC/ppc64-stackmap.ll
+++ b/test/CodeGen/PowerPC/ppc64-stackmap.ll
@@ -7,6 +7,40 @@
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
+; CHECK-LABEL: constantargs:
+; CHECK: {{^}}.L[[constantargs_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: osrinline:
+; CHECK: {{^}}.L[[osrinline_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: osrcold:
+; CHECK: {{^}}.L[[osrcold_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: propertyRead:
+; CHECK: {{^}}.L[[propertyRead_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: propertyWrite:
+; CHECK: {{^}}.L[[propertyWrite_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: jsVoidCall:
+; CHECK: {{^}}.L[[jsVoidCall_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: jsIntCall:
+; CHECK: {{^}}.L[[jsIntCall_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: spilledValue:
+; CHECK: {{^}}.L[[spilledValue_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: spilledStackMapValue:
+; CHECK: {{^}}.L[[spilledStackMapValue_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: liveConstant:
+; CHECK: {{^}}.L[[liveConstant_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: clobberLR:
+; CHECK: {{^}}.L[[clobberLR_BEGIN:.*]]:{{$}}
+
+
 ; CHECK-LABEL:  .section  .llvm_stackmaps
 ; CHECK-NEXT:  __LLVM_StackMaps:
 ; Header
@@ -36,7 +70,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 ; CHECK-NEXT:   .quad jsIntCall
 ; CHECK-NEXT:   .quad 128
 ; CHECK-NEXT:   .quad spilledValue
-; CHECK-NEXT:   .quad 320
+; CHECK-NEXT:   .quad 304
 ; CHECK-NEXT:   .quad spilledStackMapValue
 ; CHECK-NEXT:   .quad 224
 ; CHECK-NEXT:   .quad liveConstant
@@ -51,7 +85,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 ; Constant arguments
 ;
 ; CHECK-NEXT:   .quad   1
-; CHECK-NEXT:   .long   .L{{.*}}-.L.constantargs
+; CHECK-NEXT:   .long   .L{{.*}}-.L[[constantargs_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  4
 ; SmallConstant
@@ -78,13 +112,13 @@ target triple = "powerpc64-unknown-linux-gnu"
 define void @constantargs() {
 entry:
   %0 = inttoptr i64 244837814094590 to i8*
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 1, i32 24, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 24, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296)
   ret void
 }
 
 ; Inline OSR Exit
 ;
-; CHECK-LABEL:  .long   .L{{.*}}-.L.osrinline
+; CHECK:  .long   .L{{.*}}-.L[[osrinline_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
@@ -100,7 +134,7 @@ entry:
   ; Runtime void->void call.
   call void inttoptr (i64 244837814094590 to void ()*)()
   ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
   ret void
 }
 
@@ -108,7 +142,7 @@ entry:
 ;
 ; 2 live variables in register.
 ;
-; CHECK-LABEL:  .long   .L{{.*}}-.L.osrcold
+; CHECK:  .long   .L{{.*}}-.L[[osrcold_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
@@ -126,14 +160,14 @@ entry:
 cold:
   ; OSR patchpoint with 12-byte nop-slide and 2 live vars.
   %thunk = inttoptr i64 244837814094590 to i8*
-  call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 4, i32 24, i8* %thunk, i32 0, i64 %a, i64 %b)
+  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 24, i8* %thunk, i32 0, i64 %a, i64 %b)
   unreachable
 ret:
   ret void
 }
 
 ; Property Read
-; CHECK-LABEL:  .long   .L{{.*}}-.L.propertyRead
+; CHECK:  .long   .L{{.*}}-.L[[propertyRead_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ;
@@ -142,13 +176,13 @@ ret:
 define i64 @propertyRead(i64* %obj) {
 entry:
   %resolveRead = inttoptr i64 244837814094590 to i8*
-  %result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 24, i8* %resolveRead, i32 1, i64* %obj)
+  %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 24, i8* %resolveRead, i32 1, i64* %obj)
   %add = add i64 %result, 3
   ret i64 %add
 }
 
 ; Property Write
-; CHECK-LABEL:  .long   .L{{.*}}-.L.propertyWrite
+; CHECK:  .long   .L{{.*}}-.L[[propertyWrite_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
@@ -162,7 +196,7 @@ entry:
 define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
 entry:
   %resolveWrite = inttoptr i64 244837814094590 to i8*
-  call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 6, i32 24, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
+  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 24, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
   ret void
 }
 
@@ -170,7 +204,7 @@ entry:
 ;
 ; 2 live variables in registers.
 ;
-; CHECK-LABEL:  .long   .L{{.*}}-.L.jsVoidCall
+; CHECK:  .long   .L{{.*}}-.L[[jsVoidCall_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
@@ -184,7 +218,7 @@ entry:
 define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
   %resolveCall = inttoptr i64 244837814094590 to i8*
-  call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 7, i32 24, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
+  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 24, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
   ret void
 }
 
@@ -192,7 +226,7 @@ entry:
 ;
 ; 2 live variables in registers.
 ;
-; CHECK-LABEL:  .long   .L{{.*}}-.L.jsIntCall
+; CHECK:  .long   .L{{.*}}-.L[[jsIntCall_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
@@ -206,7 +240,7 @@ entry:
 define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
   %resolveCall = inttoptr i64 244837814094590 to i8*
-  %result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 8, i32 24, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
+  %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 24, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
   %add = add i64 %result, 3
   ret i64 %add
 }
@@ -215,7 +249,7 @@ entry:
 ;
 ; Verify 28 stack map entries.
 ;
-; CHECK-LABEL:  .long .L{{.*}}-.L.spilledValue
+; CHECK:  .long .L{{.*}}-.L[[spilledValue_BEGIN]]
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .short 28
 ;
@@ -226,7 +260,7 @@ entry:
 ; CHECK-NEXT:   .short 31
 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) {
 entry:
-  call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 11, i32 24, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
+  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 24, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
   ret void
 }
 
@@ -234,7 +268,7 @@ entry:
 ;
 ; Verify 30 stack map entries.
 ;
-; CHECK-LABEL:  .long .L{{.*}}-.L.spilledStackMapValue
+; CHECK:  .long .L{{.*}}-.L[[spilledStackMapValue_BEGIN]]
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .short 30
 ;
@@ -245,14 +279,14 @@ entry:
 ; CHECK-NEXT:   .short 31
 define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) {
 entry:
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29)
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29)
   ret void
 }
 
 
 ; Map a constant value.
 ;
-; CHECK-LABEL:  .long .L{{.*}}-.L.liveConstant
+; CHECK:  .long .L{{.*}}-.L[[liveConstant_BEGIN]]
 ; CHECK-NEXT:   .short 0
 ; 1 location
 ; CHECK-NEXT:   .short 1
@@ -263,13 +297,13 @@ entry:
 ; CHECK-NEXT:   .long   33
 
 define void @liveConstant() {
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 15, i32 8, i32 33)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 15, i32 8, i32 33)
   ret void
 }
 
 ; Map a value when LR is the only free register.
 ;
-; CHECK-LABEL:  .long .L{{.*}}-.L.clobberLR
+; CHECK:  .long .L{{.*}}-.L[[clobberLR_BEGIN]]
 ; CHECK-NEXT:   .short 0
 ; 1 location
 ; CHECK-NEXT:   .short 1
@@ -280,7 +314,7 @@ define void @liveConstant() {
 ; CHECK-NEXT:   .long   {{[0-9]+}}
 define void @clobberLR(i32 %a) {
   tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 16, i32 8, i32 %a)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 8, i32 %a)
   ret void
 }
 
diff --git a/test/CodeGen/PowerPC/ppc64-toc.ll b/test/CodeGen/PowerPC/ppc64-toc.ll
index f349919b7e99..7500ed606636 100644
--- a/test/CodeGen/PowerPC/ppc64-toc.ll
+++ b/test/CodeGen/PowerPC/ppc64-toc.ll
@@ -10,11 +10,12 @@ define i64 @access_int64(i64 %a) nounwind readonly {
 entry:
 ; CHECK-LABEL: access_int64:
 ; CHECK-NEXT: .align  3
-; CHECK-NEXT: .quad   .L.access_int64
+; CHECK-NEXT: .quad   .L[[BEGIN:.*]]
 ; CHECK-NEXT: .quad   .TOC.@tocbase
 ; CHECK-NEXT: .quad   0
 ; CHECK-NEXT: .text
-  %0 = load i64* @number64, align 8
+; CHECK-NEXT: .L[[BEGIN]]:
+  %0 = load i64, i64* @number64, align 8
 ; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
   %cmp = icmp eq i64 %0, %a
   %conv1 = zext i1 %cmp to i64 
@@ -25,7 +26,7 @@ define i64 @internal_static_var(i64 %a) nounwind {
 entry:
 ; CHECK-LABEL: internal_static_var:
 ; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
-  %0 = load i64* @internal_static_var.x, align 8
+  %0 = load i64, i64* @internal_static_var.x, align 8
   %cmp = icmp eq i64 %0, %a
   %conv1 = zext i1 %cmp to i64 
   ret i64 %conv1 
@@ -45,8 +46,8 @@ define i32 @access_double_array(double %a, i32 %i) nounwind readonly {
 entry:
 ; CHECK-LABEL: access_double_array:
   %idxprom = sext i32 %i to i64
-  %arrayidx = getelementptr inbounds [32 x double]* @double_array, i64 0, i64 %idxprom
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds [32 x double], [32 x double]* @double_array, i64 0, i64 %idxprom
+  %0 = load double, double* %arrayidx, align 8
 ; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
   %cmp = fcmp oeq double %0, %a
   %conv = zext i1 %cmp to i32
diff --git a/test/CodeGen/PowerPC/ppc64-zext.ll b/test/CodeGen/PowerPC/ppc64-zext.ll
index eb55445cc6c9..bbd4856babde 100644
--- a/test/CodeGen/PowerPC/ppc64-zext.ll
+++ b/test/CodeGen/PowerPC/ppc64-zext.ll
@@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-linux"
 
 define i64 @fun(i32 %arg32) nounwind {
 entry:
-; CHECK: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32
+; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
   %o = zext i32 %arg32 to i64
   ret i64 %o
 }
diff --git a/test/CodeGen/PowerPC/ppc64le-aggregates.ll b/test/CodeGen/PowerPC/ppc64le-aggregates.ll
index 4edd8d59e526..a4bec759050b 100644
--- a/test/CodeGen/PowerPC/ppc64le-aggregates.ll
+++ b/test/CodeGen/PowerPC/ppc64le-aggregates.ll
@@ -1,8 +1,11 @@
 ; RUN: llc < %s -march=ppc64le -mcpu=pwr8 -mattr=+altivec -mattr=-vsx | FileCheck %s
+; RUN: llc < %s -march=ppc64le -mattr=+altivec -mattr=-vsx | FileCheck %s
 
 ; Currently VSX support is disabled for this test because we generate lxsdx
 ; instead of lfd, and stxsdx instead of stfd.  That is a poor choice when we
 ; have reg+imm addressing, and is on the list of things to be fixed.
+; The second run step is to ensure that -march=ppc64le is adequate to select
+; the same feature set as with -mcpu=pwr8 since that is the baseline for ppc64le.
 
 target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-unknown-linux-gnu"
@@ -254,33 +257,33 @@ entry:
 
 define void @caller2() {
 entry:
-  %0 = load [8 x float]* getelementptr inbounds (%struct.float8* @g8, i64 0, i32 0), align 4
-  %1 = load [5 x float]* getelementptr inbounds (%struct.float5* @g5, i64 0, i32 0), align 4
-  %2 = load [2 x float]* getelementptr inbounds (%struct.float2* @g2, i64 0, i32 0), align 4
+  %0 = load [8 x float], [8 x float]* getelementptr inbounds (%struct.float8, %struct.float8* @g8, i64 0, i32 0), align 4
+  %1 = load [5 x float], [5 x float]* getelementptr inbounds (%struct.float5, %struct.float5* @g5, i64 0, i32 0), align 4
+  %2 = load [2 x float], [2 x float]* getelementptr inbounds (%struct.float2, %struct.float2* @g2, i64 0, i32 0), align 4
   tail call void @test2([8 x float] %0, [5 x float] %1, [2 x float] %2)
   ret void
 }
 ; CHECK-LABEL: @caller2
-; CHECK: ld [[REG:[0-9]+]], .LC
-; CHECK-DAG: lfs 1, 0([[REG]])
-; CHECK-DAG: lfs 2, 4([[REG]])
-; CHECK-DAG: lfs 3, 8([[REG]])
-; CHECK-DAG: lfs 4, 12([[REG]])
-; CHECK-DAG: lfs 5, 16([[REG]])
-; CHECK-DAG: lfs 6, 20([[REG]])
-; CHECK-DAG: lfs 7, 24([[REG]])
-; CHECK-DAG: lfs 8, 28([[REG]])
-; CHECK: ld [[REG:[0-9]+]], .LC
-; CHECK-DAG: lfs 9, 0([[REG]])
-; CHECK-DAG: lfs 10, 4([[REG]])
-; CHECK-DAG: lfs 11, 8([[REG]])
-; CHECK-DAG: lfs 12, 12([[REG]])
-; CHECK-DAG: lfs 13, 16([[REG]])
-; CHECK: ld [[REG:[0-9]+]], .LC
-; CHECK-DAG: lwz [[REG0:[0-9]+]], 0([[REG]])
-; CHECK-DAG: lwz [[REG1:[0-9]+]], 4([[REG]])
-; CHECK-DAG: sldi [[REG1]], [[REG1]], 32
-; CHECK-DAG: or 10, [[REG0]], [[REG1]]
+; CHECK: ld {{[0-9]+}}, .LC
+; CHECK-DAG: lfs 1, 0({{[0-9]+}})
+; CHECK-DAG: lfs 2, 4({{[0-9]+}})
+; CHECK-DAG: lfs 3, 8({{[0-9]+}})
+; CHECK-DAG: lfs 4, 12({{[0-9]+}})
+; CHECK-DAG: lfs 5, 16({{[0-9]+}})
+; CHECK-DAG: lfs 6, 20({{[0-9]+}})
+; CHECK-DAG: lfs 7, 24({{[0-9]+}})
+; CHECK-DAG: lfs 8, 28({{[0-9]+}})
+
+; CHECK-DAG: lfs 9, 0({{[0-9]+}})
+; CHECK-DAG: lfs 10, 4({{[0-9]+}})
+; CHECK-DAG: lfs 11, 8({{[0-9]+}})
+; CHECK-DAG: lfs 12, 12({{[0-9]+}})
+; CHECK-DAG: lfs 13, 16({{[0-9]+}})
+
+; CHECK-DAG: lwz [[REG0:[0-9]+]], 0({{[0-9]+}})
+; CHECK-DAG: lwz [[REG1:[0-9]+]], 4({{[0-9]+}})
+; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 32
+; CHECK-DAG: or 10, [[REG0]], [[REG2]]
 ; CHECK: bl test2
 
 declare void @test2([8 x float], [5 x float], [2 x float])
@@ -296,8 +299,8 @@ entry:
 
 define void @caller3(double %d) {
 entry:
-  %0 = load [8 x float]* getelementptr inbounds (%struct.float8* @g8, i64 0, i32 0), align 4
-  %1 = load [5 x float]* getelementptr inbounds (%struct.float5* @g5, i64 0, i32 0), align 4
+  %0 = load [8 x float], [8 x float]* getelementptr inbounds (%struct.float8, %struct.float8* @g8, i64 0, i32 0), align 4
+  %1 = load [5 x float], [5 x float]* getelementptr inbounds (%struct.float5, %struct.float5* @g5, i64 0, i32 0), align 4
   tail call void @test3([8 x float] %0, [5 x float] %1, double %d)
   ret void
 }
@@ -319,8 +322,8 @@ entry:
 
 define void @caller4(float %f) {
 entry:
-  %0 = load [8 x float]* getelementptr inbounds (%struct.float8* @g8, i64 0, i32 0), align 4
-  %1 = load [5 x float]* getelementptr inbounds (%struct.float5* @g5, i64 0, i32 0), align 4
+  %0 = load [8 x float], [8 x float]* getelementptr inbounds (%struct.float8, %struct.float8* @g8, i64 0, i32 0), align 4
+  %1 = load [5 x float], [5 x float]* getelementptr inbounds (%struct.float5, %struct.float5* @g5, i64 0, i32 0), align 4
   tail call void @test4([8 x float] %0, [5 x float] %1, float %f)
   ret void
 }
diff --git a/test/CodeGen/PowerPC/ppc64le-calls.ll b/test/CodeGen/PowerPC/ppc64le-calls.ll
index 0d667dde96b4..b65b9549b6b1 100644
--- a/test/CodeGen/PowerPC/ppc64le-calls.ll
+++ b/test/CodeGen/PowerPC/ppc64le-calls.ll
@@ -1,4 +1,8 @@
 ; RUN: llc -march=ppc64le -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -march=ppc64le < %s | FileCheck %s
+
+; The second run of the test case is to ensure the behaviour is the same
+; without specifying -mcpu=pwr8 as that is now the baseline for ppc64le.
 
 target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-unknown-linux-gnu"
diff --git a/test/CodeGen/PowerPC/ppc64le-localentry.ll b/test/CodeGen/PowerPC/ppc64le-localentry.ll
index 4676ce8eadc6..be64f1151769 100644
--- a/test/CodeGen/PowerPC/ppc64le-localentry.ll
+++ b/test/CodeGen/PowerPC/ppc64le-localentry.ll
@@ -1,5 +1,10 @@
 ; RUN: llc -march=ppc64le -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -march=ppc64le -mcpu=pwr8 -O0 < %s | FileCheck %s
+; RUN: llc -march=ppc64le < %s | FileCheck %s
+; RUN: llc -march=ppc64le -O0 < %s | FileCheck %s
+
+; The second run of the test case is to ensure the behaviour is the same
+; without specifying -mcpu=pwr8 as that is now the baseline for ppc64le.
 
 target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-unknown-linux-gnu"
@@ -11,13 +16,14 @@ target triple = "powerpc64le-unknown-linux-gnu"
 define i64 @use_toc(i64 %a) nounwind {
 entry:
 ; CHECK-LABEL: @use_toc
+; CHECK-NEXT: .L{{.*}}:
 ; CHECK-NEXT: .Ltmp[[TMP1:[0-9]+]]:
 ; CHECK-NEXT: addis 2, 12, .TOC.-.Ltmp[[TMP1]]@ha
 ; CHECK-NEXT: addi 2, 2, .TOC.-.Ltmp[[TMP1]]@l
 ; CHECK-NEXT: .Ltmp[[TMP2:[0-9]+]]:
 ; CHECK-NEXT: .localentry use_toc, .Ltmp[[TMP2]]-.Ltmp[[TMP1]]
 ; CHECK-NEXT: %entry
-  %0 = load i64* @number64, align 8
+  %0 = load i64, i64* @number64, align 8
   %cmp = icmp eq i64 %0, %a
   %conv1 = zext i1 %cmp to i64
   ret i64 %conv1
@@ -27,6 +33,7 @@ declare void @callee()
 define void @use_toc_implicit() nounwind {
 entry:
 ; CHECK-LABEL: @use_toc_implicit
+; CHECK-NEXT: .L{{.*}}:
 ; CHECK-NEXT: .Ltmp[[TMP1:[0-9]+]]:
 ; CHECK-NEXT: addis 2, 12, .TOC.-.Ltmp[[TMP1]]@ha
 ; CHECK-NEXT: addi 2, 2, .TOC.-.Ltmp[[TMP1]]@l
@@ -40,6 +47,7 @@ entry:
 define i64 @no_toc(i64 %a) nounwind {
 entry:
 ; CHECK-LABEL: @no_toc
+; CHECK-NEXT: .L{{.*}}:
 ; CHECK-NEXT: %entry
   ret i64 %a
 }
diff --git a/test/CodeGen/PowerPC/ppc64le-smallarg.ll b/test/CodeGen/PowerPC/ppc64le-smallarg.ll
index 120c14039f99..070a617ffe4f 100644
--- a/test/CodeGen/PowerPC/ppc64le-smallarg.ll
+++ b/test/CodeGen/PowerPC/ppc64le-smallarg.ll
@@ -17,7 +17,7 @@ define void @callee1(%struct.small_arg* noalias nocapture sret %agg.result, %str
 entry:
   %0 = bitcast %struct.small_arg* %x to i32*
   %1 = bitcast %struct.small_arg* %agg.result to i32*
-  %2 = load i32* %0, align 2
+  %2 = load i32, i32* %0, align 2
   store i32 %2, i32* %1, align 2
   ret void
 }
@@ -42,17 +42,19 @@ entry:
   ret float %x
 }
 ; CHECK: @callee2
-; CHECK: lfs {{[0-9]+}}, 136(1)
+; CHECK: addi [[TOCREG:[0-9]+]], 1, 136
+; CHECK: lxsspx {{[0-9]+}}, {{[0-9]+}}, [[TOCREG]]
 ; CHECK: blr
 
 define void @caller2() {
 entry:
-  %0 = load float* @gf, align 4
+  %0 = load float, float* @gf, align 4
   %call = tail call float @test2(float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float %0)
   ret void
 }
 ; CHECK: @caller2
-; CHECK: stfs {{[0-9]+}}, 136(1)
+; CHECK: li [[TOCOFF:[0-9]+]], 136
+; CHECK: stxsspx {{[0-9]+}}, 1, [[TOCOFF]]
 ; CHECK: bl test2
 
 declare float @test2(float, float, float, float, float, float, float, float, float, float, float, float, float, float)
diff --git a/test/CodeGen/PowerPC/ppcf128-1.ll b/test/CodeGen/PowerPC/ppcf128-1.ll
index 2cec934c66fd..f0e58f61a867 100644
--- a/test/CodeGen/PowerPC/ppcf128-1.ll
+++ b/test/CodeGen/PowerPC/ppcf128-1.ll
@@ -12,16 +12,16 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store ppc_fp128 %x, ppc_fp128* %x_addr
 	store ppc_fp128 %y, ppc_fp128* %y_addr
-	%tmp1 = load ppc_fp128* %x_addr, align 16		; <ppc_fp128> [#uses=1]
-	%tmp2 = load ppc_fp128* %y_addr, align 16		; <ppc_fp128> [#uses=1]
+	%tmp1 = load ppc_fp128, ppc_fp128* %x_addr, align 16		; <ppc_fp128> [#uses=1]
+	%tmp2 = load ppc_fp128, ppc_fp128* %y_addr, align 16		; <ppc_fp128> [#uses=1]
 	%tmp3 = fadd ppc_fp128 %tmp1, %tmp2		; <ppc_fp128> [#uses=1]
 	store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16
-	%tmp4 = load ppc_fp128* %tmp, align 16		; <ppc_fp128> [#uses=1]
+	%tmp4 = load ppc_fp128, ppc_fp128* %tmp, align 16		; <ppc_fp128> [#uses=1]
 	store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16
 	br label %return
 
 return:		; preds = %entry
-	%retval5 = load ppc_fp128* %retval		; <ppc_fp128> [#uses=1]
+	%retval5 = load ppc_fp128, ppc_fp128* %retval		; <ppc_fp128> [#uses=1]
 	ret ppc_fp128 %retval5
 }
 
@@ -34,16 +34,16 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store ppc_fp128 %x, ppc_fp128* %x_addr
 	store ppc_fp128 %y, ppc_fp128* %y_addr
-	%tmp1 = load ppc_fp128* %x_addr, align 16		; <ppc_fp128> [#uses=1]
-	%tmp2 = load ppc_fp128* %y_addr, align 16		; <ppc_fp128> [#uses=1]
+	%tmp1 = load ppc_fp128, ppc_fp128* %x_addr, align 16		; <ppc_fp128> [#uses=1]
+	%tmp2 = load ppc_fp128, ppc_fp128* %y_addr, align 16		; <ppc_fp128> [#uses=1]
 	%tmp3 = fsub ppc_fp128 %tmp1, %tmp2		; <ppc_fp128> [#uses=1]
 	store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16
-	%tmp4 = load ppc_fp128* %tmp, align 16		; <ppc_fp128> [#uses=1]
+	%tmp4 = load ppc_fp128, ppc_fp128* %tmp, align 16		; <ppc_fp128> [#uses=1]
 	store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16
 	br label %return
 
 return:		; preds = %entry
-	%retval5 = load ppc_fp128* %retval		; <ppc_fp128> [#uses=1]
+	%retval5 = load ppc_fp128, ppc_fp128* %retval		; <ppc_fp128> [#uses=1]
 	ret ppc_fp128 %retval5
 }
 
@@ -56,16 +56,16 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store ppc_fp128 %x, ppc_fp128* %x_addr
 	store ppc_fp128 %y, ppc_fp128* %y_addr
-	%tmp1 = load ppc_fp128* %x_addr, align 16		; <ppc_fp128> [#uses=1]
-	%tmp2 = load ppc_fp128* %y_addr, align 16		; <ppc_fp128> [#uses=1]
+	%tmp1 = load ppc_fp128, ppc_fp128* %x_addr, align 16		; <ppc_fp128> [#uses=1]
+	%tmp2 = load ppc_fp128, ppc_fp128* %y_addr, align 16		; <ppc_fp128> [#uses=1]
 	%tmp3 = fmul ppc_fp128 %tmp1, %tmp2		; <ppc_fp128> [#uses=1]
 	store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16
-	%tmp4 = load ppc_fp128* %tmp, align 16		; <ppc_fp128> [#uses=1]
+	%tmp4 = load ppc_fp128, ppc_fp128* %tmp, align 16		; <ppc_fp128> [#uses=1]
 	store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16
 	br label %return
 
 return:		; preds = %entry
-	%retval5 = load ppc_fp128* %retval		; <ppc_fp128> [#uses=1]
+	%retval5 = load ppc_fp128, ppc_fp128* %retval		; <ppc_fp128> [#uses=1]
 	ret ppc_fp128 %retval5
 }
 
@@ -78,15 +78,15 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store ppc_fp128 %x, ppc_fp128* %x_addr
 	store ppc_fp128 %y, ppc_fp128* %y_addr
-	%tmp1 = load ppc_fp128* %x_addr, align 16		; <ppc_fp128> [#uses=1]
-	%tmp2 = load ppc_fp128* %y_addr, align 16		; <ppc_fp128> [#uses=1]
+	%tmp1 = load ppc_fp128, ppc_fp128* %x_addr, align 16		; <ppc_fp128> [#uses=1]
+	%tmp2 = load ppc_fp128, ppc_fp128* %y_addr, align 16		; <ppc_fp128> [#uses=1]
 	%tmp3 = fdiv ppc_fp128 %tmp1, %tmp2		; <ppc_fp128> [#uses=1]
 	store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16
-	%tmp4 = load ppc_fp128* %tmp, align 16		; <ppc_fp128> [#uses=1]
+	%tmp4 = load ppc_fp128, ppc_fp128* %tmp, align 16		; <ppc_fp128> [#uses=1]
 	store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16
 	br label %return
 
 return:		; preds = %entry
-	%retval5 = load ppc_fp128* %retval		; <ppc_fp128> [#uses=1]
+	%retval5 = load ppc_fp128, ppc_fp128* %retval		; <ppc_fp128> [#uses=1]
 	ret ppc_fp128 %retval5
 }
diff --git a/test/CodeGen/PowerPC/ppcf128-3.ll b/test/CodeGen/PowerPC/ppcf128-3.ll
index 5043b622584b..fe3b4188d11c 100644
--- a/test/CodeGen/PowerPC/ppcf128-3.ll
+++ b/test/CodeGen/PowerPC/ppcf128-3.ll
@@ -4,28 +4,28 @@
 define i32 @stp_sequence_set_short_data(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
 entry:
 	%tmp1112 = sitofp i16 0 to ppc_fp128		; <ppc_fp128> [#uses=1]
-	%tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind 		; <i32> [#uses=0]
+	%tmp13 = call i32 (...) @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind 		; <i32> [#uses=0]
 	ret i32 0
 }
 
 define i32 @stp_sequence_set_short_data2(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
 entry:
 	%tmp1112 = sitofp i8 0 to ppc_fp128		; <ppc_fp128> [#uses=1]
-	%tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind 		; <i32> [#uses=0]
+	%tmp13 = call i32 (...) @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind 		; <i32> [#uses=0]
 	ret i32 0
 }
 
 define i32 @stp_sequence_set_short_data3(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
 entry:
 	%tmp1112 = uitofp i16 0 to ppc_fp128		; <ppc_fp128> [#uses=1]
-	%tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind 		; <i32> [#uses=0]
+	%tmp13 = call i32 (...) @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind 		; <i32> [#uses=0]
 	ret i32 0
 }
 
 define i32 @stp_sequence_set_short_data4(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
 entry:
 	%tmp1112 = uitofp i8 0 to ppc_fp128		; <ppc_fp128> [#uses=1]
-	%tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind 		; <i32> [#uses=0]
+	%tmp13 = call i32 (...) @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind 		; <i32> [#uses=0]
 	ret i32 0
 }
 
diff --git a/test/CodeGen/PowerPC/ppcf128-endian.ll b/test/CodeGen/PowerPC/ppcf128-endian.ll
index 180fedf5c9f4..ee314c1db58b 100644
--- a/test/CodeGen/PowerPC/ppcf128-endian.ll
+++ b/test/CodeGen/PowerPC/ppcf128-endian.ll
@@ -9,7 +9,7 @@ define void @callee(ppc_fp128 %x) {
 entry:
   %x.addr = alloca ppc_fp128, align 16
   store ppc_fp128 %x, ppc_fp128* %x.addr, align 16
-  %0 = load ppc_fp128* %x.addr, align 16
+  %0 = load ppc_fp128, ppc_fp128* %x.addr, align 16
   store ppc_fp128 %0, ppc_fp128* @g, align 16
   ret void
 }
@@ -21,7 +21,7 @@ entry:
 
 define void @caller() {
 entry:
-  %0 = load ppc_fp128* @g, align 16
+  %0 = load ppc_fp128, ppc_fp128* @g, align 16
   call void @test(ppc_fp128 %0)
   ret void
 }
@@ -51,7 +51,7 @@ entry:
 
 define ppc_fp128 @result() {
 entry:
-  %0 = load ppc_fp128* @g, align 16
+  %0 = load ppc_fp128, ppc_fp128* @g, align 16
   ret ppc_fp128 %0
 }
 ; CHECK: @result
diff --git a/test/CodeGen/PowerPC/pr13891.ll b/test/CodeGen/PowerPC/pr13891.ll
index 4be65dd43d6a..5b695eb9f0df 100644
--- a/test/CodeGen/PowerPC/pr13891.ll
+++ b/test/CodeGen/PowerPC/pr13891.ll
@@ -10,7 +10,7 @@ define void @_Z5check3foos(%struct.foo* nocapture byval %f, i16 signext %i) noin
 ; CHECK: lha {{[0-9]+}}, {{[0-9]+}}(1)
 entry:
   %0 = bitcast %struct.foo* %f to i16*
-  %1 = load i16* %0, align 2
+  %1 = load i16, i16* %0, align 2
   %bf.val.sext = ashr i16 %1, 8
   %cmp = icmp eq i16 %bf.val.sext, %i
   br i1 %cmp, label %if.end, label %if.then
diff --git a/test/CodeGen/PowerPC/pr15031.ll b/test/CodeGen/PowerPC/pr15031.ll
index e58ad80e139b..d1b9932ca22b 100644
--- a/test/CodeGen/PowerPC/pr15031.ll
+++ b/test/CodeGen/PowerPC/pr15031.ll
@@ -298,50 +298,50 @@ declare zeroext i32 @_ZNK4llvm14MCRegisterInfo9getSubRegEjj(%"class.llvm::MCRegi
 
 define void @_ZN4llvm14MachineOperand12substPhysRegEjRKNS_18TargetRegisterInfoE(%"class.llvm::MachineOperand"* %this, i32 zeroext %Reg, %"class.llvm::TargetRegisterInfo"* %TRI) align 2 {
 entry:
-  %SubReg_TargetFlags.i = getelementptr inbounds %"class.llvm::MachineOperand"* %this, i64 0, i32 1
+  %SubReg_TargetFlags.i = getelementptr inbounds %"class.llvm::MachineOperand", %"class.llvm::MachineOperand"* %this, i64 0, i32 1
   %0 = bitcast [3 x i8]* %SubReg_TargetFlags.i to i24*
-  %bf.load.i = load i24* %0, align 1
+  %bf.load.i = load i24, i24* %0, align 1
   %bf.lshr.i = lshr i24 %bf.load.i, 12
   %tobool = icmp eq i24 %bf.lshr.i, 0
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry
   %bf.cast.i = zext i24 %bf.lshr.i to i32
-  %add.ptr = getelementptr inbounds %"class.llvm::TargetRegisterInfo"* %TRI, i64 0, i32 1
+  %add.ptr = getelementptr inbounds %"class.llvm::TargetRegisterInfo", %"class.llvm::TargetRegisterInfo"* %TRI, i64 0, i32 1
   %call3 = tail call zeroext i32 @_ZNK4llvm14MCRegisterInfo9getSubRegEjj(%"class.llvm::MCRegisterInfo"* %add.ptr, i32 zeroext %Reg, i32 zeroext %bf.cast.i)
-  %bf.load.i10 = load i24* %0, align 1
+  %bf.load.i10 = load i24, i24* %0, align 1
   %bf.clear.i = and i24 %bf.load.i10, 4095
   store i24 %bf.clear.i, i24* %0, align 1
   br label %if.end
 
 if.end:                                           ; preds = %entry, %if.then
   %Reg.addr.0 = phi i32 [ %call3, %if.then ], [ %Reg, %entry ]
-  %RegNo.i.i = getelementptr inbounds %"class.llvm::MachineOperand"* %this, i64 0, i32 2, i32 0
-  %1 = load i32* %RegNo.i.i, align 4
+  %RegNo.i.i = getelementptr inbounds %"class.llvm::MachineOperand", %"class.llvm::MachineOperand"* %this, i64 0, i32 2, i32 0
+  %1 = load i32, i32* %RegNo.i.i, align 4
   %cmp.i = icmp eq i32 %1, %Reg.addr.0
   br i1 %cmp.i, label %_ZN4llvm14MachineOperand6setRegEj.exit, label %if.end.i
 
 if.end.i:                                         ; preds = %if.end
-  %ParentMI.i.i = getelementptr inbounds %"class.llvm::MachineOperand"* %this, i64 0, i32 3
-  %2 = load %"class.llvm::MachineInstr"** %ParentMI.i.i, align 8
+  %ParentMI.i.i = getelementptr inbounds %"class.llvm::MachineOperand", %"class.llvm::MachineOperand"* %this, i64 0, i32 3
+  %2 = load %"class.llvm::MachineInstr"*, %"class.llvm::MachineInstr"** %ParentMI.i.i, align 8
   %tobool.i = icmp eq %"class.llvm::MachineInstr"* %2, null
   br i1 %tobool.i, label %if.end13.i, label %if.then3.i
 
 if.then3.i:                                       ; preds = %if.end.i
-  %Parent.i.i = getelementptr inbounds %"class.llvm::MachineInstr"* %2, i64 0, i32 2
-  %3 = load %"class.llvm::MachineBasicBlock"** %Parent.i.i, align 8
+  %Parent.i.i = getelementptr inbounds %"class.llvm::MachineInstr", %"class.llvm::MachineInstr"* %2, i64 0, i32 2
+  %3 = load %"class.llvm::MachineBasicBlock"*, %"class.llvm::MachineBasicBlock"** %Parent.i.i, align 8
   %tobool5.i = icmp eq %"class.llvm::MachineBasicBlock"* %3, null
   br i1 %tobool5.i, label %if.end13.i, label %if.then6.i
 
 if.then6.i:                                       ; preds = %if.then3.i
-  %xParent.i.i = getelementptr inbounds %"class.llvm::MachineBasicBlock"* %3, i64 0, i32 4
-  %4 = load %"class.llvm::MachineFunction"** %xParent.i.i, align 8
+  %xParent.i.i = getelementptr inbounds %"class.llvm::MachineBasicBlock", %"class.llvm::MachineBasicBlock"* %3, i64 0, i32 4
+  %4 = load %"class.llvm::MachineFunction"*, %"class.llvm::MachineFunction"** %xParent.i.i, align 8
   %tobool8.i = icmp eq %"class.llvm::MachineFunction"* %4, null
   br i1 %tobool8.i, label %if.end13.i, label %if.then9.i
 
 if.then9.i:                                       ; preds = %if.then6.i
-  %RegInfo.i.i = getelementptr inbounds %"class.llvm::MachineFunction"* %4, i64 0, i32 5
-  %5 = load %"class.llvm::MachineRegisterInfo"** %RegInfo.i.i, align 8
+  %RegInfo.i.i = getelementptr inbounds %"class.llvm::MachineFunction", %"class.llvm::MachineFunction"* %4, i64 0, i32 5
+  %5 = load %"class.llvm::MachineRegisterInfo"*, %"class.llvm::MachineRegisterInfo"** %RegInfo.i.i, align 8
   tail call void @_ZN4llvm19MachineRegisterInfo27removeRegOperandFromUseListEPNS_14MachineOperandE(%"class.llvm::MachineRegisterInfo"* %5, %"class.llvm::MachineOperand"* %this)
   store i32 %Reg.addr.0, i32* %RegNo.i.i, align 4
   tail call void @_ZN4llvm19MachineRegisterInfo22addRegOperandToUseListEPNS_14MachineOperandE(%"class.llvm::MachineRegisterInfo"* %5, %"class.llvm::MachineOperand"* %this)
diff --git a/test/CodeGen/PowerPC/pr15630.ll b/test/CodeGen/PowerPC/pr15630.ll
index 3c1b604f0090..54a1b36868e9 100644
--- a/test/CodeGen/PowerPC/pr15630.ll
+++ b/test/CodeGen/PowerPC/pr15630.ll
@@ -8,7 +8,7 @@ entry:
   %newval = alloca i8
   %ordering = alloca i32, align 4
   store i8 %newval_arg, i8* %newval
-  %tmp = load i8* %newval
+  %tmp = load i8, i8* %newval
   store atomic volatile i8 %tmp, i8* %val_arg seq_cst, align 1
   ret void
 }
diff --git a/test/CodeGen/PowerPC/pr16556-2.ll b/test/CodeGen/PowerPC/pr16556-2.ll
index e2dae4573c72..9155ed5926f5 100644
--- a/test/CodeGen/PowerPC/pr16556-2.ll
+++ b/test/CodeGen/PowerPC/pr16556-2.ll
@@ -11,7 +11,7 @@ target triple = "powerpc-unknown-linux-gnu"
 @_D4core4time12TickDuration11ticksPerSecyl = global i64 0
 @.str5 = internal unnamed_addr constant [40 x i8] c"..\5Cldc\5Cruntime\5Cdruntime\5Csrc\5Ccore\5Ctime.d\00"
 @.str83 = internal constant [10 x i8] c"null this\00"
-@.modulefilename = internal constant { i32, i8* } { i32 39, i8* getelementptr inbounds ([40 x i8]* @.str5, i32 0, i32 0) }
+@.modulefilename = internal constant { i32, i8* } { i32 39, i8* getelementptr inbounds ([40 x i8], [40 x i8]* @.str5, i32 0, i32 0) }
 
 declare i8* @_d_assert_msg({ i32, i8* }, { i32, i8* }, i32)
 
@@ -23,15 +23,15 @@ entry:
   br i1 %tmp, label %noassert, label %assert
 
 assert:                                           ; preds = %entry
-  %tmp1 = load { i32, i8* }* @.modulefilename
-  %0 = call i8* @_d_assert_msg({ i32, i8* } { i32 9, i8* getelementptr inbounds ([10 x i8]* @.str83, i32 0, i32 0) }, { i32, i8* } %tmp1, i32 1586)
+  %tmp1 = load { i32, i8* }, { i32, i8* }* @.modulefilename
+  %0 = call i8* @_d_assert_msg({ i32, i8* } { i32 9, i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str83, i32 0, i32 0) }, { i32, i8* } %tmp1, i32 1586)
   unreachable
 
 noassert:                                         ; preds = %entry
-  %tmp2 = getelementptr %core.time.TickDuration* %.this_arg, i32 0, i32 0
-  %tmp3 = load i64* %tmp2
+  %tmp2 = getelementptr %core.time.TickDuration, %core.time.TickDuration* %.this_arg, i32 0, i32 0
+  %tmp3 = load i64, i64* %tmp2
   %tmp4 = sitofp i64 %tmp3 to ppc_fp128
-  %tmp5 = load i64* @_D4core4time12TickDuration11ticksPerSecyl
+  %tmp5 = load i64, i64* @_D4core4time12TickDuration11ticksPerSecyl
   %tmp6 = sitofp i64 %tmp5 to ppc_fp128
   %tmp7 = fdiv ppc_fp128 %tmp6, 0xM80000000000000000000000000000000
   %tmp8 = fdiv ppc_fp128 %tmp4, %tmp7
diff --git a/test/CodeGen/PowerPC/pr17168.ll b/test/CodeGen/PowerPC/pr17168.ll
index 62a9ede0200b..096895491381 100644
--- a/test/CodeGen/PowerPC/pr17168.ll
+++ b/test/CodeGen/PowerPC/pr17168.ll
@@ -24,8 +24,8 @@ for.cond968.preheader:                            ; preds = %for.cond968.prehead
 
 for.end1042:                                      ; preds = %for.cond968.preheader, %for.cond964.preheader, %entry
   %0 = phi i32 [ undef, %for.cond964.preheader ], [ undef, %for.cond968.preheader ], [ undef, %entry ]
-  %1 = load i32* getelementptr inbounds ([3 x i32]* @grid_points, i64 0, i64 0), align 4, !dbg !443, !tbaa !444
-  tail call void @llvm.dbg.value(metadata i32 1, i64 0, metadata !119, metadata !{!"0x102"}), !dbg !448
+  %1 = load i32, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @grid_points, i64 0, i64 0), align 4, !dbg !443, !tbaa !444
+  tail call void @llvm.dbg.value(metadata i32 1, i64 0, metadata !119, metadata !DIExpression()), !dbg !448
   %sub10454270 = add nsw i32 %0, -1, !dbg !448
   %cmp10464271 = icmp sgt i32 %sub10454270, 1, !dbg !448
   %sub11134263 = add nsw i32 %1, -1, !dbg !450
@@ -54,468 +54,468 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!438, !464}
 
-!0 = !{!"0x11\0012\00clang version 3.4 (trunk 190311)\001\00\000\00\000", !1, !2, !2, !3, !298, !2} ; [ DW_TAG_compile_unit ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] [DW_LANG_C99]
-!1 = !{!"bt.c", !"/home/hfinkel/src/NPB2.3-omp-C/BT"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 190311)", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !298, imports: !2)
+!1 = !DIFile(filename: "bt.c", directory: "/home/hfinkel/src/NPB2.3-omp-C/BT")
 !2 = !{}
 !3 = !{!4, !82, !102, !114, !132, !145, !154, !155, !162, !183, !200, !201, !207, !208, !215, !221, !230, !238, !246, !255, !260, !261, !268, !274, !279, !280, !287, !293}
-!4 = !{!"0x2e\00main\00main\00\0074\000\001\000\006\00256\001\0074", !1, !5, !6, null, null, null, null, !12} ; [ DW_TAG_subprogram ] [line 74] [def] [main]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "main", line: 74, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 74, file: !1, scope: !5, type: !6, variables: !12)
+!5 = !DIFile(filename: "bt.c", directory: "/home/hfinkel/src/NPB2.3-omp-C/BT")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8, !9}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0xf\00\000\0064\0064\000\000", null, null, !10} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!10 = !{!"0xf\00\000\0064\0064\000\000", null, null, !11} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char]
-!11 = !{!"0x24\00char\000\008\008\000\000\008", null, null} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_unsigned_char]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !10)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !11)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_unsigned_char)
 !12 = !{!13, !14, !15, !16, !17, !18, !19, !21, !22, !23, !25, !26}
-!13 = !{!"0x101\00argc\0016777290\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [argc] [line 74]
-!14 = !{!"0x101\00argv\0033554506\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [argv] [line 74]
-!15 = !{!"0x100\00niter\0076\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [niter] [line 76]
-!16 = !{!"0x100\00step\0076\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [step] [line 76]
-!17 = !{!"0x100\00n3\0076\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [n3] [line 76]
-!18 = !{!"0x100\00nthreads\0077\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [nthreads] [line 77]
-!19 = !{!"0x100\00navg\0078\000", !4, !5, !20} ; [ DW_TAG_auto_variable ] [navg] [line 78]
-!20 = !{!"0x24\00double\000\0064\0064\000\000\004", null, null} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float]
-!21 = !{!"0x100\00mflops\0078\000", !4, !5, !20} ; [ DW_TAG_auto_variable ] [mflops] [line 78]
-!22 = !{!"0x100\00tmax\0080\000", !4, !5, !20} ; [ DW_TAG_auto_variable ] [tmax] [line 80]
-!23 = !{!"0x100\00verified\0081\000", !4, !5, !24} ; [ DW_TAG_auto_variable ] [verified] [line 81]
-!24 = !{!"0x16\00boolean\0012\000\000\000\000", !1, null, !8} ; [ DW_TAG_typedef ] [boolean] [line 12, size 0, align 0, offset 0] [from int]
-!25 = !{!"0x100\00class\0082\000", !4, !5, !11} ; [ DW_TAG_auto_variable ] [class] [line 82]
-!26 = !{!"0x100\00fp\0083\000", !4, !5, !27} ; [ DW_TAG_auto_variable ] [fp] [line 83]
-!27 = !{!"0xf\00\000\0064\0064\000\000", null, null, !28} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from FILE]
-!28 = !{!"0x16\00FILE\0049\000\000\000\000", !1, null, !29} ; [ DW_TAG_typedef ] [FILE] [line 49, size 0, align 0, offset 0] [from _IO_FILE]
-!29 = !{!"0x13\00_IO_FILE\00271\001728\0064\000\000\000", !30, null, null, !31, null, null, null} ; [ DW_TAG_structure_type ] [_IO_FILE] [line 271, size 1728, align 64, offset 0] [def] [from ]
-!30 = !{!"/usr/include/libio.h", !"/home/hfinkel/src/NPB2.3-omp-C/BT"}
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 74, arg: 1, scope: !4, file: !5, type: !8)
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 74, arg: 2, scope: !4, file: !5, type: !9)
+!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "niter", line: 76, scope: !4, file: !5, type: !8)
+!16 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "step", line: 76, scope: !4, file: !5, type: !8)
+!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "n3", line: 76, scope: !4, file: !5, type: !8)
+!18 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "nthreads", line: 77, scope: !4, file: !5, type: !8)
+!19 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "navg", line: 78, scope: !4, file: !5, type: !20)
+!20 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 64, encoding: DW_ATE_float)
+!21 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "mflops", line: 78, scope: !4, file: !5, type: !20)
+!22 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "tmax", line: 80, scope: !4, file: !5, type: !20)
+!23 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "verified", line: 81, scope: !4, file: !5, type: !24)
+!24 = !DIDerivedType(tag: DW_TAG_typedef, name: "boolean", line: 12, file: !1, baseType: !8)
+!25 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "class", line: 82, scope: !4, file: !5, type: !11)
+!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "fp", line: 83, scope: !4, file: !5, type: !27)
+!27 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !28)
+!28 = !DIDerivedType(tag: DW_TAG_typedef, name: "FILE", line: 49, file: !1, baseType: !29)
+!29 = !DICompositeType(tag: DW_TAG_structure_type, name: "_IO_FILE", line: 271, size: 1728, align: 64, file: !30, elements: !31)
+!30 = !DIFile(filename: "/usr/include/libio.h", directory: "/home/hfinkel/src/NPB2.3-omp-C/BT")
 !31 = !{!32, !33, !34, !35, !36, !37, !38, !39, !40, !41, !42, !43, !44, !52, !53, !54, !55, !58, !60, !62, !66, !68, !70, !71, !72, !73, !74, !77, !78}
-!32 = !{!"0xd\00_flags\00272\0032\0032\000\000", !30, !29, !8} ; [ DW_TAG_member ] [_flags] [line 272, size 32, align 32, offset 0] [from int]
-!33 = !{!"0xd\00_IO_read_ptr\00277\0064\0064\0064\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_read_ptr] [line 277, size 64, align 64, offset 64] [from ]
-!34 = !{!"0xd\00_IO_read_end\00278\0064\0064\00128\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_read_end] [line 278, size 64, align 64, offset 128] [from ]
-!35 = !{!"0xd\00_IO_read_base\00279\0064\0064\00192\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_read_base] [line 279, size 64, align 64, offset 192] [from ]
-!36 = !{!"0xd\00_IO_write_base\00280\0064\0064\00256\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_write_base] [line 280, size 64, align 64, offset 256] [from ]
-!37 = !{!"0xd\00_IO_write_ptr\00281\0064\0064\00320\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_write_ptr] [line 281, size 64, align 64, offset 320] [from ]
-!38 = !{!"0xd\00_IO_write_end\00282\0064\0064\00384\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_write_end] [line 282, size 64, align 64, offset 384] [from ]
-!39 = !{!"0xd\00_IO_buf_base\00283\0064\0064\00448\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_buf_base] [line 283, size 64, align 64, offset 448] [from ]
-!40 = !{!"0xd\00_IO_buf_end\00284\0064\0064\00512\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_buf_end] [line 284, size 64, align 64, offset 512] [from ]
-!41 = !{!"0xd\00_IO_save_base\00286\0064\0064\00576\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_save_base] [line 286, size 64, align 64, offset 576] [from ]
-!42 = !{!"0xd\00_IO_backup_base\00287\0064\0064\00640\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_backup_base] [line 287, size 64, align 64, offset 640] [from ]
-!43 = !{!"0xd\00_IO_save_end\00288\0064\0064\00704\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_save_end] [line 288, size 64, align 64, offset 704] [from ]
-!44 = !{!"0xd\00_markers\00290\0064\0064\00768\000", !30, !29, !45} ; [ DW_TAG_member ] [_markers] [line 290, size 64, align 64, offset 768] [from ]
-!45 = !{!"0xf\00\000\0064\0064\000\000", null, null, !46} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _IO_marker]
-!46 = !{!"0x13\00_IO_marker\00186\00192\0064\000\000\000", !30, null, null, !47, null, null, null} ; [ DW_TAG_structure_type ] [_IO_marker] [line 186, size 192, align 64, offset 0] [def] [from ]
+!32 = !DIDerivedType(tag: DW_TAG_member, name: "_flags", line: 272, size: 32, align: 32, file: !30, scope: !29, baseType: !8)
+!33 = !DIDerivedType(tag: DW_TAG_member, name: "_IO_read_ptr", line: 277, size: 64, align: 64, offset: 64, file: !30, scope: !29, baseType: !10)
+!34 = !DIDerivedType(tag: DW_TAG_member, name: "_IO_read_end", line: 278, size: 64, align: 64, offset: 128, file: !30, scope: !29, baseType: !10)
+!35 = !DIDerivedType(tag: DW_TAG_member, name: "_IO_read_base", line: 279, size: 64, align: 64, offset: 192, file: !30, scope: !29, baseType: !10)
+!36 = !DIDerivedType(tag: DW_TAG_member, name: "_IO_write_base", line: 280, size: 64, align: 64, offset: 256, file: !30, scope: !29, baseType: !10)
+!37 = !DIDerivedType(tag: DW_TAG_member, name: "_IO_write_ptr", line: 281, size: 64, align: 64, offset: 320, file: !30, scope: !29, baseType: !10)
+!38 = !DIDerivedType(tag: DW_TAG_member, name: "_IO_write_end", line: 282, size: 64, align: 64, offset: 384, file: !30, scope: !29, baseType: !10)
+!39 = !DIDerivedType(tag: DW_TAG_member, name: "_IO_buf_base", line: 283, size: 64, align: 64, offset: 448, file: !30, scope: !29, baseType: !10)
+!40 = !DIDerivedType(tag: DW_TAG_member, name: "_IO_buf_end", line: 284, size: 64, align: 64, offset: 512, file: !30, scope: !29, baseType: !10)
+!41 = !DIDerivedType(tag: DW_TAG_member, name: "_IO_save_base", line: 286, size: 64, align: 64, offset: 576, file: !30, scope: !29, baseType: !10)
+!42 = !DIDerivedType(tag: DW_TAG_member, name: "_IO_backup_base", line: 287, size: 64, align: 64, offset: 640, file: !30, scope: !29, baseType: !10)
+!43 = !DIDerivedType(tag: DW_TAG_member, name: "_IO_save_end", line: 288, size: 64, align: 64, offset: 704, file: !30, scope: !29, baseType: !10)
+!44 = !DIDerivedType(tag: DW_TAG_member, name: "_markers", line: 290, size: 64, align: 64, offset: 768, file: !30, scope: !29, baseType: !45)
+!45 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !46)
+!46 = !DICompositeType(tag: DW_TAG_structure_type, name: "_IO_marker", line: 186, size: 192, align: 64, file: !30, elements: !47)
 !47 = !{!48, !49, !51}
-!48 = !{!"0xd\00_next\00187\0064\0064\000\000", !30, !46, !45} ; [ DW_TAG_member ] [_next] [line 187, size 64, align 64, offset 0] [from ]
-!49 = !{!"0xd\00_sbuf\00188\0064\0064\0064\000", !30, !46, !50} ; [ DW_TAG_member ] [_sbuf] [line 188, size 64, align 64, offset 64] [from ]
-!50 = !{!"0xf\00\000\0064\0064\000\000", null, null, !29} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _IO_FILE]
-!51 = !{!"0xd\00_pos\00192\0032\0032\00128\000", !30, !46, !8} ; [ DW_TAG_member ] [_pos] [line 192, size 32, align 32, offset 128] [from int]
-!52 = !{!"0xd\00_chain\00292\0064\0064\00832\000", !30, !29, !50} ; [ DW_TAG_member ] [_chain] [line 292, size 64, align 64, offset 832] [from ]
-!53 = !{!"0xd\00_fileno\00294\0032\0032\00896\000", !30, !29, !8} ; [ DW_TAG_member ] [_fileno] [line 294, size 32, align 32, offset 896] [from int]
-!54 = !{!"0xd\00_flags2\00298\0032\0032\00928\000", !30, !29, !8} ; [ DW_TAG_member ] [_flags2] [line 298, size 32, align 32, offset 928] [from int]
-!55 = !{!"0xd\00_old_offset\00300\0064\0064\00960\000", !30, !29, !56} ; [ DW_TAG_member ] [_old_offset] [line 300, size 64, align 64, offset 960] [from __off_t]
-!56 = !{!"0x16\00__off_t\00141\000\000\000\000", !30, null, !57} ; [ DW_TAG_typedef ] [__off_t] [line 141, size 0, align 0, offset 0] [from long int]
-!57 = !{!"0x24\00long int\000\0064\0064\000\000\005", null, null} ; [ DW_TAG_base_type ] [long int] [line 0, size 64, align 64, offset 0, enc DW_ATE_signed]
-!58 = !{!"0xd\00_cur_column\00304\0016\0016\001024\000", !30, !29, !59} ; [ DW_TAG_member ] [_cur_column] [line 304, size 16, align 16, offset 1024] [from unsigned short]
-!59 = !{!"0x24\00unsigned short\000\0016\0016\000\000\007", null, null} ; [ DW_TAG_base_type ] [unsigned short] [line 0, size 16, align 16, offset 0, enc DW_ATE_unsigned]
-!60 = !{!"0xd\00_vtable_offset\00305\008\008\001040\000", !30, !29, !61} ; [ DW_TAG_member ] [_vtable_offset] [line 305, size 8, align 8, offset 1040] [from signed char]
-!61 = !{!"0x24\00signed char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ] [signed char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
-!62 = !{!"0xd\00_shortbuf\00306\008\008\001048\000", !30, !29, !63} ; [ DW_TAG_member ] [_shortbuf] [line 306, size 8, align 8, offset 1048] [from ]
-!63 = !{!"0x1\00\000\008\008\000\000", null, null, !11, !64, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 8, align 8, offset 0] [from char]
+!48 = !DIDerivedType(tag: DW_TAG_member, name: "_next", line: 187, size: 64, align: 64, file: !30, scope: !46, baseType: !45)
+!49 = !DIDerivedType(tag: DW_TAG_member, name: "_sbuf", line: 188, size: 64, align: 64, offset: 64, file: !30, scope: !46, baseType: !50)
+!50 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !29)
+!51 = !DIDerivedType(tag: DW_TAG_member, name: "_pos", line: 192, size: 32, align: 32, offset: 128, file: !30, scope: !46, baseType: !8)
+!52 = !DIDerivedType(tag: DW_TAG_member, name: "_chain", line: 292, size: 64, align: 64, offset: 832, file: !30, scope: !29, baseType: !50)
+!53 = !DIDerivedType(tag: DW_TAG_member, name: "_fileno", line: 294, size: 32, align: 32, offset: 896, file: !30, scope: !29, baseType: !8)
+!54 = !DIDerivedType(tag: DW_TAG_member, name: "_flags2", line: 298, size: 32, align: 32, offset: 928, file: !30, scope: !29, baseType: !8)
+!55 = !DIDerivedType(tag: DW_TAG_member, name: "_old_offset", line: 300, size: 64, align: 64, offset: 960, file: !30, scope: !29, baseType: !56)
+!56 = !DIDerivedType(tag: DW_TAG_typedef, name: "__off_t", line: 141, file: !30, baseType: !57)
+!57 = !DIBasicType(tag: DW_TAG_base_type, name: "long int", size: 64, align: 64, encoding: DW_ATE_signed)
+!58 = !DIDerivedType(tag: DW_TAG_member, name: "_cur_column", line: 304, size: 16, align: 16, offset: 1024, file: !30, scope: !29, baseType: !59)
+!59 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned short", size: 16, align: 16, encoding: DW_ATE_unsigned)
+!60 = !DIDerivedType(tag: DW_TAG_member, name: "_vtable_offset", line: 305, size: 8, align: 8, offset: 1040, file: !30, scope: !29, baseType: !61)
+!61 = !DIBasicType(tag: DW_TAG_base_type, name: "signed char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!62 = !DIDerivedType(tag: DW_TAG_member, name: "_shortbuf", line: 306, size: 8, align: 8, offset: 1048, file: !30, scope: !29, baseType: !63)
+!63 = !DICompositeType(tag: DW_TAG_array_type, size: 8, align: 8, baseType: !11, elements: !64)
 !64 = !{!65}
-!65 = !{!"0x21\000\001"}        ; [ DW_TAG_subrange_type ] [0, 0]
-!66 = !{!"0xd\00_lock\00310\0064\0064\001088\000", !30, !29, !67} ; [ DW_TAG_member ] [_lock] [line 310, size 64, align 64, offset 1088] [from ]
-!67 = !{!"0xf\00\000\0064\0064\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!68 = !{!"0xd\00_offset\00319\0064\0064\001152\000", !30, !29, !69} ; [ DW_TAG_member ] [_offset] [line 319, size 64, align 64, offset 1152] [from __off64_t]
-!69 = !{!"0x16\00__off64_t\00142\000\000\000\000", !30, null, !57} ; [ DW_TAG_typedef ] [__off64_t] [line 142, size 0, align 0, offset 0] [from long int]
-!70 = !{!"0xd\00__pad1\00328\0064\0064\001216\000", !30, !29, !67} ; [ DW_TAG_member ] [__pad1] [line 328, size 64, align 64, offset 1216] [from ]
-!71 = !{!"0xd\00__pad2\00329\0064\0064\001280\000", !30, !29, !67} ; [ DW_TAG_member ] [__pad2] [line 329, size 64, align 64, offset 1280] [from ]
-!72 = !{!"0xd\00__pad3\00330\0064\0064\001344\000", !30, !29, !67} ; [ DW_TAG_member ] [__pad3] [line 330, size 64, align 64, offset 1344] [from ]
-!73 = !{!"0xd\00__pad4\00331\0064\0064\001408\000", !30, !29, !67} ; [ DW_TAG_member ] [__pad4] [line 331, size 64, align 64, offset 1408] [from ]
-!74 = !{!"0xd\00__pad5\00332\0064\0064\001472\000", !30, !29, !75} ; [ DW_TAG_member ] [__pad5] [line 332, size 64, align 64, offset 1472] [from size_t]
-!75 = !{!"0x16\00size_t\0042\000\000\000\000", !30, null, !76} ; [ DW_TAG_typedef ] [size_t] [line 42, size 0, align 0, offset 0] [from long unsigned int]
-!76 = !{!"0x24\00long unsigned int\000\0064\0064\000\000\007", null, null} ; [ DW_TAG_base_type ] [long unsigned int] [line 0, size 64, align 64, offset 0, enc DW_ATE_unsigned]
-!77 = !{!"0xd\00_mode\00334\0032\0032\001536\000", !30, !29, !8} ; [ DW_TAG_member ] [_mode] [line 334, size 32, align 32, offset 1536] [from int]
-!78 = !{!"0xd\00_unused2\00336\00160\008\001568\000", !30, !29, !79} ; [ DW_TAG_member ] [_unused2] [line 336, size 160, align 8, offset 1568] [from ]
-!79 = !{!"0x1\00\000\00160\008\000\000", null, null, !11, !80, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 160, align 8, offset 0] [from char]
+!65 = !DISubrange(count: 1)
+!66 = !DIDerivedType(tag: DW_TAG_member, name: "_lock", line: 310, size: 64, align: 64, offset: 1088, file: !30, scope: !29, baseType: !67)
+!67 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: null)
+!68 = !DIDerivedType(tag: DW_TAG_member, name: "_offset", line: 319, size: 64, align: 64, offset: 1152, file: !30, scope: !29, baseType: !69)
+!69 = !DIDerivedType(tag: DW_TAG_typedef, name: "__off64_t", line: 142, file: !30, baseType: !57)
+!70 = !DIDerivedType(tag: DW_TAG_member, name: "__pad1", line: 328, size: 64, align: 64, offset: 1216, file: !30, scope: !29, baseType: !67)
+!71 = !DIDerivedType(tag: DW_TAG_member, name: "__pad2", line: 329, size: 64, align: 64, offset: 1280, file: !30, scope: !29, baseType: !67)
+!72 = !DIDerivedType(tag: DW_TAG_member, name: "__pad3", line: 330, size: 64, align: 64, offset: 1344, file: !30, scope: !29, baseType: !67)
+!73 = !DIDerivedType(tag: DW_TAG_member, name: "__pad4", line: 331, size: 64, align: 64, offset: 1408, file: !30, scope: !29, baseType: !67)
+!74 = !DIDerivedType(tag: DW_TAG_member, name: "__pad5", line: 332, size: 64, align: 64, offset: 1472, file: !30, scope: !29, baseType: !75)
+!75 = !DIDerivedType(tag: DW_TAG_typedef, name: "size_t", line: 42, file: !30, baseType: !76)
+!76 = !DIBasicType(tag: DW_TAG_base_type, name: "long unsigned int", size: 64, align: 64, encoding: DW_ATE_unsigned)
+!77 = !DIDerivedType(tag: DW_TAG_member, name: "_mode", line: 334, size: 32, align: 32, offset: 1536, file: !30, scope: !29, baseType: !8)
+!78 = !DIDerivedType(tag: DW_TAG_member, name: "_unused2", line: 336, size: 160, align: 8, offset: 1568, file: !30, scope: !29, baseType: !79)
+!79 = !DICompositeType(tag: DW_TAG_array_type, size: 160, align: 8, baseType: !11, elements: !80)
 !80 = !{!81}
-!81 = !{!"0x21\000\0020"}       ; [ DW_TAG_subrange_type ] [0, 19]
-!82 = !{!"0x2e\00verify\00verify\00\002388\001\001\000\006\00256\001\002388", !1, !5, !83, null, null, null, null, !86} ; [ DW_TAG_subprogram ] [line 2388] [local] [def] [verify]
-!83 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !84, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!81 = !DISubrange(count: 20)
+!82 = !DISubprogram(name: "verify", line: 2388, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2388, file: !1, scope: !5, type: !83, variables: !86)
+!83 = !DISubroutineType(types: !84)
 !84 = !{null, !8, !10, !85}
-!85 = !{!"0xf\00\000\0064\0064\000\000", null, null, !24} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from boolean]
+!85 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !24)
 !86 = !{!87, !88, !89, !90, !94, !95, !96, !97, !98, !99, !100, !101}
-!87 = !{!"0x101\00no_time_steps\0016779604\000", !82, !5, !8} ; [ DW_TAG_arg_variable ] [no_time_steps] [line 2388]
-!88 = !{!"0x101\00class\0033556820\000", !82, !5, !10} ; [ DW_TAG_arg_variable ] [class] [line 2388]
-!89 = !{!"0x101\00verified\0050334036\000", !82, !5, !85} ; [ DW_TAG_arg_variable ] [verified] [line 2388]
-!90 = !{!"0x100\00xcrref\002397\000", !82, !5, !91} ; [ DW_TAG_auto_variable ] [xcrref] [line 2397]
-!91 = !{!"0x1\00\000\00320\0064\000\000", null, null, !20, !92, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 320, align 64, offset 0] [from double]
+!87 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "no_time_steps", line: 2388, arg: 1, scope: !82, file: !5, type: !8)
+!88 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "class", line: 2388, arg: 2, scope: !82, file: !5, type: !10)
+!89 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "verified", line: 2388, arg: 3, scope: !82, file: !5, type: !85)
+!90 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xcrref", line: 2397, scope: !82, file: !5, type: !91)
+!91 = !DICompositeType(tag: DW_TAG_array_type, size: 320, align: 64, baseType: !20, elements: !92)
 !92 = !{!93}
-!93 = !{!"0x21\000\005"}        ; [ DW_TAG_subrange_type ] [0, 4]
-!94 = !{!"0x100\00xceref\002397\000", !82, !5, !91} ; [ DW_TAG_auto_variable ] [xceref] [line 2397]
-!95 = !{!"0x100\00xcrdif\002397\000", !82, !5, !91} ; [ DW_TAG_auto_variable ] [xcrdif] [line 2397]
-!96 = !{!"0x100\00xcedif\002397\000", !82, !5, !91} ; [ DW_TAG_auto_variable ] [xcedif] [line 2397]
-!97 = !{!"0x100\00epsilon\002398\000", !82, !5, !20} ; [ DW_TAG_auto_variable ] [epsilon] [line 2398]
-!98 = !{!"0x100\00xce\002398\000", !82, !5, !91} ; [ DW_TAG_auto_variable ] [xce] [line 2398]
-!99 = !{!"0x100\00xcr\002398\000", !82, !5, !91} ; [ DW_TAG_auto_variable ] [xcr] [line 2398]
-!100 = !{!"0x100\00dtref\002398\000", !82, !5, !20} ; [ DW_TAG_auto_variable ] [dtref] [line 2398]
-!101 = !{!"0x100\00m\002399\000", !82, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 2399]
-!102 = !{!"0x2e\00rhs_norm\00rhs_norm\00\00266\001\001\000\006\00256\001\00266", !1, !5, !103, null, null, null, null, !106} ; [ DW_TAG_subprogram ] [line 266] [local] [def] [rhs_norm]
-!103 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !104, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!93 = !DISubrange(count: 5)
+!94 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xceref", line: 2397, scope: !82, file: !5, type: !91)
+!95 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xcrdif", line: 2397, scope: !82, file: !5, type: !91)
+!96 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xcedif", line: 2397, scope: !82, file: !5, type: !91)
+!97 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "epsilon", line: 2398, scope: !82, file: !5, type: !20)
+!98 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xce", line: 2398, scope: !82, file: !5, type: !91)
+!99 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xcr", line: 2398, scope: !82, file: !5, type: !91)
+!100 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "dtref", line: 2398, scope: !82, file: !5, type: !20)
+!101 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 2399, scope: !82, file: !5, type: !8)
+!102 = !DISubprogram(name: "rhs_norm", line: 266, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 266, file: !1, scope: !5, type: !103, variables: !106)
+!103 = !DISubroutineType(types: !104)
 !104 = !{null, !105}
-!105 = !{!"0xf\00\000\0064\0064\000\000", null, null, !20} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from double]
+!105 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !20)
 !106 = !{!107, !108, !109, !110, !111, !112, !113}
-!107 = !{!"0x101\00rms\0016777482\000", !102, !5, !105} ; [ DW_TAG_arg_variable ] [rms] [line 266]
-!108 = !{!"0x100\00i\00271\000", !102, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 271]
-!109 = !{!"0x100\00j\00271\000", !102, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 271]
-!110 = !{!"0x100\00k\00271\000", !102, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 271]
-!111 = !{!"0x100\00d\00271\000", !102, !5, !8} ; [ DW_TAG_auto_variable ] [d] [line 271]
-!112 = !{!"0x100\00m\00271\000", !102, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 271]
-!113 = !{!"0x100\00add\00272\000", !102, !5, !20} ; [ DW_TAG_auto_variable ] [add] [line 272]
-!114 = !{!"0x2e\00compute_rhs\00compute_rhs\00\001767\001\001\000\006\00256\001\001767", !1, !5, !115, null, void ()* @compute_rhs, null, null, !117} ; [ DW_TAG_subprogram ] [line 1767] [local] [def] [compute_rhs]
-!115 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !116, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!107 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "rms", line: 266, arg: 1, scope: !102, file: !5, type: !105)
+!108 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 271, scope: !102, file: !5, type: !8)
+!109 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 271, scope: !102, file: !5, type: !8)
+!110 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 271, scope: !102, file: !5, type: !8)
+!111 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "d", line: 271, scope: !102, file: !5, type: !8)
+!112 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 271, scope: !102, file: !5, type: !8)
+!113 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "add", line: 272, scope: !102, file: !5, type: !20)
+!114 = !DISubprogram(name: "compute_rhs", line: 1767, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1767, file: !1, scope: !5, type: !115, function: void ()* @compute_rhs, variables: !117)
+!115 = !DISubroutineType(types: !116)
 !116 = !{null}
 !117 = !{!118, !119, !120, !121, !122, !123, !124, !125, !126, !127, !128, !129, !130, !131}
-!118 = !{!"0x100\00i\001769\000", !114, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 1769]
-!119 = !{!"0x100\00j\001769\000", !114, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 1769]
-!120 = !{!"0x100\00k\001769\000", !114, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 1769]
-!121 = !{!"0x100\00m\001769\000", !114, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 1769]
-!122 = !{!"0x100\00rho_inv\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [rho_inv] [line 1770]
-!123 = !{!"0x100\00uijk\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [uijk] [line 1770]
-!124 = !{!"0x100\00up1\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [up1] [line 1770]
-!125 = !{!"0x100\00um1\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [um1] [line 1770]
-!126 = !{!"0x100\00vijk\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [vijk] [line 1770]
-!127 = !{!"0x100\00vp1\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [vp1] [line 1770]
-!128 = !{!"0x100\00vm1\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [vm1] [line 1770]
-!129 = !{!"0x100\00wijk\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [wijk] [line 1770]
-!130 = !{!"0x100\00wp1\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [wp1] [line 1770]
-!131 = !{!"0x100\00wm1\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [wm1] [line 1770]
-!132 = !{!"0x2e\00error_norm\00error_norm\00\00225\001\001\000\006\00256\001\00225", !1, !5, !103, null, null, null, null, !133} ; [ DW_TAG_subprogram ] [line 225] [local] [def] [error_norm]
+!118 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 1769, scope: !114, file: !5, type: !8)
+!119 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 1769, scope: !114, file: !5, type: !8)
+!120 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 1769, scope: !114, file: !5, type: !8)
+!121 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 1769, scope: !114, file: !5, type: !8)
+!122 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "rho_inv", line: 1770, scope: !114, file: !5, type: !20)
+!123 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "uijk", line: 1770, scope: !114, file: !5, type: !20)
+!124 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "up1", line: 1770, scope: !114, file: !5, type: !20)
+!125 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "um1", line: 1770, scope: !114, file: !5, type: !20)
+!126 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vijk", line: 1770, scope: !114, file: !5, type: !20)
+!127 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vp1", line: 1770, scope: !114, file: !5, type: !20)
+!128 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vm1", line: 1770, scope: !114, file: !5, type: !20)
+!129 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "wijk", line: 1770, scope: !114, file: !5, type: !20)
+!130 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "wp1", line: 1770, scope: !114, file: !5, type: !20)
+!131 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "wm1", line: 1770, scope: !114, file: !5, type: !20)
+!132 = !DISubprogram(name: "error_norm", line: 225, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 225, file: !1, scope: !5, type: !103, variables: !133)
 !133 = !{!134, !135, !136, !137, !138, !139, !140, !141, !142, !143, !144}
-!134 = !{!"0x101\00rms\0016777441\000", !132, !5, !105} ; [ DW_TAG_arg_variable ] [rms] [line 225]
-!135 = !{!"0x100\00i\00232\000", !132, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 232]
-!136 = !{!"0x100\00j\00232\000", !132, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 232]
-!137 = !{!"0x100\00k\00232\000", !132, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 232]
-!138 = !{!"0x100\00m\00232\000", !132, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 232]
-!139 = !{!"0x100\00d\00232\000", !132, !5, !8} ; [ DW_TAG_auto_variable ] [d] [line 232]
-!140 = !{!"0x100\00xi\00233\000", !132, !5, !20} ; [ DW_TAG_auto_variable ] [xi] [line 233]
-!141 = !{!"0x100\00eta\00233\000", !132, !5, !20} ; [ DW_TAG_auto_variable ] [eta] [line 233]
-!142 = !{!"0x100\00zeta\00233\000", !132, !5, !20} ; [ DW_TAG_auto_variable ] [zeta] [line 233]
-!143 = !{!"0x100\00u_exact\00233\000", !132, !5, !91} ; [ DW_TAG_auto_variable ] [u_exact] [line 233]
-!144 = !{!"0x100\00add\00233\000", !132, !5, !20} ; [ DW_TAG_auto_variable ] [add] [line 233]
-!145 = !{!"0x2e\00exact_solution\00exact_solution\00\00643\001\001\000\006\00256\001\00644", !1, !5, !146, null, null, null, null, !148} ; [ DW_TAG_subprogram ] [line 643] [local] [def] [scope 644] [exact_solution]
-!146 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !147, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!134 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "rms", line: 225, arg: 1, scope: !132, file: !5, type: !105)
+!135 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 232, scope: !132, file: !5, type: !8)
+!136 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 232, scope: !132, file: !5, type: !8)
+!137 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 232, scope: !132, file: !5, type: !8)
+!138 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 232, scope: !132, file: !5, type: !8)
+!139 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "d", line: 232, scope: !132, file: !5, type: !8)
+!140 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xi", line: 233, scope: !132, file: !5, type: !20)
+!141 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "eta", line: 233, scope: !132, file: !5, type: !20)
+!142 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "zeta", line: 233, scope: !132, file: !5, type: !20)
+!143 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "u_exact", line: 233, scope: !132, file: !5, type: !91)
+!144 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "add", line: 233, scope: !132, file: !5, type: !20)
+!145 = !DISubprogram(name: "exact_solution", line: 643, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 644, file: !1, scope: !5, type: !146, variables: !148)
+!146 = !DISubroutineType(types: !147)
 !147 = !{null, !20, !20, !20, !105}
 !148 = !{!149, !150, !151, !152, !153}
-!149 = !{!"0x101\00xi\0016777859\000", !145, !5, !20} ; [ DW_TAG_arg_variable ] [xi] [line 643]
-!150 = !{!"0x101\00eta\0033555075\000", !145, !5, !20} ; [ DW_TAG_arg_variable ] [eta] [line 643]
-!151 = !{!"0x101\00zeta\0050332291\000", !145, !5, !20} ; [ DW_TAG_arg_variable ] [zeta] [line 643]
-!152 = !{!"0x101\00dtemp\0067109508\000", !145, !5, !105} ; [ DW_TAG_arg_variable ] [dtemp] [line 644]
-!153 = !{!"0x100\00m\00653\000", !145, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 653]
-!154 = !{!"0x2e\00set_constants\00set_constants\00\002191\001\001\000\006\00256\001\002191", !1, !5, !115, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 2191] [local] [def] [set_constants]
-!155 = !{!"0x2e\00lhsinit\00lhsinit\00\00855\001\001\000\006\00256\001\00855", !1, !5, !115, null, null, null, null, !156} ; [ DW_TAG_subprogram ] [line 855] [local] [def] [lhsinit]
+!149 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "xi", line: 643, arg: 1, scope: !145, file: !5, type: !20)
+!150 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "eta", line: 643, arg: 2, scope: !145, file: !5, type: !20)
+!151 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "zeta", line: 643, arg: 3, scope: !145, file: !5, type: !20)
+!152 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "dtemp", line: 644, arg: 4, scope: !145, file: !5, type: !105)
+!153 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 653, scope: !145, file: !5, type: !8)
+!154 = !DISubprogram(name: "set_constants", line: 2191, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2191, file: !1, scope: !5, type: !115, variables: !2)
+!155 = !DISubprogram(name: "lhsinit", line: 855, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 855, file: !1, scope: !5, type: !115, variables: !156)
 !156 = !{!157, !158, !159, !160, !161}
-!157 = !{!"0x100\00i\00857\000", !155, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 857]
-!158 = !{!"0x100\00j\00857\000", !155, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 857]
-!159 = !{!"0x100\00k\00857\000", !155, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 857]
-!160 = !{!"0x100\00m\00857\000", !155, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 857]
-!161 = !{!"0x100\00n\00857\000", !155, !5, !8} ; [ DW_TAG_auto_variable ] [n] [line 857]
-!162 = !{!"0x2e\00initialize\00initialize\00\00669\001\001\000\006\00256\001\00669", !1, !5, !115, null, null, null, null, !163} ; [ DW_TAG_subprogram ] [line 669] [local] [def] [initialize]
+!157 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 857, scope: !155, file: !5, type: !8)
+!158 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 857, scope: !155, file: !5, type: !8)
+!159 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 857, scope: !155, file: !5, type: !8)
+!160 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 857, scope: !155, file: !5, type: !8)
+!161 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "n", line: 857, scope: !155, file: !5, type: !8)
+!162 = !DISubprogram(name: "initialize", line: 669, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 669, file: !1, scope: !5, type: !115, variables: !163)
 !163 = !{!164, !165, !166, !167, !168, !169, !170, !171, !172, !173, !174, !179, !180, !181, !182}
-!164 = !{!"0x100\00i\00679\000", !162, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 679]
-!165 = !{!"0x100\00j\00679\000", !162, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 679]
-!166 = !{!"0x100\00k\00679\000", !162, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 679]
-!167 = !{!"0x100\00m\00679\000", !162, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 679]
-!168 = !{!"0x100\00ix\00679\000", !162, !5, !8} ; [ DW_TAG_auto_variable ] [ix] [line 679]
-!169 = !{!"0x100\00iy\00679\000", !162, !5, !8} ; [ DW_TAG_auto_variable ] [iy] [line 679]
-!170 = !{!"0x100\00iz\00679\000", !162, !5, !8} ; [ DW_TAG_auto_variable ] [iz] [line 679]
-!171 = !{!"0x100\00xi\00680\000", !162, !5, !20} ; [ DW_TAG_auto_variable ] [xi] [line 680]
-!172 = !{!"0x100\00eta\00680\000", !162, !5, !20} ; [ DW_TAG_auto_variable ] [eta] [line 680]
-!173 = !{!"0x100\00zeta\00680\000", !162, !5, !20} ; [ DW_TAG_auto_variable ] [zeta] [line 680]
-!174 = !{!"0x100\00Pface\00680\000", !162, !5, !175} ; [ DW_TAG_auto_variable ] [Pface] [line 680]
-!175 = !{!"0x1\00\000\001920\0064\000\000", null, null, !20, !176, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 1920, align 64, offset 0] [from double]
+!164 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 679, scope: !162, file: !5, type: !8)
+!165 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 679, scope: !162, file: !5, type: !8)
+!166 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 679, scope: !162, file: !5, type: !8)
+!167 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 679, scope: !162, file: !5, type: !8)
+!168 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "ix", line: 679, scope: !162, file: !5, type: !8)
+!169 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "iy", line: 679, scope: !162, file: !5, type: !8)
+!170 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "iz", line: 679, scope: !162, file: !5, type: !8)
+!171 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xi", line: 680, scope: !162, file: !5, type: !20)
+!172 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "eta", line: 680, scope: !162, file: !5, type: !20)
+!173 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "zeta", line: 680, scope: !162, file: !5, type: !20)
+!174 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "Pface", line: 680, scope: !162, file: !5, type: !175)
+!175 = !DICompositeType(tag: DW_TAG_array_type, size: 1920, align: 64, baseType: !20, elements: !176)
 !176 = !{!177, !178, !93}
-!177 = !{!"0x21\000\002"}       ; [ DW_TAG_subrange_type ] [0, 1]
-!178 = !{!"0x21\000\003"}       ; [ DW_TAG_subrange_type ] [0, 2]
-!179 = !{!"0x100\00Pxi\00680\000", !162, !5, !20} ; [ DW_TAG_auto_variable ] [Pxi] [line 680]
-!180 = !{!"0x100\00Peta\00680\000", !162, !5, !20} ; [ DW_TAG_auto_variable ] [Peta] [line 680]
-!181 = !{!"0x100\00Pzeta\00680\000", !162, !5, !20} ; [ DW_TAG_auto_variable ] [Pzeta] [line 680]
-!182 = !{!"0x100\00temp\00680\000", !162, !5, !91} ; [ DW_TAG_auto_variable ] [temp] [line 680]
-!183 = !{!"0x2e\00exact_rhs\00exact_rhs\00\00301\001\001\000\006\00256\001\00301", !1, !5, !115, null, null, null, null, !184} ; [ DW_TAG_subprogram ] [line 301] [local] [def] [exact_rhs]
+!177 = !DISubrange(count: 2)
+!178 = !DISubrange(count: 3)
+!179 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "Pxi", line: 680, scope: !162, file: !5, type: !20)
+!180 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "Peta", line: 680, scope: !162, file: !5, type: !20)
+!181 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "Pzeta", line: 680, scope: !162, file: !5, type: !20)
+!182 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "temp", line: 680, scope: !162, file: !5, type: !91)
+!183 = !DISubprogram(name: "exact_rhs", line: 301, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 301, file: !1, scope: !5, type: !115, variables: !184)
 !184 = !{!185, !186, !187, !188, !189, !190, !191, !192, !193, !194, !195, !196, !197, !198, !199}
-!185 = !{!"0x100\00dtemp\00310\000", !183, !5, !91} ; [ DW_TAG_auto_variable ] [dtemp] [line 310]
-!186 = !{!"0x100\00xi\00310\000", !183, !5, !20} ; [ DW_TAG_auto_variable ] [xi] [line 310]
-!187 = !{!"0x100\00eta\00310\000", !183, !5, !20} ; [ DW_TAG_auto_variable ] [eta] [line 310]
-!188 = !{!"0x100\00zeta\00310\000", !183, !5, !20} ; [ DW_TAG_auto_variable ] [zeta] [line 310]
-!189 = !{!"0x100\00dtpp\00310\000", !183, !5, !20} ; [ DW_TAG_auto_variable ] [dtpp] [line 310]
-!190 = !{!"0x100\00m\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 311]
-!191 = !{!"0x100\00i\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 311]
-!192 = !{!"0x100\00j\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 311]
-!193 = !{!"0x100\00k\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 311]
-!194 = !{!"0x100\00ip1\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [ip1] [line 311]
-!195 = !{!"0x100\00im1\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [im1] [line 311]
-!196 = !{!"0x100\00jp1\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [jp1] [line 311]
-!197 = !{!"0x100\00jm1\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [jm1] [line 311]
-!198 = !{!"0x100\00km1\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [km1] [line 311]
-!199 = !{!"0x100\00kp1\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [kp1] [line 311]
-!200 = !{!"0x2e\00adi\00adi\00\00210\001\001\000\006\00256\001\00210", !1, !5, !115, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 210] [local] [def] [adi]
-!201 = !{!"0x2e\00add\00add\00\00187\001\001\000\006\00256\001\00187", !1, !5, !115, null, null, null, null, !202} ; [ DW_TAG_subprogram ] [line 187] [local] [def] [add]
+!185 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "dtemp", line: 310, scope: !183, file: !5, type: !91)
+!186 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xi", line: 310, scope: !183, file: !5, type: !20)
+!187 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "eta", line: 310, scope: !183, file: !5, type: !20)
+!188 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "zeta", line: 310, scope: !183, file: !5, type: !20)
+!189 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "dtpp", line: 310, scope: !183, file: !5, type: !20)
+!190 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 311, scope: !183, file: !5, type: !8)
+!191 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 311, scope: !183, file: !5, type: !8)
+!192 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 311, scope: !183, file: !5, type: !8)
+!193 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 311, scope: !183, file: !5, type: !8)
+!194 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "ip1", line: 311, scope: !183, file: !5, type: !8)
+!195 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "im1", line: 311, scope: !183, file: !5, type: !8)
+!196 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "jp1", line: 311, scope: !183, file: !5, type: !8)
+!197 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "jm1", line: 311, scope: !183, file: !5, type: !8)
+!198 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "km1", line: 311, scope: !183, file: !5, type: !8)
+!199 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "kp1", line: 311, scope: !183, file: !5, type: !8)
+!200 = !DISubprogram(name: "adi", line: 210, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 210, file: !1, scope: !5, type: !115, variables: !2)
+!201 = !DISubprogram(name: "add", line: 187, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 187, file: !1, scope: !5, type: !115, variables: !202)
 !202 = !{!203, !204, !205, !206}
-!203 = !{!"0x100\00i\00193\000", !201, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 193]
-!204 = !{!"0x100\00j\00193\000", !201, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 193]
-!205 = !{!"0x100\00k\00193\000", !201, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 193]
-!206 = !{!"0x100\00m\00193\000", !201, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 193]
-!207 = !{!"0x2e\00z_solve\00z_solve\00\003457\001\001\000\006\00256\001\003457", !1, !5, !115, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 3457] [local] [def] [z_solve]
-!208 = !{!"0x2e\00z_backsubstitute\00z_backsubstitute\00\003480\001\001\000\006\00256\001\003480", !1, !5, !115, null, null, null, null, !209} ; [ DW_TAG_subprogram ] [line 3480] [local] [def] [z_backsubstitute]
+!203 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 193, scope: !201, file: !5, type: !8)
+!204 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 193, scope: !201, file: !5, type: !8)
+!205 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 193, scope: !201, file: !5, type: !8)
+!206 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 193, scope: !201, file: !5, type: !8)
+!207 = !DISubprogram(name: "z_solve", line: 3457, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3457, file: !1, scope: !5, type: !115, variables: !2)
+!208 = !DISubprogram(name: "z_backsubstitute", line: 3480, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3480, file: !1, scope: !5, type: !115, variables: !209)
 !209 = !{!210, !211, !212, !213, !214}
-!210 = !{!"0x100\00i\003492\000", !208, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 3492]
-!211 = !{!"0x100\00j\003492\000", !208, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 3492]
-!212 = !{!"0x100\00k\003492\000", !208, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 3492]
-!213 = !{!"0x100\00m\003492\000", !208, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 3492]
-!214 = !{!"0x100\00n\003492\000", !208, !5, !8} ; [ DW_TAG_auto_variable ] [n] [line 3492]
-!215 = !{!"0x2e\00z_solve_cell\00z_solve_cell\00\003512\001\001\000\006\00256\001\003512", !1, !5, !115, null, null, null, null, !216} ; [ DW_TAG_subprogram ] [line 3512] [local] [def] [z_solve_cell]
+!210 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 3492, scope: !208, file: !5, type: !8)
+!211 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 3492, scope: !208, file: !5, type: !8)
+!212 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 3492, scope: !208, file: !5, type: !8)
+!213 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 3492, scope: !208, file: !5, type: !8)
+!214 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "n", line: 3492, scope: !208, file: !5, type: !8)
+!215 = !DISubprogram(name: "z_solve_cell", line: 3512, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3512, file: !1, scope: !5, type: !115, variables: !216)
 !216 = !{!217, !218, !219, !220}
-!217 = !{!"0x100\00i\003527\000", !215, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 3527]
-!218 = !{!"0x100\00j\003527\000", !215, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 3527]
-!219 = !{!"0x100\00k\003527\000", !215, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 3527]
-!220 = !{!"0x100\00ksize\003527\000", !215, !5, !8} ; [ DW_TAG_auto_variable ] [ksize] [line 3527]
-!221 = !{!"0x2e\00binvrhs\00binvrhs\00\003154\001\001\000\006\00256\001\003154", !1, !5, !222, null, null, null, null, !225} ; [ DW_TAG_subprogram ] [line 3154] [local] [def] [binvrhs]
-!222 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !223, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!217 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 3527, scope: !215, file: !5, type: !8)
+!218 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 3527, scope: !215, file: !5, type: !8)
+!219 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 3527, scope: !215, file: !5, type: !8)
+!220 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "ksize", line: 3527, scope: !215, file: !5, type: !8)
+!221 = !DISubprogram(name: "binvrhs", line: 3154, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3154, file: !1, scope: !5, type: !222, variables: !225)
+!222 = !DISubroutineType(types: !223)
 !223 = !{null, !224, !105}
-!224 = !{!"0xf\00\000\0064\0064\000\000", null, null, !91} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
+!224 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !91)
 !225 = !{!226, !227, !228, !229}
-!226 = !{!"0x101\00lhs\0016780370\000", !221, !5, !224} ; [ DW_TAG_arg_variable ] [lhs] [line 3154]
-!227 = !{!"0x101\00r\0033557586\000", !221, !5, !105} ; [ DW_TAG_arg_variable ] [r] [line 3154]
-!228 = !{!"0x100\00pivot\003159\000", !221, !5, !20} ; [ DW_TAG_auto_variable ] [pivot] [line 3159]
-!229 = !{!"0x100\00coeff\003159\000", !221, !5, !20} ; [ DW_TAG_auto_variable ] [coeff] [line 3159]
-!230 = !{!"0x2e\00matmul_sub\00matmul_sub\00\002841\001\001\000\006\00256\001\002842", !1, !5, !231, null, null, null, null, !233} ; [ DW_TAG_subprogram ] [line 2841] [local] [def] [scope 2842] [matmul_sub]
-!231 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !232, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!226 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "lhs", line: 3154, arg: 1, scope: !221, file: !5, type: !224)
+!227 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "r", line: 3154, arg: 2, scope: !221, file: !5, type: !105)
+!228 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "pivot", line: 3159, scope: !221, file: !5, type: !20)
+!229 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "coeff", line: 3159, scope: !221, file: !5, type: !20)
+!230 = !DISubprogram(name: "matmul_sub", line: 2841, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2842, file: !1, scope: !5, type: !231, variables: !233)
+!231 = !DISubroutineType(types: !232)
 !232 = !{null, !224, !224, !224}
 !233 = !{!234, !235, !236, !237}
-!234 = !{!"0x101\00ablock\0016780057\000", !230, !5, !224} ; [ DW_TAG_arg_variable ] [ablock] [line 2841]
-!235 = !{!"0x101\00bblock\0033557273\000", !230, !5, !224} ; [ DW_TAG_arg_variable ] [bblock] [line 2841]
-!236 = !{!"0x101\00cblock\0050334490\000", !230, !5, !224} ; [ DW_TAG_arg_variable ] [cblock] [line 2842]
-!237 = !{!"0x100\00j\002851\000", !230, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 2851]
-!238 = !{!"0x2e\00matvec_sub\00matvec_sub\00\002814\001\001\000\006\00256\001\002814", !1, !5, !239, null, null, null, null, !241} ; [ DW_TAG_subprogram ] [line 2814] [local] [def] [matvec_sub]
-!239 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !240, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!234 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ablock", line: 2841, arg: 1, scope: !230, file: !5, type: !224)
+!235 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "bblock", line: 2841, arg: 2, scope: !230, file: !5, type: !224)
+!236 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "cblock", line: 2842, arg: 3, scope: !230, file: !5, type: !224)
+!237 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 2851, scope: !230, file: !5, type: !8)
+!238 = !DISubprogram(name: "matvec_sub", line: 2814, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2814, file: !1, scope: !5, type: !239, variables: !241)
+!239 = !DISubroutineType(types: !240)
 !240 = !{null, !224, !105, !105}
 !241 = !{!242, !243, !244, !245}
-!242 = !{!"0x101\00ablock\0016780030\000", !238, !5, !224} ; [ DW_TAG_arg_variable ] [ablock] [line 2814]
-!243 = !{!"0x101\00avec\0033557246\000", !238, !5, !105} ; [ DW_TAG_arg_variable ] [avec] [line 2814]
-!244 = !{!"0x101\00bvec\0050334462\000", !238, !5, !105} ; [ DW_TAG_arg_variable ] [bvec] [line 2814]
-!245 = !{!"0x100\00i\002823\000", !238, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 2823]
-!246 = !{!"0x2e\00binvcrhs\00binvcrhs\00\002885\001\001\000\006\00256\001\002885", !1, !5, !247, null, null, null, null, !249} ; [ DW_TAG_subprogram ] [line 2885] [local] [def] [binvcrhs]
-!247 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !248, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!242 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ablock", line: 2814, arg: 1, scope: !238, file: !5, type: !224)
+!243 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "avec", line: 2814, arg: 2, scope: !238, file: !5, type: !105)
+!244 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "bvec", line: 2814, arg: 3, scope: !238, file: !5, type: !105)
+!245 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 2823, scope: !238, file: !5, type: !8)
+!246 = !DISubprogram(name: "binvcrhs", line: 2885, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2885, file: !1, scope: !5, type: !247, variables: !249)
+!247 = !DISubroutineType(types: !248)
 !248 = !{null, !224, !224, !105}
 !249 = !{!250, !251, !252, !253, !254}
-!250 = !{!"0x101\00lhs\0016780101\000", !246, !5, !224} ; [ DW_TAG_arg_variable ] [lhs] [line 2885]
-!251 = !{!"0x101\00c\0033557317\000", !246, !5, !224} ; [ DW_TAG_arg_variable ] [c] [line 2885]
-!252 = !{!"0x101\00r\0050334533\000", !246, !5, !105} ; [ DW_TAG_arg_variable ] [r] [line 2885]
-!253 = !{!"0x100\00pivot\002890\000", !246, !5, !20} ; [ DW_TAG_auto_variable ] [pivot] [line 2890]
-!254 = !{!"0x100\00coeff\002890\000", !246, !5, !20} ; [ DW_TAG_auto_variable ] [coeff] [line 2890]
-!255 = !{!"0x2e\00lhsz\00lhsz\00\001475\001\001\000\006\00256\001\001475", !1, !5, !115, null, null, null, null, !256} ; [ DW_TAG_subprogram ] [line 1475] [local] [def] [lhsz]
+!250 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "lhs", line: 2885, arg: 1, scope: !246, file: !5, type: !224)
+!251 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 2885, arg: 2, scope: !246, file: !5, type: !224)
+!252 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "r", line: 2885, arg: 3, scope: !246, file: !5, type: !105)
+!253 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "pivot", line: 2890, scope: !246, file: !5, type: !20)
+!254 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "coeff", line: 2890, scope: !246, file: !5, type: !20)
+!255 = !DISubprogram(name: "lhsz", line: 1475, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1475, file: !1, scope: !5, type: !115, variables: !256)
 !256 = !{!257, !258, !259}
-!257 = !{!"0x100\00i\001484\000", !255, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 1484]
-!258 = !{!"0x100\00j\001484\000", !255, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 1484]
-!259 = !{!"0x100\00k\001484\000", !255, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 1484]
-!260 = !{!"0x2e\00y_solve\00y_solve\00\003299\001\001\000\006\00256\001\003299", !1, !5, !115, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 3299] [local] [def] [y_solve]
-!261 = !{!"0x2e\00y_backsubstitute\00y_backsubstitute\00\003323\001\001\000\006\00256\001\003323", !1, !5, !115, null, null, null, null, !262} ; [ DW_TAG_subprogram ] [line 3323] [local] [def] [y_backsubstitute]
+!257 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 1484, scope: !255, file: !5, type: !8)
+!258 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 1484, scope: !255, file: !5, type: !8)
+!259 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 1484, scope: !255, file: !5, type: !8)
+!260 = !DISubprogram(name: "y_solve", line: 3299, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3299, file: !1, scope: !5, type: !115, variables: !2)
+!261 = !DISubprogram(name: "y_backsubstitute", line: 3323, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3323, file: !1, scope: !5, type: !115, variables: !262)
 !262 = !{!263, !264, !265, !266, !267}
-!263 = !{!"0x100\00i\003335\000", !261, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 3335]
-!264 = !{!"0x100\00j\003335\000", !261, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 3335]
-!265 = !{!"0x100\00k\003335\000", !261, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 3335]
-!266 = !{!"0x100\00m\003335\000", !261, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 3335]
-!267 = !{!"0x100\00n\003335\000", !261, !5, !8} ; [ DW_TAG_auto_variable ] [n] [line 3335]
-!268 = !{!"0x2e\00y_solve_cell\00y_solve_cell\00\003355\001\001\000\006\00256\001\003355", !1, !5, !115, null, null, null, null, !269} ; [ DW_TAG_subprogram ] [line 3355] [local] [def] [y_solve_cell]
+!263 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 3335, scope: !261, file: !5, type: !8)
+!264 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 3335, scope: !261, file: !5, type: !8)
+!265 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 3335, scope: !261, file: !5, type: !8)
+!266 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 3335, scope: !261, file: !5, type: !8)
+!267 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "n", line: 3335, scope: !261, file: !5, type: !8)
+!268 = !DISubprogram(name: "y_solve_cell", line: 3355, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3355, file: !1, scope: !5, type: !115, variables: !269)
 !269 = !{!270, !271, !272, !273}
-!270 = !{!"0x100\00i\003370\000", !268, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 3370]
-!271 = !{!"0x100\00j\003370\000", !268, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 3370]
-!272 = !{!"0x100\00k\003370\000", !268, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 3370]
-!273 = !{!"0x100\00jsize\003370\000", !268, !5, !8} ; [ DW_TAG_auto_variable ] [jsize] [line 3370]
-!274 = !{!"0x2e\00lhsy\00lhsy\00\001181\001\001\000\006\00256\001\001181", !1, !5, !115, null, null, null, null, !275} ; [ DW_TAG_subprogram ] [line 1181] [local] [def] [lhsy]
+!270 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 3370, scope: !268, file: !5, type: !8)
+!271 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 3370, scope: !268, file: !5, type: !8)
+!272 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 3370, scope: !268, file: !5, type: !8)
+!273 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "jsize", line: 3370, scope: !268, file: !5, type: !8)
+!274 = !DISubprogram(name: "lhsy", line: 1181, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1181, file: !1, scope: !5, type: !115, variables: !275)
 !275 = !{!276, !277, !278}
-!276 = !{!"0x100\00i\001190\000", !274, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 1190]
-!277 = !{!"0x100\00j\001190\000", !274, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 1190]
-!278 = !{!"0x100\00k\001190\000", !274, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 1190]
-!279 = !{!"0x2e\00x_solve\00x_solve\00\002658\001\001\000\006\00256\001\002658", !1, !5, !115, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 2658] [local] [def] [x_solve]
-!280 = !{!"0x2e\00x_backsubstitute\00x_backsubstitute\00\002684\001\001\000\006\00256\001\002684", !1, !5, !115, null, null, null, null, !281} ; [ DW_TAG_subprogram ] [line 2684] [local] [def] [x_backsubstitute]
+!276 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 1190, scope: !274, file: !5, type: !8)
+!277 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 1190, scope: !274, file: !5, type: !8)
+!278 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 1190, scope: !274, file: !5, type: !8)
+!279 = !DISubprogram(name: "x_solve", line: 2658, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2658, file: !1, scope: !5, type: !115, variables: !2)
+!280 = !DISubprogram(name: "x_backsubstitute", line: 2684, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2684, file: !1, scope: !5, type: !115, variables: !281)
 !281 = !{!282, !283, !284, !285, !286}
-!282 = !{!"0x100\00i\002696\000", !280, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 2696]
-!283 = !{!"0x100\00j\002696\000", !280, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 2696]
-!284 = !{!"0x100\00k\002696\000", !280, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 2696]
-!285 = !{!"0x100\00m\002696\000", !280, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 2696]
-!286 = !{!"0x100\00n\002696\000", !280, !5, !8} ; [ DW_TAG_auto_variable ] [n] [line 2696]
-!287 = !{!"0x2e\00x_solve_cell\00x_solve_cell\00\002716\001\001\000\006\00256\001\002716", !1, !5, !115, null, null, null, null, !288} ; [ DW_TAG_subprogram ] [line 2716] [local] [def] [x_solve_cell]
+!282 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 2696, scope: !280, file: !5, type: !8)
+!283 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 2696, scope: !280, file: !5, type: !8)
+!284 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 2696, scope: !280, file: !5, type: !8)
+!285 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 2696, scope: !280, file: !5, type: !8)
+!286 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "n", line: 2696, scope: !280, file: !5, type: !8)
+!287 = !DISubprogram(name: "x_solve_cell", line: 2716, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2716, file: !1, scope: !5, type: !115, variables: !288)
 !288 = !{!289, !290, !291, !292}
-!289 = !{!"0x100\00i\002728\000", !287, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 2728]
-!290 = !{!"0x100\00j\002728\000", !287, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 2728]
-!291 = !{!"0x100\00k\002728\000", !287, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 2728]
-!292 = !{!"0x100\00isize\002728\000", !287, !5, !8} ; [ DW_TAG_auto_variable ] [isize] [line 2728]
-!293 = !{!"0x2e\00lhsx\00lhsx\00\00898\001\001\000\006\00256\001\00898", !1, !5, !115, null, null, null, null, !294} ; [ DW_TAG_subprogram ] [line 898] [local] [def] [lhsx]
+!289 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 2728, scope: !287, file: !5, type: !8)
+!290 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 2728, scope: !287, file: !5, type: !8)
+!291 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 2728, scope: !287, file: !5, type: !8)
+!292 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "isize", line: 2728, scope: !287, file: !5, type: !8)
+!293 = !DISubprogram(name: "lhsx", line: 898, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 898, file: !1, scope: !5, type: !115, variables: !294)
 !294 = !{!295, !296, !297}
-!295 = !{!"0x100\00i\00907\000", !293, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 907]
-!296 = !{!"0x100\00j\00907\000", !293, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 907]
-!297 = !{!"0x100\00k\00907\000", !293, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 907]
+!295 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 907, scope: !293, file: !5, type: !8)
+!296 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 907, scope: !293, file: !5, type: !8)
+!297 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 907, scope: !293, file: !5, type: !8)
 !298 = !{!299, !304, !305, !309, !310, !311, !312, !313, !314, !315, !316, !317, !318, !319, !320, !321, !322, !323, !324, !325, !326, !327, !328, !329, !330, !331, !332, !333, !334, !335, !336, !337, !338, !339, !340, !341, !342, !343, !347, !350, !351, !352, !353, !354, !355, !356, !360, !361, !362, !363, !364, !365, !366, !367, !368, !369, !370, !371, !372, !373, !374, !375, !376, !377, !378, !379, !380, !381, !382, !383, !384, !385, !386, !387, !388, !389, !390, !391, !392, !393, !394, !395, !396, !397, !398, !399, !400, !401, !402, !403, !404, !405, !406, !407, !408, !409, !410, !411, !412, !413, !414, !415, !416, !417, !418, !419, !422, !426, !427, !430, !431, !434, !435, !436, !437}
-!299 = !{!"0x34\00grid_points\00grid_points\00\0028\001\001", null, !300, !302, [3 x i32]* @grid_points, null} ; [ DW_TAG_variable ] [grid_points] [line 28] [local] [def]
-!300 = !{!"0x29", !301}      ; [ DW_TAG_file_type ] [/home/hfinkel/src/NPB2.3-omp-C/BT/./header.h]
+!299 = !DIGlobalVariable(name: "grid_points", line: 28, isLocal: true, isDefinition: true, scope: null, file: !300, type: !302, variable: [3 x i32]* @grid_points)
+!300 = !DIFile(filename: "./header.h", directory: "/home/hfinkel/src/NPB2.3-omp-C/BT")
 !301 = !{!"./header.h", !"/home/hfinkel/src/NPB2.3-omp-C/BT"}
-!302 = !{!"0x1\00\000\0096\0032\000\000", null, null, !8, !303, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 96, align 32, offset 0] [from int]
+!302 = !DICompositeType(tag: DW_TAG_array_type, size: 96, align: 32, baseType: !8, elements: !303)
 !303 = !{!178}
-!304 = !{!"0x34\00dt\00dt\00\0035\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dt] [line 35] [local] [def]
-!305 = !{!"0x34\00rhs\00rhs\00\0068\001\001", null, !300, !306, null, null} ; [ DW_TAG_variable ] [rhs] [line 68] [local] [def]
-!306 = !{!"0x1\00\000\001385839040\0064\000\000", null, null, !20, !307, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 1385839040, align 64, offset 0] [from double]
+!304 = !DIGlobalVariable(name: "dt", line: 35, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!305 = !DIGlobalVariable(name: "rhs", line: 68, isLocal: true, isDefinition: true, scope: null, file: !300, type: !306)
+!306 = !DICompositeType(tag: DW_TAG_array_type, size: 1385839040, align: 64, baseType: !20, elements: !307)
 !307 = !{!308, !308, !308, !93}
-!308 = !{!"0x21\000\00163"}     ; [ DW_TAG_subrange_type ] [0, 162]
-!309 = !{!"0x34\00zzcon5\00zzcon5\00\0042\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [zzcon5] [line 42] [local] [def]
-!310 = !{!"0x34\00zzcon4\00zzcon4\00\0042\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [zzcon4] [line 42] [local] [def]
-!311 = !{!"0x34\00zzcon3\00zzcon3\00\0042\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [zzcon3] [line 42] [local] [def]
-!312 = !{!"0x34\00dz5tz1\00dz5tz1\00\0043\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz5tz1] [line 43] [local] [def]
-!313 = !{!"0x34\00dz4tz1\00dz4tz1\00\0043\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz4tz1] [line 43] [local] [def]
-!314 = !{!"0x34\00dz3tz1\00dz3tz1\00\0043\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz3tz1] [line 43] [local] [def]
-!315 = !{!"0x34\00zzcon2\00zzcon2\00\0042\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [zzcon2] [line 42] [local] [def]
-!316 = !{!"0x34\00dz2tz1\00dz2tz1\00\0043\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz2tz1] [line 43] [local] [def]
-!317 = !{!"0x34\00tz2\00tz2\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tz2] [line 31] [local] [def]
-!318 = !{!"0x34\00dz1tz1\00dz1tz1\00\0043\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz1tz1] [line 43] [local] [def]
-!319 = !{!"0x34\00yycon5\00yycon5\00\0040\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [yycon5] [line 40] [local] [def]
-!320 = !{!"0x34\00yycon4\00yycon4\00\0040\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [yycon4] [line 40] [local] [def]
-!321 = !{!"0x34\00yycon3\00yycon3\00\0040\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [yycon3] [line 40] [local] [def]
-!322 = !{!"0x34\00dy5ty1\00dy5ty1\00\0041\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy5ty1] [line 41] [local] [def]
-!323 = !{!"0x34\00dy4ty1\00dy4ty1\00\0041\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy4ty1] [line 41] [local] [def]
-!324 = !{!"0x34\00dy3ty1\00dy3ty1\00\0041\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy3ty1] [line 41] [local] [def]
-!325 = !{!"0x34\00yycon2\00yycon2\00\0040\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [yycon2] [line 40] [local] [def]
-!326 = !{!"0x34\00dy2ty1\00dy2ty1\00\0041\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy2ty1] [line 41] [local] [def]
-!327 = !{!"0x34\00ty2\00ty2\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [ty2] [line 31] [local] [def]
-!328 = !{!"0x34\00dy1ty1\00dy1ty1\00\0041\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy1ty1] [line 41] [local] [def]
-!329 = !{!"0x34\00dssp\00dssp\00\0035\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dssp] [line 35] [local] [def]
-!330 = !{!"0x34\00c1\00c1\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c1] [line 45] [local] [def]
-!331 = !{!"0x34\00xxcon5\00xxcon5\00\0038\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [xxcon5] [line 38] [local] [def]
-!332 = !{!"0x34\00xxcon4\00xxcon4\00\0038\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [xxcon4] [line 38] [local] [def]
-!333 = !{!"0x34\00xxcon3\00xxcon3\00\0038\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [xxcon3] [line 38] [local] [def]
-!334 = !{!"0x34\00dx5tx1\00dx5tx1\00\0039\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx5tx1] [line 39] [local] [def]
-!335 = !{!"0x34\00dx4tx1\00dx4tx1\00\0039\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx4tx1] [line 39] [local] [def]
-!336 = !{!"0x34\00dx3tx1\00dx3tx1\00\0039\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx3tx1] [line 39] [local] [def]
-!337 = !{!"0x34\00c2\00c2\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c2] [line 45] [local] [def]
-!338 = !{!"0x34\00con43\00con43\00\0048\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [con43] [line 48] [local] [def]
-!339 = !{!"0x34\00xxcon2\00xxcon2\00\0038\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [xxcon2] [line 38] [local] [def]
-!340 = !{!"0x34\00dx2tx1\00dx2tx1\00\0039\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx2tx1] [line 39] [local] [def]
-!341 = !{!"0x34\00tx2\00tx2\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tx2] [line 31] [local] [def]
-!342 = !{!"0x34\00dx1tx1\00dx1tx1\00\0039\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx1tx1] [line 39] [local] [def]
-!343 = !{!"0x34\00forcing\00forcing\00\0066\001\001", null, !300, !344, null, null} ; [ DW_TAG_variable ] [forcing] [line 66] [local] [def]
-!344 = !{!"0x1\00\000\001663006848\0064\000\000", null, null, !20, !345, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 1663006848, align 64, offset 0] [from double]
+!308 = !DISubrange(count: 163)
+!309 = !DIGlobalVariable(name: "zzcon5", line: 42, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!310 = !DIGlobalVariable(name: "zzcon4", line: 42, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!311 = !DIGlobalVariable(name: "zzcon3", line: 42, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!312 = !DIGlobalVariable(name: "dz5tz1", line: 43, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!313 = !DIGlobalVariable(name: "dz4tz1", line: 43, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!314 = !DIGlobalVariable(name: "dz3tz1", line: 43, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!315 = !DIGlobalVariable(name: "zzcon2", line: 42, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!316 = !DIGlobalVariable(name: "dz2tz1", line: 43, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!317 = !DIGlobalVariable(name: "tz2", line: 31, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!318 = !DIGlobalVariable(name: "dz1tz1", line: 43, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!319 = !DIGlobalVariable(name: "yycon5", line: 40, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!320 = !DIGlobalVariable(name: "yycon4", line: 40, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!321 = !DIGlobalVariable(name: "yycon3", line: 40, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!322 = !DIGlobalVariable(name: "dy5ty1", line: 41, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!323 = !DIGlobalVariable(name: "dy4ty1", line: 41, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!324 = !DIGlobalVariable(name: "dy3ty1", line: 41, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!325 = !DIGlobalVariable(name: "yycon2", line: 40, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!326 = !DIGlobalVariable(name: "dy2ty1", line: 41, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!327 = !DIGlobalVariable(name: "ty2", line: 31, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!328 = !DIGlobalVariable(name: "dy1ty1", line: 41, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!329 = !DIGlobalVariable(name: "dssp", line: 35, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!330 = !DIGlobalVariable(name: "c1", line: 45, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!331 = !DIGlobalVariable(name: "xxcon5", line: 38, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!332 = !DIGlobalVariable(name: "xxcon4", line: 38, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!333 = !DIGlobalVariable(name: "xxcon3", line: 38, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!334 = !DIGlobalVariable(name: "dx5tx1", line: 39, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!335 = !DIGlobalVariable(name: "dx4tx1", line: 39, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!336 = !DIGlobalVariable(name: "dx3tx1", line: 39, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!337 = !DIGlobalVariable(name: "c2", line: 45, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!338 = !DIGlobalVariable(name: "con43", line: 48, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!339 = !DIGlobalVariable(name: "xxcon2", line: 38, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!340 = !DIGlobalVariable(name: "dx2tx1", line: 39, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!341 = !DIGlobalVariable(name: "tx2", line: 31, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!342 = !DIGlobalVariable(name: "dx1tx1", line: 39, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!343 = !DIGlobalVariable(name: "forcing", line: 66, isLocal: true, isDefinition: true, scope: null, file: !300, type: !344)
+!344 = !DICompositeType(tag: DW_TAG_array_type, size: 1663006848, align: 64, baseType: !20, elements: !345)
 !345 = !{!308, !308, !308, !346}
-!346 = !{!"0x21\000\006"}       ; [ DW_TAG_subrange_type ] [0, 5]
-!347 = !{!"0x34\00qs\00qs\00\0063\001\001", null, !300, !348, null, null} ; [ DW_TAG_variable ] [qs] [line 63] [local] [def]
-!348 = !{!"0x1\00\000\00277167808\0064\000\000", null, null, !20, !349, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 277167808, align 64, offset 0] [from double]
+!346 = !DISubrange(count: 6)
+!347 = !DIGlobalVariable(name: "qs", line: 63, isLocal: true, isDefinition: true, scope: null, file: !300, type: !348)
+!348 = !DICompositeType(tag: DW_TAG_array_type, size: 277167808, align: 64, baseType: !20, elements: !349)
 !349 = !{!308, !308, !308}
-!350 = !{!"0x34\00square\00square\00\0065\001\001", null, !300, !348, null, null} ; [ DW_TAG_variable ] [square] [line 65] [local] [def]
-!351 = !{!"0x34\00ws\00ws\00\0062\001\001", null, !300, !348, null, null} ; [ DW_TAG_variable ] [ws] [line 62] [local] [def]
-!352 = !{!"0x34\00vs\00vs\00\0061\001\001", null, !300, !348, null, null} ; [ DW_TAG_variable ] [vs] [line 61] [local] [def]
-!353 = !{!"0x34\00us\00us\00\0060\001\001", null, !300, !348, null, null} ; [ DW_TAG_variable ] [us] [line 60] [local] [def]
-!354 = !{!"0x34\00rho_i\00rho_i\00\0064\001\001", null, !300, !348, null, null} ; [ DW_TAG_variable ] [rho_i] [line 64] [local] [def]
-!355 = !{!"0x34\00u\00u\00\0067\001\001", null, !300, !306, null, null} ; [ DW_TAG_variable ] [u] [line 67] [local] [def]
-!356 = !{!"0x34\00ce\00ce\00\0036\001\001", null, !300, !357, null, null} ; [ DW_TAG_variable ] [ce] [line 36] [local] [def]
-!357 = !{!"0x1\00\000\004160\0064\000\000", null, null, !20, !358, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 4160, align 64, offset 0] [from double]
+!350 = !DIGlobalVariable(name: "square", line: 65, isLocal: true, isDefinition: true, scope: null, file: !300, type: !348)
+!351 = !DIGlobalVariable(name: "ws", line: 62, isLocal: true, isDefinition: true, scope: null, file: !300, type: !348)
+!352 = !DIGlobalVariable(name: "vs", line: 61, isLocal: true, isDefinition: true, scope: null, file: !300, type: !348)
+!353 = !DIGlobalVariable(name: "us", line: 60, isLocal: true, isDefinition: true, scope: null, file: !300, type: !348)
+!354 = !DIGlobalVariable(name: "rho_i", line: 64, isLocal: true, isDefinition: true, scope: null, file: !300, type: !348)
+!355 = !DIGlobalVariable(name: "u", line: 67, isLocal: true, isDefinition: true, scope: null, file: !300, type: !306)
+!356 = !DIGlobalVariable(name: "ce", line: 36, isLocal: true, isDefinition: true, scope: null, file: !300, type: !357)
+!357 = !DICompositeType(tag: DW_TAG_array_type, size: 4160, align: 64, baseType: !20, elements: !358)
 !358 = !{!93, !359}
-!359 = !{!"0x21\000\0013"}      ; [ DW_TAG_subrange_type ] [0, 12]
-!360 = !{!"0x34\00dnzm1\00dnzm1\00\0044\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dnzm1] [line 44] [local] [def]
-!361 = !{!"0x34\00dnym1\00dnym1\00\0044\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dnym1] [line 44] [local] [def]
-!362 = !{!"0x34\00dnxm1\00dnxm1\00\0044\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dnxm1] [line 44] [local] [def]
-!363 = !{!"0x34\00zzcon1\00zzcon1\00\0042\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [zzcon1] [line 42] [local] [def]
-!364 = !{!"0x34\00yycon1\00yycon1\00\0040\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [yycon1] [line 40] [local] [def]
-!365 = !{!"0x34\00xxcon1\00xxcon1\00\0038\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [xxcon1] [line 38] [local] [def]
-!366 = !{!"0x34\00con16\00con16\00\0048\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [con16] [line 48] [local] [def]
-!367 = !{!"0x34\00c2iv\00c2iv\00\0048\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c2iv] [line 48] [local] [def]
-!368 = !{!"0x34\00c3c4tz3\00c3c4tz3\00\0048\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c3c4tz3] [line 48] [local] [def]
-!369 = !{!"0x34\00c3c4ty3\00c3c4ty3\00\0048\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c3c4ty3] [line 48] [local] [def]
-!370 = !{!"0x34\00c3c4tx3\00c3c4tx3\00\0048\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c3c4tx3] [line 48] [local] [def]
-!371 = !{!"0x34\00comz6\00comz6\00\0047\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [comz6] [line 47] [local] [def]
-!372 = !{!"0x34\00comz5\00comz5\00\0047\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [comz5] [line 47] [local] [def]
-!373 = !{!"0x34\00comz4\00comz4\00\0047\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [comz4] [line 47] [local] [def]
-!374 = !{!"0x34\00comz1\00comz1\00\0047\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [comz1] [line 47] [local] [def]
-!375 = !{!"0x34\00dtdssp\00dtdssp\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dtdssp] [line 45] [local] [def]
-!376 = !{!"0x34\00c2dttz1\00c2dttz1\00\0047\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c2dttz1] [line 47] [local] [def]
-!377 = !{!"0x34\00c2dtty1\00c2dtty1\00\0047\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c2dtty1] [line 47] [local] [def]
-!378 = !{!"0x34\00c2dttx1\00c2dttx1\00\0047\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c2dttx1] [line 47] [local] [def]
-!379 = !{!"0x34\00dttz2\00dttz2\00\0046\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dttz2] [line 46] [local] [def]
-!380 = !{!"0x34\00dttz1\00dttz1\00\0046\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dttz1] [line 46] [local] [def]
-!381 = !{!"0x34\00dtty2\00dtty2\00\0046\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dtty2] [line 46] [local] [def]
-!382 = !{!"0x34\00dtty1\00dtty1\00\0046\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dtty1] [line 46] [local] [def]
-!383 = !{!"0x34\00dttx2\00dttx2\00\0046\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dttx2] [line 46] [local] [def]
-!384 = !{!"0x34\00dttx1\00dttx1\00\0046\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dttx1] [line 46] [local] [def]
-!385 = !{!"0x34\00c5dssp\00c5dssp\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c5dssp] [line 45] [local] [def]
-!386 = !{!"0x34\00c4dssp\00c4dssp\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c4dssp] [line 45] [local] [def]
-!387 = !{!"0x34\00dzmax\00dzmax\00\0037\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dzmax] [line 37] [local] [def]
-!388 = !{!"0x34\00dymax\00dymax\00\0037\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dymax] [line 37] [local] [def]
-!389 = !{!"0x34\00dxmax\00dxmax\00\0037\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dxmax] [line 37] [local] [def]
-!390 = !{!"0x34\00dz5\00dz5\00\0034\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz5] [line 34] [local] [def]
-!391 = !{!"0x34\00dz4\00dz4\00\0034\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz4] [line 34] [local] [def]
-!392 = !{!"0x34\00dz3\00dz3\00\0034\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz3] [line 34] [local] [def]
-!393 = !{!"0x34\00dz2\00dz2\00\0034\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz2] [line 34] [local] [def]
-!394 = !{!"0x34\00dz1\00dz1\00\0034\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz1] [line 34] [local] [def]
-!395 = !{!"0x34\00dy5\00dy5\00\0033\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy5] [line 33] [local] [def]
-!396 = !{!"0x34\00dy4\00dy4\00\0033\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy4] [line 33] [local] [def]
-!397 = !{!"0x34\00dy3\00dy3\00\0033\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy3] [line 33] [local] [def]
-!398 = !{!"0x34\00dy2\00dy2\00\0033\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy2] [line 33] [local] [def]
-!399 = !{!"0x34\00dy1\00dy1\00\0033\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy1] [line 33] [local] [def]
-!400 = !{!"0x34\00dx5\00dx5\00\0032\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx5] [line 32] [local] [def]
-!401 = !{!"0x34\00dx4\00dx4\00\0032\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx4] [line 32] [local] [def]
-!402 = !{!"0x34\00dx3\00dx3\00\0032\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx3] [line 32] [local] [def]
-!403 = !{!"0x34\00dx2\00dx2\00\0032\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx2] [line 32] [local] [def]
-!404 = !{!"0x34\00dx1\00dx1\00\0032\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx1] [line 32] [local] [def]
-!405 = !{!"0x34\00tz3\00tz3\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tz3] [line 31] [local] [def]
-!406 = !{!"0x34\00tz1\00tz1\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tz1] [line 31] [local] [def]
-!407 = !{!"0x34\00ty3\00ty3\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [ty3] [line 31] [local] [def]
-!408 = !{!"0x34\00ty1\00ty1\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [ty1] [line 31] [local] [def]
-!409 = !{!"0x34\00tx3\00tx3\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tx3] [line 31] [local] [def]
-!410 = !{!"0x34\00tx1\00tx1\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tx1] [line 31] [local] [def]
-!411 = !{!"0x34\00conz1\00conz1\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [conz1] [line 45] [local] [def]
-!412 = !{!"0x34\00c1345\00c1345\00\0044\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c1345] [line 44] [local] [def]
-!413 = !{!"0x34\00c3c4\00c3c4\00\0044\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c3c4] [line 44] [local] [def]
-!414 = !{!"0x34\00c1c5\00c1c5\00\0044\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c1c5] [line 44] [local] [def]
-!415 = !{!"0x34\00c1c2\00c1c2\00\0044\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c1c2] [line 44] [local] [def]
-!416 = !{!"0x34\00c5\00c5\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c5] [line 45] [local] [def]
-!417 = !{!"0x34\00c4\00c4\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c4] [line 45] [local] [def]
-!418 = !{!"0x34\00c3\00c3\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c3] [line 45] [local] [def]
-!419 = !{!"0x34\00lhs\00lhs\00\0069\001\001", null, !300, !420, null, null} ; [ DW_TAG_variable ] [lhs] [line 69] [local] [def]
-!420 = !{!"0x1\00\000\0020787585600\0064\000\000", null, null, !20, !421, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 20787585600, align 64, offset 0] [from double]
+!359 = !DISubrange(count: 13)
+!360 = !DIGlobalVariable(name: "dnzm1", line: 44, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!361 = !DIGlobalVariable(name: "dnym1", line: 44, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!362 = !DIGlobalVariable(name: "dnxm1", line: 44, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!363 = !DIGlobalVariable(name: "zzcon1", line: 42, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!364 = !DIGlobalVariable(name: "yycon1", line: 40, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!365 = !DIGlobalVariable(name: "xxcon1", line: 38, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!366 = !DIGlobalVariable(name: "con16", line: 48, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!367 = !DIGlobalVariable(name: "c2iv", line: 48, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!368 = !DIGlobalVariable(name: "c3c4tz3", line: 48, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!369 = !DIGlobalVariable(name: "c3c4ty3", line: 48, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!370 = !DIGlobalVariable(name: "c3c4tx3", line: 48, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!371 = !DIGlobalVariable(name: "comz6", line: 47, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!372 = !DIGlobalVariable(name: "comz5", line: 47, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!373 = !DIGlobalVariable(name: "comz4", line: 47, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!374 = !DIGlobalVariable(name: "comz1", line: 47, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!375 = !DIGlobalVariable(name: "dtdssp", line: 45, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!376 = !DIGlobalVariable(name: "c2dttz1", line: 47, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!377 = !DIGlobalVariable(name: "c2dtty1", line: 47, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!378 = !DIGlobalVariable(name: "c2dttx1", line: 47, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!379 = !DIGlobalVariable(name: "dttz2", line: 46, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!380 = !DIGlobalVariable(name: "dttz1", line: 46, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!381 = !DIGlobalVariable(name: "dtty2", line: 46, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!382 = !DIGlobalVariable(name: "dtty1", line: 46, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!383 = !DIGlobalVariable(name: "dttx2", line: 46, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!384 = !DIGlobalVariable(name: "dttx1", line: 46, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!385 = !DIGlobalVariable(name: "c5dssp", line: 45, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!386 = !DIGlobalVariable(name: "c4dssp", line: 45, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!387 = !DIGlobalVariable(name: "dzmax", line: 37, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!388 = !DIGlobalVariable(name: "dymax", line: 37, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!389 = !DIGlobalVariable(name: "dxmax", line: 37, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!390 = !DIGlobalVariable(name: "dz5", line: 34, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!391 = !DIGlobalVariable(name: "dz4", line: 34, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!392 = !DIGlobalVariable(name: "dz3", line: 34, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!393 = !DIGlobalVariable(name: "dz2", line: 34, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!394 = !DIGlobalVariable(name: "dz1", line: 34, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!395 = !DIGlobalVariable(name: "dy5", line: 33, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!396 = !DIGlobalVariable(name: "dy4", line: 33, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!397 = !DIGlobalVariable(name: "dy3", line: 33, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!398 = !DIGlobalVariable(name: "dy2", line: 33, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!399 = !DIGlobalVariable(name: "dy1", line: 33, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!400 = !DIGlobalVariable(name: "dx5", line: 32, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!401 = !DIGlobalVariable(name: "dx4", line: 32, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!402 = !DIGlobalVariable(name: "dx3", line: 32, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!403 = !DIGlobalVariable(name: "dx2", line: 32, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!404 = !DIGlobalVariable(name: "dx1", line: 32, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!405 = !DIGlobalVariable(name: "tz3", line: 31, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!406 = !DIGlobalVariable(name: "tz1", line: 31, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!407 = !DIGlobalVariable(name: "ty3", line: 31, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!408 = !DIGlobalVariable(name: "ty1", line: 31, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!409 = !DIGlobalVariable(name: "tx3", line: 31, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!410 = !DIGlobalVariable(name: "tx1", line: 31, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!411 = !DIGlobalVariable(name: "conz1", line: 45, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!412 = !DIGlobalVariable(name: "c1345", line: 44, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!413 = !DIGlobalVariable(name: "c3c4", line: 44, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!414 = !DIGlobalVariable(name: "c1c5", line: 44, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!415 = !DIGlobalVariable(name: "c1c2", line: 44, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!416 = !DIGlobalVariable(name: "c5", line: 45, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!417 = !DIGlobalVariable(name: "c4", line: 45, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!418 = !DIGlobalVariable(name: "c3", line: 45, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!419 = !DIGlobalVariable(name: "lhs", line: 69, isLocal: true, isDefinition: true, scope: null, file: !300, type: !420)
+!420 = !DICompositeType(tag: DW_TAG_array_type, size: 20787585600, align: 64, baseType: !20, elements: !421)
 !421 = !{!308, !308, !308, !178, !93, !93}
-!422 = !{!"0x34\00q\00q\00\0073\001\001", null, !300, !423, null, null} ; [ DW_TAG_variable ] [q] [line 73] [local] [def]
-!423 = !{!"0x1\00\000\0010368\0064\000\000", null, null, !20, !424, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 10368, align 64, offset 0] [from double]
+!422 = !DIGlobalVariable(name: "q", line: 73, isLocal: true, isDefinition: true, scope: null, file: !300, type: !423)
+!423 = !DICompositeType(tag: DW_TAG_array_type, size: 10368, align: 64, baseType: !20, elements: !424)
 !424 = !{!425}
-!425 = !{!"0x21\000\00162"}     ; [ DW_TAG_subrange_type ] [0, 161]
-!426 = !{!"0x34\00cuf\00cuf\00\0072\001\001", null, !300, !423, null, null} ; [ DW_TAG_variable ] [cuf] [line 72] [local] [def]
-!427 = !{!"0x34\00buf\00buf\00\0075\001\001", null, !300, !428, null, null} ; [ DW_TAG_variable ] [buf] [line 75] [local] [def]
-!428 = !{!"0x1\00\000\0051840\0064\000\000", null, null, !20, !429, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 51840, align 64, offset 0] [from double]
+!425 = !DISubrange(count: 162)
+!426 = !DIGlobalVariable(name: "cuf", line: 72, isLocal: true, isDefinition: true, scope: null, file: !300, type: !423)
+!427 = !DIGlobalVariable(name: "buf", line: 75, isLocal: true, isDefinition: true, scope: null, file: !300, type: !428)
+!428 = !DICompositeType(tag: DW_TAG_array_type, size: 51840, align: 64, baseType: !20, elements: !429)
 !429 = !{!425, !93}
-!430 = !{!"0x34\00ue\00ue\00\0074\001\001", null, !300, !428, null, null} ; [ DW_TAG_variable ] [ue] [line 74] [local] [def]
-!431 = !{!"0x34\00njac\00njac\00\0086\001\001", null, !300, !432, null, null} ; [ DW_TAG_variable ] [njac] [line 86] [local] [def]
-!432 = !{!"0x1\00\000\006886684800\0064\000\000", null, null, !20, !433, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 6886684800, align 64, offset 0] [from double]
+!430 = !DIGlobalVariable(name: "ue", line: 74, isLocal: true, isDefinition: true, scope: null, file: !300, type: !428)
+!431 = !DIGlobalVariable(name: "njac", line: 86, isLocal: true, isDefinition: true, scope: null, file: !300, type: !432)
+!432 = !DICompositeType(tag: DW_TAG_array_type, size: 6886684800, align: 64, baseType: !20, elements: !433)
 !433 = !{!308, !308, !425, !93, !93}
-!434 = !{!"0x34\00fjac\00fjac\00\0084\001\001", null, !300, !432, null, null} ; [ DW_TAG_variable ] [fjac] [line 84] [local] [def]
-!435 = !{!"0x34\00tmp3\00tmp3\00\0088\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tmp3] [line 88] [local] [def]
-!436 = !{!"0x34\00tmp2\00tmp2\00\0088\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tmp2] [line 88] [local] [def]
-!437 = !{!"0x34\00tmp1\00tmp1\00\0088\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tmp1] [line 88] [local] [def]
+!434 = !DIGlobalVariable(name: "fjac", line: 84, isLocal: true, isDefinition: true, scope: null, file: !300, type: !432)
+!435 = !DIGlobalVariable(name: "tmp3", line: 88, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!436 = !DIGlobalVariable(name: "tmp2", line: 88, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
+!437 = !DIGlobalVariable(name: "tmp1", line: 88, isLocal: true, isDefinition: true, scope: null, file: !300, type: !20)
 !438 = !{i32 2, !"Dwarf Version", i32 4}
-!439 = !MDLocation(line: 1898, scope: !440)
-!440 = !{!"0xb\001898\000\00107", !1, !114} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c]
-!441 = !MDLocation(line: 1913, scope: !442)
-!442 = !{!"0xb\001913\000\00115", !1, !114} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c]
-!443 = !MDLocation(line: 1923, scope: !114)
+!439 = !DILocation(line: 1898, scope: !440)
+!440 = distinct !DILexicalBlock(line: 1898, column: 0, file: !1, scope: !114)
+!441 = !DILocation(line: 1913, scope: !442)
+!442 = distinct !DILexicalBlock(line: 1913, column: 0, file: !1, scope: !114)
+!443 = !DILocation(line: 1923, scope: !114)
 !444 = !{!"int", !445}
 !445 = !{!"omnipotent char", !446}
 !446 = !{!"Simple C/C++ TBAA"}
 !447 = !{i32 1}
-!448 = !MDLocation(line: 1925, scope: !449)
-!449 = !{!"0xb\001925\000\00121", !1, !114} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c]
-!450 = !MDLocation(line: 1939, scope: !451)
-!451 = !{!"0xb\001939\000\00127", !1, !114} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c]
-!452 = !MDLocation(line: 1940, scope: !453)
-!453 = !{!"0xb\001940\000\00129", !1, !454} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c]
-!454 = !{!"0xb\001939\000\00128", !1, !451} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c]
-!455 = !MDLocation(line: 1941, scope: !456)
-!456 = !{!"0xb\001941\000\00131", !1, !457} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c]
-!457 = !{!"0xb\001940\000\00130", !1, !453} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c]
-!458 = !MDLocation(line: 2020, scope: !459)
-!459 = !{!"0xb\002020\000\00149", !1, !460} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c]
-!460 = !{!"0xb\002019\000\00148", !1, !461} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c]
-!461 = !{!"0xb\002019\000\00147", !1, !462} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c]
-!462 = !{!"0xb\002018\000\00146", !1, !463} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c]
-!463 = !{!"0xb\002018\000\00145", !1, !114} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c]
-!464 = !{i32 1, !"Debug Info Version", i32 2}
+!448 = !DILocation(line: 1925, scope: !449)
+!449 = distinct !DILexicalBlock(line: 1925, column: 0, file: !1, scope: !114)
+!450 = !DILocation(line: 1939, scope: !451)
+!451 = distinct !DILexicalBlock(line: 1939, column: 0, file: !1, scope: !114)
+!452 = !DILocation(line: 1940, scope: !453)
+!453 = distinct !DILexicalBlock(line: 1940, column: 0, file: !1, scope: !454)
+!454 = distinct !DILexicalBlock(line: 1939, column: 0, file: !1, scope: !451)
+!455 = !DILocation(line: 1941, scope: !456)
+!456 = distinct !DILexicalBlock(line: 1941, column: 0, file: !1, scope: !457)
+!457 = distinct !DILexicalBlock(line: 1940, column: 0, file: !1, scope: !453)
+!458 = !DILocation(line: 2020, scope: !459)
+!459 = distinct !DILexicalBlock(line: 2020, column: 0, file: !1, scope: !460)
+!460 = distinct !DILexicalBlock(line: 2019, column: 0, file: !1, scope: !461)
+!461 = distinct !DILexicalBlock(line: 2019, column: 0, file: !1, scope: !462)
+!462 = distinct !DILexicalBlock(line: 2018, column: 0, file: !1, scope: !463)
+!463 = distinct !DILexicalBlock(line: 2018, column: 0, file: !1, scope: !114)
+!464 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/PowerPC/pr17354.ll b/test/CodeGen/PowerPC/pr17354.ll
index dca81b1c2ca6..ed6fd3480dd4 100644
--- a/test/CodeGen/PowerPC/pr17354.ll
+++ b/test/CodeGen/PowerPC/pr17354.ll
@@ -14,7 +14,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define internal void @__cxx_global_var_init() section ".text.startup" {
 entry:
-  call void @_Z4funcv(%struct.CS* sret getelementptr inbounds ([1 x %struct.CS]* @_ZL3glb, i64 0, i64 0))
+  call void @_Z4funcv(%struct.CS* sret getelementptr inbounds ([1 x %struct.CS], [1 x %struct.CS]* @_ZL3glb, i64 0, i64 0))
   ret void
 }
 
@@ -25,7 +25,7 @@ entry:
 ; Function Attrs: nounwind
 define void @_Z4funcv(%struct.CS* noalias sret %agg.result) #0 {
 entry:
-  %a_ = getelementptr inbounds %struct.CS* %agg.result, i32 0, i32 0
+  %a_ = getelementptr inbounds %struct.CS, %struct.CS* %agg.result, i32 0, i32 0
   store i32 0, i32* %a_, align 4
   ret void
 }
diff --git a/test/CodeGen/PowerPC/pr18663.ll b/test/CodeGen/PowerPC/pr18663.ll
index 1b85223aa09a..04bc39276f90 100644
--- a/test/CodeGen/PowerPC/pr18663.ll
+++ b/test/CodeGen/PowerPC/pr18663.ll
@@ -61,21 +61,21 @@
 
 define void @_ZNK18TriaObjectAccessorILi3ELi3EE10barycenterEv(%class.Point.1* noalias nocapture sret %agg.result, %class.TriaObjectAccessor.57* %this) #0 align 2 {
 entry:
-  %0 = load double* null, align 8
-  %1 = load double* undef, align 8
+  %0 = load double, double* null, align 8
+  %1 = load double, double* undef, align 8
   %call18 = tail call dereferenceable(24) %class.Point.1* @_ZNK18TriaObjectAccessorILi3ELi3EE6vertexEj(%class.TriaObjectAccessor.57* %this, i32 zeroext 6)
-  %2 = load double* undef, align 8
+  %2 = load double, double* undef, align 8
   %call21 = tail call dereferenceable(24) %class.Point.1* @_ZNK18TriaObjectAccessorILi3ELi3EE6vertexEj(%class.TriaObjectAccessor.57* %this, i32 zeroext 7)
-  %3 = load double* undef, align 8
+  %3 = load double, double* undef, align 8
   %call33 = tail call dereferenceable(24) %class.Point.1* @_ZNK18TriaObjectAccessorILi3ELi3EE6vertexEj(%class.TriaObjectAccessor.57* %this, i32 zeroext 3)
-  %4 = load double* null, align 8
-  %5 = load double* undef, align 8
+  %4 = load double, double* null, align 8
+  %5 = load double, double* undef, align 8
   %call45 = tail call dereferenceable(24) %class.Point.1* @_ZNK18TriaObjectAccessorILi3ELi3EE6vertexEj(%class.TriaObjectAccessor.57* %this, i32 zeroext 7)
-  %6 = load double* undef, align 8
+  %6 = load double, double* undef, align 8
   %call48 = tail call dereferenceable(24) %class.Point.1* @_ZNK18TriaObjectAccessorILi3ELi3EE6vertexEj(%class.TriaObjectAccessor.57* %this, i32 zeroext 0)
-  %7 = load double* undef, align 8
+  %7 = load double, double* undef, align 8
   %call66 = tail call dereferenceable(24) %class.Point.1* @_ZNK18TriaObjectAccessorILi3ELi3EE6vertexEj(%class.TriaObjectAccessor.57* %this, i32 zeroext 6)
-  %8 = load double* undef, align 8
+  %8 = load double, double* undef, align 8
   %mul334 = fmul double undef, 2.000000e+00
   %mul579 = fmul double %2, %5
   %mul597 = fmul double undef, %mul579
diff --git a/test/CodeGen/PowerPC/pr20442.ll b/test/CodeGen/PowerPC/pr20442.ll
index ad43a04e70c4..555c3dae1f47 100644
--- a/test/CodeGen/PowerPC/pr20442.ll
+++ b/test/CodeGen/PowerPC/pr20442.ll
@@ -20,15 +20,15 @@ target triple = "powerpc-unknown-linux-gnu"
 ; Function Attrs: nounwind readonly uwtable
 define i32 @fn1() #0 {
 entry:
-  %0 = load %struct.anon** @b, align 4
+  %0 = load %struct.anon*, %struct.anon** @b, align 4
   %1 = ptrtoint %struct.anon* %0 to i32
   %cmp = icmp sgt %struct.anon* %0, null
-  %2 = load %struct.anon.0** @a, align 4
+  %2 = load %struct.anon.0*, %struct.anon.0** @a, align 4
   br i1 %cmp, label %for.bodythread-pre-split, label %if.end8
 
 for.bodythread-pre-split:                         ; preds = %entry
-  %aclass = getelementptr inbounds %struct.anon.0* %2, i32 0, i32 0
-  %.pr = load i32* %aclass, align 4
+  %aclass = getelementptr inbounds %struct.anon.0, %struct.anon.0* %2, i32 0, i32 0
+  %.pr = load i32, i32* %aclass, align 4
   br label %for.body
 
 for.body:                                         ; preds = %for.bodythread-pre-split, %for.body
@@ -51,10 +51,10 @@ while.cond:                                       ; preds = %while.body
 
 while.body:                                       ; preds = %while.body.lr.ph, %while.cond
   %j.110 = phi i32 [ %j.1.ph13, %while.body.lr.ph ], [ %inc7, %while.cond ]
-  %aclass_index = getelementptr inbounds %struct.anon* %0, i32 %j.110, i32 0
-  %3 = load i32* %aclass_index, align 4
-  %aclass5 = getelementptr inbounds %struct.anon.0* %2, i32 %3, i32 0
-  %4 = load i32* %aclass5, align 4
+  %aclass_index = getelementptr inbounds %struct.anon, %struct.anon* %0, i32 %j.110, i32 0
+  %3 = load i32, i32* %aclass_index, align 4
+  %aclass5 = getelementptr inbounds %struct.anon.0, %struct.anon.0* %2, i32 %3, i32 0
+  %4 = load i32, i32* %aclass5, align 4
   %tobool = icmp eq i32 %4, 0
   %inc7 = add nsw i32 %j.110, 1
   br i1 %tobool, label %while.cond, label %if.then6
diff --git a/test/CodeGen/PowerPC/pr22711.ll b/test/CodeGen/PowerPC/pr22711.ll
new file mode 100644
index 000000000000..fb1e971d4416
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr22711.ll
@@ -0,0 +1,78 @@
+; Verify that the .toc section is aligned on an 8-byte boundary.
+
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -filetype=obj -o - | llvm-readobj --sections | FileCheck %s
+
+define void @test(i32* %a) {
+entry:
+  %a.addr = alloca i32*, align 8
+  store i32* %a, i32** %a.addr, align 8
+  %0 = load i32*,  i32** %a.addr, align 8
+  %incdec.ptr = getelementptr inbounds i32, i32* %0, i32 1
+  store i32* %incdec.ptr, i32** %a.addr, align 8
+  %1 = load i32,  i32* %0, align 4
+  switch i32 %1, label %sw.epilog [
+    i32 17, label %sw.bb
+    i32 13, label %sw.bb1
+    i32 11, label %sw.bb2
+    i32 7, label %sw.bb3
+    i32 5, label %sw.bb4
+    i32 3, label %sw.bb5
+    i32 2, label %sw.bb6
+  ]
+
+sw.bb:                                            ; preds = %entry
+  %2 = load i32*,  i32** %a.addr, align 8
+  store i32 2, i32* %2, align 4
+  br label %sw.epilog
+
+sw.bb1:                                           ; preds = %entry
+  %3 = load i32*,  i32** %a.addr, align 8
+  store i32 3, i32* %3, align 4
+  br label %sw.epilog
+
+sw.bb2:                                           ; preds = %entry
+  %4 = load i32*,  i32** %a.addr, align 8
+  store i32 5, i32* %4, align 4
+  br label %sw.epilog
+
+sw.bb3:                                           ; preds = %entry
+  %5 = load i32*,  i32** %a.addr, align 8
+  store i32 7, i32* %5, align 4
+  br label %sw.epilog
+
+sw.bb4:                                           ; preds = %entry
+  %6 = load i32*,  i32** %a.addr, align 8
+  store i32 11, i32* %6, align 4
+  br label %sw.epilog
+
+sw.bb5:                                           ; preds = %entry
+  %7 = load i32*,  i32** %a.addr, align 8
+  store i32 13, i32* %7, align 4
+  br label %sw.epilog
+
+sw.bb6:                                           ; preds = %entry
+  %8 = load i32*,  i32** %a.addr, align 8
+  store i32 17, i32* %8, align 4
+  br label %sw.epilog
+
+sw.epilog:                                        ; preds = %entry, %sw.bb6, %sw.bb5, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb
+  ret void
+}
+
+; CHECK: Name: .toc
+; CHECK: AddressAlignment: 8
+; CHECK: Name: .rela.toc
+
+; This test was generated from the following from PR22711:
+
+;void test(int *a) {
+;  switch (*a++) {
+;  case 17: *a =  2; break;
+;  case 13: *a =  3; break;
+;  case 11: *a =  5; break;
+;  case  7: *a =  7; break;
+;  case  5: *a = 11; break;
+;  case  3: *a = 13; break;
+;  case  2: *a = 17; break;
+;  }
+;}
diff --git a/test/CodeGen/PowerPC/preinc-ld-sel-crash.ll b/test/CodeGen/PowerPC/preinc-ld-sel-crash.ll
new file mode 100644
index 000000000000..cb2f035e5662
--- /dev/null
+++ b/test/CodeGen/PowerPC/preinc-ld-sel-crash.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+%t1 = type { %t2*, %t3* }
+%t2 = type <{ %t3*, i32, [4 x i8] }>
+%t3 = type { %t3* }
+
+@_ZN4Foam10SLListBase13endConstIter_E = external global %t1
+
+define void @_ZN4FoamrsIbEERNS_7IstreamES2_RNS_4ListIT_EE() #0 {
+entry:
+  switch i32 undef, label %if.else82 [
+    i32 9, label %if.then
+    i32 6, label %invoke.cont10
+    i32 1, label %invoke.cont61
+  ]
+
+if.then:                                          ; preds = %entry
+  unreachable
+
+invoke.cont10:                                    ; preds = %entry
+  unreachable
+
+invoke.cont61:                                    ; preds = %entry
+  br i1 undef, label %if.end75, label %if.then64
+
+if.then64:                                        ; preds = %invoke.cont61
+  unreachable
+
+if.end75:                                         ; preds = %invoke.cont61
+  br i1 undef, label %if.then17.i, label %if.then.i181
+
+if.then.i181:                                     ; preds = %if.end75
+  unreachable
+
+if.then17.i:                                      ; preds = %if.end75
+  %tobool.i.i.i = icmp eq i32 undef, 0
+  %0 = load i64*, i64** undef, align 8
+  %agg.tmp.sroa.3.0.copyload33.in.i = select i1 %tobool.i.i.i, i64* bitcast (%t3** getelementptr inbounds (%t1, %t1* @_ZN4Foam10SLListBase13endConstIter_E, i64 0, i32 1) to i64*), i64* %0
+  %agg.tmp.sroa.3.0.copyload33.i = load i64, i64* %agg.tmp.sroa.3.0.copyload33.in.i, align 8
+  %1 = inttoptr i64 %agg.tmp.sroa.3.0.copyload33.i to %t3*
+  %2 = load %t3*, %t3** getelementptr inbounds (%t1, %t1* @_ZN4Foam10SLListBase13endConstIter_E, i64 0, i32 1), align 8
+  %cmp.i37.i = icmp eq %t3* %1, %2
+  br i1 %cmp.i37.i, label %invoke.cont79, label %for.body.lr.ph.i
+
+; CHECK-LABEL: @_ZN4FoamrsIbEERNS_7IstreamES2_RNS_4ListIT_EE
+
+for.body.lr.ph.i:                                 ; preds = %if.then17.i
+  br label %for.body.i
+
+for.body.i:                                       ; preds = %for.body.i, %for.body.lr.ph.i
+  br i1 undef, label %invoke.cont79, label %for.body.i
+
+invoke.cont79:                                    ; preds = %for.body.i, %if.then17.i
+  unreachable
+
+if.else82:                                        ; preds = %entry
+  ret void
+}
+
+attributes #0 = { "target-cpu"="a2q" }
+
diff --git a/test/CodeGen/PowerPC/preincprep-invoke.ll b/test/CodeGen/PowerPC/preincprep-invoke.ll
new file mode 100644
index 000000000000..0e09ff1b774a
--- /dev/null
+++ b/test/CodeGen/PowerPC/preincprep-invoke.ll
@@ -0,0 +1,50 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+@.str1 = external unnamed_addr constant [1 x i8], align 1
+@.str2 = external unnamed_addr constant [39 x i8], align 1
+
+declare void @_ZN13CStdOutStreamlsEPKc()
+
+declare void @_ZN13CStdOutStream5FlushEv()
+
+declare i32 @__gxx_personality_v0(...)
+
+define void @_Z11GetPasswordP13CStdOutStreamb() {
+entry:
+  br label %for.cond.i.i
+
+for.cond.i.i:                                     ; preds = %for.cond.i.i, %entry
+  br i1 undef, label %_ZN11CStringBaseIcEC2EPKc.exit.critedge, label %for.cond.i.i
+
+_ZN11CStringBaseIcEC2EPKc.exit.critedge:          ; preds = %for.cond.i.i
+  invoke void @_ZN13CStdOutStreamlsEPKc()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %_ZN11CStringBaseIcEC2EPKc.exit.critedge
+  invoke void @_ZN13CStdOutStream5FlushEv()
+          to label %invoke.cont4 unwind label %lpad
+
+invoke.cont4:                                     ; preds = %invoke.cont
+  %call7 = invoke i8* @getpass()
+          to label %for.cond.i.i30 unwind label %lpad
+
+; CHECK-LABEL: @_Z11GetPasswordP13CStdOutStreamb
+; CHECK: addi {{[0-9]+}}, 3, -1
+
+for.cond.i.i30:                                   ; preds = %for.cond.i.i30, %invoke.cont4
+  %indvars.iv.i.i26 = phi i64 [ %indvars.iv.next.i.i29, %for.cond.i.i30 ], [ 0, %invoke.cont4 ]
+  %arrayidx.i.i27 = getelementptr inbounds i8, i8* %call7, i64 %indvars.iv.i.i26
+  %0 = load i8, i8* %arrayidx.i.i27, align 1
+  %indvars.iv.next.i.i29 = add nuw nsw i64 %indvars.iv.i.i26, 1
+  br label %for.cond.i.i30
+
+lpad:                                             ; preds = %invoke.cont4, %invoke.cont, %_ZN11CStringBaseIcEC2EPKc.exit.critedge
+  %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  resume { i8*, i32 } undef
+}
+
+declare i8* @getpass()
+
diff --git a/test/CodeGen/PowerPC/private.ll b/test/CodeGen/PowerPC/private.ll
index 633fa651037f..4665fd246f33 100644
--- a/test/CodeGen/PowerPC/private.ll
+++ b/test/CodeGen/PowerPC/private.ll
@@ -19,7 +19,7 @@ define i32 @bar() nounwind {
 
 ; LINUX: lis{{.*}}.Lbaz
 ; OSX:  lis{{.*}}l_baz
-	%1 = load i32* @baz, align 4
+	%1 = load i32, i32* @baz, align 4
         ret i32 %1
 }
 
diff --git a/test/CodeGen/PowerPC/pwr7-gt-nop.ll b/test/CodeGen/PowerPC/pwr7-gt-nop.ll
index 8c8545d60df7..70f6dad362bf 100644
--- a/test/CodeGen/PowerPC/pwr7-gt-nop.ll
+++ b/test/CodeGen/PowerPC/pwr7-gt-nop.ll
@@ -8,11 +8,11 @@ define void @foo(float* nocapture %a, float* nocapture %b, float* nocapture read
 ; CHECK-LABEL: @foo
 
 entry:
-  %0 = load float* %b, align 4
+  %0 = load float, float* %b, align 4
   store float %0, float* %a, align 4
-  %1 = load float* %c, align 4
+  %1 = load float, float* %c, align 4
   store float %1, float* %b, align 4
-  %2 = load float* %a, align 4
+  %2 = load float, float* %a, align 4
   store float %2, float* %d, align 4
   ret void
 
diff --git a/test/CodeGen/PowerPC/qpx-bv-sint.ll b/test/CodeGen/PowerPC/qpx-bv-sint.ll
new file mode 100644
index 000000000000..0bc14ed4351a
--- /dev/null
+++ b/test/CodeGen/PowerPC/qpx-bv-sint.ll
@@ -0,0 +1,33 @@
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-bgq-linux"
+; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s
+
+define void @s452() nounwind {
+entry:
+  br label %for.body4
+
+for.body4:                                        ; preds = %for.body4, %entry
+  %conv.4 = sitofp i32 undef to double
+  %conv.5 = sitofp i32 undef to double
+  %mul.4.v.i0.1 = insertelement <2 x double> undef, double %conv.4, i32 0
+  %mul.4.v.i0.2 = insertelement <2 x double> %mul.4.v.i0.1, double %conv.5, i32 1
+  %mul.4 = fmul <2 x double> %mul.4.v.i0.2, undef
+  %add7.4 = fadd <2 x double> undef, %mul.4
+  store <2 x double> %add7.4, <2 x double>* undef, align 16
+  br i1 undef, label %for.end, label %for.body4
+
+for.end:                                          ; preds = %for.body4
+  unreachable
+; CHECK-LABEL: @s452
+; CHECK: lfiwax [[REG1:[0-9]+]],
+; CHECK: fcfid [[REG2:[0-9]+]], [[REG1]]
+; FIXME: We could 'promote' this to a vector earlier and remove this splat.
+; CHECK: qvesplati {{[0-9]+}}, [[REG2]], 0
+; CHECK: qvfmul
+; CHECK: qvfadd
+; CHECK: qvesplati {{[0-9]+}},
+; FIXME: We can use qvstfcdx here instead of two stores.
+; CHECK: stfd
+; CHECK: stfd
+}
+
diff --git a/test/CodeGen/PowerPC/qpx-bv.ll b/test/CodeGen/PowerPC/qpx-bv.ll
new file mode 100644
index 000000000000..ae181de383b5
--- /dev/null
+++ b/test/CodeGen/PowerPC/qpx-bv.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -mcpu=a2q | FileCheck %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+define <4 x double> @foo(double %f1, double %f2, double %f3, double %f4) {
+  %v1 = insertelement <4 x double> undef, double %f1, i32 0
+  %v2 = insertelement <4 x double> %v1,   double %f2, i32 1
+  %v3 = insertelement <4 x double> %v2,   double %f3, i32 2
+  %v4 = insertelement <4 x double> %v3,   double %f4, i32 3
+  ret <4 x double> %v4
+
+; CHECK-LABEL: @foo
+; CHECK: qvgpci [[REG1:[0-9]+]], 275
+; CHECK-DAG: qvgpci [[REG2:[0-9]+]], 101
+; CHECK-DAG: qvfperm [[REG3:[0-9]+]], 3, 4, [[REG1]]
+; CHECK-DAG: qvfperm [[REG4:[0-9]+]], 1, 2, [[REG1]]
+; CHECK-DAG: qvfperm 1, [[REG4]], [[REG3]], [[REG2]]
+; CHECK: blr
+}
+
+define <4 x float> @goo(float %f1, float %f2, float %f3, float %f4) {
+  %v1 = insertelement <4 x float> undef, float %f1, i32 0
+  %v2 = insertelement <4 x float> %v1,   float %f2, i32 1
+  %v3 = insertelement <4 x float> %v2,   float %f3, i32 2
+  %v4 = insertelement <4 x float> %v3,   float %f4, i32 3
+  ret <4 x float> %v4
+
+; CHECK-LABEL: @goo
+; CHECK: qvgpci [[REG1:[0-9]+]], 275
+; CHECK-DAG: qvgpci [[REG2:[0-9]+]], 101
+; CHECK-DAG: qvfperm [[REG3:[0-9]+]], 3, 4, [[REG1]]
+; CHECK-DAG: qvfperm [[REG4:[0-9]+]], 1, 2, [[REG1]]
+; CHECK-DAG: qvfperm 1, [[REG4]], [[REG3]], [[REG2]]
+; CHECK: blr
+}
+
diff --git a/test/CodeGen/PowerPC/qpx-func-clobber.ll b/test/CodeGen/PowerPC/qpx-func-clobber.ll
new file mode 100644
index 000000000000..511fa3827b0c
--- /dev/null
+++ b/test/CodeGen/PowerPC/qpx-func-clobber.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s
+target triple = "powerpc64-bgq-linux"
+
+declare <4 x double> @foo(<4 x double> %p)
+
+define <4 x double> @bar(<4 x double> %p, <4 x double> %q) {
+entry:
+  %v = call <4 x double> @foo(<4 x double> %p)
+  %w = call <4 x double> @foo(<4 x double> %q)
+  %x = fadd <4 x double> %v, %w
+  ret <4 x double> %x
+
+; CHECK-LABEL: @bar
+; CHECK: qvstfdx 2,
+; CHECK: bl foo
+; CHECK: qvstfdx 1,
+; CHECK: qvlfdx 1,
+; CHECK: bl foo
+; CHECK: qvlfdx [[REG:[0-9]+]],
+; CHECK: qvfadd 1, [[REG]], 1
+}
+
diff --git a/test/CodeGen/PowerPC/qpx-load.ll b/test/CodeGen/PowerPC/qpx-load.ll
new file mode 100644
index 000000000000..7637c43850cc
--- /dev/null
+++ b/test/CodeGen/PowerPC/qpx-load.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s
+target triple = "powerpc64-bgq-linux"
+
+define <4 x double> @foo(<4 x double>* %p) {
+entry:
+  %v = load <4 x double>, <4 x double>* %p, align 8
+  ret <4 x double> %v
+}
+
+; CHECK: @foo
+; CHECK-DAG: li [[REG1:[0-9]+]], 31
+; CHECK-DAG: qvlfdx [[REG4:[0-9]+]], 0, 3
+; CHECK-DAG: qvlfdx [[REG2:[0-9]+]], 3, [[REG1]]
+; CHECK-DAG: qvlpcldx [[REG3:[0-9]+]], 0, 3
+; CHECK-DAG: qvfperm 1, [[REG4]], [[REG2]], [[REG3]]
+; CHECK: blr
+
+define <4 x double> @bar(<4 x double>* %p) {
+entry:
+  %v = load <4 x double>, <4 x double>* %p, align 32
+  ret <4 x double> %v
+}
+
+; CHECK: @bar
+; CHECK: qvlfdx
+
diff --git a/test/CodeGen/PowerPC/qpx-recipest.ll b/test/CodeGen/PowerPC/qpx-recipest.ll
new file mode 100644
index 000000000000..0e01358e5791
--- /dev/null
+++ b/test/CodeGen/PowerPC/qpx-recipest.ll
@@ -0,0 +1,194 @@
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2q -enable-unsafe-fp-math | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2q | FileCheck -check-prefix=CHECK-SAFE %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+declare <4 x double> @llvm.sqrt.v4f64(<4 x double>)
+declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)
+
+define <4 x double> @foo(<4 x double> %a, <4 x double> %b) nounwind {
+entry:
+  %x = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %b)
+  %r = fdiv <4 x double> %a, %x
+  ret <4 x double> %r
+
+; CHECK-LABEL: @foo
+; CHECK: qvfrsqrte
+; CHECK: qvfmul
+; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
+;        an qvfmadd instead of a qvfnmsub
+; CHECK: qvfmadd
+; CHECK: qvfmadd
+; CHECK: qvfmul
+; CHECK: qvfmul
+; CHECK: qvfmadd
+; CHECK: qvfmul
+; CHECK: qvfmul
+; CHECK: blr
+
+; CHECK-SAFE-LABEL: @foo
+; CHECK-SAFE: fsqrt
+; CHECK-SAFE: fdiv
+; CHECK-SAFE: blr
+}
+
+define <4 x double> @foof(<4 x double> %a, <4 x float> %b) nounwind {
+entry:
+  %x = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
+  %y = fpext <4 x float> %x to <4 x double>
+  %r = fdiv <4 x double> %a, %y
+  ret <4 x double> %r
+
+; CHECK-LABEL: @foof
+; CHECK: qvfrsqrtes
+; CHECK: qvfmuls
+; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
+;        an qvfmadd instead of a qvfnmsubs
+; CHECK: qvfmadds
+; CHECK: qvfmadds
+; CHECK: qvfmuls
+; CHECK: qvfmul
+; CHECK: blr
+
+; CHECK-SAFE-LABEL: @foof
+; CHECK-SAFE: fsqrts
+; CHECK-SAFE: fdiv
+; CHECK-SAFE: blr
+}
+
+define <4 x float> @food(<4 x float> %a, <4 x double> %b) nounwind {
+entry:
+  %x = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %b)
+  %y = fptrunc <4 x double> %x to <4 x float>
+  %r = fdiv <4 x float> %a, %y
+  ret <4 x float> %r
+
+; CHECK-LABEL: @food
+; CHECK: qvfrsqrte
+; CHECK: qvfmul
+; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
+;        an qvfmadd instead of a qvfnmsub
+; CHECK: qvfmadd
+; CHECK: qvfmadd
+; CHECK: qvfmul
+; CHECK: qvfmul
+; CHECK: qvfmadd
+; CHECK: qvfmul
+; CHECK: qvfrsp
+; CHECK: qvfmuls
+; CHECK: blr
+
+; CHECK-SAFE-LABEL: @food
+; CHECK-SAFE: fsqrt
+; CHECK-SAFE: fdivs
+; CHECK-SAFE: blr
+}
+
+define <4 x float> @goo(<4 x float> %a, <4 x float> %b) nounwind {
+entry:
+  %x = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
+  %r = fdiv <4 x float> %a, %x
+  ret <4 x float> %r
+
+; CHECK-LABEL: @goo
+; CHECK: qvfrsqrtes
+; CHECK: qvfmuls
+; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
+;        an qvfmadd instead of a qvfnmsubs
+; CHECK: qvfmadds
+; CHECK: qvfmadds
+; CHECK: qvfmuls
+; CHECK: qvfmuls
+; CHECK: blr
+
+; CHECK-SAFE-LABEL: @goo
+; CHECK-SAFE: fsqrts
+; CHECK-SAFE: fdivs
+; CHECK-SAFE: blr
+}
+
+define <4 x double> @foo2(<4 x double> %a, <4 x double> %b) nounwind {
+entry:
+  %r = fdiv <4 x double> %a, %b
+  ret <4 x double> %r
+
+; CHECK-LABEL: @foo2
+; CHECK: qvfre
+; CHECK: qvfnmsub
+; CHECK: qvfmadd
+; CHECK: qvfnmsub
+; CHECK: qvfmadd
+; CHECK: qvfmul
+; CHECK: blr
+
+; CHECK-SAFE-LABEL: @foo2
+; CHECK-SAFE: fdiv
+; CHECK-SAFE: blr
+}
+
+define <4 x float> @goo2(<4 x float> %a, <4 x float> %b) nounwind {
+entry:
+  %r = fdiv <4 x float> %a, %b
+  ret <4 x float> %r
+
+; CHECK-LABEL: @goo2
+; CHECK: qvfres
+; CHECK: qvfnmsubs
+; CHECK: qvfmadds
+; CHECK: qvfmuls
+; CHECK: blr
+
+; CHECK-SAFE-LABEL: @goo2
+; CHECK-SAFE: fdivs
+; CHECK-SAFE: blr
+}
+
+define <4 x double> @foo3(<4 x double> %a) nounwind {
+entry:
+  %r = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %a)
+  ret <4 x double> %r
+
+; CHECK-LABEL: @foo3
+; CHECK: qvfrsqrte
+; CHECK: qvfmul
+; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
+;        an qvfmadd instead of a qvfnmsub
+; CHECK-DAG: qvfmadd
+; CHECK-DAG: qvfcmpeq
+; CHECK-DAG: qvfmadd
+; CHECK-DAG: qvfmul
+; CHECK-DAG: qvfmul
+; CHECK-DAG: qvfmadd
+; CHECK-DAG: qvfmul
+; CHECK-DAG: qvfmul
+; CHECK: qvfsel
+; CHECK: blr
+
+; CHECK-SAFE-LABEL: @foo3
+; CHECK-SAFE: fsqrt
+; CHECK-SAFE: blr
+}
+
+define <4 x float> @goo3(<4 x float> %a) nounwind {
+entry:
+  %r = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
+  ret <4 x float> %r
+
+; CHECK-LABEL: @goo3
+; CHECK: qvfrsqrtes
+; CHECK: qvfmuls
+; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
+;        an qvfmadds instead of a qvfnmsubs
+; CHECK-DAG: qvfmadds
+; CHECK-DAG: qvfcmpeq
+; CHECK-DAG: qvfmadds
+; CHECK-DAG: qvfmuls
+; CHECK-DAG: qvfmuls
+; CHECK: qvfsel
+; CHECK: blr
+
+; CHECK-SAFE-LABEL: @goo3
+; CHECK-SAFE: fsqrts
+; CHECK-SAFE: blr
+}
+
diff --git a/test/CodeGen/PowerPC/qpx-rounding-ops.ll b/test/CodeGen/PowerPC/qpx-rounding-ops.ll
new file mode 100644
index 000000000000..6fdd8e6a7147
--- /dev/null
+++ b/test/CodeGen/PowerPC/qpx-rounding-ops.ll
@@ -0,0 +1,109 @@
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2q | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2q -enable-unsafe-fp-math | FileCheck -check-prefix=CHECK-FM %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define <4 x float> @test1(<4 x float> %x) nounwind  {
+  %call = tail call <4 x float> @llvm.floor.v4f32(<4 x float> %x) nounwind readnone
+  ret <4 x float> %call
+
+; CHECK: test1:
+; CHECK: qvfrim 1, 1
+
+; CHECK-FM: test1:
+; CHECK-FM: qvfrim 1, 1
+}
+
+declare <4 x float> @llvm.floor.v4f32(<4 x float>) nounwind readnone
+
+define <4 x double> @test2(<4 x double> %x) nounwind  {
+  %call = tail call <4 x double> @llvm.floor.v4f64(<4 x double> %x) nounwind readnone
+  ret <4 x double> %call
+
+; CHECK: test2:
+; CHECK: qvfrim 1, 1
+
+; CHECK-FM: test2:
+; CHECK-FM: qvfrim 1, 1
+}
+
+declare <4 x double> @llvm.floor.v4f64(<4 x double>) nounwind readnone
+
+define <4 x float> @test3(<4 x float> %x) nounwind  {
+  %call = tail call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %x) nounwind readnone
+  ret <4 x float> %call
+
+; CHECK: test3:
+; CHECK-NOT: qvfrin
+
+; CHECK-FM: test3:
+; CHECK-FM-NOT: qvfrin
+}
+
+declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) nounwind readnone
+
+define <4 x double> @test4(<4 x double> %x) nounwind  {
+  %call = tail call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %x) nounwind readnone
+  ret <4 x double> %call
+
+; CHECK: test4:
+; CHECK-NOT: qvfrin
+
+; CHECK-FM: test4:
+; CHECK-FM-NOT: qvfrin
+}
+
+declare <4 x double> @llvm.nearbyint.v4f64(<4 x double>) nounwind readnone
+
+define <4 x float> @test5(<4 x float> %x) nounwind  {
+  %call = tail call <4 x float> @llvm.ceil.v4f32(<4 x float> %x) nounwind readnone
+  ret <4 x float> %call
+
+; CHECK: test5:
+; CHECK: qvfrip 1, 1
+
+; CHECK-FM: test5:
+; CHECK-FM: qvfrip 1, 1
+}
+
+declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone
+
+define <4 x double> @test6(<4 x double> %x) nounwind  {
+  %call = tail call <4 x double> @llvm.ceil.v4f64(<4 x double> %x) nounwind readnone
+  ret <4 x double> %call
+
+; CHECK: test6:
+; CHECK: qvfrip 1, 1
+
+; CHECK-FM: test6:
+; CHECK-FM: qvfrip 1, 1
+}
+
+declare <4 x double> @llvm.ceil.v4f64(<4 x double>) nounwind readnone
+
+define <4 x float> @test9(<4 x float> %x) nounwind  {
+  %call = tail call <4 x float> @llvm.trunc.v4f32(<4 x float> %x) nounwind readnone
+  ret <4 x float> %call
+
+; CHECK: test9:
+; CHECK: qvfriz 1, 1
+
+; CHECK-FM: test9:
+; CHECK-FM: qvfriz 1, 1
+}
+
+declare <4 x float> @llvm.trunc.v4f32(<4 x float>) nounwind readnone
+
+define <4 x double> @test10(<4 x double> %x) nounwind  {
+  %call = tail call <4 x double> @llvm.trunc.v4f64(<4 x double> %x) nounwind readnone
+  ret <4 x double> %call
+
+; CHECK: test10:
+; CHECK: qvfriz 1, 1
+
+; CHECK-FM: test10:
+; CHECK-FM: qvfriz 1, 1
+}
+
+declare <4 x double> @llvm.trunc.v4f64(<4 x double>) nounwind readnone
+
diff --git a/test/CodeGen/PowerPC/qpx-s-load.ll b/test/CodeGen/PowerPC/qpx-s-load.ll
new file mode 100644
index 000000000000..db147126c1ec
--- /dev/null
+++ b/test/CodeGen/PowerPC/qpx-s-load.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s
+target triple = "powerpc64-bgq-linux"
+
+define <4 x float> @foo(<4 x float>* %p) {
+entry:
+  %v = load <4 x float>, <4 x float>* %p, align 4
+  ret <4 x float> %v
+}
+
+; CHECK: @foo
+; CHECK-DAG: li [[REG1:[0-9]+]], 15
+; CHECK-DAG: qvlfsx [[REG4:[0-9]+]], 0, 3
+; CHECK-DAG: qvlfsx [[REG2:[0-9]+]], 3, [[REG1]]
+; CHECK-DAG: qvlpclsx [[REG3:[0-9]+]], 0, 3
+; CHECK-DAG: qvfperm 1, [[REG4]], [[REG2]], [[REG3]]
+; CHECK: blr
+
+define <4 x float> @bar(<4 x float>* %p) {
+entry:
+  %v = load <4 x float>, <4 x float>* %p, align 16
+  ret <4 x float> %v
+}
+
+; CHECK: @bar
+; CHECK: qvlfsx
+
diff --git a/test/CodeGen/PowerPC/qpx-s-sel.ll b/test/CodeGen/PowerPC/qpx-s-sel.ll
new file mode 100644
index 000000000000..09a615c4597d
--- /dev/null
+++ b/test/CodeGen/PowerPC/qpx-s-sel.ll
@@ -0,0 +1,144 @@
+; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s
+target triple = "powerpc64-bgq-linux"
+
+@Q = constant <4 x i1> <i1 0, i1 undef, i1 1, i1 1>, align 16
+@R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16
+
+define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x i1> %c) nounwind readnone {
+entry:
+  %r = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+  ret <4 x float> %r
+
+; CHECK-LABEL: @test1
+; CHECK: qvfsel 1, 3, 1, 2
+; CHECK: blr
+}
+
+define <4 x float> @test2(<4 x float> %a, <4 x float> %b, i1 %c1, i1 %c2, i1 %c3, i1 %c4) nounwind readnone {
+entry:
+  %v = insertelement <4 x i1> undef, i1 %c1, i32 0
+  %v2 = insertelement <4 x i1> %v, i1 %c2, i32 1
+  %v3 = insertelement <4 x i1> %v2, i1 %c3, i32 2
+  %v4 = insertelement <4 x i1> %v3, i1 %c4, i32 3
+  %r = select <4 x i1> %v4, <4 x float> %a, <4 x float> %b
+  ret <4 x float> %r
+
+; CHECK-LABEL: @test2
+; CHECK: stw
+; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]],
+; CHECK-DAG: qvlfdx [[REG2:[0-9]+]],
+; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]]
+; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
+; CHECK: qvfsel 1, [[REG4]], 1, 2
+; CHECK: blr
+}
+
+define <4 x i1> @test3(<4 x i1> %a) nounwind readnone {
+entry:
+  %v = and <4 x i1> %a, <i1 0, i1 undef, i1 1, i1 1>
+  ret <4 x i1> %v
+
+; CHECK-LABEL: @test3
+; CHECK: qvlfsx [[REG:[0-9]+]],
+; qvflogical 1, 1, [[REG]], 1
+; blr
+}
+
+define <4 x i1> @test4(<4 x i1> %a) nounwind {
+entry:
+  %q = load <4 x i1>, <4 x i1>* @Q, align 16
+  %v = and <4 x i1> %a, %q
+  ret <4 x i1> %v
+
+; CHECK-LABEL: @test4
+; CHECK-DAG: lbz
+; CHECK-DAG: qvlfdx [[REG1:[0-9]+]],
+; CHECK-DAG: stw
+; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
+; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
+; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]]
+; CHECK: qvflogical 1, 1, [[REG4]], 1
+; CHECK: blr
+}
+
+define void @test5(<4 x i1> %a) nounwind {
+entry:
+  store <4 x i1> %a, <4 x i1>* @R
+  ret void
+
+; CHECK-LABEL: @test5
+; CHECK: qvlfdx [[REG1:[0-9]+]],
+; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
+; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
+; CHECK: qvstfiwx [[REG3]],
+; CHECK: lwz
+; CHECK: stb
+; CHECK: blr
+}
+
+define i1 @test6(<4 x i1> %a) nounwind {
+entry:
+  %r = extractelement <4 x i1> %a, i32 2
+  ret i1 %r
+
+; CHECK-LABEL: @test6
+; CHECK: qvlfdx [[REG1:[0-9]+]],
+; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
+; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
+; CHECK: qvstfiwx [[REG3]],
+; CHECK: lwz
+; CHECK: blr
+}
+
+define i1 @test7(<4 x i1> %a) nounwind {
+entry:
+  %r = extractelement <4 x i1> %a, i32 2
+  %s = extractelement <4 x i1> %a, i32 3
+  %q = and i1 %r, %s
+  ret i1 %q
+
+; CHECK-LABEL: @test7
+; CHECK: qvlfdx [[REG1:[0-9]+]],
+; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
+; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
+; CHECK: qvstfiwx [[REG3]],
+; CHECK-DAG: lwz [[REG4:[0-9]+]],
+; FIXME: We're storing the vector twice, and that's silly.
+; CHECK-DAG: qvstfiwx [[REG3]],
+; CHECK: lwz [[REG5:[0-9]+]],
+; CHECK: and 3,
+; CHECK: blr
+}
+
+define i1 @test8(<3 x i1> %a) nounwind {
+entry:
+  %r = extractelement <3 x i1> %a, i32 2
+  ret i1 %r
+
+; CHECK-LABEL: @test8
+; CHECK: qvlfdx [[REG1:[0-9]+]],
+; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
+; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
+; CHECK: qvstfiwx [[REG3]],
+; CHECK: lwz
+; CHECK: blr
+}
+
+define <3 x float> @test9(<3 x float> %a, <3 x float> %b, i1 %c1, i1 %c2, i1 %c3) nounwind readnone {
+entry:
+  %v = insertelement <3 x i1> undef, i1 %c1, i32 0
+  %v2 = insertelement <3 x i1> %v, i1 %c2, i32 1
+  %v3 = insertelement <3 x i1> %v2, i1 %c3, i32 2
+  %r = select <3 x i1> %v3, <3 x float> %a, <3 x float> %b
+  ret <3 x float> %r
+
+; CHECK-LABEL: @test9
+; CHECK: stw
+; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]],
+; CHECK-DAG: qvlfdx [[REG2:[0-9]+]],
+; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]]
+; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
+; CHECK: qvfsel 1, [[REG4]], 1, 2
+; CHECK: blr
+}
+
diff --git a/test/CodeGen/PowerPC/qpx-s-store.ll b/test/CodeGen/PowerPC/qpx-s-store.ll
new file mode 100644
index 000000000000..0bd6201f767c
--- /dev/null
+++ b/test/CodeGen/PowerPC/qpx-s-store.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s
+target triple = "powerpc64-bgq-linux"
+
+define void @foo(<4 x float> %v, <4 x float>* %p) {
+entry:
+  store <4 x float> %v, <4 x float>* %p, align 4
+  ret void
+}
+
+; CHECK: @foo
+; CHECK: stfs
+; CHECK: stfs
+; CHECK: stfs
+; CHECK: stfs
+; CHECK: blr
+
+define void @bar(<4 x float> %v, <4 x float>* %p) {
+entry:
+  store <4 x float> %v, <4 x float>* %p, align 16
+  ret void
+}
+
+; CHECK: @bar
+; CHECK: qvstfsx
+
diff --git a/test/CodeGen/PowerPC/qpx-sel.ll b/test/CodeGen/PowerPC/qpx-sel.ll
new file mode 100644
index 000000000000..a375e6effbae
--- /dev/null
+++ b/test/CodeGen/PowerPC/qpx-sel.ll
@@ -0,0 +1,152 @@
+; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s
+target triple = "powerpc64-bgq-linux"
+
+@Q = constant <4 x i1> <i1 0, i1 undef, i1 1, i1 1>, align 16
+@R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16
+
+define <4 x double> @test1(<4 x double> %a, <4 x double> %b, <4 x i1> %c) nounwind readnone {
+entry:
+  %r = select <4 x i1> %c, <4 x double> %a, <4 x double> %b
+  ret <4 x double> %r
+
+; CHECK-LABEL: @test1
+; CHECK: qvfsel 1, 3, 1, 2
+; CHECK: blr
+}
+
+define <4 x double> @test2(<4 x double> %a, <4 x double> %b, i1 %c1, i1 %c2, i1 %c3, i1 %c4) nounwind readnone {
+entry:
+  %v = insertelement <4 x i1> undef, i1 %c1, i32 0
+  %v2 = insertelement <4 x i1> %v, i1 %c2, i32 1
+  %v3 = insertelement <4 x i1> %v2, i1 %c3, i32 2
+  %v4 = insertelement <4 x i1> %v3, i1 %c4, i32 3
+  %r = select <4 x i1> %v4, <4 x double> %a, <4 x double> %b
+  ret <4 x double> %r
+
+; CHECK-LABEL: @test2
+
+; FIXME: This load/store sequence is unnecessary.
+; CHECK-DAG: lbz
+; CHECK-DAG: stw
+
+; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]],
+; CHECK-DAG: qvlfdx [[REG2:[0-9]+]],
+; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]]
+; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
+; CHECK: qvfsel 1, [[REG4]], 1, 2
+; CHECK: blr
+}
+
+define <4 x i1> @test3(<4 x i1> %a) nounwind readnone {
+entry:
+  %v = and <4 x i1> %a, <i1 0, i1 undef, i1 1, i1 1>
+  ret <4 x i1> %v
+
+; CHECK-LABEL: @test3
+; CHECK: qvlfsx [[REG:[0-9]+]],
+; qvflogical 1, 1, [[REG]], 1
+; blr
+}
+
+define <4 x i1> @test4(<4 x i1> %a) nounwind {
+entry:
+  %q = load <4 x i1>, <4 x i1>* @Q, align 16
+  %v = and <4 x i1> %a, %q
+  ret <4 x i1> %v
+
+; CHECK-LABEL: @test4
+; CHECK-DAG: lbz
+; CHECK-DAG: qvlfdx [[REG1:[0-9]+]],
+; CHECK-DAG: stw
+; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
+; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
+; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]]
+; CHECK: qvflogical 1, 1, [[REG4]], 1
+; CHECK: blr
+}
+
+define void @test5(<4 x i1> %a) nounwind {
+entry:
+  store <4 x i1> %a, <4 x i1>* @R
+  ret void
+
+; CHECK-LABEL: @test5
+; CHECK: qvlfdx [[REG1:[0-9]+]],
+; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
+; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
+; CHECK: qvstfiwx [[REG3]],
+; CHECK: lwz
+; CHECK: stb
+; CHECK: blr
+}
+
+define i1 @test6(<4 x i1> %a) nounwind {
+entry:
+  %r = extractelement <4 x i1> %a, i32 2
+  ret i1 %r
+
+; CHECK-LABEL: @test6
+; CHECK: qvlfdx [[REG1:[0-9]+]],
+; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
+; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
+; CHECK: qvstfiwx [[REG3]],
+; CHECK: lwz
+; CHECK: blr
+}
+
+define i1 @test7(<4 x i1> %a) nounwind {
+entry:
+  %r = extractelement <4 x i1> %a, i32 2
+  %s = extractelement <4 x i1> %a, i32 3
+  %q = and i1 %r, %s
+  ret i1 %q
+
+; CHECK-LABEL: @test7
+; CHECK: qvlfdx [[REG1:[0-9]+]],
+; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
+; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
+; CHECK: qvstfiwx [[REG3]],
+; CHECK-DAG: lwz [[REG4:[0-9]+]],
+; FIXME: We're storing the vector twice, and that's silly.
+; CHECK-DAG: qvstfiwx [[REG3]],
+; CHECK-DAG: lwz [[REG5:[0-9]+]],
+; CHECK: and 3,
+; CHECK: blr
+}
+
+define i1 @test8(<3 x i1> %a) nounwind {
+entry:
+  %r = extractelement <3 x i1> %a, i32 2
+  ret i1 %r
+
+; CHECK-LABEL: @test8
+; CHECK: qvlfdx [[REG1:[0-9]+]],
+; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
+; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
+; CHECK: qvstfiwx [[REG3]],
+; CHECK: lwz
+; CHECK: blr
+}
+
+define <3 x double> @test9(<3 x double> %a, <3 x double> %b, i1 %c1, i1 %c2, i1 %c3) nounwind readnone {
+entry:
+  %v = insertelement <3 x i1> undef, i1 %c1, i32 0
+  %v2 = insertelement <3 x i1> %v, i1 %c2, i32 1
+  %v3 = insertelement <3 x i1> %v2, i1 %c3, i32 2
+  %r = select <3 x i1> %v3, <3 x double> %a, <3 x double> %b
+  ret <3 x double> %r
+
+; CHECK-LABEL: @test9
+
+; FIXME: This load/store sequence is unnecessary.
+; CHECK-DAG: lbz
+; CHECK-DAG: stw
+
+; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]],
+; CHECK-DAG: qvlfdx [[REG2:[0-9]+]],
+; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]]
+; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
+; CHECK: qvfsel 1, [[REG4]], 1, 2
+; CHECK: blr
+}
+
diff --git a/test/CodeGen/PowerPC/qpx-split-vsetcc.ll b/test/CodeGen/PowerPC/qpx-split-vsetcc.ll
new file mode 100644
index 000000000000..c8cef0faeaa4
--- /dev/null
+++ b/test/CodeGen/PowerPC/qpx-split-vsetcc.ll
@@ -0,0 +1,40 @@
+; RUN: llc -mcpu=a2q < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+; Function Attrs: nounwind
+define void @gsl_sf_legendre_Pl_deriv_array() #0 {
+entry:
+  br i1 undef, label %do.body.i, label %if.else.i
+
+do.body.i:                                        ; preds = %entry
+  unreachable
+
+if.else.i:                                        ; preds = %entry
+  br i1 undef, label %return, label %for.body46.lr.ph
+
+for.body46.lr.ph:                                 ; preds = %if.else.i
+  br label %vector.body198
+
+vector.body198:                                   ; preds = %vector.body198, %for.body46.lr.ph
+  %0 = icmp ne <4 x i32> undef, zeroinitializer
+  %1 = select <4 x i1> %0, <4 x double> <double 5.000000e-01, double 5.000000e-01, double 5.000000e-01, double 5.000000e-01>, <4 x double> <double -5.000000e-01, double -5.000000e-01, double -5.000000e-01, double -5.000000e-01>
+  %2 = fmul <4 x double> undef, %1
+  %3 = fmul <4 x double> undef, %2
+  %4 = fmul <4 x double> %3, undef
+  store <4 x double> %4, <4 x double>* undef, align 8
+  br label %vector.body198
+
+; CHECK-LABEL: @gsl_sf_legendre_Pl_deriv_array
+; CHECK: qvlfiwzx
+; CHECK: qvfcfidu
+; CHECK: qvfcmpeq
+; CHECK: qvfsel
+; CHECK: qvfmul
+
+return:                                           ; preds = %if.else.i
+  ret void
+}
+
+attributes #0 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/qpx-store.ll b/test/CodeGen/PowerPC/qpx-store.ll
new file mode 100644
index 000000000000..2579d2c681c9
--- /dev/null
+++ b/test/CodeGen/PowerPC/qpx-store.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s
+target triple = "powerpc64-bgq-linux"
+
+define void @foo(<4 x double> %v, <4 x double>* %p) {
+entry:
+  store <4 x double> %v, <4 x double>* %p, align 8
+  ret void
+}
+
+; CHECK: @foo
+; CHECK: stfd
+; CHECK: stfd
+; CHECK: stfd
+; CHECK: stfd
+; CHECK: blr
+
+define void @bar(<4 x double> %v, <4 x double>* %p) {
+entry:
+  store <4 x double> %v, <4 x double>* %p, align 32
+  ret void
+}
+
+; CHECK: @bar
+; CHECK: qvstfdx
+
diff --git a/test/CodeGen/PowerPC/qpx-unalperm.ll b/test/CodeGen/PowerPC/qpx-unalperm.ll
new file mode 100644
index 000000000000..51b340c5835c
--- /dev/null
+++ b/test/CodeGen/PowerPC/qpx-unalperm.ll
@@ -0,0 +1,64 @@
+; RUN: llc < %s -mcpu=a2q | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+define <4 x double> @foo(<4 x double>* %a) {
+entry:
+  %r = load <4 x double>, <4 x double>* %a, align 32
+  ret <4 x double> %r
+; CHECK: qvlfdx
+; CHECK: blr
+}
+
+define <4 x double> @bar(<4 x double>* %a) {
+entry:
+  %r = load <4 x double>, <4 x double>* %a, align 8
+  %b = getelementptr <4 x double>, <4 x double>* %a, i32 16
+  %s = load <4 x double>, <4 x double>* %b, align 32
+  %t = fadd <4 x double> %r, %s
+  ret <4 x double> %t
+; CHECK: qvlpcldx
+; CHECK: qvlfdx
+; CHECK: qvfperm
+; CHECK: blr
+}
+
+define <4 x double> @bar1(<4 x double>* %a) {
+entry:
+  %r = load <4 x double>, <4 x double>* %a, align 8
+  %b = getelementptr <4 x double>, <4 x double>* %a, i32 16
+  %s = load <4 x double>, <4 x double>* %b, align 8
+  %t = fadd <4 x double> %r, %s
+  ret <4 x double> %t
+}
+
+define <4 x double> @bar2(<4 x double>* %a) {
+entry:
+  %r = load <4 x double>, <4 x double>* %a, align 8
+  %b = getelementptr <4 x double>, <4 x double>* %a, i32 1
+  %s = load <4 x double>, <4 x double>* %b, align 32
+  %t = fadd <4 x double> %r, %s
+  ret <4 x double> %t
+}
+
+define <4 x double> @bar3(<4 x double>* %a) {
+entry:
+  %r = load <4 x double>, <4 x double>* %a, align 8
+  %b = getelementptr <4 x double>, <4 x double>* %a, i32 1
+  %s = load <4 x double>, <4 x double>* %b, align 8
+  %t = fadd <4 x double> %r, %s
+  ret <4 x double> %t
+}
+
+define <4 x double> @bar4(<4 x double>* %a) {
+entry:
+  %r = load <4 x double>, <4 x double>* %a, align 8
+  %b = getelementptr <4 x double>, <4 x double>* %a, i32 1
+  %s = load <4 x double>, <4 x double>* %b, align 8
+  %c = getelementptr <4 x double>, <4 x double>* %b, i32 1
+  %t = load <4 x double>, <4 x double>* %c, align 8
+  %u = fadd <4 x double> %r, %s
+  %v = fadd <4 x double> %u, %t
+  ret <4 x double> %v
+}
+
diff --git a/test/CodeGen/PowerPC/quadint-return.ll b/test/CodeGen/PowerPC/quadint-return.ll
index 03499915e78e..0743ce4a95c1 100644
--- a/test/CodeGen/PowerPC/quadint-return.ll
+++ b/test/CodeGen/PowerPC/quadint-return.ll
@@ -8,7 +8,7 @@ define i128 @foo() nounwind {
 entry:
   %x = alloca i128, align 16
   store i128 27, i128* %x, align 16
-  %0 = load i128* %x, align 16
+  %0 = load i128, i128* %x, align 16
   ret i128 %0
 }
 
diff --git a/test/CodeGen/PowerPC/reg-coalesce-simple.ll b/test/CodeGen/PowerPC/reg-coalesce-simple.ll
index e0ddb4250fd2..3f9cb8a74270 100644
--- a/test/CodeGen/PowerPC/reg-coalesce-simple.ll
+++ b/test/CodeGen/PowerPC/reg-coalesce-simple.ll
@@ -3,8 +3,8 @@
 %struct.foo = type { i32, i32, [0 x i8] }
 
 define i32 @test(%struct.foo* %X) nounwind {
-        %tmp1 = getelementptr %struct.foo* %X, i32 0, i32 2, i32 100            ; <i8*> [#uses=1]
-        %tmp = load i8* %tmp1           ; <i8> [#uses=1]
+        %tmp1 = getelementptr %struct.foo, %struct.foo* %X, i32 0, i32 2, i32 100            ; <i8*> [#uses=1]
+        %tmp = load i8, i8* %tmp1           ; <i8> [#uses=1]
         %tmp2 = zext i8 %tmp to i32             ; <i32> [#uses=1]
         ret i32 %tmp2
 }
diff --git a/test/CodeGen/PowerPC/reloc-align.ll b/test/CodeGen/PowerPC/reloc-align.ll
index 13d6adadfcae..754997bccbd6 100644
--- a/test/CodeGen/PowerPC/reloc-align.ll
+++ b/test/CodeGen/PowerPC/reloc-align.ll
@@ -24,7 +24,7 @@ entry:
 define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 {
 entry:
   %0 = bitcast %struct.S1* %p_91 to i64*
-  %bf.load = load i64* %0, align 1
+  %bf.load = load i64, i64* %0, align 1
   %bf.shl = shl i64 %bf.load, 26
   %bf.ashr = ashr i64 %bf.shl, 54
   %bf.cast = trunc i64 %bf.ashr to i32
diff --git a/test/CodeGen/PowerPC/remat-imm.ll b/test/CodeGen/PowerPC/remat-imm.ll
index 520921f57a93..ffae8a97cc83 100644
--- a/test/CodeGen/PowerPC/remat-imm.ll
+++ b/test/CodeGen/PowerPC/remat-imm.ll
@@ -9,7 +9,7 @@ define i32 @main() nounwind {
 entry:
 ; CHECK: li 4, 128
 ; CHECK-NOT: mr 4, {{.*}}
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), i32 128, i32 128) nounwind
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), i32 128, i32 128) nounwind
   ret i32 0
 }
 
diff --git a/test/CodeGen/PowerPC/resolvefi-basereg.ll b/test/CodeGen/PowerPC/resolvefi-basereg.ll
index 62c2d139920a..a613c3310a55 100644
--- a/test/CodeGen/PowerPC/resolvefi-basereg.ll
+++ b/test/CodeGen/PowerPC/resolvefi-basereg.ll
@@ -35,21 +35,21 @@ entry:
   call void @llvm.memset.p0i8.i64(i8* bitcast (%struct.S1998* @s1998 to i8*), i8 0, i64 5168, i32 16, i1 false)
   call void @llvm.memset.p0i8.i64(i8* bitcast ([5 x %struct.S1998]* @a1998 to i8*), i8 0, i64 25840, i32 16, i1 false)
   call void @llvm.memset.p0i8.i64(i8* bitcast (%struct.Info* @info to i8*), i8 0, i64 832, i32 8, i1 false)
-  store i8* bitcast (%struct.S1998* @s1998 to i8*), i8** getelementptr inbounds (%struct.Info* @info, i32 0, i32 2), align 8
-  store i8* bitcast ([5 x %struct.S1998]* @a1998 to i8*), i8** getelementptr inbounds (%struct.Info* @info, i32 0, i32 3), align 8
-  store i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 3) to i8*), i8** getelementptr inbounds (%struct.Info* @info, i32 0, i32 4), align 8
-  store i64 5168, i64* getelementptr inbounds (%struct.Info* @info, i32 0, i32 6), align 8
-  store i64 16, i64* getelementptr inbounds (%struct.Info* @info, i32 0, i32 8), align 8
-  store i64 16, i64* getelementptr inbounds (%struct.Info* @info, i32 0, i32 9), align 8
-  store i64 16, i64* getelementptr inbounds (%struct.Info* @info, i32 0, i32 10), align 8
-  %0 = load i64* getelementptr inbounds (%struct.Info* @info, i32 0, i32 8), align 8
+  store i8* bitcast (%struct.S1998* @s1998 to i8*), i8** getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 2), align 8
+  store i8* bitcast ([5 x %struct.S1998]* @a1998 to i8*), i8** getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 3), align 8
+  store i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 3) to i8*), i8** getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 4), align 8
+  store i64 5168, i64* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 6), align 8
+  store i64 16, i64* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 8), align 8
+  store i64 16, i64* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 9), align 8
+  store i64 16, i64* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 10), align 8
+  %0 = load i64, i64* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 8), align 8
   %sub = sub i64 %0, 1
-  %and = and i64 ptrtoint (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 3) to i64), %sub
+  %and = and i64 ptrtoint (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 3) to i64), %sub
   %tobool = icmp ne i64 %and, 0
   br i1 %tobool, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %1 = load i32* @fails, align 4
+  %1 = load i32, i32* @fails, align 4
   %inc = add nsw i32 %1, 1
   store i32 %inc, i32* @fails, align 4
   br label %if.end
@@ -57,299 +57,299 @@ if.then:                                          ; preds = %entry
 if.end:                                           ; preds = %if.then, %entry
   store i32 0, i32* %i, align 4
   store i32 0, i32* %j, align 4
-  %2 = load i32* %i, align 4
+  %2 = load i32, i32* %i, align 4
   %idxprom = sext i32 %2 to i64
-  %arrayidx = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom
-  store i8* bitcast (i32** getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 0, i64 1) to i8*), i8** %arrayidx, align 8
-  %3 = load i32* %i, align 4
+  %arrayidx = getelementptr inbounds [32 x i8*], [32 x i8*]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom
+  store i8* bitcast (i32** getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 0, i64 1) to i8*), i8** %arrayidx, align 8
+  %3 = load i32, i32* %i, align 4
   %idxprom1 = sext i32 %3 to i64
-  %arrayidx2 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom1
+  %arrayidx2 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom1
   store i64 8, i64* %arrayidx2, align 8
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %idxprom3 = sext i32 %4 to i64
-  %arrayidx4 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom3
+  %arrayidx4 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom3
   store i64 8, i64* %arrayidx4, align 8
-  store i32* getelementptr inbounds ([256 x i32]* @intarray, i32 0, i64 190), i32** getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 0, i64 1), align 8
-  store i32* getelementptr inbounds ([256 x i32]* @intarray, i32 0, i64 241), i32** getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 0, i64 1), align 8
-  %5 = load i32* %i, align 4
+  store i32* getelementptr inbounds ([256 x i32], [256 x i32]* @intarray, i32 0, i64 190), i32** getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 0, i64 1), align 8
+  store i32* getelementptr inbounds ([256 x i32], [256 x i32]* @intarray, i32 0, i64 241), i32** getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 0, i64 1), align 8
+  %5 = load i32, i32* %i, align 4
   %inc5 = add nsw i32 %5, 1
   store i32 %inc5, i32* %i, align 4
-  %6 = load i32* %i, align 4
+  %6 = load i32, i32* %i, align 4
   %idxprom6 = sext i32 %6 to i64
-  %arrayidx7 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom6
-  store i8* bitcast (i64* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 1) to i8*), i8** %arrayidx7, align 8
-  %7 = load i32* %i, align 4
+  %arrayidx7 = getelementptr inbounds [32 x i8*], [32 x i8*]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom6
+  store i8* bitcast (i64* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 1) to i8*), i8** %arrayidx7, align 8
+  %7 = load i32, i32* %i, align 4
   %idxprom8 = sext i32 %7 to i64
-  %arrayidx9 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom8
+  %arrayidx9 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom8
   store i64 8, i64* %arrayidx9, align 8
-  %8 = load i32* %i, align 4
+  %8 = load i32, i32* %i, align 4
   %idxprom10 = sext i32 %8 to i64
-  %arrayidx11 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom10
+  %arrayidx11 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom10
   store i64 8, i64* %arrayidx11, align 8
-  store i64 -3866974208859106459, i64* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 1), align 8
-  store i64 -185376695371304091, i64* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 1), align 8
-  %9 = load i32* %i, align 4
+  store i64 -3866974208859106459, i64* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 1), align 8
+  store i64 -185376695371304091, i64* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 1), align 8
+  %9 = load i32, i32* %i, align 4
   %inc12 = add nsw i32 %9, 1
   store i32 %inc12, i32* %i, align 4
-  %10 = load i32* %i, align 4
+  %10 = load i32, i32* %i, align 4
   %idxprom13 = sext i32 %10 to i64
-  %arrayidx14 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom13
-  store i8* bitcast (i64* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 2) to i8*), i8** %arrayidx14, align 8
-  %11 = load i32* %i, align 4
+  %arrayidx14 = getelementptr inbounds [32 x i8*], [32 x i8*]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom13
+  store i8* bitcast (i64* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 2) to i8*), i8** %arrayidx14, align 8
+  %11 = load i32, i32* %i, align 4
   %idxprom15 = sext i32 %11 to i64
-  %arrayidx16 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom15
+  %arrayidx16 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom15
   store i64 8, i64* %arrayidx16, align 8
-  %12 = load i32* %i, align 4
+  %12 = load i32, i32* %i, align 4
   %idxprom17 = sext i32 %12 to i64
-  %arrayidx18 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom17
+  %arrayidx18 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom17
   store i64 8, i64* %arrayidx18, align 8
-  store i64 -963638028680427187, i64* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 2), align 8
-  store i64 7510542175772455554, i64* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 2), align 8
-  %13 = load i32* %i, align 4
+  store i64 -963638028680427187, i64* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 2), align 8
+  store i64 7510542175772455554, i64* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 2), align 8
+  %13 = load i32, i32* %i, align 4
   %inc19 = add nsw i32 %13, 1
   store i32 %inc19, i32* %i, align 4
-  %14 = load i32* %i, align 4
+  %14 = load i32, i32* %i, align 4
   %idxprom20 = sext i32 %14 to i64
-  %arrayidx21 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom20
-  store i8* bitcast (double* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 3) to i8*), i8** %arrayidx21, align 8
-  %15 = load i32* %i, align 4
+  %arrayidx21 = getelementptr inbounds [32 x i8*], [32 x i8*]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom20
+  store i8* bitcast (double* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 3) to i8*), i8** %arrayidx21, align 8
+  %15 = load i32, i32* %i, align 4
   %idxprom22 = sext i32 %15 to i64
-  %arrayidx23 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom22
+  %arrayidx23 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom22
   store i64 8, i64* %arrayidx23, align 8
-  %16 = load i32* %i, align 4
+  %16 = load i32, i32* %i, align 4
   %idxprom24 = sext i32 %16 to i64
-  %arrayidx25 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom24
+  %arrayidx25 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom24
   store i64 16, i64* %arrayidx25, align 8
-  store double 0xC0F8783300000000, double* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 3), align 16
-  store double 0xC10DF3CCC0000000, double* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 3), align 16
-  %17 = load i32* %i, align 4
+  store double 0xC0F8783300000000, double* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 3), align 16
+  store double 0xC10DF3CCC0000000, double* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 3), align 16
+  %17 = load i32, i32* %i, align 4
   %inc26 = add nsw i32 %17, 1
   store i32 %inc26, i32* %i, align 4
-  %18 = load i32* %i, align 4
+  %18 = load i32, i32* %i, align 4
   %idxprom27 = sext i32 %18 to i64
-  %arrayidx28 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom27
-  store i8* bitcast (i16* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 4) to i8*), i8** %arrayidx28, align 8
-  %19 = load i32* %i, align 4
+  %arrayidx28 = getelementptr inbounds [32 x i8*], [32 x i8*]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom27
+  store i8* bitcast (i16* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 4) to i8*), i8** %arrayidx28, align 8
+  %19 = load i32, i32* %i, align 4
   %idxprom29 = sext i32 %19 to i64
-  %arrayidx30 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom29
+  %arrayidx30 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom29
   store i64 2, i64* %arrayidx30, align 8
-  %20 = load i32* %i, align 4
+  %20 = load i32, i32* %i, align 4
   %idxprom31 = sext i32 %20 to i64
-  %arrayidx32 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom31
+  %arrayidx32 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom31
   store i64 2, i64* %arrayidx32, align 8
-  store i16 -15897, i16* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 4), align 2
-  store i16 30935, i16* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 4), align 2
-  %21 = load i32* %i, align 4
+  store i16 -15897, i16* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 4), align 2
+  store i16 30935, i16* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 4), align 2
+  %21 = load i32, i32* %i, align 4
   %inc33 = add nsw i32 %21, 1
   store i32 %inc33, i32* %i, align 4
-  store i32 -419541644, i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 5), align 4
-  store i32 2125926812, i32* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 5), align 4
-  %22 = load i32* %j, align 4
+  store i32 -419541644, i32* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 5), align 4
+  store i32 2125926812, i32* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 5), align 4
+  %22 = load i32, i32* %j, align 4
   %inc34 = add nsw i32 %22, 1
   store i32 %inc34, i32* %j, align 4
-  %23 = load i32* %i, align 4
+  %23 = load i32, i32* %i, align 4
   %idxprom35 = sext i32 %23 to i64
-  %arrayidx36 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom35
-  store i8* bitcast (double* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 0, i64 0) to i8*), i8** %arrayidx36, align 8
-  %24 = load i32* %i, align 4
+  %arrayidx36 = getelementptr inbounds [32 x i8*], [32 x i8*]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom35
+  store i8* bitcast (double* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 0, i64 0) to i8*), i8** %arrayidx36, align 8
+  %24 = load i32, i32* %i, align 4
   %idxprom37 = sext i32 %24 to i64
-  %arrayidx38 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom37
+  %arrayidx38 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom37
   store i64 8, i64* %arrayidx38, align 8
-  %25 = load i32* %i, align 4
+  %25 = load i32, i32* %i, align 4
   %idxprom39 = sext i32 %25 to i64
-  %arrayidx40 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom39
+  %arrayidx40 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom39
   store i64 8, i64* %arrayidx40, align 8
-  store double 0xC0FC765780000000, double* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 0, i64 0), align 8
-  store double 0xC1025CD7A0000000, double* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 0, i64 0), align 8
-  %26 = load i32* %i, align 4
+  store double 0xC0FC765780000000, double* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 0, i64 0), align 8
+  store double 0xC1025CD7A0000000, double* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 0, i64 0), align 8
+  %26 = load i32, i32* %i, align 4
   %inc41 = add nsw i32 %26, 1
   store i32 %inc41, i32* %i, align 4
-  %bf.load = load i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 1), align 8
+  %bf.load = load i32, i32* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 1), align 8
   %bf.clear = and i32 %bf.load, 7
   %bf.set = or i32 %bf.clear, 16
-  store i32 %bf.set, i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 1), align 8
-  %bf.load42 = load i32* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 1), align 8
+  store i32 %bf.set, i32* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 1), align 8
+  %bf.load42 = load i32, i32* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 1), align 8
   %bf.clear43 = and i32 %bf.load42, 7
   %bf.set44 = or i32 %bf.clear43, 24
-  store i32 %bf.set44, i32* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 1), align 8
-  %27 = load i32* %j, align 4
+  store i32 %bf.set44, i32* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 1), align 8
+  %27 = load i32, i32* %j, align 4
   %inc45 = add nsw i32 %27, 1
   store i32 %inc45, i32* %j, align 4
-  %bf.load46 = load i16* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 2), align 4
+  %bf.load46 = load i16, i16* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 2), align 4
   %bf.clear47 = and i16 %bf.load46, 127
-  store i16 %bf.clear47, i16* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 2), align 4
-  %bf.load48 = load i16* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 2), align 4
+  store i16 %bf.clear47, i16* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 2), align 4
+  %bf.load48 = load i16, i16* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 2), align 4
   %bf.clear49 = and i16 %bf.load48, 127
-  store i16 %bf.clear49, i16* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 2), align 4
-  %28 = load i32* %j, align 4
+  store i16 %bf.clear49, i16* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 2), align 4
+  %28 = load i32, i32* %j, align 4
   %inc50 = add nsw i32 %28, 1
   store i32 %inc50, i32* %j, align 4
-  %bf.load51 = load i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 3), align 8
+  %bf.load51 = load i32, i32* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 3), align 8
   %bf.clear52 = and i32 %bf.load51, 63
-  store i32 %bf.clear52, i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 3), align 8
-  %bf.load53 = load i32* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 3), align 8
+  store i32 %bf.clear52, i32* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 3), align 8
+  %bf.load53 = load i32, i32* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 3), align 8
   %bf.clear54 = and i32 %bf.load53, 63
   %bf.set55 = or i32 %bf.clear54, 64
-  store i32 %bf.set55, i32* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 3), align 8
-  %29 = load i32* %j, align 4
+  store i32 %bf.set55, i32* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 3), align 8
+  %29 = load i32, i32* %j, align 4
   %inc56 = add nsw i32 %29, 1
   store i32 %inc56, i32* %j, align 4
-  %bf.load57 = load i24* bitcast ([3 x i8]* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 4) to i24*), align 4
+  %bf.load57 = load i24, i24* bitcast ([3 x i8]* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 4) to i24*), align 4
   %bf.clear58 = and i24 %bf.load57, 63
-  store i24 %bf.clear58, i24* bitcast ([3 x i8]* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 4) to i24*), align 4
-  %bf.load59 = load i24* bitcast ([3 x i8]* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 4) to i24*), align 4
+  store i24 %bf.clear58, i24* bitcast ([3 x i8]* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 4) to i24*), align 4
+  %bf.load59 = load i24, i24* bitcast ([3 x i8]* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 4) to i24*), align 4
   %bf.clear60 = and i24 %bf.load59, 63
-  store i24 %bf.clear60, i24* bitcast ([3 x i8]* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 4) to i24*), align 4
-  %30 = load i32* %j, align 4
+  store i24 %bf.clear60, i24* bitcast ([3 x i8]* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 4) to i24*), align 4
+  %30 = load i32, i32* %j, align 4
   %inc61 = add nsw i32 %30, 1
   store i32 %inc61, i32* %j, align 4
-  %31 = load i32* %i, align 4
+  %31 = load i32, i32* %i, align 4
   %idxprom62 = sext i32 %31 to i64
-  %arrayidx63 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom62
-  store i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 5, i64 5), i8** %arrayidx63, align 8
-  %32 = load i32* %i, align 4
+  %arrayidx63 = getelementptr inbounds [32 x i8*], [32 x i8*]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom62
+  store i8* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 5, i64 5), i8** %arrayidx63, align 8
+  %32 = load i32, i32* %i, align 4
   %idxprom64 = sext i32 %32 to i64
-  %arrayidx65 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom64
+  %arrayidx65 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom64
   store i64 1, i64* %arrayidx65, align 8
-  %33 = load i32* %i, align 4
+  %33 = load i32, i32* %i, align 4
   %idxprom66 = sext i32 %33 to i64
-  %arrayidx67 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom66
+  %arrayidx67 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom66
   store i64 1, i64* %arrayidx67, align 8
-  store i8 -83, i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 5, i64 5), align 1
-  store i8 -67, i8* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 5, i64 5), align 1
-  %34 = load i32* %i, align 4
+  store i8 -83, i8* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 5, i64 5), align 1
+  store i8 -67, i8* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 5, i64 5), align 1
+  %34 = load i32, i32* %i, align 4
   %inc68 = add nsw i32 %34, 1
   store i32 %inc68, i32* %i, align 4
-  %35 = load i32* %i, align 4
+  %35 = load i32, i32* %i, align 4
   %idxprom69 = sext i32 %35 to i64
-  %arrayidx70 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom69
-  store i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 5, i64 1), i8** %arrayidx70, align 8
-  %36 = load i32* %i, align 4
+  %arrayidx70 = getelementptr inbounds [32 x i8*], [32 x i8*]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom69
+  store i8* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 5, i64 1), i8** %arrayidx70, align 8
+  %36 = load i32, i32* %i, align 4
   %idxprom71 = sext i32 %36 to i64
-  %arrayidx72 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom71
+  %arrayidx72 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom71
   store i64 1, i64* %arrayidx72, align 8
-  %37 = load i32* %i, align 4
+  %37 = load i32, i32* %i, align 4
   %idxprom73 = sext i32 %37 to i64
-  %arrayidx74 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom73
+  %arrayidx74 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom73
   store i64 1, i64* %arrayidx74, align 8
-  store i8 34, i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 5, i64 1), align 1
-  store i8 64, i8* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 5, i64 1), align 1
-  %38 = load i32* %i, align 4
+  store i8 34, i8* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 5, i64 1), align 1
+  store i8 64, i8* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 5, i64 1), align 1
+  %38 = load i32, i32* %i, align 4
   %inc75 = add nsw i32 %38, 1
   store i32 %inc75, i32* %i, align 4
-  %39 = load i32* %i, align 4
+  %39 = load i32, i32* %i, align 4
   %idxprom76 = sext i32 %39 to i64
-  %arrayidx77 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom76
-  store i8* bitcast (i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 6, i64 3) to i8*), i8** %arrayidx77, align 8
-  %40 = load i32* %i, align 4
+  %arrayidx77 = getelementptr inbounds [32 x i8*], [32 x i8*]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom76
+  store i8* bitcast (i32* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 6, i64 3) to i8*), i8** %arrayidx77, align 8
+  %40 = load i32, i32* %i, align 4
   %idxprom78 = sext i32 %40 to i64
-  %arrayidx79 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom78
+  %arrayidx79 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom78
   store i64 4, i64* %arrayidx79, align 8
-  %41 = load i32* %i, align 4
+  %41 = load i32, i32* %i, align 4
   %idxprom80 = sext i32 %41 to i64
-  %arrayidx81 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom80
+  %arrayidx81 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom80
   store i64 4, i64* %arrayidx81, align 8
-  store i32 -3, i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 6, i64 3), align 4
-  store i32 -3, i32* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 6, i64 3), align 4
-  %42 = load i32* %i, align 4
+  store i32 -3, i32* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 6, i64 3), align 4
+  store i32 -3, i32* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 6, i64 3), align 4
+  %42 = load i32, i32* %i, align 4
   %inc82 = add nsw i32 %42, 1
   store i32 %inc82, i32* %i, align 4
-  %43 = load i32* %i, align 4
+  %43 = load i32, i32* %i, align 4
   %idxprom83 = sext i32 %43 to i64
-  %arrayidx84 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom83
-  store i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 7), i8** %arrayidx84, align 8
-  %44 = load i32* %i, align 4
+  %arrayidx84 = getelementptr inbounds [32 x i8*], [32 x i8*]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom83
+  store i8* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 7), i8** %arrayidx84, align 8
+  %44 = load i32, i32* %i, align 4
   %idxprom85 = sext i32 %44 to i64
-  %arrayidx86 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom85
+  %arrayidx86 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom85
   store i64 1, i64* %arrayidx86, align 8
-  %45 = load i32* %i, align 4
+  %45 = load i32, i32* %i, align 4
   %idxprom87 = sext i32 %45 to i64
-  %arrayidx88 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom87
+  %arrayidx88 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom87
   store i64 1, i64* %arrayidx88, align 8
-  store i8 106, i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 7), align 1
-  store i8 -102, i8* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 7), align 1
-  %46 = load i32* %i, align 4
+  store i8 106, i8* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 7), align 1
+  store i8 -102, i8* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 7), align 1
+  %46 = load i32, i32* %i, align 4
   %inc89 = add nsw i32 %46, 1
   store i32 %inc89, i32* %i, align 4
-  %47 = load i32* %i, align 4
+  %47 = load i32, i32* %i, align 4
   %idxprom90 = sext i32 %47 to i64
-  %arrayidx91 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom90
-  store i8* bitcast (i16* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 7) to i8*), i8** %arrayidx91, align 8
-  %48 = load i32* %i, align 4
+  %arrayidx91 = getelementptr inbounds [32 x i8*], [32 x i8*]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom90
+  store i8* bitcast (i16* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 7) to i8*), i8** %arrayidx91, align 8
+  %48 = load i32, i32* %i, align 4
   %idxprom92 = sext i32 %48 to i64
-  %arrayidx93 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom92
+  %arrayidx93 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom92
   store i64 2, i64* %arrayidx93, align 8
-  %49 = load i32* %i, align 4
+  %49 = load i32, i32* %i, align 4
   %idxprom94 = sext i32 %49 to i64
-  %arrayidx95 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom94
+  %arrayidx95 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom94
   store i64 2, i64* %arrayidx95, align 8
-  store i16 29665, i16* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 7), align 2
-  store i16 7107, i16* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 7), align 2
-  %50 = load i32* %i, align 4
+  store i16 29665, i16* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 7), align 2
+  store i16 7107, i16* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 7), align 2
+  %50 = load i32, i32* %i, align 4
   %inc96 = add nsw i32 %50, 1
   store i32 %inc96, i32* %i, align 4
-  %51 = load i32* %i, align 4
+  %51 = load i32, i32* %i, align 4
   %idxprom97 = sext i32 %51 to i64
-  %arrayidx98 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom97
-  store i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 8), i8** %arrayidx98, align 8
-  %52 = load i32* %i, align 4
+  %arrayidx98 = getelementptr inbounds [32 x i8*], [32 x i8*]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom97
+  store i8* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 8), i8** %arrayidx98, align 8
+  %52 = load i32, i32* %i, align 4
   %idxprom99 = sext i32 %52 to i64
-  %arrayidx100 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom99
+  %arrayidx100 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom99
   store i64 1, i64* %arrayidx100, align 8
-  %53 = load i32* %i, align 4
+  %53 = load i32, i32* %i, align 4
   %idxprom101 = sext i32 %53 to i64
-  %arrayidx102 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom101
+  %arrayidx102 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom101
   store i64 1, i64* %arrayidx102, align 8
-  store i8 52, i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 8), align 1
-  store i8 -86, i8* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 8), align 1
-  %54 = load i32* %i, align 4
+  store i8 52, i8* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 8), align 1
+  store i8 -86, i8* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 8), align 1
+  %54 = load i32, i32* %i, align 4
   %inc103 = add nsw i32 %54, 1
   store i32 %inc103, i32* %i, align 4
-  %55 = load i32* %i, align 4
+  %55 = load i32, i32* %i, align 4
   %idxprom104 = sext i32 %55 to i64
-  %arrayidx105 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom104
-  store i8* bitcast (i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 9) to i8*), i8** %arrayidx105, align 8
-  %56 = load i32* %i, align 4
+  %arrayidx105 = getelementptr inbounds [32 x i8*], [32 x i8*]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom104
+  store i8* bitcast (i32* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 9) to i8*), i8** %arrayidx105, align 8
+  %56 = load i32, i32* %i, align 4
   %idxprom106 = sext i32 %56 to i64
-  %arrayidx107 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom106
+  %arrayidx107 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom106
   store i64 4, i64* %arrayidx107, align 8
-  %57 = load i32* %i, align 4
+  %57 = load i32, i32* %i, align 4
   %idxprom108 = sext i32 %57 to i64
-  %arrayidx109 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom108
+  %arrayidx109 = getelementptr inbounds [32 x i64], [32 x i64]* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom108
   store i64 4, i64* %arrayidx109, align 8
-  store i32 -54118453, i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 9), align 4
-  store i32 1668755823, i32* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 9), align 4
-  %58 = load i32* %i, align 4
+  store i32 -54118453, i32* getelementptr inbounds (%struct.S1998, %struct.S1998* @s1998, i32 0, i32 9), align 4
+  store i32 1668755823, i32* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 9), align 4
+  %58 = load i32, i32* %i, align 4
   %inc110 = add nsw i32 %58, 1
   store i32 %inc110, i32* %i, align 4
   store i32 %inc110, i32* %tmp
-  %59 = load i32* %tmp
-  %60 = load i32* %i, align 4
-  store i32 %60, i32* getelementptr inbounds (%struct.Info* @info, i32 0, i32 0), align 4
-  %61 = load i32* %j, align 4
-  store i32 %61, i32* getelementptr inbounds (%struct.Info* @info, i32 0, i32 1), align 4
+  %59 = load i32, i32* %tmp
+  %60 = load i32, i32* %i, align 4
+  store i32 %60, i32* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 0), align 4
+  %61 = load i32, i32* %j, align 4
+  store i32 %61, i32* getelementptr inbounds (%struct.Info, %struct.Info* @info, i32 0, i32 1), align 4
   %62 = bitcast %struct.S1998* %agg.tmp111 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %62, i8* bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i32 16, i1 false)
   %63 = bitcast %struct.S1998* %agg.tmp112 to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %63, i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i32 16, i1 false)
-  call void @check1998(%struct.S1998* sret %agg.tmp, %struct.S1998* byval align 16 %agg.tmp111, %struct.S1998* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 1), %struct.S1998* byval align 16 %agg.tmp112)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %63, i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i32 16, i1 false)
+  call void @check1998(%struct.S1998* sret %agg.tmp, %struct.S1998* byval align 16 %agg.tmp111, %struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 1), %struct.S1998* byval align 16 %agg.tmp112)
   call void @checkx1998(%struct.S1998* byval align 16 %agg.tmp)
   %64 = bitcast %struct.S1998* %agg.tmp113 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %64, i8* bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i32 16, i1 false)
   %65 = bitcast %struct.S1998* %agg.tmp114 to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %65, i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i32 16, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %65, i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i32 16, i1 false)
   %66 = bitcast %struct.S1998* %agg.tmp115 to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %66, i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i32 16, i1 false)
-  call void (i32, ...)* @check1998va(i32 signext 1, double 1.000000e+00, %struct.S1998* byval align 16 %agg.tmp113, i64 2, %struct.S1998* byval align 16 %agg.tmp114, %struct.S1998* byval align 16 %agg.tmp115)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %66, i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i32 16, i1 false)
+  call void (i32, ...) @check1998va(i32 signext 1, double 1.000000e+00, %struct.S1998* byval align 16 %agg.tmp113, i64 2, %struct.S1998* byval align 16 %agg.tmp114, %struct.S1998* byval align 16 %agg.tmp115)
   %67 = bitcast %struct.S1998* %agg.tmp116 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %67, i8* bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i32 16, i1 false)
   %68 = bitcast %struct.S1998* %agg.tmp117 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %68, i8* bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i32 16, i1 false)
   %69 = bitcast %struct.S1998* %agg.tmp118 to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %69, i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i32 16, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %69, i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i32 16, i1 false)
   %70 = bitcast %struct.S1998* %agg.tmp119 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %70, i8* bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i32 16, i1 false)
-  call void (i32, ...)* @check1998va(i32 signext 2, %struct.S1998* byval align 16 %agg.tmp116, %struct.S1998* byval align 16 %agg.tmp117, ppc_fp128 0xM40000000000000000000000000000000, %struct.S1998* byval align 16 %agg.tmp118, %struct.S1998* byval align 16 %agg.tmp119)
+  call void (i32, ...) @check1998va(i32 signext 2, %struct.S1998* byval align 16 %agg.tmp116, %struct.S1998* byval align 16 %agg.tmp117, ppc_fp128 0xM40000000000000000000000000000000, %struct.S1998* byval align 16 %agg.tmp118, %struct.S1998* byval align 16 %agg.tmp119)
   ret void
 }
 
diff --git a/test/CodeGen/PowerPC/resolvefi-disp.ll b/test/CodeGen/PowerPC/resolvefi-disp.ll
index ca42bcd767a0..a1c2070a6f44 100644
--- a/test/CodeGen/PowerPC/resolvefi-disp.ll
+++ b/test/CodeGen/PowerPC/resolvefi-disp.ll
@@ -41,23 +41,23 @@ entry:
   call void @llvm.memset.p0i8.i64(i8* %7, i8 0, i64 11104, i32 32, i1 false)
   %8 = bitcast %struct.S2760* %b2 to i8*
   call void @llvm.memset.p0i8.i64(i8* %8, i8 0, i64 11104, i32 32, i1 false)
-  %b = getelementptr inbounds %struct.S2760* %arg0, i32 0, i32 1
-  %g = getelementptr inbounds %struct.anon* %b, i32 0, i32 1
-  %9 = load i64* %g, align 8
-  %10 = load i64* getelementptr inbounds (%struct.S2760* @s2760, i32 0, i32 1, i32 1), align 8
+  %b = getelementptr inbounds %struct.S2760, %struct.S2760* %arg0, i32 0, i32 1
+  %g = getelementptr inbounds %struct.anon, %struct.anon* %b, i32 0, i32 1
+  %9 = load i64, i64* %g, align 8
+  %10 = load i64, i64* getelementptr inbounds (%struct.S2760, %struct.S2760* @s2760, i32 0, i32 1, i32 1), align 8
   %cmp = icmp ne i64 %9, %10
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %11 = load i32* @fails, align 4
+  %11 = load i32, i32* @fails, align 4
   %inc = add nsw i32 %11, 1
   store i32 %inc, i32* @fails, align 4
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
-  %12 = load i64* getelementptr inbounds (%struct.S2760* @s2760, i32 0, i32 1, i32 1), align 8
-  %b3 = getelementptr inbounds %struct.S2760* %ret, i32 0, i32 1
-  %g4 = getelementptr inbounds %struct.anon* %b3, i32 0, i32 1
+  %12 = load i64, i64* getelementptr inbounds (%struct.S2760, %struct.S2760* @s2760, i32 0, i32 1, i32 1), align 8
+  %b3 = getelementptr inbounds %struct.S2760, %struct.S2760* %ret, i32 0, i32 1
+  %g4 = getelementptr inbounds %struct.anon, %struct.anon* %b3, i32 0, i32 1
   store i64 %12, i64* %g4, align 8
   %13 = bitcast %struct.S2760* %agg.result to i8*
   %14 = bitcast %struct.S2760* %ret to i8*
diff --git a/test/CodeGen/PowerPC/retaddr2.ll b/test/CodeGen/PowerPC/retaddr2.ll
index 8fa3b4d13b7e..8581f6cb9a38 100644
--- a/test/CodeGen/PowerPC/retaddr2.ll
+++ b/test/CodeGen/PowerPC/retaddr2.ll
@@ -12,8 +12,7 @@ entry:
 ; CHECK-LABEL: @test1
 ; CHECK: mflr 0
 ; CHECK: std 0, 16(1)
-; FIXME: These next two lines don't both need to load the same value.
-; CHECK-DAG: ld 3, 16(1)
+; CHECK-DAG: ld 3, 64(1)
 ; CHECK-DAG: ld 0, 16(1)
 ; CHECK: mtlr 0
 ; CHECK: blr
diff --git a/test/CodeGen/PowerPC/return-val-i128.ll b/test/CodeGen/PowerPC/return-val-i128.ll
index e14a43809a7b..2f924096661a 100644
--- a/test/CodeGen/PowerPC/return-val-i128.ll
+++ b/test/CodeGen/PowerPC/return-val-i128.ll
@@ -7,29 +7,29 @@ entry:
 	%tmp = alloca i128, align 16		; <i128*> [#uses=3]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float %a, float* %a_addr
-	%tmp1 = load float* %a_addr, align 4		; <float> [#uses=1]
+	%tmp1 = load float, float* %a_addr, align 4		; <float> [#uses=1]
 	%tmp2 = fcmp olt float %tmp1, 0.000000e+00		; <i1> [#uses=1]
 	%tmp23 = zext i1 %tmp2 to i8		; <i8> [#uses=1]
 	%toBool = icmp ne i8 %tmp23, 0		; <i1> [#uses=1]
 	br i1 %toBool, label %bb, label %bb8
 bb:		; preds = %entry
-	%tmp4 = load float* %a_addr, align 4		; <float> [#uses=1]
+	%tmp4 = load float, float* %a_addr, align 4		; <float> [#uses=1]
 	%tmp5 = fsub float -0.000000e+00, %tmp4		; <float> [#uses=1]
 	%tmp6 = call i128 @__fixunssfDI( float %tmp5 ) nounwind 		; <i128> [#uses=1]
 	%tmp7 = sub i128 0, %tmp6		; <i128> [#uses=1]
 	store i128 %tmp7, i128* %tmp, align 16
 	br label %bb11
 bb8:		; preds = %entry
-	%tmp9 = load float* %a_addr, align 4		; <float> [#uses=1]
+	%tmp9 = load float, float* %a_addr, align 4		; <float> [#uses=1]
 	%tmp10 = call i128 @__fixunssfDI( float %tmp9 ) nounwind 		; <i128> [#uses=1]
 	store i128 %tmp10, i128* %tmp, align 16
 	br label %bb11
 bb11:		; preds = %bb8, %bb
-	%tmp12 = load i128* %tmp, align 16		; <i128> [#uses=1]
+	%tmp12 = load i128, i128* %tmp, align 16		; <i128> [#uses=1]
 	store i128 %tmp12, i128* %retval, align 16
 	br label %return
 return:		; preds = %bb11
-	%retval13 = load i128* %retval		; <i128> [#uses=1]
+	%retval13 = load i128, i128* %retval		; <i128> [#uses=1]
 	ret i128 %retval13
 }
 
diff --git a/test/CodeGen/PowerPC/rlwimi-and.ll b/test/CodeGen/PowerPC/rlwimi-and.ll
index 9433f8e3dee2..59f704ee16bc 100644
--- a/test/CodeGen/PowerPC/rlwimi-and.ll
+++ b/test/CodeGen/PowerPC/rlwimi-and.ll
@@ -16,11 +16,11 @@ codeRepl12:                                       ; preds = %codeRepl4
   unreachable
 
 codeRepl17:                                       ; preds = %codeRepl4
-  %0 = load i8* undef, align 2
+  %0 = load i8, i8* undef, align 2
   %1 = and i8 %0, 1
   %not.tobool.i.i.i = icmp eq i8 %1, 0
   %2 = select i1 %not.tobool.i.i.i, i16 0, i16 256
-  %3 = load i8* undef, align 1
+  %3 = load i8, i8* undef, align 1
   %4 = and i8 %3, 1
   %not.tobool.i.1.i.i = icmp eq i8 %4, 0
   %rvml38.sroa.1.1.insert.ext = select i1 %not.tobool.i.1.i.i, i16 0, i16 1
@@ -29,7 +29,7 @@ codeRepl17:                                       ; preds = %codeRepl4
   unreachable
 
 ; CHECK: @test
-; CHECK: rlwinm [[R1:[0-9]+]], {{[0-9]+}}, 0, 31, 31
+; CHECK: clrlwi [[R1:[0-9]+]], {{[0-9]+}}, 31
 ; CHECK: rlwimi [[R1]], {{[0-9]+}}, 8, 23, 23
 
 codeRepl29:                                       ; preds = %codeRepl1
diff --git a/test/CodeGen/PowerPC/rlwimi-commute.ll b/test/CodeGen/PowerPC/rlwimi-commute.ll
index 3f90008c006b..cd0f49ed7807 100644
--- a/test/CodeGen/PowerPC/rlwimi-commute.ll
+++ b/test/CodeGen/PowerPC/rlwimi-commute.ll
@@ -4,8 +4,8 @@
 ; Make sure there is no register-register copies here.
 
 define void @test1(i32* %A, i32* %B, i32* %D, i32* %E) {
-	%A.upgrd.1 = load i32* %A		; <i32> [#uses=2]
-	%B.upgrd.2 = load i32* %B		; <i32> [#uses=1]
+	%A.upgrd.1 = load i32, i32* %A		; <i32> [#uses=2]
+	%B.upgrd.2 = load i32, i32* %B		; <i32> [#uses=1]
 	%X = and i32 %A.upgrd.1, 15		; <i32> [#uses=1]
 	%Y = and i32 %B.upgrd.2, -16		; <i32> [#uses=1]
 	%Z = or i32 %X, %Y		; <i32> [#uses=1]
@@ -15,8 +15,8 @@ define void @test1(i32* %A, i32* %B, i32* %D, i32* %E) {
 }
 
 define void @test2(i32* %A, i32* %B, i32* %D, i32* %E) {
-	%A.upgrd.3 = load i32* %A		; <i32> [#uses=1]
-	%B.upgrd.4 = load i32* %B		; <i32> [#uses=2]
+	%A.upgrd.3 = load i32, i32* %A		; <i32> [#uses=1]
+	%B.upgrd.4 = load i32, i32* %B		; <i32> [#uses=2]
 	%X = and i32 %A.upgrd.3, 15		; <i32> [#uses=1]
 	%Y = and i32 %B.upgrd.4, -16		; <i32> [#uses=1]
 	%Z = or i32 %X, %Y		; <i32> [#uses=1]
diff --git a/test/CodeGen/PowerPC/rlwimi-dyn-and.ll b/test/CodeGen/PowerPC/rlwimi-dyn-and.ll
index e02801fafbf5..76f3da66dd04 100644
--- a/test/CodeGen/PowerPC/rlwimi-dyn-and.ll
+++ b/test/CodeGen/PowerPC/rlwimi-dyn-and.ll
@@ -4,13 +4,13 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define i32 @test1() #0 {
 entry:
-  %conv67.reload = load i32* undef
+  %conv67.reload = load i32, i32* undef
   %const = bitcast i32 65535 to i32
   br label %next
 
 next:
   %shl161 = shl nuw nsw i32 %conv67.reload, 15
-  %0 = load i8* undef, align 1
+  %0 = load i8, i8* undef, align 1
   %conv169 = zext i8 %0 to i32
   %shl170 = shl nuw nsw i32 %conv169, 7
   %const_mat = add i32 %const, -32767
@@ -25,13 +25,13 @@ next:
 
 define i32 @test2() #0 {
 entry:
-  %conv67.reload = load i32* undef
+  %conv67.reload = load i32, i32* undef
   %const = bitcast i32 65535 to i32
   br label %next
 
 next:
   %shl161 = shl nuw nsw i32 %conv67.reload, 15
-  %0 = load i8* undef, align 1
+  %0 = load i8, i8* undef, align 1
   %conv169 = zext i8 %0 to i32
   %shl170 = shl nuw nsw i32 %conv169, 7
   %shl161.masked = and i32 %shl161, 32768
diff --git a/test/CodeGen/PowerPC/rm-zext.ll b/test/CodeGen/PowerPC/rm-zext.ll
index 33995e114d27..97c546c0145f 100644
--- a/test/CodeGen/PowerPC/rm-zext.ll
+++ b/test/CodeGen/PowerPC/rm-zext.ll
@@ -45,7 +45,7 @@ declare i32 @llvm.bswap.i32(i32) #0
 ; Function Attrs: nounwind readonly
 define zeroext i32 @bs32(i32* nocapture readonly %x) #1 {
 entry:
-  %0 = load i32* %x, align 4
+  %0 = load i32, i32* %x, align 4
   %1 = tail call i32 @llvm.bswap.i32(i32 %0)
   ret i32 %1
 
@@ -57,7 +57,7 @@ entry:
 ; Function Attrs: nounwind readonly
 define zeroext i16 @bs16(i16* nocapture readonly %x) #1 {
 entry:
-  %0 = load i16* %x, align 2
+  %0 = load i16, i16* %x, align 2
   %1 = tail call i16 @llvm.bswap.i16(i16 %0)
   ret i16 %1
 
diff --git a/test/CodeGen/PowerPC/rotl-2.ll b/test/CodeGen/PowerPC/rotl-2.ll
index d32ef59be6c4..86539b6c119c 100644
--- a/test/CodeGen/PowerPC/rotl-2.ll
+++ b/test/CodeGen/PowerPC/rotl-2.ll
@@ -1,5 +1,6 @@
-; RUN: llc < %s -march=ppc32  | grep rlwinm | count 4
-; RUN: llc < %s -march=ppc32  | grep rlwnm | count 2
+; RUN: llc < %s -march=ppc32  | grep rotlwi | count 2
+; RUN: llc < %s -march=ppc32  | grep clrlwi | count 2
+; RUN: llc < %s -march=ppc32  | grep rotlw | count 4
 ; RUN: llc < %s -march=ppc32  | not grep or
 
 define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
diff --git a/test/CodeGen/PowerPC/rotl-64.ll b/test/CodeGen/PowerPC/rotl-64.ll
index 674c9e4cc951..2ccdc29f2cd2 100644
--- a/test/CodeGen/PowerPC/rotl-64.ll
+++ b/test/CodeGen/PowerPC/rotl-64.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=ppc64 | grep rldicl
-; RUN: llc < %s -march=ppc64 | grep rldcl
+; RUN: llc < %s -march=ppc64 | grep rotld
+; RUN: llc < %s -march=ppc64 | grep rotldi
 ; PR1613
 
 define i64 @t1(i64 %A) {
diff --git a/test/CodeGen/PowerPC/rotl.ll b/test/CodeGen/PowerPC/rotl.ll
index 56fc4a8c911f..671f524645a7 100644
--- a/test/CodeGen/PowerPC/rotl.ll
+++ b/test/CodeGen/PowerPC/rotl.ll
@@ -1,5 +1,7 @@
-; RUN: llc < %s -march=ppc32 | grep rlwnm | count 2
-; RUN: llc < %s -march=ppc32 | grep rlwinm | count 2
+; RUN: llc < %s -march=ppc32 | grep rotrw: | count 1
+; RUN: llc < %s -march=ppc32 | grep rotlw: | count 1
+; RUN: llc < %s -march=ppc32 | grep rotlwi: | count 1
+; RUN: llc < %s -march=ppc32 | grep rotrwi: | count 1
 
 define i32 @rotlw(i32 %x, i32 %sh) {
 entry:
diff --git a/test/CodeGen/PowerPC/rs-undef-use.ll b/test/CodeGen/PowerPC/rs-undef-use.ll
index 24dd5fd9da99..007931e7407f 100644
--- a/test/CodeGen/PowerPC/rs-undef-use.ll
+++ b/test/CodeGen/PowerPC/rs-undef-use.ll
@@ -15,7 +15,7 @@ CF82.critedge:                                    ; preds = %CF
   br label %CF82
 
 CF82:                                             ; preds = %CF82, %CF82.critedge
-  %L17 = load i8* %0
+  %L17 = load i8, i8* %0
   %E18 = extractelement <2 x i64> undef, i32 0
   %PC = bitcast <2 x i1>* %A3 to i64*
   br i1 undef, label %CF82, label %CF84.critedge
@@ -25,13 +25,13 @@ CF84.critedge:                                    ; preds = %CF82
   br label %CF84
 
 CF84:                                             ; preds = %CF84, %CF84.critedge
-  %L40 = load i64* %PC
+  %L40 = load i64, i64* %PC
   store i64 -1, i64* %PC
   %Sl46 = select i1 undef, i1 undef, i1 false
   br i1 %Sl46, label %CF84, label %CF85
 
 CF85:                                             ; preds = %CF84
-  %L47 = load i64* %PC
+  %L47 = load i64, i64* %PC
   store i64 %E18, i64* %PC
   %PC52 = bitcast <8 x i32>* %A2 to ppc_fp128*
   store ppc_fp128 0xM4D436562A0416DE00000000000000000, ppc_fp128* %PC52
diff --git a/test/CodeGen/PowerPC/s000-alias-misched.ll b/test/CodeGen/PowerPC/s000-alias-misched.ll
index 3570a11b6271..2e34c65a0a38 100644
--- a/test/CodeGen/PowerPC/s000-alias-misched.ll
+++ b/test/CodeGen/PowerPC/s000-alias-misched.ll
@@ -22,7 +22,7 @@ declare signext i32 @init(i8*) nounwind
 
 define signext i32 @s000() nounwind {
 entry:
-  %call = tail call signext i32 @init(i8* getelementptr inbounds ([6 x i8]* @.str1, i64 0, i64 0))
+  %call = tail call signext i32 @init(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i64 0, i64 0))
   %call1 = tail call i64 @clock() nounwind
   br label %for.cond2.preheader
 
@@ -34,34 +34,34 @@ for.cond2.preheader:                              ; preds = %for.end, %entry
 
 for.body4:                                        ; preds = %for.body4, %for.cond2.preheader
   %indvars.iv = phi i64 [ 0, %for.cond2.preheader ], [ %indvars.iv.next.15, %for.body4 ]
-  %arrayidx = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv
-  %arrayidx6 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv
+  %arrayidx = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv
+  %arrayidx6 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv
   %0 = bitcast double* %arrayidx to <1 x double>*
-  %1 = load <1 x double>* %0, align 32
+  %1 = load <1 x double>, <1 x double>* %0, align 32
   %add = fadd <1 x double> %1, <double 1.000000e+00>
   %2 = bitcast double* %arrayidx6 to <1 x double>*
   store <1 x double> %add, <1 x double>* %2, align 32
   %indvars.iv.next.322 = or i64 %indvars.iv, 4
-  %arrayidx.4 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.322
-  %arrayidx6.4 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.322
+  %arrayidx.4 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.322
+  %arrayidx6.4 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.322
   %3 = bitcast double* %arrayidx.4 to <1 x double>*
-  %4 = load <1 x double>* %3, align 32
+  %4 = load <1 x double>, <1 x double>* %3, align 32
   %add.4 = fadd <1 x double> %4, <double 1.000000e+00>
   %5 = bitcast double* %arrayidx6.4 to <1 x double>*
   store <1 x double> %add.4, <1 x double>* %5, align 32
   %indvars.iv.next.726 = or i64 %indvars.iv, 8
-  %arrayidx.8 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.726
-  %arrayidx6.8 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.726
+  %arrayidx.8 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.726
+  %arrayidx6.8 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.726
   %6 = bitcast double* %arrayidx.8 to <1 x double>*
-  %7 = load <1 x double>* %6, align 32
+  %7 = load <1 x double>, <1 x double>* %6, align 32
   %add.8 = fadd <1 x double> %7, <double 1.000000e+00>
   %8 = bitcast double* %arrayidx6.8 to <1 x double>*
   store <1 x double> %add.8, <1 x double>* %8, align 32
   %indvars.iv.next.1130 = or i64 %indvars.iv, 12
-  %arrayidx.12 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1130
-  %arrayidx6.12 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1130
+  %arrayidx.12 = getelementptr inbounds [16000 x double], [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1130
+  %arrayidx6.12 = getelementptr inbounds [16000 x double], [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1130
   %9 = bitcast double* %arrayidx.12 to <1 x double>*
-  %10 = load <1 x double>* %9, align 32
+  %10 = load <1 x double>, <1 x double>* %9, align 32
   %add.12 = fadd <1 x double> %10, <double 1.000000e+00>
   %11 = bitcast double* %arrayidx6.12 to <1 x double>*
   store <1 x double> %add.12, <1 x double>* %11, align 32
@@ -77,7 +77,7 @@ for.body4:                                        ; preds = %for.body4, %for.con
 ; CHECK: bdnz
 
 for.end:                                          ; preds = %for.body4
-  %call7 = tail call signext i32 @dummy(double* getelementptr inbounds ([16000 x double]* @X, i64 0, i64 0), double* getelementptr inbounds ([16000 x double]* @Y, i64 0, i64 0), double* getelementptr inbounds ([16000 x double]* @Z, i64 0, i64 0), double* getelementptr inbounds ([16000 x double]* @U, i64 0, i64 0), double* getelementptr inbounds ([16000 x double]* @V, i64 0, i64 0), [256 x double]* getelementptr inbounds ([256 x [256 x double]]* @aa, i64 0, i64 0), [256 x double]* getelementptr inbounds ([256 x [256 x double]]* @bb, i64 0, i64 0), [256 x double]* getelementptr inbounds ([256 x [256 x double]]* @cc, i64 0, i64 0), double 0.000000e+00) nounwind
+  %call7 = tail call signext i32 @dummy(double* getelementptr inbounds ([16000 x double], [16000 x double]* @X, i64 0, i64 0), double* getelementptr inbounds ([16000 x double], [16000 x double]* @Y, i64 0, i64 0), double* getelementptr inbounds ([16000 x double], [16000 x double]* @Z, i64 0, i64 0), double* getelementptr inbounds ([16000 x double], [16000 x double]* @U, i64 0, i64 0), double* getelementptr inbounds ([16000 x double], [16000 x double]* @V, i64 0, i64 0), [256 x double]* getelementptr inbounds ([256 x [256 x double]], [256 x [256 x double]]* @aa, i64 0, i64 0), [256 x double]* getelementptr inbounds ([256 x [256 x double]], [256 x [256 x double]]* @bb, i64 0, i64 0), [256 x double]* getelementptr inbounds ([256 x [256 x double]], [256 x [256 x double]]* @cc, i64 0, i64 0), double 0.000000e+00) nounwind
   %inc9 = add nsw i32 %nl.018, 1
   %exitcond = icmp eq i32 %inc9, 400000
   br i1 %exitcond, label %for.end10, label %for.cond2.preheader
@@ -87,7 +87,7 @@ for.end10:                                        ; preds = %for.end
   %sub = sub nsw i64 %call11, %call1
   %conv = sitofp i64 %sub to double
   %div = fdiv double %conv, 1.000000e+06
-  %call12 = tail call signext i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str137, i64 0, i64 0), double %div) nounwind
+  %call12 = tail call signext i32 (i8*, ...) @printf(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str137, i64 0, i64 0), double %div) nounwind
   tail call void @check(i32 signext 1)
   ret i32 0
 }
diff --git a/test/CodeGen/PowerPC/sdag-ppcf128.ll b/test/CodeGen/PowerPC/sdag-ppcf128.ll
index c46bc6b22dde..6d2a04c72936 100644
--- a/test/CodeGen/PowerPC/sdag-ppcf128.ll
+++ b/test/CodeGen/PowerPC/sdag-ppcf128.ll
@@ -5,7 +5,7 @@
 define fastcc void @_D3std4math4sqrtFNaNbNfcZc() {
 entry:
   br i1 undef, label %if, label %else
-; CHECK: cmplwi 0, 3, 0
+; CHECK: cmplwi 3, 0
 if:                                               ; preds = %entry
   store { ppc_fp128, ppc_fp128 } zeroinitializer, { ppc_fp128, ppc_fp128 }* undef
   ret void
diff --git a/test/CodeGen/PowerPC/seteq-0.ll b/test/CodeGen/PowerPC/seteq-0.ll
index b7dd78085eb1..4afb8fee1776 100644
--- a/test/CodeGen/PowerPC/seteq-0.ll
+++ b/test/CodeGen/PowerPC/seteq-0.ll
@@ -5,7 +5,7 @@ define i32 @eq0(i32 %a) {
         %tmp.2 = zext i1 %tmp.1 to i32          ; <i32> [#uses=1]
         ret i32 %tmp.2
 
-; CHECK: cntlzw [[REG:r[0-9]+]], r3
+; CHECK: cntlz [[REG:r[0-9]+]], r3
 ; CHECK: rlwinm r3, [[REG]], 27, 31, 31
 ; CHECK: blr
 }
diff --git a/test/CodeGen/PowerPC/sjlj.ll b/test/CodeGen/PowerPC/sjlj.ll
index f9f887af31f3..62403e711968 100644
--- a/test/CodeGen/PowerPC/sjlj.ll
+++ b/test/CodeGen/PowerPC/sjlj.ll
@@ -37,7 +37,7 @@ entry:
   %0 = call i8* @llvm.frameaddress(i32 0)
   store i8* %0, i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**)
   %1 = call i8* @llvm.stacksave()
-  store i8* %1, i8** getelementptr (i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**), i32 2)
+  store i8* %1, i8** getelementptr (i8*, i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**), i32 2)
   %2 = call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8*))
   %tobool = icmp ne i32 %2, 0
   br i1 %tobool, label %if.then, label %if.else
@@ -55,7 +55,7 @@ if.end:                                           ; preds = %if.else
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
-  %3 = load i32* %retval
+  %3 = load i32, i32* %retval
   ret i32 %3
 
 ; FIXME: We should be saving VRSAVE on Darwin, but we're not!
@@ -110,7 +110,7 @@ entry:
   %0 = call i8* @llvm.frameaddress(i32 0)
   store i8* %0, i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**)
   %1 = call i8* @llvm.stacksave()
-  store i8* %1, i8** getelementptr (i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**), i32 2)
+  store i8* %1, i8** getelementptr (i8*, i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**), i32 2)
   %2 = call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8*))
   %tobool = icmp ne i32 %2, 0
   br i1 %tobool, label %if.then, label %if.else
@@ -128,7 +128,7 @@ if.end:                                           ; preds = %if.else
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
-  %3 = load i32* %retval
+  %3 = load i32, i32* %retval
   ret i32 %3
 
 ; CHECK: @main2
diff --git a/test/CodeGen/PowerPC/small-arguments.ll b/test/CodeGen/PowerPC/small-arguments.ll
index 19ca0985eef1..3cef817689b3 100644
--- a/test/CodeGen/PowerPC/small-arguments.ll
+++ b/test/CodeGen/PowerPC/small-arguments.ll
@@ -26,14 +26,14 @@ UnifiedReturnBlock:
 }
 
 define i32 @test4(i16* %P) {
-        %tmp.1 = load i16* %P
+        %tmp.1 = load i16, i16* %P
         %tmp.2 = zext i16 %tmp.1 to i32
         %tmp.3 = and i32 %tmp.2, 255
         ret i32 %tmp.3
 }
 
 define i32 @test5(i16* %P) {
-        %tmp.1 = load i16* %P
+        %tmp.1 = load i16, i16* %P
         %tmp.2 = bitcast i16 %tmp.1 to i16
         %tmp.3 = zext i16 %tmp.2 to i32
         %tmp.4 = and i32 %tmp.3, 255
@@ -41,7 +41,7 @@ define i32 @test5(i16* %P) {
 }
 
 define i32 @test6(i32* %P) {
-        %tmp.1 = load i32* %P
+        %tmp.1 = load i32, i32* %P
         %tmp.2 = and i32 %tmp.1, 255
         ret i32 %tmp.2
 }
diff --git a/test/CodeGen/PowerPC/split-index-tc.ll b/test/CodeGen/PowerPC/split-index-tc.ll
index 03aff243b231..38be93f28a85 100644
--- a/test/CodeGen/PowerPC/split-index-tc.ll
+++ b/test/CodeGen/PowerPC/split-index-tc.ll
@@ -13,16 +13,16 @@ define void @_ZN4llvm17ScheduleDAGInstrs14addPhysRegDepsEPNS_5SUnitEj() #0 align
 ; CHECK-NOT: lhzu
 
 entry:
-  %0 = load %"class.llvm::MachineOperand"** undef, align 8
+  %0 = load %"class.llvm::MachineOperand"*, %"class.llvm::MachineOperand"** undef, align 8
   br i1 undef, label %_ZNK4llvm14MachineOperand6getRegEv.exit, label %cond.false.i123
 
 cond.false.i123:                                  ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit
   unreachable
 
 _ZNK4llvm14MachineOperand6getRegEv.exit:          ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit
-  %IsDef.i = getelementptr inbounds %"class.llvm::MachineOperand"* %0, i64 undef, i32 1
+  %IsDef.i = getelementptr inbounds %"class.llvm::MachineOperand", %"class.llvm::MachineOperand"* %0, i64 undef, i32 1
   %1 = bitcast [3 x i8]* %IsDef.i to i24*
-  %bf.load.i = load i24* %1, align 1
+  %bf.load.i = load i24, i24* %1, align 1
   %2 = and i24 %bf.load.i, 128
   br i1 undef, label %for.cond.cleanup, label %for.body.lr.ph
 
@@ -61,7 +61,7 @@ cond.false.i257:                                  ; preds = %if.end55
   unreachable
 
 _ZNK4llvm14MachineOperand6isDeadEv.exit262:       ; preds = %if.end55
-  %bf.load.i259 = load i24* %1, align 1
+  %bf.load.i259 = load i24, i24* %1, align 1
   br i1 undef, label %if.then57, label %if.else59
 
 if.then57:                                        ; preds = %_ZNK4llvm14MachineOperand6isDeadEv.exit262
diff --git a/test/CodeGen/PowerPC/stack-protector.ll b/test/CodeGen/PowerPC/stack-protector.ll
index b81d94181cdf..8d255bd9a43b 100644
--- a/test/CodeGen/PowerPC/stack-protector.ll
+++ b/test/CodeGen/PowerPC/stack-protector.ll
@@ -11,10 +11,10 @@ entry:
   %"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store i8* %a, i8** %a_addr
 	%buf1 = bitcast [8 x i8]* %buf to i8*		; <i8*> [#uses=1]
-	%0 = load i8** %a_addr, align 4		; <i8*> [#uses=1]
+	%0 = load i8*, i8** %a_addr, align 4		; <i8*> [#uses=1]
 	%1 = call i8* @strcpy(i8* %buf1, i8* %0) nounwind		; <i8*> [#uses=0]
   %buf2 = bitcast [8 x i8]* %buf to i8*		; <i8*> [#uses=1]
-	%2 = call i32 (i8*, ...)* @printf(i8* getelementptr ([11 x i8]* @"\01LC", i32 0, i32 0), i8* %buf2) nounwind		; <i32> [#uses=0]
+	%2 = call i32 (i8*, ...) @printf(i8* getelementptr ([11 x i8], [11 x i8]* @"\01LC", i32 0, i32 0), i8* %buf2) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
diff --git a/test/CodeGen/PowerPC/stack-realign.ll b/test/CodeGen/PowerPC/stack-realign.ll
index 762f50a9cbe0..e91b563af72e 100644
--- a/test/CodeGen/PowerPC/stack-realign.ll
+++ b/test/CodeGen/PowerPC/stack-realign.ll
@@ -14,14 +14,14 @@ declare void @bar(i32*)
 define void @goo(%struct.s* byval nocapture readonly %a) {
 entry:
   %x = alloca [2 x i32], align 32
-  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
-  %0 = load i32* %a1, align 4
-  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
+  %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0
+  %0 = load i32, i32* %a1, align 4
+  %arrayidx = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 0
   store i32 %0, i32* %arrayidx, align 32
-  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
-  %1 = load i32* %b, align 4
-  %2 = load i32* @barbaz, align 4
-  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
+  %b = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 1
+  %1 = load i32, i32* %b, align 4
+  %2 = load i32, i32* @barbaz, align 4
+  %arrayidx2 = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 1
   store i32 %2, i32* %arrayidx2, align 4
   call void @bar(i32* %arrayidx)
   ret void
@@ -30,7 +30,7 @@ entry:
 ; CHECK-LABEL: @goo
 
 ; CHECK-DAG: mflr 0
-; CHECK-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59
+; CHECK-DAG: clrldi [[REG:[0-9]+]], 1, 59
 ; CHECK-DAG: std 30, -16(1)
 ; CHECK-DAG: mr 30, 1
 ; CHECK-DAG: std 0, 16(1)
@@ -52,7 +52,7 @@ entry:
 ; CHECK-FP-LABEL: @goo
 
 ; CHECK-FP-DAG: mflr 0
-; CHECK-FP-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59
+; CHECK-FP-DAG: clrldi [[REG:[0-9]+]], 1, 59
 ; CHECK-FP-DAG: std 31, -8(1)
 ; CHECK-FP-DAG: std 30, -16(1)
 ; CHECK-FP-DAG: mr 30, 1
@@ -78,7 +78,7 @@ entry:
 
 ; CHECK-32-LABEL: @goo
 ; CHECK-32-DAG: mflr 0
-; CHECK-32-DAG: rlwinm [[REG:[0-9]+]], 1, 0, 27, 31
+; CHECK-32-DAG: clrlwi [[REG:[0-9]+]], 1, 27
 ; CHECK-32-DAG: stw 30, -8(1)
 ; CHECK-32-DAG: mr 30, 1
 ; CHECK-32-DAG: stw 0, 4(1)
@@ -87,7 +87,7 @@ entry:
 
 ; CHECK-32-PIC-LABEL: @goo
 ; CHECK-32-PIC-DAG: mflr 0
-; CHECK-32-PIC-DAG: rlwinm [[REG:[0-9]+]], 1, 0, 27, 31
+; CHECK-32-PIC-DAG: clrlwi [[REG:[0-9]+]], 1, 27
 ; CHECK-32-PIC-DAG: stw 29, -12(1)
 ; CHECK-32-PIC-DAG: mr 29, 1
 ; CHECK-32-PIC-DAG: stw 0, 4(1)
@@ -98,13 +98,13 @@ entry:
 define void @hoo(%struct.s* byval nocapture readonly %a) {
 entry:
   %x = alloca [200000 x i32], align 32
-  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
-  %0 = load i32* %a1, align 4
-  %arrayidx = getelementptr inbounds [200000 x i32]* %x, i64 0, i64 0
+  %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0
+  %0 = load i32, i32* %a1, align 4
+  %arrayidx = getelementptr inbounds [200000 x i32], [200000 x i32]* %x, i64 0, i64 0
   store i32 %0, i32* %arrayidx, align 32
-  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
-  %1 = load i32* %b, align 4
-  %arrayidx2 = getelementptr inbounds [200000 x i32]* %x, i64 0, i64 1
+  %b = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 1
+  %1 = load i32, i32* %b, align 4
+  %arrayidx2 = getelementptr inbounds [200000 x i32], [200000 x i32]* %x, i64 0, i64 1
   store i32 %1, i32* %arrayidx2, align 4
   call void @bar(i32* %arrayidx)
   ret void
@@ -113,7 +113,7 @@ entry:
 ; CHECK-LABEL: @hoo
 
 ; CHECK-DAG: lis [[REG1:[0-9]+]], -13
-; CHECK-DAG: rldicl [[REG3:[0-9]+]], 1, 0, 59
+; CHECK-DAG: clrldi [[REG3:[0-9]+]], 1, 59
 ; CHECK-DAG: mflr 0
 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51808
 ; CHECK-DAG: std 30, -16(1)
@@ -129,7 +129,7 @@ entry:
 ; CHECK-32-LABEL: @hoo
 
 ; CHECK-32-DAG: lis [[REG1:[0-9]+]], -13
-; CHECK-32-DAG: rlwinm [[REG3:[0-9]+]], 1, 0, 27, 31
+; CHECK-32-DAG: clrlwi [[REG3:[0-9]+]], 1, 27
 ; CHECK-32-DAG: mflr 0
 ; CHECK-32-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
 ; CHECK-32-DAG: stw 30, -8(1)
@@ -143,7 +143,7 @@ entry:
 ; CHECK-32-PIC-LABEL: @hoo
 
 ; CHECK-32-PIC-DAG: lis [[REG1:[0-9]+]], -13
-; CHECK-32-PIC-DAG: rlwinm [[REG3:[0-9]+]], 1, 0, 27, 31
+; CHECK-32-PIC-DAG: clrlwi [[REG3:[0-9]+]], 1, 27
 ; CHECK-32-PIC-DAG: mflr 0
 ; CHECK-32-PIC-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
 ; CHECK-32-PIC-DAG: stw 29, -12(1)
@@ -159,13 +159,13 @@ entry:
 define void @loo(%struct.s* byval nocapture readonly %a) {
 entry:
   %x = alloca [2 x i32], align 32
-  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
-  %0 = load i32* %a1, align 4
-  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
+  %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0
+  %0 = load i32, i32* %a1, align 4
+  %arrayidx = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 0
   store i32 %0, i32* %arrayidx, align 32
-  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
-  %1 = load i32* %b, align 4
-  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
+  %b = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 1
+  %1 = load i32, i32* %b, align 4
+  %arrayidx2 = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 1
   store i32 %1, i32* %arrayidx2, align 4
   call void @bar(i32* %arrayidx)
   call void asm sideeffect "", "~{f30}"() nounwind
@@ -175,7 +175,7 @@ entry:
 ; CHECK-LABEL: @loo
 
 ; CHECK-DAG: mflr 0
-; CHECK-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59
+; CHECK-DAG: clrldi [[REG:[0-9]+]], 1, 59
 ; CHECK-DAG: std 30, -32(1)
 ; CHECK-DAG: mr 30, 1
 ; CHECK-DAG: std 0, 16(1)
@@ -191,7 +191,7 @@ entry:
 ; CHECK-FP-LABEL: @loo
 
 ; CHECK-FP-DAG: mflr 0
-; CHECK-FP-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59
+; CHECK-FP-DAG: clrldi [[REG:[0-9]+]], 1, 59
 ; CHECK-FP-DAG: std 31, -24(1)
 ; CHECK-FP-DAG: std 30, -32(1)
 ; CHECK-FP-DAG: mr 30, 1
diff --git a/test/CodeGen/PowerPC/std-unal-fi.ll b/test/CodeGen/PowerPC/std-unal-fi.ll
index 8b9606e1624f..74ea8cd373bd 100644
--- a/test/CodeGen/PowerPC/std-unal-fi.ll
+++ b/test/CodeGen/PowerPC/std-unal-fi.ll
@@ -9,7 +9,7 @@ BB:
   br label %CF
 
 CF:                                               ; preds = %CF80, %CF, %BB
-  %L5 = load i64* undef
+  %L5 = load i64, i64* undef
   store i8 %0, i8* %A4
   %Shuff7 = shufflevector <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> %Shuff, <16 x i32> <i32 28, i32 30, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 undef, i32 20, i32 22, i32 24, i32 26>
   %PC10 = bitcast i8* %A4 to ppc_fp128*
@@ -19,13 +19,13 @@ CF77:                                             ; preds = %CF81, %CF83, %CF77,
   br i1 undef, label %CF77, label %CF82
 
 CF82:                                             ; preds = %CF82, %CF77
-  %L19 = load i64* undef
+  %L19 = load i64, i64* undef
   store <1 x ppc_fp128> zeroinitializer, <1 x ppc_fp128>* %A
   store i8 -65, i8* %A4
   br i1 undef, label %CF82, label %CF83
 
 CF83:                                             ; preds = %CF82
-  %L34 = load i64* undef
+  %L34 = load i64, i64* undef
   br i1 undef, label %CF77, label %CF81
 
 CF81:                                             ; preds = %CF83
@@ -54,7 +54,7 @@ define void @autogen_SD88042(i8*, i32*, i8) {
 BB:
   %A4 = alloca <2 x i1>
   %A = alloca <16 x float>
-  %L = load i8* %0
+  %L = load i8, i8* %0
   %Sl = select i1 false, <16 x float>* %A, <16 x float>* %A
   %PC = bitcast <2 x i1>* %A4 to i64*
   %Sl27 = select i1 false, i8 undef, i8 %L
@@ -66,7 +66,7 @@ CF:                                               ; preds = %CF78, %CF, %BB
 
 CF77:                                             ; preds = %CF80, %CF77, %CF
   store <16 x float> zeroinitializer, <16 x float>* %Sl
-  %L58 = load i32* %PC33
+  %L58 = load i32, i32* %PC33
   store i8 0, i8* %0
   br i1 undef, label %CF77, label %CF80
 
@@ -90,7 +90,7 @@ BB:
   %A1 = alloca i1
   %I8 = insertelement <1 x i32> <i32 -1>, i32 454855, i32 0
   %Cmp = icmp ult <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, undef
-  %L10 = load i64* %2
+  %L10 = load i64, i64* %2
   %E11 = extractelement <4 x i1> %Cmp, i32 2
   br label %CF72
 
@@ -103,7 +103,7 @@ CF72:                                             ; preds = %CF74, %CF72, %BB
 CF74:                                             ; preds = %CF72
   store i8 0, i8* %0
   %PC = bitcast i1* %A1 to i64*
-  %L31 = load i64* %PC
+  %L31 = load i64, i64* %PC
   store i64 477323, i64* %PC
   %Sl37 = select i1 false, i32* undef, i32* %1
   %Cmp38 = icmp ugt i1 undef, undef
diff --git a/test/CodeGen/PowerPC/stdux-constuse.ll b/test/CodeGen/PowerPC/stdux-constuse.ll
index e62d438014ee..d4d17956868a 100644
--- a/test/CodeGen/PowerPC/stdux-constuse.ll
+++ b/test/CodeGen/PowerPC/stdux-constuse.ll
@@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define i32 @test1(i64 %add, i64* %ptr) nounwind {
 entry:
-  %p1 = getelementptr i64* %ptr, i64 144115188075855
+  %p1 = getelementptr i64, i64* %ptr, i64 144115188075855
   br label %for.cond2.preheader
 
 for.cond2.preheader:
@@ -14,10 +14,10 @@ for.cond2.preheader:
 for.body4:
   %lsr.iv = phi i32 [ %lsr.iv.next, %for.body4 ], [ 16000, %for.cond2.preheader ]
   %i0 = phi i64* [ %p1, %for.cond2.preheader ], [ %i6, %for.body4 ]
-  %i6 = getelementptr i64* %i0, i64 400000
-  %i7 = getelementptr i64* %i6, i64 300000
-  %i8 = getelementptr i64* %i6, i64 200000
-  %i9 = getelementptr i64* %i6, i64 100000
+  %i6 = getelementptr i64, i64* %i0, i64 400000
+  %i7 = getelementptr i64, i64* %i6, i64 300000
+  %i8 = getelementptr i64, i64* %i6, i64 200000
+  %i9 = getelementptr i64, i64* %i6, i64 100000
   store i64 %add, i64* %i6, align 32
   store i64 %add, i64* %i7, align 32
   store i64 %add, i64* %i8, align 32
diff --git a/test/CodeGen/PowerPC/stfiwx.ll b/test/CodeGen/PowerPC/stfiwx.ll
index 588e44fb28d3..5f90dcad032d 100644
--- a/test/CodeGen/PowerPC/stfiwx.ll
+++ b/test/CodeGen/PowerPC/stfiwx.ll
@@ -22,8 +22,8 @@ define void @test1(float %a, i32* %b) nounwind {
 define void @test2(float %a, i32* %b, i32 %i) nounwind {
 ; CHECK-LABEL: @test2
 ; CHECK-LS-LABEL: @test2
-        %tmp.2 = getelementptr i32* %b, i32 1           ; <i32*> [#uses=1]
-        %tmp.5 = getelementptr i32* %b, i32 %i          ; <i32*> [#uses=1]
+        %tmp.2 = getelementptr i32, i32* %b, i32 1           ; <i32*> [#uses=1]
+        %tmp.5 = getelementptr i32, i32* %b, i32 %i          ; <i32*> [#uses=1]
         %tmp.7 = fptosi float %a to i32         ; <i32> [#uses=3]
         store i32 %tmp.7, i32* %tmp.5
         store i32 %tmp.7, i32* %tmp.2
diff --git a/test/CodeGen/PowerPC/store-load-fwd.ll b/test/CodeGen/PowerPC/store-load-fwd.ll
index 25663c1ac68e..62dd79ec18a4 100644
--- a/test/CodeGen/PowerPC/store-load-fwd.ll
+++ b/test/CodeGen/PowerPC/store-load-fwd.ll
@@ -2,7 +2,7 @@
 
 define i32 @test(i32* %P) {
         store i32 1, i32* %P
-        %V = load i32* %P               ; <i32> [#uses=1]
+        %V = load i32, i32* %P               ; <i32> [#uses=1]
         ret i32 %V
 }
 
diff --git a/test/CodeGen/PowerPC/store-update.ll b/test/CodeGen/PowerPC/store-update.ll
index 7b9e8f720a17..65f052869702 100644
--- a/test/CodeGen/PowerPC/store-update.ll
+++ b/test/CodeGen/PowerPC/store-update.ll
@@ -5,7 +5,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define i8* @test_stbu(i8* %base, i8 zeroext %val) nounwind {
 entry:
-  %arrayidx = getelementptr inbounds i8* %base, i64 16
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 16
   store i8 %val, i8* %arrayidx, align 1
   ret i8* %arrayidx
 }
@@ -16,7 +16,7 @@ entry:
 
 define i8* @test_stbux(i8* %base, i8 zeroext %val, i64 %offset) nounwind {
 entry:
-  %arrayidx = getelementptr inbounds i8* %base, i64 %offset
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %offset
   store i8 %val, i8* %arrayidx, align 1
   ret i8* %arrayidx
 }
@@ -27,7 +27,7 @@ entry:
 
 define i16* @test_sthu(i16* %base, i16 zeroext %val) nounwind {
 entry:
-  %arrayidx = getelementptr inbounds i16* %base, i64 16
+  %arrayidx = getelementptr inbounds i16, i16* %base, i64 16
   store i16 %val, i16* %arrayidx, align 2
   ret i16* %arrayidx
 }
@@ -38,7 +38,7 @@ entry:
 
 define i16* @test_sthux(i16* %base, i16 zeroext %val, i64 %offset) nounwind {
 entry:
-  %arrayidx = getelementptr inbounds i16* %base, i64 %offset
+  %arrayidx = getelementptr inbounds i16, i16* %base, i64 %offset
   store i16 %val, i16* %arrayidx, align 2
   ret i16* %arrayidx
 }
@@ -50,7 +50,7 @@ entry:
 
 define i32* @test_stwu(i32* %base, i32 zeroext %val) nounwind {
 entry:
-  %arrayidx = getelementptr inbounds i32* %base, i64 16
+  %arrayidx = getelementptr inbounds i32, i32* %base, i64 16
   store i32 %val, i32* %arrayidx, align 4
   ret i32* %arrayidx
 }
@@ -61,7 +61,7 @@ entry:
 
 define i32* @test_stwux(i32* %base, i32 zeroext %val, i64 %offset) nounwind {
 entry:
-  %arrayidx = getelementptr inbounds i32* %base, i64 %offset
+  %arrayidx = getelementptr inbounds i32, i32* %base, i64 %offset
   store i32 %val, i32* %arrayidx, align 4
   ret i32* %arrayidx
 }
@@ -74,7 +74,7 @@ entry:
 define i8* @test_stbu8(i8* %base, i64 %val) nounwind {
 entry:
   %conv = trunc i64 %val to i8
-  %arrayidx = getelementptr inbounds i8* %base, i64 16
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 16
   store i8 %conv, i8* %arrayidx, align 1
   ret i8* %arrayidx
 }
@@ -86,7 +86,7 @@ entry:
 define i8* @test_stbux8(i8* %base, i64 %val, i64 %offset) nounwind {
 entry:
   %conv = trunc i64 %val to i8
-  %arrayidx = getelementptr inbounds i8* %base, i64 %offset
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %offset
   store i8 %conv, i8* %arrayidx, align 1
   ret i8* %arrayidx
 }
@@ -98,7 +98,7 @@ entry:
 define i16* @test_sthu8(i16* %base, i64 %val) nounwind {
 entry:
   %conv = trunc i64 %val to i16
-  %arrayidx = getelementptr inbounds i16* %base, i64 16
+  %arrayidx = getelementptr inbounds i16, i16* %base, i64 16
   store i16 %conv, i16* %arrayidx, align 2
   ret i16* %arrayidx
 }
@@ -110,7 +110,7 @@ entry:
 define i16* @test_sthux8(i16* %base, i64 %val, i64 %offset) nounwind {
 entry:
   %conv = trunc i64 %val to i16
-  %arrayidx = getelementptr inbounds i16* %base, i64 %offset
+  %arrayidx = getelementptr inbounds i16, i16* %base, i64 %offset
   store i16 %conv, i16* %arrayidx, align 2
   ret i16* %arrayidx
 }
@@ -123,7 +123,7 @@ entry:
 define i32* @test_stwu8(i32* %base, i64 %val) nounwind {
 entry:
   %conv = trunc i64 %val to i32
-  %arrayidx = getelementptr inbounds i32* %base, i64 16
+  %arrayidx = getelementptr inbounds i32, i32* %base, i64 16
   store i32 %conv, i32* %arrayidx, align 4
   ret i32* %arrayidx
 }
@@ -135,7 +135,7 @@ entry:
 define i32* @test_stwux8(i32* %base, i64 %val, i64 %offset) nounwind {
 entry:
   %conv = trunc i64 %val to i32
-  %arrayidx = getelementptr inbounds i32* %base, i64 %offset
+  %arrayidx = getelementptr inbounds i32, i32* %base, i64 %offset
   store i32 %conv, i32* %arrayidx, align 4
   ret i32* %arrayidx
 }
@@ -147,7 +147,7 @@ entry:
 
 define i64* @test_stdu(i64* %base, i64 %val) nounwind {
 entry:
-  %arrayidx = getelementptr inbounds i64* %base, i64 16
+  %arrayidx = getelementptr inbounds i64, i64* %base, i64 16
   store i64 %val, i64* %arrayidx, align 8
   ret i64* %arrayidx
 }
@@ -158,7 +158,7 @@ entry:
 
 define i64* @test_stdux(i64* %base, i64 %val, i64 %offset) nounwind {
 entry:
-  %arrayidx = getelementptr inbounds i64* %base, i64 %offset
+  %arrayidx = getelementptr inbounds i64, i64* %base, i64 %offset
   store i64 %val, i64* %arrayidx, align 8
   ret i64* %arrayidx
 }
diff --git a/test/CodeGen/PowerPC/structsinmem.ll b/test/CodeGen/PowerPC/structsinmem.ll
index b5552af0eb51..bfada4c63714 100644
--- a/test/CodeGen/PowerPC/structsinmem.ll
+++ b/test/CodeGen/PowerPC/structsinmem.ll
@@ -43,7 +43,7 @@ entry:
   %p6 = alloca %struct.s6, align 4
   %p7 = alloca %struct.s7, align 4
   %0 = bitcast %struct.s1* %p1 to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* getelementptr inbounds (%struct.s1* @caller1.p1, i32 0, i32 0), i64 1, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* getelementptr inbounds (%struct.s1, %struct.s1* @caller1.p1, i32 0, i32 0), i64 1, i32 1, i1 false)
   %1 = bitcast %struct.s2* %p2 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast (%struct.s2* @caller1.p2 to i8*), i64 2, i32 2, i1 false)
   %2 = bitcast %struct.s3* %p3 to i8*
@@ -88,28 +88,28 @@ entry:
   store i32 %z6, i32* %z6.addr, align 4
   store i32 %z7, i32* %z7.addr, align 4
   store i32 %z8, i32* %z8.addr, align 4
-  %a = getelementptr inbounds %struct.s1* %v1, i32 0, i32 0
-  %0 = load i8* %a, align 1
+  %a = getelementptr inbounds %struct.s1, %struct.s1* %v1, i32 0, i32 0
+  %0 = load i8, i8* %a, align 1
   %conv = zext i8 %0 to i32
-  %a1 = getelementptr inbounds %struct.s2* %v2, i32 0, i32 0
-  %1 = load i16* %a1, align 2
+  %a1 = getelementptr inbounds %struct.s2, %struct.s2* %v2, i32 0, i32 0
+  %1 = load i16, i16* %a1, align 2
   %conv2 = sext i16 %1 to i32
   %add = add nsw i32 %conv, %conv2
-  %a3 = getelementptr inbounds %struct.s3* %v3, i32 0, i32 0
-  %2 = load i16* %a3, align 2
+  %a3 = getelementptr inbounds %struct.s3, %struct.s3* %v3, i32 0, i32 0
+  %2 = load i16, i16* %a3, align 2
   %conv4 = sext i16 %2 to i32
   %add5 = add nsw i32 %add, %conv4
-  %a6 = getelementptr inbounds %struct.s4* %v4, i32 0, i32 0
-  %3 = load i32* %a6, align 4
+  %a6 = getelementptr inbounds %struct.s4, %struct.s4* %v4, i32 0, i32 0
+  %3 = load i32, i32* %a6, align 4
   %add7 = add nsw i32 %add5, %3
-  %a8 = getelementptr inbounds %struct.s5* %v5, i32 0, i32 0
-  %4 = load i32* %a8, align 4
+  %a8 = getelementptr inbounds %struct.s5, %struct.s5* %v5, i32 0, i32 0
+  %4 = load i32, i32* %a8, align 4
   %add9 = add nsw i32 %add7, %4
-  %a10 = getelementptr inbounds %struct.s6* %v6, i32 0, i32 0
-  %5 = load i32* %a10, align 4
+  %a10 = getelementptr inbounds %struct.s6, %struct.s6* %v6, i32 0, i32 0
+  %5 = load i32, i32* %a10, align 4
   %add11 = add nsw i32 %add9, %5
-  %a12 = getelementptr inbounds %struct.s7* %v7, i32 0, i32 0
-  %6 = load i32* %a12, align 4
+  %a12 = getelementptr inbounds %struct.s7, %struct.s7* %v7, i32 0, i32 0
+  %6 = load i32, i32* %a12, align 4
   %add13 = add nsw i32 %add11, %6
   ret i32 %add13
 
@@ -132,7 +132,7 @@ entry:
   %p6 = alloca %struct.t6, align 1
   %p7 = alloca %struct.t7, align 1
   %0 = bitcast %struct.t1* %p1 to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* getelementptr inbounds (%struct.t1* @caller2.p1, i32 0, i32 0), i64 1, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* getelementptr inbounds (%struct.t1, %struct.t1* @caller2.p1, i32 0, i32 0), i64 1, i32 1, i1 false)
   %1 = bitcast %struct.t2* %p2 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast ({ i16 }* @caller2.p2 to i8*), i64 2, i32 1, i1 false)
   %2 = bitcast %struct.t3* %p3 to i8*
@@ -180,28 +180,28 @@ entry:
   store i32 %z6, i32* %z6.addr, align 4
   store i32 %z7, i32* %z7.addr, align 4
   store i32 %z8, i32* %z8.addr, align 4
-  %a = getelementptr inbounds %struct.t1* %v1, i32 0, i32 0
-  %0 = load i8* %a, align 1
+  %a = getelementptr inbounds %struct.t1, %struct.t1* %v1, i32 0, i32 0
+  %0 = load i8, i8* %a, align 1
   %conv = zext i8 %0 to i32
-  %a1 = getelementptr inbounds %struct.t2* %v2, i32 0, i32 0
-  %1 = load i16* %a1, align 1
+  %a1 = getelementptr inbounds %struct.t2, %struct.t2* %v2, i32 0, i32 0
+  %1 = load i16, i16* %a1, align 1
   %conv2 = sext i16 %1 to i32
   %add = add nsw i32 %conv, %conv2
-  %a3 = getelementptr inbounds %struct.t3* %v3, i32 0, i32 0
-  %2 = load i16* %a3, align 1
+  %a3 = getelementptr inbounds %struct.t3, %struct.t3* %v3, i32 0, i32 0
+  %2 = load i16, i16* %a3, align 1
   %conv4 = sext i16 %2 to i32
   %add5 = add nsw i32 %add, %conv4
-  %a6 = getelementptr inbounds %struct.t4* %v4, i32 0, i32 0
-  %3 = load i32* %a6, align 1
+  %a6 = getelementptr inbounds %struct.t4, %struct.t4* %v4, i32 0, i32 0
+  %3 = load i32, i32* %a6, align 1
   %add7 = add nsw i32 %add5, %3
-  %a8 = getelementptr inbounds %struct.t5* %v5, i32 0, i32 0
-  %4 = load i32* %a8, align 1
+  %a8 = getelementptr inbounds %struct.t5, %struct.t5* %v5, i32 0, i32 0
+  %4 = load i32, i32* %a8, align 1
   %add9 = add nsw i32 %add7, %4
-  %a10 = getelementptr inbounds %struct.t6* %v6, i32 0, i32 0
-  %5 = load i32* %a10, align 1
+  %a10 = getelementptr inbounds %struct.t6, %struct.t6* %v6, i32 0, i32 0
+  %5 = load i32, i32* %a10, align 1
   %add11 = add nsw i32 %add9, %5
-  %a12 = getelementptr inbounds %struct.t7* %v7, i32 0, i32 0
-  %6 = load i32* %a12, align 1
+  %a12 = getelementptr inbounds %struct.t7, %struct.t7* %v7, i32 0, i32 0
+  %6 = load i32, i32* %a12, align 1
   %add13 = add nsw i32 %add11, %6
   ret i32 %add13
 
diff --git a/test/CodeGen/PowerPC/structsinregs.ll b/test/CodeGen/PowerPC/structsinregs.ll
index cfe32e9560ae..0fb9895a6227 100644
--- a/test/CodeGen/PowerPC/structsinregs.ll
+++ b/test/CodeGen/PowerPC/structsinregs.ll
@@ -43,7 +43,7 @@ entry:
   %p6 = alloca %struct.s6, align 4
   %p7 = alloca %struct.s7, align 4
   %0 = bitcast %struct.s1* %p1 to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* getelementptr inbounds (%struct.s1* @caller1.p1, i32 0, i32 0), i64 1, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* getelementptr inbounds (%struct.s1, %struct.s1* @caller1.p1, i32 0, i32 0), i64 1, i32 1, i1 false)
   %1 = bitcast %struct.s2* %p2 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast (%struct.s2* @caller1.p2 to i8*), i64 2, i32 2, i1 false)
   %2 = bitcast %struct.s3* %p3 to i8*
@@ -72,28 +72,28 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
 
 define internal i32 @callee1(%struct.s1* byval %v1, %struct.s2* byval %v2, %struct.s3* byval %v3, %struct.s4* byval %v4, %struct.s5* byval %v5, %struct.s6* byval %v6, %struct.s7* byval %v7) nounwind {
 entry:
-  %a = getelementptr inbounds %struct.s1* %v1, i32 0, i32 0
-  %0 = load i8* %a, align 1
+  %a = getelementptr inbounds %struct.s1, %struct.s1* %v1, i32 0, i32 0
+  %0 = load i8, i8* %a, align 1
   %conv = zext i8 %0 to i32
-  %a1 = getelementptr inbounds %struct.s2* %v2, i32 0, i32 0
-  %1 = load i16* %a1, align 2
+  %a1 = getelementptr inbounds %struct.s2, %struct.s2* %v2, i32 0, i32 0
+  %1 = load i16, i16* %a1, align 2
   %conv2 = sext i16 %1 to i32
   %add = add nsw i32 %conv, %conv2
-  %a3 = getelementptr inbounds %struct.s3* %v3, i32 0, i32 0
-  %2 = load i16* %a3, align 2
+  %a3 = getelementptr inbounds %struct.s3, %struct.s3* %v3, i32 0, i32 0
+  %2 = load i16, i16* %a3, align 2
   %conv4 = sext i16 %2 to i32
   %add5 = add nsw i32 %add, %conv4
-  %a6 = getelementptr inbounds %struct.s4* %v4, i32 0, i32 0
-  %3 = load i32* %a6, align 4
+  %a6 = getelementptr inbounds %struct.s4, %struct.s4* %v4, i32 0, i32 0
+  %3 = load i32, i32* %a6, align 4
   %add7 = add nsw i32 %add5, %3
-  %a8 = getelementptr inbounds %struct.s5* %v5, i32 0, i32 0
-  %4 = load i32* %a8, align 4
+  %a8 = getelementptr inbounds %struct.s5, %struct.s5* %v5, i32 0, i32 0
+  %4 = load i32, i32* %a8, align 4
   %add9 = add nsw i32 %add7, %4
-  %a10 = getelementptr inbounds %struct.s6* %v6, i32 0, i32 0
-  %5 = load i32* %a10, align 4
+  %a10 = getelementptr inbounds %struct.s6, %struct.s6* %v6, i32 0, i32 0
+  %5 = load i32, i32* %a10, align 4
   %add11 = add nsw i32 %add9, %5
-  %a12 = getelementptr inbounds %struct.s7* %v7, i32 0, i32 0
-  %6 = load i32* %a12, align 4
+  %a12 = getelementptr inbounds %struct.s7, %struct.s7* %v7, i32 0, i32 0
+  %6 = load i32, i32* %a12, align 4
   %add13 = add nsw i32 %add11, %6
   ret i32 %add13
 
@@ -123,7 +123,7 @@ entry:
   %p6 = alloca %struct.t6, align 1
   %p7 = alloca %struct.t7, align 1
   %0 = bitcast %struct.t1* %p1 to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* getelementptr inbounds (%struct.t1* @caller2.p1, i32 0, i32 0), i64 1, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* getelementptr inbounds (%struct.t1, %struct.t1* @caller2.p1, i32 0, i32 0), i64 1, i32 1, i1 false)
   %1 = bitcast %struct.t2* %p2 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast ({ i16 }* @caller2.p2 to i8*), i64 2, i32 1, i1 false)
   %2 = bitcast %struct.t3* %p3 to i8*
@@ -159,28 +159,28 @@ entry:
 
 define internal i32 @callee2(%struct.t1* byval %v1, %struct.t2* byval %v2, %struct.t3* byval %v3, %struct.t4* byval %v4, %struct.t5* byval %v5, %struct.t6* byval %v6, %struct.t7* byval %v7) nounwind {
 entry:
-  %a = getelementptr inbounds %struct.t1* %v1, i32 0, i32 0
-  %0 = load i8* %a, align 1
+  %a = getelementptr inbounds %struct.t1, %struct.t1* %v1, i32 0, i32 0
+  %0 = load i8, i8* %a, align 1
   %conv = zext i8 %0 to i32
-  %a1 = getelementptr inbounds %struct.t2* %v2, i32 0, i32 0
-  %1 = load i16* %a1, align 1
+  %a1 = getelementptr inbounds %struct.t2, %struct.t2* %v2, i32 0, i32 0
+  %1 = load i16, i16* %a1, align 1
   %conv2 = sext i16 %1 to i32
   %add = add nsw i32 %conv, %conv2
-  %a3 = getelementptr inbounds %struct.t3* %v3, i32 0, i32 0
-  %2 = load i16* %a3, align 1
+  %a3 = getelementptr inbounds %struct.t3, %struct.t3* %v3, i32 0, i32 0
+  %2 = load i16, i16* %a3, align 1
   %conv4 = sext i16 %2 to i32
   %add5 = add nsw i32 %add, %conv4
-  %a6 = getelementptr inbounds %struct.t4* %v4, i32 0, i32 0
-  %3 = load i32* %a6, align 1
+  %a6 = getelementptr inbounds %struct.t4, %struct.t4* %v4, i32 0, i32 0
+  %3 = load i32, i32* %a6, align 1
   %add7 = add nsw i32 %add5, %3
-  %a8 = getelementptr inbounds %struct.t5* %v5, i32 0, i32 0
-  %4 = load i32* %a8, align 1
+  %a8 = getelementptr inbounds %struct.t5, %struct.t5* %v5, i32 0, i32 0
+  %4 = load i32, i32* %a8, align 1
   %add9 = add nsw i32 %add7, %4
-  %a10 = getelementptr inbounds %struct.t6* %v6, i32 0, i32 0
-  %5 = load i32* %a10, align 1
+  %a10 = getelementptr inbounds %struct.t6, %struct.t6* %v6, i32 0, i32 0
+  %5 = load i32, i32* %a10, align 1
   %add11 = add nsw i32 %add9, %5
-  %a12 = getelementptr inbounds %struct.t7* %v7, i32 0, i32 0
-  %6 = load i32* %a12, align 1
+  %a12 = getelementptr inbounds %struct.t7, %struct.t7* %v7, i32 0, i32 0
+  %6 = load i32, i32* %a12, align 1
   %add13 = add nsw i32 %add11, %6
   ret i32 %add13
 
diff --git a/test/CodeGen/PowerPC/stwu-gta.ll b/test/CodeGen/PowerPC/stwu-gta.ll
index 980c1d502853..2b420156f739 100644
--- a/test/CodeGen/PowerPC/stwu-gta.ll
+++ b/test/CodeGen/PowerPC/stwu-gta.ll
@@ -8,8 +8,8 @@ target triple = "powerpc-unknown-linux"
 
 define void @_GLOBAL__I_a() nounwind section ".text.startup" {
 entry:
-  store i32 5, i32* getelementptr inbounds (%class.Two.0.5* @foo, i32 0, i32 0), align 4
-  store i32 6, i32* getelementptr inbounds (%class.Two.0.5* @foo, i32 0, i32 1), align 4
+  store i32 5, i32* getelementptr inbounds (%class.Two.0.5, %class.Two.0.5* @foo, i32 0, i32 0), align 4
+  store i32 6, i32* getelementptr inbounds (%class.Two.0.5, %class.Two.0.5* @foo, i32 0, i32 1), align 4
   ret void
 }
 
diff --git a/test/CodeGen/PowerPC/stwu8.ll b/test/CodeGen/PowerPC/stwu8.ll
index b220af2df4a4..bb2748432d79 100644
--- a/test/CodeGen/PowerPC/stwu8.ll
+++ b/test/CodeGen/PowerPC/stwu8.ll
@@ -11,7 +11,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define void @test1(%class.spell_checker.21.103.513.538* %this) unnamed_addr align 2 {
 entry:
-  %_M_header.i.i.i.i.i.i = getelementptr inbounds %class.spell_checker.21.103.513.538* %this, i64 0, i32 0, i32 0, i32 0, i32 1
+  %_M_header.i.i.i.i.i.i = getelementptr inbounds %class.spell_checker.21.103.513.538, %class.spell_checker.21.103.513.538* %this, i64 0, i32 0, i32 0, i32 0, i32 1
   %0 = bitcast %"struct.std::_Rb_tree_node_base.17.99.509.534"* %_M_header.i.i.i.i.i.i to i8*
   call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 40, i32 4, i1 false) nounwind
   store %"struct.std::_Rb_tree_node_base.17.99.509.534"* %_M_header.i.i.i.i.i.i, %"struct.std::_Rb_tree_node_base.17.99.509.534"** undef, align 8
diff --git a/test/CodeGen/PowerPC/stwux.ll b/test/CodeGen/PowerPC/stwux.ll
index 737e9d9f0ecb..2ed630d8002d 100644
--- a/test/CodeGen/PowerPC/stwux.ll
+++ b/test/CodeGen/PowerPC/stwux.ll
@@ -27,7 +27,7 @@ while.end:                                        ; preds = %if.end12
 
 if.end15:                                         ; preds = %while.end
   %idxprom.i.i230 = sext i32 %i.1 to i64
-  %arrayidx18 = getelementptr inbounds [100 x i32]* @multvec_i, i64 0, i64 %idxprom.i.i230
+  %arrayidx18 = getelementptr inbounds [100 x i32], [100 x i32]* @multvec_i, i64 0, i64 %idxprom.i.i230
   store i32 0, i32* %arrayidx18, align 4
   br i1 undef, label %while.body21, label %while.end90
 
diff --git a/test/CodeGen/PowerPC/subreg-postra-2.ll b/test/CodeGen/PowerPC/subreg-postra-2.ll
index 2faaa6129294..051536443413 100644
--- a/test/CodeGen/PowerPC/subreg-postra-2.ll
+++ b/test/CodeGen/PowerPC/subreg-postra-2.ll
@@ -134,8 +134,8 @@ while.body392.lr.ph:                              ; preds = %do.body378
   br label %while.body392
 
 while.body392:                                    ; preds = %wait_on_buffer.exit1319, %while.body392.lr.ph
-  %0 = load i8** undef, align 8
-  %add.ptr399 = getelementptr inbounds i8* %0, i64 -72
+  %0 = load i8*, i8** undef, align 8
+  %add.ptr399 = getelementptr inbounds i8, i8* %0, i64 -72
   %b_state.i.i1314 = bitcast i8* %add.ptr399 to i64*
   %tobool.i1316 = icmp eq i64 undef, 0
   br i1 %tobool.i1316, label %wait_on_buffer.exit1319, label %if.then.i1317
@@ -144,7 +144,7 @@ if.then.i1317:                                    ; preds = %while.body392
   unreachable
 
 wait_on_buffer.exit1319:                          ; preds = %while.body392
-  %1 = load volatile i64* %b_state.i.i1314, align 8
+  %1 = load volatile i64, i64* %b_state.i.i1314, align 8
   %conv.i.i1322 = and i64 %1, 1
   %lnot404 = icmp eq i64 %conv.i.i1322, 0
   %.err.4 = select i1 %lnot404, i32 -5, i32 undef
@@ -160,7 +160,7 @@ while.end418:                                     ; preds = %wait_on_buffer.exit
 
 ; CHECK-LABEL: @jbd2_journal_commit_transaction
 ; CHECK: andi.
-; CHECK: cror [[REG:[0-9]+]], 1, 1
+; CHECK: crmove [[REG:[0-9]+]], 1
 ; CHECK: stdcx.
 ; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
 
diff --git a/test/CodeGen/PowerPC/subreg-postra.ll b/test/CodeGen/PowerPC/subreg-postra.ll
index b10fa668cb8d..ba1b967cf204 100644
--- a/test/CodeGen/PowerPC/subreg-postra.ll
+++ b/test/CodeGen/PowerPC/subreg-postra.ll
@@ -120,8 +120,8 @@ while.body392.lr.ph:                              ; preds = %do.body378
   br label %while.body392
 
 while.body392:                                    ; preds = %wait_on_buffer.exit1319, %while.body392.lr.ph
-  %0 = load i8** undef, align 8
-  %add.ptr399 = getelementptr inbounds i8* %0, i64 -72
+  %0 = load i8*, i8** undef, align 8
+  %add.ptr399 = getelementptr inbounds i8, i8* %0, i64 -72
   %b_state.i.i1314 = bitcast i8* %add.ptr399 to i64*
   %tobool.i1316 = icmp eq i64 undef, 0
   br i1 %tobool.i1316, label %wait_on_buffer.exit1319, label %if.then.i1317
@@ -130,20 +130,20 @@ if.then.i1317:                                    ; preds = %while.body392
   unreachable
 
 wait_on_buffer.exit1319:                          ; preds = %while.body392
-  %1 = load volatile i64* %b_state.i.i1314, align 8
+  %1 = load volatile i64, i64* %b_state.i.i1314, align 8
   %conv.i.i1322 = and i64 %1, 1
   %lnot404 = icmp eq i64 %conv.i.i1322, 0
   %.err.4 = select i1 %lnot404, i32 -5, i32 undef
   %2 = call i64 asm sideeffect "1:.long 0x7c0000a8 $| ((($0) & 0x1f) << 21) $| (((0) & 0x1f) << 16) $| ((($3) & 0x1f) << 11) $| (((0) & 0x1) << 0) \0Aandc $0,$0,$2\0Astdcx. $0,0,$3\0Abne- 1b\0A", "=&r,=*m,r,r,*m,~{cc},~{memory}"(i64* %b_state.i.i1314, i64 262144, i64* %b_state.i.i1314, i64* %b_state.i.i1314) #1
-  %prev.i.i.i1325 = getelementptr inbounds i8* %0, i64 8
-  %3 = load i32** null, align 8
+  %prev.i.i.i1325 = getelementptr inbounds i8, i8* %0, i64 8
+  %3 = load i32*, i32** null, align 8
   store i32* %3, i32** undef, align 8
   call void @__brelse(i32* undef) #1
   br i1 undef, label %while.end418, label %while.body392
 
 ; CHECK-LABEL: @jbd2_journal_commit_transaction
 ; CHECK: andi.
-; CHECK: cror [[REG:[0-9]+]], 1, 1
+; CHECK: crmove [[REG:[0-9]+]], 1
 ; CHECK: stdcx.
 ; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
 
diff --git a/test/CodeGen/PowerPC/subsumes-pred-regs.ll b/test/CodeGen/PowerPC/subsumes-pred-regs.ll
index c510e36cb413..5389c1318445 100644
--- a/test/CodeGen/PowerPC/subsumes-pred-regs.ll
+++ b/test/CodeGen/PowerPC/subsumes-pred-regs.ll
@@ -20,7 +20,7 @@ if.then:                                          ; preds = %lor.end
   br i1 undef, label %return, label %if.end.i24
 
 if.end.i24:                                       ; preds = %if.then
-  %0 = load i32* undef, align 4
+  %0 = load i32, i32* undef, align 4
   %lnot.i.i16.i23 = icmp eq i32 %0, 0
   br i1 %lnot.i.i16.i23, label %if.end7.i37, label %test.exit27.i34
 
diff --git a/test/CodeGen/PowerPC/swaps-le-1.ll b/test/CodeGen/PowerPC/swaps-le-1.ll
new file mode 100644
index 000000000000..0c4163169034
--- /dev/null
+++ b/test/CodeGen/PowerPC/swaps-le-1.ll
@@ -0,0 +1,147 @@
+; RUN: llc -O3 -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -O3 -mcpu=pwr8 -disable-ppc-vsx-swap-removal -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck -check-prefix=NOOPTSWAP %s
+
+; This test was generated from the following source:
+;
+; #define N 4096
+; int ca[N] __attribute__((aligned(16)));
+; int cb[N] __attribute__((aligned(16)));
+; int cc[N] __attribute__((aligned(16)));
+; int cd[N] __attribute__((aligned(16)));
+;
+; void foo ()
+; {
+;   int i;
+;   for (i = 0; i < N; i++) {
+;     ca[i] = (cb[i] + cc[i]) * cd[i];
+;   }
+; }
+
+@cb = common global [4096 x i32] zeroinitializer, align 16
+@cc = common global [4096 x i32] zeroinitializer, align 16
+@cd = common global [4096 x i32] zeroinitializer, align 16
+@ca = common global [4096 x i32] zeroinitializer, align 16
+
+define void @foo() {
+entry:
+  br label %vector.body
+
+vector.body:
+  %index = phi i64 [ 0, %entry ], [ %index.next.3, %vector.body ]
+  %0 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cb, i64 0, i64 %index
+  %1 = bitcast i32* %0 to <4 x i32>*
+  %wide.load = load <4 x i32>, <4 x i32>* %1, align 16
+  %2 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cc, i64 0, i64 %index
+  %3 = bitcast i32* %2 to <4 x i32>*
+  %wide.load13 = load <4 x i32>, <4 x i32>* %3, align 16
+  %4 = add nsw <4 x i32> %wide.load13, %wide.load
+  %5 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cd, i64 0, i64 %index
+  %6 = bitcast i32* %5 to <4 x i32>*
+  %wide.load14 = load <4 x i32>, <4 x i32>* %6, align 16
+  %7 = mul nsw <4 x i32> %4, %wide.load14
+  %8 = getelementptr inbounds [4096 x i32], [4096 x i32]* @ca, i64 0, i64 %index
+  %9 = bitcast i32* %8 to <4 x i32>*
+  store <4 x i32> %7, <4 x i32>* %9, align 16
+  %index.next = add nuw nsw i64 %index, 4
+  %10 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cb, i64 0, i64 %index.next
+  %11 = bitcast i32* %10 to <4 x i32>*
+  %wide.load.1 = load <4 x i32>, <4 x i32>* %11, align 16
+  %12 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cc, i64 0, i64 %index.next
+  %13 = bitcast i32* %12 to <4 x i32>*
+  %wide.load13.1 = load <4 x i32>, <4 x i32>* %13, align 16
+  %14 = add nsw <4 x i32> %wide.load13.1, %wide.load.1
+  %15 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cd, i64 0, i64 %index.next
+  %16 = bitcast i32* %15 to <4 x i32>*
+  %wide.load14.1 = load <4 x i32>, <4 x i32>* %16, align 16
+  %17 = mul nsw <4 x i32> %14, %wide.load14.1
+  %18 = getelementptr inbounds [4096 x i32], [4096 x i32]* @ca, i64 0, i64 %index.next
+  %19 = bitcast i32* %18 to <4 x i32>*
+  store <4 x i32> %17, <4 x i32>* %19, align 16
+  %index.next.1 = add nuw nsw i64 %index.next, 4
+  %20 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cb, i64 0, i64 %index.next.1
+  %21 = bitcast i32* %20 to <4 x i32>*
+  %wide.load.2 = load <4 x i32>, <4 x i32>* %21, align 16
+  %22 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cc, i64 0, i64 %index.next.1
+  %23 = bitcast i32* %22 to <4 x i32>*
+  %wide.load13.2 = load <4 x i32>, <4 x i32>* %23, align 16
+  %24 = add nsw <4 x i32> %wide.load13.2, %wide.load.2
+  %25 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cd, i64 0, i64 %index.next.1
+  %26 = bitcast i32* %25 to <4 x i32>*
+  %wide.load14.2 = load <4 x i32>, <4 x i32>* %26, align 16
+  %27 = mul nsw <4 x i32> %24, %wide.load14.2
+  %28 = getelementptr inbounds [4096 x i32], [4096 x i32]* @ca, i64 0, i64 %index.next.1
+  %29 = bitcast i32* %28 to <4 x i32>*
+  store <4 x i32> %27, <4 x i32>* %29, align 16
+  %index.next.2 = add nuw nsw i64 %index.next.1, 4
+  %30 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cb, i64 0, i64 %index.next.2
+  %31 = bitcast i32* %30 to <4 x i32>*
+  %wide.load.3 = load <4 x i32>, <4 x i32>* %31, align 16
+  %32 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cc, i64 0, i64 %index.next.2
+  %33 = bitcast i32* %32 to <4 x i32>*
+  %wide.load13.3 = load <4 x i32>, <4 x i32>* %33, align 16
+  %34 = add nsw <4 x i32> %wide.load13.3, %wide.load.3
+  %35 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cd, i64 0, i64 %index.next.2
+  %36 = bitcast i32* %35 to <4 x i32>*
+  %wide.load14.3 = load <4 x i32>, <4 x i32>* %36, align 16
+  %37 = mul nsw <4 x i32> %34, %wide.load14.3
+  %38 = getelementptr inbounds [4096 x i32], [4096 x i32]* @ca, i64 0, i64 %index.next.2
+  %39 = bitcast i32* %38 to <4 x i32>*
+  store <4 x i32> %37, <4 x i32>* %39, align 16
+  %index.next.3 = add nuw nsw i64 %index.next.2, 4
+  %40 = icmp eq i64 %index.next.3, 4096
+  br i1 %40, label %for.end, label %vector.body
+
+for.end:
+  ret void
+}
+
+; CHECK-LABEL: @foo
+; CHECK-NOT: xxpermdi
+; CHECK-NOT: xxswapd
+
+; CHECK: lxvd2x
+; CHECK: lxvd2x
+; CHECK-DAG: lxvd2x
+; CHECK-DAG: vadduwm
+; CHECK: vmuluwm
+; CHECK: stxvd2x
+
+; CHECK: lxvd2x
+; CHECK: lxvd2x
+; CHECK-DAG: lxvd2x
+; CHECK-DAG: vadduwm
+; CHECK: vmuluwm
+; CHECK: stxvd2x
+
+; CHECK: lxvd2x
+; CHECK: lxvd2x
+; CHECK-DAG: lxvd2x
+; CHECK-DAG: vadduwm
+; CHECK: vmuluwm
+; CHECK: stxvd2x
+
+; CHECK: lxvd2x
+; CHECK: lxvd2x
+; CHECK-DAG: lxvd2x
+; CHECK-DAG: vadduwm
+; CHECK: vmuluwm
+; CHECK: stxvd2x
+
+
+; NOOPTSWAP-LABEL: @foo
+
+; NOOPTSWAP: lxvd2x
+; NOOPTSWAP-DAG: lxvd2x
+; NOOPTSWAP-DAG: lxvd2x
+; NOOPTSWAP-DAG: xxswapd
+; NOOPTSWAP-DAG: xxswapd
+; NOOPTSWAP-DAG: xxswapd
+; NOOPTSWAP-DAG: vadduwm
+; NOOPTSWAP: vmuluwm
+; NOOPTSWAP: xxswapd
+; NOOPTSWAP-DAG: xxswapd
+; NOOPTSWAP-DAG: xxswapd
+; NOOPTSWAP-DAG: stxvd2x
+; NOOPTSWAP-DAG: stxvd2x
+; NOOPTSWAP: stxvd2x
+
diff --git a/test/CodeGen/PowerPC/swaps-le-2.ll b/test/CodeGen/PowerPC/swaps-le-2.ll
new file mode 100644
index 000000000000..08096ed20ddb
--- /dev/null
+++ b/test/CodeGen/PowerPC/swaps-le-2.ll
@@ -0,0 +1,91 @@
+; RUN: llc -O3 -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+; Test swap removal when a vector splat must be adjusted to make it legal.
+;
+; Test generated from following C code:
+;
+; vector char vc = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
+; vector char vcr;
+; vector short vs = {0, 1, 2, 3, 4, 5, 6, 7};
+; vector short vsr;
+; vector int vi = {0, 1, 2, 3};
+; vector int vir;
+;
+; void cfoo ()
+; {
+;   vcr = (vector char){vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5],
+;                       vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5]};
+; }
+;
+; void sfoo ()
+; {
+;   vsr = (vector short){vs[6], vs[6], vs[6], vs[6],
+;                        vs[6], vs[6], vs[6], vs[6]};
+; }
+;
+; void ifoo ()
+; {
+;   vir = (vector int){vi[1], vi[1], vi[1], vi[1]};
+; }
+
+@vc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
+@vs = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
+@vi = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
+@vcr = common global <16 x i8> zeroinitializer, align 16
+@vsr = common global <8 x i16> zeroinitializer, align 16
+@vir = common global <4 x i32> zeroinitializer, align 16
+
+; Function Attrs: nounwind
+define void @cfoo() {
+entry:
+  %0 = load <16 x i8>, <16 x i8>* @vc, align 16
+  %vecinit30 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+  store <16 x i8> %vecinit30, <16 x i8>* @vcr, align 16
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @sfoo() {
+entry:
+  %0 = load <8 x i16>, <8 x i16>* @vs, align 16
+  %vecinit14 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
+  store <8 x i16> %vecinit14, <8 x i16>* @vsr, align 16
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @ifoo() {
+entry:
+  %0 = load <4 x i32>, <4 x i32>* @vi, align 16
+  %vecinit6 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+  store <4 x i32> %vecinit6, <4 x i32>* @vir, align 16
+  ret void
+}
+
+; Justification:
+;  Byte splat of element 5 (BE) becomes element 15-5 = 10 (LE)
+;  which becomes (10+8)%16 = 2 (LE swapped).
+;
+;  Halfword splat of element 6 (BE) becomes element 7-6 = 1 (LE)
+;  which becomes (1+4)%8 = 5 (LE swapped).
+;
+;  Word splat of element 1 (BE) becomes element 3-1 = 2 (LE)
+;  which becomes (2+2)%4 = 0 (LE swapped).
+
+; CHECK-NOT: xxpermdi
+; CHECK-NOT: xxswapd
+
+; CHECK-LABEL: @cfoo
+; CHECK: lxvd2x
+; CHECK: vspltb {{[0-9]+}}, {{[0-9]+}}, 2
+; CHECK: stxvd2x
+
+; CHECK-LABEL: @sfoo
+; CHECK: lxvd2x
+; CHECK: vsplth {{[0-9]+}}, {{[0-9]+}}, 5
+; CHECK: stxvd2x
+
+; CHECK-LABEL: @ifoo
+; CHECK: lxvd2x
+; CHECK: vspltw {{[0-9]+}}, {{[0-9]+}}, 0
+; CHECK: stxvd2x
diff --git a/test/CodeGen/PowerPC/tls-cse.ll b/test/CodeGen/PowerPC/tls-cse.ll
new file mode 100644
index 000000000000..7375e9ccbae3
--- /dev/null
+++ b/test/CodeGen/PowerPC/tls-cse.ll
@@ -0,0 +1,52 @@
+; RUN: llc -march=ppc64 -mcpu=pwr7 -O2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=ppc64 -mcpu=pwr7 -O2 -relocation-model=pic < %s | grep "__tls_get_addr" | count 1
+
+; This test was derived from LLVM's own
+; PrettyStackTraceEntry::~PrettyStackTraceEntry().  It demonstrates an
+; opportunity for CSE of calls to __tls_get_addr().
+
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+%"class.llvm::PrettyStackTraceEntry" = type { i32 (...)**, %"class.llvm::PrettyStackTraceEntry"* }
+
+@_ZTVN4llvm21PrettyStackTraceEntryE = unnamed_addr constant [5 x i8*] [i8* null, i8* null, i8* bitcast (void (%"class.llvm::PrettyStackTraceEntry"*)* @_ZN4llvm21PrettyStackTraceEntryD2Ev to i8*), i8* bitcast (void (%"class.llvm::PrettyStackTraceEntry"*)* @_ZN4llvm21PrettyStackTraceEntryD0Ev to i8*), i8* bitcast (void ()* @__cxa_pure_virtual to i8*)], align 8
+@_ZL20PrettyStackTraceHead = internal thread_local unnamed_addr global %"class.llvm::PrettyStackTraceEntry"* null, align 8
+@.str = private unnamed_addr constant [87 x i8] c"PrettyStackTraceHead == this && \22Pretty stack trace entry destruction is out of order\22\00", align 1
+@.str1 = private unnamed_addr constant [64 x i8] c"/home/wschmidt/llvm/llvm-test2/lib/Support/PrettyStackTrace.cpp\00", align 1
+@__PRETTY_FUNCTION__._ZN4llvm21PrettyStackTraceEntryD2Ev = private unnamed_addr constant [62 x i8] c"virtual llvm::PrettyStackTraceEntry::~PrettyStackTraceEntry()\00", align 1
+
+declare void @_ZN4llvm21PrettyStackTraceEntryD2Ev(%"class.llvm::PrettyStackTraceEntry"* %this) unnamed_addr
+declare void @__cxa_pure_virtual()
+declare void @__assert_fail(i8*, i8*, i32 zeroext, i8*)
+declare void @_ZdlPv(i8*)
+
+define void @_ZN4llvm21PrettyStackTraceEntryD0Ev(%"class.llvm::PrettyStackTraceEntry"* %this) unnamed_addr align 2 {
+entry:
+  %0 = getelementptr inbounds %"class.llvm::PrettyStackTraceEntry", %"class.llvm::PrettyStackTraceEntry"* %this, i64 0, i32 0
+  store i32 (...)** bitcast (i8** getelementptr inbounds ([5 x i8*], [5 x i8*]* @_ZTVN4llvm21PrettyStackTraceEntryE, i64 0, i64 2) to i32 (...)**), i32 (...)*** %0, align 8
+  %1 = load %"class.llvm::PrettyStackTraceEntry"*, %"class.llvm::PrettyStackTraceEntry"** @_ZL20PrettyStackTraceHead, align 8
+  %cmp.i = icmp eq %"class.llvm::PrettyStackTraceEntry"* %1, %this
+  br i1 %cmp.i, label %_ZN4llvm21PrettyStackTraceEntryD2Ev.exit, label %cond.false.i
+
+cond.false.i:                                     ; preds = %entry
+  tail call void @__assert_fail(i8* getelementptr inbounds ([87 x i8], [87 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds ([64 x i8], [64 x i8]* @.str1, i64 0, i64 0), i32 zeroext 119, i8* getelementptr inbounds ([62 x i8], [62 x i8]* @__PRETTY_FUNCTION__._ZN4llvm21PrettyStackTraceEntryD2Ev, i64 0, i64 0))
+  unreachable
+
+_ZN4llvm21PrettyStackTraceEntryD2Ev.exit:         ; preds = %entry
+  %NextEntry.i.i = getelementptr inbounds %"class.llvm::PrettyStackTraceEntry", %"class.llvm::PrettyStackTraceEntry"* %this, i64 0, i32 1
+  %2 = bitcast %"class.llvm::PrettyStackTraceEntry"** %NextEntry.i.i to i64*
+  %3 = load i64, i64* %2, align 8
+  store i64 %3, i64* bitcast (%"class.llvm::PrettyStackTraceEntry"** @_ZL20PrettyStackTraceHead to i64*), align 8
+  %4 = bitcast %"class.llvm::PrettyStackTraceEntry"* %this to i8*
+  tail call void @_ZdlPv(i8* %4)
+  ret void
+}
+
+; CHECK-LABEL: _ZN4llvm21PrettyStackTraceEntryD0Ev:
+; CHECK: addis [[REG1:[0-9]+]], 2, _ZL20PrettyStackTraceHead@got@tlsld@ha
+; CHECK: addi 3, [[REG1]], _ZL20PrettyStackTraceHead@got@tlsld@l
+; CHECK: bl __tls_get_addr(_ZL20PrettyStackTraceHead@tlsld)
+; CHECK: addis 3, 3, _ZL20PrettyStackTraceHead@dtprel@ha
+; CHECK: ld {{[0-9]+}}, _ZL20PrettyStackTraceHead@dtprel@l(3)
+; CHECK: std {{[0-9]+}}, _ZL20PrettyStackTraceHead@dtprel@l(3)
diff --git a/test/CodeGen/PowerPC/tls-pic.ll b/test/CodeGen/PowerPC/tls-pic.ll
index 9ba372591e6e..b7d9298685de 100644
--- a/test/CodeGen/PowerPC/tls-pic.ll
+++ b/test/CodeGen/PowerPC/tls-pic.ll
@@ -13,38 +13,38 @@ define signext i32 @main() nounwind {
 entry:
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   ret i32 %0
 }
 
 ; OPT0-LABEL: main:
 ; OPT0:      addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
-; OPT0-NEXT: addi 3, [[REG]], a@got@tlsld@l
+; OPT0:      addi 3, [[REG]], a@got@tlsld@l
 ; OPT0:      bl __tls_get_addr(a@tlsld)
 ; OPT0-NEXT: nop
 ; OPT0:      addis [[REG2:[0-9]+]], 3, a@dtprel@ha
-; OPT0-NEXT: addi {{[0-9]+}}, [[REG2]], a@dtprel@l
+; OPT0:      addi {{[0-9]+}}, [[REG2]], a@dtprel@l
 ; OPT0-32-LABEL: main
 ; OPT0-32:        addi {{[0-9]+}}, {{[0-9]+}}, a@got@tlsld
 ; OPT0-32:        bl __tls_get_addr(a@tlsld)@PLT
 ; OPT0-32:        addis [[REG:[0-9]+]], 3, a@dtprel@ha
-; OPT0-32-NEXT:   addi  {{[0-9]+}}, [[REG]], a@dtprel@l
+; OPT0-32:        addi  {{[0-9]+}}, [[REG]], a@dtprel@l
 ; OPT1-32-LABEL: main
 ; OPT1-32:        addi 3, {{[0-9]+}}, a@got@tlsld
 ; OPT1-32:        bl __tls_get_addr(a@tlsld)@PLT
 ; OPT1-32:        addis [[REG:[0-9]+]], 3, a@dtprel@ha
-; OPT1-32-NEXT:   addi  {{[0-9]+}}, [[REG]], a@dtprel@l
+; OPT1-32:        addi  {{[0-9]+}}, [[REG]], a@dtprel@l
 
 ; Test peephole optimization for thread-local storage using the
 ; local dynamic model.
 
 ; OPT1-LABEL: main:
 ; OPT1:      addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
-; OPT1-NEXT: addi 3, [[REG]], a@got@tlsld@l
+; OPT1:      addi 3, [[REG]], a@got@tlsld@l
 ; OPT1:      bl __tls_get_addr(a@tlsld)
 ; OPT1-NEXT: nop
 ; OPT1:      addis [[REG2:[0-9]+]], 3, a@dtprel@ha
-; OPT1-NEXT: lwa {{[0-9]+}}, a@dtprel@l([[REG2]])
+; OPT1:      lwa {{[0-9]+}}, a@dtprel@l([[REG2]])
 
 ; Test correct assembly code generation for thread-local storage using
 ; the general dynamic model.
@@ -55,13 +55,13 @@ define signext i32 @main2() nounwind {
 entry:
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
-  %0 = load i32* @a2, align 4
+  %0 = load i32, i32* @a2, align 4
   ret i32 %0
 }
 
 ; OPT1-LABEL: main2
-; OPT1: addis [[REG:[0-9]+]], 2, a2@got@tlsgd@ha
-; OPT1-NEXT: addi 3, [[REG]], a2@got@tlsgd@l
+; OPT1:      addis [[REG:[0-9]+]], 2, a2@got@tlsgd@ha
+; OPT1:      addi 3, [[REG]], a2@got@tlsgd@l
 ; OPT1:      bl __tls_get_addr(a2@tlsgd)
 ; OPT1-NEXT: nop
 ; OPT1-32-LABEL: main2
diff --git a/test/CodeGen/PowerPC/tls-store2.ll b/test/CodeGen/PowerPC/tls-store2.ll
index f884dd8a0a17..e9aa17e8c0ff 100644
--- a/test/CodeGen/PowerPC/tls-store2.ll
+++ b/test/CodeGen/PowerPC/tls-store2.ll
@@ -19,13 +19,14 @@ entry:
 }
 
 ; CHECK-LABEL: call_once:
-; CHECK: addis 3, 2, __once_callable@got@tlsgd@ha
-; CHECK: addi 3, 3, __once_callable@got@tlsgd@l
+; CHECK: addi 3, {{[0-9]+}}, __once_callable@got@tlsgd@l
 ; CHECK: bl __tls_get_addr(__once_callable@tlsgd)
 ; CHECK-NEXT: nop
-; CHECK: std {{[0-9]+}}, 0(3)
-; CHECK: addis 3, 2, __once_call@got@tlsgd@ha
-; CHECK: addi 3, 3, __once_call@got@tlsgd@l
+; FIXME: We could check here for 'std {{[0-9]+}}, 0(3)', but that no longer
+; works because, with new scheduling freedom, we create a copy of R3 based on the
+; initial scheduling, but don't coalesce it again after we move the instructions
+; so that the copy is no longer necessary.
+; CHECK: addi 3, {{[0-9]+}}, __once_call@got@tlsgd@l
 ; CHECK: bl __tls_get_addr(__once_call@tlsgd)
 ; CHECK-NEXT: nop
 ; CHECK: std {{[0-9]+}}, 0(3)
diff --git a/test/CodeGen/PowerPC/tls.ll b/test/CodeGen/PowerPC/tls.ll
index 59b4de755988..c96e444e02c8 100644
--- a/test/CodeGen/PowerPC/tls.ll
+++ b/test/CodeGen/PowerPC/tls.ll
@@ -30,7 +30,7 @@ define signext i32 @main2() nounwind {
 entry:
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
-  %0 = load i32* @a2, align 4
+  %0 = load i32, i32* @a2, align 4
   ret i32 %0
 }
 
diff --git a/test/CodeGen/PowerPC/toc-load-sched-bug.ll b/test/CodeGen/PowerPC/toc-load-sched-bug.ll
index e92c4f4018b1..5ac4e3635023 100644
--- a/test/CodeGen/PowerPC/toc-load-sched-bug.ll
+++ b/test/CodeGen/PowerPC/toc-load-sched-bug.ll
@@ -176,51 +176,51 @@ entry:
   %FileOrErr = alloca %"class.llvm::ErrorOr", align 8
   %ref.tmp = alloca %"class.llvm::SMDiagnostic", align 8
   %ref.tmp5 = alloca %"class.std::basic_string", align 8
-  %_M_p.i.i.i = getelementptr inbounds %"class.std::basic_string"* %Filename, i64 0, i32 0, i32 0
-  %0 = load i8** %_M_p.i.i.i, align 8, !tbaa !1
+  %_M_p.i.i.i = getelementptr inbounds %"class.std::basic_string", %"class.std::basic_string"* %Filename, i64 0, i32 0, i32 0
+  %0 = load i8*, i8** %_M_p.i.i.i, align 8, !tbaa !1
   %1 = ptrtoint i8* %0 to i64
-  %arrayidx.i.i.i = getelementptr inbounds i8* %0, i64 -24
+  %arrayidx.i.i.i = getelementptr inbounds i8, i8* %0, i64 -24
   %_M_length.i.i = bitcast i8* %arrayidx.i.i.i to i64*
-  %2 = load i64* %_M_length.i.i, align 8, !tbaa !7
+  %2 = load i64, i64* %_M_length.i.i, align 8, !tbaa !7
   %.fca.0.insert18 = insertvalue [2 x i64] undef, i64 %1, 0
   %.fca.1.insert21 = insertvalue [2 x i64] %.fca.0.insert18, i64 %2, 1
   call void @_ZN4llvm12MemoryBuffer14getFileOrSTDINENS_9StringRefEl(%"class.llvm::ErrorOr"* sret %FileOrErr, [2 x i64] %.fca.1.insert21, i64 -1) #3
-  %HasError.i24 = getelementptr inbounds %"class.llvm::ErrorOr"* %FileOrErr, i64 0, i32 1
-  %bf.load.i25 = load i8* %HasError.i24, align 8
+  %HasError.i24 = getelementptr inbounds %"class.llvm::ErrorOr", %"class.llvm::ErrorOr"* %FileOrErr, i64 0, i32 1
+  %bf.load.i25 = load i8, i8* %HasError.i24, align 8
   %3 = and i8 %bf.load.i25, 1
   %bf.cast.i26 = icmp eq i8 %3, 0
   br i1 %bf.cast.i26, label %_ZN4llvm7ErrorOrISt10unique_ptrINS_12MemoryBufferESt14default_deleteIS2_EEE3getEv.exit, label %_ZNK4llvm7ErrorOrISt10unique_ptrINS_12MemoryBufferESt14default_deleteIS2_EEE8getErrorEv.exit
 
 _ZNK4llvm7ErrorOrISt10unique_ptrINS_12MemoryBufferESt14default_deleteIS2_EEE8getErrorEv.exit: ; preds = %entry
   %retval.sroa.0.0..sroa_cast.i = bitcast %"class.llvm::ErrorOr"* %FileOrErr to i64*
-  %retval.sroa.0.0.copyload.i = load i64* %retval.sroa.0.0..sroa_cast.i, align 8
-  %retval.sroa.3.0..sroa_idx.i = getelementptr inbounds %"class.llvm::ErrorOr"* %FileOrErr, i64 0, i32 0, i32 0, i32 0, i32 0, i64 8
+  %retval.sroa.0.0.copyload.i = load i64, i64* %retval.sroa.0.0..sroa_cast.i, align 8
+  %retval.sroa.3.0..sroa_idx.i = getelementptr inbounds %"class.llvm::ErrorOr", %"class.llvm::ErrorOr"* %FileOrErr, i64 0, i32 0, i32 0, i32 0, i32 0, i64 8
   %retval.sroa.3.0..sroa_cast.i = bitcast i8* %retval.sroa.3.0..sroa_idx.i to i64*
-  %retval.sroa.3.0.copyload.i = load i64* %retval.sroa.3.0..sroa_cast.i, align 8
+  %retval.sroa.3.0.copyload.i = load i64, i64* %retval.sroa.3.0..sroa_cast.i, align 8
   %phitmp = trunc i64 %retval.sroa.0.0.copyload.i to i32
   %cmp.i = icmp eq i32 %phitmp, 0
   br i1 %cmp.i, label %cond.false.i.i, label %if.then
 
 if.then:                                          ; preds = %_ZNK4llvm7ErrorOrISt10unique_ptrINS_12MemoryBufferESt14default_deleteIS2_EEE8getErrorEv.exit
   %.c = inttoptr i64 %retval.sroa.3.0.copyload.i to %"class.std::error_category"*
-  %4 = load i8** %_M_p.i.i.i, align 8, !tbaa !1
-  %arrayidx.i.i.i30 = getelementptr inbounds i8* %4, i64 -24
+  %4 = load i8*, i8** %_M_p.i.i.i, align 8, !tbaa !1
+  %arrayidx.i.i.i30 = getelementptr inbounds i8, i8* %4, i64 -24
   %_M_length.i.i31 = bitcast i8* %arrayidx.i.i.i30 to i64*
-  %5 = load i64* %_M_length.i.i31, align 8, !tbaa !7
+  %5 = load i64, i64* %_M_length.i.i31, align 8, !tbaa !7
   %6 = inttoptr i64 %retval.sroa.3.0.copyload.i to void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)***
-  %vtable.i = load void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)*** %6, align 8, !tbaa !11
-  %vfn.i = getelementptr inbounds void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)** %vtable.i, i64 3
-  %7 = load void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)** %vfn.i, align 8
+  %vtable.i = load void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)**, void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)*** %6, align 8, !tbaa !11
+  %vfn.i = getelementptr inbounds void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)*, void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)** %vtable.i, i64 3
+  %7 = load void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)*, void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)** %vfn.i, align 8
   call void %7(%"class.std::basic_string"* sret %ref.tmp5, %"class.std::error_category"* %.c, i32 signext %phitmp) #3
-  %call2.i.i = call dereferenceable(8) %"class.std::basic_string"* @_ZNSs6insertEmPKcm(%"class.std::basic_string"* %ref.tmp5, i64 0, i8* getelementptr inbounds ([28 x i8]* @.str, i64 0, i64 0), i64 27) #3
-  %_M_p2.i.i.i.i = getelementptr inbounds %"class.std::basic_string"* %call2.i.i, i64 0, i32 0, i32 0
-  %8 = load i8** %_M_p2.i.i.i.i, align 8, !tbaa !13
-  store i8* bitcast (i64* getelementptr inbounds ([0 x i64]* @_ZNSs4_Rep20_S_empty_rep_storageE, i64 0, i64 3) to i8*), i8** %_M_p2.i.i.i.i, align 8, !tbaa !1
-  %arrayidx.i.i.i36 = getelementptr inbounds i8* %8, i64 -24
+  %call2.i.i = call dereferenceable(8) %"class.std::basic_string"* @_ZNSs6insertEmPKcm(%"class.std::basic_string"* %ref.tmp5, i64 0, i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str, i64 0, i64 0), i64 27) #3
+  %_M_p2.i.i.i.i = getelementptr inbounds %"class.std::basic_string", %"class.std::basic_string"* %call2.i.i, i64 0, i32 0, i32 0
+  %8 = load i8*, i8** %_M_p2.i.i.i.i, align 8, !tbaa !13
+  store i8* bitcast (i64* getelementptr inbounds ([0 x i64], [0 x i64]* @_ZNSs4_Rep20_S_empty_rep_storageE, i64 0, i64 3) to i8*), i8** %_M_p2.i.i.i.i, align 8, !tbaa !1
+  %arrayidx.i.i.i36 = getelementptr inbounds i8, i8* %8, i64 -24
   %_M_length.i.i37 = bitcast i8* %arrayidx.i.i.i36 to i64*
-  %9 = load i64* %_M_length.i.i37, align 8, !tbaa !7
-  %Filename.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 2
-  %10 = getelementptr inbounds %"class.std::allocator"* %ref.tmp.i.i2.i, i64 0, i32 0
+  %9 = load i64, i64* %_M_length.i.i37, align 8, !tbaa !7
+  %Filename.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 2
+  %10 = getelementptr inbounds %"class.std::allocator", %"class.std::allocator"* %ref.tmp.i.i2.i, i64 0, i32 0
   %11 = bitcast %"class.llvm::SMDiagnostic"* %ref.tmp to i8*
   call void @llvm.memset.p0i8.i64(i8* %11, i8 0, i64 16, i32 8, i1 false) #3
   call void @llvm.lifetime.start(i64 1, i8* %10) #3
@@ -228,8 +228,8 @@ if.then:                                          ; preds = %_ZNK4llvm7ErrorOrIS
   br i1 %tobool.i.i4.i, label %if.then.i.i6.i, label %if.end.i.i8.i
 
 if.then.i.i6.i:                                   ; preds = %if.then
-  %_M_p.i.i.i.i.i.i5.i = getelementptr inbounds %"class.std::basic_string"* %Filename.i, i64 0, i32 0, i32 0
-  store i8* bitcast (i64* getelementptr inbounds ([0 x i64]* @_ZNSs4_Rep20_S_empty_rep_storageE, i64 0, i64 3) to i8*), i8** %_M_p.i.i.i.i.i.i5.i, align 8, !tbaa !13
+  %_M_p.i.i.i.i.i.i5.i = getelementptr inbounds %"class.std::basic_string", %"class.std::basic_string"* %Filename.i, i64 0, i32 0, i32 0
+  store i8* bitcast (i64* getelementptr inbounds ([0 x i64], [0 x i64]* @_ZNSs4_Rep20_S_empty_rep_storageE, i64 0, i64 3) to i8*), i8** %_M_p.i.i.i.i.i.i5.i, align 8, !tbaa !13
   br label %_ZNK4llvm9StringRefcvSsEv.exit9.i
 
 if.end.i.i8.i:                                    ; preds = %if.then
@@ -238,21 +238,21 @@ if.end.i.i8.i:                                    ; preds = %if.then
 
 _ZNK4llvm9StringRefcvSsEv.exit9.i:                ; preds = %if.end.i.i8.i, %if.then.i.i6.i
   call void @llvm.lifetime.end(i64 1, i8* %10) #3
-  %LineNo.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 3
+  %LineNo.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 3
   store i32 -1, i32* %LineNo.i, align 8, !tbaa !14
-  %ColumnNo.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 4
+  %ColumnNo.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 4
   store i32 -1, i32* %ColumnNo.i, align 4, !tbaa !21
-  %Kind.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 5
+  %Kind.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 5
   store i32 0, i32* %Kind.i, align 8, !tbaa !22
-  %Message.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 6
-  %12 = getelementptr inbounds %"class.std::allocator"* %ref.tmp.i.i.i, i64 0, i32 0
+  %Message.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 6
+  %12 = getelementptr inbounds %"class.std::allocator", %"class.std::allocator"* %ref.tmp.i.i.i, i64 0, i32 0
   call void @llvm.lifetime.start(i64 1, i8* %12) #3
   %tobool.i.i.i = icmp eq i8* %8, null
   br i1 %tobool.i.i.i, label %if.then.i.i.i, label %if.end.i.i.i
 
 if.then.i.i.i:                                    ; preds = %_ZNK4llvm9StringRefcvSsEv.exit9.i
-  %_M_p.i.i.i.i.i.i.i = getelementptr inbounds %"class.std::basic_string"* %Message.i, i64 0, i32 0, i32 0
-  store i8* bitcast (i64* getelementptr inbounds ([0 x i64]* @_ZNSs4_Rep20_S_empty_rep_storageE, i64 0, i64 3) to i8*), i8** %_M_p.i.i.i.i.i.i.i, align 8, !tbaa !13
+  %_M_p.i.i.i.i.i.i.i = getelementptr inbounds %"class.std::basic_string", %"class.std::basic_string"* %Message.i, i64 0, i32 0, i32 0
+  store i8* bitcast (i64* getelementptr inbounds ([0 x i64], [0 x i64]* @_ZNSs4_Rep20_S_empty_rep_storageE, i64 0, i64 3) to i8*), i8** %_M_p.i.i.i.i.i.i.i, align 8, !tbaa !13
   br label %_ZN4llvm12SMDiagnosticC2ENS_9StringRefENS_9SourceMgr8DiagKindES1_.exit
 
 if.end.i.i.i:                                     ; preds = %_ZNK4llvm9StringRefcvSsEv.exit9.i
@@ -261,49 +261,49 @@ if.end.i.i.i:                                     ; preds = %_ZNK4llvm9StringRef
 
 _ZN4llvm12SMDiagnosticC2ENS_9StringRefENS_9SourceMgr8DiagKindES1_.exit: ; preds = %if.then.i.i.i, %if.end.i.i.i
   call void @llvm.lifetime.end(i64 1, i8* %12) #3
-  %_M_p.i.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 7, i32 0, i32 0
-  store i8* bitcast (i64* getelementptr inbounds ([0 x i64]* @_ZNSs4_Rep20_S_empty_rep_storageE, i64 0, i64 3) to i8*), i8** %_M_p.i.i.i.i.i, align 8, !tbaa !13
-  %Ranges.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 8
+  %_M_p.i.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 7, i32 0, i32 0
+  store i8* bitcast (i64* getelementptr inbounds ([0 x i64], [0 x i64]* @_ZNSs4_Rep20_S_empty_rep_storageE, i64 0, i64 3) to i8*), i8** %_M_p.i.i.i.i.i, align 8, !tbaa !13
+  %Ranges.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 8
   %13 = bitcast %"class.std::vector.79"* %Ranges.i to i8*
   call void @llvm.memset.p0i8.i64(i8* %13, i8 0, i64 24, i32 8, i1 false) #3
-  %14 = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 9, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0, i64 0
-  %BeginX.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 9, i32 0, i32 0, i32 0, i32 0, i32 0
+  %14 = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 9, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0, i64 0
+  %BeginX.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 9, i32 0, i32 0, i32 0, i32 0, i32 0
   store i8* %14, i8** %BeginX.i.i.i.i.i.i, align 8, !tbaa !23
-  %EndX.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 9, i32 0, i32 0, i32 0, i32 0, i32 1
+  %EndX.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 9, i32 0, i32 0, i32 0, i32 0, i32 1
   store i8* %14, i8** %EndX.i.i.i.i.i.i, align 8, !tbaa !25
-  %CapacityX.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 9, i32 0, i32 0, i32 0, i32 0, i32 2
-  %add.ptr.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 9, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0, i64 96
+  %CapacityX.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 9, i32 0, i32 0, i32 0, i32 0, i32 2
+  %add.ptr.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 9, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0, i64 96
   store i8* %add.ptr.i.i.i.i.i.i, i8** %CapacityX.i.i.i.i.i.i, align 8, !tbaa !26
   %15 = bitcast %"class.llvm::SMDiagnostic"* %Err to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %15, i8* %11, i64 16, i32 8, i1 false) #3
-  %Filename.i38 = getelementptr inbounds %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 2
+  %Filename.i38 = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 2
   call void @_ZNSs4swapERSs(%"class.std::basic_string"* %Filename.i38, %"class.std::basic_string"* dereferenceable(8) %Filename.i) #3
-  %LineNo.i39 = getelementptr inbounds %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 3
+  %LineNo.i39 = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 3
   %16 = bitcast i32* %LineNo.i39 to i8*
   %17 = bitcast i32* %LineNo.i to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %16, i8* %17, i64 12, i32 4, i1 false) #3
-  %Message.i40 = getelementptr inbounds %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 6
+  %Message.i40 = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 6
   call void @_ZNSs4swapERSs(%"class.std::basic_string"* %Message.i40, %"class.std::basic_string"* dereferenceable(8) %Message.i) #3
-  %LineContents.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 7
-  %LineContents7.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 7
+  %LineContents.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 7
+  %LineContents7.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 7
   call void @_ZNSs4swapERSs(%"class.std::basic_string"* %LineContents.i, %"class.std::basic_string"* dereferenceable(8) %LineContents7.i) #3
-  %Ranges.i41 = getelementptr inbounds %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 8
-  %_M_start.i7.i.i.i = getelementptr inbounds %"class.std::vector.79"* %Ranges.i41, i64 0, i32 0, i32 0, i32 0
-  %18 = load %"struct.std::pair"** %_M_start.i7.i.i.i, align 8, !tbaa !27
-  %_M_finish.i9.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 8, i32 0, i32 0, i32 1
-  %_M_end_of_storage.i11.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 8, i32 0, i32 0, i32 2
-  %_M_start2.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 8, i32 0, i32 0, i32 0
+  %Ranges.i41 = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 8
+  %_M_start.i7.i.i.i = getelementptr inbounds %"class.std::vector.79", %"class.std::vector.79"* %Ranges.i41, i64 0, i32 0, i32 0, i32 0
+  %18 = load %"struct.std::pair"*, %"struct.std::pair"** %_M_start.i7.i.i.i, align 8, !tbaa !27
+  %_M_finish.i9.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 8, i32 0, i32 0, i32 1
+  %_M_end_of_storage.i11.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 8, i32 0, i32 0, i32 2
+  %_M_start2.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 8, i32 0, i32 0, i32 0
   %19 = bitcast %"class.std::vector.79"* %Ranges.i41 to i8*
   call void @llvm.memset.p0i8.i64(i8* %19, i8 0, i64 16, i32 8, i1 false) #3
-  %20 = load %"struct.std::pair"** %_M_start2.i.i.i.i, align 8, !tbaa !27
+  %20 = load %"struct.std::pair"*, %"struct.std::pair"** %_M_start2.i.i.i.i, align 8, !tbaa !27
   store %"struct.std::pair"* %20, %"struct.std::pair"** %_M_start.i7.i.i.i, align 8, !tbaa !27
   store %"struct.std::pair"* null, %"struct.std::pair"** %_M_start2.i.i.i.i, align 8, !tbaa !27
-  %_M_finish3.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 8, i32 0, i32 0, i32 1
-  %21 = load %"struct.std::pair"** %_M_finish3.i.i.i.i, align 8, !tbaa !27
+  %_M_finish3.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 8, i32 0, i32 0, i32 1
+  %21 = load %"struct.std::pair"*, %"struct.std::pair"** %_M_finish3.i.i.i.i, align 8, !tbaa !27
   store %"struct.std::pair"* %21, %"struct.std::pair"** %_M_finish.i9.i.i.i, align 8, !tbaa !27
   store %"struct.std::pair"* null, %"struct.std::pair"** %_M_finish3.i.i.i.i, align 8, !tbaa !27
-  %_M_end_of_storage4.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 8, i32 0, i32 0, i32 2
-  %22 = load %"struct.std::pair"** %_M_end_of_storage4.i.i.i.i, align 8, !tbaa !27
+  %_M_end_of_storage4.i.i.i.i = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 8, i32 0, i32 0, i32 2
+  %22 = load %"struct.std::pair"*, %"struct.std::pair"** %_M_end_of_storage4.i.i.i.i, align 8, !tbaa !27
   store %"struct.std::pair"* %22, %"struct.std::pair"** %_M_end_of_storage.i11.i.i.i, align 8, !tbaa !27
   store %"struct.std::pair"* null, %"struct.std::pair"** %_M_end_of_storage4.i.i.i.i, align 8, !tbaa !27
   %tobool.i.i.i.i.i.i = icmp eq %"struct.std::pair"* %18, null
@@ -315,18 +315,18 @@ if.then.i.i.i.i.i.i:                              ; preds = %_ZN4llvm12SMDiagnos
   br label %_ZN4llvm12SMDiagnosticaSEOS0_.exit
 
 _ZN4llvm12SMDiagnosticaSEOS0_.exit:               ; preds = %_ZN4llvm12SMDiagnosticC2ENS_9StringRefENS_9SourceMgr8DiagKindES1_.exit, %if.then.i.i.i.i.i.i
-  %24 = getelementptr inbounds %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 9, i32 0
-  %25 = getelementptr inbounds %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 9, i32 0
+  %24 = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %Err, i64 0, i32 9, i32 0
+  %25 = getelementptr inbounds %"class.llvm::SMDiagnostic", %"class.llvm::SMDiagnostic"* %ref.tmp, i64 0, i32 9, i32 0
   %call2.i.i42 = call dereferenceable(48) %"class.llvm::SmallVectorImpl.85"* @_ZN4llvm15SmallVectorImplINS_7SMFixItEEaSEOS2_(%"class.llvm::SmallVectorImpl.85"* %24, %"class.llvm::SmallVectorImpl.85"* dereferenceable(48) %25) #3
   call void @_ZN4llvm12SMDiagnosticD2Ev(%"class.llvm::SMDiagnostic"* %ref.tmp) #3
-  %26 = getelementptr inbounds %"class.std::allocator"* %ref.tmp.i.i, i64 0, i32 0
+  %26 = getelementptr inbounds %"class.std::allocator", %"class.std::allocator"* %ref.tmp.i.i, i64 0, i32 0
   call void @llvm.lifetime.start(i64 1, i8* %26) #3
   %27 = bitcast i8* %arrayidx.i.i.i36 to %"struct.std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_Rep"*
   %cmp.i.i.i = icmp eq i8* %arrayidx.i.i.i36, bitcast ([0 x i64]* @_ZNSs4_Rep20_S_empty_rep_storageE to i8*)
   br i1 %cmp.i.i.i, label %_ZNSsD1Ev.exit, label %if.then.i.i.i45, !prof !28
 
 if.then.i.i.i45:                                  ; preds = %_ZN4llvm12SMDiagnosticaSEOS0_.exit
-  %_M_refcount.i.i.i = getelementptr inbounds i8* %8, i64 -8
+  %_M_refcount.i.i.i = getelementptr inbounds i8, i8* %8, i64 -8
   %28 = bitcast i8* %_M_refcount.i.i.i to i32*
   br i1 icmp ne (i8* bitcast (i32 (i32*, void (i8*)*)* @__pthread_key_create to i8*), i8* null), label %if.then.i.i.i.i, label %if.else.i.i.i.i
 
@@ -335,12 +335,12 @@ if.then.i.i.i.i:                                  ; preds = %if.then.i.i.i45
   call void @llvm.lifetime.start(i64 4, i8* %.atomicdst.i.i.i.i.i.0..atomicdst.i.i.i.i.0..atomicdst.i.i.i.0..atomicdst.i.i.0..atomicdst.i.0..sroa_cast)
   %29 = atomicrmw volatile add i32* %28, i32 -1 acq_rel
   store i32 %29, i32* %.atomicdst.i.i.i.i.i, align 4
-  %.atomicdst.i.i.i.i.i.0..atomicdst.i.i.i.i.0..atomicdst.i.i.i.0..atomicdst.i.i.0..atomicdst.i.0..atomicdst.0..atomicdst.0..i.i.i.i.i = load volatile i32* %.atomicdst.i.i.i.i.i, align 4
+  %.atomicdst.i.i.i.i.i.0..atomicdst.i.i.i.i.0..atomicdst.i.i.i.0..atomicdst.i.i.0..atomicdst.i.0..atomicdst.0..atomicdst.0..i.i.i.i.i = load volatile i32, i32* %.atomicdst.i.i.i.i.i, align 4
   call void @llvm.lifetime.end(i64 4, i8* %.atomicdst.i.i.i.i.i.0..atomicdst.i.i.i.i.0..atomicdst.i.i.i.0..atomicdst.i.i.0..atomicdst.i.0..sroa_cast)
   br label %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i.i
 
 if.else.i.i.i.i:                                  ; preds = %if.then.i.i.i45
-  %30 = load i32* %28, align 4, !tbaa !29
+  %30 = load i32, i32* %28, align 4, !tbaa !29
   %add.i.i.i.i.i = add nsw i32 %30, -1
   store i32 %add.i.i.i.i.i, i32* %28, align 4, !tbaa !29
   br label %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i.i
@@ -356,17 +356,17 @@ if.then4.i.i.i:                                   ; preds = %_ZN9__gnu_cxxL27__e
 
 _ZNSsD1Ev.exit:                                   ; preds = %_ZN4llvm12SMDiagnosticaSEOS0_.exit, %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i.i, %if.then4.i.i.i
   call void @llvm.lifetime.end(i64 1, i8* %26) #3
-  %31 = getelementptr inbounds %"class.std::allocator"* %ref.tmp.i.i47, i64 0, i32 0
+  %31 = getelementptr inbounds %"class.std::allocator", %"class.std::allocator"* %ref.tmp.i.i47, i64 0, i32 0
   call void @llvm.lifetime.start(i64 1, i8* %31) #3
-  %_M_p.i.i.i.i48 = getelementptr inbounds %"class.std::basic_string"* %ref.tmp5, i64 0, i32 0, i32 0
-  %32 = load i8** %_M_p.i.i.i.i48, align 8, !tbaa !1
-  %arrayidx.i.i.i49 = getelementptr inbounds i8* %32, i64 -24
+  %_M_p.i.i.i.i48 = getelementptr inbounds %"class.std::basic_string", %"class.std::basic_string"* %ref.tmp5, i64 0, i32 0, i32 0
+  %32 = load i8*, i8** %_M_p.i.i.i.i48, align 8, !tbaa !1
+  %arrayidx.i.i.i49 = getelementptr inbounds i8, i8* %32, i64 -24
   %33 = bitcast i8* %arrayidx.i.i.i49 to %"struct.std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_Rep"*
   %cmp.i.i.i50 = icmp eq i8* %arrayidx.i.i.i49, bitcast ([0 x i64]* @_ZNSs4_Rep20_S_empty_rep_storageE to i8*)
   br i1 %cmp.i.i.i50, label %_ZNSsD1Ev.exit62, label %if.then.i.i.i52, !prof !28
 
 if.then.i.i.i52:                                  ; preds = %_ZNSsD1Ev.exit
-  %_M_refcount.i.i.i51 = getelementptr inbounds i8* %32, i64 -8
+  %_M_refcount.i.i.i51 = getelementptr inbounds i8, i8* %32, i64 -8
   %34 = bitcast i8* %_M_refcount.i.i.i51 to i32*
   br i1 icmp ne (i8* bitcast (i32 (i32*, void (i8*)*)* @__pthread_key_create to i8*), i8* null), label %if.then.i.i.i.i55, label %if.else.i.i.i.i57
 
@@ -375,12 +375,12 @@ if.then.i.i.i.i55:                                ; preds = %if.then.i.i.i52
   call void @llvm.lifetime.start(i64 4, i8* %.atomicdst.i.i.i.i.i46.0..atomicdst.i.i.i.i.0..atomicdst.i.i.i.0..atomicdst.i.i.0..atomicdst.i.0..sroa_cast)
   %35 = atomicrmw volatile add i32* %34, i32 -1 acq_rel
   store i32 %35, i32* %.atomicdst.i.i.i.i.i46, align 4
-  %.atomicdst.i.i.i.i.i46.0..atomicdst.i.i.i.i.0..atomicdst.i.i.i.0..atomicdst.i.i.0..atomicdst.i.0..atomicdst.0..atomicdst.0..i.i.i.i.i54 = load volatile i32* %.atomicdst.i.i.i.i.i46, align 4
+  %.atomicdst.i.i.i.i.i46.0..atomicdst.i.i.i.i.0..atomicdst.i.i.i.0..atomicdst.i.i.0..atomicdst.i.0..atomicdst.0..atomicdst.0..i.i.i.i.i54 = load volatile i32, i32* %.atomicdst.i.i.i.i.i46, align 4
   call void @llvm.lifetime.end(i64 4, i8* %.atomicdst.i.i.i.i.i46.0..atomicdst.i.i.i.i.0..atomicdst.i.i.i.0..atomicdst.i.i.0..atomicdst.i.0..sroa_cast)
   br label %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i.i60
 
 if.else.i.i.i.i57:                                ; preds = %if.then.i.i.i52
-  %36 = load i32* %34, align 4, !tbaa !29
+  %36 = load i32, i32* %34, align 4, !tbaa !29
   %add.i.i.i.i.i56 = add nsw i32 %36, -1
   store i32 %add.i.i.i.i.i56, i32* %34, align 4, !tbaa !29
   br label %_ZN9__gnu_cxxL27__exchange_and_add_dispatchEPii.exit.i.i.i60
@@ -399,33 +399,33 @@ _ZNSsD1Ev.exit62:                                 ; preds = %_ZNSsD1Ev.exit, %_Z
   br label %cleanup
 
 cond.false.i.i:                                   ; preds = %_ZNK4llvm7ErrorOrISt10unique_ptrINS_12MemoryBufferESt14default_deleteIS2_EEE8getErrorEv.exit
-  call void @__assert_fail(i8* getelementptr inbounds ([54 x i8]* @.str1, i64 0, i64 0), i8* getelementptr inbounds ([61 x i8]* @.str2, i64 0, i64 0), i32 zeroext 242, i8* getelementptr inbounds ([206 x i8]* @__PRETTY_FUNCTION__._ZN4llvm7ErrorOrISt10unique_ptrINS_12MemoryBufferESt14default_deleteIS2_EEE10getStorageEv, i64 0, i64 0)) #7
+  call void @__assert_fail(i8* getelementptr inbounds ([54 x i8], [54 x i8]* @.str1, i64 0, i64 0), i8* getelementptr inbounds ([61 x i8], [61 x i8]* @.str2, i64 0, i64 0), i32 zeroext 242, i8* getelementptr inbounds ([206 x i8], [206 x i8]* @__PRETTY_FUNCTION__._ZN4llvm7ErrorOrISt10unique_ptrINS_12MemoryBufferESt14default_deleteIS2_EEE10getStorageEv, i64 0, i64 0)) #7
   unreachable
 
 _ZN4llvm7ErrorOrISt10unique_ptrINS_12MemoryBufferESt14default_deleteIS2_EEE3getEv.exit: ; preds = %entry
   %_M_head_impl.i.i.i.i.i = bitcast %"class.llvm::ErrorOr"* %FileOrErr to %"class.llvm::MemoryBuffer"**
-  %37 = load %"class.llvm::MemoryBuffer"** %_M_head_impl.i.i.i.i.i, align 8, !tbaa !27
+  %37 = load %"class.llvm::MemoryBuffer"*, %"class.llvm::MemoryBuffer"** %_M_head_impl.i.i.i.i.i, align 8, !tbaa !27
   %call9 = call %"class.llvm::Module"* @_ZN4llvm7ParseIREPNS_12MemoryBufferERNS_12SMDiagnosticERNS_11LLVMContextE(%"class.llvm::MemoryBuffer"* %37, %"class.llvm::SMDiagnostic"* dereferenceable(200) %Err, %"class.llvm::LLVMContext"* dereferenceable(8) %Context)
   br label %cleanup
 
 cleanup:                                          ; preds = %_ZN4llvm7ErrorOrISt10unique_ptrINS_12MemoryBufferESt14default_deleteIS2_EEE3getEv.exit, %_ZNSsD1Ev.exit62
   %retval.0 = phi %"class.llvm::Module"* [ null, %_ZNSsD1Ev.exit62 ], [ %call9, %_ZN4llvm7ErrorOrISt10unique_ptrINS_12MemoryBufferESt14default_deleteIS2_EEE3getEv.exit ]
-  %bf.load.i = load i8* %HasError.i24, align 8
+  %bf.load.i = load i8, i8* %HasError.i24, align 8
   %38 = and i8 %bf.load.i, 1
   %bf.cast.i = icmp eq i8 %38, 0
   br i1 %bf.cast.i, label %_ZN4llvm7ErrorOrISt10unique_ptrINS_12MemoryBufferESt14default_deleteIS2_EEE10getStorageEv.exit.i, label %_ZN4llvm7ErrorOrISt10unique_ptrINS_12MemoryBufferESt14default_deleteIS2_EEED2Ev.exit
 
 _ZN4llvm7ErrorOrISt10unique_ptrINS_12MemoryBufferESt14default_deleteIS2_EEE10getStorageEv.exit.i: ; preds = %cleanup
   %_M_head_impl.i.i.i.i.i.i = bitcast %"class.llvm::ErrorOr"* %FileOrErr to %"class.llvm::MemoryBuffer"**
-  %39 = load %"class.llvm::MemoryBuffer"** %_M_head_impl.i.i.i.i.i.i, align 8, !tbaa !27
+  %39 = load %"class.llvm::MemoryBuffer"*, %"class.llvm::MemoryBuffer"** %_M_head_impl.i.i.i.i.i.i, align 8, !tbaa !27
   %cmp.i.i = icmp eq %"class.llvm::MemoryBuffer"* %39, null
   br i1 %cmp.i.i, label %_ZNSt10unique_ptrIN4llvm12MemoryBufferESt14default_deleteIS1_EED2Ev.exit.i, label %_ZNKSt14default_deleteIN4llvm12MemoryBufferEEclEPS1_.exit.i.i
 
 _ZNKSt14default_deleteIN4llvm12MemoryBufferEEclEPS1_.exit.i.i: ; preds = %_ZN4llvm7ErrorOrISt10unique_ptrINS_12MemoryBufferESt14default_deleteIS2_EEE10getStorageEv.exit.i
   %40 = bitcast %"class.llvm::MemoryBuffer"* %39 to void (%"class.llvm::MemoryBuffer"*)***
-  %vtable.i.i.i = load void (%"class.llvm::MemoryBuffer"*)*** %40, align 8, !tbaa !11
-  %vfn.i.i.i = getelementptr inbounds void (%"class.llvm::MemoryBuffer"*)** %vtable.i.i.i, i64 1
-  %41 = load void (%"class.llvm::MemoryBuffer"*)** %vfn.i.i.i, align 8
+  %vtable.i.i.i = load void (%"class.llvm::MemoryBuffer"*)**, void (%"class.llvm::MemoryBuffer"*)*** %40, align 8, !tbaa !11
+  %vfn.i.i.i = getelementptr inbounds void (%"class.llvm::MemoryBuffer"*)*, void (%"class.llvm::MemoryBuffer"*)** %vtable.i.i.i, i64 1
+  %41 = load void (%"class.llvm::MemoryBuffer"*)*, void (%"class.llvm::MemoryBuffer"*)** %vfn.i.i.i, align 8
   call void %41(%"class.llvm::MemoryBuffer"* %39) #3
   br label %_ZNSt10unique_ptrIN4llvm12MemoryBufferESt14default_deleteIS1_EED2Ev.exit.i
 
diff --git a/test/CodeGen/PowerPC/trampoline.ll b/test/CodeGen/PowerPC/trampoline.ll
index 3ea46f50e0c0..e1a26dae7291 100644
--- a/test/CodeGen/PowerPC/trampoline.ll
+++ b/test/CodeGen/PowerPC/trampoline.ll
@@ -29,20 +29,20 @@ module asm "\09.globl .objc_class_name_NSBitmapImageRep"
 	%struct.objc_super = type opaque
 @_NSConcreteStackBlock = external global i8*		; <i8**> [#uses=1]
 @"\01L_OBJC_SELECTOR_REFERENCES_1" = internal global %struct.objc_selector* bitcast ([34 x i8]* @"\01L_OBJC_METH_VAR_NAME_1" to %struct.objc_selector*), section "__OBJC,__message_refs,literal_pointers,no_dead_strip"		; <%struct.objc_selector**> [#uses=2]
-@"\01L_OBJC_CLASS_NSBitmapImageRep" = internal global %struct._objc_class { %struct._objc_class* @"\01L_OBJC_METACLASS_NSBitmapImageRep", %struct._objc_class* bitcast ([11 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), i8* getelementptr ([17 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i32 0, i32 1, i32 0, %struct._objc_ivar_list* null, %struct._objc_method_list* bitcast ({ i8*, i32, [1 x %struct._objc_method] }* @"\01L_OBJC_INSTANCE_METHODS_NSBitmapImageRep" to %struct._objc_method_list*), %struct.objc_cache* null, %struct._objc_protocol** null, i8* null, %struct._objc_class_ext* null }, section "__OBJC,__class,regular,no_dead_strip"		; <%struct._objc_class*> [#uses=3]
+@"\01L_OBJC_CLASS_NSBitmapImageRep" = internal global %struct._objc_class { %struct._objc_class* @"\01L_OBJC_METACLASS_NSBitmapImageRep", %struct._objc_class* bitcast ([11 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), i8* getelementptr ([17 x i8], [17 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i32 0, i32 1, i32 0, %struct._objc_ivar_list* null, %struct._objc_method_list* bitcast ({ i8*, i32, [1 x %struct._objc_method] }* @"\01L_OBJC_INSTANCE_METHODS_NSBitmapImageRep" to %struct._objc_method_list*), %struct.objc_cache* null, %struct._objc_protocol** null, i8* null, %struct._objc_class_ext* null }, section "__OBJC,__class,regular,no_dead_strip"		; <%struct._objc_class*> [#uses=3]
 @"\01L_OBJC_SELECTOR_REFERENCES_0" = internal global %struct.objc_selector* bitcast ([14 x i8]* @"\01L_OBJC_METH_VAR_NAME_0" to %struct.objc_selector*), section "__OBJC,__message_refs,literal_pointers,no_dead_strip"		; <%struct.objc_selector**> [#uses=2]
 @"\01L_OBJC_SYMBOLS" = internal global { i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] } { i32 0, %struct.objc_selector** null, i16 1, i16 0, [1 x %struct._objc_class*] [ %struct._objc_class* @"\01L_OBJC_CLASS_NSBitmapImageRep" ] }, section "__OBJC,__symbols,regular,no_dead_strip"		; <{ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }*> [#uses=2]
 @"\01L_OBJC_METH_VAR_NAME_0" = internal global [14 x i8] c"copyWithZone:\00", section "__TEXT,__cstring,cstring_literals", align 4		; <[14 x i8]*> [#uses=2]
 @"\01L_OBJC_METH_VAR_TYPE_0" = internal global [20 x i8] c"@12@0:4^{_NSZone=}8\00", section "__TEXT,__cstring,cstring_literals", align 4		; <[20 x i8]*> [#uses=1]
-@"\01L_OBJC_INSTANCE_METHODS_NSBitmapImageRep" = internal global { i8*, i32, [1 x %struct._objc_method] } { i8* null, i32 1, [1 x %struct._objc_method] [ %struct._objc_method { %struct.objc_selector* bitcast ([14 x i8]* @"\01L_OBJC_METH_VAR_NAME_0" to %struct.objc_selector*), i8* getelementptr ([20 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0), i8* bitcast (%struct.objc_object* (%struct.NSBitmapImageRep*, %struct.objc_selector*, %struct.NSZone*)* @"-[NSBitmapImageRep copyWithZone:]" to i8*) } ] }, section "__OBJC,__inst_meth,regular,no_dead_strip"		; <{ i8*, i32, [1 x %struct._objc_method] }*> [#uses=2]
+@"\01L_OBJC_INSTANCE_METHODS_NSBitmapImageRep" = internal global { i8*, i32, [1 x %struct._objc_method] } { i8* null, i32 1, [1 x %struct._objc_method] [ %struct._objc_method { %struct.objc_selector* bitcast ([14 x i8]* @"\01L_OBJC_METH_VAR_NAME_0" to %struct.objc_selector*), i8* getelementptr ([20 x i8], [20 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0), i8* bitcast (%struct.objc_object* (%struct.NSBitmapImageRep*, %struct.objc_selector*, %struct.NSZone*)* @"-[NSBitmapImageRep copyWithZone:]" to i8*) } ] }, section "__OBJC,__inst_meth,regular,no_dead_strip"		; <{ i8*, i32, [1 x %struct._objc_method] }*> [#uses=2]
 @"\01L_OBJC_CLASS_NAME_0" = internal global [17 x i8] c"NSBitmapImageRep\00", section "__TEXT,__cstring,cstring_literals", align 4		; <[17 x i8]*> [#uses=1]
 @"\01L_OBJC_CLASS_NAME_1" = internal global [11 x i8] c"NSImageRep\00", section "__TEXT,__cstring,cstring_literals", align 4		; <[11 x i8]*> [#uses=2]
-@"\01L_OBJC_METACLASS_NSBitmapImageRep" = internal global %struct._objc_class { %struct._objc_class* bitcast ([11 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), %struct._objc_class* bitcast ([11 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), i8* getelementptr ([17 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i32 0, i32 2, i32 48, %struct._objc_ivar_list* null, %struct._objc_method_list* null, %struct.objc_cache* null, %struct._objc_protocol** null, i8* null, %struct._objc_class_ext* null }, section "__OBJC,__meta_class,regular,no_dead_strip"		; <%struct._objc_class*> [#uses=2]
+@"\01L_OBJC_METACLASS_NSBitmapImageRep" = internal global %struct._objc_class { %struct._objc_class* bitcast ([11 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), %struct._objc_class* bitcast ([11 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), i8* getelementptr ([17 x i8], [17 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i32 0, i32 2, i32 48, %struct._objc_ivar_list* null, %struct._objc_method_list* null, %struct.objc_cache* null, %struct._objc_protocol** null, i8* null, %struct._objc_class_ext* null }, section "__OBJC,__meta_class,regular,no_dead_strip"		; <%struct._objc_class*> [#uses=2]
 @"\01L_OBJC_METH_VAR_NAME_1" = internal global [34 x i8] c"_performBlockUsingBackingCGImage:\00", section "__TEXT,__cstring,cstring_literals", align 4		; <[34 x i8]*> [#uses=2]
 @"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] zeroinitializer, section "__OBJC, __image_info,regular"		; <[2 x i32]*> [#uses=1]
 @"\01L_OBJC_CLASS_NAME_2" = internal global [1 x i8] zeroinitializer, section "__TEXT,__cstring,cstring_literals", align 4		; <[1 x i8]*> [#uses=1]
-@"\01L_OBJC_MODULES" = internal global %struct._objc_module { i32 7, i32 16, i8* getelementptr ([1 x i8]* @"\01L_OBJC_CLASS_NAME_2", i32 0, i32 0), %struct._objc_symtab* bitcast ({ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }* @"\01L_OBJC_SYMBOLS" to %struct._objc_symtab*) }, section "__OBJC,__module_info,regular,no_dead_strip"		; <%struct._objc_module*> [#uses=1]
-@llvm.used = appending global [14 x i8*] [ i8* bitcast (%struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_1" to i8*), i8* bitcast (%struct._objc_class* @"\01L_OBJC_CLASS_NSBitmapImageRep" to i8*), i8* bitcast (%struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_0" to i8*), i8* bitcast ({ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }* @"\01L_OBJC_SYMBOLS" to i8*), i8* getelementptr ([14 x i8]* @"\01L_OBJC_METH_VAR_NAME_0", i32 0, i32 0), i8* getelementptr ([20 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0), i8* bitcast ({ i8*, i32, [1 x %struct._objc_method] }* @"\01L_OBJC_INSTANCE_METHODS_NSBitmapImageRep" to i8*), i8* getelementptr ([17 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i8* getelementptr ([11 x i8]* @"\01L_OBJC_CLASS_NAME_1", i32 0, i32 0), i8* bitcast (%struct._objc_class* @"\01L_OBJC_METACLASS_NSBitmapImageRep" to i8*), i8* getelementptr ([34 x i8]* @"\01L_OBJC_METH_VAR_NAME_1", i32 0, i32 0), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*), i8* getelementptr ([1 x i8]* @"\01L_OBJC_CLASS_NAME_2", i32 0, i32 0), i8* bitcast (%struct._objc_module* @"\01L_OBJC_MODULES" to i8*) ], section "llvm.metadata"		; <[14 x i8*]*> [#uses=0]
+@"\01L_OBJC_MODULES" = internal global %struct._objc_module { i32 7, i32 16, i8* getelementptr ([1 x i8], [1 x i8]* @"\01L_OBJC_CLASS_NAME_2", i32 0, i32 0), %struct._objc_symtab* bitcast ({ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }* @"\01L_OBJC_SYMBOLS" to %struct._objc_symtab*) }, section "__OBJC,__module_info,regular,no_dead_strip"		; <%struct._objc_module*> [#uses=1]
+@llvm.used = appending global [14 x i8*] [ i8* bitcast (%struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_1" to i8*), i8* bitcast (%struct._objc_class* @"\01L_OBJC_CLASS_NSBitmapImageRep" to i8*), i8* bitcast (%struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_0" to i8*), i8* bitcast ({ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }* @"\01L_OBJC_SYMBOLS" to i8*), i8* getelementptr ([14 x i8], [14 x i8]* @"\01L_OBJC_METH_VAR_NAME_0", i32 0, i32 0), i8* getelementptr ([20 x i8], [20 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0), i8* bitcast ({ i8*, i32, [1 x %struct._objc_method] }* @"\01L_OBJC_INSTANCE_METHODS_NSBitmapImageRep" to i8*), i8* getelementptr ([17 x i8], [17 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i8* getelementptr ([11 x i8], [11 x i8]* @"\01L_OBJC_CLASS_NAME_1", i32 0, i32 0), i8* bitcast (%struct._objc_class* @"\01L_OBJC_METACLASS_NSBitmapImageRep" to i8*), i8* getelementptr ([34 x i8], [34 x i8]* @"\01L_OBJC_METH_VAR_NAME_1", i32 0, i32 0), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*), i8* getelementptr ([1 x i8], [1 x i8]* @"\01L_OBJC_CLASS_NAME_2", i32 0, i32 0), i8* bitcast (%struct._objc_module* @"\01L_OBJC_MODULES" to i8*) ], section "llvm.metadata"		; <[14 x i8*]*> [#uses=0]
 
 define internal %struct.objc_object* @"-[NSBitmapImageRep copyWithZone:]"(%struct.NSBitmapImageRep* %self, %struct.objc_selector* %_cmd, %struct.NSZone* %zone) nounwind {
 entry:
@@ -62,55 +62,55 @@ entry:
 	store %struct.NSBitmapImageRep* %self, %struct.NSBitmapImageRep** %self_addr
 	store %struct.objc_selector* %_cmd, %struct.objc_selector** %_cmd_addr
 	store %struct.NSZone* %zone, %struct.NSZone** %zone_addr
-	%3 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 0		; <%struct.NSBitmapImageRep**> [#uses=1]
-	%4 = load %struct.NSBitmapImageRep** %self_addr, align 4		; <%struct.NSBitmapImageRep*> [#uses=1]
+	%3 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]", %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 0		; <%struct.NSBitmapImageRep**> [#uses=1]
+	%4 = load %struct.NSBitmapImageRep*, %struct.NSBitmapImageRep** %self_addr, align 4		; <%struct.NSBitmapImageRep*> [#uses=1]
 	store %struct.NSBitmapImageRep* %4, %struct.NSBitmapImageRep** %3, align 4
 	%TRAMP.91 = bitcast %struct.__builtin_trampoline* %TRAMP.9 to i8*		; <i8*> [#uses=1]
 	%FRAME.72 = bitcast %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7 to i8*		; <i8*> [#uses=1]
 	call void @llvm.init.trampoline(i8* %TRAMP.91, i8* bitcast (void (%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"*, %struct.__block_1*, %struct.CGImage*)* @__helper_1.1632 to i8*), i8* %FRAME.72)		; <i8*> [#uses=1]
         %tramp = call i8* @llvm.adjust.trampoline(i8* %TRAMP.91)
 	store i8* %tramp, i8** %0, align 4
-	%5 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 1		; <void (%struct.__block_1*, %struct.CGImage*)**> [#uses=1]
-	%6 = load i8** %0, align 4		; <i8*> [#uses=1]
+	%5 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]", %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 1		; <void (%struct.__block_1*, %struct.CGImage*)**> [#uses=1]
+	%6 = load i8*, i8** %0, align 4		; <i8*> [#uses=1]
 	%7 = bitcast i8* %6 to void (%struct.__block_1*, %struct.CGImage*)*		; <void (%struct.__block_1*, %struct.CGImage*)*> [#uses=1]
 	store void (%struct.__block_1*, %struct.CGImage*)* %7, void (%struct.__block_1*, %struct.CGImage*)** %5, align 4
 	store %struct.NSBitmapImageRep* null, %struct.NSBitmapImageRep** %new, align 4
-	%8 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0		; <%struct.__invoke_impl*> [#uses=1]
-	%9 = getelementptr %struct.__invoke_impl* %8, i32 0, i32 0		; <i8**> [#uses=1]
+	%8 = getelementptr %struct.__block_1, %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0		; <%struct.__invoke_impl*> [#uses=1]
+	%9 = getelementptr %struct.__invoke_impl, %struct.__invoke_impl* %8, i32 0, i32 0		; <i8**> [#uses=1]
 	store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** %9, align 4
-	%10 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0		; <%struct.__invoke_impl*> [#uses=1]
-	%11 = getelementptr %struct.__invoke_impl* %10, i32 0, i32 1		; <i32*> [#uses=1]
+	%10 = getelementptr %struct.__block_1, %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0		; <%struct.__invoke_impl*> [#uses=1]
+	%11 = getelementptr %struct.__invoke_impl, %struct.__invoke_impl* %10, i32 0, i32 1		; <i32*> [#uses=1]
 	store i32 67108864, i32* %11, align 4
-	%12 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0		; <%struct.__invoke_impl*> [#uses=1]
-	%13 = getelementptr %struct.__invoke_impl* %12, i32 0, i32 2		; <i32*> [#uses=1]
+	%12 = getelementptr %struct.__block_1, %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0		; <%struct.__invoke_impl*> [#uses=1]
+	%13 = getelementptr %struct.__invoke_impl, %struct.__invoke_impl* %12, i32 0, i32 2		; <i32*> [#uses=1]
 	store i32 24, i32* %13, align 4
-	%14 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 1		; <void (%struct.__block_1*, %struct.CGImage*)**> [#uses=1]
-	%15 = load void (%struct.__block_1*, %struct.CGImage*)** %14, align 4		; <void (%struct.__block_1*, %struct.CGImage*)*> [#uses=1]
+	%14 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]", %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 1		; <void (%struct.__block_1*, %struct.CGImage*)**> [#uses=1]
+	%15 = load void (%struct.__block_1*, %struct.CGImage*)*, void (%struct.__block_1*, %struct.CGImage*)** %14, align 4		; <void (%struct.__block_1*, %struct.CGImage*)*> [#uses=1]
 	store void (%struct.__block_1*, %struct.CGImage*)* %15, void (%struct.__block_1*, %struct.CGImage*)** %1, align 4
-	%16 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0		; <%struct.__invoke_impl*> [#uses=1]
-	%17 = getelementptr %struct.__invoke_impl* %16, i32 0, i32 3		; <i8**> [#uses=1]
-	%18 = load void (%struct.__block_1*, %struct.CGImage*)** %1, align 4		; <void (%struct.__block_1*, %struct.CGImage*)*> [#uses=1]
+	%16 = getelementptr %struct.__block_1, %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0		; <%struct.__invoke_impl*> [#uses=1]
+	%17 = getelementptr %struct.__invoke_impl, %struct.__invoke_impl* %16, i32 0, i32 3		; <i8**> [#uses=1]
+	%18 = load void (%struct.__block_1*, %struct.CGImage*)*, void (%struct.__block_1*, %struct.CGImage*)** %1, align 4		; <void (%struct.__block_1*, %struct.CGImage*)*> [#uses=1]
 	%19 = bitcast void (%struct.__block_1*, %struct.CGImage*)* %18 to i8*		; <i8*> [#uses=1]
 	store i8* %19, i8** %17, align 4
-	%20 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 1		; <%struct.NSZone**> [#uses=1]
-	%21 = load %struct.NSZone** %zone_addr, align 4		; <%struct.NSZone*> [#uses=1]
+	%20 = getelementptr %struct.__block_1, %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 1		; <%struct.NSZone**> [#uses=1]
+	%21 = load %struct.NSZone*, %struct.NSZone** %zone_addr, align 4		; <%struct.NSZone*> [#uses=1]
 	store %struct.NSZone* %21, %struct.NSZone** %20, align 4
-	%22 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 2		; <%struct.NSBitmapImageRep***> [#uses=1]
+	%22 = getelementptr %struct.__block_1, %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 2		; <%struct.NSBitmapImageRep***> [#uses=1]
 	store %struct.NSBitmapImageRep** %new, %struct.NSBitmapImageRep*** %22, align 4
-	%23 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 0		; <%struct.NSBitmapImageRep**> [#uses=1]
-	%24 = load %struct.NSBitmapImageRep** %23, align 4		; <%struct.NSBitmapImageRep*> [#uses=1]
+	%23 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]", %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 0		; <%struct.NSBitmapImageRep**> [#uses=1]
+	%24 = load %struct.NSBitmapImageRep*, %struct.NSBitmapImageRep** %23, align 4		; <%struct.NSBitmapImageRep*> [#uses=1]
 	store %struct.NSBitmapImageRep* %24, %struct.NSBitmapImageRep** %2, align 4
-	%25 = load %struct.NSBitmapImageRep** %2, align 4		; <%struct.NSBitmapImageRep*> [#uses=1]
+	%25 = load %struct.NSBitmapImageRep*, %struct.NSBitmapImageRep** %2, align 4		; <%struct.NSBitmapImageRep*> [#uses=1]
 	%26 = bitcast %struct.NSBitmapImageRep* %25 to %struct.objc_object*		; <%struct.objc_object*> [#uses=1]
 	store %struct.objc_object* %26, %struct.objc_object** %self.1, align 4
-	%27 = load %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_1", align 4		; <%struct.objc_selector*> [#uses=1]
+	%27 = load %struct.objc_selector*, %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_1", align 4		; <%struct.objc_selector*> [#uses=1]
 	%__block_holder_tmp_1.03 = bitcast %struct.__block_1* %__block_holder_tmp_1.0 to void (%struct.CGImage*)*		; <void (%struct.CGImage*)*> [#uses=1]
-	%28 = load %struct.objc_object** %self.1, align 4		; <%struct.objc_object*> [#uses=1]
-	%29 = call %struct.objc_object* (%struct.objc_object*, %struct.objc_selector*, ...)* inttoptr (i64 4294901504 to %struct.objc_object* (%struct.objc_object*, %struct.objc_selector*, ...)*)(%struct.objc_object* %28, %struct.objc_selector* %27, void (%struct.CGImage*)* %__block_holder_tmp_1.03) nounwind		; <%struct.objc_object*> [#uses=0]
+	%28 = load %struct.objc_object*, %struct.objc_object** %self.1, align 4		; <%struct.objc_object*> [#uses=1]
+	%29 = call %struct.objc_object* (%struct.objc_object*, %struct.objc_selector*, ...) inttoptr (i64 4294901504 to %struct.objc_object* (%struct.objc_object*, %struct.objc_selector*, ...)*)(%struct.objc_object* %28, %struct.objc_selector* %27, void (%struct.CGImage*)* %__block_holder_tmp_1.03) nounwind		; <%struct.objc_object*> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
-	%retval5 = load %struct.objc_object** %retval		; <%struct.objc_object*> [#uses=1]
+	%retval5 = load %struct.objc_object*, %struct.objc_object** %retval		; <%struct.objc_object*> [#uses=1]
 	ret %struct.objc_object* %retval5
 }
 
@@ -131,33 +131,33 @@ entry:
 	store %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %CHAIN.8, %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"** %CHAIN.8_addr
 	store %struct.__block_1* %_self, %struct.__block_1** %_self_addr
 	store %struct.CGImage* %cgImage, %struct.CGImage** %cgImage_addr
-	%1 = load %struct.__block_1** %_self_addr, align 4		; <%struct.__block_1*> [#uses=1]
-	%2 = getelementptr %struct.__block_1* %1, i32 0, i32 2		; <%struct.NSBitmapImageRep***> [#uses=1]
-	%3 = load %struct.NSBitmapImageRep*** %2, align 4		; <%struct.NSBitmapImageRep**> [#uses=1]
+	%1 = load %struct.__block_1*, %struct.__block_1** %_self_addr, align 4		; <%struct.__block_1*> [#uses=1]
+	%2 = getelementptr %struct.__block_1, %struct.__block_1* %1, i32 0, i32 2		; <%struct.NSBitmapImageRep***> [#uses=1]
+	%3 = load %struct.NSBitmapImageRep**, %struct.NSBitmapImageRep*** %2, align 4		; <%struct.NSBitmapImageRep**> [#uses=1]
 	store %struct.NSBitmapImageRep** %3, %struct.NSBitmapImageRep*** %new, align 4
-	%4 = load %struct.__block_1** %_self_addr, align 4		; <%struct.__block_1*> [#uses=1]
-	%5 = getelementptr %struct.__block_1* %4, i32 0, i32 1		; <%struct.NSZone**> [#uses=1]
-	%6 = load %struct.NSZone** %5, align 4		; <%struct.NSZone*> [#uses=1]
+	%4 = load %struct.__block_1*, %struct.__block_1** %_self_addr, align 4		; <%struct.__block_1*> [#uses=1]
+	%5 = getelementptr %struct.__block_1, %struct.__block_1* %4, i32 0, i32 1		; <%struct.NSZone**> [#uses=1]
+	%6 = load %struct.NSZone*, %struct.NSZone** %5, align 4		; <%struct.NSZone*> [#uses=1]
 	store %struct.NSZone* %6, %struct.NSZone** %zone, align 4
-	%7 = load %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"** %CHAIN.8_addr, align 4		; <%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"*> [#uses=1]
-	%8 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %7, i32 0, i32 0		; <%struct.NSBitmapImageRep**> [#uses=1]
-	%9 = load %struct.NSBitmapImageRep** %8, align 4		; <%struct.NSBitmapImageRep*> [#uses=1]
+	%7 = load %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"*, %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"** %CHAIN.8_addr, align 4		; <%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"*> [#uses=1]
+	%8 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]", %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %7, i32 0, i32 0		; <%struct.NSBitmapImageRep**> [#uses=1]
+	%9 = load %struct.NSBitmapImageRep*, %struct.NSBitmapImageRep** %8, align 4		; <%struct.NSBitmapImageRep*> [#uses=1]
 	store %struct.NSBitmapImageRep* %9, %struct.NSBitmapImageRep** %0, align 4
-	%10 = load %struct.NSBitmapImageRep** %0, align 4		; <%struct.NSBitmapImageRep*> [#uses=1]
+	%10 = load %struct.NSBitmapImageRep*, %struct.NSBitmapImageRep** %0, align 4		; <%struct.NSBitmapImageRep*> [#uses=1]
 	%11 = bitcast %struct.NSBitmapImageRep* %10 to %struct.objc_object*		; <%struct.objc_object*> [#uses=1]
-	%12 = getelementptr %struct._objc_super* %objc_super, i32 0, i32 0		; <%struct.objc_object**> [#uses=1]
+	%12 = getelementptr %struct._objc_super, %struct._objc_super* %objc_super, i32 0, i32 0		; <%struct.objc_object**> [#uses=1]
 	store %struct.objc_object* %11, %struct.objc_object** %12, align 4
-	%13 = load %struct._objc_class** getelementptr (%struct._objc_class* @"\01L_OBJC_CLASS_NSBitmapImageRep", i32 0, i32 1), align 4		; <%struct._objc_class*> [#uses=1]
-	%14 = getelementptr %struct._objc_super* %objc_super, i32 0, i32 1		; <%struct._objc_class**> [#uses=1]
+	%13 = load %struct._objc_class*, %struct._objc_class** getelementptr (%struct._objc_class, %struct._objc_class* @"\01L_OBJC_CLASS_NSBitmapImageRep", i32 0, i32 1), align 4		; <%struct._objc_class*> [#uses=1]
+	%14 = getelementptr %struct._objc_super, %struct._objc_super* %objc_super, i32 0, i32 1		; <%struct._objc_class**> [#uses=1]
 	store %struct._objc_class* %13, %struct._objc_class** %14, align 4
 	%objc_super1 = bitcast %struct._objc_super* %objc_super to %struct.objc_super*		; <%struct.objc_super*> [#uses=1]
 	store %struct.objc_super* %objc_super1, %struct.objc_super** %objc_super.5, align 4
-	%15 = load %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_0", align 4		; <%struct.objc_selector*> [#uses=1]
-	%16 = load %struct.objc_super** %objc_super.5, align 4		; <%struct.objc_super*> [#uses=1]
-	%17 = load %struct.NSZone** %zone, align 4		; <%struct.NSZone*> [#uses=1]
-	%18 = call %struct.objc_object* (%struct.objc_super*, %struct.objc_selector*, ...)* @objc_msgSendSuper(%struct.objc_super* %16, %struct.objc_selector* %15, %struct.NSZone* %17) nounwind		; <%struct.objc_object*> [#uses=1]
+	%15 = load %struct.objc_selector*, %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_0", align 4		; <%struct.objc_selector*> [#uses=1]
+	%16 = load %struct.objc_super*, %struct.objc_super** %objc_super.5, align 4		; <%struct.objc_super*> [#uses=1]
+	%17 = load %struct.NSZone*, %struct.NSZone** %zone, align 4		; <%struct.NSZone*> [#uses=1]
+	%18 = call %struct.objc_object* (%struct.objc_super*, %struct.objc_selector*, ...) @objc_msgSendSuper(%struct.objc_super* %16, %struct.objc_selector* %15, %struct.NSZone* %17) nounwind		; <%struct.objc_object*> [#uses=1]
 	%19 = bitcast %struct.objc_object* %18 to %struct.NSBitmapImageRep*		; <%struct.NSBitmapImageRep*> [#uses=1]
-	%20 = load %struct.NSBitmapImageRep*** %new, align 4		; <%struct.NSBitmapImageRep**> [#uses=1]
+	%20 = load %struct.NSBitmapImageRep**, %struct.NSBitmapImageRep*** %new, align 4		; <%struct.NSBitmapImageRep**> [#uses=1]
 	store %struct.NSBitmapImageRep* %19, %struct.NSBitmapImageRep** %20, align 4
 	br label %return
 
diff --git a/test/CodeGen/PowerPC/unal-altivec-wint.ll b/test/CodeGen/PowerPC/unal-altivec-wint.ll
index 7e0963f54b33..b71a98bc83bb 100644
--- a/test/CodeGen/PowerPC/unal-altivec-wint.ll
+++ b/test/CodeGen/PowerPC/unal-altivec-wint.ll
@@ -6,11 +6,11 @@ declare <4 x i32> @llvm.ppc.altivec.lvx(i8*) #1
 
 define <4 x i32> @test1(<4 x i32>* %h) #0 {
 entry:
-  %h1 = getelementptr <4 x i32>* %h, i64 1
+  %h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
   %hv = bitcast <4 x i32>* %h1 to i8*
   %vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
 
-  %v0 = load <4 x i32>* %h, align 8
+  %v0 = load <4 x i32>, <4 x i32>* %h, align 8
 
   %a = add <4 x i32> %v0, %vl
   ret <4 x i32> %a
@@ -27,11 +27,11 @@ declare void @llvm.ppc.altivec.stvx(<4 x i32>, i8*) #0
 
 define <4 x i32> @test2(<4 x i32>* %h, <4 x i32> %d) #0 {
 entry:
-  %h1 = getelementptr <4 x i32>* %h, i64 1
+  %h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
   %hv = bitcast <4 x i32>* %h1 to i8*
   call void @llvm.ppc.altivec.stvx(<4 x i32> %d, i8* %hv)
 
-  %v0 = load <4 x i32>* %h, align 8
+  %v0 = load <4 x i32>, <4 x i32>* %h, align 8
 
   ret <4 x i32> %v0
 
diff --git a/test/CodeGen/PowerPC/unal-altivec.ll b/test/CodeGen/PowerPC/unal-altivec.ll
index 7f333a1c508b..02f7ab40f049 100644
--- a/test/CodeGen/PowerPC/unal-altivec.ll
+++ b/test/CodeGen/PowerPC/unal-altivec.ll
@@ -8,20 +8,20 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %0 = getelementptr inbounds float* %b, i64 %index
+  %0 = getelementptr inbounds float, float* %b, i64 %index
   %1 = bitcast float* %0 to <4 x float>*
-  %wide.load = load <4 x float>* %1, align 4
+  %wide.load = load <4 x float>, <4 x float>* %1, align 4
   %.sum11 = or i64 %index, 4
-  %2 = getelementptr float* %b, i64 %.sum11
+  %2 = getelementptr float, float* %b, i64 %.sum11
   %3 = bitcast float* %2 to <4 x float>*
-  %wide.load8 = load <4 x float>* %3, align 4
+  %wide.load8 = load <4 x float>, <4 x float>* %3, align 4
   %4 = fadd <4 x float> %wide.load, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
   %5 = fadd <4 x float> %wide.load8, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
-  %6 = getelementptr inbounds float* %a, i64 %index
+  %6 = getelementptr inbounds float, float* %a, i64 %index
   %7 = bitcast float* %6 to <4 x float>*
   store <4 x float> %4, <4 x float>* %7, align 4
   %.sum12 = or i64 %index, 4
-  %8 = getelementptr float* %a, i64 %.sum12
+  %8 = getelementptr float, float* %a, i64 %.sum12
   %9 = bitcast float* %8 to <4 x float>*
   store <4 x float> %5, <4 x float>* %9, align 4
   %index.next = add i64 %index, 8
diff --git a/test/CodeGen/PowerPC/unal-altivec2.ll b/test/CodeGen/PowerPC/unal-altivec2.ll
index 7464675470f9..0d15b977ca18 100644
--- a/test/CodeGen/PowerPC/unal-altivec2.ll
+++ b/test/CodeGen/PowerPC/unal-altivec2.ll
@@ -12,131 +12,131 @@ vector.body:                                      ; preds = %vector.body, %entry
 ; CHECK: lvsl
 ; CHECK: blr
   %index = phi i64 [ 0, %entry ], [ %index.next.15, %vector.body ]
-  %0 = getelementptr inbounds float* %y, i64 %index
+  %0 = getelementptr inbounds float, float* %y, i64 %index
   %1 = bitcast float* %0 to <4 x float>*
-  %wide.load = load <4 x float>* %1, align 4
+  %wide.load = load <4 x float>, <4 x float>* %1, align 4
   %2 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load)
-  %3 = getelementptr inbounds float* %x, i64 %index
+  %3 = getelementptr inbounds float, float* %x, i64 %index
   %4 = bitcast float* %3 to <4 x float>*
   store <4 x float> %2, <4 x float>* %4, align 4
   %index.next = add i64 %index, 4
-  %5 = getelementptr inbounds float* %y, i64 %index.next
+  %5 = getelementptr inbounds float, float* %y, i64 %index.next
   %6 = bitcast float* %5 to <4 x float>*
-  %wide.load.1 = load <4 x float>* %6, align 4
+  %wide.load.1 = load <4 x float>, <4 x float>* %6, align 4
   %7 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.1)
-  %8 = getelementptr inbounds float* %x, i64 %index.next
+  %8 = getelementptr inbounds float, float* %x, i64 %index.next
   %9 = bitcast float* %8 to <4 x float>*
   store <4 x float> %7, <4 x float>* %9, align 4
   %index.next.1 = add i64 %index.next, 4
-  %10 = getelementptr inbounds float* %y, i64 %index.next.1
+  %10 = getelementptr inbounds float, float* %y, i64 %index.next.1
   %11 = bitcast float* %10 to <4 x float>*
-  %wide.load.2 = load <4 x float>* %11, align 4
+  %wide.load.2 = load <4 x float>, <4 x float>* %11, align 4
   %12 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.2)
-  %13 = getelementptr inbounds float* %x, i64 %index.next.1
+  %13 = getelementptr inbounds float, float* %x, i64 %index.next.1
   %14 = bitcast float* %13 to <4 x float>*
   store <4 x float> %12, <4 x float>* %14, align 4
   %index.next.2 = add i64 %index.next.1, 4
-  %15 = getelementptr inbounds float* %y, i64 %index.next.2
+  %15 = getelementptr inbounds float, float* %y, i64 %index.next.2
   %16 = bitcast float* %15 to <4 x float>*
-  %wide.load.3 = load <4 x float>* %16, align 4
+  %wide.load.3 = load <4 x float>, <4 x float>* %16, align 4
   %17 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.3)
-  %18 = getelementptr inbounds float* %x, i64 %index.next.2
+  %18 = getelementptr inbounds float, float* %x, i64 %index.next.2
   %19 = bitcast float* %18 to <4 x float>*
   store <4 x float> %17, <4 x float>* %19, align 4
   %index.next.3 = add i64 %index.next.2, 4
-  %20 = getelementptr inbounds float* %y, i64 %index.next.3
+  %20 = getelementptr inbounds float, float* %y, i64 %index.next.3
   %21 = bitcast float* %20 to <4 x float>*
-  %wide.load.4 = load <4 x float>* %21, align 4
+  %wide.load.4 = load <4 x float>, <4 x float>* %21, align 4
   %22 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.4)
-  %23 = getelementptr inbounds float* %x, i64 %index.next.3
+  %23 = getelementptr inbounds float, float* %x, i64 %index.next.3
   %24 = bitcast float* %23 to <4 x float>*
   store <4 x float> %22, <4 x float>* %24, align 4
   %index.next.4 = add i64 %index.next.3, 4
-  %25 = getelementptr inbounds float* %y, i64 %index.next.4
+  %25 = getelementptr inbounds float, float* %y, i64 %index.next.4
   %26 = bitcast float* %25 to <4 x float>*
-  %wide.load.5 = load <4 x float>* %26, align 4
+  %wide.load.5 = load <4 x float>, <4 x float>* %26, align 4
   %27 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.5)
-  %28 = getelementptr inbounds float* %x, i64 %index.next.4
+  %28 = getelementptr inbounds float, float* %x, i64 %index.next.4
   %29 = bitcast float* %28 to <4 x float>*
   store <4 x float> %27, <4 x float>* %29, align 4
   %index.next.5 = add i64 %index.next.4, 4
-  %30 = getelementptr inbounds float* %y, i64 %index.next.5
+  %30 = getelementptr inbounds float, float* %y, i64 %index.next.5
   %31 = bitcast float* %30 to <4 x float>*
-  %wide.load.6 = load <4 x float>* %31, align 4
+  %wide.load.6 = load <4 x float>, <4 x float>* %31, align 4
   %32 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.6)
-  %33 = getelementptr inbounds float* %x, i64 %index.next.5
+  %33 = getelementptr inbounds float, float* %x, i64 %index.next.5
   %34 = bitcast float* %33 to <4 x float>*
   store <4 x float> %32, <4 x float>* %34, align 4
   %index.next.6 = add i64 %index.next.5, 4
-  %35 = getelementptr inbounds float* %y, i64 %index.next.6
+  %35 = getelementptr inbounds float, float* %y, i64 %index.next.6
   %36 = bitcast float* %35 to <4 x float>*
-  %wide.load.7 = load <4 x float>* %36, align 4
+  %wide.load.7 = load <4 x float>, <4 x float>* %36, align 4
   %37 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.7)
-  %38 = getelementptr inbounds float* %x, i64 %index.next.6
+  %38 = getelementptr inbounds float, float* %x, i64 %index.next.6
   %39 = bitcast float* %38 to <4 x float>*
   store <4 x float> %37, <4 x float>* %39, align 4
   %index.next.7 = add i64 %index.next.6, 4
-  %40 = getelementptr inbounds float* %y, i64 %index.next.7
+  %40 = getelementptr inbounds float, float* %y, i64 %index.next.7
   %41 = bitcast float* %40 to <4 x float>*
-  %wide.load.8 = load <4 x float>* %41, align 4
+  %wide.load.8 = load <4 x float>, <4 x float>* %41, align 4
   %42 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.8)
-  %43 = getelementptr inbounds float* %x, i64 %index.next.7
+  %43 = getelementptr inbounds float, float* %x, i64 %index.next.7
   %44 = bitcast float* %43 to <4 x float>*
   store <4 x float> %42, <4 x float>* %44, align 4
   %index.next.8 = add i64 %index.next.7, 4
-  %45 = getelementptr inbounds float* %y, i64 %index.next.8
+  %45 = getelementptr inbounds float, float* %y, i64 %index.next.8
   %46 = bitcast float* %45 to <4 x float>*
-  %wide.load.9 = load <4 x float>* %46, align 4
+  %wide.load.9 = load <4 x float>, <4 x float>* %46, align 4
   %47 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.9)
-  %48 = getelementptr inbounds float* %x, i64 %index.next.8
+  %48 = getelementptr inbounds float, float* %x, i64 %index.next.8
   %49 = bitcast float* %48 to <4 x float>*
   store <4 x float> %47, <4 x float>* %49, align 4
   %index.next.9 = add i64 %index.next.8, 4
-  %50 = getelementptr inbounds float* %y, i64 %index.next.9
+  %50 = getelementptr inbounds float, float* %y, i64 %index.next.9
   %51 = bitcast float* %50 to <4 x float>*
-  %wide.load.10 = load <4 x float>* %51, align 4
+  %wide.load.10 = load <4 x float>, <4 x float>* %51, align 4
   %52 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.10)
-  %53 = getelementptr inbounds float* %x, i64 %index.next.9
+  %53 = getelementptr inbounds float, float* %x, i64 %index.next.9
   %54 = bitcast float* %53 to <4 x float>*
   store <4 x float> %52, <4 x float>* %54, align 4
   %index.next.10 = add i64 %index.next.9, 4
-  %55 = getelementptr inbounds float* %y, i64 %index.next.10
+  %55 = getelementptr inbounds float, float* %y, i64 %index.next.10
   %56 = bitcast float* %55 to <4 x float>*
-  %wide.load.11 = load <4 x float>* %56, align 4
+  %wide.load.11 = load <4 x float>, <4 x float>* %56, align 4
   %57 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.11)
-  %58 = getelementptr inbounds float* %x, i64 %index.next.10
+  %58 = getelementptr inbounds float, float* %x, i64 %index.next.10
   %59 = bitcast float* %58 to <4 x float>*
   store <4 x float> %57, <4 x float>* %59, align 4
   %index.next.11 = add i64 %index.next.10, 4
-  %60 = getelementptr inbounds float* %y, i64 %index.next.11
+  %60 = getelementptr inbounds float, float* %y, i64 %index.next.11
   %61 = bitcast float* %60 to <4 x float>*
-  %wide.load.12 = load <4 x float>* %61, align 4
+  %wide.load.12 = load <4 x float>, <4 x float>* %61, align 4
   %62 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.12)
-  %63 = getelementptr inbounds float* %x, i64 %index.next.11
+  %63 = getelementptr inbounds float, float* %x, i64 %index.next.11
   %64 = bitcast float* %63 to <4 x float>*
   store <4 x float> %62, <4 x float>* %64, align 4
   %index.next.12 = add i64 %index.next.11, 4
-  %65 = getelementptr inbounds float* %y, i64 %index.next.12
+  %65 = getelementptr inbounds float, float* %y, i64 %index.next.12
   %66 = bitcast float* %65 to <4 x float>*
-  %wide.load.13 = load <4 x float>* %66, align 4
+  %wide.load.13 = load <4 x float>, <4 x float>* %66, align 4
   %67 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.13)
-  %68 = getelementptr inbounds float* %x, i64 %index.next.12
+  %68 = getelementptr inbounds float, float* %x, i64 %index.next.12
   %69 = bitcast float* %68 to <4 x float>*
   store <4 x float> %67, <4 x float>* %69, align 4
   %index.next.13 = add i64 %index.next.12, 4
-  %70 = getelementptr inbounds float* %y, i64 %index.next.13
+  %70 = getelementptr inbounds float, float* %y, i64 %index.next.13
   %71 = bitcast float* %70 to <4 x float>*
-  %wide.load.14 = load <4 x float>* %71, align 4
+  %wide.load.14 = load <4 x float>, <4 x float>* %71, align 4
   %72 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.14)
-  %73 = getelementptr inbounds float* %x, i64 %index.next.13
+  %73 = getelementptr inbounds float, float* %x, i64 %index.next.13
   %74 = bitcast float* %73 to <4 x float>*
   store <4 x float> %72, <4 x float>* %74, align 4
   %index.next.14 = add i64 %index.next.13, 4
-  %75 = getelementptr inbounds float* %y, i64 %index.next.14
+  %75 = getelementptr inbounds float, float* %y, i64 %index.next.14
   %76 = bitcast float* %75 to <4 x float>*
-  %wide.load.15 = load <4 x float>* %76, align 4
+  %wide.load.15 = load <4 x float>, <4 x float>* %76, align 4
   %77 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.15)
-  %78 = getelementptr inbounds float* %x, i64 %index.next.14
+  %78 = getelementptr inbounds float, float* %x, i64 %index.next.14
   %79 = bitcast float* %78 to <4 x float>*
   store <4 x float> %77, <4 x float>* %79, align 4
   %index.next.15 = add i64 %index.next.14, 4
@@ -153,7 +153,7 @@ declare <4 x float> @llvm_cos_v4f32(<4 x float>) #1
 define <2 x double> @bar(double* %x) {
 entry:
   %p = bitcast double* %x to <2 x double>*
-  %r = load <2 x double>* %p, align 8
+  %r = load <2 x double>, <2 x double>* %p, align 8
 
 ; CHECK-LABEL: @bar
 ; CHECK-NOT: lvsl
diff --git a/test/CodeGen/PowerPC/unaligned.ll b/test/CodeGen/PowerPC/unaligned.ll
index 64c03cdda35e..6b23b18762d3 100644
--- a/test/CodeGen/PowerPC/unaligned.ll
+++ b/test/CodeGen/PowerPC/unaligned.ll
@@ -5,7 +5,7 @@ target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 
 define void @foo1(i16* %p, i16* %r) nounwind {
 entry:
-  %v = load i16* %p, align 1
+  %v = load i16, i16* %p, align 1
   store i16 %v, i16* %r, align 1
   ret void
 
@@ -20,7 +20,7 @@ entry:
 
 define void @foo2(i32* %p, i32* %r) nounwind {
 entry:
-  %v = load i32* %p, align 1
+  %v = load i32, i32* %p, align 1
   store i32 %v, i32* %r, align 1
   ret void
 
@@ -35,7 +35,7 @@ entry:
 
 define void @foo3(i64* %p, i64* %r) nounwind {
 entry:
-  %v = load i64* %p, align 1
+  %v = load i64, i64* %p, align 1
   store i64 %v, i64* %r, align 1
   ret void
 
@@ -50,7 +50,7 @@ entry:
 
 define void @foo4(float* %p, float* %r) nounwind {
 entry:
-  %v = load float* %p, align 1
+  %v = load float, float* %p, align 1
   store float %v, float* %r, align 1
   ret void
 
@@ -65,7 +65,7 @@ entry:
 
 define void @foo5(double* %p, double* %r) nounwind {
 entry:
-  %v = load double* %p, align 1
+  %v = load double, double* %p, align 1
   store double %v, double* %r, align 1
   ret void
 
@@ -80,7 +80,7 @@ entry:
 
 define void @foo6(<4 x float>* %p, <4 x float>* %r) nounwind {
 entry:
-  %v = load <4 x float>* %p, align 1
+  %v = load <4 x float>, <4 x float>* %p, align 1
   store <4 x float> %v, <4 x float>* %r, align 1
   ret void
 
diff --git a/test/CodeGen/PowerPC/unwind-dw2-g.ll b/test/CodeGen/PowerPC/unwind-dw2-g.ll
index 4ae6ff24a038..8bd158867c79 100644
--- a/test/CodeGen/PowerPC/unwind-dw2-g.ll
+++ b/test/CodeGen/PowerPC/unwind-dw2-g.ll
@@ -21,15 +21,15 @@ attributes #0 = { nounwind }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!8, !11}
 
-!0 = !{!"0x11\0012\00clang version 3.4\000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/unwind-dw2.c] [DW_LANG_C99]
-!1 = !{!"/tmp/unwind-dw2.c", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "/tmp/unwind-dw2.c", directory: "/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\000\000\001", !1, !5, !6, null, void ()* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/unwind-dw2.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void ()* @foo, variables: !2)
+!5 = !DIFile(filename: "/tmp/unwind-dw2.c", directory: "/tmp")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
 !8 = !{i32 2, !"Dwarf Version", i32 3}
-!9 = !MDLocation(line: 2, scope: !4)
-!10 = !MDLocation(line: 3, scope: !4)
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DILocation(line: 2, scope: !4)
+!10 = !DILocation(line: 3, scope: !4)
+!11 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/PowerPC/vaddsplat.ll b/test/CodeGen/PowerPC/vaddsplat.ll
index 4236fabea0a6..70a7ea0c5533 100644
--- a/test/CodeGen/PowerPC/vaddsplat.ll
+++ b/test/CodeGen/PowerPC/vaddsplat.ll
@@ -10,7 +10,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 %v16i8 = type <16 x i8>
 
 define void @test_v4i32_pos_even(%v4i32* %P, %v4i32* %S) {
-       %p = load %v4i32* %P
+       %p = load %v4i32, %v4i32* %P
        %r = add %v4i32 %p, < i32 18, i32 18, i32 18, i32 18 >
        store %v4i32 %r, %v4i32* %S
        ret void
@@ -21,7 +21,7 @@ define void @test_v4i32_pos_even(%v4i32* %P, %v4i32* %S) {
 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]
 
 define void @test_v4i32_neg_even(%v4i32* %P, %v4i32* %S) {
-       %p = load %v4i32* %P
+       %p = load %v4i32, %v4i32* %P
        %r = add %v4i32 %p, < i32 -28, i32 -28, i32 -28, i32 -28 >
        store %v4i32 %r, %v4i32* %S
        ret void
@@ -32,7 +32,7 @@ define void @test_v4i32_neg_even(%v4i32* %P, %v4i32* %S) {
 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]
 
 define void @test_v8i16_pos_even(%v8i16* %P, %v8i16* %S) {
-       %p = load %v8i16* %P
+       %p = load %v8i16, %v8i16* %P
        %r = add %v8i16 %p, < i16 30, i16 30, i16 30, i16 30, i16 30, i16 30, i16 30, i16 30 >
        store %v8i16 %r, %v8i16* %S
        ret void
@@ -43,7 +43,7 @@ define void @test_v8i16_pos_even(%v8i16* %P, %v8i16* %S) {
 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]]
 
 define void @test_v8i16_neg_even(%v8i16* %P, %v8i16* %S) {
-       %p = load %v8i16* %P
+       %p = load %v8i16, %v8i16* %P
        %r = add %v8i16 %p, < i16 -32, i16 -32, i16 -32, i16 -32, i16 -32, i16 -32, i16 -32, i16 -32 >
        store %v8i16 %r, %v8i16* %S
        ret void
@@ -54,7 +54,7 @@ define void @test_v8i16_neg_even(%v8i16* %P, %v8i16* %S) {
 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]]
 
 define void @test_v16i8_pos_even(%v16i8* %P, %v16i8* %S) {
-       %p = load %v16i8* %P
+       %p = load %v16i8, %v16i8* %P
        %r = add %v16i8 %p, < i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16 >
        store %v16i8 %r, %v16i8* %S
        ret void
@@ -65,7 +65,7 @@ define void @test_v16i8_pos_even(%v16i8* %P, %v16i8* %S) {
 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]]
 
 define void @test_v16i8_neg_even(%v16i8* %P, %v16i8* %S) {
-       %p = load %v16i8* %P
+       %p = load %v16i8, %v16i8* %P
        %r = add %v16i8 %p, < i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18 >
        store %v16i8 %r, %v16i8* %S
        ret void
@@ -76,7 +76,7 @@ define void @test_v16i8_neg_even(%v16i8* %P, %v16i8* %S) {
 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]]
 
 define void @test_v4i32_pos_odd(%v4i32* %P, %v4i32* %S) {
-       %p = load %v4i32* %P
+       %p = load %v4i32, %v4i32* %P
        %r = add %v4i32 %p, < i32 27, i32 27, i32 27, i32 27 >
        store %v4i32 %r, %v4i32* %S
        ret void
@@ -88,7 +88,7 @@ define void @test_v4i32_pos_odd(%v4i32* %P, %v4i32* %S) {
 ; CHECK: vsubuwm {{[0-9]+}}, [[REG1]], [[REG2]]
 
 define void @test_v4i32_neg_odd(%v4i32* %P, %v4i32* %S) {
-       %p = load %v4i32* %P
+       %p = load %v4i32, %v4i32* %P
        %r = add %v4i32 %p, < i32 -27, i32 -27, i32 -27, i32 -27 >
        store %v4i32 %r, %v4i32* %S
        ret void
@@ -100,7 +100,7 @@ define void @test_v4i32_neg_odd(%v4i32* %P, %v4i32* %S) {
 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG2]]
 
 define void @test_v8i16_pos_odd(%v8i16* %P, %v8i16* %S) {
-       %p = load %v8i16* %P
+       %p = load %v8i16, %v8i16* %P
        %r = add %v8i16 %p, < i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31 >
        store %v8i16 %r, %v8i16* %S
        ret void
@@ -112,7 +112,7 @@ define void @test_v8i16_pos_odd(%v8i16* %P, %v8i16* %S) {
 ; CHECK: vsubuhm {{[0-9]+}}, [[REG1]], [[REG2]]
 
 define void @test_v8i16_neg_odd(%v8i16* %P, %v8i16* %S) {
-       %p = load %v8i16* %P
+       %p = load %v8i16, %v8i16* %P
        %r = add %v8i16 %p, < i16 -31, i16 -31, i16 -31, i16 -31, i16 -31, i16 -31, i16 -31, i16 -31 >
        store %v8i16 %r, %v8i16* %S
        ret void
@@ -124,7 +124,7 @@ define void @test_v8i16_neg_odd(%v8i16* %P, %v8i16* %S) {
 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG2]]
 
 define void @test_v16i8_pos_odd(%v16i8* %P, %v16i8* %S) {
-       %p = load %v16i8* %P
+       %p = load %v16i8, %v16i8* %P
        %r = add %v16i8 %p, < i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17 >
        store %v16i8 %r, %v16i8* %S
        ret void
@@ -136,7 +136,7 @@ define void @test_v16i8_pos_odd(%v16i8* %P, %v16i8* %S) {
 ; CHECK: vsububm {{[0-9]+}}, [[REG1]], [[REG2]]
 
 define void @test_v16i8_neg_odd(%v16i8* %P, %v16i8* %S) {
-       %p = load %v16i8* %P
+       %p = load %v16i8, %v16i8* %P
        %r = add %v16i8 %p, < i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17 >
        store %v16i8 %r, %v16i8* %S
        ret void
diff --git a/test/CodeGen/PowerPC/varargs-struct-float.ll b/test/CodeGen/PowerPC/varargs-struct-float.ll
index 0fd9fc50892e..7bb5a3444cf5 100644
--- a/test/CodeGen/PowerPC/varargs-struct-float.ll
+++ b/test/CodeGen/PowerPC/varargs-struct-float.ll
@@ -8,11 +8,11 @@ target triple = "powerpc64-unknown-linux-gnu"
 define void @foo(float inreg %s.coerce) nounwind {
 entry:
   %s = alloca %struct.Sf1, align 4
-  %coerce.dive = getelementptr %struct.Sf1* %s, i32 0, i32 0
+  %coerce.dive = getelementptr %struct.Sf1, %struct.Sf1* %s, i32 0, i32 0
   store float %s.coerce, float* %coerce.dive, align 1
-  %coerce.dive1 = getelementptr %struct.Sf1* %s, i32 0, i32 0
-  %0 = load float* %coerce.dive1, align 1
-  call void (i32, ...)* @testvaSf1(i32 1, float inreg %0)
+  %coerce.dive1 = getelementptr %struct.Sf1, %struct.Sf1* %s, i32 0, i32 0
+  %0 = load float, float* %coerce.dive1, align 1
+  call void (i32, ...) @testvaSf1(i32 1, float inreg %0)
   ret void
 }
 
diff --git a/test/CodeGen/PowerPC/vcmp-fold.ll b/test/CodeGen/PowerPC/vcmp-fold.ll
index 7a42c27d2b4a..ee167083d4d6 100644
--- a/test/CodeGen/PowerPC/vcmp-fold.ll
+++ b/test/CodeGen/PowerPC/vcmp-fold.ll
@@ -5,11 +5,11 @@
 
 define void @test(<4 x float>* %x, <4 x float>* %y, i32* %P) {
 entry:
-	%tmp = load <4 x float>* %x		; <<4 x float>> [#uses=1]
-	%tmp2 = load <4 x float>* %y		; <<4 x float>> [#uses=1]
+	%tmp = load <4 x float>, <4 x float>* %x		; <<4 x float>> [#uses=1]
+	%tmp2 = load <4 x float>, <4 x float>* %y		; <<4 x float>> [#uses=1]
 	%tmp.upgrd.1 = call i32 @llvm.ppc.altivec.vcmpbfp.p( i32 1, <4 x float> %tmp, <4 x float> %tmp2 )		; <i32> [#uses=1]
-	%tmp4 = load <4 x float>* %x		; <<4 x float>> [#uses=1]
-	%tmp6 = load <4 x float>* %y		; <<4 x float>> [#uses=1]
+	%tmp4 = load <4 x float>, <4 x float>* %x		; <<4 x float>> [#uses=1]
+	%tmp6 = load <4 x float>, <4 x float>* %y		; <<4 x float>> [#uses=1]
 	%tmp.upgrd.2 = call <4 x i32> @llvm.ppc.altivec.vcmpbfp( <4 x float> %tmp4, <4 x float> %tmp6 )		; <<4 x i32>> [#uses=1]
 	%tmp7 = bitcast <4 x i32> %tmp.upgrd.2 to <4 x float>		; <<4 x float>> [#uses=1]
 	store <4 x float> %tmp7, <4 x float>* %x
diff --git a/test/CodeGen/PowerPC/vec-abi-align.ll b/test/CodeGen/PowerPC/vec-abi-align.ll
index 5075ff2b8c07..48f1adbe5e59 100644
--- a/test/CodeGen/PowerPC/vec-abi-align.ll
+++ b/test/CodeGen/PowerPC/vec-abi-align.ll
@@ -26,52 +26,52 @@ entry:
 ; Function Attrs: nounwind
 define void @test2(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, %struct.s2* byval nocapture readonly %vs) #0 {
 entry:
-  %m = getelementptr inbounds %struct.s2* %vs, i64 0, i32 0
-  %0 = load i64* %m, align 8
+  %m = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 0
+  %0 = load i64, i64* %m, align 8
   store i64 %0, i64* @n, align 8
-  %v = getelementptr inbounds %struct.s2* %vs, i64 0, i32 1
-  %1 = load <4 x float>* %v, align 16
+  %v = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 1
+  %1 = load <4 x float>, <4 x float>* %v, align 16
   store <4 x float> %1, <4 x float>* @ve, align 16
   ret void
 
 ; CHECK-LABEL: @test2
-; CHECK: ld {{[0-9]+}}, 112(1)
-; CHECK: li [[REG16:[0-9]+]], 16
-; CHECK: addi [[REGB:[0-9]+]], 1, 112
-; CHECK: lvx 2, [[REGB]], [[REG16]]
+; CHECK-DAG: ld {{[0-9]+}}, 112(1)
+; CHECK-DAG: li [[REG16:[0-9]+]], 16
+; CHECK-DAG: addi [[REGB:[0-9]+]], 1, 112
+; CHECK-DAG: lvx 2, [[REGB]], [[REG16]]
 ; CHECK: blr
 
 ; CHECK-VSX-LABEL: @test2
-; CHECK-VSX: ld {{[0-9]+}}, 112(1)
-; CHECK-VSX: li [[REG16:[0-9]+]], 16
-; CHECK-VSX: addi [[REGB:[0-9]+]], 1, 112
-; CHECK-VSX: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]]
+; CHECK-VSX-DAG: ld {{[0-9]+}}, 112(1)
+; CHECK-VSX-DAG: li [[REG16:[0-9]+]], 16
+; CHECK-VSX-DAG: addi [[REGB:[0-9]+]], 1, 112
+; CHECK-VSX-DAG: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]]
 ; CHECK-VSX: blr
 }
 
 ; Function Attrs: nounwind
 define void @test3(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, i64 %d9, %struct.s2* byval nocapture readonly %vs) #0 {
 entry:
-  %m = getelementptr inbounds %struct.s2* %vs, i64 0, i32 0
-  %0 = load i64* %m, align 8
+  %m = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 0
+  %0 = load i64, i64* %m, align 8
   store i64 %0, i64* @n, align 8
-  %v = getelementptr inbounds %struct.s2* %vs, i64 0, i32 1
-  %1 = load <4 x float>* %v, align 16
+  %v = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 1
+  %1 = load <4 x float>, <4 x float>* %v, align 16
   store <4 x float> %1, <4 x float>* @ve, align 16
   ret void
 
 ; CHECK-LABEL: @test3
-; CHECK: ld {{[0-9]+}}, 128(1)
-; CHECK: li [[REG16:[0-9]+]], 16
-; CHECK: addi [[REGB:[0-9]+]], 1, 128
-; CHECK: lvx 2, [[REGB]], [[REG16]]
+; CHECK-DAG: ld {{[0-9]+}}, 128(1)
+; CHECK-DAG: li [[REG16:[0-9]+]], 16
+; CHECK-DAG: addi [[REGB:[0-9]+]], 1, 128
+; CHECK-DAG: lvx 2, [[REGB]], [[REG16]]
 ; CHECK: blr
 
 ; CHECK-VSX-LABEL: @test3
-; CHECK-VSX: ld {{[0-9]+}}, 128(1)
-; CHECK-VSX: li [[REG16:[0-9]+]], 16
-; CHECK-VSX: addi [[REGB:[0-9]+]], 1, 128
-; CHECK-VSX: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]]
+; CHECK-VSX-DAG: ld {{[0-9]+}}, 128(1)
+; CHECK-VSX-DAG: li [[REG16:[0-9]+]], 16
+; CHECK-VSX-DAG: addi [[REGB:[0-9]+]], 1, 128
+; CHECK-VSX-DAG: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]]
 ; CHECK-VSX: blr
 }
 
diff --git a/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll b/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
new file mode 100644
index 000000000000..6b41141163ad
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
@@ -0,0 +1,62 @@
+; Check VMX 64-bit integer operations
+;
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
+
+define <2 x i64> @test_add(<2 x i64> %x, <2 x i64> %y) nounwind {
+       %result = add <2 x i64> %x, %y
+       ret <2 x i64> %result
+; CHECK: vaddudm 2, 2, 3
+}
+
+define <2 x i64> @increment_by_one(<2 x i64> %x) nounwind {
+       %result = add <2 x i64> %x, <i64 1, i64 1>
+       ret <2 x i64> %result
+; CHECK: vaddudm 2, 2, 3
+}
+
+define <2 x i64> @increment_by_val(<2 x i64> %x, i64 %val) nounwind {
+       %tmpvec = insertelement <2 x i64> <i64 0, i64 0>, i64 %val, i32 0
+       %tmpvec2 = insertelement <2 x i64> %tmpvec, i64 %val, i32 1
+       %result = add <2 x i64> %x, %tmpvec2
+       ret <2 x i64> %result
+; CHECK: vaddudm 2, 2, 3
+; FIXME: This is currently generating the following instruction sequence
+;
+;        std 5, -8(1)
+;        std 5, -16(1)
+;        addi 3, 1, -16
+;        ori 2, 2, 0
+;        lxvd2x 35, 0, 3
+;        vaddudm 2, 2, 3
+;        blr
+;        
+;        This will almost certainly cause a load-hit-store hazard.
+;        Since val is a value parameter, it should not need to be
+;        saved onto the stack at all (unless we're using this to set
+;        up the vector register). Instead, it would be better to splat
+;        the value into a vector register.
+}
+
+define <2 x i64> @test_sub(<2 x i64> %x, <2 x i64> %y) nounwind {
+       %result = sub <2 x i64> %x, %y
+       ret <2 x i64> %result
+; CHECK: vsubudm 2, 2, 3
+}
+
+define <2 x i64> @decrement_by_one(<2 x i64> %x) nounwind {
+       %result = sub <2 x i64> %x, <i64 -1, i64 -1>
+       ret <2 x i64> %result
+; CHECK: vsubudm 2, 2, 3
+}
+
+define <2 x i64> @decrement_by_val(<2 x i64> %x, i64 %val) nounwind {
+       %tmpvec = insertelement <2 x i64> <i64 0, i64 0>, i64 %val, i32 0
+       %tmpvec2 = insertelement <2 x i64> %tmpvec, i64 %val, i32 1
+       %result = sub <2 x i64> %x, %tmpvec2
+       ret <2 x i64> %result
+; CHECK: vsubudm 2, 2, 3
+}
+
+
+
diff --git a/test/CodeGen/PowerPC/vec_add_sub_quadword.ll b/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
new file mode 100644
index 000000000000..f7ebf479755c
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
@@ -0,0 +1,130 @@
+; Check VMX 128-bit integer operations
+;
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
+
+define <1 x i128> @test_add(<1 x i128> %x, <1 x i128> %y) nounwind {
+       %result = add <1 x i128> %x, %y
+       ret <1 x i128> %result
+; CHECK-LABEL: @test_add
+; CHECK: vadduqm 2, 2, 3
+}
+
+define <1 x i128> @increment_by_one(<1 x i128> %x) nounwind {
+       %result = add <1 x i128> %x, <i128 1>
+       ret <1 x i128> %result
+; CHECK-LABEL: @increment_by_one
+; CHECK vadduqm 2, 2, 3
+}
+
+define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind {
+       %tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 0
+       %tmpvec2 = insertelement <1 x i128> %tmpvec, i128 %val, i32 1
+       %result = add <1 x i128> %x, %tmpvec2
+       ret <1 x i128> %result
+; CHECK-LABEL: @increment_by_val
+; CHECK: vadduqm 2, 2, 3
+}
+
+define <1 x i128> @test_sub(<1 x i128> %x, <1 x i128> %y) nounwind {
+       %result = sub <1 x i128> %x, %y
+       ret <1 x i128> %result
+; CHECK-LABEL: @test_sub
+; CHECK: vsubuqm 2, 2, 3
+}
+
+define <1 x i128> @decrement_by_one(<1 x i128> %x) nounwind {
+       %result = sub <1 x i128> %x, <i128 1>
+       ret <1 x i128> %result
+; CHECK-LABEL: @decrement_by_one
+; CHECK vsubuqm 2, 2, 3
+}
+
+define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind {
+       %tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 0
+       %tmpvec2 = insertelement <1 x i128> %tmpvec, i128 %val, i32 1
+       %result = sub <1 x i128> %x, %tmpvec2
+       ret <1 x i128> %result
+; CHECK-LABEL: @decrement_by_val
+; CHECK vsubuqm   2, 2, 3
+}
+
+declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x, 
+                                              <1 x i128> %y, 
+                                              <1 x i128> %z) nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x, 
+                                             <1 x i128> %y) nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x, 
+                                              <1 x i128> %y, 
+                                              <1 x i128> %z) nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x, 
+                                              <1 x i128> %y, 
+                                              <1 x i128> %z) nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x, 
+                                             <1 x i128> %y) nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x, 
+                                              <1 x i128> %y, 
+                                              <1 x i128> %z) nounwind readnone
+
+define <1 x i128> @test_vaddeuqm(<1 x i128> %x, 
+       	    	                 <1 x i128> %y, 
+                                 <1 x i128> %z) nounwind {
+  %tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x,
+                                                         <1 x i128> %y,
+                                                         <1 x i128> %z)
+  ret <1 x i128> %tmp
+; CHECK-LABEL: @test_vaddeuqm
+; CHECK: vaddeuqm 2, 2, 3, 4
+}
+
+define <1 x i128> @test_vaddcuq(<1 x i128> %x, 
+       	    	                <1 x i128> %y) nounwind {
+  %tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x,
+                                                        <1 x i128> %y)
+  ret <1 x i128> %tmp
+; CHECK-LABEL: @test_vaddcuq
+; CHECK: vaddcuq 2, 2, 3
+}
+
+define <1 x i128> @test_vaddecuq(<1 x i128> %x, 
+       	    	                 <1 x i128> %y, 
+                                 <1 x i128> %z) nounwind {
+  %tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x,
+                                                         <1 x i128> %y,
+                                                         <1 x i128> %z)
+  ret <1 x i128> %tmp
+; CHECK-LABEL: @test_vaddecuq
+; CHECK: vaddecuq 2, 2, 3, 4
+}
+
+define <1 x i128> @test_vsubeuqm(<1 x i128> %x, 
+       	    	                 <1 x i128> %y, 
+                                 <1 x i128> %z) nounwind {
+  %tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x,
+                                                         <1 x i128> %y,
+                                                         <1 x i128> %z)
+  ret <1 x i128> %tmp
+; CHECK-LABEL: test_vsubeuqm
+; CHECK: vsubeuqm 2, 2, 3, 4
+}
+
+define <1 x i128> @test_vsubcuq(<1 x i128> %x, 
+       	    	                <1 x i128> %y) nounwind {
+  %tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x,
+                                                        <1 x i128> %y)
+  ret <1 x i128> %tmp
+; CHECK-LABEL: test_vsubcuq
+; CHECK: vsubcuq 2, 2, 3
+}
+
+define <1 x i128> @test_vsubecuq(<1 x i128> %x, 
+       	    	                 <1 x i128> %y, 
+                                 <1 x i128> %z) nounwind {
+  %tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x,
+                                                         <1 x i128> %y,
+                                                         <1 x i128> %z)
+  ret <1 x i128> %tmp
+; CHECK-LABEL: test_vsubecuq
+; CHECK: vsubecuq 2, 2, 3, 4
+}
+
diff --git a/test/CodeGen/PowerPC/vec_auto_constant.ll b/test/CodeGen/PowerPC/vec_auto_constant.ll
index 973f0890b139..ba8ef531014f 100644
--- a/test/CodeGen/PowerPC/vec_auto_constant.ll
+++ b/test/CodeGen/PowerPC/vec_auto_constant.ll
@@ -25,8 +25,8 @@ entry:
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   store <16 x i8> %x, <16 x i8>* %x_addr
   store <16 x i8> <i8 22, i8 21, i8 20, i8 3, i8 25, i8 24, i8 23, i8 3, i8 28, i8 27, i8 26, i8 3, i8 31, i8 30, i8 29, i8 3>, <16 x i8>* %temp, align 16
-  %0 = load <16 x i8>* %x_addr, align 16          ; <<16 x i8>> [#uses=1]
-  %1 = load <16 x i8>* %temp, align 16            ; <<16 x i8>> [#uses=1]
+  %0 = load <16 x i8>, <16 x i8>* %x_addr, align 16          ; <<16 x i8>> [#uses=1]
+  %1 = load <16 x i8>, <16 x i8>* %temp, align 16            ; <<16 x i8>> [#uses=1]
   %tmp = add <16 x i8> %0, %1                     ; <<16 x i8>> [#uses=1]
   store <16 x i8> %tmp, <16 x i8>* @baz, align 16
   br label %return
diff --git a/test/CodeGen/PowerPC/vec_br_cmp.ll b/test/CodeGen/PowerPC/vec_br_cmp.ll
index c34d850c0ac7..14c9620143a1 100644
--- a/test/CodeGen/PowerPC/vec_br_cmp.ll
+++ b/test/CodeGen/PowerPC/vec_br_cmp.ll
@@ -5,8 +5,8 @@
 ; A predicate compare used immediately by a branch should not generate an mfcr.
 
 define void @test(<4 x float>* %A, <4 x float>* %B) {
-	%tmp = load <4 x float>* %A		; <<4 x float>> [#uses=1]
-	%tmp3 = load <4 x float>* %B		; <<4 x float>> [#uses=1]
+	%tmp = load <4 x float>, <4 x float>* %A		; <<4 x float>> [#uses=1]
+	%tmp3 = load <4 x float>, <4 x float>* %B		; <<4 x float>> [#uses=1]
 	%tmp.upgrd.1 = tail call i32 @llvm.ppc.altivec.vcmpeqfp.p( i32 1, <4 x float> %tmp, <4 x float> %tmp3 )		; <i32> [#uses=1]
 	%tmp.upgrd.2 = icmp eq i32 %tmp.upgrd.1, 0		; <i1> [#uses=1]
 	br i1 %tmp.upgrd.2, label %cond_true, label %UnifiedReturnBlock
diff --git a/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll b/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll
index 7e58ec0bdef4..3b8507728aea 100644
--- a/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll
+++ b/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll
@@ -8,7 +8,7 @@ define void @foo() nounwind ssp {
 ; CHECK: _foo:
 ; CHECK-NOT: stw
 entry:
-    %tmp0 = load <16 x i8>* @a, align 16
+    %tmp0 = load <16 x i8>, <16 x i8>* @a, align 16
   %tmp180.i = extractelement <16 x i8> %tmp0, i32 0 ; <i8> [#uses=1]
   %tmp181.i = insertelement <16 x i8> <i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp180.i, i32 2 ; <<16 x i8>> [#uses=1]
   %tmp182.i = extractelement <16 x i8> %tmp0, i32 1 ; <i8> [#uses=1]
diff --git a/test/CodeGen/PowerPC/vec_clz.ll b/test/CodeGen/PowerPC/vec_clz.ll
new file mode 100644
index 000000000000..01cdecdbb762
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_clz.ll
@@ -0,0 +1,40 @@
+; Check the vctlz* instructions that were added in P8
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
+
+declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>) nounwind readnone
+
+define <16 x i8> @test_v16i8(<16 x i8> %x) nounwind readnone {
+       %vcnt = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x)
+       ret <16 x i8> %vcnt
+; CHECK: @test_v16i8
+; CHECK: vclzb 2, 2
+; CHECK: blr
+}
+
+define <8 x i16> @test_v8i16(<8 x i16> %x) nounwind readnone {
+       %vcnt = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %x)
+       ret <8 x i16> %vcnt
+; CHECK: @test_v8i16
+; CHECK: vclzh 2, 2
+; CHECK: blr
+}
+
+define <4 x i32> @test_v4i32(<4 x i32> %x) nounwind readnone {
+       %vcnt = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %x)
+       ret <4 x i32> %vcnt
+; CHECK: @test_v4i32
+; CHECK: vclzw 2, 2
+; CHECK: blr
+}
+
+define <2 x i64> @test_v2i64(<2 x i64> %x) nounwind readnone {
+       %vcnt = tail call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %x)
+       ret <2 x i64> %vcnt
+; CHECK: @test_v2i64
+; CHECK: vclzd 2, 2
+; CHECK: blr
+}
diff --git a/test/CodeGen/PowerPC/vec_cmpd.ll b/test/CodeGen/PowerPC/vec_cmpd.ll
new file mode 100644
index 000000000000..4a06ed9ffafd
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_cmpd.ll
@@ -0,0 +1,258 @@
+; Test the doubleword comparison instructions that were added in POWER8
+;
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
+
+define <2 x i64> @v2si64_cmp(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
+       %cmp = icmp eq <2 x i64> %x, %y
+       %result = sext <2 x i1> %cmp to <2 x i64>
+       ret <2 x i64> %result
+; CHECK-LABEL: v2si64_cmp:
+; CHECK: vcmpequd 2, 2, 3
+}
+
+define <4 x i64> @v4si64_cmp(<4 x i64> %x, <4 x i64> %y) nounwind readnone {
+       %cmp = icmp eq <4 x i64> %x, %y
+       %result = sext <4 x i1> %cmp to <4 x i64>
+       ret <4 x i64> %result
+; CHECK-LABEL: v4si64_cmp
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define <8 x i64> @v8si64_cmp(<8 x i64> %x, <8 x i64> %y) nounwind readnone {
+       %cmp = icmp eq <8 x i64> %x, %y
+       %result = sext <8 x i1> %cmp to <8 x i64>
+       ret <8 x i64> %result
+; CHECK-LABEL: v8si64_cmp
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define <16 x i64> @v16si64_cmp(<16 x i64> %x, <16 x i64> %y) nounwind readnone {
+       %cmp = icmp eq <16 x i64> %x, %y
+       %result = sext <16 x i1> %cmp to <16 x i64>
+       ret <16 x i64> %result
+; CHECK-LABEL: v16si64_cmp
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define <32 x i64> @v32si64_cmp(<32 x i64> %x, <32 x i64> %y) nounwind readnone {
+       %cmp = icmp eq <32 x i64> %x, %y
+       %result = sext <32 x i1> %cmp to <32 x i64>
+       ret <32 x i64> %result
+; CHECK-LABEL: v32si64_cmp
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+; Greater than signed
+define <2 x i64> @v2si64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
+       %cmp = icmp sgt <2 x i64> %x, %y
+       %result = sext <2 x i1> %cmp to <2 x i64>
+       ret <2 x i64> %result
+; CHECK-LABEL: v2si64_cmp_gt
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define <4 x i64> @v4si64_cmp_gt(<4 x i64> %x, <4 x i64> %y) nounwind readnone {
+       %cmp = icmp sgt <4 x i64> %x, %y
+       %result = sext <4 x i1> %cmp to <4 x i64>
+       ret <4 x i64> %result
+; CHECK-LABEL: v4si64_cmp_gt
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define <8 x i64> @v8si64_cmp_gt(<8 x i64> %x, <8 x i64> %y) nounwind readnone {
+       %cmp = icmp sgt <8 x i64> %x, %y
+       %result = sext <8 x i1> %cmp to <8 x i64>
+       ret <8 x i64> %result
+; CHECK-LABEL: v8si64_cmp_gt
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define <16 x i64> @v16si64_cmp_gt(<16 x i64> %x, <16 x i64> %y) nounwind readnone {
+       %cmp = icmp sgt <16 x i64> %x, %y
+       %result = sext <16 x i1> %cmp to <16 x i64>
+       ret <16 x i64> %result
+; CHECK-LABEL: v16si64_cmp_gt
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define <32 x i64> @v32si64_cmp_gt(<32 x i64> %x, <32 x i64> %y) nounwind readnone {
+       %cmp = icmp sgt <32 x i64> %x, %y
+       %result = sext <32 x i1> %cmp to <32 x i64>
+       ret <32 x i64> %result
+; CHECK-LABEL: v32si64_cmp_gt
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+; Greater than unsigned
+define <2 x i64> @v2ui64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
+       %cmp = icmp ugt <2 x i64> %x, %y
+       %result = sext <2 x i1> %cmp to <2 x i64>
+       ret <2 x i64> %result
+; CHECK-LABEL: v2ui64_cmp_gt
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define <4 x i64> @v4ui64_cmp_gt(<4 x i64> %x, <4 x i64> %y) nounwind readnone {
+       %cmp = icmp ugt <4 x i64> %x, %y
+       %result = sext <4 x i1> %cmp to <4 x i64>
+       ret <4 x i64> %result
+; CHECK-LABEL: v4ui64_cmp_gt
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define <8 x i64> @v8ui64_cmp_gt(<8 x i64> %x, <8 x i64> %y) nounwind readnone {
+       %cmp = icmp ugt <8 x i64> %x, %y
+       %result = sext <8 x i1> %cmp to <8 x i64>
+       ret <8 x i64> %result
+; CHECK-LABEL: v8ui64_cmp_gt
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define <16 x i64> @v16ui64_cmp_gt(<16 x i64> %x, <16 x i64> %y) nounwind readnone {
+       %cmp = icmp ugt <16 x i64> %x, %y
+       %result = sext <16 x i1> %cmp to <16 x i64>
+       ret <16 x i64> %result
+; CHECK-LABEL: v16ui64_cmp_gt
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define <32 x i64> @v32ui64_cmp_gt(<32 x i64> %x, <32 x i64> %y) nounwind readnone {
+       %cmp = icmp ugt <32 x i64> %x, %y
+       %result = sext <32 x i1> %cmp to <32 x i64>
+       ret <32 x i64> %result
+; CHECK-LABEL: v32ui64_cmp_gt
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+; Check the intrinsics also
+declare <2 x i64> @llvm.ppc.altivec.vcmpequd(<2 x i64>, <2 x i64>) nounwind readnone
+declare i32 @llvm.ppc.altivec.vcmpequd.p(i32, <2 x i64>, <2 x i64>) nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.vcmpgtsd(<2 x i64>, <2 x i64>) nounwind readnone
+declare i32 @llvm.ppc.altivec.vcmpgtsd.p(i32, <2 x i64>, <2 x i64>) nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.vcmpgtud(<2 x i64>, <2 x i64>) nounwind readnone
+declare i32 @llvm.ppc.altivec.vcmpgtud.p(i32, <2 x i64>, <2 x i64>) nounwind readnone
+
+define <2 x i64> @test_vcmpequd(<2 x i64> %x, <2 x i64> %y) {
+       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vcmpequd(<2 x i64> %x, <2 x i64> %y)
+       ret <2 x i64> %tmp
+; CHECK-LABEL: test_vcmpequd:
+; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define i32 @test_vcmpequd_p(<2 x i64> %x, <2 x i64> %y) {
+       %tmp = tail call i32 @llvm.ppc.altivec.vcmpequd.p(i32 2, <2 x i64> %x, <2 x i64> %y)
+       ret i32 %tmp
+; CHECK-LABEL: test_vcmpequd_p:
+; CHECK: vcmpequd. {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define <2 x i64> @test_vcmpgtsd(<2 x i64> %x, <2 x i64> %y) {
+       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vcmpgtsd(<2 x i64> %x, <2 x i64> %y)
+       ret <2 x i64> %tmp
+; CHECK-LABEL: test_vcmpgtsd
+; CHECK: vcmpgtsd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define i32 @test_vcmpgtsd_p(<2 x i64> %x, <2 x i64> %y) {
+       %tmp = tail call i32 @llvm.ppc.altivec.vcmpgtsd.p(i32 2, <2 x i64> %x, <2 x i64> %y)
+       ret i32 %tmp
+; CHECK-LABEL: test_vcmpgtsd_p
+; CHECK: vcmpgtsd. {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define <2 x i64> @test_vcmpgtud(<2 x i64> %x, <2 x i64> %y) {
+       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vcmpgtud(<2 x i64> %x, <2 x i64> %y)
+       ret <2 x i64> %tmp
+; CHECK-LABEL: test_vcmpgtud
+; CHECK: vcmpgtud {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+define i32 @test_vcmpgtud_p(<2 x i64> %x, <2 x i64> %y) {
+       %tmp = tail call i32 @llvm.ppc.altivec.vcmpgtud.p(i32 2, <2 x i64> %x, <2 x i64> %y)
+       ret i32 %tmp
+; CHECK-LABEL: test_vcmpgtud_p
+; CHECK: vcmpgtud. {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+
+
+
diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll
index f16b9f511f53..858b85dce543 100644
--- a/test/CodeGen/PowerPC/vec_constants.ll
+++ b/test/CodeGen/PowerPC/vec_constants.ll
@@ -1,16 +1,14 @@
-; RUN: llc -O0 -mcpu=pwr7 < %s | FileCheck %s
-
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
+; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
 define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind {
-	%tmp = load <4 x i32>* %P1		; <<4 x i32>> [#uses=1]
+	%tmp = load <4 x i32>, <4 x i32>* %P1		; <<4 x i32>> [#uses=1]
 	%tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 >		; <<4 x i32>> [#uses=1]
 	store <4 x i32> %tmp4, <4 x i32>* %P1
-	%tmp7 = load <4 x i32>* %P2		; <<4 x i32>> [#uses=1]
+	%tmp7 = load <4 x i32>, <4 x i32>* %P2		; <<4 x i32>> [#uses=1]
 	%tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 >		; <<4 x i32>> [#uses=1]
 	store <4 x i32> %tmp9, <4 x i32>* %P2
-	%tmp.upgrd.1 = load <4 x float>* %P3		; <<4 x float>> [#uses=1]
+	%tmp.upgrd.1 = load <4 x float>, <4 x float>* %P3		; <<4 x float>> [#uses=1]
 	%tmp11 = bitcast <4 x float> %tmp.upgrd.1 to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp12 = and <4 x i32> %tmp11, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 >		; <<4 x i32>> [#uses=1]
 	%tmp13 = bitcast <4 x i32> %tmp12 to <4 x float>		; <<4 x float>> [#uses=1]
diff --git a/test/CodeGen/PowerPC/vec_conv.ll b/test/CodeGen/PowerPC/vec_conv.ll
index a39ae9100355..6e19f5a010d2 100644
--- a/test/CodeGen/PowerPC/vec_conv.ll
+++ b/test/CodeGen/PowerPC/vec_conv.ll
@@ -11,7 +11,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define void @v4f32_to_v4i32(<4 x float> %x, <4 x i32>* nocapture %y) nounwind {
 entry:
-  %0 = load <4 x float>* @cte_float, align 16
+  %0 = load <4 x float>, <4 x float>* @cte_float, align 16
   %mul = fmul <4 x float> %0, %x
   %1 = fptosi <4 x float> %mul to <4 x i32>
   store <4 x i32> %1, <4 x i32>* %y, align 16
@@ -23,7 +23,7 @@ entry:
 
 define void @v4f32_to_v4u32(<4 x float> %x, <4 x i32>* nocapture %y) nounwind {
 entry:
-  %0 = load <4 x float>* @cte_float, align 16
+  %0 = load <4 x float>, <4 x float>* @cte_float, align 16
   %mul = fmul <4 x float> %0, %x
   %1 = fptoui <4 x float> %mul to <4 x i32>
   store <4 x i32> %1, <4 x i32>* %y, align 16
@@ -35,7 +35,7 @@ entry:
 
 define void @v4i32_to_v4f32(<4 x i32> %x, <4 x float>* nocapture %y) nounwind {
 entry:
-  %0 = load <4 x i32>* @cte_int, align 16
+  %0 = load <4 x i32>, <4 x i32>* @cte_int, align 16
   %mul = mul <4 x i32> %0, %x
   %1 = sitofp <4 x i32> %mul to <4 x float>
   store <4 x float> %1, <4 x float>* %y, align 16
@@ -47,7 +47,7 @@ entry:
 
 define void @v4u32_to_v4f32(<4 x i32> %x, <4 x float>* nocapture %y) nounwind {
 entry:
-  %0 = load <4 x i32>* @cte_int, align 16
+  %0 = load <4 x i32>, <4 x i32>* @cte_int, align 16
   %mul = mul <4 x i32> %0, %x
   %1 = uitofp <4 x i32> %mul to <4 x float>
   store <4 x float> %1, <4 x float>* %y, align 16
diff --git a/test/CodeGen/PowerPC/vec_fneg.ll b/test/CodeGen/PowerPC/vec_fneg.ll
index e01e65979f6f..d6f6def64ea2 100644
--- a/test/CodeGen/PowerPC/vec_fneg.ll
+++ b/test/CodeGen/PowerPC/vec_fneg.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vsubfp
 
 define void @t(<4 x float>* %A) {
-	%tmp2 = load <4 x float>* %A
+	%tmp2 = load <4 x float>, <4 x float>* %A
 	%tmp3 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp2
 	store <4 x float> %tmp3, <4 x float>* %A
 	ret void
diff --git a/test/CodeGen/PowerPC/vec_minmax.ll b/test/CodeGen/PowerPC/vec_minmax.ll
new file mode 100644
index 000000000000..e9ba6a01a9b8
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_minmax.ll
@@ -0,0 +1,34 @@
+; Test the vector min/max doubleword instructions added for P8
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
+
+declare <2 x i64> @llvm.ppc.altivec.vmaxsd(<2 x i64>, <2 x i64>) nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.vmaxud(<2 x i64>, <2 x i64>) nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.vminsd(<2 x i64>, <2 x i64>) nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.vminud(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <2 x i64> @test_vmaxsd(<2 x i64> %x, <2 x i64> %y) {
+       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vmaxsd(<2 x i64> %x, <2 x i64> %y)
+       ret <2 x i64> %tmp
+; CHECK: vmaxsd 2, 2, 3
+}
+
+define <2 x i64> @test_vmaxud(<2 x i64> %x, <2 x i64> %y) {
+       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vmaxud(<2 x i64> %x, <2 x i64> %y)
+       ret <2 x i64> %tmp
+; CHECK: vmaxud 2, 2, 3
+}
+
+define <2 x i64> @test_vminsd(<2 x i64> %x, <2 x i64> %y) {
+       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vminsd(<2 x i64> %x, <2 x i64> %y)
+       ret <2 x i64> %tmp
+; CHECK: vminsd 2, 2, 3
+}
+
+define <2 x i64> @test_vminud(<2 x i64> %x, <2 x i64> %y) {
+       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vminud(<2 x i64> %x, <2 x i64> %y)
+       ret <2 x i64> %tmp
+; CHECK: vminud 2, 2, 3
+}
+
+
diff --git a/test/CodeGen/PowerPC/vec_misaligned.ll b/test/CodeGen/PowerPC/vec_misaligned.ll
index 49f11e4e2604..ac639d719911 100644
--- a/test/CodeGen/PowerPC/vec_misaligned.ll
+++ b/test/CodeGen/PowerPC/vec_misaligned.ll
@@ -19,18 +19,18 @@ entry:
 	store i32 %x, i32* %x_addr
 	%ap1 = bitcast i8** %ap to i8*		; <i8*> [#uses=1]
 	call void @llvm.va_start( i8* %ap1 )
-	%tmp = load i8** %ap, align 4		; <i8*> [#uses=1]
+	%tmp = load i8*, i8** %ap, align 4		; <i8*> [#uses=1]
 	store i8* %tmp, i8** %ap.0, align 4
-	%tmp2 = load i8** %ap.0, align 4		; <i8*> [#uses=1]
-	%tmp3 = getelementptr i8* %tmp2, i64 16		; <i8*> [#uses=1]
+	%tmp2 = load i8*, i8** %ap.0, align 4		; <i8*> [#uses=1]
+	%tmp3 = getelementptr i8, i8* %tmp2, i64 16		; <i8*> [#uses=1]
 	store i8* %tmp3, i8** %ap, align 4
-	%tmp4 = load i8** %ap.0, align 4		; <i8*> [#uses=1]
+	%tmp4 = load i8*, i8** %ap.0, align 4		; <i8*> [#uses=1]
 	%tmp45 = bitcast i8* %tmp4 to %struct.S2203*		; <%struct.S2203*> [#uses=1]
-	%tmp6 = getelementptr %struct.S2203* @s, i32 0, i32 0		; <%struct.u16qi*> [#uses=1]
-	%tmp7 = getelementptr %struct.S2203* %tmp45, i32 0, i32 0		; <%struct.u16qi*> [#uses=1]
-	%tmp8 = getelementptr %struct.u16qi* %tmp6, i32 0, i32 0		; <<16 x i8>*> [#uses=1]
-	%tmp9 = getelementptr %struct.u16qi* %tmp7, i32 0, i32 0		; <<16 x i8>*> [#uses=1]
-	%tmp10 = load <16 x i8>* %tmp9, align 4		; <<16 x i8>> [#uses=1]
+	%tmp6 = getelementptr %struct.S2203, %struct.S2203* @s, i32 0, i32 0		; <%struct.u16qi*> [#uses=1]
+	%tmp7 = getelementptr %struct.S2203, %struct.S2203* %tmp45, i32 0, i32 0		; <%struct.u16qi*> [#uses=1]
+	%tmp8 = getelementptr %struct.u16qi, %struct.u16qi* %tmp6, i32 0, i32 0		; <<16 x i8>*> [#uses=1]
+	%tmp9 = getelementptr %struct.u16qi, %struct.u16qi* %tmp7, i32 0, i32 0		; <<16 x i8>*> [#uses=1]
+	%tmp10 = load <16 x i8>, <16 x i8>* %tmp9, align 4		; <<16 x i8>> [#uses=1]
 ; CHECK: lvsl
 ; CHECK: vperm
 ; CHECK-LE: lvsr
diff --git a/test/CodeGen/PowerPC/vec_mul.ll b/test/CodeGen/PowerPC/vec_mul.ll
index 86596d4b0a87..e1c9217ff135 100644
--- a/test/CodeGen/PowerPC/vec_mul.ll
+++ b/test/CodeGen/PowerPC/vec_mul.ll
@@ -1,12 +1,12 @@
-; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec -mattr=-vsx | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec -mattr=-vsx -mattr=-power8-altivec | FileCheck %s
 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-LE
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx -mcpu=pwr8 -mattr=-power8-altivec | FileCheck %s -check-prefix=CHECK-LE
 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-VSX
-; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-LE-VSX
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx -mcpu=pwr8 -mattr=-power8-altivec | FileCheck %s -check-prefix=CHECK-LE-VSX
 
 define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
-	%tmp = load <4 x i32>* %X		; <<4 x i32>> [#uses=1]
-	%tmp2 = load <4 x i32>* %Y		; <<4 x i32>> [#uses=1]
+	%tmp = load <4 x i32>, <4 x i32>* %X		; <<4 x i32>> [#uses=1]
+	%tmp2 = load <4 x i32>, <4 x i32>* %Y		; <<4 x i32>> [#uses=1]
 	%tmp3 = mul <4 x i32> %tmp, %tmp2		; <<4 x i32>> [#uses=1]
 	ret <4 x i32> %tmp3
 }
@@ -24,8 +24,8 @@ define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
 ; CHECK-LE-VSX-NOT: mullw
 
 define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) {
-	%tmp = load <8 x i16>* %X		; <<8 x i16>> [#uses=1]
-	%tmp2 = load <8 x i16>* %Y		; <<8 x i16>> [#uses=1]
+	%tmp = load <8 x i16>, <8 x i16>* %X		; <<8 x i16>> [#uses=1]
+	%tmp2 = load <8 x i16>, <8 x i16>* %Y		; <<8 x i16>> [#uses=1]
 	%tmp3 = mul <8 x i16> %tmp, %tmp2		; <<8 x i16>> [#uses=1]
 	ret <8 x i16> %tmp3
 }
@@ -43,8 +43,8 @@ define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) {
 ; CHECK-LE-VSX-NOT: mullw
 
 define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) {
-	%tmp = load <16 x i8>* %X		; <<16 x i8>> [#uses=1]
-	%tmp2 = load <16 x i8>* %Y		; <<16 x i8>> [#uses=1]
+	%tmp = load <16 x i8>, <16 x i8>* %X		; <<16 x i8>> [#uses=1]
+	%tmp2 = load <16 x i8>, <16 x i8>* %Y		; <<16 x i8>> [#uses=1]
 	%tmp3 = mul <16 x i8> %tmp, %tmp2		; <<16 x i8>> [#uses=1]
 	ret <16 x i8> %tmp3
 }
@@ -68,8 +68,8 @@ define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) {
 ; CHECK-LE-VSX-NOT: mullw
 
 define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) {
-	%tmp = load <4 x float>* %X
-	%tmp2 = load <4 x float>* %Y
+	%tmp = load <4 x float>, <4 x float>* %X
+	%tmp2 = load <4 x float>, <4 x float>* %Y
 	%tmp3 = fmul <4 x float> %tmp, %tmp2
 	ret <4 x float> %tmp3
 }
diff --git a/test/CodeGen/PowerPC/vec_mul_even_odd.ll b/test/CodeGen/PowerPC/vec_mul_even_odd.ll
new file mode 100644
index 000000000000..b24bafd196dd
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_mul_even_odd.ll
@@ -0,0 +1,42 @@
+; Check the vector multiply even/odd word instructions that were added in P8
+;
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
+
+declare <2 x i64> @llvm.ppc.altivec.vmuleuw(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.vmulesw(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.vmulouw(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.vmulosw(<4 x i32>, <4 x i32>) nounwind readnone
+declare <4 x i32> @llvm.ppc.altivec.vmuluwm(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <2 x i64> @test_vmuleuw(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
+       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vmuleuw(<4 x i32> %x, <4 x i32> %y)
+       ret <2 x i64> %tmp
+; CHECK: vmuleuw 2, 2, 3
+}
+
+define <2 x i64> @test_vmulesw(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
+       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vmulesw(<4 x i32> %x, <4 x i32> %y)
+       ret <2 x i64> %tmp
+; CHECK: vmulesw 2, 2, 3
+}
+
+define <2 x i64> @test_vmulouw(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
+       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vmulouw(<4 x i32> %x, <4 x i32> %y)
+       ret <2 x i64> %tmp
+; CHECK: vmulouw 2, 2, 3
+}
+
+define <2 x i64> @test_vmulosw(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
+       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vmulosw(<4 x i32> %x, <4 x i32> %y)
+       ret <2 x i64> %tmp
+; CHECK: vmulosw 2, 2, 3
+}
+
+define <4 x i32> @test_vmuluwm(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
+	%tmp = mul <4 x i32> %x, %y
+	ret <4 x i32> %tmp
+; CHECK-LABEL: test_vmuluwm
+; CHECK: vmuluwm 2, 2, 3
+}
+
diff --git a/test/CodeGen/PowerPC/vec_perf_shuffle.ll b/test/CodeGen/PowerPC/vec_perf_shuffle.ll
index 2c3594d224fe..f8b37fae7c23 100644
--- a/test/CodeGen/PowerPC/vec_perf_shuffle.ll
+++ b/test/CodeGen/PowerPC/vec_perf_shuffle.ll
@@ -1,36 +1,36 @@
 ; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep vperm
 
 define <4 x float> @test_uu72(<4 x float>* %P1, <4 x float>* %P2) {
-	%V1 = load <4 x float>* %P1		; <<4 x float>> [#uses=1]
-	%V2 = load <4 x float>* %P2		; <<4 x float>> [#uses=1]
+	%V1 = load <4 x float>, <4 x float>* %P1		; <<4 x float>> [#uses=1]
+	%V2 = load <4 x float>, <4 x float>* %P2		; <<4 x float>> [#uses=1]
 	%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 undef, i32 undef, i32 7, i32 2 >		; <<4 x float>> [#uses=1]
 	ret <4 x float> %V3
 }
 
 define <4 x float> @test_30u5(<4 x float>* %P1, <4 x float>* %P2) {
-	%V1 = load <4 x float>* %P1		; <<4 x float>> [#uses=1]
-	%V2 = load <4 x float>* %P2		; <<4 x float>> [#uses=1]
+	%V1 = load <4 x float>, <4 x float>* %P1		; <<4 x float>> [#uses=1]
+	%V2 = load <4 x float>, <4 x float>* %P2		; <<4 x float>> [#uses=1]
 	%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 0, i32 undef, i32 5 >		; <<4 x float>> [#uses=1]
 	ret <4 x float> %V3
 }
 
 define <4 x float> @test_3u73(<4 x float>* %P1, <4 x float>* %P2) {
-	%V1 = load <4 x float>* %P1		; <<4 x float>> [#uses=1]
-	%V2 = load <4 x float>* %P2		; <<4 x float>> [#uses=1]
+	%V1 = load <4 x float>, <4 x float>* %P1		; <<4 x float>> [#uses=1]
+	%V2 = load <4 x float>, <4 x float>* %P2		; <<4 x float>> [#uses=1]
 	%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 undef, i32 7, i32 3 >		; <<4 x float>> [#uses=1]
 	ret <4 x float> %V3
 }
 
 define <4 x float> @test_3774(<4 x float>* %P1, <4 x float>* %P2) {
-	%V1 = load <4 x float>* %P1		; <<4 x float>> [#uses=1]
-	%V2 = load <4 x float>* %P2		; <<4 x float>> [#uses=1]
+	%V1 = load <4 x float>, <4 x float>* %P1		; <<4 x float>> [#uses=1]
+	%V2 = load <4 x float>, <4 x float>* %P2		; <<4 x float>> [#uses=1]
 	%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 7, i32 7, i32 4 >		; <<4 x float>> [#uses=1]
 	ret <4 x float> %V3
 }
 
 define <4 x float> @test_4450(<4 x float>* %P1, <4 x float>* %P2) {
-	%V1 = load <4 x float>* %P1		; <<4 x float>> [#uses=1]
-	%V2 = load <4 x float>* %P2		; <<4 x float>> [#uses=1]
+	%V1 = load <4 x float>, <4 x float>* %P1		; <<4 x float>> [#uses=1]
+	%V2 = load <4 x float>, <4 x float>* %P2		; <<4 x float>> [#uses=1]
 	%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 4, i32 4, i32 5, i32 0 >		; <<4 x float>> [#uses=1]
 	ret <4 x float> %V3
 }
diff --git a/test/CodeGen/PowerPC/vec_popcnt.ll b/test/CodeGen/PowerPC/vec_popcnt.ll
new file mode 100644
index 000000000000..0ce9dfac1df6
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_popcnt.ll
@@ -0,0 +1,72 @@
+; Check the vecpopcnt* instructions that were added in P8
+; In addition, check the conversions to/from the v2i64 VMX register that was also added in P8.
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
+
+declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone
+
+define <16 x i8> @test_v16i8_v2i64(<2 x i64> %x) nounwind readnone {
+       %tmp  = bitcast <2 x i64> %x to <16 x i8>;
+       %vcnt = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp)
+       ret <16 x i8> %vcnt
+; CHECK: @test_v16i8_v2i64
+; CHECK: vpopcntb 2, 2
+; CHECK: blr
+}
+
+define <8 x i16> @test_v8i16_v2i64(<2 x i64> %x) nounwind readnone {
+       %tmp = bitcast <2 x i64> %x to <8 x i16>
+       %vcnt = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %tmp)
+       ret <8 x i16> %vcnt
+; CHECK: @test_v8i16_v2i64
+; CHECK: vpopcnth 2, 2
+; CHECK: blr
+}
+
+define <4 x i32> @test_v4i32_v2i64(<2 x i64> %x) nounwind readnone {
+       %tmp = bitcast <2 x i64> %x to <4 x i32>
+       %vcnt = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %tmp)
+       ret <4 x i32> %vcnt
+; CHECK: @test_v4i32_v2i64
+; CHECK: vpopcntw 2, 2
+; CHECK: blr
+}
+
+define <2 x i64> @test_v2i64_v2i64(<2 x i64> %x) nounwind readnone {
+       %vcnt = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %x)
+       ret <2 x i64> %vcnt
+; CHECK: @test_v2i64_v2i64
+; CHECK: vpopcntd 2, 2
+; CHECK: blr
+}
+
+define <2 x i64> @test_v2i64_v4i32(<4 x i32> %x) nounwind readnone {
+       %tmp = bitcast <4 x i32> %x to <2 x i64>
+       %vcnt = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %tmp)
+       ret <2 x i64> %vcnt
+; CHECK: @test_v2i64_v4i32
+; CHECK: vpopcntd 2, 2
+; CHECK: blr
+}
+
+
+define <2 x i64> @test_v2i64_v8i16(<8 x i16> %x) nounwind readnone {
+       %tmp = bitcast <8 x i16> %x to <2 x i64>
+       %vcnt = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %tmp)
+       ret <2 x i64> %vcnt
+; CHECK: @test_v2i64_v8i16
+; CHECK: vpopcntd 2, 2
+; CHECK: blr
+}
+
+define <2 x i64> @test_v2i64_v16i8(<16 x i8> %x) nounwind readnone {
+       %tmp = bitcast <16 x i8> %x to <2 x i64>
+       %vcnt = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %tmp)
+       ret <2 x i64> %vcnt
+; CHECK: @test_v2i64_v16i8
+; CHECK: vpopcntd 2, 2
+; CHECK: blr
+}
diff --git a/test/CodeGen/PowerPC/vec_rotate_shift.ll b/test/CodeGen/PowerPC/vec_rotate_shift.ll
new file mode 100644
index 000000000000..1a2e9578e039
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_rotate_shift.ll
@@ -0,0 +1,36 @@
+; Test the vector rotate and shift doubleword instructions that were added in P8
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
+
+declare <2 x i64> @llvm.ppc.altivec.vrld(<2 x i64>, <2 x i64>) nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.vsld(<2 x i64>, <2 x i64>) nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.vsrd(<2 x i64>, <2 x i64>) nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.vsrad(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <2 x i64> @test_vrld(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
+       %tmp = tail call <2 x i64> @llvm.ppc.altivec.vrld(<2 x i64> %x, <2 x i64> %y)
+       ret <2 x i64> %tmp
+; CHECK: vrld 2, 2, 3
+}
+
+define <2 x i64> @test_vsld(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
+       %tmp = shl <2 x i64> %x, %y
+       ret <2 x i64> %tmp
+; CHECK-LABEL: @test_vsld
+; CHECK: vsld 2, 2, 3
+}
+
+define <2 x i64> @test_vsrd(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
+	%tmp = lshr <2 x i64> %x, %y
+	ret <2 x i64> %tmp
+; CHECK-LABEL: @test_vsrd
+; CHECK: vsrd 2, 2, 3
+}
+
+define <2 x i64> @test_vsrad(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
+	%tmp = ashr <2 x i64> %x, %y
+	ret <2 x i64> %tmp
+; CHECK-LABER: @test_vsrad
+; CHECK: vsrad 2, 2, 3
+}
+       
diff --git a/test/CodeGen/PowerPC/vec_shuffle.ll b/test/CodeGen/PowerPC/vec_shuffle.ll
index 82706321c1c1..a942dd1c41c9 100644
--- a/test/CodeGen/PowerPC/vec_shuffle.ll
+++ b/test/CodeGen/PowerPC/vec_shuffle.ll
@@ -9,8 +9,8 @@
 
 define void @VSLDOI_xy(<8 x i16>* %A, <8 x i16>* %B) {
 entry:
-	%tmp = load <8 x i16>* %A		; <<8 x i16>> [#uses=1]
-	%tmp2 = load <8 x i16>* %B		; <<8 x i16>> [#uses=1]
+	%tmp = load <8 x i16>, <8 x i16>* %A		; <<8 x i16>> [#uses=1]
+	%tmp2 = load <8 x i16>, <8 x i16>* %B		; <<8 x i16>> [#uses=1]
 	%tmp.upgrd.1 = bitcast <8 x i16> %tmp to <16 x i8>		; <<16 x i8>> [#uses=11]
 	%tmp2.upgrd.2 = bitcast <8 x i16> %tmp2 to <16 x i8>		; <<16 x i8>> [#uses=5]
 	%tmp.upgrd.3 = extractelement <16 x i8> %tmp.upgrd.1, i32 5		; <i8> [#uses=1]
@@ -51,8 +51,8 @@ entry:
 }
 
 define void @VSLDOI_xx(<8 x i16>* %A, <8 x i16>* %B) {
-	%tmp = load <8 x i16>* %A		; <<8 x i16>> [#uses=1]
-	%tmp2 = load <8 x i16>* %A		; <<8 x i16>> [#uses=1]
+	%tmp = load <8 x i16>, <8 x i16>* %A		; <<8 x i16>> [#uses=1]
+	%tmp2 = load <8 x i16>, <8 x i16>* %A		; <<8 x i16>> [#uses=1]
 	%tmp.upgrd.5 = bitcast <8 x i16> %tmp to <16 x i8>		; <<16 x i8>> [#uses=11]
 	%tmp2.upgrd.6 = bitcast <8 x i16> %tmp2 to <16 x i8>		; <<16 x i8>> [#uses=5]
 	%tmp.upgrd.7 = extractelement <16 x i8> %tmp.upgrd.5, i32 5		; <i8> [#uses=1]
@@ -94,9 +94,9 @@ define void @VSLDOI_xx(<8 x i16>* %A, <8 x i16>* %B) {
 
 define void @VPERM_promote(<8 x i16>* %A, <8 x i16>* %B) {
 entry:
-	%tmp = load <8 x i16>* %A		; <<8 x i16>> [#uses=1]
+	%tmp = load <8 x i16>, <8 x i16>* %A		; <<8 x i16>> [#uses=1]
 	%tmp.upgrd.9 = bitcast <8 x i16> %tmp to <4 x i32>		; <<4 x i32>> [#uses=1]
-	%tmp2 = load <8 x i16>* %B		; <<8 x i16>> [#uses=1]
+	%tmp2 = load <8 x i16>, <8 x i16>* %B		; <<8 x i16>> [#uses=1]
 	%tmp2.upgrd.10 = bitcast <8 x i16> %tmp2 to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp3 = call <4 x i32> @llvm.ppc.altivec.vperm( <4 x i32> %tmp.upgrd.9, <4 x i32> %tmp2.upgrd.10, <16 x i8> < i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14 > )		; <<4 x i32>> [#uses=1]
 	%tmp3.upgrd.11 = bitcast <4 x i32> %tmp3 to <8 x i16>		; <<8 x i16>> [#uses=1]
@@ -108,8 +108,8 @@ declare <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32>, <4 x i32>, <16 x i8>)
 
 define void @tb_l(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
-	%tmp = load <16 x i8>* %A		; <<16 x i8>> [#uses=8]
-	%tmp2 = load <16 x i8>* %B		; <<16 x i8>> [#uses=8]
+	%tmp = load <16 x i8>, <16 x i8>* %A		; <<16 x i8>> [#uses=8]
+	%tmp2 = load <16 x i8>, <16 x i8>* %B		; <<16 x i8>> [#uses=8]
 	%tmp.upgrd.12 = extractelement <16 x i8> %tmp, i32 8		; <i8> [#uses=1]
 	%tmp3 = extractelement <16 x i8> %tmp2, i32 8		; <i8> [#uses=1]
 	%tmp4 = extractelement <16 x i8> %tmp, i32 9		; <i8> [#uses=1]
@@ -148,8 +148,8 @@ entry:
 
 define void @th_l(<8 x i16>* %A, <8 x i16>* %B) {
 entry:
-	%tmp = load <8 x i16>* %A		; <<8 x i16>> [#uses=4]
-	%tmp2 = load <8 x i16>* %B		; <<8 x i16>> [#uses=4]
+	%tmp = load <8 x i16>, <8 x i16>* %A		; <<8 x i16>> [#uses=4]
+	%tmp2 = load <8 x i16>, <8 x i16>* %B		; <<8 x i16>> [#uses=4]
 	%tmp.upgrd.13 = extractelement <8 x i16> %tmp, i32 4		; <i16> [#uses=1]
 	%tmp3 = extractelement <8 x i16> %tmp2, i32 4		; <i16> [#uses=1]
 	%tmp4 = extractelement <8 x i16> %tmp, i32 5		; <i16> [#uses=1]
@@ -172,8 +172,8 @@ entry:
 
 define void @tw_l(<4 x i32>* %A, <4 x i32>* %B) {
 entry:
-	%tmp = load <4 x i32>* %A		; <<4 x i32>> [#uses=2]
-	%tmp2 = load <4 x i32>* %B		; <<4 x i32>> [#uses=2]
+	%tmp = load <4 x i32>, <4 x i32>* %A		; <<4 x i32>> [#uses=2]
+	%tmp2 = load <4 x i32>, <4 x i32>* %B		; <<4 x i32>> [#uses=2]
 	%tmp.upgrd.14 = extractelement <4 x i32> %tmp, i32 2		; <i32> [#uses=1]
 	%tmp3 = extractelement <4 x i32> %tmp2, i32 2		; <i32> [#uses=1]
 	%tmp4 = extractelement <4 x i32> %tmp, i32 3		; <i32> [#uses=1]
@@ -188,8 +188,8 @@ entry:
 
 define void @tb_h(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
-	%tmp = load <16 x i8>* %A		; <<16 x i8>> [#uses=8]
-	%tmp2 = load <16 x i8>* %B		; <<16 x i8>> [#uses=8]
+	%tmp = load <16 x i8>, <16 x i8>* %A		; <<16 x i8>> [#uses=8]
+	%tmp2 = load <16 x i8>, <16 x i8>* %B		; <<16 x i8>> [#uses=8]
 	%tmp.upgrd.15 = extractelement <16 x i8> %tmp, i32 0		; <i8> [#uses=1]
 	%tmp3 = extractelement <16 x i8> %tmp2, i32 0		; <i8> [#uses=1]
 	%tmp4 = extractelement <16 x i8> %tmp, i32 1		; <i8> [#uses=1]
@@ -228,8 +228,8 @@ entry:
 
 define void @th_h(<8 x i16>* %A, <8 x i16>* %B) {
 entry:
-	%tmp = load <8 x i16>* %A		; <<8 x i16>> [#uses=4]
-	%tmp2 = load <8 x i16>* %B		; <<8 x i16>> [#uses=4]
+	%tmp = load <8 x i16>, <8 x i16>* %A		; <<8 x i16>> [#uses=4]
+	%tmp2 = load <8 x i16>, <8 x i16>* %B		; <<8 x i16>> [#uses=4]
 	%tmp.upgrd.16 = extractelement <8 x i16> %tmp, i32 0		; <i16> [#uses=1]
 	%tmp3 = extractelement <8 x i16> %tmp2, i32 0		; <i16> [#uses=1]
 	%tmp4 = extractelement <8 x i16> %tmp, i32 1		; <i16> [#uses=1]
@@ -252,8 +252,8 @@ entry:
 
 define void @tw_h(<4 x i32>* %A, <4 x i32>* %B) {
 entry:
-	%tmp = load <4 x i32>* %A		; <<4 x i32>> [#uses=2]
-	%tmp2 = load <4 x i32>* %B		; <<4 x i32>> [#uses=2]
+	%tmp = load <4 x i32>, <4 x i32>* %A		; <<4 x i32>> [#uses=2]
+	%tmp2 = load <4 x i32>, <4 x i32>* %B		; <<4 x i32>> [#uses=2]
 	%tmp.upgrd.17 = extractelement <4 x i32> %tmp2, i32 0		; <i32> [#uses=1]
 	%tmp3 = extractelement <4 x i32> %tmp, i32 0		; <i32> [#uses=1]
 	%tmp4 = extractelement <4 x i32> %tmp2, i32 1		; <i32> [#uses=1]
@@ -267,8 +267,8 @@ entry:
 }
 
 define void @tw_h_flop(<4 x i32>* %A, <4 x i32>* %B) {
-	%tmp = load <4 x i32>* %A		; <<4 x i32>> [#uses=2]
-	%tmp2 = load <4 x i32>* %B		; <<4 x i32>> [#uses=2]
+	%tmp = load <4 x i32>, <4 x i32>* %A		; <<4 x i32>> [#uses=2]
+	%tmp2 = load <4 x i32>, <4 x i32>* %B		; <<4 x i32>> [#uses=2]
 	%tmp.upgrd.18 = extractelement <4 x i32> %tmp, i32 0		; <i32> [#uses=1]
 	%tmp3 = extractelement <4 x i32> %tmp2, i32 0		; <i32> [#uses=1]
 	%tmp4 = extractelement <4 x i32> %tmp, i32 1		; <i32> [#uses=1]
@@ -283,7 +283,7 @@ define void @tw_h_flop(<4 x i32>* %A, <4 x i32>* %B) {
 
 define void @VMRG_UNARY_tb_l(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
-	%tmp = load <16 x i8>* %A		; <<16 x i8>> [#uses=16]
+	%tmp = load <16 x i8>, <16 x i8>* %A		; <<16 x i8>> [#uses=16]
 	%tmp.upgrd.19 = extractelement <16 x i8> %tmp, i32 8		; <i8> [#uses=1]
 	%tmp3 = extractelement <16 x i8> %tmp, i32 8		; <i8> [#uses=1]
 	%tmp4 = extractelement <16 x i8> %tmp, i32 9		; <i8> [#uses=1]
@@ -322,7 +322,7 @@ entry:
 
 define void @VMRG_UNARY_th_l(<8 x i16>* %A, <8 x i16>* %B) {
 entry:
-	%tmp = load <8 x i16>* %A		; <<8 x i16>> [#uses=8]
+	%tmp = load <8 x i16>, <8 x i16>* %A		; <<8 x i16>> [#uses=8]
 	%tmp.upgrd.20 = extractelement <8 x i16> %tmp, i32 4		; <i16> [#uses=1]
 	%tmp3 = extractelement <8 x i16> %tmp, i32 4		; <i16> [#uses=1]
 	%tmp4 = extractelement <8 x i16> %tmp, i32 5		; <i16> [#uses=1]
@@ -345,7 +345,7 @@ entry:
 
 define void @VMRG_UNARY_tw_l(<4 x i32>* %A, <4 x i32>* %B) {
 entry:
-	%tmp = load <4 x i32>* %A		; <<4 x i32>> [#uses=4]
+	%tmp = load <4 x i32>, <4 x i32>* %A		; <<4 x i32>> [#uses=4]
 	%tmp.upgrd.21 = extractelement <4 x i32> %tmp, i32 2		; <i32> [#uses=1]
 	%tmp3 = extractelement <4 x i32> %tmp, i32 2		; <i32> [#uses=1]
 	%tmp4 = extractelement <4 x i32> %tmp, i32 3		; <i32> [#uses=1]
@@ -360,7 +360,7 @@ entry:
 
 define void @VMRG_UNARY_tb_h(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
-	%tmp = load <16 x i8>* %A		; <<16 x i8>> [#uses=16]
+	%tmp = load <16 x i8>, <16 x i8>* %A		; <<16 x i8>> [#uses=16]
 	%tmp.upgrd.22 = extractelement <16 x i8> %tmp, i32 0		; <i8> [#uses=1]
 	%tmp3 = extractelement <16 x i8> %tmp, i32 0		; <i8> [#uses=1]
 	%tmp4 = extractelement <16 x i8> %tmp, i32 1		; <i8> [#uses=1]
@@ -399,7 +399,7 @@ entry:
 
 define void @VMRG_UNARY_th_h(<8 x i16>* %A, <8 x i16>* %B) {
 entry:
-	%tmp = load <8 x i16>* %A		; <<8 x i16>> [#uses=8]
+	%tmp = load <8 x i16>, <8 x i16>* %A		; <<8 x i16>> [#uses=8]
 	%tmp.upgrd.23 = extractelement <8 x i16> %tmp, i32 0		; <i16> [#uses=1]
 	%tmp3 = extractelement <8 x i16> %tmp, i32 0		; <i16> [#uses=1]
 	%tmp4 = extractelement <8 x i16> %tmp, i32 1		; <i16> [#uses=1]
@@ -422,7 +422,7 @@ entry:
 
 define void @VMRG_UNARY_tw_h(<4 x i32>* %A, <4 x i32>* %B) {
 entry:
-	%tmp = load <4 x i32>* %A		; <<4 x i32>> [#uses=4]
+	%tmp = load <4 x i32>, <4 x i32>* %A		; <<4 x i32>> [#uses=4]
 	%tmp.upgrd.24 = extractelement <4 x i32> %tmp, i32 0		; <i32> [#uses=1]
 	%tmp3 = extractelement <4 x i32> %tmp, i32 0		; <i32> [#uses=1]
 	%tmp4 = extractelement <4 x i32> %tmp, i32 1		; <i32> [#uses=1]
@@ -437,7 +437,7 @@ entry:
 
 define void @VPCKUHUM_unary(<8 x i16>* %A, <8 x i16>* %B) {
 entry:
-	%tmp = load <8 x i16>* %A		; <<8 x i16>> [#uses=2]
+	%tmp = load <8 x i16>, <8 x i16>* %A		; <<8 x i16>> [#uses=2]
 	%tmp.upgrd.25 = bitcast <8 x i16> %tmp to <16 x i8>		; <<16 x i8>> [#uses=8]
 	%tmp3 = bitcast <8 x i16> %tmp to <16 x i8>		; <<16 x i8>> [#uses=8]
 	%tmp.upgrd.26 = extractelement <16 x i8> %tmp.upgrd.25, i32 1		; <i8> [#uses=1]
@@ -479,7 +479,7 @@ entry:
 
 define void @VPCKUWUM_unary(<4 x i32>* %A, <4 x i32>* %B) {
 entry:
-	%tmp = load <4 x i32>* %A		; <<4 x i32>> [#uses=2]
+	%tmp = load <4 x i32>, <4 x i32>* %A		; <<4 x i32>> [#uses=2]
 	%tmp.upgrd.28 = bitcast <4 x i32> %tmp to <8 x i16>		; <<8 x i16>> [#uses=4]
 	%tmp3 = bitcast <4 x i32> %tmp to <8 x i16>		; <<8 x i16>> [#uses=4]
 	%tmp.upgrd.29 = extractelement <8 x i16> %tmp.upgrd.28, i32 1		; <i16> [#uses=1]
diff --git a/test/CodeGen/PowerPC/vec_shuffle_le.ll b/test/CodeGen/PowerPC/vec_shuffle_le.ll
index c7fc1c60c5ea..46d451ff1573 100644
--- a/test/CodeGen/PowerPC/vec_shuffle_le.ll
+++ b/test/CodeGen/PowerPC/vec_shuffle_le.ll
@@ -3,8 +3,8 @@
 define void @VPKUHUM_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VPKUHUM_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -16,7 +16,7 @@ entry:
 define void @VPKUHUM_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VPKUHUM_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
 ; CHECK: vpkuhum
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -26,8 +26,8 @@ entry:
 define void @VPKUWUM_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VPKUWUM_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 16, i32 17, i32 20, i32 21, i32 24, i32 25, i32 28, i32 29>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -39,7 +39,7 @@ entry:
 define void @VPKUWUM_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VPKUWUM_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13>
 ; CHECK: vpkuwum
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -49,8 +49,8 @@ entry:
 define void @VMRGLB_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VMRGLB_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -62,7 +62,7 @@ entry:
 define void @VMRGLB_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VMRGLB_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>
 ; CHECK: vmrglb
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -72,8 +72,8 @@ entry:
 define void @VMRGHB_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VMRGHB_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -85,7 +85,7 @@ entry:
 define void @VMRGHB_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VMRGHB_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 8, i32 9, i32 9, i32 10, i32 10, i32 11, i32 11, i32 12, i32 12, i32 13, i32 13, i32 14, i32 14, i32 15, i32 15>
 ; CHECK: vmrghb
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -95,8 +95,8 @@ entry:
 define void @VMRGLH_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VMRGLH_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -108,7 +108,7 @@ entry:
 define void @VMRGLH_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VMRGLH_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 4, i32 5, i32 4, i32 5, i32 6, i32 7, i32 6, i32 7>
 ; CHECK: vmrglh
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -118,8 +118,8 @@ entry:
 define void @VMRGHH_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VMRGHH_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -131,7 +131,7 @@ entry:
 define void @VMRGHH_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VMRGHH_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 8, i32 9, i32 10, i32 11, i32 10, i32 11, i32 12, i32 13, i32 12, i32 13, i32 14, i32 15, i32 14, i32 15>
 ; CHECK: vmrghh
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -141,8 +141,8 @@ entry:
 define void @VMRGLW_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VMRGLW_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -154,7 +154,7 @@ entry:
 define void @VMRGLW_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VMRGLW_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
 ; CHECK: vmrglw
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -164,8 +164,8 @@ entry:
 define void @VMRGHW_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VMRGHW_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -177,7 +177,7 @@ entry:
 define void @VMRGHW_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VMRGHW_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
 ; CHECK: vmrghw
         store <16 x i8> %tmp2, <16 x i8>* %A
@@ -187,8 +187,8 @@ entry:
 define void @VSLDOI_xy(<16 x i8>* %A, <16 x i8>* %B) {
 entry:
 ; CHECK: VSLDOI_xy:
-        %tmp = load <16 x i8>* %A
-        %tmp2 = load <16 x i8>* %B
+        %tmp = load <16 x i8>, <16 x i8>* %A
+        %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
 ; CHECK: lvx [[REG1:[0-9]+]]
 ; CHECK: lvx [[REG2:[0-9]+]]
@@ -200,7 +200,7 @@ entry:
 define void @VSLDOI_xx(<16 x i8>* %A) {
 entry:
 ; CHECK: VSLDOI_xx:
-        %tmp = load <16 x i8>* %A
+        %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
 ; CHECK: vsldoi
         store <16 x i8> %tmp2, <16 x i8>* %A
diff --git a/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll b/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll
new file mode 100644
index 000000000000..77802348d8e3
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll
@@ -0,0 +1,54 @@
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -mattr=+power8-vector < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck -check-prefix=CHECK-PWR7 %s
+
+define void @VPKUDUM_unary(<2 x i64>* %A) {
+entry:
+        %tmp = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
+        %tmp3 = extractelement <4 x i32> %tmp2, i32 1
+        %tmp4 = extractelement <4 x i32> %tmp2, i32 3
+        %tmp5 = insertelement <4 x i32> undef, i32 %tmp3, i32 0
+        %tmp6 = insertelement <4 x i32> %tmp5, i32 %tmp4, i32 1
+        %tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 2
+        %tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 3
+        %tmp9 = bitcast <4 x i32> %tmp8 to <2 x i64>
+        store <2 x i64> %tmp9, <2 x i64>* %A
+        ret void
+}
+
+; CHECK-LABEL: @VPKUDUM_unary
+; CHECK-NOT:   vperm
+; CHECK-NOT:   vmrglw
+; CHECK-NOT:   vmrghw
+; CHECK:       vpkudum
+; CHECK-PWR7:  vmrglw
+; CHECK-PWR7:  vmrghw
+; CHECK-PWR7:  vmrglw
+
+define void @VPKUDUM(<2 x i64>* %A, <2 x i64>* %B) {
+entry:
+        %tmp = load <2 x i64>, <2 x i64>* %A
+        %tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
+        %tmp3 = load <2 x i64>, <2 x i64>* %B
+        %tmp4 = bitcast <2 x i64> %tmp3 to <4 x i32>
+        %tmp5 = extractelement <4 x i32> %tmp2, i32 1
+        %tmp6 = extractelement <4 x i32> %tmp2, i32 3
+        %tmp7 = extractelement <4 x i32> %tmp4, i32 1
+        %tmp8 = extractelement <4 x i32> %tmp4, i32 3
+        %tmp9 = insertelement <4 x i32> undef, i32 %tmp5, i32 0
+        %tmp10 = insertelement <4 x i32> %tmp9, i32 %tmp6, i32 1
+        %tmp11 = insertelement <4 x i32> %tmp10, i32 %tmp7, i32 2
+        %tmp12 = insertelement <4 x i32> %tmp11, i32 %tmp8, i32 3
+        %tmp13 = bitcast <4 x i32> %tmp12 to <2 x i64>
+        store <2 x i64> %tmp13, <2 x i64>* %A
+        ret void
+}
+
+; CHECK-LABEL: @VPKUDUM
+; CHECK-NOT:   vperm
+; CHECK-NOT:   vmrglw
+; CHECK-NOT:   vmrghw
+; CHECK:       vpkudum
+; CHECK-PWR7:  vmrglw
+; CHECK-PWR7:  vmrghw
+; CHECK-PWR7:  vmrglw
diff --git a/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll b/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll
new file mode 100644
index 000000000000..709388675f64
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll
@@ -0,0 +1,43 @@
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+power8-vector < %s | FileCheck %s
+
+define void @VPKUDUM_unary(<2 x i64>* %A) {
+entry:
+	%tmp = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
+	%tmp3 = extractelement <4 x i32> %tmp2, i32 0
+	%tmp4 = extractelement <4 x i32> %tmp2, i32 2
+	%tmp5 = insertelement <4 x i32> undef, i32 %tmp3, i32 0
+	%tmp6 = insertelement <4 x i32> %tmp5, i32 %tmp4, i32 1
+	%tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 2
+	%tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 3
+	%tmp9 = bitcast <4 x i32> %tmp8 to <2 x i64>
+	store <2 x i64> %tmp9, <2 x i64>* %A
+	ret void
+}
+
+; CHECK-LABEL: @VPKUDUM_unary
+; CHECK-NOT:   vperm
+; CHECK:       vpkudum
+
+define void @VPKUDUM(<2 x i64>* %A, <2 x i64>* %B) {
+entry:
+	%tmp = load <2 x i64>, <2 x i64>* %A
+	%tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
+        %tmp3 = load <2 x i64>, <2 x i64>* %B
+        %tmp4 = bitcast <2 x i64> %tmp3 to <4 x i32>
+	%tmp5 = extractelement <4 x i32> %tmp2, i32 0
+	%tmp6 = extractelement <4 x i32> %tmp2, i32 2
+	%tmp7 = extractelement <4 x i32> %tmp4, i32 0
+	%tmp8 = extractelement <4 x i32> %tmp4, i32 2
+	%tmp9 = insertelement <4 x i32> undef, i32 %tmp5, i32 0
+	%tmp10 = insertelement <4 x i32> %tmp9, i32 %tmp6, i32 1
+	%tmp11 = insertelement <4 x i32> %tmp10, i32 %tmp7, i32 2
+	%tmp12 = insertelement <4 x i32> %tmp11, i32 %tmp8, i32 3
+	%tmp13 = bitcast <4 x i32> %tmp12 to <2 x i64>
+	store <2 x i64> %tmp13, <2 x i64>* %A
+	ret void
+}
+
+; CHECK-LABEL: @VPKUDUM
+; CHECK-NOT:   vperm
+; CHECK:       vpkudum
diff --git a/test/CodeGen/PowerPC/vec_splat.ll b/test/CodeGen/PowerPC/vec_splat.ll
index 61237284d36c..aeed94c91f40 100644
--- a/test/CodeGen/PowerPC/vec_splat.ll
+++ b/test/CodeGen/PowerPC/vec_splat.ll
@@ -14,7 +14,7 @@ define void @splat(%f4* %P, %f4* %Q, float %X) nounwind {
         %tmp2 = insertelement %f4 %tmp, float %X, i32 1         ; <%f4> [#uses=1]
         %tmp4 = insertelement %f4 %tmp2, float %X, i32 2                ; <%f4> [#uses=1]
         %tmp6 = insertelement %f4 %tmp4, float %X, i32 3                ; <%f4> [#uses=1]
-        %q = load %f4* %Q               ; <%f4> [#uses=1]
+        %q = load %f4, %f4* %Q               ; <%f4> [#uses=1]
         %R = fadd %f4 %q, %tmp6          ; <%f4> [#uses=1]
         store %f4 %R, %f4* %P
         ret void
@@ -25,21 +25,21 @@ define void @splat_i4(%i4* %P, %i4* %Q, i32 %X) nounwind {
         %tmp2 = insertelement %i4 %tmp, i32 %X, i32 1           ; <%i4> [#uses=1]
         %tmp4 = insertelement %i4 %tmp2, i32 %X, i32 2          ; <%i4> [#uses=1]
         %tmp6 = insertelement %i4 %tmp4, i32 %X, i32 3          ; <%i4> [#uses=1]
-        %q = load %i4* %Q               ; <%i4> [#uses=1]
+        %q = load %i4, %i4* %Q               ; <%i4> [#uses=1]
         %R = add %i4 %q, %tmp6          ; <%i4> [#uses=1]
         store %i4 %R, %i4* %P
         ret void
 }
 
 define void @splat_imm_i32(%i4* %P, %i4* %Q, i32 %X) nounwind {
-        %q = load %i4* %Q               ; <%i4> [#uses=1]
+        %q = load %i4, %i4* %Q               ; <%i4> [#uses=1]
         %R = add %i4 %q, < i32 -1, i32 -1, i32 -1, i32 -1 >             ; <%i4> [#uses=1]
         store %i4 %R, %i4* %P
         ret void
 }
 
 define void @splat_imm_i16(%i4* %P, %i4* %Q, i32 %X) nounwind {
-        %q = load %i4* %Q               ; <%i4> [#uses=1]
+        %q = load %i4, %i4* %Q               ; <%i4> [#uses=1]
         %R = add %i4 %q, < i32 65537, i32 65537, i32 65537, i32 65537 >         ; <%i4> [#uses=1]
         store %i4 %R, %i4* %P
         ret void
@@ -60,7 +60,7 @@ define void @splat_h(i16 %tmp, <16 x i8>* %dst) nounwind {
 }
 
 define void @spltish(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-        %tmp = load <16 x i8>* %B               ; <<16 x i8>> [#uses=1]
+        %tmp = load <16 x i8>, <16 x i8>* %B               ; <<16 x i8>> [#uses=1]
         %tmp.s = bitcast <16 x i8> %tmp to <16 x i8>            ; <<16 x i8>> [#uses=1]
         %tmp4 = sub <16 x i8> %tmp.s, bitcast (<8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16
  15, i16 15, i16 15 > to <16 x i8>)             ; <<16 x i8>> [#uses=1]
diff --git a/test/CodeGen/PowerPC/vec_splat_constant.ll b/test/CodeGen/PowerPC/vec_splat_constant.ll
index b227794421f2..53676fcbba4a 100644
--- a/test/CodeGen/PowerPC/vec_splat_constant.ll
+++ b/test/CodeGen/PowerPC/vec_splat_constant.ll
@@ -12,8 +12,8 @@ entry:
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   store <16 x i8> %x, <16 x i8>* %x_addr
   store <16 x i8> <i8 0, i8 0, i8 0, i8 14, i8 0, i8 0, i8 0, i8 14, i8 0, i8 0, i8 0, i8 14, i8 0, i8 0, i8 0, i8 14>, <16 x i8>* %temp, align 16
-  %0 = load <16 x i8>* %x_addr, align 16          ; <<16 x i8>> [#uses=1]
-  %1 = load <16 x i8>* %temp, align 16            ; <<16 x i8>> [#uses=1]
+  %0 = load <16 x i8>, <16 x i8>* %x_addr, align 16          ; <<16 x i8>> [#uses=1]
+  %1 = load <16 x i8>, <16 x i8>* %temp, align 16            ; <<16 x i8>> [#uses=1]
   %tmp = add <16 x i8> %0, %1                     ; <<16 x i8>> [#uses=1]
   store <16 x i8> %tmp, <16 x i8>* @baz, align 16
   br label %return
diff --git a/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll b/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll
new file mode 100644
index 000000000000..f7d5a51c11d4
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll
@@ -0,0 +1,29 @@
+; Check the miscellaneous logical vector operations added in P8
+; 
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
+; Test x eqv y
+define <4 x i32> @test_veqv(<4 x i32> %x, <4 x i32> %y) nounwind {
+       %tmp = xor <4 x i32> %x, %y
+       %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1>
+       ret <4 x i32> %ret_val
+; CHECK: veqv 2, 2, 3
+}
+
+; Test x vnand y
+define <4 x i32> @test_vnand(<4 x i32> %x, <4 x i32> %y) nounwind {
+       %tmp = and <4 x i32> %x, %y
+       %ret_val = xor <4 x i32> %tmp, <i32 -1, i32 -1, i32 -1, i32 -1>
+       ret <4 x i32> %ret_val
+; CHECK: vnand 2, 2, 3
+}
+
+; Test x vorc y and variants
+define <4 x i32> @test_vorc(<4 x i32> %x, <4 x i32> %y) nounwind {
+       %tmp1 = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
+       %tmp2 = or <4 x i32> %x, %tmp1
+; CHECK: vorc 3, 2, 3      
+       %tmp3 = xor <4 x i32> %tmp2, <i32 -1, i32 -1, i32 -1, i32 -1>
+       %tmp4 = or <4 x i32> %tmp3, %x
+; CHECK: vorc 2, 2, 3
+       ret <4 x i32> %tmp4
+}
diff --git a/test/CodeGen/PowerPC/vec_zero.ll b/test/CodeGen/PowerPC/vec_zero.ll
index f862b2cb4c4b..aec61fbd6bd6 100644
--- a/test/CodeGen/PowerPC/vec_zero.ll
+++ b/test/CodeGen/PowerPC/vec_zero.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vxor
 
 define void @foo(<4 x float>* %P) {
-        %T = load <4 x float>* %P               ; <<4 x float>> [#uses=1]
+        %T = load <4 x float>, <4 x float>* %P               ; <<4 x float>> [#uses=1]
         %S = fadd <4 x float> zeroinitializer, %T                ; <<4 x float>> [#uses=1]
         store <4 x float> %S, <4 x float>* %P
         ret void
diff --git a/test/CodeGen/PowerPC/vector-identity-shuffle.ll b/test/CodeGen/PowerPC/vector-identity-shuffle.ll
index dfa2e35435a8..35979f68a886 100644
--- a/test/CodeGen/PowerPC/vector-identity-shuffle.ll
+++ b/test/CodeGen/PowerPC/vector-identity-shuffle.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep vperm
 
 define void @test(<4 x float>* %tmp2.i) {
-        %tmp2.i.upgrd.1 = load <4 x float>* %tmp2.i             ; <<4 x float>> [#uses=4]
+        %tmp2.i.upgrd.1 = load <4 x float>, <4 x float>* %tmp2.i             ; <<4 x float>> [#uses=4]
         %xFloat0.48 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 0      ; <float> [#uses=1]
         %inFloat0.49 = insertelement <4 x float> undef, float %xFloat0.48, i32 0              ; <<4 x float>> [#uses=1]
         %xFloat1.50 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 1      ; <float> [#uses=1]
diff --git a/test/CodeGen/PowerPC/vector.ll b/test/CodeGen/PowerPC/vector.ll
index 859a85a14101..723ca54c02ba 100644
--- a/test/CodeGen/PowerPC/vector.ll
+++ b/test/CodeGen/PowerPC/vector.ll
@@ -12,56 +12,56 @@
 ;;; TEST HANDLING OF VARIOUS VECTOR SIZES
 
 define void @test_f1(%f1* %P, %f1* %Q, %f1* %S) {
-        %p = load %f1* %P               ; <%f1> [#uses=1]
-        %q = load %f1* %Q               ; <%f1> [#uses=1]
+        %p = load %f1, %f1* %P               ; <%f1> [#uses=1]
+        %q = load %f1, %f1* %Q               ; <%f1> [#uses=1]
         %R = fadd %f1 %p, %q             ; <%f1> [#uses=1]
         store %f1 %R, %f1* %S
         ret void
 }
 
 define void @test_f2(%f2* %P, %f2* %Q, %f2* %S) {
-        %p = load %f2* %P               ; <%f2> [#uses=1]
-        %q = load %f2* %Q               ; <%f2> [#uses=1]
+        %p = load %f2, %f2* %P               ; <%f2> [#uses=1]
+        %q = load %f2, %f2* %Q               ; <%f2> [#uses=1]
         %R = fadd %f2 %p, %q             ; <%f2> [#uses=1]
         store %f2 %R, %f2* %S
         ret void
 }
 
 define void @test_f4(%f4* %P, %f4* %Q, %f4* %S) {
-        %p = load %f4* %P               ; <%f4> [#uses=1]
-        %q = load %f4* %Q               ; <%f4> [#uses=1]
+        %p = load %f4, %f4* %P               ; <%f4> [#uses=1]
+        %q = load %f4, %f4* %Q               ; <%f4> [#uses=1]
         %R = fadd %f4 %p, %q             ; <%f4> [#uses=1]
         store %f4 %R, %f4* %S
         ret void
 }
 
 define void @test_f8(%f8* %P, %f8* %Q, %f8* %S) {
-        %p = load %f8* %P               ; <%f8> [#uses=1]
-        %q = load %f8* %Q               ; <%f8> [#uses=1]
+        %p = load %f8, %f8* %P               ; <%f8> [#uses=1]
+        %q = load %f8, %f8* %Q               ; <%f8> [#uses=1]
         %R = fadd %f8 %p, %q             ; <%f8> [#uses=1]
         store %f8 %R, %f8* %S
         ret void
 }
 
 define void @test_fmul(%f8* %P, %f8* %Q, %f8* %S) {
-        %p = load %f8* %P               ; <%f8> [#uses=1]
-        %q = load %f8* %Q               ; <%f8> [#uses=1]
+        %p = load %f8, %f8* %P               ; <%f8> [#uses=1]
+        %q = load %f8, %f8* %Q               ; <%f8> [#uses=1]
         %R = fmul %f8 %p, %q             ; <%f8> [#uses=1]
         store %f8 %R, %f8* %S
         ret void
 }
 
 define void @test_div(%f8* %P, %f8* %Q, %f8* %S) {
-        %p = load %f8* %P               ; <%f8> [#uses=1]
-        %q = load %f8* %Q               ; <%f8> [#uses=1]
+        %p = load %f8, %f8* %P               ; <%f8> [#uses=1]
+        %q = load %f8, %f8* %Q               ; <%f8> [#uses=1]
         %R = fdiv %f8 %p, %q            ; <%f8> [#uses=1]
         store %f8 %R, %f8* %S
         ret void
 }
 
 define void @test_rem(%f8* %P, %f8* %Q, %f8* %S) {
-        %p = load %f8* %P               ; <%f8> [#uses=1]
-        %q = load %f8* %Q               ; <%f8> [#uses=1]
+        %p = load %f8, %f8* %P               ; <%f8> [#uses=1]
+        %q = load %f8, %f8* %Q               ; <%f8> [#uses=1]
         %R = frem %f8 %p, %q            ; <%f8> [#uses=1]
         store %f8 %R, %f8* %S
         ret void
@@ -70,7 +70,7 @@ define void @test_rem(%f8* %P, %f8* %Q, %f8* %S) {
 ;;; TEST VECTOR CONSTRUCTS
 
 define void @test_cst(%f4* %P, %f4* %S) {
-        %p = load %f4* %P               ; <%f4> [#uses=1]
+        %p = load %f4, %f4* %P               ; <%f4> [#uses=1]
         %R = fadd %f4 %p, < float 0x3FB99999A0000000, float 1.000000e+00, float
  2.000000e+00, float 4.500000e+00 >             ; <%f4> [#uses=1]
         store %f4 %R, %f4* %S
@@ -78,14 +78,14 @@ define void @test_cst(%f4* %P, %f4* %S) {
 }
 
 define void @test_zero(%f4* %P, %f4* %S) {
-        %p = load %f4* %P               ; <%f4> [#uses=1]
+        %p = load %f4, %f4* %P               ; <%f4> [#uses=1]
         %R = fadd %f4 %p, zeroinitializer                ; <%f4> [#uses=1]
         store %f4 %R, %f4* %S
         ret void
 }
 
 define void @test_undef(%f4* %P, %f4* %S) {
-        %p = load %f4* %P               ; <%f4> [#uses=1]
+        %p = load %f4, %f4* %P               ; <%f4> [#uses=1]
         %R = fadd %f4 %p, undef          ; <%f4> [#uses=1]
         store %f4 %R, %f4* %S
         ret void
@@ -111,19 +111,19 @@ define void @test_scalar_to_vector(float %F, %f4* %S) {
 }
 
 define float @test_extract_elt(%f8* %P) {
-        %p = load %f8* %P               ; <%f8> [#uses=1]
+        %p = load %f8, %f8* %P               ; <%f8> [#uses=1]
         %R = extractelement %f8 %p, i32 3               ; <float> [#uses=1]
         ret float %R
 }
 
 define double @test_extract_elt2(%d8* %P) {
-        %p = load %d8* %P               ; <%d8> [#uses=1]
+        %p = load %d8, %d8* %P               ; <%d8> [#uses=1]
         %R = extractelement %d8 %p, i32 3               ; <double> [#uses=1]
         ret double %R
 }
 
 define void @test_cast_1(%f4* %b, %i4* %a) {
-        %tmp = load %f4* %b             ; <%f4> [#uses=1]
+        %tmp = load %f4, %f4* %b             ; <%f4> [#uses=1]
         %tmp2 = fadd %f4 %tmp, < float 1.000000e+00, float 2.000000e+00, float
 3.000000e+00, float 4.000000e+00 >              ; <%f4> [#uses=1]
         %tmp3 = bitcast %f4 %tmp2 to %i4                ; <%i4> [#uses=1]
@@ -133,7 +133,7 @@ define void @test_cast_1(%f4* %b, %i4* %a) {
 }
 
 define void @test_cast_2(%f8* %a, <8 x i32>* %b) {
-        %T = load %f8* %a               ; <%f8> [#uses=1]
+        %T = load %f8, %f8* %a               ; <%f8> [#uses=1]
         %T2 = bitcast %f8 %T to <8 x i32>               
         store <8 x i32> %T2, <8 x i32>* %b
         ret void
@@ -147,7 +147,7 @@ define void @splat(%f4* %P, %f4* %Q, float %X) {
         %tmp2 = insertelement %f4 %tmp, float %X, i32 1       
         %tmp4 = insertelement %f4 %tmp2, float %X, i32 2    
         %tmp6 = insertelement %f4 %tmp4, float %X, i32 3   
-        %q = load %f4* %Q               ; <%f4> [#uses=1]
+        %q = load %f4, %f4* %Q               ; <%f4> [#uses=1]
         %R = fadd %f4 %q, %tmp6          ; <%f4> [#uses=1]
         store %f4 %R, %f4* %P
         ret void
@@ -158,7 +158,7 @@ define void @splat_i4(%i4* %P, %i4* %Q, i32 %X) {
         %tmp2 = insertelement %i4 %tmp, i32 %X, i32 1         
         %tmp4 = insertelement %i4 %tmp2, i32 %X, i32 2       
         %tmp6 = insertelement %i4 %tmp4, i32 %X, i32 3     
-        %q = load %i4* %Q               ; <%i4> [#uses=1]
+        %q = load %i4, %i4* %Q               ; <%i4> [#uses=1]
         %R = add %i4 %q, %tmp6          ; <%i4> [#uses=1]
         store %i4 %R, %i4* %P
         ret void
diff --git a/test/CodeGen/PowerPC/vperm-lowering.ll b/test/CodeGen/PowerPC/vperm-lowering.ll
index d55d26c959b6..c78ffdd0c073 100644
--- a/test/CodeGen/PowerPC/vperm-lowering.ll
+++ b/test/CodeGen/PowerPC/vperm-lowering.ll
@@ -9,58 +9,23 @@ define <16 x i8> @foo() nounwind ssp {
 }
 
 ; CHECK: .LCPI0_0:
-; CHECK: .byte 31
-; CHECK: .byte 26
-; CHECK: .byte 21
-; CHECK: .byte 16
-; CHECK: .byte 11
-; CHECK: .byte 6
-; CHECK: .byte 1
-; CHECK: .byte 28
-; CHECK: .byte 23
-; CHECK: .byte 18
-; CHECK: .byte 13
-; CHECK: .byte 8
-; CHECK: .byte 3
-; CHECK: .byte 30
-; CHECK: .byte 25
-; CHECK: .byte 20
-; CHECK: .LCPI0_1:
 ; CHECK: .byte 0
-; CHECK: .byte 1
-; CHECK: .byte 2
-; CHECK: .byte 3
-; CHECK: .byte 4
 ; CHECK: .byte 5
-; CHECK: .byte 6
-; CHECK: .byte 7
-; CHECK: .byte 8
-; CHECK: .byte 9
 ; CHECK: .byte 10
-; CHECK: .byte 11
-; CHECK: .byte 12
-; CHECK: .byte 13
-; CHECK: .byte 14
 ; CHECK: .byte 15
-; CHECK: .LCPI0_2:
-; CHECK: .byte 16
-; CHECK: .byte 17
-; CHECK: .byte 18
-; CHECK: .byte 19
 ; CHECK: .byte 20
-; CHECK: .byte 21
-; CHECK: .byte 22
-; CHECK: .byte 23
-; CHECK: .byte 24
 ; CHECK: .byte 25
-; CHECK: .byte 26
-; CHECK: .byte 27
-; CHECK: .byte 28
-; CHECK: .byte 29
 ; CHECK: .byte 30
-; CHECK: .byte 31
+; CHECK: .byte 3
+; CHECK: .byte 8
+; CHECK: .byte 13
+; CHECK: .byte 18
+; CHECK: .byte 23
+; CHECK: .byte 28
+; CHECK: .byte 1
+; CHECK: .byte 6
+; CHECK: .byte 11
 ; CHECK: foo:
-; CHECK: addis [[REG1:[0-9]+]], 2, .LCPI0_2@toc@ha
-; CHECK: addi [[REG2:[0-9]+]], [[REG1]], .LCPI0_2@toc@l
+; CHECK: addis [[REG1:[0-9]+]], 2, .LCPI0_0@toc@ha
+; CHECK: addi [[REG2:[0-9]+]], [[REG1]], .LCPI0_0@toc@l
 ; CHECK: lvx [[REG3:[0-9]+]], 0, [[REG2]]
-; CHECK: vperm {{[0-9]+}}, [[REG3]], {{[0-9]+}}, {{[0-9]+}}
diff --git a/test/CodeGen/PowerPC/vsx-div.ll b/test/CodeGen/PowerPC/vsx-div.ll
index 8a9578e5ed80..0e8388543a2f 100644
--- a/test/CodeGen/PowerPC/vsx-div.ll
+++ b/test/CodeGen/PowerPC/vsx-div.ll
@@ -7,7 +7,7 @@
 
 define void @test1() {
 entry:
-  %0 = load <4 x float>* @vf, align 16
+  %0 = load <4 x float>, <4 x float>* @vf, align 16
   %1 = tail call <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float> %0, <4 x float> %0)
   store <4 x float> %1, <4 x float>* @vf_res, align 16
   ret void
@@ -17,7 +17,7 @@ entry:
 
 define void @test2() {
 entry:
-  %0 = load <2 x double>* @vd, align 16
+  %0 = load <2 x double>, <2 x double>* @vd, align 16
   %1 = tail call <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double> %0, <2 x double> %0)
   store <2 x double> %1, <2 x double>* @vd_res, align 16
   ret void
diff --git a/test/CodeGen/PowerPC/vsx-elementary-arith.ll b/test/CodeGen/PowerPC/vsx-elementary-arith.ll
new file mode 100644
index 000000000000..d8f76bb989e7
--- /dev/null
+++ b/test/CodeGen/PowerPC/vsx-elementary-arith.ll
@@ -0,0 +1,120 @@
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
+@a = global float 3.000000e+00, align 4
+@b = global float 4.000000e+00, align 4
+@c = global double 3.000000e+00, align 8
+@d = global double 4.000000e+00, align 8
+
+; Function Attrs: nounwind
+define float @emit_xsaddsp() {
+entry:
+  %0 = load float, float* @a, align 4
+  %1 = load float, float* @b, align 4
+  %add = fadd float %0, %1
+  ret float %add
+; CHECK-LABEL: @emit_xsaddsp
+; CHECK: xsaddsp {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define float @emit_xssubsp() {
+entry:
+  %0 = load float, float* @a, align 4
+  %1 = load float, float* @b, align 4
+  %sub = fsub float %0, %1
+  ret float %sub
+; CHECK-LABEL: @emit_xssubsp
+; CHECK: xssubsp {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define float @emit_xsdivsp() {
+entry:
+  %0 = load float, float* @a, align 4
+  %1 = load float, float* @b, align 4
+  %div = fdiv float %0, %1
+  ret float %div
+; CHECK-LABEL: @emit_xsdivsp
+; CHECK: xsdivsp {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define float @emit_xsmulsp() {
+entry:
+  %0 = load float, float* @a, align 4
+  %1 = load float, float* @b, align 4
+  %mul = fmul float %0, %1
+  ret float %mul
+; CHECK-LABEL: @emit_xsmulsp
+; CHECK: xsmulsp {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define float @emit_xssqrtsp() {
+entry:
+  %0 = load float, float* @b, align 4
+  %call = call float @sqrtf(float %0)
+  ret float %call
+; CHECK-LABEL: @emit_xssqrtsp
+; CHECK: xssqrtsp {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+declare float @sqrtf(float)
+
+; Function Attrs: nounwind
+define double @emit_xsadddp() {
+entry:
+  %0 = load double, double* @c, align 8
+  %1 = load double, double* @d, align 8
+  %add = fadd double %0, %1
+  ret double %add
+; CHECK-LABEL: @emit_xsadddp
+; CHECK: xsadddp {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define double @emit_xssubdp() {
+entry:
+  %0 = load double, double* @c, align 8
+  %1 = load double, double* @d, align 8
+  %sub = fsub double %0, %1
+  ret double %sub
+; CHECK-LABEL: @emit_xssubdp
+; CHECK: xssubdp {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define double @emit_xsdivdp() {
+entry:
+  %0 = load double, double* @c, align 8
+  %1 = load double, double* @d, align 8
+  %div = fdiv double %0, %1
+  ret double %div
+; CHECK-LABEL: @emit_xsdivdp
+; CHECK: xsdivdp {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define double @emit_xsmuldp() {
+entry:
+  %0 = load double, double* @c, align 8
+  %1 = load double, double* @d, align 8
+  %mul = fmul double %0, %1
+  ret double %mul
+; CHECK-LABEL: @emit_xsmuldp
+; CHECK: xsmuldp {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define double @emit_xssqrtdp() {
+entry:
+  %0 = load double, double* @d, align 8
+  %call = call double @sqrt(double %0)
+  ret double %call
+; CHECK-LABEL: @emit_xssqrtdp
+; CHECK: xssqrtdp {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+declare double @sqrt(double)
diff --git a/test/CodeGen/PowerPC/vsx-fma-m.ll b/test/CodeGen/PowerPC/vsx-fma-m.ll
index c492e169e10f..d85927396e3e 100644
--- a/test/CodeGen/PowerPC/vsx-fma-m.ll
+++ b/test/CodeGen/PowerPC/vsx-fma-m.ll
@@ -12,7 +12,7 @@ entry:
   %0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
   store double %0, double* %d, align 8
   %1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
-  %arrayidx1 = getelementptr inbounds double* %d, i64 1
+  %arrayidx1 = getelementptr inbounds double, double* %d, i64 1
   store double %1, double* %arrayidx1, align 8
   ret void
 
@@ -39,10 +39,10 @@ entry:
   %0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
   store double %0, double* %d, align 8
   %1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
-  %arrayidx1 = getelementptr inbounds double* %d, i64 1
+  %arrayidx1 = getelementptr inbounds double, double* %d, i64 1
   store double %1, double* %arrayidx1, align 8
   %2 = tail call double @llvm.fma.f64(double %b, double %f, double %a)
-  %arrayidx2 = getelementptr inbounds double* %d, i64 2
+  %arrayidx2 = getelementptr inbounds double, double* %d, i64 2
   store double %2, double* %arrayidx2, align 8
   ret void
 
@@ -77,12 +77,12 @@ entry:
   store double %0, double* %d, align 8
   %1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
   %2 = tail call double @llvm.fma.f64(double %b, double %c, double %1)
-  %arrayidx1 = getelementptr inbounds double* %d, i64 3
+  %arrayidx1 = getelementptr inbounds double, double* %d, i64 3
   store double %2, double* %arrayidx1, align 8
   %3 = tail call double @llvm.fma.f64(double %b, double %f, double %a)
-  %arrayidx2 = getelementptr inbounds double* %d, i64 2
+  %arrayidx2 = getelementptr inbounds double, double* %d, i64 2
   store double %3, double* %arrayidx2, align 8
-  %arrayidx3 = getelementptr inbounds double* %d, i64 1
+  %arrayidx3 = getelementptr inbounds double, double* %d, i64 1
   store double %1, double* %arrayidx3, align 8
   ret void
 
@@ -98,9 +98,9 @@ entry:
 ; re-ordering the instructions.
 ; CHECK-DAG: xsmaddadp [[F1]], 2, 3
 
-; CHECK-DAG: xsmaddmdp 2, 3, 4
+; CHECK-DAG: xsmaddmdp 3, 2, 4
 ; CHECK-DAG: stxsdx [[F1]], 0, 8
-; CHECK-DAG: stxsdx 2, 8, [[C1]]
+; CHECK-DAG: stxsdx 3, 8, [[C1]]
 ; CHECK-DAG: stxsdx 1, 8, [[C2]]
 ; CHECK-DAG: stxsdx 4, 8, [[C3]]
 ; CHECK: blr
@@ -125,13 +125,13 @@ entry:
   %0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
   store double %0, double* %d, align 8
   %1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
-  %arrayidx1 = getelementptr inbounds double* %d, i64 1
+  %arrayidx1 = getelementptr inbounds double, double* %d, i64 1
   store double %1, double* %arrayidx1, align 8
   %2 = tail call double @llvm.fma.f64(double %b, double %c, double %1)
-  %arrayidx3 = getelementptr inbounds double* %d, i64 3
+  %arrayidx3 = getelementptr inbounds double, double* %d, i64 3
   store double %2, double* %arrayidx3, align 8
   %3 = tail call double @llvm.fma.f64(double %b, double %f, double %a)
-  %arrayidx4 = getelementptr inbounds double* %d, i64 2
+  %arrayidx4 = getelementptr inbounds double, double* %d, i64 2
   store double %3, double* %arrayidx4, align 8
   ret void
 
@@ -178,7 +178,7 @@ entry:
   %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)
   store <2 x double> %0, <2 x double>* %d, align 8
   %1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
-  %arrayidx1 = getelementptr inbounds <2 x double>* %d, i64 1
+  %arrayidx1 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 1
   store <2 x double> %1, <2 x double>* %arrayidx1, align 8
   ret void
 
@@ -205,10 +205,10 @@ entry:
   %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)
   store <2 x double> %0, <2 x double>* %d, align 8
   %1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
-  %arrayidx1 = getelementptr inbounds <2 x double>* %d, i64 1
+  %arrayidx1 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 1
   store <2 x double> %1, <2 x double>* %arrayidx1, align 8
   %2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a)
-  %arrayidx2 = getelementptr inbounds <2 x double>* %d, i64 2
+  %arrayidx2 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 2
   store <2 x double> %2, <2 x double>* %arrayidx2, align 8
   ret void
 
@@ -243,12 +243,12 @@ entry:
   store <2 x double> %0, <2 x double>* %d, align 8
   %1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
   %2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %1)
-  %arrayidx1 = getelementptr inbounds <2 x double>* %d, i64 3
+  %arrayidx1 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 3
   store <2 x double> %2, <2 x double>* %arrayidx1, align 8
   %3 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a)
-  %arrayidx2 = getelementptr inbounds <2 x double>* %d, i64 2
+  %arrayidx2 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 2
   store <2 x double> %3, <2 x double>* %arrayidx2, align 8
-  %arrayidx3 = getelementptr inbounds <2 x double>* %d, i64 1
+  %arrayidx3 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 1
   store <2 x double> %1, <2 x double>* %arrayidx3, align 8
   ret void
 
@@ -300,13 +300,13 @@ entry:
   %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)
   store <2 x double> %0, <2 x double>* %d, align 8
   %1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
-  %arrayidx1 = getelementptr inbounds <2 x double>* %d, i64 1
+  %arrayidx1 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 1
   store <2 x double> %1, <2 x double>* %arrayidx1, align 8
   %2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %1)
-  %arrayidx3 = getelementptr inbounds <2 x double>* %d, i64 3
+  %arrayidx3 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 3
   store <2 x double> %2, <2 x double>* %arrayidx3, align 8
   %3 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a)
-  %arrayidx4 = getelementptr inbounds <2 x double>* %d, i64 2
+  %arrayidx4 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 2
   store <2 x double> %3, <2 x double>* %arrayidx4, align 8
   ret void
 
diff --git a/test/CodeGen/PowerPC/vsx-infl-copy1.ll b/test/CodeGen/PowerPC/vsx-infl-copy1.ll
new file mode 100644
index 000000000000..531e3ad2d87c
--- /dev/null
+++ b/test/CodeGen/PowerPC/vsx-infl-copy1.ll
@@ -0,0 +1,133 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+@ub = external global [1024 x i32], align 4
+@uc = external global [1024 x i32], align 4
+
+; Function Attrs: noinline nounwind
+define void @_Z8example9Pj() #0 {
+entry:
+  br label %vector.body
+
+; CHECK-LABEL: @_Z8example9Pj
+; CHECK: xxlor
+
+vector.body:                                      ; preds = %vector.body, %entry
+  %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
+  %vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %43, %vector.body ]
+  %vec.phi20 = phi <4 x i32> [ zeroinitializer, %entry ], [ %44, %vector.body ]
+  %vec.phi21 = phi <4 x i32> [ zeroinitializer, %entry ], [ %45, %vector.body ]
+  %vec.phi23 = phi <4 x i32> [ zeroinitializer, %entry ], [ %46, %vector.body ]
+  %vec.phi24 = phi <4 x i32> [ zeroinitializer, %entry ], [ %47, %vector.body ]
+  %vec.phi25 = phi <4 x i32> [ zeroinitializer, %entry ], [ %48, %vector.body ]
+  %vec.phi26 = phi <4 x i32> [ zeroinitializer, %entry ], [ %49, %vector.body ]
+  %vec.phi27 = phi <4 x i32> [ zeroinitializer, %entry ], [ %50, %vector.body ]
+  %vec.phi28 = phi <4 x i32> [ zeroinitializer, %entry ], [ %51, %vector.body ]
+  %vec.phi29 = phi <4 x i32> [ zeroinitializer, %entry ], [ %52, %vector.body ]
+  %vec.phi30 = phi <4 x i32> [ zeroinitializer, %entry ], [ %53, %vector.body ]
+  %wide.load32 = load <4 x i32>, <4 x i32>* null, align 4
+  %.sum82 = add i64 %index, 24
+  %0 = getelementptr [1024 x i32], [1024 x i32]* @ub, i64 0, i64 %.sum82
+  %1 = bitcast i32* %0 to <4 x i32>*
+  %wide.load36 = load <4 x i32>, <4 x i32>* %1, align 4
+  %wide.load37 = load <4 x i32>, <4 x i32>* undef, align 4
+  %.sum84 = add i64 %index, 32
+  %2 = getelementptr [1024 x i32], [1024 x i32]* @ub, i64 0, i64 %.sum84
+  %3 = bitcast i32* %2 to <4 x i32>*
+  %wide.load38 = load <4 x i32>, <4 x i32>* %3, align 4
+  %.sum85 = add i64 %index, 36
+  %4 = getelementptr [1024 x i32], [1024 x i32]* @ub, i64 0, i64 %.sum85
+  %5 = bitcast i32* %4 to <4 x i32>*
+  %wide.load39 = load <4 x i32>, <4 x i32>* %5, align 4
+  %6 = getelementptr [1024 x i32], [1024 x i32]* @ub, i64 0, i64 undef
+  %7 = bitcast i32* %6 to <4 x i32>*
+  %wide.load40 = load <4 x i32>, <4 x i32>* %7, align 4
+  %.sum87 = add i64 %index, 44
+  %8 = getelementptr [1024 x i32], [1024 x i32]* @ub, i64 0, i64 %.sum87
+  %9 = bitcast i32* %8 to <4 x i32>*
+  %wide.load41 = load <4 x i32>, <4 x i32>* %9, align 4
+  %10 = getelementptr inbounds [1024 x i32], [1024 x i32]* @uc, i64 0, i64 %index
+  %11 = bitcast i32* %10 to <4 x i32>*
+  %wide.load42 = load <4 x i32>, <4 x i32>* %11, align 4
+  %.sum8889 = or i64 %index, 4
+  %12 = getelementptr [1024 x i32], [1024 x i32]* @uc, i64 0, i64 %.sum8889
+  %13 = bitcast i32* %12 to <4 x i32>*
+  %wide.load43 = load <4 x i32>, <4 x i32>* %13, align 4
+  %.sum9091 = or i64 %index, 8
+  %14 = getelementptr [1024 x i32], [1024 x i32]* @uc, i64 0, i64 %.sum9091
+  %15 = bitcast i32* %14 to <4 x i32>*
+  %wide.load44 = load <4 x i32>, <4 x i32>* %15, align 4
+  %.sum94 = add i64 %index, 16
+  %16 = getelementptr [1024 x i32], [1024 x i32]* @uc, i64 0, i64 %.sum94
+  %17 = bitcast i32* %16 to <4 x i32>*
+  %wide.load46 = load <4 x i32>, <4 x i32>* %17, align 4
+  %.sum95 = add i64 %index, 20
+  %18 = getelementptr [1024 x i32], [1024 x i32]* @uc, i64 0, i64 %.sum95
+  %19 = bitcast i32* %18 to <4 x i32>*
+  %wide.load47 = load <4 x i32>, <4 x i32>* %19, align 4
+  %20 = getelementptr [1024 x i32], [1024 x i32]* @uc, i64 0, i64 undef
+  %21 = bitcast i32* %20 to <4 x i32>*
+  %wide.load48 = load <4 x i32>, <4 x i32>* %21, align 4
+  %.sum97 = add i64 %index, 28
+  %22 = getelementptr [1024 x i32], [1024 x i32]* @uc, i64 0, i64 %.sum97
+  %23 = bitcast i32* %22 to <4 x i32>*
+  %wide.load49 = load <4 x i32>, <4 x i32>* %23, align 4
+  %.sum98 = add i64 %index, 32
+  %24 = getelementptr [1024 x i32], [1024 x i32]* @uc, i64 0, i64 %.sum98
+  %25 = bitcast i32* %24 to <4 x i32>*
+  %wide.load50 = load <4 x i32>, <4 x i32>* %25, align 4
+  %.sum99 = add i64 %index, 36
+  %26 = getelementptr [1024 x i32], [1024 x i32]* @uc, i64 0, i64 %.sum99
+  %27 = bitcast i32* %26 to <4 x i32>*
+  %wide.load51 = load <4 x i32>, <4 x i32>* %27, align 4
+  %.sum100 = add i64 %index, 40
+  %28 = getelementptr [1024 x i32], [1024 x i32]* @uc, i64 0, i64 %.sum100
+  %29 = bitcast i32* %28 to <4 x i32>*
+  %wide.load52 = load <4 x i32>, <4 x i32>* %29, align 4
+  %.sum101 = add i64 %index, 44
+  %30 = getelementptr [1024 x i32], [1024 x i32]* @uc, i64 0, i64 %.sum101
+  %31 = bitcast i32* %30 to <4 x i32>*
+  %wide.load53 = load <4 x i32>, <4 x i32>* %31, align 4
+  %32 = add <4 x i32> zeroinitializer, %vec.phi
+  %33 = add <4 x i32> zeroinitializer, %vec.phi20
+  %34 = add <4 x i32> %wide.load32, %vec.phi21
+  %35 = add <4 x i32> zeroinitializer, %vec.phi23
+  %36 = add <4 x i32> zeroinitializer, %vec.phi24
+  %37 = add <4 x i32> %wide.load36, %vec.phi25
+  %38 = add <4 x i32> %wide.load37, %vec.phi26
+  %39 = add <4 x i32> %wide.load38, %vec.phi27
+  %40 = add <4 x i32> %wide.load39, %vec.phi28
+  %41 = add <4 x i32> %wide.load40, %vec.phi29
+  %42 = add <4 x i32> %wide.load41, %vec.phi30
+  %43 = sub <4 x i32> %32, %wide.load42
+  %44 = sub <4 x i32> %33, %wide.load43
+  %45 = sub <4 x i32> %34, %wide.load44
+  %46 = sub <4 x i32> %35, %wide.load46
+  %47 = sub <4 x i32> %36, %wide.load47
+  %48 = sub <4 x i32> %37, %wide.load48
+  %49 = sub <4 x i32> %38, %wide.load49
+  %50 = sub <4 x i32> %39, %wide.load50
+  %51 = sub <4 x i32> %40, %wide.load51
+  %52 = sub <4 x i32> %41, %wide.load52
+  %53 = sub <4 x i32> %42, %wide.load53
+  %index.next = add i64 %index, 48
+  br i1 false, label %middle.block, label %vector.body
+
+middle.block:                                     ; preds = %vector.body
+  %.lcssa112 = phi <4 x i32> [ %53, %vector.body ]
+  %.lcssa111 = phi <4 x i32> [ %52, %vector.body ]
+  %.lcssa110 = phi <4 x i32> [ %51, %vector.body ]
+  %.lcssa109 = phi <4 x i32> [ %50, %vector.body ]
+  %.lcssa108 = phi <4 x i32> [ %49, %vector.body ]
+  %.lcssa107 = phi <4 x i32> [ %48, %vector.body ]
+  %.lcssa106 = phi <4 x i32> [ %47, %vector.body ]
+  %.lcssa105 = phi <4 x i32> [ %46, %vector.body ]
+  %.lcssa103 = phi <4 x i32> [ %45, %vector.body ]
+  %.lcssa102 = phi <4 x i32> [ %44, %vector.body ]
+  %.lcssa = phi <4 x i32> [ %43, %vector.body ]
+  ret void
+}
+
+attributes #0 = { noinline nounwind }
+
diff --git a/test/CodeGen/PowerPC/vsx-infl-copy2.ll b/test/CodeGen/PowerPC/vsx-infl-copy2.ll
new file mode 100644
index 000000000000..32d6f1e68bd8
--- /dev/null
+++ b/test/CodeGen/PowerPC/vsx-infl-copy2.ll
@@ -0,0 +1,114 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define void @_Z28test_goto_loop_unroll_factorILi22EiEvPKT0_iPKc(i32* nocapture readonly %first) #0 {
+entry:
+  br i1 false, label %loop2_start, label %if.end5
+
+; CHECK-LABEL: @_Z28test_goto_loop_unroll_factorILi22EiEvPKT0_iPKc
+
+loop2_start:                                      ; preds = %loop2_start, %entry
+  br i1 undef, label %loop2_start, label %if.then.i31
+
+if.end5:                                          ; preds = %entry
+  br i1 undef, label %loop_start.preheader, label %if.then.i31
+
+loop_start.preheader:                             ; preds = %if.end5
+  br i1 false, label %middle.block, label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %loop_start.preheader
+  %vec.phi61 = phi <4 x i32> [ %34, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi62 = phi <4 x i32> [ %35, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi63 = phi <4 x i32> [ %36, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi65 = phi <4 x i32> [ %37, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi67 = phi <4 x i32> [ %38, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi68 = phi <4 x i32> [ %39, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi69 = phi <4 x i32> [ %40, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi70 = phi <4 x i32> [ %41, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi71 = phi <4 x i32> [ %42, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %.sum = add i64 0, 4
+  %wide.load72 = load <4 x i32>, <4 x i32>* null, align 4
+  %.sum109 = add i64 0, 8
+  %0 = getelementptr i32, i32* %first, i64 %.sum109
+  %1 = bitcast i32* %0 to <4 x i32>*
+  %wide.load73 = load <4 x i32>, <4 x i32>* %1, align 4
+  %.sum110 = add i64 0, 12
+  %2 = getelementptr i32, i32* %first, i64 %.sum110
+  %3 = bitcast i32* %2 to <4 x i32>*
+  %wide.load74 = load <4 x i32>, <4 x i32>* %3, align 4
+  %.sum112 = add i64 0, 20
+  %4 = getelementptr i32, i32* %first, i64 %.sum112
+  %5 = bitcast i32* %4 to <4 x i32>*
+  %wide.load76 = load <4 x i32>, <4 x i32>* %5, align 4
+  %.sum114 = add i64 0, 28
+  %6 = getelementptr i32, i32* %first, i64 %.sum114
+  %7 = bitcast i32* %6 to <4 x i32>*
+  %wide.load78 = load <4 x i32>, <4 x i32>* %7, align 4
+  %.sum115 = add i64 0, 32
+  %8 = getelementptr i32, i32* %first, i64 %.sum115
+  %9 = bitcast i32* %8 to <4 x i32>*
+  %wide.load79 = load <4 x i32>, <4 x i32>* %9, align 4
+  %.sum116 = add i64 0, 36
+  %10 = getelementptr i32, i32* %first, i64 %.sum116
+  %11 = bitcast i32* %10 to <4 x i32>*
+  %wide.load80 = load <4 x i32>, <4 x i32>* %11, align 4
+  %.sum117 = add i64 0, 40
+  %12 = getelementptr i32, i32* %first, i64 %.sum117
+  %13 = bitcast i32* %12 to <4 x i32>*
+  %wide.load81 = load <4 x i32>, <4 x i32>* %13, align 4
+  %.sum118 = add i64 0, 44
+  %14 = getelementptr i32, i32* %first, i64 %.sum118
+  %15 = bitcast i32* %14 to <4 x i32>*
+  %wide.load82 = load <4 x i32>, <4 x i32>* %15, align 4
+  %16 = mul <4 x i32> %wide.load72, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %17 = mul <4 x i32> %wide.load73, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %18 = mul <4 x i32> %wide.load74, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %19 = mul <4 x i32> %wide.load76, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %20 = mul <4 x i32> %wide.load78, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %21 = mul <4 x i32> %wide.load79, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %22 = mul <4 x i32> %wide.load80, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %23 = mul <4 x i32> %wide.load81, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %24 = mul <4 x i32> %wide.load82, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %25 = add <4 x i32> %16, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %26 = add <4 x i32> %17, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %27 = add <4 x i32> %18, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %28 = add <4 x i32> %19, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %29 = add <4 x i32> %20, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %30 = add <4 x i32> %21, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %31 = add <4 x i32> %22, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %32 = add <4 x i32> %23, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %33 = add <4 x i32> %24, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %34 = add nsw <4 x i32> %25, %vec.phi61
+  %35 = add nsw <4 x i32> %26, %vec.phi62
+  %36 = add nsw <4 x i32> %27, %vec.phi63
+  %37 = add nsw <4 x i32> %28, %vec.phi65
+  %38 = add nsw <4 x i32> %29, %vec.phi67
+  %39 = add nsw <4 x i32> %30, %vec.phi68
+  %40 = add nsw <4 x i32> %31, %vec.phi69
+  %41 = add nsw <4 x i32> %32, %vec.phi70
+  %42 = add nsw <4 x i32> %33, %vec.phi71
+  br i1 false, label %middle.block, label %vector.body
+
+middle.block:                                     ; preds = %vector.body, %loop_start.preheader
+  %rdx.vec.exit.phi85 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %34, %vector.body ]
+  %rdx.vec.exit.phi86 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %35, %vector.body ]
+  %rdx.vec.exit.phi87 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %36, %vector.body ]
+  %rdx.vec.exit.phi89 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %37, %vector.body ]
+  %rdx.vec.exit.phi91 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %38, %vector.body ]
+  %rdx.vec.exit.phi92 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %39, %vector.body ]
+  %rdx.vec.exit.phi93 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %40, %vector.body ]
+  %rdx.vec.exit.phi94 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %41, %vector.body ]
+  %rdx.vec.exit.phi95 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %42, %vector.body ]
+  br i1 false, label %if.then.i31, label %loop_start.prol
+
+loop_start.prol:                                  ; preds = %loop_start.prol, %middle.block
+  br label %loop_start.prol
+
+if.then.i31:                                      ; preds = %middle.block, %if.end5, %loop2_start
+  unreachable
+}
+
+attributes #0 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll b/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll
index 7367672eab8b..d6940e46df37 100644
--- a/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll
+++ b/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll
@@ -1,7 +1,6 @@
 ; RUN: llc -mcpu=pwr8 -mattr=+vsx -O2 -mtriple=powerpc64le-unknown-linux-gnu < %s > %t
 ; RUN: grep lxvd2x < %t | count 18
 ; RUN: grep stxvd2x < %t | count 18
-; RUN: grep xxpermdi < %t | count 36
 
 @vf = global <4 x float> <float -1.500000e+00, float 2.500000e+00, float -3.500000e+00, float 4.500000e+00>, align 16
 @vd = global <2 x double> <double 3.500000e+00, double -7.500000e+00>, align 16
@@ -51,117 +50,117 @@ entry:
   %__b.addr.i = alloca <4 x i32>*, align 8
   store i32 0, i32* %__a.addr.i, align 4
   store <4 x i32>* @vsi, <4 x i32>** %__b.addr.i, align 8
-  %0 = load i32* %__a.addr.i, align 4
-  %1 = load <4 x i32>** %__b.addr.i, align 8
+  %0 = load i32, i32* %__a.addr.i, align 4
+  %1 = load <4 x i32>*, <4 x i32>** %__b.addr.i, align 8
   %2 = bitcast <4 x i32>* %1 to i8*
-  %3 = getelementptr i8* %2, i32 %0
+  %3 = getelementptr i8, i8* %2, i32 %0
   %4 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %3)
   store <4 x i32> %4, <4 x i32>* @res_vsi, align 16
   store i32 0, i32* %__a.addr.i31, align 4
   store <4 x i32>* @vui, <4 x i32>** %__b.addr.i32, align 8
-  %5 = load i32* %__a.addr.i31, align 4
-  %6 = load <4 x i32>** %__b.addr.i32, align 8
+  %5 = load i32, i32* %__a.addr.i31, align 4
+  %6 = load <4 x i32>*, <4 x i32>** %__b.addr.i32, align 8
   %7 = bitcast <4 x i32>* %6 to i8*
-  %8 = getelementptr i8* %7, i32 %5
+  %8 = getelementptr i8, i8* %7, i32 %5
   %9 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %8)
   store <4 x i32> %9, <4 x i32>* @res_vui, align 16
   store i32 0, i32* %__a.addr.i29, align 4
   store <4 x float>* @vf, <4 x float>** %__b.addr.i30, align 8
-  %10 = load i32* %__a.addr.i29, align 4
-  %11 = load <4 x float>** %__b.addr.i30, align 8
+  %10 = load i32, i32* %__a.addr.i29, align 4
+  %11 = load <4 x float>*, <4 x float>** %__b.addr.i30, align 8
   %12 = bitcast <4 x float>* %11 to i8*
-  %13 = getelementptr i8* %12, i32 %10
+  %13 = getelementptr i8, i8* %12, i32 %10
   %14 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %13)
   %15 = bitcast <4 x i32> %14 to <4 x float>
   store <4 x float> %15, <4 x float>* @res_vf, align 16
   store i32 0, i32* %__a.addr.i27, align 4
   store <2 x i64>* @vsll, <2 x i64>** %__b.addr.i28, align 8
-  %16 = load i32* %__a.addr.i27, align 4
-  %17 = load <2 x i64>** %__b.addr.i28, align 8
+  %16 = load i32, i32* %__a.addr.i27, align 4
+  %17 = load <2 x i64>*, <2 x i64>** %__b.addr.i28, align 8
   %18 = bitcast <2 x i64>* %17 to i8*
-  %19 = getelementptr i8* %18, i32 %16
+  %19 = getelementptr i8, i8* %18, i32 %16
   %20 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %19)
   %21 = bitcast <2 x double> %20 to <2 x i64>
   store <2 x i64> %21, <2 x i64>* @res_vsll, align 16
   store i32 0, i32* %__a.addr.i25, align 4
   store <2 x i64>* @vull, <2 x i64>** %__b.addr.i26, align 8
-  %22 = load i32* %__a.addr.i25, align 4
-  %23 = load <2 x i64>** %__b.addr.i26, align 8
+  %22 = load i32, i32* %__a.addr.i25, align 4
+  %23 = load <2 x i64>*, <2 x i64>** %__b.addr.i26, align 8
   %24 = bitcast <2 x i64>* %23 to i8*
-  %25 = getelementptr i8* %24, i32 %22
+  %25 = getelementptr i8, i8* %24, i32 %22
   %26 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %25)
   %27 = bitcast <2 x double> %26 to <2 x i64>
   store <2 x i64> %27, <2 x i64>* @res_vull, align 16
   store i32 0, i32* %__a.addr.i23, align 4
   store <2 x double>* @vd, <2 x double>** %__b.addr.i24, align 8
-  %28 = load i32* %__a.addr.i23, align 4
-  %29 = load <2 x double>** %__b.addr.i24, align 8
+  %28 = load i32, i32* %__a.addr.i23, align 4
+  %29 = load <2 x double>*, <2 x double>** %__b.addr.i24, align 8
   %30 = bitcast <2 x double>* %29 to i8*
-  %31 = getelementptr i8* %30, i32 %28
+  %31 = getelementptr i8, i8* %30, i32 %28
   %32 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %31)
   store <2 x double> %32, <2 x double>* @res_vd, align 16
-  %33 = load <4 x i32>* @vsi, align 16
+  %33 = load <4 x i32>, <4 x i32>* @vsi, align 16
   store <4 x i32> %33, <4 x i32>* %__a.addr.i20, align 16
   store i32 0, i32* %__b.addr.i21, align 4
   store <4 x i32>* @res_vsi, <4 x i32>** %__c.addr.i22, align 8
-  %34 = load <4 x i32>* %__a.addr.i20, align 16
-  %35 = load i32* %__b.addr.i21, align 4
-  %36 = load <4 x i32>** %__c.addr.i22, align 8
+  %34 = load <4 x i32>, <4 x i32>* %__a.addr.i20, align 16
+  %35 = load i32, i32* %__b.addr.i21, align 4
+  %36 = load <4 x i32>*, <4 x i32>** %__c.addr.i22, align 8
   %37 = bitcast <4 x i32>* %36 to i8*
-  %38 = getelementptr i8* %37, i32 %35
+  %38 = getelementptr i8, i8* %37, i32 %35
   call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %34, i8* %38)
-  %39 = load <4 x i32>* @vui, align 16
+  %39 = load <4 x i32>, <4 x i32>* @vui, align 16
   store <4 x i32> %39, <4 x i32>* %__a.addr.i17, align 16
   store i32 0, i32* %__b.addr.i18, align 4
   store <4 x i32>* @res_vui, <4 x i32>** %__c.addr.i19, align 8
-  %40 = load <4 x i32>* %__a.addr.i17, align 16
-  %41 = load i32* %__b.addr.i18, align 4
-  %42 = load <4 x i32>** %__c.addr.i19, align 8
+  %40 = load <4 x i32>, <4 x i32>* %__a.addr.i17, align 16
+  %41 = load i32, i32* %__b.addr.i18, align 4
+  %42 = load <4 x i32>*, <4 x i32>** %__c.addr.i19, align 8
   %43 = bitcast <4 x i32>* %42 to i8*
-  %44 = getelementptr i8* %43, i32 %41
+  %44 = getelementptr i8, i8* %43, i32 %41
   call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %40, i8* %44)
-  %45 = load <4 x float>* @vf, align 16
+  %45 = load <4 x float>, <4 x float>* @vf, align 16
   store <4 x float> %45, <4 x float>* %__a.addr.i14, align 16
   store i32 0, i32* %__b.addr.i15, align 4
   store <4 x float>* @res_vf, <4 x float>** %__c.addr.i16, align 8
-  %46 = load <4 x float>* %__a.addr.i14, align 16
+  %46 = load <4 x float>, <4 x float>* %__a.addr.i14, align 16
   %47 = bitcast <4 x float> %46 to <4 x i32>
-  %48 = load i32* %__b.addr.i15, align 4
-  %49 = load <4 x float>** %__c.addr.i16, align 8
+  %48 = load i32, i32* %__b.addr.i15, align 4
+  %49 = load <4 x float>*, <4 x float>** %__c.addr.i16, align 8
   %50 = bitcast <4 x float>* %49 to i8*
-  %51 = getelementptr i8* %50, i32 %48
+  %51 = getelementptr i8, i8* %50, i32 %48
   call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %47, i8* %51) #1
-  %52 = load <2 x i64>* @vsll, align 16
+  %52 = load <2 x i64>, <2 x i64>* @vsll, align 16
   store <2 x i64> %52, <2 x i64>* %__a.addr.i11, align 16
   store i32 0, i32* %__b.addr.i12, align 4
   store <2 x i64>* @res_vsll, <2 x i64>** %__c.addr.i13, align 8
-  %53 = load <2 x i64>* %__a.addr.i11, align 16
+  %53 = load <2 x i64>, <2 x i64>* %__a.addr.i11, align 16
   %54 = bitcast <2 x i64> %53 to <2 x double>
-  %55 = load i32* %__b.addr.i12, align 4
-  %56 = load <2 x i64>** %__c.addr.i13, align 8
+  %55 = load i32, i32* %__b.addr.i12, align 4
+  %56 = load <2 x i64>*, <2 x i64>** %__c.addr.i13, align 8
   %57 = bitcast <2 x i64>* %56 to i8*
-  %58 = getelementptr i8* %57, i32 %55
+  %58 = getelementptr i8, i8* %57, i32 %55
   call void @llvm.ppc.vsx.stxvd2x(<2 x double> %54, i8* %58)
-  %59 = load <2 x i64>* @vull, align 16
+  %59 = load <2 x i64>, <2 x i64>* @vull, align 16
   store <2 x i64> %59, <2 x i64>* %__a.addr.i8, align 16
   store i32 0, i32* %__b.addr.i9, align 4
   store <2 x i64>* @res_vull, <2 x i64>** %__c.addr.i10, align 8
-  %60 = load <2 x i64>* %__a.addr.i8, align 16
+  %60 = load <2 x i64>, <2 x i64>* %__a.addr.i8, align 16
   %61 = bitcast <2 x i64> %60 to <2 x double>
-  %62 = load i32* %__b.addr.i9, align 4
-  %63 = load <2 x i64>** %__c.addr.i10, align 8
+  %62 = load i32, i32* %__b.addr.i9, align 4
+  %63 = load <2 x i64>*, <2 x i64>** %__c.addr.i10, align 8
   %64 = bitcast <2 x i64>* %63 to i8*
-  %65 = getelementptr i8* %64, i32 %62
+  %65 = getelementptr i8, i8* %64, i32 %62
   call void @llvm.ppc.vsx.stxvd2x(<2 x double> %61, i8* %65)
-  %66 = load <2 x double>* @vd, align 16
+  %66 = load <2 x double>, <2 x double>* @vd, align 16
   store <2 x double> %66, <2 x double>* %__a.addr.i6, align 16
   store i32 0, i32* %__b.addr.i7, align 4
   store <2 x double>* @res_vd, <2 x double>** %__c.addr.i, align 8
-  %67 = load <2 x double>* %__a.addr.i6, align 16
-  %68 = load i32* %__b.addr.i7, align 4
-  %69 = load <2 x double>** %__c.addr.i, align 8
+  %67 = load <2 x double>, <2 x double>* %__a.addr.i6, align 16
+  %68 = load i32, i32* %__b.addr.i7, align 4
+  %69 = load <2 x double>*, <2 x double>** %__c.addr.i, align 8
   %70 = bitcast <2 x double>* %69 to i8*
-  %71 = getelementptr i8* %70, i32 %68
+  %71 = getelementptr i8, i8* %70, i32 %68
   call void @llvm.ppc.vsx.stxvd2x(<2 x double> %67, i8* %71)
   ret void
 }
diff --git a/test/CodeGen/PowerPC/vsx-ldst.ll b/test/CodeGen/PowerPC/vsx-ldst.ll
index 688187d1fcb6..7f12b0480e13 100644
--- a/test/CodeGen/PowerPC/vsx-ldst.ll
+++ b/test/CodeGen/PowerPC/vsx-ldst.ll
@@ -12,7 +12,6 @@
 ; RUN: llc -mcpu=pwr8 -mattr=+vsx -O2 -mtriple=powerpc64le-unknown-linux-gnu < %s > %t
 ; RUN: grep lxvd2x < %t | count 6
 ; RUN: grep stxvd2x < %t | count 6
-; RUN: grep xxpermdi < %t | count 12
 
 @vsi = global <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, align 16
 @vui = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
@@ -30,12 +29,12 @@
 ; Function Attrs: nounwind
 define void @test1() {
 entry:
-  %0 = load <4 x i32>* @vsi, align 16
-  %1 = load <4 x i32>* @vui, align 16
-  %2 = load <4 x i32>* bitcast (<4 x float>* @vf to <4 x i32>*), align 16
-  %3 = load <2 x double>* bitcast (<2 x i64>* @vsll to <2 x double>*), align 16
-  %4 = load <2 x double>* bitcast (<2 x i64>* @vull to <2 x double>*), align 16
-  %5 = load <2 x double>* @vd, align 16
+  %0 = load <4 x i32>, <4 x i32>* @vsi, align 16
+  %1 = load <4 x i32>, <4 x i32>* @vui, align 16
+  %2 = load <4 x i32>, <4 x i32>* bitcast (<4 x float>* @vf to <4 x i32>*), align 16
+  %3 = load <2 x double>, <2 x double>* bitcast (<2 x i64>* @vsll to <2 x double>*), align 16
+  %4 = load <2 x double>, <2 x double>* bitcast (<2 x i64>* @vull to <2 x double>*), align 16
+  %5 = load <2 x double>, <2 x double>* @vd, align 16
   store <4 x i32> %0, <4 x i32>* @res_vsi, align 16
   store <4 x i32> %1, <4 x i32>* @res_vui, align 16
   store <4 x i32> %2, <4 x i32>* bitcast (<4 x float>* @res_vf to <4 x i32>*), align 16
diff --git a/test/CodeGen/PowerPC/vsx-minmax.ll b/test/CodeGen/PowerPC/vsx-minmax.ll
index 47f50abbc2a2..ad72cacae2a0 100644
--- a/test/CodeGen/PowerPC/vsx-minmax.ll
+++ b/test/CodeGen/PowerPC/vsx-minmax.ll
@@ -18,35 +18,35 @@ target triple = "powerpc64-unknown-linux-gnu"
 define void @test1() #0 {
 ; CHECK-LABEL: @test1
 entry:
-  %0 = load volatile <4 x float>* @vf, align 16
-  %1 = load volatile <4 x float>* @vf, align 16
+  %0 = load volatile <4 x float>, <4 x float>* @vf, align 16
+  %1 = load volatile <4 x float>, <4 x float>* @vf, align 16
   %2 = tail call <4 x float> @llvm.ppc.vsx.xvmaxsp(<4 x float> %0, <4 x float> %1)
 ; CHECK: xvmaxsp
   store <4 x float> %2, <4 x float>* @vf1, align 16
-  %3 = load <2 x double>* @vd, align 16
+  %3 = load <2 x double>, <2 x double>* @vd, align 16
   %4 = tail call <2 x double> @llvm.ppc.vsx.xvmaxdp(<2 x double> %3, <2 x double> %3)
 ; CHECK: xvmaxdp
   store <2 x double> %4, <2 x double>* @vd1, align 16
-  %5 = load volatile <4 x float>* @vf, align 16
-  %6 = load volatile <4 x float>* @vf, align 16
+  %5 = load volatile <4 x float>, <4 x float>* @vf, align 16
+  %6 = load volatile <4 x float>, <4 x float>* @vf, align 16
   %7 = tail call <4 x float> @llvm.ppc.vsx.xvmaxsp(<4 x float> %5, <4 x float> %6)
 ; CHECK: xvmaxsp
   store <4 x float> %7, <4 x float>* @vf2, align 16
-  %8 = load volatile <4 x float>* @vf, align 16
-  %9 = load volatile <4 x float>* @vf, align 16
+  %8 = load volatile <4 x float>, <4 x float>* @vf, align 16
+  %9 = load volatile <4 x float>, <4 x float>* @vf, align 16
   %10 = tail call <4 x float> @llvm.ppc.vsx.xvminsp(<4 x float> %8, <4 x float> %9)
 ; CHECK: xvminsp
   store <4 x float> %10, <4 x float>* @vf3, align 16
-  %11 = load <2 x double>* @vd, align 16
+  %11 = load <2 x double>, <2 x double>* @vd, align 16
   %12 = tail call <2 x double> @llvm.ppc.vsx.xvmindp(<2 x double> %11, <2 x double> %11)
 ; CHECK: xvmindp
   store <2 x double> %12, <2 x double>* @vd2, align 16
-  %13 = load volatile <4 x float>* @vf, align 16
-  %14 = load volatile <4 x float>* @vf, align 16
+  %13 = load volatile <4 x float>, <4 x float>* @vf, align 16
+  %14 = load volatile <4 x float>, <4 x float>* @vf, align 16
   %15 = tail call <4 x float> @llvm.ppc.vsx.xvminsp(<4 x float> %13, <4 x float> %14)
 ; CHECK: xvminsp
   store <4 x float> %15, <4 x float>* @vf4, align 16
-  %16 = load double* @d, align 8
+  %16 = load double, double* @d, align 8
   %17 = tail call double @llvm.ppc.vsx.xsmaxdp(double %16, double %16)
 ; CHECK: xsmaxdp
   store double %17, double* @d1, align 8
diff --git a/test/CodeGen/PowerPC/vsx-p8.ll b/test/CodeGen/PowerPC/vsx-p8.ll
index d5a19059c60d..878714baab72 100644
--- a/test/CodeGen/PowerPC/vsx-p8.ll
+++ b/test/CodeGen/PowerPC/vsx-p8.ll
@@ -8,7 +8,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 ; Unaligned loads/stores on P8 and later should use VSX where possible.
 
 define <2 x double> @test28u(<2 x double>* %a) {
-  %v = load <2 x double>* %a, align 8
+  %v = load <2 x double>, <2 x double>* %a, align 8
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test28u
@@ -26,7 +26,7 @@ define void @test29u(<2 x double>* %a, <2 x double> %b) {
 }
 
 define <4 x float> @test32u(<4 x float>* %a) {
-  %v = load <4 x float>* %a, align 8
+  %v = load <4 x float>, <4 x float>* %a, align 8
   ret <4 x float> %v
 
 ; CHECK-REG-LABEL: @test32u
diff --git a/test/CodeGen/PowerPC/vsx-recip-est.ll b/test/CodeGen/PowerPC/vsx-recip-est.ll
new file mode 100644
index 000000000000..f589c6c103e8
--- /dev/null
+++ b/test/CodeGen/PowerPC/vsx-recip-est.ll
@@ -0,0 +1,62 @@
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -enable-unsafe-fp-math | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-unsafe-fp-math | FileCheck %s
+@a = global float 3.000000e+00, align 4
+@b = global float 4.000000e+00, align 4
+@c = global double 3.000000e+00, align 8
+@d = global double 4.000000e+00, align 8
+
+; Function Attrs: nounwind
+define float @emit_xsresp() {
+entry:
+  %0 = load float, float* @a, align 4
+  %1 = load float, float* @b, align 4
+  %div = fdiv fast float %0, %1
+  ret float %div
+; CHECK-LABEL: @emit_xsresp
+; CHECK: xsresp {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define float @emit_xsrsqrtesp(float %f) {
+entry:
+  %f.addr = alloca float, align 4
+  store float %f, float* %f.addr, align 4
+  %0 = load float, float* %f.addr, align 4
+  %1 = load float, float* @b, align 4
+  %2 = call float @llvm.sqrt.f32(float %1)
+  %div = fdiv fast float %0, %2
+  ret float %div
+; CHECK-LABEL: @emit_xsrsqrtesp
+; CHECK: xsrsqrtesp {{[0-9]+}}
+}
+
+; Function Attrs: nounwind readnone
+declare float @llvm.sqrt.f32(float)
+
+; Function Attrs: nounwind
+define double @emit_xsredp() {
+entry:
+  %0 = load double, double* @c, align 8
+  %1 = load double, double* @d, align 8
+  %div = fdiv fast double %0, %1
+  ret double %div
+; CHECK-LABEL: @emit_xsredp
+; CHECK: xsredp {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define double @emit_xsrsqrtedp(double %f) {
+entry:
+  %f.addr = alloca double, align 8
+  store double %f, double* %f.addr, align 8
+  %0 = load double, double* %f.addr, align 8
+  %1 = load double, double* @d, align 8
+  %2 = call double @llvm.sqrt.f64(double %1)
+  %div = fdiv fast double %0, %2
+  ret double %div
+; CHECK-LABEL: @emit_xsrsqrtedp
+; CHECK: xsrsqrtedp {{[0-9]+}}
+}
+
+; Function Attrs: nounwind readnone
+declare double @llvm.sqrt.f64(double) #1
diff --git a/test/CodeGen/PowerPC/vsx-spill-norwstore.ll b/test/CodeGen/PowerPC/vsx-spill-norwstore.ll
new file mode 100644
index 000000000000..77b6cb29b24b
--- /dev/null
+++ b/test/CodeGen/PowerPC/vsx-spill-norwstore.ll
@@ -0,0 +1,63 @@
+; RUN: llc -mcpu=pwr7 -verify-machineinstrs < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+@.str1 = external unnamed_addr constant [5 x i8], align 1
+@.str10 = external unnamed_addr constant [9 x i8], align 1
+
+; Function Attrs: nounwind
+define void @main() #0 {
+; CHECK-LABEL: @main
+; Make sure that the stxvd2x passes -verify-machineinstrs
+; CHECK: stxvd2x
+
+entry:
+  %0 = tail call <8 x i16> @llvm.ppc.altivec.vupkhsb(<16 x i8> <i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1>) #0
+  %1 = tail call <8 x i16> @llvm.ppc.altivec.vupklsb(<16 x i8> <i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1>) #0
+  br i1 false, label %if.then.i68.i, label %check.exit69.i
+
+if.then.i68.i:                                    ; preds = %entry
+  unreachable
+
+check.exit69.i:                                   ; preds = %entry
+  br i1 undef, label %if.then.i63.i, label %check.exit64.i
+
+if.then.i63.i:                                    ; preds = %check.exit69.i
+  tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str10, i64 0, i64 0), i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str1, i64 0, i64 0)) #0
+  br label %check.exit64.i
+
+check.exit64.i:                                   ; preds = %if.then.i63.i, %check.exit69.i
+  %2 = tail call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> %0, <8 x i16> <i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 0, i16 -1, i16 0>) #0
+  %tobool.i55.i = icmp eq i32 %2, 0
+  br i1 %tobool.i55.i, label %if.then.i58.i, label %check.exit59.i
+
+if.then.i58.i:                                    ; preds = %check.exit64.i
+  unreachable
+
+check.exit59.i:                                   ; preds = %check.exit64.i
+  %3 = tail call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> %1, <8 x i16> <i16 -1, i16 0, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1>) #0
+  %tobool.i50.i = icmp eq i32 %3, 0
+  br i1 %tobool.i50.i, label %if.then.i53.i, label %check.exit54.i
+
+if.then.i53.i:                                    ; preds = %check.exit59.i
+  unreachable
+
+check.exit54.i:                                   ; preds = %check.exit59.i
+  unreachable
+}
+
+; Function Attrs: nounwind readnone
+declare <8 x i16> @llvm.ppc.altivec.vupkhsb(<16 x i8>) #1
+
+; Function Attrs: nounwind readnone
+declare <8 x i16> @llvm.ppc.altivec.vupklsb(<16 x i8>) #1
+
+; Function Attrs: nounwind
+declare void @printf(i8* nocapture readonly, ...) #0
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.altivec.vcmpequh.p(i32, <8 x i16>, <8 x i16>) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
+
diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll
index f91ffdb960bb..b185fed4cd5b 100644
--- a/test/CodeGen/PowerPC/vsx.ll
+++ b/test/CodeGen/PowerPC/vsx.ll
@@ -501,7 +501,7 @@ define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {
 }
 
 define <2 x double> @test28(<2 x double>* %a) {
-  %v = load <2 x double>* %a, align 16
+  %v = load <2 x double>, <2 x double>* %a, align 16
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test28
@@ -519,7 +519,7 @@ define void @test29(<2 x double>* %a, <2 x double> %b) {
 }
 
 define <2 x double> @test28u(<2 x double>* %a) {
-  %v = load <2 x double>* %a, align 8
+  %v = load <2 x double>, <2 x double>* %a, align 8
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test28u
@@ -537,7 +537,7 @@ define void @test29u(<2 x double>* %a, <2 x double> %b) {
 }
 
 define <2 x i64> @test30(<2 x i64>* %a) {
-  %v = load <2 x i64>* %a, align 16
+  %v = load <2 x i64>, <2 x i64>* %a, align 16
   ret <2 x i64> %v
 
 ; CHECK-REG-LABEL: @test30
@@ -562,7 +562,7 @@ define void @test31(<2 x i64>* %a, <2 x i64> %b) {
 }
 
 define <4 x float> @test32(<4 x float>* %a) {
-  %v = load <4 x float>* %a, align 16
+  %v = load <4 x float>, <4 x float>* %a, align 16
   ret <4 x float> %v
 
 ; CHECK-REG-LABEL: @test32
@@ -590,7 +590,7 @@ define void @test33(<4 x float>* %a, <4 x float> %b) {
 }
 
 define <4 x float> @test32u(<4 x float>* %a) {
-  %v = load <4 x float>* %a, align 8
+  %v = load <4 x float>, <4 x float>* %a, align 8
   ret <4 x float> %v
 
 ; CHECK-LABEL: @test32u
@@ -616,7 +616,7 @@ define void @test33u(<4 x float>* %a, <4 x float> %b) {
 }
 
 define <4 x i32> @test34(<4 x i32>* %a) {
-  %v = load <4 x i32>* %a, align 16
+  %v = load <4 x i32>, <4 x i32>* %a, align 16
   ret <4 x i32> %v
 
 ; CHECK-REG-LABEL: @test34
@@ -718,7 +718,7 @@ define <2 x i64> @test47(<2 x float> %a) {
 }
 
 define <2 x double> @test50(double* %a) {
-  %v = load double* %a, align 8
+  %v = load double, double* %a, align 8
   %w = insertelement <2 x double> undef, double %v, i32 0
   %x = insertelement <2 x double> %w, double %v, i32 1
   ret <2 x double> %x
@@ -733,7 +733,7 @@ define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test51
-; CHECK: xxpermdi 34, 34, 34, 0
+; CHECK: xxspltd 34, 34, 0
 ; CHECK: blr
 }
 
@@ -742,7 +742,7 @@ define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test52
-; CHECK: xxpermdi 34, 34, 35, 0
+; CHECK: xxmrghd 34, 34, 35
 ; CHECK: blr
 }
 
@@ -751,7 +751,7 @@ define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test53
-; CHECK: xxpermdi 34, 35, 34, 0
+; CHECK: xxmrghd 34, 35, 34
 ; CHECK: blr
 }
 
@@ -769,7 +769,7 @@ define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test55
-; CHECK: xxpermdi 34, 34, 35, 3
+; CHECK: xxmrgld 34, 34, 35
 ; CHECK: blr
 }
 
@@ -778,7 +778,7 @@ define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
   ret <2 x i64> %v
 
 ; CHECK-LABEL: @test56
-; CHECK: xxpermdi 34, 34, 35, 3
+; CHECK: xxmrgld 34, 34, 35
 ; CHECK: blr
 }
 
@@ -843,11 +843,11 @@ define double @test64(<2 x double> %a) {
   ret double %v
 
 ; CHECK-REG-LABEL: @test64
-; CHECK-REG: xxpermdi 1, 34, 34, 2
+; CHECK-REG: xxswapd 1, 34
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test64
-; CHECK-FISL: xxpermdi 34, 34, 34, 2
+; CHECK-FISL: xxswapd  34, 34
 ; CHECK-FISL: xxlor 0, 34, 34
 ; CHECK-FISL: fmr 1, 0
 ; CHECK-FISL: blr
diff --git a/test/CodeGen/PowerPC/vsx_insert_extract_le.ll b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
index 0a9df3779116..84bbdd75b0f7 100644
--- a/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
+++ b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
@@ -1,35 +1,35 @@
 ; RUN: llc -mcpu=pwr8 -mattr=+vsx -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
 define <2 x double> @testi0(<2 x double>* %p1, double* %p2) {
-  %v = load <2 x double>* %p1
-  %s = load double* %p2
+  %v = load <2 x double>, <2 x double>* %p1
+  %s = load double, double* %p2
   %r = insertelement <2 x double> %v, double %s, i32 0
   ret <2 x double> %r
 
 ; CHECK-LABEL: testi0
 ; CHECK: lxvd2x 0, 0, 3
 ; CHECK: lxsdx 34, 0, 4
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 1, 34, 34, 0
+; CHECK: xxswapd 0, 0
+; CHECK: xxspltd 1, 34, 0
 ; CHECK: xxpermdi 34, 0, 1, 1
 }
 
 define <2 x double> @testi1(<2 x double>* %p1, double* %p2) {
-  %v = load <2 x double>* %p1
-  %s = load double* %p2
+  %v = load <2 x double>, <2 x double>* %p1
+  %s = load double, double* %p2
   %r = insertelement <2 x double> %v, double %s, i32 1
   ret <2 x double> %r
 
 ; CHECK-LABEL: testi1
 ; CHECK: lxvd2x 0, 0, 3
 ; CHECK: lxsdx 34, 0, 4
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 1, 34, 34, 0
-; CHECK: xxpermdi 34, 1, 0, 3
+; CHECK: xxswapd 0, 0
+; CHECK: xxspltd 1, 34, 0
+; CHECK: xxmrgld 34, 1, 0
 }
 
 define double @teste0(<2 x double>* %p1) {
-  %v = load <2 x double>* %p1
+  %v = load <2 x double>, <2 x double>* %p1
   %r = extractelement <2 x double> %v, i32 0
   ret double %r
 
@@ -37,16 +37,16 @@ define double @teste0(<2 x double>* %p1) {
 
 ; CHECK-LABEL: teste0
 ; CHECK: lxvd2x 0, 0, 3
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 1, 0, 0, 2
+; CHECK: xxswapd 0, 0
+; CHECK: xxswapd 1, 0
 }
 
 define double @teste1(<2 x double>* %p1) {
-  %v = load <2 x double>* %p1
+  %v = load <2 x double>, <2 x double>* %p1
   %r = extractelement <2 x double> %v, i32 1
   ret double %r
 
 ; CHECK-LABEL: teste1
 ; CHECK: lxvd2x 0, 0, 3
-; CHECK: xxpermdi 1, 0, 0, 2
+; CHECK: xxswapd 1, 0
 }
diff --git a/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll b/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll
new file mode 100644
index 000000000000..102970885963
--- /dev/null
+++ b/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll
@@ -0,0 +1,139 @@
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
+
+@d = common global double 0.000000e+00, align 8
+@f = common global float 0.000000e+00, align 4
+@i = common global i32 0, align 4
+@ui = common global i32 0, align 4
+
+; Function Attrs: nounwind
+define void @dblToInt() #0 {
+entry:
+  %ii = alloca i32, align 4
+  %0 = load double, double* @d, align 8
+  %conv = fptosi double %0 to i32
+  store volatile i32 %conv, i32* %ii, align 4
+  ret void
+; CHECK-LABEL: @dblToInt
+; CHECK: xscvdpsxws [[REGCONV1:[0-9]+]],
+; CHECK: stxsiwx [[REGCONV1]],
+}
+
+; Function Attrs: nounwind
+define void @fltToInt() #0 {
+entry:
+  %ii = alloca i32, align 4
+  %0 = load float, float* @f, align 4
+  %conv = fptosi float %0 to i32
+  store volatile i32 %conv, i32* %ii, align 4
+  ret void
+; CHECK-LABEL: @fltToInt
+; CHECK: xscvdpsxws [[REGCONV2:[0-9]+]],
+; CHECK: stxsiwx [[REGCONV2]],
+}
+
+; Function Attrs: nounwind
+define void @intToDbl() #0 {
+entry:
+  %dd = alloca double, align 8
+  %0 = load i32, i32* @i, align 4
+  %conv = sitofp i32 %0 to double
+  store volatile double %conv, double* %dd, align 8
+  ret void
+; CHECK-LABEL: @intToDbl
+; CHECK: lxsiwax [[REGLD1:[0-9]+]],
+; CHECK: xscvsxddp {{[0-9]+}}, [[REGLD1]]
+}
+
+; Function Attrs: nounwind
+define void @intToFlt() #0 {
+entry:
+  %ff = alloca float, align 4
+  %0 = load i32, i32* @i, align 4
+  %conv = sitofp i32 %0 to float
+  store volatile float %conv, float* %ff, align 4
+  ret void
+; CHECK-LABEL: @intToFlt
+; CHECK: lxsiwax [[REGLD2:[0-9]+]],
+; FIXME: the below will change when the VSX form is implemented
+; CHECK: fcfids {{[0-9]}}, [[REGLD2]]
+}
+
+; Function Attrs: nounwind
+define void @dblToUInt() #0 {
+entry:
+  %uiui = alloca i32, align 4
+  %0 = load double, double* @d, align 8
+  %conv = fptoui double %0 to i32
+  store volatile i32 %conv, i32* %uiui, align 4
+  ret void
+; CHECK-LABEL: @dblToUInt
+; CHECK: xscvdpuxws [[REGCONV3:[0-9]+]],
+; CHECK: stxsiwx [[REGCONV3]],
+}
+
+; Function Attrs: nounwind
+define void @fltToUInt() #0 {
+entry:
+  %uiui = alloca i32, align 4
+  %0 = load float, float* @f, align 4
+  %conv = fptoui float %0 to i32
+  store volatile i32 %conv, i32* %uiui, align 4
+  ret void
+; CHECK-LABEL: @fltToUInt
+; CHECK: xscvdpuxws [[REGCONV4:[0-9]+]],
+; CHECK: stxsiwx [[REGCONV4]],
+}
+
+; Function Attrs: nounwind
+define void @uIntToDbl() #0 {
+entry:
+  %dd = alloca double, align 8
+  %0 = load i32, i32* @ui, align 4
+  %conv = uitofp i32 %0 to double
+  store volatile double %conv, double* %dd, align 8
+  ret void
+; CHECK-LABEL: @uIntToDbl
+; CHECK: lxsiwzx [[REGLD3:[0-9]+]],
+; CHECK: xscvuxddp {{[0-9]+}}, [[REGLD3]]
+}
+
+; Function Attrs: nounwind
+define void @uIntToFlt() #0 {
+entry:
+  %ff = alloca float, align 4
+  %0 = load i32, i32* @ui, align 4
+  %conv = uitofp i32 %0 to float
+  store volatile float %conv, float* %ff, align 4
+  ret void
+; CHECK-LABEL: @uIntToFlt
+; CHECK: lxsiwzx [[REGLD4:[0-9]+]],
+; FIXME: the below will change when the VSX form is implemented
+; CHECK: fcfidus {{[0-9]+}}, [[REGLD4]]
+}
+
+; Function Attrs: nounwind
+define void @dblToFloat() #0 {
+entry:
+  %ff = alloca float, align 4
+  %0 = load double, double* @d, align 8
+  %conv = fptrunc double %0 to float
+  store volatile float %conv, float* %ff, align 4
+  ret void
+; CHECK-LABEL: @dblToFloat
+; CHECK: lxsdx [[REGLD5:[0-9]+]],
+; CHECK: stxsspx [[REGLD5]],
+}
+
+; Function Attrs: nounwind
+define void @floatToDbl() #0 {
+entry:
+  %dd = alloca double, align 8
+  %0 = load float, float* @f, align 4
+  %conv = fpext float %0 to double
+  store volatile double %conv, double* %dd, align 8
+  ret void
+; CHECK-LABEL: @floatToDbl
+; CHECK: lxsspx [[REGLD5:[0-9]+]],
+; CHECK: stxsdx [[REGLD5]],
+}
diff --git a/test/CodeGen/PowerPC/vsx_shuffle_le.ll b/test/CodeGen/PowerPC/vsx_shuffle_le.ll
index 588cfdad7853..dcfa0e788867 100644
--- a/test/CodeGen/PowerPC/vsx_shuffle_le.ll
+++ b/test/CodeGen/PowerPC/vsx_shuffle_le.ll
@@ -1,207 +1,207 @@
 ; RUN: llc -mcpu=pwr8 -mattr=+vsx -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
 define <2 x double> @test00(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 0, i32 0>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: test00
 ; CHECK: lxvd2x 0, 0, 3
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 34, 0, 0, 3
+; CHECK: xxswapd 0, 0
+; CHECK: xxspltd 34, 0, 1
 }
 
 define <2 x double> @test01(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 0, i32 1>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: test01
 ; CHECK: lxvd2x 0, 0, 3
-; CHECK: xxpermdi 34, 0, 0, 2
+; CHECK: xxswapd 34, 0
 }
 
 define <2 x double> @test02(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 0, i32 2>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test02
 ; CHECK: lxvd2x 0, 0, 3
 ; CHECK: lxvd2x 1, 0, 4
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 1, 1, 1, 2
-; CHECK: xxpermdi 34, 1, 0, 3
+; CHECK: xxswapd 0, 0
+; CHECK: xxswapd 1, 1
+; CHECK: xxmrgld 34, 1, 0
 }
 
 define <2 x double> @test03(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 0, i32 3>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test03
 ; CHECK: lxvd2x 0, 0, 3
 ; CHECK: lxvd2x 1, 0, 4
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 1, 1, 1, 2
+; CHECK: xxswapd 0, 0
+; CHECK: xxswapd 1, 1
 ; CHECK: xxpermdi 34, 1, 0, 1
 }
 
 define <2 x double> @test10(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 1, i32 0>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test10
 ; CHECK: lxvd2x 0, 0, 3
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 34, 0, 0, 2
+; CHECK: xxswapd 0, 0
+; CHECK: xxswapd 34, 0
 }
 
 define <2 x double> @test11(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 1, i32 1>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test11
 ; CHECK: lxvd2x 0, 0, 3
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 34, 0, 0, 0
+; CHECK: xxswapd 0, 0
+; CHECK: xxspltd 34, 0, 0
 }
 
 define <2 x double> @test12(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 1, i32 2>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test12
 ; CHECK: lxvd2x 0, 0, 3
 ; CHECK: lxvd2x 1, 0, 4
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 1, 1, 1, 2
+; CHECK: xxswapd 0, 0
+; CHECK: xxswapd 1, 1
 ; CHECK: xxpermdi 34, 1, 0, 2
 }
 
 define <2 x double> @test13(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 1, i32 3>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test13
 ; CHECK: lxvd2x 0, 0, 3
 ; CHECK: lxvd2x 1, 0, 4
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 1, 1, 1, 2
-; CHECK: xxpermdi 34, 1, 0, 0
+; CHECK: xxswapd 0, 0
+; CHECK: xxswapd 1, 1
+; CHECK: xxmrghd 34, 1, 0
 }
 
 define <2 x double> @test20(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 2, i32 0>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test20
 ; CHECK: lxvd2x 0, 0, 3
 ; CHECK: lxvd2x 1, 0, 4
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 1, 1, 1, 2
-; CHECK: xxpermdi 34, 0, 1, 3
+; CHECK: xxswapd 0, 0
+; CHECK: xxswapd 1, 1
+; CHECK: xxmrgld 34, 0, 1
 }
 
 define <2 x double> @test21(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 2, i32 1>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test21
 ; CHECK: lxvd2x 0, 0, 3
 ; CHECK: lxvd2x 1, 0, 4
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 1, 1, 1, 2
+; CHECK: xxswapd 0, 0
+; CHECK: xxswapd 1, 1
 ; CHECK: xxpermdi 34, 0, 1, 1
 }
 
 define <2 x double> @test22(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 2, i32 2>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test22
 ; CHECK: lxvd2x 0, 0, 4
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 34, 0, 0, 3
+; CHECK: xxswapd 0, 0
+; CHECK: xxspltd 34, 0, 1
 }
 
 define <2 x double> @test23(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 2, i32 3>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test23
 ; CHECK: lxvd2x 0, 0, 4
-; CHECK: xxpermdi 34, 0, 0, 2
+; CHECK: xxswapd 34, 0
 }
 
 define <2 x double> @test30(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 3, i32 0>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test30
 ; CHECK: lxvd2x 0, 0, 3
 ; CHECK: lxvd2x 1, 0, 4
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 1, 1, 1, 2
+; CHECK: xxswapd 0, 0
+; CHECK: xxswapd 1, 1
 ; CHECK: xxpermdi 34, 0, 1, 2
 }
 
 define <2 x double> @test31(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 3, i32 1>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test31
 ; CHECK: lxvd2x 0, 0, 3
 ; CHECK: lxvd2x 1, 0, 4
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 1, 1, 1, 2
-; CHECK: xxpermdi 34, 0, 1, 0
+; CHECK: xxswapd 0, 0
+; CHECK: xxswapd 1, 1
+; CHECK: xxmrghd 34, 0, 1
 }
 
 define <2 x double> @test32(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 3, i32 2>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test32
 ; CHECK: lxvd2x 0, 0, 4
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 34, 0, 0, 2
+; CHECK: xxswapd 0, 0
+; CHECK: xxswapd 34, 0
 }
 
 define <2 x double> @test33(<2 x double>* %p1, <2 x double>* %p2) {
-  %v1 = load <2 x double>* %p1
-  %v2 = load <2 x double>* %p2
+  %v1 = load <2 x double>, <2 x double>* %p1
+  %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 3, i32 3>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test33
 ; CHECK: lxvd2x 0, 0, 4
-; CHECK: xxpermdi 0, 0, 0, 2
-; CHECK: xxpermdi 34, 0, 0, 0
+; CHECK: xxswapd 0, 0
+; CHECK: xxspltd 34, 0, 0
 }
diff --git a/test/CodeGen/PowerPC/weak_def_can_be_hidden.ll b/test/CodeGen/PowerPC/weak_def_can_be_hidden.ll
index e038b3f2fb25..0b87613bb4d8 100644
--- a/test/CodeGen/PowerPC/weak_def_can_be_hidden.ll
+++ b/test/CodeGen/PowerPC/weak_def_can_be_hidden.ll
@@ -11,7 +11,7 @@
 ; CHECK-D89: .weak_definition _v1
 
 define i32 @f1() {
-  %x = load i32 * @v1
+  %x = load i32 , i32 * @v1
   ret i32 %x
 }
 
@@ -45,6 +45,6 @@ define i32* @f3() {
 ; CHECK-D89: .weak_definition _v4
 
 define i32 @f4() {
-  %x = load i32 * @v4
+  %x = load i32 , i32 * @v4
   ret i32 %x
 }
diff --git a/test/CodeGen/PowerPC/xxleqv_xxlnand_xxlorc.ll b/test/CodeGen/PowerPC/xxleqv_xxlnand_xxlorc.ll
new file mode 100644
index 000000000000..4d929c627f1c
--- /dev/null
+++ b/test/CodeGen/PowerPC/xxleqv_xxlnand_xxlorc.ll
@@ -0,0 +1,52 @@
+; Check the miscellaneous logical vector operations added in P8
+; 
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; Test x eqv y
+define <4 x i32> @test_xxleqv(<4 x i32> %x, <4 x i32> %y) nounwind {
+       %tmp = xor <4 x i32> %x, %y
+       %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1>
+       ret <4 x i32> %ret_val
+; CHECK: xxleqv 34, 34, 35
+}
+
+; Test x xxlnand y
+define <4 x i32> @test_xxlnand(<4 x i32> %x, <4 x i32> %y) nounwind {
+       %tmp = and <4 x i32> %x, %y
+       %ret_val = xor <4 x i32> %tmp, <i32 -1, i32 -1, i32 -1, i32 -1>
+       ret <4 x i32> %ret_val
+; CHECK: xxlnand 34, 34, 35
+}
+
+; Test x xxlorc y
+define <4 x i32> @test_xxlorc(<4 x i32> %x, <4 x i32> %y) nounwind {
+       %tmp = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
+       %ret_val = or <4 x i32> %x, %tmp
+       ret <4 x i32> %ret_val
+; CHECK: xxlorc 34, 34, 35
+}
+
+; Test x eqv y
+define <8 x i16> @test_xxleqvv8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
+       %tmp = xor <8 x i16> %x, %y
+       %ret_val = xor <8 x i16> %tmp, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+       ret <8 x i16> %ret_val
+; CHECK: xxleqv 34, 34, 35
+}
+
+; Test x xxlnand y
+define <8 x i16> @test_xxlnandv8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
+       %tmp = and <8 x i16> %x, %y
+       %ret_val = xor <8 x i16> %tmp, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+       ret <8 x i16> %ret_val
+; CHECK: xxlnand 34, 34, 35
+}
+
+; Test x xxlorc y
+define <8 x i16> @test_xxlorcv8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
+       %tmp = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+       %ret_val = or <8 x i16> %x, %tmp
+       ret <8 x i16> %ret_val
+; CHECK: xxlorc 34, 34, 35
+}
+
diff --git a/test/CodeGen/PowerPC/zero-not-run.ll b/test/CodeGen/PowerPC/zero-not-run.ll
index 9df0d6e004ef..b3b7634f41a8 100644
--- a/test/CodeGen/PowerPC/zero-not-run.ll
+++ b/test/CodeGen/PowerPC/zero-not-run.ll
@@ -8,7 +8,7 @@ entry:
   br i1 undef, label %for.body, label %for.end731
 
 for.body:                                         ; preds = %entry
-  %0 = load i32* undef, align 4
+  %0 = load i32, i32* undef, align 4
   %or31 = or i32 %0, 319143828
   store i32 %or31, i32* undef, align 4
   %cmp32 = icmp eq i32 319143828, %or31
diff --git a/test/CodeGen/PowerPC/zext-free.ll b/test/CodeGen/PowerPC/zext-free.ll
index 080dbaa58da1..ffbbb5445019 100644
--- a/test/CodeGen/PowerPC/zext-free.ll
+++ b/test/CodeGen/PowerPC/zext-free.ll
@@ -5,22 +5,22 @@ target triple = "powerpc64-unknown-linux-gnu"
 ; Function Attrs: noreturn nounwind
 define signext i32 @_Z1fRPc(i8** nocapture dereferenceable(8) %p) #0 {
 entry:
-  %.pre = load i8** %p, align 8
+  %.pre = load i8*, i8** %p, align 8
   br label %loop
 
 loop:                                             ; preds = %loop.backedge, %entry
   %0 = phi i8* [ %.pre, %entry ], [ %.be, %loop.backedge ]
-  %1 = load i8* %0, align 1
+  %1 = load i8, i8* %0, align 1
   %tobool = icmp eq i8 %1, 0
-  %incdec.ptr = getelementptr inbounds i8* %0, i64 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %0, i64 1
   store i8* %incdec.ptr, i8** %p, align 8
-  %2 = load i8* %incdec.ptr, align 1
+  %2 = load i8, i8* %incdec.ptr, align 1
   %tobool2 = icmp ne i8 %2, 0
   %or.cond = and i1 %tobool, %tobool2
   br i1 %or.cond, label %if.then3, label %loop.backedge
 
 if.then3:                                         ; preds = %loop
-  %incdec.ptr4 = getelementptr inbounds i8* %0, i64 2
+  %incdec.ptr4 = getelementptr inbounds i8, i8* %0, i64 2
   store i8* %incdec.ptr4, i8** %p, align 8
   br label %loop.backedge
 
diff --git a/test/CodeGen/R600/128bit-kernel-args.ll b/test/CodeGen/R600/128bit-kernel-args.ll
deleted file mode 100644
index 557d86aa8376..000000000000
--- a/test/CodeGen/R600/128bit-kernel-args.ll
+++ /dev/null
@@ -1,29 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI
-
-; R600: {{^}}v4i32_kernel_arg:
-; R600-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y
-; R600-DAG: MOV {{[* ]*}}T[[GPR]].Y, KC0[3].Z
-; R600-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W
-; R600-DAG: MOV {{[* ]*}}T[[GPR]].W, KC0[4].X
-; SI: {{^}}v4i32_kernel_arg:
-; SI: buffer_store_dwordx4
-define void @v4i32_kernel_arg(<4 x i32> addrspace(1)* %out, <4 x i32>  %in) {
-entry:
-  store <4 x i32> %in, <4 x i32> addrspace(1)* %out
-  ret void
-}
-
-; R600: {{^}}v4f32_kernel_arg:
-; R600-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y
-; R600-DAG: MOV {{[* ]*}}T[[GPR]].Y, KC0[3].Z
-; R600-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W
-; R600-DAG: MOV {{[* ]*}}T[[GPR]].W, KC0[4].X
-; SI: {{^}}v4f32_kernel_arg:
-; SI: buffer_store_dwordx4
-define void @v4f32_kernel_arg(<4 x float> addrspace(1)* %out, <4 x float>  %in) {
-entry:
-  store <4 x float> %in, <4 x float> addrspace(1)* %out
-  ret void
-}
diff --git a/test/CodeGen/R600/32-bit-local-address-space.ll b/test/CodeGen/R600/32-bit-local-address-space.ll
index 71940fd88f26..c7bcfd2ddab2 100644
--- a/test/CodeGen/R600/32-bit-local-address-space.ll
+++ b/test/CodeGen/R600/32-bit-local-address-space.ll
@@ -15,7 +15,7 @@
 ; SI: ds_read_b32 v{{[0-9]+}}, [[PTR]]
 define void @local_address_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
 entry:
-  %0 = load i32 addrspace(3)* %in
+  %0 = load i32, i32 addrspace(3)* %in
   store i32 %0, i32 addrspace(1)* %out
   ret void
 }
@@ -26,8 +26,8 @@ entry:
 ; SI: ds_read_b32 [[VPTR]]
 define void @local_address_gep(i32 addrspace(1)* %out, i32 addrspace(3)* %in, i32 %offset) {
 entry:
-  %0 = getelementptr i32 addrspace(3)* %in, i32 %offset
-  %1 = load i32 addrspace(3)* %0
+  %0 = getelementptr i32, i32 addrspace(3)* %in, i32 %offset
+  %1 = load i32, i32 addrspace(3)* %0
   store i32 %1, i32 addrspace(1)* %out
   ret void
 }
@@ -37,8 +37,8 @@ entry:
 ; SI: ds_read_b32 v{{[0-9]+}}, [[VPTR]] offset:4
 define void @local_address_gep_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
 entry:
-  %0 = getelementptr i32 addrspace(3)* %in, i32 1
-  %1 = load i32 addrspace(3)* %0
+  %0 = getelementptr i32, i32 addrspace(3)* %in, i32 1
+  %1 = load i32, i32 addrspace(3)* %0
   store i32 %1, i32 addrspace(1)* %out
   ret void
 }
@@ -50,8 +50,8 @@ entry:
 ; SI: ds_read_b32 [[VPTR]]
 define void @local_address_gep_large_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
 entry:
-  %0 = getelementptr i32 addrspace(3)* %in, i32 16385
-  %1 = load i32 addrspace(3)* %0
+  %0 = getelementptr i32, i32 addrspace(3)* %in, i32 16385
+  %1 = load i32, i32 addrspace(3)* %0
   store i32 %1, i32 addrspace(1)* %out
   ret void
 }
@@ -72,8 +72,8 @@ define void @null_32bit_lds_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %lds)
 ; SI-NEXT: s_add_i32
 ; SI: ds_read_b32
 define void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] addrspace(3)* %lds, i32 %tid) {
-  %ptr = getelementptr [3 x float] addrspace(3)* %lds, i32 %tid, i32 0
-  %val = load float addrspace(3)* %ptr
+  %ptr = getelementptr [3 x float], [3 x float] addrspace(3)* %lds, i32 %tid, i32 0
+  %val = load float, float addrspace(3)* %ptr
   store float %val, float addrspace(1)* %out
   ret void
 }
@@ -84,7 +84,7 @@ define void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] addrspace(3)* %
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
 ; SI: ds_read_b32 v{{[0-9]+}}, [[REG]]
 define void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %tid) {
-  %val = load float addrspace(3)* @g_lds
+  %val = load float, float addrspace(3)* @g_lds
   store float %val, float addrspace(1)* %out
   ret void
 }
@@ -96,7 +96,7 @@ define void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %ti
 ; FUNC-LABEL: {{^}}global_ptr:
 ; SI: ds_write_b32
 define void @global_ptr() nounwind {
-  store i32 addrspace(3)* getelementptr ([16384 x i32] addrspace(3)* @dst, i32 0, i32 16), i32 addrspace(3)* addrspace(3)* @ptr
+  store i32 addrspace(3)* getelementptr ([16384 x i32], [16384 x i32] addrspace(3)* @dst, i32 0, i32 16), i32 addrspace(3)* addrspace(3)* @ptr
   ret void
 }
 
@@ -112,7 +112,7 @@ define void @local_address_store(i32 addrspace(3)* %out, i32 %val) {
 ; SI: v_mov_b32_e32 [[ADDR:v[0-9]+]], [[SADDR]]
 ; SI: ds_write_b32 [[ADDR]], v{{[0-9]+}}
 define void @local_address_gep_store(i32 addrspace(3)* %out, i32, i32 %val, i32 %offset) {
-  %gep = getelementptr i32 addrspace(3)* %out, i32 %offset
+  %gep = getelementptr i32, i32 addrspace(3)* %out, i32 %offset
   store i32 %val, i32 addrspace(3)* %gep, align 4
   ret void
 }
@@ -122,7 +122,7 @@ define void @local_address_gep_store(i32 addrspace(3)* %out, i32, i32 %val, i32
 ; SI: v_mov_b32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
 ; SI: ds_write_b32 [[VPTR]], [[VAL]] offset:4
 define void @local_address_gep_const_offset_store(i32 addrspace(3)* %out, i32 %val) {
-  %gep = getelementptr i32 addrspace(3)* %out, i32 1
+  %gep = getelementptr i32, i32 addrspace(3)* %out, i32 1
   store i32 %val, i32 addrspace(3)* %gep, align 4
   ret void
 }
@@ -131,9 +131,9 @@ define void @local_address_gep_const_offset_store(i32 addrspace(3)* %out, i32 %v
 ; FUNC-LABEL: {{^}}local_address_gep_large_const_offset_store:
 ; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
-; SI: ds_write_b32 [[VPTR]], v{{[0-9]+}} [M0]{{$}}
+; SI: ds_write_b32 [[VPTR]], v{{[0-9]+$}}
 define void @local_address_gep_large_const_offset_store(i32 addrspace(3)* %out, i32 %val) {
-  %gep = getelementptr i32 addrspace(3)* %out, i32 16385
+  %gep = getelementptr i32, i32 addrspace(3)* %out, i32 16385
   store i32 %val, i32 addrspace(3)* %gep, align 4
   ret void
 }
diff --git a/test/CodeGen/R600/64bit-kernel-args.ll b/test/CodeGen/R600/64bit-kernel-args.ll
deleted file mode 100644
index 9f2738edb6eb..000000000000
--- a/test/CodeGen/R600/64bit-kernel-args.ll
+++ /dev/null
@@ -1,11 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s --check-prefix=SI
-
-; SI: {{^}}f64_kernel_arg:
-; SI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x9
-; SI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0xb
-; SI: buffer_store_dwordx2
-define void @f64_kernel_arg(double addrspace(1)* %out, double  %in) {
-entry:
-  store double %in, double addrspace(1)* %out
-  ret void
-}
diff --git a/test/CodeGen/R600/add-debug.ll b/test/CodeGen/R600/add-debug.ll
index a83c689eb182..529905dd36a2 100644
--- a/test/CodeGen/R600/add-debug.ll
+++ b/test/CodeGen/R600/add-debug.ll
@@ -9,7 +9,7 @@ entry:
   br i1 %0, label %if, label %else
 
 if:
-  %1 = load i64 addrspace(1)* %in
+  %1 = load i64, i64 addrspace(1)* %in
   br label %endif
 
 else:
diff --git a/test/CodeGen/R600/add.ll b/test/CodeGen/R600/add.ll
index 3a8b97cd87e8..655e75dbc1a4 100644
--- a/test/CodeGen/R600/add.ll
+++ b/test/CodeGen/R600/add.ll
@@ -9,9 +9,9 @@
 ;SI-NOT: [[REG]]
 ;SI: buffer_store_dword [[REG]],
 define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %a = load i32 addrspace(1)* %in
-  %b = load i32 addrspace(1)* %b_ptr
+  %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %a = load i32, i32 addrspace(1)* %in
+  %b = load i32, i32 addrspace(1)* %b_ptr
   %result = add i32 %a, %b
   store i32 %result, i32 addrspace(1)* %out
   ret void
@@ -25,9 +25,9 @@ define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 ;SI: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 
 define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
-  %a = load <2 x i32> addrspace(1)* %in
-  %b = load <2 x i32> addrspace(1)* %b_ptr
+  %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32>, <2 x i32> addrspace(1)* %in
+  %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
   %result = add <2 x i32> %a, %b
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
   ret void
@@ -45,9 +45,9 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
 ;SI: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 
 define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
-  %a = load <4 x i32> addrspace(1)* %in
-  %b = load <4 x i32> addrspace(1)* %b_ptr
+  %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
+  %a = load <4 x i32>, <4 x i32> addrspace(1)* %in
+  %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
   %result = add <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
@@ -62,6 +62,7 @@ define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
 ; EG: ADD_INT
 ; EG: ADD_INT
 ; EG: ADD_INT
+
 ; SI: s_add_i32
 ; SI: s_add_i32
 ; SI: s_add_i32
@@ -94,6 +95,7 @@ entry:
 ; EG: ADD_INT
 ; EG: ADD_INT
 ; EG: ADD_INT
+
 ; SI: s_add_i32
 ; SI: s_add_i32
 ; SI: s_add_i32
@@ -120,6 +122,14 @@ entry:
 ; FUNC-LABEL: {{^}}add64:
 ; SI: s_add_u32
 ; SI: s_addc_u32
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
+; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
+; EG-DAG: ADD_INT {{[* ]*}}[[LO]]
+; EG-DAG: ADDC_UINT
+; EG-DAG: ADD_INT
+; EG-DAG: ADD_INT {{[* ]*}}[[HI]]
+; EG-NOT: SUB
 define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
 entry:
   %0 = add i64 %a, %b
@@ -134,9 +144,17 @@ entry:
 
 ; FUNC-LABEL: {{^}}add64_sgpr_vgpr:
 ; SI-NOT: v_addc_u32_e32 s
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
+; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
+; EG-DAG: ADD_INT {{[* ]*}}[[LO]]
+; EG-DAG: ADDC_UINT
+; EG-DAG: ADD_INT
+; EG-DAG: ADD_INT {{[* ]*}}[[HI]]
+; EG-NOT: SUB
 define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) {
 entry:
-  %0 = load i64 addrspace(1)* %in
+  %0 = load i64, i64 addrspace(1)* %in
   %1 = add i64 %a, %0
   store i64 %1, i64 addrspace(1)* %out
   ret void
@@ -146,13 +164,21 @@ entry:
 ; FUNC-LABEL: {{^}}add64_in_branch:
 ; SI: s_add_u32
 ; SI: s_addc_u32
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
+; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
+; EG-DAG: ADD_INT {{[* ]*}}[[LO]]
+; EG-DAG: ADDC_UINT
+; EG-DAG: ADD_INT
+; EG-DAG: ADD_INT {{[* ]*}}[[HI]]
+; EG-NOT: SUB
 define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
 entry:
   %0 = icmp eq i64 %a, 0
   br i1 %0, label %if, label %else
 
 if:
-  %1 = load i64 addrspace(1)* %in
+  %1 = load i64, i64 addrspace(1)* %in
   br label %endif
 
 else:
diff --git a/test/CodeGen/R600/add_i64.ll b/test/CodeGen/R600/add_i64.ll
index 1769409f5ef1..8346add7df97 100644
--- a/test/CodeGen/R600/add_i64.ll
+++ b/test/CodeGen/R600/add_i64.ll
@@ -8,10 +8,10 @@ declare i32 @llvm.r600.read.tidig.x() readnone
 ; SI: v_addc_u32
 define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) {
   %tid = call i32 @llvm.r600.read.tidig.x() readnone
-  %a_ptr = getelementptr i64 addrspace(1)* %inA, i32 %tid
-  %b_ptr = getelementptr i64 addrspace(1)* %inB, i32 %tid
-  %a = load i64 addrspace(1)* %a_ptr
-  %b = load i64 addrspace(1)* %b_ptr
+  %a_ptr = getelementptr i64, i64 addrspace(1)* %inA, i32 %tid
+  %b_ptr = getelementptr i64, i64 addrspace(1)* %inB, i32 %tid
+  %a = load i64, i64 addrspace(1)* %a_ptr
+  %b = load i64, i64 addrspace(1)* %b_ptr
   %result = add i64 %a, %b
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -22,7 +22,7 @@ define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noa
 ; SI: v_add_i32
 ; SI: v_addc_u32
 define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) {
-  %foo = load i64 addrspace(1)* %in, align 8
+  %foo = load i64, i64 addrspace(1)* %in, align 8
   %result = add i64 %foo, %a
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -35,7 +35,7 @@ define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noal
 ; SI: v_add_i32
 ; SI: v_addc_u32
 define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) {
-  %foo = load i64 addrspace(1)* %in, align 8
+  %foo = load i64, i64 addrspace(1)* %in, align 8
   %result = add i64 %a, %foo
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -60,10 +60,10 @@ define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a,
 ; SI: v_addc_u32
 define void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) {
   %tid = call i32 @llvm.r600.read.tidig.x() readnone
-  %a_ptr = getelementptr <2 x i64> addrspace(1)* %inA, i32 %tid
-  %b_ptr = getelementptr <2 x i64> addrspace(1)* %inB, i32 %tid
-  %a = load <2 x i64> addrspace(1)* %a_ptr
-  %b = load <2 x i64> addrspace(1)* %b_ptr
+  %a_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %inA, i32 %tid
+  %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %inB, i32 %tid
+  %a = load <2 x i64>, <2 x i64> addrspace(1)* %a_ptr
+  %b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr
   %result = add <2 x i64> %a, %b
   store <2 x i64> %result, <2 x i64> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/address-space.ll b/test/CodeGen/R600/address-space.ll
index aaa0628ccdc9..4be8c5847529 100644
--- a/test/CodeGen/R600/address-space.ll
+++ b/test/CodeGen/R600/address-space.ll
@@ -10,18 +10,19 @@
 
 ; CHECK-LABEL: {{^}}do_as_ptr_calcs:
 ; CHECK: s_load_dword [[SREG1:s[0-9]+]],
+; CHECK: v_mov_b32_e32 [[VREG2:v[0-9]+]], [[SREG1]]
 ; CHECK: v_mov_b32_e32 [[VREG1:v[0-9]+]], [[SREG1]]
 ; CHECK-DAG: ds_read_b32 v{{[0-9]+}}, [[VREG1]] offset:12
-; CHECK-DAG: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:20
+; CHECK-DAG: ds_read_b32 v{{[0-9]+}}, [[VREG2]] offset:20
 define void @do_as_ptr_calcs(%struct.foo addrspace(3)* nocapture %ptr) nounwind {
 entry:
-  %x = getelementptr inbounds %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 0
-  %y = getelementptr inbounds %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 2
+  %x = getelementptr inbounds %struct.foo, %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 0
+  %y = getelementptr inbounds %struct.foo, %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 2
   br label %bb32
 
 bb32:
-  %a = load float addrspace(3)* %x, align 4
-  %b = load float addrspace(3)* %y, align 4
+  %a = load float, float addrspace(3)* %x, align 4
+  %b = load float, float addrspace(3)* %y, align 4
   %cmp = fcmp one float %a, %b
   br i1 %cmp, label %bb34, label %bb33
 
diff --git a/test/CodeGen/R600/and.ll b/test/CodeGen/R600/and.ll
index 7a395ccb38d0..5672d470bd7e 100644
--- a/test/CodeGen/R600/and.ll
+++ b/test/CodeGen/R600/and.ll
@@ -10,9 +10,9 @@
 ; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 
 define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
-  %a = load <2 x i32> addrspace(1) * %in
-  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32>, <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
   %result = and <2 x i32> %a, %b
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
   ret void
@@ -30,9 +30,9 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
 ; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 
 define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
-  %a = load <4 x i32> addrspace(1) * %in
-  %b = load <4 x i32> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
+  %a = load <4 x i32>, <4 x i32> addrspace(1) * %in
+  %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
   %result = and <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
@@ -57,23 +57,41 @@ define void @s_and_constant_i32(i32 addrspace(1)* %out, i32 %a) {
 ; FUNC-LABEL: {{^}}v_and_i32:
 ; SI: v_and_b32
 define void @v_and_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) {
-  %a = load i32 addrspace(1)* %aptr, align 4
-  %b = load i32 addrspace(1)* %bptr, align 4
+  %a = load i32, i32 addrspace(1)* %aptr, align 4
+  %b = load i32, i32 addrspace(1)* %bptr, align 4
   %and = and i32 %a, %b
   store i32 %and, i32 addrspace(1)* %out, align 4
   ret void
 }
 
-; FUNC-LABEL: {{^}}v_and_constant_i32:
-; SI: v_and_b32
+; FUNC-LABEL: {{^}}v_and_constant_i32
+; SI: v_and_b32_e32 v{{[0-9]+}}, 0x12d687, v{{[0-9]+}}
 define void @v_and_constant_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
-  %a = load i32 addrspace(1)* %aptr, align 4
+  %a = load i32, i32 addrspace(1)* %aptr, align 4
   %and = and i32 %a, 1234567
   store i32 %and, i32 addrspace(1)* %out, align 4
   ret void
 }
 
-; FUNC-LABEL: {{^}}s_and_i64:
+; FUNC-LABEL: {{^}}v_and_inline_imm_64_i32
+; SI: v_and_b32_e32 v{{[0-9]+}}, 64, v{{[0-9]+}}
+define void @v_and_inline_imm_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
+  %a = load i32, i32 addrspace(1)* %aptr, align 4
+  %and = and i32 %a, 64
+  store i32 %and, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+; FUNC-LABEL: {{^}}v_and_inline_imm_neg_16_i32
+; SI: v_and_b32_e32 v{{[0-9]+}}, -16, v{{[0-9]+}}
+define void @v_and_inline_imm_neg_16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
+  %a = load i32, i32 addrspace(1)* %aptr, align 4
+  %and = and i32 %a, -16
+  store i32 %and, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+; FUNC-LABEL: {{^}}s_and_i64
 ; SI: s_and_b64
 define void @s_and_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
   %and = and i64 %a, %b
@@ -90,8 +108,8 @@ define void @s_and_i1(i1 addrspace(1)* %out, i1 %a, i1 %b) {
   ret void
 }
 
-; FUNC-LABEL: {{^}}s_and_constant_i64:
-; SI: s_and_b64
+; FUNC-LABEL: {{^}}s_and_constant_i64
+; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}
 define void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) {
   %and = and i64 %a, 281474976710655
   store i64 %and, i64 addrspace(1)* %out, align 8
@@ -102,8 +120,8 @@ define void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) {
 ; SI: v_and_b32
 ; SI: v_and_b32
 define void @v_and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) {
-  %a = load i64 addrspace(1)* %aptr, align 8
-  %b = load i64 addrspace(1)* %bptr, align 8
+  %a = load i64, i64 addrspace(1)* %aptr, align 8
+  %b = load i64, i64 addrspace(1)* %bptr, align 8
   %and = and i64 %a, %b
   store i64 %and, i64 addrspace(1)* %out, align 8
   ret void
@@ -118,8 +136,8 @@ entry:
   br i1 %tmp0, label %if, label %endif
 
 if:
-  %a = load i64 addrspace(1)* %aptr, align 8
-  %b = load i64 addrspace(1)* %bptr, align 8
+  %a = load i64, i64 addrspace(1)* %aptr, align 8
+  %b = load i64, i64 addrspace(1)* %bptr, align 8
   %and = and i64 %a, %b
   br label %endif
 
@@ -133,7 +151,7 @@ endif:
 ; SI: v_and_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
 ; SI: v_and_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
 define void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
-  %a = load i64 addrspace(1)* %aptr, align 8
+  %a = load i64, i64 addrspace(1)* %aptr, align 8
   %and = and i64 %a, 1234567
   store i64 %and, i64 addrspace(1)* %out, align 8
   ret void
@@ -144,16 +162,135 @@ define void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr)
 ; SI: v_and_b32_e32 {{v[0-9]+}}, 64, {{v[0-9]+}}
 ; SI: v_and_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}}
 define void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
-  %a = load i64 addrspace(1)* %aptr, align 8
+  %a = load i64, i64 addrspace(1)* %aptr, align 8
   %and = and i64 %a, 64
   store i64 %and, i64 addrspace(1)* %out, align 8
   ret void
 }
 
-; FUNC-LABEL: {{^}}s_and_inline_imm_i64:
+; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64
 ; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 64
-define void @s_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
+define void @s_and_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
   %and = and i64 %a, 64
   store i64 %and, i64 addrspace(1)* %out, align 8
   ret void
 }
+
+; FUNC-LABEL: {{^}}s_and_inline_imm_1_i64
+; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1
+define void @s_and_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
+  %and = and i64 %a, 1
+  store i64 %and, i64 addrspace(1)* %out, align 8
+  ret void
+}
+
+; FUNC-LABEL: {{^}}s_and_inline_imm_1.0_i64
+; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0
+define void @s_and_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
+  %and = and i64 %a, 4607182418800017408
+  store i64 %and, i64 addrspace(1)* %out, align 8
+  ret void
+}
+
+; FUNC-LABEL: {{^}}s_and_inline_imm_neg_1.0_i64
+; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0
+define void @s_and_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
+  %and = and i64 %a, 13830554455654793216
+  store i64 %and, i64 addrspace(1)* %out, align 8
+  ret void
+}
+
+; FUNC-LABEL: {{^}}s_and_inline_imm_0.5_i64
+; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5
+define void @s_and_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
+  %and = and i64 %a, 4602678819172646912
+  store i64 %and, i64 addrspace(1)* %out, align 8
+  ret void
+}
+
+; FUNC-LABEL: {{^}}s_and_inline_imm_neg_0.5_i64
+; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5
+define void @s_and_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
+  %and = and i64 %a, 13826050856027422720
+  store i64 %and, i64 addrspace(1)* %out, align 8
+  ret void
+}
+
+; FUNC-LABEL: {{^}}s_and_inline_imm_2.0_i64
+; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 2.0
+define void @s_and_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
+  %and = and i64 %a, 4611686018427387904
+  store i64 %and, i64 addrspace(1)* %out, align 8
+  ret void
+}
+
+; FUNC-LABEL: {{^}}s_and_inline_imm_neg_2.0_i64
+; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -2.0
+define void @s_and_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
+  %and = and i64 %a, 13835058055282163712
+  store i64 %and, i64 addrspace(1)* %out, align 8
+  ret void
+}
+
+; FUNC-LABEL: {{^}}s_and_inline_imm_4.0_i64
+; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0
+define void @s_and_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
+  %and = and i64 %a, 4616189618054758400
+  store i64 %and, i64 addrspace(1)* %out, align 8
+  ret void
+}
+
+; FUNC-LABEL: {{^}}s_and_inline_imm_neg_4.0_i64
+; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0
+define void @s_and_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
+  %and = and i64 %a, 13839561654909534208
+  store i64 %and, i64 addrspace(1)* %out, align 8
+  ret void
+}
+
+
+; Test with the 64-bit integer bitpattern for a 32-bit float in the
+; low 32-bits, which is not a valid 64-bit inline immmediate.
+
+; FUNC-LABEL: {{^}}s_and_inline_imm_f32_4.0_i64
+; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 4.0
+; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0{{$}}
+; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
+define void @s_and_inline_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
+  %and = and i64 %a, 1082130432
+  store i64 %and, i64 addrspace(1)* %out, align 8
+  ret void
+}
+
+; FIXME: Copy of -1 register
+; FUNC-LABEL: {{^}}s_and_inline_imm_f32_neg_4.0_i64
+; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], -4.0
+; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -1{{$}}
+; SI-DAG: s_mov_b32 s[[K_HI_COPY:[0-9]+]], s[[K_HI]]
+; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI_COPY]]{{\]}}
+define void @s_and_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
+  %and = and i64 %a, -1065353216
+  store i64 %and, i64 addrspace(1)* %out, align 8
+  ret void
+}
+
+; Shift into upper 32-bits
+; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_4.0_i64
+; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 4.0
+; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}
+; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
+define void @s_and_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
+  %and = and i64 %a, 4647714815446351872
+  store i64 %and, i64 addrspace(1)* %out, align 8
+  ret void
+}
+
+; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_neg_4.0_i64
+; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -4.0
+; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}
+; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
+define void @s_and_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
+  %and = and i64 %a, 13871086852301127680
+  store i64 %and, i64 addrspace(1)* %out, align 8
+  ret void
+}
diff --git a/test/CodeGen/R600/array-ptr-calc-i32.ll b/test/CodeGen/R600/array-ptr-calc-i32.ll
index 33a8aee0164d..8c2a0795860d 100644
--- a/test/CodeGen/R600/array-ptr-calc-i32.ll
+++ b/test/CodeGen/R600/array-ptr-calc-i32.ll
@@ -20,24 +20,24 @@ declare void @llvm.AMDGPU.barrier.local() nounwind noduplicate
 ; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this
 ; alloca to a vector.  It currently fails because it does not know how
 ; to interpret:
-; getelementptr [4 x i32]* %alloca, i32 1, i32 %b
+; getelementptr [4 x i32], [4 x i32]* %alloca, i32 1, i32 %b
 
 ; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], 16
 ; SI-PROMOTE: ds_write_b32 [[PTRREG]]
 define void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) {
   %alloca = alloca [4 x i32], i32 4, align 16
   %tid = call i32 @llvm.SI.tid() readnone
-  %a_ptr = getelementptr i32 addrspace(1)* %inA, i32 %tid
-  %b_ptr = getelementptr i32 addrspace(1)* %inB, i32 %tid
-  %a = load i32 addrspace(1)* %a_ptr
-  %b = load i32 addrspace(1)* %b_ptr
+  %a_ptr = getelementptr i32, i32 addrspace(1)* %inA, i32 %tid
+  %b_ptr = getelementptr i32, i32 addrspace(1)* %inB, i32 %tid
+  %a = load i32, i32 addrspace(1)* %a_ptr
+  %b = load i32, i32 addrspace(1)* %b_ptr
   %result = add i32 %a, %b
-  %alloca_ptr = getelementptr [4 x i32]* %alloca, i32 1, i32 %b
+  %alloca_ptr = getelementptr [4 x i32], [4 x i32]* %alloca, i32 1, i32 %b
   store i32 %result, i32* %alloca_ptr, align 4
   ; Dummy call
   call void @llvm.AMDGPU.barrier.local() nounwind noduplicate
-  %reload = load i32* %alloca_ptr, align 4
-  %out_ptr = getelementptr i32 addrspace(1)* %out, i32 %tid
+  %reload = load i32, i32* %alloca_ptr, align 4
+  %out_ptr = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
   store i32 %reload, i32 addrspace(1)* %out_ptr, align 4
   ret void
 }
diff --git a/test/CodeGen/R600/array-ptr-calc-i64.ll b/test/CodeGen/R600/array-ptr-calc-i64.ll
index 32e657db7bc6..eae095eb8449 100644
--- a/test/CodeGen/R600/array-ptr-calc-i64.ll
+++ b/test/CodeGen/R600/array-ptr-calc-i64.ll
@@ -7,10 +7,10 @@ declare i32 @llvm.SI.tid() readnone
 ; SI: v_mul_hi_i32
 define void @test_array_ptr_calc(i32 addrspace(1)* noalias %out, [1025 x i32] addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) {
   %tid = call i32 @llvm.SI.tid() readnone
-  %a_ptr = getelementptr [1025 x i32] addrspace(1)* %inA, i32 %tid, i32 0
-  %b_ptr = getelementptr i32 addrspace(1)* %inB, i32 %tid
-  %a = load i32 addrspace(1)* %a_ptr
-  %b = load i32 addrspace(1)* %b_ptr
+  %a_ptr = getelementptr [1025 x i32], [1025 x i32] addrspace(1)* %inA, i32 %tid, i32 0
+  %b_ptr = getelementptr i32, i32 addrspace(1)* %inB, i32 %tid
+  %a = load i32, i32 addrspace(1)* %a_ptr
+  %b = load i32, i32 addrspace(1)* %b_ptr
   %result = add i32 %a, %b
   store i32 %result, i32 addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/atomic_cmp_swap_local.ll b/test/CodeGen/R600/atomic_cmp_swap_local.ll
index 0d5ece4b0e0b..ef2560ef1849 100644
--- a/test/CodeGen/R600/atomic_cmp_swap_local.ll
+++ b/test/CodeGen/R600/atomic_cmp_swap_local.ll
@@ -1,16 +1,19 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=CI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SICI -check-prefix=GCN -check-prefix=FUNC  %s
+; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=SICI -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s
 
 ; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_offset:
-; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; SI-DAG: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
-; SI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
-; SI-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
-; SI: ds_cmpst_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]] offset:16 [M0]
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
+; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
+; SICI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
+; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; VI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
+; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
+; GCN-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
+; GCN: ds_cmpst_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]] offset:16
+; GCN: s_endpgm
 define void @lds_atomic_cmpxchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %swap) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic
   %result = extractvalue { i32, i1 } %pair, 0
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -18,18 +21,20 @@ define void @lds_atomic_cmpxchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrs
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i64_offset:
-; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
-; SI-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
-; SI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
-; SI-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
-; SI-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
-; SI: ds_cmpst_rtn_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32 [M0]
-; SI: buffer_store_dwordx2 [[RESULT]],
-; SI: s_endpgm
+; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
+; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
+; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
+; SICI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
+; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; VI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
+; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
+; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
+; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
+; GCN: ds_cmpst_rtn_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32
+; GCN: buffer_store_dwordx2 [[RESULT]],
+; GCN: s_endpgm
 define void @lds_atomic_cmpxchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr, i64 %swap) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic
   %result = extractvalue { i64, i1 } %pair, 0
   store i64 %result, i64 addrspace(1)* %out, align 8
@@ -38,12 +43,12 @@ define void @lds_atomic_cmpxchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrs
 
 ; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_bad_si_offset
 ; SI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
-; CI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 [M0]
-; SI: s_endpgm
+; CIVI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_cmpxchg_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %swap, i32 %a, i32 %b) nounwind {
   %sub = sub i32 %a, %b
   %add = add i32 %sub, 4
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 %add
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 %add
   %pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic
   %result = extractvalue { i32, i1 } %pair, 0
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -51,32 +56,36 @@ define void @lds_atomic_cmpxchg_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i3
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_noret_i32_offset:
-; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
-; SI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xa
-; SI-DAG: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
-; SI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
-; SI-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
-; SI: ds_cmpst_b32 [[VPTR]], [[VCMP]], [[VSWAP]] offset:16 [M0]
-; SI: s_endpgm
+; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
+; SICI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xa
+; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
+; VI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x28
+; GCN-DAG: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
+; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
+; GCN-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
+; GCN: ds_cmpst_b32 [[VPTR]], [[VCMP]], [[VSWAP]] offset:16
+; GCN: s_endpgm
 define void @lds_atomic_cmpxchg_noret_i32_offset(i32 addrspace(3)* %ptr, i32 %swap) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic
   %result = extractvalue { i32, i1 } %pair, 0
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_noret_i64_offset:
-; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
-; SI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
-; SI-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
-; SI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
-; SI-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
-; SI-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
-; SI: ds_cmpst_b64 [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32 [M0]
-; SI: s_endpgm
+; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
+; SICI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
+; VI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
+; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
+; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
+; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
+; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
+; GCN: ds_cmpst_b64 [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_cmpxchg_noret_i64_offset(i64 addrspace(3)* %ptr, i64 %swap) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic
   %result = extractvalue { i64, i1 } %pair, 0
   ret void
diff --git a/test/CodeGen/R600/atomic_load_add.ll b/test/CodeGen/R600/atomic_load_add.ll
index 5fe05f2996af..20c685447eef 100644
--- a/test/CodeGen/R600/atomic_load_add.ll
+++ b/test/CodeGen/R600/atomic_load_add.ll
@@ -14,7 +14,7 @@ define void @atomic_add_local(i32 addrspace(3)* %local) {
 ; R600: LDS_ADD *
 ; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
 define void @atomic_add_local_const_offset(i32 addrspace(3)* %local) {
-  %gep = getelementptr i32 addrspace(3)* %local, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %local, i32 4
   %val = atomicrmw volatile add i32 addrspace(3)* %gep, i32 5 seq_cst
   ret void
 }
@@ -32,7 +32,7 @@ define void @atomic_add_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %loc
 ; R600: LDS_ADD_RET *
 ; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:20
 define void @atomic_add_ret_local_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %local) {
-  %gep = getelementptr i32 addrspace(3)* %local, i32 5
+  %gep = getelementptr i32, i32 addrspace(3)* %local, i32 5
   %val = atomicrmw volatile add i32 addrspace(3)* %gep, i32 5 seq_cst
   store i32 %val, i32 addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/atomic_load_sub.ll b/test/CodeGen/R600/atomic_load_sub.ll
index 40722833d265..4c6f45525b9e 100644
--- a/test/CodeGen/R600/atomic_load_sub.ll
+++ b/test/CodeGen/R600/atomic_load_sub.ll
@@ -14,7 +14,7 @@ define void @atomic_sub_local(i32 addrspace(3)* %local) {
 ; R600: LDS_SUB *
 ; SI: ds_sub_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
 define void @atomic_sub_local_const_offset(i32 addrspace(3)* %local) {
-  %gep = getelementptr i32 addrspace(3)* %local, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %local, i32 4
   %val = atomicrmw volatile sub i32 addrspace(3)* %gep, i32 5 seq_cst
   ret void
 }
@@ -32,7 +32,7 @@ define void @atomic_sub_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %loc
 ; R600: LDS_SUB_RET *
 ; SI: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:20
 define void @atomic_sub_ret_local_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %local) {
-  %gep = getelementptr i32 addrspace(3)* %local, i32 5
+  %gep = getelementptr i32, i32 addrspace(3)* %local, i32 5
   %val = atomicrmw volatile sub i32 addrspace(3)* %gep, i32 5 seq_cst
   store i32 %val, i32 addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/bfe_uint.ll b/test/CodeGen/R600/bfe_uint.ll
index 6fe23e912952..32e3fc26106f 100644
--- a/test/CodeGen/R600/bfe_uint.ll
+++ b/test/CodeGen/R600/bfe_uint.ll
@@ -1,7 +1,5 @@
 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-; XFAIL: *
-
 ; CHECK: {{^}}bfe_def:
 ; CHECK: BFE_UINT
 define void @bfe_def(i32 addrspace(1)* %out, i32 %x) {
diff --git a/test/CodeGen/R600/big_alu.ll b/test/CodeGen/R600/big_alu.ll
index 28be216e76f2..2671c5d102b3 100644
--- a/test/CodeGen/R600/big_alu.ll
+++ b/test/CodeGen/R600/big_alu.ll
@@ -51,29 +51,29 @@ main_body:
   %43 = extractelement <4 x float> %reg7, i32 1
   %44 = extractelement <4 x float> %reg7, i32 2
   %45 = extractelement <4 x float> %reg7, i32 3
-  %46 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
+  %46 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
   %47 = extractelement <4 x float> %46, i32 0
-  %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
+  %48 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
   %49 = extractelement <4 x float> %48, i32 1
-  %50 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
+  %50 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
   %51 = extractelement <4 x float> %50, i32 2
-  %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12)
+  %52 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12)
   %53 = extractelement <4 x float> %52, i32 0
-  %54 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
+  %54 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
   %55 = extractelement <4 x float> %54, i32 0
-  %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
+  %56 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
   %57 = extractelement <4 x float> %56, i32 1
-  %58 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
+  %58 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
   %59 = extractelement <4 x float> %58, i32 2
-  %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
+  %60 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
   %61 = extractelement <4 x float> %60, i32 3
-  %62 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16)
+  %62 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16)
   %63 = extractelement <4 x float> %62, i32 0
-  %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16)
+  %64 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16)
   %65 = extractelement <4 x float> %64, i32 1
-  %66 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16)
+  %66 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16)
   %67 = extractelement <4 x float> %66, i32 2
-  %68 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+  %68 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
   %69 = extractelement <4 x float> %68, i32 0
   %70 = fcmp oge float %69, 3.500000e+00
   %71 = sext i1 %70 to i32
@@ -81,7 +81,7 @@ main_body:
   %73 = bitcast float %72 to i32
   %74 = icmp ne i32 %73, 0
   %. = select i1 %74, float 0.000000e+00, float 0.000000e+00
-  %75 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+  %75 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
   %76 = extractelement <4 x float> %75, i32 0
   %77 = fcmp oge float %76, 2.000000e+00
   %78 = sext i1 %77 to i32
@@ -135,7 +135,7 @@ IF137:                                            ; preds = %main_body
   %123 = insertelement <4 x float> %122, float 0.000000e+00, i32 3
   %124 = call float @llvm.AMDGPU.dp4(<4 x float> %119, <4 x float> %123)
   %125 = fdiv float 1.000000e+00, %124
-  %126 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
+  %126 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
   %127 = extractelement <4 x float> %126, i32 0
   %128 = fmul float %127, %125
   %129 = fmul float %103, %128
@@ -347,15 +347,15 @@ ENDIF136:                                         ; preds = %main_body, %ENDIF15
   %329 = fmul float %314, %328
   %330 = fmul float %316, %328
   %331 = fmul float %318, %328
-  %332 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
+  %332 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
   %333 = extractelement <4 x float> %332, i32 0
   %334 = fsub float -0.000000e+00, %333
   %335 = fadd float 1.000000e+00, %334
-  %336 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
+  %336 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
   %337 = extractelement <4 x float> %336, i32 0
   %338 = fsub float -0.000000e+00, %337
   %339 = fadd float 1.000000e+00, %338
-  %340 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
+  %340 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
   %341 = extractelement <4 x float> %340, i32 0
   %342 = fsub float -0.000000e+00, %341
   %343 = fadd float 1.000000e+00, %342
@@ -1018,7 +1018,7 @@ ENDIF175:                                         ; preds = %ENDIF172, %IF176
   %temp92.11 = phi float [ %877, %IF176 ], [ %temp92.10, %ENDIF172 ]
   %temp93.5 = phi float [ %878, %IF176 ], [ %temp93.4, %ENDIF172 ]
   %temp94.5 = phi float [ %879, %IF176 ], [ %temp94.4, %ENDIF172 ]
-  %880 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
+  %880 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
   %881 = extractelement <4 x float> %880, i32 0
   %882 = fcmp olt float %881, %179
   %883 = sext i1 %882 to i32
@@ -1114,12 +1114,12 @@ ENDIF178:                                         ; preds = %ENDIF175, %IF179
   %960 = fmul float %temp87.6, %956
   %961 = fmul float %2, -2.000000e+00
   %962 = fadd float %961, 1.000000e+00
-  %963 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23)
+  %963 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23)
   %964 = extractelement <4 x float> %963, i32 2
   %965 = fsub float -0.000000e+00, %964
   %966 = fadd float %962, %965
   %967 = fdiv float 1.000000e+00, %966
-  %968 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24)
+  %968 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24)
   %969 = extractelement <4 x float> %968, i32 2
   %970 = fmul float %969, %967
   %971 = fsub float -0.000000e+00, %53
diff --git a/test/CodeGen/R600/bitcast.ll b/test/CodeGen/R600/bitcast.ll
index 1ba64af7dca3..fd56d956bf31 100644
--- a/test/CodeGen/R600/bitcast.ll
+++ b/test/CodeGen/R600/bitcast.ll
@@ -9,7 +9,7 @@ declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float
 ; SI: s_endpgm
 define void @v32i8_to_v8i32(<32 x i8> addrspace(2)* inreg) #0 {
 entry:
-  %1 = load <32 x i8> addrspace(2)* %0
+  %1 = load <32 x i8>, <32 x i8> addrspace(2)* %0
   %2 = bitcast <32 x i8> %1 to <8 x i32>
   %3 = extractelement <8 x i32> %2, i32 1
   %4 = icmp ne i32 %3, 0
@@ -23,34 +23,34 @@ entry:
 define void @i8ptr_v16i8ptr(<16 x i8> addrspace(1)* %out, i8 addrspace(1)* %in) {
 entry:
   %0 = bitcast i8 addrspace(1)* %in to <16 x i8> addrspace(1)*
-  %1 = load <16 x i8> addrspace(1)* %0
+  %1 = load <16 x i8>, <16 x i8> addrspace(1)* %0
   store <16 x i8> %1, <16 x i8> addrspace(1)* %out
   ret void
 }
 
 define void @f32_to_v2i16(<2 x i16> addrspace(1)* %out, float addrspace(1)* %in) nounwind {
-  %load = load float addrspace(1)* %in, align 4
+  %load = load float, float addrspace(1)* %in, align 4
   %bc = bitcast float %load to <2 x i16>
   store <2 x i16> %bc, <2 x i16> addrspace(1)* %out, align 4
   ret void
 }
 
 define void @v2i16_to_f32(float addrspace(1)* %out, <2 x i16> addrspace(1)* %in) nounwind {
-  %load = load <2 x i16> addrspace(1)* %in, align 4
+  %load = load <2 x i16>, <2 x i16> addrspace(1)* %in, align 4
   %bc = bitcast <2 x i16> %load to float
   store float %bc, float addrspace(1)* %out, align 4
   ret void
 }
 
 define void @v4i8_to_i32(i32 addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind {
-  %load = load <4 x i8> addrspace(1)* %in, align 4
+  %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
   %bc = bitcast <4 x i8> %load to i32
   store i32 %bc, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 define void @i32_to_v4i8(<4 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %load = load i32 addrspace(1)* %in, align 4
+  %load = load i32, i32 addrspace(1)* %in, align 4
   %bc = bitcast i32 %load to <4 x i8>
   store <4 x i8> %bc, <4 x i8> addrspace(1)* %out, align 4
   ret void
@@ -59,7 +59,7 @@ define void @i32_to_v4i8(<4 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) nou
 ; FUNC-LABEL: {{^}}bitcast_v2i32_to_f64:
 ; SI: s_endpgm
 define void @bitcast_v2i32_to_f64(double addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %val = load <2 x i32> addrspace(1)* %in, align 8
+  %val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8
   %add = add <2 x i32> %val, <i32 4, i32 9>
   %bc = bitcast <2 x i32> %add to double
   store double %bc, double addrspace(1)* %out, align 8
@@ -69,7 +69,7 @@ define void @bitcast_v2i32_to_f64(double addrspace(1)* %out, <2 x i32> addrspace
 ; FUNC-LABEL: {{^}}bitcast_f64_to_v2i32:
 ; SI: s_endpgm
 define void @bitcast_f64_to_v2i32(<2 x i32> addrspace(1)* %out, double addrspace(1)* %in) {
-  %val = load double addrspace(1)* %in, align 8
+  %val = load double, double addrspace(1)* %in, align 8
   %add = fadd double %val, 4.0
   %bc = bitcast double %add to <2 x i32>
   store <2 x i32> %bc, <2 x i32> addrspace(1)* %out, align 8
diff --git a/test/CodeGen/R600/bswap.ll b/test/CodeGen/R600/bswap.ll
index e93543de49da..4cf8e4bfed50 100644
--- a/test/CodeGen/R600/bswap.ll
+++ b/test/CodeGen/R600/bswap.ll
@@ -18,7 +18,7 @@ declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) nounwind readnone
 ; SI: buffer_store_dword [[RESULT]]
 ; SI: s_endpgm
 define void @test_bswap_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %val = load i32 addrspace(1)* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %bswap = call i32 @llvm.bswap.i32(i32 %val) nounwind readnone
   store i32 %bswap, i32 addrspace(1)* %out, align 4
   ret void
@@ -33,7 +33,7 @@ define void @test_bswap_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw
 ; SI-DAG: v_bfi_b32
 ; SI: s_endpgm
 define void @test_bswap_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) nounwind {
-  %val = load <2 x i32> addrspace(1)* %in, align 8
+  %val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8
   %bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %val) nounwind readnone
   store <2 x i32> %bswap, <2 x i32> addrspace(1)* %out, align 8
   ret void
@@ -54,7 +54,7 @@ define void @test_bswap_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(
 ; SI-DAG: v_bfi_b32
 ; SI: s_endpgm
 define void @test_bswap_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) nounwind {
-  %val = load <4 x i32> addrspace(1)* %in, align 16
+  %val = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
   %bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val) nounwind readnone
   store <4 x i32> %bswap, <4 x i32> addrspace(1)* %out, align 16
   ret void
@@ -87,28 +87,28 @@ define void @test_bswap_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(
 ; SI-DAG: v_bfi_b32
 ; SI: s_endpgm
 define void @test_bswap_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) nounwind {
-  %val = load <8 x i32> addrspace(1)* %in, align 32
+  %val = load <8 x i32>, <8 x i32> addrspace(1)* %in, align 32
   %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %val) nounwind readnone
   store <8 x i32> %bswap, <8 x i32> addrspace(1)* %out, align 32
   ret void
 }
 
 define void @test_bswap_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
-  %val = load i64 addrspace(1)* %in, align 8
+  %val = load i64, i64 addrspace(1)* %in, align 8
   %bswap = call i64 @llvm.bswap.i64(i64 %val) nounwind readnone
   store i64 %bswap, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 define void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) nounwind {
-  %val = load <2 x i64> addrspace(1)* %in, align 16
+  %val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
   %bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %val) nounwind readnone
   store <2 x i64> %bswap, <2 x i64> addrspace(1)* %out, align 16
   ret void
 }
 
 define void @test_bswap_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) nounwind {
-  %val = load <4 x i64> addrspace(1)* %in, align 32
+  %val = load <4 x i64>, <4 x i64> addrspace(1)* %in, align 32
   %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %val) nounwind readnone
   store <4 x i64> %bswap, <4 x i64> addrspace(1)* %out, align 32
   ret void
diff --git a/test/CodeGen/R600/call.ll b/test/CodeGen/R600/call.ll
index 9a0eb1cc3fa0..e769fd11c282 100644
--- a/test/CodeGen/R600/call.ll
+++ b/test/CodeGen/R600/call.ll
@@ -8,9 +8,9 @@
 declare i32 @external_function(i32) nounwind
 
 define void @test_call_external(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %a = load i32 addrspace(1)* %in
-  %b = load i32 addrspace(1)* %b_ptr
+  %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %a = load i32, i32 addrspace(1)* %in
+  %b = load i32, i32 addrspace(1)* %b_ptr
   %c = call i32 @external_function(i32 %b) nounwind
   %result = add i32 %a, %c
   store i32 %result, i32 addrspace(1)* %out
@@ -23,9 +23,9 @@ define i32 @defined_function(i32 %x) nounwind noinline {
 }
 
 define void @test_call(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %a = load i32 addrspace(1)* %in
-  %b = load i32 addrspace(1)* %b_ptr
+  %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %a = load i32, i32 addrspace(1)* %in
+  %b = load i32, i32 addrspace(1)* %b_ptr
   %c = call i32 @defined_function(i32 %b) nounwind
   %result = add i32 %a, %c
   store i32 %result, i32 addrspace(1)* %out
diff --git a/test/CodeGen/R600/call_fs.ll b/test/CodeGen/R600/call_fs.ll
index db2cb6e5011c..87bebbc49d52 100644
--- a/test/CodeGen/R600/call_fs.ll
+++ b/test/CodeGen/R600/call_fs.ll
@@ -2,11 +2,11 @@
 ; RUN: llc < %s -march=r600 -mcpu=redwood -show-mc-encoding -o - | FileCheck --check-prefix=EG %s
 ; RUN: llc < %s -march=r600 -mcpu=rv710 -show-mc-encoding -o - | FileCheck --check-prefix=R600 %s
 
-; EG: {{^}}call_fs:
 ; EG: .long 257
+; EG: {{^}}call_fs:
 ; EG: CALL_FS  ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x84]
-; R600: {{^}}call_fs:
 ; R600: .long 257
+; R600: {{^}}call_fs:
 ; R600:CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x89]
 
 
diff --git a/test/CodeGen/R600/coalescer_remat.ll b/test/CodeGen/R600/coalescer_remat.ll
new file mode 100644
index 000000000000..f78a77b36154
--- /dev/null
+++ b/test/CodeGen/R600/coalescer_remat.ll
@@ -0,0 +1,57 @@
+; RUN: llc -march=amdgcn -verify-machineinstrs -o - %s | FileCheck %s
+target triple="amdgcn--"
+
+declare float @llvm.fma.f32(float, float, float)
+
+; This checks that rematerialization support of the coalescer does not
+; unnecessarily widen the register class. Without those fixes > 20 VGprs
+; are used here
+; Also check that some rematerialization of the 0 constant happened.
+; CHECK-LABEL: foobar
+; CHECK:  v_mov_b32_e32 v{{[0-9]+}}, 0
+; CHECK:  v_mov_b32_e32 v{{[0-9]+}}, 0
+; CHECK:  v_mov_b32_e32 v{{[0-9]+}}, 0
+; CHECK:  v_mov_b32_e32 v{{[0-9]+}}, 0
+; CHECK: ; NumVgprs: 12
+define void @foobar(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in, i32 %flag) {
+entry:
+  %cmpflag = icmp eq i32 %flag, 1
+  br i1 %cmpflag, label %loop, label %exit
+
+loop:
+  %c = phi i32 [0, %entry], [%cnext, %loop]
+  %v0 = phi float [0.0, %entry], [%fma.0, %loop]
+  %v1 = phi float [0.0, %entry], [%fma.1, %loop]
+  %v2 = phi float [0.0, %entry], [%fma.2, %loop]
+  %v3 = phi float [0.0, %entry], [%fma.3, %loop]
+
+  ; Try to get the 0 constant to get coalesced into a wide register
+  %blup = insertelement <4 x float> undef, float %v0, i32 0
+  store <4 x float> %blup, <4 x float> addrspace(1)* %out
+
+  %load = load <4 x float>, <4 x float> addrspace(1)* %in
+  %load.0 = extractelement <4 x float> %load, i32 0
+  %load.1 = extractelement <4 x float> %load, i32 1
+  %load.2 = extractelement <4 x float> %load, i32 2
+  %load.3 = extractelement <4 x float> %load, i32 3
+  %fma.0 = call float @llvm.fma.f32(float %v0, float %load.0, float %v0)
+  %fma.1 = call float @llvm.fma.f32(float %v1, float %load.1, float %v1)
+  %fma.2 = call float @llvm.fma.f32(float %v2, float %load.2, float %v2)
+  %fma.3 = call float @llvm.fma.f32(float %v3, float %load.3, float %v3)
+
+  %cnext = add nsw i32 %c, 1
+  %cmp = icmp eq i32 %cnext, 42
+  br i1 %cmp, label %exit, label %loop
+
+exit:
+  %ev0 = phi float [0.0, %entry], [%fma.0, %loop]
+  %ev1 = phi float [0.0, %entry], [%fma.1, %loop]
+  %ev2 = phi float [0.0, %entry], [%fma.2, %loop]
+  %ev3 = phi float [0.0, %entry], [%fma.3, %loop]
+  %dst.0 = insertelement <4 x float> undef,  float %ev0, i32 0
+  %dst.1 = insertelement <4 x float> %dst.0, float %ev1, i32 1
+  %dst.2 = insertelement <4 x float> %dst.1, float %ev2, i32 2
+  %dst.3 = insertelement <4 x float> %dst.2, float %ev3, i32 3
+  store <4 x float> %dst.3, <4 x float> addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll b/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll
index e16a397bb5a4..0aecc189e0bf 100644
--- a/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll
+++ b/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll
@@ -14,7 +14,7 @@ define void @test(i8 addrspace(1)* nocapture readonly %in, i32 %a, i8 %b) {
 entry:
   %0 = mul nsw i32 %a, 3
   %1 = sext i32 %0 to i64
-  %2 = getelementptr i8 addrspace(1)* %in, i64 %1
+  %2 = getelementptr i8, i8 addrspace(1)* %in, i64 %1
   store i8 %b, i8 addrspace(1)* %2
   ret void
 }
diff --git a/test/CodeGen/R600/combine_vloads.ll b/test/CodeGen/R600/combine_vloads.ll
index 38420b25cba9..01572afa6205 100644
--- a/test/CodeGen/R600/combine_vloads.ll
+++ b/test/CodeGen/R600/combine_vloads.ll
@@ -23,7 +23,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.01 = phi i32 [ 0, %entry ], [ %tmp19, %for.body ]
   %arrayidx_v4 = bitcast <8 x i8> addrspace(1)* %src to <32 x i8> addrspace(1)*
   %0 = bitcast <32 x i8> addrspace(1)* %arrayidx_v4 to <8 x i32> addrspace(1)*
-  %vecload2 = load <8 x i32> addrspace(1)* %0, align 32
+  %vecload2 = load <8 x i32>, <8 x i32> addrspace(1)* %0, align 32
   %1 = bitcast <8 x i32> %vecload2 to <32 x i8>
   %tmp5 = shufflevector <32 x i8> %1, <32 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   %tmp8 = shufflevector <32 x i8> %1, <32 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -32,7 +32,7 @@ for.body:                                         ; preds = %for.body, %entry
   %tmp13 = add nsw <8 x i8> %tmp9, %tmp12
   %tmp16 = shufflevector <32 x i8> %1, <32 x i8> undef, <8 x i32> <i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   %tmp17 = add nsw <8 x i8> %tmp13, %tmp16
-  %scevgep = getelementptr <8 x i8> addrspace(1)* %result, i32 %i.01
+  %scevgep = getelementptr <8 x i8>, <8 x i8> addrspace(1)* %result, i32 %i.01
   %2 = bitcast <8 x i8> %tmp17 to <2 x i32>
   %3 = bitcast <8 x i8> addrspace(1)* %scevgep to <2 x i32> addrspace(1)*
   store <2 x i32> %2, <2 x i32> addrspace(1)* %3, align 8
diff --git a/test/CodeGen/R600/commute-compares.ll b/test/CodeGen/R600/commute-compares.ll
new file mode 100644
index 000000000000..31766047a358
--- /dev/null
+++ b/test/CodeGen/R600/commute-compares.ll
@@ -0,0 +1,697 @@
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+
+declare i32 @llvm.r600.read.tidig.x() #0
+
+; --------------------------------------------------------------------------------
+; i32 compares
+; --------------------------------------------------------------------------------
+
+; GCN-LABEL: {{^}}commute_eq_64_i32:
+; GCN: v_cmp_eq_i32_e32 vcc, 64, v{{[0-9]+}}
+define void @commute_eq_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i32, i32 addrspace(1)* %gep.in
+  %cmp = icmp eq i32 %val, 64
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ne_64_i32:
+; GCN: v_cmp_ne_i32_e32 vcc, 64, v{{[0-9]+}}
+define void @commute_ne_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i32, i32 addrspace(1)* %gep.in
+  %cmp = icmp ne i32 %val, 64
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; FIXME: Why isn't this being folded as a constant?
+; GCN-LABEL: {{^}}commute_ne_litk_i32:
+; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x3039
+; GCN: v_cmp_ne_i32_e32 vcc, [[K]], v{{[0-9]+}}
+define void @commute_ne_litk_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i32, i32 addrspace(1)* %gep.in
+  %cmp = icmp ne i32 %val, 12345
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ugt_64_i32:
+; GCN: v_cmp_lt_u32_e32 vcc, 64, v{{[0-9]+}}
+define void @commute_ugt_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i32, i32 addrspace(1)* %gep.in
+  %cmp = icmp ugt i32 %val, 64
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_uge_64_i32:
+; GCN: v_cmp_lt_u32_e32 vcc, 63, v{{[0-9]+}}
+define void @commute_uge_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i32, i32 addrspace(1)* %gep.in
+  %cmp = icmp uge i32 %val, 64
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ult_64_i32:
+; GCN: v_cmp_gt_u32_e32 vcc, 64, v{{[0-9]+}}
+define void @commute_ult_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i32, i32 addrspace(1)* %gep.in
+  %cmp = icmp ult i32 %val, 64
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ule_63_i32:
+; GCN: v_cmp_gt_u32_e32 vcc, 64, v{{[0-9]+}}
+define void @commute_ule_63_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i32, i32 addrspace(1)* %gep.in
+  %cmp = icmp ule i32 %val, 63
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; FIXME: Undo canonicalization to gt (x + 1) since it doesn't use the inline imm
+
+; GCN-LABEL: {{^}}commute_ule_64_i32:
+; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x41{{$}}
+; GCN: v_cmp_gt_u32_e32 vcc, [[K]], v{{[0-9]+}}
+define void @commute_ule_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i32, i32 addrspace(1)* %gep.in
+  %cmp = icmp ule i32 %val, 64
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_sgt_neg1_i32:
+; GCN: v_cmp_lt_i32_e32 vcc, -1, v{{[0-9]+}}
+define void @commute_sgt_neg1_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i32, i32 addrspace(1)* %gep.in
+  %cmp = icmp sgt i32 %val, -1
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_sge_neg2_i32:
+; GCN: v_cmp_lt_i32_e32 vcc, -3, v{{[0-9]+}}
+define void @commute_sge_neg2_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i32, i32 addrspace(1)* %gep.in
+  %cmp = icmp sge i32 %val, -2
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_slt_neg16_i32:
+; GCN: v_cmp_gt_i32_e32 vcc, -16, v{{[0-9]+}}
+define void @commute_slt_neg16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i32, i32 addrspace(1)* %gep.in
+  %cmp = icmp slt i32 %val, -16
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_sle_5_i32:
+; GCN: v_cmp_gt_i32_e32 vcc, 6, v{{[0-9]+}}
+define void @commute_sle_5_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i32, i32 addrspace(1)* %gep.in
+  %cmp = icmp sle i32 %val, 5
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; --------------------------------------------------------------------------------
+; i64 compares
+; --------------------------------------------------------------------------------
+
+; GCN-LABEL: {{^}}commute_eq_64_i64:
+; GCN: v_cmp_eq_i64_e32 vcc, 64, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_eq_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i64, i64 addrspace(1)* %gep.in
+  %cmp = icmp eq i64 %val, 64
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ne_64_i64:
+; GCN: v_cmp_ne_i64_e32 vcc, 64, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_ne_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i64, i64 addrspace(1)* %gep.in
+  %cmp = icmp ne i64 %val, 64
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ugt_64_i64:
+; GCN: v_cmp_lt_u64_e32 vcc, 64, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_ugt_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i64, i64 addrspace(1)* %gep.in
+  %cmp = icmp ugt i64 %val, 64
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_uge_64_i64:
+; GCN: v_cmp_lt_u64_e32 vcc, 63, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_uge_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i64, i64 addrspace(1)* %gep.in
+  %cmp = icmp uge i64 %val, 64
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ult_64_i64:
+; GCN: v_cmp_gt_u64_e32 vcc, 64, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_ult_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i64, i64 addrspace(1)* %gep.in
+  %cmp = icmp ult i64 %val, 64
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ule_63_i64:
+; GCN: v_cmp_gt_u64_e32 vcc, 64, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_ule_63_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i64, i64 addrspace(1)* %gep.in
+  %cmp = icmp ule i64 %val, 63
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; FIXME: Undo canonicalization to gt (x + 1) since it doesn't use the inline imm
+
+; GCN-LABEL: {{^}}commute_ule_64_i64:
+; GCN-DAG: s_movk_i32 s[[KLO:[0-9]+]], 0x41{{$}}
+; GCN: v_cmp_gt_u64_e32 vcc, s{{\[}}[[KLO]]:{{[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_ule_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i64, i64 addrspace(1)* %gep.in
+  %cmp = icmp ule i64 %val, 64
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_sgt_neg1_i64:
+; GCN: v_cmp_lt_i64_e32 vcc, -1, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_sgt_neg1_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i64, i64 addrspace(1)* %gep.in
+  %cmp = icmp sgt i64 %val, -1
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_sge_neg2_i64:
+; GCN: v_cmp_lt_i64_e32 vcc, -3, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_sge_neg2_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i64, i64 addrspace(1)* %gep.in
+  %cmp = icmp sge i64 %val, -2
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_slt_neg16_i64:
+; GCN: v_cmp_gt_i64_e32 vcc, -16, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_slt_neg16_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i64, i64 addrspace(1)* %gep.in
+  %cmp = icmp slt i64 %val, -16
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_sle_5_i64:
+; GCN: v_cmp_gt_i64_e32 vcc, 6, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_sle_5_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load i64, i64 addrspace(1)* %gep.in
+  %cmp = icmp sle i64 %val, 5
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; --------------------------------------------------------------------------------
+; f32 compares
+; --------------------------------------------------------------------------------
+
+
+; GCN-LABEL: {{^}}commute_oeq_2.0_f32:
+; GCN: v_cmp_eq_f32_e32 vcc, 2.0, v{{[0-9]+}}
+define void @commute_oeq_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load float, float addrspace(1)* %gep.in
+  %cmp = fcmp oeq float %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+
+; GCN-LABEL: {{^}}commute_ogt_2.0_f32:
+; GCN: v_cmp_lt_f32_e32 vcc, 2.0, v{{[0-9]+}}
+define void @commute_ogt_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load float, float addrspace(1)* %gep.in
+  %cmp = fcmp ogt float %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_oge_2.0_f32:
+; GCN: v_cmp_le_f32_e32 vcc, 2.0, v{{[0-9]+}}
+define void @commute_oge_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load float, float addrspace(1)* %gep.in
+  %cmp = fcmp oge float %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_olt_2.0_f32:
+; GCN: v_cmp_gt_f32_e32 vcc, 2.0, v{{[0-9]+}}
+define void @commute_olt_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load float, float addrspace(1)* %gep.in
+  %cmp = fcmp olt float %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ole_2.0_f32:
+; GCN: v_cmp_ge_f32_e32 vcc, 2.0, v{{[0-9]+}}
+define void @commute_ole_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load float, float addrspace(1)* %gep.in
+  %cmp = fcmp ole float %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_one_2.0_f32:
+; GCN: v_cmp_lg_f32_e32 vcc, 2.0, v{{[0-9]+}}
+define void @commute_one_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load float, float addrspace(1)* %gep.in
+  %cmp = fcmp one float %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ord_2.0_f32:
+; GCN: v_cmp_o_f32_e32 vcc, [[REG:v[0-9]+]], [[REG]]
+define void @commute_ord_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load float, float addrspace(1)* %gep.in
+  %cmp = fcmp ord float %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ueq_2.0_f32:
+; GCN: v_cmp_nlg_f32_e32 vcc, 2.0, v{{[0-9]+}}
+define void @commute_ueq_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load float, float addrspace(1)* %gep.in
+  %cmp = fcmp ueq float %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ugt_2.0_f32:
+; GCN: v_cmp_nge_f32_e32 vcc, 2.0, v{{[0-9]+}}
+define void @commute_ugt_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load float, float addrspace(1)* %gep.in
+  %cmp = fcmp ugt float %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_uge_2.0_f32:
+; GCN: v_cmp_ngt_f32_e32 vcc, 2.0, v{{[0-9]+}}
+define void @commute_uge_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load float, float addrspace(1)* %gep.in
+  %cmp = fcmp uge float %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ult_2.0_f32:
+; GCN: v_cmp_nle_f32_e32 vcc, 2.0, v{{[0-9]+}}
+define void @commute_ult_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load float, float addrspace(1)* %gep.in
+  %cmp = fcmp ult float %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ule_2.0_f32:
+; GCN: v_cmp_nlt_f32_e32 vcc, 2.0, v{{[0-9]+}}
+define void @commute_ule_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load float, float addrspace(1)* %gep.in
+  %cmp = fcmp ule float %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_une_2.0_f32:
+; GCN: v_cmp_neq_f32_e32 vcc, 2.0, v{{[0-9]+}}
+define void @commute_une_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load float, float addrspace(1)* %gep.in
+  %cmp = fcmp une float %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_uno_2.0_f32:
+; GCN: v_cmp_u_f32_e32 vcc, [[REG:v[0-9]+]], [[REG]]
+define void @commute_uno_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load float, float addrspace(1)* %gep.in
+  %cmp = fcmp uno float %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; --------------------------------------------------------------------------------
+; f64 compares
+; --------------------------------------------------------------------------------
+
+
+; GCN-LABEL: {{^}}commute_oeq_2.0_f64:
+; GCN: v_cmp_eq_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_oeq_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load double, double addrspace(1)* %gep.in
+  %cmp = fcmp oeq double %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+
+; GCN-LABEL: {{^}}commute_ogt_2.0_f64:
+; GCN: v_cmp_lt_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_ogt_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load double, double addrspace(1)* %gep.in
+  %cmp = fcmp ogt double %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_oge_2.0_f64:
+; GCN: v_cmp_le_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_oge_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load double, double addrspace(1)* %gep.in
+  %cmp = fcmp oge double %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_olt_2.0_f64:
+; GCN: v_cmp_gt_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_olt_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load double, double addrspace(1)* %gep.in
+  %cmp = fcmp olt double %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ole_2.0_f64:
+; GCN: v_cmp_ge_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_ole_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load double, double addrspace(1)* %gep.in
+  %cmp = fcmp ole double %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_one_2.0_f64:
+; GCN: v_cmp_lg_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_one_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load double, double addrspace(1)* %gep.in
+  %cmp = fcmp one double %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ord_2.0_f64:
+; GCN: v_cmp_o_f64_e32 vcc, [[REG:v\[[0-9]+:[0-9]+\]]], [[REG]]
+define void @commute_ord_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load double, double addrspace(1)* %gep.in
+  %cmp = fcmp ord double %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ueq_2.0_f64:
+; GCN: v_cmp_nlg_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_ueq_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load double, double addrspace(1)* %gep.in
+  %cmp = fcmp ueq double %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ugt_2.0_f64:
+; GCN: v_cmp_nge_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_ugt_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load double, double addrspace(1)* %gep.in
+  %cmp = fcmp ugt double %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_uge_2.0_f64:
+; GCN: v_cmp_ngt_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_uge_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load double, double addrspace(1)* %gep.in
+  %cmp = fcmp uge double %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ult_2.0_f64:
+; GCN: v_cmp_nle_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_ult_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load double, double addrspace(1)* %gep.in
+  %cmp = fcmp ult double %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_ule_2.0_f64:
+; GCN: v_cmp_nlt_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_ule_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load double, double addrspace(1)* %gep.in
+  %cmp = fcmp ule double %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_une_2.0_f64:
+; GCN: v_cmp_neq_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
+define void @commute_une_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load double, double addrspace(1)* %gep.in
+  %cmp = fcmp une double %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+; GCN-LABEL: {{^}}commute_uno_2.0_f64:
+; GCN: v_cmp_u_f64_e32 vcc, [[REG:v\[[0-9]+:[0-9]+\]]], [[REG]]
+define void @commute_uno_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %val = load double, double addrspace(1)* %gep.in
+  %cmp = fcmp uno double %val, 2.0
+  %ext = sext i1 %cmp to i32
+  store i32 %ext, i32 addrspace(1)* %gep.out
+  ret void
+}
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }
diff --git a/test/CodeGen/R600/commute_modifiers.ll b/test/CodeGen/R600/commute_modifiers.ll
index 6fddb6d595c9..7fc36eabb780 100644
--- a/test/CodeGen/R600/commute_modifiers.ll
+++ b/test/CodeGen/R600/commute_modifiers.ll
@@ -10,8 +10,8 @@ declare float @llvm.fma.f32(float, float, float) nounwind readnone
 ; SI-NEXT: buffer_store_dword [[REG]]
 define void @commute_add_imm_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %x = load float addrspace(1)* %gep.0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %x = load float, float addrspace(1)* %gep.0
   %x.fabs = call float @llvm.fabs.f32(float %x) #1
   %z = fadd float 2.0, %x.fabs
   store float %z, float addrspace(1)* %out
@@ -24,8 +24,8 @@ define void @commute_add_imm_fabs_f32(float addrspace(1)* %out, float addrspace(
 ; SI-NEXT: buffer_store_dword [[REG]]
 define void @commute_mul_imm_fneg_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %x = load float addrspace(1)* %gep.0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %x = load float, float addrspace(1)* %gep.0
   %x.fabs = call float @llvm.fabs.f32(float %x) #1
   %x.fneg.fabs = fsub float -0.000000e+00, %x.fabs
   %z = fmul float 4.0, %x.fneg.fabs
@@ -39,8 +39,8 @@ define void @commute_mul_imm_fneg_fabs_f32(float addrspace(1)* %out, float addrs
 ; SI-NEXT: buffer_store_dword [[REG]]
 define void @commute_mul_imm_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %x = load float addrspace(1)* %gep.0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %x = load float, float addrspace(1)* %gep.0
   %x.fneg = fsub float -0.000000e+00, %x
   %z = fmul float 4.0, %x.fneg
   store float %z, float addrspace(1)* %out
@@ -55,8 +55,8 @@ define void @commute_mul_imm_fneg_f32(float addrspace(1)* %out, float addrspace(
 ; SI-NEXT: buffer_store_dword [[REG]]
 define void @commute_add_lit_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %x = load float addrspace(1)* %gep.0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %x = load float, float addrspace(1)* %gep.0
   %x.fabs = call float @llvm.fabs.f32(float %x) #1
   %z = fadd float 1024.0, %x.fabs
   store float %z, float addrspace(1)* %out
@@ -70,10 +70,10 @@ define void @commute_add_lit_fabs_f32(float addrspace(1)* %out, float addrspace(
 ; SI-NEXT: buffer_store_dword [[REG]]
 define void @commute_add_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %x = load float addrspace(1)* %gep.0
-  %y = load float addrspace(1)* %gep.1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %x = load float, float addrspace(1)* %gep.0
+  %y = load float, float addrspace(1)* %gep.1
   %y.fabs = call float @llvm.fabs.f32(float %y) #1
   %z = fadd float %x, %y.fabs
   store float %z, float addrspace(1)* %out
@@ -87,10 +87,10 @@ define void @commute_add_fabs_f32(float addrspace(1)* %out, float addrspace(1)*
 ; SI-NEXT: buffer_store_dword [[REG]]
 define void @commute_mul_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %x = load float addrspace(1)* %gep.0
-  %y = load float addrspace(1)* %gep.1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %x = load float, float addrspace(1)* %gep.0
+  %y = load float, float addrspace(1)* %gep.1
   %y.fneg = fsub float -0.000000e+00, %y
   %z = fmul float %x, %y.fneg
   store float %z, float addrspace(1)* %out
@@ -104,10 +104,10 @@ define void @commute_mul_fneg_f32(float addrspace(1)* %out, float addrspace(1)*
 ; SI-NEXT: buffer_store_dword [[REG]]
 define void @commute_mul_fabs_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %x = load float addrspace(1)* %gep.0
-  %y = load float addrspace(1)* %gep.1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %x = load float, float addrspace(1)* %gep.0
+  %y = load float, float addrspace(1)* %gep.1
   %y.fabs = call float @llvm.fabs.f32(float %y) #1
   %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs
   %z = fmul float %x, %y.fabs.fneg
@@ -123,10 +123,10 @@ define void @commute_mul_fabs_fneg_f32(float addrspace(1)* %out, float addrspace
 ; SI-NEXT: buffer_store_dword [[REG]]
 define void @commute_mul_fabs_x_fabs_y_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %x = load float addrspace(1)* %gep.0
-  %y = load float addrspace(1)* %gep.1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %x = load float, float addrspace(1)* %gep.0
+  %y = load float, float addrspace(1)* %gep.1
   %x.fabs = call float @llvm.fabs.f32(float %x) #1
   %y.fabs = call float @llvm.fabs.f32(float %y) #1
   %z = fmul float %x.fabs, %y.fabs
@@ -141,10 +141,10 @@ define void @commute_mul_fabs_x_fabs_y_f32(float addrspace(1)* %out, float addrs
 ; SI-NEXT: buffer_store_dword [[REG]]
 define void @commute_mul_fabs_x_fneg_fabs_y_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %x = load float addrspace(1)* %gep.0
-  %y = load float addrspace(1)* %gep.1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %x = load float, float addrspace(1)* %gep.0
+  %y = load float, float addrspace(1)* %gep.1
   %x.fabs = call float @llvm.fabs.f32(float %x) #1
   %y.fabs = call float @llvm.fabs.f32(float %y) #1
   %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs
@@ -163,12 +163,12 @@ define void @commute_mul_fabs_x_fneg_fabs_y_f32(float addrspace(1)* %out, float
 ; SI: buffer_store_dword [[RESULT]]
 define void @fma_a_2.0_neg_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %gep.out = getelementptr float addrspace(1)* %out, i32 %tid
+  %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
 
-  %r1 = load float addrspace(1)* %gep.0
-  %r2 = load float addrspace(1)* %gep.1
+  %r1 = load float, float addrspace(1)* %gep.0
+  %r2 = load float, float addrspace(1)* %gep.1
 
   %r2.fabs = call float @llvm.fabs.f32(float %r2)
 
diff --git a/test/CodeGen/R600/concat_vectors.ll b/test/CodeGen/R600/concat_vectors.ll
index b27bed3d4265..a09ed1f73857 100644
--- a/test/CodeGen/R600/concat_vectors.ll
+++ b/test/CodeGen/R600/concat_vectors.ll
@@ -288,7 +288,7 @@ define void @test_concat_v16i16(<32 x i16> addrspace(1)* %out, <16 x i16> %a, <1
 ; SI: s_endpgm
 define void @concat_vector_crash(<8 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) {
 bb:
-  %tmp = load <2 x float> addrspace(1)* %in, align 4
+  %tmp = load <2 x float>, <2 x float> addrspace(1)* %in, align 4
   %tmp1 = shufflevector <2 x float> %tmp, <2 x float> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %tmp2 = shufflevector <8 x float> undef, <8 x float> %tmp1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
   store <8 x float> %tmp2, <8 x float> addrspace(1)* %out, align 32
diff --git a/test/CodeGen/R600/copy-illegal-type.ll b/test/CodeGen/R600/copy-illegal-type.ll
index 56c43d23b4a1..8b397566066a 100644
--- a/test/CodeGen/R600/copy-illegal-type.ll
+++ b/test/CodeGen/R600/copy-illegal-type.ll
@@ -6,7 +6,7 @@
 ; SI: buffer_store_dword [[REG]]
 ; SI: s_endpgm
 define void @test_copy_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind {
-  %val = load <4 x i8> addrspace(1)* %in, align 4
+  %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
   store <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4
   ret void
 }
@@ -17,7 +17,7 @@ define void @test_copy_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)*
 ; SI: buffer_store_dword [[REG]]
 ; SI: s_endpgm
 define void @test_copy_v4i8_x2(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %in) nounwind {
-  %val = load <4 x i8> addrspace(1)* %in, align 4
+  %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
   store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
   store <4 x i8> %val, <4 x i8> addrspace(1)* %out1, align 4
   ret void
@@ -30,7 +30,7 @@ define void @test_copy_v4i8_x2(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(
 ; SI: buffer_store_dword [[REG]]
 ; SI: s_endpgm
 define void @test_copy_v4i8_x3(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind {
-  %val = load <4 x i8> addrspace(1)* %in, align 4
+  %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
   store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
   store <4 x i8> %val, <4 x i8> addrspace(1)* %out1, align 4
   store <4 x i8> %val, <4 x i8> addrspace(1)* %out2, align 4
@@ -45,7 +45,7 @@ define void @test_copy_v4i8_x3(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(
 ; SI: buffer_store_dword [[REG]]
 ; SI: s_endpgm
 define void @test_copy_v4i8_x4(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %out3, <4 x i8> addrspace(1)* %in) nounwind {
-  %val = load <4 x i8> addrspace(1)* %in, align 4
+  %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
   store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
   store <4 x i8> %val, <4 x i8> addrspace(1)* %out1, align 4
   store <4 x i8> %val, <4 x i8> addrspace(1)* %out2, align 4
@@ -82,7 +82,7 @@ define void @test_copy_v4i8_x4(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(
 
 ; SI: s_endpgm
 define void @test_copy_v4i8_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %in) nounwind {
-  %val = load <4 x i8> addrspace(1)* %in, align 4
+  %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
   %add = add <4 x i8> %val, <i8 9, i8 9, i8 9, i8 9>
   store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
   store <4 x i8> %add, <4 x i8> addrspace(1)* %out1, align 4
@@ -120,7 +120,7 @@ define void @test_copy_v4i8_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> add
 
 ; SI: s_endpgm
 define void @test_copy_v4i8_x2_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind {
-  %val = load <4 x i8> addrspace(1)* %in, align 4
+  %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
   %add = add <4 x i8> %val, <i8 9, i8 9, i8 9, i8 9>
   store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
   store <4 x i8> %add, <4 x i8> addrspace(1)* %out1, align 4
@@ -133,7 +133,7 @@ define void @test_copy_v4i8_x2_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8>
 ; SI-NOT: bfi
 ; SI: s_endpgm
 define void @test_copy_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) nounwind {
-  %val = load <3 x i8> addrspace(1)* %in, align 4
+  %val = load <3 x i8>, <3 x i8> addrspace(1)* %in, align 4
   store <3 x i8> %val, <3 x i8> addrspace(1)* %out, align 4
   ret void
 }
@@ -145,7 +145,7 @@ define void @test_copy_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)*
 ; SI: buffer_load_ubyte
 ; SI: s_endpgm
 define void @test_copy_v4i8_volatile_load(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind {
-  %val = load volatile <4 x i8> addrspace(1)* %in, align 4
+  %val = load volatile <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
   store <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4
   ret void
 }
@@ -161,7 +161,7 @@ define void @test_copy_v4i8_volatile_load(<4 x i8> addrspace(1)* %out, <4 x i8>
 ; SI: buffer_store_byte
 ; SI: s_endpgm
 define void @test_copy_v4i8_volatile_store(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind {
-  %val = load <4 x i8> addrspace(1)* %in, align 4
+  %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
   store volatile <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4
   ret void
 }
diff --git a/test/CodeGen/R600/copy-to-reg.ll b/test/CodeGen/R600/copy-to-reg.ll
index 9c1de73b3b1b..fc875f6ef7a3 100644
--- a/test/CodeGen/R600/copy-to-reg.ll
+++ b/test/CodeGen/R600/copy-to-reg.ll
@@ -13,15 +13,15 @@ entry:
 
 loop:
   %inc = phi i32 [0, %entry], [%inc.i, %loop]
-  %ptr = getelementptr [16 x i32]* %alloca, i32 0, i32 %inc
+  %ptr = getelementptr [16 x i32], [16 x i32]* %alloca, i32 0, i32 %inc
   store i32 %inc, i32* %ptr
   %inc.i = add i32 %inc, 1
   %cnd = icmp uge i32 %inc.i, 16
   br i1 %cnd, label %done, label %loop
 
 done:
-  %tmp0 = getelementptr [16 x i32]* %alloca, i32 0, i32 0
-  %tmp1 = load i32* %tmp0
+  %tmp0 = getelementptr [16 x i32], [16 x i32]* %alloca, i32 0, i32 0
+  %tmp1 = load i32, i32* %tmp0
   store i32 %tmp1, i32 addrspace(1)* %out
   ret void
 }
diff --git a/test/CodeGen/R600/ctlz_zero_undef.ll b/test/CodeGen/R600/ctlz_zero_undef.ll
index 1a4317b8095c..bd26c302fe5a 100644
--- a/test/CodeGen/R600/ctlz_zero_undef.ll
+++ b/test/CodeGen/R600/ctlz_zero_undef.ll
@@ -28,7 +28,7 @@ define void @s_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nou
 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
 define void @v_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
-  %val = load i32 addrspace(1)* %valptr, align 4
+  %val = load i32, i32 addrspace(1)* %valptr, align 4
   %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
   store i32 %ctlz, i32 addrspace(1)* %out, align 4
   ret void
@@ -44,7 +44,7 @@ define void @v_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace
 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
 define void @v_ctlz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind {
-  %val = load <2 x i32> addrspace(1)* %valptr, align 8
+  %val = load <2 x i32>, <2 x i32> addrspace(1)* %valptr, align 8
   %ctlz = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %val, i1 true) nounwind readnone
   store <2 x i32> %ctlz, <2 x i32> addrspace(1)* %out, align 8
   ret void
@@ -64,7 +64,7 @@ define void @v_ctlz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x
 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
 define void @v_ctlz_zero_undef_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind {
-  %val = load <4 x i32> addrspace(1)* %valptr, align 16
+  %val = load <4 x i32>, <4 x i32> addrspace(1)* %valptr, align 16
   %ctlz = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val, i1 true) nounwind readnone
   store <4 x i32> %ctlz, <4 x i32> addrspace(1)* %out, align 16
   ret void
diff --git a/test/CodeGen/R600/ctpop.ll b/test/CodeGen/R600/ctpop.ll
index c64f443ad697..0a031c5e24d1 100644
--- a/test/CodeGen/R600/ctpop.ll
+++ b/test/CodeGen/R600/ctpop.ll
@@ -1,4 +1,5 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC -check-prefix=VI %s
 ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 
 declare i32 @llvm.ctpop.i32(i32) nounwind readnone
@@ -8,11 +9,11 @@ declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>) nounwind readnone
 declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>) nounwind readnone
 
 ; FUNC-LABEL: {{^}}s_ctpop_i32:
-; SI: s_load_dword [[SVAL:s[0-9]+]],
-; SI: s_bcnt1_i32_b32 [[SRESULT:s[0-9]+]], [[SVAL]]
-; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
-; SI: buffer_store_dword [[VRESULT]],
-; SI: s_endpgm
+; GCN: s_load_dword [[SVAL:s[0-9]+]],
+; GCN: s_bcnt1_i32_b32 [[SRESULT:s[0-9]+]], [[SVAL]]
+; GCN: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
+; GCN: buffer_store_dword [[VRESULT]],
+; GCN: s_endpgm
 
 ; EG: BCNT_INT
 define void @s_ctpop_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
@@ -23,32 +24,33 @@ define void @s_ctpop_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
 
 ; XXX - Why 0 in register?
 ; FUNC-LABEL: {{^}}v_ctpop_i32:
-; SI: buffer_load_dword [[VAL:v[0-9]+]],
-; SI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 0
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
+; GCN: buffer_load_dword [[VAL:v[0-9]+]],
+; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 0
+; GCN: buffer_store_dword [[RESULT]],
+; GCN: s_endpgm
 
 ; EG: BCNT_INT
 define void @v_ctpop_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
-  %val = load i32 addrspace(1)* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
   store i32 %ctpop, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; FUNC-LABEL: {{^}}v_ctpop_add_chain_i32:
-; SI: buffer_load_dword [[VAL0:v[0-9]+]],
-; SI: buffer_load_dword [[VAL1:v[0-9]+]],
-; SI: v_bcnt_u32_b32_e64 [[MIDRESULT:v[0-9]+]], [[VAL1]], 0
-; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
+; GCN: buffer_load_dword [[VAL1:v[0-9]+]],
+; GCN: buffer_load_dword [[VAL0:v[0-9]+]],
+; GCN: v_bcnt_u32_b32_e64 [[MIDRESULT:v[0-9]+]], [[VAL1]], 0
+; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
+; VI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
+; GCN: buffer_store_dword [[RESULT]],
+; GCN: s_endpgm
 
 ; EG: BCNT_INT
 ; EG: BCNT_INT
 define void @v_ctpop_add_chain_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in0, i32 addrspace(1)* noalias %in1) nounwind {
-  %val0 = load i32 addrspace(1)* %in0, align 4
-  %val1 = load i32 addrspace(1)* %in1, align 4
+  %val0 = load i32, i32 addrspace(1)* %in0, align 4
+  %val1 = load i32, i32 addrspace(1)* %in1, align 4
   %ctpop0 = call i32 @llvm.ctpop.i32(i32 %val0) nounwind readnone
   %ctpop1 = call i32 @llvm.ctpop.i32(i32 %val1) nounwind readnone
   %add = add i32 %ctpop0, %ctpop1
@@ -57,13 +59,13 @@ define void @v_ctpop_add_chain_i32(i32 addrspace(1)* noalias %out, i32 addrspace
 }
 
 ; FUNC-LABEL: {{^}}v_ctpop_add_sgpr_i32:
-; SI: buffer_load_dword [[VAL0:v[0-9]+]],
-; SI-NEXT: s_waitcnt
-; SI-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], s{{[0-9]+}}
-; SI-NEXT: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
+; GCN: buffer_load_dword [[VAL0:v[0-9]+]],
+; GCN-NEXT: s_waitcnt
+; GCN-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], s{{[0-9]+}}
+; GCN-NEXT: buffer_store_dword [[RESULT]],
+; GCN: s_endpgm
 define void @v_ctpop_add_sgpr_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in0, i32 addrspace(1)* noalias %in1, i32 %sval) nounwind {
-  %val0 = load i32 addrspace(1)* %in0, align 4
+  %val0 = load i32, i32 addrspace(1)* %in0, align 4
   %ctpop0 = call i32 @llvm.ctpop.i32(i32 %val0) nounwind readnone
   %add = add i32 %ctpop0, %sval
   store i32 %add, i32 addrspace(1)* %out, align 4
@@ -71,47 +73,47 @@ define void @v_ctpop_add_sgpr_i32(i32 addrspace(1)* noalias %out, i32 addrspace(
 }
 
 ; FUNC-LABEL: {{^}}v_ctpop_v2i32:
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: s_endpgm
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: s_endpgm
 
 ; EG: BCNT_INT
 ; EG: BCNT_INT
 define void @v_ctpop_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %in) nounwind {
-  %val = load <2 x i32> addrspace(1)* %in, align 8
+  %val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8
   %ctpop = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %val) nounwind readnone
   store <2 x i32> %ctpop, <2 x i32> addrspace(1)* %out, align 8
   ret void
 }
 
 ; FUNC-LABEL: {{^}}v_ctpop_v4i32:
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: s_endpgm
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: s_endpgm
 
 ; EG: BCNT_INT
 ; EG: BCNT_INT
 ; EG: BCNT_INT
 ; EG: BCNT_INT
 define void @v_ctpop_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %in) nounwind {
-  %val = load <4 x i32> addrspace(1)* %in, align 16
+  %val = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
   %ctpop = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %val) nounwind readnone
   store <4 x i32> %ctpop, <4 x i32> addrspace(1)* %out, align 16
   ret void
 }
 
 ; FUNC-LABEL: {{^}}v_ctpop_v8i32:
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: s_endpgm
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: s_endpgm
 
 ; EG: BCNT_INT
 ; EG: BCNT_INT
@@ -122,30 +124,30 @@ define void @v_ctpop_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrs
 ; EG: BCNT_INT
 ; EG: BCNT_INT
 define void @v_ctpop_v8i32(<8 x i32> addrspace(1)* noalias %out, <8 x i32> addrspace(1)* noalias %in) nounwind {
-  %val = load <8 x i32> addrspace(1)* %in, align 32
+  %val = load <8 x i32>, <8 x i32> addrspace(1)* %in, align 32
   %ctpop = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %val) nounwind readnone
   store <8 x i32> %ctpop, <8 x i32> addrspace(1)* %out, align 32
   ret void
 }
 
 ; FUNC-LABEL: {{^}}v_ctpop_v16i32:
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: v_bcnt_u32_b32_e64
-; SI: s_endpgm
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: v_bcnt_u32_b32_e64
+; GCN: s_endpgm
 
 ; EG: BCNT_INT
 ; EG: BCNT_INT
@@ -164,21 +166,21 @@ define void @v_ctpop_v8i32(<8 x i32> addrspace(1)* noalias %out, <8 x i32> addrs
 ; EG: BCNT_INT
 ; EG: BCNT_INT
 define void @v_ctpop_v16i32(<16 x i32> addrspace(1)* noalias %out, <16 x i32> addrspace(1)* noalias %in) nounwind {
-  %val = load <16 x i32> addrspace(1)* %in, align 32
+  %val = load <16 x i32>, <16 x i32> addrspace(1)* %in, align 32
   %ctpop = call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %val) nounwind readnone
   store <16 x i32> %ctpop, <16 x i32> addrspace(1)* %out, align 32
   ret void
 }
 
 ; FUNC-LABEL: {{^}}v_ctpop_i32_add_inline_constant:
-; SI: buffer_load_dword [[VAL:v[0-9]+]],
-; SI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
+; GCN: buffer_load_dword [[VAL:v[0-9]+]],
+; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
+; GCN: buffer_store_dword [[RESULT]],
+; GCN: s_endpgm
 
 ; EG: BCNT_INT
 define void @v_ctpop_i32_add_inline_constant(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
-  %val = load i32 addrspace(1)* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
   %add = add i32 %ctpop, 4
   store i32 %add, i32 addrspace(1)* %out, align 4
@@ -186,14 +188,14 @@ define void @v_ctpop_i32_add_inline_constant(i32 addrspace(1)* noalias %out, i32
 }
 
 ; FUNC-LABEL: {{^}}v_ctpop_i32_add_inline_constant_inv:
-; SI: buffer_load_dword [[VAL:v[0-9]+]],
-; SI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
+; GCN: buffer_load_dword [[VAL:v[0-9]+]],
+; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
+; GCN: buffer_store_dword [[RESULT]],
+; GCN: s_endpgm
 
 ; EG: BCNT_INT
 define void @v_ctpop_i32_add_inline_constant_inv(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
-  %val = load i32 addrspace(1)* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
   %add = add i32 4, %ctpop
   store i32 %add, i32 addrspace(1)* %out, align 4
@@ -201,13 +203,14 @@ define void @v_ctpop_i32_add_inline_constant_inv(i32 addrspace(1)* noalias %out,
 }
 
 ; FUNC-LABEL: {{^}}v_ctpop_i32_add_literal:
-; SI: buffer_load_dword [[VAL:v[0-9]+]],
-; SI: v_mov_b32_e32 [[LIT:v[0-9]+]], 0x1869f
+; GCN: buffer_load_dword [[VAL:v[0-9]+]],
+; GCN: v_mov_b32_e32 [[LIT:v[0-9]+]], 0x1869f
 ; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[LIT]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
+; VI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[LIT]]
+; GCN: buffer_store_dword [[RESULT]],
+; GCN: s_endpgm
 define void @v_ctpop_i32_add_literal(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
-  %val = load i32 addrspace(1)* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
   %add = add i32 %ctpop, 99999
   store i32 %add, i32 addrspace(1)* %out, align 4
@@ -215,15 +218,15 @@ define void @v_ctpop_i32_add_literal(i32 addrspace(1)* noalias %out, i32 addrspa
 }
 
 ; FUNC-LABEL: {{^}}v_ctpop_i32_add_var:
-; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]],
-; SI-DAG: s_load_dword [[VAR:s[0-9]+]],
-; SI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
+; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]],
+; GCN-DAG: s_load_dword [[VAR:s[0-9]+]],
+; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]]
+; GCN: buffer_store_dword [[RESULT]],
+; GCN: s_endpgm
 
 ; EG: BCNT_INT
 define void @v_ctpop_i32_add_var(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %const) nounwind {
-  %val = load i32 addrspace(1)* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
   %add = add i32 %ctpop, %const
   store i32 %add, i32 addrspace(1)* %out, align 4
@@ -231,15 +234,15 @@ define void @v_ctpop_i32_add_var(i32 addrspace(1)* noalias %out, i32 addrspace(1
 }
 
 ; FUNC-LABEL: {{^}}v_ctpop_i32_add_var_inv:
-; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]],
-; SI-DAG: s_load_dword [[VAR:s[0-9]+]],
-; SI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
+; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]],
+; GCN-DAG: s_load_dword [[VAR:s[0-9]+]],
+; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]]
+; GCN: buffer_store_dword [[RESULT]],
+; GCN: s_endpgm
 
 ; EG: BCNT_INT
 define void @v_ctpop_i32_add_var_inv(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %const) nounwind {
-  %val = load i32 addrspace(1)* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
   %add = add i32 %const, %ctpop
   store i32 %add, i32 addrspace(1)* %out, align 4
@@ -247,18 +250,19 @@ define void @v_ctpop_i32_add_var_inv(i32 addrspace(1)* noalias %out, i32 addrspa
 }
 
 ; FUNC-LABEL: {{^}}v_ctpop_i32_add_vvar_inv:
-; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], {{0$}}
-; SI-DAG: buffer_load_dword [[VAR:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0 offset:16
+; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], {{0$}}
+; GCN-DAG: buffer_load_dword [[VAR:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0 offset:16
 ; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
+; VI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]]
+; GCN: buffer_store_dword [[RESULT]],
+; GCN: s_endpgm
 
 ; EG: BCNT_INT
 define void @v_ctpop_i32_add_vvar_inv(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 addrspace(1)* noalias %constptr) nounwind {
-  %val = load i32 addrspace(1)* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
-  %gep = getelementptr i32 addrspace(1)* %constptr, i32 4
-  %const = load i32 addrspace(1)* %gep, align 4
+  %gep = getelementptr i32, i32 addrspace(1)* %constptr, i32 4
+  %const = load i32, i32 addrspace(1)* %gep, align 4
   %add = add i32 %const, %ctpop
   store i32 %add, i32 addrspace(1)* %out, align 4
   ret void
@@ -269,10 +273,11 @@ define void @v_ctpop_i32_add_vvar_inv(i32 addrspace(1)* noalias %out, i32 addrsp
 
 ; FUNC-LABEL: {{^}}ctpop_i32_in_br:
 ; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xd
-; SI: s_bcnt1_i32_b32  [[SRESULT:s[0-9]+]], [[VAL]]
-; SI: v_mov_b32_e32 [[RESULT]], [[SRESULT]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
+; VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x34
+; GCN: s_bcnt1_i32_b32  [[SRESULT:s[0-9]+]], [[VAL]]
+; GCN: v_mov_b32_e32 [[RESULT]], [[SRESULT]]
+; GCN: buffer_store_dword [[RESULT]],
+; GCN: s_endpgm
 ; EG: BCNT_INT
 define void @ctpop_i32_in_br(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %ctpop_arg, i32 %cond) {
 entry:
@@ -284,8 +289,8 @@ if:
   br label %endif
 
 else:
-  %tmp3 = getelementptr i32 addrspace(1)* %in, i32 1
-  %tmp4 = load i32 addrspace(1)* %tmp3
+  %tmp3 = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %tmp4 = load i32, i32 addrspace(1)* %tmp3
   br label %endif
 
 endif:
diff --git a/test/CodeGen/R600/ctpop64.ll b/test/CodeGen/R600/ctpop64.ll
index 9758ac96ea9b..e1a0ee3ea217 100644
--- a/test/CodeGen/R600/ctpop64.ll
+++ b/test/CodeGen/R600/ctpop64.ll
@@ -1,4 +1,5 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
 
 declare i64 @llvm.ctpop.i64(i64) nounwind readnone
 declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone
@@ -8,10 +9,11 @@ declare <16 x i64> @llvm.ctpop.v16i64(<16 x i64>) nounwind readnone
 
 ; FUNC-LABEL: {{^}}s_ctpop_i64:
 ; SI: s_load_dwordx2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI: s_bcnt1_i32_b64 [[SRESULT:s[0-9]+]], [[SVAL]]
-; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
-; SI: buffer_store_dword [[VRESULT]],
-; SI: s_endpgm
+; VI: s_load_dwordx2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; GCN: s_bcnt1_i32_b64 [[SRESULT:s[0-9]+]], [[SVAL]]
+; GCN: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
+; GCN: buffer_store_dword [[VRESULT]],
+; GCN: s_endpgm
 define void @s_ctpop_i64(i32 addrspace(1)* noalias %out, i64 %val) nounwind {
   %ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
   %truncctpop = trunc i64 %ctpop to i32
@@ -20,13 +22,14 @@ define void @s_ctpop_i64(i32 addrspace(1)* noalias %out, i64 %val) nounwind {
 }
 
 ; FUNC-LABEL: {{^}}v_ctpop_i64:
-; SI: buffer_load_dwordx2 v{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}},
-; SI: v_bcnt_u32_b32_e64 [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0
+; GCN: buffer_load_dwordx2 v{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}},
+; GCN: v_bcnt_u32_b32_e64 [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0
 ; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
+; VI-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
+; GCN: buffer_store_dword [[RESULT]],
+; GCN: s_endpgm
 define void @v_ctpop_i64(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind {
-  %val = load i64 addrspace(1)* %in, align 8
+  %val = load i64, i64 addrspace(1)* %in, align 8
   %ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
   %truncctpop = trunc i64 %ctpop to i32
   store i32 %truncctpop, i32 addrspace(1)* %out, align 4
@@ -34,9 +37,9 @@ define void @v_ctpop_i64(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noali
 }
 
 ; FUNC-LABEL: {{^}}s_ctpop_v2i64:
-; SI: s_bcnt1_i32_b64
-; SI: s_bcnt1_i32_b64
-; SI: s_endpgm
+; GCN: s_bcnt1_i32_b64
+; GCN: s_bcnt1_i32_b64
+; GCN: s_endpgm
 define void @s_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> %val) nounwind {
   %ctpop = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val) nounwind readnone
   %truncctpop = trunc <2 x i64> %ctpop to <2 x i32>
@@ -45,11 +48,11 @@ define void @s_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> %val)
 }
 
 ; FUNC-LABEL: {{^}}s_ctpop_v4i64:
-; SI: s_bcnt1_i32_b64
-; SI: s_bcnt1_i32_b64
-; SI: s_bcnt1_i32_b64
-; SI: s_bcnt1_i32_b64
-; SI: s_endpgm
+; GCN: s_bcnt1_i32_b64
+; GCN: s_bcnt1_i32_b64
+; GCN: s_bcnt1_i32_b64
+; GCN: s_bcnt1_i32_b64
+; GCN: s_endpgm
 define void @s_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> %val) nounwind {
   %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
   %truncctpop = trunc <4 x i64> %ctpop to <4 x i32>
@@ -58,13 +61,13 @@ define void @s_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> %val)
 }
 
 ; FUNC-LABEL: {{^}}v_ctpop_v2i64:
-; SI: v_bcnt_u32_b32
-; SI: v_bcnt_u32_b32
-; SI: v_bcnt_u32_b32
-; SI: v_bcnt_u32_b32
-; SI: s_endpgm
+; GCN: v_bcnt_u32_b32
+; GCN: v_bcnt_u32_b32
+; GCN: v_bcnt_u32_b32
+; GCN: v_bcnt_u32_b32
+; GCN: s_endpgm
 define void @v_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in) nounwind {
-  %val = load <2 x i64> addrspace(1)* %in, align 16
+  %val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
   %ctpop = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val) nounwind readnone
   %truncctpop = trunc <2 x i64> %ctpop to <2 x i32>
   store <2 x i32> %truncctpop, <2 x i32> addrspace(1)* %out, align 8
@@ -72,17 +75,17 @@ define void @v_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> addrs
 }
 
 ; FUNC-LABEL: {{^}}v_ctpop_v4i64:
-; SI: v_bcnt_u32_b32
-; SI: v_bcnt_u32_b32
-; SI: v_bcnt_u32_b32
-; SI: v_bcnt_u32_b32
-; SI: v_bcnt_u32_b32
-; SI: v_bcnt_u32_b32
-; SI: v_bcnt_u32_b32
-; SI: v_bcnt_u32_b32
-; SI: s_endpgm
+; GCN: v_bcnt_u32_b32
+; GCN: v_bcnt_u32_b32
+; GCN: v_bcnt_u32_b32
+; GCN: v_bcnt_u32_b32
+; GCN: v_bcnt_u32_b32
+; GCN: v_bcnt_u32_b32
+; GCN: v_bcnt_u32_b32
+; GCN: v_bcnt_u32_b32
+; GCN: s_endpgm
 define void @v_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> addrspace(1)* noalias %in) nounwind {
-  %val = load <4 x i64> addrspace(1)* %in, align 32
+  %val = load <4 x i64>, <4 x i64> addrspace(1)* %in, align 32
   %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
   %truncctpop = trunc <4 x i64> %ctpop to <4 x i32>
   store <4 x i32> %truncctpop, <4 x i32> addrspace(1)* %out, align 16
@@ -94,11 +97,12 @@ define void @v_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> addrs
 
 ; FUNC-LABEL: {{^}}ctpop_i64_in_br:
 ; SI: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xd
-; SI: s_bcnt1_i32_b64 [[RESULT:s[0-9]+]], {{s\[}}[[LOVAL]]:[[HIVAL]]{{\]}}
-; SI: v_mov_b32_e32 v[[VLO:[0-9]+]], [[RESULT]]
-; SI: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[HIVAL]]
-; SI: buffer_store_dwordx2 {{v\[}}[[VLO]]:[[VHI]]{{\]}}
-; SI: s_endpgm
+; VI: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x34
+; GCN: s_bcnt1_i32_b64 [[RESULT:s[0-9]+]], {{s\[}}[[LOVAL]]:[[HIVAL]]{{\]}}
+; GCN: v_mov_b32_e32 v[[VLO:[0-9]+]], [[RESULT]]
+; GCN: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[HIVAL]]
+; GCN: buffer_store_dwordx2 {{v\[}}[[VLO]]:[[VHI]]{{\]}}
+; GCN: s_endpgm
 define void @ctpop_i64_in_br(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %ctpop_arg, i32 %cond) {
 entry:
   %tmp0 = icmp eq i32 %cond, 0
@@ -109,8 +113,8 @@ if:
   br label %endif
 
 else:
-  %tmp3 = getelementptr i64 addrspace(1)* %in, i32 1
-  %tmp4 = load i64 addrspace(1)* %tmp3
+  %tmp3 = getelementptr i64, i64 addrspace(1)* %in, i32 1
+  %tmp4 = load i64, i64 addrspace(1)* %tmp3
   br label %endif
 
 endif:
diff --git a/test/CodeGen/R600/cttz-ctlz.ll b/test/CodeGen/R600/cttz-ctlz.ll
deleted file mode 100644
index c957a033c5d7..000000000000
--- a/test/CodeGen/R600/cttz-ctlz.ll
+++ /dev/null
@@ -1,225 +0,0 @@
-; RUN: opt -S -codegenprepare -mtriple=r600-unknown-unknown -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=ALL %s
-; RUN: opt -S -codegenprepare -mtriple=r600-unknown-unknown -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=ALL %s
-
-
-define i64 @test1(i64 %A) {
-; ALL-LABEL: @test1(
-; SI: [[CTLZ:%[A-Za-z0-9]+]] = call i64 @llvm.ctlz.i64(i64 %A, i1 false)
-; SI-NEXT: ret i64 [[CTLZ]]
-entry:
-  %tobool = icmp eq i64 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i64 [ %0, %cond.true ], [ 64, %entry ]
-  ret i64 %cond
-}
-
-
-define i32 @test2(i32 %A) {
-; ALL-LABEL: @test2(
-; SI: [[CTLZ:%[A-Za-z0-9]+]] = call i32 @llvm.ctlz.i32(i32 %A, i1 false)
-; SI-NEXT: ret i32 [[CTLZ]]
-entry:
-  %tobool = icmp eq i32 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i32 [ %0, %cond.true ], [ 32, %entry ]
-  ret i32 %cond
-}
-
-
-define signext i16 @test3(i16 signext %A) {
-; ALL-LABEL: @test3(
-; SI: [[CTLZ:%[A-Za-z0-9]+]] = call i16 @llvm.ctlz.i16(i16 %A, i1 false)
-; SI-NEXT: ret i16 [[CTLZ]]
-entry:
-  %tobool = icmp eq i16 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i16 [ %0, %cond.true ], [ 16, %entry ]
-  ret i16 %cond
-}
-
-
-define i64 @test1b(i64 %A) {
-; ALL-LABEL: @test1b(
-; SI: [[CTTZ:%[A-Za-z0-9]+]] = call i64 @llvm.cttz.i64(i64 %A, i1 false)
-; SI-NEXT: ret i64 [[CTTZ]]
-entry:
-  %tobool = icmp eq i64 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i64 [ %0, %cond.true ], [ 64, %entry ]
-  ret i64 %cond
-}
-
-
-define i32 @test2b(i32 %A) {
-; ALL-LABEL: @test2b(
-; SI: [[CTTZ:%[A-Za-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %A, i1 false)
-; SI-NEXT: ret i32 [[CTTZ]]
-entry:
-  %tobool = icmp eq i32 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i32 [ %0, %cond.true ], [ 32, %entry ]
-  ret i32 %cond
-}
-
-
-define signext i16 @test3b(i16 signext %A) {
-; ALL-LABEL: @test3b(
-; SI: [[CTTZ:%[A-Za-z0-9]+]] = call i16 @llvm.cttz.i16(i16 %A, i1 false)
-; SI-NEXT: ret i16 [[CTTZ]]
-entry:
-  %tobool = icmp eq i16 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i16 [ %0, %cond.true ], [ 16, %entry ]
-  ret i16 %cond
-}
-
-
-define i64 @test1c(i64 %A) {
-; ALL-LABEL: @test1c(
-; ALL: icmp eq i64 %A, 0
-; ALL: call i64 @llvm.ctlz.i64(i64 %A, i1 true)
-entry:
-  %tobool = icmp eq i64 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i64 [ %0, %cond.true ], [ 63, %entry ]
-  ret i64 %cond
-}
-
-define i32 @test2c(i32 %A) {
-; ALL-LABEL: @test2c(
-; ALL: icmp eq i32 %A, 0
-; ALL: call i32 @llvm.ctlz.i32(i32 %A, i1 true)
-entry:
-  %tobool = icmp eq i32 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i32 [ %0, %cond.true ], [ 31, %entry ]
-  ret i32 %cond
-}
-
-
-define signext i16 @test3c(i16 signext %A) {
-; ALL-LABEL: @test3c(
-; ALL: icmp eq i16 %A, 0
-; ALL: call i16 @llvm.ctlz.i16(i16 %A, i1 true)
-entry:
-  %tobool = icmp eq i16 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i16 [ %0, %cond.true ], [ 15, %entry ]
-  ret i16 %cond
-}
-
-
-define i64 @test1d(i64 %A) {
-; ALL-LABEL: @test1d(
-; ALL: icmp eq i64 %A, 0
-; ALL: call i64 @llvm.cttz.i64(i64 %A, i1 true)
-entry:
-  %tobool = icmp eq i64 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i64 [ %0, %cond.true ], [ 63, %entry ]
-  ret i64 %cond
-}
-
-
-define i32 @test2d(i32 %A) {
-; ALL-LABEL: @test2d(
-; ALL: icmp eq i32 %A, 0
-; ALL: call i32 @llvm.cttz.i32(i32 %A, i1 true)
-entry:
-  %tobool = icmp eq i32 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i32 [ %0, %cond.true ], [ 31, %entry ]
-  ret i32 %cond
-}
-
-
-define signext i16 @test3d(i16 signext %A) {
-; ALL-LABEL: @test3d(
-; ALL: icmp eq i16 %A, 0
-; ALL: call i16 @llvm.cttz.i16(i16 %A, i1 true)
-entry:
-  %tobool = icmp eq i16 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i16 [ %0, %cond.true ], [ 15, %entry ]
-  ret i16 %cond
-}
-
-
-declare i64 @llvm.ctlz.i64(i64, i1)
-declare i32 @llvm.ctlz.i32(i32, i1)
-declare i16 @llvm.ctlz.i16(i16, i1)
-declare i64 @llvm.cttz.i64(i64, i1)
-declare i32 @llvm.cttz.i32(i32, i1)
-declare i16 @llvm.cttz.i16(i16, i1)
diff --git a/test/CodeGen/R600/cttz_zero_undef.ll b/test/CodeGen/R600/cttz_zero_undef.ll
index d9d284c58865..56fcb51fe14e 100644
--- a/test/CodeGen/R600/cttz_zero_undef.ll
+++ b/test/CodeGen/R600/cttz_zero_undef.ll
@@ -28,7 +28,7 @@ define void @s_cttz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nou
 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
 define void @v_cttz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
-  %val = load i32 addrspace(1)* %valptr, align 4
+  %val = load i32, i32 addrspace(1)* %valptr, align 4
   %cttz = call i32 @llvm.cttz.i32(i32 %val, i1 true) nounwind readnone
   store i32 %cttz, i32 addrspace(1)* %out, align 4
   ret void
@@ -44,7 +44,7 @@ define void @v_cttz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace
 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
 define void @v_cttz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind {
-  %val = load <2 x i32> addrspace(1)* %valptr, align 8
+  %val = load <2 x i32>, <2 x i32> addrspace(1)* %valptr, align 8
   %cttz = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %val, i1 true) nounwind readnone
   store <2 x i32> %cttz, <2 x i32> addrspace(1)* %out, align 8
   ret void
@@ -64,7 +64,7 @@ define void @v_cttz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x
 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
 define void @v_cttz_zero_undef_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind {
-  %val = load <4 x i32> addrspace(1)* %valptr, align 16
+  %val = load <4 x i32>, <4 x i32> addrspace(1)* %valptr, align 16
   %cttz = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %val, i1 true) nounwind readnone
   store <4 x i32> %cttz, <4 x i32> addrspace(1)* %out, align 16
   ret void
diff --git a/test/CodeGen/R600/cvt_f32_ubyte.ll b/test/CodeGen/R600/cvt_f32_ubyte.ll
index 69eea5919c05..3399d9da29e3 100644
--- a/test/CodeGen/R600/cvt_f32_ubyte.ll
+++ b/test/CodeGen/R600/cvt_f32_ubyte.ll
@@ -8,7 +8,7 @@
 ; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]]
 ; SI: buffer_store_dword [[CONV]],
 define void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
-  %load = load i8 addrspace(1)* %in, align 1
+  %load = load i8, i8 addrspace(1)* %in, align 1
   %cvt = uitofp i8 %load to float
   store float %cvt, float addrspace(1)* %out, align 4
   ret void
@@ -23,7 +23,7 @@ define void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* n
 ; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]]
 ; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
 define void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> addrspace(1)* noalias %in) nounwind {
-  %load = load <2 x i8> addrspace(1)* %in, align 2
+  %load = load <2 x i8>, <2 x i8> addrspace(1)* %in, align 2
   %cvt = uitofp <2 x i8> %load to <2 x float>
   store <2 x float> %cvt, <2 x float> addrspace(1)* %out, align 16
   ret void
@@ -37,7 +37,7 @@ define void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8>
 ; SI-DAG: v_cvt_f32_ubyte0_e32
 ; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
 define void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> addrspace(1)* noalias %in) nounwind {
-  %load = load <3 x i8> addrspace(1)* %in, align 4
+  %load = load <3 x i8>, <3 x i8> addrspace(1)* %in, align 4
   %cvt = uitofp <3 x i8> %load to <3 x float>
   store <3 x float> %cvt, <3 x float> addrspace(1)* %out, align 16
   ret void
@@ -53,7 +53,7 @@ define void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8>
 ; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]]
 ; SI: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
 define void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
-  %load = load <4 x i8> addrspace(1)* %in, align 4
+  %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
   %cvt = uitofp <4 x i8> %load to <4 x float>
   store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
   ret void
@@ -63,10 +63,10 @@ define void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8>
 ; position in the word for the component.
 
 ; SI-LABEL: {{^}}load_v4i8_to_v4f32_unaligned:
-; SI: buffer_load_ubyte [[LOADREG0:v[0-9]+]]
-; SI: buffer_load_ubyte [[LOADREG1:v[0-9]+]]
-; SI: buffer_load_ubyte [[LOADREG2:v[0-9]+]]
 ; SI: buffer_load_ubyte [[LOADREG3:v[0-9]+]]
+; SI: buffer_load_ubyte [[LOADREG2:v[0-9]+]]
+; SI: buffer_load_ubyte [[LOADREG1:v[0-9]+]]
+; SI: buffer_load_ubyte [[LOADREG0:v[0-9]+]]
 ; SI-NOT: v_lshlrev_b32
 ; SI-NOT: v_or_b32
 
@@ -77,7 +77,7 @@ define void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8>
 
 ; SI: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
 define void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
-  %load = load <4 x i8> addrspace(1)* %in, align 1
+  %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 1
   %cvt = uitofp <4 x i8> %load to <4 x float>
   store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
   ret void
@@ -105,7 +105,7 @@ define void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1)* noalias %out
 ; XSI: v_cvt_f32_u32_e32
 ; SI: s_endpgm
 define void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind {
-  %load = load <4 x i8> addrspace(1)* %in, align 4
+  %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
   %cvt = uitofp <4 x i8> %load to <4 x float>
   store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
   %add = add <4 x i8> %load, <i8 9, i8 9, i8 9, i8 9> ; Second use of %load
@@ -117,7 +117,7 @@ define void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <
 ; SI-LABEL: {{^}}load_v7i8_to_v7f32:
 ; SI: s_endpgm
 define void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> addrspace(1)* noalias %in) nounwind {
-  %load = load <7 x i8> addrspace(1)* %in, align 1
+  %load = load <7 x i8>, <7 x i8> addrspace(1)* %in, align 1
   %cvt = uitofp <7 x i8> %load to <7 x float>
   store <7 x float> %cvt, <7 x float> addrspace(1)* %out, align 16
   ret void
@@ -146,7 +146,7 @@ define void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8>
 ; SI: buffer_store_dword
 ; SI: buffer_store_dword
 define void @load_v8i8_to_v8f32(<8 x float> addrspace(1)* noalias %out, <8 x i8> addrspace(1)* noalias %in) nounwind {
-  %load = load <8 x i8> addrspace(1)* %in, align 8
+  %load = load <8 x i8>, <8 x i8> addrspace(1)* %in, align 8
   %cvt = uitofp <8 x i8> %load to <8 x float>
   store <8 x float> %cvt, <8 x float> addrspace(1)* %out, align 16
   ret void
@@ -158,7 +158,7 @@ define void @load_v8i8_to_v8f32(<8 x float> addrspace(1)* noalias %out, <8 x i8>
 ; SI-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]]
 ; SI: buffer_store_dword [[CONV]],
 define void @i8_zext_inreg_i32_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
-  %load = load i32 addrspace(1)* %in, align 4
+  %load = load i32, i32 addrspace(1)* %in, align 4
   %add = add i32 %load, 2
   %inreg = and i32 %add, 255
   %cvt = uitofp i32 %inreg to float
@@ -168,7 +168,7 @@ define void @i8_zext_inreg_i32_to_f32(float addrspace(1)* noalias %out, i32 addr
 
 ; SI-LABEL: {{^}}i8_zext_inreg_hi1_to_f32:
 define void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
-  %load = load i32 addrspace(1)* %in, align 4
+  %load = load i32, i32 addrspace(1)* %in, align 4
   %inreg = and i32 %load, 65280
   %shr = lshr i32 %inreg, 8
   %cvt = uitofp i32 %shr to float
@@ -180,7 +180,7 @@ define void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias %out, i32 addr
 ; We don't get these ones because of the zext, but instcombine removes
 ; them so it shouldn't really matter.
 define void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
-  %load = load i8 addrspace(1)* %in, align 1
+  %load = load i8, i8 addrspace(1)* %in, align 1
   %ext = zext i8 %load to i32
   %cvt = uitofp i32 %ext to float
   store float %cvt, float addrspace(1)* %out, align 4
@@ -188,7 +188,7 @@ define void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1
 }
 
 define void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
-  %load = load <4 x i8> addrspace(1)* %in, align 1
+  %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 1
   %ext = zext <4 x i8> %load to <4 x i32>
   %cvt = uitofp <4 x i32> %ext to <4 x float>
   store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
diff --git a/test/CodeGen/R600/cvt_flr_i32_f32.ll b/test/CodeGen/R600/cvt_flr_i32_f32.ll
new file mode 100644
index 000000000000..2dd3a9f2a776
--- /dev/null
+++ b/test/CodeGen/R600/cvt_flr_i32_f32.ll
@@ -0,0 +1,86 @@
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+
+declare float @llvm.fabs.f32(float) #1
+declare float @llvm.floor.f32(float) #1
+
+; FUNC-LABEL: {{^}}cvt_flr_i32_f32_0:
+; SI-SAFE-NOT: v_cvt_flr_i32_f32
+; SI-NOT: add
+; SI-NONAN: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
+; SI: s_endpgm
+define void @cvt_flr_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
+  %floor = call float @llvm.floor.f32(float %x) #1
+  %cvt = fptosi float %floor to i32
+  store i32 %cvt, i32 addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}cvt_flr_i32_f32_1:
+; SI: v_add_f32_e64 [[TMP:v[0-9]+]], 1.0, s{{[0-9]+}}
+; SI-SAFE-NOT: v_cvt_flr_i32_f32
+; SI-NONAN: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, [[TMP]]
+; SI: s_endpgm
+define void @cvt_flr_i32_f32_1(i32 addrspace(1)* %out, float %x) #0 {
+  %fadd = fadd float %x, 1.0
+  %floor = call float @llvm.floor.f32(float %fadd) #1
+  %cvt = fptosi float %floor to i32
+  store i32 %cvt, i32 addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs:
+; SI-NOT: add
+; SI-SAFE-NOT: v_cvt_flr_i32_f32
+; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|
+; SI: s_endpgm
+define void @cvt_flr_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
+  %x.fabs = call float @llvm.fabs.f32(float %x) #1
+  %floor = call float @llvm.floor.f32(float %x.fabs) #1
+  %cvt = fptosi float %floor to i32
+  store i32 %cvt, i32 addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fneg:
+; SI-NOT: add
+; SI-SAFE-NOT: v_cvt_flr_i32_f32
+; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
+; SI: s_endpgm
+define void @cvt_flr_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
+  %x.fneg = fsub float -0.000000e+00, %x
+  %floor = call float @llvm.floor.f32(float %x.fneg) #1
+  %cvt = fptosi float %floor to i32
+  store i32 %cvt, i32 addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs_fneg:
+; SI-NOT: add
+; SI-SAFE-NOT: v_cvt_flr_i32_f32
+; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
+; SI: s_endpgm
+define void @cvt_flr_i32_f32_fabs_fneg(i32 addrspace(1)* %out, float %x) #0 {
+  %x.fabs = call float @llvm.fabs.f32(float %x) #1
+  %x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
+  %floor = call float @llvm.floor.f32(float %x.fabs.fneg) #1
+  %cvt = fptosi float %floor to i32
+  store i32 %cvt, i32 addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}no_cvt_flr_i32_f32_0:
+; SI-NOT: v_cvt_flr_i32_f32
+; SI: v_floor_f32
+; SI: v_cvt_u32_f32_e32
+; SI: s_endpgm
+define void @no_cvt_flr_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
+  %floor = call float @llvm.floor.f32(float %x) #1
+  %cvt = fptoui float %floor to i32
+  store i32 %cvt, i32 addrspace(1)* %out
+  ret void
+}
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
diff --git a/test/CodeGen/R600/cvt_rpi_i32_f32.ll b/test/CodeGen/R600/cvt_rpi_i32_f32.ll
new file mode 100644
index 000000000000..864ac40260b3
--- /dev/null
+++ b/test/CodeGen/R600/cvt_rpi_i32_f32.ll
@@ -0,0 +1,83 @@
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
+
+declare float @llvm.fabs.f32(float) #1
+declare float @llvm.floor.f32(float) #1
+
+; FUNC-LABEL: {{^}}cvt_rpi_i32_f32:
+; SI-SAFE-NOT: v_cvt_rpi_i32_f32
+; SI-NONAN: v_cvt_rpi_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
+; SI: s_endpgm
+define void @cvt_rpi_i32_f32(i32 addrspace(1)* %out, float %x) #0 {
+  %fadd = fadd float %x, 0.5
+  %floor = call float @llvm.floor.f32(float %fadd) #1
+  %cvt = fptosi float %floor to i32
+  store i32 %cvt, i32 addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs:
+; SI-SAFE-NOT: v_cvt_rpi_i32_f32
+; SI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|{{$}}
+; SI: s_endpgm
+define void @cvt_rpi_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
+  %x.fabs = call float @llvm.fabs.f32(float %x) #1
+  %fadd = fadd float %x.fabs, 0.5
+  %floor = call float @llvm.floor.f32(float %fadd) #1
+  %cvt = fptosi float %floor to i32
+  store i32 %cvt, i32 addrspace(1)* %out
+  ret void
+}
+
+; FIXME: This doesn't work because it forms fsub 0.5, x
+; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fneg:
+; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
+; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, s{{[0-9]+}}
+; SI-SAFE-NOT: v_cvt_flr_i32_f32
+; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
+; SI: s_endpgm
+define void @cvt_rpi_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
+  %x.fneg = fsub float -0.000000e+00, %x
+  %fadd = fadd float %x.fneg, 0.5
+  %floor = call float @llvm.floor.f32(float %fadd) #1
+  %cvt = fptosi float %floor to i32
+  store i32 %cvt, i32 addrspace(1)* %out
+  ret void
+}
+
+; FIXME: This doesn't work for same reason as above
+; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs_fneg:
+; SI-SAFE-NOT: v_cvt_rpi_i32_f32
+; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
+
+; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, |s{{[0-9]+}}|
+; SI-SAFE-NOT: v_cvt_flr_i32_f32
+; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
+; SI: s_endpgm
+define void @cvt_rpi_i32_f32_fabs_fneg(i32 addrspace(1)* %out, float %x) #0 {
+  %x.fabs = call float @llvm.fabs.f32(float %x) #1
+  %x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
+  %fadd = fadd float %x.fabs.fneg, 0.5
+  %floor = call float @llvm.floor.f32(float %fadd) #1
+  %cvt = fptosi float %floor to i32
+  store i32 %cvt, i32 addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}no_cvt_rpi_i32_f32_0:
+; SI-NOT: v_cvt_rpi_i32_f32
+; SI: v_add_f32
+; SI: v_floor_f32
+; SI: v_cvt_u32_f32
+; SI: s_endpgm
+define void @no_cvt_rpi_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
+  %fadd = fadd float %x, 0.5
+  %floor = call float @llvm.floor.f32(float %fadd) #1
+  %cvt = fptoui float %floor to i32
+  store i32 %cvt, i32 addrspace(1)* %out
+  ret void
+}
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
diff --git a/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll b/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll
index 1e47bfa0c779..fb43ff4fbddd 100644
--- a/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll
+++ b/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll
@@ -12,8 +12,8 @@
 
 define void @sint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %sint = load i32 addrspace(1) * %in
+  %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %sint = load i32, i32 addrspace(1) * %in
   %conv = sitofp i32 %sint to float
   %0 = insertelement <4 x float> undef, float %conv, i32 0
   %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
@@ -26,8 +26,8 @@ entry:
 
 define void @uint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %uint = load i32 addrspace(1) * %in
+  %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %uint = load i32, i32 addrspace(1) * %in
   %conv = uitofp i32 %uint to float
   %0 = insertelement <4 x float> undef, float %conv, i32 0
   %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
diff --git a/test/CodeGen/R600/debug.ll b/test/CodeGen/R600/debug.ll
new file mode 100644
index 000000000000..a2e0e878b740
--- /dev/null
+++ b/test/CodeGen/R600/debug.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI --check-prefix=FUNC %s
+; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI --check-prefix=FUNC %s
+
+; Test for a crash in the custom assembly dump code.
+
+; SI: s_endpgm
+define void @test(i32 addrspace(1)* %out) {
+  store i32 0, i32 addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/disconnected-predset-break-bug.ll b/test/CodeGen/R600/disconnected-predset-break-bug.ll
index 858e4b98f3ab..cdd2c0cd4f43 100644
--- a/test/CodeGen/R600/disconnected-predset-break-bug.ll
+++ b/test/CodeGen/R600/disconnected-predset-break-bug.ll
@@ -18,7 +18,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.07.in = phi i32 [ %i.07, %for.body ], [ %iterations, %entry ]
   %ai.06 = phi i32 [ %add, %for.body ], [ 0, %entry ]
   %i.07 = add nsw i32 %i.07.in, -1
-  %arrayidx = getelementptr inbounds i32 addrspace(1)* %out, i32 %ai.06
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %ai.06
   store i32 %i.07, i32 addrspace(1)* %arrayidx, align 4
   %add = add nsw i32 %ai.06, 1
   %exitcond = icmp eq i32 %add, %iterations
diff --git a/test/CodeGen/R600/dot4-folding.ll b/test/CodeGen/R600/dot4-folding.ll
index dca6a59c6e6a..4df7b63bf98e 100644
--- a/test/CodeGen/R600/dot4-folding.ll
+++ b/test/CodeGen/R600/dot4-folding.ll
@@ -14,8 +14,8 @@
 
 define void @main(float addrspace(1)* %out) {
 main_body:
-  %0 = load <4 x float> addrspace(8)* null
-  %1 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %0 = load <4 x float>, <4 x float> addrspace(8)* null
+  %1 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %2 = call float @llvm.AMDGPU.dp4(<4 x float> %0,<4 x float> %1)
   %3 = insertelement <4 x float> undef, float %2, i32 0
   call void @llvm.R600.store.swizzle(<4 x float> %3, i32 0, i32 0)
diff --git a/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll b/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll
index 41afd503ef88..e7e13d6178c4 100644
--- a/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll
+++ b/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll
@@ -18,7 +18,7 @@ declare void @llvm.AMDGPU.barrier.local() #1
 ; SI-DAG: v_add_i32_e32 [[VADDR0x100:v[0-9]+]], 0x100, [[VADDR]]
 ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x100]]
 
-; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:0 offset1:1
+; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset1:1
 ; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:32 offset1:33
 ; CI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]] offset:256
 ; CHECK: s_endpgm
@@ -33,20 +33,20 @@ for.body:                                         ; preds = %for.body, %entry
   %offset.02 = phi i32 [ %mul, %entry ], [ %add14, %for.body ]
   %k.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   tail call void @llvm.AMDGPU.barrier.local() #1
-  %arrayidx = getelementptr inbounds float addrspace(3)* %lptr, i32 %offset.02
-  %tmp = load float addrspace(3)* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %offset.02
+  %tmp = load float, float addrspace(3)* %arrayidx, align 4
   %add1 = add nsw i32 %offset.02, 1
-  %arrayidx2 = getelementptr inbounds float addrspace(3)* %lptr, i32 %add1
-  %tmp1 = load float addrspace(3)* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add1
+  %tmp1 = load float, float addrspace(3)* %arrayidx2, align 4
   %add3 = add nsw i32 %offset.02, 32
-  %arrayidx4 = getelementptr inbounds float addrspace(3)* %lptr, i32 %add3
-  %tmp2 = load float addrspace(3)* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add3
+  %tmp2 = load float, float addrspace(3)* %arrayidx4, align 4
   %add5 = add nsw i32 %offset.02, 33
-  %arrayidx6 = getelementptr inbounds float addrspace(3)* %lptr, i32 %add5
-  %tmp3 = load float addrspace(3)* %arrayidx6, align 4
+  %arrayidx6 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add5
+  %tmp3 = load float, float addrspace(3)* %arrayidx6, align 4
   %add7 = add nsw i32 %offset.02, 64
-  %arrayidx8 = getelementptr inbounds float addrspace(3)* %lptr, i32 %add7
-  %tmp4 = load float addrspace(3)* %arrayidx8, align 4
+  %arrayidx8 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add7
+  %tmp4 = load float, float addrspace(3)* %arrayidx8, align 4
   %add9 = fadd float %tmp, %tmp1
   %add10 = fadd float %add9, %tmp2
   %add11 = fadd float %add10, %tmp3
@@ -59,7 +59,7 @@ for.body:                                         ; preds = %for.body, %entry
 
 for.end:                                          ; preds = %for.body
   %tmp5 = sext i32 %x.i to i64
-  %arrayidx15 = getelementptr inbounds float addrspace(1)* %out, i64 %tmp5
+  %arrayidx15 = getelementptr inbounds float, float addrspace(1)* %out, i64 %tmp5
   store float %add13, float addrspace(1)* %arrayidx15, align 4
   ret void
 }
diff --git a/test/CodeGen/R600/ds_read2.ll b/test/CodeGen/R600/ds_read2.ll
index c06b0b1392e2..5929898f8bd8 100644
--- a/test/CodeGen/R600/ds_read2.ll
+++ b/test/CodeGen/R600/ds_read2.ll
@@ -7,39 +7,39 @@
  @lds.f64 = addrspace(3) global [512 x double] undef, align 8
 
 ; SI-LABEL: @simple_read2_f32
-; SI: ds_read2_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:0 offset1:8
+; SI: ds_read2_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:8
 ; SI: s_waitcnt lgkmcnt(0)
 ; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
 ; SI: buffer_store_dword [[RESULT]]
 ; SI: s_endpgm
 define void @simple_read2_f32(float addrspace(1)* %out) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
-  %val1 = load float addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
 
 ; SI-LABEL: @simple_read2_f32_max_offset
-; SI: ds_read2_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:0 offset1:255
+; SI: ds_read2_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:255
 ; SI: s_waitcnt lgkmcnt(0)
 ; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
 ; SI: buffer_store_dword [[RESULT]]
 ; SI: s_endpgm
 define void @simple_read2_f32_max_offset(float addrspace(1)* %out) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 255
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
-  %val1 = load float addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -51,77 +51,77 @@ define void @simple_read2_f32_max_offset(float addrspace(1)* %out) #0 {
 ; SI: s_endpgm
 define void @simple_read2_f32_too_far(float addrspace(1)* %out) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 257
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
-  %val1 = load float addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
 
 ; SI-LABEL: @simple_read2_f32_x2
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset0:0 offset1:8
+; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset1:8
 ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27
 ; SI: s_endpgm
 define void @simple_read2_f32_x2(float addrspace(1)* %out) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 0
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
 
   %idx.1 = add nsw i32 %tid.x, 8
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
-  %val1 = load float addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
   %sum.0 = fadd float %val0, %val1
 
   %idx.2 = add nsw i32 %tid.x, 11
-  %arrayidx2 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
-  %val2 = load float addrspace(3)* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
+  %val2 = load float, float addrspace(3)* %arrayidx2, align 4
 
   %idx.3 = add nsw i32 %tid.x, 27
-  %arrayidx3 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
-  %val3 = load float addrspace(3)* %arrayidx3, align 4
+  %arrayidx3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
+  %val3 = load float, float addrspace(3)* %arrayidx3, align 4
   %sum.1 = fadd float %val2, %val3
 
   %sum = fadd float %sum.0, %sum.1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %idx.0
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %idx.0
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
 
 ; Make sure there is an instruction between the two sets of reads.
 ; SI-LABEL: @simple_read2_f32_x2_barrier
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset0:0 offset1:8
+; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset1:8
 ; SI: s_barrier
 ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27
 ; SI: s_endpgm
 define void @simple_read2_f32_x2_barrier(float addrspace(1)* %out) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 0
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
 
   %idx.1 = add nsw i32 %tid.x, 8
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
-  %val1 = load float addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
   %sum.0 = fadd float %val0, %val1
 
   call void @llvm.AMDGPU.barrier.local() #2
 
   %idx.2 = add nsw i32 %tid.x, 11
-  %arrayidx2 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
-  %val2 = load float addrspace(3)* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
+  %val2 = load float, float addrspace(3)* %arrayidx2, align 4
 
   %idx.3 = add nsw i32 %tid.x, 27
-  %arrayidx3 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
-  %val3 = load float addrspace(3)* %arrayidx3, align 4
+  %arrayidx3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
+  %val3 = load float, float addrspace(3)* %arrayidx3, align 4
   %sum.1 = fadd float %val2, %val3
 
   %sum = fadd float %sum.0, %sum.1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %idx.0
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %idx.0
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -136,25 +136,25 @@ define void @simple_read2_f32_x2_barrier(float addrspace(1)* %out) #0 {
 define void @simple_read2_f32_x2_nonzero_base(float addrspace(1)* %out) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 2
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
 
   %idx.1 = add nsw i32 %tid.x, 8
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
-  %val1 = load float addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
   %sum.0 = fadd float %val0, %val1
 
   %idx.2 = add nsw i32 %tid.x, 11
-  %arrayidx2 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
-  %val2 = load float addrspace(3)* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
+  %val2 = load float, float addrspace(3)* %arrayidx2, align 4
 
   %idx.3 = add nsw i32 %tid.x, 27
-  %arrayidx3 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
-  %val3 = load float addrspace(3)* %arrayidx3, align 4
+  %arrayidx3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
+  %val3 = load float, float addrspace(3)* %arrayidx3, align 4
   %sum.1 = fadd float %val2, %val3
 
   %sum = fadd float %sum.0, %sum.1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %idx.0
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %idx.0
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -174,14 +174,14 @@ define void @read2_ptr_is_subreg_arg_f32(float addrspace(1)* %out, <2 x float ad
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
   %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0
   %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0
-  %gep = getelementptr inbounds <2 x float addrspace(3)*> %lds.ptr, <2 x i32> %index.1
+  %gep = getelementptr inbounds float, <2 x float addrspace(3)*> %lds.ptr, <2 x i32> %index.1
   %gep.0 = extractelement <2 x float addrspace(3)*> %gep, i32 0
   %gep.1 = extractelement <2 x float addrspace(3)*> %gep, i32 1
-  %val0 = load float addrspace(3)* %gep.0, align 4
-  %val1 = load float addrspace(3)* %gep.1, align 4
+  %val0 = load float, float addrspace(3)* %gep.0, align 4
+  %val1 = load float, float addrspace(3)* %gep.1, align 4
   %add.x = add nsw i32 %x.i, 8
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -200,18 +200,18 @@ define void @read2_ptr_is_subreg_arg_offset_f32(float addrspace(1)* %out, <2 x f
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
   %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0
   %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0
-  %gep = getelementptr inbounds <2 x float addrspace(3)*> %lds.ptr, <2 x i32> %index.1
+  %gep = getelementptr inbounds float, <2 x float addrspace(3)*> %lds.ptr, <2 x i32> %index.1
   %gep.0 = extractelement <2 x float addrspace(3)*> %gep, i32 0
   %gep.1 = extractelement <2 x float addrspace(3)*> %gep, i32 1
 
   ; Apply an additional offset after the vector that will be more obviously folded.
-  %gep.1.offset = getelementptr float addrspace(3)* %gep.1, i32 8
+  %gep.1.offset = getelementptr float, float addrspace(3)* %gep.1, i32 8
 
-  %val0 = load float addrspace(3)* %gep.0, align 4
-  %val1 = load float addrspace(3)* %gep.1.offset, align 4
+  %val0 = load float, float addrspace(3)* %gep.0, align 4
+  %val1 = load float, float addrspace(3)* %gep.1.offset, align 4
   %add.x = add nsw i32 %x.i, 8
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -228,14 +228,14 @@ define void @read2_ptr_is_subreg_f32(float addrspace(1)* %out) #0 {
   %x.i.v.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0
   %x.i.v.1 = insertelement <2 x i32> %x.i.v.0, i32 %x.i, i32 1
   %idx = add <2 x i32> %x.i.v.1, <i32 0, i32 8>
-  %gep = getelementptr inbounds <2 x [512 x float] addrspace(3)*> %ptr.1, <2 x i32> <i32 0, i32 0>, <2 x i32> %idx
+  %gep = getelementptr inbounds [512 x float], <2 x [512 x float] addrspace(3)*> %ptr.1, <2 x i32> <i32 0, i32 0>, <2 x i32> %idx
   %gep.0 = extractelement <2 x float addrspace(3)*> %gep, i32 0
   %gep.1 = extractelement <2 x float addrspace(3)*> %gep, i32 1
-  %val0 = load float addrspace(3)* %gep.0, align 4
-  %val1 = load float addrspace(3)* %gep.1, align 4
+  %val0 = load float, float addrspace(3)* %gep.0, align 4
+  %val1 = load float, float addrspace(3)* %gep.1, align 4
   %add.x = add nsw i32 %x.i, 8
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -247,13 +247,13 @@ define void @read2_ptr_is_subreg_f32(float addrspace(1)* %out) #0 {
 ; SI: s_endpgm
 define void @simple_read2_f32_volatile_0(float addrspace(1)* %out) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
-  %val0 = load volatile float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %val0 = load volatile float, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
-  %val1 = load float addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -265,13 +265,13 @@ define void @simple_read2_f32_volatile_0(float addrspace(1)* %out) #0 {
 ; SI: s_endpgm
 define void @simple_read2_f32_volatile_1(float addrspace(1)* %out) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
-  %val1 = load volatile float addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %val1 = load volatile float, float addrspace(3)* %arrayidx1, align 4
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -284,13 +284,13 @@ define void @simple_read2_f32_volatile_1(float addrspace(1)* %out) #0 {
 ; SI: s_endpgm
 define void @unaligned_read2_f32(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds float addrspace(3)* %lds, i32 %x.i
-  %val0 = load float addrspace(3)* %arrayidx0, align 1
+  %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %x.i
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 1
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x
-  %val1 = load float addrspace(3)* %arrayidx1, align 1
+  %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 1
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -300,48 +300,48 @@ define void @unaligned_read2_f32(float addrspace(1)* %out, float addrspace(3)* %
 ; SI: s_endpgm
 define void @misaligned_2_simple_read2_f32(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds float addrspace(3)* %lds, i32 %x.i
-  %val0 = load float addrspace(3)* %arrayidx0, align 2
+  %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %x.i
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 2
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x
-  %val1 = load float addrspace(3)* %arrayidx1, align 2
+  %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 2
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
 
 ; SI-LABEL: @simple_read2_f64
 ; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, {{v[0-9]+}}
-; SI: ds_read2_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, [[VPTR]] offset0:0 offset1:8
+; SI: ds_read2_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, [[VPTR]] offset1:8
 ; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}}
 ; SI: buffer_store_dwordx2 [[RESULT]]
 ; SI: s_endpgm
 define void @simple_read2_f64(double addrspace(1)* %out) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
-  %val0 = load double addrspace(3)* %arrayidx0, align 8
+  %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
+  %val0 = load double, double addrspace(3)* %arrayidx0, align 8
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
-  %val1 = load double addrspace(3)* %arrayidx1, align 8
+  %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
+  %val1 = load double, double addrspace(3)* %arrayidx1, align 8
   %sum = fadd double %val0, %val1
-  %out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
   store double %sum, double addrspace(1)* %out.gep, align 8
   ret void
 }
 
 ; SI-LABEL: @simple_read2_f64_max_offset
-; SI: ds_read2_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:0 offset1:255
+; SI: ds_read2_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:255
 ; SI: s_endpgm
 define void @simple_read2_f64_max_offset(double addrspace(1)* %out) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
-  %val0 = load double addrspace(3)* %arrayidx0, align 8
+  %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
+  %val0 = load double, double addrspace(3)* %arrayidx0, align 8
   %add.x = add nsw i32 %x.i, 255
-  %arrayidx1 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
-  %val1 = load double addrspace(3)* %arrayidx1, align 8
+  %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
+  %val1 = load double, double addrspace(3)* %arrayidx1, align 8
   %sum = fadd double %val0, %val1
-  %out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
   store double %sum, double addrspace(1)* %out.gep, align 8
   ret void
 }
@@ -353,31 +353,31 @@ define void @simple_read2_f64_max_offset(double addrspace(1)* %out) #0 {
 ; SI: s_endpgm
 define void @simple_read2_f64_too_far(double addrspace(1)* %out) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
-  %val0 = load double addrspace(3)* %arrayidx0, align 8
+  %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
+  %val0 = load double, double addrspace(3)* %arrayidx0, align 8
   %add.x = add nsw i32 %x.i, 257
-  %arrayidx1 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
-  %val1 = load double addrspace(3)* %arrayidx1, align 8
+  %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
+  %val1 = load double, double addrspace(3)* %arrayidx1, align 8
   %sum = fadd double %val0, %val1
-  %out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
   store double %sum, double addrspace(1)* %out.gep, align 8
   ret void
 }
 
 ; Alignment only 4
 ; SI-LABEL: @misaligned_read2_f64
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:0 offset1:1
+; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset1:1
 ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:14 offset1:15
 ; SI: s_endpgm
 define void @misaligned_read2_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %x.i
-  %val0 = load double addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i
+  %val0 = load double, double addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 7
-  %arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x
-  %val1 = load double addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x
+  %val1 = load double, double addrspace(3)* %arrayidx1, align 4
   %sum = fadd double %val0, %val1
-  %out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
   store double %sum, double addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -386,10 +386,10 @@ define void @misaligned_read2_f64(double addrspace(1)* %out, double addrspace(3)
 
 ; SI-LABEL: @load_constant_adjacent_offsets
 ; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset0:0 offset1:1
+; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset1:1
 define void @load_constant_adjacent_offsets(i32 addrspace(1)* %out) {
-  %val0 = load i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4
-  %val1 = load i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 1), align 4
+  %val0 = load i32, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4
+  %val1 = load i32, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 1), align 4
   %sum = add i32 %val0, %val1
   store i32 %sum, i32 addrspace(1)* %out, align 4
   ret void
@@ -397,10 +397,10 @@ define void @load_constant_adjacent_offsets(i32 addrspace(1)* %out) {
 
 ; SI-LABEL: @load_constant_disjoint_offsets
 ; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset0:0 offset1:2
+; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset1:2
 define void @load_constant_disjoint_offsets(i32 addrspace(1)* %out) {
-  %val0 = load i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4
-  %val1 = load i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 2), align 4
+  %val0 = load i32, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4
+  %val1 = load i32, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 2), align 4
   %sum = add i32 %val0, %val1
   store i32 %sum, i32 addrspace(1)* %out, align 4
   ret void
@@ -410,11 +410,11 @@ define void @load_constant_disjoint_offsets(i32 addrspace(1)* %out) {
 
 ; SI-LABEL: @load_misaligned64_constant_offsets
 ; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset0:0 offset1:1
+; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset1:1
 ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset0:2 offset1:3
 define void @load_misaligned64_constant_offsets(i64 addrspace(1)* %out) {
-  %val0 = load i64 addrspace(3)* getelementptr inbounds ([4 x i64] addrspace(3)* @bar, i32 0, i32 0), align 4
-  %val1 = load i64 addrspace(3)* getelementptr inbounds ([4 x i64] addrspace(3)* @bar, i32 0, i32 1), align 4
+  %val0 = load i64, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 0), align 4
+  %val1 = load i64, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 1), align 4
   %sum = add i64 %val0, %val1
   store i64 %sum, i64 addrspace(1)* %out, align 8
   ret void
@@ -425,12 +425,12 @@ define void @load_misaligned64_constant_offsets(i64 addrspace(1)* %out) {
 ; SI-LABEL: @load_misaligned64_constant_large_offsets
 ; SI-DAG: v_mov_b32_e32 [[BASE0:v[0-9]+]], 0x7ff8{{$}}
 ; SI-DAG: v_mov_b32_e32 [[BASE1:v[0-9]+]], 0x4000
-; SI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASE0]] offset0:0 offset1:1
-; SI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASE1]] offset0:0 offset1:1
+; SI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASE0]] offset1:1
+; SI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASE1]] offset1:1
 ; SI: s_endpgm
 define void @load_misaligned64_constant_large_offsets(i64 addrspace(1)* %out) {
-  %val0 = load i64 addrspace(3)* getelementptr inbounds ([4096 x i64] addrspace(3)* @bar.large, i32 0, i32 2048), align 4
-  %val1 = load i64 addrspace(3)* getelementptr inbounds ([4096 x i64] addrspace(3)* @bar.large, i32 0, i32 4095), align 4
+  %val0 = load i64, i64 addrspace(3)* getelementptr inbounds ([4096 x i64], [4096 x i64] addrspace(3)* @bar.large, i32 0, i32 2048), align 4
+  %val1 = load i64, i64 addrspace(3)* getelementptr inbounds ([4096 x i64], [4096 x i64] addrspace(3)* @bar.large, i32 0, i32 4095), align 4
   %sum = add i64 %val0, %val1
   store i64 %sum, i64 addrspace(1)* %out, align 8
   ret void
@@ -442,34 +442,34 @@ define void @load_misaligned64_constant_large_offsets(i64 addrspace(1)* %out) {
 define void @sgemm_inner_loop_read2_sequence(float addrspace(1)* %C, i32 %lda, i32 %ldb) #0 {
   %x.i = tail call i32 @llvm.r600.read.tgid.x() #1
   %y.i = tail call i32 @llvm.r600.read.tidig.y() #1
-  %arrayidx44 = getelementptr inbounds [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %x.i
-  %tmp16 = load float addrspace(3)* %arrayidx44, align 4
+  %arrayidx44 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %x.i
+  %tmp16 = load float, float addrspace(3)* %arrayidx44, align 4
   %add47 = add nsw i32 %x.i, 1
-  %arrayidx48 = getelementptr inbounds [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add47
-  %tmp17 = load float addrspace(3)* %arrayidx48, align 4
+  %arrayidx48 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add47
+  %tmp17 = load float, float addrspace(3)* %arrayidx48, align 4
   %add51 = add nsw i32 %x.i, 16
-  %arrayidx52 = getelementptr inbounds [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add51
-  %tmp18 = load float addrspace(3)* %arrayidx52, align 4
+  %arrayidx52 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add51
+  %tmp18 = load float, float addrspace(3)* %arrayidx52, align 4
   %add55 = add nsw i32 %x.i, 17
-  %arrayidx56 = getelementptr inbounds [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add55
-  %tmp19 = load float addrspace(3)* %arrayidx56, align 4
-  %arrayidx60 = getelementptr inbounds [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %y.i
-  %tmp20 = load float addrspace(3)* %arrayidx60, align 4
+  %arrayidx56 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add55
+  %tmp19 = load float, float addrspace(3)* %arrayidx56, align 4
+  %arrayidx60 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %y.i
+  %tmp20 = load float, float addrspace(3)* %arrayidx60, align 4
   %add63 = add nsw i32 %y.i, 1
-  %arrayidx64 = getelementptr inbounds [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add63
-  %tmp21 = load float addrspace(3)* %arrayidx64, align 4
+  %arrayidx64 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add63
+  %tmp21 = load float, float addrspace(3)* %arrayidx64, align 4
   %add67 = add nsw i32 %y.i, 32
-  %arrayidx68 = getelementptr inbounds [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add67
-  %tmp22 = load float addrspace(3)* %arrayidx68, align 4
+  %arrayidx68 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add67
+  %tmp22 = load float, float addrspace(3)* %arrayidx68, align 4
   %add71 = add nsw i32 %y.i, 33
-  %arrayidx72 = getelementptr inbounds [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add71
-  %tmp23 = load float addrspace(3)* %arrayidx72, align 4
+  %arrayidx72 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add71
+  %tmp23 = load float, float addrspace(3)* %arrayidx72, align 4
   %add75 = add nsw i32 %y.i, 64
-  %arrayidx76 = getelementptr inbounds [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add75
-  %tmp24 = load float addrspace(3)* %arrayidx76, align 4
+  %arrayidx76 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add75
+  %tmp24 = load float, float addrspace(3)* %arrayidx76, align 4
   %add79 = add nsw i32 %y.i, 65
-  %arrayidx80 = getelementptr inbounds [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add79
-  %tmp25 = load float addrspace(3)* %arrayidx80, align 4
+  %arrayidx80 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add79
+  %tmp25 = load float, float addrspace(3)* %arrayidx80, align 4
   %sum.0 = fadd float %tmp16, %tmp17
   %sum.1 = fadd float %sum.0, %tmp18
   %sum.2 = fadd float %sum.1, %tmp19
@@ -484,13 +484,13 @@ define void @sgemm_inner_loop_read2_sequence(float addrspace(1)* %C, i32 %lda, i
 }
 
 define void @misaligned_read2_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(3)* %in) #0 {
-  %load = load <2 x i32> addrspace(3)* %in, align 4
+  %load = load <2 x i32>, <2 x i32> addrspace(3)* %in, align 4
   store <2 x i32> %load, <2 x i32> addrspace(1)* %out, align 8
   ret void
 }
 
 define void @misaligned_read2_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %in) #0 {
-  %load = load i64 addrspace(3)* %in, align 4
+  %load = load i64, i64 addrspace(3)* %in, align 4
   store i64 %load, i64 addrspace(1)* %out, align 8
   ret void
 }
diff --git a/test/CodeGen/R600/ds_read2_offset_order.ll b/test/CodeGen/R600/ds_read2_offset_order.ll
index 44306bc9d38f..9ea9a5a2617b 100644
--- a/test/CodeGen/R600/ds_read2_offset_order.ll
+++ b/test/CodeGen/R600/ds_read2_offset_order.ll
@@ -14,31 +14,31 @@
 
 define void @offset_order(float addrspace(1)* %out) {
 entry:
-  %ptr0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 0
-  %val0 = load float addrspace(3)* %ptr0
+  %ptr0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 0
+  %val0 = load float, float addrspace(3)* %ptr0
 
-  %ptr1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 256
-  %val1 = load float addrspace(3)* %ptr1
+  %ptr1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 256
+  %val1 = load float, float addrspace(3)* %ptr1
   %add1 = fadd float %val0, %val1
 
-  %ptr2 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 3
-  %val2 = load float addrspace(3)* %ptr2
+  %ptr2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 3
+  %val2 = load float, float addrspace(3)* %ptr2
   %add2 = fadd float %add1, %val2
 
-  %ptr3 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 2
-  %val3 = load float addrspace(3)* %ptr3
+  %ptr3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 2
+  %val3 = load float, float addrspace(3)* %ptr3
   %add3 = fadd float %add2, %val3
 
-  %ptr4 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 12
-  %val4 = load float addrspace(3)* %ptr4
+  %ptr4 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 12
+  %val4 = load float, float addrspace(3)* %ptr4
   %add4 = fadd float %add3, %val4
 
-  %ptr5 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 14
-  %val5 = load float addrspace(3)* %ptr5
+  %ptr5 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 14
+  %val5 = load float, float addrspace(3)* %ptr5
   %add5 = fadd float %add4, %val5
 
-  %ptr6 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 11
-  %val6 = load float addrspace(3)* %ptr6
+  %ptr6 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 11
+  %val6 = load float, float addrspace(3)* %ptr6
   %add6 = fadd float %add5, %val6
   store float %add6, float addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/ds_read2st64.ll b/test/CodeGen/R600/ds_read2st64.ll
index efd875e93176..54b3b45636d6 100644
--- a/test/CodeGen/R600/ds_read2st64.ll
+++ b/test/CodeGen/R600/ds_read2st64.ll
@@ -5,20 +5,20 @@
 
 
 ; SI-LABEL: @simple_read2st64_f32_0_1
-; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:0 offset1:1
+; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1
 ; SI: s_waitcnt lgkmcnt(0)
 ; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
 ; SI: buffer_store_dword [[RESULT]]
 ; SI: s_endpgm
 define void @simple_read2st64_f32_0_1(float addrspace(1)* %out) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 64
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
-  %val1 = load float addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -32,13 +32,13 @@ define void @simple_read2st64_f32_0_1(float addrspace(1)* %out) #0 {
 define void @simple_read2st64_f32_1_2(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
   %add.x.0 = add nsw i32 %x.i, 64
-  %arrayidx0 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x.0
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.0
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
   %add.x.1 = add nsw i32 %x.i, 128
-  %arrayidx1 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x.1
-  %val1 = load float addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.1
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -52,13 +52,13 @@ define void @simple_read2st64_f32_1_2(float addrspace(1)* %out, float addrspace(
 define void @simple_read2st64_f32_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
   %add.x.0 = add nsw i32 %x.i, 64
-  %arrayidx0 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x.0
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.0
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
   %add.x.1 = add nsw i32 %x.i, 16320
-  %arrayidx1 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x.1
-  %val1 = load float addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.1
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -72,13 +72,13 @@ define void @simple_read2st64_f32_max_offset(float addrspace(1)* %out, float add
 define void @simple_read2st64_f32_over_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
   %add.x.0 = add nsw i32 %x.i, 64
-  %arrayidx0 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x.0
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.0
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
   %add.x.1 = add nsw i32 %x.i, 16384
-  %arrayidx1 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x.1
-  %val1 = load float addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.1
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -88,13 +88,13 @@ define void @simple_read2st64_f32_over_max_offset(float addrspace(1)* %out, floa
 ; SI: s_endpgm
 define void @odd_invalid_read2st64_f32_0(float addrspace(1)* %out) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 63
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
-  %val1 = load float addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -105,32 +105,32 @@ define void @odd_invalid_read2st64_f32_0(float addrspace(1)* %out) #0 {
 define void @odd_invalid_read2st64_f32_1(float addrspace(1)* %out) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
   %add.x.0 = add nsw i32 %x.i, 64
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.0
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.0
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
   %add.x.1 = add nsw i32 %x.i, 127
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.1
-  %val1 = load float addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.1
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
   %sum = fadd float %val0, %val1
-  %out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
 
 ; SI-LABEL: @simple_read2st64_f64_0_1
-; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:0 offset1:1
+; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1
 ; SI: s_waitcnt lgkmcnt(0)
 ; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}}
 ; SI: buffer_store_dwordx2 [[RESULT]]
 ; SI: s_endpgm
 define void @simple_read2st64_f64_0_1(double addrspace(1)* %out) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
-  %val0 = load double addrspace(3)* %arrayidx0, align 8
+  %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
+  %val0 = load double, double addrspace(3)* %arrayidx0, align 8
   %add.x = add nsw i32 %x.i, 64
-  %arrayidx1 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
-  %val1 = load double addrspace(3)* %arrayidx1, align 8
+  %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
+  %val1 = load double, double addrspace(3)* %arrayidx1, align 8
   %sum = fadd double %val0, %val1
-  %out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
   store double %sum, double addrspace(1)* %out.gep, align 8
   ret void
 }
@@ -144,13 +144,13 @@ define void @simple_read2st64_f64_0_1(double addrspace(1)* %out) #0 {
 define void @simple_read2st64_f64_1_2(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
   %add.x.0 = add nsw i32 %x.i, 64
-  %arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.0
-  %val0 = load double addrspace(3)* %arrayidx0, align 8
+  %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0
+  %val0 = load double, double addrspace(3)* %arrayidx0, align 8
   %add.x.1 = add nsw i32 %x.i, 128
-  %arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.1
-  %val1 = load double addrspace(3)* %arrayidx1, align 8
+  %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.1
+  %val1 = load double, double addrspace(3)* %arrayidx1, align 8
   %sum = fadd double %val0, %val1
-  %out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
   store double %sum, double addrspace(1)* %out.gep, align 8
   ret void
 }
@@ -158,18 +158,18 @@ define void @simple_read2st64_f64_1_2(double addrspace(1)* %out, double addrspac
 ; Alignment only
 
 ; SI-LABEL: @misaligned_read2st64_f64
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:0 offset1:1
+; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset1:1
 ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:128 offset1:129
 ; SI: s_endpgm
 define void @misaligned_read2st64_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %x.i
-  %val0 = load double addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i
+  %val0 = load double, double addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 64
-  %arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x
-  %val1 = load double addrspace(3)* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x
+  %val1 = load double, double addrspace(3)* %arrayidx1, align 4
   %sum = fadd double %val0, %val1
-  %out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
   store double %sum, double addrspace(1)* %out.gep, align 4
   ret void
 }
@@ -184,13 +184,13 @@ define void @misaligned_read2st64_f64(double addrspace(1)* %out, double addrspac
 define void @simple_read2st64_f64_max_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
   %add.x.0 = add nsw i32 %x.i, 256
-  %arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.0
-  %val0 = load double addrspace(3)* %arrayidx0, align 8
+  %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0
+  %val0 = load double, double addrspace(3)* %arrayidx0, align 8
   %add.x.1 = add nsw i32 %x.i, 8128
-  %arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.1
-  %val1 = load double addrspace(3)* %arrayidx1, align 8
+  %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.1
+  %val1 = load double, double addrspace(3)* %arrayidx1, align 8
   %sum = fadd double %val0, %val1
-  %out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
   store double %sum, double addrspace(1)* %out.gep, align 8
   ret void
 }
@@ -204,13 +204,13 @@ define void @simple_read2st64_f64_max_offset(double addrspace(1)* %out, double a
 define void @simple_read2st64_f64_over_max_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
   %add.x.0 = add nsw i32 %x.i, 64
-  %arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.0
-  %val0 = load double addrspace(3)* %arrayidx0, align 8
+  %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0
+  %val0 = load double, double addrspace(3)* %arrayidx0, align 8
   %add.x.1 = add nsw i32 %x.i, 8192
-  %arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.1
-  %val1 = load double addrspace(3)* %arrayidx1, align 8
+  %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.1
+  %val1 = load double, double addrspace(3)* %arrayidx1, align 8
   %sum = fadd double %val0, %val1
-  %out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
   store double %sum, double addrspace(1)* %out.gep, align 8
   ret void
 }
@@ -221,13 +221,13 @@ define void @simple_read2st64_f64_over_max_offset(double addrspace(1)* %out, dou
 define void @invalid_read2st64_f64_odd_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
   %add.x.0 = add nsw i32 %x.i, 64
-  %arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.0
-  %val0 = load double addrspace(3)* %arrayidx0, align 8
+  %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0
+  %val0 = load double, double addrspace(3)* %arrayidx0, align 8
   %add.x.1 = add nsw i32 %x.i, 8129
-  %arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.1
-  %val1 = load double addrspace(3)* %arrayidx1, align 8
+  %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.1
+  %val1 = load double, double addrspace(3)* %arrayidx1, align 8
   %sum = fadd double %val0, %val1
-  %out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
   store double %sum, double addrspace(1)* %out.gep, align 8
   ret void
 }
@@ -237,17 +237,17 @@ define void @invalid_read2st64_f64_odd_offset(double addrspace(1)* %out, double
 
 ; SI-LABEL: @byte_size_only_divisible_64_read2_f64
 ; SI-NOT: ds_read2st_b64
-; SI: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:0 offset1:8
+; SI: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:8
 ; SI: s_endpgm
 define void @byte_size_only_divisible_64_read2_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %x.i
-  %val0 = load double addrspace(3)* %arrayidx0, align 8
+  %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i
+  %val0 = load double, double addrspace(3)* %arrayidx0, align 8
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x
-  %val1 = load double addrspace(3)* %arrayidx1, align 8
+  %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x
+  %val1 = load double, double addrspace(3)* %arrayidx1, align 8
   %sum = fadd double %val0, %val1
-  %out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
+  %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
   store double %sum, double addrspace(1)* %out.gep, align 4
   ret void
 }
diff --git a/test/CodeGen/R600/ds_write2.ll b/test/CodeGen/R600/ds_write2.ll
index 27273e7c674d..b553d3459e40 100644
--- a/test/CodeGen/R600/ds_write2.ll
+++ b/test/CodeGen/R600/ds_write2.ll
@@ -7,16 +7,16 @@
 ; SI-LABEL: @simple_write2_one_val_f32
 ; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]]
 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2_b32 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:8 [M0]
+; SI: ds_write2_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:8
 ; SI: s_endpgm
 define void @simple_write2_one_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in.gep = getelementptr float addrspace(1)* %in, i32 %x.i
-  %val = load float addrspace(1)* %in.gep, align 4
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %in.gep = getelementptr float, float addrspace(1)* %in, i32 %x.i
+  %val = load float, float addrspace(1)* %in.gep, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
   store float %val, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
   store float %val, float addrspace(3)* %arrayidx1, align 4
   ret void
 }
@@ -25,18 +25,18 @@ define void @simple_write2_one_val_f32(float addrspace(1)* %C, float addrspace(1
 ; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
 ; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:8 [M0]
+; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8 
 ; SI: s_endpgm
 define void @simple_write2_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in.gep.0 = getelementptr float addrspace(1)* %in, i32 %x.i
-  %in.gep.1 = getelementptr float addrspace(1)* %in.gep.0, i32 1
-  %val0 = load float addrspace(1)* %in.gep.0, align 4
-  %val1 = load float addrspace(1)* %in.gep.1, align 4
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i
+  %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
+  %val0 = load float, float addrspace(1)* %in.gep.0, align 4
+  %val1 = load float, float addrspace(1)* %in.gep.1, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
   store float %val0, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
   store float %val1, float addrspace(3)* %arrayidx1, align 4
   ret void
 }
@@ -48,14 +48,14 @@ define void @simple_write2_two_val_f32(float addrspace(1)* %C, float addrspace(1
 ; SI: s_endpgm
 define void @simple_write2_two_val_f32_volatile_0(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in0.gep = getelementptr float addrspace(1)* %in0, i32 %x.i
-  %in1.gep = getelementptr float addrspace(1)* %in1, i32 %x.i
-  %val0 = load float addrspace(1)* %in0.gep, align 4
-  %val1 = load float addrspace(1)* %in1.gep, align 4
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i
+  %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i
+  %val0 = load float, float addrspace(1)* %in0.gep, align 4
+  %val1 = load float, float addrspace(1)* %in1.gep, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
   store volatile float %val0, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
   store float %val1, float addrspace(3)* %arrayidx1, align 4
   ret void
 }
@@ -67,14 +67,14 @@ define void @simple_write2_two_val_f32_volatile_0(float addrspace(1)* %C, float
 ; SI: s_endpgm
 define void @simple_write2_two_val_f32_volatile_1(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in0.gep = getelementptr float addrspace(1)* %in0, i32 %x.i
-  %in1.gep = getelementptr float addrspace(1)* %in1, i32 %x.i
-  %val0 = load float addrspace(1)* %in0.gep, align 4
-  %val1 = load float addrspace(1)* %in1.gep, align 4
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i
+  %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i
+  %val0 = load float, float addrspace(1)* %in0.gep, align 4
+  %val1 = load float, float addrspace(1)* %in1.gep, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
   store float %val0, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
   store volatile float %val1, float addrspace(3)* %arrayidx1, align 4
   ret void
 }
@@ -84,20 +84,20 @@ define void @simple_write2_two_val_f32_volatile_1(float addrspace(1)* %C, float
 ; SI: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:{{[0-9]+\]}}
 ; SI: buffer_load_dwordx2 v{{\[[0-9]+}}:[[VAL1:[0-9]+]]{{\]}}
 ; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8 [M0]
+; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
 ; SI: s_endpgm
 define void @simple_write2_two_val_subreg2_mixed_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in.gep.0 = getelementptr <2 x float> addrspace(1)* %in, i32 %x.i
-  %in.gep.1 = getelementptr <2 x float> addrspace(1)* %in.gep.0, i32 1
-  %val0 = load <2 x float> addrspace(1)* %in.gep.0, align 8
-  %val1 = load <2 x float> addrspace(1)* %in.gep.1, align 8
+  %in.gep.0 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in, i32 %x.i
+  %in.gep.1 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in.gep.0, i32 1
+  %val0 = load <2 x float>, <2 x float> addrspace(1)* %in.gep.0, align 8
+  %val1 = load <2 x float>, <2 x float> addrspace(1)* %in.gep.1, align 8
   %val0.0 = extractelement <2 x float> %val0, i32 0
   %val1.1 = extractelement <2 x float> %val1, i32 1
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
   store float %val0.0, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
   store float %val1.1, float addrspace(3)* %arrayidx1, align 4
   ret void
 }
@@ -105,18 +105,18 @@ define void @simple_write2_two_val_subreg2_mixed_f32(float addrspace(1)* %C, <2
 ; SI-LABEL: @simple_write2_two_val_subreg2_f32
 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8 [M0]
+; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
 ; SI: s_endpgm
 define void @simple_write2_two_val_subreg2_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in.gep = getelementptr <2 x float> addrspace(1)* %in, i32 %x.i
-  %val = load <2 x float> addrspace(1)* %in.gep, align 8
+  %in.gep = getelementptr <2 x float>, <2 x float> addrspace(1)* %in, i32 %x.i
+  %val = load <2 x float>, <2 x float> addrspace(1)* %in.gep, align 8
   %val0 = extractelement <2 x float> %val, i32 0
   %val1 = extractelement <2 x float> %val, i32 1
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
   store float %val0, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
   store float %val1, float addrspace(3)* %arrayidx1, align 4
   ret void
 }
@@ -124,18 +124,18 @@ define void @simple_write2_two_val_subreg2_f32(float addrspace(1)* %C, <2 x floa
 ; SI-LABEL: @simple_write2_two_val_subreg4_f32
 ; SI-DAG: buffer_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8 [M0]
+; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
 ; SI: s_endpgm
 define void @simple_write2_two_val_subreg4_f32(float addrspace(1)* %C, <4 x float> addrspace(1)* %in) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in.gep = getelementptr <4 x float> addrspace(1)* %in, i32 %x.i
-  %val = load <4 x float> addrspace(1)* %in.gep, align 16
+  %in.gep = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 %x.i
+  %val = load <4 x float>, <4 x float> addrspace(1)* %in.gep, align 16
   %val0 = extractelement <4 x float> %val, i32 0
   %val1 = extractelement <4 x float> %val, i32 3
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
   store float %val0, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
   store float %val1, float addrspace(3)* %arrayidx1, align 4
   ret void
 }
@@ -144,18 +144,18 @@ define void @simple_write2_two_val_subreg4_f32(float addrspace(1)* %C, <4 x floa
 ; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
 ; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:255 [M0]
+; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255
 ; SI: s_endpgm
 define void @simple_write2_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in.gep.0 = getelementptr float addrspace(1)* %in, i32 %x.i
-  %in.gep.1 = getelementptr float addrspace(1)* %in.gep.0, i32 1
-  %val0 = load float addrspace(1)* %in.gep.0, align 4
-  %val1 = load float addrspace(1)* %in.gep.1, align 4
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i
+  %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
+  %val0 = load float, float addrspace(1)* %in.gep.0, align 4
+  %val1 = load float, float addrspace(1)* %in.gep.1, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
   store float %val0, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 255
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
   store float %val1, float addrspace(3)* %arrayidx1, align 4
   ret void
 }
@@ -166,43 +166,43 @@ define void @simple_write2_two_val_max_offset_f32(float addrspace(1)* %C, float
 ; SI: s_endpgm
 define void @simple_write2_two_val_too_far_f32(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in0.gep = getelementptr float addrspace(1)* %in0, i32 %x.i
-  %in1.gep = getelementptr float addrspace(1)* %in1, i32 %x.i
-  %val0 = load float addrspace(1)* %in0.gep, align 4
-  %val1 = load float addrspace(1)* %in1.gep, align 4
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i
+  %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i
+  %val0 = load float, float addrspace(1)* %in0.gep, align 4
+  %val1 = load float, float addrspace(1)* %in1.gep, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
   store float %val0, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 257
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
   store float %val1, float addrspace(3)* %arrayidx1, align 4
   ret void
 }
 
 ; SI-LABEL: @simple_write2_two_val_f32_x2
-; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL1:v[0-9]+]] offset0:0 offset1:8
+; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL1:v[0-9]+]] offset1:8
 ; SI-NEXT: ds_write2_b32 [[BASEADDR]], [[VAL0]], [[VAL1]] offset0:11 offset1:27
 ; SI: s_endpgm
 define void @simple_write2_two_val_f32_x2(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in0.gep = getelementptr float addrspace(1)* %in0, i32 %tid.x
-  %in1.gep = getelementptr float addrspace(1)* %in1, i32 %tid.x
-  %val0 = load float addrspace(1)* %in0.gep, align 4
-  %val1 = load float addrspace(1)* %in1.gep, align 4
+  %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %tid.x
+  %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %tid.x
+  %val0 = load float, float addrspace(1)* %in0.gep, align 4
+  %val1 = load float, float addrspace(1)* %in1.gep, align 4
 
   %idx.0 = add nsw i32 %tid.x, 0
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
   store float %val0, float addrspace(3)* %arrayidx0, align 4
 
   %idx.1 = add nsw i32 %tid.x, 8
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
   store float %val1, float addrspace(3)* %arrayidx1, align 4
 
   %idx.2 = add nsw i32 %tid.x, 11
-  %arrayidx2 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
+  %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
   store float %val0, float addrspace(3)* %arrayidx2, align 4
 
   %idx.3 = add nsw i32 %tid.x, 27
-  %arrayidx3 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
+  %arrayidx3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
   store float %val1, float addrspace(3)* %arrayidx3, align 4
 
   ret void
@@ -214,25 +214,25 @@ define void @simple_write2_two_val_f32_x2(float addrspace(1)* %C, float addrspac
 ; SI: s_endpgm
 define void @simple_write2_two_val_f32_x2_nonzero_base(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in0.gep = getelementptr float addrspace(1)* %in0, i32 %tid.x
-  %in1.gep = getelementptr float addrspace(1)* %in1, i32 %tid.x
-  %val0 = load float addrspace(1)* %in0.gep, align 4
-  %val1 = load float addrspace(1)* %in1.gep, align 4
+  %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %tid.x
+  %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %tid.x
+  %val0 = load float, float addrspace(1)* %in0.gep, align 4
+  %val1 = load float, float addrspace(1)* %in1.gep, align 4
 
   %idx.0 = add nsw i32 %tid.x, 3
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
   store float %val0, float addrspace(3)* %arrayidx0, align 4
 
   %idx.1 = add nsw i32 %tid.x, 8
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
   store float %val1, float addrspace(3)* %arrayidx1, align 4
 
   %idx.2 = add nsw i32 %tid.x, 11
-  %arrayidx2 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
+  %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
   store float %val0, float addrspace(3)* %arrayidx2, align 4
 
   %idx.3 = add nsw i32 %tid.x, 27
-  %arrayidx3 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
+  %arrayidx3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
   store float %val1, float addrspace(3)* %arrayidx3, align 4
 
   ret void
@@ -245,19 +245,19 @@ define void @simple_write2_two_val_f32_x2_nonzero_base(float addrspace(1)* %C, f
 ; SI: s_endpgm
 define void @write2_ptr_subreg_arg_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1, <2 x float addrspace(3)*> %lds.ptr) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in0.gep = getelementptr float addrspace(1)* %in0, i32 %x.i
-  %in1.gep = getelementptr float addrspace(1)* %in1, i32 %x.i
-  %val0 = load float addrspace(1)* %in0.gep, align 4
-  %val1 = load float addrspace(1)* %in1.gep, align 4
+  %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i
+  %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i
+  %val0 = load float, float addrspace(1)* %in0.gep, align 4
+  %val1 = load float, float addrspace(1)* %in1.gep, align 4
 
   %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0
   %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0
-  %gep = getelementptr inbounds <2 x float addrspace(3)*> %lds.ptr, <2 x i32> %index.1
+  %gep = getelementptr inbounds float, <2 x float addrspace(3)*> %lds.ptr, <2 x i32> %index.1
   %gep.0 = extractelement <2 x float addrspace(3)*> %gep, i32 0
   %gep.1 = extractelement <2 x float addrspace(3)*> %gep, i32 1
 
   ; Apply an additional offset after the vector that will be more obviously folded.
-  %gep.1.offset = getelementptr float addrspace(3)* %gep.1, i32 8
+  %gep.1.offset = getelementptr float, float addrspace(3)* %gep.1, i32 8
   store float %val0, float addrspace(3)* %gep.0, align 4
 
   %add.x = add nsw i32 %x.i, 8
@@ -268,16 +268,16 @@ define void @write2_ptr_subreg_arg_two_val_f32(float addrspace(1)* %C, float add
 ; SI-LABEL: @simple_write2_one_val_f64
 ; SI: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]],
 ; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}}
-; SI: ds_write2_b64 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:8 [M0]
+; SI: ds_write2_b64 [[VPTR]], [[VAL]], [[VAL]] offset1:8
 ; SI: s_endpgm
 define void @simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in.gep = getelementptr double addrspace(1)* %in, i32 %x.i
-  %val = load double addrspace(1)* %in.gep, align 8
-  %arrayidx0 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
+  %in.gep = getelementptr double, double addrspace(1)* %in, i32 %x.i
+  %val = load double, double addrspace(1)* %in.gep, align 8
+  %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
   store double %val, double addrspace(3)* %arrayidx0, align 8
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
+  %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
   store double %val, double addrspace(3)* %arrayidx1, align 8
   ret void
 }
@@ -285,17 +285,17 @@ define void @simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace
 ; SI-LABEL: @misaligned_simple_write2_one_val_f64
 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}}
-; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:1 [M0]
-; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:14 offset1:15 [M0]
+; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:1
+; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:14 offset1:15
 ; SI: s_endpgm
 define void @misaligned_simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in.gep = getelementptr double addrspace(1)* %in, i32 %x.i
-  %val = load double addrspace(1)* %in.gep, align 8
-  %arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %x.i
+  %in.gep = getelementptr double, double addrspace(1)* %in, i32 %x.i
+  %val = load double, double addrspace(1)* %in.gep, align 8
+  %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i
   store double %val, double addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 7
-  %arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x
+  %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x
   store double %val, double addrspace(3)* %arrayidx1, align 4
   ret void
 }
@@ -304,18 +304,18 @@ define void @misaligned_simple_write2_one_val_f64(double addrspace(1)* %C, doubl
 ; SI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
 ; SI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}}
-; SI: ds_write2_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:8 [M0]
+; SI: ds_write2_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8
 ; SI: s_endpgm
 define void @simple_write2_two_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in.gep.0 = getelementptr double addrspace(1)* %in, i32 %x.i
-  %in.gep.1 = getelementptr double addrspace(1)* %in.gep.0, i32 1
-  %val0 = load double addrspace(1)* %in.gep.0, align 8
-  %val1 = load double addrspace(1)* %in.gep.1, align 8
-  %arrayidx0 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
+  %in.gep.0 = getelementptr double, double addrspace(1)* %in, i32 %x.i
+  %in.gep.1 = getelementptr double, double addrspace(1)* %in.gep.0, i32 1
+  %val0 = load double, double addrspace(1)* %in.gep.0, align 8
+  %val1 = load double, double addrspace(1)* %in.gep.1, align 8
+  %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
   store double %val0, double addrspace(3)* %arrayidx0, align 8
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
+  %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
   store double %val1, double addrspace(3)* %arrayidx1, align 8
   ret void
 }
@@ -324,20 +324,20 @@ define void @simple_write2_two_val_f64(double addrspace(1)* %C, double addrspace
 
 ; SI-LABEL: @store_constant_adjacent_offsets
 ; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
-; SI: ds_write2_b32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1
+; SI: ds_write2_b32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1
 define void @store_constant_adjacent_offsets() {
-  store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4
-  store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 1), align 4
+  store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4
+  store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 1), align 4
   ret void
 }
 
 ; SI-LABEL: @store_constant_disjoint_offsets
 ; SI-DAG: v_mov_b32_e32 [[VAL:v[0-9]+]], 0x7b{{$}}
 ; SI-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
-; SI: ds_write2_b32 [[ZERO]], [[VAL]], [[VAL]] offset0:0 offset1:2
+; SI: ds_write2_b32 [[ZERO]], [[VAL]], [[VAL]] offset1:2
 define void @store_constant_disjoint_offsets() {
-  store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4
-  store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 2), align 4
+  store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4
+  store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 2), align 4
   ret void
 }
 
@@ -345,11 +345,11 @@ define void @store_constant_disjoint_offsets() {
 
 ; SI-LABEL: @store_misaligned64_constant_offsets
 ; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
-; SI: ds_write2_b32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1
+; SI: ds_write2_b32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1
 ; SI: ds_write2_b32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3
 define void @store_misaligned64_constant_offsets() {
-  store i64 123, i64 addrspace(3)* getelementptr inbounds ([4 x i64] addrspace(3)* @bar, i32 0, i32 0), align 4
-  store i64 123, i64 addrspace(3)* getelementptr inbounds ([4 x i64] addrspace(3)* @bar, i32 0, i32 1), align 4
+  store i64 123, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 0), align 4
+  store i64 123, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 1), align 4
   ret void
 }
 
@@ -358,12 +358,12 @@ define void @store_misaligned64_constant_offsets() {
 ; SI-LABEL: @store_misaligned64_constant_large_offsets
 ; SI-DAG: v_mov_b32_e32 [[BASE0:v[0-9]+]], 0x7ff8{{$}}
 ; SI-DAG: v_mov_b32_e32 [[BASE1:v[0-9]+]], 0x4000{{$}}
-; SI-DAG: ds_write2_b32 [[BASE0]], v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1
-; SI-DAG: ds_write2_b32 [[BASE1]], v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1
+; SI-DAG: ds_write2_b32 [[BASE0]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1
+; SI-DAG: ds_write2_b32 [[BASE1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1
 ; SI: s_endpgm
 define void @store_misaligned64_constant_large_offsets() {
-  store i64 123, i64 addrspace(3)* getelementptr inbounds ([4096 x i64] addrspace(3)* @bar.large, i32 0, i32 2048), align 4
-  store i64 123, i64 addrspace(3)* getelementptr inbounds ([4096 x i64] addrspace(3)* @bar.large, i32 0, i32 4095), align 4
+  store i64 123, i64 addrspace(3)* getelementptr inbounds ([4096 x i64], [4096 x i64] addrspace(3)* @bar.large, i32 0, i32 2048), align 4
+  store i64 123, i64 addrspace(3)* getelementptr inbounds ([4096 x i64], [4096 x i64] addrspace(3)* @bar.large, i32 0, i32 4095), align 4
   ret void
 }
 
@@ -373,34 +373,34 @@ define void @store_misaligned64_constant_large_offsets() {
 define void @write2_sgemm_sequence(float addrspace(1)* %C, i32 %lda, i32 %ldb, float addrspace(1)* %in) #0 {
   %x.i = tail call i32 @llvm.r600.read.tgid.x() #1
   %y.i = tail call i32 @llvm.r600.read.tidig.y() #1
-  %val = load float addrspace(1)* %in
-  %arrayidx44 = getelementptr inbounds [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %x.i
+  %val = load float, float addrspace(1)* %in
+  %arrayidx44 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %x.i
   store float %val, float addrspace(3)* %arrayidx44, align 4
   %add47 = add nsw i32 %x.i, 1
-  %arrayidx48 = getelementptr inbounds [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add47
+  %arrayidx48 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add47
   store float %val, float addrspace(3)* %arrayidx48, align 4
   %add51 = add nsw i32 %x.i, 16
-  %arrayidx52 = getelementptr inbounds [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add51
+  %arrayidx52 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add51
   store float %val, float addrspace(3)* %arrayidx52, align 4
   %add55 = add nsw i32 %x.i, 17
-  %arrayidx56 = getelementptr inbounds [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add55
+  %arrayidx56 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add55
   store float %val, float addrspace(3)* %arrayidx56, align 4
-  %arrayidx60 = getelementptr inbounds [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %y.i
+  %arrayidx60 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %y.i
   store float %val, float addrspace(3)* %arrayidx60, align 4
   %add63 = add nsw i32 %y.i, 1
-  %arrayidx64 = getelementptr inbounds [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add63
+  %arrayidx64 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add63
   store float %val, float addrspace(3)* %arrayidx64, align 4
   %add67 = add nsw i32 %y.i, 32
-  %arrayidx68 = getelementptr inbounds [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add67
+  %arrayidx68 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add67
   store float %val, float addrspace(3)* %arrayidx68, align 4
   %add71 = add nsw i32 %y.i, 33
-  %arrayidx72 = getelementptr inbounds [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add71
+  %arrayidx72 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add71
   store float %val, float addrspace(3)* %arrayidx72, align 4
   %add75 = add nsw i32 %y.i, 64
-  %arrayidx76 = getelementptr inbounds [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add75
+  %arrayidx76 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add75
   store float %val, float addrspace(3)* %arrayidx76, align 4
   %add79 = add nsw i32 %y.i, 65
-  %arrayidx80 = getelementptr inbounds [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add79
+  %arrayidx80 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add79
   store float %val, float addrspace(3)* %arrayidx80, align 4
   ret void
 }
diff --git a/test/CodeGen/R600/ds_write2st64.ll b/test/CodeGen/R600/ds_write2st64.ll
index de5f4efcbcd3..1d9d881c5c7e 100644
--- a/test/CodeGen/R600/ds_write2st64.ll
+++ b/test/CodeGen/R600/ds_write2st64.ll
@@ -7,16 +7,16 @@
 ; SI-LABEL: @simple_write2st64_one_val_f32_0_1
 ; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]]
 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2st64_b32 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:1 [M0]
+; SI: ds_write2st64_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:1
 ; SI: s_endpgm
 define void @simple_write2st64_one_val_f32_0_1(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in.gep = getelementptr float addrspace(1)* %in, i32 %x.i
-  %val = load float addrspace(1)* %in.gep, align 4
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
+  %in.gep = getelementptr float, float addrspace(1)* %in, i32 %x.i
+  %val = load float, float addrspace(1)* %in.gep, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
   store float %val, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 64
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
   store float %val, float addrspace(3)* %arrayidx1, align 4
   ret void
 }
@@ -25,19 +25,19 @@ define void @simple_write2st64_one_val_f32_0_1(float addrspace(1)* %C, float add
 ; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
 ; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5 [M0]
+; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5
 ; SI: s_endpgm
 define void @simple_write2st64_two_val_f32_2_5(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in.gep.0 = getelementptr float addrspace(1)* %in, i32 %x.i
-  %in.gep.1 = getelementptr float addrspace(1)* %in.gep.0, i32 1
-  %val0 = load float addrspace(1)* %in.gep.0, align 4
-  %val1 = load float addrspace(1)* %in.gep.1, align 4
+  %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i
+  %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
+  %val0 = load float, float addrspace(1)* %in.gep.0, align 4
+  %val1 = load float, float addrspace(1)* %in.gep.1, align 4
   %add.x.0 = add nsw i32 %x.i, 128
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.0
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.0
   store float %val0, float addrspace(3)* %arrayidx0, align 4
   %add.x.1 = add nsw i32 %x.i, 320
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.1
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.1
   store float %val1, float addrspace(3)* %arrayidx1, align 4
   ret void
 }
@@ -46,18 +46,18 @@ define void @simple_write2st64_two_val_f32_2_5(float addrspace(1)* %C, float add
 ; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
 ; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:255 [M0]
+; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255
 ; SI: s_endpgm
 define void @simple_write2st64_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in, float addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in.gep.0 = getelementptr float addrspace(1)* %in, i32 %x.i
-  %in.gep.1 = getelementptr float addrspace(1)* %in.gep.0, i32 1
-  %val0 = load float addrspace(1)* %in.gep.0, align 4
-  %val1 = load float addrspace(1)* %in.gep.1, align 4
-  %arrayidx0 = getelementptr inbounds float addrspace(3)* %lds, i32 %x.i
+  %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i
+  %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
+  %val0 = load float, float addrspace(1)* %in.gep.0, align 4
+  %val1 = load float, float addrspace(1)* %in.gep.1, align 4
+  %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %x.i
   store float %val0, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 16320
-  %arrayidx1 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x
+  %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x
   store float %val1, float addrspace(3)* %arrayidx1, align 4
   ret void
 }
@@ -66,35 +66,35 @@ define void @simple_write2st64_two_val_max_offset_f32(float addrspace(1)* %C, fl
 ; SI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
 ; SI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
 ; SI-DAG: v_add_i32_e32 [[VPTR:v[0-9]+]],
-; SI: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127 [M0]
+; SI: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127
 ; SI: s_endpgm
 define void @simple_write2st64_two_val_max_offset_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in.gep.0 = getelementptr double addrspace(1)* %in, i32 %x.i
-  %in.gep.1 = getelementptr double addrspace(1)* %in.gep.0, i32 1
-  %val0 = load double addrspace(1)* %in.gep.0, align 8
-  %val1 = load double addrspace(1)* %in.gep.1, align 8
+  %in.gep.0 = getelementptr double, double addrspace(1)* %in, i32 %x.i
+  %in.gep.1 = getelementptr double, double addrspace(1)* %in.gep.0, i32 1
+  %val0 = load double, double addrspace(1)* %in.gep.0, align 8
+  %val1 = load double, double addrspace(1)* %in.gep.1, align 8
   %add.x.0 = add nsw i32 %x.i, 256
-  %arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.0
+  %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0
   store double %val0, double addrspace(3)* %arrayidx0, align 8
   %add.x.1 = add nsw i32 %x.i, 8128
-  %arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.1
+  %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.1
   store double %val1, double addrspace(3)* %arrayidx1, align 8
   ret void
 }
 
 ; SI-LABEL: @byte_size_only_divisible_64_write2st64_f64
 ; SI-NOT: ds_write2st64_b64
-; SI: ds_write2_b64 {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:0 offset1:8
+; SI: ds_write2_b64 {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset1:8
 ; SI: s_endpgm
 define void @byte_size_only_divisible_64_write2st64_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
-  %in.gep = getelementptr double addrspace(1)* %in, i32 %x.i
-  %val = load double addrspace(1)* %in.gep, align 8
-  %arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %x.i
+  %in.gep = getelementptr double, double addrspace(1)* %in, i32 %x.i
+  %val = load double, double addrspace(1)* %in.gep, align 8
+  %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i
   store double %val, double addrspace(3)* %arrayidx0, align 8
   %add.x = add nsw i32 %x.i, 8
-  %arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x
+  %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x
   store double %val, double addrspace(3)* %arrayidx1, align 8
   ret void
 }
diff --git a/test/CodeGen/R600/elf.ll b/test/CodeGen/R600/elf.ll
index f801b3f57357..d0fd06a34379 100644
--- a/test/CodeGen/R600/elf.ll
+++ b/test/CodeGen/R600/elf.ll
@@ -5,6 +5,9 @@
 ; RUN: llc < %s -march=amdgcn -mcpu=carrizo -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s
 ; RUN: llc < %s -march=amdgcn -mcpu=carrizo -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s
 
+; Test that we don't try to produce a COFF file on windows
+; RUN: llc < %s -mtriple=amdgcn-pc-mingw -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s
+
 ; ELF: Format: ELF32
 ; ELF: Name: .AMDGPU.config
 ; ELF: Type: SHT_PROGBITS
@@ -13,12 +16,12 @@
 ; ELF: Name: test
 ; ELF: Binding: Global
 
-; CONFIG: .align 256
-; CONFIG: test:
 ; CONFIG: .section .AMDGPU.config
 ; CONFIG-NEXT: .long   45096
 ; TYPICAL-NEXT: .long   0
 ; TONGA-NEXT: .long   576
+; CONFIG: .align 256
+; CONFIG: test:
 define void @test(i32 %p) #0 {
    %i = add i32 %p, 2
    %r = bitcast i32 %i to float
diff --git a/test/CodeGen/R600/empty-function.ll b/test/CodeGen/R600/empty-function.ll
index b5593eb87ae4..a060900811ea 100644
--- a/test/CodeGen/R600/empty-function.ll
+++ b/test/CodeGen/R600/empty-function.ll
@@ -3,16 +3,16 @@
 
 ; Make sure we don't assert on empty functions
 
-; SI-LABEL: {{^}}empty_function_ret:
 ; SI: .text
+; SI-LABEL: {{^}}empty_function_ret:
 ; SI: s_endpgm
 ; SI: codeLenInByte = 4
 define void @empty_function_ret() #0 {
   ret void
 }
 
-; SI-LABEL: {{^}}empty_function_unreachable:
 ; SI: .text
+; SI-LABEL: {{^}}empty_function_unreachable:
 ; SI: codeLenInByte = 0
 define void @empty_function_unreachable() #0 {
   unreachable
diff --git a/test/CodeGen/R600/endcf-loop-header.ll b/test/CodeGen/R600/endcf-loop-header.ll
index e3c5b3c1c364..267a323c5063 100644
--- a/test/CodeGen/R600/endcf-loop-header.ll
+++ b/test/CodeGen/R600/endcf-loop-header.ll
@@ -28,7 +28,7 @@ loop:
   br i1 %tmp2, label %done, label %loop
 
 done:
-  %tmp3 = getelementptr i32 addrspace(1)* %out, i64 1
+  %tmp3 = getelementptr i32, i32 addrspace(1)* %out, i64 1
   store i32 %inc, i32 addrspace(1)* %tmp3
   ret void
 }
diff --git a/test/CodeGen/R600/extload-private.ll b/test/CodeGen/R600/extload-private.ll
index fec868232507..294c3a9c6782 100644
--- a/test/CodeGen/R600/extload-private.ll
+++ b/test/CodeGen/R600/extload-private.ll
@@ -6,7 +6,7 @@
 define void @load_i8_sext_private(i32 addrspace(1)* %out) {
 entry:
   %tmp0 = alloca i8
-  %tmp1 = load i8* %tmp0
+  %tmp1 = load i8, i8* %tmp0
   %tmp2 = sext i8 %tmp1 to i32
   store i32 %tmp2, i32 addrspace(1)* %out
   ret void
@@ -17,7 +17,7 @@ entry:
 define void @load_i8_zext_private(i32 addrspace(1)* %out) {
 entry:
   %tmp0 = alloca i8
-  %tmp1 = load i8* %tmp0
+  %tmp1 = load i8, i8* %tmp0
   %tmp2 = zext i8 %tmp1 to i32
   store i32 %tmp2, i32 addrspace(1)* %out
   ret void
@@ -28,7 +28,7 @@ entry:
 define void @load_i16_sext_private(i32 addrspace(1)* %out) {
 entry:
   %tmp0 = alloca i16
-  %tmp1 = load i16* %tmp0
+  %tmp1 = load i16, i16* %tmp0
   %tmp2 = sext i16 %tmp1 to i32
   store i32 %tmp2, i32 addrspace(1)* %out
   ret void
@@ -39,7 +39,7 @@ entry:
 define void @load_i16_zext_private(i32 addrspace(1)* %out) {
 entry:
   %tmp0 = alloca i16
-  %tmp1 = load i16* %tmp0
+  %tmp1 = load i16, i16* %tmp0
   %tmp2 = zext i16 %tmp1 to i32
   store i32 %tmp2, i32 addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/extload.ll b/test/CodeGen/R600/extload.ll
index 73d6701bfb5b..662eb7a9716b 100644
--- a/test/CodeGen/R600/extload.ll
+++ b/test/CodeGen/R600/extload.ll
@@ -3,11 +3,12 @@
 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
 ; FUNC-LABEL: {{^}}anyext_load_i8:
-; EG: AND_INT
-; EG: 255
+; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+.[XYZW]]],
+; EG: VTX_READ_32 [[VAL]]
+
 define void @anyext_load_i8(i8 addrspace(1)* nocapture noalias %out, i8 addrspace(1)* nocapture noalias %src) nounwind {
   %cast = bitcast i8 addrspace(1)* %src to i32 addrspace(1)*
-  %load = load i32 addrspace(1)* %cast, align 1
+  %load = load i32, i32 addrspace(1)* %cast, align 1
   %x = bitcast i32 %load to <4 x i8>
   %castOut = bitcast i8 addrspace(1)* %out to <4 x i8> addrspace(1)*
   store <4 x i8> %x, <4 x i8> addrspace(1)* %castOut, align 1
@@ -15,13 +16,12 @@ define void @anyext_load_i8(i8 addrspace(1)* nocapture noalias %out, i8 addrspac
 }
 
 ; FUNC-LABEL: {{^}}anyext_load_i16:
-; EG: AND_INT
-; EG: AND_INT
-; EG-DAG: 65535
-; EG-DAG: -65536
+; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+.[XYZW]]],
+; EG: VTX_READ_32 [[VAL]]
+
 define void @anyext_load_i16(i16 addrspace(1)* nocapture noalias %out, i16 addrspace(1)* nocapture noalias %src) nounwind {
   %cast = bitcast i16 addrspace(1)* %src to i32 addrspace(1)*
-  %load = load i32 addrspace(1)* %cast, align 1
+  %load = load i32, i32 addrspace(1)* %cast, align 1
   %x = bitcast i32 %load to <2 x i16>
   %castOut = bitcast i16 addrspace(1)* %out to <2 x i16> addrspace(1)*
   store <2 x i16> %x, <2 x i16> addrspace(1)* %castOut, align 1
@@ -29,11 +29,11 @@ define void @anyext_load_i16(i16 addrspace(1)* nocapture noalias %out, i16 addrs
 }
 
 ; FUNC-LABEL: {{^}}anyext_load_lds_i8:
-; EG: AND_INT
-; EG: 255
+; EG: LDS_READ_RET {{.*}}, [[VAL:T[0-9]+.[XYZW]]]
+; EG: LDS_WRITE * [[VAL]]
 define void @anyext_load_lds_i8(i8 addrspace(3)* nocapture noalias %out, i8 addrspace(3)* nocapture noalias %src) nounwind {
   %cast = bitcast i8 addrspace(3)* %src to i32 addrspace(3)*
-  %load = load i32 addrspace(3)* %cast, align 1
+  %load = load i32, i32 addrspace(3)* %cast, align 1
   %x = bitcast i32 %load to <4 x i8>
   %castOut = bitcast i8 addrspace(3)* %out to <4 x i8> addrspace(3)*
   store <4 x i8> %x, <4 x i8> addrspace(3)* %castOut, align 1
@@ -41,13 +41,11 @@ define void @anyext_load_lds_i8(i8 addrspace(3)* nocapture noalias %out, i8 addr
 }
 
 ; FUNC-LABEL: {{^}}anyext_load_lds_i16:
-; EG: AND_INT
-; EG: AND_INT
-; EG-DAG: 65535
-; EG-DAG: -65536
+; EG: LDS_READ_RET {{.*}}, [[VAL:T[0-9]+.[XYZW]]]
+; EG: LDS_WRITE * [[VAL]]
 define void @anyext_load_lds_i16(i16 addrspace(3)* nocapture noalias %out, i16 addrspace(3)* nocapture noalias %src) nounwind {
   %cast = bitcast i16 addrspace(3)* %src to i32 addrspace(3)*
-  %load = load i32 addrspace(3)* %cast, align 1
+  %load = load i32, i32 addrspace(3)* %cast, align 1
   %x = bitcast i32 %load to <2 x i16>
   %castOut = bitcast i16 addrspace(3)* %out to <2 x i16> addrspace(3)*
   store <2 x i16> %x, <2 x i16> addrspace(3)* %castOut, align 1
diff --git a/test/CodeGen/R600/extract_vector_elt_i16.ll b/test/CodeGen/R600/extract_vector_elt_i16.ll
index 0774a9ae852b..c7572efc6f5b 100644
--- a/test/CodeGen/R600/extract_vector_elt_i16.ll
+++ b/test/CodeGen/R600/extract_vector_elt_i16.ll
@@ -9,7 +9,7 @@
 define void @extract_vector_elt_v2i16(i16 addrspace(1)* %out, <2 x i16> %foo) nounwind {
   %p0 = extractelement <2 x i16> %foo, i32 0
   %p1 = extractelement <2 x i16> %foo, i32 1
-  %out1 = getelementptr i16 addrspace(1)* %out, i32 1
+  %out1 = getelementptr i16, i16 addrspace(1)* %out, i32 1
   store i16 %p1, i16 addrspace(1)* %out, align 2
   store i16 %p0, i16 addrspace(1)* %out1, align 2
   ret void
@@ -23,7 +23,7 @@ define void @extract_vector_elt_v2i16(i16 addrspace(1)* %out, <2 x i16> %foo) no
 define void @extract_vector_elt_v4i16(i16 addrspace(1)* %out, <4 x i16> %foo) nounwind {
   %p0 = extractelement <4 x i16> %foo, i32 0
   %p1 = extractelement <4 x i16> %foo, i32 2
-  %out1 = getelementptr i16 addrspace(1)* %out, i32 1
+  %out1 = getelementptr i16, i16 addrspace(1)* %out, i32 1
   store i16 %p1, i16 addrspace(1)* %out, align 2
   store i16 %p0, i16 addrspace(1)* %out1, align 2
   ret void
diff --git a/test/CodeGen/R600/fabs.f64.ll b/test/CodeGen/R600/fabs.f64.ll
index d87c08260b4c..3c6136c1a7bd 100644
--- a/test/CodeGen/R600/fabs.f64.ll
+++ b/test/CodeGen/R600/fabs.f64.ll
@@ -13,8 +13,8 @@ declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone
 define void @v_fabs_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
   %tidext = sext i32 %tid to i64
-  %gep = getelementptr double addrspace(1)* %in, i64 %tidext
-  %val = load double addrspace(1)* %gep, align 8
+  %gep = getelementptr double, double addrspace(1)* %in, i64 %tidext
+  %val = load double, double addrspace(1)* %gep, align 8
   %fabs = call double @llvm.fabs.f64(double %val)
   store double %fabs, double addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/fabs.ll b/test/CodeGen/R600/fabs.ll
index add6b75d22ae..419a73d02669 100644
--- a/test/CodeGen/R600/fabs.ll
+++ b/test/CodeGen/R600/fabs.ll
@@ -1,4 +1,5 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
 
 
@@ -10,7 +11,7 @@
 ; R600-NOT: AND
 ; R600: |PV.{{[XYZW]}}|
 
-; SI: v_and_b32
+; GCN: v_and_b32
 
 define void @fabs_fn_free(float addrspace(1)* %out, i32 %in) {
   %bc= bitcast i32 %in to float
@@ -23,7 +24,7 @@ define void @fabs_fn_free(float addrspace(1)* %out, i32 %in) {
 ; R600-NOT: AND
 ; R600: |PV.{{[XYZW]}}|
 
-; SI: v_and_b32
+; GCN: v_and_b32
 
 define void @fabs_free(float addrspace(1)* %out, i32 %in) {
   %bc= bitcast i32 %in to float
@@ -35,7 +36,7 @@ define void @fabs_free(float addrspace(1)* %out, i32 %in) {
 ; FUNC-LABEL: {{^}}fabs_f32:
 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
 
-; SI: v_and_b32
+; GCN: v_and_b32
 define void @fabs_f32(float addrspace(1)* %out, float %in) {
   %fabs = call float @llvm.fabs.f32(float %in)
   store float %fabs, float addrspace(1)* %out
@@ -46,8 +47,8 @@ define void @fabs_f32(float addrspace(1)* %out, float %in) {
 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
 
-; SI: v_and_b32
-; SI: v_and_b32
+; GCN: v_and_b32
+; GCN: v_and_b32
 define void @fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
   %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
   store <2 x float> %fabs, <2 x float> addrspace(1)* %out
@@ -60,20 +61,21 @@ define void @fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
 
-; SI: v_and_b32
-; SI: v_and_b32
-; SI: v_and_b32
-; SI: v_and_b32
+; GCN: v_and_b32
+; GCN: v_and_b32
+; GCN: v_and_b32
+; GCN: v_and_b32
 define void @fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
   %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
   store <4 x float> %fabs, <4 x float> addrspace(1)* %out
   ret void
 }
 
-; SI-LABEL: {{^}}fabs_fn_fold:
+; GCN-LABEL: {{^}}fabs_fn_fold:
 ; SI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
-; SI-NOT: and
-; SI: v_mul_f32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}}
+; VI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
+; GCN-NOT: and
+; GCN: v_mul_f32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}}
 define void @fabs_fn_fold(float addrspace(1)* %out, float %in0, float %in1) {
   %fabs = call float @fabs(float %in0)
   %fmul = fmul float %fabs, %in1
@@ -81,10 +83,11 @@ define void @fabs_fn_fold(float addrspace(1)* %out, float %in0, float %in1) {
   ret void
 }
 
-; SI-LABEL: {{^}}fabs_fold:
+; GCN-LABEL: {{^}}fabs_fold:
 ; SI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
-; SI-NOT: and
-; SI: v_mul_f32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}}
+; VI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
+; GCN-NOT: and
+; GCN: v_mul_f32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}}
 define void @fabs_fold(float addrspace(1)* %out, float %in0, float %in1) {
   %fabs = call float @llvm.fabs.f32(float %in0)
   %fmul = fmul float %fabs, %in1
diff --git a/test/CodeGen/R600/fadd.ll b/test/CodeGen/R600/fadd.ll
index 365af9b73cc0..5fac328c5981 100644
--- a/test/CodeGen/R600/fadd.ll
+++ b/test/CodeGen/R600/fadd.ll
@@ -32,9 +32,9 @@ define void @fadd_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x flo
 ; SI: v_add_f32
 ; SI: v_add_f32
 define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
-  %a = load <4 x float> addrspace(1)* %in, align 16
-  %b = load <4 x float> addrspace(1)* %b_ptr, align 16
+  %b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
+  %a = load <4 x float>, <4 x float> addrspace(1)* %in, align 16
+  %b = load <4 x float>, <4 x float> addrspace(1)* %b_ptr, align 16
   %result = fadd <4 x float> %a, %b
   store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16
   ret void
diff --git a/test/CodeGen/R600/fadd64.ll b/test/CodeGen/R600/fadd64.ll
index f1f6fef54766..485c55870c47 100644
--- a/test/CodeGen/R600/fadd64.ll
+++ b/test/CodeGen/R600/fadd64.ll
@@ -6,8 +6,8 @@
 
 define void @fadd_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
                       double addrspace(1)* %in2) {
-   %r0 = load double addrspace(1)* %in1
-   %r1 = load double addrspace(1)* %in2
+   %r0 = load double, double addrspace(1)* %in1
+   %r1 = load double, double addrspace(1)* %in2
    %r2 = fadd double %r0, %r1
    store double %r2, double addrspace(1)* %out
    ret void
diff --git a/test/CodeGen/R600/fceil64.ll b/test/CodeGen/R600/fceil64.ll
index 77cd8eae402c..e8c34f0141e4 100644
--- a/test/CodeGen/R600/fceil64.ll
+++ b/test/CodeGen/R600/fceil64.ll
@@ -1,5 +1,6 @@
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
 
 declare double @llvm.ceil.f64(double) nounwind readnone
 declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone
@@ -11,19 +12,19 @@ declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone
 ; FUNC-LABEL: {{^}}fceil_f64:
 ; CI: v_ceil_f64_e32
 ; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014
+; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
 ; SI: s_add_i32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01
 ; SI: s_lshr_b64
 ; SI: s_not_b64
 ; SI: s_and_b64
-; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
-; SI-DAG: cmp_lt_i32
+; SI: cmp_gt_i32
 ; SI: cndmask_b32
 ; SI: cndmask_b32
-; SI: cmp_gt_i32
+; SI: cmp_lt_i32
 ; SI: cndmask_b32
 ; SI: cndmask_b32
-; SI: v_cmp_lg_f64
-; SI: v_cmp_gt_f64
+; SI-DAG: v_cmp_lt_f64
+; SI-DAG: v_cmp_lg_f64
 ; SI: s_and_b64
 ; SI: v_cndmask_b32
 ; SI: v_cndmask_b32
diff --git a/test/CodeGen/R600/fcmp-cnd.ll b/test/CodeGen/R600/fcmp-cnd.ll
index 1d4e323d3abf..530274f920f0 100644
--- a/test/CodeGen/R600/fcmp-cnd.ll
+++ b/test/CodeGen/R600/fcmp-cnd.ll
@@ -6,7 +6,7 @@
 
 define void @test(i32 addrspace(1)* %out, float addrspace(1)* %in) {
 entry:
-  %0 = load float addrspace(1)* %in
+  %0 = load float, float addrspace(1)* %in
   %cmp = fcmp oeq float %0, 0.000000e+00
   %value = select i1 %cmp, i32 2, i32 3 
   store i32 %value, i32 addrspace(1)* %out
diff --git a/test/CodeGen/R600/fcmp-cnde-int-args.ll b/test/CodeGen/R600/fcmp-cnde-int-args.ll
index 55aba0d72d39..c402805feb39 100644
--- a/test/CodeGen/R600/fcmp-cnde-int-args.ll
+++ b/test/CodeGen/R600/fcmp-cnde-int-args.ll
@@ -8,7 +8,7 @@
 
 define void @test(i32 addrspace(1)* %out, float addrspace(1)* %in) {
 entry:
-  %0 = load float addrspace(1)* %in
+  %0 = load float, float addrspace(1)* %in
   %cmp = fcmp oeq float %0, 0.000000e+00
   %value = select i1 %cmp, i32 -1, i32 0
   store i32 %value, i32 addrspace(1)* %out
diff --git a/test/CodeGen/R600/fcmp.ll b/test/CodeGen/R600/fcmp.ll
index 33992181e0d9..5207ab57bade 100644
--- a/test/CodeGen/R600/fcmp.ll
+++ b/test/CodeGen/R600/fcmp.ll
@@ -5,9 +5,9 @@
 
 define void @fcmp_sext(i32 addrspace(1)* %out, float addrspace(1)* %in) {
 entry:
-  %0 = load float addrspace(1)* %in
-  %arrayidx1 = getelementptr inbounds float addrspace(1)* %in, i32 1
-  %1 = load float addrspace(1)* %arrayidx1
+  %0 = load float, float addrspace(1)* %in
+  %arrayidx1 = getelementptr inbounds float, float addrspace(1)* %in, i32 1
+  %1 = load float, float addrspace(1)* %arrayidx1
   %cmp = fcmp oeq float %0, %1
   %sext = sext i1 %cmp to i32
   store i32 %sext, i32 addrspace(1)* %out
@@ -28,7 +28,7 @@ entry:
   br i1 %0, label %IF, label %ENDIF
 
 IF:
-  %1 = getelementptr i32 addrspace(1)* %out, i32 1
+  %1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
   store i32 0, i32 addrspace(1)* %1
   br label %ENDIF
 
diff --git a/test/CodeGen/R600/fcmp64.ll b/test/CodeGen/R600/fcmp64.ll
index 9dc8b50513f2..053ab0ed7aaf 100644
--- a/test/CodeGen/R600/fcmp64.ll
+++ b/test/CodeGen/R600/fcmp64.ll
@@ -5,8 +5,8 @@
 ; CHECK: v_cmp_nge_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
 define void @flt_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
                      double addrspace(1)* %in2) {
-   %r0 = load double addrspace(1)* %in1
-   %r1 = load double addrspace(1)* %in2
+   %r0 = load double, double addrspace(1)* %in1
+   %r1 = load double, double addrspace(1)* %in2
    %r2 = fcmp ult double %r0, %r1
    %r3 = zext i1 %r2 to i32
    store i32 %r3, i32 addrspace(1)* %out
@@ -17,8 +17,8 @@ define void @flt_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
 ; CHECK: v_cmp_ngt_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
 define void @fle_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
                      double addrspace(1)* %in2) {
-   %r0 = load double addrspace(1)* %in1
-   %r1 = load double addrspace(1)* %in2
+   %r0 = load double, double addrspace(1)* %in1
+   %r1 = load double, double addrspace(1)* %in2
    %r2 = fcmp ule double %r0, %r1
    %r3 = zext i1 %r2 to i32
    store i32 %r3, i32 addrspace(1)* %out
@@ -29,8 +29,8 @@ define void @fle_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
 ; CHECK: v_cmp_nle_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
 define void @fgt_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
                      double addrspace(1)* %in2) {
-   %r0 = load double addrspace(1)* %in1
-   %r1 = load double addrspace(1)* %in2
+   %r0 = load double, double addrspace(1)* %in1
+   %r1 = load double, double addrspace(1)* %in2
    %r2 = fcmp ugt double %r0, %r1
    %r3 = zext i1 %r2 to i32
    store i32 %r3, i32 addrspace(1)* %out
@@ -41,8 +41,8 @@ define void @fgt_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
 ; CHECK: v_cmp_nlt_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
 define void @fge_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
                      double addrspace(1)* %in2) {
-   %r0 = load double addrspace(1)* %in1
-   %r1 = load double addrspace(1)* %in2
+   %r0 = load double, double addrspace(1)* %in1
+   %r1 = load double, double addrspace(1)* %in2
    %r2 = fcmp uge double %r0, %r1
    %r3 = zext i1 %r2 to i32
    store i32 %r3, i32 addrspace(1)* %out
@@ -53,8 +53,8 @@ define void @fge_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
 ; CHECK: v_cmp_neq_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
 define void @fne_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
                      double addrspace(1)* %in2) {
-   %r0 = load double addrspace(1)* %in1
-   %r1 = load double addrspace(1)* %in2
+   %r0 = load double, double addrspace(1)* %in1
+   %r1 = load double, double addrspace(1)* %in2
    %r2 = fcmp une double %r0, %r1
    %r3 = select i1 %r2, double %r0, double %r1
    store double %r3, double addrspace(1)* %out
@@ -65,8 +65,8 @@ define void @fne_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
 ; CHECK: v_cmp_nlg_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
 define void @feq_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
                      double addrspace(1)* %in2) {
-   %r0 = load double addrspace(1)* %in1
-   %r1 = load double addrspace(1)* %in2
+   %r0 = load double, double addrspace(1)* %in1
+   %r1 = load double, double addrspace(1)* %in2
    %r2 = fcmp ueq double %r0, %r1
    %r3 = select i1 %r2, double %r0, double %r1
    store double %r3, double addrspace(1)* %out
diff --git a/test/CodeGen/R600/fconst64.ll b/test/CodeGen/R600/fconst64.ll
index 28e0c909747f..89af37545c99 100644
--- a/test/CodeGen/R600/fconst64.ll
+++ b/test/CodeGen/R600/fconst64.ll
@@ -6,7 +6,7 @@
 ; CHECK-DAG: s_mov_b32 {{s[0-9]+}}, 0
 
 define void @fconst_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
-   %r1 = load double addrspace(1)* %in
+   %r1 = load double, double addrspace(1)* %in
    %r2 = fadd double %r1, 5.000000e+00
    store double %r2, double addrspace(1)* %out
    ret void
diff --git a/test/CodeGen/R600/fcopysign.f32.ll b/test/CodeGen/R600/fcopysign.f32.ll
index 4bc5145bd4de..b719d5a39785 100644
--- a/test/CodeGen/R600/fcopysign.f32.ll
+++ b/test/CodeGen/R600/fcopysign.f32.ll
@@ -1,4 +1,5 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
 ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 
 
@@ -10,12 +11,14 @@ declare <4 x float> @llvm.copysign.v4f32(<4 x float>, <4 x float>) nounwind read
 ; FUNC-LABEL: {{^}}test_copysign_f32:
 ; SI: s_load_dword [[SMAG:s[0-9]+]], {{.*}} 0xb
 ; SI: s_load_dword [[SSIGN:s[0-9]+]], {{.*}} 0xc
-; SI-DAG: v_mov_b32_e32 [[VSIGN:v[0-9]+]], [[SSIGN]]
-; SI-DAG: v_mov_b32_e32 [[VMAG:v[0-9]+]], [[SMAG]]
-; SI-DAG: s_mov_b32 [[SCONST:s[0-9]+]], 0x7fffffff
-; SI: v_bfi_b32 [[RESULT:v[0-9]+]], [[SCONST]], [[VMAG]], [[VSIGN]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
+; VI: s_load_dword [[SMAG:s[0-9]+]], {{.*}} 0x2c
+; VI: s_load_dword [[SSIGN:s[0-9]+]], {{.*}} 0x30
+; GCN-DAG: v_mov_b32_e32 [[VSIGN:v[0-9]+]], [[SSIGN]]
+; GCN-DAG: v_mov_b32_e32 [[VMAG:v[0-9]+]], [[SMAG]]
+; GCN-DAG: s_mov_b32 [[SCONST:s[0-9]+]], 0x7fffffff
+; GCN: v_bfi_b32 [[RESULT:v[0-9]+]], [[SCONST]], [[VMAG]], [[VSIGN]]
+; GCN: buffer_store_dword [[RESULT]],
+; GCN: s_endpgm
 
 ; EG: BFI_INT
 define void @test_copysign_f32(float addrspace(1)* %out, float %mag, float %sign) nounwind {
@@ -25,7 +28,7 @@ define void @test_copysign_f32(float addrspace(1)* %out, float %mag, float %sign
 }
 
 ; FUNC-LABEL: {{^}}test_copysign_v2f32:
-; SI: s_endpgm
+; GCN: s_endpgm
 
 ; EG: BFI_INT
 ; EG: BFI_INT
@@ -36,7 +39,7 @@ define void @test_copysign_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %ma
 }
 
 ; FUNC-LABEL: {{^}}test_copysign_v4f32:
-; SI: s_endpgm
+; GCN: s_endpgm
 
 ; EG: BFI_INT
 ; EG: BFI_INT
diff --git a/test/CodeGen/R600/fcopysign.f64.ll b/test/CodeGen/R600/fcopysign.f64.ll
index a14a493f72c8..3d8c55993089 100644
--- a/test/CodeGen/R600/fcopysign.f64.ll
+++ b/test/CodeGen/R600/fcopysign.f64.ll
@@ -1,4 +1,5 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
 
 declare double @llvm.copysign.f64(double, double) nounwind readnone
 declare <2 x double> @llvm.copysign.v2f64(<2 x double>, <2 x double>) nounwind readnone
@@ -7,13 +8,15 @@ declare <4 x double> @llvm.copysign.v4f64(<4 x double>, <4 x double>) nounwind r
 ; FUNC-LABEL: {{^}}test_copysign_f64:
 ; SI-DAG: s_load_dwordx2 s{{\[}}[[SMAG_LO:[0-9]+]]:[[SMAG_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
 ; SI-DAG: s_load_dwordx2 s{{\[}}[[SSIGN_LO:[0-9]+]]:[[SSIGN_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-DAG: v_mov_b32_e32 v[[VSIGN_HI:[0-9]+]], s[[SSIGN_HI]]
-; SI-DAG: v_mov_b32_e32 v[[VMAG_HI:[0-9]+]], s[[SMAG_HI]]
-; SI-DAG: s_mov_b32 [[SCONST:s[0-9]+]], 0x7fffffff
-; SI: v_bfi_b32 v[[VRESULT_HI:[0-9]+]], [[SCONST]], v[[VMAG_HI]], v[[VSIGN_HI]]
-; SI: v_mov_b32_e32 v[[VMAG_LO:[0-9]+]], s[[SMAG_LO]]
-; SI: buffer_store_dwordx2 v{{\[}}[[VMAG_LO]]:[[VRESULT_HI]]{{\]}}
-; SI: s_endpgm
+; VI-DAG: s_load_dwordx2 s{{\[}}[[SMAG_LO:[0-9]+]]:[[SMAG_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; VI-DAG: s_load_dwordx2 s{{\[}}[[SSIGN_LO:[0-9]+]]:[[SSIGN_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
+; GCN-DAG: v_mov_b32_e32 v[[VSIGN_HI:[0-9]+]], s[[SSIGN_HI]]
+; GCN-DAG: v_mov_b32_e32 v[[VMAG_HI:[0-9]+]], s[[SMAG_HI]]
+; GCN-DAG: s_mov_b32 [[SCONST:s[0-9]+]], 0x7fffffff
+; GCN: v_bfi_b32 v[[VRESULT_HI:[0-9]+]], [[SCONST]], v[[VMAG_HI]], v[[VSIGN_HI]]
+; GCN: v_mov_b32_e32 v[[VMAG_LO:[0-9]+]], s[[SMAG_LO]]
+; GCN: buffer_store_dwordx2 v{{\[}}[[VMAG_LO]]:[[VRESULT_HI]]{{\]}}
+; GCN: s_endpgm
 define void @test_copysign_f64(double addrspace(1)* %out, double %mag, double %sign) nounwind {
   %result = call double @llvm.copysign.f64(double %mag, double %sign)
   store double %result, double addrspace(1)* %out, align 8
@@ -21,7 +24,7 @@ define void @test_copysign_f64(double addrspace(1)* %out, double %mag, double %s
 }
 
 ; FUNC-LABEL: {{^}}test_copysign_v2f64:
-; SI: s_endpgm
+; GCN: s_endpgm
 define void @test_copysign_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %mag, <2 x double> %sign) nounwind {
   %result = call <2 x double> @llvm.copysign.v2f64(<2 x double> %mag, <2 x double> %sign)
   store <2 x double> %result, <2 x double> addrspace(1)* %out, align 8
@@ -29,7 +32,7 @@ define void @test_copysign_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %
 }
 
 ; FUNC-LABEL: {{^}}test_copysign_v4f64:
-; SI: s_endpgm
+; GCN: s_endpgm
 define void @test_copysign_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %mag, <4 x double> %sign) nounwind {
   %result = call <4 x double> @llvm.copysign.v4f64(<4 x double> %mag, <4 x double> %sign)
   store <4 x double> %result, <4 x double> addrspace(1)* %out, align 8
diff --git a/test/CodeGen/R600/fdiv.f64.ll b/test/CodeGen/R600/fdiv.f64.ll
index 276642f99014..7c022e38c808 100644
--- a/test/CodeGen/R600/fdiv.f64.ll
+++ b/test/CodeGen/R600/fdiv.f64.ll
@@ -25,14 +25,14 @@
 ; COMMON-DAG: v_fma_f64 [[FMA3:v\[[0-9]+:[0-9]+\]]], [[FMA1]], [[FMA2]], [[FMA1]]
 ; COMMON-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[SCALE1]], [[FMA3]]
 ; COMMON-DAG: v_fma_f64 [[FMA4:v\[[0-9]+:[0-9]+\]]], -[[SCALE0]], [[MUL]], [[SCALE1]]
-; COMMON: v_div_fmas_f64 [[FMAS:v\[[0-9]+:[0-9]+\]]], [[FMA3]], [[FMA4]], [[MUL]]
+; COMMON: v_div_fmas_f64 [[FMAS:v\[[0-9]+:[0-9]+\]]], [[FMA4]], [[FMA3]], [[MUL]]
 ; COMMON: v_div_fixup_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[FMAS]], [[DEN]], [[NUM]]
 ; COMMON: buffer_store_dwordx2 [[RESULT]]
 ; COMMON: s_endpgm
 define void @fdiv_f64(double addrspace(1)* %out, double addrspace(1)* %in) nounwind {
-  %gep.1 = getelementptr double addrspace(1)* %in, i32 1
-  %num = load double addrspace(1)* %in
-  %den = load double addrspace(1)* %gep.1
+  %gep.1 = getelementptr double, double addrspace(1)* %in, i32 1
+  %num = load double, double addrspace(1)* %in
+  %den = load double, double addrspace(1)* %gep.1
   %result = fdiv double %num, %den
   store double %result, double addrspace(1)* %out
   ret void
@@ -40,7 +40,7 @@ define void @fdiv_f64(double addrspace(1)* %out, double addrspace(1)* %in) nounw
 
 ; COMMON-LABEL: {{^}}fdiv_f64_s_v:
 define void @fdiv_f64_s_v(double addrspace(1)* %out, double addrspace(1)* %in, double %num) nounwind {
-  %den = load double addrspace(1)* %in
+  %den = load double, double addrspace(1)* %in
   %result = fdiv double %num, %den
   store double %result, double addrspace(1)* %out
   ret void
@@ -48,7 +48,7 @@ define void @fdiv_f64_s_v(double addrspace(1)* %out, double addrspace(1)* %in, d
 
 ; COMMON-LABEL: {{^}}fdiv_f64_v_s:
 define void @fdiv_f64_v_s(double addrspace(1)* %out, double addrspace(1)* %in, double %den) nounwind {
-  %num = load double addrspace(1)* %in
+  %num = load double, double addrspace(1)* %in
   %result = fdiv double %num, %den
   store double %result, double addrspace(1)* %out
   ret void
@@ -63,9 +63,9 @@ define void @fdiv_f64_s_s(double addrspace(1)* %out, double %num, double %den) n
 
 ; COMMON-LABEL: {{^}}v_fdiv_v2f64:
 define void @v_fdiv_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in) nounwind {
-  %gep.1 = getelementptr <2 x double> addrspace(1)* %in, i32 1
-  %num = load <2 x double> addrspace(1)* %in
-  %den = load <2 x double> addrspace(1)* %gep.1
+  %gep.1 = getelementptr <2 x double>, <2 x double> addrspace(1)* %in, i32 1
+  %num = load <2 x double>, <2 x double> addrspace(1)* %in
+  %den = load <2 x double>, <2 x double> addrspace(1)* %gep.1
   %result = fdiv <2 x double> %num, %den
   store <2 x double> %result, <2 x double> addrspace(1)* %out
   ret void
@@ -80,9 +80,9 @@ define void @s_fdiv_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %num, <2
 
 ; COMMON-LABEL: {{^}}v_fdiv_v4f64:
 define void @v_fdiv_v4f64(<4 x double> addrspace(1)* %out, <4 x double> addrspace(1)* %in) nounwind {
-  %gep.1 = getelementptr <4 x double> addrspace(1)* %in, i32 1
-  %num = load <4 x double> addrspace(1)* %in
-  %den = load <4 x double> addrspace(1)* %gep.1
+  %gep.1 = getelementptr <4 x double>, <4 x double> addrspace(1)* %in, i32 1
+  %num = load <4 x double>, <4 x double> addrspace(1)* %in
+  %den = load <4 x double>, <4 x double> addrspace(1)* %gep.1
   %result = fdiv <4 x double> %num, %den
   store <4 x double> %result, <4 x double> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/fdiv.ll b/test/CodeGen/R600/fdiv.ll
index 603287fbdf4f..7cbf87336399 100644
--- a/test/CodeGen/R600/fdiv.ll
+++ b/test/CodeGen/R600/fdiv.ll
@@ -59,9 +59,9 @@ entry:
 ; SI-DAG: v_rcp_f32
 ; SI-DAG: v_mul_f32
 define void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
-  %a = load <4 x float> addrspace(1) * %in
-  %b = load <4 x float> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
+  %a = load <4 x float>, <4 x float> addrspace(1) * %in
+  %b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr
   %result = fdiv <4 x float> %a, %b
   store <4 x float> %result, <4 x float> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/fetch-limits.r600.ll b/test/CodeGen/R600/fetch-limits.r600.ll
index d35573e818d4..e7160ef5d726 100644
--- a/test/CodeGen/R600/fetch-limits.r600.ll
+++ b/test/CodeGen/R600/fetch-limits.r600.ll
@@ -9,15 +9,15 @@
 
 define void @fetch_limits_r600() #0 {
 entry:
-  %0 = load <4 x float> addrspace(8)* null
-  %1 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
-  %2 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
-  %3 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
-  %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
-  %5 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
-  %6 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
-  %7 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
-  %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
+  %0 = load <4 x float>, <4 x float> addrspace(8)* null
+  %1 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %3 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+  %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+  %5 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
+  %6 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
+  %7 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
+  %8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
   %res0 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %0, i32 0, i32 0, i32 1)
   %res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1, i32 0, i32 0, i32 1)
   %res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %2, i32 0, i32 0, i32 1)
diff --git a/test/CodeGen/R600/fetch-limits.r700+.ll b/test/CodeGen/R600/fetch-limits.r700+.ll
index 17760a05caa4..acaea2aa7943 100644
--- a/test/CodeGen/R600/fetch-limits.r700+.ll
+++ b/test/CodeGen/R600/fetch-limits.r700+.ll
@@ -18,23 +18,23 @@
 
 define void @fetch_limits_r700() #0 {
 entry:
-  %0 = load <4 x float> addrspace(8)* null
-  %1 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
-  %2 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
-  %3 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
-  %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
-  %5 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
-  %6 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
-  %7 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
-  %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
-  %9 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
-  %10 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
-  %11 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
-  %12 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12)
-  %13 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13)
-  %14 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
-  %15 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15)
-  %16 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16)
+  %0 = load <4 x float>, <4 x float> addrspace(8)* null
+  %1 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %3 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+  %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+  %5 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
+  %6 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
+  %7 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
+  %8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
+  %9 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+  %10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
+  %11 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
+  %12 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12)
+  %13 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13)
+  %14 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
+  %15 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15)
+  %16 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16)
   %res0 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %0, i32 0, i32 0, i32 1)
   %res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1, i32 0, i32 0, i32 1)
   %res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %2, i32 0, i32 0, i32 1)
diff --git a/test/CodeGen/R600/ffloor.f64.ll b/test/CodeGen/R600/ffloor.f64.ll
new file mode 100644
index 000000000000..45f8382c3929
--- /dev/null
+++ b/test/CodeGen/R600/ffloor.f64.ll
@@ -0,0 +1,127 @@
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
+
+declare double @llvm.fabs.f64(double %Val)
+declare double @llvm.floor.f64(double) nounwind readnone
+declare <2 x double> @llvm.floor.v2f64(<2 x double>) nounwind readnone
+declare <3 x double> @llvm.floor.v3f64(<3 x double>) nounwind readnone
+declare <4 x double> @llvm.floor.v4f64(<4 x double>) nounwind readnone
+declare <8 x double> @llvm.floor.v8f64(<8 x double>) nounwind readnone
+declare <16 x double> @llvm.floor.v16f64(<16 x double>) nounwind readnone
+
+; FUNC-LABEL: {{^}}ffloor_f64:
+; CI: v_floor_f64_e32
+; SI: v_fract_f64_e32
+; SI: v_min_f64
+; SI: v_cmp_class_f64_e64
+; SI: v_cndmask_b32_e64
+; SI: v_cndmask_b32_e64
+; SI: v_add_f64
+; SI: s_endpgm
+define void @ffloor_f64(double addrspace(1)* %out, double %x) {
+  %y = call double @llvm.floor.f64(double %x) nounwind readnone
+  store double %y, double addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}ffloor_f64_neg:
+; CI: v_floor_f64_e64
+; SI: v_fract_f64_e64 {{v[[0-9]+:[0-9]+]}}, -[[INPUT:s[[0-9]+:[0-9]+]]]
+; SI: v_min_f64
+; SI: v_cmp_class_f64_e64
+; SI: v_cndmask_b32_e64
+; SI: v_cndmask_b32_e64
+; SI: v_add_f64 {{v[[0-9]+:[0-9]+]}}, -[[INPUT]]
+; SI: s_endpgm
+define void @ffloor_f64_neg(double addrspace(1)* %out, double %x) {
+  %neg = fsub double 0.0, %x
+  %y = call double @llvm.floor.f64(double %neg) nounwind readnone
+  store double %y, double addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}ffloor_f64_neg_abs:
+; CI: v_floor_f64_e64
+; SI: v_fract_f64_e64 {{v[[0-9]+:[0-9]+]}}, -|[[INPUT:s[[0-9]+:[0-9]+]]]|
+; SI: v_min_f64
+; SI: v_cmp_class_f64_e64
+; SI: v_cndmask_b32_e64
+; SI: v_cndmask_b32_e64
+; SI: v_add_f64 {{v[[0-9]+:[0-9]+]}}, -|[[INPUT]]|
+; SI: s_endpgm
+define void @ffloor_f64_neg_abs(double addrspace(1)* %out, double %x) {
+  %abs = call double @llvm.fabs.f64(double %x)
+  %neg = fsub double 0.0, %abs
+  %y = call double @llvm.floor.f64(double %neg) nounwind readnone
+  store double %y, double addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}ffloor_v2f64:
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+define void @ffloor_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) {
+  %y = call <2 x double> @llvm.floor.v2f64(<2 x double> %x) nounwind readnone
+  store <2 x double> %y, <2 x double> addrspace(1)* %out
+  ret void
+}
+
+; FIXME-FUNC-LABEL: {{^}}ffloor_v3f64:
+; FIXME-CI: v_floor_f64_e32
+; FIXME-CI: v_floor_f64_e32
+; FIXME-CI: v_floor_f64_e32
+; define void @ffloor_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) {
+;   %y = call <3 x double> @llvm.floor.v3f64(<3 x double> %x) nounwind readnone
+;   store <3 x double> %y, <3 x double> addrspace(1)* %out
+;   ret void
+; }
+
+; FUNC-LABEL: {{^}}ffloor_v4f64:
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+define void @ffloor_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) {
+  %y = call <4 x double> @llvm.floor.v4f64(<4 x double> %x) nounwind readnone
+  store <4 x double> %y, <4 x double> addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}ffloor_v8f64:
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+define void @ffloor_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) {
+  %y = call <8 x double> @llvm.floor.v8f64(<8 x double> %x) nounwind readnone
+  store <8 x double> %y, <8 x double> addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}ffloor_v16f64:
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+; CI: v_floor_f64_e32
+define void @ffloor_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %x) {
+  %y = call <16 x double> @llvm.floor.v16f64(<16 x double> %x) nounwind readnone
+  store <16 x double> %y, <16 x double> addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/ffloor.ll b/test/CodeGen/R600/ffloor.ll
index 9038ff81b073..61c46ac2bc03 100644
--- a/test/CodeGen/R600/ffloor.ll
+++ b/test/CodeGen/R600/ffloor.ll
@@ -1,106 +1,49 @@
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
-
-declare double @llvm.floor.f64(double) nounwind readnone
-declare <2 x double> @llvm.floor.v2f64(<2 x double>) nounwind readnone
-declare <3 x double> @llvm.floor.v3f64(<3 x double>) nounwind readnone
-declare <4 x double> @llvm.floor.v4f64(<4 x double>) nounwind readnone
-declare <8 x double> @llvm.floor.v8f64(<8 x double>) nounwind readnone
-declare <16 x double> @llvm.floor.v16f64(<16 x double>) nounwind readnone
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
+
+; FUNC-LABEL: {{^}}floor_f32:
+; SI: v_floor_f32_e32
+; R600: FLOOR
+define void @floor_f32(float addrspace(1)* %out, float %in) {
+  %tmp = call float @llvm.floor.f32(float %in) #0
+  store float %tmp, float addrspace(1)* %out
+  ret void
+}
 
-; FUNC-LABEL: {{^}}ffloor_f64:
-; CI: v_floor_f64_e32
+; FUNC-LABEL: {{^}}floor_v2f32:
+; SI: v_floor_f32_e32
+; SI: v_floor_f32_e32
 
-; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014
-; SI: s_add_i32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01
-; SI: s_lshr_b64
-; SI: s_not_b64
-; SI: s_and_b64
-; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
-; SI-DAG: cmp_lt_i32
-; SI: cndmask_b32
-; SI: cndmask_b32
-; SI: cmp_gt_i32
-; SI: cndmask_b32
-; SI: cndmask_b32
-; SI: v_cmp_lg_f64
-; SI: v_cmp_lt_f64
-; SI: s_and_b64
-; SI: v_cndmask_b32
-; SI: v_cndmask_b32
-; SI: v_add_f64
-; SI: s_endpgm
-define void @ffloor_f64(double addrspace(1)* %out, double %x) {
-  %y = call double @llvm.floor.f64(double %x) nounwind readnone
-  store double %y, double addrspace(1)* %out
+define void @floor_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
+  %tmp = call <2 x float> @llvm.floor.v2f32(<2 x float> %in) #0
+  store <2 x float> %tmp, <2 x float> addrspace(1)* %out
   ret void
 }
 
-; FUNC-LABEL: {{^}}ffloor_v2f64:
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-define void @ffloor_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) {
-  %y = call <2 x double> @llvm.floor.v2f64(<2 x double> %x) nounwind readnone
-  store <2 x double> %y, <2 x double> addrspace(1)* %out
+; FUNC-LABEL: {{^}}floor_v4f32:
+; SI: v_floor_f32_e32
+; SI: v_floor_f32_e32
+; SI: v_floor_f32_e32
+; SI: v_floor_f32_e32
+
+; R600: FLOOR
+; R600: FLOOR
+; R600: FLOOR
+; R600: FLOOR
+define void @floor_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
+  %tmp = call <4 x float> @llvm.floor.v4f32(<4 x float> %in) #0
+  store <4 x float> %tmp, <4 x float> addrspace(1)* %out
   ret void
 }
 
-; FIXME-FUNC-LABEL: {{^}}ffloor_v3f64:
-; FIXME-CI: v_floor_f64_e32
-; FIXME-CI: v_floor_f64_e32
-; FIXME-CI: v_floor_f64_e32
-; define void @ffloor_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) {
-;   %y = call <3 x double> @llvm.floor.v3f64(<3 x double> %x) nounwind readnone
-;   store <3 x double> %y, <3 x double> addrspace(1)* %out
-;   ret void
-; }
+; Function Attrs: nounwind readonly
+declare float @llvm.floor.f32(float) #0
 
-; FUNC-LABEL: {{^}}ffloor_v4f64:
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-define void @ffloor_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) {
-  %y = call <4 x double> @llvm.floor.v4f64(<4 x double> %x) nounwind readnone
-  store <4 x double> %y, <4 x double> addrspace(1)* %out
-  ret void
-}
+; Function Attrs: nounwind readonly
+declare <2 x float> @llvm.floor.v2f32(<2 x float>) #0
 
-; FUNC-LABEL: {{^}}ffloor_v8f64:
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-define void @ffloor_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) {
-  %y = call <8 x double> @llvm.floor.v8f64(<8 x double> %x) nounwind readnone
-  store <8 x double> %y, <8 x double> addrspace(1)* %out
-  ret void
-}
+; Function Attrs: nounwind readonly
+declare <4 x float> @llvm.floor.v4f32(<4 x float>) #0
 
-; FUNC-LABEL: {{^}}ffloor_v16f64:
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-define void @ffloor_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %x) {
-  %y = call <16 x double> @llvm.floor.v16f64(<16 x double> %x) nounwind readnone
-  store <16 x double> %y, <16 x double> addrspace(1)* %out
-  ret void
-}
+attributes #0 = { nounwind readnone }
diff --git a/test/CodeGen/R600/flat-address-space.ll b/test/CodeGen/R600/flat-address-space.ll
index 2e98bf51b23b..425d67d5b07c 100644
--- a/test/CodeGen/R600/flat-address-space.ll
+++ b/test/CodeGen/R600/flat-address-space.ll
@@ -26,7 +26,7 @@ global:
 end:
   %fptr = phi i32 addrspace(4)* [ %flat_local, %local ], [ %flat_global, %global ]
   store i32 %x, i32 addrspace(4)* %fptr, align 4
-;  %val = load i32 addrspace(4)* %fptr, align 4
+;  %val = load i32, i32 addrspace(4)* %fptr, align 4
 ;  store i32 %val, i32 addrspace(1)* %out, align 4
   ret void
 }
@@ -87,7 +87,7 @@ define void @store_flat_trunc_i8(i8 addrspace(1)* %gptr, i32 %x) #0 {
 ; CHECK: flat_load_dword
 define void @load_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %gptr) #0 {
   %fptr = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)*
-  %fload = load i32 addrspace(4)* %fptr, align 4
+  %fload = load i32, i32 addrspace(4)* %fptr, align 4
   store i32 %fload, i32 addrspace(1)* %out, align 4
   ret void
 }
@@ -96,7 +96,7 @@ define void @load_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noa
 ; CHECK: flat_load_dwordx2
 define void @load_flat_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %gptr) #0 {
   %fptr = addrspacecast i64 addrspace(1)* %gptr to i64 addrspace(4)*
-  %fload = load i64 addrspace(4)* %fptr, align 4
+  %fload = load i64, i64 addrspace(4)* %fptr, align 4
   store i64 %fload, i64 addrspace(1)* %out, align 8
   ret void
 }
@@ -105,7 +105,7 @@ define void @load_flat_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noa
 ; CHECK: flat_load_dwordx4
 define void @load_flat_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %gptr) #0 {
   %fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32> addrspace(4)*
-  %fload = load <4 x i32> addrspace(4)* %fptr, align 4
+  %fload = load <4 x i32>, <4 x i32> addrspace(4)* %fptr, align 4
   store <4 x i32> %fload, <4 x i32> addrspace(1)* %out, align 8
   ret void
 }
@@ -114,7 +114,7 @@ define void @load_flat_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> add
 ; CHECK: flat_load_sbyte
 define void @sextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 {
   %fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)*
-  %fload = load i8 addrspace(4)* %fptr, align 4
+  %fload = load i8, i8 addrspace(4)* %fptr, align 4
   %ext = sext i8 %fload to i32
   store i32 %ext, i32 addrspace(1)* %out, align 4
   ret void
@@ -124,7 +124,7 @@ define void @sextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* n
 ; CHECK: flat_load_ubyte
 define void @zextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 {
   %fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)*
-  %fload = load i8 addrspace(4)* %fptr, align 4
+  %fload = load i8, i8 addrspace(4)* %fptr, align 4
   %ext = zext i8 %fload to i32
   store i32 %ext, i32 addrspace(1)* %out, align 4
   ret void
@@ -134,7 +134,7 @@ define void @zextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* n
 ; CHECK: flat_load_sshort
 define void @sextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 {
   %fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)*
-  %fload = load i16 addrspace(4)* %fptr, align 4
+  %fload = load i16, i16 addrspace(4)* %fptr, align 4
   %ext = sext i16 %fload to i32
   store i32 %ext, i32 addrspace(1)* %out, align 4
   ret void
@@ -144,7 +144,7 @@ define void @sextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)*
 ; CHECK: flat_load_ushort
 define void @zextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 {
   %fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)*
-  %fload = load i16 addrspace(4)* %fptr, align 4
+  %fload = load i16, i16 addrspace(4)* %fptr, align 4
   %ext = zext i16 %fload to i32
   store i32 %ext, i32 addrspace(1)* %out, align 4
   ret void
@@ -166,12 +166,12 @@ define void @zextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)*
 define void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 {
   %alloca = alloca i32, i32 9, align 4
   %x = call i32 @llvm.r600.read.tidig.x() #3
-  %pptr = getelementptr i32* %alloca, i32 %x
+  %pptr = getelementptr i32, i32* %alloca, i32 %x
   %fptr = addrspacecast i32* %pptr to i32 addrspace(4)*
   store i32 %x, i32 addrspace(4)* %fptr
   ; Dummy call
   call void @llvm.AMDGPU.barrier.local() #1
-  %reload = load i32 addrspace(4)* %fptr, align 4
+  %reload = load i32, i32 addrspace(4)* %fptr, align 4
   store i32 %reload, i32 addrspace(1)* %out, align 4
   ret void
 }
diff --git a/test/CodeGen/R600/floor.ll b/test/CodeGen/R600/floor.ll
index 67e86c41fdcf..c6bfb8567a0f 100644
--- a/test/CodeGen/R600/floor.ll
+++ b/test/CodeGen/R600/floor.ll
@@ -1,7 +1,6 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: FLOOR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s
 
+; CHECK: FLOOR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 define void @test(<4 x float> inreg %reg0) #0 {
    %r0 = extractelement <4 x float> %reg0, i32 0
    %r1 = call float @floor(float %r0)
@@ -13,4 +12,4 @@ define void @test(<4 x float> inreg %reg0) #0 {
 declare float @floor(float) readonly
 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
 
-attributes #0 = { "ShaderType"="0" }
\ No newline at end of file
+attributes #0 = { "ShaderType"="0" }
diff --git a/test/CodeGen/R600/fma-combine.ll b/test/CodeGen/R600/fma-combine.ll
new file mode 100644
index 000000000000..bd574b877117
--- /dev/null
+++ b/test/CodeGen/R600/fma-combine.ll
@@ -0,0 +1,368 @@
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -fp-contract=fast < %s | FileCheck -check-prefix=SI-FASTFMAF -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs -fp-contract=fast < %s | FileCheck -check-prefix=SI-SLOWFMAF -check-prefix=SI -check-prefix=FUNC %s
+
+declare i32 @llvm.r600.read.tidig.x() #0
+declare double @llvm.fabs.f64(double) #0
+declare double @llvm.fma.f64(double, double, double) #0
+declare float @llvm.fma.f32(float, float, float) #0
+
+; (fadd (fmul x, y), z) -> (fma x, y, z)
+; FUNC-LABEL: {{^}}combine_to_fma_f64_0:
+; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]]
+; SI: buffer_store_dwordx2 [[RESULT]]
+define void @combine_to_fma_f64_0(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
+  %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
+
+  %a = load double, double addrspace(1)* %gep.0
+  %b = load double, double addrspace(1)* %gep.1
+  %c = load double, double addrspace(1)* %gep.2
+
+  %mul = fmul double %a, %b
+  %fma = fadd double %mul, %c
+  store double %fma, double addrspace(1)* %gep.out
+  ret void
+}
+
+; (fadd (fmul x, y), z) -> (fma x, y, z)
+; FUNC-LABEL: {{^}}combine_to_fma_f64_0_2use:
+; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}}
+; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]]
+; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[D]]
+; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI: s_endpgm
+define void @combine_to_fma_f64_0_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
+  %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
+  %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1
+
+  %a = load double, double addrspace(1)* %gep.0
+  %b = load double, double addrspace(1)* %gep.1
+  %c = load double, double addrspace(1)* %gep.2
+  %d = load double, double addrspace(1)* %gep.3
+
+  %mul = fmul double %a, %b
+  %fma0 = fadd double %mul, %c
+  %fma1 = fadd double %mul, %d
+  store double %fma0, double addrspace(1)* %gep.out.0
+  store double %fma1, double addrspace(1)* %gep.out.1
+  ret void
+}
+
+; (fadd x, (fmul y, z)) -> (fma y, z, x)
+; FUNC-LABEL: {{^}}combine_to_fma_f64_1:
+; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]]
+; SI: buffer_store_dwordx2 [[RESULT]]
+define void @combine_to_fma_f64_1(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
+  %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
+
+  %a = load double, double addrspace(1)* %gep.0
+  %b = load double, double addrspace(1)* %gep.1
+  %c = load double, double addrspace(1)* %gep.2
+
+  %mul = fmul double %a, %b
+  %fma = fadd double %c, %mul
+  store double %fma, double addrspace(1)* %gep.out
+  ret void
+}
+
+; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
+; FUNC-LABEL: {{^}}combine_to_fma_fsub_0_f64:
+; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[C]]
+; SI: buffer_store_dwordx2 [[RESULT]]
+define void @combine_to_fma_fsub_0_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
+  %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
+
+  %a = load double, double addrspace(1)* %gep.0
+  %b = load double, double addrspace(1)* %gep.1
+  %c = load double, double addrspace(1)* %gep.2
+
+  %mul = fmul double %a, %b
+  %fma = fsub double %mul, %c
+  store double %fma, double addrspace(1)* %gep.out
+  ret void
+}
+
+; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
+; FUNC-LABEL: {{^}}combine_to_fma_fsub_f64_0_2use:
+; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}}
+; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[C]]
+; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[D]]
+; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI: s_endpgm
+define void @combine_to_fma_fsub_f64_0_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
+  %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
+  %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1
+
+  %a = load double, double addrspace(1)* %gep.0
+  %b = load double, double addrspace(1)* %gep.1
+  %c = load double, double addrspace(1)* %gep.2
+  %d = load double, double addrspace(1)* %gep.3
+
+  %mul = fmul double %a, %b
+  %fma0 = fsub double %mul, %c
+  %fma1 = fsub double %mul, %d
+  store double %fma0, double addrspace(1)* %gep.out.0
+  store double %fma1, double addrspace(1)* %gep.out.1
+  ret void
+}
+
+; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
+; FUNC-LABEL: {{^}}combine_to_fma_fsub_1_f64:
+; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[C]]
+; SI: buffer_store_dwordx2 [[RESULT]]
+define void @combine_to_fma_fsub_1_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
+  %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
+
+  %a = load double, double addrspace(1)* %gep.0
+  %b = load double, double addrspace(1)* %gep.1
+  %c = load double, double addrspace(1)* %gep.2
+
+  %mul = fmul double %a, %b
+  %fma = fsub double %c, %mul
+  store double %fma, double addrspace(1)* %gep.out
+  ret void
+}
+
+; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
+; FUNC-LABEL: {{^}}combine_to_fma_fsub_1_f64_2use:
+; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}}
+; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[C]]
+; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[D]]
+; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI: s_endpgm
+define void @combine_to_fma_fsub_1_f64_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
+  %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
+  %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1
+
+  %a = load double, double addrspace(1)* %gep.0
+  %b = load double, double addrspace(1)* %gep.1
+  %c = load double, double addrspace(1)* %gep.2
+  %d = load double, double addrspace(1)* %gep.3
+
+  %mul = fmul double %a, %b
+  %fma0 = fsub double %c, %mul
+  %fma1 = fsub double %d, %mul
+  store double %fma0, double addrspace(1)* %gep.out.0
+  store double %fma1, double addrspace(1)* %gep.out.1
+  ret void
+}
+
+; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
+; FUNC-LABEL: {{^}}combine_to_fma_fsub_2_f64:
+; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]]
+; SI: buffer_store_dwordx2 [[RESULT]]
+define void @combine_to_fma_fsub_2_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
+  %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
+
+  %a = load double, double addrspace(1)* %gep.0
+  %b = load double, double addrspace(1)* %gep.1
+  %c = load double, double addrspace(1)* %gep.2
+
+  %mul = fmul double %a, %b
+  %mul.neg = fsub double -0.0, %mul
+  %fma = fsub double %mul.neg, %c
+
+  store double %fma, double addrspace(1)* %gep.out
+  ret void
+}
+
+; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
+; FUNC-LABEL: {{^}}combine_to_fma_fsub_2_f64_2uses_neg:
+; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]]
+; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[D]]
+; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI: s_endpgm
+define void @combine_to_fma_fsub_2_f64_2uses_neg(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
+  %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
+  %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1
+
+  %a = load double, double addrspace(1)* %gep.0
+  %b = load double, double addrspace(1)* %gep.1
+  %c = load double, double addrspace(1)* %gep.2
+  %d = load double, double addrspace(1)* %gep.3
+
+  %mul = fmul double %a, %b
+  %mul.neg = fsub double -0.0, %mul
+  %fma0 = fsub double %mul.neg, %c
+  %fma1 = fsub double %mul.neg, %d
+
+  store double %fma0, double addrspace(1)* %gep.out.0
+  store double %fma1, double addrspace(1)* %gep.out.1
+  ret void
+}
+
+; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
+; FUNC-LABEL: {{^}}combine_to_fma_fsub_2_f64_2uses_mul:
+; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]]
+; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[D]]
+; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI: s_endpgm
+define void @combine_to_fma_fsub_2_f64_2uses_mul(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
+  %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
+  %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1
+
+  %a = load double, double addrspace(1)* %gep.0
+  %b = load double, double addrspace(1)* %gep.1
+  %c = load double, double addrspace(1)* %gep.2
+  %d = load double, double addrspace(1)* %gep.3
+
+  %mul = fmul double %a, %b
+  %mul.neg = fsub double -0.0, %mul
+  %fma0 = fsub double %mul.neg, %c
+  %fma1 = fsub double %mul, %d
+
+  store double %fma0, double addrspace(1)* %gep.out.0
+  store double %fma1, double addrspace(1)* %gep.out.1
+  ret void
+}
+
+; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z)))
+
+; FUNC-LABEL: {{^}}aggressive_combine_to_fma_fsub_0_f64:
+; SI-DAG: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dwordx2 [[Y:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dwordx2 [[Z:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+; SI-DAG: buffer_load_dwordx2 [[U:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}}
+; SI-DAG: buffer_load_dwordx2 [[V:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:32{{$}}
+; SI: v_fma_f64 [[FMA0:v\[[0-9]+:[0-9]+\]]], [[U]], [[V]], -[[Z]]
+; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[X]], [[Y]], [[FMA0]]
+; SI: buffer_store_dwordx2 [[RESULT]]
+define void @aggressive_combine_to_fma_fsub_0_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
+  %gep.4 = getelementptr double, double addrspace(1)* %gep.0, i32 4
+  %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
+
+  %x = load double, double addrspace(1)* %gep.0
+  %y = load double, double addrspace(1)* %gep.1
+  %z = load double, double addrspace(1)* %gep.2
+  %u = load double, double addrspace(1)* %gep.3
+  %v = load double, double addrspace(1)* %gep.4
+
+  %tmp0 = fmul double %u, %v
+  %tmp1 = call double @llvm.fma.f64(double %x, double %y, double %tmp0) #0
+  %tmp2 = fsub double %tmp1, %z
+
+  store double %tmp2, double addrspace(1)* %gep.out
+  ret void
+}
+
+; fold (fsub x, (fma y, z, (fmul u, v)))
+;   -> (fma (fneg y), z, (fma (fneg u), v, x))
+
+; FUNC-LABEL: {{^}}aggressive_combine_to_fma_fsub_1_f64:
+; SI-DAG: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dwordx2 [[Y:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dwordx2 [[Z:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+; SI-DAG: buffer_load_dwordx2 [[U:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}}
+; SI-DAG: buffer_load_dwordx2 [[V:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:32{{$}}
+; SI: v_fma_f64 [[FMA0:v\[[0-9]+:[0-9]+\]]], -[[U]], [[V]], [[X]]
+; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[Y]], [[Z]], [[FMA0]]
+; SI: buffer_store_dwordx2 [[RESULT]]
+define void @aggressive_combine_to_fma_fsub_1_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
+  %gep.4 = getelementptr double, double addrspace(1)* %gep.0, i32 4
+  %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
+
+  %x = load double, double addrspace(1)* %gep.0
+  %y = load double, double addrspace(1)* %gep.1
+  %z = load double, double addrspace(1)* %gep.2
+  %u = load double, double addrspace(1)* %gep.3
+  %v = load double, double addrspace(1)* %gep.4
+
+  %tmp0 = fmul double %u, %v
+  %tmp1 = call double @llvm.fma.f64(double %y, double %z, double %tmp0) #0
+  %tmp2 = fsub double %x, %tmp1
+
+  store double %tmp2, double addrspace(1)* %gep.out
+  ret void
+}
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }
diff --git a/test/CodeGen/R600/fma.f64.ll b/test/CodeGen/R600/fma.f64.ll
index bca312bfa751..0a55ef778557 100644
--- a/test/CodeGen/R600/fma.f64.ll
+++ b/test/CodeGen/R600/fma.f64.ll
@@ -10,9 +10,9 @@ declare <4 x double> @llvm.fma.v4f64(<4 x double>, <4 x double>, <4 x double>) n
 ; SI: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
 define void @fma_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
                      double addrspace(1)* %in2, double addrspace(1)* %in3) {
-   %r0 = load double addrspace(1)* %in1
-   %r1 = load double addrspace(1)* %in2
-   %r2 = load double addrspace(1)* %in3
+   %r0 = load double, double addrspace(1)* %in1
+   %r1 = load double, double addrspace(1)* %in2
+   %r2 = load double, double addrspace(1)* %in3
    %r3 = tail call double @llvm.fma.f64(double %r0, double %r1, double %r2)
    store double %r3, double addrspace(1)* %out
    ret void
@@ -23,9 +23,9 @@ define void @fma_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
 ; SI: v_fma_f64
 define void @fma_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1,
                        <2 x double> addrspace(1)* %in2, <2 x double> addrspace(1)* %in3) {
-   %r0 = load <2 x double> addrspace(1)* %in1
-   %r1 = load <2 x double> addrspace(1)* %in2
-   %r2 = load <2 x double> addrspace(1)* %in3
+   %r0 = load <2 x double>, <2 x double> addrspace(1)* %in1
+   %r1 = load <2 x double>, <2 x double> addrspace(1)* %in2
+   %r2 = load <2 x double>, <2 x double> addrspace(1)* %in3
    %r3 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %r0, <2 x double> %r1, <2 x double> %r2)
    store <2 x double> %r3, <2 x double> addrspace(1)* %out
    ret void
@@ -38,9 +38,9 @@ define void @fma_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1
 ; SI: v_fma_f64
 define void @fma_v4f64(<4 x double> addrspace(1)* %out, <4 x double> addrspace(1)* %in1,
                        <4 x double> addrspace(1)* %in2, <4 x double> addrspace(1)* %in3) {
-   %r0 = load <4 x double> addrspace(1)* %in1
-   %r1 = load <4 x double> addrspace(1)* %in2
-   %r2 = load <4 x double> addrspace(1)* %in3
+   %r0 = load <4 x double>, <4 x double> addrspace(1)* %in1
+   %r1 = load <4 x double>, <4 x double> addrspace(1)* %in2
+   %r2 = load <4 x double>, <4 x double> addrspace(1)* %in3
    %r3 = tail call <4 x double> @llvm.fma.v4f64(<4 x double> %r0, <4 x double> %r1, <4 x double> %r2)
    store <4 x double> %r3, <4 x double> addrspace(1)* %out
    ret void
diff --git a/test/CodeGen/R600/fma.ll b/test/CodeGen/R600/fma.ll
index f3861ffa2835..d6024aa0b4c5 100644
--- a/test/CodeGen/R600/fma.ll
+++ b/test/CodeGen/R600/fma.ll
@@ -14,9 +14,9 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone
 ; EG: FMA {{\*? *}}[[RES]]
 define void @fma_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
                      float addrspace(1)* %in2, float addrspace(1)* %in3) {
-  %r0 = load float addrspace(1)* %in1
-  %r1 = load float addrspace(1)* %in2
-  %r2 = load float addrspace(1)* %in3
+  %r0 = load float, float addrspace(1)* %in1
+  %r1 = load float, float addrspace(1)* %in2
+  %r2 = load float, float addrspace(1)* %in3
   %r3 = tail call float @llvm.fma.f32(float %r0, float %r1, float %r2)
   store float %r3, float addrspace(1)* %out
   ret void
@@ -31,9 +31,9 @@ define void @fma_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
 ; EG-DAG: FMA {{\*? *}}[[RES]].[[CHHI]]
 define void @fma_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in1,
                        <2 x float> addrspace(1)* %in2, <2 x float> addrspace(1)* %in3) {
-  %r0 = load <2 x float> addrspace(1)* %in1
-  %r1 = load <2 x float> addrspace(1)* %in2
-  %r2 = load <2 x float> addrspace(1)* %in3
+  %r0 = load <2 x float>, <2 x float> addrspace(1)* %in1
+  %r1 = load <2 x float>, <2 x float> addrspace(1)* %in2
+  %r2 = load <2 x float>, <2 x float> addrspace(1)* %in3
   %r3 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %r0, <2 x float> %r1, <2 x float> %r2)
   store <2 x float> %r3, <2 x float> addrspace(1)* %out
   ret void
@@ -52,9 +52,9 @@ define void @fma_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)*
 ; EG-DAG: FMA {{\*? *}}[[RES]].W
 define void @fma_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in1,
                        <4 x float> addrspace(1)* %in2, <4 x float> addrspace(1)* %in3) {
-  %r0 = load <4 x float> addrspace(1)* %in1
-  %r1 = load <4 x float> addrspace(1)* %in2
-  %r2 = load <4 x float> addrspace(1)* %in3
+  %r0 = load <4 x float>, <4 x float> addrspace(1)* %in1
+  %r1 = load <4 x float>, <4 x float> addrspace(1)* %in2
+  %r2 = load <4 x float>, <4 x float> addrspace(1)* %in3
   %r3 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %r0, <4 x float> %r1, <4 x float> %r2)
   store <4 x float> %r3, <4 x float> addrspace(1)* %out
   ret void
@@ -64,12 +64,12 @@ define void @fma_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)*
 ; SI: v_fma_f32 {{v[0-9]+}}, 2.0, {{v[0-9]+}}, {{v[0-9]+}}
 define void @fma_commute_mul_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
   %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %in.a.gep = getelementptr float addrspace(1)* %in.a, i32 %tid
-  %in.b.gep = getelementptr float addrspace(1)* %in.b, i32 %tid
-  %out.gep = getelementptr float addrspace(1)* %out, i32 %tid
+  %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
+  %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
 
-  %a = load float addrspace(1)* %in.a.gep, align 4
-  %b = load float addrspace(1)* %in.b.gep, align 4
+  %a = load float, float addrspace(1)* %in.a.gep, align 4
+  %b = load float, float addrspace(1)* %in.b.gep, align 4
 
   %fma = call float @llvm.fma.f32(float %a, float 2.0, float %b)
   store float %fma, float addrspace(1)* %out.gep, align 4
@@ -79,12 +79,12 @@ define void @fma_commute_mul_inline_imm_f32(float addrspace(1)* noalias %out, fl
 ; FUNC-LABEL: @fma_commute_mul_s_f32
 define void @fma_commute_mul_s_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b, float %b) nounwind {
   %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %in.a.gep = getelementptr float addrspace(1)* %in.a, i32 %tid
-  %in.b.gep = getelementptr float addrspace(1)* %in.b, i32 %tid
-  %out.gep = getelementptr float addrspace(1)* %out, i32 %tid
+  %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
+  %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
 
-  %a = load float addrspace(1)* %in.a.gep, align 4
-  %c = load float addrspace(1)* %in.b.gep, align 4
+  %a = load float, float addrspace(1)* %in.a.gep, align 4
+  %c = load float, float addrspace(1)* %in.b.gep, align 4
 
   %fma = call float @llvm.fma.f32(float %a, float %b, float %c)
   store float %fma, float addrspace(1)* %out.gep, align 4
diff --git a/test/CodeGen/R600/fmax3.f64.ll b/test/CodeGen/R600/fmax3.f64.ll
index 5ca789de2a08..f78c71b28264 100644
--- a/test/CodeGen/R600/fmax3.f64.ll
+++ b/test/CodeGen/R600/fmax3.f64.ll
@@ -12,11 +12,11 @@ declare double @llvm.maxnum.f64(double, double) nounwind readnone
 ; SI: buffer_store_dwordx2 [[RESULT]],
 ; SI: s_endpgm
 define void @test_fmax3_f64(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind {
-  %bptr = getelementptr double addrspace(1)* %aptr, i32 1
-  %cptr = getelementptr double addrspace(1)* %aptr, i32 2
-  %a = load double addrspace(1)* %aptr, align 8
-  %b = load double addrspace(1)* %bptr, align 8
-  %c = load double addrspace(1)* %cptr, align 8
+  %bptr = getelementptr double, double addrspace(1)* %aptr, i32 1
+  %cptr = getelementptr double, double addrspace(1)* %aptr, i32 2
+  %a = load double, double addrspace(1)* %aptr, align 8
+  %b = load double, double addrspace(1)* %bptr, align 8
+  %c = load double, double addrspace(1)* %cptr, align 8
   %f0 = call double @llvm.maxnum.f64(double %a, double %b) nounwind readnone
   %f1 = call double @llvm.maxnum.f64(double %f0, double %c) nounwind readnone
   store double %f1, double addrspace(1)* %out, align 8
diff --git a/test/CodeGen/R600/fmax3.ll b/test/CodeGen/R600/fmax3.ll
index e1b477c5921e..c3028a6217d5 100644
--- a/test/CodeGen/R600/fmax3.ll
+++ b/test/CodeGen/R600/fmax3.ll
@@ -4,16 +4,16 @@
 declare float @llvm.maxnum.f32(float, float) nounwind readnone
 
 ; SI-LABEL: {{^}}test_fmax3_olt_0:
-; SI: buffer_load_dword [[REGA:v[0-9]+]]
-; SI: buffer_load_dword [[REGB:v[0-9]+]]
 ; SI: buffer_load_dword [[REGC:v[0-9]+]]
+; SI: buffer_load_dword [[REGB:v[0-9]+]]
+; SI: buffer_load_dword [[REGA:v[0-9]+]]
 ; SI: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
 ; SI: buffer_store_dword [[RESULT]],
 ; SI: s_endpgm
 define void @test_fmax3_olt_0(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
-  %a = load float addrspace(1)* %aptr, align 4
-  %b = load float addrspace(1)* %bptr, align 4
-  %c = load float addrspace(1)* %cptr, align 4
+  %a = load float, float addrspace(1)* %aptr, align 4
+  %b = load float, float addrspace(1)* %bptr, align 4
+  %c = load float, float addrspace(1)* %cptr, align 4
   %f0 = call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone
   %f1 = call float @llvm.maxnum.f32(float %f0, float %c) nounwind readnone
   store float %f1, float addrspace(1)* %out, align 4
@@ -22,16 +22,16 @@ define void @test_fmax3_olt_0(float addrspace(1)* %out, float addrspace(1)* %apt
 
 ; Commute operand of second fmax
 ; SI-LABEL: {{^}}test_fmax3_olt_1:
-; SI: buffer_load_dword [[REGA:v[0-9]+]]
 ; SI: buffer_load_dword [[REGB:v[0-9]+]]
+; SI: buffer_load_dword [[REGA:v[0-9]+]]
 ; SI: buffer_load_dword [[REGC:v[0-9]+]]
 ; SI: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
 ; SI: buffer_store_dword [[RESULT]],
 ; SI: s_endpgm
 define void @test_fmax3_olt_1(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
-  %a = load float addrspace(1)* %aptr, align 4
-  %b = load float addrspace(1)* %bptr, align 4
-  %c = load float addrspace(1)* %cptr, align 4
+  %a = load float, float addrspace(1)* %aptr, align 4
+  %b = load float, float addrspace(1)* %bptr, align 4
+  %c = load float, float addrspace(1)* %cptr, align 4
   %f0 = call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone
   %f1 = call float @llvm.maxnum.f32(float %c, float %f0) nounwind readnone
   store float %f1, float addrspace(1)* %out, align 4
diff --git a/test/CodeGen/R600/fmax_legacy.f64.ll b/test/CodeGen/R600/fmax_legacy.f64.ll
index a615825a45d3..828243888ac7 100644
--- a/test/CodeGen/R600/fmax_legacy.f64.ll
+++ b/test/CodeGen/R600/fmax_legacy.f64.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 ; Make sure we don't try to form FMAX_LEGACY nodes with f64
 
 declare i32 @llvm.r600.read.tidig.x() #1
@@ -6,11 +6,11 @@ declare i32 @llvm.r600.read.tidig.x() #1
 ; FUNC-LABEL: @test_fmax_legacy_uge_f64
 define void @test_fmax_legacy_uge_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr double addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr double addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
 
-  %a = load double addrspace(1)* %gep.0, align 8
-  %b = load double addrspace(1)* %gep.1, align 8
+  %a = load double, double addrspace(1)* %gep.0, align 8
+  %b = load double, double addrspace(1)* %gep.1, align 8
 
   %cmp = fcmp uge double %a, %b
   %val = select i1 %cmp, double %a, double %b
@@ -21,11 +21,11 @@ define void @test_fmax_legacy_uge_f64(double addrspace(1)* %out, double addrspac
 ; FUNC-LABEL: @test_fmax_legacy_oge_f64
 define void @test_fmax_legacy_oge_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr double addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr double addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
 
-  %a = load double addrspace(1)* %gep.0, align 8
-  %b = load double addrspace(1)* %gep.1, align 8
+  %a = load double, double addrspace(1)* %gep.0, align 8
+  %b = load double, double addrspace(1)* %gep.1, align 8
 
   %cmp = fcmp oge double %a, %b
   %val = select i1 %cmp, double %a, double %b
@@ -36,11 +36,11 @@ define void @test_fmax_legacy_oge_f64(double addrspace(1)* %out, double addrspac
 ; FUNC-LABEL: @test_fmax_legacy_ugt_f64
 define void @test_fmax_legacy_ugt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr double addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr double addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
 
-  %a = load double addrspace(1)* %gep.0, align 8
-  %b = load double addrspace(1)* %gep.1, align 8
+  %a = load double, double addrspace(1)* %gep.0, align 8
+  %b = load double, double addrspace(1)* %gep.1, align 8
 
   %cmp = fcmp ugt double %a, %b
   %val = select i1 %cmp, double %a, double %b
@@ -51,11 +51,11 @@ define void @test_fmax_legacy_ugt_f64(double addrspace(1)* %out, double addrspac
 ; FUNC-LABEL: @test_fmax_legacy_ogt_f64
 define void @test_fmax_legacy_ogt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr double addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr double addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
 
-  %a = load double addrspace(1)* %gep.0, align 8
-  %b = load double addrspace(1)* %gep.1, align 8
+  %a = load double, double addrspace(1)* %gep.0, align 8
+  %b = load double, double addrspace(1)* %gep.1, align 8
 
   %cmp = fcmp ogt double %a, %b
   %val = select i1 %cmp, double %a, double %b
diff --git a/test/CodeGen/R600/fmax_legacy.ll b/test/CodeGen/R600/fmax_legacy.ll
index 46f0e9831e6a..413957d2982a 100644
--- a/test/CodeGen/R600/fmax_legacy.ll
+++ b/test/CodeGen/R600/fmax_legacy.ll
@@ -15,11 +15,11 @@ declare i32 @llvm.r600.read.tidig.x() #1
 ; EG: MAX
 define void @test_fmax_legacy_uge_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
 
-  %a = load float addrspace(1)* %gep.0, align 4
-  %b = load float addrspace(1)* %gep.1, align 4
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
 
   %cmp = fcmp uge float %a, %b
   %val = select i1 %cmp, float %a, float %b
@@ -35,11 +35,11 @@ define void @test_fmax_legacy_uge_f32(float addrspace(1)* %out, float addrspace(
 ; EG: MAX
 define void @test_fmax_legacy_oge_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
 
-  %a = load float addrspace(1)* %gep.0, align 4
-  %b = load float addrspace(1)* %gep.1, align 4
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
 
   %cmp = fcmp oge float %a, %b
   %val = select i1 %cmp, float %a, float %b
@@ -55,11 +55,11 @@ define void @test_fmax_legacy_oge_f32(float addrspace(1)* %out, float addrspace(
 ; EG: MAX
 define void @test_fmax_legacy_ugt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
 
-  %a = load float addrspace(1)* %gep.0, align 4
-  %b = load float addrspace(1)* %gep.1, align 4
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
 
   %cmp = fcmp ugt float %a, %b
   %val = select i1 %cmp, float %a, float %b
@@ -75,11 +75,11 @@ define void @test_fmax_legacy_ugt_f32(float addrspace(1)* %out, float addrspace(
 ; EG: MAX
 define void @test_fmax_legacy_ogt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
 
-  %a = load float addrspace(1)* %gep.0, align 4
-  %b = load float addrspace(1)* %gep.1, align 4
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
 
   %cmp = fcmp ogt float %a, %b
   %val = select i1 %cmp, float %a, float %b
@@ -99,11 +99,11 @@ define void @test_fmax_legacy_ogt_f32(float addrspace(1)* %out, float addrspace(
 ; EG: MAX
 define void @test_fmax_legacy_ogt_f32_multi_use(float addrspace(1)* %out0, i1 addrspace(1)* %out1, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
 
-  %a = load float addrspace(1)* %gep.0, align 4
-  %b = load float addrspace(1)* %gep.1, align 4
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
 
   %cmp = fcmp ogt float %a, %b
   %val = select i1 %cmp, float %a, float %b
diff --git a/test/CodeGen/R600/fmaxnum.ll b/test/CodeGen/R600/fmaxnum.ll
index c105598ff811..3029bd02e4db 100644
--- a/test/CodeGen/R600/fmaxnum.ll
+++ b/test/CodeGen/R600/fmaxnum.ll
@@ -11,6 +11,9 @@ declare double @llvm.maxnum.f64(double, double)
 
 ; FUNC-LABEL: @test_fmax_f32
 ; SI: v_max_f32_e32
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG: MAX_DX10 {{.*}}[[OUT]]
 define void @test_fmax_f32(float addrspace(1)* %out, float %a, float %b) nounwind {
   %val = call float @llvm.maxnum.f32(float %a, float %b) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -20,6 +23,10 @@ define void @test_fmax_f32(float addrspace(1)* %out, float %a, float %b) nounwin
 ; FUNC-LABEL: @test_fmax_v2f32
 ; SI: v_max_f32_e32
 ; SI: v_max_f32_e32
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]]
+; EG: MAX_DX10 {{.*}}[[OUT]]
+; EG: MAX_DX10 {{.*}}[[OUT]]
 define void @test_fmax_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) nounwind {
   %val = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b) #0
   store <2 x float> %val, <2 x float> addrspace(1)* %out, align 8
@@ -31,6 +38,12 @@ define void @test_fmax_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2
 ; SI: v_max_f32_e32
 ; SI: v_max_f32_e32
 ; SI: v_max_f32_e32
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]]
+; EG: MAX_DX10 {{.*}}[[OUT]]
+; EG: MAX_DX10 {{.*}}[[OUT]]
+; EG: MAX_DX10 {{.*}}[[OUT]]
+; EG: MAX_DX10 {{.*}}[[OUT]]
 define void @test_fmax_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) nounwind {
   %val = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b) #0
   store <4 x float> %val, <4 x float> addrspace(1)* %out, align 16
@@ -46,6 +59,17 @@ define void @test_fmax_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4
 ; SI: v_max_f32_e32
 ; SI: v_max_f32_e32
 ; SI: v_max_f32_e32
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]]
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]]
+; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].X
+; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Y
+; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Z
+; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].W
+; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].X
+; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Y
+; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Z
+; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].W
 define void @test_fmax_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind {
   %val = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %a, <8 x float> %b) #0
   store <8 x float> %val, <8 x float> addrspace(1)* %out, align 32
@@ -69,6 +93,27 @@ define void @test_fmax_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8
 ; SI: v_max_f32_e32
 ; SI: v_max_f32_e32
 ; SI: v_max_f32_e32
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]]
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]]
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT3:T[0-9]+]]
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT4:T[0-9]+]]
+; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].X
+; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Y
+; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Z
+; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].W
+; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].X
+; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Y
+; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Z
+; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].W
+; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].X
+; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].Y
+; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].Z
+; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].W
+; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].X
+; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].Y
+; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].Z
+; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].W
 define void @test_fmax_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) nounwind {
   %val = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %a, <16 x float> %b) #0
   store <16 x float> %val, <16 x float> addrspace(1)* %out, align 64
@@ -79,6 +124,10 @@ define void @test_fmax_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a,
 ; SI-NOT: v_max_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MAX_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
 define void @constant_fold_fmax_f32(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.maxnum.f32(float 1.0, float 2.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -89,6 +138,11 @@ define void @constant_fold_fmax_f32(float addrspace(1)* %out) nounwind {
 ; SI-NOT: v_max_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MAX_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
+; EG: 2143289344(nan)
 define void @constant_fold_fmax_f32_nan_nan(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -99,6 +153,10 @@ define void @constant_fold_fmax_f32_nan_nan(float addrspace(1)* %out) nounwind {
 ; SI-NOT: v_max_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MAX_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
 define void @constant_fold_fmax_f32_val_nan(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.maxnum.f32(float 1.0, float 0x7FF8000000000000) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -109,6 +167,10 @@ define void @constant_fold_fmax_f32_val_nan(float addrspace(1)* %out) nounwind {
 ; SI-NOT: v_max_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MAX_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
 define void @constant_fold_fmax_f32_nan_val(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 1.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -119,6 +181,10 @@ define void @constant_fold_fmax_f32_nan_val(float addrspace(1)* %out) nounwind {
 ; SI-NOT: v_max_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MAX_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
 define void @constant_fold_fmax_f32_p0_p0(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.maxnum.f32(float 0.0, float 0.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -129,6 +195,10 @@ define void @constant_fold_fmax_f32_p0_p0(float addrspace(1)* %out) nounwind {
 ; SI-NOT: v_max_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MAX_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
 define void @constant_fold_fmax_f32_p0_n0(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.maxnum.f32(float 0.0, float -0.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -139,6 +209,10 @@ define void @constant_fold_fmax_f32_p0_n0(float addrspace(1)* %out) nounwind {
 ; SI-NOT: v_max_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MAX_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
 define void @constant_fold_fmax_f32_n0_p0(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.maxnum.f32(float -0.0, float 0.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -149,6 +223,10 @@ define void @constant_fold_fmax_f32_n0_p0(float addrspace(1)* %out) nounwind {
 ; SI-NOT: v_max_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MAX_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
 define void @constant_fold_fmax_f32_n0_n0(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.maxnum.f32(float -0.0, float -0.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -157,6 +235,10 @@ define void @constant_fold_fmax_f32_n0_n0(float addrspace(1)* %out) nounwind {
 
 ; FUNC-LABEL: @fmax_var_immediate_f32
 ; SI: v_max_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}}
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MAX_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
 define void @fmax_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind {
   %val = call float @llvm.maxnum.f32(float %a, float 2.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -165,6 +247,9 @@ define void @fmax_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind
 
 ; FUNC-LABEL: @fmax_immediate_var_f32
 ; SI: v_max_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}}
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG: MAX_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
 define void @fmax_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind {
   %val = call float @llvm.maxnum.f32(float 2.0, float %a) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -174,6 +259,9 @@ define void @fmax_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind
 ; FUNC-LABEL: @fmax_var_literal_f32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
 ; SI: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG: MAX_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
 define void @fmax_var_literal_f32(float addrspace(1)* %out, float %a) nounwind {
   %val = call float @llvm.maxnum.f32(float %a, float 99.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -183,6 +271,9 @@ define void @fmax_var_literal_f32(float addrspace(1)* %out, float %a) nounwind {
 ; FUNC-LABEL: @fmax_literal_var_f32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
 ; SI: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG: MAX_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
 define void @fmax_literal_var_f32(float addrspace(1)* %out, float %a) nounwind {
   %val = call float @llvm.maxnum.f32(float 99.0, float %a) #0
   store float %val, float addrspace(1)* %out, align 4
diff --git a/test/CodeGen/R600/fmin3.ll b/test/CodeGen/R600/fmin3.ll
index 716beb16bb10..0a76699b43e1 100644
--- a/test/CodeGen/R600/fmin3.ll
+++ b/test/CodeGen/R600/fmin3.ll
@@ -5,16 +5,16 @@
 declare float @llvm.minnum.f32(float, float) nounwind readnone
 
 ; SI-LABEL: {{^}}test_fmin3_olt_0:
-; SI: buffer_load_dword [[REGA:v[0-9]+]]
-; SI: buffer_load_dword [[REGB:v[0-9]+]]
 ; SI: buffer_load_dword [[REGC:v[0-9]+]]
+; SI: buffer_load_dword [[REGB:v[0-9]+]]
+; SI: buffer_load_dword [[REGA:v[0-9]+]]
 ; SI: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
 ; SI: buffer_store_dword [[RESULT]],
 ; SI: s_endpgm
 define void @test_fmin3_olt_0(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
-  %a = load float addrspace(1)* %aptr, align 4
-  %b = load float addrspace(1)* %bptr, align 4
-  %c = load float addrspace(1)* %cptr, align 4
+  %a = load float, float addrspace(1)* %aptr, align 4
+  %b = load float, float addrspace(1)* %bptr, align 4
+  %c = load float, float addrspace(1)* %cptr, align 4
   %f0 = call float @llvm.minnum.f32(float %a, float %b) nounwind readnone
   %f1 = call float @llvm.minnum.f32(float %f0, float %c) nounwind readnone
   store float %f1, float addrspace(1)* %out, align 4
@@ -23,16 +23,16 @@ define void @test_fmin3_olt_0(float addrspace(1)* %out, float addrspace(1)* %apt
 
 ; Commute operand of second fmin
 ; SI-LABEL: {{^}}test_fmin3_olt_1:
-; SI: buffer_load_dword [[REGA:v[0-9]+]]
 ; SI: buffer_load_dword [[REGB:v[0-9]+]]
+; SI: buffer_load_dword [[REGA:v[0-9]+]]
 ; SI: buffer_load_dword [[REGC:v[0-9]+]]
 ; SI: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
 ; SI: buffer_store_dword [[RESULT]],
 ; SI: s_endpgm
 define void @test_fmin3_olt_1(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
-  %a = load float addrspace(1)* %aptr, align 4
-  %b = load float addrspace(1)* %bptr, align 4
-  %c = load float addrspace(1)* %cptr, align 4
+  %a = load float, float addrspace(1)* %aptr, align 4
+  %b = load float, float addrspace(1)* %bptr, align 4
+  %c = load float, float addrspace(1)* %cptr, align 4
   %f0 = call float @llvm.minnum.f32(float %a, float %b) nounwind readnone
   %f1 = call float @llvm.minnum.f32(float %c, float %f0) nounwind readnone
   store float %f1, float addrspace(1)* %out, align 4
diff --git a/test/CodeGen/R600/fmin_legacy.f64.ll b/test/CodeGen/R600/fmin_legacy.f64.ll
index 51dcd06f9397..e19a48f3f7e2 100644
--- a/test/CodeGen/R600/fmin_legacy.f64.ll
+++ b/test/CodeGen/R600/fmin_legacy.f64.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
 declare i32 @llvm.r600.read.tidig.x() #1
 
@@ -16,11 +16,11 @@ define void @test_fmin_legacy_f64(<4 x double> addrspace(1)* %out, <4 x double>
 ; FUNC-LABEL: @test_fmin_legacy_ule_f64
 define void @test_fmin_legacy_ule_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr double addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr double addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
 
-  %a = load double addrspace(1)* %gep.0, align 8
-  %b = load double addrspace(1)* %gep.1, align 8
+  %a = load double, double addrspace(1)* %gep.0, align 8
+  %b = load double, double addrspace(1)* %gep.1, align 8
 
   %cmp = fcmp ule double %a, %b
   %val = select i1 %cmp, double %a, double %b
@@ -31,11 +31,11 @@ define void @test_fmin_legacy_ule_f64(double addrspace(1)* %out, double addrspac
 ; FUNC-LABEL: @test_fmin_legacy_ole_f64
 define void @test_fmin_legacy_ole_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr double addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr double addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
 
-  %a = load double addrspace(1)* %gep.0, align 8
-  %b = load double addrspace(1)* %gep.1, align 8
+  %a = load double, double addrspace(1)* %gep.0, align 8
+  %b = load double, double addrspace(1)* %gep.1, align 8
 
   %cmp = fcmp ole double %a, %b
   %val = select i1 %cmp, double %a, double %b
@@ -46,11 +46,11 @@ define void @test_fmin_legacy_ole_f64(double addrspace(1)* %out, double addrspac
 ; FUNC-LABEL: @test_fmin_legacy_olt_f64
 define void @test_fmin_legacy_olt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr double addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr double addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
 
-  %a = load double addrspace(1)* %gep.0, align 8
-  %b = load double addrspace(1)* %gep.1, align 8
+  %a = load double, double addrspace(1)* %gep.0, align 8
+  %b = load double, double addrspace(1)* %gep.1, align 8
 
   %cmp = fcmp olt double %a, %b
   %val = select i1 %cmp, double %a, double %b
@@ -61,11 +61,11 @@ define void @test_fmin_legacy_olt_f64(double addrspace(1)* %out, double addrspac
 ; FUNC-LABEL: @test_fmin_legacy_ult_f64
 define void @test_fmin_legacy_ult_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr double addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr double addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
 
-  %a = load double addrspace(1)* %gep.0, align 8
-  %b = load double addrspace(1)* %gep.1, align 8
+  %a = load double, double addrspace(1)* %gep.0, align 8
+  %b = load double, double addrspace(1)* %gep.1, align 8
 
   %cmp = fcmp ult double %a, %b
   %val = select i1 %cmp, double %a, double %b
diff --git a/test/CodeGen/R600/fmin_legacy.ll b/test/CodeGen/R600/fmin_legacy.ll
index 5014f6c55329..6a625c239d76 100644
--- a/test/CodeGen/R600/fmin_legacy.ll
+++ b/test/CodeGen/R600/fmin_legacy.ll
@@ -27,11 +27,11 @@ define void @test_fmin_legacy_f32(<4 x float> addrspace(1)* %out, <4 x float> in
 ; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
 define void @test_fmin_legacy_ule_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
 
-  %a = load float addrspace(1)* %gep.0, align 4
-  %b = load float addrspace(1)* %gep.1, align 4
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
 
   %cmp = fcmp ule float %a, %b
   %val = select i1 %cmp, float %a, float %b
@@ -46,11 +46,11 @@ define void @test_fmin_legacy_ule_f32(float addrspace(1)* %out, float addrspace(
 ; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
 define void @test_fmin_legacy_ole_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
 
-  %a = load float addrspace(1)* %gep.0, align 4
-  %b = load float addrspace(1)* %gep.1, align 4
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
 
   %cmp = fcmp ole float %a, %b
   %val = select i1 %cmp, float %a, float %b
@@ -65,11 +65,11 @@ define void @test_fmin_legacy_ole_f32(float addrspace(1)* %out, float addrspace(
 ; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
 define void @test_fmin_legacy_olt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
 
-  %a = load float addrspace(1)* %gep.0, align 4
-  %b = load float addrspace(1)* %gep.1, align 4
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
 
   %cmp = fcmp olt float %a, %b
   %val = select i1 %cmp, float %a, float %b
@@ -84,11 +84,11 @@ define void @test_fmin_legacy_olt_f32(float addrspace(1)* %out, float addrspace(
 ; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
 define void @test_fmin_legacy_ult_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
 
-  %a = load float addrspace(1)* %gep.0, align 4
-  %b = load float addrspace(1)* %gep.1, align 4
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
 
   %cmp = fcmp ult float %a, %b
   %val = select i1 %cmp, float %a, float %b
@@ -106,11 +106,11 @@ define void @test_fmin_legacy_ult_f32(float addrspace(1)* %out, float addrspace(
 ; SI: s_endpgm
 define void @test_fmin_legacy_ole_f32_multi_use(float addrspace(1)* %out0, i1 addrspace(1)* %out1, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
 
-  %a = load float addrspace(1)* %gep.0, align 4
-  %b = load float addrspace(1)* %gep.1, align 4
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
 
   %cmp = fcmp ole float %a, %b
   %val0 = select i1 %cmp, float %a, float %b
diff --git a/test/CodeGen/R600/fminnum.ll b/test/CodeGen/R600/fminnum.ll
index 6b93b830033b..4d7b52540d85 100644
--- a/test/CodeGen/R600/fminnum.ll
+++ b/test/CodeGen/R600/fminnum.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 ; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 
 declare float @llvm.minnum.f32(float, float) #0
 declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) #0
@@ -9,6 +10,9 @@ declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>) #0
 
 ; FUNC-LABEL: @test_fmin_f32
 ; SI: v_min_f32_e32
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG: MIN_DX10 {{.*}}[[OUT]]
 define void @test_fmin_f32(float addrspace(1)* %out, float %a, float %b) nounwind {
   %val = call float @llvm.minnum.f32(float %a, float %b) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -18,6 +22,10 @@ define void @test_fmin_f32(float addrspace(1)* %out, float %a, float %b) nounwin
 ; FUNC-LABEL: @test_fmin_v2f32
 ; SI: v_min_f32_e32
 ; SI: v_min_f32_e32
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]]
+; EG: MIN_DX10 {{.*}}[[OUT]]
+; EG: MIN_DX10 {{.*}}[[OUT]]
 define void @test_fmin_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) nounwind {
   %val = call <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %b) #0
   store <2 x float> %val, <2 x float> addrspace(1)* %out, align 8
@@ -29,6 +37,12 @@ define void @test_fmin_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2
 ; SI: v_min_f32_e32
 ; SI: v_min_f32_e32
 ; SI: v_min_f32_e32
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]]
+; EG: MIN_DX10 {{.*}}[[OUT]]
+; EG: MIN_DX10 {{.*}}[[OUT]]
+; EG: MIN_DX10 {{.*}}[[OUT]]
+; EG: MIN_DX10 {{.*}}[[OUT]]
 define void @test_fmin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) nounwind {
   %val = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b) #0
   store <4 x float> %val, <4 x float> addrspace(1)* %out, align 16
@@ -44,6 +58,17 @@ define void @test_fmin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4
 ; SI: v_min_f32_e32
 ; SI: v_min_f32_e32
 ; SI: v_min_f32_e32
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]]
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]]
+; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].X
+; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Y
+; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Z
+; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].W
+; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].X
+; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Y
+; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Z
+; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].W
 define void @test_fmin_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind {
   %val = call <8 x float> @llvm.minnum.v8f32(<8 x float> %a, <8 x float> %b) #0
   store <8 x float> %val, <8 x float> addrspace(1)* %out, align 32
@@ -67,6 +92,27 @@ define void @test_fmin_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8
 ; SI: v_min_f32_e32
 ; SI: v_min_f32_e32
 ; SI: v_min_f32_e32
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]]
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]]
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT3:T[0-9]+]]
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT4:T[0-9]+]]
+; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].X
+; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Y
+; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Z
+; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].W
+; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].X
+; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Y
+; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Z
+; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].W
+; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].X
+; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].Y
+; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].Z
+; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].W
+; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].X
+; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].Y
+; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].Z
+; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].W
 define void @test_fmin_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) nounwind {
   %val = call <16 x float> @llvm.minnum.v16f32(<16 x float> %a, <16 x float> %b) #0
   store <16 x float> %val, <16 x float> addrspace(1)* %out, align 64
@@ -77,6 +123,10 @@ define void @test_fmin_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a,
 ; SI-NOT: v_min_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MIN_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
 define void @constant_fold_fmin_f32(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.minnum.f32(float 1.0, float 2.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -87,6 +137,11 @@ define void @constant_fold_fmin_f32(float addrspace(1)* %out) nounwind {
 ; SI-NOT: v_min_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MIN_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
+; EG: 2143289344({{nan|1\.#QNAN0e\+00}})
 define void @constant_fold_fmin_f32_nan_nan(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -97,6 +152,10 @@ define void @constant_fold_fmin_f32_nan_nan(float addrspace(1)* %out) nounwind {
 ; SI-NOT: v_min_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MIN_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
 define void @constant_fold_fmin_f32_val_nan(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.minnum.f32(float 1.0, float 0x7FF8000000000000) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -107,6 +166,10 @@ define void @constant_fold_fmin_f32_val_nan(float addrspace(1)* %out) nounwind {
 ; SI-NOT: v_min_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MIN_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
 define void @constant_fold_fmin_f32_nan_val(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 1.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -117,6 +180,10 @@ define void @constant_fold_fmin_f32_nan_val(float addrspace(1)* %out) nounwind {
 ; SI-NOT: v_min_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MIN_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
 define void @constant_fold_fmin_f32_p0_p0(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.minnum.f32(float 0.0, float 0.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -127,6 +194,10 @@ define void @constant_fold_fmin_f32_p0_p0(float addrspace(1)* %out) nounwind {
 ; SI-NOT: v_min_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MIN_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
 define void @constant_fold_fmin_f32_p0_n0(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.minnum.f32(float 0.0, float -0.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -137,6 +208,10 @@ define void @constant_fold_fmin_f32_p0_n0(float addrspace(1)* %out) nounwind {
 ; SI-NOT: v_min_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MIN_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
 define void @constant_fold_fmin_f32_n0_p0(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.minnum.f32(float -0.0, float 0.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -147,6 +222,10 @@ define void @constant_fold_fmin_f32_n0_p0(float addrspace(1)* %out) nounwind {
 ; SI-NOT: v_min_f32_e32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
 ; SI: buffer_store_dword [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG-NOT: MIN_DX10
+; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
 define void @constant_fold_fmin_f32_n0_n0(float addrspace(1)* %out) nounwind {
   %val = call float @llvm.minnum.f32(float -0.0, float -0.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -155,6 +234,9 @@ define void @constant_fold_fmin_f32_n0_n0(float addrspace(1)* %out) nounwind {
 
 ; FUNC-LABEL: @fmin_var_immediate_f32
 ; SI: v_min_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}}
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
 define void @fmin_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind {
   %val = call float @llvm.minnum.f32(float %a, float 2.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -163,6 +245,9 @@ define void @fmin_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind
 
 ; FUNC-LABEL: @fmin_immediate_var_f32
 ; SI: v_min_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}}
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
 define void @fmin_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind {
   %val = call float @llvm.minnum.f32(float 2.0, float %a) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -172,6 +257,9 @@ define void @fmin_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind
 ; FUNC-LABEL: @fmin_var_literal_f32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
 ; SI: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
 define void @fmin_var_literal_f32(float addrspace(1)* %out, float %a) nounwind {
   %val = call float @llvm.minnum.f32(float %a, float 99.0) #0
   store float %val, float addrspace(1)* %out, align 4
@@ -181,6 +269,9 @@ define void @fmin_var_literal_f32(float addrspace(1)* %out, float %a) nounwind {
 ; FUNC-LABEL: @fmin_literal_var_f32
 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
 ; SI: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
+
+; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
+; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
 define void @fmin_literal_var_f32(float addrspace(1)* %out, float %a) nounwind {
   %val = call float @llvm.minnum.f32(float 99.0, float %a) #0
   store float %val, float addrspace(1)* %out, align 4
diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll
index 6c09aa242677..68ebc4dedfe0 100644
--- a/test/CodeGen/R600/fmul.ll
+++ b/test/CodeGen/R600/fmul.ll
@@ -42,9 +42,9 @@ entry:
 ; SI: v_mul_f32
 ; SI: v_mul_f32
 define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
-  %a = load <4 x float> addrspace(1) * %in
-  %b = load <4 x float> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
+  %a = load <4 x float>, <4 x float> addrspace(1) * %in
+  %b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr
   %result = fmul <4 x float> %a, %b
   store <4 x float> %result, <4 x float> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/fmul64.ll b/test/CodeGen/R600/fmul64.ll
index 9d7787ccbe1f..3c222eaba89d 100644
--- a/test/CodeGen/R600/fmul64.ll
+++ b/test/CodeGen/R600/fmul64.ll
@@ -5,8 +5,8 @@
 ; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
 define void @fmul_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
                       double addrspace(1)* %in2) {
-   %r0 = load double addrspace(1)* %in1
-   %r1 = load double addrspace(1)* %in2
+   %r0 = load double, double addrspace(1)* %in1
+   %r1 = load double, double addrspace(1)* %in2
    %r2 = fmul double %r0, %r1
    store double %r2, double addrspace(1)* %out
    ret void
@@ -17,8 +17,8 @@ define void @fmul_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
 ; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
 define void @fmul_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1,
                         <2 x double> addrspace(1)* %in2) {
-   %r0 = load <2 x double> addrspace(1)* %in1
-   %r1 = load <2 x double> addrspace(1)* %in2
+   %r0 = load <2 x double>, <2 x double> addrspace(1)* %in1
+   %r1 = load <2 x double>, <2 x double> addrspace(1)* %in2
    %r2 = fmul <2 x double> %r0, %r1
    store <2 x double> %r2, <2 x double> addrspace(1)* %out
    ret void
@@ -31,8 +31,8 @@ define void @fmul_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(
 ; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
 define void @fmul_v4f64(<4 x double> addrspace(1)* %out, <4 x double> addrspace(1)* %in1,
                         <4 x double> addrspace(1)* %in2) {
-   %r0 = load <4 x double> addrspace(1)* %in1
-   %r1 = load <4 x double> addrspace(1)* %in2
+   %r0 = load <4 x double>, <4 x double> addrspace(1)* %in1
+   %r1 = load <4 x double>, <4 x double> addrspace(1)* %in2
    %r2 = fmul <4 x double> %r0, %r1
    store <4 x double> %r2, <4 x double> addrspace(1)* %out
    ret void
diff --git a/test/CodeGen/R600/fmuladd.ll b/test/CodeGen/R600/fmuladd.ll
index 2b708639b122..ae84d841021d 100644
--- a/test/CodeGen/R600/fmuladd.ll
+++ b/test/CodeGen/R600/fmuladd.ll
@@ -10,9 +10,9 @@ declare float @llvm.fabs.f32(float) nounwind readnone
 
 define void @fmuladd_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
                          float addrspace(1)* %in2, float addrspace(1)* %in3) {
-   %r0 = load float addrspace(1)* %in1
-   %r1 = load float addrspace(1)* %in2
-   %r2 = load float addrspace(1)* %in3
+   %r0 = load float, float addrspace(1)* %in1
+   %r1 = load float, float addrspace(1)* %in2
+   %r2 = load float, float addrspace(1)* %in3
    %r3 = tail call float @llvm.fmuladd.f32(float %r0, float %r1, float %r2)
    store float %r3, float addrspace(1)* %out
    ret void
@@ -23,9 +23,9 @@ define void @fmuladd_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
 
 define void @fmuladd_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
                          double addrspace(1)* %in2, double addrspace(1)* %in3) {
-   %r0 = load double addrspace(1)* %in1
-   %r1 = load double addrspace(1)* %in2
-   %r2 = load double addrspace(1)* %in3
+   %r0 = load double, double addrspace(1)* %in1
+   %r1 = load double, double addrspace(1)* %in2
+   %r2 = load double, double addrspace(1)* %in3
    %r3 = tail call double @llvm.fmuladd.f64(double %r0, double %r1, double %r2)
    store double %r3, double addrspace(1)* %out
    ret void
@@ -38,12 +38,12 @@ define void @fmuladd_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
 ; CHECK: buffer_store_dword [[RESULT]]
 define void @fmuladd_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %gep.out = getelementptr float addrspace(1)* %out, i32 %tid
+  %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
 
-  %r1 = load float addrspace(1)* %gep.0
-  %r2 = load float addrspace(1)* %gep.1
+  %r1 = load float, float addrspace(1)* %gep.0
+  %r2 = load float, float addrspace(1)* %gep.1
 
   %r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1, float %r2)
   store float %r3, float addrspace(1)* %gep.out
@@ -57,12 +57,12 @@ define void @fmuladd_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %
 ; CHECK: buffer_store_dword [[RESULT]]
 define void @fmuladd_a_2.0_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %gep.out = getelementptr float addrspace(1)* %out, i32 %tid
+  %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
 
-  %r1 = load float addrspace(1)* %gep.0
-  %r2 = load float addrspace(1)* %gep.1
+  %r1 = load float, float addrspace(1)* %gep.0
+  %r2 = load float, float addrspace(1)* %gep.1
 
   %r3 = tail call float @llvm.fmuladd.f32(float %r1, float 2.0, float %r2)
   store float %r3, float addrspace(1)* %gep.out
@@ -78,12 +78,12 @@ define void @fadd_a_a_b_f32(float addrspace(1)* %out,
                             float addrspace(1)* %in1,
                             float addrspace(1)* %in2) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %gep.out = getelementptr float addrspace(1)* %out, i32 %tid
+  %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
 
-  %r0 = load float addrspace(1)* %gep.0
-  %r1 = load float addrspace(1)* %gep.1
+  %r0 = load float, float addrspace(1)* %gep.0
+  %r1 = load float, float addrspace(1)* %gep.1
 
   %add.0 = fadd float %r0, %r0
   %add.1 = fadd float %add.0, %r1
@@ -100,12 +100,12 @@ define void @fadd_b_a_a_f32(float addrspace(1)* %out,
                             float addrspace(1)* %in1,
                             float addrspace(1)* %in2) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %gep.out = getelementptr float addrspace(1)* %out, i32 %tid
+  %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
 
-  %r0 = load float addrspace(1)* %gep.0
-  %r1 = load float addrspace(1)* %gep.1
+  %r0 = load float, float addrspace(1)* %gep.0
+  %r1 = load float, float addrspace(1)* %gep.1
 
   %add.0 = fadd float %r0, %r0
   %add.1 = fadd float %r1, %add.0
@@ -120,12 +120,12 @@ define void @fadd_b_a_a_f32(float addrspace(1)* %out,
 ; CHECK: buffer_store_dword [[RESULT]]
 define void @fmuladd_neg_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %gep.out = getelementptr float addrspace(1)* %out, i32 %tid
+  %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
 
-  %r1 = load float addrspace(1)* %gep.0
-  %r2 = load float addrspace(1)* %gep.1
+  %r1 = load float, float addrspace(1)* %gep.0
+  %r2 = load float, float addrspace(1)* %gep.1
 
   %r3 = tail call float @llvm.fmuladd.f32(float -2.0, float %r1, float %r2)
   store float %r3, float addrspace(1)* %gep.out
@@ -140,12 +140,12 @@ define void @fmuladd_neg_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1
 ; CHECK: buffer_store_dword [[RESULT]]
 define void @fmuladd_neg_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %gep.out = getelementptr float addrspace(1)* %out, i32 %tid
+  %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
 
-  %r1 = load float addrspace(1)* %gep.0
-  %r2 = load float addrspace(1)* %gep.1
+  %r1 = load float, float addrspace(1)* %gep.0
+  %r2 = load float, float addrspace(1)* %gep.1
 
   %r1.fneg = fsub float -0.000000e+00, %r1
 
@@ -162,12 +162,12 @@ define void @fmuladd_neg_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspa
 ; CHECK: buffer_store_dword [[RESULT]]
 define void @fmuladd_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %gep.out = getelementptr float addrspace(1)* %out, i32 %tid
+  %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
 
-  %r1 = load float addrspace(1)* %gep.0
-  %r2 = load float addrspace(1)* %gep.1
+  %r1 = load float, float addrspace(1)* %gep.0
+  %r2 = load float, float addrspace(1)* %gep.1
 
   %r1.fneg = fsub float -0.000000e+00, %r1
 
@@ -184,12 +184,12 @@ define void @fmuladd_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1
 ; CHECK: buffer_store_dword [[RESULT]]
 define void @fmuladd_2.0_a_neg_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %gep.out = getelementptr float addrspace(1)* %out, i32 %tid
+  %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
 
-  %r1 = load float addrspace(1)* %gep.0
-  %r2 = load float addrspace(1)* %gep.1
+  %r1 = load float, float addrspace(1)* %gep.0
+  %r2 = load float, float addrspace(1)* %gep.1
 
   %r2.fneg = fsub float -0.000000e+00, %r2
 
diff --git a/test/CodeGen/R600/fneg-fabs.f64.ll b/test/CodeGen/R600/fneg-fabs.f64.ll
index 7430e7ffb33d..8830e8273661 100644
--- a/test/CodeGen/R600/fneg-fabs.f64.ll
+++ b/test/CodeGen/R600/fneg-fabs.f64.ll
@@ -5,9 +5,7 @@
 ; into 2 modifiers, although theoretically that should work.
 
 ; FUNC-LABEL: {{^}}fneg_fabs_fadd_f64:
-; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x7fffffff
-; SI: v_and_b32_e32 v[[FABS:[0-9]+]], {{s[0-9]+}}, [[IMMREG]]
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+}}:[[FABS]]{{\]}}
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|v{{\[[0-9]+:[0-9]+\]}}|
 define void @fneg_fabs_fadd_f64(double addrspace(1)* %out, double %x, double %y) {
   %fabs = call double @llvm.fabs.f64(double %x)
   %fsub = fsub double -0.000000e+00, %fabs
@@ -17,8 +15,8 @@ define void @fneg_fabs_fadd_f64(double addrspace(1)* %out, double %x, double %y)
 }
 
 define void @v_fneg_fabs_fadd_f64(double addrspace(1)* %out, double addrspace(1)* %xptr, double addrspace(1)* %yptr) {
-  %x = load double addrspace(1)* %xptr, align 8
-  %y = load double addrspace(1)* %xptr, align 8
+  %x = load double, double addrspace(1)* %xptr, align 8
+  %y = load double, double addrspace(1)* %xptr, align 8
   %fabs = call double @llvm.fabs.f64(double %x)
   %fsub = fsub double -0.000000e+00, %fabs
   %fadd = fadd double %y, %fsub
@@ -57,8 +55,8 @@ define void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
 }
 
 ; FUNC-LABEL: {{^}}fneg_fabs_f64:
-; SI: s_load_dwordx2
 ; SI: s_load_dwordx2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}}
+; SI: s_load_dwordx2
 ; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
 ; SI-DAG: v_or_b32_e32 v[[HI_V:[0-9]+]], s[[HI_X]], [[IMMREG]]
 ; SI-DAG: v_mov_b32_e32 v[[LO_V:[0-9]+]], s[[LO_X]]
diff --git a/test/CodeGen/R600/fneg-fabs.ll b/test/CodeGen/R600/fneg-fabs.ll
index 4fde0484567c..3b4930d9897d 100644
--- a/test/CodeGen/R600/fneg-fabs.ll
+++ b/test/CodeGen/R600/fneg-fabs.ll
@@ -72,7 +72,7 @@ define void @fneg_fabs_f32(float addrspace(1)* %out, float %in) {
 ; FUNC-LABEL: {{^}}v_fneg_fabs_f32:
 ; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
 define void @v_fneg_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
-  %val = load float addrspace(1)* %in, align 4
+  %val = load float, float addrspace(1)* %in, align 4
   %fabs = call float @llvm.fabs.f32(float %val)
   %fsub = fsub float -0.000000e+00, %fabs
   store float %fsub, float addrspace(1)* %out, align 4
diff --git a/test/CodeGen/R600/fneg.f64.ll b/test/CodeGen/R600/fneg.f64.ll
index eb2eb08b88b1..aa6df209035b 100644
--- a/test/CodeGen/R600/fneg.f64.ll
+++ b/test/CodeGen/R600/fneg.f64.ll
@@ -1,7 +1,8 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
 
 ; FUNC-LABEL: {{^}}fneg_f64:
-; SI: v_xor_b32
+; GCN: v_xor_b32
 define void @fneg_f64(double addrspace(1)* %out, double %in) {
   %fneg = fsub double -0.000000e+00, %in
   store double %fneg, double addrspace(1)* %out
@@ -9,8 +10,8 @@ define void @fneg_f64(double addrspace(1)* %out, double %in) {
 }
 
 ; FUNC-LABEL: {{^}}fneg_v2f64:
-; SI: v_xor_b32
-; SI: v_xor_b32
+; GCN: v_xor_b32
+; GCN: v_xor_b32
 define void @fneg_v2f64(<2 x double> addrspace(1)* nocapture %out, <2 x double> %in) {
   %fneg = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %in
   store <2 x double> %fneg, <2 x double> addrspace(1)* %out
@@ -23,10 +24,10 @@ define void @fneg_v2f64(<2 x double> addrspace(1)* nocapture %out, <2 x double>
 ; R600: -PV
 ; R600: -PV
 
-; SI: v_xor_b32
-; SI: v_xor_b32
-; SI: v_xor_b32
-; SI: v_xor_b32
+; GCN: v_xor_b32
+; GCN: v_xor_b32
+; GCN: v_xor_b32
+; GCN: v_xor_b32
 define void @fneg_v4f64(<4 x double> addrspace(1)* nocapture %out, <4 x double> %in) {
   %fneg = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %in
   store <4 x double> %fneg, <4 x double> addrspace(1)* %out
@@ -38,8 +39,7 @@ define void @fneg_v4f64(<4 x double> addrspace(1)* nocapture %out, <4 x double>
 ; unless the target returns true for isNegFree()
 
 ; FUNC-LABEL: {{^}}fneg_free_f64:
-; FIXME: Unnecessary copy to VGPRs
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, -{{v\[[0-9]+:[0-9]+\]$}}
+; GCN: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, 0, -{{s\[[0-9]+:[0-9]+\]$}}
 define void @fneg_free_f64(double addrspace(1)* %out, i64 %in) {
   %bc = bitcast i64 %in to double
   %fsub = fsub double 0.0, %bc
@@ -47,10 +47,11 @@ define void @fneg_free_f64(double addrspace(1)* %out, i64 %in) {
   ret void
 }
 
-; SI-LABEL: {{^}}fneg_fold_f64:
+; GCN-LABEL: {{^}}fneg_fold_f64:
 ; SI: s_load_dwordx2 [[NEG_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-NOT: xor
-; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, -[[NEG_VALUE]], [[NEG_VALUE]]
+; VI: s_load_dwordx2 [[NEG_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
+; GCN-NOT: xor
+; GCN: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, -[[NEG_VALUE]], [[NEG_VALUE]]
 define void @fneg_fold_f64(double addrspace(1)* %out, double %in) {
   %fsub = fsub double -0.0, %in
   %fmul = fmul double %fsub, %in
diff --git a/test/CodeGen/R600/fneg.ll b/test/CodeGen/R600/fneg.ll
index ca3350dd7f48..a0fd539863c6 100644
--- a/test/CodeGen/R600/fneg.ll
+++ b/test/CodeGen/R600/fneg.ll
@@ -1,10 +1,11 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
 
 ; FUNC-LABEL: {{^}}fneg_f32:
 ; R600: -PV
 
-; SI: v_xor_b32
+; GCN: v_xor_b32
 define void @fneg_f32(float addrspace(1)* %out, float %in) {
   %fneg = fsub float -0.000000e+00, %in
   store float %fneg, float addrspace(1)* %out
@@ -15,8 +16,8 @@ define void @fneg_f32(float addrspace(1)* %out, float %in) {
 ; R600: -PV
 ; R600: -PV
 
-; SI: v_xor_b32
-; SI: v_xor_b32
+; GCN: v_xor_b32
+; GCN: v_xor_b32
 define void @fneg_v2f32(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
   %fneg = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
   store <2 x float> %fneg, <2 x float> addrspace(1)* %out
@@ -29,10 +30,10 @@ define void @fneg_v2f32(<2 x float> addrspace(1)* nocapture %out, <2 x float> %i
 ; R600: -PV
 ; R600: -PV
 
-; SI: v_xor_b32
-; SI: v_xor_b32
-; SI: v_xor_b32
-; SI: v_xor_b32
+; GCN: v_xor_b32
+; GCN: v_xor_b32
+; GCN: v_xor_b32
+; GCN: v_xor_b32
 define void @fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
   %fneg = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
   store <4 x float> %fneg, <4 x float> addrspace(1)* %out
@@ -48,7 +49,7 @@ define void @fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %i
 ; R600: -KC0[2].Z
 
 ; XXX: We could use v_add_f32_e64 with the negate bit here instead.
-; SI: v_sub_f32_e64 v{{[0-9]}}, 0, s{{[0-9]+$}}
+; GCN: v_sub_f32_e64 v{{[0-9]}}, 0, s{{[0-9]+$}}
 define void @fneg_free_f32(float addrspace(1)* %out, i32 %in) {
   %bc = bitcast i32 %in to float
   %fsub = fsub float 0.0, %bc
@@ -58,8 +59,9 @@ define void @fneg_free_f32(float addrspace(1)* %out, i32 %in) {
 
 ; FUNC-LABEL: {{^}}fneg_fold_f32:
 ; SI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
-; SI-NOT: xor
-; SI: v_mul_f32_e64 v{{[0-9]+}}, -[[NEG_VALUE]], [[NEG_VALUE]]
+; VI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
+; GCN-NOT: xor
+; GCN: v_mul_f32_e64 v{{[0-9]+}}, -[[NEG_VALUE]], [[NEG_VALUE]]
 define void @fneg_fold_f32(float addrspace(1)* %out, float %in) {
   %fsub = fsub float -0.0, %in
   %fmul = fmul float %fsub, %in
diff --git a/test/CodeGen/R600/fp-classify.ll b/test/CodeGen/R600/fp-classify.ll
index c1de85203104..4fac5176fac9 100644
--- a/test/CodeGen/R600/fp-classify.ll
+++ b/test/CodeGen/R600/fp-classify.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=r600 -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
 
 declare i1 @llvm.AMDGPU.class.f32(float, i32) #1
 declare i1 @llvm.AMDGPU.class.f64(double, i32) #1
diff --git a/test/CodeGen/R600/fp16_to_fp.ll b/test/CodeGen/R600/fp16_to_fp.ll
index da78f6155c85..5a79ca82bc29 100644
--- a/test/CodeGen/R600/fp16_to_fp.ll
+++ b/test/CodeGen/R600/fp16_to_fp.ll
@@ -9,7 +9,7 @@ declare double @llvm.convert.from.fp16.f64(i16) nounwind readnone
 ; SI: v_cvt_f32_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
 ; SI: buffer_store_dword [[RESULT]]
 define void @test_convert_fp16_to_fp32(float addrspace(1)* noalias %out, i16 addrspace(1)* noalias %in) nounwind {
-  %val = load i16 addrspace(1)* %in, align 2
+  %val = load i16, i16 addrspace(1)* %in, align 2
   %cvt = call float @llvm.convert.from.fp16.f32(i16 %val) nounwind readnone
   store float %cvt, float addrspace(1)* %out, align 4
   ret void
@@ -22,7 +22,7 @@ define void @test_convert_fp16_to_fp32(float addrspace(1)* noalias %out, i16 add
 ; SI: v_cvt_f64_f32_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[RESULT32]]
 ; SI: buffer_store_dwordx2 [[RESULT]]
 define void @test_convert_fp16_to_fp64(double addrspace(1)* noalias %out, i16 addrspace(1)* noalias %in) nounwind {
-  %val = load i16 addrspace(1)* %in, align 2
+  %val = load i16, i16 addrspace(1)* %in, align 2
   %cvt = call double @llvm.convert.from.fp16.f64(i16 %val) nounwind readnone
   store double %cvt, double addrspace(1)* %out, align 4
   ret void
diff --git a/test/CodeGen/R600/fp32_to_fp16.ll b/test/CodeGen/R600/fp32_to_fp16.ll
index c3c65aece082..67925ebd82b6 100644
--- a/test/CodeGen/R600/fp32_to_fp16.ll
+++ b/test/CodeGen/R600/fp32_to_fp16.ll
@@ -8,7 +8,7 @@ declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone
 ; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[VAL]]
 ; SI: buffer_store_short [[RESULT]]
 define void @test_convert_fp32_to_fp16(i16 addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
-  %val = load float addrspace(1)* %in, align 4
+  %val = load float, float addrspace(1)* %in, align 4
   %cvt = call i16 @llvm.convert.to.fp16.f32(float %val) nounwind readnone
   store i16 %cvt, i16 addrspace(1)* %out, align 2
   ret void
diff --git a/test/CodeGen/R600/fp_to_sint.f64.ll b/test/CodeGen/R600/fp_to_sint.f64.ll
index e6418477a9b4..12df6606e8ff 100644
--- a/test/CodeGen/R600/fp_to_sint.f64.ll
+++ b/test/CodeGen/R600/fp_to_sint.f64.ll
@@ -48,8 +48,8 @@ define void @fp_to_sint_v4f64_v4i32(<4 x i32> addrspace(1)* %out, <4 x double> %
 ; CI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
 define void @fp_to_sint_i64_f64(i64 addrspace(1)* %out, double addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep = getelementptr double addrspace(1)* %in, i32 %tid
-  %val = load double addrspace(1)* %gep, align 8
+  %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %val = load double, double addrspace(1)* %gep, align 8
   %cast = fptosi double %val to i64
   store i64 %cast, i64 addrspace(1)* %out, align 8
   ret void
diff --git a/test/CodeGen/R600/fp_to_sint.ll b/test/CodeGen/R600/fp_to_sint.ll
index 16549c392b00..301a94b4904c 100644
--- a/test/CodeGen/R600/fp_to_sint.ll
+++ b/test/CodeGen/R600/fp_to_sint.ll
@@ -44,7 +44,7 @@ define void @fp_to_sint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
 ; SI: v_cvt_i32_f32_e32
 ; SI: v_cvt_i32_f32_e32
 define void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
-  %value = load <4 x float> addrspace(1) * %in
+  %value = load <4 x float>, <4 x float> addrspace(1) * %in
   %result = fptosi <4 x float> %value to <4 x i32>
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/fp_to_uint.f64.ll b/test/CodeGen/R600/fp_to_uint.f64.ll
index 1ffe2faadf33..41bc2a780014 100644
--- a/test/CodeGen/R600/fp_to_uint.f64.ll
+++ b/test/CodeGen/R600/fp_to_uint.f64.ll
@@ -48,8 +48,8 @@ define void @fp_to_uint_v4i32_v4f64(<4 x i32> addrspace(1)* %out, <4 x double> %
 ; CI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
 define void @fp_to_uint_i64_f64(i64 addrspace(1)* %out, double addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep = getelementptr double addrspace(1)* %in, i32 %tid
-  %val = load double addrspace(1)* %gep, align 8
+  %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %val = load double, double addrspace(1)* %gep, align 8
   %cast = fptoui double %val to i64
   store i64 %cast, i64 addrspace(1)* %out, align 4
   ret void
diff --git a/test/CodeGen/R600/fp_to_uint.ll b/test/CodeGen/R600/fp_to_uint.ll
index 804d90f476da..b7b6ccc238b3 100644
--- a/test/CodeGen/R600/fp_to_uint.ll
+++ b/test/CodeGen/R600/fp_to_uint.ll
@@ -36,7 +36,7 @@ define void @fp_to_uint_v2f32_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x float>
 ; SI: v_cvt_u32_f32_e32
 
 define void @fp_to_uint_v4f32_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
-  %value = load <4 x float> addrspace(1) * %in
+  %value = load <4 x float>, <4 x float> addrspace(1) * %in
   %result = fptoui <4 x float> %value to <4 x i32>
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/fpext.ll b/test/CodeGen/R600/fpext.ll
index 21c7bfd48df8..734a43be2296 100644
--- a/test/CodeGen/R600/fpext.ll
+++ b/test/CodeGen/R600/fpext.ll
@@ -1,10 +1,45 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
-; CHECK: {{^}}fpext:
-; CHECK: v_cvt_f64_f32_e32
-define void @fpext(double addrspace(1)* %out, float %in) {
+; FUNC-LABEL: {{^}}fpext_f32_to_f64:
+; SI: v_cvt_f64_f32_e32 {{v\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
+define void @fpext_f32_to_f64(double addrspace(1)* %out, float %in) {
   %result = fpext float %in to double
   store double %result, double addrspace(1)* %out
   ret void
 }
+
+; FUNC-LABEL: {{^}}fpext_v2f32_to_v2f64:
+; SI: v_cvt_f64_f32_e32
+; SI: v_cvt_f64_f32_e32
+define void @fpext_v2f32_to_v2f64(<2 x double> addrspace(1)* %out, <2 x float> %in) {
+  %result = fpext <2 x float> %in to <2 x double>
+  store <2 x double> %result, <2 x double> addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}fpext_v4f32_to_v4f64:
+; SI: v_cvt_f64_f32_e32
+; SI: v_cvt_f64_f32_e32
+; SI: v_cvt_f64_f32_e32
+; SI: v_cvt_f64_f32_e32
+define void @fpext_v4f32_to_v4f64(<4 x double> addrspace(1)* %out, <4 x float> %in) {
+  %result = fpext <4 x float> %in to <4 x double>
+  store <4 x double> %result, <4 x double> addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}fpext_v8f32_to_v8f64:
+; SI: v_cvt_f64_f32_e32
+; SI: v_cvt_f64_f32_e32
+; SI: v_cvt_f64_f32_e32
+; SI: v_cvt_f64_f32_e32
+; SI: v_cvt_f64_f32_e32
+; SI: v_cvt_f64_f32_e32
+; SI: v_cvt_f64_f32_e32
+; SI: v_cvt_f64_f32_e32
+define void @fpext_v8f32_to_v8f64(<8 x double> addrspace(1)* %out, <8 x float> %in) {
+  %result = fpext <8 x float> %in to <8 x double>
+  store <8 x double> %result, <8 x double> addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/fptrunc.ll b/test/CodeGen/R600/fptrunc.ll
index 94fcdab9c52f..385e10e7baae 100644
--- a/test/CodeGen/R600/fptrunc.ll
+++ b/test/CodeGen/R600/fptrunc.ll
@@ -1,10 +1,45 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
-; CHECK: {{^}}fptrunc:
-; CHECK: v_cvt_f32_f64_e32
-define void @fptrunc(float addrspace(1)* %out, double %in) {
+; FUNC-LABEL: {{^}}fptrunc_f64_to_f32:
+; SI: v_cvt_f32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
+define void @fptrunc_f64_to_f32(float addrspace(1)* %out, double %in) {
   %result = fptrunc double %in to float
   store float %result, float addrspace(1)* %out
   ret void
 }
+
+; FUNC-LABEL: {{^}}fptrunc_v2f64_to_v2f32:
+; SI: v_cvt_f32_f64_e32
+; SI: v_cvt_f32_f64_e32
+define void @fptrunc_v2f64_to_v2f32(<2 x float> addrspace(1)* %out, <2 x double> %in) {
+  %result = fptrunc <2 x double> %in to <2 x float>
+  store <2 x float> %result, <2 x float> addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}fptrunc_v4f64_to_v4f32:
+; SI: v_cvt_f32_f64_e32
+; SI: v_cvt_f32_f64_e32
+; SI: v_cvt_f32_f64_e32
+; SI: v_cvt_f32_f64_e32
+define void @fptrunc_v4f64_to_v4f32(<4 x float> addrspace(1)* %out, <4 x double> %in) {
+  %result = fptrunc <4 x double> %in to <4 x float>
+  store <4 x float> %result, <4 x float> addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}fptrunc_v8f64_to_v8f32:
+; SI: v_cvt_f32_f64_e32
+; SI: v_cvt_f32_f64_e32
+; SI: v_cvt_f32_f64_e32
+; SI: v_cvt_f32_f64_e32
+; SI: v_cvt_f32_f64_e32
+; SI: v_cvt_f32_f64_e32
+; SI: v_cvt_f32_f64_e32
+; SI: v_cvt_f32_f64_e32
+define void @fptrunc_v8f64_to_v8f32(<8 x float> addrspace(1)* %out, <8 x double> %in) {
+  %result = fptrunc <8 x double> %in to <8 x float>
+  store <8 x float> %result, <8 x float> addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/frem.ll b/test/CodeGen/R600/frem.ll
index 564634178656..f245ef08cb9d 100644
--- a/test/CodeGen/R600/frem.ll
+++ b/test/CodeGen/R600/frem.ll
@@ -1,73 +1,78 @@
-; RUN: llc -march=amdgcn -mcpu=SI -enable-misched < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -enable-misched < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=bonaire -enable-misched < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -enable-misched < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s
 
 ; FUNC-LABEL: {{^}}frem_f32:
-; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{.*$}}
-; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{.*}} offset:16
-; SI-DAG: v_cmp
-; SI-DAG: v_mul_f32
-; SI: v_rcp_f32_e32
-; SI: v_mul_f32_e32
-; SI: v_mul_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_mad_f32
-; SI: s_endpgm
+; GCN-DAG: buffer_load_dword [[X:v[0-9]+]], {{.*$}}
+; GCN-DAG: buffer_load_dword [[Y:v[0-9]+]], {{.*}} offset:16
+; GCN-DAG: v_cmp
+; GCN-DAG: v_mul_f32
+; GCN: v_rcp_f32_e32
+; GCN: v_mul_f32_e32
+; GCN: v_mul_f32_e32
+; GCN: v_trunc_f32_e32
+; GCN: v_mad_f32
+; GCN: s_endpgm
 define void @frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
                       float addrspace(1)* %in2) #0 {
-   %gep2 = getelementptr float addrspace(1)* %in2, i32 4
-   %r0 = load float addrspace(1)* %in1, align 4
-   %r1 = load float addrspace(1)* %gep2, align 4
+   %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
+   %r0 = load float, float addrspace(1)* %in1, align 4
+   %r1 = load float, float addrspace(1)* %gep2, align 4
    %r2 = frem float %r0, %r1
    store float %r2, float addrspace(1)* %out, align 4
    ret void
 }
 
 ; FUNC-LABEL: {{^}}unsafe_frem_f32:
-; SI: buffer_load_dword [[Y:v[0-9]+]], {{.*}} offset:16
-; SI: buffer_load_dword [[X:v[0-9]+]], {{.*}}
-; SI: v_rcp_f32_e32 [[INVY:v[0-9]+]], [[Y]]
-; SI: v_mul_f32_e32 [[DIV:v[0-9]+]], [[INVY]], [[X]]
-; SI: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[DIV]]
-; SI: v_mad_f32 [[RESULT:v[0-9]+]], -[[TRUNC]], [[Y]], [[X]]
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
+; GCN: buffer_load_dword [[Y:v[0-9]+]], {{.*}} offset:16
+; GCN: buffer_load_dword [[X:v[0-9]+]], {{.*}}
+; GCN: v_rcp_f32_e32 [[INVY:v[0-9]+]], [[Y]]
+; GCN: v_mul_f32_e32 [[DIV:v[0-9]+]], [[INVY]], [[X]]
+; GCN: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[DIV]]
+; GCN: v_mad_f32 [[RESULT:v[0-9]+]], -[[TRUNC]], [[Y]], [[X]]
+; GCN: buffer_store_dword [[RESULT]]
+; GCN: s_endpgm
 define void @unsafe_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
                              float addrspace(1)* %in2) #1 {
-   %gep2 = getelementptr float addrspace(1)* %in2, i32 4
-   %r0 = load float addrspace(1)* %in1, align 4
-   %r1 = load float addrspace(1)* %gep2, align 4
+   %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
+   %r0 = load float, float addrspace(1)* %in1, align 4
+   %r1 = load float, float addrspace(1)* %gep2, align 4
    %r2 = frem float %r0, %r1
    store float %r2, float addrspace(1)* %out, align 4
    ret void
 }
 
 ; FUNC-LABEL: {{^}}frem_f64:
-; SI: buffer_load_dwordx2 [[Y:v\[[0-9]+:[0-9]+\]]], {{.*}}, 0
-; SI: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]], {{.*}}, 0
-; SI-DAG: v_div_fmas_f64
-; SI-DAG: v_div_scale_f64
-; SI-DAG: v_mul_f64
-; SI: v_add_f64
-; SI: buffer_store_dwordx2
-; SI: s_endpgm
+; GCN: buffer_load_dwordx2 [[Y:v\[[0-9]+:[0-9]+\]]], {{.*}}, 0
+; GCN: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]], {{.*}}, 0
+; GCN-DAG: v_div_fmas_f64
+; GCN-DAG: v_div_scale_f64
+; GCN-DAG: v_mul_f64
+; CI: v_trunc_f64_e32
+; CI: v_mul_f64
+; GCN: v_add_f64
+; GCN: buffer_store_dwordx2
+; GCN: s_endpgm
 define void @frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
                       double addrspace(1)* %in2) #0 {
-   %r0 = load double addrspace(1)* %in1, align 8
-   %r1 = load double addrspace(1)* %in2, align 8
+   %r0 = load double, double addrspace(1)* %in1, align 8
+   %r1 = load double, double addrspace(1)* %in2, align 8
    %r2 = frem double %r0, %r1
    store double %r2, double addrspace(1)* %out, align 8
    ret void
 }
 
 ; FUNC-LABEL: {{^}}unsafe_frem_f64:
-; SI: v_rcp_f64_e32
-; SI: v_mul_f64
+; GCN: v_rcp_f64_e32
+; GCN: v_mul_f64
 ; SI: v_bfe_u32
-; SI: v_fma_f64
-; SI: s_endpgm
+; CI: v_trunc_f64_e32
+; GCN: v_fma_f64
+; GCN: s_endpgm
 define void @unsafe_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
                              double addrspace(1)* %in2) #1 {
-   %r0 = load double addrspace(1)* %in1, align 8
-   %r1 = load double addrspace(1)* %in2, align 8
+   %r0 = load double, double addrspace(1)* %in1, align 8
+   %r1 = load double, double addrspace(1)* %in2, align 8
    %r2 = frem double %r0, %r1
    store double %r2, double addrspace(1)* %out, align 8
    ret void
@@ -75,9 +80,9 @@ define void @unsafe_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in
 
 define void @frem_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in1,
                         <2 x float> addrspace(1)* %in2) #0 {
-   %gep2 = getelementptr <2 x float> addrspace(1)* %in2, i32 4
-   %r0 = load <2 x float> addrspace(1)* %in1, align 8
-   %r1 = load <2 x float> addrspace(1)* %gep2, align 8
+   %gep2 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in2, i32 4
+   %r0 = load <2 x float>, <2 x float> addrspace(1)* %in1, align 8
+   %r1 = load <2 x float>, <2 x float> addrspace(1)* %gep2, align 8
    %r2 = frem <2 x float> %r0, %r1
    store <2 x float> %r2, <2 x float> addrspace(1)* %out, align 8
    ret void
@@ -85,9 +90,9 @@ define void @frem_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)
 
 define void @frem_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in1,
                         <4 x float> addrspace(1)* %in2) #0 {
-   %gep2 = getelementptr <4 x float> addrspace(1)* %in2, i32 4
-   %r0 = load <4 x float> addrspace(1)* %in1, align 16
-   %r1 = load <4 x float> addrspace(1)* %gep2, align 16
+   %gep2 = getelementptr <4 x float>, <4 x float> addrspace(1)* %in2, i32 4
+   %r0 = load <4 x float>, <4 x float> addrspace(1)* %in1, align 16
+   %r1 = load <4 x float>, <4 x float> addrspace(1)* %gep2, align 16
    %r2 = frem <4 x float> %r0, %r1
    store <4 x float> %r2, <4 x float> addrspace(1)* %out, align 16
    ret void
@@ -95,9 +100,9 @@ define void @frem_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)
 
 define void @frem_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1,
                         <2 x double> addrspace(1)* %in2) #0 {
-   %gep2 = getelementptr <2 x double> addrspace(1)* %in2, i32 4
-   %r0 = load <2 x double> addrspace(1)* %in1, align 16
-   %r1 = load <2 x double> addrspace(1)* %gep2, align 16
+   %gep2 = getelementptr <2 x double>, <2 x double> addrspace(1)* %in2, i32 4
+   %r0 = load <2 x double>, <2 x double> addrspace(1)* %in1, align 16
+   %r1 = load <2 x double>, <2 x double> addrspace(1)* %gep2, align 16
    %r2 = frem <2 x double> %r0, %r1
    store <2 x double> %r2, <2 x double> addrspace(1)* %out, align 16
    ret void
diff --git a/test/CodeGen/R600/fsqrt.ll b/test/CodeGen/R600/fsqrt.ll
index 1fdf3e453bf3..04101346cdf9 100644
--- a/test/CodeGen/R600/fsqrt.ll
+++ b/test/CodeGen/R600/fsqrt.ll
@@ -9,7 +9,7 @@
 ; CHECK: v_sqrt_f32_e32 {{v[0-9]+, v[0-9]+}}
 
 define void @fsqrt_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
-   %r0 = load float addrspace(1)* %in
+   %r0 = load float, float addrspace(1)* %in
    %r1 = call float @llvm.sqrt.f32(float %r0)
    store float %r1, float addrspace(1)* %out
    ret void
@@ -19,7 +19,7 @@ define void @fsqrt_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
 ; CHECK: v_sqrt_f64_e32 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
 
 define void @fsqrt_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
-   %r0 = load double addrspace(1)* %in
+   %r0 = load double, double addrspace(1)* %in
    %r1 = call double @llvm.sqrt.f64(double %r0)
    store double %r1, double addrspace(1)* %out
    ret void
diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll
index ef90fea67900..dfe41cb5b111 100644
--- a/test/CodeGen/R600/fsub.ll
+++ b/test/CodeGen/R600/fsub.ll
@@ -6,9 +6,9 @@
 ; FUNC-LABEL: {{^}}v_fsub_f32:
 ; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
 define void @v_fsub_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
-  %b_ptr = getelementptr float addrspace(1)* %in, i32 1
-  %a = load float addrspace(1)* %in, align 4
-  %b = load float addrspace(1)* %b_ptr, align 4
+  %b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
+  %a = load float, float addrspace(1)* %in, align 4
+  %b = load float, float addrspace(1)* %b_ptr, align 4
   %result = fsub float %a, %b
   store float %result, float addrspace(1)* %out, align 4
   ret void
@@ -52,9 +52,9 @@ define void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x flo
 ; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
 ; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
 define void @v_fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
-  %a = load <4 x float> addrspace(1)* %in, align 16
-  %b = load <4 x float> addrspace(1)* %b_ptr, align 16
+  %b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
+  %a = load <4 x float>, <4 x float> addrspace(1)* %in, align 16
+  %b = load <4 x float>, <4 x float> addrspace(1)* %b_ptr, align 16
   %result = fsub <4 x float> %a, %b
   store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16
   ret void
diff --git a/test/CodeGen/R600/fsub64.ll b/test/CodeGen/R600/fsub64.ll
index 62f46142fe0d..f34a48e30a86 100644
--- a/test/CodeGen/R600/fsub64.ll
+++ b/test/CodeGen/R600/fsub64.ll
@@ -1,13 +1,107 @@
 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
 
+declare double @llvm.fabs.f64(double) #0
+
 ; SI-LABEL: {{^}}fsub_f64:
 ; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
 define void @fsub_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
                       double addrspace(1)* %in2) {
-   %r0 = load double addrspace(1)* %in1
-   %r1 = load double addrspace(1)* %in2
-   %r2 = fsub double %r0, %r1
-   store double %r2, double addrspace(1)* %out
-   ret void
+  %r0 = load double, double addrspace(1)* %in1
+  %r1 = load double, double addrspace(1)* %in2
+  %r2 = fsub double %r0, %r1
+  store double %r2, double addrspace(1)* %out
+  ret void
+}
+
+; SI-LABEL: {{^}}fsub_fabs_f64:
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -\|v\[[0-9]+:[0-9]+\]\|}}
+define void @fsub_fabs_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
+                           double addrspace(1)* %in2) {
+  %r0 = load double, double addrspace(1)* %in1
+  %r1 = load double, double addrspace(1)* %in2
+  %r1.fabs = call double @llvm.fabs.f64(double %r1) #0
+  %r2 = fsub double %r0, %r1.fabs
+  store double %r2, double addrspace(1)* %out
+  ret void
+}
+
+; SI-LABEL: {{^}}fsub_fabs_inv_f64:
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], |v\[[0-9]+:[0-9]+\]|, -v\[[0-9]+:[0-9]+\]}}
+define void @fsub_fabs_inv_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
+                               double addrspace(1)* %in2) {
+  %r0 = load double, double addrspace(1)* %in1
+  %r1 = load double, double addrspace(1)* %in2
+  %r0.fabs = call double @llvm.fabs.f64(double %r0) #0
+  %r2 = fsub double %r0.fabs, %r1
+  store double %r2, double addrspace(1)* %out
+  ret void
+}
+
+; SI-LABEL: {{^}}s_fsub_f64:
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
+define void @s_fsub_f64(double addrspace(1)* %out, double %a, double %b) {
+  %sub = fsub double %a, %b
+  store double %sub, double addrspace(1)* %out
+  ret void
+}
+
+; SI-LABEL: {{^}}s_fsub_imm_f64:
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], 4.0, -s\[[0-9]+:[0-9]+\]}}
+define void @s_fsub_imm_f64(double addrspace(1)* %out, double %a, double %b) {
+  %sub = fsub double 4.0, %a
+  store double %sub, double addrspace(1)* %out
+  ret void
+}
+
+; SI-LABEL: {{^}}s_fsub_imm_inv_f64:
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], -4.0, s\[[0-9]+:[0-9]+\]}}
+define void @s_fsub_imm_inv_f64(double addrspace(1)* %out, double %a, double %b) {
+  %sub = fsub double %a, 4.0
+  store double %sub, double addrspace(1)* %out
+  ret void
+}
+
+; SI-LABEL: {{^}}s_fsub_self_f64:
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -s\[[0-9]+:[0-9]+\]}}
+define void @s_fsub_self_f64(double addrspace(1)* %out, double %a) {
+  %sub = fsub double %a, %a
+  store double %sub, double addrspace(1)* %out
+  ret void
+}
+
+; SI-LABEL: {{^}}fsub_v2f64:
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
+define void @fsub_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b) {
+  %sub = fsub <2 x double> %a, %b
+  store <2 x double> %sub, <2 x double> addrspace(1)* %out
+  ret void
+}
+
+; SI-LABEL: {{^}}fsub_v4f64:
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
+define void @fsub_v4f64(<4 x double> addrspace(1)* %out, <4 x double> addrspace(1)* %in) {
+  %b_ptr = getelementptr <4 x double>, <4 x double> addrspace(1)* %in, i32 1
+  %a = load <4 x double>, <4 x double> addrspace(1)* %in
+  %b = load <4 x double>, <4 x double> addrspace(1)* %b_ptr
+  %result = fsub <4 x double> %a, %b
+  store <4 x double> %result, <4 x double> addrspace(1)* %out
+  ret void
 }
+
+; SI-LABEL: {{^}}s_fsub_v4f64:
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
+; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
+define void @s_fsub_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b) {
+  %result = fsub <4 x double> %a, %b
+  store <4 x double> %result, <4 x double> addrspace(1)* %out, align 16
+  ret void
+}
+
+attributes #0 = { nounwind readnone }
diff --git a/test/CodeGen/R600/ftrunc.f64.ll b/test/CodeGen/R600/ftrunc.f64.ll
index 2c7217ef0561..6618d8b5e57e 100644
--- a/test/CodeGen/R600/ftrunc.f64.ll
+++ b/test/CodeGen/R600/ftrunc.f64.ll
@@ -1,5 +1,6 @@
-; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
 ; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
 
 declare double @llvm.trunc.f64(double) nounwind readnone
 declare <2 x double> @llvm.trunc.v2f64(<2 x double>) nounwind readnone
@@ -13,7 +14,7 @@ declare <16 x double> @llvm.trunc.v16f64(<16 x double>) nounwind readnone
 ; SI: v_bfe_u32 {{v[0-9]+}}, {{v[0-9]+}}, 20, 11
 ; SI: s_endpgm
 define void @v_ftrunc_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
-  %x = load double addrspace(1)* %in, align 8
+  %x = load double, double addrspace(1)* %in, align 8
   %y = call double @llvm.trunc.f64(double %x) nounwind readnone
   store double %y, double addrspace(1)* %out, align 8
   ret void
@@ -23,15 +24,15 @@ define void @v_ftrunc_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
 ; CI: v_trunc_f64_e32
 
 ; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014
+; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
 ; SI: s_add_i32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01
 ; SI: s_lshr_b64
 ; SI: s_not_b64
 ; SI: s_and_b64
-; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
-; SI: cmp_lt_i32
+; SI: cmp_gt_i32
 ; SI: cndmask_b32
 ; SI: cndmask_b32
-; SI: cmp_gt_i32
+; SI: cmp_lt_i32
 ; SI: cndmask_b32
 ; SI: cndmask_b32
 ; SI: s_endpgm
diff --git a/test/CodeGen/R600/gep-address-space.ll b/test/CodeGen/R600/gep-address-space.ll
index 2d1892534dc5..471b0f6b13e7 100644
--- a/test/CodeGen/R600/gep-address-space.ll
+++ b/test/CodeGen/R600/gep-address-space.ll
@@ -1,11 +1,12 @@
 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck --check-prefix=SI --check-prefix=CHECK %s
 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s
 
 define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
 ; CHECK-LABEL: {{^}}use_gep_address_space:
 ; CHECK: v_mov_b32_e32 [[PTR:v[0-9]+]], s{{[0-9]+}}
 ; CHECK: ds_write_b32 [[PTR]], v{{[0-9]+}} offset:64
-  %p = getelementptr [1024 x i32] addrspace(3)* %array, i16 0, i16 16
+  %p = getelementptr [1024 x i32], [1024 x i32] addrspace(3)* %array, i16 0, i16 16
   store i32 99, i32 addrspace(3)* %p
   ret void
 }
@@ -17,7 +18,7 @@ define void @use_gep_address_space_large_offset([1024 x i32] addrspace(3)* %arra
 ; SI: s_or_b32
 ; CI: s_add_i32
 ; CHECK: ds_write_b32
-  %p = getelementptr [1024 x i32] addrspace(3)* %array, i16 0, i16 16384
+  %p = getelementptr [1024 x i32], [1024 x i32] addrspace(3)* %array, i16 0, i16 16384
   store i32 99, i32 addrspace(3)* %p
   ret void
 }
@@ -28,7 +29,7 @@ define void @gep_as_vector_v4(<4 x [1024 x i32] addrspace(3)*> %array) nounwind
 ; CHECK: s_add_i32
 ; CHECK: s_add_i32
 ; CHECK: s_add_i32
-  %p = getelementptr <4 x [1024 x i32] addrspace(3)*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16>
+  %p = getelementptr [1024 x i32], <4 x [1024 x i32] addrspace(3)*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16>
   %p0 = extractelement <4 x i32 addrspace(3)*> %p, i32 0
   %p1 = extractelement <4 x i32 addrspace(3)*> %p, i32 1
   %p2 = extractelement <4 x i32 addrspace(3)*> %p, i32 2
@@ -44,7 +45,7 @@ define void @gep_as_vector_v2(<2 x [1024 x i32] addrspace(3)*> %array) nounwind
 ; CHECK-LABEL: {{^}}gep_as_vector_v2:
 ; CHECK: s_add_i32
 ; CHECK: s_add_i32
-  %p = getelementptr <2 x [1024 x i32] addrspace(3)*> %array, <2 x i16> zeroinitializer, <2 x i16> <i16 16, i16 16>
+  %p = getelementptr [1024 x i32], <2 x [1024 x i32] addrspace(3)*> %array, <2 x i16> zeroinitializer, <2 x i16> <i16 16, i16 16>
   %p0 = extractelement <2 x i32 addrspace(3)*> %p, i32 0
   %p1 = extractelement <2 x i32 addrspace(3)*> %p, i32 1
   store i32 99, i32 addrspace(3)* %p0
diff --git a/test/CodeGen/R600/global-directive.ll b/test/CodeGen/R600/global-directive.ll
index 3ba12c206ad3..be775cf9292f 100644
--- a/test/CodeGen/R600/global-directive.ll
+++ b/test/CodeGen/R600/global-directive.ll
@@ -6,9 +6,9 @@
 ; SI:	.globl	foo
 ; SI: {{^}}foo:
 define void @foo(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %a = load i32 addrspace(1)* %in
-  %b = load i32 addrspace(1)* %b_ptr
+  %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %a = load i32, i32 addrspace(1)* %in
+  %b = load i32, i32 addrspace(1)* %b_ptr
   %result = add i32 %a, %b
   store i32 %result, i32 addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/global-extload-i1.ll b/test/CodeGen/R600/global-extload-i1.ll
index 5dc494900ce8..bd9557d730fb 100644
--- a/test/CodeGen/R600/global-extload-i1.ll
+++ b/test/CodeGen/R600/global-extload-i1.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 ; XUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 ; FIXME: Evergreen broken
 
@@ -8,7 +8,7 @@
 ; SI: buffer_store_dword
 ; SI: s_endpgm
 define void @zextload_global_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %a = load i1 addrspace(1)* %in
+  %a = load i1, i1 addrspace(1)* %in
   %ext = zext i1 %a to i32
   store i32 %ext, i32 addrspace(1)* %out
   ret void
@@ -20,7 +20,7 @@ define void @zextload_global_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)*
 ; SI: buffer_store_dword
 ; SI: s_endpgm
 define void @sextload_global_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %a = load i1 addrspace(1)* %in
+  %a = load i1, i1 addrspace(1)* %in
   %ext = sext i1 %a to i32
   store i32 %ext, i32 addrspace(1)* %out
   ret void
@@ -29,7 +29,7 @@ define void @sextload_global_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)*
 ; FUNC-LABEL: {{^}}zextload_global_v1i1_to_v1i32:
 ; SI: s_endpgm
 define void @zextload_global_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <1 x i1> addrspace(1)* %in
+  %load = load <1 x i1>, <1 x i1> addrspace(1)* %in
   %ext = zext <1 x i1> %load to <1 x i32>
   store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
   ret void
@@ -38,7 +38,7 @@ define void @zextload_global_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1
 ; FUNC-LABEL: {{^}}sextload_global_v1i1_to_v1i32:
 ; SI: s_endpgm
 define void @sextload_global_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <1 x i1> addrspace(1)* %in
+  %load = load <1 x i1>, <1 x i1> addrspace(1)* %in
   %ext = sext <1 x i1> %load to <1 x i32>
   store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
   ret void
@@ -47,7 +47,7 @@ define void @sextload_global_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1
 ; FUNC-LABEL: {{^}}zextload_global_v2i1_to_v2i32:
 ; SI: s_endpgm
 define void @zextload_global_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <2 x i1> addrspace(1)* %in
+  %load = load <2 x i1>, <2 x i1> addrspace(1)* %in
   %ext = zext <2 x i1> %load to <2 x i32>
   store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
   ret void
@@ -56,7 +56,7 @@ define void @zextload_global_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1
 ; FUNC-LABEL: {{^}}sextload_global_v2i1_to_v2i32:
 ; SI: s_endpgm
 define void @sextload_global_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <2 x i1> addrspace(1)* %in
+  %load = load <2 x i1>, <2 x i1> addrspace(1)* %in
   %ext = sext <2 x i1> %load to <2 x i32>
   store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
   ret void
@@ -65,7 +65,7 @@ define void @sextload_global_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1
 ; FUNC-LABEL: {{^}}zextload_global_v4i1_to_v4i32:
 ; SI: s_endpgm
 define void @zextload_global_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <4 x i1> addrspace(1)* %in
+  %load = load <4 x i1>, <4 x i1> addrspace(1)* %in
   %ext = zext <4 x i1> %load to <4 x i32>
   store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
   ret void
@@ -74,7 +74,7 @@ define void @zextload_global_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1
 ; FUNC-LABEL: {{^}}sextload_global_v4i1_to_v4i32:
 ; SI: s_endpgm
 define void @sextload_global_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <4 x i1> addrspace(1)* %in
+  %load = load <4 x i1>, <4 x i1> addrspace(1)* %in
   %ext = sext <4 x i1> %load to <4 x i32>
   store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
   ret void
@@ -83,7 +83,7 @@ define void @sextload_global_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1
 ; FUNC-LABEL: {{^}}zextload_global_v8i1_to_v8i32:
 ; SI: s_endpgm
 define void @zextload_global_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <8 x i1> addrspace(1)* %in
+  %load = load <8 x i1>, <8 x i1> addrspace(1)* %in
   %ext = zext <8 x i1> %load to <8 x i32>
   store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
   ret void
@@ -92,7 +92,7 @@ define void @zextload_global_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1
 ; FUNC-LABEL: {{^}}sextload_global_v8i1_to_v8i32:
 ; SI: s_endpgm
 define void @sextload_global_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <8 x i1> addrspace(1)* %in
+  %load = load <8 x i1>, <8 x i1> addrspace(1)* %in
   %ext = sext <8 x i1> %load to <8 x i32>
   store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
   ret void
@@ -101,7 +101,7 @@ define void @sextload_global_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1
 ; FUNC-LABEL: {{^}}zextload_global_v16i1_to_v16i32:
 ; SI: s_endpgm
 define void @zextload_global_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <16 x i1> addrspace(1)* %in
+  %load = load <16 x i1>, <16 x i1> addrspace(1)* %in
   %ext = zext <16 x i1> %load to <16 x i32>
   store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
   ret void
@@ -110,7 +110,7 @@ define void @zextload_global_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16
 ; FUNC-LABEL: {{^}}sextload_global_v16i1_to_v16i32:
 ; SI: s_endpgm
 define void @sextload_global_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <16 x i1> addrspace(1)* %in
+  %load = load <16 x i1>, <16 x i1> addrspace(1)* %in
   %ext = sext <16 x i1> %load to <16 x i32>
   store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
   ret void
@@ -119,7 +119,7 @@ define void @sextload_global_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}zextload_global_v32i1_to_v32i32:
 ; XSI: s_endpgm
 ; define void @zextload_global_v32i1_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i1> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <32 x i1> addrspace(1)* %in
+;   %load = load <32 x i1>, <32 x i1> addrspace(1)* %in
 ;   %ext = zext <32 x i1> %load to <32 x i32>
 ;   store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
 ;   ret void
@@ -128,7 +128,7 @@ define void @sextload_global_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}sextload_global_v32i1_to_v32i32:
 ; XSI: s_endpgm
 ; define void @sextload_global_v32i1_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i1> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <32 x i1> addrspace(1)* %in
+;   %load = load <32 x i1>, <32 x i1> addrspace(1)* %in
 ;   %ext = sext <32 x i1> %load to <32 x i32>
 ;   store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
 ;   ret void
@@ -137,7 +137,7 @@ define void @sextload_global_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}zextload_global_v64i1_to_v64i32:
 ; XSI: s_endpgm
 ; define void @zextload_global_v64i1_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i1> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <64 x i1> addrspace(1)* %in
+;   %load = load <64 x i1>, <64 x i1> addrspace(1)* %in
 ;   %ext = zext <64 x i1> %load to <64 x i32>
 ;   store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
 ;   ret void
@@ -146,7 +146,7 @@ define void @sextload_global_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}sextload_global_v64i1_to_v64i32:
 ; XSI: s_endpgm
 ; define void @sextload_global_v64i1_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i1> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <64 x i1> addrspace(1)* %in
+;   %load = load <64 x i1>, <64 x i1> addrspace(1)* %in
 ;   %ext = sext <64 x i1> %load to <64 x i32>
 ;   store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
 ;   ret void
@@ -157,7 +157,7 @@ define void @sextload_global_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16
 ; SI: v_mov_b32_e32 {{v[0-9]+}}, 0{{$}}
 ; SI: buffer_store_dwordx2
 define void @zextload_global_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %a = load i1 addrspace(1)* %in
+  %a = load i1, i1 addrspace(1)* %in
   %ext = zext i1 %a to i64
   store i64 %ext, i64 addrspace(1)* %out
   ret void
@@ -169,7 +169,7 @@ define void @zextload_global_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)*
 ; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]]
 ; SI: buffer_store_dwordx2
 define void @sextload_global_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %a = load i1 addrspace(1)* %in
+  %a = load i1, i1 addrspace(1)* %in
   %ext = sext i1 %a to i64
   store i64 %ext, i64 addrspace(1)* %out
   ret void
@@ -178,7 +178,7 @@ define void @sextload_global_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)*
 ; FUNC-LABEL: {{^}}zextload_global_v1i1_to_v1i64:
 ; SI: s_endpgm
 define void @zextload_global_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <1 x i1> addrspace(1)* %in
+  %load = load <1 x i1>, <1 x i1> addrspace(1)* %in
   %ext = zext <1 x i1> %load to <1 x i64>
   store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
   ret void
@@ -187,7 +187,7 @@ define void @zextload_global_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1
 ; FUNC-LABEL: {{^}}sextload_global_v1i1_to_v1i64:
 ; SI: s_endpgm
 define void @sextload_global_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <1 x i1> addrspace(1)* %in
+  %load = load <1 x i1>, <1 x i1> addrspace(1)* %in
   %ext = sext <1 x i1> %load to <1 x i64>
   store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
   ret void
@@ -196,7 +196,7 @@ define void @sextload_global_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1
 ; FUNC-LABEL: {{^}}zextload_global_v2i1_to_v2i64:
 ; SI: s_endpgm
 define void @zextload_global_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <2 x i1> addrspace(1)* %in
+  %load = load <2 x i1>, <2 x i1> addrspace(1)* %in
   %ext = zext <2 x i1> %load to <2 x i64>
   store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
   ret void
@@ -205,7 +205,7 @@ define void @zextload_global_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1
 ; FUNC-LABEL: {{^}}sextload_global_v2i1_to_v2i64:
 ; SI: s_endpgm
 define void @sextload_global_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <2 x i1> addrspace(1)* %in
+  %load = load <2 x i1>, <2 x i1> addrspace(1)* %in
   %ext = sext <2 x i1> %load to <2 x i64>
   store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
   ret void
@@ -214,7 +214,7 @@ define void @sextload_global_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1
 ; FUNC-LABEL: {{^}}zextload_global_v4i1_to_v4i64:
 ; SI: s_endpgm
 define void @zextload_global_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <4 x i1> addrspace(1)* %in
+  %load = load <4 x i1>, <4 x i1> addrspace(1)* %in
   %ext = zext <4 x i1> %load to <4 x i64>
   store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
   ret void
@@ -223,7 +223,7 @@ define void @zextload_global_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1
 ; FUNC-LABEL: {{^}}sextload_global_v4i1_to_v4i64:
 ; SI: s_endpgm
 define void @sextload_global_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <4 x i1> addrspace(1)* %in
+  %load = load <4 x i1>, <4 x i1> addrspace(1)* %in
   %ext = sext <4 x i1> %load to <4 x i64>
   store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
   ret void
@@ -232,7 +232,7 @@ define void @sextload_global_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1
 ; FUNC-LABEL: {{^}}zextload_global_v8i1_to_v8i64:
 ; SI: s_endpgm
 define void @zextload_global_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <8 x i1> addrspace(1)* %in
+  %load = load <8 x i1>, <8 x i1> addrspace(1)* %in
   %ext = zext <8 x i1> %load to <8 x i64>
   store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
   ret void
@@ -241,7 +241,7 @@ define void @zextload_global_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1
 ; FUNC-LABEL: {{^}}sextload_global_v8i1_to_v8i64:
 ; SI: s_endpgm
 define void @sextload_global_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <8 x i1> addrspace(1)* %in
+  %load = load <8 x i1>, <8 x i1> addrspace(1)* %in
   %ext = sext <8 x i1> %load to <8 x i64>
   store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
   ret void
@@ -250,7 +250,7 @@ define void @sextload_global_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1
 ; FUNC-LABEL: {{^}}zextload_global_v16i1_to_v16i64:
 ; SI: s_endpgm
 define void @zextload_global_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <16 x i1> addrspace(1)* %in
+  %load = load <16 x i1>, <16 x i1> addrspace(1)* %in
   %ext = zext <16 x i1> %load to <16 x i64>
   store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
   ret void
@@ -259,7 +259,7 @@ define void @zextload_global_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16
 ; FUNC-LABEL: {{^}}sextload_global_v16i1_to_v16i64:
 ; SI: s_endpgm
 define void @sextload_global_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i1> addrspace(1)* nocapture %in) nounwind {
-  %load = load <16 x i1> addrspace(1)* %in
+  %load = load <16 x i1>, <16 x i1> addrspace(1)* %in
   %ext = sext <16 x i1> %load to <16 x i64>
   store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
   ret void
@@ -268,7 +268,7 @@ define void @sextload_global_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}zextload_global_v32i1_to_v32i64:
 ; XSI: s_endpgm
 ; define void @zextload_global_v32i1_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i1> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <32 x i1> addrspace(1)* %in
+;   %load = load <32 x i1>, <32 x i1> addrspace(1)* %in
 ;   %ext = zext <32 x i1> %load to <32 x i64>
 ;   store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
 ;   ret void
@@ -277,7 +277,7 @@ define void @sextload_global_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}sextload_global_v32i1_to_v32i64:
 ; XSI: s_endpgm
 ; define void @sextload_global_v32i1_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i1> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <32 x i1> addrspace(1)* %in
+;   %load = load <32 x i1>, <32 x i1> addrspace(1)* %in
 ;   %ext = sext <32 x i1> %load to <32 x i64>
 ;   store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
 ;   ret void
@@ -286,7 +286,7 @@ define void @sextload_global_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}zextload_global_v64i1_to_v64i64:
 ; XSI: s_endpgm
 ; define void @zextload_global_v64i1_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i1> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <64 x i1> addrspace(1)* %in
+;   %load = load <64 x i1>, <64 x i1> addrspace(1)* %in
 ;   %ext = zext <64 x i1> %load to <64 x i64>
 ;   store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
 ;   ret void
@@ -295,7 +295,7 @@ define void @sextload_global_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}sextload_global_v64i1_to_v64i64:
 ; XSI: s_endpgm
 ; define void @sextload_global_v64i1_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i1> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <64 x i1> addrspace(1)* %in
+;   %load = load <64 x i1>, <64 x i1> addrspace(1)* %in
 ;   %ext = sext <64 x i1> %load to <64 x i64>
 ;   store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
 ;   ret void
diff --git a/test/CodeGen/R600/global-extload-i16.ll b/test/CodeGen/R600/global-extload-i16.ll
index a1740ec8236a..103a40dee270 100644
--- a/test/CodeGen/R600/global-extload-i16.ll
+++ b/test/CodeGen/R600/global-extload-i16.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 ; XUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 ; FIXME: cypress is broken because the bigger testcases spill and it's not implemented
 
@@ -8,7 +8,7 @@
 ; SI: buffer_store_dword
 ; SI: s_endpgm
 define void @zextload_global_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind {
-  %a = load i16 addrspace(1)* %in
+  %a = load i16, i16 addrspace(1)* %in
   %ext = zext i16 %a to i32
   store i32 %ext, i32 addrspace(1)* %out
   ret void
@@ -19,7 +19,7 @@ define void @zextload_global_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)
 ; SI: buffer_store_dword
 ; SI: s_endpgm
 define void @sextload_global_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind {
-  %a = load i16 addrspace(1)* %in
+  %a = load i16, i16 addrspace(1)* %in
   %ext = sext i16 %a to i32
   store i32 %ext, i32 addrspace(1)* %out
   ret void
@@ -29,7 +29,7 @@ define void @sextload_global_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)
 ; SI: buffer_load_ushort
 ; SI: s_endpgm
 define void @zextload_global_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <1 x i16> addrspace(1)* %in
+  %load = load <1 x i16>, <1 x i16> addrspace(1)* %in
   %ext = zext <1 x i16> %load to <1 x i32>
   store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
   ret void
@@ -39,7 +39,7 @@ define void @zextload_global_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i
 ; SI: buffer_load_sshort
 ; SI: s_endpgm
 define void @sextload_global_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <1 x i16> addrspace(1)* %in
+  %load = load <1 x i16>, <1 x i16> addrspace(1)* %in
   %ext = sext <1 x i16> %load to <1 x i32>
   store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
   ret void
@@ -48,7 +48,7 @@ define void @sextload_global_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i
 ; FUNC-LABEL: {{^}}zextload_global_v2i16_to_v2i32:
 ; SI: s_endpgm
 define void @zextload_global_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <2 x i16> addrspace(1)* %in
+  %load = load <2 x i16>, <2 x i16> addrspace(1)* %in
   %ext = zext <2 x i16> %load to <2 x i32>
   store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
   ret void
@@ -57,7 +57,7 @@ define void @zextload_global_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i
 ; FUNC-LABEL: {{^}}sextload_global_v2i16_to_v2i32:
 ; SI: s_endpgm
 define void @sextload_global_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <2 x i16> addrspace(1)* %in
+  %load = load <2 x i16>, <2 x i16> addrspace(1)* %in
   %ext = sext <2 x i16> %load to <2 x i32>
   store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
   ret void
@@ -66,7 +66,7 @@ define void @sextload_global_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i
 ; FUNC-LABEL: {{^}}zextload_global_v4i16_to_v4i32:
 ; SI: s_endpgm
 define void @zextload_global_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <4 x i16> addrspace(1)* %in
+  %load = load <4 x i16>, <4 x i16> addrspace(1)* %in
   %ext = zext <4 x i16> %load to <4 x i32>
   store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
   ret void
@@ -75,7 +75,7 @@ define void @zextload_global_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i
 ; FUNC-LABEL: {{^}}sextload_global_v4i16_to_v4i32:
 ; SI: s_endpgm
 define void @sextload_global_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <4 x i16> addrspace(1)* %in
+  %load = load <4 x i16>, <4 x i16> addrspace(1)* %in
   %ext = sext <4 x i16> %load to <4 x i32>
   store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
   ret void
@@ -84,7 +84,7 @@ define void @sextload_global_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i
 ; FUNC-LABEL: {{^}}zextload_global_v8i16_to_v8i32:
 ; SI: s_endpgm
 define void @zextload_global_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <8 x i16> addrspace(1)* %in
+  %load = load <8 x i16>, <8 x i16> addrspace(1)* %in
   %ext = zext <8 x i16> %load to <8 x i32>
   store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
   ret void
@@ -93,7 +93,7 @@ define void @zextload_global_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i
 ; FUNC-LABEL: {{^}}sextload_global_v8i16_to_v8i32:
 ; SI: s_endpgm
 define void @sextload_global_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <8 x i16> addrspace(1)* %in
+  %load = load <8 x i16>, <8 x i16> addrspace(1)* %in
   %ext = sext <8 x i16> %load to <8 x i32>
   store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
   ret void
@@ -102,7 +102,7 @@ define void @sextload_global_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i
 ; FUNC-LABEL: {{^}}zextload_global_v16i16_to_v16i32:
 ; SI: s_endpgm
 define void @zextload_global_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <16 x i16> addrspace(1)* %in
+  %load = load <16 x i16>, <16 x i16> addrspace(1)* %in
   %ext = zext <16 x i16> %load to <16 x i32>
   store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
   ret void
@@ -111,7 +111,7 @@ define void @zextload_global_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16
 ; FUNC-LABEL: {{^}}sextload_global_v16i16_to_v16i32:
 ; SI: s_endpgm
 define void @sextload_global_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <16 x i16> addrspace(1)* %in
+  %load = load <16 x i16>, <16 x i16> addrspace(1)* %in
   %ext = sext <16 x i16> %load to <16 x i32>
   store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
   ret void
@@ -120,7 +120,7 @@ define void @sextload_global_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16
 ; FUNC-LABEL: {{^}}zextload_global_v32i16_to_v32i32:
 ; SI: s_endpgm
 define void @zextload_global_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <32 x i16> addrspace(1)* %in
+  %load = load <32 x i16>, <32 x i16> addrspace(1)* %in
   %ext = zext <32 x i16> %load to <32 x i32>
   store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
   ret void
@@ -129,7 +129,7 @@ define void @zextload_global_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32
 ; FUNC-LABEL: {{^}}sextload_global_v32i16_to_v32i32:
 ; SI: s_endpgm
 define void @sextload_global_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <32 x i16> addrspace(1)* %in
+  %load = load <32 x i16>, <32 x i16> addrspace(1)* %in
   %ext = sext <32 x i16> %load to <32 x i32>
   store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
   ret void
@@ -138,7 +138,7 @@ define void @sextload_global_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32
 ; FUNC-LABEL: {{^}}zextload_global_v64i16_to_v64i32:
 ; SI: s_endpgm
 define void @zextload_global_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <64 x i16> addrspace(1)* %in
+  %load = load <64 x i16>, <64 x i16> addrspace(1)* %in
   %ext = zext <64 x i16> %load to <64 x i32>
   store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
   ret void
@@ -147,7 +147,7 @@ define void @zextload_global_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64
 ; FUNC-LABEL: {{^}}sextload_global_v64i16_to_v64i32:
 ; SI: s_endpgm
 define void @sextload_global_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <64 x i16> addrspace(1)* %in
+  %load = load <64 x i16>, <64 x i16> addrspace(1)* %in
   %ext = sext <64 x i16> %load to <64 x i32>
   store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
   ret void
@@ -158,7 +158,7 @@ define void @sextload_global_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64
 ; SI: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
 ; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]]
 define void @zextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind {
-  %a = load i16 addrspace(1)* %in
+  %a = load i16, i16 addrspace(1)* %in
   %ext = zext i16 %a to i64
   store i64 %ext, i64 addrspace(1)* %out
   ret void
@@ -169,7 +169,7 @@ define void @zextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)
 ; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[LOAD]]
 ; SI: buffer_store_dwordx2
 define void @sextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind {
-  %a = load i16 addrspace(1)* %in
+  %a = load i16, i16 addrspace(1)* %in
   %ext = sext i16 %a to i64
   store i64 %ext, i64 addrspace(1)* %out
   ret void
@@ -178,7 +178,7 @@ define void @sextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)
 ; FUNC-LABEL: {{^}}zextload_global_v1i16_to_v1i64:
 ; SI: s_endpgm
 define void @zextload_global_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <1 x i16> addrspace(1)* %in
+  %load = load <1 x i16>, <1 x i16> addrspace(1)* %in
   %ext = zext <1 x i16> %load to <1 x i64>
   store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
   ret void
@@ -187,7 +187,7 @@ define void @zextload_global_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i
 ; FUNC-LABEL: {{^}}sextload_global_v1i16_to_v1i64:
 ; SI: s_endpgm
 define void @sextload_global_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <1 x i16> addrspace(1)* %in
+  %load = load <1 x i16>, <1 x i16> addrspace(1)* %in
   %ext = sext <1 x i16> %load to <1 x i64>
   store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
   ret void
@@ -196,7 +196,7 @@ define void @sextload_global_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i
 ; FUNC-LABEL: {{^}}zextload_global_v2i16_to_v2i64:
 ; SI: s_endpgm
 define void @zextload_global_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <2 x i16> addrspace(1)* %in
+  %load = load <2 x i16>, <2 x i16> addrspace(1)* %in
   %ext = zext <2 x i16> %load to <2 x i64>
   store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
   ret void
@@ -205,7 +205,7 @@ define void @zextload_global_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i
 ; FUNC-LABEL: {{^}}sextload_global_v2i16_to_v2i64:
 ; SI: s_endpgm
 define void @sextload_global_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <2 x i16> addrspace(1)* %in
+  %load = load <2 x i16>, <2 x i16> addrspace(1)* %in
   %ext = sext <2 x i16> %load to <2 x i64>
   store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
   ret void
@@ -214,7 +214,7 @@ define void @sextload_global_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i
 ; FUNC-LABEL: {{^}}zextload_global_v4i16_to_v4i64:
 ; SI: s_endpgm
 define void @zextload_global_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <4 x i16> addrspace(1)* %in
+  %load = load <4 x i16>, <4 x i16> addrspace(1)* %in
   %ext = zext <4 x i16> %load to <4 x i64>
   store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
   ret void
@@ -223,7 +223,7 @@ define void @zextload_global_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i
 ; FUNC-LABEL: {{^}}sextload_global_v4i16_to_v4i64:
 ; SI: s_endpgm
 define void @sextload_global_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <4 x i16> addrspace(1)* %in
+  %load = load <4 x i16>, <4 x i16> addrspace(1)* %in
   %ext = sext <4 x i16> %load to <4 x i64>
   store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
   ret void
@@ -232,7 +232,7 @@ define void @sextload_global_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i
 ; FUNC-LABEL: {{^}}zextload_global_v8i16_to_v8i64:
 ; SI: s_endpgm
 define void @zextload_global_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <8 x i16> addrspace(1)* %in
+  %load = load <8 x i16>, <8 x i16> addrspace(1)* %in
   %ext = zext <8 x i16> %load to <8 x i64>
   store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
   ret void
@@ -241,7 +241,7 @@ define void @zextload_global_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i
 ; FUNC-LABEL: {{^}}sextload_global_v8i16_to_v8i64:
 ; SI: s_endpgm
 define void @sextload_global_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <8 x i16> addrspace(1)* %in
+  %load = load <8 x i16>, <8 x i16> addrspace(1)* %in
   %ext = sext <8 x i16> %load to <8 x i64>
   store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
   ret void
@@ -250,7 +250,7 @@ define void @sextload_global_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i
 ; FUNC-LABEL: {{^}}zextload_global_v16i16_to_v16i64:
 ; SI: s_endpgm
 define void @zextload_global_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <16 x i16> addrspace(1)* %in
+  %load = load <16 x i16>, <16 x i16> addrspace(1)* %in
   %ext = zext <16 x i16> %load to <16 x i64>
   store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
   ret void
@@ -259,7 +259,7 @@ define void @zextload_global_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16
 ; FUNC-LABEL: {{^}}sextload_global_v16i16_to_v16i64:
 ; SI: s_endpgm
 define void @sextload_global_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <16 x i16> addrspace(1)* %in
+  %load = load <16 x i16>, <16 x i16> addrspace(1)* %in
   %ext = sext <16 x i16> %load to <16 x i64>
   store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
   ret void
@@ -268,7 +268,7 @@ define void @sextload_global_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16
 ; FUNC-LABEL: {{^}}zextload_global_v32i16_to_v32i64:
 ; SI: s_endpgm
 define void @zextload_global_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <32 x i16> addrspace(1)* %in
+  %load = load <32 x i16>, <32 x i16> addrspace(1)* %in
   %ext = zext <32 x i16> %load to <32 x i64>
   store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
   ret void
@@ -277,7 +277,7 @@ define void @zextload_global_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32
 ; FUNC-LABEL: {{^}}sextload_global_v32i16_to_v32i64:
 ; SI: s_endpgm
 define void @sextload_global_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <32 x i16> addrspace(1)* %in
+  %load = load <32 x i16>, <32 x i16> addrspace(1)* %in
   %ext = sext <32 x i16> %load to <32 x i64>
   store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
   ret void
@@ -286,7 +286,7 @@ define void @sextload_global_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32
 ; FUNC-LABEL: {{^}}zextload_global_v64i16_to_v64i64:
 ; SI: s_endpgm
 define void @zextload_global_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <64 x i16> addrspace(1)* %in
+  %load = load <64 x i16>, <64 x i16> addrspace(1)* %in
   %ext = zext <64 x i16> %load to <64 x i64>
   store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
   ret void
@@ -295,7 +295,7 @@ define void @zextload_global_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64
 ; FUNC-LABEL: {{^}}sextload_global_v64i16_to_v64i64:
 ; SI: s_endpgm
 define void @sextload_global_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(1)* nocapture %in) nounwind {
-  %load = load <64 x i16> addrspace(1)* %in
+  %load = load <64 x i16>, <64 x i16> addrspace(1)* %in
   %ext = sext <64 x i16> %load to <64 x i64>
   store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/global-extload-i32.ll b/test/CodeGen/R600/global-extload-i32.ll
index f56b6ac8dc38..79b83452939e 100644
--- a/test/CodeGen/R600/global-extload-i32.ll
+++ b/test/CodeGen/R600/global-extload-i32.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 
 ; FUNC-LABEL: {{^}}zextload_global_i32_to_i64:
@@ -7,7 +7,7 @@
 ; SI: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
 ; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]]
 define void @zextload_global_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %a = load i32 addrspace(1)* %in
+  %a = load i32, i32 addrspace(1)* %in
   %ext = zext i32 %a to i64
   store i64 %ext, i64 addrspace(1)* %out
   ret void
@@ -18,7 +18,7 @@ define void @zextload_global_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)
 ; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[LOAD]]
 ; SI: buffer_store_dwordx2
 define void @sextload_global_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %a = load i32 addrspace(1)* %in
+  %a = load i32, i32 addrspace(1)* %in
   %ext = sext i32 %a to i64
   store i64 %ext, i64 addrspace(1)* %out
   ret void
@@ -29,7 +29,7 @@ define void @sextload_global_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)
 ; SI: buffer_store_dwordx2
 ; SI: s_endpgm
 define void @zextload_global_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* nocapture %in) nounwind {
-  %load = load <1 x i32> addrspace(1)* %in
+  %load = load <1 x i32>, <1 x i32> addrspace(1)* %in
   %ext = zext <1 x i32> %load to <1 x i64>
   store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
   ret void
@@ -41,7 +41,7 @@ define void @zextload_global_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i
 ; SI: buffer_store_dwordx2
 ; SI: s_endpgm
 define void @sextload_global_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* nocapture %in) nounwind {
-  %load = load <1 x i32> addrspace(1)* %in
+  %load = load <1 x i32>, <1 x i32> addrspace(1)* %in
   %ext = sext <1 x i32> %load to <1 x i64>
   store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
   ret void
@@ -53,7 +53,7 @@ define void @sextload_global_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i
 ; SI: buffer_store_dwordx2
 ; SI: s_endpgm
 define void @zextload_global_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(1)* nocapture %in) nounwind {
-  %load = load <2 x i32> addrspace(1)* %in
+  %load = load <2 x i32>, <2 x i32> addrspace(1)* %in
   %ext = zext <2 x i32> %load to <2 x i64>
   store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
   ret void
@@ -67,7 +67,7 @@ define void @zextload_global_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i
 ; SI-DAG: buffer_store_dwordx2
 ; SI: s_endpgm
 define void @sextload_global_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(1)* nocapture %in) nounwind {
-  %load = load <2 x i32> addrspace(1)* %in
+  %load = load <2 x i32>, <2 x i32> addrspace(1)* %in
   %ext = sext <2 x i32> %load to <2 x i64>
   store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
   ret void
@@ -81,7 +81,7 @@ define void @sextload_global_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i
 ; SI: buffer_store_dwordx2
 ; SI: s_endpgm
 define void @zextload_global_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(1)* nocapture %in) nounwind {
-  %load = load <4 x i32> addrspace(1)* %in
+  %load = load <4 x i32>, <4 x i32> addrspace(1)* %in
   %ext = zext <4 x i32> %load to <4 x i64>
   store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
   ret void
@@ -99,7 +99,7 @@ define void @zextload_global_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i
 ; SI-DAG: buffer_store_dwordx2
 ; SI: s_endpgm
 define void @sextload_global_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(1)* nocapture %in) nounwind {
-  %load = load <4 x i32> addrspace(1)* %in
+  %load = load <4 x i32>, <4 x i32> addrspace(1)* %in
   %ext = sext <4 x i32> %load to <4 x i64>
   store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
   ret void
@@ -124,7 +124,7 @@ define void @sextload_global_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i
 ; SI-DAG: buffer_store_dwordx2
 ; SI: s_endpgm
 define void @zextload_global_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(1)* nocapture %in) nounwind {
-  %load = load <8 x i32> addrspace(1)* %in
+  %load = load <8 x i32>, <8 x i32> addrspace(1)* %in
   %ext = zext <8 x i32> %load to <8 x i64>
   store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
   ret void
@@ -159,7 +159,7 @@ define void @zextload_global_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i
 
 ; SI: s_endpgm
 define void @sextload_global_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(1)* nocapture %in) nounwind {
-  %load = load <8 x i32> addrspace(1)* %in
+  %load = load <8 x i32>, <8 x i32> addrspace(1)* %in
   %ext = sext <8 x i32> %load to <8 x i64>
   store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
   ret void
@@ -212,7 +212,7 @@ define void @sextload_global_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i
 ; SI-DAG: buffer_store_dwordx2
 ; SI: s_endpgm
 define void @sextload_global_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(1)* nocapture %in) nounwind {
-  %load = load <16 x i32> addrspace(1)* %in
+  %load = load <16 x i32>, <16 x i32> addrspace(1)* %in
   %ext = sext <16 x i32> %load to <16 x i64>
   store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
   ret void
@@ -255,7 +255,7 @@ define void @sextload_global_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16
 
 ; SI: s_endpgm
 define void @zextload_global_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(1)* nocapture %in) nounwind {
-  %load = load <16 x i32> addrspace(1)* %in
+  %load = load <16 x i32>, <16 x i32> addrspace(1)* %in
   %ext = zext <16 x i32> %load to <16 x i64>
   store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
   ret void
@@ -369,7 +369,7 @@ define void @zextload_global_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16
 
 ; SI: s_endpgm
 define void @sextload_global_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* nocapture %in) nounwind {
-  %load = load <32 x i32> addrspace(1)* %in
+  %load = load <32 x i32>, <32 x i32> addrspace(1)* %in
   %ext = sext <32 x i32> %load to <32 x i64>
   store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
   ret void
@@ -450,7 +450,7 @@ define void @sextload_global_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32
 
 ; SI: s_endpgm
 define void @zextload_global_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* nocapture %in) nounwind {
-  %load = load <32 x i32> addrspace(1)* %in
+  %load = load <32 x i32>, <32 x i32> addrspace(1)* %in
   %ext = zext <32 x i32> %load to <32 x i64>
   store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/global-extload-i8.ll b/test/CodeGen/R600/global-extload-i8.ll
index 86245232d3e4..b31d5361d5a2 100644
--- a/test/CodeGen/R600/global-extload-i8.ll
+++ b/test/CodeGen/R600/global-extload-i8.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 
 ; FUNC-LABEL: {{^}}zextload_global_i8_to_i32:
@@ -7,7 +7,7 @@
 ; SI: buffer_store_dword
 ; SI: s_endpgm
 define void @zextload_global_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind {
-  %a = load i8 addrspace(1)* %in
+  %a = load i8, i8 addrspace(1)* %in
   %ext = zext i8 %a to i32
   store i32 %ext, i32 addrspace(1)* %out
   ret void
@@ -18,7 +18,7 @@ define void @zextload_global_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(1)*
 ; SI: buffer_store_dword
 ; SI: s_endpgm
 define void @sextload_global_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind {
-  %a = load i8 addrspace(1)* %in
+  %a = load i8, i8 addrspace(1)* %in
   %ext = sext i8 %a to i32
   store i32 %ext, i32 addrspace(1)* %out
   ret void
@@ -27,7 +27,7 @@ define void @sextload_global_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(1)*
 ; FUNC-LABEL: {{^}}zextload_global_v1i8_to_v1i32:
 ; SI: s_endpgm
 define void @zextload_global_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <1 x i8> addrspace(1)* %in
+  %load = load <1 x i8>, <1 x i8> addrspace(1)* %in
   %ext = zext <1 x i8> %load to <1 x i32>
   store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
   ret void
@@ -36,7 +36,7 @@ define void @zextload_global_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8
 ; FUNC-LABEL: {{^}}sextload_global_v1i8_to_v1i32:
 ; SI: s_endpgm
 define void @sextload_global_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <1 x i8> addrspace(1)* %in
+  %load = load <1 x i8>, <1 x i8> addrspace(1)* %in
   %ext = sext <1 x i8> %load to <1 x i32>
   store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
   ret void
@@ -45,7 +45,7 @@ define void @sextload_global_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8
 ; FUNC-LABEL: {{^}}zextload_global_v2i8_to_v2i32:
 ; SI: s_endpgm
 define void @zextload_global_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <2 x i8> addrspace(1)* %in
+  %load = load <2 x i8>, <2 x i8> addrspace(1)* %in
   %ext = zext <2 x i8> %load to <2 x i32>
   store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
   ret void
@@ -54,7 +54,7 @@ define void @zextload_global_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8
 ; FUNC-LABEL: {{^}}sextload_global_v2i8_to_v2i32:
 ; SI: s_endpgm
 define void @sextload_global_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <2 x i8> addrspace(1)* %in
+  %load = load <2 x i8>, <2 x i8> addrspace(1)* %in
   %ext = sext <2 x i8> %load to <2 x i32>
   store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
   ret void
@@ -63,7 +63,7 @@ define void @sextload_global_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8
 ; FUNC-LABEL: {{^}}zextload_global_v4i8_to_v4i32:
 ; SI: s_endpgm
 define void @zextload_global_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <4 x i8> addrspace(1)* %in
+  %load = load <4 x i8>, <4 x i8> addrspace(1)* %in
   %ext = zext <4 x i8> %load to <4 x i32>
   store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
   ret void
@@ -72,7 +72,7 @@ define void @zextload_global_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8
 ; FUNC-LABEL: {{^}}sextload_global_v4i8_to_v4i32:
 ; SI: s_endpgm
 define void @sextload_global_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <4 x i8> addrspace(1)* %in
+  %load = load <4 x i8>, <4 x i8> addrspace(1)* %in
   %ext = sext <4 x i8> %load to <4 x i32>
   store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
   ret void
@@ -81,7 +81,7 @@ define void @sextload_global_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8
 ; FUNC-LABEL: {{^}}zextload_global_v8i8_to_v8i32:
 ; SI: s_endpgm
 define void @zextload_global_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <8 x i8> addrspace(1)* %in
+  %load = load <8 x i8>, <8 x i8> addrspace(1)* %in
   %ext = zext <8 x i8> %load to <8 x i32>
   store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
   ret void
@@ -90,7 +90,7 @@ define void @zextload_global_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8
 ; FUNC-LABEL: {{^}}sextload_global_v8i8_to_v8i32:
 ; SI: s_endpgm
 define void @sextload_global_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <8 x i8> addrspace(1)* %in
+  %load = load <8 x i8>, <8 x i8> addrspace(1)* %in
   %ext = sext <8 x i8> %load to <8 x i32>
   store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
   ret void
@@ -99,7 +99,7 @@ define void @sextload_global_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8
 ; FUNC-LABEL: {{^}}zextload_global_v16i8_to_v16i32:
 ; SI: s_endpgm
 define void @zextload_global_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <16 x i8> addrspace(1)* %in
+  %load = load <16 x i8>, <16 x i8> addrspace(1)* %in
   %ext = zext <16 x i8> %load to <16 x i32>
   store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
   ret void
@@ -108,7 +108,7 @@ define void @zextload_global_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16
 ; FUNC-LABEL: {{^}}sextload_global_v16i8_to_v16i32:
 ; SI: s_endpgm
 define void @sextload_global_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <16 x i8> addrspace(1)* %in
+  %load = load <16 x i8>, <16 x i8> addrspace(1)* %in
   %ext = sext <16 x i8> %load to <16 x i32>
   store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
   ret void
@@ -117,7 +117,7 @@ define void @sextload_global_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}zextload_global_v32i8_to_v32i32:
 ; XSI: s_endpgm
 ; define void @zextload_global_v32i8_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i8> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <32 x i8> addrspace(1)* %in
+;   %load = load <32 x i8>, <32 x i8> addrspace(1)* %in
 ;   %ext = zext <32 x i8> %load to <32 x i32>
 ;   store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
 ;   ret void
@@ -126,7 +126,7 @@ define void @sextload_global_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}sextload_global_v32i8_to_v32i32:
 ; XSI: s_endpgm
 ; define void @sextload_global_v32i8_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i8> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <32 x i8> addrspace(1)* %in
+;   %load = load <32 x i8>, <32 x i8> addrspace(1)* %in
 ;   %ext = sext <32 x i8> %load to <32 x i32>
 ;   store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
 ;   ret void
@@ -135,7 +135,7 @@ define void @sextload_global_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}zextload_global_v64i8_to_v64i32:
 ; XSI: s_endpgm
 ; define void @zextload_global_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <64 x i8> addrspace(1)* %in
+;   %load = load <64 x i8>, <64 x i8> addrspace(1)* %in
 ;   %ext = zext <64 x i8> %load to <64 x i32>
 ;   store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
 ;   ret void
@@ -144,7 +144,7 @@ define void @sextload_global_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}sextload_global_v64i8_to_v64i32:
 ; XSI: s_endpgm
 ; define void @sextload_global_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <64 x i8> addrspace(1)* %in
+;   %load = load <64 x i8>, <64 x i8> addrspace(1)* %in
 ;   %ext = sext <64 x i8> %load to <64 x i32>
 ;   store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
 ;   ret void
@@ -155,7 +155,7 @@ define void @sextload_global_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16
 ; SI: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
 ; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]]
 define void @zextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind {
-  %a = load i8 addrspace(1)* %in
+  %a = load i8, i8 addrspace(1)* %in
   %ext = zext i8 %a to i64
   store i64 %ext, i64 addrspace(1)* %out
   ret void
@@ -166,7 +166,7 @@ define void @zextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)*
 ; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[LOAD]]
 ; SI: buffer_store_dwordx2
 define void @sextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind {
-  %a = load i8 addrspace(1)* %in
+  %a = load i8, i8 addrspace(1)* %in
   %ext = sext i8 %a to i64
   store i64 %ext, i64 addrspace(1)* %out
   ret void
@@ -175,7 +175,7 @@ define void @sextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)*
 ; FUNC-LABEL: {{^}}zextload_global_v1i8_to_v1i64:
 ; SI: s_endpgm
 define void @zextload_global_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <1 x i8> addrspace(1)* %in
+  %load = load <1 x i8>, <1 x i8> addrspace(1)* %in
   %ext = zext <1 x i8> %load to <1 x i64>
   store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
   ret void
@@ -184,7 +184,7 @@ define void @zextload_global_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8
 ; FUNC-LABEL: {{^}}sextload_global_v1i8_to_v1i64:
 ; SI: s_endpgm
 define void @sextload_global_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <1 x i8> addrspace(1)* %in
+  %load = load <1 x i8>, <1 x i8> addrspace(1)* %in
   %ext = sext <1 x i8> %load to <1 x i64>
   store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
   ret void
@@ -193,7 +193,7 @@ define void @sextload_global_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8
 ; FUNC-LABEL: {{^}}zextload_global_v2i8_to_v2i64:
 ; SI: s_endpgm
 define void @zextload_global_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <2 x i8> addrspace(1)* %in
+  %load = load <2 x i8>, <2 x i8> addrspace(1)* %in
   %ext = zext <2 x i8> %load to <2 x i64>
   store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
   ret void
@@ -202,7 +202,7 @@ define void @zextload_global_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8
 ; FUNC-LABEL: {{^}}sextload_global_v2i8_to_v2i64:
 ; SI: s_endpgm
 define void @sextload_global_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <2 x i8> addrspace(1)* %in
+  %load = load <2 x i8>, <2 x i8> addrspace(1)* %in
   %ext = sext <2 x i8> %load to <2 x i64>
   store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
   ret void
@@ -211,7 +211,7 @@ define void @sextload_global_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8
 ; FUNC-LABEL: {{^}}zextload_global_v4i8_to_v4i64:
 ; SI: s_endpgm
 define void @zextload_global_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <4 x i8> addrspace(1)* %in
+  %load = load <4 x i8>, <4 x i8> addrspace(1)* %in
   %ext = zext <4 x i8> %load to <4 x i64>
   store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
   ret void
@@ -220,7 +220,7 @@ define void @zextload_global_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8
 ; FUNC-LABEL: {{^}}sextload_global_v4i8_to_v4i64:
 ; SI: s_endpgm
 define void @sextload_global_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <4 x i8> addrspace(1)* %in
+  %load = load <4 x i8>, <4 x i8> addrspace(1)* %in
   %ext = sext <4 x i8> %load to <4 x i64>
   store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
   ret void
@@ -229,7 +229,7 @@ define void @sextload_global_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8
 ; FUNC-LABEL: {{^}}zextload_global_v8i8_to_v8i64:
 ; SI: s_endpgm
 define void @zextload_global_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <8 x i8> addrspace(1)* %in
+  %load = load <8 x i8>, <8 x i8> addrspace(1)* %in
   %ext = zext <8 x i8> %load to <8 x i64>
   store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
   ret void
@@ -238,7 +238,7 @@ define void @zextload_global_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8
 ; FUNC-LABEL: {{^}}sextload_global_v8i8_to_v8i64:
 ; SI: s_endpgm
 define void @sextload_global_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <8 x i8> addrspace(1)* %in
+  %load = load <8 x i8>, <8 x i8> addrspace(1)* %in
   %ext = sext <8 x i8> %load to <8 x i64>
   store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
   ret void
@@ -247,7 +247,7 @@ define void @sextload_global_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8
 ; FUNC-LABEL: {{^}}zextload_global_v16i8_to_v16i64:
 ; SI: s_endpgm
 define void @zextload_global_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <16 x i8> addrspace(1)* %in
+  %load = load <16 x i8>, <16 x i8> addrspace(1)* %in
   %ext = zext <16 x i8> %load to <16 x i64>
   store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
   ret void
@@ -256,7 +256,7 @@ define void @zextload_global_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16
 ; FUNC-LABEL: {{^}}sextload_global_v16i8_to_v16i64:
 ; SI: s_endpgm
 define void @sextload_global_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i8> addrspace(1)* nocapture %in) nounwind {
-  %load = load <16 x i8> addrspace(1)* %in
+  %load = load <16 x i8>, <16 x i8> addrspace(1)* %in
   %ext = sext <16 x i8> %load to <16 x i64>
   store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
   ret void
@@ -265,7 +265,7 @@ define void @sextload_global_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}zextload_global_v32i8_to_v32i64:
 ; XSI: s_endpgm
 ; define void @zextload_global_v32i8_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i8> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <32 x i8> addrspace(1)* %in
+;   %load = load <32 x i8>, <32 x i8> addrspace(1)* %in
 ;   %ext = zext <32 x i8> %load to <32 x i64>
 ;   store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
 ;   ret void
@@ -274,7 +274,7 @@ define void @sextload_global_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}sextload_global_v32i8_to_v32i64:
 ; XSI: s_endpgm
 ; define void @sextload_global_v32i8_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i8> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <32 x i8> addrspace(1)* %in
+;   %load = load <32 x i8>, <32 x i8> addrspace(1)* %in
 ;   %ext = sext <32 x i8> %load to <32 x i64>
 ;   store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
 ;   ret void
@@ -283,7 +283,7 @@ define void @sextload_global_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}zextload_global_v64i8_to_v64i64:
 ; XSI: s_endpgm
 ; define void @zextload_global_v64i8_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i8> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <64 x i8> addrspace(1)* %in
+;   %load = load <64 x i8>, <64 x i8> addrspace(1)* %in
 ;   %ext = zext <64 x i8> %load to <64 x i64>
 ;   store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
 ;   ret void
@@ -292,7 +292,7 @@ define void @sextload_global_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16
 ; XFUNC-LABEL: {{^}}sextload_global_v64i8_to_v64i64:
 ; XSI: s_endpgm
 ; define void @sextload_global_v64i8_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i8> addrspace(1)* nocapture %in) nounwind {
-;   %load = load <64 x i8> addrspace(1)* %in
+;   %load = load <64 x i8>, <64 x i8> addrspace(1)* %in
 ;   %ext = sext <64 x i8> %load to <64 x i64>
 ;   store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
 ;   ret void
diff --git a/test/CodeGen/R600/global-zero-initializer.ll b/test/CodeGen/R600/global-zero-initializer.ll
index 6909c58354c5..45aa8bf4e1d7 100644
--- a/test/CodeGen/R600/global-zero-initializer.ll
+++ b/test/CodeGen/R600/global-zero-initializer.ll
@@ -6,8 +6,8 @@
 @lds = addrspace(1) global [256 x i32] zeroinitializer
 
 define void @load_init_global_global(i32 addrspace(1)* %out, i1 %p) {
- %gep = getelementptr [256 x i32] addrspace(1)* @lds, i32 0, i32 10
-  %ld = load i32 addrspace(1)* %gep
+ %gep = getelementptr [256 x i32], [256 x i32] addrspace(1)* @lds, i32 0, i32 10
+  %ld = load i32, i32 addrspace(1)* %gep
   store i32 %ld, i32 addrspace(1)* %out
   ret void
 }
diff --git a/test/CodeGen/R600/global_atomics.ll b/test/CodeGen/R600/global_atomics.ll
index 5a07a028f44f..847950f6376e 100644
--- a/test/CodeGen/R600/global_atomics.ll
+++ b/test/CodeGen/R600/global_atomics.ll
@@ -4,7 +4,7 @@
 ; SI: buffer_atomic_add v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
 define void @atomic_add_i32_offset(i32 addrspace(1)* %out, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -14,7 +14,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_add_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -24,8 +24,8 @@ entry:
 ; SI: buffer_atomic_add v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
 define void @atomic_add_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -35,8 +35,8 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_add_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -64,7 +64,7 @@ entry:
 ; SI: buffer_atomic_add v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
 define void @atomic_add_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile add i32 addrspace(1)* %ptr, i32 %in seq_cst
   ret void
 }
@@ -74,7 +74,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_add_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile add i32 addrspace(1)* %ptr, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -84,7 +84,7 @@ entry:
 ; SI: buffer_atomic_and v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
 define void @atomic_and_i32_offset(i32 addrspace(1)* %out, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -94,7 +94,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_and_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -104,8 +104,8 @@ entry:
 ; SI: buffer_atomic_and v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
 define void @atomic_and_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -115,8 +115,8 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_and_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -144,7 +144,7 @@ entry:
 ; SI: buffer_atomic_and v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
 define void @atomic_and_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile and i32 addrspace(1)* %ptr, i32 %in seq_cst
   ret void
 }
@@ -154,7 +154,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_and_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile and i32 addrspace(1)* %ptr, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -164,7 +164,7 @@ entry:
 ; SI: buffer_atomic_sub v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
 define void @atomic_sub_i32_offset(i32 addrspace(1)* %out, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -174,7 +174,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_sub_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -184,8 +184,8 @@ entry:
 ; SI: buffer_atomic_sub v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
 define void @atomic_sub_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -195,8 +195,8 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_sub_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -224,7 +224,7 @@ entry:
 ; SI: buffer_atomic_sub v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
 define void @atomic_sub_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile sub i32 addrspace(1)* %ptr, i32 %in seq_cst
   ret void
 }
@@ -234,7 +234,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_sub_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile sub i32 addrspace(1)* %ptr, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -244,7 +244,7 @@ entry:
 ; SI: buffer_atomic_smax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
 define void @atomic_max_i32_offset(i32 addrspace(1)* %out, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -254,7 +254,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_max_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -264,8 +264,8 @@ entry:
 ; SI: buffer_atomic_smax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
 define void @atomic_max_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -275,8 +275,8 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_max_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -304,7 +304,7 @@ entry:
 ; SI: buffer_atomic_smax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
 define void @atomic_max_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile max i32 addrspace(1)* %ptr, i32 %in seq_cst
   ret void
 }
@@ -314,7 +314,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_max_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile max i32 addrspace(1)* %ptr, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -324,7 +324,7 @@ entry:
 ; SI: buffer_atomic_umax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
 define void @atomic_umax_i32_offset(i32 addrspace(1)* %out, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -334,7 +334,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_umax_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -344,8 +344,8 @@ entry:
 ; SI: buffer_atomic_umax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
 define void @atomic_umax_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -355,8 +355,8 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_umax_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -384,7 +384,7 @@ entry:
 ; SI: buffer_atomic_umax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
 define void @atomic_umax_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile umax i32 addrspace(1)* %ptr, i32 %in seq_cst
   ret void
 }
@@ -394,7 +394,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_umax_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile umax i32 addrspace(1)* %ptr, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -404,7 +404,7 @@ entry:
 ; SI: buffer_atomic_smin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
 define void @atomic_min_i32_offset(i32 addrspace(1)* %out, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -414,7 +414,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_min_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -424,8 +424,8 @@ entry:
 ; SI: buffer_atomic_smin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
 define void @atomic_min_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -435,8 +435,8 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_min_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -464,7 +464,7 @@ entry:
 ; SI: buffer_atomic_smin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
 define void @atomic_min_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile min i32 addrspace(1)* %ptr, i32 %in seq_cst
   ret void
 }
@@ -474,7 +474,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_min_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile min i32 addrspace(1)* %ptr, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -484,7 +484,7 @@ entry:
 ; SI: buffer_atomic_umin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
 define void @atomic_umin_i32_offset(i32 addrspace(1)* %out, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -494,7 +494,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_umin_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -504,8 +504,8 @@ entry:
 ; SI: buffer_atomic_umin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
 define void @atomic_umin_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -515,8 +515,8 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_umin_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -544,7 +544,7 @@ entry:
 ; SI: buffer_atomic_umin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
 define void @atomic_umin_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile umin i32 addrspace(1)* %ptr, i32 %in seq_cst
   ret void
 }
@@ -554,7 +554,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_umin_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile umin i32 addrspace(1)* %ptr, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -564,7 +564,7 @@ entry:
 ; SI: buffer_atomic_or v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
 define void @atomic_or_i32_offset(i32 addrspace(1)* %out, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -574,7 +574,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_or_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -584,8 +584,8 @@ entry:
 ; SI: buffer_atomic_or v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
 define void @atomic_or_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -595,8 +595,8 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_or_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -624,7 +624,7 @@ entry:
 ; SI: buffer_atomic_or v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
 define void @atomic_or_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile or i32 addrspace(1)* %ptr, i32 %in seq_cst
   ret void
 }
@@ -634,7 +634,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_or_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile or i32 addrspace(1)* %ptr, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -644,7 +644,7 @@ entry:
 ; SI: buffer_atomic_swap v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
 define void @atomic_xchg_i32_offset(i32 addrspace(1)* %out, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -654,7 +654,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_xchg_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -664,8 +664,8 @@ entry:
 ; SI: buffer_atomic_swap v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
 define void @atomic_xchg_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -675,8 +675,8 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_xchg_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -704,7 +704,7 @@ entry:
 ; SI: buffer_atomic_swap v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
 define void @atomic_xchg_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile xchg i32 addrspace(1)* %ptr, i32 %in seq_cst
   ret void
 }
@@ -714,7 +714,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_xchg_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile xchg i32 addrspace(1)* %ptr, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -724,7 +724,7 @@ entry:
 ; SI: buffer_atomic_xor v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
 define void @atomic_xor_i32_offset(i32 addrspace(1)* %out, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -734,7 +734,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_xor_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
 entry:
-  %gep = getelementptr i32 addrspace(1)* %out, i32 4
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
   %0  = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -744,8 +744,8 @@ entry:
 ; SI: buffer_atomic_xor v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
 define void @atomic_xor_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst
   ret void
 }
@@ -755,8 +755,8 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_xor_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
   %0  = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
@@ -784,7 +784,7 @@ entry:
 ; SI: buffer_atomic_xor v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
 define void @atomic_xor_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile xor i32 addrspace(1)* %ptr, i32 %in seq_cst
   ret void
 }
@@ -794,7 +794,7 @@ entry:
 ; SI: buffer_store_dword [[RET]]
 define void @atomic_xor_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
 entry:
-  %ptr = getelementptr i32 addrspace(1)* %out, i64 %index
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
   %0  = atomicrmw volatile xor i32 addrspace(1)* %ptr, i32 %in seq_cst
   store i32 %0, i32 addrspace(1)* %out2
   ret void
diff --git a/test/CodeGen/R600/gv-const-addrspace-fail.ll b/test/CodeGen/R600/gv-const-addrspace-fail.ll
index af0df413ca58..014b0a5482ab 100644
--- a/test/CodeGen/R600/gv-const-addrspace-fail.ll
+++ b/test/CodeGen/R600/gv-const-addrspace-fail.ll
@@ -9,8 +9,8 @@
 ; SI: buffer_store_byte
 ; SI: s_endpgm
 define void @test_i8( i32 %s, i8 addrspace(1)* %out) #3 {
-  %arrayidx = getelementptr inbounds [1 x i8] addrspace(2)* @a, i32 0, i32 %s
-  %1 = load i8 addrspace(2)* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds [1 x i8], [1 x i8] addrspace(2)* @a, i32 0, i32 %s
+  %1 = load i8, i8 addrspace(2)* %arrayidx, align 1
   store i8 %1, i8 addrspace(1)* %out
   ret void
 }
@@ -22,8 +22,8 @@ define void @test_i8( i32 %s, i8 addrspace(1)* %out) #3 {
 ; SI: buffer_store_short
 ; SI: s_endpgm
 define void @test_i16( i32 %s, i16 addrspace(1)* %out) #3 {
-  %arrayidx = getelementptr inbounds [1 x i16] addrspace(2)* @b, i32 0, i32 %s
-  %1 = load i16 addrspace(2)* %arrayidx, align 2
+  %arrayidx = getelementptr inbounds [1 x i16], [1 x i16] addrspace(2)* @b, i32 0, i32 %s
+  %1 = load i16, i16 addrspace(2)* %arrayidx, align 2
   store i16 %1, i16 addrspace(1)* %out
   ret void
 }
@@ -35,8 +35,8 @@ define void @test_i16( i32 %s, i16 addrspace(1)* %out) #3 {
 
 ; FUNC-LABEL: {{^}}struct_bar_gv_load:
 define void @struct_bar_gv_load(i8 addrspace(1)* %out, i32 %index) {
-  %gep = getelementptr inbounds [1 x %struct.bar] addrspace(2)* @struct_bar_gv, i32 0, i32 0, i32 1, i32 %index
-  %load = load i8 addrspace(2)* %gep, align 1
+  %gep = getelementptr inbounds [1 x %struct.bar], [1 x %struct.bar] addrspace(2)* @struct_bar_gv, i32 0, i32 0, i32 1, i32 %index
+  %load = load i8, i8 addrspace(2)* %gep, align 1
   store i8 %load, i8 addrspace(1)* %out, align 1
   ret void
 }
@@ -50,8 +50,8 @@ define void @struct_bar_gv_load(i8 addrspace(1)* %out, i32 %index) {
 
 ; FUNC-LABEL: {{^}}array_vector_gv_load:
 define void @array_vector_gv_load(<4 x i32> addrspace(1)* %out, i32 %index) {
-  %gep = getelementptr inbounds [4 x <4 x i32>] addrspace(2)* @array_vector_gv, i32 0, i32 %index
-  %load = load <4 x i32> addrspace(2)* %gep, align 16
+  %gep = getelementptr inbounds [4 x <4 x i32>], [4 x <4 x i32>] addrspace(2)* @array_vector_gv, i32 0, i32 %index
+  %load = load <4 x i32>, <4 x i32> addrspace(2)* %gep, align 16
   store <4 x i32> %load, <4 x i32> addrspace(1)* %out, align 16
   ret void
 }
diff --git a/test/CodeGen/R600/gv-const-addrspace.ll b/test/CodeGen/R600/gv-const-addrspace.ll
index c58e5846d98c..3c1fc6c98f74 100644
--- a/test/CodeGen/R600/gv-const-addrspace.ll
+++ b/test/CodeGen/R600/gv-const-addrspace.ll
@@ -1,5 +1,6 @@
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
 
 @b = internal addrspace(2) constant [1 x i16] [ i16 7 ], align 2
@@ -9,6 +10,7 @@
 ; FUNC-LABEL: {{^}}float:
 ; FIXME: We should be using s_load_dword here.
 ; SI: buffer_load_dword
+; VI: s_load_dword
 
 ; EG-DAG: MOV {{\** *}}T2.X
 ; EG-DAG: MOV {{\** *}}T3.X
@@ -19,8 +21,8 @@
 
 define void @float(float addrspace(1)* %out, i32 %index) {
 entry:
-  %0 = getelementptr inbounds [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index
-  %1 = load float addrspace(2)* %0
+  %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index
+  %1 = load float, float addrspace(2)* %0
   store float %1, float addrspace(1)* %out
   ret void
 }
@@ -31,6 +33,7 @@ entry:
 
 ; FIXME: We should be using s_load_dword here.
 ; SI: buffer_load_dword
+; VI: s_load_dword
 
 ; EG-DAG: MOV {{\** *}}T2.X
 ; EG-DAG: MOV {{\** *}}T3.X
@@ -41,8 +44,8 @@ entry:
 
 define void @i32(i32 addrspace(1)* %out, i32 %index) {
 entry:
-  %0 = getelementptr inbounds [5 x i32] addrspace(2)* @i32_gv, i32 0, i32 %index
-  %1 = load i32 addrspace(2)* %0
+  %0 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(2)* @i32_gv, i32 0, i32 %index
+  %1 = load i32, i32 addrspace(2)* %0
   store i32 %1, i32 addrspace(1)* %out
   ret void
 }
@@ -53,11 +56,11 @@ entry:
 @struct_foo_gv = internal unnamed_addr addrspace(2) constant [1 x %struct.foo] [ %struct.foo { float 16.0, [5 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4] } ]
 
 ; FUNC-LABEL: {{^}}struct_foo_gv_load:
-; SI: s_load_dword
+; GCN: s_load_dword
 
 define void @struct_foo_gv_load(i32 addrspace(1)* %out, i32 %index) {
-  %gep = getelementptr inbounds [1 x %struct.foo] addrspace(2)* @struct_foo_gv, i32 0, i32 0, i32 1, i32 %index
-  %load = load i32 addrspace(2)* %gep, align 4
+  %gep = getelementptr inbounds [1 x %struct.foo], [1 x %struct.foo] addrspace(2)* @struct_foo_gv, i32 0, i32 0, i32 1, i32 %index
+  %load = load i32, i32 addrspace(2)* %gep, align 4
   store i32 %load, i32 addrspace(1)* %out, align 4
   ret void
 }
@@ -70,9 +73,10 @@ define void @struct_foo_gv_load(i32 addrspace(1)* %out, i32 %index) {
 ; FUNC-LABEL: {{^}}array_v1_gv_load:
 ; FIXME: We should be using s_load_dword here.
 ; SI: buffer_load_dword
+; VI: s_load_dword
 define void @array_v1_gv_load(<1 x i32> addrspace(1)* %out, i32 %index) {
-  %gep = getelementptr inbounds [4 x <1 x i32>] addrspace(2)* @array_v1_gv, i32 0, i32 %index
-  %load = load <1 x i32> addrspace(2)* %gep, align 4
+  %gep = getelementptr inbounds [4 x <1 x i32>], [4 x <1 x i32>] addrspace(2)* @array_v1_gv, i32 0, i32 %index
+  %load = load <1 x i32>, <1 x i32> addrspace(2)* %gep, align 4
   store <1 x i32> %load, <1 x i32> addrspace(1)* %out, align 4
   ret void
 }
@@ -83,8 +87,8 @@ entry:
   br i1 %0, label %if, label %else
 
 if:
-  %1 = getelementptr inbounds [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index
-  %2 = load float addrspace(2)* %1
+  %1 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index
+  %2 = load float, float addrspace(2)* %1
   store float %2, float addrspace(1)* %out
   br label %endif
 
diff --git a/test/CodeGen/R600/half.ll b/test/CodeGen/R600/half.ll
index 35a41c5cd0b0..42ee788e88d5 100644
--- a/test/CodeGen/R600/half.ll
+++ b/test/CodeGen/R600/half.ll
@@ -5,7 +5,7 @@ define void @test_load_store(half addrspace(1)* %in, half addrspace(1)* %out) {
 ; CHECK-LABEL: {{^}}test_load_store:
 ; CHECK: buffer_load_ushort [[TMP:v[0-9]+]]
 ; CHECK: buffer_store_short [[TMP]]
-  %val = load half addrspace(1)* %in
+  %val = load half, half addrspace(1)* %in
   store half %val, half addrspace(1) * %out
   ret void
 }
@@ -14,7 +14,7 @@ define void @test_bitcast_from_half(half addrspace(1)* %in, i16 addrspace(1)* %o
 ; CHECK-LABEL: {{^}}test_bitcast_from_half:
 ; CHECK: buffer_load_ushort [[TMP:v[0-9]+]]
 ; CHECK: buffer_store_short [[TMP]]
-  %val = load half addrspace(1) * %in
+  %val = load half, half addrspace(1) * %in
   %val_int = bitcast half %val to i16
   store i16 %val_int, i16 addrspace(1)* %out
   ret void
@@ -24,7 +24,7 @@ define void @test_bitcast_to_half(half addrspace(1)* %out, i16 addrspace(1)* %in
 ; CHECK-LABEL: {{^}}test_bitcast_to_half:
 ; CHECK: buffer_load_ushort [[TMP:v[0-9]+]]
 ; CHECK: buffer_store_short [[TMP]]
-  %val = load i16 addrspace(1)* %in
+  %val = load i16, i16 addrspace(1)* %in
   %val_fp = bitcast i16 %val to half
   store half %val_fp, half addrspace(1)* %out
   ret void
@@ -34,7 +34,7 @@ define void @test_extend32(half addrspace(1)* %in, float addrspace(1)* %out) {
 ; CHECK-LABEL: {{^}}test_extend32:
 ; CHECK: v_cvt_f32_f16_e32
 
-  %val16 = load half addrspace(1)* %in
+  %val16 = load half, half addrspace(1)* %in
   %val32 = fpext half %val16 to float
   store float %val32, float addrspace(1)* %out
   ret void
@@ -45,7 +45,7 @@ define void @test_extend64(half addrspace(1)* %in, double addrspace(1)* %out) {
 ; CHECK: v_cvt_f32_f16_e32
 ; CHECK: v_cvt_f64_f32_e32
 
-  %val16 = load half addrspace(1)* %in
+  %val16 = load half, half addrspace(1)* %in
   %val64 = fpext half %val16 to double
   store double %val64, double addrspace(1)* %out
   ret void
@@ -55,7 +55,7 @@ define void @test_trunc32(float addrspace(1)* %in, half addrspace(1)* %out) {
 ; CHECK-LABEL: {{^}}test_trunc32:
 ; CHECK: v_cvt_f16_f32_e32
 
-  %val32 = load float addrspace(1)* %in
+  %val32 = load float, float addrspace(1)* %in
   %val16 = fptrunc float %val32 to half
   store half %val16, half addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/hsa.ll b/test/CodeGen/R600/hsa.ll
index 5ce3beaa16c0..f9113399afe8 100644
--- a/test/CodeGen/R600/hsa.ll
+++ b/test/CodeGen/R600/hsa.ll
@@ -1,8 +1,8 @@
-; RUN: llc < %s -mtriple=r600--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA %s
 
-; HSA: {{^}}simple:
 ; HSA: .section        .hsa.version
 ; HSA-NEXT: .ascii  "HSA Code Unit:0.0:AMD:0.1:GFX8.1:0"
+; HSA: {{^}}simple:
 ; Make sure we are setting the ATC bit:
 ; HSA: s_mov_b32 s[[HI:[0-9]]], 0x100f000
 ; HSA: buffer_store_dword v{{[0-9]+}}, s[0:[[HI]]], 0
diff --git a/test/CodeGen/R600/i1-copy-phi.ll b/test/CodeGen/R600/i1-copy-phi.ll
index 430466e9f80e..105cd06b330a 100644
--- a/test/CodeGen/R600/i1-copy-phi.ll
+++ b/test/CodeGen/R600/i1-copy-phi.ll
@@ -6,7 +6,7 @@
 ; SI: s_and_saveexec_b64
 ; SI: s_xor_b64
 ; SI: v_mov_b32_e32 [[REG]], -1{{$}}
-; SI: v_cmp_ne_i32_e64 {{s\[[0-9]+:[0-9]+\]}}, [[REG]], 0
+; SI: v_cmp_ne_i32_e32 vcc, 0, [[REG]]
 ; SI: s_and_saveexec_b64
 ; SI: s_xor_b64
 ; SI: s_endpgm
diff --git a/test/CodeGen/R600/i8-to-double-to-float.ll b/test/CodeGen/R600/i8-to-double-to-float.ll
index 604746627666..c218e1918bb0 100644
--- a/test/CodeGen/R600/i8-to-double-to-float.ll
+++ b/test/CodeGen/R600/i8-to-double-to-float.ll
@@ -3,7 +3,7 @@
 ;CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
 define void @test(float addrspace(1)* %out, i8 addrspace(1)* %in) {
-  %1 = load i8 addrspace(1)* %in
+  %1 = load i8, i8 addrspace(1)* %in
   %2 = uitofp i8 %1 to double
   %3 = fptrunc double %2 to float
   store float %3, float addrspace(1)* %out
diff --git a/test/CodeGen/R600/icmp-select-sete-reverse-args.ll b/test/CodeGen/R600/icmp-select-sete-reverse-args.ll
index 71705a64f50e..60e59a5a5286 100644
--- a/test/CodeGen/R600/icmp-select-sete-reverse-args.ll
+++ b/test/CodeGen/R600/icmp-select-sete-reverse-args.ll
@@ -8,9 +8,9 @@
 
 define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 entry:
-  %0 = load i32 addrspace(1)* %in
-  %arrayidx1 = getelementptr inbounds i32 addrspace(1)* %in, i32 1
-  %1 = load i32 addrspace(1)* %arrayidx1
+  %0 = load i32, i32 addrspace(1)* %in
+  %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
+  %1 = load i32, i32 addrspace(1)* %arrayidx1
   %cmp = icmp eq i32 %0, %1
   %value = select i1 %cmp, i32 0, i32 -1
   store i32 %value, i32 addrspace(1)* %out
diff --git a/test/CodeGen/R600/imm.ll b/test/CodeGen/R600/imm.ll
index 6e4fa3cc60cb..8917cd6dba33 100644
--- a/test/CodeGen/R600/imm.ll
+++ b/test/CodeGen/R600/imm.ll
@@ -1,4 +1,5 @@
-; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=CHECK %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=CHECK %s
 
 ; Use a 64-bit value with lo bits that can be represented as an inline constant
 ; CHECK-LABEL: {{^}}i64_imm_inline_lo:
@@ -22,81 +23,100 @@ entry:
   ret void
 }
 
-; CHECK-LABEL: {{^}}store_inline_imm_0.0_f32
-; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
+; CHECK-LABEL: {{^}}store_imm_neg_0.0_i64:
+; CHECK-DAG: s_mov_b32 s[[HI_SREG:[0-9]+]], 0x80000000
+; CHECK-DAG: s_mov_b32 s[[LO_SREG:[0-9]+]], 0{{$}}
+; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]]
+; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]]
+; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
+define void @store_imm_neg_0.0_i64(i64 addrspace(1) *%out) {
+  store i64 -9223372036854775808, i64 addrspace(1) *%out
+  ret void
+}
+
+; CHECK-LABEL: {{^}}store_inline_imm_neg_0.0_i32:
+; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
 ; CHECK-NEXT: buffer_store_dword [[REG]]
+define void @store_inline_imm_neg_0.0_i32(i32 addrspace(1)* %out) {
+  store i32 -2147483648, i32 addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: {{^}}store_inline_imm_0.0_f32:
+; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
+; CHECK: buffer_store_dword [[REG]]
 define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) {
   store float 0.0, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}store_imm_neg_0.0_f32
+; CHECK-LABEL: {{^}}store_imm_neg_0.0_f32:
 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @store_imm_neg_0.0_f32(float addrspace(1)* %out) {
   store float -0.0, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}store_inline_imm_0.5_f32
+; CHECK-LABEL: {{^}}store_inline_imm_0.5_f32:
 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) {
   store float 0.5, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f32
+; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f32:
 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) {
   store float -0.5, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}store_inline_imm_1.0_f32
+; CHECK-LABEL: {{^}}store_inline_imm_1.0_f32:
 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) {
   store float 1.0, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f32
+; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f32:
 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -1.0{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) {
   store float -1.0, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}store_inline_imm_2.0_f32
+; CHECK-LABEL: {{^}}store_inline_imm_2.0_f32:
 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) {
   store float 2.0, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f32
+; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f32:
 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -2.0{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) {
   store float -2.0, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}store_inline_imm_4.0_f32
+; CHECK-LABEL: {{^}}store_inline_imm_4.0_f32:
 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 4.0{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) {
   store float 4.0, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f32
+; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f32:
 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -4.0{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) {
   store float -4.0, float addrspace(1)* %out
   ret void
@@ -104,288 +124,298 @@ define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) {
 
 ; CHECK-LABEL: {{^}}store_literal_imm_f32:
 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x45800000
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @store_literal_imm_f32(float addrspace(1)* %out) {
   store float 4096.0, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_0.0_f32
+; CHECK-LABEL: {{^}}add_inline_imm_0.0_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0, [[VAL]]{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, 0.0
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_0.5_f32
+; CHECK-LABEL: {{^}}add_inline_imm_0.5_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, 0.5
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f32
+; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, -0.5
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_1.0_f32
+; CHECK-LABEL: {{^}}add_inline_imm_1.0_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, 1.0
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f32
+; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, -1.0
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_2.0_f32
+; CHECK-LABEL: {{^}}add_inline_imm_2.0_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, [[VAL]]{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, 2.0
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f32
+; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2.0, [[VAL]]{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, -2.0
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_4.0_f32
+; CHECK-LABEL: {{^}}add_inline_imm_4.0_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 4.0, [[VAL]]{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, 4.0
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f32
+; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -4.0, [[VAL]]{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, -4.0
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: @commute_add_inline_imm_0.5_f32
+; CHECK-LABEL: {{^}}commute_add_inline_imm_0.5_f32:
 ; CHECK: buffer_load_dword [[VAL:v[0-9]+]]
 ; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0.5, [[VAL]]
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @commute_add_inline_imm_0.5_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
-  %x = load float addrspace(1)* %in
+  %x = load float, float addrspace(1)* %in
   %y = fadd float %x, 0.5
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: @commute_add_literal_f32
+; CHECK-LABEL: {{^}}commute_add_literal_f32:
 ; CHECK: buffer_load_dword [[VAL:v[0-9]+]]
 ; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0x44800000, [[VAL]]
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @commute_add_literal_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
-  %x = load float addrspace(1)* %in
+  %x = load float, float addrspace(1)* %in
   %y = fadd float %x, 1024.0
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_1_f32
+; CHECK-LABEL: {{^}}add_inline_imm_1_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1, [[VAL]]{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_1_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, 0x36a0000000000000
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_2_f32
+; CHECK-LABEL: {{^}}add_inline_imm_2_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2, [[VAL]]{{$}}
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_2_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, 0x36b0000000000000
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_16_f32
+; CHECK-LABEL: {{^}}add_inline_imm_16_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 16, [[VAL]]
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_16_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, 0x36e0000000000000
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f32
+; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1, [[VAL]]
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_neg_1_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, 0xffffffffe0000000
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f32
+; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2, [[VAL]]
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_neg_2_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, 0xffffffffc0000000
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f32
+; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -16, [[VAL]]
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_neg_16_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, 0xfffffffe00000000
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_63_f32
+; CHECK-LABEL: {{^}}add_inline_imm_63_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 63, [[VAL]]
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_63_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, 0x36ff800000000000
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_64_f32
+; CHECK-LABEL: {{^}}add_inline_imm_64_f32:
 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 64, [[VAL]]
-; CHECK-NEXT: buffer_store_dword [[REG]]
+; CHECK: buffer_store_dword [[REG]]
 define void @add_inline_imm_64_f32(float addrspace(1)* %out, float %x) {
   %y = fadd float %x, 0x3700000000000000
   store float %y, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_0.0_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+
+; CHECK-LABEL: {{^}}add_inline_imm_0.0_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_0.0_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 0.0
   store double %y, double addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_0.5_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_0.5_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0.5, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_0.5_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 0.5
   store double %y, double addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -0.5, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_neg_0.5_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, -0.5
   store double %y, double addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_1.0_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_1.0_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1.0, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_1.0_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 1.0
   store double %y, double addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1.0, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_neg_1.0_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, -1.0
   store double %y, double addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_2.0_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_2.0_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2.0, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_2.0_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 2.0
   store double %y, double addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2.0, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_neg_2.0_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, -2.0
   store double %y, double addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_4.0_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_4.0_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 4.0, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_4.0_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 4.0
   store double %y, double addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -4.0, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_neg_4.0_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, -4.0
   store double %y, double addrspace(1)* %out
@@ -393,80 +423,88 @@ define void @add_inline_imm_neg_4.0_f64(double addrspace(1)* %out, double %x) {
 }
 
 
-; CHECK-LABEL: {{^}}add_inline_imm_1_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_1_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_1_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 0x0000000000000001
   store double %y, double addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_2_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_2_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_2_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 0x0000000000000002
   store double %y, double addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_16_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_16_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 16, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_16_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 0x0000000000000010
   store double %y, double addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_neg_1_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 0xffffffffffffffff
   store double %y, double addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_neg_2_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 0xfffffffffffffffe
   store double %y, double addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -16, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_neg_16_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 0xfffffffffffffff0
   store double %y, double addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_63_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_63_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 63, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_63_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 0x000000000000003F
   store double %y, double addrspace(1)* %out
   ret void
 }
 
-; CHECK-LABEL: {{^}}add_inline_imm_64_f64
-; CHECK: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; CHECK-LABEL: {{^}}add_inline_imm_64_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 64, [[VAL]]
-; CHECK-NEXT: buffer_store_dwordx2 [[REG]]
+; CHECK: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_64_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 0x0000000000000040
   store double %y, double addrspace(1)* %out
@@ -474,7 +512,7 @@ define void @add_inline_imm_64_f64(double addrspace(1)* %out, double %x) {
 }
 
 
-; CHECK-LABEL: {{^}}store_inline_imm_0.0_f64
+; CHECK-LABEL: {{^}}store_inline_imm_0.0_f64:
 ; CHECK: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0
 ; CHECK: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0
 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
@@ -482,3 +520,98 @@ define void @store_inline_imm_0.0_f64(double addrspace(1)* %out) {
   store double 0.0, double addrspace(1)* %out
   ret void
 }
+
+
+; CHECK-LABEL: {{^}}store_literal_imm_neg_0.0_f64:
+; CHECK-DAG: s_mov_b32 s[[HI_SREG:[0-9]+]], 0x80000000
+; CHECK-DAG: s_mov_b32 s[[LO_SREG:[0-9]+]], 0{{$}}
+; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]]
+; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]]
+; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
+define void @store_literal_imm_neg_0.0_f64(double addrspace(1)* %out) {
+  store double -0.0, double addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: {{^}}store_inline_imm_0.5_f64:
+; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
+; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3fe00000
+; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
+define void @store_inline_imm_0.5_f64(double addrspace(1)* %out) {
+  store double 0.5, double addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f64:
+; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
+; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbfe00000
+; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
+define void @store_inline_imm_m_0.5_f64(double addrspace(1)* %out) {
+  store double -0.5, double addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: {{^}}store_inline_imm_1.0_f64:
+; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
+; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3ff00000
+; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
+define void @store_inline_imm_1.0_f64(double addrspace(1)* %out) {
+  store double 1.0, double addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f64:
+; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
+; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbff00000
+; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
+define void @store_inline_imm_m_1.0_f64(double addrspace(1)* %out) {
+  store double -1.0, double addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: {{^}}store_inline_imm_2.0_f64:
+; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
+; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 2.0
+; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
+define void @store_inline_imm_2.0_f64(double addrspace(1)* %out) {
+  store double 2.0, double addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f64:
+; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
+; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], -2.0
+; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
+define void @store_inline_imm_m_2.0_f64(double addrspace(1)* %out) {
+  store double -2.0, double addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: {{^}}store_inline_imm_4.0_f64:
+; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
+; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x40100000
+; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
+define void @store_inline_imm_4.0_f64(double addrspace(1)* %out) {
+  store double 4.0, double addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f64:
+; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
+; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xc0100000
+; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
+define void @store_inline_imm_m_4.0_f64(double addrspace(1)* %out) {
+  store double -4.0, double addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: {{^}}store_literal_imm_f64:
+; CHECK-DAG: s_mov_b32 s[[HI_SREG:[0-9]+]], 0x40b00000
+; CHECK-DAG: s_mov_b32 s[[LO_SREG:[0-9]+]], 0{{$}}
+; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]]
+; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]]
+; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
+define void @store_literal_imm_f64(double addrspace(1)* %out) {
+  store double 4096.0, double addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/indirect-private-64.ll b/test/CodeGen/R600/indirect-private-64.ll
index cb06d609da49..d63e1b6c5212 100644
--- a/test/CodeGen/R600/indirect-private-64.ll
+++ b/test/CodeGen/R600/indirect-private-64.ll
@@ -14,12 +14,12 @@ declare void @llvm.AMDGPU.barrier.local() noduplicate nounwind
 ; SI-PROMOTE: ds_write_b64
 ; SI-PROMOTE: ds_read_b64
 define void @private_access_f64_alloca(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in, i32 %b) nounwind {
-  %val = load double addrspace(1)* %in, align 8
+  %val = load double, double addrspace(1)* %in, align 8
   %array = alloca double, i32 16, align 8
-  %ptr = getelementptr double* %array, i32 %b
+  %ptr = getelementptr double, double* %array, i32 %b
   store double %val, double* %ptr, align 8
   call void @llvm.AMDGPU.barrier.local() noduplicate nounwind
-  %result = load double* %ptr, align 8
+  %result = load double, double* %ptr, align 8
   store double %result, double addrspace(1)* %out, align 8
   ret void
 }
@@ -38,12 +38,12 @@ define void @private_access_f64_alloca(double addrspace(1)* noalias %out, double
 ; SI-PROMOTE: ds_read_b32
 ; SI-PROMOTE: ds_read_b32
 define void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out, <2 x double> addrspace(1)* noalias %in, i32 %b) nounwind {
-  %val = load <2 x double> addrspace(1)* %in, align 16
+  %val = load <2 x double>, <2 x double> addrspace(1)* %in, align 16
   %array = alloca <2 x double>, i32 16, align 16
-  %ptr = getelementptr <2 x double>* %array, i32 %b
+  %ptr = getelementptr <2 x double>, <2 x double>* %array, i32 %b
   store <2 x double> %val, <2 x double>* %ptr, align 16
   call void @llvm.AMDGPU.barrier.local() noduplicate nounwind
-  %result = load <2 x double>* %ptr, align 16
+  %result = load <2 x double>, <2 x double>* %ptr, align 16
   store <2 x double> %result, <2 x double> addrspace(1)* %out, align 16
   ret void
 }
@@ -56,12 +56,12 @@ define void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out
 ; SI-PROMOTE: ds_write_b64
 ; SI-PROMOTE: ds_read_b64
 define void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i32 %b) nounwind {
-  %val = load i64 addrspace(1)* %in, align 8
+  %val = load i64, i64 addrspace(1)* %in, align 8
   %array = alloca i64, i32 16, align 8
-  %ptr = getelementptr i64* %array, i32 %b
+  %ptr = getelementptr i64, i64* %array, i32 %b
   store i64 %val, i64* %ptr, align 8
   call void @llvm.AMDGPU.barrier.local() noduplicate nounwind
-  %result = load i64* %ptr, align 8
+  %result = load i64, i64* %ptr, align 8
   store i64 %result, i64 addrspace(1)* %out, align 8
   ret void
 }
@@ -80,12 +80,12 @@ define void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrs
 ; SI-PROMOTE: ds_read_b32
 ; SI-PROMOTE: ds_read_b32
 define void @private_access_v2i64_alloca(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in, i32 %b) nounwind {
-  %val = load <2 x i64> addrspace(1)* %in, align 16
+  %val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
   %array = alloca <2 x i64>, i32 16, align 16
-  %ptr = getelementptr <2 x i64>* %array, i32 %b
+  %ptr = getelementptr <2 x i64>, <2 x i64>* %array, i32 %b
   store <2 x i64> %val, <2 x i64>* %ptr, align 16
   call void @llvm.AMDGPU.barrier.local() noduplicate nounwind
-  %result = load <2 x i64>* %ptr, align 16
+  %result = load <2 x i64>, <2 x i64>* %ptr, align 16
   store <2 x i64> %result, <2 x i64> addrspace(1)* %out, align 16
   ret void
 }
diff --git a/test/CodeGen/R600/inline-asm.ll b/test/CodeGen/R600/inline-asm.ll
index 37e4486db380..efc2292de3a5 100644
--- a/test/CodeGen/R600/inline-asm.ll
+++ b/test/CodeGen/R600/inline-asm.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -march=r600 -mcpu=tonga -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
 
 ; CHECK: {{^}}inline_asm:
 ; CHECK: s_endpgm
diff --git a/test/CodeGen/R600/insert_vector_elt.ll b/test/CodeGen/R600/insert_vector_elt.ll
index 64afddcca21d..6de3d408c486 100644
--- a/test/CodeGen/R600/insert_vector_elt.ll
+++ b/test/CodeGen/R600/insert_vector_elt.ll
@@ -185,13 +185,13 @@ entry:
   br i1 %1, label %if, label %else
 
 if:
-  %2 = load i32 addrspace(1)* %in
+  %2 = load i32, i32 addrspace(1)* %in
   %3 = insertelement <2 x i32> %0, i32 %2, i32 1
   br label %endif
 
 else:
-  %4 = getelementptr i32 addrspace(1)* %in, i32 1
-  %5 = load i32 addrspace(1)* %4
+  %4 = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %5 = load i32, i32 addrspace(1)* %4
   %6 = insertelement <2 x i32> %0, i32 %5, i32 1
   br label %endif
 
diff --git a/test/CodeGen/R600/jump-address.ll b/test/CodeGen/R600/jump-address.ll
index a1cd3882443a..f55912e37401 100644
--- a/test/CodeGen/R600/jump-address.ll
+++ b/test/CodeGen/R600/jump-address.ll
@@ -6,7 +6,7 @@
 
 define void @main() #0 {
 main_body:
-  %0 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %0 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %1 = extractelement <4 x float> %0, i32 0
   %2 = bitcast float %1 to i32
   %3 = icmp eq i32 %2, 0
@@ -17,7 +17,7 @@ main_body:
   br i1 %7, label %ENDIF, label %ELSE
 
 ELSE:                                             ; preds = %main_body
-  %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %9 = extractelement <4 x float> %8, i32 0
   %10 = bitcast float %9 to i32
   %11 = icmp eq i32 %10, 1
@@ -40,7 +40,7 @@ ENDIF:                                            ; preds = %IF13, %ELSE, %main_
   ret void
 
 IF13:                                             ; preds = %ELSE
-  %20 = load <4 x float> addrspace(8)* null
+  %20 = load <4 x float>, <4 x float> addrspace(8)* null
   %21 = extractelement <4 x float> %20, i32 0
   %22 = fsub float -0.000000e+00, %21
   %23 = fadd float 0xFFF8000000000000, %22
diff --git a/test/CodeGen/R600/kcache-fold.ll b/test/CodeGen/R600/kcache-fold.ll
index 27840b2e1609..7e2291cfdc35 100644
--- a/test/CodeGen/R600/kcache-fold.ll
+++ b/test/CodeGen/R600/kcache-fold.ll
@@ -4,35 +4,35 @@
 ; CHECK: MOV * T{{[0-9]+\.[XYZW], KC0}}
 define void @main1() {
 main_body:
-  %0 = load <4 x float> addrspace(8)* null
+  %0 = load <4 x float>, <4 x float> addrspace(8)* null
   %1 = extractelement <4 x float> %0, i32 0
-  %2 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %3 = extractelement <4 x float> %2, i32 0
-  %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %5 = extractelement <4 x float> %4, i32 0
   %6 = fcmp ogt float %1, 0.000000e+00
   %7 = select i1 %6, float %3, float %5
-  %8 = load <4 x float> addrspace(8)* null
+  %8 = load <4 x float>, <4 x float> addrspace(8)* null
   %9 = extractelement <4 x float> %8, i32 1
-  %10 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %11 = extractelement <4 x float> %10, i32 1
-  %12 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %12 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %13 = extractelement <4 x float> %12, i32 1
   %14 = fcmp ogt float %9, 0.000000e+00
   %15 = select i1 %14, float %11, float %13
-  %16 = load <4 x float> addrspace(8)* null
+  %16 = load <4 x float>, <4 x float> addrspace(8)* null
   %17 = extractelement <4 x float> %16, i32 2
-  %18 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %18 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %19 = extractelement <4 x float> %18, i32 2
-  %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %20 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %21 = extractelement <4 x float> %20, i32 2
   %22 = fcmp ogt float %17, 0.000000e+00
   %23 = select i1 %22, float %19, float %21
-  %24 = load <4 x float> addrspace(8)* null
+  %24 = load <4 x float>, <4 x float> addrspace(8)* null
   %25 = extractelement <4 x float> %24, i32 3
-  %26 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %26 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %27 = extractelement <4 x float> %26, i32 3
-  %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %28 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %29 = extractelement <4 x float> %28, i32 3
   %30 = fcmp ogt float %25, 0.000000e+00
   %31 = select i1 %30, float %27, float %29
@@ -52,35 +52,35 @@ main_body:
 ; CHECK-NOT: MOV
 define void @main2() {
 main_body:
-  %0 = load <4 x float> addrspace(8)* null
+  %0 = load <4 x float>, <4 x float> addrspace(8)* null
   %1 = extractelement <4 x float> %0, i32 0
-  %2 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %3 = extractelement <4 x float> %2, i32 0
-  %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %5 = extractelement <4 x float> %4, i32 1
   %6 = fcmp ogt float %1, 0.000000e+00
   %7 = select i1 %6, float %3, float %5
-  %8 = load <4 x float> addrspace(8)* null
+  %8 = load <4 x float>, <4 x float> addrspace(8)* null
   %9 = extractelement <4 x float> %8, i32 1
-  %10 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %11 = extractelement <4 x float> %10, i32 0
-  %12 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %12 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %13 = extractelement <4 x float> %12, i32 1
   %14 = fcmp ogt float %9, 0.000000e+00
   %15 = select i1 %14, float %11, float %13
-  %16 = load <4 x float> addrspace(8)* null
+  %16 = load <4 x float>, <4 x float> addrspace(8)* null
   %17 = extractelement <4 x float> %16, i32 2
-  %18 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %18 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %19 = extractelement <4 x float> %18, i32 3
-  %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %20 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %21 = extractelement <4 x float> %20, i32 2
   %22 = fcmp ogt float %17, 0.000000e+00
   %23 = select i1 %22, float %19, float %21
-  %24 = load <4 x float> addrspace(8)* null
+  %24 = load <4 x float>, <4 x float> addrspace(8)* null
   %25 = extractelement <4 x float> %24, i32 3
-  %26 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %26 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %27 = extractelement <4 x float> %26, i32 3
-  %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %28 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %29 = extractelement <4 x float> %28, i32 2
   %30 = fcmp ogt float %25, 0.000000e+00
   %31 = select i1 %30, float %27, float %29
diff --git a/test/CodeGen/R600/kernel-args.ll b/test/CodeGen/R600/kernel-args.ll
index 42d289d4ef23..1dd7c2cb7995 100644
--- a/test/CodeGen/R600/kernel-args.ll
+++ b/test/CodeGen/R600/kernel-args.ll
@@ -1,11 +1,11 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG
-; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI
+; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC
+; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
+; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC
 
-; EG-LABEL: {{^}}i8_arg:
+; FUNC-LABEL: {{^}}i8_arg:
 ; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
-; SI-LABEL: {{^}}i8_arg:
-; SI: buffer_load_ubyte
+; GCN: buffer_load_ubyte
 
 define void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind {
 entry:
@@ -14,10 +14,10 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}i8_zext_arg:
+; FUNC-LABEL: {{^}}i8_zext_arg:
 ; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
-; SI-LABEL: {{^}}i8_zext_arg:
 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
+; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
 
 define void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind {
 entry:
@@ -26,10 +26,10 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}i8_sext_arg:
+; FUNC-LABEL: {{^}}i8_sext_arg:
 ; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
-; SI-LABEL: {{^}}i8_sext_arg:
 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
+; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
 
 define void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind {
 entry:
@@ -38,10 +38,9 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}i16_arg:
+; FUNC-LABEL: {{^}}i16_arg:
 ; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
-; SI-LABEL: {{^}}i16_arg:
-; SI: buffer_load_ushort
+; GCN: buffer_load_ushort
 
 define void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind {
 entry:
@@ -50,10 +49,10 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}i16_zext_arg:
+; FUNC-LABEL: {{^}}i16_zext_arg:
 ; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
-; SI-LABEL: {{^}}i16_zext_arg:
 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
+; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
 
 define void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind {
 entry:
@@ -62,10 +61,10 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}i16_sext_arg:
+; FUNC-LABEL: {{^}}i16_sext_arg:
 ; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
-; SI-LABEL: {{^}}i16_sext_arg:
 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
+; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
 
 define void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind {
 entry:
@@ -74,176 +73,170 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}i32_arg:
+; FUNC-LABEL: {{^}}i32_arg:
 ; EG: T{{[0-9]\.[XYZW]}}, KC0[2].Z
-; SI-LABEL: {{^}}i32_arg:
-; s_load_dword s{{[0-9]}}, s[0:1], 0xb
+; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
+; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
 define void @i32_arg(i32 addrspace(1)* nocapture %out, i32 %in) nounwind {
 entry:
   store i32 %in, i32 addrspace(1)* %out, align 4
   ret void
 }
 
-; EG-LABEL: {{^}}f32_arg:
+; FUNC-LABEL: {{^}}f32_arg:
 ; EG: T{{[0-9]\.[XYZW]}}, KC0[2].Z
-; SI-LABEL: {{^}}f32_arg:
-; s_load_dword s{{[0-9]}}, s[0:1], 0xb
+; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
+; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
 define void @f32_arg(float addrspace(1)* nocapture %out, float %in) nounwind {
 entry:
   store float %in, float addrspace(1)* %out, align 4
   ret void
 }
 
-; EG-LABEL: {{^}}v2i8_arg:
+; FUNC-LABEL: {{^}}v2i8_arg:
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
-; SI-LABEL: {{^}}v2i8_arg:
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
 define void @v2i8_arg(<2 x i8> addrspace(1)* %out, <2 x i8> %in) {
 entry:
   store <2 x i8> %in, <2 x i8> addrspace(1)* %out
   ret void
 }
 
-; EG-LABEL: {{^}}v2i16_arg:
+; FUNC-LABEL: {{^}}v2i16_arg:
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
-; SI-LABEL: {{^}}v2i16_arg:
-; SI-DAG: buffer_load_ushort
-; SI-DAG: buffer_load_ushort
+; GCN-DAG: buffer_load_ushort
+; GCN-DAG: buffer_load_ushort
 define void @v2i16_arg(<2 x i16> addrspace(1)* %out, <2 x i16> %in) {
 entry:
   store <2 x i16> %in, <2 x i16> addrspace(1)* %out
   ret void
 }
 
-; EG-LABEL: {{^}}v2i32_arg:
+; FUNC-LABEL: {{^}}v2i32_arg:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
-; SI-LABEL: {{^}}v2i32_arg:
 ; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb
+; VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c
 define void @v2i32_arg(<2 x i32> addrspace(1)* nocapture %out, <2 x i32> %in) nounwind {
 entry:
   store <2 x i32> %in, <2 x i32> addrspace(1)* %out, align 4
   ret void
 }
 
-; EG-LABEL: {{^}}v2f32_arg:
+; FUNC-LABEL: {{^}}v2f32_arg:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
-; SI-LABEL: {{^}}v2f32_arg:
 ; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb
+; VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c
 define void @v2f32_arg(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) nounwind {
 entry:
   store <2 x float> %in, <2 x float> addrspace(1)* %out, align 4
   ret void
 }
 
-; EG-LABEL: {{^}}v3i8_arg:
+; FUNC-LABEL: {{^}}v3i8_arg:
 ; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40
 ; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41
 ; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42
-; SI-LABEL: {{^}}v3i8_arg:
 define void @v3i8_arg(<3 x i8> addrspace(1)* nocapture %out, <3 x i8> %in) nounwind {
 entry:
   store <3 x i8> %in, <3 x i8> addrspace(1)* %out, align 4
   ret void
 }
 
-; EG-LABEL: {{^}}v3i16_arg:
+; FUNC-LABEL: {{^}}v3i16_arg:
 ; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44
 ; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46
 ; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48
-; SI-LABEL: {{^}}v3i16_arg:
 define void @v3i16_arg(<3 x i16> addrspace(1)* nocapture %out, <3 x i16> %in) nounwind {
 entry:
   store <3 x i16> %in, <3 x i16> addrspace(1)* %out, align 4
   ret void
 }
-; EG-LABEL: {{^}}v3i32_arg:
+; FUNC-LABEL: {{^}}v3i32_arg:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
-; SI-LABEL: {{^}}v3i32_arg:
 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
+; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
 define void @v3i32_arg(<3 x i32> addrspace(1)* nocapture %out, <3 x i32> %in) nounwind {
 entry:
   store <3 x i32> %in, <3 x i32> addrspace(1)* %out, align 4
   ret void
 }
 
-; EG-LABEL: {{^}}v3f32_arg:
+; FUNC-LABEL: {{^}}v3f32_arg:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
-; SI-LABEL: {{^}}v3f32_arg:
 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
+; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
 define void @v3f32_arg(<3 x float> addrspace(1)* nocapture %out, <3 x float> %in) nounwind {
 entry:
   store <3 x float> %in, <3 x float> addrspace(1)* %out, align 4
   ret void
 }
 
-; EG-LABEL: {{^}}v4i8_arg:
+; FUNC-LABEL: {{^}}v4i8_arg:
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
-; SI-LABEL: {{^}}v4i8_arg:
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
 define void @v4i8_arg(<4 x i8> addrspace(1)* %out, <4 x i8> %in) {
 entry:
   store <4 x i8> %in, <4 x i8> addrspace(1)* %out
   ret void
 }
 
-; EG-LABEL: {{^}}v4i16_arg:
+; FUNC-LABEL: {{^}}v4i16_arg:
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
-; SI-LABEL: {{^}}v4i16_arg:
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
 define void @v4i16_arg(<4 x i16> addrspace(1)* %out, <4 x i16> %in) {
 entry:
   store <4 x i16> %in, <4 x i16> addrspace(1)* %out
   ret void
 }
 
-; EG-LABEL: {{^}}v4i32_arg:
+; FUNC-LABEL: {{^}}v4i32_arg:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
-; SI-LABEL: {{^}}v4i32_arg:
 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
+; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
 define void @v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> %in) nounwind {
 entry:
   store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4
   ret void
 }
 
-; EG-LABEL: {{^}}v4f32_arg:
+; FUNC-LABEL: {{^}}v4f32_arg:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
-; SI-LABEL: {{^}}v4f32_arg:
 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
+; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
 define void @v4f32_arg(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) nounwind {
 entry:
   store <4 x float> %in, <4 x float> addrspace(1)* %out, align 4
   ret void
 }
 
-; EG-LABEL: {{^}}v8i8_arg:
+; FUNC-LABEL: {{^}}v8i8_arg:
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
@@ -252,21 +245,20 @@ entry:
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
-; SI-LABEL: {{^}}v8i8_arg:
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
 define void @v8i8_arg(<8 x i8> addrspace(1)* %out, <8 x i8> %in) {
 entry:
   store <8 x i8> %in, <8 x i8> addrspace(1)* %out
   ret void
 }
 
-; EG-LABEL: {{^}}v8i16_arg:
+; FUNC-LABEL: {{^}}v8i16_arg:
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
@@ -275,22 +267,21 @@ entry:
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
-; SI-LABEL: {{^}}v8i16_arg:
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
 define void @v8i16_arg(<8 x i16> addrspace(1)* %out, <8 x i16> %in) {
 entry:
   store <8 x i16> %in, <8 x i16> addrspace(1)* %out
   ret void
 }
 
-; EG-LABEL: {{^}}v8i32_arg:
+; FUNC-LABEL: {{^}}v8i32_arg:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W
@@ -299,15 +290,15 @@ entry:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X
-; SI-LABEL: {{^}}v8i32_arg:
 ; SI: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11
+; VI: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x44
 define void @v8i32_arg(<8 x i32> addrspace(1)* nocapture %out, <8 x i32> %in) nounwind {
 entry:
   store <8 x i32> %in, <8 x i32> addrspace(1)* %out, align 4
   ret void
 }
 
-; EG-LABEL: {{^}}v8f32_arg:
+; FUNC-LABEL: {{^}}v8f32_arg:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W
@@ -316,7 +307,6 @@ entry:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X
-; SI-LABEL: {{^}}v8f32_arg:
 ; SI: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11
 define void @v8f32_arg(<8 x float> addrspace(1)* nocapture %out, <8 x float> %in) nounwind {
 entry:
@@ -324,7 +314,7 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}v16i8_arg:
+; FUNC-LABEL: {{^}}v16i8_arg:
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
@@ -341,30 +331,29 @@ entry:
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
-; SI-LABEL: {{^}}v16i8_arg:
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
 define void @v16i8_arg(<16 x i8> addrspace(1)* %out, <16 x i8> %in) {
 entry:
   store <16 x i8> %in, <16 x i8> addrspace(1)* %out
   ret void
 }
 
-; EG-LABEL: {{^}}v16i16_arg:
+; FUNC-LABEL: {{^}}v16i16_arg:
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
@@ -381,30 +370,29 @@ entry:
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
-; SI-LABEL: {{^}}v16i16_arg:
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
+; GCN: buffer_load_ushort
 define void @v16i16_arg(<16 x i16> addrspace(1)* %out, <16 x i16> %in) {
 entry:
   store <16 x i16> %in, <16 x i16> addrspace(1)* %out
   ret void
 }
 
-; EG-LABEL: {{^}}v16i32_arg:
+; FUNC-LABEL: {{^}}v16i32_arg:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W
@@ -421,15 +409,15 @@ entry:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
-; SI-LABEL: {{^}}v16i32_arg:
 ; SI: s_load_dwordx16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19
+; VI: s_load_dwordx16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x64
 define void @v16i32_arg(<16 x i32> addrspace(1)* nocapture %out, <16 x i32> %in) nounwind {
 entry:
   store <16 x i32> %in, <16 x i32> addrspace(1)* %out, align 4
   ret void
 }
 
-; EG-LABEL: {{^}}v16f32_arg:
+; FUNC-LABEL: {{^}}v16f32_arg:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W
@@ -446,8 +434,8 @@ entry:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
-; SI-LABEL: {{^}}v16f32_arg:
 ; SI: s_load_dwordx16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19
+; VI: s_load_dwordx16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x64
 define void @v16f32_arg(<16 x float> addrspace(1)* nocapture %out, <16 x float> %in) nounwind {
 entry:
   store <16 x float> %in, <16 x float> addrspace(1)* %out, align 4
@@ -455,18 +443,30 @@ entry:
 }
 
 ; FUNC-LABEL: {{^}}kernel_arg_i64:
-; SI: s_load_dwordx2
-; SI: s_load_dwordx2
-; SI: buffer_store_dwordx2
+; GCN: s_load_dwordx2
+; GCN: s_load_dwordx2
+; GCN: buffer_store_dwordx2
 define void @kernel_arg_i64(i64 addrspace(1)* %out, i64 %a) nounwind {
   store i64 %a, i64 addrspace(1)* %out, align 8
   ret void
 }
 
+; FUNC-LABEL: {{^}}f64_kernel_arg:
+; SI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x9
+; SI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0xb
+; VI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x24
+; VI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x2c
+; GCN: buffer_store_dwordx2
+define void @f64_kernel_arg(double addrspace(1)* %out, double  %in) {
+entry:
+  store double %in, double addrspace(1)* %out
+  ret void
+}
+
 ; XFUNC-LABEL: {{^}}kernel_arg_v1i64:
-; XSI: s_load_dwordx2
-; XSI: s_load_dwordx2
-; XSI: buffer_store_dwordx2
+; XGCN: s_load_dwordx2
+; XGCN: s_load_dwordx2
+; XGCN: buffer_store_dwordx2
 ; define void @kernel_arg_v1i64(<1 x i64> addrspace(1)* %out, <1 x i64> %a) nounwind {
 ;   store <1 x i64> %a, <1 x i64> addrspace(1)* %out, align 8
 ;   ret void
diff --git a/test/CodeGen/R600/large-alloca.ll b/test/CodeGen/R600/large-alloca.ll
index 788816cf723f..671833d1a33a 100644
--- a/test/CodeGen/R600/large-alloca.ll
+++ b/test/CodeGen/R600/large-alloca.ll
@@ -5,10 +5,10 @@
 
 define void @large_alloca(i32 addrspace(1)* %out, i32 %x, i32 %y) nounwind {
   %large = alloca [8192 x i32], align 4
-  %gep = getelementptr [8192 x i32]* %large, i32 0, i32 8191
+  %gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191
   store i32 %x, i32* %gep
-  %gep1 = getelementptr [8192 x i32]* %large, i32 0, i32 %y
-  %0 = load i32* %gep1
+  %gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y
+  %0 = load i32, i32* %gep1
   store i32 %0, i32 addrspace(1)* %out
   ret void
 }
diff --git a/test/CodeGen/R600/large-constant-initializer.ll b/test/CodeGen/R600/large-constant-initializer.ll
index c8671efbe6f9..9975b1b7f5cc 100644
--- a/test/CodeGen/R600/large-constant-initializer.ll
+++ b/test/CodeGen/R600/large-constant-initializer.ll
@@ -5,7 +5,7 @@
 @gv = external unnamed_addr addrspace(2) constant [239 x i32], align 4
 
 define void @opencv_cvtfloat_crash(i32 addrspace(1)* %out, i32 %x) nounwind {
-  %val = load i32 addrspace(2)* getelementptr ([239 x i32] addrspace(2)* @gv, i64 0, i64 239), align 4
+  %val = load i32, i32 addrspace(2)* getelementptr ([239 x i32], [239 x i32] addrspace(2)* @gv, i64 0, i64 239), align 4
   %mul12 = mul nsw i32 %val, 7
   br i1 undef, label %exit, label %bb
 
diff --git a/test/CodeGen/R600/lds-initializer.ll b/test/CodeGen/R600/lds-initializer.ll
index 7344eff2572f..bf8df63be9fd 100644
--- a/test/CodeGen/R600/lds-initializer.ll
+++ b/test/CodeGen/R600/lds-initializer.ll
@@ -6,8 +6,8 @@
 @lds = addrspace(3) global [8 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8]
 
 define void @load_init_lds_global(i32 addrspace(1)* %out, i1 %p) {
- %gep = getelementptr [8 x i32] addrspace(3)* @lds, i32 0, i32 10
-  %ld = load i32 addrspace(3)* %gep
+ %gep = getelementptr [8 x i32], [8 x i32] addrspace(3)* @lds, i32 0, i32 10
+  %ld = load i32, i32 addrspace(3)* %gep
   store i32 %ld, i32 addrspace(1)* %out
   ret void
 }
diff --git a/test/CodeGen/R600/lds-oqap-crash.ll b/test/CodeGen/R600/lds-oqap-crash.ll
index fbcd778de2c2..6ff6fc3d7afc 100644
--- a/test/CodeGen/R600/lds-oqap-crash.ll
+++ b/test/CodeGen/R600/lds-oqap-crash.ll
@@ -12,7 +12,7 @@
 ; CHECK: {{^}}lds_crash:
 define void @lds_crash(i32 addrspace(1)* %out, i32 addrspace(3)* %in, i32 %a, i32 %b, i32 %c) {
 entry:
-  %0 = load i32 addrspace(3)* %in
+  %0 = load i32, i32 addrspace(3)* %in
   ; This block needs to be > 115 ISA instructions to hit the bug,
   ; so we'll use udiv instructions.
   %div0 = udiv i32 %0, %b
diff --git a/test/CodeGen/R600/lds-output-queue.ll b/test/CodeGen/R600/lds-output-queue.ll
index cda75b0e0ccc..44ffc36af149 100644
--- a/test/CodeGen/R600/lds-output-queue.ll
+++ b/test/CodeGen/R600/lds-output-queue.ll
@@ -12,12 +12,12 @@
 
 define void @lds_input_queue(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %index) {
 entry:
-  %0 = getelementptr inbounds [2 x i32] addrspace(3)* @local_mem, i32 0, i32 %index
-  %1 = load i32 addrspace(3)* %0
+  %0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(3)* @local_mem, i32 0, i32 %index
+  %1 = load i32, i32 addrspace(3)* %0
   call void @llvm.AMDGPU.barrier.local()
 
   ; This will start a new clause for the vertex fetch
-  %2 = load i32 addrspace(1)* %in
+  %2 = load i32, i32 addrspace(1)* %in
   %3 = add i32 %1, %2
   store i32 %3, i32 addrspace(1)* %out
   ret void
@@ -40,9 +40,9 @@ declare void @llvm.AMDGPU.barrier.local()
 ; load from global memory which immediately follows a load from a global value that
 ; has been declared in the local memory space:
 ;
-;  %0 = getelementptr inbounds [2 x i32] addrspace(3)* @local_mem, i32 0, i32 %index
-;  %1 = load i32 addrspace(3)* %0
-;  %2 = load i32 addrspace(1)* %in
+;  %0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(3)* @local_mem, i32 0, i32 %index
+;  %1 = load i32, i32 addrspace(3)* %0
+;  %2 = load i32, i32 addrspace(1)* %in
 ;
 ; The instruction selection phase will generate ISA that looks like this:
 ; %OQAP = LDS_READ_RET
@@ -90,9 +90,9 @@ declare void @llvm.AMDGPU.barrier.local()
 ; CHECK: MOV * T{{[0-9]\.[XYZW]}}, OQAP
 define void @local_global_alias(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 entry:
-  %0 = getelementptr inbounds [2 x i32] addrspace(3)* @local_mem, i32 0, i32 0
-  %1 = load i32 addrspace(3)* %0
-  %2 = load i32 addrspace(1)* %in
+  %0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(3)* @local_mem, i32 0, i32 0
+  %1 = load i32, i32 addrspace(3)* %0
+  %2 = load i32, i32 addrspace(1)* %in
   %3 = add i32 %2, %1
   store i32 %3, i32 addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/lds-size.ll b/test/CodeGen/R600/lds-size.ll
index 5287723ce191..3e8328659fdb 100644
--- a/test/CodeGen/R600/lds-size.ll
+++ b/test/CodeGen/R600/lds-size.ll
@@ -3,9 +3,9 @@
 ; This test makes sure we do not double count global values when they are
 ; used in different basic blocks.
 
-; CHECK-LABEL: {{^}}test:
 ; CHECK: .long   166120
 ; CHECK-NEXT: .long   1
+; CHECK-LABEL: {{^}}test:
 @lds = internal unnamed_addr addrspace(3) global i32 undef, align 4
 
 define void @test(i32 addrspace(1)* %out, i32 %cond) {
diff --git a/test/CodeGen/R600/lds-zero-initializer.ll b/test/CodeGen/R600/lds-zero-initializer.ll
index 1fb6f52f29b9..fb51bc0e50c2 100644
--- a/test/CodeGen/R600/lds-zero-initializer.ll
+++ b/test/CodeGen/R600/lds-zero-initializer.ll
@@ -6,8 +6,8 @@
 @lds = addrspace(3) global [256 x i32] zeroinitializer
 
 define void @load_zeroinit_lds_global(i32 addrspace(1)* %out, i1 %p) {
- %gep = getelementptr [256 x i32] addrspace(3)* @lds, i32 0, i32 10
-  %ld = load i32 addrspace(3)* %gep
+ %gep = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds, i32 0, i32 10
+  %ld = load i32, i32 addrspace(3)* %gep
   store i32 %ld, i32 addrspace(1)* %out
   ret void
 }
diff --git a/test/CodeGen/R600/legalizedag-bug-expand-setcc.ll b/test/CodeGen/R600/legalizedag-bug-expand-setcc.ll
index b9fa8e938ae4..4244c48d240e 100644
--- a/test/CodeGen/R600/legalizedag-bug-expand-setcc.ll
+++ b/test/CodeGen/R600/legalizedag-bug-expand-setcc.ll
@@ -16,7 +16,7 @@ entry:
   %0 = icmp eq i32 %in, 5
   br i1 %0, label %IF, label %ENDIF
 IF:
-  %1 = getelementptr i32 addrspace(1)* %out, i32 1
+  %1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
   store i32 0, i32 addrspace(1)* %1
   br label %ENDIF
 
diff --git a/test/CodeGen/R600/llvm.AMDGPU.abs.ll b/test/CodeGen/R600/llvm.AMDGPU.abs.ll
index 8bc2583899bd..8bf094b8bc7b 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.abs.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.abs.ll
@@ -28,7 +28,7 @@ define void @s_abs_i32(i32 addrspace(1)* %out, i32 %src) nounwind {
 ; EG: SUB_INT
 ; EG: MAX_INT
 define void @v_abs_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind {
-  %val = load i32 addrspace(1)* %src, align 4
+  %val = load i32, i32 addrspace(1)* %src, align 4
   %abs = call i32 @llvm.AMDGPU.abs(i32 %val) nounwind readnone
   store i32 %abs, i32 addrspace(1)* %out, align 4
   ret void
@@ -42,7 +42,7 @@ define void @v_abs_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind
 ; EG: SUB_INT
 ; EG: MAX_INT
 define void @abs_i32_legacy_amdil(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind {
-  %val = load i32 addrspace(1)* %src, align 4
+  %val = load i32, i32 addrspace(1)* %src, align 4
   %abs = call i32 @llvm.AMDIL.abs.i32(i32 %val) nounwind readnone
   store i32 %abs, i32 addrspace(1)* %out, align 4
   ret void
diff --git a/test/CodeGen/R600/llvm.AMDGPU.barrier.global.ll b/test/CodeGen/R600/llvm.AMDGPU.barrier.global.ll
index a11d9ae7af08..db883972d646 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.barrier.global.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.barrier.global.ll
@@ -10,14 +10,14 @@
 define void @test_barrier_global(i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.tidig.x()
-  %1 = getelementptr i32 addrspace(1)* %out, i32 %0
+  %1 = getelementptr i32, i32 addrspace(1)* %out, i32 %0
   store i32 %0, i32 addrspace(1)* %1
   call void @llvm.AMDGPU.barrier.global()
   %2 = call i32 @llvm.r600.read.local.size.x()
   %3 = sub i32 %2, 1
   %4 = sub i32 %3, %0
-  %5 = getelementptr i32 addrspace(1)* %out, i32 %4
-  %6 = load i32 addrspace(1)* %5
+  %5 = getelementptr i32, i32 addrspace(1)* %out, i32 %4
+  %6 = load i32, i32 addrspace(1)* %5
   store i32 %6, i32 addrspace(1)* %1
   ret void
 }
diff --git a/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll b/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll
index 76c2453d089f..48fb2e0b1a8d 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll
@@ -11,14 +11,14 @@
 define void @test_barrier_local(i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.tidig.x()
-  %1 = getelementptr i32 addrspace(1)* %out, i32 %0
+  %1 = getelementptr i32, i32 addrspace(1)* %out, i32 %0
   store i32 %0, i32 addrspace(1)* %1
   call void @llvm.AMDGPU.barrier.local()
   %2 = call i32 @llvm.r600.read.local.size.x()
   %3 = sub i32 %2, 1
   %4 = sub i32 %3, %0
-  %5 = getelementptr i32 addrspace(1)* %out, i32 %4
-  %6 = load i32 addrspace(1)* %5
+  %5 = getelementptr i32, i32 addrspace(1)* %out, i32 %4
+  %6 = load i32, i32 addrspace(1)* %5
   store i32 %6, i32 addrspace(1)* %1
   ret void
 }
diff --git a/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll b/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll
index 2ec2546be39b..1168713ca66e 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll
@@ -44,7 +44,7 @@ define void @bfe_i32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) n
 ; FUNC-LABEL: {{^}}v_bfe_print_arg:
 ; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 2, 8
 define void @v_bfe_print_arg(i32 addrspace(1)* %out, i32 addrspace(1)* %src0) nounwind {
-  %load = load i32 addrspace(1)* %src0, align 4
+  %load = load i32, i32 addrspace(1)* %src0, align 4
   %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 2, i32 8) nounwind readnone
   store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
   ret void
@@ -75,7 +75,7 @@ define void @bfe_i32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i
 ; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
 ; SI: s_endpgm
 define void @bfe_i32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = shl i32 %x, 31
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 1, i32 31)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
@@ -89,20 +89,19 @@ define void @bfe_i32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw
 ; SI: buffer_store_dword [[VREG]],
 ; SI: s_endpgm
 define void @bfe_i32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = shl i32 %x, 31
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 0, i32 31)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
   ret void
 }
 
-; FIXME: The shifts should be 1 BFE
 ; FUNC-LABEL: {{^}}bfe_i32_test_8:
 ; SI: buffer_load_dword
 ; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1
 ; SI: s_endpgm
 define void @bfe_i32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = shl i32 %x, 31
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 31, i32 1)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
@@ -115,7 +114,7 @@ define void @bfe_i32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_i32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 31, i32 1)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
   ret void
@@ -127,7 +126,7 @@ define void @bfe_i32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_i32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 1, i32 31)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
   ret void
@@ -139,7 +138,7 @@ define void @bfe_i32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_i32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 8, i32 24)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
   ret void
@@ -151,7 +150,7 @@ define void @bfe_i32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_i32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 24, i32 8)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
   ret void
@@ -162,7 +161,7 @@ define void @bfe_i32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_i32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = ashr i32 %x, 31
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 31, i32 1)
   store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
@@ -173,7 +172,7 @@ define void @bfe_i32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_i32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = lshr i32 %x, 31
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 31, i32 1)
   store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
@@ -407,18 +406,14 @@ define void @bfe_i32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind {
   ret void
 }
 
-; XXX - This should really be a single BFE, but the sext_inreg of the
-; extended type i24 is never custom lowered.
 ; FUNC-LABEL: {{^}}bfe_sext_in_reg_i24:
 ; SI: buffer_load_dword [[LOAD:v[0-9]+]],
-; SI: v_lshlrev_b32_e32 {{v[0-9]+}}, 8, {{v[0-9]+}}
-; SI: v_ashrrev_i32_e32 {{v[0-9]+}}, 8, {{v[0-9]+}}
-; XSI: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 0, 8
-; XSI-NOT: SHL
-; XSI-NOT: SHR
-; XSI: buffer_store_dword [[BFE]],
+; SI-NOT: v_lshl
+; SI-NOT: v_ashr
+; SI: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 0, 24
+; SI: buffer_store_dword [[BFE]],
 define void @bfe_sext_in_reg_i24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 0, i32 24)
   %shl = shl i32 %bfe, 8
   %ashr = ashr i32 %shl, 8
@@ -434,7 +429,7 @@ define void @bfe_sext_in_reg_i24(i32 addrspace(1)* %out, i32 addrspace(1)* %in)
 ; SI: v_ashrrev_i32_e32 [[TMP2:v[0-9]+]], 1, [[TMP1]]
 ; SI: buffer_store_dword [[TMP2]]
 define void @simplify_demanded_bfe_sdiv(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %src = load i32 addrspace(1)* %in, align 4
+  %src = load i32, i32 addrspace(1)* %in, align 4
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %src, i32 1, i32 16) nounwind readnone
   %div = sdiv i32 %bfe, 2
   store i32 %div, i32 addrspace(1)* %out, align 4
diff --git a/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll b/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll
index 6cd0108def2d..541119242a94 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll
@@ -65,7 +65,7 @@ define void @bfe_u32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_u32_zextload_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind {
-  %load = load i8 addrspace(1)* %in
+  %load = load i8, i8 addrspace(1)* %in
   %ext = zext i8 %load to i32
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 0, i32 8)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
@@ -79,7 +79,7 @@ define void @bfe_u32_zextload_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) n
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_u32_zext_in_reg_i8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %load = load i32 addrspace(1)* %in, align 4
+  %load = load i32, i32 addrspace(1)* %in, align 4
   %add = add i32 %load, 1
   %ext = and i32 %add, 255
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 0, i32 8)
@@ -94,7 +94,7 @@ define void @bfe_u32_zext_in_reg_i8(i32 addrspace(1)* %out, i32 addrspace(1)* %i
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_u32_zext_in_reg_i16(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %load = load i32 addrspace(1)* %in, align 4
+  %load = load i32, i32 addrspace(1)* %in, align 4
   %add = add i32 %load, 1
   %ext = and i32 %add, 65535
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 0, i32 16)
@@ -108,7 +108,7 @@ define void @bfe_u32_zext_in_reg_i16(i32 addrspace(1)* %out, i32 addrspace(1)* %
 ; SI: bfe
 ; SI: s_endpgm
 define void @bfe_u32_zext_in_reg_i8_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %load = load i32 addrspace(1)* %in, align 4
+  %load = load i32, i32 addrspace(1)* %in, align 4
   %add = add i32 %load, 1
   %ext = and i32 %add, 255
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 1, i32 8)
@@ -123,7 +123,7 @@ define void @bfe_u32_zext_in_reg_i8_offset_1(i32 addrspace(1)* %out, i32 addrspa
 ; SI-NEXT: bfe
 ; SI: s_endpgm
 define void @bfe_u32_zext_in_reg_i8_offset_3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %load = load i32 addrspace(1)* %in, align 4
+  %load = load i32, i32 addrspace(1)* %in, align 4
   %add = add i32 %load, 1
   %ext = and i32 %add, 255
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 3, i32 8)
@@ -138,7 +138,7 @@ define void @bfe_u32_zext_in_reg_i8_offset_3(i32 addrspace(1)* %out, i32 addrspa
 ; SI-NEXT: bfe
 ; SI: s_endpgm
 define void @bfe_u32_zext_in_reg_i8_offset_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %load = load i32 addrspace(1)* %in, align 4
+  %load = load i32, i32 addrspace(1)* %in, align 4
   %add = add i32 %load, 1
   %ext = and i32 %add, 255
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 7, i32 8)
@@ -152,7 +152,7 @@ define void @bfe_u32_zext_in_reg_i8_offset_7(i32 addrspace(1)* %out, i32 addrspa
 ; SI-NEXT: bfe
 ; SI: s_endpgm
 define void @bfe_u32_zext_in_reg_i16_offset_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %load = load i32 addrspace(1)* %in, align 4
+  %load = load i32, i32 addrspace(1)* %in, align 4
   %add = add i32 %load, 1
   %ext = and i32 %add, 65535
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 8, i32 8)
@@ -166,14 +166,14 @@ define void @bfe_u32_zext_in_reg_i16_offset_8(i32 addrspace(1)* %out, i32 addrsp
 ; SI: s_endpgm
 ; EG: AND_INT T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, 1,
 define void @bfe_u32_test_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 0, i32 1)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 define void @bfe_u32_test_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = shl i32 %x, 31
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 0, i32 8)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
@@ -181,7 +181,7 @@ define void @bfe_u32_test_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw
 }
 
 define void @bfe_u32_test_3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = shl i32 %x, 31
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 0, i32 1)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
@@ -196,7 +196,7 @@ define void @bfe_u32_test_3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw
 ; SI: buffer_store_dword [[VREG]],
 ; SI: s_endpgm
 define void @bfe_u32_test_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = shl i32 %x, 31
   %shr = lshr i32 %shl, 31
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shr, i32 31, i32 1)
@@ -211,7 +211,7 @@ define void @bfe_u32_test_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw
 ; SI: v_bfe_i32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1
 ; SI: s_endpgm
 define void @bfe_u32_test_5(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = shl i32 %x, 31
   %shr = ashr i32 %shl, 31
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shr, i32 0, i32 1)
@@ -224,7 +224,7 @@ define void @bfe_u32_test_5(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw
 ; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
 ; SI: s_endpgm
 define void @bfe_u32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = shl i32 %x, 31
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 1, i32 31)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
@@ -236,7 +236,7 @@ define void @bfe_u32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_u32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = shl i32 %x, 31
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 0, i32 31)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
@@ -249,7 +249,7 @@ define void @bfe_u32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_u32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = shl i32 %x, 31
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 31, i32 1)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
@@ -262,7 +262,7 @@ define void @bfe_u32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_u32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 31, i32 1)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
   ret void
@@ -274,7 +274,7 @@ define void @bfe_u32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_u32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 1, i32 31)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
   ret void
@@ -286,7 +286,7 @@ define void @bfe_u32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_u32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 8, i32 24)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
   ret void
@@ -298,7 +298,7 @@ define void @bfe_u32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_u32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 24, i32 8)
   store i32 %bfe, i32 addrspace(1)* %out, align 4
   ret void
@@ -309,7 +309,7 @@ define void @bfe_u32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_u32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = ashr i32 %x, 31
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 31, i32 1)
   store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
@@ -320,7 +320,7 @@ define void @bfe_u32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_u32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = lshr i32 %x, 31
   %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 31, i32 1)
   store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
@@ -439,7 +439,7 @@ define void @bfe_u32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind {
 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
 ; SI: buffer_store_dword [[VREG]],
 ; SI: s_endpgm
-; EG-NOT: BFEfppppppppppppp
+; EG-NOT: BFE
 define void @bfe_u32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind {
   %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 65536, i32 16, i32 8) nounwind readnone
   store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
@@ -568,10 +568,60 @@ define void @bfe_u32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind {
 define void @simplify_bfe_u32_multi_use_arg(i32 addrspace(1)* %out0,
                                             i32 addrspace(1)* %out1,
                                             i32 addrspace(1)* %in) nounwind {
-  %src = load i32 addrspace(1)* %in, align 4
+  %src = load i32, i32 addrspace(1)* %in, align 4
   %and = and i32 %src, 63
   %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %and, i32 2, i32 2) nounwind readnone
   store i32 %bfe_u32, i32 addrspace(1)* %out0, align 4
   store i32 %and, i32 addrspace(1)* %out1, align 4
   ret void
 }
+
+; FUNC-LABEL: {{^}}lshr_and:
+; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x30006
+; SI: buffer_store_dword
+define void @lshr_and(i32 addrspace(1)* %out, i32 %a) nounwind {
+  %b = lshr i32 %a, 6
+  %c = and i32 %b, 7
+  store i32 %c, i32 addrspace(1)* %out, align 8
+  ret void
+}
+
+; FUNC-LABEL: {{^}}v_lshr_and:
+; SI: v_bfe_u32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}, 3
+; SI: buffer_store_dword
+define void @v_lshr_and(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
+  %c = lshr i32 %a, %b
+  %d = and i32 %c, 7
+  store i32 %d, i32 addrspace(1)* %out, align 8
+  ret void
+}
+
+; FUNC-LABEL: {{^}}and_lshr:
+; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x30006
+; SI: buffer_store_dword
+define void @and_lshr(i32 addrspace(1)* %out, i32 %a) nounwind {
+  %b = and i32 %a, 448
+  %c = lshr i32 %b, 6
+  store i32 %c, i32 addrspace(1)* %out, align 8
+  ret void
+}
+
+; FUNC-LABEL: {{^}}and_lshr2:
+; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x30006
+; SI: buffer_store_dword
+define void @and_lshr2(i32 addrspace(1)* %out, i32 %a) nounwind {
+  %b = and i32 %a, 511
+  %c = lshr i32 %b, 6
+  store i32 %c, i32 addrspace(1)* %out, align 8
+  ret void
+}
+
+; FUNC-LABEL: {{^}}shl_lshr:
+; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x150002
+; SI: buffer_store_dword
+define void @shl_lshr(i32 addrspace(1)* %out, i32 %a) nounwind {
+  %b = shl i32 %a, 9
+  %c = lshr i32 %b, 11
+  store i32 %c, i32 addrspace(1)* %out, align 8
+  ret void
+}
diff --git a/test/CodeGen/R600/llvm.AMDGPU.bfm.ll b/test/CodeGen/R600/llvm.AMDGPU.bfm.ll
index 2346f408ec44..50492289d744 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.bfm.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.bfm.ll
@@ -5,7 +5,7 @@
 declare i32 @llvm.AMDGPU.bfm(i32, i32) nounwind readnone
 
 ; FUNC-LABEL: {{^}}bfm_arg_arg:
-; SI: v_bfm
+; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
 ; EG: BFM_INT
 define void @bfm_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
   %bfm = call i32 @llvm.AMDGPU.bfm(i32 %src0, i32 %src1) nounwind readnone
@@ -14,7 +14,7 @@ define void @bfm_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind
 }
 
 ; FUNC-LABEL: {{^}}bfm_arg_imm:
-; SI: v_bfm
+; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x7b
 ; EG: BFM_INT
 define void @bfm_arg_imm(i32 addrspace(1)* %out, i32 %src0) nounwind {
   %bfm = call i32 @llvm.AMDGPU.bfm(i32 %src0, i32 123) nounwind readnone
@@ -23,7 +23,7 @@ define void @bfm_arg_imm(i32 addrspace(1)* %out, i32 %src0) nounwind {
 }
 
 ; FUNC-LABEL: {{^}}bfm_imm_arg:
-; SI: v_bfm
+; SI: s_bfm_b32 {{s[0-9]+}}, 0x7b, {{s[0-9]+}}
 ; EG: BFM_INT
 define void @bfm_imm_arg(i32 addrspace(1)* %out, i32 %src1) nounwind {
   %bfm = call i32 @llvm.AMDGPU.bfm(i32 123, i32 %src1) nounwind readnone
@@ -32,10 +32,29 @@ define void @bfm_imm_arg(i32 addrspace(1)* %out, i32 %src1) nounwind {
 }
 
 ; FUNC-LABEL: {{^}}bfm_imm_imm:
-; SI: v_bfm
+; SI: s_bfm_b32 {{s[0-9]+}}, 0x7b, 0x1c8
 ; EG: BFM_INT
 define void @bfm_imm_imm(i32 addrspace(1)* %out) nounwind {
   %bfm = call i32 @llvm.AMDGPU.bfm(i32 123, i32 456) nounwind readnone
   store i32 %bfm, i32 addrspace(1)* %out, align 4
   ret void
 }
+
+; FUNC-LABEL: {{^}}bfm_pattern:
+; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+define void @bfm_pattern(i32 addrspace(1)* %out, i32 %x, i32 %y) {
+  %a = shl i32 1, %x
+  %b = sub i32 %a, 1
+  %c = shl i32 %b, %y
+  store i32 %c, i32 addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}bfm_pattern_simple:
+; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0
+define void @bfm_pattern_simple(i32 addrspace(1)* %out, i32 %x) {
+  %a = shl i32 1, %x
+  %b = sub i32 %a, 1
+  store i32 %b, i32 addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/llvm.AMDGPU.brev.ll b/test/CodeGen/R600/llvm.AMDGPU.brev.ll
index 3973f539c135..301de4b1c82d 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.brev.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.brev.ll
@@ -21,7 +21,7 @@ define void @s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
 ; SI: buffer_store_dword [[RESULT]],
 ; SI: s_endpgm
 define void @v_brev_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
-  %val = load i32 addrspace(1)* %valptr, align 4
+  %val = load i32, i32 addrspace(1)* %valptr, align 4
   %ctlz = call i32 @llvm.AMDGPU.brev(i32 %val) nounwind readnone
   store i32 %ctlz, i32 addrspace(1)* %out, align 4
   ret void
diff --git a/test/CodeGen/R600/llvm.AMDGPU.class.ll b/test/CodeGen/R600/llvm.AMDGPU.class.ll
index 974e3c71e622..805a88b59c72 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.class.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.class.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
 
 declare i1 @llvm.AMDGPU.class.f32(float, i32) #1
 declare i1 @llvm.AMDGPU.class.f64(double, i32) #1
@@ -134,9 +134,9 @@ define void @test_class_9bit_mask_f32(i32 addrspace(1)* %out, float %a) #0 {
 ; SI: s_endpgm
 define void @v_test_class_full_mask_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.in = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load float addrspace(1)* %gep.in
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load float, float addrspace(1)* %gep.in
 
   %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 511) #1
   %sext = sext i1 %result to i32
@@ -152,9 +152,9 @@ define void @v_test_class_full_mask_f32(i32 addrspace(1)* %out, float addrspace(
 ; SI: s_endpgm
 define void @test_class_inline_imm_constant_dynamic_mask_f32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.in = getelementptr i32 addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %b = load i32 addrspace(1)* %gep.in
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %b = load i32, i32 addrspace(1)* %gep.in
 
   %result = call i1 @llvm.AMDGPU.class.f32(float 1.0, i32 %b) #1
   %sext = sext i1 %result to i32
@@ -172,9 +172,9 @@ define void @test_class_inline_imm_constant_dynamic_mask_f32(i32 addrspace(1)* %
 ; SI: s_endpgm
 define void @test_class_lit_constant_dynamic_mask_f32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.in = getelementptr i32 addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %b = load i32 addrspace(1)* %gep.in
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %b = load i32, i32 addrspace(1)* %gep.in
 
   %result = call i1 @llvm.AMDGPU.class.f32(float 1024.0, i32 %b) #1
   %sext = sext i1 %result to i32
@@ -290,9 +290,9 @@ define void @test_class_full_mask_f64(i32 addrspace(1)* %out, double %a) #0 {
 ; SI: s_endpgm
 define void @v_test_class_full_mask_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.in = getelementptr double addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load double addrspace(1)* %in
+  %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load double, double addrspace(1)* %in
 
   %result = call i1 @llvm.AMDGPU.class.f64(double %a, i32 511) #1
   %sext = sext i1 %result to i32
@@ -306,9 +306,9 @@ define void @v_test_class_full_mask_f64(i32 addrspace(1)* %out, double addrspace
 ; SI: s_endpgm
 define void @test_class_inline_imm_constant_dynamic_mask_f64(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.in = getelementptr i32 addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %b = load i32 addrspace(1)* %gep.in
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %b = load i32, i32 addrspace(1)* %gep.in
 
   %result = call i1 @llvm.AMDGPU.class.f64(double 1.0, i32 %b) #1
   %sext = sext i1 %result to i32
@@ -321,9 +321,9 @@ define void @test_class_inline_imm_constant_dynamic_mask_f64(i32 addrspace(1)* %
 ; SI: s_endpgm
 define void @test_class_lit_constant_dynamic_mask_f64(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.in = getelementptr i32 addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %b = load i32 addrspace(1)* %gep.in
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %b = load i32, i32 addrspace(1)* %gep.in
 
   %result = call i1 @llvm.AMDGPU.class.f64(double 1024.0, i32 %b) #1
   %sext = sext i1 %result to i32
@@ -338,9 +338,9 @@ define void @test_class_lit_constant_dynamic_mask_f64(i32 addrspace(1)* %out, i3
 ; SI: s_endpgm
 define void @test_fold_or_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.in = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load float addrspace(1)* %gep.in
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load float, float addrspace(1)* %gep.in
 
   %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1) #1
   %class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 3) #1
@@ -358,9 +358,9 @@ define void @test_fold_or_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)
 ; SI: s_endpgm
 define void @test_fold_or3_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.in = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load float addrspace(1)* %gep.in
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load float, float addrspace(1)* %gep.in
 
   %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1) #1
   %class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 2) #1
@@ -381,9 +381,9 @@ define void @test_fold_or3_class_f32_0(i32 addrspace(1)* %out, float addrspace(1
 ; SI: s_endpgm
 define void @test_fold_or_all_tests_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.in = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load float addrspace(1)* %gep.in
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load float, float addrspace(1)* %gep.in
 
   %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1) #1
   %class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 2) #1
@@ -416,9 +416,9 @@ define void @test_fold_or_all_tests_class_f32_0(i32 addrspace(1)* %out, float ad
 ; SI: s_endpgm
 define void @test_fold_or_class_f32_1(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.in = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load float addrspace(1)* %gep.in
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load float, float addrspace(1)* %gep.in
 
   %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 4) #1
   %class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 8) #1
@@ -436,9 +436,9 @@ define void @test_fold_or_class_f32_1(i32 addrspace(1)* %out, float addrspace(1)
 ; SI: s_endpgm
 define void @test_fold_or_class_f32_2(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.in = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load float addrspace(1)* %gep.in
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load float, float addrspace(1)* %gep.in
 
   %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 7) #1
   %class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 7) #1
@@ -456,9 +456,9 @@ define void @test_fold_or_class_f32_2(i32 addrspace(1)* %out, float addrspace(1)
 ; SI: s_endpgm
 define void @test_no_fold_or_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in, float %b) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() #1
-  %gep.in = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load float addrspace(1)* %gep.in
+  %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load float, float addrspace(1)* %gep.in
 
   %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 4) #1
   %class1 = call i1 @llvm.AMDGPU.class.f32(float %b, i32 8) #1
@@ -472,7 +472,7 @@ define void @test_no_fold_or_class_f32_0(i32 addrspace(1)* %out, float addrspace
 ; SI-LABEL: {{^}}test_class_0_f32:
 ; SI-NOT: v_cmp_class
 ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
-; SI-NEXT: buffer_store_dword [[RESULT]]
+; SI: buffer_store_dword [[RESULT]]
 ; SI: s_endpgm
 define void @test_class_0_f32(i32 addrspace(1)* %out, float %a) #0 {
   %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 0) #1
diff --git a/test/CodeGen/R600/llvm.AMDGPU.cube.ll b/test/CodeGen/R600/llvm.AMDGPU.cube.ll
index aa07afdebea6..e95a51093cb7 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.cube.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.cube.ll
@@ -8,15 +8,15 @@
 ; CHECK: CUBE * T{{[0-9]}}.W
 define void @cube() #0 {
 main_body:
-  %0 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+  %0 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
   %1 = extractelement <4 x float> %0, i32 3
-  %2 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+  %2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
   %3 = extractelement <4 x float> %2, i32 0
   %4 = fdiv float %3, %1
-  %5 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+  %5 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
   %6 = extractelement <4 x float> %5, i32 1
   %7 = fdiv float %6, %1
-  %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+  %8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
   %9 = extractelement <4 x float> %8, i32 2
   %10 = fdiv float %9, %1
   %11 = insertelement <4 x float> undef, float %4, i32 0
diff --git a/test/CodeGen/R600/llvm.AMDGPU.cvt_f32_ubyte.ll b/test/CodeGen/R600/llvm.AMDGPU.cvt_f32_ubyte.ll
index 799817e01096..8b32f696449e 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.cvt_f32_ubyte.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.cvt_f32_ubyte.ll
@@ -9,7 +9,7 @@ declare float @llvm.AMDGPU.cvt.f32.ubyte3(i32) nounwind readnone
 ; SI-LABEL: {{^}}test_unpack_byte0_to_float:
 ; SI: v_cvt_f32_ubyte0
 define void @test_unpack_byte0_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %val = load i32 addrspace(1)* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte0(i32 %val) nounwind readnone
   store float %cvt, float addrspace(1)* %out, align 4
   ret void
@@ -18,7 +18,7 @@ define void @test_unpack_byte0_to_float(float addrspace(1)* %out, i32 addrspace(
 ; SI-LABEL: {{^}}test_unpack_byte1_to_float:
 ; SI: v_cvt_f32_ubyte1
 define void @test_unpack_byte1_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %val = load i32 addrspace(1)* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %val) nounwind readnone
   store float %cvt, float addrspace(1)* %out, align 4
   ret void
@@ -27,7 +27,7 @@ define void @test_unpack_byte1_to_float(float addrspace(1)* %out, i32 addrspace(
 ; SI-LABEL: {{^}}test_unpack_byte2_to_float:
 ; SI: v_cvt_f32_ubyte2
 define void @test_unpack_byte2_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %val = load i32 addrspace(1)* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte2(i32 %val) nounwind readnone
   store float %cvt, float addrspace(1)* %out, align 4
   ret void
@@ -36,7 +36,7 @@ define void @test_unpack_byte2_to_float(float addrspace(1)* %out, i32 addrspace(
 ; SI-LABEL: {{^}}test_unpack_byte3_to_float:
 ; SI: v_cvt_f32_ubyte3
 define void @test_unpack_byte3_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %val = load i32 addrspace(1)* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte3(i32 %val) nounwind readnone
   store float %cvt, float addrspace(1)* %out, align 4
   ret void
diff --git a/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll b/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll
index 52d0519ef277..55ca9c7536e5 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll
@@ -1,25 +1,29 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
 
 declare float @llvm.AMDGPU.div.fixup.f32(float, float, float) nounwind readnone
 declare double @llvm.AMDGPU.div.fixup.f64(double, double, double) nounwind readnone
 
-; SI-LABEL: {{^}}test_div_fixup_f32:
+; GCN-LABEL: {{^}}test_div_fixup_f32:
 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
-; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
-; SI: v_div_fixup_f32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
+; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34
+; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
+; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
+; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
+; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]]
+; GCN: buffer_store_dword [[RESULT]],
+; GCN: s_endpgm
 define void @test_div_fixup_f32(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
   %result = call float @llvm.AMDGPU.div.fixup.f32(float %a, float %b, float %c) nounwind readnone
   store float %result, float addrspace(1)* %out, align 4
   ret void
 }
 
-; SI-LABEL: {{^}}test_div_fixup_f64:
-; SI: v_div_fixup_f64
+; GCN-LABEL: {{^}}test_div_fixup_f64:
+; GCN: v_div_fixup_f64
 define void @test_div_fixup_f64(double addrspace(1)* %out, double %a, double %b, double %c) nounwind {
   %result = call double @llvm.AMDGPU.div.fixup.f64(double %a, double %b, double %c) nounwind readnone
   store double %result, double addrspace(1)* %out, align 8
diff --git a/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll b/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll
index bbe910a45e8f..bcb7f870f1f4 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll
@@ -9,13 +9,16 @@ declare float @llvm.AMDGPU.div.fmas.f32(float, float, float, i1) nounwind readno
 declare double @llvm.AMDGPU.div.fmas.f64(double, double, double, i1) nounwind readnone
 
 ; GCN-LABEL: {{^}}test_div_fmas_f32:
-; GCN-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; GCN-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; GCN-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
+; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
+; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
+; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
+; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34
+; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
 ; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
 ; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
 ; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
-; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], [[VC]]
+; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VB]], [[VA]], [[VC]]
 ; GCN: buffer_store_dword [[RESULT]],
 ; GCN: s_endpgm
 define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
@@ -24,8 +27,50 @@ define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, flo
   ret void
 }
 
-; SI-LABEL: {{^}}test_div_fmas_f64:
-; SI: v_div_fmas_f64
+; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_0:
+; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
+; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
+; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
+; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
+; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VB]], [[VC]]
+; SI: buffer_store_dword [[RESULT]],
+; SI: s_endpgm
+define void @test_div_fmas_f32_inline_imm_0(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
+  %result = call float @llvm.AMDGPU.div.fmas.f32(float 1.0, float %b, float %c, i1 %d) nounwind readnone
+  store float %result, float addrspace(1)* %out, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_1:
+; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
+; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
+; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
+; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
+; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VA]], [[VC]]
+; SI: buffer_store_dword [[RESULT]],
+; SI: s_endpgm
+define void @test_div_fmas_f32_inline_imm_1(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
+  %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float 1.0, float %c, i1 %d) nounwind readnone
+  store float %result, float addrspace(1)* %out, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_2:
+; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
+; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
+; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
+; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
+; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], 1.0
+; SI: buffer_store_dword [[RESULT]],
+; SI: s_endpgm
+define void @test_div_fmas_f32_inline_imm_2(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
+  %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float 1.0, i1 %d) nounwind readnone
+  store float %result, float addrspace(1)* %out, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_div_fmas_f64:
+; GCN: v_div_fmas_f64
 define void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind {
   %result = call double @llvm.AMDGPU.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone
   store double %result, double addrspace(1)* %out, align 8
@@ -33,7 +78,7 @@ define void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b,
 }
 
 ; GCN-LABEL: {{^}}test_div_fmas_f32_cond_to_vcc:
-; SI: v_cmp_eq_i32_e64 vcc, s{{[0-9]+}}, 0
+; SI: v_cmp_eq_i32_e64 vcc, 0, s{{[0-9]+}}
 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
 define void @test_div_fmas_f32_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c, i32 %i) nounwind {
   %cmp = icmp eq i32 %i, 0
@@ -61,25 +106,25 @@ define void @test_div_fmas_f32_imm_true_cond_to_vcc(float addrspace(1)* %out, fl
 }
 
 ; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc:
-; SI-DAG: v_cmp_eq_i32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0
-; SI-DAG: v_cmp_ne_i32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0
-; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]]
 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
 
-; SI: v_div_fmas_f32 {{v[0-9]+}}, [[B]], [[A]], [[C]]
+; SI-DAG: v_cmp_eq_i32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}}
+; SI-DAG: v_cmp_ne_i32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}}
+; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]]
+; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]]
 ; SI: s_endpgm
 define void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.a = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.b = getelementptr float addrspace(1)* %gep.a, i32 1
-  %gep.c = getelementptr float addrspace(1)* %gep.a, i32 2
-  %gep.out = getelementptr float addrspace(1)* %out, i32 2
+  %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1
+  %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 2
 
-  %a = load float addrspace(1)* %gep.a
-  %b = load float addrspace(1)* %gep.b
-  %c = load float addrspace(1)* %gep.c
+  %a = load float, float addrspace(1)* %gep.a
+  %b = load float, float addrspace(1)* %gep.b
+  %c = load float, float addrspace(1)* %gep.c
 
   %cmp0 = icmp eq i32 %tid, 0
   %cmp1 = icmp ne i32 %d, 0
@@ -91,17 +136,17 @@ define void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, flo
 }
 
 ; GCN-LABEL: {{^}}test_div_fmas_f32_i1_phi_vcc:
-; SI: v_cmp_eq_i32_e64 [[CMPTID:s\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0
-; SI: s_and_saveexec_b64 [[CMPTID]], [[CMPTID]]
-; SI: s_xor_b64 [[CMPTID]], exec, [[CMPTID]]
+; SI: v_cmp_eq_i32_e32 vcc, 0, v{{[0-9]+}}
+; SI: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc
+; SI: s_xor_b64 [[SAVE]], exec, [[SAVE]]
 
 ; SI: buffer_load_dword [[LOAD:v[0-9]+]]
-; SI: v_cmp_ne_i32_e64 [[CMPLOAD:s\[[0-9]+:[0-9]+\]]], [[LOAD]], 0
-; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, [[CMPLOAD]]
+; SI: v_cmp_ne_i32_e32 vcc, 0, [[LOAD]]
+; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
 
 
-; SI: BB6_2:
-; SI: s_or_b64 exec, exec, [[CMPTID]]
+; SI: BB9_2:
+; SI: s_or_b64 exec, exec, [[SAVE]]
 ; SI: v_cmp_ne_i32_e32 vcc, 0, v0
 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
 ; SI: buffer_store_dword
@@ -109,20 +154,20 @@ define void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, flo
 define void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) nounwind {
 entry:
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.out = getelementptr float addrspace(1)* %out, i32 2
-  %gep.a = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.b = getelementptr float addrspace(1)* %gep.a, i32 1
-  %gep.c = getelementptr float addrspace(1)* %gep.a, i32 2
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 2
+  %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1
+  %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2
 
-  %a = load float addrspace(1)* %gep.a
-  %b = load float addrspace(1)* %gep.b
-  %c = load float addrspace(1)* %gep.c
+  %a = load float, float addrspace(1)* %gep.a
+  %b = load float, float addrspace(1)* %gep.b
+  %c = load float, float addrspace(1)* %gep.c
 
   %cmp0 = icmp eq i32 %tid, 0
   br i1 %cmp0, label %bb, label %exit
 
 bb:
-  %val = load i32 addrspace(1)* %dummy
+  %val = load i32, i32 addrspace(1)* %dummy
   %cmp1 = icmp ne i32 %val, 0
   br label %exit
 
diff --git a/test/CodeGen/R600/llvm.AMDGPU.div_scale.ll b/test/CodeGen/R600/llvm.AMDGPU.div_scale.ll
index 5773da0bb2e4..de830de039c7 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.div_scale.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.div_scale.ll
@@ -13,11 +13,11 @@ declare float @llvm.fabs.f32(float) nounwind readnone
 ; SI: s_endpgm
 define void @test_div_scale_f32_1(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
 
-  %a = load float addrspace(1)* %gep.0, align 4
-  %b = load float addrspace(1)* %gep.1, align 4
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
 
   %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
   %result0 = extractvalue { float, i1 } %result, 0
@@ -33,11 +33,11 @@ define void @test_div_scale_f32_1(float addrspace(1)* %out, float addrspace(1)*
 ; SI: s_endpgm
 define void @test_div_scale_f32_2(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
 
-  %a = load float addrspace(1)* %gep.0, align 4
-  %b = load float addrspace(1)* %gep.1, align 4
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
 
   %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
   %result0 = extractvalue { float, i1 } %result, 0
@@ -53,11 +53,11 @@ define void @test_div_scale_f32_2(float addrspace(1)* %out, float addrspace(1)*
 ; SI: s_endpgm
 define void @test_div_scale_f64_1(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr double addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr double addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
 
-  %a = load double addrspace(1)* %gep.0, align 8
-  %b = load double addrspace(1)* %gep.1, align 8
+  %a = load double, double addrspace(1)* %gep.0, align 8
+  %b = load double, double addrspace(1)* %gep.1, align 8
 
   %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
   %result0 = extractvalue { double, i1 } %result, 0
@@ -73,11 +73,11 @@ define void @test_div_scale_f64_1(double addrspace(1)* %out, double addrspace(1)
 ; SI: s_endpgm
 define void @test_div_scale_f64_2(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr double addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr double addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
 
-  %a = load double addrspace(1)* %gep.0, align 8
-  %b = load double addrspace(1)* %gep.1, align 8
+  %a = load double, double addrspace(1)* %gep.0, align 8
+  %b = load double, double addrspace(1)* %gep.1, align 8
 
   %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
   %result0 = extractvalue { double, i1 } %result, 0
@@ -93,9 +93,9 @@ define void @test_div_scale_f64_2(double addrspace(1)* %out, double addrspace(1)
 ; SI: s_endpgm
 define void @test_div_scale_f32_scalar_num_1(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep = getelementptr float addrspace(1)* %in, i32 %tid
+  %gep = getelementptr float, float addrspace(1)* %in, i32 %tid
 
-  %b = load float addrspace(1)* %gep, align 4
+  %b = load float, float addrspace(1)* %gep, align 4
 
   %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
   %result0 = extractvalue { float, i1 } %result, 0
@@ -111,9 +111,9 @@ define void @test_div_scale_f32_scalar_num_1(float addrspace(1)* %out, float add
 ; SI: s_endpgm
 define void @test_div_scale_f32_scalar_num_2(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep = getelementptr float addrspace(1)* %in, i32 %tid
+  %gep = getelementptr float, float addrspace(1)* %in, i32 %tid
 
-  %b = load float addrspace(1)* %gep, align 4
+  %b = load float, float addrspace(1)* %gep, align 4
 
   %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
   %result0 = extractvalue { float, i1 } %result, 0
@@ -129,9 +129,9 @@ define void @test_div_scale_f32_scalar_num_2(float addrspace(1)* %out, float add
 ; SI: s_endpgm
 define void @test_div_scale_f32_scalar_den_1(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep = getelementptr float addrspace(1)* %in, i32 %tid
+  %gep = getelementptr float, float addrspace(1)* %in, i32 %tid
 
-  %a = load float addrspace(1)* %gep, align 4
+  %a = load float, float addrspace(1)* %gep, align 4
 
   %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
   %result0 = extractvalue { float, i1 } %result, 0
@@ -147,9 +147,9 @@ define void @test_div_scale_f32_scalar_den_1(float addrspace(1)* %out, float add
 ; SI: s_endpgm
 define void @test_div_scale_f32_scalar_den_2(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep = getelementptr float addrspace(1)* %in, i32 %tid
+  %gep = getelementptr float, float addrspace(1)* %in, i32 %tid
 
-  %a = load float addrspace(1)* %gep, align 4
+  %a = load float, float addrspace(1)* %gep, align 4
 
   %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
   %result0 = extractvalue { float, i1 } %result, 0
@@ -165,9 +165,9 @@ define void @test_div_scale_f32_scalar_den_2(float addrspace(1)* %out, float add
 ; SI: s_endpgm
 define void @test_div_scale_f64_scalar_num_1(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep = getelementptr double addrspace(1)* %in, i32 %tid
+  %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
 
-  %b = load double addrspace(1)* %gep, align 8
+  %b = load double, double addrspace(1)* %gep, align 8
 
   %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
   %result0 = extractvalue { double, i1 } %result, 0
@@ -183,9 +183,9 @@ define void @test_div_scale_f64_scalar_num_1(double addrspace(1)* %out, double a
 ; SI: s_endpgm
 define void @test_div_scale_f64_scalar_num_2(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep = getelementptr double addrspace(1)* %in, i32 %tid
+  %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
 
-  %b = load double addrspace(1)* %gep, align 8
+  %b = load double, double addrspace(1)* %gep, align 8
 
   %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
   %result0 = extractvalue { double, i1 } %result, 0
@@ -201,9 +201,9 @@ define void @test_div_scale_f64_scalar_num_2(double addrspace(1)* %out, double a
 ; SI: s_endpgm
 define void @test_div_scale_f64_scalar_den_1(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep = getelementptr double addrspace(1)* %in, i32 %tid
+  %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
 
-  %a = load double addrspace(1)* %gep, align 8
+  %a = load double, double addrspace(1)* %gep, align 8
 
   %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
   %result0 = extractvalue { double, i1 } %result, 0
@@ -219,9 +219,9 @@ define void @test_div_scale_f64_scalar_den_1(double addrspace(1)* %out, double a
 ; SI: s_endpgm
 define void @test_div_scale_f64_scalar_den_2(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep = getelementptr double addrspace(1)* %in, i32 %tid
+  %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
 
-  %a = load double addrspace(1)* %gep, align 8
+  %a = load double, double addrspace(1)* %gep, align 8
 
   %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
   %result0 = extractvalue { double, i1 } %result, 0
@@ -294,8 +294,8 @@ define void @test_div_scale_f64_all_scalar_2(double addrspace(1)* %out, double %
 ; SI: s_endpgm
 define void @test_div_scale_f32_inline_imm_num(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %a = load float addrspace(1)* %gep.0, align 4
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %a = load float, float addrspace(1)* %gep.0, align 4
 
   %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float 1.0, float %a, i1 false) nounwind readnone
   %result0 = extractvalue { float, i1 } %result, 0
@@ -310,8 +310,8 @@ define void @test_div_scale_f32_inline_imm_num(float addrspace(1)* %out, float a
 ; SI: s_endpgm
 define void @test_div_scale_f32_inline_imm_den(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %a = load float addrspace(1)* %gep.0, align 4
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %a = load float, float addrspace(1)* %gep.0, align 4
 
   %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float 2.0, i1 false) nounwind readnone
   %result0 = extractvalue { float, i1 } %result, 0
@@ -327,11 +327,11 @@ define void @test_div_scale_f32_inline_imm_den(float addrspace(1)* %out, float a
 ; SI: s_endpgm
 define void @test_div_scale_f32_fabs_num(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
 
-  %a = load float addrspace(1)* %gep.0, align 4
-  %b = load float addrspace(1)* %gep.1, align 4
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
 
   %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone
 
@@ -349,11 +349,11 @@ define void @test_div_scale_f32_fabs_num(float addrspace(1)* %out, float addrspa
 ; SI: s_endpgm
 define void @test_div_scale_f32_fabs_den(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
 
-  %a = load float addrspace(1)* %gep.0, align 4
-  %b = load float addrspace(1)* %gep.1, align 4
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
 
   %b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone
 
diff --git a/test/CodeGen/R600/llvm.AMDGPU.flbit.i32.ll b/test/CodeGen/R600/llvm.AMDGPU.flbit.i32.ll
index 19fbee8913b4..20c7af8ade5e 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.flbit.i32.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.flbit.i32.ll
@@ -21,7 +21,7 @@ define void @s_flbit(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
 ; SI: buffer_store_dword [[RESULT]],
 ; SI: s_endpgm
 define void @v_flbit(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
-  %val = load i32 addrspace(1)* %valptr, align 4
+  %val = load i32, i32 addrspace(1)* %valptr, align 4
   %r = call i32 @llvm.AMDGPU.flbit.i32(i32 %val) nounwind readnone
   store i32 %r, i32 addrspace(1)* %out, align 4
   ret void
diff --git a/test/CodeGen/R600/llvm.AMDGPU.fract.f64.ll b/test/CodeGen/R600/llvm.AMDGPU.fract.f64.ll
new file mode 100644
index 000000000000..e098dd35d6da
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.fract.f64.ll
@@ -0,0 +1,60 @@
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
+
+declare double @llvm.fabs.f64(double %Val)
+declare double @llvm.AMDGPU.fract.f64(double) nounwind readnone
+
+; FUNC-LABEL: {{^}}fract_f64:
+; GCN: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
+; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
+; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
+; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
+; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
+; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]]
+; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]]
+; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
+; CI: buffer_store_dwordx2 [[FRC]]
+define void @fract_f64(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
+  %val = load double, double addrspace(1)* %src, align 4
+  %fract = call double @llvm.AMDGPU.fract.f64(double %val) nounwind readnone
+  store double %fract, double addrspace(1)* %out, align 4
+  ret void
+}
+
+; FUNC-LABEL: {{^}}fract_f64_neg:
+; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
+; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
+; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
+; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
+; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
+; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]]
+; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]]
+; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
+; CI: buffer_store_dwordx2 [[FRC]]
+define void @fract_f64_neg(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
+  %val = load double, double addrspace(1)* %src, align 4
+  %neg = fsub double 0.0, %val
+  %fract = call double @llvm.AMDGPU.fract.f64(double %neg) nounwind readnone
+  store double %fract, double addrspace(1)* %out, align 4
+  ret void
+}
+
+; FUNC-LABEL: {{^}}fract_f64_neg_abs:
+; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]|
+; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
+; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
+; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
+; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
+; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]]
+; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]]
+; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
+; CI: buffer_store_dwordx2 [[FRC]]
+define void @fract_f64_neg_abs(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
+  %val = load double, double addrspace(1)* %src, align 4
+  %abs = call double @llvm.fabs.f64(double %val)
+  %neg = fsub double 0.0, %abs
+  %fract = call double @llvm.AMDGPU.fract.f64(double %neg) nounwind readnone
+  store double %fract, double addrspace(1)* %out, align 4
+  ret void
+}
diff --git a/test/CodeGen/R600/llvm.AMDGPU.fract.ll b/test/CodeGen/R600/llvm.AMDGPU.fract.ll
index ef89742441c6..7501b4b75465 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.fract.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.fract.ll
@@ -16,7 +16,7 @@ declare float @llvm.AMDIL.fraction.f32(float) nounwind readnone
 ; GCN: buffer_store_dword [[RESULT]]
 ; EG: FRACT
 define void @fract_f32(float addrspace(1)* %out, float addrspace(1)* %src) nounwind {
-  %val = load float addrspace(1)* %src, align 4
+  %val = load float, float addrspace(1)* %src, align 4
   %fract = call float @llvm.AMDGPU.fract.f32(float %val) nounwind readnone
   store float %fract, float addrspace(1)* %out, align 4
   ret void
@@ -29,7 +29,7 @@ define void @fract_f32(float addrspace(1)* %out, float addrspace(1)* %src) nounw
 ; GCN: buffer_store_dword [[RESULT]]
 ; EG: FRACT
 define void @fract_f32_legacy_amdil(float addrspace(1)* %out, float addrspace(1)* %src) nounwind {
-  %val = load float addrspace(1)* %src, align 4
+  %val = load float, float addrspace(1)* %src, align 4
   %fract = call float @llvm.AMDIL.fraction.f32(float %val) nounwind readnone
   store float %fract, float addrspace(1)* %out, align 4
   ret void
@@ -42,7 +42,7 @@ define void @fract_f32_legacy_amdil(float addrspace(1)* %out, float addrspace(1)
 ; GCN: buffer_store_dword [[RESULT]]
 ; EG: FRACT
 define void @fract_f32_neg(float addrspace(1)* %out, float addrspace(1)* %src) nounwind {
-  %val = load float addrspace(1)* %src, align 4
+  %val = load float, float addrspace(1)* %src, align 4
   %neg = fsub float 0.0, %val
   %fract = call float @llvm.AMDGPU.fract.f32(float %neg) nounwind readnone
   store float %fract, float addrspace(1)* %out, align 4
@@ -56,7 +56,7 @@ define void @fract_f32_neg(float addrspace(1)* %out, float addrspace(1)* %src) n
 ; GCN: buffer_store_dword [[RESULT]]
 ; EG: FRACT
 define void @fract_f32_neg_abs(float addrspace(1)* %out, float addrspace(1)* %src) nounwind {
-  %val = load float addrspace(1)* %src, align 4
+  %val = load float, float addrspace(1)* %src, align 4
   %abs = call float @llvm.fabs.f32(float %val)
   %neg = fsub float 0.0, %abs
   %fract = call float @llvm.AMDGPU.fract.f32(float %neg) nounwind readnone
diff --git a/test/CodeGen/R600/llvm.AMDGPU.imax.ll b/test/CodeGen/R600/llvm.AMDGPU.imax.ll
index ce7fca056a02..46662f96c290 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.imax.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.imax.ll
@@ -5,7 +5,7 @@
 ; SI: v_max_i32_e32
 define void @vector_imax(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 {
 main_body:
-  %load = load i32 addrspace(1)* %in, align 4
+  %load = load i32, i32 addrspace(1)* %in, align 4
   %max = call i32 @llvm.AMDGPU.imax(i32 %p0, i32 %load)
   %bc = bitcast i32 %max to float
   call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
diff --git a/test/CodeGen/R600/llvm.AMDGPU.imin.ll b/test/CodeGen/R600/llvm.AMDGPU.imin.ll
index 15cd38b19d7e..34b454e23755 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.imin.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.imin.ll
@@ -5,7 +5,7 @@
 ; SI: v_min_i32_e32
 define void @vector_imin(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 {
 main_body:
-  %load = load i32 addrspace(1)* %in, align 4
+  %load = load i32, i32 addrspace(1)* %in, align 4
   %min = call i32 @llvm.AMDGPU.imin(i32 %p0, i32 %load)
   %bc = bitcast i32 %min to float
   call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
diff --git a/test/CodeGen/R600/llvm.AMDGPU.kill.ll b/test/CodeGen/R600/llvm.AMDGPU.kill.ll
index 30b0fc2bd73b..057708e7b5cc 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.kill.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.kill.ll
@@ -18,8 +18,8 @@ main_body:
 
 ; SI-LABEL: {{^}}kill_vcc_implicit_def:
 ; SI-NOT: v_cmp_gt_f32_e32 vcc,
+; SI: v_cmp_gt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], 0, v{{[0-9]+}}
 ; SI: v_cmpx_le_f32_e32 vcc, 0, v{{[0-9]+}}
-; SI: v_cmp_lt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0
 ; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]]
 define void @kill_vcc_implicit_def([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #1 {
 entry:
diff --git a/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.f64.ll b/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.f64.ll
index 4318aeaac786..67f1d22c7178 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.f64.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.f64.ll
@@ -1,9 +1,21 @@
 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
 
 declare double @llvm.AMDGPU.rsq.clamped.f64(double) nounwind readnone
 
 ; FUNC-LABEL: {{^}}rsq_clamped_f64:
 ; SI: v_rsq_clamp_f64_e32
+
+; VI: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[2:3]
+; TODO: this constant should be folded:
+; VI: s_mov_b32 s[[ALLBITS:[0-9+]]], -1
+; VI: s_mov_b32 s[[HIGH1:[0-9+]]], 0x7fefffff
+; VI: s_mov_b32 s[[LOW1:[0-9+]]], s[[ALLBITS]]
+; VI: v_min_f64 v[0:1], [[RSQ]], s{{\[}}[[LOW1]]:[[HIGH1]]]
+; VI: s_mov_b32 s[[HIGH2:[0-9+]]], 0xffefffff
+; VI: s_mov_b32 s[[LOW2:[0-9+]]], s[[ALLBITS]]
+; VI: v_max_f64 v[0:1], v[0:1], s{{\[}}[[LOW2]]:[[HIGH2]]]
+
 define void @rsq_clamped_f64(double addrspace(1)* %out, double %src) nounwind {
   %rsq_clamped = call double @llvm.AMDGPU.rsq.clamped.f64(double %src) nounwind readnone
   store double %rsq_clamped, double addrspace(1)* %out, align 8
diff --git a/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.ll b/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.ll
index 9336baffc97f..eeff2536b232 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
 ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 
 
@@ -6,7 +7,15 @@ declare float @llvm.AMDGPU.rsq.clamped.f32(float) nounwind readnone
 
 ; FUNC-LABEL: {{^}}rsq_clamped_f32:
 ; SI: v_rsq_clamp_f32_e32
+
+; VI: v_rsq_f32_e32 [[RSQ:v[0-9]+]], {{s[0-9]+}}
+; VI: v_min_f32_e32 [[MIN:v[0-9]+]], 0x7f7fffff, [[RSQ]]
+; TODO: this constant should be folded:
+; VI: v_mov_b32_e32 [[MINFLT:v[0-9]+]], 0xff7fffff
+; VI: v_max_f32_e32 {{v[0-9]+}}, [[MIN]], [[MINFLT]]
+
 ; EG: RECIPSQRT_CLAMPED
+
 define void @rsq_clamped_f32(float addrspace(1)* %out, float %src) nounwind {
   %rsq_clamped = call float @llvm.AMDGPU.rsq.clamped.f32(float %src) nounwind readnone
   store float %rsq_clamped, float addrspace(1)* %out, align 4
diff --git a/test/CodeGen/R600/llvm.AMDGPU.tex.ll b/test/CodeGen/R600/llvm.AMDGPU.tex.ll
index aac014bde456..10206609bb57 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.tex.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.tex.ll
@@ -18,7 +18,7 @@
 ;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN
 
 define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
-   %addr = load <4 x float> addrspace(1)* %in
+   %addr = load <4 x float>, <4 x float> addrspace(1)* %in
    %res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %addr, i32 0, i32 0, i32 1)
    %res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res1, i32 0, i32 0, i32 2)
    %res3 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res2, i32 0, i32 0, i32 3)
diff --git a/test/CodeGen/R600/llvm.AMDGPU.trig_preop.ll b/test/CodeGen/R600/llvm.AMDGPU.trig_preop.ll
index 5829f7348df9..6b546a7e17c1 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.trig_preop.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.trig_preop.ll
@@ -10,8 +10,8 @@ declare double @llvm.AMDGPU.trig.preop.f64(double, i32) nounwind readnone
 ; SI: buffer_store_dwordx2 [[RESULT]],
 ; SI: s_endpgm
 define void @test_trig_preop_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
-  %a = load double addrspace(1)* %aptr, align 8
-  %b = load i32 addrspace(1)* %bptr, align 4
+  %a = load double, double addrspace(1)* %aptr, align 8
+  %b = load i32, i32 addrspace(1)* %bptr, align 4
   %result = call double @llvm.AMDGPU.trig.preop.f64(double %a, i32 %b) nounwind readnone
   store double %result, double addrspace(1)* %out, align 8
   ret void
@@ -23,7 +23,7 @@ define void @test_trig_preop_f64(double addrspace(1)* %out, double addrspace(1)*
 ; SI: buffer_store_dwordx2 [[RESULT]],
 ; SI: s_endpgm
 define void @test_trig_preop_f64_imm_segment(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind {
-  %a = load double addrspace(1)* %aptr, align 8
+  %a = load double, double addrspace(1)* %aptr, align 8
   %result = call double @llvm.AMDGPU.trig.preop.f64(double %a, i32 7) nounwind readnone
   store double %result, double addrspace(1)* %out, align 8
   ret void
diff --git a/test/CodeGen/R600/llvm.AMDGPU.umad24.ll b/test/CodeGen/R600/llvm.AMDGPU.umad24.ll
index 88613db2161f..77a073b0cb03 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.umad24.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.umad24.ll
@@ -25,12 +25,12 @@ define void @test_umad24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2
 ; SI: buffer_store_dword [[RESULT]]
 define void @commute_umad24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %out.gep = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %src0.gep = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %src2.gep = getelementptr i32 addrspace(1)* %src0.gep, i32 1
+  %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %src0.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %src2.gep = getelementptr i32, i32 addrspace(1)* %src0.gep, i32 1
 
-  %src0 = load i32 addrspace(1)* %src0.gep, align 4
-  %src2 = load i32 addrspace(1)* %src2.gep, align 4
+  %src0 = load i32, i32 addrspace(1)* %src0.gep, align 4
+  %src2 = load i32, i32 addrspace(1)* %src2.gep, align 4
   %mad = call i32 @llvm.AMDGPU.umad24(i32 %src0, i32 4, i32 %src2) nounwind readnone
   store i32 %mad, i32 addrspace(1)* %out.gep, align 4
   ret void
diff --git a/test/CodeGen/R600/llvm.AMDGPU.umax.ll b/test/CodeGen/R600/llvm.AMDGPU.umax.ll
index 4320dfe669d8..a97d103016d3 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.umax.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.umax.ll
@@ -5,7 +5,7 @@
 ; SI: v_max_u32_e32
 define void @vector_umax(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 {
 main_body:
-  %load = load i32 addrspace(1)* %in, align 4
+  %load = load i32, i32 addrspace(1)* %in, align 4
   %max = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %load)
   %bc = bitcast i32 %max to float
   call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
@@ -28,7 +28,7 @@ entry:
 ; SI-NOT: and
 ; SI: buffer_store_short [[RESULT]],
 define void @trunc_zext_umax(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind {
-  %tmp5 = load i8 addrspace(1)* %src, align 1
+  %tmp5 = load i8, i8 addrspace(1)* %src, align 1
   %tmp2 = zext i8 %tmp5 to i32
   %tmp3 = tail call i32 @llvm.AMDGPU.umax(i32 %tmp2, i32 0) nounwind readnone
   %tmp4 = trunc i32 %tmp3 to i8
diff --git a/test/CodeGen/R600/llvm.AMDGPU.umin.ll b/test/CodeGen/R600/llvm.AMDGPU.umin.ll
index e4cac33a07a7..2acd10e0c631 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.umin.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.umin.ll
@@ -5,7 +5,7 @@
 ; SI: v_min_u32_e32
 define void @vector_umin(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 {
 main_body:
-  %load = load i32 addrspace(1)* %in, align 4
+  %load = load i32, i32 addrspace(1)* %in, align 4
   %min = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %load)
   %bc = bitcast i32 %min to float
   call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
@@ -28,7 +28,7 @@ entry:
 ; SI-NOT: and
 ; SI: buffer_store_short [[RESULT]],
 define void @trunc_zext_umin(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind {
-  %tmp5 = load i8 addrspace(1)* %src, align 1
+  %tmp5 = load i8, i8 addrspace(1)* %src, align 1
   %tmp2 = zext i8 %tmp5 to i32
   %tmp3 = tail call i32 @llvm.AMDGPU.umin(i32 %tmp2, i32 0) nounwind readnone
   %tmp4 = trunc i32 %tmp3 to i8
diff --git a/test/CodeGen/R600/llvm.SI.fs.interp.ll b/test/CodeGen/R600/llvm.SI.fs.interp.ll
index 9f87a41de247..3d05da616e4e 100644
--- a/test/CodeGen/R600/llvm.SI.fs.interp.ll
+++ b/test/CodeGen/R600/llvm.SI.fs.interp.ll
@@ -1,11 +1,13 @@
-;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
-;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
+;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
+;RUN: llc < %s -march=amdgcn -mcpu=kabini -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s
+;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
 
-;CHECK-NOT: s_wqm
-;CHECK: s_mov_b32
-;CHECK: v_interp_p1_f32
-;CHECK: v_interp_p2_f32
-;CHECK: v_interp_mov_f32
+;GCN-LABEL: {{^}}main:
+;GCN-NOT: s_wqm
+;GCN: s_mov_b32
+;GCN-NEXT: v_interp_mov_f32
+;GCN: v_interp_p1_f32
+;GCN: v_interp_p2_f32
 
 define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) #0 {
 main_body:
@@ -16,7 +18,33 @@ main_body:
   ret void
 }
 
-declare void @llvm.AMDGPU.shader.type(i32)
+; Thest that v_interp_p1 uses different source and destination registers
+; on 16 bank LDS chips.
+
+; 16BANK-LABEL: {{^}}v_interp_p1_bank16_bug:
+; 16BANK-NOT: v_interp_p1_f32 [[DST:v[0-9]+]], [[DST]]
+
+define void @v_interp_p1_bank16_bug([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
+main_body:
+  %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
+  %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
+  %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
+  %25 = call float @fabs(float %22)
+  %26 = call float @fabs(float %23)
+  %27 = call float @fabs(float %24)
+  %28 = call i32 @llvm.SI.packf16(float %25, float %26)
+  %29 = bitcast i32 %28 to float
+  %30 = call i32 @llvm.SI.packf16(float %27, float 1.000000e+00)
+  %31 = bitcast i32 %30 to float
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %29, float %31, float %29, float %31)
+  ret void
+}
+
+; Function Attrs: readnone
+declare float @fabs(float) #2
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.SI.packf16(float, float) #1
 
 ; Function Attrs: nounwind readnone
 declare float @llvm.SI.fs.constant(i32, i32, i32) #1
@@ -28,3 +56,4 @@ declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float
 
 attributes #0 = { "ShaderType"="0" }
 attributes #1 = { nounwind readnone }
+attributes #2 = { readnone }
diff --git a/test/CodeGen/R600/llvm.SI.imageload.ll b/test/CodeGen/R600/llvm.SI.imageload.ll
index 35e4591bb1fa..b67716c3b665 100644
--- a/test/CodeGen/R600/llvm.SI.imageload.ll
+++ b/test/CodeGen/R600/llvm.SI.imageload.ll
@@ -88,16 +88,16 @@ define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
 ; CHECK: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}
 define void @vgpr_coords(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
 main_body:
-  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
-  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !2
-  %22 = getelementptr float addrspace(2)* %21, i32 0
-  %23 = load float addrspace(2)* %22, !tbaa !2, !invariant.load !1
-  %24 = getelementptr float addrspace(2)* %21, i32 1
-  %25 = load float addrspace(2)* %24, !tbaa !2, !invariant.load !1
-  %26 = getelementptr float addrspace(2)* %21, i32 4
-  %27 = load float addrspace(2)* %26, !tbaa !2, !invariant.load !1
-  %28 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
-  %29 = load <32 x i8> addrspace(2)* %28, !tbaa !2
+  %20 = getelementptr float addrspace(2)*, float addrspace(2)* addrspace(2)* %0, i32 0
+  %21 = load float addrspace(2)*, float addrspace(2)* addrspace(2)* %20, !tbaa !2
+  %22 = getelementptr float, float addrspace(2)* %21, i32 0
+  %23 = load float, float addrspace(2)* %22, !tbaa !2, !invariant.load !1
+  %24 = getelementptr float, float addrspace(2)* %21, i32 1
+  %25 = load float, float addrspace(2)* %24, !tbaa !2, !invariant.load !1
+  %26 = getelementptr float, float addrspace(2)* %21, i32 4
+  %27 = load float, float addrspace(2)* %26, !tbaa !2, !invariant.load !1
+  %28 = getelementptr <32 x i8>, <32 x i8> addrspace(2)* %2, i32 0
+  %29 = load <32 x i8>, <32 x i8> addrspace(2)* %28, !tbaa !2
   %30 = bitcast float %27 to i32
   %31 = bitcast float %23 to i32
   %32 = bitcast float %25 to i32
diff --git a/test/CodeGen/R600/llvm.SI.load.dword.ll b/test/CodeGen/R600/llvm.SI.load.dword.ll
index 8c8f2eed7d9d..f6c258539d5b 100644
--- a/test/CodeGen/R600/llvm.SI.load.dword.ll
+++ b/test/CodeGen/R600/llvm.SI.load.dword.ll
@@ -1,29 +1,41 @@
-;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
-;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
+; RUN: llc -march=amdgcn -mcpu=verde -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s
 
 ; Example of a simple geometry shader loading vertex attributes from the
 ; ESGS ring buffer
 
-; CHECK-LABEL: {{^}}main:
-; CHECK: buffer_load_dword
-; CHECK: buffer_load_dword
-; CHECK: buffer_load_dword
-; CHECK: buffer_load_dword
+; FIXME: Out of bounds immediate offset crashes
 
-define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32, i32, i32, i32) #0 {
+; CHECK-LABEL: {{^}}main:
+; CHECK: buffer_load_dword {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 glc slc
+; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen glc slc
+; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen glc slc
+; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen offen glc slc
+; CHECK: s_movk_i32 [[K:s[0-9]+]], 0x4d2 ; encoding
+; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, [[K]] idxen offen offset:65535 glc slc
+
+define void @main([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <32 x i8>] addrspace(2)* byval %arg2, [2 x <16 x i8>] addrspace(2)* byval %arg3, [17 x <16 x i8>] addrspace(2)* inreg %arg4, [17 x <16 x i8>] addrspace(2)* inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9) #0 {
 main_body:
-  %10 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
-  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
-  %12 = shl i32 %6, 2
-  %13 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %11, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0)
-  %14 = bitcast i32 %13 to float
-  %15 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %11, i32 %12, i32 0, i32 0, i32 1, i32 0, i32 1, i32 1, i32 0)
-  %16 = bitcast i32 %15 to float
-  %17 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %11, i32 %12, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 0)
-  %18 = bitcast i32 %17 to float
-  %19 = call i32 @llvm.SI.buffer.load.dword.i32.v2i32(<16 x i8> %11, <2 x i32> <i32 0, i32 0>, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 0)
-  %20 = bitcast i32 %19 to float
-  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %14, float %16, float %18, float %20)
+  %tmp = getelementptr [2 x <16 x i8>], [2 x <16 x i8>] addrspace(2)* %arg3, i64 0, i32 1
+  %tmp10 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
+  %tmp11 = shl i32 %arg6, 2
+  %tmp12 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0)
+  %tmp13 = bitcast i32 %tmp12 to float
+  %tmp14 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp10, i32 %tmp11, i32 0, i32 0, i32 1, i32 0, i32 1, i32 1, i32 0)
+  %tmp15 = bitcast i32 %tmp14 to float
+  %tmp16 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp10, i32 %tmp11, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 0)
+  %tmp17 = bitcast i32 %tmp16 to float
+  %tmp18 = call i32 @llvm.SI.buffer.load.dword.i32.v2i32(<16 x i8> %tmp10, <2 x i32> zeroinitializer, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 0)
+  %tmp19 = bitcast i32 %tmp18 to float
+
+  %tmp20 = call i32 @llvm.SI.buffer.load.dword.i32.v2i32(<16 x i8> %tmp10, <2 x i32> zeroinitializer, i32 0, i32 123, i32 1, i32 1, i32 1, i32 1, i32 0)
+  %tmp21 = bitcast i32 %tmp20 to float
+
+  %tmp22 = call i32 @llvm.SI.buffer.load.dword.i32.v2i32(<16 x i8> %tmp10, <2 x i32> zeroinitializer, i32 1234, i32 65535, i32 1, i32 1, i32 1, i32 1, i32 0)
+  %tmp23 = bitcast i32 %tmp22 to float
+
+  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %tmp13, float %tmp15, float %tmp17, float %tmp19)
+  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %tmp21, float %tmp23, float %tmp23, float %tmp23)
   ret void
 }
 
diff --git a/test/CodeGen/R600/llvm.SI.sendmsg.ll b/test/CodeGen/R600/llvm.SI.sendmsg.ll
index ce3800241953..09675d503355 100644
--- a/test/CodeGen/R600/llvm.SI.sendmsg.ll
+++ b/test/CodeGen/R600/llvm.SI.sendmsg.ll
@@ -2,6 +2,8 @@
 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: {{^}}main:
+; CHECK: s_mov_b32 m0, 0
+; CHECK-NOT: s_mov_b32 m0
 ; CHECK: s_sendmsg Gs(emit stream 0)
 ; CHECK: s_sendmsg Gs(cut stream 1)
 ; CHECK: s_sendmsg Gs(emit-cut stream 2)
diff --git a/test/CodeGen/R600/llvm.SI.tid.ll b/test/CodeGen/R600/llvm.SI.tid.ll
index 64efd2daf338..f6e6d7050ba7 100644
--- a/test/CodeGen/R600/llvm.SI.tid.ll
+++ b/test/CodeGen/R600/llvm.SI.tid.ll
@@ -1,7 +1,9 @@
-;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
+;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=GCN %s
+;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=GCN %s
 
-;CHECK: v_mbcnt_lo_u32_b32_e64
-;CHECK: v_mbcnt_hi_u32_b32_e32
+;GCN: v_mbcnt_lo_u32_b32_e64
+;SI: v_mbcnt_hi_u32_b32_e32
+;VI: v_mbcnt_hi_u32_b32_e64
 
 define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" {
 main_body:
diff --git a/test/CodeGen/R600/llvm.amdgpu.dp4.ll b/test/CodeGen/R600/llvm.amdgpu.dp4.ll
index 812b6a40ee59..036cd2ca82a6 100644
--- a/test/CodeGen/R600/llvm.amdgpu.dp4.ll
+++ b/test/CodeGen/R600/llvm.amdgpu.dp4.ll
@@ -3,8 +3,8 @@
 declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) nounwind readnone
 
 define void @test_dp4(float addrspace(1)* %out, <4 x float> addrspace(1)* %a, <4 x float> addrspace(1)* %b) nounwind {
-  %src0 = load <4 x float> addrspace(1)* %a, align 16
-  %src1 = load <4 x float> addrspace(1)* %b, align 16
+  %src0 = load <4 x float>, <4 x float> addrspace(1)* %a, align 16
+  %src1 = load <4 x float>, <4 x float> addrspace(1)* %b, align 16
   %dp4 = call float @llvm.AMDGPU.dp4(<4 x float> %src0, <4 x float> %src1) nounwind readnone
   store float %dp4, float addrspace(1)* %out, align 4
   ret void
diff --git a/test/CodeGen/R600/llvm.floor.ll b/test/CodeGen/R600/llvm.floor.ll
deleted file mode 100644
index 1016ff75ce9b..000000000000
--- a/test/CodeGen/R600/llvm.floor.ll
+++ /dev/null
@@ -1,54 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
-
-; R600-CHECK: {{^}}f32:
-; R600-CHECK: FLOOR
-; SI-CHECK: {{^}}f32:
-; SI-CHECK: v_floor_f32_e32
-define void @f32(float addrspace(1)* %out, float %in) {
-entry:
-  %0 = call float @llvm.floor.f32(float %in)
-  store float %0, float addrspace(1)* %out
-  ret void
-}
-
-; R600-CHECK: {{^}}v2f32:
-; R600-CHECK: FLOOR
-; R600-CHECK: FLOOR
-; SI-CHECK: {{^}}v2f32:
-; SI-CHECK: v_floor_f32_e32
-; SI-CHECK: v_floor_f32_e32
-define void @v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
-entry:
-  %0 = call <2 x float> @llvm.floor.v2f32(<2 x float> %in)
-  store <2 x float> %0, <2 x float> addrspace(1)* %out
-  ret void
-}
-
-; R600-CHECK: {{^}}v4f32:
-; R600-CHECK: FLOOR
-; R600-CHECK: FLOOR
-; R600-CHECK: FLOOR
-; R600-CHECK: FLOOR
-; SI-CHECK: {{^}}v4f32:
-; SI-CHECK: v_floor_f32_e32
-; SI-CHECK: v_floor_f32_e32
-; SI-CHECK: v_floor_f32_e32
-; SI-CHECK: v_floor_f32_e32
-define void @v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
-entry:
-  %0 = call <4 x float> @llvm.floor.v4f32(<4 x float> %in)
-  store <4 x float> %0, <4 x float> addrspace(1)* %out
-  ret void
-}
-
-; Function Attrs: nounwind readonly
-declare float @llvm.floor.f32(float) #0
-
-; Function Attrs: nounwind readonly
-declare <2 x float> @llvm.floor.v2f32(<2 x float>) #0
-
-; Function Attrs: nounwind readonly
-declare <4 x float> @llvm.floor.v4f32(<4 x float>) #0
-
-attributes #0 = { nounwind readonly }
diff --git a/test/CodeGen/R600/llvm.memcpy.ll b/test/CodeGen/R600/llvm.memcpy.ll
index d6f5f6275acf..e491732cf9c5 100644
--- a/test/CodeGen/R600/llvm.memcpy.ll
+++ b/test/CodeGen/R600/llvm.memcpy.ll
@@ -7,39 +7,23 @@ declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace
 
 ; FUNC-LABEL: {{^}}test_small_memcpy_i64_lds_to_lds_align1:
 ; SI: ds_read_u8
-; SI: ds_write_b8
 ; SI: ds_read_u8
-; SI: ds_write_b8
 ; SI: ds_read_u8
-; SI: ds_write_b8
 ; SI: ds_read_u8
-; SI: ds_write_b8
 ; SI: ds_read_u8
-; SI: ds_write_b8
-
 ; SI: ds_read_u8
-; SI: ds_write_b8
 ; SI: ds_read_u8
-; SI: ds_write_b8
 ; SI: ds_read_u8
-; SI: ds_write_b8
+
 ; SI: ds_read_u8
-; SI: ds_write_b8
 ; SI: ds_read_u8
-; SI: ds_write_b8
-
 ; SI: ds_read_u8
-; SI: ds_write_b8
 ; SI: ds_read_u8
-; SI: ds_write_b8
 ; SI: ds_read_u8
-; SI: ds_write_b8
 ; SI: ds_read_u8
-; SI: ds_write_b8
 ; SI: ds_read_u8
 ; SI: ds_read_u8
 
-
 ; SI: ds_read_u8
 ; SI: ds_read_u8
 ; SI: ds_read_u8
@@ -66,6 +50,14 @@ declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace
 ; SI: ds_write_b8
 ; SI: ds_write_b8
 ; SI: ds_write_b8
+
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
 ; SI: ds_write_b8
 
 ; SI: ds_write_b8
@@ -76,6 +68,14 @@ declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace
 ; SI: ds_write_b8
 ; SI: ds_write_b8
 ; SI: ds_write_b8
+
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
 ; SI: ds_write_b8
 
 ; SI: s_endpgm
diff --git a/test/CodeGen/R600/llvm.rint.f64.ll b/test/CodeGen/R600/llvm.rint.f64.ll
index 2c926341f78a..c63fb1727940 100644
--- a/test/CodeGen/R600/llvm.rint.f64.ll
+++ b/test/CodeGen/R600/llvm.rint.f64.ll
@@ -1,3 +1,4 @@
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
diff --git a/test/CodeGen/R600/llvm.round.f64.ll b/test/CodeGen/R600/llvm.round.f64.ll
new file mode 100644
index 000000000000..3d0f57e33280
--- /dev/null
+++ b/test/CodeGen/R600/llvm.round.f64.ll
@@ -0,0 +1,74 @@
+; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+
+; FUNC-LABEL: {{^}}round_f64:
+; SI: s_endpgm
+define void @round_f64(double addrspace(1)* %out, double %x) #0 {
+  %result = call double @llvm.round.f64(double %x) #1
+  store double %result, double addrspace(1)* %out
+  ret void
+}
+
+; This is a pretty large function, so just test a few of the
+; instructions that are necessary.
+
+; FUNC-LABEL: {{^}}v_round_f64:
+; SI: buffer_load_dwordx2
+; SI: v_bfe_u32 [[EXP:v[0-9]+]], v{{[0-9]+}}, 20, 11
+
+; SI-DAG: v_not_b32_e32
+; SI-DAG: v_not_b32_e32
+
+; SI-DAG: v_cmp_eq_i32
+
+; SI-DAG: s_mov_b32 [[BFIMASK:s[0-9]+]], 0x7fffffff
+; SI-DAG: v_cmp_gt_i32_e64
+; SI-DAG: v_bfi_b32 [[COPYSIGN:v[0-9]+]], [[BFIMASK]]
+
+; SI-DAG: v_cmp_gt_i32_e64
+
+
+; SI: buffer_store_dwordx2
+; SI: s_endpgm
+define void @v_round_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
+  %tid = call i32 @llvm.r600.read.tidig.x() #1
+  %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
+  %out.gep = getelementptr double, double addrspace(1)* %out, i32 %tid
+  %x = load double, double addrspace(1)* %gep
+  %result = call double @llvm.round.f64(double %x) #1
+  store double %result, double addrspace(1)* %out.gep
+  ret void
+}
+
+; FUNC-LABEL: {{^}}round_v2f64:
+; SI: s_endpgm
+define void @round_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) #0 {
+  %result = call <2 x double> @llvm.round.v2f64(<2 x double> %in) #1
+  store <2 x double> %result, <2 x double> addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}round_v4f64:
+; SI: s_endpgm
+define void @round_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) #0 {
+  %result = call <4 x double> @llvm.round.v4f64(<4 x double> %in) #1
+  store <4 x double> %result, <4 x double> addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}round_v8f64:
+; SI: s_endpgm
+define void @round_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %in) #0 {
+  %result = call <8 x double> @llvm.round.v8f64(<8 x double> %in) #1
+  store <8 x double> %result, <8 x double> addrspace(1)* %out
+  ret void
+}
+
+declare i32 @llvm.r600.read.tidig.x() #1
+
+declare double @llvm.round.f64(double) #1
+declare <2 x double> @llvm.round.v2f64(<2 x double>) #1
+declare <4 x double> @llvm.round.v4f64(<4 x double>) #1
+declare <8 x double> @llvm.round.v8f64(<8 x double>) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
diff --git a/test/CodeGen/R600/llvm.round.ll b/test/CodeGen/R600/llvm.round.ll
index bedf4ba72ae4..f5f124d915a5 100644
--- a/test/CodeGen/R600/llvm.round.ll
+++ b/test/CodeGen/R600/llvm.round.ll
@@ -1,17 +1,28 @@
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s --check-prefix=R600 --check-prefix=FUNC
-
-; FUNC-LABEL: {{^}}f32:
-; R600: FRACT {{.*}}, [[ARG:KC[0-9]\[[0-9]+\]\.[XYZW]]]
-; R600-DAG: ADD  {{.*}}, -0.5
-; R600-DAG: CEIL {{.*}} [[ARG]]
-; R600-DAG: FLOOR {{.*}} [[ARG]]
-; R600-DAG: CNDGE
-; R600-DAG: CNDGT
-; R600: CNDGE {{[^,]+}}, [[ARG]]
-define void @f32(float addrspace(1)* %out, float %in) {
-entry:
-  %0 = call float @llvm.round.f32(float %in)
-  store float %0, float addrspace(1)* %out
+; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
+
+; FUNC-LABEL: {{^}}round_f32:
+; SI-DAG: s_load_dword [[SX:s[0-9]+]]
+; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0x7fffffff
+; SI: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[SX]]
+; SI: v_sub_f32_e32 [[SUB:v[0-9]+]], [[SX]], [[TRUNC]]
+; SI: v_mov_b32_e32 [[VX:v[0-9]+]], [[SX]]
+; SI: v_bfi_b32 [[COPYSIGN:v[0-9]+]], [[K]], 1.0, [[VX]]
+; SI: v_cmp_le_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], 0.5, |[[SUB]]|
+; SI: v_cndmask_b32_e64 [[SEL:v[0-9]+]], 0, [[VX]], [[CMP]]
+; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], [[SEL]], [[TRUNC]]
+; SI: buffer_store_dword [[RESULT]]
+
+; R600: TRUNC {{.*}}, [[ARG:KC[0-9]\[[0-9]+\]\.[XYZW]]]
+; R600-DAG: ADD  {{.*}},
+; R600-DAG: BFI_INT
+; R600-DAG: SETGE
+; R600-DAG: CNDE
+; R600-DAG: ADD
+define void @round_f32(float addrspace(1)* %out, float %x) #0 {
+  %result = call float @llvm.round.f32(float %x) #1
+  store float %result, float addrspace(1)* %out
   ret void
 }
 
@@ -20,24 +31,37 @@ entry:
 ; a test for the scalar case, so the vector tests just check that the
 ; compiler doesn't crash.
 
-; FUNC-LABEL: v2f32
+; FUNC-LABEL: {{^}}round_v2f32:
+; SI: s_endpgm
 ; R600: CF_END
-define void @v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
-entry:
-  %0 = call <2 x float> @llvm.round.v2f32(<2 x float> %in)
-  store <2 x float> %0, <2 x float> addrspace(1)* %out
+define void @round_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) #0 {
+  %result = call <2 x float> @llvm.round.v2f32(<2 x float> %in) #1
+  store <2 x float> %result, <2 x float> addrspace(1)* %out
   ret void
 }
 
-; FUNC-LABEL: v4f32
+; FUNC-LABEL: {{^}}round_v4f32:
+; SI: s_endpgm
 ; R600: CF_END
-define void @v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
-entry:
-  %0 = call <4 x float> @llvm.round.v4f32(<4 x float> %in)
-  store <4 x float> %0, <4 x float> addrspace(1)* %out
+define void @round_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) #0 {
+  %result = call <4 x float> @llvm.round.v4f32(<4 x float> %in) #1
+  store <4 x float> %result, <4 x float> addrspace(1)* %out
   ret void
 }
 
-declare float @llvm.round.f32(float)
-declare <2 x float> @llvm.round.v2f32(<2 x float>)
-declare <4 x float> @llvm.round.v4f32(<4 x float>)
+; FUNC-LABEL: {{^}}round_v8f32:
+; SI: s_endpgm
+; R600: CF_END
+define void @round_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %in) #0 {
+  %result = call <8 x float> @llvm.round.v8f32(<8 x float> %in) #1
+  store <8 x float> %result, <8 x float> addrspace(1)* %out
+  ret void
+}
+
+declare float @llvm.round.f32(float) #1
+declare <2 x float> @llvm.round.v2f32(<2 x float>) #1
+declare <4 x float> @llvm.round.v4f32(<4 x float>) #1
+declare <8 x float> @llvm.round.v8f32(<8 x float>) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
diff --git a/test/CodeGen/R600/llvm.sqrt.ll b/test/CodeGen/R600/llvm.sqrt.ll
index 1f8df891654b..c6da047f5392 100644
--- a/test/CodeGen/R600/llvm.sqrt.ll
+++ b/test/CodeGen/R600/llvm.sqrt.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=r600 --mcpu=redwood | FileCheck %s --check-prefix=R600
-; RUN: llc < %s -march=r600 --mcpu=SI -verify-machineinstrs| FileCheck %s --check-prefix=SI
-; RUN: llc < %s -march=r600 --mcpu=tonga -verify-machineinstrs| FileCheck %s --check-prefix=SI
+; RUN: llc < %s -march=amdgcn --mcpu=SI -verify-machineinstrs| FileCheck %s --check-prefix=SI
+; RUN: llc < %s -march=amdgcn --mcpu=tonga -verify-machineinstrs| FileCheck %s --check-prefix=SI
 
 ; R600-LABEL: {{^}}sqrt_f32:
 ; R600: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].Z
@@ -50,6 +50,56 @@ entry:
   ret void
 }
 
+; SI-LABEL: {{^}}elim_redun_check:
+; SI: v_sqrt_f32_e32
+; SI-NOT: v_cndmask
+define void @elim_redun_check(float addrspace(1)* %out, float %in) {
+entry:
+  %sqrt = call float @llvm.sqrt.f32(float %in)
+  %cmp = fcmp olt float %in, -0.000000e+00
+  %res = select i1 %cmp, float 0x7FF8000000000000, float %sqrt
+  store float %res, float addrspace(1)* %out
+  ret void
+}
+
+; SI-LABEL: {{^}}elim_redun_check_ult:
+; SI: v_sqrt_f32_e32
+; SI-NOT: v_cndmask
+define void @elim_redun_check_ult(float addrspace(1)* %out, float %in) {
+entry:
+  %sqrt = call float @llvm.sqrt.f32(float %in)
+  %cmp = fcmp ult float %in, -0.000000e+00
+  %res = select i1 %cmp, float 0x7FF8000000000000, float %sqrt
+  store float %res, float addrspace(1)* %out
+  ret void
+}
+
+; SI-LABEL: {{^}}elim_redun_check_v2:
+; SI: v_sqrt_f32_e32
+; SI: v_sqrt_f32_e32
+; SI-NOT: v_cndmask
+define void @elim_redun_check_v2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
+entry:
+  %sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in)
+  %cmp = fcmp olt <2 x float> %in, <float -0.000000e+00, float -0.000000e+00>
+  %res = select <2 x i1> %cmp, <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>, <2 x float> %sqrt
+  store <2 x float> %res, <2 x float> addrspace(1)* %out
+  ret void
+}
+
+; SI-LABEL: {{^}}elim_redun_check_v2_ult
+; SI: v_sqrt_f32_e32
+; SI: v_sqrt_f32_e32
+; SI-NOT: v_cndmask
+define void @elim_redun_check_v2_ult(<2 x float> addrspace(1)* %out, <2 x float> %in) {
+entry:
+  %sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in)
+  %cmp = fcmp ult <2 x float> %in, <float -0.000000e+00, float -0.000000e+00>
+  %res = select <2 x i1> %cmp, <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>, <2 x float> %sqrt
+  store <2 x float> %res, <2 x float> addrspace(1)* %out
+  ret void
+}
+
 declare float @llvm.sqrt.f32(float %in)
 declare <2 x float> @llvm.sqrt.v2f32(<2 x float> %in)
 declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %in)
diff --git a/test/CodeGen/R600/llvm.trunc.ll b/test/CodeGen/R600/llvm.trunc.ll
deleted file mode 100644
index 5585477ef294..000000000000
--- a/test/CodeGen/R600/llvm.trunc.ll
+++ /dev/null
@@ -1,13 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; CHECK-LABEL: {{^}}trunc_f32:
-; CHECK: TRUNC
-
-define void @trunc_f32(float addrspace(1)* %out, float %in) {
-entry:
-  %0 = call float @llvm.trunc.f32(float %in)
-  store float %0, float  addrspace(1)* %out
-  ret void
-}
-
-declare float @llvm.trunc.f32(float)
diff --git a/test/CodeGen/R600/load-i1.ll b/test/CodeGen/R600/load-i1.ll
index 315c0a37ebf3..0ca49fde3e7b 100644
--- a/test/CodeGen/R600/load-i1.ll
+++ b/test/CodeGen/R600/load-i1.ll
@@ -11,7 +11,7 @@
 ; EG: VTX_READ_8
 ; EG: AND_INT
 define void @global_copy_i1_to_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   store i1 %load, i1 addrspace(1)* %out, align 1
   ret void
 }
@@ -26,7 +26,7 @@ define void @global_copy_i1_to_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) n
 ; EG: AND_INT
 ; EG: LDS_BYTE_WRITE
 define void @local_copy_i1_to_i1(i1 addrspace(3)* %out, i1 addrspace(3)* %in) nounwind {
-  %load = load i1 addrspace(3)* %in
+  %load = load i1, i1 addrspace(3)* %in
   store i1 %load, i1 addrspace(3)* %out, align 1
   ret void
 }
@@ -40,7 +40,7 @@ define void @local_copy_i1_to_i1(i1 addrspace(3)* %out, i1 addrspace(3)* %in) no
 ; EG: VTX_READ_8
 ; EG: AND_INT
 define void @constant_copy_i1_to_i1(i1 addrspace(1)* %out, i1 addrspace(2)* %in) nounwind {
-  %load = load i1 addrspace(2)* %in
+  %load = load i1, i1 addrspace(2)* %in
   store i1 %load, i1 addrspace(1)* %out, align 1
   ret void
 }
@@ -54,7 +54,7 @@ define void @constant_copy_i1_to_i1(i1 addrspace(1)* %out, i1 addrspace(2)* %in)
 ; EG: VTX_READ_8
 ; EG: BFE_INT
 define void @global_sextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = sext i1 %load to i32
   store i32 %ext, i32 addrspace(1)* %out, align 4
   ret void
@@ -66,7 +66,7 @@ define void @global_sextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)*
 ; SI: s_endpgm
 
 define void @global_zextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = zext i1 %load to i32
   store i32 %ext, i32 addrspace(1)* %out, align 4
   ret void
@@ -78,7 +78,7 @@ define void @global_zextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)*
 ; SI: buffer_store_dwordx2
 ; SI: s_endpgm
 define void @global_sextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = sext i1 %load to i64
   store i64 %ext, i64 addrspace(1)* %out, align 4
   ret void
@@ -90,7 +90,7 @@ define void @global_sextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)*
 ; SI: buffer_store_dwordx2
 ; SI: s_endpgm
 define void @global_zextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = zext i1 %load to i64
   store i64 %ext, i64 addrspace(1)* %out, align 4
   ret void
diff --git a/test/CodeGen/R600/load-input-fold.ll b/test/CodeGen/R600/load-input-fold.ll
index 265fa9bfeb42..1daf0e6527b9 100644
--- a/test/CodeGen/R600/load-input-fold.ll
+++ b/test/CodeGen/R600/load-input-fold.ll
@@ -14,71 +14,71 @@ main_body:
   %9 = extractelement <4 x float> %reg3, i32 1
   %10 = extractelement <4 x float> %reg3, i32 2
   %11 = extractelement <4 x float> %reg3, i32 3
-  %12 = load <4 x float> addrspace(8)* null
+  %12 = load <4 x float>, <4 x float> addrspace(8)* null
   %13 = extractelement <4 x float> %12, i32 0
   %14 = fmul float %0, %13
-  %15 = load <4 x float> addrspace(8)* null
+  %15 = load <4 x float>, <4 x float> addrspace(8)* null
   %16 = extractelement <4 x float> %15, i32 1
   %17 = fmul float %0, %16
-  %18 = load <4 x float> addrspace(8)* null
+  %18 = load <4 x float>, <4 x float> addrspace(8)* null
   %19 = extractelement <4 x float> %18, i32 2
   %20 = fmul float %0, %19
-  %21 = load <4 x float> addrspace(8)* null
+  %21 = load <4 x float>, <4 x float> addrspace(8)* null
   %22 = extractelement <4 x float> %21, i32 3
   %23 = fmul float %0, %22
-  %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %24 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %25 = extractelement <4 x float> %24, i32 0
   %26 = fmul float %1, %25
   %27 = fadd float %26, %14
-  %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %28 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %29 = extractelement <4 x float> %28, i32 1
   %30 = fmul float %1, %29
   %31 = fadd float %30, %17
-  %32 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %32 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %33 = extractelement <4 x float> %32, i32 2
   %34 = fmul float %1, %33
   %35 = fadd float %34, %20
-  %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %36 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %37 = extractelement <4 x float> %36, i32 3
   %38 = fmul float %1, %37
   %39 = fadd float %38, %23
-  %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %40 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %41 = extractelement <4 x float> %40, i32 0
   %42 = fmul float %2, %41
   %43 = fadd float %42, %27
-  %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %44 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %45 = extractelement <4 x float> %44, i32 1
   %46 = fmul float %2, %45
   %47 = fadd float %46, %31
-  %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %48 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %49 = extractelement <4 x float> %48, i32 2
   %50 = fmul float %2, %49
   %51 = fadd float %50, %35
-  %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %52 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %53 = extractelement <4 x float> %52, i32 3
   %54 = fmul float %2, %53
   %55 = fadd float %54, %39
-  %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+  %56 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
   %57 = extractelement <4 x float> %56, i32 0
   %58 = fmul float %3, %57
   %59 = fadd float %58, %43
-  %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+  %60 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
   %61 = extractelement <4 x float> %60, i32 1
   %62 = fmul float %3, %61
   %63 = fadd float %62, %47
-  %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+  %64 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
   %65 = extractelement <4 x float> %64, i32 2
   %66 = fmul float %3, %65
   %67 = fadd float %66, %51
-  %68 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+  %68 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
   %69 = extractelement <4 x float> %68, i32 3
   %70 = fmul float %3, %69
   %71 = fadd float %70, %55
-  %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+  %72 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
   %73 = extractelement <4 x float> %72, i32 0
-  %74 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+  %74 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
   %75 = extractelement <4 x float> %74, i32 1
-  %76 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+  %76 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
   %77 = extractelement <4 x float> %76, i32 2
   %78 = insertelement <4 x float> undef, float %4, i32 0
   %79 = insertelement <4 x float> %78, float %5, i32 1
diff --git a/test/CodeGen/R600/load.ll b/test/CodeGen/R600/load.ll
index b71b7cb24c49..93b1b51a0d07 100644
--- a/test/CodeGen/R600/load.ll
+++ b/test/CodeGen/R600/load.ll
@@ -13,7 +13,7 @@
 
 ; SI: buffer_load_ubyte v{{[0-9]+}},
 define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
-  %1 = load i8 addrspace(1)* %in
+  %1 = load i8, i8 addrspace(1)* %in
   %2 = zext i8 %1 to i32
   store i32 %2, i32 addrspace(1)* %out
   ret void
@@ -21,14 +21,12 @@ define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
 
 ; FUNC-LABEL: {{^}}load_i8_sext:
 ; R600: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
-; R600: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
-; R600: 24
-; R600: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
-; R600: 24
+; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
+; R600: 8
 ; SI: buffer_load_sbyte
 define void @load_i8_sext(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
 entry:
-  %0 = load i8 addrspace(1)* %in
+  %0 = load i8, i8 addrspace(1)* %in
   %1 = sext i8 %0 to i32
   store i32 %1, i32 addrspace(1)* %out
   ret void
@@ -41,7 +39,7 @@ entry:
 ; SI: buffer_load_ubyte
 define void @load_v2i8(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) {
 entry:
-  %0 = load <2 x i8> addrspace(1)* %in
+  %0 = load <2 x i8>, <2 x i8> addrspace(1)* %in
   %1 = zext <2 x i8> %0 to <2 x i32>
   store <2 x i32> %1, <2 x i32> addrspace(1)* %out
   ret void
@@ -50,19 +48,16 @@ entry:
 ; FUNC-LABEL: {{^}}load_v2i8_sext:
 ; R600-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]]
 ; R600-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
-; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]]
-; R600-DAG: 24
-; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]]
-; R600-DAG: 24
-; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]]
-; R600-DAG: 24
-; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]]
-; R600-DAG: 24
+; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal
+; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal
+; R600-DAG: 8
+; R600-DAG: 8
+
 ; SI: buffer_load_sbyte
 ; SI: buffer_load_sbyte
 define void @load_v2i8_sext(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) {
 entry:
-  %0 = load <2 x i8> addrspace(1)* %in
+  %0 = load <2 x i8>, <2 x i8> addrspace(1)* %in
   %1 = sext <2 x i8> %0 to <2 x i32>
   store <2 x i32> %1, <2 x i32> addrspace(1)* %out
   ret void
@@ -79,7 +74,7 @@ entry:
 ; SI: buffer_load_ubyte
 define void @load_v4i8(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) {
 entry:
-  %0 = load <4 x i8> addrspace(1)* %in
+  %0 = load <4 x i8>, <4 x i8> addrspace(1)* %in
   %1 = zext <4 x i8> %0 to <4 x i32>
   store <4 x i32> %1, <4 x i32> addrspace(1)* %out
   ret void
@@ -90,29 +85,21 @@ entry:
 ; R600-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
 ; R600-DAG: VTX_READ_8 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]]
 ; R600-DAG: VTX_READ_8 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]]
-; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]]
-; R600-DAG: 24
-; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]]
-; R600-DAG: 24
-; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]]
-; R600-DAG: 24
-; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]]
-; R600-DAG: 24
-; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Z_CHAN:[XYZW]]], [[DST_Z]]
-; R600-DAG: 24
-; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Z_CHAN]]
-; R600-DAG: 24
-; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_W_CHAN:[XYZW]]], [[DST_W]]
-; R600-DAG: 24
-; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_W_CHAN]]
-; R600-DAG: 24
+; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal
+; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal
+; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Z]], 0.0, literal
+; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_W]], 0.0, literal
+; R600-DAG: 8
+; R600-DAG: 8
+; R600-DAG: 8
+; R600-DAG: 8
 ; SI: buffer_load_sbyte
 ; SI: buffer_load_sbyte
 ; SI: buffer_load_sbyte
 ; SI: buffer_load_sbyte
 define void @load_v4i8_sext(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) {
 entry:
-  %0 = load <4 x i8> addrspace(1)* %in
+  %0 = load <4 x i8>, <4 x i8> addrspace(1)* %in
   %1 = sext <4 x i8> %0 to <4 x i32>
   store <4 x i32> %1, <4 x i32> addrspace(1)* %out
   ret void
@@ -124,7 +111,7 @@ entry:
 ; SI: buffer_load_ushort
 define void @load_i16(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
 entry:
-  %0 = load i16	 addrspace(1)* %in
+  %0 = load i16	, i16	 addrspace(1)* %in
   %1 = zext i16 %0 to i32
   store i32 %1, i32 addrspace(1)* %out
   ret void
@@ -132,14 +119,12 @@ entry:
 
 ; FUNC-LABEL: {{^}}load_i16_sext:
 ; R600: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]]
-; R600: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
-; R600: 16
-; R600: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
+; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
 ; R600: 16
 ; SI: buffer_load_sshort
 define void @load_i16_sext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
 entry:
-  %0 = load i16 addrspace(1)* %in
+  %0 = load i16, i16 addrspace(1)* %in
   %1 = sext i16 %0 to i32
   store i32 %1, i32 addrspace(1)* %out
   ret void
@@ -152,7 +137,7 @@ entry:
 ; SI: buffer_load_ushort
 define void @load_v2i16(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) {
 entry:
-  %0 = load <2 x i16> addrspace(1)* %in
+  %0 = load <2 x i16>, <2 x i16> addrspace(1)* %in
   %1 = zext <2 x i16> %0 to <2 x i32>
   store <2 x i32> %1, <2 x i32> addrspace(1)* %out
   ret void
@@ -161,19 +146,15 @@ entry:
 ; FUNC-LABEL: {{^}}load_v2i16_sext:
 ; R600-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]]
 ; R600-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
-; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]]
-; R600-DAG: 16
-; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]]
+; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal
+; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal
 ; R600-DAG: 16
-; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]]
-; R600-DAG: 16
-; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]]
 ; R600-DAG: 16
 ; SI: buffer_load_sshort
 ; SI: buffer_load_sshort
 define void @load_v2i16_sext(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) {
 entry:
-  %0 = load <2 x i16> addrspace(1)* %in
+  %0 = load <2 x i16>, <2 x i16> addrspace(1)* %in
   %1 = sext <2 x i16> %0 to <2 x i32>
   store <2 x i32> %1, <2 x i32> addrspace(1)* %out
   ret void
@@ -190,7 +171,7 @@ entry:
 ; SI: buffer_load_ushort
 define void @load_v4i16(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) {
 entry:
-  %0 = load <4 x i16> addrspace(1)* %in
+  %0 = load <4 x i16>, <4 x i16> addrspace(1)* %in
   %1 = zext <4 x i16> %0 to <4 x i32>
   store <4 x i32> %1, <4 x i32> addrspace(1)* %out
   ret void
@@ -201,21 +182,13 @@ entry:
 ; R600-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
 ; R600-DAG: VTX_READ_16 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]]
 ; R600-DAG: VTX_READ_16 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]]
-; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]]
-; R600-DAG: 16
-; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]]
+; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal
+; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal
+; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Z]], 0.0, literal
+; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_W]], 0.0, literal
 ; R600-DAG: 16
-; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]]
 ; R600-DAG: 16
-; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]]
 ; R600-DAG: 16
-; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Z_CHAN:[XYZW]]], [[DST_Z]]
-; R600-DAG: 16
-; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Z_CHAN]]
-; R600-DAG: 16
-; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_W_CHAN:[XYZW]]], [[DST_W]]
-; R600-DAG: 16
-; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_W_CHAN]]
 ; R600-DAG: 16
 ; SI: buffer_load_sshort
 ; SI: buffer_load_sshort
@@ -223,7 +196,7 @@ entry:
 ; SI: buffer_load_sshort
 define void @load_v4i16_sext(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) {
 entry:
-  %0 = load <4 x i16> addrspace(1)* %in
+  %0 = load <4 x i16>, <4 x i16> addrspace(1)* %in
   %1 = sext <4 x i16> %0 to <4 x i32>
   store <4 x i32> %1, <4 x i32> addrspace(1)* %out
   ret void
@@ -236,7 +209,7 @@ entry:
 ; SI: buffer_load_dword v{{[0-9]+}}
 define void @load_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 entry:
-  %0 = load i32 addrspace(1)* %in
+  %0 = load i32, i32 addrspace(1)* %in
   store i32 %0, i32 addrspace(1)* %out
   ret void
 }
@@ -248,7 +221,7 @@ entry:
 ; SI: buffer_load_dword v{{[0-9]+}}
 define void @load_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
 entry:
-  %0 = load float addrspace(1)* %in
+  %0 = load float, float addrspace(1)* %in
   store float %0, float addrspace(1)* %out
   ret void
 }
@@ -260,7 +233,7 @@ entry:
 ; SI: buffer_load_dwordx2
 define void @load_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) {
 entry:
-  %0 = load <2 x float> addrspace(1)* %in
+  %0 = load <2 x float>, <2 x float> addrspace(1)* %in
   store <2 x float> %0, <2 x float> addrspace(1)* %out
   ret void
 }
@@ -270,7 +243,7 @@ entry:
 ; SI: buffer_load_dwordx2
 define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
 entry:
-  %0 = load i64 addrspace(1)* %in
+  %0 = load i64, i64 addrspace(1)* %in
   store i64 %0, i64 addrspace(1)* %out
   ret void
 }
@@ -284,7 +257,7 @@ entry:
 
 define void @load_i64_sext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
 entry:
-  %0 = load i32 addrspace(1)* %in
+  %0 = load i32, i32 addrspace(1)* %in
   %1 = sext i32 %0 to i64
   store i64 %1, i64 addrspace(1)* %out
   ret void
@@ -295,7 +268,7 @@ entry:
 ; R600: MEM_RAT
 define void @load_i64_zext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
 entry:
-  %0 = load i32 addrspace(1)* %in
+  %0 = load i32, i32 addrspace(1)* %in
   %1 = zext i32 %0 to i64
   store i64 %1, i64 addrspace(1)* %out
   ret void
@@ -315,7 +288,7 @@ entry:
 ; SI: buffer_load_dword
 define void @load_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) {
 entry:
-  %0 = load <8 x i32> addrspace(1)* %in
+  %0 = load <8 x i32>, <8 x i32> addrspace(1)* %in
   store <8 x i32> %0, <8 x i32> addrspace(1)* %out
   ret void
 }
@@ -344,7 +317,7 @@ entry:
 ; SI: buffer_load_dword
 define void @load_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) {
 entry:
-  %0 = load <16 x i32> addrspace(1)* %in
+  %0 = load <16 x i32>, <16 x i32> addrspace(1)* %in
   store <16 x i32> %0, <16 x i32> addrspace(1)* %out
   ret void
 }
@@ -356,14 +329,12 @@ entry:
 ; Load a sign-extended i8 value
 ; FUNC-LABEL: {{^}}load_const_i8_sext:
 ; R600: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
-; R600: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
-; R600: 24
-; R600: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
-; R600: 24
+; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
+; R600: 8
 ; SI: buffer_load_sbyte v{{[0-9]+}},
 define void @load_const_i8_sext(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
 entry:
-  %0 = load i8 addrspace(2)* %in
+  %0 = load i8, i8 addrspace(2)* %in
   %1 = sext i8 %0 to i32
   store i32 %1, i32 addrspace(1)* %out
   ret void
@@ -375,7 +346,7 @@ entry:
 ; SI: buffer_load_ubyte v{{[0-9]+}},
 define void @load_const_i8_aligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
 entry:
-  %0 = load i8 addrspace(2)* %in
+  %0 = load i8, i8 addrspace(2)* %in
   %1 = zext i8 %0 to i32
   store i32 %1, i32 addrspace(1)* %out
   ret void
@@ -387,8 +358,8 @@ entry:
 ; SI: buffer_load_ubyte v{{[0-9]+}},
 define void @load_const_i8_unaligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
 entry:
-  %0 = getelementptr i8 addrspace(2)* %in, i32 1
-  %1 = load i8 addrspace(2)* %0
+  %0 = getelementptr i8, i8 addrspace(2)* %in, i32 1
+  %1 = load i8, i8 addrspace(2)* %0
   %2 = zext i8 %1 to i32
   store i32 %2, i32 addrspace(1)* %out
   ret void
@@ -397,14 +368,12 @@ entry:
 ; Load a sign-extended i16 value
 ; FUNC-LABEL: {{^}}load_const_i16_sext:
 ; R600: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]]
-; R600: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
-; R600: 16
-; R600: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
+; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
 ; R600: 16
 ; SI: buffer_load_sshort
 define void @load_const_i16_sext(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
 entry:
-  %0 = load i16 addrspace(2)* %in
+  %0 = load i16, i16 addrspace(2)* %in
   %1 = sext i16 %0 to i32
   store i32 %1, i32 addrspace(1)* %out
   ret void
@@ -416,7 +385,7 @@ entry:
 ; SI: buffer_load_ushort
 define void @load_const_i16_aligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
 entry:
-  %0 = load i16 addrspace(2)* %in
+  %0 = load i16, i16 addrspace(2)* %in
   %1 = zext i16 %0 to i32
   store i32 %1, i32 addrspace(1)* %out
   ret void
@@ -428,8 +397,8 @@ entry:
 ; SI: buffer_load_ushort
 define void @load_const_i16_unaligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
 entry:
-  %0 = getelementptr i16 addrspace(2)* %in, i32 1
-  %1 = load i16 addrspace(2)* %0
+  %0 = getelementptr i16, i16 addrspace(2)* %in, i32 1
+  %1 = load i16, i16 addrspace(2)* %0
   %2 = zext i16 %1 to i32
   store i32 %2, i32 addrspace(1)* %out
   ret void
@@ -442,7 +411,7 @@ entry:
 ; SI: s_load_dword s{{[0-9]+}}
 define void @load_const_addrspace_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) {
 entry:
-  %0 = load i32 addrspace(2)* %in
+  %0 = load i32, i32 addrspace(2)* %in
   store i32 %0, i32 addrspace(1)* %out
   ret void
 }
@@ -453,7 +422,7 @@ entry:
 
 ; SI: s_load_dword s{{[0-9]+}}
 define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(2)* %in) {
-  %1 = load float addrspace(2)* %in
+  %1 = load float, float addrspace(2)* %in
   store float %1, float addrspace(1)* %out
   ret void
 }
@@ -469,7 +438,7 @@ define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(
 ; SI: s_mov_b32 m0
 ; SI: ds_read_u8
 define void @load_i8_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) {
-  %1 = load i8 addrspace(3)* %in
+  %1 = load i8, i8 addrspace(3)* %in
   %2 = zext i8 %1 to i32
   store i32 %2, i32 addrspace(1)* %out
   ret void
@@ -477,13 +446,13 @@ define void @load_i8_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) {
 
 ; FUNC-LABEL: {{^}}load_i8_sext_local:
 ; R600: LDS_UBYTE_READ_RET
-; R600: ASHR
+; R600: BFE_INT
 ; SI-NOT: s_wqm_b64
 ; SI: s_mov_b32 m0
 ; SI: ds_read_i8
 define void @load_i8_sext_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) {
 entry:
-  %0 = load i8 addrspace(3)* %in
+  %0 = load i8, i8 addrspace(3)* %in
   %1 = sext i8 %0 to i32
   store i32 %1, i32 addrspace(1)* %out
   ret void
@@ -498,7 +467,7 @@ entry:
 ; SI: ds_read_u8
 define void @load_v2i8_local(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(3)* %in) {
 entry:
-  %0 = load <2 x i8> addrspace(3)* %in
+  %0 = load <2 x i8>, <2 x i8> addrspace(3)* %in
   %1 = zext <2 x i8> %0 to <2 x i32>
   store <2 x i32> %1, <2 x i32> addrspace(1)* %out
   ret void
@@ -507,15 +476,15 @@ entry:
 ; FUNC-LABEL: {{^}}load_v2i8_sext_local:
 ; R600-DAG: LDS_UBYTE_READ_RET
 ; R600-DAG: LDS_UBYTE_READ_RET
-; R600-DAG: ASHR
-; R600-DAG: ASHR
+; R600-DAG: BFE_INT
+; R600-DAG: BFE_INT
 ; SI-NOT: s_wqm_b64
 ; SI: s_mov_b32 m0
 ; SI: ds_read_i8
 ; SI: ds_read_i8
 define void @load_v2i8_sext_local(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(3)* %in) {
 entry:
-  %0 = load <2 x i8> addrspace(3)* %in
+  %0 = load <2 x i8>, <2 x i8> addrspace(3)* %in
   %1 = sext <2 x i8> %0 to <2 x i32>
   store <2 x i32> %1, <2 x i32> addrspace(1)* %out
   ret void
@@ -534,7 +503,7 @@ entry:
 ; SI: ds_read_u8
 define void @load_v4i8_local(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(3)* %in) {
 entry:
-  %0 = load <4 x i8> addrspace(3)* %in
+  %0 = load <4 x i8>, <4 x i8> addrspace(3)* %in
   %1 = zext <4 x i8> %0 to <4 x i32>
   store <4 x i32> %1, <4 x i32> addrspace(1)* %out
   ret void
@@ -545,10 +514,10 @@ entry:
 ; R600-DAG: LDS_UBYTE_READ_RET
 ; R600-DAG: LDS_UBYTE_READ_RET
 ; R600-DAG: LDS_UBYTE_READ_RET
-; R600-DAG: ASHR
-; R600-DAG: ASHR
-; R600-DAG: ASHR
-; R600-DAG: ASHR
+; R600-DAG: BFE_INT
+; R600-DAG: BFE_INT
+; R600-DAG: BFE_INT
+; R600-DAG: BFE_INT
 ; SI-NOT: s_wqm_b64
 ; SI: s_mov_b32 m0
 ; SI: ds_read_i8
@@ -557,7 +526,7 @@ entry:
 ; SI: ds_read_i8
 define void @load_v4i8_sext_local(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(3)* %in) {
 entry:
-  %0 = load <4 x i8> addrspace(3)* %in
+  %0 = load <4 x i8>, <4 x i8> addrspace(3)* %in
   %1 = sext <4 x i8> %0 to <4 x i32>
   store <4 x i32> %1, <4 x i32> addrspace(1)* %out
   ret void
@@ -571,7 +540,7 @@ entry:
 ; SI: ds_read_u16
 define void @load_i16_local(i32 addrspace(1)* %out, i16 addrspace(3)* %in) {
 entry:
-  %0 = load i16	 addrspace(3)* %in
+  %0 = load i16	, i16	 addrspace(3)* %in
   %1 = zext i16 %0 to i32
   store i32 %1, i32 addrspace(1)* %out
   ret void
@@ -579,13 +548,13 @@ entry:
 
 ; FUNC-LABEL: {{^}}load_i16_sext_local:
 ; R600: LDS_USHORT_READ_RET
-; R600: ASHR
+; R600: BFE_INT
 ; SI-NOT: s_wqm_b64
 ; SI: s_mov_b32 m0
 ; SI: ds_read_i16
 define void @load_i16_sext_local(i32 addrspace(1)* %out, i16 addrspace(3)* %in) {
 entry:
-  %0 = load i16 addrspace(3)* %in
+  %0 = load i16, i16 addrspace(3)* %in
   %1 = sext i16 %0 to i32
   store i32 %1, i32 addrspace(1)* %out
   ret void
@@ -600,7 +569,7 @@ entry:
 ; SI: ds_read_u16
 define void @load_v2i16_local(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(3)* %in) {
 entry:
-  %0 = load <2 x i16> addrspace(3)* %in
+  %0 = load <2 x i16>, <2 x i16> addrspace(3)* %in
   %1 = zext <2 x i16> %0 to <2 x i32>
   store <2 x i32> %1, <2 x i32> addrspace(1)* %out
   ret void
@@ -609,15 +578,15 @@ entry:
 ; FUNC-LABEL: {{^}}load_v2i16_sext_local:
 ; R600-DAG: LDS_USHORT_READ_RET
 ; R600-DAG: LDS_USHORT_READ_RET
-; R600-DAG: ASHR
-; R600-DAG: ASHR
+; R600-DAG: BFE_INT
+; R600-DAG: BFE_INT
 ; SI-NOT: s_wqm_b64
 ; SI: s_mov_b32 m0
 ; SI: ds_read_i16
 ; SI: ds_read_i16
 define void @load_v2i16_sext_local(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(3)* %in) {
 entry:
-  %0 = load <2 x i16> addrspace(3)* %in
+  %0 = load <2 x i16>, <2 x i16> addrspace(3)* %in
   %1 = sext <2 x i16> %0 to <2 x i32>
   store <2 x i32> %1, <2 x i32> addrspace(1)* %out
   ret void
@@ -636,7 +605,7 @@ entry:
 ; SI: ds_read_u16
 define void @load_v4i16_local(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(3)* %in) {
 entry:
-  %0 = load <4 x i16> addrspace(3)* %in
+  %0 = load <4 x i16>, <4 x i16> addrspace(3)* %in
   %1 = zext <4 x i16> %0 to <4 x i32>
   store <4 x i32> %1, <4 x i32> addrspace(1)* %out
   ret void
@@ -647,10 +616,10 @@ entry:
 ; R600-DAG: LDS_USHORT_READ_RET
 ; R600-DAG: LDS_USHORT_READ_RET
 ; R600-DAG: LDS_USHORT_READ_RET
-; R600-DAG: ASHR
-; R600-DAG: ASHR
-; R600-DAG: ASHR
-; R600-DAG: ASHR
+; R600-DAG: BFE_INT
+; R600-DAG: BFE_INT
+; R600-DAG: BFE_INT
+; R600-DAG: BFE_INT
 ; SI-NOT: s_wqm_b64
 ; SI: s_mov_b32 m0
 ; SI: ds_read_i16
@@ -659,7 +628,7 @@ entry:
 ; SI: ds_read_i16
 define void @load_v4i16_sext_local(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(3)* %in) {
 entry:
-  %0 = load <4 x i16> addrspace(3)* %in
+  %0 = load <4 x i16>, <4 x i16> addrspace(3)* %in
   %1 = sext <4 x i16> %0 to <4 x i32>
   store <4 x i32> %1, <4 x i32> addrspace(1)* %out
   ret void
@@ -673,7 +642,7 @@ entry:
 ; SI: ds_read_b32
 define void @load_i32_local(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
 entry:
-  %0 = load i32 addrspace(3)* %in
+  %0 = load i32, i32 addrspace(3)* %in
   store i32 %0, i32 addrspace(1)* %out
   ret void
 }
@@ -685,7 +654,7 @@ entry:
 ; SI: ds_read_b32
 define void @load_f32_local(float addrspace(1)* %out, float addrspace(3)* %in) {
 entry:
-  %0 = load float addrspace(3)* %in
+  %0 = load float, float addrspace(3)* %in
   store float %0, float addrspace(1)* %out
   ret void
 }
@@ -698,7 +667,7 @@ entry:
 ; SI: ds_read_b64
 define void @load_v2f32_local(<2 x float> addrspace(1)* %out, <2 x float> addrspace(3)* %in) {
 entry:
-  %0 = load <2 x float> addrspace(3)* %in
+  %0 = load <2 x float>, <2 x float> addrspace(3)* %in
   store <2 x float> %0, <2 x float> addrspace(1)* %out
   ret void
 }
@@ -711,10 +680,10 @@ entry:
 ; SI-DAG: ds_read_b32
 ; SI-DAG: ds_read2_b32
 define void @load_i32_v2i32_local(<2 x i32> addrspace(1)* %out, i32 addrspace(3)* %in) {
-  %scalar = load i32 addrspace(3)* %in
+  %scalar = load i32, i32 addrspace(3)* %in
   %tmp0 = bitcast i32 addrspace(3)* %in to <2 x i32> addrspace(3)*
-  %vec_ptr = getelementptr <2 x i32> addrspace(3)* %tmp0, i32 2
-  %vec0 = load <2 x i32> addrspace(3)* %vec_ptr, align 4
+  %vec_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(3)* %tmp0, i32 2
+  %vec0 = load <2 x i32>, <2 x i32> addrspace(3)* %vec_ptr, align 4
   %vec1 = insertelement <2 x i32> <i32 0, i32 0>, i32 %scalar, i32 0
   %vec = add <2 x i32> %vec0, %vec1
   store <2 x i32> %vec, <2 x i32> addrspace(1)* %out
@@ -732,9 +701,9 @@ define void @load_i32_v2i32_local(<2 x i32> addrspace(1)* %out, i32 addrspace(3)
 ; R600: LDS_READ_RET
 define void @load_i32_local_const_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
 entry:
-  %tmp0 = getelementptr [512 x i32] addrspace(3)* @lds, i32 0, i32 1
-  %tmp1 = load i32 addrspace(3)* %tmp0
-  %tmp2 = getelementptr i32 addrspace(1)* %out, i32 1
+  %tmp0 = getelementptr [512 x i32], [512 x i32] addrspace(3)* @lds, i32 0, i32 1
+  %tmp1 = load i32, i32 addrspace(3)* %tmp0
+  %tmp2 = getelementptr i32, i32 addrspace(1)* %out, i32 1
   store i32 %tmp1, i32 addrspace(1)* %tmp2
   ret void
 }
diff --git a/test/CodeGen/R600/load.vec.ll b/test/CodeGen/R600/load.vec.ll
index 346d8dc0c6e4..02f883cd8e9c 100644
--- a/test/CodeGen/R600/load.vec.ll
+++ b/test/CodeGen/R600/load.vec.ll
@@ -8,7 +8,7 @@
 ; SI: {{^}}load_v2i32:
 ; SI: buffer_load_dwordx2 v[{{[0-9]+:[0-9]+}}]
 define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %a = load <2 x i32> addrspace(1) * %in
+  %a = load <2 x i32>, <2 x i32> addrspace(1) * %in
   store <2 x i32> %a, <2 x i32> addrspace(1)* %out
   ret void
 }
@@ -19,7 +19,7 @@ define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %i
 ; SI: {{^}}load_v4i32:
 ; SI: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}]
 define void @load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %a = load <4 x i32> addrspace(1) * %in
+  %a = load <4 x i32>, <4 x i32> addrspace(1) * %in
   store <4 x i32> %a, <4 x i32> addrspace(1)* %out
   ret void
 }
diff --git a/test/CodeGen/R600/load64.ll b/test/CodeGen/R600/load64.ll
index cb3d65466061..74beabdc0076 100644
--- a/test/CodeGen/R600/load64.ll
+++ b/test/CodeGen/R600/load64.ll
@@ -6,7 +6,7 @@
 ; CHECK: buffer_load_dwordx2 v[{{[0-9]+:[0-9]+}}]
 ; CHECK: buffer_store_dwordx2 v[{{[0-9]+:[0-9]+}}]
 define void @load_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
-  %1 = load double addrspace(1)* %in
+  %1 = load double, double addrspace(1)* %in
   store double %1, double addrspace(1)* %out
   ret void
 }
@@ -15,7 +15,7 @@ define void @load_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
 ; CHECK: buffer_load_dwordx2 v[{{[0-9]+:[0-9]+}}]
 ; CHECK: buffer_store_dwordx2 v[{{[0-9]+:[0-9]+}}]
 define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
-  %tmp = load i64 addrspace(1)* %in
+  %tmp = load i64, i64 addrspace(1)* %in
   store i64 %tmp, i64 addrspace(1)* %out, align 8
   ret void
 }
@@ -25,7 +25,7 @@ define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
 ; CHECK: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}]
 ; CHECK: buffer_store_dwordx2 v[{{[0-9]+:[0-9]+}}]
 define void @load_const_addrspace_f64(double addrspace(1)* %out, double addrspace(2)* %in) {
-  %1 = load double addrspace(2)* %in
+  %1 = load double, double addrspace(2)* %in
   store double %1, double addrspace(1)* %out
   ret void
 }
diff --git a/test/CodeGen/R600/local-64.ll b/test/CodeGen/R600/local-64.ll
index f975bc1f56b0..33f3159d13eb 100644
--- a/test/CodeGen/R600/local-64.ll
+++ b/test/CodeGen/R600/local-64.ll
@@ -1,32 +1,33 @@
 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck --check-prefix=SI --check-prefix=BOTH %s
 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=BOTH %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=BOTH %s
 
 ; BOTH-LABEL: {{^}}local_i32_load
-; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} offset:28 [M0]
+; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} offset:28
 ; BOTH: buffer_store_dword [[REG]],
 define void @local_i32_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %in, i32 7
-  %val = load i32 addrspace(3)* %gep, align 4
+  %gep = getelementptr i32, i32 addrspace(3)* %in, i32 7
+  %val = load i32, i32 addrspace(3)* %gep, align 4
   store i32 %val, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; BOTH-LABEL: {{^}}local_i32_load_0_offset
-; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} [M0]
+; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}}
 ; BOTH: buffer_store_dword [[REG]],
 define void @local_i32_load_0_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
-  %val = load i32 addrspace(3)* %in, align 4
+  %val = load i32, i32 addrspace(3)* %in, align 4
   store i32 %val, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; BOTH-LABEL: {{^}}local_i8_load_i16_max_offset:
 ; BOTH-NOT: ADD
-; BOTH: ds_read_u8 [[REG:v[0-9]+]], {{v[0-9]+}} offset:65535 [M0]
+; BOTH: ds_read_u8 [[REG:v[0-9]+]], {{v[0-9]+}} offset:65535
 ; BOTH: buffer_store_byte [[REG]],
 define void @local_i8_load_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
-  %gep = getelementptr i8 addrspace(3)* %in, i32 65535
-  %val = load i8 addrspace(3)* %gep, align 4
+  %gep = getelementptr i8, i8 addrspace(3)* %in, i32 65535
+  %val = load i8, i8 addrspace(3)* %gep, align 4
   store i8 %val, i8 addrspace(1)* %out, align 4
   ret void
 }
@@ -37,67 +38,67 @@ define void @local_i8_load_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)
 ; SI: s_or_b32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
 ; CI: s_add_i32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
 ; BOTH: v_mov_b32_e32 [[VREGADDR:v[0-9]+]], [[ADDR]]
-; BOTH: ds_read_u8 [[REG:v[0-9]+]], [[VREGADDR]] [M0]
+; BOTH: ds_read_u8 [[REG:v[0-9]+]], [[VREGADDR]]
 ; BOTH: buffer_store_byte [[REG]],
 define void @local_i8_load_over_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
-  %gep = getelementptr i8 addrspace(3)* %in, i32 65536
-  %val = load i8 addrspace(3)* %gep, align 4
+  %gep = getelementptr i8, i8 addrspace(3)* %in, i32 65536
+  %val = load i8, i8 addrspace(3)* %gep, align 4
   store i8 %val, i8 addrspace(1)* %out, align 4
   ret void
 }
 
 ; BOTH-LABEL: {{^}}local_i64_load:
 ; BOTH-NOT: ADD
-; BOTH: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56 [M0]
+; BOTH: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56
 ; BOTH: buffer_store_dwordx2 [[REG]],
 define void @local_i64_load(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %in, i32 7
-  %val = load i64 addrspace(3)* %gep, align 8
+  %gep = getelementptr i64, i64 addrspace(3)* %in, i32 7
+  %val = load i64, i64 addrspace(3)* %gep, align 8
   store i64 %val, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 ; BOTH-LABEL: {{^}}local_i64_load_0_offset
-; BOTH: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} [M0]
+; BOTH: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}
 ; BOTH: buffer_store_dwordx2 [[REG]],
 define void @local_i64_load_0_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
-  %val = load i64 addrspace(3)* %in, align 8
+  %val = load i64, i64 addrspace(3)* %in, align 8
   store i64 %val, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 ; BOTH-LABEL: {{^}}local_f64_load:
 ; BOTH-NOT: ADD
-; BOTH: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56 [M0]
+; BOTH: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56
 ; BOTH: buffer_store_dwordx2 [[REG]],
 define void @local_f64_load(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
-  %gep = getelementptr double addrspace(3)* %in, i32 7
-  %val = load double addrspace(3)* %gep, align 8
+  %gep = getelementptr double, double addrspace(3)* %in, i32 7
+  %val = load double, double addrspace(3)* %gep, align 8
   store double %val, double addrspace(1)* %out, align 8
   ret void
 }
 
 ; BOTH-LABEL: {{^}}local_f64_load_0_offset
-; BOTH: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} [M0]
+; BOTH: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}
 ; BOTH: buffer_store_dwordx2 [[REG]],
 define void @local_f64_load_0_offset(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
-  %val = load double addrspace(3)* %in, align 8
+  %val = load double, double addrspace(3)* %in, align 8
   store double %val, double addrspace(1)* %out, align 8
   ret void
 }
 
 ; BOTH-LABEL: {{^}}local_i64_store:
 ; BOTH-NOT: ADD
-; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56 [M0]
+; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56
 define void @local_i64_store(i64 addrspace(3)* %out) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %out, i32 7
+  %gep = getelementptr i64, i64 addrspace(3)* %out, i32 7
   store i64 5678, i64 addrspace(3)* %gep, align 8
   ret void
 }
 
 ; BOTH-LABEL: {{^}}local_i64_store_0_offset:
 ; BOTH-NOT: ADD
-; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0]
+; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
 define void @local_i64_store_0_offset(i64 addrspace(3)* %out) nounwind {
   store i64 1234, i64 addrspace(3)* %out, align 8
   ret void
@@ -105,15 +106,15 @@ define void @local_i64_store_0_offset(i64 addrspace(3)* %out) nounwind {
 
 ; BOTH-LABEL: {{^}}local_f64_store:
 ; BOTH-NOT: ADD
-; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56 [M0]
+; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56
 define void @local_f64_store(double addrspace(3)* %out) nounwind {
-  %gep = getelementptr double addrspace(3)* %out, i32 7
+  %gep = getelementptr double, double addrspace(3)* %out, i32 7
   store double 16.0, double addrspace(3)* %gep, align 8
   ret void
 }
 
 ; BOTH-LABEL: {{^}}local_f64_store_0_offset
-; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0]
+; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
 define void @local_f64_store_0_offset(double addrspace(3)* %out) nounwind {
   store double 20.0, double addrspace(3)* %out, align 8
   ret void
@@ -121,19 +122,19 @@ define void @local_f64_store_0_offset(double addrspace(3)* %out) nounwind {
 
 ; BOTH-LABEL: {{^}}local_v2i64_store:
 ; BOTH-NOT: ADD
-; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:112 [M0]
-; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:120 [M0]
+; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:112
+; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:120
 ; BOTH: s_endpgm
 define void @local_v2i64_store(<2 x i64> addrspace(3)* %out) nounwind {
-  %gep = getelementptr <2 x i64> addrspace(3)* %out, i32 7
+  %gep = getelementptr <2 x i64>, <2 x i64> addrspace(3)* %out, i32 7
   store <2 x i64> <i64 5678, i64 5678>, <2 x i64> addrspace(3)* %gep, align 16
   ret void
 }
 
 ; BOTH-LABEL: {{^}}local_v2i64_store_0_offset:
 ; BOTH-NOT: ADD
-; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0]
-; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8 [M0]
+; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
+; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
 ; BOTH: s_endpgm
 define void @local_v2i64_store_0_offset(<2 x i64> addrspace(3)* %out) nounwind {
   store <2 x i64> <i64 1234, i64 1234>, <2 x i64> addrspace(3)* %out, align 16
@@ -142,23 +143,23 @@ define void @local_v2i64_store_0_offset(<2 x i64> addrspace(3)* %out) nounwind {
 
 ; BOTH-LABEL: {{^}}local_v4i64_store:
 ; BOTH-NOT: ADD
-; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:224 [M0]
-; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:232 [M0]
-; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:240 [M0]
-; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:248 [M0]
+; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:224
+; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:232
+; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:240
+; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:248
 ; BOTH: s_endpgm
 define void @local_v4i64_store(<4 x i64> addrspace(3)* %out) nounwind {
-  %gep = getelementptr <4 x i64> addrspace(3)* %out, i32 7
+  %gep = getelementptr <4 x i64>, <4 x i64> addrspace(3)* %out, i32 7
   store <4 x i64> <i64 5678, i64 5678, i64 5678, i64 5678>, <4 x i64> addrspace(3)* %gep, align 16
   ret void
 }
 
 ; BOTH-LABEL: {{^}}local_v4i64_store_0_offset:
 ; BOTH-NOT: ADD
-; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0]
-; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8 [M0]
-; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16 [M0]
-; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24 [M0]
+; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
+; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
+; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
+; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
 ; BOTH: s_endpgm
 define void @local_v4i64_store_0_offset(<4 x i64> addrspace(3)* %out) nounwind {
   store <4 x i64> <i64 1234, i64 1234, i64 1234, i64 1234>, <4 x i64> addrspace(3)* %out, align 16
diff --git a/test/CodeGen/R600/local-atomics.ll b/test/CodeGen/R600/local-atomics.ll
index 16d3173f3692..2aaf977ab903 100644
--- a/test/CodeGen/R600/local-atomics.ll
+++ b/test/CodeGen/R600/local-atomics.ll
@@ -1,15 +1,16 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=CI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s
 ; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 
 ; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i32:
 ; EG: LDS_WRXCHG_RET *
-; SI: s_load_dword [[SPTR:s[0-9]+]],
-; SI: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
-; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
-; SI: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
+; GCN: s_load_dword [[SPTR:s[0-9]+]],
+; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
+; GCN: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
+; GCN: buffer_store_dword [[RESULT]],
+; GCN: s_endpgm
 define void @lds_atomic_xchg_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw xchg i32 addrspace(3)* %ptr, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -18,10 +19,10 @@ define void @lds_atomic_xchg_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %
 
 ; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i32_offset:
 ; EG: LDS_WRXCHG_RET *
-; SI: ds_wrxchg_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_wrxchg_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_xchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw xchg i32 addrspace(3)* %gep, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
@@ -30,12 +31,12 @@ define void @lds_atomic_xchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspac
 ; XXX - Is it really necessary to load 4 into VGPR?
 ; FUNC-LABEL: {{^}}lds_atomic_add_ret_i32:
 ; EG: LDS_ADD_RET *
-; SI: s_load_dword [[SPTR:s[0-9]+]],
-; SI: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
-; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
-; SI: ds_add_rtn_u32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
+; GCN: s_load_dword [[SPTR:s[0-9]+]],
+; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
+; GCN: ds_add_rtn_u32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
+; GCN: buffer_store_dword [[RESULT]],
+; GCN: s_endpgm
 define void @lds_atomic_add_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw add i32 addrspace(3)* %ptr, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -44,10 +45,10 @@ define void @lds_atomic_add_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p
 
 ; FUNC-LABEL: {{^}}lds_atomic_add_ret_i32_offset:
 ; EG: LDS_ADD_RET *
-; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_add_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw add i32 addrspace(3)* %gep, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
@@ -55,13 +56,13 @@ define void @lds_atomic_add_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace
 
 ; FUNC-LABEL: {{^}}lds_atomic_add_ret_i32_bad_si_offset:
 ; EG: LDS_ADD_RET *
-; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} [M0]
-; CI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; CIVI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_add_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind {
   %sub = sub i32 %a, %b
   %add = add i32 %sub, 4
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 %add
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 %add
   %result = atomicrmw add i32 addrspace(3)* %gep, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
@@ -69,9 +70,9 @@ define void @lds_atomic_add_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 ad
 
 ; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i32:
 ; EG: LDS_ADD_RET *
-; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
-; SI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] [M0]
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
+; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]]
+; GCN: s_endpgm
 define void @lds_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw add i32 addrspace(3)* %ptr, i32 1 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -80,11 +81,11 @@ define void @lds_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p
 
 ; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i32_offset:
 ; EG: LDS_ADD_RET *
-; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
-; SI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] offset:16
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
+; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] offset:16
+; GCN: s_endpgm
 define void @lds_atomic_inc_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw add i32 addrspace(3)* %gep, i32 1 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
@@ -92,13 +93,13 @@ define void @lds_atomic_inc_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace
 
 ; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i32_bad_si_offset:
 ; EG: LDS_ADD_RET *
-; SI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} [M0]
-; CI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; SI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; CIVI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_inc_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind {
   %sub = sub i32 %a, %b
   %add = add i32 %sub, 4
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 %add
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 %add
   %result = atomicrmw add i32 addrspace(3)* %gep, i32 1 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
@@ -106,8 +107,8 @@ define void @lds_atomic_inc_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 ad
 
 ; FUNC-LABEL: {{^}}lds_atomic_sub_ret_i32:
 ; EG: LDS_SUB_RET *
-; SI: ds_sub_rtn_u32
-; SI: s_endpgm
+; GCN: ds_sub_rtn_u32
+; GCN: s_endpgm
 define void @lds_atomic_sub_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw sub i32 addrspace(3)* %ptr, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -116,10 +117,10 @@ define void @lds_atomic_sub_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p
 
 ; FUNC-LABEL: {{^}}lds_atomic_sub_ret_i32_offset:
 ; EG: LDS_SUB_RET *
-; SI: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_sub_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw sub i32 addrspace(3)* %gep, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
@@ -127,9 +128,9 @@ define void @lds_atomic_sub_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace
 
 ; FUNC-LABEL: {{^}}lds_atomic_dec_ret_i32:
 ; EG: LDS_SUB_RET *
-; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
-; SI: ds_dec_rtn_u32  v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] [M0]
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
+; GCN: ds_dec_rtn_u32  v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]]
+; GCN: s_endpgm
 define void @lds_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw sub i32 addrspace(3)* %ptr, i32 1 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -138,11 +139,11 @@ define void @lds_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p
 
 ; FUNC-LABEL: {{^}}lds_atomic_dec_ret_i32_offset:
 ; EG: LDS_SUB_RET *
-; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
-; SI: ds_dec_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] offset:16
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
+; GCN: ds_dec_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] offset:16
+; GCN: s_endpgm
 define void @lds_atomic_dec_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw sub i32 addrspace(3)* %gep, i32 1 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
@@ -150,8 +151,8 @@ define void @lds_atomic_dec_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace
 
 ; FUNC-LABEL: {{^}}lds_atomic_and_ret_i32:
 ; EG: LDS_AND_RET *
-; SI: ds_and_rtn_b32
-; SI: s_endpgm
+; GCN: ds_and_rtn_b32
+; GCN: s_endpgm
 define void @lds_atomic_and_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw and i32 addrspace(3)* %ptr, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -160,10 +161,10 @@ define void @lds_atomic_and_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p
 
 ; FUNC-LABEL: {{^}}lds_atomic_and_ret_i32_offset:
 ; EG: LDS_AND_RET *
-; SI: ds_and_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_and_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_and_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw and i32 addrspace(3)* %gep, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
@@ -171,8 +172,8 @@ define void @lds_atomic_and_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace
 
 ; FUNC-LABEL: {{^}}lds_atomic_or_ret_i32:
 ; EG: LDS_OR_RET *
-; SI: ds_or_rtn_b32
-; SI: s_endpgm
+; GCN: ds_or_rtn_b32
+; GCN: s_endpgm
 define void @lds_atomic_or_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw or i32 addrspace(3)* %ptr, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -181,10 +182,10 @@ define void @lds_atomic_or_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %pt
 
 ; FUNC-LABEL: {{^}}lds_atomic_or_ret_i32_offset:
 ; EG: LDS_OR_RET *
-; SI: ds_or_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_or_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_or_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw or i32 addrspace(3)* %gep, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
@@ -192,8 +193,8 @@ define void @lds_atomic_or_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(
 
 ; FUNC-LABEL: {{^}}lds_atomic_xor_ret_i32:
 ; EG: LDS_XOR_RET *
-; SI: ds_xor_rtn_b32
-; SI: s_endpgm
+; GCN: ds_xor_rtn_b32
+; GCN: s_endpgm
 define void @lds_atomic_xor_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw xor i32 addrspace(3)* %ptr, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -202,10 +203,10 @@ define void @lds_atomic_xor_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p
 
 ; FUNC-LABEL: {{^}}lds_atomic_xor_ret_i32_offset:
 ; EG: LDS_XOR_RET *
-; SI: ds_xor_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_xor_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_xor_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw xor i32 addrspace(3)* %gep, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
@@ -221,8 +222,8 @@ define void @lds_atomic_xor_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace
 
 ; FUNC-LABEL: {{^}}lds_atomic_min_ret_i32:
 ; EG: LDS_MIN_INT_RET *
-; SI: ds_min_rtn_i32
-; SI: s_endpgm
+; GCN: ds_min_rtn_i32
+; GCN: s_endpgm
 define void @lds_atomic_min_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw min i32 addrspace(3)* %ptr, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -231,10 +232,10 @@ define void @lds_atomic_min_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p
 
 ; FUNC-LABEL: {{^}}lds_atomic_min_ret_i32_offset:
 ; EG: LDS_MIN_INT_RET *
-; SI: ds_min_rtn_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_min_rtn_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_min_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw min i32 addrspace(3)* %gep, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
@@ -242,8 +243,8 @@ define void @lds_atomic_min_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace
 
 ; FUNC-LABEL: {{^}}lds_atomic_max_ret_i32:
 ; EG: LDS_MAX_INT_RET *
-; SI: ds_max_rtn_i32
-; SI: s_endpgm
+; GCN: ds_max_rtn_i32
+; GCN: s_endpgm
 define void @lds_atomic_max_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw max i32 addrspace(3)* %ptr, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -252,10 +253,10 @@ define void @lds_atomic_max_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p
 
 ; FUNC-LABEL: {{^}}lds_atomic_max_ret_i32_offset:
 ; EG: LDS_MAX_INT_RET *
-; SI: ds_max_rtn_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_max_rtn_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_max_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw max i32 addrspace(3)* %gep, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
@@ -263,8 +264,8 @@ define void @lds_atomic_max_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace
 
 ; FUNC-LABEL: {{^}}lds_atomic_umin_ret_i32:
 ; EG: LDS_MIN_UINT_RET *
-; SI: ds_min_rtn_u32
-; SI: s_endpgm
+; GCN: ds_min_rtn_u32
+; GCN: s_endpgm
 define void @lds_atomic_umin_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw umin i32 addrspace(3)* %ptr, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -273,10 +274,10 @@ define void @lds_atomic_umin_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %
 
 ; FUNC-LABEL: {{^}}lds_atomic_umin_ret_i32_offset:
 ; EG: LDS_MIN_UINT_RET *
-; SI: ds_min_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_min_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_umin_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw umin i32 addrspace(3)* %gep, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
@@ -284,8 +285,8 @@ define void @lds_atomic_umin_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspac
 
 ; FUNC-LABEL: {{^}}lds_atomic_umax_ret_i32:
 ; EG: LDS_MAX_UINT_RET *
-; SI: ds_max_rtn_u32
-; SI: s_endpgm
+; GCN: ds_max_rtn_u32
+; GCN: s_endpgm
 define void @lds_atomic_umax_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw umax i32 addrspace(3)* %ptr, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -294,182 +295,182 @@ define void @lds_atomic_umax_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %
 
 ; FUNC-LABEL: {{^}}lds_atomic_umax_ret_i32_offset:
 ; EG: LDS_MAX_UINT_RET *
-; SI: ds_max_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_max_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_umax_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw umax i32 addrspace(3)* %gep, i32 4 seq_cst
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_xchg_noret_i32:
-; SI: s_load_dword [[SPTR:s[0-9]+]],
-; SI: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
-; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
-; SI: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0]
-; SI: s_endpgm
+; GCN: s_load_dword [[SPTR:s[0-9]+]],
+; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
+; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
+; GCN: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
+; GCN: s_endpgm
 define void @lds_atomic_xchg_noret_i32(i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw xchg i32 addrspace(3)* %ptr, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_xchg_noret_i32_offset:
-; SI: ds_wrxchg_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_wrxchg_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_xchg_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw xchg i32 addrspace(3)* %gep, i32 4 seq_cst
   ret void
 }
 
 ; XXX - Is it really necessary to load 4 into VGPR?
 ; FUNC-LABEL: {{^}}lds_atomic_add_noret_i32:
-; SI: s_load_dword [[SPTR:s[0-9]+]],
-; SI: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
-; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
-; SI: ds_add_u32 [[VPTR]], [[DATA]] [M0]
-; SI: s_endpgm
+; GCN: s_load_dword [[SPTR:s[0-9]+]],
+; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
+; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
+; GCN: ds_add_u32 [[VPTR]], [[DATA]]
+; GCN: s_endpgm
 define void @lds_atomic_add_noret_i32(i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw add i32 addrspace(3)* %ptr, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_add_noret_i32_offset:
-; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_add_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw add i32 addrspace(3)* %gep, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_add_noret_i32_bad_si_offset
-; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} [M0]
-; CI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 [M0]
-; SI: s_endpgm
+; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}}
+; CIVI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_add_noret_i32_bad_si_offset(i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind {
   %sub = sub i32 %a, %b
   %add = add i32 %sub, 4
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 %add
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 %add
   %result = atomicrmw add i32 addrspace(3)* %gep, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i32:
-; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
-; SI: ds_inc_u32 v{{[0-9]+}}, [[NEGONE]] [M0]
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
+; GCN: ds_inc_u32 v{{[0-9]+}}, [[NEGONE]]
+; GCN: s_endpgm
 define void @lds_atomic_inc_noret_i32(i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw add i32 addrspace(3)* %ptr, i32 1 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i32_offset:
-; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
-; SI: ds_inc_u32 v{{[0-9]+}}, [[NEGONE]] offset:16
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
+; GCN: ds_inc_u32 v{{[0-9]+}}, [[NEGONE]] offset:16
+; GCN: s_endpgm
 define void @lds_atomic_inc_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw add i32 addrspace(3)* %gep, i32 1 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i32_bad_si_offset:
 ; SI: ds_inc_u32 v{{[0-9]+}}, v{{[0-9]+}}
-; CI: ds_inc_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; CIVI: ds_inc_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_inc_noret_i32_bad_si_offset(i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind {
   %sub = sub i32 %a, %b
   %add = add i32 %sub, 4
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 %add
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 %add
   %result = atomicrmw add i32 addrspace(3)* %gep, i32 1 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_sub_noret_i32:
-; SI: ds_sub_u32
-; SI: s_endpgm
+; GCN: ds_sub_u32
+; GCN: s_endpgm
 define void @lds_atomic_sub_noret_i32(i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw sub i32 addrspace(3)* %ptr, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_sub_noret_i32_offset:
-; SI: ds_sub_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_sub_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_sub_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw sub i32 addrspace(3)* %gep, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i32:
-; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
-; SI: ds_dec_u32  v{{[0-9]+}}, [[NEGONE]]
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
+; GCN: ds_dec_u32  v{{[0-9]+}}, [[NEGONE]]
+; GCN: s_endpgm
 define void @lds_atomic_dec_noret_i32(i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw sub i32 addrspace(3)* %ptr, i32 1 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i32_offset:
-; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
-; SI: ds_dec_u32 v{{[0-9]+}}, [[NEGONE]] offset:16
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
+; GCN: ds_dec_u32 v{{[0-9]+}}, [[NEGONE]] offset:16
+; GCN: s_endpgm
 define void @lds_atomic_dec_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw sub i32 addrspace(3)* %gep, i32 1 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_and_noret_i32:
-; SI: ds_and_b32
-; SI: s_endpgm
+; GCN: ds_and_b32
+; GCN: s_endpgm
 define void @lds_atomic_and_noret_i32(i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw and i32 addrspace(3)* %ptr, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_and_noret_i32_offset:
-; SI: ds_and_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_and_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_and_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw and i32 addrspace(3)* %gep, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_or_noret_i32:
-; SI: ds_or_b32
-; SI: s_endpgm
+; GCN: ds_or_b32
+; GCN: s_endpgm
 define void @lds_atomic_or_noret_i32(i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw or i32 addrspace(3)* %ptr, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_or_noret_i32_offset:
-; SI: ds_or_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_or_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_or_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw or i32 addrspace(3)* %gep, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_xor_noret_i32:
-; SI: ds_xor_b32
-; SI: s_endpgm
+; GCN: ds_xor_b32
+; GCN: s_endpgm
 define void @lds_atomic_xor_noret_i32(i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw xor i32 addrspace(3)* %ptr, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_xor_noret_i32_offset:
-; SI: ds_xor_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_xor_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_xor_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw xor i32 addrspace(3)* %gep, i32 4 seq_cst
   ret void
 }
@@ -482,69 +483,69 @@ define void @lds_atomic_xor_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
 ; }
 
 ; FUNC-LABEL: {{^}}lds_atomic_min_noret_i32:
-; SI: ds_min_i32
-; SI: s_endpgm
+; GCN: ds_min_i32
+; GCN: s_endpgm
 define void @lds_atomic_min_noret_i32(i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw min i32 addrspace(3)* %ptr, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_min_noret_i32_offset:
-; SI: ds_min_i32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_min_i32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_min_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw min i32 addrspace(3)* %gep, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_max_noret_i32:
-; SI: ds_max_i32
-; SI: s_endpgm
+; GCN: ds_max_i32
+; GCN: s_endpgm
 define void @lds_atomic_max_noret_i32(i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw max i32 addrspace(3)* %ptr, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_max_noret_i32_offset:
-; SI: ds_max_i32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_max_i32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_max_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw max i32 addrspace(3)* %gep, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_umin_noret_i32:
-; SI: ds_min_u32
-; SI: s_endpgm
+; GCN: ds_min_u32
+; GCN: s_endpgm
 define void @lds_atomic_umin_noret_i32(i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw umin i32 addrspace(3)* %ptr, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_umin_noret_i32_offset:
-; SI: ds_min_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_min_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_umin_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw umin i32 addrspace(3)* %gep, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_umax_noret_i32:
-; SI: ds_max_u32
-; SI: s_endpgm
+; GCN: ds_max_u32
+; GCN: s_endpgm
 define void @lds_atomic_umax_noret_i32(i32 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw umax i32 addrspace(3)* %ptr, i32 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_umax_noret_i32_offset:
-; SI: ds_max_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; SI: s_endpgm
+; GCN: ds_max_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
+; GCN: s_endpgm
 define void @lds_atomic_umax_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i32 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
   %result = atomicrmw umax i32 addrspace(3)* %gep, i32 4 seq_cst
   ret void
 }
diff --git a/test/CodeGen/R600/local-atomics64.ll b/test/CodeGen/R600/local-atomics64.ll
index ce6ddbd66265..0ffa5e751b7d 100644
--- a/test/CodeGen/R600/local-atomics64.ll
+++ b/test/CodeGen/R600/local-atomics64.ll
@@ -1,8 +1,9 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s
 
 ; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i64:
-; SI: ds_wrxchg_rtn_b64
-; SI: s_endpgm
+; GCN: ds_wrxchg_rtn_b64
+; GCN: s_endpgm
 define void @lds_atomic_xchg_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw xchg i64 addrspace(3)* %ptr, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
@@ -10,18 +11,18 @@ define void @lds_atomic_xchg_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i64_offset:
-; SI: ds_wrxchg_rtn_b64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_wrxchg_rtn_b64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_xchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw xchg i64 addrspace(3)* %gep, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_add_ret_i64:
-; SI: ds_add_rtn_u64
-; SI: s_endpgm
+; GCN: ds_add_rtn_u64
+; GCN: s_endpgm
 define void @lds_atomic_add_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw add i64 addrspace(3)* %ptr, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
@@ -29,26 +30,27 @@ define void @lds_atomic_add_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_add_ret_i64_offset:
+; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 9
+; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0
 ; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 9
-; SI-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0
-; SI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
-; SI: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32 [M0]
-; SI: buffer_store_dwordx2 [[RESULT]],
-; SI: s_endpgm
+; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
+; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32
+; GCN: buffer_store_dwordx2 [[RESULT]],
+; GCN: s_endpgm
 define void @lds_atomic_add_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i64 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i64 4
   %result = atomicrmw add i64 addrspace(3)* %gep, i64 9 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i64:
-; SI: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], -1
-; SI: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], -1
-; SI: ds_inc_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}
-; SI: buffer_store_dwordx2 [[RESULT]],
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], -1
+; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], -1
+; GCN: ds_inc_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}
+; GCN: buffer_store_dwordx2 [[RESULT]],
+; GCN: s_endpgm
 define void @lds_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw add i64 addrspace(3)* %ptr, i64 1 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
@@ -56,18 +58,18 @@ define void @lds_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i64_offset:
-; SI: ds_inc_rtn_u64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_inc_rtn_u64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw add i64 addrspace(3)* %gep, i64 1 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_sub_ret_i64:
-; SI: ds_sub_rtn_u64
-; SI: s_endpgm
+; GCN: ds_sub_rtn_u64
+; GCN: s_endpgm
 define void @lds_atomic_sub_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw sub i64 addrspace(3)* %ptr, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
@@ -75,21 +77,21 @@ define void @lds_atomic_sub_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_sub_ret_i64_offset:
-; SI: ds_sub_rtn_u64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_sub_rtn_u64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_sub_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw sub i64 addrspace(3)* %gep, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_dec_ret_i64:
-; SI: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], -1
-; SI: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], -1
-; SI: ds_dec_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}
-; SI: buffer_store_dwordx2 [[RESULT]],
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], -1
+; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], -1
+; GCN: ds_dec_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}
+; GCN: buffer_store_dwordx2 [[RESULT]],
+; GCN: s_endpgm
 define void @lds_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw sub i64 addrspace(3)* %ptr, i64 1 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
@@ -97,18 +99,18 @@ define void @lds_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_dec_ret_i64_offset:
-; SI: ds_dec_rtn_u64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_dec_rtn_u64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_dec_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw sub i64 addrspace(3)* %gep, i64 1 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_and_ret_i64:
-; SI: ds_and_rtn_b64
-; SI: s_endpgm
+; GCN: ds_and_rtn_b64
+; GCN: s_endpgm
 define void @lds_atomic_and_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw and i64 addrspace(3)* %ptr, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
@@ -116,18 +118,18 @@ define void @lds_atomic_and_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_and_ret_i64_offset:
-; SI: ds_and_rtn_b64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_and_rtn_b64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_and_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw and i64 addrspace(3)* %gep, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_or_ret_i64:
-; SI: ds_or_rtn_b64
-; SI: s_endpgm
+; GCN: ds_or_rtn_b64
+; GCN: s_endpgm
 define void @lds_atomic_or_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw or i64 addrspace(3)* %ptr, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
@@ -135,18 +137,18 @@ define void @lds_atomic_or_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %pt
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_or_ret_i64_offset:
-; SI: ds_or_rtn_b64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_or_rtn_b64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_or_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw or i64 addrspace(3)* %gep, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_xor_ret_i64:
-; SI: ds_xor_rtn_b64
-; SI: s_endpgm
+; GCN: ds_xor_rtn_b64
+; GCN: s_endpgm
 define void @lds_atomic_xor_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw xor i64 addrspace(3)* %ptr, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
@@ -154,10 +156,10 @@ define void @lds_atomic_xor_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_xor_ret_i64_offset:
-; SI: ds_xor_rtn_b64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_xor_rtn_b64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_xor_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw xor i64 addrspace(3)* %gep, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
   ret void
@@ -172,8 +174,8 @@ define void @lds_atomic_xor_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace
 ; }
 
 ; FUNC-LABEL: {{^}}lds_atomic_min_ret_i64:
-; SI: ds_min_rtn_i64
-; SI: s_endpgm
+; GCN: ds_min_rtn_i64
+; GCN: s_endpgm
 define void @lds_atomic_min_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw min i64 addrspace(3)* %ptr, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
@@ -181,18 +183,18 @@ define void @lds_atomic_min_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_min_ret_i64_offset:
-; SI: ds_min_rtn_i64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_min_rtn_i64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_min_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw min i64 addrspace(3)* %gep, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_max_ret_i64:
-; SI: ds_max_rtn_i64
-; SI: s_endpgm
+; GCN: ds_max_rtn_i64
+; GCN: s_endpgm
 define void @lds_atomic_max_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw max i64 addrspace(3)* %ptr, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
@@ -200,18 +202,18 @@ define void @lds_atomic_max_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_max_ret_i64_offset:
-; SI: ds_max_rtn_i64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_max_rtn_i64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_max_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw max i64 addrspace(3)* %gep, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_umin_ret_i64:
-; SI: ds_min_rtn_u64
-; SI: s_endpgm
+; GCN: ds_min_rtn_u64
+; GCN: s_endpgm
 define void @lds_atomic_umin_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw umin i64 addrspace(3)* %ptr, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
@@ -219,18 +221,18 @@ define void @lds_atomic_umin_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_umin_ret_i64_offset:
-; SI: ds_min_rtn_u64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_min_rtn_u64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_umin_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw umin i64 addrspace(3)* %gep, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_umax_ret_i64:
-; SI: ds_max_rtn_u64
-; SI: s_endpgm
+; GCN: ds_max_rtn_u64
+; GCN: s_endpgm
 define void @lds_atomic_umax_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw umax i64 addrspace(3)* %ptr, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
@@ -238,35 +240,35 @@ define void @lds_atomic_umax_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_umax_ret_i64_offset:
-; SI: ds_max_rtn_u64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_max_rtn_u64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_umax_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw umax i64 addrspace(3)* %gep, i64 4 seq_cst
   store i64 %result, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_xchg_noret_i64:
-; SI: ds_wrxchg_rtn_b64
-; SI: s_endpgm
+; GCN: ds_wrxchg_rtn_b64
+; GCN: s_endpgm
 define void @lds_atomic_xchg_noret_i64(i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw xchg i64 addrspace(3)* %ptr, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_xchg_noret_i64_offset:
-; SI: ds_wrxchg_rtn_b64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_wrxchg_rtn_b64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_xchg_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw xchg i64 addrspace(3)* %gep, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_add_noret_i64:
-; SI: ds_add_u64
-; SI: s_endpgm
+; GCN: ds_add_u64
+; GCN: s_endpgm
 define void @lds_atomic_add_noret_i64(i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw add i64 addrspace(3)* %ptr, i64 4 seq_cst
   ret void
@@ -274,119 +276,120 @@ define void @lds_atomic_add_noret_i64(i64 addrspace(3)* %ptr) nounwind {
 
 ; FUNC-LABEL: {{^}}lds_atomic_add_noret_i64_offset:
 ; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
-; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
-; SI: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 9
-; SI: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0
-; SI: ds_add_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32 [M0]
-; SI: s_endpgm
+; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
+; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 9
+; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0
+; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
+; GCN: ds_add_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_add_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i64 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i64 4
   %result = atomicrmw add i64 addrspace(3)* %gep, i64 9 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i64:
-; SI: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], -1
-; SI: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], -1
-; SI: ds_inc_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], -1
+; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], -1
+; GCN: ds_inc_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}
+; GCN: s_endpgm
 define void @lds_atomic_inc_noret_i64(i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw add i64 addrspace(3)* %ptr, i64 1 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i64_offset:
-; SI: ds_inc_u64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_inc_u64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_inc_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw add i64 addrspace(3)* %gep, i64 1 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_sub_noret_i64:
-; SI: ds_sub_u64
-; SI: s_endpgm
+; GCN: ds_sub_u64
+; GCN: s_endpgm
 define void @lds_atomic_sub_noret_i64(i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw sub i64 addrspace(3)* %ptr, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_sub_noret_i64_offset:
-; SI: ds_sub_u64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_sub_u64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_sub_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw sub i64 addrspace(3)* %gep, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i64:
-; SI: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], -1
-; SI: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], -1
-; SI: ds_dec_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], -1
+; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], -1
+; GCN: ds_dec_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}
+; GCN: s_endpgm
 define void @lds_atomic_dec_noret_i64(i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw sub i64 addrspace(3)* %ptr, i64 1 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i64_offset:
-; SI: ds_dec_u64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_dec_u64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_dec_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw sub i64 addrspace(3)* %gep, i64 1 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_and_noret_i64:
-; SI: ds_and_b64
-; SI: s_endpgm
+; GCN: ds_and_b64
+; GCN: s_endpgm
 define void @lds_atomic_and_noret_i64(i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw and i64 addrspace(3)* %ptr, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_and_noret_i64_offset:
-; SI: ds_and_b64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_and_b64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_and_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw and i64 addrspace(3)* %gep, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_or_noret_i64:
-; SI: ds_or_b64
-; SI: s_endpgm
+; GCN: ds_or_b64
+; GCN: s_endpgm
 define void @lds_atomic_or_noret_i64(i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw or i64 addrspace(3)* %ptr, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_or_noret_i64_offset:
-; SI: ds_or_b64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_or_b64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_or_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw or i64 addrspace(3)* %gep, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_xor_noret_i64:
-; SI: ds_xor_b64
-; SI: s_endpgm
+; GCN: ds_xor_b64
+; GCN: s_endpgm
 define void @lds_atomic_xor_noret_i64(i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw xor i64 addrspace(3)* %ptr, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_xor_noret_i64_offset:
-; SI: ds_xor_b64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_xor_b64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_xor_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw xor i64 addrspace(3)* %gep, i64 4 seq_cst
   ret void
 }
@@ -399,69 +402,69 @@ define void @lds_atomic_xor_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
 ; }
 
 ; FUNC-LABEL: {{^}}lds_atomic_min_noret_i64:
-; SI: ds_min_i64
-; SI: s_endpgm
+; GCN: ds_min_i64
+; GCN: s_endpgm
 define void @lds_atomic_min_noret_i64(i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw min i64 addrspace(3)* %ptr, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_min_noret_i64_offset:
-; SI: ds_min_i64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_min_i64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_min_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw min i64 addrspace(3)* %gep, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_max_noret_i64:
-; SI: ds_max_i64
-; SI: s_endpgm
+; GCN: ds_max_i64
+; GCN: s_endpgm
 define void @lds_atomic_max_noret_i64(i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw max i64 addrspace(3)* %ptr, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_max_noret_i64_offset:
-; SI: ds_max_i64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_max_i64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_max_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw max i64 addrspace(3)* %gep, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_umin_noret_i64:
-; SI: ds_min_u64
-; SI: s_endpgm
+; GCN: ds_min_u64
+; GCN: s_endpgm
 define void @lds_atomic_umin_noret_i64(i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw umin i64 addrspace(3)* %ptr, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_umin_noret_i64_offset:
-; SI: ds_min_u64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_min_u64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_umin_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw umin i64 addrspace(3)* %gep, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_umax_noret_i64:
-; SI: ds_max_u64
-; SI: s_endpgm
+; GCN: ds_max_u64
+; GCN: s_endpgm
 define void @lds_atomic_umax_noret_i64(i64 addrspace(3)* %ptr) nounwind {
   %result = atomicrmw umax i64 addrspace(3)* %ptr, i64 4 seq_cst
   ret void
 }
 
 ; FUNC-LABEL: {{^}}lds_atomic_umax_noret_i64_offset:
-; SI: ds_max_u64 {{.*}} offset:32
-; SI: s_endpgm
+; GCN: ds_max_u64 {{.*}} offset:32
+; GCN: s_endpgm
 define void @lds_atomic_umax_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
-  %gep = getelementptr i64 addrspace(3)* %ptr, i32 4
+  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
   %result = atomicrmw umax i64 addrspace(3)* %gep, i64 4 seq_cst
   ret void
 }
diff --git a/test/CodeGen/R600/local-memory-two-objects.ll b/test/CodeGen/R600/local-memory-two-objects.ll
index 60f1a0a4963a..06a8b1246e63 100644
--- a/test/CodeGen/R600/local-memory-two-objects.ll
+++ b/test/CodeGen/R600/local-memory-two-objects.ll
@@ -5,7 +5,6 @@
 @local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
 @local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
 
-; EG: {{^}}local_memory_two_objects:
 
 ; Check that the LDS size emitted correctly
 ; EG: .long 166120
@@ -13,6 +12,8 @@
 ; GCN: .long 47180
 ; GCN-NEXT: .long 38792
 
+; EG: {{^}}local_memory_two_objects:
+
 ; We would like to check the the lds writes are using different
 ; addresses, but due to variations in the scheduler, we can't do
 ; this consistently on evergreen GPUs.
@@ -30,28 +31,28 @@
 ; EG: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
 ; EG-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
 ; SI: v_add_i32_e32 [[SIPTR:v[0-9]+]], 16, v{{[0-9]+}}
-; SI: ds_read_b32 {{v[0-9]+}}, [[SIPTR]] [M0]
-; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]] offset:16 [M0]
-; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR]] [M0]
+; SI: ds_read_b32 {{v[0-9]+}}, [[SIPTR]]
+; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]] offset:16
+; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR]]
 
 define void @local_memory_two_objects(i32 addrspace(1)* %out) {
 entry:
   %x.i = call i32 @llvm.r600.read.tidig.x() #0
-  %arrayidx = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i
+  %arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i
   store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4
   %mul = shl nsw i32 %x.i, 1
-  %arrayidx1 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i
+  %arrayidx1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i
   store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4
   %sub = sub nsw i32 3, %x.i
   call void @llvm.AMDGPU.barrier.local()
-  %arrayidx2 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub
-  %0 = load i32 addrspace(3)* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds i32 addrspace(1)* %out, i32 %x.i
+  %arrayidx2 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub
+  %0 = load i32, i32 addrspace(3)* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %x.i
   store i32 %0, i32 addrspace(1)* %arrayidx3, align 4
-  %arrayidx4 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub
-  %1 = load i32 addrspace(3)* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub
+  %1 = load i32, i32 addrspace(3)* %arrayidx4, align 4
   %add = add nsw i32 %x.i, 4
-  %arrayidx5 = getelementptr inbounds i32 addrspace(1)* %out, i32 %add
+  %arrayidx5 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %add
   store i32 %1, i32 addrspace(1)* %arrayidx5, align 4
   ret void
 }
diff --git a/test/CodeGen/R600/local-memory.ll b/test/CodeGen/R600/local-memory.ll
index 68e72c556f66..9494ed75bd0c 100644
--- a/test/CodeGen/R600/local-memory.ll
+++ b/test/CodeGen/R600/local-memory.ll
@@ -4,7 +4,6 @@
 
 @local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4
 
-; FUNC-LABEL: {{^}}local_memory:
 
 ; Check that the LDS size emitted correctly
 ; EG: .long 166120
@@ -14,6 +13,8 @@
 ; CI: .long 47180
 ; CI-NEXT: .long 38792
 
+; FUNC-LABEL: {{^}}local_memory:
+
 ; EG: LDS_WRITE
 ; SI-NOT: s_wqm_b64
 ; SI: ds_write_b32
@@ -29,15 +30,15 @@
 define void @local_memory(i32 addrspace(1)* %out) {
 entry:
   %y.i = call i32 @llvm.r600.read.tidig.x() #0
-  %arrayidx = getelementptr inbounds [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %y.i
+  %arrayidx = getelementptr inbounds [128 x i32], [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %y.i
   store i32 %y.i, i32 addrspace(3)* %arrayidx, align 4
   %add = add nsw i32 %y.i, 1
   %cmp = icmp eq i32 %add, 16
   %.add = select i1 %cmp, i32 0, i32 %add
   call void @llvm.AMDGPU.barrier.local()
-  %arrayidx1 = getelementptr inbounds [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %.add
-  %0 = load i32 addrspace(3)* %arrayidx1, align 4
-  %arrayidx2 = getelementptr inbounds i32 addrspace(1)* %out, i32 %y.i
+  %arrayidx1 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %.add
+  %0 = load i32, i32 addrspace(3)* %arrayidx1, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %y.i
   store i32 %0, i32 addrspace(1)* %arrayidx2, align 4
   ret void
 }
diff --git a/test/CodeGen/R600/loop-address.ll b/test/CodeGen/R600/loop-address.ll
index 03e0f011fffc..7fadb8dba7b8 100644
--- a/test/CodeGen/R600/loop-address.ll
+++ b/test/CodeGen/R600/loop-address.ll
@@ -17,7 +17,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.07.in = phi i32 [ %i.07, %for.body ], [ %iterations, %entry ]
   %ai.06 = phi i32 [ %add, %for.body ], [ 0, %entry ]
   %i.07 = add nsw i32 %i.07.in, -1
-  %arrayidx = getelementptr inbounds i32 addrspace(1)* %out, i32 %ai.06
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %ai.06
   store i32 %i.07, i32 addrspace(1)* %arrayidx, align 4
   %add = add nsw i32 %ai.06, 1
   %exitcond = icmp eq i32 %add, %iterations
diff --git a/test/CodeGen/R600/loop-idiom.ll b/test/CodeGen/R600/loop-idiom.ll
index a0b00ab644b4..810b34fed865 100644
--- a/test/CodeGen/R600/loop-idiom.ll
+++ b/test/CodeGen/R600/loop-idiom.ll
@@ -20,9 +20,9 @@ entry:
 
 for.body:
   %0 = phi i32 [0, %entry], [%4, %for.body]
-  %1 = getelementptr i8 addrspace(3)* %in, i32 %0
-  %2 = getelementptr i8* %dest, i32 %0
-  %3 = load i8 addrspace(3)* %1
+  %1 = getelementptr i8, i8 addrspace(3)* %in, i32 %0
+  %2 = getelementptr i8, i8* %dest, i32 %0
+  %3 = load i8, i8 addrspace(3)* %1
   store i8 %3, i8* %2
   %4 = add i32 %0, 1
   %5 = icmp eq i32 %4, %size
@@ -44,7 +44,7 @@ entry:
 
 for.body:
   %0 = phi i32 [0, %entry], [%2, %for.body]
-  %1 = getelementptr i8* %dest, i32 %0
+  %1 = getelementptr i8, i8* %dest, i32 %0
   store i8 0, i8* %1
   %2 = add i32 %0, 1
   %3 = icmp eq i32 %2, %size
diff --git a/test/CodeGen/R600/m0-spill.ll b/test/CodeGen/R600/m0-spill.ll
index 4dade82325ce..1dddc85f775d 100644
--- a/test/CodeGen/R600/m0-spill.ll
+++ b/test/CodeGen/R600/m0-spill.ll
@@ -12,8 +12,8 @@ main_body:
   br i1 %cmp, label %if, label %else
 
 if:
-  %lds_ptr = getelementptr [64 x float] addrspace(3)* @lds, i32 0, i32 0
-  %lds_data = load float addrspace(3)* %lds_ptr
+  %lds_ptr = getelementptr [64 x float], [64 x float] addrspace(3)* @lds, i32 0, i32 0
+  %lds_data = load float, float addrspace(3)* %lds_ptr
   br label %endif
 
 else:
diff --git a/test/CodeGen/R600/mad-combine.ll b/test/CodeGen/R600/mad-combine.ll
new file mode 100644
index 000000000000..bc071628ead0
--- /dev/null
+++ b/test/CodeGen/R600/mad-combine.ll
@@ -0,0 +1,567 @@
+; Make sure we still form mad even when unsafe math or fp-contract is allowed instead of fma.
+
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-STD -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -fp-contract=fast < %s | FileCheck -check-prefix=SI -check-prefix=SI-STD -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=SI-STD -check-prefix=FUNC %s
+
+; Make sure we don't form mad with denormals
+; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-DENORM -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=verde -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-DENORM-SLOWFMAF -check-prefix=FUNC %s
+
+declare i32 @llvm.r600.read.tidig.x() #0
+declare float @llvm.fabs.f32(float) #0
+declare float @llvm.fma.f32(float, float, float) #0
+declare float @llvm.fmuladd.f32(float, float, float) #0
+
+; (fadd (fmul x, y), z) -> (fma x, y, z)
+; FUNC-LABEL: {{^}}combine_to_mad_f32_0:
+; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+
+; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
+
+; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
+
+; SI-DENORM-SLOWFMAF-NOT: v_fma
+; SI-DENORM-SLOWFMAF-NOT: v_mad
+
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
+; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP]]
+
+; SI: buffer_store_dword [[RESULT]]
+define void @combine_to_mad_f32_0(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %gep.0
+  %b = load float, float addrspace(1)* %gep.1
+  %c = load float, float addrspace(1)* %gep.2
+
+  %mul = fmul float %a, %b
+  %fma = fadd float %mul, %c
+  store float %fma, float addrspace(1)* %gep.out
+  ret void
+}
+
+; (fadd (fmul x, y), z) -> (fma x, y, z)
+; FUNC-LABEL: {{^}}combine_to_mad_f32_0_2use:
+; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
+
+; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], [[C]]
+; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], [[D]]
+
+; SI-DENORM-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], [[C]]
+; SI-DENORM-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], [[D]]
+
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
+; SI-DENORM-SLOWFMAF-DAG: v_add_f32_e32 [[RESULT0:v[0-9]+]], [[C]], [[TMP]]
+; SI-DENORM-SLOWFMAF-DAG: v_add_f32_e32 [[RESULT1:v[0-9]+]], [[D]], [[TMP]]
+
+; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI: s_endpgm
+define void @combine_to_mad_f32_0_2use(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr float, float addrspace(1)* %gep.0, i32 3
+  %gep.out.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.out.1 = getelementptr float, float addrspace(1)* %gep.out.0, i32 1
+
+  %a = load float, float addrspace(1)* %gep.0
+  %b = load float, float addrspace(1)* %gep.1
+  %c = load float, float addrspace(1)* %gep.2
+  %d = load float, float addrspace(1)* %gep.3
+
+  %mul = fmul float %a, %b
+  %fma0 = fadd float %mul, %c
+  %fma1 = fadd float %mul, %d
+
+  store float %fma0, float addrspace(1)* %gep.out.0
+  store float %fma1, float addrspace(1)* %gep.out.1
+  ret void
+}
+
+; (fadd x, (fmul y, z)) -> (fma y, z, x)
+; FUNC-LABEL: {{^}}combine_to_mad_f32_1:
+; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+
+; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
+; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
+
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
+; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]]
+
+; SI: buffer_store_dword [[RESULT]]
+define void @combine_to_mad_f32_1(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %gep.0
+  %b = load float, float addrspace(1)* %gep.1
+  %c = load float, float addrspace(1)* %gep.2
+
+  %mul = fmul float %a, %b
+  %fma = fadd float %c, %mul
+  store float %fma, float addrspace(1)* %gep.out
+  ret void
+}
+
+; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
+; FUNC-LABEL: {{^}}combine_to_mad_fsub_0_f32:
+; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+
+; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], -[[C]]
+; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], -[[C]]
+
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
+; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP]]
+
+; SI: buffer_store_dword [[RESULT]]
+define void @combine_to_mad_fsub_0_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %gep.0
+  %b = load float, float addrspace(1)* %gep.1
+  %c = load float, float addrspace(1)* %gep.2
+
+  %mul = fmul float %a, %b
+  %fma = fsub float %mul, %c
+  store float %fma, float addrspace(1)* %gep.out
+  ret void
+}
+
+; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
+; FUNC-LABEL: {{^}}combine_to_mad_fsub_0_f32_2use:
+; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
+
+; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], -[[C]]
+; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
+
+; SI-DENORM-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], -[[C]]
+; SI-DENORM-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
+
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
+; SI-DENORM-SLOWFMAF-DAG: v_subrev_f32_e32 [[RESULT0:v[0-9]+]], [[C]], [[TMP]]
+; SI-DENORM-SLOWFMAF-DAG: v_subrev_f32_e32 [[RESULT1:v[0-9]+]], [[D]], [[TMP]]
+
+; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI: s_endpgm
+define void @combine_to_mad_fsub_0_f32_2use(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr float, float addrspace(1)* %gep.0, i32 3
+  %gep.out.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.out.1 = getelementptr float, float addrspace(1)* %gep.out.0, i32 1
+
+  %a = load float, float addrspace(1)* %gep.0
+  %b = load float, float addrspace(1)* %gep.1
+  %c = load float, float addrspace(1)* %gep.2
+  %d = load float, float addrspace(1)* %gep.3
+
+  %mul = fmul float %a, %b
+  %fma0 = fsub float %mul, %c
+  %fma1 = fsub float %mul, %d
+  store float %fma0, float addrspace(1)* %gep.out.0
+  store float %fma1, float addrspace(1)* %gep.out.1
+  ret void
+}
+
+; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
+; FUNC-LABEL: {{^}}combine_to_mad_fsub_1_f32:
+; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+
+; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], [[C]]
+; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], [[C]]
+
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
+; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]]
+
+; SI: buffer_store_dword [[RESULT]]
+define void @combine_to_mad_fsub_1_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %gep.0
+  %b = load float, float addrspace(1)* %gep.1
+  %c = load float, float addrspace(1)* %gep.2
+
+  %mul = fmul float %a, %b
+  %fma = fsub float %c, %mul
+  store float %fma, float addrspace(1)* %gep.out
+  ret void
+}
+
+; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
+; FUNC-LABEL: {{^}}combine_to_mad_fsub_1_f32_2use:
+; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+
+; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], [[C]]
+; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], [[D]]
+
+; SI-DENORM-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], [[C]]
+; SI-DENORM-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], [[D]]
+
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
+; SI-DENORM-SLOWFMAF-DAG: v_subrev_f32_e32 [[RESULT0:v[0-9]+]], [[TMP]], [[C]]
+; SI-DENORM-SLOWFMAF-DAG: v_subrev_f32_e32 [[RESULT1:v[0-9]+]], [[TMP]], [[D]]
+
+; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI: s_endpgm
+define void @combine_to_mad_fsub_1_f32_2use(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr float, float addrspace(1)* %gep.0, i32 3
+  %gep.out.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.out.1 = getelementptr float, float addrspace(1)* %gep.out.0, i32 1
+
+  %a = load float, float addrspace(1)* %gep.0
+  %b = load float, float addrspace(1)* %gep.1
+  %c = load float, float addrspace(1)* %gep.2
+  %d = load float, float addrspace(1)* %gep.3
+
+  %mul = fmul float %a, %b
+  %fma0 = fsub float %c, %mul
+  %fma1 = fsub float %d, %mul
+  store float %fma0, float addrspace(1)* %gep.out.0
+  store float %fma1, float addrspace(1)* %gep.out.1
+  ret void
+}
+
+; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
+; FUNC-LABEL: {{^}}combine_to_mad_fsub_2_f32:
+; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+
+; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], -[[C]]
+
+; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], -[[C]]
+
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
+; SI-DENORM-SLOWFMAF: v_sub_f32_e64 [[RESULT:v[0-9]+]], -[[TMP]], [[C]]
+
+; SI: buffer_store_dword [[RESULT]]
+define void @combine_to_mad_fsub_2_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %gep.0
+  %b = load float, float addrspace(1)* %gep.1
+  %c = load float, float addrspace(1)* %gep.2
+
+  %mul = fmul float %a, %b
+  %mul.neg = fsub float -0.0, %mul
+  %fma = fsub float %mul.neg, %c
+
+  store float %fma, float addrspace(1)* %gep.out
+  ret void
+}
+
+; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
+; FUNC-LABEL: {{^}}combine_to_mad_fsub_2_f32_2uses_neg:
+; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+
+; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]]
+; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], -[[D]]
+
+; SI-DENORM-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]]
+; SI-DENORM-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], -[[D]]
+
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
+; SI-DENORM-SLOWFMAF-DAG: v_sub_f32_e64 [[RESULT0:v[0-9]+]], -[[TMP]], [[C]]
+; SI-DENORM-SLOWFMAF-DAG: v_sub_f32_e64 [[RESULT1:v[0-9]+]], -[[TMP]], [[D]]
+
+; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI: s_endpgm
+define void @combine_to_mad_fsub_2_f32_2uses_neg(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr float, float addrspace(1)* %gep.0, i32 3
+  %gep.out.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.out.1 = getelementptr float, float addrspace(1)* %gep.out.0, i32 1
+
+  %a = load float, float addrspace(1)* %gep.0
+  %b = load float, float addrspace(1)* %gep.1
+  %c = load float, float addrspace(1)* %gep.2
+  %d = load float, float addrspace(1)* %gep.3
+
+  %mul = fmul float %a, %b
+  %mul.neg = fsub float -0.0, %mul
+  %fma0 = fsub float %mul.neg, %c
+  %fma1 = fsub float %mul.neg, %d
+
+  store float %fma0, float addrspace(1)* %gep.out.0
+  store float %fma1, float addrspace(1)* %gep.out.1
+  ret void
+}
+
+; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
+; FUNC-LABEL: {{^}}combine_to_mad_fsub_2_f32_2uses_mul:
+; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+
+; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]]
+; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
+
+; SI-DENORM-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]]
+; SI-DENORM-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
+
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
+; SI-DENORM-SLOWFMAF-DAG: v_sub_f32_e64 [[RESULT0:v[0-9]+]], -[[TMP]], [[C]]
+; SI-DENORM-SLOWFMAF-DAG: v_subrev_f32_e32 [[RESULT1:v[0-9]+]], [[D]], [[TMP]]
+
+; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI: s_endpgm
+define void @combine_to_mad_fsub_2_f32_2uses_mul(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr float, float addrspace(1)* %gep.0, i32 3
+  %gep.out.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.out.1 = getelementptr float, float addrspace(1)* %gep.out.0, i32 1
+
+  %a = load float, float addrspace(1)* %gep.0
+  %b = load float, float addrspace(1)* %gep.1
+  %c = load float, float addrspace(1)* %gep.2
+  %d = load float, float addrspace(1)* %gep.3
+
+  %mul = fmul float %a, %b
+  %mul.neg = fsub float -0.0, %mul
+  %fma0 = fsub float %mul.neg, %c
+  %fma1 = fsub float %mul, %d
+
+  store float %fma0, float addrspace(1)* %gep.out.0
+  store float %fma1, float addrspace(1)* %gep.out.1
+  ret void
+}
+
+; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z)))
+
+; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_0_f32:
+; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
+; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+
+; SI-STD: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]]
+; SI-STD: v_fma_f32 [[TMP1:v[0-9]+]], [[A]], [[B]], [[TMP0]]
+; SI-STD: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP1]]
+
+; SI-DENORM: v_fma_f32 [[TMP0:v[0-9]+]], [[D]], [[E]], -[[C]]
+; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[TMP0]]
+
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]]
+; SI-DENORM-SLOWFMAF: v_fma_f32 [[TMP1:v[0-9]+]], [[A]], [[B]], [[TMP0]]
+; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT1:v[0-9]+]], [[C]], [[TMP1]]
+
+; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+define void @aggressive_combine_to_mad_fsub_0_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr float, float addrspace(1)* %gep.0, i32 3
+  %gep.4 = getelementptr float, float addrspace(1)* %gep.0, i32 4
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %x = load float, float addrspace(1)* %gep.0
+  %y = load float, float addrspace(1)* %gep.1
+  %z = load float, float addrspace(1)* %gep.2
+  %u = load float, float addrspace(1)* %gep.3
+  %v = load float, float addrspace(1)* %gep.4
+
+  %tmp0 = fmul float %u, %v
+  %tmp1 = call float @llvm.fma.f32(float %x, float %y, float %tmp0) #0
+  %tmp2 = fsub float %tmp1, %z
+
+  store float %tmp2, float addrspace(1)* %gep.out
+  ret void
+}
+
+; fold (fsub x, (fma y, z, (fmul u, v)))
+;   -> (fma (fneg y), z, (fma (fneg u), v, x))
+
+; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_1_f32:
+; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
+; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+
+; SI-STD: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]]
+; SI-STD: v_fma_f32 [[TMP1:v[0-9]+]], [[B]], [[C]], [[TMP0]]
+; SI-STD: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[TMP1]], [[A]]
+
+; SI-DENORM: v_fma_f32 [[TMP0:v[0-9]+]], -[[D]], [[E]], [[A]]
+; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], -[[B]], [[C]], [[TMP0]]
+
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]]
+; SI-DENORM-SLOWFMAF: v_fma_f32 [[TMP1:v[0-9]+]], [[B]], [[C]], [[TMP0]]
+; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[TMP1]], [[A]]
+
+; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI: s_endpgm
+define void @aggressive_combine_to_mad_fsub_1_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr float, float addrspace(1)* %gep.0, i32 3
+  %gep.4 = getelementptr float, float addrspace(1)* %gep.0, i32 4
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %x = load float, float addrspace(1)* %gep.0
+  %y = load float, float addrspace(1)* %gep.1
+  %z = load float, float addrspace(1)* %gep.2
+  %u = load float, float addrspace(1)* %gep.3
+  %v = load float, float addrspace(1)* %gep.4
+
+  %tmp0 = fmul float %u, %v
+  %tmp1 = call float @llvm.fma.f32(float %y, float %z, float %tmp0) #0
+  %tmp2 = fsub float %x, %tmp1
+
+  store float %tmp2, float addrspace(1)* %gep.out
+  ret void
+}
+
+; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z)))
+
+; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_2_f32:
+; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
+; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+
+; SI-STD: v_mad_f32 [[TMP:v[0-9]+]], [[D]], [[E]], -[[C]]
+; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[TMP]]
+
+; SI-DENORM: v_fma_f32 [[TMP:v[0-9]+]], [[D]], [[E]], -[[C]]
+; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[TMP]]
+
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]]
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP1:v[0-9]+]], [[B]], [[A]]
+; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[TMP2:v[0-9]+]], [[TMP0]], [[TMP1]]
+; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP2]]
+
+; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI: s_endpgm
+define void @aggressive_combine_to_mad_fsub_2_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr float, float addrspace(1)* %gep.0, i32 3
+  %gep.4 = getelementptr float, float addrspace(1)* %gep.0, i32 4
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %x = load float, float addrspace(1)* %gep.0
+  %y = load float, float addrspace(1)* %gep.1
+  %z = load float, float addrspace(1)* %gep.2
+  %u = load float, float addrspace(1)* %gep.3
+  %v = load float, float addrspace(1)* %gep.4
+
+  %tmp0 = fmul float %u, %v
+  %tmp1 = call float @llvm.fmuladd.f32(float %x, float %y, float %tmp0) #0
+  %tmp2 = fsub float %tmp1, %z
+
+  store float %tmp2, float addrspace(1)* %gep.out
+  ret void
+}
+
+; fold (fsub x, (fmuladd y, z, (fmul u, v)))
+;   -> (fmuladd (fneg y), z, (fmuladd (fneg u), v, x))
+
+; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_3_f32:
+; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
+; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
+; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
+; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
+
+; SI-STD: v_mad_f32 [[TMP:v[0-9]+]], -[[D]], [[E]], [[A]]
+; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], -[[B]], [[C]], [[TMP]]
+
+; SI-DENORM: v_fma_f32 [[TMP:v[0-9]+]], -[[D]], [[E]], [[A]]
+; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], -[[B]], [[C]], [[TMP]]
+
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]]
+; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP1:v[0-9]+]], [[C]], [[B]]
+; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[TMP2:v[0-9]+]], [[TMP0]], [[TMP1]]
+; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[TMP2]], [[A]]
+
+; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; SI: s_endpgm
+define void @aggressive_combine_to_mad_fsub_3_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() #0
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
+  %gep.3 = getelementptr float, float addrspace(1)* %gep.0, i32 3
+  %gep.4 = getelementptr float, float addrspace(1)* %gep.0, i32 4
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %x = load float, float addrspace(1)* %gep.0
+  %y = load float, float addrspace(1)* %gep.1
+  %z = load float, float addrspace(1)* %gep.2
+  %u = load float, float addrspace(1)* %gep.3
+  %v = load float, float addrspace(1)* %gep.4
+
+  %tmp0 = fmul float %u, %v
+  %tmp1 = call float @llvm.fmuladd.f32(float %y, float %z, float %tmp0) #0
+  %tmp2 = fsub float %x, %tmp1
+
+  store float %tmp2, float addrspace(1)* %gep.out
+  ret void
+}
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }
diff --git a/test/CodeGen/R600/mad-sub.ll b/test/CodeGen/R600/mad-sub.ll
index 7b4020d2973c..aa4194ff6106 100644
--- a/test/CodeGen/R600/mad-sub.ll
+++ b/test/CodeGen/R600/mad-sub.ll
@@ -12,15 +12,15 @@ declare float @llvm.fabs.f32(float) #0
 define void @mad_sub_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
   %tid = tail call i32 @llvm.r600.read.tidig.x() #0
   %tid.ext = sext i32 %tid to i64
-  %gep0 = getelementptr float addrspace(1)* %ptr, i64 %tid.ext
+  %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
   %add1 = add i64 %tid.ext, 1
-  %gep1 = getelementptr float addrspace(1)* %ptr, i64 %add1
+  %gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
   %add2 = add i64 %tid.ext, 2
-  %gep2 = getelementptr float addrspace(1)* %ptr, i64 %add2
-  %outgep = getelementptr float addrspace(1)* %out, i64 %tid.ext
-  %a = load float addrspace(1)* %gep0, align 4
-  %b = load float addrspace(1)* %gep1, align 4
-  %c = load float addrspace(1)* %gep2, align 4
+  %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
+  %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
+  %a = load float, float addrspace(1)* %gep0, align 4
+  %b = load float, float addrspace(1)* %gep1, align 4
+  %c = load float, float addrspace(1)* %gep2, align 4
   %mul = fmul float %a, %b
   %sub = fsub float %mul, %c
   store float %sub, float addrspace(1)* %outgep, align 4
@@ -36,15 +36,15 @@ define void @mad_sub_f32(float addrspace(1)* noalias nocapture %out, float addrs
 define void @mad_sub_inv_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
   %tid = tail call i32 @llvm.r600.read.tidig.x() #0
   %tid.ext = sext i32 %tid to i64
-  %gep0 = getelementptr float addrspace(1)* %ptr, i64 %tid.ext
+  %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
   %add1 = add i64 %tid.ext, 1
-  %gep1 = getelementptr float addrspace(1)* %ptr, i64 %add1
+  %gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
   %add2 = add i64 %tid.ext, 2
-  %gep2 = getelementptr float addrspace(1)* %ptr, i64 %add2
-  %outgep = getelementptr float addrspace(1)* %out, i64 %tid.ext
-  %a = load float addrspace(1)* %gep0, align 4
-  %b = load float addrspace(1)* %gep1, align 4
-  %c = load float addrspace(1)* %gep2, align 4
+  %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
+  %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
+  %a = load float, float addrspace(1)* %gep0, align 4
+  %b = load float, float addrspace(1)* %gep1, align 4
+  %c = load float, float addrspace(1)* %gep2, align 4
   %mul = fmul float %a, %b
   %sub = fsub float %c, %mul
   store float %sub, float addrspace(1)* %outgep, align 4
@@ -57,15 +57,15 @@ define void @mad_sub_inv_f32(float addrspace(1)* noalias nocapture %out, float a
 define void @mad_sub_f64(double addrspace(1)* noalias nocapture %out, double addrspace(1)* noalias nocapture readonly %ptr) #1 {
   %tid = tail call i32 @llvm.r600.read.tidig.x() #0
   %tid.ext = sext i32 %tid to i64
-  %gep0 = getelementptr double addrspace(1)* %ptr, i64 %tid.ext
+  %gep0 = getelementptr double, double addrspace(1)* %ptr, i64 %tid.ext
   %add1 = add i64 %tid.ext, 1
-  %gep1 = getelementptr double addrspace(1)* %ptr, i64 %add1
+  %gep1 = getelementptr double, double addrspace(1)* %ptr, i64 %add1
   %add2 = add i64 %tid.ext, 2
-  %gep2 = getelementptr double addrspace(1)* %ptr, i64 %add2
-  %outgep = getelementptr double addrspace(1)* %out, i64 %tid.ext
-  %a = load double addrspace(1)* %gep0, align 8
-  %b = load double addrspace(1)* %gep1, align 8
-  %c = load double addrspace(1)* %gep2, align 8
+  %gep2 = getelementptr double, double addrspace(1)* %ptr, i64 %add2
+  %outgep = getelementptr double, double addrspace(1)* %out, i64 %tid.ext
+  %a = load double, double addrspace(1)* %gep0, align 8
+  %b = load double, double addrspace(1)* %gep1, align 8
+  %c = load double, double addrspace(1)* %gep2, align 8
   %mul = fmul double %a, %b
   %sub = fsub double %mul, %c
   store double %sub, double addrspace(1)* %outgep, align 8
@@ -81,15 +81,15 @@ define void @mad_sub_f64(double addrspace(1)* noalias nocapture %out, double add
 define void @mad_sub_fabs_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
   %tid = tail call i32 @llvm.r600.read.tidig.x() #0
   %tid.ext = sext i32 %tid to i64
-  %gep0 = getelementptr float addrspace(1)* %ptr, i64 %tid.ext
+  %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
   %add1 = add i64 %tid.ext, 1
-  %gep1 = getelementptr float addrspace(1)* %ptr, i64 %add1
+  %gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
   %add2 = add i64 %tid.ext, 2
-  %gep2 = getelementptr float addrspace(1)* %ptr, i64 %add2
-  %outgep = getelementptr float addrspace(1)* %out, i64 %tid.ext
-  %a = load float addrspace(1)* %gep0, align 4
-  %b = load float addrspace(1)* %gep1, align 4
-  %c = load float addrspace(1)* %gep2, align 4
+  %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
+  %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
+  %a = load float, float addrspace(1)* %gep0, align 4
+  %b = load float, float addrspace(1)* %gep1, align 4
+  %c = load float, float addrspace(1)* %gep2, align 4
   %c.abs = call float @llvm.fabs.f32(float %c) #0
   %mul = fmul float %a, %b
   %sub = fsub float %mul, %c.abs
@@ -106,15 +106,15 @@ define void @mad_sub_fabs_f32(float addrspace(1)* noalias nocapture %out, float
 define void @mad_sub_fabs_inv_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
   %tid = tail call i32 @llvm.r600.read.tidig.x() #0
   %tid.ext = sext i32 %tid to i64
-  %gep0 = getelementptr float addrspace(1)* %ptr, i64 %tid.ext
+  %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
   %add1 = add i64 %tid.ext, 1
-  %gep1 = getelementptr float addrspace(1)* %ptr, i64 %add1
+  %gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
   %add2 = add i64 %tid.ext, 2
-  %gep2 = getelementptr float addrspace(1)* %ptr, i64 %add2
-  %outgep = getelementptr float addrspace(1)* %out, i64 %tid.ext
-  %a = load float addrspace(1)* %gep0, align 4
-  %b = load float addrspace(1)* %gep1, align 4
-  %c = load float addrspace(1)* %gep2, align 4
+  %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
+  %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
+  %a = load float, float addrspace(1)* %gep0, align 4
+  %b = load float, float addrspace(1)* %gep1, align 4
+  %c = load float, float addrspace(1)* %gep2, align 4
   %c.abs = call float @llvm.fabs.f32(float %c) #0
   %mul = fmul float %a, %b
   %sub = fsub float %c.abs, %mul
@@ -127,15 +127,15 @@ define void @mad_sub_fabs_inv_f32(float addrspace(1)* noalias nocapture %out, fl
 define void @neg_neg_mad_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
   %tid = tail call i32 @llvm.r600.read.tidig.x() #0
   %tid.ext = sext i32 %tid to i64
-  %gep0 = getelementptr float addrspace(1)* %ptr, i64 %tid.ext
+  %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
   %add1 = add i64 %tid.ext, 1
-  %gep1 = getelementptr float addrspace(1)* %ptr, i64 %add1
+  %gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
   %add2 = add i64 %tid.ext, 2
-  %gep2 = getelementptr float addrspace(1)* %ptr, i64 %add2
-  %outgep = getelementptr float addrspace(1)* %out, i64 %tid.ext
-  %a = load float addrspace(1)* %gep0, align 4
-  %b = load float addrspace(1)* %gep1, align 4
-  %c = load float addrspace(1)* %gep2, align 4
+  %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
+  %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
+  %a = load float, float addrspace(1)* %gep0, align 4
+  %b = load float, float addrspace(1)* %gep1, align 4
+  %c = load float, float addrspace(1)* %gep2, align 4
   %nega = fsub float -0.000000e+00, %a
   %negb = fsub float -0.000000e+00, %b
   %mul = fmul float %nega, %negb
@@ -153,15 +153,15 @@ define void @neg_neg_mad_f32(float addrspace(1)* noalias nocapture %out, float a
 define void @mad_fabs_sub_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
   %tid = tail call i32 @llvm.r600.read.tidig.x() #0
   %tid.ext = sext i32 %tid to i64
-  %gep0 = getelementptr float addrspace(1)* %ptr, i64 %tid.ext
+  %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
   %add1 = add i64 %tid.ext, 1
-  %gep1 = getelementptr float addrspace(1)* %ptr, i64 %add1
+  %gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
   %add2 = add i64 %tid.ext, 2
-  %gep2 = getelementptr float addrspace(1)* %ptr, i64 %add2
-  %outgep = getelementptr float addrspace(1)* %out, i64 %tid.ext
-  %a = load float addrspace(1)* %gep0, align 4
-  %b = load float addrspace(1)* %gep1, align 4
-  %c = load float addrspace(1)* %gep2, align 4
+  %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
+  %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
+  %a = load float, float addrspace(1)* %gep0, align 4
+  %b = load float, float addrspace(1)* %gep1, align 4
+  %c = load float, float addrspace(1)* %gep2, align 4
   %b.abs = call float @llvm.fabs.f32(float %b) #0
   %mul = fmul float %a, %b.abs
   %sub = fsub float %mul, %c
@@ -176,12 +176,12 @@ define void @mad_fabs_sub_f32(float addrspace(1)* noalias nocapture %out, float
 ; SI: buffer_store_dword [[RESULT]]
 define void @fsub_c_fadd_a_a(float addrspace(1)* %out, float addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %gep.out = getelementptr float addrspace(1)* %out, i32 %tid
+  %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
 
-  %r1 = load float addrspace(1)* %gep.0
-  %r2 = load float addrspace(1)* %gep.1
+  %r1 = load float, float addrspace(1)* %gep.0
+  %r2 = load float, float addrspace(1)* %gep.1
 
   %add = fadd float %r1, %r1
   %r3 = fsub float %r2, %add
@@ -197,12 +197,12 @@ define void @fsub_c_fadd_a_a(float addrspace(1)* %out, float addrspace(1)* %in)
 ; SI: buffer_store_dword [[RESULT]]
 define void @fsub_fadd_a_a_c(float addrspace(1)* %out, float addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %gep.out = getelementptr float addrspace(1)* %out, i32 %tid
+  %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
 
-  %r1 = load float addrspace(1)* %gep.0
-  %r2 = load float addrspace(1)* %gep.1
+  %r1 = load float, float addrspace(1)* %gep.0
+  %r2 = load float, float addrspace(1)* %gep.1
 
   %add = fadd float %r1, %r1
   %r3 = fsub float %add, %r2
diff --git a/test/CodeGen/R600/madak.ll b/test/CodeGen/R600/madak.ll
new file mode 100644
index 000000000000..933bb016d2c9
--- /dev/null
+++ b/test/CodeGen/R600/madak.ll
@@ -0,0 +1,193 @@
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
+; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
+
+; FIXME: Enable VI
+
+declare i32 @llvm.r600.read.tidig.x() nounwind readnone
+declare float @llvm.fabs.f32(float) nounwind readnone
+
+; GCN-LABEL: {{^}}madak_f32:
+; GCN: buffer_load_dword [[VA:v[0-9]+]]
+; GCN: buffer_load_dword [[VB:v[0-9]+]]
+; GCN: v_madak_f32_e32 {{v[0-9]+}}, [[VB]], [[VA]], 0x41200000
+define void @madak_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+  %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
+  %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %in.a.gep, align 4
+  %b = load float, float addrspace(1)* %in.b.gep, align 4
+
+  %mul = fmul float %a, %b
+  %madak = fadd float %mul, 10.0
+  store float %madak, float addrspace(1)* %out.gep, align 4
+  ret void
+}
+
+; Make sure this is only folded with one use. This is a code size
+; optimization and if we fold the immediate multiple times, we'll undo
+; it.
+
+; GCN-LABEL: {{^}}madak_2_use_f32:
+; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
+; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
+; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
+; GCN-DAG: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VB]], [[VK]]
+; GCN-DAG: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VC]], [[VK]]
+; GCN: s_endpgm
+define void @madak_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+
+  %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
+  %in.gep.2 = getelementptr float, float addrspace(1)* %in.gep.0, i32 2
+
+  %out.gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %out.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
+
+  %a = load float, float addrspace(1)* %in.gep.0, align 4
+  %b = load float, float addrspace(1)* %in.gep.1, align 4
+  %c = load float, float addrspace(1)* %in.gep.2, align 4
+
+  %mul0 = fmul float %a, %b
+  %mul1 = fmul float %a, %c
+  %madak0 = fadd float %mul0, 10.0
+  %madak1 = fadd float %mul1, 10.0
+
+  store float %madak0, float addrspace(1)* %out.gep.0, align 4
+  store float %madak1, float addrspace(1)* %out.gep.1, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}madak_m_inline_imm_f32:
+; GCN: buffer_load_dword [[VA:v[0-9]+]]
+; GCN: v_madak_f32_e32 {{v[0-9]+}}, 4.0, [[VA]], 0x41200000
+define void @madak_m_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+  %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %in.a.gep, align 4
+
+  %mul = fmul float 4.0, %a
+  %madak = fadd float %mul, 10.0
+  store float %madak, float addrspace(1)* %out.gep, align 4
+  ret void
+}
+
+; Make sure nothing weird happens with a value that is also allowed as
+; an inline immediate.
+
+; GCN-LABEL: {{^}}madak_inline_imm_f32:
+; GCN: buffer_load_dword [[VA:v[0-9]+]]
+; GCN: buffer_load_dword [[VB:v[0-9]+]]
+; GCN: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VB]], 4.0
+define void @madak_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+  %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
+  %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %in.a.gep, align 4
+  %b = load float, float addrspace(1)* %in.b.gep, align 4
+
+  %mul = fmul float %a, %b
+  %madak = fadd float %mul, 4.0
+  store float %madak, float addrspace(1)* %out.gep, align 4
+  ret void
+}
+
+; We can't use an SGPR when forming madak
+; GCN-LABEL: {{^}}s_v_madak_f32:
+; GCN: s_load_dword [[SB:s[0-9]+]]
+; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
+; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]]
+; GCN-NOT: v_madak_f32
+; GCN: v_mad_f32 {{v[0-9]+}}, [[SB]], [[VA]], [[VK]]
+define void @s_v_madak_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float %b) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+  %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %in.a.gep, align 4
+
+  %mul = fmul float %a, %b
+  %madak = fadd float %mul, 10.0
+  store float %madak, float addrspace(1)* %out.gep, align 4
+  ret void
+}
+
+; GCN-LABEL: @v_s_madak_f32
+; GCN-DAG: s_load_dword [[SB:s[0-9]+]]
+; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
+; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]]
+; GCN-NOT: v_madak_f32
+; GCN: v_mad_f32 {{v[0-9]+}}, [[VA]], [[SB]], [[VK]]
+define void @v_s_madak_f32(float addrspace(1)* noalias %out, float %a, float addrspace(1)* noalias %in.b) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+  %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %b = load float, float addrspace(1)* %in.b.gep, align 4
+
+  %mul = fmul float %a, %b
+  %madak = fadd float %mul, 10.0
+  store float %madak, float addrspace(1)* %out.gep, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}s_s_madak_f32:
+; GCN-NOT: v_madak_f32
+; GCN: v_mad_f32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+define void @s_s_madak_f32(float addrspace(1)* %out, float %a, float %b) nounwind {
+  %mul = fmul float %a, %b
+  %madak = fadd float %mul, 10.0
+  store float %madak, float addrspace(1)* %out, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}no_madak_src0_modifier_f32:
+; GCN: buffer_load_dword [[VA:v[0-9]+]]
+; GCN: buffer_load_dword [[VB:v[0-9]+]]
+; GCN: v_mad_f32 {{v[0-9]+}}, |{{v[0-9]+}}|, {{v[0-9]+}}, {{[sv][0-9]+}}
+; GCN: s_endpgm
+define void @no_madak_src0_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+  %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
+  %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %in.a.gep, align 4
+  %b = load float, float addrspace(1)* %in.b.gep, align 4
+
+  %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone
+
+  %mul = fmul float %a.fabs, %b
+  %madak = fadd float %mul, 10.0
+  store float %madak, float addrspace(1)* %out.gep, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}no_madak_src1_modifier_f32:
+; GCN: buffer_load_dword [[VA:v[0-9]+]]
+; GCN: buffer_load_dword [[VB:v[0-9]+]]
+; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, |{{v[0-9]+}}|, {{[sv][0-9]+}}
+; GCN: s_endpgm
+define void @no_madak_src1_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+  %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
+  %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %in.a.gep, align 4
+  %b = load float, float addrspace(1)* %in.b.gep, align 4
+
+  %b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone
+
+  %mul = fmul float %a, %b.fabs
+  %madak = fadd float %mul, 10.0
+  store float %madak, float addrspace(1)* %out.gep, align 4
+  ret void
+}
diff --git a/test/CodeGen/R600/madmk.ll b/test/CodeGen/R600/madmk.ll
new file mode 100644
index 000000000000..ba7bb221a99a
--- /dev/null
+++ b/test/CodeGen/R600/madmk.ll
@@ -0,0 +1,205 @@
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+declare i32 @llvm.r600.read.tidig.x() nounwind readnone
+declare float @llvm.fabs.f32(float) nounwind readnone
+
+; GCN-LABEL: {{^}}madmk_f32:
+; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
+; GCN: v_madmk_f32_e32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000
+define void @madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
+
+  %mul = fmul float %a, 10.0
+  %madmk = fadd float %mul, %b
+  store float %madmk, float addrspace(1)* %out.gep, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}madmk_2_use_f32:
+; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
+; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
+; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
+; GCN-DAG: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VK]], [[VB]]
+; GCN-DAG: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VK]], [[VC]]
+; GCN: s_endpgm
+define void @madmk_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+
+  %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
+  %in.gep.2 = getelementptr float, float addrspace(1)* %in.gep.0, i32 2
+
+  %out.gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %out.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
+
+  %a = load float, float addrspace(1)* %in.gep.0, align 4
+  %b = load float, float addrspace(1)* %in.gep.1, align 4
+  %c = load float, float addrspace(1)* %in.gep.2, align 4
+
+  %mul0 = fmul float %a, 10.0
+  %mul1 = fmul float %a, 10.0
+  %madmk0 = fadd float %mul0, %b
+  %madmk1 = fadd float %mul1, %c
+
+  store float %madmk0, float addrspace(1)* %out.gep.0, align 4
+  store float %madmk1, float addrspace(1)* %out.gep.1, align 4
+  ret void
+}
+
+; We don't get any benefit if the constant is an inline immediate.
+; GCN-LABEL: {{^}}madmk_inline_imm_f32:
+; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
+; GCN: v_mad_f32 {{v[0-9]+}}, 4.0, [[VA]], [[VB]]
+define void @madmk_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
+
+  %mul = fmul float %a, 4.0
+  %madmk = fadd float %mul, %b
+  store float %madmk, float addrspace(1)* %out.gep, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}s_s_madmk_f32:
+; GCN-NOT: v_madmk_f32
+; GCN: v_mad_f32
+; GCN: s_endpgm
+define void @s_s_madmk_f32(float addrspace(1)* noalias %out, float %a, float %b) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %mul = fmul float %a, 10.0
+  %madmk = fadd float %mul, %b
+  store float %madmk, float addrspace(1)* %out.gep, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}v_s_madmk_f32:
+; GCN-NOT: v_madmk_f32
+; GCN: v_mad_f32
+; GCN: s_endpgm
+define void @v_s_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %b) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %a = load float, float addrspace(1)* %gep.0, align 4
+
+  %mul = fmul float %a, 10.0
+  %madmk = fadd float %mul, %b
+  store float %madmk, float addrspace(1)* %out.gep, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}scalar_vector_madmk_f32:
+; GCN-NOT: v_madmk_f32
+; GCN: v_mad_f32
+; GCN: s_endpgm
+define void @scalar_vector_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %a) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %b = load float, float addrspace(1)* %gep.0, align 4
+
+  %mul = fmul float %a, 10.0
+  %madmk = fadd float %mul, %b
+  store float %madmk, float addrspace(1)* %out.gep, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}no_madmk_src0_modifier_f32:
+; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
+; GCN: v_mad_f32 {{v[0-9]+}}, |{{v[0-9]+}}|, {{v[0-9]+}}, {{[sv][0-9]+}}
+define void @no_madmk_src0_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
+
+  %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone
+
+  %mul = fmul float %a.fabs, 10.0
+  %madmk = fadd float %mul, %b
+  store float %madmk, float addrspace(1)* %out.gep, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}no_madmk_src2_modifier_f32:
+; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
+; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, |{{[sv][0-9]+}}|
+define void @no_madmk_src2_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %gep.0, align 4
+  %b = load float, float addrspace(1)* %gep.1, align 4
+
+  %b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone
+
+  %mul = fmul float %a, 10.0
+  %madmk = fadd float %mul, %b.fabs
+  store float %madmk, float addrspace(1)* %out.gep, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}madmk_add_inline_imm_f32:
+; GCN: buffer_load_dword [[A:v[0-9]+]]
+; GCN: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
+; GCN: v_mad_f32 {{v[0-9]+}}, [[VK]], [[A]], 2.0
+define void @madmk_add_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
+  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+
+  %a = load float, float addrspace(1)* %gep.0, align 4
+
+  %mul = fmul float %a, 10.0
+  %madmk = fadd float %mul, 2.0
+  store float %madmk, float addrspace(1)* %out.gep, align 4
+  ret void
+}
+
+; SI-LABEL: {{^}}kill_madmk_verifier_error:
+; SI: s_xor_b64
+; SI: v_madmk_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, 0x472aee8c
+; SI: s_or_b64
+define void @kill_madmk_verifier_error() nounwind {
+bb:
+  br label %bb2
+
+bb1:                                              ; preds = %bb2
+  ret void
+
+bb2:                                              ; preds = %bb6, %bb
+  %tmp = phi float [ undef, %bb ], [ %tmp8, %bb6 ]
+  %tmp3 = fsub float undef, %tmp
+  %tmp5 = fcmp oeq float %tmp3, 1.000000e+04
+  br i1 %tmp5, label %bb1, label %bb6
+
+bb6:                                              ; preds = %bb2
+  %tmp4 = fmul float %tmp, undef
+  %tmp7 = fmul float %tmp4, 0x40E55DD180000000
+  %tmp8 = fadd float %tmp7, undef
+  br label %bb2
+}
diff --git a/test/CodeGen/R600/max.ll b/test/CodeGen/R600/max.ll
index 20af99332453..1aa9e6883011 100644
--- a/test/CodeGen/R600/max.ll
+++ b/test/CodeGen/R600/max.ll
@@ -6,11 +6,11 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone
 ; SI: v_max_i32_e32
 define void @v_test_imax_sge_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
-  %gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
-  %outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load i32 addrspace(1)* %gep0, align 4
-  %b = load i32 addrspace(1)* %gep1, align 4
+  %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
+  %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load i32, i32 addrspace(1)* %gep0, align 4
+  %b = load i32, i32 addrspace(1)* %gep1, align 4
   %cmp = icmp sge i32 %a, %b
   %val = select i1 %cmp, i32 %a, i32 %b
   store i32 %val, i32 addrspace(1)* %outgep, align 4
@@ -26,15 +26,33 @@ define void @s_test_imax_sge_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin
   ret void
 }
 
+; FUNC-LABEL: {{^}}s_test_imax_sge_imm_i32:
+; SI: s_max_i32 {{s[0-9]+}}, {{s[0-9]+}}, 9
+define void @s_test_imax_sge_imm_i32(i32 addrspace(1)* %out, i32 %a) nounwind {
+  %cmp = icmp sge i32 %a, 9
+  %val = select i1 %cmp, i32 %a, i32 9
+  store i32 %val, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+; FUNC-LABEL: {{^}}s_test_imax_sgt_imm_i32:
+; SI: s_max_i32 {{s[0-9]+}}, {{s[0-9]+}}, 9
+define void @s_test_imax_sgt_imm_i32(i32 addrspace(1)* %out, i32 %a) nounwind {
+  %cmp = icmp sgt i32 %a, 9
+  %val = select i1 %cmp, i32 %a, i32 9
+  store i32 %val, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
 ; FUNC-LABEL: @v_test_imax_sgt_i32
 ; SI: v_max_i32_e32
 define void @v_test_imax_sgt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
-  %gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
-  %outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load i32 addrspace(1)* %gep0, align 4
-  %b = load i32 addrspace(1)* %gep1, align 4
+  %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
+  %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load i32, i32 addrspace(1)* %gep0, align 4
+  %b = load i32, i32 addrspace(1)* %gep1, align 4
   %cmp = icmp sgt i32 %a, %b
   %val = select i1 %cmp, i32 %a, i32 %b
   store i32 %val, i32 addrspace(1)* %outgep, align 4
@@ -54,11 +72,11 @@ define void @s_test_imax_sgt_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin
 ; SI: v_max_u32_e32
 define void @v_test_umax_uge_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
-  %gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
-  %outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load i32 addrspace(1)* %gep0, align 4
-  %b = load i32 addrspace(1)* %gep1, align 4
+  %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
+  %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load i32, i32 addrspace(1)* %gep0, align 4
+  %b = load i32, i32 addrspace(1)* %gep1, align 4
   %cmp = icmp uge i32 %a, %b
   %val = select i1 %cmp, i32 %a, i32 %b
   store i32 %val, i32 addrspace(1)* %outgep, align 4
@@ -78,11 +96,11 @@ define void @s_test_umax_uge_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin
 ; SI: v_max_u32_e32
 define void @v_test_umax_ugt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
-  %gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
-  %outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load i32 addrspace(1)* %gep0, align 4
-  %b = load i32 addrspace(1)* %gep1, align 4
+  %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
+  %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load i32, i32 addrspace(1)* %gep0, align 4
+  %b = load i32, i32 addrspace(1)* %gep1, align 4
   %cmp = icmp ugt i32 %a, %b
   %val = select i1 %cmp, i32 %a, i32 %b
   store i32 %val, i32 addrspace(1)* %outgep, align 4
diff --git a/test/CodeGen/R600/max3.ll b/test/CodeGen/R600/max3.ll
index f905e171b334..cfb94b272e51 100644
--- a/test/CodeGen/R600/max3.ll
+++ b/test/CodeGen/R600/max3.ll
@@ -6,13 +6,13 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone
 ; SI: v_max3_i32
 define void @v_test_imax3_sgt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
-  %gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
-  %gep2 = getelementptr i32 addrspace(1)* %cptr, i32 %tid
-  %outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load i32 addrspace(1)* %gep0, align 4
-  %b = load i32 addrspace(1)* %gep1, align 4
-  %c = load i32 addrspace(1)* %gep2, align 4
+  %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i32, i32 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load i32, i32 addrspace(1)* %gep0, align 4
+  %b = load i32, i32 addrspace(1)* %gep1, align 4
+  %c = load i32, i32 addrspace(1)* %gep2, align 4
   %icmp0 = icmp sgt i32 %a, %b
   %i0 = select i1 %icmp0, i32 %a, i32 %b
   %icmp1 = icmp sgt i32 %i0, %c
@@ -25,13 +25,13 @@ define void @v_test_imax3_sgt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %apt
 ; SI: v_max3_u32
 define void @v_test_umax3_ugt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
-  %gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
-  %gep2 = getelementptr i32 addrspace(1)* %cptr, i32 %tid
-  %outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load i32 addrspace(1)* %gep0, align 4
-  %b = load i32 addrspace(1)* %gep1, align 4
-  %c = load i32 addrspace(1)* %gep2, align 4
+  %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i32, i32 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load i32, i32 addrspace(1)* %gep0, align 4
+  %b = load i32, i32 addrspace(1)* %gep1, align 4
+  %c = load i32, i32 addrspace(1)* %gep2, align 4
   %icmp0 = icmp ugt i32 %a, %b
   %i0 = select i1 %icmp0, i32 %a, i32 %b
   %icmp1 = icmp ugt i32 %i0, %c
diff --git a/test/CodeGen/R600/merge-stores.ll b/test/CodeGen/R600/merge-stores.ll
new file mode 100644
index 000000000000..dbf9d4481ffb
--- /dev/null
+++ b/test/CodeGen/R600/merge-stores.ll
@@ -0,0 +1,536 @@
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
+
+; Run with devices with different unaligned load restrictions.
+
+; TODO: Vector element tests
+; TODO: Non-zero base offset for load and store combinations
+; TODO: Same base addrspacecasted
+
+
+; GCN-LABEL: {{^}}merge_global_store_2_constants_i8:
+; GCN: buffer_store_byte
+; GCN: buffer_store_byte
+; GCN: s_endpgm
+define void @merge_global_store_2_constants_i8(i8 addrspace(1)* %out) #0 {
+  %out.gep.1 = getelementptr i8, i8 addrspace(1)* %out, i32 1
+
+  store i8 123, i8 addrspace(1)* %out.gep.1
+  store i8 456, i8 addrspace(1)* %out, align 2
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_2_constants_i8_natural_align:
+; GCN: buffer_store_byte
+; GCN: buffer_store_byte
+; GCN: s_endpgm
+define void @merge_global_store_2_constants_i8_natural_align(i8 addrspace(1)* %out) #0 {
+  %out.gep.1 = getelementptr i8, i8 addrspace(1)* %out, i32 1
+
+  store i8 123, i8 addrspace(1)* %out.gep.1
+  store i8 456, i8 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_2_constants_i16:
+; GCN: buffer_store_dword v
+define void @merge_global_store_2_constants_i16(i16 addrspace(1)* %out) #0 {
+  %out.gep.1 = getelementptr i16, i16 addrspace(1)* %out, i32 1
+
+  store i16 123, i16 addrspace(1)* %out.gep.1
+  store i16 456, i16 addrspace(1)* %out, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_2_constants_0_i16:
+; GCN: buffer_store_dword v
+define void @merge_global_store_2_constants_0_i16(i16 addrspace(1)* %out) #0 {
+  %out.gep.1 = getelementptr i16, i16 addrspace(1)* %out, i32 1
+
+  store i16 0, i16 addrspace(1)* %out.gep.1
+  store i16 0, i16 addrspace(1)* %out, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_2_constants_i16_natural_align:
+; GCN: buffer_store_short
+; GCN: buffer_store_short
+; GCN: s_endpgm
+define void @merge_global_store_2_constants_i16_natural_align(i16 addrspace(1)* %out) #0 {
+  %out.gep.1 = getelementptr i16, i16 addrspace(1)* %out, i32 1
+
+  store i16 123, i16 addrspace(1)* %out.gep.1
+  store i16 456, i16 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_2_constants_i32:
+; SI-DAG: s_movk_i32 [[SLO:s[0-9]+]], 0x1c8
+; SI-DAG: s_movk_i32 [[SHI:s[0-9]+]], 0x7b
+; SI-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[SLO]]
+; SI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHI]]
+; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
+define void @merge_global_store_2_constants_i32(i32 addrspace(1)* %out) #0 {
+  %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
+
+  store i32 123, i32 addrspace(1)* %out.gep.1
+  store i32 456, i32 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_2_constants_i32_f32:
+; GCN: buffer_store_dwordx2
+define void @merge_global_store_2_constants_i32_f32(i32 addrspace(1)* %out) #0 {
+  %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
+  %out.gep.1.bc = bitcast i32 addrspace(1)* %out.gep.1 to float addrspace(1)*
+  store float 1.0, float addrspace(1)* %out.gep.1.bc
+  store i32 456, i32 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_2_constants_f32_i32:
+; GCN: buffer_store_dwordx2
+define void @merge_global_store_2_constants_f32_i32(float addrspace(1)* %out) #0 {
+  %out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
+  %out.gep.1.bc = bitcast float addrspace(1)* %out.gep.1 to i32 addrspace(1)*
+  store i32 123, i32 addrspace(1)* %out.gep.1.bc
+  store float 4.0, float addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_4_constants_i32:
+; GCN: buffer_store_dwordx4
+define void @merge_global_store_4_constants_i32(i32 addrspace(1)* %out) #0 {
+  %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
+  %out.gep.2 = getelementptr i32, i32 addrspace(1)* %out, i32 2
+  %out.gep.3 = getelementptr i32, i32 addrspace(1)* %out, i32 3
+
+  store i32 123, i32 addrspace(1)* %out.gep.1
+  store i32 456, i32 addrspace(1)* %out.gep.2
+  store i32 333, i32 addrspace(1)* %out.gep.3
+  store i32 1234, i32 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_4_constants_f32_order:
+; XGCN: buffer_store_dwordx4
+; GCN: buffer_store_dword v
+; GCN: buffer_store_dword v
+; GCN: buffer_store_dwordx2 v
+define void @merge_global_store_4_constants_f32_order(float addrspace(1)* %out) #0 {
+  %out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
+  %out.gep.2 = getelementptr float, float addrspace(1)* %out, i32 2
+  %out.gep.3 = getelementptr float, float addrspace(1)* %out, i32 3
+
+  store float 8.0, float addrspace(1)* %out
+  store float 1.0, float addrspace(1)* %out.gep.1
+  store float 2.0, float addrspace(1)* %out.gep.2
+  store float 4.0, float addrspace(1)* %out.gep.3
+  ret void
+}
+
+; First store is out of order. Because of order of combines, the
+; consecutive store fails because only some of the stores have been
+; replaced with integer constant stores, and then won't merge because
+; the types are different.
+
+; GCN-LABEL: {{^}}merge_global_store_4_constants_f32:
+; XGCN: buffer_store_dwordx4
+; GCN: buffer_store_dword v
+; GCN: buffer_store_dword v
+; GCN: buffer_store_dword v
+; GCN: buffer_store_dword v
+define void @merge_global_store_4_constants_f32(float addrspace(1)* %out) #0 {
+  %out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
+  %out.gep.2 = getelementptr float, float addrspace(1)* %out, i32 2
+  %out.gep.3 = getelementptr float, float addrspace(1)* %out, i32 3
+
+  store float 1.0, float addrspace(1)* %out.gep.1
+  store float 2.0, float addrspace(1)* %out.gep.2
+  store float 4.0, float addrspace(1)* %out.gep.3
+  store float 8.0, float addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_3_constants_i32:
+; SI-DAG: buffer_store_dwordx2
+; SI-DAG: buffer_store_dword
+; SI-NOT: buffer_store_dword
+; GCN: s_endpgm
+define void @merge_global_store_3_constants_i32(i32 addrspace(1)* %out) #0 {
+  %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
+  %out.gep.2 = getelementptr i32, i32 addrspace(1)* %out, i32 2
+
+  store i32 123, i32 addrspace(1)* %out.gep.1
+  store i32 456, i32 addrspace(1)* %out.gep.2
+  store i32 1234, i32 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_2_constants_i64:
+; XGCN: buffer_store_dwordx4
+; GCN: buffer_store_dwordx2
+; GCN: buffer_store_dwordx2
+define void @merge_global_store_2_constants_i64(i64 addrspace(1)* %out) #0 {
+  %out.gep.1 = getelementptr i64, i64 addrspace(1)* %out, i64 1
+
+  store i64 123, i64 addrspace(1)* %out.gep.1
+  store i64 456, i64 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_4_constants_i64:
+; XGCN: buffer_store_dwordx4
+; XGCN: buffer_store_dwordx4
+
+; GCN: buffer_store_dwordx2
+; GCN: buffer_store_dwordx2
+; GCN: buffer_store_dwordx2
+; GCN: buffer_store_dwordx2
+define void @merge_global_store_4_constants_i64(i64 addrspace(1)* %out) #0 {
+  %out.gep.1 = getelementptr i64, i64 addrspace(1)* %out, i64 1
+  %out.gep.2 = getelementptr i64, i64 addrspace(1)* %out, i64 2
+  %out.gep.3 = getelementptr i64, i64 addrspace(1)* %out, i64 3
+
+  store i64 123, i64 addrspace(1)* %out.gep.1
+  store i64 456, i64 addrspace(1)* %out.gep.2
+  store i64 333, i64 addrspace(1)* %out.gep.3
+  store i64 1234, i64 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_2_adjacent_loads_i32:
+; GCN: buffer_load_dwordx2 [[LOAD:v\[[0-9]+:[0-9]+\]]]
+; GCN: buffer_store_dwordx2 [[LOAD]]
+define void @merge_global_store_2_adjacent_loads_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
+  %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
+  %in.gep.1 = getelementptr i32, i32 addrspace(1)* %in, i32 1
+
+  %lo = load i32, i32 addrspace(1)* %in
+  %hi = load i32, i32 addrspace(1)* %in.gep.1
+
+  store i32 %lo, i32 addrspace(1)* %out
+  store i32 %hi, i32 addrspace(1)* %out.gep.1
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_2_adjacent_loads_i32_nonzero_base:
+; GCN: buffer_load_dwordx2 [[LOAD:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8
+; GCN: buffer_store_dwordx2 [[LOAD]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8
+define void @merge_global_store_2_adjacent_loads_i32_nonzero_base(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
+  %in.gep.0 = getelementptr i32, i32 addrspace(1)* %in, i32 2
+  %in.gep.1 = getelementptr i32, i32 addrspace(1)* %in, i32 3
+
+  %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i32 2
+  %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 3
+  %lo = load i32, i32 addrspace(1)* %in.gep.0
+  %hi = load i32, i32 addrspace(1)* %in.gep.1
+
+  store i32 %lo, i32 addrspace(1)* %out.gep.0
+  store i32 %hi, i32 addrspace(1)* %out.gep.1
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_2_adjacent_loads_shuffle_i32:
+; GCN: buffer_load_dword v
+; GCN: buffer_load_dword v
+; GCN: buffer_store_dword v
+; GCN: buffer_store_dword v
+define void @merge_global_store_2_adjacent_loads_shuffle_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
+  %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
+  %in.gep.1 = getelementptr i32, i32 addrspace(1)* %in, i32 1
+
+  %lo = load i32, i32 addrspace(1)* %in
+  %hi = load i32, i32 addrspace(1)* %in.gep.1
+
+  store i32 %hi, i32 addrspace(1)* %out
+  store i32 %lo, i32 addrspace(1)* %out.gep.1
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_4_adjacent_loads_i32:
+; GCN: buffer_load_dwordx4 [[LOAD:v\[[0-9]+:[0-9]+\]]]
+; GCN: buffer_store_dwordx4 [[LOAD]]
+define void @merge_global_store_4_adjacent_loads_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
+  %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
+  %out.gep.2 = getelementptr i32, i32 addrspace(1)* %out, i32 2
+  %out.gep.3 = getelementptr i32, i32 addrspace(1)* %out, i32 3
+  %in.gep.1 = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %in.gep.2 = getelementptr i32, i32 addrspace(1)* %in, i32 2
+  %in.gep.3 = getelementptr i32, i32 addrspace(1)* %in, i32 3
+
+  %x = load i32, i32 addrspace(1)* %in
+  %y = load i32, i32 addrspace(1)* %in.gep.1
+  %z = load i32, i32 addrspace(1)* %in.gep.2
+  %w = load i32, i32 addrspace(1)* %in.gep.3
+
+  store i32 %x, i32 addrspace(1)* %out
+  store i32 %y, i32 addrspace(1)* %out.gep.1
+  store i32 %z, i32 addrspace(1)* %out.gep.2
+  store i32 %w, i32 addrspace(1)* %out.gep.3
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_3_adjacent_loads_i32:
+; SI-DAG: buffer_load_dwordx2
+; SI-DAG: buffer_load_dword v
+; GCN: s_waitcnt
+; SI-DAG: buffer_store_dword v
+; SI-DAG: buffer_store_dwordx2 v
+; GCN: s_endpgm
+define void @merge_global_store_3_adjacent_loads_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
+  %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
+  %out.gep.2 = getelementptr i32, i32 addrspace(1)* %out, i32 2
+  %in.gep.1 = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %in.gep.2 = getelementptr i32, i32 addrspace(1)* %in, i32 2
+
+  %x = load i32, i32 addrspace(1)* %in
+  %y = load i32, i32 addrspace(1)* %in.gep.1
+  %z = load i32, i32 addrspace(1)* %in.gep.2
+
+  store i32 %x, i32 addrspace(1)* %out
+  store i32 %y, i32 addrspace(1)* %out.gep.1
+  store i32 %z, i32 addrspace(1)* %out.gep.2
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_4_adjacent_loads_f32:
+; GCN: buffer_load_dwordx4 [[LOAD:v\[[0-9]+:[0-9]+\]]]
+; GCN: buffer_store_dwordx4 [[LOAD]]
+define void @merge_global_store_4_adjacent_loads_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
+  %out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
+  %out.gep.2 = getelementptr float, float addrspace(1)* %out, i32 2
+  %out.gep.3 = getelementptr float, float addrspace(1)* %out, i32 3
+  %in.gep.1 = getelementptr float, float addrspace(1)* %in, i32 1
+  %in.gep.2 = getelementptr float, float addrspace(1)* %in, i32 2
+  %in.gep.3 = getelementptr float, float addrspace(1)* %in, i32 3
+
+  %x = load float, float addrspace(1)* %in
+  %y = load float, float addrspace(1)* %in.gep.1
+  %z = load float, float addrspace(1)* %in.gep.2
+  %w = load float, float addrspace(1)* %in.gep.3
+
+  store float %x, float addrspace(1)* %out
+  store float %y, float addrspace(1)* %out.gep.1
+  store float %z, float addrspace(1)* %out.gep.2
+  store float %w, float addrspace(1)* %out.gep.3
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_4_adjacent_loads_i32_nonzero_base:
+; GCN: buffer_load_dwordx4 [[LOAD:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:44
+; GCN: buffer_store_dwordx4 [[LOAD]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:28
+define void @merge_global_store_4_adjacent_loads_i32_nonzero_base(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
+  %in.gep.0 = getelementptr i32, i32 addrspace(1)* %in, i32 11
+  %in.gep.1 = getelementptr i32, i32 addrspace(1)* %in, i32 12
+  %in.gep.2 = getelementptr i32, i32 addrspace(1)* %in, i32 13
+  %in.gep.3 = getelementptr i32, i32 addrspace(1)* %in, i32 14
+  %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i32 7
+  %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 8
+  %out.gep.2 = getelementptr i32, i32 addrspace(1)* %out, i32 9
+  %out.gep.3 = getelementptr i32, i32 addrspace(1)* %out, i32 10
+
+  %x = load i32, i32 addrspace(1)* %in.gep.0
+  %y = load i32, i32 addrspace(1)* %in.gep.1
+  %z = load i32, i32 addrspace(1)* %in.gep.2
+  %w = load i32, i32 addrspace(1)* %in.gep.3
+
+  store i32 %x, i32 addrspace(1)* %out.gep.0
+  store i32 %y, i32 addrspace(1)* %out.gep.1
+  store i32 %z, i32 addrspace(1)* %out.gep.2
+  store i32 %w, i32 addrspace(1)* %out.gep.3
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_4_adjacent_loads_inverse_i32:
+; GCN: buffer_load_dwordx4 [[LOAD:v\[[0-9]+:[0-9]+\]]]
+; GCN: s_barrier
+; GCN: buffer_store_dwordx4 [[LOAD]]
+define void @merge_global_store_4_adjacent_loads_inverse_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
+  %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
+  %out.gep.2 = getelementptr i32, i32 addrspace(1)* %out, i32 2
+  %out.gep.3 = getelementptr i32, i32 addrspace(1)* %out, i32 3
+  %in.gep.1 = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %in.gep.2 = getelementptr i32, i32 addrspace(1)* %in, i32 2
+  %in.gep.3 = getelementptr i32, i32 addrspace(1)* %in, i32 3
+
+  %x = load i32, i32 addrspace(1)* %in
+  %y = load i32, i32 addrspace(1)* %in.gep.1
+  %z = load i32, i32 addrspace(1)* %in.gep.2
+  %w = load i32, i32 addrspace(1)* %in.gep.3
+
+  ; Make sure the barrier doesn't stop this
+  tail call void @llvm.AMDGPU.barrier.local() #1
+
+  store i32 %w, i32 addrspace(1)* %out.gep.3
+  store i32 %z, i32 addrspace(1)* %out.gep.2
+  store i32 %y, i32 addrspace(1)* %out.gep.1
+  store i32 %x, i32 addrspace(1)* %out
+
+  ret void
+}
+
+; TODO: Re-packing of loaded register required. Maybe an IR pass
+; should catch this?
+
+; GCN-LABEL: {{^}}merge_global_store_4_adjacent_loads_shuffle_i32:
+; GCN: buffer_load_dword v
+; GCN: buffer_load_dword v
+; GCN: buffer_load_dword v
+; GCN: buffer_load_dword v
+; GCN: s_barrier
+; GCN: buffer_store_dword v
+; GCN: buffer_store_dword v
+; GCN: buffer_store_dword v
+; GCN: buffer_store_dword v
+define void @merge_global_store_4_adjacent_loads_shuffle_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
+  %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
+  %out.gep.2 = getelementptr i32, i32 addrspace(1)* %out, i32 2
+  %out.gep.3 = getelementptr i32, i32 addrspace(1)* %out, i32 3
+  %in.gep.1 = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %in.gep.2 = getelementptr i32, i32 addrspace(1)* %in, i32 2
+  %in.gep.3 = getelementptr i32, i32 addrspace(1)* %in, i32 3
+
+  %x = load i32, i32 addrspace(1)* %in
+  %y = load i32, i32 addrspace(1)* %in.gep.1
+  %z = load i32, i32 addrspace(1)* %in.gep.2
+  %w = load i32, i32 addrspace(1)* %in.gep.3
+
+  ; Make sure the barrier doesn't stop this
+  tail call void @llvm.AMDGPU.barrier.local() #1
+
+  store i32 %w, i32 addrspace(1)* %out
+  store i32 %z, i32 addrspace(1)* %out.gep.1
+  store i32 %y, i32 addrspace(1)* %out.gep.2
+  store i32 %x, i32 addrspace(1)* %out.gep.3
+
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_4_adjacent_loads_i8:
+; GCN: buffer_load_dword [[LOAD:v[0-9]+]]
+; GCN: buffer_store_dword [[LOAD]]
+; GCN: s_endpgm
+define void @merge_global_store_4_adjacent_loads_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) #0 {
+  %out.gep.1 = getelementptr i8, i8 addrspace(1)* %out, i8 1
+  %out.gep.2 = getelementptr i8, i8 addrspace(1)* %out, i8 2
+  %out.gep.3 = getelementptr i8, i8 addrspace(1)* %out, i8 3
+  %in.gep.1 = getelementptr i8, i8 addrspace(1)* %in, i8 1
+  %in.gep.2 = getelementptr i8, i8 addrspace(1)* %in, i8 2
+  %in.gep.3 = getelementptr i8, i8 addrspace(1)* %in, i8 3
+
+  %x = load i8, i8 addrspace(1)* %in, align 4
+  %y = load i8, i8 addrspace(1)* %in.gep.1
+  %z = load i8, i8 addrspace(1)* %in.gep.2
+  %w = load i8, i8 addrspace(1)* %in.gep.3
+
+  store i8 %x, i8 addrspace(1)* %out, align 4
+  store i8 %y, i8 addrspace(1)* %out.gep.1
+  store i8 %z, i8 addrspace(1)* %out.gep.2
+  store i8 %w, i8 addrspace(1)* %out.gep.3
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_global_store_4_adjacent_loads_i8_natural_align:
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_load_ubyte
+; GCN: buffer_store_byte
+; GCN: buffer_store_byte
+; GCN: buffer_store_byte
+; GCN: buffer_store_byte
+; GCN: s_endpgm
+define void @merge_global_store_4_adjacent_loads_i8_natural_align(i8 addrspace(1)* %out, i8 addrspace(1)* %in) #0 {
+  %out.gep.1 = getelementptr i8, i8 addrspace(1)* %out, i8 1
+  %out.gep.2 = getelementptr i8, i8 addrspace(1)* %out, i8 2
+  %out.gep.3 = getelementptr i8, i8 addrspace(1)* %out, i8 3
+  %in.gep.1 = getelementptr i8, i8 addrspace(1)* %in, i8 1
+  %in.gep.2 = getelementptr i8, i8 addrspace(1)* %in, i8 2
+  %in.gep.3 = getelementptr i8, i8 addrspace(1)* %in, i8 3
+
+  %x = load i8, i8 addrspace(1)* %in
+  %y = load i8, i8 addrspace(1)* %in.gep.1
+  %z = load i8, i8 addrspace(1)* %in.gep.2
+  %w = load i8, i8 addrspace(1)* %in.gep.3
+
+  store i8 %x, i8 addrspace(1)* %out
+  store i8 %y, i8 addrspace(1)* %out.gep.1
+  store i8 %z, i8 addrspace(1)* %out.gep.2
+  store i8 %w, i8 addrspace(1)* %out.gep.3
+  ret void
+}
+
+; This works once AA is enabled on the subtarget
+; GCN-LABEL: {{^}}merge_global_store_4_vector_elts_loads_v4i32:
+; GCN: buffer_load_dwordx4 [[LOAD:v\[[0-9]+:[0-9]+\]]]
+; XGCN: buffer_store_dwordx4 [[LOAD]]
+; GCN: buffer_store_dword v
+; GCN: buffer_store_dword v
+; GCN: buffer_store_dword v
+; GCN: buffer_store_dword v
+define void @merge_global_store_4_vector_elts_loads_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 {
+  %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
+  %out.gep.2 = getelementptr i32, i32 addrspace(1)* %out, i32 2
+  %out.gep.3 = getelementptr i32, i32 addrspace(1)* %out, i32 3
+  %vec = load <4 x i32>, <4 x i32> addrspace(1)* %in
+
+  %x = extractelement <4 x i32> %vec, i32 0
+  %y = extractelement <4 x i32> %vec, i32 1
+  %z = extractelement <4 x i32> %vec, i32 2
+  %w = extractelement <4 x i32> %vec, i32 3
+
+  store i32 %x, i32 addrspace(1)* %out
+  store i32 %y, i32 addrspace(1)* %out.gep.1
+  store i32 %z, i32 addrspace(1)* %out.gep.2
+  store i32 %w, i32 addrspace(1)* %out.gep.3
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_local_store_2_constants_i8:
+; GCN: ds_write_b8
+; GCN: ds_write_b8
+; GCN: s_endpgm
+define void @merge_local_store_2_constants_i8(i8 addrspace(3)* %out) #0 {
+  %out.gep.1 = getelementptr i8, i8 addrspace(3)* %out, i32 1
+
+  store i8 123, i8 addrspace(3)* %out.gep.1
+  store i8 456, i8 addrspace(3)* %out, align 2
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_local_store_2_constants_i32:
+; GCN-DAG: s_movk_i32 [[SLO:s[0-9]+]], 0x1c8
+; GCN-DAG: s_movk_i32 [[SHI:s[0-9]+]], 0x7b
+; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[SLO]]
+; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHI]]
+; GCN: ds_write2_b32 v{{[0-9]+}}, v[[LO]], v[[HI]] offset1:1{{$}}
+define void @merge_local_store_2_constants_i32(i32 addrspace(3)* %out) #0 {
+  %out.gep.1 = getelementptr i32, i32 addrspace(3)* %out, i32 1
+
+  store i32 123, i32 addrspace(3)* %out.gep.1
+  store i32 456, i32 addrspace(3)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}merge_local_store_4_constants_i32:
+; GCN: ds_write_b32
+; GCN: ds_write_b32
+; GCN: ds_write_b32
+; GCN: ds_write_b32
+define void @merge_local_store_4_constants_i32(i32 addrspace(3)* %out) #0 {
+  %out.gep.1 = getelementptr i32, i32 addrspace(3)* %out, i32 1
+  %out.gep.2 = getelementptr i32, i32 addrspace(3)* %out, i32 2
+  %out.gep.3 = getelementptr i32, i32 addrspace(3)* %out, i32 3
+
+  store i32 123, i32 addrspace(3)* %out.gep.1
+  store i32 456, i32 addrspace(3)* %out.gep.2
+  store i32 333, i32 addrspace(3)* %out.gep.3
+  store i32 1234, i32 addrspace(3)* %out
+  ret void
+}
+
+declare void @llvm.AMDGPU.barrier.local() #1
+
+attributes #0 = { nounwind }
+attributes #1 = { noduplicate nounwind }
diff --git a/test/CodeGen/R600/min.ll b/test/CodeGen/R600/min.ll
index 00ba5c6cddb4..275e9a7d899b 100644
--- a/test/CodeGen/R600/min.ll
+++ b/test/CodeGen/R600/min.ll
@@ -6,11 +6,11 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone
 ; SI: v_min_i32_e32
 define void @v_test_imin_sle_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
-  %gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
-  %outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load i32 addrspace(1)* %gep0, align 4
-  %b = load i32 addrspace(1)* %gep1, align 4
+  %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
+  %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load i32, i32 addrspace(1)* %gep0, align 4
+  %b = load i32, i32 addrspace(1)* %gep1, align 4
   %cmp = icmp sle i32 %a, %b
   %val = select i1 %cmp, i32 %a, i32 %b
   store i32 %val, i32 addrspace(1)* %outgep, align 4
@@ -30,11 +30,11 @@ define void @s_test_imin_sle_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin
 ; SI: v_min_i32_e32
 define void @v_test_imin_slt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
-  %gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
-  %outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load i32 addrspace(1)* %gep0, align 4
-  %b = load i32 addrspace(1)* %gep1, align 4
+  %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
+  %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load i32, i32 addrspace(1)* %gep0, align 4
+  %b = load i32, i32 addrspace(1)* %gep1, align 4
   %cmp = icmp slt i32 %a, %b
   %val = select i1 %cmp, i32 %a, i32 %b
   store i32 %val, i32 addrspace(1)* %outgep, align 4
@@ -50,15 +50,33 @@ define void @s_test_imin_slt_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin
   ret void
 }
 
+; FUNC-LABEL: {{^}}s_test_imin_slt_imm_i32:
+; SI: s_min_i32 {{s[0-9]+}}, {{s[0-9]+}}, 8
+define void @s_test_imin_slt_imm_i32(i32 addrspace(1)* %out, i32 %a) nounwind {
+  %cmp = icmp slt i32 %a, 8
+  %val = select i1 %cmp, i32 %a, i32 8
+  store i32 %val, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+; FUNC-LABEL: {{^}}s_test_imin_sle_imm_i32:
+; SI: s_min_i32 {{s[0-9]+}}, {{s[0-9]+}}, 8
+define void @s_test_imin_sle_imm_i32(i32 addrspace(1)* %out, i32 %a) nounwind {
+  %cmp = icmp sle i32 %a, 8
+  %val = select i1 %cmp, i32 %a, i32 8
+  store i32 %val, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
 ; FUNC-LABEL: @v_test_umin_ule_i32
 ; SI: v_min_u32_e32
 define void @v_test_umin_ule_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
-  %gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
-  %outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load i32 addrspace(1)* %gep0, align 4
-  %b = load i32 addrspace(1)* %gep1, align 4
+  %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
+  %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load i32, i32 addrspace(1)* %gep0, align 4
+  %b = load i32, i32 addrspace(1)* %gep1, align 4
   %cmp = icmp ule i32 %a, %b
   %val = select i1 %cmp, i32 %a, i32 %b
   store i32 %val, i32 addrspace(1)* %outgep, align 4
@@ -78,11 +96,11 @@ define void @s_test_umin_ule_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin
 ; SI: v_min_u32_e32
 define void @v_test_umin_ult_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
-  %gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
-  %outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load i32 addrspace(1)* %gep0, align 4
-  %b = load i32 addrspace(1)* %gep1, align 4
+  %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
+  %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load i32, i32 addrspace(1)* %gep0, align 4
+  %b = load i32, i32 addrspace(1)* %gep1, align 4
   %cmp = icmp ult i32 %a, %b
   %val = select i1 %cmp, i32 %a, i32 %b
   store i32 %val, i32 addrspace(1)* %outgep, align 4
@@ -106,12 +124,12 @@ define void @s_test_umin_ult_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin
 ; SI: s_endpgm
 define void @v_test_umin_ult_i32_multi_use(i32 addrspace(1)* %out0, i1 addrspace(1)* %out1, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
-  %gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
-  %outgep0 = getelementptr i32 addrspace(1)* %out0, i32 %tid
-  %outgep1 = getelementptr i1 addrspace(1)* %out1, i32 %tid
-  %a = load i32 addrspace(1)* %gep0, align 4
-  %b = load i32 addrspace(1)* %gep1, align 4
+  %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
+  %outgep0 = getelementptr i32, i32 addrspace(1)* %out0, i32 %tid
+  %outgep1 = getelementptr i1, i1 addrspace(1)* %out1, i32 %tid
+  %a = load i32, i32 addrspace(1)* %gep0, align 4
+  %b = load i32, i32 addrspace(1)* %gep1, align 4
   %cmp = icmp ult i32 %a, %b
   %val = select i1 %cmp, i32 %a, i32 %b
   store i32 %val, i32 addrspace(1)* %outgep0, align 4
diff --git a/test/CodeGen/R600/min3.ll b/test/CodeGen/R600/min3.ll
index 6c11a650fcbb..38ef46d1bdd6 100644
--- a/test/CodeGen/R600/min3.ll
+++ b/test/CodeGen/R600/min3.ll
@@ -6,13 +6,13 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone
 ; SI: v_min3_i32
 define void @v_test_imin3_slt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
-  %gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
-  %gep2 = getelementptr i32 addrspace(1)* %cptr, i32 %tid
-  %outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load i32 addrspace(1)* %gep0, align 4
-  %b = load i32 addrspace(1)* %gep1, align 4
-  %c = load i32 addrspace(1)* %gep2, align 4
+  %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i32, i32 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load i32, i32 addrspace(1)* %gep0, align 4
+  %b = load i32, i32 addrspace(1)* %gep1, align 4
+  %c = load i32, i32 addrspace(1)* %gep2, align 4
   %icmp0 = icmp slt i32 %a, %b
   %i0 = select i1 %icmp0, i32 %a, i32 %b
   %icmp1 = icmp slt i32 %i0, %c
@@ -25,13 +25,13 @@ define void @v_test_imin3_slt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %apt
 ; SI: v_min3_u32
 define void @v_test_umin3_ult_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
-  %gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
-  %gep2 = getelementptr i32 addrspace(1)* %cptr, i32 %tid
-  %outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load i32 addrspace(1)* %gep0, align 4
-  %b = load i32 addrspace(1)* %gep1, align 4
-  %c = load i32 addrspace(1)* %gep2, align 4
+  %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i32, i32 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load i32, i32 addrspace(1)* %gep0, align 4
+  %b = load i32, i32 addrspace(1)* %gep1, align 4
+  %c = load i32, i32 addrspace(1)* %gep2, align 4
   %icmp0 = icmp ult i32 %a, %b
   %i0 = select i1 %icmp0, i32 %a, i32 %b
   %icmp1 = icmp ult i32 %i0, %c
@@ -46,21 +46,21 @@ define void @v_test_umin3_ult_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %apt
 define void @v_test_umin_umin_umin(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
   %tid2 = mul i32 %tid, 2
-  %gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
-  %gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
-  %gep2 = getelementptr i32 addrspace(1)* %cptr, i32 %tid
+  %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i32, i32 addrspace(1)* %cptr, i32 %tid
 
-  %gep3 = getelementptr i32 addrspace(1)* %aptr, i32 %tid2
-  %gep4 = getelementptr i32 addrspace(1)* %bptr, i32 %tid2
-  %gep5 = getelementptr i32 addrspace(1)* %cptr, i32 %tid2
+  %gep3 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid2
+  %gep4 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid2
+  %gep5 = getelementptr i32, i32 addrspace(1)* %cptr, i32 %tid2
 
-  %outgep0 = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %outgep1 = getelementptr i32 addrspace(1)* %out, i32 %tid2
+  %outgep0 = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %outgep1 = getelementptr i32, i32 addrspace(1)* %out, i32 %tid2
 
-  %a = load i32 addrspace(1)* %gep0, align 4
-  %b = load i32 addrspace(1)* %gep1, align 4
-  %c = load i32 addrspace(1)* %gep2, align 4
-  %d = load i32 addrspace(1)* %gep3, align 4
+  %a = load i32, i32 addrspace(1)* %gep0, align 4
+  %b = load i32, i32 addrspace(1)* %gep1, align 4
+  %c = load i32, i32 addrspace(1)* %gep2, align 4
+  %d = load i32, i32 addrspace(1)* %gep3, align 4
 
   %icmp0 = icmp slt i32 %a, %b
   %i0 = select i1 %icmp0, i32 %a, i32 %b
@@ -80,21 +80,21 @@ define void @v_test_umin_umin_umin(i32 addrspace(1)* %out, i32 addrspace(1)* %ap
 define void @v_test_umin3_2_uses(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
   %tid2 = mul i32 %tid, 2
-  %gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
-  %gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
-  %gep2 = getelementptr i32 addrspace(1)* %cptr, i32 %tid
+  %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i32, i32 addrspace(1)* %cptr, i32 %tid
 
-  %gep3 = getelementptr i32 addrspace(1)* %aptr, i32 %tid2
-  %gep4 = getelementptr i32 addrspace(1)* %bptr, i32 %tid2
-  %gep5 = getelementptr i32 addrspace(1)* %cptr, i32 %tid2
+  %gep3 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid2
+  %gep4 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid2
+  %gep5 = getelementptr i32, i32 addrspace(1)* %cptr, i32 %tid2
 
-  %outgep0 = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %outgep1 = getelementptr i32 addrspace(1)* %out, i32 %tid2
+  %outgep0 = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %outgep1 = getelementptr i32, i32 addrspace(1)* %out, i32 %tid2
 
-  %a = load i32 addrspace(1)* %gep0, align 4
-  %b = load i32 addrspace(1)* %gep1, align 4
-  %c = load i32 addrspace(1)* %gep2, align 4
-  %d = load i32 addrspace(1)* %gep3, align 4
+  %a = load i32, i32 addrspace(1)* %gep0, align 4
+  %b = load i32, i32 addrspace(1)* %gep1, align 4
+  %c = load i32, i32 addrspace(1)* %gep2, align 4
+  %d = load i32, i32 addrspace(1)* %gep3, align 4
 
   %icmp0 = icmp slt i32 %a, %b
   %i0 = select i1 %icmp0, i32 %a, i32 %b
diff --git a/test/CodeGen/R600/misaligned-load.ll b/test/CodeGen/R600/misaligned-load.ll
deleted file mode 100644
index 6290ca09d502..000000000000
--- a/test/CodeGen/R600/misaligned-load.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-; SI: @byte_aligned_load64
-; SI: ds_read_u8
-; SI: ds_read_u8
-; SI: ds_read_u8
-; SI: ds_read_u8
-; SI: ds_read_u8
-; SI: ds_read_u8
-; SI: ds_read_u8
-; SI: ds_read_u8
-; SI: s_endpgm
-define void @byte_aligned_load64(i64 addrspace(1)* %out, i64 addrspace(3)* %in) {
-entry:
-  %0 = load i64 addrspace(3)* %in, align 1
-  store i64 %0, i64 addrspace(1)* %out
-  ret void
-}
diff --git a/test/CodeGen/R600/missing-store.ll b/test/CodeGen/R600/missing-store.ll
index 8ddef35a694a..4af9cdf1b960 100644
--- a/test/CodeGen/R600/missing-store.ll
+++ b/test/CodeGen/R600/missing-store.ll
@@ -12,11 +12,11 @@
 ; SI: buffer_store_dword
 ; SI: s_endpgm
 define void @missing_store_reduced(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
-  %ptr0 = load i32 addrspace(2)* addrspace(3)* @ptr_load, align 8
-  %ptr2 = getelementptr inbounds i32 addrspace(2)* %ptr0, i64 2
+  %ptr0 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(3)* @ptr_load, align 8
+  %ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 2
 
   store i32 99, i32 addrspace(1)* %gptr, align 4
-  %tmp2 = load i32 addrspace(2)* %ptr2, align 4
+  %tmp2 = load i32, i32 addrspace(2)* %ptr2, align 4
 
   store i32 %tmp2, i32 addrspace(1)* %out, align 4
   ret void
diff --git a/test/CodeGen/R600/mubuf.ll b/test/CodeGen/R600/mubuf.ll
index 9c2a17ce04f4..b19163f294e0 100644
--- a/test/CodeGen/R600/mubuf.ll
+++ b/test/CodeGen/R600/mubuf.ll
@@ -11,8 +11,8 @@ declare i32 @llvm.r600.read.tidig.x() readnone
 ; CHECK: buffer_load_dword v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:4 ; encoding: [0x04,0x00,0x30,0xe0
 define void @mubuf_load0(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 entry:
-  %0 = getelementptr i32 addrspace(1)* %in, i64 1
-  %1 = load i32 addrspace(1)* %0
+  %0 = getelementptr i32, i32 addrspace(1)* %in, i64 1
+  %1 = load i32, i32 addrspace(1)* %0
   store i32 %1, i32 addrspace(1)* %out
   ret void
 }
@@ -22,19 +22,20 @@ entry:
 ; CHECK: buffer_load_ubyte v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0
 define void @mubuf_load1(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
 entry:
-  %0 = getelementptr i8 addrspace(1)* %in, i64 4095
-  %1 = load i8 addrspace(1)* %0
+  %0 = getelementptr i8, i8 addrspace(1)* %in, i64 4095
+  %1 = load i8, i8 addrspace(1)* %0
   store i8 %1, i8 addrspace(1)* %out
   ret void
 }
 
 ; MUBUF load with an immediate byte offset that doesn't fit into 12-bits
 ; CHECK-LABEL: {{^}}mubuf_load2:
-; CHECK: buffer_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 ; encoding: [0x00,0x80,0x30,0xe0
+; CHECK: s_movk_i32 [[SOFFSET:s[0-9]+]], 0x1000
+; CHECK: buffer_load_dword v{{[0-9]}}, s[{{[0-9]+:[0-9]+}}], [[SOFFSET]] ; encoding: [0x00,0x00,0x30,0xe0
 define void @mubuf_load2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 entry:
-  %0 = getelementptr i32 addrspace(1)* %in, i64 1024
-  %1 = load i32 addrspace(1)* %0
+  %0 = getelementptr i32, i32 addrspace(1)* %in, i64 1024
+  %1 = load i32, i32 addrspace(1)* %0
   store i32 %1, i32 addrspace(1)* %out
   ret void
 }
@@ -45,9 +46,9 @@ entry:
 ; CHECK: buffer_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:4 ; encoding: [0x04,0x80,0x30,0xe0
 define void @mubuf_load3(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i64 %offset) {
 entry:
-  %0 = getelementptr i32 addrspace(1)* %in, i64 %offset
-  %1 = getelementptr i32 addrspace(1)* %0, i64 1
-  %2 = load i32 addrspace(1)* %1
+  %0 = getelementptr i32, i32 addrspace(1)* %in, i64 %offset
+  %1 = getelementptr i32, i32 addrspace(1)* %0, i64 1
+  %2 = load i32, i32 addrspace(1)* %1
   store i32 %2, i32 addrspace(1)* %out
   ret void
 }
@@ -56,8 +57,8 @@ entry:
 ; CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 64 offen glc
 define void @soffset_max_imm([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #1 {
 main_body:
-  %tmp0 = getelementptr [6 x <16 x i8>] addrspace(2)* %0, i32 0, i32 0
-  %tmp1 = load <16 x i8> addrspace(2)* %tmp0
+  %tmp0 = getelementptr [6 x <16 x i8>], [6 x <16 x i8>] addrspace(2)* %0, i32 0, i32 0
+  %tmp1 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp0
   %tmp2 = shl i32 %6, 2
   %tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp1, i32 %tmp2, i32 64, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
   %tmp4 = add i32 %6, 16
@@ -75,8 +76,8 @@ main_body:
 ; CHECK: buffer_load_dword v{{[0-9+]}}, v{{[0-9+]}}, s[{{[0-9]+}}:{{[0-9]+}}], [[SOFFSET]] offen glc
 define void @soffset_no_fold([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #1 {
 main_body:
-  %tmp0 = getelementptr [6 x <16 x i8>] addrspace(2)* %0, i32 0, i32 0
-  %tmp1 = load <16 x i8> addrspace(2)* %tmp0
+  %tmp0 = getelementptr [6 x <16 x i8>], [6 x <16 x i8>] addrspace(2)* %0, i32 0, i32 0
+  %tmp1 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp0
   %tmp2 = shl i32 %6, 2
   %tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp1, i32 %tmp2, i32 65, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
   %tmp4 = add i32 %6, 16
@@ -85,12 +86,6 @@ main_body:
   ret void
 }
 
-declare i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #3
-declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
-
-attributes #1 = { "ShaderType"="2" "unsafe-fp-math"="true" }
-attributes #3 = { nounwind readonly }
-
 ;;;==========================================================================;;;
 ;;; MUBUF STORE TESTS
 ;;;==========================================================================;;;
@@ -100,7 +95,7 @@ attributes #3 = { nounwind readonly }
 ; CHECK: buffer_store_dword v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:4 ; encoding: [0x04,0x00,0x70,0xe0
 define void @mubuf_store0(i32 addrspace(1)* %out) {
 entry:
-  %0 = getelementptr i32 addrspace(1)* %out, i64 1
+  %0 = getelementptr i32, i32 addrspace(1)* %out, i64 1
   store i32 0, i32 addrspace(1)* %0
   ret void
 }
@@ -111,17 +106,18 @@ entry:
 
 define void @mubuf_store1(i8 addrspace(1)* %out) {
 entry:
-  %0 = getelementptr i8 addrspace(1)* %out, i64 4095
+  %0 = getelementptr i8, i8 addrspace(1)* %out, i64 4095
   store i8 0, i8 addrspace(1)* %0
   ret void
 }
 
 ; MUBUF store with an immediate byte offset that doesn't fit into 12-bits
 ; CHECK-LABEL: {{^}}mubuf_store2:
-; CHECK: buffer_store_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0 addr64 ; encoding: [0x00,0x80,0x70,0xe0
+; CHECK: s_movk_i32 [[SOFFSET:s[0-9]+]], 0x1000
+; CHECK: buffer_store_dword v{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[SOFFSET]] ; encoding: [0x00,0x00,0x70,0xe0
 define void @mubuf_store2(i32 addrspace(1)* %out) {
 entry:
-  %0 = getelementptr i32 addrspace(1)* %out, i64 1024
+  %0 = getelementptr i32, i32 addrspace(1)* %out, i64 1024
   store i32 0, i32 addrspace(1)* %0
   ret void
 }
@@ -132,8 +128,8 @@ entry:
 ; CHECK: buffer_store_dword v{{[0-9]}}, v[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0 addr64 offset:4 ; encoding: [0x04,0x80,0x70,0xe0
 define void @mubuf_store3(i32 addrspace(1)* %out, i64 %offset) {
 entry:
-  %0 = getelementptr i32 addrspace(1)* %out, i64 %offset
-  %1 = getelementptr i32 addrspace(1)* %0, i64 1
+  %0 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset
+  %1 = getelementptr i32, i32 addrspace(1)* %0, i64 1
   store i32 0, i32 addrspace(1)* %1
   ret void
 }
@@ -148,24 +144,40 @@ define void @store_sgpr_ptr(i32 addrspace(1)* %out) #0 {
 ; CHECK-LABEL: {{^}}store_sgpr_ptr_offset:
 ; CHECK: buffer_store_dword v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:40
 define void @store_sgpr_ptr_offset(i32 addrspace(1)* %out) #0 {
-  %out.gep = getelementptr i32 addrspace(1)* %out, i32 10
+  %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 10
   store i32 99, i32 addrspace(1)* %out.gep, align 4
   ret void
 }
 
 ; CHECK-LABEL: {{^}}store_sgpr_ptr_large_offset:
-; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
+; CHECK: s_mov_b32 [[SOFFSET:s[0-9]+]], 0x20000
+; CHECK: buffer_store_dword v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, [[SOFFSET]]
 define void @store_sgpr_ptr_large_offset(i32 addrspace(1)* %out) #0 {
-  %out.gep = getelementptr i32 addrspace(1)* %out, i32 32768
+  %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 32768
   store i32 99, i32 addrspace(1)* %out.gep, align 4
   ret void
 }
 
+; CHECK-LABEL: {{^}}store_sgpr_ptr_large_offset_atomic:
+; CHECK: s_mov_b32 [[SOFFSET:s[0-9]+]], 0x20000
+; CHECK: buffer_atomic_add v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, [[SOFFSET]]
+define void @store_sgpr_ptr_large_offset_atomic(i32 addrspace(1)* %out) #0 {
+  %gep = getelementptr i32, i32 addrspace(1)* %out, i32 32768
+  %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 5 seq_cst
+  ret void
+}
+
 ; CHECK-LABEL: {{^}}store_vgpr_ptr:
 ; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
 define void @store_vgpr_ptr(i32 addrspace(1)* %out) #0 {
   %tid = call i32 @llvm.r600.read.tidig.x() readnone
-  %out.gep = getelementptr i32 addrspace(1)* %out, i32 %tid
+  %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
   store i32 99, i32 addrspace(1)* %out.gep, align 4
   ret void
 }
+
+declare i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #3
+declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
+
+attributes #1 = { "ShaderType"="2" "unsafe-fp-math"="true" }
+attributes #3 = { nounwind readonly }
diff --git a/test/CodeGen/R600/mul.ll b/test/CodeGen/R600/mul.ll
index 6f15e706dff8..94e0f96b323e 100644
--- a/test/CodeGen/R600/mul.ll
+++ b/test/CodeGen/R600/mul.ll
@@ -12,9 +12,9 @@
 ; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 
 define void @test_mul_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
-  %a = load <2 x i32> addrspace(1) * %in
-  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32>, <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
   %result = mul <2 x i32> %a, %b
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
   ret void
@@ -32,9 +32,9 @@ define void @test_mul_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)
 ; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 
 define void @v_mul_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
-  %a = load <4 x i32> addrspace(1) * %in
-  %b = load <4 x i32> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
+  %a = load <4 x i32>, <4 x i32> addrspace(1) * %in
+  %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
   %result = mul <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
@@ -58,8 +58,8 @@ define void @s_trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
 ; SI: v_mul_lo_i32
 ; SI: buffer_store_dword
 define void @v_trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
-  %a = load i64 addrspace(1)* %aptr, align 8
-  %b = load i64 addrspace(1)* %bptr, align 8
+  %a = load i64, i64 addrspace(1)* %aptr, align 8
+  %b = load i64, i64 addrspace(1)* %bptr, align 8
   %mul = mul i64 %b, %a
   %trunc = trunc i64 %mul to i32
   store i32 %trunc, i32 addrspace(1)* %out, align 8
@@ -88,7 +88,7 @@ entry:
 ; SI-DAG: v_mul_hi_i32
 ; SI: s_endpgm
 define void @v_mul64_sext_c(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %val = load i32 addrspace(1)* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %ext = sext i32 %val to i64
   %mul = mul i64 %ext, 80
   store i64 %mul, i64 addrspace(1)* %out, align 8
@@ -100,7 +100,7 @@ define void @v_mul64_sext_c(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
 ; SI-DAG: v_mul_hi_i32 v{{[0-9]+}}, 9, v{{[0-9]+}}
 ; SI: s_endpgm
 define void @v_mul64_sext_inline_imm(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %val = load i32 addrspace(1)* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %ext = sext i32 %val to i64
   %mul = mul i64 %ext, 9
   store i64 %mul, i64 addrspace(1)* %out, align 8
@@ -123,9 +123,9 @@ define void @s_mul_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
 ; FUNC-LABEL: {{^}}v_mul_i32:
 ; SI: v_mul_lo_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
 define void @v_mul_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %a = load i32 addrspace(1)* %in
-  %b = load i32 addrspace(1)* %b_ptr
+  %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %a = load i32, i32 addrspace(1)* %in
+  %b = load i32, i32 addrspace(1)* %b_ptr
   %result = mul i32 %a, %b
   store i32 %result, i32 addrspace(1)* %out
   ret void
@@ -148,8 +148,8 @@ define void @s_mul_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
 ; FUNC-LABEL: {{^}}v_mul_i64:
 ; SI: v_mul_lo_i32
 define void @v_mul_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) {
-  %a = load i64 addrspace(1)* %aptr, align 8
-  %b = load i64 addrspace(1)* %bptr, align 8
+  %a = load i64, i64 addrspace(1)* %aptr, align 8
+  %b = load i64, i64 addrspace(1)* %bptr, align 8
   %mul = mul i64 %a, %b
   store i64 %mul, i64 addrspace(1)* %out, align 8
   ret void
@@ -163,7 +163,7 @@ entry:
   br i1 %0, label %if, label %else
 
 if:
-  %1 = load i32 addrspace(1)* %in
+  %1 = load i32, i32 addrspace(1)* %in
   br label %endif
 
 else:
@@ -186,7 +186,7 @@ entry:
   br i1 %0, label %if, label %else
 
 if:
-  %1 = load i64 addrspace(1)* %in
+  %1 = load i64, i64 addrspace(1)* %in
   br label %endif
 
 else:
diff --git a/test/CodeGen/R600/no-initializer-constant-addrspace.ll b/test/CodeGen/R600/no-initializer-constant-addrspace.ll
index 532edf07c301..9a814b579deb 100644
--- a/test/CodeGen/R600/no-initializer-constant-addrspace.ll
+++ b/test/CodeGen/R600/no-initializer-constant-addrspace.ll
@@ -6,7 +6,7 @@
 
 ; FUNC-LABEL: {{^}}load_extern_const_init:
 define void @load_extern_const_init(i32 addrspace(1)* %out) nounwind {
-  %val = load i32 addrspace(2)* getelementptr ([5 x i32] addrspace(2)* @extern_const_addrspace, i64 0, i64 3), align 4
+  %val = load i32, i32 addrspace(2)* getelementptr ([5 x i32], [5 x i32] addrspace(2)* @extern_const_addrspace, i64 0, i64 3), align 4
   store i32 %val, i32 addrspace(1)* %out, align 4
   ret void
 }
@@ -15,7 +15,7 @@ define void @load_extern_const_init(i32 addrspace(1)* %out) nounwind {
 
 ; FUNC-LABEL: {{^}}load_undef_const_init:
 define void @load_undef_const_init(i32 addrspace(1)* %out) nounwind {
-  %val = load i32 addrspace(2)* getelementptr ([5 x i32] addrspace(2)* @undef_const_addrspace, i64 0, i64 3), align 4
+  %val = load i32, i32 addrspace(2)* getelementptr ([5 x i32], [5 x i32] addrspace(2)* @undef_const_addrspace, i64 0, i64 3), align 4
   store i32 %val, i32 addrspace(1)* %out, align 4
   ret void
 }
diff --git a/test/CodeGen/R600/no-shrink-extloads.ll b/test/CodeGen/R600/no-shrink-extloads.ll
index 135d22d3036d..e4328ecbaca8 100644
--- a/test/CodeGen/R600/no-shrink-extloads.ll
+++ b/test/CodeGen/R600/no-shrink-extloads.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
 declare i32 @llvm.r600.read.tidig.x() nounwind readnone
 
@@ -23,9 +23,9 @@ define void @truncate_kernarg_i32_to_i16(i16 addrspace(1)* %out, i32 %arg) nounw
 ; SI: buffer_store_short v
 define void @truncate_buffer_load_i32_to_i16(i16 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.in = getelementptr i32 addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i16 addrspace(1)* %out, i32 %tid
-  %load = load i32 addrspace(1)* %gep.in
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
+  %load = load i32, i32 addrspace(1)* %gep.in
   %trunc = trunc i32 %load to i16
   store i16 %trunc, i16 addrspace(1)* %gep.out
   ret void
@@ -45,9 +45,9 @@ define void @truncate_kernarg_i32_to_i8(i8 addrspace(1)* %out, i32 %arg) nounwin
 ; SI: buffer_store_byte v
 define void @truncate_buffer_load_i32_to_i8(i8 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.in = getelementptr i32 addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i8 addrspace(1)* %out, i32 %tid
-  %load = load i32 addrspace(1)* %gep.in
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
+  %load = load i32, i32 addrspace(1)* %gep.in
   %trunc = trunc i32 %load to i8
   store i8 %trunc, i8 addrspace(1)* %gep.out
   ret void
@@ -67,9 +67,9 @@ define void @truncate_kernarg_i32_to_i1(i1 addrspace(1)* %out, i32 %arg) nounwin
 ; SI: buffer_store_byte v
 define void @truncate_buffer_load_i32_to_i1(i1 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.in = getelementptr i32 addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i1 addrspace(1)* %out, i32 %tid
-  %load = load i32 addrspace(1)* %gep.in
+  %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i1, i1 addrspace(1)* %out, i32 %tid
+  %load = load i32, i32 addrspace(1)* %gep.in
   %trunc = trunc i32 %load to i1
   store i1 %trunc, i1 addrspace(1)* %gep.out
   ret void
@@ -89,9 +89,9 @@ define void @truncate_kernarg_i64_to_i32(i32 addrspace(1)* %out, i64 %arg) nounw
 ; SI: buffer_store_dword v
 define void @truncate_buffer_load_i64_to_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.in = getelementptr i64 addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %load = load i64 addrspace(1)* %gep.in
+  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %load = load i64, i64 addrspace(1)* %gep.in
   %trunc = trunc i64 %load to i32
   store i32 %trunc, i32 addrspace(1)* %gep.out
   ret void
@@ -112,9 +112,9 @@ define void @srl_kernarg_i64_to_i32(i32 addrspace(1)* %out, i64 %arg) nounwind {
 ; SI: buffer_store_dword v
 define void @srl_buffer_load_i64_to_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.in = getelementptr i64 addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %load = load i64 addrspace(1)* %gep.in
+  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %load = load i64, i64 addrspace(1)* %gep.in
   %srl = lshr i64 %load, 32
   %trunc = trunc i64 %srl to i32
   store i32 %trunc, i32 addrspace(1)* %gep.out
@@ -136,9 +136,9 @@ define void @truncate_kernarg_i16_to_i8(i8 addrspace(1)* %out, i16 %arg) nounwin
 ; SI: buffer_store_byte v
 define void @truncate_buffer_load_i16_to_i8(i8 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.in = getelementptr i16 addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i8 addrspace(1)* %out, i32 %tid
-  %load = load i16 addrspace(1)* %gep.in
+  %gep.in = getelementptr i16, i16 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
+  %load = load i16, i16 addrspace(1)* %gep.in
   %trunc = trunc i16 %load to i8
   store i8 %trunc, i8 addrspace(1)* %gep.out
   ret void
@@ -159,9 +159,9 @@ define void @srl_kernarg_i64_to_i8(i8 addrspace(1)* %out, i64 %arg) nounwind {
 ; SI: buffer_store_byte v
 define void @srl_buffer_load_i64_to_i8(i8 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.in = getelementptr i64 addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i8 addrspace(1)* %out, i32 %tid
-  %load = load i64 addrspace(1)* %gep.in
+  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
+  %load = load i64, i64 addrspace(1)* %gep.in
   %srl = lshr i64 %load, 32
   %trunc = trunc i64 %srl to i8
   store i8 %trunc, i8 addrspace(1)* %gep.out
@@ -182,9 +182,9 @@ define void @truncate_kernarg_i64_to_i8(i8 addrspace(1)* %out, i64 %arg) nounwin
 ; SI: buffer_store_byte v
 define void @truncate_buffer_load_i64_to_i8(i8 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.in = getelementptr i64 addrspace(1)* %in, i32 %tid
-  %gep.out = getelementptr i8 addrspace(1)* %out, i32 %tid
-  %load = load i64 addrspace(1)* %gep.in
+  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %gep.out = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
+  %load = load i64, i64 addrspace(1)* %gep.in
   %trunc = trunc i64 %load to i8
   store i8 %trunc, i8 addrspace(1)* %gep.out
   ret void
diff --git a/test/CodeGen/R600/operand-folding.ll b/test/CodeGen/R600/operand-folding.ll
index 88a8145dcd62..816755efb07c 100644
--- a/test/CodeGen/R600/operand-folding.ll
+++ b/test/CodeGen/R600/operand-folding.ll
@@ -10,7 +10,7 @@ entry:
 if:
   %id = call i32 @llvm.r600.read.tidig.x()
   %offset = add i32 %fold, %id
-  %tmp1 = getelementptr i32 addrspace(1)* %out, i32 %offset
+  %tmp1 = getelementptr i32, i32 addrspace(1)* %out, i32 %offset
   store i32 0, i32 addrspace(1)* %tmp1
   br label %endif
 
@@ -19,7 +19,7 @@ endif:
 }
 
 ; CHECK-LABEL: {{^}}fold_imm:
-; CHECK v_or_i32_e32 v{{[0-9]+}}, 5
+; CHECK: v_or_b32_e32 v{{[0-9]+}}, 5
 define void @fold_imm(i32 addrspace(1)* %out, i32 %cmp) {
 entry:
   %fold = add i32 3, 2
diff --git a/test/CodeGen/R600/operand-spacing.ll b/test/CodeGen/R600/operand-spacing.ll
index dd9f25aad7f2..20420a84de6f 100644
--- a/test/CodeGen/R600/operand-spacing.ll
+++ b/test/CodeGen/R600/operand-spacing.ll
@@ -1,13 +1,16 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s
 
 ; Make sure there isn't an extra space between the instruction name and first operands.
 
-; SI-LABEL: {{^}}add_f32:
+; GCN-LABEL: {{^}}add_f32:
 ; SI-DAG: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
 ; SI-DAG: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; SI: v_mov_b32_e32 [[VREGB:v[0-9]+]], [[SREGB]]
-; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], [[SREGA]], [[VREGB]]
-; SI: buffer_store_dword [[RESULT]],
+; VI-DAG: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; VI-DAG: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
+; GCN: v_mov_b32_e32 [[VREGB:v[0-9]+]], [[SREGB]]
+; GCN: v_add_f32_e32 [[RESULT:v[0-9]+]], [[SREGA]], [[VREGB]]
+; GCN: buffer_store_dword [[RESULT]],
 define void @add_f32(float addrspace(1)* %out, float %a, float %b) {
   %result = fadd float %a, %b
   store float %result, float addrspace(1)* %out
diff --git a/test/CodeGen/R600/or.ll b/test/CodeGen/R600/or.ll
index 0d9a6992a6bd..1c04090b407f 100644
--- a/test/CodeGen/R600/or.ll
+++ b/test/CodeGen/R600/or.ll
@@ -2,45 +2,42 @@
 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 
-; EG-LABEL: {{^}}or_v2i32:
+
+; FUNC-LABEL: {{^}}or_v2i32:
 ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
-; SI-LABEL: {{^}}or_v2i32:
 ; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 ; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-
 define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
-  %a = load <2 x i32> addrspace(1) * %in
-  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32>, <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
   %result = or <2 x i32> %a, %b
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
   ret void
 }
 
-; EG-LABEL: {{^}}or_v4i32:
+; FUNC-LABEL: {{^}}or_v4i32:
 ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
-; SI-LABEL: {{^}}or_v4i32:
 ; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 ; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 ; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 ; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-
 define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
-  %a = load <4 x i32> addrspace(1) * %in
-  %b = load <4 x i32> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
+  %a = load <4 x i32>, <4 x i32> addrspace(1) * %in
+  %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
   %result = or <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
 }
 
-; SI-LABEL: {{^}}scalar_or_i32:
+; FUNC-LABEL: {{^}}scalar_or_i32:
 ; SI: s_or_b32
 define void @scalar_or_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
   %or = or i32 %a, %b
@@ -48,16 +45,16 @@ define void @scalar_or_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
   ret void
 }
 
-; SI-LABEL: {{^}}vector_or_i32:
+; FUNC-LABEL: {{^}}vector_or_i32:
 ; SI: v_or_b32_e32 v{{[0-9]}}
 define void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b) {
-  %loada = load i32 addrspace(1)* %a
+  %loada = load i32, i32 addrspace(1)* %a
   %or = or i32 %loada, %b
   store i32 %or, i32 addrspace(1)* %out
   ret void
 }
 
-; SI-LABEL: {{^}}scalar_or_literal_i32:
+; FUNC-LABEL: {{^}}scalar_or_literal_i32:
 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1869f
 define void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) {
   %or = or i32 %a, 99999
@@ -65,28 +62,28 @@ define void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) {
   ret void
 }
 
-; SI-LABEL: {{^}}vector_or_literal_i32:
+; FUNC-LABEL: {{^}}vector_or_literal_i32:
 ; SI: v_or_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
 define void @vector_or_literal_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
-  %loada = load i32 addrspace(1)* %a, align 4
+  %loada = load i32, i32 addrspace(1)* %a, align 4
   %or = or i32 %loada, 65535
   store i32 %or, i32 addrspace(1)* %out, align 4
   ret void
 }
 
-; SI-LABEL: {{^}}vector_or_inline_immediate_i32:
+; FUNC-LABEL: {{^}}vector_or_inline_immediate_i32:
 ; SI: v_or_b32_e32 v{{[0-9]+}}, 4, v{{[0-9]+}}
 define void @vector_or_inline_immediate_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
-  %loada = load i32 addrspace(1)* %a, align 4
+  %loada = load i32, i32 addrspace(1)* %a, align 4
   %or = or i32 %loada, 4
   store i32 %or, i32 addrspace(1)* %out, align 4
   ret void
 }
 
-; EG-LABEL: {{^}}scalar_or_i64:
+; FUNC-LABEL: {{^}}scalar_or_i64:
 ; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
 ; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
-; SI-LABEL: {{^}}scalar_or_i64:
+
 ; SI: s_or_b64
 define void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
   %or = or i64 %a, %b
@@ -94,28 +91,28 @@ define void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
   ret void
 }
 
-; SI-LABEL: {{^}}vector_or_i64:
+; FUNC-LABEL: {{^}}vector_or_i64:
 ; SI: v_or_b32_e32 v{{[0-9]}}
 ; SI: v_or_b32_e32 v{{[0-9]}}
 define void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 8
-  %loadb = load i64 addrspace(1)* %a, align 8
+  %loada = load i64, i64 addrspace(1)* %a, align 8
+  %loadb = load i64, i64 addrspace(1)* %a, align 8
   %or = or i64 %loada, %loadb
   store i64 %or, i64 addrspace(1)* %out
   ret void
 }
 
-; SI-LABEL: {{^}}scalar_vector_or_i64:
+; FUNC-LABEL: {{^}}scalar_vector_or_i64:
 ; SI: v_or_b32_e32 v{{[0-9]}}
 ; SI: v_or_b32_e32 v{{[0-9]}}
 define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 %b) {
-  %loada = load i64 addrspace(1)* %a
+  %loada = load i64, i64 addrspace(1)* %a
   %or = or i64 %loada, %b
   store i64 %or, i64 addrspace(1)* %out
   ret void
 }
 
-; SI-LABEL: {{^}}vector_or_i64_loadimm:
+; FUNC-LABEL: {{^}}vector_or_i64_loadimm:
 ; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xdf77987f
 ; SI-DAG: s_movk_i32 [[HI_S_IMM:s[0-9]+]], 0x146f
 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
@@ -123,26 +120,26 @@ define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a,
 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
 ; SI: s_endpgm
 define void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 8
+  %loada = load i64, i64 addrspace(1)* %a, align 8
   %or = or i64 %loada, 22470723082367
   store i64 %or, i64 addrspace(1)* %out
   ret void
 }
 
 ; FIXME: The or 0 should really be removed.
-; SI-LABEL: {{^}}vector_or_i64_imm:
+; FUNC-LABEL: {{^}}vector_or_i64_imm:
 ; SI: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
 ; SI: v_or_b32_e32 {{v[0-9]+}}, 8, v[[LO_VREG]]
 ; SI: v_or_b32_e32 {{v[0-9]+}}, 0, {{.*}}
 ; SI: s_endpgm
 define void @vector_or_i64_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 8
+  %loada = load i64, i64 addrspace(1)* %a, align 8
   %or = or i64 %loada, 8
   store i64 %or, i64 addrspace(1)* %out
   ret void
 }
 
-; SI-LABEL: {{^}}trunc_i64_or_to_i32:
+; FUNC-LABEL: {{^}}trunc_i64_or_to_i32:
 ; SI: s_load_dword s[[SREG0:[0-9]+]]
 ; SI: s_load_dword s[[SREG1:[0-9]+]]
 ; SI: s_or_b32 s[[SRESULT:[0-9]+]], s[[SREG1]], s[[SREG0]]
@@ -155,18 +152,27 @@ define void @trunc_i64_or_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
   ret void
 }
 
-; EG-CHECK: {{^}}or_i1:
-; EG-CHECK: OR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}}
+; FUNC-LABEL: {{^}}or_i1:
+; EG: OR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}}
 
-; SI-CHECK: {{^}}or_i1:
-; SI-CHECK: s_or_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
-define void @or_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
-  %a = load float addrspace(1) * %in0
-  %b = load float addrspace(1) * %in1
+; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
+define void @or_i1(i32 addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
+  %a = load float, float addrspace(1)* %in0
+  %b = load float, float addrspace(1)* %in1
   %acmp = fcmp oge float %a, 0.000000e+00
   %bcmp = fcmp oge float %b, 0.000000e+00
   %or = or i1 %acmp, %bcmp
-  %result = select i1 %or, float %a, float %b
-  store float %result, float addrspace(1)* %out
+  %result = zext i1 %or to i32
+  store i32 %result, i32 addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}s_or_i1:
+; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
+define void @s_or_i1(i1 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
+  %cmp0 = icmp eq i32 %a, %b
+  %cmp1 = icmp eq i32 %c, %d
+  %or = or i1 %cmp0, %cmp1
+  store i1 %or, i1 addrspace(1)* %out
   ret void
 }
diff --git a/test/CodeGen/R600/parallelandifcollapse.ll b/test/CodeGen/R600/parallelandifcollapse.ll
index 82b11501e865..f32b044198ab 100644
--- a/test/CodeGen/R600/parallelandifcollapse.ll
+++ b/test/CodeGen/R600/parallelandifcollapse.ll
@@ -23,14 +23,14 @@ entry:
   %c1 = alloca i32, align 4
   %d1 = alloca i32, align 4
   %data = alloca i32, align 4
-  %0 = load i32* %a0, align 4
-  %1 = load i32* %b0, align 4
+  %0 = load i32, i32* %a0, align 4
+  %1 = load i32, i32* %b0, align 4
   %cmp = icmp ne i32 %0, %1
   br i1 %cmp, label %land.lhs.true, label %if.end
 
 land.lhs.true:                                    ; preds = %entry
-  %2 = load i32* %c0, align 4
-  %3 = load i32* %d0, align 4
+  %2 = load i32, i32* %c0, align 4
+  %3 = load i32, i32* %d0, align 4
   %cmp1 = icmp ne i32 %2, %3
   br i1 %cmp1, label %if.then, label %if.end
 
@@ -39,14 +39,14 @@ if.then:                                          ; preds = %land.lhs.true
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %land.lhs.true, %entry
-  %4 = load i32* %a1, align 4
-  %5 = load i32* %b1, align 4
+  %4 = load i32, i32* %a1, align 4
+  %5 = load i32, i32* %b1, align 4
   %cmp2 = icmp ne i32 %4, %5
   br i1 %cmp2, label %land.lhs.true3, label %if.end6
 
 land.lhs.true3:                                   ; preds = %if.end
-  %6 = load i32* %c1, align 4
-  %7 = load i32* %d1, align 4
+  %6 = load i32, i32* %c1, align 4
+  %7 = load i32, i32* %d1, align 4
   %cmp4 = icmp ne i32 %6, %7
   br i1 %cmp4, label %if.then5, label %if.end6
 
diff --git a/test/CodeGen/R600/parallelorifcollapse.ll b/test/CodeGen/R600/parallelorifcollapse.ll
index feca688c30aa..1da1e91b8ab8 100644
--- a/test/CodeGen/R600/parallelorifcollapse.ll
+++ b/test/CodeGen/R600/parallelorifcollapse.ll
@@ -23,14 +23,14 @@ entry:
   %c1 = alloca i32, align 4
   %d1 = alloca i32, align 4
   %data = alloca i32, align 4
-  %0 = load i32* %a0, align 4
-  %1 = load i32* %b0, align 4
+  %0 = load i32, i32* %a0, align 4
+  %1 = load i32, i32* %b0, align 4
   %cmp = icmp ne i32 %0, %1
   br i1 %cmp, label %land.lhs.true, label %if.else
 
 land.lhs.true:                                    ; preds = %entry
-  %2 = load i32* %c0, align 4
-  %3 = load i32* %d0, align 4
+  %2 = load i32, i32* %c0, align 4
+  %3 = load i32, i32* %d0, align 4
   %cmp1 = icmp ne i32 %2, %3
   br i1 %cmp1, label %if.then, label %if.else
 
@@ -42,14 +42,14 @@ if.else:                                          ; preds = %land.lhs.true, %ent
   br label %if.end
 
 if.end:                                           ; preds = %if.else, %if.then
-  %4 = load i32* %a1, align 4
-  %5 = load i32* %b1, align 4
+  %4 = load i32, i32* %a1, align 4
+  %5 = load i32, i32* %b1, align 4
   %cmp2 = icmp ne i32 %4, %5
   br i1 %cmp2, label %land.lhs.true3, label %if.else6
 
 land.lhs.true3:                                   ; preds = %if.end
-  %6 = load i32* %c1, align 4
-  %7 = load i32* %d1, align 4
+  %6 = load i32, i32* %c1, align 4
+  %7 = load i32, i32* %d1, align 4
   %cmp4 = icmp ne i32 %6, %7
   br i1 %cmp4, label %if.then5, label %if.else6
 
diff --git a/test/CodeGen/R600/private-memory-atomics.ll b/test/CodeGen/R600/private-memory-atomics.ll
index 3ceb0c00d114..a008ac98a43b 100644
--- a/test/CodeGen/R600/private-memory-atomics.ll
+++ b/test/CodeGen/R600/private-memory-atomics.ll
@@ -7,11 +7,11 @@
 define void @atomicrmw_private(i32 addrspace(1)* %out, i32 %in) nounwind {
 entry:
   %tmp = alloca [2 x i32]
-  %tmp1 = getelementptr [2 x i32]* %tmp, i32 0, i32 0
-  %tmp2 = getelementptr [2 x i32]* %tmp, i32 0, i32 1
+  %tmp1 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 0
+  %tmp2 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 1
   store i32 0, i32* %tmp1
   store i32 1, i32* %tmp2
-  %tmp3 = getelementptr [2 x i32]* %tmp, i32 0, i32 %in
+  %tmp3 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 %in
   %tmp4 = atomicrmw add i32* %tmp3, i32 7 acq_rel
   store i32 %tmp4, i32 addrspace(1)* %out
   ret void
@@ -20,11 +20,11 @@ entry:
 define void @cmpxchg_private(i32 addrspace(1)* %out, i32 %in) nounwind {
 entry:
   %tmp = alloca [2 x i32]
-  %tmp1 = getelementptr [2 x i32]* %tmp, i32 0, i32 0
-  %tmp2 = getelementptr [2 x i32]* %tmp, i32 0, i32 1
+  %tmp1 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 0
+  %tmp2 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 1
   store i32 0, i32* %tmp1
   store i32 1, i32* %tmp2
-  %tmp3 = getelementptr [2 x i32]* %tmp, i32 0, i32 %in
+  %tmp3 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 %in
   %tmp4 = cmpxchg i32* %tmp3, i32 0, i32 1 acq_rel monotonic
   %val = extractvalue { i32, i1 } %tmp4, 0
   store i32 %val, i32 addrspace(1)* %out
diff --git a/test/CodeGen/R600/private-memory-broken.ll b/test/CodeGen/R600/private-memory-broken.ll
index 10590a9802fb..6b18a19f1956 100644
--- a/test/CodeGen/R600/private-memory-broken.ll
+++ b/test/CodeGen/R600/private-memory-broken.ll
@@ -10,11 +10,11 @@ declare i32 @foo(i32*) nounwind
 define void @call_private(i32 addrspace(1)* %out, i32 %in) nounwind {
 entry:
   %tmp = alloca [2 x i32]
-  %tmp1 = getelementptr [2 x i32]* %tmp, i32 0, i32 0
-  %tmp2 = getelementptr [2 x i32]* %tmp, i32 0, i32 1
+  %tmp1 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 0
+  %tmp2 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 1
   store i32 0, i32* %tmp1
   store i32 1, i32* %tmp2
-  %tmp3 = getelementptr [2 x i32]* %tmp, i32 0, i32 %in
+  %tmp3 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 %in
   %val = call i32 @foo(i32* %tmp3) nounwind
   store i32 %val, i32 addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/private-memory.ll b/test/CodeGen/R600/private-memory.ll
index 15153c69a48d..1c5629780508 100644
--- a/test/CodeGen/R600/private-memory.ll
+++ b/test/CodeGen/R600/private-memory.ll
@@ -1,6 +1,8 @@
 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
 ; RUN: llc -show-mc-encoding -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck %s -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC
 ; RUN: llc -show-mc-encoding -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC
+; RUN: llc -show-mc-encoding -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck %s -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC
+; RUN: llc -show-mc-encoding -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC
 
 declare i32 @llvm.r600.read.tidig.x() nounwind readnone
 
@@ -21,19 +23,19 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone
 define void @mova_same_clause(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) {
 entry:
   %stack = alloca [5 x i32], align 4
-  %0 = load i32 addrspace(1)* %in, align 4
-  %arrayidx1 = getelementptr inbounds [5 x i32]* %stack, i32 0, i32 %0
+  %0 = load i32, i32 addrspace(1)* %in, align 4
+  %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0
   store i32 4, i32* %arrayidx1, align 4
-  %arrayidx2 = getelementptr inbounds i32 addrspace(1)* %in, i32 1
-  %1 = load i32 addrspace(1)* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds [5 x i32]* %stack, i32 0, i32 %1
+  %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
+  %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1
   store i32 5, i32* %arrayidx3, align 4
-  %arrayidx10 = getelementptr inbounds [5 x i32]* %stack, i32 0, i32 0
-  %2 = load i32* %arrayidx10, align 4
+  %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0
+  %2 = load i32, i32* %arrayidx10, align 4
   store i32 %2, i32 addrspace(1)* %out, align 4
-  %arrayidx12 = getelementptr inbounds [5 x i32]* %stack, i32 0, i32 1
-  %3 = load i32* %arrayidx12
-  %arrayidx13 = getelementptr inbounds i32 addrspace(1)* %out, i32 1
+  %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1
+  %3 = load i32, i32* %arrayidx12
+  %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
   store i32 %3, i32 addrspace(1)* %arrayidx13
   ret void
 }
@@ -55,18 +57,18 @@ define void @multiple_structs(i32 addrspace(1)* %out) {
 entry:
   %a = alloca %struct.point
   %b = alloca %struct.point
-  %a.x.ptr = getelementptr %struct.point* %a, i32 0, i32 0
-  %a.y.ptr = getelementptr %struct.point* %a, i32 0, i32 1
-  %b.x.ptr = getelementptr %struct.point* %b, i32 0, i32 0
-  %b.y.ptr = getelementptr %struct.point* %b, i32 0, i32 1
+  %a.x.ptr = getelementptr %struct.point, %struct.point* %a, i32 0, i32 0
+  %a.y.ptr = getelementptr %struct.point, %struct.point* %a, i32 0, i32 1
+  %b.x.ptr = getelementptr %struct.point, %struct.point* %b, i32 0, i32 0
+  %b.y.ptr = getelementptr %struct.point, %struct.point* %b, i32 0, i32 1
   store i32 0, i32* %a.x.ptr
   store i32 1, i32* %a.y.ptr
   store i32 2, i32* %b.x.ptr
   store i32 3, i32* %b.y.ptr
-  %a.indirect.ptr = getelementptr %struct.point* %a, i32 0, i32 0
-  %b.indirect.ptr = getelementptr %struct.point* %b, i32 0, i32 0
-  %a.indirect = load i32* %a.indirect.ptr
-  %b.indirect = load i32* %b.indirect.ptr
+  %a.indirect.ptr = getelementptr %struct.point, %struct.point* %a, i32 0, i32 0
+  %b.indirect.ptr = getelementptr %struct.point, %struct.point* %b, i32 0, i32 0
+  %a.indirect = load i32, i32* %a.indirect.ptr
+  %b.indirect = load i32, i32* %b.indirect.ptr
   %0 = add i32 %a.indirect, %b.indirect
   store i32 %0, i32 addrspace(1)* %out
   ret void
@@ -84,21 +86,21 @@ define void @direct_loop(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 entry:
   %prv_array_const = alloca [2 x i32]
   %prv_array = alloca [2 x i32]
-  %a = load i32 addrspace(1)* %in
-  %b_src_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %b = load i32 addrspace(1)* %b_src_ptr
-  %a_dst_ptr = getelementptr [2 x i32]* %prv_array_const, i32 0, i32 0
+  %a = load i32, i32 addrspace(1)* %in
+  %b_src_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %b = load i32, i32 addrspace(1)* %b_src_ptr
+  %a_dst_ptr = getelementptr [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 0
   store i32 %a, i32* %a_dst_ptr
-  %b_dst_ptr = getelementptr [2 x i32]* %prv_array_const, i32 0, i32 1
+  %b_dst_ptr = getelementptr [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 1
   store i32 %b, i32* %b_dst_ptr
   br label %for.body
 
 for.body:
   %inc = phi i32 [0, %entry], [%count, %for.body]
-  %x_ptr = getelementptr [2 x i32]* %prv_array_const, i32 0, i32 0
-  %x = load i32* %x_ptr
-  %y_ptr = getelementptr [2 x i32]* %prv_array, i32 0, i32 0
-  %y = load i32* %y_ptr
+  %x_ptr = getelementptr [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 0
+  %x = load i32, i32* %x_ptr
+  %y_ptr = getelementptr [2 x i32], [2 x i32]* %prv_array, i32 0, i32 0
+  %y = load i32, i32* %y_ptr
   %xy = add i32 %x, %y
   store i32 %xy, i32* %y_ptr
   %count = add i32 %inc, 1
@@ -106,8 +108,8 @@ for.body:
   br i1 %done, label %for.end, label %for.body
 
 for.end:
-  %value_ptr = getelementptr [2 x i32]* %prv_array, i32 0, i32 0
-  %value = load i32* %value_ptr
+  %value_ptr = getelementptr [2 x i32], [2 x i32]* %prv_array, i32 0, i32 0
+  %value = load i32, i32* %value_ptr
   store i32 %value, i32 addrspace(1)* %out
   ret void
 }
@@ -122,12 +124,12 @@ for.end:
 define void @short_array(i32 addrspace(1)* %out, i32 %index) {
 entry:
   %0 = alloca [2 x i16]
-  %1 = getelementptr [2 x i16]* %0, i32 0, i32 0
-  %2 = getelementptr [2 x i16]* %0, i32 0, i32 1
+  %1 = getelementptr [2 x i16], [2 x i16]* %0, i32 0, i32 0
+  %2 = getelementptr [2 x i16], [2 x i16]* %0, i32 0, i32 1
   store i16 0, i16* %1
   store i16 1, i16* %2
-  %3 = getelementptr [2 x i16]* %0, i32 0, i32 %index
-  %4 = load i16* %3
+  %3 = getelementptr [2 x i16], [2 x i16]* %0, i32 0, i32 %index
+  %4 = load i16, i16* %3
   %5 = sext i16 %4 to i32
   store i32 %5, i32 addrspace(1)* %out
   ret void
@@ -142,12 +144,12 @@ entry:
 define void @char_array(i32 addrspace(1)* %out, i32 %index) {
 entry:
   %0 = alloca [2 x i8]
-  %1 = getelementptr [2 x i8]* %0, i32 0, i32 0
-  %2 = getelementptr [2 x i8]* %0, i32 0, i32 1
+  %1 = getelementptr [2 x i8], [2 x i8]* %0, i32 0, i32 0
+  %2 = getelementptr [2 x i8], [2 x i8]* %0, i32 0, i32 1
   store i8 0, i8* %1
   store i8 1, i8* %2
-  %3 = getelementptr [2 x i8]* %0, i32 0, i32 %index
-  %4 = load i8* %3
+  %3 = getelementptr [2 x i8], [2 x i8]* %0, i32 0, i32 %index
+  %4 = load i8, i8* %3
   %5 = sext i8 %4 to i32
   store i32 %5, i32 addrspace(1)* %out
   ret void
@@ -165,12 +167,12 @@ entry:
 define void @work_item_info(i32 addrspace(1)* %out, i32 %in) {
 entry:
   %0 = alloca [2 x i32]
-  %1 = getelementptr [2 x i32]* %0, i32 0, i32 0
-  %2 = getelementptr [2 x i32]* %0, i32 0, i32 1
+  %1 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 0
+  %2 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 1
   store i32 0, i32* %1
   store i32 1, i32* %2
-  %3 = getelementptr [2 x i32]* %0, i32 0, i32 %in
-  %4 = load i32* %3
+  %3 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 %in
+  %4 = load i32, i32* %3
   %5 = call i32 @llvm.r600.read.tidig.x()
   %6 = add i32 %4, %5
   store i32 %6, i32 addrspace(1)* %out
@@ -188,20 +190,20 @@ define void @no_overlap(i32 addrspace(1)* %out, i32 %in) {
 entry:
   %0 = alloca [3 x i8], align 1
   %1 = alloca [2 x i8], align 1
-  %2 = getelementptr [3 x i8]* %0, i32 0, i32 0
-  %3 = getelementptr [3 x i8]* %0, i32 0, i32 1
-  %4 = getelementptr [3 x i8]* %0, i32 0, i32 2
-  %5 = getelementptr [2 x i8]* %1, i32 0, i32 0
-  %6 = getelementptr [2 x i8]* %1, i32 0, i32 1
+  %2 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 0
+  %3 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 1
+  %4 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 2
+  %5 = getelementptr [2 x i8], [2 x i8]* %1, i32 0, i32 0
+  %6 = getelementptr [2 x i8], [2 x i8]* %1, i32 0, i32 1
   store i8 0, i8* %2
   store i8 1, i8* %3
   store i8 2, i8* %4
   store i8 1, i8* %5
   store i8 0, i8* %6
-  %7 = getelementptr [3 x i8]* %0, i32 0, i32 %in
-  %8 = getelementptr [2 x i8]* %1, i32 0, i32 %in
-  %9 = load i8* %7
-  %10 = load i8* %8
+  %7 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 %in
+  %8 = getelementptr [2 x i8], [2 x i8]* %1, i32 0, i32 %in
+  %9 = load i8, i8* %7
+  %10 = load i8, i8* %8
   %11 = add i8 %9, %10
   %12 = sext i8 %11 to i32
   store i32 %12, i32 addrspace(1)* %out
@@ -211,12 +213,12 @@ entry:
 define void @char_array_array(i32 addrspace(1)* %out, i32 %index) {
 entry:
   %alloca = alloca [2 x [2 x i8]]
-  %gep0 = getelementptr [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 0
-  %gep1 = getelementptr [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 1
+  %gep0 = getelementptr [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 0
+  %gep1 = getelementptr [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 1
   store i8 0, i8* %gep0
   store i8 1, i8* %gep1
-  %gep2 = getelementptr [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 %index
-  %load = load i8* %gep2
+  %gep2 = getelementptr [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 %index
+  %load = load i8, i8* %gep2
   %sext = sext i8 %load to i32
   store i32 %sext, i32 addrspace(1)* %out
   ret void
@@ -225,12 +227,12 @@ entry:
 define void @i32_array_array(i32 addrspace(1)* %out, i32 %index) {
 entry:
   %alloca = alloca [2 x [2 x i32]]
-  %gep0 = getelementptr [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 0
-  %gep1 = getelementptr [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 1
+  %gep0 = getelementptr [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 0
+  %gep1 = getelementptr [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 1
   store i32 0, i32* %gep0
   store i32 1, i32* %gep1
-  %gep2 = getelementptr [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 %index
-  %load = load i32* %gep2
+  %gep2 = getelementptr [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 %index
+  %load = load i32, i32* %gep2
   store i32 %load, i32 addrspace(1)* %out
   ret void
 }
@@ -238,12 +240,12 @@ entry:
 define void @i64_array_array(i64 addrspace(1)* %out, i32 %index) {
 entry:
   %alloca = alloca [2 x [2 x i64]]
-  %gep0 = getelementptr [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 0
-  %gep1 = getelementptr [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 1
+  %gep0 = getelementptr [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 0
+  %gep1 = getelementptr [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 1
   store i64 0, i64* %gep0
   store i64 1, i64* %gep1
-  %gep2 = getelementptr [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 %index
-  %load = load i64* %gep2
+  %gep2 = getelementptr [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 %index
+  %load = load i64, i64* %gep2
   store i64 %load, i64 addrspace(1)* %out
   ret void
 }
@@ -253,12 +255,12 @@ entry:
 define void @struct_array_array(i32 addrspace(1)* %out, i32 %index) {
 entry:
   %alloca = alloca [2 x [2 x %struct.pair32]]
-  %gep0 = getelementptr [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 0, i32 1
-  %gep1 = getelementptr [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 1, i32 1
+  %gep0 = getelementptr [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 0, i32 1
+  %gep1 = getelementptr [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 1, i32 1
   store i32 0, i32* %gep0
   store i32 1, i32* %gep1
-  %gep2 = getelementptr [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 %index, i32 0
-  %load = load i32* %gep2
+  %gep2 = getelementptr [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 %index, i32 0
+  %load = load i32, i32* %gep2
   store i32 %load, i32 addrspace(1)* %out
   ret void
 }
@@ -266,12 +268,12 @@ entry:
 define void @struct_pair32_array(i32 addrspace(1)* %out, i32 %index) {
 entry:
   %alloca = alloca [2 x %struct.pair32]
-  %gep0 = getelementptr [2 x %struct.pair32]* %alloca, i32 0, i32 0, i32 1
-  %gep1 = getelementptr [2 x %struct.pair32]* %alloca, i32 0, i32 1, i32 0
+  %gep0 = getelementptr [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 0, i32 1
+  %gep1 = getelementptr [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 1, i32 0
   store i32 0, i32* %gep0
   store i32 1, i32* %gep1
-  %gep2 = getelementptr [2 x %struct.pair32]* %alloca, i32 0, i32 %index, i32 0
-  %load = load i32* %gep2
+  %gep2 = getelementptr [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 %index, i32 0
+  %load = load i32, i32* %gep2
   store i32 %load, i32 addrspace(1)* %out
   ret void
 }
@@ -279,13 +281,13 @@ entry:
 define void @select_private(i32 addrspace(1)* %out, i32 %in) nounwind {
 entry:
   %tmp = alloca [2 x i32]
-  %tmp1 = getelementptr [2 x i32]* %tmp, i32 0, i32 0
-  %tmp2 = getelementptr [2 x i32]* %tmp, i32 0, i32 1
+  %tmp1 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 0
+  %tmp2 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 1
   store i32 0, i32* %tmp1
   store i32 1, i32* %tmp2
   %cmp = icmp eq i32 %in, 0
   %sel = select i1 %cmp, i32* %tmp1, i32* %tmp2
-  %load = load i32* %sel
+  %load = load i32, i32* %sel
   store i32 %load, i32 addrspace(1)* %out
   ret void
 }
@@ -299,13 +301,13 @@ entry:
 ; SI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:5
 define void @ptrtoint(i32 addrspace(1)* %out, i32 %a, i32 %b) {
   %alloca = alloca [16 x i32]
-  %tmp0 = getelementptr [16 x i32]* %alloca, i32 0, i32 %a
+  %tmp0 = getelementptr [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a
   store i32 5, i32* %tmp0
   %tmp1 = ptrtoint [16 x i32]* %alloca to i32
   %tmp2 = add i32 %tmp1, 5
   %tmp3 = inttoptr i32 %tmp2 to i32*
-  %tmp4 = getelementptr i32* %tmp3, i32 %b
-  %tmp5 = load i32* %tmp4
+  %tmp4 = getelementptr i32, i32* %tmp3, i32 %b
+  %tmp5 = load i32, i32* %tmp4
   store i32 %tmp5, i32 addrspace(1)* %out
   ret void
 }
diff --git a/test/CodeGen/R600/pv-packing.ll b/test/CodeGen/R600/pv-packing.ll
index e5615b99728e..abeae563ff3f 100644
--- a/test/CodeGen/R600/pv-packing.ll
+++ b/test/CodeGen/R600/pv-packing.ll
@@ -14,8 +14,8 @@ main_body:
   %6 = extractelement <4 x float> %reg3, i32 0
   %7 = extractelement <4 x float> %reg3, i32 1
   %8 = extractelement <4 x float> %reg3, i32 2
-  %9 = load <4 x float> addrspace(8)* null
-  %10 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %9 = load <4 x float>, <4 x float> addrspace(8)* null
+  %10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %11 = call float @llvm.AMDGPU.dp4(<4 x float> %9, <4 x float> %9)
   %12 = fmul float %0, %3
   %13 = fadd float %12, %6
diff --git a/test/CodeGen/R600/pv.ll b/test/CodeGen/R600/pv.ll
index 1908f15949a2..9a57dd19765a 100644
--- a/test/CodeGen/R600/pv.ll
+++ b/test/CodeGen/R600/pv.ll
@@ -33,63 +33,63 @@ main_body:
   %25 = extractelement <4 x float> %reg7, i32 1
   %26 = extractelement <4 x float> %reg7, i32 2
   %27 = extractelement <4 x float> %reg7, i32 3
-  %28 = load <4 x float> addrspace(8)* null
+  %28 = load <4 x float>, <4 x float> addrspace(8)* null
   %29 = extractelement <4 x float> %28, i32 0
   %30 = fmul float %0, %29
-  %31 = load <4 x float> addrspace(8)* null
+  %31 = load <4 x float>, <4 x float> addrspace(8)* null
   %32 = extractelement <4 x float> %31, i32 1
   %33 = fmul float %0, %32
-  %34 = load <4 x float> addrspace(8)* null
+  %34 = load <4 x float>, <4 x float> addrspace(8)* null
   %35 = extractelement <4 x float> %34, i32 2
   %36 = fmul float %0, %35
-  %37 = load <4 x float> addrspace(8)* null
+  %37 = load <4 x float>, <4 x float> addrspace(8)* null
   %38 = extractelement <4 x float> %37, i32 3
   %39 = fmul float %0, %38
-  %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %40 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %41 = extractelement <4 x float> %40, i32 0
   %42 = fmul float %1, %41
   %43 = fadd float %42, %30
-  %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %44 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %45 = extractelement <4 x float> %44, i32 1
   %46 = fmul float %1, %45
   %47 = fadd float %46, %33
-  %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %48 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %49 = extractelement <4 x float> %48, i32 2
   %50 = fmul float %1, %49
   %51 = fadd float %50, %36
-  %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %52 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %53 = extractelement <4 x float> %52, i32 3
   %54 = fmul float %1, %53
   %55 = fadd float %54, %39
-  %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %56 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %57 = extractelement <4 x float> %56, i32 0
   %58 = fmul float %2, %57
   %59 = fadd float %58, %43
-  %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %60 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %61 = extractelement <4 x float> %60, i32 1
   %62 = fmul float %2, %61
   %63 = fadd float %62, %47
-  %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %64 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %65 = extractelement <4 x float> %64, i32 2
   %66 = fmul float %2, %65
   %67 = fadd float %66, %51
-  %68 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %68 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %69 = extractelement <4 x float> %68, i32 3
   %70 = fmul float %2, %69
   %71 = fadd float %70, %55
-  %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+  %72 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
   %73 = extractelement <4 x float> %72, i32 0
   %74 = fmul float %3, %73
   %75 = fadd float %74, %59
-  %76 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+  %76 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
   %77 = extractelement <4 x float> %76, i32 1
   %78 = fmul float %3, %77
   %79 = fadd float %78, %63
-  %80 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+  %80 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
   %81 = extractelement <4 x float> %80, i32 2
   %82 = fmul float %3, %81
   %83 = fadd float %82, %67
-  %84 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+  %84 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
   %85 = extractelement <4 x float> %84, i32 3
   %86 = fmul float %3, %85
   %87 = fadd float %86, %71
@@ -107,15 +107,15 @@ main_body:
   %99 = fmul float %4, %98
   %100 = fmul float %5, %98
   %101 = fmul float %6, %98
-  %102 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+  %102 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
   %103 = extractelement <4 x float> %102, i32 0
   %104 = fmul float %103, %8
   %105 = fadd float %104, %20
-  %106 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+  %106 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
   %107 = extractelement <4 x float> %106, i32 1
   %108 = fmul float %107, %9
   %109 = fadd float %108, %21
-  %110 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+  %110 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
   %111 = extractelement <4 x float> %110, i32 2
   %112 = fmul float %111, %10
   %113 = fadd float %112, %22
@@ -123,11 +123,11 @@ main_body:
   %115 = call float @llvm.AMDIL.clamp.(float %109, float 0.000000e+00, float 1.000000e+00)
   %116 = call float @llvm.AMDIL.clamp.(float %113, float 0.000000e+00, float 1.000000e+00)
   %117 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00)
-  %118 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
+  %118 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
   %119 = extractelement <4 x float> %118, i32 0
-  %120 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
+  %120 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
   %121 = extractelement <4 x float> %120, i32 1
-  %122 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
+  %122 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
   %123 = extractelement <4 x float> %122, i32 2
   %124 = insertelement <4 x float> undef, float %99, i32 0
   %125 = insertelement <4 x float> %124, float %100, i32 1
@@ -138,11 +138,11 @@ main_body:
   %130 = insertelement <4 x float> %129, float %123, i32 2
   %131 = insertelement <4 x float> %130, float 0.000000e+00, i32 3
   %132 = call float @llvm.AMDGPU.dp4(<4 x float> %127, <4 x float> %131)
-  %133 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
+  %133 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
   %134 = extractelement <4 x float> %133, i32 0
-  %135 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
+  %135 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
   %136 = extractelement <4 x float> %135, i32 1
-  %137 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
+  %137 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
   %138 = extractelement <4 x float> %137, i32 2
   %139 = insertelement <4 x float> undef, float %99, i32 0
   %140 = insertelement <4 x float> %139, float %100, i32 1
@@ -153,31 +153,31 @@ main_body:
   %145 = insertelement <4 x float> %144, float %138, i32 2
   %146 = insertelement <4 x float> %145, float 0.000000e+00, i32 3
   %147 = call float @llvm.AMDGPU.dp4(<4 x float> %142, <4 x float> %146)
-  %148 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
+  %148 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
   %149 = extractelement <4 x float> %148, i32 0
   %150 = fmul float %149, %8
-  %151 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
+  %151 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
   %152 = extractelement <4 x float> %151, i32 1
   %153 = fmul float %152, %9
-  %154 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
+  %154 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
   %155 = extractelement <4 x float> %154, i32 2
   %156 = fmul float %155, %10
-  %157 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+  %157 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
   %158 = extractelement <4 x float> %157, i32 0
   %159 = fmul float %158, %12
-  %160 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+  %160 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
   %161 = extractelement <4 x float> %160, i32 1
   %162 = fmul float %161, %13
-  %163 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+  %163 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
   %164 = extractelement <4 x float> %163, i32 2
   %165 = fmul float %164, %14
-  %166 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
+  %166 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
   %167 = extractelement <4 x float> %166, i32 0
   %168 = fmul float %167, %16
-  %169 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
+  %169 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
   %170 = extractelement <4 x float> %169, i32 1
   %171 = fmul float %170, %17
-  %172 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
+  %172 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
   %173 = extractelement <4 x float> %172, i32 2
   %174 = fmul float %173, %18
   %175 = fcmp uge float %132, 0.000000e+00
diff --git a/test/CodeGen/R600/r600-export-fix.ll b/test/CodeGen/R600/r600-export-fix.ll
index 7d7285632078..7cb80195b368 100644
--- a/test/CodeGen/R600/r600-export-fix.ll
+++ b/test/CodeGen/R600/r600-export-fix.ll
@@ -16,83 +16,83 @@ main_body:
   %1 = extractelement <4 x float> %reg1, i32 1
   %2 = extractelement <4 x float> %reg1, i32 2
   %3 = extractelement <4 x float> %reg1, i32 3
-  %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+  %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
   %5 = extractelement <4 x float> %4, i32 0
   %6 = fmul float %5, %0
-  %7 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+  %7 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
   %8 = extractelement <4 x float> %7, i32 1
   %9 = fmul float %8, %0
-  %10 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+  %10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
   %11 = extractelement <4 x float> %10, i32 2
   %12 = fmul float %11, %0
-  %13 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+  %13 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
   %14 = extractelement <4 x float> %13, i32 3
   %15 = fmul float %14, %0
-  %16 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
+  %16 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
   %17 = extractelement <4 x float> %16, i32 0
   %18 = fmul float %17, %1
   %19 = fadd float %18, %6
-  %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
+  %20 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
   %21 = extractelement <4 x float> %20, i32 1
   %22 = fmul float %21, %1
   %23 = fadd float %22, %9
-  %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
+  %24 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
   %25 = extractelement <4 x float> %24, i32 2
   %26 = fmul float %25, %1
   %27 = fadd float %26, %12
-  %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
+  %28 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
   %29 = extractelement <4 x float> %28, i32 3
   %30 = fmul float %29, %1
   %31 = fadd float %30, %15
-  %32 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
+  %32 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
   %33 = extractelement <4 x float> %32, i32 0
   %34 = fmul float %33, %2
   %35 = fadd float %34, %19
-  %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
+  %36 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
   %37 = extractelement <4 x float> %36, i32 1
   %38 = fmul float %37, %2
   %39 = fadd float %38, %23
-  %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
+  %40 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
   %41 = extractelement <4 x float> %40, i32 2
   %42 = fmul float %41, %2
   %43 = fadd float %42, %27
-  %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
+  %44 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
   %45 = extractelement <4 x float> %44, i32 3
   %46 = fmul float %45, %2
   %47 = fadd float %46, %31
-  %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
+  %48 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
   %49 = extractelement <4 x float> %48, i32 0
   %50 = fmul float %49, %3
   %51 = fadd float %50, %35
-  %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
+  %52 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
   %53 = extractelement <4 x float> %52, i32 1
   %54 = fmul float %53, %3
   %55 = fadd float %54, %39
-  %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
+  %56 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
   %57 = extractelement <4 x float> %56, i32 2
   %58 = fmul float %57, %3
   %59 = fadd float %58, %43
-  %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
+  %60 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
   %61 = extractelement <4 x float> %60, i32 3
   %62 = fmul float %61, %3
   %63 = fadd float %62, %47
-  %64 = load <4 x float> addrspace(8)* null
+  %64 = load <4 x float>, <4 x float> addrspace(8)* null
   %65 = extractelement <4 x float> %64, i32 0
-  %66 = load <4 x float> addrspace(8)* null
+  %66 = load <4 x float>, <4 x float> addrspace(8)* null
   %67 = extractelement <4 x float> %66, i32 1
-  %68 = load <4 x float> addrspace(8)* null
+  %68 = load <4 x float>, <4 x float> addrspace(8)* null
   %69 = extractelement <4 x float> %68, i32 2
-  %70 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %70 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %71 = extractelement <4 x float> %70, i32 0
-  %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %72 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %73 = extractelement <4 x float> %72, i32 1
-  %74 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %74 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %75 = extractelement <4 x float> %74, i32 2
-  %76 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+  %76 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
   %77 = extractelement <4 x float> %76, i32 0
-  %78 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+  %78 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
   %79 = extractelement <4 x float> %78, i32 1
-  %80 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+  %80 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
   %81 = extractelement <4 x float> %80, i32 2
   %82 = insertelement <4 x float> undef, float %51, i32 0
   %83 = insertelement <4 x float> %82, float %55, i32 1
diff --git a/test/CodeGen/R600/r600cfg.ll b/test/CodeGen/R600/r600cfg.ll
index dddc9de7e963..c7b9d65220f3 100644
--- a/test/CodeGen/R600/r600cfg.ll
+++ b/test/CodeGen/R600/r600cfg.ll
@@ -83,7 +83,7 @@ ELSE45:                                           ; preds = %ENDIF40
 ENDIF43:                                          ; preds = %ELSE45, %IF44
   %.sink = phi i32 [ %49, %IF44 ], [ %51, %ELSE45 ]
   %52 = bitcast i32 %.sink to float
-  %53 = load <4 x float> addrspace(8)* null
+  %53 = load <4 x float>, <4 x float> addrspace(8)* null
   %54 = extractelement <4 x float> %53, i32 0
   %55 = bitcast float %54 to i32
   br label %LOOP47
diff --git a/test/CodeGen/R600/register-count-comments.ll b/test/CodeGen/R600/register-count-comments.ll
index 2b49f977def7..de6bfb310883 100644
--- a/test/CodeGen/R600/register-count-comments.ll
+++ b/test/CodeGen/R600/register-count-comments.ll
@@ -9,11 +9,11 @@ declare i32 @llvm.SI.tid() nounwind readnone
 ; SI: ; NumVgprs: {{[0-9]+}}
 define void @foo(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %abase, i32 addrspace(1)* %bbase) nounwind {
   %tid = call i32 @llvm.SI.tid() nounwind readnone
-  %aptr = getelementptr i32 addrspace(1)* %abase, i32 %tid
-  %bptr = getelementptr i32 addrspace(1)* %bbase, i32 %tid
-  %outptr = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %a = load i32 addrspace(1)* %aptr, align 4
-  %b = load i32 addrspace(1)* %bptr, align 4
+  %aptr = getelementptr i32, i32 addrspace(1)* %abase, i32 %tid
+  %bptr = getelementptr i32, i32 addrspace(1)* %bbase, i32 %tid
+  %outptr = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %a = load i32, i32 addrspace(1)* %aptr, align 4
+  %b = load i32, i32 addrspace(1)* %bptr, align 4
   %result = add i32 %a, %b
   store i32 %result, i32 addrspace(1)* %outptr, align 4
   ret void
diff --git a/test/CodeGen/R600/reorder-stores.ll b/test/CodeGen/R600/reorder-stores.ll
index ea50d5eed4df..187650ff9a53 100644
--- a/test/CodeGen/R600/reorder-stores.ll
+++ b/test/CodeGen/R600/reorder-stores.ll
@@ -12,8 +12,8 @@
 ; SI: buffer_store_dwordx2
 ; SI: s_endpgm
 define void @no_reorder_v2f64_global_load_store(<2 x double> addrspace(1)* nocapture %x, <2 x double> addrspace(1)* nocapture %y) nounwind {
-  %tmp1 = load <2 x double> addrspace(1)* %x, align 16
-  %tmp4 = load <2 x double> addrspace(1)* %y, align 16
+  %tmp1 = load <2 x double>, <2 x double> addrspace(1)* %x, align 16
+  %tmp4 = load <2 x double>, <2 x double> addrspace(1)* %y, align 16
   store <2 x double> %tmp4, <2 x double> addrspace(1)* %x, align 16
   store <2 x double> %tmp1, <2 x double> addrspace(1)* %y, align 16
   ret void
@@ -26,8 +26,8 @@ define void @no_reorder_v2f64_global_load_store(<2 x double> addrspace(1)* nocap
 ; SI: ds_write_b64
 ; SI: s_endpgm
 define void @no_reorder_scalarized_v2f64_local_load_store(<2 x double> addrspace(3)* nocapture %x, <2 x double> addrspace(3)* nocapture %y) nounwind {
-  %tmp1 = load <2 x double> addrspace(3)* %x, align 16
-  %tmp4 = load <2 x double> addrspace(3)* %y, align 16
+  %tmp1 = load <2 x double>, <2 x double> addrspace(3)* %x, align 16
+  %tmp4 = load <2 x double>, <2 x double> addrspace(3)* %y, align 16
   store <2 x double> %tmp4, <2 x double> addrspace(3)* %x, align 16
   store <2 x double> %tmp1, <2 x double> addrspace(3)* %y, align 16
   ret void
@@ -76,8 +76,8 @@ define void @no_reorder_scalarized_v2f64_local_load_store(<2 x double> addrspace
 ; SI: buffer_store_dword
 ; SI: s_endpgm
 define void @no_reorder_split_v8i32_global_load_store(<8 x i32> addrspace(1)* nocapture %x, <8 x i32> addrspace(1)* nocapture %y) nounwind {
-  %tmp1 = load <8 x i32> addrspace(1)* %x, align 32
-  %tmp4 = load <8 x i32> addrspace(1)* %y, align 32
+  %tmp1 = load <8 x i32>, <8 x i32> addrspace(1)* %x, align 32
+  %tmp4 = load <8 x i32>, <8 x i32> addrspace(1)* %y, align 32
   store <8 x i32> %tmp4, <8 x i32> addrspace(1)* %x, align 32
   store <8 x i32> %tmp1, <8 x i32> addrspace(1)* %y, align 32
   ret void
@@ -91,8 +91,8 @@ define void @no_reorder_split_v8i32_global_load_store(<8 x i32> addrspace(1)* no
 ; SI: ds_write_b64
 ; SI: s_endpgm
 define void @no_reorder_extload_64(<2 x i32> addrspace(3)* nocapture %x, <2 x i32> addrspace(3)* nocapture %y) nounwind {
-  %tmp1 = load <2 x i32> addrspace(3)* %x, align 8
-  %tmp4 = load <2 x i32> addrspace(3)* %y, align 8
+  %tmp1 = load <2 x i32>, <2 x i32> addrspace(3)* %x, align 8
+  %tmp4 = load <2 x i32>, <2 x i32> addrspace(3)* %y, align 8
   %tmp1ext = zext <2 x i32> %tmp1 to <2 x i64>
   %tmp4ext = zext <2 x i32> %tmp4 to <2 x i64>
   %tmp7 = add <2 x i64> %tmp1ext, <i64 1, i64 1>
diff --git a/test/CodeGen/R600/rotl.i64.ll b/test/CodeGen/R600/rotl.i64.ll
index 6da17a4fea93..3f4ceb7e0310 100644
--- a/test/CodeGen/R600/rotl.i64.ll
+++ b/test/CodeGen/R600/rotl.i64.ll
@@ -28,8 +28,8 @@ entry:
 ; BOTH: s_endpgm
 define void @v_rotl_i64(i64 addrspace(1)* %in, i64 addrspace(1)* %xptr, i64 addrspace(1)* %yptr) {
 entry:
-  %x = load i64 addrspace(1)* %xptr, align 8
-  %y = load i64 addrspace(1)* %yptr, align 8
+  %x = load i64, i64 addrspace(1)* %xptr, align 8
+  %y = load i64, i64 addrspace(1)* %yptr, align 8
   %tmp0 = shl i64 %x, %y
   %tmp1 = sub i64 64, %y
   %tmp2 = lshr i64 %x, %tmp1
diff --git a/test/CodeGen/R600/rotr.i64.ll b/test/CodeGen/R600/rotr.i64.ll
index f1d1d265f366..586de44a566c 100644
--- a/test/CodeGen/R600/rotr.i64.ll
+++ b/test/CodeGen/R600/rotr.i64.ll
@@ -26,8 +26,8 @@ entry:
 ; BOTH: v_or_b32
 define void @v_rotr_i64(i64 addrspace(1)* %in, i64 addrspace(1)* %xptr, i64 addrspace(1)* %yptr) {
 entry:
-  %x = load i64 addrspace(1)* %xptr, align 8
-  %y = load i64 addrspace(1)* %yptr, align 8
+  %x = load i64, i64 addrspace(1)* %xptr, align 8
+  %y = load i64, i64 addrspace(1)* %yptr, align 8
   %tmp0 = sub i64 64, %y
   %tmp1 = shl i64 %x, %tmp0
   %tmp2 = lshr i64 %x, %y
@@ -50,8 +50,8 @@ entry:
 ; BOTH-LABEL: {{^}}v_rotr_v2i64:
 define void @v_rotr_v2i64(<2 x i64> addrspace(1)* %in, <2 x i64> addrspace(1)* %xptr, <2 x i64> addrspace(1)* %yptr) {
 entry:
-  %x = load <2 x i64> addrspace(1)* %xptr, align 8
-  %y = load <2 x i64> addrspace(1)* %yptr, align 8
+  %x = load <2 x i64>, <2 x i64> addrspace(1)* %xptr, align 8
+  %y = load <2 x i64>, <2 x i64> addrspace(1)* %yptr, align 8
   %tmp0 = sub <2 x i64> <i64 64, i64 64>, %y
   %tmp1 = shl <2 x i64> %x, %tmp0
   %tmp2 = lshr <2 x i64> %x, %y
diff --git a/test/CodeGen/R600/rsq.ll b/test/CodeGen/R600/rsq.ll
index b8a23df63d83..b67b800c7374 100644
--- a/test/CodeGen/R600/rsq.ll
+++ b/test/CodeGen/R600/rsq.ll
@@ -9,7 +9,7 @@ declare double @llvm.sqrt.f64(double) nounwind readnone
 ; SI: v_rsq_f32_e32
 ; SI: s_endpgm
 define void @rsq_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
-  %val = load float addrspace(1)* %in, align 4
+  %val = load float, float addrspace(1)* %in, align 4
   %sqrt = call float @llvm.sqrt.f32(float %val) nounwind readnone
   %div = fdiv float 1.0, %sqrt
   store float %div, float addrspace(1)* %out, align 4
@@ -21,7 +21,7 @@ define void @rsq_f32(float addrspace(1)* noalias %out, float addrspace(1)* noali
 ; SI-SAFE: v_sqrt_f64_e32
 ; SI: s_endpgm
 define void @rsq_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) nounwind {
-  %val = load double addrspace(1)* %in, align 4
+  %val = load double, double addrspace(1)* %in, align 4
   %sqrt = call double @llvm.sqrt.f64(double %val) nounwind readnone
   %div = fdiv double 1.0, %sqrt
   store double %div, double addrspace(1)* %out, align 4
@@ -57,14 +57,14 @@ define void @rsq_f32_sgpr(float addrspace(1)* noalias %out, float %val) nounwind
 ; SI: s_endpgm
 define void @rsqrt_fmul(float addrspace(1)* %out, float addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %out.gep = getelementptr float addrspace(1)* %out, i32 %tid
-  %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
-  %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
-  %gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
+  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
+  %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
+  %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
+  %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2
 
-  %a = load float addrspace(1)* %gep.0
-  %b = load float addrspace(1)* %gep.1
-  %c = load float addrspace(1)* %gep.2
+  %a = load float, float addrspace(1)* %gep.0
+  %b = load float, float addrspace(1)* %gep.1
+  %c = load float, float addrspace(1)* %gep.2
 
   %x = call float @llvm.sqrt.f32(float %a)
   %y = fmul float %x, %b
diff --git a/test/CodeGen/R600/s_movk_i32.ll b/test/CodeGen/R600/s_movk_i32.ll
index 8be2d1d923cc..6b1a36c979c2 100644
--- a/test/CodeGen/R600/s_movk_i32.ll
+++ b/test/CodeGen/R600/s_movk_i32.ll
@@ -9,7 +9,7 @@
 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
 ; SI: s_endpgm
 define void @s_movk_i32_k0(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 4
+  %loada = load i64, i64 addrspace(1)* %a, align 4
   %or = or i64 %loada, 4295032831 ; ((1 << 16) - 1) | (1 << 32)
   store i64 %or, i64 addrspace(1)* %out
   ret void
@@ -23,7 +23,7 @@ define void @s_movk_i32_k0(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 add
 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
 ; SI: s_endpgm
 define void @s_movk_i32_k1(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 4
+  %loada = load i64, i64 addrspace(1)* %a, align 4
   %or = or i64 %loada, 4295000063 ; ((1 << 15) - 1) | (1 << 32)
   store i64 %or, i64 addrspace(1)* %out
   ret void
@@ -37,7 +37,7 @@ define void @s_movk_i32_k1(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 add
 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
 ; SI: s_endpgm
 define void @s_movk_i32_k2(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 4
+  %loada = load i64, i64 addrspace(1)* %a, align 4
   %or = or i64 %loada, 274877939711 ; ((1 << 15) - 1) | (64 << 32)
   store i64 %or, i64 addrspace(1)* %out
   ret void
@@ -51,7 +51,7 @@ define void @s_movk_i32_k2(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 add
 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
 ; SI: s_endpgm
 define void @s_movk_i32_k3(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 4
+  %loada = load i64, i64 addrspace(1)* %a, align 4
   %or = or i64 %loada, 4295000064 ; (1 << 15) | (1 << 32)
   store i64 %or, i64 addrspace(1)* %out
   ret void
@@ -65,7 +65,7 @@ define void @s_movk_i32_k3(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 add
 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
 ; SI: s_endpgm
 define void @s_movk_i32_k4(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 4
+  %loada = load i64, i64 addrspace(1)* %a, align 4
   %or = or i64 %loada, 4295098368 ; (1 << 17) | (1 << 32)
   store i64 %or, i64 addrspace(1)* %out
   ret void
@@ -79,7 +79,7 @@ define void @s_movk_i32_k4(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 add
 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
 ; SI: s_endpgm
 define void @s_movk_i32_k5(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 4
+  %loada = load i64, i64 addrspace(1)* %a, align 4
   %or = or i64 %loada, 18374967954648334319 ; -17 & 0xff00ffffffffffff
   store i64 %or, i64 addrspace(1)* %out
   ret void
@@ -93,7 +93,7 @@ define void @s_movk_i32_k5(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 add
 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
 ; SI: s_endpgm
 define void @s_movk_i32_k6(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 4
+  %loada = load i64, i64 addrspace(1)* %a, align 4
   %or = or i64 %loada, 270582939713 ; 65 | (63 << 32)
   store i64 %or, i64 addrspace(1)* %out
   ret void
@@ -107,7 +107,7 @@ define void @s_movk_i32_k6(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 add
 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
 ; SI: s_endpgm
 define void @s_movk_i32_k7(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 4
+  %loada = load i64, i64 addrspace(1)* %a, align 4
   %or = or i64 %loada, 70368744185856; ((1 << 13)) | ((1 << 14) << 32)
   store i64 %or, i64 addrspace(1)* %out
   ret void
@@ -122,7 +122,7 @@ define void @s_movk_i32_k7(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 add
 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
 ; SI: s_endpgm
 define void @s_movk_i32_k8(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 4
+  %loada = load i64, i64 addrspace(1)* %a, align 4
   %or = or i64 %loada, 1229782942255906816 ; 0x11111111ffff8000
   store i64 %or, i64 addrspace(1)* %out
   ret void
@@ -136,7 +136,7 @@ define void @s_movk_i32_k8(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 add
 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
 ; SI: s_endpgm
 define void @s_movk_i32_k9(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 4
+  %loada = load i64, i64 addrspace(1)* %a, align 4
   %or = or i64 %loada, 1229782942255906817 ; 0x11111111ffff8001
   store i64 %or, i64 addrspace(1)* %out
   ret void
@@ -150,7 +150,7 @@ define void @s_movk_i32_k9(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 add
 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
 ; SI: s_endpgm
 define void @s_movk_i32_k10(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 4
+  %loada = load i64, i64 addrspace(1)* %a, align 4
   %or = or i64 %loada, 1229782942255909000 ; 0x11111111ffff8888
   store i64 %or, i64 addrspace(1)* %out
   ret void
@@ -164,7 +164,7 @@ define void @s_movk_i32_k10(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 ad
 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
 ; SI: s_endpgm
 define void @s_movk_i32_k11(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 4
+  %loada = load i64, i64 addrspace(1)* %a, align 4
   %or = or i64 %loada, 1229782942255910911 ; 0x11111111ffff8fff
   store i64 %or, i64 addrspace(1)* %out
   ret void
@@ -178,7 +178,7 @@ define void @s_movk_i32_k11(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 ad
 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
 ; SI: s_endpgm
 define void @s_movk_i32_k12(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
-  %loada = load i64 addrspace(1)* %a, align 4
+  %loada = load i64, i64 addrspace(1)* %a, align 4
   %or = or i64 %loada, 1229782942255902721 ; 0x11111111ffff7001
   store i64 %or, i64 addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/saddo.ll b/test/CodeGen/R600/saddo.ll
index 8e625c1110a6..f8ced7942a60 100644
--- a/test/CodeGen/R600/saddo.ll
+++ b/test/CodeGen/R600/saddo.ll
@@ -28,8 +28,8 @@ define void @s_saddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32
 
 ; FUNC-LABEL: {{^}}v_saddo_i32:
 define void @v_saddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
-  %a = load i32 addrspace(1)* %aptr, align 4
-  %b = load i32 addrspace(1)* %bptr, align 4
+  %a = load i32, i32 addrspace(1)* %aptr, align 4
+  %b = load i32, i32 addrspace(1)* %bptr, align 4
   %sadd = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) nounwind
   %val = extractvalue { i32, i1 } %sadd, 0
   %carry = extractvalue { i32, i1 } %sadd, 1
@@ -52,8 +52,8 @@ define void @s_saddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64
 ; SI: v_add_i32
 ; SI: v_addc_u32
 define void @v_saddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
-  %a = load i64 addrspace(1)* %aptr, align 4
-  %b = load i64 addrspace(1)* %bptr, align 4
+  %a = load i64, i64 addrspace(1)* %aptr, align 4
+  %b = load i64, i64 addrspace(1)* %bptr, align 4
   %sadd = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) nounwind
   %val = extractvalue { i64, i1 } %sadd, 0
   %carry = extractvalue { i64, i1 } %sadd, 1
diff --git a/test/CodeGen/R600/salu-to-valu.ll b/test/CodeGen/R600/salu-to-valu.ll
index dfb181da1801..0b9649576545 100644
--- a/test/CodeGen/R600/salu-to-valu.ll
+++ b/test/CodeGen/R600/salu-to-valu.ll
@@ -27,11 +27,11 @@ entry:
 loop:
   %4 = phi i64 [0, %entry], [%5, %loop]
   %5 = add i64 %2, %4
-  %6 = getelementptr i8 addrspace(1)* %in, i64 %5
-  %7 = load i8 addrspace(1)* %6, align 1
+  %6 = getelementptr i8, i8 addrspace(1)* %in, i64 %5
+  %7 = load i8, i8 addrspace(1)* %6, align 1
   %8 = or i64 %5, 1
-  %9 = getelementptr i8 addrspace(1)* %in, i64 %8
-  %10 = load i8 addrspace(1)* %9, align 1
+  %9 = getelementptr i8, i8 addrspace(1)* %in, i64 %8
+  %10 = load i8, i8 addrspace(1)* %9, align 1
   %11 = add i8 %7, %10
   %12 = sext i8 %11 to i32
   store i32 %12, i32 addrspace(1)* %out
@@ -59,18 +59,18 @@ entry:
   br i1 %0, label %if, label %else
 
 if:
-  %1 = load i32 addrspace(2)* addrspace(1)* %in
+  %1 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %in
   br label %endif
 
 else:
-  %2 = getelementptr i32 addrspace(2)* addrspace(1)* %in
-  %3 = load i32 addrspace(2)* addrspace(1)* %2
+  %2 = getelementptr i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %in
+  %3 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %2
   br label %endif
 
 endif:
   %4 = phi i32 addrspace(2)*  [%1, %if], [%3, %else]
-  %5 = getelementptr i32 addrspace(2)* %4, i32 3000
-  %6 = load i32 addrspace(2)* %5
+  %5 = getelementptr i32, i32 addrspace(2)* %4, i32 3000
+  %6 = load i32, i32 addrspace(2)* %5
   store i32 %6, i32 addrspace(1)* %out
   ret void
 }
@@ -83,8 +83,8 @@ define void @smrd_valu2(i32 addrspace(1)* %out, [8 x i32] addrspace(2)* %in) {
 entry:
   %0 = call i32 @llvm.r600.read.tidig.x() nounwind readnone
   %1 = add i32 %0, 4
-  %2 = getelementptr [8 x i32] addrspace(2)* %in, i32 %0, i32 4
-  %3 = load i32 addrspace(2)* %2
+  %2 = getelementptr [8 x i32], [8 x i32] addrspace(2)* %in, i32 %0, i32 4
+  %3 = load i32, i32 addrspace(2)* %2
   store i32 %3, i32 addrspace(1)* %out
   ret void
 }
@@ -95,9 +95,9 @@ entry:
 define void @s_load_imm_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) {
 entry:
   %tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1
-  %tmp1 = getelementptr inbounds i32 addrspace(2)* %in, i32 %tmp0
+  %tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
   %tmp2 = bitcast i32 addrspace(2)* %tmp1 to <8 x i32> addrspace(2)*
-  %tmp3 = load <8 x i32> addrspace(2)* %tmp2, align 4
+  %tmp3 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp2, align 4
   store <8 x i32> %tmp3, <8 x i32> addrspace(1)* %out, align 32
   ret void
 }
@@ -110,9 +110,9 @@ entry:
 define void @s_load_imm_v16i32(<16 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) {
 entry:
   %tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1
-  %tmp1 = getelementptr inbounds i32 addrspace(2)* %in, i32 %tmp0
+  %tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
   %tmp2 = bitcast i32 addrspace(2)* %tmp1 to <16 x i32> addrspace(2)*
-  %tmp3 = load <16 x i32> addrspace(2)* %tmp2, align 4
+  %tmp3 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp2, align 4
   store <16 x i32> %tmp3, <16 x i32> addrspace(1)* %out, align 32
   ret void
 }
diff --git a/test/CodeGen/R600/scalar_to_vector.ll b/test/CodeGen/R600/scalar_to_vector.ll
index b82e5526f751..0970e5d30630 100644
--- a/test/CodeGen/R600/scalar_to_vector.ll
+++ b/test/CodeGen/R600/scalar_to_vector.ll
@@ -11,7 +11,7 @@
 ; SI: buffer_store_short [[RESULT]]
 ; SI: s_endpgm
 define void @scalar_to_vector_v2i32(<4 x i16> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %tmp1 = load i32 addrspace(1)* %in, align 4
+  %tmp1 = load i32, i32 addrspace(1)* %in, align 4
   %bc = bitcast i32 %tmp1 to <2 x i16>
   %tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   store <4 x i16> %tmp2, <4 x i16> addrspace(1)* %out, align 8
@@ -27,7 +27,7 @@ define void @scalar_to_vector_v2i32(<4 x i16> addrspace(1)* %out, i32 addrspace(
 ; SI: buffer_store_short [[RESULT]]
 ; SI: s_endpgm
 define void @scalar_to_vector_v2f32(<4 x i16> addrspace(1)* %out, float addrspace(1)* %in) nounwind {
-  %tmp1 = load float addrspace(1)* %in, align 4
+  %tmp1 = load float, float addrspace(1)* %in, align 4
   %bc = bitcast float %tmp1 to <2 x i16>
   %tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   store <4 x i16> %tmp2, <4 x i16> addrspace(1)* %out, align 8
@@ -39,7 +39,7 @@ define void @scalar_to_vector_v2f32(<4 x i16> addrspace(1)* %out, float addrspac
 
 
 ; define void @scalar_to_vector_test2(<8 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-;   %tmp1 = load i32 addrspace(1)* %in, align 4
+;   %tmp1 = load i32, i32 addrspace(1)* %in, align 4
 ;   %bc = bitcast i32 %tmp1 to <4 x i8>
 
 ;   %tmp2 = shufflevector <4 x i8> %bc, <4 x i8> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
diff --git a/test/CodeGen/R600/schedule-fs-loop-nested.ll b/test/CodeGen/R600/schedule-fs-loop-nested.ll
index b917ec6413e9..759197ca61f7 100644
--- a/test/CodeGen/R600/schedule-fs-loop-nested.ll
+++ b/test/CodeGen/R600/schedule-fs-loop-nested.ll
@@ -3,7 +3,7 @@
 
 define void @main() {
 main_body:
-  %0 = load <4 x float> addrspace(9)* null
+  %0 = load <4 x float>, <4 x float> addrspace(9)* null
   %1 = extractelement <4 x float> %0, i32 3
   %2 = fptosi float %1 to i32
   %3 = bitcast i32 %2 to float
@@ -20,11 +20,11 @@ main_body:
   %14 = bitcast float %12 to i32
   %15 = add i32 %13, %14
   %16 = bitcast i32 %15 to float
-  %17 = load <4 x float> addrspace(9)* null
+  %17 = load <4 x float>, <4 x float> addrspace(9)* null
   %18 = extractelement <4 x float> %17, i32 0
-  %19 = load <4 x float> addrspace(9)* null
+  %19 = load <4 x float>, <4 x float> addrspace(9)* null
   %20 = extractelement <4 x float> %19, i32 1
-  %21 = load <4 x float> addrspace(9)* null
+  %21 = load <4 x float>, <4 x float> addrspace(9)* null
   %22 = extractelement <4 x float> %21, i32 2
   br label %LOOP
 
diff --git a/test/CodeGen/R600/schedule-fs-loop.ll b/test/CodeGen/R600/schedule-fs-loop.ll
index d6c194b19b27..28cc08abc022 100644
--- a/test/CodeGen/R600/schedule-fs-loop.ll
+++ b/test/CodeGen/R600/schedule-fs-loop.ll
@@ -3,15 +3,15 @@
 
 define void @main() {
 main_body:
-  %0 = load <4 x float> addrspace(9)* null
+  %0 = load <4 x float>, <4 x float> addrspace(9)* null
   %1 = extractelement <4 x float> %0, i32 3
   %2 = fptosi float %1 to i32
   %3 = bitcast i32 %2 to float
-  %4 = load <4 x float> addrspace(9)* null
+  %4 = load <4 x float>, <4 x float> addrspace(9)* null
   %5 = extractelement <4 x float> %4, i32 0
-  %6 = load <4 x float> addrspace(9)* null
+  %6 = load <4 x float>, <4 x float> addrspace(9)* null
   %7 = extractelement <4 x float> %6, i32 1
-  %8 = load <4 x float> addrspace(9)* null
+  %8 = load <4 x float>, <4 x float> addrspace(9)* null
   %9 = extractelement <4 x float> %8, i32 2
   br label %LOOP
 
diff --git a/test/CodeGen/R600/schedule-global-loads.ll b/test/CodeGen/R600/schedule-global-loads.ll
index b6437d25b8cb..3f728fd873b3 100644
--- a/test/CodeGen/R600/schedule-global-loads.ll
+++ b/test/CodeGen/R600/schedule-global-loads.ll
@@ -14,9 +14,9 @@ declare i32 @llvm.r600.read.tidig.x() #1
 ; SI: buffer_store_dword [[REG0]]
 ; SI: buffer_store_dword [[REG1]]
 define void @cluster_global_arg_loads(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %ptr) #0 {
-  %load0 = load i32 addrspace(1)* %ptr, align 4
-  %gep = getelementptr i32 addrspace(1)* %ptr, i32 1
-  %load1 = load i32 addrspace(1)* %gep, align 4
+  %load0 = load i32, i32 addrspace(1)* %ptr, align 4
+  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 1
+  %load1 = load i32, i32 addrspace(1)* %gep, align 4
   store i32 %load0, i32 addrspace(1)* %out0, align 4
   store i32 %load1, i32 addrspace(1)* %out1, align 4
   ret void
@@ -29,9 +29,9 @@ define void @cluster_global_arg_loads(i32 addrspace(1)* %out0, i32 addrspace(1)*
 ; SI: buffer_load_dword
 define void @same_base_ptr_crash(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %offset) {
 entry:
-  %out1 = getelementptr i32 addrspace(1)* %out, i32 %offset
-  %tmp0 = load i32 addrspace(1)* %out
-  %tmp1 = load i32 addrspace(1)* %out1
+  %out1 = getelementptr i32, i32 addrspace(1)* %out, i32 %offset
+  %tmp0 = load i32, i32 addrspace(1)* %out
+  %tmp1 = load i32, i32 addrspace(1)* %out1
   %tmp2 = add i32 %tmp0, %tmp1
   store i32 %tmp2, i32 addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/schedule-if-2.ll b/test/CodeGen/R600/schedule-if-2.ll
index 38aad1850f81..549465096833 100644
--- a/test/CodeGen/R600/schedule-if-2.ll
+++ b/test/CodeGen/R600/schedule-if-2.ll
@@ -3,10 +3,10 @@
 
 define void @main() {
 main_body:
-  %0 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+  %0 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
   %1 = extractelement <4 x float> %0, i32 0
   %2 = fadd float 1.000000e+03, %1
-  %3 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %3 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %4 = extractelement <4 x float> %3, i32 0
   %5 = bitcast float %4 to i32
   %6 = icmp eq i32 %5, 0
@@ -47,7 +47,7 @@ IF:                                               ; preds = %main_body
   br label %ENDIF
 
 ELSE:                                             ; preds = %main_body
-  %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %36 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %37 = extractelement <4 x float> %36, i32 0
   %38 = bitcast float %37 to i32
   %39 = icmp eq i32 %38, 1
@@ -80,7 +80,7 @@ IF23:                                             ; preds = %ELSE
   %.28 = select i1 %54, float 0x36A0000000000000, float 0.000000e+00
   %55 = bitcast float %.28 to i32
   %56 = sitofp i32 %55 to float
-  %57 = load <4 x float> addrspace(8)* null
+  %57 = load <4 x float>, <4 x float> addrspace(8)* null
   %58 = extractelement <4 x float> %57, i32 0
   %59 = fsub float -0.000000e+00, %58
   %60 = fadd float %2, %59
diff --git a/test/CodeGen/R600/schedule-if.ll b/test/CodeGen/R600/schedule-if.ll
index f960c9323940..94c653c8f25b 100644
--- a/test/CodeGen/R600/schedule-if.ll
+++ b/test/CodeGen/R600/schedule-if.ll
@@ -3,7 +3,7 @@
 
 define void @main() {
 main_body:
-  %0 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %0 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %1 = extractelement <4 x float> %0, i32 0
   %2 = bitcast float %1 to i32
   %3 = icmp eq i32 %2, 0
@@ -14,7 +14,7 @@ main_body:
   br i1 %7, label %ENDIF, label %ELSE
 
 ELSE:                                             ; preds = %main_body
-  %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %9 = extractelement <4 x float> %8, i32 0
   %10 = bitcast float %9 to i32
   %11 = icmp eq i32 %10, 1
@@ -36,7 +36,7 @@ ENDIF:                                            ; preds = %IF13, %ELSE, %main_
   ret void
 
 IF13:                                             ; preds = %ELSE
-  %20 = load <4 x float> addrspace(8)* null
+  %20 = load <4 x float>, <4 x float> addrspace(8)* null
   %21 = extractelement <4 x float> %20, i32 0
   %22 = fsub float -0.000000e+00, %21
   %23 = fadd float 1.000000e+03, %22
diff --git a/test/CodeGen/R600/schedule-kernel-arg-loads.ll b/test/CodeGen/R600/schedule-kernel-arg-loads.ll
index 01d897ff18cb..6b3e0814c380 100644
--- a/test/CodeGen/R600/schedule-kernel-arg-loads.ll
+++ b/test/CodeGen/R600/schedule-kernel-arg-loads.ll
@@ -6,6 +6,13 @@
 ; SI-NEXT: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
 ; SI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
 ; SI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xe
+; VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x24
+; VI-NEXT: s_nop 0
+; VI-NEXT: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; VI-NEXT: s_nop 0
+; VI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
+; VI-NEXT: s_nop 0
+; VI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x38
 define void @cluster_arg_loads(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 %x, i32 %y) nounwind {
   store i32 %x, i32 addrspace(1)* %out0, align 4
   store i32 %y, i32 addrspace(1)* %out1, align 4
diff --git a/test/CodeGen/R600/schedule-vs-if-nested-loop-failure.ll b/test/CodeGen/R600/schedule-vs-if-nested-loop-failure.ll
index 76b655d712d0..3863afda5dd3 100644
--- a/test/CodeGen/R600/schedule-vs-if-nested-loop-failure.ll
+++ b/test/CodeGen/R600/schedule-vs-if-nested-loop-failure.ll
@@ -39,63 +39,63 @@ ENDIF:                                            ; preds = %main_body, %Flow2
   %temp3.0 = phi float [ 0.000000e+00, %main_body ], [ %101, %Flow2 ]
   %15 = extractelement <4 x float> %reg1, i32 1
   %16 = extractelement <4 x float> %reg1, i32 3
-  %17 = load <4 x float> addrspace(9)* null
+  %17 = load <4 x float>, <4 x float> addrspace(9)* null
   %18 = extractelement <4 x float> %17, i32 0
   %19 = fmul float %18, %0
-  %20 = load <4 x float> addrspace(9)* null
+  %20 = load <4 x float>, <4 x float> addrspace(9)* null
   %21 = extractelement <4 x float> %20, i32 1
   %22 = fmul float %21, %0
-  %23 = load <4 x float> addrspace(9)* null
+  %23 = load <4 x float>, <4 x float> addrspace(9)* null
   %24 = extractelement <4 x float> %23, i32 2
   %25 = fmul float %24, %0
-  %26 = load <4 x float> addrspace(9)* null
+  %26 = load <4 x float>, <4 x float> addrspace(9)* null
   %27 = extractelement <4 x float> %26, i32 3
   %28 = fmul float %27, %0
-  %29 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
+  %29 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
   %30 = extractelement <4 x float> %29, i32 0
   %31 = fmul float %30, %15
   %32 = fadd float %31, %19
-  %33 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
+  %33 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
   %34 = extractelement <4 x float> %33, i32 1
   %35 = fmul float %34, %15
   %36 = fadd float %35, %22
-  %37 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
+  %37 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
   %38 = extractelement <4 x float> %37, i32 2
   %39 = fmul float %38, %15
   %40 = fadd float %39, %25
-  %41 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
+  %41 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
   %42 = extractelement <4 x float> %41, i32 3
   %43 = fmul float %42, %15
   %44 = fadd float %43, %28
-  %45 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
+  %45 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
   %46 = extractelement <4 x float> %45, i32 0
   %47 = fmul float %46, %1
   %48 = fadd float %47, %32
-  %49 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
+  %49 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
   %50 = extractelement <4 x float> %49, i32 1
   %51 = fmul float %50, %1
   %52 = fadd float %51, %36
-  %53 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
+  %53 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
   %54 = extractelement <4 x float> %53, i32 2
   %55 = fmul float %54, %1
   %56 = fadd float %55, %40
-  %57 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
+  %57 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
   %58 = extractelement <4 x float> %57, i32 3
   %59 = fmul float %58, %1
   %60 = fadd float %59, %44
-  %61 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
+  %61 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
   %62 = extractelement <4 x float> %61, i32 0
   %63 = fmul float %62, %16
   %64 = fadd float %63, %48
-  %65 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
+  %65 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
   %66 = extractelement <4 x float> %65, i32 1
   %67 = fmul float %66, %16
   %68 = fadd float %67, %52
-  %69 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
+  %69 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
   %70 = extractelement <4 x float> %69, i32 2
   %71 = fmul float %70, %16
   %72 = fadd float %71, %56
-  %73 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
+  %73 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
   %74 = extractelement <4 x float> %73, i32 3
   %75 = fmul float %74, %16
   %76 = fadd float %75, %60
diff --git a/test/CodeGen/R600/schedule-vs-if-nested-loop.ll b/test/CodeGen/R600/schedule-vs-if-nested-loop.ll
index 33b20d36737b..8d980dbf8995 100644
--- a/test/CodeGen/R600/schedule-vs-if-nested-loop.ll
+++ b/test/CodeGen/R600/schedule-vs-if-nested-loop.ll
@@ -21,63 +21,63 @@ ENDIF:                                            ; preds = %ENDIF16, %LOOP, %ma
   %temp1.0 = phi float [ 1.000000e+00, %main_body ], [ %temp1.1, %LOOP ], [ %temp1.1, %ENDIF16 ]
   %temp2.0 = phi float [ 0.000000e+00, %main_body ], [ %temp2.1, %LOOP ], [ %temp2.1, %ENDIF16 ]
   %temp3.0 = phi float [ 0.000000e+00, %main_body ], [ %temp3.1, %LOOP ], [ %temp3.1, %ENDIF16 ]
-  %11 = load <4 x float> addrspace(9)* null
+  %11 = load <4 x float>, <4 x float> addrspace(9)* null
   %12 = extractelement <4 x float> %11, i32 0
   %13 = fmul float %12, %0
-  %14 = load <4 x float> addrspace(9)* null
+  %14 = load <4 x float>, <4 x float> addrspace(9)* null
   %15 = extractelement <4 x float> %14, i32 1
   %16 = fmul float %15, %0
-  %17 = load <4 x float> addrspace(9)* null
+  %17 = load <4 x float>, <4 x float> addrspace(9)* null
   %18 = extractelement <4 x float> %17, i32 2
   %19 = fmul float %18, %0
-  %20 = load <4 x float> addrspace(9)* null
+  %20 = load <4 x float>, <4 x float> addrspace(9)* null
   %21 = extractelement <4 x float> %20, i32 3
   %22 = fmul float %21, %0
-  %23 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
+  %23 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
   %24 = extractelement <4 x float> %23, i32 0
   %25 = fmul float %24, %1
   %26 = fadd float %25, %13
-  %27 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
+  %27 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
   %28 = extractelement <4 x float> %27, i32 1
   %29 = fmul float %28, %1
   %30 = fadd float %29, %16
-  %31 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
+  %31 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
   %32 = extractelement <4 x float> %31, i32 2
   %33 = fmul float %32, %1
   %34 = fadd float %33, %19
-  %35 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
+  %35 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
   %36 = extractelement <4 x float> %35, i32 3
   %37 = fmul float %36, %1
   %38 = fadd float %37, %22
-  %39 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
+  %39 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
   %40 = extractelement <4 x float> %39, i32 0
   %41 = fmul float %40, %2
   %42 = fadd float %41, %26
-  %43 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
+  %43 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
   %44 = extractelement <4 x float> %43, i32 1
   %45 = fmul float %44, %2
   %46 = fadd float %45, %30
-  %47 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
+  %47 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
   %48 = extractelement <4 x float> %47, i32 2
   %49 = fmul float %48, %2
   %50 = fadd float %49, %34
-  %51 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
+  %51 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
   %52 = extractelement <4 x float> %51, i32 3
   %53 = fmul float %52, %2
   %54 = fadd float %53, %38
-  %55 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
+  %55 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
   %56 = extractelement <4 x float> %55, i32 0
   %57 = fmul float %56, %3
   %58 = fadd float %57, %42
-  %59 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
+  %59 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
   %60 = extractelement <4 x float> %59, i32 1
   %61 = fmul float %60, %3
   %62 = fadd float %61, %46
-  %63 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
+  %63 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
   %64 = extractelement <4 x float> %63, i32 2
   %65 = fmul float %64, %3
   %66 = fadd float %65, %50
-  %67 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
+  %67 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3)
   %68 = extractelement <4 x float> %67, i32 3
   %69 = fmul float %68, %3
   %70 = fadd float %69, %54
diff --git a/test/CodeGen/R600/scratch-buffer.ll b/test/CodeGen/R600/scratch-buffer.ll
index 740328a495da..56088718ada8 100644
--- a/test/CodeGen/R600/scratch-buffer.ll
+++ b/test/CodeGen/R600/scratch-buffer.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck %s
 
 ; When a frame index offset is more than 12-bits, make sure we don't store
 ; it in mubuf's offset field.
@@ -18,23 +19,23 @@ entry:
   %scratch0 = alloca [8192 x i32]
   %scratch1 = alloca [8192 x i32]
 
-  %scratchptr0 = getelementptr [8192 x i32]* %scratch0, i32 0, i32 0
+  %scratchptr0 = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 0
   store i32 1, i32* %scratchptr0
 
-  %scratchptr1 = getelementptr [8192 x i32]* %scratch1, i32 0, i32 0
+  %scratchptr1 = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 0
   store i32 2, i32* %scratchptr1
 
   %cmp = icmp eq i32 %cond, 0
   br i1 %cmp, label %if, label %else
 
 if:
-  %if_ptr = getelementptr [8192 x i32]* %scratch0, i32 0, i32 %if_offset
-  %if_value = load i32* %if_ptr
+  %if_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %if_offset
+  %if_value = load i32, i32* %if_ptr
   br label %done
 
 else:
-  %else_ptr = getelementptr [8192 x i32]* %scratch1, i32 0, i32 %else_offset
-  %else_value = load i32* %else_ptr
+  %else_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %else_offset
+  %else_value = load i32, i32* %else_ptr
   br label %done
 
 done:
@@ -56,26 +57,26 @@ entry:
   %scratch0 = alloca [8192 x i32]
   %scratch1 = alloca [8192 x i32]
 
-  %offset0 = load i32 addrspace(1)* %offsets
-  %scratchptr0 = getelementptr [8192 x i32]* %scratch0, i32 0, i32 %offset0
+  %offset0 = load i32, i32 addrspace(1)* %offsets
+  %scratchptr0 = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %offset0
   store i32 %offset0, i32* %scratchptr0
 
-  %offsetptr1 = getelementptr i32 addrspace(1)* %offsets, i32 1
-  %offset1 = load i32 addrspace(1)* %offsetptr1
-  %scratchptr1 = getelementptr [8192 x i32]* %scratch1, i32 0, i32 %offset1
+  %offsetptr1 = getelementptr i32, i32 addrspace(1)* %offsets, i32 1
+  %offset1 = load i32, i32 addrspace(1)* %offsetptr1
+  %scratchptr1 = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %offset1
   store i32 %offset1, i32* %scratchptr1
 
   %cmp = icmp eq i32 %cond, 0
   br i1 %cmp, label %if, label %else
 
 if:
-  %if_ptr = getelementptr [8192 x i32]* %scratch0, i32 0, i32 %if_offset
-  %if_value = load i32* %if_ptr
+  %if_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %if_offset
+  %if_value = load i32, i32* %if_ptr
   br label %done
 
 else:
-  %else_ptr = getelementptr [8192 x i32]* %scratch1, i32 0, i32 %else_offset
-  %else_value = load i32* %else_ptr
+  %else_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %else_offset
+  %else_value = load i32, i32* %else_ptr
   br label %done
 
 done:
diff --git a/test/CodeGen/R600/sdiv.ll b/test/CodeGen/R600/sdiv.ll
index 07bb41768ee3..de645353a401 100644
--- a/test/CodeGen/R600/sdiv.ll
+++ b/test/CodeGen/R600/sdiv.ll
@@ -14,9 +14,9 @@
 ; FUNC-LABEL: {{^}}sdiv_i32:
 ; EG: CF_END
 define void @sdiv_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in
-  %den = load i32 addrspace(1) * %den_ptr
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in
+  %den = load i32, i32 addrspace(1) * %den_ptr
   %result = sdiv i32 %num, %den
   store i32 %result, i32 addrspace(1)* %out
   ret void
@@ -24,7 +24,7 @@ define void @sdiv_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 
 ; FUNC-LABEL: {{^}}sdiv_i32_4:
 define void @sdiv_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %num = load i32 addrspace(1) * %in
+  %num = load i32, i32 addrspace(1) * %in
   %result = sdiv i32 %num, 4
   store i32 %result, i32 addrspace(1)* %out
   ret void
@@ -44,39 +44,39 @@ define void @sdiv_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 ; SI: buffer_store_dword
 ; SI: s_endpgm
 define void @slow_sdiv_i32_3435(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %num = load i32 addrspace(1) * %in
+  %num = load i32, i32 addrspace(1) * %in
   %result = sdiv i32 %num, 3435
   store i32 %result, i32 addrspace(1)* %out
   ret void
 }
 
 define void @sdiv_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %den_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
-  %num = load <2 x i32> addrspace(1) * %in
-  %den = load <2 x i32> addrspace(1) * %den_ptr
+  %den_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
+  %num = load <2 x i32>, <2 x i32> addrspace(1) * %in
+  %den = load <2 x i32>, <2 x i32> addrspace(1) * %den_ptr
   %result = sdiv <2 x i32> %num, %den
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
   ret void
 }
 
 define void @sdiv_v2i32_4(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %num = load <2 x i32> addrspace(1) * %in
+  %num = load <2 x i32>, <2 x i32> addrspace(1) * %in
   %result = sdiv <2 x i32> %num, <i32 4, i32 4>
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
   ret void
 }
 
 define void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %den_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
-  %num = load <4 x i32> addrspace(1) * %in
-  %den = load <4 x i32> addrspace(1) * %den_ptr
+  %den_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
+  %num = load <4 x i32>, <4 x i32> addrspace(1) * %in
+  %den = load <4 x i32>, <4 x i32> addrspace(1) * %den_ptr
   %result = sdiv <4 x i32> %num, %den
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
 }
 
 define void @sdiv_v4i32_4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %num = load <4 x i32> addrspace(1) * %in
+  %num = load <4 x i32>, <4 x i32> addrspace(1) * %in
   %result = sdiv <4 x i32> %num, <i32 4, i32 4, i32 4, i32 4>
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/sdivrem24.ll b/test/CodeGen/R600/sdivrem24.ll
index e8c5c252bd72..ad5df39f5505 100644
--- a/test/CodeGen/R600/sdivrem24.ll
+++ b/test/CodeGen/R600/sdivrem24.ll
@@ -13,9 +13,9 @@
 ; EG-DAG: RECIP_IEEE
 ; EG: FLT_TO_INT
 define void @sdiv24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
-  %den_ptr = getelementptr i8 addrspace(1)* %in, i8 1
-  %num = load i8 addrspace(1) * %in
-  %den = load i8 addrspace(1) * %den_ptr
+  %den_ptr = getelementptr i8, i8 addrspace(1)* %in, i8 1
+  %num = load i8, i8 addrspace(1) * %in
+  %den = load i8, i8 addrspace(1) * %den_ptr
   %result = sdiv i8 %num, %den
   store i8 %result, i8 addrspace(1)* %out
   ret void
@@ -32,9 +32,9 @@ define void @sdiv24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
 ; EG-DAG: RECIP_IEEE
 ; EG: FLT_TO_INT
 define void @sdiv24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
-  %den_ptr = getelementptr i16 addrspace(1)* %in, i16 1
-  %num = load i16 addrspace(1) * %in, align 2
-  %den = load i16 addrspace(1) * %den_ptr, align 2
+  %den_ptr = getelementptr i16, i16 addrspace(1)* %in, i16 1
+  %num = load i16, i16 addrspace(1) * %in, align 2
+  %den = load i16, i16 addrspace(1) * %den_ptr, align 2
   %result = sdiv i16 %num, %den
   store i16 %result, i16 addrspace(1)* %out, align 2
   ret void
@@ -51,9 +51,9 @@ define void @sdiv24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
 ; EG-DAG: RECIP_IEEE
 ; EG: FLT_TO_INT
 define void @sdiv24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 8
   %den.i24.0 = shl i32 %den, 8
   %num.i24 = ashr i32 %num.i24.0, 8
@@ -70,9 +70,9 @@ define void @sdiv24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 ; EG-NOT: INT_TO_FLT
 ; EG-NOT: RECIP_IEEE
 define void @sdiv25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 7
   %den.i24.0 = shl i32 %den, 7
   %num.i24 = ashr i32 %num.i24.0, 7
@@ -89,9 +89,9 @@ define void @sdiv25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 ; EG-NOT: INT_TO_FLT
 ; EG-NOT: RECIP_IEEE
 define void @test_no_sdiv24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 8
   %den.i24.0 = shl i32 %den, 7
   %num.i24 = ashr i32 %num.i24.0, 8
@@ -108,9 +108,9 @@ define void @test_no_sdiv24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in)
 ; EG-NOT: INT_TO_FLT
 ; EG-NOT: RECIP_IEEE
 define void @test_no_sdiv24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 7
   %den.i24.0 = shl i32 %den, 8
   %num.i24 = ashr i32 %num.i24.0, 7
@@ -131,9 +131,9 @@ define void @test_no_sdiv24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in)
 ; EG-DAG: RECIP_IEEE
 ; EG: FLT_TO_INT
 define void @srem24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
-  %den_ptr = getelementptr i8 addrspace(1)* %in, i8 1
-  %num = load i8 addrspace(1) * %in
-  %den = load i8 addrspace(1) * %den_ptr
+  %den_ptr = getelementptr i8, i8 addrspace(1)* %in, i8 1
+  %num = load i8, i8 addrspace(1) * %in
+  %den = load i8, i8 addrspace(1) * %den_ptr
   %result = srem i8 %num, %den
   store i8 %result, i8 addrspace(1)* %out
   ret void
@@ -150,9 +150,9 @@ define void @srem24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
 ; EG-DAG: RECIP_IEEE
 ; EG: FLT_TO_INT
 define void @srem24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
-  %den_ptr = getelementptr i16 addrspace(1)* %in, i16 1
-  %num = load i16 addrspace(1) * %in, align 2
-  %den = load i16 addrspace(1) * %den_ptr, align 2
+  %den_ptr = getelementptr i16, i16 addrspace(1)* %in, i16 1
+  %num = load i16, i16 addrspace(1) * %in, align 2
+  %den = load i16, i16 addrspace(1) * %den_ptr, align 2
   %result = srem i16 %num, %den
   store i16 %result, i16 addrspace(1)* %out, align 2
   ret void
@@ -169,9 +169,9 @@ define void @srem24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
 ; EG-DAG: RECIP_IEEE
 ; EG: FLT_TO_INT
 define void @srem24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 8
   %den.i24.0 = shl i32 %den, 8
   %num.i24 = ashr i32 %num.i24.0, 8
@@ -188,9 +188,9 @@ define void @srem24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 ; EG-NOT: INT_TO_FLT
 ; EG-NOT: RECIP_IEEE
 define void @srem25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 7
   %den.i24.0 = shl i32 %den, 7
   %num.i24 = ashr i32 %num.i24.0, 7
@@ -207,9 +207,9 @@ define void @srem25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 ; EG-NOT: INT_TO_FLT
 ; EG-NOT: RECIP_IEEE
 define void @test_no_srem24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 8
   %den.i24.0 = shl i32 %den, 7
   %num.i24 = ashr i32 %num.i24.0, 8
@@ -226,9 +226,9 @@ define void @test_no_srem24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in)
 ; EG-NOT: INT_TO_FLT
 ; EG-NOT: RECIP_IEEE
 define void @test_no_srem24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 7
   %den.i24.0 = shl i32 %den, 8
   %num.i24 = ashr i32 %num.i24.0, 7
diff --git a/test/CodeGen/R600/sdivrem64.ll b/test/CodeGen/R600/sdivrem64.ll
new file mode 100644
index 000000000000..a9b2b7f9df55
--- /dev/null
+++ b/test/CodeGen/R600/sdivrem64.ll
@@ -0,0 +1,225 @@
+;RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC %s
+;RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC %s
+;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
+
+;FUNC-LABEL: {{^}}test_sdiv:
+;EG: RECIP_UINT
+;EG: LSHL {{.*}}, 1,
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN: v_bfe_u32
+;GCN-NOT: v_mad_f32
+;SI-NOT: v_lshr_b64
+;VI-NOT: v_lshrrev_b64
+;GCN: s_endpgm
+define void @test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+  %result = sdiv i64 %x, %y
+  store i64 %result, i64 addrspace(1)* %out
+  ret void
+}
+
+;FUNC-LABEL: {{^}}test_srem:
+;EG: RECIP_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: BFE_UINT
+;EG: AND_INT {{.*}}, 1,
+
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN-NOT: v_mad_f32
+;SI-NOT: v_lshr_b64
+;VI-NOT: v_lshrrev_b64
+;GCN: s_endpgm
+define void @test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+  %result = urem i64 %x, %y
+  store i64 %result, i64 addrspace(1)* %out
+  ret void
+}
+
+;FUNC-LABEL: {{^}}test_sdiv3264:
+;EG: RECIP_UINT
+;EG-NOT: BFE_UINT
+
+;GCN-NOT: s_bfe_u32
+;GCN-NOT: v_mad_f32
+;SI-NOT: v_lshr_b64
+;VI-NOT: v_lshrrev_b64
+;GCN: s_endpgm
+define void @test_sdiv3264(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+  %1 = ashr i64 %x, 33
+  %2 = ashr i64 %y, 33
+  %result = sdiv i64 %1, %2
+  store i64 %result, i64 addrspace(1)* %out
+  ret void
+}
+
+;FUNC-LABEL: {{^}}test_srem3264:
+;EG: RECIP_UINT
+;EG-NOT: BFE_UINT
+
+;GCN-NOT: s_bfe_u32
+;GCN-NOT: v_mad_f32
+;SI-NOT: v_lshr_b64
+;VI-NOT: v_lshrrev_b64
+;GCN: s_endpgm
+define void @test_srem3264(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+  %1 = ashr i64 %x, 33
+  %2 = ashr i64 %y, 33
+  %result = srem i64 %1, %2
+  store i64 %result, i64 addrspace(1)* %out
+  ret void
+}
+
+;FUNC-LABEL: {{^}}test_sdiv2464:
+;EG: INT_TO_FLT
+;EG: INT_TO_FLT
+;EG: FLT_TO_INT
+;EG-NOT: RECIP_UINT
+;EG-NOT: BFE_UINT
+
+;GCN-NOT: s_bfe_u32
+;GCN: v_mad_f32
+;SI-NOT: v_lshr_b64
+;VI-NOT: v_lshrrev_b64
+;GCN: s_endpgm
+define void @test_sdiv2464(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+  %1 = ashr i64 %x, 40
+  %2 = ashr i64 %y, 40
+  %result = sdiv i64 %1, %2
+  store i64 %result, i64 addrspace(1)* %out
+  ret void
+}
+
+;FUNC-LABEL: {{^}}test_srem2464:
+;EG: INT_TO_FLT
+;EG: INT_TO_FLT
+;EG: FLT_TO_INT
+;EG-NOT: RECIP_UINT
+;EG-NOT: BFE_UINT
+
+;GCN-NOT: s_bfe_u32
+;GCN: v_mad_f32
+;SI-NOT: v_lshr_b64
+;VI-NOT: v_lshrrev_b64
+;GCN: s_endpgm
+define void @test_srem2464(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+  %1 = ashr i64 %x, 40
+  %2 = ashr i64 %y, 40
+  %result = srem i64 %1, %2
+  store i64 %result, i64 addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/select64.ll b/test/CodeGen/R600/select64.ll
index 3fd648139fe2..5cebb30dc72e 100644
--- a/test/CodeGen/R600/select64.ll
+++ b/test/CodeGen/R600/select64.ll
@@ -42,10 +42,27 @@ define void @select_trunc_i64_2(i32 addrspace(1)* %out, i32 %cond, i64 %a, i64 %
 ; CHECK-NOT: v_cndmask_b32
 define void @v_select_trunc_i64_2(i32 addrspace(1)* %out, i32 %cond, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
   %cmp = icmp ugt i32 %cond, 5
-  %a = load i64 addrspace(1)* %aptr, align 8
-  %b = load i64 addrspace(1)* %bptr, align 8
+  %a = load i64, i64 addrspace(1)* %aptr, align 8
+  %b = load i64, i64 addrspace(1)* %bptr, align 8
   %sel = select i1 %cmp, i64 %a, i64 %b
   %trunc = trunc i64 %sel to i32
   store i32 %trunc, i32 addrspace(1)* %out, align 4
   ret void
 }
+
+; CHECK-LABEL: {{^}}v_select_i64_split_imm:
+; CHECK: s_mov_b32 [[SHI:s[0-9]+]], 63
+; CHECK: s_mov_b32 [[SLO:s[0-9]+]], 0
+; CHECK-DAG: v_mov_b32_e32 [[VHI:v[0-9]+]], [[SHI]]
+; CHECK-DAG: v_mov_b32_e32 [[VLO:v[0-9]+]], [[SLO]]
+; CHECK-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, [[VLO]], {{v[0-9]+}}
+; CHECK-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, [[VHI]], {{v[0-9]+}}
+; CHECK: s_endpgm
+define void @v_select_i64_split_imm(i64 addrspace(1)* %out, i32 %cond, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
+  %cmp = icmp ugt i32 %cond, 5
+  %a = load i64, i64 addrspace(1)* %aptr, align 8
+  %b = load i64, i64 addrspace(1)* %bptr, align 8
+  %sel = select i1 %cmp, i64 %a, i64 270582939648 ; 63 << 32
+  store i64 %sel, i64 addrspace(1)* %out, align 8
+  ret void
+}
diff --git a/test/CodeGen/R600/selectcc-cnd.ll b/test/CodeGen/R600/selectcc-cnd.ll
index 0bfca6937488..94d0ace75697 100644
--- a/test/CodeGen/R600/selectcc-cnd.ll
+++ b/test/CodeGen/R600/selectcc-cnd.ll
@@ -4,7 +4,7 @@
 ;CHECK: CNDE {{\*?}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1.0, literal.x,
 ;CHECK: 1073741824
 define void @test(float addrspace(1)* %out, float addrspace(1)* %in) {
-  %1 = load float addrspace(1)* %in
+  %1 = load float, float addrspace(1)* %in
   %2 = fcmp oeq float %1, 0.0
   %3 = select i1 %2, float 1.0, float 2.0
   store float %3, float addrspace(1)* %out
diff --git a/test/CodeGen/R600/selectcc-cnde-int.ll b/test/CodeGen/R600/selectcc-cnde-int.ll
index d568888f7cb2..58a4ee7d62b2 100644
--- a/test/CodeGen/R600/selectcc-cnde-int.ll
+++ b/test/CodeGen/R600/selectcc-cnde-int.ll
@@ -4,7 +4,7 @@
 ;CHECK: CNDE_INT {{\*?}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, literal.x,
 ;CHECK-NEXT: 2
 define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %1 = load i32 addrspace(1)* %in
+  %1 = load i32, i32 addrspace(1)* %in
   %2 = icmp eq i32 %1, 0
   %3 = select i1 %2, i32 1, i32 2
   store i32 %3, i32 addrspace(1)* %out
diff --git a/test/CodeGen/R600/selectcc-icmp-select-float.ll b/test/CodeGen/R600/selectcc-icmp-select-float.ll
index 6743800490b3..e870ee891e66 100644
--- a/test/CodeGen/R600/selectcc-icmp-select-float.ll
+++ b/test/CodeGen/R600/selectcc-icmp-select-float.ll
@@ -8,7 +8,7 @@
 
 define void @test(float addrspace(1)* %out, i32 addrspace(1)* %in) {
 entry:
-  %0 = load i32 addrspace(1)* %in
+  %0 = load i32, i32 addrspace(1)* %in
   %1 = icmp sge i32 %0, 0
   %2 = select i1 %1, float 1.0, float 0.0
   store float %2, float addrspace(1)* %out
diff --git a/test/CodeGen/R600/selectcc-opt.ll b/test/CodeGen/R600/selectcc-opt.ll
index 7780371329ce..65be4a626a18 100644
--- a/test/CodeGen/R600/selectcc-opt.ll
+++ b/test/CodeGen/R600/selectcc-opt.ll
@@ -19,7 +19,7 @@ entry:
   br i1 %6, label %IF, label %ENDIF
 
 IF:
-  %7 = getelementptr i32 addrspace(1)* %out, i32 1
+  %7 = getelementptr i32, i32 addrspace(1)* %out, i32 1
   store i32 0, i32 addrspace(1)* %7
   br label %ENDIF
 
@@ -47,7 +47,7 @@ entry:
   br i1 %6, label %ENDIF, label %IF
 
 IF:
-  %7 = getelementptr i32 addrspace(1)* %out, i32 1
+  %7 = getelementptr i32, i32 addrspace(1)* %out, i32 1
   store i32 0, i32 addrspace(1)* %7
   br label %ENDIF
 
diff --git a/test/CodeGen/R600/setcc-opt.ll b/test/CodeGen/R600/setcc-opt.ll
index a44c89f72cf5..4e6a10d6b78d 100644
--- a/test/CodeGen/R600/setcc-opt.ll
+++ b/test/CodeGen/R600/setcc-opt.ll
@@ -1,12 +1,13 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
 ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 
 ; FUNC-LABEL: {{^}}sext_bool_icmp_eq_0:
-; SI-NOT: v_cmp
-; SI: v_cmp_ne_i32_e32 vcc,
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
-; SI-NEXT:buffer_store_byte [[RESULT]]
-; SI-NEXT: s_endpgm
+; GCN-NOT: v_cmp
+; GCN: v_cmp_ne_i32_e32 vcc,
+; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
+; GCN-NEXT:buffer_store_byte [[RESULT]]
+; GCN-NEXT: s_endpgm
 
 ; EG: SETNE_INT * [[CMP:T[0-9]+]].[[CMPCHAN:[XYZW]]], KC0[2].Z, KC0[2].W
 ; EG: AND_INT T{{[0-9]+.[XYZW]}}, PS, 1
@@ -19,11 +20,11 @@ define void @sext_bool_icmp_eq_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind
 }
 
 ; FUNC-LABEL: {{^}}sext_bool_icmp_ne_0:
-; SI-NOT: v_cmp
-; SI: v_cmp_ne_i32_e32 vcc,
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
-; SI-NEXT: buffer_store_byte [[RESULT]]
-; SI-NEXT: s_endpgm
+; GCN-NOT: v_cmp
+; GCN: v_cmp_ne_i32_e32 vcc,
+; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
+; GCN-NEXT: buffer_store_byte [[RESULT]]
+; GCN-NEXT: s_endpgm
 
 ; EG: SETNE_INT * [[CMP:T[0-9]+]].[[CMPCHAN:[XYZW]]], KC0[2].Z, KC0[2].W
 ; EG: AND_INT T{{[0-9]+.[XYZW]}}, PS, 1
@@ -37,12 +38,12 @@ define void @sext_bool_icmp_ne_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind
 
 ; This really folds away to false
 ; FUNC-LABEL: {{^}}sext_bool_icmp_eq_1:
-; SI: v_cmp_eq_i32_e32 vcc,
-; SI-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, -1, vcc
-; SI-NEXT: v_cmp_eq_i32_e64 {{s\[[0-9]+:[0-9]+\]}}, [[TMP]], 1{{$}}
-; SI-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, 1,
-; SI-NEXT: buffer_store_byte [[TMP]]
-; SI-NEXT: s_endpgm
+; GCN: v_cmp_eq_i32_e32 vcc,
+; GCN-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_i32_e32 vcc, 1, [[TMP]]{{$}}
+; GCN-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, 1,
+; GCN-NEXT: buffer_store_byte [[TMP]]
+; GCN-NEXT: s_endpgm
 define void @sext_bool_icmp_eq_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
   %icmp0 = icmp eq i32 %a, %b
   %ext = sext i1 %icmp0 to i32
@@ -53,12 +54,12 @@ define void @sext_bool_icmp_eq_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind
 
 ; This really folds away to true
 ; FUNC-LABEL: {{^}}sext_bool_icmp_ne_1:
-; SI: v_cmp_ne_i32_e32 vcc,
-; SI-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, -1, vcc
-; SI-NEXT: v_cmp_ne_i32_e64 {{s\[[0-9]+:[0-9]+\]}}, [[TMP]], 1{{$}}
-; SI-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, 1,
-; SI-NEXT: buffer_store_byte [[TMP]]
-; SI-NEXT: s_endpgm
+; GCN: v_cmp_ne_i32_e32 vcc,
+; GCN-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, -1, vcc
+; GCN-NEXT: v_cmp_ne_i32_e32 vcc, 1, [[TMP]]{{$}}
+; GCN-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, 1,
+; GCN-NEXT: buffer_store_byte [[TMP]]
+; GCN-NEXT: s_endpgm
 define void @sext_bool_icmp_ne_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
   %icmp0 = icmp ne i32 %a, %b
   %ext = sext i1 %icmp0 to i32
@@ -68,11 +69,11 @@ define void @sext_bool_icmp_ne_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind
 }
 
 ; FUNC-LABEL: {{^}}zext_bool_icmp_eq_0:
-; SI-NOT: v_cmp
-; SI: v_cmp_ne_i32_e32 vcc,
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
-; SI-NEXT: buffer_store_byte [[RESULT]]
-; SI-NEXT: s_endpgm
+; GCN-NOT: v_cmp
+; GCN: v_cmp_ne_i32_e32 vcc,
+; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
+; GCN-NEXT: buffer_store_byte [[RESULT]]
+; GCN-NEXT: s_endpgm
 define void @zext_bool_icmp_eq_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
   %icmp0 = icmp eq i32 %a, %b
   %ext = zext i1 %icmp0 to i32
@@ -82,11 +83,11 @@ define void @zext_bool_icmp_eq_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind
 }
 
 ; FUNC-LABEL: {{^}}zext_bool_icmp_ne_0:
-; SI-NOT: v_cmp
-; SI: v_cmp_ne_i32_e32 vcc,
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
-; SI-NEXT: buffer_store_byte [[RESULT]]
-; SI-NEXT: s_endpgm
+; GCN-NOT: v_cmp
+; GCN: v_cmp_ne_i32_e32 vcc,
+; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
+; GCN-NEXT: buffer_store_byte [[RESULT]]
+; GCN-NEXT: s_endpgm
 define void @zext_bool_icmp_ne_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
   %icmp0 = icmp ne i32 %a, %b
   %ext = zext i1 %icmp0 to i32
@@ -96,11 +97,11 @@ define void @zext_bool_icmp_ne_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind
 }
 
 ; FUNC-LABEL: {{^}}zext_bool_icmp_eq_1:
-; SI-NOT: v_cmp
-; SI: v_cmp_eq_i32_e32 vcc,
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
-; SI-NEXT: buffer_store_byte [[RESULT]]
-; SI-NEXT: s_endpgm
+; GCN-NOT: v_cmp
+; GCN: v_cmp_eq_i32_e32 vcc,
+; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
+; GCN-NEXT: buffer_store_byte [[RESULT]]
+; GCN-NEXT: s_endpgm
 define void @zext_bool_icmp_eq_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
   %icmp0 = icmp eq i32 %a, %b
   %ext = zext i1 %icmp0 to i32
@@ -110,10 +111,10 @@ define void @zext_bool_icmp_eq_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind
 }
 
 ; FUNC-LABEL: {{^}}zext_bool_icmp_ne_1:
-; SI-NOT: v_cmp
-; SI: v_cmp_eq_i32_e32 vcc,
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
-; SI-NEXT: buffer_store_byte [[RESULT]]
+; GCN-NOT: v_cmp
+; GCN: v_cmp_eq_i32_e32 vcc,
+; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
+; GCN-NEXT: buffer_store_byte [[RESULT]]
 define void @zext_bool_icmp_ne_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
   %icmp0 = icmp ne i32 %a, %b
   %ext = zext i1 %icmp0 to i32
@@ -125,11 +126,13 @@ define void @zext_bool_icmp_ne_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind
 ; FUNC-LABEL: {{^}}sext_bool_icmp_ne_k:
 ; SI-DAG: s_load_dword [[A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
 ; SI-DAG: s_load_dword [[B:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]]
-; SI: v_cmp_ne_i32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[VB]], 2{{$}}
-; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CMP]]
-; SI: buffer_store_byte
-; SI: s_endpgm
+; VI-DAG: s_load_dword [[A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; VI-DAG: s_load_dword [[B:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
+; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]]
+; GCN: v_cmp_ne_i32_e32 vcc, 2, [[VB]]{{$}}
+; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
+; GCN: buffer_store_byte
+; GCN: s_endpgm
 define void @sext_bool_icmp_ne_k(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
   %icmp0 = icmp ne i32 %a, %b
   %ext = sext i1 %icmp0 to i32
@@ -139,12 +142,12 @@ define void @sext_bool_icmp_ne_k(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind
 }
 
 ; FUNC-LABEL: {{^}}cmp_zext_k_i8max:
-; SI: buffer_load_ubyte [[B:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:44
-; SI: v_mov_b32_e32 [[K255:v[0-9]+]], 0xff{{$}}
-; SI: v_cmp_ne_i32_e32 vcc, [[B]], [[K255]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
-; SI-NEXT: buffer_store_byte [[RESULT]]
-; SI: s_endpgm
+; GCN: buffer_load_ubyte [[B:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:44
+; GCN: v_mov_b32_e32 [[K255:v[0-9]+]], 0xff{{$}}
+; GCN: v_cmp_ne_i32_e32 vcc, [[K255]], [[B]]
+; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
+; GCN-NEXT: buffer_store_byte [[RESULT]]
+; GCN: s_endpgm
 define void @cmp_zext_k_i8max(i1 addrspace(1)* %out, i8 %b) nounwind {
   %b.ext = zext i8 %b to i32
   %icmp0 = icmp ne i32 %b.ext, 255
@@ -153,13 +156,13 @@ define void @cmp_zext_k_i8max(i1 addrspace(1)* %out, i8 %b) nounwind {
 }
 
 ; FUNC-LABEL: {{^}}cmp_sext_k_neg1:
-; SI: buffer_load_sbyte [[B:v[0-9]+]]
-; SI: v_cmp_ne_i32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[B]], -1{{$}}
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CMP]]
-; SI-NEXT: buffer_store_byte [[RESULT]]
-; SI: s_endpgm
+; GCN: buffer_load_sbyte [[B:v[0-9]+]]
+; GCN: v_cmp_ne_i32_e32 vcc, -1, [[B]]{{$}}
+; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
+; GCN-NEXT: buffer_store_byte [[RESULT]]
+; GCN: s_endpgm
 define void @cmp_sext_k_neg1(i1 addrspace(1)* %out, i8 addrspace(1)* %b.ptr) nounwind {
-  %b = load i8 addrspace(1)* %b.ptr
+  %b = load i8, i8 addrspace(1)* %b.ptr
   %b.ext = sext i8 %b to i32
   %icmp0 = icmp ne i32 %b.ext, -1
   store i1 %icmp0, i1 addrspace(1)* %out
@@ -167,11 +170,11 @@ define void @cmp_sext_k_neg1(i1 addrspace(1)* %out, i8 addrspace(1)* %b.ptr) nou
 }
 
 ; FUNC-LABEL: {{^}}cmp_sext_k_neg1_i8_sext_arg:
-; SI: s_load_dword [[B:s[0-9]+]]
-; SI: v_cmp_ne_i32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[B]], -1{{$}}
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CMP]]
-; SI-NEXT: buffer_store_byte [[RESULT]]
-; SI: s_endpgm
+; GCN: s_load_dword [[B:s[0-9]+]]
+; GCN: v_cmp_ne_i32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -1, [[B]]
+; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CMP]]
+; GCN-NEXT: buffer_store_byte [[RESULT]]
+; GCN: s_endpgm
 define void @cmp_sext_k_neg1_i8_sext_arg(i1 addrspace(1)* %out, i8 signext %b) nounwind {
   %b.ext = sext i8 %b to i32
   %icmp0 = icmp ne i32 %b.ext, -1
@@ -184,12 +187,12 @@ define void @cmp_sext_k_neg1_i8_sext_arg(i1 addrspace(1)* %out, i8 signext %b) n
 ; Should do a buffer_load_sbyte and compare with -1
 
 ; FUNC-LABEL: {{^}}cmp_sext_k_neg1_i8_arg:
-; SI-DAG: buffer_load_ubyte [[B:v[0-9]+]]
-; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0xff{{$}}
-; SI: v_cmp_ne_i32_e32 vcc, [[B]], [[K]]{{$}}
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
-; SI-NEXT: buffer_store_byte [[RESULT]]
-; SI: s_endpgm
+; GCN-DAG: buffer_load_ubyte [[B:v[0-9]+]]
+; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0xff{{$}}
+; GCN: v_cmp_ne_i32_e32 vcc, [[K]], [[B]]{{$}}
+; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
+; GCN-NEXT: buffer_store_byte [[RESULT]]
+; GCN: s_endpgm
 define void @cmp_sext_k_neg1_i8_arg(i1 addrspace(1)* %out, i8 %b) nounwind {
   %b.ext = sext i8 %b to i32
   %icmp0 = icmp ne i32 %b.ext, -1
@@ -198,9 +201,9 @@ define void @cmp_sext_k_neg1_i8_arg(i1 addrspace(1)* %out, i8 %b) nounwind {
 }
 
 ; FUNC-LABEL: {{^}}cmp_zext_k_neg1:
-; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 1{{$}}
-; SI-NEXT: buffer_store_byte [[RESULT]]
-; SI: s_endpgm
+; GCN: v_mov_b32_e32 [[RESULT:v[0-9]+]], 1{{$}}
+; GCN: buffer_store_byte [[RESULT]]
+; GCN: s_endpgm
 define void @cmp_zext_k_neg1(i1 addrspace(1)* %out, i8 %b) nounwind {
   %b.ext = zext i8 %b to i32
   %icmp0 = icmp ne i32 %b.ext, -1
@@ -209,9 +212,9 @@ define void @cmp_zext_k_neg1(i1 addrspace(1)* %out, i8 %b) nounwind {
 }
 
 ; FUNC-LABEL: {{^}}zext_bool_icmp_ne_k:
-; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 1{{$}}
-; SI-NEXT: buffer_store_byte [[RESULT]]
-; SI-NEXT: s_endpgm
+; GCN: v_mov_b32_e32 [[RESULT:v[0-9]+]], 1{{$}}
+; GCN: buffer_store_byte [[RESULT]]
+; GCN-NEXT: s_endpgm
 define void @zext_bool_icmp_ne_k(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
   %icmp0 = icmp ne i32 %a, %b
   %ext = zext i1 %icmp0 to i32
@@ -221,9 +224,9 @@ define void @zext_bool_icmp_ne_k(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind
 }
 
 ; FUNC-LABEL: {{^}}zext_bool_icmp_eq_k:
-; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
-; SI-NEXT: buffer_store_byte [[RESULT]]
-; SI-NEXT: s_endpgm
+; GCN: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
+; GCN: buffer_store_byte [[RESULT]]
+; GCN-NEXT: s_endpgm
 define void @zext_bool_icmp_eq_k(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
   %icmp0 = icmp ne i32 %a, %b
   %ext = zext i1 %icmp0 to i32
diff --git a/test/CodeGen/R600/setcc.ll b/test/CodeGen/R600/setcc.ll
index f9c7e4f36128..f33a82df5ffb 100644
--- a/test/CodeGen/R600/setcc.ll
+++ b/test/CodeGen/R600/setcc.ll
@@ -21,9 +21,9 @@ define void @setcc_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %
 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
 define void @setcc_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
-  %a = load <4 x i32> addrspace(1) * %in
-  %b = load <4 x i32> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
+  %a = load <4 x i32>, <4 x i32> addrspace(1) * %in
+  %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
   %result = icmp eq <4 x i32> %a, %b
   %sext = sext <4 x i1> %result to <4 x i32>
   store <4 x i32> %sext, <4 x i32> addrspace(1)* %out
@@ -344,11 +344,11 @@ entry:
 ; SI: s_endpgm
 define void @v3i32_eq(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(1)* %ptra, <3 x i32> addrspace(1)* %ptrb) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.a = getelementptr <3 x i32> addrspace(1)* %ptra, i32 %tid
-  %gep.b = getelementptr <3 x i32> addrspace(1)* %ptrb, i32 %tid
-  %gep.out = getelementptr <3 x i32> addrspace(1)* %out, i32 %tid
-  %a = load <3 x i32> addrspace(1)* %gep.a
-  %b = load <3 x i32> addrspace(1)* %gep.b
+  %gep.a = getelementptr <3 x i32>, <3 x i32> addrspace(1)* %ptra, i32 %tid
+  %gep.b = getelementptr <3 x i32>, <3 x i32> addrspace(1)* %ptrb, i32 %tid
+  %gep.out = getelementptr <3 x i32>, <3 x i32> addrspace(1)* %out, i32 %tid
+  %a = load <3 x i32>, <3 x i32> addrspace(1)* %gep.a
+  %b = load <3 x i32>, <3 x i32> addrspace(1)* %gep.b
   %cmp = icmp eq <3 x i32> %a, %b
   %ext = sext <3 x i1> %cmp to <3 x i32>
   store <3 x i32> %ext, <3 x i32> addrspace(1)* %gep.out
@@ -365,11 +365,11 @@ define void @v3i32_eq(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(1)* %ptr
 ; SI: s_endpgm
 define void @v3i8_eq(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %ptra, <3 x i8> addrspace(1)* %ptrb) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep.a = getelementptr <3 x i8> addrspace(1)* %ptra, i32 %tid
-  %gep.b = getelementptr <3 x i8> addrspace(1)* %ptrb, i32 %tid
-  %gep.out = getelementptr <3 x i8> addrspace(1)* %out, i32 %tid
-  %a = load <3 x i8> addrspace(1)* %gep.a
-  %b = load <3 x i8> addrspace(1)* %gep.b
+  %gep.a = getelementptr <3 x i8>, <3 x i8> addrspace(1)* %ptra, i32 %tid
+  %gep.b = getelementptr <3 x i8>, <3 x i8> addrspace(1)* %ptrb, i32 %tid
+  %gep.out = getelementptr <3 x i8>, <3 x i8> addrspace(1)* %out, i32 %tid
+  %a = load <3 x i8>, <3 x i8> addrspace(1)* %gep.a
+  %b = load <3 x i8>, <3 x i8> addrspace(1)* %gep.b
   %cmp = icmp eq <3 x i8> %a, %b
   %ext = sext <3 x i1> %cmp to <3 x i8>
   store <3 x i8> %ext, <3 x i8> addrspace(1)* %gep.out
diff --git a/test/CodeGen/R600/sext-in-reg.ll b/test/CodeGen/R600/sext-in-reg.ll
index 3260179921f9..d9ad4935968d 100644
--- a/test/CodeGen/R600/sext-in-reg.ll
+++ b/test/CodeGen/R600/sext-in-reg.ll
@@ -187,11 +187,11 @@ define void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) noun
 ; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
 define void @v_sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x()
-  %a.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid
-  %b.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid
-  %out.gep = getelementptr i64 addrspace(1)* %out, i32 %tid
-  %a = load i64 addrspace(1)* %a.gep, align 8
-  %b = load i64 addrspace(1)* %b.gep, align 8
+  %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+  %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+  %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
+  %a = load i64, i64 addrspace(1)* %a.gep, align 8
+  %b = load i64, i64 addrspace(1)* %b.gep, align 8
 
   %c = shl i64 %a, %b
   %shl = shl i64 %c, 63
@@ -208,11 +208,11 @@ define void @v_sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %
 ; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
 define void @v_sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x()
-  %a.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid
-  %b.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid
-  %out.gep = getelementptr i64 addrspace(1)* %out, i32 %tid
-  %a = load i64 addrspace(1)* %a.gep, align 8
-  %b = load i64 addrspace(1)* %b.gep, align 8
+  %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+  %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+  %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
+  %a = load i64, i64 addrspace(1)* %a.gep, align 8
+  %b = load i64, i64 addrspace(1)* %b.gep, align 8
 
   %c = shl i64 %a, %b
   %shl = shl i64 %c, 56
@@ -229,11 +229,11 @@ define void @v_sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %
 ; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
 define void @v_sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x()
-  %a.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid
-  %b.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid
-  %out.gep = getelementptr i64 addrspace(1)* %out, i32 %tid
-  %a = load i64 addrspace(1)* %a.gep, align 8
-  %b = load i64 addrspace(1)* %b.gep, align 8
+  %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+  %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+  %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
+  %a = load i64, i64 addrspace(1)* %a.gep, align 8
+  %b = load i64, i64 addrspace(1)* %b.gep, align 8
 
   %c = shl i64 %a, %b
   %shl = shl i64 %c, 48
@@ -249,11 +249,11 @@ define void @v_sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)*
 ; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[SHR]]{{\]}}
 define void @v_sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x()
-  %a.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid
-  %b.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid
-  %out.gep = getelementptr i64 addrspace(1)* %out, i32 %tid
-  %a = load i64 addrspace(1)* %a.gep, align 8
-  %b = load i64 addrspace(1)* %b.gep, align 8
+  %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+  %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+  %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
+  %a = load i64, i64 addrspace(1)* %a.gep, align 8
+  %b = load i64, i64 addrspace(1)* %b.gep, align 8
 
   %c = shl i64 %a, %b
   %shl = shl i64 %c, 32
@@ -263,9 +263,9 @@ define void @v_sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)*
 }
 
 ; FUNC-LABEL: {{^}}sext_in_reg_i1_in_i32_other_amount:
-; SI-NOT: {{[^@]}}bfe
-; SI: s_lshl_b32 [[REG:s[0-9]+]], {{s[0-9]+}}, 6
-; SI: s_ashr_i32 {{s[0-9]+}}, [[REG]], 7
+; SI-NOT: s_lshl
+; SI-NOT: s_ashr
+; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001
 
 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
 ; EG-NOT: BFE
@@ -282,10 +282,10 @@ define void @sext_in_reg_i1_in_i32_other_amount(i32 addrspace(1)* %out, i32 %a,
 }
 
 ; FUNC-LABEL: {{^}}sext_in_reg_v2i1_in_v2i32_other_amount:
-; SI-DAG: s_lshl_b32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6
-; SI-DAG: s_ashr_i32 {{s[0-9]+}}, [[REG0]], 7
-; SI-DAG: s_lshl_b32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6
-; SI-DAG: s_ashr_i32 {{s[0-9]+}}, [[REG1]], 7
+; SI-NOT: s_lshl
+; SI-NOT: s_ashr
+; SI-DAG: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001
+; SI-DAG: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001
 ; SI: s_endpgm
 
 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
@@ -428,8 +428,8 @@ define void @testcase_3(i8 addrspace(1)* %out, i8 %a) nounwind {
 ; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
 ; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
 define void @vgpr_sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) nounwind {
-  %loada = load <4 x i32> addrspace(1)* %a, align 16
-  %loadb = load <4 x i32> addrspace(1)* %b, align 16
+  %loada = load <4 x i32>, <4 x i32> addrspace(1)* %a, align 16
+  %loadb = load <4 x i32>, <4 x i32> addrspace(1)* %b, align 16
   %c = add <4 x i32> %loada, %loadb ; add to prevent folding into extload
   %shl = shl <4 x i32> %c, <i32 24, i32 24, i32 24, i32 24>
   %ashr = ashr <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
@@ -441,8 +441,8 @@ define void @vgpr_sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i
 ; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16
 ; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16
 define void @vgpr_sext_in_reg_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) nounwind {
-  %loada = load <4 x i32> addrspace(1)* %a, align 16
-  %loadb = load <4 x i32> addrspace(1)* %b, align 16
+  %loada = load <4 x i32>, <4 x i32> addrspace(1)* %a, align 16
+  %loadb = load <4 x i32>, <4 x i32> addrspace(1)* %b, align 16
   %c = add <4 x i32> %loada, %loadb ; add to prevent folding into extload
   %shl = shl <4 x i32> %c, <i32 16, i32 16, i32 16, i32 16>
   %ashr = ashr <4 x i32> %shl, <i32 16, i32 16, i32 16, i32 16>
@@ -459,7 +459,7 @@ define void @vgpr_sext_in_reg_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x
 ; SI: v_bfe_i32
 ; SI: buffer_store_short
 define void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind {
-  %tmp5 = load i8 addrspace(1)* %src, align 1
+  %tmp5 = load i8, i8 addrspace(1)* %src, align 1
   %tmp2 = sext i8 %tmp5 to i32
   %tmp3 = tail call i32 @llvm.AMDGPU.imax(i32 %tmp2, i32 0) nounwind readnone
   %tmp4 = trunc i32 %tmp3 to i8
@@ -474,7 +474,7 @@ declare i32 @llvm.AMDGPU.bfe.i32(i32, i32, i32) nounwind readnone
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_0_width(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwind {
-  %load = load i32 addrspace(1)* %ptr, align 4
+  %load = load i32, i32 addrspace(1)* %ptr, align 4
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 8, i32 0) nounwind readnone
   store i32 %bfe, i32 addrspace(1)* %out, align 4
   ret void
@@ -485,7 +485,7 @@ define void @bfe_0_width(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwin
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_8_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwind {
-  %load = load i32 addrspace(1)* %ptr, align 4
+  %load = load i32, i32 addrspace(1)* %ptr, align 4
   %bfe0 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 0, i32 8) nounwind readnone
   %bfe1 = call i32 @llvm.AMDGPU.bfe.i32(i32 %bfe0, i32 0, i32 8) nounwind readnone
   store i32 %bfe1, i32 addrspace(1)* %out, align 4
@@ -496,7 +496,7 @@ define void @bfe_8_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwin
 ; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8
 ; SI: s_endpgm
 define void @bfe_8_bfe_16(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwind {
-  %load = load i32 addrspace(1)* %ptr, align 4
+  %load = load i32, i32 addrspace(1)* %ptr, align 4
   %bfe0 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 0, i32 8) nounwind readnone
   %bfe1 = call i32 @llvm.AMDGPU.bfe.i32(i32 %bfe0, i32 0, i32 16) nounwind readnone
   store i32 %bfe1, i32 addrspace(1)* %out, align 4
@@ -509,7 +509,7 @@ define void @bfe_8_bfe_16(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwi
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @bfe_16_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwind {
-  %load = load i32 addrspace(1)* %ptr, align 4
+  %load = load i32, i32 addrspace(1)* %ptr, align 4
   %bfe0 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 0, i32 16) nounwind readnone
   %bfe1 = call i32 @llvm.AMDGPU.bfe.i32(i32 %bfe0, i32 0, i32 8) nounwind readnone
   store i32 %bfe1, i32 addrspace(1)* %out, align 4
@@ -545,7 +545,7 @@ define void @sext_in_reg_i8_to_i32_bfe_wrong(i32 addrspace(1)* %out, i32 %a, i32
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @sextload_i8_to_i32_bfe(i32 addrspace(1)* %out, i8 addrspace(1)* %ptr) nounwind {
-  %load = load i8 addrspace(1)* %ptr, align 1
+  %load = load i8, i8 addrspace(1)* %ptr, align 1
   %sext = sext i8 %load to i32
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %sext, i32 0, i32 8) nounwind readnone
   %shl = shl i32 %bfe, 24
@@ -554,12 +554,12 @@ define void @sextload_i8_to_i32_bfe(i32 addrspace(1)* %out, i8 addrspace(1)* %pt
   ret void
 }
 
-; FUNC-LABEL: {{^}}sextload_i8_to_i32_bfe_0:
 ; SI: .text
+; FUNC-LABEL: {{^}}sextload_i8_to_i32_bfe_0:{{.*$}}
 ; SI-NOT: {{[^@]}}bfe
 ; SI: s_endpgm
 define void @sextload_i8_to_i32_bfe_0(i32 addrspace(1)* %out, i8 addrspace(1)* %ptr) nounwind {
-  %load = load i8 addrspace(1)* %ptr, align 1
+  %load = load i8, i8 addrspace(1)* %ptr, align 1
   %sext = sext i8 %load to i32
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %sext, i32 8, i32 0) nounwind readnone
   %shl = shl i32 %bfe, 24
@@ -574,7 +574,7 @@ define void @sextload_i8_to_i32_bfe_0(i32 addrspace(1)* %out, i8 addrspace(1)* %
 ; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1
 ; SI: s_endpgm
 define void @sext_in_reg_i1_bfe_offset_0(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = shl i32 %x, 31
   %shr = ashr i32 %shl, 31
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shr, i32 0, i32 1)
@@ -589,7 +589,7 @@ define void @sext_in_reg_i1_bfe_offset_0(i32 addrspace(1)* %out, i32 addrspace(1
 ; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 1
 ; SI: s_endpgm
 define void @sext_in_reg_i1_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = shl i32 %x, 30
   %shr = ashr i32 %shl, 30
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shr, i32 1, i32 1)
@@ -599,12 +599,13 @@ define void @sext_in_reg_i1_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1
 
 ; FUNC-LABEL: {{^}}sext_in_reg_i2_bfe_offset_1:
 ; SI: buffer_load_dword
-; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 30, v{{[0-9]+}}
-; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 30, v{{[0-9]+}}
+; SI-NOT: v_lshl
+; SI-NOT: v_ashr
+; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 2
 ; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 2
 ; SI: s_endpgm
 define void @sext_in_reg_i2_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %x = load i32 addrspace(1)* %in, align 4
+  %x = load i32, i32 addrspace(1)* %in, align 4
   %shl = shl i32 %x, 30
   %shr = ashr i32 %shl, 30
   %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shr, i32 1, i32 2)
diff --git a/test/CodeGen/R600/sgpr-control-flow.ll b/test/CodeGen/R600/sgpr-control-flow.ll
index f0236acc6daa..38289ced632a 100644
--- a/test/CodeGen/R600/sgpr-control-flow.ll
+++ b/test/CodeGen/R600/sgpr-control-flow.ll
@@ -64,15 +64,15 @@ endif:
 
 ; SI-LABEL: {{^}}sgpr_if_else_valu_cmp_phi_br:
 ; SI: buffer_load_dword [[AVAL:v[0-9]+]]
-; SI: v_cmp_lt_i32_e64 [[CMP_IF:s\[[0-9]+:[0-9]+\]]], [[AVAL]], 0
+; SI: v_cmp_gt_i32_e32 [[CMP_IF:vcc]], 0, [[AVAL]]
 ; SI: v_cndmask_b32_e64 [[V_CMP:v[0-9]+]], 0, -1, [[CMP_IF]]
 
 ; SI: BB2_1:
 ; SI: buffer_load_dword [[AVAL:v[0-9]+]]
-; SI: v_cmp_eq_i32_e64 [[CMP_ELSE:s\[[0-9]+:[0-9]+\]]], [[AVAL]], 0
+; SI: v_cmp_eq_i32_e32 [[CMP_ELSE:vcc]], 0, [[AVAL]]
 ; SI: v_cndmask_b32_e64 [[V_CMP]], 0, -1, [[CMP_ELSE]]
 
-; SI: v_cmp_ne_i32_e64 [[CMP_CMP:s\[[0-9]+:[0-9]+\]]], [[V_CMP]], 0
+; SI: v_cmp_ne_i32_e32 [[CMP_CMP:vcc]], 0, [[V_CMP]]
 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP_CMP]]
 ; SI: buffer_store_dword [[RESULT]]
 define void @sgpr_if_else_valu_cmp_phi_br(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
@@ -82,14 +82,14 @@ entry:
   br i1 %tmp1, label %if, label %else
 
 if:
-  %gep.if = getelementptr i32 addrspace(1)* %a, i32 %tid
-  %a.val = load i32 addrspace(1)* %gep.if
+  %gep.if = getelementptr i32, i32 addrspace(1)* %a, i32 %tid
+  %a.val = load i32, i32 addrspace(1)* %gep.if
   %cmp.if = icmp eq i32 %a.val, 0
   br label %endif
 
 else:
-  %gep.else = getelementptr i32 addrspace(1)* %b, i32 %tid
-  %b.val = load i32 addrspace(1)* %gep.else
+  %gep.else = getelementptr i32, i32 addrspace(1)* %b, i32 %tid
+  %b.val = load i32, i32 addrspace(1)* %gep.else
   %cmp.else = icmp slt i32 %b.val, 0
   br label %endif
 
diff --git a/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll b/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll
index 893f5a3c50db..df67fcca22fe 100644
--- a/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll
+++ b/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll
@@ -7,7 +7,7 @@
 ; SI-LABEL: {{^}}test_dup_operands:
 ; SI: v_add_i32_e32
 define void @test_dup_operands(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %in) {
-  %a = load <2 x i32> addrspace(1)* %in
+  %a = load <2 x i32>, <2 x i32> addrspace(1)* %in
   %lo = extractelement <2 x i32> %a, i32 0
   %hi = extractelement <2 x i32> %a, i32 1
   %add = add i32 %lo, %lo
diff --git a/test/CodeGen/R600/sgpr-copy.ll b/test/CodeGen/R600/sgpr-copy.ll
index 57cbadd9239d..b849c4038bc7 100644
--- a/test/CodeGen/R600/sgpr-copy.ll
+++ b/test/CodeGen/R600/sgpr-copy.ll
@@ -9,8 +9,8 @@
 
 define void @phi1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
 main_body:
-  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
-  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !1
+  %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
+  %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20, !tbaa !1
   %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
   %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
   %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
@@ -33,8 +33,8 @@ ENDIF:                                            ; preds = %main_body, %ELSE
 ; CHECK-LABEL: {{^}}phi2:
 define void @phi2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
 main_body:
-  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
-  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !1
+  %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
+  %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20, !tbaa !1
   %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
   %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
   %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
@@ -50,10 +50,10 @@ main_body:
   %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 84)
   %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 88)
   %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 92)
-  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
-  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !1
-  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
-  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !1
+  %37 = getelementptr <32 x i8>, <32 x i8> addrspace(2)* %2, i32 0
+  %38 = load <32 x i8>, <32 x i8> addrspace(2)* %37, !tbaa !1
+  %39 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %1, i32 0
+  %40 = load <16 x i8>, <16 x i8> addrspace(2)* %39, !tbaa !1
   %41 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
   %42 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
   %43 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
@@ -154,8 +154,8 @@ ENDIF24:                                          ; preds = %ENDIF, %IF25
 
 define void @loop(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
 main_body:
-  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
-  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !1
+  %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
+  %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20, !tbaa !1
   %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
   %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
   %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
@@ -236,13 +236,13 @@ declare i32 @llvm.SI.packf16(float, float) #1
 define void @sample_v3([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
 
 entry:
-  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
-  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !2
+  %21 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
+  %22 = load <16 x i8>, <16 x i8> addrspace(2)* %21, !tbaa !2
   %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
-  %24 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
-  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !2
-  %26 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
-  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !2
+  %24 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
+  %25 = load <32 x i8>, <32 x i8> addrspace(2)* %24, !tbaa !2
+  %26 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
+  %27 = load <16 x i8>, <16 x i8> addrspace(2)* %26, !tbaa !2
   %28 = fcmp oeq float %23, 0.0
   br i1 %28, label %if, label %else
 
@@ -276,7 +276,7 @@ endif:
 ; CHECK: s_endpgm
 define void @copy1(float addrspace(1)* %out, float addrspace(1)* %in0) {
 entry:
-  %0 = load float addrspace(1)* %in0
+  %0 = load float, float addrspace(1)* %in0
   %1 = fcmp oeq float %0, 0.0
   br i1 %1, label %if0, label %endif
 
@@ -334,13 +334,13 @@ attributes #0 = { "ShaderType"="0" }
 ; CHECK: s_endpgm
 define void @sample_rsrc([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <4 x i32>] addrspace(2)* byval %arg2, [32 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
 bb:
-  %tmp = getelementptr [17 x <16 x i8>] addrspace(2)* %arg1, i32 0, i32 0
-  %tmp22 = load <16 x i8> addrspace(2)* %tmp, !tbaa !0
+  %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg1, i32 0, i32 0
+  %tmp22 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
   %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp22, i32 16)
-  %tmp25 = getelementptr [32 x <8 x i32>] addrspace(2)* %arg3, i32 0, i32 0
-  %tmp26 = load <8 x i32> addrspace(2)* %tmp25, !tbaa !0
-  %tmp27 = getelementptr [16 x <4 x i32>] addrspace(2)* %arg2, i32 0, i32 0
-  %tmp28 = load <4 x i32> addrspace(2)* %tmp27, !tbaa !0
+  %tmp25 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %arg3, i32 0, i32 0
+  %tmp26 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp25, !tbaa !0
+  %tmp27 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %arg2, i32 0, i32 0
+  %tmp28 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp27, !tbaa !0
   %tmp29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg5, <2 x i32> %arg7)
   %tmp30 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg5, <2 x i32> %arg7)
   %tmp31 = bitcast float %tmp23 to i32
diff --git a/test/CodeGen/R600/shl.ll b/test/CodeGen/R600/shl.ll
index f89353b10844..53b63dc4b8ad 100644
--- a/test/CodeGen/R600/shl.ll
+++ b/test/CodeGen/R600/shl.ll
@@ -15,9 +15,9 @@
 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 
 define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
-  %a = load <2 x i32> addrspace(1) * %in
-  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32>, <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
   %result = shl <2 x i32> %a, %b
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
   ret void
@@ -42,9 +42,9 @@ define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in
 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 
 define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
-  %a = load <4 x i32> addrspace(1) * %in
-  %b = load <4 x i32> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
+  %a = load <4 x i32>, <4 x i32> addrspace(1) * %in
+  %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
   %result = shl <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
@@ -69,9 +69,9 @@ define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in
 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
 
 define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
-  %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1
-  %a = load i64 addrspace(1) * %in
-  %b = load i64 addrspace(1) * %b_ptr
+  %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
+  %a = load i64, i64 addrspace(1) * %in
+  %b = load i64, i64 addrspace(1) * %b_ptr
   %result = shl i64 %a, %b
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -108,9 +108,9 @@ define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
 
 define void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
-  %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1
-  %a = load <2 x i64> addrspace(1) * %in
-  %b = load <2 x i64> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1
+  %a = load <2 x i64>, <2 x i64> addrspace(1) * %in
+  %b = load <2 x i64>, <2 x i64> addrspace(1) * %b_ptr
   %result = shl <2 x i64> %a, %b
   store <2 x i64> %result, <2 x i64> addrspace(1)* %out
   ret void
@@ -171,9 +171,9 @@ define void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in
 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
 
 define void @shl_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1
-  %a = load <4 x i64> addrspace(1) * %in
-  %b = load <4 x i64> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
+  %a = load <4 x i64>, <4 x i64> addrspace(1) * %in
+  %b = load <4 x i64>, <4 x i64> addrspace(1) * %b_ptr
   %result = shl <4 x i64> %a, %b
   store <4 x i64> %result, <4 x i64> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/shl_add_constant.ll b/test/CodeGen/R600/shl_add_constant.ll
index 6915495beece..b1485bfaaebb 100644
--- a/test/CodeGen/R600/shl_add_constant.ll
+++ b/test/CodeGen/R600/shl_add_constant.ll
@@ -11,8 +11,8 @@ declare i32 @llvm.r600.read.tidig.x() #1
 ; SI: s_endpgm
 define void @shl_2_add_9_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
-  %ptr = getelementptr i32 addrspace(1)* %in, i32 %tid.x
-  %val = load i32 addrspace(1)* %ptr, align 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %tid.x
+  %val = load i32, i32 addrspace(1)* %ptr, align 4
   %add = add i32 %val, 9
   %result = shl i32 %add, 2
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -27,8 +27,8 @@ define void @shl_2_add_9_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
 ; SI: s_endpgm
 define void @shl_2_add_9_i32_2_add_uses(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %in) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
-  %ptr = getelementptr i32 addrspace(1)* %in, i32 %tid.x
-  %val = load i32 addrspace(1)* %ptr, align 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %tid.x
+  %val = load i32, i32 addrspace(1)* %ptr, align 4
   %add = add i32 %val, 9
   %result = shl i32 %add, 2
   store i32 %result, i32 addrspace(1)* %out0, align 4
@@ -45,8 +45,8 @@ define void @shl_2_add_9_i32_2_add_uses(i32 addrspace(1)* %out0, i32 addrspace(1
 ; SI: s_endpgm
 define void @shl_2_add_999_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
-  %ptr = getelementptr i32 addrspace(1)* %in, i32 %tid.x
-  %val = load i32 addrspace(1)* %ptr, align 4
+  %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %tid.x
+  %val = load i32, i32 addrspace(1)* %ptr, align 4
   %shl = add i32 %val, 999
   %result = shl i32 %shl, 2
   store i32 %result, i32 addrspace(1)* %out, align 4
diff --git a/test/CodeGen/R600/shl_add_ptr.ll b/test/CodeGen/R600/shl_add_ptr.ll
index 15602e820608..6671e909cd1d 100644
--- a/test/CodeGen/R600/shl_add_ptr.ll
+++ b/test/CodeGen/R600/shl_add_ptr.ll
@@ -17,13 +17,13 @@ declare i32 @llvm.r600.read.tidig.x() #1
 
 ; SI-LABEL: {{^}}load_shl_base_lds_0:
 ; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; SI: ds_read_b32 {{v[0-9]+}}, [[PTR]] offset:8 [M0]
+; SI: ds_read_b32 {{v[0-9]+}}, [[PTR]] offset:8
 ; SI: s_endpgm
 define void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 2
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
   store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
   store float %val0, float addrspace(1)* %out
   ret void
@@ -34,7 +34,7 @@ define void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %ad
 
 ; SI-LABEL: {{^}}load_shl_base_lds_1:
 ; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; SI: ds_read_b32 [[RESULT:v[0-9]+]], [[PTR]] offset:8 [M0]
+; SI: ds_read_b32 [[RESULT:v[0-9]+]], [[PTR]] offset:8
 ; SI: v_add_i32_e32 [[ADDUSE:v[0-9]+]], 8, v{{[0-9]+}}
 ; SI-DAG: buffer_store_dword [[RESULT]]
 ; SI-DAG: buffer_store_dword [[ADDUSE]]
@@ -42,8 +42,8 @@ define void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %ad
 define void @load_shl_base_lds_1(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 2
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
   %shl_add_use = shl i32 %idx.0, 2
   store i32 %shl_add_use, i32 addrspace(1)* %add_use, align 4
   store float %val0, float addrspace(1)* %out
@@ -58,8 +58,8 @@ define void @load_shl_base_lds_1(float addrspace(1)* %out, i32 addrspace(1)* %ad
 define void @load_shl_base_lds_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %lds, i32 addrspace(1)* %add_use) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 65535
-  %arrayidx0 = getelementptr inbounds [65536 x i8] addrspace(3)* @maxlds, i32 0, i32 %idx.0
-  %val0 = load i8 addrspace(3)* %arrayidx0
+  %arrayidx0 = getelementptr inbounds [65536 x i8], [65536 x i8] addrspace(3)* @maxlds, i32 0, i32 %idx.0
+  %val0 = load i8, i8 addrspace(3)* %arrayidx0
   store i32 %idx.0, i32 addrspace(1)* %add_use
   store i8 %val0, i8 addrspace(1)* %out
   ret void
@@ -69,17 +69,17 @@ define void @load_shl_base_lds_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)
 ; pointer can be used with an offset into the second one.
 
 ; SI-LABEL: {{^}}load_shl_base_lds_2:
+; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
 ; SI: s_mov_b32 m0, -1
-; SI-NEXT: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; SI-NEXT: ds_read2st64_b32 {{v\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:1 offset1:9 [M0]
+; SI-NEXT: ds_read2st64_b32 {{v\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:1 offset1:9
 ; SI: s_endpgm
 define void @load_shl_base_lds_2(float addrspace(1)* %out) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 64
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
-  %val0 = load float addrspace(3)* %arrayidx0, align 4
-  %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds1, i32 0, i32 %idx.0
-  %val1 = load float addrspace(3)* %arrayidx1, align 4
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
+  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
+  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds1, i32 0, i32 %idx.0
+  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
   %sum = fadd float %val0, %val1
   store float %sum, float addrspace(1)* %out, align 4
   ret void
@@ -87,12 +87,12 @@ define void @load_shl_base_lds_2(float addrspace(1)* %out) #0 {
 
 ; SI-LABEL: {{^}}store_shl_base_lds_0:
 ; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; SI: ds_write_b32 [[PTR]], {{v[0-9]+}} offset:8 [M0]
+; SI: ds_write_b32 [[PTR]], {{v[0-9]+}} offset:8
 ; SI: s_endpgm
 define void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 2
-  %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
+  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
   store float 1.0, float addrspace(3)* %arrayidx0, align 4
   store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
   ret void
@@ -107,8 +107,8 @@ define void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %a
 ; define void @atomic_load_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
 ;   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
 ;   %idx.0 = add nsw i32 %tid.x, 2
-;   %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
-;   %val = load atomic i32 addrspace(3)* %arrayidx0 seq_cst, align 4
+;   %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
+;   %val = load atomic i32, i32 addrspace(3)* %arrayidx0 seq_cst, align 4
 ;   store i32 %val, i32 addrspace(1)* %out, align 4
 ;   store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
 ;   ret void
@@ -122,7 +122,7 @@ define void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %a
 define void @atomic_cmpxchg_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use, i32 %swap) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 2
-  %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
+  %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
   %pair = cmpxchg i32 addrspace(3)* %arrayidx0, i32 7, i32 %swap seq_cst monotonic
   %result = extractvalue { i32, i1 } %pair, 0
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -137,7 +137,7 @@ define void @atomic_cmpxchg_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace
 define void @atomic_swap_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 2
-  %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
+  %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
   %val = atomicrmw xchg i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
   store i32 %val, i32 addrspace(1)* %out, align 4
   store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
@@ -151,7 +151,7 @@ define void @atomic_swap_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)
 define void @atomic_add_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 2
-  %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
+  %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
   %val = atomicrmw add i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
   store i32 %val, i32 addrspace(1)* %out, align 4
   store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
@@ -165,7 +165,7 @@ define void @atomic_add_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)*
 define void @atomic_sub_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 2
-  %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
+  %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
   %val = atomicrmw sub i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
   store i32 %val, i32 addrspace(1)* %out, align 4
   store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
@@ -179,7 +179,7 @@ define void @atomic_sub_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)*
 define void @atomic_and_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 2
-  %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
+  %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
   %val = atomicrmw and i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
   store i32 %val, i32 addrspace(1)* %out, align 4
   store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
@@ -193,7 +193,7 @@ define void @atomic_and_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)*
 define void @atomic_or_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 2
-  %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
+  %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
   %val = atomicrmw or i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
   store i32 %val, i32 addrspace(1)* %out, align 4
   store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
@@ -207,7 +207,7 @@ define void @atomic_or_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)*
 define void @atomic_xor_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 2
-  %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
+  %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
   %val = atomicrmw xor i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
   store i32 %val, i32 addrspace(1)* %out, align 4
   store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
@@ -217,7 +217,7 @@ define void @atomic_xor_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)*
 ; define void @atomic_nand_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
 ;   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
 ;   %idx.0 = add nsw i32 %tid.x, 2
-;   %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
+;   %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
 ;   %val = atomicrmw nand i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
 ;   store i32 %val, i32 addrspace(1)* %out, align 4
 ;   store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
@@ -231,7 +231,7 @@ define void @atomic_xor_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)*
 define void @atomic_min_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 2
-  %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
+  %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
   %val = atomicrmw min i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
   store i32 %val, i32 addrspace(1)* %out, align 4
   store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
@@ -245,7 +245,7 @@ define void @atomic_min_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)*
 define void @atomic_max_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 2
-  %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
+  %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
   %val = atomicrmw max i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
   store i32 %val, i32 addrspace(1)* %out, align 4
   store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
@@ -259,7 +259,7 @@ define void @atomic_max_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)*
 define void @atomic_umin_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 2
-  %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
+  %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
   %val = atomicrmw umin i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
   store i32 %val, i32 addrspace(1)* %out, align 4
   store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
@@ -273,7 +273,7 @@ define void @atomic_umin_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)
 define void @atomic_umax_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
   %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
   %idx.0 = add nsw i32 %tid.x, 2
-  %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
+  %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
   %val = atomicrmw umax i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
   store i32 %val, i32 addrspace(1)* %out, align 4
   store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
diff --git a/test/CodeGen/R600/si-annotate-cf.ll b/test/CodeGen/R600/si-annotate-cf.ll
index 1b49a8272fa3..bbcb861f37dc 100644
--- a/test/CodeGen/R600/si-annotate-cf.ll
+++ b/test/CodeGen/R600/si-annotate-cf.ll
@@ -29,10 +29,10 @@ ENDIF:
 ; FIXME: This could be folded into the s_or_b64 instruction
 ; SI: s_mov_b64 [[ZERO:s\[[0-9]+:[0-9]+\]]], 0
 ; SI: [[LOOP_LABEL:[A-Z0-9]+]]
-; SI: v_cmp_ne_i32_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0
+; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
 
 ; SI_IF_BREAK instruction:
-; SI: s_or_b64 [[BREAK:s\[[0-9]+:[0-9]+\]]], [[COND]], [[ZERO]]
+; SI: s_or_b64 [[BREAK:s\[[0-9]+:[0-9]+\]]], vcc, [[ZERO]]
 
 ; SI_LOOP instruction:
 ; SI: s_andn2_b64 exec, exec, [[BREAK]]
diff --git a/test/CodeGen/R600/si-lod-bias.ll b/test/CodeGen/R600/si-lod-bias.ll
index d6cbd0fd367d..944499a11461 100644
--- a/test/CodeGen/R600/si-lod-bias.ll
+++ b/test/CodeGen/R600/si-lod-bias.ll
@@ -9,13 +9,13 @@
 
 define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
 main_body:
-  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
-  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !1
+  %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
+  %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20, !tbaa !1
   %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
-  %23 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
-  %24 = load <32 x i8> addrspace(2)* %23, !tbaa !1
-  %25 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
-  %26 = load <16 x i8> addrspace(2)* %25, !tbaa !1
+  %23 = getelementptr <32 x i8>, <32 x i8> addrspace(2)* %2, i32 0
+  %24 = load <32 x i8>, <32 x i8> addrspace(2)* %23, !tbaa !1
+  %25 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %1, i32 0
+  %26 = load <16 x i8>, <16 x i8> addrspace(2)* %25, !tbaa !1
   %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
   %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
   %29 = bitcast float %22 to i32
diff --git a/test/CodeGen/R600/si-sgpr-spill.ll b/test/CodeGen/R600/si-sgpr-spill.ll
index 18fda20b0d14..84652701f773 100644
--- a/test/CodeGen/R600/si-sgpr-spill.ll
+++ b/test/CodeGen/R600/si-sgpr-spill.ll
@@ -13,8 +13,8 @@
 
 define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
 main_body:
-  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
-  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
+  %21 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
+  %22 = load <16 x i8>, <16 x i8> addrspace(2)* %21, !tbaa !0
   %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 96)
   %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 100)
   %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 104)
@@ -53,38 +53,38 @@ main_body:
   %58 = call float @llvm.SI.load.const(<16 x i8> %22, i32 372)
   %59 = call float @llvm.SI.load.const(<16 x i8> %22, i32 376)
   %60 = call float @llvm.SI.load.const(<16 x i8> %22, i32 384)
-  %61 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
-  %62 = load <32 x i8> addrspace(2)* %61, !tbaa !0
-  %63 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
-  %64 = load <16 x i8> addrspace(2)* %63, !tbaa !0
-  %65 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
-  %66 = load <32 x i8> addrspace(2)* %65, !tbaa !0
-  %67 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
-  %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0
-  %69 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2
-  %70 = load <32 x i8> addrspace(2)* %69, !tbaa !0
-  %71 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2
-  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
-  %73 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 3
-  %74 = load <32 x i8> addrspace(2)* %73, !tbaa !0
-  %75 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 3
-  %76 = load <16 x i8> addrspace(2)* %75, !tbaa !0
-  %77 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 4
-  %78 = load <32 x i8> addrspace(2)* %77, !tbaa !0
-  %79 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 4
-  %80 = load <16 x i8> addrspace(2)* %79, !tbaa !0
-  %81 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 5
-  %82 = load <32 x i8> addrspace(2)* %81, !tbaa !0
-  %83 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 5
-  %84 = load <16 x i8> addrspace(2)* %83, !tbaa !0
-  %85 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 6
-  %86 = load <32 x i8> addrspace(2)* %85, !tbaa !0
-  %87 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 6
-  %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0
-  %89 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 7
-  %90 = load <32 x i8> addrspace(2)* %89, !tbaa !0
-  %91 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 7
-  %92 = load <16 x i8> addrspace(2)* %91, !tbaa !0
+  %61 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
+  %62 = load <32 x i8>, <32 x i8> addrspace(2)* %61, !tbaa !0
+  %63 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
+  %64 = load <16 x i8>, <16 x i8> addrspace(2)* %63, !tbaa !0
+  %65 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
+  %66 = load <32 x i8>, <32 x i8> addrspace(2)* %65, !tbaa !0
+  %67 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
+  %68 = load <16 x i8>, <16 x i8> addrspace(2)* %67, !tbaa !0
+  %69 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2
+  %70 = load <32 x i8>, <32 x i8> addrspace(2)* %69, !tbaa !0
+  %71 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2
+  %72 = load <16 x i8>, <16 x i8> addrspace(2)* %71, !tbaa !0
+  %73 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 3
+  %74 = load <32 x i8>, <32 x i8> addrspace(2)* %73, !tbaa !0
+  %75 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 3
+  %76 = load <16 x i8>, <16 x i8> addrspace(2)* %75, !tbaa !0
+  %77 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 4
+  %78 = load <32 x i8>, <32 x i8> addrspace(2)* %77, !tbaa !0
+  %79 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 4
+  %80 = load <16 x i8>, <16 x i8> addrspace(2)* %79, !tbaa !0
+  %81 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 5
+  %82 = load <32 x i8>, <32 x i8> addrspace(2)* %81, !tbaa !0
+  %83 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 5
+  %84 = load <16 x i8>, <16 x i8> addrspace(2)* %83, !tbaa !0
+  %85 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 6
+  %86 = load <32 x i8>, <32 x i8> addrspace(2)* %85, !tbaa !0
+  %87 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 6
+  %88 = load <16 x i8>, <16 x i8> addrspace(2)* %87, !tbaa !0
+  %89 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 7
+  %90 = load <32 x i8>, <32 x i8> addrspace(2)* %89, !tbaa !0
+  %91 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 7
+  %92 = load <16 x i8>, <16 x i8> addrspace(2)* %91, !tbaa !0
   %93 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
   %94 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
   %95 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6)
@@ -103,29 +103,29 @@ main_body:
   %108 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %4, <2 x i32> %6)
   %109 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %4, <2 x i32> %6)
   %110 = call i32 @llvm.SI.tid()
-  %111 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %110
+  %111 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %110
   %112 = bitcast float %93 to i32
   store i32 %112, i32 addrspace(3)* %111
   %113 = bitcast float %94 to i32
   store i32 %113, i32 addrspace(3)* %111
   %114 = call i32 @llvm.SI.tid()
-  %115 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %114
+  %115 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %114
   %116 = and i32 %114, -4
-  %117 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %116
+  %117 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %116
   %118 = add i32 %116, 1
-  %119 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %118
+  %119 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %118
   %120 = bitcast float %93 to i32
   store i32 %120, i32 addrspace(3)* %115
-  %121 = load i32 addrspace(3)* %117
+  %121 = load i32, i32 addrspace(3)* %117
   %122 = bitcast i32 %121 to float
-  %123 = load i32 addrspace(3)* %119
+  %123 = load i32, i32 addrspace(3)* %119
   %124 = bitcast i32 %123 to float
   %125 = fsub float %124, %122
   %126 = bitcast float %94 to i32
   store i32 %126, i32 addrspace(3)* %115
-  %127 = load i32 addrspace(3)* %117
+  %127 = load i32, i32 addrspace(3)* %117
   %128 = bitcast i32 %127 to float
-  %129 = load i32 addrspace(3)* %119
+  %129 = load i32, i32 addrspace(3)* %119
   %130 = bitcast i32 %129 to float
   %131 = fsub float %130, %128
   %132 = insertelement <4 x float> undef, float %125, i32 0
@@ -139,7 +139,7 @@ main_body:
   %140 = fmul float %60, %94
   %141 = fmul float %60, %94
   %142 = call i32 @llvm.SI.tid()
-  %143 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %142
+  %143 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %142
   %144 = bitcast float %138 to i32
   store i32 %144, i32 addrspace(3)* %143
   %145 = bitcast float %139 to i32
@@ -149,37 +149,37 @@ main_body:
   %147 = bitcast float %141 to i32
   store i32 %147, i32 addrspace(3)* %143
   %148 = call i32 @llvm.SI.tid()
-  %149 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %148
+  %149 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %148
   %150 = and i32 %148, -4
-  %151 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %150
+  %151 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %150
   %152 = add i32 %150, 2
-  %153 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %152
+  %153 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %152
   %154 = bitcast float %138 to i32
   store i32 %154, i32 addrspace(3)* %149
-  %155 = load i32 addrspace(3)* %151
+  %155 = load i32, i32 addrspace(3)* %151
   %156 = bitcast i32 %155 to float
-  %157 = load i32 addrspace(3)* %153
+  %157 = load i32, i32 addrspace(3)* %153
   %158 = bitcast i32 %157 to float
   %159 = fsub float %158, %156
   %160 = bitcast float %139 to i32
   store i32 %160, i32 addrspace(3)* %149
-  %161 = load i32 addrspace(3)* %151
+  %161 = load i32, i32 addrspace(3)* %151
   %162 = bitcast i32 %161 to float
-  %163 = load i32 addrspace(3)* %153
+  %163 = load i32, i32 addrspace(3)* %153
   %164 = bitcast i32 %163 to float
   %165 = fsub float %164, %162
   %166 = bitcast float %140 to i32
   store i32 %166, i32 addrspace(3)* %149
-  %167 = load i32 addrspace(3)* %151
+  %167 = load i32, i32 addrspace(3)* %151
   %168 = bitcast i32 %167 to float
-  %169 = load i32 addrspace(3)* %153
+  %169 = load i32, i32 addrspace(3)* %153
   %170 = bitcast i32 %169 to float
   %171 = fsub float %170, %168
   %172 = bitcast float %141 to i32
   store i32 %172, i32 addrspace(3)* %149
-  %173 = load i32 addrspace(3)* %151
+  %173 = load i32, i32 addrspace(3)* %151
   %174 = bitcast i32 %173 to float
-  %175 = load i32 addrspace(3)* %153
+  %175 = load i32, i32 addrspace(3)* %153
   %176 = bitcast i32 %175 to float
   %177 = fsub float %176, %174
   %178 = insertelement <4 x float> undef, float %159, i32 0
@@ -694,8 +694,8 @@ attributes #4 = { nounwind readonly }
 ; CHECK: s_endpgm
 define void @main1([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
 main_body:
-  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
-  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
+  %21 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
+  %22 = load <16 x i8>, <16 x i8> addrspace(2)* %21, !tbaa !0
   %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
   %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
   %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8)
@@ -799,42 +799,42 @@ main_body:
   %123 = call float @llvm.SI.load.const(<16 x i8> %22, i32 716)
   %124 = call float @llvm.SI.load.const(<16 x i8> %22, i32 864)
   %125 = call float @llvm.SI.load.const(<16 x i8> %22, i32 868)
-  %126 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
-  %127 = load <32 x i8> addrspace(2)* %126, !tbaa !0
-  %128 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
-  %129 = load <16 x i8> addrspace(2)* %128, !tbaa !0
-  %130 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
-  %131 = load <32 x i8> addrspace(2)* %130, !tbaa !0
-  %132 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
-  %133 = load <16 x i8> addrspace(2)* %132, !tbaa !0
-  %134 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2
-  %135 = load <32 x i8> addrspace(2)* %134, !tbaa !0
-  %136 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2
-  %137 = load <16 x i8> addrspace(2)* %136, !tbaa !0
-  %138 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 3
-  %139 = load <32 x i8> addrspace(2)* %138, !tbaa !0
-  %140 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 3
-  %141 = load <16 x i8> addrspace(2)* %140, !tbaa !0
-  %142 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 4
-  %143 = load <32 x i8> addrspace(2)* %142, !tbaa !0
-  %144 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 4
-  %145 = load <16 x i8> addrspace(2)* %144, !tbaa !0
-  %146 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 5
-  %147 = load <32 x i8> addrspace(2)* %146, !tbaa !0
-  %148 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 5
-  %149 = load <16 x i8> addrspace(2)* %148, !tbaa !0
-  %150 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 6
-  %151 = load <32 x i8> addrspace(2)* %150, !tbaa !0
-  %152 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 6
-  %153 = load <16 x i8> addrspace(2)* %152, !tbaa !0
-  %154 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 7
-  %155 = load <32 x i8> addrspace(2)* %154, !tbaa !0
-  %156 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 7
-  %157 = load <16 x i8> addrspace(2)* %156, !tbaa !0
-  %158 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 8
-  %159 = load <32 x i8> addrspace(2)* %158, !tbaa !0
-  %160 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 8
-  %161 = load <16 x i8> addrspace(2)* %160, !tbaa !0
+  %126 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
+  %127 = load <32 x i8>, <32 x i8> addrspace(2)* %126, !tbaa !0
+  %128 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
+  %129 = load <16 x i8>, <16 x i8> addrspace(2)* %128, !tbaa !0
+  %130 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
+  %131 = load <32 x i8>, <32 x i8> addrspace(2)* %130, !tbaa !0
+  %132 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
+  %133 = load <16 x i8>, <16 x i8> addrspace(2)* %132, !tbaa !0
+  %134 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2
+  %135 = load <32 x i8>, <32 x i8> addrspace(2)* %134, !tbaa !0
+  %136 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2
+  %137 = load <16 x i8>, <16 x i8> addrspace(2)* %136, !tbaa !0
+  %138 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 3
+  %139 = load <32 x i8>, <32 x i8> addrspace(2)* %138, !tbaa !0
+  %140 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 3
+  %141 = load <16 x i8>, <16 x i8> addrspace(2)* %140, !tbaa !0
+  %142 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 4
+  %143 = load <32 x i8>, <32 x i8> addrspace(2)* %142, !tbaa !0
+  %144 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 4
+  %145 = load <16 x i8>, <16 x i8> addrspace(2)* %144, !tbaa !0
+  %146 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 5
+  %147 = load <32 x i8>, <32 x i8> addrspace(2)* %146, !tbaa !0
+  %148 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 5
+  %149 = load <16 x i8>, <16 x i8> addrspace(2)* %148, !tbaa !0
+  %150 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 6
+  %151 = load <32 x i8>, <32 x i8> addrspace(2)* %150, !tbaa !0
+  %152 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 6
+  %153 = load <16 x i8>, <16 x i8> addrspace(2)* %152, !tbaa !0
+  %154 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 7
+  %155 = load <32 x i8>, <32 x i8> addrspace(2)* %154, !tbaa !0
+  %156 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 7
+  %157 = load <16 x i8>, <16 x i8> addrspace(2)* %156, !tbaa !0
+  %158 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 8
+  %159 = load <32 x i8>, <32 x i8> addrspace(2)* %158, !tbaa !0
+  %160 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 8
+  %161 = load <16 x i8>, <16 x i8> addrspace(2)* %160, !tbaa !0
   %162 = fcmp ugt float %17, 0.000000e+00
   %163 = select i1 %162, float 1.000000e+00, float 0.000000e+00
   %164 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
diff --git a/test/CodeGen/R600/si-spill-cf.ll b/test/CodeGen/R600/si-spill-cf.ll
new file mode 100644
index 000000000000..4b2d8ec6bf0a
--- /dev/null
+++ b/test/CodeGen/R600/si-spill-cf.ll
@@ -0,0 +1,501 @@
+; RUN: llc -march=amdgcn -mcpu=SI < %s -verify-machineinstrs | FileCheck -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=tonga < %s -verify-machineinstrs | FileCheck -check-prefix=SI %s
+
+; If this occurs it is likely due to reordering and the restore was
+; originally supposed to happen before SI_END_CF.
+; SI: s_or_b64 exec, exec, [[SAVED:s\[[0-9]+:[0-9]+\]|[a-z]+]]
+; SI-NOT: v_readlane_b32 [[SAVED]]
+
+define void @main() #0 {
+main_body:
+  %0 = call float @llvm.SI.load.const(<16 x i8> undef, i32 16)
+  %1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 32)
+  %2 = call float @llvm.SI.load.const(<16 x i8> undef, i32 80)
+  %3 = call float @llvm.SI.load.const(<16 x i8> undef, i32 84)
+  %4 = call float @llvm.SI.load.const(<16 x i8> undef, i32 88)
+  %5 = call float @llvm.SI.load.const(<16 x i8> undef, i32 96)
+  %6 = call float @llvm.SI.load.const(<16 x i8> undef, i32 100)
+  %7 = call float @llvm.SI.load.const(<16 x i8> undef, i32 104)
+  %8 = call float @llvm.SI.load.const(<16 x i8> undef, i32 112)
+  %9 = call float @llvm.SI.load.const(<16 x i8> undef, i32 116)
+  %10 = call float @llvm.SI.load.const(<16 x i8> undef, i32 120)
+  %11 = call float @llvm.SI.load.const(<16 x i8> undef, i32 128)
+  %12 = call float @llvm.SI.load.const(<16 x i8> undef, i32 132)
+  %13 = call float @llvm.SI.load.const(<16 x i8> undef, i32 136)
+  %14 = call float @llvm.SI.load.const(<16 x i8> undef, i32 144)
+  %15 = call float @llvm.SI.load.const(<16 x i8> undef, i32 148)
+  %16 = call float @llvm.SI.load.const(<16 x i8> undef, i32 152)
+  %17 = call float @llvm.SI.load.const(<16 x i8> undef, i32 160)
+  %18 = call float @llvm.SI.load.const(<16 x i8> undef, i32 164)
+  %19 = call float @llvm.SI.load.const(<16 x i8> undef, i32 168)
+  %20 = call float @llvm.SI.load.const(<16 x i8> undef, i32 176)
+  %21 = call float @llvm.SI.load.const(<16 x i8> undef, i32 180)
+  %22 = call float @llvm.SI.load.const(<16 x i8> undef, i32 184)
+  %23 = call float @llvm.SI.load.const(<16 x i8> undef, i32 192)
+  %24 = call float @llvm.SI.load.const(<16 x i8> undef, i32 196)
+  %25 = call float @llvm.SI.load.const(<16 x i8> undef, i32 200)
+  %26 = call float @llvm.SI.load.const(<16 x i8> undef, i32 208)
+  %27 = call float @llvm.SI.load.const(<16 x i8> undef, i32 212)
+  %28 = call float @llvm.SI.load.const(<16 x i8> undef, i32 216)
+  %29 = call float @llvm.SI.load.const(<16 x i8> undef, i32 224)
+  %30 = call float @llvm.SI.load.const(<16 x i8> undef, i32 228)
+  %31 = call float @llvm.SI.load.const(<16 x i8> undef, i32 232)
+  %32 = call float @llvm.SI.load.const(<16 x i8> undef, i32 240)
+  %33 = call float @llvm.SI.load.const(<16 x i8> undef, i32 244)
+  %34 = call float @llvm.SI.load.const(<16 x i8> undef, i32 248)
+  %35 = call float @llvm.SI.load.const(<16 x i8> undef, i32 256)
+  %36 = call float @llvm.SI.load.const(<16 x i8> undef, i32 260)
+  %37 = call float @llvm.SI.load.const(<16 x i8> undef, i32 264)
+  %38 = call float @llvm.SI.load.const(<16 x i8> undef, i32 272)
+  %39 = call float @llvm.SI.load.const(<16 x i8> undef, i32 276)
+  %40 = call float @llvm.SI.load.const(<16 x i8> undef, i32 280)
+  %41 = call float @llvm.SI.load.const(<16 x i8> undef, i32 288)
+  %42 = call float @llvm.SI.load.const(<16 x i8> undef, i32 292)
+  %43 = call float @llvm.SI.load.const(<16 x i8> undef, i32 296)
+  %44 = call float @llvm.SI.load.const(<16 x i8> undef, i32 304)
+  %45 = call float @llvm.SI.load.const(<16 x i8> undef, i32 308)
+  %46 = call float @llvm.SI.load.const(<16 x i8> undef, i32 312)
+  %47 = call float @llvm.SI.load.const(<16 x i8> undef, i32 320)
+  %48 = call float @llvm.SI.load.const(<16 x i8> undef, i32 324)
+  %49 = call float @llvm.SI.load.const(<16 x i8> undef, i32 328)
+  %50 = call float @llvm.SI.load.const(<16 x i8> undef, i32 336)
+  %51 = call float @llvm.SI.load.const(<16 x i8> undef, i32 340)
+  %52 = call float @llvm.SI.load.const(<16 x i8> undef, i32 344)
+  %53 = call float @llvm.SI.load.const(<16 x i8> undef, i32 352)
+  %54 = call float @llvm.SI.load.const(<16 x i8> undef, i32 356)
+  %55 = call float @llvm.SI.load.const(<16 x i8> undef, i32 360)
+  %56 = call float @llvm.SI.load.const(<16 x i8> undef, i32 368)
+  %57 = call float @llvm.SI.load.const(<16 x i8> undef, i32 372)
+  %58 = call float @llvm.SI.load.const(<16 x i8> undef, i32 376)
+  %59 = call float @llvm.SI.load.const(<16 x i8> undef, i32 384)
+  %60 = call float @llvm.SI.load.const(<16 x i8> undef, i32 388)
+  %61 = call float @llvm.SI.load.const(<16 x i8> undef, i32 392)
+  %62 = call float @llvm.SI.load.const(<16 x i8> undef, i32 400)
+  %63 = call float @llvm.SI.load.const(<16 x i8> undef, i32 404)
+  %64 = call float @llvm.SI.load.const(<16 x i8> undef, i32 408)
+  %65 = call float @llvm.SI.load.const(<16 x i8> undef, i32 416)
+  %66 = call float @llvm.SI.load.const(<16 x i8> undef, i32 420)
+  br label %LOOP
+
+LOOP:                                             ; preds = %ENDIF2795, %main_body
+  %temp894.0 = phi float [ 0.000000e+00, %main_body ], [ %temp894.1, %ENDIF2795 ]
+  %temp18.0 = phi float [ undef, %main_body ], [ %temp18.1, %ENDIF2795 ]
+  %67 = icmp sgt i32 undef, 4
+  br i1 %67, label %ENDLOOP, label %ENDIF
+
+ENDLOOP:                                          ; preds = %ELSE2566, %LOOP
+  %68 = call float @llvm.AMDGPU.lrp(float %0, float undef, float undef)
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float undef, float %68, float undef, float 1.000000e+00)
+  ret void
+
+ENDIF:                                            ; preds = %LOOP
+  %69 = fsub float %2, undef
+  %70 = fsub float %3, undef
+  %71 = fsub float %4, undef
+  %72 = fmul float %69, 0.000000e+00
+  %73 = fmul float %70, undef
+  %74 = fmul float %71, undef
+  %75 = fsub float %6, undef
+  %76 = fsub float %7, undef
+  %77 = fmul float %75, undef
+  %78 = fmul float %76, 0.000000e+00
+  %79 = call float @llvm.minnum.f32(float %74, float %78)
+  %80 = call float @llvm.maxnum.f32(float %72, float 0.000000e+00)
+  %81 = call float @llvm.maxnum.f32(float %73, float %77)
+  %82 = call float @llvm.maxnum.f32(float undef, float %79)
+  %83 = call float @llvm.minnum.f32(float %80, float %81)
+  %84 = call float @llvm.minnum.f32(float %83, float undef)
+  %85 = fsub float %14, undef
+  %86 = fsub float %15, undef
+  %87 = fsub float %16, undef
+  %88 = fmul float %85, undef
+  %89 = fmul float %86, undef
+  %90 = fmul float %87, undef
+  %91 = fsub float %17, undef
+  %92 = fsub float %18, undef
+  %93 = fsub float %19, undef
+  %94 = fmul float %91, 0.000000e+00
+  %95 = fmul float %92, undef
+  %96 = fmul float %93, undef
+  %97 = call float @llvm.minnum.f32(float %89, float %95)
+  %98 = call float @llvm.maxnum.f32(float %88, float %94)
+  %99 = call float @llvm.maxnum.f32(float %90, float %96)
+  %100 = call float @llvm.maxnum.f32(float undef, float %97)
+  %101 = call float @llvm.maxnum.f32(float %100, float undef)
+  %102 = call float @llvm.minnum.f32(float %98, float undef)
+  %103 = call float @llvm.minnum.f32(float %102, float %99)
+  %104 = fsub float %30, undef
+  %105 = fsub float %31, undef
+  %106 = fmul float %104, 0.000000e+00
+  %107 = fmul float %105, 0.000000e+00
+  %108 = call float @llvm.minnum.f32(float undef, float %106)
+  %109 = call float @llvm.maxnum.f32(float undef, float %107)
+  %110 = call float @llvm.maxnum.f32(float undef, float %108)
+  %111 = call float @llvm.maxnum.f32(float %110, float undef)
+  %112 = call float @llvm.minnum.f32(float undef, float %109)
+  %113 = fsub float %32, undef
+  %114 = fsub float %33, undef
+  %115 = fsub float %34, undef
+  %116 = fmul float %113, 0.000000e+00
+  %117 = fmul float %114, undef
+  %118 = fmul float %115, undef
+  %119 = fsub float %35, undef
+  %120 = fsub float %36, undef
+  %121 = fsub float %37, undef
+  %122 = fmul float %119, undef
+  %123 = fmul float %120, undef
+  %124 = fmul float %121, undef
+  %125 = call float @llvm.minnum.f32(float %116, float %122)
+  %126 = call float @llvm.minnum.f32(float %117, float %123)
+  %127 = call float @llvm.minnum.f32(float %118, float %124)
+  %128 = call float @llvm.maxnum.f32(float %125, float %126)
+  %129 = call float @llvm.maxnum.f32(float %128, float %127)
+  %130 = fsub float %38, undef
+  %131 = fsub float %39, undef
+  %132 = fsub float %40, undef
+  %133 = fmul float %130, 0.000000e+00
+  %134 = fmul float %131, undef
+  %135 = fmul float %132, undef
+  %136 = fsub float %41, undef
+  %137 = fsub float %42, undef
+  %138 = fsub float %43, undef
+  %139 = fmul float %136, undef
+  %140 = fmul float %137, undef
+  %141 = fmul float %138, undef
+  %142 = call float @llvm.minnum.f32(float %133, float %139)
+  %143 = call float @llvm.minnum.f32(float %134, float %140)
+  %144 = call float @llvm.minnum.f32(float %135, float %141)
+  %145 = call float @llvm.maxnum.f32(float %142, float %143)
+  %146 = call float @llvm.maxnum.f32(float %145, float %144)
+  %147 = fsub float %44, undef
+  %148 = fsub float %45, undef
+  %149 = fsub float %46, undef
+  %150 = fmul float %147, 0.000000e+00
+  %151 = fmul float %148, 0.000000e+00
+  %152 = fmul float %149, undef
+  %153 = fsub float %47, undef
+  %154 = fsub float %48, undef
+  %155 = fsub float %49, undef
+  %156 = fmul float %153, undef
+  %157 = fmul float %154, 0.000000e+00
+  %158 = fmul float %155, undef
+  %159 = call float @llvm.minnum.f32(float %150, float %156)
+  %160 = call float @llvm.minnum.f32(float %151, float %157)
+  %161 = call float @llvm.minnum.f32(float %152, float %158)
+  %162 = call float @llvm.maxnum.f32(float %159, float %160)
+  %163 = call float @llvm.maxnum.f32(float %162, float %161)
+  %164 = fsub float %50, undef
+  %165 = fsub float %51, undef
+  %166 = fsub float %52, undef
+  %167 = fmul float %164, undef
+  %168 = fmul float %165, 0.000000e+00
+  %169 = fmul float %166, 0.000000e+00
+  %170 = fsub float %53, undef
+  %171 = fsub float %54, undef
+  %172 = fsub float %55, undef
+  %173 = fdiv float 1.000000e+00, %temp18.0
+  %174 = fmul float %170, undef
+  %175 = fmul float %171, undef
+  %176 = fmul float %172, %173
+  %177 = call float @llvm.minnum.f32(float %167, float %174)
+  %178 = call float @llvm.minnum.f32(float %168, float %175)
+  %179 = call float @llvm.minnum.f32(float %169, float %176)
+  %180 = call float @llvm.maxnum.f32(float %177, float %178)
+  %181 = call float @llvm.maxnum.f32(float %180, float %179)
+  %182 = fsub float %62, undef
+  %183 = fsub float %63, undef
+  %184 = fsub float %64, undef
+  %185 = fmul float %182, 0.000000e+00
+  %186 = fmul float %183, undef
+  %187 = fmul float %184, undef
+  %188 = fsub float %65, undef
+  %189 = fsub float %66, undef
+  %190 = fmul float %188, undef
+  %191 = fmul float %189, undef
+  %192 = call float @llvm.maxnum.f32(float %185, float %190)
+  %193 = call float @llvm.maxnum.f32(float %186, float %191)
+  %194 = call float @llvm.maxnum.f32(float %187, float undef)
+  %195 = call float @llvm.minnum.f32(float %192, float %193)
+  %196 = call float @llvm.minnum.f32(float %195, float %194)
+  %.temp292.7 = select i1 undef, float %163, float undef
+  %temp292.9 = select i1 false, float %181, float %.temp292.7
+  %.temp292.9 = select i1 undef, float undef, float %temp292.9
+  %197 = fcmp ogt float undef, 0.000000e+00
+  %198 = fcmp olt float undef, %196
+  %199 = and i1 %197, %198
+  %200 = fcmp olt float undef, %.temp292.9
+  %201 = and i1 %199, %200
+  %temp292.11 = select i1 %201, float undef, float %.temp292.9
+  br i1 undef, label %IF2565, label %ELSE2566
+
+IF2565:                                           ; preds = %ENDIF
+  br i1 false, label %ENDIF2582, label %ELSE2584
+
+ELSE2566:                                         ; preds = %ENDIF
+  %202 = fcmp oeq float %temp292.11, 1.000000e+04
+  br i1 %202, label %ENDLOOP, label %ELSE2593
+
+ENDIF2564:                                        ; preds = %ENDIF2594, %ENDIF2588
+  %temp894.1 = phi float [ undef, %ENDIF2588 ], [ %temp894.2, %ENDIF2594 ]
+  %temp18.1 = phi float [ %219, %ENDIF2588 ], [ undef, %ENDIF2594 ]
+  %203 = fsub float %5, undef
+  %204 = fmul float %203, undef
+  %205 = call float @llvm.maxnum.f32(float undef, float %204)
+  %206 = call float @llvm.minnum.f32(float %205, float undef)
+  %207 = call float @llvm.minnum.f32(float %206, float undef)
+  %208 = fcmp ogt float undef, 0.000000e+00
+  %209 = fcmp olt float undef, 1.000000e+00
+  %210 = and i1 %208, %209
+  %211 = fcmp olt float undef, %207
+  %212 = and i1 %210, %211
+  br i1 %212, label %ENDIF2795, label %ELSE2797
+
+ELSE2584:                                         ; preds = %IF2565
+  br label %ENDIF2582
+
+ENDIF2582:                                        ; preds = %ELSE2584, %IF2565
+  %213 = fadd float %1, undef
+  %214 = fadd float 0.000000e+00, %213
+  %215 = call float @llvm.AMDIL.fraction.(float %214)
+  br i1 undef, label %IF2589, label %ELSE2590
+
+IF2589:                                           ; preds = %ENDIF2582
+  br label %ENDIF2588
+
+ELSE2590:                                         ; preds = %ENDIF2582
+  br label %ENDIF2588
+
+ENDIF2588:                                        ; preds = %ELSE2590, %IF2589
+  %216 = fsub float 1.000000e+00, %215
+  %217 = call float @llvm.sqrt.f32(float %216)
+  %218 = fmul float %217, undef
+  %219 = fadd float %218, undef
+  br label %ENDIF2564
+
+ELSE2593:                                         ; preds = %ELSE2566
+  %220 = fcmp oeq float %temp292.11, %82
+  %221 = fcmp olt float %82, %84
+  %222 = and i1 %220, %221
+  br i1 %222, label %ENDIF2594, label %ELSE2596
+
+ELSE2596:                                         ; preds = %ELSE2593
+  %223 = fcmp oeq float %temp292.11, %101
+  %224 = fcmp olt float %101, %103
+  %225 = and i1 %223, %224
+  br i1 %225, label %ENDIF2594, label %ELSE2632
+
+ENDIF2594:                                        ; preds = %ELSE2788, %ELSE2785, %ELSE2782, %ELSE2779, %IF2775, %ELSE2761, %ELSE2758, %IF2757, %ELSE2704, %ELSE2686, %ELSE2671, %ELSE2668, %IF2667, %ELSE2632, %ELSE2596, %ELSE2593
+  %temp894.2 = phi float [ 0.000000e+00, %IF2667 ], [ 0.000000e+00, %ELSE2671 ], [ 0.000000e+00, %IF2757 ], [ 0.000000e+00, %ELSE2761 ], [ %temp894.0, %ELSE2758 ], [ 0.000000e+00, %IF2775 ], [ 0.000000e+00, %ELSE2779 ], [ 0.000000e+00, %ELSE2782 ], [ %.2848, %ELSE2788 ], [ 0.000000e+00, %ELSE2785 ], [ 0.000000e+00, %ELSE2593 ], [ 0.000000e+00, %ELSE2632 ], [ 0.000000e+00, %ELSE2704 ], [ 0.000000e+00, %ELSE2686 ], [ 0.000000e+00, %ELSE2668 ], [ 0.000000e+00, %ELSE2596 ]
+  %226 = fmul float %temp894.2, undef
+  br label %ENDIF2564
+
+ELSE2632:                                         ; preds = %ELSE2596
+  br i1 undef, label %ENDIF2594, label %ELSE2650
+
+ELSE2650:                                         ; preds = %ELSE2632
+  %227 = fcmp oeq float %temp292.11, %111
+  %228 = fcmp olt float %111, %112
+  %229 = and i1 %227, %228
+  br i1 %229, label %IF2667, label %ELSE2668
+
+IF2667:                                           ; preds = %ELSE2650
+  br i1 undef, label %ENDIF2594, label %ELSE2671
+
+ELSE2668:                                         ; preds = %ELSE2650
+  %230 = fcmp oeq float %temp292.11, %129
+  %231 = fcmp olt float %129, undef
+  %232 = and i1 %230, %231
+  br i1 %232, label %ENDIF2594, label %ELSE2686
+
+ELSE2671:                                         ; preds = %IF2667
+  br label %ENDIF2594
+
+ELSE2686:                                         ; preds = %ELSE2668
+  %233 = fcmp oeq float %temp292.11, %146
+  %234 = fcmp olt float %146, undef
+  %235 = and i1 %233, %234
+  br i1 %235, label %ENDIF2594, label %ELSE2704
+
+ELSE2704:                                         ; preds = %ELSE2686
+  %236 = fcmp oeq float %temp292.11, %181
+  %237 = fcmp olt float %181, undef
+  %238 = and i1 %236, %237
+  br i1 %238, label %ENDIF2594, label %ELSE2740
+
+ELSE2740:                                         ; preds = %ELSE2704
+  br i1 undef, label %IF2757, label %ELSE2758
+
+IF2757:                                           ; preds = %ELSE2740
+  br i1 undef, label %ENDIF2594, label %ELSE2761
+
+ELSE2758:                                         ; preds = %ELSE2740
+  br i1 undef, label %IF2775, label %ENDIF2594
+
+ELSE2761:                                         ; preds = %IF2757
+  br label %ENDIF2594
+
+IF2775:                                           ; preds = %ELSE2758
+  %239 = fcmp olt float undef, undef
+  br i1 %239, label %ENDIF2594, label %ELSE2779
+
+ELSE2779:                                         ; preds = %IF2775
+  br i1 undef, label %ENDIF2594, label %ELSE2782
+
+ELSE2782:                                         ; preds = %ELSE2779
+  br i1 undef, label %ENDIF2594, label %ELSE2785
+
+ELSE2785:                                         ; preds = %ELSE2782
+  %240 = fcmp olt float undef, 0.000000e+00
+  br i1 %240, label %ENDIF2594, label %ELSE2788
+
+ELSE2788:                                         ; preds = %ELSE2785
+  %241 = fcmp olt float 0.000000e+00, undef
+  %.2848 = select i1 %241, float -1.000000e+00, float 1.000000e+00
+  br label %ENDIF2594
+
+ELSE2797:                                         ; preds = %ENDIF2564
+  %242 = fsub float %8, undef
+  %243 = fsub float %9, undef
+  %244 = fsub float %10, undef
+  %245 = fmul float %242, undef
+  %246 = fmul float %243, undef
+  %247 = fmul float %244, undef
+  %248 = fsub float %11, undef
+  %249 = fsub float %12, undef
+  %250 = fsub float %13, undef
+  %251 = fmul float %248, undef
+  %252 = fmul float %249, undef
+  %253 = fmul float %250, undef
+  %254 = call float @llvm.minnum.f32(float %245, float %251)
+  %255 = call float @llvm.minnum.f32(float %246, float %252)
+  %256 = call float @llvm.maxnum.f32(float %247, float %253)
+  %257 = call float @llvm.maxnum.f32(float %254, float %255)
+  %258 = call float @llvm.maxnum.f32(float %257, float undef)
+  %259 = call float @llvm.minnum.f32(float undef, float %256)
+  %260 = fcmp ogt float %258, 0.000000e+00
+  %261 = fcmp olt float %258, 1.000000e+00
+  %262 = and i1 %260, %261
+  %263 = fcmp olt float %258, %259
+  %264 = and i1 %262, %263
+  br i1 %264, label %ENDIF2795, label %ELSE2800
+
+ENDIF2795:                                        ; preds = %ELSE2824, %ELSE2821, %ELSE2818, %ELSE2815, %ELSE2812, %ELSE2809, %ELSE2806, %ELSE2803, %ELSE2800, %ELSE2797, %ENDIF2564
+  br label %LOOP
+
+ELSE2800:                                         ; preds = %ELSE2797
+  br i1 undef, label %ENDIF2795, label %ELSE2803
+
+ELSE2803:                                         ; preds = %ELSE2800
+  %265 = fsub float %20, undef
+  %266 = fsub float %21, undef
+  %267 = fsub float %22, undef
+  %268 = fmul float %265, undef
+  %269 = fmul float %266, undef
+  %270 = fmul float %267, 0.000000e+00
+  %271 = fsub float %23, undef
+  %272 = fsub float %24, undef
+  %273 = fsub float %25, undef
+  %274 = fmul float %271, undef
+  %275 = fmul float %272, undef
+  %276 = fmul float %273, undef
+  %277 = call float @llvm.minnum.f32(float %268, float %274)
+  %278 = call float @llvm.maxnum.f32(float %269, float %275)
+  %279 = call float @llvm.maxnum.f32(float %270, float %276)
+  %280 = call float @llvm.maxnum.f32(float %277, float undef)
+  %281 = call float @llvm.maxnum.f32(float %280, float undef)
+  %282 = call float @llvm.minnum.f32(float undef, float %278)
+  %283 = call float @llvm.minnum.f32(float %282, float %279)
+  %284 = fcmp ogt float %281, 0.000000e+00
+  %285 = fcmp olt float %281, 1.000000e+00
+  %286 = and i1 %284, %285
+  %287 = fcmp olt float %281, %283
+  %288 = and i1 %286, %287
+  br i1 %288, label %ENDIF2795, label %ELSE2806
+
+ELSE2806:                                         ; preds = %ELSE2803
+  %289 = fsub float %26, undef
+  %290 = fsub float %27, undef
+  %291 = fsub float %28, undef
+  %292 = fmul float %289, undef
+  %293 = fmul float %290, 0.000000e+00
+  %294 = fmul float %291, undef
+  %295 = fsub float %29, undef
+  %296 = fmul float %295, undef
+  %297 = call float @llvm.minnum.f32(float %292, float %296)
+  %298 = call float @llvm.minnum.f32(float %293, float undef)
+  %299 = call float @llvm.maxnum.f32(float %294, float undef)
+  %300 = call float @llvm.maxnum.f32(float %297, float %298)
+  %301 = call float @llvm.maxnum.f32(float %300, float undef)
+  %302 = call float @llvm.minnum.f32(float undef, float %299)
+  %303 = fcmp ogt float %301, 0.000000e+00
+  %304 = fcmp olt float %301, 1.000000e+00
+  %305 = and i1 %303, %304
+  %306 = fcmp olt float %301, %302
+  %307 = and i1 %305, %306
+  br i1 %307, label %ENDIF2795, label %ELSE2809
+
+ELSE2809:                                         ; preds = %ELSE2806
+  br i1 undef, label %ENDIF2795, label %ELSE2812
+
+ELSE2812:                                         ; preds = %ELSE2809
+  br i1 undef, label %ENDIF2795, label %ELSE2815
+
+ELSE2815:                                         ; preds = %ELSE2812
+  br i1 undef, label %ENDIF2795, label %ELSE2818
+
+ELSE2818:                                         ; preds = %ELSE2815
+  br i1 undef, label %ENDIF2795, label %ELSE2821
+
+ELSE2821:                                         ; preds = %ELSE2818
+  %308 = fsub float %56, undef
+  %309 = fsub float %57, undef
+  %310 = fsub float %58, undef
+  %311 = fmul float %308, undef
+  %312 = fmul float %309, 0.000000e+00
+  %313 = fmul float %310, undef
+  %314 = fsub float %59, undef
+  %315 = fsub float %60, undef
+  %316 = fsub float %61, undef
+  %317 = fmul float %314, undef
+  %318 = fmul float %315, undef
+  %319 = fmul float %316, undef
+  %320 = call float @llvm.maxnum.f32(float %311, float %317)
+  %321 = call float @llvm.maxnum.f32(float %312, float %318)
+  %322 = call float @llvm.maxnum.f32(float %313, float %319)
+  %323 = call float @llvm.minnum.f32(float %320, float %321)
+  %324 = call float @llvm.minnum.f32(float %323, float %322)
+  %325 = fcmp ogt float undef, 0.000000e+00
+  %326 = fcmp olt float undef, 1.000000e+00
+  %327 = and i1 %325, %326
+  %328 = fcmp olt float undef, %324
+  %329 = and i1 %327, %328
+  br i1 %329, label %ENDIF2795, label %ELSE2824
+
+ELSE2824:                                         ; preds = %ELSE2821
+  %.2849 = select i1 undef, float 0.000000e+00, float 1.000000e+00
+  br label %ENDIF2795
+}
+
+; Function Attrs: nounwind readnone
+declare float @llvm.SI.load.const(<16 x i8>, i32) #1
+
+; Function Attrs: readnone
+declare float @llvm.AMDIL.fraction.(float) #2
+
+; Function Attrs: nounwind readnone
+declare float @llvm.sqrt.f32(float) #1
+
+; Function Attrs: nounwind readnone
+declare float @llvm.minnum.f32(float, float) #1
+
+; Function Attrs: nounwind readnone
+declare float @llvm.maxnum.f32(float, float) #1
+
+; Function Attrs: readnone
+declare float @llvm.AMDGPU.lrp(float, float, float) #2
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
+
+attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" }
+attributes #1 = { nounwind readnone }
+attributes #2 = { readnone }
diff --git a/test/CodeGen/R600/si-triv-disjoint-mem-access.ll b/test/CodeGen/R600/si-triv-disjoint-mem-access.ll
index f6dcb388248a..5a6129aaa3fa 100644
--- a/test/CodeGen/R600/si-triv-disjoint-mem-access.ll
+++ b/test/CodeGen/R600/si-triv-disjoint-mem-access.ll
@@ -14,14 +14,14 @@ declare void @llvm.AMDGPU.barrier.local() #2
 ; CI-NEXT: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:8
 ; CI: buffer_store_dword
 define void @reorder_local_load_global_store_local_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
-  %ptr0 = load i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
+  %ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
 
-  %ptr1 = getelementptr inbounds i32 addrspace(3)* %ptr0, i32 1
-  %ptr2 = getelementptr inbounds i32 addrspace(3)* %ptr0, i32 2
+  %ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1
+  %ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 2
 
-  %tmp1 = load i32 addrspace(3)* %ptr1, align 4
+  %tmp1 = load i32, i32 addrspace(3)* %ptr1, align 4
   store i32 99, i32 addrspace(1)* %gptr, align 4
-  %tmp2 = load i32 addrspace(3)* %ptr2, align 4
+  %tmp2 = load i32, i32 addrspace(3)* %ptr2, align 4
 
   %add = add nsw i32 %tmp1, %tmp2
 
@@ -34,14 +34,14 @@ define void @reorder_local_load_global_store_local_load(i32 addrspace(1)* %out,
 ; CI: buffer_store_dword
 ; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:8
 define void @no_reorder_local_load_volatile_global_store_local_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
-  %ptr0 = load i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
+  %ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
 
-  %ptr1 = getelementptr inbounds i32 addrspace(3)* %ptr0, i32 1
-  %ptr2 = getelementptr inbounds i32 addrspace(3)* %ptr0, i32 2
+  %ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1
+  %ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 2
 
-  %tmp1 = load i32 addrspace(3)* %ptr1, align 4
+  %tmp1 = load i32, i32 addrspace(3)* %ptr1, align 4
   store volatile i32 99, i32 addrspace(1)* %gptr, align 4
-  %tmp2 = load i32 addrspace(3)* %ptr2, align 4
+  %tmp2 = load i32, i32 addrspace(3)* %ptr2, align 4
 
   %add = add nsw i32 %tmp1, %tmp2
 
@@ -54,15 +54,15 @@ define void @no_reorder_local_load_volatile_global_store_local_load(i32 addrspac
 ; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:8
 ; CI: buffer_store_dword
 define void @no_reorder_barrier_local_load_global_store_local_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
-  %ptr0 = load i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
+  %ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
 
-  %ptr1 = getelementptr inbounds i32 addrspace(3)* %ptr0, i32 1
-  %ptr2 = getelementptr inbounds i32 addrspace(3)* %ptr0, i32 2
+  %ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1
+  %ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 2
 
-  %tmp1 = load i32 addrspace(3)* %ptr1, align 4
+  %tmp1 = load i32, i32 addrspace(3)* %ptr1, align 4
   store i32 99, i32 addrspace(1)* %gptr, align 4
   call void @llvm.AMDGPU.barrier.local() #2
-  %tmp2 = load i32 addrspace(3)* %ptr2, align 4
+  %tmp2 = load i32, i32 addrspace(3)* %ptr2, align 4
 
   %add = add nsw i32 %tmp1, %tmp2
 
@@ -79,14 +79,14 @@ define void @no_reorder_barrier_local_load_global_store_local_load(i32 addrspace
 ; CI: buffer_load_dword
 ; CI: buffer_store_dword
 define void @no_reorder_constant_load_global_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
-  %ptr0 = load i32 addrspace(2)* addrspace(3)* @stored_constant_ptr, align 8
+  %ptr0 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(3)* @stored_constant_ptr, align 8
 
-  %ptr1 = getelementptr inbounds i32 addrspace(2)* %ptr0, i64 1
-  %ptr2 = getelementptr inbounds i32 addrspace(2)* %ptr0, i64 2
+  %ptr1 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 1
+  %ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 2
 
-  %tmp1 = load i32 addrspace(2)* %ptr1, align 4
+  %tmp1 = load i32, i32 addrspace(2)* %ptr1, align 4
   store i32 99, i32 addrspace(1)* %gptr, align 4
-  %tmp2 = load i32 addrspace(2)* %ptr2, align 4
+  %tmp2 = load i32, i32 addrspace(2)* %ptr2, align 4
 
   %add = add nsw i32 %tmp1, %tmp2
 
@@ -94,22 +94,20 @@ define void @no_reorder_constant_load_global_store_constant_load(i32 addrspace(1
   ret void
 }
 
-; XXX: Should be able to reorder this, but the laods count as ordered
-
 ; FUNC-LABEL: @reorder_constant_load_local_store_constant_load
 ; CI: buffer_load_dword
-; CI: ds_write_b32
 ; CI: buffer_load_dword
+; CI: ds_write_b32
 ; CI: buffer_store_dword
 define void @reorder_constant_load_local_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(3)* %lptr) #0 {
-  %ptr0 = load i32 addrspace(2)* addrspace(3)* @stored_constant_ptr, align 8
+  %ptr0 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(3)* @stored_constant_ptr, align 8
 
-  %ptr1 = getelementptr inbounds i32 addrspace(2)* %ptr0, i64 1
-  %ptr2 = getelementptr inbounds i32 addrspace(2)* %ptr0, i64 2
+  %ptr1 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 1
+  %ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 2
 
-  %tmp1 = load i32 addrspace(2)* %ptr1, align 4
+  %tmp1 = load i32, i32 addrspace(2)* %ptr1, align 4
   store i32 99, i32 addrspace(3)* %lptr, align 4
-  %tmp2 = load i32 addrspace(2)* %ptr2, align 4
+  %tmp2 = load i32, i32 addrspace(2)* %ptr2, align 4
 
   %add = add nsw i32 %tmp1, %tmp2
 
@@ -124,12 +122,12 @@ define void @reorder_constant_load_local_store_constant_load(i32 addrspace(1)* %
 ; CI: ds_write_b32
 ; CI: buffer_store_dword
 define void @reorder_smrd_load_local_store_smrd_load(i32 addrspace(1)* %out, i32 addrspace(3)* noalias %lptr, i32 addrspace(2)* %ptr0) #0 {
-  %ptr1 = getelementptr inbounds i32 addrspace(2)* %ptr0, i64 1
-  %ptr2 = getelementptr inbounds i32 addrspace(2)* %ptr0, i64 2
+  %ptr1 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 1
+  %ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 2
 
-  %tmp1 = load i32 addrspace(2)* %ptr1, align 4
+  %tmp1 = load i32, i32 addrspace(2)* %ptr1, align 4
   store i32 99, i32 addrspace(3)* %lptr, align 4
-  %tmp2 = load i32 addrspace(2)* %ptr2, align 4
+  %tmp2 = load i32, i32 addrspace(2)* %ptr2, align 4
 
   %add = add nsw i32 %tmp1, %tmp2
 
@@ -143,12 +141,12 @@ define void @reorder_smrd_load_local_store_smrd_load(i32 addrspace(1)* %out, i32
 ; CI: ds_write_b32
 ; CI: buffer_store_dword
 define void @reorder_global_load_local_store_global_load(i32 addrspace(1)* %out, i32 addrspace(3)* %lptr, i32 addrspace(1)* %ptr0) #0 {
-  %ptr1 = getelementptr inbounds i32 addrspace(1)* %ptr0, i64 1
-  %ptr2 = getelementptr inbounds i32 addrspace(1)* %ptr0, i64 2
+  %ptr1 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i64 1
+  %ptr2 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i64 2
 
-  %tmp1 = load i32 addrspace(1)* %ptr1, align 4
+  %tmp1 = load i32, i32 addrspace(1)* %ptr1, align 4
   store i32 99, i32 addrspace(3)* %lptr, align 4
-  %tmp2 = load i32 addrspace(1)* %ptr2, align 4
+  %tmp2 = load i32, i32 addrspace(1)* %ptr2, align 4
 
   %add = add nsw i32 %tmp1, %tmp2
 
@@ -165,15 +163,15 @@ define void @reorder_global_load_local_store_global_load(i32 addrspace(1)* %out,
 ; CI: buffer_store_dword
 ; CI: s_endpgm
 define void @reorder_local_offsets(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* noalias nocapture readnone %gptr, i32 addrspace(3)* noalias nocapture %ptr0) #0 {
-  %ptr1 = getelementptr inbounds i32 addrspace(3)* %ptr0, i32 3
-  %ptr2 = getelementptr inbounds i32 addrspace(3)* %ptr0, i32 100
-  %ptr3 = getelementptr inbounds i32 addrspace(3)* %ptr0, i32 101
+  %ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 3
+  %ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 100
+  %ptr3 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 101
 
   store i32 123, i32 addrspace(3)* %ptr1, align 4
-  %tmp1 = load i32 addrspace(3)* %ptr2, align 4
-  %tmp2 = load i32 addrspace(3)* %ptr3, align 4
+  %tmp1 = load i32, i32 addrspace(3)* %ptr2, align 4
+  %tmp2 = load i32, i32 addrspace(3)* %ptr3, align 4
   store i32 123, i32 addrspace(3)* %ptr2, align 4
-  %tmp3 = load i32 addrspace(3)* %ptr1, align 4
+  %tmp3 = load i32, i32 addrspace(3)* %ptr1, align 4
   store i32 789, i32 addrspace(3)* %ptr3, align 4
 
   %add.0 = add nsw i32 %tmp2, %tmp1
@@ -191,15 +189,15 @@ define void @reorder_local_offsets(i32 addrspace(1)* nocapture %out, i32 addrspa
 ; CI: buffer_store_dword
 ; CI: s_endpgm
 define void @reorder_global_offsets(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* noalias nocapture readnone %gptr, i32 addrspace(1)* noalias nocapture %ptr0) #0 {
-  %ptr1 = getelementptr inbounds i32 addrspace(1)* %ptr0, i32 3
-  %ptr2 = getelementptr inbounds i32 addrspace(1)* %ptr0, i32 100
-  %ptr3 = getelementptr inbounds i32 addrspace(1)* %ptr0, i32 101
+  %ptr1 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 3
+  %ptr2 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 100
+  %ptr3 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 101
 
   store i32 123, i32 addrspace(1)* %ptr1, align 4
-  %tmp1 = load i32 addrspace(1)* %ptr2, align 4
-  %tmp2 = load i32 addrspace(1)* %ptr3, align 4
+  %tmp1 = load i32, i32 addrspace(1)* %ptr2, align 4
+  %tmp2 = load i32, i32 addrspace(1)* %ptr3, align 4
   store i32 123, i32 addrspace(1)* %ptr2, align 4
-  %tmp3 = load i32 addrspace(1)* %ptr1, align 4
+  %tmp3 = load i32, i32 addrspace(1)* %ptr1, align 4
   store i32 789, i32 addrspace(1)* %ptr3, align 4
 
   %add.0 = add nsw i32 %tmp2, %tmp1
@@ -213,19 +211,19 @@ define void @reorder_global_offsets(i32 addrspace(1)* nocapture %out, i32 addrsp
 ; XCI: TBUFFER_STORE_FORMAT
 ; XCI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}}, 0x8
 ; define void @reorder_local_load_tbuffer_store_local_load(i32 addrspace(1)* %out, i32 %a1, i32 %vaddr) #1 {
-;   %ptr0 = load i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
+;   %ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
 
-;   %ptr1 = getelementptr inbounds i32 addrspace(3)* %ptr0, i32 1
-;   %ptr2 = getelementptr inbounds i32 addrspace(3)* %ptr0, i32 2
+;   %ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1
+;   %ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 2
 
-;   %tmp1 = load i32 addrspace(3)* %ptr1, align 4
+;   %tmp1 = load i32, i32 addrspace(3)* %ptr1, align 4
 
 ;   %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
 ;   call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata,
 ;         i32 4, i32 %vaddr, i32 0, i32 32, i32 14, i32 4, i32 1, i32 0, i32 1,
 ;         i32 1, i32 0)
 
-;   %tmp2 = load i32 addrspace(3)* %ptr2, align 4
+;   %tmp2 = load i32, i32 addrspace(3)* %ptr2, align 4
 
 ;   %add = add nsw i32 %tmp1, %tmp2
 
diff --git a/test/CodeGen/R600/si-vector-hang.ll b/test/CodeGen/R600/si-vector-hang.ll
index 61812c61ba19..94c47fe3c600 100644
--- a/test/CodeGen/R600/si-vector-hang.ll
+++ b/test/CodeGen/R600/si-vector-hang.ll
@@ -17,52 +17,52 @@ target triple = "r600--"
 ; Function Attrs: nounwind
 define void @test_8_min_char(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture readonly %in0, i8 addrspace(1)* nocapture readonly %in1) #0 {
 entry:
-  %0 = load i8 addrspace(1)* %in0, align 1
+  %0 = load i8, i8 addrspace(1)* %in0, align 1
   %1 = insertelement <8 x i8> undef, i8 %0, i32 0
-  %arrayidx2.i.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 1
-  %2 = load i8 addrspace(1)* %arrayidx2.i.i, align 1
+  %arrayidx2.i.i = getelementptr inbounds i8, i8 addrspace(1)* %in0, i64 1
+  %2 = load i8, i8 addrspace(1)* %arrayidx2.i.i, align 1
   %3 = insertelement <8 x i8> %1, i8 %2, i32 1
-  %arrayidx6.i.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 2
-  %4 = load i8 addrspace(1)* %arrayidx6.i.i, align 1
+  %arrayidx6.i.i = getelementptr inbounds i8, i8 addrspace(1)* %in0, i64 2
+  %4 = load i8, i8 addrspace(1)* %arrayidx6.i.i, align 1
   %5 = insertelement <8 x i8> %3, i8 %4, i32 2
-  %arrayidx10.i.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 3
-  %6 = load i8 addrspace(1)* %arrayidx10.i.i, align 1
+  %arrayidx10.i.i = getelementptr inbounds i8, i8 addrspace(1)* %in0, i64 3
+  %6 = load i8, i8 addrspace(1)* %arrayidx10.i.i, align 1
   %7 = insertelement <8 x i8> %5, i8 %6, i32 3
-  %arrayidx.i.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 4
-  %8 = load i8 addrspace(1)* %arrayidx.i.i, align 1
+  %arrayidx.i.i = getelementptr inbounds i8, i8 addrspace(1)* %in0, i64 4
+  %8 = load i8, i8 addrspace(1)* %arrayidx.i.i, align 1
   %9 = insertelement <8 x i8> undef, i8 %8, i32 0
-  %arrayidx2.i9.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 5
-  %10 = load i8 addrspace(1)* %arrayidx2.i9.i, align 1
+  %arrayidx2.i9.i = getelementptr inbounds i8, i8 addrspace(1)* %in0, i64 5
+  %10 = load i8, i8 addrspace(1)* %arrayidx2.i9.i, align 1
   %11 = insertelement <8 x i8> %9, i8 %10, i32 1
-  %arrayidx6.i11.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 6
-  %12 = load i8 addrspace(1)* %arrayidx6.i11.i, align 1
+  %arrayidx6.i11.i = getelementptr inbounds i8, i8 addrspace(1)* %in0, i64 6
+  %12 = load i8, i8 addrspace(1)* %arrayidx6.i11.i, align 1
   %13 = insertelement <8 x i8> %11, i8 %12, i32 2
-  %arrayidx10.i13.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 7
-  %14 = load i8 addrspace(1)* %arrayidx10.i13.i, align 1
+  %arrayidx10.i13.i = getelementptr inbounds i8, i8 addrspace(1)* %in0, i64 7
+  %14 = load i8, i8 addrspace(1)* %arrayidx10.i13.i, align 1
   %15 = insertelement <8 x i8> %13, i8 %14, i32 3
   %vecinit5.i = shufflevector <8 x i8> %7, <8 x i8> %15, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
-  %16 = load i8 addrspace(1)* %in1, align 1
+  %16 = load i8, i8 addrspace(1)* %in1, align 1
   %17 = insertelement <8 x i8> undef, i8 %16, i32 0
-  %arrayidx2.i.i4 = getelementptr inbounds i8 addrspace(1)* %in1, i64 1
-  %18 = load i8 addrspace(1)* %arrayidx2.i.i4, align 1
+  %arrayidx2.i.i4 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 1
+  %18 = load i8, i8 addrspace(1)* %arrayidx2.i.i4, align 1
   %19 = insertelement <8 x i8> %17, i8 %18, i32 1
-  %arrayidx6.i.i5 = getelementptr inbounds i8 addrspace(1)* %in1, i64 2
-  %20 = load i8 addrspace(1)* %arrayidx6.i.i5, align 1
+  %arrayidx6.i.i5 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 2
+  %20 = load i8, i8 addrspace(1)* %arrayidx6.i.i5, align 1
   %21 = insertelement <8 x i8> %19, i8 %20, i32 2
-  %arrayidx10.i.i6 = getelementptr inbounds i8 addrspace(1)* %in1, i64 3
-  %22 = load i8 addrspace(1)* %arrayidx10.i.i6, align 1
+  %arrayidx10.i.i6 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 3
+  %22 = load i8, i8 addrspace(1)* %arrayidx10.i.i6, align 1
   %23 = insertelement <8 x i8> %21, i8 %22, i32 3
-  %arrayidx.i.i7 = getelementptr inbounds i8 addrspace(1)* %in1, i64 4
-  %24 = load i8 addrspace(1)* %arrayidx.i.i7, align 1
+  %arrayidx.i.i7 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 4
+  %24 = load i8, i8 addrspace(1)* %arrayidx.i.i7, align 1
   %25 = insertelement <8 x i8> undef, i8 %24, i32 0
-  %arrayidx2.i9.i8 = getelementptr inbounds i8 addrspace(1)* %in1, i64 5
-  %26 = load i8 addrspace(1)* %arrayidx2.i9.i8, align 1
+  %arrayidx2.i9.i8 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 5
+  %26 = load i8, i8 addrspace(1)* %arrayidx2.i9.i8, align 1
   %27 = insertelement <8 x i8> %25, i8 %26, i32 1
-  %arrayidx6.i11.i9 = getelementptr inbounds i8 addrspace(1)* %in1, i64 6
-  %28 = load i8 addrspace(1)* %arrayidx6.i11.i9, align 1
+  %arrayidx6.i11.i9 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 6
+  %28 = load i8, i8 addrspace(1)* %arrayidx6.i11.i9, align 1
   %29 = insertelement <8 x i8> %27, i8 %28, i32 2
-  %arrayidx10.i13.i10 = getelementptr inbounds i8 addrspace(1)* %in1, i64 7
-  %30 = load i8 addrspace(1)* %arrayidx10.i13.i10, align 1
+  %arrayidx10.i13.i10 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 7
+  %30 = load i8, i8 addrspace(1)* %arrayidx10.i13.i10, align 1
   %31 = insertelement <8 x i8> %29, i8 %30, i32 3
   %vecinit5.i11 = shufflevector <8 x i8> %23, <8 x i8> %31, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
   %cmp.i = icmp slt <8 x i8> %vecinit5.i, %vecinit5.i11
@@ -70,25 +70,25 @@ entry:
   %32 = extractelement <8 x i8> %cond.i, i32 0
   store i8 %32, i8 addrspace(1)* %out, align 1
   %33 = extractelement <8 x i8> %cond.i, i32 1
-  %arrayidx2.i.i.i = getelementptr inbounds i8 addrspace(1)* %out, i64 1
+  %arrayidx2.i.i.i = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 1
   store i8 %33, i8 addrspace(1)* %arrayidx2.i.i.i, align 1
   %34 = extractelement <8 x i8> %cond.i, i32 2
-  %arrayidx.i.i.i = getelementptr inbounds i8 addrspace(1)* %out, i64 2
+  %arrayidx.i.i.i = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 2
   store i8 %34, i8 addrspace(1)* %arrayidx.i.i.i, align 1
   %35 = extractelement <8 x i8> %cond.i, i32 3
-  %arrayidx2.i6.i.i = getelementptr inbounds i8 addrspace(1)* %out, i64 3
+  %arrayidx2.i6.i.i = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 3
   store i8 %35, i8 addrspace(1)* %arrayidx2.i6.i.i, align 1
-  %arrayidx.i.i3 = getelementptr inbounds i8 addrspace(1)* %out, i64 4
+  %arrayidx.i.i3 = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 4
   %36 = extractelement <8 x i8> %cond.i, i32 4
   store i8 %36, i8 addrspace(1)* %arrayidx.i.i3, align 1
   %37 = extractelement <8 x i8> %cond.i, i32 5
-  %arrayidx2.i.i6.i = getelementptr inbounds i8 addrspace(1)* %out, i64 5
+  %arrayidx2.i.i6.i = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 5
   store i8 %37, i8 addrspace(1)* %arrayidx2.i.i6.i, align 1
   %38 = extractelement <8 x i8> %cond.i, i32 6
-  %arrayidx.i.i7.i = getelementptr inbounds i8 addrspace(1)* %out, i64 6
+  %arrayidx.i.i7.i = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 6
   store i8 %38, i8 addrspace(1)* %arrayidx.i.i7.i, align 1
   %39 = extractelement <8 x i8> %cond.i, i32 7
-  %arrayidx2.i6.i8.i = getelementptr inbounds i8 addrspace(1)* %out, i64 7
+  %arrayidx2.i6.i8.i = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 7
   store i8 %39, i8 addrspace(1)* %arrayidx2.i6.i8.i, align 1
   ret void
 }
diff --git a/test/CodeGen/R600/sign_extend.ll b/test/CodeGen/R600/sign_extend.ll
index 9550c2a7f061..06bee114c23a 100644
--- a/test/CodeGen/R600/sign_extend.ll
+++ b/test/CodeGen/R600/sign_extend.ll
@@ -24,8 +24,9 @@ entry:
 }
 
 ; SI-LABEL: {{^}}s_sext_i1_to_i64:
-; SI: v_cndmask_b32_e64
-; SI: v_cndmask_b32_e64
+; SI: v_cndmask_b32_e64 v[[LOREG:[0-9]+]], 0, -1, vcc
+; SI: v_mov_b32_e32 v[[HIREG:[0-9]+]], v[[LOREG]]
+; SI: buffer_store_dwordx2 v{{\[}}[[LOREG]]:[[HIREG]]{{\]}}
 ; SI: s_endpgm
 define void @s_sext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
   %cmp = icmp eq i32 %a, %b
@@ -47,7 +48,7 @@ define void @s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a) nounwind {
 ; SI: v_ashr
 ; SI: s_endpgm
 define void @v_sext_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
-  %val = load i32 addrspace(1)* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %sext = sext i32 %val to i64
   store i64 %sext, i64 addrspace(1)* %out, align 8
   ret void
diff --git a/test/CodeGen/R600/simplify-demanded-bits-build-pair.ll b/test/CodeGen/R600/simplify-demanded-bits-build-pair.ll
index 28a413cd1b3c..dffee70b6b02 100644
--- a/test/CodeGen/R600/simplify-demanded-bits-build-pair.ll
+++ b/test/CodeGen/R600/simplify-demanded-bits-build-pair.ll
@@ -22,16 +22,16 @@ define void @trunc_select_i64(i32 addrspace(1)* %out, i64 %a, i64 %b, i32 %c) {
 define void @trunc_load_alloca_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) {
   %idx = add i32 %a, %b
   %alloca = alloca i64, i32 4
-  %gep0 = getelementptr i64* %alloca, i64 0
-  %gep1 = getelementptr i64* %alloca, i64 1
-  %gep2 = getelementptr i64* %alloca, i64 2
-  %gep3 = getelementptr i64* %alloca, i64 3
+  %gep0 = getelementptr i64, i64* %alloca, i64 0
+  %gep1 = getelementptr i64, i64* %alloca, i64 1
+  %gep2 = getelementptr i64, i64* %alloca, i64 2
+  %gep3 = getelementptr i64, i64* %alloca, i64 3
   store i64 24, i64* %gep0, align 8
   store i64 9334, i64* %gep1, align 8
   store i64 3935, i64* %gep2, align 8
   store i64 9342, i64* %gep3, align 8
-  %gep = getelementptr i64* %alloca, i32 %idx
-  %load = load i64* %gep, align 8
+  %gep = getelementptr i64, i64* %alloca, i32 %idx
+  %load = load i64, i64* %gep, align 8
   %mask = and i64 %load, 4294967296
   %add = add i64 %mask, -1
   store i64 %add, i64 addrspace(1)* %out, align 4
diff --git a/test/CodeGen/R600/sint_to_fp.f64.ll b/test/CodeGen/R600/sint_to_fp.f64.ll
index 77844a6aa384..da4e91db3a38 100644
--- a/test/CodeGen/R600/sint_to_fp.f64.ll
+++ b/test/CodeGen/R600/sint_to_fp.f64.ll
@@ -10,12 +10,13 @@ define void @sint_to_fp_i32_to_f64(double addrspace(1)* %out, i32 %in) {
   ret void
 }
 
+; FIXME: select on 0, 0
 ; SI-LABEL: {{^}}sint_to_fp_i1_f64:
 ; SI: v_cmp_eq_i32_e64 [[CMP:s\[[0-9]+:[0-9]\]]],
 ; We can't fold the SGPRs into v_cndmask_b32_e64, because it already
 ; uses an SGPR for [[CMP]]
 ; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, v{{[0-9]+}}, [[CMP]]
-; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, v{{[0-9]+}}, [[CMP]]
+; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 0, [[CMP]]
 ; SI: buffer_store_dwordx2
 ; SI: s_endpgm
 define void @sint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) {
@@ -52,8 +53,8 @@ define void @s_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 %in) {
 ; SI: buffer_store_dwordx2 [[RESULT]]
 define void @v_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep = getelementptr i64 addrspace(1)* %in, i32 %tid
-  %val = load i64 addrspace(1)* %gep, align 8
+  %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %val = load i64, i64 addrspace(1)* %gep, align 8
   %result = sitofp i64 %val to double
   store double %result, double addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/sint_to_fp.ll b/test/CodeGen/R600/sint_to_fp.ll
index 6a291cfe9269..8506441d1361 100644
--- a/test/CodeGen/R600/sint_to_fp.ll
+++ b/test/CodeGen/R600/sint_to_fp.ll
@@ -35,7 +35,7 @@ define void @sint_to_fp_v2i32(<2 x float> addrspace(1)* %out, <2 x i32> %in) {
 ; SI: v_cvt_f32_i32_e32
 ; SI: v_cvt_f32_i32_e32
 define void @sint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %value = load <4 x i32> addrspace(1) * %in
+  %value = load <4 x i32>, <4 x i32> addrspace(1) * %in
   %result = sitofp <4 x i32> %value to <4 x float>
   store <4 x float> %result, <4 x float> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/smrd.ll b/test/CodeGen/R600/smrd.ll
index a66ad0201bf9..b0c18ca5959c 100644
--- a/test/CodeGen/R600/smrd.ll
+++ b/test/CodeGen/R600/smrd.ll
@@ -1,65 +1,73 @@
-; RUN: llc < %s -march=amdgcn -mcpu=SI -show-mc-encoding -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -march=amdgcn -mcpu=SI -show-mc-encoding -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=GCN %s
+; RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=GCN %s
 
 ; SMRD load with an immediate offset.
-; CHECK-LABEL: {{^}}smrd0:
-; CHECK: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
+; GCN-LABEL: {{^}}smrd0:
+; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
+; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4
 define void @smrd0(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
 entry:
-  %0 = getelementptr i32 addrspace(2)* %ptr, i64 1
-  %1 = load i32 addrspace(2)* %0
+  %0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 1
+  %1 = load i32, i32 addrspace(2)* %0
   store i32 %1, i32 addrspace(1)* %out
   ret void
 }
 
 ; SMRD load with the largest possible immediate offset.
-; CHECK-LABEL: {{^}}smrd1:
-; CHECK: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
+; GCN-LABEL: {{^}}smrd1:
+; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
+; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
 define void @smrd1(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
 entry:
-  %0 = getelementptr i32 addrspace(2)* %ptr, i64 255
-  %1 = load i32 addrspace(2)* %0
+  %0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 255
+  %1 = load i32, i32 addrspace(2)* %0
   store i32 %1, i32 addrspace(1)* %out
   ret void
 }
 
 ; SMRD load with an offset greater than the largest possible immediate.
-; CHECK-LABEL: {{^}}smrd2:
-; CHECK: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
-; CHECK: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
-; CHECK: s_endpgm
+; GCN-LABEL: {{^}}smrd2:
+; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
+; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
+; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
+; GCN: s_endpgm
 define void @smrd2(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
 entry:
-  %0 = getelementptr i32 addrspace(2)* %ptr, i64 256
-  %1 = load i32 addrspace(2)* %0
+  %0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 256
+  %1 = load i32, i32 addrspace(2)* %0
   store i32 %1, i32 addrspace(1)* %out
   ret void
 }
 
 ; SMRD load with a 64-bit offset
-; CHECK-LABEL: {{^}}smrd3:
-; CHECK-DAG: s_mov_b32 s[[SHI:[0-9]+]], 4
-; CHECK-DAG: s_mov_b32 s[[SLO:[0-9]+]], 0 ;
-; FIXME: We don't need to copy these values to VGPRs
-; CHECK-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]]
-; CHECK-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]]
+; GCN-LABEL: {{^}}smrd3:
+; FIXME: There are too many copies here because we don't fold immediates
+;        through REG_SEQUENCE
+; SI: s_mov_b32 s[[SLO:[0-9]+]], 0 ;
+; SI: s_mov_b32 s[[SHI:[0-9]+]], 4
+; SI: s_mov_b32 s[[SSLO:[0-9]+]], s[[SLO]]
+; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SSLO]]
+; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]]
 ; FIXME: We should be able to use s_load_dword here
-; CHECK: buffer_load_dword v{{[0-9]+}}, v{{\[}}[[VLO]]:[[VHI]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64
-; CHECK: s_endpgm
+; SI: buffer_load_dword v{{[0-9]+}}, v{{\[}}[[VLO]]:[[VHI]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64
+; TODO: Add VI checks
+; GCN: s_endpgm
 define void @smrd3(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
 entry:
-  %0 = getelementptr i32 addrspace(2)* %ptr, i64 4294967296 ; 2 ^ 32
-  %1 = load i32 addrspace(2)* %0
+  %0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 4294967296 ; 2 ^ 32
+  %1 = load i32, i32 addrspace(2)* %0
   store i32 %1, i32 addrspace(1)* %out
   ret void
 }
 
 ; SMRD load using the load.const intrinsic with an immediate offset
-; CHECK-LABEL: {{^}}smrd_load_const0:
-; CHECK: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04
+; GCN-LABEL: {{^}}smrd_load_const0:
+; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04
+; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10
 define void @smrd_load_const0(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
 main_body:
-  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
-  %21 = load <16 x i8> addrspace(2)* %20
+  %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
+  %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20
   %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
   call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
   ret void
@@ -67,12 +75,13 @@ main_body:
 
 ; SMRD load using the load.const intrinsic with the largest possible immediate
 ; offset.
-; CHECK-LABEL: {{^}}smrd_load_const1:
-; CHECK: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
+; GCN-LABEL: {{^}}smrd_load_const1:
+; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
+; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
 define void @smrd_load_const1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
 main_body:
-  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
-  %21 = load <16 x i8> addrspace(2)* %20
+  %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
+  %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20
   %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1020)
   call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
   ret void
@@ -80,13 +89,14 @@ main_body:
 ; SMRD load using the load.const intrinsic with an offset greater than the
 ; largets possible immediate.
 ; immediate offset.
-; CHECK-LABEL: {{^}}smrd_load_const2:
-; CHECK: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
-; CHECK: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
+; GCN-LABEL: {{^}}smrd_load_const2:
+; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
+; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
+; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
 define void @smrd_load_const2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
 main_body:
-  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
-  %21 = load <16 x i8> addrspace(2)* %20
+  %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
+  %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20
   %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1024)
   call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
   ret void
diff --git a/test/CodeGen/R600/split-scalar-i64-add.ll b/test/CodeGen/R600/split-scalar-i64-add.ll
index ec50fd9f4c1e..46409cdfae1c 100644
--- a/test/CodeGen/R600/split-scalar-i64-add.ll
+++ b/test/CodeGen/R600/split-scalar-i64-add.ll
@@ -37,8 +37,8 @@ define void @imp_def_vcc_split_i64_add_1(i64 addrspace(1)* %out, i32 %val0, i64
 ; SI: v_addc_u32
 define void @imp_def_vcc_split_i64_add_2(i64 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %val0, i64 %val1) {
   %tid = call i32 @llvm.r600.read.tidig.x() readnone
-  %gep = getelementptr i32 addrspace(1)* %in, i32 %tid
-  %load = load i32 addrspace(1)* %gep
+  %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
+  %load = load i32, i32 addrspace(1)* %gep
   %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0
   %vec.1 = insertelement <2 x i32> %vec.0, i32 %load, i32 1
   %bc = bitcast <2 x i32> %vec.1 to i64
diff --git a/test/CodeGen/R600/sra.ll b/test/CodeGen/R600/sra.ll
index d6c6ccd28382..bcbc32f4c053 100644
--- a/test/CodeGen/R600/sra.ll
+++ b/test/CodeGen/R600/sra.ll
@@ -15,9 +15,9 @@
 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 
 define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
-  %a = load <2 x i32> addrspace(1) * %in
-  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32>, <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
   %result = ashr <2 x i32> %a, %b
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
   ret void
@@ -42,9 +42,9 @@ define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %i
 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 
 define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
-  %a = load <4 x i32> addrspace(1) * %in
-  %b = load <4 x i32> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
+  %a = load <4 x i32>, <4 x i32> addrspace(1) * %in
+  %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
   %result = ashr <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
@@ -89,9 +89,9 @@ entry:
 
 define void @ashr_i64_2(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
 entry:
-  %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1
-  %a = load i64 addrspace(1) * %in
-  %b = load i64 addrspace(1) * %b_ptr
+  %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
+  %a = load i64, i64 addrspace(1) * %in
+  %b = load i64, i64 addrspace(1) * %b_ptr
   %result = ashr i64 %a, %b
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -132,9 +132,9 @@ entry:
 ;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
 
 define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
-  %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1
-  %a = load <2 x i64> addrspace(1) * %in
-  %b = load <2 x i64> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1
+  %a = load <2 x i64>, <2 x i64> addrspace(1) * %in
+  %b = load <2 x i64>, <2 x i64> addrspace(1) * %b_ptr
   %result = ashr <2 x i64> %a, %b
   store <2 x i64> %result, <2 x i64> addrspace(1)* %out
   ret void
@@ -203,9 +203,9 @@ define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %i
 ;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
 
 define void @ashr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1
-  %a = load <4 x i64> addrspace(1) * %in
-  %b = load <4 x i64> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
+  %a = load <4 x i64>, <4 x i64> addrspace(1) * %in
+  %b = load <4 x i64>, <4 x i64> addrspace(1) * %b_ptr
   %result = ashr <4 x i64> %a, %b
   store <4 x i64> %result, <4 x i64> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/srem.ll b/test/CodeGen/R600/srem.ll
index 2aa8c7452542..c78fd549b316 100644
--- a/test/CodeGen/R600/srem.ll
+++ b/test/CodeGen/R600/srem.ll
@@ -1,51 +1,112 @@
-; RUN: llc -march=amdgcn -mcpu=SI < %s
-; RUN: llc -march=amdgcn -mcpu=tonga < %s
+; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 ; RUN: llc -march=r600 -mcpu=redwood < %s
 
 define void @srem_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in
-  %den = load i32 addrspace(1) * %den_ptr
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in
+  %den = load i32, i32 addrspace(1) * %den_ptr
   %result = srem i32 %num, %den
   store i32 %result, i32 addrspace(1)* %out
   ret void
 }
 
 define void @srem_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %num = load i32 addrspace(1) * %in
+  %num = load i32, i32 addrspace(1) * %in
   %result = srem i32 %num, 4
   store i32 %result, i32 addrspace(1)* %out
   ret void
 }
 
+; FUNC-LABEL: {{^}}srem_i32_7:
+; SI: v_mov_b32_e32 [[MAGIC:v[0-9]+]], 0x92492493
+; SI: v_mul_hi_i32 {{v[0-9]+}}, [[MAGIC]],
+; SI: v_mul_lo_i32
+; SI: v_sub_i32
+; SI: s_endpgm
+define void @srem_i32_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
+  %num = load i32, i32 addrspace(1) * %in
+  %result = srem i32 %num, 7
+  store i32 %result, i32 addrspace(1)* %out
+  ret void
+}
+
 define void @srem_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %den_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
-  %num = load <2 x i32> addrspace(1) * %in
-  %den = load <2 x i32> addrspace(1) * %den_ptr
+  %den_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
+  %num = load <2 x i32>, <2 x i32> addrspace(1) * %in
+  %den = load <2 x i32>, <2 x i32> addrspace(1) * %den_ptr
   %result = srem <2 x i32> %num, %den
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
   ret void
 }
 
 define void @srem_v2i32_4(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %num = load <2 x i32> addrspace(1) * %in
+  %num = load <2 x i32>, <2 x i32> addrspace(1) * %in
   %result = srem <2 x i32> %num, <i32 4, i32 4>
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
   ret void
 }
 
 define void @srem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %den_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
-  %num = load <4 x i32> addrspace(1) * %in
-  %den = load <4 x i32> addrspace(1) * %den_ptr
+  %den_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
+  %num = load <4 x i32>, <4 x i32> addrspace(1) * %in
+  %den = load <4 x i32>, <4 x i32> addrspace(1) * %den_ptr
   %result = srem <4 x i32> %num, %den
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
 }
 
 define void @srem_v4i32_4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %num = load <4 x i32> addrspace(1) * %in
+  %num = load <4 x i32>, <4 x i32> addrspace(1) * %in
   %result = srem <4 x i32> %num, <i32 4, i32 4, i32 4, i32 4>
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
 }
+
+define void @srem_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
+  %den_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
+  %num = load i64, i64 addrspace(1) * %in
+  %den = load i64, i64 addrspace(1) * %den_ptr
+  %result = srem i64 %num, %den
+  store i64 %result, i64 addrspace(1)* %out
+  ret void
+}
+
+define void @srem_i64_4(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
+  %num = load i64, i64 addrspace(1) * %in
+  %result = srem i64 %num, 4
+  store i64 %result, i64 addrspace(1)* %out
+  ret void
+}
+
+define void @srem_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
+  %den_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1
+  %num = load <2 x i64>, <2 x i64> addrspace(1) * %in
+  %den = load <2 x i64>, <2 x i64> addrspace(1) * %den_ptr
+  %result = srem <2 x i64> %num, %den
+  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
+  ret void
+}
+
+define void @srem_v2i64_4(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
+  %num = load <2 x i64>, <2 x i64> addrspace(1) * %in
+  %result = srem <2 x i64> %num, <i64 4, i64 4>
+  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
+  ret void
+}
+
+define void @srem_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
+  %den_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
+  %num = load <4 x i64>, <4 x i64> addrspace(1) * %in
+  %den = load <4 x i64>, <4 x i64> addrspace(1) * %den_ptr
+  %result = srem <4 x i64> %num, %den
+  store <4 x i64> %result, <4 x i64> addrspace(1)* %out
+  ret void
+}
+
+define void @srem_v4i64_4(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
+  %num = load <4 x i64>, <4 x i64> addrspace(1) * %in
+  %result = srem <4 x i64> %num, <i64 4, i64 4, i64 4, i64 4>
+  store <4 x i64> %result, <4 x i64> addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/srl.ll b/test/CodeGen/R600/srl.ll
index 9e7b35e8338a..4904d7fa1bd0 100644
--- a/test/CodeGen/R600/srl.ll
+++ b/test/CodeGen/R600/srl.ll
@@ -1,13 +1,15 @@
 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 
 ; FUNC-LABEL: {{^}}lshr_i32:
 ; SI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
+; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 ; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 define void @lshr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %a = load i32 addrspace(1)* %in
-  %b = load i32 addrspace(1)* %b_ptr
+  %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %a = load i32, i32 addrspace(1)* %in
+  %b = load i32, i32 addrspace(1)* %b_ptr
   %result = lshr i32 %a, %b
   store i32 %result, i32 addrspace(1)* %out
   ret void
@@ -17,12 +19,15 @@ define void @lshr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 ; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 ; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 
+; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
+; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
+
 ; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 define void @lshr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
-  %a = load <2 x i32> addrspace(1)* %in
-  %b = load <2 x i32> addrspace(1)* %b_ptr
+  %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32>, <2 x i32> addrspace(1)* %in
+  %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
   %result = lshr <2 x i32> %a, %b
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
   ret void
@@ -34,14 +39,19 @@ define void @lshr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %i
 ; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 ; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 
+; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
+; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
+; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
+; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
+
 ; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
-  %a = load <4 x i32> addrspace(1)* %in
-  %b = load <4 x i32> addrspace(1)* %b_ptr
+  %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
+  %a = load <4 x i32>, <4 x i32> addrspace(1)* %in
+  %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
   %result = lshr <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
@@ -49,6 +59,7 @@ define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %i
 
 ; FUNC-LABEL: {{^}}lshr_i64:
 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
+; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
 
 ; EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
 ; EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
@@ -62,9 +73,9 @@ define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %i
 ; EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
 ; EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0
 define void @lshr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
-  %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1
-  %a = load i64 addrspace(1)* %in
-  %b = load i64 addrspace(1)* %b_ptr
+  %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
+  %a = load i64, i64 addrspace(1)* %in
+  %b = load i64, i64 addrspace(1)* %b_ptr
   %result = lshr i64 %a, %b
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -74,6 +85,9 @@ define void @lshr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
 
+; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
+; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
+
 ; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
 ; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
 ; EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
@@ -97,9 +111,9 @@ define void @lshr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
 ; EG-DAG: CNDE_INT
 ; EG-DAG: CNDE_INT
 define void @lshr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
-  %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1
-  %a = load <2 x i64> addrspace(1)* %in
-  %b = load <2 x i64> addrspace(1)* %b_ptr
+  %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1
+  %a = load <2 x i64>, <2 x i64> addrspace(1)* %in
+  %b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr
   %result = lshr <2 x i64> %a, %b
   store <2 x i64> %result, <2 x i64> addrspace(1)* %out
   ret void
@@ -111,6 +125,11 @@ define void @lshr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %i
 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
 
+; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
+; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
+; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
+; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
+
 ; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
 ; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
 ; EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
@@ -158,9 +177,9 @@ define void @lshr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %i
 ; EG-DAG: CNDE_INT
 ; EG-DAG: CNDE_INT
 define void @lshr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1
-  %a = load <4 x i64> addrspace(1)* %in
-  %b = load <4 x i64> addrspace(1)* %b_ptr
+  %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
+  %a = load <4 x i64>, <4 x i64> addrspace(1)* %in
+  %b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr
   %result = lshr <4 x i64> %a, %b
   store <4 x i64> %result, <4 x i64> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/ssubo.ll b/test/CodeGen/R600/ssubo.ll
index 09d3959b2b3d..26884a1b7761 100644
--- a/test/CodeGen/R600/ssubo.ll
+++ b/test/CodeGen/R600/ssubo.ll
@@ -28,8 +28,8 @@ define void @s_ssubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32
 
 ; FUNC-LABEL: {{^}}v_ssubo_i32:
 define void @v_ssubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
-  %a = load i32 addrspace(1)* %aptr, align 4
-  %b = load i32 addrspace(1)* %bptr, align 4
+  %a = load i32, i32 addrspace(1)* %aptr, align 4
+  %b = load i32, i32 addrspace(1)* %bptr, align 4
   %ssub = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) nounwind
   %val = extractvalue { i32, i1 } %ssub, 0
   %carry = extractvalue { i32, i1 } %ssub, 1
@@ -54,8 +54,8 @@ define void @s_ssubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64
 ; SI: v_sub_i32_e32
 ; SI: v_subb_u32_e32
 define void @v_ssubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
-  %a = load i64 addrspace(1)* %aptr, align 4
-  %b = load i64 addrspace(1)* %bptr, align 4
+  %a = load i64, i64 addrspace(1)* %aptr, align 4
+  %b = load i64, i64 addrspace(1)* %bptr, align 4
   %ssub = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) nounwind
   %val = extractvalue { i64, i1 } %ssub, 0
   %carry = extractvalue { i64, i1 } %ssub, 1
diff --git a/test/CodeGen/R600/store-barrier.ll b/test/CodeGen/R600/store-barrier.ll
index 350b006ba5e0..4a72b4d090ad 100644
--- a/test/CodeGen/R600/store-barrier.ll
+++ b/test/CodeGen/R600/store-barrier.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck  --check-prefix=CHECK %s
-; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck  --check-prefix=CHECK %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck  --check-prefix=CHECK %s
+; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck  --check-prefix=CHECK %s
 
 ; This test is for a bug in the machine scheduler where stores without
 ; an underlying object would be moved across the barrier.  In this
@@ -14,24 +14,24 @@
 ; Function Attrs: nounwind
 define void @test(<2 x i8> addrspace(3)* nocapture %arg, <2 x i8> addrspace(1)* nocapture readonly %arg1, i32 addrspace(1)* nocapture readonly %arg2, <2 x i8> addrspace(1)* nocapture %arg3, i32 %arg4, i64 %tmp9) {
 bb:
-  %tmp10 = getelementptr inbounds i32 addrspace(1)* %arg2, i64 %tmp9
-  %tmp13 = load i32 addrspace(1)* %tmp10, align 2
-  %tmp14 = getelementptr inbounds <2 x i8> addrspace(3)* %arg, i32 %tmp13
-  %tmp15 = load <2 x i8> addrspace(3)* %tmp14, align 2
+  %tmp10 = getelementptr inbounds i32, i32 addrspace(1)* %arg2, i64 %tmp9
+  %tmp13 = load i32, i32 addrspace(1)* %tmp10, align 2
+  %tmp14 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(3)* %arg, i32 %tmp13
+  %tmp15 = load <2 x i8>, <2 x i8> addrspace(3)* %tmp14, align 2
   %tmp16 = add i32 %tmp13, 1
-  %tmp17 = getelementptr inbounds <2 x i8> addrspace(3)* %arg, i32 %tmp16
+  %tmp17 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(3)* %arg, i32 %tmp16
   store <2 x i8> %tmp15, <2 x i8> addrspace(3)* %tmp17, align 2
   tail call void @llvm.AMDGPU.barrier.local() #2
-  %tmp25 = load i32 addrspace(1)* %tmp10, align 4
+  %tmp25 = load i32, i32 addrspace(1)* %tmp10, align 4
   %tmp26 = sext i32 %tmp25 to i64
   %tmp27 = sext i32 %arg4 to i64
-  %tmp28 = getelementptr inbounds <2 x i8> addrspace(3)* %arg, i32 %tmp25, i32 %arg4
-  %tmp29 = load i8 addrspace(3)* %tmp28, align 1
-  %tmp30 = getelementptr inbounds <2 x i8> addrspace(1)* %arg3, i64 %tmp26, i64 %tmp27
+  %tmp28 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(3)* %arg, i32 %tmp25, i32 %arg4
+  %tmp29 = load i8, i8 addrspace(3)* %tmp28, align 1
+  %tmp30 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(1)* %arg3, i64 %tmp26, i64 %tmp27
   store i8 %tmp29, i8 addrspace(1)* %tmp30, align 1
-  %tmp32 = getelementptr inbounds <2 x i8> addrspace(3)* %arg, i32 %tmp25, i32 0
-  %tmp33 = load i8 addrspace(3)* %tmp32, align 1
-  %tmp35 = getelementptr inbounds <2 x i8> addrspace(1)* %arg3, i64 %tmp26, i64 0
+  %tmp32 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(3)* %arg, i32 %tmp25, i32 0
+  %tmp33 = load i8, i8 addrspace(3)* %tmp32, align 1
+  %tmp35 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(1)* %arg3, i64 %tmp26, i64 0
   store i8 %tmp33, i8 addrspace(1)* %tmp35, align 1
   ret void
 }
diff --git a/test/CodeGen/R600/store-v3i64.ll b/test/CodeGen/R600/store-v3i64.ll
index 4db9b67e0118..e0c554ad2c17 100644
--- a/test/CodeGen/R600/store-v3i64.ll
+++ b/test/CodeGen/R600/store-v3i64.ll
@@ -1,6 +1,6 @@
 ; XFAIL: *
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
 
 ; SI-LABEL: {{^}}global_store_v3i64:
 ; SI: buffer_store_dwordx4
diff --git a/test/CodeGen/R600/store-vector-ptrs.ll b/test/CodeGen/R600/store-vector-ptrs.ll
index ba4d94f73245..d5af3b29118a 100644
--- a/test/CodeGen/R600/store-vector-ptrs.ll
+++ b/test/CodeGen/R600/store-vector-ptrs.ll
@@ -6,7 +6,7 @@
 ; scratch loads and stores.
 ; CHECK-LABEL: {{^}}store_vector_ptrs:
 define void @store_vector_ptrs(<4 x i32*>* %out, <4 x [1024 x i32]*> %array) nounwind {
-  %p = getelementptr <4 x [1024 x i32]*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16>
+  %p = getelementptr [1024 x i32], <4 x [1024 x i32]*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16>
   store <4 x i32*> %p, <4 x i32*>* %out
   ret void
 }
diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll
index e4cb31365786..0f89405e073b 100644
--- a/test/CodeGen/R600/store.ll
+++ b/test/CodeGen/R600/store.ll
@@ -16,7 +16,7 @@ entry:
 }
 
 ; i8 store
-; EG-LABEL: {{^}}store_i8:
+; FUNC-LABEL: {{^}}store_i8:
 ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
 
 ; IG 0: Get the byte index and truncate the value
@@ -37,7 +37,6 @@ entry:
 ; EG: MOV T[[RW_GPR]].Y, 0.0
 ; EG: MOV * T[[RW_GPR]].Z, 0.0
 
-; SI-LABEL: {{^}}store_i8:
 ; SI: buffer_store_byte
 
 define void @store_i8(i8 addrspace(1)* %out, i8 %in) {
@@ -47,7 +46,7 @@ entry:
 }
 
 ; i16 store
-; EG-LABEL: {{^}}store_i16:
+; FUNC-LABEL: {{^}}store_i16:
 ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
 
 ; IG 0: Get the byte index and truncate the value
@@ -71,7 +70,6 @@ entry:
 ; EG: MOV T[[RW_GPR]].Y, 0.0
 ; EG: MOV * T[[RW_GPR]].Z, 0.0
 
-; SI-LABEL: {{^}}store_i16:
 ; SI: buffer_store_short
 define void @store_i16(i16 addrspace(1)* %out, i16 %in) {
 entry:
@@ -79,10 +77,10 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}store_v2i8:
+; FUNC-LABEL: {{^}}store_v2i8:
 ; EG: MEM_RAT MSKOR
 ; EG-NOT: MEM_RAT MSKOR
-; SI-LABEL: {{^}}store_v2i8:
+
 ; SI: buffer_store_byte
 ; SI: buffer_store_byte
 define void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) {
@@ -93,11 +91,11 @@ entry:
 }
 
 
-; EG-LABEL: {{^}}store_v2i16:
+; FUNC-LABEL: {{^}}store_v2i16:
 ; EG: MEM_RAT_CACHELESS STORE_RAW
-; CM-LABEL: {{^}}store_v2i16:
+
 ; CM: MEM_RAT_CACHELESS STORE_DWORD
-; SI-LABEL: {{^}}store_v2i16:
+
 ; SI: buffer_store_short
 ; SI: buffer_store_short
 define void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) {
@@ -107,11 +105,11 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}store_v4i8:
+; FUNC-LABEL: {{^}}store_v4i8:
 ; EG: MEM_RAT_CACHELESS STORE_RAW
-; CM-LABEL: {{^}}store_v4i8:
+
 ; CM: MEM_RAT_CACHELESS STORE_DWORD
-; SI-LABEL: {{^}}store_v4i8:
+
 ; SI: buffer_store_byte
 ; SI: buffer_store_byte
 ; SI: buffer_store_byte
@@ -124,11 +122,11 @@ entry:
 }
 
 ; floating-point store
-; EG-LABEL: {{^}}store_f32:
+; FUNC-LABEL: {{^}}store_f32:
 ; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1
-; CM-LABEL: {{^}}store_f32:
+
 ; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
-; SI-LABEL: {{^}}store_f32:
+
 ; SI: buffer_store_dword
 
 define void @store_f32(float addrspace(1)* %out, float %in) {
@@ -136,13 +134,13 @@ define void @store_f32(float addrspace(1)* %out, float %in) {
   ret void
 }
 
-; EG-LABEL: {{^}}store_v4i16:
+; FUNC-LABEL: {{^}}store_v4i16:
 ; EG: MEM_RAT MSKOR
 ; EG: MEM_RAT MSKOR
 ; EG: MEM_RAT MSKOR
 ; EG: MEM_RAT MSKOR
 ; EG-NOT: MEM_RAT MSKOR
-; SI-LABEL: {{^}}store_v4i16:
+
 ; SI: buffer_store_short
 ; SI: buffer_store_short
 ; SI: buffer_store_short
@@ -156,11 +154,11 @@ entry:
 }
 
 ; vec2 floating-point stores
-; EG-LABEL: {{^}}store_v2f32:
+; FUNC-LABEL: {{^}}store_v2f32:
 ; EG: MEM_RAT_CACHELESS STORE_RAW
-; CM-LABEL: {{^}}store_v2f32:
+
 ; CM: MEM_RAT_CACHELESS STORE_DWORD
-; SI-LABEL: {{^}}store_v2f32:
+
 ; SI: buffer_store_dwordx2
 
 define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) {
@@ -171,13 +169,13 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}store_v4i32:
+; FUNC-LABEL: {{^}}store_v4i32:
 ; EG: MEM_RAT_CACHELESS STORE_RAW
 ; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
-; CM-LABEL: {{^}}store_v4i32:
+
 ; CM: MEM_RAT_CACHELESS STORE_DWORD
 ; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
-; SI-LABEL: {{^}}store_v4i32:
+
 ; SI: buffer_store_dwordx4
 define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
 entry:
@@ -218,29 +216,29 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}store_local_i8:
+; FUNC-LABEL: {{^}}store_local_i8:
 ; EG: LDS_BYTE_WRITE
-; SI-LABEL: {{^}}store_local_i8:
+
 ; SI: ds_write_b8
 define void @store_local_i8(i8 addrspace(3)* %out, i8 %in) {
   store i8 %in, i8 addrspace(3)* %out
   ret void
 }
 
-; EG-LABEL: {{^}}store_local_i16:
+; FUNC-LABEL: {{^}}store_local_i16:
 ; EG: LDS_SHORT_WRITE
-; SI-LABEL: {{^}}store_local_i16:
+
 ; SI: ds_write_b16
 define void @store_local_i16(i16 addrspace(3)* %out, i16 %in) {
   store i16 %in, i16 addrspace(3)* %out
   ret void
 }
 
-; EG-LABEL: {{^}}store_local_v2i16:
+; FUNC-LABEL: {{^}}store_local_v2i16:
 ; EG: LDS_WRITE
-; CM-LABEL: {{^}}store_local_v2i16:
+
 ; CM: LDS_WRITE
-; SI-LABEL: {{^}}store_local_v2i16:
+
 ; SI: ds_write_b16
 ; SI: ds_write_b16
 define void @store_local_v2i16(<2 x i16> addrspace(3)* %out, <2 x i16> %in) {
@@ -249,11 +247,11 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}store_local_v4i8:
+; FUNC-LABEL: {{^}}store_local_v4i8:
 ; EG: LDS_WRITE
-; CM-LABEL: {{^}}store_local_v4i8:
+
 ; CM: LDS_WRITE
-; SI-LABEL: {{^}}store_local_v4i8:
+
 ; SI: ds_write_b8
 ; SI: ds_write_b8
 ; SI: ds_write_b8
@@ -264,13 +262,13 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}store_local_v2i32:
+; FUNC-LABEL: {{^}}store_local_v2i32:
 ; EG: LDS_WRITE
 ; EG: LDS_WRITE
-; CM-LABEL: {{^}}store_local_v2i32:
+
 ; CM: LDS_WRITE
 ; CM: LDS_WRITE
-; SI-LABEL: {{^}}store_local_v2i32:
+
 ; SI: ds_write_b64
 define void @store_local_v2i32(<2 x i32> addrspace(3)* %out, <2 x i32> %in) {
 entry:
@@ -278,17 +276,17 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}store_local_v4i32:
+; FUNC-LABEL: {{^}}store_local_v4i32:
 ; EG: LDS_WRITE
 ; EG: LDS_WRITE
 ; EG: LDS_WRITE
 ; EG: LDS_WRITE
-; CM-LABEL: {{^}}store_local_v4i32:
+
 ; CM: LDS_WRITE
 ; CM: LDS_WRITE
 ; CM: LDS_WRITE
 ; CM: LDS_WRITE
-; SI-LABEL: {{^}}store_local_v4i32:
+
 ; SI: ds_write_b32
 ; SI: ds_write_b32
 ; SI: ds_write_b32
@@ -326,19 +324,19 @@ entry:
 ; Evergreen / Northern Islands don't support 64-bit stores yet, so there should
 ; be two 32-bit stores.
 
-; EG-LABEL: {{^}}vecload2:
+; FUNC-LABEL: {{^}}vecload2:
 ; EG: MEM_RAT_CACHELESS STORE_RAW
-; CM-LABEL: {{^}}vecload2:
+
 ; CM: MEM_RAT_CACHELESS STORE_DWORD
-; SI-LABEL: {{^}}vecload2:
+
 ; SI: buffer_store_dwordx2
 define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
 entry:
-  %0 = load i32 addrspace(2)* %mem, align 4
-  %arrayidx1.i = getelementptr inbounds i32 addrspace(2)* %mem, i64 1
-  %1 = load i32 addrspace(2)* %arrayidx1.i, align 4
+  %0 = load i32, i32 addrspace(2)* %mem, align 4
+  %arrayidx1.i = getelementptr inbounds i32, i32 addrspace(2)* %mem, i64 1
+  %1 = load i32, i32 addrspace(2)* %arrayidx1.i, align 4
   store i32 %0, i32 addrspace(1)* %out, align 4
-  %arrayidx1 = getelementptr inbounds i32 addrspace(1)* %out, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 1
   store i32 %1, i32 addrspace(1)* %arrayidx1, align 4
   ret void
 }
@@ -357,16 +355,15 @@ attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"=
 ; CM: STORE_DWORD
 ; CM: STORE_DWORD
 ; CM: STORE_DWORD
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
+; SI: buffer_store_dwordx4
 define void @i128-const-store(i32 addrspace(1)* %out) {
 entry:
   store i32 1, i32 addrspace(1)* %out, align 4
-  %arrayidx2 = getelementptr inbounds i32 addrspace(1)* %out, i64 1
+  %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 1
   store i32 1, i32 addrspace(1)* %arrayidx2, align 4
-  %arrayidx4 = getelementptr inbounds i32 addrspace(1)* %out, i64 2
+  %arrayidx4 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 2
   store i32 2, i32 addrspace(1)* %arrayidx4, align 4
-  %arrayidx6 = getelementptr inbounds i32 addrspace(1)* %out, i64 3
+  %arrayidx6 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 3
   store i32 2, i32 addrspace(1)* %arrayidx6, align 4
   ret void
 }
diff --git a/test/CodeGen/R600/store.r600.ll b/test/CodeGen/R600/store.r600.ll
index 21972603cac9..696fb033b5ec 100644
--- a/test/CodeGen/R600/store.r600.ll
+++ b/test/CodeGen/R600/store.r600.ll
@@ -7,7 +7,7 @@
 ; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
 
 define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %1 = load <4 x i32> addrspace(1) * %in
+  %1 = load <4 x i32>, <4 x i32> addrspace(1) * %in
   store <4 x i32> %1, <4 x i32> addrspace(1)* %out
   ret void
 }
@@ -16,7 +16,7 @@ define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %
 ; EG: {{^}}store_v4f32:
 ; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
 define void @store_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
-  %1 = load <4 x float> addrspace(1) * %in
+  %1 = load <4 x float>, <4 x float> addrspace(1) * %in
   store <4 x float> %1, <4 x float> addrspace(1)* %out
   ret void
 }
diff --git a/test/CodeGen/R600/sub.ll b/test/CodeGen/R600/sub.ll
index be48e186e870..b7fba0efa5b2 100644
--- a/test/CodeGen/R600/sub.ll
+++ b/test/CodeGen/R600/sub.ll
@@ -9,9 +9,9 @@ declare i32 @llvm.r600.read.tidig.x() readnone
 
 ; SI: v_subrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 define void @test_sub_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %a = load i32 addrspace(1)* %in
-  %b = load i32 addrspace(1)* %b_ptr
+  %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %a = load i32, i32 addrspace(1)* %in
+  %b = load i32, i32 addrspace(1)* %b_ptr
   %result = sub i32 %a, %b
   store i32 %result, i32 addrspace(1)* %out
   ret void
@@ -26,9 +26,9 @@ define void @test_sub_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 ; SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 
 define void @test_sub_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
-  %a = load <2 x i32> addrspace(1) * %in
-  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32>, <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
   %result = sub <2 x i32> %a, %b
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
   ret void
@@ -46,9 +46,9 @@ define void @test_sub_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)
 ; SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 
 define void @test_sub_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
-  %a = load <4 x i32> addrspace(1) * %in
-  %b = load <4 x i32> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
+  %a = load <4 x i32>, <4 x i32> addrspace(1) * %in
+  %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
   %result = sub <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
@@ -58,11 +58,13 @@ define void @test_sub_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)
 ; SI: s_sub_u32
 ; SI: s_subb_u32
 
-; EG-DAG: SETGE_UINT
-; EG-DAG: CNDE_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SUB_INT
+; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
+; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
+; EG-DAG: SUB_INT {{[* ]*}}[[LO]]
+; EG-DAG: SUBB_UINT
 ; EG-DAG: SUB_INT
+; EG-DAG: SUB_INT {{[* ]*}}[[HI]]
+; EG-NOT: SUB
 define void @s_sub_i64(i64 addrspace(1)* noalias %out, i64 %a, i64 %b) nounwind {
   %result = sub i64 %a, %b
   store i64 %result, i64 addrspace(1)* %out, align 8
@@ -73,17 +75,19 @@ define void @s_sub_i64(i64 addrspace(1)* noalias %out, i64 %a, i64 %b) nounwind
 ; SI: v_sub_i32_e32
 ; SI: v_subb_u32_e32
 
-; EG-DAG: SETGE_UINT
-; EG-DAG: CNDE_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SUB_INT
+; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
+; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
+; EG-DAG: SUB_INT {{[* ]*}}[[LO]]
+; EG-DAG: SUBB_UINT
 ; EG-DAG: SUB_INT
+; EG-DAG: SUB_INT {{[* ]*}}[[HI]]
+; EG-NOT: SUB
 define void @v_sub_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) nounwind {
   %tid = call i32 @llvm.r600.read.tidig.x() readnone
-  %a_ptr = getelementptr i64 addrspace(1)* %inA, i32 %tid
-  %b_ptr = getelementptr i64 addrspace(1)* %inB, i32 %tid
-  %a = load i64 addrspace(1)* %a_ptr
-  %b = load i64 addrspace(1)* %b_ptr
+  %a_ptr = getelementptr i64, i64 addrspace(1)* %inA, i32 %tid
+  %b_ptr = getelementptr i64, i64 addrspace(1)* %inB, i32 %tid
+  %a = load i64, i64 addrspace(1)* %a_ptr
+  %b = load i64, i64 addrspace(1)* %b_ptr
   %result = sub i64 %a, %b
   store i64 %result, i64 addrspace(1)* %out, align 8
   ret void
@@ -96,10 +100,10 @@ define void @v_sub_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias
 ; SI: v_subb_u32_e32
 define void @v_test_sub_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) {
   %tid = call i32 @llvm.r600.read.tidig.x() readnone
-  %a_ptr = getelementptr <2 x i64> addrspace(1)* %inA, i32 %tid
-  %b_ptr = getelementptr <2 x i64> addrspace(1)* %inB, i32 %tid
-  %a = load <2 x i64> addrspace(1)* %a_ptr
-  %b = load <2 x i64> addrspace(1)* %b_ptr
+  %a_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %inA, i32 %tid
+  %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %inB, i32 %tid
+  %a = load <2 x i64>, <2 x i64> addrspace(1)* %a_ptr
+  %b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr
   %result = sub <2 x i64> %a, %b
   store <2 x i64> %result, <2 x i64> addrspace(1)* %out
   ret void
@@ -116,10 +120,10 @@ define void @v_test_sub_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(
 ; SI: v_subb_u32_e32
 define void @v_test_sub_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* noalias %inA, <4 x i64> addrspace(1)* noalias %inB) {
   %tid = call i32 @llvm.r600.read.tidig.x() readnone
-  %a_ptr = getelementptr <4 x i64> addrspace(1)* %inA, i32 %tid
-  %b_ptr = getelementptr <4 x i64> addrspace(1)* %inB, i32 %tid
-  %a = load <4 x i64> addrspace(1)* %a_ptr
-  %b = load <4 x i64> addrspace(1)* %b_ptr
+  %a_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %inA, i32 %tid
+  %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %inB, i32 %tid
+  %a = load <4 x i64>, <4 x i64> addrspace(1)* %a_ptr
+  %b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr
   %result = sub <4 x i64> %a, %b
   store <4 x i64> %result, <4 x i64> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/subreg-coalescer-crash.ll b/test/CodeGen/R600/subreg-coalescer-crash.ll
index a9eec7908b6c..c4dae4736cfa 100644
--- a/test/CodeGen/R600/subreg-coalescer-crash.ll
+++ b/test/CodeGen/R600/subreg-coalescer-crash.ll
@@ -1,10 +1,10 @@
 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -o - %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - %s
-; ModuleID = 'bugpoint-reduced-simplified.bc'
 
+; SI-LABEL:{{^}}row_filter_C1_D0:
 ; SI: s_endpgm
 ; Function Attrs: nounwind
-define void @row_filter_C1_D0() #0 {
+define void @row_filter_C1_D0() {
 entry:
   br i1 undef, label %for.inc.1, label %do.body.preheader
 
@@ -42,3 +42,68 @@ for.inc.1:                                        ; preds = %do.body.1562.prehea
   unreachable
 }
 
+; SI-LABEL: {{^}}foo:
+; SI: s_endpgm
+define void @foo() #0 {
+bb:
+  br i1 undef, label %bb2, label %bb1
+
+bb1:                                              ; preds = %bb
+  br i1 undef, label %bb4, label %bb6
+
+bb2:                                              ; preds = %bb4, %bb
+  %tmp = phi float [ %tmp5, %bb4 ], [ 0.000000e+00, %bb ]
+  br i1 undef, label %bb9, label %bb13
+
+bb4:                                              ; preds = %bb7, %bb6, %bb1
+  %tmp5 = phi float [ undef, %bb1 ], [ undef, %bb6 ], [ %tmp8, %bb7 ]
+  br label %bb2
+
+bb6:                                              ; preds = %bb1
+  br i1 undef, label %bb7, label %bb4
+
+bb7:                                              ; preds = %bb6
+  %tmp8 = fmul float undef, undef
+  br label %bb4
+
+bb9:                                              ; preds = %bb2
+  %tmp10 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 2)
+  %tmp11 = extractelement <4 x float> %tmp10, i32 1
+  %tmp12 = extractelement <4 x float> %tmp10, i32 3
+  br label %bb14
+
+bb13:                                             ; preds = %bb2
+  br i1 undef, label %bb23, label %bb24
+
+bb14:                                             ; preds = %bb27, %bb24, %bb9
+  %tmp15 = phi float [ %tmp12, %bb9 ], [ undef, %bb27 ], [ 0.000000e+00, %bb24 ]
+  %tmp16 = phi float [ %tmp11, %bb9 ], [ undef, %bb27 ], [ %tmp25, %bb24 ]
+  %tmp17 = fmul float 10.5, %tmp16
+  %tmp18 = fmul float 11.5, %tmp15
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp18, float %tmp17, float %tmp17, float %tmp17)
+  ret void
+
+bb23:                                             ; preds = %bb13
+  br i1 undef, label %bb24, label %bb26
+
+bb24:                                             ; preds = %bb26, %bb23, %bb13
+  %tmp25 = phi float [ %tmp, %bb13 ], [ %tmp, %bb26 ], [ 0.000000e+00, %bb23 ]
+  br i1 undef, label %bb27, label %bb14
+
+bb26:                                             ; preds = %bb23
+  br label %bb24
+
+bb27:                                             ; preds = %bb24
+  br label %bb14
+}
+
+; Function Attrs: nounwind readnone
+declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.SI.packf16(float, float) #1
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
+
+attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" }
+attributes #1 = { nounwind readnone }
diff --git a/test/CodeGen/R600/swizzle-export.ll b/test/CodeGen/R600/swizzle-export.ll
index 5eaca7675237..000ee2faa478 100644
--- a/test/CodeGen/R600/swizzle-export.ll
+++ b/test/CodeGen/R600/swizzle-export.ll
@@ -12,56 +12,56 @@ main_body:
   %1 = extractelement <4 x float> %reg1, i32 1
   %2 = extractelement <4 x float> %reg1, i32 2
   %3 = extractelement <4 x float> %reg1, i32 3
-  %4 = load <4 x float> addrspace(8)* null
+  %4 = load <4 x float>, <4 x float> addrspace(8)* null
   %5 = extractelement <4 x float> %4, i32 1
-  %6 = load <4 x float> addrspace(8)* null
+  %6 = load <4 x float>, <4 x float> addrspace(8)* null
   %7 = extractelement <4 x float> %6, i32 2
-  %8 = load <4 x float> addrspace(8)* null
+  %8 = load <4 x float>, <4 x float> addrspace(8)* null
   %9 = extractelement <4 x float> %8, i32 0
   %10 = fmul float 0.000000e+00, %9
-  %11 = load <4 x float> addrspace(8)* null
+  %11 = load <4 x float>, <4 x float> addrspace(8)* null
   %12 = extractelement <4 x float> %11, i32 0
   %13 = fmul float %5, %12
-  %14 = load <4 x float> addrspace(8)* null
+  %14 = load <4 x float>, <4 x float> addrspace(8)* null
   %15 = extractelement <4 x float> %14, i32 0
   %16 = fmul float 0.000000e+00, %15
-  %17 = load <4 x float> addrspace(8)* null
+  %17 = load <4 x float>, <4 x float> addrspace(8)* null
   %18 = extractelement <4 x float> %17, i32 0
   %19 = fmul float 0.000000e+00, %18
-  %20 = load <4 x float> addrspace(8)* null
+  %20 = load <4 x float>, <4 x float> addrspace(8)* null
   %21 = extractelement <4 x float> %20, i32 0
   %22 = fmul float %7, %21
-  %23 = load <4 x float> addrspace(8)* null
+  %23 = load <4 x float>, <4 x float> addrspace(8)* null
   %24 = extractelement <4 x float> %23, i32 0
   %25 = fmul float 0.000000e+00, %24
-  %26 = load <4 x float> addrspace(8)* null
+  %26 = load <4 x float>, <4 x float> addrspace(8)* null
   %27 = extractelement <4 x float> %26, i32 0
   %28 = fmul float 0.000000e+00, %27
-  %29 = load <4 x float> addrspace(8)* null
+  %29 = load <4 x float>, <4 x float> addrspace(8)* null
   %30 = extractelement <4 x float> %29, i32 0
   %31 = fmul float 0.000000e+00, %30
-  %32 = load <4 x float> addrspace(8)* null
+  %32 = load <4 x float>, <4 x float> addrspace(8)* null
   %33 = extractelement <4 x float> %32, i32 0
   %34 = fmul float 0.000000e+00, %33
-  %35 = load <4 x float> addrspace(8)* null
+  %35 = load <4 x float>, <4 x float> addrspace(8)* null
   %36 = extractelement <4 x float> %35, i32 0
   %37 = fmul float 0.000000e+00, %36
-  %38 = load <4 x float> addrspace(8)* null
+  %38 = load <4 x float>, <4 x float> addrspace(8)* null
   %39 = extractelement <4 x float> %38, i32 0
   %40 = fmul float 1.000000e+00, %39
-  %41 = load <4 x float> addrspace(8)* null
+  %41 = load <4 x float>, <4 x float> addrspace(8)* null
   %42 = extractelement <4 x float> %41, i32 0
   %43 = fmul float 0.000000e+00, %42
-  %44 = load <4 x float> addrspace(8)* null
+  %44 = load <4 x float>, <4 x float> addrspace(8)* null
   %45 = extractelement <4 x float> %44, i32 0
   %46 = fmul float 0.000000e+00, %45
-  %47 = load <4 x float> addrspace(8)* null
+  %47 = load <4 x float>, <4 x float> addrspace(8)* null
   %48 = extractelement <4 x float> %47, i32 0
   %49 = fmul float 0.000000e+00, %48
-  %50 = load <4 x float> addrspace(8)* null
+  %50 = load <4 x float>, <4 x float> addrspace(8)* null
   %51 = extractelement <4 x float> %50, i32 0
   %52 = fmul float 0.000000e+00, %51
-  %53 = load <4 x float> addrspace(8)* null
+  %53 = load <4 x float>, <4 x float> addrspace(8)* null
   %54 = extractelement <4 x float> %53, i32 0
   %55 = fmul float 1.000000e+00, %54
   %56 = insertelement <4 x float> undef, float %0, i32 0
@@ -102,12 +102,12 @@ main_body:
   %1 = extractelement <4 x float> %reg1, i32 1
   %2 = fadd float %0, 2.5
   %3 = fmul float %1, 3.5
-  %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
   %5 = extractelement <4 x float> %4, i32 0
   %6 = call float @llvm.cos.f32(float %5)
-  %7 = load <4 x float> addrspace(8)* null
+  %7 = load <4 x float>, <4 x float> addrspace(8)* null
   %8 = extractelement <4 x float> %7, i32 0
-  %9 = load <4 x float> addrspace(8)* null
+  %9 = load <4 x float>, <4 x float> addrspace(8)* null
   %10 = extractelement <4 x float> %9, i32 1
   %11 = insertelement <4 x float> undef, float %2, i32 0
   %12 = insertelement <4 x float> %11, float %3, i32 1
diff --git a/test/CodeGen/R600/trunc-cmp-constant.ll b/test/CodeGen/R600/trunc-cmp-constant.ll
index 67a9aaffb6ff..dac74728b3ce 100644
--- a/test/CodeGen/R600/trunc-cmp-constant.ll
+++ b/test/CodeGen/R600/trunc-cmp-constant.ll
@@ -1,15 +1,15 @@
-; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
 ; FUNC-LABEL {{^}}sextload_i1_to_i32_trunc_cmp_eq_0:
 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
-; SI: v_cmp_eq_i32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[TMP]], 1{{$}}
-; SI: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1{{$}}
+; SI: v_cmp_eq_i32_e32 vcc, 1, [[TMP]]{{$}}
+; SI: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, vcc, -1{{$}}
 ; SI: v_cndmask_b32_e64
 ; SI: buffer_store_byte
 define void @sextload_i1_to_i32_trunc_cmp_eq_0(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = sext i1 %load to i32
   %cmp = icmp eq i32 %ext, 0
   store i1 %cmp, i1 addrspace(1)* %out
@@ -20,12 +20,12 @@ define void @sextload_i1_to_i32_trunc_cmp_eq_0(i1 addrspace(1)* %out, i1 addrspa
 ; FUNC-LABEL: {{^}}zextload_i1_to_i32_trunc_cmp_eq_0:
 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
-; SI: v_cmp_eq_i32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], [[TMP]], 1{{$}}
-; SI-NEXT: s_xor_b64 [[NEG:s\[[0-9]+:[0-9]+\]]], [[CMP0]], -1
+; SI: v_cmp_eq_i32_e32 vcc, 1, [[TMP]]{{$}}
+; SI-NEXT: s_xor_b64 [[NEG:s\[[0-9]+:[0-9]+\]]], vcc, -1
 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[NEG]]
 ; SI-NEXT: buffer_store_byte [[RESULT]]
 define void @zextload_i1_to_i32_trunc_cmp_eq_0(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = zext i1 %load to i32
   %cmp = icmp eq i32 %ext, 0
   store i1 %cmp, i1 addrspace(1)* %out
@@ -34,9 +34,9 @@ define void @zextload_i1_to_i32_trunc_cmp_eq_0(i1 addrspace(1)* %out, i1 addrspa
 
 ; FUNC-LABEL: {{^}}sextload_i1_to_i32_trunc_cmp_eq_1:
 ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
-; SI-NEXT: buffer_store_byte [[RESULT]]
+; SI: buffer_store_byte [[RESULT]]
 define void @sextload_i1_to_i32_trunc_cmp_eq_1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = sext i1 %load to i32
   %cmp = icmp eq i32 %ext, 1
   store i1 %cmp, i1 addrspace(1)* %out
@@ -48,7 +48,7 @@ define void @sextload_i1_to_i32_trunc_cmp_eq_1(i1 addrspace(1)* %out, i1 addrspa
 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
 ; SI-NEXT: buffer_store_byte [[RESULT]]
 define void @zextload_i1_to_i32_trunc_cmp_eq_1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = zext i1 %load to i32
   %cmp = icmp eq i32 %ext, 1
   store i1 %cmp, i1 addrspace(1)* %out
@@ -60,7 +60,7 @@ define void @zextload_i1_to_i32_trunc_cmp_eq_1(i1 addrspace(1)* %out, i1 addrspa
 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
 ; SI-NEXT: buffer_store_byte [[RESULT]]
 define void @sextload_i1_to_i32_trunc_cmp_eq_neg1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = sext i1 %load to i32
   %cmp = icmp eq i32 %ext, -1
   store i1 %cmp, i1 addrspace(1)* %out
@@ -69,9 +69,9 @@ define void @sextload_i1_to_i32_trunc_cmp_eq_neg1(i1 addrspace(1)* %out, i1 addr
 
 ; FUNC-LABEL: {{^}}zextload_i1_to_i32_trunc_cmp_eq_neg1:
 ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
-; SI-NEXT: buffer_store_byte [[RESULT]]
+; SI: buffer_store_byte [[RESULT]]
 define void @zextload_i1_to_i32_trunc_cmp_eq_neg1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = zext i1 %load to i32
   %cmp = icmp eq i32 %ext, -1
   store i1 %cmp, i1 addrspace(1)* %out
@@ -84,7 +84,7 @@ define void @zextload_i1_to_i32_trunc_cmp_eq_neg1(i1 addrspace(1)* %out, i1 addr
 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
 ; SI-NEXT: buffer_store_byte [[RESULT]]
 define void @sextload_i1_to_i32_trunc_cmp_ne_0(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = sext i1 %load to i32
   %cmp = icmp ne i32 %ext, 0
   store i1 %cmp, i1 addrspace(1)* %out
@@ -96,7 +96,7 @@ define void @sextload_i1_to_i32_trunc_cmp_ne_0(i1 addrspace(1)* %out, i1 addrspa
 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
 ; SI-NEXT: buffer_store_byte [[RESULT]]
 define void @zextload_i1_to_i32_trunc_cmp_ne_0(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = zext i1 %load to i32
   %cmp = icmp ne i32 %ext, 0
   store i1 %cmp, i1 addrspace(1)* %out
@@ -105,9 +105,9 @@ define void @zextload_i1_to_i32_trunc_cmp_ne_0(i1 addrspace(1)* %out, i1 addrspa
 
 ; FUNC-LABEL: {{^}}sextload_i1_to_i32_trunc_cmp_ne_1:
 ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 1{{$}}
-; SI-NEXT: buffer_store_byte [[RESULT]]
+; SI: buffer_store_byte [[RESULT]]
 define void @sextload_i1_to_i32_trunc_cmp_ne_1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = sext i1 %load to i32
   %cmp = icmp ne i32 %ext, 1
   store i1 %cmp, i1 addrspace(1)* %out
@@ -117,12 +117,12 @@ define void @sextload_i1_to_i32_trunc_cmp_ne_1(i1 addrspace(1)* %out, i1 addrspa
 ; FUNC-LABEL: {{^}}zextload_i1_to_i32_trunc_cmp_ne_1:
 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
-; SI: v_cmp_eq_i32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], [[TMP]], 1{{$}}
-; SI-NEXT: s_xor_b64 [[NEG:s\[[0-9]+:[0-9]+\]]], [[CMP0]], -1
+; SI: v_cmp_eq_i32_e32 vcc, 1, [[TMP]]{{$}}
+; SI-NEXT: s_xor_b64 [[NEG:s\[[0-9]+:[0-9]+\]]], vcc, -1
 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[NEG]]
 ; SI-NEXT: buffer_store_byte [[RESULT]]
 define void @zextload_i1_to_i32_trunc_cmp_ne_1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = zext i1 %load to i32
   %cmp = icmp ne i32 %ext, 1
   store i1 %cmp, i1 addrspace(1)* %out
@@ -137,7 +137,7 @@ define void @zextload_i1_to_i32_trunc_cmp_ne_1(i1 addrspace(1)* %out, i1 addrspa
 ; XSI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CMP0]]
 ; XSI-NEXT: buffer_store_byte [[RESULT]]
 define void @sextload_i1_to_i32_trunc_cmp_ne_neg1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = sext i1 %load to i32
   %cmp = icmp ne i32 %ext, -1
   store i1 %cmp, i1 addrspace(1)* %out
@@ -146,9 +146,9 @@ define void @sextload_i1_to_i32_trunc_cmp_ne_neg1(i1 addrspace(1)* %out, i1 addr
 
 ; FUNC-LABEL: {{^}}zextload_i1_to_i32_trunc_cmp_ne_neg1:
 ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 1{{$}}
-; SI-NEXT: buffer_store_byte [[RESULT]]
+; SI: buffer_store_byte [[RESULT]]
 define void @zextload_i1_to_i32_trunc_cmp_ne_neg1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
-  %load = load i1 addrspace(1)* %in
+  %load = load i1, i1 addrspace(1)* %in
   %ext = zext i1 %load to i32
   %cmp = icmp ne i32 %ext, -1
   store i1 %cmp, i1 addrspace(1)* %out
@@ -157,11 +157,11 @@ define void @zextload_i1_to_i32_trunc_cmp_ne_neg1(i1 addrspace(1)* %out, i1 addr
 
 ; FUNC-LABEL: {{^}}masked_load_i1_to_i32_trunc_cmp_ne_neg1:
 ; SI: buffer_load_sbyte [[LOAD:v[0-9]+]]
-; SI: v_cmp_ne_i32_e64 {{s\[[0-9]+:[0-9]+\]}}, [[LOAD]], -1{{$}}
+; SI: v_cmp_ne_i32_e32 vcc, -1, [[LOAD]]{{$}}
 ; SI-NEXT: v_cndmask_b32_e64
 ; SI-NEXT: buffer_store_byte
 define void @masked_load_i1_to_i32_trunc_cmp_ne_neg1(i1 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind {
-  %load = load i8 addrspace(1)* %in
+  %load = load i8, i8 addrspace(1)* %in
   %masked = and i8 %load, 255
   %ext = sext i8 %masked to i32
   %cmp = icmp ne i32 %ext, -1
diff --git a/test/CodeGen/R600/trunc.ll b/test/CodeGen/R600/trunc.ll
index bc00db7dbeef..bf690ca4cb28 100644
--- a/test/CodeGen/R600/trunc.ll
+++ b/test/CodeGen/R600/trunc.ll
@@ -36,6 +36,8 @@ define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) {
 ; SI: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2
 ; SI: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],
 ; SI: s_addc_u32
+; SI: v_mov_b32_e32
+; SI: v_mov_b32_e32
 ; SI: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]
 ; SI: buffer_store_dword v[[LO_VREG]],
 define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) {
@@ -51,7 +53,7 @@ define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64
 ; SI: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
 ; SI: v_cmp_eq_i32
 define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) {
-  %a = load i32 addrspace(1)* %ptr, align 4
+  %a = load i32, i32 addrspace(1)* %ptr, align 4
   %trunc = trunc i32 %a to i1
   %result = select i1 %trunc, i32 1, i32 0
   store i32 %result, i32 addrspace(1)* %out, align 4
@@ -71,8 +73,8 @@ define void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {
 ; SI-LABEL: {{^}}s_trunc_i64_to_i1:
 ; SI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xb
 ; SI: v_and_b32_e64 [[MASKED:v[0-9]+]], 1, s[[SLO]]
-; SI: v_cmp_eq_i32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[MASKED]], 1
-; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, [[CMP]]
+; SI: v_cmp_eq_i32_e32 vcc, 1, [[MASKED]]
+; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc
 define void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 %x) {
   %trunc = trunc i64 %x to i1
   %sel = select i1 %trunc, i32 63, i32 -12
@@ -83,13 +85,13 @@ define void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 %x) {
 ; SI-LABEL: {{^}}v_trunc_i64_to_i1:
 ; SI: buffer_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}
 ; SI: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]
-; SI: v_cmp_eq_i32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[MASKED]], 1
-; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, [[CMP]]
+; SI: v_cmp_eq_i32_e32 vcc, 1, [[MASKED]]
+; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc
 define void @v_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep = getelementptr i64 addrspace(1)* %in, i32 %tid
-  %out.gep = getelementptr i32 addrspace(1)* %out, i32 %tid
-  %x = load i64 addrspace(1)* %gep
+  %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+  %x = load i64, i64 addrspace(1)* %gep
 
   %trunc = trunc i64 %x to i1
   %sel = select i1 %trunc, i32 63, i32 -12
diff --git a/test/CodeGen/R600/tti-unroll-prefs.ll b/test/CodeGen/R600/tti-unroll-prefs.ll
index 0009c42f79bc..76c32afc1f21 100644
--- a/test/CodeGen/R600/tti-unroll-prefs.ll
+++ b/test/CodeGen/R600/tti-unroll-prefs.ll
@@ -39,7 +39,7 @@ if.then4:                                         ; preds = %if.then4.lr.ph, %if
   %add2 = add nsw i32 %b.addr.014, 1
   %1 = sext i32 %b.addr.014 to i64
   %add.ptr.sum = add nsw i64 %1, %0
-  %add.ptr5 = getelementptr inbounds i8 addrspace(1)* %dst, i64 %add.ptr.sum
+  %add.ptr5 = getelementptr inbounds i8, i8 addrspace(1)* %dst, i64 %add.ptr.sum
   store i8 0, i8 addrspace(1)* %add.ptr5, align 1
   %inc = add nsw i32 %i.015, 1
   %cmp1 = icmp slt i32 %inc, 4
diff --git a/test/CodeGen/R600/uaddo.ll b/test/CodeGen/R600/uaddo.ll
index 57d7835f99fb..11438f267ad0 100644
--- a/test/CodeGen/R600/uaddo.ll
+++ b/test/CodeGen/R600/uaddo.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs< %s
+; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs< %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 
 declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
 declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
@@ -9,6 +9,9 @@ declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
 ; SI: add
 ; SI: addc
 ; SI: addc
+
+; EG: ADDC_UINT
+; EG: ADDC_UINT
 define void @uaddo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
   %uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) nounwind
   %val = extractvalue { i64, i1 } %uadd, 0
@@ -21,6 +24,9 @@ define void @uaddo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
 
 ; FUNC-LABEL: {{^}}s_uaddo_i32:
 ; SI: s_add_i32
+
+; EG: ADDC_UINT
+; EG: ADD_INT
 define void @s_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) nounwind {
   %uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) nounwind
   %val = extractvalue { i32, i1 } %uadd, 0
@@ -32,9 +38,12 @@ define void @s_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32
 
 ; FUNC-LABEL: {{^}}v_uaddo_i32:
 ; SI: v_add_i32
+
+; EG: ADDC_UINT
+; EG: ADD_INT
 define void @v_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
-  %a = load i32 addrspace(1)* %aptr, align 4
-  %b = load i32 addrspace(1)* %bptr, align 4
+  %a = load i32, i32 addrspace(1)* %aptr, align 4
+  %b = load i32, i32 addrspace(1)* %bptr, align 4
   %uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) nounwind
   %val = extractvalue { i32, i1 } %uadd, 0
   %carry = extractvalue { i32, i1 } %uadd, 1
@@ -46,6 +55,9 @@ define void @v_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32
 ; FUNC-LABEL: {{^}}s_uaddo_i64:
 ; SI: s_add_u32
 ; SI: s_addc_u32
+
+; EG: ADDC_UINT
+; EG: ADD_INT
 define void @s_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a, i64 %b) nounwind {
   %uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) nounwind
   %val = extractvalue { i64, i1 } %uadd, 0
@@ -58,9 +70,12 @@ define void @s_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64
 ; FUNC-LABEL: {{^}}v_uaddo_i64:
 ; SI: v_add_i32
 ; SI: v_addc_u32
+
+; EG: ADDC_UINT
+; EG: ADD_INT
 define void @v_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
-  %a = load i64 addrspace(1)* %aptr, align 4
-  %b = load i64 addrspace(1)* %bptr, align 4
+  %a = load i64, i64 addrspace(1)* %aptr, align 4
+  %b = load i64, i64 addrspace(1)* %bptr, align 4
   %uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) nounwind
   %val = extractvalue { i64, i1 } %uadd, 0
   %carry = extractvalue { i64, i1 } %uadd, 1
diff --git a/test/CodeGen/R600/udiv.ll b/test/CodeGen/R600/udiv.ll
index 0c2c65bb7bf6..de22a22e5029 100644
--- a/test/CodeGen/R600/udiv.ll
+++ b/test/CodeGen/R600/udiv.ll
@@ -7,9 +7,9 @@
 ;EG: CF_END
 
 define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %a = load i32 addrspace(1) * %in
-  %b = load i32 addrspace(1) * %b_ptr
+  %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %a = load i32, i32 addrspace(1) * %in
+  %b = load i32, i32 addrspace(1) * %b_ptr
   %result = udiv i32 %a, %b
   store i32 %result, i32 addrspace(1)* %out
   ret void
@@ -25,9 +25,9 @@ define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 ;SI: s_endpgm
 
 define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
-  %a = load <2 x i32> addrspace(1) * %in
-  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32>, <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
   %result = udiv <2 x i32> %a, %b
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
   ret void
@@ -39,9 +39,9 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
 ;SI: s_endpgm
 
 define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
-  %a = load <4 x i32> addrspace(1) * %in
-  %b = load <4 x i32> addrspace(1) * %b_ptr
+  %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
+  %a = load <4 x i32>, <4 x i32> addrspace(1) * %in
+  %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
   %result = udiv <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/udivrem.ll b/test/CodeGen/R600/udivrem.ll
index b439d7aa892a..b3837f28209a 100644
--- a/test/CodeGen/R600/udivrem.ll
+++ b/test/CodeGen/R600/udivrem.ll
@@ -118,7 +118,7 @@ define void @test_udivrem(i32 addrspace(1)* %out, i32 %x, i32 %y) {
 ; SI-DAG: v_cndmask_b32_e64
 ; SI-DAG: v_mul_hi_u32 [[FIRST_Quotient:v[0-9]+]]
 ; SI-DAG: v_mul_lo_i32 [[FIRST_Num_S_Remainder:v[0-9]+]]
-; SI-DAG: v_sub_i32_e32 [[FIRST_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[FIRST_Num_S_Remainder]]
+; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder:v[0-9]+]], [[FIRST_Num_S_Remainder]], v{{[0-9]+}}
 ; SI-DAG: v_cndmask_b32_e64
 ; SI-DAG: v_cndmask_b32_e64
 ; SI-DAG: v_and_b32_e32 [[FIRST_Tmp1:v[0-9]+]]
@@ -141,7 +141,7 @@ define void @test_udivrem(i32 addrspace(1)* %out, i32 %x, i32 %y) {
 ; SI-DAG: v_cndmask_b32_e64
 ; SI-DAG: v_mul_hi_u32 [[SECOND_Quotient:v[0-9]+]]
 ; SI-DAG: v_mul_lo_i32 [[SECOND_Num_S_Remainder:v[0-9]+]]
-; SI-DAG: v_sub_i32_e32 [[SECOND_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[SECOND_Num_S_Remainder]]
+; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder:v[0-9]+]], [[SECOND_Num_S_Remainder]], v{{[0-9]+}}
 ; SI-DAG: v_cndmask_b32_e64
 ; SI-DAG: v_cndmask_b32_e64
 ; SI-DAG: v_and_b32_e32 [[SECOND_Tmp1:v[0-9]+]]
@@ -268,7 +268,7 @@ define void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i3
 ; SI-DAG: v_cndmask_b32_e64
 ; SI-DAG: v_mul_hi_u32 [[FIRST_Quotient:v[0-9]+]]
 ; SI-DAG: v_mul_lo_i32 [[FIRST_Num_S_Remainder:v[0-9]+]]
-; SI-DAG: v_sub_i32_e32 [[FIRST_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[FIRST_Num_S_Remainder]]
+; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder:v[l0-9]+]], [[FIRST_Num_S_Remainder]], v{{[0-9]+}}
 ; SI-DAG: v_cndmask_b32_e64
 ; SI-DAG: v_cndmask_b32_e64
 ; SI-DAG: v_and_b32_e32 [[FIRST_Tmp1:v[0-9]+]]
@@ -291,7 +291,7 @@ define void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i3
 ; SI-DAG: v_cndmask_b32_e64
 ; SI-DAG: v_mul_hi_u32 [[SECOND_Quotient:v[0-9]+]]
 ; SI-DAG: v_mul_lo_i32 [[SECOND_Num_S_Remainder:v[0-9]+]]
-; SI-DAG: v_sub_i32_e32 [[SECOND_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[SECOND_Num_S_Remainder]]
+; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder:v[0-9]+]], [[SECOND_Num_S_Remainder]], v{{[0-9]+}}
 ; SI-DAG: v_cndmask_b32_e64
 ; SI-DAG: v_cndmask_b32_e64
 ; SI-DAG: v_and_b32_e32 [[SECOND_Tmp1:v[0-9]+]]
@@ -314,7 +314,7 @@ define void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i3
 ; SI-DAG: v_cndmask_b32_e64
 ; SI-DAG: v_mul_hi_u32 [[THIRD_Quotient:v[0-9]+]]
 ; SI-DAG: v_mul_lo_i32 [[THIRD_Num_S_Remainder:v[0-9]+]]
-; SI-DAG: v_sub_i32_e32 [[THIRD_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[THIRD_Num_S_Remainder]]
+; SI-DAG: v_subrev_i32_e32 [[THIRD_Remainder:v[0-9]+]], [[THIRD_Num_S_Remainder]], {{v[0-9]+}}
 ; SI-DAG: v_cndmask_b32_e64
 ; SI-DAG: v_cndmask_b32_e64
 ; SI-DAG: v_and_b32_e32 [[THIRD_Tmp1:v[0-9]+]]
@@ -335,20 +335,6 @@ define void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i3
 ; SI-DAG: v_add_i32_e32 [[FOURTH_RCP_A_E:v[0-9]+]], [[FOURTH_E]], [[FOURTH_RCP]]
 ; SI-DAG: v_subrev_i32_e32 [[FOURTH_RCP_S_E:v[0-9]+]], [[FOURTH_E]], [[FOURTH_RCP]]
 ; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_mul_hi_u32 [[FOURTH_Quotient:v[0-9]+]]
-; SI-DAG: v_mul_lo_i32 [[FOURTH_Num_S_Remainder:v[0-9]+]]
-; SI-DAG: v_sub_i32_e32 [[FOURTH_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[FOURTH_Num_S_Remainder]]
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_and_b32_e32 [[FOURTH_Tmp1:v[0-9]+]]
-; SI-DAG: v_add_i32_e32 [[FOURTH_Quotient_A_One:v[0-9]+]], {{.*}}, [[FOURTH_Quotient]]
-; SI-DAG: v_subrev_i32_e32 [[FOURTH_Quotient_S_One:v[0-9]+]],
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_i32_e32 [[FOURTH_Remainder_A_Den:v[0-9]+]],
-; SI-DAG: v_subrev_i32_e32 [[FOURTH_Remainder_S_Den:v[0-9]+]],
-; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_cndmask_b32_e64
 ; SI: s_endpgm
 define void @test_udivrem_v4(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
   %result0 = udiv <4 x i32> %x, %y
diff --git a/test/CodeGen/R600/udivrem24.ll b/test/CodeGen/R600/udivrem24.ll
index 4b98ac67b220..4de881b66f10 100644
--- a/test/CodeGen/R600/udivrem24.ll
+++ b/test/CodeGen/R600/udivrem24.ll
@@ -13,9 +13,9 @@
 ; EG-DAG: RECIP_IEEE
 ; EG: FLT_TO_UINT
 define void @udiv24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
-  %den_ptr = getelementptr i8 addrspace(1)* %in, i8 1
-  %num = load i8 addrspace(1) * %in
-  %den = load i8 addrspace(1) * %den_ptr
+  %den_ptr = getelementptr i8, i8 addrspace(1)* %in, i8 1
+  %num = load i8, i8 addrspace(1) * %in
+  %den = load i8, i8 addrspace(1) * %den_ptr
   %result = udiv i8 %num, %den
   store i8 %result, i8 addrspace(1)* %out
   ret void
@@ -32,9 +32,9 @@ define void @udiv24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
 ; EG-DAG: RECIP_IEEE
 ; EG: FLT_TO_UINT
 define void @udiv24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
-  %den_ptr = getelementptr i16 addrspace(1)* %in, i16 1
-  %num = load i16 addrspace(1) * %in, align 2
-  %den = load i16 addrspace(1) * %den_ptr, align 2
+  %den_ptr = getelementptr i16, i16 addrspace(1)* %in, i16 1
+  %num = load i16, i16 addrspace(1) * %in, align 2
+  %den = load i16, i16 addrspace(1) * %den_ptr, align 2
   %result = udiv i16 %num, %den
   store i16 %result, i16 addrspace(1)* %out, align 2
   ret void
@@ -51,9 +51,9 @@ define void @udiv24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
 ; EG-DAG: RECIP_IEEE
 ; EG: FLT_TO_UINT
 define void @udiv24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 8
   %den.i24.0 = shl i32 %den, 8
   %num.i24 = lshr i32 %num.i24.0, 8
@@ -71,9 +71,9 @@ define void @udiv24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 ; EG-NOT: UINT_TO_FLT
 ; EG-NOT: RECIP_IEEE
 define void @udiv25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 7
   %den.i24.0 = shl i32 %den, 7
   %num.i24 = lshr i32 %num.i24.0, 7
@@ -91,9 +91,9 @@ define void @udiv25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 ; EG-NOT: UINT_TO_FLT
 ; EG-NOT: RECIP_IEEE
 define void @test_no_udiv24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 8
   %den.i24.0 = shl i32 %den, 7
   %num.i24 = lshr i32 %num.i24.0, 8
@@ -111,9 +111,9 @@ define void @test_no_udiv24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in)
 ; EG-NOT: UINT_TO_FLT
 ; EG-NOT: RECIP_IEEE
 define void @test_no_udiv24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 7
   %den.i24.0 = shl i32 %den, 8
   %num.i24 = lshr i32 %num.i24.0, 7
@@ -134,9 +134,9 @@ define void @test_no_udiv24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in)
 ; EG-DAG: RECIP_IEEE
 ; EG: FLT_TO_UINT
 define void @urem24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
-  %den_ptr = getelementptr i8 addrspace(1)* %in, i8 1
-  %num = load i8 addrspace(1) * %in
-  %den = load i8 addrspace(1) * %den_ptr
+  %den_ptr = getelementptr i8, i8 addrspace(1)* %in, i8 1
+  %num = load i8, i8 addrspace(1) * %in
+  %den = load i8, i8 addrspace(1) * %den_ptr
   %result = urem i8 %num, %den
   store i8 %result, i8 addrspace(1)* %out
   ret void
@@ -153,9 +153,9 @@ define void @urem24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
 ; EG-DAG: RECIP_IEEE
 ; EG: FLT_TO_UINT
 define void @urem24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
-  %den_ptr = getelementptr i16 addrspace(1)* %in, i16 1
-  %num = load i16 addrspace(1) * %in, align 2
-  %den = load i16 addrspace(1) * %den_ptr, align 2
+  %den_ptr = getelementptr i16, i16 addrspace(1)* %in, i16 1
+  %num = load i16, i16 addrspace(1) * %in, align 2
+  %den = load i16, i16 addrspace(1) * %den_ptr, align 2
   %result = urem i16 %num, %den
   store i16 %result, i16 addrspace(1)* %out, align 2
   ret void
@@ -172,9 +172,9 @@ define void @urem24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
 ; EG-DAG: RECIP_IEEE
 ; EG: FLT_TO_UINT
 define void @urem24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 8
   %den.i24.0 = shl i32 %den, 8
   %num.i24 = lshr i32 %num.i24.0, 8
@@ -192,9 +192,9 @@ define void @urem24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 ; EG-NOT: UINT_TO_FLT
 ; EG-NOT: RECIP_IEEE
 define void @urem25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 7
   %den.i24.0 = shl i32 %den, 7
   %num.i24 = lshr i32 %num.i24.0, 7
@@ -212,9 +212,9 @@ define void @urem25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 ; EG-NOT: UINT_TO_FLT
 ; EG-NOT: RECIP_IEEE
 define void @test_no_urem24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 8
   %den.i24.0 = shl i32 %den, 7
   %num.i24 = lshr i32 %num.i24.0, 8
@@ -232,9 +232,9 @@ define void @test_no_urem24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in)
 ; EG-NOT: UINT_TO_FLT
 ; EG-NOT: RECIP_IEEE
 define void @test_no_urem24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %num = load i32 addrspace(1) * %in, align 4
-  %den = load i32 addrspace(1) * %den_ptr, align 4
+  %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %num = load i32, i32 addrspace(1) * %in, align 4
+  %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 7
   %den.i24.0 = shl i32 %den, 8
   %num.i24 = lshr i32 %num.i24.0, 7
diff --git a/test/CodeGen/R600/udivrem64.ll b/test/CodeGen/R600/udivrem64.ll
index 77922fe8dab6..9f3069bdf80c 100644
--- a/test/CodeGen/R600/udivrem64.ll
+++ b/test/CodeGen/R600/udivrem64.ll
@@ -1,5 +1,5 @@
-;RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s
-;RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s
+;RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC %s
+;RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC %s
 ;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
 
 ;FUNC-LABEL: {{^}}test_udiv:
@@ -35,7 +35,41 @@
 ;EG: BFE_UINT
 ;EG: BFE_UINT
 ;EG: BFE_UINT
-;SI: s_endpgm
+
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN-NOT: v_mad_f32
+;SI-NOT: v_lshr_b64
+;VI-NOT: v_lshrrev_b64
+;GCN: s_endpgm
 define void @test_udiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
   %result = udiv i64 %x, %y
   store i64 %result, i64 addrspace(1)* %out
@@ -75,9 +109,115 @@ define void @test_udiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ;EG: BFE_UINT
 ;EG: BFE_UINT
 ;EG: AND_INT {{.*}}, 1,
-;SI: s_endpgm
+
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN: s_bfe_u32
+;GCN-NOT: v_mad_f32
+;SI-NOT: v_lshr_b64
+;VI-NOT: v_lshrrev_b64
+;GCN: s_endpgm
 define void @test_urem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
   %result = urem i64 %x, %y
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
+
+;FUNC-LABEL: {{^}}test_udiv3264:
+;EG: RECIP_UINT
+;EG-NOT: BFE_UINT
+
+;GCN-NOT: s_bfe_u32
+;GCN-NOT: v_mad_f32
+;SI-NOT: v_lshr_b64
+;VI-NOT: v_lshrrev_b64
+;GCN: s_endpgm
+define void @test_udiv3264(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+  %1 = lshr i64 %x, 33
+  %2 = lshr i64 %y, 33
+  %result = udiv i64 %1, %2
+  store i64 %result, i64 addrspace(1)* %out
+  ret void
+}
+
+;FUNC-LABEL: {{^}}test_urem3264:
+;EG: RECIP_UINT
+;EG-NOT: BFE_UINT
+
+;GCN-NOT: s_bfe_u32
+;GCN-NOT: v_mad_f32
+;SI-NOT: v_lshr_b64
+;VI-NOT: v_lshrrev_b64
+;GCN: s_endpgm
+define void @test_urem3264(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+  %1 = lshr i64 %x, 33
+  %2 = lshr i64 %y, 33
+  %result = urem i64 %1, %2
+  store i64 %result, i64 addrspace(1)* %out
+  ret void
+}
+
+;FUNC-LABEL: {{^}}test_udiv2464:
+;EG: UINT_TO_FLT
+;EG: UINT_TO_FLT
+;EG: FLT_TO_UINT
+;EG-NOT: RECIP_UINT
+;EG-NOT: BFE_UINT
+
+;SI-NOT: v_lshr_b64
+;VI-NOT: v_lshrrev_b64
+;GCN: v_mad_f32
+;GCN: s_endpgm
+define void @test_udiv2464(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+  %1 = lshr i64 %x, 40
+  %2 = lshr i64 %y, 40
+  %result = udiv i64 %1, %2
+  store i64 %result, i64 addrspace(1)* %out
+  ret void
+}
+
+;FUNC-LABEL: {{^}}test_urem2464:
+;EG: UINT_TO_FLT
+;EG: UINT_TO_FLT
+;EG: FLT_TO_UINT
+;EG-NOT: RECIP_UINT
+;EG-NOT: BFE_UINT
+
+;SI-NOT: v_lshr_b64
+;VI-NOT: v_lshrrev_b64
+;GCN: v_mad_f32
+;GCN: s_endpgm
+define void @test_urem2464(i64 addrspace(1)* %out, i64 %x, i64 %y) {
+  %1 = lshr i64 %x, 40
+  %2 = lshr i64 %y, 40
+  %result = urem i64 %1, %2
+  store i64 %result, i64 addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/uint_to_fp.f64.ll b/test/CodeGen/R600/uint_to_fp.f64.ll
index 09e987dd14da..dfec8eb15cb7 100644
--- a/test/CodeGen/R600/uint_to_fp.f64.ll
+++ b/test/CodeGen/R600/uint_to_fp.f64.ll
@@ -11,8 +11,8 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone
 ; SI: buffer_store_dwordx2 [[RESULT]]
 define void @v_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) {
   %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
-  %gep = getelementptr i64 addrspace(1)* %in, i32 %tid
-  %val = load i64 addrspace(1)* %gep, align 8
+  %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
+  %val = load i64, i64 addrspace(1)* %gep, align 8
   %result = uitofp i64 %val to double
   store double %result, double addrspace(1)* %out
   ret void
@@ -70,12 +70,13 @@ define void @s_uint_to_fp_v4i32_to_v4f64(<4 x double> addrspace(1)* %out, <4 x i
   ret void
 }
 
+; FIXME: select on 0, 0
 ; SI-LABEL: {{^}}uint_to_fp_i1_to_f64:
 ; SI: v_cmp_eq_i32_e64 [[CMP:s\[[0-9]+:[0-9]\]]],
 ; We can't fold the SGPRs into v_cndmask_b32_e64, because it already
 ; uses an SGPR for [[CMP]]
 ; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, v{{[0-9]+}}, [[CMP]]
-; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, v{{[0-9]+}}, [[CMP]]
+; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 0, [[CMP]]
 ; SI: buffer_store_dwordx2
 ; SI: s_endpgm
 define void @uint_to_fp_i1_to_f64(double addrspace(1)* %out, i32 %in) {
diff --git a/test/CodeGen/R600/uint_to_fp.ll b/test/CodeGen/R600/uint_to_fp.ll
index cf14c25759f7..00fea80b1bc8 100644
--- a/test/CodeGen/R600/uint_to_fp.ll
+++ b/test/CodeGen/R600/uint_to_fp.ll
@@ -38,7 +38,7 @@ define void @uint_to_fp_v2i32_to_v2f32(<2 x float> addrspace(1)* %out, <2 x i32>
 ; SI: v_cvt_f32_u32_e32
 ; SI: s_endpgm
 define void @uint_to_fp_v4i32_to_v4f32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %value = load <4 x i32> addrspace(1) * %in
+  %value = load <4 x i32>, <4 x i32> addrspace(1) * %in
   %result = uitofp <4 x i32> %value to <4 x float>
   store <4 x float> %result, <4 x float> addrspace(1)* %out
   ret void
@@ -50,7 +50,7 @@ define void @uint_to_fp_v4i32_to_v4f32(<4 x float> addrspace(1)* %out, <4 x i32>
 ; R600: MULADD_IEEE
 ; SI: v_cvt_f32_u32_e32
 ; SI: v_cvt_f32_u32_e32
-; SI: v_mad_f32
+; SI: v_madmk_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, 0x4f800000
 ; SI: s_endpgm
 define void @uint_to_fp_i64_to_f32(float addrspace(1)* %out, i64 %in) {
 entry:
diff --git a/test/CodeGen/R600/unaligned-load-store.ll b/test/CodeGen/R600/unaligned-load-store.ll
index 665dc37c200a..82d88ebd3ae7 100644
--- a/test/CodeGen/R600/unaligned-load-store.ll
+++ b/test/CodeGen/R600/unaligned-load-store.ll
@@ -8,7 +8,7 @@
 ; SI: ds_write_b8
 ; SI: s_endpgm
 define void @unaligned_load_store_i16_local(i16 addrspace(3)* %p, i16 addrspace(3)* %r) nounwind {
-  %v = load i16 addrspace(3)* %p, align 1
+  %v = load i16, i16 addrspace(3)* %p, align 1
   store i16 %v, i16 addrspace(3)* %r, align 1
   ret void
 }
@@ -20,7 +20,7 @@ define void @unaligned_load_store_i16_local(i16 addrspace(3)* %p, i16 addrspace(
 ; SI: buffer_store_byte
 ; SI: s_endpgm
 define void @unaligned_load_store_i16_global(i16 addrspace(1)* %p, i16 addrspace(1)* %r) nounwind {
-  %v = load i16 addrspace(1)* %p, align 1
+  %v = load i16, i16 addrspace(1)* %p, align 1
   store i16 %v, i16 addrspace(1)* %r, align 1
   ret void
 }
@@ -36,7 +36,7 @@ define void @unaligned_load_store_i16_global(i16 addrspace(1)* %p, i16 addrspace
 ; SI: ds_write_b8
 ; SI: s_endpgm
 define void @unaligned_load_store_i32_local(i32 addrspace(3)* %p, i32 addrspace(3)* %r) nounwind {
-  %v = load i32 addrspace(3)* %p, align 1
+  %v = load i32, i32 addrspace(3)* %p, align 1
   store i32 %v, i32 addrspace(3)* %r, align 1
   ret void
 }
@@ -51,7 +51,7 @@ define void @unaligned_load_store_i32_local(i32 addrspace(3)* %p, i32 addrspace(
 ; SI: buffer_store_byte
 ; SI: buffer_store_byte
 define void @unaligned_load_store_i32_global(i32 addrspace(1)* %p, i32 addrspace(1)* %r) nounwind {
-  %v = load i32 addrspace(1)* %p, align 1
+  %v = load i32, i32 addrspace(1)* %p, align 1
   store i32 %v, i32 addrspace(1)* %r, align 1
   ret void
 }
@@ -75,7 +75,7 @@ define void @unaligned_load_store_i32_global(i32 addrspace(1)* %p, i32 addrspace
 ; SI: ds_write_b8
 ; SI: s_endpgm
 define void @unaligned_load_store_i64_local(i64 addrspace(3)* %p, i64 addrspace(3)* %r) {
-  %v = load i64 addrspace(3)* %p, align 1
+  %v = load i64, i64 addrspace(3)* %p, align 1
   store i64 %v, i64 addrspace(3)* %r, align 1
   ret void
 }
@@ -98,7 +98,7 @@ define void @unaligned_load_store_i64_local(i64 addrspace(3)* %p, i64 addrspace(
 ; SI: buffer_store_byte
 ; SI: buffer_store_byte
 define void @unaligned_load_store_i64_global(i64 addrspace(1)* %p, i64 addrspace(1)* %r) {
-  %v = load i64 addrspace(1)* %p, align 1
+  %v = load i64, i64 addrspace(1)* %p, align 1
   store i64 %v, i64 addrspace(1)* %r, align 1
   ret void
 }
@@ -145,7 +145,7 @@ define void @unaligned_load_store_i64_global(i64 addrspace(1)* %p, i64 addrspace
 ; SI: ds_write_b8
 ; SI: s_endpgm
 define void @unaligned_load_store_v4i32_local(<4 x i32> addrspace(3)* %p, <4 x i32> addrspace(3)* %r) nounwind {
-  %v = load <4 x i32> addrspace(3)* %p, align 1
+  %v = load <4 x i32>, <4 x i32> addrspace(3)* %p, align 1
   store <4 x i32> %v, <4 x i32> addrspace(3)* %r, align 1
   ret void
 }
@@ -169,7 +169,7 @@ define void @unaligned_load_store_v4i32_local(<4 x i32> addrspace(3)* %p, <4 x i
 ; FIXME-SI: buffer_load_ubyte
 ; FIXME-SI: buffer_load_ubyte
 define void @unaligned_load_store_v4i32_global(<4 x i32> addrspace(1)* %p, <4 x i32> addrspace(1)* %r) nounwind {
-  %v = load <4 x i32> addrspace(1)* %p, align 1
+  %v = load <4 x i32>, <4 x i32> addrspace(1)* %p, align 1
   store <4 x i32> %v, <4 x i32> addrspace(1)* %r, align 1
   ret void
 }
@@ -178,7 +178,7 @@ define void @unaligned_load_store_v4i32_global(<4 x i32> addrspace(1)* %p, <4 x
 ; SI: ds_read2_b32
 ; SI: s_endpgm
 define void @load_lds_i64_align_4(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
-  %val = load i64 addrspace(3)* %in, align 4
+  %val = load i64, i64 addrspace(3)* %in, align 4
   store i64 %val, i64 addrspace(1)* %out, align 8
   ret void
 }
@@ -187,21 +187,21 @@ define void @load_lds_i64_align_4(i64 addrspace(1)* nocapture %out, i64 addrspac
 ; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset0:8 offset1:9
 ; SI: s_endpgm
 define void @load_lds_i64_align_4_with_offset(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
-  %ptr = getelementptr i64 addrspace(3)* %in, i32 4
-  %val = load i64 addrspace(3)* %ptr, align 4
+  %ptr = getelementptr i64, i64 addrspace(3)* %in, i32 4
+  %val = load i64, i64 addrspace(3)* %ptr, align 4
   store i64 %val, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 ; SI-LABEL: {{^}}load_lds_i64_align_4_with_split_offset:
 ; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits
-; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset0:0 offset1:1
+; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset1:1
 ; SI: s_endpgm
 define void @load_lds_i64_align_4_with_split_offset(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
   %ptr = bitcast i64 addrspace(3)* %in to i32 addrspace(3)*
-  %ptr255 = getelementptr i32 addrspace(3)* %ptr, i32 255
+  %ptr255 = getelementptr i32, i32 addrspace(3)* %ptr, i32 255
   %ptri64 = bitcast i32 addrspace(3)* %ptr255 to i64 addrspace(3)*
-  %val = load i64 addrspace(3)* %ptri64, align 4
+  %val = load i64, i64 addrspace(3)* %ptri64, align 4
   store i64 %val, i64 addrspace(1)* %out, align 8
   ret void
 }
@@ -219,7 +219,7 @@ define void @load_lds_i64_align_4_with_split_offset(i64 addrspace(1)* nocapture
 ; SI: s_endpgm
 
 define void @load_lds_i64_align_1(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
-  %val = load i64 addrspace(3)* %in, align 1
+  %val = load i64, i64 addrspace(3)* %in, align 1
   store i64 %val, i64 addrspace(1)* %out, align 8
   ret void
 }
@@ -236,18 +236,18 @@ define void @store_lds_i64_align_4(i64 addrspace(3)* %out, i64 %val) #0 {
 ; SI: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:8 offset1:9
 ; SI: s_endpgm
 define void @store_lds_i64_align_4_with_offset(i64 addrspace(3)* %out) #0 {
-  %ptr = getelementptr i64 addrspace(3)* %out, i32 4
+  %ptr = getelementptr i64, i64 addrspace(3)* %out, i32 4
   store i64 0, i64 addrspace(3)* %ptr, align 4
   ret void
 }
 
 ; SI-LABEL: {{^}}store_lds_i64_align_4_with_split_offset:
 ; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits
-; SI: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1
+; SI: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1
 ; SI: s_endpgm
 define void @store_lds_i64_align_4_with_split_offset(i64 addrspace(3)* %out) #0 {
   %ptr = bitcast i64 addrspace(3)* %out to i32 addrspace(3)*
-  %ptr255 = getelementptr i32 addrspace(3)* %ptr, i32 255
+  %ptr255 = getelementptr i32, i32 addrspace(3)* %ptr, i32 255
   %ptri64 = bitcast i32 addrspace(3)* %ptr255 to i64 addrspace(3)*
   store i64 0, i64 addrspace(3)* %out, align 4
   ret void
diff --git a/test/CodeGen/R600/unhandled-loop-condition-assertion.ll b/test/CodeGen/R600/unhandled-loop-condition-assertion.ll
index c615f0b84913..036a7e91b47f 100644
--- a/test/CodeGen/R600/unhandled-loop-condition-assertion.ll
+++ b/test/CodeGen/R600/unhandled-loop-condition-assertion.ll
@@ -20,20 +20,20 @@ for.body.lr.ph:                                   ; preds = %entry
 for.body:                                         ; preds = %for.body, %for.body.lr.ph
   %main.addr.011 = phi i8 addrspace(1)* [ %main, %for.body.lr.ph ], [ %add.ptr6, %for.body ]
   %0 = bitcast i8 addrspace(1)* %main.addr.011 to i32 addrspace(1)*
-  %1 = load i32 addrspace(1)* %0, align 4
-  %add.ptr = getelementptr inbounds i8 addrspace(1)* %main.addr.011, i32 %main_stride
+  %1 = load i32, i32 addrspace(1)* %0, align 4
+  %add.ptr = getelementptr inbounds i8, i8 addrspace(1)* %main.addr.011, i32 %main_stride
   %2 = bitcast i8 addrspace(1)* %add.ptr to i32 addrspace(1)*
-  %3 = load i32 addrspace(1)* %2, align 4
-  %add.ptr1 = getelementptr inbounds i8 addrspace(1)* %main.addr.011, i32 %add.ptr.sum
+  %3 = load i32, i32 addrspace(1)* %2, align 4
+  %add.ptr1 = getelementptr inbounds i8, i8 addrspace(1)* %main.addr.011, i32 %add.ptr.sum
   %4 = bitcast i8 addrspace(1)* %add.ptr1 to i32 addrspace(1)*
-  %5 = load i32 addrspace(1)* %4, align 4
-  %add.ptr2 = getelementptr inbounds i8 addrspace(1)* %main.addr.011, i32 %add.ptr1.sum
+  %5 = load i32, i32 addrspace(1)* %4, align 4
+  %add.ptr2 = getelementptr inbounds i8, i8 addrspace(1)* %main.addr.011, i32 %add.ptr1.sum
   %6 = bitcast i8 addrspace(1)* %add.ptr2 to i32 addrspace(1)*
-  %7 = load i32 addrspace(1)* %6, align 4
-  %add.ptr3 = getelementptr inbounds i8 addrspace(1)* %main.addr.011, i32 %add.ptr4.sum
+  %7 = load i32, i32 addrspace(1)* %6, align 4
+  %add.ptr3 = getelementptr inbounds i8, i8 addrspace(1)* %main.addr.011, i32 %add.ptr4.sum
   %8 = bitcast i8 addrspace(1)* %add.ptr3 to i32 addrspace(1)*
-  %9 = load i32 addrspace(1)* %8, align 4
-  %add.ptr6 = getelementptr inbounds i8 addrspace(1)* %main.addr.011, i32 undef
+  %9 = load i32, i32 addrspace(1)* %8, align 4
+  %add.ptr6 = getelementptr inbounds i8, i8 addrspace(1)* %main.addr.011, i32 undef
   br i1 undef, label %for.end, label %for.body
 
 for.end:                                          ; preds = %for.body, %entry
@@ -56,20 +56,20 @@ for.body.lr.ph:                                   ; preds = %entry
 for.body:                                         ; preds = %for.body, %for.body.lr.ph
   %main.addr.011 = phi i8 addrspace(1)* [ %main, %for.body.lr.ph ], [ %add.ptr6, %for.body ]
   %0 = bitcast i8 addrspace(1)* %main.addr.011 to i32 addrspace(1)*
-  %1 = load i32 addrspace(1)* %0, align 4
-  %add.ptr = getelementptr inbounds i8 addrspace(1)* %main.addr.011, i32 %main_stride
+  %1 = load i32, i32 addrspace(1)* %0, align 4
+  %add.ptr = getelementptr inbounds i8, i8 addrspace(1)* %main.addr.011, i32 %main_stride
   %2 = bitcast i8 addrspace(1)* %add.ptr to i32 addrspace(1)*
-  %3 = load i32 addrspace(1)* %2, align 4
-  %add.ptr1 = getelementptr inbounds i8 addrspace(1)* %main.addr.011, i32 %add.ptr.sum
+  %3 = load i32, i32 addrspace(1)* %2, align 4
+  %add.ptr1 = getelementptr inbounds i8, i8 addrspace(1)* %main.addr.011, i32 %add.ptr.sum
   %4 = bitcast i8 addrspace(1)* %add.ptr1 to i32 addrspace(1)*
-  %5 = load i32 addrspace(1)* %4, align 4
-  %add.ptr2 = getelementptr inbounds i8 addrspace(1)* %main.addr.011, i32 %add.ptr1.sum
+  %5 = load i32, i32 addrspace(1)* %4, align 4
+  %add.ptr2 = getelementptr inbounds i8, i8 addrspace(1)* %main.addr.011, i32 %add.ptr1.sum
   %6 = bitcast i8 addrspace(1)* %add.ptr2 to i32 addrspace(1)*
-  %7 = load i32 addrspace(1)* %6, align 4
-  %add.ptr3 = getelementptr inbounds i8 addrspace(1)* %main.addr.011, i32 %add.ptr4.sum
+  %7 = load i32, i32 addrspace(1)* %6, align 4
+  %add.ptr3 = getelementptr inbounds i8, i8 addrspace(1)* %main.addr.011, i32 %add.ptr4.sum
   %8 = bitcast i8 addrspace(1)* %add.ptr3 to i32 addrspace(1)*
-  %9 = load i32 addrspace(1)* %8, align 4
-  %add.ptr6 = getelementptr inbounds i8 addrspace(1)* %main.addr.011, i32 undef
+  %9 = load i32, i32 addrspace(1)* %8, align 4
+  %add.ptr6 = getelementptr inbounds i8, i8 addrspace(1)* %main.addr.011, i32 undef
   br i1 undef, label %for.end, label %for.body
 
 for.end:                                          ; preds = %for.body, %entry
@@ -92,20 +92,20 @@ for.body.lr.ph:                                   ; preds = %entry
 for.body:                                         ; preds = %for.body, %for.body.lr.ph
   %main.addr.011 = phi i8 addrspace(1)* [ %main, %for.body.lr.ph ], [ %add.ptr6, %for.body ]
   %0 = bitcast i8 addrspace(1)* %main.addr.011 to i32 addrspace(1)*
-  %1 = load i32 addrspace(1)* %0, align 4
-  %add.ptr = getelementptr inbounds i8 addrspace(1)* %main.addr.011, i32 %main_stride
+  %1 = load i32, i32 addrspace(1)* %0, align 4
+  %add.ptr = getelementptr inbounds i8, i8 addrspace(1)* %main.addr.011, i32 %main_stride
   %2 = bitcast i8 addrspace(1)* %add.ptr to i32 addrspace(1)*
-  %3 = load i32 addrspace(1)* %2, align 4
-  %add.ptr1 = getelementptr inbounds i8 addrspace(1)* %main.addr.011, i32 %add.ptr.sum
+  %3 = load i32, i32 addrspace(1)* %2, align 4
+  %add.ptr1 = getelementptr inbounds i8, i8 addrspace(1)* %main.addr.011, i32 %add.ptr.sum
   %4 = bitcast i8 addrspace(1)* %add.ptr1 to i32 addrspace(1)*
-  %5 = load i32 addrspace(1)* %4, align 4
-  %add.ptr2 = getelementptr inbounds i8 addrspace(1)* %main.addr.011, i32 %add.ptr1.sum
+  %5 = load i32, i32 addrspace(1)* %4, align 4
+  %add.ptr2 = getelementptr inbounds i8, i8 addrspace(1)* %main.addr.011, i32 %add.ptr1.sum
   %6 = bitcast i8 addrspace(1)* %add.ptr2 to i32 addrspace(1)*
-  %7 = load i32 addrspace(1)* %6, align 4
-  %add.ptr3 = getelementptr inbounds i8 addrspace(1)* %main.addr.011, i32 %add.ptr4.sum
+  %7 = load i32, i32 addrspace(1)* %6, align 4
+  %add.ptr3 = getelementptr inbounds i8, i8 addrspace(1)* %main.addr.011, i32 %add.ptr4.sum
   %8 = bitcast i8 addrspace(1)* %add.ptr3 to i32 addrspace(1)*
-  %9 = load i32 addrspace(1)* %8, align 4
-  %add.ptr6 = getelementptr inbounds i8 addrspace(1)* %main.addr.011, i32 undef
+  %9 = load i32, i32 addrspace(1)* %8, align 4
+  %add.ptr6 = getelementptr inbounds i8, i8 addrspace(1)* %main.addr.011, i32 undef
   br i1 undef, label %for.end, label %for.body
 
 for.end:                                          ; preds = %for.body, %entry
diff --git a/test/CodeGen/R600/unroll.ll b/test/CodeGen/R600/unroll.ll
index e0035eae71cf..ca8d822ec7ed 100644
--- a/test/CodeGen/R600/unroll.ll
+++ b/test/CodeGen/R600/unroll.ll
@@ -20,7 +20,7 @@ loop.header:
   br label %loop.body
 
 loop.body:
-  %ptr = getelementptr [32 x i32]* %0, i32 0, i32 %counter
+  %ptr = getelementptr [32 x i32], [32 x i32]* %0, i32 0, i32 %counter
   store i32 %counter, i32* %ptr
   br label %loop.inc
 
@@ -30,8 +30,8 @@ loop.inc:
   br i1 %1, label  %exit, label %loop.header
 
 exit:
-  %2 = getelementptr [32 x i32]* %0, i32 0, i32 5
-  %3 = load i32* %2
+  %2 = getelementptr [32 x i32], [32 x i32]* %0, i32 0, i32 5
+  %3 = load i32, i32* %2
   store i32 %3, i32 addrspace(1)* %out
   ret void
 }
diff --git a/test/CodeGen/R600/urem.ll b/test/CodeGen/R600/urem.ll
index dce517fcd823..62841ec2d6c5 100644
--- a/test/CodeGen/R600/urem.ll
+++ b/test/CodeGen/R600/urem.ll
@@ -10,21 +10,36 @@
 ; SI: s_endpgm
 ; EG: CF_END
 define void @test_urem_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
-  %a = load i32 addrspace(1)* %in
-  %b = load i32 addrspace(1)* %b_ptr
+  %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
+  %a = load i32, i32 addrspace(1)* %in
+  %b = load i32, i32 addrspace(1)* %b_ptr
   %result = urem i32 %a, %b
   store i32 %result, i32 addrspace(1)* %out
   ret void
 }
 
+; FUNC-LABEL: {{^}}test_urem_i32_7:
+; SI: v_mov_b32_e32 [[MAGIC:v[0-9]+]], 0x24924925
+; SI: v_mul_hi_u32 {{v[0-9]+}}, [[MAGIC]]
+; SI: v_subrev_i32
+; SI: v_mul_lo_i32
+; SI: v_sub_i32
+; SI: buffer_store_dword
+; SI: s_endpgm
+define void @test_urem_i32_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
+  %num = load i32, i32 addrspace(1) * %in
+  %result = urem i32 %num, 7
+  store i32 %result, i32 addrspace(1)* %out
+  ret void
+}
+
 ; FUNC-LABEL: {{^}}test_urem_v2i32:
 ; SI: s_endpgm
 ; EG: CF_END
 define void @test_urem_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
-  %a = load <2 x i32> addrspace(1)* %in
-  %b = load <2 x i32> addrspace(1)* %b_ptr
+  %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32>, <2 x i32> addrspace(1)* %in
+  %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
   %result = urem <2 x i32> %a, %b
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
   ret void
@@ -34,9 +49,9 @@ define void @test_urem_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1
 ; SI: s_endpgm
 ; EG: CF_END
 define void @test_urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
-  %a = load <4 x i32> addrspace(1)* %in
-  %b = load <4 x i32> addrspace(1)* %b_ptr
+  %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
+  %a = load <4 x i32>, <4 x i32> addrspace(1)* %in
+  %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
   %result = urem <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
@@ -46,9 +61,9 @@ define void @test_urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1
 ; SI: s_endpgm
 ; EG: CF_END
 define void @test_urem_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
-  %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1
-  %a = load i64 addrspace(1)* %in
-  %b = load i64 addrspace(1)* %b_ptr
+  %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
+  %a = load i64, i64 addrspace(1)* %in
+  %b = load i64, i64 addrspace(1)* %b_ptr
   %result = urem i64 %a, %b
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -58,9 +73,9 @@ define void @test_urem_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
 ; SI: s_endpgm
 ; EG: CF_END
 define void @test_urem_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
-  %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1
-  %a = load <2 x i64> addrspace(1)* %in
-  %b = load <2 x i64> addrspace(1)* %b_ptr
+  %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1
+  %a = load <2 x i64>, <2 x i64> addrspace(1)* %in
+  %b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr
   %result = urem <2 x i64> %a, %b
   store <2 x i64> %result, <2 x i64> addrspace(1)* %out
   ret void
@@ -70,9 +85,9 @@ define void @test_urem_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1
 ; SI: s_endpgm
 ; EG: CF_END
 define void @test_urem_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
-  %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1
-  %a = load <4 x i64> addrspace(1)* %in
-  %b = load <4 x i64> addrspace(1)* %b_ptr
+  %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
+  %a = load <4 x i64>, <4 x i64> addrspace(1)* %in
+  %b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr
   %result = urem <4 x i64> %a, %b
   store <4 x i64> %result, <4 x i64> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/use-sgpr-multiple-times.ll b/test/CodeGen/R600/use-sgpr-multiple-times.ll
index 97d73ba74bc5..f26f30022b4f 100644
--- a/test/CodeGen/R600/use-sgpr-multiple-times.ll
+++ b/test/CodeGen/R600/use-sgpr-multiple-times.ll
@@ -1,80 +1,87 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
 
 declare float @llvm.fma.f32(float, float, float) #1
 declare float @llvm.fmuladd.f32(float, float, float) #1
 declare i32 @llvm.AMDGPU.imad24(i32, i32, i32) #1
 
 
-; SI-LABEL: {{^}}test_sgpr_use_twice_binop:
-; SI: s_load_dword [[SGPR:s[0-9]+]],
-; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]]
-; SI: buffer_store_dword [[RESULT]]
+; GCN-LABEL: {{^}}test_sgpr_use_twice_binop:
+; GCN: s_load_dword [[SGPR:s[0-9]+]],
+; GCN: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]]
+; GCN: buffer_store_dword [[RESULT]]
 define void @test_sgpr_use_twice_binop(float addrspace(1)* %out, float %a) #0 {
   %dbl = fadd float %a, %a
   store float %dbl, float addrspace(1)* %out, align 4
   ret void
 }
 
-; SI-LABEL: {{^}}test_sgpr_use_three_ternary_op:
-; SI: s_load_dword [[SGPR:s[0-9]+]],
-; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]]
-; SI: buffer_store_dword [[RESULT]]
+; GCN-LABEL: {{^}}test_sgpr_use_three_ternary_op:
+; GCN: s_load_dword [[SGPR:s[0-9]+]],
+; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]]
+; GCN: buffer_store_dword [[RESULT]]
 define void @test_sgpr_use_three_ternary_op(float addrspace(1)* %out, float %a) #0 {
   %fma = call float @llvm.fma.f32(float %a, float %a, float %a) #1
   store float %fma, float addrspace(1)* %out, align 4
   ret void
 }
 
-; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_b:
+; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_b:
 ; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
 ; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; SI: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
-; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[SGPR0]], [[VGPR1]]
-; SI: buffer_store_dword [[RESULT]]
+; VI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; VI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
+; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
+; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[SGPR0]], [[VGPR1]]
+; GCN: buffer_store_dword [[RESULT]]
 define void @test_sgpr_use_twice_ternary_op_a_a_b(float addrspace(1)* %out, float %a, float %b) #0 {
   %fma = call float @llvm.fma.f32(float %a, float %a, float %b) #1
   store float %fma, float addrspace(1)* %out, align 4
   ret void
 }
 
-; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_b_a:
+; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_b_a:
 ; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
 ; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; SI: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
-; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], [[SGPR0]], [[SGPR0]]
-; SI: buffer_store_dword [[RESULT]]
+; VI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; VI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
+; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
+; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], [[SGPR0]], [[SGPR0]]
+; GCN: buffer_store_dword [[RESULT]]
 define void @test_sgpr_use_twice_ternary_op_a_b_a(float addrspace(1)* %out, float %a, float %b) #0 {
   %fma = call float @llvm.fma.f32(float %a, float %b, float %a) #1
   store float %fma, float addrspace(1)* %out, align 4
   ret void
 }
 
-; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_b_a_a:
+; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_b_a_a:
 ; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
 ; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; SI: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
-; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[VGPR1]], [[SGPR0]]
-; SI: buffer_store_dword [[RESULT]]
+; VI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; VI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
+; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
+; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[VGPR1]], [[SGPR0]]
+; GCN: buffer_store_dword [[RESULT]]
 define void @test_sgpr_use_twice_ternary_op_b_a_a(float addrspace(1)* %out, float %a, float %b) #0 {
   %fma = call float @llvm.fma.f32(float %b, float %a, float %a) #1
   store float %fma, float addrspace(1)* %out, align 4
   ret void
 }
 
-; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_imm:
-; SI: s_load_dword [[SGPR:s[0-9]+]]
-; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], 2.0
-; SI: buffer_store_dword [[RESULT]]
+; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_imm:
+; GCN: s_load_dword [[SGPR:s[0-9]+]]
+; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], 2.0
+; GCN: buffer_store_dword [[RESULT]]
 define void @test_sgpr_use_twice_ternary_op_a_a_imm(float addrspace(1)* %out, float %a) #0 {
   %fma = call float @llvm.fma.f32(float %a, float %a, float 2.0) #1
   store float %fma, float addrspace(1)* %out, align 4
   ret void
 }
 
-; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_imm_a:
-; SI: s_load_dword [[SGPR:s[0-9]+]]
-; SI: v_fma_f32 [[RESULT:v[0-9]+]], 2.0, [[SGPR]], [[SGPR]]
-; SI: buffer_store_dword [[RESULT]]
+; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_imm_a:
+; GCN: s_load_dword [[SGPR:s[0-9]+]]
+; GCN: v_fma_f32 [[RESULT:v[0-9]+]], 2.0, [[SGPR]], [[SGPR]]
+; GCN: buffer_store_dword [[RESULT]]
 define void @test_sgpr_use_twice_ternary_op_a_imm_a(float addrspace(1)* %out, float %a) #0 {
   %fma = call float @llvm.fma.f32(float %a, float 2.0, float %a) #1
   store float %fma, float addrspace(1)* %out, align 4
@@ -82,10 +89,10 @@ define void @test_sgpr_use_twice_ternary_op_a_imm_a(float addrspace(1)* %out, fl
 }
 
 ; Don't use fma since fma c, x, y is canonicalized to fma x, c, y
-; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_imm_a_a:
-; SI: s_load_dword [[SGPR:s[0-9]+]]
-; SI: v_mad_i32_i24 [[RESULT:v[0-9]+]], 2, [[SGPR]], [[SGPR]]
-; SI: buffer_store_dword [[RESULT]]
+; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_imm_a_a:
+; GCN: s_load_dword [[SGPR:s[0-9]+]]
+; GCN: v_mad_i32_i24 [[RESULT:v[0-9]+]], 2, [[SGPR]], [[SGPR]]
+; GCN: buffer_store_dword [[RESULT]]
 define void @test_sgpr_use_twice_ternary_op_imm_a_a(i32 addrspace(1)* %out, i32 %a) #0 {
   %fma = call i32 @llvm.AMDGPU.imad24(i32 2, i32 %a, i32 %a) #1
   store i32 %fma, i32 addrspace(1)* %out, align 4
diff --git a/test/CodeGen/R600/usubo.ll b/test/CodeGen/R600/usubo.ll
index be1e66673bc9..3c9b1622a076 100644
--- a/test/CodeGen/R600/usubo.ll
+++ b/test/CodeGen/R600/usubo.ll
@@ -1,11 +1,14 @@
 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs< %s
+; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs< %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 
 declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
 declare { i64, i1 } @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
 
 ; FUNC-LABEL: {{^}}usubo_i64_zext:
+
+; EG: SUBB_UINT
+; EG: ADDC_UINT
 define void @usubo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
   %usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) nounwind
   %val = extractvalue { i64, i1 } %usub, 0
@@ -18,6 +21,9 @@ define void @usubo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
 
 ; FUNC-LABEL: {{^}}s_usubo_i32:
 ; SI: s_sub_i32
+
+; EG-DAG: SUBB_UINT
+; EG-DAG: SUB_INT
 define void @s_usubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) nounwind {
   %usub = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b) nounwind
   %val = extractvalue { i32, i1 } %usub, 0
@@ -29,9 +35,12 @@ define void @s_usubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32
 
 ; FUNC-LABEL: {{^}}v_usubo_i32:
 ; SI: v_subrev_i32_e32
+
+; EG-DAG: SUBB_UINT
+; EG-DAG: SUB_INT
 define void @v_usubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
-  %a = load i32 addrspace(1)* %aptr, align 4
-  %b = load i32 addrspace(1)* %bptr, align 4
+  %a = load i32, i32 addrspace(1)* %aptr, align 4
+  %b = load i32, i32 addrspace(1)* %bptr, align 4
   %usub = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b) nounwind
   %val = extractvalue { i32, i1 } %usub, 0
   %carry = extractvalue { i32, i1 } %usub, 1
@@ -43,6 +52,11 @@ define void @v_usubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32
 ; FUNC-LABEL: {{^}}s_usubo_i64:
 ; SI: s_sub_u32
 ; SI: s_subb_u32
+
+; EG-DAG: SUBB_UINT
+; EG-DAG: SUB_INT
+; EG-DAG: SUB_INT
+; EG: SUB_INT
 define void @s_usubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a, i64 %b) nounwind {
   %usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) nounwind
   %val = extractvalue { i64, i1 } %usub, 0
@@ -55,9 +69,14 @@ define void @s_usubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64
 ; FUNC-LABEL: {{^}}v_usubo_i64:
 ; SI: v_sub_i32
 ; SI: v_subb_u32
+
+; EG-DAG: SUBB_UINT
+; EG-DAG: SUB_INT
+; EG-DAG: SUB_INT
+; EG: SUB_INT
 define void @v_usubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
-  %a = load i64 addrspace(1)* %aptr, align 4
-  %b = load i64 addrspace(1)* %bptr, align 4
+  %a = load i64, i64 addrspace(1)* %aptr, align 4
+  %b = load i64, i64 addrspace(1)* %bptr, align 4
   %usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) nounwind
   %val = extractvalue { i64, i1 } %usub, 0
   %carry = extractvalue { i64, i1 } %usub, 1
diff --git a/test/CodeGen/R600/v_cndmask.ll b/test/CodeGen/R600/v_cndmask.ll
index 85936ecda774..c368c5aaf7dc 100644
--- a/test/CodeGen/R600/v_cndmask.ll
+++ b/test/CodeGen/R600/v_cndmask.ll
@@ -10,8 +10,8 @@ declare i32 @llvm.r600.read.tidig.x() #1
 ; SI: s_endpgm
 define void @v_cnd_nan_nosgpr(float addrspace(1)* %out, i32 %c, float addrspace(1)* %fptr) #0 {
   %idx = call i32 @llvm.r600.read.tidig.x() #1
-  %f.gep = getelementptr float addrspace(1)* %fptr, i32 %idx
-  %f = load float addrspace(1)* %fptr
+  %f.gep = getelementptr float, float addrspace(1)* %fptr, i32 %idx
+  %f = load float, float addrspace(1)* %fptr
   %setcc = icmp ne i32 %c, 0
   %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f
   store float %select, float addrspace(1)* %out
diff --git a/test/CodeGen/R600/valu-i1.ll b/test/CodeGen/R600/valu-i1.ll
index a4027178431b..7d0ebd139f51 100644
--- a/test/CodeGen/R600/valu-i1.ll
+++ b/test/CodeGen/R600/valu-i1.ll
@@ -15,18 +15,18 @@ entry:
   ]
 
 case0:
-  %arrayidx1 = getelementptr i32 addrspace(1)* %dst, i32 %b
+  %arrayidx1 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b
   store i32 0, i32 addrspace(1)* %arrayidx1, align 4
   br label %end
 
 case1:
-  %arrayidx5 = getelementptr i32 addrspace(1)* %dst, i32 %b
+  %arrayidx5 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b
   store i32 1, i32 addrspace(1)* %arrayidx5, align 4
   br label %end
 
 default:
   %cmp8 = icmp eq i32 %a, 2
-  %arrayidx10 = getelementptr i32 addrspace(1)* %dst, i32 %b
+  %arrayidx10 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b
   br i1 %cmp8, label %if, label %else
 
 if:
@@ -42,8 +42,8 @@ end:
 }
 
 ; SI-LABEL: @simple_test_v_if
-; SI: v_cmp_ne_i32_e64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0
-; SI: s_and_saveexec_b64 [[BR_SREG]], [[BR_SREG]]
+; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
+; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
 ; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
 
 ; SI: ; BB#1
@@ -59,7 +59,7 @@ define void @simple_test_v_if(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1
   br i1 %is.0, label %store, label %exit
 
 store:
-  %gep = getelementptr i32 addrspace(1)* %dst, i32 %tid
+  %gep = getelementptr i32, i32 addrspace(1)* %dst, i32 %tid
   store i32 999, i32 addrspace(1)* %gep
   ret void
 
@@ -68,8 +68,8 @@ exit:
 }
 
 ; SI-LABEL: @simple_test_v_loop
-; SI: v_cmp_ne_i32_e64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0
-; SI: s_and_saveexec_b64 [[BR_SREG]], [[BR_SREG]]
+; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
+; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
 ; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
 ; SI: s_cbranch_execz BB2_2
 
@@ -81,7 +81,6 @@ exit:
 ; SI: buffer_store_dword
 ; SI: v_cmp_eq_i32_e32 vcc,
 ; SI: s_or_b64 [[OR_SREG:s\[[0-9]+:[0-9]+\]]]
-; SI: v_add_i32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}}
 ; SI: s_andn2_b64 exec, exec, [[OR_SREG]]
 ; SI: s_cbranch_execnz BB2_3
 
@@ -94,9 +93,9 @@ entry:
 
 loop:
   %i = phi i32 [%tid, %entry], [%i.inc, %loop]
-  %gep.src = getelementptr i32 addrspace(1)* %src, i32 %i
-  %gep.dst = getelementptr i32 addrspace(1)* %dst, i32 %i
-  %load = load i32 addrspace(1)* %src
+  %gep.src = getelementptr i32, i32 addrspace(1)* %src, i32 %i
+  %gep.dst = getelementptr i32, i32 addrspace(1)* %dst, i32 %i
+  %load = load i32, i32 addrspace(1)* %src
   store i32 %load, i32 addrspace(1)* %gep.dst
   %i.inc = add nsw i32 %i, 1
   %cmp = icmp eq i32 %limit, %i.inc
@@ -112,8 +111,8 @@ exit:
 ; Branch to exit if uniformly not taken
 ; SI: ; BB#0:
 ; SI: buffer_load_dword [[VBOUND:v[0-9]+]]
-; SI: v_cmp_gt_i32_e64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]]
-; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG]], [[OUTER_CMP_SREG]]
+; SI: v_cmp_lt_i32_e32 vcc
+; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]], vcc
 ; SI: s_xor_b64 [[OUTER_CMP_SREG]], exec, [[OUTER_CMP_SREG]]
 ; SI: s_cbranch_execz BB3_2
 
@@ -124,10 +123,10 @@ exit:
 
 ; Clear exec bits for workitems that load -1s
 ; SI: BB3_3:
-; SI: buffer_load_dword [[A:v[0-9]+]]
 ; SI: buffer_load_dword [[B:v[0-9]+]]
-; SI-DAG: v_cmp_ne_i32_e64 [[NEG1_CHECK_0:s\[[0-9]+:[0-9]+\]]], [[A]], -1
-; SI-DAG: v_cmp_ne_i32_e64 [[NEG1_CHECK_1:s\[[0-9]+:[0-9]+\]]], [[B]], -1
+; SI: buffer_load_dword [[A:v[0-9]+]]
+; SI-DAG: v_cmp_ne_i32_e64 [[NEG1_CHECK_0:s\[[0-9]+:[0-9]+\]]], -1, [[A]]
+; SI-DAG: v_cmp_ne_i32_e32 [[NEG1_CHECK_1:vcc]], -1, [[B]]
 ; SI: s_and_b64 [[ORNEG1:s\[[0-9]+:[0-9]+\]]], [[NEG1_CHECK_1]], [[NEG1_CHECK_0]]
 ; SI: s_and_saveexec_b64 [[ORNEG1]], [[ORNEG1]]
 ; SI: s_xor_b64 [[ORNEG1]], exec, [[ORNEG1]]
@@ -155,8 +154,8 @@ define void @multi_vcond_loop(i32 addrspace(1)* noalias nocapture %arg, i32 addr
 bb:
   %tmp = tail call i32 @llvm.r600.read.tidig.x() #0
   %tmp4 = sext i32 %tmp to i64
-  %tmp5 = getelementptr inbounds i32 addrspace(1)* %arg3, i64 %tmp4
-  %tmp6 = load i32 addrspace(1)* %tmp5, align 4
+  %tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg3, i64 %tmp4
+  %tmp6 = load i32, i32 addrspace(1)* %tmp5, align 4
   %tmp7 = icmp sgt i32 %tmp6, 0
   %tmp8 = sext i32 %tmp6 to i64
   br i1 %tmp7, label %bb10, label %bb26
@@ -164,10 +163,10 @@ bb:
 bb10:                                             ; preds = %bb, %bb20
   %tmp11 = phi i64 [ %tmp23, %bb20 ], [ 0, %bb ]
   %tmp12 = add nsw i64 %tmp11, %tmp4
-  %tmp13 = getelementptr inbounds i32 addrspace(1)* %arg1, i64 %tmp12
-  %tmp14 = load i32 addrspace(1)* %tmp13, align 4
-  %tmp15 = getelementptr inbounds i32 addrspace(1)* %arg2, i64 %tmp12
-  %tmp16 = load i32 addrspace(1)* %tmp15, align 4
+  %tmp13 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 %tmp12
+  %tmp14 = load i32, i32 addrspace(1)* %tmp13, align 4
+  %tmp15 = getelementptr inbounds i32, i32 addrspace(1)* %arg2, i64 %tmp12
+  %tmp16 = load i32, i32 addrspace(1)* %tmp15, align 4
   %tmp17 = icmp ne i32 %tmp14, -1
   %tmp18 = icmp ne i32 %tmp16, -1
   %tmp19 = and i1 %tmp17, %tmp18
@@ -175,7 +174,7 @@ bb10:                                             ; preds = %bb, %bb20
 
 bb20:                                             ; preds = %bb10
   %tmp21 = add nsw i32 %tmp16, %tmp14
-  %tmp22 = getelementptr inbounds i32 addrspace(1)* %arg, i64 %tmp12
+  %tmp22 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp12
   store i32 %tmp21, i32 addrspace(1)* %tmp22, align 4
   %tmp23 = add nuw nsw i64 %tmp11, 1
   %tmp24 = icmp slt i64 %tmp23, %tmp8
diff --git a/test/CodeGen/R600/vector-alloca.ll b/test/CodeGen/R600/vector-alloca.ll
index 228868aa7feb..6f3b4847fbdf 100644
--- a/test/CodeGen/R600/vector-alloca.ll
+++ b/test/CodeGen/R600/vector-alloca.ll
@@ -13,16 +13,16 @@
 define void @vector_read(i32 addrspace(1)* %out, i32 %index) {
 entry:
   %0 = alloca [4 x i32]
-  %x = getelementptr [4 x i32]* %0, i32 0, i32 0
-  %y = getelementptr [4 x i32]* %0, i32 0, i32 1
-  %z = getelementptr [4 x i32]* %0, i32 0, i32 2
-  %w = getelementptr [4 x i32]* %0, i32 0, i32 3
+  %x = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 0
+  %y = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 1
+  %z = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 2
+  %w = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 3
   store i32 0, i32* %x
   store i32 1, i32* %y
   store i32 2, i32* %z
   store i32 3, i32* %w
-  %1 = getelementptr [4 x i32]* %0, i32 0, i32 %index
-  %2 = load i32* %1
+  %1 = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 %index
+  %2 = load i32, i32* %1
   store i32 %2, i32 addrspace(1)* %out
   ret void
 }
@@ -37,18 +37,18 @@ entry:
 define void @vector_write(i32 addrspace(1)* %out, i32 %w_index, i32 %r_index) {
 entry:
   %0 = alloca [4 x i32]
-  %x = getelementptr [4 x i32]* %0, i32 0, i32 0
-  %y = getelementptr [4 x i32]* %0, i32 0, i32 1
-  %z = getelementptr [4 x i32]* %0, i32 0, i32 2
-  %w = getelementptr [4 x i32]* %0, i32 0, i32 3
+  %x = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 0
+  %y = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 1
+  %z = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 2
+  %w = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 3
   store i32 0, i32* %x
   store i32 0, i32* %y
   store i32 0, i32* %z
   store i32 0, i32* %w
-  %1 = getelementptr [4 x i32]* %0, i32 0, i32 %w_index
+  %1 = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 %w_index
   store i32 1, i32* %1
-  %2 = getelementptr [4 x i32]* %0, i32 0, i32 %r_index
-  %3 = load i32* %2
+  %2 = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 %r_index
+  %3 = load i32, i32* %2
   store i32 %3, i32 addrspace(1)* %out
   ret void
 }
@@ -60,18 +60,18 @@ entry:
 define void @bitcast_gep(i32 addrspace(1)* %out, i32 %w_index, i32 %r_index) {
 entry:
   %0 = alloca [4 x i32]
-  %x = getelementptr [4 x i32]* %0, i32 0, i32 0
-  %y = getelementptr [4 x i32]* %0, i32 0, i32 1
-  %z = getelementptr [4 x i32]* %0, i32 0, i32 2
-  %w = getelementptr [4 x i32]* %0, i32 0, i32 3
+  %x = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 0
+  %y = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 1
+  %z = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 2
+  %w = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 3
   store i32 0, i32* %x
   store i32 0, i32* %y
   store i32 0, i32* %z
   store i32 0, i32* %w
-  %1 = getelementptr [4 x i32]* %0, i32 0, i32 1
+  %1 = getelementptr [4 x i32], [4 x i32]* %0, i32 0, i32 1
   %2 = bitcast i32* %1 to [4 x i32]*
-  %3 = getelementptr [4 x i32]* %2, i32 0, i32 0
-  %4 = load i32* %3
+  %3 = getelementptr [4 x i32], [4 x i32]* %2, i32 0, i32 0
+  %4 = load i32, i32* %3
   store i32 %4, i32 addrspace(1)* %out
   ret void
 }
diff --git a/test/CodeGen/R600/vertex-fetch-encoding.ll b/test/CodeGen/R600/vertex-fetch-encoding.ll
index e4d117f6310b..fb6a17e67146 100644
--- a/test/CodeGen/R600/vertex-fetch-encoding.ll
+++ b/test/CodeGen/R600/vertex-fetch-encoding.ll
@@ -8,7 +8,7 @@
 
 define void @vtx_fetch32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 entry:
-  %0 = load i32 addrspace(1)* %in
+  %0 = load i32, i32 addrspace(1)* %in
   store i32 %0, i32 addrspace(1)* %out
   ret void
 }
@@ -19,7 +19,7 @@ entry:
 
 define void @vtx_fetch128(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
 entry:
-  %0 = load <4 x i32> addrspace(1)* %in
+  %0 = load <4 x i32>, <4 x i32> addrspace(1)* %in
   store <4 x i32> %0, <4 x i32> addrspace(1)* %out
   ret void
 }
diff --git a/test/CodeGen/R600/vop-shrink.ll b/test/CodeGen/R600/vop-shrink.ll
index d5a46e38ce26..9b2f229c05af 100644
--- a/test/CodeGen/R600/vop-shrink.ll
+++ b/test/CodeGen/R600/vop-shrink.ll
@@ -15,7 +15,7 @@ entry:
   br i1 %tmp, label %if, label %else
 
 if:                                               ; preds = %entry
-  %tmp1 = getelementptr i32 addrspace(1)* %out, i32 1
+  %tmp1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
   %tmp2 = extractelement <4 x i32> %sgpr, i32 1
   store i32 %tmp2, i32 addrspace(1)* %out
   br label %endif
diff --git a/test/CodeGen/R600/vselect.ll b/test/CodeGen/R600/vselect.ll
index a6152f7881ef..a3014b03d2b3 100644
--- a/test/CodeGen/R600/vselect.ll
+++ b/test/CodeGen/R600/vselect.ll
@@ -12,8 +12,8 @@
 
 define void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) {
 entry:
-  %0 = load <2 x i32> addrspace(1)* %in0
-  %1 = load <2 x i32> addrspace(1)* %in1
+  %0 = load <2 x i32>, <2 x i32> addrspace(1)* %in0
+  %1 = load <2 x i32>, <2 x i32> addrspace(1)* %in1
   %cmp = icmp ne <2 x i32> %0, %1
   %result = select <2 x i1> %cmp, <2 x i32> %0, <2 x i32> %1
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
@@ -30,8 +30,8 @@ entry:
 
 define void @test_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in0, <2 x float> addrspace(1)* %in1) {
 entry:
-  %0 = load <2 x float> addrspace(1)* %in0
-  %1 = load <2 x float> addrspace(1)* %in1
+  %0 = load <2 x float>, <2 x float> addrspace(1)* %in0
+  %1 = load <2 x float>, <2 x float> addrspace(1)* %in1
   %cmp = fcmp une <2 x float> %0, %1
   %result = select <2 x i1> %cmp, <2 x float> %0, <2 x float> %1
   store <2 x float> %result, <2 x float> addrspace(1)* %out
@@ -52,8 +52,8 @@ entry:
 
 define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) {
 entry:
-  %0 = load <4 x i32> addrspace(1)* %in0
-  %1 = load <4 x i32> addrspace(1)* %in1
+  %0 = load <4 x i32>, <4 x i32> addrspace(1)* %in0
+  %1 = load <4 x i32>, <4 x i32> addrspace(1)* %in1
   %cmp = icmp ne <4 x i32> %0, %1
   %result = select <4 x i1> %cmp, <4 x i32> %0, <4 x i32> %1
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
@@ -68,8 +68,8 @@ entry:
 
 define void @test_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in0, <4 x float> addrspace(1)* %in1) {
 entry:
-  %0 = load <4 x float> addrspace(1)* %in0
-  %1 = load <4 x float> addrspace(1)* %in1
+  %0 = load <4 x float>, <4 x float> addrspace(1)* %in0
+  %1 = load <4 x float>, <4 x float> addrspace(1)* %in1
   %cmp = fcmp une <4 x float> %0, %1
   %result = select <4 x i1> %cmp, <4 x float> %0, <4 x float> %1
   store <4 x float> %result, <4 x float> addrspace(1)* %out
diff --git a/test/CodeGen/R600/vtx-fetch-branch.ll b/test/CodeGen/R600/vtx-fetch-branch.ll
index bcbe34ea543b..4584d6e25254 100644
--- a/test/CodeGen/R600/vtx-fetch-branch.ll
+++ b/test/CodeGen/R600/vtx-fetch-branch.ll
@@ -16,7 +16,7 @@ entry:
   br i1 %0, label %endif, label %if
 
 if:
-  %1 = load i32 addrspace(1)* %in
+  %1 = load i32, i32 addrspace(1)* %in
   br label %endif
 
 endif:
diff --git a/test/CodeGen/R600/vtx-schedule.ll b/test/CodeGen/R600/vtx-schedule.ll
index 8254c9923477..912e258ebb83 100644
--- a/test/CodeGen/R600/vtx-schedule.ll
+++ b/test/CodeGen/R600/vtx-schedule.ll
@@ -11,8 +11,8 @@
 ; CHECK: VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0
 define void @test(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* addrspace(1)* nocapture %in0) {
 entry:
-  %0 = load i32 addrspace(1)* addrspace(1)* %in0
-  %1 = load i32 addrspace(1)* %0
+  %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* %in0
+  %1 = load i32, i32 addrspace(1)* %0
   store i32 %1, i32 addrspace(1)* %out
   ret void
 }
diff --git a/test/CodeGen/R600/wait.ll b/test/CodeGen/R600/wait.ll
index 93cfdd46093e..5cc7577cad33 100644
--- a/test/CodeGen/R600/wait.ll
+++ b/test/CodeGen/R600/wait.ll
@@ -4,22 +4,21 @@
 ; CHECK-LABEL: {{^}}main:
 ; CHECK: s_load_dwordx4
 ; CHECK: s_load_dwordx4
-; CHECK: s_waitcnt lgkmcnt(0){{$}}
-; CHECK: s_waitcnt vmcnt(0){{$}}
-; CHECK: s_waitcnt expcnt(0) lgkmcnt(0){{$}}
+; CHECK: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
+; CHECK: s_endpgm
 define void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, <16 x i8> addrspace(2)* inreg %arg3, <16 x i8> addrspace(2)* inreg %arg4, i32 inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(2)* inreg %constptr) #0 {
 main_body:
-  %tmp = getelementptr <16 x i8> addrspace(2)* %arg3, i32 0
-  %tmp10 = load <16 x i8> addrspace(2)* %tmp, !tbaa !0
+  %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg3, i32 0
+  %tmp10 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
   %tmp11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %tmp10, i32 0, i32 %arg6)
   %tmp12 = extractelement <4 x float> %tmp11, i32 0
   %tmp13 = extractelement <4 x float> %tmp11, i32 1
   call void @llvm.AMDGPU.barrier.global() #1
   %tmp14 = extractelement <4 x float> %tmp11, i32 2
 ;  %tmp15 = extractelement <4 x float> %tmp11, i32 3
-  %tmp15 = load float addrspace(2)* %constptr, align 4 ; Force waiting for expcnt and lgkmcnt
-  %tmp16 = getelementptr <16 x i8> addrspace(2)* %arg3, i32 1
-  %tmp17 = load <16 x i8> addrspace(2)* %tmp16, !tbaa !0
+  %tmp15 = load float, float addrspace(2)* %constptr, align 4 ; Force waiting for expcnt and lgkmcnt
+  %tmp16 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg3, i32 1
+  %tmp17 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp16, !tbaa !0
   %tmp18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %tmp17, i32 0, i32 %arg6)
   %tmp19 = extractelement <4 x float> %tmp18, i32 0
   %tmp20 = extractelement <4 x float> %tmp18, i32 1
diff --git a/test/CodeGen/R600/work-item-intrinsics.ll b/test/CodeGen/R600/work-item-intrinsics.ll
index 37c0e0f304ce..4328e964c1bf 100644
--- a/test/CodeGen/R600/work-item-intrinsics.ll
+++ b/test/CodeGen/R600/work-item-intrinsics.ll
@@ -1,14 +1,15 @@
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
 
 ; FUNC-LABEL: {{^}}ngroups_x:
 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
 ; EG: MOV [[VAL]], KC0[0].X
 
-; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0
-; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[VVAL]]
+; GCN: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0
+; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
+; GCN: buffer_store_dword [[VVAL]]
 define void @ngroups_x (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.ngroups.x() #0
@@ -21,8 +22,9 @@ entry:
 ; EG: MOV [[VAL]], KC0[0].Y
 
 ; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1
-; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[VVAL]]
+; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
+; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
+; GCN: buffer_store_dword [[VVAL]]
 define void @ngroups_y (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.ngroups.y() #0
@@ -35,8 +37,9 @@ entry:
 ; EG: MOV [[VAL]], KC0[0].Z
 
 ; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2
-; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[VVAL]]
+; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
+; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
+; GCN: buffer_store_dword [[VVAL]]
 define void @ngroups_z (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.ngroups.z() #0
@@ -49,8 +52,9 @@ entry:
 ; EG: MOV [[VAL]], KC0[0].W
 
 ; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x3
-; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[VVAL]]
+; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xc
+; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
+; GCN: buffer_store_dword [[VVAL]]
 define void @global_size_x (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.global.size.x() #0
@@ -63,8 +67,9 @@ entry:
 ; EG: MOV [[VAL]], KC0[1].X
 
 ; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
-; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[VVAL]]
+; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x10
+; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
+; GCN: buffer_store_dword [[VVAL]]
 define void @global_size_y (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.global.size.y() #0
@@ -77,8 +82,9 @@ entry:
 ; EG: MOV [[VAL]], KC0[1].Y
 
 ; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x5
-; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[VVAL]]
+; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x14
+; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
+; GCN: buffer_store_dword [[VVAL]]
 define void @global_size_z (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.global.size.z() #0
@@ -91,8 +97,9 @@ entry:
 ; EG: MOV [[VAL]], KC0[1].Z
 
 ; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x6
-; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[VVAL]]
+; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x18
+; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
+; GCN: buffer_store_dword [[VVAL]]
 define void @local_size_x (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.local.size.x() #0
@@ -105,8 +112,9 @@ entry:
 ; EG: MOV [[VAL]], KC0[1].W
 
 ; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x7
-; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[VVAL]]
+; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1c
+; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
+; GCN: buffer_store_dword [[VVAL]]
 define void @local_size_y (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.local.size.y() #0
@@ -119,8 +127,9 @@ entry:
 ; EG: MOV [[VAL]], KC0[2].X
 
 ; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
-; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[VVAL]]
+; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x20
+; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
+; GCN: buffer_store_dword [[VVAL]]
 define void @local_size_z (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.local.size.z() #0
@@ -133,8 +142,9 @@ entry:
 ; EG: MOV [[VAL]], KC0[2].Z
 
 ; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
-; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[VVAL]]
+; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
+; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
+; GCN: buffer_store_dword [[VVAL]]
 define void @get_work_dim (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.AMDGPU.read.workdim() #0
@@ -147,8 +157,8 @@ entry:
 ; kernel arguments, but this may change in the future.
 
 ; FUNC-LABEL: {{^}}tgid_x:
-; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], s4
-; SI: buffer_store_dword [[VVAL]]
+; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], s4
+; GCN: buffer_store_dword [[VVAL]]
 define void @tgid_x (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.tgid.x() #0
@@ -157,8 +167,8 @@ entry:
 }
 
 ; FUNC-LABEL: {{^}}tgid_y:
-; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], s5
-; SI: buffer_store_dword [[VVAL]]
+; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], s5
+; GCN: buffer_store_dword [[VVAL]]
 define void @tgid_y (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.tgid.y() #0
@@ -167,8 +177,8 @@ entry:
 }
 
 ; FUNC-LABEL: {{^}}tgid_z:
-; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], s6
-; SI: buffer_store_dword [[VVAL]]
+; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], s6
+; GCN: buffer_store_dword [[VVAL]]
 define void @tgid_z (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.tgid.z() #0
@@ -177,7 +187,7 @@ entry:
 }
 
 ; FUNC-LABEL: {{^}}tidig_x:
-; SI: buffer_store_dword v0
+; GCN: buffer_store_dword v0
 define void @tidig_x (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.tidig.x() #0
@@ -186,7 +196,7 @@ entry:
 }
 
 ; FUNC-LABEL: {{^}}tidig_y:
-; SI: buffer_store_dword v1
+; GCN: buffer_store_dword v1
 define void @tidig_y (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.tidig.y() #0
@@ -195,7 +205,7 @@ entry:
 }
 
 ; FUNC-LABEL: {{^}}tidig_z:
-; SI: buffer_store_dword v2
+; GCN: buffer_store_dword v2
 define void @tidig_z (i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.tidig.z() #0
diff --git a/test/CodeGen/R600/wrong-transalu-pos-fix.ll b/test/CodeGen/R600/wrong-transalu-pos-fix.ll
index 4e77c07c0ea1..5ab465338e15 100644
--- a/test/CodeGen/R600/wrong-transalu-pos-fix.ll
+++ b/test/CodeGen/R600/wrong-transalu-pos-fix.ll
@@ -35,7 +35,7 @@ entry:
   %z.i8.i = tail call i32 @llvm.r600.read.tidig.z() #1
   %add.i = add i32 %z.i8.i, %mul33.i
   %add13 = add i32 %add.i, %add
-  %arrayidx = getelementptr inbounds i32 addrspace(1)* %out, i32 %add13
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %add13
   store i32 %mul3, i32 addrspace(1)* %arrayidx, align 4
   ret void
 }
diff --git a/test/CodeGen/R600/xor.ll b/test/CodeGen/R600/xor.ll
index b43ff4006473..089db59eabc7 100644
--- a/test/CodeGen/R600/xor.ll
+++ b/test/CodeGen/R600/xor.ll
@@ -11,8 +11,8 @@
 ; SI: v_xor_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
 
 define void @xor_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) {
-  %a = load <2 x i32> addrspace(1) * %in0
-  %b = load <2 x i32> addrspace(1) * %in1
+  %a = load <2 x i32>, <2 x i32> addrspace(1) * %in0
+  %b = load <2 x i32>, <2 x i32> addrspace(1) * %in1
   %result = xor <2 x i32> %a, %b
   store <2 x i32> %result, <2 x i32> addrspace(1)* %out
   ret void
@@ -30,8 +30,8 @@ define void @xor_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in
 ; SI: v_xor_b32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
 
 define void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) {
-  %a = load <4 x i32> addrspace(1) * %in0
-  %b = load <4 x i32> addrspace(1) * %in1
+  %a = load <4 x i32>, <4 x i32> addrspace(1) * %in0
+  %b = load <4 x i32>, <4 x i32> addrspace(1) * %in1
   %result = xor <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
@@ -40,15 +40,15 @@ define void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in
 ; FUNC-LABEL: {{^}}xor_i1:
 ; EG: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}}
 
-; SI-DAG: v_cmp_ge_f32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, 0
-; SI-DAG: v_cmp_ge_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, 1.0
+; SI-DAG: v_cmp_le_f32_e32 [[CMP0:vcc]], 0, {{v[0-9]+}}
+; SI-DAG: v_cmp_le_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 1.0, {{v[0-9]+}}
 ; SI: s_xor_b64 [[XOR:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, [[XOR]]
 ; SI: buffer_store_dword [[RESULT]]
 ; SI: s_endpgm
 define void @xor_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
-  %a = load float addrspace(1) * %in0
-  %b = load float addrspace(1) * %in1
+  %a = load float, float addrspace(1) * %in0
+  %b = load float, float addrspace(1) * %in1
   %acmp = fcmp oge float %a, 0.000000e+00
   %bcmp = fcmp oge float %b, 1.000000e+00
   %xor = xor i1 %acmp, %bcmp
@@ -58,14 +58,14 @@ define void @xor_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float ad
 }
 
 ; FUNC-LABEL: {{^}}v_xor_i1:
-; SI: buffer_load_ubyte [[A:v[0-9]+]]
 ; SI: buffer_load_ubyte [[B:v[0-9]+]]
+; SI: buffer_load_ubyte [[A:v[0-9]+]]
 ; SI: v_xor_b32_e32 [[XOR:v[0-9]+]], [[A]], [[B]]
 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[XOR]]
 ; SI: buffer_store_byte [[RESULT]]
 define void @v_xor_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in0, i1 addrspace(1)* %in1) {
-  %a = load i1 addrspace(1)* %in0
-  %b = load i1 addrspace(1)* %in1
+  %a = load i1, i1 addrspace(1)* %in0
+  %b = load i1, i1 addrspace(1)* %in1
   %xor = xor i1 %a, %b
   store i1 %xor, i1 addrspace(1)* %out
   ret void
@@ -74,8 +74,8 @@ define void @v_xor_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in0, i1 addrspace
 ; FUNC-LABEL: {{^}}vector_xor_i32:
 ; SI: v_xor_b32_e32
 define void @vector_xor_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) {
-  %a = load i32 addrspace(1)* %in0
-  %b = load i32 addrspace(1)* %in1
+  %a = load i32, i32 addrspace(1)* %in0
+  %b = load i32, i32 addrspace(1)* %in1
   %result = xor i32 %a, %b
   store i32 %result, i32 addrspace(1)* %out
   ret void
@@ -100,8 +100,8 @@ define void @scalar_not_i32(i32 addrspace(1)* %out, i32 %a) {
 ; FUNC-LABEL: {{^}}vector_not_i32:
 ; SI: v_not_b32
 define void @vector_not_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) {
-  %a = load i32 addrspace(1)* %in0
-  %b = load i32 addrspace(1)* %in1
+  %a = load i32, i32 addrspace(1)* %in0
+  %b = load i32, i32 addrspace(1)* %in1
   %result = xor i32 %a, -1
   store i32 %result, i32 addrspace(1)* %out
   ret void
@@ -112,8 +112,8 @@ define void @vector_not_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32
 ; SI: v_xor_b32_e32
 ; SI: s_endpgm
 define void @vector_xor_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i64 addrspace(1)* %in1) {
-  %a = load i64 addrspace(1)* %in0
-  %b = load i64 addrspace(1)* %in1
+  %a = load i64, i64 addrspace(1)* %in0
+  %b = load i64, i64 addrspace(1)* %in1
   %result = xor i64 %a, %b
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -140,8 +140,8 @@ define void @scalar_not_i64(i64 addrspace(1)* %out, i64 %a) {
 ; SI: v_not_b32
 ; SI: v_not_b32
 define void @vector_not_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i64 addrspace(1)* %in1) {
-  %a = load i64 addrspace(1)* %in0
-  %b = load i64 addrspace(1)* %in1
+  %a = load i64, i64 addrspace(1)* %in0
+  %b = load i64, i64 addrspace(1)* %in1
   %result = xor i64 %a, -1
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -163,7 +163,7 @@ if:
   br label %endif
 
 else:
-  %2 = load i64 addrspace(1)* %in
+  %2 = load i64, i64 addrspace(1)* %in
   br label %endif
 
 endif:
diff --git a/test/CodeGen/R600/zero_extend.ll b/test/CodeGen/R600/zero_extend.ll
index d052ee64c6f1..033055db185a 100644
--- a/test/CodeGen/R600/zero_extend.ll
+++ b/test/CodeGen/R600/zero_extend.ll
@@ -30,9 +30,9 @@ entry:
 }
 
 ; SI-LABEL: {{^}}zext_i1_to_i64:
+; SI: s_mov_b32 s{{[0-9]+}}, 0
 ; SI: v_cmp_eq_i32
 ; SI: v_cndmask_b32
-; SI: s_mov_b32 s{{[0-9]+}}, 0
 define void @zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
   %cmp = icmp eq i32 %a, %b
   %ext = zext i1 %cmp to i64
diff --git a/test/CodeGen/SPARC/2008-10-10-InlineAsmMemoryOperand.ll b/test/CodeGen/SPARC/2008-10-10-InlineAsmMemoryOperand.ll
index e8315f17ebb6..07e250b3c98a 100644
--- a/test/CodeGen/SPARC/2008-10-10-InlineAsmMemoryOperand.ll
+++ b/test/CodeGen/SPARC/2008-10-10-InlineAsmMemoryOperand.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=sparc
+; RUN: llc < %s -march=sparc -no-integrated-as
 ; PR 1557
 
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f128:128:128"
@@ -8,7 +8,7 @@ define internal void @set_fast_math() nounwind {
 entry:
 	%fsr = alloca i32		; <i32*> [#uses=4]
 	call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
-	%0 = load i32* %fsr, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* %fsr, align 4		; <i32> [#uses=1]
 	%1 = or i32 %0, 4194304		; <i32> [#uses=1]
 	store i32 %1, i32* %fsr, align 4
 	call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
diff --git a/test/CodeGen/SPARC/2008-10-10-InlineAsmRegOperand.ll b/test/CodeGen/SPARC/2008-10-10-InlineAsmRegOperand.ll
index c12e9c13409b..7975ee468232 100644
--- a/test/CodeGen/SPARC/2008-10-10-InlineAsmRegOperand.ll
+++ b/test/CodeGen/SPARC/2008-10-10-InlineAsmRegOperand.ll
@@ -7,7 +7,7 @@ module asm "\09.section\09\22.dtors\22,#alloc,#write"
 
 define void @frame_dummy() nounwind {
 entry:
-	%asmtmp = tail call void (i8*)* (void (i8*)*)* asm "", "=r,0"(void (i8*)* @_Jv_RegisterClasses) nounwind		; <void (i8*)*> [#uses=0]
+	%asmtmp = tail call void (i8*)* (void (i8*)*) asm "", "=r,0"(void (i8*)* @_Jv_RegisterClasses) nounwind		; <void (i8*)*> [#uses=0]
 	unreachable
 }
 
diff --git a/test/CodeGen/SPARC/2009-08-28-PIC.ll b/test/CodeGen/SPARC/2009-08-28-PIC.ll
index b004b11b853b..baad2ae507d3 100644
--- a/test/CodeGen/SPARC/2009-08-28-PIC.ll
+++ b/test/CodeGen/SPARC/2009-08-28-PIC.ll
@@ -14,7 +14,7 @@
 
 define i32 @func(i32 %a) nounwind readonly {
 entry:
-  %0 = load i32* @foo, align 4                    ; <i32> [#uses=1]
+  %0 = load i32, i32* @foo, align 4                    ; <i32> [#uses=1]
   ret i32 %0
 }
 
@@ -36,7 +36,7 @@ entry:
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
-  %ret =  load i32* @foo, align 4
+  %ret =  load i32, i32* @foo, align 4
   ret i32 %ret
 
 if.end:
diff --git a/test/CodeGen/SPARC/2011-01-11-CC.ll b/test/CodeGen/SPARC/2011-01-11-CC.ll
index 50f3a65ff9a9..6ea78dd7e169 100755
--- a/test/CodeGen/SPARC/2011-01-11-CC.ll
+++ b/test/CodeGen/SPARC/2011-01-11-CC.ll
@@ -177,13 +177,13 @@ define void @test_adde_sube(i8* %a, i8* %b, i8* %sum, i8* %diff) {
 entry:
    %0 = bitcast i8* %a to i128*
    %1 = bitcast i8* %b to i128*
-   %2 = load i128* %0
-   %3 = load i128* %1
+   %2 = load i128, i128* %0
+   %3 = load i128, i128* %1
    %4 = add i128 %2, %3
    %5 = bitcast i8* %sum to i128*
    store i128 %4, i128* %5
    tail call void asm sideeffect "", "=*m,*m"(i128 *%0, i128* %5) nounwind
-   %6 = load i128* %0
+   %6 = load i128, i128* %0
    %7 = sub i128 %2, %6
    %8 = bitcast i8* %diff to i128*
    store i128 %7, i128* %8
diff --git a/test/CodeGen/SPARC/2011-01-11-Call.ll b/test/CodeGen/SPARC/2011-01-11-Call.ll
index 067bade16609..8097e49ad3f7 100644
--- a/test/CodeGen/SPARC/2011-01-11-Call.ll
+++ b/test/CodeGen/SPARC/2011-01-11-Call.ll
@@ -22,8 +22,8 @@
 
 define void @test() nounwind {
 entry:
- %0 = tail call i32 (...)* @foo() nounwind
- tail call void (...)* @bar() nounwind
+ %0 = tail call i32 (...) @foo() nounwind
+ tail call void (...) @bar() nounwind
  ret void
 }
 
@@ -48,6 +48,6 @@ declare void @bar(...)
 
 define i32 @test_tail_call_with_return() nounwind {
 entry:
- %0 = tail call i32 (...)* @foo() nounwind
+ %0 = tail call i32 (...) @foo() nounwind
  ret i32 %0
 }
diff --git a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
index 8a3edc64b2da..29bca67e2d24 100644
--- a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
+++ b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
@@ -66,7 +66,7 @@ entry:
   br i1 %0, label %bb, label %bb1
 
 bb:                                               ; preds = %entry
-  %1 = tail call i32 (...)* @foo(i32 %a) nounwind
+  %1 = tail call i32 (...) @foo(i32 %a) nounwind
   ret i32 %1
 
 bb1:                                              ; preds = %entry
diff --git a/test/CodeGen/SPARC/2011-01-22-SRet.ll b/test/CodeGen/SPARC/2011-01-22-SRet.ll
index fc44bc495f46..ae9764e82084 100644
--- a/test/CodeGen/SPARC/2011-01-22-SRet.ll
+++ b/test/CodeGen/SPARC/2011-01-22-SRet.ll
@@ -7,11 +7,11 @@ entry:
 ;CHECK-LABEL: make_foo:
 ;CHECK: ld [%sp+64], {{.+}}
 ;CHECK: jmp %o7+12
-  %0 = getelementptr inbounds %struct.foo_t* %agg.result, i32 0, i32 0
+  %0 = getelementptr inbounds %struct.foo_t, %struct.foo_t* %agg.result, i32 0, i32 0
   store i32 %a, i32* %0, align 4
-  %1 = getelementptr inbounds %struct.foo_t* %agg.result, i32 0, i32 1
+  %1 = getelementptr inbounds %struct.foo_t, %struct.foo_t* %agg.result, i32 0, i32 1
   store i32 %b, i32* %1, align 4
-  %2 = getelementptr inbounds %struct.foo_t* %agg.result, i32 0, i32 2
+  %2 = getelementptr inbounds %struct.foo_t, %struct.foo_t* %agg.result, i32 0, i32 2
   store i32 %c, i32* %2, align 4
   ret void
 }
@@ -24,12 +24,12 @@ entry:
 ;CHECK: unimp 12
   %f = alloca %struct.foo_t, align 8
   call void @make_foo(%struct.foo_t* noalias sret %f, i32 10, i32 20, i32 30) nounwind
-  %0 = getelementptr inbounds %struct.foo_t* %f, i32 0, i32 0
-  %1 = load i32* %0, align 8
-  %2 = getelementptr inbounds %struct.foo_t* %f, i32 0, i32 1
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds %struct.foo_t* %f, i32 0, i32 2
-  %5 = load i32* %4, align 8
+  %0 = getelementptr inbounds %struct.foo_t, %struct.foo_t* %f, i32 0, i32 0
+  %1 = load i32, i32* %0, align 8
+  %2 = getelementptr inbounds %struct.foo_t, %struct.foo_t* %f, i32 0, i32 1
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds %struct.foo_t, %struct.foo_t* %f, i32 0, i32 2
+  %5 = load i32, i32* %4, align 8
   %6 = add nsw i32 %3, %1
   %7 = add nsw i32 %6, %5
   ret i32 %7
diff --git a/test/CodeGen/SPARC/64abi.ll b/test/CodeGen/SPARC/64abi.ll
index a88e19a5e2d4..7c08998a1427 100644
--- a/test/CodeGen/SPARC/64abi.ll
+++ b/test/CodeGen/SPARC/64abi.ll
@@ -240,10 +240,10 @@ define void @call_inreg_ii(i32* %p, i32 %i1, i32 %i2) {
 ; CHECK: ldx [%i2], %i0
 ; CHECK: ldx [%i3], %i1
 define { i64, i64 } @ret_i64_pair(i32 %a0, i32 %a1, i64* %p, i64* %q) {
-  %r1 = load i64* %p
+  %r1 = load i64, i64* %p
   %rv1 = insertvalue { i64, i64 } undef, i64 %r1, 0
   store i64 0, i64* %p
-  %r2 = load i64* %q
+  %r2 = load i64, i64* %q
   %rv2 = insertvalue { i64, i64 } %rv1, i64 %r2, 1
   ret { i64, i64 } %rv2
 }
@@ -268,10 +268,10 @@ define void @call_ret_i64_pair(i64* %i0) {
 ; CHECK: ld [%i3], %f2
 define { i32, float } @ret_i32_float_pair(i32 %a0, i32 %a1,
                                           i32* %p, float* %q) {
-  %r1 = load i32* %p
+  %r1 = load i32, i32* %p
   %rv1 = insertvalue { i32, float } undef, i32 %r1, 0
   store i32 0, i32* %p
-  %r2 = load float* %q
+  %r2 = load float, float* %q
   %rv2 = insertvalue { i32, float } %rv1, float %r2, 1
   ret { i32, float } %rv2
 }
@@ -297,10 +297,10 @@ define void @call_ret_i32_float_pair(i32* %i0, float* %i1) {
 ; CHECK: ld [%i3], %f1
 define inreg { i32, float } @ret_i32_float_packed(i32 %a0, i32 %a1,
                                                   i32* %p, float* %q) {
-  %r1 = load i32* %p
+  %r1 = load i32, i32* %p
   %rv1 = insertvalue { i32, float } undef, i32 %r1, 0
   store i32 0, i32* %p
-  %r2 = load float* %q
+  %r2 = load float, float* %q
   %rv2 = insertvalue { i32, float } %rv1, float %r2, 1
   ret { i32, float } %rv2
 }
@@ -329,10 +329,10 @@ define void @call_ret_i32_float_packed(i32* %i0, float* %i1) {
 ; CHECK: or [[R3]], [[R1]], %i0
 define inreg { i32, i32 } @ret_i32_packed(i32 %a0, i32 %a1,
                                           i32* %p, i32* %q) {
-  %r1 = load i32* %p
+  %r1 = load i32, i32* %p
   %rv1 = insertvalue { i32, i32 } undef, i32 %r1, 1
   store i32 0, i32* %p
-  %r2 = load i32* %q
+  %r2 = load i32, i32* %q
   %rv2 = insertvalue { i32, i32 } %rv1, i32 %r2, 0
   ret { i32, i32 } %rv2
 }
@@ -405,7 +405,7 @@ entry:
 define i32 @test_large_stack() {
 entry:
   %buffer1 = alloca [16384 x i8], align 8
-  %buffer1.sub = getelementptr inbounds [16384 x i8]* %buffer1, i32 0, i32 0
+  %buffer1.sub = getelementptr inbounds [16384 x i8], [16384 x i8]* %buffer1, i32 0, i32 0
   %0 = call i32 @use_buf(i32 16384, i8* %buffer1.sub)
   ret i32 %0
 }
@@ -436,7 +436,7 @@ declare i64 @receive_fp128(i64 %a, ...)
 ; CHECK:       call receive_fp128
 define i64 @test_fp128_variable_args(i64 %a, fp128 %b) {
 entry:
-  %0 = call i64 (i64, ...)* @receive_fp128(i64 %a, fp128 %b)
+  %0 = call i64 (i64, ...) @receive_fp128(i64 %a, fp128 %b)
   ret i64 %0
 }
 
diff --git a/test/CodeGen/SPARC/64bit.ll b/test/CodeGen/SPARC/64bit.ll
index b18f1bc0e837..274fa32fad35 100644
--- a/test/CodeGen/SPARC/64bit.ll
+++ b/test/CodeGen/SPARC/64bit.ll
@@ -140,17 +140,17 @@ define i64 @reg_imm_alu(i64 %x, i64 %y, i64 %z) {
 ; CHECK: ldsh [%i3]
 ; CHECK: sth %
 define i64 @loads(i64* %p, i32* %q, i32* %r, i16* %s) {
-  %a = load i64* %p
+  %a = load i64, i64* %p
   %ai = add i64 1, %a
   store i64 %ai, i64* %p
-  %b = load i32* %q
+  %b = load i32, i32* %q
   %b2 = zext i32 %b to i64
   %bi = trunc i64 %ai to i32
   store i32 %bi, i32* %q
-  %c = load i32* %r
+  %c = load i32, i32* %r
   %c2 = sext i32 %c to i64
   store i64 %ai, i64* %p
-  %d = load i16* %s
+  %d = load i16, i16* %s
   %d2 = sext i16 %d to i64
   %di = trunc i64 %ai to i16
   store i16 %di, i16* %s
@@ -164,7 +164,7 @@ define i64 @loads(i64* %p, i32* %q, i32* %r, i16* %s) {
 ; CHECK: load_bool
 ; CHECK: ldub [%i0], %i0
 define i64 @load_bool(i1* %p) {
-  %a = load i1* %p
+  %a = load i1, i1* %p
   %b = zext i1 %a to i64
   ret i64 %b
 }
@@ -176,20 +176,20 @@ define i64 @load_bool(i1* %p) {
 ; CHECK: sth [[R]], [%i2+40]
 ; CHECK: stb [[R]], [%i3+-20]
 define void @stores(i64* %p, i32* %q, i16* %r, i8* %s) {
-  %p1 = getelementptr i64* %p, i64 1
-  %p2 = getelementptr i64* %p, i64 2
-  %pv = load i64* %p1
+  %p1 = getelementptr i64, i64* %p, i64 1
+  %p2 = getelementptr i64, i64* %p, i64 2
+  %pv = load i64, i64* %p1
   store i64 %pv, i64* %p2
 
-  %q2 = getelementptr i32* %q, i32 -2
+  %q2 = getelementptr i32, i32* %q, i32 -2
   %qv = trunc i64 %pv to i32
   store i32 %qv, i32* %q2
 
-  %r2 = getelementptr i16* %r, i16 20
+  %r2 = getelementptr i16, i16* %r, i16 20
   %rv = trunc i64 %pv to i16
   store i16 %rv, i16* %r2
 
-  %s2 = getelementptr i8* %s, i8 -20
+  %s2 = getelementptr i8, i8* %s, i8 -20
   %sv = trunc i64 %pv to i8
   store i8 %sv, i8* %s2
 
@@ -200,8 +200,8 @@ define void @stores(i64* %p, i32* %q, i16* %r, i8* %s) {
 ; CHECK: ldub [%i0], [[R:%[goli][0-7]]]
 ; CHECK: sll [[R]], [[R]], %i0
 define i8 @promote_shifts(i8* %p) {
-  %L24 = load i8* %p
-  %L32 = load i8* %p
+  %L24 = load i8, i8* %p
+  %L32 = load i8, i8* %p
   %B36 = shl i8 %L24, %L32
   ret i8 %B36
 }
@@ -230,7 +230,7 @@ define i64 @unsigned_divide(i64 %a, i64 %b) {
 define void @access_fi() {
 entry:
   %b = alloca [32 x i8], align 1
-  %arraydecay = getelementptr inbounds [32 x i8]* %b, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [32 x i8], [32 x i8]* %b, i64 0, i64 0
   call void @g(i8* %arraydecay) #2
   ret void
 }
@@ -281,7 +281,7 @@ define double @bitcast_f64_i64(i64 %x) {
 define i64 @store_zero(i64* nocapture %a, i64* nocapture %b) {
 entry:
   store i64 0, i64* %a, align 8
-  %0 = getelementptr inbounds i64* %b, i32 1
+  %0 = getelementptr inbounds i64, i64* %b, i32 1
   store i64 0, i64* %0, align 8
   ret i64 0
 }
diff --git a/test/CodeGen/SPARC/atomics.ll b/test/CodeGen/SPARC/atomics.ll
index ee6c1f8999b0..bea9a3374696 100644
--- a/test/CodeGen/SPARC/atomics.ll
+++ b/test/CodeGen/SPARC/atomics.ll
@@ -9,8 +9,8 @@
 ; CHECK:       st {{.+}}, [%o2]
 define i32 @test_atomic_i32(i32* %ptr1, i32* %ptr2, i32* %ptr3) {
 entry:
-  %0 = load atomic i32* %ptr1 acquire, align 8
-  %1 = load atomic i32* %ptr2 acquire, align 8
+  %0 = load atomic i32, i32* %ptr1 acquire, align 8
+  %1 = load atomic i32, i32* %ptr2 acquire, align 8
   %2 = add i32 %0, %1
   store atomic i32 %2, i32* %ptr3 release, align 8
   ret i32 %2
@@ -25,8 +25,8 @@ entry:
 ; CHECK:       stx {{.+}}, [%o2]
 define i64 @test_atomic_i64(i64* %ptr1, i64* %ptr2, i64* %ptr3) {
 entry:
-  %0 = load atomic i64* %ptr1 acquire, align 8
-  %1 = load atomic i64* %ptr2 acquire, align 8
+  %0 = load atomic i64, i64* %ptr1 acquire, align 8
+  %1 = load atomic i64, i64* %ptr2 acquire, align 8
   %2 = add i64 %0, %1
   store atomic i64 %2, i64* %ptr3 release, align 8
   ret i64 %2
diff --git a/test/CodeGen/SPARC/basictest.ll b/test/CodeGen/SPARC/basictest.ll
index ba858253287a..7b540074a35f 100644
--- a/test/CodeGen/SPARC/basictest.ll
+++ b/test/CodeGen/SPARC/basictest.ll
@@ -31,8 +31,56 @@ define i32 @test2(i32 %X, i32 %Y) {
 define i32 @store_zero(i32* %a, i32* %b) {
 entry:
   store i32 0, i32* %a, align 4
-  %0 = getelementptr inbounds i32* %b, i32 1
+  %0 = getelementptr inbounds i32, i32* %b, i32 1
   store i32 0, i32* %0, align 4
   ret i32 0
 }
 
+; CHECK-LABEL: signed_divide:
+; CHECK: sra %o0, 31, %o2
+; CHECK: wr %o2, %g0, %y
+; CHECK: sdiv %o0, %o1, %o0
+define i32 @signed_divide(i32 %a, i32 %b) {
+  %r = sdiv i32 %a, %b
+  ret i32 %r
+}
+
+; CHECK-LABEL: unsigned_divide:
+; CHECK: wr %g0, %g0, %y
+; CHECK: udiv %o0, %o1, %o0
+define i32 @unsigned_divide(i32 %a, i32 %b) {
+  %r = udiv i32 %a, %b
+  ret i32 %r
+}
+
+; CHECK-LABEL: multiply_32x32:
+; CHECK: smul %o0, %o1, %o0
+define i32 @multiply_32x32(i32 %a, i32 %b) {
+  %r = mul i32 %a, %b
+  ret i32 %r
+}
+
+; CHECK-LABEL: signed_multiply_32x32_64:
+; CHECK: smul %o0, %o1, %o1
+; CHECK: rd %y, %o0
+define i64 @signed_multiply_32x32_64(i32 %a, i32 %b) {
+  %xa = sext i32 %a to i64
+  %xb = sext i32 %b to i64
+  %r = mul i64 %xa, %xb
+  ret i64 %r
+}
+
+; CHECK-LABEL: unsigned_multiply_32x32_64:
+; CHECK: umul %o0, %o1, %o2
+; CHECK: rd %y, %o2
+;FIXME: the smul in the output is totally redundant and should not there.
+; CHECK: smul %o0, %o1, %o1
+; CHECK: retl
+; CHECK: mov      %o2, %o0
+define i64 @unsigned_multiply_32x32_64(i32 %a, i32 %b) {
+  %xa = zext i32 %a to i64
+  %xb = zext i32 %b to i64
+  %r = mul i64 %xa, %xb
+  ret i64 %r
+}
+
diff --git a/test/CodeGen/SPARC/empty-functions.ll b/test/CodeGen/SPARC/empty-functions.ll
index 38d288903d4a..1f8c5e3a312d 100644
--- a/test/CodeGen/SPARC/empty-functions.ll
+++ b/test/CodeGen/SPARC/empty-functions.ll
@@ -28,5 +28,5 @@ entry:
 ; LINUX-FP-NEXT: {{^}}.L{{.*}}:{{$}}
 ; LINUX-FP-NEXT: .cfi_register 15, 31
 ; LINUX-FP-NEXT: {{^}}.L{{.*}}:{{$}}
-; LINUX-FP-NEXT: .size   func, .Ltmp3-func
+; LINUX-FP-NEXT: .size   func, .Lfunc_end0-func
 ; LINUX-FP-NEXT: .cfi_endproc
diff --git a/test/CodeGen/SPARC/exception.ll b/test/CodeGen/SPARC/exception.ll
index eca9c8bf739f..0af48d0b64b8 100644
--- a/test/CodeGen/SPARC/exception.ll
+++ b/test/CodeGen/SPARC/exception.ll
@@ -121,13 +121,13 @@ entry:
 
 "11":                                             ; preds = %"8"
   %10 = tail call i8* @__cxa_begin_catch(i8* %exc_ptr12) #1
-  %11 = tail call i32 @puts(i8* getelementptr inbounds ([12 x i8]* @.cst, i32 0, i32 0))
+  %11 = tail call i32 @puts(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.cst, i32 0, i32 0))
   tail call void @__cxa_end_catch() #1
   br label %"5"
 
 "13":                                             ; preds = %8
   %12 = tail call i8* @__cxa_begin_catch(i8* %exc_ptr12) #1
-  %13 = tail call i32 @puts(i8* getelementptr inbounds ([14 x i8]* @.cst1, i32 0, i32 0))
+  %13 = tail call i32 @puts(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.cst1, i32 0, i32 0))
   tail call void @__cxa_end_catch() #1
   br label %"5"
 }
diff --git a/test/CodeGen/SPARC/float.ll b/test/CodeGen/SPARC/float.ll
index 66367042cad9..d7a79cb05a82 100644
--- a/test/CodeGen/SPARC/float.ll
+++ b/test/CodeGen/SPARC/float.ll
@@ -154,11 +154,11 @@ entry:
 ; SPARC64:          fitod
 ; SPARC64:          fdtoi
 
-define void @test_itod_dtoi(i32 %a, i32* %ptr0, double* %ptr1) {
+define void @test_itod_dtoi(i32 %a, double %b, i32* %ptr0, double* %ptr1) {
 entry:
   %0 = sitofp i32 %a to double
   store double %0, double* %ptr1, align 8
-  %1 = fptosi double %0 to i32
+  %1 = fptosi double %b to i32
   store i32 %1, i32* %ptr0, align 8
   ret void
 }
diff --git a/test/CodeGen/SPARC/fp128.ll b/test/CodeGen/SPARC/fp128.ll
index abd89bf264e1..c864cb7d599b 100644
--- a/test/CodeGen/SPARC/fp128.ll
+++ b/test/CodeGen/SPARC/fp128.ll
@@ -28,10 +28,10 @@
 
 define void @f128_ops(fp128* noalias sret %scalar.result, fp128* byval %a, fp128* byval %b, fp128* byval %c, fp128* byval %d) {
 entry:
-  %0 = load fp128* %a, align 8
-  %1 = load fp128* %b, align 8
-  %2 = load fp128* %c, align 8
-  %3 = load fp128* %d, align 8
+  %0 = load fp128, fp128* %a, align 8
+  %1 = load fp128, fp128* %b, align 8
+  %2 = load fp128, fp128* %c, align 8
+  %3 = load fp128, fp128* %d, align 8
   %4 = fadd fp128 %0, %1
   %5 = fsub fp128 %4, %2
   %6 = fmul fp128 %5, %3
@@ -56,7 +56,7 @@ entry:
 
 define void @f128_spill(fp128* noalias sret %scalar.result, fp128* byval %a) {
 entry:
-  %0 = load fp128* %a, align 8
+  %0 = load fp128, fp128* %a, align 8
   call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
   store fp128 %0, fp128* %scalar.result, align 8
   ret void
@@ -71,8 +71,8 @@ entry:
 
 define i32 @f128_compare(fp128* byval %f0, fp128* byval %f1, i32 %a, i32 %b) {
 entry:
-   %0 = load fp128* %f0, align 8
-   %1 = load fp128* %f1, align 8
+   %0 = load fp128, fp128* %f0, align 8
+   %1 = load fp128, fp128* %f1, align 8
    %cond = fcmp ult fp128 %0, %1
    %ret = select i1 %cond, i32 %a, i32 %b
    ret i32 %ret
@@ -107,7 +107,7 @@ entry:
 
 define void @f128_abs(fp128* noalias sret %scalar.result, fp128* byval %a) {
 entry:
-  %0 = load fp128* %a, align 8
+  %0 = load fp128, fp128* %a, align 8
   %1 = tail call fp128 @llvm.fabs.f128(fp128 %0)
   store fp128 %1, fp128* %scalar.result, align 8
   ret void
@@ -142,8 +142,8 @@ entry:
 
 define void @fp128_unaligned(fp128* %a, fp128* %b, fp128* %c) {
 entry:
-  %0 = load fp128* %a, align 1
-  %1 = load fp128* %b, align 1
+  %0 = load fp128, fp128* %a, align 1
+  %1 = load fp128, fp128* %b, align 1
   %2 = fadd fp128 %0, %1
   store fp128 %2, fp128* %c, align 1
   ret void
@@ -173,8 +173,8 @@ entry:
 
 define i32 @f128_to_i32(fp128* %a, fp128* %b) {
 entry:
-  %0 = load fp128* %a, align 8
-  %1 = load fp128* %b, align 8
+  %0 = load fp128, fp128* %a, align 8
+  %1 = load fp128, fp128* %b, align 8
   %2 = fptoui fp128 %0 to i32
   %3 = fptosi fp128 %1 to i32
   %4 = add i32 %2, %3
@@ -182,26 +182,28 @@ entry:
 }
 
 ; HARD-LABEL:    test_itoq_qtoi
-; HARD:          call _Q_lltoq
-; HARD:          call _Q_qtoll
-; HARD:          fitoq
-; HARD:          fqtoi
+; HARD-DAG:      call _Q_lltoq
+; HARD-DAG:      call _Q_qtoll
+; HARD-DAG:      fitoq
+; HARD-DAG:      fqtoi
 
 ; SOFT-LABEL:    test_itoq_qtoi
-; SOFT:          call _Q_lltoq
-; SOFT:          call _Q_qtoll
-; SOFT:          call _Q_itoq
-; SOFT:          call _Q_qtoi
+; SOFT-DAG:      call _Q_lltoq
+; SOFT-DAG:      call _Q_qtoll
+; SOFT-DAG:      call _Q_itoq
+; SOFT-DAG:      call _Q_qtoi
 
-define void @test_itoq_qtoi(i64 %a, i32 %b, i64* %ptr0, fp128* %ptr1) {
+define void @test_itoq_qtoi(i64 %a, i32 %b, fp128* %c, fp128* %d, i64* %ptr0, fp128* %ptr1) {
 entry:
   %0 = sitofp i64 %a to fp128
   store  fp128 %0, fp128* %ptr1, align 8
-  %1 = fptosi fp128 %0 to i64
+  %cval = load fp128, fp128* %c, align 8
+  %1 = fptosi fp128 %cval to i64
   store  i64 %1, i64* %ptr0, align 8
   %2 = sitofp i32 %b to fp128
   store  fp128 %2, fp128* %ptr1, align 8
-  %3 = fptosi fp128 %2 to i32
+  %dval = load fp128, fp128* %d, align 8
+  %3 = fptosi fp128 %dval to i32
   %4 = bitcast i64* %ptr0 to i32*
   store  i32 %3, i32* %4, align 8
   ret void
@@ -219,15 +221,17 @@ entry:
 ; SOFT-DAG:      call _Q_utoq
 ; SOFT-DAG:      call _Q_qtou
 
-define void @test_utoq_qtou(i64 %a, i32 %b, i64* %ptr0, fp128* %ptr1) {
+define void @test_utoq_qtou(i64 %a, i32 %b, fp128* %c, fp128* %d, i64* %ptr0, fp128* %ptr1) {
 entry:
   %0 = uitofp i64 %a to fp128
   store  fp128 %0, fp128* %ptr1, align 8
-  %1 = fptoui fp128 %0 to i64
+  %cval = load fp128, fp128* %c, align 8
+  %1 = fptoui fp128 %cval to i64
   store  i64 %1, i64* %ptr0, align 8
   %2 = uitofp i32 %b to fp128
   store  fp128 %2, fp128* %ptr1, align 8
-  %3 = fptoui fp128 %2 to i32
+  %dval = load fp128, fp128* %d, align 8
+  %3 = fptoui fp128 %dval to i32
   %4 = bitcast i64* %ptr0 to i32*
   store  i32 %3, i32* %4, align 8
   ret void
@@ -238,7 +242,7 @@ entry:
 
 define void @f128_neg(fp128* noalias sret %scalar.result, fp128* byval %a) {
 entry:
-  %0 = load fp128* %a, align 8
+  %0 = load fp128, fp128* %a, align 8
   %1 = fsub fp128 0xL00000000000000008000000000000000, %0
   store fp128 %1, fp128* %scalar.result, align 8
   ret void
diff --git a/test/CodeGen/SPARC/globals.ll b/test/CodeGen/SPARC/globals.ll
index 3d3eba28af62..3ef135f6d70b 100644
--- a/test/CodeGen/SPARC/globals.ll
+++ b/test/CodeGen/SPARC/globals.ll
@@ -8,7 +8,7 @@
 @G = external global i8
 
 define zeroext i8 @loadG() {
-  %tmp = load i8* @G
+  %tmp = load i8, i8* @G
   ret i8 %tmp
 }
 
diff --git a/test/CodeGen/SPARC/inlineasm.ll b/test/CodeGen/SPARC/inlineasm.ll
index 2650533b7fec..526cde8de8b4 100644
--- a/test/CodeGen/SPARC/inlineasm.ll
+++ b/test/CodeGen/SPARC/inlineasm.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=sparc <%s | FileCheck %s
+; RUN: llc -march=sparc -no-integrated-as <%s | FileCheck %s
 
 ; CHECK-LABEL: test_constraint_r
 ; CHECK:       add %o1, %o0, %o0
diff --git a/test/CodeGen/SPARC/leafproc.ll b/test/CodeGen/SPARC/leafproc.ll
index abb8ed9be439..fd74e5ca723e 100644
--- a/test/CodeGen/SPARC/leafproc.ll
+++ b/test/CodeGen/SPARC/leafproc.ll
@@ -70,11 +70,11 @@ define i32 @leaf_proc_with_local_array(i32 %a, i32 %b, i32 %c) {
 entry:
   %array = alloca [2 x i32], align 4
   %0 = sub nsw i32 %b, %c
-  %1 = getelementptr inbounds [2 x i32]* %array, i32 0, i32 0
+  %1 = getelementptr inbounds [2 x i32], [2 x i32]* %array, i32 0, i32 0
   store i32 1, i32* %1, align 4
-  %2 = getelementptr inbounds [2 x i32]* %array, i32 0, i32 1
+  %2 = getelementptr inbounds [2 x i32], [2 x i32]* %array, i32 0, i32 1
   store i32 2, i32* %2, align 4
-  %3 = getelementptr inbounds [2 x i32]* %array, i32 0, i32 %a
-  %4 = load i32* %3, align 4
+  %3 = getelementptr inbounds [2 x i32], [2 x i32]* %array, i32 0, i32 %a
+  %4 = load i32, i32* %3, align 4
   ret i32 %4
 }
diff --git a/test/CodeGen/SPARC/mult-alt-generic-sparc.ll b/test/CodeGen/SPARC/mult-alt-generic-sparc.ll
index 6013b17d9372..49496c304d23 100644
--- a/test/CodeGen/SPARC/mult-alt-generic-sparc.ll
+++ b/test/CodeGen/SPARC/mult-alt-generic-sparc.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=sparc
+; RUN: llc < %s -march=sparc -no-integrated-as
 ; ModuleID = 'mult-alt-generic.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"
 target triple = "sparc"
@@ -33,10 +33,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,<r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,r<"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -48,10 +48,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,>r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,r>"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -63,7 +63,7 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
@@ -120,10 +120,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r,imr"(i32 1) nounwind
@@ -137,15 +137,15 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r,X"(i32 1) nounwind
   store i32 %2, i32* %out0, align 4
-  %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %3, i32* %out0, align 4
 ; No lowering support.
 ;  %4 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind
@@ -159,14 +159,14 @@ define void @single_p() nounwind {
 entry:
   %out0 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
-  %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
 }
 
 define void @multi_m() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*m|r,m|r"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
@@ -191,10 +191,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|<r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|r<"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -206,10 +206,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|>r"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|r>"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -221,7 +221,7 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|m"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
@@ -278,10 +278,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 1) nounwind
@@ -295,15 +295,15 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 1) nounwind
   store i32 %2, i32* %out0, align 4
-  %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %3, i32* %out0, align 4
 ; No lowering support.
 ;  %4 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind
@@ -317,7 +317,7 @@ define void @multi_p() nounwind {
 entry:
   %out0 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
-  %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
 }
diff --git a/test/CodeGen/SPARC/obj-relocs.ll b/test/CodeGen/SPARC/obj-relocs.ll
index 6d57598795d4..115263ac5d46 100644
--- a/test/CodeGen/SPARC/obj-relocs.ll
+++ b/test/CodeGen/SPARC/obj-relocs.ll
@@ -21,7 +21,7 @@
 
 define i64 @foo(i64 %a) {
 entry:
-  %0 = load i64* @AGlobalVar, align 4
+  %0 = load i64, i64* @AGlobalVar, align 4
   %1 = add i64 %a, %0
   %2 = call i64 @bar(i64 %1)
   ret i64 %2
diff --git a/test/CodeGen/SPARC/private.ll b/test/CodeGen/SPARC/private.ll
index 38cea4ca6e4f..400d907e150f 100644
--- a/test/CodeGen/SPARC/private.ll
+++ b/test/CodeGen/SPARC/private.ll
@@ -11,7 +11,7 @@ define private void @foo() {
 
 define i32 @bar() {
         call void @foo()
-	%1 = load i32* @baz, align 4
+	%1 = load i32, i32* @baz, align 4
         ret i32 %1
 }
 
diff --git a/test/CodeGen/SPARC/setjmp.ll b/test/CodeGen/SPARC/setjmp.ll
index 17afb36ca74c..17519c516273 100644
--- a/test/CodeGen/SPARC/setjmp.ll
+++ b/test/CodeGen/SPARC/setjmp.ll
@@ -26,16 +26,16 @@
 ; Function Attrs: nounwind
 define i32 @foo(%struct.jmpbuf_env* byval %inbuf) #0 {
 entry:
-  %0 = getelementptr inbounds %struct.jmpbuf_env* %inbuf, i32 0, i32 0
+  %0 = getelementptr inbounds %struct.jmpbuf_env, %struct.jmpbuf_env* %inbuf, i32 0, i32 0
   store i32 0, i32* %0, align 4, !tbaa !4
-  %1 = getelementptr inbounds %struct.jmpbuf_env* %inbuf, i32 0, i32 1
+  %1 = getelementptr inbounds %struct.jmpbuf_env, %struct.jmpbuf_env* %inbuf, i32 0, i32 1
   store i32 1, i32* %1, align 4, !tbaa !4
-  %2 = getelementptr inbounds %struct.jmpbuf_env* %inbuf, i32 0, i32 2, i32 0
+  %2 = getelementptr inbounds %struct.jmpbuf_env, %struct.jmpbuf_env* %inbuf, i32 0, i32 2, i32 0
   %3 = call i32 @_setjmp(%struct.__jmp_buf_tag* %2) #2
-  %4 = getelementptr inbounds %struct.jmpbuf_env* %inbuf, i32 0, i32 3
+  %4 = getelementptr inbounds %struct.jmpbuf_env, %struct.jmpbuf_env* %inbuf, i32 0, i32 3
   store i32 %3, i32* %4, align 4, !tbaa !4
   store %struct.jmpbuf_env* %inbuf, %struct.jmpbuf_env** @jenv, align 4, !tbaa !3
-  %5 = load i32* %1, align 4, !tbaa !4
+  %5 = load i32, i32* %1, align 4, !tbaa !4
   %6 = icmp eq i32 %5, 1
   %7 = icmp eq i32 %3, 0
   %or.cond = and i1 %6, %7
@@ -46,8 +46,8 @@ entry:
   unreachable
 
 bar.exit:                                         ; preds = %entry
-  %8 = load i32* %0, align 4, !tbaa !4
-  %9 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([30 x i8]* @.cst, i32 0, i32 0), i32 %8) #0
+  %8 = load i32, i32* %0, align 4, !tbaa !4
+  %9 = call i32 (i8*, ...) @printf(i8* noalias getelementptr inbounds ([30 x i8], [30 x i8]* @.cst, i32 0, i32 0), i32 %8) #0
   ret i32 0
 }
 
diff --git a/test/CodeGen/SPARC/spillsize.ll b/test/CodeGen/SPARC/spillsize.ll
index 64f63f97d509..a82e5098ffd0 100644
--- a/test/CodeGen/SPARC/spillsize.ll
+++ b/test/CodeGen/SPARC/spillsize.ll
@@ -11,13 +11,13 @@ target triple = "sparcv9"
 ; CHECK: ldx [%fp+
 define void @spill4(i64* nocapture %p) {
 entry:
-  %val0 = load i64* %p
+  %val0 = load i64, i64* %p
   %cmp0 = icmp ult i64 %val0, 385672958347594845
   %cm80 = zext i1 %cmp0 to i64
   store i64 %cm80, i64* %p, align 8
   tail call void asm sideeffect "", "~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{g2},~{g3},~{g4},~{g5},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o7}"()
-  %arrayidx1 = getelementptr inbounds i64* %p, i64 1
-  %val = load i64* %arrayidx1
+  %arrayidx1 = getelementptr inbounds i64, i64* %p, i64 1
+  %val = load i64, i64* %arrayidx1
   %cmp = icmp ult i64 %val, 385672958347594845
   %cm8 = select i1 %cmp, i64 10, i64 20
   store i64 %cm8, i64* %arrayidx1, align 8
diff --git a/test/CodeGen/SPARC/tls.ll b/test/CodeGen/SPARC/tls.ll
index ce3e00539845..a70637b283f5 100644
--- a/test/CodeGen/SPARC/tls.ll
+++ b/test/CodeGen/SPARC/tls.ll
@@ -34,7 +34,7 @@
 
 define i32 @test_tls_local() {
 entry:
-  %0 = load i32* @local_symbol, align 4
+  %0 = load i32, i32* @local_symbol, align 4
   %1 = add i32 %0, 1
   store i32 %1, i32* @local_symbol, align 4
   ret i32 %1
@@ -68,7 +68,7 @@ entry:
 
 define i32 @test_tls_extern() {
 entry:
-  %0 = load i32* @extern_symbol, align 4
+  %0 = load i32, i32* @extern_symbol, align 4
   %1 = add i32 %0, 1
   store i32 %1, i32* @extern_symbol, align 4
   ret i32 %1
@@ -99,7 +99,7 @@ entry:
 ; v9abs-obj: ]
 
 ; pic-obj: Relocations [
-; pic-obj:  Section (2) .rela.text {
+; pic-obj:  Section {{.*}} .rela.text {
 ; pic-obj:    0x{{[0-9,A-F]+}} R_SPARC_PC22 _GLOBAL_OFFSET_TABLE_ 0x4
 ; pic-obj:    0x{{[0-9,A-F]+}} R_SPARC_PC10 _GLOBAL_OFFSET_TABLE_ 0x8
 ; pic-obj:    0x{{[0-9,A-F]+}} R_SPARC_TLS_LDO_HIX22 local_symbol 0x0
diff --git a/test/CodeGen/SPARC/varargs.ll b/test/CodeGen/SPARC/varargs.ll
index 76e16cd44f6a..c2d1e98b698b 100644
--- a/test/CodeGen/SPARC/varargs.ll
+++ b/test/CodeGen/SPARC/varargs.ll
@@ -24,8 +24,8 @@ entry:
 for.cond:
   %fmt.addr.0 = phi i8* [ %fmt, %entry ], [ %incdec.ptr, %for.cond.backedge ]
   %sum.addr.0 = phi double [ %sum, %entry ], [ %sum.addr.0.be, %for.cond.backedge ]
-  %incdec.ptr = getelementptr inbounds i8* %fmt.addr.0, i64 1
-  %0 = load i8* %fmt.addr.0, align 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %fmt.addr.0, i64 1
+  %0 = load i8, i8* %fmt.addr.0, align 1
   %conv = sext i8 %0 to i32
   switch i32 %conv, label %sw.default [
     i32 105, label %sw.bb
@@ -71,6 +71,6 @@ declare void @llvm.va_start(i8*)
 ; CHECK: , %f2
 define i32 @call_1d() #0 {
 entry:
-  %call = call double (i8*, double, ...)* @varargsfunc(i8* undef, double 1.000000e+00, double 2.000000e+00)
+  %call = call double (i8*, double, ...) @varargsfunc(i8* undef, double 1.000000e+00, double 2.000000e+00)
   ret i32 1
 }
diff --git a/test/CodeGen/SystemZ/Large/branch-range-01.py b/test/CodeGen/SystemZ/Large/branch-range-01.py
index edb631d8c6d5..365d7e420818 100644
--- a/test/CodeGen/SystemZ/Large/branch-range-01.py
+++ b/test/CodeGen/SystemZ/Large/branch-range-01.py
@@ -78,8 +78,8 @@ print ''
 for i in xrange(branch_blocks):
     next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
     print 'before%d:' % i
-    print '  %%bstop%d = getelementptr i32 *%%stop, i64 %d' % (i, i)
-    print '  %%bcur%d = load i32 *%%bstop%d' % (i, i)
+    print '  %%bstop%d = getelementptr i32, i32 *%%stop, i64 %d' % (i, i)
+    print '  %%bcur%d = load i32 , i32 *%%bstop%d' % (i, i)
     print '  %%btest%d = icmp eq i32 %%limit, %%bcur%d' % (i, i)
     print '  br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
     print ''
@@ -90,12 +90,12 @@ for i in xrange(0, main_size, 6):
     a, b = b, a + b
     offset = 4096 + b % 500000
     value = a % 256
-    print '  %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset)
+    print '  %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
     print '  store volatile i8 %d, i8 *%%ptr%d' % (value, i)
 
 for i in xrange(branch_blocks):
-    print '  %%astop%d = getelementptr i32 *%%stop, i64 %d' % (i, i + 25)
-    print '  %%acur%d = load i32 *%%astop%d' % (i, i)
+    print '  %%astop%d = getelementptr i32, i32 *%%stop, i64 %d' % (i, i + 25)
+    print '  %%acur%d = load i32 , i32 *%%astop%d' % (i, i)
     print '  %%atest%d = icmp eq i32 %%limit, %%acur%d' % (i, i)
     print '  br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
     print ''
diff --git a/test/CodeGen/SystemZ/Large/branch-range-02.py b/test/CodeGen/SystemZ/Large/branch-range-02.py
index 743e12de0f1f..7f7b09954a61 100644
--- a/test/CodeGen/SystemZ/Large/branch-range-02.py
+++ b/test/CodeGen/SystemZ/Large/branch-range-02.py
@@ -71,8 +71,8 @@ for i in xrange(blocks):
     other = 'end' if 2 * i < blocks else 'b0'
     print 'b%d:' % i
     print '  store volatile i8 %d, i8 *%%base' % value
-    print '  %%astop%d = getelementptr i32 *%%stop, i64 %d' % (i, i)
-    print '  %%acur%d = load i32 *%%astop%d' % (i, i)
+    print '  %%astop%d = getelementptr i32, i32 *%%stop, i64 %d' % (i, i)
+    print '  %%acur%d = load i32 , i32 *%%astop%d' % (i, i)
     print '  %%atest%d = icmp eq i32 %%limit, %%acur%d' % (i, i)
     print '  br i1 %%atest%d, label %%%s, label %%%s' % (i, other, next)
 
diff --git a/test/CodeGen/SystemZ/Large/branch-range-03.py b/test/CodeGen/SystemZ/Large/branch-range-03.py
index 5c9a93b87f73..745d733211ff 100644
--- a/test/CodeGen/SystemZ/Large/branch-range-03.py
+++ b/test/CodeGen/SystemZ/Large/branch-range-03.py
@@ -78,8 +78,8 @@ print ''
 for i in xrange(branch_blocks):
     next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
     print 'before%d:' % i
-    print '  %%bstop%d = getelementptr i8 *%%stop, i64 %d' % (i, i)
-    print '  %%bcur%d = load i8 *%%bstop%d' % (i, i)
+    print '  %%bstop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i)
+    print '  %%bcur%d = load i8 , i8 *%%bstop%d' % (i, i)
     print '  %%bext%d = sext i8 %%bcur%d to i32' % (i, i)
     print '  %%btest%d = icmp eq i32 %%limit, %%bext%d' % (i, i)
     print '  br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
@@ -91,12 +91,12 @@ for i in xrange(0, main_size, 6):
     a, b = b, a + b
     offset = 4096 + b % 500000
     value = a % 256
-    print '  %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset)
+    print '  %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
     print '  store volatile i8 %d, i8 *%%ptr%d' % (value, i)
 
 for i in xrange(branch_blocks):
-    print '  %%astop%d = getelementptr i8 *%%stop, i64 %d' % (i, i + 25)
-    print '  %%acur%d = load i8 *%%astop%d' % (i, i)
+    print '  %%astop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i + 25)
+    print '  %%acur%d = load i8 , i8 *%%astop%d' % (i, i)
     print '  %%aext%d = sext i8 %%acur%d to i32' % (i, i)
     print '  %%atest%d = icmp eq i32 %%limit, %%aext%d' % (i, i)
     print '  br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
diff --git a/test/CodeGen/SystemZ/Large/branch-range-04.py b/test/CodeGen/SystemZ/Large/branch-range-04.py
index 2c9090fa2067..a0c9c4426456 100644
--- a/test/CodeGen/SystemZ/Large/branch-range-04.py
+++ b/test/CodeGen/SystemZ/Large/branch-range-04.py
@@ -82,8 +82,8 @@ print ''
 for i in xrange(branch_blocks):
     next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
     print 'before%d:' % i
-    print '  %%bstop%d = getelementptr i8 *%%stop, i64 %d' % (i, i)
-    print '  %%bcur%d = load i8 *%%bstop%d' % (i, i)
+    print '  %%bstop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i)
+    print '  %%bcur%d = load i8 , i8 *%%bstop%d' % (i, i)
     print '  %%bext%d = sext i8 %%bcur%d to i64' % (i, i)
     print '  %%btest%d = icmp eq i64 %%limit, %%bext%d' % (i, i)
     print '  br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
@@ -95,12 +95,12 @@ for i in xrange(0, main_size, 6):
     a, b = b, a + b
     offset = 4096 + b % 500000
     value = a % 256
-    print '  %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset)
+    print '  %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
     print '  store volatile i8 %d, i8 *%%ptr%d' % (value, i)
 
 for i in xrange(branch_blocks):
-    print '  %%astop%d = getelementptr i8 *%%stop, i64 %d' % (i, i + 25)
-    print '  %%acur%d = load i8 *%%astop%d' % (i, i)
+    print '  %%astop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i + 25)
+    print '  %%acur%d = load i8 , i8 *%%astop%d' % (i, i)
     print '  %%aext%d = sext i8 %%acur%d to i64' % (i, i)
     print '  %%atest%d = icmp eq i64 %%limit, %%aext%d' % (i, i)
     print '  br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
diff --git a/test/CodeGen/SystemZ/Large/branch-range-05.py b/test/CodeGen/SystemZ/Large/branch-range-05.py
index 52f4a961c88f..69a8112162a0 100644
--- a/test/CodeGen/SystemZ/Large/branch-range-05.py
+++ b/test/CodeGen/SystemZ/Large/branch-range-05.py
@@ -82,7 +82,7 @@ print ''
 for i in xrange(branch_blocks):
     next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
     print 'before%d:' % i
-    print '  %%bcur%d = load i8 *%%stop' % i
+    print '  %%bcur%d = load i8 , i8 *%%stop' % i
     print '  %%bext%d = sext i8 %%bcur%d to i32' % (i, i)
     print '  %%btest%d = icmp slt i32 %%bext%d, %d' % (i, i, i + 50)
     print '  br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
@@ -94,11 +94,11 @@ for i in xrange(0, main_size, 6):
     a, b = b, a + b
     offset = 4096 + b % 500000
     value = a % 256
-    print '  %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset)
+    print '  %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
     print '  store volatile i8 %d, i8 *%%ptr%d' % (value, i)
 
 for i in xrange(branch_blocks):
-    print '  %%acur%d = load i8 *%%stop' % i
+    print '  %%acur%d = load i8 , i8 *%%stop' % i
     print '  %%aext%d = sext i8 %%acur%d to i32' % (i, i)
     print '  %%atest%d = icmp slt i32 %%aext%d, %d' % (i, i, i + 100)
     print '  br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
diff --git a/test/CodeGen/SystemZ/Large/branch-range-06.py b/test/CodeGen/SystemZ/Large/branch-range-06.py
index c34ebac4ce36..b08bc119c454 100644
--- a/test/CodeGen/SystemZ/Large/branch-range-06.py
+++ b/test/CodeGen/SystemZ/Large/branch-range-06.py
@@ -82,7 +82,7 @@ print ''
 for i in xrange(branch_blocks):
     next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
     print 'before%d:' % i
-    print '  %%bcur%d = load i8 *%%stop' % i
+    print '  %%bcur%d = load i8 , i8 *%%stop' % i
     print '  %%bext%d = sext i8 %%bcur%d to i64' % (i, i)
     print '  %%btest%d = icmp slt i64 %%bext%d, %d' % (i, i, i + 50)
     print '  br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
@@ -94,11 +94,11 @@ for i in xrange(0, main_size, 6):
     a, b = b, a + b
     offset = 4096 + b % 500000
     value = a % 256
-    print '  %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset)
+    print '  %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
     print '  store volatile i8 %d, i8 *%%ptr%d' % (value, i)
 
 for i in xrange(branch_blocks):
-    print '  %%acur%d = load i8 *%%stop' % i
+    print '  %%acur%d = load i8 , i8 *%%stop' % i
     print '  %%aext%d = sext i8 %%acur%d to i64' % (i, i)
     print '  %%atest%d = icmp slt i64 %%aext%d, %d' % (i, i, i + 100)
     print '  br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
diff --git a/test/CodeGen/SystemZ/Large/branch-range-07.py b/test/CodeGen/SystemZ/Large/branch-range-07.py
index 90c442092e82..c5fef10577f6 100644
--- a/test/CodeGen/SystemZ/Large/branch-range-07.py
+++ b/test/CodeGen/SystemZ/Large/branch-range-07.py
@@ -39,8 +39,8 @@ print 'define void @f1(i8 *%base, i32 *%counts) {'
 print 'entry:'
 
 for i in xrange(branch_blocks - 1, -1, -1):
-    print '  %%countptr%d = getelementptr i32 *%%counts, i64 %d' % (i, i)
-    print '  %%initcount%d = load i32 *%%countptr%d' % (i, i)
+    print '  %%countptr%d = getelementptr i32, i32 *%%counts, i64 %d' % (i, i)
+    print '  %%initcount%d = load i32 , i32 *%%countptr%d' % (i, i)
     print '  br label %%loop%d' % i
     
     print 'loop%d:' % i
@@ -54,7 +54,7 @@ for i in xrange(0, main_size, 6):
     a, b = b, a + b
     offset = 4096 + b % 500000
     value = a % 256
-    print '  %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset)
+    print '  %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
     print '  store volatile i8 %d, i8 *%%ptr%d' % (value, i)
 
 for i in xrange(branch_blocks):
diff --git a/test/CodeGen/SystemZ/Large/branch-range-08.py b/test/CodeGen/SystemZ/Large/branch-range-08.py
index ac1b1370a3e3..8b6b67398337 100644
--- a/test/CodeGen/SystemZ/Large/branch-range-08.py
+++ b/test/CodeGen/SystemZ/Large/branch-range-08.py
@@ -40,8 +40,8 @@ print 'define void @f1(i8 *%base, i64 *%counts) {'
 print 'entry:'
 
 for i in xrange(branch_blocks - 1, -1, -1):
-    print '  %%countptr%d = getelementptr i64 *%%counts, i64 %d' % (i, i)
-    print '  %%initcount%d = load i64 *%%countptr%d' % (i, i)
+    print '  %%countptr%d = getelementptr i64, i64 *%%counts, i64 %d' % (i, i)
+    print '  %%initcount%d = load i64 , i64 *%%countptr%d' % (i, i)
     print '  br label %%loop%d' % i
     
     print 'loop%d:' % i
@@ -55,7 +55,7 @@ for i in xrange(0, main_size, 6):
     a, b = b, a + b
     offset = 4096 + b % 500000
     value = a % 256
-    print '  %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset)
+    print '  %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
     print '  store volatile i8 %d, i8 *%%ptr%d' % (value, i)
 
 for i in xrange(branch_blocks):
diff --git a/test/CodeGen/SystemZ/Large/branch-range-09.py b/test/CodeGen/SystemZ/Large/branch-range-09.py
index bc712cb164ea..d4693358f502 100644
--- a/test/CodeGen/SystemZ/Large/branch-range-09.py
+++ b/test/CodeGen/SystemZ/Large/branch-range-09.py
@@ -78,8 +78,8 @@ print ''
 for i in xrange(branch_blocks):
     next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
     print 'before%d:' % i
-    print '  %%bstop%d = getelementptr i8 *%%stop, i64 %d' % (i, i)
-    print '  %%bcur%d = load i8 *%%bstop%d' % (i, i)
+    print '  %%bstop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i)
+    print '  %%bcur%d = load i8 , i8 *%%bstop%d' % (i, i)
     print '  %%bext%d = sext i8 %%bcur%d to i32' % (i, i)
     print '  %%btest%d = icmp ult i32 %%limit, %%bext%d' % (i, i)
     print '  br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
@@ -91,12 +91,12 @@ for i in xrange(0, main_size, 6):
     a, b = b, a + b
     offset = 4096 + b % 500000
     value = a % 256
-    print '  %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset)
+    print '  %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
     print '  store volatile i8 %d, i8 *%%ptr%d' % (value, i)
 
 for i in xrange(branch_blocks):
-    print '  %%astop%d = getelementptr i8 *%%stop, i64 %d' % (i, i + 25)
-    print '  %%acur%d = load i8 *%%astop%d' % (i, i)
+    print '  %%astop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i + 25)
+    print '  %%acur%d = load i8 , i8 *%%astop%d' % (i, i)
     print '  %%aext%d = sext i8 %%acur%d to i32' % (i, i)
     print '  %%atest%d = icmp ult i32 %%limit, %%aext%d' % (i, i)
     print '  br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
diff --git a/test/CodeGen/SystemZ/Large/branch-range-10.py b/test/CodeGen/SystemZ/Large/branch-range-10.py
index 8c483c33724c..c928081f5544 100644
--- a/test/CodeGen/SystemZ/Large/branch-range-10.py
+++ b/test/CodeGen/SystemZ/Large/branch-range-10.py
@@ -82,8 +82,8 @@ print ''
 for i in xrange(branch_blocks):
     next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
     print 'before%d:' % i
-    print '  %%bstop%d = getelementptr i8 *%%stop, i64 %d' % (i, i)
-    print '  %%bcur%d = load i8 *%%bstop%d' % (i, i)
+    print '  %%bstop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i)
+    print '  %%bcur%d = load i8 , i8 *%%bstop%d' % (i, i)
     print '  %%bext%d = sext i8 %%bcur%d to i64' % (i, i)
     print '  %%btest%d = icmp ult i64 %%limit, %%bext%d' % (i, i)
     print '  br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
@@ -95,12 +95,12 @@ for i in xrange(0, main_size, 6):
     a, b = b, a + b
     offset = 4096 + b % 500000
     value = a % 256
-    print '  %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset)
+    print '  %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
     print '  store volatile i8 %d, i8 *%%ptr%d' % (value, i)
 
 for i in xrange(branch_blocks):
-    print '  %%astop%d = getelementptr i8 *%%stop, i64 %d' % (i, i + 25)
-    print '  %%acur%d = load i8 *%%astop%d' % (i, i)
+    print '  %%astop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i + 25)
+    print '  %%acur%d = load i8 , i8 *%%astop%d' % (i, i)
     print '  %%aext%d = sext i8 %%acur%d to i64' % (i, i)
     print '  %%atest%d = icmp ult i64 %%limit, %%aext%d' % (i, i)
     print '  br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
diff --git a/test/CodeGen/SystemZ/Large/branch-range-11.py b/test/CodeGen/SystemZ/Large/branch-range-11.py
index 054610380e31..85166bc15656 100644
--- a/test/CodeGen/SystemZ/Large/branch-range-11.py
+++ b/test/CodeGen/SystemZ/Large/branch-range-11.py
@@ -98,8 +98,8 @@ print ''
 for i in xrange(branch_blocks):
     next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
     print 'before%d:' % i
-    print '  %%bcur%da = load i32 *%%stopa' % i
-    print '  %%bcur%db = load i32 *%%stopb' % i
+    print '  %%bcur%da = load i32 , i32 *%%stopa' % i
+    print '  %%bcur%db = load i32 , i32 *%%stopb' % i
     print '  %%bsub%d = sub i32 %%bcur%da, %%bcur%db' % (i, i, i)
     print '  %%btest%d = icmp ult i32 %%bsub%d, %d' % (i, i, i + 50)
     print '  br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
@@ -111,12 +111,12 @@ for i in xrange(0, main_size, 6):
     a, b = b, a + b
     offset = 4096 + b % 500000
     value = a % 256
-    print '  %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset)
+    print '  %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
     print '  store volatile i8 %d, i8 *%%ptr%d' % (value, i)
 
 for i in xrange(branch_blocks):
-    print '  %%acur%da = load i32 *%%stopa' % i
-    print '  %%acur%db = load i32 *%%stopb' % i
+    print '  %%acur%da = load i32 , i32 *%%stopa' % i
+    print '  %%acur%db = load i32 , i32 *%%stopb' % i
     print '  %%asub%d = sub i32 %%acur%da, %%acur%db' % (i, i, i)
     print '  %%atest%d = icmp ult i32 %%asub%d, %d' % (i, i, i + 100)
     print '  br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
diff --git a/test/CodeGen/SystemZ/Large/branch-range-12.py b/test/CodeGen/SystemZ/Large/branch-range-12.py
index 626c8998d5d4..e1d9e2977d41 100644
--- a/test/CodeGen/SystemZ/Large/branch-range-12.py
+++ b/test/CodeGen/SystemZ/Large/branch-range-12.py
@@ -98,8 +98,8 @@ print ''
 for i in xrange(branch_blocks):
     next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
     print 'before%d:' % i
-    print '  %%bcur%da = load i64 *%%stopa' % i
-    print '  %%bcur%db = load i64 *%%stopb' % i
+    print '  %%bcur%da = load i64 , i64 *%%stopa' % i
+    print '  %%bcur%db = load i64 , i64 *%%stopb' % i
     print '  %%bsub%d = sub i64 %%bcur%da, %%bcur%db' % (i, i, i)
     print '  %%btest%d = icmp ult i64 %%bsub%d, %d' % (i, i, i + 50)
     print '  br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
@@ -111,12 +111,12 @@ for i in xrange(0, main_size, 6):
     a, b = b, a + b
     offset = 4096 + b % 500000
     value = a % 256
-    print '  %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset)
+    print '  %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
     print '  store volatile i8 %d, i8 *%%ptr%d' % (value, i)
 
 for i in xrange(branch_blocks):
-    print '  %%acur%da = load i64 *%%stopa' % i
-    print '  %%acur%db = load i64 *%%stopb' % i
+    print '  %%acur%da = load i64 , i64 *%%stopa' % i
+    print '  %%acur%db = load i64 , i64 *%%stopb' % i
     print '  %%asub%d = sub i64 %%acur%da, %%acur%db' % (i, i, i)
     print '  %%atest%d = icmp ult i64 %%asub%d, %d' % (i, i, i + 100)
     print '  br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
diff --git a/test/CodeGen/SystemZ/Large/lit.local.cfg b/test/CodeGen/SystemZ/Large/lit.local.cfg
index 4f22a970c3a6..d9d464726135 100644
--- a/test/CodeGen/SystemZ/Large/lit.local.cfg
+++ b/test/CodeGen/SystemZ/Large/lit.local.cfg
@@ -1,8 +1,8 @@
 config.suffixes = ['.py']
 
 # These tests take on the order of seconds to run, so skip them unless
-# running natively.
-if config.root.host_arch not in ['SystemZ']:
+# we're running long tests.
+if 'long_tests' not in config.available_features:
     config.unsupported = True
 
 if not 'SystemZ' in config.root.targets:
diff --git a/test/CodeGen/SystemZ/Large/spill-01.py b/test/CodeGen/SystemZ/Large/spill-01.py
index 3c1d0b611bb4..f59f607d5beb 100644
--- a/test/CodeGen/SystemZ/Large/spill-01.py
+++ b/test/CodeGen/SystemZ/Large/spill-01.py
@@ -25,8 +25,8 @@ print ''
 print 'define void @f1(i64 *%base0, i64 *%base1) {'
 
 for i in range(count):
-    print '  %%ptr%d = getelementptr i64 *%%base%d, i64 %d' % (i, i % 2, i / 2)
-    print '  %%val%d = load i64 *%%ptr%d' % (i, i)
+    print '  %%ptr%d = getelementptr i64, i64 *%%base%d, i64 %d' % (i, i % 2, i / 2)
+    print '  %%val%d = load i64 , i64 *%%ptr%d' % (i, i)
     print ''
 
 print '  call void @foo()'
diff --git a/test/CodeGen/SystemZ/Large/spill-02.py b/test/CodeGen/SystemZ/Large/spill-02.py
index 0aa43d18054b..4ccfa11a0d3e 100644
--- a/test/CodeGen/SystemZ/Large/spill-02.py
+++ b/test/CodeGen/SystemZ/Large/spill-02.py
@@ -29,7 +29,7 @@ print 'entry:'
 
 # Make the allocation big, so that it goes at the top of the frame.
 print '  %array = alloca [1000 x i64]'
-print '  %area = getelementptr [1000 x i64] *%array, i64 0, i64 0'
+print '  %area = getelementptr [1000 x i64], [1000 x i64] *%array, i64 0, i64 0'
 print '  %%base = call i64 *@foo(i64 *%%area%s)' % (', i64 0' * args)
 print ''
 
@@ -37,8 +37,8 @@ print ''
 # another for %base, so we need 14 live values.
 count = 14
 for i in range(count):
-    print '  %%ptr%d = getelementptr i64 *%%base, i64 %d' % (i, i / 2)
-    print '  %%val%d = load volatile i64 *%%ptr%d' % (i, i)
+    print '  %%ptr%d = getelementptr i64, i64 *%%base, i64 %d' % (i, i / 2)
+    print '  %%val%d = load volatile i64 , i64 *%%ptr%d' % (i, i)
     print ''
 
 # Encourage the register allocator to give preference to these %vals
diff --git a/test/CodeGen/SystemZ/addr-01.ll b/test/CodeGen/SystemZ/addr-01.ll
index d0960cdb1047..736efe8887d6 100644
--- a/test/CodeGen/SystemZ/addr-01.ll
+++ b/test/CodeGen/SystemZ/addr-01.ll
@@ -10,7 +10,7 @@ define void @f1(i64 %addr, i64 %index) {
 ; CHECK: br %r14
   %add = add i64 %addr, %index
   %ptr = inttoptr i64 %add to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   ret void
 }
 
@@ -22,7 +22,7 @@ define void @f2(i64 %addr, i64 %index) {
   %add1 = add i64 %addr, %index
   %add2 = add i64 %add1, 100
   %ptr = inttoptr i64 %add2 to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   ret void
 }
 
@@ -34,7 +34,7 @@ define void @f3(i64 %addr, i64 %index) {
   %add1 = add i64 %addr, 100
   %add2 = add i64 %add1, %index
   %ptr = inttoptr i64 %add2 to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   ret void
 }
 
@@ -46,7 +46,7 @@ define void @f4(i64 %addr, i64 %index) {
   %add1 = add i64 %addr, %index
   %add2 = sub i64 %add1, 100
   %ptr = inttoptr i64 %add2 to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   ret void
 }
 
@@ -58,7 +58,7 @@ define void @f5(i64 %addr, i64 %index) {
   %add1 = sub i64 %addr, 100
   %add2 = add i64 %add1, %index
   %ptr = inttoptr i64 %add2 to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   ret void
 }
 
@@ -72,7 +72,7 @@ define void @f6(i64 %addr, i64 %index) {
   %or = or i64 %aligned, 6
   %add = add i64 %or, %index
   %ptr = inttoptr i64 %add to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   ret void
 }
 
@@ -85,7 +85,7 @@ define void @f7(i64 %addr, i64 %index) {
   %or = or i64 %addr, 6
   %add = add i64 %or, %index
   %ptr = inttoptr i64 %add to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   ret void
 }
 
@@ -102,6 +102,6 @@ define void @f8(i64 %addr, i64 %index) {
   %add = add i64 %aligned, %index
   %or = or i64 %add, 6
   %ptr = inttoptr i64 %or to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   ret void
 }
diff --git a/test/CodeGen/SystemZ/addr-02.ll b/test/CodeGen/SystemZ/addr-02.ll
index 56c48794b072..7e9b2f18ef82 100644
--- a/test/CodeGen/SystemZ/addr-02.ll
+++ b/test/CodeGen/SystemZ/addr-02.ll
@@ -11,7 +11,7 @@ define void @f1(i64 %addr, i64 %index, i8 **%dst) {
 ; CHECK: br %r14
   %add = add i64 %addr, %index
   %ptr = inttoptr i64 %add to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   store volatile i8 *%ptr, i8 **%dst
   ret void
 }
@@ -24,7 +24,7 @@ define void @f2(i64 %addr, i64 %index, i8 **%dst) {
   %add1 = add i64 %addr, %index
   %add2 = add i64 %add1, 100
   %ptr = inttoptr i64 %add2 to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   store volatile i8 *%ptr, i8 **%dst
   ret void
 }
@@ -37,7 +37,7 @@ define void @f3(i64 %addr, i64 %index, i8 **%dst) {
   %add1 = add i64 %addr, 100
   %add2 = add i64 %add1, %index
   %ptr = inttoptr i64 %add2 to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   store volatile i8 *%ptr, i8 **%dst
   ret void
 }
@@ -50,7 +50,7 @@ define void @f4(i64 %addr, i64 %index, i8 **%dst) {
   %add1 = add i64 %addr, %index
   %add2 = sub i64 %add1, 100
   %ptr = inttoptr i64 %add2 to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   store volatile i8 *%ptr, i8 **%dst
   ret void
 }
@@ -63,7 +63,7 @@ define void @f5(i64 %addr, i64 %index, i8 **%dst) {
   %add1 = sub i64 %addr, 100
   %add2 = add i64 %add1, %index
   %ptr = inttoptr i64 %add2 to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   store volatile i8 *%ptr, i8 **%dst
   ret void
 }
@@ -78,7 +78,7 @@ define void @f6(i64 %addr, i64 %index, i8 **%dst) {
   %or = or i64 %aligned, 6
   %add = add i64 %or, %index
   %ptr = inttoptr i64 %add to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   store volatile i8 *%ptr, i8 **%dst
   ret void
 }
@@ -92,7 +92,7 @@ define void @f7(i64 %addr, i64 %index, i8 **%dst) {
   %or = or i64 %addr, 6
   %add = add i64 %or, %index
   %ptr = inttoptr i64 %add to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   store volatile i8 *%ptr, i8 **%dst
   ret void
 }
@@ -110,7 +110,7 @@ define void @f8(i64 %addr, i64 %index, i8 **%dst) {
   %add = add i64 %aligned, %index
   %or = or i64 %add, 6
   %ptr = inttoptr i64 %or to i8 *
-  %a = load volatile i8 *%ptr
+  %a = load volatile i8 , i8 *%ptr
   store volatile i8 *%ptr, i8 **%dst
   ret void
 }
diff --git a/test/CodeGen/SystemZ/addr-03.ll b/test/CodeGen/SystemZ/addr-03.ll
index 1146926a4c2e..b2fd400c6bda 100644
--- a/test/CodeGen/SystemZ/addr-03.ll
+++ b/test/CodeGen/SystemZ/addr-03.ll
@@ -7,7 +7,7 @@ define void @f1() {
 ; CHECK: lb %r0, 0
 ; CHECK: br %r14
   %ptr = inttoptr i64 0 to i8 *
-  %val = load volatile i8 *%ptr
+  %val = load volatile i8 , i8 *%ptr
   ret void
 }
 
@@ -16,7 +16,7 @@ define void @f2() {
 ; CHECK: lb %r0, -524288
 ; CHECK: br %r14
   %ptr = inttoptr i64 -524288 to i8 *
-  %val = load volatile i8 *%ptr
+  %val = load volatile i8 , i8 *%ptr
   ret void
 }
 
@@ -25,7 +25,7 @@ define void @f3() {
 ; CHECK-NOT: lb %r0, -524289
 ; CHECK: br %r14
   %ptr = inttoptr i64 -524289 to i8 *
-  %val = load volatile i8 *%ptr
+  %val = load volatile i8 , i8 *%ptr
   ret void
 }
 
@@ -34,7 +34,7 @@ define void @f4() {
 ; CHECK: lb %r0, 524287
 ; CHECK: br %r14
   %ptr = inttoptr i64 524287 to i8 *
-  %val = load volatile i8 *%ptr
+  %val = load volatile i8 , i8 *%ptr
   ret void
 }
 
@@ -43,6 +43,6 @@ define void @f5() {
 ; CHECK-NOT: lb %r0, 524288
 ; CHECK: br %r14
   %ptr = inttoptr i64 524288 to i8 *
-  %val = load volatile i8 *%ptr
+  %val = load volatile i8 , i8 *%ptr
   ret void
 }
diff --git a/test/CodeGen/SystemZ/alias-01.ll b/test/CodeGen/SystemZ/alias-01.ll
index 89a731830187..852d18e8de79 100644
--- a/test/CodeGen/SystemZ/alias-01.ll
+++ b/test/CodeGen/SystemZ/alias-01.ll
@@ -7,7 +7,7 @@ define void @f1(<16 x i32> *%src1, <16 x float> *%dest) {
 ; CHECK-LABEL: f1:
 ; CHECK-NOT: %r15
 ; CHECK: br %r14
-  %val = load <16 x i32> *%src1, !tbaa !1
+  %val = load <16 x i32> , <16 x i32> *%src1, !tbaa !1
   %add = add <16 x i32> %val, %val
   %res = bitcast <16 x i32> %add to <16 x float>
   store <16 x float> %res, <16 x float> *%dest, !tbaa !2
diff --git a/test/CodeGen/SystemZ/alloca-01.ll b/test/CodeGen/SystemZ/alloca-01.ll
index 2ddefd70cc9d..06c336a331d8 100644
--- a/test/CodeGen/SystemZ/alloca-01.ll
+++ b/test/CodeGen/SystemZ/alloca-01.ll
@@ -52,13 +52,13 @@ define i64 @f1(i64 %length, i64 %index) {
 ; CHECK-FP: lgr %r11, %r15
 ; CHECK-FP: lmg %r6, %r15, 224(%r11)
   %a = alloca i8, i64 %length
-  %b = getelementptr i8 *%a, i64 1
+  %b = getelementptr i8, i8 *%a, i64 1
   %cindex = add i64 %index, 3919
-  %c = getelementptr i8 *%a, i64 %cindex
+  %c = getelementptr i8, i8 *%a, i64 %cindex
   %dindex = add i64 %index, 3920
-  %d = getelementptr i8 *%a, i64 %dindex
+  %d = getelementptr i8, i8 *%a, i64 %dindex
   %eindex = add i64 %index, 4095
-  %e = getelementptr i8 *%a, i64 %eindex
+  %e = getelementptr i8, i8 *%a, i64 %eindex
   %count = call i64 @bar(i8 *%a, i8 *%b, i8 *%c, i8 *%d, i8 *%e, i64 0, i64 0)
   %res = add i64 %count, 1
   ret i64 %res
diff --git a/test/CodeGen/SystemZ/alloca-02.ll b/test/CodeGen/SystemZ/alloca-02.ll
index b5787b102358..092ad86e8529 100644
--- a/test/CodeGen/SystemZ/alloca-02.ll
+++ b/test/CodeGen/SystemZ/alloca-02.ll
@@ -38,13 +38,13 @@ define i64 @f1(i64 %length, i64 %index) {
 ; CHECK-E: stcy [[TMP]], 4096({{%r3,%r2|%r2,%r3}})
   %a = alloca i8, i64 %length
   store volatile i8 0, i8 *%a
-  %b = getelementptr i8 *%a, i64 4095
+  %b = getelementptr i8, i8 *%a, i64 4095
   store volatile i8 1, i8 *%b
-  %c = getelementptr i8 *%a, i64 %index
+  %c = getelementptr i8, i8 *%a, i64 %index
   store volatile i8 2, i8 *%c
-  %d = getelementptr i8 *%c, i64 4095
+  %d = getelementptr i8, i8 *%c, i64 4095
   store volatile i8 3, i8 *%d
-  %e = getelementptr i8 *%d, i64 1
+  %e = getelementptr i8, i8 *%d, i64 1
   store volatile i8 4, i8 *%e
   %count = call i64 @bar(i8 *%a)
   %res = add i64 %count, 1
diff --git a/test/CodeGen/SystemZ/and-01.ll b/test/CodeGen/SystemZ/and-01.ll
index 3b230ba1081f..56fe2799fdc0 100644
--- a/test/CodeGen/SystemZ/and-01.ll
+++ b/test/CodeGen/SystemZ/and-01.ll
@@ -19,7 +19,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: n %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %and = and i32 %a, %b
   ret i32 %and
 }
@@ -29,8 +29,8 @@ define i32 @f3(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: n %r2, 4092(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1023
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 1023
+  %b = load i32 , i32 *%ptr
   %and = and i32 %a, %b
   ret i32 %and
 }
@@ -40,8 +40,8 @@ define i32 @f4(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: ny %r2, 4096(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1024
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 1024
+  %b = load i32 , i32 *%ptr
   %and = and i32 %a, %b
   ret i32 %and
 }
@@ -51,8 +51,8 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: ny %r2, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %b = load i32 , i32 *%ptr
   %and = and i32 %a, %b
   ret i32 %and
 }
@@ -64,8 +64,8 @@ define i32 @f6(i32 %a, i32 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: n %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %b = load i32 , i32 *%ptr
   %and = and i32 %a, %b
   ret i32 %and
 }
@@ -75,8 +75,8 @@ define i32 @f7(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: ny %r2, -4(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %b = load i32 , i32 *%ptr
   %and = and i32 %a, %b
   ret i32 %and
 }
@@ -86,8 +86,8 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f8:
 ; CHECK: ny %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %b = load i32 , i32 *%ptr
   %and = and i32 %a, %b
   ret i32 %and
 }
@@ -99,8 +99,8 @@ define i32 @f9(i32 %a, i32 *%src) {
 ; CHECK: agfi %r3, -524292
 ; CHECK: n %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %b = load i32 , i32 *%ptr
   %and = and i32 %a, %b
   ret i32 %and
 }
@@ -113,7 +113,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4092
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %and = and i32 %a, %b
   ret i32 %and
 }
@@ -126,7 +126,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %and = and i32 %a, %b
   ret i32 %and
 }
@@ -137,26 +137,26 @@ define i32 @f12(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: n %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-  %ptr9 = getelementptr i32 *%ptr0, i64 18
-
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
-  %val9 = load i32 *%ptr9
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32, i32 *%ptr0, i64 18
+
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
+  %val9 = load i32 , i32 *%ptr9
 
   %ret = call i32 @foo()
 
diff --git a/test/CodeGen/SystemZ/and-03.ll b/test/CodeGen/SystemZ/and-03.ll
index a0560d46e4ea..5c15d2462b89 100644
--- a/test/CodeGen/SystemZ/and-03.ll
+++ b/test/CodeGen/SystemZ/and-03.ll
@@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: ng %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i64 *%src
+  %b = load i64 , i64 *%src
   %and = and i64 %a, %b
   ret i64 %and
 }
@@ -29,8 +29,8 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: ng %r2, 524280(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65535
+  %b = load i64 , i64 *%ptr
   %and = and i64 %a, %b
   ret i64 %and
 }
@@ -42,8 +42,8 @@ define i64 @f4(i64 %a, i64 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: ng %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65536
+  %b = load i64 , i64 *%ptr
   %and = and i64 %a, %b
   ret i64 %and
 }
@@ -53,8 +53,8 @@ define i64 @f5(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: ng %r2, -8(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -1
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -1
+  %b = load i64 , i64 *%ptr
   %and = and i64 %a, %b
   ret i64 %and
 }
@@ -64,8 +64,8 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: ng %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
+  %b = load i64 , i64 *%ptr
   %and = and i64 %a, %b
   ret i64 %and
 }
@@ -77,8 +77,8 @@ define i64 @f7(i64 %a, i64 *%src) {
 ; CHECK: agfi %r3, -524296
 ; CHECK: ng %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
+  %b = load i64 , i64 *%ptr
   %and = and i64 %a, %b
   ret i64 %and
 }
@@ -91,7 +91,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524280
   %ptr = inttoptr i64 %add2 to i64 *
-  %b = load i64 *%ptr
+  %b = load i64 , i64 *%ptr
   %and = and i64 %a, %b
   ret i64 %and
 }
@@ -102,26 +102,26 @@ define i64 @f9(i64 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: ng %r2, 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i64 *%ptr0, i64 2
-  %ptr2 = getelementptr i64 *%ptr0, i64 4
-  %ptr3 = getelementptr i64 *%ptr0, i64 6
-  %ptr4 = getelementptr i64 *%ptr0, i64 8
-  %ptr5 = getelementptr i64 *%ptr0, i64 10
-  %ptr6 = getelementptr i64 *%ptr0, i64 12
-  %ptr7 = getelementptr i64 *%ptr0, i64 14
-  %ptr8 = getelementptr i64 *%ptr0, i64 16
-  %ptr9 = getelementptr i64 *%ptr0, i64 18
+  %ptr1 = getelementptr i64, i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64, i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64, i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64, i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64, i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64, i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64, i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64, i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64, i64 *%ptr0, i64 18
 
-  %val0 = load i64 *%ptr0
-  %val1 = load i64 *%ptr1
-  %val2 = load i64 *%ptr2
-  %val3 = load i64 *%ptr3
-  %val4 = load i64 *%ptr4
-  %val5 = load i64 *%ptr5
-  %val6 = load i64 *%ptr6
-  %val7 = load i64 *%ptr7
-  %val8 = load i64 *%ptr8
-  %val9 = load i64 *%ptr9
+  %val0 = load i64 , i64 *%ptr0
+  %val1 = load i64 , i64 *%ptr1
+  %val2 = load i64 , i64 *%ptr2
+  %val3 = load i64 , i64 *%ptr3
+  %val4 = load i64 , i64 *%ptr4
+  %val5 = load i64 , i64 *%ptr5
+  %val6 = load i64 , i64 *%ptr6
+  %val7 = load i64 , i64 *%ptr7
+  %val8 = load i64 , i64 *%ptr8
+  %val9 = load i64 , i64 *%ptr9
 
   %ret = call i64 @foo()
 
diff --git a/test/CodeGen/SystemZ/and-05.ll b/test/CodeGen/SystemZ/and-05.ll
index dafd9d5c51b0..488ec5bc9ae6 100644
--- a/test/CodeGen/SystemZ/and-05.ll
+++ b/test/CodeGen/SystemZ/and-05.ll
@@ -7,7 +7,7 @@ define void @f1(i8 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: ni 0(%r2), 1
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %and = and i8 %val, -255
   store i8 %and, i8 *%ptr
   ret void
@@ -18,7 +18,7 @@ define void @f2(i8 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %and = and i8 %val, -2
   store i8 %and, i8 *%ptr
   ret void
@@ -29,7 +29,7 @@ define void @f3(i8 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: ni 0(%r2), 1
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %and = and i8 %val, 1
   store i8 %and, i8 *%ptr
   ret void
@@ -40,7 +40,7 @@ define void @f4(i8 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %and = and i8 %val, 254
   store i8 %and, i8 *%ptr
   ret void
@@ -51,8 +51,8 @@ define void @f5(i8 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: ni 4095(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4095
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 4095
+  %val = load i8 , i8 *%ptr
   %and = and i8 %val, 127
   store i8 %and, i8 *%ptr
   ret void
@@ -63,8 +63,8 @@ define void @f6(i8 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: niy 4096(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4096
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 4096
+  %val = load i8 , i8 *%ptr
   %and = and i8 %val, 127
   store i8 %and, i8 *%ptr
   ret void
@@ -75,8 +75,8 @@ define void @f7(i8 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: niy 524287(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524287
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524287
+  %val = load i8 , i8 *%ptr
   %and = and i8 %val, 127
   store i8 %and, i8 *%ptr
   ret void
@@ -89,8 +89,8 @@ define void @f8(i8 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: ni 0(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524288
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524288
+  %val = load i8 , i8 *%ptr
   %and = and i8 %val, 127
   store i8 %and, i8 *%ptr
   ret void
@@ -101,8 +101,8 @@ define void @f9(i8 *%src) {
 ; CHECK-LABEL: f9:
 ; CHECK: niy -1(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -1
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -1
+  %val = load i8 , i8 *%ptr
   %and = and i8 %val, 127
   store i8 %and, i8 *%ptr
   ret void
@@ -113,8 +113,8 @@ define void @f10(i8 *%src) {
 ; CHECK-LABEL: f10:
 ; CHECK: niy -524288(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524288
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524288
+  %val = load i8 , i8 *%ptr
   %and = and i8 %val, 127
   store i8 %and, i8 *%ptr
   ret void
@@ -127,8 +127,8 @@ define void @f11(i8 *%src) {
 ; CHECK: agfi %r2, -524289
 ; CHECK: ni 0(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524289
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524289
+  %val = load i8 , i8 *%ptr
   %and = and i8 %val, 127
   store i8 %and, i8 *%ptr
   ret void
@@ -143,7 +143,7 @@ define void @f12(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4095
   %ptr = inttoptr i64 %add2 to i8 *
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %and = and i8 %val, 127
   store i8 %and, i8 *%ptr
   ret void
@@ -158,7 +158,7 @@ define void @f13(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i8 *
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %and = and i8 %val, 127
   store i8 %and, i8 *%ptr
   ret void
diff --git a/test/CodeGen/SystemZ/and-06.ll b/test/CodeGen/SystemZ/and-06.ll
index f796618dd4f4..537ee100589a 100644
--- a/test/CodeGen/SystemZ/and-06.ll
+++ b/test/CodeGen/SystemZ/and-06.ll
@@ -8,7 +8,7 @@ define void @f1(i8 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %and = and i32 %ext, -2
   %trunc = trunc i32 %and to i8
@@ -21,7 +21,7 @@ define void @f2(i8 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %and = and i64 %ext, -2
   %trunc = trunc i64 %and to i8
@@ -34,7 +34,7 @@ define void @f3(i8 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %and = and i32 %ext, 254
   %trunc = trunc i32 %and to i8
@@ -47,7 +47,7 @@ define void @f4(i8 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %and = and i64 %ext, 254
   %trunc = trunc i64 %and to i8
@@ -60,7 +60,7 @@ define void @f5(i8 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %and = and i32 %ext, -2
   %trunc = trunc i32 %and to i8
@@ -73,7 +73,7 @@ define void @f6(i8 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %and = and i64 %ext, -2
   %trunc = trunc i64 %and to i8
@@ -86,7 +86,7 @@ define void @f7(i8 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %and = and i32 %ext, 254
   %trunc = trunc i32 %and to i8
@@ -99,7 +99,7 @@ define void @f8(i8 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %and = and i64 %ext, 254
   %trunc = trunc i64 %and to i8
diff --git a/test/CodeGen/SystemZ/and-08.ll b/test/CodeGen/SystemZ/and-08.ll
index a328c4ea2046..0622950243ed 100644
--- a/test/CodeGen/SystemZ/and-08.ll
+++ b/test/CodeGen/SystemZ/and-08.ll
@@ -12,9 +12,9 @@ define void @f1(i8 *%ptr1) {
 ; CHECK-LABEL: f1:
 ; CHECK: nc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i8 *%ptr1, i64 1
-  %val = load i8 *%ptr1
-  %old = load i8 *%ptr2
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 1
+  %val = load i8 , i8 *%ptr1
+  %old = load i8 , i8 *%ptr2
   %and = and i8 %val, %old
   store i8 %and, i8 *%ptr2
   ret void
@@ -25,9 +25,9 @@ define void @f2(i8 *%ptr1) {
 ; CHECK-LABEL: f2:
 ; CHECK: nc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i8 *%ptr1, i64 1
-  %val = load i8 *%ptr1
-  %old = load i8 *%ptr2
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 1
+  %val = load i8 , i8 *%ptr1
+  %old = load i8 , i8 *%ptr2
   %and = and i8 %old, %val
   store i8 %and, i8 *%ptr2
   ret void
@@ -39,10 +39,10 @@ define void @f3(i8 *%ptr1) {
 ; CHECK-LABEL: f3:
 ; CHECK: nc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i8 *%ptr1, i64 1
-  %val = load i8 *%ptr1
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 1
+  %val = load i8 , i8 *%ptr1
   %extval = zext i8 %val to i32
-  %old = load i8 *%ptr2
+  %old = load i8 , i8 *%ptr2
   %extold = sext i8 %old to i32
   %and = and i32 %extval, %extold
   %trunc = trunc i32 %and to i8
@@ -55,10 +55,10 @@ define void @f4(i8 *%ptr1) {
 ; CHECK-LABEL: f4:
 ; CHECK: nc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i8 *%ptr1, i64 1
-  %val = load i8 *%ptr1
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 1
+  %val = load i8 , i8 *%ptr1
   %extval = sext i8 %val to i32
-  %old = load i8 *%ptr2
+  %old = load i8 , i8 *%ptr2
   %extold = zext i8 %old to i32
   %and = and i32 %extval, %extold
   %trunc = trunc i32 %and to i8
@@ -71,10 +71,10 @@ define void @f5(i8 *%ptr1) {
 ; CHECK-LABEL: f5:
 ; CHECK: nc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i8 *%ptr1, i64 1
-  %val = load i8 *%ptr1
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 1
+  %val = load i8 , i8 *%ptr1
   %extval = sext i8 %val to i32
-  %old = load i8 *%ptr2
+  %old = load i8 , i8 *%ptr2
   %extold = sext i8 %old to i32
   %and = and i32 %extval, %extold
   %trunc = trunc i32 %and to i8
@@ -87,10 +87,10 @@ define void @f6(i8 *%ptr1) {
 ; CHECK-LABEL: f6:
 ; CHECK: nc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i8 *%ptr1, i64 1
-  %val = load i8 *%ptr1
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 1
+  %val = load i8 , i8 *%ptr1
   %extval = zext i8 %val to i32
-  %old = load i8 *%ptr2
+  %old = load i8 , i8 *%ptr2
   %extold = zext i8 %old to i32
   %and = and i32 %extval, %extold
   %trunc = trunc i32 %and to i8
@@ -104,10 +104,10 @@ define void @f7(i8 *%ptr1) {
 ; CHECK-LABEL: f7:
 ; CHECK: nc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i8 *%ptr1, i64 1
-  %val = load i8 *%ptr1
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 1
+  %val = load i8 , i8 *%ptr1
   %extval = sext i8 %val to i64
-  %old = load i8 *%ptr2
+  %old = load i8 , i8 *%ptr2
   %extold = zext i8 %old to i64
   %and = and i64 %extval, %extold
   %trunc = trunc i64 %and to i8
@@ -120,9 +120,9 @@ define void @f8(i16 *%ptr1) {
 ; CHECK-LABEL: f8:
 ; CHECK: nc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i16 *%ptr1, i64 1
-  %val = load i16 *%ptr1
-  %old = load i16 *%ptr2
+  %ptr2 = getelementptr i16, i16 *%ptr1, i64 1
+  %val = load i16 , i16 *%ptr1
+  %old = load i16 , i16 *%ptr2
   %and = and i16 %val, %old
   store i16 %and, i16 *%ptr2
   ret void
@@ -133,10 +133,10 @@ define void @f9(i16 *%ptr1) {
 ; CHECK-LABEL: f9:
 ; CHECK: nc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i16 *%ptr1, i64 1
-  %val = load i16 *%ptr1
+  %ptr2 = getelementptr i16, i16 *%ptr1, i64 1
+  %val = load i16 , i16 *%ptr1
   %extval = zext i16 %val to i32
-  %old = load i16 *%ptr2
+  %old = load i16 , i16 *%ptr2
   %extold = sext i16 %old to i32
   %and = and i32 %extval, %extold
   %trunc = trunc i32 %and to i16
@@ -149,10 +149,10 @@ define void @f10(i16 *%ptr1) {
 ; CHECK-LABEL: f10:
 ; CHECK: nc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i16 *%ptr1, i64 1
-  %val = load i16 *%ptr1
+  %ptr2 = getelementptr i16, i16 *%ptr1, i64 1
+  %val = load i16 , i16 *%ptr1
   %extval = sext i16 %val to i64
-  %old = load i16 *%ptr2
+  %old = load i16 , i16 *%ptr2
   %extold = zext i16 %old to i64
   %and = and i64 %extval, %extold
   %trunc = trunc i64 %and to i16
@@ -165,9 +165,9 @@ define void @f11(i32 *%ptr1) {
 ; CHECK-LABEL: f11:
 ; CHECK: nc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i32 *%ptr1, i64 1
-  %val = load i32 *%ptr1
-  %old = load i32 *%ptr2
+  %ptr2 = getelementptr i32, i32 *%ptr1, i64 1
+  %val = load i32 , i32 *%ptr1
+  %old = load i32 , i32 *%ptr2
   %and = and i32 %old, %val
   store i32 %and, i32 *%ptr2
   ret void
@@ -178,10 +178,10 @@ define void @f12(i32 *%ptr1) {
 ; CHECK-LABEL: f12:
 ; CHECK: nc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i32 *%ptr1, i64 1
-  %val = load i32 *%ptr1
+  %ptr2 = getelementptr i32, i32 *%ptr1, i64 1
+  %val = load i32 , i32 *%ptr1
   %extval = sext i32 %val to i64
-  %old = load i32 *%ptr2
+  %old = load i32 , i32 *%ptr2
   %extold = zext i32 %old to i64
   %and = and i64 %extval, %extold
   %trunc = trunc i64 %and to i32
@@ -194,9 +194,9 @@ define void @f13(i64 *%ptr1) {
 ; CHECK-LABEL: f13:
 ; CHECK: nc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i64 *%ptr1, i64 1
-  %val = load i64 *%ptr1
-  %old = load i64 *%ptr2
+  %ptr2 = getelementptr i64, i64 *%ptr1, i64 1
+  %val = load i64 , i64 *%ptr1
+  %old = load i64 , i64 *%ptr2
   %and = and i64 %old, %val
   store i64 %and, i64 *%ptr2
   ret void
@@ -207,9 +207,9 @@ define void @f14(i64 *%ptr1) {
 ; CHECK-LABEL: f14:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
-  %ptr2 = getelementptr i64 *%ptr1, i64 1
-  %val = load volatile i64 *%ptr1
-  %old = load i64 *%ptr2
+  %ptr2 = getelementptr i64, i64 *%ptr1, i64 1
+  %val = load volatile i64 , i64 *%ptr1
+  %old = load i64 , i64 *%ptr2
   %and = and i64 %old, %val
   store i64 %and, i64 *%ptr2
   ret void
@@ -220,9 +220,9 @@ define void @f15(i64 *%ptr1) {
 ; CHECK-LABEL: f15:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
-  %ptr2 = getelementptr i64 *%ptr1, i64 1
-  %val = load i64 *%ptr1
-  %old = load volatile i64 *%ptr2
+  %ptr2 = getelementptr i64, i64 *%ptr1, i64 1
+  %val = load i64 , i64 *%ptr1
+  %old = load volatile i64 , i64 *%ptr2
   %and = and i64 %old, %val
   store i64 %and, i64 *%ptr2
   ret void
@@ -233,9 +233,9 @@ define void @f16(i64 *%ptr1) {
 ; CHECK-LABEL: f16:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
-  %ptr2 = getelementptr i64 *%ptr1, i64 1
-  %val = load i64 *%ptr1
-  %old = load i64 *%ptr2
+  %ptr2 = getelementptr i64, i64 *%ptr1, i64 1
+  %val = load i64 , i64 *%ptr1
+  %old = load i64 , i64 *%ptr2
   %and = and i64 %old, %val
   store volatile i64 %and, i64 *%ptr2
   ret void
@@ -248,8 +248,8 @@ define void @f17(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f17:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
-  %val = load i64 *%ptr1
-  %old = load i64 *%ptr2
+  %val = load i64 , i64 *%ptr1
+  %old = load i64 , i64 *%ptr2
   %and = and i64 %old, %val
   store i64 %and, i64 *%ptr2
   ret void
@@ -260,8 +260,8 @@ define void @f18(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f18:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
-  %val = load i64 *%ptr1, align 2
-  %old = load i64 *%ptr2
+  %val = load i64 , i64 *%ptr1, align 2
+  %old = load i64 , i64 *%ptr2
   %and = and i64 %old, %val
   store i64 %and, i64 *%ptr2
   ret void
@@ -272,8 +272,8 @@ define void @f19(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f19:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
-  %val = load i64 *%ptr1, align 2
-  %old = load i64 *%ptr2
+  %val = load i64 , i64 *%ptr1, align 2
+  %old = load i64 , i64 *%ptr2
   %and = and i64 %val, %old
   store i64 %and, i64 *%ptr2
   ret void
@@ -284,8 +284,8 @@ define void @f20(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f20:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
-  %val = load i64 *%ptr1
-  %old = load i64 *%ptr2, align 2
+  %val = load i64 , i64 *%ptr1
+  %old = load i64 , i64 *%ptr2, align 2
   %and = and i64 %val, %old
   store i64 %and, i64 *%ptr2, align 2
   ret void
@@ -299,8 +299,8 @@ define void @f21(i64 %base) {
   %add = add i64 %base, 1
   %ptr1 = inttoptr i64 %base to i64 *
   %ptr2 = inttoptr i64 %add to i64 *
-  %val = load i64 *%ptr1
-  %old = load i64 *%ptr2, align 1
+  %val = load i64 , i64 *%ptr1
+  %old = load i64 , i64 *%ptr2, align 1
   %and = and i64 %old, %val
   store i64 %and, i64 *%ptr2, align 1
   ret void
@@ -313,8 +313,8 @@ define void @f22(i8 *%ptr) {
 ; CHECK-DAG: larl [[DST:%r[0-5]]], g1dst
 ; CHECK: nc 0(1,[[DST]]), 0([[SRC]])
 ; CHECK: br %r14
-  %val = load i8 *@g1src
-  %old = load i8 *@g1dst
+  %val = load i8 , i8 *@g1src
+  %old = load i8 , i8 *@g1dst
   %and = and i8 %val, %old
   store i8 %and, i8 *@g1dst
   ret void
@@ -327,8 +327,8 @@ define void @f23(i16 *%ptr) {
 ; CHECK-DAG: larl [[DST:%r[0-5]]], g2dst
 ; CHECK: nc 0(2,[[DST]]), 0([[SRC]])
 ; CHECK: br %r14
-  %val = load i16 *@g2src
-  %old = load i16 *@g2dst
+  %val = load i16 , i16 *@g2src
+  %old = load i16 , i16 *@g2dst
   %and = and i16 %val, %old
   store i16 %and, i16 *@g2dst
   ret void
@@ -339,9 +339,9 @@ define void @f24(i64 *%ptr1) {
 ; CHECK-LABEL: f24:
 ; CHECK: nc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i64 *%ptr1, i64 1
-  %val = load i64 *%ptr1, align 1
-  %old = load i64 *%ptr2, align 1
+  %ptr2 = getelementptr i64, i64 *%ptr1, i64 1
+  %val = load i64 , i64 *%ptr1, align 1
+  %old = load i64 , i64 *%ptr2, align 1
   %and = and i64 %old, %val
   store i64 %and, i64 *%ptr2, align 1
   ret void
@@ -352,8 +352,8 @@ define void @f25(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f25:
 ; CHECK: nc 0(8,%r3), 0(%r2)
 ; CHECK: br %r14
-  %val = load i64 *%ptr1, align 2, !tbaa !3
-  %old = load i64 *%ptr2, align 2, !tbaa !4
+  %val = load i64 , i64 *%ptr1, align 2, !tbaa !3
+  %old = load i64 , i64 *%ptr2, align 2, !tbaa !4
   %and = and i64 %old, %val
   store i64 %and, i64 *%ptr2, align 2, !tbaa !4
   ret void
@@ -364,8 +364,8 @@ define void @f26(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f26:
 ; CHECK-NOT: nc
 ; CHECK: br %r14
-  %val = load i64 *%ptr1, align 2, !tbaa !3
-  %old = load i64 *%ptr2, align 2, !tbaa !3
+  %val = load i64 , i64 *%ptr1, align 2, !tbaa !3
+  %old = load i64 , i64 *%ptr2, align 2, !tbaa !3
   %and = and i64 %old, %val
   store i64 %and, i64 *%ptr2, align 2, !tbaa !3
   ret void
diff --git a/test/CodeGen/SystemZ/asm-18.ll b/test/CodeGen/SystemZ/asm-18.ll
index 71e145a285ff..999984be88d4 100644
--- a/test/CodeGen/SystemZ/asm-18.ll
+++ b/test/CodeGen/SystemZ/asm-18.ll
@@ -16,12 +16,12 @@ define void @f1(i32 *%ptr1, i32 *%ptr2) {
 ; CHECK-DAG: stfh [[REG3]], 4096(%r2)
 ; CHECK-DAG: sty [[REG4]], 524284(%r3)
 ; CHECK: br %r14
-  %ptr3 = getelementptr i32 *%ptr1, i64 1024
-  %ptr4 = getelementptr i32 *%ptr2, i64 131071
-  %old1 = load i32 *%ptr1
-  %old2 = load i32 *%ptr2
-  %old3 = load i32 *%ptr3
-  %old4 = load i32 *%ptr4
+  %ptr3 = getelementptr i32, i32 *%ptr1, i64 1024
+  %ptr4 = getelementptr i32, i32 *%ptr2, i64 131071
+  %old1 = load i32 , i32 *%ptr1
+  %old2 = load i32 , i32 *%ptr2
+  %old3 = load i32 , i32 *%ptr3
+  %old4 = load i32 , i32 *%ptr4
   %res = call { i32, i32, i32, i32 } asm "blah $0, $1, $2, $3",
               "=h,=r,=h,=r,0,1,2,3"(i32 %old1, i32 %old2, i32 %old3, i32 %old4)
   %new1 = extractvalue { i32, i32, i32, i32 } %res, 0
@@ -60,12 +60,12 @@ define void @f3(i8 *%ptr1, i8 *%ptr2) {
 ; CHECK-DAG: lb [[REG4:%r[0-5]]], 524287(%r3)
 ; CHECK: blah [[REG1]], [[REG2]]
 ; CHECK: br %r14
-  %ptr3 = getelementptr i8 *%ptr1, i64 4096
-  %ptr4 = getelementptr i8 *%ptr2, i64 524287
-  %val1 = load i8 *%ptr1
-  %val2 = load i8 *%ptr2
-  %val3 = load i8 *%ptr3
-  %val4 = load i8 *%ptr4
+  %ptr3 = getelementptr i8, i8 *%ptr1, i64 4096
+  %ptr4 = getelementptr i8, i8 *%ptr2, i64 524287
+  %val1 = load i8 , i8 *%ptr1
+  %val2 = load i8 , i8 *%ptr2
+  %val3 = load i8 , i8 *%ptr3
+  %val4 = load i8 , i8 *%ptr4
   %ext1 = sext i8 %val1 to i32
   %ext2 = sext i8 %val2 to i32
   %ext3 = sext i8 %val3 to i32
@@ -84,12 +84,12 @@ define void @f4(i16 *%ptr1, i16 *%ptr2) {
 ; CHECK-DAG: lhy [[REG4:%r[0-5]]], 524286(%r3)
 ; CHECK: blah [[REG1]], [[REG2]]
 ; CHECK: br %r14
-  %ptr3 = getelementptr i16 *%ptr1, i64 2048
-  %ptr4 = getelementptr i16 *%ptr2, i64 262143
-  %val1 = load i16 *%ptr1
-  %val2 = load i16 *%ptr2
-  %val3 = load i16 *%ptr3
-  %val4 = load i16 *%ptr4
+  %ptr3 = getelementptr i16, i16 *%ptr1, i64 2048
+  %ptr4 = getelementptr i16, i16 *%ptr2, i64 262143
+  %val1 = load i16 , i16 *%ptr1
+  %val2 = load i16 , i16 *%ptr2
+  %val3 = load i16 , i16 *%ptr3
+  %val4 = load i16 , i16 *%ptr4
   %ext1 = sext i16 %val1 to i32
   %ext2 = sext i16 %val2 to i32
   %ext3 = sext i16 %val3 to i32
@@ -108,12 +108,12 @@ define void @f5(i8 *%ptr1, i8 *%ptr2) {
 ; CHECK-DAG: llc [[REG4:%r[0-5]]], 524287(%r3)
 ; CHECK: blah [[REG1]], [[REG2]]
 ; CHECK: br %r14
-  %ptr3 = getelementptr i8 *%ptr1, i64 4096
-  %ptr4 = getelementptr i8 *%ptr2, i64 524287
-  %val1 = load i8 *%ptr1
-  %val2 = load i8 *%ptr2
-  %val3 = load i8 *%ptr3
-  %val4 = load i8 *%ptr4
+  %ptr3 = getelementptr i8, i8 *%ptr1, i64 4096
+  %ptr4 = getelementptr i8, i8 *%ptr2, i64 524287
+  %val1 = load i8 , i8 *%ptr1
+  %val2 = load i8 , i8 *%ptr2
+  %val3 = load i8 , i8 *%ptr3
+  %val4 = load i8 , i8 *%ptr4
   %ext1 = zext i8 %val1 to i32
   %ext2 = zext i8 %val2 to i32
   %ext3 = zext i8 %val3 to i32
@@ -132,12 +132,12 @@ define void @f6(i16 *%ptr1, i16 *%ptr2) {
 ; CHECK-DAG: llh [[REG4:%r[0-5]]], 524286(%r3)
 ; CHECK: blah [[REG1]], [[REG2]]
 ; CHECK: br %r14
-  %ptr3 = getelementptr i16 *%ptr1, i64 2048
-  %ptr4 = getelementptr i16 *%ptr2, i64 262143
-  %val1 = load i16 *%ptr1
-  %val2 = load i16 *%ptr2
-  %val3 = load i16 *%ptr3
-  %val4 = load i16 *%ptr4
+  %ptr3 = getelementptr i16, i16 *%ptr1, i64 2048
+  %ptr4 = getelementptr i16, i16 *%ptr2, i64 262143
+  %val1 = load i16 , i16 *%ptr1
+  %val2 = load i16 , i16 *%ptr2
+  %val3 = load i16 , i16 *%ptr3
+  %val4 = load i16 , i16 *%ptr4
   %ext1 = zext i16 %val1 to i32
   %ext2 = zext i16 %val2 to i32
   %ext3 = zext i16 %val3 to i32
@@ -161,8 +161,8 @@ define void @f7(i8 *%ptr1, i8 *%ptr2) {
   %res2 = extractvalue { i32, i32 } %res, 1
   %trunc1 = trunc i32 %res1 to i8
   %trunc2 = trunc i32 %res2 to i8
-  %ptr3 = getelementptr i8 *%ptr1, i64 4096
-  %ptr4 = getelementptr i8 *%ptr2, i64 524287
+  %ptr3 = getelementptr i8, i8 *%ptr1, i64 4096
+  %ptr4 = getelementptr i8, i8 *%ptr2, i64 524287
   store i8 %trunc1, i8 *%ptr1
   store i8 %trunc2, i8 *%ptr2
   store i8 %trunc1, i8 *%ptr3
@@ -184,8 +184,8 @@ define void @f8(i16 *%ptr1, i16 *%ptr2) {
   %res2 = extractvalue { i32, i32 } %res, 1
   %trunc1 = trunc i32 %res1 to i16
   %trunc2 = trunc i32 %res2 to i16
-  %ptr3 = getelementptr i16 *%ptr1, i64 2048
-  %ptr4 = getelementptr i16 *%ptr2, i64 262143
+  %ptr3 = getelementptr i16, i16 *%ptr1, i64 2048
+  %ptr4 = getelementptr i16, i16 *%ptr2, i64 262143
   store i16 %trunc1, i16 *%ptr1
   store i16 %trunc2, i16 *%ptr2
   store i16 %trunc1, i16 *%ptr3
@@ -713,11 +713,11 @@ define void @f33(i32 *%ptr1, i32 *%ptr2) {
 ; CHECK: clhf [[REG2]], 0(%r3)
 ; CHECK: br %r14
   %res1 = call i32 asm "stepa $0", "=h"()
-  %load1 = load i32 *%ptr1
+  %load1 = load i32 , i32 *%ptr1
   %cmp1 = icmp sle i32 %res1, %load1
   %sel1 = select i1 %cmp1, i32 0, i32 1
   %res2 = call i32 asm "stepb $0, $1", "=h,r"(i32 %sel1)
-  %load2 = load i32 *%ptr2
+  %load2 = load i32 , i32 *%ptr2
   %cmp2 = icmp ule i32 %res2, %load2
   %sel2 = select i1 %cmp2, i32 0, i32 1
   store i32 %sel2, i32 *%ptr1
@@ -733,11 +733,11 @@ define void @f34(i32 *%ptr1, i32 *%ptr2) {
 ; CHECK: cl [[REG2]], 0(%r3)
 ; CHECK: br %r14
   %res1 = call i32 asm "stepa $0", "=r"()
-  %load1 = load i32 *%ptr1
+  %load1 = load i32 , i32 *%ptr1
   %cmp1 = icmp sle i32 %res1, %load1
   %sel1 = select i1 %cmp1, i32 0, i32 1
   %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %sel1)
-  %load2 = load i32 *%ptr2
+  %load2 = load i32 , i32 *%ptr2
   %cmp2 = icmp ule i32 %res2, %load2
   %sel2 = select i1 %cmp2, i32 0, i32 1
   store i32 %sel2, i32 *%ptr1
diff --git a/test/CodeGen/SystemZ/atomic-load-01.ll b/test/CodeGen/SystemZ/atomic-load-01.ll
index f3acd605b012..b2f4ebe6639e 100644
--- a/test/CodeGen/SystemZ/atomic-load-01.ll
+++ b/test/CodeGen/SystemZ/atomic-load-01.ll
@@ -7,6 +7,6 @@ define i8 @f1(i8 *%src) {
 ; CHECK: bcr 1{{[45]}}, %r0
 ; CHECK: lb %r2, 0(%r2)
 ; CHECK: br %r14
-  %val = load atomic i8 *%src seq_cst, align 1
+  %val = load atomic i8 , i8 *%src seq_cst, align 1
   ret i8 %val
 }
diff --git a/test/CodeGen/SystemZ/atomic-load-02.ll b/test/CodeGen/SystemZ/atomic-load-02.ll
index d9bec60f4c1b..b2b60f3d0160 100644
--- a/test/CodeGen/SystemZ/atomic-load-02.ll
+++ b/test/CodeGen/SystemZ/atomic-load-02.ll
@@ -7,6 +7,6 @@ define i16 @f1(i16 *%src) {
 ; CHECK: bcr 1{{[45]}}, %r0
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: br %r14
-  %val = load atomic i16 *%src seq_cst, align 2
+  %val = load atomic i16 , i16 *%src seq_cst, align 2
   ret i16 %val
 }
diff --git a/test/CodeGen/SystemZ/atomic-load-03.ll b/test/CodeGen/SystemZ/atomic-load-03.ll
index 7e5eb9249a93..d83c430bd0af 100644
--- a/test/CodeGen/SystemZ/atomic-load-03.ll
+++ b/test/CodeGen/SystemZ/atomic-load-03.ll
@@ -7,6 +7,6 @@ define i32 @f1(i32 *%src) {
 ; CHECK: bcr 1{{[45]}}, %r0
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: br %r14
-  %val = load atomic i32 *%src seq_cst, align 4
+  %val = load atomic i32 , i32 *%src seq_cst, align 4
   ret i32 %val
 }
diff --git a/test/CodeGen/SystemZ/atomic-load-04.ll b/test/CodeGen/SystemZ/atomic-load-04.ll
index c7a9a98a425d..dc6b271e00e5 100644
--- a/test/CodeGen/SystemZ/atomic-load-04.ll
+++ b/test/CodeGen/SystemZ/atomic-load-04.ll
@@ -7,6 +7,6 @@ define i64 @f1(i64 *%src) {
 ; CHECK: bcr 1{{[45]}}, %r0
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: br %r14
-  %val = load atomic i64 *%src seq_cst, align 8
+  %val = load atomic i64 , i64 *%src seq_cst, align 8
   ret i64 %val
 }
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-05.ll b/test/CodeGen/SystemZ/atomicrmw-add-05.ll
index 956c0d9642cd..f722f79bd42f 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-05.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-05.ll
@@ -26,7 +26,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f3:
 ; CHECK: laa %r2, %r4, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 131071
+  %ptr = getelementptr i32, i32 *%src, i32 131071
   %res = atomicrmw add i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -37,7 +37,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: laa %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 131072
+  %ptr = getelementptr i32, i32 *%src, i32 131072
   %res = atomicrmw add i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -47,7 +47,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f5:
 ; CHECK: laa %r2, %r4, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 -131072
+  %ptr = getelementptr i32, i32 *%src, i32 -131072
   %res = atomicrmw add i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -58,7 +58,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: agfi %r3, -524292
 ; CHECK: laa %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 -131073
+  %ptr = getelementptr i32, i32 *%src, i32 -131073
   %res = atomicrmw add i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-06.ll b/test/CodeGen/SystemZ/atomicrmw-add-06.ll
index f508858d1562..ef77dc018340 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-06.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-06.ll
@@ -26,7 +26,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f3:
 ; CHECK: laag %r2, %r4, 524280(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
+  %ptr = getelementptr i64, i64 *%src, i64 65535
   %res = atomicrmw add i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -37,7 +37,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: laag %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
+  %ptr = getelementptr i64, i64 *%src, i64 65536
   %res = atomicrmw add i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -47,7 +47,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f5:
 ; CHECK: laag %r2, %r4, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
   %res = atomicrmw add i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -58,7 +58,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: agfi %r3, -524296
 ; CHECK: laag %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
   %res = atomicrmw add i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-05.ll b/test/CodeGen/SystemZ/atomicrmw-and-05.ll
index f0b999c60431..b8ccbe2f4e50 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-05.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-05.ll
@@ -26,7 +26,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f3:
 ; CHECK: lan %r2, %r4, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 131071
+  %ptr = getelementptr i32, i32 *%src, i32 131071
   %res = atomicrmw and i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -37,7 +37,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: lan %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 131072
+  %ptr = getelementptr i32, i32 *%src, i32 131072
   %res = atomicrmw and i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -47,7 +47,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f5:
 ; CHECK: lan %r2, %r4, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 -131072
+  %ptr = getelementptr i32, i32 *%src, i32 -131072
   %res = atomicrmw and i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -58,7 +58,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: agfi %r3, -524292
 ; CHECK: lan %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 -131073
+  %ptr = getelementptr i32, i32 *%src, i32 -131073
   %res = atomicrmw and i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-06.ll b/test/CodeGen/SystemZ/atomicrmw-and-06.ll
index e5b71945d57c..9885cdec1f1f 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-06.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-06.ll
@@ -26,7 +26,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f3:
 ; CHECK: lang %r2, %r4, 524280(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
+  %ptr = getelementptr i64, i64 *%src, i64 65535
   %res = atomicrmw and i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -37,7 +37,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: lang %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
+  %ptr = getelementptr i64, i64 *%src, i64 65536
   %res = atomicrmw and i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -47,7 +47,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f5:
 ; CHECK: lang %r2, %r4, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
   %res = atomicrmw and i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -58,7 +58,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: agfi %r3, -524296
 ; CHECK: lang %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
   %res = atomicrmw and i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
index f2152c6f28bc..4ab48e46fc82 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
@@ -69,7 +69,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: l %r2, 4092(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1023
+  %ptr = getelementptr i32, i32 *%src, i64 1023
   %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -80,7 +80,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: ly %r2, 4096(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1024
+  %ptr = getelementptr i32, i32 *%src, i64 1024
   %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -91,7 +91,7 @@ define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: ly %r2, 524284(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
+  %ptr = getelementptr i32, i32 *%src, i64 131071
   %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -103,7 +103,7 @@ define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
+  %ptr = getelementptr i32, i32 *%src, i64 131072
   %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -114,7 +114,7 @@ define i32 @f9(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: ly %r2, -4(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
+  %ptr = getelementptr i32, i32 *%src, i64 -1
   %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -125,7 +125,7 @@ define i32 @f10(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: ly %r2, -524288(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
   %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -137,7 +137,7 @@ define i32 @f11(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
   %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
index 037eb1aa9367..afd88a3dd42d 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
@@ -69,7 +69,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lg %r2, 524280(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
+  %ptr = getelementptr i64, i64 *%src, i64 65535
   %res = atomicrmw min i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -81,7 +81,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
+  %ptr = getelementptr i64, i64 *%src, i64 65536
   %res = atomicrmw min i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -92,7 +92,7 @@ define i64 @f7(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lg %r2, -524288(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
   %res = atomicrmw min i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -104,7 +104,7 @@ define i64 @f8(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
   %res = atomicrmw min i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-05.ll b/test/CodeGen/SystemZ/atomicrmw-or-05.ll
index b38654ca6f07..54b5be431473 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-05.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-05.ll
@@ -26,7 +26,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f3:
 ; CHECK: lao %r2, %r4, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 131071
+  %ptr = getelementptr i32, i32 *%src, i32 131071
   %res = atomicrmw or i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -37,7 +37,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: lao %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 131072
+  %ptr = getelementptr i32, i32 *%src, i32 131072
   %res = atomicrmw or i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -47,7 +47,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f5:
 ; CHECK: lao %r2, %r4, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 -131072
+  %ptr = getelementptr i32, i32 *%src, i32 -131072
   %res = atomicrmw or i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -58,7 +58,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: agfi %r3, -524292
 ; CHECK: lao %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 -131073
+  %ptr = getelementptr i32, i32 *%src, i32 -131073
   %res = atomicrmw or i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-06.ll b/test/CodeGen/SystemZ/atomicrmw-or-06.ll
index 30874abfe4a2..3f7a05c7324d 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-06.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-06.ll
@@ -26,7 +26,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f3:
 ; CHECK: laog %r2, %r4, 524280(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
+  %ptr = getelementptr i64, i64 *%src, i64 65535
   %res = atomicrmw or i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -37,7 +37,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: laog %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
+  %ptr = getelementptr i64, i64 *%src, i64 65536
   %res = atomicrmw or i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -47,7 +47,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f5:
 ; CHECK: laog %r2, %r4, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
   %res = atomicrmw or i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -58,7 +58,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: agfi %r3, -524296
 ; CHECK: laog %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
   %res = atomicrmw or i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-05.ll b/test/CodeGen/SystemZ/atomicrmw-sub-05.ll
index 7668f0e2a7ac..e505f373ac73 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-05.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-05.ll
@@ -28,7 +28,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: lcr [[NEG:%r[0-5]]], %r4
 ; CHECK: laa %r2, [[NEG]], 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 131071
+  %ptr = getelementptr i32, i32 *%src, i32 131071
   %res = atomicrmw sub i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -40,7 +40,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-DAG: agfi %r3, 524288
 ; CHECK: laa %r2, [[NEG]], 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 131072
+  %ptr = getelementptr i32, i32 *%src, i32 131072
   %res = atomicrmw sub i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -51,7 +51,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: lcr [[NEG:%r[0-5]]], %r4
 ; CHECK: laa %r2, [[NEG]], -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 -131072
+  %ptr = getelementptr i32, i32 *%src, i32 -131072
   %res = atomicrmw sub i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -63,7 +63,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-DAG: agfi %r3, -524292
 ; CHECK: laa %r2, [[NEG]], 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 -131073
+  %ptr = getelementptr i32, i32 *%src, i32 -131073
   %res = atomicrmw sub i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-06.ll b/test/CodeGen/SystemZ/atomicrmw-sub-06.ll
index 5d11bdf96cde..7330cfa5aef3 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-06.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-06.ll
@@ -28,7 +28,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lcgr [[NEG:%r[0-5]]], %r4
 ; CHECK: laag %r2, [[NEG]], 524280(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
+  %ptr = getelementptr i64, i64 *%src, i64 65535
   %res = atomicrmw sub i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -40,7 +40,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-DAG: agfi %r3, 524288
 ; CHECK: laag %r2, [[NEG]], 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
+  %ptr = getelementptr i64, i64 *%src, i64 65536
   %res = atomicrmw sub i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -51,7 +51,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lcgr [[NEG:%r[0-5]]], %r4
 ; CHECK: laag %r2, [[NEG]], -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
   %res = atomicrmw sub i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -63,7 +63,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-DAG: agfi %r3, -524296
 ; CHECK: laag %r2, [[NEG]], 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
   %res = atomicrmw sub i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
index a602a02a189e..0e49a9f1ede7 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
@@ -20,7 +20,7 @@ define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: l %r2, 4092(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1023
+  %ptr = getelementptr i32, i32 *%src, i64 1023
   %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -31,7 +31,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: ly %r2, 4096(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1024
+  %ptr = getelementptr i32, i32 *%src, i64 1024
   %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -42,7 +42,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: ly %r2, 524284(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
+  %ptr = getelementptr i32, i32 *%src, i64 131071
   %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -54,7 +54,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
+  %ptr = getelementptr i32, i32 *%src, i64 131072
   %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -65,7 +65,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: ly %r2, -4(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
+  %ptr = getelementptr i32, i32 *%src, i64 -1
   %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -76,7 +76,7 @@ define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: ly %r2, -524288(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
   %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -88,7 +88,7 @@ define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
   %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
index 80c0eeb7121b..7afc50e238fc 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
@@ -20,7 +20,7 @@ define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lg %r2, 524280(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
+  %ptr = getelementptr i64, i64 *%src, i64 65535
   %res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -32,7 +32,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
+  %ptr = getelementptr i64, i64 *%src, i64 65536
   %res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -43,7 +43,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lg %r2, -524288(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
   %res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -55,7 +55,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
   %res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-05.ll b/test/CodeGen/SystemZ/atomicrmw-xor-05.ll
index e9e7d30b3578..e821f7ee8ae4 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-05.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-05.ll
@@ -26,7 +26,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f3:
 ; CHECK: lax %r2, %r4, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 131071
+  %ptr = getelementptr i32, i32 *%src, i32 131071
   %res = atomicrmw xor i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -37,7 +37,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: lax %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 131072
+  %ptr = getelementptr i32, i32 *%src, i32 131072
   %res = atomicrmw xor i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -47,7 +47,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f5:
 ; CHECK: lax %r2, %r4, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 -131072
+  %ptr = getelementptr i32, i32 *%src, i32 -131072
   %res = atomicrmw xor i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
@@ -58,7 +58,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: agfi %r3, -524292
 ; CHECK: lax %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i32 -131073
+  %ptr = getelementptr i32, i32 *%src, i32 -131073
   %res = atomicrmw xor i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-06.ll b/test/CodeGen/SystemZ/atomicrmw-xor-06.ll
index 0870c6476f61..630ff6a60977 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-06.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-06.ll
@@ -26,7 +26,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f3:
 ; CHECK: laxg %r2, %r4, 524280(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
+  %ptr = getelementptr i64, i64 *%src, i64 65535
   %res = atomicrmw xor i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -37,7 +37,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: laxg %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
+  %ptr = getelementptr i64, i64 *%src, i64 65536
   %res = atomicrmw xor i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -47,7 +47,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f5:
 ; CHECK: laxg %r2, %r4, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
   %res = atomicrmw xor i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
@@ -58,7 +58,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: agfi %r3, -524296
 ; CHECK: laxg %r2, %r4, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
   %res = atomicrmw xor i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
diff --git a/test/CodeGen/SystemZ/branch-02.ll b/test/CodeGen/SystemZ/branch-02.ll
index 38b5d27049d8..5a30cad66918 100644
--- a/test/CodeGen/SystemZ/branch-02.ll
+++ b/test/CodeGen/SystemZ/branch-02.ll
@@ -12,7 +12,7 @@ define void @f1(i32 *%src, i32 %target) {
 ; CHECK-NEXT: je .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile i32 *%src
+  %val = load volatile i32 , i32 *%src
   %cond = icmp eq i32 %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -27,7 +27,7 @@ define void @f2(i32 *%src, i32 %target) {
 ; CHECK-NEXT: jlh .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile i32 *%src
+  %val = load volatile i32 , i32 *%src
   %cond = icmp ne i32 %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -42,7 +42,7 @@ define void @f3(i32 *%src, i32 %target) {
 ; CHECK-NEXT: jle .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile i32 *%src
+  %val = load volatile i32 , i32 *%src
   %cond = icmp sle i32 %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -57,7 +57,7 @@ define void @f4(i32 *%src, i32 %target) {
 ; CHECK-NEXT: jl .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile i32 *%src
+  %val = load volatile i32 , i32 *%src
   %cond = icmp slt i32 %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -72,7 +72,7 @@ define void @f5(i32 *%src, i32 %target) {
 ; CHECK-NEXT: jh .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile i32 *%src
+  %val = load volatile i32 , i32 *%src
   %cond = icmp sgt i32 %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -87,7 +87,7 @@ define void @f6(i32 *%src, i32 %target) {
 ; CHECK-NEXT: jhe .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile i32 *%src
+  %val = load volatile i32 , i32 *%src
   %cond = icmp sge i32 %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
diff --git a/test/CodeGen/SystemZ/branch-03.ll b/test/CodeGen/SystemZ/branch-03.ll
index ef31a9c696ea..a258e850ea3e 100644
--- a/test/CodeGen/SystemZ/branch-03.ll
+++ b/test/CodeGen/SystemZ/branch-03.ll
@@ -10,7 +10,7 @@ define void @f1(i32 *%src, i32 %target) {
 ; CHECK-NEXT: jle .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile i32 *%src
+  %val = load volatile i32 , i32 *%src
   %cond = icmp ule i32 %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -25,7 +25,7 @@ define void @f2(i32 *%src, i32 %target) {
 ; CHECK-NEXT: jl .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile i32 *%src
+  %val = load volatile i32 , i32 *%src
   %cond = icmp ult i32 %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -40,7 +40,7 @@ define void @f3(i32 *%src, i32 %target) {
 ; CHECK-NEXT: jh .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile i32 *%src
+  %val = load volatile i32 , i32 *%src
   %cond = icmp ugt i32 %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -55,7 +55,7 @@ define void @f4(i32 *%src, i32 %target) {
 ; CHECK-NEXT: jhe .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile i32 *%src
+  %val = load volatile i32 , i32 *%src
   %cond = icmp uge i32 %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
diff --git a/test/CodeGen/SystemZ/branch-04.ll b/test/CodeGen/SystemZ/branch-04.ll
index fafb234616f1..8df2ca029f5f 100644
--- a/test/CodeGen/SystemZ/branch-04.ll
+++ b/test/CodeGen/SystemZ/branch-04.ll
@@ -11,7 +11,7 @@ define void @f1(float *%src, float %target) {
 ; CHECK-NEXT: je .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile float *%src
+  %val = load volatile float , float *%src
   %cond = fcmp oeq float %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -26,7 +26,7 @@ define void @f2(float *%src, float %target) {
 ; CHECK-NEXT: jlh .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile float *%src
+  %val = load volatile float , float *%src
   %cond = fcmp one float %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -41,7 +41,7 @@ define void @f3(float *%src, float %target) {
 ; CHECK-NEXT: jle .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile float *%src
+  %val = load volatile float , float *%src
   %cond = fcmp ole float %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -56,7 +56,7 @@ define void @f4(float *%src, float %target) {
 ; CHECK-NEXT: jl .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile float *%src
+  %val = load volatile float , float *%src
   %cond = fcmp olt float %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -71,7 +71,7 @@ define void @f5(float *%src, float %target) {
 ; CHECK-NEXT: jh .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile float *%src
+  %val = load volatile float , float *%src
   %cond = fcmp ogt float %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -86,7 +86,7 @@ define void @f6(float *%src, float %target) {
 ; CHECK-NEXT: jhe .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile float *%src
+  %val = load volatile float , float *%src
   %cond = fcmp oge float %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -101,7 +101,7 @@ define void @f7(float *%src, float %target) {
 ; CHECK-NEXT: jnlh .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile float *%src
+  %val = load volatile float , float *%src
   %cond = fcmp ueq float %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -116,7 +116,7 @@ define void @f8(float *%src, float %target) {
 ; CHECK-NEXT: jne .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile float *%src
+  %val = load volatile float , float *%src
   %cond = fcmp une float %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -131,7 +131,7 @@ define void @f9(float *%src, float %target) {
 ; CHECK-NEXT: jnh .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile float *%src
+  %val = load volatile float , float *%src
   %cond = fcmp ule float %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -146,7 +146,7 @@ define void @f10(float *%src, float %target) {
 ; CHECK-NEXT: jnhe .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile float *%src
+  %val = load volatile float , float *%src
   %cond = fcmp ult float %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -161,7 +161,7 @@ define void @f11(float *%src, float %target) {
 ; CHECK-NEXT: jnle .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile float *%src
+  %val = load volatile float , float *%src
   %cond = fcmp ugt float %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -176,7 +176,7 @@ define void @f12(float *%src, float %target) {
 ; CHECK-NEXT: jnl .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile float *%src
+  %val = load volatile float , float *%src
   %cond = fcmp uge float %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -193,7 +193,7 @@ define void @f13(float *%src, float %target) {
 ; CHECK-NEXT: jno .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile float *%src
+  %val = load volatile float , float *%src
   %cond = fcmp ord float %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
@@ -210,7 +210,7 @@ define void @f14(float *%src, float %target) {
 ; CHECK-NEXT: jo .L[[LABEL]]
   br label %loop
 loop:
-  %val = load volatile float *%src
+  %val = load volatile float , float *%src
   %cond = fcmp uno float %target, %val
   br i1 %cond, label %loop, label %exit
 exit:
diff --git a/test/CodeGen/SystemZ/branch-06.ll b/test/CodeGen/SystemZ/branch-06.ll
index 2fa23b744afb..4549b1295cf8 100644
--- a/test/CodeGen/SystemZ/branch-06.ll
+++ b/test/CodeGen/SystemZ/branch-06.ll
@@ -100,7 +100,7 @@ define void @f7(i8 *%targetptr) {
   br label %loop
 loop:
   %val = call i32 @foo()
-  %byte = load i8 *%targetptr
+  %byte = load i8 , i8 *%targetptr
   %target = zext i8 %byte to i32
   %cond = icmp eq i32 %val, %target
   br i1 %cond, label %loop, label %exit
@@ -118,7 +118,7 @@ define void @f8(i16 *%targetptr) {
   br label %loop
 loop:
   %val = call i32 @foo()
-  %half = load i16 *%targetptr
+  %half = load i16 , i16 *%targetptr
   %target = zext i16 %half to i32
   %cond = icmp eq i32 %val, %target
   br i1 %cond, label %loop, label %exit
@@ -136,7 +136,7 @@ define void @f9(i16 *%targetptr) {
   br label %loop
 loop:
   %val = call i32 @foo()
-  %half = load i16 *@g1
+  %half = load i16 , i16 *@g1
   %target = zext i16 %half to i32
   %cond = icmp eq i32 %val, %target
   br i1 %cond, label %loop, label %exit
@@ -156,9 +156,9 @@ define void @f10(i8 *%targetptr1) {
   br label %loop
 loop:
   %val = call i32 @foo()
-  %targetptr2 = getelementptr i8 *%targetptr1, i64 1
-  %byte1 = load i8 *%targetptr1
-  %byte2 = load i8 *%targetptr2
+  %targetptr2 = getelementptr i8, i8 *%targetptr1, i64 1
+  %byte1 = load i8 , i8 *%targetptr1
+  %byte2 = load i8 , i8 *%targetptr2
   %ext1 = zext i8 %byte1 to i32
   %ext2 = zext i8 %byte2 to i32
   %cond = icmp ult i32 %ext1, %ext2
@@ -178,9 +178,9 @@ define void @f11(i16 *%targetptr1) {
   br label %loop
 loop:
   %val = call i32 @foo()
-  %targetptr2 = getelementptr i16 *%targetptr1, i64 1
-  %half1 = load i16 *%targetptr1
-  %half2 = load i16 *%targetptr2
+  %targetptr2 = getelementptr i16, i16 *%targetptr1, i64 1
+  %half1 = load i16 , i16 *%targetptr1
+  %half2 = load i16 , i16 *%targetptr2
   %ext1 = zext i16 %half1 to i32
   %ext2 = zext i16 %half2 to i32
   %cond = icmp ult i32 %ext1, %ext2
diff --git a/test/CodeGen/SystemZ/branch-08.ll b/test/CodeGen/SystemZ/branch-08.ll
index 6741d29aec03..0aa48063d071 100644
--- a/test/CodeGen/SystemZ/branch-08.ll
+++ b/test/CodeGen/SystemZ/branch-08.ll
@@ -14,7 +14,7 @@ define i32 @f1(i32 %a, i32 *%bptr) {
 ; CHECK: .L[[LABEL]]:
 ; CHECK: brasl %r14, foo@PLT
 entry:
-  %b = load i32 *%bptr
+  %b = load i32 , i32 *%bptr
   %cmp = icmp ult i32 %a, %b
   br i1 %cmp, label %callit, label %return
 
diff --git a/test/CodeGen/SystemZ/bswap-02.ll b/test/CodeGen/SystemZ/bswap-02.ll
index db69ea53dfe1..9c964569dfd5 100644
--- a/test/CodeGen/SystemZ/bswap-02.ll
+++ b/test/CodeGen/SystemZ/bswap-02.ll
@@ -9,7 +9,7 @@ define i32 @f1(i32 *%src) {
 ; CHECK-LABEL: f1:
 ; CHECK: lrv %r2, 0(%r2)
 ; CHECK: br %r14
-  %a = load i32 *%src
+  %a = load i32 , i32 *%src
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %swapped
 }
@@ -19,8 +19,8 @@ define i32 @f2(i32 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: lrv %r2, 524284(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %a = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %a = load i32 , i32 *%ptr
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %swapped
 }
@@ -32,8 +32,8 @@ define i32 @f3(i32 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: lrv %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %a = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %a = load i32 , i32 *%ptr
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %swapped
 }
@@ -43,8 +43,8 @@ define i32 @f4(i32 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: lrv %r2, -4(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %a = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %a = load i32 , i32 *%ptr
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %swapped
 }
@@ -54,8 +54,8 @@ define i32 @f5(i32 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: lrv %r2, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %a = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %a = load i32 , i32 *%ptr
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %swapped
 }
@@ -67,8 +67,8 @@ define i32 @f6(i32 *%src) {
 ; CHECK: agfi %r2, -524292
 ; CHECK: lrv %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %a = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %a = load i32 , i32 *%ptr
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %swapped
 }
@@ -81,7 +81,7 @@ define i32 @f7(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i32 *
-  %a = load i32 *%ptr
+  %a = load i32 , i32 *%ptr
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %swapped
 }
@@ -93,7 +93,7 @@ define i32 @f8(i32 *%src) {
 ; CHECK: l [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: lrvr %r2, [[REG]]
 ; CHECK: br %r14
-  %a = load volatile i32 *%src
+  %a = load volatile i32 , i32 *%src
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %swapped
 }
@@ -104,22 +104,22 @@ define void @f9(i32 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: lrv {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile i32 *%ptr
-  %val1 = load volatile i32 *%ptr
-  %val2 = load volatile i32 *%ptr
-  %val3 = load volatile i32 *%ptr
-  %val4 = load volatile i32 *%ptr
-  %val5 = load volatile i32 *%ptr
-  %val6 = load volatile i32 *%ptr
-  %val7 = load volatile i32 *%ptr
-  %val8 = load volatile i32 *%ptr
-  %val9 = load volatile i32 *%ptr
-  %val10 = load volatile i32 *%ptr
-  %val11 = load volatile i32 *%ptr
-  %val12 = load volatile i32 *%ptr
-  %val13 = load volatile i32 *%ptr
-  %val14 = load volatile i32 *%ptr
-  %val15 = load volatile i32 *%ptr
+  %val0 = load volatile i32 , i32 *%ptr
+  %val1 = load volatile i32 , i32 *%ptr
+  %val2 = load volatile i32 , i32 *%ptr
+  %val3 = load volatile i32 , i32 *%ptr
+  %val4 = load volatile i32 , i32 *%ptr
+  %val5 = load volatile i32 , i32 *%ptr
+  %val6 = load volatile i32 , i32 *%ptr
+  %val7 = load volatile i32 , i32 *%ptr
+  %val8 = load volatile i32 , i32 *%ptr
+  %val9 = load volatile i32 , i32 *%ptr
+  %val10 = load volatile i32 , i32 *%ptr
+  %val11 = load volatile i32 , i32 *%ptr
+  %val12 = load volatile i32 , i32 *%ptr
+  %val13 = load volatile i32 , i32 *%ptr
+  %val14 = load volatile i32 , i32 *%ptr
+  %val15 = load volatile i32 , i32 *%ptr
 
   %swapped0 = call i32 @llvm.bswap.i32(i32 %val0)
   %swapped1 = call i32 @llvm.bswap.i32(i32 %val1)
diff --git a/test/CodeGen/SystemZ/bswap-03.ll b/test/CodeGen/SystemZ/bswap-03.ll
index d9e5ad1b52f6..ea62c4f71df6 100644
--- a/test/CodeGen/SystemZ/bswap-03.ll
+++ b/test/CodeGen/SystemZ/bswap-03.ll
@@ -9,7 +9,7 @@ define i64 @f1(i64 *%src) {
 ; CHECK-LABEL: f1:
 ; CHECK: lrvg %r2, 0(%r2)
 ; CHECK: br %r14
-  %a = load i64 *%src
+  %a = load i64 , i64 *%src
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %swapped
 }
@@ -19,8 +19,8 @@ define i64 @f2(i64 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: lrvg %r2, 524280(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
-  %a = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65535
+  %a = load i64 , i64 *%ptr
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %swapped
 }
@@ -32,8 +32,8 @@ define i64 @f3(i64 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: lrvg %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
-  %a = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65536
+  %a = load i64 , i64 *%ptr
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %swapped
 }
@@ -43,8 +43,8 @@ define i64 @f4(i64 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: lrvg %r2, -8(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -1
-  %a = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -1
+  %a = load i64 , i64 *%ptr
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %swapped
 }
@@ -54,8 +54,8 @@ define i64 @f5(i64 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: lrvg %r2, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
-  %a = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
+  %a = load i64 , i64 *%ptr
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %swapped
 }
@@ -67,8 +67,8 @@ define i64 @f6(i64 *%src) {
 ; CHECK: agfi %r2, -524296
 ; CHECK: lrvg %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
-  %a = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
+  %a = load i64 , i64 *%ptr
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %swapped
 }
@@ -81,7 +81,7 @@ define i64 @f7(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i64 *
-  %a = load i64 *%ptr
+  %a = load i64 , i64 *%ptr
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %swapped
 }
@@ -93,7 +93,7 @@ define i64 @f8(i64 *%src) {
 ; CHECK: lg [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: lrvgr %r2, [[REG]]
 ; CHECK: br %r14
-  %a = load volatile i64 *%src
+  %a = load volatile i64 , i64 *%src
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %swapped
 }
@@ -104,22 +104,22 @@ define void @f9(i64 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: lrvg {{%r[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile i64 *%ptr
-  %val1 = load volatile i64 *%ptr
-  %val2 = load volatile i64 *%ptr
-  %val3 = load volatile i64 *%ptr
-  %val4 = load volatile i64 *%ptr
-  %val5 = load volatile i64 *%ptr
-  %val6 = load volatile i64 *%ptr
-  %val7 = load volatile i64 *%ptr
-  %val8 = load volatile i64 *%ptr
-  %val9 = load volatile i64 *%ptr
-  %val10 = load volatile i64 *%ptr
-  %val11 = load volatile i64 *%ptr
-  %val12 = load volatile i64 *%ptr
-  %val13 = load volatile i64 *%ptr
-  %val14 = load volatile i64 *%ptr
-  %val15 = load volatile i64 *%ptr
+  %val0 = load volatile i64 , i64 *%ptr
+  %val1 = load volatile i64 , i64 *%ptr
+  %val2 = load volatile i64 , i64 *%ptr
+  %val3 = load volatile i64 , i64 *%ptr
+  %val4 = load volatile i64 , i64 *%ptr
+  %val5 = load volatile i64 , i64 *%ptr
+  %val6 = load volatile i64 , i64 *%ptr
+  %val7 = load volatile i64 , i64 *%ptr
+  %val8 = load volatile i64 , i64 *%ptr
+  %val9 = load volatile i64 , i64 *%ptr
+  %val10 = load volatile i64 , i64 *%ptr
+  %val11 = load volatile i64 , i64 *%ptr
+  %val12 = load volatile i64 , i64 *%ptr
+  %val13 = load volatile i64 , i64 *%ptr
+  %val14 = load volatile i64 , i64 *%ptr
+  %val15 = load volatile i64 , i64 *%ptr
 
   %swapped0 = call i64 @llvm.bswap.i64(i64 %val0)
   %swapped1 = call i64 @llvm.bswap.i64(i64 %val1)
diff --git a/test/CodeGen/SystemZ/bswap-04.ll b/test/CodeGen/SystemZ/bswap-04.ll
index 29d5a7b07212..ce4395210f1f 100644
--- a/test/CodeGen/SystemZ/bswap-04.ll
+++ b/test/CodeGen/SystemZ/bswap-04.ll
@@ -19,7 +19,7 @@ define void @f2(i32 *%dst, i32 %a) {
 ; CHECK-LABEL: f2:
 ; CHECK: strv %r3, 524284(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%dst, i64 131071
+  %ptr = getelementptr i32, i32 *%dst, i64 131071
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
   store i32 %swapped, i32 *%ptr
   ret void
@@ -32,7 +32,7 @@ define void @f3(i32 *%dst, i32 %a) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: strv %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%dst, i64 131072
+  %ptr = getelementptr i32, i32 *%dst, i64 131072
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
   store i32 %swapped, i32 *%ptr
   ret void
@@ -43,7 +43,7 @@ define void @f4(i32 *%dst, i32 %a) {
 ; CHECK-LABEL: f4:
 ; CHECK: strv %r3, -4(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%dst, i64 -1
+  %ptr = getelementptr i32, i32 *%dst, i64 -1
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
   store i32 %swapped, i32 *%ptr
   ret void
@@ -54,7 +54,7 @@ define void @f5(i32 *%dst, i32 %a) {
 ; CHECK-LABEL: f5:
 ; CHECK: strv %r3, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%dst, i64 -131072
+  %ptr = getelementptr i32, i32 *%dst, i64 -131072
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
   store i32 %swapped, i32 *%ptr
   ret void
@@ -67,7 +67,7 @@ define void @f6(i32 *%dst, i32 %a) {
 ; CHECK: agfi %r2, -524292
 ; CHECK: strv %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%dst, i64 -131073
+  %ptr = getelementptr i32, i32 *%dst, i64 -131073
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
   store i32 %swapped, i32 *%ptr
   ret void
diff --git a/test/CodeGen/SystemZ/bswap-05.ll b/test/CodeGen/SystemZ/bswap-05.ll
index 5c8361e26cea..5f90ef3b9b65 100644
--- a/test/CodeGen/SystemZ/bswap-05.ll
+++ b/test/CodeGen/SystemZ/bswap-05.ll
@@ -19,7 +19,7 @@ define void @f2(i64 *%dst, i64 %a) {
 ; CHECK-LABEL: f2:
 ; CHECK: strvg %r3, 524280(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%dst, i64 65535
+  %ptr = getelementptr i64, i64 *%dst, i64 65535
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   store i64 %swapped, i64 *%ptr
   ret void
@@ -32,7 +32,7 @@ define void @f3(i64 *%dst, i64 %a) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: strvg %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%dst, i64 65536
+  %ptr = getelementptr i64, i64 *%dst, i64 65536
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   store i64 %swapped, i64 *%ptr
   ret void
@@ -43,7 +43,7 @@ define void @f4(i64 *%dst, i64 %a) {
 ; CHECK-LABEL: f4:
 ; CHECK: strvg %r3, -8(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%dst, i64 -1
+  %ptr = getelementptr i64, i64 *%dst, i64 -1
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   store i64 %swapped, i64 *%ptr
   ret void
@@ -54,7 +54,7 @@ define void @f5(i64 *%dst, i64 %a) {
 ; CHECK-LABEL: f5:
 ; CHECK: strvg %r3, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%dst, i64 -65536
+  %ptr = getelementptr i64, i64 *%dst, i64 -65536
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   store i64 %swapped, i64 *%ptr
   ret void
@@ -67,7 +67,7 @@ define void @f6(i64 *%dst, i64 %a) {
 ; CHECK: agfi %r2, -524296
 ; CHECK: strvg %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%dst, i64 -65537
+  %ptr = getelementptr i64, i64 *%dst, i64 -65537
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   store i64 %swapped, i64 *%ptr
   ret void
diff --git a/test/CodeGen/SystemZ/cmpxchg-03.ll b/test/CodeGen/SystemZ/cmpxchg-03.ll
index c5fab4dc0439..c6e1955a50fd 100644
--- a/test/CodeGen/SystemZ/cmpxchg-03.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-03.ll
@@ -17,7 +17,7 @@ define i32 @f2(i32 %cmp, i32 %swap, i32 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: cs %r2, %r3, 4092(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1023
+  %ptr = getelementptr i32, i32 *%src, i64 1023
   %pair = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst seq_cst
   %val = extractvalue { i32, i1 } %pair, 0
   ret i32 %val
@@ -28,7 +28,7 @@ define i32 @f3(i32 %cmp, i32 %swap, i32 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: csy %r2, %r3, 4096(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1024
+  %ptr = getelementptr i32, i32 *%src, i64 1024
   %pair = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst seq_cst
   %val = extractvalue { i32, i1 } %pair, 0
   ret i32 %val
@@ -39,7 +39,7 @@ define i32 @f4(i32 %cmp, i32 %swap, i32 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: csy %r2, %r3, 524284(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
+  %ptr = getelementptr i32, i32 *%src, i64 131071
   %pair = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst seq_cst
   %val = extractvalue { i32, i1 } %pair, 0
   ret i32 %val
@@ -52,7 +52,7 @@ define i32 @f5(i32 %cmp, i32 %swap, i32 *%src) {
 ; CHECK: agfi %r4, 524288
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
+  %ptr = getelementptr i32, i32 *%src, i64 131072
   %pair = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst seq_cst
   %val = extractvalue { i32, i1 } %pair, 0
   ret i32 %val
@@ -63,7 +63,7 @@ define i32 @f6(i32 %cmp, i32 %swap, i32 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: csy %r2, %r3, -4(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
+  %ptr = getelementptr i32, i32 *%src, i64 -1
   %pair = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst seq_cst
   %val = extractvalue { i32, i1 } %pair, 0
   ret i32 %val
@@ -74,7 +74,7 @@ define i32 @f7(i32 %cmp, i32 %swap, i32 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: csy %r2, %r3, -524288(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
   %pair = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst seq_cst
   %val = extractvalue { i32, i1 } %pair, 0
   ret i32 %val
@@ -87,7 +87,7 @@ define i32 @f8(i32 %cmp, i32 %swap, i32 *%src) {
 ; CHECK: agfi %r4, -524292
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
   %pair = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst seq_cst
   %val = extractvalue { i32, i1 } %pair, 0
   ret i32 %val
diff --git a/test/CodeGen/SystemZ/cmpxchg-04.ll b/test/CodeGen/SystemZ/cmpxchg-04.ll
index ba1493e1853e..b0560876b876 100644
--- a/test/CodeGen/SystemZ/cmpxchg-04.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-04.ll
@@ -17,7 +17,7 @@ define i64 @f2(i64 %cmp, i64 %swap, i64 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: csg %r2, %r3, 524280(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
+  %ptr = getelementptr i64, i64 *%src, i64 65535
   %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
   %val = extractvalue { i64, i1 } %pairval, 0
   ret i64 %val
@@ -30,7 +30,7 @@ define i64 @f3(i64 %cmp, i64 %swap, i64 *%src) {
 ; CHECK: agfi %r4, 524288
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
+  %ptr = getelementptr i64, i64 *%src, i64 65536
   %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
   %val = extractvalue { i64, i1 } %pairval, 0
   ret i64 %val
@@ -41,7 +41,7 @@ define i64 @f4(i64 %cmp, i64 %swap, i64 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: csg %r2, %r3, -8(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -1
+  %ptr = getelementptr i64, i64 *%src, i64 -1
   %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
   %val = extractvalue { i64, i1 } %pairval, 0
   ret i64 %val
@@ -52,7 +52,7 @@ define i64 @f5(i64 %cmp, i64 %swap, i64 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: csg %r2, %r3, -524288(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
   %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
   %val = extractvalue { i64, i1 } %pairval, 0
   ret i64 %val
@@ -65,7 +65,7 @@ define i64 @f6(i64 %cmp, i64 %swap, i64 *%src) {
 ; CHECK: agfi %r4, -524296
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
   %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
   %val = extractvalue { i64, i1 } %pairval, 0
   ret i64 %val
diff --git a/test/CodeGen/SystemZ/cond-load-01.ll b/test/CodeGen/SystemZ/cond-load-01.ll
index 1030226798d1..97d4027126b8 100644
--- a/test/CodeGen/SystemZ/cond-load-01.ll
+++ b/test/CodeGen/SystemZ/cond-load-01.ll
@@ -11,7 +11,7 @@ define i32 @f1(i32 %easy, i32 *%ptr, i32 %limit) {
 ; CHECK: loche %r2, 0(%r3)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 42
-  %other = load i32 *%ptr
+  %other = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %easy, i32 %other
   ret i32 %res
 }
@@ -23,7 +23,7 @@ define i32 @f2(i32 %easy, i32 *%ptr, i32 %limit) {
 ; CHECK: locl %r2, 0(%r3)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 42
-  %other = load i32 *%ptr
+  %other = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %other, i32 %easy
   ret i32 %res
 }
@@ -34,9 +34,9 @@ define i32 @f3(i32 %easy, i32 *%base, i32 %limit) {
 ; CHECK: clfi %r4, 42
 ; CHECK: loche %r2, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131071
+  %ptr = getelementptr i32, i32 *%base, i64 131071
   %cond = icmp ult i32 %limit, 42
-  %other = load i32 *%ptr
+  %other = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %easy, i32 %other
   ret i32 %res
 }
@@ -48,9 +48,9 @@ define i32 @f4(i32 %easy, i32 *%base, i32 %limit) {
 ; CHECK: clfi %r4, 42
 ; CHECK: loche %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131072
+  %ptr = getelementptr i32, i32 *%base, i64 131072
   %cond = icmp ult i32 %limit, 42
-  %other = load i32 *%ptr
+  %other = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %easy, i32 %other
   ret i32 %res
 }
@@ -61,9 +61,9 @@ define i32 @f5(i32 %easy, i32 *%base, i32 %limit) {
 ; CHECK: clfi %r4, 42
 ; CHECK: loche %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131072
+  %ptr = getelementptr i32, i32 *%base, i64 -131072
   %cond = icmp ult i32 %limit, 42
-  %other = load i32 *%ptr
+  %other = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %easy, i32 %other
   ret i32 %res
 }
@@ -75,9 +75,9 @@ define i32 @f6(i32 %easy, i32 *%base, i32 %limit) {
 ; CHECK: clfi %r4, 42
 ; CHECK: loche %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131073
+  %ptr = getelementptr i32, i32 *%base, i64 -131073
   %cond = icmp ult i32 %limit, 42
-  %other = load i32 *%ptr
+  %other = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %easy, i32 %other
   ret i32 %res
 }
@@ -91,7 +91,7 @@ define i32 @f7(i32 %alt, i32 %limit) {
   %ptr = alloca i32
   %easy = call i32 @foo(i32 *%ptr)
   %cond = icmp ult i32 %limit, 42
-  %other = load i32 *%ptr
+  %other = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %easy, i32 %other
   ret i32 %res
 }
@@ -105,7 +105,7 @@ define i32 @f8(i32 %easy, i32 %limit, i64 %base, i64 %index) {
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i32 *
   %cond = icmp ult i32 %limit, 42
-  %other = load i32 *%ptr
+  %other = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %easy, i32 %other
   ret i32 %res
 }
@@ -121,7 +121,7 @@ entry:
   br i1 %cmp, label %load, label %exit
 
 load:
-  %other = load i32 *%ptr
+  %other = load i32 , i32 *%ptr
   br label %exit
 
 exit:
diff --git a/test/CodeGen/SystemZ/cond-load-02.ll b/test/CodeGen/SystemZ/cond-load-02.ll
index e97f4728bc0b..d0fe65e2fe0e 100644
--- a/test/CodeGen/SystemZ/cond-load-02.ll
+++ b/test/CodeGen/SystemZ/cond-load-02.ll
@@ -11,7 +11,7 @@ define i64 @f1(i64 %easy, i64 *%ptr, i64 %limit) {
 ; CHECK: locghe %r2, 0(%r3)
 ; CHECK: br %r14
   %cond = icmp ult i64 %limit, 42
-  %other = load i64 *%ptr
+  %other = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %easy, i64 %other
   ret i64 %res
 }
@@ -23,7 +23,7 @@ define i64 @f2(i64 %easy, i64 *%ptr, i64 %limit) {
 ; CHECK: locgl %r2, 0(%r3)
 ; CHECK: br %r14
   %cond = icmp ult i64 %limit, 42
-  %other = load i64 *%ptr
+  %other = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %other, i64 %easy
   ret i64 %res
 }
@@ -34,9 +34,9 @@ define i64 @f3(i64 %easy, i64 *%base, i64 %limit) {
 ; CHECK: clgfi %r4, 42
 ; CHECK: locghe %r2, 524280(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 65535
+  %ptr = getelementptr i64, i64 *%base, i64 65535
   %cond = icmp ult i64 %limit, 42
-  %other = load i64 *%ptr
+  %other = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %easy, i64 %other
   ret i64 %res
 }
@@ -48,9 +48,9 @@ define i64 @f4(i64 %easy, i64 *%base, i64 %limit) {
 ; CHECK: clgfi %r4, 42
 ; CHECK: locghe %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 65536
+  %ptr = getelementptr i64, i64 *%base, i64 65536
   %cond = icmp ult i64 %limit, 42
-  %other = load i64 *%ptr
+  %other = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %easy, i64 %other
   ret i64 %res
 }
@@ -61,9 +61,9 @@ define i64 @f5(i64 %easy, i64 *%base, i64 %limit) {
 ; CHECK: clgfi %r4, 42
 ; CHECK: locghe %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -65536
+  %ptr = getelementptr i64, i64 *%base, i64 -65536
   %cond = icmp ult i64 %limit, 42
-  %other = load i64 *%ptr
+  %other = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %easy, i64 %other
   ret i64 %res
 }
@@ -75,9 +75,9 @@ define i64 @f6(i64 %easy, i64 *%base, i64 %limit) {
 ; CHECK: clgfi %r4, 42
 ; CHECK: locghe %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -65537
+  %ptr = getelementptr i64, i64 *%base, i64 -65537
   %cond = icmp ult i64 %limit, 42
-  %other = load i64 *%ptr
+  %other = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %easy, i64 %other
   ret i64 %res
 }
@@ -91,7 +91,7 @@ define i64 @f7(i64 %alt, i64 %limit) {
   %ptr = alloca i64
   %easy = call i64 @foo(i64 *%ptr)
   %cond = icmp ult i64 %limit, 42
-  %other = load i64 *%ptr
+  %other = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %easy, i64 %other
   ret i64 %res
 }
@@ -105,7 +105,7 @@ define i64 @f8(i64 %easy, i64 %limit, i64 %base, i64 %index) {
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i64 *
   %cond = icmp ult i64 %limit, 42
-  %other = load i64 *%ptr
+  %other = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %easy, i64 %other
   ret i64 %res
 }
@@ -121,7 +121,7 @@ entry:
   br i1 %cmp, label %load, label %exit
 
 load:
-  %other = load i64 *%ptr
+  %other = load i64 , i64 *%ptr
   br label %exit
 
 exit:
diff --git a/test/CodeGen/SystemZ/cond-store-01.ll b/test/CodeGen/SystemZ/cond-store-01.ll
index 62e9796fa21b..ec7fc4a31fcd 100644
--- a/test/CodeGen/SystemZ/cond-store-01.ll
+++ b/test/CodeGen/SystemZ/cond-store-01.ll
@@ -15,7 +15,7 @@ define void @f1(i8 *%ptr, i8 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
@@ -31,7 +31,7 @@ define void @f2(i8 *%ptr, i8 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %alt, i8 %orig
   store i8 %res, i8 *%ptr
   ret void
@@ -48,7 +48,7 @@ define void @f3(i8 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %ext = sext i8 %orig to i32
   %res = select i1 %cond, i32 %ext, i32 %alt
   %trunc = trunc i32 %res to i8
@@ -66,7 +66,7 @@ define void @f4(i8 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %ext = sext i8 %orig to i32
   %res = select i1 %cond, i32 %alt, i32 %ext
   %trunc = trunc i32 %res to i8
@@ -85,7 +85,7 @@ define void @f5(i8 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %ext = zext i8 %orig to i32
   %res = select i1 %cond, i32 %ext, i32 %alt
   %trunc = trunc i32 %res to i8
@@ -103,7 +103,7 @@ define void @f6(i8 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %ext = zext i8 %orig to i32
   %res = select i1 %cond, i32 %alt, i32 %ext
   %trunc = trunc i32 %res to i8
@@ -122,7 +122,7 @@ define void @f7(i8 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %ext = sext i8 %orig to i64
   %res = select i1 %cond, i64 %ext, i64 %alt
   %trunc = trunc i64 %res to i8
@@ -140,7 +140,7 @@ define void @f8(i8 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %ext = sext i8 %orig to i64
   %res = select i1 %cond, i64 %alt, i64 %ext
   %trunc = trunc i64 %res to i8
@@ -159,7 +159,7 @@ define void @f9(i8 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %ext = zext i8 %orig to i64
   %res = select i1 %cond, i64 %ext, i64 %alt
   %trunc = trunc i64 %res to i8
@@ -177,7 +177,7 @@ define void @f10(i8 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %ext = zext i8 %orig to i64
   %res = select i1 %cond, i64 %alt, i64 %ext
   %trunc = trunc i64 %res to i8
@@ -194,9 +194,9 @@ define void @f11(i8 *%base, i8 %alt, i32 %limit) {
 ; CHECK: stc %r3, 4095(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%base, i64 4095
+  %ptr = getelementptr i8, i8 *%base, i64 4095
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
@@ -211,9 +211,9 @@ define void @f12(i8 *%base, i8 %alt, i32 %limit) {
 ; CHECK: stcy %r3, 4096(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%base, i64 4096
+  %ptr = getelementptr i8, i8 *%base, i64 4096
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
@@ -228,9 +228,9 @@ define void @f13(i8 *%base, i8 %alt, i32 %limit) {
 ; CHECK: stcy %r3, 524287(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%base, i64 524287
+  %ptr = getelementptr i8, i8 *%base, i64 524287
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
@@ -247,9 +247,9 @@ define void @f14(i8 *%base, i8 %alt, i32 %limit) {
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%base, i64 524288
+  %ptr = getelementptr i8, i8 *%base, i64 524288
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
@@ -264,9 +264,9 @@ define void @f15(i8 *%base, i8 %alt, i32 %limit) {
 ; CHECK: stcy %r3, -524288(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%base, i64 -524288
+  %ptr = getelementptr i8, i8 *%base, i64 -524288
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
@@ -283,9 +283,9 @@ define void @f16(i8 *%base, i8 %alt, i32 %limit) {
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%base, i64 -524289
+  %ptr = getelementptr i8, i8 *%base, i64 -524289
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
@@ -304,7 +304,7 @@ define void @f17(i64 %base, i64 %index, i8 %alt, i32 %limit) {
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i8 *
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
@@ -319,7 +319,7 @@ define void @f18(i8 *%ptr, i8 %alt, i32 %limit) {
 ; CHECK: stc {{%r[0-5]}}, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load volatile i8 *%ptr
+  %orig = load volatile i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
@@ -334,7 +334,7 @@ define void @f19(i8 *%ptr, i8 %alt, i32 %limit) {
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store volatile i8 %res, i8 *%ptr
   ret void
@@ -353,7 +353,7 @@ define void @f20(i8 *%ptr, i8 %alt, i32 %limit) {
 ; CHECK: stc {{%r[0-9]+}}, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load atomic i8 *%ptr unordered, align 1
+  %orig = load atomic i8 , i8 *%ptr unordered, align 1
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
@@ -369,7 +369,7 @@ define void @f21(i8 *%ptr, i8 %alt, i32 %limit) {
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store atomic i8 %res, i8 *%ptr unordered, align 1
   ret void
@@ -389,7 +389,7 @@ define void @f22(i8 %alt, i32 %limit) {
   %ptr = alloca i8
   call void @foo(i8 *%ptr)
   %cond = icmp ult i32 %limit, 420
-  %orig = load i8 *%ptr
+  %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   call void @foo(i8 *%ptr)
diff --git a/test/CodeGen/SystemZ/cond-store-02.ll b/test/CodeGen/SystemZ/cond-store-02.ll
index 4fbcdaba5103..22bdfa3c27dc 100644
--- a/test/CodeGen/SystemZ/cond-store-02.ll
+++ b/test/CodeGen/SystemZ/cond-store-02.ll
@@ -15,7 +15,7 @@ define void @f1(i16 *%ptr, i16 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
@@ -31,7 +31,7 @@ define void @f2(i16 *%ptr, i16 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %alt, i16 %orig
   store i16 %res, i16 *%ptr
   ret void
@@ -48,7 +48,7 @@ define void @f3(i16 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %ext = sext i16 %orig to i32
   %res = select i1 %cond, i32 %ext, i32 %alt
   %trunc = trunc i32 %res to i16
@@ -66,7 +66,7 @@ define void @f4(i16 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %ext = sext i16 %orig to i32
   %res = select i1 %cond, i32 %alt, i32 %ext
   %trunc = trunc i32 %res to i16
@@ -85,7 +85,7 @@ define void @f5(i16 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %ext = zext i16 %orig to i32
   %res = select i1 %cond, i32 %ext, i32 %alt
   %trunc = trunc i32 %res to i16
@@ -103,7 +103,7 @@ define void @f6(i16 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %ext = zext i16 %orig to i32
   %res = select i1 %cond, i32 %alt, i32 %ext
   %trunc = trunc i32 %res to i16
@@ -122,7 +122,7 @@ define void @f7(i16 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %ext = sext i16 %orig to i64
   %res = select i1 %cond, i64 %ext, i64 %alt
   %trunc = trunc i64 %res to i16
@@ -140,7 +140,7 @@ define void @f8(i16 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %ext = sext i16 %orig to i64
   %res = select i1 %cond, i64 %alt, i64 %ext
   %trunc = trunc i64 %res to i16
@@ -159,7 +159,7 @@ define void @f9(i16 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %ext = zext i16 %orig to i64
   %res = select i1 %cond, i64 %ext, i64 %alt
   %trunc = trunc i64 %res to i16
@@ -177,7 +177,7 @@ define void @f10(i16 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %ext = zext i16 %orig to i64
   %res = select i1 %cond, i64 %alt, i64 %ext
   %trunc = trunc i64 %res to i16
@@ -194,9 +194,9 @@ define void @f11(i16 *%base, i16 %alt, i32 %limit) {
 ; CHECK: sth %r3, 4094(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%base, i64 2047
+  %ptr = getelementptr i16, i16 *%base, i64 2047
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
@@ -211,9 +211,9 @@ define void @f12(i16 *%base, i16 %alt, i32 %limit) {
 ; CHECK: sthy %r3, 4096(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%base, i64 2048
+  %ptr = getelementptr i16, i16 *%base, i64 2048
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
@@ -228,9 +228,9 @@ define void @f13(i16 *%base, i16 %alt, i32 %limit) {
 ; CHECK: sthy %r3, 524286(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%base, i64 262143
+  %ptr = getelementptr i16, i16 *%base, i64 262143
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
@@ -247,9 +247,9 @@ define void @f14(i16 *%base, i16 %alt, i32 %limit) {
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%base, i64 262144
+  %ptr = getelementptr i16, i16 *%base, i64 262144
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
@@ -264,9 +264,9 @@ define void @f15(i16 *%base, i16 %alt, i32 %limit) {
 ; CHECK: sthy %r3, -524288(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%base, i64 -262144
+  %ptr = getelementptr i16, i16 *%base, i64 -262144
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
@@ -283,9 +283,9 @@ define void @f16(i16 *%base, i16 %alt, i32 %limit) {
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%base, i64 -262145
+  %ptr = getelementptr i16, i16 *%base, i64 -262145
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
@@ -304,7 +304,7 @@ define void @f17(i64 %base, i64 %index, i16 %alt, i32 %limit) {
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i16 *
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
@@ -319,7 +319,7 @@ define void @f18(i16 *%ptr, i16 %alt, i32 %limit) {
 ; CHECK: sth {{%r[0-5]}}, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load volatile i16 *%ptr
+  %orig = load volatile i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
@@ -334,7 +334,7 @@ define void @f19(i16 *%ptr, i16 %alt, i32 %limit) {
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store volatile i16 %res, i16 *%ptr
   ret void
@@ -353,7 +353,7 @@ define void @f20(i16 *%ptr, i16 %alt, i32 %limit) {
 ; CHECK: sth {{%r[0-9]+}}, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load atomic i16 *%ptr unordered, align 2
+  %orig = load atomic i16 , i16 *%ptr unordered, align 2
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
@@ -369,7 +369,7 @@ define void @f21(i16 *%ptr, i16 %alt, i32 %limit) {
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store atomic i16 %res, i16 *%ptr unordered, align 2
   ret void
@@ -389,7 +389,7 @@ define void @f22(i16 %alt, i32 %limit) {
   %ptr = alloca i16
   call void @foo(i16 *%ptr)
   %cond = icmp ult i32 %limit, 420
-  %orig = load i16 *%ptr
+  %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   call void @foo(i16 *%ptr)
diff --git a/test/CodeGen/SystemZ/cond-store-03.ll b/test/CodeGen/SystemZ/cond-store-03.ll
index 4b22555d0d60..7207164a6314 100644
--- a/test/CodeGen/SystemZ/cond-store-03.ll
+++ b/test/CodeGen/SystemZ/cond-store-03.ll
@@ -14,7 +14,7 @@ define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
@@ -30,7 +30,7 @@ define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %alt, i32 %orig
   store i32 %res, i32 *%ptr
   ret void
@@ -47,7 +47,7 @@ define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %ext = sext i32 %orig to i64
   %res = select i1 %cond, i64 %ext, i64 %alt
   %trunc = trunc i64 %res to i32
@@ -65,7 +65,7 @@ define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %ext = sext i32 %orig to i64
   %res = select i1 %cond, i64 %alt, i64 %ext
   %trunc = trunc i64 %res to i32
@@ -84,7 +84,7 @@ define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %ext = zext i32 %orig to i64
   %res = select i1 %cond, i64 %ext, i64 %alt
   %trunc = trunc i64 %res to i32
@@ -102,7 +102,7 @@ define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %ext = zext i32 %orig to i64
   %res = select i1 %cond, i64 %alt, i64 %ext
   %trunc = trunc i64 %res to i32
@@ -119,9 +119,9 @@ define void @f7(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK: st %r3, 4092(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 1023
+  %ptr = getelementptr i32, i32 *%base, i64 1023
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
@@ -136,9 +136,9 @@ define void @f8(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK: sty %r3, 4096(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 1024
+  %ptr = getelementptr i32, i32 *%base, i64 1024
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
@@ -153,9 +153,9 @@ define void @f9(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK: sty %r3, 524284(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131071
+  %ptr = getelementptr i32, i32 *%base, i64 131071
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
@@ -172,9 +172,9 @@ define void @f10(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131072
+  %ptr = getelementptr i32, i32 *%base, i64 131072
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
@@ -189,9 +189,9 @@ define void @f11(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK: sty %r3, -524288(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131072
+  %ptr = getelementptr i32, i32 *%base, i64 -131072
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
@@ -208,9 +208,9 @@ define void @f12(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131073
+  %ptr = getelementptr i32, i32 *%base, i64 -131073
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
@@ -229,7 +229,7 @@ define void @f13(i64 %base, i64 %index, i32 %alt, i32 %limit) {
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i32 *
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
@@ -244,7 +244,7 @@ define void @f14(i32 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: st {{%r[0-5]}}, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load volatile i32 *%ptr
+  %orig = load volatile i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
@@ -259,7 +259,7 @@ define void @f15(i32 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store volatile i32 %res, i32 *%ptr
   ret void
@@ -278,7 +278,7 @@ define void @f16(i32 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: st {{%r[0-5]}}, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load atomic i32 *%ptr unordered, align 4
+  %orig = load atomic i32 , i32 *%ptr unordered, align 4
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
@@ -294,7 +294,7 @@ define void @f17(i32 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store atomic i32 %res, i32 *%ptr unordered, align 4
   ret void
@@ -314,7 +314,7 @@ define void @f18(i32 %alt, i32 %limit) {
   %ptr = alloca i32
   call void @foo(i32 *%ptr)
   %cond = icmp ult i32 %limit, 420
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   call void @foo(i32 *%ptr)
diff --git a/test/CodeGen/SystemZ/cond-store-04.ll b/test/CodeGen/SystemZ/cond-store-04.ll
index 346b51a17d78..7e25bb5c14a0 100644
--- a/test/CodeGen/SystemZ/cond-store-04.ll
+++ b/test/CodeGen/SystemZ/cond-store-04.ll
@@ -14,7 +14,7 @@ define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
@@ -30,7 +30,7 @@ define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %alt, i64 %orig
   store i64 %res, i64 *%ptr
   ret void
@@ -45,9 +45,9 @@ define void @f3(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK: stg %r3, 524280(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 65535
+  %ptr = getelementptr i64, i64 *%base, i64 65535
   %cond = icmp ult i32 %limit, 420
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
@@ -64,9 +64,9 @@ define void @f4(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 65536
+  %ptr = getelementptr i64, i64 *%base, i64 65536
   %cond = icmp ult i32 %limit, 420
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
@@ -81,9 +81,9 @@ define void @f5(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK: stg %r3, -524288(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -65536
+  %ptr = getelementptr i64, i64 *%base, i64 -65536
   %cond = icmp ult i32 %limit, 420
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
@@ -100,9 +100,9 @@ define void @f6(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -65537
+  %ptr = getelementptr i64, i64 *%base, i64 -65537
   %cond = icmp ult i32 %limit, 420
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
@@ -121,7 +121,7 @@ define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) {
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i64 *
   %cond = icmp ult i32 %limit, 420
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
@@ -136,7 +136,7 @@ define void @f8(i64 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: stg {{%r[0-5]}}, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load volatile i64 *%ptr
+  %orig = load volatile i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
@@ -151,7 +151,7 @@ define void @f9(i64 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store volatile i64 %res, i64 *%ptr
   ret void
@@ -170,7 +170,7 @@ define void @f10(i64 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: stg {{%r[0-5]}}, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load atomic i64 *%ptr unordered, align 8
+  %orig = load atomic i64 , i64 *%ptr unordered, align 8
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
@@ -186,7 +186,7 @@ define void @f11(i64 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store atomic i64 %res, i64 *%ptr unordered, align 8
   ret void
@@ -206,7 +206,7 @@ define void @f12(i64 %alt, i32 %limit) {
   %ptr = alloca i64
   call void @foo(i64 *%ptr)
   %cond = icmp ult i32 %limit, 420
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   call void @foo(i64 *%ptr)
diff --git a/test/CodeGen/SystemZ/cond-store-05.ll b/test/CodeGen/SystemZ/cond-store-05.ll
index f8056f73c928..0cc068380e07 100644
--- a/test/CodeGen/SystemZ/cond-store-05.ll
+++ b/test/CodeGen/SystemZ/cond-store-05.ll
@@ -14,7 +14,7 @@ define void @f1(float *%ptr, float %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load float *%ptr
+  %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
@@ -30,7 +30,7 @@ define void @f2(float *%ptr, float %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load float *%ptr
+  %orig = load float , float *%ptr
   %res = select i1 %cond, float %alt, float %orig
   store float %res, float *%ptr
   ret void
@@ -45,9 +45,9 @@ define void @f3(float *%base, float %alt, i32 %limit) {
 ; CHECK: ste %f0, 4092(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1023
+  %ptr = getelementptr float, float *%base, i64 1023
   %cond = icmp ult i32 %limit, 420
-  %orig = load float *%ptr
+  %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
@@ -62,9 +62,9 @@ define void @f4(float *%base, float %alt, i32 %limit) {
 ; CHECK: stey %f0, 4096(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1024
+  %ptr = getelementptr float, float *%base, i64 1024
   %cond = icmp ult i32 %limit, 420
-  %orig = load float *%ptr
+  %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
@@ -79,9 +79,9 @@ define void @f5(float *%base, float %alt, i32 %limit) {
 ; CHECK: stey %f0, 524284(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 131071
+  %ptr = getelementptr float, float *%base, i64 131071
   %cond = icmp ult i32 %limit, 420
-  %orig = load float *%ptr
+  %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
@@ -98,9 +98,9 @@ define void @f6(float *%base, float %alt, i32 %limit) {
 ; CHECK: ste %f0, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 131072
+  %ptr = getelementptr float, float *%base, i64 131072
   %cond = icmp ult i32 %limit, 420
-  %orig = load float *%ptr
+  %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
@@ -115,9 +115,9 @@ define void @f7(float *%base, float %alt, i32 %limit) {
 ; CHECK: stey %f0, -524288(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 -131072
+  %ptr = getelementptr float, float *%base, i64 -131072
   %cond = icmp ult i32 %limit, 420
-  %orig = load float *%ptr
+  %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
@@ -134,9 +134,9 @@ define void @f8(float *%base, float %alt, i32 %limit) {
 ; CHECK: ste %f0, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 -131073
+  %ptr = getelementptr float, float *%base, i64 -131073
   %cond = icmp ult i32 %limit, 420
-  %orig = load float *%ptr
+  %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
@@ -155,7 +155,7 @@ define void @f9(i64 %base, i64 %index, float %alt, i32 %limit) {
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to float *
   %cond = icmp ult i32 %limit, 420
-  %orig = load float *%ptr
+  %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
@@ -170,7 +170,7 @@ define void @f10(float *%ptr, float %alt, i32 %limit) {
 ; CHECK: ste {{%f[0-5]}}, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load volatile float *%ptr
+  %orig = load volatile float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
@@ -185,7 +185,7 @@ define void @f11(float *%ptr, float %alt, i32 %limit) {
 ; CHECK: ste %f0, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load float *%ptr
+  %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store volatile float %res, float *%ptr
   ret void
@@ -205,7 +205,7 @@ define void @f12(float %alt, i32 %limit) {
   %ptr = alloca float
   call void @foo(float *%ptr)
   %cond = icmp ult i32 %limit, 420
-  %orig = load float *%ptr
+  %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   call void @foo(float *%ptr)
diff --git a/test/CodeGen/SystemZ/cond-store-06.ll b/test/CodeGen/SystemZ/cond-store-06.ll
index 66681958d474..01948b811504 100644
--- a/test/CodeGen/SystemZ/cond-store-06.ll
+++ b/test/CodeGen/SystemZ/cond-store-06.ll
@@ -14,7 +14,7 @@ define void @f1(double *%ptr, double %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load double *%ptr
+  %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
@@ -30,7 +30,7 @@ define void @f2(double *%ptr, double %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load double *%ptr
+  %orig = load double , double *%ptr
   %res = select i1 %cond, double %alt, double %orig
   store double %res, double *%ptr
   ret void
@@ -45,9 +45,9 @@ define void @f3(double *%base, double %alt, i32 %limit) {
 ; CHECK: std %f0, 4088(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 511
+  %ptr = getelementptr double, double *%base, i64 511
   %cond = icmp ult i32 %limit, 420
-  %orig = load double *%ptr
+  %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
@@ -62,9 +62,9 @@ define void @f4(double *%base, double %alt, i32 %limit) {
 ; CHECK: stdy %f0, 4096(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 512
+  %ptr = getelementptr double, double *%base, i64 512
   %cond = icmp ult i32 %limit, 420
-  %orig = load double *%ptr
+  %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
@@ -79,9 +79,9 @@ define void @f5(double *%base, double %alt, i32 %limit) {
 ; CHECK: stdy %f0, 524280(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 65535
+  %ptr = getelementptr double, double *%base, i64 65535
   %cond = icmp ult i32 %limit, 420
-  %orig = load double *%ptr
+  %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
@@ -98,9 +98,9 @@ define void @f6(double *%base, double %alt, i32 %limit) {
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 65536
+  %ptr = getelementptr double, double *%base, i64 65536
   %cond = icmp ult i32 %limit, 420
-  %orig = load double *%ptr
+  %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
@@ -115,9 +115,9 @@ define void @f7(double *%base, double %alt, i32 %limit) {
 ; CHECK: stdy %f0, -524288(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 -65536
+  %ptr = getelementptr double, double *%base, i64 -65536
   %cond = icmp ult i32 %limit, 420
-  %orig = load double *%ptr
+  %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
@@ -134,9 +134,9 @@ define void @f8(double *%base, double %alt, i32 %limit) {
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 -65537
+  %ptr = getelementptr double, double *%base, i64 -65537
   %cond = icmp ult i32 %limit, 420
-  %orig = load double *%ptr
+  %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
@@ -155,7 +155,7 @@ define void @f9(i64 %base, i64 %index, double %alt, i32 %limit) {
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to double *
   %cond = icmp ult i32 %limit, 420
-  %orig = load double *%ptr
+  %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
@@ -170,7 +170,7 @@ define void @f10(double *%ptr, double %alt, i32 %limit) {
 ; CHECK: std {{%f[0-5]}}, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load volatile double *%ptr
+  %orig = load volatile double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
@@ -185,7 +185,7 @@ define void @f11(double *%ptr, double %alt, i32 %limit) {
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
-  %orig = load double *%ptr
+  %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store volatile double %res, double *%ptr
   ret void
@@ -205,7 +205,7 @@ define void @f12(double %alt, i32 %limit) {
   %ptr = alloca double
   call void @foo(double *%ptr)
   %cond = icmp ult i32 %limit, 420
-  %orig = load double *%ptr
+  %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   call void @foo(double *%ptr)
diff --git a/test/CodeGen/SystemZ/cond-store-07.ll b/test/CodeGen/SystemZ/cond-store-07.ll
index b1df525566a3..35b1303f4024 100644
--- a/test/CodeGen/SystemZ/cond-store-07.ll
+++ b/test/CodeGen/SystemZ/cond-store-07.ll
@@ -11,7 +11,7 @@ define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: stoche %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 42
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
@@ -24,7 +24,7 @@ define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK: stocl %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 42
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %alt, i32 %orig
   store i32 %res, i32 *%ptr
   ret void
@@ -38,7 +38,7 @@ define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: stoche %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 42
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %ext = sext i32 %orig to i64
   %res = select i1 %cond, i64 %ext, i64 %alt
   %trunc = trunc i64 %res to i32
@@ -53,7 +53,7 @@ define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: stocl %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 42
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %ext = sext i32 %orig to i64
   %res = select i1 %cond, i64 %alt, i64 %ext
   %trunc = trunc i64 %res to i32
@@ -69,7 +69,7 @@ define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: stoche %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 42
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %ext = zext i32 %orig to i64
   %res = select i1 %cond, i64 %ext, i64 %alt
   %trunc = trunc i64 %res to i32
@@ -84,7 +84,7 @@ define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: stocl %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 42
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %ext = zext i32 %orig to i64
   %res = select i1 %cond, i64 %alt, i64 %ext
   %trunc = trunc i64 %res to i32
@@ -98,9 +98,9 @@ define void @f7(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK: clfi %r4, 42
 ; CHECK: stoche %r3, 524284(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131071
+  %ptr = getelementptr i32, i32 *%base, i64 131071
   %cond = icmp ult i32 %limit, 42
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
@@ -113,9 +113,9 @@ define void @f8(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK: clfi %r4, 42
 ; CHECK: stoche %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131072
+  %ptr = getelementptr i32, i32 *%base, i64 131072
   %cond = icmp ult i32 %limit, 42
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
@@ -127,9 +127,9 @@ define void @f9(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK: clfi %r4, 42
 ; CHECK: stoche %r3, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131072
+  %ptr = getelementptr i32, i32 *%base, i64 -131072
   %cond = icmp ult i32 %limit, 42
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
@@ -142,9 +142,9 @@ define void @f10(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK: clfi %r4, 42
 ; CHECK: stoche %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131073
+  %ptr = getelementptr i32, i32 *%base, i64 -131073
   %cond = icmp ult i32 %limit, 42
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
@@ -160,7 +160,7 @@ define void @f11(i32 %alt, i32 %limit) {
   %ptr = alloca i32
   call void @foo(i32 *%ptr)
   %cond = icmp ult i32 %limit, 42
-  %orig = load i32 *%ptr
+  %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   call void @foo(i32 *%ptr)
diff --git a/test/CodeGen/SystemZ/cond-store-08.ll b/test/CodeGen/SystemZ/cond-store-08.ll
index 56dc7ee7777c..4c2b005968e8 100644
--- a/test/CodeGen/SystemZ/cond-store-08.ll
+++ b/test/CodeGen/SystemZ/cond-store-08.ll
@@ -11,7 +11,7 @@ define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: stocghe %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 42
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
@@ -24,7 +24,7 @@ define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK: stocgl %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 42
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %alt, i64 %orig
   store i64 %res, i64 *%ptr
   ret void
@@ -36,9 +36,9 @@ define void @f3(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK: clfi %r4, 42
 ; CHECK: stocghe %r3, 524280(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 65535
+  %ptr = getelementptr i64, i64 *%base, i64 65535
   %cond = icmp ult i32 %limit, 42
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
@@ -51,9 +51,9 @@ define void @f4(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK: clfi %r4, 42
 ; CHECK: stocghe %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 65536
+  %ptr = getelementptr i64, i64 *%base, i64 65536
   %cond = icmp ult i32 %limit, 42
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
@@ -65,9 +65,9 @@ define void @f5(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK: clfi %r4, 42
 ; CHECK: stocghe %r3, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -65536
+  %ptr = getelementptr i64, i64 *%base, i64 -65536
   %cond = icmp ult i32 %limit, 42
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
@@ -80,9 +80,9 @@ define void @f6(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK: clfi %r4, 42
 ; CHECK: stocghe %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -65537
+  %ptr = getelementptr i64, i64 *%base, i64 -65537
   %cond = icmp ult i32 %limit, 42
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
@@ -98,7 +98,7 @@ define void @f7(i64 %alt, i32 %limit) {
   %ptr = alloca i64
   call void @foo(i64 *%ptr)
   %cond = icmp ult i32 %limit, 42
-  %orig = load i64 *%ptr
+  %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   call void @foo(i64 *%ptr)
diff --git a/test/CodeGen/SystemZ/ctpop-01.ll b/test/CodeGen/SystemZ/ctpop-01.ll
new file mode 100644
index 000000000000..ad80f9f21515
--- /dev/null
+++ b/test/CodeGen/SystemZ/ctpop-01.ll
@@ -0,0 +1,96 @@
+; Test population-count instruction
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i32 @llvm.ctpop.i32(i32 %a)
+declare i64 @llvm.ctpop.i64(i64 %a)
+
+define i32 @f1(i32 %a) {
+; CHECK-LABEL: f1:
+; CHECK: popcnt  %r0, %r2
+; CHECK: sllk    %r1, %r0, 16
+; CHECK: ar      %r1, %r0
+; CHECK: sllk    %r2, %r1, 8
+; CHECK: ar      %r2, %r1
+; CHECK: srl     %r2, 24
+; CHECK: br      %r14
+
+  %popcnt = call i32 @llvm.ctpop.i32(i32 %a)
+  ret i32 %popcnt
+}
+
+define i32 @f2(i32 %a) {
+; CHECK-LABEL: f2:
+; CHECK: llhr    %r0, %r2
+; CHECK: popcnt  %r0, %r0
+; CHECK: risblg  %r2, %r0, 16, 151, 8
+; CHECK: ar      %r2, %r0
+; CHECK: srl     %r2, 8
+; CHECK: br      %r14
+  %and = and i32 %a, 65535
+  %popcnt = call i32 @llvm.ctpop.i32(i32 %and)
+  ret i32 %popcnt
+}
+
+define i32 @f3(i32 %a) {
+; CHECK-LABEL: f3:
+; CHECK: llcr    %r0, %r2
+; CHECK: popcnt  %r2, %r0
+; CHECK: br      %r14
+  %and = and i32 %a, 255
+  %popcnt = call i32 @llvm.ctpop.i32(i32 %and)
+  ret i32 %popcnt
+}
+
+define i64 @f4(i64 %a) {
+; CHECK-LABEL: f4:
+; CHECK: popcnt  %r0, %r2
+; CHECK: sllg    %r1, %r0, 32
+; CHECK: agr     %r1, %r0
+; CHECK: sllg    %r0, %r1, 16
+; CHECK: agr     %r0, %r1
+; CHECK: sllg    %r1, %r0, 8
+; CHECK: agr     %r1, %r0
+; CHECK: srlg    %r2, %r1, 56
+; CHECK: br      %r14
+  %popcnt = call i64 @llvm.ctpop.i64(i64 %a)
+  ret i64 %popcnt
+}
+
+define i64 @f5(i64 %a) {
+; CHECK-LABEL: f5:
+; CHECK: llgfr   %r0, %r2
+; CHECK: popcnt  %r0, %r0
+; CHECK: sllg    %r1, %r0, 16
+; CHECK: algfr   %r0, %r1
+; CHECK: sllg    %r1, %r0, 8
+; CHECK: algfr   %r0, %r1
+; CHECK: srlg    %r2, %r0, 24
+  %and = and i64 %a, 4294967295
+  %popcnt = call i64 @llvm.ctpop.i64(i64 %and)
+  ret i64 %popcnt
+}
+
+define i64 @f6(i64 %a) {
+; CHECK-LABEL: f6:
+; CHECK: llghr   %r0, %r2
+; CHECK: popcnt  %r0, %r0
+; CHECK: risbg   %r1, %r0, 48, 183, 8
+; CHECK: agr     %r1, %r0
+; CHECK: srlg    %r2, %r1, 8
+; CHECK: br      %r14
+  %and = and i64 %a, 65535
+  %popcnt = call i64 @llvm.ctpop.i64(i64 %and)
+  ret i64 %popcnt
+}
+
+define i64 @f7(i64 %a) {
+; CHECK-LABEL: f7:
+; CHECK: llgcr   %r0, %r2
+; CHECK: popcnt  %r2, %r0
+; CHECK: br      %r14
+  %and = and i64 %a, 255
+  %popcnt = call i64 @llvm.ctpop.i64(i64 %and)
+  ret i64 %popcnt
+}
+
diff --git a/test/CodeGen/SystemZ/fp-abs-01.ll b/test/CodeGen/SystemZ/fp-abs-01.ll
index 0b4067da3d14..3b143d93315b 100644
--- a/test/CodeGen/SystemZ/fp-abs-01.ll
+++ b/test/CodeGen/SystemZ/fp-abs-01.ll
@@ -1,6 +1,7 @@
 ; Test floating-point absolute.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 ; Test f32.
 declare float @llvm.fabs.f32(float %f)
@@ -31,9 +32,9 @@ define void @f3(fp128 *%ptr, fp128 *%ptr2) {
 ; CHECK: lpxbr
 ; CHECK: dxbr
 ; CHECK: br %r14
-  %orig = load fp128 *%ptr
+  %orig = load fp128 , fp128 *%ptr
   %abs = call fp128 @llvm.fabs.f128(fp128 %orig)
-  %op2 = load fp128 *%ptr2
+  %op2 = load fp128 , fp128 *%ptr2
   %res = fdiv fp128 %abs, %op2
   store fp128 %res, fp128 *%ptr
   ret void
diff --git a/test/CodeGen/SystemZ/fp-abs-02.ll b/test/CodeGen/SystemZ/fp-abs-02.ll
index 909c48a06377..e831ddb86fea 100644
--- a/test/CodeGen/SystemZ/fp-abs-02.ll
+++ b/test/CodeGen/SystemZ/fp-abs-02.ll
@@ -1,6 +1,7 @@
 ; Test negated floating-point absolute.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 ; Test f32.
 declare float @llvm.fabs.f32(float %f)
@@ -33,10 +34,10 @@ define void @f3(fp128 *%ptr, fp128 *%ptr2) {
 ; CHECK: lnxbr
 ; CHECK: dxbr
 ; CHECK: br %r14
-  %orig = load fp128 *%ptr
+  %orig = load fp128 , fp128 *%ptr
   %abs = call fp128 @llvm.fabs.f128(fp128 %orig)
   %negabs = fsub fp128 0xL00000000000000008000000000000000, %abs
-  %op2 = load fp128 *%ptr2
+  %op2 = load fp128 , fp128 *%ptr2
   %res = fdiv fp128 %negabs, %op2
   store fp128 %res, fp128 *%ptr
   ret void
diff --git a/test/CodeGen/SystemZ/fp-add-01.ll b/test/CodeGen/SystemZ/fp-add-01.ll
index 28a212801a63..5b0ed0513a37 100644
--- a/test/CodeGen/SystemZ/fp-add-01.ll
+++ b/test/CodeGen/SystemZ/fp-add-01.ll
@@ -18,7 +18,7 @@ define float @f2(float %f1, float *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: aeb %f0, 0(%r2)
 ; CHECK: br %r14
-  %f2 = load float *%ptr
+  %f2 = load float , float *%ptr
   %res = fadd float %f1, %f2
   ret float %res
 }
@@ -28,8 +28,8 @@ define float @f3(float %f1, float *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: aeb %f0, 4092(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1023
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1023
+  %f2 = load float , float *%ptr
   %res = fadd float %f1, %f2
   ret float %res
 }
@@ -41,8 +41,8 @@ define float @f4(float %f1, float *%base) {
 ; CHECK: aghi %r2, 4096
 ; CHECK: aeb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1024
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1024
+  %f2 = load float , float *%ptr
   %res = fadd float %f1, %f2
   ret float %res
 }
@@ -53,8 +53,8 @@ define float @f5(float %f1, float *%base) {
 ; CHECK: aghi %r2, -4
 ; CHECK: aeb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 -1
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 -1
+  %f2 = load float , float *%ptr
   %res = fadd float %f1, %f2
   ret float %res
 }
@@ -65,9 +65,9 @@ define float @f6(float %f1, float *%base, i64 %index) {
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: aeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%base, i64 %index
-  %ptr2 = getelementptr float *%ptr1, i64 100
-  %f2 = load float *%ptr2
+  %ptr1 = getelementptr float, float *%base, i64 %index
+  %ptr2 = getelementptr float, float *%ptr1, i64 100
+  %f2 = load float , float *%ptr2
   %res = fadd float %f1, %f2
   ret float %res
 }
@@ -78,28 +78,28 @@ define float @f7(float *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: aeb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%ptr0, i64 2
-  %ptr2 = getelementptr float *%ptr0, i64 4
-  %ptr3 = getelementptr float *%ptr0, i64 6
-  %ptr4 = getelementptr float *%ptr0, i64 8
-  %ptr5 = getelementptr float *%ptr0, i64 10
-  %ptr6 = getelementptr float *%ptr0, i64 12
-  %ptr7 = getelementptr float *%ptr0, i64 14
-  %ptr8 = getelementptr float *%ptr0, i64 16
-  %ptr9 = getelementptr float *%ptr0, i64 18
-  %ptr10 = getelementptr float *%ptr0, i64 20
+  %ptr1 = getelementptr float, float *%ptr0, i64 2
+  %ptr2 = getelementptr float, float *%ptr0, i64 4
+  %ptr3 = getelementptr float, float *%ptr0, i64 6
+  %ptr4 = getelementptr float, float *%ptr0, i64 8
+  %ptr5 = getelementptr float, float *%ptr0, i64 10
+  %ptr6 = getelementptr float, float *%ptr0, i64 12
+  %ptr7 = getelementptr float, float *%ptr0, i64 14
+  %ptr8 = getelementptr float, float *%ptr0, i64 16
+  %ptr9 = getelementptr float, float *%ptr0, i64 18
+  %ptr10 = getelementptr float, float *%ptr0, i64 20
 
-  %val0 = load float *%ptr0
-  %val1 = load float *%ptr1
-  %val2 = load float *%ptr2
-  %val3 = load float *%ptr3
-  %val4 = load float *%ptr4
-  %val5 = load float *%ptr5
-  %val6 = load float *%ptr6
-  %val7 = load float *%ptr7
-  %val8 = load float *%ptr8
-  %val9 = load float *%ptr9
-  %val10 = load float *%ptr10
+  %val0 = load float , float *%ptr0
+  %val1 = load float , float *%ptr1
+  %val2 = load float , float *%ptr2
+  %val3 = load float , float *%ptr3
+  %val4 = load float , float *%ptr4
+  %val5 = load float , float *%ptr5
+  %val6 = load float , float *%ptr6
+  %val7 = load float , float *%ptr7
+  %val8 = load float , float *%ptr8
+  %val9 = load float , float *%ptr9
+  %val10 = load float , float *%ptr10
 
   %ret = call float @foo()
 
diff --git a/test/CodeGen/SystemZ/fp-add-02.ll b/test/CodeGen/SystemZ/fp-add-02.ll
index 067c7474fb43..5be1ad79d453 100644
--- a/test/CodeGen/SystemZ/fp-add-02.ll
+++ b/test/CodeGen/SystemZ/fp-add-02.ll
@@ -1,7 +1,8 @@
 ; Test 64-bit floating-point addition.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
-
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 declare double @foo()
 
 ; Check register addition.
@@ -18,7 +19,7 @@ define double @f2(double %f1, double *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: adb %f0, 0(%r2)
 ; CHECK: br %r14
-  %f2 = load double *%ptr
+  %f2 = load double , double *%ptr
   %res = fadd double %f1, %f2
   ret double %res
 }
@@ -28,8 +29,8 @@ define double @f3(double %f1, double *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: adb %f0, 4088(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 511
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 511
+  %f2 = load double , double *%ptr
   %res = fadd double %f1, %f2
   ret double %res
 }
@@ -41,8 +42,8 @@ define double @f4(double %f1, double *%base) {
 ; CHECK: aghi %r2, 4096
 ; CHECK: adb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 512
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 512
+  %f2 = load double , double *%ptr
   %res = fadd double %f1, %f2
   ret double %res
 }
@@ -53,8 +54,8 @@ define double @f5(double %f1, double *%base) {
 ; CHECK: aghi %r2, -8
 ; CHECK: adb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 -1
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 -1
+  %f2 = load double , double *%ptr
   %res = fadd double %f1, %f2
   ret double %res
 }
@@ -65,9 +66,9 @@ define double @f6(double %f1, double *%base, i64 %index) {
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: adb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
-  %ptr1 = getelementptr double *%base, i64 %index
-  %ptr2 = getelementptr double *%ptr1, i64 100
-  %f2 = load double *%ptr2
+  %ptr1 = getelementptr double, double *%base, i64 %index
+  %ptr2 = getelementptr double, double *%ptr1, i64 100
+  %f2 = load double , double *%ptr2
   %res = fadd double %f1, %f2
   ret double %res
 }
@@ -76,30 +77,30 @@ define double @f6(double %f1, double *%base, i64 %index) {
 define double @f7(double *%ptr0) {
 ; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
-; CHECK: adb %f0, 160(%r15)
+; CHECK-SCALAR: adb %f0, 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr double *%ptr0, i64 2
-  %ptr2 = getelementptr double *%ptr0, i64 4
-  %ptr3 = getelementptr double *%ptr0, i64 6
-  %ptr4 = getelementptr double *%ptr0, i64 8
-  %ptr5 = getelementptr double *%ptr0, i64 10
-  %ptr6 = getelementptr double *%ptr0, i64 12
-  %ptr7 = getelementptr double *%ptr0, i64 14
-  %ptr8 = getelementptr double *%ptr0, i64 16
-  %ptr9 = getelementptr double *%ptr0, i64 18
-  %ptr10 = getelementptr double *%ptr0, i64 20
+  %ptr1 = getelementptr double, double *%ptr0, i64 2
+  %ptr2 = getelementptr double, double *%ptr0, i64 4
+  %ptr3 = getelementptr double, double *%ptr0, i64 6
+  %ptr4 = getelementptr double, double *%ptr0, i64 8
+  %ptr5 = getelementptr double, double *%ptr0, i64 10
+  %ptr6 = getelementptr double, double *%ptr0, i64 12
+  %ptr7 = getelementptr double, double *%ptr0, i64 14
+  %ptr8 = getelementptr double, double *%ptr0, i64 16
+  %ptr9 = getelementptr double, double *%ptr0, i64 18
+  %ptr10 = getelementptr double, double *%ptr0, i64 20
 
-  %val0 = load double *%ptr0
-  %val1 = load double *%ptr1
-  %val2 = load double *%ptr2
-  %val3 = load double *%ptr3
-  %val4 = load double *%ptr4
-  %val5 = load double *%ptr5
-  %val6 = load double *%ptr6
-  %val7 = load double *%ptr7
-  %val8 = load double *%ptr8
-  %val9 = load double *%ptr9
-  %val10 = load double *%ptr10
+  %val0 = load double , double *%ptr0
+  %val1 = load double , double *%ptr1
+  %val2 = load double , double *%ptr2
+  %val3 = load double , double *%ptr3
+  %val4 = load double , double *%ptr4
+  %val5 = load double , double *%ptr5
+  %val6 = load double , double *%ptr6
+  %val7 = load double , double *%ptr7
+  %val8 = load double , double *%ptr8
+  %val9 = load double , double *%ptr9
+  %val10 = load double , double *%ptr10
 
   %ret = call double @foo()
 
diff --git a/test/CodeGen/SystemZ/fp-add-03.ll b/test/CodeGen/SystemZ/fp-add-03.ll
index cb4042eee472..53342e194edf 100644
--- a/test/CodeGen/SystemZ/fp-add-03.ll
+++ b/test/CodeGen/SystemZ/fp-add-03.ll
@@ -12,7 +12,7 @@ define void @f1(fp128 *%ptr, float %f2) {
 ; CHECK: std %f1, 0(%r2)
 ; CHECK: std %f3, 8(%r2)
 ; CHECK: br %r14
-  %f1 = load fp128 *%ptr
+  %f1 = load fp128 , fp128 *%ptr
   %f2x = fpext float %f2 to fp128
   %sum = fadd fp128 %f1, %f2x
   store fp128 %sum, fp128 *%ptr
diff --git a/test/CodeGen/SystemZ/fp-cmp-01.ll b/test/CodeGen/SystemZ/fp-cmp-01.ll
index d7c0cce9c2a5..ed58103e59a5 100644
--- a/test/CodeGen/SystemZ/fp-cmp-01.ll
+++ b/test/CodeGen/SystemZ/fp-cmp-01.ll
@@ -24,7 +24,7 @@ define i64 @f2(i64 %a, i64 %b, float %f1, float *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %f2 = load float *%ptr
+  %f2 = load float , float *%ptr
   %cond = fcmp oeq float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -37,8 +37,8 @@ define i64 @f3(i64 %a, i64 %b, float %f1, float *%base) {
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1023
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1023
+  %f2 = load float , float *%ptr
   %cond = fcmp oeq float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -53,8 +53,8 @@ define i64 @f4(i64 %a, i64 %b, float %f1, float *%base) {
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1024
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1024
+  %f2 = load float , float *%ptr
   %cond = fcmp oeq float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -68,8 +68,8 @@ define i64 @f5(i64 %a, i64 %b, float %f1, float *%base) {
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 -1
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 -1
+  %f2 = load float , float *%ptr
   %cond = fcmp oeq float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -83,9 +83,9 @@ define i64 @f6(i64 %a, i64 %b, float %f1, float *%base, i64 %index) {
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%base, i64 %index
-  %ptr2 = getelementptr float *%ptr1, i64 100
-  %f2 = load float *%ptr2
+  %ptr1 = getelementptr float, float *%base, i64 %index
+  %ptr2 = getelementptr float, float *%ptr1, i64 100
+  %f2 = load float , float *%ptr2
   %cond = fcmp oeq float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -97,28 +97,28 @@ define float @f7(float *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: ceb {{%f[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%ptr0, i64 2
-  %ptr2 = getelementptr float *%ptr0, i64 4
-  %ptr3 = getelementptr float *%ptr0, i64 6
-  %ptr4 = getelementptr float *%ptr0, i64 8
-  %ptr5 = getelementptr float *%ptr0, i64 10
-  %ptr6 = getelementptr float *%ptr0, i64 12
-  %ptr7 = getelementptr float *%ptr0, i64 14
-  %ptr8 = getelementptr float *%ptr0, i64 16
-  %ptr9 = getelementptr float *%ptr0, i64 18
-  %ptr10 = getelementptr float *%ptr0, i64 20
+  %ptr1 = getelementptr float, float *%ptr0, i64 2
+  %ptr2 = getelementptr float, float *%ptr0, i64 4
+  %ptr3 = getelementptr float, float *%ptr0, i64 6
+  %ptr4 = getelementptr float, float *%ptr0, i64 8
+  %ptr5 = getelementptr float, float *%ptr0, i64 10
+  %ptr6 = getelementptr float, float *%ptr0, i64 12
+  %ptr7 = getelementptr float, float *%ptr0, i64 14
+  %ptr8 = getelementptr float, float *%ptr0, i64 16
+  %ptr9 = getelementptr float, float *%ptr0, i64 18
+  %ptr10 = getelementptr float, float *%ptr0, i64 20
 
-  %val0 = load float *%ptr0
-  %val1 = load float *%ptr1
-  %val2 = load float *%ptr2
-  %val3 = load float *%ptr3
-  %val4 = load float *%ptr4
-  %val5 = load float *%ptr5
-  %val6 = load float *%ptr6
-  %val7 = load float *%ptr7
-  %val8 = load float *%ptr8
-  %val9 = load float *%ptr9
-  %val10 = load float *%ptr10
+  %val0 = load float , float *%ptr0
+  %val1 = load float , float *%ptr1
+  %val2 = load float , float *%ptr2
+  %val3 = load float , float *%ptr3
+  %val4 = load float , float *%ptr4
+  %val5 = load float , float *%ptr5
+  %val6 = load float , float *%ptr6
+  %val7 = load float , float *%ptr7
+  %val8 = load float , float *%ptr8
+  %val9 = load float , float *%ptr9
+  %val10 = load float , float *%ptr10
 
   %ret = call float @foo()
 
@@ -169,7 +169,7 @@ define i64 @f9(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-NEXT: je {{\.L.*}}
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %f1 = load float *%ptr
+  %f1 = load float , float *%ptr
   %cond = fcmp oeq float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -182,7 +182,7 @@ define i64 @f10(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-NEXT: jlh {{\.L.*}}
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %f1 = load float *%ptr
+  %f1 = load float , float *%ptr
   %cond = fcmp one float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -195,7 +195,7 @@ define i64 @f11(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %f1 = load float *%ptr
+  %f1 = load float , float *%ptr
   %cond = fcmp olt float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -208,7 +208,7 @@ define i64 @f12(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-NEXT: jhe {{\.L.*}}
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %f1 = load float *%ptr
+  %f1 = load float , float *%ptr
   %cond = fcmp ole float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -221,7 +221,7 @@ define i64 @f13(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-NEXT: jle {{\.L.*}}
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %f1 = load float *%ptr
+  %f1 = load float , float *%ptr
   %cond = fcmp oge float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -234,7 +234,7 @@ define i64 @f14(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-NEXT: jl {{\.L.*}}
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %f1 = load float *%ptr
+  %f1 = load float , float *%ptr
   %cond = fcmp ogt float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -247,7 +247,7 @@ define i64 @f15(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-NEXT: jnlh {{\.L.*}}
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %f1 = load float *%ptr
+  %f1 = load float , float *%ptr
   %cond = fcmp ueq float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -260,7 +260,7 @@ define i64 @f16(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-NEXT: jne {{\.L.*}}
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %f1 = load float *%ptr
+  %f1 = load float , float *%ptr
   %cond = fcmp une float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -273,7 +273,7 @@ define i64 @f17(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-NEXT: jnle {{\.L.*}}
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %f1 = load float *%ptr
+  %f1 = load float , float *%ptr
   %cond = fcmp ult float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -286,7 +286,7 @@ define i64 @f18(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-NEXT: jnl {{\.L.*}}
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %f1 = load float *%ptr
+  %f1 = load float , float *%ptr
   %cond = fcmp ule float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -299,7 +299,7 @@ define i64 @f19(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-NEXT: jnh {{\.L.*}}
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %f1 = load float *%ptr
+  %f1 = load float , float *%ptr
   %cond = fcmp uge float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -312,7 +312,7 @@ define i64 @f20(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-NEXT: jnhe {{\.L.*}}
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %f1 = load float *%ptr
+  %f1 = load float , float *%ptr
   %cond = fcmp ugt float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
diff --git a/test/CodeGen/SystemZ/fp-cmp-02.ll b/test/CodeGen/SystemZ/fp-cmp-02.ll
index c61f04ed244e..94a256777c75 100644
--- a/test/CodeGen/SystemZ/fp-cmp-02.ll
+++ b/test/CodeGen/SystemZ/fp-cmp-02.ll
@@ -1,7 +1,10 @@
 ; Test 64-bit floating-point comparison.  The tests assume a z10 implementation
 ; of select, using conditional branches rather than LOCGR.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-VECTOR %s
 
 declare double @foo()
 
@@ -9,8 +12,9 @@ declare double @foo()
 define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) {
 ; CHECK-LABEL: f1:
 ; CHECK: cdbr %f0, %f2
-; CHECK-NEXT: je
-; CHECK: lgr %r2, %r3
+; CHECK-SCALAR-NEXT: je
+; CHECK-SCALAR: lgr %r2, %r3
+; CHECK-VECTOR-NEXT: locgrne %r2, %r3
 ; CHECK: br %r14
   %cond = fcmp oeq double %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
@@ -21,10 +25,11 @@ define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) {
 define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: cdb %f0, 0(%r4)
-; CHECK-NEXT: je
-; CHECK: lgr %r2, %r3
+; CHECK-SCALAR-NEXT: je
+; CHECK-SCALAR: lgr %r2, %r3
+; CHECK-VECTOR-NEXT: locgrne %r2, %r3
 ; CHECK: br %r14
-  %f2 = load double *%ptr
+  %f2 = load double , double *%ptr
   %cond = fcmp oeq double %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -34,11 +39,12 @@ define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) {
 define i64 @f3(i64 %a, i64 %b, double %f1, double *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: cdb %f0, 4088(%r4)
-; CHECK-NEXT: je
-; CHECK: lgr %r2, %r3
+; CHECK-SCALAR-NEXT: je
+; CHECK-SCALAR: lgr %r2, %r3
+; CHECK-VECTOR-NEXT: locgrne %r2, %r3
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 511
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 511
+  %f2 = load double , double *%ptr
   %cond = fcmp oeq double %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -50,11 +56,12 @@ define i64 @f4(i64 %a, i64 %b, double %f1, double *%base) {
 ; CHECK-LABEL: f4:
 ; CHECK: aghi %r4, 4096
 ; CHECK: cdb %f0, 0(%r4)
-; CHECK-NEXT: je
-; CHECK: lgr %r2, %r3
+; CHECK-SCALAR-NEXT: je
+; CHECK-SCALAR: lgr %r2, %r3
+; CHECK-VECTOR-NEXT: locgrne %r2, %r3
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 512
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 512
+  %f2 = load double , double *%ptr
   %cond = fcmp oeq double %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -65,11 +72,12 @@ define i64 @f5(i64 %a, i64 %b, double %f1, double *%base) {
 ; CHECK-LABEL: f5:
 ; CHECK: aghi %r4, -8
 ; CHECK: cdb %f0, 0(%r4)
-; CHECK-NEXT: je
-; CHECK: lgr %r2, %r3
+; CHECK-SCALAR-NEXT: je
+; CHECK-SCALAR: lgr %r2, %r3
+; CHECK-VECTOR-NEXT: locgrne %r2, %r3
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 -1
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 -1
+  %f2 = load double , double *%ptr
   %cond = fcmp oeq double %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -80,12 +88,13 @@ define i64 @f6(i64 %a, i64 %b, double %f1, double *%base, i64 %index) {
 ; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r5, 3
 ; CHECK: cdb %f0, 800(%r1,%r4)
-; CHECK-NEXT: je
-; CHECK: lgr %r2, %r3
+; CHECK-SCALAR-NEXT: je
+; CHECK-SCALAR: lgr %r2, %r3
+; CHECK-VECTOR-NEXT: locgrne %r2, %r3
 ; CHECK: br %r14
-  %ptr1 = getelementptr double *%base, i64 %index
-  %ptr2 = getelementptr double *%ptr1, i64 100
-  %f2 = load double *%ptr2
+  %ptr1 = getelementptr double, double *%base, i64 %index
+  %ptr2 = getelementptr double, double *%ptr1, i64 100
+  %f2 = load double , double *%ptr2
   %cond = fcmp oeq double %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -95,30 +104,30 @@ define i64 @f6(i64 %a, i64 %b, double %f1, double *%base, i64 %index) {
 define double @f7(double *%ptr0) {
 ; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
-; CHECK: cdb {{%f[0-9]+}}, 160(%r15)
+; CHECK-SCALAR: cdb {{%f[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr double *%ptr0, i64 2
-  %ptr2 = getelementptr double *%ptr0, i64 4
-  %ptr3 = getelementptr double *%ptr0, i64 6
-  %ptr4 = getelementptr double *%ptr0, i64 8
-  %ptr5 = getelementptr double *%ptr0, i64 10
-  %ptr6 = getelementptr double *%ptr0, i64 12
-  %ptr7 = getelementptr double *%ptr0, i64 14
-  %ptr8 = getelementptr double *%ptr0, i64 16
-  %ptr9 = getelementptr double *%ptr0, i64 18
-  %ptr10 = getelementptr double *%ptr0, i64 20
+  %ptr1 = getelementptr double, double *%ptr0, i64 2
+  %ptr2 = getelementptr double, double *%ptr0, i64 4
+  %ptr3 = getelementptr double, double *%ptr0, i64 6
+  %ptr4 = getelementptr double, double *%ptr0, i64 8
+  %ptr5 = getelementptr double, double *%ptr0, i64 10
+  %ptr6 = getelementptr double, double *%ptr0, i64 12
+  %ptr7 = getelementptr double, double *%ptr0, i64 14
+  %ptr8 = getelementptr double, double *%ptr0, i64 16
+  %ptr9 = getelementptr double, double *%ptr0, i64 18
+  %ptr10 = getelementptr double, double *%ptr0, i64 20
 
-  %val0 = load double *%ptr0
-  %val1 = load double *%ptr1
-  %val2 = load double *%ptr2
-  %val3 = load double *%ptr3
-  %val4 = load double *%ptr4
-  %val5 = load double *%ptr5
-  %val6 = load double *%ptr6
-  %val7 = load double *%ptr7
-  %val8 = load double *%ptr8
-  %val9 = load double *%ptr9
-  %val10 = load double *%ptr10
+  %val0 = load double , double *%ptr0
+  %val1 = load double , double *%ptr1
+  %val2 = load double , double *%ptr2
+  %val3 = load double , double *%ptr3
+  %val4 = load double , double *%ptr4
+  %val5 = load double , double *%ptr5
+  %val6 = load double , double *%ptr6
+  %val7 = load double , double *%ptr7
+  %val8 = load double , double *%ptr8
+  %val9 = load double , double *%ptr9
+  %val10 = load double , double *%ptr10
 
   %ret = call double @foo()
 
@@ -152,9 +161,12 @@ define double @f7(double *%ptr0) {
 ; Check comparison with zero.
 define i64 @f8(i64 %a, i64 %b, double %f) {
 ; CHECK-LABEL: f8:
-; CHECK: ltdbr %f0, %f0
-; CHECK-NEXT: je
-; CHECK: lgr %r2, %r3
+; CHECK-SCALAR: ltdbr %f0, %f0
+; CHECK-SCALAR-NEXT: je
+; CHECK-SCALAR: lgr %r2, %r3
+; CHECK-VECTOR: lzdr %f1
+; CHECK-VECTOR-NEXT: cdbr %f0, %f1
+; CHECK-VECTOR-NEXT: locgrne %r2, %r3
 ; CHECK: br %r14
   %cond = fcmp oeq double %f, 0.0
   %res = select i1 %cond, i64 %a, i64 %b
@@ -165,10 +177,11 @@ define i64 @f8(i64 %a, i64 %b, double %f) {
 define i64 @f9(i64 %a, i64 %b, double %f2, double *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: cdb %f0, 0(%r4)
-; CHECK-NEXT: jl {{\.L.*}}
-; CHECK: lgr %r2, %r3
+; CHECK-SCALAR-NEXT: jl
+; CHECK-SCALAR: lgr %r2, %r3
+; CHECK-VECTOR-NEXT: locgrnl %r2, %r3
 ; CHECK: br %r14
-  %f1 = load double *%ptr
+  %f1 = load double , double *%ptr
   %cond = fcmp ogt double %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
diff --git a/test/CodeGen/SystemZ/fp-cmp-03.ll b/test/CodeGen/SystemZ/fp-cmp-03.ll
index e777d00c9687..862c5e9b65b8 100644
--- a/test/CodeGen/SystemZ/fp-cmp-03.ll
+++ b/test/CodeGen/SystemZ/fp-cmp-03.ll
@@ -14,7 +14,7 @@ define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) {
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f2x = fpext float %f2 to fp128
-  %f1 = load fp128 *%ptr
+  %f1 = load fp128 , fp128 *%ptr
   %cond = fcmp oeq fp128 %f1, %f2x
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
@@ -29,7 +29,7 @@ define i64 @f2(i64 %a, i64 %b, fp128 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
-  %f = load fp128 *%ptr
+  %f = load fp128 , fp128 *%ptr
   %cond = fcmp oeq fp128 %f, 0xL00000000000000000000000000000000
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
diff --git a/test/CodeGen/SystemZ/fp-cmp-04.ll b/test/CodeGen/SystemZ/fp-cmp-04.ll
index 1637ccb0791b..05c6dfe7e8e4 100644
--- a/test/CodeGen/SystemZ/fp-cmp-04.ll
+++ b/test/CodeGen/SystemZ/fp-cmp-04.ll
@@ -88,7 +88,7 @@ define float @f5(float %a, float %b, float *%dest) {
 ; CHECK-NEXT: jnhe .L{{.*}}
 ; CHECK: br %r14
 entry:
-  %cur = load float *%dest
+  %cur = load float , float *%dest
   %res = fsub float %a, %cur
   %cmp = fcmp ult float %res, 0.0
   br i1 %cmp, label %exit, label %store
@@ -284,8 +284,8 @@ define void @f14(fp128 *%ptr1, fp128 *%ptr2) {
 ; CHECK-NEXT: jl .L{{.*}}
 ; CHECK: br %r14
 entry:
-  %val1 = load fp128 *%ptr1
-  %val2 = load fp128 *%ptr2
+  %val1 = load fp128 , fp128 *%ptr1
+  %val2 = load fp128 , fp128 *%ptr2
   %div = fdiv fp128 %val1, %val2
   store fp128 %div, fp128 *%ptr1
   %mul = fmul fp128 %val1, %val2
diff --git a/test/CodeGen/SystemZ/fp-conv-01.ll b/test/CodeGen/SystemZ/fp-conv-01.ll
index 49ed43bce51c..06740ed4b4a6 100644
--- a/test/CodeGen/SystemZ/fp-conv-01.ll
+++ b/test/CodeGen/SystemZ/fp-conv-01.ll
@@ -1,11 +1,15 @@
 ; Test floating-point truncations.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-VECTOR %s
 
 ; Test f64->f32.
 define float @f1(double %d1, double %d2) {
 ; CHECK-LABEL: f1:
-; CHECK: ledbr %f0, %f2
+; CHECK-SCALAR: ledbr %f0, %f2
+; CHECK-VECTOR: ledbra %f0, 0, %f2, 0
 ; CHECK: br %r14
   %res = fptrunc double %d2 to float
   ret float %res
@@ -16,7 +20,7 @@ define float @f2(fp128 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: lexbr %f0, %f0
 ; CHECK: br %r14
-  %val = load fp128 *%ptr
+  %val = load fp128 , fp128 *%ptr
   %res = fptrunc fp128 %val to float
   ret float %res
 }
@@ -29,7 +33,7 @@ define void @f3(float *%dst, fp128 *%ptr, float %d1, float %d2) {
 ; CHECK: aebr %f1, %f2
 ; CHECK: ste %f1, 0(%r2)
 ; CHECK: br %r14
-  %val = load fp128 *%ptr
+  %val = load fp128 , fp128 *%ptr
   %conv = fptrunc fp128 %val to float
   %res = fadd float %conv, %d2
   store float %res, float *%dst
@@ -41,7 +45,7 @@ define double @f4(fp128 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: ldxbr %f0, %f0
 ; CHECK: br %r14
-  %val = load fp128 *%ptr
+  %val = load fp128 , fp128 *%ptr
   %res = fptrunc fp128 %val to double
   ret double %res
 }
@@ -50,10 +54,12 @@ define double @f4(fp128 *%ptr) {
 define void @f5(double *%dst, fp128 *%ptr, double %d1, double %d2) {
 ; CHECK-LABEL: f5:
 ; CHECK: ldxbr %f1, %f1
-; CHECK: adbr %f1, %f2
-; CHECK: std %f1, 0(%r2)
+; CHECK-SCALAR: adbr %f1, %f2
+; CHECK-SCALAR: std %f1, 0(%r2)
+; CHECK-VECTOR: wfadb [[REG:%f[0-9]+]], %f1, %f2
+; CHECK-VECTOR: std [[REG]], 0(%r2)
 ; CHECK: br %r14
-  %val = load fp128 *%ptr
+  %val = load fp128 , fp128 *%ptr
   %conv = fptrunc fp128 %val to double
   %res = fadd double %conv, %d2
   store double %res, double *%dst
diff --git a/test/CodeGen/SystemZ/fp-conv-02.ll b/test/CodeGen/SystemZ/fp-conv-02.ll
index 93fb7c8d4d92..be32bfe7ba9a 100644
--- a/test/CodeGen/SystemZ/fp-conv-02.ll
+++ b/test/CodeGen/SystemZ/fp-conv-02.ll
@@ -1,6 +1,8 @@
 ; Test extensions of f32 to f64.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 ; Check register extension.
 define double @f1(float %val) {
@@ -16,7 +18,7 @@ define double @f2(float *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: ldeb %f0, 0(%r2)
 ; CHECK: br %r14
-  %val = load float *%ptr
+  %val = load float , float *%ptr
   %res = fpext float %val to double
   ret double %res
 }
@@ -26,8 +28,8 @@ define double @f3(float *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: ldeb %f0, 4092(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1023
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1023
+  %val = load float , float *%ptr
   %res = fpext float %val to double
   ret double %res
 }
@@ -39,8 +41,8 @@ define double @f4(float *%base) {
 ; CHECK: aghi %r2, 4096
 ; CHECK: ldeb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1024
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1024
+  %val = load float , float *%ptr
   %res = fpext float %val to double
   ret double %res
 }
@@ -51,8 +53,8 @@ define double @f5(float *%base) {
 ; CHECK: aghi %r2, -4
 ; CHECK: ldeb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 -1
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 -1
+  %val = load float , float *%ptr
   %res = fpext float %val to double
   ret double %res
 }
@@ -63,9 +65,9 @@ define double @f6(float *%base, i64 %index) {
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: ldeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%base, i64 %index
-  %ptr2 = getelementptr float *%ptr1, i64 100
-  %val = load float *%ptr2
+  %ptr1 = getelementptr float, float *%base, i64 %index
+  %ptr2 = getelementptr float, float *%ptr1, i64 100
+  %val = load float , float *%ptr2
   %res = fpext float %val to double
   ret double %res
 }
@@ -74,25 +76,25 @@ define double @f6(float *%base, i64 %index) {
 ; to use LDEB if possible.
 define void @f7(double *%ptr1, float *%ptr2) {
 ; CHECK-LABEL: f7:
-; CHECK: ldeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
+; CHECK-SCALAR: ldeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile float *%ptr2
-  %val1 = load volatile float *%ptr2
-  %val2 = load volatile float *%ptr2
-  %val3 = load volatile float *%ptr2
-  %val4 = load volatile float *%ptr2
-  %val5 = load volatile float *%ptr2
-  %val6 = load volatile float *%ptr2
-  %val7 = load volatile float *%ptr2
-  %val8 = load volatile float *%ptr2
-  %val9 = load volatile float *%ptr2
-  %val10 = load volatile float *%ptr2
-  %val11 = load volatile float *%ptr2
-  %val12 = load volatile float *%ptr2
-  %val13 = load volatile float *%ptr2
-  %val14 = load volatile float *%ptr2
-  %val15 = load volatile float *%ptr2
-  %val16 = load volatile float *%ptr2
+  %val0 = load volatile float , float *%ptr2
+  %val1 = load volatile float , float *%ptr2
+  %val2 = load volatile float , float *%ptr2
+  %val3 = load volatile float , float *%ptr2
+  %val4 = load volatile float , float *%ptr2
+  %val5 = load volatile float , float *%ptr2
+  %val6 = load volatile float , float *%ptr2
+  %val7 = load volatile float , float *%ptr2
+  %val8 = load volatile float , float *%ptr2
+  %val9 = load volatile float , float *%ptr2
+  %val10 = load volatile float , float *%ptr2
+  %val11 = load volatile float , float *%ptr2
+  %val12 = load volatile float , float *%ptr2
+  %val13 = load volatile float , float *%ptr2
+  %val14 = load volatile float , float *%ptr2
+  %val15 = load volatile float , float *%ptr2
+  %val16 = load volatile float , float *%ptr2
 
   %ext0 = fpext float %val0 to double
   %ext1 = fpext float %val1 to double
diff --git a/test/CodeGen/SystemZ/fp-conv-03.ll b/test/CodeGen/SystemZ/fp-conv-03.ll
index d42ce6650aaf..bb14e610f720 100644
--- a/test/CodeGen/SystemZ/fp-conv-03.ll
+++ b/test/CodeGen/SystemZ/fp-conv-03.ll
@@ -21,7 +21,7 @@ define void @f2(fp128 *%dst, float *%ptr) {
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
-  %val = load float *%ptr
+  %val = load float , float *%ptr
   %res = fpext float %val to fp128
   store fp128 %res, fp128 *%dst
   ret void
@@ -34,8 +34,8 @@ define void @f3(fp128 *%dst, float *%base) {
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1023
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1023
+  %val = load float , float *%ptr
   %res = fpext float %val to fp128
   store fp128 %res, fp128 *%dst
   ret void
@@ -50,8 +50,8 @@ define void @f4(fp128 *%dst, float *%base) {
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1024
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1024
+  %val = load float , float *%ptr
   %res = fpext float %val to fp128
   store fp128 %res, fp128 *%dst
   ret void
@@ -65,8 +65,8 @@ define void @f5(fp128 *%dst, float *%base) {
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 -1
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 -1
+  %val = load float , float *%ptr
   %res = fpext float %val to fp128
   store fp128 %res, fp128 *%dst
   ret void
@@ -80,9 +80,9 @@ define void @f6(fp128 *%dst, float *%base, i64 %index) {
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%base, i64 %index
-  %ptr2 = getelementptr float *%ptr1, i64 100
-  %val = load float *%ptr2
+  %ptr1 = getelementptr float, float *%base, i64 %index
+  %ptr2 = getelementptr float, float *%ptr1, i64 100
+  %val = load float , float *%ptr2
   %res = fpext float %val to fp128
   store fp128 %res, fp128 *%dst
   ret void
@@ -94,23 +94,23 @@ define void @f7(fp128 *%ptr1, float *%ptr2) {
 ; CHECK-LABEL: f7:
 ; CHECK: lxeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile float *%ptr2
-  %val1 = load volatile float *%ptr2
-  %val2 = load volatile float *%ptr2
-  %val3 = load volatile float *%ptr2
-  %val4 = load volatile float *%ptr2
-  %val5 = load volatile float *%ptr2
-  %val6 = load volatile float *%ptr2
-  %val7 = load volatile float *%ptr2
-  %val8 = load volatile float *%ptr2
-  %val9 = load volatile float *%ptr2
-  %val10 = load volatile float *%ptr2
-  %val11 = load volatile float *%ptr2
-  %val12 = load volatile float *%ptr2
-  %val13 = load volatile float *%ptr2
-  %val14 = load volatile float *%ptr2
-  %val15 = load volatile float *%ptr2
-  %val16 = load volatile float *%ptr2
+  %val0 = load volatile float , float *%ptr2
+  %val1 = load volatile float , float *%ptr2
+  %val2 = load volatile float , float *%ptr2
+  %val3 = load volatile float , float *%ptr2
+  %val4 = load volatile float , float *%ptr2
+  %val5 = load volatile float , float *%ptr2
+  %val6 = load volatile float , float *%ptr2
+  %val7 = load volatile float , float *%ptr2
+  %val8 = load volatile float , float *%ptr2
+  %val9 = load volatile float , float *%ptr2
+  %val10 = load volatile float , float *%ptr2
+  %val11 = load volatile float , float *%ptr2
+  %val12 = load volatile float , float *%ptr2
+  %val13 = load volatile float , float *%ptr2
+  %val14 = load volatile float , float *%ptr2
+  %val15 = load volatile float , float *%ptr2
+  %val16 = load volatile float , float *%ptr2
 
   %ext0 = fpext float %val0 to fp128
   %ext1 = fpext float %val1 to fp128
diff --git a/test/CodeGen/SystemZ/fp-conv-04.ll b/test/CodeGen/SystemZ/fp-conv-04.ll
index 518d6c28d867..cfcb98aaa70a 100644
--- a/test/CodeGen/SystemZ/fp-conv-04.ll
+++ b/test/CodeGen/SystemZ/fp-conv-04.ll
@@ -21,7 +21,7 @@ define void @f2(fp128 *%dst, double *%ptr) {
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
-  %val = load double *%ptr
+  %val = load double , double *%ptr
   %res = fpext double %val to fp128
   store fp128 %res, fp128 *%dst
   ret void
@@ -34,8 +34,8 @@ define void @f3(fp128 *%dst, double *%base) {
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 511
-  %val = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 511
+  %val = load double , double *%ptr
   %res = fpext double %val to fp128
   store fp128 %res, fp128 *%dst
   ret void
@@ -50,8 +50,8 @@ define void @f4(fp128 *%dst, double *%base) {
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 512
-  %val = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 512
+  %val = load double , double *%ptr
   %res = fpext double %val to fp128
   store fp128 %res, fp128 *%dst
   ret void
@@ -65,8 +65,8 @@ define void @f5(fp128 *%dst, double *%base) {
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 -1
-  %val = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 -1
+  %val = load double , double *%ptr
   %res = fpext double %val to fp128
   store fp128 %res, fp128 *%dst
   ret void
@@ -80,9 +80,9 @@ define void @f6(fp128 *%dst, double *%base, i64 %index) {
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
-  %ptr1 = getelementptr double *%base, i64 %index
-  %ptr2 = getelementptr double *%ptr1, i64 100
-  %val = load double *%ptr2
+  %ptr1 = getelementptr double, double *%base, i64 %index
+  %ptr2 = getelementptr double, double *%ptr1, i64 100
+  %val = load double , double *%ptr2
   %res = fpext double %val to fp128
   store fp128 %res, fp128 *%dst
   ret void
@@ -94,23 +94,23 @@ define void @f7(fp128 *%ptr1, double *%ptr2) {
 ; CHECK-LABEL: f7:
 ; CHECK: lxdb {{%f[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile double *%ptr2
-  %val1 = load volatile double *%ptr2
-  %val2 = load volatile double *%ptr2
-  %val3 = load volatile double *%ptr2
-  %val4 = load volatile double *%ptr2
-  %val5 = load volatile double *%ptr2
-  %val6 = load volatile double *%ptr2
-  %val7 = load volatile double *%ptr2
-  %val8 = load volatile double *%ptr2
-  %val9 = load volatile double *%ptr2
-  %val10 = load volatile double *%ptr2
-  %val11 = load volatile double *%ptr2
-  %val12 = load volatile double *%ptr2
-  %val13 = load volatile double *%ptr2
-  %val14 = load volatile double *%ptr2
-  %val15 = load volatile double *%ptr2
-  %val16 = load volatile double *%ptr2
+  %val0 = load volatile double , double *%ptr2
+  %val1 = load volatile double , double *%ptr2
+  %val2 = load volatile double , double *%ptr2
+  %val3 = load volatile double , double *%ptr2
+  %val4 = load volatile double , double *%ptr2
+  %val5 = load volatile double , double *%ptr2
+  %val6 = load volatile double , double *%ptr2
+  %val7 = load volatile double , double *%ptr2
+  %val8 = load volatile double , double *%ptr2
+  %val9 = load volatile double , double *%ptr2
+  %val10 = load volatile double , double *%ptr2
+  %val11 = load volatile double , double *%ptr2
+  %val12 = load volatile double , double *%ptr2
+  %val13 = load volatile double , double *%ptr2
+  %val14 = load volatile double , double *%ptr2
+  %val15 = load volatile double , double *%ptr2
+  %val16 = load volatile double , double *%ptr2
 
   %ext0 = fpext double %val0 to fp128
   %ext1 = fpext double %val1 to fp128
diff --git a/test/CodeGen/SystemZ/fp-conv-09.ll b/test/CodeGen/SystemZ/fp-conv-09.ll
index 6aee73644a16..21b809d40e29 100644
--- a/test/CodeGen/SystemZ/fp-conv-09.ll
+++ b/test/CodeGen/SystemZ/fp-conv-09.ll
@@ -27,7 +27,7 @@ define i32 @f3(fp128 *%src) {
 ; CHECK: ld %f2, 8(%r2)
 ; CHECK: cfxbr %r2, 5, %f0
 ; CHECK: br %r14
-  %f = load fp128 *%src
+  %f = load fp128 , fp128 *%src
   %conv = fptosi fp128 %f to i32
   ret i32 %conv
 }
diff --git a/test/CodeGen/SystemZ/fp-conv-10.ll b/test/CodeGen/SystemZ/fp-conv-10.ll
index b8155ed067da..cfbe0b939747 100644
--- a/test/CodeGen/SystemZ/fp-conv-10.ll
+++ b/test/CodeGen/SystemZ/fp-conv-10.ll
@@ -39,7 +39,7 @@ define i32 @f3(fp128 *%src) {
 ; CHECK: cfxbr
 ; CHECK: xilf
 ; CHECK: br %r14
-  %f = load fp128 *%src
+  %f = load fp128 , fp128 *%src
   %conv = fptoui fp128 %f to i32
   ret i32 %conv
 }
diff --git a/test/CodeGen/SystemZ/fp-conv-11.ll b/test/CodeGen/SystemZ/fp-conv-11.ll
index 46f4cb3a6d89..eb996cb3bb1b 100644
--- a/test/CodeGen/SystemZ/fp-conv-11.ll
+++ b/test/CodeGen/SystemZ/fp-conv-11.ll
@@ -27,7 +27,7 @@ define i64 @f3(fp128 *%src) {
 ; CHECK: ld %f2, 8(%r2)
 ; CHECK: cgxbr %r2, 5, %f0
 ; CHECK: br %r14
-  %f = load fp128 *%src
+  %f = load fp128 , fp128 *%src
   %conv = fptosi fp128 %f to i64
   ret i64 %conv
 }
diff --git a/test/CodeGen/SystemZ/fp-conv-12.ll b/test/CodeGen/SystemZ/fp-conv-12.ll
index 770c9407a0af..28a521605a95 100644
--- a/test/CodeGen/SystemZ/fp-conv-12.ll
+++ b/test/CodeGen/SystemZ/fp-conv-12.ll
@@ -38,7 +38,7 @@ define i64 @f3(fp128 *%src) {
 ; CHECK: cgxbr
 ; CHECK: xihf
 ; CHECK: br %r14
-  %f = load fp128 *%src
+  %f = load fp128 , fp128 *%src
   %conv = fptoui fp128 %f to i64
   ret i64 %conv
 }
diff --git a/test/CodeGen/SystemZ/fp-conv-14.ll b/test/CodeGen/SystemZ/fp-conv-14.ll
index e926e9bb31f5..e4f0a27022e8 100644
--- a/test/CodeGen/SystemZ/fp-conv-14.ll
+++ b/test/CodeGen/SystemZ/fp-conv-14.ll
@@ -27,7 +27,7 @@ define i32 @f3(fp128 *%src) {
 ; CHECK-DAG: ld %f2, 8(%r2)
 ; CHECK: clfxbr %r2, 5, %f0, 0
 ; CHECK: br %r14
-  %f = load fp128 *%src
+  %f = load fp128 , fp128 *%src
   %conv = fptoui fp128 %f to i32
   ret i32 %conv
 }
@@ -57,7 +57,7 @@ define i64 @f6(fp128 *%src) {
 ; CHECK-DAG: ld %f2, 8(%r2)
 ; CHECK: clgxbr %r2, 5, %f0, 0
 ; CHECK: br %r14
-  %f = load fp128 *%src
+  %f = load fp128 , fp128 *%src
   %conv = fptoui fp128 %f to i64
   ret i64 %conv
 }
diff --git a/test/CodeGen/SystemZ/fp-copysign-01.ll b/test/CodeGen/SystemZ/fp-copysign-01.ll
index 50177e5f41bf..57ad76fcbb2a 100644
--- a/test/CodeGen/SystemZ/fp-copysign-01.ll
+++ b/test/CodeGen/SystemZ/fp-copysign-01.ll
@@ -35,7 +35,7 @@ define float @f3(float %a, fp128 *%bptr) {
 ; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2)
 ; CHECK: cpsdr %f0, %f0, [[BHIGH]]
 ; CHECK: br %r14
-  %bl = load volatile fp128 *%bptr
+  %bl = load volatile fp128 , fp128 *%bptr
   %b = fptrunc fp128 %bl to float
   %res = call float @copysignf(float %a, float %b) readnone
   ret float %res
@@ -69,7 +69,7 @@ define double @f6(double %a, fp128 *%bptr) {
 ; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2)
 ; CHECK: cpsdr %f0, %f0, [[BHIGH]]
 ; CHECK: br %r14
-  %bl = load volatile fp128 *%bptr
+  %bl = load volatile fp128 , fp128 *%bptr
   %b = fptrunc fp128 %bl to double
   %res = call double @copysign(double %a, double %b) readnone
   ret double %res
@@ -86,7 +86,7 @@ define void @f7(fp128 *%cptr, fp128 *%aptr, float %bf) {
 ; CHECK: std [[AHIGH]], 0(%r2)
 ; CHECK: std [[ALOW]], 8(%r2)
 ; CHECK: br %r14
-  %a = load volatile fp128 *%aptr
+  %a = load volatile fp128 , fp128 *%aptr
   %b = fpext float %bf to fp128
   %c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone
   store fp128 %c, fp128 *%cptr
@@ -102,7 +102,7 @@ define void @f8(fp128 *%cptr, fp128 *%aptr, double %bd) {
 ; CHECK: std [[AHIGH]], 0(%r2)
 ; CHECK: std [[ALOW]], 8(%r2)
 ; CHECK: br %r14
-  %a = load volatile fp128 *%aptr
+  %a = load volatile fp128 , fp128 *%aptr
   %b = fpext double %bd to fp128
   %c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone
   store fp128 %c, fp128 *%cptr
@@ -120,8 +120,8 @@ define void @f9(fp128 *%cptr, fp128 *%aptr, fp128 *%bptr) {
 ; CHECK: std [[AHIGH]], 0(%r2)
 ; CHECK: std [[ALOW]], 8(%r2)
 ; CHECK: br %r14
-  %a = load volatile fp128 *%aptr
-  %b = load volatile fp128 *%bptr
+  %a = load volatile fp128 , fp128 *%aptr
+  %b = load volatile fp128 , fp128 *%bptr
   %c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone
   store fp128 %c, fp128 *%cptr
   ret void
diff --git a/test/CodeGen/SystemZ/fp-div-01.ll b/test/CodeGen/SystemZ/fp-div-01.ll
index 1b99463327b4..0791e8db93f8 100644
--- a/test/CodeGen/SystemZ/fp-div-01.ll
+++ b/test/CodeGen/SystemZ/fp-div-01.ll
@@ -18,7 +18,7 @@ define float @f2(float %f1, float *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: deb %f0, 0(%r2)
 ; CHECK: br %r14
-  %f2 = load float *%ptr
+  %f2 = load float , float *%ptr
   %res = fdiv float %f1, %f2
   ret float %res
 }
@@ -28,8 +28,8 @@ define float @f3(float %f1, float *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: deb %f0, 4092(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1023
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1023
+  %f2 = load float , float *%ptr
   %res = fdiv float %f1, %f2
   ret float %res
 }
@@ -41,8 +41,8 @@ define float @f4(float %f1, float *%base) {
 ; CHECK: aghi %r2, 4096
 ; CHECK: deb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1024
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1024
+  %f2 = load float , float *%ptr
   %res = fdiv float %f1, %f2
   ret float %res
 }
@@ -53,8 +53,8 @@ define float @f5(float %f1, float *%base) {
 ; CHECK: aghi %r2, -4
 ; CHECK: deb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 -1
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 -1
+  %f2 = load float , float *%ptr
   %res = fdiv float %f1, %f2
   ret float %res
 }
@@ -65,9 +65,9 @@ define float @f6(float %f1, float *%base, i64 %index) {
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: deb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%base, i64 %index
-  %ptr2 = getelementptr float *%ptr1, i64 100
-  %f2 = load float *%ptr2
+  %ptr1 = getelementptr float, float *%base, i64 %index
+  %ptr2 = getelementptr float, float *%ptr1, i64 100
+  %f2 = load float , float *%ptr2
   %res = fdiv float %f1, %f2
   ret float %res
 }
@@ -78,28 +78,28 @@ define float @f7(float *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: deb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%ptr0, i64 2
-  %ptr2 = getelementptr float *%ptr0, i64 4
-  %ptr3 = getelementptr float *%ptr0, i64 6
-  %ptr4 = getelementptr float *%ptr0, i64 8
-  %ptr5 = getelementptr float *%ptr0, i64 10
-  %ptr6 = getelementptr float *%ptr0, i64 12
-  %ptr7 = getelementptr float *%ptr0, i64 14
-  %ptr8 = getelementptr float *%ptr0, i64 16
-  %ptr9 = getelementptr float *%ptr0, i64 18
-  %ptr10 = getelementptr float *%ptr0, i64 20
+  %ptr1 = getelementptr float, float *%ptr0, i64 2
+  %ptr2 = getelementptr float, float *%ptr0, i64 4
+  %ptr3 = getelementptr float, float *%ptr0, i64 6
+  %ptr4 = getelementptr float, float *%ptr0, i64 8
+  %ptr5 = getelementptr float, float *%ptr0, i64 10
+  %ptr6 = getelementptr float, float *%ptr0, i64 12
+  %ptr7 = getelementptr float, float *%ptr0, i64 14
+  %ptr8 = getelementptr float, float *%ptr0, i64 16
+  %ptr9 = getelementptr float, float *%ptr0, i64 18
+  %ptr10 = getelementptr float, float *%ptr0, i64 20
 
-  %val0 = load float *%ptr0
-  %val1 = load float *%ptr1
-  %val2 = load float *%ptr2
-  %val3 = load float *%ptr3
-  %val4 = load float *%ptr4
-  %val5 = load float *%ptr5
-  %val6 = load float *%ptr6
-  %val7 = load float *%ptr7
-  %val8 = load float *%ptr8
-  %val9 = load float *%ptr9
-  %val10 = load float *%ptr10
+  %val0 = load float , float *%ptr0
+  %val1 = load float , float *%ptr1
+  %val2 = load float , float *%ptr2
+  %val3 = load float , float *%ptr3
+  %val4 = load float , float *%ptr4
+  %val5 = load float , float *%ptr5
+  %val6 = load float , float *%ptr6
+  %val7 = load float , float *%ptr7
+  %val8 = load float , float *%ptr8
+  %val9 = load float , float *%ptr9
+  %val10 = load float , float *%ptr10
 
   %ret = call float @foo()
 
diff --git a/test/CodeGen/SystemZ/fp-div-02.ll b/test/CodeGen/SystemZ/fp-div-02.ll
index 513664bd9496..f120e7c923dc 100644
--- a/test/CodeGen/SystemZ/fp-div-02.ll
+++ b/test/CodeGen/SystemZ/fp-div-02.ll
@@ -1,6 +1,8 @@
 ; Test 64-bit floating-point division.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 declare double @foo()
 
@@ -18,7 +20,7 @@ define double @f2(double %f1, double *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: ddb %f0, 0(%r2)
 ; CHECK: br %r14
-  %f2 = load double *%ptr
+  %f2 = load double , double *%ptr
   %res = fdiv double %f1, %f2
   ret double %res
 }
@@ -28,8 +30,8 @@ define double @f3(double %f1, double *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: ddb %f0, 4088(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 511
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 511
+  %f2 = load double , double *%ptr
   %res = fdiv double %f1, %f2
   ret double %res
 }
@@ -41,8 +43,8 @@ define double @f4(double %f1, double *%base) {
 ; CHECK: aghi %r2, 4096
 ; CHECK: ddb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 512
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 512
+  %f2 = load double , double *%ptr
   %res = fdiv double %f1, %f2
   ret double %res
 }
@@ -53,8 +55,8 @@ define double @f5(double %f1, double *%base) {
 ; CHECK: aghi %r2, -8
 ; CHECK: ddb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 -1
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 -1
+  %f2 = load double , double *%ptr
   %res = fdiv double %f1, %f2
   ret double %res
 }
@@ -65,9 +67,9 @@ define double @f6(double %f1, double *%base, i64 %index) {
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: ddb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
-  %ptr1 = getelementptr double *%base, i64 %index
-  %ptr2 = getelementptr double *%ptr1, i64 100
-  %f2 = load double *%ptr2
+  %ptr1 = getelementptr double, double *%base, i64 %index
+  %ptr2 = getelementptr double, double *%ptr1, i64 100
+  %f2 = load double , double *%ptr2
   %res = fdiv double %f1, %f2
   ret double %res
 }
@@ -76,30 +78,30 @@ define double @f6(double %f1, double *%base, i64 %index) {
 define double @f7(double *%ptr0) {
 ; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
-; CHECK: ddb %f0, 160(%r15)
+; CHECK-SCALAR: ddb %f0, 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr double *%ptr0, i64 2
-  %ptr2 = getelementptr double *%ptr0, i64 4
-  %ptr3 = getelementptr double *%ptr0, i64 6
-  %ptr4 = getelementptr double *%ptr0, i64 8
-  %ptr5 = getelementptr double *%ptr0, i64 10
-  %ptr6 = getelementptr double *%ptr0, i64 12
-  %ptr7 = getelementptr double *%ptr0, i64 14
-  %ptr8 = getelementptr double *%ptr0, i64 16
-  %ptr9 = getelementptr double *%ptr0, i64 18
-  %ptr10 = getelementptr double *%ptr0, i64 20
+  %ptr1 = getelementptr double, double *%ptr0, i64 2
+  %ptr2 = getelementptr double, double *%ptr0, i64 4
+  %ptr3 = getelementptr double, double *%ptr0, i64 6
+  %ptr4 = getelementptr double, double *%ptr0, i64 8
+  %ptr5 = getelementptr double, double *%ptr0, i64 10
+  %ptr6 = getelementptr double, double *%ptr0, i64 12
+  %ptr7 = getelementptr double, double *%ptr0, i64 14
+  %ptr8 = getelementptr double, double *%ptr0, i64 16
+  %ptr9 = getelementptr double, double *%ptr0, i64 18
+  %ptr10 = getelementptr double, double *%ptr0, i64 20
 
-  %val0 = load double *%ptr0
-  %val1 = load double *%ptr1
-  %val2 = load double *%ptr2
-  %val3 = load double *%ptr3
-  %val4 = load double *%ptr4
-  %val5 = load double *%ptr5
-  %val6 = load double *%ptr6
-  %val7 = load double *%ptr7
-  %val8 = load double *%ptr8
-  %val9 = load double *%ptr9
-  %val10 = load double *%ptr10
+  %val0 = load double , double *%ptr0
+  %val1 = load double , double *%ptr1
+  %val2 = load double , double *%ptr2
+  %val3 = load double , double *%ptr3
+  %val4 = load double , double *%ptr4
+  %val5 = load double , double *%ptr5
+  %val6 = load double , double *%ptr6
+  %val7 = load double , double *%ptr7
+  %val8 = load double , double *%ptr8
+  %val9 = load double , double *%ptr9
+  %val10 = load double , double *%ptr10
 
   %ret = call double @foo()
 
diff --git a/test/CodeGen/SystemZ/fp-div-03.ll b/test/CodeGen/SystemZ/fp-div-03.ll
index 079b349b4084..f052635a483e 100644
--- a/test/CodeGen/SystemZ/fp-div-03.ll
+++ b/test/CodeGen/SystemZ/fp-div-03.ll
@@ -12,7 +12,7 @@ define void @f1(fp128 *%ptr, float %f2) {
 ; CHECK: std %f1, 0(%r2)
 ; CHECK: std %f3, 8(%r2)
 ; CHECK: br %r14
-  %f1 = load fp128 *%ptr
+  %f1 = load fp128 , fp128 *%ptr
   %f2x = fpext float %f2 to fp128
   %sum = fdiv fp128 %f1, %f2x
   store fp128 %sum, fp128 *%ptr
diff --git a/test/CodeGen/SystemZ/fp-move-01.ll b/test/CodeGen/SystemZ/fp-move-01.ll
index d16502f2f7c8..843b1b6a6e64 100644
--- a/test/CodeGen/SystemZ/fp-move-01.ll
+++ b/test/CodeGen/SystemZ/fp-move-01.ll
@@ -1,11 +1,13 @@
 ; Test moves between FPRs.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 ; Test f32 moves.
 define float @f1(float %a, float %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: ler %f0, %f2
+; CHECK: br %r14
   ret float %b
 }
 
@@ -13,6 +15,7 @@ define float @f1(float %a, float %b) {
 define double @f2(double %a, double %b) {
 ; CHECK-LABEL: f2:
 ; CHECK: ldr %f0, %f2
+; CHECK: br %r14
   ret double %b
 }
 
@@ -22,7 +25,8 @@ define void @f3(fp128 *%x) {
 ; CHECK-LABEL: f3:
 ; CHECK: lxr
 ; CHECK: axbr
-  %val = load volatile fp128 *%x
+; CHECK: br %r14
+  %val = load volatile fp128 , fp128 *%x
   %sum = fadd fp128 %val, %val
   store volatile fp128 %sum, fp128 *%x
   store volatile fp128 %val, fp128 *%x
diff --git a/test/CodeGen/SystemZ/fp-move-02.ll b/test/CodeGen/SystemZ/fp-move-02.ll
index 505ee8d37a4e..2bd63f4674d9 100644
--- a/test/CodeGen/SystemZ/fp-move-02.ll
+++ b/test/CodeGen/SystemZ/fp-move-02.ll
@@ -71,7 +71,7 @@ define void @f6(fp128 *%a, i128 *%b) {
 ; CHECK: stg
 ; CHECK: stg
 ; CHECK: br %r14
-  %val = load i128 *%b
+  %val = load i128 , i128 *%b
   %res = bitcast i128 %val to fp128
   store fp128 %res, fp128 *%a
   ret void
@@ -102,7 +102,7 @@ define void @f9(fp128 *%a, i128 *%b) {
 ; CHECK: ld
 ; CHECK: std
 ; CHECK: std
-  %val = load fp128 *%a
+  %val = load fp128 , fp128 *%a
   %res = bitcast fp128 %val to i128
   store i128 %res, i128 *%b
   ret void
@@ -119,34 +119,34 @@ define void @f10(double %extra) {
 ; CHECK: %exit
 ; CHECK: br %r14
 entry:
-  %double0 = load volatile double *@dptr
+  %double0 = load volatile double , double *@dptr
   %biased0 = fadd double %double0, %extra
   %int0 = bitcast double %biased0 to i64
-  %double1 = load volatile double *@dptr
+  %double1 = load volatile double , double *@dptr
   %biased1 = fadd double %double1, %extra
   %int1 = bitcast double %biased1 to i64
-  %double2 = load volatile double *@dptr
+  %double2 = load volatile double , double *@dptr
   %biased2 = fadd double %double2, %extra
   %int2 = bitcast double %biased2 to i64
-  %double3 = load volatile double *@dptr
+  %double3 = load volatile double , double *@dptr
   %biased3 = fadd double %double3, %extra
   %int3 = bitcast double %biased3 to i64
-  %double4 = load volatile double *@dptr
+  %double4 = load volatile double , double *@dptr
   %biased4 = fadd double %double4, %extra
   %int4 = bitcast double %biased4 to i64
-  %double5 = load volatile double *@dptr
+  %double5 = load volatile double , double *@dptr
   %biased5 = fadd double %double5, %extra
   %int5 = bitcast double %biased5 to i64
-  %double6 = load volatile double *@dptr
+  %double6 = load volatile double , double *@dptr
   %biased6 = fadd double %double6, %extra
   %int6 = bitcast double %biased6 to i64
-  %double7 = load volatile double *@dptr
+  %double7 = load volatile double , double *@dptr
   %biased7 = fadd double %double7, %extra
   %int7 = bitcast double %biased7 to i64
-  %double8 = load volatile double *@dptr
+  %double8 = load volatile double , double *@dptr
   %biased8 = fadd double %double8, %extra
   %int8 = bitcast double %biased8 to i64
-  %double9 = load volatile double *@dptr
+  %double9 = load volatile double , double *@dptr
   %biased9 = fadd double %double9, %extra
   %int9 = bitcast double %biased9 to i64
   br label %loop
@@ -181,34 +181,34 @@ define void @f11(i64 %mask) {
 ; CHECK: %exit
 ; CHECK: br %r14
 entry:
-  %int0 = load volatile i64 *@iptr
+  %int0 = load volatile i64 , i64 *@iptr
   %masked0 = and i64 %int0, %mask
   %double0 = bitcast i64 %masked0 to double
-  %int1 = load volatile i64 *@iptr
+  %int1 = load volatile i64 , i64 *@iptr
   %masked1 = and i64 %int1, %mask
   %double1 = bitcast i64 %masked1 to double
-  %int2 = load volatile i64 *@iptr
+  %int2 = load volatile i64 , i64 *@iptr
   %masked2 = and i64 %int2, %mask
   %double2 = bitcast i64 %masked2 to double
-  %int3 = load volatile i64 *@iptr
+  %int3 = load volatile i64 , i64 *@iptr
   %masked3 = and i64 %int3, %mask
   %double3 = bitcast i64 %masked3 to double
-  %int4 = load volatile i64 *@iptr
+  %int4 = load volatile i64 , i64 *@iptr
   %masked4 = and i64 %int4, %mask
   %double4 = bitcast i64 %masked4 to double
-  %int5 = load volatile i64 *@iptr
+  %int5 = load volatile i64 , i64 *@iptr
   %masked5 = and i64 %int5, %mask
   %double5 = bitcast i64 %masked5 to double
-  %int6 = load volatile i64 *@iptr
+  %int6 = load volatile i64 , i64 *@iptr
   %masked6 = and i64 %int6, %mask
   %double6 = bitcast i64 %masked6 to double
-  %int7 = load volatile i64 *@iptr
+  %int7 = load volatile i64 , i64 *@iptr
   %masked7 = and i64 %int7, %mask
   %double7 = bitcast i64 %masked7 to double
-  %int8 = load volatile i64 *@iptr
+  %int8 = load volatile i64 , i64 *@iptr
   %masked8 = and i64 %int8, %mask
   %double8 = bitcast i64 %masked8 to double
-  %int9 = load volatile i64 *@iptr
+  %int9 = load volatile i64 , i64 *@iptr
   %masked9 = and i64 %int9, %mask
   %double9 = bitcast i64 %masked9 to double
   br label %loop
@@ -275,7 +275,7 @@ loop:
 
 exit:
   %unused1 = call i64 @foo()
-  %factor = load volatile double *@dptr
+  %factor = load volatile double , double *@dptr
 
   %conv0 = bitcast i64 %add0 to double
   %mul0 = fmul double %conv0, %factor
@@ -354,7 +354,7 @@ loop:
 
 exit:
   %unused1 = call i64 @foo()
-  %bias = load volatile i64 *@iptr
+  %bias = load volatile i64 , i64 *@iptr
 
   %conv0 = bitcast double %mul0 to i64
   %add0 = add i64 %conv0, %bias
diff --git a/test/CodeGen/SystemZ/fp-move-03.ll b/test/CodeGen/SystemZ/fp-move-03.ll
index 1273358f65ad..f50e097bef69 100644
--- a/test/CodeGen/SystemZ/fp-move-03.ll
+++ b/test/CodeGen/SystemZ/fp-move-03.ll
@@ -7,7 +7,7 @@ define float @f1(float *%src) {
 ; CHECK-LABEL: f1:
 ; CHECK: le %f0, 0(%r2)
 ; CHECK: br %r14
-  %val = load float *%src
+  %val = load float , float *%src
   ret float %val
 }
 
@@ -16,8 +16,8 @@ define float @f2(float *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: le %f0, 4092(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%src, i64 1023
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%src, i64 1023
+  %val = load float , float *%ptr
   ret float %val
 }
 
@@ -26,8 +26,8 @@ define float @f3(float *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: ley %f0, 4096(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%src, i64 1024
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%src, i64 1024
+  %val = load float , float *%ptr
   ret float %val
 }
 
@@ -36,8 +36,8 @@ define float @f4(float *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: ley %f0, 524284(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%src, i64 131071
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%src, i64 131071
+  %val = load float , float *%ptr
   ret float %val
 }
 
@@ -48,8 +48,8 @@ define float @f5(float *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: le %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%src, i64 131072
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%src, i64 131072
+  %val = load float , float *%ptr
   ret float %val
 }
 
@@ -58,8 +58,8 @@ define float @f6(float *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: ley %f0, -4(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%src, i64 -1
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%src, i64 -1
+  %val = load float , float *%ptr
   ret float %val
 }
 
@@ -68,8 +68,8 @@ define float @f7(float *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: ley %f0, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%src, i64 -131072
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%src, i64 -131072
+  %val = load float , float *%ptr
   ret float %val
 }
 
@@ -80,8 +80,8 @@ define float @f8(float *%src) {
 ; CHECK: agfi %r2, -524292
 ; CHECK: le %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%src, i64 -131073
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%src, i64 -131073
+  %val = load float , float *%ptr
   ret float %val
 }
 
@@ -93,7 +93,7 @@ define float @f9(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4092
   %ptr = inttoptr i64 %add2 to float *
-  %val = load float *%ptr
+  %val = load float , float *%ptr
   ret float %val
 }
 
@@ -105,6 +105,6 @@ define float @f10(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to float *
-  %val = load float *%ptr
+  %val = load float , float *%ptr
   ret float %val
 }
diff --git a/test/CodeGen/SystemZ/fp-move-04.ll b/test/CodeGen/SystemZ/fp-move-04.ll
index 1b0278fdee0f..6650419b2c38 100644
--- a/test/CodeGen/SystemZ/fp-move-04.ll
+++ b/test/CodeGen/SystemZ/fp-move-04.ll
@@ -1,13 +1,14 @@
 ; Test 64-bit floating-point loads.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 ; Test the low end of the LD range.
 define double @f1(double *%src) {
 ; CHECK-LABEL: f1:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: br %r14
-  %val = load double *%src
+  %val = load double , double *%src
   ret double %val
 }
 
@@ -16,8 +17,8 @@ define double @f2(double *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: ld %f0, 4088(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%src, i64 511
-  %val = load double *%ptr
+  %ptr = getelementptr double, double *%src, i64 511
+  %val = load double , double *%ptr
   ret double %val
 }
 
@@ -26,8 +27,8 @@ define double @f3(double *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: ldy %f0, 4096(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%src, i64 512
-  %val = load double *%ptr
+  %ptr = getelementptr double, double *%src, i64 512
+  %val = load double , double *%ptr
   ret double %val
 }
 
@@ -36,8 +37,8 @@ define double @f4(double *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: ldy %f0, 524280(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%src, i64 65535
-  %val = load double *%ptr
+  %ptr = getelementptr double, double *%src, i64 65535
+  %val = load double , double *%ptr
   ret double %val
 }
 
@@ -48,8 +49,8 @@ define double @f5(double *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%src, i64 65536
-  %val = load double *%ptr
+  %ptr = getelementptr double, double *%src, i64 65536
+  %val = load double , double *%ptr
   ret double %val
 }
 
@@ -58,8 +59,8 @@ define double @f6(double *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: ldy %f0, -8(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%src, i64 -1
-  %val = load double *%ptr
+  %ptr = getelementptr double, double *%src, i64 -1
+  %val = load double , double *%ptr
   ret double %val
 }
 
@@ -68,8 +69,8 @@ define double @f7(double *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: ldy %f0, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%src, i64 -65536
-  %val = load double *%ptr
+  %ptr = getelementptr double, double *%src, i64 -65536
+  %val = load double , double *%ptr
   ret double %val
 }
 
@@ -80,8 +81,8 @@ define double @f8(double *%src) {
 ; CHECK: agfi %r2, -524296
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%src, i64 -65537
-  %val = load double *%ptr
+  %ptr = getelementptr double, double *%src, i64 -65537
+  %val = load double , double *%ptr
   ret double %val
 }
 
@@ -93,7 +94,7 @@ define double @f9(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4095
   %ptr = inttoptr i64 %add2 to double *
-  %val = load double *%ptr
+  %val = load double , double *%ptr
   ret double %val
 }
 
@@ -105,6 +106,6 @@ define double @f10(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to double *
-  %val = load double *%ptr
+  %val = load double , double *%ptr
   ret double %val
 }
diff --git a/test/CodeGen/SystemZ/fp-move-05.ll b/test/CodeGen/SystemZ/fp-move-05.ll
index d302a0f9c633..da12af6d68c1 100644
--- a/test/CodeGen/SystemZ/fp-move-05.ll
+++ b/test/CodeGen/SystemZ/fp-move-05.ll
@@ -9,7 +9,7 @@ define double @f1(i64 %src) {
 ; CHECK: ld %f2, 8(%r2)
 ; CHECK: br %r14
   %ptr = inttoptr i64 %src to fp128 *
-  %val = load fp128 *%ptr
+  %val = load fp128 , fp128 *%ptr
   %trunc = fptrunc fp128 %val to double
   ret double %trunc
 }
@@ -22,7 +22,7 @@ define double @f2(i64 %src) {
 ; CHECK: br %r14
   %add = add i64 %src, 4080
   %ptr = inttoptr i64 %add to fp128 *
-  %val = load fp128 *%ptr
+  %val = load fp128 , fp128 *%ptr
   %trunc = fptrunc fp128 %val to double
   ret double %trunc
 }
@@ -35,7 +35,7 @@ define double @f3(i64 %src) {
 ; CHECK: br %r14
   %add = add i64 %src, 4088
   %ptr = inttoptr i64 %add to fp128 *
-  %val = load fp128 *%ptr
+  %val = load fp128 , fp128 *%ptr
   %trunc = fptrunc fp128 %val to double
   ret double %trunc
 }
@@ -48,7 +48,7 @@ define double @f4(i64 %src) {
 ; CHECK: br %r14
   %add = add i64 %src, 4096
   %ptr = inttoptr i64 %add to fp128 *
-  %val = load fp128 *%ptr
+  %val = load fp128 , fp128 *%ptr
   %trunc = fptrunc fp128 %val to double
   ret double %trunc
 }
@@ -61,7 +61,7 @@ define double @f5(i64 %src) {
 ; CHECK: br %r14
   %add = add i64 %src, 524272
   %ptr = inttoptr i64 %add to fp128 *
-  %val = load fp128 *%ptr
+  %val = load fp128 , fp128 *%ptr
   %trunc = fptrunc fp128 %val to double
   ret double %trunc
 }
@@ -76,7 +76,7 @@ define double @f6(i64 %src) {
 ; CHECK: br %r14
   %add = add i64 %src, 524280
   %ptr = inttoptr i64 %add to fp128 *
-  %val = load fp128 *%ptr
+  %val = load fp128 , fp128 *%ptr
   %trunc = fptrunc fp128 %val to double
   ret double %trunc
 }
@@ -90,7 +90,7 @@ define double @f7(i64 %src) {
 ; CHECK: br %r14
   %add = add i64 %src, -8
   %ptr = inttoptr i64 %add to fp128 *
-  %val = load fp128 *%ptr
+  %val = load fp128 , fp128 *%ptr
   %trunc = fptrunc fp128 %val to double
   ret double %trunc
 }
@@ -103,7 +103,7 @@ define double @f8(i64 %src) {
 ; CHECK: br %r14
   %add = add i64 %src, -16
   %ptr = inttoptr i64 %add to fp128 *
-  %val = load fp128 *%ptr
+  %val = load fp128 , fp128 *%ptr
   %trunc = fptrunc fp128 %val to double
   ret double %trunc
 }
@@ -116,7 +116,7 @@ define double @f9(i64 %src) {
 ; CHECK: br %r14
   %add = add i64 %src, -524288
   %ptr = inttoptr i64 %add to fp128 *
-  %val = load fp128 *%ptr
+  %val = load fp128 , fp128 *%ptr
   %trunc = fptrunc fp128 %val to double
   ret double %trunc
 }
@@ -131,7 +131,7 @@ define double @f10(i64 %src) {
 ; CHECK: br %r14
   %add = add i64 %src, -524296
   %ptr = inttoptr i64 %add to fp128 *
-  %val = load fp128 *%ptr
+  %val = load fp128 , fp128 *%ptr
   %trunc = fptrunc fp128 %val to double
   ret double %trunc
 }
@@ -145,7 +145,7 @@ define double @f11(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4088
   %ptr = inttoptr i64 %add2 to fp128 *
-  %val = load fp128 *%ptr
+  %val = load fp128 , fp128 *%ptr
   %trunc = fptrunc fp128 %val to double
   ret double %trunc
 }
diff --git a/test/CodeGen/SystemZ/fp-move-06.ll b/test/CodeGen/SystemZ/fp-move-06.ll
index da67691729e3..eb0f87f1c572 100644
--- a/test/CodeGen/SystemZ/fp-move-06.ll
+++ b/test/CodeGen/SystemZ/fp-move-06.ll
@@ -16,7 +16,7 @@ define void @f2(float *%src, float %val) {
 ; CHECK-LABEL: f2:
 ; CHECK: ste %f0, 4092(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%src, i64 1023
+  %ptr = getelementptr float, float *%src, i64 1023
   store float %val, float *%ptr
   ret void
 }
@@ -26,7 +26,7 @@ define void @f3(float *%src, float %val) {
 ; CHECK-LABEL: f3:
 ; CHECK: stey %f0, 4096(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%src, i64 1024
+  %ptr = getelementptr float, float *%src, i64 1024
   store float %val, float *%ptr
   ret void
 }
@@ -36,7 +36,7 @@ define void @f4(float *%src, float %val) {
 ; CHECK-LABEL: f4:
 ; CHECK: stey %f0, 524284(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%src, i64 131071
+  %ptr = getelementptr float, float *%src, i64 131071
   store float %val, float *%ptr
   ret void
 }
@@ -48,7 +48,7 @@ define void @f5(float *%src, float %val) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: ste %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%src, i64 131072
+  %ptr = getelementptr float, float *%src, i64 131072
   store float %val, float *%ptr
   ret void
 }
@@ -58,7 +58,7 @@ define void @f6(float *%src, float %val) {
 ; CHECK-LABEL: f6:
 ; CHECK: stey %f0, -4(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%src, i64 -1
+  %ptr = getelementptr float, float *%src, i64 -1
   store float %val, float *%ptr
   ret void
 }
@@ -68,7 +68,7 @@ define void @f7(float *%src, float %val) {
 ; CHECK-LABEL: f7:
 ; CHECK: stey %f0, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%src, i64 -131072
+  %ptr = getelementptr float, float *%src, i64 -131072
   store float %val, float *%ptr
   ret void
 }
@@ -80,7 +80,7 @@ define void @f8(float *%src, float %val) {
 ; CHECK: agfi %r2, -524292
 ; CHECK: ste %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%src, i64 -131073
+  %ptr = getelementptr float, float *%src, i64 -131073
   store float %val, float *%ptr
   ret void
 }
diff --git a/test/CodeGen/SystemZ/fp-move-07.ll b/test/CodeGen/SystemZ/fp-move-07.ll
index a4f1820d1204..5361002a97e0 100644
--- a/test/CodeGen/SystemZ/fp-move-07.ll
+++ b/test/CodeGen/SystemZ/fp-move-07.ll
@@ -1,6 +1,7 @@
 ; Test 64-bit floating-point stores.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 ; Test the low end of the STD range.
 define void @f1(double *%src, double %val) {
@@ -16,7 +17,7 @@ define void @f2(double *%src, double %val) {
 ; CHECK-LABEL: f2:
 ; CHECK: std %f0, 4088(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%src, i64 511
+  %ptr = getelementptr double, double *%src, i64 511
   store double %val, double *%ptr
   ret void
 }
@@ -26,7 +27,7 @@ define void @f3(double *%src, double %val) {
 ; CHECK-LABEL: f3:
 ; CHECK: stdy %f0, 4096(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%src, i64 512
+  %ptr = getelementptr double, double *%src, i64 512
   store double %val, double *%ptr
   ret void
 }
@@ -36,7 +37,7 @@ define void @f4(double *%src, double %val) {
 ; CHECK-LABEL: f4:
 ; CHECK: stdy %f0, 524280(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%src, i64 65535
+  %ptr = getelementptr double, double *%src, i64 65535
   store double %val, double *%ptr
   ret void
 }
@@ -48,7 +49,7 @@ define void @f5(double *%src, double %val) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%src, i64 65536
+  %ptr = getelementptr double, double *%src, i64 65536
   store double %val, double *%ptr
   ret void
 }
@@ -58,7 +59,7 @@ define void @f6(double *%src, double %val) {
 ; CHECK-LABEL: f6:
 ; CHECK: stdy %f0, -8(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%src, i64 -1
+  %ptr = getelementptr double, double *%src, i64 -1
   store double %val, double *%ptr
   ret void
 }
@@ -68,7 +69,7 @@ define void @f7(double *%src, double %val) {
 ; CHECK-LABEL: f7:
 ; CHECK: stdy %f0, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%src, i64 -65536
+  %ptr = getelementptr double, double *%src, i64 -65536
   store double %val, double *%ptr
   ret void
 }
@@ -80,7 +81,7 @@ define void @f8(double *%src, double %val) {
 ; CHECK: agfi %r2, -524296
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%src, i64 -65537
+  %ptr = getelementptr double, double *%src, i64 -65537
   store double %val, double *%ptr
   ret void
 }
diff --git a/test/CodeGen/SystemZ/fp-move-09.ll b/test/CodeGen/SystemZ/fp-move-09.ll
index 52b2ee2e31ab..5e8dce272c23 100644
--- a/test/CodeGen/SystemZ/fp-move-09.ll
+++ b/test/CodeGen/SystemZ/fp-move-09.ll
@@ -1,4 +1,4 @@
-; Test moves between FPRs and GPRs for z196 and above.
+; Test moves between FPRs and GPRs for z196 and zEC12.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
 
@@ -9,7 +9,7 @@ define float @f1(i16 *%ptr) {
 ; CHECK: oihh [[REG]], 16256
 ; CHECK: ldgr %f0, [[REG]]
 ; CHECK: br %r14
-  %base = load i16 *%ptr
+  %base = load i16 , i16 *%ptr
   %ext = zext i16 %base to i32
   %full = or i32 %ext, 1065353216
   %res = bitcast i32 %full to float
@@ -38,7 +38,7 @@ define void @f3(float %val, i8 *%ptr, i32 %which) {
 ; CHECK: br %r14
   %int = bitcast float %val to i32
   %trunc = trunc i32 %int to i8
-  %old = load i8 *%ptr
+  %old = load i8 , i8 *%ptr
   %cmp = icmp eq i32 %which, 0
   %res = select i1 %cmp, i8 %trunc, i8 %old
   store i8 %res, i8 *%ptr
@@ -54,7 +54,7 @@ define void @f4(float %val, i16 *%ptr, i32 %which) {
 ; CHECK: br %r14
   %int = bitcast float %val to i32
   %trunc = trunc i32 %int to i16
-  %old = load i16 *%ptr
+  %old = load i16 , i16 *%ptr
   %cmp = icmp eq i32 %which, 0
   %res = select i1 %cmp, i16 %trunc, i16 %old
   store i16 %res, i16 *%ptr
diff --git a/test/CodeGen/SystemZ/fp-move-10.ll b/test/CodeGen/SystemZ/fp-move-10.ll
new file mode 100644
index 000000000000..602397d58a8d
--- /dev/null
+++ b/test/CodeGen/SystemZ/fp-move-10.ll
@@ -0,0 +1,61 @@
+; Test moves between FPRs and GPRs for z13 and above.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Check that moves from i32s to floats use a low GR32 and vector operation.
+define float @f1(i16 *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: llh [[REG:%r[0-5]]], 0(%r2)
+; CHECK: oilh [[REG]], 16256
+; CHECK: vlvgf %v0, [[REG]], 0
+; CHECK: br %r14
+  %base = load i16, i16 *%ptr
+  %ext = zext i16 %base to i32
+  %full = or i32 %ext, 1065353216
+  %res = bitcast i32 %full to float
+  ret float %res
+}
+
+; Check that moves from floats to i32s use a low GR32 and vector operation.
+define void @f2(float %val, i8 *%ptr) {
+; CHECK-LABEL: f2:
+; CHECK: vlgvf [[REG:%r[0-5]]], %v0, 0
+; CHECK: stc [[REG]], 0(%r2)
+; CHECK: br %r14
+  %res = bitcast float %val to i32
+  %trunc = trunc i32 %res to i8
+  store i8 %trunc, i8 *%ptr
+  ret void
+}
+
+; Like f2, but with a conditional store.
+define void @f3(float %val, i8 *%ptr, i32 %which) {
+; CHECK-LABEL: f3:
+; CHECK-DAG: cijlh %r3, 0,
+; CHECK-DAG: vlgvf [[REG:%r[0-5]]], %v0, 0
+; CHECK: stc [[REG]], 0(%r2)
+; CHECK: br %r14
+  %int = bitcast float %val to i32
+  %trunc = trunc i32 %int to i8
+  %old = load i8, i8 *%ptr
+  %cmp = icmp eq i32 %which, 0
+  %res = select i1 %cmp, i8 %trunc, i8 %old
+  store i8 %res, i8 *%ptr
+  ret void
+}
+
+; ...and again with 16-bit memory.
+define void @f4(float %val, i16 *%ptr, i32 %which) {
+; CHECK-LABEL: f4:
+; CHECK-DAG: cijlh %r3, 0,
+; CHECK-DAG: vlgvf [[REG:%r[0-5]]], %v0, 0
+; CHECK: sth [[REG]], 0(%r2)
+; CHECK: br %r14
+  %int = bitcast float %val to i32
+  %trunc = trunc i32 %int to i16
+  %old = load i16, i16 *%ptr
+  %cmp = icmp eq i32 %which, 0
+  %res = select i1 %cmp, i16 %trunc, i16 %old
+  store i16 %res, i16 *%ptr
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/fp-move-11.ll b/test/CodeGen/SystemZ/fp-move-11.ll
new file mode 100644
index 000000000000..ce45019425cb
--- /dev/null
+++ b/test/CodeGen/SystemZ/fp-move-11.ll
@@ -0,0 +1,110 @@
+; Test 32-bit floating-point loads for z13.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test that we use LDE instead of LE - low end of the LE range.
+define float @f1(float *%src) {
+; CHECK-LABEL: f1:
+; CHECK: lde %f0, 0(%r2)
+; CHECK: br %r14
+  %val = load float, float *%src
+  ret float %val
+}
+
+; Test that we use LDE instead of LE - high end of the LE range.
+define float @f2(float *%src) {
+; CHECK-LABEL: f2:
+; CHECK: lde %f0, 4092(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr float, float *%src, i64 1023
+  %val = load float, float *%ptr
+  ret float %val
+}
+
+; Check the next word up, which should use LEY instead of LDE.
+define float @f3(float *%src) {
+; CHECK-LABEL: f3:
+; CHECK: ley %f0, 4096(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr float, float *%src, i64 1024
+  %val = load float, float *%ptr
+  ret float %val
+}
+
+; Check the high end of the aligned LEY range.
+define float @f4(float *%src) {
+; CHECK-LABEL: f4:
+; CHECK: ley %f0, 524284(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr float, float *%src, i64 131071
+  %val = load float, float *%ptr
+  ret float %val
+}
+
+; Check the next word up, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define float @f5(float *%src) {
+; CHECK-LABEL: f5:
+; CHECK: agfi %r2, 524288
+; CHECK: lde %f0, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr float, float *%src, i64 131072
+  %val = load float, float *%ptr
+  ret float %val
+}
+
+; Check the high end of the negative aligned LEY range.
+define float @f6(float *%src) {
+; CHECK-LABEL: f6:
+; CHECK: ley %f0, -4(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr float, float *%src, i64 -1
+  %val = load float, float *%ptr
+  ret float %val
+}
+
+; Check the low end of the LEY range.
+define float @f7(float *%src) {
+; CHECK-LABEL: f7:
+; CHECK: ley %f0, -524288(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr float, float *%src, i64 -131072
+  %val = load float, float *%ptr
+  ret float %val
+}
+
+; Check the next word down, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define float @f8(float *%src) {
+; CHECK-LABEL: f8:
+; CHECK: agfi %r2, -524292
+; CHECK: lde %f0, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr float, float *%src, i64 -131073
+  %val = load float, float *%ptr
+  ret float %val
+}
+
+; Check that LDE allows an index.
+define float @f9(i64 %src, i64 %index) {
+; CHECK-LABEL: f9:
+; CHECK: lde %f0, 4092({{%r3,%r2|%r2,%r3}})
+; CHECK: br %r14
+  %add1 = add i64 %src, %index
+  %add2 = add i64 %add1, 4092
+  %ptr = inttoptr i64 %add2 to float *
+  %val = load float, float *%ptr
+  ret float %val
+}
+
+; Check that LEY allows an index.
+define float @f10(i64 %src, i64 %index) {
+; CHECK-LABEL: f10:
+; CHECK: ley %f0, 4096({{%r3,%r2|%r2,%r3}})
+; CHECK: br %r14
+  %add1 = add i64 %src, %index
+  %add2 = add i64 %add1, 4096
+  %ptr = inttoptr i64 %add2 to float *
+  %val = load float, float *%ptr
+  ret float %val
+}
diff --git a/test/CodeGen/SystemZ/fp-mul-01.ll b/test/CodeGen/SystemZ/fp-mul-01.ll
index 7562d6bf071b..3b72d25e0b5c 100644
--- a/test/CodeGen/SystemZ/fp-mul-01.ll
+++ b/test/CodeGen/SystemZ/fp-mul-01.ll
@@ -18,7 +18,7 @@ define float @f2(float %f1, float *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: meeb %f0, 0(%r2)
 ; CHECK: br %r14
-  %f2 = load float *%ptr
+  %f2 = load float , float *%ptr
   %res = fmul float %f1, %f2
   ret float %res
 }
@@ -28,8 +28,8 @@ define float @f3(float %f1, float *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: meeb %f0, 4092(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1023
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1023
+  %f2 = load float , float *%ptr
   %res = fmul float %f1, %f2
   ret float %res
 }
@@ -41,8 +41,8 @@ define float @f4(float %f1, float *%base) {
 ; CHECK: aghi %r2, 4096
 ; CHECK: meeb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1024
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1024
+  %f2 = load float , float *%ptr
   %res = fmul float %f1, %f2
   ret float %res
 }
@@ -53,8 +53,8 @@ define float @f5(float %f1, float *%base) {
 ; CHECK: aghi %r2, -4
 ; CHECK: meeb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 -1
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 -1
+  %f2 = load float , float *%ptr
   %res = fmul float %f1, %f2
   ret float %res
 }
@@ -65,9 +65,9 @@ define float @f6(float %f1, float *%base, i64 %index) {
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: meeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%base, i64 %index
-  %ptr2 = getelementptr float *%ptr1, i64 100
-  %f2 = load float *%ptr2
+  %ptr1 = getelementptr float, float *%base, i64 %index
+  %ptr2 = getelementptr float, float *%ptr1, i64 100
+  %f2 = load float , float *%ptr2
   %res = fmul float %f1, %f2
   ret float %res
 }
@@ -78,28 +78,28 @@ define float @f7(float *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: meeb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%ptr0, i64 2
-  %ptr2 = getelementptr float *%ptr0, i64 4
-  %ptr3 = getelementptr float *%ptr0, i64 6
-  %ptr4 = getelementptr float *%ptr0, i64 8
-  %ptr5 = getelementptr float *%ptr0, i64 10
-  %ptr6 = getelementptr float *%ptr0, i64 12
-  %ptr7 = getelementptr float *%ptr0, i64 14
-  %ptr8 = getelementptr float *%ptr0, i64 16
-  %ptr9 = getelementptr float *%ptr0, i64 18
-  %ptr10 = getelementptr float *%ptr0, i64 20
+  %ptr1 = getelementptr float, float *%ptr0, i64 2
+  %ptr2 = getelementptr float, float *%ptr0, i64 4
+  %ptr3 = getelementptr float, float *%ptr0, i64 6
+  %ptr4 = getelementptr float, float *%ptr0, i64 8
+  %ptr5 = getelementptr float, float *%ptr0, i64 10
+  %ptr6 = getelementptr float, float *%ptr0, i64 12
+  %ptr7 = getelementptr float, float *%ptr0, i64 14
+  %ptr8 = getelementptr float, float *%ptr0, i64 16
+  %ptr9 = getelementptr float, float *%ptr0, i64 18
+  %ptr10 = getelementptr float, float *%ptr0, i64 20
 
-  %val0 = load float *%ptr0
-  %val1 = load float *%ptr1
-  %val2 = load float *%ptr2
-  %val3 = load float *%ptr3
-  %val4 = load float *%ptr4
-  %val5 = load float *%ptr5
-  %val6 = load float *%ptr6
-  %val7 = load float *%ptr7
-  %val8 = load float *%ptr8
-  %val9 = load float *%ptr9
-  %val10 = load float *%ptr10
+  %val0 = load float , float *%ptr0
+  %val1 = load float , float *%ptr1
+  %val2 = load float , float *%ptr2
+  %val3 = load float , float *%ptr3
+  %val4 = load float , float *%ptr4
+  %val5 = load float , float *%ptr5
+  %val6 = load float , float *%ptr6
+  %val7 = load float , float *%ptr7
+  %val8 = load float , float *%ptr8
+  %val9 = load float , float *%ptr9
+  %val10 = load float , float *%ptr10
 
   %ret = call float @foo()
 
diff --git a/test/CodeGen/SystemZ/fp-mul-02.ll b/test/CodeGen/SystemZ/fp-mul-02.ll
index cf4448fd7dd1..8435c3f5d3a1 100644
--- a/test/CodeGen/SystemZ/fp-mul-02.ll
+++ b/test/CodeGen/SystemZ/fp-mul-02.ll
@@ -20,7 +20,7 @@ define double @f2(float %f1, float *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: mdeb %f0, 0(%r2)
 ; CHECK: br %r14
-  %f2 = load float *%ptr
+  %f2 = load float , float *%ptr
   %f1x = fpext float %f1 to double
   %f2x = fpext float %f2 to double
   %res = fmul double %f1x, %f2x
@@ -32,8 +32,8 @@ define double @f3(float %f1, float *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: mdeb %f0, 4092(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1023
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1023
+  %f2 = load float , float *%ptr
   %f1x = fpext float %f1 to double
   %f2x = fpext float %f2 to double
   %res = fmul double %f1x, %f2x
@@ -47,8 +47,8 @@ define double @f4(float %f1, float *%base) {
 ; CHECK: aghi %r2, 4096
 ; CHECK: mdeb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1024
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1024
+  %f2 = load float , float *%ptr
   %f1x = fpext float %f1 to double
   %f2x = fpext float %f2 to double
   %res = fmul double %f1x, %f2x
@@ -61,8 +61,8 @@ define double @f5(float %f1, float *%base) {
 ; CHECK: aghi %r2, -4
 ; CHECK: mdeb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 -1
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 -1
+  %f2 = load float , float *%ptr
   %f1x = fpext float %f1 to double
   %f2x = fpext float %f2 to double
   %res = fmul double %f1x, %f2x
@@ -75,9 +75,9 @@ define double @f6(float %f1, float *%base, i64 %index) {
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: mdeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%base, i64 %index
-  %ptr2 = getelementptr float *%ptr1, i64 100
-  %f2 = load float *%ptr2
+  %ptr1 = getelementptr float, float *%base, i64 %index
+  %ptr2 = getelementptr float, float *%ptr1, i64 100
+  %f2 = load float , float *%ptr2
   %f1x = fpext float %f1 to double
   %f2x = fpext float %f2 to double
   %res = fmul double %f1x, %f2x
@@ -90,28 +90,28 @@ define float @f7(float *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mdeb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%ptr0, i64 2
-  %ptr2 = getelementptr float *%ptr0, i64 4
-  %ptr3 = getelementptr float *%ptr0, i64 6
-  %ptr4 = getelementptr float *%ptr0, i64 8
-  %ptr5 = getelementptr float *%ptr0, i64 10
-  %ptr6 = getelementptr float *%ptr0, i64 12
-  %ptr7 = getelementptr float *%ptr0, i64 14
-  %ptr8 = getelementptr float *%ptr0, i64 16
-  %ptr9 = getelementptr float *%ptr0, i64 18
-  %ptr10 = getelementptr float *%ptr0, i64 20
-
-  %val0 = load float *%ptr0
-  %val1 = load float *%ptr1
-  %val2 = load float *%ptr2
-  %val3 = load float *%ptr3
-  %val4 = load float *%ptr4
-  %val5 = load float *%ptr5
-  %val6 = load float *%ptr6
-  %val7 = load float *%ptr7
-  %val8 = load float *%ptr8
-  %val9 = load float *%ptr9
-  %val10 = load float *%ptr10
+  %ptr1 = getelementptr float, float *%ptr0, i64 2
+  %ptr2 = getelementptr float, float *%ptr0, i64 4
+  %ptr3 = getelementptr float, float *%ptr0, i64 6
+  %ptr4 = getelementptr float, float *%ptr0, i64 8
+  %ptr5 = getelementptr float, float *%ptr0, i64 10
+  %ptr6 = getelementptr float, float *%ptr0, i64 12
+  %ptr7 = getelementptr float, float *%ptr0, i64 14
+  %ptr8 = getelementptr float, float *%ptr0, i64 16
+  %ptr9 = getelementptr float, float *%ptr0, i64 18
+  %ptr10 = getelementptr float, float *%ptr0, i64 20
+
+  %val0 = load float , float *%ptr0
+  %val1 = load float , float *%ptr1
+  %val2 = load float , float *%ptr2
+  %val3 = load float , float *%ptr3
+  %val4 = load float , float *%ptr4
+  %val5 = load float , float *%ptr5
+  %val6 = load float , float *%ptr6
+  %val7 = load float , float *%ptr7
+  %val8 = load float , float *%ptr8
+  %val9 = load float , float *%ptr9
+  %val10 = load float , float *%ptr10
 
   %frob0 = fadd float %val0, %val0
   %frob1 = fadd float %val1, %val1
diff --git a/test/CodeGen/SystemZ/fp-mul-03.ll b/test/CodeGen/SystemZ/fp-mul-03.ll
index 6d296f07d1f2..0d52121f41c6 100644
--- a/test/CodeGen/SystemZ/fp-mul-03.ll
+++ b/test/CodeGen/SystemZ/fp-mul-03.ll
@@ -1,6 +1,8 @@
 ; Test multiplication of two f64s, producing an f64 result.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 declare double @foo()
 
@@ -18,7 +20,7 @@ define double @f2(double %f1, double *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: mdb %f0, 0(%r2)
 ; CHECK: br %r14
-  %f2 = load double *%ptr
+  %f2 = load double , double *%ptr
   %res = fmul double %f1, %f2
   ret double %res
 }
@@ -28,8 +30,8 @@ define double @f3(double %f1, double *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: mdb %f0, 4088(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 511
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 511
+  %f2 = load double , double *%ptr
   %res = fmul double %f1, %f2
   ret double %res
 }
@@ -41,8 +43,8 @@ define double @f4(double %f1, double *%base) {
 ; CHECK: aghi %r2, 4096
 ; CHECK: mdb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 512
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 512
+  %f2 = load double , double *%ptr
   %res = fmul double %f1, %f2
   ret double %res
 }
@@ -53,8 +55,8 @@ define double @f5(double %f1, double *%base) {
 ; CHECK: aghi %r2, -8
 ; CHECK: mdb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 -1
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 -1
+  %f2 = load double , double *%ptr
   %res = fmul double %f1, %f2
   ret double %res
 }
@@ -65,9 +67,9 @@ define double @f6(double %f1, double *%base, i64 %index) {
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: mdb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
-  %ptr1 = getelementptr double *%base, i64 %index
-  %ptr2 = getelementptr double *%ptr1, i64 100
-  %f2 = load double *%ptr2
+  %ptr1 = getelementptr double, double *%base, i64 %index
+  %ptr2 = getelementptr double, double *%ptr1, i64 100
+  %f2 = load double , double *%ptr2
   %res = fmul double %f1, %f2
   ret double %res
 }
@@ -76,30 +78,30 @@ define double @f6(double %f1, double *%base, i64 %index) {
 define double @f7(double *%ptr0) {
 ; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
-; CHECK: mdb %f0, 160(%r15)
+; CHECK-SCALAR: mdb %f0, 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr double *%ptr0, i64 2
-  %ptr2 = getelementptr double *%ptr0, i64 4
-  %ptr3 = getelementptr double *%ptr0, i64 6
-  %ptr4 = getelementptr double *%ptr0, i64 8
-  %ptr5 = getelementptr double *%ptr0, i64 10
-  %ptr6 = getelementptr double *%ptr0, i64 12
-  %ptr7 = getelementptr double *%ptr0, i64 14
-  %ptr8 = getelementptr double *%ptr0, i64 16
-  %ptr9 = getelementptr double *%ptr0, i64 18
-  %ptr10 = getelementptr double *%ptr0, i64 20
+  %ptr1 = getelementptr double, double *%ptr0, i64 2
+  %ptr2 = getelementptr double, double *%ptr0, i64 4
+  %ptr3 = getelementptr double, double *%ptr0, i64 6
+  %ptr4 = getelementptr double, double *%ptr0, i64 8
+  %ptr5 = getelementptr double, double *%ptr0, i64 10
+  %ptr6 = getelementptr double, double *%ptr0, i64 12
+  %ptr7 = getelementptr double, double *%ptr0, i64 14
+  %ptr8 = getelementptr double, double *%ptr0, i64 16
+  %ptr9 = getelementptr double, double *%ptr0, i64 18
+  %ptr10 = getelementptr double, double *%ptr0, i64 20
 
-  %val0 = load double *%ptr0
-  %val1 = load double *%ptr1
-  %val2 = load double *%ptr2
-  %val3 = load double *%ptr3
-  %val4 = load double *%ptr4
-  %val5 = load double *%ptr5
-  %val6 = load double *%ptr6
-  %val7 = load double *%ptr7
-  %val8 = load double *%ptr8
-  %val9 = load double *%ptr9
-  %val10 = load double *%ptr10
+  %val0 = load double , double *%ptr0
+  %val1 = load double , double *%ptr1
+  %val2 = load double , double *%ptr2
+  %val3 = load double , double *%ptr3
+  %val4 = load double , double *%ptr4
+  %val5 = load double , double *%ptr5
+  %val6 = load double , double *%ptr6
+  %val7 = load double , double *%ptr7
+  %val8 = load double , double *%ptr8
+  %val9 = load double , double *%ptr9
+  %val10 = load double , double *%ptr10
 
   %ret = call double @foo()
 
diff --git a/test/CodeGen/SystemZ/fp-mul-04.ll b/test/CodeGen/SystemZ/fp-mul-04.ll
index 3c4325e6cbbb..4226a3f61dff 100644
--- a/test/CodeGen/SystemZ/fp-mul-04.ll
+++ b/test/CodeGen/SystemZ/fp-mul-04.ll
@@ -27,7 +27,7 @@ define void @f2(double %f1, double *%ptr, fp128 *%dst) {
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
 ; CHECK: br %r14
-  %f2 = load double *%ptr
+  %f2 = load double , double *%ptr
   %f1x = fpext double %f1 to fp128
   %f2x = fpext double %f2 to fp128
   %res = fmul fp128 %f1x, %f2x
@@ -42,8 +42,8 @@ define void @f3(double %f1, double *%base, fp128 *%dst) {
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 511
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 511
+  %f2 = load double , double *%ptr
   %f1x = fpext double %f1 to fp128
   %f2x = fpext double %f2 to fp128
   %res = fmul fp128 %f1x, %f2x
@@ -60,8 +60,8 @@ define void @f4(double %f1, double *%base, fp128 *%dst) {
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 512
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 512
+  %f2 = load double , double *%ptr
   %f1x = fpext double %f1 to fp128
   %f2x = fpext double %f2 to fp128
   %res = fmul fp128 %f1x, %f2x
@@ -77,8 +77,8 @@ define void @f5(double %f1, double *%base, fp128 *%dst) {
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 -1
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 -1
+  %f2 = load double , double *%ptr
   %f1x = fpext double %f1 to fp128
   %f2x = fpext double %f2 to fp128
   %res = fmul fp128 %f1x, %f2x
@@ -94,9 +94,9 @@ define void @f6(double %f1, double *%base, i64 %index, fp128 *%dst) {
 ; CHECK: std %f0, 0(%r4)
 ; CHECK: std %f2, 8(%r4)
 ; CHECK: br %r14
-  %ptr1 = getelementptr double *%base, i64 %index
-  %ptr2 = getelementptr double *%ptr1, i64 100
-  %f2 = load double *%ptr2
+  %ptr1 = getelementptr double, double *%base, i64 %index
+  %ptr2 = getelementptr double, double *%ptr1, i64 100
+  %f2 = load double , double *%ptr2
   %f1x = fpext double %f1 to fp128
   %f2x = fpext double %f2 to fp128
   %res = fmul fp128 %f1x, %f2x
@@ -110,28 +110,28 @@ define double @f7(double *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mxdb %f0, 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr double *%ptr0, i64 2
-  %ptr2 = getelementptr double *%ptr0, i64 4
-  %ptr3 = getelementptr double *%ptr0, i64 6
-  %ptr4 = getelementptr double *%ptr0, i64 8
-  %ptr5 = getelementptr double *%ptr0, i64 10
-  %ptr6 = getelementptr double *%ptr0, i64 12
-  %ptr7 = getelementptr double *%ptr0, i64 14
-  %ptr8 = getelementptr double *%ptr0, i64 16
-  %ptr9 = getelementptr double *%ptr0, i64 18
-  %ptr10 = getelementptr double *%ptr0, i64 20
-
-  %val0 = load double *%ptr0
-  %val1 = load double *%ptr1
-  %val2 = load double *%ptr2
-  %val3 = load double *%ptr3
-  %val4 = load double *%ptr4
-  %val5 = load double *%ptr5
-  %val6 = load double *%ptr6
-  %val7 = load double *%ptr7
-  %val8 = load double *%ptr8
-  %val9 = load double *%ptr9
-  %val10 = load double *%ptr10
+  %ptr1 = getelementptr double, double *%ptr0, i64 2
+  %ptr2 = getelementptr double, double *%ptr0, i64 4
+  %ptr3 = getelementptr double, double *%ptr0, i64 6
+  %ptr4 = getelementptr double, double *%ptr0, i64 8
+  %ptr5 = getelementptr double, double *%ptr0, i64 10
+  %ptr6 = getelementptr double, double *%ptr0, i64 12
+  %ptr7 = getelementptr double, double *%ptr0, i64 14
+  %ptr8 = getelementptr double, double *%ptr0, i64 16
+  %ptr9 = getelementptr double, double *%ptr0, i64 18
+  %ptr10 = getelementptr double, double *%ptr0, i64 20
+
+  %val0 = load double , double *%ptr0
+  %val1 = load double , double *%ptr1
+  %val2 = load double , double *%ptr2
+  %val3 = load double , double *%ptr3
+  %val4 = load double , double *%ptr4
+  %val5 = load double , double *%ptr5
+  %val6 = load double , double *%ptr6
+  %val7 = load double , double *%ptr7
+  %val8 = load double , double *%ptr8
+  %val9 = load double , double *%ptr9
+  %val10 = load double , double *%ptr10
 
   %frob0 = fadd double %val0, %val0
   %frob1 = fadd double %val1, %val1
diff --git a/test/CodeGen/SystemZ/fp-mul-05.ll b/test/CodeGen/SystemZ/fp-mul-05.ll
index 0be1fe8b41a0..48d0dcdcaff4 100644
--- a/test/CodeGen/SystemZ/fp-mul-05.ll
+++ b/test/CodeGen/SystemZ/fp-mul-05.ll
@@ -12,7 +12,7 @@ define void @f1(fp128 *%ptr, float %f2) {
 ; CHECK: std %f1, 0(%r2)
 ; CHECK: std %f3, 8(%r2)
 ; CHECK: br %r14
-  %f1 = load fp128 *%ptr
+  %f1 = load fp128 , fp128 *%ptr
   %f2x = fpext float %f2 to fp128
   %diff = fmul fp128 %f1, %f2x
   store fp128 %diff, fp128 *%ptr
diff --git a/test/CodeGen/SystemZ/fp-mul-06.ll b/test/CodeGen/SystemZ/fp-mul-06.ll
index 3f631a68b575..896fafecbdaf 100644
--- a/test/CodeGen/SystemZ/fp-mul-06.ll
+++ b/test/CodeGen/SystemZ/fp-mul-06.ll
@@ -16,7 +16,7 @@ define float @f2(float %f1, float *%ptr, float %acc) {
 ; CHECK: maeb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
-  %f2 = load float *%ptr
+  %f2 = load float , float *%ptr
   %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc)
   ret float %res
 }
@@ -26,8 +26,8 @@ define float @f3(float %f1, float *%base, float %acc) {
 ; CHECK: maeb %f2, %f0, 4092(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1023
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1023
+  %f2 = load float , float *%ptr
   %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc)
   ret float %res
 }
@@ -41,8 +41,8 @@ define float @f4(float %f1, float *%base, float %acc) {
 ; CHECK: maeb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1024
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1024
+  %f2 = load float , float *%ptr
   %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc)
   ret float %res
 }
@@ -56,8 +56,8 @@ define float @f5(float %f1, float *%base, float %acc) {
 ; CHECK: maeb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 -1
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 -1
+  %f2 = load float , float *%ptr
   %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc)
   ret float %res
 }
@@ -68,8 +68,8 @@ define float @f6(float %f1, float *%base, i64 %index, float %acc) {
 ; CHECK: maeb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 %index
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 %index
+  %f2 = load float , float *%ptr
   %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc)
   ret float %res
 }
@@ -81,8 +81,8 @@ define float @f7(float %f1, float *%base, i64 %index, float %acc) {
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
   %index2 = add i64 %index, 1023
-  %ptr = getelementptr float *%base, i64 %index2
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 %index2
+  %f2 = load float , float *%ptr
   %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc)
   ret float %res
 }
@@ -95,8 +95,8 @@ define float @f8(float %f1, float *%base, i64 %index, float %acc) {
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
   %index2 = add i64 %index, 1024
-  %ptr = getelementptr float *%base, i64 %index2
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 %index2
+  %f2 = load float , float *%ptr
   %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc)
   ret float %res
 }
diff --git a/test/CodeGen/SystemZ/fp-mul-07.ll b/test/CodeGen/SystemZ/fp-mul-07.ll
index e4f590447215..e0b4a5c5d780 100644
--- a/test/CodeGen/SystemZ/fp-mul-07.ll
+++ b/test/CodeGen/SystemZ/fp-mul-07.ll
@@ -1,11 +1,15 @@
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-VECTOR %s
 
 declare double @llvm.fma.f64(double %f1, double %f2, double %f3)
 
 define double @f1(double %f1, double %f2, double %acc) {
 ; CHECK-LABEL: f1:
-; CHECK: madbr %f4, %f0, %f2
-; CHECK: ldr %f0, %f4
+; CHECK-SCALAR: madbr %f4, %f0, %f2
+; CHECK-SCALAR: ldr %f0, %f4
+; CHECK-VECTOR: wfmadb %f0, %f0, %f2, %f4
 ; CHECK: br %r14
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc)
   ret double %res
@@ -16,7 +20,7 @@ define double @f2(double %f1, double *%ptr, double %acc) {
 ; CHECK: madb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %f2 = load double *%ptr
+  %f2 = load double , double *%ptr
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc)
   ret double %res
 }
@@ -26,8 +30,8 @@ define double @f3(double %f1, double *%base, double %acc) {
 ; CHECK: madb %f2, %f0, 4088(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 511
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 511
+  %f2 = load double , double *%ptr
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc)
   ret double %res
 }
@@ -41,8 +45,8 @@ define double @f4(double %f1, double *%base, double %acc) {
 ; CHECK: madb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 512
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 512
+  %f2 = load double , double *%ptr
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc)
   ret double %res
 }
@@ -56,8 +60,8 @@ define double @f5(double %f1, double *%base, double %acc) {
 ; CHECK: madb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 -1
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 -1
+  %f2 = load double , double *%ptr
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc)
   ret double %res
 }
@@ -68,8 +72,8 @@ define double @f6(double %f1, double *%base, i64 %index, double %acc) {
 ; CHECK: madb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 %index
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 %index
+  %f2 = load double , double *%ptr
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc)
   ret double %res
 }
@@ -81,8 +85,8 @@ define double @f7(double %f1, double *%base, i64 %index, double %acc) {
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %index2 = add i64 %index, 511
-  %ptr = getelementptr double *%base, i64 %index2
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 %index2
+  %f2 = load double , double *%ptr
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc)
   ret double %res
 }
@@ -95,8 +99,8 @@ define double @f8(double %f1, double *%base, i64 %index, double %acc) {
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %index2 = add i64 %index, 512
-  %ptr = getelementptr double *%base, i64 %index2
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 %index2
+  %f2 = load double , double *%ptr
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc)
   ret double %res
 }
diff --git a/test/CodeGen/SystemZ/fp-mul-08.ll b/test/CodeGen/SystemZ/fp-mul-08.ll
index ab5fcb2cbefd..5e5538bfacc9 100644
--- a/test/CodeGen/SystemZ/fp-mul-08.ll
+++ b/test/CodeGen/SystemZ/fp-mul-08.ll
@@ -17,7 +17,7 @@ define float @f2(float %f1, float *%ptr, float %acc) {
 ; CHECK: mseb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
-  %f2 = load float *%ptr
+  %f2 = load float , float *%ptr
   %negacc = fsub float -0.0, %acc
   %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc)
   ret float %res
@@ -28,8 +28,8 @@ define float @f3(float %f1, float *%base, float %acc) {
 ; CHECK: mseb %f2, %f0, 4092(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1023
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1023
+  %f2 = load float , float *%ptr
   %negacc = fsub float -0.0, %acc
   %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc)
   ret float %res
@@ -44,8 +44,8 @@ define float @f4(float %f1, float *%base, float %acc) {
 ; CHECK: mseb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1024
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1024
+  %f2 = load float , float *%ptr
   %negacc = fsub float -0.0, %acc
   %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc)
   ret float %res
@@ -60,8 +60,8 @@ define float @f5(float %f1, float *%base, float %acc) {
 ; CHECK: mseb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 -1
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 -1
+  %f2 = load float , float *%ptr
   %negacc = fsub float -0.0, %acc
   %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc)
   ret float %res
@@ -73,8 +73,8 @@ define float @f6(float %f1, float *%base, i64 %index, float %acc) {
 ; CHECK: mseb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 %index
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 %index
+  %f2 = load float , float *%ptr
   %negacc = fsub float -0.0, %acc
   %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc)
   ret float %res
@@ -87,8 +87,8 @@ define float @f7(float %f1, float *%base, i64 %index, float %acc) {
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
   %index2 = add i64 %index, 1023
-  %ptr = getelementptr float *%base, i64 %index2
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 %index2
+  %f2 = load float , float *%ptr
   %negacc = fsub float -0.0, %acc
   %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc)
   ret float %res
@@ -102,8 +102,8 @@ define float @f8(float %f1, float *%base, i64 %index, float %acc) {
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
   %index2 = add i64 %index, 1024
-  %ptr = getelementptr float *%base, i64 %index2
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 %index2
+  %f2 = load float , float *%ptr
   %negacc = fsub float -0.0, %acc
   %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc)
   ret float %res
diff --git a/test/CodeGen/SystemZ/fp-mul-09.ll b/test/CodeGen/SystemZ/fp-mul-09.ll
index 7e740968a8c7..927a8064823c 100644
--- a/test/CodeGen/SystemZ/fp-mul-09.ll
+++ b/test/CodeGen/SystemZ/fp-mul-09.ll
@@ -1,11 +1,15 @@
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-VECTOR %s
 
 declare double @llvm.fma.f64(double %f1, double %f2, double %f3)
 
 define double @f1(double %f1, double %f2, double %acc) {
 ; CHECK-LABEL: f1:
-; CHECK: msdbr %f4, %f0, %f2
-; CHECK: ldr %f0, %f4
+; CHECK-SCALAR: msdbr %f4, %f0, %f2
+; CHECK-SCALAR: ldr %f0, %f4
+; CHECK-VECTOR: wfmsdb %f0, %f0, %f2, %f4
 ; CHECK: br %r14
   %negacc = fsub double -0.0, %acc
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc)
@@ -17,7 +21,7 @@ define double @f2(double %f1, double *%ptr, double %acc) {
 ; CHECK: msdb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %f2 = load double *%ptr
+  %f2 = load double , double *%ptr
   %negacc = fsub double -0.0, %acc
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc)
   ret double %res
@@ -28,8 +32,8 @@ define double @f3(double %f1, double *%base, double %acc) {
 ; CHECK: msdb %f2, %f0, 4088(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 511
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 511
+  %f2 = load double , double *%ptr
   %negacc = fsub double -0.0, %acc
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc)
   ret double %res
@@ -44,8 +48,8 @@ define double @f4(double %f1, double *%base, double %acc) {
 ; CHECK: msdb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 512
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 512
+  %f2 = load double , double *%ptr
   %negacc = fsub double -0.0, %acc
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc)
   ret double %res
@@ -60,8 +64,8 @@ define double @f5(double %f1, double *%base, double %acc) {
 ; CHECK: msdb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 -1
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 -1
+  %f2 = load double , double *%ptr
   %negacc = fsub double -0.0, %acc
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc)
   ret double %res
@@ -73,8 +77,8 @@ define double @f6(double %f1, double *%base, i64 %index, double %acc) {
 ; CHECK: msdb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 %index
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 %index
+  %f2 = load double , double *%ptr
   %negacc = fsub double -0.0, %acc
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc)
   ret double %res
@@ -87,8 +91,8 @@ define double @f7(double %f1, double *%base, i64 %index, double %acc) {
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %index2 = add i64 %index, 511
-  %ptr = getelementptr double *%base, i64 %index2
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 %index2
+  %f2 = load double , double *%ptr
   %negacc = fsub double -0.0, %acc
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc)
   ret double %res
@@ -102,8 +106,8 @@ define double @f8(double %f1, double *%base, i64 %index, double %acc) {
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %index2 = add i64 %index, 512
-  %ptr = getelementptr double *%base, i64 %index2
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 %index2
+  %f2 = load double , double *%ptr
   %negacc = fsub double -0.0, %acc
   %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc)
   ret double %res
diff --git a/test/CodeGen/SystemZ/fp-neg-01.ll b/test/CodeGen/SystemZ/fp-neg-01.ll
index 1cc6d816fee3..fe2e5f67cf5b 100644
--- a/test/CodeGen/SystemZ/fp-neg-01.ll
+++ b/test/CodeGen/SystemZ/fp-neg-01.ll
@@ -1,6 +1,7 @@
 ; Test floating-point negation.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 ; Test f32.
 define float @f1(float %f) {
@@ -28,10 +29,10 @@ define void @f3(fp128 *%ptr, fp128 *%ptr2) {
 ; CHECK: lcxbr
 ; CHECK: dxbr
 ; CHECK: br %r14
-  %orig = load fp128 *%ptr
+  %orig = load fp128 , fp128 *%ptr
   %negzero = fpext float -0.0 to fp128
   %neg = fsub fp128 0xL00000000000000008000000000000000, %orig
-  %op2 = load fp128 *%ptr2
+  %op2 = load fp128 , fp128 *%ptr2
   %res = fdiv fp128 %neg, %op2
   store fp128 %res, fp128 *%ptr
   ret void
diff --git a/test/CodeGen/SystemZ/fp-round-01.ll b/test/CodeGen/SystemZ/fp-round-01.ll
index 565db5ad4f51..bdec02f19c83 100644
--- a/test/CodeGen/SystemZ/fp-round-01.ll
+++ b/test/CodeGen/SystemZ/fp-round-01.ll
@@ -28,7 +28,7 @@ define void @f3(fp128 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: fixbr %f0, 0, %f0
 ; CHECK: br %r14
-  %src = load fp128 *%ptr
+  %src = load fp128 , fp128 *%ptr
   %res = call fp128 @llvm.rint.f128(fp128 %src)
   store fp128 %res, fp128 *%ptr
   ret void
diff --git a/test/CodeGen/SystemZ/fp-round-02.ll b/test/CodeGen/SystemZ/fp-round-02.ll
index d79c9c47050a..428261478dc8 100644
--- a/test/CodeGen/SystemZ/fp-round-02.ll
+++ b/test/CodeGen/SystemZ/fp-round-02.ll
@@ -1,6 +1,9 @@
 ; Test rounding functions for z196 and above.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-VECTOR %s
 
 ; Test rint for f32.
 declare float @llvm.rint.f32(float %f)
@@ -16,7 +19,8 @@ define float @f1(float %f) {
 declare double @llvm.rint.f64(double %f)
 define double @f2(double %f) {
 ; CHECK-LABEL: f2:
-; CHECK: fidbr %f0, 0, %f0
+; CHECK-SCALAR: fidbr %f0, 0, %f0
+; CHECK-VECTOR: fidbra %f0, 0, %f0, 0
 ; CHECK: br %r14
   %res = call double @llvm.rint.f64(double %f)
   ret double %res
@@ -28,7 +32,7 @@ define void @f3(fp128 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: fixbr %f0, 0, %f0
 ; CHECK: br %r14
-  %src = load fp128 *%ptr
+  %src = load fp128 , fp128 *%ptr
   %res = call fp128 @llvm.rint.f128(fp128 %src)
   store fp128 %res, fp128 *%ptr
   ret void
@@ -60,7 +64,7 @@ define void @f6(fp128 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK: fixbra %f0, 0, %f0, 4
 ; CHECK: br %r14
-  %src = load fp128 *%ptr
+  %src = load fp128 , fp128 *%ptr
   %res = call fp128 @llvm.nearbyint.f128(fp128 %src)
   store fp128 %res, fp128 *%ptr
   ret void
@@ -92,7 +96,7 @@ define void @f9(fp128 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: fixbra %f0, 7, %f0, 4
 ; CHECK: br %r14
-  %src = load fp128 *%ptr
+  %src = load fp128 , fp128 *%ptr
   %res = call fp128 @llvm.floor.f128(fp128 %src)
   store fp128 %res, fp128 *%ptr
   ret void
@@ -124,7 +128,7 @@ define void @f12(fp128 *%ptr) {
 ; CHECK-LABEL: f12:
 ; CHECK: fixbra %f0, 6, %f0, 4
 ; CHECK: br %r14
-  %src = load fp128 *%ptr
+  %src = load fp128 , fp128 *%ptr
   %res = call fp128 @llvm.ceil.f128(fp128 %src)
   store fp128 %res, fp128 *%ptr
   ret void
@@ -156,7 +160,7 @@ define void @f15(fp128 *%ptr) {
 ; CHECK-LABEL: f15:
 ; CHECK: fixbra %f0, 5, %f0, 4
 ; CHECK: br %r14
-  %src = load fp128 *%ptr
+  %src = load fp128 , fp128 *%ptr
   %res = call fp128 @llvm.trunc.f128(fp128 %src)
   store fp128 %res, fp128 *%ptr
   ret void
@@ -188,7 +192,7 @@ define void @f18(fp128 *%ptr) {
 ; CHECK-LABEL: f18:
 ; CHECK: fixbra %f0, 1, %f0, 4
 ; CHECK: br %r14
-  %src = load fp128 *%ptr
+  %src = load fp128 , fp128 *%ptr
   %res = call fp128 @llvm.round.f128(fp128 %src)
   store fp128 %res, fp128 *%ptr
   ret void
diff --git a/test/CodeGen/SystemZ/fp-sqrt-01.ll b/test/CodeGen/SystemZ/fp-sqrt-01.ll
index 7465af456b83..e8bf65bdc981 100644
--- a/test/CodeGen/SystemZ/fp-sqrt-01.ll
+++ b/test/CodeGen/SystemZ/fp-sqrt-01.ll
@@ -19,7 +19,7 @@ define float @f2(float *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: sqeb %f0, 0(%r2)
 ; CHECK: br %r14
-  %val = load float *%ptr
+  %val = load float , float *%ptr
   %res = call float @llvm.sqrt.f32(float %val)
   ret float %res
 }
@@ -29,8 +29,8 @@ define float @f3(float *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: sqeb %f0, 4092(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1023
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1023
+  %val = load float , float *%ptr
   %res = call float @llvm.sqrt.f32(float %val)
   ret float %res
 }
@@ -42,8 +42,8 @@ define float @f4(float *%base) {
 ; CHECK: aghi %r2, 4096
 ; CHECK: sqeb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1024
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1024
+  %val = load float , float *%ptr
   %res = call float @llvm.sqrt.f32(float %val)
   ret float %res
 }
@@ -54,8 +54,8 @@ define float @f5(float *%base) {
 ; CHECK: aghi %r2, -4
 ; CHECK: sqeb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 -1
-  %val = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 -1
+  %val = load float , float *%ptr
   %res = call float @llvm.sqrt.f32(float %val)
   ret float %res
 }
@@ -66,9 +66,9 @@ define float @f6(float *%base, i64 %index) {
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: sqeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%base, i64 %index
-  %ptr2 = getelementptr float *%ptr1, i64 100
-  %val = load float *%ptr2
+  %ptr1 = getelementptr float, float *%base, i64 %index
+  %ptr2 = getelementptr float, float *%ptr1, i64 100
+  %val = load float , float *%ptr2
   %res = call float @llvm.sqrt.f32(float %val)
   ret float %res
 }
@@ -79,23 +79,23 @@ define void @f7(float *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK: sqeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile float *%ptr
-  %val1 = load volatile float *%ptr
-  %val2 = load volatile float *%ptr
-  %val3 = load volatile float *%ptr
-  %val4 = load volatile float *%ptr
-  %val5 = load volatile float *%ptr
-  %val6 = load volatile float *%ptr
-  %val7 = load volatile float *%ptr
-  %val8 = load volatile float *%ptr
-  %val9 = load volatile float *%ptr
-  %val10 = load volatile float *%ptr
-  %val11 = load volatile float *%ptr
-  %val12 = load volatile float *%ptr
-  %val13 = load volatile float *%ptr
-  %val14 = load volatile float *%ptr
-  %val15 = load volatile float *%ptr
-  %val16 = load volatile float *%ptr
+  %val0 = load volatile float , float *%ptr
+  %val1 = load volatile float , float *%ptr
+  %val2 = load volatile float , float *%ptr
+  %val3 = load volatile float , float *%ptr
+  %val4 = load volatile float , float *%ptr
+  %val5 = load volatile float , float *%ptr
+  %val6 = load volatile float , float *%ptr
+  %val7 = load volatile float , float *%ptr
+  %val8 = load volatile float , float *%ptr
+  %val9 = load volatile float , float *%ptr
+  %val10 = load volatile float , float *%ptr
+  %val11 = load volatile float , float *%ptr
+  %val12 = load volatile float , float *%ptr
+  %val13 = load volatile float , float *%ptr
+  %val14 = load volatile float , float *%ptr
+  %val15 = load volatile float , float *%ptr
+  %val16 = load volatile float , float *%ptr
 
   %sqrt0 = call float @llvm.sqrt.f32(float %val0)
   %sqrt1 = call float @llvm.sqrt.f32(float %val1)
diff --git a/test/CodeGen/SystemZ/fp-sqrt-02.ll b/test/CodeGen/SystemZ/fp-sqrt-02.ll
index 66ffd19d6c31..a162466064e8 100644
--- a/test/CodeGen/SystemZ/fp-sqrt-02.ll
+++ b/test/CodeGen/SystemZ/fp-sqrt-02.ll
@@ -1,6 +1,8 @@
 ; Test 64-bit square root.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 declare double @llvm.sqrt.f64(double %f)
 declare double @sqrt(double)
@@ -19,7 +21,7 @@ define double @f2(double *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: sqdb %f0, 0(%r2)
 ; CHECK: br %r14
-  %val = load double *%ptr
+  %val = load double , double *%ptr
   %res = call double @llvm.sqrt.f64(double %val)
   ret double %res
 }
@@ -29,8 +31,8 @@ define double @f3(double *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: sqdb %f0, 4088(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 511
-  %val = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 511
+  %val = load double , double *%ptr
   %res = call double @llvm.sqrt.f64(double %val)
   ret double %res
 }
@@ -42,8 +44,8 @@ define double @f4(double *%base) {
 ; CHECK: aghi %r2, 4096
 ; CHECK: sqdb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 512
-  %val = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 512
+  %val = load double , double *%ptr
   %res = call double @llvm.sqrt.f64(double %val)
   ret double %res
 }
@@ -54,8 +56,8 @@ define double @f5(double *%base) {
 ; CHECK: aghi %r2, -8
 ; CHECK: sqdb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 -1
-  %val = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 -1
+  %val = load double , double *%ptr
   %res = call double @llvm.sqrt.f64(double %val)
   ret double %res
 }
@@ -66,9 +68,9 @@ define double @f6(double *%base, i64 %index) {
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: sqdb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
-  %ptr1 = getelementptr double *%base, i64 %index
-  %ptr2 = getelementptr double *%ptr1, i64 100
-  %val = load double *%ptr2
+  %ptr1 = getelementptr double, double *%base, i64 %index
+  %ptr2 = getelementptr double, double *%ptr1, i64 100
+  %val = load double , double *%ptr2
   %res = call double @llvm.sqrt.f64(double %val)
   ret double %res
 }
@@ -77,25 +79,25 @@ define double @f6(double *%base, i64 %index) {
 ; to use SQDB if possible.
 define void @f7(double *%ptr) {
 ; CHECK-LABEL: f7:
-; CHECK: sqdb {{%f[0-9]+}}, 160(%r15)
+; CHECK-SCALAR: sqdb {{%f[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile double *%ptr
-  %val1 = load volatile double *%ptr
-  %val2 = load volatile double *%ptr
-  %val3 = load volatile double *%ptr
-  %val4 = load volatile double *%ptr
-  %val5 = load volatile double *%ptr
-  %val6 = load volatile double *%ptr
-  %val7 = load volatile double *%ptr
-  %val8 = load volatile double *%ptr
-  %val9 = load volatile double *%ptr
-  %val10 = load volatile double *%ptr
-  %val11 = load volatile double *%ptr
-  %val12 = load volatile double *%ptr
-  %val13 = load volatile double *%ptr
-  %val14 = load volatile double *%ptr
-  %val15 = load volatile double *%ptr
-  %val16 = load volatile double *%ptr
+  %val0 = load volatile double , double *%ptr
+  %val1 = load volatile double , double *%ptr
+  %val2 = load volatile double , double *%ptr
+  %val3 = load volatile double , double *%ptr
+  %val4 = load volatile double , double *%ptr
+  %val5 = load volatile double , double *%ptr
+  %val6 = load volatile double , double *%ptr
+  %val7 = load volatile double , double *%ptr
+  %val8 = load volatile double , double *%ptr
+  %val9 = load volatile double , double *%ptr
+  %val10 = load volatile double , double *%ptr
+  %val11 = load volatile double , double *%ptr
+  %val12 = load volatile double , double *%ptr
+  %val13 = load volatile double , double *%ptr
+  %val14 = load volatile double , double *%ptr
+  %val15 = load volatile double , double *%ptr
+  %val16 = load volatile double , double *%ptr
 
   %sqrt0 = call double @llvm.sqrt.f64(double %val0)
   %sqrt1 = call double @llvm.sqrt.f64(double %val1)
diff --git a/test/CodeGen/SystemZ/fp-sqrt-03.ll b/test/CodeGen/SystemZ/fp-sqrt-03.ll
index 71426440aca3..4bc05f100a0a 100644
--- a/test/CodeGen/SystemZ/fp-sqrt-03.ll
+++ b/test/CodeGen/SystemZ/fp-sqrt-03.ll
@@ -13,7 +13,7 @@ define void @f1(fp128 *%ptr) {
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
-  %orig = load fp128 *%ptr
+  %orig = load fp128 , fp128 *%ptr
   %sqrt = call fp128 @llvm.sqrt.f128(fp128 %orig)
   store fp128 %sqrt, fp128 *%ptr
   ret void
diff --git a/test/CodeGen/SystemZ/fp-sub-01.ll b/test/CodeGen/SystemZ/fp-sub-01.ll
index 76f46f626705..f4185ca3108d 100644
--- a/test/CodeGen/SystemZ/fp-sub-01.ll
+++ b/test/CodeGen/SystemZ/fp-sub-01.ll
@@ -18,7 +18,7 @@ define float @f2(float %f1, float *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: seb %f0, 0(%r2)
 ; CHECK: br %r14
-  %f2 = load float *%ptr
+  %f2 = load float , float *%ptr
   %res = fsub float %f1, %f2
   ret float %res
 }
@@ -28,8 +28,8 @@ define float @f3(float %f1, float *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: seb %f0, 4092(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1023
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1023
+  %f2 = load float , float *%ptr
   %res = fsub float %f1, %f2
   ret float %res
 }
@@ -41,8 +41,8 @@ define float @f4(float %f1, float *%base) {
 ; CHECK: aghi %r2, 4096
 ; CHECK: seb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 1024
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 1024
+  %f2 = load float , float *%ptr
   %res = fsub float %f1, %f2
   ret float %res
 }
@@ -53,8 +53,8 @@ define float @f5(float %f1, float *%base) {
 ; CHECK: aghi %r2, -4
 ; CHECK: seb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr float *%base, i64 -1
-  %f2 = load float *%ptr
+  %ptr = getelementptr float, float *%base, i64 -1
+  %f2 = load float , float *%ptr
   %res = fsub float %f1, %f2
   ret float %res
 }
@@ -65,9 +65,9 @@ define float @f6(float %f1, float *%base, i64 %index) {
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: seb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%base, i64 %index
-  %ptr2 = getelementptr float *%ptr1, i64 100
-  %f2 = load float *%ptr2
+  %ptr1 = getelementptr float, float *%base, i64 %index
+  %ptr2 = getelementptr float, float *%ptr1, i64 100
+  %f2 = load float , float *%ptr2
   %res = fsub float %f1, %f2
   ret float %res
 }
@@ -78,28 +78,28 @@ define float @f7(float *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: seb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%ptr0, i64 2
-  %ptr2 = getelementptr float *%ptr0, i64 4
-  %ptr3 = getelementptr float *%ptr0, i64 6
-  %ptr4 = getelementptr float *%ptr0, i64 8
-  %ptr5 = getelementptr float *%ptr0, i64 10
-  %ptr6 = getelementptr float *%ptr0, i64 12
-  %ptr7 = getelementptr float *%ptr0, i64 14
-  %ptr8 = getelementptr float *%ptr0, i64 16
-  %ptr9 = getelementptr float *%ptr0, i64 18
-  %ptr10 = getelementptr float *%ptr0, i64 20
+  %ptr1 = getelementptr float, float *%ptr0, i64 2
+  %ptr2 = getelementptr float, float *%ptr0, i64 4
+  %ptr3 = getelementptr float, float *%ptr0, i64 6
+  %ptr4 = getelementptr float, float *%ptr0, i64 8
+  %ptr5 = getelementptr float, float *%ptr0, i64 10
+  %ptr6 = getelementptr float, float *%ptr0, i64 12
+  %ptr7 = getelementptr float, float *%ptr0, i64 14
+  %ptr8 = getelementptr float, float *%ptr0, i64 16
+  %ptr9 = getelementptr float, float *%ptr0, i64 18
+  %ptr10 = getelementptr float, float *%ptr0, i64 20
 
-  %val0 = load float *%ptr0
-  %val1 = load float *%ptr1
-  %val2 = load float *%ptr2
-  %val3 = load float *%ptr3
-  %val4 = load float *%ptr4
-  %val5 = load float *%ptr5
-  %val6 = load float *%ptr6
-  %val7 = load float *%ptr7
-  %val8 = load float *%ptr8
-  %val9 = load float *%ptr9
-  %val10 = load float *%ptr10
+  %val0 = load float , float *%ptr0
+  %val1 = load float , float *%ptr1
+  %val2 = load float , float *%ptr2
+  %val3 = load float , float *%ptr3
+  %val4 = load float , float *%ptr4
+  %val5 = load float , float *%ptr5
+  %val6 = load float , float *%ptr6
+  %val7 = load float , float *%ptr7
+  %val8 = load float , float *%ptr8
+  %val9 = load float , float *%ptr9
+  %val10 = load float , float *%ptr10
 
   %ret = call float @foo()
 
diff --git a/test/CodeGen/SystemZ/fp-sub-02.ll b/test/CodeGen/SystemZ/fp-sub-02.ll
index 99cafed8d08b..143baac23e19 100644
--- a/test/CodeGen/SystemZ/fp-sub-02.ll
+++ b/test/CodeGen/SystemZ/fp-sub-02.ll
@@ -1,6 +1,8 @@
 ; Test 64-bit floating-point subtraction.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \
+; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 declare double @foo()
 
@@ -18,7 +20,7 @@ define double @f2(double %f1, double *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: sdb %f0, 0(%r2)
 ; CHECK: br %r14
-  %f2 = load double *%ptr
+  %f2 = load double , double *%ptr
   %res = fsub double %f1, %f2
   ret double %res
 }
@@ -28,8 +30,8 @@ define double @f3(double %f1, double *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: sdb %f0, 4088(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 511
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 511
+  %f2 = load double , double *%ptr
   %res = fsub double %f1, %f2
   ret double %res
 }
@@ -41,8 +43,8 @@ define double @f4(double %f1, double *%base) {
 ; CHECK: aghi %r2, 4096
 ; CHECK: sdb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 512
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 512
+  %f2 = load double , double *%ptr
   %res = fsub double %f1, %f2
   ret double %res
 }
@@ -53,8 +55,8 @@ define double @f5(double %f1, double *%base) {
 ; CHECK: aghi %r2, -8
 ; CHECK: sdb %f0, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr double *%base, i64 -1
-  %f2 = load double *%ptr
+  %ptr = getelementptr double, double *%base, i64 -1
+  %f2 = load double , double *%ptr
   %res = fsub double %f1, %f2
   ret double %res
 }
@@ -65,9 +67,9 @@ define double @f6(double %f1, double *%base, i64 %index) {
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: sdb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
-  %ptr1 = getelementptr double *%base, i64 %index
-  %ptr2 = getelementptr double *%ptr1, i64 100
-  %f2 = load double *%ptr2
+  %ptr1 = getelementptr double, double *%base, i64 %index
+  %ptr2 = getelementptr double, double *%ptr1, i64 100
+  %f2 = load double , double *%ptr2
   %res = fsub double %f1, %f2
   ret double %res
 }
@@ -76,30 +78,30 @@ define double @f6(double %f1, double *%base, i64 %index) {
 define double @f7(double *%ptr0) {
 ; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
-; CHECK: sdb %f0, 16{{[04]}}(%r15)
+; CHECK-SCALAR: sdb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr double *%ptr0, i64 2
-  %ptr2 = getelementptr double *%ptr0, i64 4
-  %ptr3 = getelementptr double *%ptr0, i64 6
-  %ptr4 = getelementptr double *%ptr0, i64 8
-  %ptr5 = getelementptr double *%ptr0, i64 10
-  %ptr6 = getelementptr double *%ptr0, i64 12
-  %ptr7 = getelementptr double *%ptr0, i64 14
-  %ptr8 = getelementptr double *%ptr0, i64 16
-  %ptr9 = getelementptr double *%ptr0, i64 18
-  %ptr10 = getelementptr double *%ptr0, i64 20
+  %ptr1 = getelementptr double, double *%ptr0, i64 2
+  %ptr2 = getelementptr double, double *%ptr0, i64 4
+  %ptr3 = getelementptr double, double *%ptr0, i64 6
+  %ptr4 = getelementptr double, double *%ptr0, i64 8
+  %ptr5 = getelementptr double, double *%ptr0, i64 10
+  %ptr6 = getelementptr double, double *%ptr0, i64 12
+  %ptr7 = getelementptr double, double *%ptr0, i64 14
+  %ptr8 = getelementptr double, double *%ptr0, i64 16
+  %ptr9 = getelementptr double, double *%ptr0, i64 18
+  %ptr10 = getelementptr double, double *%ptr0, i64 20
 
-  %val0 = load double *%ptr0
-  %val1 = load double *%ptr1
-  %val2 = load double *%ptr2
-  %val3 = load double *%ptr3
-  %val4 = load double *%ptr4
-  %val5 = load double *%ptr5
-  %val6 = load double *%ptr6
-  %val7 = load double *%ptr7
-  %val8 = load double *%ptr8
-  %val9 = load double *%ptr9
-  %val10 = load double *%ptr10
+  %val0 = load double , double *%ptr0
+  %val1 = load double , double *%ptr1
+  %val2 = load double , double *%ptr2
+  %val3 = load double , double *%ptr3
+  %val4 = load double , double *%ptr4
+  %val5 = load double , double *%ptr5
+  %val6 = load double , double *%ptr6
+  %val7 = load double , double *%ptr7
+  %val8 = load double , double *%ptr8
+  %val9 = load double , double *%ptr9
+  %val10 = load double , double *%ptr10
 
   %ret = call double @foo()
 
diff --git a/test/CodeGen/SystemZ/fp-sub-03.ll b/test/CodeGen/SystemZ/fp-sub-03.ll
index a1404c4ff0e7..86faafeaaca2 100644
--- a/test/CodeGen/SystemZ/fp-sub-03.ll
+++ b/test/CodeGen/SystemZ/fp-sub-03.ll
@@ -12,7 +12,7 @@ define void @f1(fp128 *%ptr, float %f2) {
 ; CHECK: std %f1, 0(%r2)
 ; CHECK: std %f3, 8(%r2)
 ; CHECK: br %r14
-  %f1 = load fp128 *%ptr
+  %f1 = load fp128 , fp128 *%ptr
   %f2x = fpext float %f2 to fp128
   %sum = fsub fp128 %f1, %f2x
   store fp128 %sum, fp128 *%ptr
diff --git a/test/CodeGen/SystemZ/frame-01.ll b/test/CodeGen/SystemZ/frame-01.ll
index f61836ca8552..5afc4f1cef34 100644
--- a/test/CodeGen/SystemZ/frame-01.ll
+++ b/test/CodeGen/SystemZ/frame-01.ll
@@ -31,7 +31,7 @@ define void @f2(i64 %x) {
 ; CHECK: aghi %r15, 32760
 ; CHECK: br %r14
   %y = alloca [4073 x i64], align 8
-  %ptr = getelementptr inbounds [4073 x i64]* %y, i64 0, i64 0
+  %ptr = getelementptr inbounds [4073 x i64], [4073 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
@@ -46,7 +46,7 @@ define void @f3(i64 %x) {
 ; CHECK: agfi %r15, 32768
 ; CHECK: br %r14
   %y = alloca [4074 x i64], align 8
-  %ptr = getelementptr inbounds [4074 x i64]* %y, i64 0, i64 0
+  %ptr = getelementptr inbounds [4074 x i64], [4074 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
@@ -61,7 +61,7 @@ define void @f4(i64 %x) {
 ; CHECK: agfi %r15, 32776
 ; CHECK: br %r14
   %y = alloca [4075 x i64], align 8
-  %ptr = getelementptr inbounds [4075 x i64]* %y, i64 0, i64 0
+  %ptr = getelementptr inbounds [4075 x i64], [4075 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
@@ -75,7 +75,7 @@ define void @f5(i64 %x) {
 ; CHECK: agfi %r15, 2147483640
 ; CHECK: br %r14
   %y = alloca [268435433 x i64], align 8
-  %ptr = getelementptr inbounds [268435433 x i64]* %y, i64 0, i64 0
+  %ptr = getelementptr inbounds [268435433 x i64], [268435433 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
@@ -90,7 +90,7 @@ define void @f6(i64 %x) {
 ; CHECK: aghi %r15, 8
 ; CHECK: br %r14
   %y = alloca [268435434 x i64], align 8
-  %ptr = getelementptr inbounds [268435434 x i64]* %y, i64 0, i64 0
+  %ptr = getelementptr inbounds [268435434 x i64], [268435434 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
@@ -106,7 +106,7 @@ define void @f7(i64 %x) {
 ; CHECK: aghi %r15, 16
 ; CHECK: br %r14
   %y = alloca [268435435 x i64], align 8
-  %ptr = getelementptr inbounds [268435435 x i64]* %y, i64 0, i64 0
+  %ptr = getelementptr inbounds [268435435 x i64], [268435435 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
diff --git a/test/CodeGen/SystemZ/frame-02.ll b/test/CodeGen/SystemZ/frame-02.ll
index 9a7f8eac9eba..a41db77e851a 100644
--- a/test/CodeGen/SystemZ/frame-02.ll
+++ b/test/CodeGen/SystemZ/frame-02.ll
@@ -37,22 +37,22 @@ define void @f1(float *%ptr) {
 ; CHECK: ld %f15, 160(%r15)
 ; CHECK: aghi %r15, 224
 ; CHECK: br %r14
-  %l0 = load volatile float *%ptr
-  %l1 = load volatile float *%ptr
-  %l2 = load volatile float *%ptr
-  %l3 = load volatile float *%ptr
-  %l4 = load volatile float *%ptr
-  %l5 = load volatile float *%ptr
-  %l6 = load volatile float *%ptr
-  %l7 = load volatile float *%ptr
-  %l8 = load volatile float *%ptr
-  %l9 = load volatile float *%ptr
-  %l10 = load volatile float *%ptr
-  %l11 = load volatile float *%ptr
-  %l12 = load volatile float *%ptr
-  %l13 = load volatile float *%ptr
-  %l14 = load volatile float *%ptr
-  %l15 = load volatile float *%ptr
+  %l0 = load volatile float , float *%ptr
+  %l1 = load volatile float , float *%ptr
+  %l2 = load volatile float , float *%ptr
+  %l3 = load volatile float , float *%ptr
+  %l4 = load volatile float , float *%ptr
+  %l5 = load volatile float , float *%ptr
+  %l6 = load volatile float , float *%ptr
+  %l7 = load volatile float , float *%ptr
+  %l8 = load volatile float , float *%ptr
+  %l9 = load volatile float , float *%ptr
+  %l10 = load volatile float , float *%ptr
+  %l11 = load volatile float , float *%ptr
+  %l12 = load volatile float , float *%ptr
+  %l13 = load volatile float , float *%ptr
+  %l14 = load volatile float , float *%ptr
+  %l15 = load volatile float , float *%ptr
   %add0 = fadd float %l0, %l0
   %add1 = fadd float %l1, %add0
   %add2 = fadd float %l2, %add1
@@ -119,21 +119,21 @@ define void @f2(float *%ptr) {
 ; CHECK: ld %f14, 160(%r15)
 ; CHECK: aghi %r15, 216
 ; CHECK: br %r14
-  %l0 = load volatile float *%ptr
-  %l1 = load volatile float *%ptr
-  %l2 = load volatile float *%ptr
-  %l3 = load volatile float *%ptr
-  %l4 = load volatile float *%ptr
-  %l5 = load volatile float *%ptr
-  %l6 = load volatile float *%ptr
-  %l7 = load volatile float *%ptr
-  %l8 = load volatile float *%ptr
-  %l9 = load volatile float *%ptr
-  %l10 = load volatile float *%ptr
-  %l11 = load volatile float *%ptr
-  %l12 = load volatile float *%ptr
-  %l13 = load volatile float *%ptr
-  %l14 = load volatile float *%ptr
+  %l0 = load volatile float , float *%ptr
+  %l1 = load volatile float , float *%ptr
+  %l2 = load volatile float , float *%ptr
+  %l3 = load volatile float , float *%ptr
+  %l4 = load volatile float , float *%ptr
+  %l5 = load volatile float , float *%ptr
+  %l6 = load volatile float , float *%ptr
+  %l7 = load volatile float , float *%ptr
+  %l8 = load volatile float , float *%ptr
+  %l9 = load volatile float , float *%ptr
+  %l10 = load volatile float , float *%ptr
+  %l11 = load volatile float , float *%ptr
+  %l12 = load volatile float , float *%ptr
+  %l13 = load volatile float , float *%ptr
+  %l14 = load volatile float , float *%ptr
   %add0 = fadd float %l0, %l0
   %add1 = fadd float %l1, %add0
   %add2 = fadd float %l2, %add1
@@ -185,15 +185,15 @@ define void @f3(float *%ptr) {
 ; CHECK: ld %f8, 160(%r15)
 ; CHECK: aghi %r15, 168
 ; CHECK: br %r14
-  %l0 = load volatile float *%ptr
-  %l1 = load volatile float *%ptr
-  %l2 = load volatile float *%ptr
-  %l3 = load volatile float *%ptr
-  %l4 = load volatile float *%ptr
-  %l5 = load volatile float *%ptr
-  %l6 = load volatile float *%ptr
-  %l7 = load volatile float *%ptr
-  %l8 = load volatile float *%ptr
+  %l0 = load volatile float , float *%ptr
+  %l1 = load volatile float , float *%ptr
+  %l2 = load volatile float , float *%ptr
+  %l3 = load volatile float , float *%ptr
+  %l4 = load volatile float , float *%ptr
+  %l5 = load volatile float , float *%ptr
+  %l6 = load volatile float , float *%ptr
+  %l7 = load volatile float , float *%ptr
+  %l8 = load volatile float , float *%ptr
   %add0 = fadd float %l0, %l0
   %add1 = fadd float %l1, %add0
   %add2 = fadd float %l2, %add1
@@ -229,14 +229,14 @@ define void @f4(float *%ptr) {
 ; CHECK-NOT: %f14
 ; CHECK-NOT: %f15
 ; CHECK: br %r14
-  %l0 = load volatile float *%ptr
-  %l1 = load volatile float *%ptr
-  %l2 = load volatile float *%ptr
-  %l3 = load volatile float *%ptr
-  %l4 = load volatile float *%ptr
-  %l5 = load volatile float *%ptr
-  %l6 = load volatile float *%ptr
-  %l7 = load volatile float *%ptr
+  %l0 = load volatile float , float *%ptr
+  %l1 = load volatile float , float *%ptr
+  %l2 = load volatile float , float *%ptr
+  %l3 = load volatile float , float *%ptr
+  %l4 = load volatile float , float *%ptr
+  %l5 = load volatile float , float *%ptr
+  %l6 = load volatile float , float *%ptr
+  %l7 = load volatile float , float *%ptr
   %add0 = fadd float %l0, %l0
   %add1 = fadd float %l1, %add0
   %add2 = fadd float %l2, %add1
diff --git a/test/CodeGen/SystemZ/frame-03.ll b/test/CodeGen/SystemZ/frame-03.ll
index db146c7c985d..21b8fdb0d672 100644
--- a/test/CodeGen/SystemZ/frame-03.ll
+++ b/test/CodeGen/SystemZ/frame-03.ll
@@ -2,7 +2,7 @@
 ; uses a different register class, but the set of saved and restored
 ; registers should be the same.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; This function should require all FPRs, but no other spill slots.
 ; We need to save and restore 8 of the 16 FPRs, so the frame size
@@ -39,22 +39,22 @@ define void @f1(double *%ptr) {
 ; CHECK: ld %f15, 160(%r15)
 ; CHECK: aghi %r15, 224
 ; CHECK: br %r14
-  %l0 = load volatile double *%ptr
-  %l1 = load volatile double *%ptr
-  %l2 = load volatile double *%ptr
-  %l3 = load volatile double *%ptr
-  %l4 = load volatile double *%ptr
-  %l5 = load volatile double *%ptr
-  %l6 = load volatile double *%ptr
-  %l7 = load volatile double *%ptr
-  %l8 = load volatile double *%ptr
-  %l9 = load volatile double *%ptr
-  %l10 = load volatile double *%ptr
-  %l11 = load volatile double *%ptr
-  %l12 = load volatile double *%ptr
-  %l13 = load volatile double *%ptr
-  %l14 = load volatile double *%ptr
-  %l15 = load volatile double *%ptr
+  %l0 = load volatile double , double *%ptr
+  %l1 = load volatile double , double *%ptr
+  %l2 = load volatile double , double *%ptr
+  %l3 = load volatile double , double *%ptr
+  %l4 = load volatile double , double *%ptr
+  %l5 = load volatile double , double *%ptr
+  %l6 = load volatile double , double *%ptr
+  %l7 = load volatile double , double *%ptr
+  %l8 = load volatile double , double *%ptr
+  %l9 = load volatile double , double *%ptr
+  %l10 = load volatile double , double *%ptr
+  %l11 = load volatile double , double *%ptr
+  %l12 = load volatile double , double *%ptr
+  %l13 = load volatile double , double *%ptr
+  %l14 = load volatile double , double *%ptr
+  %l15 = load volatile double , double *%ptr
   %add0 = fadd double %l0, %l0
   %add1 = fadd double %l1, %add0
   %add2 = fadd double %l2, %add1
@@ -121,21 +121,21 @@ define void @f2(double *%ptr) {
 ; CHECK: ld %f14, 160(%r15)
 ; CHECK: aghi %r15, 216
 ; CHECK: br %r14
-  %l0 = load volatile double *%ptr
-  %l1 = load volatile double *%ptr
-  %l2 = load volatile double *%ptr
-  %l3 = load volatile double *%ptr
-  %l4 = load volatile double *%ptr
-  %l5 = load volatile double *%ptr
-  %l6 = load volatile double *%ptr
-  %l7 = load volatile double *%ptr
-  %l8 = load volatile double *%ptr
-  %l9 = load volatile double *%ptr
-  %l10 = load volatile double *%ptr
-  %l11 = load volatile double *%ptr
-  %l12 = load volatile double *%ptr
-  %l13 = load volatile double *%ptr
-  %l14 = load volatile double *%ptr
+  %l0 = load volatile double , double *%ptr
+  %l1 = load volatile double , double *%ptr
+  %l2 = load volatile double , double *%ptr
+  %l3 = load volatile double , double *%ptr
+  %l4 = load volatile double , double *%ptr
+  %l5 = load volatile double , double *%ptr
+  %l6 = load volatile double , double *%ptr
+  %l7 = load volatile double , double *%ptr
+  %l8 = load volatile double , double *%ptr
+  %l9 = load volatile double , double *%ptr
+  %l10 = load volatile double , double *%ptr
+  %l11 = load volatile double , double *%ptr
+  %l12 = load volatile double , double *%ptr
+  %l13 = load volatile double , double *%ptr
+  %l14 = load volatile double , double *%ptr
   %add0 = fadd double %l0, %l0
   %add1 = fadd double %l1, %add0
   %add2 = fadd double %l2, %add1
@@ -187,15 +187,15 @@ define void @f3(double *%ptr) {
 ; CHECK: ld %f8, 160(%r15)
 ; CHECK: aghi %r15, 168
 ; CHECK: br %r14
-  %l0 = load volatile double *%ptr
-  %l1 = load volatile double *%ptr
-  %l2 = load volatile double *%ptr
-  %l3 = load volatile double *%ptr
-  %l4 = load volatile double *%ptr
-  %l5 = load volatile double *%ptr
-  %l6 = load volatile double *%ptr
-  %l7 = load volatile double *%ptr
-  %l8 = load volatile double *%ptr
+  %l0 = load volatile double , double *%ptr
+  %l1 = load volatile double , double *%ptr
+  %l2 = load volatile double , double *%ptr
+  %l3 = load volatile double , double *%ptr
+  %l4 = load volatile double , double *%ptr
+  %l5 = load volatile double , double *%ptr
+  %l6 = load volatile double , double *%ptr
+  %l7 = load volatile double , double *%ptr
+  %l8 = load volatile double , double *%ptr
   %add0 = fadd double %l0, %l0
   %add1 = fadd double %l1, %add0
   %add2 = fadd double %l2, %add1
@@ -231,14 +231,14 @@ define void @f4(double *%ptr) {
 ; CHECK-NOT: %f14
 ; CHECK-NOT: %f15
 ; CHECK: br %r14
-  %l0 = load volatile double *%ptr
-  %l1 = load volatile double *%ptr
-  %l2 = load volatile double *%ptr
-  %l3 = load volatile double *%ptr
-  %l4 = load volatile double *%ptr
-  %l5 = load volatile double *%ptr
-  %l6 = load volatile double *%ptr
-  %l7 = load volatile double *%ptr
+  %l0 = load volatile double , double *%ptr
+  %l1 = load volatile double , double *%ptr
+  %l2 = load volatile double , double *%ptr
+  %l3 = load volatile double , double *%ptr
+  %l4 = load volatile double , double *%ptr
+  %l5 = load volatile double , double *%ptr
+  %l6 = load volatile double , double *%ptr
+  %l7 = load volatile double , double *%ptr
   %add0 = fadd double %l0, %l0
   %add1 = fadd double %l1, %add0
   %add2 = fadd double %l2, %add1
diff --git a/test/CodeGen/SystemZ/frame-04.ll b/test/CodeGen/SystemZ/frame-04.ll
index 93c59a3bc15f..602050978d30 100644
--- a/test/CodeGen/SystemZ/frame-04.ll
+++ b/test/CodeGen/SystemZ/frame-04.ll
@@ -38,14 +38,14 @@ define void @f1(fp128 *%ptr) {
 ; CHECK: ld %f15, 160(%r15)
 ; CHECK: aghi %r15, 224
 ; CHECK: br %r14
-  %l0 = load volatile fp128 *%ptr
-  %l1 = load volatile fp128 *%ptr
-  %l4 = load volatile fp128 *%ptr
-  %l5 = load volatile fp128 *%ptr
-  %l8 = load volatile fp128 *%ptr
-  %l9 = load volatile fp128 *%ptr
-  %l12 = load volatile fp128 *%ptr
-  %l13 = load volatile fp128 *%ptr
+  %l0 = load volatile fp128 , fp128 *%ptr
+  %l1 = load volatile fp128 , fp128 *%ptr
+  %l4 = load volatile fp128 , fp128 *%ptr
+  %l5 = load volatile fp128 , fp128 *%ptr
+  %l8 = load volatile fp128 , fp128 *%ptr
+  %l9 = load volatile fp128 , fp128 *%ptr
+  %l12 = load volatile fp128 , fp128 *%ptr
+  %l13 = load volatile fp128 , fp128 *%ptr
   %add0 = fadd fp128 %l0, %l0
   %add1 = fadd fp128 %l1, %add0
   %add4 = fadd fp128 %l4, %add1
@@ -94,13 +94,13 @@ define void @f2(fp128 *%ptr) {
 ; CHECK: ld %f14, 160(%r15)
 ; CHECK: aghi %r15, 208
 ; CHECK: br %r14
-  %l0 = load volatile fp128 *%ptr
-  %l1 = load volatile fp128 *%ptr
-  %l4 = load volatile fp128 *%ptr
-  %l5 = load volatile fp128 *%ptr
-  %l8 = load volatile fp128 *%ptr
-  %l9 = load volatile fp128 *%ptr
-  %l12 = load volatile fp128 *%ptr
+  %l0 = load volatile fp128 , fp128 *%ptr
+  %l1 = load volatile fp128 , fp128 *%ptr
+  %l4 = load volatile fp128 , fp128 *%ptr
+  %l5 = load volatile fp128 , fp128 *%ptr
+  %l8 = load volatile fp128 , fp128 *%ptr
+  %l9 = load volatile fp128 , fp128 *%ptr
+  %l12 = load volatile fp128 , fp128 *%ptr
   %add0 = fadd fp128 %l0, %l0
   %add1 = fadd fp128 %l1, %add0
   %add4 = fadd fp128 %l4, %add1
@@ -139,11 +139,11 @@ define void @f3(fp128 *%ptr) {
 ; CHECK: ld %f10, 160(%r15)
 ; CHECK: aghi %r15, 176
 ; CHECK: br %r14
-  %l0 = load volatile fp128 *%ptr
-  %l1 = load volatile fp128 *%ptr
-  %l4 = load volatile fp128 *%ptr
-  %l5 = load volatile fp128 *%ptr
-  %l8 = load volatile fp128 *%ptr
+  %l0 = load volatile fp128 , fp128 *%ptr
+  %l1 = load volatile fp128 , fp128 *%ptr
+  %l4 = load volatile fp128 , fp128 *%ptr
+  %l5 = load volatile fp128 , fp128 *%ptr
+  %l8 = load volatile fp128 , fp128 *%ptr
   %add0 = fadd fp128 %l0, %l0
   %add1 = fadd fp128 %l1, %add0
   %add4 = fadd fp128 %l4, %add1
@@ -171,10 +171,10 @@ define void @f4(fp128 *%ptr) {
 ; CHECK-NOT: %f14
 ; CHECK-NOT: %f15
 ; CHECK: br %r14
-  %l0 = load volatile fp128 *%ptr
-  %l1 = load volatile fp128 *%ptr
-  %l4 = load volatile fp128 *%ptr
-  %l5 = load volatile fp128 *%ptr
+  %l0 = load volatile fp128 , fp128 *%ptr
+  %l1 = load volatile fp128 , fp128 *%ptr
+  %l4 = load volatile fp128 , fp128 *%ptr
+  %l5 = load volatile fp128 , fp128 *%ptr
   %add0 = fadd fp128 %l0, %l0
   %add1 = fadd fp128 %l1, %add0
   %add4 = fadd fp128 %l4, %add1
diff --git a/test/CodeGen/SystemZ/frame-05.ll b/test/CodeGen/SystemZ/frame-05.ll
index f95284deeb79..93130dcbfbbc 100644
--- a/test/CodeGen/SystemZ/frame-05.ll
+++ b/test/CodeGen/SystemZ/frame-05.ll
@@ -32,20 +32,20 @@ define void @f1(i32 *%ptr) {
 ; CHECK: st {{.*}}, 4(%r2)
 ; CHECK: lmg %r6, %r15, 48(%r15)
 ; CHECK: br %r14
-  %l0 = load volatile i32 *%ptr
-  %l1 = load volatile i32 *%ptr
-  %l3 = load volatile i32 *%ptr
-  %l4 = load volatile i32 *%ptr
-  %l5 = load volatile i32 *%ptr
-  %l6 = load volatile i32 *%ptr
-  %l7 = load volatile i32 *%ptr
-  %l8 = load volatile i32 *%ptr
-  %l9 = load volatile i32 *%ptr
-  %l10 = load volatile i32 *%ptr
-  %l11 = load volatile i32 *%ptr
-  %l12 = load volatile i32 *%ptr
-  %l13 = load volatile i32 *%ptr
-  %l14 = load volatile i32 *%ptr
+  %l0 = load volatile i32 , i32 *%ptr
+  %l1 = load volatile i32 , i32 *%ptr
+  %l3 = load volatile i32 , i32 *%ptr
+  %l4 = load volatile i32 , i32 *%ptr
+  %l5 = load volatile i32 , i32 *%ptr
+  %l6 = load volatile i32 , i32 *%ptr
+  %l7 = load volatile i32 , i32 *%ptr
+  %l8 = load volatile i32 , i32 *%ptr
+  %l9 = load volatile i32 , i32 *%ptr
+  %l10 = load volatile i32 , i32 *%ptr
+  %l11 = load volatile i32 , i32 *%ptr
+  %l12 = load volatile i32 , i32 *%ptr
+  %l13 = load volatile i32 , i32 *%ptr
+  %l14 = load volatile i32 , i32 *%ptr
   %add0 = add i32 %l0, %l0
   %add1 = add i32 %l1, %add0
   %add3 = add i32 %l3, %add1
@@ -73,7 +73,7 @@ define void @f1(i32 *%ptr) {
   store volatile i32 %add11, i32 *%ptr
   store volatile i32 %add12, i32 *%ptr
   store volatile i32 %add13, i32 *%ptr
-  %final = getelementptr i32 *%ptr, i32 1
+  %final = getelementptr i32, i32 *%ptr, i32 1
   store volatile i32 %add14, i32 *%final
   ret void
 }
@@ -100,19 +100,19 @@ define void @f2(i32 *%ptr) {
 ; CHECK: st {{.*}}, 4(%r2)
 ; CHECK: lmg %r7, %r15, 56(%r15)
 ; CHECK: br %r14
-  %l0 = load volatile i32 *%ptr
-  %l1 = load volatile i32 *%ptr
-  %l3 = load volatile i32 *%ptr
-  %l4 = load volatile i32 *%ptr
-  %l5 = load volatile i32 *%ptr
-  %l7 = load volatile i32 *%ptr
-  %l8 = load volatile i32 *%ptr
-  %l9 = load volatile i32 *%ptr
-  %l10 = load volatile i32 *%ptr
-  %l11 = load volatile i32 *%ptr
-  %l12 = load volatile i32 *%ptr
-  %l13 = load volatile i32 *%ptr
-  %l14 = load volatile i32 *%ptr
+  %l0 = load volatile i32 , i32 *%ptr
+  %l1 = load volatile i32 , i32 *%ptr
+  %l3 = load volatile i32 , i32 *%ptr
+  %l4 = load volatile i32 , i32 *%ptr
+  %l5 = load volatile i32 , i32 *%ptr
+  %l7 = load volatile i32 , i32 *%ptr
+  %l8 = load volatile i32 , i32 *%ptr
+  %l9 = load volatile i32 , i32 *%ptr
+  %l10 = load volatile i32 , i32 *%ptr
+  %l11 = load volatile i32 , i32 *%ptr
+  %l12 = load volatile i32 , i32 *%ptr
+  %l13 = load volatile i32 , i32 *%ptr
+  %l14 = load volatile i32 , i32 *%ptr
   %add0 = add i32 %l0, %l0
   %add1 = add i32 %l1, %add0
   %add3 = add i32 %l3, %add1
@@ -138,7 +138,7 @@ define void @f2(i32 *%ptr) {
   store volatile i32 %add11, i32 *%ptr
   store volatile i32 %add12, i32 *%ptr
   store volatile i32 %add13, i32 *%ptr
-  %final = getelementptr i32 *%ptr, i32 1
+  %final = getelementptr i32, i32 *%ptr, i32 1
   store volatile i32 %add14, i32 *%final
   ret void
 }
@@ -163,12 +163,12 @@ define void @f3(i32 *%ptr) {
 ; CHECK: st {{.*}}, 4(%r2)
 ; CHECK: lmg %r14, %r15, 112(%r15)
 ; CHECK: br %r14
-  %l0 = load volatile i32 *%ptr
-  %l1 = load volatile i32 *%ptr
-  %l3 = load volatile i32 *%ptr
-  %l4 = load volatile i32 *%ptr
-  %l5 = load volatile i32 *%ptr
-  %l14 = load volatile i32 *%ptr
+  %l0 = load volatile i32 , i32 *%ptr
+  %l1 = load volatile i32 , i32 *%ptr
+  %l3 = load volatile i32 , i32 *%ptr
+  %l4 = load volatile i32 , i32 *%ptr
+  %l5 = load volatile i32 , i32 *%ptr
+  %l14 = load volatile i32 , i32 *%ptr
   %add0 = add i32 %l0, %l0
   %add1 = add i32 %l1, %add0
   %add3 = add i32 %l3, %add1
@@ -180,7 +180,7 @@ define void @f3(i32 *%ptr) {
   store volatile i32 %add3, i32 *%ptr
   store volatile i32 %add4, i32 *%ptr
   store volatile i32 %add5, i32 *%ptr
-  %final = getelementptr i32 *%ptr, i32 1
+  %final = getelementptr i32, i32 *%ptr, i32 1
   store volatile i32 %add14, i32 *%final
   ret void
 }
@@ -199,11 +199,11 @@ define void @f4(i32 *%ptr) {
 ; CHECK-NOT: %r12
 ; CHECK-NOT: %r13
 ; CHECK: br %r14
-  %l0 = load volatile i32 *%ptr
-  %l1 = load volatile i32 *%ptr
-  %l3 = load volatile i32 *%ptr
-  %l4 = load volatile i32 *%ptr
-  %l5 = load volatile i32 *%ptr
+  %l0 = load volatile i32 , i32 *%ptr
+  %l1 = load volatile i32 , i32 *%ptr
+  %l3 = load volatile i32 , i32 *%ptr
+  %l4 = load volatile i32 , i32 *%ptr
+  %l5 = load volatile i32 , i32 *%ptr
   %add0 = add i32 %l0, %l0
   %add1 = add i32 %l1, %add0
   %add3 = add i32 %l3, %add1
@@ -213,7 +213,7 @@ define void @f4(i32 *%ptr) {
   store volatile i32 %add1, i32 *%ptr
   store volatile i32 %add3, i32 *%ptr
   store volatile i32 %add4, i32 *%ptr
-  %final = getelementptr i32 *%ptr, i32 1
+  %final = getelementptr i32, i32 *%ptr, i32 1
   store volatile i32 %add5, i32 *%final
   ret void
 }
diff --git a/test/CodeGen/SystemZ/frame-06.ll b/test/CodeGen/SystemZ/frame-06.ll
index ad22f10903ad..c2aa8af336a0 100644
--- a/test/CodeGen/SystemZ/frame-06.ll
+++ b/test/CodeGen/SystemZ/frame-06.ll
@@ -29,20 +29,20 @@ define void @f1(i64 *%ptr) {
 ; CHECK: stg {{.*}}, 8(%r2)
 ; CHECK: lmg %r6, %r15, 48(%r15)
 ; CHECK: br %r14
-  %l0 = load volatile i64 *%ptr
-  %l1 = load volatile i64 *%ptr
-  %l3 = load volatile i64 *%ptr
-  %l4 = load volatile i64 *%ptr
-  %l5 = load volatile i64 *%ptr
-  %l6 = load volatile i64 *%ptr
-  %l7 = load volatile i64 *%ptr
-  %l8 = load volatile i64 *%ptr
-  %l9 = load volatile i64 *%ptr
-  %l10 = load volatile i64 *%ptr
-  %l11 = load volatile i64 *%ptr
-  %l12 = load volatile i64 *%ptr
-  %l13 = load volatile i64 *%ptr
-  %l14 = load volatile i64 *%ptr
+  %l0 = load volatile i64 , i64 *%ptr
+  %l1 = load volatile i64 , i64 *%ptr
+  %l3 = load volatile i64 , i64 *%ptr
+  %l4 = load volatile i64 , i64 *%ptr
+  %l5 = load volatile i64 , i64 *%ptr
+  %l6 = load volatile i64 , i64 *%ptr
+  %l7 = load volatile i64 , i64 *%ptr
+  %l8 = load volatile i64 , i64 *%ptr
+  %l9 = load volatile i64 , i64 *%ptr
+  %l10 = load volatile i64 , i64 *%ptr
+  %l11 = load volatile i64 , i64 *%ptr
+  %l12 = load volatile i64 , i64 *%ptr
+  %l13 = load volatile i64 , i64 *%ptr
+  %l14 = load volatile i64 , i64 *%ptr
   %add0 = add i64 %l0, %l0
   %add1 = add i64 %l1, %add0
   %add3 = add i64 %l3, %add1
@@ -70,7 +70,7 @@ define void @f1(i64 *%ptr) {
   store volatile i64 %add11, i64 *%ptr
   store volatile i64 %add12, i64 *%ptr
   store volatile i64 %add13, i64 *%ptr
-  %final = getelementptr i64 *%ptr, i64 1
+  %final = getelementptr i64, i64 *%ptr, i64 1
   store volatile i64 %add14, i64 *%final
   ret void
 }
@@ -97,19 +97,19 @@ define void @f2(i64 *%ptr) {
 ; CHECK: stg {{.*}}, 8(%r2)
 ; CHECK: lmg %r7, %r15, 56(%r15)
 ; CHECK: br %r14
-  %l0 = load volatile i64 *%ptr
-  %l1 = load volatile i64 *%ptr
-  %l3 = load volatile i64 *%ptr
-  %l4 = load volatile i64 *%ptr
-  %l5 = load volatile i64 *%ptr
-  %l7 = load volatile i64 *%ptr
-  %l8 = load volatile i64 *%ptr
-  %l9 = load volatile i64 *%ptr
-  %l10 = load volatile i64 *%ptr
-  %l11 = load volatile i64 *%ptr
-  %l12 = load volatile i64 *%ptr
-  %l13 = load volatile i64 *%ptr
-  %l14 = load volatile i64 *%ptr
+  %l0 = load volatile i64 , i64 *%ptr
+  %l1 = load volatile i64 , i64 *%ptr
+  %l3 = load volatile i64 , i64 *%ptr
+  %l4 = load volatile i64 , i64 *%ptr
+  %l5 = load volatile i64 , i64 *%ptr
+  %l7 = load volatile i64 , i64 *%ptr
+  %l8 = load volatile i64 , i64 *%ptr
+  %l9 = load volatile i64 , i64 *%ptr
+  %l10 = load volatile i64 , i64 *%ptr
+  %l11 = load volatile i64 , i64 *%ptr
+  %l12 = load volatile i64 , i64 *%ptr
+  %l13 = load volatile i64 , i64 *%ptr
+  %l14 = load volatile i64 , i64 *%ptr
   %add0 = add i64 %l0, %l0
   %add1 = add i64 %l1, %add0
   %add3 = add i64 %l3, %add1
@@ -135,7 +135,7 @@ define void @f2(i64 *%ptr) {
   store volatile i64 %add11, i64 *%ptr
   store volatile i64 %add12, i64 *%ptr
   store volatile i64 %add13, i64 *%ptr
-  %final = getelementptr i64 *%ptr, i64 1
+  %final = getelementptr i64, i64 *%ptr, i64 1
   store volatile i64 %add14, i64 *%final
   ret void
 }
@@ -160,12 +160,12 @@ define void @f3(i64 *%ptr) {
 ; CHECK: stg {{.*}}, 8(%r2)
 ; CHECK: lmg %r14, %r15, 112(%r15)
 ; CHECK: br %r14
-  %l0 = load volatile i64 *%ptr
-  %l1 = load volatile i64 *%ptr
-  %l3 = load volatile i64 *%ptr
-  %l4 = load volatile i64 *%ptr
-  %l5 = load volatile i64 *%ptr
-  %l14 = load volatile i64 *%ptr
+  %l0 = load volatile i64 , i64 *%ptr
+  %l1 = load volatile i64 , i64 *%ptr
+  %l3 = load volatile i64 , i64 *%ptr
+  %l4 = load volatile i64 , i64 *%ptr
+  %l5 = load volatile i64 , i64 *%ptr
+  %l14 = load volatile i64 , i64 *%ptr
   %add0 = add i64 %l0, %l0
   %add1 = add i64 %l1, %add0
   %add3 = add i64 %l3, %add1
@@ -177,7 +177,7 @@ define void @f3(i64 *%ptr) {
   store volatile i64 %add3, i64 *%ptr
   store volatile i64 %add4, i64 *%ptr
   store volatile i64 %add5, i64 *%ptr
-  %final = getelementptr i64 *%ptr, i64 1
+  %final = getelementptr i64, i64 *%ptr, i64 1
   store volatile i64 %add14, i64 *%final
   ret void
 }
@@ -196,11 +196,11 @@ define void @f4(i64 *%ptr) {
 ; CHECK-NOT: %r12
 ; CHECK-NOT: %r13
 ; CHECK: br %r14
-  %l0 = load volatile i64 *%ptr
-  %l1 = load volatile i64 *%ptr
-  %l3 = load volatile i64 *%ptr
-  %l4 = load volatile i64 *%ptr
-  %l5 = load volatile i64 *%ptr
+  %l0 = load volatile i64 , i64 *%ptr
+  %l1 = load volatile i64 , i64 *%ptr
+  %l3 = load volatile i64 , i64 *%ptr
+  %l4 = load volatile i64 , i64 *%ptr
+  %l5 = load volatile i64 , i64 *%ptr
   %add0 = add i64 %l0, %l0
   %add1 = add i64 %l1, %add0
   %add3 = add i64 %l3, %add1
@@ -210,7 +210,7 @@ define void @f4(i64 *%ptr) {
   store volatile i64 %add1, i64 *%ptr
   store volatile i64 %add3, i64 *%ptr
   store volatile i64 %add4, i64 *%ptr
-  %final = getelementptr i64 *%ptr, i64 1
+  %final = getelementptr i64, i64 *%ptr, i64 1
   store volatile i64 %add5, i64 *%final
   ret void
 }
diff --git a/test/CodeGen/SystemZ/frame-07.ll b/test/CodeGen/SystemZ/frame-07.ll
index eab313744b94..dd8101429628 100644
--- a/test/CodeGen/SystemZ/frame-07.ll
+++ b/test/CodeGen/SystemZ/frame-07.ll
@@ -1,7 +1,7 @@
 ; Test the saving and restoring of FPRs in large frames.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s
-; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck -check-prefix=CHECK-NOFP %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s
 
 ; Test a frame size that requires some FPRs to be saved and loaded using
 ; the 20-bit STDY and LDY while others can use the 12-bit STD and LD.
@@ -66,24 +66,24 @@ define void @f1(double *%ptr, i64 %x) {
 ; CHECK-FP: lmg %r11, %r15, 4216(%r11)
 ; CHECK-FP: br %r14
   %y = alloca [486 x i64], align 8
-  %elem = getelementptr inbounds [486 x i64]* %y, i64 0, i64 0
+  %elem = getelementptr inbounds [486 x i64], [486 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %elem
-  %l0 = load volatile double *%ptr
-  %l1 = load volatile double *%ptr
-  %l2 = load volatile double *%ptr
-  %l3 = load volatile double *%ptr
-  %l4 = load volatile double *%ptr
-  %l5 = load volatile double *%ptr
-  %l6 = load volatile double *%ptr
-  %l7 = load volatile double *%ptr
-  %l8 = load volatile double *%ptr
-  %l9 = load volatile double *%ptr
-  %l10 = load volatile double *%ptr
-  %l11 = load volatile double *%ptr
-  %l12 = load volatile double *%ptr
-  %l13 = load volatile double *%ptr
-  %l14 = load volatile double *%ptr
-  %l15 = load volatile double *%ptr
+  %l0 = load volatile double , double *%ptr
+  %l1 = load volatile double , double *%ptr
+  %l2 = load volatile double , double *%ptr
+  %l3 = load volatile double , double *%ptr
+  %l4 = load volatile double , double *%ptr
+  %l5 = load volatile double , double *%ptr
+  %l6 = load volatile double , double *%ptr
+  %l7 = load volatile double , double *%ptr
+  %l8 = load volatile double , double *%ptr
+  %l9 = load volatile double , double *%ptr
+  %l10 = load volatile double , double *%ptr
+  %l11 = load volatile double , double *%ptr
+  %l12 = load volatile double , double *%ptr
+  %l13 = load volatile double , double *%ptr
+  %l14 = load volatile double , double *%ptr
+  %l15 = load volatile double , double *%ptr
   %add0 = fadd double %l0, %l0
   %add1 = fadd double %l1, %add0
   %add2 = fadd double %l2, %add1
@@ -195,24 +195,24 @@ define void @f2(double *%ptr, i64 %x) {
 ; CHECK-FP: lmg %r11, %r15, 524280(%r11)
 ; CHECK-FP: br %r14
   %y = alloca [65510 x i64], align 8
-  %elem = getelementptr inbounds [65510 x i64]* %y, i64 0, i64 0
+  %elem = getelementptr inbounds [65510 x i64], [65510 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %elem
-  %l0 = load volatile double *%ptr
-  %l1 = load volatile double *%ptr
-  %l2 = load volatile double *%ptr
-  %l3 = load volatile double *%ptr
-  %l4 = load volatile double *%ptr
-  %l5 = load volatile double *%ptr
-  %l6 = load volatile double *%ptr
-  %l7 = load volatile double *%ptr
-  %l8 = load volatile double *%ptr
-  %l9 = load volatile double *%ptr
-  %l10 = load volatile double *%ptr
-  %l11 = load volatile double *%ptr
-  %l12 = load volatile double *%ptr
-  %l13 = load volatile double *%ptr
-  %l14 = load volatile double *%ptr
-  %l15 = load volatile double *%ptr
+  %l0 = load volatile double , double *%ptr
+  %l1 = load volatile double , double *%ptr
+  %l2 = load volatile double , double *%ptr
+  %l3 = load volatile double , double *%ptr
+  %l4 = load volatile double , double *%ptr
+  %l5 = load volatile double , double *%ptr
+  %l6 = load volatile double , double *%ptr
+  %l7 = load volatile double , double *%ptr
+  %l8 = load volatile double , double *%ptr
+  %l9 = load volatile double , double *%ptr
+  %l10 = load volatile double , double *%ptr
+  %l11 = load volatile double , double *%ptr
+  %l12 = load volatile double , double *%ptr
+  %l13 = load volatile double , double *%ptr
+  %l14 = load volatile double , double *%ptr
+  %l15 = load volatile double , double *%ptr
   %add0 = fadd double %l0, %l0
   %add1 = fadd double %l1, %add0
   %add2 = fadd double %l2, %add1
diff --git a/test/CodeGen/SystemZ/frame-08.ll b/test/CodeGen/SystemZ/frame-08.ll
index aa4e3f481da4..99e64108bca1 100644
--- a/test/CodeGen/SystemZ/frame-08.ll
+++ b/test/CodeGen/SystemZ/frame-08.ll
@@ -25,19 +25,19 @@ define void @f1(i32 *%ptr, i64 %x) {
 ; CHECK-NOT: ag
 ; CHECK: lmg %r6, %r15, 524280(%r15)
 ; CHECK: br %r14
-  %l0 = load volatile i32 *%ptr
-  %l1 = load volatile i32 *%ptr
-  %l4 = load volatile i32 *%ptr
-  %l5 = load volatile i32 *%ptr
-  %l6 = load volatile i32 *%ptr
-  %l7 = load volatile i32 *%ptr
-  %l8 = load volatile i32 *%ptr
-  %l9 = load volatile i32 *%ptr
-  %l10 = load volatile i32 *%ptr
-  %l11 = load volatile i32 *%ptr
-  %l12 = load volatile i32 *%ptr
-  %l13 = load volatile i32 *%ptr
-  %l14 = load volatile i32 *%ptr
+  %l0 = load volatile i32 , i32 *%ptr
+  %l1 = load volatile i32 , i32 *%ptr
+  %l4 = load volatile i32 , i32 *%ptr
+  %l5 = load volatile i32 , i32 *%ptr
+  %l6 = load volatile i32 , i32 *%ptr
+  %l7 = load volatile i32 , i32 *%ptr
+  %l8 = load volatile i32 , i32 *%ptr
+  %l9 = load volatile i32 , i32 *%ptr
+  %l10 = load volatile i32 , i32 *%ptr
+  %l11 = load volatile i32 , i32 *%ptr
+  %l12 = load volatile i32 , i32 *%ptr
+  %l13 = load volatile i32 , i32 *%ptr
+  %l14 = load volatile i32 , i32 *%ptr
   %add0 = add i32 %l0, %l0
   %add1 = add i32 %l1, %add0
   %add4 = add i32 %l4, %add1
@@ -65,7 +65,7 @@ define void @f1(i32 *%ptr, i64 %x) {
   store volatile i32 %add13, i32 *%ptr
   store volatile i32 %add14, i32 *%ptr
   %y = alloca [65507 x i64], align 8
-  %entry = getelementptr inbounds [65507 x i64]* %y, i64 0, i64 0
+  %entry = getelementptr inbounds [65507 x i64], [65507 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %entry
   ret void
 }
@@ -85,11 +85,11 @@ define void @f2(i32 *%ptr, i64 %x) {
 ; CHECK-NOT: ag
 ; CHECK: lmg %r14, %r15, 524280(%r15)
 ; CHECK: br %r14
-  %l0 = load volatile i32 *%ptr
-  %l1 = load volatile i32 *%ptr
-  %l4 = load volatile i32 *%ptr
-  %l5 = load volatile i32 *%ptr
-  %l14 = load volatile i32 *%ptr
+  %l0 = load volatile i32 , i32 *%ptr
+  %l1 = load volatile i32 , i32 *%ptr
+  %l4 = load volatile i32 , i32 *%ptr
+  %l5 = load volatile i32 , i32 *%ptr
+  %l14 = load volatile i32 , i32 *%ptr
   %add0 = add i32 %l0, %l0
   %add1 = add i32 %l1, %add0
   %add4 = add i32 %l4, %add1
@@ -101,7 +101,7 @@ define void @f2(i32 *%ptr, i64 %x) {
   store volatile i32 %add5, i32 *%ptr
   store volatile i32 %add14, i32 *%ptr
   %y = alloca [65499 x i64], align 8
-  %entry = getelementptr inbounds [65499 x i64]* %y, i64 0, i64 0
+  %entry = getelementptr inbounds [65499 x i64], [65499 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %entry
   ret void
 }
@@ -128,19 +128,19 @@ define void @f3(i32 *%ptr, i64 %x) {
 ; CHECK: aghi %r15, 8
 ; CHECK: lmg %r6, %r15, 524280(%r15)
 ; CHECK: br %r14
-  %l0 = load volatile i32 *%ptr
-  %l1 = load volatile i32 *%ptr
-  %l4 = load volatile i32 *%ptr
-  %l5 = load volatile i32 *%ptr
-  %l6 = load volatile i32 *%ptr
-  %l7 = load volatile i32 *%ptr
-  %l8 = load volatile i32 *%ptr
-  %l9 = load volatile i32 *%ptr
-  %l10 = load volatile i32 *%ptr
-  %l11 = load volatile i32 *%ptr
-  %l12 = load volatile i32 *%ptr
-  %l13 = load volatile i32 *%ptr
-  %l14 = load volatile i32 *%ptr
+  %l0 = load volatile i32 , i32 *%ptr
+  %l1 = load volatile i32 , i32 *%ptr
+  %l4 = load volatile i32 , i32 *%ptr
+  %l5 = load volatile i32 , i32 *%ptr
+  %l6 = load volatile i32 , i32 *%ptr
+  %l7 = load volatile i32 , i32 *%ptr
+  %l8 = load volatile i32 , i32 *%ptr
+  %l9 = load volatile i32 , i32 *%ptr
+  %l10 = load volatile i32 , i32 *%ptr
+  %l11 = load volatile i32 , i32 *%ptr
+  %l12 = load volatile i32 , i32 *%ptr
+  %l13 = load volatile i32 , i32 *%ptr
+  %l14 = load volatile i32 , i32 *%ptr
   %add0 = add i32 %l0, %l0
   %add1 = add i32 %l1, %add0
   %add4 = add i32 %l4, %add1
@@ -168,7 +168,7 @@ define void @f3(i32 *%ptr, i64 %x) {
   store volatile i32 %add13, i32 *%ptr
   store volatile i32 %add14, i32 *%ptr
   %y = alloca [65508 x i64], align 8
-  %entry = getelementptr inbounds [65508 x i64]* %y, i64 0, i64 0
+  %entry = getelementptr inbounds [65508 x i64], [65508 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %entry
   ret void
 }
@@ -187,11 +187,11 @@ define void @f4(i32 *%ptr, i64 %x) {
 ; CHECK: aghi %r15, 8
 ; CHECK: lmg %r14, %r15, 524280(%r15)
 ; CHECK: br %r14
-  %l0 = load volatile i32 *%ptr
-  %l1 = load volatile i32 *%ptr
-  %l4 = load volatile i32 *%ptr
-  %l5 = load volatile i32 *%ptr
-  %l14 = load volatile i32 *%ptr
+  %l0 = load volatile i32 , i32 *%ptr
+  %l1 = load volatile i32 , i32 *%ptr
+  %l4 = load volatile i32 , i32 *%ptr
+  %l5 = load volatile i32 , i32 *%ptr
+  %l14 = load volatile i32 , i32 *%ptr
   %add0 = add i32 %l0, %l0
   %add1 = add i32 %l1, %add0
   %add4 = add i32 %l4, %add1
@@ -203,7 +203,7 @@ define void @f4(i32 *%ptr, i64 %x) {
   store volatile i32 %add5, i32 *%ptr
   store volatile i32 %add14, i32 *%ptr
   %y = alloca [65500 x i64], align 8
-  %entry = getelementptr inbounds [65500 x i64]* %y, i64 0, i64 0
+  %entry = getelementptr inbounds [65500 x i64], [65500 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %entry
   ret void
 }
@@ -221,11 +221,11 @@ define void @f5(i32 *%ptr, i64 %x) {
 ; CHECK: aghi %r15, 32760
 ; CHECK: lmg %r14, %r15, 524280(%r15)
 ; CHECK: br %r14
-  %l0 = load volatile i32 *%ptr
-  %l1 = load volatile i32 *%ptr
-  %l4 = load volatile i32 *%ptr
-  %l5 = load volatile i32 *%ptr
-  %l14 = load volatile i32 *%ptr
+  %l0 = load volatile i32 , i32 *%ptr
+  %l1 = load volatile i32 , i32 *%ptr
+  %l4 = load volatile i32 , i32 *%ptr
+  %l5 = load volatile i32 , i32 *%ptr
+  %l14 = load volatile i32 , i32 *%ptr
   %add0 = add i32 %l0, %l0
   %add1 = add i32 %l1, %add0
   %add4 = add i32 %l4, %add1
@@ -237,7 +237,7 @@ define void @f5(i32 *%ptr, i64 %x) {
   store volatile i32 %add5, i32 *%ptr
   store volatile i32 %add14, i32 *%ptr
   %y = alloca [69594 x i64], align 8
-  %entry = getelementptr inbounds [69594 x i64]* %y, i64 0, i64 0
+  %entry = getelementptr inbounds [69594 x i64], [69594 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %entry
   ret void
 }
@@ -255,11 +255,11 @@ define void @f6(i32 *%ptr, i64 %x) {
 ; CHECK: agfi %r15, 32768
 ; CHECK: lmg %r14, %r15, 524280(%r15)
 ; CHECK: br %r14
-  %l0 = load volatile i32 *%ptr
-  %l1 = load volatile i32 *%ptr
-  %l4 = load volatile i32 *%ptr
-  %l5 = load volatile i32 *%ptr
-  %l14 = load volatile i32 *%ptr
+  %l0 = load volatile i32 , i32 *%ptr
+  %l1 = load volatile i32 , i32 *%ptr
+  %l4 = load volatile i32 , i32 *%ptr
+  %l5 = load volatile i32 , i32 *%ptr
+  %l14 = load volatile i32 , i32 *%ptr
   %add0 = add i32 %l0, %l0
   %add1 = add i32 %l1, %add0
   %add4 = add i32 %l4, %add1
@@ -271,7 +271,7 @@ define void @f6(i32 *%ptr, i64 %x) {
   store volatile i32 %add5, i32 *%ptr
   store volatile i32 %add14, i32 *%ptr
   %y = alloca [69595 x i64], align 8
-  %entry = getelementptr inbounds [69595 x i64]* %y, i64 0, i64 0
+  %entry = getelementptr inbounds [69595 x i64], [69595 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %entry
   ret void
 }
diff --git a/test/CodeGen/SystemZ/frame-09.ll b/test/CodeGen/SystemZ/frame-09.ll
index 8a4f99c343a0..ead944e59f98 100644
--- a/test/CodeGen/SystemZ/frame-09.ll
+++ b/test/CodeGen/SystemZ/frame-09.ll
@@ -64,19 +64,19 @@ define void @f3(i32 *%ptr) {
 ; CHECK: st {{.*}}, 4(%r2)
 ; CHECK: lmg %r6, %r15, 48(%r11)
 ; CHECK: br %r14
-  %l0 = load volatile i32 *%ptr
-  %l1 = load volatile i32 *%ptr
-  %l3 = load volatile i32 *%ptr
-  %l4 = load volatile i32 *%ptr
-  %l5 = load volatile i32 *%ptr
-  %l6 = load volatile i32 *%ptr
-  %l7 = load volatile i32 *%ptr
-  %l8 = load volatile i32 *%ptr
-  %l9 = load volatile i32 *%ptr
-  %l10 = load volatile i32 *%ptr
-  %l12 = load volatile i32 *%ptr
-  %l13 = load volatile i32 *%ptr
-  %l14 = load volatile i32 *%ptr
+  %l0 = load volatile i32 , i32 *%ptr
+  %l1 = load volatile i32 , i32 *%ptr
+  %l3 = load volatile i32 , i32 *%ptr
+  %l4 = load volatile i32 , i32 *%ptr
+  %l5 = load volatile i32 , i32 *%ptr
+  %l6 = load volatile i32 , i32 *%ptr
+  %l7 = load volatile i32 , i32 *%ptr
+  %l8 = load volatile i32 , i32 *%ptr
+  %l9 = load volatile i32 , i32 *%ptr
+  %l10 = load volatile i32 , i32 *%ptr
+  %l12 = load volatile i32 , i32 *%ptr
+  %l13 = load volatile i32 , i32 *%ptr
+  %l14 = load volatile i32 , i32 *%ptr
   %add0 = add i32 %l0, %l0
   %add1 = add i32 %l1, %add0
   %add3 = add i32 %l3, %add1
@@ -102,7 +102,7 @@ define void @f3(i32 *%ptr) {
   store volatile i32 %add10, i32 *%ptr
   store volatile i32 %add12, i32 *%ptr
   store volatile i32 %add13, i32 *%ptr
-  %final = getelementptr i32 *%ptr, i32 1
+  %final = getelementptr i32, i32 *%ptr, i32 1
   store volatile i32 %add14, i32 *%final
   ret void
 }
@@ -124,7 +124,7 @@ define void @f4(i64 %x) {
 ; CHECK: lmg %r11, %r15, 524280(%r11)
 ; CHECK: br %r14
   %y = alloca [65502 x i64], align 8
-  %ptr = getelementptr inbounds [65502 x i64]* %y, i64 0, i64 0
+  %ptr = getelementptr inbounds [65502 x i64], [65502 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
@@ -144,7 +144,7 @@ define void @f5(i64 %x) {
 ; CHECK: lmg %r11, %r15, 524280(%r11)
 ; CHECK: br %r14
   %y = alloca [65503 x i64], align 8
-  %ptr = getelementptr inbounds [65503 x i64]* %y, i64 0, i64 0
+  %ptr = getelementptr inbounds [65503 x i64], [65503 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
diff --git a/test/CodeGen/SystemZ/frame-13.ll b/test/CodeGen/SystemZ/frame-13.ll
index 58dee1da58b5..2afe6d74388b 100644
--- a/test/CodeGen/SystemZ/frame-13.ll
+++ b/test/CodeGen/SystemZ/frame-13.ll
@@ -34,8 +34,8 @@ define void @f1() {
 ; CHECK-FP: br %r14
   %region1 = alloca [978 x i32], align 8
   %region2 = alloca [978 x i32], align 8
-  %ptr1 = getelementptr inbounds [978 x i32]* %region1, i64 0, i64 1
-  %ptr2 = getelementptr inbounds [978 x i32]* %region2, i64 0, i64 1
+  %ptr1 = getelementptr inbounds [978 x i32], [978 x i32]* %region1, i64 0, i64 1
+  %ptr2 = getelementptr inbounds [978 x i32], [978 x i32]* %region2, i64 0, i64 1
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -54,8 +54,8 @@ define void @f2() {
 ; CHECK-FP: br %r14
   %region1 = alloca [978 x i32], align 8
   %region2 = alloca [978 x i32], align 8
-  %ptr1 = getelementptr inbounds [978 x i32]* %region1, i64 0, i64 2
-  %ptr2 = getelementptr inbounds [978 x i32]* %region2, i64 0, i64 2
+  %ptr1 = getelementptr inbounds [978 x i32], [978 x i32]* %region1, i64 0, i64 2
+  %ptr2 = getelementptr inbounds [978 x i32], [978 x i32]* %region2, i64 0, i64 2
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -74,8 +74,8 @@ define void @f3() {
 ; CHECK-FP: br %r14
   %region1 = alloca [978 x i32], align 8
   %region2 = alloca [978 x i32], align 8
-  %ptr1 = getelementptr inbounds [978 x i32]* %region1, i64 0, i64 3
-  %ptr2 = getelementptr inbounds [978 x i32]* %region2, i64 0, i64 3
+  %ptr1 = getelementptr inbounds [978 x i32], [978 x i32]* %region1, i64 0, i64 3
+  %ptr2 = getelementptr inbounds [978 x i32], [978 x i32]* %region2, i64 0, i64 3
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -94,8 +94,8 @@ define void @f4() {
 ; CHECK-FP: br %r14
   %region1 = alloca [2002 x i32], align 8
   %region2 = alloca [2002 x i32], align 8
-  %ptr1 = getelementptr inbounds [2002 x i32]* %region1, i64 0, i64 1
-  %ptr2 = getelementptr inbounds [2002 x i32]* %region2, i64 0, i64 1
+  %ptr1 = getelementptr inbounds [2002 x i32], [2002 x i32]* %region1, i64 0, i64 1
+  %ptr2 = getelementptr inbounds [2002 x i32], [2002 x i32]* %region2, i64 0, i64 1
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -114,8 +114,8 @@ define void @f5() {
 ; CHECK-FP: br %r14
   %region1 = alloca [2002 x i32], align 8
   %region2 = alloca [2002 x i32], align 8
-  %ptr1 = getelementptr inbounds [2002 x i32]* %region1, i64 0, i64 2
-  %ptr2 = getelementptr inbounds [2002 x i32]* %region2, i64 0, i64 2
+  %ptr1 = getelementptr inbounds [2002 x i32], [2002 x i32]* %region1, i64 0, i64 2
+  %ptr2 = getelementptr inbounds [2002 x i32], [2002 x i32]* %region2, i64 0, i64 2
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -134,8 +134,8 @@ define void @f6() {
 ; CHECK-FP: br %r14
   %region1 = alloca [2002 x i32], align 8
   %region2 = alloca [2002 x i32], align 8
-  %ptr1 = getelementptr inbounds [2002 x i32]* %region1, i64 0, i64 3
-  %ptr2 = getelementptr inbounds [2002 x i32]* %region2, i64 0, i64 3
+  %ptr1 = getelementptr inbounds [2002 x i32], [2002 x i32]* %region1, i64 0, i64 3
+  %ptr2 = getelementptr inbounds [2002 x i32], [2002 x i32]* %region2, i64 0, i64 3
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -156,8 +156,8 @@ define void @f7() {
 ; CHECK-FP: br %r14
   %region1 = alloca [2004 x i32], align 8
   %region2 = alloca [2004 x i32], align 8
-  %ptr1 = getelementptr inbounds [2004 x i32]* %region1, i64 0, i64 1023
-  %ptr2 = getelementptr inbounds [2004 x i32]* %region2, i64 0, i64 1023
+  %ptr1 = getelementptr inbounds [2004 x i32], [2004 x i32]* %region1, i64 0, i64 1023
+  %ptr2 = getelementptr inbounds [2004 x i32], [2004 x i32]* %region2, i64 0, i64 1023
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -177,8 +177,8 @@ define void @f8() {
 ; CHECK-FP: br %r14
   %region1 = alloca [2006 x i32], align 8
   %region2 = alloca [2006 x i32], align 8
-  %ptr1 = getelementptr inbounds [2006 x i32]* %region1, i64 0, i64 1023
-  %ptr2 = getelementptr inbounds [2006 x i32]* %region2, i64 0, i64 1023
+  %ptr1 = getelementptr inbounds [2006 x i32], [2006 x i32]* %region1, i64 0, i64 1023
+  %ptr2 = getelementptr inbounds [2006 x i32], [2006 x i32]* %region2, i64 0, i64 1023
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -198,8 +198,8 @@ define void @f9() {
 ; CHECK-FP: br %r14
   %region1 = alloca [2006 x i32], align 8
   %region2 = alloca [2006 x i32], align 8
-  %ptr1 = getelementptr inbounds [2006 x i32]* %region1, i64 0, i64 1024
-  %ptr2 = getelementptr inbounds [2006 x i32]* %region2, i64 0, i64 1024
+  %ptr1 = getelementptr inbounds [2006 x i32], [2006 x i32]* %region1, i64 0, i64 1024
+  %ptr2 = getelementptr inbounds [2006 x i32], [2006 x i32]* %region2, i64 0, i64 1024
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -222,15 +222,15 @@ define void @f10(i32 *%vptr) {
 ; CHECK-FP: mvhi 0([[REGISTER]]), 42
 ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
 ; CHECK-FP: br %r14
-  %i0 = load volatile i32 *%vptr
-  %i1 = load volatile i32 *%vptr
-  %i3 = load volatile i32 *%vptr
-  %i4 = load volatile i32 *%vptr
-  %i5 = load volatile i32 *%vptr
+  %i0 = load volatile i32 , i32 *%vptr
+  %i1 = load volatile i32 , i32 *%vptr
+  %i3 = load volatile i32 , i32 *%vptr
+  %i4 = load volatile i32 , i32 *%vptr
+  %i5 = load volatile i32 , i32 *%vptr
   %region1 = alloca [978 x i32], align 8
   %region2 = alloca [978 x i32], align 8
-  %ptr1 = getelementptr inbounds [978 x i32]* %region1, i64 0, i64 2
-  %ptr2 = getelementptr inbounds [978 x i32]* %region2, i64 0, i64 2
+  %ptr1 = getelementptr inbounds [978 x i32], [978 x i32]* %region1, i64 0, i64 2
+  %ptr2 = getelementptr inbounds [978 x i32], [978 x i32]* %region2, i64 0, i64 2
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   store volatile i32 %i0, i32 *%vptr
@@ -254,24 +254,24 @@ define void @f11(i32 *%vptr) {
 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: lmg %r6, %r15,
 ; CHECK-NOFP: br %r14
-  %i0 = load volatile i32 *%vptr
-  %i1 = load volatile i32 *%vptr
-  %i3 = load volatile i32 *%vptr
-  %i4 = load volatile i32 *%vptr
-  %i5 = load volatile i32 *%vptr
-  %i6 = load volatile i32 *%vptr
-  %i7 = load volatile i32 *%vptr
-  %i8 = load volatile i32 *%vptr
-  %i9 = load volatile i32 *%vptr
-  %i10 = load volatile i32 *%vptr
-  %i11 = load volatile i32 *%vptr
-  %i12 = load volatile i32 *%vptr
-  %i13 = load volatile i32 *%vptr
-  %i14 = load volatile i32 *%vptr
+  %i0 = load volatile i32 , i32 *%vptr
+  %i1 = load volatile i32 , i32 *%vptr
+  %i3 = load volatile i32 , i32 *%vptr
+  %i4 = load volatile i32 , i32 *%vptr
+  %i5 = load volatile i32 , i32 *%vptr
+  %i6 = load volatile i32 , i32 *%vptr
+  %i7 = load volatile i32 , i32 *%vptr
+  %i8 = load volatile i32 , i32 *%vptr
+  %i9 = load volatile i32 , i32 *%vptr
+  %i10 = load volatile i32 , i32 *%vptr
+  %i11 = load volatile i32 , i32 *%vptr
+  %i12 = load volatile i32 , i32 *%vptr
+  %i13 = load volatile i32 , i32 *%vptr
+  %i14 = load volatile i32 , i32 *%vptr
   %region1 = alloca [978 x i32], align 8
   %region2 = alloca [978 x i32], align 8
-  %ptr1 = getelementptr inbounds [978 x i32]* %region1, i64 0, i64 2
-  %ptr2 = getelementptr inbounds [978 x i32]* %region2, i64 0, i64 2
+  %ptr1 = getelementptr inbounds [978 x i32], [978 x i32]* %region1, i64 0, i64 2
+  %ptr2 = getelementptr inbounds [978 x i32], [978 x i32]* %region2, i64 0, i64 2
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   store volatile i32 %i0, i32 *%vptr
diff --git a/test/CodeGen/SystemZ/frame-14.ll b/test/CodeGen/SystemZ/frame-14.ll
index 24169cf61f00..3c080a401648 100644
--- a/test/CodeGen/SystemZ/frame-14.ll
+++ b/test/CodeGen/SystemZ/frame-14.ll
@@ -33,8 +33,8 @@ define void @f1() {
 ; CHECK-FP: br %r14
   %region1 = alloca [3912 x i8], align 8
   %region2 = alloca [3912 x i8], align 8
-  %ptr1 = getelementptr inbounds [3912 x i8]* %region1, i64 0, i64 7
-  %ptr2 = getelementptr inbounds [3912 x i8]* %region2, i64 0, i64 7
+  %ptr1 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region1, i64 0, i64 7
+  %ptr2 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region2, i64 0, i64 7
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -51,8 +51,8 @@ define void @f2() {
 ; CHECK-FP: br %r14
   %region1 = alloca [3912 x i8], align 8
   %region2 = alloca [3912 x i8], align 8
-  %ptr1 = getelementptr inbounds [3912 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [3912 x i8]* %region2, i64 0, i64 8
+  %ptr1 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region2, i64 0, i64 8
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -72,8 +72,8 @@ define void @f3() {
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
-  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 7
-  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 7
+  %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 7
+  %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 7
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -96,8 +96,8 @@ define void @f4() {
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
-  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8
+  %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -119,8 +119,8 @@ define void @f5() {
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
-  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 4103
-  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 4103
+  %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 4103
+  %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 4103
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -141,8 +141,8 @@ define void @f6() {
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
-  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 4104
-  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 4104
+  %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 4104
+  %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 4104
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -166,8 +166,8 @@ define void @f7() {
 ; CHECK-FP: br %r14
   %region1 = alloca [1048400 x i8], align 8
   %region2 = alloca [1048400 x i8], align 8
-  %ptr1 = getelementptr inbounds [1048400 x i8]* %region1, i64 0, i64 524287
-  %ptr2 = getelementptr inbounds [1048400 x i8]* %region2, i64 0, i64 524287
+  %ptr1 = getelementptr inbounds [1048400 x i8], [1048400 x i8]* %region1, i64 0, i64 524287
+  %ptr2 = getelementptr inbounds [1048400 x i8], [1048400 x i8]* %region2, i64 0, i64 524287
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -189,8 +189,8 @@ define void @f8() {
 ; CHECK-FP: br %r14
   %region1 = alloca [1048408 x i8], align 8
   %region2 = alloca [1048408 x i8], align 8
-  %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524287
-  %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524287
+  %ptr1 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region1, i64 0, i64 524287
+  %ptr2 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region2, i64 0, i64 524287
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -219,8 +219,8 @@ define void @f9() {
 ; CHECK-FP: br %r14
   %region1 = alloca [1048408 x i8], align 8
   %region2 = alloca [1048408 x i8], align 8
-  %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524288
-  %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524288
+  %ptr1 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region1, i64 0, i64 524288
+  %ptr2 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region2, i64 0, i64 524288
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -245,15 +245,15 @@ define void @f10(i32 *%vptr) {
 ; CHECK-FP: mvi 0([[REGISTER]]), 42
 ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
 ; CHECK-FP: br %r14
-  %i0 = load volatile i32 *%vptr
-  %i1 = load volatile i32 *%vptr
-  %i3 = load volatile i32 *%vptr
-  %i4 = load volatile i32 *%vptr
-  %i5 = load volatile i32 *%vptr
+  %i0 = load volatile i32 , i32 *%vptr
+  %i1 = load volatile i32 , i32 *%vptr
+  %i3 = load volatile i32 , i32 *%vptr
+  %i4 = load volatile i32 , i32 *%vptr
+  %i5 = load volatile i32 , i32 *%vptr
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
-  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8
+  %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   store volatile i32 %i0, i32 *%vptr
@@ -278,24 +278,24 @@ define void @f11(i32 *%vptr) {
 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: lmg %r6, %r15,
 ; CHECK-NOFP: br %r14
-  %i0 = load volatile i32 *%vptr
-  %i1 = load volatile i32 *%vptr
-  %i3 = load volatile i32 *%vptr
-  %i4 = load volatile i32 *%vptr
-  %i5 = load volatile i32 *%vptr
-  %i6 = load volatile i32 *%vptr
-  %i7 = load volatile i32 *%vptr
-  %i8 = load volatile i32 *%vptr
-  %i9 = load volatile i32 *%vptr
-  %i10 = load volatile i32 *%vptr
-  %i11 = load volatile i32 *%vptr
-  %i12 = load volatile i32 *%vptr
-  %i13 = load volatile i32 *%vptr
-  %i14 = load volatile i32 *%vptr
+  %i0 = load volatile i32 , i32 *%vptr
+  %i1 = load volatile i32 , i32 *%vptr
+  %i3 = load volatile i32 , i32 *%vptr
+  %i4 = load volatile i32 , i32 *%vptr
+  %i5 = load volatile i32 , i32 *%vptr
+  %i6 = load volatile i32 , i32 *%vptr
+  %i7 = load volatile i32 , i32 *%vptr
+  %i8 = load volatile i32 , i32 *%vptr
+  %i9 = load volatile i32 , i32 *%vptr
+  %i10 = load volatile i32 , i32 *%vptr
+  %i11 = load volatile i32 , i32 *%vptr
+  %i12 = load volatile i32 , i32 *%vptr
+  %i13 = load volatile i32 , i32 *%vptr
+  %i14 = load volatile i32 , i32 *%vptr
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
-  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8
+  %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   store volatile i32 %i0, i32 *%vptr
diff --git a/test/CodeGen/SystemZ/frame-15.ll b/test/CodeGen/SystemZ/frame-15.ll
index b3c95e73c1af..f81c9dc5c2c4 100644
--- a/test/CodeGen/SystemZ/frame-15.ll
+++ b/test/CodeGen/SystemZ/frame-15.ll
@@ -36,13 +36,13 @@ define void @f1(double *%dst) {
 ; CHECK-FP: br %r14
   %region1 = alloca [978 x float], align 8
   %region2 = alloca [978 x float], align 8
-  %start1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 0
+  %start1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 1
-  %ptr2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 1
-  %float1 = load float *%ptr1
-  %float2 = load float *%ptr2
+  %ptr1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 1
+  %ptr2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 1
+  %float1 = load float , float *%ptr1
+  %float2 = load float , float *%ptr2
   %double1 = fpext float %float1 to double
   %double2 = fpext float %float2 to double
   store volatile double %double1, double *%dst
@@ -63,13 +63,13 @@ define void @f2(double *%dst) {
 ; CHECK-FP: br %r14
   %region1 = alloca [978 x float], align 8
   %region2 = alloca [978 x float], align 8
-  %start1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 0
+  %start1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 2
-  %ptr2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 2
-  %float1 = load float *%ptr1
-  %float2 = load float *%ptr2
+  %ptr1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 2
+  %ptr2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 2
+  %float1 = load float , float *%ptr1
+  %float2 = load float , float *%ptr2
   %double1 = fpext float %float1 to double
   %double2 = fpext float %float2 to double
   store volatile double %double1, double *%dst
@@ -90,13 +90,13 @@ define void @f3(double *%dst) {
 ; CHECK-FP: br %r14
   %region1 = alloca [978 x float], align 8
   %region2 = alloca [978 x float], align 8
-  %start1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 0
+  %start1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 3
-  %ptr2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 3
-  %float1 = load float *%ptr1
-  %float2 = load float *%ptr2
+  %ptr1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 3
+  %ptr2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 3
+  %float1 = load float , float *%ptr1
+  %float2 = load float , float *%ptr2
   %double1 = fpext float %float1 to double
   %double2 = fpext float %float2 to double
   store volatile double %double1, double *%dst
@@ -117,13 +117,13 @@ define void @f4(double *%dst) {
 ; CHECK-FP: br %r14
   %region1 = alloca [2002 x float], align 8
   %region2 = alloca [2002 x float], align 8
-  %start1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 0
+  %start1 = getelementptr inbounds [2002 x float], [2002 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [2002 x float], [2002 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 1
-  %ptr2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 1
-  %float1 = load float *%ptr1
-  %float2 = load float *%ptr2
+  %ptr1 = getelementptr inbounds [2002 x float], [2002 x float]* %region1, i64 0, i64 1
+  %ptr2 = getelementptr inbounds [2002 x float], [2002 x float]* %region2, i64 0, i64 1
+  %float1 = load float , float *%ptr1
+  %float2 = load float , float *%ptr2
   %double1 = fpext float %float1 to double
   %double2 = fpext float %float2 to double
   store volatile double %double1, double *%dst
@@ -144,13 +144,13 @@ define void @f5(double *%dst) {
 ; CHECK-FP: br %r14
   %region1 = alloca [2002 x float], align 8
   %region2 = alloca [2002 x float], align 8
-  %start1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 0
+  %start1 = getelementptr inbounds [2002 x float], [2002 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [2002 x float], [2002 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 2
-  %ptr2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 2
-  %float1 = load float *%ptr1
-  %float2 = load float *%ptr2
+  %ptr1 = getelementptr inbounds [2002 x float], [2002 x float]* %region1, i64 0, i64 2
+  %ptr2 = getelementptr inbounds [2002 x float], [2002 x float]* %region2, i64 0, i64 2
+  %float1 = load float , float *%ptr1
+  %float2 = load float , float *%ptr2
   %double1 = fpext float %float1 to double
   %double2 = fpext float %float2 to double
   store volatile double %double1, double *%dst
@@ -171,13 +171,13 @@ define void @f6(double *%dst) {
 ; CHECK-FP: br %r14
   %region1 = alloca [2002 x float], align 8
   %region2 = alloca [2002 x float], align 8
-  %start1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 0
+  %start1 = getelementptr inbounds [2002 x float], [2002 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [2002 x float], [2002 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 3
-  %ptr2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 3
-  %float1 = load float *%ptr1
-  %float2 = load float *%ptr2
+  %ptr1 = getelementptr inbounds [2002 x float], [2002 x float]* %region1, i64 0, i64 3
+  %ptr2 = getelementptr inbounds [2002 x float], [2002 x float]* %region2, i64 0, i64 3
+  %float1 = load float , float *%ptr1
+  %float2 = load float , float *%ptr2
   %double1 = fpext float %float1 to double
   %double2 = fpext float %float2 to double
   store volatile double %double1, double *%dst
@@ -200,13 +200,13 @@ define void @f7(double *%dst) {
 ; CHECK-FP: br %r14
   %region1 = alloca [2004 x float], align 8
   %region2 = alloca [2004 x float], align 8
-  %start1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 0
+  %start1 = getelementptr inbounds [2004 x float], [2004 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [2004 x float], [2004 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 1023
-  %ptr2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 1023
-  %float1 = load float *%ptr1
-  %float2 = load float *%ptr2
+  %ptr1 = getelementptr inbounds [2004 x float], [2004 x float]* %region1, i64 0, i64 1023
+  %ptr2 = getelementptr inbounds [2004 x float], [2004 x float]* %region2, i64 0, i64 1023
+  %float1 = load float , float *%ptr1
+  %float2 = load float , float *%ptr2
   %double1 = fpext float %float1 to double
   %double2 = fpext float %float2 to double
   store volatile double %double1, double *%dst
@@ -228,13 +228,13 @@ define void @f8(double *%dst) {
 ; CHECK-FP: br %r14
   %region1 = alloca [2006 x float], align 8
   %region2 = alloca [2006 x float], align 8
-  %start1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 0
+  %start1 = getelementptr inbounds [2006 x float], [2006 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [2006 x float], [2006 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 1023
-  %ptr2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 1023
-  %float1 = load float *%ptr1
-  %float2 = load float *%ptr2
+  %ptr1 = getelementptr inbounds [2006 x float], [2006 x float]* %region1, i64 0, i64 1023
+  %ptr2 = getelementptr inbounds [2006 x float], [2006 x float]* %region2, i64 0, i64 1023
+  %float1 = load float , float *%ptr1
+  %float2 = load float , float *%ptr2
   %double1 = fpext float %float1 to double
   %double2 = fpext float %float2 to double
   store volatile double %double1, double *%dst
@@ -257,13 +257,13 @@ define void @f9(double *%dst) {
 ; CHECK-FP: br %r14
   %region1 = alloca [2006 x float], align 8
   %region2 = alloca [2006 x float], align 8
-  %start1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 0
+  %start1 = getelementptr inbounds [2006 x float], [2006 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [2006 x float], [2006 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 1024
-  %ptr2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 1024
-  %float1 = load float *%ptr1
-  %float2 = load float *%ptr2
+  %ptr1 = getelementptr inbounds [2006 x float], [2006 x float]* %region1, i64 0, i64 1024
+  %ptr2 = getelementptr inbounds [2006 x float], [2006 x float]* %region2, i64 0, i64 1024
+  %float1 = load float , float *%ptr1
+  %float2 = load float , float *%ptr2
   %double1 = fpext float %float1 to double
   %double2 = fpext float %float2 to double
   store volatile double %double1, double *%dst
@@ -291,20 +291,20 @@ define void @f10(i32 *%vptr, double *%dst) {
 ; CHECK-FP: br %r14
   %region1 = alloca [978 x float], align 8
   %region2 = alloca [978 x float], align 8
-  %start1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 0
+  %start1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 2
-  %ptr2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 2
-  %i0 = load volatile i32 *%vptr
-  %i1 = load volatile i32 *%vptr
-  %i2 = load volatile i32 *%vptr
-  %i3 = load volatile i32 *%vptr
-  %i4 = load volatile i32 *%vptr
-  %i5 = load volatile i32 *%vptr
-  %i14 = load volatile i32 *%vptr
-  %float1 = load float *%ptr1
-  %float2 = load float *%ptr2
+  %ptr1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 2
+  %ptr2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 2
+  %i0 = load volatile i32 , i32 *%vptr
+  %i1 = load volatile i32 , i32 *%vptr
+  %i2 = load volatile i32 , i32 *%vptr
+  %i3 = load volatile i32 , i32 *%vptr
+  %i4 = load volatile i32 , i32 *%vptr
+  %i5 = load volatile i32 , i32 *%vptr
+  %i14 = load volatile i32 , i32 *%vptr
+  %float1 = load float , float *%ptr1
+  %float2 = load float , float *%ptr2
   %double1 = fpext float %float1 to double
   %double2 = fpext float %float2 to double
   store volatile double %double1, double *%dst
@@ -334,19 +334,19 @@ define void @f11(double *%dst, i64 %index) {
 ; CHECK-FP: br %r14
   %region1 = alloca [978 x float], align 8
   %region2 = alloca [978 x float], align 8
-  %start1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 0
+  %start1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %elem1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 2
-  %elem2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 2
+  %elem1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 2
+  %elem2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 2
   %base1 = ptrtoint float *%elem1 to i64
   %base2 = ptrtoint float *%elem2 to i64
   %addr1 = add i64 %base1, %index
   %addr2 = add i64 %base2, %index
   %ptr1 = inttoptr i64 %addr1 to float *
   %ptr2 = inttoptr i64 %addr2 to float *
-  %float1 = load float *%ptr1
-  %float2 = load float *%ptr2
+  %float1 = load float , float *%ptr1
+  %float2 = load float , float *%ptr2
   %double1 = fpext float %float1 to double
   %double2 = fpext float %float2 to double
   store volatile double %double1, double *%dst
diff --git a/test/CodeGen/SystemZ/frame-16.ll b/test/CodeGen/SystemZ/frame-16.ll
index f7e2dfa35149..75da04447b3a 100644
--- a/test/CodeGen/SystemZ/frame-16.ll
+++ b/test/CodeGen/SystemZ/frame-16.ll
@@ -33,8 +33,8 @@ define void @f1(i8 %byte) {
 ; CHECK-FP: br %r14
   %region1 = alloca [3912 x i8], align 8
   %region2 = alloca [3912 x i8], align 8
-  %ptr1 = getelementptr inbounds [3912 x i8]* %region1, i64 0, i64 7
-  %ptr2 = getelementptr inbounds [3912 x i8]* %region2, i64 0, i64 7
+  %ptr1 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region1, i64 0, i64 7
+  %ptr2 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region2, i64 0, i64 7
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -51,8 +51,8 @@ define void @f2(i8 %byte) {
 ; CHECK-FP: br %r14
   %region1 = alloca [3912 x i8], align 8
   %region2 = alloca [3912 x i8], align 8
-  %ptr1 = getelementptr inbounds [3912 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [3912 x i8]* %region2, i64 0, i64 8
+  %ptr1 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region2, i64 0, i64 8
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -72,8 +72,8 @@ define void @f3(i8 %byte) {
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
-  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 7
-  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 7
+  %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 7
+  %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 7
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -94,8 +94,8 @@ define void @f4(i8 %byte) {
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
-  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8
+  %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -115,8 +115,8 @@ define void @f5(i8 %byte) {
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
-  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 4103
-  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 4103
+  %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 4103
+  %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 4103
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -135,8 +135,8 @@ define void @f6(i8 %byte) {
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
-  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 4104
-  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 4104
+  %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 4104
+  %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 4104
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -158,8 +158,8 @@ define void @f7(i8 %byte) {
 ; CHECK-FP: br %r14
   %region1 = alloca [1048400 x i8], align 8
   %region2 = alloca [1048400 x i8], align 8
-  %ptr1 = getelementptr inbounds [1048400 x i8]* %region1, i64 0, i64 524287
-  %ptr2 = getelementptr inbounds [1048400 x i8]* %region2, i64 0, i64 524287
+  %ptr1 = getelementptr inbounds [1048400 x i8], [1048400 x i8]* %region1, i64 0, i64 524287
+  %ptr2 = getelementptr inbounds [1048400 x i8], [1048400 x i8]* %region2, i64 0, i64 524287
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -179,8 +179,8 @@ define void @f8(i8 %byte) {
 ; CHECK-FP: br %r14
   %region1 = alloca [1048408 x i8], align 8
   %region2 = alloca [1048408 x i8], align 8
-  %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524287
-  %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524287
+  %ptr1 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region1, i64 0, i64 524287
+  %ptr2 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region2, i64 0, i64 524287
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -209,8 +209,8 @@ define void @f9(i8 %byte) {
 ; CHECK-FP: br %r14
   %region1 = alloca [1048408 x i8], align 8
   %region2 = alloca [1048408 x i8], align 8
-  %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524288
-  %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524288
+  %ptr1 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region1, i64 0, i64 524288
+  %ptr2 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region2, i64 0, i64 524288
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -233,14 +233,14 @@ define void @f10(i32 *%vptr, i8 %byte) {
 ; CHECK-FP: stc %r3, 0([[REGISTER]],%r11)
 ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
 ; CHECK-FP: br %r14
-  %i0 = load volatile i32 *%vptr
-  %i1 = load volatile i32 *%vptr
-  %i4 = load volatile i32 *%vptr
-  %i5 = load volatile i32 *%vptr
+  %i0 = load volatile i32 , i32 *%vptr
+  %i1 = load volatile i32 , i32 *%vptr
+  %i4 = load volatile i32 , i32 *%vptr
+  %i5 = load volatile i32 , i32 *%vptr
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
-  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8
+  %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   store volatile i32 %i0, i32 *%vptr
@@ -272,23 +272,23 @@ define void @f11(i32 *%vptr, i8 %byte) {
 ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
 ; CHECK-FP: lmg %r6, %r15,
 ; CHECK-FP: br %r14
-  %i0 = load volatile i32 *%vptr
-  %i1 = load volatile i32 *%vptr
-  %i4 = load volatile i32 *%vptr
-  %i5 = load volatile i32 *%vptr
-  %i6 = load volatile i32 *%vptr
-  %i7 = load volatile i32 *%vptr
-  %i8 = load volatile i32 *%vptr
-  %i9 = load volatile i32 *%vptr
-  %i10 = load volatile i32 *%vptr
-  %i11 = load volatile i32 *%vptr
-  %i12 = load volatile i32 *%vptr
-  %i13 = load volatile i32 *%vptr
-  %i14 = load volatile i32 *%vptr
+  %i0 = load volatile i32 , i32 *%vptr
+  %i1 = load volatile i32 , i32 *%vptr
+  %i4 = load volatile i32 , i32 *%vptr
+  %i5 = load volatile i32 , i32 *%vptr
+  %i6 = load volatile i32 , i32 *%vptr
+  %i7 = load volatile i32 , i32 *%vptr
+  %i8 = load volatile i32 , i32 *%vptr
+  %i9 = load volatile i32 , i32 *%vptr
+  %i10 = load volatile i32 , i32 *%vptr
+  %i11 = load volatile i32 , i32 *%vptr
+  %i12 = load volatile i32 , i32 *%vptr
+  %i13 = load volatile i32 , i32 *%vptr
+  %i14 = load volatile i32 , i32 *%vptr
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
-  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8
+  %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   store volatile i32 %i0, i32 *%vptr
@@ -323,8 +323,8 @@ define void @f12(i8 %byte, i64 %index) {
   %region1 = alloca [524104 x i8], align 8
   %region2 = alloca [524104 x i8], align 8
   %index1 = add i64 %index, 8
-  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 %index1
-  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 %index1
+  %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 %index1
+  %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 %index1
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
diff --git a/test/CodeGen/SystemZ/frame-17.ll b/test/CodeGen/SystemZ/frame-17.ll
index 97cf83dfd78e..502e541bafc1 100644
--- a/test/CodeGen/SystemZ/frame-17.ll
+++ b/test/CodeGen/SystemZ/frame-17.ll
@@ -1,6 +1,6 @@
 ; Test spilling of FPRs.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; We need to save and restore 8 of the 16 FPRs and allocate an additional
 ; 4-byte spill slot, rounded to 8 bytes.  The frame size should be exactly
@@ -31,23 +31,23 @@ define void @f1(float *%ptr) {
 ; CHECK: ld %f15, 168(%r15)
 ; CHECK: aghi %r15, 232
 ; CHECK: br %r14
-  %l0 = load volatile float *%ptr
-  %l1 = load volatile float *%ptr
-  %l2 = load volatile float *%ptr
-  %l3 = load volatile float *%ptr
-  %l4 = load volatile float *%ptr
-  %l5 = load volatile float *%ptr
-  %l6 = load volatile float *%ptr
-  %l7 = load volatile float *%ptr
-  %l8 = load volatile float *%ptr
-  %l9 = load volatile float *%ptr
-  %l10 = load volatile float *%ptr
-  %l11 = load volatile float *%ptr
-  %l12 = load volatile float *%ptr
-  %l13 = load volatile float *%ptr
-  %l14 = load volatile float *%ptr
-  %l15 = load volatile float *%ptr
-  %lx = load volatile float *%ptr
+  %l0 = load volatile float , float *%ptr
+  %l1 = load volatile float , float *%ptr
+  %l2 = load volatile float , float *%ptr
+  %l3 = load volatile float , float *%ptr
+  %l4 = load volatile float , float *%ptr
+  %l5 = load volatile float , float *%ptr
+  %l6 = load volatile float , float *%ptr
+  %l7 = load volatile float , float *%ptr
+  %l8 = load volatile float , float *%ptr
+  %l9 = load volatile float , float *%ptr
+  %l10 = load volatile float , float *%ptr
+  %l11 = load volatile float , float *%ptr
+  %l12 = load volatile float , float *%ptr
+  %l13 = load volatile float , float *%ptr
+  %l14 = load volatile float , float *%ptr
+  %l15 = load volatile float , float *%ptr
+  %lx = load volatile float , float *%ptr
   store volatile float %lx, float *%ptr
   store volatile float %l15, float *%ptr
   store volatile float %l14, float *%ptr
@@ -92,23 +92,23 @@ define void @f2(double *%ptr) {
 ; CHECK: ld %f15, 168(%r15)
 ; CHECK: aghi %r15, 232
 ; CHECK: br %r14
-  %l0 = load volatile double *%ptr
-  %l1 = load volatile double *%ptr
-  %l2 = load volatile double *%ptr
-  %l3 = load volatile double *%ptr
-  %l4 = load volatile double *%ptr
-  %l5 = load volatile double *%ptr
-  %l6 = load volatile double *%ptr
-  %l7 = load volatile double *%ptr
-  %l8 = load volatile double *%ptr
-  %l9 = load volatile double *%ptr
-  %l10 = load volatile double *%ptr
-  %l11 = load volatile double *%ptr
-  %l12 = load volatile double *%ptr
-  %l13 = load volatile double *%ptr
-  %l14 = load volatile double *%ptr
-  %l15 = load volatile double *%ptr
-  %lx = load volatile double *%ptr
+  %l0 = load volatile double , double *%ptr
+  %l1 = load volatile double , double *%ptr
+  %l2 = load volatile double , double *%ptr
+  %l3 = load volatile double , double *%ptr
+  %l4 = load volatile double , double *%ptr
+  %l5 = load volatile double , double *%ptr
+  %l6 = load volatile double , double *%ptr
+  %l7 = load volatile double , double *%ptr
+  %l8 = load volatile double , double *%ptr
+  %l9 = load volatile double , double *%ptr
+  %l10 = load volatile double , double *%ptr
+  %l11 = load volatile double , double *%ptr
+  %l12 = load volatile double , double *%ptr
+  %l13 = load volatile double , double *%ptr
+  %l14 = load volatile double , double *%ptr
+  %l15 = load volatile double , double *%ptr
+  %lx = load volatile double , double *%ptr
   store volatile double %lx, double *%ptr
   store volatile double %l15, double *%ptr
   store volatile double %l14, double *%ptr
@@ -155,15 +155,15 @@ define void @f3(fp128 *%ptr) {
 ; CHECK: ld %f15, 176(%r15)
 ; CHECK: aghi %r15, 240
 ; CHECK: br %r14
-  %l0 = load volatile fp128 *%ptr
-  %l1 = load volatile fp128 *%ptr
-  %l4 = load volatile fp128 *%ptr
-  %l5 = load volatile fp128 *%ptr
-  %l8 = load volatile fp128 *%ptr
-  %l9 = load volatile fp128 *%ptr
-  %l12 = load volatile fp128 *%ptr
-  %l13 = load volatile fp128 *%ptr
-  %lx = load volatile fp128 *%ptr
+  %l0 = load volatile fp128 , fp128 *%ptr
+  %l1 = load volatile fp128 , fp128 *%ptr
+  %l4 = load volatile fp128 , fp128 *%ptr
+  %l5 = load volatile fp128 , fp128 *%ptr
+  %l8 = load volatile fp128 , fp128 *%ptr
+  %l9 = load volatile fp128 , fp128 *%ptr
+  %l12 = load volatile fp128 , fp128 *%ptr
+  %l13 = load volatile fp128 , fp128 *%ptr
+  %lx = load volatile fp128 , fp128 *%ptr
   store volatile fp128 %lx, fp128 *%ptr
   store volatile fp128 %l13, fp128 *%ptr
   store volatile fp128 %l12, fp128 *%ptr
diff --git a/test/CodeGen/SystemZ/frame-18.ll b/test/CodeGen/SystemZ/frame-18.ll
index 21dfc1238a13..0f58e437f9fd 100644
--- a/test/CodeGen/SystemZ/frame-18.ll
+++ b/test/CodeGen/SystemZ/frame-18.ll
@@ -16,21 +16,21 @@ define void @f1(i32 *%ptr) {
 ; CHECK-NOT: 160(%r15)
 ; CHECK: lmg %r6, %r15, 216(%r15)
 ; CHECK: br %r14
-  %l0 = load volatile i32 *%ptr
-  %l1 = load volatile i32 *%ptr
-  %l3 = load volatile i32 *%ptr
-  %l4 = load volatile i32 *%ptr
-  %l5 = load volatile i32 *%ptr
-  %l6 = load volatile i32 *%ptr
-  %l7 = load volatile i32 *%ptr
-  %l8 = load volatile i32 *%ptr
-  %l9 = load volatile i32 *%ptr
-  %l10 = load volatile i32 *%ptr
-  %l11 = load volatile i32 *%ptr
-  %l12 = load volatile i32 *%ptr
-  %l13 = load volatile i32 *%ptr
-  %l14 = load volatile i32 *%ptr
-  %lx = load volatile i32 *%ptr
+  %l0 = load volatile i32 , i32 *%ptr
+  %l1 = load volatile i32 , i32 *%ptr
+  %l3 = load volatile i32 , i32 *%ptr
+  %l4 = load volatile i32 , i32 *%ptr
+  %l5 = load volatile i32 , i32 *%ptr
+  %l6 = load volatile i32 , i32 *%ptr
+  %l7 = load volatile i32 , i32 *%ptr
+  %l8 = load volatile i32 , i32 *%ptr
+  %l9 = load volatile i32 , i32 *%ptr
+  %l10 = load volatile i32 , i32 *%ptr
+  %l11 = load volatile i32 , i32 *%ptr
+  %l12 = load volatile i32 , i32 *%ptr
+  %l13 = load volatile i32 , i32 *%ptr
+  %l14 = load volatile i32 , i32 *%ptr
+  %lx = load volatile i32 , i32 *%ptr
   store volatile i32 %lx, i32 *%ptr
   store volatile i32 %l14, i32 *%ptr
   store volatile i32 %l13, i32 *%ptr
@@ -58,21 +58,21 @@ define void @f2(i64 *%ptr) {
 ; CHECK: lg [[REGISTER]], 160(%r15)
 ; CHECK: lmg %r6, %r15, 216(%r15)
 ; CHECK: br %r14
-  %l0 = load volatile i64 *%ptr
-  %l1 = load volatile i64 *%ptr
-  %l3 = load volatile i64 *%ptr
-  %l4 = load volatile i64 *%ptr
-  %l5 = load volatile i64 *%ptr
-  %l6 = load volatile i64 *%ptr
-  %l7 = load volatile i64 *%ptr
-  %l8 = load volatile i64 *%ptr
-  %l9 = load volatile i64 *%ptr
-  %l10 = load volatile i64 *%ptr
-  %l11 = load volatile i64 *%ptr
-  %l12 = load volatile i64 *%ptr
-  %l13 = load volatile i64 *%ptr
-  %l14 = load volatile i64 *%ptr
-  %lx = load volatile i64 *%ptr
+  %l0 = load volatile i64 , i64 *%ptr
+  %l1 = load volatile i64 , i64 *%ptr
+  %l3 = load volatile i64 , i64 *%ptr
+  %l4 = load volatile i64 , i64 *%ptr
+  %l5 = load volatile i64 , i64 *%ptr
+  %l6 = load volatile i64 , i64 *%ptr
+  %l7 = load volatile i64 , i64 *%ptr
+  %l8 = load volatile i64 , i64 *%ptr
+  %l9 = load volatile i64 , i64 *%ptr
+  %l10 = load volatile i64 , i64 *%ptr
+  %l11 = load volatile i64 , i64 *%ptr
+  %l12 = load volatile i64 , i64 *%ptr
+  %l13 = load volatile i64 , i64 *%ptr
+  %l14 = load volatile i64 , i64 *%ptr
+  %lx = load volatile i64 , i64 *%ptr
   store volatile i64 %lx, i64 *%ptr
   store volatile i64 %l14, i64 *%ptr
   store volatile i64 %l13, i64 *%ptr
diff --git a/test/CodeGen/SystemZ/frame-19.ll b/test/CodeGen/SystemZ/frame-19.ll
new file mode 100644
index 000000000000..f6e327c3ae39
--- /dev/null
+++ b/test/CodeGen/SystemZ/frame-19.ll
@@ -0,0 +1,314 @@
+; Test spilling of vector registers.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; We need to allocate a 16-byte spill slot and save the 8 call-saved FPRs.
+; The frame size should be exactly 160 + 16 + 8 * 8 = 240.
+define void @f1(<16 x i8> *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: aghi %r15, -240
+; CHECK-DAG: std %f8,
+; CHECK-DAG: std %f9,
+; CHECK-DAG: std %f10,
+; CHECK-DAG: std %f11,
+; CHECK-DAG: std %f12,
+; CHECK-DAG: std %f13,
+; CHECK-DAG: std %f14,
+; CHECK-DAG: std %f15,
+; CHECK: vst {{%v[0-9]+}}, 160(%r15)
+; CHECK: vl {{%v[0-9]+}}, 160(%r15)
+; CHECK-DAG: ld %f8,
+; CHECK-DAG: ld %f9,
+; CHECK-DAG: ld %f10,
+; CHECK-DAG: ld %f11,
+; CHECK-DAG: ld %f12,
+; CHECK-DAG: ld %f13,
+; CHECK-DAG: ld %f14,
+; CHECK-DAG: ld %f15,
+; CHECK: aghi %r15, 240
+; CHECK: br %r14
+  %v0 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v1 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v2 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v3 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v4 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v5 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v6 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v7 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v8 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v9 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v10 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v11 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v12 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v13 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v14 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v15 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v16 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v17 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v18 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v19 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v20 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v21 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v22 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v23 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v24 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v25 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v26 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v27 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v28 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v29 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v30 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v31 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %vx = load volatile <16 x i8>, <16 x i8> *%ptr
+  store volatile <16 x i8> %vx, <16 x i8> *%ptr
+  store volatile <16 x i8> %v31, <16 x i8> *%ptr
+  store volatile <16 x i8> %v30, <16 x i8> *%ptr
+  store volatile <16 x i8> %v29, <16 x i8> *%ptr
+  store volatile <16 x i8> %v28, <16 x i8> *%ptr
+  store volatile <16 x i8> %v27, <16 x i8> *%ptr
+  store volatile <16 x i8> %v26, <16 x i8> *%ptr
+  store volatile <16 x i8> %v25, <16 x i8> *%ptr
+  store volatile <16 x i8> %v24, <16 x i8> *%ptr
+  store volatile <16 x i8> %v23, <16 x i8> *%ptr
+  store volatile <16 x i8> %v22, <16 x i8> *%ptr
+  store volatile <16 x i8> %v21, <16 x i8> *%ptr
+  store volatile <16 x i8> %v20, <16 x i8> *%ptr
+  store volatile <16 x i8> %v19, <16 x i8> *%ptr
+  store volatile <16 x i8> %v18, <16 x i8> *%ptr
+  store volatile <16 x i8> %v17, <16 x i8> *%ptr
+  store volatile <16 x i8> %v16, <16 x i8> *%ptr
+  store volatile <16 x i8> %v15, <16 x i8> *%ptr
+  store volatile <16 x i8> %v14, <16 x i8> *%ptr
+  store volatile <16 x i8> %v13, <16 x i8> *%ptr
+  store volatile <16 x i8> %v12, <16 x i8> *%ptr
+  store volatile <16 x i8> %v11, <16 x i8> *%ptr
+  store volatile <16 x i8> %v10, <16 x i8> *%ptr
+  store volatile <16 x i8> %v9, <16 x i8> *%ptr
+  store volatile <16 x i8> %v8, <16 x i8> *%ptr
+  store volatile <16 x i8> %v7, <16 x i8> *%ptr
+  store volatile <16 x i8> %v6, <16 x i8> *%ptr
+  store volatile <16 x i8> %v5, <16 x i8> *%ptr
+  store volatile <16 x i8> %v4, <16 x i8> *%ptr
+  store volatile <16 x i8> %v3, <16 x i8> *%ptr
+  store volatile <16 x i8> %v2, <16 x i8> *%ptr
+  store volatile <16 x i8> %v1, <16 x i8> *%ptr
+  store volatile <16 x i8> %v0, <16 x i8> *%ptr
+  ret void
+}
+
+; Like f1, but no 16-byte slot should be needed.
+define void @f2(<16 x i8> *%ptr) {
+; CHECK-LABEL: f2:
+; CHECK: aghi %r15, -224
+; CHECK-DAG: std %f8,
+; CHECK-DAG: std %f9,
+; CHECK-DAG: std %f10,
+; CHECK-DAG: std %f11,
+; CHECK-DAG: std %f12,
+; CHECK-DAG: std %f13,
+; CHECK-DAG: std %f14,
+; CHECK-DAG: std %f15,
+; CHECK-NOT: vst {{.*}}(%r15)
+; CHECK-NOT: vl {{.*}}(%r15)
+; CHECK-DAG: ld %f8,
+; CHECK-DAG: ld %f9,
+; CHECK-DAG: ld %f10,
+; CHECK-DAG: ld %f11,
+; CHECK-DAG: ld %f12,
+; CHECK-DAG: ld %f13,
+; CHECK-DAG: ld %f14,
+; CHECK-DAG: ld %f15,
+; CHECK: aghi %r15, 224
+; CHECK: br %r14
+  %v0 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v1 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v2 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v3 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v4 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v5 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v6 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v7 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v8 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v9 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v10 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v11 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v12 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v13 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v14 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v15 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v16 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v17 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v18 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v19 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v20 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v21 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v22 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v23 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v24 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v25 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v26 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v27 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v28 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v29 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v30 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v31 = load volatile <16 x i8>, <16 x i8> *%ptr
+  store volatile <16 x i8> %v31, <16 x i8> *%ptr
+  store volatile <16 x i8> %v30, <16 x i8> *%ptr
+  store volatile <16 x i8> %v29, <16 x i8> *%ptr
+  store volatile <16 x i8> %v28, <16 x i8> *%ptr
+  store volatile <16 x i8> %v27, <16 x i8> *%ptr
+  store volatile <16 x i8> %v26, <16 x i8> *%ptr
+  store volatile <16 x i8> %v25, <16 x i8> *%ptr
+  store volatile <16 x i8> %v24, <16 x i8> *%ptr
+  store volatile <16 x i8> %v23, <16 x i8> *%ptr
+  store volatile <16 x i8> %v22, <16 x i8> *%ptr
+  store volatile <16 x i8> %v21, <16 x i8> *%ptr
+  store volatile <16 x i8> %v20, <16 x i8> *%ptr
+  store volatile <16 x i8> %v19, <16 x i8> *%ptr
+  store volatile <16 x i8> %v18, <16 x i8> *%ptr
+  store volatile <16 x i8> %v17, <16 x i8> *%ptr
+  store volatile <16 x i8> %v16, <16 x i8> *%ptr
+  store volatile <16 x i8> %v15, <16 x i8> *%ptr
+  store volatile <16 x i8> %v14, <16 x i8> *%ptr
+  store volatile <16 x i8> %v13, <16 x i8> *%ptr
+  store volatile <16 x i8> %v12, <16 x i8> *%ptr
+  store volatile <16 x i8> %v11, <16 x i8> *%ptr
+  store volatile <16 x i8> %v10, <16 x i8> *%ptr
+  store volatile <16 x i8> %v9, <16 x i8> *%ptr
+  store volatile <16 x i8> %v8, <16 x i8> *%ptr
+  store volatile <16 x i8> %v7, <16 x i8> *%ptr
+  store volatile <16 x i8> %v6, <16 x i8> *%ptr
+  store volatile <16 x i8> %v5, <16 x i8> *%ptr
+  store volatile <16 x i8> %v4, <16 x i8> *%ptr
+  store volatile <16 x i8> %v3, <16 x i8> *%ptr
+  store volatile <16 x i8> %v2, <16 x i8> *%ptr
+  store volatile <16 x i8> %v1, <16 x i8> *%ptr
+  store volatile <16 x i8> %v0, <16 x i8> *%ptr
+  ret void
+}
+
+; Like f2, but only %f8 should be saved.
+define void @f3(<16 x i8> *%ptr) {
+; CHECK-LABEL: f3:
+; CHECK: aghi %r15, -168
+; CHECK-DAG: std %f8,
+; CHECK-NOT: vst {{.*}}(%r15)
+; CHECK-NOT: vl {{.*}}(%r15)
+; CHECK-NOT: %v9
+; CHECK-NOT: %v10
+; CHECK-NOT: %v11
+; CHECK-NOT: %v12
+; CHECK-NOT: %v13
+; CHECK-NOT: %v14
+; CHECK-NOT: %v15
+; CHECK-DAG: ld %f8,
+; CHECK: aghi %r15, 168
+; CHECK: br %r14
+  %v0 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v1 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v2 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v3 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v4 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v5 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v6 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v7 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v8 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v16 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v17 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v18 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v19 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v20 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v21 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v22 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v23 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v24 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v25 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v26 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v27 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v28 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v29 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v30 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v31 = load volatile <16 x i8>, <16 x i8> *%ptr
+  store volatile <16 x i8> %v31, <16 x i8> *%ptr
+  store volatile <16 x i8> %v30, <16 x i8> *%ptr
+  store volatile <16 x i8> %v29, <16 x i8> *%ptr
+  store volatile <16 x i8> %v28, <16 x i8> *%ptr
+  store volatile <16 x i8> %v27, <16 x i8> *%ptr
+  store volatile <16 x i8> %v26, <16 x i8> *%ptr
+  store volatile <16 x i8> %v25, <16 x i8> *%ptr
+  store volatile <16 x i8> %v24, <16 x i8> *%ptr
+  store volatile <16 x i8> %v23, <16 x i8> *%ptr
+  store volatile <16 x i8> %v22, <16 x i8> *%ptr
+  store volatile <16 x i8> %v21, <16 x i8> *%ptr
+  store volatile <16 x i8> %v20, <16 x i8> *%ptr
+  store volatile <16 x i8> %v19, <16 x i8> *%ptr
+  store volatile <16 x i8> %v18, <16 x i8> *%ptr
+  store volatile <16 x i8> %v17, <16 x i8> *%ptr
+  store volatile <16 x i8> %v16, <16 x i8> *%ptr
+  store volatile <16 x i8> %v8, <16 x i8> *%ptr
+  store volatile <16 x i8> %v7, <16 x i8> *%ptr
+  store volatile <16 x i8> %v6, <16 x i8> *%ptr
+  store volatile <16 x i8> %v5, <16 x i8> *%ptr
+  store volatile <16 x i8> %v4, <16 x i8> *%ptr
+  store volatile <16 x i8> %v3, <16 x i8> *%ptr
+  store volatile <16 x i8> %v2, <16 x i8> *%ptr
+  store volatile <16 x i8> %v1, <16 x i8> *%ptr
+  store volatile <16 x i8> %v0, <16 x i8> *%ptr
+  ret void
+}
+
+; Like f2, but no registers should be saved.
+define void @f4(<16 x i8> *%ptr) {
+; CHECK-LABEL: f4:
+; CHECK-NOT: %r15
+; CHECK: br %r14
+  %v0 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v1 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v2 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v3 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v4 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v5 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v6 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v7 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v16 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v17 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v18 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v19 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v20 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v21 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v22 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v23 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v24 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v25 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v26 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v27 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v28 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v29 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v30 = load volatile <16 x i8>, <16 x i8> *%ptr
+  %v31 = load volatile <16 x i8>, <16 x i8> *%ptr
+  store volatile <16 x i8> %v31, <16 x i8> *%ptr
+  store volatile <16 x i8> %v30, <16 x i8> *%ptr
+  store volatile <16 x i8> %v29, <16 x i8> *%ptr
+  store volatile <16 x i8> %v28, <16 x i8> *%ptr
+  store volatile <16 x i8> %v27, <16 x i8> *%ptr
+  store volatile <16 x i8> %v26, <16 x i8> *%ptr
+  store volatile <16 x i8> %v25, <16 x i8> *%ptr
+  store volatile <16 x i8> %v24, <16 x i8> *%ptr
+  store volatile <16 x i8> %v23, <16 x i8> *%ptr
+  store volatile <16 x i8> %v22, <16 x i8> *%ptr
+  store volatile <16 x i8> %v21, <16 x i8> *%ptr
+  store volatile <16 x i8> %v20, <16 x i8> *%ptr
+  store volatile <16 x i8> %v19, <16 x i8> *%ptr
+  store volatile <16 x i8> %v18, <16 x i8> *%ptr
+  store volatile <16 x i8> %v17, <16 x i8> *%ptr
+  store volatile <16 x i8> %v16, <16 x i8> *%ptr
+  store volatile <16 x i8> %v7, <16 x i8> *%ptr
+  store volatile <16 x i8> %v6, <16 x i8> *%ptr
+  store volatile <16 x i8> %v5, <16 x i8> *%ptr
+  store volatile <16 x i8> %v4, <16 x i8> *%ptr
+  store volatile <16 x i8> %v3, <16 x i8> *%ptr
+  store volatile <16 x i8> %v2, <16 x i8> *%ptr
+  store volatile <16 x i8> %v1, <16 x i8> *%ptr
+  store volatile <16 x i8> %v0, <16 x i8> *%ptr
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/frame-20.ll b/test/CodeGen/SystemZ/frame-20.ll
new file mode 100644
index 000000000000..8d601c6f6d51
--- /dev/null
+++ b/test/CodeGen/SystemZ/frame-20.ll
@@ -0,0 +1,445 @@
+; Like frame-03.ll, but for z13.  In this case we have 16 more registers
+; available.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; This function should require all FPRs, but no other spill slots.
+; We need to save and restore 8 of the 16 FPRs, so the frame size
+; should be exactly 160 + 8 * 8 = 224.  The CFA offset is 160
+; (the caller-allocated part of the frame) + 224.
+define void @f1(double *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: aghi %r15, -224
+; CHECK: .cfi_def_cfa_offset 384
+; CHECK: std %f8, 216(%r15)
+; CHECK: std %f9, 208(%r15)
+; CHECK: std %f10, 200(%r15)
+; CHECK: std %f11, 192(%r15)
+; CHECK: std %f12, 184(%r15)
+; CHECK: std %f13, 176(%r15)
+; CHECK: std %f14, 168(%r15)
+; CHECK: std %f15, 160(%r15)
+; CHECK: .cfi_offset %f8, -168
+; CHECK: .cfi_offset %f9, -176
+; CHECK: .cfi_offset %f10, -184
+; CHECK: .cfi_offset %f11, -192
+; CHECK: .cfi_offset %f12, -200
+; CHECK: .cfi_offset %f13, -208
+; CHECK: .cfi_offset %f14, -216
+; CHECK: .cfi_offset %f15, -224
+; CHECK-DAG: ld %f0, 0(%r2)
+; CHECK-DAG: ld %f7, 0(%r2)
+; CHECK-DAG: ld %f8, 0(%r2)
+; CHECK-DAG: ld %f15, 0(%r2)
+; CHECK-DAG: vlrepg %v16, 0(%r2)
+; CHECK-DAG: vlrepg %v23, 0(%r2)
+; CHECK-DAG: vlrepg %v24, 0(%r2)
+; CHECK-DAG: vlrepg %v31, 0(%r2)
+; CHECK: ld %f8, 216(%r15)
+; CHECK: ld %f9, 208(%r15)
+; CHECK: ld %f10, 200(%r15)
+; CHECK: ld %f11, 192(%r15)
+; CHECK: ld %f12, 184(%r15)
+; CHECK: ld %f13, 176(%r15)
+; CHECK: ld %f14, 168(%r15)
+; CHECK: ld %f15, 160(%r15)
+; CHECK: aghi %r15, 224
+; CHECK: br %r14
+  %l0 = load volatile double, double *%ptr
+  %l1 = load volatile double, double *%ptr
+  %l2 = load volatile double, double *%ptr
+  %l3 = load volatile double, double *%ptr
+  %l4 = load volatile double, double *%ptr
+  %l5 = load volatile double, double *%ptr
+  %l6 = load volatile double, double *%ptr
+  %l7 = load volatile double, double *%ptr
+  %l8 = load volatile double, double *%ptr
+  %l9 = load volatile double, double *%ptr
+  %l10 = load volatile double, double *%ptr
+  %l11 = load volatile double, double *%ptr
+  %l12 = load volatile double, double *%ptr
+  %l13 = load volatile double, double *%ptr
+  %l14 = load volatile double, double *%ptr
+  %l15 = load volatile double, double *%ptr
+  %l16 = load volatile double, double *%ptr
+  %l17 = load volatile double, double *%ptr
+  %l18 = load volatile double, double *%ptr
+  %l19 = load volatile double, double *%ptr
+  %l20 = load volatile double, double *%ptr
+  %l21 = load volatile double, double *%ptr
+  %l22 = load volatile double, double *%ptr
+  %l23 = load volatile double, double *%ptr
+  %l24 = load volatile double, double *%ptr
+  %l25 = load volatile double, double *%ptr
+  %l26 = load volatile double, double *%ptr
+  %l27 = load volatile double, double *%ptr
+  %l28 = load volatile double, double *%ptr
+  %l29 = load volatile double, double *%ptr
+  %l30 = load volatile double, double *%ptr
+  %l31 = load volatile double, double *%ptr
+  %acc0 = fsub double %l0, %l0
+  %acc1 = fsub double %l1, %acc0
+  %acc2 = fsub double %l2, %acc1
+  %acc3 = fsub double %l3, %acc2
+  %acc4 = fsub double %l4, %acc3
+  %acc5 = fsub double %l5, %acc4
+  %acc6 = fsub double %l6, %acc5
+  %acc7 = fsub double %l7, %acc6
+  %acc8 = fsub double %l8, %acc7
+  %acc9 = fsub double %l9, %acc8
+  %acc10 = fsub double %l10, %acc9
+  %acc11 = fsub double %l11, %acc10
+  %acc12 = fsub double %l12, %acc11
+  %acc13 = fsub double %l13, %acc12
+  %acc14 = fsub double %l14, %acc13
+  %acc15 = fsub double %l15, %acc14
+  %acc16 = fsub double %l16, %acc15
+  %acc17 = fsub double %l17, %acc16
+  %acc18 = fsub double %l18, %acc17
+  %acc19 = fsub double %l19, %acc18
+  %acc20 = fsub double %l20, %acc19
+  %acc21 = fsub double %l21, %acc20
+  %acc22 = fsub double %l22, %acc21
+  %acc23 = fsub double %l23, %acc22
+  %acc24 = fsub double %l24, %acc23
+  %acc25 = fsub double %l25, %acc24
+  %acc26 = fsub double %l26, %acc25
+  %acc27 = fsub double %l27, %acc26
+  %acc28 = fsub double %l28, %acc27
+  %acc29 = fsub double %l29, %acc28
+  %acc30 = fsub double %l30, %acc29
+  %acc31 = fsub double %l31, %acc30
+  store volatile double %acc0, double *%ptr
+  store volatile double %acc1, double *%ptr
+  store volatile double %acc2, double *%ptr
+  store volatile double %acc3, double *%ptr
+  store volatile double %acc4, double *%ptr
+  store volatile double %acc5, double *%ptr
+  store volatile double %acc6, double *%ptr
+  store volatile double %acc7, double *%ptr
+  store volatile double %acc8, double *%ptr
+  store volatile double %acc9, double *%ptr
+  store volatile double %acc10, double *%ptr
+  store volatile double %acc11, double *%ptr
+  store volatile double %acc12, double *%ptr
+  store volatile double %acc13, double *%ptr
+  store volatile double %acc14, double *%ptr
+  store volatile double %acc15, double *%ptr
+  store volatile double %acc16, double *%ptr
+  store volatile double %acc17, double *%ptr
+  store volatile double %acc18, double *%ptr
+  store volatile double %acc19, double *%ptr
+  store volatile double %acc20, double *%ptr
+  store volatile double %acc21, double *%ptr
+  store volatile double %acc22, double *%ptr
+  store volatile double %acc23, double *%ptr
+  store volatile double %acc24, double *%ptr
+  store volatile double %acc25, double *%ptr
+  store volatile double %acc26, double *%ptr
+  store volatile double %acc27, double *%ptr
+  store volatile double %acc28, double *%ptr
+  store volatile double %acc29, double *%ptr
+  store volatile double %acc30, double *%ptr
+  store volatile double %acc31, double *%ptr
+  ret void
+}
+
+; Like f1, but requires one fewer FPR.  We allocate in numerical order,
+; so %f15 is the one that gets dropped.
+define void @f2(double *%ptr) {
+; CHECK-LABEL: f2:
+; CHECK: aghi %r15, -216
+; CHECK: .cfi_def_cfa_offset 376
+; CHECK: std %f8, 208(%r15)
+; CHECK: std %f9, 200(%r15)
+; CHECK: std %f10, 192(%r15)
+; CHECK: std %f11, 184(%r15)
+; CHECK: std %f12, 176(%r15)
+; CHECK: std %f13, 168(%r15)
+; CHECK: std %f14, 160(%r15)
+; CHECK: .cfi_offset %f8, -168
+; CHECK: .cfi_offset %f9, -176
+; CHECK: .cfi_offset %f10, -184
+; CHECK: .cfi_offset %f11, -192
+; CHECK: .cfi_offset %f12, -200
+; CHECK: .cfi_offset %f13, -208
+; CHECK: .cfi_offset %f14, -216
+; CHECK-NOT: %v15
+; CHECK-NOT: %f15
+; CHECK: ld %f8, 208(%r15)
+; CHECK: ld %f9, 200(%r15)
+; CHECK: ld %f10, 192(%r15)
+; CHECK: ld %f11, 184(%r15)
+; CHECK: ld %f12, 176(%r15)
+; CHECK: ld %f13, 168(%r15)
+; CHECK: ld %f14, 160(%r15)
+; CHECK: aghi %r15, 216
+; CHECK: br %r14
+  %l0 = load volatile double, double *%ptr
+  %l1 = load volatile double, double *%ptr
+  %l2 = load volatile double, double *%ptr
+  %l3 = load volatile double, double *%ptr
+  %l4 = load volatile double, double *%ptr
+  %l5 = load volatile double, double *%ptr
+  %l6 = load volatile double, double *%ptr
+  %l7 = load volatile double, double *%ptr
+  %l8 = load volatile double, double *%ptr
+  %l9 = load volatile double, double *%ptr
+  %l10 = load volatile double, double *%ptr
+  %l11 = load volatile double, double *%ptr
+  %l12 = load volatile double, double *%ptr
+  %l13 = load volatile double, double *%ptr
+  %l14 = load volatile double, double *%ptr
+  %l16 = load volatile double, double *%ptr
+  %l17 = load volatile double, double *%ptr
+  %l18 = load volatile double, double *%ptr
+  %l19 = load volatile double, double *%ptr
+  %l20 = load volatile double, double *%ptr
+  %l21 = load volatile double, double *%ptr
+  %l22 = load volatile double, double *%ptr
+  %l23 = load volatile double, double *%ptr
+  %l24 = load volatile double, double *%ptr
+  %l25 = load volatile double, double *%ptr
+  %l26 = load volatile double, double *%ptr
+  %l27 = load volatile double, double *%ptr
+  %l28 = load volatile double, double *%ptr
+  %l29 = load volatile double, double *%ptr
+  %l30 = load volatile double, double *%ptr
+  %l31 = load volatile double, double *%ptr
+  %acc0 = fsub double %l0, %l0
+  %acc1 = fsub double %l1, %acc0
+  %acc2 = fsub double %l2, %acc1
+  %acc3 = fsub double %l3, %acc2
+  %acc4 = fsub double %l4, %acc3
+  %acc5 = fsub double %l5, %acc4
+  %acc6 = fsub double %l6, %acc5
+  %acc7 = fsub double %l7, %acc6
+  %acc8 = fsub double %l8, %acc7
+  %acc9 = fsub double %l9, %acc8
+  %acc10 = fsub double %l10, %acc9
+  %acc11 = fsub double %l11, %acc10
+  %acc12 = fsub double %l12, %acc11
+  %acc13 = fsub double %l13, %acc12
+  %acc14 = fsub double %l14, %acc13
+  %acc16 = fsub double %l16, %acc14
+  %acc17 = fsub double %l17, %acc16
+  %acc18 = fsub double %l18, %acc17
+  %acc19 = fsub double %l19, %acc18
+  %acc20 = fsub double %l20, %acc19
+  %acc21 = fsub double %l21, %acc20
+  %acc22 = fsub double %l22, %acc21
+  %acc23 = fsub double %l23, %acc22
+  %acc24 = fsub double %l24, %acc23
+  %acc25 = fsub double %l25, %acc24
+  %acc26 = fsub double %l26, %acc25
+  %acc27 = fsub double %l27, %acc26
+  %acc28 = fsub double %l28, %acc27
+  %acc29 = fsub double %l29, %acc28
+  %acc30 = fsub double %l30, %acc29
+  %acc31 = fsub double %l31, %acc30
+  store volatile double %acc0, double *%ptr
+  store volatile double %acc1, double *%ptr
+  store volatile double %acc2, double *%ptr
+  store volatile double %acc3, double *%ptr
+  store volatile double %acc4, double *%ptr
+  store volatile double %acc5, double *%ptr
+  store volatile double %acc6, double *%ptr
+  store volatile double %acc7, double *%ptr
+  store volatile double %acc8, double *%ptr
+  store volatile double %acc9, double *%ptr
+  store volatile double %acc10, double *%ptr
+  store volatile double %acc11, double *%ptr
+  store volatile double %acc12, double *%ptr
+  store volatile double %acc13, double *%ptr
+  store volatile double %acc14, double *%ptr
+  store volatile double %acc16, double *%ptr
+  store volatile double %acc17, double *%ptr
+  store volatile double %acc18, double *%ptr
+  store volatile double %acc19, double *%ptr
+  store volatile double %acc20, double *%ptr
+  store volatile double %acc21, double *%ptr
+  store volatile double %acc22, double *%ptr
+  store volatile double %acc23, double *%ptr
+  store volatile double %acc24, double *%ptr
+  store volatile double %acc25, double *%ptr
+  store volatile double %acc26, double *%ptr
+  store volatile double %acc27, double *%ptr
+  store volatile double %acc28, double *%ptr
+  store volatile double %acc29, double *%ptr
+  store volatile double %acc30, double *%ptr
+  store volatile double %acc31, double *%ptr
+  ret void
+}
+
+; Like f1, but should require only one call-saved FPR.
+define void @f3(double *%ptr) {
+; CHECK-LABEL: f3:
+; CHECK: aghi %r15, -168
+; CHECK: .cfi_def_cfa_offset 328
+; CHECK: std %f8, 160(%r15)
+; CHECK: .cfi_offset %f8, -168
+; CHECK-NOT: {{%[fv]9}}
+; CHECK-NOT: {{%[fv]1[0-5]}}
+; CHECK: ld %f8, 160(%r15)
+; CHECK: aghi %r15, 168
+; CHECK: br %r14
+  %l0 = load volatile double, double *%ptr
+  %l1 = load volatile double, double *%ptr
+  %l2 = load volatile double, double *%ptr
+  %l3 = load volatile double, double *%ptr
+  %l4 = load volatile double, double *%ptr
+  %l5 = load volatile double, double *%ptr
+  %l6 = load volatile double, double *%ptr
+  %l7 = load volatile double, double *%ptr
+  %l8 = load volatile double, double *%ptr
+  %l16 = load volatile double, double *%ptr
+  %l17 = load volatile double, double *%ptr
+  %l18 = load volatile double, double *%ptr
+  %l19 = load volatile double, double *%ptr
+  %l20 = load volatile double, double *%ptr
+  %l21 = load volatile double, double *%ptr
+  %l22 = load volatile double, double *%ptr
+  %l23 = load volatile double, double *%ptr
+  %l24 = load volatile double, double *%ptr
+  %l25 = load volatile double, double *%ptr
+  %l26 = load volatile double, double *%ptr
+  %l27 = load volatile double, double *%ptr
+  %l28 = load volatile double, double *%ptr
+  %l29 = load volatile double, double *%ptr
+  %l30 = load volatile double, double *%ptr
+  %l31 = load volatile double, double *%ptr
+  %acc0 = fsub double %l0, %l0
+  %acc1 = fsub double %l1, %acc0
+  %acc2 = fsub double %l2, %acc1
+  %acc3 = fsub double %l3, %acc2
+  %acc4 = fsub double %l4, %acc3
+  %acc5 = fsub double %l5, %acc4
+  %acc6 = fsub double %l6, %acc5
+  %acc7 = fsub double %l7, %acc6
+  %acc8 = fsub double %l8, %acc7
+  %acc16 = fsub double %l16, %acc8
+  %acc17 = fsub double %l17, %acc16
+  %acc18 = fsub double %l18, %acc17
+  %acc19 = fsub double %l19, %acc18
+  %acc20 = fsub double %l20, %acc19
+  %acc21 = fsub double %l21, %acc20
+  %acc22 = fsub double %l22, %acc21
+  %acc23 = fsub double %l23, %acc22
+  %acc24 = fsub double %l24, %acc23
+  %acc25 = fsub double %l25, %acc24
+  %acc26 = fsub double %l26, %acc25
+  %acc27 = fsub double %l27, %acc26
+  %acc28 = fsub double %l28, %acc27
+  %acc29 = fsub double %l29, %acc28
+  %acc30 = fsub double %l30, %acc29
+  %acc31 = fsub double %l31, %acc30
+  store volatile double %acc0, double *%ptr
+  store volatile double %acc1, double *%ptr
+  store volatile double %acc2, double *%ptr
+  store volatile double %acc3, double *%ptr
+  store volatile double %acc4, double *%ptr
+  store volatile double %acc5, double *%ptr
+  store volatile double %acc6, double *%ptr
+  store volatile double %acc7, double *%ptr
+  store volatile double %acc8, double *%ptr
+  store volatile double %acc16, double *%ptr
+  store volatile double %acc17, double *%ptr
+  store volatile double %acc18, double *%ptr
+  store volatile double %acc19, double *%ptr
+  store volatile double %acc20, double *%ptr
+  store volatile double %acc21, double *%ptr
+  store volatile double %acc22, double *%ptr
+  store volatile double %acc23, double *%ptr
+  store volatile double %acc24, double *%ptr
+  store volatile double %acc25, double *%ptr
+  store volatile double %acc26, double *%ptr
+  store volatile double %acc27, double *%ptr
+  store volatile double %acc28, double *%ptr
+  store volatile double %acc29, double *%ptr
+  store volatile double %acc30, double *%ptr
+  store volatile double %acc31, double *%ptr
+  ret void
+}
+
+; This function should use all call-clobbered FPRs and vector registers
+; but no call-saved ones.  It shouldn't need to create a frame.
+define void @f4(double *%ptr) {
+; CHECK-LABEL: f4:
+; CHECK-NOT: %r15
+; CHECK-NOT: {{%[fv][89]}}
+; CHECK-NOT: {{%[fv]1[0-5]}}
+; CHECK: br %r14
+  %l0 = load volatile double, double *%ptr
+  %l1 = load volatile double, double *%ptr
+  %l2 = load volatile double, double *%ptr
+  %l3 = load volatile double, double *%ptr
+  %l4 = load volatile double, double *%ptr
+  %l5 = load volatile double, double *%ptr
+  %l6 = load volatile double, double *%ptr
+  %l7 = load volatile double, double *%ptr
+  %l16 = load volatile double, double *%ptr
+  %l17 = load volatile double, double *%ptr
+  %l18 = load volatile double, double *%ptr
+  %l19 = load volatile double, double *%ptr
+  %l20 = load volatile double, double *%ptr
+  %l21 = load volatile double, double *%ptr
+  %l22 = load volatile double, double *%ptr
+  %l23 = load volatile double, double *%ptr
+  %l24 = load volatile double, double *%ptr
+  %l25 = load volatile double, double *%ptr
+  %l26 = load volatile double, double *%ptr
+  %l27 = load volatile double, double *%ptr
+  %l28 = load volatile double, double *%ptr
+  %l29 = load volatile double, double *%ptr
+  %l30 = load volatile double, double *%ptr
+  %l31 = load volatile double, double *%ptr
+  %acc0 = fsub double %l0, %l0
+  %acc1 = fsub double %l1, %acc0
+  %acc2 = fsub double %l2, %acc1
+  %acc3 = fsub double %l3, %acc2
+  %acc4 = fsub double %l4, %acc3
+  %acc5 = fsub double %l5, %acc4
+  %acc6 = fsub double %l6, %acc5
+  %acc7 = fsub double %l7, %acc6
+  %acc16 = fsub double %l16, %acc7
+  %acc17 = fsub double %l17, %acc16
+  %acc18 = fsub double %l18, %acc17
+  %acc19 = fsub double %l19, %acc18
+  %acc20 = fsub double %l20, %acc19
+  %acc21 = fsub double %l21, %acc20
+  %acc22 = fsub double %l22, %acc21
+  %acc23 = fsub double %l23, %acc22
+  %acc24 = fsub double %l24, %acc23
+  %acc25 = fsub double %l25, %acc24
+  %acc26 = fsub double %l26, %acc25
+  %acc27 = fsub double %l27, %acc26
+  %acc28 = fsub double %l28, %acc27
+  %acc29 = fsub double %l29, %acc28
+  %acc30 = fsub double %l30, %acc29
+  %acc31 = fsub double %l31, %acc30
+  store volatile double %acc0, double *%ptr
+  store volatile double %acc1, double *%ptr
+  store volatile double %acc2, double *%ptr
+  store volatile double %acc3, double *%ptr
+  store volatile double %acc4, double *%ptr
+  store volatile double %acc5, double *%ptr
+  store volatile double %acc6, double *%ptr
+  store volatile double %acc7, double *%ptr
+  store volatile double %acc16, double *%ptr
+  store volatile double %acc17, double *%ptr
+  store volatile double %acc18, double *%ptr
+  store volatile double %acc19, double *%ptr
+  store volatile double %acc20, double *%ptr
+  store volatile double %acc21, double *%ptr
+  store volatile double %acc22, double *%ptr
+  store volatile double %acc23, double *%ptr
+  store volatile double %acc24, double *%ptr
+  store volatile double %acc25, double *%ptr
+  store volatile double %acc26, double *%ptr
+  store volatile double %acc27, double *%ptr
+  store volatile double %acc28, double *%ptr
+  store volatile double %acc29, double *%ptr
+  store volatile double %acc30, double *%ptr
+  store volatile double %acc31, double *%ptr
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/htm-intrinsics.ll b/test/CodeGen/SystemZ/htm-intrinsics.ll
new file mode 100644
index 000000000000..6441ef94b406
--- /dev/null
+++ b/test/CodeGen/SystemZ/htm-intrinsics.ll
@@ -0,0 +1,352 @@
+; Test transactional-execution intrinsics.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
+
+declare i32 @llvm.s390.tbegin(i8 *, i32)
+declare i32 @llvm.s390.tbegin.nofloat(i8 *, i32)
+declare void @llvm.s390.tbeginc(i8 *, i32)
+declare i32 @llvm.s390.tend()
+declare void @llvm.s390.tabort(i64)
+declare void @llvm.s390.ntstg(i64, i64 *)
+declare i32 @llvm.s390.etnd()
+declare void @llvm.s390.ppa.txassist(i32)
+
+; TBEGIN.
+define void @test_tbegin() {
+; CHECK-LABEL: test_tbegin:
+; CHECK-NOT: stmg
+; CHECK: std %f8,
+; CHECK: std %f9,
+; CHECK: std %f10,
+; CHECK: std %f11,
+; CHECK: std %f12,
+; CHECK: std %f13,
+; CHECK: std %f14,
+; CHECK: std %f15,
+; CHECK: tbegin 0, 65292
+; CHECK: ld %f8,
+; CHECK: ld %f9,
+; CHECK: ld %f10,
+; CHECK: ld %f11,
+; CHECK: ld %f12,
+; CHECK: ld %f13,
+; CHECK: ld %f14,
+; CHECK: ld %f15,
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin(i8 *null, i32 65292)
+  ret void
+}
+
+; TBEGIN (nofloat).
+define void @test_tbegin_nofloat1() {
+; CHECK-LABEL: test_tbegin_nofloat1:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  ret void
+}
+
+; TBEGIN (nofloat) with integer CC return value.
+define i32 @test_tbegin_nofloat2() {
+; CHECK-LABEL: test_tbegin_nofloat2:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  ret i32 %res
+}
+
+; TBEGIN (nofloat) with implicit CC check.
+define void @test_tbegin_nofloat3(i32 *%ptr) {
+; CHECK-LABEL: test_tbegin_nofloat3:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: jnh  {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret void
+}
+
+; TBEGIN (nofloat) with dual CC use.
+define i32 @test_tbegin_nofloat4(i32 %pad, i32 *%ptr) {
+; CHECK-LABEL: test_tbegin_nofloat4:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: cijlh %r2, 2,  {{\.L*}}
+; CHECK: mvhi 0(%r3), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret i32 %res
+}
+
+; TBEGIN (nofloat) with register.
+define void @test_tbegin_nofloat5(i8 *%ptr) {
+; CHECK-LABEL: test_tbegin_nofloat5:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0(%r2), 65292
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *%ptr, i32 65292)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0x0f00.
+define void @test_tbegin_nofloat6() {
+; CHECK-LABEL: test_tbegin_nofloat6:
+; CHECK: stmg %r6, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 3840
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 3840)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xf100.
+define void @test_tbegin_nofloat7() {
+; CHECK-LABEL: test_tbegin_nofloat7:
+; CHECK: stmg %r8, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 61696
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 61696)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xfe00 -- stack pointer added automatically.
+define void @test_tbegin_nofloat8() {
+; CHECK-LABEL: test_tbegin_nofloat8:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65280
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65024)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xfb00 -- no frame pointer needed.
+define void @test_tbegin_nofloat9() {
+; CHECK-LABEL: test_tbegin_nofloat9:
+; CHECK: stmg %r10, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 64256
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xfb00 -- frame pointer added automatically.
+define void @test_tbegin_nofloat10(i64 %n) {
+; CHECK-LABEL: test_tbegin_nofloat10:
+; CHECK: stmg %r11, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65280
+; CHECK: br %r14
+  %buf = alloca i8, i64 %n
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
+  ret void
+}
+
+; TBEGINC.
+define void @test_tbeginc() {
+; CHECK-LABEL: test_tbeginc:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbeginc 0, 65288
+; CHECK: br %r14
+  call void @llvm.s390.tbeginc(i8 *null, i32 65288)
+  ret void
+}
+
+; TEND with integer CC return value.
+define i32 @test_tend1() {
+; CHECK-LABEL: test_tend1:
+; CHECK: tend
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tend()
+  ret i32 %res
+}
+
+; TEND with implicit CC check.
+define void @test_tend3(i32 *%ptr) {
+; CHECK-LABEL: test_tend3:
+; CHECK: tend
+; CHECK: je  {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tend()
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret void
+}
+
+; TEND with dual CC use.
+define i32 @test_tend2(i32 %pad, i32 *%ptr) {
+; CHECK-LABEL: test_tend2:
+; CHECK: tend
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: cijlh %r2, 2,  {{\.L*}}
+; CHECK: mvhi 0(%r3), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tend()
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret i32 %res
+}
+
+; TABORT with register only.
+define void @test_tabort1(i64 %val) {
+; CHECK-LABEL: test_tabort1:
+; CHECK: tabort 0(%r2)
+; CHECK: br %r14
+  call void @llvm.s390.tabort(i64 %val)
+  ret void
+}
+
+; TABORT with immediate only.
+define void @test_tabort2(i64 %val) {
+; CHECK-LABEL: test_tabort2:
+; CHECK: tabort 1234
+; CHECK: br %r14
+  call void @llvm.s390.tabort(i64 1234)
+  ret void
+}
+
+; TABORT with register + immediate.
+define void @test_tabort3(i64 %val) {
+; CHECK-LABEL: test_tabort3:
+; CHECK: tabort 1234(%r2)
+; CHECK: br %r14
+  %sum = add i64 %val, 1234
+  call void @llvm.s390.tabort(i64 %sum)
+  ret void
+}
+
+; TABORT with out-of-range immediate.
+define void @test_tabort4(i64 %val) {
+; CHECK-LABEL: test_tabort4:
+; CHECK: tabort 0({{%r[1-5]}})
+; CHECK: br %r14
+  call void @llvm.s390.tabort(i64 4096)
+  ret void
+}
+
+; NTSTG with base pointer only.
+define void @test_ntstg1(i64 *%ptr, i64 %val) {
+; CHECK-LABEL: test_ntstg1:
+; CHECK: ntstg %r3, 0(%r2)
+; CHECK: br %r14
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with base and index.
+; Check that VSTL doesn't allow an index.
+define void @test_ntstg2(i64 *%base, i64 %index, i64 %val) {
+; CHECK-LABEL: test_ntstg2:
+; CHECK: sllg [[REG:%r[1-5]]], %r3, 3
+; CHECK: ntstg %r4, 0([[REG]],%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 %index
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with the highest in-range displacement.
+define void @test_ntstg3(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg3:
+; CHECK: ntstg %r3, 524280(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 65535
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with an out-of-range positive displacement.
+define void @test_ntstg4(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg4:
+; CHECK: ntstg %r3, 0({{%r[1-5]}})
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 65536
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with the lowest in-range displacement.
+define void @test_ntstg5(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg5:
+; CHECK: ntstg %r3, -524288(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 -65536
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with an out-of-range negative displacement.
+define void @test_ntstg6(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg6:
+; CHECK: ntstg %r3, 0({{%r[1-5]}})
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 -65537
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; ETND.
+define i32 @test_etnd() {
+; CHECK-LABEL: test_etnd:
+; CHECK: etnd %r2
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.etnd()
+  ret i32 %res
+}
+
+; PPA (Transaction-Abort Assist)
+define void @test_ppa_txassist(i32 %val) {
+; CHECK-LABEL: test_ppa_txassist:
+; CHECK: ppa %r2, 0, 1
+; CHECK: br %r14
+  call void @llvm.s390.ppa.txassist(i32 %val)
+  ret void
+}
+
diff --git a/test/CodeGen/SystemZ/insert-01.ll b/test/CodeGen/SystemZ/insert-01.ll
index 0b54e85dc4ed..eb39552f1a2e 100644
--- a/test/CodeGen/SystemZ/insert-01.ll
+++ b/test/CodeGen/SystemZ/insert-01.ll
@@ -9,7 +9,7 @@ define i32 @f1(i32 %orig, i8 *%ptr) {
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i32
   %ptr1 = and i32 %orig, -256
   %or = or i32 %ptr1, %ptr2
@@ -22,7 +22,7 @@ define i32 @f2(i32 %orig, i8 *%ptr) {
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i32
   %ptr1 = and i32 %orig, -256
   %or = or i32 %ptr2, %ptr1
@@ -36,7 +36,7 @@ define i32 @f3(i32 %orig, i8 *%ptr) {
 ; CHECK: nill %r2, 65024
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i32
   %ptr1 = and i32 %orig, -512
   %or = or i32 %ptr1, %ptr2
@@ -49,7 +49,7 @@ define i32 @f4(i32 %orig, i8 *%ptr) {
 ; CHECK: nill %r2, 65024
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i32
   %ptr1 = and i32 %orig, -512
   %or = or i32 %ptr2, %ptr1
@@ -62,7 +62,7 @@ define i32 @f5(i32 %orig, i8 *%ptr) {
 ; CHECK: sll %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i32
   %ptr1 = shl i32 %orig, 8
   %or = or i32 %ptr1, %ptr2
@@ -75,7 +75,7 @@ define i32 @f6(i32 %orig, i8 *%ptr) {
 ; CHECK: sll %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i32
   %ptr1 = shl i32 %orig, 8
   %or = or i32 %ptr2, %ptr1
@@ -88,7 +88,7 @@ define i32 @f7(i32 %orig, i8 *%ptr) {
 ; CHECK: lhi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i32
   %or = or i32 %ptr2, 256
   ret i32 %or
@@ -100,7 +100,7 @@ define i32 @f8(i32 %orig, i8 *%ptr) {
 ; CHECK: lhi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i32
   %or = or i32 256, %ptr2
   ret i32 %or
@@ -111,8 +111,8 @@ define i32 @f9(i32 %orig, i8 *%src) {
 ; CHECK-LABEL: f9:
 ; CHECK: ic %r2, 4095(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4095
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 4095
+  %val = load i8 , i8 *%ptr
   %src2 = zext i8 %val to i32
   %src1 = and i32 %orig, -256
   %or = or i32 %src2, %src1
@@ -124,8 +124,8 @@ define i32 @f10(i32 %orig, i8 *%src) {
 ; CHECK-LABEL: f10:
 ; CHECK: icy %r2, 4096(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4096
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 4096
+  %val = load i8 , i8 *%ptr
   %src2 = zext i8 %val to i32
   %src1 = and i32 %orig, -256
   %or = or i32 %src2, %src1
@@ -137,8 +137,8 @@ define i32 @f11(i32 %orig, i8 *%src) {
 ; CHECK-LABEL: f11:
 ; CHECK: icy %r2, 524287(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524287
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524287
+  %val = load i8 , i8 *%ptr
   %src2 = zext i8 %val to i32
   %src1 = and i32 %orig, -256
   %or = or i32 %src2, %src1
@@ -152,8 +152,8 @@ define i32 @f12(i32 %orig, i8 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524288
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524288
+  %val = load i8 , i8 *%ptr
   %src2 = zext i8 %val to i32
   %src1 = and i32 %orig, -256
   %or = or i32 %src2, %src1
@@ -165,8 +165,8 @@ define i32 @f13(i32 %orig, i8 *%src) {
 ; CHECK-LABEL: f13:
 ; CHECK: icy %r2, -1(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -1
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -1
+  %val = load i8 , i8 *%ptr
   %src2 = zext i8 %val to i32
   %src1 = and i32 %orig, -256
   %or = or i32 %src2, %src1
@@ -178,8 +178,8 @@ define i32 @f14(i32 %orig, i8 *%src) {
 ; CHECK-LABEL: f14:
 ; CHECK: icy %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524288
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524288
+  %val = load i8 , i8 *%ptr
   %src2 = zext i8 %val to i32
   %src1 = and i32 %orig, -256
   %or = or i32 %src2, %src1
@@ -193,8 +193,8 @@ define i32 @f15(i32 %orig, i8 *%src) {
 ; CHECK: agfi %r3, -524289
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524289
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524289
+  %val = load i8 , i8 *%ptr
   %src2 = zext i8 %val to i32
   %src1 = and i32 %orig, -256
   %or = or i32 %src2, %src1
@@ -206,9 +206,9 @@ define i32 @f16(i32 %orig, i8 *%src, i64 %index) {
 ; CHECK-LABEL: f16:
 ; CHECK: ic %r2, 4095({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
-  %ptr1 = getelementptr i8 *%src, i64 %index
-  %ptr2 = getelementptr i8 *%ptr1, i64 4095
-  %val = load i8 *%ptr2
+  %ptr1 = getelementptr i8, i8 *%src, i64 %index
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 4095
+  %val = load i8 , i8 *%ptr2
   %src2 = zext i8 %val to i32
   %src1 = and i32 %orig, -256
   %or = or i32 %src2, %src1
@@ -220,9 +220,9 @@ define i32 @f17(i32 %orig, i8 *%src, i64 %index) {
 ; CHECK-LABEL: f17:
 ; CHECK: icy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
-  %ptr1 = getelementptr i8 *%src, i64 %index
-  %ptr2 = getelementptr i8 *%ptr1, i64 4096
-  %val = load i8 *%ptr2
+  %ptr1 = getelementptr i8, i8 *%src, i64 %index
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 4096
+  %val = load i8 , i8 *%ptr2
   %src2 = zext i8 %val to i32
   %src1 = and i32 %orig, -256
   %or = or i32 %src2, %src1
diff --git a/test/CodeGen/SystemZ/insert-02.ll b/test/CodeGen/SystemZ/insert-02.ll
index 7a85b0bee4d8..8ecfd1f16efe 100644
--- a/test/CodeGen/SystemZ/insert-02.ll
+++ b/test/CodeGen/SystemZ/insert-02.ll
@@ -9,7 +9,7 @@ define i64 @f1(i64 %orig, i8 *%ptr) {
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i64
   %ptr1 = and i64 %orig, -256
   %or = or i64 %ptr1, %ptr2
@@ -22,7 +22,7 @@ define i64 @f2(i64 %orig, i8 *%ptr) {
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i64
   %ptr1 = and i64 %orig, -256
   %or = or i64 %ptr2, %ptr1
@@ -36,7 +36,7 @@ define i64 @f3(i64 %orig, i8 *%ptr) {
 ; CHECK: nill %r2, 65024
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i64
   %ptr1 = and i64 %orig, -512
   %or = or i64 %ptr1, %ptr2
@@ -49,7 +49,7 @@ define i64 @f4(i64 %orig, i8 *%ptr) {
 ; CHECK: nill %r2, 65024
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i64
   %ptr1 = and i64 %orig, -512
   %or = or i64 %ptr2, %ptr1
@@ -62,7 +62,7 @@ define i64 @f5(i64 %orig, i8 *%ptr) {
 ; CHECK: sllg %r2, %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i64
   %ptr1 = shl i64 %orig, 8
   %or = or i64 %ptr1, %ptr2
@@ -75,7 +75,7 @@ define i64 @f6(i64 %orig, i8 *%ptr) {
 ; CHECK: sllg %r2, %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i64
   %ptr1 = shl i64 %orig, 8
   %or = or i64 %ptr2, %ptr1
@@ -88,7 +88,7 @@ define i64 @f7(i64 %orig, i8 *%ptr) {
 ; CHECK: lghi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i64
   %or = or i64 %ptr2, 256
   ret i64 %or
@@ -100,7 +100,7 @@ define i64 @f8(i64 %orig, i8 *%ptr) {
 ; CHECK: lghi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ptr2 = zext i8 %val to i64
   %or = or i64 256, %ptr2
   ret i64 %or
@@ -111,8 +111,8 @@ define i64 @f9(i64 %orig, i8 *%src) {
 ; CHECK-LABEL: f9:
 ; CHECK: ic %r2, 4095(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4095
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 4095
+  %val = load i8 , i8 *%ptr
   %src2 = zext i8 %val to i64
   %src1 = and i64 %orig, -256
   %or = or i64 %src2, %src1
@@ -124,8 +124,8 @@ define i64 @f10(i64 %orig, i8 *%src) {
 ; CHECK-LABEL: f10:
 ; CHECK: icy %r2, 4096(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4096
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 4096
+  %val = load i8 , i8 *%ptr
   %src2 = zext i8 %val to i64
   %src1 = and i64 %orig, -256
   %or = or i64 %src2, %src1
@@ -137,8 +137,8 @@ define i64 @f11(i64 %orig, i8 *%src) {
 ; CHECK-LABEL: f11:
 ; CHECK: icy %r2, 524287(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524287
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524287
+  %val = load i8 , i8 *%ptr
   %src2 = zext i8 %val to i64
   %src1 = and i64 %orig, -256
   %or = or i64 %src2, %src1
@@ -152,8 +152,8 @@ define i64 @f12(i64 %orig, i8 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524288
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524288
+  %val = load i8 , i8 *%ptr
   %src2 = zext i8 %val to i64
   %src1 = and i64 %orig, -256
   %or = or i64 %src2, %src1
@@ -165,8 +165,8 @@ define i64 @f13(i64 %orig, i8 *%src) {
 ; CHECK-LABEL: f13:
 ; CHECK: icy %r2, -1(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -1
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -1
+  %val = load i8 , i8 *%ptr
   %src2 = zext i8 %val to i64
   %src1 = and i64 %orig, -256
   %or = or i64 %src2, %src1
@@ -178,8 +178,8 @@ define i64 @f14(i64 %orig, i8 *%src) {
 ; CHECK-LABEL: f14:
 ; CHECK: icy %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524288
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524288
+  %val = load i8 , i8 *%ptr
   %src2 = zext i8 %val to i64
   %src1 = and i64 %orig, -256
   %or = or i64 %src2, %src1
@@ -193,8 +193,8 @@ define i64 @f15(i64 %orig, i8 *%src) {
 ; CHECK: agfi %r3, -524289
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524289
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524289
+  %val = load i8 , i8 *%ptr
   %src2 = zext i8 %val to i64
   %src1 = and i64 %orig, -256
   %or = or i64 %src2, %src1
@@ -206,9 +206,9 @@ define i64 @f16(i64 %orig, i8 *%src, i64 %index) {
 ; CHECK-LABEL: f16:
 ; CHECK: ic %r2, 4095({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
-  %ptr1 = getelementptr i8 *%src, i64 %index
-  %ptr2 = getelementptr i8 *%ptr1, i64 4095
-  %val = load i8 *%ptr2
+  %ptr1 = getelementptr i8, i8 *%src, i64 %index
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 4095
+  %val = load i8 , i8 *%ptr2
   %src2 = zext i8 %val to i64
   %src1 = and i64 %orig, -256
   %or = or i64 %src2, %src1
@@ -220,9 +220,9 @@ define i64 @f17(i64 %orig, i8 *%src, i64 %index) {
 ; CHECK-LABEL: f17:
 ; CHECK: icy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
-  %ptr1 = getelementptr i8 *%src, i64 %index
-  %ptr2 = getelementptr i8 *%ptr1, i64 4096
-  %val = load i8 *%ptr2
+  %ptr1 = getelementptr i8, i8 *%src, i64 %index
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 4096
+  %val = load i8 , i8 *%ptr2
   %src2 = zext i8 %val to i64
   %src1 = and i64 %orig, -256
   %or = or i64 %src2, %src1
diff --git a/test/CodeGen/SystemZ/insert-06.ll b/test/CodeGen/SystemZ/insert-06.ll
index 81a9c8770708..3243d9f4cb0c 100644
--- a/test/CodeGen/SystemZ/insert-06.ll
+++ b/test/CodeGen/SystemZ/insert-06.ll
@@ -85,7 +85,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %low = zext i32 %b to i64
   %high = and i64 %a, -4294967296
   %res = or i64 %high, %low
@@ -98,7 +98,7 @@ define i64 @f8(i64 %a, i8 *%src) {
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lb %r2, 0(%r3)
 ; CHECK: br %r14
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   %b = sext i8 %byte to i32
   %low = zext i32 %b to i64
   %high = and i64 %a, -4294967296
@@ -185,7 +185,7 @@ define i64 @f15(i64 %a, i8 *%src) {
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lb %r2, 0(%r3)
 ; CHECK: br %r14
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   %b = sext i8 %byte to i64
   %low = and i64 %b, 4294967295
   %high = and i64 %a, -4294967296
diff --git a/test/CodeGen/SystemZ/int-add-01.ll b/test/CodeGen/SystemZ/int-add-01.ll
index 4114686e41e8..f7a3a264913a 100644
--- a/test/CodeGen/SystemZ/int-add-01.ll
+++ b/test/CodeGen/SystemZ/int-add-01.ll
@@ -8,7 +8,7 @@ define i32 @f1(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f1:
 ; CHECK: ah %r2, 0(%r3)
 ; CHECK: br %r14
-  %half = load i16 *%src
+  %half = load i16 , i16 *%src
   %rhs = sext i16 %half to i32
   %res = add i32 %lhs, %rhs
   ret i32 %res
@@ -19,8 +19,8 @@ define i32 @f2(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: ah %r2, 4094(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 2047
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 2047
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = add i32 %lhs, %rhs
   ret i32 %res
@@ -31,8 +31,8 @@ define i32 @f3(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: ahy %r2, 4096(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 2048
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 2048
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = add i32 %lhs, %rhs
   ret i32 %res
@@ -43,8 +43,8 @@ define i32 @f4(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: ahy %r2, 524286(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262143
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262143
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = add i32 %lhs, %rhs
   ret i32 %res
@@ -57,8 +57,8 @@ define i32 @f5(i32 %lhs, i16 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: ah %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262144
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = add i32 %lhs, %rhs
   ret i32 %res
@@ -69,8 +69,8 @@ define i32 @f6(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: ahy %r2, -2(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -1
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -1
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = add i32 %lhs, %rhs
   ret i32 %res
@@ -81,8 +81,8 @@ define i32 @f7(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: ahy %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262144
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = add i32 %lhs, %rhs
   ret i32 %res
@@ -95,8 +95,8 @@ define i32 @f8(i32 %lhs, i16 *%src) {
 ; CHECK: agfi %r3, -524290
 ; CHECK: ah %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262145
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262145
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = add i32 %lhs, %rhs
   ret i32 %res
@@ -110,7 +110,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4094
   %ptr = inttoptr i64 %add2 to i16 *
-  %half = load i16 *%ptr
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = add i32 %lhs, %rhs
   ret i32 %res
@@ -124,7 +124,7 @@ define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i16 *
-  %half = load i16 *%ptr
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = add i32 %lhs, %rhs
   ret i32 %res
diff --git a/test/CodeGen/SystemZ/int-add-02.ll b/test/CodeGen/SystemZ/int-add-02.ll
index 4386b5a4d496..01e77de31b5f 100644
--- a/test/CodeGen/SystemZ/int-add-02.ll
+++ b/test/CodeGen/SystemZ/int-add-02.ll
@@ -19,7 +19,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: a %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %add = add i32 %a, %b
   ret i32 %add
 }
@@ -29,8 +29,8 @@ define i32 @f3(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: a %r2, 4092(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1023
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 1023
+  %b = load i32 , i32 *%ptr
   %add = add i32 %a, %b
   ret i32 %add
 }
@@ -40,8 +40,8 @@ define i32 @f4(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: ay %r2, 4096(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1024
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 1024
+  %b = load i32 , i32 *%ptr
   %add = add i32 %a, %b
   ret i32 %add
 }
@@ -51,8 +51,8 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: ay %r2, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %b = load i32 , i32 *%ptr
   %add = add i32 %a, %b
   ret i32 %add
 }
@@ -64,8 +64,8 @@ define i32 @f6(i32 %a, i32 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: a %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %b = load i32 , i32 *%ptr
   %add = add i32 %a, %b
   ret i32 %add
 }
@@ -75,8 +75,8 @@ define i32 @f7(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: ay %r2, -4(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %b = load i32 , i32 *%ptr
   %add = add i32 %a, %b
   ret i32 %add
 }
@@ -86,8 +86,8 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f8:
 ; CHECK: ay %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %b = load i32 , i32 *%ptr
   %add = add i32 %a, %b
   ret i32 %add
 }
@@ -99,8 +99,8 @@ define i32 @f9(i32 %a, i32 *%src) {
 ; CHECK: agfi %r3, -524292
 ; CHECK: a %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %b = load i32 , i32 *%ptr
   %add = add i32 %a, %b
   ret i32 %add
 }
@@ -113,7 +113,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4092
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %add = add i32 %a, %b
   ret i32 %add
 }
@@ -126,7 +126,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %add = add i32 %a, %b
   ret i32 %add
 }
@@ -137,26 +137,26 @@ define i32 @f12(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: a %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-  %ptr9 = getelementptr i32 *%ptr0, i64 18
-
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
-  %val9 = load i32 *%ptr9
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32, i32 *%ptr0, i64 18
+
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
+  %val9 = load i32 , i32 *%ptr9
 
   %ret = call i32 @foo()
 
diff --git a/test/CodeGen/SystemZ/int-add-03.ll b/test/CodeGen/SystemZ/int-add-03.ll
index 56000a80cd9b..92e3c1656d7f 100644
--- a/test/CodeGen/SystemZ/int-add-03.ll
+++ b/test/CodeGen/SystemZ/int-add-03.ll
@@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: agf %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %bext = sext i32 %b to i64
   %add = add i64 %a, %bext
   ret i64 %add
@@ -30,8 +30,8 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: agf %r2, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %add = add i64 %a, %bext
   ret i64 %add
@@ -44,8 +44,8 @@ define i64 @f4(i64 %a, i32 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: agf %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %add = add i64 %a, %bext
   ret i64 %add
@@ -56,8 +56,8 @@ define i64 @f5(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: agf %r2, -4(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %add = add i64 %a, %bext
   ret i64 %add
@@ -68,8 +68,8 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: agf %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %add = add i64 %a, %bext
   ret i64 %add
@@ -82,8 +82,8 @@ define i64 @f7(i64 %a, i32 *%src) {
 ; CHECK: agfi %r3, -524292
 ; CHECK: agf %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %add = add i64 %a, %bext
   ret i64 %add
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524284
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %add = add i64 %a, %bext
   ret i64 %add
@@ -109,26 +109,26 @@ define i64 @f9(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: agf %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-  %ptr9 = getelementptr i32 *%ptr0, i64 18
-
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
-  %val9 = load i32 *%ptr9
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32, i32 *%ptr0, i64 18
+
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
+  %val9 = load i32 , i32 *%ptr9
 
   %frob0 = add i32 %val0, 100
   %frob1 = add i32 %val1, 100
diff --git a/test/CodeGen/SystemZ/int-add-04.ll b/test/CodeGen/SystemZ/int-add-04.ll
index 675e36babfa7..6828b615e238 100644
--- a/test/CodeGen/SystemZ/int-add-04.ll
+++ b/test/CodeGen/SystemZ/int-add-04.ll
@@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: algf %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %bext = zext i32 %b to i64
   %add = add i64 %a, %bext
   ret i64 %add
@@ -30,8 +30,8 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: algf %r2, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i64
   %add = add i64 %a, %bext
   ret i64 %add
@@ -44,8 +44,8 @@ define i64 @f4(i64 %a, i32 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: algf %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i64
   %add = add i64 %a, %bext
   ret i64 %add
@@ -56,8 +56,8 @@ define i64 @f5(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: algf %r2, -4(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i64
   %add = add i64 %a, %bext
   ret i64 %add
@@ -68,8 +68,8 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: algf %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i64
   %add = add i64 %a, %bext
   ret i64 %add
@@ -82,8 +82,8 @@ define i64 @f7(i64 %a, i32 *%src) {
 ; CHECK: agfi %r3, -524292
 ; CHECK: algf %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i64
   %add = add i64 %a, %bext
   ret i64 %add
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524284
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i64
   %add = add i64 %a, %bext
   ret i64 %add
@@ -109,26 +109,26 @@ define i64 @f9(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: algf %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-  %ptr9 = getelementptr i32 *%ptr0, i64 18
-
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
-  %val9 = load i32 *%ptr9
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32, i32 *%ptr0, i64 18
+
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
+  %val9 = load i32 , i32 *%ptr9
 
   %frob0 = add i32 %val0, 100
   %frob1 = add i32 %val1, 100
diff --git a/test/CodeGen/SystemZ/int-add-05.ll b/test/CodeGen/SystemZ/int-add-05.ll
index a05fdd9059c1..f28e305dc407 100644
--- a/test/CodeGen/SystemZ/int-add-05.ll
+++ b/test/CodeGen/SystemZ/int-add-05.ll
@@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: ag %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i64 *%src
+  %b = load i64 , i64 *%src
   %add = add i64 %a, %b
   ret i64 %add
 }
@@ -29,8 +29,8 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: ag %r2, 524280(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65535
+  %b = load i64 , i64 *%ptr
   %add = add i64 %a, %b
   ret i64 %add
 }
@@ -42,8 +42,8 @@ define i64 @f4(i64 %a, i64 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: ag %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65536
+  %b = load i64 , i64 *%ptr
   %add = add i64 %a, %b
   ret i64 %add
 }
@@ -53,8 +53,8 @@ define i64 @f5(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: ag %r2, -8(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -1
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -1
+  %b = load i64 , i64 *%ptr
   %add = add i64 %a, %b
   ret i64 %add
 }
@@ -64,8 +64,8 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: ag %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
+  %b = load i64 , i64 *%ptr
   %add = add i64 %a, %b
   ret i64 %add
 }
@@ -77,8 +77,8 @@ define i64 @f7(i64 %a, i64 *%src) {
 ; CHECK: agfi %r3, -524296
 ; CHECK: ag %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
+  %b = load i64 , i64 *%ptr
   %add = add i64 %a, %b
   ret i64 %add
 }
@@ -91,7 +91,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524280
   %ptr = inttoptr i64 %add2 to i64 *
-  %b = load i64 *%ptr
+  %b = load i64 , i64 *%ptr
   %add = add i64 %a, %b
   ret i64 %add
 }
@@ -102,26 +102,26 @@ define i64 @f9(i64 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: ag %r2, 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i64 *%ptr0, i64 2
-  %ptr2 = getelementptr i64 *%ptr0, i64 4
-  %ptr3 = getelementptr i64 *%ptr0, i64 6
-  %ptr4 = getelementptr i64 *%ptr0, i64 8
-  %ptr5 = getelementptr i64 *%ptr0, i64 10
-  %ptr6 = getelementptr i64 *%ptr0, i64 12
-  %ptr7 = getelementptr i64 *%ptr0, i64 14
-  %ptr8 = getelementptr i64 *%ptr0, i64 16
-  %ptr9 = getelementptr i64 *%ptr0, i64 18
+  %ptr1 = getelementptr i64, i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64, i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64, i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64, i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64, i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64, i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64, i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64, i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64, i64 *%ptr0, i64 18
 
-  %val0 = load i64 *%ptr0
-  %val1 = load i64 *%ptr1
-  %val2 = load i64 *%ptr2
-  %val3 = load i64 *%ptr3
-  %val4 = load i64 *%ptr4
-  %val5 = load i64 *%ptr5
-  %val6 = load i64 *%ptr6
-  %val7 = load i64 *%ptr7
-  %val8 = load i64 *%ptr8
-  %val9 = load i64 *%ptr9
+  %val0 = load i64 , i64 *%ptr0
+  %val1 = load i64 , i64 *%ptr1
+  %val2 = load i64 , i64 *%ptr2
+  %val3 = load i64 , i64 *%ptr3
+  %val4 = load i64 , i64 *%ptr4
+  %val5 = load i64 , i64 *%ptr5
+  %val6 = load i64 , i64 *%ptr6
+  %val7 = load i64 , i64 *%ptr7
+  %val8 = load i64 , i64 *%ptr8
+  %val9 = load i64 , i64 *%ptr9
 
   %ret = call i64 @foo()
 
diff --git a/test/CodeGen/SystemZ/int-add-08.ll b/test/CodeGen/SystemZ/int-add-08.ll
index bcef914ed872..75b85d0888a2 100644
--- a/test/CodeGen/SystemZ/int-add-08.ll
+++ b/test/CodeGen/SystemZ/int-add-08.ll
@@ -11,7 +11,7 @@ define void @f1(i128 *%ptr) {
 ; CHECK: algr
 ; CHECK: alcgr
 ; CHECK: br %r14
-  %value = load i128 *%ptr
+  %value = load i128 , i128 *%ptr
   %add = add i128 %value, %value
   store i128 %add, i128 *%ptr
   ret void
@@ -25,8 +25,8 @@ define void @f2(i128 *%aptr, i64 %addr) {
 ; CHECK: alcg {{%r[0-5]}}, 0(%r3)
 ; CHECK: br %r14
   %bptr = inttoptr i64 %addr to i128 *
-  %a = load volatile i128 *%aptr
-  %b = load i128 *%bptr
+  %a = load volatile i128 , i128 *%aptr
+  %b = load i128 , i128 *%bptr
   %add = add i128 %a, %b
   store i128 %add, i128 *%aptr
   ret void
@@ -40,8 +40,8 @@ define void @f3(i128 *%aptr, i64 %base) {
 ; CHECK: br %r14
   %addr = add i64 %base, 524272
   %bptr = inttoptr i64 %addr to i128 *
-  %a = load volatile i128 *%aptr
-  %b = load i128 *%bptr
+  %a = load volatile i128 , i128 *%aptr
+  %b = load i128 , i128 *%bptr
   %add = add i128 %a, %b
   store i128 %add, i128 *%aptr
   ret void
@@ -57,8 +57,8 @@ define void @f4(i128 *%aptr, i64 %base) {
 ; CHECK: br %r14
   %addr = add i64 %base, 524280
   %bptr = inttoptr i64 %addr to i128 *
-  %a = load volatile i128 *%aptr
-  %b = load i128 *%bptr
+  %a = load volatile i128 , i128 *%aptr
+  %b = load i128 , i128 *%bptr
   %add = add i128 %a, %b
   store i128 %add, i128 *%aptr
   ret void
@@ -74,8 +74,8 @@ define void @f5(i128 *%aptr, i64 %base) {
 ; CHECK: br %r14
   %addr = add i64 %base, 524288
   %bptr = inttoptr i64 %addr to i128 *
-  %a = load volatile i128 *%aptr
-  %b = load i128 *%bptr
+  %a = load volatile i128 , i128 *%aptr
+  %b = load i128 , i128 *%bptr
   %add = add i128 %a, %b
   store i128 %add, i128 *%aptr
   ret void
@@ -89,8 +89,8 @@ define void @f6(i128 *%aptr, i64 %base) {
 ; CHECK: br %r14
   %addr = add i64 %base, -524288
   %bptr = inttoptr i64 %addr to i128 *
-  %a = load volatile i128 *%aptr
-  %b = load i128 *%bptr
+  %a = load volatile i128 , i128 *%aptr
+  %b = load i128 , i128 *%bptr
   %add = add i128 %a, %b
   store i128 %add, i128 *%aptr
   ret void
@@ -104,8 +104,8 @@ define void @f7(i128 *%aptr, i64 %base) {
 ; CHECK: br %r14
   %addr = add i64 %base, -524296
   %bptr = inttoptr i64 %addr to i128 *
-  %a = load volatile i128 *%aptr
-  %b = load i128 *%bptr
+  %a = load volatile i128 , i128 *%aptr
+  %b = load i128 , i128 *%bptr
   %add = add i128 %a, %b
   store i128 %add, i128 *%aptr
   ret void
@@ -119,20 +119,20 @@ define void @f8(i128 *%ptr0) {
 ; CHECK: alg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
 ; CHECK: alcg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i128 *%ptr0, i128 2
-  %ptr2 = getelementptr i128 *%ptr0, i128 4
-  %ptr3 = getelementptr i128 *%ptr0, i128 6
-  %ptr4 = getelementptr i128 *%ptr0, i128 8
+  %ptr1 = getelementptr i128, i128 *%ptr0, i128 2
+  %ptr2 = getelementptr i128, i128 *%ptr0, i128 4
+  %ptr3 = getelementptr i128, i128 *%ptr0, i128 6
+  %ptr4 = getelementptr i128, i128 *%ptr0, i128 8
 
-  %val0 = load i128 *%ptr0
-  %val1 = load i128 *%ptr1
-  %val2 = load i128 *%ptr2
-  %val3 = load i128 *%ptr3
-  %val4 = load i128 *%ptr4
+  %val0 = load i128 , i128 *%ptr0
+  %val1 = load i128 , i128 *%ptr1
+  %val2 = load i128 , i128 *%ptr2
+  %val3 = load i128 , i128 *%ptr3
+  %val4 = load i128 , i128 *%ptr4
 
   %retptr = call i128 *@foo()
 
-  %ret = load i128 *%retptr
+  %ret = load i128 , i128 *%retptr
   %add0 = add i128 %ret, %val0
   %add1 = add i128 %add0, %val1
   %add2 = add i128 %add1, %val2
diff --git a/test/CodeGen/SystemZ/int-add-09.ll b/test/CodeGen/SystemZ/int-add-09.ll
index fd151a7f979a..b7bcdc8b93a8 100644
--- a/test/CodeGen/SystemZ/int-add-09.ll
+++ b/test/CodeGen/SystemZ/int-add-09.ll
@@ -9,7 +9,7 @@ define void @f1(i128 *%aptr) {
 ; CHECK: algfi {{%r[0-5]}}, 1
 ; CHECK: alcg
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 128
   %add = add i128 %xor, 1
   store i128 %add, i128 *%aptr
@@ -22,7 +22,7 @@ define void @f2(i128 *%aptr) {
 ; CHECK: algfi {{%r[0-5]}}, 4294967295
 ; CHECK: alcg
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 128
   %add = add i128 %xor, 4294967295
   store i128 %add, i128 *%aptr
@@ -35,7 +35,7 @@ define void @f3(i128 *%aptr) {
 ; CHECK: algr
 ; CHECK: alcg
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 128
   %add = add i128 %xor, 4294967296
   store i128 %add, i128 *%aptr
@@ -48,7 +48,7 @@ define void @f4(i128 *%aptr) {
 ; CHECK: algr
 ; CHECK: alcg
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 128
   %add = add i128 %xor, -1
   store i128 %add, i128 *%aptr
diff --git a/test/CodeGen/SystemZ/int-add-10.ll b/test/CodeGen/SystemZ/int-add-10.ll
index 01d0a661ed29..f55788dc8bb6 100644
--- a/test/CodeGen/SystemZ/int-add-10.ll
+++ b/test/CodeGen/SystemZ/int-add-10.ll
@@ -9,7 +9,7 @@ define void @f1(i128 *%aptr, i32 %b) {
 ; CHECK: algfr {{%r[0-5]}}, %r3
 ; CHECK: alcg
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
   %bext = zext i32 %b to i128
   %add = add i128 %xor, %bext
@@ -23,7 +23,7 @@ define void @f2(i128 *%aptr, i64 %b) {
 ; CHECK: algfr {{%r[0-5]}}, %r3
 ; CHECK: alcg
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
   %trunc = trunc i64 %b to i32
   %bext = zext i32 %trunc to i128
@@ -39,7 +39,7 @@ define void @f3(i128 *%aptr, i64 %b) {
 ; CHECK: algfr {{%r[0-5]}}, %r3
 ; CHECK: alcg
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
   %bext = zext i64 %b to i128
   %and = and i128 %bext, 4294967295
@@ -54,9 +54,9 @@ define void @f4(i128 *%aptr, i32 *%bsrc) {
 ; CHECK: algf {{%r[0-5]}}, 0(%r3)
 ; CHECK: alcg
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
-  %b = load i32 *%bsrc
+  %b = load i32 , i32 *%bsrc
   %bext = zext i32 %b to i128
   %add = add i128 %xor, %bext
   store i128 %add, i128 *%aptr
@@ -69,10 +69,10 @@ define void @f5(i128 *%aptr, i32 *%bsrc) {
 ; CHECK: algf {{%r[0-5]}}, 524284(%r3)
 ; CHECK: alcg
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
-  %ptr = getelementptr i32 *%bsrc, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%bsrc, i64 131071
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i128
   %add = add i128 %xor, %bext
   store i128 %add, i128 *%aptr
@@ -87,10 +87,10 @@ define void @f6(i128 *%aptr, i32 *%bsrc) {
 ; CHECK: algf {{%r[0-5]}}, 0(%r3)
 ; CHECK: alcg
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
-  %ptr = getelementptr i32 *%bsrc, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%bsrc, i64 131072
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i128
   %add = add i128 %xor, %bext
   store i128 %add, i128 *%aptr
@@ -103,10 +103,10 @@ define void @f7(i128 *%aptr, i32 *%bsrc) {
 ; CHECK: algf {{%r[0-5]}}, -4(%r3)
 ; CHECK: alcg
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
-  %ptr = getelementptr i32 *%bsrc, i128 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%bsrc, i128 -1
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i128
   %add = add i128 %xor, %bext
   store i128 %add, i128 *%aptr
@@ -119,10 +119,10 @@ define void @f8(i128 *%aptr, i32 *%bsrc) {
 ; CHECK: algf {{%r[0-5]}}, -524288(%r3)
 ; CHECK: alcg
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
-  %ptr = getelementptr i32 *%bsrc, i128 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%bsrc, i128 -131072
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i128
   %add = add i128 %xor, %bext
   store i128 %add, i128 *%aptr
@@ -137,10 +137,10 @@ define void @f9(i128 *%aptr, i32 *%bsrc) {
 ; CHECK: algf {{%r[0-5]}}, 0(%r3)
 ; CHECK: alcg
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
-  %ptr = getelementptr i32 *%bsrc, i128 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%bsrc, i128 -131073
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i128
   %add = add i128 %xor, %bext
   store i128 %add, i128 *%aptr
@@ -152,12 +152,12 @@ define void @f10(i128 *%aptr, i64 %src, i64 %index) {
 ; CHECK-LABEL: f10:
 ; CHECK: algf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524284
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i128
   %add = add i128 %xor, %bext
   store i128 %add, i128 *%aptr
diff --git a/test/CodeGen/SystemZ/int-add-11.ll b/test/CodeGen/SystemZ/int-add-11.ll
index 679c206094f3..b93555f5d357 100644
--- a/test/CodeGen/SystemZ/int-add-11.ll
+++ b/test/CodeGen/SystemZ/int-add-11.ll
@@ -8,7 +8,7 @@ define void @f1(i32 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: asi 0(%r2), 1
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %add = add i32 %val, 127
   store i32 %add, i32 *%ptr
   ret void
@@ -19,7 +19,7 @@ define void @f2(i32 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: asi 0(%r2), 127
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %add = add i32 %val, 127
   store i32 %add, i32 *%ptr
   ret void
@@ -32,7 +32,7 @@ define void @f3(i32 *%ptr) {
 ; CHECK-NOT: asi
 ; CHECK: st %r0, 0(%r2)
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %add = add i32 %val, 128
   store i32 %add, i32 *%ptr
   ret void
@@ -43,7 +43,7 @@ define void @f4(i32 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: asi 0(%r2), -128
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %add = add i32 %val, -128
   store i32 %add, i32 *%ptr
   ret void
@@ -55,7 +55,7 @@ define void @f5(i32 *%ptr) {
 ; CHECK-NOT: asi
 ; CHECK: st %r0, 0(%r2)
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %add = add i32 %val, -129
   store i32 %add, i32 *%ptr
   ret void
@@ -66,8 +66,8 @@ define void @f6(i32 *%base) {
 ; CHECK-LABEL: f6:
 ; CHECK: asi 524284(%r2), 1
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131071
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 131071
+  %val = load i32 , i32 *%ptr
   %add = add i32 %val, 1
   store i32 %add, i32 *%ptr
   ret void
@@ -80,8 +80,8 @@ define void @f7(i32 *%base) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: asi 0(%r2), 1
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131072
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 131072
+  %val = load i32 , i32 *%ptr
   %add = add i32 %val, 1
   store i32 %add, i32 *%ptr
   ret void
@@ -92,8 +92,8 @@ define void @f8(i32 *%base) {
 ; CHECK-LABEL: f8:
 ; CHECK: asi -524288(%r2), 1
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131072
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -131072
+  %val = load i32 , i32 *%ptr
   %add = add i32 %val, 1
   store i32 %add, i32 *%ptr
   ret void
@@ -106,8 +106,8 @@ define void @f9(i32 *%base) {
 ; CHECK: agfi %r2, -524292
 ; CHECK: asi 0(%r2), 1
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131073
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -131073
+  %val = load i32 , i32 *%ptr
   %add = add i32 %val, 1
   store i32 %add, i32 *%ptr
   ret void
@@ -122,7 +122,7 @@ define void @f10(i64 %base, i64 %index) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4
   %ptr = inttoptr i64 %add2 to i32 *
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %add = add i32 %val, 1
   store i32 %add, i32 *%ptr
   ret void
@@ -134,22 +134,22 @@ define void @f11(i32 *%ptr, i32 %sel) {
 ; CHECK: asi {{[0-9]+}}(%r15), 127
 ; CHECK: br %r14
 entry:
-  %val0 = load volatile i32 *%ptr
-  %val1 = load volatile i32 *%ptr
-  %val2 = load volatile i32 *%ptr
-  %val3 = load volatile i32 *%ptr
-  %val4 = load volatile i32 *%ptr
-  %val5 = load volatile i32 *%ptr
-  %val6 = load volatile i32 *%ptr
-  %val7 = load volatile i32 *%ptr
-  %val8 = load volatile i32 *%ptr
-  %val9 = load volatile i32 *%ptr
-  %val10 = load volatile i32 *%ptr
-  %val11 = load volatile i32 *%ptr
-  %val12 = load volatile i32 *%ptr
-  %val13 = load volatile i32 *%ptr
-  %val14 = load volatile i32 *%ptr
-  %val15 = load volatile i32 *%ptr
+  %val0 = load volatile i32 , i32 *%ptr
+  %val1 = load volatile i32 , i32 *%ptr
+  %val2 = load volatile i32 , i32 *%ptr
+  %val3 = load volatile i32 , i32 *%ptr
+  %val4 = load volatile i32 , i32 *%ptr
+  %val5 = load volatile i32 , i32 *%ptr
+  %val6 = load volatile i32 , i32 *%ptr
+  %val7 = load volatile i32 , i32 *%ptr
+  %val8 = load volatile i32 , i32 *%ptr
+  %val9 = load volatile i32 , i32 *%ptr
+  %val10 = load volatile i32 , i32 *%ptr
+  %val11 = load volatile i32 , i32 *%ptr
+  %val12 = load volatile i32 , i32 *%ptr
+  %val13 = load volatile i32 , i32 *%ptr
+  %val14 = load volatile i32 , i32 *%ptr
+  %val15 = load volatile i32 , i32 *%ptr
 
   %test = icmp ne i32 %sel, 0
   br i1 %test, label %add, label %store
@@ -217,22 +217,22 @@ define void @f12(i32 *%ptr, i32 %sel) {
 ; CHECK: asi {{[0-9]+}}(%r15), -128
 ; CHECK: br %r14
 entry:
-  %val0 = load volatile i32 *%ptr
-  %val1 = load volatile i32 *%ptr
-  %val2 = load volatile i32 *%ptr
-  %val3 = load volatile i32 *%ptr
-  %val4 = load volatile i32 *%ptr
-  %val5 = load volatile i32 *%ptr
-  %val6 = load volatile i32 *%ptr
-  %val7 = load volatile i32 *%ptr
-  %val8 = load volatile i32 *%ptr
-  %val9 = load volatile i32 *%ptr
-  %val10 = load volatile i32 *%ptr
-  %val11 = load volatile i32 *%ptr
-  %val12 = load volatile i32 *%ptr
-  %val13 = load volatile i32 *%ptr
-  %val14 = load volatile i32 *%ptr
-  %val15 = load volatile i32 *%ptr
+  %val0 = load volatile i32 , i32 *%ptr
+  %val1 = load volatile i32 , i32 *%ptr
+  %val2 = load volatile i32 , i32 *%ptr
+  %val3 = load volatile i32 , i32 *%ptr
+  %val4 = load volatile i32 , i32 *%ptr
+  %val5 = load volatile i32 , i32 *%ptr
+  %val6 = load volatile i32 , i32 *%ptr
+  %val7 = load volatile i32 , i32 *%ptr
+  %val8 = load volatile i32 , i32 *%ptr
+  %val9 = load volatile i32 , i32 *%ptr
+  %val10 = load volatile i32 , i32 *%ptr
+  %val11 = load volatile i32 , i32 *%ptr
+  %val12 = load volatile i32 , i32 *%ptr
+  %val13 = load volatile i32 , i32 *%ptr
+  %val14 = load volatile i32 , i32 *%ptr
+  %val15 = load volatile i32 , i32 *%ptr
 
   %test = icmp ne i32 %sel, 0
   br i1 %test, label %add, label %store
diff --git a/test/CodeGen/SystemZ/int-add-12.ll b/test/CodeGen/SystemZ/int-add-12.ll
index 741cce19d72c..496650f435c9 100644
--- a/test/CodeGen/SystemZ/int-add-12.ll
+++ b/test/CodeGen/SystemZ/int-add-12.ll
@@ -7,7 +7,7 @@ define void @f1(i64 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: agsi 0(%r2), 1
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %add = add i64 %val, 127
   store i64 %add, i64 *%ptr
   ret void
@@ -18,7 +18,7 @@ define void @f2(i64 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: agsi 0(%r2), 127
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %add = add i64 %val, 127
   store i64 %add, i64 *%ptr
   ret void
@@ -31,7 +31,7 @@ define void @f3(i64 *%ptr) {
 ; CHECK-NOT: agsi
 ; CHECK: stg %r0, 0(%r2)
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %add = add i64 %val, 128
   store i64 %add, i64 *%ptr
   ret void
@@ -42,7 +42,7 @@ define void @f4(i64 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: agsi 0(%r2), -128
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %add = add i64 %val, -128
   store i64 %add, i64 *%ptr
   ret void
@@ -54,7 +54,7 @@ define void @f5(i64 *%ptr) {
 ; CHECK-NOT: agsi
 ; CHECK: stg %r0, 0(%r2)
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %add = add i64 %val, -129
   store i64 %add, i64 *%ptr
   ret void
@@ -65,8 +65,8 @@ define void @f6(i64 *%base) {
 ; CHECK-LABEL: f6:
 ; CHECK: agsi 524280(%r2), 1
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 65535
-  %val = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 65535
+  %val = load i64 , i64 *%ptr
   %add = add i64 %val, 1
   store i64 %add, i64 *%ptr
   ret void
@@ -79,8 +79,8 @@ define void @f7(i64 *%base) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: agsi 0(%r2), 1
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 65536
-  %val = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 65536
+  %val = load i64 , i64 *%ptr
   %add = add i64 %val, 1
   store i64 %add, i64 *%ptr
   ret void
@@ -91,8 +91,8 @@ define void @f8(i64 *%base) {
 ; CHECK-LABEL: f8:
 ; CHECK: agsi -524288(%r2), 1
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -65536
-  %val = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 -65536
+  %val = load i64 , i64 *%ptr
   %add = add i64 %val, 1
   store i64 %add, i64 *%ptr
   ret void
@@ -105,8 +105,8 @@ define void @f9(i64 *%base) {
 ; CHECK: agfi %r2, -524296
 ; CHECK: agsi 0(%r2), 1
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -65537
-  %val = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 -65537
+  %val = load i64 , i64 *%ptr
   %add = add i64 %val, 1
   store i64 %add, i64 *%ptr
   ret void
@@ -121,7 +121,7 @@ define void @f10(i64 %base, i64 %index) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 8
   %ptr = inttoptr i64 %add2 to i64 *
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %add = add i64 %val, 1
   store i64 %add, i64 *%ptr
   ret void
@@ -133,22 +133,22 @@ define void @f11(i64 *%ptr, i32 %sel) {
 ; CHECK: agsi {{[0-9]+}}(%r15), 127
 ; CHECK: br %r14
 entry:
-  %val0 = load volatile i64 *%ptr
-  %val1 = load volatile i64 *%ptr
-  %val2 = load volatile i64 *%ptr
-  %val3 = load volatile i64 *%ptr
-  %val4 = load volatile i64 *%ptr
-  %val5 = load volatile i64 *%ptr
-  %val6 = load volatile i64 *%ptr
-  %val7 = load volatile i64 *%ptr
-  %val8 = load volatile i64 *%ptr
-  %val9 = load volatile i64 *%ptr
-  %val10 = load volatile i64 *%ptr
-  %val11 = load volatile i64 *%ptr
-  %val12 = load volatile i64 *%ptr
-  %val13 = load volatile i64 *%ptr
-  %val14 = load volatile i64 *%ptr
-  %val15 = load volatile i64 *%ptr
+  %val0 = load volatile i64 , i64 *%ptr
+  %val1 = load volatile i64 , i64 *%ptr
+  %val2 = load volatile i64 , i64 *%ptr
+  %val3 = load volatile i64 , i64 *%ptr
+  %val4 = load volatile i64 , i64 *%ptr
+  %val5 = load volatile i64 , i64 *%ptr
+  %val6 = load volatile i64 , i64 *%ptr
+  %val7 = load volatile i64 , i64 *%ptr
+  %val8 = load volatile i64 , i64 *%ptr
+  %val9 = load volatile i64 , i64 *%ptr
+  %val10 = load volatile i64 , i64 *%ptr
+  %val11 = load volatile i64 , i64 *%ptr
+  %val12 = load volatile i64 , i64 *%ptr
+  %val13 = load volatile i64 , i64 *%ptr
+  %val14 = load volatile i64 , i64 *%ptr
+  %val15 = load volatile i64 , i64 *%ptr
 
   %test = icmp ne i32 %sel, 0
   br i1 %test, label %add, label %store
@@ -216,22 +216,22 @@ define void @f12(i64 *%ptr, i32 %sel) {
 ; CHECK: agsi {{[0-9]+}}(%r15), -128
 ; CHECK: br %r14
 entry:
-  %val0 = load volatile i64 *%ptr
-  %val1 = load volatile i64 *%ptr
-  %val2 = load volatile i64 *%ptr
-  %val3 = load volatile i64 *%ptr
-  %val4 = load volatile i64 *%ptr
-  %val5 = load volatile i64 *%ptr
-  %val6 = load volatile i64 *%ptr
-  %val7 = load volatile i64 *%ptr
-  %val8 = load volatile i64 *%ptr
-  %val9 = load volatile i64 *%ptr
-  %val10 = load volatile i64 *%ptr
-  %val11 = load volatile i64 *%ptr
-  %val12 = load volatile i64 *%ptr
-  %val13 = load volatile i64 *%ptr
-  %val14 = load volatile i64 *%ptr
-  %val15 = load volatile i64 *%ptr
+  %val0 = load volatile i64 , i64 *%ptr
+  %val1 = load volatile i64 , i64 *%ptr
+  %val2 = load volatile i64 , i64 *%ptr
+  %val3 = load volatile i64 , i64 *%ptr
+  %val4 = load volatile i64 , i64 *%ptr
+  %val5 = load volatile i64 , i64 *%ptr
+  %val6 = load volatile i64 , i64 *%ptr
+  %val7 = load volatile i64 , i64 *%ptr
+  %val8 = load volatile i64 , i64 *%ptr
+  %val9 = load volatile i64 , i64 *%ptr
+  %val10 = load volatile i64 , i64 *%ptr
+  %val11 = load volatile i64 , i64 *%ptr
+  %val12 = load volatile i64 , i64 *%ptr
+  %val13 = load volatile i64 , i64 *%ptr
+  %val14 = load volatile i64 , i64 *%ptr
+  %val15 = load volatile i64 , i64 *%ptr
 
   %test = icmp ne i32 %sel, 0
   br i1 %test, label %add, label %store
diff --git a/test/CodeGen/SystemZ/int-cmp-01.ll b/test/CodeGen/SystemZ/int-cmp-01.ll
index 6653b6f706f7..97b697db3bdb 100644
--- a/test/CodeGen/SystemZ/int-cmp-01.ll
+++ b/test/CodeGen/SystemZ/int-cmp-01.ll
@@ -8,7 +8,7 @@ define void @f1(i32 %lhs, i16 *%src, i32 *%dst) {
 ; CHECK-LABEL: f1:
 ; CHECK: ch %r2, 0(%r3)
 ; CHECK: br %r14
-  %half = load i16 *%src
+  %half = load i16 , i16 *%src
   %rhs = sext i16 %half to i32
   %cond = icmp slt i32 %lhs, %rhs
   %res = select i1 %cond, i32 100, i32 200
@@ -21,8 +21,8 @@ define void @f2(i32 %lhs, i16 *%src, i32 *%dst) {
 ; CHECK-LABEL: f2:
 ; CHECK: ch %r2, 4094(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 2047
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 2047
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %cond = icmp slt i32 %lhs, %rhs
   %res = select i1 %cond, i32 100, i32 200
@@ -35,8 +35,8 @@ define void @f3(i32 %lhs, i16 *%src, i32 *%dst) {
 ; CHECK-LABEL: f3:
 ; CHECK: chy %r2, 4096(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 2048
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 2048
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %cond = icmp slt i32 %lhs, %rhs
   %res = select i1 %cond, i32 100, i32 200
@@ -49,8 +49,8 @@ define void @f4(i32 %lhs, i16 *%src, i32 *%dst) {
 ; CHECK-LABEL: f4:
 ; CHECK: chy %r2, 524286(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262143
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262143
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %cond = icmp slt i32 %lhs, %rhs
   %res = select i1 %cond, i32 100, i32 200
@@ -65,8 +65,8 @@ define void @f5(i32 %lhs, i16 *%src, i32 *%dst) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: ch %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262144
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %cond = icmp slt i32 %lhs, %rhs
   %res = select i1 %cond, i32 100, i32 200
@@ -79,8 +79,8 @@ define void @f6(i32 %lhs, i16 *%src, i32 *%dst) {
 ; CHECK-LABEL: f6:
 ; CHECK: chy %r2, -2(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -1
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -1
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %cond = icmp slt i32 %lhs, %rhs
   %res = select i1 %cond, i32 100, i32 200
@@ -93,8 +93,8 @@ define void @f7(i32 %lhs, i16 *%src, i32 *%dst) {
 ; CHECK-LABEL: f7:
 ; CHECK: chy %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262144
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %cond = icmp slt i32 %lhs, %rhs
   %res = select i1 %cond, i32 100, i32 200
@@ -109,8 +109,8 @@ define void @f8(i32 %lhs, i16 *%src, i32 *%dst) {
 ; CHECK: agfi %r3, -524290
 ; CHECK: ch %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262145
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262145
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %cond = icmp slt i32 %lhs, %rhs
   %res = select i1 %cond, i32 100, i32 200
@@ -126,7 +126,7 @@ define void @f9(i32 %lhs, i64 %base, i64 %index, i32 *%dst) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4094
   %ptr = inttoptr i64 %add2 to i16 *
-  %half = load i16 *%ptr
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %cond = icmp slt i32 %lhs, %rhs
   %res = select i1 %cond, i32 100, i32 200
@@ -142,7 +142,7 @@ define void @f10(i32 %lhs, i64 %base, i64 %index, i32 *%dst) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i16 *
-  %half = load i16 *%ptr
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %cond = icmp slt i32 %lhs, %rhs
   %res = select i1 %cond, i32 100, i32 200
@@ -157,7 +157,7 @@ define double @f11(double %a, double %b, i32 %rhs, i16 *%src) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %half = load i16 *%src
+  %half = load i16 , i16 *%src
   %lhs = sext i16 %half to i32
   %cond = icmp slt i32 %lhs, %rhs
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-02.ll b/test/CodeGen/SystemZ/int-cmp-02.ll
index 4a8a1a9ade33..d5aef0f0f977 100644
--- a/test/CodeGen/SystemZ/int-cmp-02.ll
+++ b/test/CodeGen/SystemZ/int-cmp-02.ll
@@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %i2 = load i32 *%ptr
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -35,8 +35,8 @@ define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 1023
-  %i2 = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 1023
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -49,8 +49,8 @@ define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 1024
-  %i2 = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 1024
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -63,8 +63,8 @@ define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131071
-  %i2 = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 131071
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -79,8 +79,8 @@ define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131072
-  %i2 = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 131072
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -93,8 +93,8 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -1
-  %i2 = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -1
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -107,8 +107,8 @@ define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131072
-  %i2 = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -131072
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -123,8 +123,8 @@ define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131073
-  %i2 = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -131073
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -140,7 +140,7 @@ define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4092
   %ptr = inttoptr i64 %add2 to i32 *
-  %i2 = load i32 *%ptr
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -156,7 +156,7 @@ define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i32 *
-  %i2 = load i32 *%ptr
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -189,7 +189,7 @@ define double @f13(double %a, double %b, i32 %i2, i32 *%ptr) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %i1 = load i32 *%ptr
+  %i1 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
diff --git a/test/CodeGen/SystemZ/int-cmp-03.ll b/test/CodeGen/SystemZ/int-cmp-03.ll
index aa654e086dc6..0246666f06fe 100644
--- a/test/CodeGen/SystemZ/int-cmp-03.ll
+++ b/test/CodeGen/SystemZ/int-cmp-03.ll
@@ -20,7 +20,7 @@ define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %i2 = load i32 *%ptr
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -33,8 +33,8 @@ define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 1023
-  %i2 = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 1023
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -47,8 +47,8 @@ define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 1024
-  %i2 = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 1024
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -61,8 +61,8 @@ define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131071
-  %i2 = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 131071
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -77,8 +77,8 @@ define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131072
-  %i2 = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 131072
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -91,8 +91,8 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -1
-  %i2 = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -1
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -105,8 +105,8 @@ define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131072
-  %i2 = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -131072
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -121,8 +121,8 @@ define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131073
-  %i2 = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -131073
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -138,7 +138,7 @@ define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4092
   %ptr = inttoptr i64 %add2 to i32 *
-  %i2 = load i32 *%ptr
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -154,7 +154,7 @@ define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i32 *
-  %i2 = load i32 *%ptr
+  %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -167,7 +167,7 @@ define double @f12(double %a, double %b, i32 %i2, i32 *%ptr) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %i1 = load i32 *%ptr
+  %i1 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
diff --git a/test/CodeGen/SystemZ/int-cmp-04.ll b/test/CodeGen/SystemZ/int-cmp-04.ll
index a6606f392923..90f05ea38680 100644
--- a/test/CodeGen/SystemZ/int-cmp-04.ll
+++ b/test/CodeGen/SystemZ/int-cmp-04.ll
@@ -8,7 +8,7 @@ define void @f1(i64 %lhs, i16 *%src, i64 *%dst) {
 ; CHECK-LABEL: f1:
 ; CHECK: cgh %r2, 0(%r3)
 ; CHECK: br %r14
-  %half = load i16 *%src
+  %half = load i16 , i16 *%src
   %rhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, i64 100, i64 200
@@ -21,8 +21,8 @@ define void @f2(i64 %lhs, i16 *%src, i64 *%dst) {
 ; CHECK-LABEL: f2:
 ; CHECK: cgh %r2, 524286(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262143
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262143
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, i64 100, i64 200
@@ -37,8 +37,8 @@ define void @f3(i64 %lhs, i16 *%src, i64 *%dst) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: cgh %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262144
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, i64 100, i64 200
@@ -51,8 +51,8 @@ define void @f4(i64 %lhs, i16 *%src, i64 *%dst) {
 ; CHECK-LABEL: f4:
 ; CHECK: cgh %r2, -2(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -1
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -1
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, i64 100, i64 200
@@ -65,8 +65,8 @@ define void @f5(i64 %lhs, i16 *%src, i64 *%dst) {
 ; CHECK-LABEL: f5:
 ; CHECK: cgh %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262144
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, i64 100, i64 200
@@ -81,8 +81,8 @@ define void @f6(i64 %lhs, i16 *%src, i64 *%dst) {
 ; CHECK: agfi %r3, -524290
 ; CHECK: cgh %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262145
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262145
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, i64 100, i64 200
@@ -98,7 +98,7 @@ define void @f7(i64 %lhs, i64 %base, i64 %index, i64 *%dst) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i16 *
-  %half = load i16 *%ptr
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, i64 100, i64 200
@@ -113,7 +113,7 @@ define double @f8(double %a, double %b, i64 %rhs, i16 *%src) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %half = load i16 *%src
+  %half = load i16 , i16 *%src
   %lhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-05.ll b/test/CodeGen/SystemZ/int-cmp-05.ll
index 0be43a3ef1bf..70640b607bcd 100644
--- a/test/CodeGen/SystemZ/int-cmp-05.ll
+++ b/test/CodeGen/SystemZ/int-cmp-05.ll
@@ -61,7 +61,7 @@ define double @f5(double %a, double %b, i64 %i1, i32 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %unext = load i32 *%ptr
+  %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i64 %i1, i32 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: cgf
 ; CHECK: br %r14
-  %unext = load i32 *%ptr
+  %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -87,7 +87,7 @@ define double @f7(double %a, double %b, i64 %i1, i32 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %unext = load i32 *%ptr
+  %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp eq i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -101,7 +101,7 @@ define double @f8(double %a, double %b, i64 %i1, i32 *%ptr) {
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %unext = load i32 *%ptr
+  %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp ne i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -115,8 +115,8 @@ define double @f9(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131071
-  %unext = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 131071
+  %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -132,8 +132,8 @@ define double @f10(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131072
-  %unext = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 131072
+  %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -147,8 +147,8 @@ define double @f11(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -1
-  %unext = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -1
+  %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -162,8 +162,8 @@ define double @f12(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131072
-  %unext = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -131072
+  %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -179,8 +179,8 @@ define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131073
-  %unext = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -131073
+  %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -197,7 +197,7 @@ define double @f14(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 524284
   %ptr = inttoptr i64 %add2 to i32 *
-  %unext = load i32 *%ptr
+  %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -210,26 +210,26 @@ define i64 @f15(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: cgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-  %ptr9 = getelementptr i32 *%ptr0, i64 18
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32, i32 *%ptr0, i64 18
 
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
-  %val9 = load i32 *%ptr9
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
+  %val9 = load i32 , i32 *%ptr9
 
   %frob0 = add i32 %val0, 100
   %frob1 = add i32 %val1, 100
@@ -311,7 +311,7 @@ define double @f17(double %a, double %b, i64 %i2, i32 *%ptr) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %unext = load i32 *%ptr
+  %unext = load i32 , i32 *%ptr
   %i1 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-06.ll b/test/CodeGen/SystemZ/int-cmp-06.ll
index 82007e221766..16c2ade83553 100644
--- a/test/CodeGen/SystemZ/int-cmp-06.ll
+++ b/test/CodeGen/SystemZ/int-cmp-06.ll
@@ -111,7 +111,7 @@ define double @f9(double %a, double %b, i64 %i1, i32 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %unext = load i32 *%ptr
+  %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -123,7 +123,7 @@ define double @f10(double %a, double %b, i64 %i1, i32 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK-NOT: clgf
 ; CHECK: br %r14
-  %unext = load i32 *%ptr
+  %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -137,7 +137,7 @@ define double @f11(double %a, double %b, i64 %i1, i32 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %unext = load i32 *%ptr
+  %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp eq i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -151,7 +151,7 @@ define double @f12(double %a, double %b, i64 %i1, i32 *%ptr) {
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %unext = load i32 *%ptr
+  %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ne i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -165,8 +165,8 @@ define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131071
-  %unext = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 131071
+  %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -182,8 +182,8 @@ define double @f14(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 131072
-  %unext = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 131072
+  %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -197,8 +197,8 @@ define double @f15(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -1
-  %unext = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -1
+  %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -212,8 +212,8 @@ define double @f16(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131072
-  %unext = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -131072
+  %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -229,8 +229,8 @@ define double @f17(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -131073
-  %unext = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -131073
+  %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -247,7 +247,7 @@ define double @f18(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 524284
   %ptr = inttoptr i64 %add2 to i32 *
-  %unext = load i32 *%ptr
+  %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
@@ -260,26 +260,26 @@ define i64 @f19(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: clgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-  %ptr9 = getelementptr i32 *%ptr0, i64 18
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32, i32 *%ptr0, i64 18
 
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
-  %val9 = load i32 *%ptr9
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
+  %val9 = load i32 , i32 *%ptr9
 
   %frob0 = add i32 %val0, 100
   %frob1 = add i32 %val1, 100
@@ -374,7 +374,7 @@ define double @f22(double %a, double %b, i64 %i2, i32 *%ptr) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %unext = load i32 *%ptr
+  %unext = load i32 , i32 *%ptr
   %i1 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-07.ll b/test/CodeGen/SystemZ/int-cmp-07.ll
index 530d1787a770..0a787c9ea01d 100644
--- a/test/CodeGen/SystemZ/int-cmp-07.ll
+++ b/test/CodeGen/SystemZ/int-cmp-07.ll
@@ -20,7 +20,7 @@ define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %i2 = load i64 *%ptr
+  %i2 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -33,8 +33,8 @@ define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 65535
-  %i2 = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 65535
+  %i2 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -49,8 +49,8 @@ define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 65536
-  %i2 = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 65536
+  %i2 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -63,8 +63,8 @@ define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -1
-  %i2 = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 -1
+  %i2 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -77,8 +77,8 @@ define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -65536
-  %i2 = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 -65536
+  %i2 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -93,8 +93,8 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -65537
-  %i2 = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 -65537
+  %i2 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -110,7 +110,7 @@ define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 524280
   %ptr = inttoptr i64 %add2 to i64 *
-  %i2 = load i64 *%ptr
+  %i2 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -123,7 +123,7 @@ define double @f9(double %a, double %b, i64 %i2, i64 *%ptr) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %i1 = load i64 *%ptr
+  %i1 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
diff --git a/test/CodeGen/SystemZ/int-cmp-08.ll b/test/CodeGen/SystemZ/int-cmp-08.ll
index ebf158a1144b..384b41b549b9 100644
--- a/test/CodeGen/SystemZ/int-cmp-08.ll
+++ b/test/CodeGen/SystemZ/int-cmp-08.ll
@@ -20,7 +20,7 @@ define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %i2 = load i64 *%ptr
+  %i2 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -33,8 +33,8 @@ define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 65535
-  %i2 = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 65535
+  %i2 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -49,8 +49,8 @@ define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 65536
-  %i2 = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 65536
+  %i2 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -63,8 +63,8 @@ define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -1
-  %i2 = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 -1
+  %i2 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -77,8 +77,8 @@ define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -65536
-  %i2 = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 -65536
+  %i2 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -93,8 +93,8 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -65537
-  %i2 = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 -65537
+  %i2 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -110,7 +110,7 @@ define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 524280
   %ptr = inttoptr i64 %add2 to i64 *
-  %i2 = load i64 *%ptr
+  %i2 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -123,7 +123,7 @@ define double @f9(double %a, double %b, i64 %i2, i64 *%ptr) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %i1 = load i64 *%ptr
+  %i1 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
diff --git a/test/CodeGen/SystemZ/int-cmp-12.ll b/test/CodeGen/SystemZ/int-cmp-12.ll
index 077b22423e06..d9c6a9fc4efc 100644
--- a/test/CodeGen/SystemZ/int-cmp-12.ll
+++ b/test/CodeGen/SystemZ/int-cmp-12.ll
@@ -49,13 +49,24 @@ define double @f4(double %a, double %b, i64 %i1) {
   ret double %res
 }
 
-; Check the next value up, which must use a register comparison.
+; Check the next value up, which can use a shifted comparison
 define double @f5(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f5:
-; CHECK: clgrjl %r2,
+; CHECK: srlg [[REG:%r[0-5]]], %r2, 32
+; CHECK: cgije [[REG]], 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ult i64 %i1, 4294967296
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
+; Check the next value up, which must use a register comparison.
+define double @f6(double %a, double %b, i64 %i1) {
+; CHECK-LABEL: f6:
+; CHECK: clgrjl %r2,
+; CHECK: ldr %f0, %f2
+; CHECK: br %r14
+  %cond = icmp ult i64 %i1, 4294967297
+  %res = select i1 %cond, double %a, double %b
+  ret double %res
+}
diff --git a/test/CodeGen/SystemZ/int-cmp-15.ll b/test/CodeGen/SystemZ/int-cmp-15.ll
index 48a068e49e8f..3c1e052bc35f 100644
--- a/test/CodeGen/SystemZ/int-cmp-15.ll
+++ b/test/CodeGen/SystemZ/int-cmp-15.ll
@@ -8,7 +8,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %cond = icmp ugt i8 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -20,7 +20,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %cond = icmp ult i8 %val, 254
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -32,7 +32,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %cond = icmp slt i8 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -44,7 +44,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %cond = icmp sle i8 %val, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -56,7 +56,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %cond = icmp sge i8 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -68,7 +68,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %cond = icmp sgt i8 %val, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -80,7 +80,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %cond = icmp eq i8 %val, -128
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -92,7 +92,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %cond = icmp eq i8 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -104,7 +104,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %cond = icmp eq i8 %val, 127
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -116,7 +116,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %cond = icmp eq i8 %val, 255
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -127,8 +127,8 @@ define double @f11(double %a, double %b, i8 *%src) {
 ; CHECK-LABEL: f11:
 ; CHECK: cli 4095(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4095
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 4095
+  %val = load i8 , i8 *%ptr
   %cond = icmp ult i8 %val, 127
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -139,8 +139,8 @@ define double @f12(double %a, double %b, i8 *%src) {
 ; CHECK-LABEL: f12:
 ; CHECK: cliy 4096(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4096
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 4096
+  %val = load i8 , i8 *%ptr
   %cond = icmp ult i8 %val, 127
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -151,8 +151,8 @@ define double @f13(double %a, double %b, i8 *%src) {
 ; CHECK-LABEL: f13:
 ; CHECK: cliy 524287(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524287
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524287
+  %val = load i8 , i8 *%ptr
   %cond = icmp ult i8 %val, 127
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -165,8 +165,8 @@ define double @f14(double %a, double %b, i8 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: cli 0(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524288
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524288
+  %val = load i8 , i8 *%ptr
   %cond = icmp ult i8 %val, 127
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -177,8 +177,8 @@ define double @f15(double %a, double %b, i8 *%src) {
 ; CHECK-LABEL: f15:
 ; CHECK: cliy -1(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -1
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -1
+  %val = load i8 , i8 *%ptr
   %cond = icmp ult i8 %val, 127
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -189,8 +189,8 @@ define double @f16(double %a, double %b, i8 *%src) {
 ; CHECK-LABEL: f16:
 ; CHECK: cliy -524288(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524288
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524288
+  %val = load i8 , i8 *%ptr
   %cond = icmp ult i8 %val, 127
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -203,8 +203,8 @@ define double @f17(double %a, double %b, i8 *%src) {
 ; CHECK: agfi %r2, -524289
 ; CHECK: cli 0(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524289
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524289
+  %val = load i8 , i8 *%ptr
   %cond = icmp ult i8 %val, 127
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -219,7 +219,7 @@ define double @f18(double %a, double %b, i64 %base, i64 %index) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4095
   %ptr = inttoptr i64 %add2 to i8 *
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %cond = icmp ult i8 %val, 127
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -234,7 +234,7 @@ define double @f19(double %a, double %b, i64 %base, i64 %index) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i8 *
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %cond = icmp ult i8 %val, 127
   %res = select i1 %cond, double %a, double %b
   ret double %res
diff --git a/test/CodeGen/SystemZ/int-cmp-16.ll b/test/CodeGen/SystemZ/int-cmp-16.ll
index be206d9c9470..37508b5e740f 100644
--- a/test/CodeGen/SystemZ/int-cmp-16.ll
+++ b/test/CodeGen/SystemZ/int-cmp-16.ll
@@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp eq i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp eq i32 %ext, 255
   %res = select i1 %cond, double %a, double %b
@@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp eq i32 %ext, 256
   %res = select i1 %cond, double %a, double %b
@@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp eq i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp eq i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp eq i32 %ext, 127
   %res = select i1 %cond, double %a, double %b
@@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp eq i32 %ext, 128
   %res = select i1 %cond, double %a, double %b
@@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp eq i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp eq i32 %ext, -128
   %res = select i1 %cond, double %a, double %b
@@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp eq i32 %ext, -129
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-17.ll b/test/CodeGen/SystemZ/int-cmp-17.ll
index 3df4ecc66803..a22fb604d453 100644
--- a/test/CodeGen/SystemZ/int-cmp-17.ll
+++ b/test/CodeGen/SystemZ/int-cmp-17.ll
@@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp ne i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp ne i32 %ext, 255
   %res = select i1 %cond, double %a, double %b
@@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp ne i32 %ext, 256
   %res = select i1 %cond, double %a, double %b
@@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp ne i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ne i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ne i32 %ext, 127
   %res = select i1 %cond, double %a, double %b
@@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ne i32 %ext, 128
   %res = select i1 %cond, double %a, double %b
@@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ne i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ne i32 %ext, -128
   %res = select i1 %cond, double %a, double %b
@@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ne i32 %ext, -129
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-18.ll b/test/CodeGen/SystemZ/int-cmp-18.ll
index d03d6ac9a2c7..f4bc5c0e5ce9 100644
--- a/test/CodeGen/SystemZ/int-cmp-18.ll
+++ b/test/CodeGen/SystemZ/int-cmp-18.ll
@@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp eq i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp eq i64 %ext, 255
   %res = select i1 %cond, double %a, double %b
@@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp eq i64 %ext, 256
   %res = select i1 %cond, double %a, double %b
@@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp eq i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp eq i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp eq i64 %ext, 127
   %res = select i1 %cond, double %a, double %b
@@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp eq i64 %ext, 128
   %res = select i1 %cond, double %a, double %b
@@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp eq i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp eq i64 %ext, -128
   %res = select i1 %cond, double %a, double %b
@@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp eq i64 %ext, -129
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-19.ll b/test/CodeGen/SystemZ/int-cmp-19.ll
index b5f0856b4002..0a23f06a0581 100644
--- a/test/CodeGen/SystemZ/int-cmp-19.ll
+++ b/test/CodeGen/SystemZ/int-cmp-19.ll
@@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp ne i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp ne i64 %ext, 255
   %res = select i1 %cond, double %a, double %b
@@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp ne i64 %ext, 256
   %res = select i1 %cond, double %a, double %b
@@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp ne i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ne i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ne i64 %ext, 127
   %res = select i1 %cond, double %a, double %b
@@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ne i64 %ext, 128
   %res = select i1 %cond, double %a, double %b
@@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ne i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ne i64 %ext, -128
   %res = select i1 %cond, double %a, double %b
@@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ne i64 %ext, -129
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-20.ll b/test/CodeGen/SystemZ/int-cmp-20.ll
index 98c41cd3a240..2acff55af59c 100644
--- a/test/CodeGen/SystemZ/int-cmp-20.ll
+++ b/test/CodeGen/SystemZ/int-cmp-20.ll
@@ -10,7 +10,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp ugt i32 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -24,7 +24,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ugt i32 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -38,7 +38,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp ult i32 %ext, 254
   %res = select i1 %cond, double %a, double %b
@@ -52,7 +52,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ult i32 %ext, -2
   %res = select i1 %cond, double %a, double %b
@@ -65,7 +65,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK-NOT: cli {{.*}}
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp ult i32 %ext, 256
   %res = select i1 %cond, double %a, double %b
@@ -81,7 +81,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: cli {{.*}}
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ult i32 %ext, 128
   %res = select i1 %cond, double %a, double %b
@@ -93,7 +93,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: cli {{.*}}
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ult i32 %ext, -129
   %res = select i1 %cond, double %a, double %b
@@ -107,7 +107,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp sgt i32 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -120,7 +120,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK-NOT: cli {{.*}}
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp sgt i32 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -134,7 +134,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp slt i32 %ext, 254
   %res = select i1 %cond, double %a, double %b
@@ -147,7 +147,7 @@ define double @f11(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f11:
 ; CHECK-NOT: cli {{.*}}
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp slt i32 %ext, -2
   %res = select i1 %cond, double %a, double %b
@@ -160,7 +160,7 @@ define double @f12(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f12:
 ; CHECK-NOT: cli {{.*}}
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp slt i32 %ext, 256
   %res = select i1 %cond, double %a, double %b
@@ -173,7 +173,7 @@ define double @f13(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp sge i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -186,7 +186,7 @@ define double @f14(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp sgt i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -199,7 +199,7 @@ define double @f15(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp slt i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -212,7 +212,7 @@ define double @f16(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp sle i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-21.ll b/test/CodeGen/SystemZ/int-cmp-21.ll
index ca9225dead92..5be97324f643 100644
--- a/test/CodeGen/SystemZ/int-cmp-21.ll
+++ b/test/CodeGen/SystemZ/int-cmp-21.ll
@@ -10,7 +10,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp ugt i64 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -24,7 +24,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ugt i64 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -38,7 +38,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp ult i64 %ext, 254
   %res = select i1 %cond, double %a, double %b
@@ -52,7 +52,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ult i64 %ext, -2
   %res = select i1 %cond, double %a, double %b
@@ -65,7 +65,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp ult i64 %ext, 256
   %res = select i1 %cond, double %a, double %b
@@ -81,7 +81,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ult i64 %ext, 128
   %res = select i1 %cond, double %a, double %b
@@ -93,7 +93,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ult i64 %ext, -129
   %res = select i1 %cond, double %a, double %b
@@ -107,7 +107,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp sgt i64 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -120,7 +120,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp sgt i64 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -134,7 +134,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp slt i64 %ext, 254
   %res = select i1 %cond, double %a, double %b
@@ -147,7 +147,7 @@ define double @f11(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f11:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp slt i64 %ext, -2
   %res = select i1 %cond, double %a, double %b
@@ -160,7 +160,7 @@ define double @f12(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f12:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp slt i64 %ext, 256
   %res = select i1 %cond, double %a, double %b
@@ -173,7 +173,7 @@ define double @f13(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp sge i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -186,7 +186,7 @@ define double @f14(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp sgt i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -199,7 +199,7 @@ define double @f15(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp slt i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -212,7 +212,7 @@ define double @f16(double %a, double %b, i8 *%ptr) {
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp sle i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-22.ll b/test/CodeGen/SystemZ/int-cmp-22.ll
index 43daec95b7d8..f29023cf02ae 100644
--- a/test/CodeGen/SystemZ/int-cmp-22.ll
+++ b/test/CodeGen/SystemZ/int-cmp-22.ll
@@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK-NEXT: jle
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -35,7 +35,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, 32766
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -48,7 +48,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -61,7 +61,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, -32766
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -74,8 +74,8 @@ define double @f6(double %a, double %b, i16 %i1, i16 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%base, i64 2047
-  %val = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%base, i64 2047
+  %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -89,8 +89,8 @@ define double @f7(double %a, double %b, i16 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%base, i64 2048
-  %val = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%base, i64 2048
+  %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -104,8 +104,8 @@ define double @f8(double %a, double %b, i16 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%base, i64 -1
-  %val = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%base, i64 -1
+  %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -121,7 +121,7 @@ define double @f9(double %a, double %b, i64 %base, i64 %index) {
 ; CHECK: br %r14
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i16 *
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
diff --git a/test/CodeGen/SystemZ/int-cmp-23.ll b/test/CodeGen/SystemZ/int-cmp-23.ll
index 99fe74b1c787..df6b62616a79 100644
--- a/test/CodeGen/SystemZ/int-cmp-23.ll
+++ b/test/CodeGen/SystemZ/int-cmp-23.ll
@@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp ugt i16 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp ult i16 %val, 65534
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -35,8 +35,8 @@ define double @f3(double %a, double %b, i16 %i1, i16 *%base) {
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%base, i64 2047
-  %val = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%base, i64 2047
+  %val = load i16 , i16 *%ptr
   %cond = icmp ugt i16 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -50,8 +50,8 @@ define double @f4(double %a, double %b, i16 *%base) {
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%base, i64 2048
-  %val = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%base, i64 2048
+  %val = load i16 , i16 *%ptr
   %cond = icmp ugt i16 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -65,8 +65,8 @@ define double @f5(double %a, double %b, i16 *%base) {
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%base, i64 -1
-  %val = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%base, i64 -1
+  %val = load i16 , i16 *%ptr
   %cond = icmp ugt i16 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -82,7 +82,7 @@ define double @f6(double %a, double %b, i64 %base, i64 %index) {
 ; CHECK: br %r14
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i16 *
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp ugt i16 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
diff --git a/test/CodeGen/SystemZ/int-cmp-24.ll b/test/CodeGen/SystemZ/int-cmp-24.ll
index 1a8e587b0341..e1141a78ddda 100644
--- a/test/CodeGen/SystemZ/int-cmp-24.ll
+++ b/test/CodeGen/SystemZ/int-cmp-24.ll
@@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp eq i16 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp eq i16 %val, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -35,7 +35,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp eq i16 %val, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -48,7 +48,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp eq i16 %val, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
diff --git a/test/CodeGen/SystemZ/int-cmp-25.ll b/test/CodeGen/SystemZ/int-cmp-25.ll
index 50803df1ba91..268530316506 100644
--- a/test/CodeGen/SystemZ/int-cmp-25.ll
+++ b/test/CodeGen/SystemZ/int-cmp-25.ll
@@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp ne i16 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp ne i16 %val, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -35,7 +35,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp ne i16 %val, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -48,7 +48,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %cond = icmp ne i16 %val, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
diff --git a/test/CodeGen/SystemZ/int-cmp-26.ll b/test/CodeGen/SystemZ/int-cmp-26.ll
index 60778654b275..ba93f081e9b9 100644
--- a/test/CodeGen/SystemZ/int-cmp-26.ll
+++ b/test/CodeGen/SystemZ/int-cmp-26.ll
@@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp eq i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp eq i32 %ext, 65535
   %res = select i1 %cond, double %a, double %b
@@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp eq i32 %ext, 65536
   %res = select i1 %cond, double %a, double %b
@@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp eq i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp eq i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp eq i32 %ext, 32767
   %res = select i1 %cond, double %a, double %b
@@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp eq i32 %ext, 32768
   %res = select i1 %cond, double %a, double %b
@@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp eq i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp eq i32 %ext, -32768
   %res = select i1 %cond, double %a, double %b
@@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp eq i32 %ext, -32769
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-27.ll b/test/CodeGen/SystemZ/int-cmp-27.ll
index 3102f5c5faa4..9a503c9254a2 100644
--- a/test/CodeGen/SystemZ/int-cmp-27.ll
+++ b/test/CodeGen/SystemZ/int-cmp-27.ll
@@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp ne i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp ne i32 %ext, 65535
   %res = select i1 %cond, double %a, double %b
@@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp ne i32 %ext, 65536
   %res = select i1 %cond, double %a, double %b
@@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp ne i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ne i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ne i32 %ext, 32767
   %res = select i1 %cond, double %a, double %b
@@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ne i32 %ext, 32768
   %res = select i1 %cond, double %a, double %b
@@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ne i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ne i32 %ext, -32768
   %res = select i1 %cond, double %a, double %b
@@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ne i32 %ext, -32769
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-28.ll b/test/CodeGen/SystemZ/int-cmp-28.ll
index c3b905974ebc..68f1cd28c62d 100644
--- a/test/CodeGen/SystemZ/int-cmp-28.ll
+++ b/test/CodeGen/SystemZ/int-cmp-28.ll
@@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp eq i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp eq i64 %ext, 65535
   %res = select i1 %cond, double %a, double %b
@@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp eq i64 %ext, 65536
   %res = select i1 %cond, double %a, double %b
@@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp eq i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp eq i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp eq i64 %ext, 32767
   %res = select i1 %cond, double %a, double %b
@@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp eq i64 %ext, 32768
   %res = select i1 %cond, double %a, double %b
@@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp eq i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp eq i64 %ext, -32768
   %res = select i1 %cond, double %a, double %b
@@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp eq i64 %ext, -32769
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-29.ll b/test/CodeGen/SystemZ/int-cmp-29.ll
index 1b40d8cfb2ae..4fb2e8577699 100644
--- a/test/CodeGen/SystemZ/int-cmp-29.ll
+++ b/test/CodeGen/SystemZ/int-cmp-29.ll
@@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp ne i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp ne i64 %ext, 65535
   %res = select i1 %cond, double %a, double %b
@@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp ne i64 %ext, 65536
   %res = select i1 %cond, double %a, double %b
@@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp ne i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ne i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
@@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ne i64 %ext, 32767
   %res = select i1 %cond, double %a, double %b
@@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ne i64 %ext, 32768
   %res = select i1 %cond, double %a, double %b
@@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ne i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
@@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ne i64 %ext, -32768
   %res = select i1 %cond, double %a, double %b
@@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ne i64 %ext, -32769
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-30.ll b/test/CodeGen/SystemZ/int-cmp-30.ll
index 6c9498cb3320..043ff484c145 100644
--- a/test/CodeGen/SystemZ/int-cmp-30.ll
+++ b/test/CodeGen/SystemZ/int-cmp-30.ll
@@ -10,7 +10,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp ugt i32 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -24,7 +24,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ugt i32 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -38,7 +38,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp ult i32 %ext, 65534
   %res = select i1 %cond, double %a, double %b
@@ -52,7 +52,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ult i32 %ext, -2
   %res = select i1 %cond, double %a, double %b
@@ -65,7 +65,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp ult i32 %ext, 65536
   %res = select i1 %cond, double %a, double %b
@@ -82,7 +82,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ult i32 %ext, 32768
   %res = select i1 %cond, double %a, double %b
@@ -94,7 +94,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ult i32 %ext, -32769
   %res = select i1 %cond, double %a, double %b
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp sgt i32 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; CHECK: chhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp sgt i32 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -136,7 +136,7 @@ define double @f10(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp slt i32 %ext, 65534
   %res = select i1 %cond, double %a, double %b
@@ -150,7 +150,7 @@ define double @f11(double %a, double %b, i16 *%ptr) {
 ; CHECK: chhsi 0(%r2), -2
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp slt i32 %ext, -2
   %res = select i1 %cond, double %a, double %b
@@ -163,7 +163,7 @@ define double @f12(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f12:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp slt i32 %ext, 65536
   %res = select i1 %cond, double %a, double %b
@@ -177,7 +177,7 @@ define double @f13(double %a, double %b, i16 *%ptr) {
 ; CHECK: chhsi 0(%r2), 32766
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp slt i32 %ext, 32766
   %res = select i1 %cond, double %a, double %b
@@ -190,7 +190,7 @@ define double @f14(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f14:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp slt i32 %ext, 32768
   %res = select i1 %cond, double %a, double %b
@@ -204,7 +204,7 @@ define double @f15(double %a, double %b, i16 *%ptr) {
 ; CHECK: chhsi 0(%r2), -32767
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp sgt i32 %ext, -32767
   %res = select i1 %cond, double %a, double %b
@@ -217,7 +217,7 @@ define double @f16(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f16:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp sgt i32 %ext, -32769
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-31.ll b/test/CodeGen/SystemZ/int-cmp-31.ll
index 21539f20470e..298b446e7f1d 100644
--- a/test/CodeGen/SystemZ/int-cmp-31.ll
+++ b/test/CodeGen/SystemZ/int-cmp-31.ll
@@ -10,7 +10,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp ugt i64 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -24,7 +24,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ugt i64 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -38,7 +38,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp ult i64 %ext, 65534
   %res = select i1 %cond, double %a, double %b
@@ -52,7 +52,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ult i64 %ext, -2
   %res = select i1 %cond, double %a, double %b
@@ -65,7 +65,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp ult i64 %ext, 65536
   %res = select i1 %cond, double %a, double %b
@@ -82,7 +82,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ult i64 %ext, 32768
   %res = select i1 %cond, double %a, double %b
@@ -94,7 +94,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ult i64 %ext, -32769
   %res = select i1 %cond, double %a, double %b
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp sgt i64 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; CHECK: chhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp sgt i64 %ext, 1
   %res = select i1 %cond, double %a, double %b
@@ -136,7 +136,7 @@ define double @f10(double %a, double %b, i16 *%ptr) {
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp slt i64 %ext, 65534
   %res = select i1 %cond, double %a, double %b
@@ -150,7 +150,7 @@ define double @f11(double %a, double %b, i16 *%ptr) {
 ; CHECK: chhsi 0(%r2), -2
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp slt i64 %ext, -2
   %res = select i1 %cond, double %a, double %b
@@ -163,7 +163,7 @@ define double @f12(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f12:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp slt i64 %ext, 65536
   %res = select i1 %cond, double %a, double %b
@@ -177,7 +177,7 @@ define double @f13(double %a, double %b, i16 *%ptr) {
 ; CHECK: chhsi 0(%r2), 32766
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp slt i64 %ext, 32766
   %res = select i1 %cond, double %a, double %b
@@ -190,7 +190,7 @@ define double @f14(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f14:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp slt i64 %ext, 32768
   %res = select i1 %cond, double %a, double %b
@@ -204,7 +204,7 @@ define double @f15(double %a, double %b, i16 *%ptr) {
 ; CHECK: chhsi 0(%r2), -32767
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp sgt i64 %ext, -32767
   %res = select i1 %cond, double %a, double %b
@@ -217,7 +217,7 @@ define double @f16(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f16:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
-  %val = load i16 *%ptr
+  %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp sgt i64 %ext, -32769
   %res = select i1 %cond, double %a, double %b
diff --git a/test/CodeGen/SystemZ/int-cmp-32.ll b/test/CodeGen/SystemZ/int-cmp-32.ll
index 6596f9f3ad84..da0e2d7562dd 100644
--- a/test/CodeGen/SystemZ/int-cmp-32.ll
+++ b/test/CodeGen/SystemZ/int-cmp-32.ll
@@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i32 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i32 *%ptr) {
 ; CHECK-NEXT: jle
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -35,7 +35,7 @@ define double @f3(double %a, double %b, i32 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -46,7 +46,7 @@ define double @f4(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -59,7 +59,7 @@ define double @f5(double %a, double %b, i32 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -72,7 +72,7 @@ define double @f6(double %a, double %b, i32 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -83,7 +83,7 @@ define double @f7(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, -32769
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -96,7 +96,7 @@ define double @f8(double %a, double %b, i32 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -109,7 +109,7 @@ define double @f9(double %a, double %b, i32 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -122,7 +122,7 @@ define double @f10(double %a, double %b, i32 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -133,7 +133,7 @@ define double @f11(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f11:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, 32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -146,7 +146,7 @@ define double @f12(double %a, double %b, i32 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -159,7 +159,7 @@ define double @f13(double %a, double %b, i32 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -170,7 +170,7 @@ define double @f14(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f14:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, -32769
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -183,8 +183,8 @@ define double @f15(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 1023
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 1023
+  %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -198,8 +198,8 @@ define double @f16(double %a, double %b, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 1024
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 1024
+  %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -213,8 +213,8 @@ define double @f17(double %a, double %b, i32 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -1
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -1
+  %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -230,7 +230,7 @@ define double @f18(double %a, double %b, i64 %base, i64 %index) {
 ; CHECK: br %r14
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i32 *
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
diff --git a/test/CodeGen/SystemZ/int-cmp-33.ll b/test/CodeGen/SystemZ/int-cmp-33.ll
index e5a653b3815d..94f3e705391e 100644
--- a/test/CodeGen/SystemZ/int-cmp-33.ll
+++ b/test/CodeGen/SystemZ/int-cmp-33.ll
@@ -10,7 +10,7 @@ define double @f1(double %a, double %b, i32 *%ptr) {
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp ugt i32 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -23,7 +23,7 @@ define double @f2(double %a, double %b, i32 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp ult i32 %val, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: clfhsi
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp ult i32 %val, 65536
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -48,7 +48,7 @@ define double @f4(double %a, double %b, i32 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, 32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -61,7 +61,7 @@ define double @f5(double %a, double %b, i32 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -72,7 +72,7 @@ define double @f6(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: clfhsi
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, 65536
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -85,8 +85,8 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 1023
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 1023
+  %val = load i32 , i32 *%ptr
   %cond = icmp ugt i32 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -100,8 +100,8 @@ define double @f8(double %a, double %b, i32 *%base) {
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 1024
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 1024
+  %val = load i32 , i32 *%ptr
   %cond = icmp ugt i32 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -115,8 +115,8 @@ define double @f9(double %a, double %b, i32 *%base) {
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%base, i64 -1
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%base, i64 -1
+  %val = load i32 , i32 *%ptr
   %cond = icmp ugt i32 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -132,7 +132,7 @@ define double @f10(double %a, double %b, i64 %base, i64 %index) {
 ; CHECK: br %r14
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i32 *
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %cond = icmp ugt i32 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
diff --git a/test/CodeGen/SystemZ/int-cmp-34.ll b/test/CodeGen/SystemZ/int-cmp-34.ll
index 8a0219775a4e..114b694a3b09 100644
--- a/test/CodeGen/SystemZ/int-cmp-34.ll
+++ b/test/CodeGen/SystemZ/int-cmp-34.ll
@@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i64 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i64 *%ptr) {
 ; CHECK-NEXT: jle
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -35,7 +35,7 @@ define double @f3(double %a, double %b, i64 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -46,7 +46,7 @@ define double @f4(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -59,7 +59,7 @@ define double @f5(double %a, double %b, i64 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -72,7 +72,7 @@ define double @f6(double %a, double %b, i64 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -83,7 +83,7 @@ define double @f7(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, -32769
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -96,7 +96,7 @@ define double @f8(double %a, double %b, i64 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -109,7 +109,7 @@ define double @f9(double %a, double %b, i64 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -122,7 +122,7 @@ define double @f10(double %a, double %b, i64 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -133,7 +133,7 @@ define double @f11(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f11:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, 32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -146,7 +146,7 @@ define double @f12(double %a, double %b, i64 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -159,7 +159,7 @@ define double @f13(double %a, double %b, i64 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -170,7 +170,7 @@ define double @f14(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f14:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, -32769
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -183,8 +183,8 @@ define double @f15(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 511
-  %val = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 511
+  %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -198,8 +198,8 @@ define double @f16(double %a, double %b, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 512
-  %val = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 512
+  %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -213,8 +213,8 @@ define double @f17(double %a, double %b, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -1
-  %val = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 -1
+  %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -230,7 +230,7 @@ define double @f18(double %a, double %b, i64 %base, i64 %index) {
 ; CHECK: br %r14
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i64 *
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
diff --git a/test/CodeGen/SystemZ/int-cmp-35.ll b/test/CodeGen/SystemZ/int-cmp-35.ll
index 539248a86a7b..0eaf4fa0a075 100644
--- a/test/CodeGen/SystemZ/int-cmp-35.ll
+++ b/test/CodeGen/SystemZ/int-cmp-35.ll
@@ -10,7 +10,7 @@ define double @f1(double %a, double %b, i64 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp ult i64 %val, 2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -23,7 +23,7 @@ define double @f2(double %a, double %b, i64 *%ptr) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp ult i64 %val, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: clghsi
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp ult i64 %val, 65536
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -48,7 +48,7 @@ define double @f4(double %a, double %b, i64 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, 32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -61,7 +61,7 @@ define double @f5(double %a, double %b, i64 *%ptr) {
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -72,7 +72,7 @@ define double @f6(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: clghsi
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, 65536
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -85,8 +85,8 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 511
-  %val = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 511
+  %val = load i64 , i64 *%ptr
   %cond = icmp ult i64 %val, 2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -100,8 +100,8 @@ define double @f8(double %a, double %b, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 512
-  %val = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 512
+  %val = load i64 , i64 *%ptr
   %cond = icmp ult i64 %val, 2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -115,8 +115,8 @@ define double @f9(double %a, double %b, i64 *%base) {
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%base, i64 -1
-  %val = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%base, i64 -1
+  %val = load i64 , i64 *%ptr
   %cond = icmp ult i64 %val, 2
   %res = select i1 %cond, double %a, double %b
   ret double %res
@@ -132,7 +132,7 @@ define double @f10(double %a, double %b, i64 %base, i64 %index) {
 ; CHECK: br %r14
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i64 *
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   %cond = icmp ult i64 %val, 2
   %res = select i1 %cond, double %a, double %b
   ret double %res
diff --git a/test/CodeGen/SystemZ/int-cmp-36.ll b/test/CodeGen/SystemZ/int-cmp-36.ll
index fa2d4bf6c617..113d2c1587e0 100644
--- a/test/CodeGen/SystemZ/int-cmp-36.ll
+++ b/test/CodeGen/SystemZ/int-cmp-36.ll
@@ -13,7 +13,7 @@ define i32 @f1(i32 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = sext i16 %val to i32
   %cond = icmp slt i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -31,7 +31,7 @@ define i32 @f2(i32 %src1) {
 ; CHECK-NOT: chrl
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = sext i16 %val to i32
   %cond = icmp ult i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -50,7 +50,7 @@ define i32 @f3(i32 %src1) {
 ; CHECK-NEXT: je
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = sext i16 %val to i32
   %cond = icmp eq i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -69,7 +69,7 @@ define i32 @f4(i32 %src1) {
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = sext i16 %val to i32
   %cond = icmp ne i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -89,7 +89,7 @@ define i32 @f5(i32 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@h, align 1
+  %val = load i16 , i16 *@h, align 1
   %src2 = sext i16 %val to i32
   %cond = icmp slt i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -108,7 +108,7 @@ define i32 @f6(i32 %src2) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src1 = sext i16 %val to i32
   %cond = icmp slt i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
diff --git a/test/CodeGen/SystemZ/int-cmp-37.ll b/test/CodeGen/SystemZ/int-cmp-37.ll
index 8095ed173012..ac5d39f96511 100644
--- a/test/CodeGen/SystemZ/int-cmp-37.ll
+++ b/test/CodeGen/SystemZ/int-cmp-37.ll
@@ -13,7 +13,7 @@ define i32 @f1(i32 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i32
   %cond = icmp ult i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -31,7 +31,7 @@ define i32 @f2(i32 %src1) {
 ; CHECK-NOT: clhrl
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i32
   %cond = icmp slt i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -50,7 +50,7 @@ define i32 @f3(i32 %src1) {
 ; CHECK-NEXT: je
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i32
   %cond = icmp eq i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -69,7 +69,7 @@ define i32 @f4(i32 %src1) {
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i32
   %cond = icmp ne i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -89,7 +89,7 @@ define i32 @f5(i32 %src1) {
 ; CHECK: clrjl %r2, [[VAL]],
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@h, align 1
+  %val = load i16 , i16 *@h, align 1
   %src2 = zext i16 %val to i32
   %cond = icmp ult i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -108,7 +108,7 @@ define i32 @f6(i32 %src2) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src1 = zext i16 %val to i32
   %cond = icmp ult i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
diff --git a/test/CodeGen/SystemZ/int-cmp-38.ll b/test/CodeGen/SystemZ/int-cmp-38.ll
index 901758378729..0d8913b02861 100644
--- a/test/CodeGen/SystemZ/int-cmp-38.ll
+++ b/test/CodeGen/SystemZ/int-cmp-38.ll
@@ -13,7 +13,7 @@ define i32 @f1(i32 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %src2 = load i32 *@g
+  %src2 = load i32 , i32 *@g
   %cond = icmp slt i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
@@ -31,7 +31,7 @@ define i32 @f2(i32 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %src2 = load i32 *@g
+  %src2 = load i32 , i32 *@g
   %cond = icmp ult i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
@@ -49,7 +49,7 @@ define i32 @f3(i32 %src1) {
 ; CHECK-NEXT: je
 ; CHECK: br %r14
 entry:
-  %src2 = load i32 *@g
+  %src2 = load i32 , i32 *@g
   %cond = icmp eq i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
@@ -67,7 +67,7 @@ define i32 @f4(i32 %src1) {
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
 entry:
-  %src2 = load i32 *@g
+  %src2 = load i32 , i32 *@g
   %cond = icmp ne i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
@@ -86,7 +86,7 @@ define i32 @f5(i32 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %src2 = load i32 *@h, align 2
+  %src2 = load i32 , i32 *@h, align 2
   %cond = icmp slt i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
@@ -105,7 +105,7 @@ define i32 @f6(i32 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %src2 = load i32 *@h, align 2
+  %src2 = load i32 , i32 *@h, align 2
   %cond = icmp ult i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
@@ -123,7 +123,7 @@ define i32 @f7(i32 %src2) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: br %r14
 entry:
-  %src1 = load i32 *@g
+  %src1 = load i32 , i32 *@g
   %cond = icmp slt i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
diff --git a/test/CodeGen/SystemZ/int-cmp-39.ll b/test/CodeGen/SystemZ/int-cmp-39.ll
index fc9547d4ceb4..5e3abceeca45 100644
--- a/test/CodeGen/SystemZ/int-cmp-39.ll
+++ b/test/CodeGen/SystemZ/int-cmp-39.ll
@@ -13,7 +13,7 @@ define i64 @f1(i64 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = sext i16 %val to i64
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -31,7 +31,7 @@ define i64 @f2(i64 %src1) {
 ; CHECK-NOT: cghrl
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = sext i16 %val to i64
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -50,7 +50,7 @@ define i64 @f3(i64 %src1) {
 ; CHECK-NEXT: je
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = sext i16 %val to i64
   %cond = icmp eq i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -69,7 +69,7 @@ define i64 @f4(i64 %src1) {
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = sext i16 %val to i64
   %cond = icmp ne i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -89,7 +89,7 @@ define i64 @f5(i64 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@h, align 1
+  %val = load i16 , i16 *@h, align 1
   %src2 = sext i16 %val to i64
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -108,7 +108,7 @@ define i64 @f6(i64 %src2) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src1 = sext i16 %val to i64
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
diff --git a/test/CodeGen/SystemZ/int-cmp-40.ll b/test/CodeGen/SystemZ/int-cmp-40.ll
index 9c532f1cbc6b..92696d71fc48 100644
--- a/test/CodeGen/SystemZ/int-cmp-40.ll
+++ b/test/CodeGen/SystemZ/int-cmp-40.ll
@@ -13,7 +13,7 @@ define i64 @f1(i64 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i64
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -31,7 +31,7 @@ define i64 @f2(i64 %src1) {
 ; CHECK-NOT: clghrl
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i64
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -50,7 +50,7 @@ define i64 @f3(i64 %src1) {
 ; CHECK-NEXT: je
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i64
   %cond = icmp eq i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -69,7 +69,7 @@ define i64 @f4(i64 %src1) {
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i64
   %cond = icmp ne i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -89,7 +89,7 @@ define i64 @f5(i64 %src1) {
 ; CHECK: clgrjl %r2, [[VAL]],
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@h, align 1
+  %val = load i16 , i16 *@h, align 1
   %src2 = zext i16 %val to i64
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -108,7 +108,7 @@ define i64 @f6(i64 %src2) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src1 = zext i16 %val to i64
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
diff --git a/test/CodeGen/SystemZ/int-cmp-41.ll b/test/CodeGen/SystemZ/int-cmp-41.ll
index 77f6e7d76f1c..f4f5b4a0cf16 100644
--- a/test/CodeGen/SystemZ/int-cmp-41.ll
+++ b/test/CodeGen/SystemZ/int-cmp-41.ll
@@ -13,7 +13,7 @@ define i64 @f1(i64 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %val = load i32 *@g
+  %val = load i32 , i32 *@g
   %src2 = sext i32 %val to i64
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -31,7 +31,7 @@ define i64 @f2(i64 %src1) {
 ; CHECK-NOT: cgfrl
 ; CHECK: br %r14
 entry:
-  %val = load i32 *@g
+  %val = load i32 , i32 *@g
   %src2 = sext i32 %val to i64
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -50,7 +50,7 @@ define i64 @f3(i64 %src1) {
 ; CHECK-NEXT: je
 ; CHECK: br %r14
 entry:
-  %val = load i32 *@g
+  %val = load i32 , i32 *@g
   %src2 = sext i32 %val to i64
   %cond = icmp eq i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -69,7 +69,7 @@ define i64 @f4(i64 %src1) {
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
 entry:
-  %val = load i32 *@g
+  %val = load i32 , i32 *@g
   %src2 = sext i32 %val to i64
   %cond = icmp ne i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -89,7 +89,7 @@ define i64 @f5(i64 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %val = load i32 *@h, align 2
+  %val = load i32 , i32 *@h, align 2
   %src2 = sext i32 %val to i64
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -108,7 +108,7 @@ define i64 @f6(i64 %src2) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: br %r14
 entry:
-  %val = load i32 *@g
+  %val = load i32 , i32 *@g
   %src1 = sext i32 %val to i64
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
diff --git a/test/CodeGen/SystemZ/int-cmp-42.ll b/test/CodeGen/SystemZ/int-cmp-42.ll
index 94ef0082c441..ca87b865ad14 100644
--- a/test/CodeGen/SystemZ/int-cmp-42.ll
+++ b/test/CodeGen/SystemZ/int-cmp-42.ll
@@ -13,7 +13,7 @@ define i64 @f1(i64 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %val = load i32 *@g
+  %val = load i32 , i32 *@g
   %src2 = zext i32 %val to i64
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -31,7 +31,7 @@ define i64 @f2(i64 %src1) {
 ; CHECK-NOT: clgfrl
 ; CHECK: br %r14
 entry:
-  %val = load i32 *@g
+  %val = load i32 , i32 *@g
   %src2 = zext i32 %val to i64
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -50,7 +50,7 @@ define i64 @f3(i64 %src1) {
 ; CHECK-NEXT: je
 ; CHECK: br %r14
 entry:
-  %val = load i32 *@g
+  %val = load i32 , i32 *@g
   %src2 = zext i32 %val to i64
   %cond = icmp eq i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -69,7 +69,7 @@ define i64 @f4(i64 %src1) {
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
 entry:
-  %val = load i32 *@g
+  %val = load i32 , i32 *@g
   %src2 = zext i32 %val to i64
   %cond = icmp ne i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -89,7 +89,7 @@ define i64 @f5(i64 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %val = load i32 *@h, align 2
+  %val = load i32 , i32 *@h, align 2
   %src2 = zext i32 %val to i64
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -108,7 +108,7 @@ define i64 @f6(i64 %src2) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: br %r14
 entry:
-  %val = load i32 *@g
+  %val = load i32 , i32 *@g
   %src1 = zext i32 %val to i64
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
diff --git a/test/CodeGen/SystemZ/int-cmp-43.ll b/test/CodeGen/SystemZ/int-cmp-43.ll
index 1a625886dec2..108b041fa377 100644
--- a/test/CodeGen/SystemZ/int-cmp-43.ll
+++ b/test/CodeGen/SystemZ/int-cmp-43.ll
@@ -13,7 +13,7 @@ define i64 @f1(i64 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %src2 = load i64 *@g
+  %src2 = load i64 , i64 *@g
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
@@ -31,7 +31,7 @@ define i64 @f2(i64 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %src2 = load i64 *@g
+  %src2 = load i64 , i64 *@g
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
@@ -49,7 +49,7 @@ define i64 @f3(i64 %src1) {
 ; CHECK-NEXT: je
 ; CHECK: br %r14
 entry:
-  %src2 = load i64 *@g
+  %src2 = load i64 , i64 *@g
   %cond = icmp eq i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
@@ -67,7 +67,7 @@ define i64 @f4(i64 %src1) {
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
 entry:
-  %src2 = load i64 *@g
+  %src2 = load i64 , i64 *@g
   %cond = icmp ne i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
@@ -86,7 +86,7 @@ define i64 @f5(i64 %src1) {
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %src2 = load i64 *@h, align 4
+  %src2 = load i64 , i64 *@h, align 4
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
@@ -104,7 +104,7 @@ define i64 @f6(i64 %src2) {
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: br %r14
 entry:
-  %src1 = load i64 *@g
+  %src1 = load i64 , i64 *@g
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
diff --git a/test/CodeGen/SystemZ/int-cmp-44.ll b/test/CodeGen/SystemZ/int-cmp-44.ll
index 30c1c4f1ed6c..97d48521254d 100644
--- a/test/CodeGen/SystemZ/int-cmp-44.ll
+++ b/test/CodeGen/SystemZ/int-cmp-44.ll
@@ -127,7 +127,7 @@ define i32 @f7(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-NEXT: jne .L{{.*}}
 ; CHECK: br %r14
 entry:
-  %cur = load i32 *%dest
+  %cur = load i32 , i32 *%dest
   %res = sub i32 %a, %cur
   %cmp = icmp ne i32 %res, 0
   br i1 %cmp, label %exit, label %store
@@ -147,7 +147,7 @@ define i32 @f8(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-NEXT: cijl %r2, 0, .L{{.*}}
 ; CHECK: br %r14
 entry:
-  %cur = load i32 *%dest
+  %cur = load i32 , i32 *%dest
   %res = sub i32 %a, %cur
   %cmp = icmp slt i32 %res, 0
   br i1 %cmp, label %exit, label %store
@@ -468,7 +468,7 @@ define void @f24(i32 *%ptr) {
 ; CHECK-NEXT: cijlh [[REG]], 0, .L{{.*}}
 ; CHECK: br %r14
 entry:
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %xor = xor i32 %val, 1
   %add = add i32 %xor, 1000000
   call void @foo()
@@ -561,7 +561,7 @@ define void @f28(i64 %a, i64 *%dest) {
 ; CHECK: br %r14
 entry:
   %ptr = inttoptr i64 %a to i8 *
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %xor = xor i8 %val, 15
   store i8 %xor, i8 *%ptr
   %cmp = icmp eq i64 %a, 0
@@ -584,7 +584,7 @@ define i32 @f29(i64 %base, i64 %index, i32 *%dest) {
 entry:
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i32 *
-  %res = load i32 *%ptr
+  %res = load i32 , i32 *%ptr
   %cmp = icmp sle i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
@@ -606,7 +606,7 @@ entry:
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 100000
   %ptr = inttoptr i64 %add2 to i32 *
-  %res = load i32 *%ptr
+  %res = load i32 , i32 *%ptr
   %cmp = icmp sle i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
@@ -627,7 +627,7 @@ define i64 @f31(i64 %base, i64 %index, i64 *%dest) {
 entry:
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i64 *
-  %res = load i64 *%ptr
+  %res = load i64 , i64 *%ptr
   %cmp = icmp sge i64 %res, 0
   br i1 %cmp, label %exit, label %store
 
@@ -648,7 +648,7 @@ define i64 @f32(i64 %base, i64 %index, i64 *%dest) {
 entry:
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i32 *
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %res = sext i32 %val to i64
   %cmp = icmp sgt i64 %res, 0
   br i1 %cmp, label %exit, label %store
@@ -853,7 +853,7 @@ define i32 @f41(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-NEXT: jne .L{{.*}}
 ; CHECK: br %r14
 entry:
-  %cur = load i32 *%dest
+  %cur = load i32 , i32 *%dest
   %res = sub i32 %a, %cur
   %cmp = icmp ne i32 %a, %cur
   br i1 %cmp, label %exit, label %store
@@ -875,7 +875,7 @@ define i64 @f42(i64 %base, i64 %index, i64 *%dest) {
 entry:
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i32 *
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   %res = sext i32 %val to i64
   %cmp = icmp sgt i32 %val, 0
   br i1 %cmp, label %exit, label %store
diff --git a/test/CodeGen/SystemZ/int-cmp-45.ll b/test/CodeGen/SystemZ/int-cmp-45.ll
index c9affa672d54..e5474fa4863d 100644
--- a/test/CodeGen/SystemZ/int-cmp-45.ll
+++ b/test/CodeGen/SystemZ/int-cmp-45.ll
@@ -12,7 +12,7 @@ define i32 @f1(i32 %a, i32 %b, i32 *%cptr) {
 ; CHECK: br %r14
   %add = add i32 %a, 1000000
   %cmp = icmp eq i32 %add, 0
-  %c = load i32 *%cptr
+  %c = load i32 , i32 *%cptr
   %arg = select i1 %cmp, i32 %c, i32 %b
   call void asm sideeffect "blah $0", "{r3}"(i32 %arg)
   ret i32 %add
@@ -26,7 +26,7 @@ define i32 @f2(i32 %a, i32 %b, i32 *%cptr) {
 ; CHECK: br %r14
   %add = add i32 %a, 1000000
   %cmp = icmp eq i32 %add, 0
-  %c = load i32 *%cptr
+  %c = load i32 , i32 *%cptr
   %newval = select i1 %cmp, i32 %b, i32 %c
   store i32 %newval, i32 *%cptr
   ret i32 %add
@@ -53,7 +53,7 @@ define i32 @f4(i32 %a, i32 %b, i32 *%cptr) {
 ; CHECK: br %r14
   %add = add i32 %a, 1000000
   %cmp = icmp eq i32 %add, 0
-  %c = load i32 *%cptr
+  %c = load i32 , i32 *%cptr
   %arg = select i1 %cmp, i32 %b, i32 %c
   call void asm sideeffect "blah $0", "{r3}"(i32 %arg)
   ret i32 %add
@@ -67,7 +67,7 @@ define i32 @f5(i32 %a, i32 %b, i32 *%cptr) {
 ; CHECK: br %r14
   %add = add i32 %a, 1000000
   %cmp = icmp eq i32 %add, 0
-  %c = load i32 *%cptr
+  %c = load i32 , i32 *%cptr
   %newval = select i1 %cmp, i32 %c, i32 %b
   store i32 %newval, i32 *%cptr
   ret i32 %add
@@ -94,7 +94,7 @@ define i32 @f7(i32 %a, i32 %b, i32 *%cptr) {
 ; CHECK: br %r14
   %add = add i32 %a, 1000000
   %cmp = icmp ne i32 %add, 0
-  %c = load i32 *%cptr
+  %c = load i32 , i32 *%cptr
   %arg = select i1 %cmp, i32 %b, i32 %c
   call void asm sideeffect "blah $0", "{r3}"(i32 %arg)
   ret i32 %add
@@ -108,7 +108,7 @@ define i32 @f8(i32 %a, i32 %b, i32 *%cptr) {
 ; CHECK: br %r14
   %add = add i32 %a, 1000000
   %cmp = icmp ne i32 %add, 0
-  %c = load i32 *%cptr
+  %c = load i32 , i32 *%cptr
   %newval = select i1 %cmp, i32 %c, i32 %b
   store i32 %newval, i32 *%cptr
   ret i32 %add
diff --git a/test/CodeGen/SystemZ/int-cmp-47.ll b/test/CodeGen/SystemZ/int-cmp-47.ll
index 038a25b2a6ed..274350d24de1 100644
--- a/test/CodeGen/SystemZ/int-cmp-47.ll
+++ b/test/CodeGen/SystemZ/int-cmp-47.ll
@@ -309,7 +309,8 @@ exit:
 define void @f17(i64 %a) {
 ; CHECK-LABEL: f17:
 ; CHECK-NOT: tmhh
-; CHECK: llihh {{%r[0-5]}}, 49151
+; CHECK: srlg [[REG:%r[0-5]]], %r2, 48
+; CHECK: cgfi [[REG]], 49151
 ; CHECK-NOT: tmhh
 ; CHECK: br %r14
 entry:
diff --git a/test/CodeGen/SystemZ/int-cmp-48.ll b/test/CodeGen/SystemZ/int-cmp-48.ll
index d7c6370a2323..e26694753e7c 100644
--- a/test/CodeGen/SystemZ/int-cmp-48.ll
+++ b/test/CodeGen/SystemZ/int-cmp-48.ll
@@ -11,7 +11,7 @@ define void @f1(i8 *%src) {
 ; CHECK: je {{\.L.*}}
 ; CHECK: br %r14
 entry:
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   %and = and i8 %byte, 1
   %cmp = icmp eq i8 %and, 0
   br i1 %cmp, label %exit, label %store
@@ -34,7 +34,7 @@ define void @f2(i8 *%src) {
 ; CHECK: je {{\.L.*}}
 ; CHECK: br %r14
 entry:
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   store i8 0, i8 *%src
   %and = and i8 %byte, 1
   %cmp = icmp eq i8 %and, 0
@@ -54,7 +54,7 @@ define double @f3(i8 *%src, double %a, double %b) {
 ; CHECK: tm 0(%r2), 1
 ; CHECK: je {{\.L.*}}
 ; CHECK: br %r14
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   %and = and i8 %byte, 1
   %cmp = icmp eq i8 %and, 0
   %res = select i1 %cmp, double %b, double %a
@@ -68,7 +68,7 @@ define double @f4(i8 *%src, double %a, double %b) {
 ; CHECK: je {{\.L.*}}
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: br %r14
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   %and = and i8 %byte, 1
   %cmp = icmp eq i8 %and, 0
   %res = select i1 %cmp, double %b, double %a
@@ -82,7 +82,7 @@ define double @f5(i8 *%src, double %a, double %b) {
 ; CHECK: tm 0(%r2), 1
 ; CHECK: jne {{\.L.*}}
 ; CHECK: br %r14
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   %and = and i8 %byte, 1
   %cmp = icmp ne i8 %and, 0
   %res = select i1 %cmp, double %b, double %a
@@ -95,7 +95,7 @@ define double @f6(i8 *%src, double %a, double %b) {
 ; CHECK: tm 0(%r2), 254
 ; CHECK: jo {{\.L.*}}
 ; CHECK: br %r14
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   %and = and i8 %byte, 254
   %cmp = icmp eq i8 %and, 254
   %res = select i1 %cmp, double %b, double %a
@@ -108,7 +108,7 @@ define double @f7(i8 *%src, double %a, double %b) {
 ; CHECK: tm 0(%r2), 254
 ; CHECK: jno {{\.L.*}}
 ; CHECK: br %r14
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   %and = and i8 %byte, 254
   %cmp = icmp ne i8 %and, 254
   %res = select i1 %cmp, double %b, double %a
@@ -123,7 +123,7 @@ define double @f8(i8 *%src, double %a, double %b) {
 ; CHECK: tmll [[REG]], 3
 ; CHECK: jh {{\.L.*}}
 ; CHECK: br %r14
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   %and = and i8 %byte, 3
   %cmp = icmp eq i8 %and, 2
   %res = select i1 %cmp, double %b, double %a
@@ -137,7 +137,7 @@ define double @f9(i8 *%src, double %a, double %b) {
 ; CHECK: tmll [[REG]], 3
 ; CHECK: jl {{\.L.*}}
 ; CHECK: br %r14
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   %and = and i8 %byte, 3
   %cmp = icmp eq i8 %and, 1
   %res = select i1 %cmp, double %b, double %a
@@ -150,8 +150,8 @@ define double @f10(i8 *%src, double %a, double %b) {
 ; CHECK: tm 4095(%r2), 1
 ; CHECK: je {{\.L.*}}
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4095
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 4095
+  %byte = load i8 , i8 *%ptr
   %and = and i8 %byte, 1
   %cmp = icmp eq i8 %and, 0
   %res = select i1 %cmp, double %b, double %a
@@ -164,8 +164,8 @@ define double @f11(i8 *%src, double %a, double %b) {
 ; CHECK: tmy 4096(%r2), 1
 ; CHECK: je {{\.L.*}}
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4096
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 4096
+  %byte = load i8 , i8 *%ptr
   %and = and i8 %byte, 1
   %cmp = icmp eq i8 %and, 0
   %res = select i1 %cmp, double %b, double %a
@@ -178,8 +178,8 @@ define double @f12(i8 *%src, double %a, double %b) {
 ; CHECK: tmy 524287(%r2), 1
 ; CHECK: je {{\.L.*}}
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524287
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524287
+  %byte = load i8 , i8 *%ptr
   %and = and i8 %byte, 1
   %cmp = icmp eq i8 %and, 0
   %res = select i1 %cmp, double %b, double %a
@@ -193,8 +193,8 @@ define double @f13(i8 *%src, double %a, double %b) {
 ; CHECK: tm 0(%r2), 1
 ; CHECK: je {{\.L.*}}
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524288
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524288
+  %byte = load i8 , i8 *%ptr
   %and = and i8 %byte, 1
   %cmp = icmp eq i8 %and, 0
   %res = select i1 %cmp, double %b, double %a
@@ -207,8 +207,8 @@ define double @f14(i8 *%src, double %a, double %b) {
 ; CHECK: tmy -524288(%r2), 1
 ; CHECK: je {{\.L.*}}
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524288
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524288
+  %byte = load i8 , i8 *%ptr
   %and = and i8 %byte, 1
   %cmp = icmp eq i8 %and, 0
   %res = select i1 %cmp, double %b, double %a
@@ -222,8 +222,8 @@ define double @f15(i8 *%src, double %a, double %b) {
 ; CHECK: tm 0(%r2), 1
 ; CHECK: je {{\.L.*}}
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524289
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524289
+  %byte = load i8 , i8 *%ptr
   %and = and i8 %byte, 1
   %cmp = icmp eq i8 %and, 0
   %res = select i1 %cmp, double %b, double %a
@@ -236,8 +236,8 @@ define double @f16(i8 *%src, i64 %index, double %a, double %b) {
 ; CHECK: tm 0({{%r[1-5]}}), 1
 ; CHECK: je {{\.L.*}}
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 %index
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 %index
+  %byte = load i8 , i8 *%ptr
   %and = and i8 %byte, 1
   %cmp = icmp eq i8 %and, 0
   %res = select i1 %cmp, double %b, double %a
diff --git a/test/CodeGen/SystemZ/int-cmp-50.ll b/test/CodeGen/SystemZ/int-cmp-50.ll
new file mode 100644
index 000000000000..287ac2c49a78
--- /dev/null
+++ b/test/CodeGen/SystemZ/int-cmp-50.ll
@@ -0,0 +1,30 @@
+; Verify that we do not crash on always-true conditions
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -O0
+;
+; This test was compiled using clang -O0 from the following source code:
+;
+; int test(unsigned long x)
+; {
+;   return x >= 0 && x <= 15;
+; }
+
+define signext i32 @test(i64 %x) {
+entry:
+  %x.addr = alloca i64, align 8
+  store i64 %x, i64* %x.addr, align 8
+  %0 = load i64, i64* %x.addr, align 8
+  %cmp = icmp uge i64 %0, 0
+  br i1 %cmp, label %land.rhs, label %land.end
+
+land.rhs:                                         ; preds = %entry
+  %1 = load i64, i64* %x.addr, align 8
+  %cmp1 = icmp ule i64 %1, 15
+  br label %land.end
+
+land.end:                                         ; preds = %land.rhs, %entry
+  %2 = phi i1 [ false, %entry ], [ %cmp1, %land.rhs ]
+  %land.ext = zext i1 %2 to i32
+  ret i32 %land.ext
+}
+
diff --git a/test/CodeGen/SystemZ/int-const-03.ll b/test/CodeGen/SystemZ/int-const-03.ll
index af1cef2c138a..7352ea32e76a 100644
--- a/test/CodeGen/SystemZ/int-const-03.ll
+++ b/test/CodeGen/SystemZ/int-const-03.ll
@@ -70,7 +70,7 @@ define void @f8(i8 *%src) {
 ; CHECK-LABEL: f8:
 ; CHECK: mvi 4095(%r2), 42
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4095
+  %ptr = getelementptr i8, i8 *%src, i64 4095
   store i8 42, i8 *%ptr
   ret void
 }
@@ -80,7 +80,7 @@ define void @f9(i8 *%src) {
 ; CHECK-LABEL: f9:
 ; CHECK: mviy 4096(%r2), 42
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4096
+  %ptr = getelementptr i8, i8 *%src, i64 4096
   store i8 42, i8 *%ptr
   ret void
 }
@@ -90,7 +90,7 @@ define void @f10(i8 *%src) {
 ; CHECK-LABEL: f10:
 ; CHECK: mviy 524287(%r2), 42
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524287
+  %ptr = getelementptr i8, i8 *%src, i64 524287
   store i8 42, i8 *%ptr
   ret void
 }
@@ -102,7 +102,7 @@ define void @f11(i8 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: mvi 0(%r2), 42
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524288
+  %ptr = getelementptr i8, i8 *%src, i64 524288
   store i8 42, i8 *%ptr
   ret void
 }
@@ -112,7 +112,7 @@ define void @f12(i8 *%src) {
 ; CHECK-LABEL: f12:
 ; CHECK: mviy -1(%r2), 42
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -1
+  %ptr = getelementptr i8, i8 *%src, i64 -1
   store i8 42, i8 *%ptr
   ret void
 }
@@ -122,7 +122,7 @@ define void @f13(i8 *%src) {
 ; CHECK-LABEL: f13:
 ; CHECK: mviy -524288(%r2), 42
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524288
+  %ptr = getelementptr i8, i8 *%src, i64 -524288
   store i8 42, i8 *%ptr
   ret void
 }
@@ -134,7 +134,7 @@ define void @f14(i8 *%src) {
 ; CHECK: agfi %r2, -524289
 ; CHECK: mvi 0(%r2), 42
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524289
+  %ptr = getelementptr i8, i8 *%src, i64 -524289
   store i8 42, i8 *%ptr
   ret void
 }
diff --git a/test/CodeGen/SystemZ/int-const-04.ll b/test/CodeGen/SystemZ/int-const-04.ll
index aced50b5601b..fd943991196e 100644
--- a/test/CodeGen/SystemZ/int-const-04.ll
+++ b/test/CodeGen/SystemZ/int-const-04.ll
@@ -70,7 +70,7 @@ define void @f8(i16 *%a) {
 ; CHECK-LABEL: f8:
 ; CHECK: mvhhi 4094(%r2), 42
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%a, i64 2047
+  %ptr = getelementptr i16, i16 *%a, i64 2047
   store i16 42, i16 *%ptr
   ret void
 }
@@ -82,7 +82,7 @@ define void @f9(i16 *%a) {
 ; CHECK: lhi [[TMP:%r[0-5]]], 42
 ; CHECK: sthy [[TMP]], 4096(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%a, i64 2048
+  %ptr = getelementptr i16, i16 *%a, i64 2048
   store i16 42, i16 *%ptr
   ret void
 }
@@ -93,7 +93,7 @@ define void @f10(i16 *%a) {
 ; CHECK: lhi [[TMP:%r[0-5]]], 42
 ; CHECK: sthy [[TMP]], -2(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%a, i64 -1
+  %ptr = getelementptr i16, i16 *%a, i64 -1
   store i16 42, i16 *%ptr
   ret void
 }
diff --git a/test/CodeGen/SystemZ/int-const-05.ll b/test/CodeGen/SystemZ/int-const-05.ll
index 98d6851c197d..c7b455168990 100644
--- a/test/CodeGen/SystemZ/int-const-05.ll
+++ b/test/CodeGen/SystemZ/int-const-05.ll
@@ -61,7 +61,7 @@ define void @f7(i32 *%a) {
 ; CHECK-LABEL: f7:
 ; CHECK: mvhi 4092(%r2), 42
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%a, i64 1023
+  %ptr = getelementptr i32, i32 *%a, i64 1023
   store i32 42, i32 *%ptr
   ret void
 }
@@ -72,7 +72,7 @@ define void @f8(i32 *%a) {
 ; CHECK: lhi [[TMP:%r[0-5]]], 42
 ; CHECK: sty [[TMP]], 4096(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%a, i64 1024
+  %ptr = getelementptr i32, i32 *%a, i64 1024
   store i32 42, i32 *%ptr
   ret void
 }
@@ -83,7 +83,7 @@ define void @f9(i32 *%a) {
 ; CHECK: lhi [[TMP:%r[0-5]]], 42
 ; CHECK: sty [[TMP]], -4(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%a, i64 -1
+  %ptr = getelementptr i32, i32 *%a, i64 -1
   store i32 42, i32 *%ptr
   ret void
 }
diff --git a/test/CodeGen/SystemZ/int-const-06.ll b/test/CodeGen/SystemZ/int-const-06.ll
index cf07c665dde7..fc47a04094b5 100644
--- a/test/CodeGen/SystemZ/int-const-06.ll
+++ b/test/CodeGen/SystemZ/int-const-06.ll
@@ -61,7 +61,7 @@ define void @f7(i64 *%a) {
 ; CHECK-LABEL: f7:
 ; CHECK: mvghi 4088(%r2), 42
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%a, i64 511
+  %ptr = getelementptr i64, i64 *%a, i64 511
   store i64 42, i64 *%ptr
   ret void
 }
@@ -73,7 +73,7 @@ define void @f8(i64 *%a) {
 ; CHECK: lghi [[TMP:%r[0-5]]], 42
 ; CHECK: stg [[TMP]], 4096(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%a, i64 512
+  %ptr = getelementptr i64, i64 *%a, i64 512
   store i64 42, i64 *%ptr
   ret void
 }
@@ -84,7 +84,7 @@ define void @f9(i64 *%a) {
 ; CHECK: lghi [[TMP:%r[0-5]]], 42
 ; CHECK: stg [[TMP]], -8(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%a, i64 -1
+  %ptr = getelementptr i64, i64 *%a, i64 -1
   store i64 42, i64 *%ptr
   ret void
 }
diff --git a/test/CodeGen/SystemZ/int-conv-01.ll b/test/CodeGen/SystemZ/int-conv-01.ll
index e5c411cdec1d..70ef78a06110 100644
--- a/test/CodeGen/SystemZ/int-conv-01.ll
+++ b/test/CodeGen/SystemZ/int-conv-01.ll
@@ -27,7 +27,7 @@ define i32 @f3(i8 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: lb %r2, 0(%r2)
 ; CHECK: br %r14
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   %ext = sext i8 %byte to i32
   ret i32 %ext
 }
@@ -37,8 +37,8 @@ define i32 @f4(i8 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: lb %r2, 524287(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524287
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524287
+  %byte = load i8 , i8 *%ptr
   %ext = sext i8 %byte to i32
   ret i32 %ext
 }
@@ -50,8 +50,8 @@ define i32 @f5(i8 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: lb %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524288
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524288
+  %byte = load i8 , i8 *%ptr
   %ext = sext i8 %byte to i32
   ret i32 %ext
 }
@@ -61,8 +61,8 @@ define i32 @f6(i8 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: lb %r2, -1(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -1
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -1
+  %byte = load i8 , i8 *%ptr
   %ext = sext i8 %byte to i32
   ret i32 %ext
 }
@@ -72,8 +72,8 @@ define i32 @f7(i8 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: lb %r2, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524288
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524288
+  %byte = load i8 , i8 *%ptr
   %ext = sext i8 %byte to i32
   ret i32 %ext
 }
@@ -85,8 +85,8 @@ define i32 @f8(i8 *%src) {
 ; CHECK: agfi %r2, -524289
 ; CHECK: lb %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524289
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524289
+  %byte = load i8 , i8 *%ptr
   %ext = sext i8 %byte to i32
   ret i32 %ext
 }
@@ -99,7 +99,7 @@ define i32 @f9(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i8 *
-  %byte = load i8 *%ptr
+  %byte = load i8 , i8 *%ptr
   %ext = sext i8 %byte to i32
   ret i32 %ext
 }
@@ -110,22 +110,22 @@ define void @f10(i32 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK: lb {{%r[0-9]+}}, 16{{[37]}}(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile i32 *%ptr
-  %val1 = load volatile i32 *%ptr
-  %val2 = load volatile i32 *%ptr
-  %val3 = load volatile i32 *%ptr
-  %val4 = load volatile i32 *%ptr
-  %val5 = load volatile i32 *%ptr
-  %val6 = load volatile i32 *%ptr
-  %val7 = load volatile i32 *%ptr
-  %val8 = load volatile i32 *%ptr
-  %val9 = load volatile i32 *%ptr
-  %val10 = load volatile i32 *%ptr
-  %val11 = load volatile i32 *%ptr
-  %val12 = load volatile i32 *%ptr
-  %val13 = load volatile i32 *%ptr
-  %val14 = load volatile i32 *%ptr
-  %val15 = load volatile i32 *%ptr
+  %val0 = load volatile i32 , i32 *%ptr
+  %val1 = load volatile i32 , i32 *%ptr
+  %val2 = load volatile i32 , i32 *%ptr
+  %val3 = load volatile i32 , i32 *%ptr
+  %val4 = load volatile i32 , i32 *%ptr
+  %val5 = load volatile i32 , i32 *%ptr
+  %val6 = load volatile i32 , i32 *%ptr
+  %val7 = load volatile i32 , i32 *%ptr
+  %val8 = load volatile i32 , i32 *%ptr
+  %val9 = load volatile i32 , i32 *%ptr
+  %val10 = load volatile i32 , i32 *%ptr
+  %val11 = load volatile i32 , i32 *%ptr
+  %val12 = load volatile i32 , i32 *%ptr
+  %val13 = load volatile i32 , i32 *%ptr
+  %val14 = load volatile i32 , i32 *%ptr
+  %val15 = load volatile i32 , i32 *%ptr
 
   %trunc0 = trunc i32 %val0 to i8
   %trunc1 = trunc i32 %val1 to i8
diff --git a/test/CodeGen/SystemZ/int-conv-02.ll b/test/CodeGen/SystemZ/int-conv-02.ll
index dd7760d08cf5..5b248cce1efc 100644
--- a/test/CodeGen/SystemZ/int-conv-02.ll
+++ b/test/CodeGen/SystemZ/int-conv-02.ll
@@ -37,7 +37,7 @@ define i32 @f4(i8 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: llc %r2, 0(%r2)
 ; CHECK: br %r14
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   %ext = zext i8 %byte to i32
   ret i32 %ext
 }
@@ -47,8 +47,8 @@ define i32 @f5(i8 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: llc %r2, 524287(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524287
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524287
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i32
   ret i32 %ext
 }
@@ -60,8 +60,8 @@ define i32 @f6(i8 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: llc %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524288
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524288
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i32
   ret i32 %ext
 }
@@ -71,8 +71,8 @@ define i32 @f7(i8 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: llc %r2, -1(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -1
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -1
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i32
   ret i32 %ext
 }
@@ -82,8 +82,8 @@ define i32 @f8(i8 *%src) {
 ; CHECK-LABEL: f8:
 ; CHECK: llc %r2, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524288
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524288
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i32
   ret i32 %ext
 }
@@ -95,8 +95,8 @@ define i32 @f9(i8 *%src) {
 ; CHECK: agfi %r2, -524289
 ; CHECK: llc %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524289
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524289
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i32
   ret i32 %ext
 }
@@ -109,7 +109,7 @@ define i32 @f10(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i8 *
-  %byte = load i8 *%ptr
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i32
   ret i32 %ext
 }
@@ -120,22 +120,22 @@ define void @f11(i32 *%ptr) {
 ; CHECK-LABEL: f11:
 ; CHECK: llc {{%r[0-9]+}}, 16{{[37]}}(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile i32 *%ptr
-  %val1 = load volatile i32 *%ptr
-  %val2 = load volatile i32 *%ptr
-  %val3 = load volatile i32 *%ptr
-  %val4 = load volatile i32 *%ptr
-  %val5 = load volatile i32 *%ptr
-  %val6 = load volatile i32 *%ptr
-  %val7 = load volatile i32 *%ptr
-  %val8 = load volatile i32 *%ptr
-  %val9 = load volatile i32 *%ptr
-  %val10 = load volatile i32 *%ptr
-  %val11 = load volatile i32 *%ptr
-  %val12 = load volatile i32 *%ptr
-  %val13 = load volatile i32 *%ptr
-  %val14 = load volatile i32 *%ptr
-  %val15 = load volatile i32 *%ptr
+  %val0 = load volatile i32 , i32 *%ptr
+  %val1 = load volatile i32 , i32 *%ptr
+  %val2 = load volatile i32 , i32 *%ptr
+  %val3 = load volatile i32 , i32 *%ptr
+  %val4 = load volatile i32 , i32 *%ptr
+  %val5 = load volatile i32 , i32 *%ptr
+  %val6 = load volatile i32 , i32 *%ptr
+  %val7 = load volatile i32 , i32 *%ptr
+  %val8 = load volatile i32 , i32 *%ptr
+  %val9 = load volatile i32 , i32 *%ptr
+  %val10 = load volatile i32 , i32 *%ptr
+  %val11 = load volatile i32 , i32 *%ptr
+  %val12 = load volatile i32 , i32 *%ptr
+  %val13 = load volatile i32 , i32 *%ptr
+  %val14 = load volatile i32 , i32 *%ptr
+  %val15 = load volatile i32 , i32 *%ptr
 
   %trunc0 = trunc i32 %val0 to i8
   %trunc1 = trunc i32 %val1 to i8
diff --git a/test/CodeGen/SystemZ/int-conv-03.ll b/test/CodeGen/SystemZ/int-conv-03.ll
index cad9581296a4..e621bcd69dee 100644
--- a/test/CodeGen/SystemZ/int-conv-03.ll
+++ b/test/CodeGen/SystemZ/int-conv-03.ll
@@ -27,7 +27,7 @@ define i64 @f3(i8 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: lgb %r2, 0(%r2)
 ; CHECK: br %r14
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   %ext = sext i8 %byte to i64
   ret i64 %ext
 }
@@ -37,8 +37,8 @@ define i64 @f4(i8 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: lgb %r2, 524287(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524287
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524287
+  %byte = load i8 , i8 *%ptr
   %ext = sext i8 %byte to i64
   ret i64 %ext
 }
@@ -50,8 +50,8 @@ define i64 @f5(i8 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: lgb %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524288
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524288
+  %byte = load i8 , i8 *%ptr
   %ext = sext i8 %byte to i64
   ret i64 %ext
 }
@@ -61,8 +61,8 @@ define i64 @f6(i8 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: lgb %r2, -1(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -1
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -1
+  %byte = load i8 , i8 *%ptr
   %ext = sext i8 %byte to i64
   ret i64 %ext
 }
@@ -72,8 +72,8 @@ define i64 @f7(i8 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: lgb %r2, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524288
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524288
+  %byte = load i8 , i8 *%ptr
   %ext = sext i8 %byte to i64
   ret i64 %ext
 }
@@ -85,8 +85,8 @@ define i64 @f8(i8 *%src) {
 ; CHECK: agfi %r2, -524289
 ; CHECK: lgb %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524289
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524289
+  %byte = load i8 , i8 *%ptr
   %ext = sext i8 %byte to i64
   ret i64 %ext
 }
@@ -99,7 +99,7 @@ define i64 @f9(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i8 *
-  %byte = load i8 *%ptr
+  %byte = load i8 , i8 *%ptr
   %ext = sext i8 %byte to i64
   ret i64 %ext
 }
@@ -110,22 +110,22 @@ define void @f10(i64 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK: lgb {{%r[0-9]+}}, 167(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile i64 *%ptr
-  %val1 = load volatile i64 *%ptr
-  %val2 = load volatile i64 *%ptr
-  %val3 = load volatile i64 *%ptr
-  %val4 = load volatile i64 *%ptr
-  %val5 = load volatile i64 *%ptr
-  %val6 = load volatile i64 *%ptr
-  %val7 = load volatile i64 *%ptr
-  %val8 = load volatile i64 *%ptr
-  %val9 = load volatile i64 *%ptr
-  %val10 = load volatile i64 *%ptr
-  %val11 = load volatile i64 *%ptr
-  %val12 = load volatile i64 *%ptr
-  %val13 = load volatile i64 *%ptr
-  %val14 = load volatile i64 *%ptr
-  %val15 = load volatile i64 *%ptr
+  %val0 = load volatile i64 , i64 *%ptr
+  %val1 = load volatile i64 , i64 *%ptr
+  %val2 = load volatile i64 , i64 *%ptr
+  %val3 = load volatile i64 , i64 *%ptr
+  %val4 = load volatile i64 , i64 *%ptr
+  %val5 = load volatile i64 , i64 *%ptr
+  %val6 = load volatile i64 , i64 *%ptr
+  %val7 = load volatile i64 , i64 *%ptr
+  %val8 = load volatile i64 , i64 *%ptr
+  %val9 = load volatile i64 , i64 *%ptr
+  %val10 = load volatile i64 , i64 *%ptr
+  %val11 = load volatile i64 , i64 *%ptr
+  %val12 = load volatile i64 , i64 *%ptr
+  %val13 = load volatile i64 , i64 *%ptr
+  %val14 = load volatile i64 , i64 *%ptr
+  %val15 = load volatile i64 , i64 *%ptr
 
   %trunc0 = trunc i64 %val0 to i8
   %trunc1 = trunc i64 %val1 to i8
diff --git a/test/CodeGen/SystemZ/int-conv-04.ll b/test/CodeGen/SystemZ/int-conv-04.ll
index 1c6be7b6e8a4..a0f5d63d2605 100644
--- a/test/CodeGen/SystemZ/int-conv-04.ll
+++ b/test/CodeGen/SystemZ/int-conv-04.ll
@@ -36,7 +36,7 @@ define i64 @f4(i8 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   %ext = zext i8 %byte to i64
   ret i64 %ext
 }
@@ -46,8 +46,8 @@ define i64 @f5(i8 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: llgc %r2, 524287(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524287
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524287
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i64
   ret i64 %ext
 }
@@ -59,8 +59,8 @@ define i64 @f6(i8 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524288
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524288
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i64
   ret i64 %ext
 }
@@ -70,8 +70,8 @@ define i64 @f7(i8 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: llgc %r2, -1(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -1
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -1
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i64
   ret i64 %ext
 }
@@ -81,8 +81,8 @@ define i64 @f8(i8 *%src) {
 ; CHECK-LABEL: f8:
 ; CHECK: llgc %r2, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524288
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524288
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i64
   ret i64 %ext
 }
@@ -94,8 +94,8 @@ define i64 @f9(i8 *%src) {
 ; CHECK: agfi %r2, -524289
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524289
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524289
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i64
   ret i64 %ext
 }
@@ -108,7 +108,7 @@ define i64 @f10(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i8 *
-  %byte = load i8 *%ptr
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i64
   ret i64 %ext
 }
@@ -119,22 +119,22 @@ define void @f11(i64 *%ptr) {
 ; CHECK-LABEL: f11:
 ; CHECK: llgc {{%r[0-9]+}}, 167(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile i64 *%ptr
-  %val1 = load volatile i64 *%ptr
-  %val2 = load volatile i64 *%ptr
-  %val3 = load volatile i64 *%ptr
-  %val4 = load volatile i64 *%ptr
-  %val5 = load volatile i64 *%ptr
-  %val6 = load volatile i64 *%ptr
-  %val7 = load volatile i64 *%ptr
-  %val8 = load volatile i64 *%ptr
-  %val9 = load volatile i64 *%ptr
-  %val10 = load volatile i64 *%ptr
-  %val11 = load volatile i64 *%ptr
-  %val12 = load volatile i64 *%ptr
-  %val13 = load volatile i64 *%ptr
-  %val14 = load volatile i64 *%ptr
-  %val15 = load volatile i64 *%ptr
+  %val0 = load volatile i64 , i64 *%ptr
+  %val1 = load volatile i64 , i64 *%ptr
+  %val2 = load volatile i64 , i64 *%ptr
+  %val3 = load volatile i64 , i64 *%ptr
+  %val4 = load volatile i64 , i64 *%ptr
+  %val5 = load volatile i64 , i64 *%ptr
+  %val6 = load volatile i64 , i64 *%ptr
+  %val7 = load volatile i64 , i64 *%ptr
+  %val8 = load volatile i64 , i64 *%ptr
+  %val9 = load volatile i64 , i64 *%ptr
+  %val10 = load volatile i64 , i64 *%ptr
+  %val11 = load volatile i64 , i64 *%ptr
+  %val12 = load volatile i64 , i64 *%ptr
+  %val13 = load volatile i64 , i64 *%ptr
+  %val14 = load volatile i64 , i64 *%ptr
+  %val15 = load volatile i64 , i64 *%ptr
 
   %trunc0 = trunc i64 %val0 to i8
   %trunc1 = trunc i64 %val1 to i8
diff --git a/test/CodeGen/SystemZ/int-conv-05.ll b/test/CodeGen/SystemZ/int-conv-05.ll
index 5eade93ac584..55299529c480 100644
--- a/test/CodeGen/SystemZ/int-conv-05.ll
+++ b/test/CodeGen/SystemZ/int-conv-05.ll
@@ -27,7 +27,7 @@ define i32 @f3(i16 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: br %r14
-  %half = load i16 *%src
+  %half = load i16 , i16 *%src
   %ext = sext i16 %half to i32
   ret i32 %ext
 }
@@ -37,8 +37,8 @@ define i32 @f4(i16 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: lh %r2, 4094(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 2047
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 2047
+  %half = load i16 , i16 *%ptr
   %ext = sext i16 %half to i32
   ret i32 %ext
 }
@@ -48,8 +48,8 @@ define i32 @f5(i16 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: lhy %r2, 4096(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 2048
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 2048
+  %half = load i16 , i16 *%ptr
   %ext = sext i16 %half to i32
   ret i32 %ext
 }
@@ -59,8 +59,8 @@ define i32 @f6(i16 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: lhy %r2, 524286(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262143
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262143
+  %half = load i16 , i16 *%ptr
   %ext = sext i16 %half to i32
   ret i32 %ext
 }
@@ -72,8 +72,8 @@ define i32 @f7(i16 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262144
+  %half = load i16 , i16 *%ptr
   %ext = sext i16 %half to i32
   ret i32 %ext
 }
@@ -83,8 +83,8 @@ define i32 @f8(i16 *%src) {
 ; CHECK-LABEL: f8:
 ; CHECK: lhy %r2, -2(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -1
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -1
+  %half = load i16 , i16 *%ptr
   %ext = sext i16 %half to i32
   ret i32 %ext
 }
@@ -94,8 +94,8 @@ define i32 @f9(i16 *%src) {
 ; CHECK-LABEL: f9:
 ; CHECK: lhy %r2, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262144
+  %half = load i16 , i16 *%ptr
   %ext = sext i16 %half to i32
   ret i32 %ext
 }
@@ -107,8 +107,8 @@ define i32 @f10(i16 *%src) {
 ; CHECK: agfi %r2, -524290
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262145
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262145
+  %half = load i16 , i16 *%ptr
   %ext = sext i16 %half to i32
   ret i32 %ext
 }
@@ -121,7 +121,7 @@ define i32 @f11(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4094
   %ptr = inttoptr i64 %add2 to i16 *
-  %half = load i16 *%ptr
+  %half = load i16 , i16 *%ptr
   %ext = sext i16 %half to i32
   ret i32 %ext
 }
@@ -134,7 +134,7 @@ define i32 @f12(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i16 *
-  %half = load i16 *%ptr
+  %half = load i16 , i16 *%ptr
   %ext = sext i16 %half to i32
   ret i32 %ext
 }
@@ -145,22 +145,22 @@ define void @f13(i32 *%ptr) {
 ; CHECK-LABEL: f13:
 ; CHECK: lh {{%r[0-9]+}}, 16{{[26]}}(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile i32 *%ptr
-  %val1 = load volatile i32 *%ptr
-  %val2 = load volatile i32 *%ptr
-  %val3 = load volatile i32 *%ptr
-  %val4 = load volatile i32 *%ptr
-  %val5 = load volatile i32 *%ptr
-  %val6 = load volatile i32 *%ptr
-  %val7 = load volatile i32 *%ptr
-  %val8 = load volatile i32 *%ptr
-  %val9 = load volatile i32 *%ptr
-  %val10 = load volatile i32 *%ptr
-  %val11 = load volatile i32 *%ptr
-  %val12 = load volatile i32 *%ptr
-  %val13 = load volatile i32 *%ptr
-  %val14 = load volatile i32 *%ptr
-  %val15 = load volatile i32 *%ptr
+  %val0 = load volatile i32 , i32 *%ptr
+  %val1 = load volatile i32 , i32 *%ptr
+  %val2 = load volatile i32 , i32 *%ptr
+  %val3 = load volatile i32 , i32 *%ptr
+  %val4 = load volatile i32 , i32 *%ptr
+  %val5 = load volatile i32 , i32 *%ptr
+  %val6 = load volatile i32 , i32 *%ptr
+  %val7 = load volatile i32 , i32 *%ptr
+  %val8 = load volatile i32 , i32 *%ptr
+  %val9 = load volatile i32 , i32 *%ptr
+  %val10 = load volatile i32 , i32 *%ptr
+  %val11 = load volatile i32 , i32 *%ptr
+  %val12 = load volatile i32 , i32 *%ptr
+  %val13 = load volatile i32 , i32 *%ptr
+  %val14 = load volatile i32 , i32 *%ptr
+  %val15 = load volatile i32 , i32 *%ptr
 
   %trunc0 = trunc i32 %val0 to i16
   %trunc1 = trunc i32 %val1 to i16
diff --git a/test/CodeGen/SystemZ/int-conv-06.ll b/test/CodeGen/SystemZ/int-conv-06.ll
index 33860d12270f..99ff84efbe76 100644
--- a/test/CodeGen/SystemZ/int-conv-06.ll
+++ b/test/CodeGen/SystemZ/int-conv-06.ll
@@ -37,7 +37,7 @@ define i32 @f4(i16 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: llh %r2, 0(%r2)
 ; CHECK: br %r14
-  %half = load i16 *%src
+  %half = load i16 , i16 *%src
   %ext = zext i16 %half to i32
   ret i32 %ext
 }
@@ -47,8 +47,8 @@ define i32 @f5(i16 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: llh %r2, 524286(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262143
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262143
+  %half = load i16 , i16 *%ptr
   %ext = zext i16 %half to i32
   ret i32 %ext
 }
@@ -60,8 +60,8 @@ define i32 @f6(i16 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: llh %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262144
+  %half = load i16 , i16 *%ptr
   %ext = zext i16 %half to i32
   ret i32 %ext
 }
@@ -71,8 +71,8 @@ define i32 @f7(i16 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: llh %r2, -2(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -1
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -1
+  %half = load i16 , i16 *%ptr
   %ext = zext i16 %half to i32
   ret i32 %ext
 }
@@ -82,8 +82,8 @@ define i32 @f8(i16 *%src) {
 ; CHECK-LABEL: f8:
 ; CHECK: llh %r2, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262144
+  %half = load i16 , i16 *%ptr
   %ext = zext i16 %half to i32
   ret i32 %ext
 }
@@ -95,8 +95,8 @@ define i32 @f9(i16 *%src) {
 ; CHECK: agfi %r2, -524290
 ; CHECK: llh %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262145
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262145
+  %half = load i16 , i16 *%ptr
   %ext = zext i16 %half to i32
   ret i32 %ext
 }
@@ -109,7 +109,7 @@ define i32 @f10(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i16 *
-  %half = load i16 *%ptr
+  %half = load i16 , i16 *%ptr
   %ext = zext i16 %half to i32
   ret i32 %ext
 }
@@ -120,22 +120,22 @@ define void @f11(i32 *%ptr) {
 ; CHECK-LABEL: f11:
 ; CHECK: llh {{%r[0-9]+}}, 16{{[26]}}(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile i32 *%ptr
-  %val1 = load volatile i32 *%ptr
-  %val2 = load volatile i32 *%ptr
-  %val3 = load volatile i32 *%ptr
-  %val4 = load volatile i32 *%ptr
-  %val5 = load volatile i32 *%ptr
-  %val6 = load volatile i32 *%ptr
-  %val7 = load volatile i32 *%ptr
-  %val8 = load volatile i32 *%ptr
-  %val9 = load volatile i32 *%ptr
-  %val10 = load volatile i32 *%ptr
-  %val11 = load volatile i32 *%ptr
-  %val12 = load volatile i32 *%ptr
-  %val13 = load volatile i32 *%ptr
-  %val14 = load volatile i32 *%ptr
-  %val15 = load volatile i32 *%ptr
+  %val0 = load volatile i32 , i32 *%ptr
+  %val1 = load volatile i32 , i32 *%ptr
+  %val2 = load volatile i32 , i32 *%ptr
+  %val3 = load volatile i32 , i32 *%ptr
+  %val4 = load volatile i32 , i32 *%ptr
+  %val5 = load volatile i32 , i32 *%ptr
+  %val6 = load volatile i32 , i32 *%ptr
+  %val7 = load volatile i32 , i32 *%ptr
+  %val8 = load volatile i32 , i32 *%ptr
+  %val9 = load volatile i32 , i32 *%ptr
+  %val10 = load volatile i32 , i32 *%ptr
+  %val11 = load volatile i32 , i32 *%ptr
+  %val12 = load volatile i32 , i32 *%ptr
+  %val13 = load volatile i32 , i32 *%ptr
+  %val14 = load volatile i32 , i32 *%ptr
+  %val15 = load volatile i32 , i32 *%ptr
 
   %trunc0 = trunc i32 %val0 to i16
   %trunc1 = trunc i32 %val1 to i16
diff --git a/test/CodeGen/SystemZ/int-conv-07.ll b/test/CodeGen/SystemZ/int-conv-07.ll
index 4b78c773d1ea..5e989e4737e8 100644
--- a/test/CodeGen/SystemZ/int-conv-07.ll
+++ b/test/CodeGen/SystemZ/int-conv-07.ll
@@ -27,7 +27,7 @@ define i64 @f3(i16 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: lgh %r2, 0(%r2)
 ; CHECK: br %r14
-  %half = load i16 *%src
+  %half = load i16 , i16 *%src
   %ext = sext i16 %half to i64
   ret i64 %ext
 }
@@ -37,8 +37,8 @@ define i64 @f4(i16 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: lgh %r2, 524286(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262143
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262143
+  %half = load i16 , i16 *%ptr
   %ext = sext i16 %half to i64
   ret i64 %ext
 }
@@ -50,8 +50,8 @@ define i64 @f5(i16 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: lgh %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262144
+  %half = load i16 , i16 *%ptr
   %ext = sext i16 %half to i64
   ret i64 %ext
 }
@@ -61,8 +61,8 @@ define i64 @f6(i16 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: lgh %r2, -2(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -1
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -1
+  %half = load i16 , i16 *%ptr
   %ext = sext i16 %half to i64
   ret i64 %ext
 }
@@ -72,8 +72,8 @@ define i64 @f7(i16 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: lgh %r2, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262144
+  %half = load i16 , i16 *%ptr
   %ext = sext i16 %half to i64
   ret i64 %ext
 }
@@ -85,8 +85,8 @@ define i64 @f8(i16 *%src) {
 ; CHECK: agfi %r2, -524290
 ; CHECK: lgh %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262145
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262145
+  %half = load i16 , i16 *%ptr
   %ext = sext i16 %half to i64
   ret i64 %ext
 }
@@ -99,7 +99,7 @@ define i64 @f9(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i16 *
-  %half = load i16 *%ptr
+  %half = load i16 , i16 *%ptr
   %ext = sext i16 %half to i64
   ret i64 %ext
 }
@@ -110,22 +110,22 @@ define void @f10(i64 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK: lgh {{%r[0-9]+}}, 166(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile i64 *%ptr
-  %val1 = load volatile i64 *%ptr
-  %val2 = load volatile i64 *%ptr
-  %val3 = load volatile i64 *%ptr
-  %val4 = load volatile i64 *%ptr
-  %val5 = load volatile i64 *%ptr
-  %val6 = load volatile i64 *%ptr
-  %val7 = load volatile i64 *%ptr
-  %val8 = load volatile i64 *%ptr
-  %val9 = load volatile i64 *%ptr
-  %val10 = load volatile i64 *%ptr
-  %val11 = load volatile i64 *%ptr
-  %val12 = load volatile i64 *%ptr
-  %val13 = load volatile i64 *%ptr
-  %val14 = load volatile i64 *%ptr
-  %val15 = load volatile i64 *%ptr
+  %val0 = load volatile i64 , i64 *%ptr
+  %val1 = load volatile i64 , i64 *%ptr
+  %val2 = load volatile i64 , i64 *%ptr
+  %val3 = load volatile i64 , i64 *%ptr
+  %val4 = load volatile i64 , i64 *%ptr
+  %val5 = load volatile i64 , i64 *%ptr
+  %val6 = load volatile i64 , i64 *%ptr
+  %val7 = load volatile i64 , i64 *%ptr
+  %val8 = load volatile i64 , i64 *%ptr
+  %val9 = load volatile i64 , i64 *%ptr
+  %val10 = load volatile i64 , i64 *%ptr
+  %val11 = load volatile i64 , i64 *%ptr
+  %val12 = load volatile i64 , i64 *%ptr
+  %val13 = load volatile i64 , i64 *%ptr
+  %val14 = load volatile i64 , i64 *%ptr
+  %val15 = load volatile i64 , i64 *%ptr
 
   %trunc0 = trunc i64 %val0 to i16
   %trunc1 = trunc i64 %val1 to i16
diff --git a/test/CodeGen/SystemZ/int-conv-08.ll b/test/CodeGen/SystemZ/int-conv-08.ll
index 6b6cb672fb9a..8524dfebe277 100644
--- a/test/CodeGen/SystemZ/int-conv-08.ll
+++ b/test/CodeGen/SystemZ/int-conv-08.ll
@@ -36,7 +36,7 @@ define i64 @f4(i16 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: llgh %r2, 0(%r2)
 ; CHECK: br %r14
-  %half = load i16 *%src
+  %half = load i16 , i16 *%src
   %ext = zext i16 %half to i64
   ret i64 %ext
 }
@@ -46,8 +46,8 @@ define i64 @f5(i16 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: llgh %r2, 524286(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262143
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262143
+  %half = load i16 , i16 *%ptr
   %ext = zext i16 %half to i64
   ret i64 %ext
 }
@@ -59,8 +59,8 @@ define i64 @f6(i16 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: llgh %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262144
+  %half = load i16 , i16 *%ptr
   %ext = zext i16 %half to i64
   ret i64 %ext
 }
@@ -70,8 +70,8 @@ define i64 @f7(i16 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: llgh %r2, -2(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -1
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -1
+  %half = load i16 , i16 *%ptr
   %ext = zext i16 %half to i64
   ret i64 %ext
 }
@@ -81,8 +81,8 @@ define i64 @f8(i16 *%src) {
 ; CHECK-LABEL: f8:
 ; CHECK: llgh %r2, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262144
+  %half = load i16 , i16 *%ptr
   %ext = zext i16 %half to i64
   ret i64 %ext
 }
@@ -94,8 +94,8 @@ define i64 @f9(i16 *%src) {
 ; CHECK: agfi %r2, -524290
 ; CHECK: llgh %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262145
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262145
+  %half = load i16 , i16 *%ptr
   %ext = zext i16 %half to i64
   ret i64 %ext
 }
@@ -108,7 +108,7 @@ define i64 @f10(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i16 *
-  %half = load i16 *%ptr
+  %half = load i16 , i16 *%ptr
   %ext = zext i16 %half to i64
   ret i64 %ext
 }
@@ -119,22 +119,22 @@ define void @f11(i64 *%ptr) {
 ; CHECK-LABEL: f11:
 ; CHECK: llgh {{%r[0-9]+}}, 166(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile i64 *%ptr
-  %val1 = load volatile i64 *%ptr
-  %val2 = load volatile i64 *%ptr
-  %val3 = load volatile i64 *%ptr
-  %val4 = load volatile i64 *%ptr
-  %val5 = load volatile i64 *%ptr
-  %val6 = load volatile i64 *%ptr
-  %val7 = load volatile i64 *%ptr
-  %val8 = load volatile i64 *%ptr
-  %val9 = load volatile i64 *%ptr
-  %val10 = load volatile i64 *%ptr
-  %val11 = load volatile i64 *%ptr
-  %val12 = load volatile i64 *%ptr
-  %val13 = load volatile i64 *%ptr
-  %val14 = load volatile i64 *%ptr
-  %val15 = load volatile i64 *%ptr
+  %val0 = load volatile i64 , i64 *%ptr
+  %val1 = load volatile i64 , i64 *%ptr
+  %val2 = load volatile i64 , i64 *%ptr
+  %val3 = load volatile i64 , i64 *%ptr
+  %val4 = load volatile i64 , i64 *%ptr
+  %val5 = load volatile i64 , i64 *%ptr
+  %val6 = load volatile i64 , i64 *%ptr
+  %val7 = load volatile i64 , i64 *%ptr
+  %val8 = load volatile i64 , i64 *%ptr
+  %val9 = load volatile i64 , i64 *%ptr
+  %val10 = load volatile i64 , i64 *%ptr
+  %val11 = load volatile i64 , i64 *%ptr
+  %val12 = load volatile i64 , i64 *%ptr
+  %val13 = load volatile i64 , i64 *%ptr
+  %val14 = load volatile i64 , i64 *%ptr
+  %val15 = load volatile i64 , i64 *%ptr
 
   %trunc0 = trunc i64 %val0 to i16
   %trunc1 = trunc i64 %val1 to i16
diff --git a/test/CodeGen/SystemZ/int-conv-09.ll b/test/CodeGen/SystemZ/int-conv-09.ll
index b9c508917d4d..ffd20491030a 100644
--- a/test/CodeGen/SystemZ/int-conv-09.ll
+++ b/test/CodeGen/SystemZ/int-conv-09.ll
@@ -26,7 +26,7 @@ define i64 @f3(i32 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: lgf %r2, 0(%r2)
 ; CHECK: br %r14
-  %word = load i32 *%src
+  %word = load i32 , i32 *%src
   %ext = sext i32 %word to i64
   ret i64 %ext
 }
@@ -36,8 +36,8 @@ define i64 @f4(i32 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: lgf %r2, 524284(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %word = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %word = load i32 , i32 *%ptr
   %ext = sext i32 %word to i64
   ret i64 %ext
 }
@@ -49,8 +49,8 @@ define i64 @f5(i32 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: lgf %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %word = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %word = load i32 , i32 *%ptr
   %ext = sext i32 %word to i64
   ret i64 %ext
 }
@@ -60,8 +60,8 @@ define i64 @f6(i32 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: lgf %r2, -4(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %word = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %word = load i32 , i32 *%ptr
   %ext = sext i32 %word to i64
   ret i64 %ext
 }
@@ -71,8 +71,8 @@ define i64 @f7(i32 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: lgf %r2, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %word = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %word = load i32 , i32 *%ptr
   %ext = sext i32 %word to i64
   ret i64 %ext
 }
@@ -84,8 +84,8 @@ define i64 @f8(i32 *%src) {
 ; CHECK: agfi %r2, -524292
 ; CHECK: lgf %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %word = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %word = load i32 , i32 *%ptr
   %ext = sext i32 %word to i64
   ret i64 %ext
 }
@@ -98,7 +98,7 @@ define i64 @f9(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i32 *
-  %word = load i32 *%ptr
+  %word = load i32 , i32 *%ptr
   %ext = sext i32 %word to i64
   ret i64 %ext
 }
diff --git a/test/CodeGen/SystemZ/int-conv-10.ll b/test/CodeGen/SystemZ/int-conv-10.ll
index 781c74c7fa23..a5e74061017e 100644
--- a/test/CodeGen/SystemZ/int-conv-10.ll
+++ b/test/CodeGen/SystemZ/int-conv-10.ll
@@ -35,7 +35,7 @@ define i64 @f4(i32 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: llgf %r2, 0(%r2)
 ; CHECK: br %r14
-  %word = load i32 *%src
+  %word = load i32 , i32 *%src
   %ext = zext i32 %word to i64
   ret i64 %ext
 }
@@ -45,8 +45,8 @@ define i64 @f5(i32 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: llgf %r2, 524284(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %word = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %word = load i32 , i32 *%ptr
   %ext = zext i32 %word to i64
   ret i64 %ext
 }
@@ -58,8 +58,8 @@ define i64 @f6(i32 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: llgf %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %word = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %word = load i32 , i32 *%ptr
   %ext = zext i32 %word to i64
   ret i64 %ext
 }
@@ -69,8 +69,8 @@ define i64 @f7(i32 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: llgf %r2, -4(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %word = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %word = load i32 , i32 *%ptr
   %ext = zext i32 %word to i64
   ret i64 %ext
 }
@@ -80,8 +80,8 @@ define i64 @f8(i32 *%src) {
 ; CHECK-LABEL: f8:
 ; CHECK: llgf %r2, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %word = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %word = load i32 , i32 *%ptr
   %ext = zext i32 %word to i64
   ret i64 %ext
 }
@@ -93,8 +93,8 @@ define i64 @f9(i32 *%src) {
 ; CHECK: agfi %r2, -524292
 ; CHECK: llgf %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %word = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %word = load i32 , i32 *%ptr
   %ext = zext i32 %word to i64
   ret i64 %ext
 }
@@ -107,7 +107,7 @@ define i64 @f10(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i32 *
-  %word = load i32 *%ptr
+  %word = load i32 , i32 *%ptr
   %ext = zext i32 %word to i64
   ret i64 %ext
 }
diff --git a/test/CodeGen/SystemZ/int-conv-11.ll b/test/CodeGen/SystemZ/int-conv-11.ll
index 30769621bf82..cfa0870cd5d2 100644
--- a/test/CodeGen/SystemZ/int-conv-11.ll
+++ b/test/CodeGen/SystemZ/int-conv-11.ll
@@ -8,38 +8,38 @@ define void @f1(i32 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: llc{{h?}} {{%r[0-9]+}}, 16{{[37]}}(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile i32 *%ptr
-  %val1 = load volatile i32 *%ptr
-  %val2 = load volatile i32 *%ptr
-  %val3 = load volatile i32 *%ptr
-  %val4 = load volatile i32 *%ptr
-  %val5 = load volatile i32 *%ptr
-  %val6 = load volatile i32 *%ptr
-  %val7 = load volatile i32 *%ptr
-  %val8 = load volatile i32 *%ptr
-  %val9 = load volatile i32 *%ptr
-  %val10 = load volatile i32 *%ptr
-  %val11 = load volatile i32 *%ptr
-  %val12 = load volatile i32 *%ptr
-  %val13 = load volatile i32 *%ptr
-  %val14 = load volatile i32 *%ptr
-  %val15 = load volatile i32 *%ptr
-  %val16 = load volatile i32 *%ptr
-  %val17 = load volatile i32 *%ptr
-  %val18 = load volatile i32 *%ptr
-  %val19 = load volatile i32 *%ptr
-  %val20 = load volatile i32 *%ptr
-  %val21 = load volatile i32 *%ptr
-  %val22 = load volatile i32 *%ptr
-  %val23 = load volatile i32 *%ptr
-  %val24 = load volatile i32 *%ptr
-  %val25 = load volatile i32 *%ptr
-  %val26 = load volatile i32 *%ptr
-  %val27 = load volatile i32 *%ptr
-  %val28 = load volatile i32 *%ptr
-  %val29 = load volatile i32 *%ptr
-  %val30 = load volatile i32 *%ptr
-  %val31 = load volatile i32 *%ptr
+  %val0 = load volatile i32 , i32 *%ptr
+  %val1 = load volatile i32 , i32 *%ptr
+  %val2 = load volatile i32 , i32 *%ptr
+  %val3 = load volatile i32 , i32 *%ptr
+  %val4 = load volatile i32 , i32 *%ptr
+  %val5 = load volatile i32 , i32 *%ptr
+  %val6 = load volatile i32 , i32 *%ptr
+  %val7 = load volatile i32 , i32 *%ptr
+  %val8 = load volatile i32 , i32 *%ptr
+  %val9 = load volatile i32 , i32 *%ptr
+  %val10 = load volatile i32 , i32 *%ptr
+  %val11 = load volatile i32 , i32 *%ptr
+  %val12 = load volatile i32 , i32 *%ptr
+  %val13 = load volatile i32 , i32 *%ptr
+  %val14 = load volatile i32 , i32 *%ptr
+  %val15 = load volatile i32 , i32 *%ptr
+  %val16 = load volatile i32 , i32 *%ptr
+  %val17 = load volatile i32 , i32 *%ptr
+  %val18 = load volatile i32 , i32 *%ptr
+  %val19 = load volatile i32 , i32 *%ptr
+  %val20 = load volatile i32 , i32 *%ptr
+  %val21 = load volatile i32 , i32 *%ptr
+  %val22 = load volatile i32 , i32 *%ptr
+  %val23 = load volatile i32 , i32 *%ptr
+  %val24 = load volatile i32 , i32 *%ptr
+  %val25 = load volatile i32 , i32 *%ptr
+  %val26 = load volatile i32 , i32 *%ptr
+  %val27 = load volatile i32 , i32 *%ptr
+  %val28 = load volatile i32 , i32 *%ptr
+  %val29 = load volatile i32 , i32 *%ptr
+  %val30 = load volatile i32 , i32 *%ptr
+  %val31 = load volatile i32 , i32 *%ptr
 
   %trunc0 = trunc i32 %val0 to i8
   %trunc1 = trunc i32 %val1 to i8
@@ -181,38 +181,38 @@ define void @f2(i32 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: llh{{h?}} {{%r[0-9]+}}, 16{{[26]}}(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile i32 *%ptr
-  %val1 = load volatile i32 *%ptr
-  %val2 = load volatile i32 *%ptr
-  %val3 = load volatile i32 *%ptr
-  %val4 = load volatile i32 *%ptr
-  %val5 = load volatile i32 *%ptr
-  %val6 = load volatile i32 *%ptr
-  %val7 = load volatile i32 *%ptr
-  %val8 = load volatile i32 *%ptr
-  %val9 = load volatile i32 *%ptr
-  %val10 = load volatile i32 *%ptr
-  %val11 = load volatile i32 *%ptr
-  %val12 = load volatile i32 *%ptr
-  %val13 = load volatile i32 *%ptr
-  %val14 = load volatile i32 *%ptr
-  %val15 = load volatile i32 *%ptr
-  %val16 = load volatile i32 *%ptr
-  %val17 = load volatile i32 *%ptr
-  %val18 = load volatile i32 *%ptr
-  %val19 = load volatile i32 *%ptr
-  %val20 = load volatile i32 *%ptr
-  %val21 = load volatile i32 *%ptr
-  %val22 = load volatile i32 *%ptr
-  %val23 = load volatile i32 *%ptr
-  %val24 = load volatile i32 *%ptr
-  %val25 = load volatile i32 *%ptr
-  %val26 = load volatile i32 *%ptr
-  %val27 = load volatile i32 *%ptr
-  %val28 = load volatile i32 *%ptr
-  %val29 = load volatile i32 *%ptr
-  %val30 = load volatile i32 *%ptr
-  %val31 = load volatile i32 *%ptr
+  %val0 = load volatile i32 , i32 *%ptr
+  %val1 = load volatile i32 , i32 *%ptr
+  %val2 = load volatile i32 , i32 *%ptr
+  %val3 = load volatile i32 , i32 *%ptr
+  %val4 = load volatile i32 , i32 *%ptr
+  %val5 = load volatile i32 , i32 *%ptr
+  %val6 = load volatile i32 , i32 *%ptr
+  %val7 = load volatile i32 , i32 *%ptr
+  %val8 = load volatile i32 , i32 *%ptr
+  %val9 = load volatile i32 , i32 *%ptr
+  %val10 = load volatile i32 , i32 *%ptr
+  %val11 = load volatile i32 , i32 *%ptr
+  %val12 = load volatile i32 , i32 *%ptr
+  %val13 = load volatile i32 , i32 *%ptr
+  %val14 = load volatile i32 , i32 *%ptr
+  %val15 = load volatile i32 , i32 *%ptr
+  %val16 = load volatile i32 , i32 *%ptr
+  %val17 = load volatile i32 , i32 *%ptr
+  %val18 = load volatile i32 , i32 *%ptr
+  %val19 = load volatile i32 , i32 *%ptr
+  %val20 = load volatile i32 , i32 *%ptr
+  %val21 = load volatile i32 , i32 *%ptr
+  %val22 = load volatile i32 , i32 *%ptr
+  %val23 = load volatile i32 , i32 *%ptr
+  %val24 = load volatile i32 , i32 *%ptr
+  %val25 = load volatile i32 , i32 *%ptr
+  %val26 = load volatile i32 , i32 *%ptr
+  %val27 = load volatile i32 , i32 *%ptr
+  %val28 = load volatile i32 , i32 *%ptr
+  %val29 = load volatile i32 , i32 *%ptr
+  %val30 = load volatile i32 , i32 *%ptr
+  %val31 = load volatile i32 , i32 *%ptr
 
   %trunc0 = trunc i32 %val0 to i16
   %trunc1 = trunc i32 %val1 to i16
diff --git a/test/CodeGen/SystemZ/int-div-01.ll b/test/CodeGen/SystemZ/int-div-01.ll
index 2c21186e3369..1442109dc23c 100644
--- a/test/CodeGen/SystemZ/int-div-01.ll
+++ b/test/CodeGen/SystemZ/int-div-01.ll
@@ -69,7 +69,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-NOT: dsgfr
 ; CHECK: or %r2, %r3
 ; CHECK: br %r14
-  %a = load i32 *%src
+  %a = load i32 , i32 *%src
   %div = sdiv i32 %a, %b
   %rem = srem i32 %a, %b
   %or = or i32 %rem, %div
@@ -83,7 +83,7 @@ define void @f6(i32 *%dest, i32 %a, i32 *%src) {
 ; CHECK: dsgf %r0, 0(%r4)
 ; CHECK: st %r1, 0(%r2)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %div = sdiv i32 %a, %b
   store i32 %div, i32 *%dest
   ret void
@@ -96,7 +96,7 @@ define void @f7(i32 *%dest, i32 %a, i32 *%src) {
 ; CHECK: dsgf %r0, 0(%r4)
 ; CHECK: st %r0, 0(%r2)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %rem = srem i32 %a, %b
   store i32 %rem, i32 *%dest
   ret void
@@ -112,7 +112,7 @@ define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
 ; CHECK-NOT: {{dsgf|dsgfr}}
 ; CHECK: or %r2, %r3
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %div = sdiv i32 %a, %b
   %rem = srem i32 %a, %b
   %or = or i32 %rem, %div
@@ -124,8 +124,8 @@ define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
 ; CHECK-LABEL: f9:
 ; CHECK: dsgf %r2, 524284(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %b = load i32 , i32 *%ptr
   %rem = srem i32 %a, %b
   ret i32 %rem
 }
@@ -137,8 +137,8 @@ define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
 ; CHECK: agfi %r4, 524288
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %b = load i32 , i32 *%ptr
   %rem = srem i32 %a, %b
   ret i32 %rem
 }
@@ -148,8 +148,8 @@ define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
 ; CHECK-LABEL: f11:
 ; CHECK: dsgf %r2, -4(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %b = load i32 , i32 *%ptr
   %rem = srem i32 %a, %b
   ret i32 %rem
 }
@@ -159,8 +159,8 @@ define i32 @f12(i32 %dummy, i32 %a, i32 *%src) {
 ; CHECK-LABEL: f12:
 ; CHECK: dsgf %r2, -524288(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %b = load i32 , i32 *%ptr
   %rem = srem i32 %a, %b
   ret i32 %rem
 }
@@ -172,8 +172,8 @@ define i32 @f13(i32 %dummy, i32 %a, i32 *%src) {
 ; CHECK: agfi %r4, -524292
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %b = load i32 , i32 *%ptr
   %rem = srem i32 %a, %b
   ret i32 %rem
 }
@@ -186,7 +186,7 @@ define i32 @f14(i32 %dummy, i32 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %rem = srem i32 %a, %b
   ret i32 %rem
 }
@@ -200,7 +200,7 @@ define void @f15(i32 *%dest, i32 *%src) {
 ; CHECK: lgfr %r1, %r2
 ; CHECK: dsgfr %r0, [[B]]
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %a = call i32 @foo()
   %div = sdiv i32 %a, %b
   store i32 %div, i32 *%dest
@@ -213,26 +213,26 @@ define i32 @f16(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: dsgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-  %ptr9 = getelementptr i32 *%ptr0, i64 18
-
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
-  %val9 = load i32 *%ptr9
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32, i32 *%ptr0, i64 18
+
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
+  %val9 = load i32 , i32 *%ptr9
 
   %ret = call i32 @foo()
 
diff --git a/test/CodeGen/SystemZ/int-div-02.ll b/test/CodeGen/SystemZ/int-div-02.ll
index f3287a56c6cd..1a4b4d95c936 100644
--- a/test/CodeGen/SystemZ/int-div-02.ll
+++ b/test/CodeGen/SystemZ/int-div-02.ll
@@ -57,7 +57,7 @@ define void @f4(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
 ; CHECK: dl %r2, 0(%r4)
 ; CHECK: st %r3, 0(%r5)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %div = udiv i32 %a, %b
   store i32 %div, i32 *%dest
   ret void
@@ -72,7 +72,7 @@ define void @f5(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
 ; CHECK: dl %r2, 0(%r4)
 ; CHECK: st %r2, 0(%r5)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %rem = urem i32 %a, %b
   store i32 %rem, i32 *%dest
   ret void
@@ -88,7 +88,7 @@ define i32 @f6(i32 %dummy, i32 %a, i32 *%src) {
 ; CHECK-NOT: {{dl|dlr}}
 ; CHECK: or %r2, %r3
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %div = udiv i32 %a, %b
   %rem = urem i32 %a, %b
   %or = or i32 %rem, %div
@@ -100,8 +100,8 @@ define i32 @f7(i32 %dummy, i32 %a, i32 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: dl %r2, 524284(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %b = load i32 , i32 *%ptr
   %rem = urem i32 %a, %b
   ret i32 %rem
 }
@@ -113,8 +113,8 @@ define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
 ; CHECK: agfi %r4, 524288
 ; CHECK: dl %r2, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %b = load i32 , i32 *%ptr
   %rem = urem i32 %a, %b
   ret i32 %rem
 }
@@ -124,8 +124,8 @@ define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
 ; CHECK-LABEL: f9:
 ; CHECK: dl %r2, -4(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %b = load i32 , i32 *%ptr
   %rem = urem i32 %a, %b
   ret i32 %rem
 }
@@ -135,8 +135,8 @@ define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
 ; CHECK-LABEL: f10:
 ; CHECK: dl %r2, -524288(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %b = load i32 , i32 *%ptr
   %rem = urem i32 %a, %b
   ret i32 %rem
 }
@@ -148,8 +148,8 @@ define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
 ; CHECK: agfi %r4, -524292
 ; CHECK: dl %r2, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %b = load i32 , i32 *%ptr
   %rem = urem i32 %a, %b
   ret i32 %rem
 }
@@ -162,7 +162,7 @@ define i32 @f12(i32 %dummy, i32 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %rem = urem i32 %a, %b
   ret i32 %rem
 }
@@ -173,26 +173,26 @@ define i32 @f13(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: dl {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-  %ptr9 = getelementptr i32 *%ptr0, i64 18
-
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
-  %val9 = load i32 *%ptr9
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32, i32 *%ptr0, i64 18
+
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
+  %val9 = load i32 , i32 *%ptr9
 
   %ret = call i32 @foo()
 
diff --git a/test/CodeGen/SystemZ/int-div-03.ll b/test/CodeGen/SystemZ/int-div-03.ll
index 7c0409018f16..37a7c4f748c9 100644
--- a/test/CodeGen/SystemZ/int-div-03.ll
+++ b/test/CodeGen/SystemZ/int-div-03.ll
@@ -75,7 +75,7 @@ define void @f6(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: stg %r3, 0(%r5)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %bext = sext i32 %b to i64
   %div = sdiv i64 %a, %bext
   store i64 %div, i64 *%dest
@@ -89,7 +89,7 @@ define void @f7(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: stg %r2, 0(%r5)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %bext = sext i32 %b to i64
   %rem = srem i64 %a, %bext
   store i64 %rem, i64 *%dest
@@ -104,7 +104,7 @@ define i64 @f8(i64 %dummy, i64 %a, i32 *%src) {
 ; CHECK-NOT: {{dsgf|dsgfr}}
 ; CHECK: ogr %r2, %r3
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %bext = sext i32 %b to i64
   %div = sdiv i64 %a, %bext
   %rem = srem i64 %a, %bext
@@ -117,8 +117,8 @@ define i64 @f9(i64 %dummy, i64 %a, i32 *%src) {
 ; CHECK-LABEL: f9:
 ; CHECK: dsgf %r2, 524284(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %rem = srem i64 %a, %bext
   ret i64 %rem
@@ -131,8 +131,8 @@ define i64 @f10(i64 %dummy, i64 %a, i32 *%src) {
 ; CHECK: agfi %r4, 524288
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %rem = srem i64 %a, %bext
   ret i64 %rem
@@ -143,8 +143,8 @@ define i64 @f11(i64 %dummy, i64 %a, i32 *%src) {
 ; CHECK-LABEL: f11:
 ; CHECK: dsgf %r2, -4(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %rem = srem i64 %a, %bext
   ret i64 %rem
@@ -155,8 +155,8 @@ define i64 @f12(i64 %dummy, i64 %a, i32 *%src) {
 ; CHECK-LABEL: f12:
 ; CHECK: dsgf %r2, -524288(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %rem = srem i64 %a, %bext
   ret i64 %rem
@@ -169,8 +169,8 @@ define i64 @f13(i64 %dummy, i64 %a, i32 *%src) {
 ; CHECK: agfi %r4, -524292
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %rem = srem i64 %a, %bext
   ret i64 %rem
@@ -184,7 +184,7 @@ define i64 @f14(i64 %dummy, i64 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %rem = srem i64 %a, %bext
   ret i64 %rem
@@ -199,7 +199,7 @@ define void @f15(i64 *%dest, i32 *%src) {
 ; CHECK: lgr %r1, %r2
 ; CHECK: dsgfr %r0, [[B]]
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %a = call i64 @foo()
   %ext = sext i32 %b to i64
   %div = sdiv i64 %a, %ext
diff --git a/test/CodeGen/SystemZ/int-div-04.ll b/test/CodeGen/SystemZ/int-div-04.ll
index 87f1e105f6a4..e8c6f3e03c6a 100644
--- a/test/CodeGen/SystemZ/int-div-04.ll
+++ b/test/CodeGen/SystemZ/int-div-04.ll
@@ -49,7 +49,7 @@ define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: stg %r3, 0(%r5)
 ; CHECK: br %r14
-  %b = load i64 *%src
+  %b = load i64 , i64 *%src
   %div = sdiv i64 %a, %b
   store i64 %div, i64 *%dest
   ret void
@@ -62,7 +62,7 @@ define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: stg %r2, 0(%r5)
 ; CHECK: br %r14
-  %b = load i64 *%src
+  %b = load i64 , i64 *%src
   %rem = srem i64 %a, %b
   store i64 %rem, i64 *%dest
   ret void
@@ -76,7 +76,7 @@ define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK-NOT: {{dsg|dsgr}}
 ; CHECK: ogr %r2, %r3
 ; CHECK: br %r14
-  %b = load i64 *%src
+  %b = load i64 , i64 *%src
   %div = sdiv i64 %a, %b
   %rem = srem i64 %a, %b
   %or = or i64 %rem, %div
@@ -88,8 +88,8 @@ define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: dsg %r2, 524280(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65535
+  %b = load i64 , i64 *%ptr
   %rem = srem i64 %a, %b
   ret i64 %rem
 }
@@ -101,8 +101,8 @@ define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK: agfi %r4, 524288
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65536
+  %b = load i64 , i64 *%ptr
   %rem = srem i64 %a, %b
   ret i64 %rem
 }
@@ -112,8 +112,8 @@ define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK-LABEL: f9:
 ; CHECK: dsg %r2, -8(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -1
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -1
+  %b = load i64 , i64 *%ptr
   %rem = srem i64 %a, %b
   ret i64 %rem
 }
@@ -123,8 +123,8 @@ define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK-LABEL: f10:
 ; CHECK: dsg %r2, -524288(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
+  %b = load i64 , i64 *%ptr
   %rem = srem i64 %a, %b
   ret i64 %rem
 }
@@ -136,8 +136,8 @@ define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK: agfi %r4, -524296
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
+  %b = load i64 , i64 *%ptr
   %rem = srem i64 %a, %b
   ret i64 %rem
 }
@@ -150,7 +150,7 @@ define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i64 *
-  %b = load i64 *%ptr
+  %b = load i64 , i64 *%ptr
   %rem = srem i64 %a, %b
   ret i64 %rem
 }
@@ -161,28 +161,28 @@ define i64 @f13(i64 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: dsg {{%r[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i64 *%ptr0, i64 2
-  %ptr2 = getelementptr i64 *%ptr0, i64 4
-  %ptr3 = getelementptr i64 *%ptr0, i64 6
-  %ptr4 = getelementptr i64 *%ptr0, i64 8
-  %ptr5 = getelementptr i64 *%ptr0, i64 10
-  %ptr6 = getelementptr i64 *%ptr0, i64 12
-  %ptr7 = getelementptr i64 *%ptr0, i64 14
-  %ptr8 = getelementptr i64 *%ptr0, i64 16
-  %ptr9 = getelementptr i64 *%ptr0, i64 18
-  %ptr10 = getelementptr i64 *%ptr0, i64 20
-
-  %val0 = load i64 *%ptr0
-  %val1 = load i64 *%ptr1
-  %val2 = load i64 *%ptr2
-  %val3 = load i64 *%ptr3
-  %val4 = load i64 *%ptr4
-  %val5 = load i64 *%ptr5
-  %val6 = load i64 *%ptr6
-  %val7 = load i64 *%ptr7
-  %val8 = load i64 *%ptr8
-  %val9 = load i64 *%ptr9
-  %val10 = load i64 *%ptr10
+  %ptr1 = getelementptr i64, i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64, i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64, i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64, i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64, i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64, i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64, i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64, i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64, i64 *%ptr0, i64 18
+  %ptr10 = getelementptr i64, i64 *%ptr0, i64 20
+
+  %val0 = load i64 , i64 *%ptr0
+  %val1 = load i64 , i64 *%ptr1
+  %val2 = load i64 , i64 *%ptr2
+  %val3 = load i64 , i64 *%ptr3
+  %val4 = load i64 , i64 *%ptr4
+  %val5 = load i64 , i64 *%ptr5
+  %val6 = load i64 , i64 *%ptr6
+  %val7 = load i64 , i64 *%ptr7
+  %val8 = load i64 , i64 *%ptr8
+  %val9 = load i64 , i64 *%ptr9
+  %val10 = load i64 , i64 *%ptr10
 
   %ret = call i64 @foo()
 
diff --git a/test/CodeGen/SystemZ/int-div-05.ll b/test/CodeGen/SystemZ/int-div-05.ll
index 817983005a9d..f80a139238ea 100644
--- a/test/CodeGen/SystemZ/int-div-05.ll
+++ b/test/CodeGen/SystemZ/int-div-05.ll
@@ -57,7 +57,7 @@ define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 ; CHECK: dlg %r2, 0(%r4)
 ; CHECK: stg %r3, 0(%r5)
 ; CHECK: br %r14
-  %b = load i64 *%src
+  %b = load i64 , i64 *%src
   %div = udiv i64 %a, %b
   store i64 %div, i64 *%dest
   ret void
@@ -72,7 +72,7 @@ define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 ; CHECK: dlg %r2, 0(%r4)
 ; CHECK: stg %r2, 0(%r5)
 ; CHECK: br %r14
-  %b = load i64 *%src
+  %b = load i64 , i64 *%src
   %rem = urem i64 %a, %b
   store i64 %rem, i64 *%dest
   ret void
@@ -88,7 +88,7 @@ define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK-NOT: {{dlg|dlgr}}
 ; CHECK: ogr %r2, %r3
 ; CHECK: br %r14
-  %b = load i64 *%src
+  %b = load i64 , i64 *%src
   %div = udiv i64 %a, %b
   %rem = urem i64 %a, %b
   %or = or i64 %rem, %div
@@ -100,8 +100,8 @@ define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: dlg %r2, 524280(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65535
+  %b = load i64 , i64 *%ptr
   %rem = urem i64 %a, %b
   ret i64 %rem
 }
@@ -113,8 +113,8 @@ define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK: agfi %r4, 524288
 ; CHECK: dlg %r2, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65536
+  %b = load i64 , i64 *%ptr
   %rem = urem i64 %a, %b
   ret i64 %rem
 }
@@ -124,8 +124,8 @@ define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK-LABEL: f9:
 ; CHECK: dlg %r2, -8(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -1
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -1
+  %b = load i64 , i64 *%ptr
   %rem = urem i64 %a, %b
   ret i64 %rem
 }
@@ -135,8 +135,8 @@ define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK-LABEL: f10:
 ; CHECK: dlg %r2, -524288(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
+  %b = load i64 , i64 *%ptr
   %rem = urem i64 %a, %b
   ret i64 %rem
 }
@@ -148,8 +148,8 @@ define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK: agfi %r4, -524296
 ; CHECK: dlg %r2, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
+  %b = load i64 , i64 *%ptr
   %rem = urem i64 %a, %b
   ret i64 %rem
 }
@@ -162,7 +162,7 @@ define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i64 *
-  %b = load i64 *%ptr
+  %b = load i64 , i64 *%ptr
   %rem = urem i64 %a, %b
   ret i64 %rem
 }
@@ -173,28 +173,28 @@ define i64 @f13(i64 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: dlg {{%r[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i64 *%ptr0, i64 2
-  %ptr2 = getelementptr i64 *%ptr0, i64 4
-  %ptr3 = getelementptr i64 *%ptr0, i64 6
-  %ptr4 = getelementptr i64 *%ptr0, i64 8
-  %ptr5 = getelementptr i64 *%ptr0, i64 10
-  %ptr6 = getelementptr i64 *%ptr0, i64 12
-  %ptr7 = getelementptr i64 *%ptr0, i64 14
-  %ptr8 = getelementptr i64 *%ptr0, i64 16
-  %ptr9 = getelementptr i64 *%ptr0, i64 18
-  %ptr10 = getelementptr i64 *%ptr0, i64 20
-
-  %val0 = load i64 *%ptr0
-  %val1 = load i64 *%ptr1
-  %val2 = load i64 *%ptr2
-  %val3 = load i64 *%ptr3
-  %val4 = load i64 *%ptr4
-  %val5 = load i64 *%ptr5
-  %val6 = load i64 *%ptr6
-  %val7 = load i64 *%ptr7
-  %val8 = load i64 *%ptr8
-  %val9 = load i64 *%ptr9
-  %val10 = load i64 *%ptr10
+  %ptr1 = getelementptr i64, i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64, i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64, i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64, i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64, i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64, i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64, i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64, i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64, i64 *%ptr0, i64 18
+  %ptr10 = getelementptr i64, i64 *%ptr0, i64 20
+
+  %val0 = load i64 , i64 *%ptr0
+  %val1 = load i64 , i64 *%ptr1
+  %val2 = load i64 , i64 *%ptr2
+  %val3 = load i64 , i64 *%ptr3
+  %val4 = load i64 , i64 *%ptr4
+  %val5 = load i64 , i64 *%ptr5
+  %val6 = load i64 , i64 *%ptr6
+  %val7 = load i64 , i64 *%ptr7
+  %val8 = load i64 , i64 *%ptr8
+  %val9 = load i64 , i64 *%ptr9
+  %val10 = load i64 , i64 *%ptr10
 
   %ret = call i64 @foo()
 
diff --git a/test/CodeGen/SystemZ/int-move-02.ll b/test/CodeGen/SystemZ/int-move-02.ll
index 5fc0843290f9..7ec0f418502a 100644
--- a/test/CodeGen/SystemZ/int-move-02.ll
+++ b/test/CodeGen/SystemZ/int-move-02.ll
@@ -7,7 +7,7 @@ define i32 @f1(i32 *%src) {
 ; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: br %r14
-  %val = load i32 *%src
+  %val = load i32 , i32 *%src
   ret i32 %val
 }
 
@@ -16,8 +16,8 @@ define i32 @f2(i32 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: l %r2, 4092(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1023
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 1023
+  %val = load i32 , i32 *%ptr
   ret i32 %val
 }
 
@@ -26,8 +26,8 @@ define i32 @f3(i32 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: ly %r2, 4096(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1024
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 1024
+  %val = load i32 , i32 *%ptr
   ret i32 %val
 }
 
@@ -36,8 +36,8 @@ define i32 @f4(i32 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: ly %r2, 524284(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %val = load i32 , i32 *%ptr
   ret i32 %val
 }
 
@@ -48,8 +48,8 @@ define i32 @f5(i32 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %val = load i32 , i32 *%ptr
   ret i32 %val
 }
 
@@ -58,8 +58,8 @@ define i32 @f6(i32 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: ly %r2, -4(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %val = load i32 , i32 *%ptr
   ret i32 %val
 }
 
@@ -68,8 +68,8 @@ define i32 @f7(i32 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: ly %r2, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %val = load i32 , i32 *%ptr
   ret i32 %val
 }
 
@@ -80,8 +80,8 @@ define i32 @f8(i32 *%src) {
 ; CHECK: agfi %r2, -524292
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %val = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %val = load i32 , i32 *%ptr
   ret i32 %val
 }
 
@@ -93,7 +93,7 @@ define i32 @f9(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4095
   %ptr = inttoptr i64 %add2 to i32 *
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   ret i32 %val
 }
 
@@ -105,6 +105,6 @@ define i32 @f10(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i32 *
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   ret i32 %val
 }
diff --git a/test/CodeGen/SystemZ/int-move-03.ll b/test/CodeGen/SystemZ/int-move-03.ll
index 2894512e8eea..60eb0042ca87 100644
--- a/test/CodeGen/SystemZ/int-move-03.ll
+++ b/test/CodeGen/SystemZ/int-move-03.ll
@@ -7,7 +7,7 @@ define i64 @f1(i64 *%src) {
 ; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: br %r14
-  %val = load i64 *%src
+  %val = load i64 , i64 *%src
   ret i64 %val
 }
 
@@ -16,8 +16,8 @@ define i64 @f2(i64 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 524280(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
-  %val = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65535
+  %val = load i64 , i64 *%ptr
   ret i64 %val
 }
 
@@ -28,8 +28,8 @@ define i64 @f3(i64 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
-  %val = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65536
+  %val = load i64 , i64 *%ptr
   ret i64 %val
 }
 
@@ -38,8 +38,8 @@ define i64 @f4(i64 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: lg %r2, -8(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -1
-  %val = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -1
+  %val = load i64 , i64 *%ptr
   ret i64 %val
 }
 
@@ -48,8 +48,8 @@ define i64 @f5(i64 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: lg %r2, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
-  %val = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
+  %val = load i64 , i64 *%ptr
   ret i64 %val
 }
 
@@ -60,8 +60,8 @@ define i64 @f6(i64 *%src) {
 ; CHECK: agfi %r2, -524296
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
-  %val = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
+  %val = load i64 , i64 *%ptr
   ret i64 %val
 }
 
@@ -73,6 +73,6 @@ define i64 @f7(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i64 *
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   ret i64 %val
 }
diff --git a/test/CodeGen/SystemZ/int-move-04.ll b/test/CodeGen/SystemZ/int-move-04.ll
index d97ed2f54a4b..cb7d86428b7e 100644
--- a/test/CodeGen/SystemZ/int-move-04.ll
+++ b/test/CodeGen/SystemZ/int-move-04.ll
@@ -36,7 +36,7 @@ define void @f4(i8 *%dst, i8 %val) {
 ; CHECK-LABEL: f4:
 ; CHECK: stc %r3, 4095(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%dst, i64 4095
+  %ptr = getelementptr i8, i8 *%dst, i64 4095
   store i8 %val, i8 *%ptr
   ret void
 }
@@ -46,7 +46,7 @@ define void @f5(i8 *%dst, i8 %val) {
 ; CHECK-LABEL: f5:
 ; CHECK: stcy %r3, 4096(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%dst, i64 4096
+  %ptr = getelementptr i8, i8 *%dst, i64 4096
   store i8 %val, i8 *%ptr
   ret void
 }
@@ -56,7 +56,7 @@ define void @f6(i8 *%dst, i8 %val) {
 ; CHECK-LABEL: f6:
 ; CHECK: stcy %r3, 524287(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%dst, i64 524287
+  %ptr = getelementptr i8, i8 *%dst, i64 524287
   store i8 %val, i8 *%ptr
   ret void
 }
@@ -68,7 +68,7 @@ define void @f7(i8 *%dst, i8 %val) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%dst, i64 524288
+  %ptr = getelementptr i8, i8 *%dst, i64 524288
   store i8 %val, i8 *%ptr
   ret void
 }
@@ -78,7 +78,7 @@ define void @f8(i8 *%dst, i8 %val) {
 ; CHECK-LABEL: f8:
 ; CHECK: stcy %r3, -1(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%dst, i64 -1
+  %ptr = getelementptr i8, i8 *%dst, i64 -1
   store i8 %val, i8 *%ptr
   ret void
 }
@@ -88,7 +88,7 @@ define void @f9(i8 *%dst, i8 %val) {
 ; CHECK-LABEL: f9:
 ; CHECK: stcy %r3, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%dst, i64 -524288
+  %ptr = getelementptr i8, i8 *%dst, i64 -524288
   store i8 %val, i8 *%ptr
   ret void
 }
@@ -100,7 +100,7 @@ define void @f10(i8 *%dst, i8 %val) {
 ; CHECK: agfi %r2, -524289
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%dst, i64 -524289
+  %ptr = getelementptr i8, i8 *%dst, i64 -524289
   store i8 %val, i8 *%ptr
   ret void
 }
diff --git a/test/CodeGen/SystemZ/int-move-05.ll b/test/CodeGen/SystemZ/int-move-05.ll
index c21b88aa7baa..2bfe03447c84 100644
--- a/test/CodeGen/SystemZ/int-move-05.ll
+++ b/test/CodeGen/SystemZ/int-move-05.ll
@@ -36,7 +36,7 @@ define void @f4(i16 *%dst, i16 %val) {
 ; CHECK-LABEL: f4:
 ; CHECK: sth %r3, 4094(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%dst, i64 2047
+  %ptr = getelementptr i16, i16 *%dst, i64 2047
   store i16 %val, i16 *%ptr
   ret void
 }
@@ -46,7 +46,7 @@ define void @f5(i16 *%dst, i16 %val) {
 ; CHECK-LABEL: f5:
 ; CHECK: sthy %r3, 4096(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%dst, i64 2048
+  %ptr = getelementptr i16, i16 *%dst, i64 2048
   store i16 %val, i16 *%ptr
   ret void
 }
@@ -56,7 +56,7 @@ define void @f6(i16 *%dst, i16 %val) {
 ; CHECK-LABEL: f6:
 ; CHECK: sthy %r3, 524286(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%dst, i64 262143
+  %ptr = getelementptr i16, i16 *%dst, i64 262143
   store i16 %val, i16 *%ptr
   ret void
 }
@@ -68,7 +68,7 @@ define void @f7(i16 *%dst, i16 %val) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%dst, i64 262144
+  %ptr = getelementptr i16, i16 *%dst, i64 262144
   store i16 %val, i16 *%ptr
   ret void
 }
@@ -78,7 +78,7 @@ define void @f8(i16 *%dst, i16 %val) {
 ; CHECK-LABEL: f8:
 ; CHECK: sthy %r3, -2(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%dst, i64 -1
+  %ptr = getelementptr i16, i16 *%dst, i64 -1
   store i16 %val, i16 *%ptr
   ret void
 }
@@ -88,7 +88,7 @@ define void @f9(i16 *%dst, i16 %val) {
 ; CHECK-LABEL: f9:
 ; CHECK: sthy %r3, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%dst, i64 -262144
+  %ptr = getelementptr i16, i16 *%dst, i64 -262144
   store i16 %val, i16 *%ptr
   ret void
 }
@@ -100,7 +100,7 @@ define void @f10(i16 *%dst, i16 %val) {
 ; CHECK: agfi %r2, -524290
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%dst, i64 -262145
+  %ptr = getelementptr i16, i16 *%dst, i64 -262145
   store i16 %val, i16 *%ptr
   ret void
 }
diff --git a/test/CodeGen/SystemZ/int-move-06.ll b/test/CodeGen/SystemZ/int-move-06.ll
index b8c6f53e15d8..f078ec62341f 100644
--- a/test/CodeGen/SystemZ/int-move-06.ll
+++ b/test/CodeGen/SystemZ/int-move-06.ll
@@ -23,7 +23,7 @@ define void @f3(i32 *%dst, i32 %val) {
 ; CHECK-LABEL: f3:
 ; CHECK: st %r3, 4092(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%dst, i64 1023
+  %ptr = getelementptr i32, i32 *%dst, i64 1023
   store i32 %val, i32 *%ptr
   ret void
 }
@@ -33,7 +33,7 @@ define void @f4(i32 *%dst, i32 %val) {
 ; CHECK-LABEL: f4:
 ; CHECK: sty %r3, 4096(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%dst, i64 1024
+  %ptr = getelementptr i32, i32 *%dst, i64 1024
   store i32 %val, i32 *%ptr
   ret void
 }
@@ -43,7 +43,7 @@ define void @f5(i32 *%dst, i32 %val) {
 ; CHECK-LABEL: f5:
 ; CHECK: sty %r3, 524284(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%dst, i64 131071
+  %ptr = getelementptr i32, i32 *%dst, i64 131071
   store i32 %val, i32 *%ptr
   ret void
 }
@@ -55,7 +55,7 @@ define void @f6(i32 *%dst, i32 %val) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%dst, i64 131072
+  %ptr = getelementptr i32, i32 *%dst, i64 131072
   store i32 %val, i32 *%ptr
   ret void
 }
@@ -65,7 +65,7 @@ define void @f7(i32 *%dst, i32 %val) {
 ; CHECK-LABEL: f7:
 ; CHECK: sty %r3, -4(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%dst, i64 -1
+  %ptr = getelementptr i32, i32 *%dst, i64 -1
   store i32 %val, i32 *%ptr
   ret void
 }
@@ -75,7 +75,7 @@ define void @f8(i32 *%dst, i32 %val) {
 ; CHECK-LABEL: f8:
 ; CHECK: sty %r3, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%dst, i64 -131072
+  %ptr = getelementptr i32, i32 *%dst, i64 -131072
   store i32 %val, i32 *%ptr
   ret void
 }
@@ -87,7 +87,7 @@ define void @f9(i32 *%dst, i32 %val) {
 ; CHECK: agfi %r2, -524292
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%dst, i64 -131073
+  %ptr = getelementptr i32, i32 *%dst, i64 -131073
   store i32 %val, i32 *%ptr
   ret void
 }
diff --git a/test/CodeGen/SystemZ/int-move-07.ll b/test/CodeGen/SystemZ/int-move-07.ll
index 5cac1e5b1a2e..77713adeebe3 100644
--- a/test/CodeGen/SystemZ/int-move-07.ll
+++ b/test/CodeGen/SystemZ/int-move-07.ll
@@ -16,7 +16,7 @@ define void @f2(i64 *%dst, i64 %val) {
 ; CHECK-LABEL: f2:
 ; CHECK: stg %r3, 524280(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%dst, i64 65535
+  %ptr = getelementptr i64, i64 *%dst, i64 65535
   store i64 %val, i64 *%ptr
   ret void
 }
@@ -28,7 +28,7 @@ define void @f3(i64 *%dst, i64 %val) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%dst, i64 65536
+  %ptr = getelementptr i64, i64 *%dst, i64 65536
   store i64 %val, i64 *%ptr
   ret void
 }
@@ -38,7 +38,7 @@ define void @f4(i64 *%dst, i64 %val) {
 ; CHECK-LABEL: f4:
 ; CHECK: stg %r3, -8(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%dst, i64 -1
+  %ptr = getelementptr i64, i64 *%dst, i64 -1
   store i64 %val, i64 *%ptr
   ret void
 }
@@ -48,7 +48,7 @@ define void @f5(i64 *%dst, i64 %val) {
 ; CHECK-LABEL: f5:
 ; CHECK: stg %r3, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%dst, i64 -65536
+  %ptr = getelementptr i64, i64 *%dst, i64 -65536
   store i64 %val, i64 *%ptr
   ret void
 }
@@ -60,7 +60,7 @@ define void @f6(i64 *%dst, i64 %val) {
 ; CHECK: agfi %r2, -524296
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%dst, i64 -65537
+  %ptr = getelementptr i64, i64 *%dst, i64 -65537
   store i64 %val, i64 *%ptr
   ret void
 }
diff --git a/test/CodeGen/SystemZ/int-move-08.ll b/test/CodeGen/SystemZ/int-move-08.ll
index 56fcbc6d802b..d28d298013ff 100644
--- a/test/CodeGen/SystemZ/int-move-08.ll
+++ b/test/CodeGen/SystemZ/int-move-08.ll
@@ -18,7 +18,7 @@ define i32 @f1() {
 ; CHECK-LABEL: f1:
 ; CHECK: lhrl %r2, gsrc16
 ; CHECK: br %r14
-  %val = load i16 *@gsrc16
+  %val = load i16 , i16 *@gsrc16
   %ext = sext i16 %val to i32
   ret i32 %ext
 }
@@ -28,7 +28,7 @@ define i32 @f2() {
 ; CHECK-LABEL: f2:
 ; CHECK: llhrl %r2, gsrc16
 ; CHECK: br %r14
-  %val = load i16 *@gsrc16
+  %val = load i16 , i16 *@gsrc16
   %ext = zext i16 %val to i32
   ret i32 %ext
 }
@@ -49,7 +49,7 @@ define void @f4() {
 ; CHECK: lrl %r0, gsrc32
 ; CHECK: strl %r0, gdst32
 ; CHECK: br %r14
-  %val = load i32 *@gsrc32
+  %val = load i32 , i32 *@gsrc32
   store i32 %val, i32 *@gdst32
   ret void
 }
@@ -60,7 +60,7 @@ define i32 @f5() {
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
 ; CHECK: lh %r2, 0([[REG]])
 ; CHECK: br %r14
-  %val = load i16 *@gsrc16u, align 1
+  %val = load i16 , i16 *@gsrc16u, align 1
   %ext = sext i16 %val to i32
   ret i32 %ext
 }
@@ -71,7 +71,7 @@ define i32 @f6() {
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
 ; CHECK: llh %r2, 0([[REG]])
 ; CHECK: br %r14
-  %val = load i16 *@gsrc16u, align 1
+  %val = load i16 , i16 *@gsrc16u, align 1
   %ext = zext i16 %val to i32
   ret i32 %ext
 }
@@ -95,7 +95,7 @@ define void @f8() {
 ; CHECK: larl [[REG:%r[0-5]]], gdst32u
 ; CHECK: st [[VAL]], 0([[REG]])
 ; CHECK: br %r14
-  %val = load i32 *@gsrc32u, align 2
+  %val = load i32 , i32 *@gsrc32u, align 2
   store i32 %val, i32 *@gdst32u, align 2
   ret void
 }
@@ -109,9 +109,9 @@ define void @f9() {
 ; CHECK: srl [[VAL]], 1
 ; CHECK: stc [[VAL]], 1([[REG]])
 ; CHECK: br %r14
-  %ptr1 = getelementptr [2 x i8] *@garray8, i64 0, i64 0
-  %ptr2 = getelementptr [2 x i8] *@garray8, i64 0, i64 1
-  %val = load i8 *%ptr1
+  %ptr1 = getelementptr [2 x i8], [2 x i8] *@garray8, i64 0, i64 0
+  %ptr2 = getelementptr [2 x i8], [2 x i8] *@garray8, i64 0, i64 1
+  %val = load i8 , i8 *%ptr1
   %shr = lshr i8 %val, 1
   store i8 %shr, i8 *%ptr2
   ret void
@@ -125,9 +125,9 @@ define void @f10() {
 ; CHECK: srl [[VAL]], 1
 ; CHECK: sthrl [[VAL]], garray16+2
 ; CHECK: br %r14
-  %ptr1 = getelementptr [2 x i16] *@garray16, i64 0, i64 0
-  %ptr2 = getelementptr [2 x i16] *@garray16, i64 0, i64 1
-  %val = load i16 *%ptr1
+  %ptr1 = getelementptr [2 x i16], [2 x i16] *@garray16, i64 0, i64 0
+  %ptr2 = getelementptr [2 x i16], [2 x i16] *@garray16, i64 0, i64 1
+  %val = load i16 , i16 *%ptr1
   %shr = lshr i16 %val, 1
   store i16 %shr, i16 *%ptr2
   ret void
diff --git a/test/CodeGen/SystemZ/int-move-09.ll b/test/CodeGen/SystemZ/int-move-09.ll
index b5c9cb13d288..6476842dd12b 100644
--- a/test/CodeGen/SystemZ/int-move-09.ll
+++ b/test/CodeGen/SystemZ/int-move-09.ll
@@ -20,7 +20,7 @@ define i64 @f1() {
 ; CHECK-LABEL: f1:
 ; CHECK: lghrl %r2, gsrc16
 ; CHECK: br %r14
-  %val = load i16 *@gsrc16
+  %val = load i16 , i16 *@gsrc16
   %ext = sext i16 %val to i64
   ret i64 %ext
 }
@@ -30,7 +30,7 @@ define i64 @f2() {
 ; CHECK-LABEL: f2:
 ; CHECK: llghrl %r2, gsrc16
 ; CHECK: br %r14
-  %val = load i16 *@gsrc16
+  %val = load i16 , i16 *@gsrc16
   %ext = zext i16 %val to i64
   ret i64 %ext
 }
@@ -40,7 +40,7 @@ define i64 @f3() {
 ; CHECK-LABEL: f3:
 ; CHECK: lgfrl %r2, gsrc32
 ; CHECK: br %r14
-  %val = load i32 *@gsrc32
+  %val = load i32 , i32 *@gsrc32
   %ext = sext i32 %val to i64
   ret i64 %ext
 }
@@ -50,7 +50,7 @@ define i64 @f4() {
 ; CHECK-LABEL: f4:
 ; CHECK: llgfrl %r2, gsrc32
 ; CHECK: br %r14
-  %val = load i32 *@gsrc32
+  %val = load i32 , i32 *@gsrc32
   %ext = zext i32 %val to i64
   ret i64 %ext
 }
@@ -81,7 +81,7 @@ define void @f7() {
 ; CHECK: lgrl %r0, gsrc64
 ; CHECK: stgrl %r0, gdst64
 ; CHECK: br %r14
-  %val = load i64 *@gsrc64
+  %val = load i64 , i64 *@gsrc64
   store i64 %val, i64 *@gdst64
   ret void
 }
@@ -92,7 +92,7 @@ define i64 @f8() {
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
 ; CHECK: lgh %r2, 0([[REG]])
 ; CHECK: br %r14
-  %val = load i16 *@gsrc16u, align 1
+  %val = load i16 , i16 *@gsrc16u, align 1
   %ext = sext i16 %val to i64
   ret i64 %ext
 }
@@ -103,7 +103,7 @@ define i64 @f9() {
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
 ; CHECK: llgh %r2, 0([[REG]])
 ; CHECK: br %r14
-  %val = load i16 *@gsrc16u, align 1
+  %val = load i16 , i16 *@gsrc16u, align 1
   %ext = zext i16 %val to i64
   ret i64 %ext
 }
@@ -114,7 +114,7 @@ define i64 @f10() {
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: lgf %r2, 0([[REG]])
 ; CHECK: br %r14
-  %val = load i32 *@gsrc32u, align 2
+  %val = load i32 , i32 *@gsrc32u, align 2
   %ext = sext i32 %val to i64
   ret i64 %ext
 }
@@ -125,7 +125,7 @@ define i64 @f11() {
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: llgf %r2, 0([[REG]])
 ; CHECK: br %r14
-  %val = load i32 *@gsrc32u, align 2
+  %val = load i32 , i32 *@gsrc32u, align 2
   %ext = zext i32 %val to i64
   ret i64 %ext
 }
@@ -160,7 +160,7 @@ define void @f14() {
 ; CHECK: larl [[REG:%r[0-5]]], gdst64u
 ; CHECK: stg [[VAL]], 0([[REG]])
 ; CHECK: br %r14
-  %val = load i64 *@gsrc64u, align 4
+  %val = load i64 , i64 *@gsrc64u, align 4
   store i64 %val, i64 *@gdst64u, align 4
   ret void
 }
diff --git a/test/CodeGen/SystemZ/int-mul-01.ll b/test/CodeGen/SystemZ/int-mul-01.ll
index d5f7155f8c48..b0adc1874b9f 100644
--- a/test/CodeGen/SystemZ/int-mul-01.ll
+++ b/test/CodeGen/SystemZ/int-mul-01.ll
@@ -8,7 +8,7 @@ define i32 @f1(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f1:
 ; CHECK: mh %r2, 0(%r3)
 ; CHECK: br %r14
-  %half = load i16 *%src
+  %half = load i16 , i16 *%src
   %rhs = sext i16 %half to i32
   %res = mul i32 %lhs, %rhs
   ret i32 %res
@@ -19,8 +19,8 @@ define i32 @f2(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: mh %r2, 4094(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 2047
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 2047
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = mul i32 %lhs, %rhs
   ret i32 %res
@@ -31,8 +31,8 @@ define i32 @f3(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: mhy %r2, 4096(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 2048
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 2048
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = mul i32 %lhs, %rhs
   ret i32 %res
@@ -43,8 +43,8 @@ define i32 @f4(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: mhy %r2, 524286(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262143
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262143
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = mul i32 %lhs, %rhs
   ret i32 %res
@@ -57,8 +57,8 @@ define i32 @f5(i32 %lhs, i16 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: mh %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262144
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = mul i32 %lhs, %rhs
   ret i32 %res
@@ -69,8 +69,8 @@ define i32 @f6(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: mhy %r2, -2(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -1
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -1
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = mul i32 %lhs, %rhs
   ret i32 %res
@@ -81,8 +81,8 @@ define i32 @f7(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: mhy %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262144
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = mul i32 %lhs, %rhs
   ret i32 %res
@@ -95,8 +95,8 @@ define i32 @f8(i32 %lhs, i16 *%src) {
 ; CHECK: agfi %r3, -524290
 ; CHECK: mh %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262145
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262145
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = mul i32 %lhs, %rhs
   ret i32 %res
@@ -110,7 +110,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4094
   %ptr = inttoptr i64 %add2 to i16 *
-  %half = load i16 *%ptr
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = mul i32 %lhs, %rhs
   ret i32 %res
@@ -124,7 +124,7 @@ define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i16 *
-  %half = load i16 *%ptr
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = mul i32 %lhs, %rhs
   ret i32 %res
diff --git a/test/CodeGen/SystemZ/int-mul-02.ll b/test/CodeGen/SystemZ/int-mul-02.ll
index d002a7f2f9bd..265674f6c667 100644
--- a/test/CodeGen/SystemZ/int-mul-02.ll
+++ b/test/CodeGen/SystemZ/int-mul-02.ll
@@ -18,7 +18,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: ms %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %mul = mul i32 %a, %b
   ret i32 %mul
 }
@@ -28,8 +28,8 @@ define i32 @f3(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: ms %r2, 4092(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1023
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 1023
+  %b = load i32 , i32 *%ptr
   %mul = mul i32 %a, %b
   ret i32 %mul
 }
@@ -39,8 +39,8 @@ define i32 @f4(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: msy %r2, 4096(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1024
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 1024
+  %b = load i32 , i32 *%ptr
   %mul = mul i32 %a, %b
   ret i32 %mul
 }
@@ -50,8 +50,8 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: msy %r2, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %b = load i32 , i32 *%ptr
   %mul = mul i32 %a, %b
   ret i32 %mul
 }
@@ -63,8 +63,8 @@ define i32 @f6(i32 %a, i32 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: ms %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %b = load i32 , i32 *%ptr
   %mul = mul i32 %a, %b
   ret i32 %mul
 }
@@ -74,8 +74,8 @@ define i32 @f7(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: msy %r2, -4(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %b = load i32 , i32 *%ptr
   %mul = mul i32 %a, %b
   ret i32 %mul
 }
@@ -85,8 +85,8 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f8:
 ; CHECK: msy %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %b = load i32 , i32 *%ptr
   %mul = mul i32 %a, %b
   ret i32 %mul
 }
@@ -98,8 +98,8 @@ define i32 @f9(i32 %a, i32 *%src) {
 ; CHECK: agfi %r3, -524292
 ; CHECK: ms %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %b = load i32 , i32 *%ptr
   %mul = mul i32 %a, %b
   ret i32 %mul
 }
@@ -112,7 +112,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4092
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %mul = mul i32 %a, %b
   ret i32 %mul
 }
@@ -125,7 +125,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %mul = mul i32 %a, %b
   ret i32 %mul
 }
@@ -136,26 +136,26 @@ define i32 @f12(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: ms %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-  %ptr9 = getelementptr i32 *%ptr0, i64 18
-
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
-  %val9 = load i32 *%ptr9
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32, i32 *%ptr0, i64 18
+
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
+  %val9 = load i32 , i32 *%ptr9
 
   %ret = call i32 @foo()
 
diff --git a/test/CodeGen/SystemZ/int-mul-03.ll b/test/CodeGen/SystemZ/int-mul-03.ll
index df18050d0242..c4d16cefc1c2 100644
--- a/test/CodeGen/SystemZ/int-mul-03.ll
+++ b/test/CodeGen/SystemZ/int-mul-03.ll
@@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: msgf %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %bext = sext i32 %b to i64
   %mul = mul i64 %a, %bext
   ret i64 %mul
@@ -30,8 +30,8 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: msgf %r2, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %mul = mul i64 %a, %bext
   ret i64 %mul
@@ -44,8 +44,8 @@ define i64 @f4(i64 %a, i32 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: msgf %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %mul = mul i64 %a, %bext
   ret i64 %mul
@@ -56,8 +56,8 @@ define i64 @f5(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: msgf %r2, -4(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %mul = mul i64 %a, %bext
   ret i64 %mul
@@ -68,8 +68,8 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: msgf %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %mul = mul i64 %a, %bext
   ret i64 %mul
@@ -82,8 +82,8 @@ define i64 @f7(i64 %a, i32 *%src) {
 ; CHECK: agfi %r3, -524292
 ; CHECK: msgf %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %mul = mul i64 %a, %bext
   ret i64 %mul
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524284
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %mul = mul i64 %a, %bext
   ret i64 %mul
@@ -109,26 +109,26 @@ define i64 @f9(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: msgf %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-  %ptr9 = getelementptr i32 *%ptr0, i64 18
-
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
-  %val9 = load i32 *%ptr9
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32, i32 *%ptr0, i64 18
+
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
+  %val9 = load i32 , i32 *%ptr9
 
   %frob0 = add i32 %val0, 100
   %frob1 = add i32 %val1, 100
diff --git a/test/CodeGen/SystemZ/int-mul-04.ll b/test/CodeGen/SystemZ/int-mul-04.ll
index 183a9a748c37..1ec466174bc7 100644
--- a/test/CodeGen/SystemZ/int-mul-04.ll
+++ b/test/CodeGen/SystemZ/int-mul-04.ll
@@ -18,7 +18,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: msg %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i64 *%src
+  %b = load i64 , i64 *%src
   %mul = mul i64 %a, %b
   ret i64 %mul
 }
@@ -28,8 +28,8 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: msg %r2, 524280(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65535
+  %b = load i64 , i64 *%ptr
   %mul = mul i64 %a, %b
   ret i64 %mul
 }
@@ -41,8 +41,8 @@ define i64 @f4(i64 %a, i64 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: msg %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65536
+  %b = load i64 , i64 *%ptr
   %mul = mul i64 %a, %b
   ret i64 %mul
 }
@@ -52,8 +52,8 @@ define i64 @f5(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: msg %r2, -8(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -1
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -1
+  %b = load i64 , i64 *%ptr
   %mul = mul i64 %a, %b
   ret i64 %mul
 }
@@ -63,8 +63,8 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: msg %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
+  %b = load i64 , i64 *%ptr
   %mul = mul i64 %a, %b
   ret i64 %mul
 }
@@ -76,8 +76,8 @@ define i64 @f7(i64 %a, i64 *%src) {
 ; CHECK: agfi %r3, -524296
 ; CHECK: msg %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
+  %b = load i64 , i64 *%ptr
   %mul = mul i64 %a, %b
   ret i64 %mul
 }
@@ -90,7 +90,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524280
   %ptr = inttoptr i64 %add2 to i64 *
-  %b = load i64 *%ptr
+  %b = load i64 , i64 *%ptr
   %mul = mul i64 %a, %b
   ret i64 %mul
 }
@@ -101,26 +101,26 @@ define i64 @f9(i64 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: msg %r2, 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i64 *%ptr0, i64 2
-  %ptr2 = getelementptr i64 *%ptr0, i64 4
-  %ptr3 = getelementptr i64 *%ptr0, i64 6
-  %ptr4 = getelementptr i64 *%ptr0, i64 8
-  %ptr5 = getelementptr i64 *%ptr0, i64 10
-  %ptr6 = getelementptr i64 *%ptr0, i64 12
-  %ptr7 = getelementptr i64 *%ptr0, i64 14
-  %ptr8 = getelementptr i64 *%ptr0, i64 16
-  %ptr9 = getelementptr i64 *%ptr0, i64 18
+  %ptr1 = getelementptr i64, i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64, i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64, i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64, i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64, i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64, i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64, i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64, i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64, i64 *%ptr0, i64 18
 
-  %val0 = load i64 *%ptr0
-  %val1 = load i64 *%ptr1
-  %val2 = load i64 *%ptr2
-  %val3 = load i64 *%ptr3
-  %val4 = load i64 *%ptr4
-  %val5 = load i64 *%ptr5
-  %val6 = load i64 *%ptr6
-  %val7 = load i64 *%ptr7
-  %val8 = load i64 *%ptr8
-  %val9 = load i64 *%ptr9
+  %val0 = load i64 , i64 *%ptr0
+  %val1 = load i64 , i64 *%ptr1
+  %val2 = load i64 , i64 *%ptr2
+  %val3 = load i64 , i64 *%ptr3
+  %val4 = load i64 , i64 *%ptr4
+  %val5 = load i64 , i64 *%ptr5
+  %val6 = load i64 , i64 *%ptr6
+  %val7 = load i64 , i64 *%ptr7
+  %val8 = load i64 , i64 *%ptr8
+  %val9 = load i64 , i64 *%ptr9
 
   %ret = call i64 @foo()
 
diff --git a/test/CodeGen/SystemZ/int-mul-08.ll b/test/CodeGen/SystemZ/int-mul-08.ll
index 90b26a4f3dde..c43089677ff5 100644
--- a/test/CodeGen/SystemZ/int-mul-08.ll
+++ b/test/CodeGen/SystemZ/int-mul-08.ll
@@ -88,7 +88,7 @@ define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: mlg %r2, 0(%r4)
 ; CHECK: br %r14
-  %b = load i64 *%src
+  %b = load i64 , i64 *%src
   %ax = zext i64 %a to i128
   %bx = zext i64 %b to i128
   %mulx = mul i128 %ax, %bx
@@ -102,8 +102,8 @@ define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: mlg %r2, 524280(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65535
+  %b = load i64 , i64 *%ptr
   %ax = zext i64 %a to i128
   %bx = zext i64 %b to i128
   %mulx = mul i128 %ax, %bx
@@ -119,8 +119,8 @@ define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK: agfi %r4, 524288
 ; CHECK: mlg %r2, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65536
+  %b = load i64 , i64 *%ptr
   %ax = zext i64 %a to i128
   %bx = zext i64 %b to i128
   %mulx = mul i128 %ax, %bx
@@ -134,8 +134,8 @@ define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK-LABEL: f9:
 ; CHECK: mlg %r2, -8(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -1
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -1
+  %b = load i64 , i64 *%ptr
   %ax = zext i64 %a to i128
   %bx = zext i64 %b to i128
   %mulx = mul i128 %ax, %bx
@@ -149,8 +149,8 @@ define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
 ; CHECK-LABEL: f10:
 ; CHECK: mlg %r2, -524288(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
+  %b = load i64 , i64 *%ptr
   %ax = zext i64 %a to i128
   %bx = zext i64 %b to i128
   %mulx = mul i128 %ax, %bx
@@ -166,8 +166,8 @@ define i64 @f11(i64 *%dest, i64 %a, i64 *%src) {
 ; CHECK: agfi %r4, -524296
 ; CHECK: mlg %r2, 0(%r4)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
+  %b = load i64 , i64 *%ptr
   %ax = zext i64 %a to i128
   %bx = zext i64 %b to i128
   %mulx = mul i128 %ax, %bx
@@ -184,7 +184,7 @@ define i64 @f12(i64 *%dest, i64 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i64 *
-  %b = load i64 *%ptr
+  %b = load i64 , i64 *%ptr
   %ax = zext i64 %a to i128
   %bx = zext i64 %b to i128
   %mulx = mul i128 %ax, %bx
@@ -199,26 +199,26 @@ define i64 @f13(i64 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mlg {{%r[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i64 *%ptr0, i64 2
-  %ptr2 = getelementptr i64 *%ptr0, i64 4
-  %ptr3 = getelementptr i64 *%ptr0, i64 6
-  %ptr4 = getelementptr i64 *%ptr0, i64 8
-  %ptr5 = getelementptr i64 *%ptr0, i64 10
-  %ptr6 = getelementptr i64 *%ptr0, i64 12
-  %ptr7 = getelementptr i64 *%ptr0, i64 14
-  %ptr8 = getelementptr i64 *%ptr0, i64 16
-  %ptr9 = getelementptr i64 *%ptr0, i64 18
+  %ptr1 = getelementptr i64, i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64, i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64, i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64, i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64, i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64, i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64, i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64, i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64, i64 *%ptr0, i64 18
 
-  %val0 = load i64 *%ptr0
-  %val1 = load i64 *%ptr1
-  %val2 = load i64 *%ptr2
-  %val3 = load i64 *%ptr3
-  %val4 = load i64 *%ptr4
-  %val5 = load i64 *%ptr5
-  %val6 = load i64 *%ptr6
-  %val7 = load i64 *%ptr7
-  %val8 = load i64 *%ptr8
-  %val9 = load i64 *%ptr9
+  %val0 = load i64 , i64 *%ptr0
+  %val1 = load i64 , i64 *%ptr1
+  %val2 = load i64 , i64 *%ptr2
+  %val3 = load i64 , i64 *%ptr3
+  %val4 = load i64 , i64 *%ptr4
+  %val5 = load i64 , i64 *%ptr5
+  %val6 = load i64 , i64 *%ptr6
+  %val7 = load i64 , i64 *%ptr7
+  %val8 = load i64 , i64 *%ptr8
+  %val9 = load i64 , i64 *%ptr9
 
   %ret = call i64 @foo()
 
diff --git a/test/CodeGen/SystemZ/int-sub-01.ll b/test/CodeGen/SystemZ/int-sub-01.ll
index 8d1e56ddcaba..c04a619298da 100644
--- a/test/CodeGen/SystemZ/int-sub-01.ll
+++ b/test/CodeGen/SystemZ/int-sub-01.ll
@@ -19,7 +19,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %sub = sub i32 %a, %b
   ret i32 %sub
 }
@@ -29,8 +29,8 @@ define i32 @f3(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: s %r2, 4092(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1023
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 1023
+  %b = load i32 , i32 *%ptr
   %sub = sub i32 %a, %b
   ret i32 %sub
 }
@@ -40,8 +40,8 @@ define i32 @f4(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: sy %r2, 4096(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1024
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 1024
+  %b = load i32 , i32 *%ptr
   %sub = sub i32 %a, %b
   ret i32 %sub
 }
@@ -51,8 +51,8 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: sy %r2, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %b = load i32 , i32 *%ptr
   %sub = sub i32 %a, %b
   ret i32 %sub
 }
@@ -64,8 +64,8 @@ define i32 @f6(i32 %a, i32 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %b = load i32 , i32 *%ptr
   %sub = sub i32 %a, %b
   ret i32 %sub
 }
@@ -75,8 +75,8 @@ define i32 @f7(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: sy %r2, -4(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %b = load i32 , i32 *%ptr
   %sub = sub i32 %a, %b
   ret i32 %sub
 }
@@ -86,8 +86,8 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f8:
 ; CHECK: sy %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %b = load i32 , i32 *%ptr
   %sub = sub i32 %a, %b
   ret i32 %sub
 }
@@ -99,8 +99,8 @@ define i32 @f9(i32 %a, i32 *%src) {
 ; CHECK: agfi %r3, -524292
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %b = load i32 , i32 *%ptr
   %sub = sub i32 %a, %b
   ret i32 %sub
 }
@@ -113,7 +113,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4092
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %sub = sub i32 %a, %b
   ret i32 %sub
 }
@@ -126,7 +126,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %sub = sub i32 %a, %b
   ret i32 %sub
 }
@@ -137,26 +137,26 @@ define i32 @f12(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: s %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-  %ptr9 = getelementptr i32 *%ptr0, i64 18
-
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
-  %val9 = load i32 *%ptr9
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32, i32 *%ptr0, i64 18
+
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
+  %val9 = load i32 , i32 *%ptr9
 
   %ret = call i32 @foo()
 
diff --git a/test/CodeGen/SystemZ/int-sub-02.ll b/test/CodeGen/SystemZ/int-sub-02.ll
index a1c5ec50ee9c..23be240b0c5b 100644
--- a/test/CodeGen/SystemZ/int-sub-02.ll
+++ b/test/CodeGen/SystemZ/int-sub-02.ll
@@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: sgf %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %bext = sext i32 %b to i64
   %sub = sub i64 %a, %bext
   ret i64 %sub
@@ -30,8 +30,8 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: sgf %r2, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %sub = sub i64 %a, %bext
   ret i64 %sub
@@ -44,8 +44,8 @@ define i64 @f4(i64 %a, i32 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: sgf %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %sub = sub i64 %a, %bext
   ret i64 %sub
@@ -56,8 +56,8 @@ define i64 @f5(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: sgf %r2, -4(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %sub = sub i64 %a, %bext
   ret i64 %sub
@@ -68,8 +68,8 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: sgf %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %sub = sub i64 %a, %bext
   ret i64 %sub
@@ -82,8 +82,8 @@ define i64 @f7(i64 %a, i32 *%src) {
 ; CHECK: agfi %r3, -524292
 ; CHECK: sgf %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %sub = sub i64 %a, %bext
   ret i64 %sub
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524284
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %bext = sext i32 %b to i64
   %sub = sub i64 %a, %bext
   ret i64 %sub
@@ -109,26 +109,26 @@ define i64 @f9(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: sgf %r2, 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-  %ptr9 = getelementptr i32 *%ptr0, i64 18
-
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
-  %val9 = load i32 *%ptr9
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32, i32 *%ptr0, i64 18
+
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
+  %val9 = load i32 , i32 *%ptr9
 
   %frob0 = add i32 %val0, 100
   %frob1 = add i32 %val1, 100
diff --git a/test/CodeGen/SystemZ/int-sub-03.ll b/test/CodeGen/SystemZ/int-sub-03.ll
index 44edd84bda4f..9d5100644102 100644
--- a/test/CodeGen/SystemZ/int-sub-03.ll
+++ b/test/CodeGen/SystemZ/int-sub-03.ll
@@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: slgf %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %bext = zext i32 %b to i64
   %sub = sub i64 %a, %bext
   ret i64 %sub
@@ -30,8 +30,8 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: slgf %r2, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i64
   %sub = sub i64 %a, %bext
   ret i64 %sub
@@ -44,8 +44,8 @@ define i64 @f4(i64 %a, i32 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: slgf %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i64
   %sub = sub i64 %a, %bext
   ret i64 %sub
@@ -56,8 +56,8 @@ define i64 @f5(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: slgf %r2, -4(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i64
   %sub = sub i64 %a, %bext
   ret i64 %sub
@@ -68,8 +68,8 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: slgf %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i64
   %sub = sub i64 %a, %bext
   ret i64 %sub
@@ -82,8 +82,8 @@ define i64 @f7(i64 %a, i32 *%src) {
 ; CHECK: agfi %r3, -524292
 ; CHECK: slgf %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i64
   %sub = sub i64 %a, %bext
   ret i64 %sub
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524284
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i64
   %sub = sub i64 %a, %bext
   ret i64 %sub
@@ -109,26 +109,26 @@ define i64 @f9(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: slgf %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-  %ptr9 = getelementptr i32 *%ptr0, i64 18
-
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
-  %val9 = load i32 *%ptr9
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32, i32 *%ptr0, i64 18
+
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
+  %val9 = load i32 , i32 *%ptr9
 
   %frob0 = add i32 %val0, 100
   %frob1 = add i32 %val1, 100
diff --git a/test/CodeGen/SystemZ/int-sub-04.ll b/test/CodeGen/SystemZ/int-sub-04.ll
index 85104536c5d7..ec2944d12709 100644
--- a/test/CodeGen/SystemZ/int-sub-04.ll
+++ b/test/CodeGen/SystemZ/int-sub-04.ll
@@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i64 *%src
+  %b = load i64 , i64 *%src
   %sub = sub i64 %a, %b
   ret i64 %sub
 }
@@ -29,8 +29,8 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: sg %r2, 524280(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65535
+  %b = load i64 , i64 *%ptr
   %sub = sub i64 %a, %b
   ret i64 %sub
 }
@@ -42,8 +42,8 @@ define i64 @f4(i64 %a, i64 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65536
+  %b = load i64 , i64 *%ptr
   %sub = sub i64 %a, %b
   ret i64 %sub
 }
@@ -53,8 +53,8 @@ define i64 @f5(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: sg %r2, -8(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -1
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -1
+  %b = load i64 , i64 *%ptr
   %sub = sub i64 %a, %b
   ret i64 %sub
 }
@@ -64,8 +64,8 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: sg %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
+  %b = load i64 , i64 *%ptr
   %sub = sub i64 %a, %b
   ret i64 %sub
 }
@@ -77,8 +77,8 @@ define i64 @f7(i64 %a, i64 *%src) {
 ; CHECK: agfi %r3, -524296
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
+  %b = load i64 , i64 *%ptr
   %sub = sub i64 %a, %b
   ret i64 %sub
 }
@@ -91,7 +91,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524280
   %ptr = inttoptr i64 %add2 to i64 *
-  %b = load i64 *%ptr
+  %b = load i64 , i64 *%ptr
   %sub = sub i64 %a, %b
   ret i64 %sub
 }
@@ -102,26 +102,26 @@ define i64 @f9(i64 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: sg %r2, 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i64 *%ptr0, i64 2
-  %ptr2 = getelementptr i64 *%ptr0, i64 4
-  %ptr3 = getelementptr i64 *%ptr0, i64 6
-  %ptr4 = getelementptr i64 *%ptr0, i64 8
-  %ptr5 = getelementptr i64 *%ptr0, i64 10
-  %ptr6 = getelementptr i64 *%ptr0, i64 12
-  %ptr7 = getelementptr i64 *%ptr0, i64 14
-  %ptr8 = getelementptr i64 *%ptr0, i64 16
-  %ptr9 = getelementptr i64 *%ptr0, i64 18
+  %ptr1 = getelementptr i64, i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64, i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64, i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64, i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64, i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64, i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64, i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64, i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64, i64 *%ptr0, i64 18
 
-  %val0 = load i64 *%ptr0
-  %val1 = load i64 *%ptr1
-  %val2 = load i64 *%ptr2
-  %val3 = load i64 *%ptr3
-  %val4 = load i64 *%ptr4
-  %val5 = load i64 *%ptr5
-  %val6 = load i64 *%ptr6
-  %val7 = load i64 *%ptr7
-  %val8 = load i64 *%ptr8
-  %val9 = load i64 *%ptr9
+  %val0 = load i64 , i64 *%ptr0
+  %val1 = load i64 , i64 *%ptr1
+  %val2 = load i64 , i64 *%ptr2
+  %val3 = load i64 , i64 *%ptr3
+  %val4 = load i64 , i64 *%ptr4
+  %val5 = load i64 , i64 *%ptr5
+  %val6 = load i64 , i64 *%ptr6
+  %val7 = load i64 , i64 *%ptr7
+  %val8 = load i64 , i64 *%ptr8
+  %val9 = load i64 , i64 *%ptr9
 
   %ret = call i64 @foo()
 
diff --git a/test/CodeGen/SystemZ/int-sub-05.ll b/test/CodeGen/SystemZ/int-sub-05.ll
index 85ea14cd15f3..9775298a7a2e 100644
--- a/test/CodeGen/SystemZ/int-sub-05.ll
+++ b/test/CodeGen/SystemZ/int-sub-05.ll
@@ -11,7 +11,7 @@ define void @f1(i128 *%ptr, i64 %high, i64 %low) {
 ; CHECK: slgr {{%r[0-5]}}, %r4
 ; CHECK: slbgr {{%r[0-5]}}, %r3
 ; CHECK: br %r14
-  %a = load i128 *%ptr
+  %a = load i128 , i128 *%ptr
   %highx = zext i64 %high to i128
   %lowx = zext i64 %low to i128
   %bhigh = shl i128 %highx, 64
@@ -28,9 +28,9 @@ define void @f2(i64 %addr) {
 ; CHECK: slbg {{%r[0-5]}}, 0(%r2)
 ; CHECK: br %r14
   %bptr = inttoptr i64 %addr to i128 *
-  %aptr = getelementptr i128 *%bptr, i64 -8
-  %a = load i128 *%aptr
-  %b = load i128 *%bptr
+  %aptr = getelementptr i128, i128 *%bptr, i64 -8
+  %a = load i128 , i128 *%aptr
+  %b = load i128 , i128 *%bptr
   %sub = sub i128 %a, %b
   store i128 %sub, i128 *%aptr
   ret void
@@ -44,9 +44,9 @@ define void @f3(i64 %base) {
 ; CHECK: br %r14
   %addr = add i64 %base, 524272
   %bptr = inttoptr i64 %addr to i128 *
-  %aptr = getelementptr i128 *%bptr, i64 -8
-  %a = load i128 *%aptr
-  %b = load i128 *%bptr
+  %aptr = getelementptr i128, i128 *%bptr, i64 -8
+  %a = load i128 , i128 *%aptr
+  %b = load i128 , i128 *%bptr
   %sub = sub i128 %a, %b
   store i128 %sub, i128 *%aptr
   ret void
@@ -62,9 +62,9 @@ define void @f4(i64 %base) {
 ; CHECK: br %r14
   %addr = add i64 %base, 524280
   %bptr = inttoptr i64 %addr to i128 *
-  %aptr = getelementptr i128 *%bptr, i64 -8
-  %a = load i128 *%aptr
-  %b = load i128 *%bptr
+  %aptr = getelementptr i128, i128 *%bptr, i64 -8
+  %a = load i128 , i128 *%aptr
+  %b = load i128 , i128 *%bptr
   %sub = sub i128 %a, %b
   store i128 %sub, i128 *%aptr
   ret void
@@ -80,9 +80,9 @@ define void @f5(i64 %base) {
 ; CHECK: br %r14
   %addr = add i64 %base, 524288
   %bptr = inttoptr i64 %addr to i128 *
-  %aptr = getelementptr i128 *%bptr, i64 -8
-  %a = load i128 *%aptr
-  %b = load i128 *%bptr
+  %aptr = getelementptr i128, i128 *%bptr, i64 -8
+  %a = load i128 , i128 *%aptr
+  %b = load i128 , i128 *%bptr
   %sub = sub i128 %a, %b
   store i128 %sub, i128 *%aptr
   ret void
@@ -96,9 +96,9 @@ define void @f6(i64 %base) {
 ; CHECK: br %r14
   %addr = add i64 %base, -524288
   %bptr = inttoptr i64 %addr to i128 *
-  %aptr = getelementptr i128 *%bptr, i64 -8
-  %a = load i128 *%aptr
-  %b = load i128 *%bptr
+  %aptr = getelementptr i128, i128 *%bptr, i64 -8
+  %a = load i128 , i128 *%aptr
+  %b = load i128 , i128 *%bptr
   %sub = sub i128 %a, %b
   store i128 %sub, i128 *%aptr
   ret void
@@ -112,9 +112,9 @@ define void @f7(i64 %base) {
 ; CHECK: br %r14
   %addr = add i64 %base, -524296
   %bptr = inttoptr i64 %addr to i128 *
-  %aptr = getelementptr i128 *%bptr, i64 -8
-  %a = load i128 *%aptr
-  %b = load i128 *%bptr
+  %aptr = getelementptr i128, i128 *%bptr, i64 -8
+  %a = load i128 , i128 *%aptr
+  %b = load i128 , i128 *%bptr
   %sub = sub i128 %a, %b
   store i128 %sub, i128 *%aptr
   ret void
@@ -128,20 +128,20 @@ define void @f8(i128 *%ptr0) {
 ; CHECK: slg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
 ; CHECK: slbg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i128 *%ptr0, i128 2
-  %ptr2 = getelementptr i128 *%ptr0, i128 4
-  %ptr3 = getelementptr i128 *%ptr0, i128 6
-  %ptr4 = getelementptr i128 *%ptr0, i128 8
+  %ptr1 = getelementptr i128, i128 *%ptr0, i128 2
+  %ptr2 = getelementptr i128, i128 *%ptr0, i128 4
+  %ptr3 = getelementptr i128, i128 *%ptr0, i128 6
+  %ptr4 = getelementptr i128, i128 *%ptr0, i128 8
 
-  %val0 = load i128 *%ptr0
-  %val1 = load i128 *%ptr1
-  %val2 = load i128 *%ptr2
-  %val3 = load i128 *%ptr3
-  %val4 = load i128 *%ptr4
+  %val0 = load i128 , i128 *%ptr0
+  %val1 = load i128 , i128 *%ptr1
+  %val2 = load i128 , i128 *%ptr2
+  %val3 = load i128 , i128 *%ptr3
+  %val4 = load i128 , i128 *%ptr4
 
   %retptr = call i128 *@foo()
 
-  %ret = load i128 *%retptr
+  %ret = load i128 , i128 *%retptr
   %sub0 = sub i128 %ret, %val0
   %sub1 = sub i128 %sub0, %val1
   %sub2 = sub i128 %sub1, %val2
diff --git a/test/CodeGen/SystemZ/int-sub-06.ll b/test/CodeGen/SystemZ/int-sub-06.ll
index 395d584b23de..c26383e9df03 100644
--- a/test/CodeGen/SystemZ/int-sub-06.ll
+++ b/test/CodeGen/SystemZ/int-sub-06.ll
@@ -9,7 +9,7 @@ define void @f1(i128 *%aptr, i32 %b) {
 ; CHECK: slgfr {{%r[0-5]}}, %r3
 ; CHECK: slbgr
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
   %bext = zext i32 %b to i128
   %sub = sub i128 %xor, %bext
@@ -23,7 +23,7 @@ define void @f2(i128 *%aptr, i64 %b) {
 ; CHECK: slgfr {{%r[0-5]}}, %r3
 ; CHECK: slbgr
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
   %trunc = trunc i64 %b to i32
   %bext = zext i32 %trunc to i128
@@ -39,7 +39,7 @@ define void @f3(i128 *%aptr, i64 %b) {
 ; CHECK: slgfr {{%r[0-5]}}, %r3
 ; CHECK: slbgr
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
   %bext = zext i64 %b to i128
   %and = and i128 %bext, 4294967295
@@ -54,9 +54,9 @@ define void @f4(i128 *%aptr, i32 *%bsrc) {
 ; CHECK: slgf {{%r[0-5]}}, 0(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
-  %b = load i32 *%bsrc
+  %b = load i32 , i32 *%bsrc
   %bext = zext i32 %b to i128
   %sub = sub i128 %xor, %bext
   store i128 %sub, i128 *%aptr
@@ -69,10 +69,10 @@ define void @f5(i128 *%aptr, i32 *%bsrc) {
 ; CHECK: slgf {{%r[0-5]}}, 524284(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
-  %ptr = getelementptr i32 *%bsrc, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%bsrc, i64 131071
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i128
   %sub = sub i128 %xor, %bext
   store i128 %sub, i128 *%aptr
@@ -87,10 +87,10 @@ define void @f6(i128 *%aptr, i32 *%bsrc) {
 ; CHECK: slgf {{%r[0-5]}}, 0(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
-  %ptr = getelementptr i32 *%bsrc, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%bsrc, i64 131072
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i128
   %sub = sub i128 %xor, %bext
   store i128 %sub, i128 *%aptr
@@ -103,10 +103,10 @@ define void @f7(i128 *%aptr, i32 *%bsrc) {
 ; CHECK: slgf {{%r[0-5]}}, -4(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
-  %ptr = getelementptr i32 *%bsrc, i128 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%bsrc, i128 -1
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i128
   %sub = sub i128 %xor, %bext
   store i128 %sub, i128 *%aptr
@@ -119,10 +119,10 @@ define void @f8(i128 *%aptr, i32 *%bsrc) {
 ; CHECK: slgf {{%r[0-5]}}, -524288(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
-  %ptr = getelementptr i32 *%bsrc, i128 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%bsrc, i128 -131072
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i128
   %sub = sub i128 %xor, %bext
   store i128 %sub, i128 *%aptr
@@ -137,10 +137,10 @@ define void @f9(i128 *%aptr, i32 *%bsrc) {
 ; CHECK: slgf {{%r[0-5]}}, 0(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
-  %ptr = getelementptr i32 *%bsrc, i128 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%bsrc, i128 -131073
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i128
   %sub = sub i128 %xor, %bext
   store i128 %sub, i128 *%aptr
@@ -152,12 +152,12 @@ define void @f10(i128 *%aptr, i64 %src, i64 %index) {
 ; CHECK-LABEL: f10:
 ; CHECK: slgf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
-  %a = load i128 *%aptr
+  %a = load i128 , i128 *%aptr
   %xor = xor i128 %a, 127
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524284
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %bext = zext i32 %b to i128
   %sub = sub i128 %xor, %bext
   store i128 %sub, i128 *%aptr
diff --git a/test/CodeGen/SystemZ/int-sub-07.ll b/test/CodeGen/SystemZ/int-sub-07.ll
index 5c1f42c1cc96..1d54fd6714cf 100644
--- a/test/CodeGen/SystemZ/int-sub-07.ll
+++ b/test/CodeGen/SystemZ/int-sub-07.ll
@@ -8,7 +8,7 @@ define i32 @f1(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f1:
 ; CHECK: sh %r2, 0(%r3)
 ; CHECK: br %r14
-  %half = load i16 *%src
+  %half = load i16 , i16 *%src
   %rhs = sext i16 %half to i32
   %res = sub i32 %lhs, %rhs
   ret i32 %res
@@ -19,8 +19,8 @@ define i32 @f2(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: sh %r2, 4094(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 2047
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 2047
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = sub i32 %lhs, %rhs
   ret i32 %res
@@ -31,8 +31,8 @@ define i32 @f3(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: shy %r2, 4096(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 2048
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 2048
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = sub i32 %lhs, %rhs
   ret i32 %res
@@ -43,8 +43,8 @@ define i32 @f4(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: shy %r2, 524286(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262143
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262143
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = sub i32 %lhs, %rhs
   ret i32 %res
@@ -57,8 +57,8 @@ define i32 @f5(i32 %lhs, i16 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: sh %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262144
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = sub i32 %lhs, %rhs
   ret i32 %res
@@ -69,8 +69,8 @@ define i32 @f6(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: shy %r2, -2(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -1
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -1
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = sub i32 %lhs, %rhs
   ret i32 %res
@@ -81,8 +81,8 @@ define i32 @f7(i32 %lhs, i16 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: shy %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262144
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = sub i32 %lhs, %rhs
   ret i32 %res
@@ -95,8 +95,8 @@ define i32 @f8(i32 %lhs, i16 *%src) {
 ; CHECK: agfi %r3, -524290
 ; CHECK: sh %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262145
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262145
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = sub i32 %lhs, %rhs
   ret i32 %res
@@ -110,7 +110,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
   %sub1 = add i64 %src, %index
   %sub2 = add i64 %sub1, 4094
   %ptr = inttoptr i64 %sub2 to i16 *
-  %half = load i16 *%ptr
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = sub i32 %lhs, %rhs
   ret i32 %res
@@ -124,7 +124,7 @@ define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
   %sub1 = add i64 %src, %index
   %sub2 = add i64 %sub1, 4096
   %ptr = inttoptr i64 %sub2 to i16 *
-  %half = load i16 *%ptr
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i32
   %res = sub i32 %lhs, %rhs
   ret i32 %res
diff --git a/test/CodeGen/SystemZ/loop-01.ll b/test/CodeGen/SystemZ/loop-01.ll
index 580080173563..b51c96d52e3a 100644
--- a/test/CodeGen/SystemZ/loop-01.ll
+++ b/test/CodeGen/SystemZ/loop-01.ll
@@ -14,7 +14,7 @@ entry:
 
 loop:
   %index = phi i64 [ 0, %entry ], [ %next, %loop ]
-  %ptr = getelementptr i32 *%dest, i64 %index
+  %ptr = getelementptr i32, i32 *%dest, i64 %index
   store i32 %a, i32 *%ptr
   %next = add i64 %index, 1
   %cmp = icmp ne i64 %next, 100
@@ -37,7 +37,7 @@ entry:
 loop:
   %count = phi i32 [ 0, %entry ], [ %next, %loop.next ]
   %next = add i32 %count, 1
-  %val = load volatile i32 *%src
+  %val = load volatile i32 , i32 *%src
   %cmp = icmp eq i32 %val, 0
   br i1 %cmp, label %loop.next, label %loop.store
 
@@ -67,7 +67,7 @@ entry:
 loop:
   %count = phi i64 [ 0, %entry ], [ %next, %loop.next ]
   %next = add i64 %count, 1
-  %val = load volatile i64 *%src
+  %val = load volatile i64 , i64 *%src
   %cmp = icmp eq i64 %val, 0
   br i1 %cmp, label %loop.next, label %loop.store
 
@@ -100,7 +100,7 @@ entry:
 loop:
   %left = phi i64 [ %count, %entry ], [ %next, %loop.next ]
   store volatile i64 %left, i64 *%dest2
-  %val = load volatile i32 *%src
+  %val = load volatile i32 , i32 *%src
   %cmp = icmp eq i32 %val, 0
   br i1 %cmp, label %loop.next, label %loop.store
 
diff --git a/test/CodeGen/SystemZ/memchr-02.ll b/test/CodeGen/SystemZ/memchr-02.ll
index 8986627a6057..71b2cf02b352 100644
--- a/test/CodeGen/SystemZ/memchr-02.ll
+++ b/test/CodeGen/SystemZ/memchr-02.ll
@@ -29,7 +29,7 @@ define i8 *@f2(i8 *%src, i8 *%charptr, i64 %len) {
 ; CHECK-NOT: %r0
 ; CHECK: srst %r2, [[RES1]]
 ; CHECK: br %r14
-  %char = load volatile i8 *%charptr
+  %char = load volatile i8 , i8 *%charptr
   %charext = zext i8 %char to i32
   %res1 = call i8 *@memchr(i8 *%src, i32 %charext, i64 %len)
   %res2 = call i8 *@memchr(i8 *%res1, i32 %charext, i64 %len)
@@ -48,7 +48,7 @@ define i8 *@f3(i8 *%src, i8 *%charptr, i64 %len) {
 ; CHECK: lr %r0, [[CHAR]]
 ; CHECK: srst %r2, [[RES1]]
 ; CHECK: br %r14
-  %char = load volatile i8 *%charptr
+  %char = load volatile i8 , i8 *%charptr
   %charext = zext i8 %char to i32
   %res1 = call i8 *@memchr(i8 *%src, i32 %charext, i64 %len)
   call void asm sideeffect "blah $0", "{r0}" (i32 0)
diff --git a/test/CodeGen/SystemZ/memcpy-01.ll b/test/CodeGen/SystemZ/memcpy-01.ll
index b53ec5452e25..1d7b28e940b9 100644
--- a/test/CodeGen/SystemZ/memcpy-01.ll
+++ b/test/CodeGen/SystemZ/memcpy-01.ll
@@ -126,8 +126,8 @@ define void @f11(i8 *%srcbase, i8 *%destbase) {
 ; CHECK: mvc 512(256,[[NEWDEST]]), 0([[NEWSRC]])
 ; CHECK: mvc 768(255,[[NEWDEST]]), 256([[NEWSRC]])
 ; CHECK: br %r14
-  %dest = getelementptr i8 *%srcbase, i64 4000
-  %src = getelementptr i8* %destbase, i64 3500
+  %dest = getelementptr i8, i8 *%srcbase, i64 4000
+  %src = getelementptr i8, i8* %destbase, i64 3500
   call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 1279, i32 1,
                                        i1 false)
   ret void
@@ -146,8 +146,8 @@ define void @f12() {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: br %r14
   %arr = alloca [6000 x i8]
-  %dest = getelementptr [6000 x i8] *%arr, i64 0, i64 3900
-  %src = getelementptr [6000 x i8] *%arr, i64 0, i64 1924
+  %dest = getelementptr [6000 x i8], [6000 x i8] *%arr, i64 0, i64 3900
+  %src = getelementptr [6000 x i8], [6000 x i8] *%arr, i64 0, i64 1924
   call void @foo(i8 *%dest, i8 *%src)
   call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 1279, i32 1,
                                        i1 false)
@@ -168,8 +168,8 @@ define void @f13() {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: br %r14
   %arr = alloca [6000 x i8]
-  %dest = getelementptr [6000 x i8] *%arr, i64 0, i64 24
-  %src = getelementptr [6000 x i8] *%arr, i64 0, i64 3650
+  %dest = getelementptr [6000 x i8], [6000 x i8] *%arr, i64 0, i64 24
+  %src = getelementptr [6000 x i8], [6000 x i8] *%arr, i64 0, i64 3650
   call void @foo(i8 *%dest, i8 *%src)
   call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 1279, i32 1,
                                        i1 false)
@@ -225,8 +225,8 @@ define void @f16() {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: br %r14
   %arr = alloca [3200 x i8]
-  %dest = getelementptr [3200 x i8] *%arr, i64 0, i64 1600
-  %src = getelementptr [3200 x i8] *%arr, i64 0, i64 0
+  %dest = getelementptr [3200 x i8], [3200 x i8] *%arr, i64 0, i64 1600
+  %src = getelementptr [3200 x i8], [3200 x i8] *%arr, i64 0, i64 0
   call void @foo(i8 *%dest, i8 *%src)
   call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 1537, i32 1,
                                        i1 false)
diff --git a/test/CodeGen/SystemZ/memcpy-02.ll b/test/CodeGen/SystemZ/memcpy-02.ll
index 776cfee50be9..df44502a8098 100644
--- a/test/CodeGen/SystemZ/memcpy-02.ll
+++ b/test/CodeGen/SystemZ/memcpy-02.ll
@@ -16,8 +16,8 @@ define void @f1(i8 *%ptr1) {
 ; CHECK-LABEL: f1:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i8 *%ptr1, i64 1
-  %val = load i8 *%ptr1
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 1
+  %val = load i8 , i8 *%ptr1
   store i8 %val, i8 *%ptr2
   ret void
 }
@@ -27,8 +27,8 @@ define void @f2(i8 *%ptr1) {
 ; CHECK-LABEL: f2:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i8 *%ptr1, i64 1
-  %val = load i8 *%ptr1
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 1
+  %val = load i8 , i8 *%ptr1
   %ext = zext i8 %val to i32
   %trunc = trunc i32 %ext to i8
   store i8 %trunc, i8 *%ptr2
@@ -40,8 +40,8 @@ define void @f3(i8 *%ptr1) {
 ; CHECK-LABEL: f3:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i8 *%ptr1, i64 1
-  %val = load i8 *%ptr1
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 1
+  %val = load i8 , i8 *%ptr1
   %ext = zext i8 %val to i64
   %trunc = trunc i64 %ext to i8
   store i8 %trunc, i8 *%ptr2
@@ -53,8 +53,8 @@ define void @f4(i8 *%ptr1) {
 ; CHECK-LABEL: f4:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i8 *%ptr1, i64 1
-  %val = load i8 *%ptr1
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 1
+  %val = load i8 , i8 *%ptr1
   %ext = sext i8 %val to i32
   %trunc = trunc i32 %ext to i8
   store i8 %trunc, i8 *%ptr2
@@ -66,8 +66,8 @@ define void @f5(i8 *%ptr1) {
 ; CHECK-LABEL: f5:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i8 *%ptr1, i64 1
-  %val = load i8 *%ptr1
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 1
+  %val = load i8 , i8 *%ptr1
   %ext = sext i8 %val to i64
   %trunc = trunc i64 %ext to i8
   store i8 %trunc, i8 *%ptr2
@@ -79,8 +79,8 @@ define void @f6(i16 *%ptr1) {
 ; CHECK-LABEL: f6:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i16 *%ptr1, i64 1
-  %val = load i16 *%ptr1
+  %ptr2 = getelementptr i16, i16 *%ptr1, i64 1
+  %val = load i16 , i16 *%ptr1
   store i16 %val, i16 *%ptr2
   ret void
 }
@@ -90,8 +90,8 @@ define void @f7(i16 *%ptr1) {
 ; CHECK-LABEL: f7:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i16 *%ptr1, i64 1
-  %val = load i16 *%ptr1
+  %ptr2 = getelementptr i16, i16 *%ptr1, i64 1
+  %val = load i16 , i16 *%ptr1
   %ext = zext i16 %val to i32
   %trunc = trunc i32 %ext to i16
   store i16 %trunc, i16 *%ptr2
@@ -103,8 +103,8 @@ define void @f8(i16 *%ptr1) {
 ; CHECK-LABEL: f8:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i16 *%ptr1, i64 1
-  %val = load i16 *%ptr1
+  %ptr2 = getelementptr i16, i16 *%ptr1, i64 1
+  %val = load i16 , i16 *%ptr1
   %ext = zext i16 %val to i64
   %trunc = trunc i64 %ext to i16
   store i16 %trunc, i16 *%ptr2
@@ -116,8 +116,8 @@ define void @f9(i16 *%ptr1) {
 ; CHECK-LABEL: f9:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i16 *%ptr1, i64 1
-  %val = load i16 *%ptr1
+  %ptr2 = getelementptr i16, i16 *%ptr1, i64 1
+  %val = load i16 , i16 *%ptr1
   %ext = sext i16 %val to i32
   %trunc = trunc i32 %ext to i16
   store i16 %trunc, i16 *%ptr2
@@ -129,8 +129,8 @@ define void @f10(i16 *%ptr1) {
 ; CHECK-LABEL: f10:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i16 *%ptr1, i64 1
-  %val = load i16 *%ptr1
+  %ptr2 = getelementptr i16, i16 *%ptr1, i64 1
+  %val = load i16 , i16 *%ptr1
   %ext = sext i16 %val to i64
   %trunc = trunc i64 %ext to i16
   store i16 %trunc, i16 *%ptr2
@@ -142,8 +142,8 @@ define void @f11(i32 *%ptr1) {
 ; CHECK-LABEL: f11:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i32 *%ptr1, i64 1
-  %val = load i32 *%ptr1
+  %ptr2 = getelementptr i32, i32 *%ptr1, i64 1
+  %val = load i32 , i32 *%ptr1
   store i32 %val, i32 *%ptr2
   ret void
 }
@@ -153,8 +153,8 @@ define void @f12(i32 *%ptr1) {
 ; CHECK-LABEL: f12:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i32 *%ptr1, i64 1
-  %val = load i32 *%ptr1
+  %ptr2 = getelementptr i32, i32 *%ptr1, i64 1
+  %val = load i32 , i32 *%ptr1
   %ext = zext i32 %val to i64
   %trunc = trunc i64 %ext to i32
   store i32 %trunc, i32 *%ptr2
@@ -166,8 +166,8 @@ define void @f13(i32 *%ptr1) {
 ; CHECK-LABEL: f13:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i32 *%ptr1, i64 1
-  %val = load i32 *%ptr1
+  %ptr2 = getelementptr i32, i32 *%ptr1, i64 1
+  %val = load i32 , i32 *%ptr1
   %ext = sext i32 %val to i64
   %trunc = trunc i64 %ext to i32
   store i32 %trunc, i32 *%ptr2
@@ -179,8 +179,8 @@ define void @f14(i64 *%ptr1) {
 ; CHECK-LABEL: f14:
 ; CHECK: mvc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i64 *%ptr1, i64 1
-  %val = load i64 *%ptr1
+  %ptr2 = getelementptr i64, i64 *%ptr1, i64 1
+  %val = load i64 , i64 *%ptr1
   store i64 %val, i64 *%ptr2
   ret void
 }
@@ -190,8 +190,8 @@ define void @f15(float *%ptr1) {
 ; CHECK-LABEL: f15:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr float *%ptr1, i64 1
-  %val = load float *%ptr1
+  %ptr2 = getelementptr float, float *%ptr1, i64 1
+  %val = load float , float *%ptr1
   store float %val, float *%ptr2
   ret void
 }
@@ -201,8 +201,8 @@ define void @f16(double *%ptr1) {
 ; CHECK-LABEL: f16:
 ; CHECK: mvc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr double *%ptr1, i64 1
-  %val = load double *%ptr1
+  %ptr2 = getelementptr double, double *%ptr1, i64 1
+  %val = load double , double *%ptr1
   store double %val, double *%ptr2
   ret void
 }
@@ -212,8 +212,8 @@ define void @f17(fp128 *%ptr1) {
 ; CHECK-LABEL: f17:
 ; CHECK: mvc 16(16,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr fp128 *%ptr1, i64 1
-  %val = load fp128 *%ptr1
+  %ptr2 = getelementptr fp128, fp128 *%ptr1, i64 1
+  %val = load fp128 , fp128 *%ptr1
   store fp128 %val, fp128 *%ptr2
   ret void
 }
@@ -223,8 +223,8 @@ define void @f18(i64 *%ptr1) {
 ; CHECK-LABEL: f18:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
-  %ptr2 = getelementptr i64 *%ptr1, i64 1
-  %val = load volatile i64 *%ptr1
+  %ptr2 = getelementptr i64, i64 *%ptr1, i64 1
+  %val = load volatile i64 , i64 *%ptr1
   store i64 %val, i64 *%ptr2
   ret void
 }
@@ -234,8 +234,8 @@ define void @f19(i64 *%ptr1) {
 ; CHECK-LABEL: f19:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
-  %ptr2 = getelementptr i64 *%ptr1, i64 1
-  %val = load i64 *%ptr1
+  %ptr2 = getelementptr i64, i64 *%ptr1, i64 1
+  %val = load i64 , i64 *%ptr1
   store volatile i64 %val, i64 *%ptr2
   ret void
 }
@@ -247,7 +247,7 @@ define void @f20(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f20:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
-  %val = load i64 *%ptr1
+  %val = load i64 , i64 *%ptr1
   store i64 %val, i64 *%ptr2
   ret void
 }
@@ -257,7 +257,7 @@ define void @f21(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f21:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
-  %val = load i64 *%ptr1, align 2
+  %val = load i64 , i64 *%ptr1, align 2
   store i64 %val, i64 *%ptr2, align 2
   ret void
 }
@@ -270,7 +270,7 @@ define void @f22(i64 %base) {
   %add = add i64 %base, 1
   %ptr1 = inttoptr i64 %base to i64 *
   %ptr2 = inttoptr i64 %add to i64 *
-  %val = load i64 *%ptr1, align 1
+  %val = load i64 , i64 *%ptr1, align 1
   store i64 %val, i64 *%ptr2, align 1
   ret void
 }
@@ -282,7 +282,7 @@ define void @f23(i8 *%ptr) {
 ; CHECK-DAG: larl [[DST:%r[0-5]]], g1dst
 ; CHECK: mvc 0(1,[[DST]]), 0([[SRC]])
 ; CHECK: br %r14
-  %val = load i8 *@g1src
+  %val = load i8 , i8 *@g1src
   store i8 %val, i8 *@g1dst
   ret void
 }
@@ -293,7 +293,7 @@ define void @f24(i16 *%ptr) {
 ; CHECK: lhrl [[REG:%r[0-5]]], g2src
 ; CHECK: sthrl [[REG]], g2dst
 ; CHECK: br %r14
-  %val = load i16 *@g2src
+  %val = load i16 , i16 *@g2src
   store i16 %val, i16 *@g2dst
   ret void
 }
@@ -304,7 +304,7 @@ define void @f25(i32 *%ptr) {
 ; CHECK: lrl [[REG:%r[0-5]]], g3
 ; CHECK: st [[REG]], 0(%r2)
 ; CHECK: br %r14
-  %val = load i32 *@g3
+  %val = load i32 , i32 *@g3
   store i32 %val, i32 *%ptr
   ret void
 }
@@ -315,7 +315,7 @@ define void @f26(i32 *%ptr) {
 ; CHECK: l [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: strl [[REG]], g3
 ; CHECK: br %r14
-  %val = load i32 *%ptr
+  %val = load i32 , i32 *%ptr
   store i32 %val, i32 *@g3
   ret void
 }
@@ -326,7 +326,7 @@ define void @f27(i64 *%ptr) {
 ; CHECK: lgrl [[REG:%r[0-5]]], g4
 ; CHECK: stg [[REG]], 0(%r2)
 ; CHECK: br %r14
-  %val = load i64 *@g4
+  %val = load i64 , i64 *@g4
   store i64 %val, i64 *%ptr
   ret void
 }
@@ -337,7 +337,7 @@ define void @f28(i64 *%ptr) {
 ; CHECK: lg [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: stgrl [[REG]], g4
 ; CHECK: br %r14
-  %val = load i64 *%ptr
+  %val = load i64 , i64 *%ptr
   store i64 %val, i64 *@g4
   ret void
 }
@@ -349,7 +349,7 @@ define void @f29(fp128 *%ptr) {
 ; CHECK-DAG: larl [[DST:%r[0-5]]], g5dst
 ; CHECK: mvc 0(16,[[DST]]), 0([[SRC]])
 ; CHECK: br %r14
-  %val = load fp128 *@g5src, align 16
+  %val = load fp128 , fp128 *@g5src, align 16
   store fp128 %val, fp128 *@g5dst, align 16
   ret void
 }
@@ -359,8 +359,8 @@ define void @f30(i64 *%ptr1) {
 ; CHECK-LABEL: f30:
 ; CHECK: mvc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i64 *%ptr1, i64 1
-  %val = load i64 *%ptr1, align 1
+  %ptr2 = getelementptr i64, i64 *%ptr1, i64 1
+  %val = load i64 , i64 *%ptr1, align 1
   store i64 %val, i64 *%ptr2, align 1
   ret void
 }
@@ -370,7 +370,7 @@ define void @f31(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f31:
 ; CHECK: mvc 0(8,%r3), 0(%r2)
 ; CHECK: br %r14
-  %val = load i64 *%ptr1, align 2, !tbaa !1
+  %val = load i64 , i64 *%ptr1, align 2, !tbaa !1
   store i64 %val, i64 *%ptr2, align 2, !tbaa !2
   ret void
 }
@@ -380,7 +380,7 @@ define void @f32(i64 *%ptr1, i64 *%ptr2) {
 ; CHECK-LABEL: f32:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
-  %val = load i64 *%ptr1, align 2, !tbaa !1
+  %val = load i64 , i64 *%ptr1, align 2, !tbaa !1
   store i64 %val, i64 *%ptr2, align 2, !tbaa !1
   ret void
 }
diff --git a/test/CodeGen/SystemZ/or-01.ll b/test/CodeGen/SystemZ/or-01.ll
index 23946d320678..ce556ef85a1b 100644
--- a/test/CodeGen/SystemZ/or-01.ll
+++ b/test/CodeGen/SystemZ/or-01.ll
@@ -19,7 +19,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: o %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %or = or i32 %a, %b
   ret i32 %or
 }
@@ -29,8 +29,8 @@ define i32 @f3(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: o %r2, 4092(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1023
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 1023
+  %b = load i32 , i32 *%ptr
   %or = or i32 %a, %b
   ret i32 %or
 }
@@ -40,8 +40,8 @@ define i32 @f4(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: oy %r2, 4096(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1024
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 1024
+  %b = load i32 , i32 *%ptr
   %or = or i32 %a, %b
   ret i32 %or
 }
@@ -51,8 +51,8 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: oy %r2, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %b = load i32 , i32 *%ptr
   %or = or i32 %a, %b
   ret i32 %or
 }
@@ -64,8 +64,8 @@ define i32 @f6(i32 %a, i32 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: o %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %b = load i32 , i32 *%ptr
   %or = or i32 %a, %b
   ret i32 %or
 }
@@ -75,8 +75,8 @@ define i32 @f7(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: oy %r2, -4(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %b = load i32 , i32 *%ptr
   %or = or i32 %a, %b
   ret i32 %or
 }
@@ -86,8 +86,8 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f8:
 ; CHECK: oy %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %b = load i32 , i32 *%ptr
   %or = or i32 %a, %b
   ret i32 %or
 }
@@ -99,8 +99,8 @@ define i32 @f9(i32 %a, i32 *%src) {
 ; CHECK: agfi %r3, -524292
 ; CHECK: o %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %b = load i32 , i32 *%ptr
   %or = or i32 %a, %b
   ret i32 %or
 }
@@ -113,7 +113,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4092
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %or = or i32 %a, %b
   ret i32 %or
 }
@@ -126,7 +126,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %or = or i32 %a, %b
   ret i32 %or
 }
@@ -137,26 +137,26 @@ define i32 @f12(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: o %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-  %ptr9 = getelementptr i32 *%ptr0, i64 18
-
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
-  %val9 = load i32 *%ptr9
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32, i32 *%ptr0, i64 18
+
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
+  %val9 = load i32 , i32 *%ptr9
 
   %ret = call i32 @foo()
 
diff --git a/test/CodeGen/SystemZ/or-03.ll b/test/CodeGen/SystemZ/or-03.ll
index 5fdbdfd1ed1f..f29953796b06 100644
--- a/test/CodeGen/SystemZ/or-03.ll
+++ b/test/CodeGen/SystemZ/or-03.ll
@@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: og %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i64 *%src
+  %b = load i64 , i64 *%src
   %or = or i64 %a, %b
   ret i64 %or
 }
@@ -29,8 +29,8 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: og %r2, 524280(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65535
+  %b = load i64 , i64 *%ptr
   %or = or i64 %a, %b
   ret i64 %or
 }
@@ -42,8 +42,8 @@ define i64 @f4(i64 %a, i64 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: og %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65536
+  %b = load i64 , i64 *%ptr
   %or = or i64 %a, %b
   ret i64 %or
 }
@@ -53,8 +53,8 @@ define i64 @f5(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: og %r2, -8(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -1
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -1
+  %b = load i64 , i64 *%ptr
   %or = or i64 %a, %b
   ret i64 %or
 }
@@ -64,8 +64,8 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: og %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
+  %b = load i64 , i64 *%ptr
   %or = or i64 %a, %b
   ret i64 %or
 }
@@ -77,8 +77,8 @@ define i64 @f7(i64 %a, i64 *%src) {
 ; CHECK: agfi %r3, -524296
 ; CHECK: og %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
+  %b = load i64 , i64 *%ptr
   %or = or i64 %a, %b
   ret i64 %or
 }
@@ -91,7 +91,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524280
   %ptr = inttoptr i64 %add2 to i64 *
-  %b = load i64 *%ptr
+  %b = load i64 , i64 *%ptr
   %or = or i64 %a, %b
   ret i64 %or
 }
@@ -102,26 +102,26 @@ define i64 @f9(i64 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: og %r2, 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i64 *%ptr0, i64 2
-  %ptr2 = getelementptr i64 *%ptr0, i64 4
-  %ptr3 = getelementptr i64 *%ptr0, i64 6
-  %ptr4 = getelementptr i64 *%ptr0, i64 8
-  %ptr5 = getelementptr i64 *%ptr0, i64 10
-  %ptr6 = getelementptr i64 *%ptr0, i64 12
-  %ptr7 = getelementptr i64 *%ptr0, i64 14
-  %ptr8 = getelementptr i64 *%ptr0, i64 16
-  %ptr9 = getelementptr i64 *%ptr0, i64 18
+  %ptr1 = getelementptr i64, i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64, i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64, i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64, i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64, i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64, i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64, i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64, i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64, i64 *%ptr0, i64 18
 
-  %val0 = load i64 *%ptr0
-  %val1 = load i64 *%ptr1
-  %val2 = load i64 *%ptr2
-  %val3 = load i64 *%ptr3
-  %val4 = load i64 *%ptr4
-  %val5 = load i64 *%ptr5
-  %val6 = load i64 *%ptr6
-  %val7 = load i64 *%ptr7
-  %val8 = load i64 *%ptr8
-  %val9 = load i64 *%ptr9
+  %val0 = load i64 , i64 *%ptr0
+  %val1 = load i64 , i64 *%ptr1
+  %val2 = load i64 , i64 *%ptr2
+  %val3 = load i64 , i64 *%ptr3
+  %val4 = load i64 , i64 *%ptr4
+  %val5 = load i64 , i64 *%ptr5
+  %val6 = load i64 , i64 *%ptr6
+  %val7 = load i64 , i64 *%ptr7
+  %val8 = load i64 , i64 *%ptr8
+  %val9 = load i64 , i64 *%ptr9
 
   %ret = call i64 @foo()
 
diff --git a/test/CodeGen/SystemZ/or-05.ll b/test/CodeGen/SystemZ/or-05.ll
index d90589128674..3fb70d94b37d 100644
--- a/test/CodeGen/SystemZ/or-05.ll
+++ b/test/CodeGen/SystemZ/or-05.ll
@@ -7,7 +7,7 @@ define void @f1(i8 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: oi 0(%r2), 1
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %or = or i8 %val, -255
   store i8 %or, i8 *%ptr
   ret void
@@ -18,7 +18,7 @@ define void @f2(i8 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %or = or i8 %val, -2
   store i8 %or, i8 *%ptr
   ret void
@@ -29,7 +29,7 @@ define void @f3(i8 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: oi 0(%r2), 1
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %or = or i8 %val, 1
   store i8 %or, i8 *%ptr
   ret void
@@ -40,7 +40,7 @@ define void @f4(i8 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %or = or i8 %val, 254
   store i8 %or, i8 *%ptr
   ret void
@@ -51,8 +51,8 @@ define void @f5(i8 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: oi 4095(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4095
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 4095
+  %val = load i8 , i8 *%ptr
   %or = or i8 %val, 127
   store i8 %or, i8 *%ptr
   ret void
@@ -63,8 +63,8 @@ define void @f6(i8 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: oiy 4096(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4096
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 4096
+  %val = load i8 , i8 *%ptr
   %or = or i8 %val, 127
   store i8 %or, i8 *%ptr
   ret void
@@ -75,8 +75,8 @@ define void @f7(i8 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: oiy 524287(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524287
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524287
+  %val = load i8 , i8 *%ptr
   %or = or i8 %val, 127
   store i8 %or, i8 *%ptr
   ret void
@@ -89,8 +89,8 @@ define void @f8(i8 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: oi 0(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524288
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524288
+  %val = load i8 , i8 *%ptr
   %or = or i8 %val, 127
   store i8 %or, i8 *%ptr
   ret void
@@ -101,8 +101,8 @@ define void @f9(i8 *%src) {
 ; CHECK-LABEL: f9:
 ; CHECK: oiy -1(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -1
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -1
+  %val = load i8 , i8 *%ptr
   %or = or i8 %val, 127
   store i8 %or, i8 *%ptr
   ret void
@@ -113,8 +113,8 @@ define void @f10(i8 *%src) {
 ; CHECK-LABEL: f10:
 ; CHECK: oiy -524288(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524288
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524288
+  %val = load i8 , i8 *%ptr
   %or = or i8 %val, 127
   store i8 %or, i8 *%ptr
   ret void
@@ -127,8 +127,8 @@ define void @f11(i8 *%src) {
 ; CHECK: agfi %r2, -524289
 ; CHECK: oi 0(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524289
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524289
+  %val = load i8 , i8 *%ptr
   %or = or i8 %val, 127
   store i8 %or, i8 *%ptr
   ret void
@@ -143,7 +143,7 @@ define void @f12(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4095
   %ptr = inttoptr i64 %add2 to i8 *
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %or = or i8 %val, 127
   store i8 %or, i8 *%ptr
   ret void
@@ -158,7 +158,7 @@ define void @f13(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i8 *
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %or = or i8 %val, 127
   store i8 %or, i8 *%ptr
   ret void
diff --git a/test/CodeGen/SystemZ/or-06.ll b/test/CodeGen/SystemZ/or-06.ll
index 0a865d350942..6f441f44b96a 100644
--- a/test/CodeGen/SystemZ/or-06.ll
+++ b/test/CodeGen/SystemZ/or-06.ll
@@ -8,7 +8,7 @@ define void @f1(i8 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %or = or i32 %ext, -2
   %trunc = trunc i32 %or to i8
@@ -21,7 +21,7 @@ define void @f2(i8 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %or = or i64 %ext, -2
   %trunc = trunc i64 %or to i8
@@ -34,7 +34,7 @@ define void @f3(i8 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %or = or i32 %ext, 254
   %trunc = trunc i32 %or to i8
@@ -47,7 +47,7 @@ define void @f4(i8 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %or = or i64 %ext, 254
   %trunc = trunc i64 %or to i8
@@ -60,7 +60,7 @@ define void @f5(i8 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %or = or i32 %ext, -2
   %trunc = trunc i32 %or to i8
@@ -73,7 +73,7 @@ define void @f6(i8 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %or = or i64 %ext, -2
   %trunc = trunc i64 %or to i8
@@ -86,7 +86,7 @@ define void @f7(i8 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %or = or i32 %ext, 254
   %trunc = trunc i32 %or to i8
@@ -99,7 +99,7 @@ define void @f8(i8 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %or = or i64 %ext, 254
   %trunc = trunc i64 %or to i8
diff --git a/test/CodeGen/SystemZ/or-08.ll b/test/CodeGen/SystemZ/or-08.ll
index 8f5bf3170bed..a9921b11e227 100644
--- a/test/CodeGen/SystemZ/or-08.ll
+++ b/test/CodeGen/SystemZ/or-08.ll
@@ -7,9 +7,9 @@ define void @f1(i8 *%ptr1) {
 ; CHECK-LABEL: f1:
 ; CHECK: oc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i8 *%ptr1, i64 1
-  %val = load i8 *%ptr1
-  %old = load i8 *%ptr2
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 1
+  %val = load i8 , i8 *%ptr1
+  %old = load i8 , i8 *%ptr2
   %or = or i8 %val, %old
   store i8 %or, i8 *%ptr2
   ret void
@@ -20,9 +20,9 @@ define void @f2(i16 *%ptr1) {
 ; CHECK-LABEL: f2:
 ; CHECK: oc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i16 *%ptr1, i64 1
-  %val = load i16 *%ptr1
-  %old = load i16 *%ptr2
+  %ptr2 = getelementptr i16, i16 *%ptr1, i64 1
+  %val = load i16 , i16 *%ptr1
+  %old = load i16 , i16 *%ptr2
   %or = or i16 %val, %old
   store i16 %or, i16 *%ptr2
   ret void
@@ -33,9 +33,9 @@ define void @f3(i32 *%ptr1) {
 ; CHECK-LABEL: f3:
 ; CHECK: oc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i32 *%ptr1, i64 1
-  %val = load i32 *%ptr1
-  %old = load i32 *%ptr2
+  %ptr2 = getelementptr i32, i32 *%ptr1, i64 1
+  %val = load i32 , i32 *%ptr1
+  %old = load i32 , i32 *%ptr2
   %or = or i32 %old, %val
   store i32 %or, i32 *%ptr2
   ret void
@@ -46,9 +46,9 @@ define void @f4(i64 *%ptr1) {
 ; CHECK-LABEL: f4:
 ; CHECK: oc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i64 *%ptr1, i64 1
-  %val = load i64 *%ptr1
-  %old = load i64 *%ptr2
+  %ptr2 = getelementptr i64, i64 *%ptr1, i64 1
+  %val = load i64 , i64 *%ptr1
+  %old = load i64 , i64 *%ptr2
   %or = or i64 %old, %val
   store i64 %or, i64 *%ptr2
   ret void
diff --git a/test/CodeGen/SystemZ/prefetch-01.ll b/test/CodeGen/SystemZ/prefetch-01.ll
index bb7fea99ca7c..814738022269 100644
--- a/test/CodeGen/SystemZ/prefetch-01.ll
+++ b/test/CodeGen/SystemZ/prefetch-01.ll
@@ -48,7 +48,7 @@ define void @f5(i8 *%base, i64 %index) {
 ; CHECK: pfd 2, -524288({{%r2,%r3|%r3,%r2}})
 ; CHECK: br %r14
   %add = add i64 %index, -524288
-  %ptr = getelementptr i8 *%base, i64 %add
+  %ptr = getelementptr i8, i8 *%base, i64 %add
   call void @llvm.prefetch(i8 *%ptr, i32 1, i32 0, i32 1)
   ret void
 }
@@ -59,7 +59,7 @@ define void @f6(i8 *%base, i64 %index) {
 ; CHECK: pfd 2, 524287({{%r2,%r3|%r3,%r2}})
 ; CHECK: br %r14
   %add = add i64 %index, 524287
-  %ptr = getelementptr i8 *%base, i64 %add
+  %ptr = getelementptr i8, i8 *%base, i64 %add
   call void @llvm.prefetch(i8 *%ptr, i32 1, i32 0, i32 1)
   ret void
 }
@@ -71,7 +71,7 @@ define void @f7(i8 *%base, i64 %index) {
 ; CHECK: pfd 2,
 ; CHECK: br %r14
   %add = add i64 %index, 524288
-  %ptr = getelementptr i8 *%base, i64 %add
+  %ptr = getelementptr i8, i8 *%base, i64 %add
   call void @llvm.prefetch(i8 *%ptr, i32 1, i32 0, i32 1)
   ret void
 }
@@ -81,7 +81,7 @@ define void @f8() {
 ; CHECK-LABEL: f8:
 ; CHECK: pfdrl 2, g
 ; CHECK: br %r14
-  %ptr = getelementptr [4096 x i8] *@g, i64 0, i64 0
+  %ptr = getelementptr [4096 x i8], [4096 x i8] *@g, i64 0, i64 0
   call void @llvm.prefetch(i8 *%ptr, i32 1, i32 0, i32 1)
   ret void
 }
diff --git a/test/CodeGen/SystemZ/risbg-03.ll b/test/CodeGen/SystemZ/risbg-03.ll
new file mode 100644
index 000000000000..c3c08ad17961
--- /dev/null
+++ b/test/CodeGen/SystemZ/risbg-03.ll
@@ -0,0 +1,30 @@
+; Test use of RISBG vs RISBGN on zEC12.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
+
+; On zEC12, we generally prefer RISBGN.
+define i64 @f1(i64 %a, i64 %b) {
+; CHECK-LABEL: f1:
+; CHECK: risbgn %r2, %r3, 60, 62, 0
+; CHECK: br %r14
+  %anda = and i64 %a, -15
+  %andb = and i64 %b, 14
+  %or = or i64 %anda, %andb
+  ret i64 %or
+}
+
+; But we may fall back to RISBG if we can use the condition code.
+define i64 @f2(i64 %a, i64 %b, i32* %c) {
+; CHECK-LABEL: f2:
+; CHECK: risbg %r2, %r3, 60, 62, 0
+; CHECK-NEXT: ipm
+; CHECK: br %r14
+  %anda = and i64 %a, -15
+  %andb = and i64 %b, 14
+  %or = or i64 %anda, %andb
+  %cmp = icmp sgt i64 %or, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* %c, align 4
+  ret i64 %or
+}
+
diff --git a/test/CodeGen/SystemZ/serialize-01.ll b/test/CodeGen/SystemZ/serialize-01.ll
index 7801fac8d472..4a245172465f 100644
--- a/test/CodeGen/SystemZ/serialize-01.ll
+++ b/test/CodeGen/SystemZ/serialize-01.ll
@@ -16,6 +16,6 @@ define i32 @f1(i32 *%src) {
 ; CHECK-FAST: bcr 14, %r0
 ; CHECK-FAST: l %r2, 0(%r2)
 ; CHECK-FAST: br %r14
-  %val = load volatile i32 *%src
+  %val = load volatile i32 , i32 *%src
   ret i32 %val
 }
diff --git a/test/CodeGen/SystemZ/shift-01.ll b/test/CodeGen/SystemZ/shift-01.ll
index 5dab36b379c4..3e838f56ae3f 100644
--- a/test/CodeGen/SystemZ/shift-01.ll
+++ b/test/CodeGen/SystemZ/shift-01.ll
@@ -108,7 +108,7 @@ define i32 @f11(i32 %a, i32 *%ptr) {
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: sll %r2, 0(%r1)
 ; CHECK: br %r14
-  %amt = load i32 *%ptr
+  %amt = load i32 , i32 *%ptr
   %shift = shl i32 %a, %amt
   ret i32 %shift
 }
diff --git a/test/CodeGen/SystemZ/shift-02.ll b/test/CodeGen/SystemZ/shift-02.ll
index 27e73cd3a1f8..43576dbddeb1 100644
--- a/test/CodeGen/SystemZ/shift-02.ll
+++ b/test/CodeGen/SystemZ/shift-02.ll
@@ -108,7 +108,7 @@ define i32 @f11(i32 %a, i32 *%ptr) {
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: srl %r2, 0(%r1)
 ; CHECK: br %r14
-  %amt = load i32 *%ptr
+  %amt = load i32 , i32 *%ptr
   %shift = lshr i32 %a, %amt
   ret i32 %shift
 }
diff --git a/test/CodeGen/SystemZ/shift-03.ll b/test/CodeGen/SystemZ/shift-03.ll
index c45ae48b4071..6803ff5ae311 100644
--- a/test/CodeGen/SystemZ/shift-03.ll
+++ b/test/CodeGen/SystemZ/shift-03.ll
@@ -108,7 +108,7 @@ define i32 @f11(i32 %a, i32 *%ptr) {
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: sra %r2, 0(%r1)
 ; CHECK: br %r14
-  %amt = load i32 *%ptr
+  %amt = load i32 , i32 *%ptr
   %shift = ashr i32 %a, %amt
   ret i32 %shift
 }
diff --git a/test/CodeGen/SystemZ/shift-04.ll b/test/CodeGen/SystemZ/shift-04.ll
index de2d74f27fa3..2a32872a69ce 100644
--- a/test/CodeGen/SystemZ/shift-04.ll
+++ b/test/CodeGen/SystemZ/shift-04.ll
@@ -180,7 +180,7 @@ define i32 @f14(i32 %a, i32 *%ptr) {
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: rll %r2, %r2, 0(%r1)
 ; CHECK: br %r14
-  %amt = load i32 *%ptr
+  %amt = load i32 , i32 *%ptr
   %amtb = sub i32 32, %amt
   %parta = shl i32 %a, %amt
   %partb = lshr i32 %a, %amtb
diff --git a/test/CodeGen/SystemZ/shift-05.ll b/test/CodeGen/SystemZ/shift-05.ll
index 833b2fbae1e5..240be3f9df1f 100644
--- a/test/CodeGen/SystemZ/shift-05.ll
+++ b/test/CodeGen/SystemZ/shift-05.ll
@@ -143,7 +143,7 @@ define i64 @f14(i64 %a, i64 *%ptr) {
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: sllg %r2, %r2, 0(%r1)
 ; CHECK: br %r14
-  %amt = load i64 *%ptr
+  %amt = load i64 , i64 *%ptr
   %shift = shl i64 %a, %amt
   ret i64 %shift
 }
diff --git a/test/CodeGen/SystemZ/shift-06.ll b/test/CodeGen/SystemZ/shift-06.ll
index 74cae1213a3e..d9b9f473fe7c 100644
--- a/test/CodeGen/SystemZ/shift-06.ll
+++ b/test/CodeGen/SystemZ/shift-06.ll
@@ -143,7 +143,7 @@ define i64 @f14(i64 %a, i64 *%ptr) {
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: srlg %r2, %r2, 0(%r1)
 ; CHECK: br %r14
-  %amt = load i64 *%ptr
+  %amt = load i64 , i64 *%ptr
   %shift = lshr i64 %a, %amt
   ret i64 %shift
 }
diff --git a/test/CodeGen/SystemZ/shift-07.ll b/test/CodeGen/SystemZ/shift-07.ll
index 712849df8ad1..161628864e1b 100644
--- a/test/CodeGen/SystemZ/shift-07.ll
+++ b/test/CodeGen/SystemZ/shift-07.ll
@@ -143,7 +143,7 @@ define i64 @f14(i64 %a, i64 *%ptr) {
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: srag %r2, %r2, 0(%r1)
 ; CHECK: br %r14
-  %amt = load i64 *%ptr
+  %amt = load i64 , i64 *%ptr
   %shift = ashr i64 %a, %amt
   ret i64 %shift
 }
diff --git a/test/CodeGen/SystemZ/shift-08.ll b/test/CodeGen/SystemZ/shift-08.ll
index 47283b50221c..0db53c92246d 100644
--- a/test/CodeGen/SystemZ/shift-08.ll
+++ b/test/CodeGen/SystemZ/shift-08.ll
@@ -181,7 +181,7 @@ define i64 @f14(i64 %a, i64 *%ptr) {
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: rllg %r2, %r2, 0(%r1)
 ; CHECK: br %r14
-  %amt = load i64 *%ptr
+  %amt = load i64 , i64 *%ptr
   %amtb = sub i64 64, %amt
   %parta = shl i64 %a, %amt
   %partb = lshr i64 %a, %amtb
diff --git a/test/CodeGen/SystemZ/spill-01.ll b/test/CodeGen/SystemZ/spill-01.ll
index c1f780c55d3c..a59c06f192b6 100644
--- a/test/CodeGen/SystemZ/spill-01.ll
+++ b/test/CodeGen/SystemZ/spill-01.ll
@@ -37,20 +37,20 @@ define void @f1(i32 *%ptr0) {
 ; CHECK-NOT: %r15
 ; CHECK: lmg
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i32 2
-  %ptr2 = getelementptr i32 *%ptr0, i32 4
-  %ptr3 = getelementptr i32 *%ptr0, i32 6
-  %ptr4 = getelementptr i32 *%ptr0, i32 8
-  %ptr5 = getelementptr i32 *%ptr0, i32 10
-  %ptr6 = getelementptr i32 *%ptr0, i32 12
-
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
+  %ptr1 = getelementptr i32, i32 *%ptr0, i32 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i32 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i32 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i32 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i32 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i32 12
+
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
 
   call void @foo()
 
@@ -73,24 +73,24 @@ define void @f2(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mvc [[OFFSET2]](4,{{%r[0-9]+}}), [[OFFSET1]](%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
 
   call void @foo()
 
@@ -115,24 +115,24 @@ define void @f3(i64 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mvc [[OFFSET]](8,{{%r[0-9]+}}), 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i64 *%ptr0, i64 2
-  %ptr2 = getelementptr i64 *%ptr0, i64 4
-  %ptr3 = getelementptr i64 *%ptr0, i64 6
-  %ptr4 = getelementptr i64 *%ptr0, i64 8
-  %ptr5 = getelementptr i64 *%ptr0, i64 10
-  %ptr6 = getelementptr i64 *%ptr0, i64 12
-  %ptr7 = getelementptr i64 *%ptr0, i64 14
-  %ptr8 = getelementptr i64 *%ptr0, i64 16
-
-  %val0 = load i64 *%ptr0
-  %val1 = load i64 *%ptr1
-  %val2 = load i64 *%ptr2
-  %val3 = load i64 *%ptr3
-  %val4 = load i64 *%ptr4
-  %val5 = load i64 *%ptr5
-  %val6 = load i64 *%ptr6
-  %val7 = load i64 *%ptr7
-  %val8 = load i64 *%ptr8
+  %ptr1 = getelementptr i64, i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64, i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64, i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64, i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64, i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64, i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64, i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64, i64 *%ptr0, i64 16
+
+  %val0 = load i64 , i64 *%ptr0
+  %val1 = load i64 , i64 *%ptr1
+  %val2 = load i64 , i64 *%ptr2
+  %val3 = load i64 , i64 *%ptr3
+  %val4 = load i64 , i64 *%ptr4
+  %val5 = load i64 , i64 *%ptr5
+  %val6 = load i64 , i64 *%ptr6
+  %val7 = load i64 , i64 *%ptr7
+  %val8 = load i64 , i64 *%ptr8
 
   call void @foo()
 
@@ -160,26 +160,26 @@ define void @f4(float *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mvc [[OFFSET2]](4,{{%r[0-9]+}}), [[OFFSET1]](%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr float *%ptr0, i64 2
-  %ptr2 = getelementptr float *%ptr0, i64 4
-  %ptr3 = getelementptr float *%ptr0, i64 6
-  %ptr4 = getelementptr float *%ptr0, i64 8
-  %ptr5 = getelementptr float *%ptr0, i64 10
-  %ptr6 = getelementptr float *%ptr0, i64 12
-  %ptr7 = getelementptr float *%ptr0, i64 14
-  %ptr8 = getelementptr float *%ptr0, i64 16
-  %ptr9 = getelementptr float *%ptr0, i64 18
-
-  %val0 = load float *%ptr0
-  %val1 = load float *%ptr1
-  %val2 = load float *%ptr2
-  %val3 = load float *%ptr3
-  %val4 = load float *%ptr4
-  %val5 = load float *%ptr5
-  %val6 = load float *%ptr6
-  %val7 = load float *%ptr7
-  %val8 = load float *%ptr8
-  %val9 = load float *%ptr9
+  %ptr1 = getelementptr float, float *%ptr0, i64 2
+  %ptr2 = getelementptr float, float *%ptr0, i64 4
+  %ptr3 = getelementptr float, float *%ptr0, i64 6
+  %ptr4 = getelementptr float, float *%ptr0, i64 8
+  %ptr5 = getelementptr float, float *%ptr0, i64 10
+  %ptr6 = getelementptr float, float *%ptr0, i64 12
+  %ptr7 = getelementptr float, float *%ptr0, i64 14
+  %ptr8 = getelementptr float, float *%ptr0, i64 16
+  %ptr9 = getelementptr float, float *%ptr0, i64 18
+
+  %val0 = load float , float *%ptr0
+  %val1 = load float , float *%ptr1
+  %val2 = load float , float *%ptr2
+  %val3 = load float , float *%ptr3
+  %val4 = load float , float *%ptr4
+  %val5 = load float , float *%ptr5
+  %val6 = load float , float *%ptr6
+  %val7 = load float , float *%ptr7
+  %val8 = load float , float *%ptr8
+  %val9 = load float , float *%ptr9
 
   call void @foo()
 
@@ -204,26 +204,26 @@ define void @f5(double *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mvc [[OFFSET]](8,{{%r[0-9]+}}), 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr double *%ptr0, i64 2
-  %ptr2 = getelementptr double *%ptr0, i64 4
-  %ptr3 = getelementptr double *%ptr0, i64 6
-  %ptr4 = getelementptr double *%ptr0, i64 8
-  %ptr5 = getelementptr double *%ptr0, i64 10
-  %ptr6 = getelementptr double *%ptr0, i64 12
-  %ptr7 = getelementptr double *%ptr0, i64 14
-  %ptr8 = getelementptr double *%ptr0, i64 16
-  %ptr9 = getelementptr double *%ptr0, i64 18
-
-  %val0 = load double *%ptr0
-  %val1 = load double *%ptr1
-  %val2 = load double *%ptr2
-  %val3 = load double *%ptr3
-  %val4 = load double *%ptr4
-  %val5 = load double *%ptr5
-  %val6 = load double *%ptr6
-  %val7 = load double *%ptr7
-  %val8 = load double *%ptr8
-  %val9 = load double *%ptr9
+  %ptr1 = getelementptr double, double *%ptr0, i64 2
+  %ptr2 = getelementptr double, double *%ptr0, i64 4
+  %ptr3 = getelementptr double, double *%ptr0, i64 6
+  %ptr4 = getelementptr double, double *%ptr0, i64 8
+  %ptr5 = getelementptr double, double *%ptr0, i64 10
+  %ptr6 = getelementptr double, double *%ptr0, i64 12
+  %ptr7 = getelementptr double, double *%ptr0, i64 14
+  %ptr8 = getelementptr double, double *%ptr0, i64 16
+  %ptr9 = getelementptr double, double *%ptr0, i64 18
+
+  %val0 = load double , double *%ptr0
+  %val1 = load double , double *%ptr1
+  %val2 = load double , double *%ptr2
+  %val3 = load double , double *%ptr3
+  %val4 = load double , double *%ptr4
+  %val5 = load double , double *%ptr5
+  %val6 = load double , double *%ptr6
+  %val7 = load double , double *%ptr7
+  %val8 = load double , double *%ptr8
+  %val9 = load double , double *%ptr9
 
   call void @foo()
 
@@ -246,24 +246,24 @@ define void @f6(i32 *%ptr0) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-
-  %val0 = load atomic i32 *%ptr0 unordered, align 4
-  %val1 = load atomic i32 *%ptr1 unordered, align 4
-  %val2 = load atomic i32 *%ptr2 unordered, align 4
-  %val3 = load atomic i32 *%ptr3 unordered, align 4
-  %val4 = load atomic i32 *%ptr4 unordered, align 4
-  %val5 = load atomic i32 *%ptr5 unordered, align 4
-  %val6 = load atomic i32 *%ptr6 unordered, align 4
-  %val7 = load atomic i32 *%ptr7 unordered, align 4
-  %val8 = load atomic i32 *%ptr8 unordered, align 4
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+
+  %val0 = load atomic i32 , i32 *%ptr0 unordered, align 4
+  %val1 = load atomic i32 , i32 *%ptr1 unordered, align 4
+  %val2 = load atomic i32 , i32 *%ptr2 unordered, align 4
+  %val3 = load atomic i32 , i32 *%ptr3 unordered, align 4
+  %val4 = load atomic i32 , i32 *%ptr4 unordered, align 4
+  %val5 = load atomic i32 , i32 *%ptr5 unordered, align 4
+  %val6 = load atomic i32 , i32 *%ptr6 unordered, align 4
+  %val7 = load atomic i32 , i32 *%ptr7 unordered, align 4
+  %val8 = load atomic i32 , i32 *%ptr8 unordered, align 4
 
   call void @foo()
 
@@ -285,24 +285,24 @@ define void @f7(i32 *%ptr0) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-
-  %val0 = load volatile i32 *%ptr0
-  %val1 = load volatile i32 *%ptr1
-  %val2 = load volatile i32 *%ptr2
-  %val3 = load volatile i32 *%ptr3
-  %val4 = load volatile i32 *%ptr4
-  %val5 = load volatile i32 *%ptr5
-  %val6 = load volatile i32 *%ptr6
-  %val7 = load volatile i32 *%ptr7
-  %val8 = load volatile i32 *%ptr8
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+
+  %val0 = load volatile i32 , i32 *%ptr0
+  %val1 = load volatile i32 , i32 *%ptr1
+  %val2 = load volatile i32 , i32 *%ptr2
+  %val3 = load volatile i32 , i32 *%ptr3
+  %val4 = load volatile i32 , i32 *%ptr4
+  %val5 = load volatile i32 , i32 *%ptr5
+  %val6 = load volatile i32 , i32 *%ptr6
+  %val7 = load volatile i32 , i32 *%ptr7
+  %val8 = load volatile i32 , i32 *%ptr8
 
   call void @foo()
 
@@ -324,16 +324,16 @@ define void @f8() {
 ; CHECK-LABEL: f8:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
-  %val0 = load i32 *@g0
-  %val1 = load i32 *@g1
-  %val2 = load i32 *@g2
-  %val3 = load i32 *@g3
-  %val4 = load i32 *@g4
-  %val5 = load i32 *@g5
-  %val6 = load i32 *@g6
-  %val7 = load i32 *@g7
-  %val8 = load i32 *@g8
-  %val9 = load i32 *@g9
+  %val0 = load i32 , i32 *@g0
+  %val1 = load i32 , i32 *@g1
+  %val2 = load i32 , i32 *@g2
+  %val3 = load i32 , i32 *@g3
+  %val4 = load i32 , i32 *@g4
+  %val5 = load i32 , i32 *@g5
+  %val6 = load i32 , i32 *@g6
+  %val7 = load i32 , i32 *@g7
+  %val8 = load i32 , i32 *@g8
+  %val9 = load i32 , i32 *@g9
 
   call void @foo()
 
@@ -356,16 +356,16 @@ define void @f9() {
 ; CHECK-LABEL: f9:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
-  %val0 = load i64 *@h0
-  %val1 = load i64 *@h1
-  %val2 = load i64 *@h2
-  %val3 = load i64 *@h3
-  %val4 = load i64 *@h4
-  %val5 = load i64 *@h5
-  %val6 = load i64 *@h6
-  %val7 = load i64 *@h7
-  %val8 = load i64 *@h8
-  %val9 = load i64 *@h9
+  %val0 = load i64 , i64 *@h0
+  %val1 = load i64 , i64 *@h1
+  %val2 = load i64 , i64 *@h2
+  %val3 = load i64 , i64 *@h3
+  %val4 = load i64 , i64 *@h4
+  %val5 = load i64 , i64 *@h5
+  %val6 = load i64 , i64 *@h6
+  %val7 = load i64 , i64 *@h7
+  %val8 = load i64 , i64 *@h8
+  %val9 = load i64 , i64 *@h9
 
   call void @foo()
 
@@ -400,16 +400,16 @@ define void @f10() {
 ; CHECK: stgrl [[REG]], h8
 ; CHECK: br %r14
 entry:
-  %val8 = load volatile i64 *@h8
-  %val0 = load volatile i64 *@h0
-  %val1 = load volatile i64 *@h1
-  %val2 = load volatile i64 *@h2
-  %val3 = load volatile i64 *@h3
-  %val4 = load volatile i64 *@h4
-  %val5 = load volatile i64 *@h5
-  %val6 = load volatile i64 *@h6
-  %val7 = load volatile i64 *@h7
-  %val9 = load volatile i64 *@h9
+  %val8 = load volatile i64 , i64 *@h8
+  %val0 = load volatile i64 , i64 *@h0
+  %val1 = load volatile i64 , i64 *@h1
+  %val2 = load volatile i64 , i64 *@h2
+  %val3 = load volatile i64 , i64 *@h3
+  %val4 = load volatile i64 , i64 *@h4
+  %val5 = load volatile i64 , i64 *@h5
+  %val6 = load volatile i64 , i64 *@h6
+  %val7 = load volatile i64 , i64 *@h7
+  %val9 = load volatile i64 , i64 *@h9
 
   call void @foo()
 
@@ -422,7 +422,7 @@ entry:
   store volatile i64 %val6, i64 *@h6
   store volatile i64 %val7, i64 *@h7
 
-  %check = load volatile i64 *@h0
+  %check = load volatile i64 , i64 *@h0
   %cond = icmp eq i64 %check, 0
   br i1 %cond, label %skip, label %fallthru
 
@@ -464,17 +464,17 @@ define void @f11() {
 ; CHECK-NOT: mvc [[OFFSET:[0-9]+]](8,%r15), [[OFFSET]](%r15)
 ; CHECK: br %r14
 entry:
-  %val0 = load volatile i64 *@h0
-  %val1 = load volatile i64 *@h1
-  %val2 = load volatile i64 *@h2
-  %val3 = load volatile i64 *@h3
-  %val4 = load volatile i64 *@h4
-  %val5 = load volatile i64 *@h5
-  %val6 = load volatile i64 *@h6
-  %val7 = load volatile i64 *@h7
-
-  %altval0 = load volatile i64 *@h0
-  %altval1 = load volatile i64 *@h1
+  %val0 = load volatile i64 , i64 *@h0
+  %val1 = load volatile i64 , i64 *@h1
+  %val2 = load volatile i64 , i64 *@h2
+  %val3 = load volatile i64 , i64 *@h3
+  %val4 = load volatile i64 , i64 *@h4
+  %val5 = load volatile i64 , i64 *@h5
+  %val6 = load volatile i64 , i64 *@h6
+  %val7 = load volatile i64 , i64 *@h7
+
+  %altval0 = load volatile i64 , i64 *@h0
+  %altval1 = load volatile i64 , i64 *@h1
 
   call void @foo()
 
@@ -487,7 +487,7 @@ entry:
   store volatile i64 %val6, i64 *@h6
   store volatile i64 %val7, i64 *@h7
 
-  %check = load volatile i64 *@h0
+  %check = load volatile i64 , i64 *@h0
   %cond = icmp eq i64 %check, 0
   br i1 %cond, label %a1, label %b1
 
diff --git a/test/CodeGen/SystemZ/strcpy-01.ll b/test/CodeGen/SystemZ/strcpy-01.ll
index 29bab629ecf8..d6d0edf494b1 100644
--- a/test/CodeGen/SystemZ/strcpy-01.ll
+++ b/test/CodeGen/SystemZ/strcpy-01.ll
@@ -43,7 +43,7 @@ define i32 @f3(i32 %dummy, i8 *%dest, i8 *%src, i32 *%resptr, i32 *%storeptr) {
 ; CHECK-NEXT: jo [[LABEL]]
 ; CHECK: mvhi 0(%r6), 0
 ; CHECK: br %r14
-  %res = load i32 *%resptr
+  %res = load i32 , i32 *%resptr
   %unused = call i8 *@strcpy(i8 *%dest, i8 *%src)
   store i32 0, i32 *%storeptr
   ret i32 %res
diff --git a/test/CodeGen/SystemZ/tail-call-mem-intrinsics.ll b/test/CodeGen/SystemZ/tail-call-mem-intrinsics.ll
new file mode 100644
index 000000000000..65cc394f8a98
--- /dev/null
+++ b/test/CodeGen/SystemZ/tail-call-mem-intrinsics.ll
@@ -0,0 +1,31 @@
+; RUN: llc -march=systemz < %s | FileCheck %s
+
+; CHECK-LABEL: tail_memcpy:
+; CHECK: jg memcpy
+define void @tail_memcpy(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 {
+entry:
+  tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: tail_memmove:
+; CHECK: jg memmove
+define void @tail_memmove(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 {
+entry:
+  tail call void @llvm.memmove.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: tail_memset:
+; CHECK: jg memset
+define void @tail_memset(i8* nocapture %p, i8 %c, i32 %n) #0 {
+entry:
+  tail call void @llvm.memset.p0i8.i32(i8* %p, i8 %c, i32 %n, i32 1, i1 false)
+  ret void
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0
+declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0
+declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) #0
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/SystemZ/tls-01.ll b/test/CodeGen/SystemZ/tls-01.ll
index 16bc8f6e500f..da7176c0599f 100644
--- a/test/CodeGen/SystemZ/tls-01.ll
+++ b/test/CodeGen/SystemZ/tls-01.ll
@@ -1,7 +1,7 @@
-; Test initial-exec TLS accesses.
+; Test local-exec TLS accesses.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-CP
+; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN
+; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-CP
 
 @x = thread_local global i32 0
 
diff --git a/test/CodeGen/SystemZ/tls-02.ll b/test/CodeGen/SystemZ/tls-02.ll
new file mode 100644
index 000000000000..15918d08a936
--- /dev/null
+++ b/test/CodeGen/SystemZ/tls-02.ll
@@ -0,0 +1,18 @@
+; Test initial-exec TLS accesses.
+;
+; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=CHECK-MAIN
+
+@x = thread_local(initialexec) global i32 0
+
+; The offset must be loaded from the GOT.  This TLS access model does
+; not use literal pool constants.
+define i32 *@foo() {
+; CHECK-MAIN-LABEL: foo:
+; CHECK-MAIN: ear [[HIGH:%r[0-5]]], %a0
+; CHECK-MAIN: sllg %r2, [[HIGH]], 32
+; CHECK-MAIN: ear %r2, %a1
+; CHECK-MAIN: larl %r1, x@INDNTPOFF
+; CHECK-MAIN: ag %r2, 0(%r1)
+; CHECK-MAIN: br %r14
+  ret i32 *@x
+}
diff --git a/test/CodeGen/SystemZ/tls-03.ll b/test/CodeGen/SystemZ/tls-03.ll
new file mode 100644
index 000000000000..c9f7bd632904
--- /dev/null
+++ b/test/CodeGen/SystemZ/tls-03.ll
@@ -0,0 +1,23 @@
+; Test general-dynamic TLS accesses.
+;
+; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=CHECK-MAIN
+; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=CHECK-CP
+
+@x = thread_local global i32 0
+
+; Call __tls_get_offset to retrieve the symbol's TLS offset.
+define i32 *@foo() {
+; CHECK-CP: .LCP{{.*}}:
+; CHECK-CP: .quad x@TLSGD
+;
+; CHECK-MAIN-LABEL: foo:
+; CHECK-MAIN-DAG: larl %r12, _GLOBAL_OFFSET_TABLE_
+; CHECK-MAIN-DAG: lgrl %r2, .LCP{{.*}}
+; CHECK-MAIN: brasl %r14, __tls_get_offset@PLT:tls_gdcall:x
+; CHECK-MAIN: ear [[HIGH:%r[0-5]]], %a0
+; CHECK-MAIN: sllg [[TP:%r[0-5]]], [[HIGH]], 32
+; CHECK-MAIN: ear [[TP]], %a1
+; CHECK-MAIN: agr %r2, [[TP]]
+; CHECK-MAIN: br %r14
+  ret i32 *@x
+}
diff --git a/test/CodeGen/SystemZ/tls-04.ll b/test/CodeGen/SystemZ/tls-04.ll
new file mode 100644
index 000000000000..dcb210a71272
--- /dev/null
+++ b/test/CodeGen/SystemZ/tls-04.ll
@@ -0,0 +1,28 @@
+; Test local-dynamic TLS accesses.
+;
+; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=CHECK-MAIN
+; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=CHECK-CP
+
+@x = thread_local(localdynamic) global i32 0
+
+; Call __tls_get_offset to retrieve the module's TLS base offset.
+; Add the per-symbol offset and the thread pointer.
+define i32 *@foo() {
+; CHECK-CP: .LCP{{.*}}_0:
+; CHECK-CP: .quad x@TLSLDM
+; CHECK-CP: .LCP{{.*}}_1:
+; CHECK-CP: .quad x@DTPOFF
+;
+; CHECK-MAIN-LABEL: foo:
+; CHECK-MAIN-DAG: larl %r12, _GLOBAL_OFFSET_TABLE_
+; CHECK-MAIN-DAG: lgrl %r2, .LCP{{.*}}_0
+; CHECK-MAIN: brasl %r14, __tls_get_offset@PLT:tls_ldcall:x
+; CHECK-MAIN: larl %r1, .LCP{{.*}}_1
+; CHECK-MAIN: ag %r2, 0(%r1)
+; CHECK-MAIN: ear [[HIGH:%r[0-5]]], %a0
+; CHECK-MAIN: sllg [[TP:%r[0-5]]], [[HIGH]], 32
+; CHECK-MAIN: ear [[TP]], %a1
+; CHECK-MAIN: agr %r2, [[TP]]
+; CHECK-MAIN: br %r14
+  ret i32 *@x
+}
diff --git a/test/CodeGen/SystemZ/tls-05.ll b/test/CodeGen/SystemZ/tls-05.ll
new file mode 100644
index 000000000000..502d6d45852c
--- /dev/null
+++ b/test/CodeGen/SystemZ/tls-05.ll
@@ -0,0 +1,15 @@
+; Test general-dynamic TLS access optimizations.
+;
+; If we access the same TLS variable twice, there should only be
+; a single call to __tls_get_offset.
+;
+; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | grep "__tls_get_offset" | count 1
+
+@x = thread_local global i32 0
+
+define i32 @foo() {
+  %val = load i32, i32* @x
+  %inc = add nsw i32 %val, 1
+  store i32 %inc, i32* @x
+  ret i32 %val
+}
diff --git a/test/CodeGen/SystemZ/tls-06.ll b/test/CodeGen/SystemZ/tls-06.ll
new file mode 100644
index 000000000000..8f1796df7291
--- /dev/null
+++ b/test/CodeGen/SystemZ/tls-06.ll
@@ -0,0 +1,17 @@
+; Test general-dynamic TLS access optimizations.
+;
+; If we access two different TLS variables, we need two calls to
+; __tls_get_offset, but should load _GLOBAL_OFFSET_TABLE only once.
+;
+; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | grep "__tls_get_offset" | count 2
+; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | grep "_GLOBAL_OFFSET_TABLE_" | count 1
+
+@x = thread_local global i32 0
+@y = thread_local global i32 0
+
+define i32 @foo() {
+  %valx = load i32, i32* @x
+  %valy = load i32, i32* @y
+  %add = add nsw i32 %valx, %valy
+  ret i32 %add
+}
diff --git a/test/CodeGen/SystemZ/tls-07.ll b/test/CodeGen/SystemZ/tls-07.ll
new file mode 100644
index 000000000000..be66c093bd42
--- /dev/null
+++ b/test/CodeGen/SystemZ/tls-07.ll
@@ -0,0 +1,16 @@
+; Test local-dynamic TLS access optimizations.
+;
+; If we access two different local-dynamic TLS variables, we only
+; need a single call to __tls_get_offset.
+;
+; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | grep "__tls_get_offset" | count 1
+
+@x = thread_local(localdynamic) global i32 0
+@y = thread_local(localdynamic) global i32 0
+
+define i32 @foo() {
+  %valx = load i32, i32* @x
+  %valy = load i32, i32* @y
+  %add = add nsw i32 %valx, %valy
+  ret i32 %add
+}
diff --git a/test/CodeGen/SystemZ/unaligned-01.ll b/test/CodeGen/SystemZ/unaligned-01.ll
index 526a068100ef..94cad0e1743a 100644
--- a/test/CodeGen/SystemZ/unaligned-01.ll
+++ b/test/CodeGen/SystemZ/unaligned-01.ll
@@ -12,9 +12,9 @@ define void @f1(i8 *%ptr) {
 ; CHECK: iilf [[REG:%r[0-5]]], 66051
 ; CHECK: st [[REG]], 0(%r2)
 ; CHECK: br %r14
-  %off1 = getelementptr i8 *%ptr, i64 1
-  %off2 = getelementptr i8 *%ptr, i64 2
-  %off3 = getelementptr i8 *%ptr, i64 3
+  %off1 = getelementptr i8, i8 *%ptr, i64 1
+  %off2 = getelementptr i8, i8 *%ptr, i64 2
+  %off3 = getelementptr i8, i8 *%ptr, i64 3
   store i8 0, i8 *%ptr
   store i8 1, i8 *%off1
   store i8 2, i8 *%off2
@@ -28,7 +28,7 @@ define i16 @f2(i16 *%src, i16 *%dst) {
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: sth %r2, 0(%r3)
 ; CHECK: br %r14
-  %val = load i16 *%src, align 1
+  %val = load i16 , i16 *%src, align 1
   store i16 %val, i16 *%dst, align 1
   ret i16 %val
 }
@@ -40,8 +40,8 @@ define i32 @f3(i32 *%src1, i32 *%src2, i32 *%dst) {
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: st %r2, 0(%r4)
 ; CHECK: br %r14
-  %val1 = load i32 *%src1, align 1
-  %val2 = load i32 *%src2, align 2
+  %val1 = load i32 , i32 *%src1, align 1
+  %val2 = load i32 , i32 *%src2, align 2
   %sub = sub i32 %val1, %val2
   store i32 %sub, i32 *%dst, align 1
   ret i32 %sub
@@ -54,8 +54,8 @@ define i64 @f4(i64 *%src1, i64 *%src2, i64 *%dst) {
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: stg %r2, 0(%r4)
 ; CHECK: br %r14
-  %val1 = load i64 *%src1, align 1
-  %val2 = load i64 *%src2, align 2
+  %val1 = load i64 , i64 *%src1, align 1
+  %val2 = load i64 , i64 *%src2, align 2
   %sub = sub i64 %val1, %val2
   store i64 %sub, i64 *%dst, align 4
   ret i64 %sub
diff --git a/test/CodeGen/SystemZ/vec-abi-align.ll b/test/CodeGen/SystemZ/vec-abi-align.ll
new file mode 100644
index 000000000000..01b97a8583eb
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-abi-align.ll
@@ -0,0 +1,49 @@
+; Verify that we use the vector ABI datalayout if and only if
+; the vector facility is present.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | \
+; RUN:   FileCheck -check-prefix=CHECK-NOVECTOR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=generic | \
+; RUN:   FileCheck -check-prefix=CHECK-NOVECTOR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | \
+; RUN:   FileCheck -check-prefix=CHECK-NOVECTOR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | \
+; RUN:   FileCheck -check-prefix=CHECK-NOVECTOR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | \
+; RUN:   FileCheck -check-prefix=CHECK-NOVECTOR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | \
+; RUN:   FileCheck -check-prefix=CHECK-VECTOR %s
+
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=vector | \
+; RUN:   FileCheck -check-prefix=CHECK-VECTOR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=+vector | \
+; RUN:   FileCheck -check-prefix=CHECK-VECTOR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=-vector,vector | \
+; RUN:   FileCheck -check-prefix=CHECK-VECTOR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=-vector,+vector | \
+; RUN:   FileCheck -check-prefix=CHECK-VECTOR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=-vector | \
+; RUN:   FileCheck -check-prefix=CHECK-NOVECTOR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=vector,-vector | \
+; RUN:   FileCheck -check-prefix=CHECK-NOVECTOR %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=+vector,-vector | \
+; RUN:   FileCheck -check-prefix=CHECK-NOVECTOR %s
+
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -mattr=-vector | \
+; RUN:   FileCheck -check-prefix=CHECK-NOVECTOR %s
+
+%struct.S = type { i8, <2 x i64> }
+
+define void @test(%struct.S* %s) nounwind {
+; CHECK-VECTOR-LABEL: @test
+; CHECK-VECTOR: vl %v0, 8(%r2)
+; CHECK-NOVECTOR-LABEL: @test
+; CHECK-NOVECTOR-DAG: agsi 16(%r2), 1
+; CHECK-NOVECTOR-DAG: agsi 24(%r2), 1
+  %ptr = getelementptr %struct.S, %struct.S* %s, i64 0, i32 1
+  %vec = load <2 x i64>, <2 x i64>* %ptr
+  %add = add <2 x i64> %vec, <i64 1, i64 1>
+  store <2 x i64> %add, <2 x i64>* %ptr
+  ret void
+}
+
diff --git a/test/CodeGen/SystemZ/vec-abs-01.ll b/test/CodeGen/SystemZ/vec-abs-01.ll
new file mode 100644
index 000000000000..aec3b9314f19
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-abs-01.ll
@@ -0,0 +1,146 @@
+; Test v16i8 absolute.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test with slt.
+define <16 x i8> @f1(<16 x i8> %val) {
+; CHECK-LABEL: f1:
+; CHECK: vlpb %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp slt <16 x i8> %val, zeroinitializer
+  %neg = sub <16 x i8> zeroinitializer, %val
+  %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
+  ret <16 x i8> %ret
+}
+
+; Test with sle.
+define <16 x i8> @f2(<16 x i8> %val) {
+; CHECK-LABEL: f2:
+; CHECK: vlpb %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp sle <16 x i8> %val, zeroinitializer
+  %neg = sub <16 x i8> zeroinitializer, %val
+  %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
+  ret <16 x i8> %ret
+}
+
+; Test with sgt.
+define <16 x i8> @f3(<16 x i8> %val) {
+; CHECK-LABEL: f3:
+; CHECK: vlpb %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp sgt <16 x i8> %val, zeroinitializer
+  %neg = sub <16 x i8> zeroinitializer, %val
+  %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
+  ret <16 x i8> %ret
+}
+
+; Test with sge.
+define <16 x i8> @f4(<16 x i8> %val) {
+; CHECK-LABEL: f4:
+; CHECK: vlpb %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp sge <16 x i8> %val, zeroinitializer
+  %neg = sub <16 x i8> zeroinitializer, %val
+  %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
+  ret <16 x i8> %ret
+}
+
+; Test that negative absolute uses VLPB too.  There is no vector equivalent
+; of LOAD NEGATIVE.
+define <16 x i8> @f5(<16 x i8> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vlpb [[REG:%v[0-9]+]], %v24
+; CHECK: vlcb %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp slt <16 x i8> %val, zeroinitializer
+  %neg = sub <16 x i8> zeroinitializer, %val
+  %abs = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
+  %ret = sub <16 x i8> zeroinitializer, %abs
+  ret <16 x i8> %ret
+}
+
+; Try another form of negative absolute (slt version).
+define <16 x i8> @f6(<16 x i8> %val) {
+; CHECK-LABEL: f6:
+; CHECK: vlpb [[REG:%v[0-9]+]], %v24
+; CHECK: vlcb %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp slt <16 x i8> %val, zeroinitializer
+  %neg = sub <16 x i8> zeroinitializer, %val
+  %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
+  ret <16 x i8> %ret
+}
+
+; Test with sle.
+define <16 x i8> @f7(<16 x i8> %val) {
+; CHECK-LABEL: f7:
+; CHECK: vlpb [[REG:%v[0-9]+]], %v24
+; CHECK: vlcb %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp sle <16 x i8> %val, zeroinitializer
+  %neg = sub <16 x i8> zeroinitializer, %val
+  %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg
+  ret <16 x i8> %ret
+}
+
+; Test with sgt.
+define <16 x i8> @f8(<16 x i8> %val) {
+; CHECK-LABEL: f8:
+; CHECK: vlpb [[REG:%v[0-9]+]], %v24
+; CHECK: vlcb %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp sgt <16 x i8> %val, zeroinitializer
+  %neg = sub <16 x i8> zeroinitializer, %val
+  %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
+  ret <16 x i8> %ret
+}
+
+; Test with sge.
+define <16 x i8> @f9(<16 x i8> %val) {
+; CHECK-LABEL: f9:
+; CHECK: vlpb [[REG:%v[0-9]+]], %v24
+; CHECK: vlcb %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp sge <16 x i8> %val, zeroinitializer
+  %neg = sub <16 x i8> zeroinitializer, %val
+  %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val
+  ret <16 x i8> %ret
+}
+
+; Test with an SRA-based boolean vector.
+define <16 x i8> @f10(<16 x i8> %val) {
+; CHECK-LABEL: f10:
+; CHECK: vlpb %v24, %v24
+; CHECK: br %r14
+  %shr = ashr <16 x i8> %val,
+              <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,
+               i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %neg = sub <16 x i8> zeroinitializer, %val
+  %and1 = and <16 x i8> %shr, %neg
+  %not = xor <16 x i8> %shr,
+             <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+              i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %and2 = and <16 x i8> %not, %val
+  %ret = or <16 x i8> %and1, %and2
+  ret <16 x i8> %ret
+}
+
+; ...and again in reverse
+define <16 x i8> @f11(<16 x i8> %val) {
+; CHECK-LABEL: f11:
+; CHECK: vlpb [[REG:%v[0-9]+]], %v24
+; CHECK: vlcb %v24, [[REG]]
+; CHECK: br %r14
+  %shr = ashr <16 x i8> %val,
+              <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,
+               i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %and1 = and <16 x i8> %shr, %val
+  %not = xor <16 x i8> %shr,
+             <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+              i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %neg = sub <16 x i8> zeroinitializer, %val
+  %and2 = and <16 x i8> %not, %neg
+  %ret = or <16 x i8> %and1, %and2
+  ret <16 x i8> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-abs-02.ll b/test/CodeGen/SystemZ/vec-abs-02.ll
new file mode 100644
index 000000000000..c5af619f0ba6
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-abs-02.ll
@@ -0,0 +1,142 @@
+; Test v8i16 absolute.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test with slt.
+define <8 x i16> @f1(<8 x i16> %val) {
+; CHECK-LABEL: f1:
+; CHECK: vlph %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp slt <8 x i16> %val, zeroinitializer
+  %neg = sub <8 x i16> zeroinitializer, %val
+  %ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val
+  ret <8 x i16> %ret
+}
+
+; Test with sle.
+define <8 x i16> @f2(<8 x i16> %val) {
+; CHECK-LABEL: f2:
+; CHECK: vlph %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp sle <8 x i16> %val, zeroinitializer
+  %neg = sub <8 x i16> zeroinitializer, %val
+  %ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val
+  ret <8 x i16> %ret
+}
+
+; Test with sgt.
+define <8 x i16> @f3(<8 x i16> %val) {
+; CHECK-LABEL: f3:
+; CHECK: vlph %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp sgt <8 x i16> %val, zeroinitializer
+  %neg = sub <8 x i16> zeroinitializer, %val
+  %ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg
+  ret <8 x i16> %ret
+}
+
+; Test with sge.
+define <8 x i16> @f4(<8 x i16> %val) {
+; CHECK-LABEL: f4:
+; CHECK: vlph %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp sge <8 x i16> %val, zeroinitializer
+  %neg = sub <8 x i16> zeroinitializer, %val
+  %ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg
+  ret <8 x i16> %ret
+}
+
+; Test that negative absolute uses VLPH too.  There is no vector equivalent
+; of LOAD NEGATIVE.
+define <8 x i16> @f5(<8 x i16> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vlph [[REG:%v[0-9]+]], %v24
+; CHECK: vlch %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp slt <8 x i16> %val, zeroinitializer
+  %neg = sub <8 x i16> zeroinitializer, %val
+  %abs = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val
+  %ret = sub <8 x i16> zeroinitializer, %abs
+  ret <8 x i16> %ret
+}
+
+; Try another form of negative absolute (slt version).
+define <8 x i16> @f6(<8 x i16> %val) {
+; CHECK-LABEL: f6:
+; CHECK: vlph [[REG:%v[0-9]+]], %v24
+; CHECK: vlch %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp slt <8 x i16> %val, zeroinitializer
+  %neg = sub <8 x i16> zeroinitializer, %val
+  %ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg
+  ret <8 x i16> %ret
+}
+
+; Test with sle.
+define <8 x i16> @f7(<8 x i16> %val) {
+; CHECK-LABEL: f7:
+; CHECK: vlph [[REG:%v[0-9]+]], %v24
+; CHECK: vlch %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp sle <8 x i16> %val, zeroinitializer
+  %neg = sub <8 x i16> zeroinitializer, %val
+  %ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg
+  ret <8 x i16> %ret
+}
+
+; Test with sgt.
+define <8 x i16> @f8(<8 x i16> %val) {
+; CHECK-LABEL: f8:
+; CHECK: vlph [[REG:%v[0-9]+]], %v24
+; CHECK: vlch %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp sgt <8 x i16> %val, zeroinitializer
+  %neg = sub <8 x i16> zeroinitializer, %val
+  %ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val
+  ret <8 x i16> %ret
+}
+
+; Test with sge.
+define <8 x i16> @f9(<8 x i16> %val) {
+; CHECK-LABEL: f9:
+; CHECK: vlph [[REG:%v[0-9]+]], %v24
+; CHECK: vlch %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp sge <8 x i16> %val, zeroinitializer
+  %neg = sub <8 x i16> zeroinitializer, %val
+  %ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val
+  ret <8 x i16> %ret
+}
+
+; Test with an SRA-based boolean vector.
+define <8 x i16> @f10(<8 x i16> %val) {
+; CHECK-LABEL: f10:
+; CHECK: vlph %v24, %v24
+; CHECK: br %r14
+  %shr = ashr <8 x i16> %val,
+              <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+  %neg = sub <8 x i16> zeroinitializer, %val
+  %and1 = and <8 x i16> %shr, %neg
+  %not = xor <8 x i16> %shr,
+             <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+  %and2 = and <8 x i16> %not, %val
+  %ret = or <8 x i16> %and1, %and2
+  ret <8 x i16> %ret
+}
+
+; ...and again in reverse
+define <8 x i16> @f11(<8 x i16> %val) {
+; CHECK-LABEL: f11:
+; CHECK: vlph [[REG:%v[0-9]+]], %v24
+; CHECK: vlch %v24, [[REG]]
+; CHECK: br %r14
+  %shr = ashr <8 x i16> %val,
+              <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+  %and1 = and <8 x i16> %shr, %val
+  %not = xor <8 x i16> %shr,
+             <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+  %neg = sub <8 x i16> zeroinitializer, %val
+  %and2 = and <8 x i16> %not, %neg
+  %ret = or <8 x i16> %and1, %and2
+  ret <8 x i16> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-abs-03.ll b/test/CodeGen/SystemZ/vec-abs-03.ll
new file mode 100644
index 000000000000..cb17a8895e1a
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-abs-03.ll
@@ -0,0 +1,138 @@
+; Test v4i32 absolute.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test with slt.
+define <4 x i32> @f1(<4 x i32> %val) {
+; CHECK-LABEL: f1:
+; CHECK: vlpf %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp slt <4 x i32> %val, zeroinitializer
+  %neg = sub <4 x i32> zeroinitializer, %val
+  %ret = select <4 x i1> %cmp, <4 x i32> %neg, <4 x i32> %val
+  ret <4 x i32> %ret
+}
+
+; Test with sle.
+define <4 x i32> @f2(<4 x i32> %val) {
+; CHECK-LABEL: f2:
+; CHECK: vlpf %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp sle <4 x i32> %val, zeroinitializer
+  %neg = sub <4 x i32> zeroinitializer, %val
+  %ret = select <4 x i1> %cmp, <4 x i32> %neg, <4 x i32> %val
+  ret <4 x i32> %ret
+}
+
+; Test with sgt.
+define <4 x i32> @f3(<4 x i32> %val) {
+; CHECK-LABEL: f3:
+; CHECK: vlpf %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp sgt <4 x i32> %val, zeroinitializer
+  %neg = sub <4 x i32> zeroinitializer, %val
+  %ret = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %neg
+  ret <4 x i32> %ret
+}
+
+; Test with sge.
+define <4 x i32> @f4(<4 x i32> %val) {
+; CHECK-LABEL: f4:
+; CHECK: vlpf %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp sge <4 x i32> %val, zeroinitializer
+  %neg = sub <4 x i32> zeroinitializer, %val
+  %ret = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %neg
+  ret <4 x i32> %ret
+}
+
+; Test that negative absolute uses VLPF too.  There is no vector equivalent
+; of LOAD NEGATIVE.
+define <4 x i32> @f5(<4 x i32> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vlpf [[REG:%v[0-9]+]], %v24
+; CHECK: vlcf %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp slt <4 x i32> %val, zeroinitializer
+  %neg = sub <4 x i32> zeroinitializer, %val
+  %abs = select <4 x i1> %cmp, <4 x i32> %neg, <4 x i32> %val
+  %ret = sub <4 x i32> zeroinitializer, %abs
+  ret <4 x i32> %ret
+}
+
+; Try another form of negative absolute (slt version).
+define <4 x i32> @f6(<4 x i32> %val) {
+; CHECK-LABEL: f6:
+; CHECK: vlpf [[REG:%v[0-9]+]], %v24
+; CHECK: vlcf %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp slt <4 x i32> %val, zeroinitializer
+  %neg = sub <4 x i32> zeroinitializer, %val
+  %ret = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %neg
+  ret <4 x i32> %ret
+}
+
+; Test with sle.
+define <4 x i32> @f7(<4 x i32> %val) {
+; CHECK-LABEL: f7:
+; CHECK: vlpf [[REG:%v[0-9]+]], %v24
+; CHECK: vlcf %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp sle <4 x i32> %val, zeroinitializer
+  %neg = sub <4 x i32> zeroinitializer, %val
+  %ret = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %neg
+  ret <4 x i32> %ret
+}
+
+; Test with sgt.
+define <4 x i32> @f8(<4 x i32> %val) {
+; CHECK-LABEL: f8:
+; CHECK: vlpf [[REG:%v[0-9]+]], %v24
+; CHECK: vlcf %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp sgt <4 x i32> %val, zeroinitializer
+  %neg = sub <4 x i32> zeroinitializer, %val
+  %ret = select <4 x i1> %cmp, <4 x i32> %neg, <4 x i32> %val
+  ret <4 x i32> %ret
+}
+
+; Test with sge.
+define <4 x i32> @f9(<4 x i32> %val) {
+; CHECK-LABEL: f9:
+; CHECK: vlpf [[REG:%v[0-9]+]], %v24
+; CHECK: vlcf %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp sge <4 x i32> %val, zeroinitializer
+  %neg = sub <4 x i32> zeroinitializer, %val
+  %ret = select <4 x i1> %cmp, <4 x i32> %neg, <4 x i32> %val
+  ret <4 x i32> %ret
+}
+
+; Test with an SRA-based boolean vector.
+define <4 x i32> @f10(<4 x i32> %val) {
+; CHECK-LABEL: f10:
+; CHECK: vlpf %v24, %v24
+; CHECK: br %r14
+  %shr = ashr <4 x i32> %val, <i32 31, i32 31, i32 31, i32 31>
+  %neg = sub <4 x i32> zeroinitializer, %val
+  %and1 = and <4 x i32> %shr, %neg
+  %not = xor <4 x i32> %shr, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %and2 = and <4 x i32> %not, %val
+  %ret = or <4 x i32> %and1, %and2
+  ret <4 x i32> %ret
+}
+
+; ...and again in reverse
+define <4 x i32> @f11(<4 x i32> %val) {
+; CHECK-LABEL: f11:
+; CHECK: vlpf [[REG:%v[0-9]+]], %v24
+; CHECK: vlcf %v24, [[REG]]
+; CHECK: br %r14
+  %shr = ashr <4 x i32> %val, <i32 31, i32 31, i32 31, i32 31>
+  %and1 = and <4 x i32> %shr, %val
+  %not = xor <4 x i32> %shr, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %neg = sub <4 x i32> zeroinitializer, %val
+  %and2 = and <4 x i32> %not, %neg
+  %ret = or <4 x i32> %and1, %and2
+  ret <4 x i32> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-abs-04.ll b/test/CodeGen/SystemZ/vec-abs-04.ll
new file mode 100644
index 000000000000..31c489b00b35
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-abs-04.ll
@@ -0,0 +1,138 @@
+; Test v2i64 absolute.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test with slt.
+define <2 x i64> @f1(<2 x i64> %val) {
+; CHECK-LABEL: f1:
+; CHECK: vlpg %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp slt <2 x i64> %val, zeroinitializer
+  %neg = sub <2 x i64> zeroinitializer, %val
+  %ret = select <2 x i1> %cmp, <2 x i64> %neg, <2 x i64> %val
+  ret <2 x i64> %ret
+}
+
+; Test with sle.
+define <2 x i64> @f2(<2 x i64> %val) {
+; CHECK-LABEL: f2:
+; CHECK: vlpg %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp sle <2 x i64> %val, zeroinitializer
+  %neg = sub <2 x i64> zeroinitializer, %val
+  %ret = select <2 x i1> %cmp, <2 x i64> %neg, <2 x i64> %val
+  ret <2 x i64> %ret
+}
+
+; Test with sgt.
+define <2 x i64> @f3(<2 x i64> %val) {
+; CHECK-LABEL: f3:
+; CHECK: vlpg %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp sgt <2 x i64> %val, zeroinitializer
+  %neg = sub <2 x i64> zeroinitializer, %val
+  %ret = select <2 x i1> %cmp, <2 x i64> %val, <2 x i64> %neg
+  ret <2 x i64> %ret
+}
+
+; Test with sge.
+define <2 x i64> @f4(<2 x i64> %val) {
+; CHECK-LABEL: f4:
+; CHECK: vlpg %v24, %v24
+; CHECK: br %r14
+  %cmp = icmp sge <2 x i64> %val, zeroinitializer
+  %neg = sub <2 x i64> zeroinitializer, %val
+  %ret = select <2 x i1> %cmp, <2 x i64> %val, <2 x i64> %neg
+  ret <2 x i64> %ret
+}
+
+; Test that negative absolute uses VLPG too.  There is no vector equivalent
+; of LOAD NEGATIVE.
+define <2 x i64> @f5(<2 x i64> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vlpg [[REG:%v[0-9]+]], %v24
+; CHECK: vlcg %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp slt <2 x i64> %val, zeroinitializer
+  %neg = sub <2 x i64> zeroinitializer, %val
+  %abs = select <2 x i1> %cmp, <2 x i64> %neg, <2 x i64> %val
+  %ret = sub <2 x i64> zeroinitializer, %abs
+  ret <2 x i64> %ret
+}
+
+; Try another form of negative absolute (slt version).
+define <2 x i64> @f6(<2 x i64> %val) {
+; CHECK-LABEL: f6:
+; CHECK: vlpg [[REG:%v[0-9]+]], %v24
+; CHECK: vlcg %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp slt <2 x i64> %val, zeroinitializer
+  %neg = sub <2 x i64> zeroinitializer, %val
+  %ret = select <2 x i1> %cmp, <2 x i64> %val, <2 x i64> %neg
+  ret <2 x i64> %ret
+}
+
+; Test with sle.
+define <2 x i64> @f7(<2 x i64> %val) {
+; CHECK-LABEL: f7:
+; CHECK: vlpg [[REG:%v[0-9]+]], %v24
+; CHECK: vlcg %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp sle <2 x i64> %val, zeroinitializer
+  %neg = sub <2 x i64> zeroinitializer, %val
+  %ret = select <2 x i1> %cmp, <2 x i64> %val, <2 x i64> %neg
+  ret <2 x i64> %ret
+}
+
+; Test with sgt.
+define <2 x i64> @f8(<2 x i64> %val) {
+; CHECK-LABEL: f8:
+; CHECK: vlpg [[REG:%v[0-9]+]], %v24
+; CHECK: vlcg %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp sgt <2 x i64> %val, zeroinitializer
+  %neg = sub <2 x i64> zeroinitializer, %val
+  %ret = select <2 x i1> %cmp, <2 x i64> %neg, <2 x i64> %val
+  ret <2 x i64> %ret
+}
+
+; Test with sge.
+define <2 x i64> @f9(<2 x i64> %val) {
+; CHECK-LABEL: f9:
+; CHECK: vlpg [[REG:%v[0-9]+]], %v24
+; CHECK: vlcg %v24, [[REG]]
+; CHECK: br %r14
+  %cmp = icmp sge <2 x i64> %val, zeroinitializer
+  %neg = sub <2 x i64> zeroinitializer, %val
+  %ret = select <2 x i1> %cmp, <2 x i64> %neg, <2 x i64> %val
+  ret <2 x i64> %ret
+}
+
+; Test with an SRA-based boolean vector.
+define <2 x i64> @f10(<2 x i64> %val) {
+; CHECK-LABEL: f10:
+; CHECK: vlpg %v24, %v24
+; CHECK: br %r14
+  %shr = ashr <2 x i64> %val, <i64 63, i64 63>
+  %neg = sub <2 x i64> zeroinitializer, %val
+  %and1 = and <2 x i64> %shr, %neg
+  %not = xor <2 x i64> %shr, <i64 -1, i64 -1>
+  %and2 = and <2 x i64> %not, %val
+  %ret = or <2 x i64> %and1, %and2
+  ret <2 x i64> %ret
+}
+
+; ...and again in reverse
+define <2 x i64> @f11(<2 x i64> %val) {
+; CHECK-LABEL: f11:
+; CHECK: vlpg [[REG:%v[0-9]+]], %v24
+; CHECK: vlcg %v24, [[REG]]
+; CHECK: br %r14
+  %shr = ashr <2 x i64> %val, <i64 63, i64 63>
+  %and1 = and <2 x i64> %shr, %val
+  %not = xor <2 x i64> %shr, <i64 -1, i64 -1>
+  %neg = sub <2 x i64> zeroinitializer, %val
+  %and2 = and <2 x i64> %not, %neg
+  %ret = or <2 x i64> %and1, %and2
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-abs-05.ll b/test/CodeGen/SystemZ/vec-abs-05.ll
new file mode 100644
index 000000000000..63210f87b94e
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-abs-05.ll
@@ -0,0 +1,46 @@
+; Test f64 and v2f64 absolute.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+declare double @llvm.fabs.f64(double)
+declare <2 x double> @llvm.fabs.v2f64(<2 x double>)
+
+; Test a plain absolute.
+define <2 x double> @f1(<2 x double> %val) {
+; CHECK-LABEL: f1:
+; CHECK: vflpdb %v24, %v24
+; CHECK: br %r14
+  %ret = call <2 x double> @llvm.fabs.v2f64(<2 x double> %val)
+  ret <2 x double> %ret
+}
+
+; Test a negative absolute.
+define <2 x double> @f2(<2 x double> %val) {
+; CHECK-LABEL: f2:
+; CHECK: vflndb %v24, %v24
+; CHECK: br %r14
+  %abs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %val)
+  %ret = fsub <2 x double> <double -0.0, double -0.0>, %abs
+  ret <2 x double> %ret
+}
+
+; Test an f64 absolute that uses vector registers.
+define double @f3(<2 x double> %val) {
+; CHECK-LABEL: f3:
+; CHECK: wflpdb %f0, %v24
+; CHECK: br %r14
+  %scalar = extractelement <2 x double> %val, i32 0
+  %ret = call double @llvm.fabs.f64(double %scalar)
+  ret double %ret
+}
+
+; Test an f64 negative absolute that uses vector registers.
+define double @f4(<2 x double> %val) {
+; CHECK-LABEL: f4:
+; CHECK: wflndb %f0, %v24
+; CHECK: br %r14
+  %scalar = extractelement <2 x double> %val, i32 0
+  %abs = call double @llvm.fabs.f64(double %scalar)
+  %ret = fsub double -0.0, %abs
+  ret double %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-add-01.ll b/test/CodeGen/SystemZ/vec-add-01.ll
new file mode 100644
index 000000000000..317034377671
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-add-01.ll
@@ -0,0 +1,60 @@
+; Test vector addition.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 addition.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vab %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = add <16 x i8> %val1, %val2
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 addition.
+define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vah %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = add <8 x i16> %val1, %val2
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 addition.
+define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vaf %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = add <4 x i32> %val1, %val2
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 addition.
+define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vag %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = add <2 x i64> %val1, %val2
+  ret <2 x i64> %ret
+}
+
+; Test a v2f64 addition.
+define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1,
+                        <2 x double> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vfadb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = fadd <2 x double> %val1, %val2
+  ret <2 x double> %ret
+}
+
+; Test an f64 addition that uses vector registers.
+define double @f6(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: wfadb %f0, %v24, %v26
+; CHECK: br %r14
+  %scalar1 = extractelement <2 x double> %val1, i32 0
+  %scalar2 = extractelement <2 x double> %val2, i32 0
+  %ret = fadd double %scalar1, %scalar2
+  ret double %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-and-01.ll b/test/CodeGen/SystemZ/vec-and-01.ll
new file mode 100644
index 000000000000..d467de69cea2
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-and-01.ll
@@ -0,0 +1,39 @@
+; Test vector AND.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 AND.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vn %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = and <16 x i8> %val1, %val2
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 AND.
+define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vn %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = and <8 x i16> %val1, %val2
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 AND.
+define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vn %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = and <4 x i32> %val1, %val2
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 AND.
+define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vn %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = and <2 x i64> %val1, %val2
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-and-02.ll b/test/CodeGen/SystemZ/vec-and-02.ll
new file mode 100644
index 000000000000..30bc92416892
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-and-02.ll
@@ -0,0 +1,91 @@
+; Test vector AND-NOT.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 AND-NOT.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vnc %v24, %v26, %v28
+; CHECK: br %r14
+  %not = xor <16 x i8> %val2, <i8 -1, i8 -1, i8 -1, i8 -1,
+                               i8 -1, i8 -1, i8 -1, i8 -1,
+                               i8 -1, i8 -1, i8 -1, i8 -1,
+                               i8 -1, i8 -1, i8 -1, i8 -1>
+  %ret = and <16 x i8> %val1, %not
+  ret <16 x i8> %ret
+}
+
+; ...and again with the reverse.
+define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vnc %v24, %v28, %v26
+; CHECK: br %r14
+  %not = xor <16 x i8> %val1, <i8 -1, i8 -1, i8 -1, i8 -1,
+                               i8 -1, i8 -1, i8 -1, i8 -1,
+                               i8 -1, i8 -1, i8 -1, i8 -1,
+                               i8 -1, i8 -1, i8 -1, i8 -1>
+  %ret = and <16 x i8> %not, %val2
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 AND-NOT.
+define <8 x i16> @f3(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vnc %v24, %v26, %v28
+; CHECK: br %r14
+  %not = xor <8 x i16> %val2, <i16 -1, i16 -1, i16 -1, i16 -1,
+                               i16 -1, i16 -1, i16 -1, i16 -1>
+  %ret = and <8 x i16> %val1, %not
+  ret <8 x i16> %ret
+}
+
+; ...and again with the reverse.
+define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vnc %v24, %v28, %v26
+; CHECK: br %r14
+  %not = xor <8 x i16> %val1, <i16 -1, i16 -1, i16 -1, i16 -1,
+                               i16 -1, i16 -1, i16 -1, i16 -1>
+  %ret = and <8 x i16> %not, %val2
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 AND-NOT.
+define <4 x i32> @f5(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vnc %v24, %v26, %v28
+; CHECK: br %r14
+  %not = xor <4 x i32> %val2, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %ret = and <4 x i32> %val1, %not
+  ret <4 x i32> %ret
+}
+
+; ...and again with the reverse.
+define <4 x i32> @f6(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vnc %v24, %v28, %v26
+; CHECK: br %r14
+  %not = xor <4 x i32> %val1, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %ret = and <4 x i32> %not, %val2
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 AND-NOT.
+define <2 x i64> @f7(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vnc %v24, %v26, %v28
+; CHECK: br %r14
+  %not = xor <2 x i64> %val2, <i64 -1, i64 -1>
+  %ret = and <2 x i64> %val1, %not
+  ret <2 x i64> %ret
+}
+
+; ...and again with the reverse.
+define <2 x i64> @f8(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vnc %v24, %v28, %v26
+; CHECK: br %r14
+  %not = xor <2 x i64> %val1, <i64 -1, i64 -1>
+  %ret = and <2 x i64> %not, %val2
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-and-03.ll b/test/CodeGen/SystemZ/vec-and-03.ll
new file mode 100644
index 000000000000..c73d570fb7b0
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-and-03.ll
@@ -0,0 +1,113 @@
+; Test vector zero extensions, which need to be implemented as ANDs.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i1->v16i8 extension.
+define <16 x i8> @f1(<16 x i8> %val) {
+; CHECK-LABEL: f1:
+; CHECK: vrepib [[REG:%v[0-9]+]], 1
+; CHECK: vn %v24, %v24, [[REG]]
+; CHECK: br %r14
+  %trunc = trunc <16 x i8> %val to <16 x i1>
+  %ret = zext <16 x i1> %trunc to <16 x i8>
+  ret <16 x i8> %ret
+}
+
+; Test a v8i1->v8i16 extension.
+define <8 x i16> @f2(<8 x i16> %val) {
+; CHECK-LABEL: f2:
+; CHECK: vrepih [[REG:%v[0-9]+]], 1
+; CHECK: vn %v24, %v24, [[REG]]
+; CHECK: br %r14
+  %trunc = trunc <8 x i16> %val to <8 x i1>
+  %ret = zext <8 x i1> %trunc to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test a v8i8->v8i16 extension.
+define <8 x i16> @f3(<8 x i16> %val) {
+; CHECK-LABEL: f3:
+; CHECK: vgbm [[REG:%v[0-9]+]], 21845
+; CHECK: vn %v24, %v24, [[REG]]
+; CHECK: br %r14
+  %trunc = trunc <8 x i16> %val to <8 x i8>
+  %ret = zext <8 x i8> %trunc to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test a v4i1->v4i32 extension.
+define <4 x i32> @f4(<4 x i32> %val) {
+; CHECK-LABEL: f4:
+; CHECK: vrepif [[REG:%v[0-9]+]], 1
+; CHECK: vn %v24, %v24, [[REG]]
+; CHECK: br %r14
+  %trunc = trunc <4 x i32> %val to <4 x i1>
+  %ret = zext <4 x i1> %trunc to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test a v4i8->v4i32 extension.
+define <4 x i32> @f5(<4 x i32> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vgbm [[REG:%v[0-9]+]], 4369
+; CHECK: vn %v24, %v24, [[REG]]
+; CHECK: br %r14
+  %trunc = trunc <4 x i32> %val to <4 x i8>
+  %ret = zext <4 x i8> %trunc to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test a v4i16->v4i32 extension.
+define <4 x i32> @f6(<4 x i32> %val) {
+; CHECK-LABEL: f6:
+; CHECK: vgbm [[REG:%v[0-9]+]], 13107
+; CHECK: vn %v24, %v24, [[REG]]
+; CHECK: br %r14
+  %trunc = trunc <4 x i32> %val to <4 x i16>
+  %ret = zext <4 x i16> %trunc to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test a v2i1->v2i64 extension.
+define <2 x i64> @f7(<2 x i64> %val) {
+; CHECK-LABEL: f7:
+; CHECK: vrepig [[REG:%v[0-9]+]], 1
+; CHECK: vn %v24, %v24, [[REG]]
+; CHECK: br %r14
+  %trunc = trunc <2 x i64> %val to <2 x i1>
+  %ret = zext <2 x i1> %trunc to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test a v2i8->v2i64 extension.
+define <2 x i64> @f8(<2 x i64> %val) {
+; CHECK-LABEL: f8:
+; CHECK: vgbm [[REG:%v[0-9]+]], 257
+; CHECK: vn %v24, %v24, [[REG]]
+; CHECK: br %r14
+  %trunc = trunc <2 x i64> %val to <2 x i8>
+  %ret = zext <2 x i8> %trunc to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test a v2i16->v2i64 extension.
+define <2 x i64> @f9(<2 x i64> %val) {
+; CHECK-LABEL: f9:
+; CHECK: vgbm [[REG:%v[0-9]+]], 771
+; CHECK: vn %v24, %v24, [[REG]]
+; CHECK: br %r14
+  %trunc = trunc <2 x i64> %val to <2 x i16>
+  %ret = zext <2 x i16> %trunc to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test a v2i32->v2i64 extension.
+define <2 x i64> @f10(<2 x i64> %val) {
+; CHECK-LABEL: f10:
+; CHECK: vgbm [[REG:%v[0-9]+]], 3855
+; CHECK: vn %v24, %v24, [[REG]]
+; CHECK: br %r14
+  %trunc = trunc <2 x i64> %val to <2 x i32>
+  %ret = zext <2 x i32> %trunc to <2 x i64>
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-args-01.ll b/test/CodeGen/SystemZ/vec-args-01.ll
new file mode 100644
index 000000000000..e07ab7447b2a
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-args-01.ll
@@ -0,0 +1,48 @@
+; Test the handling of named vector arguments.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-STACK
+
+; This routine has 6 integer arguments, which fill up r2-r5 and
+; the stack slot at offset 160, and 10 vector arguments, which
+; fill up v24-v31 and the two double-wide stack slots at 168
+; and 184.
+declare void @bar(i64, i64, i64, i64, i64, i64,
+                  <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>,
+                  <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>,
+                  <4 x i32>, <4 x i32>)
+
+define void @foo() {
+; CHECK-VEC-LABEL: foo:
+; CHECK-VEC-DAG: vrepif %v24, 1
+; CHECK-VEC-DAG: vrepif %v26, 2
+; CHECK-VEC-DAG: vrepif %v28, 3
+; CHECK-VEC-DAG: vrepif %v30, 4
+; CHECK-VEC-DAG: vrepif %v25, 5
+; CHECK-VEC-DAG: vrepif %v27, 6
+; CHECK-VEC-DAG: vrepif %v29, 7
+; CHECK-VEC-DAG: vrepif %v31, 8
+; CHECK-VEC: brasl %r14, bar@PLT
+;
+; CHECK-STACK-LABEL: foo:
+; CHECK-STACK: aghi %r15, -200
+; CHECK-STACK-DAG: mvghi 160(%r15), 6
+; CHECK-STACK-DAG: vrepif [[REG1:%v[0-9]+]], 9
+; CHECK-STACK-DAG: vst [[REG1]], 168(%r15)
+; CHECK-STACK-DAG: vrepif [[REG2:%v[0-9]+]], 10
+; CHECK-STACK-DAG: vst [[REG2]], 184(%r15)
+; CHECK-STACK: brasl %r14, bar@PLT
+
+  call void @bar (i64 1, i64 2, i64 3, i64 4, i64 5, i64 6,
+                  <4 x i32> <i32 1, i32 1, i32 1, i32 1>,
+                  <4 x i32> <i32 2, i32 2, i32 2, i32 2>,
+                  <4 x i32> <i32 3, i32 3, i32 3, i32 3>,
+                  <4 x i32> <i32 4, i32 4, i32 4, i32 4>,
+                  <4 x i32> <i32 5, i32 5, i32 5, i32 5>,
+                  <4 x i32> <i32 6, i32 6, i32 6, i32 6>,
+                  <4 x i32> <i32 7, i32 7, i32 7, i32 7>,
+                  <4 x i32> <i32 8, i32 8, i32 8, i32 8>,
+                  <4 x i32> <i32 9, i32 9, i32 9, i32 9>,
+                  <4 x i32> <i32 10, i32 10, i32 10, i32 10>)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/vec-args-02.ll b/test/CodeGen/SystemZ/vec-args-02.ll
new file mode 100644
index 000000000000..b6081598326a
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-args-02.ll
@@ -0,0 +1,31 @@
+; Test the handling of unnamed vector arguments.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-STACK
+
+; This routine is called with two named vector argument (passed
+; in %v24 and %v26) and two unnamed vector arguments (passed
+; in the double-wide stack slots at 160 and 176).
+declare void @bar(<4 x i32>, <4 x i32>, ...)
+
+define void @foo() {
+; CHECK-VEC-LABEL: foo:
+; CHECK-VEC-DAG: vrepif %v24, 1
+; CHECK-VEC-DAG: vrepif %v26, 2
+; CHECK-VEC: brasl %r14, bar@PLT
+;
+; CHECK-STACK-LABEL: foo:
+; CHECK-STACK: aghi %r15, -192
+; CHECK-STACK-DAG: vrepif [[REG1:%v[0-9]+]], 3
+; CHECK-STACK-DAG: vst [[REG1]], 160(%r15)
+; CHECK-STACK-DAG: vrepif [[REG2:%v[0-9]+]], 4
+; CHECK-STACK-DAG: vst [[REG2]], 176(%r15)
+; CHECK-STACK: brasl %r14, bar@PLT
+
+  call void (<4 x i32>, <4 x i32>, ...) @bar
+              (<4 x i32> <i32 1, i32 1, i32 1, i32 1>,
+               <4 x i32> <i32 2, i32 2, i32 2, i32 2>,
+               <4 x i32> <i32 3, i32 3, i32 3, i32 3>,
+               <4 x i32> <i32 4, i32 4, i32 4, i32 4>)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/vec-args-03.ll b/test/CodeGen/SystemZ/vec-args-03.ll
new file mode 100644
index 000000000000..c47d8461021a
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-args-03.ll
@@ -0,0 +1,30 @@
+; Test the handling of incoming vector arguments.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; This routine has 10 vector arguments, which fill up %v24-%v31 and
+; the two double-wide stack slots at 160 and 176.
+define <4 x i32> @foo(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4,
+                      <4 x i32> %v5, <4 x i32> %v6, <4 x i32> %v7, <4 x i32> %v8,
+                      <4 x i32> %v9, <4 x i32> %v10) {
+; CHECK-LABEL: foo:
+; CHECK: vl [[REG1:%v[0-9]+]], 176(%r15)
+; CHECK: vsf %v24, %v26, [[REG1]]
+; CHECK: br %r14
+  %y = sub <4 x i32> %v2, %v10
+  ret <4 x i32> %y
+}
+
+; This routine has 10 vector arguments, which fill up %v24-%v31 and
+; the two single-wide stack slots at 160 and 168.
+define <4 x i8> @bar(<4 x i8> %v1, <4 x i8> %v2, <4 x i8> %v3, <4 x i8> %v4,
+                     <4 x i8> %v5, <4 x i8> %v6, <4 x i8> %v7, <4 x i8> %v8,
+                     <4 x i8> %v9, <4 x i8> %v10) {
+; CHECK-LABEL: bar:
+; CHECK: vlrepg [[REG1:%v[0-9]+]], 168(%r15)
+; CHECK: vsb %v24, %v26, [[REG1]]
+; CHECK: br %r14
+  %y = sub <4 x i8> %v2, %v10
+  ret <4 x i8> %y
+}
+
diff --git a/test/CodeGen/SystemZ/vec-args-04.ll b/test/CodeGen/SystemZ/vec-args-04.ll
new file mode 100644
index 000000000000..3a25404934e2
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-args-04.ll
@@ -0,0 +1,50 @@
+; Test the handling of named short vector arguments.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-STACK
+
+; This routine has 12 vector arguments, which fill up %v24-%v31
+; and the four single-wide stack slots starting at 160.
+declare void @bar(<1 x i8>, <2 x i8>, <4 x i8>, <8 x i8>,
+                  <1 x i8>, <2 x i8>, <4 x i8>, <8 x i8>,
+                  <1 x i8>, <2 x i8>, <4 x i8>, <8 x i8>)
+
+define void @foo() {
+; CHECK-VEC-LABEL: foo:
+; CHECK-VEC-DAG: vrepib %v24, 1
+; CHECK-VEC-DAG: vrepib %v26, 2
+; CHECK-VEC-DAG: vrepib %v28, 3
+; CHECK-VEC-DAG: vrepib %v30, 4
+; CHECK-VEC-DAG: vrepib %v25, 5
+; CHECK-VEC-DAG: vrepib %v27, 6
+; CHECK-VEC-DAG: vrepib %v29, 7
+; CHECK-VEC-DAG: vrepib %v31, 8
+; CHECK-VEC: brasl %r14, bar@PLT
+;
+; CHECK-STACK-LABEL: foo:
+; CHECK-STACK: aghi %r15, -192
+; CHECK-STACK-DAG: llihh [[REG1:%r[0-9]+]], 2304
+; CHECK-STACK-DAG: stg [[REG1]], 160(%r15)
+; CHECK-STACK-DAG: llihh [[REG2:%r[0-9]+]], 2570
+; CHECK-STACK-DAG: stg [[REG2]], 168(%r15)
+; CHECK-STACK-DAG: llihf [[REG3:%r[0-9]+]], 185273099
+; CHECK-STACK-DAG: stg [[REG3]], 176(%r15)
+; CHECK-STACK-DAG: llihf [[REG4:%r[0-9]+]], 202116108
+; CHECK-STACK-DAG: oilf [[REG4]], 202116108
+; CHECK-STACK-DAG: stg [[REG4]], 176(%r15)
+; CHECK-STACK: brasl %r14, bar@PLT
+
+  call void @bar (<1 x i8> <i8 1>,
+                  <2 x i8> <i8 2, i8 2>,
+                  <4 x i8> <i8 3, i8 3, i8 3, i8 3>,
+                  <8 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>,
+                  <1 x i8> <i8 5>,
+                  <2 x i8> <i8 6, i8 6>,
+                  <4 x i8> <i8 7, i8 7, i8 7, i8 7>,
+                  <8 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>,
+                  <1 x i8> <i8 9>,
+                  <2 x i8> <i8 10, i8 10>,
+                  <4 x i8> <i8 11, i8 11, i8 11, i8 11>,
+                  <8 x i8> <i8 12, i8 12, i8 12, i8 12, i8 12, i8 12, i8 12, i8 12>)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/vec-args-05.ll b/test/CodeGen/SystemZ/vec-args-05.ll
new file mode 100644
index 000000000000..cd1448b8611e
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-args-05.ll
@@ -0,0 +1,32 @@
+; Test the handling of unnamed short vector arguments.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-STACK
+
+; This routine is called with two named vector argument (passed
+; in %v24 and %v26) and two unnamed vector arguments (passed
+; in the single-wide stack slots at 160 and 168).
+declare void @bar(<4 x i8>, <4 x i8>, ...)
+
+define void @foo() {
+; CHECK-VEC-LABEL: foo:
+; CHECK-VEC-DAG: vrepib %v24, 1
+; CHECK-VEC-DAG: vrepib %v26, 2
+; CHECK-VEC: brasl %r14, bar@PLT
+;
+; CHECK-STACK-LABEL: foo:
+; CHECK-STACK: aghi %r15, -176
+; CHECK-STACK-DAG: llihf [[REG1:%r[0-9]+]], 50529027
+; CHECK-STACK-DAG: stg [[REG1]], 160(%r15)
+; CHECK-STACK-DAG: llihf [[REG2:%r[0-9]+]], 67372036
+; CHECK-STACK-DAG: stg [[REG2]], 168(%r15)
+; CHECK-STACK: brasl %r14, bar@PLT
+
+  call void (<4 x i8>, <4 x i8>, ...) @bar
+              (<4 x i8> <i8 1, i8 1, i8 1, i8 1>,
+               <4 x i8> <i8 2, i8 2, i8 2, i8 2>,
+               <4 x i8> <i8 3, i8 3, i8 3, i8 3>,
+               <4 x i8> <i8 4, i8 4, i8 4, i8 4>)
+  ret void
+}
+
diff --git a/test/CodeGen/SystemZ/vec-args-error-01.ll b/test/CodeGen/SystemZ/vec-args-error-01.ll
new file mode 100644
index 000000000000..e2f537949595
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-args-error-01.ll
@@ -0,0 +1,9 @@
+; Verify that we detect unsupported single-element vector types.
+
+; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s
+
+define void @foo(<1 x i128>) {
+  ret void
+}
+
+; CHECK: LLVM ERROR: Unsupported vector argument or return type
diff --git a/test/CodeGen/SystemZ/vec-args-error-02.ll b/test/CodeGen/SystemZ/vec-args-error-02.ll
new file mode 100644
index 000000000000..a5ae1102a748
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-args-error-02.ll
@@ -0,0 +1,9 @@
+; Verify that we detect unsupported single-element vector types.
+
+; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s
+
+define <1 x i128> @foo() {
+  ret <1 x i128><i128 0>
+}
+
+; CHECK: LLVM ERROR: Unsupported vector argument or return type
diff --git a/test/CodeGen/SystemZ/vec-args-error-03.ll b/test/CodeGen/SystemZ/vec-args-error-03.ll
new file mode 100644
index 000000000000..14698aae43bc
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-args-error-03.ll
@@ -0,0 +1,12 @@
+; Verify that we detect unsupported single-element vector types.
+
+; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s
+
+declare void @bar(<1 x i128>)
+
+define void @foo() {
+  call void @bar (<1 x i128> <i128 0>)
+  ret void
+}
+
+; CHECK: LLVM ERROR: Unsupported vector argument or return type
diff --git a/test/CodeGen/SystemZ/vec-args-error-04.ll b/test/CodeGen/SystemZ/vec-args-error-04.ll
new file mode 100644
index 000000000000..a54ee90022c8
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-args-error-04.ll
@@ -0,0 +1,12 @@
+; Verify that we detect unsupported single-element vector types.
+
+; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s
+
+declare <1 x i128> @bar()
+
+define void @foo() {
+  %res = call <1 x i128> @bar ()
+  ret void
+}
+
+; CHECK: LLVM ERROR: Unsupported vector argument or return type
diff --git a/test/CodeGen/SystemZ/vec-args-error-05.ll b/test/CodeGen/SystemZ/vec-args-error-05.ll
new file mode 100644
index 000000000000..067deb1c88b8
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-args-error-05.ll
@@ -0,0 +1,9 @@
+; Verify that we detect unsupported single-element vector types.
+
+; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s
+
+define void @foo(<1 x fp128>) {
+  ret void
+}
+
+; CHECK: LLVM ERROR: Unsupported vector argument or return type
diff --git a/test/CodeGen/SystemZ/vec-args-error-06.ll b/test/CodeGen/SystemZ/vec-args-error-06.ll
new file mode 100644
index 000000000000..a9184d735750
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-args-error-06.ll
@@ -0,0 +1,9 @@
+; Verify that we detect unsupported single-element vector types.
+
+; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s
+
+define <1 x fp128> @foo() {
+  ret <1 x fp128><fp128 0xL00000000000000000000000000000000>
+}
+
+; CHECK: LLVM ERROR: Unsupported vector argument or return type
diff --git a/test/CodeGen/SystemZ/vec-args-error-07.ll b/test/CodeGen/SystemZ/vec-args-error-07.ll
new file mode 100644
index 000000000000..4e9140093915
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-args-error-07.ll
@@ -0,0 +1,12 @@
+; Verify that we detect unsupported single-element vector types.
+
+; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s
+
+declare void @bar(<1 x fp128>)
+
+define void @foo() {
+  call void @bar (<1 x fp128> <fp128 0xL00000000000000000000000000000000>)
+  ret void
+}
+
+; CHECK: LLVM ERROR: Unsupported vector argument or return type
diff --git a/test/CodeGen/SystemZ/vec-args-error-08.ll b/test/CodeGen/SystemZ/vec-args-error-08.ll
new file mode 100644
index 000000000000..7b16b9f46e39
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-args-error-08.ll
@@ -0,0 +1,12 @@
+; Verify that we detect unsupported single-element vector types.
+
+; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s
+
+declare <1 x fp128> @bar()
+
+define void @foo() {
+  %res = call <1 x fp128> @bar ()
+  ret void
+}
+
+; CHECK: LLVM ERROR: Unsupported vector argument or return type
diff --git a/test/CodeGen/SystemZ/vec-cmp-01.ll b/test/CodeGen/SystemZ/vec-cmp-01.ll
new file mode 100644
index 000000000000..a7546db8d7f1
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-cmp-01.ll
@@ -0,0 +1,228 @@
+; Test v16i8 comparisons.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test eq.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vceqb %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = icmp eq <16 x i8> %val1, %val2
+  %ret = sext <16 x i1> %cmp to <16 x i8>
+  ret <16 x i8> %ret
+}
+
+; Test ne.
+define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vceqb [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ne <16 x i8> %val1, %val2
+  %ret = sext <16 x i1> %cmp to <16 x i8>
+  ret <16 x i8> %ret
+}
+
+; Test sgt.
+define <16 x i8> @f3(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vchb %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = icmp sgt <16 x i8> %val1, %val2
+  %ret = sext <16 x i1> %cmp to <16 x i8>
+  ret <16 x i8> %ret
+}
+
+; Test sge.
+define <16 x i8> @f4(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vchb [[REG:%v[0-9]+]], %v28, %v26
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sge <16 x i8> %val1, %val2
+  %ret = sext <16 x i1> %cmp to <16 x i8>
+  ret <16 x i8> %ret
+}
+
+; Test sle.
+define <16 x i8> @f5(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vchb [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sle <16 x i8> %val1, %val2
+  %ret = sext <16 x i1> %cmp to <16 x i8>
+  ret <16 x i8> %ret
+}
+
+; Test slt.
+define <16 x i8> @f6(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vchb %v24, %v28, %v26
+; CHECK-NEXT: br %r14
+  %cmp = icmp slt <16 x i8> %val1, %val2
+  %ret = sext <16 x i1> %cmp to <16 x i8>
+  ret <16 x i8> %ret
+}
+
+; Test ugt.
+define <16 x i8> @f7(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vchlb %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = icmp ugt <16 x i8> %val1, %val2
+  %ret = sext <16 x i1> %cmp to <16 x i8>
+  ret <16 x i8> %ret
+}
+
+; Test uge.
+define <16 x i8> @f8(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vchlb [[REG:%v[0-9]+]], %v28, %v26
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp uge <16 x i8> %val1, %val2
+  %ret = sext <16 x i1> %cmp to <16 x i8>
+  ret <16 x i8> %ret
+}
+
+; Test ule.
+define <16 x i8> @f9(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f9:
+; CHECK: vchlb [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ule <16 x i8> %val1, %val2
+  %ret = sext <16 x i1> %cmp to <16 x i8>
+  ret <16 x i8> %ret
+}
+
+; Test ult.
+define <16 x i8> @f10(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f10:
+; CHECK: vchlb %v24, %v28, %v26
+; CHECK-NEXT: br %r14
+  %cmp = icmp ult <16 x i8> %val1, %val2
+  %ret = sext <16 x i1> %cmp to <16 x i8>
+  ret <16 x i8> %ret
+}
+
+; Test eq selects.
+define <16 x i8> @f11(<16 x i8> %val1, <16 x i8> %val2,
+                      <16 x i8> %val3, <16 x i8> %val4) {
+; CHECK-LABEL: f11:
+; CHECK: vceqb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp eq <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
+  ret <16 x i8> %ret
+}
+
+; Test ne selects.
+define <16 x i8> @f12(<16 x i8> %val1, <16 x i8> %val2,
+                      <16 x i8> %val3, <16 x i8> %val4) {
+; CHECK-LABEL: f12:
+; CHECK: vceqb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ne <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
+  ret <16 x i8> %ret
+}
+
+; Test sgt selects.
+define <16 x i8> @f13(<16 x i8> %val1, <16 x i8> %val2,
+                      <16 x i8> %val3, <16 x i8> %val4) {
+; CHECK-LABEL: f13:
+; CHECK: vchb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sgt <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
+  ret <16 x i8> %ret
+}
+
+; Test sge selects.
+define <16 x i8> @f14(<16 x i8> %val1, <16 x i8> %val2,
+                      <16 x i8> %val3, <16 x i8> %val4) {
+; CHECK-LABEL: f14:
+; CHECK: vchb [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sge <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
+  ret <16 x i8> %ret
+}
+
+; Test sle selects.
+define <16 x i8> @f15(<16 x i8> %val1, <16 x i8> %val2,
+                      <16 x i8> %val3, <16 x i8> %val4) {
+; CHECK-LABEL: f15:
+; CHECK: vchb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sle <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
+  ret <16 x i8> %ret
+}
+
+; Test slt selects.
+define <16 x i8> @f16(<16 x i8> %val1, <16 x i8> %val2,
+                      <16 x i8> %val3, <16 x i8> %val4) {
+; CHECK-LABEL: f16:
+; CHECK: vchb [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp slt <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
+  ret <16 x i8> %ret
+}
+
+; Test ugt selects.
+define <16 x i8> @f17(<16 x i8> %val1, <16 x i8> %val2,
+                      <16 x i8> %val3, <16 x i8> %val4) {
+; CHECK-LABEL: f17:
+; CHECK: vchlb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ugt <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
+  ret <16 x i8> %ret
+}
+
+; Test uge selects.
+define <16 x i8> @f18(<16 x i8> %val1, <16 x i8> %val2,
+                      <16 x i8> %val3, <16 x i8> %val4) {
+; CHECK-LABEL: f18:
+; CHECK: vchlb [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp uge <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
+  ret <16 x i8> %ret
+}
+
+; Test ule selects.
+define <16 x i8> @f19(<16 x i8> %val1, <16 x i8> %val2,
+                      <16 x i8> %val3, <16 x i8> %val4) {
+; CHECK-LABEL: f19:
+; CHECK: vchlb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ule <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
+  ret <16 x i8> %ret
+}
+
+; Test ult selects.
+define <16 x i8> @f20(<16 x i8> %val1, <16 x i8> %val2,
+                      <16 x i8> %val3, <16 x i8> %val4) {
+; CHECK-LABEL: f20:
+; CHECK: vchlb [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ult <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
+  ret <16 x i8> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-cmp-02.ll b/test/CodeGen/SystemZ/vec-cmp-02.ll
new file mode 100644
index 000000000000..78fb46c01c08
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-cmp-02.ll
@@ -0,0 +1,228 @@
+; Test v8i16 comparisons.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test eq.
+define <8 x i16> @f1(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vceqh %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = icmp eq <8 x i16> %val1, %val2
+  %ret = sext <8 x i1> %cmp to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test ne.
+define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vceqh [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ne <8 x i16> %val1, %val2
+  %ret = sext <8 x i1> %cmp to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test sgt.
+define <8 x i16> @f3(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vchh %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = icmp sgt <8 x i16> %val1, %val2
+  %ret = sext <8 x i1> %cmp to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test sge.
+define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vchh [[REG:%v[0-9]+]], %v28, %v26
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sge <8 x i16> %val1, %val2
+  %ret = sext <8 x i1> %cmp to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test sle.
+define <8 x i16> @f5(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vchh [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sle <8 x i16> %val1, %val2
+  %ret = sext <8 x i1> %cmp to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test slt.
+define <8 x i16> @f6(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vchh %v24, %v28, %v26
+; CHECK-NEXT: br %r14
+  %cmp = icmp slt <8 x i16> %val1, %val2
+  %ret = sext <8 x i1> %cmp to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test ugt.
+define <8 x i16> @f7(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vchlh %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = icmp ugt <8 x i16> %val1, %val2
+  %ret = sext <8 x i1> %cmp to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test uge.
+define <8 x i16> @f8(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vchlh [[REG:%v[0-9]+]], %v28, %v26
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp uge <8 x i16> %val1, %val2
+  %ret = sext <8 x i1> %cmp to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test ule.
+define <8 x i16> @f9(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f9:
+; CHECK: vchlh [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ule <8 x i16> %val1, %val2
+  %ret = sext <8 x i1> %cmp to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test ult.
+define <8 x i16> @f10(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f10:
+; CHECK: vchlh %v24, %v28, %v26
+; CHECK-NEXT: br %r14
+  %cmp = icmp ult <8 x i16> %val1, %val2
+  %ret = sext <8 x i1> %cmp to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test eq selects.
+define <8 x i16> @f11(<8 x i16> %val1, <8 x i16> %val2,
+                      <8 x i16> %val3, <8 x i16> %val4) {
+; CHECK-LABEL: f11:
+; CHECK: vceqh [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp eq <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
+  ret <8 x i16> %ret
+}
+
+; Test ne selects.
+define <8 x i16> @f12(<8 x i16> %val1, <8 x i16> %val2,
+                      <8 x i16> %val3, <8 x i16> %val4) {
+; CHECK-LABEL: f12:
+; CHECK: vceqh [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ne <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
+  ret <8 x i16> %ret
+}
+
+; Test sgt selects.
+define <8 x i16> @f13(<8 x i16> %val1, <8 x i16> %val2,
+                      <8 x i16> %val3, <8 x i16> %val4) {
+; CHECK-LABEL: f13:
+; CHECK: vchh [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sgt <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
+  ret <8 x i16> %ret
+}
+
+; Test sge selects.
+define <8 x i16> @f14(<8 x i16> %val1, <8 x i16> %val2,
+                      <8 x i16> %val3, <8 x i16> %val4) {
+; CHECK-LABEL: f14:
+; CHECK: vchh [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sge <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
+  ret <8 x i16> %ret
+}
+
+; Test sle selects.
+define <8 x i16> @f15(<8 x i16> %val1, <8 x i16> %val2,
+                      <8 x i16> %val3, <8 x i16> %val4) {
+; CHECK-LABEL: f15:
+; CHECK: vchh [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sle <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
+  ret <8 x i16> %ret
+}
+
+; Test slt selects.
+define <8 x i16> @f16(<8 x i16> %val1, <8 x i16> %val2,
+                      <8 x i16> %val3, <8 x i16> %val4) {
+; CHECK-LABEL: f16:
+; CHECK: vchh [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp slt <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
+  ret <8 x i16> %ret
+}
+
+; Test ugt selects.
+define <8 x i16> @f17(<8 x i16> %val1, <8 x i16> %val2,
+                      <8 x i16> %val3, <8 x i16> %val4) {
+; CHECK-LABEL: f17:
+; CHECK: vchlh [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ugt <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
+  ret <8 x i16> %ret
+}
+
+; Test uge selects.
+define <8 x i16> @f18(<8 x i16> %val1, <8 x i16> %val2,
+                      <8 x i16> %val3, <8 x i16> %val4) {
+; CHECK-LABEL: f18:
+; CHECK: vchlh [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp uge <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
+  ret <8 x i16> %ret
+}
+
+; Test ule selects.
+define <8 x i16> @f19(<8 x i16> %val1, <8 x i16> %val2,
+                      <8 x i16> %val3, <8 x i16> %val4) {
+; CHECK-LABEL: f19:
+; CHECK: vchlh [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ule <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
+  ret <8 x i16> %ret
+}
+
+; Test ult selects.
+define <8 x i16> @f20(<8 x i16> %val1, <8 x i16> %val2,
+                      <8 x i16> %val3, <8 x i16> %val4) {
+; CHECK-LABEL: f20:
+; CHECK: vchlh [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ult <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
+  ret <8 x i16> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-cmp-03.ll b/test/CodeGen/SystemZ/vec-cmp-03.ll
new file mode 100644
index 000000000000..4b070acc935b
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-cmp-03.ll
@@ -0,0 +1,228 @@
+; Test v4i32 comparisons.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test eq.
+define <4 x i32> @f1(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vceqf %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = icmp eq <4 x i32> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test ne.
+define <4 x i32> @f2(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vceqf [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ne <4 x i32> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test sgt.
+define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vchf %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = icmp sgt <4 x i32> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test sge.
+define <4 x i32> @f4(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vchf [[REG:%v[0-9]+]], %v28, %v26
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sge <4 x i32> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test sle.
+define <4 x i32> @f5(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sle <4 x i32> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test slt.
+define <4 x i32> @f6(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vchf %v24, %v28, %v26
+; CHECK-NEXT: br %r14
+  %cmp = icmp slt <4 x i32> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test ugt.
+define <4 x i32> @f7(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vchlf %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = icmp ugt <4 x i32> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test uge.
+define <4 x i32> @f8(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vchlf [[REG:%v[0-9]+]], %v28, %v26
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp uge <4 x i32> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test ule.
+define <4 x i32> @f9(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f9:
+; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ule <4 x i32> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test ult.
+define <4 x i32> @f10(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f10:
+; CHECK: vchlf %v24, %v28, %v26
+; CHECK-NEXT: br %r14
+  %cmp = icmp ult <4 x i32> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test eq selects.
+define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2,
+                      <4 x i32> %val3, <4 x i32> %val4) {
+; CHECK-LABEL: f11:
+; CHECK: vceqf [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp eq <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
+  ret <4 x i32> %ret
+}
+
+; Test ne selects.
+define <4 x i32> @f12(<4 x i32> %val1, <4 x i32> %val2,
+                      <4 x i32> %val3, <4 x i32> %val4) {
+; CHECK-LABEL: f12:
+; CHECK: vceqf [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ne <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
+  ret <4 x i32> %ret
+}
+
+; Test sgt selects.
+define <4 x i32> @f13(<4 x i32> %val1, <4 x i32> %val2,
+                      <4 x i32> %val3, <4 x i32> %val4) {
+; CHECK-LABEL: f13:
+; CHECK: vchf [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sgt <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
+  ret <4 x i32> %ret
+}
+
+; Test sge selects.
+define <4 x i32> @f14(<4 x i32> %val1, <4 x i32> %val2,
+                      <4 x i32> %val3, <4 x i32> %val4) {
+; CHECK-LABEL: f14:
+; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sge <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
+  ret <4 x i32> %ret
+}
+
+; Test sle selects.
+define <4 x i32> @f15(<4 x i32> %val1, <4 x i32> %val2,
+                      <4 x i32> %val3, <4 x i32> %val4) {
+; CHECK-LABEL: f15:
+; CHECK: vchf [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sle <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
+  ret <4 x i32> %ret
+}
+
+; Test slt selects.
+define <4 x i32> @f16(<4 x i32> %val1, <4 x i32> %val2,
+                      <4 x i32> %val3, <4 x i32> %val4) {
+; CHECK-LABEL: f16:
+; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp slt <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
+  ret <4 x i32> %ret
+}
+
+; Test ugt selects.
+define <4 x i32> @f17(<4 x i32> %val1, <4 x i32> %val2,
+                      <4 x i32> %val3, <4 x i32> %val4) {
+; CHECK-LABEL: f17:
+; CHECK: vchlf [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ugt <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
+  ret <4 x i32> %ret
+}
+
+; Test uge selects.
+define <4 x i32> @f18(<4 x i32> %val1, <4 x i32> %val2,
+                      <4 x i32> %val3, <4 x i32> %val4) {
+; CHECK-LABEL: f18:
+; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp uge <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
+  ret <4 x i32> %ret
+}
+
+; Test ule selects.
+define <4 x i32> @f19(<4 x i32> %val1, <4 x i32> %val2,
+                      <4 x i32> %val3, <4 x i32> %val4) {
+; CHECK-LABEL: f19:
+; CHECK: vchlf [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ule <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
+  ret <4 x i32> %ret
+}
+
+; Test ult selects.
+define <4 x i32> @f20(<4 x i32> %val1, <4 x i32> %val2,
+                      <4 x i32> %val3, <4 x i32> %val4) {
+; CHECK-LABEL: f20:
+; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ult <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
+  ret <4 x i32> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-cmp-04.ll b/test/CodeGen/SystemZ/vec-cmp-04.ll
new file mode 100644
index 000000000000..5cecaa7251b7
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-cmp-04.ll
@@ -0,0 +1,228 @@
+; Test v2i64 comparisons.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test eq.
+define <2 x i64> @f1(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vceqg %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = icmp eq <2 x i64> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ne.
+define <2 x i64> @f2(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vceqg [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ne <2 x i64> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test sgt.
+define <2 x i64> @f3(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vchg %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = icmp sgt <2 x i64> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test sge.
+define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vchg [[REG:%v[0-9]+]], %v28, %v26
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sge <2 x i64> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test sle.
+define <2 x i64> @f5(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vchg [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sle <2 x i64> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test slt.
+define <2 x i64> @f6(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vchg %v24, %v28, %v26
+; CHECK-NEXT: br %r14
+  %cmp = icmp slt <2 x i64> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ugt.
+define <2 x i64> @f7(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vchlg %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = icmp ugt <2 x i64> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test uge.
+define <2 x i64> @f8(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vchlg [[REG:%v[0-9]+]], %v28, %v26
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp uge <2 x i64> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ule.
+define <2 x i64> @f9(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f9:
+; CHECK: vchlg [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ule <2 x i64> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ult.
+define <2 x i64> @f10(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f10:
+; CHECK: vchlg %v24, %v28, %v26
+; CHECK-NEXT: br %r14
+  %cmp = icmp ult <2 x i64> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test eq selects.
+define <2 x i64> @f11(<2 x i64> %val1, <2 x i64> %val2,
+                      <2 x i64> %val3, <2 x i64> %val4) {
+; CHECK-LABEL: f11:
+; CHECK: vceqg [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp eq <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
+  ret <2 x i64> %ret
+}
+
+; Test ne selects.
+define <2 x i64> @f12(<2 x i64> %val1, <2 x i64> %val2,
+                      <2 x i64> %val3, <2 x i64> %val4) {
+; CHECK-LABEL: f12:
+; CHECK: vceqg [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ne <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
+  ret <2 x i64> %ret
+}
+
+; Test sgt selects.
+define <2 x i64> @f13(<2 x i64> %val1, <2 x i64> %val2,
+                      <2 x i64> %val3, <2 x i64> %val4) {
+; CHECK-LABEL: f13:
+; CHECK: vchg [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sgt <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
+  ret <2 x i64> %ret
+}
+
+; Test sge selects.
+define <2 x i64> @f14(<2 x i64> %val1, <2 x i64> %val2,
+                      <2 x i64> %val3, <2 x i64> %val4) {
+; CHECK-LABEL: f14:
+; CHECK: vchg [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sge <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
+  ret <2 x i64> %ret
+}
+
+; Test sle selects.
+define <2 x i64> @f15(<2 x i64> %val1, <2 x i64> %val2,
+                      <2 x i64> %val3, <2 x i64> %val4) {
+; CHECK-LABEL: f15:
+; CHECK: vchg [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp sle <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
+  ret <2 x i64> %ret
+}
+
+; Test slt selects.
+define <2 x i64> @f16(<2 x i64> %val1, <2 x i64> %val2,
+                      <2 x i64> %val3, <2 x i64> %val4) {
+; CHECK-LABEL: f16:
+; CHECK: vchg [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp slt <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
+  ret <2 x i64> %ret
+}
+
+; Test ugt selects.
+define <2 x i64> @f17(<2 x i64> %val1, <2 x i64> %val2,
+                      <2 x i64> %val3, <2 x i64> %val4) {
+; CHECK-LABEL: f17:
+; CHECK: vchlg [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ugt <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
+  ret <2 x i64> %ret
+}
+
+; Test uge selects.
+define <2 x i64> @f18(<2 x i64> %val1, <2 x i64> %val2,
+                      <2 x i64> %val3, <2 x i64> %val4) {
+; CHECK-LABEL: f18:
+; CHECK: vchlg [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp uge <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
+  ret <2 x i64> %ret
+}
+
+; Test ule selects.
+define <2 x i64> @f19(<2 x i64> %val1, <2 x i64> %val2,
+                      <2 x i64> %val3, <2 x i64> %val4) {
+; CHECK-LABEL: f19:
+; CHECK: vchlg [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ule <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
+  ret <2 x i64> %ret
+}
+
+; Test ult selects.
+define <2 x i64> @f20(<2 x i64> %val1, <2 x i64> %val2,
+                      <2 x i64> %val3, <2 x i64> %val4) {
+; CHECK-LABEL: f20:
+; CHECK: vchlg [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = icmp ult <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-cmp-05.ll b/test/CodeGen/SystemZ/vec-cmp-05.ll
new file mode 100644
index 000000000000..74e990960972
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-cmp-05.ll
@@ -0,0 +1,472 @@
+; Test v4f32 comparisons.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test oeq.
+define <4 x i32> @f1(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f1:
+; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
+; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
+; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
+; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
+; CHECK-DAG: vfcedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
+; CHECK-DAG: vfcedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
+; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp oeq <4 x float> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test one.
+define <4 x i32> @f2(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f2:
+; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
+; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
+; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
+; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
+; CHECK-DAG: vfchdb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
+; CHECK-DAG: vfchdb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
+; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
+; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
+; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]]
+; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]
+; CHECK: vo %v24, [[RES1]], [[RES0]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp one <4 x float> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test ogt.
+define <4 x i32> @f3(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f3:
+; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
+; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
+; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
+; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
+; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
+; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
+; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ogt <4 x float> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test oge.
+define <4 x i32> @f4(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f4:
+; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
+; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
+; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
+; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
+; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
+; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
+; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp oge <4 x float> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test ole.
+define <4 x i32> @f5(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f5:
+; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
+; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
+; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
+; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
+; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
+; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
+; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ole <4 x float> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test olt.
+define <4 x i32> @f6(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f6:
+; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
+; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
+; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
+; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
+; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
+; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
+; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp olt <4 x float> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test ueq.
+define <4 x i32> @f7(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f7:
+; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
+; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
+; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
+; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
+; CHECK-DAG: vfchdb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
+; CHECK-DAG: vfchdb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
+; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
+; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
+; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]]
+; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]
+; CHECK: vno %v24, [[RES1]], [[RES0]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ueq <4 x float> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test une.
+define <4 x i32> @f8(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f8:
+; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
+; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
+; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
+; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
+; CHECK-DAG: vfcedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
+; CHECK-DAG: vfcedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
+; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]]
+; CHECK-NEXT: vno %v24, [[RES]], [[RES]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp une <4 x float> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test ugt.
+define <4 x i32> @f9(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f9:
+; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
+; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
+; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
+; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
+; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
+; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
+; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]]
+; CHECK-NEXT: vno %v24, [[RES]], [[RES]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ugt <4 x float> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test uge.
+define <4 x i32> @f10(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f10:
+; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
+; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
+; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
+; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
+; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
+; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
+; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]]
+; CHECK-NEXT: vno %v24, [[RES]], [[RES]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp uge <4 x float> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test ule.
+define <4 x i32> @f11(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f11:
+; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
+; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
+; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
+; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
+; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
+; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
+; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]]
+; CHECK-NEXT: vno %v24, [[RES]], [[RES]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ule <4 x float> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test ult.
+define <4 x i32> @f12(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f12:
+; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
+; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
+; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
+; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
+; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
+; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
+; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]]
+; CHECK-NEXT: vno %v24, [[RES]], [[RES]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ult <4 x float> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test ord.
+define <4 x i32> @f13(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f13:
+; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
+; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
+; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
+; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
+; CHECK-DAG: vfchedb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
+; CHECK-DAG: vfchedb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
+; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
+; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
+; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]]
+; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]
+; CHECK: vo %v24, [[RES1]], [[RES0]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ord <4 x float> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test uno.
+define <4 x i32> @f14(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f14:
+; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
+; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
+; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
+; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
+; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
+; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
+; CHECK-DAG: vfchedb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
+; CHECK-DAG: vfchedb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
+; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
+; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
+; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]]
+; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]
+; CHECK: vno %v24, [[RES1]], [[RES0]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp uno <4 x float> %val1, %val2
+  %ret = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test oeq selects.
+define <4 x float> @f15(<4 x float> %val1, <4 x float> %val2,
+                        <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: f15:
+; CHECK: vpkg [[REG:%v[0-9]+]],
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp oeq <4 x float> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
+  ret <4 x float> %ret
+}
+
+; Test one selects.
+define <4 x float> @f16(<4 x float> %val1, <4 x float> %val2,
+                        <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: f16:
+; CHECK: vo [[REG:%v[0-9]+]],
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp one <4 x float> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
+  ret <4 x float> %ret
+}
+
+; Test ogt selects.
+define <4 x float> @f17(<4 x float> %val1, <4 x float> %val2,
+                        <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: f17:
+; CHECK: vpkg [[REG:%v[0-9]+]],
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ogt <4 x float> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
+  ret <4 x float> %ret
+}
+
+; Test oge selects.
+define <4 x float> @f18(<4 x float> %val1, <4 x float> %val2,
+                        <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: f18:
+; CHECK: vpkg [[REG:%v[0-9]+]],
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp oge <4 x float> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
+  ret <4 x float> %ret
+}
+
+; Test ole selects.
+define <4 x float> @f19(<4 x float> %val1, <4 x float> %val2,
+                        <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: f19:
+; CHECK: vpkg [[REG:%v[0-9]+]],
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ole <4 x float> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
+  ret <4 x float> %ret
+}
+
+; Test olt selects.
+define <4 x float> @f20(<4 x float> %val1, <4 x float> %val2,
+                        <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: f20:
+; CHECK: vpkg [[REG:%v[0-9]+]],
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp olt <4 x float> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
+  ret <4 x float> %ret
+}
+
+; Test ueq selects.
+define <4 x float> @f21(<4 x float> %val1, <4 x float> %val2,
+                        <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: f21:
+; CHECK: vo [[REG:%v[0-9]+]],
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ueq <4 x float> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
+  ret <4 x float> %ret
+}
+
+; Test une selects.
+define <4 x float> @f22(<4 x float> %val1, <4 x float> %val2,
+                        <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: f22:
+; CHECK: vpkg [[REG:%v[0-9]+]],
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp une <4 x float> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
+  ret <4 x float> %ret
+}
+
+; Test ugt selects.
+define <4 x float> @f23(<4 x float> %val1, <4 x float> %val2,
+                        <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: f23:
+; CHECK: vpkg [[REG:%v[0-9]+]],
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ugt <4 x float> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
+  ret <4 x float> %ret
+}
+
+; Test uge selects.
+define <4 x float> @f24(<4 x float> %val1, <4 x float> %val2,
+                        <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: f24:
+; CHECK: vpkg [[REG:%v[0-9]+]],
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp uge <4 x float> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
+  ret <4 x float> %ret
+}
+
+; Test ule selects.
+define <4 x float> @f25(<4 x float> %val1, <4 x float> %val2,
+                        <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: f25:
+; CHECK: vpkg [[REG:%v[0-9]+]],
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ule <4 x float> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
+  ret <4 x float> %ret
+}
+
+; Test ult selects.
+define <4 x float> @f26(<4 x float> %val1, <4 x float> %val2,
+                        <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: f26:
+; CHECK: vpkg [[REG:%v[0-9]+]],
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ult <4 x float> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
+  ret <4 x float> %ret
+}
+
+; Test ord selects.
+define <4 x float> @f27(<4 x float> %val1, <4 x float> %val2,
+                        <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: f27:
+; CHECK: vo [[REG:%v[0-9]+]],
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ord <4 x float> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
+  ret <4 x float> %ret
+}
+
+; Test uno selects.
+define <4 x float> @f28(<4 x float> %val1, <4 x float> %val2,
+                        <4 x float> %val3, <4 x float> %val4) {
+; CHECK-LABEL: f28:
+; CHECK: vo [[REG:%v[0-9]+]],
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp uno <4 x float> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
+  ret <4 x float> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-cmp-06.ll b/test/CodeGen/SystemZ/vec-cmp-06.ll
new file mode 100644
index 000000000000..eef57555b482
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-cmp-06.ll
@@ -0,0 +1,349 @@
+; Test f64 and v2f64 comparisons.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test oeq.
+define <2 x i64> @f1(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vfcedb %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = fcmp oeq <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test one.
+define <2 x i64> @f2(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f2:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26
+; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v26, %v28
+; CHECK: vo %v24, [[REG1]], [[REG2]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp one <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ogt.
+define <2 x i64> @f3(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vfchdb %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ogt <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test oge.
+define <2 x i64> @f4(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vfchedb %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = fcmp oge <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ole.
+define <2 x i64> @f5(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vfchedb %v24, %v28, %v26
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ole <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test olt.
+define <2 x i64> @f6(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vfchdb %v24, %v28, %v26
+; CHECK-NEXT: br %r14
+  %cmp = fcmp olt <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ueq.
+define <2 x i64> @f7(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f7:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26
+; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v26, %v28
+; CHECK: vno %v24, [[REG1]], [[REG2]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ueq <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test une.
+define <2 x i64> @f8(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vfcedb [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp une <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ugt.
+define <2 x i64> @f9(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f9:
+; CHECK: vfchedb [[REG:%v[0-9]+]], %v28, %v26
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ugt <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test uge.
+define <2 x i64> @f10(<2 x i64> %dummy, <2 x double> %val1,
+                      <2 x double> %val2) {
+; CHECK-LABEL: f10:
+; CHECK: vfchdb [[REG:%v[0-9]+]], %v28, %v26
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp uge <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ule.
+define <2 x i64> @f11(<2 x i64> %dummy, <2 x double> %val1,
+                      <2 x double> %val2) {
+; CHECK-LABEL: f11:
+; CHECK: vfchdb [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ule <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ult.
+define <2 x i64> @f12(<2 x i64> %dummy, <2 x double> %val1,
+                      <2 x double> %val2) {
+; CHECK-LABEL: f12:
+; CHECK: vfchedb [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ult <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ord.
+define <2 x i64> @f13(<2 x i64> %dummy, <2 x double> %val1,
+                      <2 x double> %val2) {
+; CHECK-LABEL: f13:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26
+; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v26, %v28
+; CHECK: vo %v24, [[REG1]], [[REG2]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ord <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test uno.
+define <2 x i64> @f14(<2 x i64> %dummy, <2 x double> %val1,
+                      <2 x double> %val2) {
+; CHECK-LABEL: f14:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26
+; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v26, %v28
+; CHECK: vno %v24, [[REG1]], [[REG2]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp uno <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test oeq selects.
+define <2 x double> @f15(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f15:
+; CHECK: vfcedb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp oeq <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test one selects.
+define <2 x double> @f16(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f16:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24
+; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v24, %v26
+; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp one <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test ogt selects.
+define <2 x double> @f17(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f17:
+; CHECK: vfchdb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ogt <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test oge selects.
+define <2 x double> @f18(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f18:
+; CHECK: vfchedb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp oge <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test ole selects.
+define <2 x double> @f19(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f19:
+; CHECK: vfchedb [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ole <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test olt selects.
+define <2 x double> @f20(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f20:
+; CHECK: vfchdb [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp olt <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test ueq selects.
+define <2 x double> @f21(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f21:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24
+; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v24, %v26
+; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ueq <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test une selects.
+define <2 x double> @f22(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f22:
+; CHECK: vfcedb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp une <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test ugt selects.
+define <2 x double> @f23(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f23:
+; CHECK: vfchedb [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ugt <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test uge selects.
+define <2 x double> @f24(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f24:
+; CHECK: vfchdb [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp uge <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test ule selects.
+define <2 x double> @f25(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f25:
+; CHECK: vfchdb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ule <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test ult selects.
+define <2 x double> @f26(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f26:
+; CHECK: vfchedb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ult <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test ord selects.
+define <2 x double> @f27(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f27:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24
+; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v24, %v26
+; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ord <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test uno selects.
+define <2 x double> @f28(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f28:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24
+; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v24, %v26
+; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp uno <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test an f64 comparison that uses vector registers.
+define i64 @f29(i64 %a, i64 %b, double %f1, <2 x double> %vec) {
+; CHECK-LABEL: f29:
+; CHECK: wfcdb %f0, %v24
+; CHECK-NEXT: locgrne %r2, %r3
+; CHECK: br %r14
+  %f2 = extractelement <2 x double> %vec, i32 0
+  %cond = fcmp oeq double %f1, %f2
+  %res = select i1 %cond, i64 %a, i64 %b
+  ret i64 %res
+}
diff --git a/test/CodeGen/SystemZ/vec-combine-01.ll b/test/CodeGen/SystemZ/vec-combine-01.ll
new file mode 100644
index 000000000000..a35934421726
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-combine-01.ll
@@ -0,0 +1,155 @@
+; Test various target-specific DAG combiner patterns.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Check that an extraction followed by a truncation is effectively treated
+; as a bitcast.
+define void @f1(<4 x i32> %v1, <4 x i32> %v2, i8 *%ptr1, i8 *%ptr2) {
+; CHECK-LABEL: f1:
+; CHECK: vaf [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-DAG: vsteb [[REG]], 0(%r2), 3
+; CHECK-DAG: vsteb [[REG]], 0(%r3), 15
+; CHECK: br %r14
+  %add = add <4 x i32> %v1, %v2
+  %elem1 = extractelement <4 x i32> %add, i32 0
+  %elem2 = extractelement <4 x i32> %add, i32 3
+  %trunc1 = trunc i32 %elem1 to i8
+  %trunc2 = trunc i32 %elem2 to i8
+  store i8 %trunc1, i8 *%ptr1
+  store i8 %trunc2, i8 *%ptr2
+  ret void
+}
+
+; Test a case where a pack-type shuffle can be eliminated.
+define i16 @f2(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
+; CHECK-LABEL: f2:
+; CHECK-NOT: vpk
+; CHECK-DAG: vaf [[REG1:%v[0-9]+]], %v24, %v26
+; CHECK-DAG: vaf [[REG2:%v[0-9]+]], %v26, %v28
+; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG1]], 3
+; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG2]], 7
+; CHECK: br %r14
+  %add1 = add <4 x i32> %v1, %v2
+  %add2 = add <4 x i32> %v2, %v3
+  %shuffle = shufflevector <4 x i32> %add1, <4 x i32> %add2,
+                           <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %bitcast = bitcast <4 x i32> %shuffle to <8 x i16>
+  %elem1 = extractelement <8 x i16> %bitcast, i32 1
+  %elem2 = extractelement <8 x i16> %bitcast, i32 7
+  %res = add i16 %elem1, %elem2
+  ret i16 %res
+}
+
+; ...and again in a case where there's also a splat and a bitcast.
+define i16 @f3(<4 x i32> %v1, <4 x i32> %v2, <2 x i64> %v3) {
+; CHECK-LABEL: f3:
+; CHECK-NOT: vrepg
+; CHECK-NOT: vpk
+; CHECK-DAG: vaf [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG]], 6
+; CHECK-DAG: vlgvh {{%r[0-5]}}, %v28, 3
+; CHECK: br %r14
+  %add = add <4 x i32> %v1, %v2
+  %splat = shufflevector <2 x i64> %v3, <2 x i64> undef,
+                         <2 x i32> <i32 0, i32 0>
+  %splatcast = bitcast <2 x i64> %splat to <4 x i32>
+  %shuffle = shufflevector <4 x i32> %add, <4 x i32> %splatcast,
+                           <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %bitcast = bitcast <4 x i32> %shuffle to <8 x i16>
+  %elem1 = extractelement <8 x i16> %bitcast, i32 2
+  %elem2 = extractelement <8 x i16> %bitcast, i32 7
+  %res = add i16 %elem1, %elem2
+  ret i16 %res
+}
+
+; ...and again with a merge low instead of a pack.
+define i16 @f4(<4 x i32> %v1, <4 x i32> %v2, <2 x i64> %v3) {
+; CHECK-LABEL: f4:
+; CHECK-NOT: vrepg
+; CHECK-NOT: vmr
+; CHECK-DAG: vaf [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG]], 6
+; CHECK-DAG: vlgvh {{%r[0-5]}}, %v28, 3
+; CHECK: br %r14
+  %add = add <4 x i32> %v1, %v2
+  %splat = shufflevector <2 x i64> %v3, <2 x i64> undef,
+                         <2 x i32> <i32 0, i32 0>
+  %splatcast = bitcast <2 x i64> %splat to <4 x i32>
+  %shuffle = shufflevector <4 x i32> %add, <4 x i32> %splatcast,
+                           <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+  %bitcast = bitcast <4 x i32> %shuffle to <8 x i16>
+  %elem1 = extractelement <8 x i16> %bitcast, i32 4
+  %elem2 = extractelement <8 x i16> %bitcast, i32 7
+  %res = add i16 %elem1, %elem2
+  ret i16 %res
+}
+
+; ...and again with a merge high.
+define i16 @f5(<4 x i32> %v1, <4 x i32> %v2, <2 x i64> %v3) {
+; CHECK-LABEL: f5:
+; CHECK-NOT: vrepg
+; CHECK-NOT: vmr
+; CHECK-DAG: vaf [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG]], 2
+; CHECK-DAG: vlgvh {{%r[0-5]}}, %v28, 3
+; CHECK: br %r14
+  %add = add <4 x i32> %v1, %v2
+  %splat = shufflevector <2 x i64> %v3, <2 x i64> undef,
+                         <2 x i32> <i32 0, i32 0>
+  %splatcast = bitcast <2 x i64> %splat to <4 x i32>
+  %shuffle = shufflevector <4 x i32> %add, <4 x i32> %splatcast,
+                           <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+  %bitcast = bitcast <4 x i32> %shuffle to <8 x i16>
+  %elem1 = extractelement <8 x i16> %bitcast, i32 4
+  %elem2 = extractelement <8 x i16> %bitcast, i32 7
+  %res = add i16 %elem1, %elem2
+  ret i16 %res
+}
+
+; Test a case where an unpack high can be eliminated from the usual
+; load-extend sequence.
+define void @f6(<8 x i8> *%ptr1, i8 *%ptr2, i8 *%ptr3, i8 *%ptr4) {
+; CHECK-LABEL: f6:
+; CHECK: vlrepg [[REG:%v[0-9]+]], 0(%r2)
+; CHECK-NOT: vup
+; CHECK-DAG: vsteb [[REG]], 0(%r3), 1
+; CHECK-DAG: vsteb [[REG]], 0(%r4), 2
+; CHECK-DAG: vsteb [[REG]], 0(%r5), 7
+; CHECK: br %r14
+  %vec = load <8 x i8>, <8 x i8> *%ptr1
+  %ext = sext <8 x i8> %vec to <8 x i16>
+  %elem1 = extractelement <8 x i16> %ext, i32 1
+  %elem2 = extractelement <8 x i16> %ext, i32 2
+  %elem3 = extractelement <8 x i16> %ext, i32 7
+  %trunc1 = trunc i16 %elem1 to i8
+  %trunc2 = trunc i16 %elem2 to i8
+  %trunc3 = trunc i16 %elem3 to i8
+  store i8 %trunc1, i8 *%ptr2
+  store i8 %trunc2, i8 *%ptr3
+  store i8 %trunc3, i8 *%ptr4
+  ret void
+}
+
+; ...and again with a bitcast inbetween.
+define void @f7(<4 x i8> *%ptr1, i8 *%ptr2, i8 *%ptr3, i8 *%ptr4) {
+; CHECK-LABEL: f7:
+; CHECK: vlrepf [[REG:%v[0-9]+]], 0(%r2)
+; CHECK-NOT: vup
+; CHECK-DAG: vsteb [[REG]], 0(%r3), 0
+; CHECK-DAG: vsteb [[REG]], 0(%r4), 1
+; CHECK-DAG: vsteb [[REG]], 0(%r5), 3
+; CHECK: br %r14
+  %vec = load <4 x i8>, <4 x i8> *%ptr1
+  %ext = sext <4 x i8> %vec to <4 x i32>
+  %bitcast = bitcast <4 x i32> %ext to <8 x i16>
+  %elem1 = extractelement <8 x i16> %bitcast, i32 1
+  %elem2 = extractelement <8 x i16> %bitcast, i32 3
+  %elem3 = extractelement <8 x i16> %bitcast, i32 7
+  %trunc1 = trunc i16 %elem1 to i8
+  %trunc2 = trunc i16 %elem2 to i8
+  %trunc3 = trunc i16 %elem3 to i8
+  store i8 %trunc1, i8 *%ptr2
+  store i8 %trunc2, i8 *%ptr3
+  store i8 %trunc3, i8 *%ptr4
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/vec-combine-02.ll b/test/CodeGen/SystemZ/vec-combine-02.ll
new file mode 100644
index 000000000000..db0bf849017b
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-combine-02.ll
@@ -0,0 +1,433 @@
+; Test various representations of pack-like operations.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; One way of writing a <4 x i32> -> <8 x i16> pack.
+define <8 x i16> @f1(<4 x i32> %val0, <4 x i32> %val1) {
+; CHECK-LABEL: f1:
+; CHECK: vpkf %v24, %v24, %v26
+; CHECK: br %r14
+  %elem0 = extractelement <4 x i32> %val0, i32 0
+  %elem1 = extractelement <4 x i32> %val0, i32 1
+  %elem2 = extractelement <4 x i32> %val0, i32 2
+  %elem3 = extractelement <4 x i32> %val0, i32 3
+  %elem4 = extractelement <4 x i32> %val1, i32 0
+  %elem5 = extractelement <4 x i32> %val1, i32 1
+  %elem6 = extractelement <4 x i32> %val1, i32 2
+  %elem7 = extractelement <4 x i32> %val1, i32 3
+  %hboth0 = bitcast i32 %elem0 to <2 x i16>
+  %hboth1 = bitcast i32 %elem1 to <2 x i16>
+  %hboth2 = bitcast i32 %elem2 to <2 x i16>
+  %hboth3 = bitcast i32 %elem3 to <2 x i16>
+  %hboth4 = bitcast i32 %elem4 to <2 x i16>
+  %hboth5 = bitcast i32 %elem5 to <2 x i16>
+  %hboth6 = bitcast i32 %elem6 to <2 x i16>
+  %hboth7 = bitcast i32 %elem7 to <2 x i16>
+  %hlow0 = shufflevector <2 x i16> %hboth0, <2 x i16> %hboth1,
+                         <2 x i32> <i32 1, i32 3>
+  %hlow1 = shufflevector <2 x i16> %hboth2, <2 x i16> %hboth3,
+                         <2 x i32> <i32 1, i32 3>
+  %hlow2 = shufflevector <2 x i16> %hboth4, <2 x i16> %hboth5,
+                         <2 x i32> <i32 1, i32 3>
+  %hlow3 = shufflevector <2 x i16> %hboth6, <2 x i16> %hboth7,
+                         <2 x i32> <i32 1, i32 3>
+  %join0 = shufflevector <2 x i16> %hlow0, <2 x i16> %hlow1,
+                         <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %join1 = shufflevector <2 x i16> %hlow2, <2 x i16> %hlow3,
+                         <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %ret = shufflevector <4 x i16> %join0, <4 x i16> %join1,
+                       <8 x i32> <i32 0, i32 1, i32 2, i32 3,
+                                  i32 4, i32 5, i32 6, i32 7>
+  ret <8 x i16> %ret
+}
+
+; A different way of writing a <4 x i32> -> <8 x i16> pack.
+define <8 x i16> @f2(<4 x i32> %val0, <4 x i32> %val1) {
+; CHECK-LABEL: f2:
+; CHECK: vpkf %v24, %v24, %v26
+; CHECK: br %r14
+  %elem0 = extractelement <4 x i32> %val0, i32 0
+  %elem1 = extractelement <4 x i32> %val0, i32 1
+  %elem2 = extractelement <4 x i32> %val0, i32 2
+  %elem3 = extractelement <4 x i32> %val0, i32 3
+  %elem4 = extractelement <4 x i32> %val1, i32 0
+  %elem5 = extractelement <4 x i32> %val1, i32 1
+  %elem6 = extractelement <4 x i32> %val1, i32 2
+  %elem7 = extractelement <4 x i32> %val1, i32 3
+  %wvec0 = insertelement <4 x i32> undef, i32 %elem0, i32 0
+  %wvec1 = insertelement <4 x i32> undef, i32 %elem1, i32 0
+  %wvec2 = insertelement <4 x i32> undef, i32 %elem2, i32 0
+  %wvec3 = insertelement <4 x i32> undef, i32 %elem3, i32 0
+  %wvec4 = insertelement <4 x i32> undef, i32 %elem4, i32 0
+  %wvec5 = insertelement <4 x i32> undef, i32 %elem5, i32 0
+  %wvec6 = insertelement <4 x i32> undef, i32 %elem6, i32 0
+  %wvec7 = insertelement <4 x i32> undef, i32 %elem7, i32 0
+  %hvec0 = bitcast <4 x i32> %wvec0 to <8 x i16>
+  %hvec1 = bitcast <4 x i32> %wvec1 to <8 x i16>
+  %hvec2 = bitcast <4 x i32> %wvec2 to <8 x i16>
+  %hvec3 = bitcast <4 x i32> %wvec3 to <8 x i16>
+  %hvec4 = bitcast <4 x i32> %wvec4 to <8 x i16>
+  %hvec5 = bitcast <4 x i32> %wvec5 to <8 x i16>
+  %hvec6 = bitcast <4 x i32> %wvec6 to <8 x i16>
+  %hvec7 = bitcast <4 x i32> %wvec7 to <8 x i16>
+  %hlow0 = shufflevector <8 x i16> %hvec0, <8 x i16> %hvec1,
+                         <8 x i32> <i32 1, i32 9, i32 undef, i32 undef,
+                                    i32 undef, i32 undef, i32 undef, i32 undef>
+  %hlow1 = shufflevector <8 x i16> %hvec2, <8 x i16> %hvec3,
+                         <8 x i32> <i32 1, i32 9, i32 undef, i32 undef,
+                                    i32 undef, i32 undef, i32 undef, i32 undef>
+  %hlow2 = shufflevector <8 x i16> %hvec4, <8 x i16> %hvec5,
+                         <8 x i32> <i32 1, i32 9, i32 undef, i32 undef,
+                                    i32 undef, i32 undef, i32 undef, i32 undef>
+  %hlow3 = shufflevector <8 x i16> %hvec6, <8 x i16> %hvec7,
+                         <8 x i32> <i32 1, i32 9, i32 undef, i32 undef,
+                                    i32 undef, i32 undef, i32 undef, i32 undef>
+  %join0 = shufflevector <8 x i16> %hlow0, <8 x i16> %hlow1,
+                         <8 x i32> <i32 0, i32 1, i32 8, i32 9,
+                                    i32 undef, i32 undef, i32 undef, i32 undef>
+  %join1 = shufflevector <8 x i16> %hlow2, <8 x i16> %hlow3,
+                         <8 x i32> <i32 0, i32 1, i32 8, i32 9,
+                                    i32 undef, i32 undef, i32 undef, i32 undef>
+  %ret = shufflevector <8 x i16> %join0, <8 x i16> %join1,
+                       <8 x i32> <i32 0, i32 1, i32 2, i32 3,
+                                  i32 8, i32 9, i32 10, i32 11>
+  ret <8 x i16> %ret
+}
+
+; A direct pack operation.
+define <8 x i16> @f3(<4 x i32> %val0, <4 x i32> %val1) {
+; CHECK-LABEL: f3:
+; CHECK: vpkf %v24, %v24, %v26
+; CHECK: br %r14
+  %bitcast0 = bitcast <4 x i32> %val0 to <8 x i16>
+  %bitcast1 = bitcast <4 x i32> %val1 to <8 x i16>
+  %ret = shufflevector <8 x i16> %bitcast0, <8 x i16> %bitcast1,
+                       <8 x i32> <i32 1, i32 3, i32 5, i32 7,
+                                  i32 9, i32 11, i32 13, i32 15>
+  ret <8 x i16> %ret
+}
+
+; One way of writing a <4 x i32> -> <16 x i8> pack.  It doesn't matter
+; whether the first pack is VPKF or VPKH since the even bytes of the
+; result are discarded.
+define <16 x i8> @f4(<4 x i32> %val0, <4 x i32> %val1,
+                     <4 x i32> %val2, <4 x i32> %val3) {
+; CHECK-LABEL: f4:
+; CHECK-DAG: vpk{{[hf]}} [[REG1:%v[0-9]+]], %v24, %v26
+; CHECK-DAG: vpk{{[hf]}} [[REG2:%v[0-9]+]], %v28, %v30
+; CHECK: vpkh %v24, [[REG1]], [[REG2]]
+; CHECK: br %r14
+  %bitcast0 = bitcast <4 x i32> %val0 to <8 x i16>
+  %bitcast1 = bitcast <4 x i32> %val1 to <8 x i16>
+  %bitcast2 = bitcast <4 x i32> %val2 to <8 x i16>
+  %bitcast3 = bitcast <4 x i32> %val3 to <8 x i16>
+  %join0 = shufflevector <8 x i16> %bitcast0, <8 x i16> %bitcast1,
+                         <8 x i32> <i32 1, i32 3, i32 5, i32 7,
+                                    i32 9, i32 11, i32 13, i32 15>
+  %join1 = shufflevector <8 x i16> %bitcast2, <8 x i16> %bitcast3,
+                         <8 x i32> <i32 1, i32 3, i32 5, i32 7,
+                                    i32 9, i32 11, i32 13, i32 15>
+  %bitcast4 = bitcast <8 x i16> %join0 to <16 x i8>
+  %bitcast5 = bitcast <8 x i16> %join1 to <16 x i8>
+  %ret = shufflevector <16 x i8> %bitcast4, <16 x i8> %bitcast5,
+                       <16 x i32> <i32 1, i32 3, i32 5, i32 7,
+                                   i32 9, i32 11, i32 13, i32 15,
+                                   i32 17, i32 19, i32 21, i32 23,
+                                   i32 25, i32 27, i32 29, i32 31>
+  ret <16 x i8> %ret
+}
+
+; Check the same operation, but with elements being extracted from the result.
+define void @f5(<4 x i32> %val0, <4 x i32> %val1,
+                <4 x i32> %val2, <4 x i32> %val3,
+                i8 *%base) {
+; CHECK-LABEL: f5:
+; CHECK-DAG: vsteb %v24, 0(%r2), 11
+; CHECK-DAG: vsteb %v26, 1(%r2), 15
+; CHECK-DAG: vsteb %v28, 2(%r2), 3
+; CHECK-DAG: vsteb %v30, 3(%r2), 7
+; CHECK: br %r14
+  %bitcast0 = bitcast <4 x i32> %val0 to <8 x i16>
+  %bitcast1 = bitcast <4 x i32> %val1 to <8 x i16>
+  %bitcast2 = bitcast <4 x i32> %val2 to <8 x i16>
+  %bitcast3 = bitcast <4 x i32> %val3 to <8 x i16>
+  %join0 = shufflevector <8 x i16> %bitcast0, <8 x i16> %bitcast1,
+                         <8 x i32> <i32 1, i32 3, i32 5, i32 7,
+                                    i32 9, i32 11, i32 13, i32 15>
+  %join1 = shufflevector <8 x i16> %bitcast2, <8 x i16> %bitcast3,
+                         <8 x i32> <i32 1, i32 3, i32 5, i32 7,
+                                    i32 9, i32 11, i32 13, i32 15>
+  %bitcast4 = bitcast <8 x i16> %join0 to <16 x i8>
+  %bitcast5 = bitcast <8 x i16> %join1 to <16 x i8>
+  %vec = shufflevector <16 x i8> %bitcast4, <16 x i8> %bitcast5,
+                       <16 x i32> <i32 1, i32 3, i32 5, i32 7,
+                                   i32 9, i32 11, i32 13, i32 15,
+                                   i32 17, i32 19, i32 21, i32 23,
+                                   i32 25, i32 27, i32 29, i32 31>
+
+  %ptr0 = getelementptr i8, i8 *%base, i64 0
+  %ptr1 = getelementptr i8, i8 *%base, i64 1
+  %ptr2 = getelementptr i8, i8 *%base, i64 2
+  %ptr3 = getelementptr i8, i8 *%base, i64 3
+
+  %byte0 = extractelement <16 x i8> %vec, i32 2
+  %byte1 = extractelement <16 x i8> %vec, i32 7
+  %byte2 = extractelement <16 x i8> %vec, i32 8
+  %byte3 = extractelement <16 x i8> %vec, i32 13
+
+  store i8 %byte0, i8 *%ptr0
+  store i8 %byte1, i8 *%ptr1
+  store i8 %byte2, i8 *%ptr2
+  store i8 %byte3, i8 *%ptr3
+
+  ret void
+}
+
+; A different way of writing a <4 x i32> -> <16 x i8> pack.
+define <16 x i8> @f6(<4 x i32> %val0, <4 x i32> %val1,
+                     <4 x i32> %val2, <4 x i32> %val3) {
+; CHECK-LABEL: f6:
+; CHECK-DAG: vpk{{[hf]}} [[REG1:%v[0-9]+]], %v24, %v26
+; CHECK-DAG: vpk{{[hf]}} [[REG2:%v[0-9]+]], %v28, %v30
+; CHECK: vpkh %v24, [[REG1]], [[REG2]]
+; CHECK: br %r14
+  %elem0 = extractelement <4 x i32> %val0, i32 0
+  %elem1 = extractelement <4 x i32> %val0, i32 1
+  %elem2 = extractelement <4 x i32> %val0, i32 2
+  %elem3 = extractelement <4 x i32> %val0, i32 3
+  %elem4 = extractelement <4 x i32> %val1, i32 0
+  %elem5 = extractelement <4 x i32> %val1, i32 1
+  %elem6 = extractelement <4 x i32> %val1, i32 2
+  %elem7 = extractelement <4 x i32> %val1, i32 3
+  %elem8 = extractelement <4 x i32> %val2, i32 0
+  %elem9 = extractelement <4 x i32> %val2, i32 1
+  %elem10 = extractelement <4 x i32> %val2, i32 2
+  %elem11 = extractelement <4 x i32> %val2, i32 3
+  %elem12 = extractelement <4 x i32> %val3, i32 0
+  %elem13 = extractelement <4 x i32> %val3, i32 1
+  %elem14 = extractelement <4 x i32> %val3, i32 2
+  %elem15 = extractelement <4 x i32> %val3, i32 3
+  %bitcast0 = bitcast i32 %elem0 to <2 x i16>
+  %bitcast1 = bitcast i32 %elem1 to <2 x i16>
+  %bitcast2 = bitcast i32 %elem2 to <2 x i16>
+  %bitcast3 = bitcast i32 %elem3 to <2 x i16>
+  %bitcast4 = bitcast i32 %elem4 to <2 x i16>
+  %bitcast5 = bitcast i32 %elem5 to <2 x i16>
+  %bitcast6 = bitcast i32 %elem6 to <2 x i16>
+  %bitcast7 = bitcast i32 %elem7 to <2 x i16>
+  %bitcast8 = bitcast i32 %elem8 to <2 x i16>
+  %bitcast9 = bitcast i32 %elem9 to <2 x i16>
+  %bitcast10 = bitcast i32 %elem10 to <2 x i16>
+  %bitcast11 = bitcast i32 %elem11 to <2 x i16>
+  %bitcast12 = bitcast i32 %elem12 to <2 x i16>
+  %bitcast13 = bitcast i32 %elem13 to <2 x i16>
+  %bitcast14 = bitcast i32 %elem14 to <2 x i16>
+  %bitcast15 = bitcast i32 %elem15 to <2 x i16>
+  %low0 = shufflevector <2 x i16> %bitcast0, <2 x i16> %bitcast1,
+                        <2 x i32> <i32 1, i32 3>
+  %low1 = shufflevector <2 x i16> %bitcast2, <2 x i16> %bitcast3,
+                        <2 x i32> <i32 1, i32 3>
+  %low2 = shufflevector <2 x i16> %bitcast4, <2 x i16> %bitcast5,
+                        <2 x i32> <i32 1, i32 3>
+  %low3 = shufflevector <2 x i16> %bitcast6, <2 x i16> %bitcast7,
+                        <2 x i32> <i32 1, i32 3>
+  %low4 = shufflevector <2 x i16> %bitcast8, <2 x i16> %bitcast9,
+                        <2 x i32> <i32 1, i32 3>
+  %low5 = shufflevector <2 x i16> %bitcast10, <2 x i16> %bitcast11,
+                        <2 x i32> <i32 1, i32 3>
+  %low6 = shufflevector <2 x i16> %bitcast12, <2 x i16> %bitcast13,
+                        <2 x i32> <i32 1, i32 3>
+  %low7 = shufflevector <2 x i16> %bitcast14, <2 x i16> %bitcast15,
+                        <2 x i32> <i32 1, i32 3>
+  %bytes0 = bitcast <2 x i16> %low0 to <4 x i8>
+  %bytes1 = bitcast <2 x i16> %low1 to <4 x i8>
+  %bytes2 = bitcast <2 x i16> %low2 to <4 x i8>
+  %bytes3 = bitcast <2 x i16> %low3 to <4 x i8>
+  %bytes4 = bitcast <2 x i16> %low4 to <4 x i8>
+  %bytes5 = bitcast <2 x i16> %low5 to <4 x i8>
+  %bytes6 = bitcast <2 x i16> %low6 to <4 x i8>
+  %bytes7 = bitcast <2 x i16> %low7 to <4 x i8>
+  %blow0 = shufflevector <4 x i8> %bytes0, <4 x i8> %bytes1,
+                         <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %blow1 = shufflevector <4 x i8> %bytes2, <4 x i8> %bytes3,
+                         <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %blow2 = shufflevector <4 x i8> %bytes4, <4 x i8> %bytes5,
+                         <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %blow3 = shufflevector <4 x i8> %bytes6, <4 x i8> %bytes7,
+                         <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %join0 = shufflevector <4 x i8> %blow0, <4 x i8> %blow1,
+                         <8 x i32> <i32 0, i32 1, i32 2, i32 3,
+                                    i32 4, i32 5, i32 6, i32 7>
+  %join1 = shufflevector <4 x i8> %blow2, <4 x i8> %blow3,
+                         <8 x i32> <i32 0, i32 1, i32 2, i32 3,
+                                    i32 4, i32 5, i32 6, i32 7>
+  %ret = shufflevector <8 x i8> %join0, <8 x i8> %join1,
+                       <16 x i32> <i32 0, i32 1, i32 2, i32 3,
+                                   i32 4, i32 5, i32 6, i32 7,
+                                   i32 8, i32 9, i32 10, i32 11,
+                                   i32 12, i32 13, i32 14, i32 15>
+  ret <16 x i8> %ret
+}
+
+; One way of writing a <2 x i64> -> <16 x i8> pack.
+define <16 x i8> @f7(<2 x i64> %val0, <2 x i64> %val1,
+                     <2 x i64> %val2, <2 x i64> %val3,
+                     <2 x i64> %val4, <2 x i64> %val5,
+                     <2 x i64> %val6, <2 x i64> %val7) {
+; CHECK-LABEL: f7:
+; CHECK-DAG: vpk{{[hfg]}} [[REG1:%v[0-9]+]], %v24, %v26
+; CHECK-DAG: vpk{{[hfg]}} [[REG2:%v[0-9]+]], %v28, %v30
+; CHECK-DAG: vpk{{[hfg]}} [[REG3:%v[0-9]+]], %v25, %v27
+; CHECK-DAG: vpk{{[hfg]}} [[REG4:%v[0-9]+]], %v29, %v31
+; CHECK-DAG: vpk{{[hf]}} [[REG5:%v[0-9]+]], [[REG1]], [[REG2]]
+; CHECK-DAG: vpk{{[hf]}} [[REG6:%v[0-9]+]], [[REG3]], [[REG4]]
+; CHECK: vpkh %v24, [[REG5]], [[REG6]]
+; CHECK: br %r14
+  %elem0 = extractelement <2 x i64> %val0, i32 0
+  %elem1 = extractelement <2 x i64> %val0, i32 1
+  %elem2 = extractelement <2 x i64> %val1, i32 0
+  %elem3 = extractelement <2 x i64> %val1, i32 1
+  %elem4 = extractelement <2 x i64> %val2, i32 0
+  %elem5 = extractelement <2 x i64> %val2, i32 1
+  %elem6 = extractelement <2 x i64> %val3, i32 0
+  %elem7 = extractelement <2 x i64> %val3, i32 1
+  %elem8 = extractelement <2 x i64> %val4, i32 0
+  %elem9 = extractelement <2 x i64> %val4, i32 1
+  %elem10 = extractelement <2 x i64> %val5, i32 0
+  %elem11 = extractelement <2 x i64> %val5, i32 1
+  %elem12 = extractelement <2 x i64> %val6, i32 0
+  %elem13 = extractelement <2 x i64> %val6, i32 1
+  %elem14 = extractelement <2 x i64> %val7, i32 0
+  %elem15 = extractelement <2 x i64> %val7, i32 1
+  %bitcast0 = bitcast i64 %elem0 to <2 x i32>
+  %bitcast1 = bitcast i64 %elem1 to <2 x i32>
+  %bitcast2 = bitcast i64 %elem2 to <2 x i32>
+  %bitcast3 = bitcast i64 %elem3 to <2 x i32>
+  %bitcast4 = bitcast i64 %elem4 to <2 x i32>
+  %bitcast5 = bitcast i64 %elem5 to <2 x i32>
+  %bitcast6 = bitcast i64 %elem6 to <2 x i32>
+  %bitcast7 = bitcast i64 %elem7 to <2 x i32>
+  %bitcast8 = bitcast i64 %elem8 to <2 x i32>
+  %bitcast9 = bitcast i64 %elem9 to <2 x i32>
+  %bitcast10 = bitcast i64 %elem10 to <2 x i32>
+  %bitcast11 = bitcast i64 %elem11 to <2 x i32>
+  %bitcast12 = bitcast i64 %elem12 to <2 x i32>
+  %bitcast13 = bitcast i64 %elem13 to <2 x i32>
+  %bitcast14 = bitcast i64 %elem14 to <2 x i32>
+  %bitcast15 = bitcast i64 %elem15 to <2 x i32>
+  %low0 = shufflevector <2 x i32> %bitcast0, <2 x i32> %bitcast1,
+                        <2 x i32> <i32 1, i32 3>
+  %low1 = shufflevector <2 x i32> %bitcast2, <2 x i32> %bitcast3,
+                        <2 x i32> <i32 1, i32 3>
+  %low2 = shufflevector <2 x i32> %bitcast4, <2 x i32> %bitcast5,
+                        <2 x i32> <i32 1, i32 3>
+  %low3 = shufflevector <2 x i32> %bitcast6, <2 x i32> %bitcast7,
+                        <2 x i32> <i32 1, i32 3>
+  %low4 = shufflevector <2 x i32> %bitcast8, <2 x i32> %bitcast9,
+                        <2 x i32> <i32 1, i32 3>
+  %low5 = shufflevector <2 x i32> %bitcast10, <2 x i32> %bitcast11,
+                        <2 x i32> <i32 1, i32 3>
+  %low6 = shufflevector <2 x i32> %bitcast12, <2 x i32> %bitcast13,
+                        <2 x i32> <i32 1, i32 3>
+  %low7 = shufflevector <2 x i32> %bitcast14, <2 x i32> %bitcast15,
+                        <2 x i32> <i32 1, i32 3>
+  %half0 = bitcast <2 x i32> %low0 to <4 x i16>
+  %half1 = bitcast <2 x i32> %low1 to <4 x i16>
+  %half2 = bitcast <2 x i32> %low2 to <4 x i16>
+  %half3 = bitcast <2 x i32> %low3 to <4 x i16>
+  %half4 = bitcast <2 x i32> %low4 to <4 x i16>
+  %half5 = bitcast <2 x i32> %low5 to <4 x i16>
+  %half6 = bitcast <2 x i32> %low6 to <4 x i16>
+  %half7 = bitcast <2 x i32> %low7 to <4 x i16>
+  %hlow0 = shufflevector <4 x i16> %half0, <4 x i16> %half1,
+                         <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %hlow1 = shufflevector <4 x i16> %half2, <4 x i16> %half3,
+                         <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %hlow2 = shufflevector <4 x i16> %half4, <4 x i16> %half5,
+                         <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %hlow3 = shufflevector <4 x i16> %half6, <4 x i16> %half7,
+                         <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %bytes0 = bitcast <4 x i16> %hlow0 to <8 x i8>
+  %bytes1 = bitcast <4 x i16> %hlow1 to <8 x i8>
+  %bytes2 = bitcast <4 x i16> %hlow2 to <8 x i8>
+  %bytes3 = bitcast <4 x i16> %hlow3 to <8 x i8>
+  %join0 = shufflevector <8 x i8> %bytes0, <8 x i8> %bytes1,
+                         <8 x i32> <i32 1, i32 3, i32 5, i32 7,
+                                    i32 9, i32 11, i32 13, i32 15>
+  %join1 = shufflevector <8 x i8> %bytes2, <8 x i8> %bytes3,
+                         <8 x i32> <i32 1, i32 3, i32 5, i32 7,
+                                    i32 9, i32 11, i32 13, i32 15>
+  %ret = shufflevector <8 x i8> %join0, <8 x i8> %join1,
+                       <16 x i32> <i32 0, i32 1, i32 2, i32 3,
+                                   i32 4, i32 5, i32 6, i32 7,
+                                   i32 8, i32 9, i32 10, i32 11,
+                                   i32 12, i32 13, i32 14, i32 15>
+  ret <16 x i8> %ret
+}
+
+; Test a <2 x i64> -> <4 x f32> pack in which only individual elements are
+; needed.
+define float @f8(i64 %scalar0, i64 %scalar1, i64 %scalar2, i64 %scalar3) {
+; CHECK-LABEL: f8:
+; CHECK-NOT: vperm
+; CHECK-NOT: vpk
+; CHECK-NOT: vmrh
+; CHECK: aebr {{%f[0-7]}},
+; CHECK: aebr {{%f[0-7]}},
+; CHECK: meebr %f0,
+; CHECK: br %r14
+  %vec0 = insertelement <2 x i64> undef, i64 %scalar0, i32 0
+  %vec1 = insertelement <2 x i64> undef, i64 %scalar1, i32 0
+  %vec2 = insertelement <2 x i64> undef, i64 %scalar2, i32 0
+  %vec3 = insertelement <2 x i64> undef, i64 %scalar3, i32 0
+  %join0 = shufflevector <2 x i64> %vec0, <2 x i64> %vec1,
+                         <2 x i32> <i32 0, i32 2>
+  %join1 = shufflevector <2 x i64> %vec2, <2 x i64> %vec3,
+                         <2 x i32> <i32 0, i32 2>
+  %bitcast0 = bitcast <2 x i64> %join0 to <4 x float>
+  %bitcast1 = bitcast <2 x i64> %join1 to <4 x float>
+  %pack = shufflevector <4 x float> %bitcast0, <4 x float> %bitcast1,
+                        <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %elt0 = extractelement <4 x float> %pack, i32 0
+  %elt1 = extractelement <4 x float> %pack, i32 1
+  %elt2 = extractelement <4 x float> %pack, i32 2
+  %elt3 = extractelement <4 x float> %pack, i32 3
+  %add0 = fadd float %elt0, %elt2
+  %add1 = fadd float %elt1, %elt3
+  %ret = fmul float %add0, %add1
+  ret float %ret
+}
+
+; Test a <2 x f64> -> <4 x i32> pack in which only individual elements are
+; needed.
+define i32 @f9(double %scalar0, double %scalar1, double %scalar2,
+               double %scalar3) {
+; CHECK-LABEL: f9:
+; CHECK-NOT: vperm
+; CHECK-NOT: vpk
+; CHECK-NOT: vmrh
+; CHECK: ar {{%r[0-5]}},
+; CHECK: ar {{%r[0-5]}},
+; CHECK: or %r2,
+; CHECK: br %r14
+  %vec0 = insertelement <2 x double> undef, double %scalar0, i32 0
+  %vec1 = insertelement <2 x double> undef, double %scalar1, i32 0
+  %vec2 = insertelement <2 x double> undef, double %scalar2, i32 0
+  %vec3 = insertelement <2 x double> undef, double %scalar3, i32 0
+  %join0 = shufflevector <2 x double> %vec0, <2 x double> %vec1,
+                         <2 x i32> <i32 0, i32 2>
+  %join1 = shufflevector <2 x double> %vec2, <2 x double> %vec3,
+                         <2 x i32> <i32 0, i32 2>
+  %bitcast0 = bitcast <2 x double> %join0 to <4 x i32>
+  %bitcast1 = bitcast <2 x double> %join1 to <4 x i32>
+  %pack = shufflevector <4 x i32> %bitcast0, <4 x i32> %bitcast1,
+                        <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %elt0 = extractelement <4 x i32> %pack, i32 0
+  %elt1 = extractelement <4 x i32> %pack, i32 1
+  %elt2 = extractelement <4 x i32> %pack, i32 2
+  %elt3 = extractelement <4 x i32> %pack, i32 3
+  %add0 = add i32 %elt0, %elt2
+  %add1 = add i32 %elt1, %elt3
+  %ret = or i32 %add0, %add1
+  ret i32 %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-const-01.ll b/test/CodeGen/SystemZ/vec-const-01.ll
new file mode 100644
index 000000000000..4cdcbf7c2dcb
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-01.ll
@@ -0,0 +1,103 @@
+; Test vector byte masks, v16i8 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test an all-zeros vector.
+define <16 x i8> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vgbm %v24, 0
+; CHECK: br %r14
+  ret <16 x i8> zeroinitializer
+}
+
+; Test an all-ones vector.
+define <16 x i8> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vgbm %v24, 65535
+; CHECK: br %r14
+  ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1,
+                 i8 -1, i8 -1, i8 -1, i8 -1,
+                 i8 -1, i8 -1, i8 -1, i8 -1,
+                 i8 -1, i8 -1, i8 -1, i8 -1>
+}
+
+; Test a mixed vector (mask 0x8c75).
+define <16 x i8> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vgbm %v24, 35957
+; CHECK: br %r14
+  ret <16 x i8> <i8 -1, i8 0, i8 0, i8 0,
+                 i8 -1, i8 -1, i8 0, i8 0,
+                 i8 0, i8 -1, i8 -1, i8 -1,
+                 i8 0, i8 -1, i8 0, i8 -1>
+}
+
+; Test that undefs are treated as zero.
+define <16 x i8> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vgbm %v24, 35957
+; CHECK: br %r14
+  ret <16 x i8> <i8 -1, i8 undef, i8 undef, i8 undef,
+                 i8 -1, i8 -1, i8 undef, i8 undef,
+                 i8 undef, i8 -1, i8 -1, i8 -1,
+                 i8 undef, i8 -1, i8 undef, i8 -1>
+}
+
+; Test that we don't use VGBM if one of the bytes is not 0 or 0xff.
+define <16 x i8> @f5() {
+; CHECK-LABEL: f5:
+; CHECK-NOT: vgbm
+; CHECK: br %r14
+  ret <16 x i8> <i8 -1, i8 0, i8 0, i8 0,
+                 i8 -1, i8 -1, i8 0, i8 1,
+                 i8 0, i8 -1, i8 -1, i8 -1,
+                 i8 0, i8 -1, i8 0, i8 -1>
+}
+
+; Test an all-zeros v2i8 that gets promoted to v16i8.
+define <2 x i8> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vgbm %v24, 0
+; CHECK: br %r14
+  ret <2 x i8> zeroinitializer
+}
+
+; Test a mixed v2i8 that gets promoted to v16i8 (mask 0x8000).
+define <2 x i8> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vgbm %v24, 32768
+; CHECK: br %r14
+  ret <2 x i8> <i8 255, i8 0>
+}
+
+; Test an all-zeros v4i8 that gets promoted to v16i8.
+define <4 x i8> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vgbm %v24, 0
+; CHECK: br %r14
+  ret <4 x i8> zeroinitializer
+}
+
+; Test a mixed v4i8 that gets promoted to v16i8 (mask 0x9000).
+define <4 x i8> @f9() {
+; CHECK-LABEL: f9:
+; CHECK: vgbm %v24, 36864
+; CHECK: br %r14
+  ret <4 x i8> <i8 255, i8 0, i8 0, i8 255>
+}
+
+; Test an all-zeros v8i8 that gets promoted to v16i8.
+define <8 x i8> @f10() {
+; CHECK-LABEL: f10:
+; CHECK: vgbm %v24, 0
+; CHECK: br %r14
+  ret <8 x i8> zeroinitializer
+}
+
+; Test a mixed v8i8 that gets promoted to v16i8 (mask 0xE500).
+define <8 x i8> @f11() {
+; CHECK-LABEL: f11:
+; CHECK: vgbm %v24, 58624
+; CHECK: br %r14
+  ret <8 x i8> <i8 255, i8 255, i8 255, i8 0, i8 0, i8 255, i8 0, i8 255>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-02.ll b/test/CodeGen/SystemZ/vec-const-02.ll
new file mode 100644
index 000000000000..73a89d4a841b
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-02.ll
@@ -0,0 +1,79 @@
+; Test vector byte masks, v8i16 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test an all-zeros vector.
+define <8 x i16> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vgbm %v24, 0
+; CHECK: br %r14
+  ret <8 x i16> zeroinitializer
+}
+
+; Test an all-ones vector.
+define <8 x i16> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vgbm %v24, 65535
+; CHECK: br %r14
+  ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1,
+                 i16 -1, i16 -1, i16 -1, i16 -1>
+}
+
+; Test a mixed vector (mask 0x8c76).
+define <8 x i16> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vgbm %v24, 35958
+; CHECK: br %r14
+  ret <8 x i16> <i16 65280, i16 0, i16 65535, i16 0,
+                 i16 255, i16 65535, i16 255, i16 65280>
+}
+
+; Test that undefs are treated as zero.
+define <8 x i16> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vgbm %v24, 35958
+; CHECK: br %r14
+  ret <8 x i16> <i16 65280, i16 undef, i16 65535, i16 undef,
+                 i16 255, i16 65535, i16 255, i16 65280>
+}
+
+; Test that we don't use VGBM if one of the bytes is not 0 or 0xff.
+define <8 x i16> @f5() {
+; CHECK-LABEL: f5:
+; CHECK-NOT: vgbm
+; CHECK: br %r14
+  ret <8 x i16> <i16 65280, i16 0, i16 65535, i16 0,
+                 i16 255, i16 65535, i16 256, i16 65280>
+}
+
+; Test an all-zeros v2i16 that gets promoted to v8i16.
+define <2 x i16> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vgbm %v24, 0
+; CHECK: br %r14
+  ret <2 x i16> zeroinitializer
+}
+
+; Test a mixed v2i16 that gets promoted to v8i16 (mask 0xc000).
+define <2 x i16> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vgbm %v24, 49152
+; CHECK: br %r14
+  ret <2 x i16> <i16 65535, i16 0>
+}
+
+; Test an all-zeros v4i16 that gets promoted to v8i16.
+define <4 x i16> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vgbm %v24, 0
+; CHECK: br %r14
+  ret <4 x i16> zeroinitializer
+}
+
+; Test a mixed v4i16 that gets promoted to v8i16 (mask 0x7200).
+define <4 x i16> @f9() {
+; CHECK-LABEL: f9:
+; CHECK: vgbm %v24, 29184
+; CHECK: br %r14
+  ret <4 x i16> <i16 255, i16 65535, i16 0, i16 65280>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-03.ll b/test/CodeGen/SystemZ/vec-const-03.ll
new file mode 100644
index 000000000000..adc1105229e6
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-03.ll
@@ -0,0 +1,59 @@
+; Test vector byte masks, v4i32 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test an all-zeros vector.
+define <4 x i32> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vgbm %v24, 0
+; CHECK: br %r14
+  ret <4 x i32> zeroinitializer
+}
+
+; Test an all-ones vector.
+define <4 x i32> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vgbm %v24, 65535
+; CHECK: br %r14
+  ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
+}
+
+; Test a mixed vector (mask 0x8c76).
+define <4 x i32> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vgbm %v24, 35958
+; CHECK: br %r14
+  ret <4 x i32> <i32 4278190080, i32 4294901760, i32 16777215, i32 16776960>
+}
+
+; Test that undefs are treated as zero (mask 0x8076).
+define <4 x i32> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vgbm %v24, 32886
+; CHECK: br %r14
+  ret <4 x i32> <i32 4278190080, i32 undef, i32 16777215, i32 16776960>
+}
+
+; Test that we don't use VGBM if one of the bytes is not 0 or 0xff.
+define <4 x i32> @f5() {
+; CHECK-LABEL: f5:
+; CHECK-NOT: vgbm
+; CHECK: br %r14
+  ret <4 x i32> <i32 4278190080, i32 1, i32 16777215, i32 16776960>
+}
+
+; Test an all-zeros v2i32 that gets promoted to v4i32.
+define <2 x i32> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vgbm %v24, 0
+; CHECK: br %r14
+  ret <2 x i32> zeroinitializer
+}
+
+; Test a mixed v2i32 that gets promoted to v4i32 (mask 0xae00).
+define <2 x i32> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vgbm %v24, 44544
+; CHECK: br %r14
+  ret <2 x i32> <i32 4278255360, i32 -256>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-04.ll b/test/CodeGen/SystemZ/vec-const-04.ll
new file mode 100644
index 000000000000..1c2fb414d25f
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-04.ll
@@ -0,0 +1,43 @@
+; Test vector byte masks, v2i64 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test an all-zeros vector.
+define <2 x i64> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vgbm %v24, 0
+; CHECK: br %r14
+  ret <2 x i64> zeroinitializer
+}
+
+; Test an all-ones vector.
+define <2 x i64> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vgbm %v24, 65535
+; CHECK: br %r14
+  ret <2 x i64> <i64 -1, i64 -1>
+}
+
+; Test a mixed vector (mask 0x8c76).
+define <2 x i64> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vgbm %v24, 35958
+; CHECK: br %r14
+  ret <2 x i64> <i64 18374686483966525440, i64 72057589759737600>
+}
+
+; Test that undefs are treated as zero (mask 0x8c00).
+define <2 x i64> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vgbm %v24, 35840
+; CHECK: br %r14
+  ret <2 x i64> <i64 18374686483966525440, i64 undef>
+}
+
+; Test that we don't use VGBM if one of the bytes is not 0 or 0xff.
+define <2 x i64> @f5() {
+; CHECK-LABEL: f5:
+; CHECK-NOT: vgbm
+; CHECK: br %r14
+  ret <2 x i64> <i64 18374686483966525441, i64 72057589759737600>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-05.ll b/test/CodeGen/SystemZ/vec-const-05.ll
new file mode 100644
index 000000000000..55f3cdd59027
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-05.ll
@@ -0,0 +1,63 @@
+; Test vector byte masks, v4f32 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test an all-zeros vector.
+define <4 x float> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vgbm %v24, 0
+; CHECK: br %r14
+  ret <4 x float> zeroinitializer
+}
+
+; Test an all-ones vector.
+define <4 x float> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vgbm %v24, 65535
+; CHECK: br %r14
+  ret <4 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000,
+                   float 0xffffffffe0000000, float 0xffffffffe0000000>
+}
+
+; Test a mixed vector (mask 0xc731).
+define <4 x float> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vgbm %v24, 50993
+; CHECK: br %r14
+  ret <4 x float> <float 0xffffe00000000000, float 0x381fffffe0000000,
+                   float 0x379fffe000000000, float 0x371fe00000000000>
+}
+
+; Test that undefs are treated as zero (mask 0xc031).
+define <4 x float> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vgbm %v24, 49201
+; CHECK: br %r14
+  ret <4 x float> <float 0xffffe00000000000, float undef,
+                   float 0x379fffe000000000, float 0x371fe00000000000>
+}
+
+; Test that we don't use VGBM if one of the bytes is not 0 or 0xff.
+define <4 x float> @f5() {
+; CHECK-LABEL: f5:
+; CHECK-NOT: vgbm
+; CHECK: br %r14
+  ret <4 x float> <float 0xffffe00000000000, float 0x381fffffc0000000,
+                   float 0x379fffe000000000, float 0x371fe00000000000>
+}
+
+; Test an all-zeros v2f32 that gets promoted to v4f32.
+define <2 x float> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vgbm %v24, 0
+; CHECK: br %r14
+  ret <2 x float> zeroinitializer
+}
+
+; Test a mixed v2f32 that gets promoted to v4f32 (mask 0xc700).
+define <2 x float> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vgbm %v24, 50944
+; CHECK: br %r14
+  ret <2 x float> <float 0xffffe00000000000, float 0x381fffffe0000000>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-06.ll b/test/CodeGen/SystemZ/vec-const-06.ll
new file mode 100644
index 000000000000..be53a0581ec2
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-06.ll
@@ -0,0 +1,43 @@
+; Test vector byte masks, v2f64 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test an all-zeros vector.
+define <2 x double> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vgbm %v24, 0
+; CHECK: br %r14
+  ret <2 x double> zeroinitializer
+}
+
+; Test an all-ones vector.
+define <2 x double> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vgbm %v24, 65535
+; CHECK: br %r14
+  ret <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff>
+}
+
+; Test a mixed vector (mask 0x8c76).
+define <2 x double> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vgbm %v24, 35958
+; CHECK: br %r14
+  ret <2 x double> <double 0xff000000ffff0000, double 0x00ffffff00ffff00>
+}
+
+; Test that undefs are treated as zero (mask 0x8c00).
+define <2 x double> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vgbm %v24, 35840
+; CHECK: br %r14
+  ret <2 x double> <double 0xff000000ffff0000, double undef>
+}
+
+; Test that we don't use VGBM if one of the bytes is not 0 or 0xff.
+define <2 x double> @f5() {
+; CHECK-LABEL: f5:
+; CHECK-NOT: vgbm
+; CHECK: br %r14
+  ret <2 x double> <double 0xfe000000ffff0000, double 0x00ffffff00ffff00>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-07.ll b/test/CodeGen/SystemZ/vec-const-07.ll
new file mode 100644
index 000000000000..6fcf95b69218
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-07.ll
@@ -0,0 +1,229 @@
+; Test vector replicates, v16i8 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a byte-granularity replicate with the lowest useful value.
+define <16 x i8> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vrepib %v24, 1
+; CHECK: br %r14
+  ret <16 x i8> <i8 1, i8 1, i8 1, i8 1,
+                 i8 1, i8 1, i8 1, i8 1,
+                 i8 1, i8 1, i8 1, i8 1,
+                 i8 1, i8 1, i8 1, i8 1>
+}
+
+; Test a byte-granularity replicate with an arbitrary value.
+define <16 x i8> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vrepib %v24, -55
+; CHECK: br %r14
+  ret <16 x i8> <i8 201, i8 201, i8 201, i8 201,
+                 i8 201, i8 201, i8 201, i8 201,
+                 i8 201, i8 201, i8 201, i8 201,
+                 i8 201, i8 201, i8 201, i8 201>
+}
+
+; Test a byte-granularity replicate with the highest useful value.
+define <16 x i8> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vrepib %v24, -2
+; CHECK: br %r14
+  ret <16 x i8> <i8 254, i8 254, i8 254, i8 254,
+                 i8 254, i8 254, i8 254, i8 254,
+                 i8 254, i8 254, i8 254, i8 254,
+                 i8 254, i8 254, i8 254, i8 254>
+}
+
+; Test a halfword-granularity replicate with the lowest useful value.
+define <16 x i8> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vrepih %v24, 1
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 1, i8 0, i8 1,
+                 i8 0, i8 1, i8 0, i8 1,
+                 i8 0, i8 1, i8 0, i8 1,
+                 i8 0, i8 1, i8 0, i8 1>
+}
+
+; Test a halfword-granularity replicate with an arbitrary value.
+define <16 x i8> @f5() {
+; CHECK-LABEL: f5:
+; CHECK: vrepih %v24, 25650
+; CHECK: br %r14
+  ret <16 x i8> <i8 100, i8 50, i8 100, i8 50,
+                 i8 100, i8 50, i8 100, i8 50,
+                 i8 100, i8 50, i8 100, i8 50,
+                 i8 100, i8 50, i8 100, i8 50>
+}
+
+; Test a halfword-granularity replicate with the highest useful value.
+define <16 x i8> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vrepih %v24, -2
+; CHECK: br %r14
+  ret <16 x i8> <i8 255, i8 254, i8 255, i8 254,
+                 i8 255, i8 254, i8 255, i8 254,
+                 i8 255, i8 254, i8 255, i8 254,
+                 i8 255, i8 254, i8 255, i8 254>
+}
+
+; Test a word-granularity replicate with the lowest useful positive value.
+define <16 x i8> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vrepif %v24, 1
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 0, i8 0, i8 1,
+                 i8 0, i8 0, i8 0, i8 1,
+                 i8 0, i8 0, i8 0, i8 1,
+                 i8 0, i8 0, i8 0, i8 1>
+}
+
+; Test a word-granularity replicate with the highest in-range value.
+define <16 x i8> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vrepif %v24, 32767
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 0, i8 127, i8 255,
+                 i8 0, i8 0, i8 127, i8 255,
+                 i8 0, i8 0, i8 127, i8 255,
+                 i8 0, i8 0, i8 127, i8 255>
+}
+
+; Test a word-granularity replicate with the next highest value.
+; This cannot use VREPIF.
+define <16 x i8> @f9() {
+; CHECK-LABEL: f9:
+; CHECK-NOT: vrepif
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 0, i8 128, i8 0,
+                 i8 0, i8 0, i8 128, i8 0,
+                 i8 0, i8 0, i8 128, i8 0,
+                 i8 0, i8 0, i8 128, i8 0>
+}
+
+; Test a word-granularity replicate with the lowest in-range value.
+define <16 x i8> @f10() {
+; CHECK-LABEL: f10:
+; CHECK: vrepif %v24, -32768
+; CHECK: br %r14
+  ret <16 x i8> <i8 255, i8 255, i8 128, i8 0,
+                 i8 255, i8 255, i8 128, i8 0,
+                 i8 255, i8 255, i8 128, i8 0,
+                 i8 255, i8 255, i8 128, i8 0>
+}
+
+; Test a word-granularity replicate with the next lowest value.
+; This cannot use VREPIF.
+define <16 x i8> @f11() {
+; CHECK-LABEL: f11:
+; CHECK-NOT: vrepif
+; CHECK: br %r14
+  ret <16 x i8> <i8 255, i8 255, i8 127, i8 255,
+                 i8 255, i8 255, i8 127, i8 255,
+                 i8 255, i8 255, i8 127, i8 255,
+                 i8 255, i8 255, i8 127, i8 255>
+}
+
+; Test a word-granularity replicate with the highest useful negative value.
+define <16 x i8> @f12() {
+; CHECK-LABEL: f12:
+; CHECK: vrepif %v24, -2
+; CHECK: br %r14
+  ret <16 x i8> <i8 255, i8 255, i8 255, i8 254,
+                 i8 255, i8 255, i8 255, i8 254,
+                 i8 255, i8 255, i8 255, i8 254,
+                 i8 255, i8 255, i8 255, i8 254>
+}
+
+; Test a doubleword-granularity replicate with the lowest useful positive
+; value.
+define <16 x i8> @f13() {
+; CHECK-LABEL: f13:
+; CHECK: vrepig %v24, 1
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 0, i8 0, i8 0,
+                 i8 0, i8 0, i8 0, i8 1,
+                 i8 0, i8 0, i8 0, i8 0,
+                 i8 0, i8 0, i8 0, i8 1>
+}
+
+; Test a doubleword-granularity replicate with the highest in-range value.
+define <16 x i8> @f14() {
+; CHECK-LABEL: f14:
+; CHECK: vrepig %v24, 32767
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 0, i8 0, i8 0,
+                 i8 0, i8 0, i8 127, i8 255,
+                 i8 0, i8 0, i8 0, i8 0,
+                 i8 0, i8 0, i8 127, i8 255>
+}
+
+; Test a doubleword-granularity replicate with the next highest value.
+; This cannot use VREPIG.
+define <16 x i8> @f15() {
+; CHECK-LABEL: f15:
+; CHECK-NOT: vrepig
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 0, i8 0, i8 0,
+                 i8 0, i8 0, i8 128, i8 0,
+                 i8 0, i8 0, i8 0, i8 0,
+                 i8 0, i8 0, i8 128, i8 0>
+}
+
+; Test a doubleword-granularity replicate with the lowest in-range value.
+define <16 x i8> @f16() {
+; CHECK-LABEL: f16:
+; CHECK: vrepig %v24, -32768
+; CHECK: br %r14
+  ret <16 x i8> <i8 255, i8 255, i8 255, i8 255,
+                 i8 255, i8 255, i8 128, i8 0,
+                 i8 255, i8 255, i8 255, i8 255,
+                 i8 255, i8 255, i8 128, i8 0>
+}
+
+; Test a doubleword-granularity replicate with the next lowest value.
+; This cannot use VREPIG.
+define <16 x i8> @f17() {
+; CHECK-LABEL: f17:
+; CHECK-NOT: vrepig
+; CHECK: br %r14
+  ret <16 x i8> <i8 255, i8 255, i8 255, i8 255,
+                 i8 255, i8 255, i8 127, i8 255,
+                 i8 255, i8 255, i8 255, i8 255,
+                 i8 255, i8 255, i8 127, i8 255>
+}
+
+; Test a doubleword-granularity replicate with the highest useful negative
+; value.
+define <16 x i8> @f18() {
+; CHECK-LABEL: f18:
+; CHECK: vrepig %v24, -2
+; CHECK: br %r14
+  ret <16 x i8> <i8 255, i8 255, i8 255, i8 255,
+                 i8 255, i8 255, i8 255, i8 254,
+                 i8 255, i8 255, i8 255, i8 255,
+                 i8 255, i8 255, i8 255, i8 254>
+}
+
+; Repeat f14 with undefs optimistically treated as 0.
+define <16 x i8> @f19() {
+; CHECK-LABEL: f19:
+; CHECK: vrepig %v24, 32767
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 undef, i8 0, i8 0,
+                 i8 0, i8 0, i8 127, i8 255,
+                 i8 undef, i8 0, i8 undef, i8 0,
+                 i8 0, i8 0, i8 127, i8 255>
+}
+
+; Repeat f18 with undefs optimistically treated as -1.
+define <16 x i8> @f20() {
+; CHECK-LABEL: f20:
+; CHECK: vrepig %v24, -2
+; CHECK: br %r14
+  ret <16 x i8> <i8 undef, i8 255, i8 255, i8 255,
+                 i8 255, i8 255, i8 undef, i8 254,
+                 i8 255, i8 255, i8 255, i8 undef,
+                 i8 255, i8 undef, i8 255, i8 254>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-08.ll b/test/CodeGen/SystemZ/vec-const-08.ll
new file mode 100644
index 000000000000..5ab6947e548e
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-08.ll
@@ -0,0 +1,189 @@
+; Test vector replicates, v8i16 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a byte-granularity replicate with the lowest useful value.
+define <8 x i16> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vrepib %v24, 1
+; CHECK: br %r14
+  ret <8 x i16> <i16 257, i16 257, i16 257, i16 257,
+                 i16 257, i16 257, i16 257, i16 257>
+}
+
+; Test a byte-granularity replicate with an arbitrary value.
+define <8 x i16> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vrepib %v24, -55
+; CHECK: br %r14
+  ret <8 x i16> <i16 51657, i16 51657, i16 51657, i16 51657,
+                 i16 51657, i16 51657, i16 51657, i16 51657>
+}
+
+; Test a byte-granularity replicate with the highest useful value.
+define <8 x i16> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vrepib %v24, -2
+; CHECK: br %r14
+  ret <8 x i16> <i16 -258, i16 -258, i16 -258, i16 -258,
+                 i16 -258, i16 -258, i16 -258, i16 -258>
+}
+
+; Test a halfword-granularity replicate with the lowest useful value.
+define <8 x i16> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vrepih %v24, 1
+; CHECK: br %r14
+  ret <8 x i16> <i16 1, i16 1, i16 1, i16 1,
+                 i16 1, i16 1, i16 1, i16 1>
+}
+
+; Test a halfword-granularity replicate with an arbitrary value.
+define <8 x i16> @f5() {
+; CHECK-LABEL: f5:
+; CHECK: vrepih %v24, 25650
+; CHECK: br %r14
+  ret <8 x i16> <i16 25650, i16 25650, i16 25650, i16 25650,
+                 i16 25650, i16 25650, i16 25650, i16 25650>
+}
+
+; Test a halfword-granularity replicate with the highest useful value.
+define <8 x i16> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vrepih %v24, -2
+; CHECK: br %r14
+  ret <8 x i16> <i16 65534, i16 65534, i16 65534, i16 65534,
+                 i16 65534, i16 65534, i16 65534, i16 65534>
+}
+
+; Test a word-granularity replicate with the lowest useful positive value.
+define <8 x i16> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vrepif %v24, 1
+; CHECK: br %r14
+  ret <8 x i16> <i16 0, i16 1, i16 0, i16 1,
+                 i16 0, i16 1, i16 0, i16 1>
+}
+
+; Test a word-granularity replicate with the highest in-range value.
+define <8 x i16> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vrepif %v24, 32767
+; CHECK: br %r14
+  ret <8 x i16> <i16 0, i16 32767, i16 0, i16 32767,
+                 i16 0, i16 32767, i16 0, i16 32767>
+}
+
+; Test a word-granularity replicate with the next highest value.
+; This cannot use VREPIF.
+define <8 x i16> @f9() {
+; CHECK-LABEL: f9:
+; CHECK-NOT: vrepif
+; CHECK: br %r14
+  ret <8 x i16> <i16 0, i16 32768, i16 0, i16 32768,
+                 i16 0, i16 32768, i16 0, i16 32768>
+}
+
+; Test a word-granularity replicate with the lowest in-range value.
+define <8 x i16> @f10() {
+; CHECK-LABEL: f10:
+; CHECK: vrepif %v24, -32768
+; CHECK: br %r14
+  ret <8 x i16> <i16 -1, i16 -32768, i16 -1, i16 -32768,
+                 i16 -1, i16 -32768, i16 -1, i16 -32768>
+}
+
+; Test a word-granularity replicate with the next lowest value.
+; This cannot use VREPIF.
+define <8 x i16> @f11() {
+; CHECK-LABEL: f11:
+; CHECK-NOT: vrepif
+; CHECK: br %r14
+  ret <8 x i16> <i16 -1, i16 -32769, i16 -1, i16 -32769,
+                 i16 -1, i16 -32769, i16 -1, i16 -32769>
+}
+
+; Test a word-granularity replicate with the highest useful negative value.
+define <8 x i16> @f12() {
+; CHECK-LABEL: f12:
+; CHECK: vrepif %v24, -2
+; CHECK: br %r14
+  ret <8 x i16> <i16 -1, i16 -2, i16 -1, i16 -2,
+                 i16 -1, i16 -2, i16 -1, i16 -2>
+}
+
+; Test a doubleword-granularity replicate with the lowest useful positive
+; value.
+define <8 x i16> @f13() {
+; CHECK-LABEL: f13:
+; CHECK: vrepig %v24, 1
+; CHECK: br %r14
+  ret <8 x i16> <i16 0, i16 0, i16 0, i16 1,
+                 i16 0, i16 0, i16 0, i16 1>
+}
+
+; Test a doubleword-granularity replicate with the highest in-range value.
+define <8 x i16> @f14() {
+; CHECK-LABEL: f14:
+; CHECK: vrepig %v24, 32767
+; CHECK: br %r14
+  ret <8 x i16> <i16 0, i16 0, i16 0, i16 32767,
+                 i16 0, i16 0, i16 0, i16 32767>
+}
+
+; Test a doubleword-granularity replicate with the next highest value.
+; This cannot use VREPIG.
+define <8 x i16> @f15() {
+; CHECK-LABEL: f15:
+; CHECK-NOT: vrepig
+; CHECK: br %r14
+  ret <8 x i16> <i16 0, i16 0, i16 0, i16 32768,
+                 i16 0, i16 0, i16 0, i16 32768>
+}
+
+; Test a doubleword-granularity replicate with the lowest in-range value.
+define <8 x i16> @f16() {
+; CHECK-LABEL: f16:
+; CHECK: vrepig %v24, -32768
+; CHECK: br %r14
+  ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -32768,
+                 i16 -1, i16 -1, i16 -1, i16 -32768>
+}
+
+; Test a doubleword-granularity replicate with the next lowest value.
+; This cannot use VREPIG.
+define <8 x i16> @f17() {
+; CHECK-LABEL: f17:
+; CHECK-NOT: vrepig
+; CHECK: br %r14
+  ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -32769,
+                 i16 -1, i16 -1, i16 -1, i16 -32769>
+}
+
+; Test a doubleword-granularity replicate with the highest useful negative
+; value.
+define <8 x i16> @f18() {
+; CHECK-LABEL: f18:
+; CHECK: vrepig %v24, -2
+; CHECK: br %r14
+  ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -2,
+                 i16 -1, i16 -1, i16 -1, i16 -2>
+}
+
+; Repeat f14 with undefs optimistically treated as 0.
+define <8 x i16> @f19() {
+; CHECK-LABEL: f19:
+; CHECK: vrepig %v24, 32767
+; CHECK: br %r14
+  ret <8 x i16> <i16 0, i16 undef, i16 0, i16 32767,
+                 i16 undef, i16 0, i16 undef, i16 32767>
+}
+
+; Repeat f18 with undefs optimistically treated as -1.
+define <8 x i16> @f20() {
+; CHECK-LABEL: f20:
+; CHECK: vrepig %v24, -2
+; CHECK: br %r14
+  ret <8 x i16> <i16 -1, i16 -1, i16 undef, i16 -2,
+                 i16 undef, i16 undef, i16 -1, i16 -2>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-09.ll b/test/CodeGen/SystemZ/vec-const-09.ll
new file mode 100644
index 000000000000..2cbe92594525
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-09.ll
@@ -0,0 +1,169 @@
+; Test vector replicates, v4i32 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a byte-granularity replicate with the lowest useful value.
+define <4 x i32> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vrepib %v24, 1
+; CHECK: br %r14
+  ret <4 x i32> <i32 16843009, i32 16843009, i32 16843009, i32 16843009>
+}
+
+; Test a byte-granularity replicate with an arbitrary value.
+define <4 x i32> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vrepib %v24, -55
+; CHECK: br %r14
+  ret <4 x i32> <i32 3385444809, i32 3385444809, i32 3385444809, i32 3385444809>
+}
+
+; Test a byte-granularity replicate with the highest useful value.
+define <4 x i32> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vrepib %v24, -2
+; CHECK: br %r14
+  ret <4 x i32> <i32 4278124286, i32 4278124286, i32 4278124286, i32 4278124286>
+}
+
+; Test a halfword-granularity replicate with the lowest useful value.
+define <4 x i32> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vrepih %v24, 1
+; CHECK: br %r14
+  ret <4 x i32> <i32 65537, i32 65537, i32 65537, i32 65537>
+}
+
+; Test a halfword-granularity replicate with an arbitrary value.
+define <4 x i32> @f5() {
+; CHECK-LABEL: f5:
+; CHECK: vrepih %v24, 25650
+; CHECK: br %r14
+  ret <4 x i32> <i32 1681024050, i32 1681024050, i32 1681024050, i32 1681024050>
+}
+
+; Test a halfword-granularity replicate with the highest useful value.
+define <4 x i32> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vrepih %v24, -2
+; CHECK: br %r14
+  ret <4 x i32> <i32 -65538, i32 -65538, i32 -65538, i32 -65538>
+}
+
+; Test a word-granularity replicate with the lowest useful positive value.
+define <4 x i32> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vrepif %v24, 1
+; CHECK: br %r14
+  ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+}
+
+; Test a word-granularity replicate with the highest in-range value.
+define <4 x i32> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vrepif %v24, 32767
+; CHECK: br %r14
+  ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
+}
+
+; Test a word-granularity replicate with the next highest value.
+; This cannot use VREPIF.
+define <4 x i32> @f9() {
+; CHECK-LABEL: f9:
+; CHECK-NOT: vrepif
+; CHECK: br %r14
+  ret <4 x i32> <i32 32768, i32 32768, i32 32768, i32 32768>
+}
+
+; Test a word-granularity replicate with the lowest in-range value.
+define <4 x i32> @f10() {
+; CHECK-LABEL: f10:
+; CHECK: vrepif %v24, -32768
+; CHECK: br %r14
+  ret <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
+}
+
+; Test a word-granularity replicate with the next lowest value.
+; This cannot use VREPIF.
+define <4 x i32> @f11() {
+; CHECK-LABEL: f11:
+; CHECK-NOT: vrepif
+; CHECK: br %r14
+  ret <4 x i32> <i32 -32769, i32 -32769, i32 -32769, i32 -32769>
+}
+
+; Test a word-granularity replicate with the highest useful negative value.
+define <4 x i32> @f12() {
+; CHECK-LABEL: f12:
+; CHECK: vrepif %v24, -2
+; CHECK: br %r14
+  ret <4 x i32> <i32 -2, i32 -2, i32 -2, i32 -2>
+}
+
+; Test a doubleword-granularity replicate with the lowest useful positive
+; value.
+define <4 x i32> @f13() {
+; CHECK-LABEL: f13:
+; CHECK: vrepig %v24, 1
+; CHECK: br %r14
+  ret <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+}
+
+; Test a doubleword-granularity replicate with the highest in-range value.
+define <4 x i32> @f14() {
+; CHECK-LABEL: f14:
+; CHECK: vrepig %v24, 32767
+; CHECK: br %r14
+  ret <4 x i32> <i32 0, i32 32767, i32 0, i32 32767>
+}
+
+; Test a doubleword-granularity replicate with the next highest value.
+; This cannot use VREPIG.
+define <4 x i32> @f15() {
+; CHECK-LABEL: f15:
+; CHECK-NOT: vrepig
+; CHECK: br %r14
+  ret <4 x i32> <i32 0, i32 32768, i32 0, i32 32768>
+}
+
+; Test a doubleword-granularity replicate with the lowest in-range value.
+define <4 x i32> @f16() {
+; CHECK-LABEL: f16:
+; CHECK: vrepig %v24, -32768
+; CHECK: br %r14
+  ret <4 x i32> <i32 -1, i32 -32768, i32 -1, i32 -32768>
+}
+
+; Test a doubleword-granularity replicate with the next lowest value.
+; This cannot use VREPIG.
+define <4 x i32> @f17() {
+; CHECK-LABEL: f17:
+; CHECK-NOT: vrepig
+; CHECK: br %r14
+  ret <4 x i32> <i32 -1, i32 -32769, i32 -1, i32 -32769>
+}
+
+; Test a doubleword-granularity replicate with the highest useful negative
+; value.
+define <4 x i32> @f18() {
+; CHECK-LABEL: f18:
+; CHECK: vrepig %v24, -2
+; CHECK: br %r14
+  ret <4 x i32> <i32 -1, i32 -2, i32 -1, i32 -2>
+}
+
+; Repeat f14 with undefs optimistically treated as 0, 32767.
+define <4 x i32> @f19() {
+; CHECK-LABEL: f19:
+; CHECK: vrepig %v24, 32767
+; CHECK: br %r14
+  ret <4 x i32> <i32 undef, i32 undef, i32 0, i32 32767>
+}
+
+; Repeat f18 with undefs optimistically treated as -2, -1.
+define <4 x i32> @f20() {
+; CHECK-LABEL: f20:
+; CHECK: vrepig %v24, -2
+; CHECK: br %r14
+  ret <4 x i32> <i32 -1, i32 undef, i32 undef, i32 -2>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-10.ll b/test/CodeGen/SystemZ/vec-const-10.ll
new file mode 100644
index 000000000000..0613b69a2777
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-10.ll
@@ -0,0 +1,169 @@
+; Test vector replicates, v2i64 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a byte-granularity replicate with the lowest useful value.
+define <2 x i64> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vrepib %v24, 1
+; CHECK: br %r14
+  ret <2 x i64> <i64 72340172838076673, i64 72340172838076673>
+}
+
+; Test a byte-granularity replicate with an arbitrary value.
+define <2 x i64> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vrepib %v24, -55
+; CHECK: br %r14
+  ret <2 x i64> <i64 -3906369333256140343, i64 -3906369333256140343>
+}
+
+; Test a byte-granularity replicate with the highest useful value.
+define <2 x i64> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vrepib %v24, -2
+; CHECK: br %r14
+  ret <2 x i64> <i64 -72340172838076674, i64 -72340172838076674>
+}
+
+; Test a halfword-granularity replicate with the lowest useful value.
+define <2 x i64> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vrepih %v24, 1
+; CHECK: br %r14
+  ret <2 x i64> <i64 281479271743489, i64 281479271743489>
+}
+
+; Test a halfword-granularity replicate with an arbitrary value.
+define <2 x i64> @f5() {
+; CHECK-LABEL: f5:
+; CHECK: vrepih %v24, 25650
+; CHECK: br %r14
+  ret <2 x i64> <i64 7219943320220492850, i64 7219943320220492850>
+}
+
+; Test a halfword-granularity replicate with the highest useful value.
+define <2 x i64> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vrepih %v24, -2
+; CHECK: br %r14
+  ret <2 x i64> <i64 -281479271743490, i64 -281479271743490>
+}
+
+; Test a word-granularity replicate with the lowest useful positive value.
+define <2 x i64> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vrepif %v24, 1
+; CHECK: br %r14
+  ret <2 x i64> <i64 4294967297, i64 4294967297>
+}
+
+; Test a word-granularity replicate with the highest in-range value.
+define <2 x i64> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vrepif %v24, 32767
+; CHECK: br %r14
+  ret <2 x i64> <i64 140733193420799, i64 140733193420799>
+}
+
+; Test a word-granularity replicate with the next highest value.
+; This cannot use VREPIF.
+define <2 x i64> @f9() {
+; CHECK-LABEL: f9:
+; CHECK-NOT: vrepif
+; CHECK: br %r14
+  ret <2 x i64> <i64 140737488388096, i64 140737488388096>
+}
+
+; Test a word-granularity replicate with the lowest in-range value.
+define <2 x i64> @f10() {
+; CHECK-LABEL: f10:
+; CHECK: vrepif %v24, -32768
+; CHECK: br %r14
+  ret <2 x i64> <i64 -140733193420800, i64 -140733193420800>
+}
+
+; Test a word-granularity replicate with the next lowest value.
+; This cannot use VREPIF.
+define <2 x i64> @f11() {
+; CHECK-LABEL: f11:
+; CHECK-NOT: vrepif
+; CHECK: br %r14
+  ret <2 x i64> <i64 -140737488388097, i64 -140737488388097>
+}
+
+; Test a word-granularity replicate with the highest useful negative value.
+define <2 x i64> @f12() {
+; CHECK-LABEL: f12:
+; CHECK: vrepif %v24, -2
+; CHECK: br %r14
+  ret <2 x i64> <i64 -4294967298, i64 -4294967298>
+}
+
+; Test a doubleword-granularity replicate with the lowest useful positive
+; value.
+define <2 x i64> @f13() {
+; CHECK-LABEL: f13:
+; CHECK: vrepig %v24, 1
+; CHECK: br %r14
+  ret <2 x i64> <i64 1, i64 1>
+}
+
+; Test a doubleword-granularity replicate with the highest in-range value.
+define <2 x i64> @f14() {
+; CHECK-LABEL: f14:
+; CHECK: vrepig %v24, 32767
+; CHECK: br %r14
+  ret <2 x i64> <i64 32767, i64 32767>
+}
+
+; Test a doubleword-granularity replicate with the next highest value.
+; This cannot use VREPIG.
+define <2 x i64> @f15() {
+; CHECK-LABEL: f15:
+; CHECK-NOT: vrepig
+; CHECK: br %r14
+  ret <2 x i64> <i64 32768, i64 32768>
+}
+
+; Test a doubleword-granularity replicate with the lowest in-range value.
+define <2 x i64> @f16() {
+; CHECK-LABEL: f16:
+; CHECK: vrepig %v24, -32768
+; CHECK: br %r14
+  ret <2 x i64> <i64 -32768, i64 -32768>
+}
+
+; Test a doubleword-granularity replicate with the next lowest value.
+; This cannot use VREPIG.
+define <2 x i64> @f17() {
+; CHECK-LABEL: f17:
+; CHECK-NOT: vrepig
+; CHECK: br %r14
+  ret <2 x i64> <i64 -32769, i64 -32769>
+}
+
+; Test a doubleword-granularity replicate with the highest useful negative
+; value.
+define <2 x i64> @f18() {
+; CHECK-LABEL: f18:
+; CHECK: vrepig %v24, -2
+; CHECK: br %r14
+  ret <2 x i64> <i64 -2, i64 -2>
+}
+
+; Repeat f14 with undefs optimistically treated as 32767.
+define <2 x i64> @f19() {
+; CHECK-LABEL: f19:
+; CHECK: vrepig %v24, 32767
+; CHECK: br %r14
+  ret <2 x i64> <i64 undef, i64 32767>
+}
+
+; Repeat f18 with undefs optimistically treated as -2.
+define <2 x i64> @f20() {
+; CHECK-LABEL: f20:
+; CHECK: vrepig %v24, -2
+; CHECK: br %r14
+  ret <2 x i64> <i64 undef, i64 -2>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-11.ll b/test/CodeGen/SystemZ/vec-const-11.ll
new file mode 100644
index 000000000000..0c69b8803b2f
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-11.ll
@@ -0,0 +1,189 @@
+; Test vector replicates, v4f32 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a byte-granularity replicate with the lowest useful value.
+define <4 x float> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vrepib %v24, 1
+; CHECK: br %r14
+  ret <4 x float> <float 0x3820202020000000, float 0x3820202020000000,
+                   float 0x3820202020000000, float 0x3820202020000000>
+}
+
+; Test a byte-granularity replicate with an arbitrary value.
+define <4 x float> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vrepib %v24, -55
+; CHECK: br %r14
+  ret <4 x float> <float 0xc139393920000000, float 0xc139393920000000,
+                   float 0xc139393920000000, float 0xc139393920000000>
+}
+
+; Test a byte-granularity replicate with the highest useful value.
+define <4 x float> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vrepib %v24, -2
+; CHECK: br %r14
+  ret <4 x float> <float 0xc7dfdfdfc0000000, float 0xc7dfdfdfc0000000,
+                   float 0xc7dfdfdfc0000000, float 0xc7dfdfdfc0000000>
+}
+
+; Test a halfword-granularity replicate with the lowest useful value.
+define <4 x float> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vrepih %v24, 1
+; CHECK: br %r14
+  ret <4 x float> <float 0x37a0001000000000, float 0x37a0001000000000,
+                   float 0x37a0001000000000, float 0x37a0001000000000>
+}
+
+; Test a halfword-granularity replicate with an arbitrary value.
+define <4 x float> @f5() {
+; CHECK-LABEL: f5:
+; CHECK: vrepih %v24, 25650
+; CHECK: br %r14
+  ret <4 x float> <float 0x44864c8640000000, float 0x44864c8640000000,
+                   float 0x44864c8640000000, float 0x44864c8640000000>
+}
+
+; Test a halfword-granularity replicate with the highest useful value.
+define <4 x float> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vrepih %v24, -2
+; CHECK: br %r14
+  ret <4 x float> <float 0xffffdfffc0000000, float 0xffffdfffc0000000,
+                   float 0xffffdfffc0000000, float 0xffffdfffc0000000>
+}
+
+; Test a word-granularity replicate with the lowest useful positive value.
+define <4 x float> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vrepif %v24, 1
+; CHECK: br %r14
+  ret <4 x float> <float 0x36a0000000000000, float 0x36a0000000000000,
+                   float 0x36a0000000000000, float 0x36a0000000000000>
+}
+
+; Test a word-granularity replicate with the highest in-range value.
+define <4 x float> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vrepif %v24, 32767
+; CHECK: br %r14
+  ret <4 x float> <float 0x378fffc000000000, float 0x378fffc000000000,
+                   float 0x378fffc000000000, float 0x378fffc000000000>
+}
+
+; Test a word-granularity replicate with the next highest value.
+; This cannot use VREPIF.
+define <4 x float> @f9() {
+; CHECK-LABEL: f9:
+; CHECK-NOT: vrepif
+; CHECK: br %r14
+  ret <4 x float> <float 0x3790000000000000, float 0x3790000000000000,
+                   float 0x3790000000000000, float 0x3790000000000000>
+}
+
+; Test a word-granularity replicate with the lowest in-range value.
+define <4 x float> @f10() {
+; CHECK-LABEL: f10:
+; CHECK: vrepif %v24, -32768
+; CHECK: br %r14
+  ret <4 x float> <float 0xfffff00000000000, float 0xfffff00000000000,
+                   float 0xfffff00000000000, float 0xfffff00000000000>
+}
+
+; Test a word-granularity replicate with the next lowest value.
+; This cannot use VREPIF.
+define <4 x float> @f11() {
+; CHECK-LABEL: f11:
+; CHECK-NOT: vrepif
+; CHECK: br %r14
+  ret <4 x float> <float 0xffffefffe0000000, float 0xffffefffe0000000,
+                   float 0xffffefffe0000000, float 0xffffefffe0000000>
+}
+
+; Test a word-granularity replicate with the highest useful negative value.
+define <4 x float> @f12() {
+; CHECK-LABEL: f12:
+; CHECK: vrepif %v24, -2
+; CHECK: br %r14
+  ret <4 x float> <float 0xffffffffc0000000, float 0xffffffffc0000000,
+                   float 0xffffffffc0000000, float 0xffffffffc0000000>
+}
+
+; Test a doubleword-granularity replicate with the lowest useful positive
+; value.
+define <4 x float> @f13() {
+; CHECK-LABEL: f13:
+; CHECK: vrepig %v24, 1
+; CHECK: br %r14
+  ret <4 x float> <float 0.0, float 0x36a0000000000000,
+                   float 0.0, float 0x36a0000000000000>
+}
+
+; Test a doubleword-granularity replicate with the highest in-range value.
+define <4 x float> @f14() {
+; CHECK-LABEL: f14:
+; CHECK: vrepig %v24, 32767
+; CHECK: br %r14
+  ret <4 x float> <float 0.0, float 0x378fffc000000000,
+                   float 0.0, float 0x378fffc000000000>
+}
+
+; Test a doubleword-granularity replicate with the next highest value.
+; This cannot use VREPIG.
+define <4 x float> @f15() {
+; CHECK-LABEL: f15:
+; CHECK-NOT: vrepig
+; CHECK: br %r14
+  ret <4 x float> <float 0.0, float 0x3790000000000000,
+                   float 0.0, float 0x3790000000000000>
+}
+
+; Test a doubleword-granularity replicate with the lowest in-range value.
+define <4 x float> @f16() {
+; CHECK-LABEL: f16:
+; CHECK: vrepig %v24, -32768
+; CHECK: br %r14
+  ret <4 x float> <float 0xffffffffe0000000, float 0xfffff00000000000,
+                   float 0xffffffffe0000000, float 0xfffff00000000000>
+}
+
+; Test a doubleword-granularity replicate with the next lowest value.
+; This cannot use VREPIG.
+define <4 x float> @f17() {
+; CHECK-LABEL: f17:
+; CHECK-NOT: vrepig
+; CHECK: br %r14
+  ret <4 x float> <float 0xffffffffe0000000, float 0xffffefffe0000000,
+                   float 0xffffffffe0000000, float 0xffffefffe0000000>
+}
+
+; Test a doubleword-granularity replicate with the highest useful negative
+; value.
+define <4 x float> @f18() {
+; CHECK-LABEL: f18:
+; CHECK: vrepig %v24, -2
+; CHECK: br %r14
+  ret <4 x float> <float 0xffffffffe0000000, float 0xffffffffc0000000,
+                   float 0xffffffffe0000000, float 0xffffffffc0000000>
+}
+
+; Repeat f14 with undefs optimistically treated as 0, 32767.
+define <4 x float> @f19() {
+; CHECK-LABEL: f19:
+; CHECK: vrepig %v24, 32767
+; CHECK: br %r14
+  ret <4 x float> <float undef, float undef,
+                   float 0.0, float 0x378fffc000000000>
+}
+
+; Repeat f18 with undefs optimistically treated as -2, -1.
+define <4 x float> @f20() {
+; CHECK-LABEL: f20:
+; CHECK: vrepig %v24, -2
+; CHECK: br %r14
+  ret <4 x float> <float 0xffffffffe0000000, float undef,
+                   float undef, float 0xffffffffc0000000>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-12.ll b/test/CodeGen/SystemZ/vec-const-12.ll
new file mode 100644
index 000000000000..ca66a3d173eb
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-12.ll
@@ -0,0 +1,169 @@
+; Test vector replicates, v2f64 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a byte-granularity replicate with the lowest useful value.
+define <2 x double> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vrepib %v24, 1
+; CHECK: br %r14
+  ret <2 x double> <double 0x0101010101010101, double 0x0101010101010101>
+}
+
+; Test a byte-granularity replicate with an arbitrary value.
+define <2 x double> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vrepib %v24, -55
+; CHECK: br %r14
+  ret <2 x double> <double 0xc9c9c9c9c9c9c9c9, double 0xc9c9c9c9c9c9c9c9>
+}
+
+; Test a byte-granularity replicate with the highest useful value.
+define <2 x double> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vrepib %v24, -2
+; CHECK: br %r14
+  ret <2 x double> <double 0xfefefefefefefefe, double 0xfefefefefefefefe>
+}
+
+; Test a halfword-granularity replicate with the lowest useful value.
+define <2 x double> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vrepih %v24, 1
+; CHECK: br %r14
+  ret <2 x double> <double 0x0001000100010001, double 0x0001000100010001>
+}
+
+; Test a halfword-granularity replicate with an arbitrary value.
+define <2 x double> @f5() {
+; CHECK-LABEL: f5:
+; CHECK: vrepih %v24, 25650
+; CHECK: br %r14
+  ret <2 x double> <double 0x6432643264326432, double 0x6432643264326432>
+}
+
+; Test a halfword-granularity replicate with the highest useful value.
+define <2 x double> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vrepih %v24, -2
+; CHECK: br %r14
+  ret <2 x double> <double 0xfffefffefffefffe, double 0xfffefffefffefffe>
+}
+
+; Test a word-granularity replicate with the lowest useful positive value.
+define <2 x double> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vrepif %v24, 1
+; CHECK: br %r14
+  ret <2 x double> <double 0x0000000100000001, double 0x0000000100000001>
+}
+
+; Test a word-granularity replicate with the highest in-range value.
+define <2 x double> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vrepif %v24, 32767
+; CHECK: br %r14
+  ret <2 x double> <double 0x00007fff00007fff, double 0x00007fff00007fff>
+}
+
+; Test a word-granularity replicate with the next highest value.
+; This cannot use VREPIF.
+define <2 x double> @f9() {
+; CHECK-LABEL: f9:
+; CHECK-NOT: vrepif
+; CHECK: br %r14
+  ret <2 x double> <double 0x0000800000008000, double 0x0000800000008000>
+}
+
+; Test a word-granularity replicate with the lowest in-range value.
+define <2 x double> @f10() {
+; CHECK-LABEL: f10:
+; CHECK: vrepif %v24, -32768
+; CHECK: br %r14
+  ret <2 x double> <double 0xffff8000ffff8000, double 0xffff8000ffff8000>
+}
+
+; Test a word-granularity replicate with the next lowest value.
+; This cannot use VREPIF.
+define <2 x double> @f11() {
+; CHECK-LABEL: f11:
+; CHECK-NOT: vrepif
+; CHECK: br %r14
+  ret <2 x double> <double 0xffff7fffffff7fff, double 0xffff7fffffff7fff>
+}
+
+; Test a word-granularity replicate with the highest useful negative value.
+define <2 x double> @f12() {
+; CHECK-LABEL: f12:
+; CHECK: vrepif %v24, -2
+; CHECK: br %r14
+  ret <2 x double> <double 0xfffffffefffffffe, double 0xfffffffefffffffe>
+}
+
+; Test a doubleword-granularity replicate with the lowest useful positive
+; value.
+define <2 x double> @f13() {
+; CHECK-LABEL: f13:
+; CHECK: vrepig %v24, 1
+; CHECK: br %r14
+  ret <2 x double> <double 0x0000000000000001, double 0x0000000000000001>
+}
+
+; Test a doubleword-granularity replicate with the highest in-range value.
+define <2 x double> @f14() {
+; CHECK-LABEL: f14:
+; CHECK: vrepig %v24, 32767
+; CHECK: br %r14
+  ret <2 x double> <double 0x0000000000007fff, double 0x0000000000007fff>
+}
+
+; Test a doubleword-granularity replicate with the next highest value.
+; This cannot use VREPIG.
+define <2 x double> @f15() {
+; CHECK-LABEL: f15:
+; CHECK-NOT: vrepig
+; CHECK: br %r14
+  ret <2 x double> <double 0x0000000000008000, double 0x0000000000008000>
+}
+
+; Test a doubleword-granularity replicate with the lowest in-range value.
+define <2 x double> @f16() {
+; CHECK-LABEL: f16:
+; CHECK: vrepig %v24, -32768
+; CHECK: br %r14
+  ret <2 x double> <double 0xffffffffffff8000, double 0xffffffffffff8000>
+}
+
+; Test a doubleword-granularity replicate with the next lowest value.
+; This cannot use VREPIG.
+define <2 x double> @f17() {
+; CHECK-LABEL: f17:
+; CHECK-NOT: vrepig
+; CHECK: br %r14
+  ret <2 x double> <double 0xffffffffffff7fff, double 0xffffffffffff7fff>
+}
+
+; Test a doubleword-granularity replicate with the highest useful negative
+; value.
+define <2 x double> @f18() {
+; CHECK-LABEL: f18:
+; CHECK: vrepig %v24, -2
+; CHECK: br %r14
+  ret <2 x double> <double 0xfffffffffffffffe, double 0xfffffffffffffffe>
+}
+
+; Repeat f14 with undefs optimistically treated as 32767.
+define <2 x double> @f19() {
+; CHECK-LABEL: f19:
+; CHECK: vrepig %v24, 32767
+; CHECK: br %r14
+  ret <2 x double> <double undef, double 0x0000000000007fff>
+}
+
+; Repeat f18 with undefs optimistically treated as -2.
+define <2 x double> @f20() {
+; CHECK-LABEL: f20:
+; CHECK: vrepig %v24, -2
+; CHECK: br %r14
+  ret <2 x double> <double undef, double 0xfffffffffffffffe>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-13.ll b/test/CodeGen/SystemZ/vec-const-13.ll
new file mode 100644
index 000000000000..2cc425252c21
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-13.ll
@@ -0,0 +1,193 @@
+; Test vector replicates that use VECTOR GENERATE MASK, v16i8 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a word-granularity replicate with the lowest value that cannot use
+; VREPIF.
+define <16 x i8> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vgmf %v24, 16, 16
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 0, i8 128, i8 0,
+                 i8 0, i8 0, i8 128, i8 0,
+                 i8 0, i8 0, i8 128, i8 0,
+                 i8 0, i8 0, i8 128, i8 0>
+}
+
+; Test a word-granularity replicate that has the lower 17 bits set.
+define <16 x i8> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vgmf %v24, 15, 31
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 1, i8 255, i8 255,
+                 i8 0, i8 1, i8 255, i8 255,
+                 i8 0, i8 1, i8 255, i8 255,
+                 i8 0, i8 1, i8 255, i8 255>
+}
+
+; Test a word-granularity replicate that has the upper 15 bits set.
+define <16 x i8> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vgmf %v24, 0, 14
+; CHECK: br %r14
+  ret <16 x i8> <i8 255, i8 254, i8 0, i8 0,
+                 i8 255, i8 254, i8 0, i8 0,
+                 i8 255, i8 254, i8 0, i8 0,
+                 i8 255, i8 254, i8 0, i8 0>
+}
+
+; Test a word-granularity replicate that has middle bits set.
+define <16 x i8> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vgmf %v24, 12, 17
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 15, i8 192, i8 0,
+                 i8 0, i8 15, i8 192, i8 0,
+                 i8 0, i8 15, i8 192, i8 0,
+                 i8 0, i8 15, i8 192, i8 0>
+}
+
+; Test a word-granularity replicate with a wrap-around mask.
+define <16 x i8> @f5() {
+; CHECK-LABEL: f5:
+; CHECK: vgmf %v24, 17, 15
+; CHECK: br %r14
+  ret <16 x i8> <i8 255, i8 255, i8 127, i8 255,
+                 i8 255, i8 255, i8 127, i8 255,
+                 i8 255, i8 255, i8 127, i8 255,
+                 i8 255, i8 255, i8 127, i8 255>
+}
+
+; Test a doubleword-granularity replicate with the lowest value that cannot
+; use VREPIG.
+define <16 x i8> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vgmg %v24, 48, 48
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 0, i8 0, i8 0,
+                 i8 0, i8 0, i8 128, i8 0,
+                 i8 0, i8 0, i8 0, i8 0,
+                 i8 0, i8 0, i8 128, i8 0>
+}
+
+; Test a doubleword-granularity replicate that has the lower 22 bits set.
+define <16 x i8> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vgmg %v24, 42, 63
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 0, i8 0, i8 0,
+                 i8 0, i8 63, i8 255, i8 255,
+                 i8 0, i8 0, i8 0, i8 0,
+                 i8 0, i8 63, i8 255, i8 255>
+}
+
+; Test a doubleword-granularity replicate that has the upper 45 bits set.
+define <16 x i8> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vgmg %v24, 0, 44
+; CHECK: br %r14
+  ret <16 x i8> <i8 255, i8 255, i8 255, i8 255,
+                 i8 255, i8 248, i8 0, i8 0,
+                 i8 255, i8 255, i8 255, i8 255,
+                 i8 255, i8 248, i8 0, i8 0>
+}
+
+; Test a doubleword-granularity replicate that has middle bits set.
+define <16 x i8> @f9() {
+; CHECK-LABEL: f9:
+; CHECK: vgmg %v24, 31, 42
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 0, i8 0, i8 1,
+                 i8 255, i8 224, i8 0, i8 0,
+                 i8 0, i8 0, i8 0, i8 1,
+                 i8 255, i8 224, i8 0, i8 0>
+}
+
+; Test a doubleword-granularity replicate with a wrap-around mask.
+define <16 x i8> @f10() {
+; CHECK-LABEL: f10:
+; CHECK: vgmg %v24, 18, 0
+; CHECK: br %r14
+  ret <16 x i8> <i8 128, i8 0, i8 63, i8 255,
+                 i8 255, i8 255, i8 255, i8 255,
+                 i8 128, i8 0, i8 63, i8 255,
+                 i8 255, i8 255, i8 255, i8 255>
+}
+
+; Retest f1 with arbitrary undefs instead of 0s.
+define <16 x i8> @f11() {
+; CHECK-LABEL: f11:
+; CHECK: vgmf %v24, 16, 16
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 undef, i8 128, i8 0,
+                 i8 0, i8 0, i8 128, i8 undef,
+                 i8 undef, i8 0, i8 128, i8 0,
+                 i8 undef, i8 undef, i8 128, i8 0>
+}
+
+; Try a case where we want consistent undefs to be treated as 0.
+define <16 x i8> @f12() {
+; CHECK-LABEL: f12:
+; CHECK: vgmf %v24, 15, 23
+; CHECK: br %r14
+  ret <16 x i8> <i8 undef, i8 1, i8 255, i8 0,
+                 i8 undef, i8 1, i8 255, i8 0,
+                 i8 undef, i8 1, i8 255, i8 0,
+                 i8 undef, i8 1, i8 255, i8 0>
+}
+
+; ...and again with the lower bits of the replicated constant.
+define <16 x i8> @f13() {
+; CHECK-LABEL: f13:
+; CHECK: vgmf %v24, 15, 22
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 1, i8 254, i8 undef,
+                 i8 0, i8 1, i8 254, i8 undef,
+                 i8 0, i8 1, i8 254, i8 undef,
+                 i8 0, i8 1, i8 254, i8 undef>
+}
+
+; Try a case where we want consistent undefs to be treated as -1.
+define <16 x i8> @f14() {
+; CHECK-LABEL: f14:
+; CHECK: vgmf %v24, 28, 8
+; CHECK: br %r14
+  ret <16 x i8> <i8 undef, i8 128, i8 0, i8 15,
+                 i8 undef, i8 128, i8 0, i8 15,
+                 i8 undef, i8 128, i8 0, i8 15,
+                 i8 undef, i8 128, i8 0, i8 15>
+}
+
+; ...and again with the lower bits of the replicated constant.
+define <16 x i8> @f15() {
+; CHECK-LABEL: f15:
+; CHECK: vgmf %v24, 18, 3
+; CHECK: br %r14
+  ret <16 x i8> <i8 240, i8 0, i8 63, i8 undef,
+                 i8 240, i8 0, i8 63, i8 undef,
+                 i8 240, i8 0, i8 63, i8 undef,
+                 i8 240, i8 0, i8 63, i8 undef>
+}
+
+; Repeat f9 with arbitrary undefs.
+define <16 x i8> @f16() {
+; CHECK-LABEL: f16:
+; CHECK: vgmg %v24, 31, 42
+; CHECK: br %r14
+  ret <16 x i8> <i8 undef, i8 0, i8 undef, i8 1,
+                 i8 255, i8 undef, i8 0, i8 0,
+                 i8 0, i8 0, i8 0, i8 1,
+                 i8 undef, i8 224, i8 undef, i8 undef>
+}
+
+; Try a case where we want some consistent undefs to be treated as 0
+; and some to be treated as 255.
+define <16 x i8> @f17() {
+; CHECK-LABEL: f17:
+; CHECK: vgmg %v24, 23, 35
+; CHECK: br %r14
+  ret <16 x i8> <i8 0, i8 undef, i8 1, i8 undef,
+                 i8 240, i8 undef, i8 0, i8 0,
+                 i8 0, i8 undef, i8 1, i8 undef,
+                 i8 240, i8 undef, i8 0, i8 0>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-14.ll b/test/CodeGen/SystemZ/vec-const-14.ll
new file mode 100644
index 000000000000..0e3f124dbf6a
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-14.ll
@@ -0,0 +1,113 @@
+; Test vector replicates that use VECTOR GENERATE MASK, v8i16 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a word-granularity replicate with the lowest value that cannot use
+; VREPIF.
+define <8 x i16> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vgmf %v24, 16, 16
+; CHECK: br %r14
+  ret <8 x i16> <i16 0, i16 32768, i16 0, i16 32768,
+                 i16 0, i16 32768, i16 0, i16 32768>
+}
+
+; Test a word-granularity replicate that has the lower 17 bits set.
+define <8 x i16> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vgmf %v24, 15, 31
+; CHECK: br %r14
+  ret <8 x i16> <i16 1, i16 -1, i16 1, i16 -1,
+                 i16 1, i16 -1, i16 1, i16 -1>
+}
+
+; Test a word-granularity replicate that has the upper 15 bits set.
+define <8 x i16> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vgmf %v24, 0, 14
+; CHECK: br %r14
+  ret <8 x i16> <i16 -2, i16 0, i16 -2, i16 0,
+                 i16 -2, i16 0, i16 -2, i16 0>
+}
+
+; Test a word-granularity replicate that has middle bits set.
+define <8 x i16> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vgmf %v24, 12, 17
+; CHECK: br %r14
+  ret <8 x i16> <i16 15, i16 49152, i16 15, i16 49152,
+                 i16 15, i16 49152, i16 15, i16 49152>
+}
+
+; Test a word-granularity replicate with a wrap-around mask.
+define <8 x i16> @f5() {
+; CHECK-LABEL: f5:
+; CHECK: vgmf %v24, 17, 15
+; CHECK: br %r14
+  ret <8 x i16> <i16 -1, i16 32767, i16 -1, i16 32767,
+                 i16 -1, i16 32767, i16 -1, i16 32767>
+}
+
+; Test a doubleword-granularity replicate with the lowest value that cannot
+; use VREPIG.
+define <8 x i16> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vgmg %v24, 48, 48
+; CHECK: br %r14
+  ret <8 x i16> <i16 0, i16 0, i16 0, i16 32768,
+                 i16 0, i16 0, i16 0, i16 32768>
+}
+
+; Test a doubleword-granularity replicate that has the lower 22 bits set.
+define <8 x i16> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vgmg %v24, 42, 63
+; CHECK: br %r14
+  ret <8 x i16> <i16 0, i16 0, i16 63, i16 -1,
+                 i16 0, i16 0, i16 63, i16 -1>
+}
+
+; Test a doubleword-granularity replicate that has the upper 45 bits set.
+define <8 x i16> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vgmg %v24, 0, 44
+; CHECK: br %r14
+  ret <8 x i16> <i16 -1, i16 -1, i16 -8, i16 0,
+                 i16 -1, i16 -1, i16 -8, i16 0>
+}
+
+; Test a doubleword-granularity replicate that has middle bits set.
+define <8 x i16> @f9() {
+; CHECK-LABEL: f9:
+; CHECK: vgmg %v24, 31, 42
+; CHECK: br %r14
+  ret <8 x i16> <i16 0, i16 1, i16 -32, i16 0,
+                 i16 0, i16 1, i16 -32, i16 0>
+}
+
+; Test a doubleword-granularity replicate with a wrap-around mask.
+define <8 x i16> @f10() {
+; CHECK-LABEL: f10:
+; CHECK: vgmg %v24, 18, 0
+; CHECK: br %r14
+  ret <8 x i16> <i16 32768, i16 16383, i16 -1, i16 -1,
+                 i16 32768, i16 16383, i16 -1, i16 -1>
+}
+
+; Retest f1 with arbitrary undefs instead of 0s.
+define <8 x i16> @f11() {
+; CHECK-LABEL: f11:
+; CHECK: vgmf %v24, 16, 16
+; CHECK: br %r14
+  ret <8 x i16> <i16 undef, i16 32768, i16 0, i16 32768,
+                 i16 0, i16 32768, i16 undef, i16 32768>
+}
+
+; ...likewise f9.
+define <8 x i16> @f12() {
+; CHECK-LABEL: f12:
+; CHECK: vgmg %v24, 31, 42
+; CHECK: br %r14
+  ret <8 x i16> <i16 undef, i16 1, i16 -32, i16 0,
+                 i16 0, i16 1, i16 -32, i16 undef>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-15.ll b/test/CodeGen/SystemZ/vec-const-15.ll
new file mode 100644
index 000000000000..cec445efe893
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-15.ll
@@ -0,0 +1,85 @@
+; Test vector replicates that use VECTOR GENERATE MASK, v4i32 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a word-granularity replicate with the lowest value that cannot use
+; VREPIF.
+define <4 x i32> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vgmf %v24, 16, 16
+; CHECK: br %r14
+  ret <4 x i32> <i32 32768, i32 32768, i32 32768, i32 32768>
+}
+
+; Test a word-granularity replicate that has the lower 17 bits set.
+define <4 x i32> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vgmf %v24, 15, 31
+; CHECK: br %r14
+  ret <4 x i32> <i32 131071, i32 131071, i32 131071, i32 131071>
+}
+
+; Test a word-granularity replicate that has the upper 15 bits set.
+define <4 x i32> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vgmf %v24, 0, 14
+; CHECK: br %r14
+  ret <4 x i32> <i32 -131072, i32 -131072, i32 -131072, i32 -131072>
+}
+
+; Test a word-granularity replicate that has middle bits set.
+define <4 x i32> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vgmf %v24, 12, 17
+; CHECK: br %r14
+  ret <4 x i32> <i32 1032192, i32 1032192, i32 1032192, i32 1032192>
+}
+
+; Test a word-granularity replicate with a wrap-around mask.
+define <4 x i32> @f5() {
+; CHECK-LABEL: f5:
+; CHECK: vgmf %v24, 17, 15
+; CHECK: br %r14
+  ret <4 x i32> <i32 -32769, i32 -32769, i32 -32769, i32 -32769>
+}
+
+; Test a doubleword-granularity replicate with the lowest value that cannot
+; use VREPIG.
+define <4 x i32> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vgmg %v24, 48, 48
+; CHECK: br %r14
+  ret <4 x i32> <i32 0, i32 32768, i32 0, i32 32768>
+}
+
+; Test a doubleword-granularity replicate that has the lower 22 bits set.
+define <4 x i32> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vgmg %v24, 42, 63
+; CHECK: br %r14
+  ret <4 x i32> <i32 0, i32 4194303, i32 0, i32 4194303>
+}
+
+; Test a doubleword-granularity replicate that has the upper 45 bits set.
+define <4 x i32> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vgmg %v24, 0, 44
+; CHECK: br %r14
+  ret <4 x i32> <i32 -1, i32 -524288, i32 -1, i32 -524288>
+}
+
+; Test a doubleword-granularity replicate that has middle bits set.
+define <4 x i32> @f9() {
+; CHECK-LABEL: f9:
+; CHECK: vgmg %v24, 31, 42
+; CHECK: br %r14
+  ret <4 x i32> <i32 1, i32 -2097152, i32 1, i32 -2097152>
+}
+
+; Test a doubleword-granularity replicate with a wrap-around mask.
+define <4 x i32> @f10() {
+; CHECK-LABEL: f10:
+; CHECK: vgmg %v24, 18, 0
+; CHECK: br %r14
+  ret <4 x i32> <i32 -2147467265, i32 -1, i32 -2147467265, i32 -1>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-16.ll b/test/CodeGen/SystemZ/vec-const-16.ll
new file mode 100644
index 000000000000..1ab7de2761cf
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-16.ll
@@ -0,0 +1,85 @@
+; Test vector replicates that use VECTOR GENERATE MASK, v2i64 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a word-granularity replicate with the lowest value that cannot use
+; VREPIF.
+define <2 x i64> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vgmf %v24, 16, 16
+; CHECK: br %r14
+  ret <2 x i64> <i64 140737488388096, i64 140737488388096>
+}
+
+; Test a word-granularity replicate that has the lower 17 bits set.
+define <2 x i64> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vgmf %v24, 15, 31
+; CHECK: br %r14
+  ret <2 x i64> <i64 562945658585087, i64 562945658585087>
+}
+
+; Test a word-granularity replicate that has the upper 15 bits set.
+define <2 x i64> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vgmf %v24, 0, 14
+; CHECK: br %r14
+  ret <2 x i64> <i64 -562945658585088, i64 -562945658585088>
+}
+
+; Test a word-granularity replicate that has middle bits set.
+define <2 x i64> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vgmf %v24, 12, 17
+; CHECK: br %r14
+  ret <2 x i64> <i64 4433230884225024, i64 4433230884225024>
+}
+
+; Test a word-granularity replicate with a wrap-around mask.
+define <2 x i64> @f5() {
+; CHECK-LABEL: f5:
+; CHECK: vgmf %v24, 17, 15
+; CHECK: br %r14
+  ret <2 x i64> <i64 -140737488388097, i64 -140737488388097>
+}
+
+; Test a doubleword-granularity replicate with the lowest value that cannot
+; use VREPIG.
+define <2 x i64> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vgmg %v24, 48, 48
+; CHECK: br %r14
+  ret <2 x i64> <i64 32768, i64 32768>
+}
+
+; Test a doubleword-granularity replicate that has the lower 22 bits set.
+define <2 x i64> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vgmg %v24, 42, 63
+; CHECK: br %r14
+  ret <2 x i64> <i64 4194303, i64 4194303>
+}
+
+; Test a doubleword-granularity replicate that has the upper 45 bits set.
+define <2 x i64> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vgmg %v24, 0, 44
+; CHECK: br %r14
+  ret <2 x i64> <i64 -524288, i64 -524288>
+}
+
+; Test a doubleword-granularity replicate that has middle bits set.
+define <2 x i64> @f9() {
+; CHECK-LABEL: f9:
+; CHECK: vgmg %v24, 31, 42
+; CHECK: br %r14
+  ret <2 x i64> <i64 8587837440, i64 8587837440>
+}
+
+; Test a doubleword-granularity replicate with a wrap-around mask.
+define <2 x i64> @f10() {
+; CHECK-LABEL: f10:
+; CHECK: vgmg %v24, 18, 0
+; CHECK: br %r14
+  ret <2 x i64> <i64 -9223301668110598145, i64 -9223301668110598145>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-17.ll b/test/CodeGen/SystemZ/vec-const-17.ll
new file mode 100644
index 000000000000..1306eab556e9
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-17.ll
@@ -0,0 +1,95 @@
+; Test vector replicates that use VECTOR GENERATE MASK, v4f32 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a word-granularity replicate with the lowest value that cannot use
+; VREPIF.
+define <4 x float> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vgmf %v24, 16, 16
+; CHECK: br %r14
+  ret <4 x float> <float 0x3790000000000000, float 0x3790000000000000,
+                   float 0x3790000000000000, float 0x3790000000000000>
+}
+
+; Test a word-granularity replicate that has the lower 17 bits set.
+define <4 x float> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vgmf %v24, 15, 31
+; CHECK: br %r14
+  ret <4 x float> <float 0x37affff000000000, float 0x37affff000000000,
+                   float 0x37affff000000000, float 0x37affff000000000>
+}
+
+; Test a word-granularity replicate that has the upper 15 bits set.
+define <4 x float> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vgmf %v24, 0, 14
+; CHECK: br %r14
+  ret <4 x float> <float 0xffffc00000000000, float 0xffffc00000000000,
+                   float 0xffffc00000000000, float 0xffffc00000000000>
+}
+
+; Test a word-granularity replicate that has middle bits set.
+define <4 x float> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vgmf %v24, 2, 8
+; CHECK: br %r14
+  ret <4 x float> <float 0x3ff0000000000000, float 0x3ff0000000000000,
+                   float 0x3ff0000000000000, float 0x3ff0000000000000>
+}
+
+; Test a word-granularity replicate with a wrap-around mask.
+define <4 x float> @f5() {
+; CHECK-LABEL: f5:
+; CHECK: vgmf %v24, 9, 1
+; CHECK: br %r14
+  ret <4 x float> <float 0xc00fffffe0000000, float 0xc00fffffe0000000,
+                   float 0xc00fffffe0000000, float 0xc00fffffe0000000>
+}
+
+; Test a doubleword-granularity replicate with the lowest value that cannot
+; use VREPIG.
+define <4 x float> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vgmg %v24, 48, 48
+; CHECK: br %r14
+  ret <4 x float> <float 0.0, float 0x3790000000000000,
+                   float 0.0, float 0x3790000000000000>
+}
+
+; Test a doubleword-granularity replicate that has the lower 22 bits set.
+define <4 x float> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vgmg %v24, 42, 63
+; CHECK: br %r14
+  ret <4 x float> <float 0.0, float 0x37ffffff80000000,
+                   float 0.0, float 0x37ffffff80000000>
+}
+
+; Test a doubleword-granularity replicate that has the upper 45 bits set.
+define <4 x float> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vgmg %v24, 0, 44
+; CHECK: br %r14
+  ret <4 x float> <float 0xffffffffe0000000, float 0xffff000000000000,
+                   float 0xffffffffe0000000, float 0xffff000000000000>
+}
+
+; Test a doubleword-granularity replicate that has middle bits set.
+define <4 x float> @f9() {
+; CHECK-LABEL: f9:
+; CHECK: vgmg %v24, 34, 41
+; CHECK: br %r14
+  ret <4 x float> <float 0.0, float 0x3ff8000000000000,
+                   float 0.0, float 0x3ff8000000000000>
+}
+
+; Test a doubleword-granularity replicate with a wrap-around mask.
+define <4 x float> @f10() {
+; CHECK-LABEL: f10:
+; CHECK: vgmg %v24, 32, 0
+; CHECK: br %r14
+  ret <4 x float> <float 0x8000000000000000, float 0xffffffffe0000000,
+                   float 0x8000000000000000, float 0xffffffffe0000000>
+}
diff --git a/test/CodeGen/SystemZ/vec-const-18.ll b/test/CodeGen/SystemZ/vec-const-18.ll
new file mode 100644
index 000000000000..c6c20c2a0037
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-const-18.ll
@@ -0,0 +1,85 @@
+; Test vector replicates that use VECTOR GENERATE MASK, v2f64 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a word-granularity replicate with the lowest value that cannot use
+; VREPIF.
+define <2 x double> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vgmf %v24, 16, 16
+; CHECK: br %r14
+  ret <2 x double> <double 0x0000800000008000, double 0x0000800000008000>
+}
+
+; Test a word-granularity replicate that has the lower 17 bits set.
+define <2 x double> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vgmf %v24, 15, 31
+; CHECK: br %r14
+  ret <2 x double> <double 0x0001ffff0001ffff, double 0x0001ffff0001ffff>
+}
+
+; Test a word-granularity replicate that has the upper 15 bits set.
+define <2 x double> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vgmf %v24, 0, 14
+; CHECK: br %r14
+  ret <2 x double> <double 0xfffe0000fffe0000, double 0xfffe0000fffe0000>
+}
+
+; Test a word-granularity replicate that has middle bits set.
+define <2 x double> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vgmf %v24, 2, 11
+; CHECK: br %r14
+  ret <2 x double> <double 0x3ff000003ff00000, double 0x3ff000003ff00000>
+}
+
+; Test a word-granularity replicate with a wrap-around mask.
+define <2 x double> @f5() {
+; CHECK-LABEL: f5:
+; CHECK: vgmf %v24, 17, 15
+; CHECK: br %r14
+  ret <2 x double> <double 0xffff7fffffff7fff, double 0xffff7fffffff7fff>
+}
+
+; Test a doubleword-granularity replicate with the lowest value that cannot
+; use VREPIG.
+define <2 x double> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vgmg %v24, 48, 48
+; CHECK: br %r14
+  ret <2 x double> <double 0x0000000000008000, double 0x0000000000008000>
+}
+
+; Test a doubleword-granularity replicate that has the lower 22 bits set.
+define <2 x double> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vgmg %v24, 42, 63
+; CHECK: br %r14
+  ret <2 x double> <double 0x000000000003fffff, double 0x000000000003fffff>
+}
+
+; Test a doubleword-granularity replicate that has the upper 45 bits set.
+define <2 x double> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vgmg %v24, 0, 44
+; CHECK: br %r14
+  ret <2 x double> <double 0xfffffffffff80000, double 0xfffffffffff80000>
+}
+
+; Test a doubleword-granularity replicate that has middle bits set.
+define <2 x double> @f9() {
+; CHECK-LABEL: f9:
+; CHECK: vgmg %v24, 2, 11
+; CHECK: br %r14
+  ret <2 x double> <double 0x3ff0000000000000, double 0x3ff0000000000000>
+}
+
+; Test a doubleword-granularity replicate with a wrap-around mask.
+define <2 x double> @f10() {
+; CHECK-LABEL: f10:
+; CHECK: vgmg %v24, 10, 0
+; CHECK: br %r14
+  ret <2 x double> <double 0x803fffffffffffff, double 0x803fffffffffffff>
+}
diff --git a/test/CodeGen/SystemZ/vec-conv-01.ll b/test/CodeGen/SystemZ/vec-conv-01.ll
new file mode 100644
index 000000000000..cbf42c0f533e
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-conv-01.ll
@@ -0,0 +1,95 @@
+; Test conversions between integer and float elements.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test conversion of f64s to signed i64s.
+define <2 x i64> @f1(<2 x double> %doubles) {
+; CHECK-LABEL: f1:
+; CHECK: vcgdb %v24, %v24, 0, 5
+; CHECK: br %r14
+  %dwords = fptosi <2 x double> %doubles to <2 x i64>
+  ret <2 x i64> %dwords
+}
+
+; Test conversion of f64s to unsigned i64s.
+define <2 x i64> @f2(<2 x double> %doubles) {
+; CHECK-LABEL: f2:
+; CHECK: vclgdb %v24, %v24, 0, 5
+; CHECK: br %r14
+  %dwords = fptoui <2 x double> %doubles to <2 x i64>
+  ret <2 x i64> %dwords
+}
+
+; Test conversion of signed i64s to f64s.
+define <2 x double> @f3(<2 x i64> %dwords) {
+; CHECK-LABEL: f3:
+; CHECK: vcdgb %v24, %v24, 0, 0
+; CHECK: br %r14
+  %doubles = sitofp <2 x i64> %dwords to <2 x double>
+  ret <2 x double> %doubles
+}
+
+; Test conversion of unsigned i64s to f64s.
+define <2 x double> @f4(<2 x i64> %dwords) {
+; CHECK-LABEL: f4:
+; CHECK: vcdlgb %v24, %v24, 0, 0
+; CHECK: br %r14
+  %doubles = uitofp <2 x i64> %dwords to <2 x double>
+  ret <2 x double> %doubles
+}
+
+; Test conversion of f64s to signed i32s, which must compile.
+define void @f5(<2 x double> %doubles, <2 x i32> *%ptr) {
+  %words = fptosi <2 x double> %doubles to <2 x i32>
+  store <2 x i32> %words, <2 x i32> *%ptr
+  ret void
+}
+
+; Test conversion of f64s to unsigned i32s, which must compile.
+define void @f6(<2 x double> %doubles, <2 x i32> *%ptr) {
+  %words = fptoui <2 x double> %doubles to <2 x i32>
+  store <2 x i32> %words, <2 x i32> *%ptr
+  ret void
+}
+
+; Test conversion of signed i32s to f64s, which must compile.
+define <2 x double> @f7(<2 x i32> *%ptr) {
+  %words = load <2 x i32>, <2 x i32> *%ptr
+  %doubles = sitofp <2 x i32> %words to <2 x double>
+  ret <2 x double> %doubles
+}
+
+; Test conversion of unsigned i32s to f64s, which must compile.
+define <2 x double> @f8(<2 x i32> *%ptr) {
+  %words = load <2 x i32>, <2 x i32> *%ptr
+  %doubles = uitofp <2 x i32> %words to <2 x double>
+  ret <2 x double> %doubles
+}
+
+; Test conversion of f32s to signed i64s, which must compile.
+define <2 x i64> @f9(<2 x float> *%ptr) {
+  %floats = load <2 x float>, <2 x float> *%ptr
+  %dwords = fptosi <2 x float> %floats to <2 x i64>
+  ret <2 x i64> %dwords
+}
+
+; Test conversion of f32s to unsigned i64s, which must compile.
+define <2 x i64> @f10(<2 x float> *%ptr) {
+  %floats = load <2 x float>, <2 x float> *%ptr
+  %dwords = fptoui <2 x float> %floats to <2 x i64>
+  ret <2 x i64> %dwords
+}
+
+; Test conversion of signed i64s to f32, which must compile.
+define void @f11(<2 x i64> %dwords, <2 x float> *%ptr) {
+  %floats = sitofp <2 x i64> %dwords to <2 x float>
+  store <2 x float> %floats, <2 x float> *%ptr
+  ret void
+}
+
+; Test conversion of unsigned i64s to f32, which must compile.
+define void @f12(<2 x i64> %dwords, <2 x float> *%ptr) {
+  %floats = uitofp <2 x i64> %dwords to <2 x float>
+  store <2 x float> %floats, <2 x float> *%ptr
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/vec-conv-02.ll b/test/CodeGen/SystemZ/vec-conv-02.ll
new file mode 100644
index 000000000000..ab84389f3c8e
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-conv-02.ll
@@ -0,0 +1,33 @@
+; Test conversions between different-sized float elements.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test cases where both elements of a v2f64 are converted to f32s.
+define void @f1(<2 x double> %val, <2 x float> *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: vledb {{%v[0-9]+}}, %v24, 0, 0
+; CHECK: br %r14
+  %res = fptrunc <2 x double> %val to <2 x float>
+  store <2 x float> %res, <2 x float> *%ptr
+  ret void
+}
+
+; Test conversion of an f64 in a vector register to an f32.
+define float @f2(<2 x double> %vec) {
+; CHECK-LABEL: f2:
+; CHECK: wledb %f0, %v24
+; CHECK: br %r14
+  %scalar = extractelement <2 x double> %vec, i32 0
+  %ret = fptrunc double %scalar to float
+  ret float %ret
+}
+
+; Test conversion of an f32 in a vector register to an f64.
+define double @f3(<4 x float> %vec) {
+; CHECK-LABEL: f3:
+; CHECK: wldeb %f0, %v24
+; CHECK: br %r14
+  %scalar = extractelement <4 x float> %vec, i32 0
+  %ret = fpext float %scalar to double
+  ret double %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-ctlz-01.ll b/test/CodeGen/SystemZ/vec-ctlz-01.ll
new file mode 100644
index 000000000000..f6502202ef58
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-ctlz-01.ll
@@ -0,0 +1,81 @@
+; Test vector count leading zeros
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 %is_zero_undef)
+declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 %is_zero_undef)
+declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 %is_zero_undef)
+declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 %is_zero_undef)
+
+define <16 x i8> @f1(<16 x i8> %a) {
+; CHECK-LABEL: f1:
+; CHECK: vclzb %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @f2(<16 x i8> %a) {
+; CHECK-LABEL: f2:
+; CHECK: vclzb %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 true)
+  ret <16 x i8> %res
+}
+
+define <8 x i16> @f3(<8 x i16> %a) {
+; CHECK-LABEL: f3:
+; CHECK: vclzh %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 false)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @f4(<8 x i16> %a) {
+; CHECK-LABEL: f4:
+; CHECK: vclzh %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 true)
+  ret <8 x i16> %res
+}
+
+define <4 x i32> @f5(<4 x i32> %a) {
+; CHECK-LABEL: f5:
+; CHECK: vclzf %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @f6(<4 x i32> %a) {
+; CHECK-LABEL: f6:
+; CHECK: vclzf %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 true)
+  ret <4 x i32> %res
+}
+
+define <2 x i64> @f7(<2 x i64> %a) {
+; CHECK-LABEL: f7:
+; CHECK: vclzg %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 false)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @f8(<2 x i64> %a) {
+; CHECK-LABEL: f8:
+; CHECK: vclzg %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 true)
+  ret <2 x i64> %res
+}
+
diff --git a/test/CodeGen/SystemZ/vec-ctpop-01.ll b/test/CodeGen/SystemZ/vec-ctpop-01.ll
new file mode 100644
index 000000000000..0056af73a2e1
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-ctpop-01.ll
@@ -0,0 +1,53 @@
+; Test vector population-count instruction
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %a)
+declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %a)
+declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %a)
+declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)
+
+define <16 x i8> @f1(<16 x i8> %a) {
+; CHECK-LABEL: f1:
+; CHECK: vpopct  %v24, %v24, 0
+; CHECK: br      %r14
+
+  %popcnt = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %a)
+  ret <16 x i8> %popcnt
+}
+
+define <8 x i16> @f2(<8 x i16> %a) {
+; CHECK-LABEL: f2:
+; CHECK: vpopct  [[T1:%v[0-9]+]], %v24, 0
+; CHECK: veslh   [[T2:%v[0-9]+]], [[T1]], 8
+; CHECK: vah     [[T3:%v[0-9]+]], [[T1]], [[T2]]
+; CHECK: vesrlh  %v24, [[T3]], 8
+; CHECK: br      %r14
+
+  %popcnt = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %a)
+  ret <8 x i16> %popcnt
+}
+
+define <4 x i32> @f3(<4 x i32> %a) {
+; CHECK-LABEL: f3:
+; CHECK: vpopct  [[T1:%v[0-9]+]], %v24, 0
+; CHECK: vgbm    [[T2:%v[0-9]+]], 0
+; CHECK: vsumb   %v24, [[T1]], [[T2]]
+; CHECK: br      %r14
+
+  %popcnt = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %a)
+  ret <4 x i32> %popcnt
+}
+
+define <2 x i64> @f4(<2 x i64> %a) {
+; CHECK-LABEL: f4:
+; CHECK: vpopct  [[T1:%v[0-9]+]], %v24, 0
+; CHECK: vgbm    [[T2:%v[0-9]+]], 0
+; CHECK: vsumb   [[T3:%v[0-9]+]], [[T1]], [[T2]]
+; CHECK: vsumgf  %v24, [[T3]], [[T2]]
+; CHECK: br      %r14
+
+  %popcnt = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)
+  ret <2 x i64> %popcnt
+}
+
diff --git a/test/CodeGen/SystemZ/vec-cttz-01.ll b/test/CodeGen/SystemZ/vec-cttz-01.ll
new file mode 100644
index 000000000000..00a0d21b42fe
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-cttz-01.ll
@@ -0,0 +1,81 @@
+; Test vector count trailing zeros
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+declare <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 %is_zero_undef)
+declare <8 x i16> @llvm.cttz.v8i16(<8 x i16> %src, i1 %is_zero_undef)
+declare <4 x i32> @llvm.cttz.v4i32(<4 x i32> %src, i1 %is_zero_undef)
+declare <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 %is_zero_undef)
+
+define <16 x i8> @f1(<16 x i8> %a) {
+; CHECK-LABEL: f1:
+; CHECK: vctzb %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %a, i1 false)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @f2(<16 x i8> %a) {
+; CHECK-LABEL: f2:
+; CHECK: vctzb %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %a, i1 true)
+  ret <16 x i8> %res
+}
+
+define <8 x i16> @f3(<8 x i16> %a) {
+; CHECK-LABEL: f3:
+; CHECK: vctzh %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %a, i1 false)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @f4(<8 x i16> %a) {
+; CHECK-LABEL: f4:
+; CHECK: vctzh %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %a, i1 true)
+  ret <8 x i16> %res
+}
+
+define <4 x i32> @f5(<4 x i32> %a) {
+; CHECK-LABEL: f5:
+; CHECK: vctzf %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 false)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @f6(<4 x i32> %a) {
+; CHECK-LABEL: f6:
+; CHECK: vctzf %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 true)
+  ret <4 x i32> %res
+}
+
+define <2 x i64> @f7(<2 x i64> %a) {
+; CHECK-LABEL: f7:
+; CHECK: vctzg %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 false)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @f8(<2 x i64> %a) {
+; CHECK-LABEL: f8:
+; CHECK: vctzg %v24, %v24
+; CHECK: br    %r14
+
+  %res = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 true)
+  ret <2 x i64> %res
+}
+
diff --git a/test/CodeGen/SystemZ/vec-div-01.ll b/test/CodeGen/SystemZ/vec-div-01.ll
new file mode 100644
index 000000000000..506d40861d35
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-div-01.ll
@@ -0,0 +1,83 @@
+; Test vector division.  There is no native integer support for this,
+; so the integer cases are really a test of the operation legalization code.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 division.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vlvgp [[REG:%v[0-9]+]],
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 0
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 1
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 2
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 3
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 4
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 5
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 6
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 8
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 9
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 10
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 11
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 12
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 13
+; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 14
+; CHECK: br %r14
+  %ret = sdiv <16 x i8> %val1, %val2
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 division.
+define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vlvgp [[REG:%v[0-9]+]],
+; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 0
+; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 1
+; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 2
+; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 4
+; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 5
+; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 6
+; CHECK: br %r14
+  %ret = sdiv <8 x i16> %val1, %val2
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 division.
+define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vlvgp [[REG:%v[0-9]+]],
+; CHECK-DAG: vlvgf [[REG]], {{%r[0-5]}}, 0
+; CHECK-DAG: vlvgf [[REG]], {{%r[0-5]}}, 2
+; CHECK: br %r14
+  %ret = sdiv <4 x i32> %val1, %val2
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 division.
+define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vlvgp %v24,
+; CHECK: br %r14
+  %ret = sdiv <2 x i64> %val1, %val2
+  ret <2 x i64> %ret
+}
+
+; Test a v2f64 division.
+define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1,
+                        <2 x double> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vfddb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = fdiv <2 x double> %val1, %val2
+  ret <2 x double> %ret
+}
+
+; Test an f64 division that uses vector registers.
+define double @f6(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: wfddb %f0, %v24, %v26
+; CHECK: br %r14
+  %scalar1 = extractelement <2 x double> %val1, i32 0
+  %scalar2 = extractelement <2 x double> %val2, i32 0
+  %ret = fdiv double %scalar1, %scalar2
+  ret double %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-extract-01.ll b/test/CodeGen/SystemZ/vec-extract-01.ll
new file mode 100644
index 000000000000..549392ffd64d
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-extract-01.ll
@@ -0,0 +1,13 @@
+; Verify ReplaceExtractVectorEltOfLoadWithNarrowedLoad fixes
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a memory copy of a v2i32 (via the constant pool).
+define void @f1(<2 x i32> *%dest) {
+; CHECK-LABEL: f1:
+; CHECK: lgrl [[REG:%r[0-5]]], {{[._A-Za-z0-9]}}
+; CHECK: stg [[REG]], 0(%r2)
+; CHECK: br %r14
+  store <2 x i32> <i32 1000000, i32 99999>, <2 x i32> *%dest
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/vec-extract-02.ll b/test/CodeGen/SystemZ/vec-extract-02.ll
new file mode 100644
index 000000000000..c91e852fcf45
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-extract-02.ll
@@ -0,0 +1,15 @@
+; Verify ReplaceExtractVectorEltOfLoadWithNarrowedLoad fixes
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a case where a vector extraction can be simplified to a scalar load.
+; The index must be extended from i32 to i64.
+define i32 @f1(<4 x i32> *%ptr, i32 %index) {
+; CHECK-LABEL: f1:
+; CHECK: risbg {{%r[0-5]}}, %r3, 30, 189, 2
+; CHECK: l %r2,
+; CHECK: br %r14
+  %vec = load <4 x i32>, <4 x i32> *%ptr
+  %res = extractelement <4 x i32> %vec, i32 %index
+  ret i32 %res
+}
diff --git a/test/CodeGen/SystemZ/vec-intrinsics.ll b/test/CodeGen/SystemZ/vec-intrinsics.ll
new file mode 100644
index 000000000000..55527787da4c
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-intrinsics.ll
@@ -0,0 +1,3335 @@
+; Test vector intrinsics.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+declare i32 @llvm.s390.lcbb(i8 *, i32)
+declare <16 x i8> @llvm.s390.vlbb(i8 *, i32)
+declare <16 x i8> @llvm.s390.vll(i32, i8 *)
+declare <2 x i64> @llvm.s390.vpdi(<2 x i64>, <2 x i64>, i32)
+declare <16 x i8> @llvm.s390.vperm(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.s390.vpksh(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.s390.vpksf(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.s390.vpksg(<2 x i64>, <2 x i64>)
+declare {<16 x i8>, i32} @llvm.s390.vpkshs(<8 x i16>, <8 x i16>)
+declare {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32>, <4 x i32>)
+declare {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64>, <2 x i64>)
+declare <16 x i8> @llvm.s390.vpklsh(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.s390.vpklsf(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.s390.vpklsg(<2 x i64>, <2 x i64>)
+declare {<16 x i8>, i32} @llvm.s390.vpklshs(<8 x i16>, <8 x i16>)
+declare {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32>, <4 x i32>)
+declare {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64>, <2 x i64>)
+declare void @llvm.s390.vstl(<16 x i8>, i32, i8 *)
+declare <8 x i16> @llvm.s390.vuphb(<16 x i8>)
+declare <4 x i32> @llvm.s390.vuphh(<8 x i16>)
+declare <2 x i64> @llvm.s390.vuphf(<4 x i32>)
+declare <8 x i16> @llvm.s390.vuplhb(<16 x i8>)
+declare <4 x i32> @llvm.s390.vuplhh(<8 x i16>)
+declare <2 x i64> @llvm.s390.vuplhf(<4 x i32>)
+declare <8 x i16> @llvm.s390.vuplb(<16 x i8>)
+declare <4 x i32> @llvm.s390.vuplhw(<8 x i16>)
+declare <2 x i64> @llvm.s390.vuplf(<4 x i32>)
+declare <8 x i16> @llvm.s390.vupllb(<16 x i8>)
+declare <4 x i32> @llvm.s390.vupllh(<8 x i16>)
+declare <2 x i64> @llvm.s390.vupllf(<4 x i32>)
+declare <16 x i8> @llvm.s390.vaccb(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.s390.vacch(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vaccf(<4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.s390.vaccg(<2 x i64>, <2 x i64>)
+declare <16 x i8> @llvm.s390.vaq(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.s390.vacq(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.s390.vaccq(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.s390.vacccq(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.s390.vavgb(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.s390.vavgh(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vavgf(<4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.s390.vavgg(<2 x i64>, <2 x i64>)
+declare <16 x i8> @llvm.s390.vavglb(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.s390.vavglh(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vavglf(<4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.s390.vavglg(<2 x i64>, <2 x i64>)
+declare <4 x i32> @llvm.s390.vcksm(<4 x i32>, <4 x i32>)
+declare <8 x i16> @llvm.s390.vgfmb(<16 x i8>, <16 x i8>)
+declare <4 x i32> @llvm.s390.vgfmh(<8 x i16>, <8 x i16>)
+declare <2 x i64> @llvm.s390.vgfmf(<4 x i32>, <4 x i32>)
+declare <16 x i8> @llvm.s390.vgfmg(<2 x i64>, <2 x i64>)
+declare <8 x i16> @llvm.s390.vgfmab(<16 x i8>, <16 x i8>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vgfmah(<8 x i16>, <8 x i16>, <4 x i32>)
+declare <2 x i64> @llvm.s390.vgfmaf(<4 x i32>, <4 x i32>, <2 x i64>)
+declare <16 x i8> @llvm.s390.vgfmag(<2 x i64>, <2 x i64>, <16 x i8>)
+declare <16 x i8> @llvm.s390.vmahb(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.s390.vmahh(<8 x i16>, <8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vmahf(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <16 x i8> @llvm.s390.vmalhb(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.s390.vmalhh(<8 x i16>, <8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vmalhf(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <8 x i16> @llvm.s390.vmaeb(<16 x i8>, <16 x i8>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vmaeh(<8 x i16>, <8 x i16>, <4 x i32>)
+declare <2 x i64> @llvm.s390.vmaef(<4 x i32>, <4 x i32>, <2 x i64>)
+declare <8 x i16> @llvm.s390.vmaleb(<16 x i8>, <16 x i8>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vmaleh(<8 x i16>, <8 x i16>, <4 x i32>)
+declare <2 x i64> @llvm.s390.vmalef(<4 x i32>, <4 x i32>, <2 x i64>)
+declare <8 x i16> @llvm.s390.vmaob(<16 x i8>, <16 x i8>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vmaoh(<8 x i16>, <8 x i16>, <4 x i32>)
+declare <2 x i64> @llvm.s390.vmaof(<4 x i32>, <4 x i32>, <2 x i64>)
+declare <8 x i16> @llvm.s390.vmalob(<16 x i8>, <16 x i8>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vmaloh(<8 x i16>, <8 x i16>, <4 x i32>)
+declare <2 x i64> @llvm.s390.vmalof(<4 x i32>, <4 x i32>, <2 x i64>)
+declare <16 x i8> @llvm.s390.vmhb(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.s390.vmhh(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vmhf(<4 x i32>, <4 x i32>)
+declare <16 x i8> @llvm.s390.vmlhb(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.s390.vmlhh(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vmlhf(<4 x i32>, <4 x i32>)
+declare <8 x i16> @llvm.s390.vmeb(<16 x i8>, <16 x i8>)
+declare <4 x i32> @llvm.s390.vmeh(<8 x i16>, <8 x i16>)
+declare <2 x i64> @llvm.s390.vmef(<4 x i32>, <4 x i32>)
+declare <8 x i16> @llvm.s390.vmleb(<16 x i8>, <16 x i8>)
+declare <4 x i32> @llvm.s390.vmleh(<8 x i16>, <8 x i16>)
+declare <2 x i64> @llvm.s390.vmlef(<4 x i32>, <4 x i32>)
+declare <8 x i16> @llvm.s390.vmob(<16 x i8>, <16 x i8>)
+declare <4 x i32> @llvm.s390.vmoh(<8 x i16>, <8 x i16>)
+declare <2 x i64> @llvm.s390.vmof(<4 x i32>, <4 x i32>)
+declare <8 x i16> @llvm.s390.vmlob(<16 x i8>, <16 x i8>)
+declare <4 x i32> @llvm.s390.vmloh(<8 x i16>, <8 x i16>)
+declare <2 x i64> @llvm.s390.vmlof(<4 x i32>, <4 x i32>)
+declare <16 x i8> @llvm.s390.verllvb(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.s390.verllvh(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.s390.verllvf(<4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.s390.verllvg(<2 x i64>, <2 x i64>)
+declare <16 x i8> @llvm.s390.verllb(<16 x i8>, i32)
+declare <8 x i16> @llvm.s390.verllh(<8 x i16>, i32)
+declare <4 x i32> @llvm.s390.verllf(<4 x i32>, i32)
+declare <2 x i64> @llvm.s390.verllg(<2 x i64>, i32)
+declare <16 x i8> @llvm.s390.verimb(<16 x i8>, <16 x i8>, <16 x i8>, i32)
+declare <8 x i16> @llvm.s390.verimh(<8 x i16>, <8 x i16>, <8 x i16>, i32)
+declare <4 x i32> @llvm.s390.verimf(<4 x i32>, <4 x i32>, <4 x i32>, i32)
+declare <2 x i64> @llvm.s390.verimg(<2 x i64>, <2 x i64>, <2 x i64>, i32)
+declare <16 x i8> @llvm.s390.vsl(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.s390.vslb(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.s390.vsra(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.s390.vsrab(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.s390.vsrl(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.s390.vsrlb(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.s390.vsldb(<16 x i8>, <16 x i8>, i32)
+declare <16 x i8> @llvm.s390.vscbib(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.s390.vscbih(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vscbif(<4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.s390.vscbig(<2 x i64>, <2 x i64>)
+declare <16 x i8> @llvm.s390.vsq(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.s390.vsbiq(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.s390.vscbiq(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.s390.vsbcbiq(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <4 x i32> @llvm.s390.vsumb(<16 x i8>, <16 x i8>)
+declare <4 x i32> @llvm.s390.vsumh(<8 x i16>, <8 x i16>)
+declare <2 x i64> @llvm.s390.vsumgh(<8 x i16>, <8 x i16>)
+declare <2 x i64> @llvm.s390.vsumgf(<4 x i32>, <4 x i32>)
+declare <16 x i8> @llvm.s390.vsumqf(<4 x i32>, <4 x i32>)
+declare <16 x i8> @llvm.s390.vsumqg(<2 x i64>, <2 x i64>)
+declare i32 @llvm.s390.vtm(<16 x i8>, <16 x i8>)
+declare {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8>, <16 x i8>)
+declare {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16>, <8 x i16>)
+declare {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32>, <4 x i32>)
+declare {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64>, <2 x i64>)
+declare {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8>, <16 x i8>)
+declare {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16>, <8 x i16>)
+declare {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32>, <4 x i32>)
+declare {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64>, <2 x i64>)
+declare {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8>, <16 x i8>)
+declare {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16>, <8 x i16>)
+declare {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32>, <4 x i32>)
+declare {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64>, <2 x i64>)
+declare <16 x i8> @llvm.s390.vfaeb(<16 x i8>, <16 x i8>, i32)
+declare <8 x i16> @llvm.s390.vfaeh(<8 x i16>, <8 x i16>, i32)
+declare <4 x i32> @llvm.s390.vfaef(<4 x i32>, <4 x i32>, i32)
+declare {<16 x i8>, i32} @llvm.s390.vfaebs(<16 x i8>, <16 x i8>, i32)
+declare {<8 x i16>, i32} @llvm.s390.vfaehs(<8 x i16>, <8 x i16>, i32)
+declare {<4 x i32>, i32} @llvm.s390.vfaefs(<4 x i32>, <4 x i32>, i32)
+declare <16 x i8> @llvm.s390.vfaezb(<16 x i8>, <16 x i8>, i32)
+declare <8 x i16> @llvm.s390.vfaezh(<8 x i16>, <8 x i16>, i32)
+declare <4 x i32> @llvm.s390.vfaezf(<4 x i32>, <4 x i32>, i32)
+declare {<16 x i8>, i32} @llvm.s390.vfaezbs(<16 x i8>, <16 x i8>, i32)
+declare {<8 x i16>, i32} @llvm.s390.vfaezhs(<8 x i16>, <8 x i16>, i32)
+declare {<4 x i32>, i32} @llvm.s390.vfaezfs(<4 x i32>, <4 x i32>, i32)
+declare <16 x i8> @llvm.s390.vfeeb(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.s390.vfeeh(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vfeef(<4 x i32>, <4 x i32>)
+declare {<16 x i8>, i32} @llvm.s390.vfeebs(<16 x i8>, <16 x i8>)
+declare {<8 x i16>, i32} @llvm.s390.vfeehs(<8 x i16>, <8 x i16>)
+declare {<4 x i32>, i32} @llvm.s390.vfeefs(<4 x i32>, <4 x i32>)
+declare <16 x i8> @llvm.s390.vfeezb(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.s390.vfeezh(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vfeezf(<4 x i32>, <4 x i32>)
+declare {<16 x i8>, i32} @llvm.s390.vfeezbs(<16 x i8>, <16 x i8>)
+declare {<8 x i16>, i32} @llvm.s390.vfeezhs(<8 x i16>, <8 x i16>)
+declare {<4 x i32>, i32} @llvm.s390.vfeezfs(<4 x i32>, <4 x i32>)
+declare <16 x i8> @llvm.s390.vfeneb(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.s390.vfeneh(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vfenef(<4 x i32>, <4 x i32>)
+declare {<16 x i8>, i32} @llvm.s390.vfenebs(<16 x i8>, <16 x i8>)
+declare {<8 x i16>, i32} @llvm.s390.vfenehs(<8 x i16>, <8 x i16>)
+declare {<4 x i32>, i32} @llvm.s390.vfenefs(<4 x i32>, <4 x i32>)
+declare <16 x i8> @llvm.s390.vfenezb(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.s390.vfenezh(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.s390.vfenezf(<4 x i32>, <4 x i32>)
+declare {<16 x i8>, i32} @llvm.s390.vfenezbs(<16 x i8>, <16 x i8>)
+declare {<8 x i16>, i32} @llvm.s390.vfenezhs(<8 x i16>, <8 x i16>)
+declare {<4 x i32>, i32} @llvm.s390.vfenezfs(<4 x i32>, <4 x i32>)
+declare <16 x i8> @llvm.s390.vistrb(<16 x i8>)
+declare <8 x i16> @llvm.s390.vistrh(<8 x i16>)
+declare <4 x i32> @llvm.s390.vistrf(<4 x i32>)
+declare {<16 x i8>, i32} @llvm.s390.vistrbs(<16 x i8>)
+declare {<8 x i16>, i32} @llvm.s390.vistrhs(<8 x i16>)
+declare {<4 x i32>, i32} @llvm.s390.vistrfs(<4 x i32>)
+declare <16 x i8> @llvm.s390.vstrcb(<16 x i8>, <16 x i8>, <16 x i8>, i32)
+declare <8 x i16> @llvm.s390.vstrch(<8 x i16>, <8 x i16>, <8 x i16>, i32)
+declare <4 x i32> @llvm.s390.vstrcf(<4 x i32>, <4 x i32>, <4 x i32>, i32)
+declare {<16 x i8>, i32} @llvm.s390.vstrcbs(<16 x i8>, <16 x i8>, <16 x i8>,
+                                            i32)
+declare {<8 x i16>, i32} @llvm.s390.vstrchs(<8 x i16>, <8 x i16>, <8 x i16>,
+                                            i32)
+declare {<4 x i32>, i32} @llvm.s390.vstrcfs(<4 x i32>, <4 x i32>, <4 x i32>,
+                                            i32)
+declare <16 x i8> @llvm.s390.vstrczb(<16 x i8>, <16 x i8>, <16 x i8>, i32)
+declare <8 x i16> @llvm.s390.vstrczh(<8 x i16>, <8 x i16>, <8 x i16>, i32)
+declare <4 x i32> @llvm.s390.vstrczf(<4 x i32>, <4 x i32>, <4 x i32>, i32)
+declare {<16 x i8>, i32} @llvm.s390.vstrczbs(<16 x i8>, <16 x i8>, <16 x i8>,
+                                             i32)
+declare {<8 x i16>, i32} @llvm.s390.vstrczhs(<8 x i16>, <8 x i16>, <8 x i16>,
+                                             i32)
+declare {<4 x i32>, i32} @llvm.s390.vstrczfs(<4 x i32>, <4 x i32>, <4 x i32>,
+                                             i32)
+declare {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double>, <2 x double>)
+declare {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double>, <2 x double>)
+declare {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double>, <2 x double>)
+declare {<2 x i64>, i32} @llvm.s390.vftcidb(<2 x double>, i32)
+declare <2 x double> @llvm.s390.vfidb(<2 x double>, i32, i32)
+
+; LCBB with the lowest M3 operand.
+define i32 @test_lcbb1(i8 *%ptr) {
+; CHECK-LABEL: test_lcbb1:
+; CHECK: lcbb %r2, 0(%r2), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.lcbb(i8 *%ptr, i32 0)
+  ret i32 %res
+}
+
+; LCBB with the highest M3 operand.
+define i32 @test_lcbb2(i8 *%ptr) {
+; CHECK-LABEL: test_lcbb2:
+; CHECK: lcbb %r2, 0(%r2), 15
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.lcbb(i8 *%ptr, i32 15)
+  ret i32 %res
+}
+
+; LCBB with a displacement and index.
+define i32 @test_lcbb3(i8 *%base, i64 %index) {
+; CHECK-LABEL: test_lcbb3:
+; CHECK: lcbb %r2, 4095({{%r2,%r3|%r3,%r2}}), 4
+; CHECK: br %r14
+  %add = add i64 %index, 4095
+  %ptr = getelementptr i8, i8 *%base, i64 %add
+  %res = call i32 @llvm.s390.lcbb(i8 *%ptr, i32 4)
+  ret i32 %res
+}
+
+; LCBB with an out-of-range displacement.
+define i32 @test_lcbb4(i8 *%base) {
+; CHECK-LABEL: test_lcbb4:
+; CHECK: lcbb %r2, 0({{%r[1-5]}}), 5
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i64 4096
+  %res = call i32 @llvm.s390.lcbb(i8 *%ptr, i32 5)
+  ret i32 %res
+}
+
+; VLBB with the lowest M3 operand.
+define <16 x i8> @test_vlbb1(i8 *%ptr) {
+; CHECK-LABEL: test_vlbb1:
+; CHECK: vlbb %v24, 0(%r2), 0
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vlbb(i8 *%ptr, i32 0)
+  ret <16 x i8> %res
+}
+
+; VLBB with the highest M3 operand.
+define <16 x i8> @test_vlbb2(i8 *%ptr) {
+; CHECK-LABEL: test_vlbb2:
+; CHECK: vlbb %v24, 0(%r2), 15
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vlbb(i8 *%ptr, i32 15)
+  ret <16 x i8> %res
+}
+
+; VLBB with a displacement and index.
+define <16 x i8> @test_vlbb3(i8 *%base, i64 %index) {
+; CHECK-LABEL: test_vlbb3:
+; CHECK: vlbb %v24, 4095({{%r2,%r3|%r3,%r2}}), 4
+; CHECK: br %r14
+  %add = add i64 %index, 4095
+  %ptr = getelementptr i8, i8 *%base, i64 %add
+  %res = call <16 x i8> @llvm.s390.vlbb(i8 *%ptr, i32 4)
+  ret <16 x i8> %res
+}
+
+; VLBB with an out-of-range displacement.
+define <16 x i8> @test_vlbb4(i8 *%base) {
+; CHECK-LABEL: test_vlbb4:
+; CHECK: vlbb %v24, 0({{%r[1-5]}}), 5
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i64 4096
+  %res = call <16 x i8> @llvm.s390.vlbb(i8 *%ptr, i32 5)
+  ret <16 x i8> %res
+}
+
+; VLL with the lowest in-range displacement.
+define <16 x i8> @test_vll1(i8 *%ptr, i32 %length) {
+; CHECK-LABEL: test_vll1:
+; CHECK: vll %v24, %r3, 0(%r2)
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vll(i32 %length, i8 *%ptr)
+  ret <16 x i8> %res
+}
+
+; VLL with the highest in-range displacement.
+define <16 x i8> @test_vll2(i8 *%base, i32 %length) {
+; CHECK-LABEL: test_vll2:
+; CHECK: vll %v24, %r3, 4095(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i64 4095
+  %res = call <16 x i8> @llvm.s390.vll(i32 %length, i8 *%ptr)
+  ret <16 x i8> %res
+}
+
+; VLL with an out-of-range displacementa.
+define <16 x i8> @test_vll3(i8 *%base, i32 %length) {
+; CHECK-LABEL: test_vll3:
+; CHECK: vll %v24, %r3, 0({{%r[1-5]}})
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i64 4096
+  %res = call <16 x i8> @llvm.s390.vll(i32 %length, i8 *%ptr)
+  ret <16 x i8> %res
+}
+
+; Check that VLL doesn't allow an index.
+define <16 x i8> @test_vll4(i8 *%base, i64 %index, i32 %length) {
+; CHECK-LABEL: test_vll4:
+; CHECK: vll %v24, %r4, 0({{%r[1-5]}})
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i64 %index
+  %res = call <16 x i8> @llvm.s390.vll(i32 %length, i8 *%ptr)
+  ret <16 x i8> %res
+}
+
+; VPDI taking element 0 from each half.
+define <2 x i64> @test_vpdi1(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vpdi1:
+; CHECK: vpdi %v24, %v24, %v26, 0
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vpdi(<2 x i64> %a, <2 x i64> %b, i32 0)
+  ret <2 x i64> %res
+}
+
+; VPDI taking element 1 from each half.
+define <2 x i64> @test_vpdi2(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vpdi2:
+; CHECK: vpdi %v24, %v24, %v26, 10
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vpdi(<2 x i64> %a, <2 x i64> %b, i32 10)
+  ret <2 x i64> %res
+}
+
+; VPERM.
+define <16 x i8> @test_vperm(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vperm:
+; CHECK: vperm %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vperm(<16 x i8> %a, <16 x i8> %b,
+                                         <16 x i8> %c)
+  ret <16 x i8> %res
+}
+
+; VPKSH.
+define <16 x i8> @test_vpksh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vpksh:
+; CHECK: vpksh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vpksh(<8 x i16> %a, <8 x i16> %b)
+  ret <16 x i8> %res
+}
+
+; VPKSF.
+define <8 x i16> @test_vpksf(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vpksf:
+; CHECK: vpksf %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vpksf(<4 x i32> %a, <4 x i32> %b)
+  ret <8 x i16> %res
+}
+
+; VPKSG.
+define <4 x i32> @test_vpksg(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vpksg:
+; CHECK: vpksg %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vpksg(<2 x i64> %a, <2 x i64> %b)
+  ret <4 x i32> %res
+}
+
+; VPKSHS with no processing of the result.
+define <16 x i8> @test_vpkshs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vpkshs:
+; CHECK: vpkshs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vpkshs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <16 x i8> %res
+}
+
+; VPKSHS, storing to %ptr if all values were saturated.
+define <16 x i8> @test_vpkshs_all_store(<8 x i16> %a, <8 x i16> %b, i32 *%ptr) {
+; CHECK-LABEL: test_vpkshs_all_store:
+; CHECK: vpkshs %v24, %v24, %v26
+; CHECK-NEXT: {{jno|jle}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vpkshs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  %cmp = icmp uge i32 %cc, 3
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <16 x i8> %res
+}
+
+; VPKSFS with no processing of the result.
+define <8 x i16> @test_vpksfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vpksfs:
+; CHECK: vpksfs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <8 x i16> %res
+}
+
+; VPKSFS, storing to %ptr if any values were saturated.
+define <8 x i16> @test_vpksfs_any_store(<4 x i32> %a, <4 x i32> %b, i32 *%ptr) {
+; CHECK-LABEL: test_vpksfs_any_store:
+; CHECK: vpksfs %v24, %v24, %v26
+; CHECK-NEXT: {{jhe|je}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  %cmp = icmp ugt i32 %cc, 0
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <8 x i16> %res
+}
+
+; VPKSGS with no processing of the result.
+define <4 x i32> @test_vpksgs(<2 x i64> %a, <2 x i64> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vpksgs:
+; CHECK: vpksgs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64> %a, <2 x i64> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <4 x i32> %res
+}
+
+; VPKSGS, storing to %ptr if no elements were saturated
+define <4 x i32> @test_vpksgs_none_store(<2 x i64> %a, <2 x i64> %b,
+                                         i32 *%ptr) {
+; CHECK-LABEL: test_vpksgs_none_store:
+; CHECK: vpksgs %v24, %v24, %v26
+; CHECK-NEXT: {{jnhe|jne}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64> %a, <2 x i64> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  %cmp = icmp sle i32 %cc, 0
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <4 x i32> %res
+}
+
+; VPKLSH.
+define <16 x i8> @test_vpklsh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vpklsh:
+; CHECK: vpklsh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vpklsh(<8 x i16> %a, <8 x i16> %b)
+  ret <16 x i8> %res
+}
+
+; VPKLSF.
+define <8 x i16> @test_vpklsf(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vpklsf:
+; CHECK: vpklsf %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vpklsf(<4 x i32> %a, <4 x i32> %b)
+  ret <8 x i16> %res
+}
+
+; VPKLSG.
+define <4 x i32> @test_vpklsg(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vpklsg:
+; CHECK: vpklsg %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vpklsg(<2 x i64> %a, <2 x i64> %b)
+  ret <4 x i32> %res
+}
+
+; VPKLSHS with no processing of the result.
+define <16 x i8> @test_vpklshs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vpklshs:
+; CHECK: vpklshs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vpklshs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <16 x i8> %res
+}
+
+; VPKLSHS, storing to %ptr if all values were saturated.
+define <16 x i8> @test_vpklshs_all_store(<8 x i16> %a, <8 x i16> %b,
+                                         i32 *%ptr) {
+; CHECK-LABEL: test_vpklshs_all_store:
+; CHECK: vpklshs %v24, %v24, %v26
+; CHECK-NEXT: {{jno|jle}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vpklshs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  %cmp = icmp eq i32 %cc, 3
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <16 x i8> %res
+}
+
+; VPKLSFS with no processing of the result.
+define <8 x i16> @test_vpklsfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vpklsfs:
+; CHECK: vpklsfs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <8 x i16> %res
+}
+
+; VPKLSFS, storing to %ptr if any values were saturated.
+define <8 x i16> @test_vpklsfs_any_store(<4 x i32> %a, <4 x i32> %b,
+                                         i32 *%ptr) {
+; CHECK-LABEL: test_vpklsfs_any_store:
+; CHECK: vpklsfs %v24, %v24, %v26
+; CHECK-NEXT: {{jhe|je}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  %cmp = icmp ne i32 %cc, 0
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <8 x i16> %res
+}
+
+; VPKLSGS with no processing of the result.
+define <4 x i32> @test_vpklsgs(<2 x i64> %a, <2 x i64> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vpklsgs:
+; CHECK: vpklsgs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64> %a, <2 x i64> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <4 x i32> %res
+}
+
+; VPKLSGS, storing to %ptr if no elements were saturated
+define <4 x i32> @test_vpklsgs_none_store(<2 x i64> %a, <2 x i64> %b,
+                                          i32 *%ptr) {
+; CHECK-LABEL: test_vpklsgs_none_store:
+; CHECK: vpklsgs %v24, %v24, %v26
+; CHECK-NEXT: {{jnhe|jne}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64> %a, <2 x i64> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  %cmp = icmp eq i32 %cc, 0
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <4 x i32> %res
+}
+
+; VSTL with the lowest in-range displacement.
+define void @test_vstl1(<16 x i8> %vec, i8 *%ptr, i32 %length) {
+; CHECK-LABEL: test_vstl1:
+; CHECK: vstl %v24, %r3, 0(%r2)
+; CHECK: br %r14
+  call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, i8 *%ptr)
+  ret void
+}
+
+; VSTL with the highest in-range displacement.
+define void @test_vstl2(<16 x i8> %vec, i8 *%base, i32 %length) {
+; CHECK-LABEL: test_vstl2:
+; CHECK: vstl %v24, %r3, 4095(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i64 4095
+  call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, i8 *%ptr)
+  ret void
+}
+
+; VSTL with an out-of-range displacement.
+define void @test_vstl3(<16 x i8> %vec, i8 *%base, i32 %length) {
+; CHECK-LABEL: test_vstl3:
+; CHECK: vstl %v24, %r3, 0({{%r[1-5]}})
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i64 4096
+  call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, i8 *%ptr)
+  ret void
+}
+
+; Check that VSTL doesn't allow an index.
+define void @test_vstl4(<16 x i8> %vec, i8 *%base, i64 %index, i32 %length) {
+; CHECK-LABEL: test_vstl4:
+; CHECK: vstl %v24, %r4, 0({{%r[1-5]}})
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i64 %index
+  call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, i8 *%ptr)
+  ret void
+}
+
+; VUPHB.
+define <8 x i16> @test_vuphb(<16 x i8> %a) {
+; CHECK-LABEL: test_vuphb:
+; CHECK: vuphb %v24, %v24
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vuphb(<16 x i8> %a)
+  ret <8 x i16> %res
+}
+
+; VUPHH.
+define <4 x i32> @test_vuphh(<8 x i16> %a) {
+; CHECK-LABEL: test_vuphh:
+; CHECK: vuphh %v24, %v24
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vuphh(<8 x i16> %a)
+  ret <4 x i32> %res
+}
+
+; VUPHF.
+define <2 x i64> @test_vuphf(<4 x i32> %a) {
+; CHECK-LABEL: test_vuphf:
+; CHECK: vuphf %v24, %v24
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vuphf(<4 x i32> %a)
+  ret <2 x i64> %res
+}
+
+; VUPLHB.
+define <8 x i16> @test_vuplhb(<16 x i8> %a) {
+; CHECK-LABEL: test_vuplhb:
+; CHECK: vuplhb %v24, %v24
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vuplhb(<16 x i8> %a)
+  ret <8 x i16> %res
+}
+
+; VUPLHH.
+define <4 x i32> @test_vuplhh(<8 x i16> %a) {
+; CHECK-LABEL: test_vuplhh:
+; CHECK: vuplhh %v24, %v24
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vuplhh(<8 x i16> %a)
+  ret <4 x i32> %res
+}
+
+; VUPLHF.
+define <2 x i64> @test_vuplhf(<4 x i32> %a) {
+; CHECK-LABEL: test_vuplhf:
+; CHECK: vuplhf %v24, %v24
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vuplhf(<4 x i32> %a)
+  ret <2 x i64> %res
+}
+
+; VUPLB.
+define <8 x i16> @test_vuplb(<16 x i8> %a) {
+; CHECK-LABEL: test_vuplb:
+; CHECK: vuplb %v24, %v24
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vuplb(<16 x i8> %a)
+  ret <8 x i16> %res
+}
+
+; VUPLHW.
+define <4 x i32> @test_vuplhw(<8 x i16> %a) {
+; CHECK-LABEL: test_vuplhw:
+; CHECK: vuplhw %v24, %v24
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vuplhw(<8 x i16> %a)
+  ret <4 x i32> %res
+}
+
+; VUPLF.
+define <2 x i64> @test_vuplf(<4 x i32> %a) {
+; CHECK-LABEL: test_vuplf:
+; CHECK: vuplf %v24, %v24
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vuplf(<4 x i32> %a)
+  ret <2 x i64> %res
+}
+
+; VUPLLB.
+define <8 x i16> @test_vupllb(<16 x i8> %a) {
+; CHECK-LABEL: test_vupllb:
+; CHECK: vupllb %v24, %v24
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vupllb(<16 x i8> %a)
+  ret <8 x i16> %res
+}
+
+; VUPLLH.
+define <4 x i32> @test_vupllh(<8 x i16> %a) {
+; CHECK-LABEL: test_vupllh:
+; CHECK: vupllh %v24, %v24
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vupllh(<8 x i16> %a)
+  ret <4 x i32> %res
+}
+
+; VUPLLF.
+define <2 x i64> @test_vupllf(<4 x i32> %a) {
+; CHECK-LABEL: test_vupllf:
+; CHECK: vupllf %v24, %v24
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vupllf(<4 x i32> %a)
+  ret <2 x i64> %res
+}
+
+; VACCB.
+define <16 x i8> @test_vaccb(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vaccb:
+; CHECK: vaccb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vaccb(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VACCH.
+define <8 x i16> @test_vacch(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vacch:
+; CHECK: vacch %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vacch(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %res
+}
+
+; VACCF.
+define <4 x i32> @test_vaccf(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vaccf:
+; CHECK: vaccf %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vaccf(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %res
+}
+
+; VACCG.
+define <2 x i64> @test_vaccg(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vaccg:
+; CHECK: vaccg %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vaccg(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %res
+}
+
+; VAQ.
+define <16 x i8> @test_vaq(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vaq:
+; CHECK: vaq %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vaq(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VACQ.
+define <16 x i8> @test_vacq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vacq:
+; CHECK: vacq %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vacq(<16 x i8> %a, <16 x i8> %b,
+                                        <16 x i8> %c)
+  ret <16 x i8> %res
+}
+
+; VACCQ.
+define <16 x i8> @test_vaccq(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vaccq:
+; CHECK: vaccq %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vaccq(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VACCCQ.
+define <16 x i8> @test_vacccq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vacccq:
+; CHECK: vacccq %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vacccq(<16 x i8> %a, <16 x i8> %b,
+                                          <16 x i8> %c)
+  ret <16 x i8> %res
+}
+
+; VAVGB.
+define <16 x i8> @test_vavgb(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vavgb:
+; CHECK: vavgb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vavgb(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VAVGH.
+define <8 x i16> @test_vavgh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vavgh:
+; CHECK: vavgh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vavgh(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %res
+}
+
+; VAVGF.
+define <4 x i32> @test_vavgf(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vavgf:
+; CHECK: vavgf %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vavgf(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %res
+}
+
+; VAVGG.
+define <2 x i64> @test_vavgg(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vavgg:
+; CHECK: vavgg %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vavgg(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %res
+}
+
+; VAVGLB.
+define <16 x i8> @test_vavglb(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vavglb:
+; CHECK: vavglb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vavglb(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VAVGLH.
+define <8 x i16> @test_vavglh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vavglh:
+; CHECK: vavglh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vavglh(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %res
+}
+
+; VAVGLF.
+define <4 x i32> @test_vavglf(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vavglf:
+; CHECK: vavglf %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vavglf(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %res
+}
+
+; VAVGLG.
+define <2 x i64> @test_vavglg(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vavglg:
+; CHECK: vavglg %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vavglg(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %res
+}
+
+; VCKSM.
+define <4 x i32> @test_vcksm(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vcksm:
+; CHECK: vcksm %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vcksm(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %res
+}
+
+; VGFMB.
+define <8 x i16> @test_vgfmb(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vgfmb:
+; CHECK: vgfmb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vgfmb(<16 x i8> %a, <16 x i8> %b)
+  ret <8 x i16> %res
+}
+
+; VGFMH.
+define <4 x i32> @test_vgfmh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vgfmh:
+; CHECK: vgfmh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vgfmh(<8 x i16> %a, <8 x i16> %b)
+  ret <4 x i32> %res
+}
+
+; VGFMF.
+define <2 x i64> @test_vgfmf(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vgfmf:
+; CHECK: vgfmf %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vgfmf(<4 x i32> %a, <4 x i32> %b)
+  ret <2 x i64> %res
+}
+
+; VGFMG.
+define <16 x i8> @test_vgfmg(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vgfmg:
+; CHECK: vgfmg %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vgfmg(<2 x i64> %a, <2 x i64> %b)
+  ret <16 x i8> %res
+}
+
+; VGFMAB.
+define <8 x i16> @test_vgfmab(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) {
+; CHECK-LABEL: test_vgfmab:
+; CHECK: vgfmab %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vgfmab(<16 x i8> %a, <16 x i8> %b,
+                                          <8 x i16> %c)
+  ret <8 x i16> %res
+}
+
+; VGFMAH.
+define <4 x i32> @test_vgfmah(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) {
+; CHECK-LABEL: test_vgfmah:
+; CHECK: vgfmah %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vgfmah(<8 x i16> %a, <8 x i16> %b,
+                                          <4 x i32> %c)
+  ret <4 x i32> %res
+}
+
+; VGFMAF.
+define <2 x i64> @test_vgfmaf(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vgfmaf:
+; CHECK: vgfmaf %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vgfmaf(<4 x i32> %a, <4 x i32> %b,
+                                          <2 x i64> %c)
+  ret <2 x i64> %res
+}
+
+; VGFMAG.
+define <16 x i8> @test_vgfmag(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vgfmag:
+; CHECK: vgfmag %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vgfmag(<2 x i64> %a, <2 x i64> %b,
+                                          <16 x i8> %c)
+  ret <16 x i8> %res
+}
+
+; VMAHB.
+define <16 x i8> @test_vmahb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vmahb:
+; CHECK: vmahb %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vmahb(<16 x i8> %a, <16 x i8> %b,
+                                         <16 x i8> %c)
+  ret <16 x i8> %res
+}
+
+; VMAHH.
+define <8 x i16> @test_vmahh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
+; CHECK-LABEL: test_vmahh:
+; CHECK: vmahh %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vmahh(<8 x i16> %a, <8 x i16> %b,
+                                         <8 x i16> %c)
+  ret <8 x i16> %res
+}
+
+; VMAHF.
+define <4 x i32> @test_vmahf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
+; CHECK-LABEL: test_vmahf:
+; CHECK: vmahf %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vmahf(<4 x i32> %a, <4 x i32> %b,
+                                         <4 x i32> %c)
+  ret <4 x i32> %res
+}
+
+; VMALHB.
+define <16 x i8> @test_vmalhb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vmalhb:
+; CHECK: vmalhb %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vmalhb(<16 x i8> %a, <16 x i8> %b,
+                                          <16 x i8> %c)
+  ret <16 x i8> %res
+}
+
+; VMALHH.
+define <8 x i16> @test_vmalhh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
+; CHECK-LABEL: test_vmalhh:
+; CHECK: vmalhh %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vmalhh(<8 x i16> %a, <8 x i16> %b,
+                                          <8 x i16> %c)
+  ret <8 x i16> %res
+}
+
+; VMALHF.
+define <4 x i32> @test_vmalhf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
+; CHECK-LABEL: test_vmalhf:
+; CHECK: vmalhf %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vmalhf(<4 x i32> %a, <4 x i32> %b,
+                                          <4 x i32> %c)
+  ret <4 x i32> %res
+}
+
+; VMAEB.
+define <8 x i16> @test_vmaeb(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) {
+; CHECK-LABEL: test_vmaeb:
+; CHECK: vmaeb %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vmaeb(<16 x i8> %a, <16 x i8> %b,
+                                         <8 x i16> %c)
+  ret <8 x i16> %res
+}
+
+; VMAEH.
+define <4 x i32> @test_vmaeh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) {
+; CHECK-LABEL: test_vmaeh:
+; CHECK: vmaeh %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vmaeh(<8 x i16> %a, <8 x i16> %b,
+                                         <4 x i32> %c)
+  ret <4 x i32> %res
+}
+
+; VMAEF.
+define <2 x i64> @test_vmaef(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vmaef:
+; CHECK: vmaef %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vmaef(<4 x i32> %a, <4 x i32> %b,
+                                         <2 x i64> %c)
+  ret <2 x i64> %res
+}
+
+; VMALEB.
+define <8 x i16> @test_vmaleb(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) {
+; CHECK-LABEL: test_vmaleb:
+; CHECK: vmaleb %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vmaleb(<16 x i8> %a, <16 x i8> %b,
+                                          <8 x i16> %c)
+  ret <8 x i16> %res
+}
+
+; VMALEH.
+define <4 x i32> @test_vmaleh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) {
+; CHECK-LABEL: test_vmaleh:
+; CHECK: vmaleh %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vmaleh(<8 x i16> %a, <8 x i16> %b,
+                                          <4 x i32> %c)
+  ret <4 x i32> %res
+}
+
+; VMALEF.
+define <2 x i64> @test_vmalef(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vmalef:
+; CHECK: vmalef %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vmalef(<4 x i32> %a, <4 x i32> %b,
+                                          <2 x i64> %c)
+  ret <2 x i64> %res
+}
+
+; VMAOB.
+define <8 x i16> @test_vmaob(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) {
+; CHECK-LABEL: test_vmaob:
+; CHECK: vmaob %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vmaob(<16 x i8> %a, <16 x i8> %b,
+                                         <8 x i16> %c)
+  ret <8 x i16> %res
+}
+
+; VMAOH.
+define <4 x i32> @test_vmaoh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) {
+; CHECK-LABEL: test_vmaoh:
+; CHECK: vmaoh %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vmaoh(<8 x i16> %a, <8 x i16> %b,
+                                         <4 x i32> %c)
+  ret <4 x i32> %res
+}
+
+; VMAOF.
+define <2 x i64> @test_vmaof(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vmaof:
+; CHECK: vmaof %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vmaof(<4 x i32> %a, <4 x i32> %b,
+                                         <2 x i64> %c)
+  ret <2 x i64> %res
+}
+
+; VMALOB.
+define <8 x i16> @test_vmalob(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) {
+; CHECK-LABEL: test_vmalob:
+; CHECK: vmalob %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vmalob(<16 x i8> %a, <16 x i8> %b,
+                                          <8 x i16> %c)
+  ret <8 x i16> %res
+}
+
+; VMALOH.
+define <4 x i32> @test_vmaloh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) {
+; CHECK-LABEL: test_vmaloh:
+; CHECK: vmaloh %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vmaloh(<8 x i16> %a, <8 x i16> %b,
+                                          <4 x i32> %c)
+  ret <4 x i32> %res
+}
+
+; VMALOF.
+define <2 x i64> @test_vmalof(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_vmalof:
+; CHECK: vmalof %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vmalof(<4 x i32> %a, <4 x i32> %b,
+                                          <2 x i64> %c)
+  ret <2 x i64> %res
+}
+
+; VMHB.
+define <16 x i8> @test_vmhb(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vmhb:
+; CHECK: vmhb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vmhb(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VMHH.
+define <8 x i16> @test_vmhh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vmhh:
+; CHECK: vmhh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vmhh(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %res
+}
+
+; VMHF.
+define <4 x i32> @test_vmhf(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vmhf:
+; CHECK: vmhf %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vmhf(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %res
+}
+
+; VMLHB.
+define <16 x i8> @test_vmlhb(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vmlhb:
+; CHECK: vmlhb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vmlhb(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VMLHH.
+define <8 x i16> @test_vmlhh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vmlhh:
+; CHECK: vmlhh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vmlhh(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %res
+}
+
+; VMLHF.
+define <4 x i32> @test_vmlhf(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vmlhf:
+; CHECK: vmlhf %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vmlhf(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %res
+}
+
+; VMEB.
+define <8 x i16> @test_vmeb(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vmeb:
+; CHECK: vmeb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vmeb(<16 x i8> %a, <16 x i8> %b)
+  ret <8 x i16> %res
+}
+
+; VMEH.
+define <4 x i32> @test_vmeh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vmeh:
+; CHECK: vmeh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vmeh(<8 x i16> %a, <8 x i16> %b)
+  ret <4 x i32> %res
+}
+
+; VMEF.
+define <2 x i64> @test_vmef(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vmef:
+; CHECK: vmef %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vmef(<4 x i32> %a, <4 x i32> %b)
+  ret <2 x i64> %res
+}
+
+; VMLEB.
+define <8 x i16> @test_vmleb(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vmleb:
+; CHECK: vmleb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vmleb(<16 x i8> %a, <16 x i8> %b)
+  ret <8 x i16> %res
+}
+
+; VMLEH.
+define <4 x i32> @test_vmleh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vmleh:
+; CHECK: vmleh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vmleh(<8 x i16> %a, <8 x i16> %b)
+  ret <4 x i32> %res
+}
+
+; VMLEF.
+define <2 x i64> @test_vmlef(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vmlef:
+; CHECK: vmlef %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vmlef(<4 x i32> %a, <4 x i32> %b)
+  ret <2 x i64> %res
+}
+
+; VMOB.
+define <8 x i16> @test_vmob(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vmob:
+; CHECK: vmob %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vmob(<16 x i8> %a, <16 x i8> %b)
+  ret <8 x i16> %res
+}
+
+; VMOH.
+define <4 x i32> @test_vmoh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vmoh:
+; CHECK: vmoh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vmoh(<8 x i16> %a, <8 x i16> %b)
+  ret <4 x i32> %res
+}
+
+; VMOF.
+define <2 x i64> @test_vmof(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vmof:
+; CHECK: vmof %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vmof(<4 x i32> %a, <4 x i32> %b)
+  ret <2 x i64> %res
+}
+
+; VMLOB.
+define <8 x i16> @test_vmlob(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vmlob:
+; CHECK: vmlob %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vmlob(<16 x i8> %a, <16 x i8> %b)
+  ret <8 x i16> %res
+}
+
+; VMLOH.
+define <4 x i32> @test_vmloh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vmloh:
+; CHECK: vmloh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vmloh(<8 x i16> %a, <8 x i16> %b)
+  ret <4 x i32> %res
+}
+
+; VMLOF.
+define <2 x i64> @test_vmlof(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vmlof:
+; CHECK: vmlof %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vmlof(<4 x i32> %a, <4 x i32> %b)
+  ret <2 x i64> %res
+}
+
+; VERLLVB.
+define <16 x i8> @test_verllvb(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_verllvb:
+; CHECK: verllvb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.verllvb(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VERLLVH.
+define <8 x i16> @test_verllvh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_verllvh:
+; CHECK: verllvh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.verllvh(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %res
+}
+
+; VERLLVF.
+define <4 x i32> @test_verllvf(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_verllvf:
+; CHECK: verllvf %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.verllvf(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %res
+}
+
+; VERLLVG.
+define <2 x i64> @test_verllvg(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_verllvg:
+; CHECK: verllvg %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.verllvg(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %res
+}
+
+; VERLLB.
+define <16 x i8> @test_verllb(<16 x i8> %a, i32 %b) {
+; CHECK-LABEL: test_verllb:
+; CHECK: verllb %v24, %v24, 0(%r2)
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 %b)
+  ret <16 x i8> %res
+}
+
+; VERLLH.
+define <8 x i16> @test_verllh(<8 x i16> %a, i32 %b) {
+; CHECK-LABEL: test_verllh:
+; CHECK: verllh %v24, %v24, 0(%r2)
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.verllh(<8 x i16> %a, i32 %b)
+  ret <8 x i16> %res
+}
+
+; VERLLF.
+define <4 x i32> @test_verllf(<4 x i32> %a, i32 %b) {
+; CHECK-LABEL: test_verllf:
+; CHECK: verllf %v24, %v24, 0(%r2)
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.verllf(<4 x i32> %a, i32 %b)
+  ret <4 x i32> %res
+}
+
+; VERLLG.
+define <2 x i64> @test_verllg(<2 x i64> %a, i32 %b) {
+; CHECK-LABEL: test_verllg:
+; CHECK: verllg %v24, %v24, 0(%r2)
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.verllg(<2 x i64> %a, i32 %b)
+  ret <2 x i64> %res
+}
+
+; VERLLB with the smallest count.
+define <16 x i8> @test_verllb_1(<16 x i8> %a) {
+; CHECK-LABEL: test_verllb_1:
+; CHECK: verllb %v24, %v24, 1
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 1)
+  ret <16 x i8> %res
+}
+
+; VERLLB with the largest count.
+define <16 x i8> @test_verllb_4095(<16 x i8> %a) {
+; CHECK-LABEL: test_verllb_4095:
+; CHECK: verllb %v24, %v24, 4095
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 4095)
+  ret <16 x i8> %res
+}
+
+; VERLLB with the largest count + 1.
+define <16 x i8> @test_verllb_4096(<16 x i8> %a) {
+; CHECK-LABEL: test_verllb_4096:
+; CHECK: lhi [[REG:%r[1-5]]], 4096
+; CHECK: verllb %v24, %v24, 0([[REG]])
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 4096)
+  ret <16 x i8> %res
+}
+
+; VERIMB.
+define <16 x i8> @test_verimb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_verimb:
+; CHECK: verimb %v24, %v26, %v28, 1
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.verimb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, i32 1)
+  ret <16 x i8> %res
+}
+
+; VERIMH.
+define <8 x i16> @test_verimh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
+; CHECK-LABEL: test_verimh:
+; CHECK: verimh %v24, %v26, %v28, 1
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.verimh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, i32 1)
+  ret <8 x i16> %res
+}
+
+; VERIMF.
+define <4 x i32> @test_verimf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
+; CHECK-LABEL: test_verimf:
+; CHECK: verimf %v24, %v26, %v28, 1
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.verimf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, i32 1)
+  ret <4 x i32> %res
+}
+
+; VERIMG.
+define <2 x i64> @test_verimg(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: test_verimg:
+; CHECK: verimg %v24, %v26, %v28, 1
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.verimg(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, i32 1)
+  ret <2 x i64> %res
+}
+
+; VERIMB with a different mask.
+define <16 x i8> @test_verimb_254(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_verimb_254:
+; CHECK: verimb %v24, %v26, %v28, 254
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.verimb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, i32 254)
+  ret <16 x i8> %res
+}
+
+; VSL.
+define <16 x i8> @test_vsl(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vsl:
+; CHECK: vsl %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vsl(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VSLB.
+define <16 x i8> @test_vslb(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vslb:
+; CHECK: vslb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vslb(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VSRA.
+define <16 x i8> @test_vsra(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vsra:
+; CHECK: vsra %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vsra(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VSRAB.
+define <16 x i8> @test_vsrab(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vsrab:
+; CHECK: vsrab %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vsrab(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VSRL.
+define <16 x i8> @test_vsrl(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vsrl:
+; CHECK: vsrl %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vsrl(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VSRLB.
+define <16 x i8> @test_vsrlb(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vsrlb:
+; CHECK: vsrlb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vsrlb(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VSLDB with the minimum useful value.
+define <16 x i8> @test_vsldb_1(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vsldb_1:
+; CHECK: vsldb %v24, %v24, %v26, 1
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vsldb(<16 x i8> %a, <16 x i8> %b, i32 1)
+  ret <16 x i8> %res
+}
+
+; VSLDB with the maximum value.
+define <16 x i8> @test_vsldb_15(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vsldb_15:
+; CHECK: vsldb %v24, %v24, %v26, 15
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vsldb(<16 x i8> %a, <16 x i8> %b, i32 15)
+  ret <16 x i8> %res
+}
+
+; VSCBIB.
+define <16 x i8> @test_vscbib(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vscbib:
+; CHECK: vscbib %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vscbib(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VSCBIH.
+define <8 x i16> @test_vscbih(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vscbih:
+; CHECK: vscbih %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vscbih(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %res
+}
+
+; VSCBIF.
+define <4 x i32> @test_vscbif(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vscbif:
+; CHECK: vscbif %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vscbif(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %res
+}
+
+; VSCBIG.
+define <2 x i64> @test_vscbig(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vscbig:
+; CHECK: vscbig %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vscbig(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %res
+}
+
+; VSQ.
+define <16 x i8> @test_vsq(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vsq:
+; CHECK: vsq %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vsq(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VSBIQ.
+define <16 x i8> @test_vsbiq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vsbiq:
+; CHECK: vsbiq %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vsbiq(<16 x i8> %a, <16 x i8> %b,
+                                         <16 x i8> %c)
+  ret <16 x i8> %res
+}
+
+; VSCBIQ.
+define <16 x i8> @test_vscbiq(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vscbiq:
+; CHECK: vscbiq %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vscbiq(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VSBCBIQ.
+define <16 x i8> @test_vsbcbiq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vsbcbiq:
+; CHECK: vsbcbiq %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vsbcbiq(<16 x i8> %a, <16 x i8> %b,
+                                           <16 x i8> %c)
+  ret <16 x i8> %res
+}
+
+; VSUMB.
+define <4 x i32> @test_vsumb(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vsumb:
+; CHECK: vsumb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vsumb(<16 x i8> %a, <16 x i8> %b)
+  ret <4 x i32> %res
+}
+
+; VSUMH.
+define <4 x i32> @test_vsumh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vsumh:
+; CHECK: vsumh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vsumh(<8 x i16> %a, <8 x i16> %b)
+  ret <4 x i32> %res
+}
+
+; VSUMGH.
+define <2 x i64> @test_vsumgh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vsumgh:
+; CHECK: vsumgh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vsumgh(<8 x i16> %a, <8 x i16> %b)
+  ret <2 x i64> %res
+}
+
+; VSUMGF.
+define <2 x i64> @test_vsumgf(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vsumgf:
+; CHECK: vsumgf %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <2 x i64> @llvm.s390.vsumgf(<4 x i32> %a, <4 x i32> %b)
+  ret <2 x i64> %res
+}
+
+; VSUMQF.
+define <16 x i8> @test_vsumqf(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vsumqf:
+; CHECK: vsumqf %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vsumqf(<4 x i32> %a, <4 x i32> %b)
+  ret <16 x i8> %res
+}
+
+; VSUMQG.
+define <16 x i8> @test_vsumqg(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vsumqg:
+; CHECK: vsumqg %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vsumqg(<2 x i64> %a, <2 x i64> %b)
+  ret <16 x i8> %res
+}
+
+; VTM with no processing of the result.
+define i32 @test_vtm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vtm:
+; CHECK: vtm %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.vtm(<16 x i8> %a, <16 x i8> %b)
+  ret i32 %res
+}
+
+; VTM, storing to %ptr if all bits are set.
+define void @test_vtm_all_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) {
+; CHECK-LABEL: test_vtm_all_store:
+; CHECK-NOT: %r
+; CHECK: vtm %v24, %v26
+; CHECK-NEXT: {{jno|jle}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.vtm(<16 x i8> %a, <16 x i8> %b)
+  %cmp = icmp sge i32 %res, 3
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret void
+}
+
+; VCEQBS with no processing of the result.
+define i32 @test_vceqbs(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vceqbs:
+; CHECK: vceqbs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8> %a, <16 x i8> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 1
+  ret i32 %res
+}
+
+; VCEQBS, returning 1 if any elements are equal (CC != 3).
+define i32 @test_vceqbs_any_bool(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vceqbs_any_bool:
+; CHECK: vceqbs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: afi %r2, -536870912
+; CHECK: srl %r2, 31
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8> %a, <16 x i8> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 1
+  %cmp = icmp ne i32 %res, 3
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VCEQBS, storing to %ptr if any elements are equal.
+define <16 x i8> @test_vceqbs_any_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) {
+; CHECK-LABEL: test_vceqbs_any_store:
+; CHECK-NOT: %r
+; CHECK: vceqbs %v24, %v24, %v26
+; CHECK-NEXT: {{jo|jnle}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8> %a, <16 x i8> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  %cmp = icmp ule i32 %cc, 2
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <16 x i8> %res
+}
+
+; VCEQHS with no processing of the result.
+define i32 @test_vceqhs(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vceqhs:
+; CHECK: vceqhs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 1
+  ret i32 %res
+}
+
+; VCEQHS, returning 1 if not all elements are equal.
+define i32 @test_vceqhs_notall_bool(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vceqhs_notall_bool:
+; CHECK: vceqhs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: risblg %r2, [[REG]], 31, 159, 36
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 1
+  %cmp = icmp sge i32 %res, 1
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VCEQHS, storing to %ptr if not all elements are equal.
+define <8 x i16> @test_vceqhs_notall_store(<8 x i16> %a, <8 x i16> %b,
+                                           i32 *%ptr) {
+; CHECK-LABEL: test_vceqhs_notall_store:
+; CHECK-NOT: %r
+; CHECK: vceqhs %v24, %v24, %v26
+; CHECK-NEXT: {{jhe|je}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  %cmp = icmp ugt i32 %cc, 0
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <8 x i16> %res
+}
+
+; VCEQFS with no processing of the result.
+define i32 @test_vceqfs(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vceqfs:
+; CHECK: vceqfs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 1
+  ret i32 %res
+}
+
+; VCEQFS, returning 1 if no elements are equal.
+define i32 @test_vceqfs_none_bool(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vceqfs_none_bool:
+; CHECK: vceqfs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: risblg %r2, [[REG]], 31, 159, 35
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 1
+  %cmp = icmp eq i32 %res, 3
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VCEQFS, storing to %ptr if no elements are equal.
+define <4 x i32> @test_vceqfs_none_store(<4 x i32> %a, <4 x i32> %b,
+                                         i32 *%ptr) {
+; CHECK-LABEL: test_vceqfs_none_store:
+; CHECK-NOT: %r
+; CHECK: vceqfs %v24, %v24, %v26
+; CHECK-NEXT: {{jno|jle}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  %cmp = icmp uge i32 %cc, 3
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <4 x i32> %res
+}
+
+; VCEQGS with no processing of the result.
+define i32 @test_vceqgs(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vceqgs:
+; CHECK: vceqgs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64> %a, <2 x i64> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 1
+  ret i32 %res
+}
+
+; VCEQGS returning 1 if all elements are equal (CC == 0).
+define i32 @test_vceqgs_all_bool(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vceqgs_all_bool:
+; CHECK: vceqgs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: afi %r2, -268435456
+; CHECK: srl %r2, 31
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64> %a, <2 x i64> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 1
+  %cmp = icmp ult i32 %res, 1
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VCEQGS, storing to %ptr if all elements are equal.
+define <2 x i64> @test_vceqgs_all_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) {
+; CHECK-LABEL: test_vceqgs_all_store:
+; CHECK-NOT: %r
+; CHECK: vceqgs %v24, %v24, %v26
+; CHECK-NEXT: {{jnhe|jne}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64> %a, <2 x i64> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 0
+  %cc = extractvalue {<2 x i64>, i32} %call, 1
+  %cmp = icmp sle i32 %cc, 0
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <2 x i64> %res
+}
+
+; VCHBS with no processing of the result.
+define i32 @test_vchbs(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vchbs:
+; CHECK: vchbs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8> %a, <16 x i8> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 1
+  ret i32 %res
+}
+
+; VCHBS, returning 1 if any elements are higher (CC != 3).
+define i32 @test_vchbs_any_bool(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vchbs_any_bool:
+; CHECK: vchbs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: afi %r2, -536870912
+; CHECK: srl %r2, 31
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8> %a, <16 x i8> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 1
+  %cmp = icmp ne i32 %res, 3
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VCHBS, storing to %ptr if any elements are higher.
+define <16 x i8> @test_vchbs_any_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) {
+; CHECK-LABEL: test_vchbs_any_store:
+; CHECK-NOT: %r
+; CHECK: vchbs %v24, %v24, %v26
+; CHECK-NEXT: {{jo|jnle}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8> %a, <16 x i8> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  %cmp = icmp ule i32 %cc, 2
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <16 x i8> %res
+}
+
+; VCHHS with no processing of the result.
+define i32 @test_vchhs(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vchhs:
+; CHECK: vchhs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 1
+  ret i32 %res
+}
+
+; VCHHS, returning 1 if not all elements are higher.
+define i32 @test_vchhs_notall_bool(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vchhs_notall_bool:
+; CHECK: vchhs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: risblg %r2, [[REG]], 31, 159, 36
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 1
+  %cmp = icmp sge i32 %res, 1
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VCHHS, storing to %ptr if not all elements are higher.
+define <8 x i16> @test_vchhs_notall_store(<8 x i16> %a, <8 x i16> %b,
+                                          i32 *%ptr) {
+; CHECK-LABEL: test_vchhs_notall_store:
+; CHECK-NOT: %r
+; CHECK: vchhs %v24, %v24, %v26
+; CHECK-NEXT: {{jhe|je}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  %cmp = icmp ugt i32 %cc, 0
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <8 x i16> %res
+}
+
+; VCHFS with no processing of the result.
+define i32 @test_vchfs(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vchfs:
+; CHECK: vchfs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 1
+  ret i32 %res
+}
+
+; VCHFS, returning 1 if no elements are higher.
+define i32 @test_vchfs_none_bool(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vchfs_none_bool:
+; CHECK: vchfs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: risblg %r2, [[REG]], 31, 159, 35
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 1
+  %cmp = icmp eq i32 %res, 3
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VCHFS, storing to %ptr if no elements are higher.
+define <4 x i32> @test_vchfs_none_store(<4 x i32> %a, <4 x i32> %b, i32 *%ptr) {
+; CHECK-LABEL: test_vchfs_none_store:
+; CHECK-NOT: %r
+; CHECK: vchfs %v24, %v24, %v26
+; CHECK-NEXT: {{jno|jle}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  %cmp = icmp uge i32 %cc, 3
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <4 x i32> %res
+}
+
+; VCHGS with no processing of the result.
+define i32 @test_vchgs(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vchgs:
+; CHECK: vchgs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64> %a, <2 x i64> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 1
+  ret i32 %res
+}
+
+; VCHGS returning 1 if all elements are higher (CC == 0).
+define i32 @test_vchgs_all_bool(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vchgs_all_bool:
+; CHECK: vchgs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: afi %r2, -268435456
+; CHECK: srl %r2, 31
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64> %a, <2 x i64> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 1
+  %cmp = icmp ult i32 %res, 1
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VCHGS, storing to %ptr if all elements are higher.
+define <2 x i64> @test_vchgs_all_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) {
+; CHECK-LABEL: test_vchgs_all_store:
+; CHECK-NOT: %r
+; CHECK: vchgs %v24, %v24, %v26
+; CHECK-NEXT: {{jnhe|jne}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64> %a, <2 x i64> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 0
+  %cc = extractvalue {<2 x i64>, i32} %call, 1
+  %cmp = icmp sle i32 %cc, 0
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <2 x i64> %res
+}
+
+; VCHLBS with no processing of the result.
+define i32 @test_vchlbs(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vchlbs:
+; CHECK: vchlbs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8> %a, <16 x i8> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 1
+  ret i32 %res
+}
+
+; VCHLBS, returning 1 if any elements are higher (CC != 3).
+define i32 @test_vchlbs_any_bool(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vchlbs_any_bool:
+; CHECK: vchlbs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: afi %r2, -536870912
+; CHECK: srl %r2, 31
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8> %a, <16 x i8> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 1
+  %cmp = icmp ne i32 %res, 3
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VCHLBS, storing to %ptr if any elements are higher.
+define <16 x i8> @test_vchlbs_any_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) {
+; CHECK-LABEL: test_vchlbs_any_store:
+; CHECK-NOT: %r
+; CHECK: vchlbs %v24, %v24, %v26
+; CHECK-NEXT: {{jo|jnle}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8> %a, <16 x i8> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  %cmp = icmp sle i32 %cc, 2
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <16 x i8> %res
+}
+
+; VCHLHS with no processing of the result.
+define i32 @test_vchlhs(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vchlhs:
+; CHECK: vchlhs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 1
+  ret i32 %res
+}
+
+; VCHLHS, returning 1 if not all elements are higher.
+define i32 @test_vchlhs_notall_bool(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vchlhs_notall_bool:
+; CHECK: vchlhs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: risblg %r2, [[REG]], 31, 159, 36
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 1
+  %cmp = icmp uge i32 %res, 1
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VCHLHS, storing to %ptr if not all elements are higher.
+define <8 x i16> @test_vchlhs_notall_store(<8 x i16> %a, <8 x i16> %b,
+                                           i32 *%ptr) {
+; CHECK-LABEL: test_vchlhs_notall_store:
+; CHECK-NOT: %r
+; CHECK: vchlhs %v24, %v24, %v26
+; CHECK-NEXT: {{jhe|je}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  %cmp = icmp sgt i32 %cc, 0
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <8 x i16> %res
+}
+
+; VCHLFS with no processing of the result.
+define i32 @test_vchlfs(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vchlfs:
+; CHECK: vchlfs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 1
+  ret i32 %res
+}
+
+; VCHLFS, returning 1 if no elements are higher.
+define i32 @test_vchlfs_none_bool(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vchlfs_none_bool:
+; CHECK: vchlfs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: risblg %r2, [[REG]], 31, 159, 35
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 1
+  %cmp = icmp eq i32 %res, 3
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VCHLFS, storing to %ptr if no elements are higher.
+define <4 x i32> @test_vchlfs_none_store(<4 x i32> %a, <4 x i32> %b,
+                                         i32 *%ptr) {
+; CHECK-LABEL: test_vchlfs_none_store:
+; CHECK-NOT: %r
+; CHECK: vchlfs %v24, %v24, %v26
+; CHECK-NEXT: {{jno|jle}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  %cmp = icmp sge i32 %cc, 3
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <4 x i32> %res
+}
+
+; VCHLGS with no processing of the result.
+define i32 @test_vchlgs(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vchlgs:
+; CHECK: vchlgs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64> %a, <2 x i64> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 1
+  ret i32 %res
+}
+
+; VCHLGS returning 1 if all elements are higher (CC == 0).
+define i32 @test_vchlgs_all_bool(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vchlgs_all_bool:
+; CHECK: vchlgs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: afi %r2, -268435456
+; CHECK: srl %r2, 31
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64> %a, <2 x i64> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 1
+  %cmp = icmp slt i32 %res, 1
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VCHLGS, storing to %ptr if all elements are higher.
+define <2 x i64> @test_vchlgs_all_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) {
+; CHECK-LABEL: test_vchlgs_all_store:
+; CHECK-NOT: %r
+; CHECK: vchlgs %v24, %v24, %v26
+; CHECK-NEXT: {{jnhe|jne}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64> %a, <2 x i64> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 0
+  %cc = extractvalue {<2 x i64>, i32} %call, 1
+  %cmp = icmp ule i32 %cc, 0
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <2 x i64> %res
+}
+
+; VFAEB with !IN !RT.
+define <16 x i8> @test_vfaeb_0(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vfaeb_0:
+; CHECK: vfaeb %v24, %v24, %v26, 0
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 0)
+  ret <16 x i8> %res
+}
+
+; VFAEB with !IN RT.
+define <16 x i8> @test_vfaeb_4(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vfaeb_4:
+; CHECK: vfaeb %v24, %v24, %v26, 4
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 4)
+  ret <16 x i8> %res
+}
+
+; VFAEB with IN !RT.
+define <16 x i8> @test_vfaeb_8(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vfaeb_8:
+; CHECK: vfaeb %v24, %v24, %v26, 8
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 8)
+  ret <16 x i8> %res
+}
+
+; VFAEB with IN RT.
+define <16 x i8> @test_vfaeb_12(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vfaeb_12:
+; CHECK: vfaeb %v24, %v24, %v26, 12
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 12)
+  ret <16 x i8> %res
+}
+
+; VFAEB with CS -- should be ignored.
+define <16 x i8> @test_vfaeb_1(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vfaeb_1:
+; CHECK: vfaeb %v24, %v24, %v26, 0
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 1)
+  ret <16 x i8> %res
+}
+
+; VFAEH.
+define <8 x i16> @test_vfaeh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vfaeh:
+; CHECK: vfaeh %v24, %v24, %v26, 4
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vfaeh(<8 x i16> %a, <8 x i16> %b, i32 4)
+  ret <8 x i16> %res
+}
+
+; VFAEF.
+define <4 x i32> @test_vfaef(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vfaef:
+; CHECK: vfaef %v24, %v24, %v26, 8
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vfaef(<4 x i32> %a, <4 x i32> %b, i32 8)
+  ret <4 x i32> %res
+}
+
+; VFAEBS.
+define <16 x i8> @test_vfaebs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfaebs:
+; CHECK: vfaebs %v24, %v24, %v26, 0
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vfaebs(<16 x i8> %a, <16 x i8> %b,
+                                                  i32 0)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <16 x i8> %res
+}
+
+; VFAEHS.
+define <8 x i16> @test_vfaehs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfaehs:
+; CHECK: vfaehs %v24, %v24, %v26, 4
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vfaehs(<8 x i16> %a, <8 x i16> %b,
+                                                  i32 4)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <8 x i16> %res
+}
+
+; VFAEFS.
+define <4 x i32> @test_vfaefs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfaefs:
+; CHECK: vfaefs %v24, %v24, %v26, 8
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vfaefs(<4 x i32> %a, <4 x i32> %b,
+                                                  i32 8)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <4 x i32> %res
+}
+
+; VFAEZB with !IN !RT.
+define <16 x i8> @test_vfaezb_0(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vfaezb_0:
+; CHECK: vfaezb %v24, %v24, %v26, 0
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 0)
+  ret <16 x i8> %res
+}
+
+; VFAEZB with !IN RT.
+define <16 x i8> @test_vfaezb_4(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vfaezb_4:
+; CHECK: vfaezb %v24, %v24, %v26, 4
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 4)
+  ret <16 x i8> %res
+}
+
+; VFAEZB with IN !RT.
+define <16 x i8> @test_vfaezb_8(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vfaezb_8:
+; CHECK: vfaezb %v24, %v24, %v26, 8
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 8)
+  ret <16 x i8> %res
+}
+
+; VFAEZB with IN RT.
+define <16 x i8> @test_vfaezb_12(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vfaezb_12:
+; CHECK: vfaezb %v24, %v24, %v26, 12
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 12)
+  ret <16 x i8> %res
+}
+
+; VFAEZB with CS -- should be ignored.
+define <16 x i8> @test_vfaezb_1(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vfaezb_1:
+; CHECK: vfaezb %v24, %v24, %v26, 0
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 1)
+  ret <16 x i8> %res
+}
+
+; VFAEZH.
+define <8 x i16> @test_vfaezh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vfaezh:
+; CHECK: vfaezh %v24, %v24, %v26, 4
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vfaezh(<8 x i16> %a, <8 x i16> %b, i32 4)
+  ret <8 x i16> %res
+}
+
+; VFAEZF.
+define <4 x i32> @test_vfaezf(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vfaezf:
+; CHECK: vfaezf %v24, %v24, %v26, 8
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vfaezf(<4 x i32> %a, <4 x i32> %b, i32 8)
+  ret <4 x i32> %res
+}
+
+; VFAEZBS.
+define <16 x i8> @test_vfaezbs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfaezbs:
+; CHECK: vfaezbs %v24, %v24, %v26, 0
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vfaezbs(<16 x i8> %a, <16 x i8> %b,
+                                                   i32 0)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <16 x i8> %res
+}
+
+; VFAEZHS.
+define <8 x i16> @test_vfaezhs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfaezhs:
+; CHECK: vfaezhs %v24, %v24, %v26, 4
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vfaezhs(<8 x i16> %a, <8 x i16> %b,
+                                                   i32 4)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <8 x i16> %res
+}
+
+; VFAEZFS.
+define <4 x i32> @test_vfaezfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfaezfs:
+; CHECK: vfaezfs %v24, %v24, %v26, 8
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vfaezfs(<4 x i32> %a, <4 x i32> %b,
+                                                   i32 8)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <4 x i32> %res
+}
+
+; VFEEB.
+define <16 x i8> @test_vfeeb_0(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vfeeb_0:
+; CHECK: vfeeb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vfeeb(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VFEEH.
+define <8 x i16> @test_vfeeh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vfeeh:
+; CHECK: vfeeh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vfeeh(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %res
+}
+
+; VFEEF.
+define <4 x i32> @test_vfeef(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vfeef:
+; CHECK: vfeef %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vfeef(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %res
+}
+
+; VFEEBS.
+define <16 x i8> @test_vfeebs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfeebs:
+; CHECK: vfeebs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vfeebs(<16 x i8> %a, <16 x i8> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <16 x i8> %res
+}
+
+; VFEEHS.
+define <8 x i16> @test_vfeehs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfeehs:
+; CHECK: vfeehs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vfeehs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <8 x i16> %res
+}
+
+; VFEEFS.
+define <4 x i32> @test_vfeefs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfeefs:
+; CHECK: vfeefs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vfeefs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <4 x i32> %res
+}
+
+; VFEEZB.
+define <16 x i8> @test_vfeezb(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vfeezb:
+; CHECK: vfeezb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vfeezb(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VFEEZH.
+define <8 x i16> @test_vfeezh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vfeezh:
+; CHECK: vfeezh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vfeezh(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %res
+}
+
+; VFEEZF.
+define <4 x i32> @test_vfeezf(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vfeezf:
+; CHECK: vfeezf %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vfeezf(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %res
+}
+
+; VFEEZBS.
+define <16 x i8> @test_vfeezbs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfeezbs:
+; CHECK: vfeezbs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vfeezbs(<16 x i8> %a, <16 x i8> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <16 x i8> %res
+}
+
+; VFEEZHS.
+define <8 x i16> @test_vfeezhs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfeezhs:
+; CHECK: vfeezhs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vfeezhs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <8 x i16> %res
+}
+
+; VFEEZFS.
+define <4 x i32> @test_vfeezfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfeezfs:
+; CHECK: vfeezfs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vfeezfs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <4 x i32> %res
+}
+
+; VFENEB.
+define <16 x i8> @test_vfeneb_0(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vfeneb_0:
+; CHECK: vfeneb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vfeneb(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VFENEH.
+define <8 x i16> @test_vfeneh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vfeneh:
+; CHECK: vfeneh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vfeneh(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %res
+}
+
+; VFENEF.
+define <4 x i32> @test_vfenef(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vfenef:
+; CHECK: vfenef %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vfenef(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %res
+}
+
+; VFENEBS.
+define <16 x i8> @test_vfenebs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfenebs:
+; CHECK: vfenebs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vfenebs(<16 x i8> %a, <16 x i8> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <16 x i8> %res
+}
+
+; VFENEHS.
+define <8 x i16> @test_vfenehs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfenehs:
+; CHECK: vfenehs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vfenehs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <8 x i16> %res
+}
+
+; VFENEFS.
+define <4 x i32> @test_vfenefs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfenefs:
+; CHECK: vfenefs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vfenefs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <4 x i32> %res
+}
+
+; VFENEZB.
+define <16 x i8> @test_vfenezb(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vfenezb:
+; CHECK: vfenezb %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vfenezb(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+}
+
+; VFENEZH.
+define <8 x i16> @test_vfenezh(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vfenezh:
+; CHECK: vfenezh %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vfenezh(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %res
+}
+
+; VFENEZF.
+define <4 x i32> @test_vfenezf(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vfenezf:
+; CHECK: vfenezf %v24, %v24, %v26
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vfenezf(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %res
+}
+
+; VFENEZBS.
+define <16 x i8> @test_vfenezbs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfenezbs:
+; CHECK: vfenezbs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vfenezbs(<16 x i8> %a, <16 x i8> %b)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <16 x i8> %res
+}
+
+; VFENEZHS.
+define <8 x i16> @test_vfenezhs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfenezhs:
+; CHECK: vfenezhs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vfenezhs(<8 x i16> %a, <8 x i16> %b)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <8 x i16> %res
+}
+
+; VFENEZFS.
+define <4 x i32> @test_vfenezfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) {
+; CHECK-LABEL: test_vfenezfs:
+; CHECK: vfenezfs %v24, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vfenezfs(<4 x i32> %a, <4 x i32> %b)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <4 x i32> %res
+}
+
+; VISTRB.
+define <16 x i8> @test_vistrb(<16 x i8> %a) {
+; CHECK-LABEL: test_vistrb:
+; CHECK: vistrb %v24, %v24
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vistrb(<16 x i8> %a)
+  ret <16 x i8> %res
+}
+
+; VISTRH.
+define <8 x i16> @test_vistrh(<8 x i16> %a) {
+; CHECK-LABEL: test_vistrh:
+; CHECK: vistrh %v24, %v24
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vistrh(<8 x i16> %a)
+  ret <8 x i16> %res
+}
+
+; VISTRF.
+define <4 x i32> @test_vistrf(<4 x i32> %a) {
+; CHECK-LABEL: test_vistrf:
+; CHECK: vistrf %v24, %v24
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vistrf(<4 x i32> %a)
+  ret <4 x i32> %res
+}
+
+; VISTRBS.
+define <16 x i8> @test_vistrbs(<16 x i8> %a, i32 *%ccptr) {
+; CHECK-LABEL: test_vistrbs:
+; CHECK: vistrbs %v24, %v24
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vistrbs(<16 x i8> %a)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <16 x i8> %res
+}
+
+; VISTRHS.
+define <8 x i16> @test_vistrhs(<8 x i16> %a, i32 *%ccptr) {
+; CHECK-LABEL: test_vistrhs:
+; CHECK: vistrhs %v24, %v24
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vistrhs(<8 x i16> %a)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <8 x i16> %res
+}
+
+; VISTRFS.
+define <4 x i32> @test_vistrfs(<4 x i32> %a, i32 *%ccptr) {
+; CHECK-LABEL: test_vistrfs:
+; CHECK: vistrfs %v24, %v24
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vistrfs(<4 x i32> %a)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <4 x i32> %res
+}
+
+; VSTRCB with !IN !RT.
+define <16 x i8> @test_vstrcb_0(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vstrcb_0:
+; CHECK: vstrcb %v24, %v24, %v26, %v28, 0
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b,
+                                          <16 x i8> %c, i32 0)
+  ret <16 x i8> %res
+}
+
+; VSTRCB with !IN RT.
+define <16 x i8> @test_vstrcb_4(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vstrcb_4:
+; CHECK: vstrcb %v24, %v24, %v26, %v28, 4
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b,
+                                          <16 x i8> %c, i32 4)
+  ret <16 x i8> %res
+}
+
+; VSTRCB with IN !RT.
+define <16 x i8> @test_vstrcb_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vstrcb_8:
+; CHECK: vstrcb %v24, %v24, %v26, %v28, 8
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b,
+                                          <16 x i8> %c, i32 8)
+  ret <16 x i8> %res
+}
+
+; VSTRCB with IN RT.
+define <16 x i8> @test_vstrcb_12(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vstrcb_12:
+; CHECK: vstrcb %v24, %v24, %v26, %v28, 12
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b,
+                                          <16 x i8> %c, i32 12)
+  ret <16 x i8> %res
+}
+
+; VSTRCB with CS -- should be ignored.
+define <16 x i8> @test_vstrcb_1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vstrcb_1:
+; CHECK: vstrcb %v24, %v24, %v26, %v28, 0
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b,
+                                          <16 x i8> %c, i32 1)
+  ret <16 x i8> %res
+}
+
+; VSTRCH.
+define <8 x i16> @test_vstrch(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
+; CHECK-LABEL: test_vstrch:
+; CHECK: vstrch %v24, %v24, %v26, %v28, 4
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vstrch(<8 x i16> %a, <8 x i16> %b,
+                                          <8 x i16> %c, i32 4)
+  ret <8 x i16> %res
+}
+
+; VSTRCF.
+define <4 x i32> @test_vstrcf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
+; CHECK-LABEL: test_vstrcf:
+; CHECK: vstrcf %v24, %v24, %v26, %v28, 8
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vstrcf(<4 x i32> %a, <4 x i32> %b,
+                                          <4 x i32> %c, i32 8)
+  ret <4 x i32> %res
+}
+
+; VSTRCBS.
+define <16 x i8> @test_vstrcbs(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c,
+                               i32 *%ccptr) {
+; CHECK-LABEL: test_vstrcbs:
+; CHECK: vstrcbs %v24, %v24, %v26, %v28, 0
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vstrcbs(<16 x i8> %a, <16 x i8> %b,
+                                                   <16 x i8> %c, i32 0)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <16 x i8> %res
+}
+
+; VSTRCHS.
+define <8 x i16> @test_vstrchs(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c,
+                               i32 *%ccptr) {
+; CHECK-LABEL: test_vstrchs:
+; CHECK: vstrchs %v24, %v24, %v26, %v28, 4
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vstrchs(<8 x i16> %a, <8 x i16> %b,
+                                                   <8 x i16> %c, i32 4)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <8 x i16> %res
+}
+
+; VSTRCFS.
+define <4 x i32> @test_vstrcfs(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c,
+                               i32 *%ccptr) {
+; CHECK-LABEL: test_vstrcfs:
+; CHECK: vstrcfs %v24, %v24, %v26, %v28, 8
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vstrcfs(<4 x i32> %a, <4 x i32> %b,
+                                                   <4 x i32> %c, i32 8)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <4 x i32> %res
+}
+
+; VSTRCZB with !IN !RT.
+define <16 x i8> @test_vstrczb_0(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vstrczb_0:
+; CHECK: vstrczb %v24, %v24, %v26, %v28, 0
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b,
+                                           <16 x i8> %c, i32 0)
+  ret <16 x i8> %res
+}
+
+; VSTRCZB with !IN RT.
+define <16 x i8> @test_vstrczb_4(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vstrczb_4:
+; CHECK: vstrczb %v24, %v24, %v26, %v28, 4
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b,
+                                           <16 x i8> %c, i32 4)
+  ret <16 x i8> %res
+}
+
+; VSTRCZB with IN !RT.
+define <16 x i8> @test_vstrczb_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vstrczb_8:
+; CHECK: vstrczb %v24, %v24, %v26, %v28, 8
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b,
+                                           <16 x i8> %c, i32 8)
+  ret <16 x i8> %res
+}
+
+; VSTRCZB with IN RT.
+define <16 x i8> @test_vstrczb_12(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vstrczb_12:
+; CHECK: vstrczb %v24, %v24, %v26, %v28, 12
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b,
+                                           <16 x i8> %c, i32 12)
+  ret <16 x i8> %res
+}
+
+; VSTRCZB with CS -- should be ignored.
+define <16 x i8> @test_vstrczb_1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_vstrczb_1:
+; CHECK: vstrczb %v24, %v24, %v26, %v28, 0
+; CHECK: br %r14
+  %res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b,
+                                           <16 x i8> %c, i32 1)
+  ret <16 x i8> %res
+}
+
+; VSTRCZH.
+define <8 x i16> @test_vstrczh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
+; CHECK-LABEL: test_vstrczh:
+; CHECK: vstrczh %v24, %v24, %v26, %v28, 4
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vstrczh(<8 x i16> %a, <8 x i16> %b,
+                                           <8 x i16> %c,  i32 4)
+  ret <8 x i16> %res
+}
+
+; VSTRCZF.
+define <4 x i32> @test_vstrczf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
+; CHECK-LABEL: test_vstrczf:
+; CHECK: vstrczf %v24, %v24, %v26, %v28, 8
+; CHECK: br %r14
+  %res = call <4 x i32> @llvm.s390.vstrczf(<4 x i32> %a, <4 x i32> %b,
+                                           <4 x i32> %c, i32 8)
+  ret <4 x i32> %res
+}
+
+; VSTRCZBS.
+define <16 x i8> @test_vstrczbs(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c,
+                                i32 *%ccptr) {
+; CHECK-LABEL: test_vstrczbs:
+; CHECK: vstrczbs %v24, %v24, %v26, %v28, 0
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<16 x i8>, i32} @llvm.s390.vstrczbs(<16 x i8> %a, <16 x i8> %b,
+                                                    <16 x i8> %c, i32 0)
+  %res = extractvalue {<16 x i8>, i32} %call, 0
+  %cc = extractvalue {<16 x i8>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <16 x i8> %res
+}
+
+; VSTRCZHS.
+define <8 x i16> @test_vstrczhs(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c,
+                                i32 *%ccptr) {
+; CHECK-LABEL: test_vstrczhs:
+; CHECK: vstrczhs %v24, %v24, %v26, %v28, 4
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<8 x i16>, i32} @llvm.s390.vstrczhs(<8 x i16> %a, <8 x i16> %b,
+                                                    <8 x i16> %c, i32 4)
+  %res = extractvalue {<8 x i16>, i32} %call, 0
+  %cc = extractvalue {<8 x i16>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <8 x i16> %res
+}
+
+; VSTRCZFS.
+define <4 x i32> @test_vstrczfs(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c,
+                                i32 *%ccptr) {
+; CHECK-LABEL: test_vstrczfs:
+; CHECK: vstrczfs %v24, %v24, %v26, %v28, 8
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: srl [[REG]], 28
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %call = call {<4 x i32>, i32} @llvm.s390.vstrczfs(<4 x i32> %a, <4 x i32> %b,
+                                                    <4 x i32> %c, i32 8)
+  %res = extractvalue {<4 x i32>, i32} %call, 0
+  %cc = extractvalue {<4 x i32>, i32} %call, 1
+  store i32 %cc, i32 *%ccptr
+  ret <4 x i32> %res
+}
+
+; VFCEDBS with no processing of the result.
+define i32 @test_vfcedbs(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: test_vfcedbs:
+; CHECK: vfcedbs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double> %a,
+                                                   <2 x double> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 1
+  ret i32 %res
+}
+
+; VFCEDBS, returning 1 if any elements are equal (CC != 3).
+define i32 @test_vfcedbs_any_bool(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: test_vfcedbs_any_bool:
+; CHECK: vfcedbs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: afi %r2, -536870912
+; CHECK: srl %r2, 31
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double> %a,
+                                                   <2 x double> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 1
+  %cmp = icmp ne i32 %res, 3
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VFCEDBS, storing to %ptr if any elements are equal.
+define <2 x i64> @test_vfcedbs_any_store(<2 x double> %a, <2 x double> %b,
+                                         i32 *%ptr) {
+; CHECK-LABEL: test_vfcedbs_any_store:
+; CHECK-NOT: %r
+; CHECK: vfcedbs %v24, %v24, %v26
+; CHECK-NEXT: {{jo|jnle}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double> %a,
+                                                   <2 x double> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 0
+  %cc = extractvalue {<2 x i64>, i32} %call, 1
+  %cmp = icmp ule i32 %cc, 2
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <2 x i64> %res
+}
+
+; VFCHDBS with no processing of the result.
+define i32 @test_vfchdbs(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: test_vfchdbs:
+; CHECK: vfchdbs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double> %a,
+                                                   <2 x double> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 1
+  ret i32 %res
+}
+
+; VFCHDBS, returning 1 if not all elements are higher.
+define i32 @test_vfchdbs_notall_bool(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: test_vfchdbs_notall_bool:
+; CHECK: vfchdbs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: risblg %r2, [[REG]], 31, 159, 36
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double> %a,
+                                                   <2 x double> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 1
+  %cmp = icmp sge i32 %res, 1
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VFCHDBS, storing to %ptr if not all elements are higher.
+define <2 x i64> @test_vfchdbs_notall_store(<2 x double> %a, <2 x double> %b,
+                                            i32 *%ptr) {
+; CHECK-LABEL: test_vfchdbs_notall_store:
+; CHECK-NOT: %r
+; CHECK: vfchdbs %v24, %v24, %v26
+; CHECK-NEXT: {{jhe|je}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double> %a,
+                                                   <2 x double> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 0
+  %cc = extractvalue {<2 x i64>, i32} %call, 1
+  %cmp = icmp ugt i32 %cc, 0
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <2 x i64> %res
+}
+
+; VFCHEDBS with no processing of the result.
+define i32 @test_vfchedbs(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: test_vfchedbs:
+; CHECK: vfchedbs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double> %a,
+						    <2 x double> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 1
+  ret i32 %res
+}
+
+; VFCHEDBS, returning 1 if neither element is higher or equal.
+define i32 @test_vfchedbs_none_bool(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: test_vfchedbs_none_bool:
+; CHECK: vfchedbs {{%v[0-9]+}}, %v24, %v26
+; CHECK: ipm [[REG:%r[0-5]]]
+; CHECK: risblg %r2, [[REG]], 31, 159, 35
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double> %a,
+						    <2 x double> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 1
+  %cmp = icmp eq i32 %res, 3
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VFCHEDBS, storing to %ptr if neither element is higher or equal.
+define <2 x i64> @test_vfchedbs_none_store(<2 x double> %a, <2 x double> %b,
+                                           i32 *%ptr) {
+; CHECK-LABEL: test_vfchedbs_none_store:
+; CHECK-NOT: %r
+; CHECK: vfchedbs %v24, %v24, %v26
+; CHECK-NEXT: {{jno|jle}} {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double> %a,
+						    <2 x double> %b)
+  %res = extractvalue {<2 x i64>, i32} %call, 0
+  %cc = extractvalue {<2 x i64>, i32} %call, 1
+  %cmp = icmp uge i32 %cc, 3
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 0, i32 *%ptr
+  br label %exit
+
+exit:
+  ret <2 x i64> %res
+}
+
+; VFTCIDB with the lowest useful class selector and no processing of the result.
+define i32 @test_vftcidb(<2 x double> %a) {
+; CHECK-LABEL: test_vftcidb:
+; CHECK: vftcidb {{%v[0-9]+}}, %v24, 1
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vftcidb(<2 x double> %a, i32 1)
+  %res = extractvalue {<2 x i64>, i32} %call, 1
+  ret i32 %res
+}
+
+; VFTCIDB with the highest useful class selector, returning 1 if all elements
+; have the right class (CC == 0).
+define i32 @test_vftcidb_all_bool(<2 x double> %a) {
+; CHECK-LABEL: test_vftcidb_all_bool:
+; CHECK: vftcidb {{%v[0-9]+}}, %v24, 4094
+; CHECK: afi %r2, -268435456
+; CHECK: srl %r2, 31
+; CHECK: br %r14
+  %call = call {<2 x i64>, i32} @llvm.s390.vftcidb(<2 x double> %a, i32 4094)
+  %res = extractvalue {<2 x i64>, i32} %call, 1
+  %cmp = icmp eq i32 %res, 0
+  %ext = zext i1 %cmp to i32
+  ret i32 %ext
+}
+
+; VFIDB with a rounding mode not usable via standard intrinsics.
+define <2 x double> @test_vfidb_0_4(<2 x double> %a) {
+; CHECK-LABEL: test_vfidb_0_4:
+; CHECK: vfidb %v24, %v24, 0, 4
+; CHECK: br %r14
+  %res = call <2 x double> @llvm.s390.vfidb(<2 x double> %a, i32 0, i32 4)
+  ret <2 x double> %res
+}
+
+; VFIDB with IEEE-inexact exception suppressed.
+define <2 x double> @test_vfidb_4_0(<2 x double> %a) {
+; CHECK-LABEL: test_vfidb_4_0:
+; CHECK: vfidb %v24, %v24, 4, 0
+; CHECK: br %r14
+  %res = call <2 x double> @llvm.s390.vfidb(<2 x double> %a, i32 4, i32 0)
+  ret <2 x double> %res
+}
+
diff --git a/test/CodeGen/SystemZ/vec-log-01.ll b/test/CodeGen/SystemZ/vec-log-01.ll
new file mode 100644
index 000000000000..f9b7402f08e7
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-log-01.ll
@@ -0,0 +1,15 @@
+; Test v2f64 logarithm.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+declare <2 x double> @llvm.log.v2f64(<2 x double>)
+
+define <2 x double> @f1(<2 x double> %val) {
+; CHECK-LABEL: f1:
+; CHECK: brasl %r14, log@PLT
+; CHECK: brasl %r14, log@PLT
+; CHECK: vmrhg %v24,
+; CHECK: br %r14
+  %ret = call <2 x double> @llvm.log.v2f64(<2 x double> %val)
+  ret <2 x double> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-max-01.ll b/test/CodeGen/SystemZ/vec-max-01.ll
new file mode 100644
index 000000000000..ca6f08aa493f
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-max-01.ll
@@ -0,0 +1,83 @@
+; Test v16i8 maximum.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test with slt.
+define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp slt <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
+  ret <16 x i8> %ret
+}
+
+; Test with sle.
+define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sle <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
+  ret <16 x i8> %ret
+}
+
+; Test with sgt.
+define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sgt <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
+  ret <16 x i8> %ret
+}
+
+; Test with sge.
+define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sge <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
+  ret <16 x i8> %ret
+}
+
+; Test with ult.
+define <16 x i8> @f5(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ult <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
+  ret <16 x i8> %ret
+}
+
+; Test with ule.
+define <16 x i8> @f6(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ule <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
+  ret <16 x i8> %ret
+}
+
+; Test with ugt.
+define <16 x i8> @f7(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ugt <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
+  ret <16 x i8> %ret
+}
+
+; Test with uge.
+define <16 x i8> @f8(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp uge <16 x i8> %val1, %val2
+  %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
+  ret <16 x i8> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-max-02.ll b/test/CodeGen/SystemZ/vec-max-02.ll
new file mode 100644
index 000000000000..2c61603b6f3b
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-max-02.ll
@@ -0,0 +1,83 @@
+; Test v8i16 maximum.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test with slt.
+define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp slt <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
+  ret <8 x i16> %ret
+}
+
+; Test with sle.
+define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sle <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
+  ret <8 x i16> %ret
+}
+
+; Test with sgt.
+define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sgt <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
+  ret <8 x i16> %ret
+}
+
+; Test with sge.
+define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sge <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
+  ret <8 x i16> %ret
+}
+
+; Test with ult.
+define <8 x i16> @f5(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ult <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
+  ret <8 x i16> %ret
+}
+
+; Test with ule.
+define <8 x i16> @f6(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ule <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
+  ret <8 x i16> %ret
+}
+
+; Test with ugt.
+define <8 x i16> @f7(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ugt <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
+  ret <8 x i16> %ret
+}
+
+; Test with uge.
+define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp uge <8 x i16> %val1, %val2
+  %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
+  ret <8 x i16> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-max-03.ll b/test/CodeGen/SystemZ/vec-max-03.ll
new file mode 100644
index 000000000000..a43879483997
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-max-03.ll
@@ -0,0 +1,83 @@
+; Test v4i32 maximum.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test with slt.
+define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp slt <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
+  ret <4 x i32> %ret
+}
+
+; Test with sle.
+define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sle <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
+  ret <4 x i32> %ret
+}
+
+; Test with sgt.
+define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sgt <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
+  ret <4 x i32> %ret
+}
+
+; Test with sge.
+define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sge <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
+  ret <4 x i32> %ret
+}
+
+; Test with ult.
+define <4 x i32> @f5(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ult <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
+  ret <4 x i32> %ret
+}
+
+; Test with ule.
+define <4 x i32> @f6(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ule <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
+  ret <4 x i32> %ret
+}
+
+; Test with ugt.
+define <4 x i32> @f7(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ugt <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
+  ret <4 x i32> %ret
+}
+
+; Test with uge.
+define <4 x i32> @f8(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp uge <4 x i32> %val1, %val2
+  %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
+  ret <4 x i32> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-max-04.ll b/test/CodeGen/SystemZ/vec-max-04.ll
new file mode 100644
index 000000000000..ab7c62391277
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-max-04.ll
@@ -0,0 +1,83 @@
+; Test v2i64 maximum.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test with slt.
+define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp slt <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
+  ret <2 x i64> %ret
+}
+
+; Test with sle.
+define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sle <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
+  ret <2 x i64> %ret
+}
+
+; Test with sgt.
+define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sgt <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
+  ret <2 x i64> %ret
+}
+
+; Test with sge.
+define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sge <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
+  ret <2 x i64> %ret
+}
+
+; Test with ult.
+define <2 x i64> @f5(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ult <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
+  ret <2 x i64> %ret
+}
+
+; Test with ule.
+define <2 x i64> @f6(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ule <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
+  ret <2 x i64> %ret
+}
+
+; Test with ugt.
+define <2 x i64> @f7(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ugt <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
+  ret <2 x i64> %ret
+}
+
+; Test with uge.
+define <2 x i64> @f8(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp uge <2 x i64> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-min-01.ll b/test/CodeGen/SystemZ/vec-min-01.ll
new file mode 100644
index 000000000000..255dc57e1134
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-min-01.ll
@@ -0,0 +1,83 @@
+; Test v16i8 minimum.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test with slt.
+define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp slt <16 x i8> %val2, %val1
+  %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
+  ret <16 x i8> %ret
+}
+
+; Test with sle.
+define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sle <16 x i8> %val2, %val1
+  %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
+  ret <16 x i8> %ret
+}
+
+; Test with sgt.
+define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sgt <16 x i8> %val2, %val1
+  %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
+  ret <16 x i8> %ret
+}
+
+; Test with sge.
+define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sge <16 x i8> %val2, %val1
+  %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
+  ret <16 x i8> %ret
+}
+
+; Test with ult.
+define <16 x i8> @f5(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ult <16 x i8> %val2, %val1
+  %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
+  ret <16 x i8> %ret
+}
+
+; Test with ule.
+define <16 x i8> @f6(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ule <16 x i8> %val2, %val1
+  %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
+  ret <16 x i8> %ret
+}
+
+; Test with ugt.
+define <16 x i8> @f7(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ugt <16 x i8> %val2, %val1
+  %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
+  ret <16 x i8> %ret
+}
+
+; Test with uge.
+define <16 x i8> @f8(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp uge <16 x i8> %val2, %val1
+  %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
+  ret <16 x i8> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-min-02.ll b/test/CodeGen/SystemZ/vec-min-02.ll
new file mode 100644
index 000000000000..cad8a61506c8
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-min-02.ll
@@ -0,0 +1,83 @@
+; Test v8i16 minimum.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test with slt.
+define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp slt <8 x i16> %val2, %val1
+  %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
+  ret <8 x i16> %ret
+}
+
+; Test with sle.
+define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sle <8 x i16> %val2, %val1
+  %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
+  ret <8 x i16> %ret
+}
+
+; Test with sgt.
+define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sgt <8 x i16> %val2, %val1
+  %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
+  ret <8 x i16> %ret
+}
+
+; Test with sge.
+define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sge <8 x i16> %val2, %val1
+  %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
+  ret <8 x i16> %ret
+}
+
+; Test with ult.
+define <8 x i16> @f5(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ult <8 x i16> %val2, %val1
+  %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
+  ret <8 x i16> %ret
+}
+
+; Test with ule.
+define <8 x i16> @f6(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ule <8 x i16> %val2, %val1
+  %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
+  ret <8 x i16> %ret
+}
+
+; Test with ugt.
+define <8 x i16> @f7(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ugt <8 x i16> %val2, %val1
+  %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
+  ret <8 x i16> %ret
+}
+
+; Test with uge.
+define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp uge <8 x i16> %val2, %val1
+  %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
+  ret <8 x i16> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-min-03.ll b/test/CodeGen/SystemZ/vec-min-03.ll
new file mode 100644
index 000000000000..febac50aa462
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-min-03.ll
@@ -0,0 +1,83 @@
+; Test v4i32 minimum.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test with slt.
+define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp slt <4 x i32> %val2, %val1
+  %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
+  ret <4 x i32> %ret
+}
+
+; Test with sle.
+define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sle <4 x i32> %val2, %val1
+  %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
+  ret <4 x i32> %ret
+}
+
+; Test with sgt.
+define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sgt <4 x i32> %val2, %val1
+  %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
+  ret <4 x i32> %ret
+}
+
+; Test with sge.
+define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sge <4 x i32> %val2, %val1
+  %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
+  ret <4 x i32> %ret
+}
+
+; Test with ult.
+define <4 x i32> @f5(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ult <4 x i32> %val2, %val1
+  %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
+  ret <4 x i32> %ret
+}
+
+; Test with ule.
+define <4 x i32> @f6(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ule <4 x i32> %val2, %val1
+  %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
+  ret <4 x i32> %ret
+}
+
+; Test with ugt.
+define <4 x i32> @f7(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ugt <4 x i32> %val2, %val1
+  %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
+  ret <4 x i32> %ret
+}
+
+; Test with uge.
+define <4 x i32> @f8(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp uge <4 x i32> %val2, %val1
+  %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
+  ret <4 x i32> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-min-04.ll b/test/CodeGen/SystemZ/vec-min-04.ll
new file mode 100644
index 000000000000..765ce1956b5d
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-min-04.ll
@@ -0,0 +1,83 @@
+; Test v2i64 minimum.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test with slt.
+define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp slt <2 x i64> %val2, %val1
+  %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
+  ret <2 x i64> %ret
+}
+
+; Test with sle.
+define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sle <2 x i64> %val2, %val1
+  %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
+  ret <2 x i64> %ret
+}
+
+; Test with sgt.
+define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sgt <2 x i64> %val2, %val1
+  %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
+  ret <2 x i64> %ret
+}
+
+; Test with sge.
+define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp sge <2 x i64> %val2, %val1
+  %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
+  ret <2 x i64> %ret
+}
+
+; Test with ult.
+define <2 x i64> @f5(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ult <2 x i64> %val2, %val1
+  %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
+  ret <2 x i64> %ret
+}
+
+; Test with ule.
+define <2 x i64> @f6(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ule <2 x i64> %val2, %val1
+  %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
+  ret <2 x i64> %ret
+}
+
+; Test with ugt.
+define <2 x i64> @f7(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp ugt <2 x i64> %val2, %val1
+  %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
+  ret <2 x i64> %ret
+}
+
+; Test with uge.
+define <2 x i64> @f8(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}}
+; CHECK: br %r14
+  %cmp = icmp uge <2 x i64> %val2, %val1
+  %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-move-01.ll b/test/CodeGen/SystemZ/vec-move-01.ll
new file mode 100644
index 000000000000..3ef98b7eda03
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-01.ll
@@ -0,0 +1,107 @@
+; Test vector register moves.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test v16i8 moves.
+define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vlr %v24, %v26
+; CHECK: br %r14
+  ret <16 x i8> %val2
+}
+
+; Test v8i16 moves.
+define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vlr %v24, %v26
+; CHECK: br %r14
+  ret <8 x i16> %val2
+}
+
+; Test v4i32 moves.
+define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vlr %v24, %v26
+; CHECK: br %r14
+  ret <4 x i32> %val2
+}
+
+; Test v2i64 moves.
+define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vlr %v24, %v26
+; CHECK: br %r14
+  ret <2 x i64> %val2
+}
+
+; Test v4f32 moves.
+define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vlr %v24, %v26
+; CHECK: br %r14
+  ret <4 x float> %val2
+}
+
+; Test v2f64 moves.
+define <2 x double> @f6(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vlr %v24, %v26
+; CHECK: br %r14
+  ret <2 x double> %val2
+}
+
+; Test v2i8 moves.
+define <2 x i8> @f7(<2 x i8> %val1, <2 x i8> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vlr %v24, %v26
+; CHECK: br %r14
+  ret <2 x i8> %val2
+}
+
+; Test v4i8 moves.
+define <4 x i8> @f8(<4 x i8> %val1, <4 x i8> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vlr %v24, %v26
+; CHECK: br %r14
+  ret <4 x i8> %val2
+}
+
+; Test v8i8 moves.
+define <8 x i8> @f9(<8 x i8> %val1, <8 x i8> %val2) {
+; CHECK-LABEL: f9:
+; CHECK: vlr %v24, %v26
+; CHECK: br %r14
+  ret <8 x i8> %val2
+}
+
+; Test v2i16 moves.
+define <2 x i16> @f10(<2 x i16> %val1, <2 x i16> %val2) {
+; CHECK-LABEL: f10:
+; CHECK: vlr %v24, %v26
+; CHECK: br %r14
+  ret <2 x i16> %val2
+}
+
+; Test v4i16 moves.
+define <4 x i16> @f11(<4 x i16> %val1, <4 x i16> %val2) {
+; CHECK-LABEL: f11:
+; CHECK: vlr %v24, %v26
+; CHECK: br %r14
+  ret <4 x i16> %val2
+}
+
+; Test v2i32 moves.
+define <2 x i32> @f12(<2 x i32> %val1, <2 x i32> %val2) {
+; CHECK-LABEL: f12:
+; CHECK: vlr %v24, %v26
+; CHECK: br %r14
+  ret <2 x i32> %val2
+}
+
+; Test v2f32 moves.
+define <2 x float> @f13(<2 x float> %val1, <2 x float> %val2) {
+; CHECK-LABEL: f13:
+; CHECK: vlr %v24, %v26
+; CHECK: br %r14
+  ret <2 x float> %val2
+}
diff --git a/test/CodeGen/SystemZ/vec-move-02.ll b/test/CodeGen/SystemZ/vec-move-02.ll
new file mode 100644
index 000000000000..dcaf0acccb2f
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-02.ll
@@ -0,0 +1,174 @@
+; Test vector loads.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test v16i8 loads.
+define <16 x i8> @f1(<16 x i8> *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: vl %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = load <16 x i8>, <16 x i8> *%ptr
+  ret <16 x i8> %ret
+}
+
+; Test v8i16 loads.
+define <8 x i16> @f2(<8 x i16> *%ptr) {
+; CHECK-LABEL: f2:
+; CHECK: vl %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = load <8 x i16>, <8 x i16> *%ptr
+  ret <8 x i16> %ret
+}
+
+; Test v4i32 loads.
+define <4 x i32> @f3(<4 x i32> *%ptr) {
+; CHECK-LABEL: f3:
+; CHECK: vl %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = load <4 x i32>, <4 x i32> *%ptr
+  ret <4 x i32> %ret
+}
+
+; Test v2i64 loads.
+define <2 x i64> @f4(<2 x i64> *%ptr) {
+; CHECK-LABEL: f4:
+; CHECK: vl %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = load <2 x i64>, <2 x i64> *%ptr
+  ret <2 x i64> %ret
+}
+
+; Test v4f32 loads.
+define <4 x float> @f5(<4 x float> *%ptr) {
+; CHECK-LABEL: f5:
+; CHECK: vl %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = load <4 x float>, <4 x float> *%ptr
+  ret <4 x float> %ret
+}
+
+; Test v2f64 loads.
+define <2 x double> @f6(<2 x double> *%ptr) {
+; CHECK-LABEL: f6:
+; CHECK: vl %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = load <2 x double>, <2 x double> *%ptr
+  ret <2 x double> %ret
+}
+
+; Test the highest aligned in-range offset.
+define <16 x i8> @f7(<16 x i8> *%base) {
+; CHECK-LABEL: f7:
+; CHECK: vl %v24, 4080(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 255
+  %ret = load <16 x i8>, <16 x i8> *%ptr
+  ret <16 x i8> %ret
+}
+
+; Test the highest unaligned in-range offset.
+define <16 x i8> @f8(i8 *%base) {
+; CHECK-LABEL: f8:
+; CHECK: vl %v24, 4095(%r2)
+; CHECK: br %r14
+  %addr = getelementptr i8, i8 *%base, i64 4095
+  %ptr = bitcast i8 *%addr to <16 x i8> *
+  %ret = load <16 x i8>, <16 x i8> *%ptr, align 1
+  ret <16 x i8> %ret
+}
+
+; Test the next offset up, which requires separate address logic,
+define <16 x i8> @f9(<16 x i8> *%base) {
+; CHECK-LABEL: f9:
+; CHECK: aghi %r2, 4096
+; CHECK: vl %v24, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 256
+  %ret = load <16 x i8>, <16 x i8> *%ptr
+  ret <16 x i8> %ret
+}
+
+; Test negative offsets, which also require separate address logic,
+define <16 x i8> @f10(<16 x i8> *%base) {
+; CHECK-LABEL: f10:
+; CHECK: aghi %r2, -16
+; CHECK: vl %v24, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 -1
+  %ret = load <16 x i8>, <16 x i8> *%ptr
+  ret <16 x i8> %ret
+}
+
+; Check that indexes are allowed.
+define <16 x i8> @f11(i8 *%base, i64 %index) {
+; CHECK-LABEL: f11:
+; CHECK: vl %v24, 0(%r3,%r2)
+; CHECK: br %r14
+  %addr = getelementptr i8, i8 *%base, i64 %index
+  %ptr = bitcast i8 *%addr to <16 x i8> *
+  %ret = load <16 x i8>, <16 x i8> *%ptr, align 1
+  ret <16 x i8> %ret
+}
+
+; Test v2i8 loads.
+define <2 x i8> @f12(<2 x i8> *%ptr) {
+; CHECK-LABEL: f12:
+; CHECK: vlreph %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = load <2 x i8>, <2 x i8> *%ptr
+  ret <2 x i8> %ret
+}
+
+; Test v4i8 loads.
+define <4 x i8> @f13(<4 x i8> *%ptr) {
+; CHECK-LABEL: f13:
+; CHECK: vlrepf %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = load <4 x i8>, <4 x i8> *%ptr
+  ret <4 x i8> %ret
+}
+
+; Test v8i8 loads.
+define <8 x i8> @f14(<8 x i8> *%ptr) {
+; CHECK-LABEL: f14:
+; CHECK: vlrepg %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = load <8 x i8>, <8 x i8> *%ptr
+  ret <8 x i8> %ret
+}
+
+; Test v2i16 loads.
+define <2 x i16> @f15(<2 x i16> *%ptr) {
+; CHECK-LABEL: f15:
+; CHECK: vlrepf %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = load <2 x i16>, <2 x i16> *%ptr
+  ret <2 x i16> %ret
+}
+
+; Test v4i16 loads.
+define <4 x i16> @f16(<4 x i16> *%ptr) {
+; CHECK-LABEL: f16:
+; CHECK: vlrepg %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = load <4 x i16>, <4 x i16> *%ptr
+  ret <4 x i16> %ret
+}
+
+; Test v2i32 loads.
+define <2 x i32> @f17(<2 x i32> *%ptr) {
+; CHECK-LABEL: f17:
+; CHECK: vlrepg %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = load <2 x i32>, <2 x i32> *%ptr
+  ret <2 x i32> %ret
+}
+
+; Test v2f32 loads.
+define <2 x float> @f18(<2 x float> *%ptr) {
+; CHECK-LABEL: f18:
+; CHECK: vlrepg %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = load <2 x float>, <2 x float> *%ptr
+  ret <2 x float> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-move-03.ll b/test/CodeGen/SystemZ/vec-move-03.ll
new file mode 100644
index 000000000000..f40e2cb2bf28
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-03.ll
@@ -0,0 +1,174 @@
+; Test vector stores.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test v16i8 stores.
+define void @f1(<16 x i8> %val, <16 x i8> *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: vst %v24, 0(%r2)
+; CHECK: br %r14
+  store <16 x i8> %val, <16 x i8> *%ptr
+  ret void
+}
+
+; Test v8i16 stores.
+define void @f2(<8 x i16> %val, <8 x i16> *%ptr) {
+; CHECK-LABEL: f2:
+; CHECK: vst %v24, 0(%r2)
+; CHECK: br %r14
+  store <8 x i16> %val, <8 x i16> *%ptr
+  ret void
+}
+
+; Test v4i32 stores.
+define void @f3(<4 x i32> %val, <4 x i32> *%ptr) {
+; CHECK-LABEL: f3:
+; CHECK: vst %v24, 0(%r2)
+; CHECK: br %r14
+  store <4 x i32> %val, <4 x i32> *%ptr
+  ret void
+}
+
+; Test v2i64 stores.
+define void @f4(<2 x i64> %val, <2 x i64> *%ptr) {
+; CHECK-LABEL: f4:
+; CHECK: vst %v24, 0(%r2)
+; CHECK: br %r14
+  store <2 x i64> %val, <2 x i64> *%ptr
+  ret void
+}
+
+; Test v4f32 stores.
+define void @f5(<4 x float> %val, <4 x float> *%ptr) {
+; CHECK-LABEL: f5:
+; CHECK: vst %v24, 0(%r2)
+; CHECK: br %r14
+  store <4 x float> %val, <4 x float> *%ptr
+  ret void
+}
+
+; Test v2f64 stores.
+define void @f6(<2 x double> %val, <2 x double> *%ptr) {
+; CHECK-LABEL: f6:
+; CHECK: vst %v24, 0(%r2)
+; CHECK: br %r14
+  store <2 x double> %val, <2 x double> *%ptr
+  ret void
+}
+
+; Test the highest aligned in-range offset.
+define void @f7(<16 x i8> %val, <16 x i8> *%base) {
+; CHECK-LABEL: f7:
+; CHECK: vst %v24, 4080(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 255
+  store <16 x i8> %val, <16 x i8> *%ptr
+  ret void
+}
+
+; Test the highest unaligned in-range offset.
+define void @f8(<16 x i8> %val, i8 *%base) {
+; CHECK-LABEL: f8:
+; CHECK: vst %v24, 4095(%r2)
+; CHECK: br %r14
+  %addr = getelementptr i8, i8 *%base, i64 4095
+  %ptr = bitcast i8 *%addr to <16 x i8> *
+  store <16 x i8> %val, <16 x i8> *%ptr, align 1
+  ret void
+}
+
+; Test the next offset up, which requires separate address logic,
+define void @f9(<16 x i8> %val, <16 x i8> *%base) {
+; CHECK-LABEL: f9:
+; CHECK: aghi %r2, 4096
+; CHECK: vst %v24, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 256
+  store <16 x i8> %val, <16 x i8> *%ptr
+  ret void
+}
+
+; Test negative offsets, which also require separate address logic,
+define void @f10(<16 x i8> %val, <16 x i8> *%base) {
+; CHECK-LABEL: f10:
+; CHECK: aghi %r2, -16
+; CHECK: vst %v24, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 -1
+  store <16 x i8> %val, <16 x i8> *%ptr
+  ret void
+}
+
+; Check that indexes are allowed.
+define void @f11(<16 x i8> %val, i8 *%base, i64 %index) {
+; CHECK-LABEL: f11:
+; CHECK: vst %v24, 0(%r3,%r2)
+; CHECK: br %r14
+  %addr = getelementptr i8, i8 *%base, i64 %index
+  %ptr = bitcast i8 *%addr to <16 x i8> *
+  store <16 x i8> %val, <16 x i8> *%ptr, align 1
+  ret void
+}
+
+; Test v2i8 stores.
+define void @f12(<2 x i8> %val, <2 x i8> *%ptr) {
+; CHECK-LABEL: f12:
+; CHECK: vsteh %v24, 0(%r2), 0
+; CHECK: br %r14
+  store <2 x i8> %val, <2 x i8> *%ptr
+  ret void
+}
+
+; Test v4i8 stores.
+define void @f13(<4 x i8> %val, <4 x i8> *%ptr) {
+; CHECK-LABEL: f13:
+; CHECK: vstef %v24, 0(%r2)
+; CHECK: br %r14
+  store <4 x i8> %val, <4 x i8> *%ptr
+  ret void
+}
+
+; Test v8i8 stores.
+define void @f14(<8 x i8> %val, <8 x i8> *%ptr) {
+; CHECK-LABEL: f14:
+; CHECK: vsteg %v24, 0(%r2)
+; CHECK: br %r14
+  store <8 x i8> %val, <8 x i8> *%ptr
+  ret void
+}
+
+; Test v2i16 stores.
+define void @f15(<2 x i16> %val, <2 x i16> *%ptr) {
+; CHECK-LABEL: f15:
+; CHECK: vstef %v24, 0(%r2), 0
+; CHECK: br %r14
+  store <2 x i16> %val, <2 x i16> *%ptr
+  ret void
+}
+
+; Test v4i16 stores.
+define void @f16(<4 x i16> %val, <4 x i16> *%ptr) {
+; CHECK-LABEL: f16:
+; CHECK: vsteg %v24, 0(%r2)
+; CHECK: br %r14
+  store <4 x i16> %val, <4 x i16> *%ptr
+  ret void
+}
+
+; Test v2i32 stores.
+define void @f17(<2 x i32> %val, <2 x i32> *%ptr) {
+; CHECK-LABEL: f17:
+; CHECK: vsteg %v24, 0(%r2), 0
+; CHECK: br %r14
+  store <2 x i32> %val, <2 x i32> *%ptr
+  ret void
+}
+
+; Test v2f32 stores.
+define void @f18(<2 x float> %val, <2 x float> *%ptr) {
+; CHECK-LABEL: f18:
+; CHECK: vsteg %v24, 0(%r2), 0
+; CHECK: br %r14
+  store <2 x float> %val, <2 x float> *%ptr
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/vec-move-04.ll b/test/CodeGen/SystemZ/vec-move-04.ll
new file mode 100644
index 000000000000..27c9e5f71f40
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-04.ll
@@ -0,0 +1,179 @@
+; Test vector insertion of register variables.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test v16i8 insertion into the first element.
+define <16 x i8> @f1(<16 x i8> %val, i8 %element) {
+; CHECK-LABEL: f1:
+; CHECK: vlvgb %v24, %r2, 0
+; CHECK: br %r14
+  %ret = insertelement <16 x i8> %val, i8 %element, i32 0
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 insertion into the last element.
+define <16 x i8> @f2(<16 x i8> %val, i8 %element) {
+; CHECK-LABEL: f2:
+; CHECK: vlvgb %v24, %r2, 15
+; CHECK: br %r14
+  %ret = insertelement <16 x i8> %val, i8 %element, i32 15
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 insertion into a variable element.
+define <16 x i8> @f3(<16 x i8> %val, i8 %element, i32 %index) {
+; CHECK-LABEL: f3:
+; CHECK: vlvgb %v24, %r2, 0(%r3)
+; CHECK: br %r14
+  %ret = insertelement <16 x i8> %val, i8 %element, i32 %index
+  ret <16 x i8> %ret
+}
+
+; Test v8i16 insertion into the first element.
+define <8 x i16> @f4(<8 x i16> %val, i16 %element) {
+; CHECK-LABEL: f4:
+; CHECK: vlvgh %v24, %r2, 0
+; CHECK: br %r14
+  %ret = insertelement <8 x i16> %val, i16 %element, i32 0
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 insertion into the last element.
+define <8 x i16> @f5(<8 x i16> %val, i16 %element) {
+; CHECK-LABEL: f5:
+; CHECK: vlvgh %v24, %r2, 7
+; CHECK: br %r14
+  %ret = insertelement <8 x i16> %val, i16 %element, i32 7
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 insertion into a variable element.
+define <8 x i16> @f6(<8 x i16> %val, i16 %element, i32 %index) {
+; CHECK-LABEL: f6:
+; CHECK: vlvgh %v24, %r2, 0(%r3)
+; CHECK: br %r14
+  %ret = insertelement <8 x i16> %val, i16 %element, i32 %index
+  ret <8 x i16> %ret
+}
+
+; Test v4i32 insertion into the first element.
+define <4 x i32> @f7(<4 x i32> %val, i32 %element) {
+; CHECK-LABEL: f7:
+; CHECK: vlvgf %v24, %r2, 0
+; CHECK: br %r14
+  %ret = insertelement <4 x i32> %val, i32 %element, i32 0
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion into the last element.
+define <4 x i32> @f8(<4 x i32> %val, i32 %element) {
+; CHECK-LABEL: f8:
+; CHECK: vlvgf %v24, %r2, 3
+; CHECK: br %r14
+  %ret = insertelement <4 x i32> %val, i32 %element, i32 3
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion into a variable element.
+define <4 x i32> @f9(<4 x i32> %val, i32 %element, i32 %index) {
+; CHECK-LABEL: f9:
+; CHECK: vlvgf %v24, %r2, 0(%r3)
+; CHECK: br %r14
+  %ret = insertelement <4 x i32> %val, i32 %element, i32 %index
+  ret <4 x i32> %ret
+}
+
+; Test v2i64 insertion into the first element.
+define <2 x i64> @f10(<2 x i64> %val, i64 %element) {
+; CHECK-LABEL: f10:
+; CHECK: vlvgg %v24, %r2, 0
+; CHECK: br %r14
+  %ret = insertelement <2 x i64> %val, i64 %element, i32 0
+  ret <2 x i64> %ret
+}
+
+; Test v2i64 insertion into the last element.
+define <2 x i64> @f11(<2 x i64> %val, i64 %element) {
+; CHECK-LABEL: f11:
+; CHECK: vlvgg %v24, %r2, 1
+; CHECK: br %r14
+  %ret = insertelement <2 x i64> %val, i64 %element, i32 1
+  ret <2 x i64> %ret
+}
+
+; Test v2i64 insertion into a variable element.
+define <2 x i64> @f12(<2 x i64> %val, i64 %element, i32 %index) {
+; CHECK-LABEL: f12:
+; CHECK: vlvgg %v24, %r2, 0(%r3)
+; CHECK: br %r14
+  %ret = insertelement <2 x i64> %val, i64 %element, i32 %index
+  ret <2 x i64> %ret
+}
+
+; Test v4f32 insertion into the first element.
+define <4 x float> @f13(<4 x float> %val, float %element) {
+; CHECK-LABEL: f13:
+; CHECK: vlgvf [[REG:%r[0-5]]], %v0, 0
+; CHECK: vlvgf %v24, [[REG]], 0
+; CHECK: br %r14
+  %ret = insertelement <4 x float> %val, float %element, i32 0
+  ret <4 x float> %ret
+}
+
+; Test v4f32 insertion into the last element.
+define <4 x float> @f14(<4 x float> %val, float %element) {
+; CHECK-LABEL: f14:
+; CHECK: vlgvf [[REG:%r[0-5]]], %v0, 0
+; CHECK: vlvgf %v24, [[REG]], 3
+; CHECK: br %r14
+  %ret = insertelement <4 x float> %val, float %element, i32 3
+  ret <4 x float> %ret
+}
+
+; Test v4f32 insertion into a variable element.
+define <4 x float> @f15(<4 x float> %val, float %element, i32 %index) {
+; CHECK-LABEL: f15:
+; CHECK: vlgvf [[REG:%r[0-5]]], %v0, 0
+; CHECK: vlvgf %v24, [[REG]], 0(%r2)
+; CHECK: br %r14
+  %ret = insertelement <4 x float> %val, float %element, i32 %index
+  ret <4 x float> %ret
+}
+
+; Test v2f64 insertion into the first element.
+define <2 x double> @f16(<2 x double> %val, double %element) {
+; CHECK-LABEL: f16:
+; CHECK: vpdi %v24, %v0, %v24, 1
+; CHECK: br %r14
+  %ret = insertelement <2 x double> %val, double %element, i32 0
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion into the last element.
+define <2 x double> @f17(<2 x double> %val, double %element) {
+; CHECK-LABEL: f17:
+; CHECK: vpdi %v24, %v24, %v0, 0
+; CHECK: br %r14
+  %ret = insertelement <2 x double> %val, double %element, i32 1
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion into a variable element.
+define <2 x double> @f18(<2 x double> %val, double %element, i32 %index) {
+; CHECK-LABEL: f18:
+; CHECK: lgdr [[REG:%r[0-5]]], %f0
+; CHECK: vlvgg %v24, [[REG]], 0(%r2)
+; CHECK: br %r14
+  %ret = insertelement <2 x double> %val, double %element, i32 %index
+  ret <2 x double> %ret
+}
+
+; Test v16i8 insertion into a variable element plus one.
+define <16 x i8> @f19(<16 x i8> %val, i8 %element, i32 %index) {
+; CHECK-LABEL: f19:
+; CHECK: vlvgb %v24, %r2, 1(%r3)
+; CHECK: br %r14
+  %add = add i32 %index, 1
+  %ret = insertelement <16 x i8> %val, i8 %element, i32 %add
+  ret <16 x i8> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-move-05.ll b/test/CodeGen/SystemZ/vec-move-05.ll
new file mode 100644
index 000000000000..99871196d685
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-05.ll
@@ -0,0 +1,249 @@
+; Test vector extraction.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test v16i8 extraction of the first element.
+define i8 @f1(<16 x i8> %val) {
+; CHECK-LABEL: f1:
+; CHECK: vlgvb %r2, %v24, 0
+; CHECK: br %r14
+  %ret = extractelement <16 x i8> %val, i32 0
+  ret i8 %ret
+}
+
+; Test v16i8 extraction of the last element.
+define i8 @f2(<16 x i8> %val) {
+; CHECK-LABEL: f2:
+; CHECK: vlgvb %r2, %v24, 15
+; CHECK: br %r14
+  %ret = extractelement <16 x i8> %val, i32 15
+  ret i8 %ret
+}
+
+; Test v16i8 extractions of an absurd element number.  This must compile
+; but we don't care what it does.
+define i8 @f3(<16 x i8> %val) {
+; CHECK-LABEL: f3:
+; CHECK-NOT: vlgvb %r2, %v24, 100000
+; CHECK: br %r14
+  %ret = extractelement <16 x i8> %val, i32 100000
+  ret i8 %ret
+}
+
+; Test v16i8 extraction of a variable element.
+define i8 @f4(<16 x i8> %val, i32 %index) {
+; CHECK-LABEL: f4:
+; CHECK: vlgvb %r2, %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = extractelement <16 x i8> %val, i32 %index
+  ret i8 %ret
+}
+
+; Test v8i16 extraction of the first element.
+define i16 @f5(<8 x i16> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vlgvh %r2, %v24, 0
+; CHECK: br %r14
+  %ret = extractelement <8 x i16> %val, i32 0
+  ret i16 %ret
+}
+
+; Test v8i16 extraction of the last element.
+define i16 @f6(<8 x i16> %val) {
+; CHECK-LABEL: f6:
+; CHECK: vlgvh %r2, %v24, 7
+; CHECK: br %r14
+  %ret = extractelement <8 x i16> %val, i32 7
+  ret i16 %ret
+}
+
+; Test v8i16 extractions of an absurd element number.  This must compile
+; but we don't care what it does.
+define i16 @f7(<8 x i16> %val) {
+; CHECK-LABEL: f7:
+; CHECK-NOT: vlgvh %r2, %v24, 100000
+; CHECK: br %r14
+  %ret = extractelement <8 x i16> %val, i32 100000
+  ret i16 %ret
+}
+
+; Test v8i16 extraction of a variable element.
+define i16 @f8(<8 x i16> %val, i32 %index) {
+; CHECK-LABEL: f8:
+; CHECK: vlgvh %r2, %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = extractelement <8 x i16> %val, i32 %index
+  ret i16 %ret
+}
+
+; Test v4i32 extraction of the first element.
+define i32 @f9(<4 x i32> %val) {
+; CHECK-LABEL: f9:
+; CHECK: vlgvf %r2, %v24, 0
+; CHECK: br %r14
+  %ret = extractelement <4 x i32> %val, i32 0
+  ret i32 %ret
+}
+
+; Test v4i32 extraction of the last element.
+define i32 @f10(<4 x i32> %val) {
+; CHECK-LABEL: f10:
+; CHECK: vlgvf %r2, %v24, 3
+; CHECK: br %r14
+  %ret = extractelement <4 x i32> %val, i32 3
+  ret i32 %ret
+}
+
+; Test v4i32 extractions of an absurd element number.  This must compile
+; but we don't care what it does.
+define i32 @f11(<4 x i32> %val) {
+; CHECK-LABEL: f11:
+; CHECK-NOT: vlgvf %r2, %v24, 100000
+; CHECK: br %r14
+  %ret = extractelement <4 x i32> %val, i32 100000
+  ret i32 %ret
+}
+
+; Test v4i32 extraction of a variable element.
+define i32 @f12(<4 x i32> %val, i32 %index) {
+; CHECK-LABEL: f12:
+; CHECK: vlgvf %r2, %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = extractelement <4 x i32> %val, i32 %index
+  ret i32 %ret
+}
+
+; Test v2i64 extraction of the first element.
+define i64 @f13(<2 x i64> %val) {
+; CHECK-LABEL: f13:
+; CHECK: vlgvg %r2, %v24, 0
+; CHECK: br %r14
+  %ret = extractelement <2 x i64> %val, i32 0
+  ret i64 %ret
+}
+
+; Test v2i64 extraction of the last element.
+define i64 @f14(<2 x i64> %val) {
+; CHECK-LABEL: f14:
+; CHECK: vlgvg %r2, %v24, 1
+; CHECK: br %r14
+  %ret = extractelement <2 x i64> %val, i32 1
+  ret i64 %ret
+}
+
+; Test v2i64 extractions of an absurd element number.  This must compile
+; but we don't care what it does.
+define i64 @f15(<2 x i64> %val) {
+; CHECK-LABEL: f15:
+; CHECK-NOT: vlgvg %r2, %v24, 100000
+; CHECK: br %r14
+  %ret = extractelement <2 x i64> %val, i32 100000
+  ret i64 %ret
+}
+
+; Test v2i64 extraction of a variable element.
+define i64 @f16(<2 x i64> %val, i32 %index) {
+; CHECK-LABEL: f16:
+; CHECK: vlgvg %r2, %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = extractelement <2 x i64> %val, i32 %index
+  ret i64 %ret
+}
+
+; Test v4f32 extraction of element 0.
+define float @f17(<4 x float> %val) {
+; CHECK-LABEL: f17:
+; CHECK: vlr %v0, %v24
+; CHECK: br %r14
+  %ret = extractelement <4 x float> %val, i32 0
+  ret float %ret
+}
+
+; Test v4f32 extraction of element 1.
+define float @f18(<4 x float> %val) {
+; CHECK-LABEL: f18:
+; CHECK: vrepf %v0, %v24, 1
+; CHECK: br %r14
+  %ret = extractelement <4 x float> %val, i32 1
+  ret float %ret
+}
+
+; Test v4f32 extraction of element 2.
+define float @f19(<4 x float> %val) {
+; CHECK-LABEL: f19:
+; CHECK: vrepf %v0, %v24, 2
+; CHECK: br %r14
+  %ret = extractelement <4 x float> %val, i32 2
+  ret float %ret
+}
+
+; Test v4f32 extraction of element 3.
+define float @f20(<4 x float> %val) {
+; CHECK-LABEL: f20:
+; CHECK: vrepf %v0, %v24, 3
+; CHECK: br %r14
+  %ret = extractelement <4 x float> %val, i32 3
+  ret float %ret
+}
+
+; Test v4f32 extractions of an absurd element number.  This must compile
+; but we don't care what it does.
+define float @f21(<4 x float> %val) {
+  %ret = extractelement <4 x float> %val, i32 100000
+  ret float %ret
+}
+
+; Test v4f32 extraction of a variable element.
+define float @f22(<4 x float> %val, i32 %index) {
+; CHECK-LABEL: f22:
+; CHECK: vlgvf [[REG:%r[0-5]]], %v24, 0(%r2)
+; CHECK: vlvgf %v0, [[REG]], 0
+; CHECK: br %r14
+  %ret = extractelement <4 x float> %val, i32 %index
+  ret float %ret
+}
+
+; Test v2f64 extraction of the first element.
+define double @f23(<2 x double> %val) {
+; CHECK-LABEL: f23:
+; CHECK: vlr %v0, %v24
+; CHECK: br %r14
+  %ret = extractelement <2 x double> %val, i32 0
+  ret double %ret
+}
+
+; Test v2f64 extraction of the last element.
+define double @f24(<2 x double> %val) {
+; CHECK-LABEL: f24:
+; CHECK: vrepg %v0, %v24, 1
+; CHECK: br %r14
+  %ret = extractelement <2 x double> %val, i32 1
+  ret double %ret
+}
+
+; Test v2f64 extractions of an absurd element number.  This must compile
+; but we don't care what it does.
+define double @f25(<2 x double> %val) {
+  %ret = extractelement <2 x double> %val, i32 100000
+  ret double %ret
+}
+
+; Test v2f64 extraction of a variable element.
+define double @f26(<2 x double> %val, i32 %index) {
+; CHECK-LABEL: f26:
+; CHECK: vlgvg [[REG:%r[0-5]]], %v24, 0(%r2)
+; CHECK: ldgr %f0, [[REG]]
+; CHECK: br %r14
+  %ret = extractelement <2 x double> %val, i32 %index
+  ret double %ret
+}
+
+; Test v16i8 extraction of a variable element with an offset.
+define i8 @f27(<16 x i8> %val, i32 %index) {
+; CHECK-LABEL: f27:
+; CHECK: vlgvb %r2, %v24, 1(%r2)
+; CHECK: br %r14
+  %add = add i32 %index, 1
+  %ret = extractelement <16 x i8> %val, i32 %add
+  ret i8 %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-move-06.ll b/test/CodeGen/SystemZ/vec-move-06.ll
new file mode 100644
index 000000000000..de3960cad956
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-06.ll
@@ -0,0 +1,13 @@
+; Test vector builds using VLVGP.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test the basic v2i64 usage.
+define <2 x i64> @f1(i64 %a, i64 %b) {
+; CHECK-LABEL: f1:
+; CHECK: vlvgp %v24, %r2, %r3
+; CHECK: br %r14
+  %veca = insertelement <2 x i64> undef, i64 %a, i32 0
+  %vecb = insertelement <2 x i64> %veca, i64 %b, i32 1
+  ret <2 x i64> %vecb
+}
diff --git a/test/CodeGen/SystemZ/vec-move-07.ll b/test/CodeGen/SystemZ/vec-move-07.ll
new file mode 100644
index 000000000000..b0d06f782dee
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-07.ll
@@ -0,0 +1,57 @@
+; Test scalar_to_vector expansion.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test v16i8.
+define <16 x i8> @f1(i8 %val) {
+; CHECK-LABEL: f1:
+; CHECK: vlvgb %v24, %r2, 0
+; CHECK: br %r14
+  %ret = insertelement <16 x i8> undef, i8 %val, i32 0
+  ret <16 x i8> %ret
+}
+
+; Test v8i16.
+define <8 x i16> @f2(i16 %val) {
+; CHECK-LABEL: f2:
+; CHECK: vlvgh %v24, %r2, 0
+; CHECK: br %r14
+  %ret = insertelement <8 x i16> undef, i16 %val, i32 0
+  ret <8 x i16> %ret
+}
+
+; Test v4i32.
+define <4 x i32> @f3(i32 %val) {
+; CHECK-LABEL: f3:
+; CHECK: vlvgf %v24, %r2, 0
+; CHECK: br %r14
+  %ret = insertelement <4 x i32> undef, i32 %val, i32 0
+  ret <4 x i32> %ret
+}
+
+; Test v2i64.  Here we load %val into both halves.
+define <2 x i64> @f4(i64 %val) {
+; CHECK-LABEL: f4:
+; CHECK: vlvgp %v24, %r2, %r2
+; CHECK: br %r14
+  %ret = insertelement <2 x i64> undef, i64 %val, i32 0
+  ret <2 x i64> %ret
+}
+
+; Test v4f32, which is just a move.
+define <4 x float> @f5(float %val) {
+; CHECK-LABEL: f5:
+; CHECK: vlr %v24, %v0
+; CHECK: br %r14
+  %ret = insertelement <4 x float> undef, float %val, i32 0
+  ret <4 x float> %ret
+}
+
+; Likewise v2f64.
+define <2 x double> @f6(double %val) {
+; CHECK-LABEL: f6:
+; CHECK: vlr %v24, %v0
+; CHECK: br %r14
+  %ret = insertelement <2 x double> undef, double %val, i32 0
+  ret <2 x double> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-move-08.ll b/test/CodeGen/SystemZ/vec-move-08.ll
new file mode 100644
index 000000000000..5396a1edec6a
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-08.ll
@@ -0,0 +1,444 @@
+; Test vector insertion of memory values.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test v16i8 insertion into the first element.
+define <16 x i8> @f1(<16 x i8> %val, i8 *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: vleb %v24, 0(%r2), 0
+; CHECK: br %r14
+  %element = load i8, i8 *%ptr
+  %ret = insertelement <16 x i8> %val, i8 %element, i32 0
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 insertion into the last element.
+define <16 x i8> @f2(<16 x i8> %val, i8 *%ptr) {
+; CHECK-LABEL: f2:
+; CHECK: vleb %v24, 0(%r2), 15
+; CHECK: br %r14
+  %element = load i8, i8 *%ptr
+  %ret = insertelement <16 x i8> %val, i8 %element, i32 15
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 insertion with the highest in-range offset.
+define <16 x i8> @f3(<16 x i8> %val, i8 *%base) {
+; CHECK-LABEL: f3:
+; CHECK: vleb %v24, 4095(%r2), 10
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i32 4095
+  %element = load i8, i8 *%ptr
+  %ret = insertelement <16 x i8> %val, i8 %element, i32 10
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 insertion with the first ouf-of-range offset.
+define <16 x i8> @f4(<16 x i8> %val, i8 *%base) {
+; CHECK-LABEL: f4:
+; CHECK: aghi %r2, 4096
+; CHECK: vleb %v24, 0(%r2), 5
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i32 4096
+  %element = load i8, i8 *%ptr
+  %ret = insertelement <16 x i8> %val, i8 %element, i32 5
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 insertion into a variable element.
+define <16 x i8> @f5(<16 x i8> %val, i8 *%ptr, i32 %index) {
+; CHECK-LABEL: f5:
+; CHECK-NOT: vleb
+; CHECK: br %r14
+  %element = load i8, i8 *%ptr
+  %ret = insertelement <16 x i8> %val, i8 %element, i32 %index
+  ret <16 x i8> %ret
+}
+
+; Test v8i16 insertion into the first element.
+define <8 x i16> @f6(<8 x i16> %val, i16 *%ptr) {
+; CHECK-LABEL: f6:
+; CHECK: vleh %v24, 0(%r2), 0
+; CHECK: br %r14
+  %element = load i16, i16 *%ptr
+  %ret = insertelement <8 x i16> %val, i16 %element, i32 0
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 insertion into the last element.
+define <8 x i16> @f7(<8 x i16> %val, i16 *%ptr) {
+; CHECK-LABEL: f7:
+; CHECK: vleh %v24, 0(%r2), 7
+; CHECK: br %r14
+  %element = load i16, i16 *%ptr
+  %ret = insertelement <8 x i16> %val, i16 %element, i32 7
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 insertion with the highest in-range offset.
+define <8 x i16> @f8(<8 x i16> %val, i16 *%base) {
+; CHECK-LABEL: f8:
+; CHECK: vleh %v24, 4094(%r2), 5
+; CHECK: br %r14
+  %ptr = getelementptr i16, i16 *%base, i32 2047
+  %element = load i16, i16 *%ptr
+  %ret = insertelement <8 x i16> %val, i16 %element, i32 5
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 insertion with the first ouf-of-range offset.
+define <8 x i16> @f9(<8 x i16> %val, i16 *%base) {
+; CHECK-LABEL: f9:
+; CHECK: aghi %r2, 4096
+; CHECK: vleh %v24, 0(%r2), 1
+; CHECK: br %r14
+  %ptr = getelementptr i16, i16 *%base, i32 2048
+  %element = load i16, i16 *%ptr
+  %ret = insertelement <8 x i16> %val, i16 %element, i32 1
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 insertion into a variable element.
+define <8 x i16> @f10(<8 x i16> %val, i16 *%ptr, i32 %index) {
+; CHECK-LABEL: f10:
+; CHECK-NOT: vleh
+; CHECK: br %r14
+  %element = load i16, i16 *%ptr
+  %ret = insertelement <8 x i16> %val, i16 %element, i32 %index
+  ret <8 x i16> %ret
+}
+
+; Test v4i32 insertion into the first element.
+define <4 x i32> @f11(<4 x i32> %val, i32 *%ptr) {
+; CHECK-LABEL: f11:
+; CHECK: vlef %v24, 0(%r2), 0
+; CHECK: br %r14
+  %element = load i32, i32 *%ptr
+  %ret = insertelement <4 x i32> %val, i32 %element, i32 0
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion into the last element.
+define <4 x i32> @f12(<4 x i32> %val, i32 *%ptr) {
+; CHECK-LABEL: f12:
+; CHECK: vlef %v24, 0(%r2), 3
+; CHECK: br %r14
+  %element = load i32, i32 *%ptr
+  %ret = insertelement <4 x i32> %val, i32 %element, i32 3
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion with the highest in-range offset.
+define <4 x i32> @f13(<4 x i32> %val, i32 *%base) {
+; CHECK-LABEL: f13:
+; CHECK: vlef %v24, 4092(%r2), 2
+; CHECK: br %r14
+  %ptr = getelementptr i32, i32 *%base, i32 1023
+  %element = load i32, i32 *%ptr
+  %ret = insertelement <4 x i32> %val, i32 %element, i32 2
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion with the first ouf-of-range offset.
+define <4 x i32> @f14(<4 x i32> %val, i32 *%base) {
+; CHECK-LABEL: f14:
+; CHECK: aghi %r2, 4096
+; CHECK: vlef %v24, 0(%r2), 1
+; CHECK: br %r14
+  %ptr = getelementptr i32, i32 *%base, i32 1024
+  %element = load i32, i32 *%ptr
+  %ret = insertelement <4 x i32> %val, i32 %element, i32 1
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion into a variable element.
+define <4 x i32> @f15(<4 x i32> %val, i32 *%ptr, i32 %index) {
+; CHECK-LABEL: f15:
+; CHECK-NOT: vlef
+; CHECK: br %r14
+  %element = load i32, i32 *%ptr
+  %ret = insertelement <4 x i32> %val, i32 %element, i32 %index
+  ret <4 x i32> %ret
+}
+
+; Test v2i64 insertion into the first element.
+define <2 x i64> @f16(<2 x i64> %val, i64 *%ptr) {
+; CHECK-LABEL: f16:
+; CHECK: vleg %v24, 0(%r2), 0
+; CHECK: br %r14
+  %element = load i64, i64 *%ptr
+  %ret = insertelement <2 x i64> %val, i64 %element, i32 0
+  ret <2 x i64> %ret
+}
+
+; Test v2i64 insertion into the last element.
+define <2 x i64> @f17(<2 x i64> %val, i64 *%ptr) {
+; CHECK-LABEL: f17:
+; CHECK: vleg %v24, 0(%r2), 1
+; CHECK: br %r14
+  %element = load i64, i64 *%ptr
+  %ret = insertelement <2 x i64> %val, i64 %element, i32 1
+  ret <2 x i64> %ret
+}
+
+; Test v2i64 insertion with the highest in-range offset.
+define <2 x i64> @f18(<2 x i64> %val, i64 *%base) {
+; CHECK-LABEL: f18:
+; CHECK: vleg %v24, 4088(%r2), 1
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i32 511
+  %element = load i64, i64 *%ptr
+  %ret = insertelement <2 x i64> %val, i64 %element, i32 1
+  ret <2 x i64> %ret
+}
+
+; Test v2i64 insertion with the first ouf-of-range offset.
+define <2 x i64> @f19(<2 x i64> %val, i64 *%base) {
+; CHECK-LABEL: f19:
+; CHECK: aghi %r2, 4096
+; CHECK: vleg %v24, 0(%r2), 0
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i32 512
+  %element = load i64, i64 *%ptr
+  %ret = insertelement <2 x i64> %val, i64 %element, i32 0
+  ret <2 x i64> %ret
+}
+
+; Test v2i64 insertion into a variable element.
+define <2 x i64> @f20(<2 x i64> %val, i64 *%ptr, i32 %index) {
+; CHECK-LABEL: f20:
+; CHECK-NOT: vleg
+; CHECK: br %r14
+  %element = load i64, i64 *%ptr
+  %ret = insertelement <2 x i64> %val, i64 %element, i32 %index
+  ret <2 x i64> %ret
+}
+
+; Test v4f32 insertion into the first element.
+define <4 x float> @f21(<4 x float> %val, float *%ptr) {
+; CHECK-LABEL: f21:
+; CHECK: vlef %v24, 0(%r2), 0
+; CHECK: br %r14
+  %element = load float, float *%ptr
+  %ret = insertelement <4 x float> %val, float %element, i32 0
+  ret <4 x float> %ret
+}
+
+; Test v4f32 insertion into the last element.
+define <4 x float> @f22(<4 x float> %val, float *%ptr) {
+; CHECK-LABEL: f22:
+; CHECK: vlef %v24, 0(%r2), 3
+; CHECK: br %r14
+  %element = load float, float *%ptr
+  %ret = insertelement <4 x float> %val, float %element, i32 3
+  ret <4 x float> %ret
+}
+
+; Test v4f32 insertion with the highest in-range offset.
+define <4 x float> @f23(<4 x float> %val, float *%base) {
+; CHECK-LABEL: f23:
+; CHECK: vlef %v24, 4092(%r2), 2
+; CHECK: br %r14
+  %ptr = getelementptr float, float *%base, i32 1023
+  %element = load float, float *%ptr
+  %ret = insertelement <4 x float> %val, float %element, i32 2
+  ret <4 x float> %ret
+}
+
+; Test v4f32 insertion with the first ouf-of-range offset.
+define <4 x float> @f24(<4 x float> %val, float *%base) {
+; CHECK-LABEL: f24:
+; CHECK: aghi %r2, 4096
+; CHECK: vlef %v24, 0(%r2), 1
+; CHECK: br %r14
+  %ptr = getelementptr float, float *%base, i32 1024
+  %element = load float, float *%ptr
+  %ret = insertelement <4 x float> %val, float %element, i32 1
+  ret <4 x float> %ret
+}
+
+; Test v4f32 insertion into a variable element.
+define <4 x float> @f25(<4 x float> %val, float *%ptr, i32 %index) {
+; CHECK-LABEL: f25:
+; CHECK-NOT: vlef
+; CHECK: br %r14
+  %element = load float, float *%ptr
+  %ret = insertelement <4 x float> %val, float %element, i32 %index
+  ret <4 x float> %ret
+}
+
+; Test v2f64 insertion into the first element.
+define <2 x double> @f26(<2 x double> %val, double *%ptr) {
+; CHECK-LABEL: f26:
+; CHECK: vleg %v24, 0(%r2), 0
+; CHECK: br %r14
+  %element = load double, double *%ptr
+  %ret = insertelement <2 x double> %val, double %element, i32 0
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion into the last element.
+define <2 x double> @f27(<2 x double> %val, double *%ptr) {
+; CHECK-LABEL: f27:
+; CHECK: vleg %v24, 0(%r2), 1
+; CHECK: br %r14
+  %element = load double, double *%ptr
+  %ret = insertelement <2 x double> %val, double %element, i32 1
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion with the highest in-range offset.
+define <2 x double> @f28(<2 x double> %val, double *%base) {
+; CHECK-LABEL: f28:
+; CHECK: vleg %v24, 4088(%r2), 1
+; CHECK: br %r14
+  %ptr = getelementptr double, double *%base, i32 511
+  %element = load double, double *%ptr
+  %ret = insertelement <2 x double> %val, double %element, i32 1
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion with the first ouf-of-range offset.
+define <2 x double> @f29(<2 x double> %val, double *%base) {
+; CHECK-LABEL: f29:
+; CHECK: aghi %r2, 4096
+; CHECK: vleg %v24, 0(%r2), 0
+; CHECK: br %r14
+  %ptr = getelementptr double, double *%base, i32 512
+  %element = load double, double *%ptr
+  %ret = insertelement <2 x double> %val, double %element, i32 0
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion into a variable element.
+define <2 x double> @f30(<2 x double> %val, double *%ptr, i32 %index) {
+; CHECK-LABEL: f30:
+; CHECK-NOT: vleg
+; CHECK: br %r14
+  %element = load double, double *%ptr
+  %ret = insertelement <2 x double> %val, double %element, i32 %index
+  ret <2 x double> %ret
+}
+
+; Test a v4i32 gather of the first element.
+define <4 x i32> @f31(<4 x i32> %val, <4 x i32> %index, i64 %base) {
+; CHECK-LABEL: f31:
+; CHECK: vgef %v24, 0(%v26,%r2), 0
+; CHECK: br %r14
+  %elem = extractelement <4 x i32> %index, i32 0
+  %ext = zext i32 %elem to i64
+  %add = add i64 %base, %ext
+  %ptr = inttoptr i64 %add to i32 *
+  %element = load i32, i32 *%ptr
+  %ret = insertelement <4 x i32> %val, i32 %element, i32 0
+  ret <4 x i32> %ret
+}
+
+; Test a v4i32 gather of the last element.
+define <4 x i32> @f32(<4 x i32> %val, <4 x i32> %index, i64 %base) {
+; CHECK-LABEL: f32:
+; CHECK: vgef %v24, 0(%v26,%r2), 3
+; CHECK: br %r14
+  %elem = extractelement <4 x i32> %index, i32 3
+  %ext = zext i32 %elem to i64
+  %add = add i64 %base, %ext
+  %ptr = inttoptr i64 %add to i32 *
+  %element = load i32, i32 *%ptr
+  %ret = insertelement <4 x i32> %val, i32 %element, i32 3
+  ret <4 x i32> %ret
+}
+
+; Test a v4i32 gather with the highest in-range offset.
+define <4 x i32> @f33(<4 x i32> %val, <4 x i32> %index, i64 %base) {
+; CHECK-LABEL: f33:
+; CHECK: vgef %v24, 4095(%v26,%r2), 1
+; CHECK: br %r14
+  %elem = extractelement <4 x i32> %index, i32 1
+  %ext = zext i32 %elem to i64
+  %add1 = add i64 %base, %ext
+  %add2 = add i64 %add1, 4095
+  %ptr = inttoptr i64 %add2 to i32 *
+  %element = load i32, i32 *%ptr
+  %ret = insertelement <4 x i32> %val, i32 %element, i32 1
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 gather of the first element.
+define <2 x i64> @f34(<2 x i64> %val, <2 x i64> %index, i64 %base) {
+; CHECK-LABEL: f34:
+; CHECK: vgeg %v24, 0(%v26,%r2), 0
+; CHECK: br %r14
+  %elem = extractelement <2 x i64> %index, i32 0
+  %add = add i64 %base, %elem
+  %ptr = inttoptr i64 %add to i64 *
+  %element = load i64, i64 *%ptr
+  %ret = insertelement <2 x i64> %val, i64 %element, i32 0
+  ret <2 x i64> %ret
+}
+
+; Test a v2i64 gather of the last element.
+define <2 x i64> @f35(<2 x i64> %val, <2 x i64> %index, i64 %base) {
+; CHECK-LABEL: f35:
+; CHECK: vgeg %v24, 0(%v26,%r2), 1
+; CHECK: br %r14
+  %elem = extractelement <2 x i64> %index, i32 1
+  %add = add i64 %base, %elem
+  %ptr = inttoptr i64 %add to i64 *
+  %element = load i64, i64 *%ptr
+  %ret = insertelement <2 x i64> %val, i64 %element, i32 1
+  ret <2 x i64> %ret
+}
+
+; Test a v4f32 gather of the first element.
+define <4 x float> @f36(<4 x float> %val, <4 x i32> %index, i64 %base) {
+; CHECK-LABEL: f36:
+; CHECK: vgef %v24, 0(%v26,%r2), 0
+; CHECK: br %r14
+  %elem = extractelement <4 x i32> %index, i32 0
+  %ext = zext i32 %elem to i64
+  %add = add i64 %base, %ext
+  %ptr = inttoptr i64 %add to float *
+  %element = load float, float *%ptr
+  %ret = insertelement <4 x float> %val, float %element, i32 0
+  ret <4 x float> %ret
+}
+
+; Test a v4f32 gather of the last element.
+define <4 x float> @f37(<4 x float> %val, <4 x i32> %index, i64 %base) {
+; CHECK-LABEL: f37:
+; CHECK: vgef %v24, 0(%v26,%r2), 3
+; CHECK: br %r14
+  %elem = extractelement <4 x i32> %index, i32 3
+  %ext = zext i32 %elem to i64
+  %add = add i64 %base, %ext
+  %ptr = inttoptr i64 %add to float *
+  %element = load float, float *%ptr
+  %ret = insertelement <4 x float> %val, float %element, i32 3
+  ret <4 x float> %ret
+}
+
+; Test a v2f64 gather of the first element.
+define <2 x double> @f38(<2 x double> %val, <2 x i64> %index, i64 %base) {
+; CHECK-LABEL: f38:
+; CHECK: vgeg %v24, 0(%v26,%r2), 0
+; CHECK: br %r14
+  %elem = extractelement <2 x i64> %index, i32 0
+  %add = add i64 %base, %elem
+  %ptr = inttoptr i64 %add to double *
+  %element = load double, double *%ptr
+  %ret = insertelement <2 x double> %val, double %element, i32 0
+  ret <2 x double> %ret
+}
+
+; Test a v2f64 gather of the last element.
+define <2 x double> @f39(<2 x double> %val, <2 x i64> %index, i64 %base) {
+; CHECK-LABEL: f39:
+; CHECK: vgeg %v24, 0(%v26,%r2), 1
+; CHECK: br %r14
+  %elem = extractelement <2 x i64> %index, i32 1
+  %add = add i64 %base, %elem
+  %ptr = inttoptr i64 %add to double *
+  %element = load double, double *%ptr
+  %ret = insertelement <2 x double> %val, double %element, i32 1
+  ret <2 x double> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-move-09.ll b/test/CodeGen/SystemZ/vec-move-09.ll
new file mode 100644
index 000000000000..5a53a2d6a198
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-09.ll
@@ -0,0 +1,291 @@
+; Test vector insertion of constants.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test v16i8 insertion into the first element.
+define <16 x i8> @f1(<16 x i8> %val) {
+; CHECK-LABEL: f1:
+; CHECK: vleib %v24, 0, 0
+; CHECK: br %r14
+  %ret = insertelement <16 x i8> %val, i8 0, i32 0
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 insertion into the last element.
+define <16 x i8> @f2(<16 x i8> %val) {
+; CHECK-LABEL: f2:
+; CHECK: vleib %v24, 100, 15
+; CHECK: br %r14
+  %ret = insertelement <16 x i8> %val, i8 100, i32 15
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 insertion with the maximum signed value.
+define <16 x i8> @f3(<16 x i8> %val) {
+; CHECK-LABEL: f3:
+; CHECK: vleib %v24, 127, 10
+; CHECK: br %r14
+  %ret = insertelement <16 x i8> %val, i8 127, i32 10
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 insertion with the minimum signed value.
+define <16 x i8> @f4(<16 x i8> %val) {
+; CHECK-LABEL: f4:
+; CHECK: vleib %v24, -128, 11
+; CHECK: br %r14
+  %ret = insertelement <16 x i8> %val, i8 128, i32 11
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 insertion with the maximum unsigned value.
+define <16 x i8> @f5(<16 x i8> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vleib %v24, -1, 12
+; CHECK: br %r14
+  %ret = insertelement <16 x i8> %val, i8 255, i32 12
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 insertion into a variable element.
+define <16 x i8> @f6(<16 x i8> %val, i32 %index) {
+; CHECK-LABEL: f6:
+; CHECK-NOT: vleib
+; CHECK: br %r14
+  %ret = insertelement <16 x i8> %val, i8 0, i32 %index
+  ret <16 x i8> %ret
+}
+
+; Test v8i16 insertion into the first element.
+define <8 x i16> @f7(<8 x i16> %val) {
+; CHECK-LABEL: f7:
+; CHECK: vleih %v24, 0, 0
+; CHECK: br %r14
+  %ret = insertelement <8 x i16> %val, i16 0, i32 0
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 insertion into the last element.
+define <8 x i16> @f8(<8 x i16> %val) {
+; CHECK-LABEL: f8:
+; CHECK: vleih %v24, 0, 7
+; CHECK: br %r14
+  %ret = insertelement <8 x i16> %val, i16 0, i32 7
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 insertion with the maximum signed value.
+define <8 x i16> @f9(<8 x i16> %val) {
+; CHECK-LABEL: f9:
+; CHECK: vleih %v24, 32767, 4
+; CHECK: br %r14
+  %ret = insertelement <8 x i16> %val, i16 32767, i32 4
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 insertion with the minimum signed value.
+define <8 x i16> @f10(<8 x i16> %val) {
+; CHECK-LABEL: f10:
+; CHECK: vleih %v24, -32768, 5
+; CHECK: br %r14
+  %ret = insertelement <8 x i16> %val, i16 32768, i32 5
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 insertion with the maximum unsigned value.
+define <8 x i16> @f11(<8 x i16> %val) {
+; CHECK-LABEL: f11:
+; CHECK: vleih %v24, -1, 6
+; CHECK: br %r14
+  %ret = insertelement <8 x i16> %val, i16 65535, i32 6
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 insertion into a variable element.
+define <8 x i16> @f12(<8 x i16> %val, i32 %index) {
+; CHECK-LABEL: f12:
+; CHECK-NOT: vleih
+; CHECK: br %r14
+  %ret = insertelement <8 x i16> %val, i16 0, i32 %index
+  ret <8 x i16> %ret
+}
+
+; Test v4i32 insertion into the first element.
+define <4 x i32> @f13(<4 x i32> %val) {
+; CHECK-LABEL: f13:
+; CHECK: vleif %v24, 0, 0
+; CHECK: br %r14
+  %ret = insertelement <4 x i32> %val, i32 0, i32 0
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion into the last element.
+define <4 x i32> @f14(<4 x i32> %val) {
+; CHECK-LABEL: f14:
+; CHECK: vleif %v24, 0, 3
+; CHECK: br %r14
+  %ret = insertelement <4 x i32> %val, i32 0, i32 3
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion with the maximum value allowed by VLEIF.
+define <4 x i32> @f15(<4 x i32> %val) {
+; CHECK-LABEL: f15:
+; CHECK: vleif %v24, 32767, 1
+; CHECK: br %r14
+  %ret = insertelement <4 x i32> %val, i32 32767, i32 1
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion with the next value up.
+define <4 x i32> @f16(<4 x i32> %val) {
+; CHECK-LABEL: f16:
+; CHECK-NOT: vleif
+; CHECK: br %r14
+  %ret = insertelement <4 x i32> %val, i32 32768, i32 1
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion with the minimum value allowed by VLEIF.
+define <4 x i32> @f17(<4 x i32> %val) {
+; CHECK-LABEL: f17:
+; CHECK: vleif %v24, -32768, 2
+; CHECK: br %r14
+  %ret = insertelement <4 x i32> %val, i32 -32768, i32 2
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion with the next value down.
+define <4 x i32> @f18(<4 x i32> %val) {
+; CHECK-LABEL: f18:
+; CHECK-NOT: vleif
+; CHECK: br %r14
+  %ret = insertelement <4 x i32> %val, i32 -32769, i32 2
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion into a variable element.
+define <4 x i32> @f19(<4 x i32> %val, i32 %index) {
+; CHECK-LABEL: f19:
+; CHECK-NOT: vleif
+; CHECK: br %r14
+  %ret = insertelement <4 x i32> %val, i32 0, i32 %index
+  ret <4 x i32> %ret
+}
+
+; Test v2i64 insertion into the first element.
+define <2 x i64> @f20(<2 x i64> %val) {
+; CHECK-LABEL: f20:
+; CHECK: vleig %v24, 0, 0
+; CHECK: br %r14
+  %ret = insertelement <2 x i64> %val, i64 0, i32 0
+  ret <2 x i64> %ret
+}
+
+; Test v2i64 insertion into the last element.
+define <2 x i64> @f21(<2 x i64> %val) {
+; CHECK-LABEL: f21:
+; CHECK: vleig %v24, 0, 1
+; CHECK: br %r14
+  %ret = insertelement <2 x i64> %val, i64 0, i32 1
+  ret <2 x i64> %ret
+}
+
+; Test v2i64 insertion with the maximum value allowed by VLEIG.
+define <2 x i64> @f22(<2 x i64> %val) {
+; CHECK-LABEL: f22:
+; CHECK: vleig %v24, 32767, 1
+; CHECK: br %r14
+  %ret = insertelement <2 x i64> %val, i64 32767, i32 1
+  ret <2 x i64> %ret
+}
+
+; Test v2i64 insertion with the next value up.
+define <2 x i64> @f23(<2 x i64> %val) {
+; CHECK-LABEL: f23:
+; CHECK-NOT: vleig
+; CHECK: br %r14
+  %ret = insertelement <2 x i64> %val, i64 32768, i32 1
+  ret <2 x i64> %ret
+}
+
+; Test v2i64 insertion with the minimum value allowed by VLEIG.
+define <2 x i64> @f24(<2 x i64> %val) {
+; CHECK-LABEL: f24:
+; CHECK: vleig %v24, -32768, 0
+; CHECK: br %r14
+  %ret = insertelement <2 x i64> %val, i64 -32768, i32 0
+  ret <2 x i64> %ret
+}
+
+; Test v2i64 insertion with the next value down.
+define <2 x i64> @f25(<2 x i64> %val) {
+; CHECK-LABEL: f25:
+; CHECK-NOT: vleig
+; CHECK: br %r14
+  %ret = insertelement <2 x i64> %val, i64 -32769, i32 0
+  ret <2 x i64> %ret
+}
+
+; Test v2i64 insertion into a variable element.
+define <2 x i64> @f26(<2 x i64> %val, i32 %index) {
+; CHECK-LABEL: f26:
+; CHECK-NOT: vleig
+; CHECK: br %r14
+  %ret = insertelement <2 x i64> %val, i64 0, i32 %index
+  ret <2 x i64> %ret
+}
+
+; Test v4f32 insertion of 0 into the first element.
+define <4 x float> @f27(<4 x float> %val) {
+; CHECK-LABEL: f27:
+; CHECK: vleif %v24, 0, 0
+; CHECK: br %r14
+  %ret = insertelement <4 x float> %val, float 0.0, i32 0
+  ret <4 x float> %ret
+}
+
+; Test v4f32 insertion of 0 into the last element.
+define <4 x float> @f28(<4 x float> %val) {
+; CHECK-LABEL: f28:
+; CHECK: vleif %v24, 0, 3
+; CHECK: br %r14
+  %ret = insertelement <4 x float> %val, float 0.0, i32 3
+  ret <4 x float> %ret
+}
+
+; Test v4f32 insertion of a nonzero value.
+define <4 x float> @f29(<4 x float> %val) {
+; CHECK-LABEL: f29:
+; CHECK-NOT: vleif
+; CHECK: br %r14
+  %ret = insertelement <4 x float> %val, float 1.0, i32 1
+  ret <4 x float> %ret
+}
+
+; Test v2f64 insertion of 0 into the first element.
+define <2 x double> @f30(<2 x double> %val) {
+; CHECK-LABEL: f30:
+; CHECK: vleig %v24, 0, 0
+; CHECK: br %r14
+  %ret = insertelement <2 x double> %val, double 0.0, i32 0
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion of 0 into the last element.
+define <2 x double> @f31(<2 x double> %val) {
+; CHECK-LABEL: f31:
+; CHECK: vleig %v24, 0, 1
+; CHECK: br %r14
+  %ret = insertelement <2 x double> %val, double 0.0, i32 1
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion of a nonzero value.
+define <2 x double> @f32(<2 x double> %val) {
+; CHECK-LABEL: f32:
+; CHECK-NOT: vleig
+; CHECK: br %r14
+  %ret = insertelement <2 x double> %val, double 1.0, i32 1
+  ret <2 x double> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-move-10.ll b/test/CodeGen/SystemZ/vec-move-10.ll
new file mode 100644
index 000000000000..894d0c2b41fa
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-10.ll
@@ -0,0 +1,499 @@
+; Test vector extraction to memory.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test v16i8 extraction from the first element.
+define void @f1(<16 x i8> %val, i8 *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: vsteb %v24, 0(%r2), 0
+; CHECK: br %r14
+  %element = extractelement <16 x i8> %val, i32 0
+  store i8 %element, i8 *%ptr
+  ret void
+}
+
+; Test v16i8 extraction from the last element.
+define void @f2(<16 x i8> %val, i8 *%ptr) {
+; CHECK-LABEL: f2:
+; CHECK: vsteb %v24, 0(%r2), 15
+; CHECK: br %r14
+  %element = extractelement <16 x i8> %val, i32 15
+  store i8 %element, i8 *%ptr
+  ret void
+}
+
+; Test v16i8 extraction of an invalid element.  This must compile,
+; but we don't care what it does.
+define void @f3(<16 x i8> %val, i8 *%ptr) {
+; CHECK-LABEL: f3:
+; CHECK-NOT: vsteb %v24, 0(%r2), 16
+; CHECK: br %r14
+  %element = extractelement <16 x i8> %val, i32 16
+  store i8 %element, i8 *%ptr
+  ret void
+}
+
+; Test v16i8 extraction with the highest in-range offset.
+define void @f4(<16 x i8> %val, i8 *%base) {
+; CHECK-LABEL: f4:
+; CHECK: vsteb %v24, 4095(%r2), 10
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i32 4095
+  %element = extractelement <16 x i8> %val, i32 10
+  store i8 %element, i8 *%ptr
+  ret void
+}
+
+; Test v16i8 extraction with the first ouf-of-range offset.
+define void @f5(<16 x i8> %val, i8 *%base) {
+; CHECK-LABEL: f5:
+; CHECK: aghi %r2, 4096
+; CHECK: vsteb %v24, 0(%r2), 5
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i32 4096
+  %element = extractelement <16 x i8> %val, i32 5
+  store i8 %element, i8 *%ptr
+  ret void
+}
+
+; Test v16i8 extraction from a variable element.
+define void @f6(<16 x i8> %val, i8 *%ptr, i32 %index) {
+; CHECK-LABEL: f6:
+; CHECK-NOT: vsteb
+; CHECK: br %r14
+  %element = extractelement <16 x i8> %val, i32 %index
+  store i8 %element, i8 *%ptr
+  ret void
+}
+
+; Test v8i16 extraction from the first element.
+define void @f7(<8 x i16> %val, i16 *%ptr) {
+; CHECK-LABEL: f7:
+; CHECK: vsteh %v24, 0(%r2), 0
+; CHECK: br %r14
+  %element = extractelement <8 x i16> %val, i32 0
+  store i16 %element, i16 *%ptr
+  ret void
+}
+
+; Test v8i16 extraction from the last element.
+define void @f8(<8 x i16> %val, i16 *%ptr) {
+; CHECK-LABEL: f8:
+; CHECK: vsteh %v24, 0(%r2), 7
+; CHECK: br %r14
+  %element = extractelement <8 x i16> %val, i32 7
+  store i16 %element, i16 *%ptr
+  ret void
+}
+
+; Test v8i16 extraction of an invalid element.  This must compile,
+; but we don't care what it does.
+define void @f9(<8 x i16> %val, i16 *%ptr) {
+; CHECK-LABEL: f9:
+; CHECK-NOT: vsteh %v24, 0(%r2), 8
+; CHECK: br %r14
+  %element = extractelement <8 x i16> %val, i32 8
+  store i16 %element, i16 *%ptr
+  ret void
+}
+
+; Test v8i16 extraction with the highest in-range offset.
+define void @f10(<8 x i16> %val, i16 *%base) {
+; CHECK-LABEL: f10:
+; CHECK: vsteh %v24, 4094(%r2), 5
+; CHECK: br %r14
+  %ptr = getelementptr i16, i16 *%base, i32 2047
+  %element = extractelement <8 x i16> %val, i32 5
+  store i16 %element, i16 *%ptr
+  ret void
+}
+
+; Test v8i16 extraction with the first ouf-of-range offset.
+define void @f11(<8 x i16> %val, i16 *%base) {
+; CHECK-LABEL: f11:
+; CHECK: aghi %r2, 4096
+; CHECK: vsteh %v24, 0(%r2), 1
+; CHECK: br %r14
+  %ptr = getelementptr i16, i16 *%base, i32 2048
+  %element = extractelement <8 x i16> %val, i32 1
+  store i16 %element, i16 *%ptr
+  ret void
+}
+
+; Test v8i16 extraction from a variable element.
+define void @f12(<8 x i16> %val, i16 *%ptr, i32 %index) {
+; CHECK-LABEL: f12:
+; CHECK-NOT: vsteh
+; CHECK: br %r14
+  %element = extractelement <8 x i16> %val, i32 %index
+  store i16 %element, i16 *%ptr
+  ret void
+}
+
+; Test v4i32 extraction from the first element.
+define void @f13(<4 x i32> %val, i32 *%ptr) {
+; CHECK-LABEL: f13:
+; CHECK: vstef %v24, 0(%r2), 0
+; CHECK: br %r14
+  %element = extractelement <4 x i32> %val, i32 0
+  store i32 %element, i32 *%ptr
+  ret void
+}
+
+; Test v4i32 extraction from the last element.
+define void @f14(<4 x i32> %val, i32 *%ptr) {
+; CHECK-LABEL: f14:
+; CHECK: vstef %v24, 0(%r2), 3
+; CHECK: br %r14
+  %element = extractelement <4 x i32> %val, i32 3
+  store i32 %element, i32 *%ptr
+  ret void
+}
+
+; Test v4i32 extraction of an invalid element.  This must compile,
+; but we don't care what it does.
+define void @f15(<4 x i32> %val, i32 *%ptr) {
+; CHECK-LABEL: f15:
+; CHECK-NOT: vstef %v24, 0(%r2), 4
+; CHECK: br %r14
+  %element = extractelement <4 x i32> %val, i32 4
+  store i32 %element, i32 *%ptr
+  ret void
+}
+
+; Test v4i32 extraction with the highest in-range offset.
+define void @f16(<4 x i32> %val, i32 *%base) {
+; CHECK-LABEL: f16:
+; CHECK: vstef %v24, 4092(%r2), 2
+; CHECK: br %r14
+  %ptr = getelementptr i32, i32 *%base, i32 1023
+  %element = extractelement <4 x i32> %val, i32 2
+  store i32 %element, i32 *%ptr
+  ret void
+}
+
+; Test v4i32 extraction with the first ouf-of-range offset.
+define void @f17(<4 x i32> %val, i32 *%base) {
+; CHECK-LABEL: f17:
+; CHECK: aghi %r2, 4096
+; CHECK: vstef %v24, 0(%r2), 1
+; CHECK: br %r14
+  %ptr = getelementptr i32, i32 *%base, i32 1024
+  %element = extractelement <4 x i32> %val, i32 1
+  store i32 %element, i32 *%ptr
+  ret void
+}
+
+; Test v4i32 extraction from a variable element.
+define void @f18(<4 x i32> %val, i32 *%ptr, i32 %index) {
+; CHECK-LABEL: f18:
+; CHECK-NOT: vstef
+; CHECK: br %r14
+  %element = extractelement <4 x i32> %val, i32 %index
+  store i32 %element, i32 *%ptr
+  ret void
+}
+
+; Test v2i64 extraction from the first element.
+define void @f19(<2 x i64> %val, i64 *%ptr) {
+; CHECK-LABEL: f19:
+; CHECK: vsteg %v24, 0(%r2), 0
+; CHECK: br %r14
+  %element = extractelement <2 x i64> %val, i32 0
+  store i64 %element, i64 *%ptr
+  ret void
+}
+
+; Test v2i64 extraction from the last element.
+define void @f20(<2 x i64> %val, i64 *%ptr) {
+; CHECK-LABEL: f20:
+; CHECK: vsteg %v24, 0(%r2), 1
+; CHECK: br %r14
+  %element = extractelement <2 x i64> %val, i32 1
+  store i64 %element, i64 *%ptr
+  ret void
+}
+
+; Test v2i64 extraction of an invalid element.  This must compile,
+; but we don't care what it does.
+define void @f21(<2 x i64> %val, i64 *%ptr) {
+; CHECK-LABEL: f21:
+; CHECK-NOT: vsteg %v24, 0(%r2), 2
+; CHECK: br %r14
+  %element = extractelement <2 x i64> %val, i32 2
+  store i64 %element, i64 *%ptr
+  ret void
+}
+
+; Test v2i64 extraction with the highest in-range offset.
+define void @f22(<2 x i64> %val, i64 *%base) {
+; CHECK-LABEL: f22:
+; CHECK: vsteg %v24, 4088(%r2), 1
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i32 511
+  %element = extractelement <2 x i64> %val, i32 1
+  store i64 %element, i64 *%ptr
+  ret void
+}
+
+; Test v2i64 extraction with the first ouf-of-range offset.
+define void @f23(<2 x i64> %val, i64 *%base) {
+; CHECK-LABEL: f23:
+; CHECK: aghi %r2, 4096
+; CHECK: vsteg %v24, 0(%r2), 0
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i32 512
+  %element = extractelement <2 x i64> %val, i32 0
+  store i64 %element, i64 *%ptr
+  ret void
+}
+
+; Test v2i64 extraction from a variable element.
+define void @f24(<2 x i64> %val, i64 *%ptr, i32 %index) {
+; CHECK-LABEL: f24:
+; CHECK-NOT: vsteg
+; CHECK: br %r14
+  %element = extractelement <2 x i64> %val, i32 %index
+  store i64 %element, i64 *%ptr
+  ret void
+}
+
+; Test v4f32 extraction from the first element.
+define void @f25(<4 x float> %val, float *%ptr) {
+; CHECK-LABEL: f25:
+; CHECK: vstef %v24, 0(%r2), 0
+; CHECK: br %r14
+  %element = extractelement <4 x float> %val, i32 0
+  store float %element, float *%ptr
+  ret void
+}
+
+; Test v4f32 extraction from the last element.
+define void @f26(<4 x float> %val, float *%ptr) {
+; CHECK-LABEL: f26:
+; CHECK: vstef %v24, 0(%r2), 3
+; CHECK: br %r14
+  %element = extractelement <4 x float> %val, i32 3
+  store float %element, float *%ptr
+  ret void
+}
+
+; Test v4f32 extraction of an invalid element.  This must compile,
+; but we don't care what it does.
+define void @f27(<4 x float> %val, float *%ptr) {
+; CHECK-LABEL: f27:
+; CHECK-NOT: vstef %v24, 0(%r2), 4
+; CHECK: br %r14
+  %element = extractelement <4 x float> %val, i32 4
+  store float %element, float *%ptr
+  ret void
+}
+
+; Test v4f32 extraction with the highest in-range offset.
+define void @f28(<4 x float> %val, float *%base) {
+; CHECK-LABEL: f28:
+; CHECK: vstef %v24, 4092(%r2), 2
+; CHECK: br %r14
+  %ptr = getelementptr float, float *%base, i32 1023
+  %element = extractelement <4 x float> %val, i32 2
+  store float %element, float *%ptr
+  ret void
+}
+
+; Test v4f32 extraction with the first ouf-of-range offset.
+define void @f29(<4 x float> %val, float *%base) {
+; CHECK-LABEL: f29:
+; CHECK: aghi %r2, 4096
+; CHECK: vstef %v24, 0(%r2), 1
+; CHECK: br %r14
+  %ptr = getelementptr float, float *%base, i32 1024
+  %element = extractelement <4 x float> %val, i32 1
+  store float %element, float *%ptr
+  ret void
+}
+
+; Test v4f32 extraction from a variable element.
+define void @f30(<4 x float> %val, float *%ptr, i32 %index) {
+; CHECK-LABEL: f30:
+; CHECK-NOT: vstef
+; CHECK: br %r14
+  %element = extractelement <4 x float> %val, i32 %index
+  store float %element, float *%ptr
+  ret void
+}
+
+; Test v2f64 extraction from the first element.
+define void @f32(<2 x double> %val, double *%ptr) {
+; CHECK-LABEL: f32:
+; CHECK: vsteg %v24, 0(%r2), 0
+; CHECK: br %r14
+  %element = extractelement <2 x double> %val, i32 0
+  store double %element, double *%ptr
+  ret void
+}
+
+; Test v2f64 extraction from the last element.
+define void @f33(<2 x double> %val, double *%ptr) {
+; CHECK-LABEL: f33:
+; CHECK: vsteg %v24, 0(%r2), 1
+; CHECK: br %r14
+  %element = extractelement <2 x double> %val, i32 1
+  store double %element, double *%ptr
+  ret void
+}
+
+; Test v2f64 extraction with the highest in-range offset.
+define void @f34(<2 x double> %val, double *%base) {
+; CHECK-LABEL: f34:
+; CHECK: vsteg %v24, 4088(%r2), 1
+; CHECK: br %r14
+  %ptr = getelementptr double, double *%base, i32 511
+  %element = extractelement <2 x double> %val, i32 1
+  store double %element, double *%ptr
+  ret void
+}
+
+; Test v2f64 extraction with the first ouf-of-range offset.
+define void @f35(<2 x double> %val, double *%base) {
+; CHECK-LABEL: f35:
+; CHECK: aghi %r2, 4096
+; CHECK: vsteg %v24, 0(%r2), 0
+; CHECK: br %r14
+  %ptr = getelementptr double, double *%base, i32 512
+  %element = extractelement <2 x double> %val, i32 0
+  store double %element, double *%ptr
+  ret void
+}
+
+; Test v2f64 extraction from a variable element.
+define void @f36(<2 x double> %val, double *%ptr, i32 %index) {
+; CHECK-LABEL: f36:
+; CHECK-NOT: vsteg
+; CHECK: br %r14
+  %element = extractelement <2 x double> %val, i32 %index
+  store double %element, double *%ptr
+  ret void
+}
+
+; Test a v4i32 scatter of the first element.
+define void @f37(<4 x i32> %val, <4 x i32> %index, i64 %base) {
+; CHECK-LABEL: f37:
+; CHECK: vscef %v24, 0(%v26,%r2), 0
+; CHECK: br %r14
+  %elem = extractelement <4 x i32> %index, i32 0
+  %ext = zext i32 %elem to i64
+  %add = add i64 %base, %ext
+  %ptr = inttoptr i64 %add to i32 *
+  %element = extractelement <4 x i32> %val, i32 0
+  store i32 %element, i32 *%ptr
+  ret void
+}
+
+; Test a v4i32 scatter of the last element.
+define void @f38(<4 x i32> %val, <4 x i32> %index, i64 %base) {
+; CHECK-LABEL: f38:
+; CHECK: vscef %v24, 0(%v26,%r2), 3
+; CHECK: br %r14
+  %elem = extractelement <4 x i32> %index, i32 3
+  %ext = zext i32 %elem to i64
+  %add = add i64 %base, %ext
+  %ptr = inttoptr i64 %add to i32 *
+  %element = extractelement <4 x i32> %val, i32 3
+  store i32 %element, i32 *%ptr
+  ret void
+}
+
+; Test a v4i32 scatter with the highest in-range offset.
+define void @f39(<4 x i32> %val, <4 x i32> %index, i64 %base) {
+; CHECK-LABEL: f39:
+; CHECK: vscef %v24, 4095(%v26,%r2), 1
+; CHECK: br %r14
+  %elem = extractelement <4 x i32> %index, i32 1
+  %ext = zext i32 %elem to i64
+  %add1 = add i64 %base, %ext
+  %add2 = add i64 %add1, 4095
+  %ptr = inttoptr i64 %add2 to i32 *
+  %element = extractelement <4 x i32> %val, i32 1
+  store i32 %element, i32 *%ptr
+  ret void
+}
+
+; Test a v2i64 scatter of the first element.
+define void @f40(<2 x i64> %val, <2 x i64> %index, i64 %base) {
+; CHECK-LABEL: f40:
+; CHECK: vsceg %v24, 0(%v26,%r2), 0
+; CHECK: br %r14
+  %elem = extractelement <2 x i64> %index, i32 0
+  %add = add i64 %base, %elem
+  %ptr = inttoptr i64 %add to i64 *
+  %element = extractelement <2 x i64> %val, i32 0
+  store i64 %element, i64 *%ptr
+  ret void
+}
+
+; Test a v2i64 scatter of the last element.
+define void @f41(<2 x i64> %val, <2 x i64> %index, i64 %base) {
+; CHECK-LABEL: f41:
+; CHECK: vsceg %v24, 0(%v26,%r2), 1
+; CHECK: br %r14
+  %elem = extractelement <2 x i64> %index, i32 1
+  %add = add i64 %base, %elem
+  %ptr = inttoptr i64 %add to i64 *
+  %element = extractelement <2 x i64> %val, i32 1
+  store i64 %element, i64 *%ptr
+  ret void
+}
+
+; Test a v4f32 scatter of the first element.
+define void @f42(<4 x float> %val, <4 x i32> %index, i64 %base) {
+; CHECK-LABEL: f42:
+; CHECK: vscef %v24, 0(%v26,%r2), 0
+; CHECK: br %r14
+  %elem = extractelement <4 x i32> %index, i32 0
+  %ext = zext i32 %elem to i64
+  %add = add i64 %base, %ext
+  %ptr = inttoptr i64 %add to float *
+  %element = extractelement <4 x float> %val, i32 0
+  store float %element, float *%ptr
+  ret void
+}
+
+; Test a v4f32 scatter of the last element.
+define void @f43(<4 x float> %val, <4 x i32> %index, i64 %base) {
+; CHECK-LABEL: f43:
+; CHECK: vscef %v24, 0(%v26,%r2), 3
+; CHECK: br %r14
+  %elem = extractelement <4 x i32> %index, i32 3
+  %ext = zext i32 %elem to i64
+  %add = add i64 %base, %ext
+  %ptr = inttoptr i64 %add to float *
+  %element = extractelement <4 x float> %val, i32 3
+  store float %element, float *%ptr
+  ret void
+}
+
+; Test a v2f64 scatter of the first element.
+define void @f44(<2 x double> %val, <2 x i64> %index, i64 %base) {
+; CHECK-LABEL: f44:
+; CHECK: vsceg %v24, 0(%v26,%r2), 0
+; CHECK: br %r14
+  %elem = extractelement <2 x i64> %index, i32 0
+  %add = add i64 %base, %elem
+  %ptr = inttoptr i64 %add to double *
+  %element = extractelement <2 x double> %val, i32 0
+  store double %element, double *%ptr
+  ret void
+}
+
+; Test a v2f64 scatter of the last element.
+define void @f45(<2 x double> %val, <2 x i64> %index, i64 %base) {
+; CHECK-LABEL: f45:
+; CHECK: vsceg %v24, 0(%v26,%r2), 1
+; CHECK: br %r14
+  %elem = extractelement <2 x i64> %index, i32 1
+  %add = add i64 %base, %elem
+  %ptr = inttoptr i64 %add to double *
+  %element = extractelement <2 x double> %val, i32 1
+  store double %element, double *%ptr
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/vec-move-11.ll b/test/CodeGen/SystemZ/vec-move-11.ll
new file mode 100644
index 000000000000..fd9c3d3559f0
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-11.ll
@@ -0,0 +1,111 @@
+; Test insertions of register values into a nonzero index of an undef.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test v16i8 insertion into an undef, with an arbitrary index.
+define <16 x i8> @f1(i8 %val) {
+; CHECK-LABEL: f1:
+; CHECK: vlvgb %v24, %r2, 12
+; CHECK-NEXT: br %r14
+  %ret = insertelement <16 x i8> undef, i8 %val, i32 12
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 insertion into an undef, with the first good index for VLVGP.
+define <16 x i8> @f2(i8 %val) {
+; CHECK-LABEL: f2:
+; CHECK: vlvgp %v24, %r2, %r2
+; CHECK-NEXT: br %r14
+  %ret = insertelement <16 x i8> undef, i8 %val, i32 7
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 insertion into an undef, with the second good index for VLVGP.
+define <16 x i8> @f3(i8 %val) {
+; CHECK-LABEL: f3:
+; CHECK: vlvgp %v24, %r2, %r2
+; CHECK-NEXT: br %r14
+  %ret = insertelement <16 x i8> undef, i8 %val, i32 15
+  ret <16 x i8> %ret
+}
+
+; Test v8i16 insertion into an undef, with an arbitrary index.
+define <8 x i16> @f4(i16 %val) {
+; CHECK-LABEL: f4:
+; CHECK: vlvgh %v24, %r2, 5
+; CHECK-NEXT: br %r14
+  %ret = insertelement <8 x i16> undef, i16 %val, i32 5
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 insertion into an undef, with the first good index for VLVGP.
+define <8 x i16> @f5(i16 %val) {
+; CHECK-LABEL: f5:
+; CHECK: vlvgp %v24, %r2, %r2
+; CHECK-NEXT: br %r14
+  %ret = insertelement <8 x i16> undef, i16 %val, i32 3
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 insertion into an undef, with the second good index for VLVGP.
+define <8 x i16> @f6(i16 %val) {
+; CHECK-LABEL: f6:
+; CHECK: vlvgp %v24, %r2, %r2
+; CHECK-NEXT: br %r14
+  %ret = insertelement <8 x i16> undef, i16 %val, i32 7
+  ret <8 x i16> %ret
+}
+
+; Test v4i32 insertion into an undef, with an arbitrary index.
+define <4 x i32> @f7(i32 %val) {
+; CHECK-LABEL: f7:
+; CHECK: vlvgf %v24, %r2, 2
+; CHECK-NEXT: br %r14
+  %ret = insertelement <4 x i32> undef, i32 %val, i32 2
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion into an undef, with the first good index for VLVGP.
+define <4 x i32> @f8(i32 %val) {
+; CHECK-LABEL: f8:
+; CHECK: vlvgp %v24, %r2, %r2
+; CHECK-NEXT: br %r14
+  %ret = insertelement <4 x i32> undef, i32 %val, i32 1
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion into an undef, with the second good index for VLVGP.
+define <4 x i32> @f9(i32 %val) {
+; CHECK-LABEL: f9:
+; CHECK: vlvgp %v24, %r2, %r2
+; CHECK-NEXT: br %r14
+  %ret = insertelement <4 x i32> undef, i32 %val, i32 3
+  ret <4 x i32> %ret
+}
+
+; Test v2i64 insertion into an undef.
+define <2 x i64> @f10(i64 %val) {
+; CHECK-LABEL: f10:
+; CHECK: vlvgp %v24, %r2, %r2
+; CHECK-NEXT: br %r14
+  %ret = insertelement <2 x i64> undef, i64 %val, i32 1
+  ret <2 x i64> %ret
+}
+
+; Test v4f32 insertion into an undef.
+define <4 x float> @f11(float %val) {
+; CHECK-LABEL: f11:
+; CHECK: vrepf %v24, %v0, 0
+; CHECK: br %r14
+  %ret = insertelement <4 x float> undef, float %val, i32 2
+  ret <4 x float> %ret
+}
+
+; Test v2f64 insertion into an undef.
+define <2 x double> @f12(double %val) {
+; CHECK-LABEL: f12:
+; CHECK: vrepg %v24, %v0, 0
+; CHECK: br %r14
+  %ret = insertelement <2 x double> undef, double %val, i32 1
+  ret <2 x double> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-move-12.ll b/test/CodeGen/SystemZ/vec-move-12.ll
new file mode 100644
index 000000000000..bc8ff97f8057
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-12.ll
@@ -0,0 +1,123 @@
+; Test insertions of memory values into a nonzero index of an undef.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test v16i8 insertion into an undef, with an arbitrary index.
+define <16 x i8> @f1(i8 *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: vlrepb %v24, 0(%r2)
+; CHECK-NEXT: br %r14
+  %val = load i8, i8 *%ptr
+  %ret = insertelement <16 x i8> undef, i8 %val, i32 12
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 insertion into an undef, with the first good index for VLVGP.
+define <16 x i8> @f2(i8 *%ptr) {
+; CHECK-LABEL: f2:
+; CHECK: {{vlrepb|vllezb}} %v24, 0(%r2)
+; CHECK-NEXT: br %r14
+  %val = load i8, i8 *%ptr
+  %ret = insertelement <16 x i8> undef, i8 %val, i32 7
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 insertion into an undef, with the second good index for VLVGP.
+define <16 x i8> @f3(i8 *%ptr) {
+; CHECK-LABEL: f3:
+; CHECK: vlrepb %v24, 0(%r2)
+; CHECK-NEXT: br %r14
+  %val = load i8, i8 *%ptr
+  %ret = insertelement <16 x i8> undef, i8 %val, i32 15
+  ret <16 x i8> %ret
+}
+
+; Test v8i16 insertion into an undef, with an arbitrary index.
+define <8 x i16> @f4(i16 *%ptr) {
+; CHECK-LABEL: f4:
+; CHECK: vlreph %v24, 0(%r2)
+; CHECK-NEXT: br %r14
+  %val = load i16, i16 *%ptr
+  %ret = insertelement <8 x i16> undef, i16 %val, i32 5
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 insertion into an undef, with the first good index for VLVGP.
+define <8 x i16> @f5(i16 *%ptr) {
+; CHECK-LABEL: f5:
+; CHECK: {{vlreph|vllezh}} %v24, 0(%r2)
+; CHECK-NEXT: br %r14
+  %val = load i16, i16 *%ptr
+  %ret = insertelement <8 x i16> undef, i16 %val, i32 3
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 insertion into an undef, with the second good index for VLVGP.
+define <8 x i16> @f6(i16 *%ptr) {
+; CHECK-LABEL: f6:
+; CHECK: vlreph %v24, 0(%r2)
+; CHECK-NEXT: br %r14
+  %val = load i16, i16 *%ptr
+  %ret = insertelement <8 x i16> undef, i16 %val, i32 7
+  ret <8 x i16> %ret
+}
+
+; Test v4i32 insertion into an undef, with an arbitrary index.
+define <4 x i32> @f7(i32 *%ptr) {
+; CHECK-LABEL: f7:
+; CHECK: vlrepf %v24, 0(%r2)
+; CHECK-NEXT: br %r14
+  %val = load i32, i32 *%ptr
+  %ret = insertelement <4 x i32> undef, i32 %val, i32 2
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion into an undef, with the first good index for VLVGP.
+define <4 x i32> @f8(i32 *%ptr) {
+; CHECK-LABEL: f8:
+; CHECK: {{vlrepf|vllezf}} %v24, 0(%r2)
+; CHECK-NEXT: br %r14
+  %val = load i32, i32 *%ptr
+  %ret = insertelement <4 x i32> undef, i32 %val, i32 1
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 insertion into an undef, with the second good index for VLVGP.
+define <4 x i32> @f9(i32 *%ptr) {
+; CHECK-LABEL: f9:
+; CHECK: vlrepf %v24, 0(%r2)
+; CHECK-NEXT: br %r14
+  %val = load i32, i32 *%ptr
+  %ret = insertelement <4 x i32> undef, i32 %val, i32 3
+  ret <4 x i32> %ret
+}
+
+; Test v2i64 insertion into an undef.
+define <2 x i64> @f10(i64 *%ptr) {
+; CHECK-LABEL: f10:
+; CHECK: vlrepg %v24, 0(%r2)
+; CHECK-NEXT: br %r14
+  %val = load i64, i64 *%ptr
+  %ret = insertelement <2 x i64> undef, i64 %val, i32 1
+  ret <2 x i64> %ret
+}
+
+; Test v4f32 insertion into an undef.
+define <4 x float> @f11(float *%ptr) {
+; CHECK-LABEL: f11:
+; CHECK: vlrepf %v24, 0(%r2)
+; CHECK: br %r14
+  %val = load float, float *%ptr
+  %ret = insertelement <4 x float> undef, float %val, i32 2
+  ret <4 x float> %ret
+}
+
+; Test v2f64 insertion into an undef.
+define <2 x double> @f12(double *%ptr) {
+; CHECK-LABEL: f12:
+; CHECK: vlrepg %v24, 0(%r2)
+; CHECK: br %r14
+  %val = load double, double *%ptr
+  %ret = insertelement <2 x double> undef, double %val, i32 1
+  ret <2 x double> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-move-13.ll b/test/CodeGen/SystemZ/vec-move-13.ll
new file mode 100644
index 000000000000..165c3498702f
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-13.ll
@@ -0,0 +1,69 @@
+; Test insertions of register values into 0.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test v16i8 insertion into 0.
+define <16 x i8> @f1(i8 %val1, i8 %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vgbm %v24, 0
+; CHECK-DAG: vlvgb %v24, %r2, 2
+; CHECK-DAG: vlvgb %v24, %r3, 12
+; CHECK: br %r14
+  %vec1 = insertelement <16 x i8> zeroinitializer, i8 %val1, i32 2
+  %vec2 = insertelement <16 x i8> %vec1, i8 %val2, i32 12
+  ret <16 x i8> %vec2
+}
+
+; Test v8i16 insertion into 0.
+define <8 x i16> @f2(i16 %val1, i16 %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vgbm %v24, 0
+; CHECK-DAG: vlvgh %v24, %r2, 3
+; CHECK-DAG: vlvgh %v24, %r3, 5
+; CHECK: br %r14
+  %vec1 = insertelement <8 x i16> zeroinitializer, i16 %val1, i32 3
+  %vec2 = insertelement <8 x i16> %vec1, i16 %val2, i32 5
+  ret <8 x i16> %vec2
+}
+
+; Test v4i32 insertion into 0.
+define <4 x i32> @f3(i32 %val) {
+; CHECK-LABEL: f3:
+; CHECK: vgbm %v24, 0
+; CHECK: vlvgf %v24, %r2, 3
+; CHECK: br %r14
+  %ret = insertelement <4 x i32> zeroinitializer, i32 %val, i32 3
+  ret <4 x i32> %ret
+}
+
+; Test v2i64 insertion into 0.
+define <2 x i64> @f4(i64 %val) {
+; CHECK-LABEL: f4:
+; CHECK: lghi [[REG:%r[0-5]]], 0
+; CHECK: vlvgp %v24, [[REG]], %r2
+; CHECK: br %r14
+  %ret = insertelement <2 x i64> zeroinitializer, i64 %val, i32 1
+  ret <2 x i64> %ret
+}
+
+; Test v4f32 insertion into 0.
+define <4 x float> @f5(float %val) {
+; CHECK-LABEL: f5:
+; CHECK-DAG: vuplhf [[REG:%v[0-9]+]], %v0
+; CHECK-DAG: vgbm [[ZERO:%v[0-9]+]], 0
+; CHECK: vmrhg %v24, [[ZERO]], [[REG]]
+; CHECK: br %r14
+  %ret = insertelement <4 x float> zeroinitializer, float %val, i32 3
+  ret <4 x float> %ret
+}
+
+; Test v2f64 insertion into 0.
+define <2 x double> @f6(double %val) {
+; CHECK-LABEL: f6:
+; CHECK: vgbm [[REG:%v[0-9]+]], 0
+; CHECK: vmrhg %v24, [[REG]], %v0
+; CHECK: br %r14
+  %ret = insertelement <2 x double> zeroinitializer, double %val, i32 1
+  ret <2 x double> %ret
+}
+
diff --git a/test/CodeGen/SystemZ/vec-move-14.ll b/test/CodeGen/SystemZ/vec-move-14.ll
new file mode 100644
index 000000000000..e41eb9da0346
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-14.ll
@@ -0,0 +1,96 @@
+; Test insertions of memory values into 0.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test VLLEZB.
+define <16 x i8> @f1(i8 *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: vllezb %v24, 0(%r2)
+; CHECK: br %r14
+  %val = load i8, i8 *%ptr
+  %ret = insertelement <16 x i8> zeroinitializer, i8 %val, i32 7
+  ret <16 x i8> %ret
+}
+
+; Test VLLEZB with the highest in-range offset.
+define <16 x i8> @f2(i8 *%base) {
+; CHECK-LABEL: f2:
+; CHECK: vllezb %v24, 4095(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i64 4095
+  %val = load i8, i8 *%ptr
+  %ret = insertelement <16 x i8> zeroinitializer, i8 %val, i32 7
+  ret <16 x i8> %ret
+}
+
+; Test VLLEZB with the next highest offset.
+define <16 x i8> @f3(i8 *%base) {
+; CHECK-LABEL: f3:
+; CHECK-NOT: vllezb %v24, 4096(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i64 4096
+  %val = load i8, i8 *%ptr
+  %ret = insertelement <16 x i8> zeroinitializer, i8 %val, i32 7
+  ret <16 x i8> %ret
+}
+
+; Test that VLLEZB allows an index.
+define <16 x i8> @f4(i8 *%base, i64 %index) {
+; CHECK-LABEL: f4:
+; CHECK: vllezb %v24, 0({{%r2,%r3|%r3,%r2}})
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i64 %index
+  %val = load i8, i8 *%ptr
+  %ret = insertelement <16 x i8> zeroinitializer, i8 %val, i32 7
+  ret <16 x i8> %ret
+}
+
+; Test VLLEZH.
+define <8 x i16> @f5(i16 *%ptr) {
+; CHECK-LABEL: f5:
+; CHECK: vllezh %v24, 0(%r2)
+; CHECK: br %r14
+  %val = load i16, i16 *%ptr
+  %ret = insertelement <8 x i16> zeroinitializer, i16 %val, i32 3
+  ret <8 x i16> %ret
+}
+
+; Test VLLEZF.
+define <4 x i32> @f6(i32 *%ptr) {
+; CHECK-LABEL: f6:
+; CHECK: vllezf %v24, 0(%r2)
+; CHECK: br %r14
+  %val = load i32, i32 *%ptr
+  %ret = insertelement <4 x i32> zeroinitializer, i32 %val, i32 1
+  ret <4 x i32> %ret
+}
+
+; Test VLLEZG.
+define <2 x i64> @f7(i64 *%ptr) {
+; CHECK-LABEL: f7:
+; CHECK: vllezg %v24, 0(%r2)
+; CHECK: br %r14
+  %val = load i64, i64 *%ptr
+  %ret = insertelement <2 x i64> zeroinitializer, i64 %val, i32 0
+  ret <2 x i64> %ret
+}
+
+; Test VLLEZF with a float.
+define <4 x float> @f8(float *%ptr) {
+; CHECK-LABEL: f8:
+; CHECK: vllezf %v24, 0(%r2)
+; CHECK: br %r14
+  %val = load float, float *%ptr
+  %ret = insertelement <4 x float> zeroinitializer, float %val, i32 1
+  ret <4 x float> %ret
+}
+
+; Test VLLEZG with a double.
+define <2 x double> @f9(double *%ptr) {
+; CHECK-LABEL: f9:
+; CHECK: vllezg %v24, 0(%r2)
+; CHECK: br %r14
+  %val = load double, double *%ptr
+  %ret = insertelement <2 x double> zeroinitializer, double %val, i32 0
+  ret <2 x double> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-move-15.ll b/test/CodeGen/SystemZ/vec-move-15.ll
new file mode 100644
index 000000000000..503627c163c6
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-15.ll
@@ -0,0 +1,105 @@
+; Test vector sign-extending loads.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i1->v16i8 extension.
+define <16 x i8> @f1(<16 x i1> *%ptr) {
+; No expected output, but must compile.
+  %val = load <16 x i1>, <16 x i1> *%ptr
+  %ret = sext <16 x i1> %val to <16 x i8>
+  ret <16 x i8> %ret
+}
+
+; Test a v8i1->v8i16 extension.
+define <8 x i16> @f2(<8 x i1> *%ptr) {
+; No expected output, but must compile.
+  %val = load <8 x i1>, <8 x i1> *%ptr
+  %ret = sext <8 x i1> %val to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test a v8i8->v8i16 extension.
+define <8 x i16> @f3(<8 x i8> *%ptr) {
+; CHECK-LABEL: f3:
+; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
+; CHECK: vuphb %v24, [[REG1]]
+; CHECK: br %r14
+  %val = load <8 x i8>, <8 x i8> *%ptr
+  %ret = sext <8 x i8> %val to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test a v4i1->v4i32 extension.
+define <4 x i32> @f4(<4 x i1> *%ptr) {
+; No expected output, but must compile.
+  %val = load <4 x i1>, <4 x i1> *%ptr
+  %ret = sext <4 x i1> %val to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test a v4i8->v4i32 extension.
+define <4 x i32> @f5(<4 x i8> *%ptr) {
+; CHECK-LABEL: f5:
+; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)
+; CHECK: vuphb [[REG2:%v[0-9]+]], [[REG1]]
+; CHECK: vuphh %v24, [[REG2]]
+; CHECK: br %r14
+  %val = load <4 x i8>, <4 x i8> *%ptr
+  %ret = sext <4 x i8> %val to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test a v4i16->v4i32 extension.
+define <4 x i32> @f6(<4 x i16> *%ptr) {
+; CHECK-LABEL: f6:
+; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
+; CHECK: vuphh %v24, [[REG1]]
+; CHECK: br %r14
+  %val = load <4 x i16>, <4 x i16> *%ptr
+  %ret = sext <4 x i16> %val to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test a v2i1->v2i64 extension.
+define <2 x i64> @f7(<2 x i1> *%ptr) {
+; No expected output, but must compile.
+  %val = load <2 x i1>, <2 x i1> *%ptr
+  %ret = sext <2 x i1> %val to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test a v2i8->v2i64 extension.
+define <2 x i64> @f8(<2 x i8> *%ptr) {
+; CHECK-LABEL: f8:
+; CHECK: vlreph [[REG1:%v[0-9]+]], 0(%r2)
+; CHECK: vuphb [[REG2:%v[0-9]+]], [[REG1]]
+; CHECK: vuphh [[REG3:%v[0-9]+]], [[REG2]]
+; CHECK: vuphf %v24, [[REG3]]
+; CHECK: br %r14
+  %val = load <2 x i8>, <2 x i8> *%ptr
+  %ret = sext <2 x i8> %val to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test a v2i16->v2i64 extension.
+define <2 x i64> @f9(<2 x i16> *%ptr) {
+; CHECK-LABEL: f9:
+; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)
+; CHECK: vuphh [[REG2:%v[0-9]+]], [[REG1]]
+; CHECK: vuphf %v24, [[REG2]]
+; CHECK: br %r14
+  %val = load <2 x i16>, <2 x i16> *%ptr
+  %ret = sext <2 x i16> %val to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test a v2i32->v2i64 extension.
+define <2 x i64> @f10(<2 x i32> *%ptr) {
+; CHECK-LABEL: f10:
+; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
+; CHECK: vuphf %v24, [[REG1]]
+; CHECK: br %r14
+  %val = load <2 x i32>, <2 x i32> *%ptr
+  %ret = sext <2 x i32> %val to <2 x i64>
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-move-16.ll b/test/CodeGen/SystemZ/vec-move-16.ll
new file mode 100644
index 000000000000..cd2577396800
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-16.ll
@@ -0,0 +1,105 @@
+; Test vector zero-extending loads.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i1->v16i8 extension.
+define <16 x i8> @f1(<16 x i1> *%ptr) {
+; No expected output, but must compile.
+  %val = load <16 x i1>, <16 x i1> *%ptr
+  %ret = zext <16 x i1> %val to <16 x i8>
+  ret <16 x i8> %ret
+}
+
+; Test a v8i1->v8i16 extension.
+define <8 x i16> @f2(<8 x i1> *%ptr) {
+; No expected output, but must compile.
+  %val = load <8 x i1>, <8 x i1> *%ptr
+  %ret = zext <8 x i1> %val to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test a v8i8->v8i16 extension.
+define <8 x i16> @f3(<8 x i8> *%ptr) {
+; CHECK-LABEL: f3:
+; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
+; CHECK: vuplhb %v24, [[REG1]]
+; CHECK: br %r14
+  %val = load <8 x i8>, <8 x i8> *%ptr
+  %ret = zext <8 x i8> %val to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test a v4i1->v4i32 extension.
+define <4 x i32> @f4(<4 x i1> *%ptr) {
+; No expected output, but must compile.
+  %val = load <4 x i1>, <4 x i1> *%ptr
+  %ret = zext <4 x i1> %val to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test a v4i8->v4i32 extension.
+define <4 x i32> @f5(<4 x i8> *%ptr) {
+; CHECK-LABEL: f5:
+; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)
+; CHECK: vuplhb [[REG2:%v[0-9]+]], [[REG1]]
+; CHECK: vuplhh %v24, [[REG2]]
+; CHECK: br %r14
+  %val = load <4 x i8>, <4 x i8> *%ptr
+  %ret = zext <4 x i8> %val to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test a v4i16->v4i32 extension.
+define <4 x i32> @f6(<4 x i16> *%ptr) {
+; CHECK-LABEL: f6:
+; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
+; CHECK: vuplhh %v24, [[REG1]]
+; CHECK: br %r14
+  %val = load <4 x i16>, <4 x i16> *%ptr
+  %ret = zext <4 x i16> %val to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test a v2i1->v2i64 extension.
+define <2 x i64> @f7(<2 x i1> *%ptr) {
+; No expected output, but must compile.
+  %val = load <2 x i1>, <2 x i1> *%ptr
+  %ret = zext <2 x i1> %val to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test a v2i8->v2i64 extension.
+define <2 x i64> @f8(<2 x i8> *%ptr) {
+; CHECK-LABEL: f8:
+; CHECK: vlreph [[REG1:%v[0-9]+]], 0(%r2)
+; CHECK: vuplhb [[REG2:%v[0-9]+]], [[REG1]]
+; CHECK: vuplhh [[REG3:%v[0-9]+]], [[REG2]]
+; CHECK: vuplhf %v24, [[REG3]]
+; CHECK: br %r14
+  %val = load <2 x i8>, <2 x i8> *%ptr
+  %ret = zext <2 x i8> %val to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test a v2i16->v2i64 extension.
+define <2 x i64> @f9(<2 x i16> *%ptr) {
+; CHECK-LABEL: f9:
+; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)
+; CHECK: vuplhh [[REG2:%v[0-9]+]], [[REG1]]
+; CHECK: vuplhf %v24, [[REG2]]
+; CHECK: br %r14
+  %val = load <2 x i16>, <2 x i16> *%ptr
+  %ret = zext <2 x i16> %val to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test a v2i32->v2i64 extension.
+define <2 x i64> @f10(<2 x i32> *%ptr) {
+; CHECK-LABEL: f10:
+; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
+; CHECK: vuplhf %v24, [[REG1]]
+; CHECK: br %r14
+  %val = load <2 x i32>, <2 x i32> *%ptr
+  %ret = zext <2 x i32> %val to <2 x i64>
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-move-17.ll b/test/CodeGen/SystemZ/vec-move-17.ll
new file mode 100644
index 000000000000..e7fc06c9260c
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-move-17.ll
@@ -0,0 +1,104 @@
+; Test vector truncating stores.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8->v16i1 truncation.
+define void @f1(<16 x i8> %val, <16 x i1> *%ptr) {
+; No expected output, but must compile.
+  %trunc = trunc <16 x i8> %val to <16 x i1>
+  store <16 x i1> %trunc, <16 x i1> *%ptr
+  ret void
+}
+
+; Test a v8i16->v8i1 truncation.
+define void @f2(<8 x i16> %val, <8 x i1> *%ptr) {
+; No expected output, but must compile.
+  %trunc = trunc <8 x i16> %val to <8 x i1>
+  store <8 x i1> %trunc, <8 x i1> *%ptr
+  ret void
+}
+
+; Test a v8i16->v8i8 truncation.
+define void @f3(<8 x i16> %val, <8 x i8> *%ptr) {
+; CHECK-LABEL: f3:
+; CHECK: vpkh [[REG1:%v[0-9]+]], %v24, %v24
+; CHECK: vsteg [[REG1]], 0(%r2)
+; CHECK: br %r14
+  %trunc = trunc <8 x i16> %val to <8 x i8>
+  store <8 x i8> %trunc, <8 x i8> *%ptr
+  ret void
+}
+
+; Test a v4i32->v4i1 truncation.
+define void @f4(<4 x i32> %val, <4 x i1> *%ptr) {
+; No expected output, but must compile.
+  %trunc = trunc <4 x i32> %val to <4 x i1>
+  store <4 x i1> %trunc, <4 x i1> *%ptr
+  ret void
+}
+
+; Test a v4i32->v4i8 truncation.  At the moment we use a VPERM rather than
+; a chain of packs.
+define void @f5(<4 x i32> %val, <4 x i8> *%ptr) {
+; CHECK-LABEL: f5:
+; CHECK: vperm [[REG:%v[0-9]+]],
+; CHECK: vstef [[REG]], 0(%r2)
+; CHECK: br %r14
+  %trunc = trunc <4 x i32> %val to <4 x i8>
+  store <4 x i8> %trunc, <4 x i8> *%ptr
+  ret void
+}
+
+; Test a v4i32->v4i16 truncation.
+define void @f6(<4 x i32> %val, <4 x i16> *%ptr) {
+; CHECK-LABEL: f6:
+; CHECK: vpkf [[REG1:%v[0-9]+]], %v24, %v24
+; CHECK: vsteg [[REG1]], 0(%r2)
+; CHECK: br %r14
+  %trunc = trunc <4 x i32> %val to <4 x i16>
+  store <4 x i16> %trunc, <4 x i16> *%ptr
+  ret void
+}
+
+; Test a v2i64->v2i1 truncation.
+define void @f7(<2 x i64> %val, <2 x i1> *%ptr) {
+; No expected output, but must compile.
+  %trunc = trunc <2 x i64> %val to <2 x i1>
+  store <2 x i1> %trunc, <2 x i1> *%ptr
+  ret void
+}
+
+; Test a v2i64->v2i8 truncation.  At the moment we use a VPERM rather than
+; a chain of packs.
+define void @f8(<2 x i64> %val, <2 x i8> *%ptr) {
+; CHECK-LABEL: f8:
+; CHECK: vperm [[REG:%v[0-9]+]],
+; CHECK: vsteh [[REG]], 0(%r2)
+; CHECK: br %r14
+  %trunc = trunc <2 x i64> %val to <2 x i8>
+  store <2 x i8> %trunc, <2 x i8> *%ptr
+  ret void
+}
+
+; Test a v2i64->v2i16 truncation.  At the moment we use a VPERM rather than
+; a chain of packs.
+define void @f9(<2 x i64> %val, <2 x i16> *%ptr) {
+; CHECK-LABEL: f9:
+; CHECK: vperm [[REG:%v[0-9]+]],
+; CHECK: vstef [[REG]], 0(%r2)
+; CHECK: br %r14
+  %trunc = trunc <2 x i64> %val to <2 x i16>
+  store <2 x i16> %trunc, <2 x i16> *%ptr
+  ret void
+}
+
+; Test a v2i64->v2i32 truncation.
+define void @f10(<2 x i64> %val, <2 x i32> *%ptr) {
+; CHECK-LABEL: f10:
+; CHECK: vpkg [[REG1:%v[0-9]+]], %v24, %v24
+; CHECK: vsteg [[REG1]], 0(%r2)
+; CHECK: br %r14
+  %trunc = trunc <2 x i64> %val to <2 x i32>
+  store <2 x i32> %trunc, <2 x i32> *%ptr
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/vec-mul-01.ll b/test/CodeGen/SystemZ/vec-mul-01.ll
new file mode 100644
index 000000000000..5ecc30d4427a
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-mul-01.ll
@@ -0,0 +1,60 @@
+; Test vector multiplication.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 multiplication.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vmlb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = mul <16 x i8> %val1, %val2
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 multiplication.
+define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vmlhw %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = mul <8 x i16> %val1, %val2
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 multiplication.
+define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vmlf %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = mul <4 x i32> %val1, %val2
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 multiplication.  There's no vector equivalent.
+define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f4:
+; CHECK-NOT: vmlg
+; CHECK: br %r14
+  %ret = mul <2 x i64> %val1, %val2
+  ret <2 x i64> %ret
+}
+
+; Test a v2f64 multiplication.
+define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1,
+                        <2 x double> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vfmdb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = fmul <2 x double> %val1, %val2
+  ret <2 x double> %ret
+}
+
+; Test an f64 multiplication that uses vector registers.
+define double @f6(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: wfmdb %f0, %v24, %v26
+; CHECK: br %r14
+  %scalar1 = extractelement <2 x double> %val1, i32 0
+  %scalar2 = extractelement <2 x double> %val2, i32 0
+  %ret = fmul double %scalar1, %scalar2
+  ret double %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-mul-02.ll b/test/CodeGen/SystemZ/vec-mul-02.ll
new file mode 100644
index 000000000000..11a651e49975
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-mul-02.ll
@@ -0,0 +1,63 @@
+; Test vector multiply-and-add.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)
+
+; Test a v16i8 multiply-and-add.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2,
+                     <16 x i8> %val3) {
+; CHECK-LABEL: f1:
+; CHECK: vmalb %v24, %v26, %v28, %v30
+; CHECK: br %r14
+  %mul = mul <16 x i8> %val1, %val2
+  %ret = add <16 x i8> %mul, %val3
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 multiply-and-add.
+define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2,
+                     <8 x i16> %val3) {
+; CHECK-LABEL: f2:
+; CHECK: vmalhw %v24, %v26, %v28, %v30
+; CHECK: br %r14
+  %mul = mul <8 x i16> %val1, %val2
+  %ret = add <8 x i16> %mul, %val3
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 multiply-and-add.
+define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2,
+                     <4 x i32> %val3) {
+; CHECK-LABEL: f3:
+; CHECK: vmalf %v24, %v26, %v28, %v30
+; CHECK: br %r14
+  %mul = mul <4 x i32> %val1, %val2
+  %ret = add <4 x i32> %mul, %val3
+  ret <4 x i32> %ret
+}
+
+; Test a v2f64 multiply-and-add.
+define <2 x double> @f4(<2 x double> %dummy, <2 x double> %val1,
+                        <2 x double> %val2, <2 x double> %val3) {
+; CHECK-LABEL: f4:
+; CHECK: vfmadb %v24, %v26, %v28, %v30
+; CHECK: br %r14
+  %ret = call <2 x double> @llvm.fma.v2f64 (<2 x double> %val1,
+                                            <2 x double> %val2,
+                                            <2 x double> %val3)
+  ret <2 x double> %ret
+}
+
+; Test a v2f64 multiply-and-subtract.
+define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1,
+                        <2 x double> %val2, <2 x double> %val3) {
+; CHECK-LABEL: f5:
+; CHECK: vfmsdb %v24, %v26, %v28, %v30
+; CHECK: br %r14
+  %negval3 = fsub <2 x double> <double -0.0, double -0.0>, %val3
+  %ret = call <2 x double> @llvm.fma.v2f64 (<2 x double> %val1,
+                                            <2 x double> %val2,
+                                            <2 x double> %negval3)
+  ret <2 x double> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-neg-01.ll b/test/CodeGen/SystemZ/vec-neg-01.ll
new file mode 100644
index 000000000000..b1389ce4d6d0
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-neg-01.ll
@@ -0,0 +1,58 @@
+; Test vector negation.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 negation.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val) {
+; CHECK-LABEL: f1:
+; CHECK: vlcb %v24, %v26
+; CHECK: br %r14
+  %ret = sub <16 x i8> zeroinitializer, %val
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 negation.
+define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val) {
+; CHECK-LABEL: f2:
+; CHECK: vlch %v24, %v26
+; CHECK: br %r14
+  %ret = sub <8 x i16> zeroinitializer, %val
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 negation.
+define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val) {
+; CHECK-LABEL: f3:
+; CHECK: vlcf %v24, %v26
+; CHECK: br %r14
+  %ret = sub <4 x i32> zeroinitializer, %val
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 negation.
+define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val) {
+; CHECK-LABEL: f4:
+; CHECK: vlcg %v24, %v26
+; CHECK: br %r14
+  %ret = sub <2 x i64> zeroinitializer, %val
+  ret <2 x i64> %ret
+}
+
+; Test a v2f64 negation.
+define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vflcdb %v24, %v26
+; CHECK: br %r14
+  %ret = fsub <2 x double> <double -0.0, double -0.0>, %val
+  ret <2 x double> %ret
+}
+
+; Test an f64 negation that uses vector registers.
+define double @f6(<2 x double> %val) {
+; CHECK-LABEL: f6:
+; CHECK: wflcdb %f0, %v24
+; CHECK: br %r14
+  %scalar = extractelement <2 x double> %val, i32 0
+  %ret = fsub double -0.0, %scalar
+  ret double %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-or-01.ll b/test/CodeGen/SystemZ/vec-or-01.ll
new file mode 100644
index 000000000000..789150ad2d1b
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-or-01.ll
@@ -0,0 +1,39 @@
+; Test vector OR.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 OR.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vo %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = or <16 x i8> %val1, %val2
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 OR.
+define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vo %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = or <8 x i16> %val1, %val2
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 OR.
+define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vo %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = or <4 x i32> %val1, %val2
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 OR.
+define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vo %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = or <2 x i64> %val1, %val2
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-or-02.ll b/test/CodeGen/SystemZ/vec-or-02.ll
new file mode 100644
index 000000000000..eeb86e36ff00
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-or-02.ll
@@ -0,0 +1,107 @@
+; Test vector (or (and X, Z), (and Y, (not Z))) patterns.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test v16i8.
+define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {
+; CHECK-LABEL: f1:
+; CHECK: vsel %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %not = xor <16 x i8> %val3, <i8 -1, i8 -1, i8 -1, i8 -1,
+                               i8 -1, i8 -1, i8 -1, i8 -1,
+                               i8 -1, i8 -1, i8 -1, i8 -1,
+                               i8 -1, i8 -1, i8 -1, i8 -1>
+  %and1 = and <16 x i8> %val1, %val3
+  %and2 = and <16 x i8> %val2, %not
+  %ret = or <16 x i8> %and1, %and2
+  ret <16 x i8> %ret
+}
+
+; ...and again with the XOR applied to the other operand of the AND.
+define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {
+; CHECK-LABEL: f2:
+; CHECK: vsel %v24, %v26, %v24, %v28
+; CHECK: br %r14
+  %not = xor <16 x i8> %val3, <i8 -1, i8 -1, i8 -1, i8 -1,
+                               i8 -1, i8 -1, i8 -1, i8 -1,
+                               i8 -1, i8 -1, i8 -1, i8 -1,
+                               i8 -1, i8 -1, i8 -1, i8 -1>
+  %and1 = and <16 x i8> %val1, %not
+  %and2 = and <16 x i8> %val2, %val3
+  %ret = or <16 x i8> %and1, %and2
+  ret <16 x i8> %ret
+}
+
+; Test v8i16.
+define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {
+; CHECK-LABEL: f3:
+; CHECK: vsel %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %not = xor <8 x i16> %val3, <i16 -1, i16 -1, i16 -1, i16 -1,
+                               i16 -1, i16 -1, i16 -1, i16 -1>
+  %and1 = and <8 x i16> %val1, %val3
+  %and2 = and <8 x i16> %val2, %not
+  %ret = or <8 x i16> %and1, %and2
+  ret <8 x i16> %ret
+}
+
+; ...and again with the XOR applied to the other operand of the AND.
+define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {
+; CHECK-LABEL: f4:
+; CHECK: vsel %v24, %v26, %v24, %v28
+; CHECK: br %r14
+  %not = xor <8 x i16> %val3, <i16 -1, i16 -1, i16 -1, i16 -1,
+                               i16 -1, i16 -1, i16 -1, i16 -1>
+  %and1 = and <8 x i16> %val1, %not
+  %and2 = and <8 x i16> %val2, %val3
+  %ret = or <8 x i16> %and1, %and2
+  ret <8 x i16> %ret
+}
+
+; Test v4i32.
+define <4 x i32> @f5(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) {
+; CHECK-LABEL: f5:
+; CHECK: vsel %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %not = xor <4 x i32> %val3, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %and1 = and <4 x i32> %val1, %val3
+  %and2 = and <4 x i32> %val2, %not
+  %ret = or <4 x i32> %and1, %and2
+  ret <4 x i32> %ret
+}
+
+; ...and again with the XOR applied to the other operand of the AND.
+define <4 x i32> @f6(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) {
+; CHECK-LABEL: f6:
+; CHECK: vsel %v24, %v26, %v24, %v28
+; CHECK: br %r14
+  %not = xor <4 x i32> %val3, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %and1 = and <4 x i32> %val1, %not
+  %and2 = and <4 x i32> %val2, %val3
+  %ret = or <4 x i32> %and1, %and2
+  ret <4 x i32> %ret
+}
+
+; Test v2i64.
+define <2 x i64> @f7(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3) {
+; CHECK-LABEL: f7:
+; CHECK: vsel %v24, %v24, %v26, %v28
+; CHECK: br %r14
+  %not = xor <2 x i64> %val3, <i64 -1, i64 -1>
+  %and1 = and <2 x i64> %val1, %val3
+  %and2 = and <2 x i64> %val2, %not
+  %ret = or <2 x i64> %and1, %and2
+  ret <2 x i64> %ret
+}
+
+; ...and again with the XOR applied to the other operand of the AND.
+define <2 x i64> @f8(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3) {
+; CHECK-LABEL: f8:
+; CHECK: vsel %v24, %v26, %v24, %v28
+; CHECK: br %r14
+  %not = xor <2 x i64> %val3, <i64 -1, i64 -1>
+  %and1 = and <2 x i64> %val1, %not
+  %and2 = and <2 x i64> %val2, %val3
+  %ret = or <2 x i64> %and1, %and2
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-perm-01.ll b/test/CodeGen/SystemZ/vec-perm-01.ll
new file mode 100644
index 000000000000..4beec05eaece
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-perm-01.ll
@@ -0,0 +1,175 @@
+; Test vector splat.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test v16i8 splat of the first element.
+define <16 x i8> @f1(<16 x i8> %val) {
+; CHECK-LABEL: f1:
+; CHECK: vrepb %v24, %v24, 0
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val, <16 x i8> undef,
+                       <16 x i32> zeroinitializer
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 splat of the last element.
+define <16 x i8> @f2(<16 x i8> %val) {
+; CHECK-LABEL: f2:
+; CHECK: vrepb %v24, %v24, 15
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val, <16 x i8> undef,
+                       <16 x i32> <i32 15, i32 15, i32 15, i32 15,
+                                   i32 15, i32 15, i32 15, i32 15,
+                                   i32 15, i32 15, i32 15, i32 15,
+                                   i32 15, i32 15, i32 15, i32 15>
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 splat of an arbitrary element, using the second operand of
+; the shufflevector.
+define <16 x i8> @f3(<16 x i8> %val) {
+; CHECK-LABEL: f3:
+; CHECK: vrepb %v24, %v24, 4
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> undef, <16 x i8> %val,
+                       <16 x i32> <i32 20, i32 20, i32 20, i32 20,
+                                   i32 20, i32 20, i32 20, i32 20,
+                                   i32 20, i32 20, i32 20, i32 20,
+                                   i32 20, i32 20, i32 20, i32 20>
+  ret <16 x i8> %ret
+}
+
+; Test v8i16 splat of the first element.
+define <8 x i16> @f4(<8 x i16> %val) {
+; CHECK-LABEL: f4:
+; CHECK: vreph %v24, %v24, 0
+; CHECK: br %r14
+  %ret = shufflevector <8 x i16> %val, <8 x i16> undef,
+                       <8 x i32> zeroinitializer
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 splat of the last element.
+define <8 x i16> @f5(<8 x i16> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vreph %v24, %v24, 7
+; CHECK: br %r14
+  %ret = shufflevector <8 x i16> %val, <8 x i16> undef,
+                       <8 x i32> <i32 7, i32 7, i32 7, i32 7,
+                                  i32 7, i32 7, i32 7, i32 7>
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 splat of an arbitrary element, using the second operand of
+; the shufflevector.
+define <8 x i16> @f6(<8 x i16> %val) {
+; CHECK-LABEL: f6:
+; CHECK: vreph %v24, %v24, 2
+; CHECK: br %r14
+  %ret = shufflevector <8 x i16> undef, <8 x i16> %val,
+                       <8 x i32> <i32 10, i32 10, i32 10, i32 10,
+                                  i32 10, i32 10, i32 10, i32 10>
+  ret <8 x i16> %ret
+}
+
+; Test v4i32 splat of the first element.
+define <4 x i32> @f7(<4 x i32> %val) {
+; CHECK-LABEL: f7:
+; CHECK: vrepf %v24, %v24, 0
+; CHECK: br %r14
+  %ret = shufflevector <4 x i32> %val, <4 x i32> undef,
+                       <4 x i32> zeroinitializer
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 splat of the last element.
+define <4 x i32> @f8(<4 x i32> %val) {
+; CHECK-LABEL: f8:
+; CHECK: vrepf %v24, %v24, 3
+; CHECK: br %r14
+  %ret = shufflevector <4 x i32> %val, <4 x i32> undef,
+                       <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 splat of an arbitrary element, using the second operand of
+; the shufflevector.
+define <4 x i32> @f9(<4 x i32> %val) {
+; CHECK-LABEL: f9:
+; CHECK: vrepf %v24, %v24, 1
+; CHECK: br %r14
+  %ret = shufflevector <4 x i32> undef, <4 x i32> %val,
+                       <4 x i32> <i32 5, i32 5, i32 5, i32 5>
+  ret <4 x i32> %ret
+}
+
+; Test v2i64 splat of the first element.
+define <2 x i64> @f10(<2 x i64> %val) {
+; CHECK-LABEL: f10:
+; CHECK: vrepg %v24, %v24, 0
+; CHECK: br %r14
+  %ret = shufflevector <2 x i64> %val, <2 x i64> undef,
+                       <2 x i32> zeroinitializer
+  ret <2 x i64> %ret
+}
+
+; Test v2i64 splat of the last element.
+define <2 x i64> @f11(<2 x i64> %val) {
+; CHECK-LABEL: f11:
+; CHECK: vrepg %v24, %v24, 1
+; CHECK: br %r14
+  %ret = shufflevector <2 x i64> %val, <2 x i64> undef,
+                       <2 x i32> <i32 1, i32 1>
+  ret <2 x i64> %ret
+}
+
+; Test v4f32 splat of the first element.
+define <4 x float> @f12(<4 x float> %val) {
+; CHECK-LABEL: f12:
+; CHECK: vrepf %v24, %v24, 0
+; CHECK: br %r14
+  %ret = shufflevector <4 x float> %val, <4 x float> undef,
+                       <4 x i32> zeroinitializer
+  ret <4 x float> %ret
+}
+
+; Test v4f32 splat of the last element.
+define <4 x float> @f13(<4 x float> %val) {
+; CHECK-LABEL: f13:
+; CHECK: vrepf %v24, %v24, 3
+; CHECK: br %r14
+  %ret = shufflevector <4 x float> %val, <4 x float> undef,
+                       <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+  ret <4 x float> %ret
+}
+
+; Test v4f32 splat of an arbitrary element, using the second operand of
+; the shufflevector.
+define <4 x float> @f14(<4 x float> %val) {
+; CHECK-LABEL: f14:
+; CHECK: vrepf %v24, %v24, 1
+; CHECK: br %r14
+  %ret = shufflevector <4 x float> undef, <4 x float> %val,
+                       <4 x i32> <i32 5, i32 5, i32 5, i32 5>
+  ret <4 x float> %ret
+}
+
+; Test v2f64 splat of the first element.
+define <2 x double> @f15(<2 x double> %val) {
+; CHECK-LABEL: f15:
+; CHECK: vrepg %v24, %v24, 0
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val, <2 x double> undef,
+                       <2 x i32> zeroinitializer
+  ret <2 x double> %ret
+}
+
+; Test v2f64 splat of the last element.
+define <2 x double> @f16(<2 x double> %val) {
+; CHECK-LABEL: f16:
+; CHECK: vrepg %v24, %v24, 1
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val, <2 x double> undef,
+                       <2 x i32> <i32 1, i32 1>
+  ret <2 x double> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-perm-02.ll b/test/CodeGen/SystemZ/vec-perm-02.ll
new file mode 100644
index 000000000000..e5c6df8e955a
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-perm-02.ll
@@ -0,0 +1,200 @@
+; Test replications of a scalar register value, represented as splats.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test v16i8 splat of the first element.
+define <16 x i8> @f1(i8 %scalar) {
+; CHECK-LABEL: f1:
+; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2
+; CHECK: vrepb %v24, [[REG]], 7
+; CHECK: br %r14
+  %val = insertelement <16 x i8> undef, i8 %scalar, i32 0
+  %ret = shufflevector <16 x i8> %val, <16 x i8> undef,
+                       <16 x i32> zeroinitializer
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 splat of the last element.
+define <16 x i8> @f2(i8 %scalar) {
+; CHECK-LABEL: f2:
+; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2
+; CHECK: vrepb %v24, [[REG]], 7
+; CHECK: br %r14
+  %val = insertelement <16 x i8> undef, i8 %scalar, i32 15
+  %ret = shufflevector <16 x i8> %val, <16 x i8> undef,
+                       <16 x i32> <i32 15, i32 15, i32 15, i32 15,
+                                   i32 15, i32 15, i32 15, i32 15,
+                                   i32 15, i32 15, i32 15, i32 15,
+                                   i32 15, i32 15, i32 15, i32 15>
+  ret <16 x i8> %ret
+}
+
+; Test v16i8 splat of an arbitrary element, using the second operand of
+; the shufflevector.
+define <16 x i8> @f3(i8 %scalar) {
+; CHECK-LABEL: f3:
+; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2
+; CHECK: vrepb %v24, [[REG]], 7
+; CHECK: br %r14
+  %val = insertelement <16 x i8> undef, i8 %scalar, i32 4
+  %ret = shufflevector <16 x i8> undef, <16 x i8> %val,
+                       <16 x i32> <i32 20, i32 20, i32 20, i32 20,
+                                   i32 20, i32 20, i32 20, i32 20,
+                                   i32 20, i32 20, i32 20, i32 20,
+                                   i32 20, i32 20, i32 20, i32 20>
+  ret <16 x i8> %ret
+}
+
+; Test v8i16 splat of the first element.
+define <8 x i16> @f4(i16 %scalar) {
+; CHECK-LABEL: f4:
+; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2
+; CHECK: vreph %v24, [[REG]], 3
+; CHECK: br %r14
+  %val = insertelement <8 x i16> undef, i16 %scalar, i32 0
+  %ret = shufflevector <8 x i16> %val, <8 x i16> undef,
+                       <8 x i32> zeroinitializer
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 splat of the last element.
+define <8 x i16> @f5(i16 %scalar) {
+; CHECK-LABEL: f5:
+; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2
+; CHECK: vreph %v24, [[REG]], 3
+; CHECK: br %r14
+  %val = insertelement <8 x i16> undef, i16 %scalar, i32 7
+  %ret = shufflevector <8 x i16> %val, <8 x i16> undef,
+                       <8 x i32> <i32 7, i32 7, i32 7, i32 7,
+                                  i32 7, i32 7, i32 7, i32 7>
+  ret <8 x i16> %ret
+}
+
+; Test v8i16 splat of an arbitrary element, using the second operand of
+; the shufflevector.
+define <8 x i16> @f6(i16 %scalar) {
+; CHECK-LABEL: f6:
+; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2
+; CHECK: vreph %v24, [[REG]], 3
+; CHECK: br %r14
+  %val = insertelement <8 x i16> undef, i16 %scalar, i32 2
+  %ret = shufflevector <8 x i16> undef, <8 x i16> %val,
+                       <8 x i32> <i32 10, i32 10, i32 10, i32 10,
+                                  i32 10, i32 10, i32 10, i32 10>
+  ret <8 x i16> %ret
+}
+
+; Test v4i32 splat of the first element.
+define <4 x i32> @f7(i32 %scalar) {
+; CHECK-LABEL: f7:
+; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2
+; CHECK: vrepf %v24, [[REG]], 1
+; CHECK: br %r14
+  %val = insertelement <4 x i32> undef, i32 %scalar, i32 0
+  %ret = shufflevector <4 x i32> %val, <4 x i32> undef,
+                       <4 x i32> zeroinitializer
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 splat of the last element.
+define <4 x i32> @f8(i32 %scalar) {
+; CHECK-LABEL: f8:
+; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2
+; CHECK: vrepf %v24, [[REG]], 1
+; CHECK: br %r14
+  %val = insertelement <4 x i32> undef, i32 %scalar, i32 3
+  %ret = shufflevector <4 x i32> %val, <4 x i32> undef,
+                       <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+  ret <4 x i32> %ret
+}
+
+; Test v4i32 splat of an arbitrary element, using the second operand of
+; the shufflevector.
+define <4 x i32> @f9(i32 %scalar) {
+; CHECK-LABEL: f9:
+; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2
+; CHECK: vrepf %v24, [[REG]], 1
+; CHECK: br %r14
+  %val = insertelement <4 x i32> undef, i32 %scalar, i32 1
+  %ret = shufflevector <4 x i32> undef, <4 x i32> %val,
+                       <4 x i32> <i32 5, i32 5, i32 5, i32 5>
+  ret <4 x i32> %ret
+}
+
+; Test v2i64 splat of the first element.
+define <2 x i64> @f10(i64 %scalar) {
+; CHECK-LABEL: f10:
+; CHECK: vlvgp %v24, %r2, %r2
+; CHECK: br %r14
+  %val = insertelement <2 x i64> undef, i64 %scalar, i32 0
+  %ret = shufflevector <2 x i64> %val, <2 x i64> undef,
+                       <2 x i32> zeroinitializer
+  ret <2 x i64> %ret
+}
+
+; Test v2i64 splat of the last element.
+define <2 x i64> @f11(i64 %scalar) {
+; CHECK-LABEL: f11:
+; CHECK: vlvgp %v24, %r2, %r2
+; CHECK: br %r14
+  %val = insertelement <2 x i64> undef, i64 %scalar, i32 1
+  %ret = shufflevector <2 x i64> %val, <2 x i64> undef,
+                       <2 x i32> <i32 1, i32 1>
+  ret <2 x i64> %ret
+}
+
+; Test v4f32 splat of the first element.
+define <4 x float> @f12(float %scalar) {
+; CHECK-LABEL: f12:
+; CHECK: vrepf %v24, %v0, 0
+; CHECK: br %r14
+  %val = insertelement <4 x float> undef, float %scalar, i32 0
+  %ret = shufflevector <4 x float> %val, <4 x float> undef,
+                       <4 x i32> zeroinitializer
+  ret <4 x float> %ret
+}
+
+; Test v4f32 splat of the last element.
+define <4 x float> @f13(float %scalar) {
+; CHECK-LABEL: f13:
+; CHECK: vrepf %v24, %v0, 0
+; CHECK: br %r14
+  %val = insertelement <4 x float> undef, float %scalar, i32 3
+  %ret = shufflevector <4 x float> %val, <4 x float> undef,
+                       <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+  ret <4 x float> %ret
+}
+
+; Test v4f32 splat of an arbitrary element, using the second operand of
+; the shufflevector.
+define <4 x float> @f14(float %scalar) {
+; CHECK-LABEL: f14:
+; CHECK: vrepf %v24, %v0, 0
+; CHECK: br %r14
+  %val = insertelement <4 x float> undef, float %scalar, i32 1
+  %ret = shufflevector <4 x float> undef, <4 x float> %val,
+                       <4 x i32> <i32 5, i32 5, i32 5, i32 5>
+  ret <4 x float> %ret
+}
+
+; Test v2f64 splat of the first element.
+define <2 x double> @f15(double %scalar) {
+; CHECK-LABEL: f15:
+; CHECK: vrepg %v24, %v0, 0
+; CHECK: br %r14
+  %val = insertelement <2 x double> undef, double %scalar, i32 0
+  %ret = shufflevector <2 x double> %val, <2 x double> undef,
+                       <2 x i32> zeroinitializer
+  ret <2 x double> %ret
+}
+
+; Test v2f64 splat of the last element.
+define <2 x double> @f16(double %scalar) {
+; CHECK-LABEL: f16:
+; CHECK: vrepg %v24, %v0, 0
+; CHECK: br %r14
+  %val = insertelement <2 x double> undef, double %scalar, i32 1
+  %ret = shufflevector <2 x double> %val, <2 x double> undef,
+                       <2 x i32> <i32 1, i32 1>
+  ret <2 x double> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-perm-03.ll b/test/CodeGen/SystemZ/vec-perm-03.ll
new file mode 100644
index 000000000000..663815549c33
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-perm-03.ll
@@ -0,0 +1,251 @@
+; Test replications of a scalar memory value, represented as splats.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 replicating load with no offset.
+define <16 x i8> @f1(i8 *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: vlrepb %v24, 0(%r2)
+; CHECK: br %r14
+  %scalar = load i8, i8 *%ptr
+  %val = insertelement <16 x i8> undef, i8 %scalar, i32 0
+  %ret = shufflevector <16 x i8> %val, <16 x i8> undef,
+                       <16 x i32> zeroinitializer
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 replicating load with the maximum in-range offset.
+define <16 x i8> @f2(i8 *%base) {
+; CHECK-LABEL: f2:
+; CHECK: vlrepb %v24, 4095(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i64 4095
+  %scalar = load i8, i8 *%ptr
+  %val = insertelement <16 x i8> undef, i8 %scalar, i32 0
+  %ret = shufflevector <16 x i8> %val, <16 x i8> undef,
+                       <16 x i32> zeroinitializer
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 replicating load with the first out-of-range offset.
+define <16 x i8> @f3(i8 *%base) {
+; CHECK-LABEL: f3:
+; CHECK: aghi %r2, 4096
+; CHECK: vlrepb %v24, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i8, i8 *%base, i64 4096
+  %scalar = load i8, i8 *%ptr
+  %val = insertelement <16 x i8> undef, i8 %scalar, i32 0
+  %ret = shufflevector <16 x i8> %val, <16 x i8> undef,
+                       <16 x i32> zeroinitializer
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 replicating load with no offset.
+define <8 x i16> @f4(i16 *%ptr) {
+; CHECK-LABEL: f4:
+; CHECK: vlreph %v24, 0(%r2)
+; CHECK: br %r14
+  %scalar = load i16, i16 *%ptr
+  %val = insertelement <8 x i16> undef, i16 %scalar, i32 0
+  %ret = shufflevector <8 x i16> %val, <8 x i16> undef,
+                       <8 x i32> zeroinitializer
+  ret <8 x i16> %ret
+}
+
+; Test a v8i16 replicating load with the maximum in-range offset.
+define <8 x i16> @f5(i16 *%base) {
+; CHECK-LABEL: f5:
+; CHECK: vlreph %v24, 4094(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i16, i16 *%base, i64 2047
+  %scalar = load i16, i16 *%ptr
+  %val = insertelement <8 x i16> undef, i16 %scalar, i32 0
+  %ret = shufflevector <8 x i16> %val, <8 x i16> undef,
+                       <8 x i32> zeroinitializer
+  ret <8 x i16> %ret
+}
+
+; Test a v8i16 replicating load with the first out-of-range offset.
+define <8 x i16> @f6(i16 *%base) {
+; CHECK-LABEL: f6:
+; CHECK: aghi %r2, 4096
+; CHECK: vlreph %v24, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i16, i16 *%base, i64 2048
+  %scalar = load i16, i16 *%ptr
+  %val = insertelement <8 x i16> undef, i16 %scalar, i32 0
+  %ret = shufflevector <8 x i16> %val, <8 x i16> undef,
+                       <8 x i32> zeroinitializer
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 replicating load with no offset.
+define <4 x i32> @f7(i32 *%ptr) {
+; CHECK-LABEL: f7:
+; CHECK: vlrepf %v24, 0(%r2)
+; CHECK: br %r14
+  %scalar = load i32, i32 *%ptr
+  %val = insertelement <4 x i32> undef, i32 %scalar, i32 0
+  %ret = shufflevector <4 x i32> %val, <4 x i32> undef,
+                       <4 x i32> zeroinitializer
+  ret <4 x i32> %ret
+}
+
+; Test a v4i32 replicating load with the maximum in-range offset.
+define <4 x i32> @f8(i32 *%base) {
+; CHECK-LABEL: f8:
+; CHECK: vlrepf %v24, 4092(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i32, i32 *%base, i64 1023
+  %scalar = load i32, i32 *%ptr
+  %val = insertelement <4 x i32> undef, i32 %scalar, i32 0
+  %ret = shufflevector <4 x i32> %val, <4 x i32> undef,
+                       <4 x i32> zeroinitializer
+  ret <4 x i32> %ret
+}
+
+; Test a v4i32 replicating load with the first out-of-range offset.
+define <4 x i32> @f9(i32 *%base) {
+; CHECK-LABEL: f9:
+; CHECK: aghi %r2, 4096
+; CHECK: vlrepf %v24, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i32, i32 *%base, i64 1024
+  %scalar = load i32, i32 *%ptr
+  %val = insertelement <4 x i32> undef, i32 %scalar, i32 0
+  %ret = shufflevector <4 x i32> %val, <4 x i32> undef,
+                       <4 x i32> zeroinitializer
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 replicating load with no offset.
+define <2 x i64> @f10(i64 *%ptr) {
+; CHECK-LABEL: f10:
+; CHECK: vlrepg %v24, 0(%r2)
+; CHECK: br %r14
+  %scalar = load i64, i64 *%ptr
+  %val = insertelement <2 x i64> undef, i64 %scalar, i32 0
+  %ret = shufflevector <2 x i64> %val, <2 x i64> undef,
+                       <2 x i32> zeroinitializer
+  ret <2 x i64> %ret
+}
+
+; Test a v2i64 replicating load with the maximum in-range offset.
+define <2 x i64> @f11(i64 *%base) {
+; CHECK-LABEL: f11:
+; CHECK: vlrepg %v24, 4088(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i32 511
+  %scalar = load i64, i64 *%ptr
+  %val = insertelement <2 x i64> undef, i64 %scalar, i32 0
+  %ret = shufflevector <2 x i64> %val, <2 x i64> undef,
+                       <2 x i32> zeroinitializer
+  ret <2 x i64> %ret
+}
+
+; Test a v2i64 replicating load with the first out-of-range offset.
+define <2 x i64> @f12(i64 *%base) {
+; CHECK-LABEL: f12:
+; CHECK: aghi %r2, 4096
+; CHECK: vlrepg %v24, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i32 512
+  %scalar = load i64, i64 *%ptr
+  %val = insertelement <2 x i64> undef, i64 %scalar, i32 0
+  %ret = shufflevector <2 x i64> %val, <2 x i64> undef,
+                       <2 x i32> zeroinitializer
+  ret <2 x i64> %ret
+}
+
+; Test a v4f32 replicating load with no offset.
+define <4 x float> @f13(float *%ptr) {
+; CHECK-LABEL: f13:
+; CHECK: vlrepf %v24, 0(%r2)
+; CHECK: br %r14
+  %scalar = load float, float *%ptr
+  %val = insertelement <4 x float> undef, float %scalar, i32 0
+  %ret = shufflevector <4 x float> %val, <4 x float> undef,
+                       <4 x i32> zeroinitializer
+  ret <4 x float> %ret
+}
+
+; Test a v4f32 replicating load with the maximum in-range offset.
+define <4 x float> @f14(float *%base) {
+; CHECK-LABEL: f14:
+; CHECK: vlrepf %v24, 4092(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr float, float *%base, i64 1023
+  %scalar = load float, float *%ptr
+  %val = insertelement <4 x float> undef, float %scalar, i32 0
+  %ret = shufflevector <4 x float> %val, <4 x float> undef,
+                       <4 x i32> zeroinitializer
+  ret <4 x float> %ret
+}
+
+; Test a v4f32 replicating load with the first out-of-range offset.
+define <4 x float> @f15(float *%base) {
+; CHECK-LABEL: f15:
+; CHECK: aghi %r2, 4096
+; CHECK: vlrepf %v24, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr float, float *%base, i64 1024
+  %scalar = load float, float *%ptr
+  %val = insertelement <4 x float> undef, float %scalar, i32 0
+  %ret = shufflevector <4 x float> %val, <4 x float> undef,
+                       <4 x i32> zeroinitializer
+  ret <4 x float> %ret
+}
+
+; Test a v2f64 replicating load with no offset.
+define <2 x double> @f16(double *%ptr) {
+; CHECK-LABEL: f16:
+; CHECK: vlrepg %v24, 0(%r2)
+; CHECK: br %r14
+  %scalar = load double, double *%ptr
+  %val = insertelement <2 x double> undef, double %scalar, i32 0
+  %ret = shufflevector <2 x double> %val, <2 x double> undef,
+                       <2 x i32> zeroinitializer
+  ret <2 x double> %ret
+}
+
+; Test a v2f64 replicating load with the maximum in-range offset.
+define <2 x double> @f17(double *%base) {
+; CHECK-LABEL: f17:
+; CHECK: vlrepg %v24, 4088(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr double, double *%base, i32 511
+  %scalar = load double, double *%ptr
+  %val = insertelement <2 x double> undef, double %scalar, i32 0
+  %ret = shufflevector <2 x double> %val, <2 x double> undef,
+                       <2 x i32> zeroinitializer
+  ret <2 x double> %ret
+}
+
+; Test a v2f64 replicating load with the first out-of-range offset.
+define <2 x double> @f18(double *%base) {
+; CHECK-LABEL: f18:
+; CHECK: aghi %r2, 4096
+; CHECK: vlrepg %v24, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr double, double *%base, i32 512
+  %scalar = load double, double *%ptr
+  %val = insertelement <2 x double> undef, double %scalar, i32 0
+  %ret = shufflevector <2 x double> %val, <2 x double> undef,
+                       <2 x i32> zeroinitializer
+  ret <2 x double> %ret
+}
+
+; Test a v16i8 replicating load with an index.
+define <16 x i8> @f19(i8 *%base, i64 %index) {
+; CHECK-LABEL: f19:
+; CHECK: vlrepb %v24, 1023(%r3,%r2)
+; CHECK: br %r14
+  %ptr1 = getelementptr i8, i8 *%base, i64 %index
+  %ptr = getelementptr i8, i8 *%ptr1, i64 1023
+  %scalar = load i8, i8 *%ptr
+  %val = insertelement <16 x i8> undef, i8 %scalar, i32 0
+  %ret = shufflevector <16 x i8> %val, <16 x i8> undef,
+                       <16 x i32> zeroinitializer
+  ret <16 x i8> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-perm-04.ll b/test/CodeGen/SystemZ/vec-perm-04.ll
new file mode 100644
index 000000000000..0df6f4fbb012
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-perm-04.ll
@@ -0,0 +1,200 @@
+; Test vector merge high.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a canonical v16i8 merge high.
+define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vmrhb %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 0, i32 16, i32 1, i32 17,
+                                   i32 2, i32 18, i32 3, i32 19,
+                                   i32 4, i32 20, i32 5, i32 21,
+                                   i32 6, i32 22, i32 7, i32 23>
+  ret <16 x i8> %ret
+}
+
+; Test a reversed v16i8 merge high.
+define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vmrhb %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 16, i32 0, i32 17, i32 1,
+                                   i32 18, i32 2, i32 19, i32 3,
+                                   i32 20, i32 4, i32 21, i32 5,
+                                   i32 22, i32 6, i32 23, i32 7>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 merge high with only the first operand being used.
+define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vmrhb %v24, %v24, %v24
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 0, i32 0, i32 1, i32 1,
+                                   i32 2, i32 2, i32 3, i32 3,
+                                   i32 4, i32 4, i32 5, i32 5,
+                                   i32 6, i32 6, i32 7, i32 7>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 merge high with only the second operand being used.
+; This is converted into @f3 by target-independent code.
+define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vmrhb %v24, %v26, %v26
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 16, i32 16, i32 17, i32 17,
+                                   i32 18, i32 18, i32 19, i32 19,
+                                   i32 20, i32 20, i32 21, i32 21,
+                                   i32 22, i32 22, i32 23, i32 23>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 merge with both operands being the same.  This too is
+; converted into @f3 by target-independent code.
+define <16 x i8> @f5(<16 x i8> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vmrhb %v24, %v24, %v24
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val, <16 x i8> %val,
+                       <16 x i32> <i32 0, i32 16, i32 17, i32 17,
+                                   i32 18, i32 2, i32 3, i32 3,
+                                   i32 20, i32 20, i32 5, i32 5,
+                                   i32 6, i32 22, i32 23, i32 7>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 merge in which some of the indices are don't care.
+define <16 x i8> @f6(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vmrhb %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 0, i32 undef, i32 1, i32 17,
+                                   i32 undef, i32 18, i32 undef, i32 undef,
+                                   i32 undef, i32 20, i32 5, i32 21,
+                                   i32 undef, i32 22, i32 7, i32 undef>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 merge in which one of the operands is undefined and where
+; indices for that operand are "don't care".  Target-independent code
+; converts the indices themselves into "undef"s.
+define <16 x i8> @f7(<16 x i8> %val) {
+; CHECK-LABEL: f7:
+; CHECK: vmrhb %v24, %v24, %v24
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> undef, <16 x i8> %val,
+                       <16 x i32> <i32 11, i32 16, i32 17, i32 5,
+                                   i32 18, i32 10, i32 19, i32 19,
+                                   i32 20, i32 20, i32 21, i32 3,
+                                   i32 2, i32 22, i32 9, i32 23>
+  ret <16 x i8> %ret
+}
+
+; Test a canonical v8i16 merge high.
+define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vmrhh %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
+                       <8 x i32> <i32 0, i32 8, i32 1, i32 9,
+                                  i32 2, i32 10, i32 3, i32 11>
+  ret <8 x i16> %ret
+}
+
+; Test a reversed v8i16 merge high.
+define <8 x i16> @f9(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f9:
+; CHECK: vmrhh %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
+                       <8 x i32> <i32 8, i32 0, i32 9, i32 1,
+                                  i32 10, i32 2, i32 11, i32 3>
+  ret <8 x i16> %ret
+}
+
+; Test a canonical v4i32 merge high.
+define <4 x i32> @f10(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f10:
+; CHECK: vmrhf %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
+                       <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+  ret <4 x i32> %ret
+}
+
+; Test a reversed v4i32 merge high.
+define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f11:
+; CHECK: vmrhf %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
+                       <4 x i32> <i32 4, i32 0, i32 5, i32 1>
+  ret <4 x i32> %ret
+}
+
+; Test a canonical v2i64 merge high.
+define <2 x i64> @f12(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f12:
+; CHECK: vmrhg %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <2 x i64> %val1, <2 x i64> %val2,
+                       <2 x i32> <i32 0, i32 2>
+  ret <2 x i64> %ret
+}
+
+; Test a reversed v2i64 merge high.
+define <2 x i64> @f13(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f13:
+; CHECK: vmrhg %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <2 x i64> %val1, <2 x i64> %val2,
+                       <2 x i32> <i32 2, i32 0>
+  ret <2 x i64> %ret
+}
+
+; Test a canonical v4f32 merge high.
+define <4 x float> @f14(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f14:
+; CHECK: vmrhf %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <4 x float> %val1, <4 x float> %val2,
+                       <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+  ret <4 x float> %ret
+}
+
+; Test a reversed v4f32 merge high.
+define <4 x float> @f15(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f15:
+; CHECK: vmrhf %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <4 x float> %val1, <4 x float> %val2,
+                       <4 x i32> <i32 4, i32 0, i32 5, i32 1>
+  ret <4 x float> %ret
+}
+
+; Test a canonical v2f64 merge high.
+define <2 x double> @f16(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f16:
+; CHECK: vmrhg %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val1, <2 x double> %val2,
+                       <2 x i32> <i32 0, i32 2>
+  ret <2 x double> %ret
+}
+
+; Test a reversed v2f64 merge high.
+define <2 x double> @f17(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f17:
+; CHECK: vmrhg %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val1, <2 x double> %val2,
+                       <2 x i32> <i32 2, i32 0>
+  ret <2 x double> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-perm-05.ll b/test/CodeGen/SystemZ/vec-perm-05.ll
new file mode 100644
index 000000000000..b585cefbf845
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-perm-05.ll
@@ -0,0 +1,200 @@
+; Test vector merge low.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a canonical v16i8 merge low.
+define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vmrlb %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 8, i32 24, i32 9, i32 25,
+                                   i32 10, i32 26, i32 11, i32 27,
+                                   i32 12, i32 28, i32 13, i32 29,
+                                   i32 14, i32 30, i32 15, i32 31>
+  ret <16 x i8> %ret
+}
+
+; Test a reversed v16i8 merge low.
+define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vmrlb %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 24, i32 8, i32 25, i32 9,
+                                   i32 26, i32 10, i32 27, i32 11,
+                                   i32 28, i32 12, i32 29, i32 13,
+                                   i32 30, i32 14, i32 31, i32 15>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 merge low with only the first operand being used.
+define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vmrlb %v24, %v24, %v24
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 8, i32 8, i32 9, i32 9,
+                                   i32 10, i32 10, i32 11, i32 11,
+                                   i32 12, i32 12, i32 13, i32 13,
+                                   i32 14, i32 14, i32 15, i32 15>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 merge low with only the second operand being used.
+; This is converted into @f3 by target-independent code.
+define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vmrlb %v24, %v26, %v26
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 24, i32 24, i32 25, i32 25,
+                                   i32 26, i32 26, i32 27, i32 27,
+                                   i32 28, i32 28, i32 29, i32 29,
+                                   i32 30, i32 30, i32 31, i32 31>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 merge with both operands being the same.  This too is
+; converted into @f3 by target-independent code.
+define <16 x i8> @f5(<16 x i8> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vmrlb %v24, %v24, %v24
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val, <16 x i8> %val,
+                       <16 x i32> <i32 8, i32 24, i32 25, i32 25,
+                                   i32 26, i32 10, i32 11, i32 11,
+                                   i32 28, i32 28, i32 13, i32 13,
+                                   i32 14, i32 30, i32 31, i32 15>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 merge in which some of the indices are don't care.
+define <16 x i8> @f6(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vmrlb %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 8, i32 undef, i32 9, i32 25,
+                                   i32 undef, i32 26, i32 undef, i32 undef,
+                                   i32 undef, i32 28, i32 13, i32 29,
+                                   i32 undef, i32 30, i32 15, i32 undef>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 merge in which one of the operands is undefined and where
+; indices for that operand are "don't care".  Target-independent code
+; converts the indices themselves into "undef"s.
+define <16 x i8> @f7(<16 x i8> %val) {
+; CHECK-LABEL: f7:
+; CHECK: vmrlb %v24, %v24, %v24
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> undef, <16 x i8> %val,
+                       <16 x i32> <i32 11, i32 24, i32 25, i32 5,
+                                   i32 26, i32 10, i32 27, i32 27,
+                                   i32 28, i32 28, i32 29, i32 3,
+                                   i32 2, i32 30, i32 9, i32 31>
+  ret <16 x i8> %ret
+}
+
+; Test a canonical v8i16 merge low.
+define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vmrlh %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
+                       <8 x i32> <i32 4, i32 12, i32 5, i32 13,
+                                  i32 6, i32 14, i32 7, i32 15>
+  ret <8 x i16> %ret
+}
+
+; Test a reversed v8i16 merge low.
+define <8 x i16> @f9(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f9:
+; CHECK: vmrlh %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
+                       <8 x i32> <i32 12, i32 4, i32 13, i32 5,
+                                  i32 14, i32 6, i32 15, i32 7>
+  ret <8 x i16> %ret
+}
+
+; Test a canonical v4i32 merge low.
+define <4 x i32> @f10(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f10:
+; CHECK: vmrlf %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
+                       <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+  ret <4 x i32> %ret
+}
+
+; Test a reversed v4i32 merge low.
+define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f11:
+; CHECK: vmrlf %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
+                       <4 x i32> <i32 6, i32 2, i32 7, i32 3>
+  ret <4 x i32> %ret
+}
+
+; Test a canonical v2i64 merge low.
+define <2 x i64> @f12(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f12:
+; CHECK: vmrlg %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <2 x i64> %val1, <2 x i64> %val2,
+                       <2 x i32> <i32 1, i32 3>
+  ret <2 x i64> %ret
+}
+
+; Test a reversed v2i64 merge low.
+define <2 x i64> @f13(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f13:
+; CHECK: vmrlg %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <2 x i64> %val1, <2 x i64> %val2,
+                       <2 x i32> <i32 3, i32 1>
+  ret <2 x i64> %ret
+}
+
+; Test a canonical v4f32 merge low.
+define <4 x float> @f14(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f14:
+; CHECK: vmrlf %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <4 x float> %val1, <4 x float> %val2,
+                       <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+  ret <4 x float> %ret
+}
+
+; Test a reversed v4f32 merge low.
+define <4 x float> @f15(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f15:
+; CHECK: vmrlf %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <4 x float> %val1, <4 x float> %val2,
+                       <4 x i32> <i32 6, i32 2, i32 7, i32 3>
+  ret <4 x float> %ret
+}
+
+; Test a canonical v2f64 merge low.
+define <2 x double> @f16(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f16:
+; CHECK: vmrlg %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val1, <2 x double> %val2,
+                       <2 x i32> <i32 1, i32 3>
+  ret <2 x double> %ret
+}
+
+; Test a reversed v2f64 merge low.
+define <2 x double> @f17(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f17:
+; CHECK: vmrlg %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val1, <2 x double> %val2,
+                       <2 x i32> <i32 3, i32 1>
+  ret <2 x double> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-perm-06.ll b/test/CodeGen/SystemZ/vec-perm-06.ll
new file mode 100644
index 000000000000..835276a36725
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-perm-06.ll
@@ -0,0 +1,160 @@
+; Test vector pack.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a canonical v16i8 pack.
+define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vpkh %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 1, i32 3, i32 5, i32 7,
+                                   i32 9, i32 11, i32 13, i32 15,
+                                   i32 17, i32 19, i32 21, i32 23,
+                                   i32 25, i32 27, i32 29, i32 31>
+  ret <16 x i8> %ret
+}
+
+; Test a reversed v16i8 pack.
+define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vpkh %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 17, i32 19, i32 21, i32 23,
+                                   i32 25, i32 27, i32 29, i32 31,
+                                   i32 1, i32 3, i32 5, i32 7,
+                                   i32 9, i32 11, i32 13, i32 15>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 pack with only the first operand being used.
+define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vpkh %v24, %v24, %v24
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 1, i32 3, i32 5, i32 7,
+                                   i32 9, i32 11, i32 13, i32 15,
+                                   i32 1, i32 3, i32 5, i32 7,
+                                   i32 9, i32 11, i32 13, i32 15>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 pack with only the second operand being used.
+; This is converted into @f3 by target-independent code.
+define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vpkh %v24, %v26, %v26
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 17, i32 19, i32 21, i32 23,
+                                   i32 25, i32 27, i32 29, i32 31,
+                                   i32 17, i32 19, i32 21, i32 23,
+                                   i32 25, i32 27, i32 29, i32 31>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 pack with both operands being the same.  This too is
+; converted into @f3 by target-independent code.
+define <16 x i8> @f5(<16 x i8> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vpkh %v24, %v24, %v24
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val, <16 x i8> %val,
+                       <16 x i32> <i32 1, i32 3, i32 5, i32 7,
+                                   i32 9, i32 11, i32 13, i32 15,
+                                   i32 17, i32 19, i32 21, i32 23,
+                                   i32 25, i32 27, i32 29, i32 31>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 pack in which some of the indices are don't care.
+define <16 x i8> @f6(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vpkh %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 1, i32 undef, i32 5, i32 7,
+                                   i32 undef, i32 11, i32 undef, i32 undef,
+                                   i32 undef, i32 19, i32 21, i32 23,
+                                   i32 undef, i32 27, i32 29, i32 undef>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 pack in which one of the operands is undefined and where
+; indices for that operand are "don't care".  Target-independent code
+; converts the indices themselves into "undef"s.
+define <16 x i8> @f7(<16 x i8> %val) {
+; CHECK-LABEL: f7:
+; CHECK: vpkh %v24, %v24, %v24
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> undef, <16 x i8> %val,
+                       <16 x i32> <i32 7, i32 1, i32 9, i32 15,
+                                   i32 15, i32 3, i32 5, i32 1,
+                                   i32 17, i32 19, i32 21, i32 23,
+                                   i32 25, i32 27, i32 29, i32 31>
+  ret <16 x i8> %ret
+}
+
+; Test a canonical v8i16 pack.
+define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vpkf %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
+                       <8 x i32> <i32 1, i32 3, i32 5, i32 7,
+                                  i32 9, i32 11, i32 13, i32 15>
+  ret <8 x i16> %ret
+}
+
+; Test a reversed v8i16 pack.
+define <8 x i16> @f9(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f9:
+; CHECK: vpkf %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
+                       <8 x i32> <i32 9, i32 11, i32 13, i32 15,
+                                  i32 1, i32 3, i32 5, i32 7>
+  ret <8 x i16> %ret
+}
+
+; Test a canonical v4i32 pack.
+define <4 x i32> @f10(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f10:
+; CHECK: vpkg %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
+                       <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  ret <4 x i32> %ret
+}
+
+; Test a reversed v4i32 pack.
+define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f11:
+; CHECK: vpkg %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
+                       <4 x i32> <i32 5, i32 7, i32 1, i32 3>
+  ret <4 x i32> %ret
+}
+
+; Test a canonical v4f32 pack.
+define <4 x float> @f12(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f12:
+; CHECK: vpkg %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <4 x float> %val1, <4 x float> %val2,
+                       <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  ret <4 x float> %ret
+}
+
+; Test a reversed v4f32 pack.
+define <4 x float> @f13(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f13:
+; CHECK: vpkg %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <4 x float> %val1, <4 x float> %val2,
+                       <4 x i32> <i32 5, i32 7, i32 1, i32 3>
+  ret <4 x float> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-perm-07.ll b/test/CodeGen/SystemZ/vec-perm-07.ll
new file mode 100644
index 000000000000..9a370af2c0e7
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-perm-07.ll
@@ -0,0 +1,145 @@
+; Test vector shift left double immediate.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 shift with the lowest useful shift amount.
+define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vsldb %v24, %v24, %v26, 1
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 1, i32 2, i32 3, i32 4,
+                                   i32 5, i32 6, i32 7, i32 8,
+                                   i32 9, i32 10, i32 11, i32 12,
+                                   i32 13, i32 14, i32 15, i32 16>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 shift with the highest shift amount.
+define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vsldb %v24, %v24, %v26, 15
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 15, i32 16, i32 17, i32 18,
+                                   i32 19, i32 20, i32 21, i32 22,
+                                   i32 23, i32 24, i32 25, i32 26,
+                                   i32 27, i32 28, i32 29, i32 30>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 shift in which the operands need to be reversed.
+define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vsldb %v24, %v26, %v24, 4
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 20, i32 21, i32 22, i32 23,
+                                   i32 24, i32 25, i32 26, i32 27,
+                                   i32 28, i32 29, i32 30, i32 31,
+                                   i32 0, i32 1, i32 2, i32 3>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 shift in which the operands need to be duplicated.
+define <16 x i8> @f4(<16 x i8> %val) {
+; CHECK-LABEL: f4:
+; CHECK: vsldb %v24, %v24, %v24, 7
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val, <16 x i8> undef,
+                       <16 x i32> <i32 7, i32 8, i32 9, i32 10,
+                                   i32 11, i32 12, i32 13, i32 14,
+                                   i32 15, i32 0, i32 1, i32 2,
+                                   i32 3, i32 4, i32 5, i32 6>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 shift in which some of the indices are undefs.
+define <16 x i8> @f5(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vsldb %v24, %v24, %v26, 11
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef,
+                                   i32 15, i32 16, i32 undef, i32 18,
+                                   i32 19, i32 20, i32 21, i32 22,
+                                   i32 23, i32 24, i32 25, i32 26>
+  ret <16 x i8> %ret
+}
+
+; ...and again with reversed operands.
+define <16 x i8> @f6(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vsldb %v24, %v26, %v24, 13
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 undef, i32 undef, i32 31, i32 0,
+                                   i32 1, i32 2, i32 3, i32 4,
+                                   i32 5, i32 6, i32 7, i32 8,
+                                   i32 9, i32 10, i32 11, i32 12>
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 shift with the lowest useful shift amount.
+define <8 x i16> @f7(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vsldb %v24, %v24, %v26, 2
+; CHECK: br %r14
+  %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
+                       <8 x i32> <i32 1, i32 2, i32 3, i32 4,
+                                  i32 5, i32 6, i32 7, i32 8>
+  ret <8 x i16> %ret
+}
+
+; Test a v8i16 shift with the highest useful shift amount.
+define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vsldb %v24, %v24, %v26, 14
+; CHECK: br %r14
+  %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
+                       <8 x i32> <i32 7, i32 8, i32 9, i32 10,
+                                  i32 11, i32 12, i32 13, i32 14>
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 shift with the lowest useful shift amount.
+define <4 x i32> @f9(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f9:
+; CHECK: vsldb %v24, %v24, %v26, 4
+; CHECK: br %r14
+  %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
+                       <4 x i32> <i32 1, i32 2, i32 3, i32 4>
+  ret <4 x i32> %ret
+}
+
+; Test a v4i32 shift with the highest useful shift amount.
+define <4 x i32> @f10(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f10:
+; CHECK: vsldb %v24, %v24, %v26, 12
+; CHECK: br %r14
+  %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
+                       <4 x i32> <i32 3, i32 4, i32 5, i32 6>
+  ret <4 x i32> %ret
+}
+
+; Test a v4f32 shift with the lowest useful shift amount.
+define <4 x float> @f12(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f12:
+; CHECK: vsldb %v24, %v24, %v26, 4
+; CHECK: br %r14
+  %ret = shufflevector <4 x float> %val1, <4 x float> %val2,
+                       <4 x i32> <i32 1, i32 2, i32 3, i32 4>
+  ret <4 x float> %ret
+}
+
+; Test a v4f32 shift with the highest useful shift amount.
+define <4 x float> @f13(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f13:
+; CHECK: vsldb %v24, %v24, %v26, 12
+; CHECK: br %r14
+  %ret = shufflevector <4 x float> %val1, <4 x float> %val2,
+                       <4 x i32> <i32 3, i32 4, i32 5, i32 6>
+  ret <4 x float> %ret
+}
+
+; We use VPDI for v2i64 shuffles.
diff --git a/test/CodeGen/SystemZ/vec-perm-08.ll b/test/CodeGen/SystemZ/vec-perm-08.ll
new file mode 100644
index 000000000000..a18ca7b73975
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-perm-08.ll
@@ -0,0 +1,170 @@
+; Test vector permutes using VPDI.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a high1/low2 permute for v16i8.
+define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vpdi %v24, %v24, %v26, 1
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 0, i32 1, i32 2, i32 3,
+                                   i32 4, i32 5, i32 6, i32 7,
+                                   i32 24, i32 25, i32 26, i32 27,
+                                   i32 28, i32 29, i32 30, i32 31>
+  ret <16 x i8> %ret
+}
+
+; Test a low2/high1 permute for v16i8.
+define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vpdi %v24, %v26, %v24, 4
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 24, i32 25, i32 26, i32 27,
+                                   i32 28, i32 29, i32 30, i32 31,
+                                   i32 0, i32 1, i32 2, i32 3,
+                                   i32 4, i32 5, i32 6, i32 7>
+  ret <16 x i8> %ret
+}
+
+; Test a low1/high2 permute for v16i8.
+define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vpdi %v24, %v24, %v26, 4
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 8, i32 9, i32 10, i32 undef,
+                                   i32 12, i32 undef, i32 14, i32 15,
+                                   i32 16, i32 17, i32 undef, i32 19,
+                                   i32 20, i32 21, i32 22, i32 undef>
+  ret <16 x i8> %ret
+}
+
+; Test a high2/low1 permute for v16i8.
+define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vpdi %v24, %v26, %v24, 1
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 16, i32 17, i32 18, i32 19,
+                                   i32 20, i32 21, i32 22, i32 23,
+                                   i32 8, i32 9, i32 10, i32 11,
+                                   i32 12, i32 13, i32 14, i32 15>
+  ret <16 x i8> %ret
+}
+
+; Test reversing two doublewords in a v16i8.
+define <16 x i8> @f5(<16 x i8> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vpdi %v24, %v24, %v24, 4
+; CHECK: br %r14
+  %ret = shufflevector <16 x i8> %val, <16 x i8> undef,
+                       <16 x i32> <i32 8, i32 9, i32 10, i32 11,
+                                   i32 12, i32 13, i32 14, i32 15,
+                                   i32 0, i32 1, i32 2, i32 3,
+                                   i32 4, i32 5, i32 6, i32 7>
+  ret <16 x i8> %ret
+}
+
+; Test a high1/low2 permute for v8i16.
+define <8 x i16> @f6(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vpdi %v24, %v24, %v26, 1
+; CHECK: br %r14
+  %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
+                       <8 x i32> <i32 0, i32 1, i32 2, i32 3,
+                                  i32 12, i32 13, i32 14, i32 15>
+  ret <8 x i16> %ret
+}
+
+; Test a low2/high1 permute for v8i16.
+define <8 x i16> @f7(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: vpdi %v24, %v26, %v24, 4
+; CHECK: br %r14
+  %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
+                       <8 x i32> <i32 12, i32 13, i32 14, i32 15,
+                                  i32 0, i32 1, i32 2, i32 3>
+  ret <8 x i16> %ret
+}
+
+; Test a high1/low2 permute for v4i32.
+define <4 x i32> @f8(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vpdi %v24, %v24, %v26, 1
+; CHECK: br %r14
+  %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
+                       <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+  ret <4 x i32> %ret
+}
+
+; Test a low2/high1 permute for v4i32.
+define <4 x i32> @f9(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f9:
+; CHECK: vpdi %v24, %v26, %v24, 4
+; CHECK: br %r14
+  %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
+                       <4 x i32> <i32 6, i32 7, i32 0, i32 1>
+  ret <4 x i32> %ret
+}
+
+; Test a high1/low2 permute for v2i64.
+define <2 x i64> @f10(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f10:
+; CHECK: vpdi %v24, %v24, %v26, 1
+; CHECK: br %r14
+  %ret = shufflevector <2 x i64> %val1, <2 x i64> %val2,
+                       <2 x i32> <i32 0, i32 3>
+  ret <2 x i64> %ret
+}
+
+; Test low2/high1 permute for v2i64.
+define <2 x i64> @f11(<2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f11:
+; CHECK: vpdi %v24, %v26, %v24, 4
+; CHECK: br %r14
+  %ret = shufflevector <2 x i64> %val1, <2 x i64> %val2,
+                       <2 x i32> <i32 3, i32 0>
+  ret <2 x i64> %ret
+}
+
+; Test a high1/low2 permute for v4f32.
+define <4 x float> @f12(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f12:
+; CHECK: vpdi %v24, %v24, %v26, 1
+; CHECK: br %r14
+  %ret = shufflevector <4 x float> %val1, <4 x float> %val2,
+                       <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+  ret <4 x float> %ret
+}
+
+; Test a low2/high1 permute for v4f32.
+define <4 x float> @f13(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f13:
+; CHECK: vpdi %v24, %v26, %v24, 4
+; CHECK: br %r14
+  %ret = shufflevector <4 x float> %val1, <4 x float> %val2,
+                       <4 x i32> <i32 6, i32 7, i32 0, i32 1>
+  ret <4 x float> %ret
+}
+
+; Test a high1/low2 permute for v2f64.
+define <2 x double> @f14(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f14:
+; CHECK: vpdi %v24, %v24, %v26, 1
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val1, <2 x double> %val2,
+                       <2 x i32> <i32 0, i32 3>
+  ret <2 x double> %ret
+}
+
+; Test a low2/high1 permute for v2f64.
+define <2 x double> @f15(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f15:
+; CHECK: vpdi %v24, %v26, %v24, 4
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val1, <2 x double> %val2,
+                       <2 x i32> <i32 3, i32 0>
+  ret <2 x double> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-perm-09.ll b/test/CodeGen/SystemZ/vec-perm-09.ll
new file mode 100644
index 000000000000..9c9632cf0305
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-perm-09.ll
@@ -0,0 +1,38 @@
+; Test general vector permute of a v16i8.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | \
+; RUN:   FileCheck -check-prefix=CHECK-CODE %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | \
+; RUN:   FileCheck -check-prefix=CHECK-VECTOR %s
+
+define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-CODE-LABEL: f1:
+; CHECK-CODE: larl [[REG:%r[0-5]]],
+; CHECK-CODE: vl [[MASK:%v[0-9]+]], 0([[REG]])
+; CHECK-CODE: vperm %v24, %v24, %v26, [[MASK]]
+; CHECK-CODE: br %r14
+;
+; CHECK-VECTOR: .byte 1
+; CHECK-VECTOR-NEXT: .byte 19
+; CHECK-VECTOR-NEXT: .byte 6
+; CHECK-VECTOR-NEXT: .byte 5
+; CHECK-VECTOR-NEXT: .byte 20
+; CHECK-VECTOR-NEXT: .byte 22
+; CHECK-VECTOR-NEXT: .byte 1
+; CHECK-VECTOR-NEXT: .byte 1
+; CHECK-VECTOR-NEXT: .byte 25
+; CHECK-VECTOR-NEXT: .byte 29
+; CHECK-VECTOR-NEXT: .byte 11
+; Any byte would be OK here
+; CHECK-VECTOR-NEXT: .space 1
+; CHECK-VECTOR-NEXT: .byte 31
+; CHECK-VECTOR-NEXT: .byte 4
+; CHECK-VECTOR-NEXT: .byte 15
+; CHECK-VECTOR-NEXT: .byte 19
+  %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
+                       <16 x i32> <i32 1, i32 19, i32 6, i32 5,
+                                   i32 20, i32 22, i32 1, i32 1,
+                                   i32 25, i32 29, i32 11, i32 undef,
+                                   i32 31, i32 4, i32 15, i32 19>
+  ret <16 x i8> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-perm-10.ll b/test/CodeGen/SystemZ/vec-perm-10.ll
new file mode 100644
index 000000000000..382e6dc4c3fb
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-perm-10.ll
@@ -0,0 +1,36 @@
+; Test general vector permute of a v8i16.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | \
+; RUN:   FileCheck -check-prefix=CHECK-CODE %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | \
+; RUN:   FileCheck -check-prefix=CHECK-VECTOR %s
+
+define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-CODE-LABEL: f1:
+; CHECK-CODE: larl [[REG:%r[0-5]]],
+; CHECK-CODE: vl [[MASK:%v[0-9]+]], 0([[REG]])
+; CHECK-CODE: vperm %v24, %v26, %v24, [[MASK]]
+; CHECK-CODE: br %r14
+;
+; CHECK-VECTOR: .byte 0
+; CHECK-VECTOR-NEXT: .byte 1
+; CHECK-VECTOR-NEXT: .byte 26
+; CHECK-VECTOR-NEXT: .byte 27
+; Any 2 bytes would be OK here
+; CHECK-VECTOR-NEXT: .space 1
+; CHECK-VECTOR-NEXT: .space 1
+; CHECK-VECTOR-NEXT: .byte 28
+; CHECK-VECTOR-NEXT: .byte 29
+; CHECK-VECTOR-NEXT: .byte 6
+; CHECK-VECTOR-NEXT: .byte 7
+; CHECK-VECTOR-NEXT: .byte 14
+; CHECK-VECTOR-NEXT: .byte 15
+; CHECK-VECTOR-NEXT: .byte 8
+; CHECK-VECTOR-NEXT: .byte 9
+; CHECK-VECTOR-NEXT: .byte 16
+; CHECK-VECTOR-NEXT: .byte 17
+  %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
+                       <8 x i32> <i32 8, i32 5, i32 undef, i32 6,
+                                  i32 11, i32 15, i32 12, i32 0>
+  ret <8 x i16> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-perm-11.ll b/test/CodeGen/SystemZ/vec-perm-11.ll
new file mode 100644
index 000000000000..c9e29880fe07
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-perm-11.ll
@@ -0,0 +1,35 @@
+; Test general vector permute of a v4i32.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | \
+; RUN:   FileCheck -check-prefix=CHECK-CODE %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | \
+; RUN:   FileCheck -check-prefix=CHECK-VECTOR %s
+
+define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-CODE-LABEL: f1:
+; CHECK-CODE: larl [[REG:%r[0-5]]],
+; CHECK-CODE: vl [[MASK:%v[0-9]+]], 0([[REG]])
+; CHECK-CODE: vperm %v24, %v26, %v24, [[MASK]]
+; CHECK-CODE: br %r14
+;
+; CHECK-VECTOR: .byte 4
+; CHECK-VECTOR-NEXT: .byte 5
+; CHECK-VECTOR-NEXT: .byte 6
+; CHECK-VECTOR-NEXT: .byte 7
+; CHECK-VECTOR-NEXT: .byte 20
+; CHECK-VECTOR-NEXT: .byte 21
+; CHECK-VECTOR-NEXT: .byte 22
+; CHECK-VECTOR-NEXT: .byte 23
+; Any 4 bytes would be OK here
+; CHECK-VECTOR-NEXT: .space 1
+; CHECK-VECTOR-NEXT: .space 1
+; CHECK-VECTOR-NEXT: .space 1
+; CHECK-VECTOR-NEXT: .space 1
+; CHECK-VECTOR-NEXT: .byte 12
+; CHECK-VECTOR-NEXT: .byte 13
+; CHECK-VECTOR-NEXT: .byte 14
+; CHECK-VECTOR-NEXT: .byte 15
+  %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
+                       <4 x i32> <i32 5, i32 1, i32 undef, i32 7>
+  ret <4 x i32> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-round-01.ll b/test/CodeGen/SystemZ/vec-round-01.ll
new file mode 100644
index 000000000000..82718276bb08
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-round-01.ll
@@ -0,0 +1,118 @@
+; Test v2f64 rounding.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+declare double @llvm.rint.f64(double)
+declare double @llvm.nearbyint.f64(double)
+declare double @llvm.floor.f64(double)
+declare double @llvm.ceil.f64(double)
+declare double @llvm.trunc.f64(double)
+declare double @llvm.round.f64(double)
+declare <2 x double> @llvm.rint.v2f64(<2 x double>)
+declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>)
+declare <2 x double> @llvm.floor.v2f64(<2 x double>)
+declare <2 x double> @llvm.ceil.v2f64(<2 x double>)
+declare <2 x double> @llvm.trunc.v2f64(<2 x double>)
+declare <2 x double> @llvm.round.v2f64(<2 x double>)
+
+define <2 x double> @f1(<2 x double> %val) {
+; CHECK-LABEL: f1:
+; CHECK: vfidb %v24, %v24, 0, 0
+; CHECK: br %r14
+  %res = call <2 x double> @llvm.rint.v2f64(<2 x double> %val)
+  ret <2 x double> %res
+}
+
+define <2 x double> @f2(<2 x double> %val) {
+; CHECK-LABEL: f2:
+; CHECK: vfidb %v24, %v24, 4, 0
+; CHECK: br %r14
+  %res = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %val)
+  ret <2 x double> %res
+}
+
+define <2 x double> @f3(<2 x double> %val) {
+; CHECK-LABEL: f3:
+; CHECK: vfidb %v24, %v24, 4, 7
+; CHECK: br %r14
+  %res = call <2 x double> @llvm.floor.v2f64(<2 x double> %val)
+  ret <2 x double> %res
+}
+
+define <2 x double> @f4(<2 x double> %val) {
+; CHECK-LABEL: f4:
+; CHECK: vfidb %v24, %v24, 4, 6
+; CHECK: br %r14
+  %res = call <2 x double> @llvm.ceil.v2f64(<2 x double> %val)
+  ret <2 x double> %res
+}
+
+define <2 x double> @f5(<2 x double> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vfidb %v24, %v24, 4, 5
+; CHECK: br %r14
+  %res = call <2 x double> @llvm.trunc.v2f64(<2 x double> %val)
+  ret <2 x double> %res
+}
+
+define <2 x double> @f6(<2 x double> %val) {
+; CHECK-LABEL: f6:
+; CHECK: vfidb %v24, %v24, 4, 1
+; CHECK: br %r14
+  %res = call <2 x double> @llvm.round.v2f64(<2 x double> %val)
+  ret <2 x double> %res
+}
+
+define double @f7(<2 x double> %val) {
+; CHECK-LABEL: f7:
+; CHECK: wfidb %f0, %v24, 0, 0
+; CHECK: br %r14
+  %scalar = extractelement <2 x double> %val, i32 0
+  %res = call double @llvm.rint.f64(double %scalar)
+  ret double %res
+}
+
+define double @f8(<2 x double> %val) {
+; CHECK-LABEL: f8:
+; CHECK: wfidb %f0, %v24, 4, 0
+; CHECK: br %r14
+  %scalar = extractelement <2 x double> %val, i32 0
+  %res = call double @llvm.nearbyint.f64(double %scalar)
+  ret double %res
+}
+
+define double @f9(<2 x double> %val) {
+; CHECK-LABEL: f9:
+; CHECK: wfidb %f0, %v24, 4, 7
+; CHECK: br %r14
+  %scalar = extractelement <2 x double> %val, i32 0
+  %res = call double @llvm.floor.f64(double %scalar)
+  ret double %res
+}
+
+define double @f10(<2 x double> %val) {
+; CHECK-LABEL: f10:
+; CHECK: wfidb %f0, %v24, 4, 6
+; CHECK: br %r14
+  %scalar = extractelement <2 x double> %val, i32 0
+  %res = call double @llvm.ceil.f64(double %scalar)
+  ret double %res
+}
+
+define double @f11(<2 x double> %val) {
+; CHECK-LABEL: f11:
+; CHECK: wfidb %f0, %v24, 4, 5
+; CHECK: br %r14
+  %scalar = extractelement <2 x double> %val, i32 0
+  %res = call double @llvm.trunc.f64(double %scalar)
+  ret double %res
+}
+
+define double @f12(<2 x double> %val) {
+; CHECK-LABEL: f12:
+; CHECK: wfidb %f0, %v24, 4, 1
+; CHECK: br %r14
+  %scalar = extractelement <2 x double> %val, i32 0
+  %res = call double @llvm.round.f64(double %scalar)
+  ret double %res
+}
diff --git a/test/CodeGen/SystemZ/vec-shift-01.ll b/test/CodeGen/SystemZ/vec-shift-01.ll
new file mode 100644
index 000000000000..be8605b182c9
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-shift-01.ll
@@ -0,0 +1,39 @@
+; Test vector shift left with vector shift amount.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 shift.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: veslvb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = shl <16 x i8> %val1, %val2
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 shift.
+define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: veslvh %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = shl <8 x i16> %val1, %val2
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 shift.
+define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: veslvf %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = shl <4 x i32> %val1, %val2
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 shift.
+define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: veslvg %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = shl <2 x i64> %val1, %val2
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-shift-02.ll b/test/CodeGen/SystemZ/vec-shift-02.ll
new file mode 100644
index 000000000000..2825872e023d
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-shift-02.ll
@@ -0,0 +1,39 @@
+; Test vector arithmetic shift right with vector shift amount.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 shift.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vesravb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = ashr <16 x i8> %val1, %val2
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 shift.
+define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vesravh %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = ashr <8 x i16> %val1, %val2
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 shift.
+define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vesravf %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = ashr <4 x i32> %val1, %val2
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 shift.
+define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vesravg %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = ashr <2 x i64> %val1, %val2
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-shift-03.ll b/test/CodeGen/SystemZ/vec-shift-03.ll
new file mode 100644
index 000000000000..c923d8b5d452
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-shift-03.ll
@@ -0,0 +1,39 @@
+; Test vector logical shift right with vector shift amount.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 shift.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vesrlvb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = lshr <16 x i8> %val1, %val2
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 shift.
+define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vesrlvh %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = lshr <8 x i16> %val1, %val2
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 shift.
+define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vesrlvf %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = lshr <4 x i32> %val1, %val2
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 shift.
+define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vesrlvg %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = lshr <2 x i64> %val1, %val2
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-shift-04.ll b/test/CodeGen/SystemZ/vec-shift-04.ll
new file mode 100644
index 000000000000..6fd12897bf5a
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-shift-04.ll
@@ -0,0 +1,134 @@
+; Test vector shift left with scalar shift amount.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 shift by a variable.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, i32 %shift) {
+; CHECK-LABEL: f1:
+; CHECK: veslb %v24, %v26, 0(%r2)
+; CHECK: br %r14
+  %truncshift = trunc i32 %shift to i8
+  %shiftvec = insertelement <16 x i8> undef, i8 %truncshift, i32 0
+  %val2 = shufflevector <16 x i8> %shiftvec, <16 x i8> undef,
+                        <16 x i32> zeroinitializer
+  %ret = shl <16 x i8> %val1, %val2
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 shift by the lowest useful constant.
+define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val) {
+; CHECK-LABEL: f2:
+; CHECK: veslb %v24, %v26, 1
+; CHECK: br %r14
+  %ret = shl <16 x i8> %val, <i8 1, i8 1, i8 1, i8 1,
+                              i8 1, i8 1, i8 1, i8 1,
+                              i8 1, i8 1, i8 1, i8 1,
+                              i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 shift by the highest useful constant.
+define <16 x i8> @f3(<16 x i8> %dummy, <16 x i8> %val) {
+; CHECK-LABEL: f3:
+; CHECK: veslb %v24, %v26, 7
+; CHECK: br %r14
+  %ret = shl <16 x i8> %val, <i8 7, i8 7, i8 7, i8 7,
+                              i8 7, i8 7, i8 7, i8 7,
+                              i8 7, i8 7, i8 7, i8 7,
+                              i8 7, i8 7, i8 7, i8 7>
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 shift by a variable.
+define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, i32 %shift) {
+; CHECK-LABEL: f4:
+; CHECK: veslh %v24, %v26, 0(%r2)
+; CHECK: br %r14
+  %truncshift = trunc i32 %shift to i16
+  %shiftvec = insertelement <8 x i16> undef, i16 %truncshift, i32 0
+  %val2 = shufflevector <8 x i16> %shiftvec, <8 x i16> undef,
+                        <8 x i32> zeroinitializer
+  %ret = shl <8 x i16> %val1, %val2
+  ret <8 x i16> %ret
+}
+
+; Test a v8i16 shift by the lowest useful constant.
+define <8 x i16> @f5(<8 x i16> %dummy, <8 x i16> %val) {
+; CHECK-LABEL: f5:
+; CHECK: veslh %v24, %v26, 1
+; CHECK: br %r14
+  %ret = shl <8 x i16> %val, <i16 1, i16 1, i16 1, i16 1,
+                              i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %ret
+}
+
+; Test a v8i16 shift by the highest useful constant.
+define <8 x i16> @f6(<8 x i16> %dummy, <8 x i16> %val) {
+; CHECK-LABEL: f6:
+; CHECK: veslh %v24, %v26, 15
+; CHECK: br %r14
+  %ret = shl <8 x i16> %val, <i16 15, i16 15, i16 15, i16 15,
+                              i16 15, i16 15, i16 15, i16 15>
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 shift by a variable.
+define <4 x i32> @f7(<4 x i32> %dummy, <4 x i32> %val1, i32 %shift) {
+; CHECK-LABEL: f7:
+; CHECK: veslf %v24, %v26, 0(%r2)
+; CHECK: br %r14
+  %shiftvec = insertelement <4 x i32> undef, i32 %shift, i32 0
+  %val2 = shufflevector <4 x i32> %shiftvec, <4 x i32> undef,
+                        <4 x i32> zeroinitializer
+  %ret = shl <4 x i32> %val1, %val2
+  ret <4 x i32> %ret
+}
+
+; Test a v4i32 shift by the lowest useful constant.
+define <4 x i32> @f8(<4 x i32> %dummy, <4 x i32> %val) {
+; CHECK-LABEL: f8:
+; CHECK: veslf %v24, %v26, 1
+; CHECK: br %r14
+  %ret = shl <4 x i32> %val, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %ret
+}
+
+; Test a v4i32 shift by the highest useful constant.
+define <4 x i32> @f9(<4 x i32> %dummy, <4 x i32> %val) {
+; CHECK-LABEL: f9:
+; CHECK: veslf %v24, %v26, 31
+; CHECK: br %r14
+  %ret = shl <4 x i32> %val, <i32 31, i32 31, i32 31, i32 31>
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 shift by a variable.
+define <2 x i64> @f10(<2 x i64> %dummy, <2 x i64> %val1, i32 %shift) {
+; CHECK-LABEL: f10:
+; CHECK: veslg %v24, %v26, 0(%r2)
+; CHECK: br %r14
+  %extshift = sext i32 %shift to i64
+  %shiftvec = insertelement <2 x i64> undef, i64 %extshift, i32 0
+  %val2 = shufflevector <2 x i64> %shiftvec, <2 x i64> undef,
+                        <2 x i32> zeroinitializer
+  %ret = shl <2 x i64> %val1, %val2
+  ret <2 x i64> %ret
+}
+
+; Test a v2i64 shift by the lowest useful constant.
+define <2 x i64> @f11(<2 x i64> %dummy, <2 x i64> %val) {
+; CHECK-LABEL: f11:
+; CHECK: veslg %v24, %v26, 1
+; CHECK: br %r14
+  %ret = shl <2 x i64> %val, <i64 1, i64 1>
+  ret <2 x i64> %ret
+}
+
+; Test a v2i64 shift by the highest useful constant.
+define <2 x i64> @f12(<2 x i64> %dummy, <2 x i64> %val) {
+; CHECK-LABEL: f12:
+; CHECK: veslg %v24, %v26, 63
+; CHECK: br %r14
+  %ret = shl <2 x i64> %val, <i64 63, i64 63>
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-shift-05.ll b/test/CodeGen/SystemZ/vec-shift-05.ll
new file mode 100644
index 000000000000..22ce46b2d0d6
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-shift-05.ll
@@ -0,0 +1,134 @@
+; Test vector arithmetic shift right with scalar shift amount.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 shift by a variable.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, i32 %shift) {
+; CHECK-LABEL: f1:
+; CHECK: vesrab %v24, %v26, 0(%r2)
+; CHECK: br %r14
+  %truncshift = trunc i32 %shift to i8
+  %shiftvec = insertelement <16 x i8> undef, i8 %truncshift, i32 0
+  %val2 = shufflevector <16 x i8> %shiftvec, <16 x i8> undef,
+                        <16 x i32> zeroinitializer
+  %ret = ashr <16 x i8> %val1, %val2
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 shift by the lowest useful constant.
+define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val) {
+; CHECK-LABEL: f2:
+; CHECK: vesrab %v24, %v26, 1
+; CHECK: br %r14
+  %ret = ashr <16 x i8> %val, <i8 1, i8 1, i8 1, i8 1,
+                               i8 1, i8 1, i8 1, i8 1,
+                               i8 1, i8 1, i8 1, i8 1,
+                               i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 shift by the highest useful constant.
+define <16 x i8> @f3(<16 x i8> %dummy, <16 x i8> %val) {
+; CHECK-LABEL: f3:
+; CHECK: vesrab %v24, %v26, 7
+; CHECK: br %r14
+  %ret = ashr <16 x i8> %val, <i8 7, i8 7, i8 7, i8 7,
+                               i8 7, i8 7, i8 7, i8 7,
+                               i8 7, i8 7, i8 7, i8 7,
+                               i8 7, i8 7, i8 7, i8 7>
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 shift by a variable.
+define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, i32 %shift) {
+; CHECK-LABEL: f4:
+; CHECK: vesrah %v24, %v26, 0(%r2)
+; CHECK: br %r14
+  %truncshift = trunc i32 %shift to i16
+  %shiftvec = insertelement <8 x i16> undef, i16 %truncshift, i32 0
+  %val2 = shufflevector <8 x i16> %shiftvec, <8 x i16> undef,
+                        <8 x i32> zeroinitializer
+  %ret = ashr <8 x i16> %val1, %val2
+  ret <8 x i16> %ret
+}
+
+; Test a v8i16 shift by the lowest useful constant.
+define <8 x i16> @f5(<8 x i16> %dummy, <8 x i16> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vesrah %v24, %v26, 1
+; CHECK: br %r14
+  %ret = ashr <8 x i16> %val, <i16 1, i16 1, i16 1, i16 1,
+                               i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %ret
+}
+
+; Test a v8i16 shift by the highest useful constant.
+define <8 x i16> @f6(<8 x i16> %dummy, <8 x i16> %val) {
+; CHECK-LABEL: f6:
+; CHECK: vesrah %v24, %v26, 15
+; CHECK: br %r14
+  %ret = ashr <8 x i16> %val, <i16 15, i16 15, i16 15, i16 15,
+                               i16 15, i16 15, i16 15, i16 15>
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 shift by a variable.
+define <4 x i32> @f7(<4 x i32> %dummy, <4 x i32> %val1, i32 %shift) {
+; CHECK-LABEL: f7:
+; CHECK: vesraf %v24, %v26, 0(%r2)
+; CHECK: br %r14
+  %shiftvec = insertelement <4 x i32> undef, i32 %shift, i32 0
+  %val2 = shufflevector <4 x i32> %shiftvec, <4 x i32> undef,
+                        <4 x i32> zeroinitializer
+  %ret = ashr <4 x i32> %val1, %val2
+  ret <4 x i32> %ret
+}
+
+; Test a v4i32 shift by the lowest useful constant.
+define <4 x i32> @f8(<4 x i32> %dummy, <4 x i32> %val) {
+; CHECK-LABEL: f8:
+; CHECK: vesraf %v24, %v26, 1
+; CHECK: br %r14
+  %ret = ashr <4 x i32> %val, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %ret
+}
+
+; Test a v4i32 shift by the highest useful constant.
+define <4 x i32> @f9(<4 x i32> %dummy, <4 x i32> %val) {
+; CHECK-LABEL: f9:
+; CHECK: vesraf %v24, %v26, 31
+; CHECK: br %r14
+  %ret = ashr <4 x i32> %val, <i32 31, i32 31, i32 31, i32 31>
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 shift by a variable.
+define <2 x i64> @f10(<2 x i64> %dummy, <2 x i64> %val1, i32 %shift) {
+; CHECK-LABEL: f10:
+; CHECK: vesrag %v24, %v26, 0(%r2)
+; CHECK: br %r14
+  %extshift = sext i32 %shift to i64
+  %shiftvec = insertelement <2 x i64> undef, i64 %extshift, i32 0
+  %val2 = shufflevector <2 x i64> %shiftvec, <2 x i64> undef,
+                        <2 x i32> zeroinitializer
+  %ret = ashr <2 x i64> %val1, %val2
+  ret <2 x i64> %ret
+}
+
+; Test a v2i64 shift by the lowest useful constant.
+define <2 x i64> @f11(<2 x i64> %dummy, <2 x i64> %val) {
+; CHECK-LABEL: f11:
+; CHECK: vesrag %v24, %v26, 1
+; CHECK: br %r14
+  %ret = ashr <2 x i64> %val, <i64 1, i64 1>
+  ret <2 x i64> %ret
+}
+
+; Test a v2i64 shift by the highest useful constant.
+define <2 x i64> @f12(<2 x i64> %dummy, <2 x i64> %val) {
+; CHECK-LABEL: f12:
+; CHECK: vesrag %v24, %v26, 63
+; CHECK: br %r14
+  %ret = ashr <2 x i64> %val, <i64 63, i64 63>
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-shift-06.ll b/test/CodeGen/SystemZ/vec-shift-06.ll
new file mode 100644
index 000000000000..8a5bb0a9a55a
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-shift-06.ll
@@ -0,0 +1,134 @@
+; Test vector logical shift right with scalar shift amount.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 shift by a variable.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, i32 %shift) {
+; CHECK-LABEL: f1:
+; CHECK: vesrlb %v24, %v26, 0(%r2)
+; CHECK: br %r14
+  %truncshift = trunc i32 %shift to i8
+  %shiftvec = insertelement <16 x i8> undef, i8 %truncshift, i32 0
+  %val2 = shufflevector <16 x i8> %shiftvec, <16 x i8> undef,
+                        <16 x i32> zeroinitializer
+  %ret = lshr <16 x i8> %val1, %val2
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 shift by the lowest useful constant.
+define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val) {
+; CHECK-LABEL: f2:
+; CHECK: vesrlb %v24, %v26, 1
+; CHECK: br %r14
+  %ret = lshr <16 x i8> %val, <i8 1, i8 1, i8 1, i8 1,
+                               i8 1, i8 1, i8 1, i8 1,
+                               i8 1, i8 1, i8 1, i8 1,
+                               i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %ret
+}
+
+; Test a v16i8 shift by the highest useful constant.
+define <16 x i8> @f3(<16 x i8> %dummy, <16 x i8> %val) {
+; CHECK-LABEL: f3:
+; CHECK: vesrlb %v24, %v26, 7
+; CHECK: br %r14
+  %ret = lshr <16 x i8> %val, <i8 7, i8 7, i8 7, i8 7,
+                               i8 7, i8 7, i8 7, i8 7,
+                               i8 7, i8 7, i8 7, i8 7,
+                               i8 7, i8 7, i8 7, i8 7>
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 shift by a variable.
+define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, i32 %shift) {
+; CHECK-LABEL: f4:
+; CHECK: vesrlh %v24, %v26, 0(%r2)
+; CHECK: br %r14
+  %truncshift = trunc i32 %shift to i16
+  %shiftvec = insertelement <8 x i16> undef, i16 %truncshift, i32 0
+  %val2 = shufflevector <8 x i16> %shiftvec, <8 x i16> undef,
+                        <8 x i32> zeroinitializer
+  %ret = lshr <8 x i16> %val1, %val2
+  ret <8 x i16> %ret
+}
+
+; Test a v8i16 shift by the lowest useful constant.
+define <8 x i16> @f5(<8 x i16> %dummy, <8 x i16> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vesrlh %v24, %v26, 1
+; CHECK: br %r14
+  %ret = lshr <8 x i16> %val, <i16 1, i16 1, i16 1, i16 1,
+                               i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %ret
+}
+
+; Test a v8i16 shift by the highest useful constant.
+define <8 x i16> @f6(<8 x i16> %dummy, <8 x i16> %val) {
+; CHECK-LABEL: f6:
+; CHECK: vesrlh %v24, %v26, 15
+; CHECK: br %r14
+  %ret = lshr <8 x i16> %val, <i16 15, i16 15, i16 15, i16 15,
+                               i16 15, i16 15, i16 15, i16 15>
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 shift by a variable.
+define <4 x i32> @f7(<4 x i32> %dummy, <4 x i32> %val1, i32 %shift) {
+; CHECK-LABEL: f7:
+; CHECK: vesrlf %v24, %v26, 0(%r2)
+; CHECK: br %r14
+  %shiftvec = insertelement <4 x i32> undef, i32 %shift, i32 0
+  %val2 = shufflevector <4 x i32> %shiftvec, <4 x i32> undef,
+                        <4 x i32> zeroinitializer
+  %ret = lshr <4 x i32> %val1, %val2
+  ret <4 x i32> %ret
+}
+
+; Test a v4i32 shift by the lowest useful constant.
+define <4 x i32> @f8(<4 x i32> %dummy, <4 x i32> %val) {
+; CHECK-LABEL: f8:
+; CHECK: vesrlf %v24, %v26, 1
+; CHECK: br %r14
+  %ret = lshr <4 x i32> %val, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %ret
+}
+
+; Test a v4i32 shift by the highest useful constant.
+define <4 x i32> @f9(<4 x i32> %dummy, <4 x i32> %val) {
+; CHECK-LABEL: f9:
+; CHECK: vesrlf %v24, %v26, 31
+; CHECK: br %r14
+  %ret = lshr <4 x i32> %val, <i32 31, i32 31, i32 31, i32 31>
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 shift by a variable.
+define <2 x i64> @f10(<2 x i64> %dummy, <2 x i64> %val1, i32 %shift) {
+; CHECK-LABEL: f10:
+; CHECK: vesrlg %v24, %v26, 0(%r2)
+; CHECK: br %r14
+  %extshift = sext i32 %shift to i64
+  %shiftvec = insertelement <2 x i64> undef, i64 %extshift, i32 0
+  %val2 = shufflevector <2 x i64> %shiftvec, <2 x i64> undef,
+                        <2 x i32> zeroinitializer
+  %ret = lshr <2 x i64> %val1, %val2
+  ret <2 x i64> %ret
+}
+
+; Test a v2i64 shift by the lowest useful constant.
+define <2 x i64> @f11(<2 x i64> %dummy, <2 x i64> %val) {
+; CHECK-LABEL: f11:
+; CHECK: vesrlg %v24, %v26, 1
+; CHECK: br %r14
+  %ret = lshr <2 x i64> %val, <i64 1, i64 1>
+  ret <2 x i64> %ret
+}
+
+; Test a v2i64 shift by the highest useful constant.
+define <2 x i64> @f12(<2 x i64> %dummy, <2 x i64> %val) {
+; CHECK-LABEL: f12:
+; CHECK: vesrlg %v24, %v26, 63
+; CHECK: br %r14
+  %ret = lshr <2 x i64> %val, <i64 63, i64 63>
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-shift-07.ll b/test/CodeGen/SystemZ/vec-shift-07.ll
new file mode 100644
index 000000000000..f229c5e25a46
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-shift-07.ll
@@ -0,0 +1,182 @@
+; Test vector sign extensions.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i1->v16i8 extension.
+define <16 x i8> @f1(<16 x i8> %val) {
+; CHECK-LABEL: f1:
+; CHECK: veslb [[REG:%v[0-9]+]], %v24, 7
+; CHECK: vesrab %v24, [[REG]], 7
+; CHECK: br %r14
+  %trunc = trunc <16 x i8> %val to <16 x i1>
+  %ret = sext <16 x i1> %trunc to <16 x i8>
+  ret <16 x i8> %ret
+}
+
+; Test a v8i1->v8i16 extension.
+define <8 x i16> @f2(<8 x i16> %val) {
+; CHECK-LABEL: f2:
+; CHECK: veslh [[REG:%v[0-9]+]], %v24, 15
+; CHECK: vesrah %v24, [[REG]], 15
+; CHECK: br %r14
+  %trunc = trunc <8 x i16> %val to <8 x i1>
+  %ret = sext <8 x i1> %trunc to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test a v8i8->v8i16 extension.
+define <8 x i16> @f3(<8 x i16> %val) {
+; CHECK-LABEL: f3:
+; CHECK: veslh [[REG:%v[0-9]+]], %v24, 8
+; CHECK: vesrah %v24, [[REG]], 8
+; CHECK: br %r14
+  %trunc = trunc <8 x i16> %val to <8 x i8>
+  %ret = sext <8 x i8> %trunc to <8 x i16>
+  ret <8 x i16> %ret
+}
+
+; Test a v4i1->v4i32 extension.
+define <4 x i32> @f4(<4 x i32> %val) {
+; CHECK-LABEL: f4:
+; CHECK: veslf [[REG:%v[0-9]+]], %v24, 31
+; CHECK: vesraf %v24, [[REG]], 31
+; CHECK: br %r14
+  %trunc = trunc <4 x i32> %val to <4 x i1>
+  %ret = sext <4 x i1> %trunc to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test a v4i8->v4i32 extension.
+define <4 x i32> @f5(<4 x i32> %val) {
+; CHECK-LABEL: f5:
+; CHECK: veslf [[REG:%v[0-9]+]], %v24, 24
+; CHECK: vesraf %v24, [[REG]], 24
+; CHECK: br %r14
+  %trunc = trunc <4 x i32> %val to <4 x i8>
+  %ret = sext <4 x i8> %trunc to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test a v4i16->v4i32 extension.
+define <4 x i32> @f6(<4 x i32> %val) {
+; CHECK-LABEL: f6:
+; CHECK: veslf [[REG:%v[0-9]+]], %v24, 16
+; CHECK: vesraf %v24, [[REG]], 16
+; CHECK: br %r14
+  %trunc = trunc <4 x i32> %val to <4 x i16>
+  %ret = sext <4 x i16> %trunc to <4 x i32>
+  ret <4 x i32> %ret
+}
+
+; Test a v2i1->v2i64 extension.
+define <2 x i64> @f7(<2 x i64> %val) {
+; CHECK-LABEL: f7:
+; CHECK: veslg [[REG:%v[0-9]+]], %v24, 63
+; CHECK: vesrag %v24, [[REG]], 63
+; CHECK: br %r14
+  %trunc = trunc <2 x i64> %val to <2 x i1>
+  %ret = sext <2 x i1> %trunc to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test a v2i8->v2i64 extension.
+define <2 x i64> @f8(<2 x i64> %val) {
+; CHECK-LABEL: f8:
+; CHECK: vsegb %v24, %v24
+; CHECK: br %r14
+  %trunc = trunc <2 x i64> %val to <2 x i8>
+  %ret = sext <2 x i8> %trunc to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test a v2i16->v2i64 extension.
+define <2 x i64> @f9(<2 x i64> %val) {
+; CHECK-LABEL: f9:
+; CHECK: vsegh %v24, %v24
+; CHECK: br %r14
+  %trunc = trunc <2 x i64> %val to <2 x i16>
+  %ret = sext <2 x i16> %trunc to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test a v2i32->v2i64 extension.
+define <2 x i64> @f10(<2 x i64> %val) {
+; CHECK-LABEL: f10:
+; CHECK: vsegf %v24, %v24
+; CHECK: br %r14
+  %trunc = trunc <2 x i64> %val to <2 x i32>
+  %ret = sext <2 x i32> %trunc to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test an alternative v2i8->v2i64 extension.
+define <2 x i64> @f11(<2 x i64> %val) {
+; CHECK-LABEL: f11:
+; CHECK: vsegb %v24, %v24
+; CHECK: br %r14
+  %shl = shl <2 x i64> %val, <i64 56, i64 56>
+  %ret = ashr <2 x i64> %shl, <i64 56, i64 56>
+  ret <2 x i64> %ret
+}
+
+; Test an alternative v2i16->v2i64 extension.
+define <2 x i64> @f12(<2 x i64> %val) {
+; CHECK-LABEL: f12:
+; CHECK: vsegh %v24, %v24
+; CHECK: br %r14
+  %shl = shl <2 x i64> %val, <i64 48, i64 48>
+  %ret = ashr <2 x i64> %shl, <i64 48, i64 48>
+  ret <2 x i64> %ret
+}
+
+; Test an alternative v2i32->v2i64 extension.
+define <2 x i64> @f13(<2 x i64> %val) {
+; CHECK-LABEL: f13:
+; CHECK: vsegf %v24, %v24
+; CHECK: br %r14
+  %shl = shl <2 x i64> %val, <i64 32, i64 32>
+  %ret = ashr <2 x i64> %shl, <i64 32, i64 32>
+  ret <2 x i64> %ret
+}
+
+; Test an extraction-based v2i8->v2i64 extension.
+define <2 x i64> @f14(<16 x i8> %val) {
+; CHECK-LABEL: f14:
+; CHECK: vsegb %v24, %v24
+; CHECK: br %r14
+  %elt0 = extractelement <16 x i8> %val, i32 7
+  %elt1 = extractelement <16 x i8> %val, i32 15
+  %ext0 = sext i8 %elt0 to i64
+  %ext1 = sext i8 %elt1 to i64
+  %vec0 = insertelement <2 x i64> undef, i64 %ext0, i32 0
+  %vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1
+  ret <2 x i64> %vec1
+}
+
+; Test an extraction-based v2i16->v2i64 extension.
+define <2 x i64> @f15(<16 x i16> %val) {
+; CHECK-LABEL: f15:
+; CHECK: vsegh %v24, %v24
+; CHECK: br %r14
+  %elt0 = extractelement <16 x i16> %val, i32 3
+  %elt1 = extractelement <16 x i16> %val, i32 7
+  %ext0 = sext i16 %elt0 to i64
+  %ext1 = sext i16 %elt1 to i64
+  %vec0 = insertelement <2 x i64> undef, i64 %ext0, i32 0
+  %vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1
+  ret <2 x i64> %vec1
+}
+
+; Test an extraction-based v2i32->v2i64 extension.
+define <2 x i64> @f16(<16 x i32> %val) {
+; CHECK-LABEL: f16:
+; CHECK: vsegf %v24, %v24
+; CHECK: br %r14
+  %elt0 = extractelement <16 x i32> %val, i32 1
+  %elt1 = extractelement <16 x i32> %val, i32 3
+  %ext0 = sext i32 %elt0 to i64
+  %ext1 = sext i32 %elt1 to i64
+  %vec0 = insertelement <2 x i64> undef, i64 %ext0, i32 0
+  %vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1
+  ret <2 x i64> %vec1
+}
diff --git a/test/CodeGen/SystemZ/vec-sqrt-01.ll b/test/CodeGen/SystemZ/vec-sqrt-01.ll
new file mode 100644
index 000000000000..5c3ffb3b0643
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-sqrt-01.ll
@@ -0,0 +1,23 @@
+; Test f64 and v2f64 square root.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+declare double @llvm.sqrt.f64(double)
+declare <2 x double> @llvm.sqrt.v2f64(<2 x double>)
+
+define <2 x double> @f1(<2 x double> %val) {
+; CHECK-LABEL: f1:
+; CHECK: vfsqdb %v24, %v24
+; CHECK: br %r14
+  %ret = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %val)
+  ret <2 x double> %ret
+}
+
+define double @f2(<2 x double> %val) {
+; CHECK-LABEL: f2:
+; CHECK: wfsqdb %f0, %v24
+; CHECK: br %r14
+  %scalar = extractelement <2 x double> %val, i32 0
+  %ret = call double @llvm.sqrt.f64(double %scalar)
+  ret double %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-sub-01.ll b/test/CodeGen/SystemZ/vec-sub-01.ll
new file mode 100644
index 000000000000..4afad8bef659
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-sub-01.ll
@@ -0,0 +1,148 @@
+; Test vector subtraction.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 subtraction.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vsb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = sub <16 x i8> %val1, %val2
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 subtraction.
+define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vsh %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = sub <8 x i16> %val1, %val2
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 subtraction.
+define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vsf %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = sub <4 x i32> %val1, %val2
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 subtraction.
+define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vsg %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = sub <2 x i64> %val1, %val2
+  ret <2 x i64> %ret
+}
+
+; Test a v4f32 subtraction, as an example of an operation that needs to be
+; scalarized and reassembled.  At present there's an unnecessary move that
+; could be avoided with smarter ordering.  It also isn't important whether
+; the VSLDBs use the result of the VLRs or use %v24 and %v26 directly.
+define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f5:
+; CHECK-DAG: vlr %v[[A1:[0-5]]], %v24
+; CHECK-DAG: vlr %v[[A2:[0-5]]], %v26
+; CHECK-DAG: vrepf %v[[B1:[0-5]]], %v[[A1]], 1
+; CHECK-DAG: vrepf %v[[B2:[0-5]]], %v[[A2]], 1
+; CHECK-DAG: vrepf %v[[C1:[0-5]]], %v[[A1]], 2
+; CHECK-DAG: vrepf %v[[C2:[0-5]]], %v[[A2]], 2
+; CHECK-DAG: vrepf %v[[D1:[0-5]]], %v[[A1]], 3
+; CHECK-DAG: vrepf %v[[D2:[0-5]]], %v[[A2]], 3
+; CHECK-DAG: ler %f[[A1copy:[0-5]]], %f[[A1]]
+; CHECK-DAG: sebr %f[[A1copy]], %f[[A2]]
+; CHECK-DAG: sebr %f[[B1]], %f[[B2]]
+; CHECK-DAG: sebr %f[[C1]], %f[[C2]]
+; CHECK-DAG: sebr %f[[D1]], %f[[D2]]
+; CHECK-DAG: vmrhf [[HIGH:%v[0-9]+]], %v[[A1copy]], %v[[B1]]
+; CHECK-DAG: vmrhf [[LOW:%v[0-9]+]], %v[[C1]], %v[[D1]]
+; CHECK: vmrhg %v24, [[HIGH]], [[LOW]]
+; CHECK: br %r14
+  %ret = fsub <4 x float> %val1, %val2
+  ret <4 x float> %ret
+}
+
+; Test a v2f64 subtraction.
+define <2 x double> @f6(<2 x double> %dummy, <2 x double> %val1,
+                        <2 x double> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vfsdb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = fsub <2 x double> %val1, %val2
+  ret <2 x double> %ret
+}
+
+; Test an f64 subtraction that uses vector registers.
+define double @f7(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f7:
+; CHECK: wfsdb %f0, %v24, %v26
+; CHECK: br %r14
+  %scalar1 = extractelement <2 x double> %val1, i32 0
+  %scalar2 = extractelement <2 x double> %val2, i32 0
+  %ret = fsub double %scalar1, %scalar2
+  ret double %ret
+}
+
+; Test a v2i8 subtraction, which gets promoted to v16i8.
+define <2 x i8> @f8(<2 x i8> %dummy, <2 x i8> %val1, <2 x i8> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vsb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = sub <2 x i8> %val1, %val2
+  ret <2 x i8> %ret
+}
+
+; Test a v4i8 subtraction, which gets promoted to v16i8.
+define <4 x i8> @f9(<4 x i8> %dummy, <4 x i8> %val1, <4 x i8> %val2) {
+; CHECK-LABEL: f9:
+; CHECK: vsb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = sub <4 x i8> %val1, %val2
+  ret <4 x i8> %ret
+}
+
+; Test a v8i8 subtraction, which gets promoted to v16i8.
+define <8 x i8> @f10(<8 x i8> %dummy, <8 x i8> %val1, <8 x i8> %val2) {
+; CHECK-LABEL: f10:
+; CHECK: vsb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = sub <8 x i8> %val1, %val2
+  ret <8 x i8> %ret
+}
+
+; Test a v2i16 subtraction, which gets promoted to v8i16.
+define <2 x i16> @f11(<2 x i16> %dummy, <2 x i16> %val1, <2 x i16> %val2) {
+; CHECK-LABEL: f11:
+; CHECK: vsh %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = sub <2 x i16> %val1, %val2
+  ret <2 x i16> %ret
+}
+
+; Test a v4i16 subtraction, which gets promoted to v8i16.
+define <4 x i16> @f12(<4 x i16> %dummy, <4 x i16> %val1, <4 x i16> %val2) {
+; CHECK-LABEL: f12:
+; CHECK: vsh %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = sub <4 x i16> %val1, %val2
+  ret <4 x i16> %ret
+}
+
+; Test a v2i32 subtraction, which gets promoted to v4i32.
+define <2 x i32> @f13(<2 x i32> %dummy, <2 x i32> %val1, <2 x i32> %val2) {
+; CHECK-LABEL: f13:
+; CHECK: vsf %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = sub <2 x i32> %val1, %val2
+  ret <2 x i32> %ret
+}
+
+; Test a v2f32 subtraction, which gets promoted to v4f32.
+define <2 x float> @f14(<2 x float> %val1, <2 x float> %val2) {
+; No particular output expected, but must compile.
+  %ret = fsub <2 x float> %val1, %val2
+  ret <2 x float> %ret
+}
diff --git a/test/CodeGen/SystemZ/vec-xor-01.ll b/test/CodeGen/SystemZ/vec-xor-01.ll
new file mode 100644
index 000000000000..063b768117c1
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-xor-01.ll
@@ -0,0 +1,39 @@
+; Test vector XOR.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a v16i8 XOR.
+define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vx %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = xor <16 x i8> %val1, %val2
+  ret <16 x i8> %ret
+}
+
+; Test a v8i16 XOR.
+define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
+; CHECK-LABEL: f2:
+; CHECK: vx %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = xor <8 x i16> %val1, %val2
+  ret <8 x i16> %ret
+}
+
+; Test a v4i32 XOR.
+define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vx %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = xor <4 x i32> %val1, %val2
+  ret <4 x i32> %ret
+}
+
+; Test a v2i64 XOR.
+define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vx %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = xor <2 x i64> %val1, %val2
+  ret <2 x i64> %ret
+}
diff --git a/test/CodeGen/SystemZ/xor-01.ll b/test/CodeGen/SystemZ/xor-01.ll
index 185d6bb0a754..e0aaffbb257e 100644
--- a/test/CodeGen/SystemZ/xor-01.ll
+++ b/test/CodeGen/SystemZ/xor-01.ll
@@ -19,7 +19,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: x %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i32 *%src
+  %b = load i32 , i32 *%src
   %xor = xor i32 %a, %b
   ret i32 %xor
 }
@@ -29,8 +29,8 @@ define i32 @f3(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: x %r2, 4092(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1023
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 1023
+  %b = load i32 , i32 *%ptr
   %xor = xor i32 %a, %b
   ret i32 %xor
 }
@@ -40,8 +40,8 @@ define i32 @f4(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f4:
 ; CHECK: xy %r2, 4096(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 1024
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 1024
+  %b = load i32 , i32 *%ptr
   %xor = xor i32 %a, %b
   ret i32 %xor
 }
@@ -51,8 +51,8 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: xy %r2, 524284(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131071
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %b = load i32 , i32 *%ptr
   %xor = xor i32 %a, %b
   ret i32 %xor
 }
@@ -64,8 +64,8 @@ define i32 @f6(i32 %a, i32 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: x %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %b = load i32 , i32 *%ptr
   %xor = xor i32 %a, %b
   ret i32 %xor
 }
@@ -75,8 +75,8 @@ define i32 @f7(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: xy %r2, -4(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -1
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %b = load i32 , i32 *%ptr
   %xor = xor i32 %a, %b
   ret i32 %xor
 }
@@ -86,8 +86,8 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; CHECK-LABEL: f8:
 ; CHECK: xy %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131072
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %b = load i32 , i32 *%ptr
   %xor = xor i32 %a, %b
   ret i32 %xor
 }
@@ -99,8 +99,8 @@ define i32 @f9(i32 %a, i32 *%src) {
 ; CHECK: agfi %r3, -524292
 ; CHECK: x %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i32 *%src, i64 -131073
-  %b = load i32 *%ptr
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %b = load i32 , i32 *%ptr
   %xor = xor i32 %a, %b
   ret i32 %xor
 }
@@ -113,7 +113,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4092
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %xor = xor i32 %a, %b
   ret i32 %xor
 }
@@ -126,7 +126,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i32 *
-  %b = load i32 *%ptr
+  %b = load i32 , i32 *%ptr
   %xor = xor i32 %a, %b
   ret i32 %xor
 }
@@ -137,26 +137,26 @@ define i32 @f12(i32 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: x %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i32 *%ptr0, i64 2
-  %ptr2 = getelementptr i32 *%ptr0, i64 4
-  %ptr3 = getelementptr i32 *%ptr0, i64 6
-  %ptr4 = getelementptr i32 *%ptr0, i64 8
-  %ptr5 = getelementptr i32 *%ptr0, i64 10
-  %ptr6 = getelementptr i32 *%ptr0, i64 12
-  %ptr7 = getelementptr i32 *%ptr0, i64 14
-  %ptr8 = getelementptr i32 *%ptr0, i64 16
-  %ptr9 = getelementptr i32 *%ptr0, i64 18
-
-  %val0 = load i32 *%ptr0
-  %val1 = load i32 *%ptr1
-  %val2 = load i32 *%ptr2
-  %val3 = load i32 *%ptr3
-  %val4 = load i32 *%ptr4
-  %val5 = load i32 *%ptr5
-  %val6 = load i32 *%ptr6
-  %val7 = load i32 *%ptr7
-  %val8 = load i32 *%ptr8
-  %val9 = load i32 *%ptr9
+  %ptr1 = getelementptr i32, i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32, i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32, i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32, i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32, i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32, i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32, i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32, i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32, i32 *%ptr0, i64 18
+
+  %val0 = load i32 , i32 *%ptr0
+  %val1 = load i32 , i32 *%ptr1
+  %val2 = load i32 , i32 *%ptr2
+  %val3 = load i32 , i32 *%ptr3
+  %val4 = load i32 , i32 *%ptr4
+  %val5 = load i32 , i32 *%ptr5
+  %val6 = load i32 , i32 *%ptr6
+  %val7 = load i32 , i32 *%ptr7
+  %val8 = load i32 , i32 *%ptr8
+  %val9 = load i32 , i32 *%ptr9
 
   %ret = call i32 @foo()
 
diff --git a/test/CodeGen/SystemZ/xor-03.ll b/test/CodeGen/SystemZ/xor-03.ll
index ab7f2584b60d..36fb1df45a84 100644
--- a/test/CodeGen/SystemZ/xor-03.ll
+++ b/test/CodeGen/SystemZ/xor-03.ll
@@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: xg %r2, 0(%r3)
 ; CHECK: br %r14
-  %b = load i64 *%src
+  %b = load i64 , i64 *%src
   %xor = xor i64 %a, %b
   ret i64 %xor
 }
@@ -29,8 +29,8 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f3:
 ; CHECK: xg %r2, 524280(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65535
+  %b = load i64 , i64 *%ptr
   %xor = xor i64 %a, %b
   ret i64 %xor
 }
@@ -42,8 +42,8 @@ define i64 @f4(i64 %a, i64 *%src) {
 ; CHECK: agfi %r3, 524288
 ; CHECK: xg %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 65536
+  %b = load i64 , i64 *%ptr
   %xor = xor i64 %a, %b
   ret i64 %xor
 }
@@ -53,8 +53,8 @@ define i64 @f5(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: xg %r2, -8(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -1
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -1
+  %b = load i64 , i64 *%ptr
   %xor = xor i64 %a, %b
   ret i64 %xor
 }
@@ -64,8 +64,8 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: xg %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65536
+  %b = load i64 , i64 *%ptr
   %xor = xor i64 %a, %b
   ret i64 %xor
 }
@@ -77,8 +77,8 @@ define i64 @f7(i64 %a, i64 *%src) {
 ; CHECK: agfi %r3, -524296
 ; CHECK: xg %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
-  %b = load i64 *%ptr
+  %ptr = getelementptr i64, i64 *%src, i64 -65537
+  %b = load i64 , i64 *%ptr
   %xor = xor i64 %a, %b
   ret i64 %xor
 }
@@ -91,7 +91,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524280
   %ptr = inttoptr i64 %add2 to i64 *
-  %b = load i64 *%ptr
+  %b = load i64 , i64 *%ptr
   %xor = xor i64 %a, %b
   ret i64 %xor
 }
@@ -102,26 +102,26 @@ define i64 @f9(i64 *%ptr0) {
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: xg %r2, 160(%r15)
 ; CHECK: br %r14
-  %ptr1 = getelementptr i64 *%ptr0, i64 2
-  %ptr2 = getelementptr i64 *%ptr0, i64 4
-  %ptr3 = getelementptr i64 *%ptr0, i64 6
-  %ptr4 = getelementptr i64 *%ptr0, i64 8
-  %ptr5 = getelementptr i64 *%ptr0, i64 10
-  %ptr6 = getelementptr i64 *%ptr0, i64 12
-  %ptr7 = getelementptr i64 *%ptr0, i64 14
-  %ptr8 = getelementptr i64 *%ptr0, i64 16
-  %ptr9 = getelementptr i64 *%ptr0, i64 18
+  %ptr1 = getelementptr i64, i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64, i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64, i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64, i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64, i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64, i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64, i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64, i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64, i64 *%ptr0, i64 18
 
-  %val0 = load i64 *%ptr0
-  %val1 = load i64 *%ptr1
-  %val2 = load i64 *%ptr2
-  %val3 = load i64 *%ptr3
-  %val4 = load i64 *%ptr4
-  %val5 = load i64 *%ptr5
-  %val6 = load i64 *%ptr6
-  %val7 = load i64 *%ptr7
-  %val8 = load i64 *%ptr8
-  %val9 = load i64 *%ptr9
+  %val0 = load i64 , i64 *%ptr0
+  %val1 = load i64 , i64 *%ptr1
+  %val2 = load i64 , i64 *%ptr2
+  %val3 = load i64 , i64 *%ptr3
+  %val4 = load i64 , i64 *%ptr4
+  %val5 = load i64 , i64 *%ptr5
+  %val6 = load i64 , i64 *%ptr6
+  %val7 = load i64 , i64 *%ptr7
+  %val8 = load i64 , i64 *%ptr8
+  %val9 = load i64 , i64 *%ptr9
 
   %ret = call i64 @foo()
 
diff --git a/test/CodeGen/SystemZ/xor-05.ll b/test/CodeGen/SystemZ/xor-05.ll
index fbd5660ad058..7b79c7f544d0 100644
--- a/test/CodeGen/SystemZ/xor-05.ll
+++ b/test/CodeGen/SystemZ/xor-05.ll
@@ -7,7 +7,7 @@ define void @f1(i8 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: xi 0(%r2), 1
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %xor = xor i8 %val, -255
   store i8 %xor, i8 *%ptr
   ret void
@@ -18,7 +18,7 @@ define void @f2(i8 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %xor = xor i8 %val, -2
   store i8 %xor, i8 *%ptr
   ret void
@@ -29,7 +29,7 @@ define void @f3(i8 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: xi 0(%r2), 1
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %xor = xor i8 %val, 1
   store i8 %xor, i8 *%ptr
   ret void
@@ -40,7 +40,7 @@ define void @f4(i8 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %xor = xor i8 %val, 254
   store i8 %xor, i8 *%ptr
   ret void
@@ -51,8 +51,8 @@ define void @f5(i8 *%src) {
 ; CHECK-LABEL: f5:
 ; CHECK: xi 4095(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4095
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 4095
+  %val = load i8 , i8 *%ptr
   %xor = xor i8 %val, 127
   store i8 %xor, i8 *%ptr
   ret void
@@ -63,8 +63,8 @@ define void @f6(i8 *%src) {
 ; CHECK-LABEL: f6:
 ; CHECK: xiy 4096(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 4096
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 4096
+  %val = load i8 , i8 *%ptr
   %xor = xor i8 %val, 127
   store i8 %xor, i8 *%ptr
   ret void
@@ -75,8 +75,8 @@ define void @f7(i8 *%src) {
 ; CHECK-LABEL: f7:
 ; CHECK: xiy 524287(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524287
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524287
+  %val = load i8 , i8 *%ptr
   %xor = xor i8 %val, 127
   store i8 %xor, i8 *%ptr
   ret void
@@ -89,8 +89,8 @@ define void @f8(i8 *%src) {
 ; CHECK: agfi %r2, 524288
 ; CHECK: xi 0(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524288
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524288
+  %val = load i8 , i8 *%ptr
   %xor = xor i8 %val, 127
   store i8 %xor, i8 *%ptr
   ret void
@@ -101,8 +101,8 @@ define void @f9(i8 *%src) {
 ; CHECK-LABEL: f9:
 ; CHECK: xiy -1(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -1
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -1
+  %val = load i8 , i8 *%ptr
   %xor = xor i8 %val, 127
   store i8 %xor, i8 *%ptr
   ret void
@@ -113,8 +113,8 @@ define void @f10(i8 *%src) {
 ; CHECK-LABEL: f10:
 ; CHECK: xiy -524288(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524288
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524288
+  %val = load i8 , i8 *%ptr
   %xor = xor i8 %val, 127
   store i8 %xor, i8 *%ptr
   ret void
@@ -127,8 +127,8 @@ define void @f11(i8 *%src) {
 ; CHECK: agfi %r2, -524289
 ; CHECK: xi 0(%r2), 127
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524289
-  %val = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524289
+  %val = load i8 , i8 *%ptr
   %xor = xor i8 %val, 127
   store i8 %xor, i8 *%ptr
   ret void
@@ -143,7 +143,7 @@ define void @f12(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4095
   %ptr = inttoptr i64 %add2 to i8 *
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %xor = xor i8 %val, 127
   store i8 %xor, i8 *%ptr
   ret void
@@ -158,7 +158,7 @@ define void @f13(i64 %src, i64 %index) {
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i8 *
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %xor = xor i8 %val, 127
   store i8 %xor, i8 *%ptr
   ret void
diff --git a/test/CodeGen/SystemZ/xor-06.ll b/test/CodeGen/SystemZ/xor-06.ll
index f39c0fec4e40..40db3cb21a3e 100644
--- a/test/CodeGen/SystemZ/xor-06.ll
+++ b/test/CodeGen/SystemZ/xor-06.ll
@@ -8,7 +8,7 @@ define void @f1(i8 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %xor = xor i32 %ext, -2
   %trunc = trunc i32 %xor to i8
@@ -21,7 +21,7 @@ define void @f2(i8 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %xor = xor i64 %ext, -2
   %trunc = trunc i64 %xor to i8
@@ -34,7 +34,7 @@ define void @f3(i8 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %xor = xor i32 %ext, 254
   %trunc = trunc i32 %xor to i8
@@ -47,7 +47,7 @@ define void @f4(i8 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %xor = xor i64 %ext, 254
   %trunc = trunc i64 %xor to i8
@@ -60,7 +60,7 @@ define void @f5(i8 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %xor = xor i32 %ext, -2
   %trunc = trunc i32 %xor to i8
@@ -73,7 +73,7 @@ define void @f6(i8 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %xor = xor i64 %ext, -2
   %trunc = trunc i64 %xor to i8
@@ -86,7 +86,7 @@ define void @f7(i8 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %xor = xor i32 %ext, 254
   %trunc = trunc i32 %xor to i8
@@ -99,7 +99,7 @@ define void @f8(i8 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
-  %val = load i8 *%ptr
+  %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %xor = xor i64 %ext, 254
   %trunc = trunc i64 %xor to i8
diff --git a/test/CodeGen/SystemZ/xor-08.ll b/test/CodeGen/SystemZ/xor-08.ll
index 8cba41e742ce..9988a4cb45c2 100644
--- a/test/CodeGen/SystemZ/xor-08.ll
+++ b/test/CodeGen/SystemZ/xor-08.ll
@@ -7,9 +7,9 @@ define void @f1(i8 *%ptr1) {
 ; CHECK-LABEL: f1:
 ; CHECK: xc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i8 *%ptr1, i64 1
-  %val = load i8 *%ptr1
-  %old = load i8 *%ptr2
+  %ptr2 = getelementptr i8, i8 *%ptr1, i64 1
+  %val = load i8 , i8 *%ptr1
+  %old = load i8 , i8 *%ptr2
   %xor = xor i8 %val, %old
   store i8 %xor, i8 *%ptr2
   ret void
@@ -20,9 +20,9 @@ define void @f2(i16 *%ptr1) {
 ; CHECK-LABEL: f2:
 ; CHECK: xc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i16 *%ptr1, i64 1
-  %val = load i16 *%ptr1
-  %old = load i16 *%ptr2
+  %ptr2 = getelementptr i16, i16 *%ptr1, i64 1
+  %val = load i16 , i16 *%ptr1
+  %old = load i16 , i16 *%ptr2
   %xor = xor i16 %val, %old
   store i16 %xor, i16 *%ptr2
   ret void
@@ -33,9 +33,9 @@ define void @f3(i32 *%ptr1) {
 ; CHECK-LABEL: f3:
 ; CHECK: xc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i32 *%ptr1, i64 1
-  %val = load i32 *%ptr1
-  %old = load i32 *%ptr2
+  %ptr2 = getelementptr i32, i32 *%ptr1, i64 1
+  %val = load i32 , i32 *%ptr1
+  %old = load i32 , i32 *%ptr2
   %xor = xor i32 %old, %val
   store i32 %xor, i32 *%ptr2
   ret void
@@ -46,9 +46,9 @@ define void @f4(i64 *%ptr1) {
 ; CHECK-LABEL: f4:
 ; CHECK: xc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
-  %ptr2 = getelementptr i64 *%ptr1, i64 1
-  %val = load i64 *%ptr1
-  %old = load i64 *%ptr2
+  %ptr2 = getelementptr i64, i64 *%ptr1, i64 1
+  %val = load i64 , i64 *%ptr1
+  %old = load i64 , i64 *%ptr2
   %xor = xor i64 %old, %val
   store i64 %xor, i64 *%ptr2
   ret void
diff --git a/test/CodeGen/Thumb/2007-01-31-RegInfoAssert.ll b/test/CodeGen/Thumb/2007-01-31-RegInfoAssert.ll
index 1e61b235a2bb..2d2ac9c566a9 100644
--- a/test/CodeGen/Thumb/2007-01-31-RegInfoAssert.ll
+++ b/test/CodeGen/Thumb/2007-01-31-RegInfoAssert.ll
@@ -6,10 +6,10 @@
 define void @f1() {
 	%D = alloca %struct.rtx_def, align 1
 	%tmp1 = bitcast %struct.rtx_def* %D to i32*
-	%tmp7 = load i32* %tmp1
+	%tmp7 = load i32, i32* %tmp1
 	%tmp14 = lshr i32 %tmp7, 1
 	%tmp1415 = and i32 %tmp14, 1
-	call void (i32, ...)* @printf( i32 undef, i32 0, i32 %tmp1415 )
+	call void (i32, ...) @printf( i32 undef, i32 0, i32 %tmp1415 )
 	ret void
 }
 
diff --git a/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll b/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll
index 929c472d1ef6..079ab879afbf 100644
--- a/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll
+++ b/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll
@@ -9,7 +9,7 @@ target triple = "thumb-unknown-linux-gnueabi"
 
 define i8* @f(i8* %a) {
 entry:
-	%tmp1 = load i32* @i.1882		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* @i.1882		; <i32> [#uses=1]
 	%tmp2 = add i32 %tmp1, 1		; <i32> [#uses=2]
 	store i32 %tmp2, i32* @i.1882
 	%tmp34 = inttoptr i32 %tmp2 to i8*		; <i8*> [#uses=1]
@@ -21,16 +21,16 @@ entry:
 	%t = alloca i32, align 4		; <i32*> [#uses=4]
 	%ret = alloca i32, align 4		; <i32*> [#uses=3]
 	%tmp1 = call i32 @pthread_create( i32* %t, %struct.pthread_attr_t* null, i8* (i8*)* @f, i8* null )		; <i32> [#uses=0]
-	%tmp2 = load i32* %t		; <i32> [#uses=1]
+	%tmp2 = load i32, i32* %t		; <i32> [#uses=1]
 	%ret3 = bitcast i32* %ret to i8**		; <i8**> [#uses=2]
 	%tmp4 = call i32 @pthread_join( i32 %tmp2, i8** %ret3 )		; <i32> [#uses=0]
-	%tmp5 = load i32* %ret		; <i32> [#uses=1]
-	%tmp7 = call i32 (i8*, ...)* @printf( i8* getelementptr ([14 x i8]* @.str, i32 0, i32 0), i32 %tmp5 )		; <i32> [#uses=0]
+	%tmp5 = load i32, i32* %ret		; <i32> [#uses=1]
+	%tmp7 = call i32 (i8*, ...) @printf( i8* getelementptr ([14 x i8], [14 x i8]* @.str, i32 0, i32 0), i32 %tmp5 )		; <i32> [#uses=0]
 	%tmp8 = call i32 @pthread_create( i32* %t, %struct.pthread_attr_t* null, i8* (i8*)* @f, i8* null )		; <i32> [#uses=0]
-	%tmp9 = load i32* %t		; <i32> [#uses=1]
+	%tmp9 = load i32, i32* %t		; <i32> [#uses=1]
 	%tmp11 = call i32 @pthread_join( i32 %tmp9, i8** %ret3 )		; <i32> [#uses=0]
-	%tmp12 = load i32* %ret		; <i32> [#uses=1]
-	%tmp14 = call i32 (i8*, ...)* @printf( i8* getelementptr ([14 x i8]* @.str1, i32 0, i32 0), i32 %tmp12 )		; <i32> [#uses=0]
+	%tmp12 = load i32, i32* %ret		; <i32> [#uses=1]
+	%tmp14 = call i32 (i8*, ...) @printf( i8* getelementptr ([14 x i8], [14 x i8]* @.str1, i32 0, i32 0), i32 %tmp12 )		; <i32> [#uses=0]
 	ret i32 0
 }
 
diff --git a/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll b/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll
index d4651a1f3fa7..fd300322f23f 100644
--- a/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll
+++ b/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll
@@ -4,7 +4,7 @@
 
 define i64 @millisecs() nounwind {
 entry:
-	%0 = load i64* @Time.2535, align 4		; <i64> [#uses=2]
+	%0 = load i64, i64* @Time.2535, align 4		; <i64> [#uses=2]
 	%1 = add i64 %0, 1		; <i64> [#uses=1]
 	store i64 %1, i64* @Time.2535, align 4
 	ret i64 %0
diff --git a/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll b/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll
index 5b420fc74503..7036dd19b4bc 100644
--- a/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll
+++ b/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll
@@ -4,697 +4,697 @@
 
 define void @BF_encrypt(i32* nocapture %data, %struct.BF_KEY* nocapture %key, i32 %encrypt) nounwind {
 entry:
-	%0 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 0; <i32*> [#uses=2]
-	%1 = load i32* %data, align 4             ; <i32> [#uses=2]
-	%2 = load i32* undef, align 4             ; <i32> [#uses=2]
+	%0 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 0; <i32*> [#uses=2]
+	%1 = load i32, i32* %data, align 4             ; <i32> [#uses=2]
+	%2 = load i32, i32* undef, align 4             ; <i32> [#uses=2]
 	br i1 undef, label %bb1, label %bb
 
 bb:                                               ; preds = %entry
-	%3 = load i32* %0, align 4                ; <i32> [#uses=1]
+	%3 = load i32, i32* %0, align 4                ; <i32> [#uses=1]
 	%4 = xor i32 %3, %1                       ; <i32> [#uses=4]
-	%5 = load i32* null, align 4              ; <i32> [#uses=1]
+	%5 = load i32, i32* null, align 4              ; <i32> [#uses=1]
 	%6 = lshr i32 %4, 24                      ; <i32> [#uses=1]
-	%7 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %6; <i32*> [#uses=1]
-	%8 = load i32* %7, align 4                ; <i32> [#uses=1]
+	%7 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %6; <i32*> [#uses=1]
+	%8 = load i32, i32* %7, align 4                ; <i32> [#uses=1]
 	%9 = lshr i32 %4, 16                      ; <i32> [#uses=1]
 	%10 = or i32 %9, 256                      ; <i32> [#uses=1]
 	%11 = and i32 %10, 511                    ; <i32> [#uses=1]
-	%12 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %11; <i32*> [#uses=1]
-	%13 = load i32* %12, align 4              ; <i32> [#uses=1]
+	%12 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %11; <i32*> [#uses=1]
+	%13 = load i32, i32* %12, align 4              ; <i32> [#uses=1]
 	%14 = add i32 %13, %8                     ; <i32> [#uses=1]
-	%15 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 undef; <i32*> [#uses=1]
-	%16 = load i32* %15, align 4              ; <i32> [#uses=1]
+	%15 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 undef; <i32*> [#uses=1]
+	%16 = load i32, i32* %15, align 4              ; <i32> [#uses=1]
 	%17 = xor i32 %14, %16                    ; <i32> [#uses=1]
 	%18 = or i32 %4, 768                      ; <i32> [#uses=1]
 	%19 = and i32 %18, 1023                   ; <i32> [#uses=1]
-	%20 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %19; <i32*> [#uses=1]
-	%21 = load i32* %20, align 4              ; <i32> [#uses=1]
+	%20 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %19; <i32*> [#uses=1]
+	%21 = load i32, i32* %20, align 4              ; <i32> [#uses=1]
 	%22 = add i32 %17, %21                    ; <i32> [#uses=1]
 	%23 = xor i32 %5, %2                      ; <i32> [#uses=1]
 	%24 = xor i32 %23, %22                    ; <i32> [#uses=5]
-	%25 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 2; <i32*> [#uses=1]
-	%26 = load i32* %25, align 4              ; <i32> [#uses=1]
+	%25 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 2; <i32*> [#uses=1]
+	%26 = load i32, i32* %25, align 4              ; <i32> [#uses=1]
 	%27 = lshr i32 %24, 24                    ; <i32> [#uses=1]
-	%28 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %27; <i32*> [#uses=1]
-	%29 = load i32* %28, align 4              ; <i32> [#uses=1]
+	%28 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %27; <i32*> [#uses=1]
+	%29 = load i32, i32* %28, align 4              ; <i32> [#uses=1]
 	%30 = lshr i32 %24, 16                    ; <i32> [#uses=1]
 	%31 = or i32 %30, 256                     ; <i32> [#uses=1]
 	%32 = and i32 %31, 511                    ; <i32> [#uses=1]
-	%33 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %32; <i32*> [#uses=1]
-	%34 = load i32* %33, align 4              ; <i32> [#uses=1]
+	%33 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %32; <i32*> [#uses=1]
+	%34 = load i32, i32* %33, align 4              ; <i32> [#uses=1]
 	%35 = add i32 %34, %29                    ; <i32> [#uses=1]
 	%36 = lshr i32 %24, 8                     ; <i32> [#uses=1]
 	%37 = or i32 %36, 512                     ; <i32> [#uses=1]
 	%38 = and i32 %37, 767                    ; <i32> [#uses=1]
-	%39 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %38; <i32*> [#uses=1]
-	%40 = load i32* %39, align 4              ; <i32> [#uses=1]
+	%39 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %38; <i32*> [#uses=1]
+	%40 = load i32, i32* %39, align 4              ; <i32> [#uses=1]
 	%41 = xor i32 %35, %40                    ; <i32> [#uses=1]
 	%42 = or i32 %24, 768                     ; <i32> [#uses=1]
 	%43 = and i32 %42, 1023                   ; <i32> [#uses=1]
-	%44 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %43; <i32*> [#uses=1]
-	%45 = load i32* %44, align 4              ; <i32> [#uses=1]
+	%44 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %43; <i32*> [#uses=1]
+	%45 = load i32, i32* %44, align 4              ; <i32> [#uses=1]
 	%46 = add i32 %41, %45                    ; <i32> [#uses=1]
 	%47 = xor i32 %26, %4                     ; <i32> [#uses=1]
 	%48 = xor i32 %47, %46                    ; <i32> [#uses=5]
-	%49 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 3; <i32*> [#uses=1]
-	%50 = load i32* %49, align 4              ; <i32> [#uses=1]
+	%49 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 3; <i32*> [#uses=1]
+	%50 = load i32, i32* %49, align 4              ; <i32> [#uses=1]
 	%51 = lshr i32 %48, 24                    ; <i32> [#uses=1]
-	%52 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %51; <i32*> [#uses=1]
-	%53 = load i32* %52, align 4              ; <i32> [#uses=1]
+	%52 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %51; <i32*> [#uses=1]
+	%53 = load i32, i32* %52, align 4              ; <i32> [#uses=1]
 	%54 = lshr i32 %48, 16                    ; <i32> [#uses=1]
 	%55 = or i32 %54, 256                     ; <i32> [#uses=1]
 	%56 = and i32 %55, 511                    ; <i32> [#uses=1]
-	%57 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %56; <i32*> [#uses=1]
-	%58 = load i32* %57, align 4              ; <i32> [#uses=1]
+	%57 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %56; <i32*> [#uses=1]
+	%58 = load i32, i32* %57, align 4              ; <i32> [#uses=1]
 	%59 = add i32 %58, %53                    ; <i32> [#uses=1]
 	%60 = lshr i32 %48, 8                     ; <i32> [#uses=1]
 	%61 = or i32 %60, 512                     ; <i32> [#uses=1]
 	%62 = and i32 %61, 767                    ; <i32> [#uses=1]
-	%63 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %62; <i32*> [#uses=1]
-	%64 = load i32* %63, align 4              ; <i32> [#uses=1]
+	%63 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %62; <i32*> [#uses=1]
+	%64 = load i32, i32* %63, align 4              ; <i32> [#uses=1]
 	%65 = xor i32 %59, %64                    ; <i32> [#uses=1]
 	%66 = or i32 %48, 768                     ; <i32> [#uses=1]
 	%67 = and i32 %66, 1023                   ; <i32> [#uses=1]
-	%68 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %67; <i32*> [#uses=1]
-	%69 = load i32* %68, align 4              ; <i32> [#uses=1]
+	%68 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %67; <i32*> [#uses=1]
+	%69 = load i32, i32* %68, align 4              ; <i32> [#uses=1]
 	%70 = add i32 %65, %69                    ; <i32> [#uses=1]
 	%71 = xor i32 %50, %24                    ; <i32> [#uses=1]
 	%72 = xor i32 %71, %70                    ; <i32> [#uses=5]
-	%73 = load i32* null, align 4             ; <i32> [#uses=1]
+	%73 = load i32, i32* null, align 4             ; <i32> [#uses=1]
 	%74 = lshr i32 %72, 24                    ; <i32> [#uses=1]
-	%75 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %74; <i32*> [#uses=1]
-	%76 = load i32* %75, align 4              ; <i32> [#uses=1]
+	%75 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %74; <i32*> [#uses=1]
+	%76 = load i32, i32* %75, align 4              ; <i32> [#uses=1]
 	%77 = lshr i32 %72, 16                    ; <i32> [#uses=1]
 	%78 = or i32 %77, 256                     ; <i32> [#uses=1]
 	%79 = and i32 %78, 511                    ; <i32> [#uses=1]
-	%80 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %79; <i32*> [#uses=1]
-	%81 = load i32* %80, align 4              ; <i32> [#uses=1]
+	%80 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %79; <i32*> [#uses=1]
+	%81 = load i32, i32* %80, align 4              ; <i32> [#uses=1]
 	%82 = add i32 %81, %76                    ; <i32> [#uses=1]
 	%83 = lshr i32 %72, 8                     ; <i32> [#uses=1]
 	%84 = or i32 %83, 512                     ; <i32> [#uses=1]
 	%85 = and i32 %84, 767                    ; <i32> [#uses=1]
-	%86 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %85; <i32*> [#uses=1]
-	%87 = load i32* %86, align 4              ; <i32> [#uses=1]
+	%86 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %85; <i32*> [#uses=1]
+	%87 = load i32, i32* %86, align 4              ; <i32> [#uses=1]
 	%88 = xor i32 %82, %87                    ; <i32> [#uses=1]
 	%89 = or i32 %72, 768                     ; <i32> [#uses=1]
 	%90 = and i32 %89, 1023                   ; <i32> [#uses=1]
-	%91 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %90; <i32*> [#uses=1]
-	%92 = load i32* %91, align 4              ; <i32> [#uses=1]
+	%91 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %90; <i32*> [#uses=1]
+	%92 = load i32, i32* %91, align 4              ; <i32> [#uses=1]
 	%93 = add i32 %88, %92                    ; <i32> [#uses=1]
 	%94 = xor i32 %73, %48                    ; <i32> [#uses=1]
 	%95 = xor i32 %94, %93                    ; <i32> [#uses=5]
-	%96 = load i32* undef, align 4            ; <i32> [#uses=1]
+	%96 = load i32, i32* undef, align 4            ; <i32> [#uses=1]
 	%97 = lshr i32 %95, 24                    ; <i32> [#uses=1]
-	%98 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %97; <i32*> [#uses=1]
-	%99 = load i32* %98, align 4              ; <i32> [#uses=1]
+	%98 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %97; <i32*> [#uses=1]
+	%99 = load i32, i32* %98, align 4              ; <i32> [#uses=1]
 	%100 = lshr i32 %95, 16                   ; <i32> [#uses=1]
 	%101 = or i32 %100, 256                   ; <i32> [#uses=1]
 	%102 = and i32 %101, 511                  ; <i32> [#uses=1]
-	%103 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %102; <i32*> [#uses=1]
-	%104 = load i32* %103, align 4            ; <i32> [#uses=1]
+	%103 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %102; <i32*> [#uses=1]
+	%104 = load i32, i32* %103, align 4            ; <i32> [#uses=1]
 	%105 = add i32 %104, %99                  ; <i32> [#uses=1]
 	%106 = lshr i32 %95, 8                    ; <i32> [#uses=1]
 	%107 = or i32 %106, 512                   ; <i32> [#uses=1]
 	%108 = and i32 %107, 767                  ; <i32> [#uses=1]
-	%109 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %108; <i32*> [#uses=1]
-	%110 = load i32* %109, align 4            ; <i32> [#uses=1]
+	%109 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %108; <i32*> [#uses=1]
+	%110 = load i32, i32* %109, align 4            ; <i32> [#uses=1]
 	%111 = xor i32 %105, %110                 ; <i32> [#uses=1]
 	%112 = or i32 %95, 768                    ; <i32> [#uses=1]
 	%113 = and i32 %112, 1023                 ; <i32> [#uses=1]
-	%114 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %113; <i32*> [#uses=1]
-	%115 = load i32* %114, align 4            ; <i32> [#uses=1]
+	%114 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %113; <i32*> [#uses=1]
+	%115 = load i32, i32* %114, align 4            ; <i32> [#uses=1]
 	%116 = add i32 %111, %115                 ; <i32> [#uses=1]
 	%117 = xor i32 %96, %72                   ; <i32> [#uses=1]
 	%118 = xor i32 %117, %116                 ; <i32> [#uses=5]
-	%119 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 6; <i32*> [#uses=1]
-	%120 = load i32* %119, align 4            ; <i32> [#uses=1]
+	%119 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 6; <i32*> [#uses=1]
+	%120 = load i32, i32* %119, align 4            ; <i32> [#uses=1]
 	%121 = lshr i32 %118, 24                  ; <i32> [#uses=1]
-	%122 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %121; <i32*> [#uses=1]
-	%123 = load i32* %122, align 4            ; <i32> [#uses=1]
+	%122 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %121; <i32*> [#uses=1]
+	%123 = load i32, i32* %122, align 4            ; <i32> [#uses=1]
 	%124 = lshr i32 %118, 16                  ; <i32> [#uses=1]
 	%125 = or i32 %124, 256                   ; <i32> [#uses=1]
 	%126 = and i32 %125, 511                  ; <i32> [#uses=1]
-	%127 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %126; <i32*> [#uses=1]
-	%128 = load i32* %127, align 4            ; <i32> [#uses=1]
+	%127 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %126; <i32*> [#uses=1]
+	%128 = load i32, i32* %127, align 4            ; <i32> [#uses=1]
 	%129 = add i32 %128, %123                 ; <i32> [#uses=1]
 	%130 = lshr i32 %118, 8                   ; <i32> [#uses=1]
 	%131 = or i32 %130, 512                   ; <i32> [#uses=1]
 	%132 = and i32 %131, 767                  ; <i32> [#uses=1]
-	%133 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %132; <i32*> [#uses=1]
-	%134 = load i32* %133, align 4            ; <i32> [#uses=1]
+	%133 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %132; <i32*> [#uses=1]
+	%134 = load i32, i32* %133, align 4            ; <i32> [#uses=1]
 	%135 = xor i32 %129, %134                 ; <i32> [#uses=1]
 	%136 = or i32 %118, 768                   ; <i32> [#uses=1]
 	%137 = and i32 %136, 1023                 ; <i32> [#uses=1]
-	%138 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %137; <i32*> [#uses=1]
-	%139 = load i32* %138, align 4            ; <i32> [#uses=1]
+	%138 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %137; <i32*> [#uses=1]
+	%139 = load i32, i32* %138, align 4            ; <i32> [#uses=1]
 	%140 = add i32 %135, %139                 ; <i32> [#uses=1]
 	%141 = xor i32 %120, %95                  ; <i32> [#uses=1]
 	%142 = xor i32 %141, %140                 ; <i32> [#uses=5]
-	%143 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 7; <i32*> [#uses=1]
-	%144 = load i32* %143, align 4            ; <i32> [#uses=1]
+	%143 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 7; <i32*> [#uses=1]
+	%144 = load i32, i32* %143, align 4            ; <i32> [#uses=1]
 	%145 = lshr i32 %142, 24                  ; <i32> [#uses=1]
-	%146 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %145; <i32*> [#uses=1]
-	%147 = load i32* %146, align 4            ; <i32> [#uses=1]
+	%146 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %145; <i32*> [#uses=1]
+	%147 = load i32, i32* %146, align 4            ; <i32> [#uses=1]
 	%148 = lshr i32 %142, 16                  ; <i32> [#uses=1]
 	%149 = or i32 %148, 256                   ; <i32> [#uses=1]
 	%150 = and i32 %149, 511                  ; <i32> [#uses=1]
-	%151 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %150; <i32*> [#uses=1]
-	%152 = load i32* %151, align 4            ; <i32> [#uses=1]
+	%151 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %150; <i32*> [#uses=1]
+	%152 = load i32, i32* %151, align 4            ; <i32> [#uses=1]
 	%153 = add i32 %152, %147                 ; <i32> [#uses=1]
 	%154 = lshr i32 %142, 8                   ; <i32> [#uses=1]
 	%155 = or i32 %154, 512                   ; <i32> [#uses=1]
 	%156 = and i32 %155, 767                  ; <i32> [#uses=1]
-	%157 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %156; <i32*> [#uses=1]
-	%158 = load i32* %157, align 4            ; <i32> [#uses=1]
+	%157 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %156; <i32*> [#uses=1]
+	%158 = load i32, i32* %157, align 4            ; <i32> [#uses=1]
 	%159 = xor i32 %153, %158                 ; <i32> [#uses=1]
 	%160 = or i32 %142, 768                   ; <i32> [#uses=1]
 	%161 = and i32 %160, 1023                 ; <i32> [#uses=1]
-	%162 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %161; <i32*> [#uses=1]
-	%163 = load i32* %162, align 4            ; <i32> [#uses=1]
+	%162 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %161; <i32*> [#uses=1]
+	%163 = load i32, i32* %162, align 4            ; <i32> [#uses=1]
 	%164 = add i32 %159, %163                 ; <i32> [#uses=1]
 	%165 = xor i32 %144, %118                 ; <i32> [#uses=1]
 	%166 = xor i32 %165, %164                 ; <i32> [#uses=5]
-	%167 = load i32* undef, align 4           ; <i32> [#uses=1]
+	%167 = load i32, i32* undef, align 4           ; <i32> [#uses=1]
 	%168 = lshr i32 %166, 24                  ; <i32> [#uses=1]
-	%169 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %168; <i32*> [#uses=1]
-	%170 = load i32* %169, align 4            ; <i32> [#uses=1]
+	%169 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %168; <i32*> [#uses=1]
+	%170 = load i32, i32* %169, align 4            ; <i32> [#uses=1]
 	%171 = lshr i32 %166, 16                  ; <i32> [#uses=1]
 	%172 = or i32 %171, 256                   ; <i32> [#uses=1]
 	%173 = and i32 %172, 511                  ; <i32> [#uses=1]
-	%174 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %173; <i32*> [#uses=1]
-	%175 = load i32* %174, align 4            ; <i32> [#uses=1]
+	%174 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %173; <i32*> [#uses=1]
+	%175 = load i32, i32* %174, align 4            ; <i32> [#uses=1]
 	%176 = add i32 %175, %170                 ; <i32> [#uses=1]
 	%177 = lshr i32 %166, 8                   ; <i32> [#uses=1]
 	%178 = or i32 %177, 512                   ; <i32> [#uses=1]
 	%179 = and i32 %178, 767                  ; <i32> [#uses=1]
-	%180 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %179; <i32*> [#uses=1]
-	%181 = load i32* %180, align 4            ; <i32> [#uses=1]
+	%180 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %179; <i32*> [#uses=1]
+	%181 = load i32, i32* %180, align 4            ; <i32> [#uses=1]
 	%182 = xor i32 %176, %181                 ; <i32> [#uses=1]
 	%183 = or i32 %166, 768                   ; <i32> [#uses=1]
 	%184 = and i32 %183, 1023                 ; <i32> [#uses=1]
-	%185 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %184; <i32*> [#uses=1]
-	%186 = load i32* %185, align 4            ; <i32> [#uses=1]
+	%185 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %184; <i32*> [#uses=1]
+	%186 = load i32, i32* %185, align 4            ; <i32> [#uses=1]
 	%187 = add i32 %182, %186                 ; <i32> [#uses=1]
 	%188 = xor i32 %167, %142                 ; <i32> [#uses=1]
 	%189 = xor i32 %188, %187                 ; <i32> [#uses=5]
-	%190 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 9; <i32*> [#uses=1]
-	%191 = load i32* %190, align 4            ; <i32> [#uses=1]
+	%190 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 9; <i32*> [#uses=1]
+	%191 = load i32, i32* %190, align 4            ; <i32> [#uses=1]
 	%192 = lshr i32 %189, 24                  ; <i32> [#uses=1]
-	%193 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %192; <i32*> [#uses=1]
-	%194 = load i32* %193, align 4            ; <i32> [#uses=1]
+	%193 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %192; <i32*> [#uses=1]
+	%194 = load i32, i32* %193, align 4            ; <i32> [#uses=1]
 	%195 = lshr i32 %189, 16                  ; <i32> [#uses=1]
 	%196 = or i32 %195, 256                   ; <i32> [#uses=1]
 	%197 = and i32 %196, 511                  ; <i32> [#uses=1]
-	%198 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %197; <i32*> [#uses=1]
-	%199 = load i32* %198, align 4            ; <i32> [#uses=1]
+	%198 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %197; <i32*> [#uses=1]
+	%199 = load i32, i32* %198, align 4            ; <i32> [#uses=1]
 	%200 = add i32 %199, %194                 ; <i32> [#uses=1]
 	%201 = lshr i32 %189, 8                   ; <i32> [#uses=1]
 	%202 = or i32 %201, 512                   ; <i32> [#uses=1]
 	%203 = and i32 %202, 767                  ; <i32> [#uses=1]
-	%204 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %203; <i32*> [#uses=1]
-	%205 = load i32* %204, align 4            ; <i32> [#uses=1]
+	%204 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %203; <i32*> [#uses=1]
+	%205 = load i32, i32* %204, align 4            ; <i32> [#uses=1]
 	%206 = xor i32 %200, %205                 ; <i32> [#uses=1]
 	%207 = or i32 %189, 768                   ; <i32> [#uses=1]
 	%208 = and i32 %207, 1023                 ; <i32> [#uses=1]
-	%209 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %208; <i32*> [#uses=1]
-	%210 = load i32* %209, align 4            ; <i32> [#uses=1]
+	%209 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %208; <i32*> [#uses=1]
+	%210 = load i32, i32* %209, align 4            ; <i32> [#uses=1]
 	%211 = add i32 %206, %210                 ; <i32> [#uses=1]
 	%212 = xor i32 %191, %166                 ; <i32> [#uses=1]
 	%213 = xor i32 %212, %211                 ; <i32> [#uses=5]
-	%214 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 10; <i32*> [#uses=1]
-	%215 = load i32* %214, align 4            ; <i32> [#uses=1]
+	%214 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 10; <i32*> [#uses=1]
+	%215 = load i32, i32* %214, align 4            ; <i32> [#uses=1]
 	%216 = lshr i32 %213, 24                  ; <i32> [#uses=1]
-	%217 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %216; <i32*> [#uses=1]
-	%218 = load i32* %217, align 4            ; <i32> [#uses=1]
+	%217 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %216; <i32*> [#uses=1]
+	%218 = load i32, i32* %217, align 4            ; <i32> [#uses=1]
 	%219 = lshr i32 %213, 16                  ; <i32> [#uses=1]
 	%220 = or i32 %219, 256                   ; <i32> [#uses=1]
 	%221 = and i32 %220, 511                  ; <i32> [#uses=1]
-	%222 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %221; <i32*> [#uses=1]
-	%223 = load i32* %222, align 4            ; <i32> [#uses=1]
+	%222 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %221; <i32*> [#uses=1]
+	%223 = load i32, i32* %222, align 4            ; <i32> [#uses=1]
 	%224 = add i32 %223, %218                 ; <i32> [#uses=1]
 	%225 = lshr i32 %213, 8                   ; <i32> [#uses=1]
 	%226 = or i32 %225, 512                   ; <i32> [#uses=1]
 	%227 = and i32 %226, 767                  ; <i32> [#uses=1]
-	%228 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %227; <i32*> [#uses=1]
-	%229 = load i32* %228, align 4            ; <i32> [#uses=1]
+	%228 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %227; <i32*> [#uses=1]
+	%229 = load i32, i32* %228, align 4            ; <i32> [#uses=1]
 	%230 = xor i32 %224, %229                 ; <i32> [#uses=1]
 	%231 = or i32 %213, 768                   ; <i32> [#uses=1]
 	%232 = and i32 %231, 1023                 ; <i32> [#uses=1]
-	%233 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %232; <i32*> [#uses=1]
-	%234 = load i32* %233, align 4            ; <i32> [#uses=1]
+	%233 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %232; <i32*> [#uses=1]
+	%234 = load i32, i32* %233, align 4            ; <i32> [#uses=1]
 	%235 = add i32 %230, %234                 ; <i32> [#uses=1]
 	%236 = xor i32 %215, %189                 ; <i32> [#uses=1]
 	%237 = xor i32 %236, %235                 ; <i32> [#uses=5]
-	%238 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 11; <i32*> [#uses=1]
-	%239 = load i32* %238, align 4            ; <i32> [#uses=1]
+	%238 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 11; <i32*> [#uses=1]
+	%239 = load i32, i32* %238, align 4            ; <i32> [#uses=1]
 	%240 = lshr i32 %237, 24                  ; <i32> [#uses=1]
-	%241 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %240; <i32*> [#uses=1]
-	%242 = load i32* %241, align 4            ; <i32> [#uses=1]
+	%241 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %240; <i32*> [#uses=1]
+	%242 = load i32, i32* %241, align 4            ; <i32> [#uses=1]
 	%243 = lshr i32 %237, 16                  ; <i32> [#uses=1]
 	%244 = or i32 %243, 256                   ; <i32> [#uses=1]
 	%245 = and i32 %244, 511                  ; <i32> [#uses=1]
-	%246 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %245; <i32*> [#uses=1]
-	%247 = load i32* %246, align 4            ; <i32> [#uses=1]
+	%246 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %245; <i32*> [#uses=1]
+	%247 = load i32, i32* %246, align 4            ; <i32> [#uses=1]
 	%248 = add i32 %247, %242                 ; <i32> [#uses=1]
 	%249 = lshr i32 %237, 8                   ; <i32> [#uses=1]
 	%250 = or i32 %249, 512                   ; <i32> [#uses=1]
 	%251 = and i32 %250, 767                  ; <i32> [#uses=1]
-	%252 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %251; <i32*> [#uses=1]
-	%253 = load i32* %252, align 4            ; <i32> [#uses=1]
+	%252 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %251; <i32*> [#uses=1]
+	%253 = load i32, i32* %252, align 4            ; <i32> [#uses=1]
 	%254 = xor i32 %248, %253                 ; <i32> [#uses=1]
 	%255 = or i32 %237, 768                   ; <i32> [#uses=1]
 	%256 = and i32 %255, 1023                 ; <i32> [#uses=1]
-	%257 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %256; <i32*> [#uses=1]
-	%258 = load i32* %257, align 4            ; <i32> [#uses=1]
+	%257 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %256; <i32*> [#uses=1]
+	%258 = load i32, i32* %257, align 4            ; <i32> [#uses=1]
 	%259 = add i32 %254, %258                 ; <i32> [#uses=1]
 	%260 = xor i32 %239, %213                 ; <i32> [#uses=1]
 	%261 = xor i32 %260, %259                 ; <i32> [#uses=5]
-	%262 = load i32* undef, align 4           ; <i32> [#uses=1]
+	%262 = load i32, i32* undef, align 4           ; <i32> [#uses=1]
 	%263 = lshr i32 %261, 24                  ; <i32> [#uses=1]
-	%264 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %263; <i32*> [#uses=1]
-	%265 = load i32* %264, align 4            ; <i32> [#uses=1]
+	%264 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %263; <i32*> [#uses=1]
+	%265 = load i32, i32* %264, align 4            ; <i32> [#uses=1]
 	%266 = lshr i32 %261, 16                  ; <i32> [#uses=1]
 	%267 = or i32 %266, 256                   ; <i32> [#uses=1]
 	%268 = and i32 %267, 511                  ; <i32> [#uses=1]
-	%269 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %268; <i32*> [#uses=1]
-	%270 = load i32* %269, align 4            ; <i32> [#uses=1]
+	%269 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %268; <i32*> [#uses=1]
+	%270 = load i32, i32* %269, align 4            ; <i32> [#uses=1]
 	%271 = add i32 %270, %265                 ; <i32> [#uses=1]
 	%272 = lshr i32 %261, 8                   ; <i32> [#uses=1]
 	%273 = or i32 %272, 512                   ; <i32> [#uses=1]
 	%274 = and i32 %273, 767                  ; <i32> [#uses=1]
-	%275 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %274; <i32*> [#uses=1]
-	%276 = load i32* %275, align 4            ; <i32> [#uses=1]
+	%275 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %274; <i32*> [#uses=1]
+	%276 = load i32, i32* %275, align 4            ; <i32> [#uses=1]
 	%277 = xor i32 %271, %276                 ; <i32> [#uses=1]
 	%278 = or i32 %261, 768                   ; <i32> [#uses=1]
 	%279 = and i32 %278, 1023                 ; <i32> [#uses=1]
-	%280 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %279; <i32*> [#uses=1]
-	%281 = load i32* %280, align 4            ; <i32> [#uses=1]
+	%280 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %279; <i32*> [#uses=1]
+	%281 = load i32, i32* %280, align 4            ; <i32> [#uses=1]
 	%282 = add i32 %277, %281                 ; <i32> [#uses=1]
 	%283 = xor i32 %262, %237                 ; <i32> [#uses=1]
 	%284 = xor i32 %283, %282                 ; <i32> [#uses=4]
-	%285 = load i32* null, align 4            ; <i32> [#uses=1]
+	%285 = load i32, i32* null, align 4            ; <i32> [#uses=1]
 	%286 = lshr i32 %284, 24                  ; <i32> [#uses=1]
-	%287 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %286; <i32*> [#uses=1]
-	%288 = load i32* %287, align 4            ; <i32> [#uses=1]
+	%287 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %286; <i32*> [#uses=1]
+	%288 = load i32, i32* %287, align 4            ; <i32> [#uses=1]
 	%289 = lshr i32 %284, 16                  ; <i32> [#uses=1]
 	%290 = or i32 %289, 256                   ; <i32> [#uses=1]
 	%291 = and i32 %290, 511                  ; <i32> [#uses=1]
-	%292 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %291; <i32*> [#uses=1]
-	%293 = load i32* %292, align 4            ; <i32> [#uses=1]
+	%292 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %291; <i32*> [#uses=1]
+	%293 = load i32, i32* %292, align 4            ; <i32> [#uses=1]
 	%294 = add i32 %293, %288                 ; <i32> [#uses=1]
 	%295 = lshr i32 %284, 8                   ; <i32> [#uses=1]
 	%296 = or i32 %295, 512                   ; <i32> [#uses=1]
 	%297 = and i32 %296, 767                  ; <i32> [#uses=1]
-	%298 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %297; <i32*> [#uses=1]
-	%299 = load i32* %298, align 4            ; <i32> [#uses=1]
+	%298 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %297; <i32*> [#uses=1]
+	%299 = load i32, i32* %298, align 4            ; <i32> [#uses=1]
 	%300 = xor i32 %294, %299                 ; <i32> [#uses=1]
 	%301 = or i32 %284, 768                   ; <i32> [#uses=1]
 	%302 = and i32 %301, 1023                 ; <i32> [#uses=1]
-	%303 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %302; <i32*> [#uses=1]
-	%304 = load i32* %303, align 4            ; <i32> [#uses=1]
+	%303 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %302; <i32*> [#uses=1]
+	%304 = load i32, i32* %303, align 4            ; <i32> [#uses=1]
 	%305 = add i32 %300, %304                 ; <i32> [#uses=1]
 	%306 = xor i32 %285, %261                 ; <i32> [#uses=1]
 	%307 = xor i32 %306, %305                 ; <i32> [#uses=1]
-	%308 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 15; <i32*> [#uses=1]
-	%309 = load i32* %308, align 4            ; <i32> [#uses=1]
-	%310 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 0; <i32*> [#uses=1]
-	%311 = load i32* %310, align 4            ; <i32> [#uses=1]
+	%308 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 15; <i32*> [#uses=1]
+	%309 = load i32, i32* %308, align 4            ; <i32> [#uses=1]
+	%310 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 0; <i32*> [#uses=1]
+	%311 = load i32, i32* %310, align 4            ; <i32> [#uses=1]
 	%312 = or i32 0, 256                      ; <i32> [#uses=1]
 	%313 = and i32 %312, 511                  ; <i32> [#uses=1]
-	%314 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %313; <i32*> [#uses=1]
-	%315 = load i32* %314, align 4            ; <i32> [#uses=1]
+	%314 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %313; <i32*> [#uses=1]
+	%315 = load i32, i32* %314, align 4            ; <i32> [#uses=1]
 	%316 = add i32 %315, %311                 ; <i32> [#uses=1]
 	%317 = or i32 0, 512                      ; <i32> [#uses=1]
 	%318 = and i32 %317, 767                  ; <i32> [#uses=1]
-	%319 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %318; <i32*> [#uses=1]
-	%320 = load i32* %319, align 4            ; <i32> [#uses=1]
+	%319 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %318; <i32*> [#uses=1]
+	%320 = load i32, i32* %319, align 4            ; <i32> [#uses=1]
 	%321 = xor i32 %316, %320                 ; <i32> [#uses=1]
 	%322 = or i32 0, 768                      ; <i32> [#uses=1]
 	%323 = and i32 %322, 1023                 ; <i32> [#uses=1]
-	%324 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %323; <i32*> [#uses=1]
-	%325 = load i32* %324, align 4            ; <i32> [#uses=1]
+	%324 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %323; <i32*> [#uses=1]
+	%325 = load i32, i32* %324, align 4            ; <i32> [#uses=1]
 	%326 = add i32 %321, %325                 ; <i32> [#uses=1]
 	%327 = xor i32 %309, %307                 ; <i32> [#uses=1]
 	%328 = xor i32 %327, %326                 ; <i32> [#uses=5]
-	%329 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 17; <i32*> [#uses=1]
+	%329 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 17; <i32*> [#uses=1]
 	br label %bb2
 
 bb1:                                              ; preds = %entry
-	%330 = load i32* null, align 4            ; <i32> [#uses=1]
+	%330 = load i32, i32* null, align 4            ; <i32> [#uses=1]
 	%331 = xor i32 %330, %1                   ; <i32> [#uses=4]
-	%332 = load i32* null, align 4            ; <i32> [#uses=1]
+	%332 = load i32, i32* null, align 4            ; <i32> [#uses=1]
 	%333 = lshr i32 %331, 24                  ; <i32> [#uses=1]
-	%334 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %333; <i32*> [#uses=1]
-	%335 = load i32* %334, align 4            ; <i32> [#uses=1]
-	%336 = load i32* null, align 4            ; <i32> [#uses=1]
+	%334 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %333; <i32*> [#uses=1]
+	%335 = load i32, i32* %334, align 4            ; <i32> [#uses=1]
+	%336 = load i32, i32* null, align 4            ; <i32> [#uses=1]
 	%337 = add i32 %336, %335                 ; <i32> [#uses=1]
 	%338 = lshr i32 %331, 8                   ; <i32> [#uses=1]
 	%339 = or i32 %338, 512                   ; <i32> [#uses=1]
 	%340 = and i32 %339, 767                  ; <i32> [#uses=1]
-	%341 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %340; <i32*> [#uses=1]
-	%342 = load i32* %341, align 4            ; <i32> [#uses=1]
+	%341 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %340; <i32*> [#uses=1]
+	%342 = load i32, i32* %341, align 4            ; <i32> [#uses=1]
 	%343 = xor i32 %337, %342                 ; <i32> [#uses=1]
 	%344 = or i32 %331, 768                   ; <i32> [#uses=1]
 	%345 = and i32 %344, 1023                 ; <i32> [#uses=1]
-	%346 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %345; <i32*> [#uses=1]
-	%347 = load i32* %346, align 4            ; <i32> [#uses=1]
+	%346 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %345; <i32*> [#uses=1]
+	%347 = load i32, i32* %346, align 4            ; <i32> [#uses=1]
 	%348 = add i32 %343, %347                 ; <i32> [#uses=1]
 	%349 = xor i32 %332, %2                   ; <i32> [#uses=1]
 	%350 = xor i32 %349, %348                 ; <i32> [#uses=5]
-	%351 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 15; <i32*> [#uses=1]
-	%352 = load i32* %351, align 4            ; <i32> [#uses=1]
+	%351 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 15; <i32*> [#uses=1]
+	%352 = load i32, i32* %351, align 4            ; <i32> [#uses=1]
 	%353 = lshr i32 %350, 24                  ; <i32> [#uses=1]
-	%354 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %353; <i32*> [#uses=1]
-	%355 = load i32* %354, align 4            ; <i32> [#uses=1]
+	%354 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %353; <i32*> [#uses=1]
+	%355 = load i32, i32* %354, align 4            ; <i32> [#uses=1]
 	%356 = lshr i32 %350, 16                  ; <i32> [#uses=1]
 	%357 = or i32 %356, 256                   ; <i32> [#uses=1]
 	%358 = and i32 %357, 511                  ; <i32> [#uses=1]
-	%359 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %358; <i32*> [#uses=1]
-	%360 = load i32* %359, align 4            ; <i32> [#uses=1]
+	%359 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %358; <i32*> [#uses=1]
+	%360 = load i32, i32* %359, align 4            ; <i32> [#uses=1]
 	%361 = add i32 %360, %355                 ; <i32> [#uses=1]
 	%362 = lshr i32 %350, 8                   ; <i32> [#uses=1]
 	%363 = or i32 %362, 512                   ; <i32> [#uses=1]
 	%364 = and i32 %363, 767                  ; <i32> [#uses=1]
-	%365 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %364; <i32*> [#uses=1]
-	%366 = load i32* %365, align 4            ; <i32> [#uses=1]
+	%365 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %364; <i32*> [#uses=1]
+	%366 = load i32, i32* %365, align 4            ; <i32> [#uses=1]
 	%367 = xor i32 %361, %366                 ; <i32> [#uses=1]
 	%368 = or i32 %350, 768                   ; <i32> [#uses=1]
 	%369 = and i32 %368, 1023                 ; <i32> [#uses=1]
-	%370 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %369; <i32*> [#uses=1]
-	%371 = load i32* %370, align 4            ; <i32> [#uses=1]
+	%370 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %369; <i32*> [#uses=1]
+	%371 = load i32, i32* %370, align 4            ; <i32> [#uses=1]
 	%372 = add i32 %367, %371                 ; <i32> [#uses=1]
 	%373 = xor i32 %352, %331                 ; <i32> [#uses=1]
 	%374 = xor i32 %373, %372                 ; <i32> [#uses=5]
-	%375 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 14; <i32*> [#uses=1]
-	%376 = load i32* %375, align 4            ; <i32> [#uses=1]
+	%375 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 14; <i32*> [#uses=1]
+	%376 = load i32, i32* %375, align 4            ; <i32> [#uses=1]
 	%377 = lshr i32 %374, 24                  ; <i32> [#uses=1]
-	%378 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %377; <i32*> [#uses=1]
-	%379 = load i32* %378, align 4            ; <i32> [#uses=1]
+	%378 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %377; <i32*> [#uses=1]
+	%379 = load i32, i32* %378, align 4            ; <i32> [#uses=1]
 	%380 = lshr i32 %374, 16                  ; <i32> [#uses=1]
 	%381 = or i32 %380, 256                   ; <i32> [#uses=1]
 	%382 = and i32 %381, 511                  ; <i32> [#uses=1]
-	%383 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %382; <i32*> [#uses=1]
-	%384 = load i32* %383, align 4            ; <i32> [#uses=1]
+	%383 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %382; <i32*> [#uses=1]
+	%384 = load i32, i32* %383, align 4            ; <i32> [#uses=1]
 	%385 = add i32 %384, %379                 ; <i32> [#uses=1]
 	%386 = lshr i32 %374, 8                   ; <i32> [#uses=1]
 	%387 = or i32 %386, 512                   ; <i32> [#uses=1]
 	%388 = and i32 %387, 767                  ; <i32> [#uses=1]
-	%389 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %388; <i32*> [#uses=1]
-	%390 = load i32* %389, align 4            ; <i32> [#uses=1]
+	%389 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %388; <i32*> [#uses=1]
+	%390 = load i32, i32* %389, align 4            ; <i32> [#uses=1]
 	%391 = xor i32 %385, %390                 ; <i32> [#uses=1]
 	%392 = or i32 %374, 768                   ; <i32> [#uses=1]
 	%393 = and i32 %392, 1023                 ; <i32> [#uses=1]
-	%394 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %393; <i32*> [#uses=1]
-	%395 = load i32* %394, align 4            ; <i32> [#uses=1]
+	%394 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %393; <i32*> [#uses=1]
+	%395 = load i32, i32* %394, align 4            ; <i32> [#uses=1]
 	%396 = add i32 %391, %395                 ; <i32> [#uses=1]
 	%397 = xor i32 %376, %350                 ; <i32> [#uses=1]
 	%398 = xor i32 %397, %396                 ; <i32> [#uses=5]
-	%399 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 13; <i32*> [#uses=1]
-	%400 = load i32* %399, align 4            ; <i32> [#uses=1]
+	%399 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 13; <i32*> [#uses=1]
+	%400 = load i32, i32* %399, align 4            ; <i32> [#uses=1]
 	%401 = lshr i32 %398, 24                  ; <i32> [#uses=1]
-	%402 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %401; <i32*> [#uses=1]
-	%403 = load i32* %402, align 4            ; <i32> [#uses=1]
+	%402 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %401; <i32*> [#uses=1]
+	%403 = load i32, i32* %402, align 4            ; <i32> [#uses=1]
 	%404 = lshr i32 %398, 16                  ; <i32> [#uses=1]
 	%405 = or i32 %404, 256                   ; <i32> [#uses=1]
 	%406 = and i32 %405, 511                  ; <i32> [#uses=1]
-	%407 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %406; <i32*> [#uses=1]
-	%408 = load i32* %407, align 4            ; <i32> [#uses=1]
+	%407 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %406; <i32*> [#uses=1]
+	%408 = load i32, i32* %407, align 4            ; <i32> [#uses=1]
 	%409 = add i32 %408, %403                 ; <i32> [#uses=1]
 	%410 = lshr i32 %398, 8                   ; <i32> [#uses=1]
 	%411 = or i32 %410, 512                   ; <i32> [#uses=1]
 	%412 = and i32 %411, 767                  ; <i32> [#uses=1]
-	%413 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %412; <i32*> [#uses=1]
-	%414 = load i32* %413, align 4            ; <i32> [#uses=1]
+	%413 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %412; <i32*> [#uses=1]
+	%414 = load i32, i32* %413, align 4            ; <i32> [#uses=1]
 	%415 = xor i32 %409, %414                 ; <i32> [#uses=1]
 	%416 = or i32 %398, 768                   ; <i32> [#uses=1]
 	%417 = and i32 %416, 1023                 ; <i32> [#uses=1]
-	%418 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %417; <i32*> [#uses=1]
-	%419 = load i32* %418, align 4            ; <i32> [#uses=1]
+	%418 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %417; <i32*> [#uses=1]
+	%419 = load i32, i32* %418, align 4            ; <i32> [#uses=1]
 	%420 = add i32 %415, %419                 ; <i32> [#uses=1]
 	%421 = xor i32 %400, %374                 ; <i32> [#uses=1]
 	%422 = xor i32 %421, %420                 ; <i32> [#uses=5]
-	%423 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 12; <i32*> [#uses=1]
-	%424 = load i32* %423, align 4            ; <i32> [#uses=1]
+	%423 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 12; <i32*> [#uses=1]
+	%424 = load i32, i32* %423, align 4            ; <i32> [#uses=1]
 	%425 = lshr i32 %422, 24                  ; <i32> [#uses=1]
-	%426 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %425; <i32*> [#uses=1]
-	%427 = load i32* %426, align 4            ; <i32> [#uses=1]
+	%426 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %425; <i32*> [#uses=1]
+	%427 = load i32, i32* %426, align 4            ; <i32> [#uses=1]
 	%428 = lshr i32 %422, 16                  ; <i32> [#uses=1]
 	%429 = or i32 %428, 256                   ; <i32> [#uses=1]
 	%430 = and i32 %429, 511                  ; <i32> [#uses=1]
-	%431 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %430; <i32*> [#uses=1]
-	%432 = load i32* %431, align 4            ; <i32> [#uses=1]
+	%431 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %430; <i32*> [#uses=1]
+	%432 = load i32, i32* %431, align 4            ; <i32> [#uses=1]
 	%433 = add i32 %432, %427                 ; <i32> [#uses=1]
 	%434 = lshr i32 %422, 8                   ; <i32> [#uses=1]
 	%435 = or i32 %434, 512                   ; <i32> [#uses=1]
 	%436 = and i32 %435, 767                  ; <i32> [#uses=1]
-	%437 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %436; <i32*> [#uses=1]
-	%438 = load i32* %437, align 4            ; <i32> [#uses=1]
+	%437 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %436; <i32*> [#uses=1]
+	%438 = load i32, i32* %437, align 4            ; <i32> [#uses=1]
 	%439 = xor i32 %433, %438                 ; <i32> [#uses=1]
 	%440 = or i32 %422, 768                   ; <i32> [#uses=1]
 	%441 = and i32 %440, 1023                 ; <i32> [#uses=1]
-	%442 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %441; <i32*> [#uses=1]
-	%443 = load i32* %442, align 4            ; <i32> [#uses=1]
+	%442 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %441; <i32*> [#uses=1]
+	%443 = load i32, i32* %442, align 4            ; <i32> [#uses=1]
 	%444 = add i32 %439, %443                 ; <i32> [#uses=1]
 	%445 = xor i32 %424, %398                 ; <i32> [#uses=1]
 	%446 = xor i32 %445, %444                 ; <i32> [#uses=5]
-	%447 = load i32* undef, align 4           ; <i32> [#uses=1]
+	%447 = load i32, i32* undef, align 4           ; <i32> [#uses=1]
 	%448 = lshr i32 %446, 24                  ; <i32> [#uses=1]
-	%449 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %448; <i32*> [#uses=1]
-	%450 = load i32* %449, align 4            ; <i32> [#uses=1]
+	%449 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %448; <i32*> [#uses=1]
+	%450 = load i32, i32* %449, align 4            ; <i32> [#uses=1]
 	%451 = lshr i32 %446, 16                  ; <i32> [#uses=1]
 	%452 = or i32 %451, 256                   ; <i32> [#uses=1]
 	%453 = and i32 %452, 511                  ; <i32> [#uses=1]
-	%454 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %453; <i32*> [#uses=1]
-	%455 = load i32* %454, align 4            ; <i32> [#uses=1]
+	%454 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %453; <i32*> [#uses=1]
+	%455 = load i32, i32* %454, align 4            ; <i32> [#uses=1]
 	%456 = add i32 %455, %450                 ; <i32> [#uses=1]
 	%457 = lshr i32 %446, 8                   ; <i32> [#uses=1]
 	%458 = or i32 %457, 512                   ; <i32> [#uses=1]
 	%459 = and i32 %458, 767                  ; <i32> [#uses=1]
-	%460 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %459; <i32*> [#uses=1]
-	%461 = load i32* %460, align 4            ; <i32> [#uses=1]
+	%460 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %459; <i32*> [#uses=1]
+	%461 = load i32, i32* %460, align 4            ; <i32> [#uses=1]
 	%462 = xor i32 %456, %461                 ; <i32> [#uses=1]
 	%463 = or i32 %446, 768                   ; <i32> [#uses=1]
 	%464 = and i32 %463, 1023                 ; <i32> [#uses=1]
-	%465 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %464; <i32*> [#uses=1]
-	%466 = load i32* %465, align 4            ; <i32> [#uses=1]
+	%465 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %464; <i32*> [#uses=1]
+	%466 = load i32, i32* %465, align 4            ; <i32> [#uses=1]
 	%467 = add i32 %462, %466                 ; <i32> [#uses=1]
 	%468 = xor i32 %447, %422                 ; <i32> [#uses=1]
 	%469 = xor i32 %468, %467                 ; <i32> [#uses=5]
-	%470 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 10; <i32*> [#uses=1]
-	%471 = load i32* %470, align 4            ; <i32> [#uses=1]
+	%470 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 10; <i32*> [#uses=1]
+	%471 = load i32, i32* %470, align 4            ; <i32> [#uses=1]
 	%472 = lshr i32 %469, 24                  ; <i32> [#uses=1]
-	%473 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %472; <i32*> [#uses=1]
-	%474 = load i32* %473, align 4            ; <i32> [#uses=1]
+	%473 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %472; <i32*> [#uses=1]
+	%474 = load i32, i32* %473, align 4            ; <i32> [#uses=1]
 	%475 = lshr i32 %469, 16                  ; <i32> [#uses=1]
 	%476 = or i32 %475, 256                   ; <i32> [#uses=1]
 	%477 = and i32 %476, 511                  ; <i32> [#uses=1]
-	%478 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %477; <i32*> [#uses=1]
-	%479 = load i32* %478, align 4            ; <i32> [#uses=1]
+	%478 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %477; <i32*> [#uses=1]
+	%479 = load i32, i32* %478, align 4            ; <i32> [#uses=1]
 	%480 = add i32 %479, %474                 ; <i32> [#uses=1]
 	%481 = lshr i32 %469, 8                   ; <i32> [#uses=1]
 	%482 = or i32 %481, 512                   ; <i32> [#uses=1]
 	%483 = and i32 %482, 767                  ; <i32> [#uses=1]
-	%484 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %483; <i32*> [#uses=1]
-	%485 = load i32* %484, align 4            ; <i32> [#uses=1]
+	%484 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %483; <i32*> [#uses=1]
+	%485 = load i32, i32* %484, align 4            ; <i32> [#uses=1]
 	%486 = xor i32 %480, %485                 ; <i32> [#uses=1]
 	%487 = or i32 %469, 768                   ; <i32> [#uses=1]
 	%488 = and i32 %487, 1023                 ; <i32> [#uses=1]
-	%489 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %488; <i32*> [#uses=1]
-	%490 = load i32* %489, align 4            ; <i32> [#uses=1]
+	%489 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %488; <i32*> [#uses=1]
+	%490 = load i32, i32* %489, align 4            ; <i32> [#uses=1]
 	%491 = add i32 %486, %490                 ; <i32> [#uses=1]
 	%492 = xor i32 %471, %446                 ; <i32> [#uses=1]
 	%493 = xor i32 %492, %491                 ; <i32> [#uses=5]
-	%494 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 9; <i32*> [#uses=1]
-	%495 = load i32* %494, align 4            ; <i32> [#uses=1]
+	%494 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 9; <i32*> [#uses=1]
+	%495 = load i32, i32* %494, align 4            ; <i32> [#uses=1]
 	%496 = lshr i32 %493, 24                  ; <i32> [#uses=1]
-	%497 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %496; <i32*> [#uses=1]
-	%498 = load i32* %497, align 4            ; <i32> [#uses=1]
+	%497 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %496; <i32*> [#uses=1]
+	%498 = load i32, i32* %497, align 4            ; <i32> [#uses=1]
 	%499 = lshr i32 %493, 16                  ; <i32> [#uses=1]
 	%500 = or i32 %499, 256                   ; <i32> [#uses=1]
 	%501 = and i32 %500, 511                  ; <i32> [#uses=1]
-	%502 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %501; <i32*> [#uses=1]
-	%503 = load i32* %502, align 4            ; <i32> [#uses=1]
+	%502 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %501; <i32*> [#uses=1]
+	%503 = load i32, i32* %502, align 4            ; <i32> [#uses=1]
 	%504 = add i32 %503, %498                 ; <i32> [#uses=1]
 	%505 = lshr i32 %493, 8                   ; <i32> [#uses=1]
 	%506 = or i32 %505, 512                   ; <i32> [#uses=1]
 	%507 = and i32 %506, 767                  ; <i32> [#uses=1]
-	%508 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %507; <i32*> [#uses=1]
-	%509 = load i32* %508, align 4            ; <i32> [#uses=1]
+	%508 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %507; <i32*> [#uses=1]
+	%509 = load i32, i32* %508, align 4            ; <i32> [#uses=1]
 	%510 = xor i32 %504, %509                 ; <i32> [#uses=1]
 	%511 = or i32 %493, 768                   ; <i32> [#uses=1]
 	%512 = and i32 %511, 1023                 ; <i32> [#uses=1]
-	%513 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %512; <i32*> [#uses=1]
-	%514 = load i32* %513, align 4            ; <i32> [#uses=1]
+	%513 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %512; <i32*> [#uses=1]
+	%514 = load i32, i32* %513, align 4            ; <i32> [#uses=1]
 	%515 = add i32 %510, %514                 ; <i32> [#uses=1]
 	%516 = xor i32 %495, %469                 ; <i32> [#uses=1]
 	%517 = xor i32 %516, %515                 ; <i32> [#uses=5]
-	%518 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 8; <i32*> [#uses=1]
-	%519 = load i32* %518, align 4            ; <i32> [#uses=1]
+	%518 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 8; <i32*> [#uses=1]
+	%519 = load i32, i32* %518, align 4            ; <i32> [#uses=1]
 	%520 = lshr i32 %517, 24                  ; <i32> [#uses=1]
-	%521 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %520; <i32*> [#uses=1]
-	%522 = load i32* %521, align 4            ; <i32> [#uses=1]
+	%521 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %520; <i32*> [#uses=1]
+	%522 = load i32, i32* %521, align 4            ; <i32> [#uses=1]
 	%523 = lshr i32 %517, 16                  ; <i32> [#uses=1]
 	%524 = or i32 %523, 256                   ; <i32> [#uses=1]
 	%525 = and i32 %524, 511                  ; <i32> [#uses=1]
-	%526 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %525; <i32*> [#uses=1]
-	%527 = load i32* %526, align 4            ; <i32> [#uses=1]
+	%526 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %525; <i32*> [#uses=1]
+	%527 = load i32, i32* %526, align 4            ; <i32> [#uses=1]
 	%528 = add i32 %527, %522                 ; <i32> [#uses=1]
 	%529 = lshr i32 %517, 8                   ; <i32> [#uses=1]
 	%530 = or i32 %529, 512                   ; <i32> [#uses=1]
 	%531 = and i32 %530, 767                  ; <i32> [#uses=1]
-	%532 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %531; <i32*> [#uses=1]
-	%533 = load i32* %532, align 4            ; <i32> [#uses=1]
+	%532 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %531; <i32*> [#uses=1]
+	%533 = load i32, i32* %532, align 4            ; <i32> [#uses=1]
 	%534 = xor i32 %528, %533                 ; <i32> [#uses=1]
 	%535 = or i32 %517, 768                   ; <i32> [#uses=1]
 	%536 = and i32 %535, 1023                 ; <i32> [#uses=1]
-	%537 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %536; <i32*> [#uses=1]
-	%538 = load i32* %537, align 4            ; <i32> [#uses=1]
+	%537 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %536; <i32*> [#uses=1]
+	%538 = load i32, i32* %537, align 4            ; <i32> [#uses=1]
 	%539 = add i32 %534, %538                 ; <i32> [#uses=1]
 	%540 = xor i32 %519, %493                 ; <i32> [#uses=1]
 	%541 = xor i32 %540, %539                 ; <i32> [#uses=5]
-	%542 = load i32* undef, align 4           ; <i32> [#uses=1]
+	%542 = load i32, i32* undef, align 4           ; <i32> [#uses=1]
 	%543 = lshr i32 %541, 24                  ; <i32> [#uses=1]
-	%544 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %543; <i32*> [#uses=1]
-	%545 = load i32* %544, align 4            ; <i32> [#uses=1]
+	%544 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %543; <i32*> [#uses=1]
+	%545 = load i32, i32* %544, align 4            ; <i32> [#uses=1]
 	%546 = lshr i32 %541, 16                  ; <i32> [#uses=1]
 	%547 = or i32 %546, 256                   ; <i32> [#uses=1]
 	%548 = and i32 %547, 511                  ; <i32> [#uses=1]
-	%549 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %548; <i32*> [#uses=1]
-	%550 = load i32* %549, align 4            ; <i32> [#uses=1]
+	%549 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %548; <i32*> [#uses=1]
+	%550 = load i32, i32* %549, align 4            ; <i32> [#uses=1]
 	%551 = add i32 %550, %545                 ; <i32> [#uses=1]
 	%552 = lshr i32 %541, 8                   ; <i32> [#uses=1]
 	%553 = or i32 %552, 512                   ; <i32> [#uses=1]
 	%554 = and i32 %553, 767                  ; <i32> [#uses=1]
-	%555 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %554; <i32*> [#uses=1]
-	%556 = load i32* %555, align 4            ; <i32> [#uses=1]
+	%555 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %554; <i32*> [#uses=1]
+	%556 = load i32, i32* %555, align 4            ; <i32> [#uses=1]
 	%557 = xor i32 %551, %556                 ; <i32> [#uses=1]
 	%558 = or i32 %541, 768                   ; <i32> [#uses=1]
 	%559 = and i32 %558, 1023                 ; <i32> [#uses=1]
-	%560 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %559; <i32*> [#uses=1]
-	%561 = load i32* %560, align 4            ; <i32> [#uses=1]
+	%560 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %559; <i32*> [#uses=1]
+	%561 = load i32, i32* %560, align 4            ; <i32> [#uses=1]
 	%562 = add i32 %557, %561                 ; <i32> [#uses=1]
 	%563 = xor i32 %542, %517                 ; <i32> [#uses=1]
 	%564 = xor i32 %563, %562                 ; <i32> [#uses=5]
-	%565 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 6; <i32*> [#uses=1]
-	%566 = load i32* %565, align 4            ; <i32> [#uses=1]
+	%565 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 6; <i32*> [#uses=1]
+	%566 = load i32, i32* %565, align 4            ; <i32> [#uses=1]
 	%567 = lshr i32 %564, 24                  ; <i32> [#uses=1]
-	%568 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %567; <i32*> [#uses=1]
-	%569 = load i32* %568, align 4            ; <i32> [#uses=1]
+	%568 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %567; <i32*> [#uses=1]
+	%569 = load i32, i32* %568, align 4            ; <i32> [#uses=1]
 	%570 = lshr i32 %564, 16                  ; <i32> [#uses=1]
 	%571 = or i32 %570, 256                   ; <i32> [#uses=1]
 	%572 = and i32 %571, 511                  ; <i32> [#uses=1]
-	%573 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %572; <i32*> [#uses=1]
-	%574 = load i32* %573, align 4            ; <i32> [#uses=1]
+	%573 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %572; <i32*> [#uses=1]
+	%574 = load i32, i32* %573, align 4            ; <i32> [#uses=1]
 	%575 = add i32 %574, %569                 ; <i32> [#uses=1]
 	%576 = lshr i32 %564, 8                   ; <i32> [#uses=1]
 	%577 = or i32 %576, 512                   ; <i32> [#uses=1]
 	%578 = and i32 %577, 767                  ; <i32> [#uses=1]
-	%579 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %578; <i32*> [#uses=1]
-	%580 = load i32* %579, align 4            ; <i32> [#uses=1]
+	%579 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %578; <i32*> [#uses=1]
+	%580 = load i32, i32* %579, align 4            ; <i32> [#uses=1]
 	%581 = xor i32 %575, %580                 ; <i32> [#uses=1]
 	%582 = or i32 %564, 768                   ; <i32> [#uses=1]
 	%583 = and i32 %582, 1023                 ; <i32> [#uses=1]
-	%584 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %583; <i32*> [#uses=1]
-	%585 = load i32* %584, align 4            ; <i32> [#uses=1]
+	%584 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %583; <i32*> [#uses=1]
+	%585 = load i32, i32* %584, align 4            ; <i32> [#uses=1]
 	%586 = add i32 %581, %585                 ; <i32> [#uses=1]
 	%587 = xor i32 %566, %541                 ; <i32> [#uses=1]
 	%588 = xor i32 %587, %586                 ; <i32> [#uses=5]
-	%589 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 5; <i32*> [#uses=1]
-	%590 = load i32* %589, align 4            ; <i32> [#uses=1]
+	%589 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 5; <i32*> [#uses=1]
+	%590 = load i32, i32* %589, align 4            ; <i32> [#uses=1]
 	%591 = lshr i32 %588, 24                  ; <i32> [#uses=1]
-	%592 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %591; <i32*> [#uses=1]
-	%593 = load i32* %592, align 4            ; <i32> [#uses=1]
+	%592 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %591; <i32*> [#uses=1]
+	%593 = load i32, i32* %592, align 4            ; <i32> [#uses=1]
 	%594 = lshr i32 %588, 16                  ; <i32> [#uses=1]
 	%595 = or i32 %594, 256                   ; <i32> [#uses=1]
 	%596 = and i32 %595, 511                  ; <i32> [#uses=1]
-	%597 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %596; <i32*> [#uses=1]
-	%598 = load i32* %597, align 4            ; <i32> [#uses=1]
+	%597 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %596; <i32*> [#uses=1]
+	%598 = load i32, i32* %597, align 4            ; <i32> [#uses=1]
 	%599 = add i32 %598, %593                 ; <i32> [#uses=1]
 	%600 = lshr i32 %588, 8                   ; <i32> [#uses=1]
 	%601 = or i32 %600, 512                   ; <i32> [#uses=1]
 	%602 = and i32 %601, 767                  ; <i32> [#uses=1]
-	%603 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %602; <i32*> [#uses=1]
-	%604 = load i32* %603, align 4            ; <i32> [#uses=1]
+	%603 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %602; <i32*> [#uses=1]
+	%604 = load i32, i32* %603, align 4            ; <i32> [#uses=1]
 	%605 = xor i32 %599, %604                 ; <i32> [#uses=1]
 	%606 = or i32 %588, 768                   ; <i32> [#uses=1]
 	%607 = and i32 %606, 1023                 ; <i32> [#uses=1]
-	%608 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %607; <i32*> [#uses=1]
-	%609 = load i32* %608, align 4            ; <i32> [#uses=1]
+	%608 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %607; <i32*> [#uses=1]
+	%609 = load i32, i32* %608, align 4            ; <i32> [#uses=1]
 	%610 = add i32 %605, %609                 ; <i32> [#uses=1]
 	%611 = xor i32 %590, %564                 ; <i32> [#uses=1]
 	%612 = xor i32 %611, %610                 ; <i32> [#uses=5]
-	%613 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 4; <i32*> [#uses=1]
-	%614 = load i32* %613, align 4            ; <i32> [#uses=1]
+	%613 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 4; <i32*> [#uses=1]
+	%614 = load i32, i32* %613, align 4            ; <i32> [#uses=1]
 	%615 = lshr i32 %612, 24                  ; <i32> [#uses=1]
-	%616 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %615; <i32*> [#uses=1]
-	%617 = load i32* %616, align 4            ; <i32> [#uses=1]
+	%616 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %615; <i32*> [#uses=1]
+	%617 = load i32, i32* %616, align 4            ; <i32> [#uses=1]
 	%618 = lshr i32 %612, 16                  ; <i32> [#uses=1]
 	%619 = or i32 %618, 256                   ; <i32> [#uses=1]
 	%620 = and i32 %619, 511                  ; <i32> [#uses=1]
-	%621 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %620; <i32*> [#uses=1]
-	%622 = load i32* %621, align 4            ; <i32> [#uses=1]
+	%621 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %620; <i32*> [#uses=1]
+	%622 = load i32, i32* %621, align 4            ; <i32> [#uses=1]
 	%623 = add i32 %622, %617                 ; <i32> [#uses=1]
 	%624 = lshr i32 %612, 8                   ; <i32> [#uses=1]
 	%625 = or i32 %624, 512                   ; <i32> [#uses=1]
 	%626 = and i32 %625, 767                  ; <i32> [#uses=1]
-	%627 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %626; <i32*> [#uses=1]
-	%628 = load i32* %627, align 4            ; <i32> [#uses=1]
+	%627 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %626; <i32*> [#uses=1]
+	%628 = load i32, i32* %627, align 4            ; <i32> [#uses=1]
 	%629 = xor i32 %623, %628                 ; <i32> [#uses=1]
 	%630 = or i32 %612, 768                   ; <i32> [#uses=1]
 	%631 = and i32 %630, 1023                 ; <i32> [#uses=1]
-	%632 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %631; <i32*> [#uses=1]
-	%633 = load i32* %632, align 4            ; <i32> [#uses=1]
+	%632 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %631; <i32*> [#uses=1]
+	%633 = load i32, i32* %632, align 4            ; <i32> [#uses=1]
 	%634 = add i32 %629, %633                 ; <i32> [#uses=1]
 	%635 = xor i32 %614, %588                 ; <i32> [#uses=1]
 	%636 = xor i32 %635, %634                 ; <i32> [#uses=5]
-	%637 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 3; <i32*> [#uses=1]
-	%638 = load i32* %637, align 4            ; <i32> [#uses=1]
+	%637 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 3; <i32*> [#uses=1]
+	%638 = load i32, i32* %637, align 4            ; <i32> [#uses=1]
 	%639 = lshr i32 %636, 24                  ; <i32> [#uses=1]
-	%640 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %639; <i32*> [#uses=1]
-	%641 = load i32* %640, align 4            ; <i32> [#uses=1]
+	%640 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %639; <i32*> [#uses=1]
+	%641 = load i32, i32* %640, align 4            ; <i32> [#uses=1]
 	%642 = lshr i32 %636, 16                  ; <i32> [#uses=1]
 	%643 = or i32 %642, 256                   ; <i32> [#uses=1]
 	%644 = and i32 %643, 511                  ; <i32> [#uses=1]
-	%645 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %644; <i32*> [#uses=1]
-	%646 = load i32* %645, align 4            ; <i32> [#uses=1]
+	%645 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %644; <i32*> [#uses=1]
+	%646 = load i32, i32* %645, align 4            ; <i32> [#uses=1]
 	%647 = add i32 %646, %641                 ; <i32> [#uses=1]
 	%648 = lshr i32 %636, 8                   ; <i32> [#uses=1]
 	%649 = or i32 %648, 512                   ; <i32> [#uses=1]
 	%650 = and i32 %649, 767                  ; <i32> [#uses=1]
-	%651 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %650; <i32*> [#uses=1]
-	%652 = load i32* %651, align 4            ; <i32> [#uses=1]
+	%651 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %650; <i32*> [#uses=1]
+	%652 = load i32, i32* %651, align 4            ; <i32> [#uses=1]
 	%653 = xor i32 %647, %652                 ; <i32> [#uses=1]
 	%654 = or i32 %636, 768                   ; <i32> [#uses=1]
 	%655 = and i32 %654, 1023                 ; <i32> [#uses=1]
-	%656 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %655; <i32*> [#uses=1]
-	%657 = load i32* %656, align 4            ; <i32> [#uses=1]
+	%656 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %655; <i32*> [#uses=1]
+	%657 = load i32, i32* %656, align 4            ; <i32> [#uses=1]
 	%658 = add i32 %653, %657                 ; <i32> [#uses=1]
 	%659 = xor i32 %638, %612                 ; <i32> [#uses=1]
 	%660 = xor i32 %659, %658                 ; <i32> [#uses=5]
-	%661 = load i32* undef, align 4           ; <i32> [#uses=1]
+	%661 = load i32, i32* undef, align 4           ; <i32> [#uses=1]
 	%662 = lshr i32 %660, 24                  ; <i32> [#uses=1]
-	%663 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %662; <i32*> [#uses=1]
-	%664 = load i32* %663, align 4            ; <i32> [#uses=1]
+	%663 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %662; <i32*> [#uses=1]
+	%664 = load i32, i32* %663, align 4            ; <i32> [#uses=1]
 	%665 = lshr i32 %660, 16                  ; <i32> [#uses=1]
 	%666 = or i32 %665, 256                   ; <i32> [#uses=1]
 	%667 = and i32 %666, 511                  ; <i32> [#uses=1]
-	%668 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %667; <i32*> [#uses=1]
-	%669 = load i32* %668, align 4            ; <i32> [#uses=1]
+	%668 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %667; <i32*> [#uses=1]
+	%669 = load i32, i32* %668, align 4            ; <i32> [#uses=1]
 	%670 = add i32 %669, %664                 ; <i32> [#uses=1]
 	%671 = lshr i32 %660, 8                   ; <i32> [#uses=1]
 	%672 = or i32 %671, 512                   ; <i32> [#uses=1]
 	%673 = and i32 %672, 767                  ; <i32> [#uses=1]
-	%674 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %673; <i32*> [#uses=1]
-	%675 = load i32* %674, align 4            ; <i32> [#uses=1]
+	%674 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %673; <i32*> [#uses=1]
+	%675 = load i32, i32* %674, align 4            ; <i32> [#uses=1]
 	%676 = xor i32 %670, %675                 ; <i32> [#uses=1]
 	%677 = or i32 %660, 768                   ; <i32> [#uses=1]
 	%678 = and i32 %677, 1023                 ; <i32> [#uses=1]
-	%679 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %678; <i32*> [#uses=1]
-	%680 = load i32* %679, align 4            ; <i32> [#uses=1]
+	%679 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %678; <i32*> [#uses=1]
+	%680 = load i32, i32* %679, align 4            ; <i32> [#uses=1]
 	%681 = add i32 %676, %680                 ; <i32> [#uses=1]
 	%682 = xor i32 %661, %636                 ; <i32> [#uses=1]
 	%683 = xor i32 %682, %681                 ; <i32> [#uses=5]
-	%684 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 1; <i32*> [#uses=1]
+	%684 = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 0, i32 1; <i32*> [#uses=1]
 	br label %bb2
 
 bb2:                                              ; preds = %bb1, %bb
@@ -712,21 +712,21 @@ bb2:                                              ; preds = %bb1, %bb
 	%.pn15 = lshr i32 %.pn15.in, 24           ; <i32> [#uses=1]
 	%.pn14 = and i32 %.pn14.in, 511           ; <i32> [#uses=1]
 	%.pn13.in = or i32 %.pn13.in.in, 512      ; <i32> [#uses=1]
-	%.pn11.in = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %.pn15; <i32*> [#uses=1]
-	%.pn12.in = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %.pn14; <i32*> [#uses=1]
+	%.pn11.in = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %.pn15; <i32*> [#uses=1]
+	%.pn12.in = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %.pn14; <i32*> [#uses=1]
 	%.pn13 = and i32 %.pn13.in, 767           ; <i32> [#uses=1]
 	%.pn10.in = or i32 %.pn10.in.in, 768      ; <i32> [#uses=1]
-	%.pn11 = load i32* %.pn11.in              ; <i32> [#uses=1]
-	%.pn12 = load i32* %.pn12.in              ; <i32> [#uses=1]
-	%.pn9.in = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %.pn13; <i32*> [#uses=1]
+	%.pn11 = load i32, i32* %.pn11.in              ; <i32> [#uses=1]
+	%.pn12 = load i32, i32* %.pn12.in              ; <i32> [#uses=1]
+	%.pn9.in = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %.pn13; <i32*> [#uses=1]
 	%.pn10 = and i32 %.pn10.in, 1023          ; <i32> [#uses=1]
 	%.pn8 = add i32 %.pn12, %.pn11            ; <i32> [#uses=1]
-	%.pn9 = load i32* %.pn9.in                ; <i32> [#uses=1]
-	%.pn7.in = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %.pn10; <i32*> [#uses=1]
+	%.pn9 = load i32, i32* %.pn9.in                ; <i32> [#uses=1]
+	%.pn7.in = getelementptr %struct.BF_KEY, %struct.BF_KEY* %key, i32 0, i32 1, i32 %.pn10; <i32*> [#uses=1]
 	%.pn6 = xor i32 %.pn8, %.pn9              ; <i32> [#uses=1]
-	%.pn7 = load i32* %.pn7.in                ; <i32> [#uses=1]
-	%.pn4 = load i32* %.pn4.in                ; <i32> [#uses=1]
-	%.pn2 = load i32* %.pn2.in                ; <i32> [#uses=1]
+	%.pn7 = load i32, i32* %.pn7.in                ; <i32> [#uses=1]
+	%.pn4 = load i32, i32* %.pn4.in                ; <i32> [#uses=1]
+	%.pn2 = load i32, i32* %.pn2.in                ; <i32> [#uses=1]
 	%.pn = add i32 %.pn6, %.pn7               ; <i32> [#uses=1]
 	%r.0 = xor i32 %.pn2, %.pn3               ; <i32> [#uses=1]
 	%.pn1 = xor i32 %.pn, %.pn5               ; <i32> [#uses=1]
diff --git a/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll b/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll
index 041306db9f0d..983e0f5cfda4 100644
--- a/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll
+++ b/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll
@@ -11,19 +11,19 @@ define i8* @vorbis_comment_query(%struct.vorbis_comment* nocapture %vc, i8* %tag
 entry:
 	%0 = alloca i8, i32 undef, align 4        ; <i8*> [#uses=2]
 	%1 = call  i8* @__strcpy_chk(i8* %0, i8* %tag, i32 -1) nounwind; <i8*> [#uses=0]
-	%2 = call  i8* @__strcat_chk(i8* %0, i8* getelementptr ([2 x i8]* @.str16, i32 0, i32 0), i32 -1) nounwind; <i8*> [#uses=0]
-	%3 = getelementptr %struct.vorbis_comment* %vc, i32 0, i32 0; <i8***> [#uses=1]
+	%2 = call  i8* @__strcat_chk(i8* %0, i8* getelementptr ([2 x i8], [2 x i8]* @.str16, i32 0, i32 0), i32 -1) nounwind; <i8*> [#uses=0]
+	%3 = getelementptr %struct.vorbis_comment, %struct.vorbis_comment* %vc, i32 0, i32 0; <i8***> [#uses=1]
 	br label %bb11
 
 bb6:                                              ; preds = %bb11
-	%4 = load i8*** %3, align 4               ; <i8**> [#uses=1]
-	%scevgep = getelementptr i8** %4, i32 %8  ; <i8**> [#uses=1]
-	%5 = load i8** %scevgep, align 4          ; <i8*> [#uses=1]
+	%4 = load i8**, i8*** %3, align 4               ; <i8**> [#uses=1]
+	%scevgep = getelementptr i8*, i8** %4, i32 %8  ; <i8**> [#uses=1]
+	%5 = load i8*, i8** %scevgep, align 4          ; <i8*> [#uses=1]
 	br label %bb3.i
 
 bb3.i:                                            ; preds = %bb3.i, %bb6
-	%scevgep7.i = getelementptr i8* %5, i32 0 ; <i8*> [#uses=1]
-	%6 = load i8* %scevgep7.i, align 1        ; <i8> [#uses=0]
+	%scevgep7.i = getelementptr i8, i8* %5, i32 0 ; <i8*> [#uses=1]
+	%6 = load i8, i8* %scevgep7.i, align 1        ; <i8> [#uses=0]
 	br i1 undef, label %bb3.i, label %bb10
 
 bb10:                                             ; preds = %bb3.i
diff --git a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
index 414b76d750b9..86d702395726 100644
--- a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
+++ b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
@@ -18,15 +18,15 @@ entry:
   br i1 %0, label %bb13, label %bb1
 
 bb1:                                              ; preds = %entry
-  %1 = getelementptr inbounds %struct.asl_file_t* %s, i32 0, i32 11 ; <%struct.FILE**> [#uses=2]
-  %2 = load %struct.FILE** %1, align 4            ; <%struct.FILE*> [#uses=2]
+  %1 = getelementptr inbounds %struct.asl_file_t, %struct.asl_file_t* %s, i32 0, i32 11 ; <%struct.FILE**> [#uses=2]
+  %2 = load %struct.FILE*, %struct.FILE** %1, align 4            ; <%struct.FILE*> [#uses=2]
   %3 = icmp eq %struct.FILE* %2, null             ; <i1> [#uses=1]
   br i1 %3, label %bb13, label %bb3
 
 bb3:                                              ; preds = %bb1
   %4 = add nsw i64 %off, 8                        ; <i64> [#uses=1]
-  %5 = getelementptr inbounds %struct.asl_file_t* %s, i32 0, i32 10 ; <i32*> [#uses=1]
-  %6 = load i32* %5, align 4                      ; <i32> [#uses=1]
+  %5 = getelementptr inbounds %struct.asl_file_t, %struct.asl_file_t* %s, i32 0, i32 10 ; <i32*> [#uses=1]
+  %6 = load i32, i32* %5, align 4                      ; <i32> [#uses=1]
   %7 = zext i32 %6 to i64                         ; <i64> [#uses=1]
   %8 = icmp sgt i64 %4, %7                        ; <i1> [#uses=1]
   br i1 %8, label %bb13, label %bb5
@@ -38,7 +38,7 @@ bb5:                                              ; preds = %bb3
 
 bb7:                                              ; preds = %bb5
   store i64 0, i64* %val, align 4
-  %11 = load %struct.FILE** %1, align 4           ; <%struct.FILE*> [#uses=1]
+  %11 = load %struct.FILE*, %struct.FILE** %1, align 4           ; <%struct.FILE*> [#uses=1]
   %val8 = bitcast i64* %val to i8*                ; <i8*> [#uses=1]
   %12 = call  i32 @fread(i8* noalias %val8, i32 8, i32 1, %struct.FILE* noalias %11) nounwind ; <i32> [#uses=1]
   %13 = icmp eq i32 %12, 1                        ; <i1> [#uses=1]
@@ -49,7 +49,7 @@ bb10:                                             ; preds = %bb7
   br i1 %14, label %bb13, label %bb11
 
 bb11:                                             ; preds = %bb10
-  %15 = load i64* %val, align 4                   ; <i64> [#uses=1]
+  %15 = load i64, i64* %val, align 4                   ; <i64> [#uses=1]
   %16 = call  i64 @asl_core_ntohq(i64 %15) nounwind ; <i64> [#uses=1]
   store i64 %16, i64* %out, align 4
   ret i32 0
diff --git a/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll b/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll
index 132d9acf6745..e7684177e31c 100644
--- a/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll
+++ b/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll
@@ -12,17 +12,17 @@ target triple = "thumbv7-apple-darwin10"
 
 define i32 @interpret_threaded(i8* nocapture %opcodes) nounwind readonly optsize {
 entry:
-  %0 = load i8* %opcodes, align 1                 ; <i8> [#uses=1]
+  %0 = load i8, i8* %opcodes, align 1                 ; <i8> [#uses=1]
   %1 = zext i8 %0 to i32                          ; <i32> [#uses=1]
-  %2 = getelementptr inbounds [5 x i8*]* @codetable.2928, i32 0, i32 %1 ; <i8**> [#uses=1]
+  %2 = getelementptr inbounds [5 x i8*], [5 x i8*]* @codetable.2928, i32 0, i32 %1 ; <i8**> [#uses=1]
   br label %bb
 
 bb:                                               ; preds = %bb.backedge, %entry
   %indvar = phi i32 [ %phitmp, %bb.backedge ], [ 1, %entry ] ; <i32> [#uses=2]
   %gotovar.22.0.in = phi i8** [ %gotovar.22.0.in.be, %bb.backedge ], [ %2, %entry ] ; <i8**> [#uses=1]
   %result.0 = phi i32 [ %result.0.be, %bb.backedge ], [ 0, %entry ] ; <i32> [#uses=6]
-  %opcodes_addr.0 = getelementptr i8* %opcodes, i32 %indvar ; <i8*> [#uses=4]
-  %gotovar.22.0 = load i8** %gotovar.22.0.in, align 4 ; <i8*> [#uses=1]
+  %opcodes_addr.0 = getelementptr i8, i8* %opcodes, i32 %indvar ; <i8*> [#uses=4]
+  %gotovar.22.0 = load i8*, i8** %gotovar.22.0.in, align 4 ; <i8*> [#uses=1]
   indirectbr i8* %gotovar.22.0, [label %RETURN, label %INCREMENT, label %DECREMENT, label %DOUBLE, label %SWAPWORD]
 
 RETURN:                                           ; preds = %bb
@@ -30,9 +30,9 @@ RETURN:                                           ; preds = %bb
 
 INCREMENT:                                        ; preds = %bb
   %3 = add nsw i32 %result.0, 1                   ; <i32> [#uses=1]
-  %4 = load i8* %opcodes_addr.0, align 1          ; <i8> [#uses=1]
+  %4 = load i8, i8* %opcodes_addr.0, align 1          ; <i8> [#uses=1]
   %5 = zext i8 %4 to i32                          ; <i32> [#uses=1]
-  %6 = getelementptr inbounds [5 x i8*]* @codetable.2928, i32 0, i32 %5 ; <i8**> [#uses=1]
+  %6 = getelementptr inbounds [5 x i8*], [5 x i8*]* @codetable.2928, i32 0, i32 %5 ; <i8**> [#uses=1]
   br label %bb.backedge
 
 bb.backedge:                                      ; preds = %SWAPWORD, %DOUBLE, %DECREMENT, %INCREMENT
@@ -43,24 +43,24 @@ bb.backedge:                                      ; preds = %SWAPWORD, %DOUBLE,
 
 DECREMENT:                                        ; preds = %bb
   %7 = add i32 %result.0, -1                      ; <i32> [#uses=1]
-  %8 = load i8* %opcodes_addr.0, align 1          ; <i8> [#uses=1]
+  %8 = load i8, i8* %opcodes_addr.0, align 1          ; <i8> [#uses=1]
   %9 = zext i8 %8 to i32                          ; <i32> [#uses=1]
-  %10 = getelementptr inbounds [5 x i8*]* @codetable.2928, i32 0, i32 %9 ; <i8**> [#uses=1]
+  %10 = getelementptr inbounds [5 x i8*], [5 x i8*]* @codetable.2928, i32 0, i32 %9 ; <i8**> [#uses=1]
   br label %bb.backedge
 
 DOUBLE:                                           ; preds = %bb
   %11 = shl i32 %result.0, 1                      ; <i32> [#uses=1]
-  %12 = load i8* %opcodes_addr.0, align 1         ; <i8> [#uses=1]
+  %12 = load i8, i8* %opcodes_addr.0, align 1         ; <i8> [#uses=1]
   %13 = zext i8 %12 to i32                        ; <i32> [#uses=1]
-  %14 = getelementptr inbounds [5 x i8*]* @codetable.2928, i32 0, i32 %13 ; <i8**> [#uses=1]
+  %14 = getelementptr inbounds [5 x i8*], [5 x i8*]* @codetable.2928, i32 0, i32 %13 ; <i8**> [#uses=1]
   br label %bb.backedge
 
 SWAPWORD:                                         ; preds = %bb
   %15 = shl i32 %result.0, 16                     ; <i32> [#uses=1]
   %16 = ashr i32 %result.0, 16                    ; <i32> [#uses=1]
   %17 = or i32 %15, %16                           ; <i32> [#uses=1]
-  %18 = load i8* %opcodes_addr.0, align 1         ; <i8> [#uses=1]
+  %18 = load i8, i8* %opcodes_addr.0, align 1         ; <i8> [#uses=1]
   %19 = zext i8 %18 to i32                        ; <i32> [#uses=1]
-  %20 = getelementptr inbounds [5 x i8*]* @codetable.2928, i32 0, i32 %19 ; <i8**> [#uses=1]
+  %20 = getelementptr inbounds [5 x i8*], [5 x i8*]* @codetable.2928, i32 0, i32 %19 ; <i8**> [#uses=1]
   br label %bb.backedge
 }
diff --git a/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll b/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll
index 622f55d994f6..0fd1a9e1e232 100644
--- a/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll
+++ b/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll
@@ -25,11 +25,11 @@ define void @_Z19getClosestDiagonal3ii(%0* noalias sret, i32, i32) nounwind {
   %storemerge = phi double [ -1.000000e+00, %4 ], [ 1.000000e+00, %3 ], [ 1.000000e+00, %3 ] ; <double> [#uses=1]
   %v_6 = icmp slt i32 %1, 2                         ; <i1> [#uses=1]
   %storemerge1 = select i1 %v_6, double 1.000000e+00, double -1.000000e+00 ; <double> [#uses=3]
-  call void @llvm.dbg.value(metadata double %storemerge, i64 0, metadata !91, metadata !{!"0x102"}), !dbg !0
+  call void @llvm.dbg.value(metadata double %storemerge, i64 0, metadata !91, metadata !DIExpression()), !dbg !0
   %v_7 = icmp eq i32 %2, 1, !dbg !92                ; <i1> [#uses=1]
   %storemerge2 = select i1 %v_7, double 1.000000e+00, double -1.000000e+00 ; <double> [#uses=3]
-  %v_8 = getelementptr inbounds %0* %0, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
-  %v_10 = getelementptr inbounds %0* %0, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+  %v_8 = getelementptr inbounds %0, %0* %0, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+  %v_10 = getelementptr inbounds %0, %0* %0, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
   %v_11 = fmul double %storemerge1, %storemerge1, !dbg !93 ; <double> [#uses=1]
   %v_15 = tail call double @sqrt(double %v_11) nounwind readonly, !dbg !93 ; <double> [#uses=1]
   %v_16 = fdiv double 1.000000e+00, %v_15, !dbg !93   ; <double> [#uses=3]
@@ -48,108 +48,108 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 
 !llvm.dbg.cu = !{!5}
 !llvm.module.flags = !{!104}
-!0 = !MDLocation(line: 46, scope: !1)
-!1 = !{!"0xb\0044\000\000", !101, !2} ; [ DW_TAG_lexical_block ]
-!2 = !{!"0xb\0044\000\000", !101, !3} ; [ DW_TAG_lexical_block ]
-!3 = !{!"0x2e\00getClosestDiagonal3\00getClosestDiagonal3\00_Z19getClosestDiagonal3ii\0044\000\001\000\006\000\000\000", !101, null, !6, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!4 = !{!"0x29", !101} ; [ DW_TAG_file_type ]
-!5 = !{!"0x11\004\004.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)\001\00\000\00\000", !101, !102, !102, !103, null, null} ; [ DW_TAG_compile_unit ]
-!6 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocation(line: 46, scope: !1)
+!1 = distinct !DILexicalBlock(line: 44, column: 0, file: !101, scope: !2)
+!2 = distinct !DILexicalBlock(line: 44, column: 0, file: !101, scope: !3)
+!3 = !DISubprogram(name: "getClosestDiagonal3", linkageName: "_Z19getClosestDiagonal3ii", line: 44, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !101, scope: null, type: !6)
+!4 = !DIFile(filename: "ggEdgeDiscrepancy.cc", directory: "/Volumes/Home/grosbaj/sources/llvm-externals/speccpu2000/benchspec/CINT2000/252.eon/src")
+!5 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)", isOptimized: true, emissionKind: 0, file: !101, enums: !102, retainedTypes: !102, subprograms: !103)
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !22, !22}
-!8 = !{!"0x13\00ggVector3\0066\00192\0032\000\000\000", !99, null, null, !10, null, null, null} ; [ DW_TAG_structure_type ] [ggVector3] [line 66, size 192, align 32, offset 0] [def] [from ]
-!9 = !{!"0x29", !"ggVector3.h", !"/Volumes/Home/grosbaj/sources/llvm-externals/speccpu2000/benchspec/CINT2000/252.eon/src", !5} ; [ DW_TAG_file_type ]
-!99 = !{!"ggVector3.h", !"/Volumes/Home/grosbaj/sources/llvm-externals/speccpu2000/benchspec/CINT2000/252.eon/src"}
+!8 = !DICompositeType(tag: DW_TAG_structure_type, name: "ggVector3", line: 66, size: 192, align: 32, file: !99, elements: !10)
+!9 = !DIFile(filename: "ggVector3.h", directory: "/Volumes/Home/grosbaj/sources/llvm-externals/speccpu2000/benchspec/CINT2000/252.eon/src")
+!99 = !DIFile(filename: "ggVector3.h", directory: "/Volumes/Home/grosbaj/sources/llvm-externals/speccpu2000/benchspec/CINT2000/252.eon/src")
 !10 = !{!11, !16, !23, !26, !29, !30, !35, !36, !37, !41, !42, !43, !46, !47, !48, !52, !53, !54, !57, !60, !63, !66, !70, !71, !74, !75, !76, !77, !78, !81, !82, !83, !84, !85, !88, !89, !90}
-!11 = !{!"0xd\00e\00160\00192\0032\000\000", !99, !8, !12} ; [ DW_TAG_member ]
-!12 = !{!"0x1\00\000\00192\0032\000\000", !101, !4, !13, !14, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 192, align 32, offset 0] [from double]
-!13 = !{!"0x24\00double\000\0064\0032\000\000\004", !101, !4} ; [ DW_TAG_base_type ]
+!11 = !DIDerivedType(tag: DW_TAG_member, name: "e", line: 160, size: 192, align: 32, file: !99, scope: !8, baseType: !12)
+!12 = !DICompositeType(tag: DW_TAG_array_type, size: 192, align: 32, file: !101, scope: !4, baseType: !13, elements: !14)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 32, encoding: DW_ATE_float)
 !14 = !{!15}
-!15 = !{!"0x21\000\003"}        ; [ DW_TAG_subrange_type ]
-!16 = !{!"0x2e\00ggVector3\00ggVector3\00\0072\000\000\000\006\000\000\000", !9, !8, !17, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!17 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !18, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!15 = !DISubrange(count: 3)
+!16 = !DISubprogram(name: "ggVector3", line: 72, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !17)
+!17 = !DISubroutineType(types: !18)
 !18 = !{null, !19, !20}
-!19 = !{!"0xf\00\000\0032\0032\000\0064", !101, !4, !8} ; [ DW_TAG_pointer_type ]
-!20 = !{!"0x16\00ggBoolean\00478\000\000\000\000", !100, null, !22} ; [ DW_TAG_typedef ]
-!21 = !{!"0x29", !"math.h", !"/Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS4.2.Internal.sdk/usr/include/architecture/arm", !5} ; [ DW_TAG_file_type ]
-!100 = !{!"math.h", !"/Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS4.2.Internal.sdk/usr/include/architecture/arm"}
-!22 = !{!"0x24\00int\000\0032\0032\000\000\005", !101, !4} ; [ DW_TAG_base_type ]
-!23 = !{!"0x2e\00ggVector3\00ggVector3\00\0073\000\000\000\006\000\000\000", !9, !8, !24, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!24 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !25, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!19 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, flags: DIFlagArtificial, file: !101, scope: !4, baseType: !8)
+!20 = !DIDerivedType(tag: DW_TAG_typedef, name: "ggBoolean", line: 478, file: !100, baseType: !22)
+!21 = !DIFile(filename: "math.h", directory: "/Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS4.2.Internal.sdk/usr/include/architecture/arm")
+!100 = !DIFile(filename: "math.h", directory: "/Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS4.2.Internal.sdk/usr/include/architecture/arm")
+!22 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!23 = !DISubprogram(name: "ggVector3", line: 73, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !24)
+!24 = !DISubroutineType(types: !25)
 !25 = !{null, !19}
-!26 = !{!"0x2e\00ggVector3\00ggVector3\00\0074\000\000\000\006\000\000\000", !9, !8, !27, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!27 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !28, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!26 = !DISubprogram(name: "ggVector3", line: 74, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !27)
+!27 = !DISubroutineType(types: !28)
 !28 = !{null, !19, !13, !13, !13}
-!29 = !{!"0x2e\00Set\00Set\00_ZN9ggVector33SetEddd\0081\000\000\000\006\000\000\000", !9, !8, !27, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!30 = !{!"0x2e\00x\00x\00_ZNK9ggVector31xEv\0082\000\000\000\006\000\000\000", !9, !8, !31, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!31 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !32, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!29 = !DISubprogram(name: "Set", linkageName: "_ZN9ggVector33SetEddd", line: 81, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !27)
+!30 = !DISubprogram(name: "x", linkageName: "_ZNK9ggVector31xEv", line: 82, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !31)
+!31 = !DISubroutineType(types: !32)
 !32 = !{!13, !33}
-!33 = !{!"0xf\00\000\0032\0032\000\0064", !101, !4, !34} ; [ DW_TAG_pointer_type ]
-!34 = !{!"0x26\00\000\00192\0032\000\000", !101, !4, !8} ; [ DW_TAG_const_type ]
-!35 = !{!"0x2e\00y\00y\00_ZNK9ggVector31yEv\0083\000\000\000\006\000\000\000", !9, !8, !31, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!36 = !{!"0x2e\00z\00z\00_ZNK9ggVector31zEv\0084\000\000\000\006\000\000\000", !9, !8, !31, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!37 = !{!"0x2e\00x\00x\00_ZN9ggVector31xEv\0085\000\001\000\006\000\000\000", !9, !8, !38, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!38 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !39, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!33 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, flags: DIFlagArtificial, file: !101, scope: !4, baseType: !34)
+!34 = !DIDerivedType(tag: DW_TAG_const_type, size: 192, align: 32, file: !101, scope: !4, baseType: !8)
+!35 = !DISubprogram(name: "y", linkageName: "_ZNK9ggVector31yEv", line: 83, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !31)
+!36 = !DISubprogram(name: "z", linkageName: "_ZNK9ggVector31zEv", line: 84, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !31)
+!37 = !DISubprogram(name: "x", linkageName: "_ZN9ggVector31xEv", line: 85, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !38)
+!38 = !DISubroutineType(types: !39)
 !39 = !{!40, !19}
-!40 = !{!"0x10\00double\000\0032\0032\000\000", !101, !4, !13} ; [ DW_TAG_reference_type ]
-!41 = !{!"0x2e\00y\00y\00_ZN9ggVector31yEv\0086\000\001\000\006\000\000\000", !9, !8, !38, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!42 = !{!"0x2e\00z\00z\00_ZN9ggVector31zEv\0087\000\001\000\006\000\000\000", !9, !8, !38, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!43 = !{!"0x2e\00SetX\00SetX\00_ZN9ggVector34SetXEd\0088\000\000\000\006\000\000\000", !9, !8, !44, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!44 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !45, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!40 = !DIDerivedType(tag: DW_TAG_reference_type, name: "double", size: 32, align: 32, file: !101, scope: !4, baseType: !13)
+!41 = !DISubprogram(name: "y", linkageName: "_ZN9ggVector31yEv", line: 86, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !38)
+!42 = !DISubprogram(name: "z", linkageName: "_ZN9ggVector31zEv", line: 87, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !38)
+!43 = !DISubprogram(name: "SetX", linkageName: "_ZN9ggVector34SetXEd", line: 88, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !44)
+!44 = !DISubroutineType(types: !45)
 !45 = !{null, !19, !13}
-!46 = !{!"0x2e\00SetY\00SetY\00_ZN9ggVector34SetYEd\0089\000\000\000\006\000\000\000", !9, !8, !44, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!47 = !{!"0x2e\00SetZ\00SetZ\00_ZN9ggVector34SetZEd\0090\000\000\000\006\000\000\000", !9, !8, !44, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!48 = !{!"0x2e\00ggVector3\00ggVector3\00\0092\000\000\000\006\000\000\000", !9, !8, !49, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!49 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !50, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!46 = !DISubprogram(name: "SetY", linkageName: "_ZN9ggVector34SetYEd", line: 89, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !44)
+!47 = !DISubprogram(name: "SetZ", linkageName: "_ZN9ggVector34SetZEd", line: 90, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !44)
+!48 = !DISubprogram(name: "ggVector3", line: 92, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !49)
+!49 = !DISubroutineType(types: !50)
 !50 = !{null, !19, !51}
-!51 = !{!"0x10\00\000\0032\0032\000\000", !101, !4, !34} ; [ DW_TAG_reference_type ]
-!52 = !{!"0x2e\00tolerance\00tolerance\00_ZNK9ggVector39toleranceEv\00100\000\000\000\006\000\000\000", !9, !8, !31, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!53 = !{!"0x2e\00tolerance\00tolerance\00_ZN9ggVector39toleranceEv\00101\000\000\000\006\000\000\000", !9, !8, !38, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!54 = !{!"0x2e\00operator+\00operator+\00_ZNK9ggVector3psEv\00107\000\000\000\006\000\000\000", !9, !8, !55, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!55 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !56, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!51 = !DIDerivedType(tag: DW_TAG_reference_type, size: 32, align: 32, file: !101, scope: !4, baseType: !34)
+!52 = !DISubprogram(name: "tolerance", linkageName: "_ZNK9ggVector39toleranceEv", line: 100, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !31)
+!53 = !DISubprogram(name: "tolerance", linkageName: "_ZN9ggVector39toleranceEv", line: 101, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !38)
+!54 = !DISubprogram(name: "operator+", linkageName: "_ZNK9ggVector3psEv", line: 107, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !55)
+!55 = !DISubroutineType(types: !56)
 !56 = !{!51, !33}
-!57 = !{!"0x2e\00operator-\00operator-\00_ZNK9ggVector3ngEv\00108\000\000\000\006\000\000\000", !9, !8, !58, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!58 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !59, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!57 = !DISubprogram(name: "operator-", linkageName: "_ZNK9ggVector3ngEv", line: 108, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !58)
+!58 = !DISubroutineType(types: !59)
 !59 = !{!8, !33}
-!60 = !{!"0x2e\00operator[]\00operator[]\00_ZNK9ggVector3ixEi\00290\000\000\000\006\000\000\000", !9, !8, !61, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!61 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !62, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!60 = !DISubprogram(name: "operator[]", linkageName: "_ZNK9ggVector3ixEi", line: 290, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !61)
+!61 = !DISubroutineType(types: !62)
 !62 = !{!13, !33, !22}
-!63 = !{!"0x2e\00operator[]\00operator[]\00_ZN9ggVector3ixEi\00278\000\000\000\006\000\000\000", !9, !8, !64, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!64 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !65, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!63 = !DISubprogram(name: "operator[]", linkageName: "_ZN9ggVector3ixEi", line: 278, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !64)
+!64 = !DISubroutineType(types: !65)
 !65 = !{!40, !19, !22}
-!66 = !{!"0x2e\00operator+=\00operator+=\00_ZN9ggVector3pLERKS_\00303\000\000\000\006\000\000\000", !9, !8, !67, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!67 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !68, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!66 = !DISubprogram(name: "operator+=", linkageName: "_ZN9ggVector3pLERKS_", line: 303, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !67)
+!67 = !DISubroutineType(types: !68)
 !68 = !{!69, !19, !51}
-!69 = !{!"0x10\00ggVector3\000\0032\0032\000\000", !101, !4, !8} ; [ DW_TAG_reference_type ]
-!70 = !{!"0x2e\00operator-=\00operator-=\00_ZN9ggVector3mIERKS_\00310\000\000\000\006\000\000\000", !9, !8, !67, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!71 = !{!"0x2e\00operator*=\00operator*=\00_ZN9ggVector3mLEd\00317\000\000\000\006\000\000\000", !9, !8, !72, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!72 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !73, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!69 = !DIDerivedType(tag: DW_TAG_reference_type, name: "ggVector3", size: 32, align: 32, file: !101, scope: !4, baseType: !8)
+!70 = !DISubprogram(name: "operator-=", linkageName: "_ZN9ggVector3mIERKS_", line: 310, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !67)
+!71 = !DISubprogram(name: "operator*=", linkageName: "_ZN9ggVector3mLEd", line: 317, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !72)
+!72 = !DISubroutineType(types: !73)
 !73 = !{!69, !19, !13}
-!74 = !{!"0x2e\00operator/=\00operator/=\00_ZN9ggVector3dVEd\00324\000\000\000\006\000\000\000", !9, !8, !72, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!75 = !{!"0x2e\00length\00length\00_ZNK9ggVector36lengthEv\00121\000\000\000\006\000\000\000", !9, !8, !31, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!76 = !{!"0x2e\00squaredLength\00squaredLength\00_ZNK9ggVector313squaredLengthEv\00122\000\000\000\006\000\000\000", !9, !8, !31, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!77 = !{!"0x2e\00MakeUnitVector\00MakeUnitVector\00_ZN9ggVector314MakeUnitVectorEv\00217\000\001\000\006\000\000\000", !9, !8, !24, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!78 = !{!"0x2e\00Perturb\00Perturb\00_ZNK9ggVector37PerturbEdd\00126\000\000\000\006\000\000\000", !9, !8, !79, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!79 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !80, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!74 = !DISubprogram(name: "operator/=", linkageName: "_ZN9ggVector3dVEd", line: 324, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !72)
+!75 = !DISubprogram(name: "length", linkageName: "_ZNK9ggVector36lengthEv", line: 121, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !31)
+!76 = !DISubprogram(name: "squaredLength", linkageName: "_ZNK9ggVector313squaredLengthEv", line: 122, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !31)
+!77 = !DISubprogram(name: "MakeUnitVector", linkageName: "_ZN9ggVector314MakeUnitVectorEv", line: 217, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !24)
+!78 = !DISubprogram(name: "Perturb", linkageName: "_ZNK9ggVector37PerturbEdd", line: 126, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !79)
+!79 = !DISubroutineType(types: !80)
 !80 = !{!8, !33, !13, !13}
-!81 = !{!"0x2e\00maxComponent\00maxComponent\00_ZNK9ggVector312maxComponentEv\00128\000\000\000\006\000\000\000", !9, !8, !31, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!82 = !{!"0x2e\00minComponent\00minComponent\00_ZNK9ggVector312minComponentEv\00129\000\000\000\006\000\000\000", !9, !8, !31, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!83 = !{!"0x2e\00maxAbsComponent\00maxAbsComponent\00_ZNK9ggVector315maxAbsComponentEv\00131\000\000\000\006\000\000\000", !9, !8, !31, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!84 = !{!"0x2e\00minAbsComponent\00minAbsComponent\00_ZNK9ggVector315minAbsComponentEv\00132\000\000\000\006\000\000\000", !9, !8, !31, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!85 = !{!"0x2e\00indexOfMinComponent\00indexOfMinComponent\00_ZNK9ggVector319indexOfMinComponentEv\00133\000\000\000\006\000\000\000", !9, !8, !86, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!86 = !{!"0x15\00\000\000\000\000\000\000", !101, !4, null, !87, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!81 = !DISubprogram(name: "maxComponent", linkageName: "_ZNK9ggVector312maxComponentEv", line: 128, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !31)
+!82 = !DISubprogram(name: "minComponent", linkageName: "_ZNK9ggVector312minComponentEv", line: 129, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !31)
+!83 = !DISubprogram(name: "maxAbsComponent", linkageName: "_ZNK9ggVector315maxAbsComponentEv", line: 131, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !31)
+!84 = !DISubprogram(name: "minAbsComponent", linkageName: "_ZNK9ggVector315minAbsComponentEv", line: 132, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !31)
+!85 = !DISubprogram(name: "indexOfMinComponent", linkageName: "_ZNK9ggVector319indexOfMinComponentEv", line: 133, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !86)
+!86 = !DISubroutineType(types: !87)
 !87 = !{!22, !33}
-!88 = !{!"0x2e\00indexOfMinAbsComponent\00indexOfMinAbsComponent\00_ZNK9ggVector322indexOfMinAbsComponentEv\00137\000\000\000\006\000\000\000", !9, !8, !86, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!89 = !{!"0x2e\00indexOfMaxComponent\00indexOfMaxComponent\00_ZNK9ggVector319indexOfMaxComponentEv\00146\000\000\000\006\000\000\000", !9, !8, !86, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!90 = !{!"0x2e\00indexOfMaxAbsComponent\00indexOfMaxAbsComponent\00_ZNK9ggVector322indexOfMaxAbsComponentEv\00150\000\000\000\006\000\000\000", !9, !8, !86, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!91 = !{!"0x100\00vx\0046\000", !1, !4, !13} ; [ DW_TAG_auto_variable ]
-!92 = !MDLocation(line: 48, scope: !1)
-!93 = !MDLocation(line: 218, scope: !94, inlinedAt: !96)
-!94 = !{!"0xb\00217\000\000", !101, !95} ; [ DW_TAG_lexical_block ]
-!95 = !{!"0xb\00217\000\000", !101, !77} ; [ DW_TAG_lexical_block ]
-!96 = !MDLocation(line: 51, scope: !1)
-!97 = !MDLocation(line: 227, scope: !94, inlinedAt: !96)
-!98 = !MDLocation(line: 52, scope: !1)
-!101 = !{!"ggEdgeDiscrepancy.cc", !"/Volumes/Home/grosbaj/sources/llvm-externals/speccpu2000/benchspec/CINT2000/252.eon/src"}
-!102 = !{i32 0}
+!88 = !DISubprogram(name: "indexOfMinAbsComponent", linkageName: "_ZNK9ggVector322indexOfMinAbsComponentEv", line: 137, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !86)
+!89 = !DISubprogram(name: "indexOfMaxComponent", linkageName: "_ZNK9ggVector319indexOfMaxComponentEv", line: 146, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !86)
+!90 = !DISubprogram(name: "indexOfMaxAbsComponent", linkageName: "_ZNK9ggVector322indexOfMaxAbsComponentEv", line: 150, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !9, scope: !8, type: !86)
+!91 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vx", line: 46, scope: !1, file: !4, type: !13)
+!92 = !DILocation(line: 48, scope: !1)
+!93 = !DILocation(line: 218, scope: !94, inlinedAt: !96)
+!94 = distinct !DILexicalBlock(line: 217, column: 0, file: !101, scope: !95)
+!95 = distinct !DILexicalBlock(line: 217, column: 0, file: !101, scope: !77)
+!96 = !DILocation(line: 51, scope: !1)
+!97 = !DILocation(line: 227, scope: !94, inlinedAt: !96)
+!98 = !DILocation(line: 52, scope: !1)
+!101 = !DIFile(filename: "ggEdgeDiscrepancy.cc", directory: "/Volumes/Home/grosbaj/sources/llvm-externals/speccpu2000/benchspec/CINT2000/252.eon/src")
+!102 = !{}
 !103 = !{!3, !77}
-!104 = !{i32 1, !"Debug Info Version", i32 2}
+!104 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll b/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
index ed55bb5dcf89..d8e165145bd6 100644
--- a/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
+++ b/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
@@ -23,32 +23,32 @@ entry:
   br label %do.body
 
 do.body:                                          ; preds = %entry
-  %tmp = load i8** @kkkkkk, align 4
-  %tmp1 = load %struct.MMMMMMMMMMMM** %aidData.addr
-  %eph = getelementptr inbounds %struct.MMMMMMMMMMMM* %tmp1, i32 0, i32 0
-  %arrayidx = getelementptr inbounds [4 x %struct.RRRRRRRR]* %eph, i32 0, i32 0
+  %tmp = load i8*, i8** @kkkkkk, align 4
+  %tmp1 = load %struct.MMMMMMMMMMMM*, %struct.MMMMMMMMMMMM** %aidData.addr
+  %eph = getelementptr inbounds %struct.MMMMMMMMMMMM, %struct.MMMMMMMMMMMM* %tmp1, i32 0, i32 0
+  %arrayidx = getelementptr inbounds [4 x %struct.RRRRRRRR], [4 x %struct.RRRRRRRR]* %eph, i32 0, i32 0
   %tmp2 = bitcast %struct.RRRRRRRR* %agg.tmp to i8*
   %tmp3 = bitcast %struct.RRRRRRRR* %arrayidx to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp2, i8* %tmp3, i32 312, i32 4, i1 false)
-  %tmp5 = load %struct.MMMMMMMMMMMM** %aidData.addr
-  %eph6 = getelementptr inbounds %struct.MMMMMMMMMMMM* %tmp5, i32 0, i32 0
-  %arrayidx7 = getelementptr inbounds [4 x %struct.RRRRRRRR]* %eph6, i32 0, i32 1
+  %tmp5 = load %struct.MMMMMMMMMMMM*, %struct.MMMMMMMMMMMM** %aidData.addr
+  %eph6 = getelementptr inbounds %struct.MMMMMMMMMMMM, %struct.MMMMMMMMMMMM* %tmp5, i32 0, i32 0
+  %arrayidx7 = getelementptr inbounds [4 x %struct.RRRRRRRR], [4 x %struct.RRRRRRRR]* %eph6, i32 0, i32 1
   %tmp8 = bitcast %struct.RRRRRRRR* %agg.tmp4 to i8*
   %tmp9 = bitcast %struct.RRRRRRRR* %arrayidx7 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp8, i8* %tmp9, i32 312, i32 4, i1 false)
-  %tmp11 = load %struct.MMMMMMMMMMMM** %aidData.addr
-  %eph12 = getelementptr inbounds %struct.MMMMMMMMMMMM* %tmp11, i32 0, i32 0
-  %arrayidx13 = getelementptr inbounds [4 x %struct.RRRRRRRR]* %eph12, i32 0, i32 2
+  %tmp11 = load %struct.MMMMMMMMMMMM*, %struct.MMMMMMMMMMMM** %aidData.addr
+  %eph12 = getelementptr inbounds %struct.MMMMMMMMMMMM, %struct.MMMMMMMMMMMM* %tmp11, i32 0, i32 0
+  %arrayidx13 = getelementptr inbounds [4 x %struct.RRRRRRRR], [4 x %struct.RRRRRRRR]* %eph12, i32 0, i32 2
   %tmp14 = bitcast %struct.RRRRRRRR* %agg.tmp10 to i8*
   %tmp15 = bitcast %struct.RRRRRRRR* %arrayidx13 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp14, i8* %tmp15, i32 312, i32 4, i1 false)
-  %tmp17 = load %struct.MMMMMMMMMMMM** %aidData.addr
-  %eph18 = getelementptr inbounds %struct.MMMMMMMMMMMM* %tmp17, i32 0, i32 0
-  %arrayidx19 = getelementptr inbounds [4 x %struct.RRRRRRRR]* %eph18, i32 0, i32 3
+  %tmp17 = load %struct.MMMMMMMMMMMM*, %struct.MMMMMMMMMMMM** %aidData.addr
+  %eph18 = getelementptr inbounds %struct.MMMMMMMMMMMM, %struct.MMMMMMMMMMMM* %tmp17, i32 0, i32 0
+  %arrayidx19 = getelementptr inbounds [4 x %struct.RRRRRRRR], [4 x %struct.RRRRRRRR]* %eph18, i32 0, i32 3
   %tmp20 = bitcast %struct.RRRRRRRR* %agg.tmp16 to i8*
   %tmp21 = bitcast %struct.RRRRRRRR* %arrayidx19 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp20, i8* %tmp21, i32 312, i32 4, i1 false)
-  call void (i8*, i32, i8*, i8*, ...)* @CLLoggingLog(i8* %tmp, i32 2, i8* getelementptr inbounds ([62 x i8]* @__PRETTY_FUNCTION__._ZN12CLGll, i32 0, i32 0), i8* getelementptr inbounds ([75 x i8]* @.str, i32 0, i32 0), %struct.RRRRRRRR* byval %agg.tmp, %struct.RRRRRRRR* byval %agg.tmp4, %struct.RRRRRRRR* byval %agg.tmp10, %struct.RRRRRRRR* byval %agg.tmp16)
+  call void (i8*, i32, i8*, i8*, ...) @CLLoggingLog(i8* %tmp, i32 2, i8* getelementptr inbounds ([62 x i8], [62 x i8]* @__PRETTY_FUNCTION__._ZN12CLGll, i32 0, i32 0), i8* getelementptr inbounds ([75 x i8], [75 x i8]* @.str, i32 0, i32 0), %struct.RRRRRRRR* byval %agg.tmp, %struct.RRRRRRRR* byval %agg.tmp4, %struct.RRRRRRRR* byval %agg.tmp10, %struct.RRRRRRRR* byval %agg.tmp16)
   br label %do.end
 
 do.end:                                           ; preds = %do.body
diff --git a/test/CodeGen/Thumb/2011-06-16-NoGPRs.ll b/test/CodeGen/Thumb/2011-06-16-NoGPRs.ll
index d39a76085af2..accb82c18e70 100644
--- a/test/CodeGen/Thumb/2011-06-16-NoGPRs.ll
+++ b/test/CodeGen/Thumb/2011-06-16-NoGPRs.ll
@@ -16,7 +16,7 @@ declare i8* @f2(i8*, i8*, ...)
 
 define internal void @f(i8* %self, i8* %_cmd, %0* %inObjects, %0* %inIndexes) optsize ssp {
 entry:
-  %call14 = tail call i8* (i8*, i8*, ...)* (i8*, i8*)* @f1(i8* undef, i8* %_cmd) optsize
+  %call14 = tail call i8* (i8*, i8*, ...)* (i8*, i8*) @f1(i8* undef, i8* %_cmd) optsize
   %0 = bitcast i8* (i8*, i8*, ...)* %call14 to void (i8*, i8*, %0*, %0*)*
   tail call void %0(i8* %self, i8* %_cmd, %0* %inObjects, %0* %inIndexes) optsize
   tail call void bitcast (i8* (i8*, i8*, ...)* @f2 to void (i8*, i8*, i32, %0*, %0*)*)(i8* %self, i8* undef, i32 2, %0* %inIndexes, %0* undef) optsize
diff --git a/test/CodeGen/Thumb/2011-EpilogueBug.ll b/test/CodeGen/Thumb/2011-EpilogueBug.ll
index 16789e66cc18..9657dc7e0abc 100644
--- a/test/CodeGen/Thumb/2011-EpilogueBug.ll
+++ b/test/CodeGen/Thumb/2011-EpilogueBug.ll
@@ -6,7 +6,7 @@
 
 define void @t1(%struct.state* %v) {
 ; CHECK: push {r4
-  %tmp6 = load i32* null
+  %tmp6 = load i32, i32* null
   %tmp8 = alloca float, i32 %tmp6
   store i32 1, i32* null
   br label %return
diff --git a/test/CodeGen/Thumb/2014-06-10-thumb1-ldst-opt-bug.ll b/test/CodeGen/Thumb/2014-06-10-thumb1-ldst-opt-bug.ll
index cfa1159bda2c..d5c8db76de86 100644
--- a/test/CodeGen/Thumb/2014-06-10-thumb1-ldst-opt-bug.ll
+++ b/test/CodeGen/Thumb/2014-06-10-thumb1-ldst-opt-bug.ll
@@ -7,9 +7,9 @@ entry:
 ; CHECK: ldm
 ; CHECK-NEXT: subs
 ; CHECK-NEXT: bl
-  %0 = load i32* %A, align 4
-  %arrayidx1 = getelementptr inbounds i32* %A, i32 1
-  %1 = load i32* %arrayidx1, align 4
+  %0 = load i32, i32* %A, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i32 1
+  %1 = load i32, i32* %arrayidx1, align 4
   tail call void @bar(i32* %A, i32 %0, i32 %1) #2
   ret void
 }
diff --git a/test/CodeGen/Thumb/PR17309.ll b/test/CodeGen/Thumb/PR17309.ll
index b7b08e941898..f1033e7d7418 100644
--- a/test/CodeGen/Thumb/PR17309.ll
+++ b/test/CodeGen/Thumb/PR17309.ll
@@ -10,7 +10,7 @@
 define void @pass_C() #0 {
 entry:
   %c = alloca %struct.C, align 1
-  %0 = getelementptr inbounds %struct.C* %c, i32 0, i32 0, i32 0
+  %0 = getelementptr inbounds %struct.C, %struct.C* %c, i32 0, i32 0, i32 0
   call void @llvm.lifetime.start(i64 1000, i8* %0) #1
   call void @use_C(%struct.C* byval %c) #3
   call void @llvm.lifetime.end(i64 1000, i8* %0) #1
diff --git a/test/CodeGen/Thumb/asmprinter-bug.ll b/test/CodeGen/Thumb/asmprinter-bug.ll
index 18e11baf444c..e12fcb161a4a 100644
--- a/test/CodeGen/Thumb/asmprinter-bug.ll
+++ b/test/CodeGen/Thumb/asmprinter-bug.ll
@@ -15,14 +15,14 @@
 
 define void @adpcm_coder(i16* nocapture %indata, i8* nocapture %outdata, i32 %len, %struct.adpcm_state* nocapture %state) nounwind {
 entry:
-	%0 = getelementptr %struct.adpcm_state* %state, i32 0, i32 0		; <i16*> [#uses=2]
-	%1 = load i16* %0, align 2		; <i16> [#uses=1]
+	%0 = getelementptr %struct.adpcm_state, %struct.adpcm_state* %state, i32 0, i32 0		; <i16*> [#uses=2]
+	%1 = load i16, i16* %0, align 2		; <i16> [#uses=1]
 	%2 = sext i16 %1 to i32		; <i32> [#uses=2]
-	%3 = getelementptr %struct.adpcm_state* %state, i32 0, i32 1		; <i8*> [#uses=2]
-	%4 = load i8* %3, align 2		; <i8> [#uses=1]
+	%3 = getelementptr %struct.adpcm_state, %struct.adpcm_state* %state, i32 0, i32 1		; <i8*> [#uses=2]
+	%4 = load i8, i8* %3, align 2		; <i8> [#uses=1]
 	%5 = sext i8 %4 to i32		; <i32> [#uses=3]
-	%6 = getelementptr [89 x i32]* @stepsizeTable, i32 0, i32 %5		; <i32*> [#uses=1]
-	%7 = load i32* %6, align 4		; <i32> [#uses=1]
+	%6 = getelementptr [89 x i32], [89 x i32]* @stepsizeTable, i32 0, i32 %5		; <i32*> [#uses=1]
+	%7 = load i32, i32* %6, align 4		; <i32> [#uses=1]
 	%8 = icmp sgt i32 %len, 0		; <i1> [#uses=1]
 	br i1 %8, label %bb, label %bb27
 
@@ -34,8 +34,8 @@ bb:		; preds = %bb25, %entry
 	%index.033 = phi i32 [ %5, %entry ], [ %index.2, %bb25 ]		; <i32> [#uses=1]
 	%valpred.132 = phi i32 [ %2, %entry ], [ %valpred.2, %bb25 ]		; <i32> [#uses=2]
 	%step.031 = phi i32 [ %7, %entry ], [ %36, %bb25 ]		; <i32> [#uses=5]
-	%inp.038 = getelementptr i16* %indata, i32 %indvar		; <i16*> [#uses=1]
-	%9 = load i16* %inp.038, align 2		; <i16> [#uses=1]
+	%inp.038 = getelementptr i16, i16* %indata, i32 %indvar		; <i16*> [#uses=1]
+	%9 = load i16, i16* %inp.038, align 2		; <i16> [#uses=1]
 	%10 = sext i16 %9 to i32		; <i32> [#uses=1]
 	%11 = sub i32 %10, %valpred.132		; <i32> [#uses=3]
 	%12 = icmp slt i32 %11, 0		; <i1> [#uses=1]
@@ -79,15 +79,15 @@ bb18:		; preds = %bb17, %bb16, %bb
 	%delta.1 = or i32 %21, %iftmp.1.0		; <i32> [#uses=1]
 	%delta.2 = or i32 %delta.1, %25		; <i32> [#uses=1]
 	%29 = xor i32 %delta.2, 1		; <i32> [#uses=3]
-	%30 = getelementptr [16 x i32]* @indexTable, i32 0, i32 %29		; <i32*> [#uses=1]
-	%31 = load i32* %30, align 4		; <i32> [#uses=1]
+	%30 = getelementptr [16 x i32], [16 x i32]* @indexTable, i32 0, i32 %29		; <i32*> [#uses=1]
+	%31 = load i32, i32* %30, align 4		; <i32> [#uses=1]
 	%32 = add i32 %31, %index.033		; <i32> [#uses=2]
 	%33 = icmp slt i32 %32, 0		; <i1> [#uses=1]
 	%index.1 = select i1 %33, i32 0, i32 %32		; <i32> [#uses=2]
 	%34 = icmp sgt i32 %index.1, 88		; <i1> [#uses=1]
 	%index.2 = select i1 %34, i32 88, i32 %index.1		; <i32> [#uses=3]
-	%35 = getelementptr [89 x i32]* @stepsizeTable, i32 0, i32 %index.2		; <i32*> [#uses=1]
-	%36 = load i32* %35, align 4		; <i32> [#uses=1]
+	%35 = getelementptr [89 x i32], [89 x i32]* @stepsizeTable, i32 0, i32 %index.2		; <i32*> [#uses=1]
+	%36 = load i32, i32* %35, align 4		; <i32> [#uses=1]
 	%37 = icmp eq i32 %bufferstep.035, 0		; <i1> [#uses=1]
 	br i1 %37, label %bb24, label %bb23
 
@@ -102,7 +102,7 @@ bb24:		; preds = %bb18
 	%42 = trunc i32 %outputbuffer.134 to i8		; <i8> [#uses=1]
 	%43 = or i8 %41, %42		; <i8> [#uses=1]
 	store i8 %43, i8* %outp.136, align 1
-	%44 = getelementptr i8* %outp.136, i32 1		; <i8*> [#uses=1]
+	%44 = getelementptr i8, i8* %outp.136, i32 1		; <i8*> [#uses=1]
 	br label %bb25
 
 bb25:		; preds = %bb24, %bb23
@@ -140,14 +140,14 @@ bb29:		; preds = %bb28, %bb27
 
 define void @adpcm_decoder(i8* nocapture %indata, i16* nocapture %outdata, i32 %len, %struct.adpcm_state* nocapture %state) nounwind {
 entry:
-	%0 = getelementptr %struct.adpcm_state* %state, i32 0, i32 0		; <i16*> [#uses=2]
-	%1 = load i16* %0, align 2		; <i16> [#uses=1]
+	%0 = getelementptr %struct.adpcm_state, %struct.adpcm_state* %state, i32 0, i32 0		; <i16*> [#uses=2]
+	%1 = load i16, i16* %0, align 2		; <i16> [#uses=1]
 	%2 = sext i16 %1 to i32		; <i32> [#uses=2]
-	%3 = getelementptr %struct.adpcm_state* %state, i32 0, i32 1		; <i8*> [#uses=2]
-	%4 = load i8* %3, align 2		; <i8> [#uses=1]
+	%3 = getelementptr %struct.adpcm_state, %struct.adpcm_state* %state, i32 0, i32 1		; <i8*> [#uses=2]
+	%4 = load i8, i8* %3, align 2		; <i8> [#uses=1]
 	%5 = sext i8 %4 to i32		; <i32> [#uses=3]
-	%6 = getelementptr [89 x i32]* @stepsizeTable, i32 0, i32 %5		; <i32*> [#uses=1]
-	%7 = load i32* %6, align 4		; <i32> [#uses=1]
+	%6 = getelementptr [89 x i32], [89 x i32]* @stepsizeTable, i32 0, i32 %5		; <i32*> [#uses=1]
+	%7 = load i32, i32* %6, align 4		; <i32> [#uses=1]
 	%8 = icmp sgt i32 %len, 0		; <i1> [#uses=1]
 	br i1 %8, label %bb, label %bb22
 
@@ -159,14 +159,14 @@ bb:		; preds = %bb20, %entry
 	%index.026 = phi i32 [ %5, %entry ], [ %index.2, %bb20 ]		; <i32> [#uses=1]
 	%valpred.125 = phi i32 [ %2, %entry ], [ %valpred.2, %bb20 ]		; <i32> [#uses=1]
 	%step.024 = phi i32 [ %7, %entry ], [ %35, %bb20 ]		; <i32> [#uses=4]
-	%outp.030 = getelementptr i16* %outdata, i32 %indvar		; <i16*> [#uses=1]
+	%outp.030 = getelementptr i16, i16* %outdata, i32 %indvar		; <i16*> [#uses=1]
 	%9 = icmp eq i32 %bufferstep.028, 0		; <i1> [#uses=1]
 	br i1 %9, label %bb2, label %bb3
 
 bb2:		; preds = %bb
-	%10 = load i8* %inp.131, align 1		; <i8> [#uses=1]
+	%10 = load i8, i8* %inp.131, align 1		; <i8> [#uses=1]
 	%11 = sext i8 %10 to i32		; <i32> [#uses=2]
-	%12 = getelementptr i8* %inp.131, i32 1		; <i8*> [#uses=1]
+	%12 = getelementptr i8, i8* %inp.131, i32 1		; <i8*> [#uses=1]
 	%13 = ashr i32 %11, 4		; <i32> [#uses=1]
 	br label %bb3
 
@@ -176,8 +176,8 @@ bb3:		; preds = %bb2, %bb
 	%inp.0 = phi i8* [ %12, %bb2 ], [ %inp.131, %bb ]		; <i8*> [#uses=1]
 	%delta.0 = and i32 %delta.0.in, 15		; <i32> [#uses=1]
 	%tmp = xor i32 %bufferstep.028, 1		; <i32> [#uses=1]
-	%14 = getelementptr [16 x i32]* @indexTable, i32 0, i32 %delta.0		; <i32*> [#uses=1]
-	%15 = load i32* %14, align 4		; <i32> [#uses=1]
+	%14 = getelementptr [16 x i32], [16 x i32]* @indexTable, i32 0, i32 %delta.0		; <i32*> [#uses=1]
+	%15 = load i32, i32* %14, align 4		; <i32> [#uses=1]
 	%16 = add i32 %15, %index.026		; <i32> [#uses=2]
 	%17 = icmp slt i32 %16, 0		; <i1> [#uses=1]
 	%index.1 = select i1 %17, i32 0, i32 %16		; <i32> [#uses=2]
@@ -227,8 +227,8 @@ bb19:		; preds = %bb18
 
 bb20:		; preds = %bb19, %bb18, %bb13
 	%valpred.2 = phi i32 [ -32768, %bb19 ], [ 32767, %bb13 ], [ %valpred.0, %bb18 ]		; <i32> [#uses=3]
-	%34 = getelementptr [89 x i32]* @stepsizeTable, i32 0, i32 %index.2		; <i32*> [#uses=1]
-	%35 = load i32* %34, align 4		; <i32> [#uses=1]
+	%34 = getelementptr [89 x i32], [89 x i32]* @stepsizeTable, i32 0, i32 %index.2		; <i32*> [#uses=1]
+	%35 = load i32, i32* %34, align 4		; <i32> [#uses=1]
 	%36 = trunc i32 %valpred.2 to i16		; <i16> [#uses=1]
 	store i16 %36, i16* %outp.030, align 2
 	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=2]
@@ -250,12 +250,12 @@ entry:
 	br label %bb
 
 bb:		; preds = %bb3, %entry
-	%0 = tail call  i32 (...)* @read(i32 0, i8* getelementptr ([500 x i8]* @abuf, i32 0, i32 0), i32 500) nounwind		; <i32> [#uses=4]
+	%0 = tail call  i32 (...) @read(i32 0, i8* getelementptr ([500 x i8], [500 x i8]* @abuf, i32 0, i32 0), i32 500) nounwind		; <i32> [#uses=4]
 	%1 = icmp slt i32 %0, 0		; <i1> [#uses=1]
 	br i1 %1, label %bb1, label %bb2
 
 bb1:		; preds = %bb
-	tail call  void @perror(i8* getelementptr ([11 x i8]* @.str, i32 0, i32 0)) nounwind
+	tail call  void @perror(i8* getelementptr ([11 x i8], [11 x i8]* @.str, i32 0, i32 0)) nounwind
 	ret i32 1
 
 bb2:		; preds = %bb
@@ -264,18 +264,18 @@ bb2:		; preds = %bb
 
 bb3:		; preds = %bb2
 	%3 = shl i32 %0, 1		; <i32> [#uses=1]
-	tail call  void @adpcm_decoder(i8* getelementptr ([500 x i8]* @abuf, i32 0, i32 0), i16* getelementptr ([1000 x i16]* @sbuf, i32 0, i32 0), i32 %3, %struct.adpcm_state* @state) nounwind
+	tail call  void @adpcm_decoder(i8* getelementptr ([500 x i8], [500 x i8]* @abuf, i32 0, i32 0), i16* getelementptr ([1000 x i16], [1000 x i16]* @sbuf, i32 0, i32 0), i32 %3, %struct.adpcm_state* @state) nounwind
 	%4 = shl i32 %0, 2		; <i32> [#uses=1]
-	%5 = tail call  i32 (...)* @write(i32 1, i16* getelementptr ([1000 x i16]* @sbuf, i32 0, i32 0), i32 %4) nounwind		; <i32> [#uses=0]
+	%5 = tail call  i32 (...) @write(i32 1, i16* getelementptr ([1000 x i16], [1000 x i16]* @sbuf, i32 0, i32 0), i32 %4) nounwind		; <i32> [#uses=0]
 	br label %bb
 
 bb4:		; preds = %bb2
-	%6 = load %struct.FILE** @__stderrp, align 4		; <%struct.FILE*> [#uses=1]
-	%7 = load i16* getelementptr (%struct.adpcm_state* @state, i32 0, i32 0), align 4		; <i16> [#uses=1]
+	%6 = load %struct.FILE*, %struct.FILE** @__stderrp, align 4		; <%struct.FILE*> [#uses=1]
+	%7 = load i16, i16* getelementptr (%struct.adpcm_state, %struct.adpcm_state* @state, i32 0, i32 0), align 4		; <i16> [#uses=1]
 	%8 = sext i16 %7 to i32		; <i32> [#uses=1]
-	%9 = load i8* getelementptr (%struct.adpcm_state* @state, i32 0, i32 1), align 2		; <i8> [#uses=1]
+	%9 = load i8, i8* getelementptr (%struct.adpcm_state, %struct.adpcm_state* @state, i32 0, i32 1), align 2		; <i8> [#uses=1]
 	%10 = sext i8 %9 to i32		; <i32> [#uses=1]
-	%11 = tail call  i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %6, i8* getelementptr ([28 x i8]* @.str1, i32 0, i32 0), i32 %8, i32 %10) nounwind		; <i32> [#uses=0]
+	%11 = tail call  i32 (%struct.FILE*, i8*, ...) @fprintf(%struct.FILE* %6, i8* getelementptr ([28 x i8], [28 x i8]* @.str1, i32 0, i32 0), i32 %8, i32 %10) nounwind		; <i32> [#uses=0]
 	ret i32 0
 }
 
diff --git a/test/CodeGen/Thumb/cortex-m0-unaligned-access.ll b/test/CodeGen/Thumb/cortex-m0-unaligned-access.ll
index c4403fe7efe6..cba1ca68569f 100644
--- a/test/CodeGen/Thumb/cortex-m0-unaligned-access.ll
+++ b/test/CodeGen/Thumb/cortex-m0-unaligned-access.ll
@@ -8,6 +8,6 @@ define i32 @split_load(i32* %p) nounwind {
 ; V7M-LABEL: split_load
 ; V7M-NOT: ldrh
 ; V7M: bx lr
-  %val = load i32* %p, align 2
+  %val = load i32, i32* %p, align 2
   ret i32 %val
 }
diff --git a/test/CodeGen/Thumb/dyn-stackalloc.ll b/test/CodeGen/Thumb/dyn-stackalloc.ll
index 309d80217c11..c94c904e4cd2 100644
--- a/test/CodeGen/Thumb/dyn-stackalloc.ll
+++ b/test/CodeGen/Thumb/dyn-stackalloc.ll
@@ -12,7 +12,7 @@ define void @t1(%struct.state* %v) {
 ; CHECK: mov r[[R1:[0-9]+]], sp
 ; CHECK: subs r[[R2:[0-9]+]], r[[R1]], r[[R0]]
 ; CHECK: mov sp, r[[R2]]
-	%tmp6 = load i32* null
+	%tmp6 = load i32, i32* null
 	%tmp8 = alloca float, i32 %tmp6
 	store i32 1, i32* null
 	br i1 false, label %bb123.preheader, label %return
@@ -22,8 +22,8 @@ bb123.preheader:
 
 bb43:
 	call fastcc void @f1( float* %tmp8, float* null, i32 0 )
-	%tmp70 = load i32* null
-	%tmp85 = getelementptr float* %tmp8, i32 0
+	%tmp70 = load i32, i32* null
+	%tmp85 = getelementptr float, float* %tmp8, i32 0
 	call fastcc void @f2( float* null, float* null, float* %tmp85, i32 %tmp70 )
 	ret void
 
@@ -60,8 +60,8 @@ define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) {
 	%tmp6 = alloca i8, i32 %tmp5
 	%tmp9 = call i8* @strcpy( i8* %tmp6, i8* %tag )
 	%tmp6.len = call i32 @strlen( i8* %tmp6 )
-	%tmp6.indexed = getelementptr i8* %tmp6, i32 %tmp6.len
-	call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp6.indexed, i8* getelementptr inbounds ([2 x i8]* @str215, i32 0, i32 0), i32 2, i32 1, i1 false)
+	%tmp6.indexed = getelementptr i8, i8* %tmp6, i32 %tmp6.len
+	call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp6.indexed, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str215, i32 0, i32 0), i32 2, i32 1, i1 false)
 	%tmp15 = call i8* @strcat( i8* %tmp6, i8* %contents )
 	call fastcc void @comment_add( %struct.comment* %vc, i8* %tmp6 )
 	ret void
diff --git a/test/CodeGen/Thumb/large-stack.ll b/test/CodeGen/Thumb/large-stack.ll
index 269bdd938d0a..0d534589ae0a 100644
--- a/test/CodeGen/Thumb/large-stack.ll
+++ b/test/CodeGen/Thumb/large-stack.ll
@@ -56,7 +56,7 @@ define i32 @test3() {
     %tmp = alloca i32, align 4
     %a = alloca [805306369 x i8], align 16
     store i32 0, i32* %tmp
-    %tmp1 = load i32* %tmp
+    %tmp1 = load i32, i32* %tmp
     ret i32 %tmp1
 }
 
diff --git a/test/CodeGen/Thumb/ldm-merge-call.ll b/test/CodeGen/Thumb/ldm-merge-call.ll
index febc96b07ce6..eb7852934726 100644
--- a/test/CodeGen/Thumb/ldm-merge-call.ll
+++ b/test/CodeGen/Thumb/ldm-merge-call.ll
@@ -8,9 +8,9 @@ entry:
 ; CHECK-LABEL: foo:
 ; CHECK: ldm r[[BASE:[0-9]]]!,
 ; CHECK-NEXT: mov r[[BASE]],
-  %0 = load i32* %A, align 4
-  %arrayidx1 = getelementptr inbounds i32* %A, i32 1
-  %1 = load i32* %arrayidx1, align 4
+  %0 = load i32, i32* %A, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i32 1
+  %1 = load i32, i32* %arrayidx1, align 4
   %call = tail call i32 @bar(i32 %0, i32 %1, i32 %0, i32 %1) #2
   %call2 = tail call i32 @bar(i32 %0, i32 %1, i32 %0, i32 %1) #2
   ret void
diff --git a/test/CodeGen/Thumb/ldm-merge-struct.ll b/test/CodeGen/Thumb/ldm-merge-struct.ll
index 2f732e00bf74..9815a9e505f1 100644
--- a/test/CodeGen/Thumb/ldm-merge-struct.ll
+++ b/test/CodeGen/Thumb/ldm-merge-struct.ll
@@ -11,8 +11,8 @@ entry:
 ; CHECK-LABEL: f:
 ; CHECK: ldm r[[BASE:[0-9]]],
 ; CHECK-NEXT-NOT: subs r[[BASE]]
-  %0 = load i32* getelementptr inbounds (%struct.S* @s, i32 0, i32 0), align 4
-  %1 = load i32* getelementptr inbounds (%struct.S* @s, i32 0, i32 1), align 4
+  %0 = load i32, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 0), align 4
+  %1 = load i32, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1), align 4
   %cmp = icmp sgt i32 %0, %1
   %2 = sub i32 0, %1
   %cond.p = select i1 %cmp, i32 %1, i32 %2
diff --git a/test/CodeGen/Thumb/ldm-stm-base-materialization.ll b/test/CodeGen/Thumb/ldm-stm-base-materialization.ll
index 6382c25b60fe..916e5ea299a3 100644
--- a/test/CodeGen/Thumb/ldm-stm-base-materialization.ll
+++ b/test/CodeGen/Thumb/ldm-stm-base-materialization.ll
@@ -15,11 +15,11 @@ entry:
 ; CHECK-NEXT: ldm r[[NLB]],
 ; CHECK: adds r[[NSB:[0-9]]], r[[SB]], #4
 ; CHECK-NEXT: stm r[[NSB]]
-  %0 = load i32** @a, align 4
-  %arrayidx = getelementptr inbounds i32* %0, i32 1
+  %0 = load i32*, i32** @a, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %0, i32 1
   %1 = bitcast i32* %arrayidx to i8*
-  %2 = load i32** @b, align 4
-  %arrayidx1 = getelementptr inbounds i32* %2, i32 1
+  %2 = load i32*, i32** @b, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %2, i32 1
   %3 = bitcast i32* %arrayidx1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %1, i8* %3, i32 24, i32 4, i1 false)
   ret void
diff --git a/test/CodeGen/Thumb/ldr_ext.ll b/test/CodeGen/Thumb/ldr_ext.ll
index 2d25af35b513..90194aecec97 100644
--- a/test/CodeGen/Thumb/ldr_ext.ll
+++ b/test/CodeGen/Thumb/ldr_ext.ll
@@ -7,7 +7,7 @@ define i32 @test1(i8* %t1) nounwind {
 ; V5: ldrb
 
 ; V6: ldrb
-    %tmp.u = load i8* %t1
+    %tmp.u = load i8, i8* %t1
     %tmp1.s = zext i8 %tmp.u to i32
     ret i32 %tmp1.s
 }
@@ -16,7 +16,7 @@ define i32 @test2(i16* %t1) nounwind {
 ; V5: ldrh
 
 ; V6: ldrh
-    %tmp.u = load i16* %t1
+    %tmp.u = load i16, i16* %t1
     %tmp1.s = zext i16 %tmp.u to i32
     ret i32 %tmp1.s
 }
@@ -28,7 +28,7 @@ define i32 @test3(i8* %t0) nounwind {
 
 ; V6: ldrb
 ; V6: sxtb
-    %tmp.s = load i8* %t0
+    %tmp.s = load i8, i8* %t0
     %tmp1.s = sext i8 %tmp.s to i32
     ret i32 %tmp1.s
 }
@@ -40,7 +40,7 @@ define i32 @test4(i16* %t0) nounwind {
 
 ; V6: ldrh
 ; V6: sxth
-    %tmp.s = load i16* %t0
+    %tmp.s = load i16, i16* %t0
     %tmp1.s = sext i16 %tmp.s to i32
     ret i32 %tmp1.s
 }
@@ -51,7 +51,7 @@ define i32 @test5() nounwind {
 
 ; V6: movs r0, #0
 ; V6: ldrsh
-    %tmp.s = load i16* null
+    %tmp.s = load i16, i16* null
     %tmp1.s = sext i16 %tmp.s to i32
     ret i32 %tmp1.s
 }
diff --git a/test/CodeGen/Thumb/ldr_frame.ll b/test/CodeGen/Thumb/ldr_frame.ll
index 0e879d7379a8..fdcf3b7678e5 100644
--- a/test/CodeGen/Thumb/ldr_frame.ll
+++ b/test/CodeGen/Thumb/ldr_frame.ll
@@ -4,8 +4,8 @@ define i32 @f1() {
 ; CHECK-LABEL: f1:
 ; CHECK: ldr r0
 	%buf = alloca [32 x i32], align 4
-	%tmp = getelementptr [32 x i32]* %buf, i32 0, i32 0
-	%tmp1 = load i32* %tmp
+	%tmp = getelementptr [32 x i32], [32 x i32]* %buf, i32 0, i32 0
+	%tmp1 = load i32, i32* %tmp
 	ret i32 %tmp1
 }
 
@@ -14,8 +14,8 @@ define i32 @f2() {
 ; CHECK: mov r0
 ; CHECK: ldrb
 	%buf = alloca [32 x i8], align 4
-	%tmp = getelementptr [32 x i8]* %buf, i32 0, i32 0
-	%tmp1 = load i8* %tmp
+	%tmp = getelementptr [32 x i8], [32 x i8]* %buf, i32 0, i32 0
+	%tmp1 = load i8, i8* %tmp
         %tmp2 = zext i8 %tmp1 to i32
 	ret i32 %tmp2
 }
@@ -24,8 +24,8 @@ define i32 @f3() {
 ; CHECK-LABEL: f3:
 ; CHECK: ldr r0
 	%buf = alloca [32 x i32], align 4
-	%tmp = getelementptr [32 x i32]* %buf, i32 0, i32 32
-	%tmp1 = load i32* %tmp
+	%tmp = getelementptr [32 x i32], [32 x i32]* %buf, i32 0, i32 32
+	%tmp1 = load i32, i32* %tmp
 	ret i32 %tmp1
 }
 
@@ -34,8 +34,8 @@ define i32 @f4() {
 ; CHECK: mov r0
 ; CHECK: ldrb
 	%buf = alloca [32 x i8], align 4
-	%tmp = getelementptr [32 x i8]* %buf, i32 0, i32 2
-	%tmp1 = load i8* %tmp
+	%tmp = getelementptr [32 x i8], [32 x i8]* %buf, i32 0, i32 2
+	%tmp1 = load i8, i8* %tmp
         %tmp2 = zext i8 %tmp1 to i32
 	ret i32 %tmp2
 }
diff --git a/test/CodeGen/Thumb/long.ll b/test/CodeGen/Thumb/long.ll
index 2449e5ad6777..33f63892ec3f 100644
--- a/test/CodeGen/Thumb/long.ll
+++ b/test/CodeGen/Thumb/long.ll
@@ -65,7 +65,7 @@ entry:
 define i64 @f10() {
 entry:
         %a = alloca i64, align 8                ; <i64*> [#uses=1]
-        %retval = load i64* %a          ; <i64> [#uses=1]
+        %retval = load i64, i64* %a          ; <i64> [#uses=1]
         ret i64 %retval
 }
 
diff --git a/test/CodeGen/Thumb/segmented-stacks.ll b/test/CodeGen/Thumb/segmented-stacks.ll
index d6e25c7792e8..09f5db852bf4 100644
--- a/test/CodeGen/Thumb/segmented-stacks.ll
+++ b/test/CodeGen/Thumb/segmented-stacks.ll
@@ -55,7 +55,7 @@ define void @test_basic() #0 {
 }
 
 define i32 @test_nested(i32 * nest %closure, i32 %other) #0 {
-       %addend = load i32 * %closure
+       %addend = load i32 , i32 * %closure
        %result = add i32 %other, %addend
        %mem = alloca i32, i32 10
        call void @dummy_use (i32* %mem, i32 10)
diff --git a/test/CodeGen/Thumb/stack-access.ll b/test/CodeGen/Thumb/stack-access.ll
new file mode 100644
index 000000000000..fded4104207c
--- /dev/null
+++ b/test/CodeGen/Thumb/stack-access.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=thumb-eabi < %s -o - | FileCheck %s
+
+; Check that stack addresses are generated using a single ADD
+define void @test1(i8** %p) {
+  %x = alloca i8, align 1
+  %y = alloca i8, align 1
+  %z = alloca i8, align 1
+; CHECK: add r1, sp, #8
+; CHECK: str r1, [r0]
+  store i8* %x, i8** %p, align 4
+; CHECK: add r1, sp, #4
+; CHECK: str r1, [r0]
+  store i8* %y, i8** %p, align 4
+; CHECK: mov r1, sp
+; CHECK: str r1, [r0]
+  store i8* %z, i8** %p, align 4
+  ret void
+}
+
+; Stack offsets larger than 1020 still need two ADDs
+define void @test2([1024 x i8]** %p) {
+  %arr1 = alloca [1024 x i8], align 1
+  %arr2 = alloca [1024 x i8], align 1
+; CHECK: add r1, sp, #1020
+; CHECK: adds r1, #4
+; CHECK: str r1, [r0]
+  store [1024 x i8]* %arr1, [1024 x i8]** %p, align 4
+; CHECK: mov r1, sp
+; CHECK: str r1, [r0]
+  store [1024 x i8]* %arr2, [1024 x i8]** %p, align 4
+  ret void
+}
+
+; If possible stack-based lrdb/ldrh are widened to use SP-based addressing
+define i32 @test3() #0 {
+  %x = alloca i8, align 1
+  %y = alloca i8, align 1
+; CHECK: ldr r0, [sp]
+  %1 = load i8, i8* %x, align 1
+; CHECK: ldr r1, [sp, #4]
+  %2 = load i8, i8* %y, align 1
+  %3 = add nsw i8 %1, %2
+  %4 = zext i8 %3 to i32
+  ret i32 %4
+}
+
+define i32 @test4() #0 {
+  %x = alloca i16, align 2
+  %y = alloca i16, align 2
+; CHECK: ldr r0, [sp]
+  %1 = load i16, i16* %x, align 2
+; CHECK: ldr r1, [sp, #4]
+  %2 = load i16, i16* %y, align 2
+  %3 = add nsw i16 %1, %2
+  %4 = zext i16 %3 to i32
+  ret i32 %4
+}
+
+; Don't widen if the value needs to be zero-extended
+define zeroext i8 @test5() {
+  %x = alloca i8, align 1
+; CHECK: mov r0, sp
+; CHECK: ldrb r0, [r0]
+  %1 = load i8, i8* %x, align 1
+  ret i8 %1
+}
+
+define zeroext i16 @test6() {
+  %x = alloca i16, align 2
+; CHECK: mov r0, sp
+; CHECK: ldrh r0, [r0]
+  %1 = load i16, i16* %x, align 2
+  ret i16 %1
+}
+
+; Accessing the bottom of a large array shouldn't require materializing a base
+define void @test7() {
+  %arr = alloca [200 x i32], align 4
+
+  ; CHECK: movs [[REG:r[0-9]+]], #1
+  ; CHECK: str [[REG]], [sp, #4]
+  %arrayidx = getelementptr inbounds [200 x i32], [200 x i32]* %arr, i32 0, i32 1
+  store i32 1, i32* %arrayidx, align 4
+
+  ; CHECK: str [[REG]], [sp, #16]
+  %arrayidx1 = getelementptr inbounds [200 x i32], [200 x i32]* %arr, i32 0, i32 4
+  store i32 1, i32* %arrayidx1, align 4
+
+  ret void
+}
+
+; Check that loads/stores with out-of-range offsets are handled correctly
+define void @test8() {
+  %arr3 = alloca [224 x i32], align 4
+  %arr2 = alloca [224 x i32], align 4
+  %arr1 = alloca [224 x i32], align 4
+
+; CHECK: movs [[REG:r[0-9]+]], #1
+; CHECK: str [[REG]], [sp]
+  %arr1idx1 = getelementptr inbounds [224 x i32], [224 x i32]* %arr1, i32 0, i32 0
+  store i32 1, i32* %arr1idx1, align 4
+
+; Offset in range for sp-based store, but not for non-sp-based store
+; CHECK: str [[REG]], [sp, #128]
+  %arr1idx2 = getelementptr inbounds [224 x i32], [224 x i32]* %arr1, i32 0, i32 32
+  store i32 1, i32* %arr1idx2, align 4
+
+; CHECK: str [[REG]], [sp, #896]
+  %arr2idx1 = getelementptr inbounds [224 x i32], [224 x i32]* %arr2, i32 0, i32 0
+  store i32 1, i32* %arr2idx1, align 4
+
+; %arr2 is in range, but this element of it is not
+; CHECK: str [[REG]], [{{r[0-9]+}}]
+  %arr2idx2 = getelementptr inbounds [224 x i32], [224 x i32]* %arr2, i32 0, i32 32
+  store i32 1, i32* %arr2idx2, align 4
+
+; %arr3 is not in range
+; CHECK: str [[REG]], [{{r[0-9]+}}]
+  %arr3idx1 = getelementptr inbounds [224 x i32], [224 x i32]* %arr3, i32 0, i32 0
+  store i32 1, i32* %arr3idx1, align 4
+
+; CHECK: str [[REG]], [{{r[0-9]+}}]
+  %arr3idx2 = getelementptr inbounds [224 x i32], [224 x i32]* %arr3, i32 0, i32 32
+  store i32 1, i32* %arr3idx2, align 4
+
+  ret void
+}
diff --git a/test/CodeGen/Thumb/stack_guard_remat.ll b/test/CodeGen/Thumb/stack_guard_remat.ll
index e949cc181f15..41edef5a58e6 100644
--- a/test/CodeGen/Thumb/stack_guard_remat.ll
+++ b/test/CodeGen/Thumb/stack_guard_remat.ll
@@ -28,7 +28,7 @@ define i32 @test_stack_guard_remat() #0 {
   %a1 = alloca [256 x i32], align 4
   %1 = bitcast [256 x i32]* %a1 to i8*
   call void @llvm.lifetime.start(i64 1024, i8* %1)
-  %2 = getelementptr inbounds [256 x i32]* %a1, i32 0, i32 0
+  %2 = getelementptr inbounds [256 x i32], [256 x i32]* %a1, i32 0, i32 0
   call void @foo3(i32* %2) #3
   call void asm sideeffect "foo2", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{sp},~{lr}"()
   call void @llvm.lifetime.end(i64 1024, i8* %1)
diff --git a/test/CodeGen/Thumb/stm-merge.ll b/test/CodeGen/Thumb/stm-merge.ll
index 76e71f4da652..5492ad8f5121 100644
--- a/test/CodeGen/Thumb/stm-merge.ll
+++ b/test/CodeGen/Thumb/stm-merge.ll
@@ -7,17 +7,18 @@ target triple = "thumbv6m--linux-gnueabi"
 @e = internal unnamed_addr global i32* null, align 4
 
 ; Function Attrs: nounwind optsize
-define void @fn1() #0 {
+define void @fn1(i32 %x, i32 %y, i32 %z) #0 {
 entry:
 ; CHECK-LABEL: fn1:
 ; CHECK: stm r[[BASE:[0-9]]]!, {{.*}}
 ; CHECK-NOT: {{.*}} r[[BASE]]
-; CHECK: ldr r[[BASE]], {{.*}}
   %g = alloca i32, align 4
   %h = alloca i32, align 4
-  store i32 1, i32* %g, align 4
-  store i32 0, i32* %h, align 4
-  %.pr = load i32* @d, align 4
+  %i = alloca i32, align 4
+  store i32 %x, i32* %i, align 4
+  store i32 %y, i32* %h, align 4
+  store i32 %z, i32* %g, align 4
+  %.pr = load i32, i32* @d, align 4
   %cmp11 = icmp slt i32 %.pr, 1
   br i1 %cmp11, label %for.inc.lr.ph, label %for.body5
 
diff --git a/test/CodeGen/Thumb/thumb-ldm.ll b/test/CodeGen/Thumb/thumb-ldm.ll
index 7e9560eec8d5..8c49669943ce 100644
--- a/test/CodeGen/Thumb/thumb-ldm.ll
+++ b/test/CodeGen/Thumb/thumb-ldm.ll
@@ -7,8 +7,8 @@ define i32 @t1() {
 ; CHECK: push {r7, lr}
 ; CHECK: ldm
 ; CHECK: pop {r7, pc}
-        %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0)            ; <i32> [#uses=1]
-        %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1)           ; <i32> [#uses=1]
+        %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 0)            ; <i32> [#uses=1]
+        %tmp3 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 1)           ; <i32> [#uses=1]
         %tmp4 = call i32 @f1( i32 %tmp, i32 %tmp3 )                ; <i32> [#uses=1]
         ret i32 %tmp4
 }
@@ -18,9 +18,9 @@ define i32 @t2() {
 ; CHECK: push {r7, lr}
 ; CHECK: ldm
 ; CHECK: pop {r7, pc}
-        %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2)            ; <i32> [#uses=1]
-        %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3)           ; <i32> [#uses=1]
-        %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4)           ; <i32> [#uses=1]
+        %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 2)            ; <i32> [#uses=1]
+        %tmp3 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 3)           ; <i32> [#uses=1]
+        %tmp5 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 4)           ; <i32> [#uses=1]
         %tmp6 = call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 )             ; <i32> [#uses=1]
         ret i32 %tmp6
 }
@@ -30,9 +30,9 @@ define i32 @t3() {
 ; CHECK: push {r7, lr}
 ; CHECK: ldm
 ; CHECK: pop {r7, pc}
-        %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1)            ; <i32> [#uses=1]
-        %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2)           ; <i32> [#uses=1]
-        %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3)           ; <i32> [#uses=1]
+        %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 1)            ; <i32> [#uses=1]
+        %tmp3 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 2)           ; <i32> [#uses=1]
+        %tmp5 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 3)           ; <i32> [#uses=1]
         %tmp6 = call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 )             ; <i32> [#uses=1]
         ret i32 %tmp6
 }
diff --git a/test/CodeGen/Thumb/vargs.ll b/test/CodeGen/Thumb/vargs.ll
index 4078b01ba30c..1c7b631741b7 100644
--- a/test/CodeGen/Thumb/vargs.ll
+++ b/test/CodeGen/Thumb/vargs.ll
@@ -6,6 +6,10 @@
 
 define void @f(i32 %a, ...) {
 entry:
+; Check that space is reserved above the pushed lr for variadic argument
+; registers to be stored in.
+; CHECK: sub sp, #[[IMM:[0-9]+]]
+; CHECK: push
         %va = alloca i8*, align 4               ; <i8**> [#uses=4]
         %va.upgrd.1 = bitcast i8** %va to i8*           ; <i8*> [#uses=1]
         call void @llvm.va_start( i8* %va.upgrd.1 )
@@ -13,8 +17,8 @@ entry:
 
 bb:             ; preds = %bb, %entry
         %a_addr.0 = phi i32 [ %a, %entry ], [ %tmp5, %bb ]              ; <i32> [#uses=2]
-        %tmp = load volatile i8** %va           ; <i8*> [#uses=2]
-        %tmp2 = getelementptr i8* %tmp, i32 4           ; <i8*> [#uses=1]
+        %tmp = load volatile i8*, i8** %va           ; <i8*> [#uses=2]
+        %tmp2 = getelementptr i8, i8* %tmp, i32 4           ; <i8*> [#uses=1]
         store volatile i8* %tmp2, i8** %va
         %tmp5 = add i32 %a_addr.0, -1           ; <i32> [#uses=1]
         %tmp.upgrd.2 = icmp eq i32 %a_addr.0, 1         ; <i1> [#uses=1]
@@ -22,11 +26,18 @@ bb:             ; preds = %bb, %entry
 
 bb7:            ; preds = %bb
         %tmp3 = bitcast i8* %tmp to i32*                ; <i32*> [#uses=1]
-        %tmp.upgrd.3 = load i32* %tmp3          ; <i32> [#uses=1]
-        %tmp10 = call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @str, i32 0, i64 0), i32 %tmp.upgrd.3 )                ; <i32> [#uses=0]
+        %tmp.upgrd.3 = load i32, i32* %tmp3          ; <i32> [#uses=1]
+        %tmp10 = call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @str, i32 0, i64 0), i32 %tmp.upgrd.3 )                ; <i32> [#uses=0]
         %va.upgrd.4 = bitcast i8** %va to i8*           ; <i8*> [#uses=1]
         call void @llvm.va_end( i8* %va.upgrd.4 )
         ret void
+
+; The return sequence should pop the lr to r3, recover the stack space used to
+; store variadic argument registers, then return via r3. Possibly there is a pop
+; before this, but only if the function happened to use callee-saved registers.
+; CHECK: pop {r3}
+; CHECK: add sp, #[[IMM]]
+; CHECK: bx r3
 }
 
 declare void @llvm.va_start(i8*)
@@ -34,8 +45,3 @@ declare void @llvm.va_start(i8*)
 declare i32 @printf(i8*, ...)
 
 declare void @llvm.va_end(i8*)
-
-; CHECK: pop
-; CHECK: pop
-; CHECK-NOT: pop
-
diff --git a/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll b/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll
index 76ffe2a18f19..f76c8ff4d0f8 100644
--- a/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll
+++ b/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll
@@ -17,8 +17,8 @@ bb1:		; preds = %entry
 bb.i:		; preds = %bb.i, %bb1
 	%indvar.i = phi i32 [ 0, %bb1 ], [ %2, %bb.i ]		; <i32> [#uses=3]
 	%tmp39 = add i32 %indvar.i, %tmp38		; <i32> [#uses=1]
-	%p_addr.0.i = getelementptr i8* undef, i32 %tmp39		; <i8*> [#uses=1]
-	%0 = load i8* %p_addr.0.i, align 1		; <i8> [#uses=1]
+	%p_addr.0.i = getelementptr i8, i8* undef, i32 %tmp39		; <i8*> [#uses=1]
+	%0 = load i8, i8* %p_addr.0.i, align 1		; <i8> [#uses=1]
 	%1 = icmp slt i8 %0, 0		; <i1> [#uses=1]
 	%2 = add i32 %indvar.i, 1		; <i32> [#uses=1]
 	br i1 %1, label %bb.i, label %read_uleb128.exit
@@ -26,7 +26,7 @@ bb.i:		; preds = %bb.i, %bb1
 read_uleb128.exit:		; preds = %bb.i
 	%.sum40 = add i32 %indvar.i, undef		; <i32> [#uses=1]
 	%.sum31 = add i32 %.sum40, 2		; <i32> [#uses=1]
-	%scevgep.i = getelementptr %struct.dwarf_cie* %cie, i32 0, i32 3, i32 %.sum31		; <i8*> [#uses=1]
+	%scevgep.i = getelementptr %struct.dwarf_cie, %struct.dwarf_cie* %cie, i32 0, i32 3, i32 %.sum31		; <i8*> [#uses=1]
 	%3 = call  i8* @read_sleb128(i8* %scevgep.i, i32* undef)		; <i8*> [#uses=0]
 	unreachable
 
diff --git a/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll b/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
index 4abeca930c1f..e363a343f0be 100644
--- a/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
+++ b/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
@@ -7,24 +7,24 @@ define i32 @t(i32, ...) nounwind {
 entry:
 ; CHECK-LABEL: t:
 ; CHECK: add r7, sp, #12
-	%1 = load i8** undef, align 4		; <i8*> [#uses=3]
-	%2 = getelementptr i8* %1, i32 4		; <i8*> [#uses=1]
-	%3 = getelementptr i8* %1, i32 8		; <i8*> [#uses=1]
+	%1 = load i8*, i8** undef, align 4		; <i8*> [#uses=3]
+	%2 = getelementptr i8, i8* %1, i32 4		; <i8*> [#uses=1]
+	%3 = getelementptr i8, i8* %1, i32 8		; <i8*> [#uses=1]
 	%4 = bitcast i8* %2 to i32*		; <i32*> [#uses=1]
-	%5 = load i32* %4, align 4		; <i32> [#uses=1]
+	%5 = load i32, i32* %4, align 4		; <i32> [#uses=1]
 	%6 = trunc i32 %5 to i8		; <i8> [#uses=1]
-	%7 = getelementptr i8* %1, i32 12		; <i8*> [#uses=1]
+	%7 = getelementptr i8, i8* %1, i32 12		; <i8*> [#uses=1]
 	%8 = bitcast i8* %3 to i32*		; <i32*> [#uses=1]
-	%9 = load i32* %8, align 4		; <i32> [#uses=1]
+	%9 = load i32, i32* %8, align 4		; <i32> [#uses=1]
 	%10 = trunc i32 %9 to i16		; <i16> [#uses=1]
 	%11 = bitcast i8* %7 to i32*		; <i32*> [#uses=1]
-	%12 = load i32* %11, align 4		; <i32> [#uses=1]
+	%12 = load i32, i32* %11, align 4		; <i32> [#uses=1]
 	%13 = trunc i32 %12 to i16		; <i16> [#uses=1]
-	%14 = load i32* undef, align 4		; <i32> [#uses=2]
+	%14 = load i32, i32* undef, align 4		; <i32> [#uses=2]
 	%15 = sext i8 %6 to i32		; <i32> [#uses=2]
 	%16 = sext i16 %10 to i32		; <i32> [#uses=2]
 	%17 = sext i16 %13 to i32		; <i32> [#uses=2]
-	%18 = call  i32 (i8*, ...)* @printf(i8* getelementptr ([36 x i8]* @"\01LC", i32 0, i32 0), i32 -128, i32 0, i32 %15, i32 %16, i32 %17, i32 0, i32 %14) nounwind		; <i32> [#uses=0]
+	%18 = call  i32 (i8*, ...) @printf(i8* getelementptr ([36 x i8], [36 x i8]* @"\01LC", i32 0, i32 0), i32 -128, i32 0, i32 %15, i32 %16, i32 %17, i32 0, i32 %14) nounwind		; <i32> [#uses=0]
 	%19 = add i32 0, %15		; <i32> [#uses=1]
 	%20 = add i32 %19, %16		; <i32> [#uses=1]
 	%21 = add i32 %20, %14		; <i32> [#uses=1]
diff --git a/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll b/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll
index 3e0761898925..77d2991160d9 100644
--- a/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll
+++ b/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll
@@ -31,35 +31,35 @@
 define void @jpeg_idct_float(%struct.jpeg_decompress_struct* nocapture %cinfo, %struct.jpeg_component_info* nocapture %compptr, i16* nocapture %coef_block, i8** nocapture %output_buf, i32 %output_col) nounwind {
 entry:
 	%workspace = alloca [64 x float], align 4		; <[64 x float]*> [#uses=11]
-	%0 = load i8** undef, align 4		; <i8*> [#uses=5]
+	%0 = load i8*, i8** undef, align 4		; <i8*> [#uses=5]
 	br label %bb
 
 bb:		; preds = %bb, %entry
 	%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]		; <i32> [#uses=11]
 	%tmp39 = add i32 %indvar, 8		; <i32> [#uses=0]
 	%tmp41 = add i32 %indvar, 16		; <i32> [#uses=2]
-	%scevgep42 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp41		; <float*> [#uses=1]
+	%scevgep42 = getelementptr [64 x float], [64 x float]* %workspace, i32 0, i32 %tmp41		; <float*> [#uses=1]
 	%tmp43 = add i32 %indvar, 24		; <i32> [#uses=1]
-	%scevgep44 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp43		; <float*> [#uses=1]
+	%scevgep44 = getelementptr [64 x float], [64 x float]* %workspace, i32 0, i32 %tmp43		; <float*> [#uses=1]
 	%tmp45 = add i32 %indvar, 32		; <i32> [#uses=1]
-	%scevgep46 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp45		; <float*> [#uses=1]
+	%scevgep46 = getelementptr [64 x float], [64 x float]* %workspace, i32 0, i32 %tmp45		; <float*> [#uses=1]
 	%tmp47 = add i32 %indvar, 40		; <i32> [#uses=1]
-	%scevgep48 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp47		; <float*> [#uses=1]
+	%scevgep48 = getelementptr [64 x float], [64 x float]* %workspace, i32 0, i32 %tmp47		; <float*> [#uses=1]
 	%tmp49 = add i32 %indvar, 48		; <i32> [#uses=1]
-	%scevgep50 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp49		; <float*> [#uses=1]
+	%scevgep50 = getelementptr [64 x float], [64 x float]* %workspace, i32 0, i32 %tmp49		; <float*> [#uses=1]
 	%tmp51 = add i32 %indvar, 56		; <i32> [#uses=1]
-	%scevgep52 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp51		; <float*> [#uses=1]
-	%wsptr.119 = getelementptr [64 x float]* %workspace, i32 0, i32 %indvar		; <float*> [#uses=1]
+	%scevgep52 = getelementptr [64 x float], [64 x float]* %workspace, i32 0, i32 %tmp51		; <float*> [#uses=1]
+	%wsptr.119 = getelementptr [64 x float], [64 x float]* %workspace, i32 0, i32 %indvar		; <float*> [#uses=1]
 	%tmp54 = shl i32 %indvar, 2		; <i32> [#uses=1]
-	%scevgep76 = getelementptr i8* undef, i32 %tmp54		; <i8*> [#uses=1]
+	%scevgep76 = getelementptr i8, i8* undef, i32 %tmp54		; <i8*> [#uses=1]
 	%quantptr.118 = bitcast i8* %scevgep76 to float*		; <float*> [#uses=1]
-	%scevgep79 = getelementptr i16* %coef_block, i32 %tmp41		; <i16*> [#uses=0]
-	%inptr.117 = getelementptr i16* %coef_block, i32 %indvar		; <i16*> [#uses=1]
-	%1 = load i16* null, align 2		; <i16> [#uses=1]
-	%2 = load i16* undef, align 2		; <i16> [#uses=1]
-	%3 = load i16* %inptr.117, align 2		; <i16> [#uses=1]
+	%scevgep79 = getelementptr i16, i16* %coef_block, i32 %tmp41		; <i16*> [#uses=0]
+	%inptr.117 = getelementptr i16, i16* %coef_block, i32 %indvar		; <i16*> [#uses=1]
+	%1 = load i16, i16* null, align 2		; <i16> [#uses=1]
+	%2 = load i16, i16* undef, align 2		; <i16> [#uses=1]
+	%3 = load i16, i16* %inptr.117, align 2		; <i16> [#uses=1]
 	%4 = sitofp i16 %3 to float		; <float> [#uses=1]
-	%5 = load float* %quantptr.118, align 4		; <float> [#uses=1]
+	%5 = load float, float* %quantptr.118, align 4		; <float> [#uses=1]
 	%6 = fmul float %4, %5		; <float> [#uses=1]
 	%7 = fsub float %6, undef		; <float> [#uses=2]
 	%8 = fmul float undef, 0x3FF6A09E60000000		; <float> [#uses=1]
@@ -70,7 +70,7 @@ bb:		; preds = %bb, %entry
 	%13 = sitofp i16 %1 to float		; <float> [#uses=1]
 	%14 = fmul float %13, undef		; <float> [#uses=2]
 	%15 = sitofp i16 %2 to float		; <float> [#uses=1]
-	%16 = load float* undef, align 4		; <float> [#uses=1]
+	%16 = load float, float* undef, align 4		; <float> [#uses=1]
 	%17 = fmul float %15, %16		; <float> [#uses=1]
 	%18 = fadd float %14, undef		; <float> [#uses=2]
 	%19 = fsub float %14, undef		; <float> [#uses=2]
@@ -114,22 +114,22 @@ bb6:		; preds = %bb
 
 bb8:		; preds = %bb8, %bb6
 	%ctr.116 = phi i32 [ 0, %bb6 ], [ %88, %bb8 ]		; <i32> [#uses=3]
-	%scevgep = getelementptr i8** %output_buf, i32 %ctr.116		; <i8**> [#uses=1]
+	%scevgep = getelementptr i8*, i8** %output_buf, i32 %ctr.116		; <i8**> [#uses=1]
 	%tmp = shl i32 %ctr.116, 3		; <i32> [#uses=5]
 	%tmp2392 = or i32 %tmp, 4		; <i32> [#uses=1]
-	%scevgep24 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp2392		; <float*> [#uses=1]
+	%scevgep24 = getelementptr [64 x float], [64 x float]* %workspace, i32 0, i32 %tmp2392		; <float*> [#uses=1]
 	%tmp2591 = or i32 %tmp, 2		; <i32> [#uses=1]
-	%scevgep26 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp2591		; <float*> [#uses=1]
+	%scevgep26 = getelementptr [64 x float], [64 x float]* %workspace, i32 0, i32 %tmp2591		; <float*> [#uses=1]
 	%tmp2790 = or i32 %tmp, 6		; <i32> [#uses=1]
-	%scevgep28 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp2790		; <float*> [#uses=1]
+	%scevgep28 = getelementptr [64 x float], [64 x float]* %workspace, i32 0, i32 %tmp2790		; <float*> [#uses=1]
 	%tmp3586 = or i32 %tmp, 7		; <i32> [#uses=0]
-	%wsptr.215 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp		; <float*> [#uses=1]
-	%40 = load i8** %scevgep, align 4		; <i8*> [#uses=4]
-	%41 = load float* %wsptr.215, align 4		; <float> [#uses=1]
-	%42 = load float* %scevgep24, align 4		; <float> [#uses=1]
+	%wsptr.215 = getelementptr [64 x float], [64 x float]* %workspace, i32 0, i32 %tmp		; <float*> [#uses=1]
+	%40 = load i8*, i8** %scevgep, align 4		; <i8*> [#uses=4]
+	%41 = load float, float* %wsptr.215, align 4		; <float> [#uses=1]
+	%42 = load float, float* %scevgep24, align 4		; <float> [#uses=1]
 	%43 = fadd float %41, %42		; <float> [#uses=1]
-	%44 = load float* %scevgep26, align 4		; <float> [#uses=1]
-	%45 = load float* %scevgep28, align 4		; <float> [#uses=1]
+	%44 = load float, float* %scevgep26, align 4		; <float> [#uses=1]
+	%45 = load float, float* %scevgep28, align 4		; <float> [#uses=1]
 	%46 = fadd float %44, %45		; <float> [#uses=1]
 	%47 = fsub float %43, %46		; <float> [#uses=2]
 	%48 = fsub float undef, 0.000000e+00		; <float> [#uses=1]
@@ -139,13 +139,13 @@ bb8:		; preds = %bb8, %bb6
 	%52 = lshr i32 %51, 3		; <i32> [#uses=1]
 	%53 = and i32 %52, 1023		; <i32> [#uses=1]
 	%.sum14 = add i32 %53, 128		; <i32> [#uses=1]
-	%54 = getelementptr i8* %0, i32 %.sum14		; <i8*> [#uses=1]
-	%55 = load i8* %54, align 1		; <i8> [#uses=1]
+	%54 = getelementptr i8, i8* %0, i32 %.sum14		; <i8*> [#uses=1]
+	%55 = load i8, i8* %54, align 1		; <i8> [#uses=1]
 	store i8 %55, i8* null, align 1
-	%56 = getelementptr i8* %40, i32 %.sum10		; <i8*> [#uses=1]
+	%56 = getelementptr i8, i8* %40, i32 %.sum10		; <i8*> [#uses=1]
 	store i8 0, i8* %56, align 1
-	%57 = load i8* null, align 1		; <i8> [#uses=1]
-	%58 = getelementptr i8* %40, i32 %.sum8		; <i8*> [#uses=1]
+	%57 = load i8, i8* null, align 1		; <i8> [#uses=1]
+	%58 = getelementptr i8, i8* %40, i32 %.sum8		; <i8*> [#uses=1]
 	store i8 %57, i8* %58, align 1
 	%59 = fadd float undef, %48		; <float> [#uses=1]
 	%60 = fptosi float %59 to i32		; <i32> [#uses=1]
@@ -153,17 +153,17 @@ bb8:		; preds = %bb8, %bb6
 	%62 = lshr i32 %61, 3		; <i32> [#uses=1]
 	%63 = and i32 %62, 1023		; <i32> [#uses=1]
 	%.sum7 = add i32 %63, 128		; <i32> [#uses=1]
-	%64 = getelementptr i8* %0, i32 %.sum7		; <i8*> [#uses=1]
-	%65 = load i8* %64, align 1		; <i8> [#uses=1]
-	%66 = getelementptr i8* %40, i32 %.sum6		; <i8*> [#uses=1]
+	%64 = getelementptr i8, i8* %0, i32 %.sum7		; <i8*> [#uses=1]
+	%65 = load i8, i8* %64, align 1		; <i8> [#uses=1]
+	%66 = getelementptr i8, i8* %40, i32 %.sum6		; <i8*> [#uses=1]
 	store i8 %65, i8* %66, align 1
 	%67 = fptosi float undef to i32		; <i32> [#uses=1]
 	%68 = add i32 %67, 4		; <i32> [#uses=1]
 	%69 = lshr i32 %68, 3		; <i32> [#uses=1]
 	%70 = and i32 %69, 1023		; <i32> [#uses=1]
 	%.sum5 = add i32 %70, 128		; <i32> [#uses=1]
-	%71 = getelementptr i8* %0, i32 %.sum5		; <i8*> [#uses=1]
-	%72 = load i8* %71, align 1		; <i8> [#uses=1]
+	%71 = getelementptr i8, i8* %0, i32 %.sum5		; <i8*> [#uses=1]
+	%72 = load i8, i8* %71, align 1		; <i8> [#uses=1]
 	store i8 %72, i8* undef, align 1
 	%73 = fadd float %47, undef		; <float> [#uses=1]
 	%74 = fptosi float %73 to i32		; <i32> [#uses=1]
@@ -171,8 +171,8 @@ bb8:		; preds = %bb8, %bb6
 	%76 = lshr i32 %75, 3		; <i32> [#uses=1]
 	%77 = and i32 %76, 1023		; <i32> [#uses=1]
 	%.sum3 = add i32 %77, 128		; <i32> [#uses=1]
-	%78 = getelementptr i8* %0, i32 %.sum3		; <i8*> [#uses=1]
-	%79 = load i8* %78, align 1		; <i8> [#uses=1]
+	%78 = getelementptr i8, i8* %0, i32 %.sum3		; <i8*> [#uses=1]
+	%79 = load i8, i8* %78, align 1		; <i8> [#uses=1]
 	store i8 %79, i8* undef, align 1
 	%80 = fsub float %47, undef		; <float> [#uses=1]
 	%81 = fptosi float %80 to i32		; <i32> [#uses=1]
@@ -180,9 +180,9 @@ bb8:		; preds = %bb8, %bb6
 	%83 = lshr i32 %82, 3		; <i32> [#uses=1]
 	%84 = and i32 %83, 1023		; <i32> [#uses=1]
 	%.sum1 = add i32 %84, 128		; <i32> [#uses=1]
-	%85 = getelementptr i8* %0, i32 %.sum1		; <i8*> [#uses=1]
-	%86 = load i8* %85, align 1		; <i8> [#uses=1]
-	%87 = getelementptr i8* %40, i32 %.sum		; <i8*> [#uses=1]
+	%85 = getelementptr i8, i8* %0, i32 %.sum1		; <i8*> [#uses=1]
+	%86 = load i8, i8* %85, align 1		; <i8> [#uses=1]
+	%87 = getelementptr i8, i8* %40, i32 %.sum		; <i8*> [#uses=1]
 	store i8 %86, i8* %87, align 1
 	%88 = add i32 %ctr.116, 1		; <i32> [#uses=2]
 	%exitcond = icmp eq i32 %88, 8		; <i1> [#uses=1]
diff --git a/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll b/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
index 09e0ed1ead63..4a99e280e7ab 100644
--- a/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
+++ b/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
@@ -22,7 +22,7 @@ bb4.preheader.i:		; preds = %entry
 	br i1 undef, label %tbl.exit, label %bb.i.preheader
 
 bb.i.preheader:		; preds = %bb4.preheader.i
-	%line3.i.i.i = getelementptr [200 x i8]* %line.i.i.i, i32 0, i32 0		; <i8*> [#uses=1]
+	%line3.i.i.i = getelementptr [200 x i8], [200 x i8]* %line.i.i.i, i32 0, i32 0		; <i8*> [#uses=1]
 	br label %bb.i
 
 bb.i:		; preds = %bb4.backedge.i, %bb.i.preheader
@@ -38,7 +38,7 @@ bb2.i184.i.i:		; preds = %bb.i183.i.i, %bb3.i
 	br i1 undef, label %bb5.i185.i.i, label %bb35.preheader.i.i.i
 
 bb35.preheader.i.i.i:		; preds = %bb2.i184.i.i
-	%0 = load i8* %line3.i.i.i, align 1		; <i8> [#uses=1]
+	%0 = load i8, i8* %line3.i.i.i, align 1		; <i8> [#uses=1]
 	%1 = icmp eq i8 %0, 59		; <i1> [#uses=1]
 	br i1 %1, label %bb36.i.i.i, label %bb9.i186.i.i
 
@@ -53,16 +53,16 @@ bb36.i.i.i:		; preds = %bb35.preheader.i.i.i
 
 bb.i171.i.i:		; preds = %bb3.i176.i.i, %bb36.i.i.i, %bb5.i185.i.i
 	%2 = phi i32 [ %4, %bb3.i176.i.i ], [ 0, %bb36.i.i.i ], [ 0, %bb5.i185.i.i ]		; <i32> [#uses=6]
-	%scevgep16.i.i.i = getelementptr [20 x i32]* @sep, i32 0, i32 %2		; <i32*> [#uses=1]
-	%scevgep18.i.i.i = getelementptr [20 x [10 x i8]]* @cll, i32 0, i32 %2, i32 0		; <i8*> [#uses=0]
+	%scevgep16.i.i.i = getelementptr [20 x i32], [20 x i32]* @sep, i32 0, i32 %2		; <i32*> [#uses=1]
+	%scevgep18.i.i.i = getelementptr [20 x [10 x i8]], [20 x [10 x i8]]* @cll, i32 0, i32 %2, i32 0		; <i8*> [#uses=0]
 	store i32 -1, i32* %scevgep16.i.i.i, align 4
 	br label %bb1.i175.i.i
 
 bb1.i175.i.i:		; preds = %bb1.i175.i.i, %bb.i171.i.i
 	%i.03.i172.i.i = phi i32 [ 0, %bb.i171.i.i ], [ %3, %bb1.i175.i.i ]		; <i32> [#uses=4]
-	%scevgep11.i.i.i = getelementptr [100 x [20 x i32]]* @lefline, i32 0, i32 %i.03.i172.i.i, i32 %2		; <i32*> [#uses=1]
-	%scevgep12.i.i.i = getelementptr [100 x [20 x [4 x i8]]]* @vsize, i32 0, i32 %i.03.i172.i.i, i32 %2, i32 0		; <i8*> [#uses=1]
-	%scevgep13.i.i.i = getelementptr [100 x [20 x [4 x i8]]]* @csize, i32 0, i32 %i.03.i172.i.i, i32 %2, i32 0		; <i8*> [#uses=0]
+	%scevgep11.i.i.i = getelementptr [100 x [20 x i32]], [100 x [20 x i32]]* @lefline, i32 0, i32 %i.03.i172.i.i, i32 %2		; <i32*> [#uses=1]
+	%scevgep12.i.i.i = getelementptr [100 x [20 x [4 x i8]]], [100 x [20 x [4 x i8]]]* @vsize, i32 0, i32 %i.03.i172.i.i, i32 %2, i32 0		; <i8*> [#uses=1]
+	%scevgep13.i.i.i = getelementptr [100 x [20 x [4 x i8]]], [100 x [20 x [4 x i8]]]* @csize, i32 0, i32 %i.03.i172.i.i, i32 %2, i32 0		; <i8*> [#uses=0]
 	store i8 0, i8* %scevgep12.i.i.i, align 1
 	store i32 0, i32* %scevgep11.i.i.i, align 4
 	store i32 108, i32* undef, align 4
diff --git a/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll b/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll
index 0b5610327107..55b0921779d4 100644
--- a/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll
+++ b/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll
@@ -26,15 +26,15 @@ declare void @_ZN10xalanc_1_814FormatterToXML17writeParentTagEndEv(%"struct.xala
 
 define void @_ZN10xalanc_1_814FormatterToXML5cdataEPKtj(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 %length) {
 entry:
-	%0 = getelementptr %"struct.xalanc_1_8::FormatterToXML"* %this, i32 0, i32 13		; <i8*> [#uses=1]
+	%0 = getelementptr %"struct.xalanc_1_8::FormatterToXML", %"struct.xalanc_1_8::FormatterToXML"* %this, i32 0, i32 13		; <i8*> [#uses=1]
 	br i1 undef, label %bb4, label %bb
 
 bb:		; preds = %entry
 	store i8 0, i8* %0, align 1
-	%1 = getelementptr %"struct.xalanc_1_8::FormatterToXML"* %this, i32 0, i32 0, i32 0, i32 0		; <i32 (...)***> [#uses=1]
-	%2 = load i32 (...)*** %1, align 4		; <i32 (...)**> [#uses=1]
-	%3 = getelementptr i32 (...)** %2, i32 11		; <i32 (...)**> [#uses=1]
-	%4 = load i32 (...)** %3, align 4		; <i32 (...)*> [#uses=1]
+	%1 = getelementptr %"struct.xalanc_1_8::FormatterToXML", %"struct.xalanc_1_8::FormatterToXML"* %this, i32 0, i32 0, i32 0, i32 0		; <i32 (...)***> [#uses=1]
+	%2 = load i32 (...)**, i32 (...)*** %1, align 4		; <i32 (...)**> [#uses=1]
+	%3 = getelementptr i32 (...)*, i32 (...)** %2, i32 11		; <i32 (...)**> [#uses=1]
+	%4 = load i32 (...)*, i32 (...)** %3, align 4		; <i32 (...)*> [#uses=1]
 	%5 = bitcast i32 (...)* %4 to void (%"struct.xalanc_1_8::FormatterToXML"*, i16*, i32)*		; <void (%"struct.xalanc_1_8::FormatterToXML"*, i16*, i32)*> [#uses=1]
 	tail call  void %5(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 %length)
 	ret void
diff --git a/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll b/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll
index acff2615cbb3..b75a14b0a674 100644
--- a/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll
+++ b/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll
@@ -17,7 +17,7 @@ bb1:		; preds = %entry
 
 bb2:		; preds = %bb1
 	%0 = call i8* @llvm.frameaddress(i32 0)		; <i8*> [#uses=1]
-	%1 = call  i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* noalias undef, i8* noalias getelementptr ([30 x i8]* @.str2, i32 0, i32 0), i8* %0, i8* null) nounwind		; <i32> [#uses=0]
+	%1 = call  i32 (%struct.FILE*, i8*, ...) @fprintf(%struct.FILE* noalias undef, i8* noalias getelementptr ([30 x i8], [30 x i8]* @.str2, i32 0, i32 0), i8* %0, i8* null) nounwind		; <i32> [#uses=0]
 	unreachable
 
 bb9:		; preds = %bb1
diff --git a/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll b/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll
index 28ac28bbc550..ccec979bf8cf 100644
--- a/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll
+++ b/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll
@@ -44,8 +44,8 @@ entry:
 
 bb5:		; preds = %bb5, %entry
 	%.pn = phi %struct.rec* [ %y.0, %bb5 ], [ undef, %entry ]		; <%struct.rec*> [#uses=1]
-	%y.0.in = getelementptr %struct.rec* %.pn, i32 0, i32 0, i32 0, i32 1, i32 0		; <%struct.rec**> [#uses=1]
-	%y.0 = load %struct.rec** %y.0.in		; <%struct.rec*> [#uses=2]
+	%y.0.in = getelementptr %struct.rec, %struct.rec* %.pn, i32 0, i32 0, i32 0, i32 1, i32 0		; <%struct.rec**> [#uses=1]
+	%y.0 = load %struct.rec*, %struct.rec** %y.0.in		; <%struct.rec*> [#uses=2]
 	br i1 undef, label %bb5, label %bb6
 
 bb6:		; preds = %bb5
@@ -62,33 +62,33 @@ bb.i1:		; preds = %FontHalfXHeight.exit
 	br label %FontSize.exit
 
 FontSize.exit:		; preds = %bb.i1, %FontHalfXHeight.exit
-	%1 = load i32* undef, align 4		; <i32> [#uses=1]
+	%1 = load i32, i32* undef, align 4		; <i32> [#uses=1]
 	%2 = icmp ult i32 0, undef		; <i1> [#uses=1]
 	br i1 %2, label %bb.i5, label %FontName.exit
 
 bb.i5:		; preds = %FontSize.exit
-	call  void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([10 x i8]* @.str81872, i32 0, i32 0)) nounwind
+	call  void (i32, i32, i8*, i32, %struct.FILE_POS*, ...) @Error(i32 1, i32 2, i8* getelementptr ([20 x i8], [20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([10 x i8], [10 x i8]* @.str81872, i32 0, i32 0)) nounwind
 	br label %FontName.exit
 
 FontName.exit:		; preds = %bb.i5, %FontSize.exit
-	%3 = call  i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([8 x i8]* @.str1822946, i32 0, i32 0), i32 %1, i8* undef) nounwind		; <i32> [#uses=0]
-	%4 = call  i32 @"\01_fwrite"(i8* getelementptr ([11 x i8]* @.str1842948, i32 0, i32 0), i32 1, i32 10, i8* undef) nounwind		; <i32> [#uses=0]
+	%3 = call  i32 (%struct.FILE*, i8*, ...) @fprintf(%struct.FILE* undef, i8* getelementptr ([8 x i8], [8 x i8]* @.str1822946, i32 0, i32 0), i32 %1, i8* undef) nounwind		; <i32> [#uses=0]
+	%4 = call  i32 @"\01_fwrite"(i8* getelementptr ([11 x i8], [11 x i8]* @.str1842948, i32 0, i32 0), i32 1, i32 10, i8* undef) nounwind		; <i32> [#uses=0]
 	%5 = sub i32 %colmark, undef		; <i32> [#uses=1]
 	%6 = sub i32 %rowmark, undef		; <i32> [#uses=1]
-	%7 = load %struct.FILE** @out_fp, align 4		; <%struct.FILE*> [#uses=1]
-	%8 = call  i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %7, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 %5, i32 %6) nounwind		; <i32> [#uses=0]
+	%7 = load %struct.FILE*, %struct.FILE** @out_fp, align 4		; <%struct.FILE*> [#uses=1]
+	%8 = call  i32 (%struct.FILE*, i8*, ...) @fprintf(%struct.FILE* %7, i8* getelementptr ([17 x i8], [17 x i8]* @.str212784, i32 0, i32 0), i32 %5, i32 %6) nounwind		; <i32> [#uses=0]
 	store i32 0, i32* @cpexists, align 4
-	%9 = getelementptr %struct.rec* %y.0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 1		; <i32*> [#uses=1]
-	%10 = load i32* %9, align 4		; <i32> [#uses=1]
+	%9 = getelementptr %struct.rec, %struct.rec* %y.0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 1		; <i32*> [#uses=1]
+	%10 = load i32, i32* %9, align 4		; <i32> [#uses=1]
 	%11 = sub i32 0, %10		; <i32> [#uses=1]
-	%12 = load %struct.FILE** @out_fp, align 4		; <%struct.FILE*> [#uses=1]
-	%13 = call  i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %12, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 undef, i32 %11) nounwind		; <i32> [#uses=0]
+	%12 = load %struct.FILE*, %struct.FILE** @out_fp, align 4		; <%struct.FILE*> [#uses=1]
+	%13 = call  i32 (%struct.FILE*, i8*, ...) @fprintf(%struct.FILE* %12, i8* getelementptr ([17 x i8], [17 x i8]* @.str212784, i32 0, i32 0), i32 undef, i32 %11) nounwind		; <i32> [#uses=0]
 	store i32 0, i32* @cpexists, align 4
 	br label %bb100.outer.outer
 
 bb100.outer.outer:		; preds = %bb79.critedge, %bb1.i3, %FontName.exit
 	%x_addr.0.ph.ph = phi %struct.rec* [ %x, %FontName.exit ], [ null, %bb79.critedge ], [ null, %bb1.i3 ]		; <%struct.rec*> [#uses=1]
-	%14 = getelementptr %struct.rec* %x_addr.0.ph.ph, i32 0, i32 0, i32 1, i32 0		; <%struct.FILE_POS*> [#uses=0]
+	%14 = getelementptr %struct.rec, %struct.rec* %x_addr.0.ph.ph, i32 0, i32 0, i32 1, i32 0		; <%struct.FILE_POS*> [#uses=0]
 	br label %bb100.outer
 
 bb.i80:		; preds = %bb3.i85
@@ -116,7 +116,7 @@ bb.i47:		; preds = %bb3.i52
 	br i1 undef, label %bb2.i51, label %bb2.i.i15.critedge
 
 bb2.i51:		; preds = %bb.i47, %StringBeginsWith.exit88, %bb.i80
-	%15 = load i8* undef, align 1		; <i8> [#uses=0]
+	%15 = load i8, i8* undef, align 1		; <i8> [#uses=0]
 	br i1 false, label %StringBeginsWith.exit55thread-split, label %bb3.i52
 
 bb3.i52:		; preds = %bb2.i51
diff --git a/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll b/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll
index 88accf8063ed..89f47d9d26f9 100644
--- a/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll
+++ b/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll
@@ -76,8 +76,8 @@ declare i8* @fgets(i8*, i32, %struct.FILE* nocapture) nounwind
 define void @PS_PrintGraphicInclude(%struct.rec* %x, i32 %colmark, i32 %rowmark) nounwind {
 entry:
 	%buff = alloca [512 x i8], align 4		; <[512 x i8]*> [#uses=5]
-	%0 = getelementptr %struct.rec* %x, i32 0, i32 0, i32 1, i32 0, i32 0		; <i8*> [#uses=2]
-	%1 = load i8* %0, align 4		; <i8> [#uses=1]
+	%0 = getelementptr %struct.rec, %struct.rec* %x, i32 0, i32 0, i32 1, i32 0, i32 0		; <i8*> [#uses=2]
+	%1 = load i8, i8* %0, align 4		; <i8> [#uses=1]
 	%2 = add i8 %1, -94		; <i8> [#uses=1]
 	%3 = icmp ugt i8 %2, 1		; <i1> [#uses=1]
 	br i1 %3, label %bb, label %bb1
@@ -86,28 +86,28 @@ bb:		; preds = %entry
 	br label %bb1
 
 bb1:		; preds = %bb, %entry
-	%4 = getelementptr %struct.rec* %x, i32 0, i32 0, i32 2		; <%struct.SECOND_UNION*> [#uses=1]
+	%4 = getelementptr %struct.rec, %struct.rec* %x, i32 0, i32 0, i32 2		; <%struct.SECOND_UNION*> [#uses=1]
 	%5 = bitcast %struct.SECOND_UNION* %4 to %5*		; <%5*> [#uses=1]
-	%6 = getelementptr %5* %5, i32 0, i32 1		; <i8*> [#uses=1]
-	%7 = load i8* %6, align 1		; <i8> [#uses=1]
+	%6 = getelementptr %5, %5* %5, i32 0, i32 1		; <i8*> [#uses=1]
+	%7 = load i8, i8* %6, align 1		; <i8> [#uses=1]
 	%8 = icmp eq i8 %7, 0		; <i1> [#uses=1]
 	br i1 %8, label %bb2, label %bb3
 
 bb2:		; preds = %bb1
-	call  void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([40 x i8]* @.str1802944, i32 0, i32 0)) nounwind
+	call  void (i32, i32, i8*, i32, %struct.FILE_POS*, ...) @Error(i32 1, i32 2, i8* getelementptr ([20 x i8], [20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([40 x i8], [40 x i8]* @.str1802944, i32 0, i32 0)) nounwind
 	br label %bb3
 
 bb3:		; preds = %bb2, %bb1
-	%9 = load %struct.rec** undef, align 4		; <%struct.rec*> [#uses=0]
+	%9 = load %struct.rec*, %struct.rec** undef, align 4		; <%struct.rec*> [#uses=0]
 	br label %bb5
 
 bb5:		; preds = %bb5, %bb3
-	%y.0 = load %struct.rec** null		; <%struct.rec*> [#uses=2]
+	%y.0 = load %struct.rec*, %struct.rec** null		; <%struct.rec*> [#uses=2]
 	br i1 false, label %bb5, label %bb6
 
 bb6:		; preds = %bb5
-	%10 = load i8* %0, align 4		; <i8> [#uses=1]
-	%11 = getelementptr %struct.rec* %y.0, i32 0, i32 0, i32 1, i32 0		; <%struct.FILE_POS*> [#uses=1]
+	%10 = load i8, i8* %0, align 4		; <i8> [#uses=1]
+	%11 = getelementptr %struct.rec, %struct.rec* %y.0, i32 0, i32 0, i32 1, i32 0		; <%struct.FILE_POS*> [#uses=1]
 	%12 = call  %struct.FILE* @OpenIncGraphicFile(i8* undef, i8 zeroext %10, %struct.rec** null, %struct.FILE_POS* %11, i32* undef) nounwind		; <%struct.FILE*> [#uses=4]
 	br i1 false, label %bb7, label %bb8
 
@@ -116,7 +116,7 @@ bb7:		; preds = %bb6
 
 bb8:		; preds = %bb6
 	%13 = and i32 undef, 4095		; <i32> [#uses=2]
-	%14 = load i32* @currentfont, align 4		; <i32> [#uses=0]
+	%14 = load i32, i32* @currentfont, align 4		; <i32> [#uses=0]
 	br i1 false, label %bb10, label %bb9
 
 bb9:		; preds = %bb8
@@ -124,8 +124,8 @@ bb9:		; preds = %bb8
 	br i1 %15, label %bb.i, label %FontHalfXHeight.exit
 
 bb.i:		; preds = %bb9
-	call  void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([17 x i8]* @.str111875, i32 0, i32 0)) nounwind
-	%.pre186 = load i32* @currentfont, align 4		; <i32> [#uses=1]
+	call  void (i32, i32, i8*, i32, %struct.FILE_POS*, ...) @Error(i32 1, i32 2, i8* getelementptr ([20 x i8], [20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([17 x i8], [17 x i8]* @.str111875, i32 0, i32 0)) nounwind
+	%.pre186 = load i32, i32* @currentfont, align 4		; <i32> [#uses=1]
 	br label %FontHalfXHeight.exit
 
 FontHalfXHeight.exit:		; preds = %bb.i, %bb9
@@ -139,55 +139,55 @@ bb1.i:		; preds = %bb.i1, %FontHalfXHeight.exit
 	br i1 undef, label %bb2.i, label %FontSize.exit
 
 bb2.i:		; preds = %bb1.i
-	call  void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 37, i32 61, i8* getelementptr ([30 x i8]* @.str101874, i32 0, i32 0), i32 1, %struct.FILE_POS* null) nounwind
+	call  void (i32, i32, i8*, i32, %struct.FILE_POS*, ...) @Error(i32 37, i32 61, i8* getelementptr ([30 x i8], [30 x i8]* @.str101874, i32 0, i32 0), i32 1, %struct.FILE_POS* null) nounwind
 	unreachable
 
 FontSize.exit:		; preds = %bb1.i
-	%17 = getelementptr %struct.FONT_INFO* undef, i32 %16, i32 5		; <%struct.rec**> [#uses=0]
-	%18 = load i32* undef, align 4		; <i32> [#uses=1]
-	%19 = load i32* @currentfont, align 4		; <i32> [#uses=2]
-	%20 = load i32* @font_count, align 4		; <i32> [#uses=1]
+	%17 = getelementptr %struct.FONT_INFO, %struct.FONT_INFO* undef, i32 %16, i32 5		; <%struct.rec**> [#uses=0]
+	%18 = load i32, i32* undef, align 4		; <i32> [#uses=1]
+	%19 = load i32, i32* @currentfont, align 4		; <i32> [#uses=2]
+	%20 = load i32, i32* @font_count, align 4		; <i32> [#uses=1]
 	%21 = icmp ult i32 %20, %19		; <i1> [#uses=1]
 	br i1 %21, label %bb.i5, label %FontName.exit
 
 bb.i5:		; preds = %FontSize.exit
-	call  void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([10 x i8]* @.str81872, i32 0, i32 0)) nounwind
+	call  void (i32, i32, i8*, i32, %struct.FILE_POS*, ...) @Error(i32 1, i32 2, i8* getelementptr ([20 x i8], [20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([10 x i8], [10 x i8]* @.str81872, i32 0, i32 0)) nounwind
 	br label %FontName.exit
 
 FontName.exit:		; preds = %bb.i5, %FontSize.exit
 	%22 = phi %struct.FONT_INFO* [ undef, %bb.i5 ], [ undef, %FontSize.exit ]		; <%struct.FONT_INFO*> [#uses=1]
-	%23 = getelementptr %struct.FONT_INFO* %22, i32 %19, i32 5		; <%struct.rec**> [#uses=0]
-	%24 = call  i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([8 x i8]* @.str1822946, i32 0, i32 0), i32 %18, i8* null) nounwind		; <i32> [#uses=0]
+	%23 = getelementptr %struct.FONT_INFO, %struct.FONT_INFO* %22, i32 %19, i32 5		; <%struct.rec**> [#uses=0]
+	%24 = call  i32 (%struct.FILE*, i8*, ...) @fprintf(%struct.FILE* undef, i8* getelementptr ([8 x i8], [8 x i8]* @.str1822946, i32 0, i32 0), i32 %18, i8* null) nounwind		; <i32> [#uses=0]
 	br label %bb10
 
 bb10:		; preds = %FontName.exit, %bb8
-	%25 = call  i32 @"\01_fwrite"(i8* getelementptr ([11 x i8]* @.str1842948, i32 0, i32 0), i32 1, i32 10, i8* undef) nounwind		; <i32> [#uses=0]
+	%25 = call  i32 @"\01_fwrite"(i8* getelementptr ([11 x i8], [11 x i8]* @.str1842948, i32 0, i32 0), i32 1, i32 10, i8* undef) nounwind		; <i32> [#uses=0]
 	%26 = sub i32 %rowmark, undef		; <i32> [#uses=1]
-	%27 = load %struct.FILE** @out_fp, align 4		; <%struct.FILE*> [#uses=1]
-	%28 = call  i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %27, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 undef, i32 %26) nounwind		; <i32> [#uses=0]
+	%27 = load %struct.FILE*, %struct.FILE** @out_fp, align 4		; <%struct.FILE*> [#uses=1]
+	%28 = call  i32 (%struct.FILE*, i8*, ...) @fprintf(%struct.FILE* %27, i8* getelementptr ([17 x i8], [17 x i8]* @.str212784, i32 0, i32 0), i32 undef, i32 %26) nounwind		; <i32> [#uses=0]
 	store i32 0, i32* @cpexists, align 4
-	%29 = call  i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([17 x i8]* @.str192782, i32 0, i32 0), double 2.000000e+01, double 2.000000e+01) nounwind		; <i32> [#uses=0]
-	%30 = getelementptr %struct.rec* %y.0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 0		; <i32*> [#uses=1]
-	%31 = load i32* %30, align 4		; <i32> [#uses=1]
+	%29 = call  i32 (%struct.FILE*, i8*, ...) @fprintf(%struct.FILE* undef, i8* getelementptr ([17 x i8], [17 x i8]* @.str192782, i32 0, i32 0), double 2.000000e+01, double 2.000000e+01) nounwind		; <i32> [#uses=0]
+	%30 = getelementptr %struct.rec, %struct.rec* %y.0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 0		; <i32*> [#uses=1]
+	%31 = load i32, i32* %30, align 4		; <i32> [#uses=1]
 	%32 = sub i32 0, %31		; <i32> [#uses=1]
-	%33 = load i32* undef, align 4		; <i32> [#uses=1]
+	%33 = load i32, i32* undef, align 4		; <i32> [#uses=1]
 	%34 = sub i32 0, %33		; <i32> [#uses=1]
-	%35 = load %struct.FILE** @out_fp, align 4		; <%struct.FILE*> [#uses=1]
-	%36 = call  i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %35, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 %32, i32 %34) nounwind		; <i32> [#uses=0]
+	%35 = load %struct.FILE*, %struct.FILE** @out_fp, align 4		; <%struct.FILE*> [#uses=1]
+	%36 = call  i32 (%struct.FILE*, i8*, ...) @fprintf(%struct.FILE* %35, i8* getelementptr ([17 x i8], [17 x i8]* @.str212784, i32 0, i32 0), i32 %32, i32 %34) nounwind		; <i32> [#uses=0]
 	store i32 0, i32* @cpexists, align 4
-	%37 = load %struct.rec** null, align 4		; <%struct.rec*> [#uses=1]
-	%38 = getelementptr %struct.rec* %37, i32 0, i32 0, i32 4		; <%struct.FOURTH_UNION*> [#uses=1]
-	%39 = call  i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([23 x i8]* @.str1852949, i32 0, i32 0), %struct.FOURTH_UNION* %38) nounwind		; <i32> [#uses=0]
-	%buff14 = getelementptr [512 x i8]* %buff, i32 0, i32 0		; <i8*> [#uses=5]
+	%37 = load %struct.rec*, %struct.rec** null, align 4		; <%struct.rec*> [#uses=1]
+	%38 = getelementptr %struct.rec, %struct.rec* %37, i32 0, i32 0, i32 4		; <%struct.FOURTH_UNION*> [#uses=1]
+	%39 = call  i32 (%struct.FILE*, i8*, ...) @fprintf(%struct.FILE* undef, i8* getelementptr ([23 x i8], [23 x i8]* @.str1852949, i32 0, i32 0), %struct.FOURTH_UNION* %38) nounwind		; <i32> [#uses=0]
+	%buff14 = getelementptr [512 x i8], [512 x i8]* %buff, i32 0, i32 0		; <i8*> [#uses=5]
 	%40 = call  i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind		; <i8*> [#uses=0]
 	%iftmp.506.0 = select i1 undef, i32 2, i32 0		; <i32> [#uses=1]
-	%41 = getelementptr [512 x i8]* %buff, i32 0, i32 26		; <i8*> [#uses=1]
+	%41 = getelementptr [512 x i8], [512 x i8]* %buff, i32 0, i32 26		; <i8*> [#uses=1]
 	br label %bb100.outer.outer
 
 bb100.outer.outer:		; preds = %bb83, %bb10
 	%state.0.ph.ph = phi i32 [ %iftmp.506.0, %bb10 ], [ undef, %bb83 ]		; <i32> [#uses=1]
 	%x_addr.0.ph.ph = phi %struct.rec* [ %x, %bb10 ], [ %71, %bb83 ]		; <%struct.rec*> [#uses=1]
-	%42 = getelementptr %struct.rec* %x_addr.0.ph.ph, i32 0, i32 0, i32 1, i32 0		; <%struct.FILE_POS*> [#uses=0]
+	%42 = getelementptr %struct.rec, %struct.rec* %x_addr.0.ph.ph, i32 0, i32 0, i32 1, i32 0		; <%struct.FILE_POS*> [#uses=0]
 	br label %bb100.outer
 
 bb.i80:		; preds = %bb3.i85
@@ -197,19 +197,19 @@ bb.i80:		; preds = %bb3.i85
 
 bb2.i84:		; preds = %bb100.outer, %bb.i80
 	%indvar.i81 = phi i32 [ %indvar.next.i79, %bb.i80 ], [ 0, %bb100.outer ]		; <i32> [#uses=3]
-	%pp.0.i82 = getelementptr [27 x i8]* @.str141878, i32 0, i32 %indvar.i81		; <i8*> [#uses=2]
-	%sp.0.i83 = getelementptr [512 x i8]* %buff, i32 0, i32 %indvar.i81		; <i8*> [#uses=1]
-	%44 = load i8* %sp.0.i83, align 1		; <i8> [#uses=2]
+	%pp.0.i82 = getelementptr [27 x i8], [27 x i8]* @.str141878, i32 0, i32 %indvar.i81		; <i8*> [#uses=2]
+	%sp.0.i83 = getelementptr [512 x i8], [512 x i8]* %buff, i32 0, i32 %indvar.i81		; <i8*> [#uses=1]
+	%44 = load i8, i8* %sp.0.i83, align 1		; <i8> [#uses=2]
 	%45 = icmp eq i8 %44, 0		; <i1> [#uses=1]
 	br i1 %45, label %StringBeginsWith.exit88thread-split, label %bb3.i85
 
 bb3.i85:		; preds = %bb2.i84
-	%46 = load i8* %pp.0.i82, align 1		; <i8> [#uses=3]
+	%46 = load i8, i8* %pp.0.i82, align 1		; <i8> [#uses=3]
 	%47 = icmp eq i8 %46, 0		; <i1> [#uses=1]
 	br i1 %47, label %StringBeginsWith.exit88, label %bb.i80
 
 StringBeginsWith.exit88thread-split:		; preds = %bb2.i84
-	%.pr = load i8* %pp.0.i82		; <i8> [#uses=1]
+	%.pr = load i8, i8* %pp.0.i82		; <i8> [#uses=1]
 	br label %StringBeginsWith.exit88
 
 StringBeginsWith.exit88:		; preds = %StringBeginsWith.exit88thread-split, %bb3.i85
@@ -224,17 +224,17 @@ bb2.i75:		; preds = %bb2.i.i68
 	br label %bb3.i77
 
 bb3.i77:		; preds = %bb2.i75, %StringBeginsWith.exit88
-	%sp.0.i76 = getelementptr [512 x i8]* %buff, i32 0, i32 undef		; <i8*> [#uses=1]
-	%49 = load i8* %sp.0.i76, align 1		; <i8> [#uses=1]
+	%sp.0.i76 = getelementptr [512 x i8], [512 x i8]* %buff, i32 0, i32 undef		; <i8*> [#uses=1]
+	%49 = load i8, i8* %sp.0.i76, align 1		; <i8> [#uses=1]
 	%50 = icmp eq i8 %49, 0		; <i1> [#uses=1]
 	br i1 %50, label %bb24, label %bb2.i.i68
 
 bb24:		; preds = %bb3.i77
 	%51 = call  %struct.rec* @MakeWord(i32 11, i8* %41, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind		; <%struct.rec*> [#uses=0]
-	%52 = load i8* getelementptr ([150 x i8]* @zz_lengths, i32 0, i32 0), align 4		; <i8> [#uses=1]
+	%52 = load i8, i8* getelementptr ([150 x i8], [150 x i8]* @zz_lengths, i32 0, i32 0), align 4		; <i8> [#uses=1]
 	%53 = zext i8 %52 to i32		; <i32> [#uses=2]
-	%54 = getelementptr [524 x %struct.rec*]* @zz_free, i32 0, i32 %53		; <%struct.rec**> [#uses=2]
-	%55 = load %struct.rec** %54, align 4		; <%struct.rec*> [#uses=3]
+	%54 = getelementptr [524 x %struct.rec*], [524 x %struct.rec*]* @zz_free, i32 0, i32 %53		; <%struct.rec**> [#uses=2]
+	%55 = load %struct.rec*, %struct.rec** %54, align 4		; <%struct.rec*> [#uses=3]
 	%56 = icmp eq %struct.rec* %55, null		; <i1> [#uses=1]
 	br i1 %56, label %bb27, label %bb28
 
@@ -245,7 +245,7 @@ bb.i56:		; preds = %bb27
 	br i1 undef, label %bb1.i58, label %bb2.i60
 
 bb1.i58:		; preds = %bb.i56
-	call  void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 31, i32 1, i8* getelementptr ([32 x i8]* @.str1575, i32 0, i32 0), i32 1, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind
+	call  void (i32, i32, i8*, i32, %struct.FILE_POS*, ...) @Error(i32 31, i32 1, i8* getelementptr ([32 x i8], [32 x i8]* @.str1575, i32 0, i32 0), i32 1, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind
 	br label %bb2.i60
 
 bb2.i60:		; preds = %bb1.i58, %bb.i56
@@ -255,14 +255,14 @@ bb2.i60:		; preds = %bb1.i58, %bb.i56
 
 GetMemory.exit62:		; preds = %bb2.i60, %bb27
 	%57 = phi i8** [ %.pre1.i59, %bb2.i60 ], [ undef, %bb27 ]		; <i8**> [#uses=1]
-	%58 = getelementptr i8** %57, i32 %53		; <i8**> [#uses=1]
+	%58 = getelementptr i8*, i8** %57, i32 %53		; <i8**> [#uses=1]
 	store i8** %58, i8*** @next_free.4772, align 4
 	store %struct.rec* undef, %struct.rec** @zz_hold, align 4
 	br label %bb29
 
 bb28:		; preds = %bb24
 	store %struct.rec* %55, %struct.rec** @zz_hold, align 4
-	%59 = load %struct.rec** null, align 4		; <%struct.rec*> [#uses=1]
+	%59 = load %struct.rec*, %struct.rec** null, align 4		; <%struct.rec*> [#uses=1]
 	store %struct.rec* %59, %struct.rec** %54, align 4
 	br label %bb29
 
@@ -280,7 +280,7 @@ bb35:		; preds = %bb31, %bb29
 	br i1 undef, label %bb41, label %bb37
 
 bb37:		; preds = %bb35
-	%60 = load %struct.rec** null, align 4		; <%struct.rec*> [#uses=1]
+	%60 = load %struct.rec*, %struct.rec** null, align 4		; <%struct.rec*> [#uses=1]
 	store %struct.rec* %60, %struct.rec** undef
 	store %struct.rec* undef, %struct.rec** null
 	store %struct.rec* %.pre184, %struct.rec** null, align 4
@@ -297,12 +297,12 @@ bb.i47:		; preds = %bb3.i52
 	br i1 %63, label %bb2.i51, label %bb2.i41
 
 bb2.i51:		; preds = %bb.i47, %bb2.i.i68, %StringBeginsWith.exit88, %bb.i80
-	%pp.0.i49 = getelementptr [17 x i8]* @.str1872951, i32 0, i32 0		; <i8*> [#uses=1]
-	%64 = load i8* null, align 1		; <i8> [#uses=1]
+	%pp.0.i49 = getelementptr [17 x i8], [17 x i8]* @.str1872951, i32 0, i32 0		; <i8*> [#uses=1]
+	%64 = load i8, i8* null, align 1		; <i8> [#uses=1]
 	br i1 false, label %StringBeginsWith.exit55thread-split, label %bb3.i52
 
 bb3.i52:		; preds = %bb2.i51
-	%65 = load i8* %pp.0.i49, align 1		; <i8> [#uses=1]
+	%65 = load i8, i8* %pp.0.i49, align 1		; <i8> [#uses=1]
 	br i1 false, label %StringBeginsWith.exit55, label %bb.i47
 
 StringBeginsWith.exit55thread-split:		; preds = %bb2.i51
@@ -318,11 +318,11 @@ bb2.i41:		; preds = %bb2.i41, %bb49, %StringBeginsWith.exit55, %bb.i47
 	br i1 false, label %bb2.i41, label %bb2.i.i15
 
 bb2.i.i15:		; preds = %bb2.i41
-	%pp.0.i.i13 = getelementptr [6 x i8]* @.str742838, i32 0, i32 0		; <i8*> [#uses=1]
+	%pp.0.i.i13 = getelementptr [6 x i8], [6 x i8]* @.str742838, i32 0, i32 0		; <i8*> [#uses=1]
 	br i1 false, label %StringBeginsWith.exitthread-split.i18, label %bb3.i.i16
 
 bb3.i.i16:		; preds = %bb2.i.i15
-	%66 = load i8* %pp.0.i.i13, align 1		; <i8> [#uses=1]
+	%66 = load i8, i8* %pp.0.i.i13, align 1		; <i8> [#uses=1]
 	br label %StringBeginsWith.exit.i20
 
 StringBeginsWith.exitthread-split.i18:		; preds = %bb2.i.i15
@@ -335,9 +335,9 @@ StringBeginsWith.exit.i20:		; preds = %StringBeginsWith.exitthread-split.i18, %b
 
 bb2.i6.i26:		; preds = %bb2.i6.i26, %StringBeginsWith.exit.i20
 	%indvar.i3.i23 = phi i32 [ %indvar.next.i1.i21, %bb2.i6.i26 ], [ 0, %StringBeginsWith.exit.i20 ]		; <i32> [#uses=3]
-	%sp.0.i5.i25 = getelementptr [512 x i8]* %buff, i32 0, i32 %indvar.i3.i23		; <i8*> [#uses=0]
-	%pp.0.i4.i24 = getelementptr [10 x i8]* @.str752839, i32 0, i32 %indvar.i3.i23		; <i8*> [#uses=1]
-	%68 = load i8* %pp.0.i4.i24, align 1		; <i8> [#uses=0]
+	%sp.0.i5.i25 = getelementptr [512 x i8], [512 x i8]* %buff, i32 0, i32 %indvar.i3.i23		; <i8*> [#uses=0]
+	%pp.0.i4.i24 = getelementptr [10 x i8], [10 x i8]* @.str752839, i32 0, i32 %indvar.i3.i23		; <i8*> [#uses=1]
+	%68 = load i8, i8* %pp.0.i4.i24, align 1		; <i8> [#uses=0]
 	%indvar.next.i1.i21 = add i32 %indvar.i3.i23, 1		; <i32> [#uses=1]
 	br i1 undef, label %bb2.i6.i26, label %bb55
 
@@ -368,10 +368,10 @@ StringBeginsWith.exit:		; preds = %StringBeginsWith.exitthread-split, %bb3.i
 
 bb66:		; preds = %StringBeginsWith.exit
 	%71 = call  %struct.rec* @MakeWord(i32 11, i8* undef, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind		; <%struct.rec*> [#uses=4]
-	%72 = load i8* getelementptr ([150 x i8]* @zz_lengths, i32 0, i32 0), align 4		; <i8> [#uses=1]
+	%72 = load i8, i8* getelementptr ([150 x i8], [150 x i8]* @zz_lengths, i32 0, i32 0), align 4		; <i8> [#uses=1]
 	%73 = zext i8 %72 to i32		; <i32> [#uses=2]
-	%74 = getelementptr [524 x %struct.rec*]* @zz_free, i32 0, i32 %73		; <%struct.rec**> [#uses=2]
-	%75 = load %struct.rec** %74, align 4		; <%struct.rec*> [#uses=3]
+	%74 = getelementptr [524 x %struct.rec*], [524 x %struct.rec*]* @zz_free, i32 0, i32 %73		; <%struct.rec**> [#uses=2]
+	%75 = load %struct.rec*, %struct.rec** %74, align 4		; <%struct.rec*> [#uses=3]
 	%76 = icmp eq %struct.rec* %75, null		; <i1> [#uses=1]
 	br i1 %76, label %bb69, label %bb70
 
@@ -385,43 +385,43 @@ bb.i2:		; preds = %bb69
 	br i1 undef, label %bb1.i3, label %bb2.i4
 
 bb1.i3:		; preds = %bb.i2
-	call  void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 31, i32 1, i8* getelementptr ([32 x i8]* @.str1575, i32 0, i32 0), i32 1, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind
+	call  void (i32, i32, i8*, i32, %struct.FILE_POS*, ...) @Error(i32 31, i32 1, i8* getelementptr ([32 x i8], [32 x i8]* @.str1575, i32 0, i32 0), i32 1, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind
 	br label %bb2.i4
 
 bb2.i4:		; preds = %bb1.i3, %bb.i2
 	%.pre1.i = phi i8** [ undef, %bb1.i3 ], [ %78, %bb.i2 ]		; <i8**> [#uses=1]
 	%79 = phi i8** [ undef, %bb1.i3 ], [ %78, %bb.i2 ]		; <i8**> [#uses=1]
-	%80 = getelementptr i8** %79, i32 1020		; <i8**> [#uses=1]
+	%80 = getelementptr i8*, i8** %79, i32 1020		; <i8**> [#uses=1]
 	store i8** %80, i8*** @top_free.4773, align 4
 	br label %GetMemory.exit
 
 GetMemory.exit:		; preds = %bb2.i4, %bb69
 	%81 = phi i8** [ %.pre1.i, %bb2.i4 ], [ undef, %bb69 ]		; <i8**> [#uses=2]
 	%82 = bitcast i8** %81 to %struct.rec*		; <%struct.rec*> [#uses=3]
-	%83 = getelementptr i8** %81, i32 %73		; <i8**> [#uses=1]
+	%83 = getelementptr i8*, i8** %81, i32 %73		; <i8**> [#uses=1]
 	store i8** %83, i8*** @next_free.4772, align 4
 	store %struct.rec* %82, %struct.rec** @zz_hold, align 4
 	br label %bb71
 
 bb70:		; preds = %bb66
-	%84 = load %struct.rec** null, align 4		; <%struct.rec*> [#uses=1]
+	%84 = load %struct.rec*, %struct.rec** null, align 4		; <%struct.rec*> [#uses=1]
 	store %struct.rec* %84, %struct.rec** %74, align 4
 	br label %bb71
 
 bb71:		; preds = %bb70, %GetMemory.exit
 	%.pre185 = phi %struct.rec* [ %75, %bb70 ], [ %82, %GetMemory.exit ]		; <%struct.rec*> [#uses=8]
 	%85 = phi %struct.rec* [ %75, %bb70 ], [ %82, %GetMemory.exit ]		; <%struct.rec*> [#uses=1]
-	%86 = getelementptr %struct.rec* %85, i32 0, i32 0, i32 1, i32 0, i32 0		; <i8*> [#uses=0]
-	%87 = getelementptr %struct.rec* %.pre185, i32 0, i32 0, i32 0, i32 1, i32 1		; <%struct.rec**> [#uses=0]
-	%88 = getelementptr %struct.rec* %.pre185, i32 0, i32 0, i32 0, i32 1, i32 0		; <%struct.rec**> [#uses=1]
+	%86 = getelementptr %struct.rec, %struct.rec* %85, i32 0, i32 0, i32 1, i32 0, i32 0		; <i8*> [#uses=0]
+	%87 = getelementptr %struct.rec, %struct.rec* %.pre185, i32 0, i32 0, i32 0, i32 1, i32 1		; <%struct.rec**> [#uses=0]
+	%88 = getelementptr %struct.rec, %struct.rec* %.pre185, i32 0, i32 0, i32 0, i32 1, i32 0		; <%struct.rec**> [#uses=1]
 	store %struct.rec* %.pre185, %struct.rec** @xx_link, align 4
 	store %struct.rec* %.pre185, %struct.rec** @zz_res, align 4
-	%89 = load %struct.rec** @needs, align 4		; <%struct.rec*> [#uses=2]
+	%89 = load %struct.rec*, %struct.rec** @needs, align 4		; <%struct.rec*> [#uses=2]
 	store %struct.rec* %89, %struct.rec** @zz_hold, align 4
 	br i1 false, label %bb77, label %bb73
 
 bb73:		; preds = %bb71
-	%90 = getelementptr %struct.rec* %89, i32 0, i32 0, i32 0, i32 0, i32 0		; <%struct.rec**> [#uses=1]
+	%90 = getelementptr %struct.rec, %struct.rec* %89, i32 0, i32 0, i32 0, i32 0, i32 0		; <%struct.rec**> [#uses=1]
 	store %struct.rec* null, %struct.rec** @zz_tmp, align 4
 	store %struct.rec* %.pre185, %struct.rec** %90
 	store %struct.rec* %.pre185, %struct.rec** undef, align 4
@@ -433,11 +433,11 @@ bb77:		; preds = %bb73, %bb71
 	br i1 undef, label %bb83, label %bb79
 
 bb79:		; preds = %bb77
-	%91 = getelementptr %struct.rec* %71, i32 0, i32 0, i32 0, i32 1, i32 0		; <%struct.rec**> [#uses=1]
+	%91 = getelementptr %struct.rec, %struct.rec* %71, i32 0, i32 0, i32 0, i32 1, i32 0		; <%struct.rec**> [#uses=1]
 	store %struct.rec* null, %struct.rec** @zz_tmp, align 4
-	%92 = load %struct.rec** %88, align 4		; <%struct.rec*> [#uses=1]
+	%92 = load %struct.rec*, %struct.rec** %88, align 4		; <%struct.rec*> [#uses=1]
 	store %struct.rec* %92, %struct.rec** %91
-	%93 = getelementptr %struct.rec* undef, i32 0, i32 0, i32 0, i32 1, i32 1		; <%struct.rec**> [#uses=1]
+	%93 = getelementptr %struct.rec, %struct.rec* undef, i32 0, i32 0, i32 0, i32 1, i32 1		; <%struct.rec**> [#uses=1]
 	store %struct.rec* %71, %struct.rec** %93, align 4
 	store %struct.rec* %.pre185, %struct.rec** undef, align 4
 	br label %bb83
@@ -467,11 +467,11 @@ bb2.i6.i:		; preds = %bb.i2.i, %StringBeginsWith.exit.i, %bb.i.i
 	br i1 undef, label %strip_out.exitthread-split, label %bb3.i7.i
 
 bb3.i7.i:		; preds = %bb2.i6.i
-	%94 = load i8* undef, align 1		; <i8> [#uses=1]
+	%94 = load i8, i8* undef, align 1		; <i8> [#uses=1]
 	br i1 undef, label %strip_out.exit, label %bb.i2.i
 
 strip_out.exitthread-split:		; preds = %bb2.i6.i
-	%.pr100 = load i8* undef		; <i8> [#uses=1]
+	%.pr100 = load i8, i8* undef		; <i8> [#uses=1]
 	br label %strip_out.exit
 
 strip_out.exit:		; preds = %strip_out.exitthread-split, %bb3.i7.i
@@ -497,12 +497,12 @@ bb101.split:		; preds = %bb100.outer
 	br i1 %97, label %bb103, label %bb102
 
 bb102:		; preds = %bb101.split
-	%98 = call  i32 @remove(i8* getelementptr ([9 x i8]* @.str19294, i32 0, i32 0)) nounwind		; <i32> [#uses=0]
+	%98 = call  i32 @remove(i8* getelementptr ([9 x i8], [9 x i8]* @.str19294, i32 0, i32 0)) nounwind		; <i32> [#uses=0]
 	unreachable
 
 bb103:		; preds = %bb101.split
-	%99 = load %struct.FILE** @out_fp, align 4		; <%struct.FILE*> [#uses=1]
-	%100 = call  i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %99, i8* getelementptr ([26 x i8]* @.str1932957, i32 0, i32 0)) nounwind		; <i32> [#uses=0]
+	%99 = load %struct.FILE*, %struct.FILE** @out_fp, align 4		; <%struct.FILE*> [#uses=1]
+	%100 = call  i32 (%struct.FILE*, i8*, ...) @fprintf(%struct.FILE* %99, i8* getelementptr ([26 x i8], [26 x i8]* @.str1932957, i32 0, i32 0)) nounwind		; <i32> [#uses=0]
 	store i32 0, i32* @wordcount, align 4
 	ret void
 }
diff --git a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll
index ad32dc9d0a07..66ed876f98e3 100644
--- a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll
+++ b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll
@@ -17,7 +17,7 @@ bb5:		; preds = %bb5, %bb3.preheader
 	br i1 undef, label %bb11, label %bb5
 
 bb11:		; preds = %bb5
-	%0 = load i32* undef, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* undef, align 4		; <i32> [#uses=1]
 	%1 = xor i32 %0, 123459876		; <i32> [#uses=1]
 	%2 = sdiv i32 %1, 127773		; <i32> [#uses=1]
 	%3 = mul i32 %2, 2836		; <i32> [#uses=1]
diff --git a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
index 59c236732118..a451321838e7 100644
--- a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
+++ b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
@@ -7,8 +7,8 @@ entry:
 ; CHECK-LABEL: __gcov_execlp:
 ; CHECK: sub sp, #8
 ; CHECK: push
-; CHECK: add r7, sp, #4
-; CHECK: sub.w r4, r7, #4
+; CHECK: add r7, sp, #8
+; CHECK: sub.w r4, r7, #8
 ; CHECK: mov sp, r4
 ; CHECK-NOT: mov sp, r7
 ; CHECK: add sp, #8
diff --git a/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll b/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll
index f3baeb74e2cb..5480868d7a66 100644
--- a/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll
+++ b/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll
@@ -33,12 +33,12 @@ entry:
 	br label %bb
 
 bb:		; preds = %bb, %entry
-	%0 = load float* undef, align 4		; <float> [#uses=1]
+	%0 = load float, float* undef, align 4		; <float> [#uses=1]
 	%1 = fmul float undef, %0		; <float> [#uses=2]
 	%tmp73 = add i32 0, 224		; <i32> [#uses=1]
-	%scevgep74 = getelementptr i8* null, i32 %tmp73		; <i8*> [#uses=1]
+	%scevgep74 = getelementptr i8, i8* null, i32 %tmp73		; <i8*> [#uses=1]
 	%scevgep7475 = bitcast i8* %scevgep74 to float*		; <float*> [#uses=1]
-	%2 = load float* null, align 4		; <float> [#uses=1]
+	%2 = load float, float* null, align 4		; <float> [#uses=1]
 	%3 = fmul float 0.000000e+00, %2		; <float> [#uses=2]
 	%4 = fadd float %1, %3		; <float> [#uses=1]
 	%5 = fsub float %1, %3		; <float> [#uses=2]
@@ -51,7 +51,7 @@ bb:		; preds = %bb, %entry
 	%12 = sitofp i16 undef to float		; <float> [#uses=1]
 	%13 = fmul float %12, 0.000000e+00		; <float> [#uses=2]
 	%14 = sitofp i16 undef to float		; <float> [#uses=1]
-	%15 = load float* %scevgep7475, align 4		; <float> [#uses=1]
+	%15 = load float, float* %scevgep7475, align 4		; <float> [#uses=1]
 	%16 = fmul float %14, %15		; <float> [#uses=2]
 	%17 = fadd float undef, undef		; <float> [#uses=2]
 	%18 = fadd float %13, %16		; <float> [#uses=2]
diff --git a/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll b/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll
index 974ce50d6d44..2bbed1beae15 100644
--- a/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll
+++ b/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll
@@ -3,11 +3,11 @@
 define float @t1(i32 %v0) nounwind {
 entry:
 	store i32 undef, i32* undef, align 4
-	%0 = load [4 x i8]** undef, align 4		; <[4 x i8]*> [#uses=1]
-	%1 = load i8* undef, align 1		; <i8> [#uses=1]
+	%0 = load [4 x i8]*, [4 x i8]** undef, align 4		; <[4 x i8]*> [#uses=1]
+	%1 = load i8, i8* undef, align 1		; <i8> [#uses=1]
 	%2 = zext i8 %1 to i32		; <i32> [#uses=1]
-	%3 = getelementptr [4 x i8]* %0, i32 %v0, i32 0		; <i8*> [#uses=1]
-	%4 = load i8* %3, align 1		; <i8> [#uses=1]
+	%3 = getelementptr [4 x i8], [4 x i8]* %0, i32 %v0, i32 0		; <i8*> [#uses=1]
+	%4 = load i8, i8* %3, align 1		; <i8> [#uses=1]
 	%5 = zext i8 %4 to i32		; <i32> [#uses=1]
 	%6 = sub i32 %5, %2		; <i32> [#uses=1]
 	%7 = sitofp i32 %6 to float		; <float> [#uses=1]
diff --git a/test/CodeGen/Thumb2/2009-08-21-PostRAKill4.ll b/test/CodeGen/Thumb2/2009-08-21-PostRAKill4.ll
index 5cfc68d09408..04dcb9d03ad5 100644
--- a/test/CodeGen/Thumb2/2009-08-21-PostRAKill4.ll
+++ b/test/CodeGen/Thumb2/2009-08-21-PostRAKill4.ll
@@ -18,9 +18,9 @@ declare i32 @printf(i8* nocapture, ...) nounwind
 
 define i32 @main() nounwind {
 entry:
-  %0 = tail call  i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 1, i32 1, i32 1, i32 1, i32 1, i32 1) nounwind ; <i32> [#uses=0]
-  %1 = tail call  i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 -128, i32 116, i32 116, i32 -3852, i32 -31232, i32 -1708916736) nounwind ; <i32> [#uses=0]
-  %2 = tail call  i32 (i32, ...)* @getUnknown(i32 undef, i32 116, i32 116, i32 -3852, i32 -31232, i32 30556, i32 -1708916736) nounwind ; <i32> [#uses=1]
-  %3 = tail call  i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str2, i32 0, i32 0), i32 %2) nounwind ; <i32> [#uses=0]
+  %0 = tail call  i32 (i8*, ...) @printf(i8* getelementptr ([31 x i8], [31 x i8]* @.str1, i32 0, i32 0), i32 1, i32 1, i32 1, i32 1, i32 1, i32 1) nounwind ; <i32> [#uses=0]
+  %1 = tail call  i32 (i8*, ...) @printf(i8* getelementptr ([31 x i8], [31 x i8]* @.str1, i32 0, i32 0), i32 -128, i32 116, i32 116, i32 -3852, i32 -31232, i32 -1708916736) nounwind ; <i32> [#uses=0]
+  %2 = tail call  i32 (i32, ...) @getUnknown(i32 undef, i32 116, i32 116, i32 -3852, i32 -31232, i32 30556, i32 -1708916736) nounwind ; <i32> [#uses=1]
+  %3 = tail call  i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @.str2, i32 0, i32 0), i32 %2) nounwind ; <i32> [#uses=0]
   ret i32 0
 }
diff --git a/test/CodeGen/Thumb2/2009-09-01-PostRAProlog.ll b/test/CodeGen/Thumb2/2009-09-01-PostRAProlog.ll
index 06a152d56e4d..84f69f4b6e0b 100644
--- a/test/CodeGen/Thumb2/2009-09-01-PostRAProlog.ll
+++ b/test/CodeGen/Thumb2/2009-09-01-PostRAProlog.ll
@@ -37,25 +37,25 @@ declare i32 @getchar() nounwind
 define internal i32 @transpose() nounwind readonly {
 ; CHECK: push
 entry:
-  %0 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 1), align 4 ; <i32> [#uses=1]
+  %0 = load i32, i32* getelementptr inbounds ([128 x i32], [128 x i32]* @columns, i32 0, i32 1), align 4 ; <i32> [#uses=1]
   %1 = shl i32 %0, 7                              ; <i32> [#uses=1]
-  %2 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 2), align 4 ; <i32> [#uses=1]
+  %2 = load i32, i32* getelementptr inbounds ([128 x i32], [128 x i32]* @columns, i32 0, i32 2), align 4 ; <i32> [#uses=1]
   %3 = or i32 %1, %2                              ; <i32> [#uses=1]
   %4 = shl i32 %3, 7                              ; <i32> [#uses=1]
-  %5 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 3), align 4 ; <i32> [#uses=1]
+  %5 = load i32, i32* getelementptr inbounds ([128 x i32], [128 x i32]* @columns, i32 0, i32 3), align 4 ; <i32> [#uses=1]
   %6 = or i32 %4, %5                              ; <i32> [#uses=3]
-  %7 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 7), align 4 ; <i32> [#uses=1]
+  %7 = load i32, i32* getelementptr inbounds ([128 x i32], [128 x i32]* @columns, i32 0, i32 7), align 4 ; <i32> [#uses=1]
   %8 = shl i32 %7, 7                              ; <i32> [#uses=1]
-  %9 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 6), align 4 ; <i32> [#uses=1]
+  %9 = load i32, i32* getelementptr inbounds ([128 x i32], [128 x i32]* @columns, i32 0, i32 6), align 4 ; <i32> [#uses=1]
   %10 = or i32 %8, %9                             ; <i32> [#uses=1]
   %11 = shl i32 %10, 7                            ; <i32> [#uses=1]
-  %12 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 5), align 4 ; <i32> [#uses=1]
+  %12 = load i32, i32* getelementptr inbounds ([128 x i32], [128 x i32]* @columns, i32 0, i32 5), align 4 ; <i32> [#uses=1]
   %13 = or i32 %11, %12                           ; <i32> [#uses=3]
   %14 = icmp ugt i32 %6, %13                      ; <i1> [#uses=2]
   %.pn2.in.i = select i1 %14, i32 %6, i32 %13     ; <i32> [#uses=1]
   %.pn1.in.i = select i1 %14, i32 %13, i32 %6     ; <i32> [#uses=1]
   %.pn2.i = shl i32 %.pn2.in.i, 7                 ; <i32> [#uses=1]
-  %.pn3.i = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 4) ; <i32> [#uses=1]
+  %.pn3.i = load i32, i32* getelementptr inbounds ([128 x i32], [128 x i32]* @columns, i32 0, i32 4) ; <i32> [#uses=1]
   %.pn.in.in.i = or i32 %.pn2.i, %.pn3.i          ; <i32> [#uses=1]
   %.pn.in.i = zext i32 %.pn.in.in.i to i64        ; <i64> [#uses=1]
   %.pn.i = shl i64 %.pn.in.i, 21                  ; <i64> [#uses=1]
@@ -67,19 +67,19 @@ entry:
   %18 = trunc i64 %17 to i32                      ; <i32> [#uses=1]
   %19 = urem i32 %16, 179                         ; <i32> [#uses=1]
   %20 = or i32 %19, 131072                        ; <i32> [#uses=1]
-  %21 = load i32** @ht, align 4                   ; <i32*> [#uses=1]
+  %21 = load i32*, i32** @ht, align 4                   ; <i32*> [#uses=1]
   br label %bb5
 
 bb:                                               ; preds = %bb5
-  %22 = getelementptr inbounds i32* %21, i32 %x.0 ; <i32*> [#uses=1]
-  %23 = load i32* %22, align 4                    ; <i32> [#uses=1]
+  %22 = getelementptr inbounds i32, i32* %21, i32 %x.0 ; <i32*> [#uses=1]
+  %23 = load i32, i32* %22, align 4                    ; <i32> [#uses=1]
   %24 = icmp eq i32 %23, %16                      ; <i1> [#uses=1]
   br i1 %24, label %bb1, label %bb2
 
 bb1:                                              ; preds = %bb
-  %25 = load i8** @he, align 4                    ; <i8*> [#uses=1]
-  %26 = getelementptr inbounds i8* %25, i32 %x.0  ; <i8*> [#uses=1]
-  %27 = load i8* %26, align 1                     ; <i8> [#uses=1]
+  %25 = load i8*, i8** @he, align 4                    ; <i8*> [#uses=1]
+  %26 = getelementptr inbounds i8, i8* %25, i32 %x.0  ; <i8*> [#uses=1]
+  %27 = load i8, i8* %26, align 1                     ; <i8> [#uses=1]
   %28 = sext i8 %27 to i32                        ; <i32> [#uses=1]
   ret i32 %28
 
diff --git a/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll b/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
index a9a2478e4034..8fdff02f9c1b 100644
--- a/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
+++ b/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
@@ -25,8 +25,8 @@ if.then366:                                       ; preds = %lor.end, %lor.end
   unreachable
 
 if.end371:                                        ; preds = %lor.end
-  %arrayidx56.2.i = getelementptr [4 x %struct.pix_pos]* %pix_a.i294, i32 0, i32 2 ; <%struct.pix_pos*> [#uses=1]
-  %arrayidx56.3.i = getelementptr [4 x %struct.pix_pos]* %pix_a.i294, i32 0, i32 3 ; <%struct.pix_pos*> [#uses=1]
+  %arrayidx56.2.i = getelementptr [4 x %struct.pix_pos], [4 x %struct.pix_pos]* %pix_a.i294, i32 0, i32 2 ; <%struct.pix_pos*> [#uses=1]
+  %arrayidx56.3.i = getelementptr [4 x %struct.pix_pos], [4 x %struct.pix_pos]* %pix_a.i294, i32 0, i32 3 ; <%struct.pix_pos*> [#uses=1]
   br i1 undef, label %for.body1857, label %for.end4557
 
 for.body1857:                                     ; preds = %if.end371
@@ -44,13 +44,13 @@ for.body1940:                                     ; preds = %for.cond1933
   br i1 undef, label %if.then1992, label %if.else2003
 
 if.then1992:                                      ; preds = %for.body1940
-  %tmp14.i302 = load i32* undef                   ; <i32> [#uses=4]
+  %tmp14.i302 = load i32, i32* undef                   ; <i32> [#uses=4]
   %add.i307452 = or i32 %shl1959, 1               ; <i32> [#uses=1]
   %sub.i308 = add i32 %shl, -1                    ; <i32> [#uses=4]
   call  void undef(i32 %tmp14.i302, i32 %sub.i308, i32 %shl1959, i32 0, %struct.pix_pos* undef) nounwind
-  %tmp49.i309 = load void (i32, i32, i32, i32, %struct.pix_pos*)** @getNeighbour ; <void (i32, i32, i32, i32, %struct.pix_pos*)*> [#uses=1]
+  %tmp49.i309 = load void (i32, i32, i32, i32, %struct.pix_pos*)*, void (i32, i32, i32, i32, %struct.pix_pos*)** @getNeighbour ; <void (i32, i32, i32, i32, %struct.pix_pos*)*> [#uses=1]
   call  void %tmp49.i309(i32 %tmp14.i302, i32 %sub.i308, i32 %add.i307452, i32 0, %struct.pix_pos* null) nounwind
-  %tmp49.1.i = load void (i32, i32, i32, i32, %struct.pix_pos*)** @getNeighbour ; <void (i32, i32, i32, i32, %struct.pix_pos*)*> [#uses=1]
+  %tmp49.1.i = load void (i32, i32, i32, i32, %struct.pix_pos*)*, void (i32, i32, i32, i32, %struct.pix_pos*)** @getNeighbour ; <void (i32, i32, i32, i32, %struct.pix_pos*)*> [#uses=1]
   call  void %tmp49.1.i(i32 %tmp14.i302, i32 %sub.i308, i32 undef, i32 0, %struct.pix_pos* %arrayidx56.2.i) nounwind
   call  void undef(i32 %tmp14.i302, i32 %sub.i308, i32 undef, i32 0, %struct.pix_pos* %arrayidx56.3.i) nounwind
   unreachable
@@ -101,12 +101,12 @@ for.inc3040:                                      ; preds = %for.inc3040, %for.c
 if.then3689:                                      ; preds = %for.cond2882.preheader
   %add3695 = add nsw i32 %mul3693, %shl1959       ; <i32> [#uses=1]
   %mul3697 = shl i32 %add3695, 2                  ; <i32> [#uses=2]
-  %arrayidx3705 = getelementptr inbounds i16* undef, i32 1 ; <i16*> [#uses=1]
-  %tmp3706 = load i16* %arrayidx3705              ; <i16> [#uses=1]
+  %arrayidx3705 = getelementptr inbounds i16, i16* undef, i32 1 ; <i16*> [#uses=1]
+  %tmp3706 = load i16, i16* %arrayidx3705              ; <i16> [#uses=1]
   %conv3707 = sext i16 %tmp3706 to i32            ; <i32> [#uses=1]
   %add3708 = add nsw i32 %conv3707, %mul3697      ; <i32> [#uses=1]
-  %arrayidx3724 = getelementptr inbounds i16* null, i32 1 ; <i16*> [#uses=1]
-  %tmp3725 = load i16* %arrayidx3724              ; <i16> [#uses=1]
+  %arrayidx3724 = getelementptr inbounds i16, i16* null, i32 1 ; <i16*> [#uses=1]
+  %tmp3725 = load i16, i16* %arrayidx3724              ; <i16> [#uses=1]
   %conv3726 = sext i16 %tmp3725 to i32            ; <i32> [#uses=1]
   %add3727 = add nsw i32 %conv3726, %mul3697      ; <i32> [#uses=1]
   br label %if.end3770
@@ -115,11 +115,11 @@ if.else3728:                                      ; preds = %for.cond2882.prehea
   %mul3733 = add i32 %shl1959, 1073741816         ; <i32> [#uses=1]
   %add3735 = add nsw i32 %mul3733, %mul3693       ; <i32> [#uses=1]
   %mul3737 = shl i32 %add3735, 2                  ; <i32> [#uses=2]
-  %tmp3746 = load i16* undef                      ; <i16> [#uses=1]
+  %tmp3746 = load i16, i16* undef                      ; <i16> [#uses=1]
   %conv3747 = sext i16 %tmp3746 to i32            ; <i32> [#uses=1]
   %add3748 = add nsw i32 %conv3747, %mul3737      ; <i32> [#uses=1]
-  %arrayidx3765 = getelementptr inbounds i16* null, i32 1 ; <i16*> [#uses=1]
-  %tmp3766 = load i16* %arrayidx3765              ; <i16> [#uses=1]
+  %arrayidx3765 = getelementptr inbounds i16, i16* null, i32 1 ; <i16*> [#uses=1]
+  %tmp3766 = load i16, i16* %arrayidx3765              ; <i16> [#uses=1]
   %conv3767 = sext i16 %tmp3766 to i32            ; <i32> [#uses=1]
   %add3768 = add nsw i32 %conv3767, %mul3737      ; <i32> [#uses=1]
   br label %if.end3770
diff --git a/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll b/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll
index 956263b4fe2d..e283cb3434cc 100644
--- a/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll
+++ b/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll
@@ -7,7 +7,7 @@ declare void @Perl_mg_set(%struct.SV*) nounwind
 
 define %struct.OP* @Perl_pp_complement() nounwind {
 entry:
-  %0 = load %struct.SV** null, align 4            ; <%struct.SV*> [#uses=2]
+  %0 = load %struct.SV*, %struct.SV** null, align 4            ; <%struct.SV*> [#uses=2]
   br i1 undef, label %bb21, label %bb5
 
 bb5:                                              ; preds = %entry
@@ -17,15 +17,15 @@ bb6:                                              ; preds = %bb5
   br i1 undef, label %bb8, label %bb7
 
 bb7:                                              ; preds = %bb6
-  %1 = getelementptr inbounds %struct.SV* %0, i32 0, i32 0 ; <i8**> [#uses=1]
-  %2 = load i8** %1, align 4                      ; <i8*> [#uses=1]
-  %3 = getelementptr inbounds i8* %2, i32 12      ; <i8*> [#uses=1]
+  %1 = getelementptr inbounds %struct.SV, %struct.SV* %0, i32 0, i32 0 ; <i8**> [#uses=1]
+  %2 = load i8*, i8** %1, align 4                      ; <i8*> [#uses=1]
+  %3 = getelementptr inbounds i8, i8* %2, i32 12      ; <i8*> [#uses=1]
   %4 = bitcast i8* %3 to i32*                     ; <i32*> [#uses=1]
-  %5 = load i32* %4, align 4                      ; <i32> [#uses=1]
+  %5 = load i32, i32* %4, align 4                      ; <i32> [#uses=1]
   %storemerge5 = xor i32 %5, -1                   ; <i32> [#uses=1]
   call  void @Perl_sv_setiv(%struct.SV* undef, i32 %storemerge5) nounwind
-  %6 = getelementptr inbounds %struct.SV* undef, i32 0, i32 2 ; <i32*> [#uses=1]
-  %7 = load i32* %6, align 4                      ; <i32> [#uses=1]
+  %6 = getelementptr inbounds %struct.SV, %struct.SV* undef, i32 0, i32 2 ; <i32*> [#uses=1]
+  %7 = load i32, i32* %6, align 4                      ; <i32> [#uses=1]
   %8 = and i32 %7, 16384                          ; <i32> [#uses=1]
   %9 = icmp eq i32 %8, 0                          ; <i1> [#uses=1]
   br i1 %9, label %bb12, label %bb11
@@ -53,8 +53,8 @@ bb1.i:                                            ; preds = %bb13
   br label %Perl_sv_setuv.exit
 
 Perl_sv_setuv.exit:                               ; preds = %bb1.i, %bb.i
-  %11 = getelementptr inbounds %struct.SV* undef, i32 0, i32 2 ; <i32*> [#uses=1]
-  %12 = load i32* %11, align 4                    ; <i32> [#uses=1]
+  %11 = getelementptr inbounds %struct.SV, %struct.SV* undef, i32 0, i32 2 ; <i32*> [#uses=1]
+  %12 = load i32, i32* %11, align 4                    ; <i32> [#uses=1]
   %13 = and i32 %12, 16384                        ; <i32> [#uses=1]
   %14 = icmp eq i32 %13, 0                        ; <i1> [#uses=1]
   br i1 %14, label %bb20, label %bb19
diff --git a/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll b/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll
index 89b7148f5ecd..e59e84d49ecf 100644
--- a/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll
+++ b/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll
@@ -1,6 +1,8 @@
 ; RUN: opt < %s -O3 | \
 ; RUN:   llc -mtriple=thumbv7-apple-darwin10 -mattr=+neon | FileCheck %s
 
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+
 define void @fred(i32 %three_by_three, i8* %in, double %dt1, i32 %x_size, i32 %y_size, i8* %bp) nounwind {
 entry:
 ; -- The loop following the load should only use a single add-literation
@@ -43,16 +45,16 @@ entry:
   store i32 %x_size, i32* %x_size_addr
   store i32 %y_size, i32* %y_size_addr
   store i8* %bp, i8** %bp_addr
-  %0 = load i8** %in_addr, align 4                ; <i8*> [#uses=1]
+  %0 = load i8*, i8** %in_addr, align 4                ; <i8*> [#uses=1]
   store i8* %0, i8** %out, align 4
-  %1 = call  i32 (...)* @foo() nounwind ; <i32> [#uses=1]
+  %1 = call  i32 (...) @foo() nounwind ; <i32> [#uses=1]
   store i32 %1, i32* %i, align 4
-  %2 = load i32* %three_by_three_addr, align 4    ; <i32> [#uses=1]
+  %2 = load i32, i32* %three_by_three_addr, align 4    ; <i32> [#uses=1]
   %3 = icmp eq i32 %2, 0                          ; <i1> [#uses=1]
   br i1 %3, label %bb, label %bb2
 
 bb:                                               ; preds = %entry
-  %4 = load float* %dt_addr, align 4              ; <float> [#uses=1]
+  %4 = load float, float* %dt_addr, align 4              ; <float> [#uses=1]
   %5 = fpext float %4 to double                   ; <double> [#uses=1]
   %6 = fmul double %5, 1.500000e+00               ; <double> [#uses=1]
   %7 = fptosi double %6 to i32                    ; <i32> [#uses=1]
@@ -65,54 +67,54 @@ bb2:                                              ; preds = %entry
   br label %bb3
 
 bb3:                                              ; preds = %bb2, %bb
-  %9 = load i32* %mask_size, align 4              ; <i32> [#uses=1]
+  %9 = load i32, i32* %mask_size, align 4              ; <i32> [#uses=1]
   %10 = mul i32 %9, 2                             ; <i32> [#uses=1]
   %11 = add nsw i32 %10, 1                        ; <i32> [#uses=1]
   store i32 %11, i32* %n_max, align 4
-  %12 = load i32* %x_size_addr, align 4           ; <i32> [#uses=1]
-  %13 = load i32* %n_max, align 4                 ; <i32> [#uses=1]
+  %12 = load i32, i32* %x_size_addr, align 4           ; <i32> [#uses=1]
+  %13 = load i32, i32* %n_max, align 4                 ; <i32> [#uses=1]
   %14 = sub i32 %12, %13                          ; <i32> [#uses=1]
   store i32 %14, i32* %increment, align 4
-  %15 = load i32* %n_max, align 4                 ; <i32> [#uses=1]
-  %16 = load i32* %n_max, align 4                 ; <i32> [#uses=1]
+  %15 = load i32, i32* %n_max, align 4                 ; <i32> [#uses=1]
+  %16 = load i32, i32* %n_max, align 4                 ; <i32> [#uses=1]
   %17 = mul i32 %15, %16                          ; <i32> [#uses=1]
   %18 = call  noalias i8* @malloc(i32 %17) nounwind ; <i8*> [#uses=1]
   store i8* %18, i8** %dp, align 4
-  %19 = load i8** %dp, align 4                    ; <i8*> [#uses=1]
+  %19 = load i8*, i8** %dp, align 4                    ; <i8*> [#uses=1]
   store i8* %19, i8** %dpt, align 4
-  %20 = load float* %dt_addr, align 4             ; <float> [#uses=1]
-  %21 = load float* %dt_addr, align 4             ; <float> [#uses=1]
+  %20 = load float, float* %dt_addr, align 4             ; <float> [#uses=1]
+  %21 = load float, float* %dt_addr, align 4             ; <float> [#uses=1]
   %22 = fmul float %20, %21                       ; <float> [#uses=1]
   %23 = fsub float -0.000000e+00, %22             ; <float> [#uses=1]
   store float %23, float* %temp, align 4
-  %24 = load i32* %mask_size, align 4             ; <i32> [#uses=1]
+  %24 = load i32, i32* %mask_size, align 4             ; <i32> [#uses=1]
   %25 = sub i32 0, %24                            ; <i32> [#uses=1]
   store i32 %25, i32* %j, align 4
   br label %bb5
 
 bb4:                                              ; preds = %bb5
-  %26 = load i32* %j, align 4                     ; <i32> [#uses=1]
-  %27 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %26 = load i32, i32* %j, align 4                     ; <i32> [#uses=1]
+  %27 = load i32, i32* %j, align 4                     ; <i32> [#uses=1]
   %28 = mul i32 %26, %27                          ; <i32> [#uses=1]
   %29 = sitofp i32 %28 to double                  ; <double> [#uses=1]
   %30 = fmul double %29, 1.234000e+00             ; <double> [#uses=1]
   %31 = fptosi double %30 to i32                  ; <i32> [#uses=1]
   store i32 %31, i32* %x, align 4
-  %32 = load i32* %x, align 4                     ; <i32> [#uses=1]
+  %32 = load i32, i32* %x, align 4                     ; <i32> [#uses=1]
   %33 = trunc i32 %32 to i8                       ; <i8> [#uses=1]
-  %34 = load i8** %dpt, align 4                   ; <i8*> [#uses=1]
+  %34 = load i8*, i8** %dpt, align 4                   ; <i8*> [#uses=1]
   store i8 %33, i8* %34, align 1
-  %35 = load i8** %dpt, align 4                   ; <i8*> [#uses=1]
-  %36 = getelementptr inbounds i8* %35, i64 1     ; <i8*> [#uses=1]
+  %35 = load i8*, i8** %dpt, align 4                   ; <i8*> [#uses=1]
+  %36 = getelementptr inbounds i8, i8* %35, i64 1     ; <i8*> [#uses=1]
   store i8* %36, i8** %dpt, align 4
-  %37 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %37 = load i32, i32* %j, align 4                     ; <i32> [#uses=1]
   %38 = add nsw i32 %37, 1                        ; <i32> [#uses=1]
   store i32 %38, i32* %j, align 4
   br label %bb5
 
 bb5:                                              ; preds = %bb4, %bb3
-  %39 = load i32* %j, align 4                     ; <i32> [#uses=1]
-  %40 = load i32* %mask_size, align 4             ; <i32> [#uses=1]
+  %39 = load i32, i32* %j, align 4                     ; <i32> [#uses=1]
+  %40 = load i32, i32* %mask_size, align 4             ; <i32> [#uses=1]
   %41 = icmp sle i32 %39, %40                     ; <i1> [#uses=1]
   br i1 %41, label %bb4, label %bb6
 
diff --git a/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll b/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll
index 348e9d3f20a7..56206ef77336 100644
--- a/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll
+++ b/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll
@@ -19,8 +19,8 @@ target triple = "thumbv7-apple-darwin10"
 
 define %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache22CreateCacheIfNecessaryEv() nounwind {
 entry:
-  %0 = tail call  i32 @pthread_mutex_lock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind
-  %.b24 = load i1* @_ZN3WTFL10tsd_initedE.b, align 4 ; <i1> [#uses=1]
+  %0 = tail call  i32 @pthread_mutex_lock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock, %struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind
+  %.b24 = load i1, i1* @_ZN3WTFL10tsd_initedE.b, align 4 ; <i1> [#uses=1]
   br i1 %.b24, label %bb5, label %bb6
 
 bb5:                                              ; preds = %entry
@@ -32,19 +32,19 @@ bb6:                                              ; preds = %bb5, %entry
   br label %bb11
 
 bb7:                                              ; preds = %bb11
-  %2 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache"* %h.0, i32 0, i32 1
-  %3 = load %struct._opaque_pthread_t** %2, align 4
+  %2 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache", %"struct.WTF::TCMalloc_ThreadCache"* %h.0, i32 0, i32 1
+  %3 = load %struct._opaque_pthread_t*, %struct._opaque_pthread_t** %2, align 4
   %4 = tail call  i32 @pthread_equal(%struct._opaque_pthread_t* %3, %struct._opaque_pthread_t* %me.0) nounwind
   %5 = icmp eq i32 %4, 0
   br i1 %5, label %bb10, label %bb14
 
 bb10:                                             ; preds = %bb7
-  %6 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache"* %h.0, i32 0, i32 6
+  %6 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache", %"struct.WTF::TCMalloc_ThreadCache"* %h.0, i32 0, i32 6
   br label %bb11
 
 bb11:                                             ; preds = %bb10, %bb6
   %h.0.in = phi %"struct.WTF::TCMalloc_ThreadCache"** [ @_ZN3WTFL12thread_heapsE, %bb6 ], [ %6, %bb10 ] ; <%"struct.WTF::TCMalloc_ThreadCache"**> [#uses=1]
-  %h.0 = load %"struct.WTF::TCMalloc_ThreadCache"** %h.0.in, align 4 ; <%"struct.WTF::TCMalloc_ThreadCache"*> [#uses=4]
+  %h.0 = load %"struct.WTF::TCMalloc_ThreadCache"*, %"struct.WTF::TCMalloc_ThreadCache"** %h.0.in, align 4 ; <%"struct.WTF::TCMalloc_ThreadCache"*> [#uses=4]
   %7 = icmp eq %"struct.WTF::TCMalloc_ThreadCache"* %h.0, null
   br i1 %7, label %bb13, label %bb7
 
@@ -54,19 +54,19 @@ bb13:                                             ; preds = %bb11
 
 bb14:                                             ; preds = %bb13, %bb7
   %heap.1 = phi %"struct.WTF::TCMalloc_ThreadCache"* [ %8, %bb13 ], [ %h.0, %bb7 ] ; <%"struct.WTF::TCMalloc_ThreadCache"*> [#uses=4]
-  %9 = tail call  i32 @pthread_mutex_unlock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind
-  %10 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache"* %heap.1, i32 0, i32 2
-  %11 = load i8* %10, align 4
+  %9 = tail call  i32 @pthread_mutex_unlock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock, %struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind
+  %10 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache", %"struct.WTF::TCMalloc_ThreadCache"* %heap.1, i32 0, i32 2
+  %11 = load i8, i8* %10, align 4
   %toBool15not = icmp eq i8 %11, 0                ; <i1> [#uses=1]
   br i1 %toBool15not, label %bb19, label %bb22
 
 bb19:                                             ; preds = %bb14
-  %.b = load i1* @_ZN3WTFL10tsd_initedE.b, align 4 ; <i1> [#uses=1]
+  %.b = load i1, i1* @_ZN3WTFL10tsd_initedE.b, align 4 ; <i1> [#uses=1]
   br i1 %.b, label %bb21, label %bb22
 
 bb21:                                             ; preds = %bb19
   store i8 1, i8* %10, align 4
-  %12 = load i32* @_ZN3WTFL8heap_keyE, align 4
+  %12 = load i32, i32* @_ZN3WTFL8heap_keyE, align 4
   %13 = bitcast %"struct.WTF::TCMalloc_ThreadCache"* %heap.1 to i8*
   %14 = tail call  i32 @pthread_setspecific(i32 %12, i8* %13) nounwind
   ret %"struct.WTF::TCMalloc_ThreadCache"* %heap.1
diff --git a/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll b/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll
index 771a4f813634..a20d36ba5ed3 100644
--- a/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll
+++ b/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll
@@ -47,7 +47,7 @@ bb35:                                             ; preds = %bb5
 
 bb46:                                             ; preds = %bb26, %bb10
   %1 = bitcast double* %value to i16*             ; <i16*> [#uses=1]
-  %v47 = getelementptr inbounds [6 x i16]* %v, i32 0, i32 0 ; <i16*> [#uses=1]
+  %v47 = getelementptr inbounds [6 x i16], [6 x i16]* %v, i32 0, i32 0 ; <i16*> [#uses=1]
   call  void @etoe53(i16* %v47, i16* %1) nounwind
   ret void
 }
diff --git a/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll b/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll
index 7ce3c2586677..7d19d15f2a30 100644
--- a/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll
+++ b/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll
@@ -70,7 +70,7 @@ bb163:                                            ; preds = %bb162, %bb161
   unreachable
 
 bb224:                                            ; preds = %bb162
-  %0 = call  i32 @SyFopen(i8* undef, i8* getelementptr inbounds ([2 x i8]* @.str41196, i32 0, i32 0)) nounwind ; <i32> [#uses=2]
+  %0 = call  i32 @SyFopen(i8* undef, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str41196, i32 0, i32 0)) nounwind ; <i32> [#uses=2]
   br i1 false, label %bb297, label %bb300
 
 bb297:                                            ; preds = %bb224
@@ -138,8 +138,8 @@ bb345:                                            ; preds = %bb345, %bb339
   %4 = phi i8 [ %5, %bb345 ], [ undef, %bb339 ]   ; <i8> [#uses=0]
   %indvar670 = phi i32 [ %tmp673, %bb345 ], [ 0, %bb339 ] ; <i32> [#uses=1]
   %tmp673 = add i32 %indvar670, 1                 ; <i32> [#uses=2]
-  %scevgep674 = getelementptr [256 x i8]* %last, i32 0, i32 %tmp673 ; <i8*> [#uses=1]
-  %5 = load i8* %scevgep674, align 1              ; <i8> [#uses=1]
+  %scevgep674 = getelementptr [256 x i8], [256 x i8]* %last, i32 0, i32 %tmp673 ; <i8*> [#uses=1]
+  %5 = load i8, i8* %scevgep674, align 1              ; <i8> [#uses=1]
   br i1 undef, label %bb347, label %bb345
 
 bb347:                                            ; preds = %bb345
@@ -166,8 +166,8 @@ bb362:                                            ; preds = %bb361
 bb366:                                            ; preds = %bb366, %bb360
   %indvar662 = phi i32 [ %tmp665, %bb366 ], [ 0, %bb360 ] ; <i32> [#uses=1]
   %tmp665 = add i32 %indvar662, 1                 ; <i32> [#uses=2]
-  %scevgep666 = getelementptr [256 x i8]* %last2, i32 0, i32 %tmp665 ; <i8*> [#uses=1]
-  %6 = load i8* %scevgep666, align 1              ; <i8> [#uses=0]
+  %scevgep666 = getelementptr [256 x i8], [256 x i8]* %last2, i32 0, i32 %tmp665 ; <i8*> [#uses=1]
+  %6 = load i8, i8* %scevgep666, align 1              ; <i8> [#uses=0]
   br i1 false, label %bb368, label %bb366
 
 bb368:                                            ; preds = %bb366
@@ -189,7 +189,7 @@ bb376:                                            ; preds = %bb375
   ret void
 
 bb383:                                            ; preds = %bb373
-  %10 = load i8* undef, align 1                   ; <i8> [#uses=1]
+  %10 = load i8, i8* undef, align 1                   ; <i8> [#uses=1]
   %cond1 = icmp eq i8 %10, 46                     ; <i1> [#uses=1]
   br i1 %cond1, label %bb373, label %bb388
 
@@ -203,7 +203,7 @@ bb390:                                            ; preds = %isdigit1498.exit83,
 
 bb391:                                            ; preds = %bb390, %bb388
   %indvar724 = phi i32 [ %indvar.next725, %bb390 ], [ 0, %bb388 ] ; <i32> [#uses=2]
-  %11 = load i8* undef, align 1                   ; <i8> [#uses=0]
+  %11 = load i8, i8* undef, align 1                   ; <i8> [#uses=0]
   br i1 false, label %bb395, label %bb392
 
 bb392:                                            ; preds = %bb391
@@ -217,7 +217,7 @@ bb394:                                            ; preds = %isdigit1498.exit87
 
 bb395:                                            ; preds = %bb394, %isdigit1498.exit83, %bb391
   %storemerge14.sum = add i32 %indvar724, undef   ; <i32> [#uses=1]
-  %p.26 = getelementptr [256 x i8]* %line, i32 0, i32 %storemerge14.sum ; <i8*> [#uses=1]
+  %p.26 = getelementptr [256 x i8], [256 x i8]* %line, i32 0, i32 %storemerge14.sum ; <i8*> [#uses=1]
   br i1 undef, label %bb400, label %isdigit1498.exit87
 
 isdigit1498.exit87:                               ; preds = %bb395
@@ -227,7 +227,7 @@ bb400:                                            ; preds = %isdigit1498.exit87,
   br i1 undef, label %bb402, label %bb403
 
 bb402:                                            ; preds = %bb400
-  %12 = getelementptr inbounds i8* %p.26, i32 undef ; <i8*> [#uses=1]
+  %12 = getelementptr inbounds i8, i8* %p.26, i32 undef ; <i8*> [#uses=1]
   br label %bb403
 
 bb403:                                            ; preds = %bb402, %bb400
diff --git a/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll b/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll
index fcf1bae796b0..d3a44957a2eb 100644
--- a/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll
+++ b/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll
@@ -20,23 +20,23 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-
 ; CHECK: InlineAsm Start
 define void @test(%s1* %this, i32 %format, i32 %w, i32 %h, i32 %levels, i32* %s, i8* %data, i32* nocapture %rowbytes, void (i8*, i8*)* %release, i8* %info) nounwind {
 entry:
-  %tmp1 = getelementptr inbounds %s1* %this, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0
+  %tmp1 = getelementptr inbounds %s1, %s1* %this, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0
   store volatile i32 1, i32* %tmp1, align 4
-  %tmp12 = getelementptr inbounds %s1* %this, i32 0, i32 1
+  %tmp12 = getelementptr inbounds %s1, %s1* %this, i32 0, i32 1
   store i32 %levels, i32* %tmp12, align 4
-  %tmp13 = getelementptr inbounds %s1* %this, i32 0, i32 3
+  %tmp13 = getelementptr inbounds %s1, %s1* %this, i32 0, i32 3
   store i8* %data, i8** %tmp13, align 4
-  %tmp14 = getelementptr inbounds %s1* %this, i32 0, i32 4
+  %tmp14 = getelementptr inbounds %s1, %s1* %this, i32 0, i32 4
   store void (i8*, i8*)* %release, void (i8*, i8*)** %tmp14, align 4
-  %tmp15 = getelementptr inbounds %s1* %this, i32 0, i32 5
+  %tmp15 = getelementptr inbounds %s1, %s1* %this, i32 0, i32 5
   store i8* %info, i8** %tmp15, align 4
-  %tmp16 = getelementptr inbounds %s1* %this, i32 0, i32 6
+  %tmp16 = getelementptr inbounds %s1, %s1* %this, i32 0, i32 6
   store i32* null, i32** %tmp16, align 4
-  %tmp17 = getelementptr inbounds %s1* %this, i32 0, i32 7
+  %tmp17 = getelementptr inbounds %s1, %s1* %this, i32 0, i32 7
   store i32* null, i32** %tmp17, align 4
-  %tmp19 = getelementptr inbounds %s1* %this, i32 0, i32 10
+  %tmp19 = getelementptr inbounds %s1, %s1* %this, i32 0, i32 10
   store i64 0, i64* %tmp19, align 4
-  %tmp20 = getelementptr inbounds %s1* %this, i32 0, i32 0
+  %tmp20 = getelementptr inbounds %s1, %s1* %this, i32 0, i32 0
   tail call  void @f1(%s3* %tmp20, i32* %s) nounwind
   %tmp21 = shl i32 %format, 6
   %tmp22 = tail call  zeroext i8 @f2(i32 %format) nounwind
@@ -45,16 +45,16 @@ entry:
   %flags.0 = or i32 %tmp23, %tmp21
   %tmp24 = shl i32 %flags.0, 16
   %asmtmp.i.i.i = tail call %0 asm sideeffect "\0A0:\09ldrex $1, [$2]\0A\09orr $1, $1, $3\0A\09strex $0, $1, [$2]\0A\09cmp $0, #0\0A\09bne 0b", "=&r,=&r,r,r,~{memory},~{cc}"(i32* %tmp1, i32 %tmp24) nounwind
-  %tmp25 = getelementptr inbounds %s1* %this, i32 0, i32 2, i32 0, i32 0
+  %tmp25 = getelementptr inbounds %s1, %s1* %this, i32 0, i32 2, i32 0, i32 0
   store volatile i32 1, i32* %tmp25, align 4
   %tmp26 = icmp eq i32 %levels, 0
   br i1 %tmp26, label %return, label %bb4
 
 bb4:
   %l.09 = phi i32 [ %tmp28, %bb4 ], [ 0, %entry ]
-  %scevgep = getelementptr %s1* %this, i32 0, i32 11, i32 %l.09
-  %scevgep10 = getelementptr i32* %rowbytes, i32 %l.09
-  %tmp27 = load i32* %scevgep10, align 4
+  %scevgep = getelementptr %s1, %s1* %this, i32 0, i32 11, i32 %l.09
+  %scevgep10 = getelementptr i32, i32* %rowbytes, i32 %l.09
+  %tmp27 = load i32, i32* %scevgep10, align 4
   store i32 %tmp27, i32* %scevgep, align 4
   %tmp28 = add i32 %l.09, 1
   %exitcond = icmp eq i32 %tmp28, %levels
diff --git a/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll b/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll
index 06762bad854f..24a995a11538 100644
--- a/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll
+++ b/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll
@@ -32,10 +32,10 @@ entry:
   %tmp7 = extractelement <2 x double> %5, i32 0   ; <double> [#uses=1]
   %tmp5 = extractelement <2 x double> %5, i32 1   ; <double> [#uses=1]
 ; CHECK: printf
-  %7 = tail call  i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), double %tmp7, double %tmp5) nounwind ; <i32> [#uses=0]
+  %7 = tail call  i32 (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), double %tmp7, double %tmp5) nounwind ; <i32> [#uses=0]
   %tmp3 = extractelement <2 x double> %6, i32 0   ; <double> [#uses=1]
   %tmp1 = extractelement <2 x double> %6, i32 1   ; <double> [#uses=1]
-  %8 = tail call  i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), double %tmp3, double %tmp1) nounwind ; <i32> [#uses=0]
+  %8 = tail call  i32 (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), double %tmp3, double %tmp1) nounwind ; <i32> [#uses=0]
   ret i32 0
 }
 
diff --git a/test/CodeGen/Thumb2/2010-06-19-ITBlockCrash.ll b/test/CodeGen/Thumb2/2010-06-19-ITBlockCrash.ll
index 501f763bda28..eba2e584ddc0 100644
--- a/test/CodeGen/Thumb2/2010-06-19-ITBlockCrash.ll
+++ b/test/CodeGen/Thumb2/2010-06-19-ITBlockCrash.ll
@@ -18,7 +18,7 @@ bb1.i.i11:                                        ; preds = %bb11
   %1 = tail call arm_apcscc  i32 @__maskrune(i32 %0, i32 32768) nounwind ; <i32> [#uses=1]
   %2 = icmp ne i32 %1, 0                          ; <i1> [#uses=1]
   %3 = zext i1 %2 to i32                          ; <i32> [#uses=1]
-  %.pre = load i8* undef, align 1                 ; <i8> [#uses=1]
+  %.pre = load i8, i8* undef, align 1                 ; <i8> [#uses=1]
   br label %isupper144.exit12
 
 isupper144.exit12:                                ; preds = %bb1.i.i11, %bb.i.i10
diff --git a/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
index f3046e1fcb82..34569e9116f2 100644
--- a/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
+++ b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
@@ -86,17 +86,17 @@ bb10:                                             ; preds = %bb9
 
 bb11:                                             ; preds = %bb10, %bb9
   %p.0 = phi i8* [ undef, %bb10 ], [ %p.1, %bb9 ] ; <i8*> [#uses=1]
-  %0 = load %struct.FILE** @finput, align 4       ; <%struct.FILE*> [#uses=1]
+  %0 = load %struct.FILE*, %struct.FILE** @finput, align 4       ; <%struct.FILE*> [#uses=1]
   %1 = tail call i32 @getc(%struct.FILE* %0) nounwind ; <i32> [#uses=0]
   br label %bb12
 
 bb12:                                             ; preds = %bb11, %bb.i.i
-  %p.1 = phi i8* [ %p.0, %bb11 ], [ getelementptr inbounds ([1025 x i8]* @token_buffer, i32 0, i32 0), %bb.i.i ] ; <i8*> [#uses=2]
+  %p.1 = phi i8* [ %p.0, %bb11 ], [ getelementptr inbounds ([1025 x i8], [1025 x i8]* @token_buffer, i32 0, i32 0), %bb.i.i ] ; <i8*> [#uses=2]
   %2 = icmp ult i32 undef, 128                    ; <i1> [#uses=1]
   br i1 %2, label %bb.i.i2, label %bb1.i.i3
 
 bb.i.i2:                                          ; preds = %bb12
-  %3 = load i32* null, align 4                    ; <i32> [#uses=1]
+  %3 = load i32, i32* null, align 4                    ; <i32> [#uses=1]
   %4 = lshr i32 %3, 8                             ; <i32> [#uses=1]
   %.lobit.i1 = and i32 %4, 1                      ; <i32> [#uses=1]
   %.not = icmp ne i32 %.lobit.i1, 0               ; <i1> [#uses=1]
diff --git a/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll b/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll
index 547950fb17f0..3b14d22ddbff 100644
--- a/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll
+++ b/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll
@@ -14,9 +14,9 @@ entry:
 
 bb:                                               ; preds = %entry
   %1 = alloca [1000 x i8], align 4                ; <[1000 x i8]*> [#uses=1]
-  %.sub = getelementptr inbounds [1000 x i8]* %1, i32 0, i32 0 ; <i8*> [#uses=2]
-  %2 = call i32 (i8*, i32, i32, i8*, ...)* @__sprintf_chk(i8* %.sub, i32 0, i32 1000, i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 %i) nounwind ; <i32> [#uses=0]
-  %3 = load i8* %.sub, align 4                    ; <i8> [#uses=1]
+  %.sub = getelementptr inbounds [1000 x i8], [1000 x i8]* %1, i32 0, i32 0 ; <i8*> [#uses=2]
+  %2 = call i32 (i8*, i32, i32, i8*, ...) @__sprintf_chk(i8* %.sub, i32 0, i32 1000, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %i) nounwind ; <i32> [#uses=0]
+  %3 = load i8, i8* %.sub, align 4                    ; <i8> [#uses=1]
   %4 = sext i8 %3 to i32                          ; <i32> [#uses=1]
   ret i32 %4
 
@@ -52,7 +52,7 @@ bb2:                                              ; preds = %bb
 ; CHECK-NOT: mov sp, r7
 ; CHECK-NOT: sub sp, #12
 ; CHECK: pop
-  %4 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 %2) nounwind ; <i32> [#uses=0]
+  %4 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %2) nounwind ; <i32> [#uses=0]
   ret i32 0
 }
 
diff --git a/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll b/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll
index 240df83252cc..b9bfdcbec4e4 100644
--- a/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll
+++ b/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll
@@ -3,13 +3,13 @@
 %struct.op = type { %struct.op*, %struct.op*, %struct.op* ()*, i32, i16, i16, i8, i8 }
 
 ; CHECK: Perl_ck_sort
-; CHECK: ldreq
-; CHECK: moveq [[REGISTER:(r[0-9]+)|(lr)]]
-; CHECK: streq {{(r[0-9])|(lr)}}, {{\[}}[[REGISTER]]{{\]}}, #24
+; CHECK: ldr
+; CHECK: mov [[REGISTER:(r[0-9]+)|(lr)]]
+; CHECK: str {{(r[0-9])|(lr)}}, {{\[}}[[REGISTER]]{{\]}}, #24
 
 define void @Perl_ck_sort() nounwind optsize {
 entry:
-  %tmp27 = load %struct.op** undef, align 4
+  %tmp27 = load %struct.op*, %struct.op** undef, align 4
   switch i16 undef, label %if.end151 [
     i16 178, label %if.then60
     i16 177, label %if.then60
@@ -19,14 +19,14 @@ if.then60:                                        ; preds = %if.then40
   br i1 undef, label %if.then67, label %if.end95
 
 if.then67:                                        ; preds = %if.then60
-  %op_next71 = getelementptr inbounds %struct.op* %tmp27, i32 0, i32 0
+  %op_next71 = getelementptr inbounds %struct.op, %struct.op* %tmp27, i32 0, i32 0
   store %struct.op* %tmp27, %struct.op** %op_next71, align 4
-  %0 = getelementptr inbounds %struct.op* %tmp27, i32 1, i32 0
+  %0 = getelementptr inbounds %struct.op, %struct.op* %tmp27, i32 1, i32 0
   br label %if.end95
 
 if.end95:                                         ; preds = %if.else92, %if.then67
   %.pre-phi = phi %struct.op** [ undef, %if.then60 ], [ %0, %if.then67 ]
-  %tmp98 = load %struct.op** %.pre-phi, align 4
+  %tmp98 = load %struct.op*, %struct.op** %.pre-phi, align 4
   br label %if.end151
 
 if.end151:                                        ; preds = %if.end100, %if.end, %entry
diff --git a/test/CodeGen/Thumb2/2011-12-16-T2SizeReduceAssert.ll b/test/CodeGen/Thumb2/2011-12-16-T2SizeReduceAssert.ll
index ea8d233e79f1..7c8802ddad67 100644
--- a/test/CodeGen/Thumb2/2011-12-16-T2SizeReduceAssert.ll
+++ b/test/CodeGen/Thumb2/2011-12-16-T2SizeReduceAssert.ll
@@ -8,15 +8,15 @@ entry:
   br label %bb3
 
 bb:                                               ; preds = %bb3
-  %Scan.0.idx7.val = load i8** undef, align 4
-  %.idx = getelementptr i8* %Scan.0.idx7.val, i32 4
+  %Scan.0.idx7.val = load i8*, i8** undef, align 4
+  %.idx = getelementptr i8, i8* %Scan.0.idx7.val, i32 4
   %0 = bitcast i8* %.idx to i8**
-  %.idx.val = load i8** %0, align 4
+  %.idx.val = load i8*, i8** %0, align 4
   %1 = icmp eq i8* %.idx.val, %Key
   br i1 %1, label %bb5, label %bb2
 
 bb2:                                              ; preds = %bb
-  %Scan.0.idx8.val = load %struct.LIST_NODE.0.16** undef, align 4
+  %Scan.0.idx8.val = load %struct.LIST_NODE.0.16*, %struct.LIST_NODE.0.16** undef, align 4
   br label %bb3
 
 bb3:                                              ; preds = %bb2, %entry
@@ -34,7 +34,7 @@ entry:
   br i1 undef, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.body, %entry
-  %0 = load double* null, align 8
+  %0 = load double, double* null, align 8
   %cmp2.6 = fcmp ogt double %0, 0.000000e+00
   %idx.1.6 = select i1 %cmp2.6, i32 undef, i32 0
   %idx.1.7 = select i1 undef, i32 undef, i32 %idx.1.6
diff --git a/test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll b/test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll
index 500871519234..9121044be4ff 100644
--- a/test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll
+++ b/test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll
@@ -22,16 +22,16 @@ tailrecurse:                                      ; preds = %if.then10, %entry
   br i1 %cmp, label %if.end11, label %if.end
 
 if.end:                                           ; preds = %tailrecurse
-  %string = getelementptr inbounds %struct.Dict_node_struct* %dn.tr, i32 0, i32 0
-  %0 = load i8** %string, align 4
+  %string = getelementptr inbounds %struct.Dict_node_struct, %struct.Dict_node_struct* %dn.tr, i32 0, i32 0
+  %0 = load i8*, i8** %string, align 4
   br label %while.cond.i
 
 while.cond.i:                                     ; preds = %while.body.i, %if.end
   %1 = phi i8* [ %s, %if.end ], [ %incdec.ptr.i, %while.body.i ]
   %storemerge.i = phi i8* [ %0, %if.end ], [ %incdec.ptr6.i, %while.body.i ]
-  %2 = load i8* %1, align 1
+  %2 = load i8, i8* %1, align 1
   %cmp.i = icmp eq i8 %2, 0
-  %.pre.i = load i8* %storemerge.i, align 1
+  %.pre.i = load i8, i8* %storemerge.i, align 1
   br i1 %cmp.i, label %lor.lhs.false.i, label %land.end.i
 
 land.end.i:                                       ; preds = %while.cond.i
@@ -39,8 +39,8 @@ land.end.i:                                       ; preds = %while.cond.i
   br i1 %cmp4.i, label %while.body.i, label %while.end.i
 
 while.body.i:                                     ; preds = %land.end.i
-  %incdec.ptr.i = getelementptr inbounds i8* %1, i32 1
-  %incdec.ptr6.i = getelementptr inbounds i8* %storemerge.i, i32 1
+  %incdec.ptr.i = getelementptr inbounds i8, i8* %1, i32 1
+  %incdec.ptr6.i = getelementptr inbounds i8, i8* %storemerge.i, i32 1
   br label %while.cond.i
 
 while.end.i:                                      ; preds = %land.end.i
@@ -68,8 +68,8 @@ if.end3:                                          ; preds = %dict_match.exit, %l
 ; CHECK: cmp
 ; CHECK-NOT: cbnz
   %storemerge1.i3 = phi i32 [ %sub.i, %dict_match.exit ], [ 0, %lor.lhs.false.i ], [ 0, %while.end.i ]
-  %right = getelementptr inbounds %struct.Dict_node_struct* %dn.tr, i32 0, i32 4
-  %4 = load %struct.Dict_node_struct** %right, align 4
+  %right = getelementptr inbounds %struct.Dict_node_struct, %struct.Dict_node_struct* %dn.tr, i32 0, i32 4
+  %4 = load %struct.Dict_node_struct*, %struct.Dict_node_struct** %right, align 4
   tail call fastcc void @rdictionary_lookup(%struct.Dict_node_struct* %4, i8* %s)
   %cmp4 = icmp eq i32 %storemerge1.i3, 0
   br i1 %cmp4, label %if.then5, label %if.end8
@@ -79,8 +79,8 @@ if.then5:                                         ; preds = %if.end3
   %5 = bitcast i8* %call6 to %struct.Dict_node_struct*
   %6 = bitcast %struct.Dict_node_struct* %dn.tr to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %call6, i8* %6, i32 16, i32 4, i1 false)
-  %7 = load %struct.Dict_node_struct** @lookup_list, align 4
-  %right7 = getelementptr inbounds i8* %call6, i32 16
+  %7 = load %struct.Dict_node_struct*, %struct.Dict_node_struct** @lookup_list, align 4
+  %right7 = getelementptr inbounds i8, i8* %call6, i32 16
   %8 = bitcast i8* %right7 to %struct.Dict_node_struct**
   store %struct.Dict_node_struct* %7, %struct.Dict_node_struct** %8, align 4
   store %struct.Dict_node_struct* %5, %struct.Dict_node_struct** @lookup_list, align 4
@@ -91,8 +91,8 @@ if.end8:                                          ; preds = %if.end3
   br i1 %cmp9, label %if.then10, label %if.end11
 
 if.then10:                                        ; preds = %if.end8, %if.then5, %dict_match.exit
-  %left = getelementptr inbounds %struct.Dict_node_struct* %dn.tr, i32 0, i32 3
-  %9 = load %struct.Dict_node_struct** %left, align 4
+  %left = getelementptr inbounds %struct.Dict_node_struct, %struct.Dict_node_struct* %dn.tr, i32 0, i32 3
+  %9 = load %struct.Dict_node_struct*, %struct.Dict_node_struct** %left, align 4
   br label %tailrecurse
 
 if.end11:                                         ; preds = %if.end8, %tailrecurse
diff --git a/test/CodeGen/Thumb2/2013-02-19-tail-call-register-hint.ll b/test/CodeGen/Thumb2/2013-02-19-tail-call-register-hint.ll
index e905cb9114c2..c9d3f3dd2847 100644
--- a/test/CodeGen/Thumb2/2013-02-19-tail-call-register-hint.ll
+++ b/test/CodeGen/Thumb2/2013-02-19-tail-call-register-hint.ll
@@ -12,19 +12,19 @@
 %struct.foo = type { i32, [40 x i8] }
 
 define hidden void @func(i8* %Data) nounwind ssp {
-  %1 = getelementptr inbounds i8* %Data, i32 12
+  %1 = getelementptr inbounds i8, i8* %Data, i32 12
   %2 = bitcast i8* %1 to %"myclass"*
   tail call void @abc(%"myclass"* %2) nounwind
   tail call void @def(%"myclass"* %2) nounwind
-  %3 = getelementptr inbounds i8* %Data, i32 8
+  %3 = getelementptr inbounds i8, i8* %Data, i32 8
   %4 = bitcast i8* %3 to i8**
-  %5 = load i8** %4, align 4
+  %5 = load i8*, i8** %4, align 4
   tail call void @ghi(i8* %5) nounwind
   %6 = bitcast i8* %Data to void (i8*)**
-  %7 = load void (i8*)** %6, align 4
-  %8 = getelementptr inbounds i8* %Data, i32 4
+  %7 = load void (i8*)*, void (i8*)** %6, align 4
+  %8 = getelementptr inbounds i8, i8* %Data, i32 4
   %9 = bitcast i8* %8 to i8**
-  %10 = load i8** %9, align 4
+  %10 = load i8*, i8** %9, align 4
   %11 = icmp eq i8* %Data, null
   br i1 %11, label %14, label %12
 
diff --git a/test/CodeGen/Thumb2/2013-03-02-vduplane-nonconstant-source-index.ll b/test/CodeGen/Thumb2/2013-03-02-vduplane-nonconstant-source-index.ll
index 937ecc0d6679..5936b7803002 100644
--- a/test/CodeGen/Thumb2/2013-03-02-vduplane-nonconstant-source-index.ll
+++ b/test/CodeGen/Thumb2/2013-03-02-vduplane-nonconstant-source-index.ll
@@ -1,9 +1,9 @@
 ; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
 
 define void @bar(<4 x i32>* %p, i32 %lane, <4 x i32> %phitmp) nounwind {
-; CHECK:  vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[SOURCE:[0-9]+]]:128]
-; CHECK:  add.w r[[ADDR:[0-9]+]], r[[SOURCE]], {{r[0-9]+}}, lsl #2
-; CHECK:  vld1.32 {[[DREG:d[0-9]+]][], [[DREG2:d[0-9]+]][]}, [r[[ADDR]]:32]
+; CHECK:  lsls r[[ADDR:[0-9]+]], r[[ADDR]], #2
+; CHECK:  vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[SOURCE:[0-9]+]]:128], r[[ADDR]]
+; CHECK:  vld1.32 {[[DREG:d[0-9]+]][], [[DREG2:d[0-9]+]][]}, [r[[SOURCE]]:32]
 ; CHECK:  vst1.32 {[[DREG]], [[DREG2]]}, [r0]
   %val = extractelement <4 x i32> %phitmp, i32 %lane
   %r1 = insertelement <4 x i32> undef, i32 %val, i32 1
diff --git a/test/CodeGen/Thumb2/aligned-constants.ll b/test/CodeGen/Thumb2/aligned-constants.ll
index 16b3a193c9d7..13cca113452c 100644
--- a/test/CodeGen/Thumb2/aligned-constants.ll
+++ b/test/CodeGen/Thumb2/aligned-constants.ll
@@ -16,10 +16,10 @@ target triple = "thumbv7-apple-ios"
 ; CHECK:	.long	1123477881
 define void @func(float* nocapture %x, double* nocapture %y) nounwind ssp {
 entry:
-  %0 = load float* %x, align 4
+  %0 = load float, float* %x, align 4
   %add = fadd float %0, 0x405EDD2F20000000
   store float %add, float* %x, align 4
-  %1 = load double* %y, align 4
+  %1 = load double, double* %y, align 4
   %add1 = fadd double %1, 2.234560e+02
   store double %add1, double* %y, align 4
   ret void
diff --git a/test/CodeGen/Thumb2/aligned-spill.ll b/test/CodeGen/Thumb2/aligned-spill.ll
index 4ef294bdf5ff..59f546b8e8e6 100644
--- a/test/CodeGen/Thumb2/aligned-spill.ll
+++ b/test/CodeGen/Thumb2/aligned-spill.ll
@@ -13,7 +13,7 @@ target triple = "thumbv7-apple-ios"
 ; CHECK: mov sp, r4
 define void @f(double* nocapture %p) nounwind ssp {
 entry:
-  %0 = load double* %p, align 4
+  %0 = load double, double* %p, align 4
   tail call void asm sideeffect "", "~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15}"() nounwind
   tail call void @g() nounwind
   store double %0, double* %p, align 4
diff --git a/test/CodeGen/Thumb2/bfi.ll b/test/CodeGen/Thumb2/bfi.ll
index 4f056d571c4c..337f46a22748 100644
--- a/test/CodeGen/Thumb2/bfi.ll
+++ b/test/CodeGen/Thumb2/bfi.ll
@@ -9,7 +9,7 @@ entry:
 ; CHECK: f1
 ; CHECK: movs r2, #10
 ; CHECK: bfi r1, r2, #22, #4
-  %0 = load i32* bitcast (%struct.F* @X to i32*), align 4 ; <i32> [#uses=1]
+  %0 = load i32, i32* bitcast (%struct.F* @X to i32*), align 4 ; <i32> [#uses=1]
   %1 = and i32 %0, -62914561                      ; <i32> [#uses=1]
   %2 = or i32 %1, 41943040                        ; <i32> [#uses=1]
   store i32 %2, i32* bitcast (%struct.F* @X to i32*), align 4
diff --git a/test/CodeGen/Thumb2/cbnz.ll b/test/CodeGen/Thumb2/cbnz.ll
new file mode 100644
index 000000000000..5c0bb5bfe1cd
--- /dev/null
+++ b/test/CodeGen/Thumb2/cbnz.ll
@@ -0,0 +1,54 @@
+; RUN: llc -mtriple thumbv7-unknown-linux -o - %s | FileCheck %s
+
+declare void @x()
+declare void @y()
+
+define void @f(i32 %x, i32 %y) {
+  ; CHECK-LABEL: f:
+  ; CHECK: cbnz
+  %p = icmp eq i32 %x, 0
+  br i1 %p, label %t, label %f
+
+t:
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  ; CHECK: cbnz
+  %q = icmp eq i32 %y, 0
+  br i1 %q, label %t2, label %f
+
+t2:
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  call void @x()
+  br label %f
+
+f:
+  call void @y()
+  ret void
+}
diff --git a/test/CodeGen/Thumb2/constant-islands-new-island-padding.ll b/test/CodeGen/Thumb2/constant-islands-new-island-padding.ll
index 991b043f0bdc..c2a2c068ca48 100644
--- a/test/CodeGen/Thumb2/constant-islands-new-island-padding.ll
+++ b/test/CodeGen/Thumb2/constant-islands-new-island-padding.ll
@@ -15,22 +15,22 @@ declare i32 @llvm.arm.space(i32, i32)
 
 define i32 @testpadding(i32 %a) {
 entry:
-  %0 = load i32* @g0, align 4
+  %0 = load i32, i32* @g0, align 4
   %add = add nsw i32 %0, 12
   store i32 %add, i32* @g0, align 4
-  %1 = load double* @d0, align 8
+  %1 = load double, double* @d0, align 8
   %add1 = fadd double %1, 0x3FF3C0B8ED46EACB
   store double %add1, double* @d0, align 8
   %tmpcall11 = call i32 @llvm.arm.space(i32 28, i32 undef)
   call void @foo20(i32 191)
-  %2 = load float* @f0, align 4
+  %2 = load float, float* @f0, align 4
   %add2 = fadd float %2, 0x3FF3C0BDC0000000
   store float %add2, float* @f0, align 4
   br label %do.body
 
 do.body:                                          ; preds = %do.body, %entry
   tail call void @foo20(i32 19)
-  %3 = load i32* @g1, align 4
+  %3 = load i32, i32* @g1, align 4
   %tobool = icmp eq i32 %3, 0
   br i1 %tobool, label %do.end, label %do.body
 
diff --git a/test/CodeGen/Thumb2/constant-islands.ll b/test/CodeGen/Thumb2/constant-islands.ll
index 255b709edb73..a64d72e86efb 100644
--- a/test/CodeGen/Thumb2/constant-islands.ll
+++ b/test/CodeGen/Thumb2/constant-islands.ll
@@ -262,170 +262,170 @@ entry:
   store %class.btDynamicsWorld* %ownerWorld, %class.btDynamicsWorld** %ownerWorld.addr, align 4
   store %class.btVector3* %positionOffset, %class.btVector3** %positionOffset.addr, align 4
   store float %scale, float* %scale.addr, align 4
-  %this1 = load %class.RagDoll** %this.addr
+  %this1 = load %class.RagDoll*, %class.RagDoll** %this.addr
   store %class.RagDoll* %this1, %class.RagDoll** %retval
   %0 = bitcast %class.RagDoll* %this1 to i8***
-  store i8** getelementptr inbounds ([4 x i8*]* @_ZTV7RagDoll, i64 0, i64 2), i8*** %0
-  %m_ownerWorld = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 1
-  %1 = load %class.btDynamicsWorld** %ownerWorld.addr, align 4
+  store i8** getelementptr inbounds ([4 x i8*], [4 x i8*]* @_ZTV7RagDoll, i64 0, i64 2), i8*** %0
+  %m_ownerWorld = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 1
+  %1 = load %class.btDynamicsWorld*, %class.btDynamicsWorld** %ownerWorld.addr, align 4
   store %class.btDynamicsWorld* %1, %class.btDynamicsWorld** %m_ownerWorld, align 4
   %call = call i8* @_ZN13btConvexShapenwEm(i32 56)
   %2 = bitcast i8* %call to %class.btCapsuleShape*
-  %3 = load float* %scale.addr, align 4
+  %3 = load float, float* %scale.addr, align 4
   %mul = fmul float 0x3FC3333340000000, %3
-  %4 = load float* %scale.addr, align 4
+  %4 = load float, float* %scale.addr, align 4
   %mul2 = fmul float 0x3FC99999A0000000, %4
   %call3 = invoke %class.btCapsuleShape* @_ZN14btCapsuleShapeC1Eff(%class.btCapsuleShape* %2, float %mul, float %mul2)
           to label %invoke.cont unwind label %lpad
 
 invoke.cont:                                      ; preds = %entry
   %5 = bitcast %class.btCapsuleShape* %2 to %class.btCollisionShape*
-  %m_shapes = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes, i32 0, i32 0
+  %m_shapes = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes, i32 0, i32 0
   store %class.btCollisionShape* %5, %class.btCollisionShape** %arrayidx, align 4
   %call5 = call i8* @_ZN13btConvexShapenwEm(i32 56)
   %6 = bitcast i8* %call5 to %class.btCapsuleShape*
-  %7 = load float* %scale.addr, align 4
+  %7 = load float, float* %scale.addr, align 4
   %mul6 = fmul float 0x3FC3333340000000, %7
-  %8 = load float* %scale.addr, align 4
+  %8 = load float, float* %scale.addr, align 4
   %mul7 = fmul float 0x3FD1EB8520000000, %8
   %call10 = invoke %class.btCapsuleShape* @_ZN14btCapsuleShapeC1Eff(%class.btCapsuleShape* %6, float %mul6, float %mul7)
           to label %invoke.cont9 unwind label %lpad8
 
 invoke.cont9:                                     ; preds = %invoke.cont
   %9 = bitcast %class.btCapsuleShape* %6 to %class.btCollisionShape*
-  %m_shapes12 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx13 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes12, i32 0, i32 1
+  %m_shapes12 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx13 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes12, i32 0, i32 1
   store %class.btCollisionShape* %9, %class.btCollisionShape** %arrayidx13, align 4
   %call14 = call i8* @_ZN13btConvexShapenwEm(i32 56)
   %10 = bitcast i8* %call14 to %class.btCapsuleShape*
-  %11 = load float* %scale.addr, align 4
+  %11 = load float, float* %scale.addr, align 4
   %mul15 = fmul float 0x3FB99999A0000000, %11
-  %12 = load float* %scale.addr, align 4
+  %12 = load float, float* %scale.addr, align 4
   %mul16 = fmul float 0x3FA99999A0000000, %12
   %call19 = invoke %class.btCapsuleShape* @_ZN14btCapsuleShapeC1Eff(%class.btCapsuleShape* %10, float %mul15, float %mul16)
           to label %invoke.cont18 unwind label %lpad17
 
 invoke.cont18:                                    ; preds = %invoke.cont9
   %13 = bitcast %class.btCapsuleShape* %10 to %class.btCollisionShape*
-  %m_shapes21 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx22 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes21, i32 0, i32 2
+  %m_shapes21 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx22 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes21, i32 0, i32 2
   store %class.btCollisionShape* %13, %class.btCollisionShape** %arrayidx22, align 4
   %call23 = call i8* @_ZN13btConvexShapenwEm(i32 56)
   %14 = bitcast i8* %call23 to %class.btCapsuleShape*
-  %15 = load float* %scale.addr, align 4
+  %15 = load float, float* %scale.addr, align 4
   %mul24 = fmul float 0x3FB1EB8520000000, %15
-  %16 = load float* %scale.addr, align 4
+  %16 = load float, float* %scale.addr, align 4
   %mul25 = fmul float 0x3FDCCCCCC0000000, %16
   %call28 = invoke %class.btCapsuleShape* @_ZN14btCapsuleShapeC1Eff(%class.btCapsuleShape* %14, float %mul24, float %mul25)
           to label %invoke.cont27 unwind label %lpad26
 
 invoke.cont27:                                    ; preds = %invoke.cont18
   %17 = bitcast %class.btCapsuleShape* %14 to %class.btCollisionShape*
-  %m_shapes30 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx31 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes30, i32 0, i32 3
+  %m_shapes30 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx31 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes30, i32 0, i32 3
   store %class.btCollisionShape* %17, %class.btCollisionShape** %arrayidx31, align 4
   %call32 = call i8* @_ZN13btConvexShapenwEm(i32 56)
   %18 = bitcast i8* %call32 to %class.btCapsuleShape*
-  %19 = load float* %scale.addr, align 4
+  %19 = load float, float* %scale.addr, align 4
   %mul33 = fmul float 0x3FA99999A0000000, %19
-  %20 = load float* %scale.addr, align 4
+  %20 = load float, float* %scale.addr, align 4
   %mul34 = fmul float 0x3FD7AE1480000000, %20
   %call37 = invoke %class.btCapsuleShape* @_ZN14btCapsuleShapeC1Eff(%class.btCapsuleShape* %18, float %mul33, float %mul34)
           to label %invoke.cont36 unwind label %lpad35
 
 invoke.cont36:                                    ; preds = %invoke.cont27
   %21 = bitcast %class.btCapsuleShape* %18 to %class.btCollisionShape*
-  %m_shapes39 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx40 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes39, i32 0, i32 4
+  %m_shapes39 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx40 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes39, i32 0, i32 4
   store %class.btCollisionShape* %21, %class.btCollisionShape** %arrayidx40, align 4
   %call41 = call i8* @_ZN13btConvexShapenwEm(i32 56)
   %22 = bitcast i8* %call41 to %class.btCapsuleShape*
-  %23 = load float* %scale.addr, align 4
+  %23 = load float, float* %scale.addr, align 4
   %mul42 = fmul float 0x3FB1EB8520000000, %23
-  %24 = load float* %scale.addr, align 4
+  %24 = load float, float* %scale.addr, align 4
   %mul43 = fmul float 0x3FDCCCCCC0000000, %24
   %call46 = invoke %class.btCapsuleShape* @_ZN14btCapsuleShapeC1Eff(%class.btCapsuleShape* %22, float %mul42, float %mul43)
           to label %invoke.cont45 unwind label %lpad44
 
 invoke.cont45:                                    ; preds = %invoke.cont36
   %25 = bitcast %class.btCapsuleShape* %22 to %class.btCollisionShape*
-  %m_shapes48 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx49 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes48, i32 0, i32 5
+  %m_shapes48 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx49 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes48, i32 0, i32 5
   store %class.btCollisionShape* %25, %class.btCollisionShape** %arrayidx49, align 4
   %call50 = call i8* @_ZN13btConvexShapenwEm(i32 56)
   %26 = bitcast i8* %call50 to %class.btCapsuleShape*
-  %27 = load float* %scale.addr, align 4
+  %27 = load float, float* %scale.addr, align 4
   %mul51 = fmul float 0x3FA99999A0000000, %27
-  %28 = load float* %scale.addr, align 4
+  %28 = load float, float* %scale.addr, align 4
   %mul52 = fmul float 0x3FD7AE1480000000, %28
   %call55 = invoke %class.btCapsuleShape* @_ZN14btCapsuleShapeC1Eff(%class.btCapsuleShape* %26, float %mul51, float %mul52)
           to label %invoke.cont54 unwind label %lpad53
 
 invoke.cont54:                                    ; preds = %invoke.cont45
   %29 = bitcast %class.btCapsuleShape* %26 to %class.btCollisionShape*
-  %m_shapes57 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx58 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes57, i32 0, i32 6
+  %m_shapes57 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx58 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes57, i32 0, i32 6
   store %class.btCollisionShape* %29, %class.btCollisionShape** %arrayidx58, align 4
   %call59 = call i8* @_ZN13btConvexShapenwEm(i32 56)
   %30 = bitcast i8* %call59 to %class.btCapsuleShape*
-  %31 = load float* %scale.addr, align 4
+  %31 = load float, float* %scale.addr, align 4
   %mul60 = fmul float 0x3FA99999A0000000, %31
-  %32 = load float* %scale.addr, align 4
+  %32 = load float, float* %scale.addr, align 4
   %mul61 = fmul float 0x3FD51EB860000000, %32
   %call64 = invoke %class.btCapsuleShape* @_ZN14btCapsuleShapeC1Eff(%class.btCapsuleShape* %30, float %mul60, float %mul61)
           to label %invoke.cont63 unwind label %lpad62
 
 invoke.cont63:                                    ; preds = %invoke.cont54
   %33 = bitcast %class.btCapsuleShape* %30 to %class.btCollisionShape*
-  %m_shapes66 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx67 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes66, i32 0, i32 7
+  %m_shapes66 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx67 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes66, i32 0, i32 7
   store %class.btCollisionShape* %33, %class.btCollisionShape** %arrayidx67, align 4
   %call68 = call i8* @_ZN13btConvexShapenwEm(i32 56)
   %34 = bitcast i8* %call68 to %class.btCapsuleShape*
-  %35 = load float* %scale.addr, align 4
+  %35 = load float, float* %scale.addr, align 4
   %mul69 = fmul float 0x3FA47AE140000000, %35
-  %36 = load float* %scale.addr, align 4
+  %36 = load float, float* %scale.addr, align 4
   %mul70 = fmul float 2.500000e-01, %36
   %call73 = invoke %class.btCapsuleShape* @_ZN14btCapsuleShapeC1Eff(%class.btCapsuleShape* %34, float %mul69, float %mul70)
           to label %invoke.cont72 unwind label %lpad71
 
 invoke.cont72:                                    ; preds = %invoke.cont63
   %37 = bitcast %class.btCapsuleShape* %34 to %class.btCollisionShape*
-  %m_shapes75 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx76 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes75, i32 0, i32 8
+  %m_shapes75 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx76 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes75, i32 0, i32 8
   store %class.btCollisionShape* %37, %class.btCollisionShape** %arrayidx76, align 4
   %call77 = call i8* @_ZN13btConvexShapenwEm(i32 56)
   %38 = bitcast i8* %call77 to %class.btCapsuleShape*
-  %39 = load float* %scale.addr, align 4
+  %39 = load float, float* %scale.addr, align 4
   %mul78 = fmul float 0x3FA99999A0000000, %39
-  %40 = load float* %scale.addr, align 4
+  %40 = load float, float* %scale.addr, align 4
   %mul79 = fmul float 0x3FD51EB860000000, %40
   %call82 = invoke %class.btCapsuleShape* @_ZN14btCapsuleShapeC1Eff(%class.btCapsuleShape* %38, float %mul78, float %mul79)
           to label %invoke.cont81 unwind label %lpad80
 
 invoke.cont81:                                    ; preds = %invoke.cont72
   %41 = bitcast %class.btCapsuleShape* %38 to %class.btCollisionShape*
-  %m_shapes84 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx85 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes84, i32 0, i32 9
+  %m_shapes84 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx85 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes84, i32 0, i32 9
   store %class.btCollisionShape* %41, %class.btCollisionShape** %arrayidx85, align 4
   %call86 = call i8* @_ZN13btConvexShapenwEm(i32 56)
   %42 = bitcast i8* %call86 to %class.btCapsuleShape*
-  %43 = load float* %scale.addr, align 4
+  %43 = load float, float* %scale.addr, align 4
   %mul87 = fmul float 0x3FA47AE140000000, %43
-  %44 = load float* %scale.addr, align 4
+  %44 = load float, float* %scale.addr, align 4
   %mul88 = fmul float 2.500000e-01, %44
   %call91 = invoke %class.btCapsuleShape* @_ZN14btCapsuleShapeC1Eff(%class.btCapsuleShape* %42, float %mul87, float %mul88)
           to label %invoke.cont90 unwind label %lpad89
 
 invoke.cont90:                                    ; preds = %invoke.cont81
   %45 = bitcast %class.btCapsuleShape* %42 to %class.btCollisionShape*
-  %m_shapes93 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx94 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes93, i32 0, i32 10
+  %m_shapes93 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx94 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes93, i32 0, i32 10
   store %class.btCollisionShape* %45, %class.btCollisionShape** %arrayidx94, align 4
   %call95 = call %class.btTransform* @_ZN11btTransformC1Ev(%class.btTransform* %offset)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %offset)
-  %46 = load %class.btVector3** %positionOffset.addr, align 4
+  %46 = load %class.btVector3*, %class.btVector3** %positionOffset.addr, align 4
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %offset, %class.btVector3* %46)
   %call96 = call %class.btTransform* @_ZN11btTransformC1Ev(%class.btTransform* %transform)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %transform)
@@ -436,12 +436,12 @@ invoke.cont90:                                    ; preds = %invoke.cont81
   call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp, float* %scale.addr, %class.btVector3* %ref.tmp97)
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp)
   call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp102, %class.btTransform* %offset, %class.btTransform* %transform)
-  %m_shapes103 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx104 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes103, i32 0, i32 0
-  %47 = load %class.btCollisionShape** %arrayidx104, align 4
+  %m_shapes103 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx104 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes103, i32 0, i32 0
+  %47 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx104, align 4
   %call105 = call %class.btRigidBody* @_ZN7RagDoll20localCreateRigidBodyEfRK11btTransformP16btCollisionShape(%class.RagDoll* %this1, float 1.000000e+00, %class.btTransform* %ref.tmp102, %class.btCollisionShape* %47)
-  %m_bodies = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx106 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies, i32 0, i32 0
+  %m_bodies = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx106 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies, i32 0, i32 0
   store %class.btRigidBody* %call105, %class.btRigidBody** %arrayidx106, align 4
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %transform)
   store float 0.000000e+00, float* %ref.tmp109, align 4
@@ -451,12 +451,12 @@ invoke.cont90:                                    ; preds = %invoke.cont81
   call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp107, float* %scale.addr, %class.btVector3* %ref.tmp108)
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp107)
   call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp113, %class.btTransform* %offset, %class.btTransform* %transform)
-  %m_shapes114 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx115 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes114, i32 0, i32 1
-  %48 = load %class.btCollisionShape** %arrayidx115, align 4
+  %m_shapes114 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx115 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes114, i32 0, i32 1
+  %48 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx115, align 4
   %call116 = call %class.btRigidBody* @_ZN7RagDoll20localCreateRigidBodyEfRK11btTransformP16btCollisionShape(%class.RagDoll* %this1, float 1.000000e+00, %class.btTransform* %ref.tmp113, %class.btCollisionShape* %48)
-  %m_bodies117 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx118 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies117, i32 0, i32 1
+  %m_bodies117 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx118 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies117, i32 0, i32 1
   store %class.btRigidBody* %call116, %class.btRigidBody** %arrayidx118, align 4
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %transform)
   store float 0.000000e+00, float* %ref.tmp121, align 4
@@ -466,12 +466,12 @@ invoke.cont90:                                    ; preds = %invoke.cont81
   call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp119, float* %scale.addr, %class.btVector3* %ref.tmp120)
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp119)
   call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp125, %class.btTransform* %offset, %class.btTransform* %transform)
-  %m_shapes126 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx127 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes126, i32 0, i32 2
-  %49 = load %class.btCollisionShape** %arrayidx127, align 4
+  %m_shapes126 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx127 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes126, i32 0, i32 2
+  %49 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx127, align 4
   %call128 = call %class.btRigidBody* @_ZN7RagDoll20localCreateRigidBodyEfRK11btTransformP16btCollisionShape(%class.RagDoll* %this1, float 1.000000e+00, %class.btTransform* %ref.tmp125, %class.btCollisionShape* %49)
-  %m_bodies129 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx130 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies129, i32 0, i32 2
+  %m_bodies129 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx130 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies129, i32 0, i32 2
   store %class.btRigidBody* %call128, %class.btRigidBody** %arrayidx130, align 4
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %transform)
   store float 0xBFC70A3D80000000, float* %ref.tmp133, align 4
@@ -481,12 +481,12 @@ invoke.cont90:                                    ; preds = %invoke.cont81
   call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp131, float* %scale.addr, %class.btVector3* %ref.tmp132)
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp131)
   call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp137, %class.btTransform* %offset, %class.btTransform* %transform)
-  %m_shapes138 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx139 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes138, i32 0, i32 3
-  %50 = load %class.btCollisionShape** %arrayidx139, align 4
+  %m_shapes138 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx139 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes138, i32 0, i32 3
+  %50 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx139, align 4
   %call140 = call %class.btRigidBody* @_ZN7RagDoll20localCreateRigidBodyEfRK11btTransformP16btCollisionShape(%class.RagDoll* %this1, float 1.000000e+00, %class.btTransform* %ref.tmp137, %class.btCollisionShape* %50)
-  %m_bodies141 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx142 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies141, i32 0, i32 3
+  %m_bodies141 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx142 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies141, i32 0, i32 3
   store %class.btRigidBody* %call140, %class.btRigidBody** %arrayidx142, align 4
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %transform)
   store float 0xBFC70A3D80000000, float* %ref.tmp145, align 4
@@ -496,12 +496,12 @@ invoke.cont90:                                    ; preds = %invoke.cont81
   call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp143, float* %scale.addr, %class.btVector3* %ref.tmp144)
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp143)
   call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp149, %class.btTransform* %offset, %class.btTransform* %transform)
-  %m_shapes150 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx151 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes150, i32 0, i32 4
-  %51 = load %class.btCollisionShape** %arrayidx151, align 4
+  %m_shapes150 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx151 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes150, i32 0, i32 4
+  %51 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx151, align 4
   %call152 = call %class.btRigidBody* @_ZN7RagDoll20localCreateRigidBodyEfRK11btTransformP16btCollisionShape(%class.RagDoll* %this1, float 1.000000e+00, %class.btTransform* %ref.tmp149, %class.btCollisionShape* %51)
-  %m_bodies153 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx154 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies153, i32 0, i32 4
+  %m_bodies153 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx154 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies153, i32 0, i32 4
   store %class.btRigidBody* %call152, %class.btRigidBody** %arrayidx154, align 4
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %transform)
   store float 0x3FC70A3D80000000, float* %ref.tmp157, align 4
@@ -511,12 +511,12 @@ invoke.cont90:                                    ; preds = %invoke.cont81
   call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp155, float* %scale.addr, %class.btVector3* %ref.tmp156)
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp155)
   call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp161, %class.btTransform* %offset, %class.btTransform* %transform)
-  %m_shapes162 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx163 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes162, i32 0, i32 5
-  %52 = load %class.btCollisionShape** %arrayidx163, align 4
+  %m_shapes162 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx163 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes162, i32 0, i32 5
+  %52 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx163, align 4
   %call164 = call %class.btRigidBody* @_ZN7RagDoll20localCreateRigidBodyEfRK11btTransformP16btCollisionShape(%class.RagDoll* %this1, float 1.000000e+00, %class.btTransform* %ref.tmp161, %class.btCollisionShape* %52)
-  %m_bodies165 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx166 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies165, i32 0, i32 5
+  %m_bodies165 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx166 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies165, i32 0, i32 5
   store %class.btRigidBody* %call164, %class.btRigidBody** %arrayidx166, align 4
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %transform)
   store float 0x3FC70A3D80000000, float* %ref.tmp169, align 4
@@ -526,12 +526,12 @@ invoke.cont90:                                    ; preds = %invoke.cont81
   call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp167, float* %scale.addr, %class.btVector3* %ref.tmp168)
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp167)
   call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp173, %class.btTransform* %offset, %class.btTransform* %transform)
-  %m_shapes174 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx175 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes174, i32 0, i32 6
-  %53 = load %class.btCollisionShape** %arrayidx175, align 4
+  %m_shapes174 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx175 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes174, i32 0, i32 6
+  %53 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx175, align 4
   %call176 = call %class.btRigidBody* @_ZN7RagDoll20localCreateRigidBodyEfRK11btTransformP16btCollisionShape(%class.RagDoll* %this1, float 1.000000e+00, %class.btTransform* %ref.tmp173, %class.btCollisionShape* %53)
-  %m_bodies177 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx178 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies177, i32 0, i32 6
+  %m_bodies177 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx178 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies177, i32 0, i32 6
   store %class.btRigidBody* %call176, %class.btRigidBody** %arrayidx178, align 4
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %transform)
   store float 0xBFD6666660000000, float* %ref.tmp181, align 4
@@ -543,12 +543,12 @@ invoke.cont90:                                    ; preds = %invoke.cont81
   %call185 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %transform)
   call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call185, float 0.000000e+00, float 0.000000e+00, float 0x3FF921FB60000000)
   call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp186, %class.btTransform* %offset, %class.btTransform* %transform)
-  %m_shapes187 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx188 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes187, i32 0, i32 7
-  %54 = load %class.btCollisionShape** %arrayidx188, align 4
+  %m_shapes187 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx188 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes187, i32 0, i32 7
+  %54 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx188, align 4
   %call189 = call %class.btRigidBody* @_ZN7RagDoll20localCreateRigidBodyEfRK11btTransformP16btCollisionShape(%class.RagDoll* %this1, float 1.000000e+00, %class.btTransform* %ref.tmp186, %class.btCollisionShape* %54)
-  %m_bodies190 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx191 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies190, i32 0, i32 7
+  %m_bodies190 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx191 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies190, i32 0, i32 7
   store %class.btRigidBody* %call189, %class.btRigidBody** %arrayidx191, align 4
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %transform)
   store float 0xBFE6666660000000, float* %ref.tmp194, align 4
@@ -560,12 +560,12 @@ invoke.cont90:                                    ; preds = %invoke.cont81
   %call198 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %transform)
   call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call198, float 0.000000e+00, float 0.000000e+00, float 0x3FF921FB60000000)
   call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp199, %class.btTransform* %offset, %class.btTransform* %transform)
-  %m_shapes200 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx201 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes200, i32 0, i32 8
-  %55 = load %class.btCollisionShape** %arrayidx201, align 4
+  %m_shapes200 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx201 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes200, i32 0, i32 8
+  %55 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx201, align 4
   %call202 = call %class.btRigidBody* @_ZN7RagDoll20localCreateRigidBodyEfRK11btTransformP16btCollisionShape(%class.RagDoll* %this1, float 1.000000e+00, %class.btTransform* %ref.tmp199, %class.btCollisionShape* %55)
-  %m_bodies203 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx204 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies203, i32 0, i32 8
+  %m_bodies203 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx204 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies203, i32 0, i32 8
   store %class.btRigidBody* %call202, %class.btRigidBody** %arrayidx204, align 4
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %transform)
   store float 0x3FD6666660000000, float* %ref.tmp207, align 4
@@ -577,12 +577,12 @@ invoke.cont90:                                    ; preds = %invoke.cont81
   %call211 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %transform)
   call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call211, float 0.000000e+00, float 0.000000e+00, float 0xBFF921FB60000000)
   call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp212, %class.btTransform* %offset, %class.btTransform* %transform)
-  %m_shapes213 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx214 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes213, i32 0, i32 9
-  %56 = load %class.btCollisionShape** %arrayidx214, align 4
+  %m_shapes213 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx214 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes213, i32 0, i32 9
+  %56 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx214, align 4
   %call215 = call %class.btRigidBody* @_ZN7RagDoll20localCreateRigidBodyEfRK11btTransformP16btCollisionShape(%class.RagDoll* %this1, float 1.000000e+00, %class.btTransform* %ref.tmp212, %class.btCollisionShape* %56)
-  %m_bodies216 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx217 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies216, i32 0, i32 9
+  %m_bodies216 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx217 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies216, i32 0, i32 9
   store %class.btRigidBody* %call215, %class.btRigidBody** %arrayidx217, align 4
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %transform)
   store float 0x3FE6666660000000, float* %ref.tmp220, align 4
@@ -594,42 +594,42 @@ invoke.cont90:                                    ; preds = %invoke.cont81
   %call224 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %transform)
   call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call224, float 0.000000e+00, float 0.000000e+00, float 0xBFF921FB60000000)
   call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp225, %class.btTransform* %offset, %class.btTransform* %transform)
-  %m_shapes226 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 2
-  %arrayidx227 = getelementptr inbounds [11 x %class.btCollisionShape*]* %m_shapes226, i32 0, i32 10
-  %57 = load %class.btCollisionShape** %arrayidx227, align 4
+  %m_shapes226 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2
+  %arrayidx227 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes226, i32 0, i32 10
+  %57 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx227, align 4
   %call228 = call %class.btRigidBody* @_ZN7RagDoll20localCreateRigidBodyEfRK11btTransformP16btCollisionShape(%class.RagDoll* %this1, float 1.000000e+00, %class.btTransform* %ref.tmp225, %class.btCollisionShape* %57)
-  %m_bodies229 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx230 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies229, i32 0, i32 10
+  %m_bodies229 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx230 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies229, i32 0, i32 10
   store %class.btRigidBody* %call228, %class.btRigidBody** %arrayidx230, align 4
   store i32 0, i32* %i, align 4
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %invoke.cont90
-  %58 = load i32* %i, align 4
+  %58 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %58, 11
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %59 = load i32* %i, align 4
-  %m_bodies231 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx232 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies231, i32 0, i32 %59
-  %60 = load %class.btRigidBody** %arrayidx232, align 4
+  %59 = load i32, i32* %i, align 4
+  %m_bodies231 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx232 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies231, i32 0, i32 %59
+  %60 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx232, align 4
   call void @_ZN11btRigidBody10setDampingEff(%class.btRigidBody* %60, float 0x3FA99999A0000000, float 0x3FEB333340000000)
-  %61 = load i32* %i, align 4
-  %m_bodies233 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx234 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies233, i32 0, i32 %61
-  %62 = load %class.btRigidBody** %arrayidx234, align 4
+  %61 = load i32, i32* %i, align 4
+  %m_bodies233 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx234 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies233, i32 0, i32 %61
+  %62 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx234, align 4
   %63 = bitcast %class.btRigidBody* %62 to %class.btCollisionObject*
   call void @_ZN17btCollisionObject19setDeactivationTimeEf(%class.btCollisionObject* %63, float 0x3FE99999A0000000)
-  %64 = load i32* %i, align 4
-  %m_bodies235 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx236 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies235, i32 0, i32 %64
-  %65 = load %class.btRigidBody** %arrayidx236, align 4
+  %64 = load i32, i32* %i, align 4
+  %m_bodies235 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx236 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies235, i32 0, i32 %64
+  %65 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx236, align 4
   call void @_ZN11btRigidBody21setSleepingThresholdsEff(%class.btRigidBody* %65, float 0x3FF99999A0000000, float 2.500000e+00)
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %66 = load i32* %i, align 4
+  %66 = load i32, i32* %i, align 4
   %inc = add nsw i32 %66, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
@@ -800,33 +800,33 @@ for.end:                                          ; preds = %for.cond
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp247)
   %call253 = call noalias i8* @_Znwm(i32 780)
   %100 = bitcast i8* %call253 to %class.btHingeConstraint*
-  %m_bodies254 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx255 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies254, i32 0, i32 0
-  %101 = load %class.btRigidBody** %arrayidx255, align 4
-  %m_bodies256 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx257 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies256, i32 0, i32 1
-  %102 = load %class.btRigidBody** %arrayidx257, align 4
+  %m_bodies254 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx255 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies254, i32 0, i32 0
+  %101 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx255, align 4
+  %m_bodies256 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx257 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies256, i32 0, i32 1
+  %102 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx257, align 4
   %call260 = invoke %class.btHingeConstraint* @_ZN17btHingeConstraintC1ER11btRigidBodyS1_RK11btTransformS4_b(%class.btHingeConstraint* %100, %class.btRigidBody* %101, %class.btRigidBody* %102, %class.btTransform* %localA, %class.btTransform* %localB, i1 zeroext false)
           to label %invoke.cont259 unwind label %lpad258
 
 invoke.cont259:                                   ; preds = %for.end
   store %class.btHingeConstraint* %100, %class.btHingeConstraint** %hingeC, align 4
-  %103 = load %class.btHingeConstraint** %hingeC, align 4
+  %103 = load %class.btHingeConstraint*, %class.btHingeConstraint** %hingeC, align 4
   call void @_ZN17btHingeConstraint8setLimitEfffff(%class.btHingeConstraint* %103, float 0xBFE921FB60000000, float 0x3FF921FB60000000, float 0x3FECCCCCC0000000, float 0x3FD3333340000000, float 1.000000e+00)
-  %104 = load %class.btHingeConstraint** %hingeC, align 4
+  %104 = load %class.btHingeConstraint*, %class.btHingeConstraint** %hingeC, align 4
   %105 = bitcast %class.btHingeConstraint* %104 to %class.btTypedConstraint*
-  %m_joints = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx261 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints, i32 0, i32 0
+  %m_joints = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx261 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints, i32 0, i32 0
   store %class.btTypedConstraint* %105, %class.btTypedConstraint** %arrayidx261, align 4
-  %m_ownerWorld262 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 1
-  %106 = load %class.btDynamicsWorld** %m_ownerWorld262, align 4
+  %m_ownerWorld262 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 1
+  %106 = load %class.btDynamicsWorld*, %class.btDynamicsWorld** %m_ownerWorld262, align 4
   %107 = bitcast %class.btDynamicsWorld* %106 to void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)***
-  %vtable = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %107
-  %vfn = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable, i64 10
-  %108 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn
-  %m_joints263 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx264 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints263, i32 0, i32 0
-  %109 = load %class.btTypedConstraint** %arrayidx264, align 4
+  %vtable = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)**, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %107
+  %vfn = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable, i64 10
+  %108 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn
+  %m_joints263 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx264 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints263, i32 0, i32 0
+  %109 = load %class.btTypedConstraint*, %class.btTypedConstraint** %arrayidx264, align 4
   call void %108(%class.btDynamicsWorld* %106, %class.btTypedConstraint* %109, i1 zeroext true)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localA)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localB)
@@ -848,33 +848,33 @@ invoke.cont259:                                   ; preds = %for.end
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp273)
   %call279 = call noalias i8* @_Znwm(i32 628)
   %110 = bitcast i8* %call279 to %class.btConeTwistConstraint*
-  %m_bodies280 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx281 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies280, i32 0, i32 1
-  %111 = load %class.btRigidBody** %arrayidx281, align 4
-  %m_bodies282 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx283 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies282, i32 0, i32 2
-  %112 = load %class.btRigidBody** %arrayidx283, align 4
+  %m_bodies280 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx281 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies280, i32 0, i32 1
+  %111 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx281, align 4
+  %m_bodies282 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx283 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies282, i32 0, i32 2
+  %112 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx283, align 4
   %call286 = invoke %class.btConeTwistConstraint* @_ZN21btConeTwistConstraintC1ER11btRigidBodyS1_RK11btTransformS4_(%class.btConeTwistConstraint* %110, %class.btRigidBody* %111, %class.btRigidBody* %112, %class.btTransform* %localA, %class.btTransform* %localB)
           to label %invoke.cont285 unwind label %lpad284
 
 invoke.cont285:                                   ; preds = %invoke.cont259
   store %class.btConeTwistConstraint* %110, %class.btConeTwistConstraint** %coneC, align 4
-  %113 = load %class.btConeTwistConstraint** %coneC, align 4
+  %113 = load %class.btConeTwistConstraint*, %class.btConeTwistConstraint** %coneC, align 4
   call void @_ZN21btConeTwistConstraint8setLimitEffffff(%class.btConeTwistConstraint* %113, float 0x3FE921FB60000000, float 0x3FE921FB60000000, float 0x3FF921FB60000000, float 1.000000e+00, float 0x3FD3333340000000, float 1.000000e+00)
-  %114 = load %class.btConeTwistConstraint** %coneC, align 4
+  %114 = load %class.btConeTwistConstraint*, %class.btConeTwistConstraint** %coneC, align 4
   %115 = bitcast %class.btConeTwistConstraint* %114 to %class.btTypedConstraint*
-  %m_joints287 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx288 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints287, i32 0, i32 1
+  %m_joints287 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx288 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints287, i32 0, i32 1
   store %class.btTypedConstraint* %115, %class.btTypedConstraint** %arrayidx288, align 4
-  %m_ownerWorld289 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 1
-  %116 = load %class.btDynamicsWorld** %m_ownerWorld289, align 4
+  %m_ownerWorld289 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 1
+  %116 = load %class.btDynamicsWorld*, %class.btDynamicsWorld** %m_ownerWorld289, align 4
   %117 = bitcast %class.btDynamicsWorld* %116 to void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)***
-  %vtable290 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %117
-  %vfn291 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable290, i64 10
-  %118 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn291
-  %m_joints292 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx293 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints292, i32 0, i32 1
-  %119 = load %class.btTypedConstraint** %arrayidx293, align 4
+  %vtable290 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)**, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %117
+  %vfn291 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable290, i64 10
+  %118 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn291
+  %m_joints292 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx293 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints292, i32 0, i32 1
+  %119 = load %class.btTypedConstraint*, %class.btTypedConstraint** %arrayidx293, align 4
   call void %118(%class.btDynamicsWorld* %116, %class.btTypedConstraint* %119, i1 zeroext true)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localA)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localB)
@@ -896,33 +896,33 @@ invoke.cont285:                                   ; preds = %invoke.cont259
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp302)
   %call308 = call noalias i8* @_Znwm(i32 628)
   %120 = bitcast i8* %call308 to %class.btConeTwistConstraint*
-  %m_bodies309 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx310 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies309, i32 0, i32 0
-  %121 = load %class.btRigidBody** %arrayidx310, align 4
-  %m_bodies311 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx312 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies311, i32 0, i32 3
-  %122 = load %class.btRigidBody** %arrayidx312, align 4
+  %m_bodies309 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx310 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies309, i32 0, i32 0
+  %121 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx310, align 4
+  %m_bodies311 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx312 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies311, i32 0, i32 3
+  %122 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx312, align 4
   %call315 = invoke %class.btConeTwistConstraint* @_ZN21btConeTwistConstraintC1ER11btRigidBodyS1_RK11btTransformS4_(%class.btConeTwistConstraint* %120, %class.btRigidBody* %121, %class.btRigidBody* %122, %class.btTransform* %localA, %class.btTransform* %localB)
           to label %invoke.cont314 unwind label %lpad313
 
 invoke.cont314:                                   ; preds = %invoke.cont285
   store %class.btConeTwistConstraint* %120, %class.btConeTwistConstraint** %coneC, align 4
-  %123 = load %class.btConeTwistConstraint** %coneC, align 4
+  %123 = load %class.btConeTwistConstraint*, %class.btConeTwistConstraint** %coneC, align 4
   call void @_ZN21btConeTwistConstraint8setLimitEffffff(%class.btConeTwistConstraint* %123, float 0x3FE921FB60000000, float 0x3FE921FB60000000, float 0.000000e+00, float 1.000000e+00, float 0x3FD3333340000000, float 1.000000e+00)
-  %124 = load %class.btConeTwistConstraint** %coneC, align 4
+  %124 = load %class.btConeTwistConstraint*, %class.btConeTwistConstraint** %coneC, align 4
   %125 = bitcast %class.btConeTwistConstraint* %124 to %class.btTypedConstraint*
-  %m_joints316 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx317 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints316, i32 0, i32 2
+  %m_joints316 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx317 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints316, i32 0, i32 2
   store %class.btTypedConstraint* %125, %class.btTypedConstraint** %arrayidx317, align 4
-  %m_ownerWorld318 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 1
-  %126 = load %class.btDynamicsWorld** %m_ownerWorld318, align 4
+  %m_ownerWorld318 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 1
+  %126 = load %class.btDynamicsWorld*, %class.btDynamicsWorld** %m_ownerWorld318, align 4
   %127 = bitcast %class.btDynamicsWorld* %126 to void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)***
-  %vtable319 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %127
-  %vfn320 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable319, i64 10
-  %128 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn320
-  %m_joints321 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx322 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints321, i32 0, i32 2
-  %129 = load %class.btTypedConstraint** %arrayidx322, align 4
+  %vtable319 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)**, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %127
+  %vfn320 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable319, i64 10
+  %128 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn320
+  %m_joints321 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx322 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints321, i32 0, i32 2
+  %129 = load %class.btTypedConstraint*, %class.btTypedConstraint** %arrayidx322, align 4
   call void %128(%class.btDynamicsWorld* %126, %class.btTypedConstraint* %129, i1 zeroext true)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localA)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localB)
@@ -944,33 +944,33 @@ invoke.cont314:                                   ; preds = %invoke.cont285
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp331)
   %call337 = call noalias i8* @_Znwm(i32 780)
   %130 = bitcast i8* %call337 to %class.btHingeConstraint*
-  %m_bodies338 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx339 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies338, i32 0, i32 3
-  %131 = load %class.btRigidBody** %arrayidx339, align 4
-  %m_bodies340 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx341 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies340, i32 0, i32 4
-  %132 = load %class.btRigidBody** %arrayidx341, align 4
+  %m_bodies338 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx339 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies338, i32 0, i32 3
+  %131 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx339, align 4
+  %m_bodies340 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx341 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies340, i32 0, i32 4
+  %132 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx341, align 4
   %call344 = invoke %class.btHingeConstraint* @_ZN17btHingeConstraintC1ER11btRigidBodyS1_RK11btTransformS4_b(%class.btHingeConstraint* %130, %class.btRigidBody* %131, %class.btRigidBody* %132, %class.btTransform* %localA, %class.btTransform* %localB, i1 zeroext false)
           to label %invoke.cont343 unwind label %lpad342
 
 invoke.cont343:                                   ; preds = %invoke.cont314
   store %class.btHingeConstraint* %130, %class.btHingeConstraint** %hingeC, align 4
-  %133 = load %class.btHingeConstraint** %hingeC, align 4
+  %133 = load %class.btHingeConstraint*, %class.btHingeConstraint** %hingeC, align 4
   call void @_ZN17btHingeConstraint8setLimitEfffff(%class.btHingeConstraint* %133, float 0.000000e+00, float 0x3FF921FB60000000, float 0x3FECCCCCC0000000, float 0x3FD3333340000000, float 1.000000e+00)
-  %134 = load %class.btHingeConstraint** %hingeC, align 4
+  %134 = load %class.btHingeConstraint*, %class.btHingeConstraint** %hingeC, align 4
   %135 = bitcast %class.btHingeConstraint* %134 to %class.btTypedConstraint*
-  %m_joints345 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx346 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints345, i32 0, i32 3
+  %m_joints345 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx346 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints345, i32 0, i32 3
   store %class.btTypedConstraint* %135, %class.btTypedConstraint** %arrayidx346, align 4
-  %m_ownerWorld347 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 1
-  %136 = load %class.btDynamicsWorld** %m_ownerWorld347, align 4
+  %m_ownerWorld347 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 1
+  %136 = load %class.btDynamicsWorld*, %class.btDynamicsWorld** %m_ownerWorld347, align 4
   %137 = bitcast %class.btDynamicsWorld* %136 to void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)***
-  %vtable348 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %137
-  %vfn349 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable348, i64 10
-  %138 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn349
-  %m_joints350 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx351 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints350, i32 0, i32 3
-  %139 = load %class.btTypedConstraint** %arrayidx351, align 4
+  %vtable348 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)**, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %137
+  %vfn349 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable348, i64 10
+  %138 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn349
+  %m_joints350 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx351 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints350, i32 0, i32 3
+  %139 = load %class.btTypedConstraint*, %class.btTypedConstraint** %arrayidx351, align 4
   call void %138(%class.btDynamicsWorld* %136, %class.btTypedConstraint* %139, i1 zeroext true)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localA)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localB)
@@ -992,33 +992,33 @@ invoke.cont343:                                   ; preds = %invoke.cont314
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp360)
   %call366 = call noalias i8* @_Znwm(i32 628)
   %140 = bitcast i8* %call366 to %class.btConeTwistConstraint*
-  %m_bodies367 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx368 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies367, i32 0, i32 0
-  %141 = load %class.btRigidBody** %arrayidx368, align 4
-  %m_bodies369 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx370 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies369, i32 0, i32 5
-  %142 = load %class.btRigidBody** %arrayidx370, align 4
+  %m_bodies367 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx368 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies367, i32 0, i32 0
+  %141 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx368, align 4
+  %m_bodies369 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx370 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies369, i32 0, i32 5
+  %142 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx370, align 4
   %call373 = invoke %class.btConeTwistConstraint* @_ZN21btConeTwistConstraintC1ER11btRigidBodyS1_RK11btTransformS4_(%class.btConeTwistConstraint* %140, %class.btRigidBody* %141, %class.btRigidBody* %142, %class.btTransform* %localA, %class.btTransform* %localB)
           to label %invoke.cont372 unwind label %lpad371
 
 invoke.cont372:                                   ; preds = %invoke.cont343
   store %class.btConeTwistConstraint* %140, %class.btConeTwistConstraint** %coneC, align 4
-  %143 = load %class.btConeTwistConstraint** %coneC, align 4
+  %143 = load %class.btConeTwistConstraint*, %class.btConeTwistConstraint** %coneC, align 4
   call void @_ZN21btConeTwistConstraint8setLimitEffffff(%class.btConeTwistConstraint* %143, float 0x3FE921FB60000000, float 0x3FE921FB60000000, float 0.000000e+00, float 1.000000e+00, float 0x3FD3333340000000, float 1.000000e+00)
-  %144 = load %class.btConeTwistConstraint** %coneC, align 4
+  %144 = load %class.btConeTwistConstraint*, %class.btConeTwistConstraint** %coneC, align 4
   %145 = bitcast %class.btConeTwistConstraint* %144 to %class.btTypedConstraint*
-  %m_joints374 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx375 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints374, i32 0, i32 4
+  %m_joints374 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx375 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints374, i32 0, i32 4
   store %class.btTypedConstraint* %145, %class.btTypedConstraint** %arrayidx375, align 4
-  %m_ownerWorld376 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 1
-  %146 = load %class.btDynamicsWorld** %m_ownerWorld376, align 4
+  %m_ownerWorld376 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 1
+  %146 = load %class.btDynamicsWorld*, %class.btDynamicsWorld** %m_ownerWorld376, align 4
   %147 = bitcast %class.btDynamicsWorld* %146 to void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)***
-  %vtable377 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %147
-  %vfn378 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable377, i64 10
-  %148 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn378
-  %m_joints379 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx380 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints379, i32 0, i32 4
-  %149 = load %class.btTypedConstraint** %arrayidx380, align 4
+  %vtable377 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)**, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %147
+  %vfn378 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable377, i64 10
+  %148 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn378
+  %m_joints379 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx380 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints379, i32 0, i32 4
+  %149 = load %class.btTypedConstraint*, %class.btTypedConstraint** %arrayidx380, align 4
   call void %148(%class.btDynamicsWorld* %146, %class.btTypedConstraint* %149, i1 zeroext true)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localA)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localB)
@@ -1040,33 +1040,33 @@ invoke.cont372:                                   ; preds = %invoke.cont343
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp389)
   %call395 = call noalias i8* @_Znwm(i32 780)
   %150 = bitcast i8* %call395 to %class.btHingeConstraint*
-  %m_bodies396 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx397 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies396, i32 0, i32 5
-  %151 = load %class.btRigidBody** %arrayidx397, align 4
-  %m_bodies398 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx399 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies398, i32 0, i32 6
-  %152 = load %class.btRigidBody** %arrayidx399, align 4
+  %m_bodies396 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx397 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies396, i32 0, i32 5
+  %151 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx397, align 4
+  %m_bodies398 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx399 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies398, i32 0, i32 6
+  %152 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx399, align 4
   %call402 = invoke %class.btHingeConstraint* @_ZN17btHingeConstraintC1ER11btRigidBodyS1_RK11btTransformS4_b(%class.btHingeConstraint* %150, %class.btRigidBody* %151, %class.btRigidBody* %152, %class.btTransform* %localA, %class.btTransform* %localB, i1 zeroext false)
           to label %invoke.cont401 unwind label %lpad400
 
 invoke.cont401:                                   ; preds = %invoke.cont372
   store %class.btHingeConstraint* %150, %class.btHingeConstraint** %hingeC, align 4
-  %153 = load %class.btHingeConstraint** %hingeC, align 4
+  %153 = load %class.btHingeConstraint*, %class.btHingeConstraint** %hingeC, align 4
   call void @_ZN17btHingeConstraint8setLimitEfffff(%class.btHingeConstraint* %153, float 0.000000e+00, float 0x3FF921FB60000000, float 0x3FECCCCCC0000000, float 0x3FD3333340000000, float 1.000000e+00)
-  %154 = load %class.btHingeConstraint** %hingeC, align 4
+  %154 = load %class.btHingeConstraint*, %class.btHingeConstraint** %hingeC, align 4
   %155 = bitcast %class.btHingeConstraint* %154 to %class.btTypedConstraint*
-  %m_joints403 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx404 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints403, i32 0, i32 5
+  %m_joints403 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx404 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints403, i32 0, i32 5
   store %class.btTypedConstraint* %155, %class.btTypedConstraint** %arrayidx404, align 4
-  %m_ownerWorld405 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 1
-  %156 = load %class.btDynamicsWorld** %m_ownerWorld405, align 4
+  %m_ownerWorld405 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 1
+  %156 = load %class.btDynamicsWorld*, %class.btDynamicsWorld** %m_ownerWorld405, align 4
   %157 = bitcast %class.btDynamicsWorld* %156 to void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)***
-  %vtable406 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %157
-  %vfn407 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable406, i64 10
-  %158 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn407
-  %m_joints408 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx409 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints408, i32 0, i32 5
-  %159 = load %class.btTypedConstraint** %arrayidx409, align 4
+  %vtable406 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)**, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %157
+  %vfn407 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable406, i64 10
+  %158 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn407
+  %m_joints408 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx409 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints408, i32 0, i32 5
+  %159 = load %class.btTypedConstraint*, %class.btTypedConstraint** %arrayidx409, align 4
   call void %158(%class.btDynamicsWorld* %156, %class.btTypedConstraint* %159, i1 zeroext true)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localA)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localB)
@@ -1088,33 +1088,33 @@ invoke.cont401:                                   ; preds = %invoke.cont372
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp418)
   %call424 = call noalias i8* @_Znwm(i32 628)
   %160 = bitcast i8* %call424 to %class.btConeTwistConstraint*
-  %m_bodies425 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx426 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies425, i32 0, i32 1
-  %161 = load %class.btRigidBody** %arrayidx426, align 4
-  %m_bodies427 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx428 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies427, i32 0, i32 7
-  %162 = load %class.btRigidBody** %arrayidx428, align 4
+  %m_bodies425 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx426 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies425, i32 0, i32 1
+  %161 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx426, align 4
+  %m_bodies427 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx428 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies427, i32 0, i32 7
+  %162 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx428, align 4
   %call431 = invoke %class.btConeTwistConstraint* @_ZN21btConeTwistConstraintC1ER11btRigidBodyS1_RK11btTransformS4_(%class.btConeTwistConstraint* %160, %class.btRigidBody* %161, %class.btRigidBody* %162, %class.btTransform* %localA, %class.btTransform* %localB)
           to label %invoke.cont430 unwind label %lpad429
 
 invoke.cont430:                                   ; preds = %invoke.cont401
   store %class.btConeTwistConstraint* %160, %class.btConeTwistConstraint** %coneC, align 4
-  %163 = load %class.btConeTwistConstraint** %coneC, align 4
+  %163 = load %class.btConeTwistConstraint*, %class.btConeTwistConstraint** %coneC, align 4
   call void @_ZN21btConeTwistConstraint8setLimitEffffff(%class.btConeTwistConstraint* %163, float 0x3FF921FB60000000, float 0x3FF921FB60000000, float 0.000000e+00, float 1.000000e+00, float 0x3FD3333340000000, float 1.000000e+00)
-  %164 = load %class.btConeTwistConstraint** %coneC, align 4
+  %164 = load %class.btConeTwistConstraint*, %class.btConeTwistConstraint** %coneC, align 4
   %165 = bitcast %class.btConeTwistConstraint* %164 to %class.btTypedConstraint*
-  %m_joints432 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx433 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints432, i32 0, i32 6
+  %m_joints432 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx433 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints432, i32 0, i32 6
   store %class.btTypedConstraint* %165, %class.btTypedConstraint** %arrayidx433, align 4
-  %m_ownerWorld434 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 1
-  %166 = load %class.btDynamicsWorld** %m_ownerWorld434, align 4
+  %m_ownerWorld434 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 1
+  %166 = load %class.btDynamicsWorld*, %class.btDynamicsWorld** %m_ownerWorld434, align 4
   %167 = bitcast %class.btDynamicsWorld* %166 to void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)***
-  %vtable435 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %167
-  %vfn436 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable435, i64 10
-  %168 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn436
-  %m_joints437 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx438 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints437, i32 0, i32 6
-  %169 = load %class.btTypedConstraint** %arrayidx438, align 4
+  %vtable435 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)**, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %167
+  %vfn436 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable435, i64 10
+  %168 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn436
+  %m_joints437 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx438 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints437, i32 0, i32 6
+  %169 = load %class.btTypedConstraint*, %class.btTypedConstraint** %arrayidx438, align 4
   call void %168(%class.btDynamicsWorld* %166, %class.btTypedConstraint* %169, i1 zeroext true)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localA)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localB)
@@ -1136,33 +1136,33 @@ invoke.cont430:                                   ; preds = %invoke.cont401
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp447)
   %call453 = call noalias i8* @_Znwm(i32 780)
   %170 = bitcast i8* %call453 to %class.btHingeConstraint*
-  %m_bodies454 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx455 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies454, i32 0, i32 7
-  %171 = load %class.btRigidBody** %arrayidx455, align 4
-  %m_bodies456 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx457 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies456, i32 0, i32 8
-  %172 = load %class.btRigidBody** %arrayidx457, align 4
+  %m_bodies454 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx455 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies454, i32 0, i32 7
+  %171 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx455, align 4
+  %m_bodies456 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx457 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies456, i32 0, i32 8
+  %172 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx457, align 4
   %call460 = invoke %class.btHingeConstraint* @_ZN17btHingeConstraintC1ER11btRigidBodyS1_RK11btTransformS4_b(%class.btHingeConstraint* %170, %class.btRigidBody* %171, %class.btRigidBody* %172, %class.btTransform* %localA, %class.btTransform* %localB, i1 zeroext false)
           to label %invoke.cont459 unwind label %lpad458
 
 invoke.cont459:                                   ; preds = %invoke.cont430
   store %class.btHingeConstraint* %170, %class.btHingeConstraint** %hingeC, align 4
-  %173 = load %class.btHingeConstraint** %hingeC, align 4
+  %173 = load %class.btHingeConstraint*, %class.btHingeConstraint** %hingeC, align 4
   call void @_ZN17btHingeConstraint8setLimitEfffff(%class.btHingeConstraint* %173, float 0xBFF921FB60000000, float 0.000000e+00, float 0x3FECCCCCC0000000, float 0x3FD3333340000000, float 1.000000e+00)
-  %174 = load %class.btHingeConstraint** %hingeC, align 4
+  %174 = load %class.btHingeConstraint*, %class.btHingeConstraint** %hingeC, align 4
   %175 = bitcast %class.btHingeConstraint* %174 to %class.btTypedConstraint*
-  %m_joints461 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx462 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints461, i32 0, i32 7
+  %m_joints461 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx462 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints461, i32 0, i32 7
   store %class.btTypedConstraint* %175, %class.btTypedConstraint** %arrayidx462, align 4
-  %m_ownerWorld463 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 1
-  %176 = load %class.btDynamicsWorld** %m_ownerWorld463, align 4
+  %m_ownerWorld463 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 1
+  %176 = load %class.btDynamicsWorld*, %class.btDynamicsWorld** %m_ownerWorld463, align 4
   %177 = bitcast %class.btDynamicsWorld* %176 to void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)***
-  %vtable464 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %177
-  %vfn465 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable464, i64 10
-  %178 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn465
-  %m_joints466 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx467 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints466, i32 0, i32 7
-  %179 = load %class.btTypedConstraint** %arrayidx467, align 4
+  %vtable464 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)**, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %177
+  %vfn465 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable464, i64 10
+  %178 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn465
+  %m_joints466 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx467 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints466, i32 0, i32 7
+  %179 = load %class.btTypedConstraint*, %class.btTypedConstraint** %arrayidx467, align 4
   call void %178(%class.btDynamicsWorld* %176, %class.btTypedConstraint* %179, i1 zeroext true)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localA)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localB)
@@ -1184,33 +1184,33 @@ invoke.cont459:                                   ; preds = %invoke.cont430
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp476)
   %call482 = call noalias i8* @_Znwm(i32 628)
   %180 = bitcast i8* %call482 to %class.btConeTwistConstraint*
-  %m_bodies483 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx484 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies483, i32 0, i32 1
-  %181 = load %class.btRigidBody** %arrayidx484, align 4
-  %m_bodies485 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx486 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies485, i32 0, i32 9
-  %182 = load %class.btRigidBody** %arrayidx486, align 4
+  %m_bodies483 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx484 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies483, i32 0, i32 1
+  %181 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx484, align 4
+  %m_bodies485 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx486 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies485, i32 0, i32 9
+  %182 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx486, align 4
   %call489 = invoke %class.btConeTwistConstraint* @_ZN21btConeTwistConstraintC1ER11btRigidBodyS1_RK11btTransformS4_(%class.btConeTwistConstraint* %180, %class.btRigidBody* %181, %class.btRigidBody* %182, %class.btTransform* %localA, %class.btTransform* %localB)
           to label %invoke.cont488 unwind label %lpad487
 
 invoke.cont488:                                   ; preds = %invoke.cont459
   store %class.btConeTwistConstraint* %180, %class.btConeTwistConstraint** %coneC, align 4
-  %183 = load %class.btConeTwistConstraint** %coneC, align 4
+  %183 = load %class.btConeTwistConstraint*, %class.btConeTwistConstraint** %coneC, align 4
   call void @_ZN21btConeTwistConstraint8setLimitEffffff(%class.btConeTwistConstraint* %183, float 0x3FF921FB60000000, float 0x3FF921FB60000000, float 0.000000e+00, float 1.000000e+00, float 0x3FD3333340000000, float 1.000000e+00)
-  %184 = load %class.btConeTwistConstraint** %coneC, align 4
+  %184 = load %class.btConeTwistConstraint*, %class.btConeTwistConstraint** %coneC, align 4
   %185 = bitcast %class.btConeTwistConstraint* %184 to %class.btTypedConstraint*
-  %m_joints490 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx491 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints490, i32 0, i32 8
+  %m_joints490 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx491 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints490, i32 0, i32 8
   store %class.btTypedConstraint* %185, %class.btTypedConstraint** %arrayidx491, align 4
-  %m_ownerWorld492 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 1
-  %186 = load %class.btDynamicsWorld** %m_ownerWorld492, align 4
+  %m_ownerWorld492 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 1
+  %186 = load %class.btDynamicsWorld*, %class.btDynamicsWorld** %m_ownerWorld492, align 4
   %187 = bitcast %class.btDynamicsWorld* %186 to void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)***
-  %vtable493 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %187
-  %vfn494 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable493, i64 10
-  %188 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn494
-  %m_joints495 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx496 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints495, i32 0, i32 8
-  %189 = load %class.btTypedConstraint** %arrayidx496, align 4
+  %vtable493 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)**, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %187
+  %vfn494 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable493, i64 10
+  %188 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn494
+  %m_joints495 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx496 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints495, i32 0, i32 8
+  %189 = load %class.btTypedConstraint*, %class.btTypedConstraint** %arrayidx496, align 4
   call void %188(%class.btDynamicsWorld* %186, %class.btTypedConstraint* %189, i1 zeroext true)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localA)
   call void @_ZN11btTransform11setIdentityEv(%class.btTransform* %localB)
@@ -1232,35 +1232,35 @@ invoke.cont488:                                   ; preds = %invoke.cont459
   call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp505)
   %call511 = call noalias i8* @_Znwm(i32 780)
   %190 = bitcast i8* %call511 to %class.btHingeConstraint*
-  %m_bodies512 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx513 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies512, i32 0, i32 9
-  %191 = load %class.btRigidBody** %arrayidx513, align 4
-  %m_bodies514 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 3
-  %arrayidx515 = getelementptr inbounds [11 x %class.btRigidBody*]* %m_bodies514, i32 0, i32 10
-  %192 = load %class.btRigidBody** %arrayidx515, align 4
+  %m_bodies512 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx513 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies512, i32 0, i32 9
+  %191 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx513, align 4
+  %m_bodies514 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 3
+  %arrayidx515 = getelementptr inbounds [11 x %class.btRigidBody*], [11 x %class.btRigidBody*]* %m_bodies514, i32 0, i32 10
+  %192 = load %class.btRigidBody*, %class.btRigidBody** %arrayidx515, align 4
   %call518 = invoke %class.btHingeConstraint* @_ZN17btHingeConstraintC1ER11btRigidBodyS1_RK11btTransformS4_b(%class.btHingeConstraint* %190, %class.btRigidBody* %191, %class.btRigidBody* %192, %class.btTransform* %localA, %class.btTransform* %localB, i1 zeroext false)
           to label %invoke.cont517 unwind label %lpad516
 
 invoke.cont517:                                   ; preds = %invoke.cont488
   store %class.btHingeConstraint* %190, %class.btHingeConstraint** %hingeC, align 4
-  %193 = load %class.btHingeConstraint** %hingeC, align 4
+  %193 = load %class.btHingeConstraint*, %class.btHingeConstraint** %hingeC, align 4
   call void @_ZN17btHingeConstraint8setLimitEfffff(%class.btHingeConstraint* %193, float 0xBFF921FB60000000, float 0.000000e+00, float 0x3FECCCCCC0000000, float 0x3FD3333340000000, float 1.000000e+00)
-  %194 = load %class.btHingeConstraint** %hingeC, align 4
+  %194 = load %class.btHingeConstraint*, %class.btHingeConstraint** %hingeC, align 4
   %195 = bitcast %class.btHingeConstraint* %194 to %class.btTypedConstraint*
-  %m_joints519 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx520 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints519, i32 0, i32 9
+  %m_joints519 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx520 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints519, i32 0, i32 9
   store %class.btTypedConstraint* %195, %class.btTypedConstraint** %arrayidx520, align 4
-  %m_ownerWorld521 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 1
-  %196 = load %class.btDynamicsWorld** %m_ownerWorld521, align 4
+  %m_ownerWorld521 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 1
+  %196 = load %class.btDynamicsWorld*, %class.btDynamicsWorld** %m_ownerWorld521, align 4
   %197 = bitcast %class.btDynamicsWorld* %196 to void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)***
-  %vtable522 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %197
-  %vfn523 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable522, i64 10
-  %198 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn523
-  %m_joints524 = getelementptr inbounds %class.RagDoll* %this1, i32 0, i32 4
-  %arrayidx525 = getelementptr inbounds [10 x %class.btTypedConstraint*]* %m_joints524, i32 0, i32 9
-  %199 = load %class.btTypedConstraint** %arrayidx525, align 4
+  %vtable522 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)**, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*** %197
+  %vfn523 = getelementptr inbounds void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vtable522, i64 10
+  %198 = load void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)*, void (%class.btDynamicsWorld*, %class.btTypedConstraint*, i1)** %vfn523
+  %m_joints524 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 4
+  %arrayidx525 = getelementptr inbounds [10 x %class.btTypedConstraint*], [10 x %class.btTypedConstraint*]* %m_joints524, i32 0, i32 9
+  %199 = load %class.btTypedConstraint*, %class.btTypedConstraint** %arrayidx525, align 4
   call void %198(%class.btDynamicsWorld* %196, %class.btTypedConstraint* %199, i1 zeroext true)
-  %200 = load %class.RagDoll** %retval
+  %200 = load %class.RagDoll*, %class.RagDoll** %retval
   ret %class.RagDoll* %200
 
 lpad258:                                          ; preds = %for.end
@@ -1364,8 +1364,8 @@ lpad516:                                          ; preds = %invoke.cont488
   br label %eh.resume
 
 eh.resume:                                        ; preds = %lpad516, %lpad487, %lpad458, %lpad429, %lpad400, %lpad371, %lpad342, %lpad313, %lpad284, %lpad258, %invoke.cont92, %invoke.cont83, %invoke.cont74, %invoke.cont65, %invoke.cont56, %invoke.cont47, %invoke.cont38, %invoke.cont29, %invoke.cont20, %invoke.cont11, %invoke.cont4
-  %exn = load i8** %exn.slot
-  %sel = load i32* %ehselector.slot
+  %exn = load i8*, i8** %exn.slot
+  %sel = load i32, i32* %ehselector.slot
   %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn, 0
   %lpad.val526 = insertvalue { i8*, i32 } %lpad.val, i32 %sel, 1
   resume { i8*, i32 } %lpad.val526
diff --git a/test/CodeGen/Thumb2/crash.ll b/test/CodeGen/Thumb2/crash.ll
index 6ce0b82b94d7..893a45d8f722 100644
--- a/test/CodeGen/Thumb2/crash.ll
+++ b/test/CodeGen/Thumb2/crash.ll
@@ -7,13 +7,13 @@ target triple = "thumbv7-apple-darwin10"
 define arm_apcscc void @NEON_vst4q_u32(i32* nocapture %sp0, i32* nocapture %sp1, i32* nocapture %sp2, i32* nocapture %sp3, i32* %dp) nounwind {
 entry:
   %0 = bitcast i32* %sp0 to <4 x i32>*            ; <<4 x i32>*> [#uses=1]
-  %1 = load <4 x i32>* %0, align 16               ; <<4 x i32>> [#uses=1]
+  %1 = load <4 x i32>, <4 x i32>* %0, align 16               ; <<4 x i32>> [#uses=1]
   %2 = bitcast i32* %sp1 to <4 x i32>*            ; <<4 x i32>*> [#uses=1]
-  %3 = load <4 x i32>* %2, align 16               ; <<4 x i32>> [#uses=1]
+  %3 = load <4 x i32>, <4 x i32>* %2, align 16               ; <<4 x i32>> [#uses=1]
   %4 = bitcast i32* %sp2 to <4 x i32>*            ; <<4 x i32>*> [#uses=1]
-  %5 = load <4 x i32>* %4, align 16               ; <<4 x i32>> [#uses=1]
+  %5 = load <4 x i32>, <4 x i32>* %4, align 16               ; <<4 x i32>> [#uses=1]
   %6 = bitcast i32* %sp3 to <4 x i32>*            ; <<4 x i32>*> [#uses=1]
-  %7 = load <4 x i32>* %6, align 16               ; <<4 x i32>> [#uses=1]
+  %7 = load <4 x i32>, <4 x i32>* %6, align 16               ; <<4 x i32>> [#uses=1]
   %8 = bitcast i32* %dp to i8*                    ; <i8*> [#uses=1]
   tail call void @llvm.arm.neon.vst4.v4i32(i8* %8, <4 x i32> %1, <4 x i32> %3, <4 x i32> %5, <4 x i32> %7, i32 1)
   ret void
@@ -32,8 +32,8 @@ bb.nph:
 
 bb:                                               ; preds = %bb, %bb.nph
   %0 = phi i32 [ 0, %bb.nph ], [ %1, %bb ]        ; <i32> [#uses=4]
-  %scevgep = getelementptr [16 x i32]* @sbuf, i32 0, i32 %0 ; <i32*> [#uses=1]
-  %scevgep5 = getelementptr [16 x i32]* @dbuf, i32 0, i32 %0 ; <i32*> [#uses=1]
+  %scevgep = getelementptr [16 x i32], [16 x i32]* @sbuf, i32 0, i32 %0 ; <i32*> [#uses=1]
+  %scevgep5 = getelementptr [16 x i32], [16 x i32]* @dbuf, i32 0, i32 %0 ; <i32*> [#uses=1]
   store i32 %0, i32* %scevgep, align 4
   store i32 -1, i32* %scevgep5, align 4
   %1 = add nsw i32 %0, 1                          ; <i32> [#uses=2]
@@ -41,10 +41,10 @@ bb:                                               ; preds = %bb, %bb.nph
   br i1 %exitcond, label %bb2, label %bb
 
 bb2:                                              ; preds = %bb
-  %2 = load <4 x i32>* bitcast ([16 x i32]* @sbuf to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
-  %3 = load <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 4) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
-  %4 = load <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 8) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
-  %5 = load <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 12) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
+  %2 = load <4 x i32>, <4 x i32>* bitcast ([16 x i32]* @sbuf to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
+  %3 = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @sbuf, i32 0, i32 4) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
+  %4 = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @sbuf, i32 0, i32 8) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
+  %5 = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @sbuf, i32 0, i32 12) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
   tail call void @llvm.arm.neon.vst4.v4i32(i8* bitcast ([16 x i32]* @dbuf to i8*), <4 x i32> %2, <4 x i32> %3, <4 x i32> %4, <4 x i32> %5, i32 1) nounwind
   ret i32 0
 }
@@ -70,8 +70,8 @@ declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
 %class = type { i8*, %class*, i32 }
 define void @f11101911(%class* %this, i32 %num) ssp align 2 {
 entry:
-  %p1 = getelementptr inbounds %class* %this, i32 0, i32 1
-  %p2 = getelementptr inbounds %class* %this, i32 0, i32 2
+  %p1 = getelementptr inbounds %class, %class* %this, i32 0, i32 1
+  %p2 = getelementptr inbounds %class, %class* %this, i32 0, i32 2
   tail call void asm sideeffect "", "~{r1},~{r3},~{r5},~{r11},~{r13}"() nounwind
   store %class* %this, %class** %p1, align 4
   store i32 %num, i32* %p2, align 4
diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
index 88c7f0f17ab9..ecb63b18b622 100644
--- a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
+++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
@@ -26,27 +26,27 @@ bb8:                                              ; preds = %bb8, %bb7
 ; CHECK-NOT: vmov.f32
 ; CHECK: blt
   %tmp54 = add i32 0, %tmp53                      ; <i32> [#uses=0]
-  %fi.1 = getelementptr float* %fz, i32 undef     ; <float*> [#uses=2]
+  %fi.1 = getelementptr float, float* %fz, i32 undef     ; <float*> [#uses=2]
   %tmp80 = add i32 0, %tmp79                      ; <i32> [#uses=1]
-  %scevgep81 = getelementptr float* %fz, i32 %tmp80 ; <float*> [#uses=1]
-  %2 = load float* undef, align 4                 ; <float> [#uses=1]
+  %scevgep81 = getelementptr float, float* %fz, i32 %tmp80 ; <float*> [#uses=1]
+  %2 = load float, float* undef, align 4                 ; <float> [#uses=1]
   %3 = fmul float %2, %1                          ; <float> [#uses=1]
-  %4 = load float* null, align 4                  ; <float> [#uses=2]
+  %4 = load float, float* null, align 4                  ; <float> [#uses=2]
   %5 = fmul float %4, %0                          ; <float> [#uses=1]
   %6 = fsub float %3, %5                          ; <float> [#uses=1]
   %7 = fmul float %4, %1                          ; <float> [#uses=1]
   %8 = fadd float undef, %7                       ; <float> [#uses=2]
-  %9 = load float* %fi.1, align 4                 ; <float> [#uses=2]
+  %9 = load float, float* %fi.1, align 4                 ; <float> [#uses=2]
   %10 = fsub float %9, %8                         ; <float> [#uses=1]
   %11 = fadd float %9, %8                         ; <float> [#uses=1]
   %12 = fsub float 0.000000e+00, %6               ; <float> [#uses=1]
   %13 = fsub float 0.000000e+00, undef            ; <float> [#uses=2]
   %14 = fmul float undef, %0                      ; <float> [#uses=1]
   %15 = fadd float %14, undef                     ; <float> [#uses=2]
-  %16 = load float* %scevgep81, align 4           ; <float> [#uses=2]
+  %16 = load float, float* %scevgep81, align 4           ; <float> [#uses=2]
   %17 = fsub float %16, %15                       ; <float> [#uses=1]
   %18 = fadd float %16, %15                       ; <float> [#uses=2]
-  %19 = load float* undef, align 4                ; <float> [#uses=2]
+  %19 = load float, float* undef, align 4                ; <float> [#uses=2]
   %20 = fsub float %19, %13                       ; <float> [#uses=2]
   %21 = fadd float %19, %13                       ; <float> [#uses=1]
   %22 = fmul float %s1.02, %18                    ; <float> [#uses=1]
diff --git a/test/CodeGen/Thumb2/div.ll b/test/CodeGen/Thumb2/div.ll
index b273a8903265..80a842dc07fd 100644
--- a/test/CodeGen/Thumb2/div.ll
+++ b/test/CodeGen/Thumb2/div.ll
@@ -4,6 +4,10 @@
 ; RUN:    | FileCheck %s -check-prefix=CHECK-THUMBV7M
 ; RUN: llc -mtriple=thumb-apple-darwin -mcpu=swift %s -o - \
 ; RUN:    | FileCheck %s -check-prefix=CHECK-HWDIV
+; RUN: llc -mtriple=thumb-apple-darwin -mcpu=cortex-r4 %s -o - \
+; RUN:    | FileCheck %s -check-prefix=CHECK-HWDIV
+; RUN: llc -mtriple=thumb-apple-darwin -mcpu=cortex-r4f %s -o - \
+; RUN:    | FileCheck %s -check-prefix=CHECK-HWDIV
 ; RUN: llc -mtriple=thumb-apple-darwin -mcpu=cortex-r5 %s -o - \
 ; RUN:    | FileCheck %s -check-prefix=CHECK-HWDIV
 
diff --git a/test/CodeGen/Thumb2/float-ops.ll b/test/CodeGen/Thumb2/float-ops.ll
index d383065cd53e..7ec08f866655 100644
--- a/test/CodeGen/Thumb2/float-ops.ll
+++ b/test/CodeGen/Thumb2/float-ops.ll
@@ -102,16 +102,16 @@ entry:
 ; CHECK-LABEL: load_f:
 ; NONE: ldr r0, [r0]
 ; HARD: vldr s0, [r0]
-  %0 = load float* %a, align 4
+  %0 = load float, float* %a, align 4
   ret float %0
 }
 
 define double @load_d(double* %a) {
 entry:
 ; CHECK-LABEL: load_d:
-; NONE: ldm.w r0, {r0, r1}
+; NONE: ldm r0, {r0, r1}
 ; HARD: vldr d0, [r0]
-  %0 = load double* %a, align 8
+  %0 = load double, double* %a, align 8
   ret double %0
 }
 
diff --git a/test/CodeGen/Thumb2/frameless2.ll b/test/CodeGen/Thumb2/frameless2.ll
index c5d32390266b..374335421a54 100644
--- a/test/CodeGen/Thumb2/frameless2.ll
+++ b/test/CodeGen/Thumb2/frameless2.ll
@@ -5,8 +5,8 @@
 
 define void @vorbis_encode_noisebias_setup(i8* nocapture %vi.0.7.val, double %s, i32 %block, i32* nocapture %suppress, %struct.noise3* nocapture %in, %struct.noiseguard* nocapture %guard, double %userbias) nounwind {
 entry:
-  %0 = getelementptr %struct.noiseguard* %guard, i32 %block, i32 2; <i32*> [#uses=1]
-  %1 = load i32* %0, align 4                      ; <i32> [#uses=1]
+  %0 = getelementptr %struct.noiseguard, %struct.noiseguard* %guard, i32 %block, i32 2; <i32*> [#uses=1]
+  %1 = load i32, i32* %0, align 4                      ; <i32> [#uses=1]
   store i32 %1, i32* undef, align 4
   unreachable
 }
diff --git a/test/CodeGen/Thumb2/ifcvt-compare.ll b/test/CodeGen/Thumb2/ifcvt-compare.ll
new file mode 100644
index 000000000000..8af139a5ef6e
--- /dev/null
+++ b/test/CodeGen/Thumb2/ifcvt-compare.ll
@@ -0,0 +1,47 @@
+; RUN: llc -mtriple=thumbv7-unknown-linux %s -o - | FileCheck %s
+
+declare void @x()
+
+define void @f0(i32 %x) optsize {
+  ; CHECK-LABEL: f0:
+  ; CHECK: cbnz
+  %p = icmp eq i32 %x, 0
+  br i1 %p, label %t, label %f
+
+t:
+  call void @x()
+  br label %f
+
+f:
+  ret void
+}
+
+define void @f1(i32 %x) optsize {
+  ; CHECK-LABEL: f1:
+  ; CHECK: cmp r0, #1
+  ; CHECK: it eq
+  %p = icmp eq i32 %x, 1
+  br i1 %p, label %t, label %f
+
+t:
+  call void @x()
+  br label %f
+
+f:
+  ret void
+}
+
+define void @f2(i32 %x) {
+  ; CHECK-LABEL: f2:
+  ; CHECK: cmp r0, #0
+  ; CHECK: it eq
+  %p = icmp eq i32 %x, 0
+  br i1 %p, label %t, label %f
+
+t:
+  call void @x()
+  br label %f
+
+f:
+  ret void
+}
diff --git a/test/CodeGen/Thumb2/ifcvt-neon.ll b/test/CodeGen/Thumb2/ifcvt-neon.ll
index 501b0b6a007c..83c0b601aba9 100644
--- a/test/CodeGen/Thumb2/ifcvt-neon.ll
+++ b/test/CodeGen/Thumb2/ifcvt-neon.ll
@@ -7,14 +7,14 @@
 define float @t(i32 %c) nounwind {
 entry:
   %0 = icmp sgt i32 %c, 1                         ; <i1> [#uses=1]
-  %1 = load float* @a, align 4                    ; <float> [#uses=2]
-  %2 = load float* @b, align 4                    ; <float> [#uses=2]
+  %1 = load float, float* @a, align 4                    ; <float> [#uses=2]
+  %2 = load float, float* @b, align 4                    ; <float> [#uses=2]
   br i1 %0, label %bb, label %bb1
 
 bb:                                               ; preds = %entry
-; CHECK:      ite lt
-; CHECK:      vsublt.f32
-; CHECK-NEXT: vaddge.f32
+; CHECK:      vsub.f32
+; CHECK-NEXT: vadd.f32
+; CHECK:      it gt
   %3 = fadd float %1, %2                          ; <float> [#uses=1]
   br label %bb2
 
diff --git a/test/CodeGen/Thumb2/inflate-regs.ll b/test/CodeGen/Thumb2/inflate-regs.ll
index d8a558c97e27..4814db281bfe 100644
--- a/test/CodeGen/Thumb2/inflate-regs.ll
+++ b/test/CodeGen/Thumb2/inflate-regs.ll
@@ -14,7 +14,7 @@ target triple = "thumbv7-apple-ios"
 ; CHECK: vstr s
 define void @local_split(float* nocapture %p) nounwind ssp {
 entry:
-  %x = load float* %p, align 4
+  %x = load float, float* %p, align 4
   %a = fadd float %x, 1.0
   tail call void asm sideeffect "", "~{d0},~{d1},~{d2},~{d3},~{d4},~{d5},~{d6},~{d7},~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15}"() nounwind
   store float %a, float* %p, align 4
@@ -33,7 +33,7 @@ entry:
 ; CHECK: vstr s
 define void @global_split(float* nocapture %p1, float* nocapture %p2) nounwind ssp {
 entry:
-  %0 = load float* %p1, align 4
+  %0 = load float, float* %p1, align 4
   %add = fadd float %0, 1.000000e+00
   tail call void asm sideeffect "", "~{d0},~{d1},~{d2},~{d3},~{d4},~{d5},~{d6},~{d7},~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15}"() nounwind
   %cmp = fcmp ogt float %add, 0.000000e+00
diff --git a/test/CodeGen/Thumb2/large-call.ll b/test/CodeGen/Thumb2/large-call.ll
index 1b4d4625dd05..f6a5a60ba3c2 100644
--- a/test/CodeGen/Thumb2/large-call.ll
+++ b/test/CodeGen/Thumb2/large-call.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mcpu=cortex-a8 | FileCheck %s
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mcpu=cortex-a8 | FileCheck %s
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
 target triple = "thumbv7-apple-ios0.0.0"
 
@@ -21,8 +21,8 @@ define i32 @main() ssp {
 entry:
   %d = alloca double, align 8
   store double 1.000000e+00, double* %d, align 8
-  %0 = load double* %d, align 8
-  call void (i8*, i8*, i8*, ...)* @variadic(i8* null, i8* null, i8* null, i32 1, double 1.234800e+03, double 2.363450e+03, double %0, i32 1, double 1.234560e+03, double 2.345670e+03, double 4.6334563e+03, double 2.423440e+03, double 4.234330e+03, double 2.965430e+03, i32 1, double 4.669300e+03, double 2.927500e+03, double 4.663100e+03, double 2.921000e+03, double 4.663100e+03, double 2.345100e+03, i32 1, double 3.663100e+03, double 2.905100e+03, double 4.669300e+03, double 2.898600e+03, double 4.676900e+03, double 2.898600e+03, i32 1, double 4.684600e+03, double 2.898600e+03, double 1.234800e+03, double 2.905100e+03, double 1.234800e+03, double 2.345100e+03, i32 1, double 7.719700e+03, double 2.920500e+03, double 4.713500e+03, double 2.927000e+03, double 4.705800e+03, double 2.927000e+03, i32 1, double 8.698200e+03, double 2.927000e+03, double 4.692000e+03, double 2.920500e+03, double 4.692000e+03, double 2.912500e+03, i32 1, double 4.692000e+03, double 2.945600e+03, double 4.698200e+03, double 2.898100e+03, double 4.705800e+03, double 2.898100e+03, i32 1, double 4.713500e+03, double 2.898100e+03, double 4.719700e+03, double 2.945600e+03, double 4.719700e+03, double 2.912500e+03, i32 1, double 4.749200e+03, double 2.920100e+03, double 4.743000e+03, double 2.926600e+03, double 4.735300e+03, double 2.926600e+03, i32 1, double 4.727700e+03, double 2.926600e+03, double 4.721500e+03, double 2.920100e+03, double 4.721500e+03, double 2.912100e+03, i32 1, double 4.721500e+03, double 2.945100e+03, double 4.727700e+03, double 2.897700e+03, double 4.735300e+03, double 2.897700e+03, i32 1, double 4.743000e+03, double 2.897700e+03, double 4.749200e+03, double 2.945100e+03, double 4.749200e+03, double 2.912100e+03, i32 1, double 4.778200e+03, double 2.920100e+03, double 4.772000e+03, double 2.926600e+03, double 4.764300e+03, double 2.926600e+03, i32 1, double 4.756700e+03, double 2.926600e+03, double 4.750500e+03, double 2.920100e+03, double 4.750500e+03, double 2.912100e+03, i32 1, double 4.750500e+03, double 2.945100e+03, double 4.756700e+03, double 2.897700e+03, double 4.764300e+03, double 2.897700e+03, i32 1, double 4.772000e+03, double 2.897700e+03, double 4.778200e+03, double 2.945100e+03, double 4.778200e+03, double 2.912100e+03, i32 1, double 4.801900e+03, double 2.942100e+03, double 4.795700e+03, double 2.948500e+03, double 4.788100e+03, double 2.948500e+03, i32 1, double 4.780500e+03, double 2.948500e+03, double 4.774300e+03, double 2.942100e+03, double 4.774300e+03, double 2.934100e+03, i32 1, double 4.774300e+03, double 2.926100e+03, double 4.780500e+03, double 2.919600e+03, double 4.788100e+03, double 2.919600e+03, i32 1, double 4.795700e+03, double 2.919600e+03, double 4.801900e+03, double 2.926100e+03, double 4.801900e+03, double 2.934100e+03, i32 1, double 4.801500e+03, double 2.972500e+03, double 4.795300e+03, double 2.978900e+03, double 4.787700e+03, double 2.978900e+03, i32 1, double 4.780000e+03, double 2.978900e+03, double 4.773800e+03, double 2.972500e+03, double 4.773800e+03, double 2.964500e+03, i32 1, double 4.773800e+03, double 2.956500e+03, double 4.780000e+03, double 2.950000e+03, double 4.787700e+03, double 2.950000e+03, i32 1, double 4.795300e+03, double 2.950000e+03, double 4.801500e+03, double 2.956500e+03, double 4.801500e+03, double 2.964500e+03, i32 1, double 4.802400e+03, double 3.010200e+03, double 4.796200e+03, double 3.016600e+03, double 4.788500e+03, double 3.016600e+03, i32 1, double 4.780900e+03, double 3.016600e+03, double 4.774700e+03, double 3.010200e+03, double 4.774700e+03, double 3.002200e+03, i32 1, double 4.774700e+03, double 2.994200e+03, double 4.780900e+03, double 2.987700e+03, double 4.788500e+03, double 2.987700e+03, i32 1, double 4.796200e+03, double 2.987700e+03, double 4.802400e+03, double 2.994200e+03, double 4.802400e+03, double 3.002200e+03, i32 1, double 4.802400e+03, double 3.039400e+03, double 4.796200e+03, double 3.455800e+03, double 4.788500e+03, double 3.455800e+03, i32 1, double 4.780900e+03, double 3.455800e+03, double 4.774700e+03, double 3.039400e+03, double 4.774700e+03, double 3.031400e+03, i32 1, double 4.774700e+03, double 3.023400e+03, double 4.780900e+03, double 3.016900e+03, double 4.788500e+03, double 3.016900e+03, i32 1, double 4.796200e+03, double 3.016900e+03, double 4.802400e+03, double 3.023400e+03, double 4.802400e+03, double 3.031400e+03, i32 1, double 4.778600e+03, double 3.063100e+03, double 4.772400e+03, double 3.069600e+03, double 4.764700e+03, double 3.069600e+03, i32 1, double 4.757100e+03, double 3.069600e+03, double 4.750900e+03, double 3.063100e+03, double 4.750900e+03, double 3.055100e+03, i32 1, double 4.750900e+03, double 3.457100e+03, double 4.757100e+03, double 3.450700e+03, double 4.764700e+03, double 3.450700e+03, i32 1, double 4.772400e+03, double 3.450700e+03, double 4.778600e+03, double 3.457100e+03, double 4.778600e+03, double 3.055100e+03, i32 1, double 4.748600e+03, double 3.063600e+03, double 4.742400e+03, double 3.070000e+03, double 4.734700e+03, double 3.070000e+03, i32 1, double 4.727100e+03, double 3.070000e+03, double 4.720900e+03, double 3.063600e+03, double 4.720900e+03, double 3.055600e+03, i32 1, double 4.720900e+03, double 3.457600e+03, double 4.727100e+03, double 3.451100e+03, double 4.734700e+03, double 3.451100e+03, i32 1, double 4.742400e+03, double 3.451100e+03, double 4.748600e+03, double 3.457600e+03, double 4.748600e+03, double 3.055600e+03, i32 1, double 4.719500e+03, double 3.063600e+03, double 4.713300e+03, double 3.070000e+03, double 4.705700e+03, double 3.070000e+03, i32 1, double 4.698000e+03, double 3.070000e+03, double 4.691900e+03, double 3.063600e+03, double 4.691900e+03, double 3.055600e+03, i32 1, double 4.691900e+03, double 3.457600e+03, double 4.698000e+03, double 3.451100e+03, double 4.705700e+03, double 3.451100e+03, i32 1, double 4.713300e+03, double 3.451100e+03, double 4.719500e+03, double 3.457600e+03, double 4.719500e+03, double 3.055600e+03, i32 1, double 4.691300e+03, double 3.064000e+03, double 4.685100e+03, double 3.070500e+03, double 4.677500e+03, double 3.070500e+03, i32 1, double 4.669900e+03, double 3.070500e+03, double 4.663700e+03, double 3.064000e+03, double 4.663700e+03, double 3.056000e+03, i32 1, double 4.663700e+03, double 3.458000e+03, double 4.669900e+03, double 3.451600e+03, double 4.677500e+03, double 3.451600e+03, i32 1, double 4.685100e+03, double 3.451600e+03, double 4.691300e+03, double 3.458000e+03, double 4.691300e+03, double 3.056000e+03, i32 1, double 4.668500e+03, double 3.453000e+03, double 4.662300e+03, double 3.459400e+03, double 4.654700e+03, double 3.459400e+03, i32 1, double 4.647000e+03, double 3.459400e+03, double 4.640900e+03, double 3.453000e+03, double 4.640900e+03, double 3.035000e+03, i32 1, double 4.640900e+03, double 3.027000e+03, double 4.647000e+03, double 3.020500e+03, double 4.654700e+03, double 3.020500e+03, i32 1, double 4.662300e+03, double 3.020500e+03, double 4.668500e+03, double 3.027000e+03, double 4.668500e+03, double 3.035000e+03, i32 1, double 4.668500e+03, double 3.014300e+03, double 4.662300e+03, double 3.020800e+03, double 4.654700e+03, double 3.020800e+03, i32 1, double 4.647000e+03, double 3.020800e+03, double 4.640900e+03, double 3.014300e+03, double 4.640900e+03, double 3.006400e+03, i32 1, double 4.640900e+03, double 2.998400e+03, double 4.647000e+03, double 2.991900e+03, double 4.654700e+03, double 2.991900e+03, i32 1, double 4.662300e+03, double 2.991900e+03, double 4.668500e+03, double 2.998400e+03, double 4.668500e+03, double 3.006400e+03, i32 1, double 4.668100e+03, double 2.941100e+03, double 4.661900e+03, double 2.947600e+03, double 4.654200e+03, double 2.947600e+03, i32 1, double 4.646600e+03, double 2.947600e+03, double 4.640400e+03, double 2.941100e+03, double 4.640400e+03, double 2.933100e+03, i32 1, double 4.640400e+03, double 2.925200e+03, double 4.646600e+03, double 2.918700e+03, double 4.654200e+03, double 2.918700e+03, i32 1, double 4.661900e+03, double 2.918700e+03, double 4.668100e+03, double 2.925200e+03, double 4.668100e+03, double 2.933100e+03, i32 1, double 4.668500e+03, double 2.971600e+03, double 4.662300e+03, double 2.978100e+03, double 4.654700e+03, double 2.978100e+03, i32 1, double 4.647000e+03, double 2.978100e+03, double 4.640900e+03, double 2.971600e+03, double 4.640900e+03, double 2.963600e+03, i32 1, double 4.640900e+03, double 2.955700e+03, double 4.647000e+03, double 2.949200e+03, double 4.654700e+03, double 2.949200e+03, i32 1, double 4.662300e+03, double 2.949200e+03, double 4.668500e+03, double 2.955700e+03, double 4.668500e+03, double 2.963600e+03, i32 2, i32 1, double 4.691300e+03, double 3.056000e+03, i32 2, i32 1, double 4.748600e+03, double 3.055600e+03, i32 2, i32 1, double 4.778200e+03, double 2.912100e+03, i32 2, i32 1, double 4.749200e+03, double 2.912100e+03, i32 2, i32 1, double 4.802400e+03, double 3.031400e+03, i32 2, i32 1, double 4.778600e+03, double 3.055100e+03, i32 2, i32 1, double 4.801500e+03, double 2.964500e+03, i32 2, i32 1, double 4.802400e+03, double 3.002200e+03, i32 2, i32 1, double 4.719700e+03, double 2.912500e+03, i32 2, i32 1, double 4.801900e+03, double 2.934100e+03, i32 2, i32 1, double 4.719500e+03, double 3.055600e+03, i32 2, i32 1, double 4.668500e+03, double 3.006400e+03, i32 2, i32 1, double 4.668500e+03, double 3.035000e+03, i32 2, i32 1, double 4.668100e+03, double 2.933100e+03, i32 2, i32 1, double 4.668500e+03, double 2.963600e+03, i32 2, i32 48)
+  %0 = load double, double* %d, align 8
+  call void (i8*, i8*, i8*, ...) @variadic(i8* null, i8* null, i8* null, i32 1, double 1.234800e+03, double 2.363450e+03, double %0, i32 1, double 1.234560e+03, double 2.345670e+03, double 4.6334563e+03, double 2.423440e+03, double 4.234330e+03, double 2.965430e+03, i32 1, double 4.669300e+03, double 2.927500e+03, double 4.663100e+03, double 2.921000e+03, double 4.663100e+03, double 2.345100e+03, i32 1, double 3.663100e+03, double 2.905100e+03, double 4.669300e+03, double 2.898600e+03, double 4.676900e+03, double 2.898600e+03, i32 1, double 4.684600e+03, double 2.898600e+03, double 1.234800e+03, double 2.905100e+03, double 1.234800e+03, double 2.345100e+03, i32 1, double 7.719700e+03, double 2.920500e+03, double 4.713500e+03, double 2.927000e+03, double 4.705800e+03, double 2.927000e+03, i32 1, double 8.698200e+03, double 2.927000e+03, double 4.692000e+03, double 2.920500e+03, double 4.692000e+03, double 2.912500e+03, i32 1, double 4.692000e+03, double 2.945600e+03, double 4.698200e+03, double 2.898100e+03, double 4.705800e+03, double 2.898100e+03, i32 1, double 4.713500e+03, double 2.898100e+03, double 4.719700e+03, double 2.945600e+03, double 4.719700e+03, double 2.912500e+03, i32 1, double 4.749200e+03, double 2.920100e+03, double 4.743000e+03, double 2.926600e+03, double 4.735300e+03, double 2.926600e+03, i32 1, double 4.727700e+03, double 2.926600e+03, double 4.721500e+03, double 2.920100e+03, double 4.721500e+03, double 2.912100e+03, i32 1, double 4.721500e+03, double 2.945100e+03, double 4.727700e+03, double 2.897700e+03, double 4.735300e+03, double 2.897700e+03, i32 1, double 4.743000e+03, double 2.897700e+03, double 4.749200e+03, double 2.945100e+03, double 4.749200e+03, double 2.912100e+03, i32 1, double 4.778200e+03, double 2.920100e+03, double 4.772000e+03, double 2.926600e+03, double 4.764300e+03, double 2.926600e+03, i32 1, double 4.756700e+03, double 2.926600e+03, double 4.750500e+03, double 2.920100e+03, double 4.750500e+03, double 2.912100e+03, i32 1, double 4.750500e+03, double 2.945100e+03, double 4.756700e+03, double 2.897700e+03, double 4.764300e+03, double 2.897700e+03, i32 1, double 4.772000e+03, double 2.897700e+03, double 4.778200e+03, double 2.945100e+03, double 4.778200e+03, double 2.912100e+03, i32 1, double 4.801900e+03, double 2.942100e+03, double 4.795700e+03, double 2.948500e+03, double 4.788100e+03, double 2.948500e+03, i32 1, double 4.780500e+03, double 2.948500e+03, double 4.774300e+03, double 2.942100e+03, double 4.774300e+03, double 2.934100e+03, i32 1, double 4.774300e+03, double 2.926100e+03, double 4.780500e+03, double 2.919600e+03, double 4.788100e+03, double 2.919600e+03, i32 1, double 4.795700e+03, double 2.919600e+03, double 4.801900e+03, double 2.926100e+03, double 4.801900e+03, double 2.934100e+03, i32 1, double 4.801500e+03, double 2.972500e+03, double 4.795300e+03, double 2.978900e+03, double 4.787700e+03, double 2.978900e+03, i32 1, double 4.780000e+03, double 2.978900e+03, double 4.773800e+03, double 2.972500e+03, double 4.773800e+03, double 2.964500e+03, i32 1, double 4.773800e+03, double 2.956500e+03, double 4.780000e+03, double 2.950000e+03, double 4.787700e+03, double 2.950000e+03, i32 1, double 4.795300e+03, double 2.950000e+03, double 4.801500e+03, double 2.956500e+03, double 4.801500e+03, double 2.964500e+03, i32 1, double 4.802400e+03, double 3.010200e+03, double 4.796200e+03, double 3.016600e+03, double 4.788500e+03, double 3.016600e+03, i32 1, double 4.780900e+03, double 3.016600e+03, double 4.774700e+03, double 3.010200e+03, double 4.774700e+03, double 3.002200e+03, i32 1, double 4.774700e+03, double 2.994200e+03, double 4.780900e+03, double 2.987700e+03, double 4.788500e+03, double 2.987700e+03, i32 1, double 4.796200e+03, double 2.987700e+03, double 4.802400e+03, double 2.994200e+03, double 4.802400e+03, double 3.002200e+03, i32 1, double 4.802400e+03, double 3.039400e+03, double 4.796200e+03, double 3.455800e+03, double 4.788500e+03, double 3.455800e+03, i32 1, double 4.780900e+03, double 3.455800e+03, double 4.774700e+03, double 3.039400e+03, double 4.774700e+03, double 3.031400e+03, i32 1, double 4.774700e+03, double 3.023400e+03, double 4.780900e+03, double 3.016900e+03, double 4.788500e+03, double 3.016900e+03, i32 1, double 4.796200e+03, double 3.016900e+03, double 4.802400e+03, double 3.023400e+03, double 4.802400e+03, double 3.031400e+03, i32 1, double 4.778600e+03, double 3.063100e+03, double 4.772400e+03, double 3.069600e+03, double 4.764700e+03, double 3.069600e+03, i32 1, double 4.757100e+03, double 3.069600e+03, double 4.750900e+03, double 3.063100e+03, double 4.750900e+03, double 3.055100e+03, i32 1, double 4.750900e+03, double 3.457100e+03, double 4.757100e+03, double 3.450700e+03, double 4.764700e+03, double 3.450700e+03, i32 1, double 4.772400e+03, double 3.450700e+03, double 4.778600e+03, double 3.457100e+03, double 4.778600e+03, double 3.055100e+03, i32 1, double 4.748600e+03, double 3.063600e+03, double 4.742400e+03, double 3.070000e+03, double 4.734700e+03, double 3.070000e+03, i32 1, double 4.727100e+03, double 3.070000e+03, double 4.720900e+03, double 3.063600e+03, double 4.720900e+03, double 3.055600e+03, i32 1, double 4.720900e+03, double 3.457600e+03, double 4.727100e+03, double 3.451100e+03, double 4.734700e+03, double 3.451100e+03, i32 1, double 4.742400e+03, double 3.451100e+03, double 4.748600e+03, double 3.457600e+03, double 4.748600e+03, double 3.055600e+03, i32 1, double 4.719500e+03, double 3.063600e+03, double 4.713300e+03, double 3.070000e+03, double 4.705700e+03, double 3.070000e+03, i32 1, double 4.698000e+03, double 3.070000e+03, double 4.691900e+03, double 3.063600e+03, double 4.691900e+03, double 3.055600e+03, i32 1, double 4.691900e+03, double 3.457600e+03, double 4.698000e+03, double 3.451100e+03, double 4.705700e+03, double 3.451100e+03, i32 1, double 4.713300e+03, double 3.451100e+03, double 4.719500e+03, double 3.457600e+03, double 4.719500e+03, double 3.055600e+03, i32 1, double 4.691300e+03, double 3.064000e+03, double 4.685100e+03, double 3.070500e+03, double 4.677500e+03, double 3.070500e+03, i32 1, double 4.669900e+03, double 3.070500e+03, double 4.663700e+03, double 3.064000e+03, double 4.663700e+03, double 3.056000e+03, i32 1, double 4.663700e+03, double 3.458000e+03, double 4.669900e+03, double 3.451600e+03, double 4.677500e+03, double 3.451600e+03, i32 1, double 4.685100e+03, double 3.451600e+03, double 4.691300e+03, double 3.458000e+03, double 4.691300e+03, double 3.056000e+03, i32 1, double 4.668500e+03, double 3.453000e+03, double 4.662300e+03, double 3.459400e+03, double 4.654700e+03, double 3.459400e+03, i32 1, double 4.647000e+03, double 3.459400e+03, double 4.640900e+03, double 3.453000e+03, double 4.640900e+03, double 3.035000e+03, i32 1, double 4.640900e+03, double 3.027000e+03, double 4.647000e+03, double 3.020500e+03, double 4.654700e+03, double 3.020500e+03, i32 1, double 4.662300e+03, double 3.020500e+03, double 4.668500e+03, double 3.027000e+03, double 4.668500e+03, double 3.035000e+03, i32 1, double 4.668500e+03, double 3.014300e+03, double 4.662300e+03, double 3.020800e+03, double 4.654700e+03, double 3.020800e+03, i32 1, double 4.647000e+03, double 3.020800e+03, double 4.640900e+03, double 3.014300e+03, double 4.640900e+03, double 3.006400e+03, i32 1, double 4.640900e+03, double 2.998400e+03, double 4.647000e+03, double 2.991900e+03, double 4.654700e+03, double 2.991900e+03, i32 1, double 4.662300e+03, double 2.991900e+03, double 4.668500e+03, double 2.998400e+03, double 4.668500e+03, double 3.006400e+03, i32 1, double 4.668100e+03, double 2.941100e+03, double 4.661900e+03, double 2.947600e+03, double 4.654200e+03, double 2.947600e+03, i32 1, double 4.646600e+03, double 2.947600e+03, double 4.640400e+03, double 2.941100e+03, double 4.640400e+03, double 2.933100e+03, i32 1, double 4.640400e+03, double 2.925200e+03, double 4.646600e+03, double 2.918700e+03, double 4.654200e+03, double 2.918700e+03, i32 1, double 4.661900e+03, double 2.918700e+03, double 4.668100e+03, double 2.925200e+03, double 4.668100e+03, double 2.933100e+03, i32 1, double 4.668500e+03, double 2.971600e+03, double 4.662300e+03, double 2.978100e+03, double 4.654700e+03, double 2.978100e+03, i32 1, double 4.647000e+03, double 2.978100e+03, double 4.640900e+03, double 2.971600e+03, double 4.640900e+03, double 2.963600e+03, i32 1, double 4.640900e+03, double 2.955700e+03, double 4.647000e+03, double 2.949200e+03, double 4.654700e+03, double 2.949200e+03, i32 1, double 4.662300e+03, double 2.949200e+03, double 4.668500e+03, double 2.955700e+03, double 4.668500e+03, double 2.963600e+03, i32 2, i32 1, double 4.691300e+03, double 3.056000e+03, i32 2, i32 1, double 4.748600e+03, double 3.055600e+03, i32 2, i32 1, double 4.778200e+03, double 2.912100e+03, i32 2, i32 1, double 4.749200e+03, double 2.912100e+03, i32 2, i32 1, double 4.802400e+03, double 3.031400e+03, i32 2, i32 1, double 4.778600e+03, double 3.055100e+03, i32 2, i32 1, double 4.801500e+03, double 2.964500e+03, i32 2, i32 1, double 4.802400e+03, double 3.002200e+03, i32 2, i32 1, double 4.719700e+03, double 2.912500e+03, i32 2, i32 1, double 4.801900e+03, double 2.934100e+03, i32 2, i32 1, double 4.719500e+03, double 3.055600e+03, i32 2, i32 1, double 4.668500e+03, double 3.006400e+03, i32 2, i32 1, double 4.668500e+03, double 3.035000e+03, i32 2, i32 1, double 4.668100e+03, double 2.933100e+03, i32 2, i32 1, double 4.668500e+03, double 2.963600e+03, i32 2, i32 48)
   ret i32 0
 }
 
diff --git a/test/CodeGen/Thumb2/large-stack.ll b/test/CodeGen/Thumb2/large-stack.ll
index 8d79da7982b1..4fe49825fa32 100644
--- a/test/CodeGen/Thumb2/large-stack.ll
+++ b/test/CodeGen/Thumb2/large-stack.ll
@@ -29,13 +29,13 @@ define i32 @test3() {
 ; DARWIN: sub.w sp, sp, #805306368
 ; DARWIN: sub sp, #20
 ; LINUX-LABEL: test3:
-; LINUX: push.w {r4, r7, r11, lr}
+; LINUX: push {r4, r6, r7, lr}
 ; LINUX: sub.w sp, sp, #805306368
 ; LINUX: sub sp, #16
     %retval = alloca i32, align 4
     %tmp = alloca i32, align 4
     %a = alloca [805306369 x i8], align 16
     store i32 0, i32* %tmp
-    %tmp1 = load i32* %tmp
+    %tmp1 = load i32, i32* %tmp
     ret i32 %tmp1
 }
diff --git a/test/CodeGen/Thumb2/lsr-deficiency.ll b/test/CodeGen/Thumb2/lsr-deficiency.ll
index 7ce6768a2187..ccf7faedac6e 100644
--- a/test/CodeGen/Thumb2/lsr-deficiency.ll
+++ b/test/CodeGen/Thumb2/lsr-deficiency.ll
@@ -10,7 +10,7 @@ define void @t() nounwind optsize {
 ; CHECK-LABEL: t:
 ; CHECK: mov{{.*}}, #1000
 entry:
-  %.pre = load i32* @G, align 4                   ; <i32> [#uses=1]
+  %.pre = load i32, i32* @G, align 4                   ; <i32> [#uses=1]
   br label %bb
 
 bb:                                               ; preds = %bb, %entry
@@ -22,9 +22,9 @@ bb:                                               ; preds = %bb, %entry
   %0 = phi i32 [ %.pre, %entry ], [ %3, %bb ]     ; <i32> [#uses=1]
   %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
   %tmp5 = sub i32 1000, %indvar                   ; <i32> [#uses=1]
-  %1 = load i32** @array, align 4                 ; <i32*> [#uses=1]
-  %scevgep = getelementptr i32* %1, i32 %tmp5     ; <i32*> [#uses=1]
-  %2 = load i32* %scevgep, align 4                ; <i32> [#uses=1]
+  %1 = load i32*, i32** @array, align 4                 ; <i32*> [#uses=1]
+  %scevgep = getelementptr i32, i32* %1, i32 %tmp5     ; <i32*> [#uses=1]
+  %2 = load i32, i32* %scevgep, align 4                ; <i32> [#uses=1]
   %3 = add nsw i32 %2, %0                         ; <i32> [#uses=2]
   store i32 %3, i32* @G, align 4
   %indvar.next = add i32 %indvar, 1               ; <i32> [#uses=2]
diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll
index d9da846294c4..2b1caa393072 100644
--- a/test/CodeGen/Thumb2/machine-licm.ll
+++ b/test/CodeGen/Thumb2/machine-licm.ll
@@ -29,14 +29,14 @@ bb.nph:                                           ; preds = %entry
 ; PIC: LBB0_
 ; PIC-NOT: LCPI0_0:
 ; PIC: .section
-  %.pre = load i32* @GV, align 4                  ; <i32> [#uses=1]
+  %.pre = load i32, i32* @GV, align 4                  ; <i32> [#uses=1]
   br label %bb
 
 bb:                                               ; preds = %bb, %bb.nph
   %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ]    ; <i32> [#uses=1]
   %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ]     ; <i32> [#uses=2]
-  %scevgep = getelementptr i32* %vals, i32 %i.03  ; <i32*> [#uses=1]
-  %2 = load i32* %scevgep, align 4                ; <i32> [#uses=1]
+  %scevgep = getelementptr i32, i32* %vals, i32 %i.03  ; <i32*> [#uses=1]
+  %2 = load i32, i32* %scevgep, align 4                ; <i32> [#uses=1]
   %3 = add nsw i32 %1, %2                         ; <i32> [#uses=2]
   store i32 %3, i32* @GV, align 4
   %4 = add i32 %i.03, 1                           ; <i32> [#uses=2]
@@ -58,10 +58,10 @@ bb1:
 ; CHECK: %bb1
   %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ]
   %tmp1 = shl i32 %indvar, 2
-  %gep1 = getelementptr i8* %ptr1, i32 %tmp1
+  %gep1 = getelementptr i8, i8* %ptr1, i32 %tmp1
   %tmp2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %gep1, i32 1)
   %tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <4 x float> %tmp2)
-  %gep2 = getelementptr i8* %ptr2, i32 %tmp1
+  %gep2 = getelementptr i8, i8* %ptr2, i32 %tmp1
   call void @llvm.arm.neon.vst1.v4f32(i8* %gep2, <4 x float> %tmp3, i32 1)
   %indvar.next = add i32 %indvar, 1
   %cond = icmp eq i32 %indvar.next, 10
diff --git a/test/CodeGen/Thumb2/pic-load.ll b/test/CodeGen/Thumb2/pic-load.ll
index b22fd1dc72e1..53d456c53452 100644
--- a/test/CodeGen/Thumb2/pic-load.ll
+++ b/test/CodeGen/Thumb2/pic-load.ll
@@ -10,9 +10,9 @@ entry:
 ; CHECK-LABEL: atexit:
 ; CHECK: add r0, pc
 	%r = alloca %struct.one_atexit_routine, align 4		; <%struct.one_atexit_routine*> [#uses=3]
-	%0 = getelementptr %struct.one_atexit_routine* %r, i32 0, i32 0, i32 0		; <void ()**> [#uses=1]
+	%0 = getelementptr %struct.one_atexit_routine, %struct.one_atexit_routine* %r, i32 0, i32 0, i32 0		; <void ()**> [#uses=1]
 	store void ()* %func, void ()** %0, align 4
-	%1 = getelementptr %struct.one_atexit_routine* %r, i32 0, i32 1		; <i32*> [#uses=1]
+	%1 = getelementptr %struct.one_atexit_routine, %struct.one_atexit_routine* %r, i32 0, i32 1		; <i32*> [#uses=1]
 	store i32 0, i32* %1, align 4
 	%2 = call  i32 @atexit_common(%struct.one_atexit_routine* %r, i8* bitcast ({ }* @__dso_handle to i8*)) nounwind		; <i32> [#uses=1]
 	ret i32 %2
diff --git a/test/CodeGen/Thumb2/stack_guard_remat.ll b/test/CodeGen/Thumb2/stack_guard_remat.ll
index c8ea8714d317..cf34e8c0c2fb 100644
--- a/test/CodeGen/Thumb2/stack_guard_remat.ll
+++ b/test/CodeGen/Thumb2/stack_guard_remat.ll
@@ -25,7 +25,7 @@ define i32 @test_stack_guard_remat() #0 {
   %a1 = alloca [256 x i32], align 4
   %1 = bitcast [256 x i32]* %a1 to i8*
   call void @llvm.lifetime.start(i64 1024, i8* %1)
-  %2 = getelementptr inbounds [256 x i32]* %a1, i32 0, i32 0
+  %2 = getelementptr inbounds [256 x i32], [256 x i32]* %a1, i32 0, i32 0
   call void @foo3(i32* %2) #3
   call void asm sideeffect "foo2", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{sp},~{lr}"()
   call void @llvm.lifetime.end(i64 1024, i8* %1)
diff --git a/test/CodeGen/Thumb2/tail-call-r9.ll b/test/CodeGen/Thumb2/tail-call-r9.ll
index 673aa7c12ebc..33cbd3d37c99 100644
--- a/test/CodeGen/Thumb2/tail-call-r9.ll
+++ b/test/CodeGen/Thumb2/tail-call-r9.ll
@@ -7,7 +7,7 @@
 define arm_aapcscc void @test(i32 %a) nounwind {
 ; CHECK-LABEL: test:
 ; CHECK-NOT: bx r9
-  %tmp = load void ()** @foo, align 4
+  %tmp = load void ()*, void ()** @foo, align 4
   tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r12}"() nounwind
   tail call arm_aapcscc void %tmp() nounwind
   ret void
diff --git a/test/CodeGen/Thumb2/thumb2-call-tc.ll b/test/CodeGen/Thumb2/thumb2-call-tc.ll
index 2902949d9768..96f63ba9ac0b 100644
--- a/test/CodeGen/Thumb2/thumb2-call-tc.ll
+++ b/test/CodeGen/Thumb2/thumb2-call-tc.ll
@@ -22,7 +22,7 @@ define void @h() {
 
 ; LINUX-LABEL: h:
 ; LINUX: bx r0 @ TAILCALL
-        %tmp = load i32 ()** @t         ; <i32 ()*> [#uses=1]
+        %tmp = load i32 ()*, i32 ()** @t         ; <i32 ()*> [#uses=1]
         %tmp.upgrd.2 = tail call i32 %tmp( )            ; <i32> [#uses=0]
         ret void
 }
diff --git a/test/CodeGen/Thumb2/thumb2-call.ll b/test/CodeGen/Thumb2/thumb2-call.ll
index 1d2eaa77c7fe..62b47a44b494 100644
--- a/test/CodeGen/Thumb2/thumb2-call.ll
+++ b/test/CodeGen/Thumb2/thumb2-call.ll
@@ -21,7 +21,7 @@ define void @h() {
 
 ; LINUX-LABEL: h:
 ; LINUX: blx r0
-        %tmp = load i32 ()** @t         ; <i32 ()*> [#uses=1]
+        %tmp = load i32 ()*, i32 ()** @t         ; <i32 ()*> [#uses=1]
         %tmp.upgrd.2 = call i32 %tmp( )            ; <i32> [#uses=0]
         ret void
 }
diff --git a/test/CodeGen/Thumb2/thumb2-cbnz.ll b/test/CodeGen/Thumb2/thumb2-cbnz.ll
index f0f79168c904..8104dc714da0 100644
--- a/test/CodeGen/Thumb2/thumb2-cbnz.ll
+++ b/test/CodeGen/Thumb2/thumb2-cbnz.ll
@@ -29,7 +29,7 @@ bb9:                                              ; preds = %bb7
   br label %bb11
 
 bb11:                                             ; preds = %bb9, %bb7
-  %1 = getelementptr i32* undef, i32 0
+  %1 = getelementptr i32, i32* undef, i32 0
   store i32 0, i32* %1
   ret void
 }
diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll b/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll
index d86a897a4a09..ebc12dc3c1d5 100644
--- a/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll
@@ -63,7 +63,7 @@ bb17:		; preds = %cond_false, %cond_true, %entry
 
 define void @foo(i32 %a) nounwind {
 entry:
-	%tmp = load i32** @x		; <i32*> [#uses=1]
+	%tmp = load i32*, i32** @x		; <i32*> [#uses=1]
 	store i32 %a, i32* %tmp
 	ret void
 }
diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
index 13a1ca2e26cd..da1057b8bb4a 100644
--- a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
@@ -65,7 +65,7 @@ bb17:		; preds = %cond_false, %cond_true, %entry
 
 define void @foo(i32 %a) nounwind {
 entry:
-	%tmp = load i32** @x		; <i32*> [#uses=1]
+	%tmp = load i32*, i32** @x		; <i32*> [#uses=1]
 	store i32 %a, i32* %tmp
 	ret void
 }
diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
index a861912fe113..1d2ba0008be8 100644
--- a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
@@ -15,7 +15,7 @@ entry:
 	br i1 %tmp7, label %cond_true, label %UnifiedReturnBlock
 
 cond_true:		; preds = %entry
-	%tmp10 = call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp10 = call i32 (...) @bar( )		; <i32> [#uses=0]
 	ret void
 
 UnifiedReturnBlock:		; preds = %entry
@@ -41,9 +41,9 @@ entry:
 	br label %tailrecurse
 
 tailrecurse:		; preds = %bb, %entry
-	%tmp6 = load %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=1]
-	%tmp9 = load %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=2]
-	%tmp12 = load %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=1]
+	%tmp6 = load %struct.quad_struct*, %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=1]
+	%tmp9 = load %struct.quad_struct*, %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=2]
+	%tmp12 = load %struct.quad_struct*, %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=1]
 	%tmp14 = icmp eq %struct.quad_struct* null, null		; <i1> [#uses=1]
 	%tmp17 = icmp eq %struct.quad_struct* %tmp6, null		; <i1> [#uses=1]
 	%tmp23 = icmp eq %struct.quad_struct* %tmp9, null		; <i1> [#uses=1]
diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt3.ll b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll
index 79667d43b95e..24eb1a98a066 100644
--- a/test/CodeGen/Thumb2/thumb2-ifcvt3.ll
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll
@@ -25,7 +25,7 @@ bb52:                                             ; preds = %newFuncRoot
 ; CHECK: movne
 ; CHECK: moveq
 ; CHECK: pop
-  %0 = load i64* @posed, align 4                  ; <i64> [#uses=3]
+  %0 = load i64, i64* @posed, align 4                  ; <i64> [#uses=3]
   %1 = sub i64 %0, %.reload78                     ; <i64> [#uses=1]
   %2 = ashr i64 %1, 1                             ; <i64> [#uses=3]
   %3 = icmp eq i64 %2, 0                          ; <i1> [#uses=1]
diff --git a/test/CodeGen/Thumb2/thumb2-ldm.ll b/test/CodeGen/Thumb2/thumb2-ldm.ll
index adfcf2b6aaf1..28903aca3267 100644
--- a/test/CodeGen/Thumb2/thumb2-ldm.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldm.ll
@@ -7,8 +7,8 @@ define i32 @t1() {
 ; CHECK: push {r7, lr}
 ; CHECK: ldrd
 ; CHECK: pop {r7, pc}
-        %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0)            ; <i32> [#uses=1]
-        %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1)           ; <i32> [#uses=1]
+        %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 0)            ; <i32> [#uses=1]
+        %tmp3 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 1)           ; <i32> [#uses=1]
         %tmp4 = call i32 @f1( i32 %tmp, i32 %tmp3 )                ; <i32> [#uses=1]
         ret i32 %tmp4
 }
@@ -18,9 +18,9 @@ define i32 @t2() {
 ; CHECK: push {r7, lr}
 ; CHECK: ldm
 ; CHECK: pop {r7, pc}
-        %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2)            ; <i32> [#uses=1]
-        %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3)           ; <i32> [#uses=1]
-        %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4)           ; <i32> [#uses=1]
+        %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 2)            ; <i32> [#uses=1]
+        %tmp3 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 3)           ; <i32> [#uses=1]
+        %tmp5 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 4)           ; <i32> [#uses=1]
         %tmp6 = call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 )             ; <i32> [#uses=1]
         ret i32 %tmp6
 }
@@ -30,9 +30,9 @@ define i32 @t3() {
 ; CHECK: push {r7, lr}
 ; CHECK: ldm
 ; CHECK: pop {r7, pc}
-        %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1)            ; <i32> [#uses=1]
-        %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2)           ; <i32> [#uses=1]
-        %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3)           ; <i32> [#uses=1]
+        %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 1)            ; <i32> [#uses=1]
+        %tmp3 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 2)           ; <i32> [#uses=1]
+        %tmp5 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 3)           ; <i32> [#uses=1]
         %tmp6 = call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 )             ; <i32> [#uses=1]
         ret i32 %tmp6
 }
diff --git a/test/CodeGen/Thumb2/thumb2-ldr.ll b/test/CodeGen/Thumb2/thumb2-ldr.ll
index c25ed789de04..4b3ce86ef8d1 100644
--- a/test/CodeGen/Thumb2/thumb2-ldr.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldr.ll
@@ -4,7 +4,7 @@ define i32 @f1(i32* %v) {
 entry:
 ; CHECK-LABEL: f1:
 ; CHECK: ldr r0, [r0]
-        %tmp = load i32* %v
+        %tmp = load i32, i32* %v
         ret i32 %tmp
 }
 
@@ -12,8 +12,8 @@ define i32 @f2(i32* %v) {
 entry:
 ; CHECK-LABEL: f2:
 ; CHECK: ldr.w r0, [r0, #4092]
-        %tmp2 = getelementptr i32* %v, i32 1023
-        %tmp = load i32* %tmp2
+        %tmp2 = getelementptr i32, i32* %v, i32 1023
+        %tmp = load i32, i32* %tmp2
         ret i32 %tmp
 }
 
@@ -22,8 +22,8 @@ entry:
 ; CHECK-LABEL: f3:
 ; CHECK: mov.w r1, #4096
 ; CHECK: ldr r0, [r0, r1]
-        %tmp2 = getelementptr i32* %v, i32 1024
-        %tmp = load i32* %tmp2
+        %tmp2 = getelementptr i32, i32* %v, i32 1024
+        %tmp = load i32, i32* %tmp2
         ret i32 %tmp
 }
 
@@ -33,7 +33,7 @@ entry:
 ; CHECK: ldr r0, [r0, #-128]
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i32*
-        %tmp3 = load i32* %tmp2
+        %tmp3 = load i32, i32* %tmp2
         ret i32 %tmp3
 }
 
@@ -43,7 +43,7 @@ entry:
 ; CHECK: ldr r0, [r0, r1]
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i32*
-        %tmp3 = load i32* %tmp2
+        %tmp3 = load i32, i32* %tmp2
         ret i32 %tmp3
 }
 
@@ -54,7 +54,7 @@ entry:
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
         %tmp3 = inttoptr i32 %tmp2 to i32*
-        %tmp4 = load i32* %tmp3
+        %tmp4 = load i32, i32* %tmp3
         ret i32 %tmp4
 }
 
@@ -67,6 +67,6 @@ entry:
         %tmp1 = lshr i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
         %tmp3 = inttoptr i32 %tmp2 to i32*
-        %tmp4 = load i32* %tmp3
+        %tmp4 = load i32, i32* %tmp3
         ret i32 %tmp4
 }
diff --git a/test/CodeGen/Thumb2/thumb2-ldr_ext.ll b/test/CodeGen/Thumb2/thumb2-ldr_ext.ll
index b50b33320597..a911775ebc7b 100644
--- a/test/CodeGen/Thumb2/thumb2-ldr_ext.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldr_ext.ll
@@ -1,25 +1,25 @@
 ; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
 
 define i32 @test1(i8* %v.pntr.s0.u1) {
-    %tmp.u = load i8* %v.pntr.s0.u1
+    %tmp.u = load i8, i8* %v.pntr.s0.u1
     %tmp1.s = zext i8 %tmp.u to i32
     ret i32 %tmp1.s
 }
 
 define i32 @test2(i16* %v.pntr.s0.u1) {
-    %tmp.u = load i16* %v.pntr.s0.u1
+    %tmp.u = load i16, i16* %v.pntr.s0.u1
     %tmp1.s = zext i16 %tmp.u to i32
     ret i32 %tmp1.s
 }
 
 define i32 @test3(i8* %v.pntr.s1.u0) {
-    %tmp.s = load i8* %v.pntr.s1.u0
+    %tmp.s = load i8, i8* %v.pntr.s1.u0
     %tmp1.s = sext i8 %tmp.s to i32
     ret i32 %tmp1.s
 }
 
 define i32 @test4() {
-    %tmp.s = load i16* null
+    %tmp.s = load i16, i16* null
     %tmp1.s = sext i16 %tmp.s to i32
     ret i32 %tmp1.s
 }
diff --git a/test/CodeGen/Thumb2/thumb2-ldr_post.ll b/test/CodeGen/Thumb2/thumb2-ldr_post.ll
index c26e6b154e55..cb7e795a0450 100644
--- a/test/CodeGen/Thumb2/thumb2-ldr_post.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldr_post.ll
@@ -3,7 +3,7 @@
 define i32 @test(i32 %a, i32 %b, i32 %c) {
         %tmp1 = mul i32 %a, %b          ; <i32> [#uses=2]
         %tmp2 = inttoptr i32 %tmp1 to i32*              ; <i32*> [#uses=1]
-        %tmp3 = load i32* %tmp2         ; <i32> [#uses=1]
+        %tmp3 = load i32, i32* %tmp2         ; <i32> [#uses=1]
         %tmp4 = sub i32 %tmp1, 8               ; <i32> [#uses=1]
         %tmp5 = mul i32 %tmp4, %tmp3            ; <i32> [#uses=1]
         ret i32 %tmp5
diff --git a/test/CodeGen/Thumb2/thumb2-ldr_pre.ll b/test/CodeGen/Thumb2/thumb2-ldr_pre.ll
index cafb02a4984f..2bb327c8f864 100644
--- a/test/CodeGen/Thumb2/thumb2-ldr_pre.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldr_pre.ll
@@ -1,8 +1,8 @@
 ; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
 
 define i32* @test1(i32* %X, i32* %dest) {
-        %Y = getelementptr i32* %X, i32 4               ; <i32*> [#uses=2]
-        %A = load i32* %Y               ; <i32> [#uses=1]
+        %Y = getelementptr i32, i32* %X, i32 4               ; <i32*> [#uses=2]
+        %A = load i32, i32* %Y               ; <i32> [#uses=1]
         store i32 %A, i32* %dest
         ret i32* %Y
 }
@@ -12,7 +12,7 @@ define i32* @test1(i32* %X, i32* %dest) {
 define i32 @test2(i32 %a, i32 %b) {
         %tmp1 = sub i32 %a, 64          ; <i32> [#uses=2]
         %tmp2 = inttoptr i32 %tmp1 to i32*              ; <i32*> [#uses=1]
-        %tmp3 = load i32* %tmp2         ; <i32> [#uses=1]
+        %tmp3 = load i32, i32* %tmp2         ; <i32> [#uses=1]
         %tmp4 = sub i32 %tmp1, %b               ; <i32> [#uses=1]
         %tmp5 = add i32 %tmp4, %tmp3            ; <i32> [#uses=1]
         ret i32 %tmp5
@@ -21,8 +21,8 @@ define i32 @test2(i32 %a, i32 %b) {
 ; CHECK: ldr{{.*}}!
 
 define i8* @test3(i8* %X, i32* %dest) {
-        %tmp1 = getelementptr i8* %X, i32 4
-        %tmp2 = load i8* %tmp1
+        %tmp1 = getelementptr i8, i8* %X, i32 4
+        %tmp2 = load i8, i8* %tmp1
         %tmp3 = sext i8 %tmp2 to i32
         store i32 %tmp3, i32* %dest
         ret i8* %tmp1
diff --git a/test/CodeGen/Thumb2/thumb2-ldrb.ll b/test/CodeGen/Thumb2/thumb2-ldrb.ll
index 0b3441eb1e22..cf8fd6dca6df 100644
--- a/test/CodeGen/Thumb2/thumb2-ldrb.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldrb.ll
@@ -4,7 +4,7 @@ define i8 @f1(i8* %v) {
 entry:
 ; CHECK-LABEL: f1:
 ; CHECK: ldrb r0, [r0]
-        %tmp = load i8* %v
+        %tmp = load i8, i8* %v
         ret i8 %tmp
 }
 
@@ -12,8 +12,8 @@ define i8 @f2(i8* %v) {
 entry:
 ; CHECK-LABEL: f2:
 ; CHECK: ldrb r0, [r0, #-1]
-        %tmp2 = getelementptr i8* %v, i8 1023
-        %tmp = load i8* %tmp2
+        %tmp2 = getelementptr i8, i8* %v, i8 1023
+        %tmp = load i8, i8* %tmp2
         ret i8 %tmp
 }
 
@@ -24,7 +24,7 @@ entry:
 ; CHECK: ldrb r0, [r0, r1]
         %tmp1 = add i32 %base, 4096
         %tmp2 = inttoptr i32 %tmp1 to i8*
-        %tmp3 = load i8* %tmp2
+        %tmp3 = load i8, i8* %tmp2
         ret i8 %tmp3
 }
 
@@ -34,7 +34,7 @@ entry:
 ; CHECK: ldrb r0, [r0, #-128]
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i8*
-        %tmp3 = load i8* %tmp2
+        %tmp3 = load i8, i8* %tmp2
         ret i8 %tmp3
 }
 
@@ -44,7 +44,7 @@ entry:
 ; CHECK: ldrb r0, [r0, r1]
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i8*
-        %tmp3 = load i8* %tmp2
+        %tmp3 = load i8, i8* %tmp2
         ret i8 %tmp3
 }
 
@@ -55,7 +55,7 @@ entry:
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
         %tmp3 = inttoptr i32 %tmp2 to i8*
-        %tmp4 = load i8* %tmp3
+        %tmp4 = load i8, i8* %tmp3
         ret i8 %tmp4
 }
 
@@ -67,6 +67,6 @@ entry:
         %tmp1 = lshr i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
         %tmp3 = inttoptr i32 %tmp2 to i8*
-        %tmp4 = load i8* %tmp3
+        %tmp4 = load i8, i8* %tmp3
         ret i8 %tmp4
 }
diff --git a/test/CodeGen/Thumb2/thumb2-ldrd.ll b/test/CodeGen/Thumb2/thumb2-ldrd.ll
index 2e83ea146cd0..c25359b40577 100644
--- a/test/CodeGen/Thumb2/thumb2-ldrd.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldrd.ll
@@ -6,8 +6,8 @@ define i64 @t(i64 %a) nounwind readonly {
 entry:
 ; CHECK: ldrd
 ; CHECK: umull
-	%0 = load i64** @b, align 4
-	%1 = load i64* %0, align 4
+	%0 = load i64*, i64** @b, align 4
+	%1 = load i64, i64* %0, align 4
 	%2 = mul i64 %1, %a
 	ret i64 %2
 }
diff --git a/test/CodeGen/Thumb2/thumb2-ldrh.ll b/test/CodeGen/Thumb2/thumb2-ldrh.ll
index db5dcfac2ba1..33dd681bb04b 100644
--- a/test/CodeGen/Thumb2/thumb2-ldrh.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldrh.ll
@@ -4,7 +4,7 @@ define i16 @f1(i16* %v) {
 entry:
 ; CHECK-LABEL: f1:
 ; CHECK: ldrh r0, [r0]
-        %tmp = load i16* %v
+        %tmp = load i16, i16* %v
         ret i16 %tmp
 }
 
@@ -12,8 +12,8 @@ define i16 @f2(i16* %v) {
 entry:
 ; CHECK-LABEL: f2:
 ; CHECK: ldrh.w r0, [r0, #2046]
-        %tmp2 = getelementptr i16* %v, i16 1023
-        %tmp = load i16* %tmp2
+        %tmp2 = getelementptr i16, i16* %v, i16 1023
+        %tmp = load i16, i16* %tmp2
         ret i16 %tmp
 }
 
@@ -22,8 +22,8 @@ entry:
 ; CHECK-LABEL: f3:
 ; CHECK: mov.w r1, #4096
 ; CHECK: ldrh r0, [r0, r1]
-        %tmp2 = getelementptr i16* %v, i16 2048
-        %tmp = load i16* %tmp2
+        %tmp2 = getelementptr i16, i16* %v, i16 2048
+        %tmp = load i16, i16* %tmp2
         ret i16 %tmp
 }
 
@@ -33,7 +33,7 @@ entry:
 ; CHECK: ldrh r0, [r0, #-128]
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i16*
-        %tmp3 = load i16* %tmp2
+        %tmp3 = load i16, i16* %tmp2
         ret i16 %tmp3
 }
 
@@ -43,7 +43,7 @@ entry:
 ; CHECK: ldrh r0, [r0, r1]
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i16*
-        %tmp3 = load i16* %tmp2
+        %tmp3 = load i16, i16* %tmp2
         ret i16 %tmp3
 }
 
@@ -54,7 +54,7 @@ entry:
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
         %tmp3 = inttoptr i32 %tmp2 to i16*
-        %tmp4 = load i16* %tmp3
+        %tmp4 = load i16, i16* %tmp3
         ret i16 %tmp4
 }
 
@@ -66,6 +66,6 @@ entry:
         %tmp1 = lshr i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
         %tmp3 = inttoptr i32 %tmp2 to i16*
-        %tmp4 = load i16* %tmp3
+        %tmp4 = load i16, i16* %tmp3
         ret i16 %tmp4
 }
diff --git a/test/CodeGen/Thumb2/thumb2-smul.ll b/test/CodeGen/Thumb2/thumb2-smul.ll
index 67783d284e9c..937f7737f2b3 100644
--- a/test/CodeGen/Thumb2/thumb2-smul.ll
+++ b/test/CodeGen/Thumb2/thumb2-smul.ll
@@ -6,7 +6,7 @@
 define i32 @f1(i32 %y) {
 ; CHECK: f1
 ; CHECK: smulbt r0, r1, r0
-        %tmp = load i16* @x             ; <i16> [#uses=1]
+        %tmp = load i16, i16* @x             ; <i16> [#uses=1]
         %tmp1 = add i16 %tmp, 2         ; <i16> [#uses=1]
         %tmp2 = sext i16 %tmp1 to i32           ; <i32> [#uses=1]
         %tmp3 = ashr i32 %y, 16         ; <i32> [#uses=1]
diff --git a/test/CodeGen/Thumb2/thumb2-spill-q.ll b/test/CodeGen/Thumb2/thumb2-spill-q.ll
index d1deb461574f..e0f7b5bd919c 100644
--- a/test/CodeGen/Thumb2/thumb2-spill-q.ll
+++ b/test/CodeGen/Thumb2/thumb2-spill-q.ll
@@ -43,7 +43,7 @@ entry:
   store float 0.000000e+00, float* undef, align 4
   %ld12 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
   store float 0.000000e+00, float* undef, align 4
-  %val173 = load <4 x float>* undef               ; <<4 x float>> [#uses=1]
+  %val173 = load <4 x float>, <4 x float>* undef               ; <<4 x float>> [#uses=1]
   br label %bb4
 
 bb4:                                              ; preds = %bb193, %entry
diff --git a/test/CodeGen/Thumb2/thumb2-str.ll b/test/CodeGen/Thumb2/thumb2-str.ll
index 4008145b0732..9bda67ae406c 100644
--- a/test/CodeGen/Thumb2/thumb2-str.ll
+++ b/test/CodeGen/Thumb2/thumb2-str.ll
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a, i32* %v) {
 define i32 @f2(i32 %a, i32* %v) {
 ; CHECK-LABEL: f2:
 ; CHECK: str.w r0, [r1, #4092]
-        %tmp2 = getelementptr i32* %v, i32 1023
+        %tmp2 = getelementptr i32, i32* %v, i32 1023
         store i32 %a, i32* %tmp2
         ret i32 %a
 }
@@ -18,7 +18,7 @@ define i32 @f2(i32 %a, i32* %v) {
 define i32 @f2a(i32 %a, i32* %v) {
 ; CHECK-LABEL: f2a:
 ; CHECK: str r0, [r1, #-128]
-        %tmp2 = getelementptr i32* %v, i32 -32
+        %tmp2 = getelementptr i32, i32* %v, i32 -32
         store i32 %a, i32* %tmp2
         ret i32 %a
 }
@@ -27,7 +27,7 @@ define i32 @f3(i32 %a, i32* %v) {
 ; CHECK-LABEL: f3:
 ; CHECK: mov.w r2, #4096
 ; CHECK: str r0, [r1, r2]
-        %tmp2 = getelementptr i32* %v, i32 1024
+        %tmp2 = getelementptr i32, i32* %v, i32 1024
         store i32 %a, i32* %tmp2
         ret i32 %a
 }
diff --git a/test/CodeGen/Thumb2/thumb2-str_post.ll b/test/CodeGen/Thumb2/thumb2-str_post.ll
index aed849e50f74..377c814823cb 100644
--- a/test/CodeGen/Thumb2/thumb2-str_post.ll
+++ b/test/CodeGen/Thumb2/thumb2-str_post.ll
@@ -3,7 +3,7 @@
 define i16 @test1(i32* %X, i16* %A) {
 ; CHECK-LABEL: test1:
 ; CHECK: strh {{.*}}[{{.*}}], #-4
-        %Y = load i32* %X               ; <i32> [#uses=1]
+        %Y = load i32, i32* %X               ; <i32> [#uses=1]
         %tmp1 = trunc i32 %Y to i16             ; <i16> [#uses=1]
         store i16 %tmp1, i16* %A
         %tmp2 = ptrtoint i16* %A to i16         ; <i16> [#uses=1]
@@ -14,7 +14,7 @@ define i16 @test1(i32* %X, i16* %A) {
 define i32 @test2(i32* %X, i32* %A) {
 ; CHECK-LABEL: test2:
 ; CHECK: str {{.*}}[{{.*}}],
-        %Y = load i32* %X               ; <i32> [#uses=1]
+        %Y = load i32, i32* %X               ; <i32> [#uses=1]
         store i32 %Y, i32* %A
         %tmp1 = ptrtoint i32* %A to i32         ; <i32> [#uses=1]
         %tmp2 = sub i32 %tmp1, 4                ; <i32> [#uses=1]
diff --git a/test/CodeGen/Thumb2/thumb2-str_pre.ll b/test/CodeGen/Thumb2/thumb2-str_pre.ll
index e957400fe28f..d69a1024fadb 100644
--- a/test/CodeGen/Thumb2/thumb2-str_pre.ll
+++ b/test/CodeGen/Thumb2/thumb2-str_pre.ll
@@ -3,8 +3,8 @@
 define void @test1(i32* %X, i32* %A, i32** %dest) {
 ; CHECK: test1
 ; CHECK: str  r1, [r0, #16]!
-        %B = load i32* %A               ; <i32> [#uses=1]
-        %Y = getelementptr i32* %X, i32 4               ; <i32*> [#uses=2]
+        %B = load i32, i32* %A               ; <i32> [#uses=1]
+        %Y = getelementptr i32, i32* %X, i32 4               ; <i32*> [#uses=2]
         store i32 %B, i32* %Y
         store i32* %Y, i32** %dest
         ret void
@@ -13,8 +13,8 @@ define void @test1(i32* %X, i32* %A, i32** %dest) {
 define i16* @test2(i16* %X, i32* %A) {
 ; CHECK: test2
 ; CHECK: strh r1, [r0, #8]!
-        %B = load i32* %A               ; <i32> [#uses=1]
-        %Y = getelementptr i16* %X, i32 4               ; <i16*> [#uses=2]
+        %B = load i32, i32* %A               ; <i32> [#uses=1]
+        %Y = getelementptr i16, i16* %X, i32 4               ; <i16*> [#uses=2]
         %tmp = trunc i32 %B to i16              ; <i16> [#uses=1]
         store i16 %tmp, i16* %Y
         ret i16* %Y
diff --git a/test/CodeGen/Thumb2/thumb2-strb.ll b/test/CodeGen/Thumb2/thumb2-strb.ll
index a2558eccc2b1..8ee9d2d158ea 100644
--- a/test/CodeGen/Thumb2/thumb2-strb.ll
+++ b/test/CodeGen/Thumb2/thumb2-strb.ll
@@ -10,7 +10,7 @@ define i8 @f1(i8 %a, i8* %v) {
 define i8 @f2(i8 %a, i8* %v) {
 ; CHECK-LABEL: f2:
 ; CHECK: strb.w r0, [r1, #4092]
-        %tmp2 = getelementptr i8* %v, i32 4092
+        %tmp2 = getelementptr i8, i8* %v, i32 4092
         store i8 %a, i8* %tmp2
         ret i8 %a
 }
@@ -18,7 +18,7 @@ define i8 @f2(i8 %a, i8* %v) {
 define i8 @f2a(i8 %a, i8* %v) {
 ; CHECK-LABEL: f2a:
 ; CHECK: strb r0, [r1, #-128]
-        %tmp2 = getelementptr i8* %v, i32 -128
+        %tmp2 = getelementptr i8, i8* %v, i32 -128
         store i8 %a, i8* %tmp2
         ret i8 %a
 }
@@ -27,7 +27,7 @@ define i8 @f3(i8 %a, i8* %v) {
 ; CHECK-LABEL: f3:
 ; CHECK: mov.w r2, #4096
 ; CHECK: strb r0, [r1, r2]
-        %tmp2 = getelementptr i8* %v, i32 4096
+        %tmp2 = getelementptr i8, i8* %v, i32 4096
         store i8 %a, i8* %tmp2
         ret i8 %a
 }
diff --git a/test/CodeGen/Thumb2/thumb2-strh.ll b/test/CodeGen/Thumb2/thumb2-strh.ll
index cbe73d5cf057..dfd1c90d9623 100644
--- a/test/CodeGen/Thumb2/thumb2-strh.ll
+++ b/test/CodeGen/Thumb2/thumb2-strh.ll
@@ -10,7 +10,7 @@ define i16 @f1(i16 %a, i16* %v) {
 define i16 @f2(i16 %a, i16* %v) {
 ; CHECK-LABEL: f2:
 ; CHECK: strh.w r0, [r1, #4092]
-        %tmp2 = getelementptr i16* %v, i32 2046
+        %tmp2 = getelementptr i16, i16* %v, i32 2046
         store i16 %a, i16* %tmp2
         ret i16 %a
 }
@@ -18,7 +18,7 @@ define i16 @f2(i16 %a, i16* %v) {
 define i16 @f2a(i16 %a, i16* %v) {
 ; CHECK-LABEL: f2a:
 ; CHECK: strh r0, [r1, #-128]
-        %tmp2 = getelementptr i16* %v, i32 -64
+        %tmp2 = getelementptr i16, i16* %v, i32 -64
         store i16 %a, i16* %tmp2
         ret i16 %a
 }
@@ -27,7 +27,7 @@ define i16 @f3(i16 %a, i16* %v) {
 ; CHECK-LABEL: f3:
 ; CHECK: mov.w r2, #4096
 ; CHECK: strh r0, [r1, r2]
-        %tmp2 = getelementptr i16* %v, i32 2048
+        %tmp2 = getelementptr i16, i16* %v, i32 2048
         store i16 %a, i16* %tmp2
         ret i16 %a
 }
diff --git a/test/CodeGen/Thumb2/thumb2-tbb.ll b/test/CodeGen/Thumb2/thumb2-tbb.ll
index d57638bbb4f6..758f792695fd 100644
--- a/test/CodeGen/Thumb2/thumb2-tbb.ll
+++ b/test/CodeGen/Thumb2/thumb2-tbb.ll
@@ -11,43 +11,43 @@ entry:
 
     switch i32 %n.u, label %bb12 [i32 1, label %bb i32 2, label %bb6 i32 4, label %bb7 i32 5, label %bb8 i32 6, label %bb10 i32 7, label %bb1 i32 8, label %bb3 i32 9, label %bb4 i32 10, label %bb9 i32 11, label %bb2 i32 12, label %bb5 i32 13, label %bb11 ]
 bb:
-    tail call void(...)* @foo1()
+    tail call void(...) @foo1()
     ret void
 bb1:
-    tail call void(...)* @foo2()
+    tail call void(...) @foo2()
     ret void
 bb2:
-    tail call void(...)* @foo6()
+    tail call void(...) @foo6()
     ret void
 bb3:
-    tail call void(...)* @foo3()
+    tail call void(...) @foo3()
     ret void
 bb4:
-    tail call void(...)* @foo4()
+    tail call void(...) @foo4()
     ret void
 bb5:
-    tail call void(...)* @foo5()
+    tail call void(...) @foo5()
     ret void
 bb6:
-    tail call void(...)* @foo1()
+    tail call void(...) @foo1()
     ret void
 bb7:
-    tail call void(...)* @foo2()
+    tail call void(...) @foo2()
     ret void
 bb8:
-    tail call void(...)* @foo6()
+    tail call void(...) @foo6()
     ret void
 bb9:
-    tail call void(...)* @foo3()
+    tail call void(...) @foo3()
     ret void
 bb10:
-    tail call void(...)* @foo4()
+    tail call void(...) @foo4()
     ret void
 bb11:
-    tail call void(...)* @foo5()
+    tail call void(...) @foo5()
     ret void
 bb12:
-    tail call void(...)* @foo6()
+    tail call void(...) @foo6()
     ret void
 }
 
diff --git a/test/CodeGen/Thumb2/thumb2-tbh.ll b/test/CodeGen/Thumb2/thumb2-tbh.ll
index bf1c7c613ab5..a5a5ed0c8da2 100644
--- a/test/CodeGen/Thumb2/thumb2-tbh.ll
+++ b/test/CodeGen/Thumb2/thumb2-tbh.ll
@@ -45,7 +45,7 @@ bb33.i:		; preds = %bb42.i
 	unreachable
 
 bb34.i:		; preds = %bb42.i
-	%3 = load i32* @_C_nextcmd, align 4		; <i32> [#uses=1]
+	%3 = load i32, i32* @_C_nextcmd, align 4		; <i32> [#uses=1]
 	%4 = add i32 %3, 1		; <i32> [#uses=1]
 	store i32 %4, i32* @_C_nextcmd, align 4
 	%5 = call  noalias i8* @calloc(i32 22, i32 1) nounwind		; <i8*> [#uses=0]
@@ -60,7 +60,7 @@ bb37.i:		; preds = %bb42.i
 	unreachable
 
 bb39.i:		; preds = %bb42.i
-	call  void @Z_fatal(i8* getelementptr ([28 x i8]* @.str31, i32 0, i32 0)) nounwind
+	call  void @Z_fatal(i8* getelementptr ([28 x i8], [28 x i8]* @.str31, i32 0, i32 0)) nounwind
 	unreachable
 
 bb40.i:		; preds = %bb42.i, %bb5.i, %bb1.i2
diff --git a/test/CodeGen/Thumb2/tls1.ll b/test/CodeGen/Thumb2/tls1.ll
index 40973562d2b9..6acf27d1ad5d 100644
--- a/test/CodeGen/Thumb2/tls1.ll
+++ b/test/CodeGen/Thumb2/tls1.ll
@@ -10,7 +10,7 @@
 
 define i32 @f() {
 entry:
-	%tmp1 = load i32* @i		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* @i		; <i32> [#uses=1]
 	ret i32 %tmp1
 }
 
diff --git a/test/CodeGen/Thumb2/tls2.ll b/test/CodeGen/Thumb2/tls2.ll
index e6bed2f65a49..8f05ceab19fc 100644
--- a/test/CodeGen/Thumb2/tls2.ll
+++ b/test/CodeGen/Thumb2/tls2.ll
@@ -12,7 +12,7 @@ entry:
 
 ; CHECK-PIC-LABEL: f:
 ; CHECK-PIC: bl __tls_get_addr(PLT)
-	%tmp1 = load i32* @i		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* @i		; <i32> [#uses=1]
 	ret i32 %tmp1
 }
 
diff --git a/test/CodeGen/Thumb2/tpsoft.ll b/test/CodeGen/Thumb2/tpsoft.ll
index 6ab8bf01761b..de358d98d49c 100644
--- a/test/CodeGen/Thumb2/tpsoft.ll
+++ b/test/CodeGen/Thumb2/tpsoft.ll
@@ -16,7 +16,7 @@
 
 define arm_aapcs_vfpcc i32 @main() nounwind {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   switch i32 %0, label %bb2 [
     i32 12, label %bb
     i32 13, label %bb1
@@ -32,13 +32,13 @@ bb:                                               ; preds = %entry
 ; ELFOBJ:        Section {
 ; ELFOBJ:          Name: .text
 ; ELFOBJ-LE:          SectionData (
-;;;                  BL __aeabi_read_tp is ---------+
-;;;                                                 V
-; ELFOBJ-LE-NEXT:     0000: 2DE90048 0E487844 0168FFF7 FEFF4058
+;;;                  BL __aeabi_read_tp is ---+
+;;;                                           V
+; ELFOBJ-LE-NEXT:     0000: 80B50E48 78440168 FFF7FEFF 40580D28
 ; ELFOBJ-BE:          SectionData (
-;;;                  BL __aeabi_read_tp is ---------+
-;;;                                                 V
-; ELFOBJ-BE-NEXT:     0000: E92D4800 480E4478 6801F7FF FFFE5840
+;;;                  BL __aeabi_read_tp is ---+
+;;;                                           V
+; ELFOBJ-BE-NEXT:     0000: B580480E 44786801 F7FFFFFE 5840280D
 
 
 bb1:                                              ; preds = %entry
diff --git a/test/CodeGen/Thumb2/v8_IT_2.ll b/test/CodeGen/Thumb2/v8_IT_2.ll
index 170b4135b536..9a3f263c5259 100644
--- a/test/CodeGen/Thumb2/v8_IT_2.ll
+++ b/test/CodeGen/Thumb2/v8_IT_2.ll
@@ -16,9 +16,9 @@ entry:
 	br label %tailrecurse
 
 tailrecurse:		; preds = %bb, %entry
-	%tmp6 = load %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=1]
-	%tmp9 = load %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=2]
-	%tmp12 = load %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=1]
+	%tmp6 = load %struct.quad_struct*, %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=1]
+	%tmp9 = load %struct.quad_struct*, %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=2]
+	%tmp12 = load %struct.quad_struct*, %struct.quad_struct** null		; <%struct.quad_struct*> [#uses=1]
 	%tmp14 = icmp eq %struct.quad_struct* null, null		; <i1> [#uses=1]
 	%tmp17 = icmp eq %struct.quad_struct* %tmp6, null		; <i1> [#uses=1]
 	%tmp23 = icmp eq %struct.quad_struct* %tmp9, null		; <i1> [#uses=1]
diff --git a/test/CodeGen/Thumb2/v8_IT_3.ll b/test/CodeGen/Thumb2/v8_IT_3.ll
index a028deebc8e8..3ccee5fbb8ca 100644
--- a/test/CodeGen/Thumb2/v8_IT_3.ll
+++ b/test/CodeGen/Thumb2/v8_IT_3.ll
@@ -21,17 +21,17 @@ entry:
   %block_count = alloca i32, align 4
   %index_cache = alloca i32, align 4
   store i32 0, i32* %index_cache, align 4
-  %tmp = load i32* @G, align 4
+  %tmp = load i32, i32* @G, align 4
   %tmp1 = call i32 @bar(i32 0, i32 0, i32 %tmp) nounwind
   switch i32 %tmp1, label %bb8 [
-    i32 0, label %bb
+    i32 1, label %bb
     i32 536870913, label %bb4
     i32 536870914, label %bb6
   ]
 
 bb:
-  %tmp2 = load i32* @G, align 4
-  %tmp4 = icmp eq i32 %tmp2, 0
+  %tmp2 = load i32, i32* @G, align 4
+  %tmp4 = icmp eq i32 %tmp2, 1
   br i1 %tmp4, label %bb1, label %bb8
 
 bb1:
@@ -41,14 +41,14 @@ bb1:
 ; CHECK-NEXT: it	eq
 ; CHECK-NEXT: cmpeq
 ; CHECK: %bb1
-  %tmp5 = load i32* %block_size, align 4
-  %tmp6 = load i32* %block_count, align 4
+  %tmp5 = load i32, i32* %block_size, align 4
+  %tmp6 = load i32, i32* %block_count, align 4
   %tmp7 = call %struct.FF* @Get() nounwind
   store %struct.FF* %tmp7, %struct.FF** @FuncPtr, align 4
   %tmp10 = zext i32 %tmp6 to i64
   %tmp11 = zext i32 %tmp5 to i64
   %tmp12 = mul nsw i64 %tmp10, %tmp11
-  %tmp13 = call i32 @foo(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0), i64 %tmp12, i32 %tmp5) nounwind
+  %tmp13 = call i32 @foo(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), i64 %tmp12, i32 %tmp5) nounwind
   br label %bb8
 
 bb4:
diff --git a/test/CodeGen/Thumb2/v8_IT_5.ll b/test/CodeGen/Thumb2/v8_IT_5.ll
index 2da75ad21436..78b80d7dcdef 100644
--- a/test/CodeGen/Thumb2/v8_IT_5.ll
+++ b/test/CodeGen/Thumb2/v8_IT_5.ll
@@ -3,8 +3,7 @@
 ; CHECK: it	ne
 ; CHECK-NEXT: cmpne
 ; CHECK-NEXT: bne [[JUMPTARGET:.LBB[0-9]+_[0-9]+]]
-; CHECK: cmp
-; CHECK-NEXT: beq
+; CHECK: cbz
 ; CHECK-NEXT: %if.else163
 ; CHECK-NEXT: mov.w
 ; CHECK-NEXT: b
diff --git a/test/CodeGen/WinEH/cppeh-alloca-sink.ll b/test/CodeGen/WinEH/cppeh-alloca-sink.ll
new file mode 100644
index 000000000000..d50237fa78a7
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-alloca-sink.ll
@@ -0,0 +1,180 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test describes two difficult cases in sinking allocas into child frames.
+; We don't currently do this optimization, but we'll need to tweak these tests
+; when we do.
+
+; This test is based on the following code:
+;
+; // In this case we can sink the alloca from the parent into the catch because
+; // the lifetime is limited to the catch.
+; extern "C" void may_throw();
+; extern "C" void sink_alloca_to_catch() {
+;   try {
+;     may_throw();
+;   } catch (int) {
+;     volatile int only_used_in_catch = 42;
+;   }
+; }
+;
+; // In this case we cannot. The variable should live as long as the parent
+; // frame lives.
+; extern "C" void use_catch_var(int *);
+; extern "C" void dont_sink_alloca_to_catch(int n) {
+;   int live_in_out_catch = 0;
+;   while (n > 0) {
+;     try {
+;       may_throw();
+;     } catch (int) {
+;       use_catch_var(&live_in_out_catch);
+;     }
+;     n--;
+;   }
+; }
+
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+declare void @may_throw() #1
+declare i32 @__CxxFrameHandler3(...)
+declare i32 @llvm.eh.typeid.for(i8*) #2
+declare void @llvm.eh.begincatch(i8* nocapture, i8* nocapture) #3
+declare void @llvm.eh.endcatch() #3
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+%eh.CatchHandlerType = type { i32, i8* }
+
+$"\01??_R0H@8" = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+@llvm.eh.handlertype.H.0 = private unnamed_addr constant %eh.CatchHandlerType { i32 0, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*) }, section "llvm.metadata"
+
+; Function Attrs: uwtable
+define void @sink_alloca_to_catch() #0 {
+entry:
+  %0 = alloca i32
+  %only_used_in_catch = alloca i32, align 4
+  invoke void @may_throw()
+          to label %try.cont unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.H.0
+  %2 = extractvalue { i8*, i32 } %1, 1
+  %3 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*)) #3
+  %matches = icmp eq i32 %2, %3
+  br i1 %matches, label %catch, label %eh.resume
+
+catch:                                            ; preds = %lpad
+  %4 = extractvalue { i8*, i32 } %1, 0
+  call void @llvm.eh.begincatch(i8* %4, i8* null) #3
+  store volatile i32 42, i32* %only_used_in_catch, align 4
+  tail call void @llvm.eh.endcatch() #3
+  br label %try.cont
+
+try.cont:                                         ; preds = %entry, %catch
+  ret void
+
+eh.resume:                                        ; preds = %lpad
+  resume { i8*, i32 } %1
+}
+
+; CHECK-LABEL: define void @sink_alloca_to_catch()
+; CHECK: call void (...) @llvm.frameescape(i32* %only_used_in_catch)
+
+declare void @use_catch_var(i32*) #1
+
+; Function Attrs: uwtable
+define void @dont_sink_alloca_to_catch(i32 %n) #0 {
+entry:
+  %0 = alloca i32
+  %n.addr = alloca i32, align 4
+  %live_in_out_catch = alloca i32, align 4
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  store i32 %n, i32* %n.addr, align 4
+  br label %while.cond
+
+while.cond:                                       ; preds = %try.cont, %entry
+  %1 = load i32, i32* %n.addr, align 4
+  %cmp = icmp sgt i32 %1, 0
+  br i1 %cmp, label %while.body, label %while.end
+
+while.body:                                       ; preds = %while.cond
+  invoke void @may_throw()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %while.body
+  br label %try.cont
+
+lpad:                                             ; preds = %while.body
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*)
+  %3 = extractvalue { i8*, i32 } %2, 0
+  store i8* %3, i8** %exn.slot
+  %4 = extractvalue { i8*, i32 } %2, 1
+  store i32 %4, i32* %ehselector.slot
+  br label %catch.dispatch
+
+catch.dispatch:                                   ; preds = %lpad
+  %sel = load i32, i32* %ehselector.slot
+  %5 = call i32 @llvm.eh.typeid.for(i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*)) #3
+  %matches = icmp eq i32 %sel, %5
+  br i1 %matches, label %catch, label %eh.resume
+
+catch:                                            ; preds = %catch.dispatch
+  %exn = load i8*, i8** %exn.slot
+  call void @llvm.eh.begincatch(i8* %exn, i8* null) #3
+  invoke void @use_catch_var(i32* %live_in_out_catch)
+          to label %invoke.cont2 unwind label %lpad1
+
+invoke.cont2:                                     ; preds = %catch
+  call void @llvm.eh.endcatch() #3
+  br label %try.cont
+
+try.cont:                                         ; preds = %invoke.cont2, %invoke.cont
+  %6 = load i32, i32* %0
+  %7 = load i32, i32* %n.addr, align 4
+  %dec = add nsw i32 %7, -1
+  store i32 %dec, i32* %n.addr, align 4
+  br label %while.cond
+
+lpad1:                                            ; preds = %catch
+  %8 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %9 = extractvalue { i8*, i32 } %8, 0
+  store i8* %9, i8** %exn.slot
+  %10 = extractvalue { i8*, i32 } %8, 1
+  store i32 %10, i32* %ehselector.slot
+  call void @llvm.eh.endcatch() #3
+  br label %eh.resume
+
+while.end:                                        ; preds = %while.cond
+  ret void
+
+eh.resume:                                        ; preds = %lpad1, %catch.dispatch
+  %exn3 = load i8*, i8** %exn.slot
+  %sel4 = load i32, i32* %ehselector.slot
+  %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn3, 0
+  %lpad.val5 = insertvalue { i8*, i32 } %lpad.val, i32 %sel4, 1
+  resume { i8*, i32 } %lpad.val5
+}
+
+; CHECK-LABEL: define void @dont_sink_alloca_to_catch(i32 %n)
+; CHECK: call void (...) @llvm.frameescape(i32* %live_in_out_catch)
+
+; CHECK-LABEL: define internal i8* @sink_alloca_to_catch.catch(i8*, i8*)
+; CHECK: %only_used_in_catch.i8 = call i8* @llvm.framerecover({{.*}}, i32 0)
+; CHECK: %only_used_in_catch = bitcast
+
+; CHECK-LABEL: define internal i8* @dont_sink_alloca_to_catch.catch(i8*, i8*)
+; CHECK: %live_in_out_catch.i8 = call i8* @llvm.framerecover({{.*}}, i32 0)
+; CHECK: %live_in_out_catch = bitcast
+
+
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind }
diff --git a/test/CodeGen/WinEH/cppeh-catch-all.ll b/test/CodeGen/WinEH/cppeh-catch-all.ll
new file mode 100644
index 000000000000..a6c94d400797
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-catch-all.ll
@@ -0,0 +1,97 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test is based on the following code:
+;
+; void test()
+; {
+;   try {
+;     may_throw();
+;   } catch (...) {
+;     handle_exception();
+;   }
+; }
+;
+; Parts of the IR have been hand-edited to simplify the test case.
+; The full IR will be restored when Windows C++ EH support is complete.
+
+; ModuleID = 'catch-all.cpp'
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+; The function entry in this case remains unchanged.
+; CHECK: define void @_Z4testv()
+; CHECK: entry:
+; CHECK:   invoke void @_Z9may_throwv()
+; CHECK:           to label %invoke.cont unwind label %[[LPAD_LABEL:lpad[0-9]*]]
+
+; Function Attrs: uwtable
+define void @_Z4testv() #0 {
+entry:
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  invoke void @_Z9may_throwv()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %entry
+  br label %try.cont
+
+; CHECK: [[LPAD_LABEL]]:{{[ ]+}}; preds = %entry
+; CHECK:   landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK-NEXT:           catch i8* null
+; CHECK-NEXT:   [[RECOVER:\%.+]] = call i8* (...) @llvm.eh.actions(i32 1, i8* null, i32 -1, i8* (i8*, i8*)* @_Z4testv.catch)
+; CHECK-NEXT:   indirectbr i8* [[RECOVER]], [label %try.cont]
+
+lpad:                                             ; preds = %entry
+  %tmp = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* null
+  %tmp1 = extractvalue { i8*, i32 } %tmp, 0
+  store i8* %tmp1, i8** %exn.slot
+  %tmp2 = extractvalue { i8*, i32 } %tmp, 1
+  store i32 %tmp2, i32* %ehselector.slot
+  br label %catch
+
+; CHECK-NOT: catch:
+
+catch:                                            ; preds = %lpad
+  %exn = load i8*, i8** %exn.slot
+  call void @llvm.eh.begincatch(i8* %exn, i8* null) #2
+  call void @_Z16handle_exceptionv()
+  br label %invoke.cont2
+
+; CHECK-NOT: invoke.cont2:
+
+invoke.cont2:                                     ; preds = %catch
+  call void @llvm.eh.endcatch()
+  br label %try.cont
+
+try.cont:                                         ; preds = %invoke.cont2, %invoke.cont
+  ret void
+
+; CHECK: }
+}
+
+; CHECK: define internal i8* @_Z4testv.catch(i8*, i8*)
+; CHECK: entry:
+; CHECK:   call void @_Z16handle_exceptionv()
+; CHECK:   ret i8* blockaddress(@_Z4testv, %try.cont)
+; CHECK: }
+
+declare void @_Z9may_throwv() #1
+
+declare i32 @__CxxFrameHandler3(...)
+
+declare void @llvm.eh.begincatch(i8*, i8*)
+
+declare void @_Z16handle_exceptionv() #1
+
+declare void @llvm.eh.endcatch()
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { noinline noreturn nounwind }
+attributes #3 = { nounwind }
+attributes #4 = { noreturn nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 226027)"}
diff --git a/test/CodeGen/WinEH/cppeh-catch-and-throw.ll b/test/CodeGen/WinEH/cppeh-catch-and-throw.ll
new file mode 100644
index 000000000000..c60a339f6ba2
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-catch-and-throw.ll
@@ -0,0 +1,143 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test is based on the following code:
+;
+; class Obj {
+; public:
+;   ~Obj();
+; };
+;
+; void test(void)
+; {
+;   try {
+;     Obj o;
+;     throw 1;
+;   } catch (...) {
+;     throw;
+;   }
+; }
+
+; ModuleID = 'cppeh-catch-and-throw.cpp'
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+%eh.CatchableType = type { i32, i32, i32, i32, i32, i32, i32 }
+%eh.CatchableTypeArray.1 = type { i32, [1 x i32] }
+%eh.ThrowInfo = type { i32, i32, i32, i32 }
+%class.Obj = type { i8 }
+
+$"\01??_R0H@8" = comdat any
+
+$"_CT??_R0H@84" = comdat any
+
+$_CTA1H = comdat any
+
+$_TI1H = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+@__ImageBase = external constant i8
+@"_CT??_R0H@84" = linkonce_odr unnamed_addr constant %eh.CatchableType { i32 1, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32), i32 0, i32 -1, i32 0, i32 4, i32 0 }, section ".xdata", comdat
+@_CTA1H = linkonce_odr unnamed_addr constant %eh.CatchableTypeArray.1 { i32 1, [1 x i32] [i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableType* @"_CT??_R0H@84" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32)] }, section ".xdata", comdat
+@_TI1H = linkonce_odr unnamed_addr constant %eh.ThrowInfo { i32 0, i32 0, i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableTypeArray.1* @_CTA1H to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32) }, section ".xdata", comdat
+
+; This is just a minimal check to verify that main was handled by WinEHPrepare.
+; CHECK: define void @"\01?test@@YAXXZ"()
+; CHECK: entry:
+; CHECK:   call void (...) @llvm.frameescape
+; CHECK:   invoke void @_CxxThrowException
+; CHECK: }
+
+; Function Attrs: uwtable
+define void @"\01?test@@YAXXZ"() #0 {
+entry:
+  %o = alloca %class.Obj, align 1
+  %tmp = alloca i32, align 4
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  store i32 1, i32* %tmp
+  %0 = bitcast i32* %tmp to i8*
+  invoke void @_CxxThrowException(i8* %0, %eh.ThrowInfo* @_TI1H) #3
+          to label %unreachable unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* null
+  %2 = extractvalue { i8*, i32 } %1, 0
+  store i8* %2, i8** %exn.slot
+  %3 = extractvalue { i8*, i32 } %1, 1
+  store i32 %3, i32* %ehselector.slot
+  call void @"\01??1Obj@@QEAA@XZ"(%class.Obj* %o) #2
+  br label %catch
+
+catch:                                            ; preds = %lpad
+  %exn = load i8*, i8** %exn.slot
+  call void @llvm.eh.begincatch(i8* %exn, i8* null) #2
+  invoke void @_CxxThrowException(i8* null, %eh.ThrowInfo* null) #3
+          to label %unreachable unwind label %lpad1
+
+lpad1:                                            ; preds = %catch
+  %4 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %5 = extractvalue { i8*, i32 } %4, 0
+  store i8* %5, i8** %exn.slot
+  %6 = extractvalue { i8*, i32 } %4, 1
+  store i32 %6, i32* %ehselector.slot
+  call void @llvm.eh.endcatch() #2
+  br label %eh.resume
+
+try.cont:                                         ; No predecessors!
+  ret void
+
+eh.resume:                                        ; preds = %lpad1
+  %exn2 = load i8*, i8** %exn.slot
+  %sel = load i32, i32* %ehselector.slot
+  %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn2, 0
+  %lpad.val3 = insertvalue { i8*, i32 } %lpad.val, i32 %sel, 1
+  resume { i8*, i32 } %lpad.val3
+
+unreachable:                                      ; preds = %catch, %entry
+  unreachable
+}
+
+; Verify that we inserted a stub invoke into the outlined cleanup handler.
+;
+; CHECK-LABEL: define internal void @"\01?test@@YAXXZ.cleanup"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   call i8* @llvm.framerecover
+; CHECK:   call void @"\01??1Obj@@QEAA@XZ"
+; CHECK:   invoke void @llvm.donothing()
+; CHECK:           to label %[[SPLIT_LABEL:.+]] unwind label %[[LPAD_LABEL:.+]]
+;
+; CHECK: [[SPLIT_LABEL]]
+;
+; CHECK: [[LPAD_LABEL]]
+; CHECK:   landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK:           cleanup
+; CHECK:   unreachable
+; CHECK: }
+
+declare void @_CxxThrowException(i8*, %eh.ThrowInfo*)
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind
+declare void @"\01??1Obj@@QEAA@XZ"(%class.Obj*) #1
+
+; Function Attrs: nounwind
+declare void @llvm.eh.begincatch(i8* nocapture, i8* nocapture) #2
+
+; Function Attrs: nounwind
+declare void @llvm.eh.endcatch() #2
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind }
+attributes #3 = { noreturn }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 (trunk 235214) (llvm/trunk 235213)"}
diff --git a/test/CodeGen/WinEH/cppeh-catch-scalar.ll b/test/CodeGen/WinEH/cppeh-catch-scalar.ll
new file mode 100644
index 000000000000..4faef82a75fc
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-catch-scalar.ll
@@ -0,0 +1,126 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test is based on the following code:
+;
+; void test()
+; {
+;   try {
+;     may_throw();
+;   } catch (int i) {
+;     handle_int(i);
+;   }
+; }
+;
+; Parts of the IR have been hand-edited to simplify the test case.
+; The full IR will be restored when Windows C++ EH support is complete.
+
+;ModuleID = 'cppeh-catch-scalar.cpp'
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+@_ZTIi = external constant i8*
+
+; The function entry will be rewritten like this.
+; CHECK: define void @_Z4testv()
+; CHECK: entry:
+; CHECK:   [[I_PTR:\%.+]] = alloca i32, align 4
+; CHECK:   call void (...) @llvm.frameescape(i32* [[I_PTR]])
+; CHECK:   invoke void @_Z9may_throwv()
+; CHECK:           to label %invoke.cont unwind label %[[LPAD_LABEL:lpad[0-9]*]]
+
+; Function Attrs: uwtable
+define void @_Z4testv() #0 {
+entry:
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  %i = alloca i32, align 4
+  invoke void @_Z9may_throwv()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %entry
+  br label %try.cont
+
+; CHECK: [[LPAD_LABEL]]:{{[ ]+}}; preds = %entry
+; CHECK:   landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK-NEXT:           catch i8* bitcast (i8** @_ZTIi to i8*)
+; CHECK-NEXT:   [[RECOVER:\%.+]] = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (i8** @_ZTIi to i8*), i32 0, i8* (i8*, i8*)* @_Z4testv.catch)
+; CHECK-NEXT:   indirectbr i8* [[RECOVER]], [label %try.cont]
+
+lpad:                                             ; preds = %entry
+  %tmp = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %tmp1 = extractvalue { i8*, i32 } %tmp, 0
+  store i8* %tmp1, i8** %exn.slot
+  %tmp2 = extractvalue { i8*, i32 } %tmp, 1
+  store i32 %tmp2, i32* %ehselector.slot
+  br label %catch.dispatch
+
+; CHECK-NOT: catch-dispatch:
+
+catch.dispatch:                                   ; preds = %lpad
+  %sel = load i32, i32* %ehselector.slot
+  %tmp3 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) #3
+  %matches = icmp eq i32 %sel, %tmp3
+  br i1 %matches, label %catch, label %eh.resume
+
+; CHECK-NOT: catch:
+
+catch:                                            ; preds = %catch.dispatch
+  %exn11 = load i8*, i8** %exn.slot
+  %i.i8 = bitcast i32* %i to i8*
+  call void @llvm.eh.begincatch(i8* %exn11, i8* %i.i8) #3
+  %tmp7 = load i32, i32* %i, align 4
+  call void @_Z10handle_inti(i32 %tmp7)
+  br label %invoke.cont2
+
+; CHECK-NOT: invoke.cont2:
+
+invoke.cont2:                                     ; preds = %catch
+  call void @llvm.eh.endcatch() #3
+  br label %try.cont
+
+try.cont:                                         ; preds = %invoke.cont2, %invoke.cont
+  ret void
+
+; CHECK-NOT: eh.resume:
+
+eh.resume:                                        ; preds = %catch.dispatch
+  %exn3 = load i8*, i8** %exn.slot
+  %sel4 = load i32, i32* %ehselector.slot
+  %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn3, 0
+  %lpad.val5 = insertvalue { i8*, i32 } %lpad.val, i32 %sel4, 1
+  resume { i8*, i32 } %lpad.val5
+
+; CHECK: }
+}
+
+; CHECK: define internal i8* @_Z4testv.catch(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_I:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @_Z4testv to i8*), i8* %1, i32 0)
+; CHECK:   [[I_PTR1:\%.+]] = bitcast i8* [[RECOVER_I]] to i32*
+; CHECK:   [[TMP:\%.+]] = load i32, i32* [[I_PTR1]], align 4
+; CHECK:   call void @_Z10handle_inti(i32 [[TMP]])
+; CHECK:   ret i8* blockaddress(@_Z4testv, %try.cont)
+; CHECK: }
+
+declare void @_Z9may_throwv() #1
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #2
+
+declare void @llvm.eh.begincatch(i8*, i8*)
+
+declare void @llvm.eh.endcatch()
+
+declare void @_Z10handle_inti(i32) #1
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 227474) (llvm/trunk 227508)"}
diff --git a/test/CodeGen/WinEH/cppeh-catch-unwind.ll b/test/CodeGen/WinEH/cppeh-catch-unwind.ll
new file mode 100644
index 000000000000..0fd735be57a1
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-catch-unwind.ll
@@ -0,0 +1,240 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test was generated from the following source:
+;
+; void test() {
+;   try {
+;     SomeClass obj;
+;     may_throw();
+;     try {
+;       may_throw();
+;     } catch (int) {
+;       handle_exception();
+;     }
+;   } catch (int) {
+;     handle_exception();
+;   }
+; }
+;
+; The code above was compiled with the -O2 option.
+
+; ModuleID = 'catch-unwind.cpp'
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+%class.SomeClass = type { i8 }
+
+$"\01??_R0H@8" = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+
+
+; CHECK-LABEL: define void @"\01?test@@YAXXZ"() #0 {
+; CHECK: entry:
+; CHECK:   [[OBJ_PTR:\%.+]] = alloca %class.SomeClass
+; CHECK:   [[TMP0:\%.+]] = alloca i32, align 4
+; CHECK:   [[TMP1:\%.+]] = alloca i32, align 4
+; CHECK:   call void (...) @llvm.frameescape(i32* [[TMP1]], %class.SomeClass* [[OBJ_PTR]], i32* [[TMP0]])
+; CHECK:   %call = invoke %class.SomeClass* @"\01??0SomeClass@@QEAA@XZ"(%class.SomeClass* %obj)
+; CHECK:           to label %invoke.cont unwind label %[[LPAD_LABEL:lpad[0-9]*]]
+
+; Function Attrs: uwtable
+define void @"\01?test@@YAXXZ"() #0 {
+entry:
+  %obj = alloca %class.SomeClass, align 1
+  %0 = alloca i32, align 4
+  %1 = alloca i32, align 4
+  %call = invoke %class.SomeClass* @"\01??0SomeClass@@QEAA@XZ"(%class.SomeClass* %obj)
+          to label %invoke.cont unwind label %lpad
+
+; CHECK: invoke.cont:
+; CHECK:   invoke void @"\01?may_throw@@YAXXZ"()
+; CHECK:           to label %invoke.cont2 unwind label %[[LPAD1_LABEL:lpad[0-9]*]]
+
+invoke.cont:                                      ; preds = %entry
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %invoke.cont2 unwind label %lpad1
+
+; CHECK: invoke.cont2:
+; CHECK:   invoke void @"\01?may_throw@@YAXXZ"()
+; CHECK:           to label %try.cont unwind label %[[LPAD3_LABEL:lpad[0-9]*]]
+
+invoke.cont2:                                     ; preds = %invoke.cont
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %try.cont unwind label %lpad3
+
+; CHECK: [[LPAD_LABEL]]:{{[ ]+}}; preds = %entry
+; CHECK:   [[LPAD_VAL:\%.+]] = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK-NEXT:           catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+; CHECK-NEXT:   [[RECOVER:\%.+]] = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*), i32 0, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch")
+; CHECK-NEXT:   indirectbr i8* [[RECOVER]], [label %try.cont15]
+
+lpad:                                             ; preds = %entry
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+  %3 = extractvalue { i8*, i32 } %2, 0
+  %4 = extractvalue { i8*, i32 } %2, 1
+  br label %catch.dispatch7
+
+; CHECK: [[LPAD1_LABEL]]:{{[ ]+}}; preds = %invoke.cont
+; CHECK:   [[LPAD1_VAL:\%.+]] = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK-NEXT:           cleanup
+; CHECK-NEXT:           catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+; CHECK-NEXT:   [[RECOVER1:\%.+]] = call i8* (...) @llvm.eh.actions(i32 0, void (i8*, i8*)* @"\01?test@@YAXXZ.cleanup", i32 1, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*), i32 0, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch")
+; CHECK-NEXT:   indirectbr i8* [[RECOVER1]], [label %try.cont15]
+
+lpad1:                                            ; preds = %invoke.cont
+  %5 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+          catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+  %6 = extractvalue { i8*, i32 } %5, 0
+  %7 = extractvalue { i8*, i32 } %5, 1
+  br label %ehcleanup
+
+; CHECK: [[LPAD3_LABEL]]:{{[ ]+}}; preds = %invoke.cont2
+; CHECK:   [[LPAD3_VAL:\%.+]] = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK-NEXT:           cleanup
+; CHECK-NEXT:           catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+; CHECK-NEXT:   [[RECOVER3:\%.+]] = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*), i32 2, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch.1", i32 0, void (i8*, i8*)* @"\01?test@@YAXXZ.cleanup")
+; CHECK-NEXT:   indirectbr i8* [[RECOVER3]], [label %try.cont, label %try.cont15]
+
+lpad3:                                            ; preds = %invoke.cont2
+  %8 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+          catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+  %9 = extractvalue { i8*, i32 } %8, 0
+  %10 = extractvalue { i8*, i32 } %8, 1
+  %11 = call i32 @llvm.eh.typeid.for(i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)) #3
+  %matches = icmp eq i32 %10, %11
+  br i1 %matches, label %catch, label %ehcleanup
+
+; CHECK-NOT: catch:
+catch:                                            ; preds = %lpad3
+  %12 = bitcast i32* %0 to i8*
+  call void @llvm.eh.begincatch(i8* %9, i8* %12) #3
+  invoke void @"\01?handle_exception@@YAXXZ"()
+          to label %invoke.cont6 unwind label %lpad5
+
+; CHECK-NOT: invoke.cont6:
+invoke.cont6:                                     ; preds = %catch
+  call void @llvm.eh.endcatch() #3
+  br label %try.cont
+
+try.cont:                                         ; preds = %invoke.cont2, %invoke.cont6
+  call void @"\01??1SomeClass@@QEAA@XZ"(%class.SomeClass* %obj) #3
+  br label %try.cont15
+
+; CHECK-NOT: lpad5:
+lpad5:                                            ; preds = %catch
+  %13 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+          catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+  %14 = extractvalue { i8*, i32 } %13, 0
+  %15 = extractvalue { i8*, i32 } %13, 1
+  call void @llvm.eh.endcatch() #3
+  br label %ehcleanup
+
+; CHECK-NOT: ehcleanup
+ehcleanup:                                        ; preds = %lpad5, %lpad3, %lpad1
+  %exn.slot.0 = phi i8* [ %14, %lpad5 ], [ %9, %lpad3 ], [ %6, %lpad1 ]
+  %ehselector.slot.0 = phi i32 [ %15, %lpad5 ], [ %10, %lpad3 ], [ %7, %lpad1 ]
+  call void @"\01??1SomeClass@@QEAA@XZ"(%class.SomeClass* %obj) #3
+  br label %catch.dispatch7
+
+; CHECK-NOT: catch.dispatch7:
+catch.dispatch7:                                  ; preds = %ehcleanup, %lpad
+  %exn.slot.1 = phi i8* [ %exn.slot.0, %ehcleanup ], [ %3, %lpad ]
+  %ehselector.slot.1 = phi i32 [ %ehselector.slot.0, %ehcleanup ], [ %4, %lpad ]
+  %16 = call i32 @llvm.eh.typeid.for(i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)) #3
+  %matches9 = icmp eq i32 %ehselector.slot.1, %16
+  br i1 %matches9, label %catch10, label %eh.resume
+
+; CHECK-NOT: catch10:
+catch10:                                          ; preds = %catch.dispatch7
+  %17 = bitcast i32* %1 to i8*
+  call void @llvm.eh.begincatch(i8* %exn.slot.1, i8* %17) #3
+  call void @"\01?handle_exception@@YAXXZ"()
+  br label %invoke.cont13
+
+; CHECK-NOT: invoke.cont13:
+invoke.cont13:                                    ; preds = %catch10
+  call void @llvm.eh.endcatch() #3
+  br label %try.cont15
+
+try.cont15:                                       ; preds = %invoke.cont13, %try.cont
+  ret void
+
+; CHECK-NOT: eh.resume
+eh.resume:                                        ; preds = %catch.dispatch7
+  %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn.slot.1, 0
+  %lpad.val18 = insertvalue { i8*, i32 } %lpad.val, i32 %ehselector.slot.1, 1
+  resume { i8*, i32 } %lpad.val18
+
+; CHECK: }
+}
+
+; CHECK-LABEL: define internal i8* @"\01?test@@YAXXZ.catch"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_TMP1:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 0)
+; CHECK:   [[TMP1_PTR:\%.+]] = bitcast i8* [[RECOVER_TMP1]] to i32*
+; CHECK:   call void @"\01?handle_exception@@YAXXZ"()
+; CHECK:   ret i8* blockaddress(@"\01?test@@YAXXZ", %try.cont15)
+; CHECK: }
+
+; CHECK-LABEL: define internal void @"\01?test@@YAXXZ.cleanup"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_OBJ:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 1)
+; CHECK:   [[OBJ_PTR:\%.+]] = bitcast i8* %obj.i8 to %class.SomeClass*
+; CHECK:   call void @"\01??1SomeClass@@QEAA@XZ"(%class.SomeClass* [[OBJ_PTR]])
+; CHECK:   ret void
+; CHECK: }
+
+; CHECK-LABEL: define internal i8* @"\01?test@@YAXXZ.catch.1"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_TMP0:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 2)
+; CHECK:   [[TMP0_PTR:\%.+]] = bitcast i8* [[RECOVER_TMP0]] to i32*
+; CHECK:   invoke void @"\01?handle_exception@@YAXXZ"()
+; CHECK:           to label %invoke.cont6 unwind label %[[LPAD5_LABEL:lpad[0-9]+]]
+;
+; CHECK: invoke.cont6:                                     ; preds = %entry
+; CHECK:   ret i8* blockaddress(@"\01?test@@YAXXZ", %try.cont)
+;
+; CHECK: [[LPAD5_LABEL]]:{{[ ]+}}; preds = %entry
+; CHECK:   [[LPAD5_VAL:\%.+]] = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK:           cleanup
+; CHECK:           catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+; CHECK: }
+
+declare %class.SomeClass* @"\01??0SomeClass@@QEAA@XZ"(%class.SomeClass* returned) #1
+
+declare i32 @__CxxFrameHandler3(...)
+
+declare void @"\01?may_throw@@YAXXZ"() #1
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #2
+
+; Function Attrs: nounwind
+declare void @llvm.eh.begincatch(i8* nocapture, i8* nocapture) #3
+
+declare void @"\01?handle_exception@@YAXXZ"() #1
+
+; Function Attrs: nounwind
+declare void @llvm.eh.endcatch() #3
+
+; Function Attrs: nounwind
+declare void @"\01??1SomeClass@@QEAA@XZ"(%class.SomeClass*) #4
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind }
+attributes #4 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 (trunk 232069) (llvm/trunk 232070)"}
diff --git a/test/CodeGen/WinEH/cppeh-cleanup-invoke.ll b/test/CodeGen/WinEH/cppeh-cleanup-invoke.ll
new file mode 100644
index 000000000000..5a570431510f
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-cleanup-invoke.ll
@@ -0,0 +1,91 @@
+; RUN: opt -winehprepare -S < %s | FileCheck %s
+
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+; Modified based on this code:
+; struct HasDtor {
+;   ~HasDtor();
+; };
+; extern "C" void may_throw();
+; int main() {
+;   try {
+;     HasDtor o;
+;     may_throw();
+;   } catch (int) {
+;   }
+; }
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+%eh.CatchHandlerType = type { i32, i8* }
+%struct.HasDtor = type { i8 }
+
+$"\01??_R0H@8" = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+@llvm.eh.handlertype.H.0 = private unnamed_addr constant %eh.CatchHandlerType { i32 0, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*) }, section "llvm.metadata"
+
+define i32 @main() {
+entry:
+  %o = alloca %struct.HasDtor, align 1
+  invoke void @may_throw()
+          to label %invoke.cont2 unwind label %lpad1
+
+invoke.cont2:                                     ; preds = %invoke.cont
+  call void @"\01??1HasDtor@@QEAA@XZ"(%struct.HasDtor* %o)
+  br label %try.cont
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.H.0
+  %1 = extractvalue { i8*, i32 } %0, 0
+  %2 = extractvalue { i8*, i32 } %0, 1
+  br label %catch.dispatch
+
+lpad1:                                            ; preds = %invoke.cont
+  %3 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.H.0
+  %4 = extractvalue { i8*, i32 } %3, 0
+  %5 = extractvalue { i8*, i32 } %3, 1
+  invoke void @"\01??1HasDtor@@QEAA@XZ"(%struct.HasDtor* %o)
+	  to label %catch.dispatch unwind label %lpad
+
+catch.dispatch:                                   ; preds = %lpad1, %lpad
+  %exn.slot.0 = phi i8* [ %4, %lpad1 ], [ %1, %lpad ]
+  %ehselector.slot.0 = phi i32 [ %5, %lpad1 ], [ %2, %lpad ]
+  %6 = call i32 @llvm.eh.typeid.for(i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*))
+  %matches = icmp eq i32 %ehselector.slot.0, %6
+  br i1 %matches, label %catch, label %eh.resume
+
+catch:                                            ; preds = %catch.dispatch
+  call void @llvm.eh.begincatch(i8* %exn.slot.0, i8* null)
+  call void @llvm.eh.endcatch()
+  br label %try.cont
+
+try.cont:                                         ; preds = %catch, %invoke.cont2
+  ret i32 0
+
+eh.resume:                                        ; preds = %catch.dispatch
+  %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn.slot.0, 0
+  %lpad.val5 = insertvalue { i8*, i32 } %lpad.val, i32 %ehselector.slot.0, 1
+  resume { i8*, i32 } %lpad.val5
+}
+
+; CHECK-LABEL: define i32 @main()
+; CHECK: @llvm.eh.actions(i32 0, void (i8*, i8*)* @main.cleanup, i32 1, i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*), i32 -1, i8* (i8*, i8*)* @main.catch)
+
+; CHECK-LABEL: define internal void @main.cleanup(i8*, i8*)
+; CHECK: call void @"\01??1HasDtor@@QEAA@XZ"(%struct.HasDtor* %{{.*}})
+; CHECK: ret void
+
+declare void @may_throw()
+
+declare i32 @__CxxFrameHandler3(...)
+
+declare void @"\01??1HasDtor@@QEAA@XZ"(%struct.HasDtor*)
+
+declare i32 @llvm.eh.typeid.for(i8*)
+declare void @llvm.eh.begincatch(i8* nocapture, i8* nocapture)
+declare void @llvm.eh.endcatch()
diff --git a/test/CodeGen/WinEH/cppeh-demote-liveout.ll b/test/CodeGen/WinEH/cppeh-demote-liveout.ll
new file mode 100644
index 000000000000..48d9b39ca64a
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-demote-liveout.ll
@@ -0,0 +1,72 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S < %s | FileCheck %s
+
+; Notionally based on this C++ source:
+; int liveout_catch(int p) {
+;   int val = p + 1;
+;   try {
+;     might_throw();
+;   } catch (int) {
+;     val++;
+;   }
+;   return val;
+; }
+
+declare void @llvm.eh.begincatch(i8*, i8*)
+declare void @llvm.eh.endcatch()
+declare void @might_throw()
+declare i32 @__CxxFrameHandler3(...)
+declare i32 @llvm.eh.typeid.for(i8*)
+
+@typeinfo.int = external global i32
+
+define i32 @liveout_catch(i32 %p) {
+entry:
+  %val.entry = add i32 %p, 1
+  invoke void @might_throw()
+      to label %ret unwind label %lpad
+
+lpad:
+  %ehvals = landingpad { i8*, i32 } personality i32 (...)* @__CxxFrameHandler3
+      cleanup
+      catch i32* @typeinfo.int
+  %ehptr = extractvalue { i8*, i32 } %ehvals, 0
+  %sel = extractvalue { i8*, i32 } %ehvals, 1
+  %int_sel = call i32 @llvm.eh.typeid.for(i8* bitcast (i32* @typeinfo.int to i8*))
+  %match = icmp eq i32 %sel, %int_sel
+  br i1 %match, label %catchit, label %resume
+
+catchit:
+  call void @llvm.eh.begincatch(i8* %ehptr, i8* null)
+  %val.lpad = add i32 %val.entry, 1
+  call void @llvm.eh.endcatch()
+  br label %ret
+
+ret:
+  %rv = phi i32 [%val.entry, %entry], [%val.lpad, %catchit]
+  ret i32 %rv
+
+resume:
+  resume {i8*, i32} %ehvals
+}
+
+; CHECK-LABEL: define i32 @liveout_catch(i32 %p)
+; CHECK: %val.entry = add i32 %p, 1
+; CHECK-NEXT: store i32 %val.entry, i32* %val.entry.reg2mem
+; CHECK: invoke void @might_throw()
+;
+; CHECK: landingpad
+; CHECK: indirectbr i8* {{.*}}, [label %catchit.split]
+;
+; CHECK: catchit.split:
+; CHECK: load i32, i32* %val.lpad.reg2mem
+; CHECK: br label %ret
+;
+; CHECK: ret:
+; CHECK: %rv = phi i32 [ {{.*}}, %entry ], [ {{.*}}, %catchit.split ]
+; CHECK: ret i32
+
+; CHECK-LABEL: define internal i8* @liveout_catch.catch(i8*, i8*)
+; CHECK: %[[val:[^ ]*]] = load i32, i32*
+; CHECK-NEXT: %[[val_lpad:[^ ]*]] = add i32 %[[val]], 1
+; CHECK-NEXT: store i32 %[[val_lpad]], i32*
+; CHECK: ret i8* blockaddress(@liveout_catch, %catchit.split)
diff --git a/test/CodeGen/WinEH/cppeh-frame-vars.ll b/test/CodeGen/WinEH/cppeh-frame-vars.ll
new file mode 100644
index 000000000000..eeda4319a6e6
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-frame-vars.ll
@@ -0,0 +1,272 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test is based on the following code:
+;
+; struct SomeData {
+;   int a;
+;   int b;
+; };
+;
+; void may_throw();
+; void does_not_throw(int i);
+; void dump(int *, int, SomeData&);
+;
+; void test() {
+;   int NumExceptions = 0;
+;   int ExceptionVal[10];
+;   SomeData Data = { 0, 0 };
+;
+;   for (int i = 0; i < 10; ++i) {
+;     try {
+;       may_throw();
+;       Data.a += i;
+;     }
+;     catch (int e) {
+;       ExceptionVal[NumExceptions] = e;
+;       ++NumExceptions;
+;       if (e == i)
+;         Data.b += e;
+;       else
+;         Data.a += e;
+;     }
+;     does_not_throw(NumExceptions);
+;   }
+;   dump(ExceptionVal, NumExceptions, Data);
+; }
+
+; ModuleID = 'cppeh-frame-vars.cpp'
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+%struct.SomeData = type { i32, i32 }
+
+$"\01??_R0H@8" = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+
+; The function entry should be rewritten like this.
+; CHECK: define void @"\01?test@@YAXXZ"()
+; CHECK: entry:
+; CHECK:   [[NUMEXCEPTIONS_PTR:\%.+]] = alloca i32, align 4
+; CHECK:   [[EXCEPTIONVAL_PTR:\%.+]] = alloca [10 x i32], align 16
+; CHECK:   [[DATA_PTR:\%.+]] = alloca %struct.SomeData, align 4
+; CHECK:   [[I_PTR:\%.+]] = alloca i32, align 4
+; CHECK:   [[E_PTR:\%.+]] = alloca i32, align 4
+; CHECK:   store i32 0, i32* [[NUMEXCEPTIONS_PTR]], align 4
+; CHECK:   [[TMP:\%.+]] = bitcast %struct.SomeData* [[DATA_PTR]] to i8*
+; CHECK:   call void @llvm.memset(i8* [[TMP]], i8 0, i64 8, i32 4, i1 false)
+; CHECK:   store i32 0, i32* [[I_PTR]], align 4
+; CHECK:   call void (...) @llvm.frameescape(i32* [[E_PTR]], i32* [[NUMEXCEPTIONS_PTR]], [10 x i32]* [[EXCEPTIONVAL_PTR]], i32* [[I_PTR]], %struct.SomeData* [[DATA_PTR]])
+; CHECK:   br label %for.cond
+
+; Function Attrs: uwtable
+define void @"\01?test@@YAXXZ"() #0 {
+entry:
+  %NumExceptions = alloca i32, align 4
+  %ExceptionVal = alloca [10 x i32], align 16
+  %Data = alloca %struct.SomeData, align 4
+  %i = alloca i32, align 4
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  %e = alloca i32, align 4
+  store i32 0, i32* %NumExceptions, align 4
+  %tmp = bitcast %struct.SomeData* %Data to i8*
+  call void @llvm.memset(i8* %tmp, i8 0, i64 8, i32 4, i1 false)
+  store i32 0, i32* %i, align 4
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %entry
+  %tmp1 = load i32, i32* %i, align 4
+  %cmp = icmp slt i32 %tmp1, 10
+  br i1 %cmp, label %for.body, label %for.end
+
+; CHECK: for.body:
+; CHECK:   invoke void @"\01?may_throw@@YAXXZ"()
+; CHECK:           to label %invoke.cont unwind label %[[LPAD_LABEL:lpad[0-9]*]]
+
+for.body:                                         ; preds = %for.cond
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %for.body
+  %tmp2 = load i32, i32* %i, align 4
+  %a = getelementptr inbounds %struct.SomeData, %struct.SomeData* %Data, i32 0, i32 0
+  %tmp3 = load i32, i32* %a, align 4
+  %add = add nsw i32 %tmp3, %tmp2
+  store i32 %add, i32* %a, align 4
+  br label %try.cont
+
+; CHECK: [[LPAD_LABEL]]:{{[ ]+}}; preds = %for.body
+; CHECK:   landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK-NEXT:           catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+; CHECK-NEXT:   [[RECOVER:\%.+]] = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*), i32 0, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch")
+; CHECK-NEXT:   indirectbr i8* [[RECOVER]], [label %try.cont]
+
+lpad:                                             ; preds = %for.body
+  %tmp4 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+  %tmp5 = extractvalue { i8*, i32 } %tmp4, 0
+  store i8* %tmp5, i8** %exn.slot
+  %tmp6 = extractvalue { i8*, i32 } %tmp4, 1
+  store i32 %tmp6, i32* %ehselector.slot
+  br label %catch.dispatch
+
+; CHECK-NOT: catch.dispatch:
+
+catch.dispatch:                                   ; preds = %lpad
+  %sel = load i32, i32* %ehselector.slot
+  %tmp7 = call i32 @llvm.eh.typeid.for(i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)) #1
+  %matches = icmp eq i32 %sel, %tmp7
+  br i1 %matches, label %catch, label %eh.resume
+
+; CHECK-NOT: catch:
+
+catch:                                            ; preds = %catch.dispatch
+  %exn = load i8*, i8** %exn.slot
+  %e.i8 = bitcast i32* %e to i8*
+  call void @llvm.eh.begincatch(i8* %exn, i8* %e.i8) #1
+  %tmp11 = load i32, i32* %e, align 4
+  %tmp12 = load i32, i32* %NumExceptions, align 4
+  %idxprom = sext i32 %tmp12 to i64
+  %arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* %ExceptionVal, i32 0, i64 %idxprom
+  store i32 %tmp11, i32* %arrayidx, align 4
+  %tmp13 = load i32, i32* %NumExceptions, align 4
+  %inc = add nsw i32 %tmp13, 1
+  store i32 %inc, i32* %NumExceptions, align 4
+  %tmp14 = load i32, i32* %e, align 4
+  %tmp15 = load i32, i32* %i, align 4
+  %cmp1 = icmp eq i32 %tmp14, %tmp15
+  br i1 %cmp1, label %if.then, label %if.else
+
+; CHECK-NOT: if.then:
+
+if.then:                                          ; preds = %catch
+  %tmp16 = load i32, i32* %e, align 4
+  %b = getelementptr inbounds %struct.SomeData, %struct.SomeData* %Data, i32 0, i32 1
+  %tmp17 = load i32, i32* %b, align 4
+  %add2 = add nsw i32 %tmp17, %tmp16
+  store i32 %add2, i32* %b, align 4
+  br label %if.end
+
+; CHECK-NOT: if.else:
+
+if.else:                                          ; preds = %catch
+  %tmp18 = load i32, i32* %e, align 4
+  %a3 = getelementptr inbounds %struct.SomeData, %struct.SomeData* %Data, i32 0, i32 0
+  %tmp19 = load i32, i32* %a3, align 4
+  %add4 = add nsw i32 %tmp19, %tmp18
+  store i32 %add4, i32* %a3, align 4
+  br label %if.end
+
+; CHECK-NOT: if.end:
+
+if.end:                                           ; preds = %if.else, %if.then
+  call void @llvm.eh.endcatch() #1
+  br label %try.cont
+
+try.cont:                                         ; preds = %if.end, %invoke.cont
+  %tmp20 = load i32, i32* %NumExceptions, align 4
+  call void @"\01?does_not_throw@@YAXH@Z"(i32 %tmp20)
+  br label %for.inc
+
+for.inc:                                          ; preds = %try.cont
+  %tmp21 = load i32, i32* %i, align 4
+  %inc5 = add nsw i32 %tmp21, 1
+  store i32 %inc5, i32* %i, align 4
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  %tmp22 = load i32, i32* %NumExceptions, align 4
+  %arraydecay = getelementptr inbounds [10 x i32], [10 x i32]* %ExceptionVal, i32 0, i32 0
+  call void @"\01?dump@@YAXPEAHHAEAUSomeData@@@Z"(i32* %arraydecay, i32 %tmp22, %struct.SomeData* dereferenceable(8) %Data)
+  ret void
+
+; CHECK-NOT: eh.resume:
+
+eh.resume:                                        ; preds = %catch.dispatch
+  %exn6 = load i8*, i8** %exn.slot
+  %sel7 = load i32, i32* %ehselector.slot
+  %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn6, 0
+  %lpad.val8 = insertvalue { i8*, i32 } %lpad.val, i32 %sel7, 1
+  resume { i8*, i32 } %lpad.val8
+
+; CHECK: }
+}
+
+; The following catch handler should be outlined.
+; CHECK-LABEL: define internal i8* @"\01?test@@YAXXZ.catch"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_E:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 0)
+; CHECK:   [[E_PTR1:\%.+]] = bitcast i8* [[RECOVER_E]] to i32*
+; CHECK:   [[RECOVER_NUMEXCEPTIONS:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 1)
+; CHECK:   [[NUMEXCEPTIONS_PTR1:\%.+]] = bitcast i8* [[RECOVER_NUMEXCEPTIONS]] to i32*
+; CHECK:   [[RECOVER_EXCEPTIONVAL:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 2)
+; CHECK:   [[EXCEPTIONVAL_PTR1:\%.+]] = bitcast i8* [[RECOVER_EXCEPTIONVAL]] to [10 x i32]*
+; CHECK:   [[RECOVER_I:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 3)
+; CHECK:   [[I_PTR1:\%.+]] = bitcast i8* [[RECOVER_I]] to i32*
+; CHECK:   [[RECOVER_DATA:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 4)
+; CHECK:   [[DATA_PTR1:\%.+]] = bitcast i8* [[RECOVER_DATA]] to %struct.SomeData*
+; CHECK:   [[TMP:\%.+]] = load i32, i32* [[E_PTR1]], align 4
+; CHECK:   [[TMP1:\%.+]] = load i32, i32* [[NUMEXCEPTIONS_PTR]], align 4
+; CHECK:   [[IDXPROM:\%.+]] = sext i32 [[TMP1]] to i64
+; CHECK:   [[ARRAYIDX:\%.+]] = getelementptr inbounds [10 x i32], [10 x i32]* [[EXCEPTIONVAL_PTR1]], i32 0, i64 [[IDXPROM]]
+; CHECK:   store i32 [[TMP]], i32* [[ARRAYIDX]], align 4
+; CHECK:   [[TMP2:\%.+]] = load i32, i32* [[NUMEXCEPTIONS_PTR1]], align 4
+; CHECK:   [[INC:\%.+]] = add nsw i32 [[TMP2]], 1
+; CHECK:   store i32 [[INC]], i32* [[NUMEXCEPTIONS_PTR]], align 4
+; CHECK:   [[TMP3:\%.+]] = load i32, i32* [[E_PTR1]], align 4
+; CHECK:   [[TMP4:\%.+]] = load i32, i32* [[I_PTR1]], align 4
+; CHECK:   [[CMP:\%.+]] = icmp eq i32 [[TMP3]], [[TMP4]]
+; CHECK:   br i1 [[CMP]], label %if.then, label %if.else
+;
+; CHECK: if.then:                                          ; preds = %entry
+; CHECK:   [[TMP5:\%.+]] = load i32, i32* [[E_PTR1]], align 4
+; CHECK:   [[B_PTR:\%.+]] = getelementptr inbounds %struct.SomeData, %struct.SomeData* [[DATA_PTR1]], i32 0, i32 1
+; CHECK:   [[TMP6:\%.+]] = load i32, i32* [[B_PTR]], align 4
+; CHECK:   %add2 = add nsw i32 [[TMP6]], [[TMP5]]
+; CHECK:   store i32 [[ADD:\%.+]], i32* [[B_PTR]], align 4
+; CHECK:   br label %if.end
+;
+; CHECK: if.else:                                          ; preds = %entry
+; CHECK:   [[TMP7:\%.+]] = load i32, i32* %e, align 4
+; CHECK:   [[A3:\%.+]] = getelementptr inbounds %struct.SomeData, %struct.SomeData* %Data, i32 0, i32 0
+; CHECK:   [[TMP8:\%.+]] = load i32, i32* %a3, align 4
+; CHECK:   [[ADD1:\%.+]] = add nsw i32 [[TMP8]], [[TMP7]]
+; CHECK:   store i32 [[ADD1]], i32* [[A3]], align 4
+; CHECK:   br label %if.end
+;
+; CHECK: if.end:                                           ; preds = %if.else, %if.then
+; CHECK:   ret i8* blockaddress(@"\01?test@@YAXXZ", %try.cont)
+; CHECK: }
+
+
+; Function Attrs: nounwind
+declare void @llvm.memset(i8* nocapture, i8, i64, i32, i1) #1
+
+declare void @"\01?may_throw@@YAXXZ"() #2
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #3
+
+declare void @llvm.eh.begincatch(i8*, i8*)
+
+declare void @llvm.eh.endcatch()
+
+declare void @"\01?does_not_throw@@YAXH@Z"(i32) #2
+
+declare void @"\01?dump@@YAXPEAHHAEAUSomeData@@@Z"(i32*, i32, %struct.SomeData* dereferenceable(8)) #2
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind }
+attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { nounwind readnone }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 (trunk 228868)"}
diff --git a/test/CodeGen/WinEH/cppeh-inalloca.ll b/test/CodeGen/WinEH/cppeh-inalloca.ll
new file mode 100644
index 000000000000..13471b8661a3
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-inalloca.ll
@@ -0,0 +1,194 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test is built from the following code:
+; struct A {
+;   A(int a);
+;   A(const A &o);
+;   ~A();
+;   int a;
+; };
+;
+; void may_throw();
+;
+; int test(A a) {
+;   try {
+;     may_throw();
+;   }
+;   catch (int e) {
+;     return a.a + e;
+;   }
+;   return 0;
+; }
+;
+; The test was built for a 32-bit Windows target and then the reference to
+; the inalloca instruction was manually sunk into the landingpad.
+
+; ModuleID = 'cppeh-inalloca.cpp'
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+%struct.A = type { i32 }
+
+$"\01??_R0H@8" = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+
+; The function entry should be rewritten like this.
+; CHECK: define i32 @"\01?test@@YAHUA@@@Z"(<{ %struct.A }>* inalloca)
+; CHECK: entry:
+; CHECK:   [[TMP_REGMEM:\%.+]] = alloca <{ %struct.A }>*
+; CHECK:   store <{ %struct.A }>* %0, <{ %struct.A }>** [[TMP_REGMEM]]
+; CHECK:   [[RETVAL:\%.+]] = alloca i32, align 4
+; CHECK:   [[E_PTR:\%.+]] = alloca i32, align 4
+; CHECK:   [[CLEANUP_SLOT:\%.+]] = alloca i32
+; CHECK:   call void (...) @llvm.frameescape(i32* %e, <{ %struct.A }>** [[TMP_REGMEM]], i32* [[RETVAL]], i32* [[CLEANUP_SLOT]])
+; CHECK:   invoke void @"\01?may_throw@@YAXXZ"()
+; CHECK:           to label %invoke.cont unwind label %[[LPAD_LABEL:lpad[0-9]*]]
+
+define i32 @"\01?test@@YAHUA@@@Z"(<{ %struct.A }>* inalloca) #0 {
+entry:
+  %retval = alloca i32, align 4
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  %e = alloca i32, align 4
+  %cleanup.dest.slot = alloca i32
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %entry
+  br label %try.cont
+
+; CHECK: [[LPAD_LABEL]]:{{[ ]+}}; preds = %entry
+; CHECK:   landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK-NEXT:           cleanup
+; CHECK-NEXT:           catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+; CHECK-NEXT:   [[RECOVER:\%recover.*]] = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*), i32 0, i8* (i8*, i8*)* @"\01?test@@YAHUA@@@Z.catch", i32 0, void (i8*, i8*)* @"\01?test@@YAHUA@@@Z.cleanup")
+; CHECK-NEXT:   indirectbr i8* [[RECOVER]], [label %cleanup]
+
+lpad:                                             ; preds = %entry
+  %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+          catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+  %2 = extractvalue { i8*, i32 } %1, 0
+  store i8* %2, i8** %exn.slot
+  %3 = extractvalue { i8*, i32 } %1, 1
+  store i32 %3, i32* %ehselector.slot
+  br label %catch.dispatch
+
+; CHECK-NOT: catch.dispatch:
+
+catch.dispatch:                                   ; preds = %lpad
+  %sel = load i32, i32* %ehselector.slot
+  %4 = call i32 @llvm.eh.typeid.for(i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)) #3
+  %matches = icmp eq i32 %sel, %4
+  br i1 %matches, label %catch, label %ehcleanup
+
+; CHECK-NOT: catch:
+
+catch:                                            ; preds = %catch.dispatch
+  %exn = load i8*, i8** %exn.slot
+  %e.i8 = bitcast i32* %e to i8*
+  call void @llvm.eh.begincatch(i8* %exn, i8* %e.i8) #3
+  %a = getelementptr inbounds <{ %struct.A }>, <{ %struct.A }>* %0, i32 0, i32 0
+  %a1 = getelementptr inbounds %struct.A, %struct.A* %a, i32 0, i32 0
+  %tmp8 = load i32, i32* %a1, align 4
+  %tmp9 = load i32, i32* %e, align 4
+  %add = add nsw i32 %tmp8, %tmp9
+  store i32 %add, i32* %retval
+  store i32 1, i32* %cleanup.dest.slot
+  call void @llvm.eh.endcatch() #3
+  br label %cleanup
+
+try.cont:                                         ; preds = %invoke.cont
+  store i32 0, i32* %retval
+  store i32 1, i32* %cleanup.dest.slot
+  br label %cleanup
+
+; The cleanup block should be re-written like this.
+; CHECK: cleanup:{{[ ]+}}; preds = %[[LPAD_LABEL]], %try.cont
+; CHECK:   %a2 = getelementptr inbounds <{ %struct.A }>, <{ %struct.A }>* %0, i32 0, i32 0
+; CHECK:   call x86_thiscallcc void @"\01??1A@@QAE@XZ"(%struct.A* %a2)
+; CHECK:   [[TMP1:\%.+]] = load i32, i32* [[RETVAL]]
+; CHECK:   ret i32 [[TMP1]]
+
+cleanup:                                          ; preds = %try.cont, %catch
+  %a2 = getelementptr inbounds <{ %struct.A }>, <{ %struct.A }>* %0, i32 0, i32 0
+  call x86_thiscallcc void @"\01??1A@@QAE@XZ"(%struct.A* %a2) #3
+  %tmp10 = load i32, i32* %retval
+  ret i32 %tmp10
+
+; CHECK-NOT: ehcleanup:
+
+ehcleanup:                                        ; preds = %catch.dispatch
+  %a3 = getelementptr inbounds <{ %struct.A }>, <{ %struct.A }>* %0, i32 0, i32 0
+  call x86_thiscallcc void @"\01??1A@@QAE@XZ"(%struct.A* %a3) #3
+  br label %eh.resume
+
+; CHECK-NOT: eh.resume:
+
+eh.resume:                                        ; preds = %ehcleanup
+  %exn2 = load i8*, i8** %exn.slot
+  %sel3 = load i32, i32* %ehselector.slot
+  %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn2, 0
+  %lpad.val4 = insertvalue { i8*, i32 } %lpad.val, i32 %sel3, 1
+  resume { i8*, i32 } %lpad.val4
+
+; CHECK: }
+}
+
+; The following catch handler should be outlined.
+; CHECK: define internal i8* @"\01?test@@YAHUA@@@Z.catch"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_E:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (i32 (<{ %struct.A }>*)* @"\01?test@@YAHUA@@@Z" to i8*), i8* %1, i32 0)
+; CHECK:   [[E_PTR:\%.+]] = bitcast i8* [[RECOVER_E]] to i32*
+; CHECK:   [[RECOVER_EH_TEMP:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (i32 (<{ %struct.A }>*)* @"\01?test@@YAHUA@@@Z" to i8*), i8* %1, i32 1)
+; CHECK:   [[EH_TEMP:\%.+]] = bitcast i8* [[RECOVER_EH_TEMP]] to <{ %struct.A }>**
+; CHECK:   [[RECOVER_RETVAL:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (i32 (<{ %struct.A }>*)* @"\01?test@@YAHUA@@@Z" to i8*), i8* %1, i32 2)
+; CHECK:   [[RETVAL1:\%.+]] = bitcast i8* [[RECOVER_RETVAL]] to i32*
+; CHECK:   [[RECOVER_CLEANUPSLOT:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (i32 (<{ %struct.A }>*)* @"\01?test@@YAHUA@@@Z" to i8*), i8* %1, i32 3)
+; CHECK:   [[CLEANUPSLOT1:\%.+]] = bitcast i8* [[RECOVER_CLEANUPSLOT]] to i32*
+; CHECK:   [[E_I8PTR:\%.+]] = bitcast i32* [[E_PTR]] to i8*
+; CHECK:   [[TMP_RELOAD:\%.+]] = load <{ %struct.A }>*, <{ %struct.A }>** [[EH_TEMP]]
+; CHECK:   [[RECOVER_A:\%.+]] = getelementptr inbounds <{ %struct.A }>, <{ %struct.A }>* [[TMP_RELOAD]], i32 0, i32 0
+; CHECK:   [[A1:\%.+]] = getelementptr inbounds %struct.A, %struct.A* [[RECOVER_A]], i32 0, i32 0
+; CHECK:   [[TMP2:\%.+]] = load i32, i32* [[A1]], align 4
+; CHECK:   [[TMP3:\%.+]] = load i32, i32* [[E_PTR]], align 4
+; CHECK:   [[ADD:\%.+]] = add nsw i32 [[TMP2]], [[TMP3]]
+; CHECK:   store i32 [[ADD]], i32* [[RETVAL1]]
+; CHECK:   store i32 1, i32* [[CLEANUPSLOT1]]
+; CHECK:   ret i8* blockaddress(@"\01?test@@YAHUA@@@Z", %cleanup)
+; CHECK: }
+
+; The following cleanup handler should be outlined.
+; CHECK: define internal void @"\01?test@@YAHUA@@@Z.cleanup"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_EH_TEMP1:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (i32 (<{ %struct.A }>*)* @"\01?test@@YAHUA@@@Z" to i8*), i8* %1, i32 1)
+; CHECK:   [[EH_TEMP1:\%.+]] = bitcast i8* [[RECOVER_EH_TEMP]] to <{ %struct.A }>**
+; CHECK:   [[TMP_RELOAD1:\%.+]] = load <{ %struct.A }>*, <{ %struct.A }>** [[EH_TEMP1]]
+; CHECK:   [[A3:\%.+]] = getelementptr inbounds <{ %struct.A }>, <{ %struct.A }>* [[TMP_RELOAD1]], i32 0, i32 0
+; CHECK:   call x86_thiscallcc void @"\01??1A@@QAE@XZ"(%struct.A* [[A3]])
+; CHECK:   ret void
+; CHECK: }
+
+declare void @"\01?may_throw@@YAXXZ"() #0
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #1
+
+declare void @llvm.eh.begincatch(i8*, i8*)
+
+declare void @llvm.eh.endcatch()
+
+; Function Attrs: nounwind
+declare x86_thiscallcc void @"\01??1A@@QAE@XZ"(%struct.A*) #2
+
+attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 228868)"}
diff --git a/test/CodeGen/WinEH/cppeh-min-unwind.ll b/test/CodeGen/WinEH/cppeh-min-unwind.ll
new file mode 100644
index 000000000000..3fffa47a081b
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-min-unwind.ll
@@ -0,0 +1,99 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test was generated from the following source:
+;
+; class SomeClass {
+; public:
+;   SomeClass();
+;   ~SomeClass();
+; };
+;
+; void test() {
+;   SomeClass obj;
+;   may_throw();
+; }
+
+
+; ModuleID = 'min-unwind.cpp'
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%class.SomeClass = type { [28 x i32] }
+
+; The function entry should be rewritten like this.
+; CHECK: define void @_Z4testv()
+; CHECK: entry:
+; CHECK:   [[OBJ_PTR:\%.+]] = alloca %class.SomeClass, align 4
+; CHECK:   call void @_ZN9SomeClassC1Ev(%class.SomeClass* [[OBJ_PTR]])
+; CHECK:   call void (...) @llvm.frameescape(%class.SomeClass* [[OBJ_PTR]])
+; CHECK:   invoke void @_Z9may_throwv()
+; CHECK:           to label %invoke.cont unwind label %[[LPAD_LABEL:lpad[0-9]*]]
+
+; Function Attrs: uwtable
+define void @_Z4testv() #0 {
+entry:
+  %obj = alloca %class.SomeClass, align 4
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  call void @_ZN9SomeClassC1Ev(%class.SomeClass* %obj)
+  invoke void @_Z9may_throwv()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %entry
+  call void @_ZN9SomeClassD1Ev(%class.SomeClass* %obj)
+  ret void
+
+; CHECK: [[LPAD_LABEL]]:{{[ ]+}}; preds = %entry
+; CHECK:   landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK-NEXT:           cleanup
+; CHECK-NEXT:   [[RECOVER:\%.+]] = call i8* (...) @llvm.eh.actions(i32 0, void (i8*, i8*)* @_Z4testv.cleanup)
+; CHECK-NEXT:   indirectbr i8* [[RECOVER]], []
+
+lpad:                                             ; preds = %entry
+  %tmp = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %tmp1 = extractvalue { i8*, i32 } %tmp, 0
+  store i8* %tmp1, i8** %exn.slot
+  %tmp2 = extractvalue { i8*, i32 } %tmp, 1
+  store i32 %tmp2, i32* %ehselector.slot
+  call void @_ZN9SomeClassD1Ev(%class.SomeClass* %obj)
+  br label %eh.resume
+
+; CHECK-NOT: eh.resume:
+
+eh.resume:                                        ; preds = %lpad
+  %exn = load i8*, i8** %exn.slot
+  %sel = load i32, i32* %ehselector.slot
+  %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn, 0
+  %lpad.val2 = insertvalue { i8*, i32 } %lpad.val, i32 %sel, 1
+  resume { i8*, i32 } %lpad.val2
+
+; CHECK: }
+}
+
+; This cleanup handler should be outlined.
+; CHECK: define internal void @_Z4testv.cleanup(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_OBJ:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @_Z4testv to i8*), i8* %1, i32 0)
+; CHECK:   [[OBJ_PTR1:\%.+]] = bitcast i8* [[RECOVER_OBJ]] to %class.SomeClass*
+; CHECK:   call void @_ZN9SomeClassD1Ev(%class.SomeClass* [[OBJ_PTR1]])
+; CHECK:   ret void
+; CHECK: }
+
+declare void @_ZN9SomeClassC1Ev(%class.SomeClass*) #1
+
+declare void @_Z9may_throwv() #1
+
+declare i32 @__CxxFrameHandler3(...)
+
+declare void @_ZN9SomeClassD1Ev(%class.SomeClass*) #1
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { noinline noreturn nounwind }
+attributes #3 = { noreturn nounwind }
+attributes #4 = { nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 226027)"}
diff --git a/test/CodeGen/WinEH/cppeh-mixed-catch-and-cleanup.ll b/test/CodeGen/WinEH/cppeh-mixed-catch-and-cleanup.ll
new file mode 100644
index 000000000000..52f613276d54
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-mixed-catch-and-cleanup.ll
@@ -0,0 +1,106 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test is based on the following code:
+;
+; void test()
+; {
+;   try {
+;     Obj o;
+;     may_throw();
+;   } catch (...) {
+;   }
+; }
+;
+; The purpose of this test is to verify that we create separate catch and
+; cleanup handlers.  When compiling for the C++ 11 standard, this isn't
+; strictly necessary, since calling the destructor from the catch handler
+; would be logically equivalent to calling it from a cleanup handler.
+; However, if the -std=c++98 option is used, an exception in the cleanup
+; code should terminate the process (the MSVCRT runtime will do that) but
+; if the destructor is called from the catch handler, it wouldn't terminate
+; the process
+
+
+; ModuleID = 'cppeh-mixed-catch-and-cleanup.cpp'
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%class.Obj = type { i8 }
+
+; This just verifies that the function was processed by WinEHPrepare.
+;
+; CHECK-LABEL: define void @"\01?test@@YAXXZ"()
+; CHECK: entry:
+; CHECK:   call void (...) @llvm.frameescape
+; CHECK: }
+
+; Function Attrs: nounwind uwtable
+define void @"\01?test@@YAXXZ"() #0 {
+entry:
+  %o = alloca %class.Obj, align 1
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %entry
+  call void @"\01??1Obj@@QEAA@XZ"(%class.Obj* %o) #3
+  br label %try.cont
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* null
+  %1 = extractvalue { i8*, i32 } %0, 0
+  store i8* %1, i8** %exn.slot
+  %2 = extractvalue { i8*, i32 } %0, 1
+  store i32 %2, i32* %ehselector.slot
+  call void @"\01??1Obj@@QEAA@XZ"(%class.Obj* %o) #3
+  %exn = load i8*, i8** %exn.slot
+  call void @llvm.eh.begincatch(i8* %exn, i8* null) #3
+  call void @llvm.eh.endcatch() #3
+  br label %try.cont
+
+try.cont:                                         ; preds = %catch, %invoke.cont
+  ret void
+}
+
+; Verify that a cleanup handler was created and that it calls ~Obj().
+; CHECK-LABEL: define internal void @"\01?test@@YAXXZ.cleanup"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 0)
+; CHECK:   call void @"\01??1Obj@@QEAA@XZ"
+; CHECK:   ret void
+; CHECK: }
+
+; Verify that a catch handler was created and that it does not call ~Obj().
+; CHECK-LABEL: define internal i8* @"\01?test@@YAXXZ.catch"(i8*, i8*)
+; CHECK: entry:
+; CHECK-NOT:  call void @"\01??1Obj@@QEAA@XZ"
+; CHECK:   ret i8* blockaddress(@"\01?test@@YAXXZ", %try.cont)
+; CHECK: }
+
+
+
+declare void @"\01?may_throw@@YAXXZ"() #1
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind
+declare void @"\01??1Obj@@QEAA@XZ"(%class.Obj*) #2
+
+; Function Attrs: nounwind
+declare void @llvm.eh.begincatch(i8* nocapture, i8* nocapture) #3
+
+; Function Attrs: nounwind
+declare void @llvm.eh.endcatch() #3
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 (trunk 235779) (llvm/trunk 235769)"}
diff --git a/test/CodeGen/WinEH/cppeh-multi-catch.ll b/test/CodeGen/WinEH/cppeh-multi-catch.ll
new file mode 100644
index 000000000000..28340c60ad1e
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-multi-catch.ll
@@ -0,0 +1,226 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test is based on the following code:
+;
+; void test()
+; {
+;   try {
+;     may_throw();
+;   } catch (int i) {
+;     handle_int(i);
+;   } catch (long long ll) {
+;     handle_long_long(ll);
+;   } catch (SomeClass &obj) {
+;     handle_obj(&obj);
+;   } catch (...) {
+;     handle_exception();
+;   }
+; }
+;
+; The catch handlers were edited to insert 'ret void' after the endcatch call.
+
+; ModuleID = 'catch-with-type.cpp'
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+%eh.HandlerMapEntry = type { i32, i32 }
+%rtti.TypeDescriptor3 = type { i8**, i8*, [4 x i8] }
+%rtti.TypeDescriptor15 = type { i8**, i8*, [16 x i8] }
+%class.SomeClass = type { i8 }
+
+$"\01??_R0H@8" = comdat any
+
+$"\01??_R0_J@8" = comdat any
+
+$"\01??_R0?AVSomeClass@@@8" = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+@__ImageBase = external constant i8
+@llvm.eh.handlermapentry.H = private unnamed_addr constant %eh.HandlerMapEntry { i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32) }, section "llvm.metadata"
+@"\01??_R0_J@8" = linkonce_odr global %rtti.TypeDescriptor3 { i8** @"\01??_7type_info@@6B@", i8* null, [4 x i8] c"._J\00" }, comdat
+@llvm.eh.handlermapentry._J = private unnamed_addr constant %eh.HandlerMapEntry { i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor3* @"\01??_R0_J@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32) }, section "llvm.metadata"
+@"\01??_R0?AVSomeClass@@@8" = linkonce_odr global %rtti.TypeDescriptor15 { i8** @"\01??_7type_info@@6B@", i8* null, [16 x i8] c".?AVSomeClass@@\00" }, comdat
+@"llvm.eh.handlermapentry.reference.?AVSomeClass@@" = private unnamed_addr constant %eh.HandlerMapEntry { i32 8, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor15* @"\01??_R0?AVSomeClass@@@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32) }, section "llvm.metadata"
+
+
+; CHECK: define void @"\01?test@@YAXXZ"() #0 {
+; CHECK: entry:
+; CHECK:   [[OBJ_PTR:\%.+]] = alloca %class.SomeClass*, align 8
+; CHECK:   [[LL_PTR:\%.+]] = alloca i64, align 8
+; CHECK:   [[I_PTR:\%.+]] = alloca i32, align 4
+; CHECK:   call void (...) @llvm.frameescape(i32* [[I_PTR]], i64* [[LL_PTR]], %class.SomeClass** [[OBJ_PTR]])
+; CHECK:   invoke void @"\01?may_throw@@YAXXZ"()
+; CHECK:           to label %invoke.cont unwind label %[[LPAD_LABEL:lpad[0-9]*]]
+
+; Function Attrs: uwtable
+define void @"\01?test@@YAXXZ"() #0 {
+entry:
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  %obj = alloca %class.SomeClass*, align 8
+  %ll = alloca i64, align 8
+  %i = alloca i32, align 4
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %entry
+  br label %try.cont
+
+; CHECK: [[LPAD_LABEL]]:{{[ ]+}}; preds = %entry
+; CHECK:   landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK-NEXT:           catch %eh.HandlerMapEntry* @llvm.eh.handlermapentry.H
+; CHECK-NEXT:           catch %eh.HandlerMapEntry* @llvm.eh.handlermapentry._J
+; CHECK-NEXT:           catch %eh.HandlerMapEntry* @"llvm.eh.handlermapentry.reference.?AVSomeClass@@"
+; CHECK-NEXT:           catch i8* null
+; CHECK-NEXT:   [[RECOVER:\%.+]] = call i8* (...) @llvm.eh.actions(
+; CHECK-SAME:	     i32 1, i8* bitcast (%eh.HandlerMapEntry* @llvm.eh.handlermapentry.H to i8*), i32 0, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch",
+; CHECK-SAME:        i32 1, i8* bitcast (%eh.HandlerMapEntry* @llvm.eh.handlermapentry._J to i8*), i32 1, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch.1",
+; CHECK-SAME:        i32 1, i8* bitcast (%eh.HandlerMapEntry* @"llvm.eh.handlermapentry.reference.?AVSomeClass@@" to i8*), i32 2, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch.2",
+; CHECK-SAME:        i32 1, i8* null, i32 -1, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch.3")
+; CHECK-NEXT:   indirectbr i8* [[RECOVER]], [label %ret]
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch %eh.HandlerMapEntry* @llvm.eh.handlermapentry.H
+          catch %eh.HandlerMapEntry* @llvm.eh.handlermapentry._J
+          catch %eh.HandlerMapEntry* @"llvm.eh.handlermapentry.reference.?AVSomeClass@@"
+          catch i8* null
+  %1 = extractvalue { i8*, i32 } %0, 0
+  store i8* %1, i8** %exn.slot
+  %2 = extractvalue { i8*, i32 } %0, 1
+  store i32 %2, i32* %ehselector.slot
+  br label %catch.dispatch
+
+; CHECK-NOT: catch.dispatch:
+catch.dispatch:                                   ; preds = %lpad
+  %sel = load i32, i32* %ehselector.slot
+  %3 = call i32 @llvm.eh.typeid.for(i8* bitcast (%eh.HandlerMapEntry* @llvm.eh.handlermapentry.H to i8*)) #3
+  %matches = icmp eq i32 %sel, %3
+  br i1 %matches, label %catch14, label %catch.fallthrough
+
+ret:
+  ret void
+
+; CHECK-NOT: catch14:
+; CHECK: ret:
+; CHECK-NEXT:   ret void
+catch14:                                          ; preds = %catch.dispatch
+  %exn15 = load i8*, i8** %exn.slot
+  %4 = bitcast i32* %i to i8*
+  call void @llvm.eh.begincatch(i8* %exn15, i8* %4) #3
+  %5 = load i32, i32* %i, align 4
+  call void @"\01?handle_int@@YAXH@Z"(i32 %5)
+  call void @llvm.eh.endcatch() #3
+  br label %ret
+
+try.cont:                                         ; preds = %invoke.cont
+  br label %ret
+
+; CHECK-NOT: catch.fallthrough:
+catch.fallthrough:                                ; preds = %catch.dispatch
+  %6 = call i32 @llvm.eh.typeid.for(i8* bitcast (%eh.HandlerMapEntry* @llvm.eh.handlermapentry._J to i8*)) #3
+  %matches1 = icmp eq i32 %sel, %6
+  br i1 %matches1, label %catch10, label %catch.fallthrough2
+
+; CHECK-NOT: catch10:
+catch10:                                          ; preds = %catch.fallthrough
+  %exn11 = load i8*, i8** %exn.slot
+  %7 = bitcast i64* %ll to i8*
+  call void @llvm.eh.begincatch(i8* %exn11, i8* %7) #3
+  %8 = load i64, i64* %ll, align 8
+  call void @"\01?handle_long_long@@YAX_J@Z"(i64 %8)
+  call void @llvm.eh.endcatch() #3
+  br label %ret
+
+; CHECK-NOT: catch.fallthrough2:
+catch.fallthrough2:                               ; preds = %catch.fallthrough
+  %9 = call i32 @llvm.eh.typeid.for(i8* bitcast (%eh.HandlerMapEntry* @"llvm.eh.handlermapentry.reference.?AVSomeClass@@" to i8*)) #3
+  %matches3 = icmp eq i32 %sel, %9
+  br i1 %matches3, label %catch6, label %catch
+
+; CHECK-NOT: catch6:
+catch6:                                           ; preds = %catch.fallthrough2
+  %exn7 = load i8*, i8** %exn.slot
+  %10 = bitcast %class.SomeClass** %obj to i8*
+  call void @llvm.eh.begincatch(i8* %exn7, i8* %10) #3
+  %11 = load %class.SomeClass*, %class.SomeClass** %obj, align 8
+  call void @"\01?handle_obj@@YAXPEAVSomeClass@@@Z"(%class.SomeClass* %11)
+  call void @llvm.eh.endcatch() #3
+  br label %ret
+
+; CHECK-NOT: catch:
+catch:                                            ; preds = %catch.fallthrough2
+  %exn = load i8*, i8** %exn.slot
+  call void @llvm.eh.begincatch(i8* %exn, i8* null) #3
+  call void @"\01?handle_exception@@YAXXZ"()  call void @llvm.eh.endcatch() #3
+  br label %ret
+; CHECK: }
+}
+
+; CHECK-LABEL: define internal i8* @"\01?test@@YAXXZ.catch"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_I:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 0)
+; CHECK:   [[I_PTR:\%.+]] = bitcast i8* [[RECOVER_I]] to i32*
+; CHECK:   [[TMP1:\%.+]] = load i32, i32* [[I_PTR]], align 4
+; CHECK:   call void @"\01?handle_int@@YAXH@Z"(i32 [[TMP1]])
+; CHECK:   ret i8* blockaddress(@"\01?test@@YAXXZ", %ret)
+; CHECK: }
+
+; CHECK-LABEL: define internal i8* @"\01?test@@YAXXZ.catch.1"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_LL:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 1)
+; CHECK:   [[LL_PTR:\%.+]] = bitcast i8* [[RECOVER_LL]] to i64*
+; CHECK:   [[TMP2:\%.+]] = load i64, i64* [[LL_PTR]], align 8
+; CHECK:   call void @"\01?handle_long_long@@YAX_J@Z"(i64 [[TMP2]])
+; CHECK:   ret i8* blockaddress(@"\01?test@@YAXXZ", %ret)
+; CHECK: }
+
+; CHECK-LABEL: define internal i8* @"\01?test@@YAXXZ.catch.2"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_OBJ:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 2)
+; CHECK:   [[OBJ_PTR:\%.+]] = bitcast i8* [[RECOVER_OBJ]] to %class.SomeClass**
+; CHECK:   [[TMP3:\%.+]] = load %class.SomeClass*, %class.SomeClass** [[OBJ_PTR]], align 8
+; CHECK:   call void @"\01?handle_obj@@YAXPEAVSomeClass@@@Z"(%class.SomeClass* [[TMP3]])
+; CHECK:   ret i8* blockaddress(@"\01?test@@YAXXZ", %ret)
+; CHECK: }
+
+; CHECK-LABEL: define internal i8* @"\01?test@@YAXXZ.catch.3"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   call void @"\01?handle_exception@@YAXXZ"()
+; CHECK:   ret i8* blockaddress(@"\01?test@@YAXXZ", %ret)
+; CHECK: }
+
+
+declare void @"\01?may_throw@@YAXXZ"() #1
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #2
+
+; Function Attrs: nounwind
+declare void @llvm.eh.begincatch(i8* nocapture, i8* nocapture) #3
+
+declare void @"\01?handle_exception@@YAXXZ"() #1
+
+; Function Attrs: nounwind
+declare void @llvm.eh.endcatch() #3
+
+declare void @"\01?handle_obj@@YAXPEAVSomeClass@@@Z"(%class.SomeClass*) #1
+
+declare void @"\01?handle_long_long@@YAX_J@Z"(i64) #1
+
+declare void @"\01?handle_int@@YAXH@Z"(i32) #1
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 (trunk 233155) (llvm/trunk 233153)"}
diff --git a/test/CodeGen/WinEH/cppeh-nested-1.ll b/test/CodeGen/WinEH/cppeh-nested-1.ll
new file mode 100644
index 000000000000..2b13510c5745
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-nested-1.ll
@@ -0,0 +1,194 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test is based on the following code:
+;
+;void test()
+;{
+;  try {
+;    try {
+;       may_throw();
+;    } catch (int i) {
+;      handle_int(i);
+;    }
+;  } catch (float f) {
+;    handle_float(f);
+;  }
+;  done();
+;}
+
+; ModuleID = 'cppeh-nested-1.cpp'
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+
+$"\01??_R0M@8" = comdat any
+
+$"\01??_R0H@8" = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0M@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".M\00" }, comdat
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+
+; CHECK: define void @"\01?test@@YAXXZ"()
+; CHECK: entry:
+; CHECK:   %i = alloca i32, align 4
+; CHECK:   %f = alloca float, align 4
+; CHECK:   call void (...) @llvm.frameescape(float* %f, i32* %i)
+; CHECK:   invoke void @"\01?may_throw@@YAXXZ"()
+; CHECK:           to label %invoke.cont unwind label %[[LPAD_LABEL:lpad[0-9]*]]
+
+; Function Attrs: uwtable
+define void @"\01?test@@YAXXZ"() #0 {
+entry:
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  %i = alloca i32, align 4
+  %f = alloca float, align 4
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %entry
+  br label %try.cont
+
+; CHECK: [[LPAD_LABEL]]:
+; CHECK:   landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK:           catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+; CHECK:           catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*)
+; CHECK:   [[RECOVER:\%.+]] = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*), i32 1, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch.1", i32 1, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*), i32 0, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch")
+; CHECK:   indirectbr i8* [[RECOVER]], [label %try.cont, label %try.cont10]
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+          catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*)
+  %1 = extractvalue { i8*, i32 } %0, 0
+  store i8* %1, i8** %exn.slot
+  %2 = extractvalue { i8*, i32 } %0, 1
+  store i32 %2, i32* %ehselector.slot
+  br label %catch.dispatch
+
+; CHECK-NOT: catch.dispatch:
+catch.dispatch:                                   ; preds = %lpad
+  %sel = load i32, i32* %ehselector.slot
+  %3 = call i32 @llvm.eh.typeid.for(i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)) #3
+  %matches = icmp eq i32 %sel, %3
+  br i1 %matches, label %catch, label %catch.dispatch3
+
+; CHECK-NOT: catch:
+catch:                                            ; preds = %catch.dispatch
+  %exn = load i8*, i8** %exn.slot
+  %4 = bitcast i32* %i to i8*
+  call void @llvm.eh.begincatch(i8* %exn, i8* %4) #3
+  %5 = load i32, i32* %i, align 4
+  invoke void @"\01?handle_int@@YAXH@Z"(i32 %5)
+          to label %invoke.cont2 unwind label %lpad1
+
+; CHECK-NOT: invoke.cont2:
+invoke.cont2:                                     ; preds = %catch
+  call void @llvm.eh.endcatch() #3
+  br label %try.cont
+
+try.cont:                                         ; preds = %invoke.cont2, %invoke.cont
+  br label %try.cont10
+
+; CHECK-NOT: lpad1:
+lpad1:                                            ; preds = %catch
+  %6 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*)
+  %7 = extractvalue { i8*, i32 } %6, 0
+  store i8* %7, i8** %exn.slot
+  %8 = extractvalue { i8*, i32 } %6, 1
+  store i32 %8, i32* %ehselector.slot
+  call void @llvm.eh.endcatch() #3
+  br label %catch.dispatch3
+
+; CHECK-NOT: catch.dispatch3:
+catch.dispatch3:                                  ; preds = %lpad1, %catch.dispatch
+  %sel4 = load i32, i32* %ehselector.slot
+  %9 = call i32 @llvm.eh.typeid.for(i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*)) #3
+  %matches5 = icmp eq i32 %sel4, %9
+  br i1 %matches5, label %catch6, label %eh.resume
+
+; CHECK-NOT: catch6:
+catch6:                                           ; preds = %catch.dispatch3
+  %exn7 = load i8*, i8** %exn.slot
+  %10 = bitcast float* %f to i8*
+  call void @llvm.eh.begincatch(i8* %exn7, i8* %10) #3
+  %11 = load float, float* %f, align 4
+  call void @"\01?handle_float@@YAXM@Z"(float %11)
+  call void @llvm.eh.endcatch() #3
+  br label %try.cont10
+
+try.cont10:                                       ; preds = %catch6, %try.cont
+  call void @"\01?done@@YAXXZ"()
+  ret void
+
+; CHECK-NOT: eh.resume:
+eh.resume:                                        ; %catch.dispatch3
+  %exn11 = load i8*, i8** %exn.slot
+  %sel12 = load i32, i32* %ehselector.slot
+  %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn11, 0
+  %lpad.val13 = insertvalue { i8*, i32 } %lpad.val, i32 %sel12, 1
+  resume { i8*, i32 } %lpad.val13
+; CHECK: }
+}
+
+; CHECK: define internal i8* @"\01?test@@YAXXZ.catch"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_F1:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 0)
+; CHECK:   [[F_PTR1:\%.+]] = bitcast i8* [[RECOVER_F1]] to float*
+; CHECK:   [[TMP2:\%.+]] = load float, float* [[F_PTR1]], align 4
+; CHECK:   call void @"\01?handle_float@@YAXM@Z"(float [[TMP2]])
+; CHECK:   ret i8* blockaddress(@"\01?test@@YAXXZ", %try.cont10)
+; CHECK: }
+
+; CHECK: define internal i8* @"\01?test@@YAXXZ.catch.1"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_I:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 1)
+; CHECK:   [[I_PTR:\%.+]] = bitcast i8* [[RECOVER_I]] to i32*
+; CHECK:   [[TMP1:\%.+]] = load i32, i32* [[I_PTR]], align 4
+; CHECK:   invoke void @"\01?handle_int@@YAXH@Z"(i32 [[TMP1]])
+; CHECK:           to label %invoke.cont2 unwind label %[[LPAD1_LABEL:lpad[0-9]*]]
+;
+; CHECK: invoke.cont2:
+; CHECK:   ret i8* blockaddress(@"\01?test@@YAXXZ", %try.cont)
+;
+; CHECK: [[LPAD1_LABEL]]:{{[ ]+}}; preds = %entry
+; CHECK:   [[LPAD1_VAL:\%.+]] = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK:           catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*)
+; CHECK:   [[RECOVER1:\%.+]] = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*), i32 0, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch")
+; CHECK:   indirectbr i8* [[RECOVER1]], []
+;
+; CHECK: }
+
+
+declare void @"\01?may_throw@@YAXXZ"() #1
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #2
+
+; Function Attrs: nounwind
+declare void @llvm.eh.begincatch(i8* nocapture, i8* nocapture) #3
+
+declare void @"\01?handle_int@@YAXH@Z"(i32) #1
+
+; Function Attrs: nounwind
+declare void @llvm.eh.endcatch() #3
+
+declare void @"\01?handle_float@@YAXM@Z"(float) #1
+
+declare void @"\01?done@@YAXXZ"() #1
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 (trunk 232069) (llvm/trunk 232070)"}
diff --git a/test/CodeGen/WinEH/cppeh-nested-2.ll b/test/CodeGen/WinEH/cppeh-nested-2.ll
new file mode 100644
index 000000000000..f12f3dbed085
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-nested-2.ll
@@ -0,0 +1,324 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test is based on the following code:
+;
+; class Inner {
+; public:
+;   Inner();
+;   ~Inner();
+; };
+; class Outer {
+; public:
+;   Outer();
+;   ~Outer();
+; };
+; void test() {
+;   try {
+;     Outer outer;
+;     try {
+;        Inner inner;
+;        may_throw();
+;     } catch (int i) {
+;       handle_int(i);
+;     }
+;   } catch (float f) {
+;     handle_float(f);
+;   }
+;   done();
+; }
+
+; ModuleID = 'nested-2.cpp'
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%class.Outer = type { i8 }
+%class.Inner = type { i8 }
+
+@_ZTIf = external constant i8*
+@_ZTIi = external constant i8*
+
+; The function entry should be rewritten like this.
+; CHECK: define void @_Z4testv()
+; CHECK: entry:
+; CHECK:   %outer = alloca %class.Outer, align 1
+; CHECK:   %inner = alloca %class.Inner, align 1
+; CHECK:   %i = alloca i32, align 4
+; CHECK:   %f = alloca float, align 4
+; CHECK:   call void (...) @llvm.frameescape(float* %f, i32* %i, %class.Outer* %outer, %class.Inner* %inner)
+; CHECK:   invoke void @_ZN5OuterC1Ev(%class.Outer* %outer)
+; CHECK:           to label %invoke.cont unwind label %[[LPAD_LABEL:lpad[0-9]*]]
+
+; Function Attrs: uwtable
+define void @_Z4testv() #0 {
+entry:
+  %outer = alloca %class.Outer, align 1
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  %inner = alloca %class.Inner, align 1
+  %i = alloca i32, align 4
+  %f = alloca float, align 4
+  invoke void @_ZN5OuterC1Ev(%class.Outer* %outer)
+          to label %invoke.cont unwind label %lpad
+
+; CHECK: invoke.cont:
+; CHECK:   invoke void @_ZN5InnerC1Ev(%class.Inner* %inner)
+; CHECK:           to label %invoke.cont2 unwind label %[[LPAD1_LABEL:lpad[0-9]*]]
+
+invoke.cont:                                      ; preds = %entry
+  invoke void @_ZN5InnerC1Ev(%class.Inner* %inner)
+          to label %invoke.cont2 unwind label %lpad1
+
+; CHECK: invoke.cont2:
+; CHECK:   invoke void @_Z9may_throwv()
+; CHECK:           to label %invoke.cont4 unwind label %[[LPAD3_LABEL:lpad[0-9]*]]
+
+invoke.cont2:                                     ; preds = %invoke.cont
+  invoke void @_Z9may_throwv()
+          to label %invoke.cont4 unwind label %lpad3
+
+; CHECK: invoke.cont4:
+; CHECK:   invoke void @_ZN5InnerD1Ev(%class.Inner* %inner)
+; CHECK:           to label %invoke.cont5 unwind label %[[LPAD1_LABEL]]
+
+invoke.cont4:                                     ; preds = %invoke.cont2
+  invoke void @_ZN5InnerD1Ev(%class.Inner* %inner)
+          to label %invoke.cont5 unwind label %lpad1
+
+; CHECK: invoke.cont5:
+; CHECK:   br label %try.cont
+
+invoke.cont5:                                     ; preds = %invoke.cont4
+  br label %try.cont
+
+; CHECK: [[LPAD_LABEL]]:
+; CHECK:   landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK-NEXT:           catch i8* bitcast (i8** @_ZTIf to i8*)
+; CHECK-NEXT:   [[RECOVER:\%.+]] = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (i8** @_ZTIf to i8*), i32 0, i8* (i8*, i8*)* @_Z4testv.catch)
+; CHECK-NEXT:   indirectbr i8* [[RECOVER]], [label %try.cont19]
+
+lpad:                                             ; preds = %try.cont, %entry
+  %tmp = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (i8** @_ZTIf to i8*)
+  %tmp1 = extractvalue { i8*, i32 } %tmp, 0
+  store i8* %tmp1, i8** %exn.slot
+  %tmp2 = extractvalue { i8*, i32 } %tmp, 1
+  store i32 %tmp2, i32* %ehselector.slot
+  br label %catch.dispatch11
+
+; CHECK: [[LPAD1_LABEL]]:
+; CHECK:   landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK-NEXT:           cleanup
+; CHECK-NEXT:           catch i8* bitcast (i8** @_ZTIi to i8*)
+; CHECK-NEXT:           catch i8* bitcast (i8** @_ZTIf to i8*)
+; CHECK-NEXT:   [[RECOVER1:\%.+]] = call i8* (...) @llvm.eh.actions(
+; CHECK-SAME:       i32 1, i8* bitcast (i8** @_ZTIi to i8*), i32 1, i8* (i8*, i8*)* @_Z4testv.catch.1,
+; CHECK-SAME:       i32 0, void (i8*, i8*)* @_Z4testv.cleanup,
+; CHECK-SAME:       i32 1, i8* bitcast (i8** @_ZTIf to i8*), i32 0, i8* (i8*, i8*)* @_Z4testv.catch)
+; CHECK-NEXT:   indirectbr i8* [[RECOVER1]], [label %try.cont, label %try.cont19]
+
+lpad1:                                            ; preds = %invoke.cont4, %invoke.cont
+  %tmp3 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+          catch i8* bitcast (i8** @_ZTIf to i8*)
+  %tmp4 = extractvalue { i8*, i32 } %tmp3, 0
+  store i8* %tmp4, i8** %exn.slot
+  %tmp5 = extractvalue { i8*, i32 } %tmp3, 1
+  store i32 %tmp5, i32* %ehselector.slot
+  br label %catch.dispatch
+
+; CHECK: [[LPAD3_LABEL]]:
+; CHECK:   landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK-NEXT:           cleanup
+; CHECK-NEXT:           catch i8* bitcast (i8** @_ZTIi to i8*)
+; CHECK-NEXT:           catch i8* bitcast (i8** @_ZTIf to i8*)
+; CHECK-NEXT:   [[RECOVER3:\%.+]] = call i8* (...) @llvm.eh.actions(
+; CHECK-SAME:       i32 0, void (i8*, i8*)* @_Z4testv.cleanup.2,
+; CHECK-SAME:       i32 1, i8* bitcast (i8** @_ZTIi to i8*), i32 1, i8* (i8*, i8*)* @_Z4testv.catch.1,
+; CHECK-SAME:       i32 0, void (i8*, i8*)* @_Z4testv.cleanup,
+; CHECK-SAME:       i32 1, i8* bitcast (i8** @_ZTIf to i8*), i32 0, i8* (i8*, i8*)* @_Z4testv.catch)
+; CHECK-NEXT:   indirectbr i8* [[RECOVER3]], [label %try.cont, label %try.cont19]
+
+lpad3:                                            ; preds = %invoke.cont2
+  %tmp6 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+          catch i8* bitcast (i8** @_ZTIf to i8*)
+  %tmp7 = extractvalue { i8*, i32 } %tmp6, 0
+  store i8* %tmp7, i8** %exn.slot
+  %tmp8 = extractvalue { i8*, i32 } %tmp6, 1
+  store i32 %tmp8, i32* %ehselector.slot
+  call void @_ZN5InnerD1Ev(%class.Inner* %inner)
+  br label %catch.dispatch
+
+; CHECK-NOT: catch.dispatch:
+
+catch.dispatch:                                   ; preds = %lpad3, %lpad1
+  %sel = load i32, i32* %ehselector.slot
+  %tmp9 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) #4
+  %matches = icmp eq i32 %sel, %tmp9
+  br i1 %matches, label %catch, label %ehcleanup
+
+; CHECK-NOT: catch:
+
+catch:                                            ; preds = %catch.dispatch
+  %exn = load i8*, i8** %exn.slot
+  %i.i8 = bitcast i32* %i to i8*
+  call void @llvm.eh.begincatch(i8* %exn, i8* %i.i8) #4
+  %tmp13 = load i32, i32* %i, align 4
+  invoke void @_Z10handle_inti(i32 %tmp13)
+          to label %invoke.cont8 unwind label %lpad7
+
+; CHECK-NOT: invoke.cont8:
+
+invoke.cont8:                                     ; preds = %catch
+  call void @llvm.eh.endcatch() #4
+  br label %try.cont
+
+; CHECK: try.cont:
+; CHECK:   invoke void @_ZN5OuterD1Ev(%class.Outer* %outer)
+; CHECK:           to label %invoke.cont9 unwind label %[[LPAD_LABEL]]
+
+try.cont:                                         ; preds = %invoke.cont8, %invoke.cont5
+  invoke void @_ZN5OuterD1Ev(%class.Outer* %outer)
+          to label %invoke.cont9 unwind label %lpad
+
+invoke.cont9:                                     ; preds = %try.cont
+  br label %try.cont19
+
+; CHECK-NOT: lpad7:
+
+lpad7:                                            ; preds = %catch
+  %tmp14 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+          catch i8* bitcast (i8** @_ZTIf to i8*)
+  %tmp15 = extractvalue { i8*, i32 } %tmp14, 0
+  store i8* %tmp15, i8** %exn.slot
+  %tmp16 = extractvalue { i8*, i32 } %tmp14, 1
+  store i32 %tmp16, i32* %ehselector.slot
+  call void @llvm.eh.endcatch() #4
+  br label %ehcleanup
+
+; CHECK-NOT: ehcleanup:                                        ; preds = %lpad7, %catch.dispatch
+
+ehcleanup:                                        ; preds = %lpad7, %catch.dispatch
+  call void @_ZN5OuterD1Ev(%class.Outer* %outer)
+  br label %catch.dispatch11
+
+; CHECK-NOT: catch.dispatch11:
+
+catch.dispatch11:                                 ; preds = %ehcleanup, %lpad
+  %sel12 = load i32, i32* %ehselector.slot
+  %tmp17 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIf to i8*)) #4
+  %matches13 = icmp eq i32 %sel12, %tmp17
+  br i1 %matches13, label %catch14, label %eh.resume
+
+; CHECK-NOT: catch14:
+
+catch14:                                          ; preds = %catch.dispatch11
+  %exn15 = load i8*, i8** %exn.slot
+  %f.i8 = bitcast float* %f to i8*
+  call void @llvm.eh.begincatch(i8* %exn15, i8* %f.i8) #4
+  %tmp21 = load float, float* %f, align 4
+  call void @_Z12handle_floatf(float %tmp21)
+  call void @llvm.eh.endcatch() #4
+  br label %try.cont19
+
+try.cont19:                                       ; preds = %catch14, %invoke.cont9
+  call void @_Z4donev()
+  ret void
+
+; CHECK-NOT: eh.resume:
+
+eh.resume:                                        ; preds = %catch.dispatch11
+  %exn20 = load i8*, i8** %exn.slot
+  %sel21 = load i32, i32* %ehselector.slot
+  %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn20, 0
+  %lpad.val22 = insertvalue { i8*, i32 } %lpad.val, i32 %sel21, 1
+  resume { i8*, i32 } %lpad.val22
+
+; CHECK: }
+}
+
+; This catch handler should be outlined.
+; CHECK: define internal i8* @_Z4testv.catch(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_F:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @_Z4testv to i8*), i8* %1, i32 0)
+; CHECK:   [[F_PTR:\%.+]] = bitcast i8* [[RECOVER_F]] to float*
+; CHECK:   [[TMP:\%.+]] = load float, float* [[F_PTR]], align 4
+; CHECK:   call void @_Z12handle_floatf(float [[TMP]])
+; CHECK:   ret i8* blockaddress(@_Z4testv, %try.cont19)
+; CHECK: }
+
+; This catch handler should be outlined.
+; CHECK: define internal i8* @_Z4testv.catch.1(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_I:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @_Z4testv to i8*), i8* %1, i32 1)
+; CHECK:   [[I_PTR:\%.+]] = bitcast i8* [[RECOVER_I]] to i32*
+; CHECK:   [[TMP1:\%.+]] = load i32, i32* [[I_PTR]], align 4
+; CHECK:   invoke void @_Z10handle_inti(i32 [[TMP1]])
+; CHECK:           to label %invoke.cont8 unwind label %[[LPAD7_LABEL:lpad[0-9]*]]
+;
+; CHECK: invoke.cont8:                                     ; preds = %entry
+; CHECK:   ret i8* blockaddress(@_Z4testv, %try.cont)
+;
+; CHECK: [[LPAD7_LABEL]]:{{[ ]+}}; preds = %entry
+; CHECK:   [[LPAD7_VAL:\%.+]] = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; (FIXME) The nested handler body isn't being populated yet.
+; CHECK: }
+
+; This cleanup handler should be outlined.
+; CHECK: define internal void @_Z4testv.cleanup(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_OUTER:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @_Z4testv to i8*), i8* %1, i32 2)
+; CHECK:   [[OUTER_PTR:\%.+]] = bitcast i8* [[RECOVER_OUTER]] to %class.Outer*
+; CHECK:   call void @_ZN5OuterD1Ev(%class.Outer* [[OUTER_PTR]])
+; CHECK:   ret void
+; CHECK: }
+
+; This cleanup handler should be outlined.
+; CHECK: define internal void @_Z4testv.cleanup.2(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_INNER:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @_Z4testv to i8*), i8* %1, i32 3)
+; CHECK:   [[INNER_PTR:\%.+]] = bitcast i8* [[RECOVER_INNER]] to %class.Inner*
+; CHECK:   call void @_ZN5InnerD1Ev(%class.Inner* [[INNER_PTR]])
+; CHECK:   ret void
+; CHECK: }
+
+
+
+declare void @_ZN5OuterC1Ev(%class.Outer*) #1
+
+declare i32 @__CxxFrameHandler3(...)
+
+declare void @_ZN5InnerC1Ev(%class.Inner*) #1
+
+declare void @_Z9may_throwv() #1
+
+declare void @_ZN5InnerD1Ev(%class.Inner*) #1
+
+declare void @llvm.eh.begincatch(i8*, i8*)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #3
+
+declare void @_Z10handle_inti(i32) #1
+
+declare void @llvm.eh.endcatch()
+
+declare void @_ZN5OuterD1Ev(%class.Outer*) #1
+
+declare void @_Z12handle_floatf(float) #1
+
+declare void @_Z4donev() #1
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { noinline noreturn nounwind }
+attributes #3 = { nounwind readnone }
+attributes #4 = { nounwind }
+attributes #5 = { noreturn nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 226027)"}
diff --git a/test/CodeGen/WinEH/cppeh-nested-3.ll b/test/CodeGen/WinEH/cppeh-nested-3.ll
new file mode 100644
index 000000000000..c96abcc6e81c
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-nested-3.ll
@@ -0,0 +1,260 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test is based on the following code:
+;
+;void test()
+;{
+;  try {
+;    try {
+;       may_throw();
+;    } catch (int i) {
+;      try {
+;        may_throw();
+;      }
+;      catch (int j) {
+;        i = j;
+;      }
+;      handle_int(i);
+;    }
+;  } catch (float f) {
+;    handle_float(f);
+;  }
+;  done();
+;}
+
+; ModuleID = 'cppeh-nested-3.cpp'
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+
+$"\01??_R0M@8" = comdat any
+
+$"\01??_R0H@8" = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0M@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".M\00" }, comdat
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+
+; CHECK: define void @"\01?test@@YAXXZ"()
+; CHECK: entry:
+; CHECK:   %i = alloca i32, align 4
+; CHECK:   %j = alloca i32, align 4
+; CHECK:   %f = alloca float, align 4
+; CHECK:   call void (...) @llvm.frameescape(i32* %j, i32* %i, float* %f)
+; CHECK:   invoke void @"\01?may_throw@@YAXXZ"()
+; CHECK:           to label %invoke.cont unwind label %[[LPAD_LABEL:lpad[0-9]*]]
+
+; Function Attrs: uwtable
+define void @"\01?test@@YAXXZ"() #0 {
+entry:
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  %i = alloca i32, align 4
+  %j = alloca i32, align 4
+  %f = alloca float, align 4
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %entry
+  br label %try.cont10
+
+; CHECK: [[LPAD_LABEL]]:
+; CHECK:   landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK:           catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+; CHECK:           catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*)
+; CHECK:   [[RECOVER:\%.+]] = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*), i32 1, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch.2", i32 1, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*), i32 2, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch.1")
+; CHECK:   indirectbr i8* [[RECOVER]], [label %try.cont10, label %try.cont19]
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+          catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*)
+  %1 = extractvalue { i8*, i32 } %0, 0
+  store i8* %1, i8** %exn.slot
+  %2 = extractvalue { i8*, i32 } %0, 1
+  store i32 %2, i32* %ehselector.slot
+  br label %catch.dispatch
+
+; CHECK-NOT: catch.dispatch:
+catch.dispatch:                                   ; preds = %lpad
+  %sel = load i32, i32* %ehselector.slot
+  %3 = call i32 @llvm.eh.typeid.for(i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)) #3
+  %matches = icmp eq i32 %sel, %3
+  br i1 %matches, label %catch, label %catch.dispatch11
+
+; CHECK-NOT: catch:
+catch:                                            ; preds = %catch.dispatch
+  %exn = load i8*, i8** %exn.slot
+  %4 = bitcast i32* %i to i8*
+  call void @llvm.eh.begincatch(i8* %exn, i8* %4) #3
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %invoke.cont2 unwind label %lpad1
+
+; CHECK-NOT: invoke.cont2:
+invoke.cont2:                                     ; preds = %catch
+  br label %try.cont
+
+; CHECK-NOT: lpad1:
+lpad1:                                            ; preds = %catch
+  %5 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+          catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*)
+  %6 = extractvalue { i8*, i32 } %5, 0
+  store i8* %6, i8** %exn.slot
+  %7 = extractvalue { i8*, i32 } %5, 1
+  store i32 %7, i32* %ehselector.slot
+  br label %catch.dispatch3
+
+; CHECK-NOT: catch.dispatch3:
+catch.dispatch3:                                  ; preds = %lpad1
+  %sel4 = load i32, i32* %ehselector.slot
+  %8 = call i32 @llvm.eh.typeid.for(i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)) #3
+  %matches5 = icmp eq i32 %sel4, %8
+  br i1 %matches5, label %catch6, label %catch.dispatch11
+
+; CHECK-NOT: catch6:
+catch6:                                           ; preds = %catch.dispatch3
+  %exn7 = load i8*, i8** %exn.slot
+  %9 = bitcast i32* %j to i8*
+  call void @llvm.eh.begincatch(i8* %exn7, i8* %9) #3
+  %10 = load i32, i32* %j, align 4
+  store i32 %10, i32* %i, align 4
+  call void @llvm.eh.endcatch() #3
+  br label %try.cont
+
+; CHECK-NOT: try.cont:
+try.cont:                                         ; preds = %catch6, %invoke.cont2
+  %11 = load i32, i32* %i, align 4
+  invoke void @"\01?handle_int@@YAXH@Z"(i32 %11)
+          to label %invoke.cont9 unwind label %lpad8
+
+; CHECK-NOT: invoke.cont9:
+invoke.cont9:                                     ; preds = %try.cont
+  call void @llvm.eh.endcatch() #3
+  br label %try.cont10
+
+try.cont10:                                       ; preds = %invoke.cont9, %invoke.cont
+  br label %try.cont19
+
+; CHECK-NOT: lpad8:
+lpad8:                                            ; preds = %try.cont
+  %12 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*)
+  %13 = extractvalue { i8*, i32 } %12, 0
+  store i8* %13, i8** %exn.slot
+  %14 = extractvalue { i8*, i32 } %12, 1
+  store i32 %14, i32* %ehselector.slot
+  call void @llvm.eh.endcatch() #3
+  br label %catch.dispatch11
+
+; CHECK-NOT: catch.dispatch11:
+catch.dispatch11:                                 ; preds = %lpad8, %catch.dispatch3, %catch.dispatch
+  %sel12 = load i32, i32* %ehselector.slot
+  %15 = call i32 @llvm.eh.typeid.for(i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*)) #3
+  %matches13 = icmp eq i32 %sel12, %15
+  br i1 %matches13, label %catch14, label %eh.resume
+
+; CHECK-NOT: catch14:
+catch14:                                          ; preds = %catch.dispatch11
+  %exn15 = load i8*, i8** %exn.slot
+  %16 = bitcast float* %f to i8*
+  call void @llvm.eh.begincatch(i8* %exn15, i8* %16) #3
+  %17 = load float, float* %f, align 4
+  call void @"\01?handle_float@@YAXM@Z"(float %17)
+  call void @llvm.eh.endcatch() #3
+  br label %try.cont19
+
+try.cont19:                                       ; preds = %catch14, %try.cont10
+  call void @"\01?done@@YAXXZ"()
+  ret void
+
+; CHECK-NOT: eh.resume:
+eh.resume:                                        ; preds = %lpad16, %catch.dispatch11
+  %exn20 = load i8*, i8** %exn.slot
+  %sel21 = load i32, i32* %ehselector.slot
+  %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn20, 0
+  %lpad.val22 = insertvalue { i8*, i32 } %lpad.val, i32 %sel21, 1
+  resume { i8*, i32 } %lpad.val22
+; CHECK: }
+}
+
+; CHECK: define internal i8* @"\01?test@@YAXXZ.catch"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_J:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 0)
+; CHECK:   [[J_PTR:\%.+]] = bitcast i8* [[RECOVER_J]] to i32*
+; CHECK:   [[RECOVER_I1:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 1)
+; CHECK:   [[I_PTR1:\%.+]] = bitcast i8* [[RECOVER_I1]] to i32*
+; CHECK:   [[TMP3:\%.+]] = load i32, i32* [[J_PTR]], align 4
+; CHECK:   store i32 [[TMP3]], i32* [[I_PTR1]]
+; CHECK:   ret i8* blockaddress(@"\01?test@@YAXXZ.catch.2", %invoke.cont2)
+; CHECK: }
+
+; CHECK: define internal i8* @"\01?test@@YAXXZ.catch.1"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_F:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 2)
+; CHECK:   [[F_PTR:\%.+]] = bitcast i8* [[RECOVER_F]] to float*
+; CHECK:   [[TMP2:\%.+]] = load float, float* [[F_PTR]], align 4
+; CHECK:   call void @"\01?handle_float@@YAXM@Z"(float [[TMP2]])
+; CHECK:   ret i8* blockaddress(@"\01?test@@YAXXZ", %try.cont19)
+; CHECK: }
+
+; CHECK: define internal i8* @"\01?test@@YAXXZ.catch.2"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_I:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 1)
+; CHECK:   [[I_PTR:\%.+]] = bitcast i8* [[RECOVER_I]] to i32*
+; CHECK:   invoke void @"\01?may_throw@@YAXXZ"()
+; CHECK:           to label %invoke.cont2 unwind label %[[LPAD1_LABEL:lpad[0-9]*]]
+;
+; CHECK: invoke.cont2:                                     ; preds = %[[LPAD1_LABEL]], %entry
+; CHECK:   [[TMP1:\%.+]] = load i32, i32* [[I_PTR]], align 4
+; CHECK:   invoke void @"\01?handle_int@@YAXH@Z"(i32 [[TMP1]])
+; CHECK:           to label %invoke.cont9 unwind label %[[LPAD8_LABEL:lpad[0-9]*]]
+;
+; CHECK: [[LPAD1_LABEL]]:{{[ ]+}}; preds = %entry
+; CHECK:   [[LPAD1_VAL:\%.+]] = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK:           catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+; CHECK:           catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*)
+; CHECK:   [[RECOVER1:\%.+]] = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*), i32 0, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch", i32 1, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*), i32 2, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch.1")
+; CHECK:   indirectbr i8* [[RECOVER1]], [label %invoke.cont2]
+;
+; CHECK: invoke.cont9:
+; CHECK:   ret i8* blockaddress(@"\01?test@@YAXXZ", %try.cont10)
+;
+; CHECK: [[LPAD8_LABEL]]:{{[ ]+}}; preds = %invoke.cont2
+; CHECK:   [[LPAD8_VAL:\%.+]] = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK:           catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*)
+; CHECK:   [[RECOVER2:\%.+]] = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0M@8" to i8*), i32 2, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch.1")
+; CHECK:   indirectbr i8* [[RECOVER2]], []
+;
+; CHECK: }
+
+declare void @"\01?may_throw@@YAXXZ"() #1
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #2
+
+; Function Attrs: nounwind
+declare void @llvm.eh.begincatch(i8* nocapture, i8* nocapture) #3
+
+; Function Attrs: nounwind
+declare void @llvm.eh.endcatch() #3
+
+declare void @"\01?handle_int@@YAXH@Z"(i32) #1
+
+declare void @"\01?handle_float@@YAXM@Z"(float) #1
+
+declare void @"\01?done@@YAXXZ"() #1
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 (trunk 232069) (llvm/trunk 232070)"}
diff --git a/test/CodeGen/WinEH/cppeh-nested-rethrow.ll b/test/CodeGen/WinEH/cppeh-nested-rethrow.ll
new file mode 100644
index 000000000000..60b404113345
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-nested-rethrow.ll
@@ -0,0 +1,212 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test was generated from the following code.
+;
+; void test1() {
+;   try {
+;     try {
+;       throw 1;
+;     } catch(...) { throw; }
+;   } catch (...) { }
+; }
+; void test2() {
+;   try {
+;     throw 1;
+;   } catch(...) {
+;     try {
+;       throw; 
+;     } catch (...) {}
+;   }
+; }
+;
+; These two functions result in functionally equivalent code, but the last
+; catch block contains a call to llvm.eh.endcatch that tripped up processing
+; during development.
+;
+; The main purpose of this test is to verify that we can correctly
+; handle the case of nested landing pads that return directly to a block in
+; the parent function.
+
+; ModuleID = 'cppeh-nested-rethrow.cpp'
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+%eh.CatchableType = type { i32, i32, i32, i32, i32, i32, i32 }
+%eh.CatchableTypeArray.1 = type { i32, [1 x i32] }
+%eh.ThrowInfo = type { i32, i32, i32, i32 }
+
+$"\01??_R0H@8" = comdat any
+
+$"_CT??_R0H@84" = comdat any
+
+$_CTA1H = comdat any
+
+$_TI1H = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+@__ImageBase = external constant i8
+@"_CT??_R0H@84" = linkonce_odr unnamed_addr constant %eh.CatchableType { i32 1, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32), i32 0, i32 -1, i32 0, i32 4, i32 0 }, section ".xdata", comdat
+@_CTA1H = linkonce_odr unnamed_addr constant %eh.CatchableTypeArray.1 { i32 1, [1 x i32] [i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableType* @"_CT??_R0H@84" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32)] }, section ".xdata", comdat
+@_TI1H = linkonce_odr unnamed_addr constant %eh.ThrowInfo { i32 0, i32 0, i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableTypeArray.1* @_CTA1H to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32) }, section ".xdata", comdat
+
+; CHECK-LABEL: define void @"\01?test1@@YAXXZ"()
+; CHECK: entry:
+; CHECK:   call void (...) @llvm.frameescape
+
+; Function Attrs: nounwind uwtable
+define void @"\01?test1@@YAXXZ"() #0 {
+entry:
+  %tmp = alloca i32, align 4
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  store i32 1, i32* %tmp
+  %0 = bitcast i32* %tmp to i8*
+  invoke void @_CxxThrowException(i8* %0, %eh.ThrowInfo* @_TI1H) #2
+          to label %unreachable unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* null
+  %2 = extractvalue { i8*, i32 } %1, 0
+  store i8* %2, i8** %exn.slot
+  %3 = extractvalue { i8*, i32 } %1, 1
+  store i32 %3, i32* %ehselector.slot
+  br label %catch
+
+catch:                                            ; preds = %lpad
+  %exn = load i8*, i8** %exn.slot
+  call void @llvm.eh.begincatch(i8* %exn, i8* null) #1
+  invoke void @_CxxThrowException(i8* null, %eh.ThrowInfo* null) #2
+          to label %unreachable unwind label %lpad1
+
+lpad1:                                            ; preds = %catch
+  %4 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* null
+  %5 = extractvalue { i8*, i32 } %4, 0
+  store i8* %5, i8** %exn.slot
+  %6 = extractvalue { i8*, i32 } %4, 1
+  store i32 %6, i32* %ehselector.slot
+  br label %catch2
+
+catch2:                                           ; preds = %lpad1
+  %exn3 = load i8*, i8** %exn.slot
+  call void @llvm.eh.begincatch(i8* %exn3, i8* null) #1
+  call void @llvm.eh.endcatch() #1
+  br label %try.cont.4
+
+; This block should not be eliminated.
+; CHECK: try.cont.4:
+try.cont.4:                                        ; preds = %catch2, %try.cont
+  ret void
+
+try.cont:                                         ; No predecessors!
+  br label %try.cont.4
+
+unreachable:                                      ; preds = %catch, %entry
+  unreachable
+; CHECK: }
+}
+
+declare void @_CxxThrowException(i8*, %eh.ThrowInfo*)
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind
+declare void @llvm.eh.begincatch(i8* nocapture, i8* nocapture) #1
+
+; Function Attrs: nounwind
+declare void @llvm.eh.endcatch() #1
+
+; CHECK-LABEL: define void @"\01?test2@@YAXXZ"()
+; CHECK: entry:
+; CHECK:   call void (...) @llvm.frameescape
+
+; Function Attrs: nounwind uwtable
+define void @"\01?test2@@YAXXZ"() #0 {
+entry:
+  %tmp = alloca i32, align 4
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  store i32 1, i32* %tmp
+  %0 = bitcast i32* %tmp to i8*
+  invoke void @_CxxThrowException(i8* %0, %eh.ThrowInfo* @_TI1H) #2
+          to label %unreachable unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* null
+  %2 = extractvalue { i8*, i32 } %1, 0
+  store i8* %2, i8** %exn.slot
+  %3 = extractvalue { i8*, i32 } %1, 1
+  store i32 %3, i32* %ehselector.slot
+  br label %catch
+
+catch:                                            ; preds = %lpad
+  %exn = load i8*, i8** %exn.slot
+  call void @llvm.eh.begincatch(i8* %exn, i8* null) #1
+  invoke void @_CxxThrowException(i8* null, %eh.ThrowInfo* null) #2
+          to label %unreachable unwind label %lpad1
+
+lpad1:                                            ; preds = %catch
+  %4 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* null
+  %5 = extractvalue { i8*, i32 } %4, 0
+  store i8* %5, i8** %exn.slot
+  %6 = extractvalue { i8*, i32 } %4, 1
+  store i32 %6, i32* %ehselector.slot
+  br label %catch2
+
+catch2:                                           ; preds = %lpad1
+  %exn3 = load i8*, i8** %exn.slot
+  call void @llvm.eh.begincatch(i8* %exn3, i8* null) #1
+  call void @llvm.eh.endcatch() #1
+  br label %try.cont
+
+; This block should not be eliminated.
+; CHECK: try.cont:
+; The endcatch call should be eliminated.
+; CHECK-NOT: call void @llvm.eh.endcatch()
+try.cont:                                         ; preds = %catch2
+  call void @llvm.eh.endcatch() #1
+  br label %try.cont.4
+
+try.cont.4:                                        ; preds = %try.cont
+  ret void
+
+unreachable:                                      ; preds = %catch, %entry
+  unreachable
+; CHECK: }
+}
+
+; The outlined test1.catch handler should return to a valid block address.
+; CHECK-LABEL: define internal i8* @"\01?test1@@YAXXZ.catch"(i8*, i8*)
+; CHECK-NOT:  ret i8* inttoptr (i32 1 to i8*)
+; CHECK: }
+
+; The outlined test1.catch1 handler should not contain a return instruction.
+; CHECK-LABEL: define internal i8* @"\01?test1@@YAXXZ.catch.1"(i8*, i8*)
+; CHECK-NOT: ret
+; CHECK: }
+
+; The outlined test2.catch handler should return to a valid block address.
+; CHECK-LABEL: define internal i8* @"\01?test2@@YAXXZ.catch"(i8*, i8*)
+; CHECK-NOT:  ret i8* inttoptr (i32 1 to i8*)
+; CHECK: }
+
+; The outlined test2.catch2 handler should not contain a return instruction.
+; CHECK-LABEL: define internal i8* @"\01?test2@@YAXXZ.catch.2"(i8*, i8*)
+; CHECK-NOT: ret
+; CHECK: }
+
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind }
+attributes #2 = { noreturn }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 (trunk 236059)"}
diff --git a/test/CodeGen/WinEH/cppeh-nonalloca-frame-values.ll b/test/CodeGen/WinEH/cppeh-nonalloca-frame-values.ll
new file mode 100644
index 000000000000..15f6bfb4680d
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-nonalloca-frame-values.ll
@@ -0,0 +1,278 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test is based on the following code:
+;
+; struct SomeData {
+;   int a;
+;   int b;
+; };
+; 
+; void may_throw();
+; void does_not_throw(int i);
+; void dump(int *, int, SomeData&);
+; 
+; void test() {
+;   int NumExceptions = 0;
+;   int ExceptionVal[10];
+;   SomeData Data = { 0, 0 };
+; 
+;   for (int i = 0; i < 10; ++i) {
+;     try {
+;       may_throw();
+;       Data.a += i;
+;     }
+;     catch (int e) {
+;       ExceptionVal[NumExceptions] = e;
+;       ++NumExceptions;
+;       if (e == i)
+;         Data.b += e;
+;       else
+;         Data.a += e;
+;     }
+;     does_not_throw(NumExceptions);
+;   }
+;   dump(ExceptionVal, NumExceptions, Data);
+; }
+;
+; Unlike the cppeh-frame-vars.ll test, this test was generated using -O2
+; optimization, which results in non-alloca values being used in the
+; catch handler.
+
+; ModuleID = 'cppeh-frame-vars.cpp'
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+%struct.SomeData = type { i32, i32 }
+
+$"\01??_R0H@8" = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+
+; The function entry should be rewritten like this.
+; CHECK: define void @"\01?test@@YAXXZ"()
+; CHECK: entry:
+; CHECK:   [[NUMEXCEPTIONS_REGMEM:\%.+]] = alloca i32
+; CHECK:   [[I_REGMEM:\%.+]] = alloca i32
+; CHECK:   [[B_REGMEM:\%.+]] = alloca i32*
+; CHECK:   [[A_REGMEM:\%.+]] = alloca i32*
+; CHECK:   [[E_PTR:\%.+]] = alloca i32, align 4
+; CHECK:   [[EXCEPTIONVAL:\%.+]] = alloca [10 x i32], align 16
+; CHECK:   [[DATA_PTR:\%.+]] = alloca i64, align 8
+; CHECK:   [[TMPCAST:\%.+]] = bitcast i64* [[DATA_PTR]] to %struct.SomeData*
+; CHECK:   [[TMP:\%.+]] = bitcast [10 x i32]* [[EXCEPTIONVAL]] to i8*
+; CHECK:   call void @llvm.lifetime.start(i64 40, i8* [[TMP]])
+; CHECK:   store i64 0, i64* [[DATA_PTR]], align 8
+; CHECK:   [[A_PTR:\%.+]] = bitcast i64* [[DATA_PTR]] to i32*
+; CHECK:   store i32* [[A_PTR]], i32** [[A_REGMEM]]
+; CHECK:   [[B_PTR:\%.+]] = getelementptr inbounds %struct.SomeData, %struct.SomeData* [[TMPCAST]], i64 0, i32 1
+; CHECK:   store i32* [[B_PTR]], i32** [[B_REGMEM]]
+; CHECK:   call void (...) @llvm.frameescape(i32* %e, i32* %NumExceptions.020.reg2mem, [10 x i32]* [[EXCEPTIONVAL]], i32* %inc.reg2mem, i32* [[I_REGMEM]], i32** [[A_REGMEM]], i32** [[B_REGMEM]])
+; CHECK:   br label %for.body
+
+; Function Attrs: uwtable
+define void @"\01?test@@YAXXZ"() #0 {
+entry:
+  %e = alloca i32, align 4
+  %ExceptionVal = alloca [10 x i32], align 16
+  %Data = alloca i64, align 8
+  %tmpcast = bitcast i64* %Data to %struct.SomeData*
+  %0 = bitcast [10 x i32]* %ExceptionVal to i8*
+  call void @llvm.lifetime.start(i64 40, i8* %0) #1
+  store i64 0, i64* %Data, align 8
+  %a = bitcast i64* %Data to i32*
+  %b = getelementptr inbounds %struct.SomeData, %struct.SomeData* %tmpcast, i64 0, i32 1
+  br label %for.body
+
+; CHECK: for.body:
+; CHECK:   [[NUMEXCEPTIONS_PHI:\%.*]] = phi i32 [ 0, %entry ], [ {{\%NumExceptions.*}}, %try.cont ]
+; CHECK:   [[I_PHI:\%.*]] = phi i32 [ 0, %entry ], [ {{\%inc.*}}, %try.cont ]
+; CHECK:   store i32 [[I_PHI]], i32* [[I_REGMEM]]
+; CHECK:   store i32 [[NUMEXCEPTIONS_PHI]], i32* [[NUMEXCEPTIONS_REGMEM]]
+; CHECK:   invoke void @"\01?may_throw@@YAXXZ"()
+for.body:                                         ; preds = %entry, %try.cont
+  %NumExceptions.020 = phi i32 [ 0, %entry ], [ %NumExceptions.1, %try.cont ]
+  %i.019 = phi i32 [ 0, %entry ], [ %inc5, %try.cont ]
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %invoke.cont unwind label %lpad
+
+; CHECK: invoke.cont:                                      ; preds = %for.body
+; CHECK:   [[A_RELOAD:\%.+]] = load i32*, i32** [[A_REGMEM]]
+; CHECK:   [[TMP1:\%.+]] = load i32, i32* [[A_RELOAD]], align 8
+; CHECK:   [[I_RELOAD:\%.+]] = load i32, i32* [[I_REGMEM]]
+; CHECK:   [[ADD:\%.+]] = add nsw i32 [[TMP1]], [[I_RELOAD]]
+; CHECK:   [[A_RELOAD1:\%.+]] = load i32*, i32** [[A_REGMEM]]
+; CHECK:   [[NUMEXCEPTIONS_RELOAD:\%.+]] = load i32, i32* [[NUMEXCEPTIONS_REGMEM]]
+; CHECK:   br label %try.cont
+invoke.cont:                                      ; preds = %for.body
+  %1 = load i32, i32* %a, align 8, !tbaa !2
+  %add = add nsw i32 %1, %i.019
+  store i32 %add, i32* %a, align 8, !tbaa !2
+  br label %try.cont
+
+; CHECK: [[LPAD_LABEL:lpad[0-9]*]]:{{[ ]+}}; preds = %for.body
+; CHECK:   landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK-NEXT:           catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+; CHECK-NEXT:   [[RECOVER:\%.+]] = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*), i32 0, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch")
+; CHECK-NEXT:   indirectbr i8* [[RECOVER]], [label %[[SPLIT_RECOVER_BB:.*]]]
+
+lpad:                                             ; preds = %for.body
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)
+  %3 = extractvalue { i8*, i32 } %2, 1
+  %4 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*)) #1
+  %matches = icmp eq i32 %3, %4
+  br i1 %matches, label %catch, label %eh.resume
+
+; CHECK-NOT: catch:
+
+catch:                                            ; preds = %lpad
+  %5 = extractvalue { i8*, i32 } %2, 0
+  %e.i8 = bitcast i32* %e to i8*
+  call void @llvm.eh.begincatch(i8* %5, i8* %e.i8) #1
+  %tmp8 = load i32, i32* %e, align 4, !tbaa !7
+  %idxprom = sext i32 %NumExceptions.020 to i64
+  %arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* %ExceptionVal, i64 0, i64 %idxprom
+  store i32 %tmp8, i32* %arrayidx, align 4, !tbaa !7
+  %inc = add nsw i32 %NumExceptions.020, 1
+  %cmp1 = icmp eq i32 %tmp8, %i.019
+  br i1 %cmp1, label %if.then, label %if.else
+
+if.then:                                          ; preds = %catch
+  %tmp9 = load i32, i32* %b, align 4, !tbaa !8
+  %add2 = add nsw i32 %tmp9, %i.019
+  store i32 %add2, i32* %b, align 4, !tbaa !8
+  br label %if.end
+
+; CHECK-NOT: if.else:
+
+if.else:                                          ; preds = %catch
+  %tmp10 = load i32, i32* %a, align 8, !tbaa !2
+  %add4 = add nsw i32 %tmp10, %tmp8
+  store i32 %add4, i32* %a, align 8, !tbaa !2
+  br label %if.end
+
+; CHECK-NOT: if.end:
+; CHECK: [[SPLIT_RECOVER_BB]]:
+; CHECK: [[INC_RELOAD:\%.*]] = load i32, i32*
+; CHECK: br label %try.cont
+
+if.end:                                           ; preds = %if.else, %if.then
+  tail call void @llvm.eh.endcatch() #1
+  br label %try.cont
+
+; CHECK: try.cont:{{[ ]+}}; preds = %[[SPLIT_RECOVER_BB]], %invoke.cont
+; CHECK:   [[NUMEXCEPTIONS_PHI:\%.*]] = phi i32 [ [[NUMEXCEPTIONS_RELOAD]], %invoke.cont ], [ [[INC_RELOAD]], %[[SPLIT_RECOVER_BB]] ]
+; CHECK:   tail call void @"\01?does_not_throw@@YAXH@Z"(i32 [[NUMEXCEPTIONS_PHI]])
+; CHECK:   [[I_RELOAD:\%.+]] = load i32, i32* [[I_REGMEM]]
+; CHECK:   [[INC:\%.+]] = add nuw nsw i32 [[I_RELOAD]], 1
+; CHECK:   [[CMP:\%.+]] = icmp slt i32 [[INC]], 10
+; CHECK:   br i1 [[CMP]], label %for.body, label %for.end
+
+try.cont:                                         ; preds = %if.end, %invoke.cont
+  %NumExceptions.1 = phi i32 [ %NumExceptions.020, %invoke.cont ], [ %inc, %if.end ]
+  tail call void @"\01?does_not_throw@@YAXH@Z"(i32 %NumExceptions.1)
+  %inc5 = add nuw nsw i32 %i.019, 1
+  %cmp = icmp slt i32 %inc5, 10
+  br i1 %cmp, label %for.body, label %for.end
+
+for.end:                                          ; preds = %try.cont
+  %NumExceptions.1.lcssa = phi i32 [ %NumExceptions.1, %try.cont ]
+  %arraydecay = getelementptr inbounds [10 x i32], [10 x i32]* %ExceptionVal, i64 0, i64 0
+  call void @"\01?dump@@YAXPEAHHAEAUSomeData@@@Z"(i32* %arraydecay, i32 %NumExceptions.1.lcssa, %struct.SomeData* dereferenceable(8) %tmpcast)
+  call void @llvm.lifetime.end(i64 40, i8* %0) #1
+  ret void
+
+eh.resume:                                        ; preds = %lpad
+  %.lcssa = phi { i8*, i32 } [ %2, %lpad ]
+  resume { i8*, i32 } %.lcssa
+}
+
+; The following catch handler should be outlined.
+; CHECK: define internal i8* @"\01?test@@YAXXZ.catch"(i8*, i8*)
+; CHECK: entry:
+; CHECK:   [[RECOVER_E:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 0)
+; CHECK:   [[E_PTR:\%.+]] = bitcast i8* [[RECOVER_E]] to i32*
+; CHECK:   [[RECOVER_NUMEXCEPTIONS:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 1)
+; CHECK:   [[NUMEXCEPTIONS_REGMEM:\%.+]] = bitcast i8* [[RECOVER_NUMEXCEPTIONS]] to i32*
+; CHECK:   [[RECOVER_EXCEPTIONVAL:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 2)
+; CHECK:   [[EXCEPTIONVAL:\%.+]] = bitcast i8* [[RECOVER_EXCEPTIONVAL]] to [10 x i32]*
+; CHECK:   [[RECOVER_INC:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 3)
+; CHECK:   [[INC_REGMEM:\%.+]] = bitcast i8* [[RECOVER_INC]] to i32*
+; CHECK:   [[RECOVER_I:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 4)
+; CHECK:   [[I_REGMEM:\%.+]] = bitcast i8* [[RECOVER_I]] to i32*
+; CHECK:   [[RECOVER_A:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 5)
+; CHECK:   [[A_REGMEM:\%.+]] = bitcast i8* [[RECOVER_A]] to i32**
+; CHECK:   [[RECOVER_B:\%.+]] = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 6)
+; CHECK:   [[B_REGMEM:\%.+]] = bitcast i8* [[RECOVER_B]] to i32**
+; CHECK:   [[E_I8PTR:\%.+]] = bitcast i32* [[E_PTR]] to i8*
+; CHECK:   [[TMP:\%.+]] = load i32, i32* [[E_PTR]], align 4
+; CHECK:   [[NUMEXCEPTIONS_RELOAD:\%.+]] = load i32, i32* [[NUMEXCEPTIONS_REGMEM]]
+; CHECK:   [[IDXPROM:\%.+]] = sext i32 [[NUMEXCEPTIONS_RELOAD]] to i64
+; CHECK:   [[ARRAYIDX:\%.+]] = getelementptr inbounds [10 x i32], [10 x i32]* [[EXCEPTIONVAL]], i64 0, i64 [[IDXPROM]]
+; CHECK:   store i32 [[TMP]], i32* [[ARRAYIDX]], align 4
+; CHECK:   [[NUMEXCEPTIONS_RELOAD:\%.+]] = load i32, i32* [[NUMEXCEPTIONS_REGMEM]]
+; CHECK:   [[INC:\%.+]] = add nsw i32 [[NUMEXCEPTIONS_RELOAD]], 1
+; CHECK:   [[CMP:\%.+]] = icmp eq i32 [[TMP]], [[I_RELOAD]]
+; CHECK:   br i1 [[CMP]], label %if.then, label %if.else
+;
+; CHECK: if.then:{{[ ]+}}; preds = %entry
+; CHECK:   [[B_RELOAD:\%.+]] = load i32*, i32** [[B_REGMEM]]
+; CHECK:   [[TMP1:\%.+]] = load i32, i32* [[B_RELOAD]], align 4
+; CHECK:   [[I_RELOAD:\%.+]] = load i32, i32* [[I_REGMEM]]
+; CHECK:   [[ADD:\%.+]] = add nsw i32 [[TMP1]], [[I_RELOAD]]
+; CHECK:   [[B_RELOAD:\%.+]] = load i32*, i32** [[B_REGMEM]]
+; CHECK:   store i32 [[ADD]], i32* [[B_RELOAD]], align 4
+; CHECK:   br label %if.end
+;
+; CHECK: if.else:{{[ ]+}}; preds = %entry
+; CHECK:   [[A_RELOAD:\%.+]] = load i32*, i32** [[A_REGMEM]]
+; CHECK:   [[TMP2:\%.+]] = load i32, i32* [[A_RELOAD]], align 8
+; CHECK:   [[ADD2:\%.+]] = add nsw i32 [[TMP2]], [[TMP]]
+; CHECK:   [[A_RELOAD:\%.+]] = load i32*, i32** [[A_REGMEM]]
+; CHECK:   store i32 [[ADD2]], i32* [[A_RELOAD]], align 8
+; CHECK:   br label %if.end
+;
+; CHECK: if.end:{{[ ]+}}; preds = %if.else, %if.then
+; CHECK:   ret i8* blockaddress(@"\01?test@@YAXXZ", %[[SPLIT_RECOVER_BB]])
+; CHECK: }
+
+; Function Attrs: nounwind
+declare void @llvm.lifetime.start(i64, i8* nocapture) #1
+
+declare void @"\01?may_throw@@YAXXZ"() #2
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #3
+
+declare void @llvm.eh.begincatch(i8*, i8*)
+
+declare void @llvm.eh.endcatch()
+
+declare void @"\01?does_not_throw@@YAXH@Z"(i32) #2
+
+declare void @"\01?dump@@YAXPEAHHAEAUSomeData@@@Z"(i32*, i32, %struct.SomeData* dereferenceable(8)) #2
+
+; Function Attrs: nounwind
+declare void @llvm.lifetime.end(i64, i8* nocapture) #1
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind }
+attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { nounwind readnone }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 (trunk 228868)"}
+!2 = !{!3, !4, i64 0}
+!3 = !{!"?AUSomeData@@", !4, i64 0, !4, i64 4}
+!4 = !{!"int", !5, i64 0}
+!5 = !{!"omnipotent char", !6, i64 0}
+!6 = !{!"Simple C/C++ TBAA"}
+!7 = !{!4, !4, i64 0}
+!8 = !{!3, !4, i64 4}
diff --git a/test/CodeGen/WinEH/cppeh-prepared-catch-all.ll b/test/CodeGen/WinEH/cppeh-prepared-catch-all.ll
new file mode 100644
index 000000000000..f395d64c7b5e
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-prepared-catch-all.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+; This test case is equivalent to:
+; extern "C" void may_throw();
+; extern "C" void test_catch_all() {
+;   try {
+;     may_throw();
+;   } catch (...) {
+;   }
+; }
+
+declare void @may_throw() #1
+declare i32 @__CxxFrameHandler3(...)
+declare void @llvm.eh.begincatch(i8* nocapture, i8* nocapture) #2
+declare void @llvm.eh.endcatch() #2
+
+; Function Attrs: nounwind uwtable
+define void @test_catch_all() #0 {
+entry:
+  invoke void @may_throw()
+          to label %try.cont unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* null
+  %1 = extractvalue { i8*, i32 } %0, 0
+  tail call void @llvm.eh.begincatch(i8* %1, i8* null) #2
+  tail call void @llvm.eh.endcatch() #2
+  br label %try.cont
+
+try.cont:                                         ; preds = %entry, %lpad
+  ret void
+}
+
+; CHECK-LABEL: $handlerMap$0$test_catch_all:
+; CHECK:         .long   {{[0-9]+}}
+; CHECK:         .long   0
+; CHECK:         .long   0
+; CHECK:         .long   test_catch_all.catch@IMGREL
+; CHECK:         .long   .Ltest_catch_all.catch$parent_frame_offset
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind }
diff --git a/test/CodeGen/WinEH/cppeh-prepared-catch-reordered.ll b/test/CodeGen/WinEH/cppeh-prepared-catch-reordered.ll
new file mode 100644
index 000000000000..6383ca7f1883
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-prepared-catch-reordered.ll
@@ -0,0 +1,164 @@
+; RUN: llc < %s | FileCheck %s
+
+; Verify that we get the right frame escape label when the catch comes after the
+; parent function.
+
+; This test case is equivalent to:
+; int main() {
+;   try {
+;     throw 42;
+;   } catch (int e) {
+;     printf("e: %d\n", e);
+;   }
+; }
+
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+%eh.CatchableType = type { i32, i32, i32, i32, i32, i32, i32 }
+%eh.CatchableTypeArray.1 = type { i32, [1 x i32] }
+%eh.ThrowInfo = type { i32, i32, i32, i32 }
+%eh.CatchHandlerType = type { i32, i8* }
+
+$"\01??_R0H@8" = comdat any
+
+$"_CT??_R0H@84" = comdat any
+
+$_CTA1H = comdat any
+
+$_TI1H = comdat any
+
+$"\01??_C@_06PNOAJMHG@e?3?5?$CFd?6?$AA@" = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+@__ImageBase = external constant i8
+@"_CT??_R0H@84" = linkonce_odr unnamed_addr constant %eh.CatchableType { i32 1, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32), i32 0, i32 -1, i32 0, i32 4, i32 0 }, section ".xdata", comdat
+@_CTA1H = linkonce_odr unnamed_addr constant %eh.CatchableTypeArray.1 { i32 1, [1 x i32] [i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableType* @"_CT??_R0H@84" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32)] }, section ".xdata", comdat
+@_TI1H = linkonce_odr unnamed_addr constant %eh.ThrowInfo { i32 0, i32 0, i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableTypeArray.1* @_CTA1H to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32) }, section ".xdata", comdat
+@llvm.eh.handlertype.H.0 = private unnamed_addr constant %eh.CatchHandlerType { i32 0, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*) }, section "llvm.metadata"
+@"\01??_C@_06PNOAJMHG@e?3?5?$CFd?6?$AA@" = linkonce_odr unnamed_addr constant [7 x i8] c"e: %d\0A\00", comdat, align 1
+
+declare void @_CxxThrowException(i8*, %eh.ThrowInfo*)
+
+; Function Attrs: uwtable
+define i32 @main() #1 {
+entry:
+  %tmp.i = alloca i32, align 4
+  %e = alloca i32, align 4
+  %0 = bitcast i32* %tmp.i to i8*
+  store i32 42, i32* %tmp.i, align 4, !tbaa !2
+  call void (...) @llvm.frameescape(i32* %e)
+  invoke void @_CxxThrowException(i8* %0, %eh.ThrowInfo* @_TI1H) #6
+          to label %.noexc unwind label %lpad1
+
+.noexc:                                           ; preds = %entry
+  unreachable
+
+lpad1:                                            ; preds = %entry
+  %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.H.0
+  %recover = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*), i32 0, i8* (i8*, i8*)* @main.catch)
+  indirectbr i8* %recover, [label %try.cont.split]
+
+try.cont.split:                                   ; preds = %lpad1
+  ret i32 0
+}
+
+; CHECK-LABEL: main:
+; CHECK:        .seh_handlerdata
+; CHECK:        .long   ($cppxdata$main)@IMGREL
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #2
+
+; Function Attrs: nounwind
+declare void @llvm.eh.begincatch(i8* nocapture, i8* nocapture) #3
+
+; Function Attrs: nounwind
+declare i32 @printf(i8* nocapture readonly, ...) #4
+
+; Function Attrs: nounwind
+declare void @llvm.eh.endcatch() #3
+
+; Function Attrs: nounwind
+declare void @llvm.lifetime.start(i64, i8* nocapture) #3
+
+; Function Attrs: nounwind
+declare i8* @llvm.eh.actions(...) #3
+
+define internal i8* @main.catch(i8*, i8*) #5 {
+entry:
+  %e.i8 = call i8* @llvm.framerecover(i8* bitcast (i32 ()* @main to i8*), i8* %1, i32 0)
+  %e = bitcast i8* %e.i8 to i32*
+  %2 = bitcast i32* %e to i8*
+  %3 = load i32, i32* %e, align 4, !tbaa !2
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @"\01??_C@_06PNOAJMHG@e?3?5?$CFd?6?$AA@", i64 0, i64 0), i32 %3)
+  invoke void @llvm.donothing()
+          to label %entry.split unwind label %stub
+
+entry.split:                                      ; preds = %entry
+  ret i8* blockaddress(@main, %try.cont.split)
+
+stub:                                             ; preds = %entry
+  %4 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %recover = call i8* (...) @llvm.eh.actions()
+  unreachable
+}
+
+; CHECK-LABEL: main.catch:
+; CHECK:        .seh_handlerdata
+; CHECK:        .long   ($cppxdata$main)@IMGREL
+
+; CHECK-NEXT: $cppxdata$main:
+; CHECK-NEXT:         .long   429065506
+; CHECK-NEXT:         .long   2
+; CHECK-NEXT:         .long   ($stateUnwindMap$main)@IMGREL
+; CHECK-NEXT:         .long   1
+; CHECK-NEXT:         .long   ($tryMap$main)@IMGREL
+; CHECK-NEXT:         .long   3
+; CHECK-NEXT:         .long   ($ip2state$main)@IMGREL
+; CHECK-NEXT:         .long   40
+; CHECK-NEXT:         .long   0
+; CHECK-NEXT:         .long   1
+
+; Make sure we get the right frame escape label.
+
+; CHECK: $handlerMap$0$main:
+; CHECK-NEXT:         .long   0
+; CHECK-NEXT:         .long   "??_R0H@8"@IMGREL
+; CHECK-NEXT:         .long   .Lmain$frame_escape_0
+; CHECK-NEXT:         .long   main.catch@IMGREL
+; CHECK-NEXT:         .long   .Lmain.catch$parent_frame_offset
+
+; Function Attrs: nounwind readnone
+declare void @llvm.donothing() #2
+
+; Function Attrs: nounwind
+declare void @llvm.frameescape(...) #3
+
+; Function Attrs: nounwind readnone
+declare i8* @llvm.framerecover(i8*, i8*, i32) #2
+
+attributes #0 = { noreturn uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" "wineh-parent"="main" }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind }
+attributes #4 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #5 = { "wineh-parent"="main" }
+attributes #6 = { noreturn }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 "}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"int", !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C/C++ TBAA"}
+
diff --git a/test/CodeGen/WinEH/cppeh-prepared-catch.ll b/test/CodeGen/WinEH/cppeh-prepared-catch.ll
new file mode 100644
index 000000000000..e7aaca86a882
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-prepared-catch.ll
@@ -0,0 +1,210 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+; This test case is equivalent to:
+; void f() {
+;   try {
+;     try {
+;       may_throw();
+;     } catch (int &) {
+;       may_throw();
+;     }
+;     may_throw();
+;   } catch (double) {
+;   }
+; }
+
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+%eh.CatchHandlerType = type { i32, i8* }
+
+$"\01??_R0N@8" = comdat any
+
+$"\01??_R0H@8" = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0N@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".N\00" }, comdat
+@llvm.eh.handlertype.N.0 = private unnamed_addr constant %eh.CatchHandlerType { i32 0, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0N@8" to i8*) }, section "llvm.metadata"
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+@llvm.eh.handlertype.H.8 = private unnamed_addr constant %eh.CatchHandlerType { i32 8, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*) }, section "llvm.metadata"
+
+define internal i8* @"\01?f@@YAXXZ.catch"(i8*, i8*) #4 {
+entry:
+  %.i8 = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?f@@YAXXZ" to i8*), i8* %1, i32 0)
+  %bc2 = bitcast i8* %.i8 to i32**
+  %bc3 = bitcast i32** %bc2 to i8*
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %invoke.cont2 unwind label %lpad1
+
+invoke.cont2:                                     ; preds = %entry
+  ret i8* blockaddress(@"\01?f@@YAXXZ", %try.cont)
+
+lpad1:                                            ; preds = %entry
+  %lp4 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.N.0
+  %recover = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.N.0 to i8*), i32 1, i8* (i8*, i8*)* @"\01?f@@YAXXZ.catch1")
+  indirectbr i8* %recover, [label %invoke.cont2]
+}
+
+; CHECK-LABEL: "?f@@YAXXZ.catch":
+; No code should be generated for the indirectbr.
+; CHECK-NOT: jmpq *
+; CHECK:        .seh_handlerdata
+; CHECK:        .long   ("$cppxdata$?f@@YAXXZ")@IMGREL
+
+
+define internal i8* @"\01?f@@YAXXZ.catch1"(i8*, i8*) #4 {
+entry:
+  %.i8 = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?f@@YAXXZ" to i8*), i8* %1, i32 1)
+  %2 = bitcast i8* %.i8 to double*
+  %3 = bitcast double* %2 to i8*
+  invoke void (...) @llvm.donothing()
+          to label %done unwind label %lpad
+
+done:
+  ret i8* blockaddress(@"\01?f@@YAXXZ", %try.cont8)
+
+lpad:                                             ; preds = %entry
+  %4 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %recover = call i8* (...) @llvm.eh.actions()
+  unreachable
+}
+
+; CHECK-LABEL: "?f@@YAXXZ.catch1":
+; No code should be generated for the indirectbr.
+; CHECK-NOT: jmpq *
+; CHECK: ".L?f@@YAXXZ.catch1$parent_frame_offset" = 16
+; CHECK:         movq    %rdx, 16(%rsp)
+; CHECK:        .seh_handlerdata
+; CHECK:        .long   ("$cppxdata$?f@@YAXXZ")@IMGREL
+
+define void @"\01?f@@YAXXZ"() #0 {
+entry:
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  %0 = alloca i32*, align 8
+  %1 = alloca double, align 8
+  call void (...) @llvm.frameescape(i32** %0, double* %1)
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %invoke.cont unwind label %lpad2
+
+invoke.cont:                                      ; preds = %entry
+  br label %try.cont
+
+lpad2:                                            ; preds = %entry
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.H.8
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.N.0
+  %recover = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.8 to i8*), i32 0, i8* (i8*, i8*)* @"\01?f@@YAXXZ.catch", i32 1, i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.N.0 to i8*), i32 1, i8* (i8*, i8*)* @"\01?f@@YAXXZ.catch1")
+  indirectbr i8* %recover, [label %try.cont, label %try.cont8]
+
+try.cont:                                         ; preds = %lpad2, %invoke.cont
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %try.cont8 unwind label %lpad1
+
+lpad1:
+  %3 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.N.0
+  %recover2 = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.N.0 to i8*), i32 1, i8* (i8*, i8*)* @"\01?f@@YAXXZ.catch1")
+  indirectbr i8* %recover2, [label %try.cont8]
+
+try.cont8:                                        ; preds = %lpad2, %try.cont
+  ret void
+}
+
+; CHECK-LABEL: "?f@@YAXXZ":
+; No code should be generated for the indirectbr.
+; CHECK-NOT: jmpq *
+; CHECK:             .seh_handlerdata
+; CHECK-NEXT:        .long   ("$cppxdata$?f@@YAXXZ")@IMGREL
+; CHECK-NEXT:"$cppxdata$?f@@YAXXZ":
+; CHECK-NEXT:        .long   429065506
+; CHECK-NEXT:        .long   4
+; CHECK-NEXT:        .long   ("$stateUnwindMap$?f@@YAXXZ")@IMGREL
+; CHECK-NEXT:        .long   2
+; CHECK-NEXT:        .long   ("$tryMap$?f@@YAXXZ")@IMGREL
+; CHECK-NEXT:        .long   6
+; CHECK-NEXT:        .long   ("$ip2state$?f@@YAXXZ")@IMGREL
+; CHECK-NEXT:        .long   32
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   1
+; CHECK-NEXT:"$stateUnwindMap$?f@@YAXXZ":
+; CHECK-NEXT:        .long   -1
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   -1
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:"$tryMap$?f@@YAXXZ":
+; CHECK-NEXT:        .long   1
+; CHECK-NEXT:        .long   1
+; CHECK-NEXT:        .long   2
+; CHECK-NEXT:        .long   1
+; CHECK-NEXT:        .long   ("$handlerMap$0$?f@@YAXXZ")@IMGREL
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   2
+; CHECK-NEXT:        .long   3
+; CHECK-NEXT:        .long   1
+; CHECK-NEXT:        .long   ("$handlerMap$1$?f@@YAXXZ")@IMGREL
+; CHECK-NEXT:"$handlerMap$0$?f@@YAXXZ":
+; CHECK-NEXT:        .long   8
+; CHECK-NEXT:        .long   "??_R0H@8"@IMGREL
+; CHECK-NEXT:        .long   ".L?f@@YAXXZ$frame_escape_0"
+; CHECK-NEXT:        .long   "?f@@YAXXZ.catch"@IMGREL
+; CHECK-NEXT:        .long   ".L?f@@YAXXZ.catch$parent_frame_offset"
+; CHECK-NEXT:"$handlerMap$1$?f@@YAXXZ":
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   "??_R0N@8"@IMGREL
+; CHECK-NEXT:        .long   ".L?f@@YAXXZ$frame_escape_1"
+; CHECK-NEXT:        .long   "?f@@YAXXZ.catch1"@IMGREL
+; CHECK-NEXT:        .long   ".L?f@@YAXXZ.catch1$parent_frame_offset"
+; CHECK-NEXT:"$ip2state$?f@@YAXXZ":
+; CHECK-NEXT:        .long   .Lfunc_begin0@IMGREL
+; CHECK-NEXT:        .long   2
+; CHECK-NEXT:        .long   .Ltmp0@IMGREL
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   .Lfunc_begin1@IMGREL
+; CHECK-NEXT:        .long   3
+; CHECK-NEXT:        .long   .Lfunc_begin2@IMGREL
+; CHECK-NEXT:        .long   -1
+; CHECK-NEXT:        .long   .Ltmp13@IMGREL
+; CHECK-NEXT:        .long   1
+; CHECK-NEXT:        .long   .Ltmp16@IMGREL
+; CHECK-NEXT:        .long   0
+
+
+declare void @"\01?may_throw@@YAXXZ"() #1
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #2
+
+; Function Attrs: nounwind
+declare void @llvm.eh.begincatch(i8* nocapture, i8* nocapture) #3
+
+; Function Attrs: nounwind
+declare void @llvm.eh.endcatch() #3
+
+; Function Attrs: nounwind
+declare i8* @llvm.eh.actions(...) #3
+
+; Function Attrs: nounwind
+declare void @llvm.frameescape(...) #3
+
+; Function Attrs: nounwind readnone
+declare i8* @llvm.framerecover(i8*, i8*, i32) #2
+
+declare void @llvm.donothing(...)
+
+attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" "wineh-parent"="
?f@@YAXXZ" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind }
+attributes #4 = { "wineh-parent"="
?f@@YAXXZ" }
diff --git a/test/CodeGen/WinEH/cppeh-prepared-cleanups.ll b/test/CodeGen/WinEH/cppeh-prepared-cleanups.ll
new file mode 100644
index 000000000000..876cb53baba1
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-prepared-cleanups.ll
@@ -0,0 +1,243 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+%eh.CatchableType = type { i32, i32, i32, i32, i32, i32, i32 }
+%eh.CatchableTypeArray.1 = type { i32, [1 x i32] }
+%eh.ThrowInfo = type { i32, i32, i32, i32 }
+%struct.S = type { i8 }
+
+$"\01??_DS@@QEAA@XZ" = comdat any
+
+$"\01??_R0H@8" = comdat any
+
+$"_CT??_R0H@84" = comdat any
+
+$_CTA1H = comdat any
+
+$_TI1H = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+@__ImageBase = external constant i8
+@"_CT??_R0H@84" = linkonce_odr unnamed_addr constant %eh.CatchableType { i32 1, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32), i32 0, i32 -1, i32 0, i32 4, i32 0 }, section ".xdata", comdat
+@_CTA1H = linkonce_odr unnamed_addr constant %eh.CatchableTypeArray.1 { i32 1, [1 x i32] [i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableType* @"_CT??_R0H@84" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32)] }, section ".xdata", comdat
+@_TI1H = linkonce_odr unnamed_addr constant %eh.ThrowInfo { i32 0, i32 0, i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableTypeArray.1* @_CTA1H to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32) }, section ".xdata", comdat
+
+
+; CHECK-LABEL: "?test1@@YAXXZ":
+; CHECK:             .seh_handlerdata
+; CHECK-NEXT:        .long   ("$cppxdata$?test1@@YAXXZ")@IMGREL
+; CHECK-NEXT:"$cppxdata$?test1@@YAXXZ":
+; CHECK-NEXT:        .long   429065506
+; CHECK-NEXT:        .long   1
+; CHECK-NEXT:        .long   ("$stateUnwindMap$?test1@@YAXXZ")@IMGREL
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   2
+; CHECK-NEXT:        .long   ("$ip2state$?test1@@YAXXZ")@IMGREL
+; CHECK-NEXT:        .long   32
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   1
+; CHECK-NEXT:"$stateUnwindMap$?test1@@YAXXZ":
+; CHECK-NEXT:        .long   -1
+; CHECK-NEXT:        .long   "?test1@@YAXXZ.cleanup"@IMGREL
+; CHECK-NEXT:"$ip2state$?test1@@YAXXZ":
+; CHECK-NEXT:        .long   .Lfunc_begin0@IMGREL
+; CHECK-NEXT:        .long   -1
+; CHECK-NEXT:        .long   .Ltmp0@IMGREL
+; CHECK-NEXT:        .long   0
+
+define void @"\01?test1@@YAXXZ"() #0 {
+entry:
+  %unwindhelp = alloca i64
+  %tmp = alloca i32, align 4
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  store i32 0, i32* %tmp
+  %0 = bitcast i32* %tmp to i8*
+  call void (...) @llvm.frameescape()
+  store volatile i64 -2, i64* %unwindhelp
+  %1 = bitcast i64* %unwindhelp to i8*
+  call void @llvm.eh.unwindhelp(i8* %1)
+  invoke void @_CxxThrowException(i8* %0, %eh.ThrowInfo* @_TI1H) #8
+          to label %unreachable unwind label %lpad1
+
+lpad1:                                            ; preds = %entry
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %recover = call i8* (...) @llvm.eh.actions(i32 0, void (i8*, i8*)* @"\01?test1@@YAXXZ.cleanup")
+  indirectbr i8* %recover, []
+
+unreachable:                                      ; preds = %entry
+  unreachable
+}
+
+declare void @_CxxThrowException(i8*, %eh.ThrowInfo*)
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind
+define linkonce_odr void @"\01??_DS@@QEAA@XZ"(%struct.S* %this) unnamed_addr #1 comdat align 2 {
+entry:
+  %this.addr = alloca %struct.S*, align 8
+  store %struct.S* %this, %struct.S** %this.addr, align 8
+  %this1 = load %struct.S*, %struct.S** %this.addr
+  call void @"\01??1S@@QEAA@XZ"(%struct.S* %this1) #4
+  ret void
+}
+
+; CHECK-LABEL: "?test2@@YAX_N@Z":
+; CHECK:             .seh_handlerdata
+; CHECK-NEXT:        .long   ("$cppxdata$?test2@@YAX_N@Z")@IMGREL
+; CHECK-NEXT:"$cppxdata$?test2@@YAX_N@Z":
+; CHECK-NEXT:        .long   429065506
+; CHECK-NEXT:        .long   2
+; CHECK-NEXT:        .long   ("$stateUnwindMap$?test2@@YAX_N@Z")@IMGREL
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   4
+; CHECK-NEXT:        .long   ("$ip2state$?test2@@YAX_N@Z")@IMGREL
+; CHECK-NEXT:        .long   40
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   1
+; CHECK-NEXT:"$stateUnwindMap$?test2@@YAX_N@Z":
+; CHECK-NEXT:        .long   -1
+; CHECK-NEXT:        .long   "?test2@@YAX_N@Z.cleanup"@IMGREL
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   "?test2@@YAX_N@Z.cleanup1"@IMGREL
+; CHECK-NEXT:"$ip2state$?test2@@YAX_N@Z":
+; CHECK-NEXT:        .long   .Lfunc_begin1@IMGREL
+; CHECK-NEXT:        .long   -1
+; CHECK-NEXT:        .long   .Ltmp7@IMGREL
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   .Ltmp9@IMGREL
+; CHECK-NEXT:        .long   1
+; CHECK-NEXT:        .long   .Ltmp12@IMGREL
+; CHECK-NEXT:        .long   0
+
+define void @"\01?test2@@YAX_N@Z"(i1 zeroext %b) #2 {
+  %b.addr = alloca i8, align 1
+  %s = alloca %struct.S, align 1
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  %s1 = alloca %struct.S, align 1
+  %frombool = zext i1 %b to i8
+  store i8 %frombool, i8* %b.addr, align 1
+  call void (...) @llvm.frameescape(%struct.S* %s, %struct.S* %s1)
+  call void @"\01?may_throw@@YAXXZ"()
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %invoke.cont unwind label %lpad1
+
+invoke.cont:                                      ; preds = %entry
+  %1 = load i8, i8* %b.addr, align 1
+  %tobool = trunc i8 %1 to i1
+  br i1 %tobool, label %if.then, label %if.else
+
+if.then:                                          ; preds = %invoke.cont
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %invoke.cont3 unwind label %lpad3
+
+invoke.cont3:                                     ; preds = %if.then
+  call void @"\01??_DS@@QEAA@XZ"(%struct.S* %s1) #4
+  br label %if.end
+
+lpad1:                                            ; preds = %entry, %if.end
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %recover = call i8* (...) @llvm.eh.actions(i32 0, void (i8*, i8*)* @"\01?test2@@YAX_N@Z.cleanup")
+  indirectbr i8* %recover, []
+
+lpad3:                                            ; preds = %if.then
+  %3 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %recover4 = call i8* (...) @llvm.eh.actions(i32 0, void (i8*, i8*)* @"\01?test2@@YAX_N@Z.cleanup1", i32 0, void (i8*, i8*)* @"\01?test2@@YAX_N@Z.cleanup")
+  indirectbr i8* %recover4, []
+
+if.else:                                          ; preds = %invoke.cont
+  call void @"\01?dont_throw@@YAXXZ"() #4
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %invoke.cont3
+  invoke void @"\01?may_throw@@YAXXZ"()
+          to label %invoke.cont4 unwind label %lpad1
+
+invoke.cont4:                                     ; preds = %if.end
+  call void @"\01??_DS@@QEAA@XZ"(%struct.S* %s) #4
+  ret void
+}
+
+declare void @"\01?may_throw@@YAXXZ"() #3
+
+; Function Attrs: nounwind
+declare void @"\01?dont_throw@@YAXXZ"() #1
+
+; Function Attrs: nounwind
+declare void @"\01??1S@@QEAA@XZ"(%struct.S*) #1
+
+; Function Attrs: nounwind
+declare i8* @llvm.eh.actions(...) #4
+
+define internal void @"\01?test1@@YAXXZ.cleanup"(i8*, i8*) #5 {
+entry:
+  %s = alloca %struct.S, align 1
+  call void @"\01??_DS@@QEAA@XZ"(%struct.S* %s) #4
+  ret void
+}
+
+; Function Attrs: nounwind
+declare void @llvm.frameescape(...) #4
+
+; Function Attrs: nounwind readnone
+declare i8* @llvm.framerecover(i8*, i8*, i32) #6
+
+; Function Attrs: nounwind
+declare void @llvm.eh.unwindhelp(i8*) #4
+
+define internal void @"\01?test2@@YAX_N@Z.cleanup"(i8*, i8*) #7 {
+entry:
+  %s.i8 = call i8* @llvm.framerecover(i8* bitcast (void (i1)* @"\01?test2@@YAX_N@Z" to i8*), i8* %1, i32 0)
+  %s = bitcast i8* %s.i8 to %struct.S*
+  call void @"\01??_DS@@QEAA@XZ"(%struct.S* %s) #4
+  invoke void @llvm.donothing()
+          to label %entry.split unwind label %stub
+
+entry.split:                                      ; preds = %entry
+  ret void
+
+stub:                                             ; preds = %entry
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  unreachable
+}
+
+define internal void @"\01?test2@@YAX_N@Z.cleanup1"(i8*, i8*) #7 {
+entry:
+  %s1.i8 = call i8* @llvm.framerecover(i8* bitcast (void (i1)* @"\01?test2@@YAX_N@Z" to i8*), i8* %1, i32 1)
+  %s1 = bitcast i8* %s1.i8 to %struct.S*
+  call void @"\01??_DS@@QEAA@XZ"(%struct.S* %s1) #4
+  invoke void @llvm.donothing()
+          to label %entry.split unwind label %stub
+
+entry.split:                                      ; preds = %entry
+  ret void
+
+stub:                                             ; preds = %entry
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  unreachable
+}
+
+declare void @llvm.donothing()
+
+attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" "wineh-parent"="
?test1@@YAXXZ" }
+attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" "wineh-parent"="
?test2@@YAX_N@Z" }
+attributes #3 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #4 = { nounwind }
+attributes #5 = { "wineh-parent"="
?test1@@YAXXZ" }
+attributes #6 = { nounwind readnone }
+attributes #7 = { "wineh-parent"="
?test2@@YAX_N@Z" }
+attributes #8 = { noreturn }
diff --git a/test/CodeGen/WinEH/cppeh-shared-empty-catch.ll b/test/CodeGen/WinEH/cppeh-shared-empty-catch.ll
new file mode 100644
index 000000000000..dd99a092b201
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-shared-empty-catch.ll
@@ -0,0 +1,110 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test is based on the following source, built with -O2
+;
+; void f() {
+;   try {
+;     g();
+;     try {
+;       throw;
+;     } catch (int) {
+;     }
+;   } catch (...) {
+;   }
+; }
+;
+
+; ModuleID = '<stdin>'
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+%eh.CatchHandlerType = type { i32, i8* }
+%eh.ThrowInfo = type { i32, i32, i32, i32 }
+
+$"\01??_R0H@8" = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+@llvm.eh.handlertype.H.0 = private unnamed_addr constant %eh.CatchHandlerType { i32 0, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*) }, section "llvm.metadata"
+
+; CHECK-LABEL: define void @"\01?f@@YAXXZ"()
+; CHECK: entry:
+; CHECK:   call void (...) @llvm.frameescape()
+; CHECK:   invoke void @"\01?g@@YAXXZ"()
+
+; Function Attrs: nounwind
+define void @"\01?f@@YAXXZ"() #0 {
+entry:
+  invoke void @"\01?g@@YAXXZ"()
+          to label %invoke.cont unwind label %lpad
+
+; CHECK-LABEL: invoke.cont:
+; CHECK:   invoke void @_CxxThrowException(i8* null, %eh.ThrowInfo* null)
+; CHECK:           to label %unreachable unwind label %[[LPAD1_LABEL:lpad[0-9]+]]
+
+invoke.cont:                                      ; preds = %entry
+  invoke void @_CxxThrowException(i8* null, %eh.ThrowInfo* null) #4
+          to label %unreachable unwind label %lpad1
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* null
+  %1 = extractvalue { i8*, i32 } %0, 0
+  br label %catch2
+
+; Note: Even though this landing pad has two catch clauses, it only has one action because both
+;       handlers do the same thing.
+; CHECK: [[LPAD1_LABEL]]:
+; CHECK:   landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+; CHECK-NEXT:           catch %eh.CatchHandlerType* @llvm.eh.handlertype.H.0
+; CHECK-NEXT:           catch i8* null
+; CHECK-NEXT:   [[RECOVER:\%.+]] = call i8* (...) @llvm.eh.actions(i32 1, i8* null, i32 -1, i8* (i8*, i8*)* @"\01?f@@YAXXZ.catch")
+; CHECK-NEXT:   indirectbr i8* [[RECOVER]], [label %try.cont4]
+
+lpad1:                                            ; preds = %invoke.cont
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.H.0
+          catch i8* null
+  %3 = extractvalue { i8*, i32 } %2, 0
+  br label %catch2
+
+catch2:                                           ; preds = %lpad1, %lpad
+  %exn.slot.0 = phi i8* [ %3, %lpad1 ], [ %1, %lpad ]
+  tail call void @llvm.eh.begincatch(i8* %exn.slot.0, i8* null) #3
+  tail call void @llvm.eh.endcatch() #3
+  br label %try.cont4
+
+try.cont4:                                        ; preds = %catch, %catch2
+  ret void
+
+unreachable:                                      ; preds = %invoke.cont
+  unreachable
+
+; CHECK: }
+}
+
+declare void @"\01?g@@YAXXZ"() #1
+
+declare i32 @__CxxFrameHandler3(...)
+
+declare void @_CxxThrowException(i8*, %eh.ThrowInfo*)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #2
+
+; Function Attrs: nounwind
+declare void @llvm.eh.begincatch(i8* nocapture, i8* nocapture) #3
+
+; Function Attrs: nounwind
+declare void @llvm.eh.endcatch() #3
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind }
+attributes #4 = { noreturn }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 235112) (llvm/trunk 235121)"}
diff --git a/test/CodeGen/WinEH/cppeh-similar-catch-blocks.ll b/test/CodeGen/WinEH/cppeh-similar-catch-blocks.ll
new file mode 100644
index 000000000000..81ee4542062d
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-similar-catch-blocks.ll
@@ -0,0 +1,394 @@
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -winehprepare -S -o - < %s | FileCheck %s
+
+; This test is based on the following code:
+;
+; int main(void) {
+;   try {
+;     try {
+;       throw 'a';
+;     } catch (char c) {
+;       printf("%c\n", c);
+;     }
+;     throw 1;
+;   } catch(int x) {
+;     printf("%d\n", x);
+;   } catch(...) {
+;     printf("...\n");
+;   }
+;   try {
+;     try {
+;       throw 'b';
+;     } catch (char c) {
+;       printf("%c\n", c);
+;     }
+;     throw 2;
+;   } catch(int x) {
+;     printf("%d\n", x);
+;   } catch (char c) {
+;     printf("%c\n", c);
+;   } catch(...) {
+;     printf("...\n");
+;   }
+;   return 0;
+; }
+
+; This test is just checking for failures in processing the IR.
+; Extensive handler matching is not required.
+
+; ModuleID = 'cppeh-similar-catch-blocks.cpp'
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+%eh.CatchHandlerType = type { i32, i8* }
+%eh.CatchableType = type { i32, i32, i32, i32, i32, i32, i32 }
+%eh.CatchableTypeArray.1 = type { i32, [1 x i32] }
+%eh.ThrowInfo = type { i32, i32, i32, i32 }
+
+$"\01??_R0H@8" = comdat any
+
+$"\01??_R0D@8" = comdat any
+
+$"_CT??_R0D@81" = comdat any
+
+$_CTA1D = comdat any
+
+$_TI1D = comdat any
+
+$"\01??_C@_03PJCJOCBM@?$CFc?6?$AA@" = comdat any
+
+$"_CT??_R0H@84" = comdat any
+
+$_CTA1H = comdat any
+
+$_TI1H = comdat any
+
+$"\01??_C@_04MPPNMCOK@?4?4?4?6?$AA@" = comdat any
+
+$"\01??_C@_03PMGGPEJJ@?$CFd?6?$AA@" = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+@llvm.eh.handlertype.H.0 = private unnamed_addr constant %eh.CatchHandlerType { i32 0, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*) }, section "llvm.metadata"
+@"\01??_R0D@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".D\00" }, comdat
+@llvm.eh.handlertype.D.0 = private unnamed_addr constant %eh.CatchHandlerType { i32 0, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0D@8" to i8*) }, section "llvm.metadata"
+@__ImageBase = external constant i8
+@"_CT??_R0D@81" = linkonce_odr unnamed_addr constant %eh.CatchableType { i32 1, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor2* @"\01??_R0D@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32), i32 0, i32 -1, i32 0, i32 1, i32 0 }, section ".xdata", comdat
+@_CTA1D = linkonce_odr unnamed_addr constant %eh.CatchableTypeArray.1 { i32 1, [1 x i32] [i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableType* @"_CT??_R0D@81" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32)] }, section ".xdata", comdat
+@_TI1D = linkonce_odr unnamed_addr constant %eh.ThrowInfo { i32 0, i32 0, i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableTypeArray.1* @_CTA1D to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32) }, section ".xdata", comdat
+@"\01??_C@_03PJCJOCBM@?$CFc?6?$AA@" = linkonce_odr unnamed_addr constant [4 x i8] c"%c\0A\00", comdat, align 1
+@"_CT??_R0H@84" = linkonce_odr unnamed_addr constant %eh.CatchableType { i32 1, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32), i32 0, i32 -1, i32 0, i32 4, i32 0 }, section ".xdata", comdat
+@_CTA1H = linkonce_odr unnamed_addr constant %eh.CatchableTypeArray.1 { i32 1, [1 x i32] [i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableType* @"_CT??_R0H@84" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32)] }, section ".xdata", comdat
+@_TI1H = linkonce_odr unnamed_addr constant %eh.ThrowInfo { i32 0, i32 0, i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableTypeArray.1* @_CTA1H to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32) }, section ".xdata", comdat
+@"\01??_C@_04MPPNMCOK@?4?4?4?6?$AA@" = linkonce_odr unnamed_addr constant [5 x i8] c"...\0A\00", comdat, align 1
+@"\01??_C@_03PMGGPEJJ@?$CFd?6?$AA@" = linkonce_odr unnamed_addr constant [4 x i8] c"%d\0A\00", comdat, align 1
+
+; This is just a minimal check to verify that main was handled by WinEHPrepare.
+; CHECK: define i32 @main()
+; CHECK: entry:
+; CHECK:   call void (...) @llvm.frameescape(i32* [[X_PTR:\%.+]], i32* [[X2_PTR:\%.+]], i8* [[C2_PTR:\%.+]], i8* [[C3_PTR:\%.+]], i8* [[C_PTR:\%.+]])
+; CHECK:   invoke void @_CxxThrowException
+; CHECK: }
+
+; Function Attrs: uwtable
+define i32 @main() #0 {
+entry:
+  %retval = alloca i32, align 4
+  %tmp = alloca i8, align 1
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  %c = alloca i8, align 1
+  %tmp3 = alloca i32, align 4
+  %x = alloca i32, align 4
+  %tmp20 = alloca i8, align 1
+  %c28 = alloca i8, align 1
+  %tmp34 = alloca i32, align 4
+  %c48 = alloca i8, align 1
+  %x56 = alloca i32, align 4
+  store i32 0, i32* %retval
+  store i8 97, i8* %tmp
+  invoke void @_CxxThrowException(i8* %tmp, %eh.ThrowInfo* @_TI1D) #4
+          to label %unreachable unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.D.0
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.H.0
+          catch i8* null
+  %1 = extractvalue { i8*, i32 } %0, 0
+  store i8* %1, i8** %exn.slot
+  %2 = extractvalue { i8*, i32 } %0, 1
+  store i32 %2, i32* %ehselector.slot
+  br label %catch.dispatch
+
+catch.dispatch:                                   ; preds = %lpad
+  %sel = load i32, i32* %ehselector.slot
+  %3 = call i32 @llvm.eh.typeid.for(i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.D.0 to i8*)) #2
+  %matches = icmp eq i32 %sel, %3
+  br i1 %matches, label %catch, label %catch.dispatch5
+
+catch:                                            ; preds = %catch.dispatch
+  %exn = load i8*, i8** %exn.slot
+  call void @llvm.eh.begincatch(i8* %exn, i8* %c) #2
+  %4 = load i8, i8* %c, align 1
+  %conv = sext i8 %4 to i32
+  %call = invoke i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01??_C@_03PJCJOCBM@?$CFc?6?$AA@", i32 0, i32 0), i32 %conv)
+          to label %invoke.cont unwind label %lpad2
+
+invoke.cont:                                      ; preds = %catch
+  call void @llvm.eh.endcatch() #2
+  br label %try.cont
+
+try.cont:                                         ; preds = %invoke.cont
+  store i32 1, i32* %tmp3
+  %5 = bitcast i32* %tmp3 to i8*
+  invoke void @_CxxThrowException(i8* %5, %eh.ThrowInfo* @_TI1H) #4
+          to label %unreachable unwind label %lpad4
+
+lpad2:                                            ; preds = %catch
+  %6 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.H.0
+          catch i8* null
+  %7 = extractvalue { i8*, i32 } %6, 0
+  store i8* %7, i8** %exn.slot
+  %8 = extractvalue { i8*, i32 } %6, 1
+  store i32 %8, i32* %ehselector.slot
+  call void @llvm.eh.endcatch() #2
+  br label %catch.dispatch5
+
+lpad4:                                            ; preds = %try.cont
+  %9 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.H.0
+          catch i8* null
+  %10 = extractvalue { i8*, i32 } %9, 0
+  store i8* %10, i8** %exn.slot
+  %11 = extractvalue { i8*, i32 } %9, 1
+  store i32 %11, i32* %ehselector.slot
+  br label %catch.dispatch5
+
+catch.dispatch5:                                  ; preds = %lpad4, %lpad2, %catch.dispatch
+  %sel6 = load i32, i32* %ehselector.slot
+  %12 = call i32 @llvm.eh.typeid.for(i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*)) #2
+  %matches7 = icmp eq i32 %sel6, %12
+  br i1 %matches7, label %catch13, label %catch8
+
+catch13:                                          ; preds = %catch.dispatch5
+  %exn14 = load i8*, i8** %exn.slot
+  %13 = bitcast i32* %x to i8*
+  call void @llvm.eh.begincatch(i8* %exn14, i8* %13) #2
+  %14 = load i32, i32* %x, align 4
+  %call18 = invoke i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01??_C@_03PMGGPEJJ@?$CFd?6?$AA@", i32 0, i32 0), i32 %14)
+          to label %invoke.cont17 unwind label %lpad16
+
+invoke.cont17:                                    ; preds = %catch13
+  call void @llvm.eh.endcatch() #2
+  br label %try.cont19
+
+try.cont19:                                       ; preds = %invoke.cont17, %invoke.cont11
+  store i8 98, i8* %tmp20
+  invoke void @_CxxThrowException(i8* %tmp20, %eh.ThrowInfo* @_TI1D) #4
+          to label %unreachable unwind label %lpad21
+
+catch8:                                           ; preds = %catch.dispatch5
+  %exn9 = load i8*, i8** %exn.slot
+  call void @llvm.eh.begincatch(i8* %exn9, i8* null) #2
+  %call12 = invoke i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @"\01??_C@_04MPPNMCOK@?4?4?4?6?$AA@", i32 0, i32 0))
+          to label %invoke.cont11 unwind label %lpad10
+
+invoke.cont11:                                    ; preds = %catch8
+  call void @llvm.eh.endcatch() #2
+  br label %try.cont19
+
+lpad10:                                           ; preds = %catch8
+  %15 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %16 = extractvalue { i8*, i32 } %15, 0
+  store i8* %16, i8** %exn.slot
+  %17 = extractvalue { i8*, i32 } %15, 1
+  store i32 %17, i32* %ehselector.slot
+  call void @llvm.eh.endcatch() #2
+  br label %eh.resume
+
+lpad16:                                           ; preds = %catch13
+  %18 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %19 = extractvalue { i8*, i32 } %18, 0
+  store i8* %19, i8** %exn.slot
+  %20 = extractvalue { i8*, i32 } %18, 1
+  store i32 %20, i32* %ehselector.slot
+  call void @llvm.eh.endcatch() #2
+  br label %eh.resume
+
+lpad21:                                           ; preds = %try.cont19
+  %21 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.D.0 to i8*)
+          catch i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*)
+          catch i8* null
+  %22 = extractvalue { i8*, i32 } %21, 0
+  store i8* %22, i8** %exn.slot
+  %23 = extractvalue { i8*, i32 } %21, 1
+  store i32 %23, i32* %ehselector.slot
+  br label %catch.dispatch22
+
+catch.dispatch22:                                 ; preds = %lpad21
+  %sel23 = load i32, i32* %ehselector.slot
+  %24 = call i32 @llvm.eh.typeid.for(i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.D.0 to i8*)) #2
+  %matches24 = icmp eq i32 %sel23, %24
+  br i1 %matches24, label %catch25, label %catch.dispatch36
+
+catch25:                                          ; preds = %catch.dispatch22
+  %exn26 = load i8*, i8** %exn.slot
+  call void @llvm.eh.begincatch(i8* %exn26, i8* %c28) #2
+  %25 = load i8, i8* %c28, align 1
+  %conv29 = sext i8 %25 to i32
+  %call32 = invoke i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01??_C@_03PJCJOCBM@?$CFc?6?$AA@", i32 0, i32 0), i32 %conv29)
+          to label %invoke.cont31 unwind label %lpad30
+
+invoke.cont31:                                    ; preds = %catch25
+  call void @llvm.eh.endcatch() #2
+  br label %try.cont33
+
+try.cont33:                                       ; preds = %invoke.cont31
+  store i32 2, i32* %tmp34
+  %26 = bitcast i32* %tmp34 to i8*
+  invoke void @_CxxThrowException(i8* %26, %eh.ThrowInfo* @_TI1H) #4
+          to label %unreachable unwind label %lpad35
+
+lpad30:                                           ; preds = %catch25
+  %27 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*)
+          catch i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.D.0 to i8*)
+          catch i8* null
+  %28 = extractvalue { i8*, i32 } %27, 0
+  store i8* %28, i8** %exn.slot
+  %29 = extractvalue { i8*, i32 } %27, 1
+  store i32 %29, i32* %ehselector.slot
+  call void @llvm.eh.endcatch() #2
+  br label %catch.dispatch36
+
+lpad35:                                           ; preds = %try.cont33
+  %30 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*)
+          catch i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.D.0 to i8*)
+          catch i8* null
+  %31 = extractvalue { i8*, i32 } %30, 0
+  store i8* %31, i8** %exn.slot
+  %32 = extractvalue { i8*, i32 } %30, 1
+  store i32 %32, i32* %ehselector.slot
+  br label %catch.dispatch36
+
+catch.dispatch36:                                 ; preds = %lpad35, %lpad30, %catch.dispatch22
+  %sel37 = load i32, i32* %ehselector.slot
+  %33 = call i32 @llvm.eh.typeid.for(i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*)) #2
+  %matches38 = icmp eq i32 %sel37, %33
+  br i1 %matches38, label %catch53, label %catch.fallthrough
+
+catch53:                                          ; preds = %catch.dispatch36
+  %exn54 = load i8*, i8** %exn.slot
+  %34 = bitcast i32* %x56 to i8*
+  call void @llvm.eh.begincatch(i8* %exn54, i8* %34) #2
+  %35 = load i32, i32* %x56, align 4
+  %call59 = invoke i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01??_C@_03PMGGPEJJ@?$CFd?6?$AA@", i32 0, i32 0), i32 %35)
+          to label %invoke.cont58 unwind label %lpad57
+
+invoke.cont58:                                    ; preds = %catch53
+  call void @llvm.eh.endcatch() #2
+  br label %try.cont60
+
+try.cont60:                                       ; preds = %invoke.cont58, %invoke.cont51, %invoke.cont43
+  ret i32 0
+
+catch.fallthrough:                                ; preds = %catch.dispatch36
+  %36 = call i32 @llvm.eh.typeid.for(i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.D.0 to i8*)) #2
+  %matches39 = icmp eq i32 %sel37, %36
+  br i1 %matches39, label %catch45, label %catch40
+
+catch45:                                          ; preds = %catch.fallthrough
+  %exn46 = load i8*, i8** %exn.slot
+  call void @llvm.eh.begincatch(i8* %exn46, i8* %c48) #2
+  %37 = load i8, i8* %c48, align 1
+  %conv49 = sext i8 %37 to i32
+  %call52 = invoke i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01??_C@_03PJCJOCBM@?$CFc?6?$AA@", i32 0, i32 0), i32 %conv49)
+          to label %invoke.cont51 unwind label %lpad50
+
+invoke.cont51:                                    ; preds = %catch45
+  call void @llvm.eh.endcatch() #2
+  br label %try.cont60
+
+catch40:                                          ; preds = %catch.fallthrough
+  %exn41 = load i8*, i8** %exn.slot
+  call void @llvm.eh.begincatch(i8* %exn41, i8* null) #2
+  %call44 = invoke i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @"\01??_C@_04MPPNMCOK@?4?4?4?6?$AA@", i32 0, i32 0))
+          to label %invoke.cont43 unwind label %lpad42
+
+invoke.cont43:                                    ; preds = %catch40
+  call void @llvm.eh.endcatch() #2
+  br label %try.cont60
+
+lpad42:                                           ; preds = %catch40
+  %38 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %39 = extractvalue { i8*, i32 } %38, 0
+  store i8* %39, i8** %exn.slot
+  %40 = extractvalue { i8*, i32 } %38, 1
+  store i32 %40, i32* %ehselector.slot
+  call void @llvm.eh.endcatch() #2
+  br label %eh.resume
+
+lpad50:                                           ; preds = %catch45
+  %41 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %42 = extractvalue { i8*, i32 } %41, 0
+  store i8* %42, i8** %exn.slot
+  %43 = extractvalue { i8*, i32 } %41, 1
+  store i32 %43, i32* %ehselector.slot
+  call void @llvm.eh.endcatch() #2
+  br label %eh.resume
+
+lpad57:                                           ; preds = %catch53
+  %44 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %45 = extractvalue { i8*, i32 } %44, 0
+  store i8* %45, i8** %exn.slot
+  %46 = extractvalue { i8*, i32 } %44, 1
+  store i32 %46, i32* %ehselector.slot
+  call void @llvm.eh.endcatch() #2
+  br label %eh.resume
+
+eh.resume:                                        ; preds = %lpad57, %lpad50, %lpad42, %lpad16, %lpad10
+  %exn61 = load i8*, i8** %exn.slot
+  %sel62 = load i32, i32* %ehselector.slot
+  %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn61, 0
+  %lpad.val63 = insertvalue { i8*, i32 } %lpad.val, i32 %sel62, 1
+  resume { i8*, i32 } %lpad.val63
+
+unreachable:                                      ; preds = %try.cont33, %try.cont19, %try.cont, %entry
+  unreachable
+}
+
+declare void @_CxxThrowException(i8*, %eh.ThrowInfo*)
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #1
+
+; Function Attrs: nounwind
+declare void @llvm.eh.begincatch(i8* nocapture, i8* nocapture) #2
+
+declare i32 @printf(i8*, ...) #3
+
+; Function Attrs: nounwind
+declare void @llvm.eh.endcatch() #2
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind }
+attributes #3 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #4 = { noreturn }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 (trunk 235214) (llvm/trunk 235213)"}
diff --git a/test/CodeGen/WinEH/cppeh-state-calc-1.ll b/test/CodeGen/WinEH/cppeh-state-calc-1.ll
new file mode 100644
index 000000000000..3549b1d51dee
--- /dev/null
+++ b/test/CodeGen/WinEH/cppeh-state-calc-1.ll
@@ -0,0 +1,289 @@
+; RUN: llc < %s | FileCheck %s
+
+; This test was generated from the following code.
+;
+; void test() {
+;   try {
+;     try {
+;       try {
+;         two();
+;         throw 2;
+;       } catch (int x) {
+;         catch_two();
+;       }
+;       a();
+;       throw 'a';
+;     } catch (char c) {
+;       catch_a();
+;     }
+;     one();
+;     throw 1;
+;   } catch(int x) { 
+;     catch_one();
+;   } catch(...) {
+;     catch_all();
+;   }
+; }
+;
+; The function calls before the throws were declared as 'noexcept' and are
+; just here to make blocks easier to identify in the IR.
+
+; ModuleID = '<stdin>'
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
+%eh.CatchHandlerType = type { i32, i8* }
+%eh.CatchableType = type { i32, i32, i32, i32, i32, i32, i32 }
+%eh.CatchableTypeArray.1 = type { i32, [1 x i32] }
+%eh.ThrowInfo = type { i32, i32, i32, i32 }
+
+$"\01??_R0H@8" = comdat any
+
+$"\01??_R0D@8" = comdat any
+
+$"_CT??_R0H@84" = comdat any
+
+$_CTA1H = comdat any
+
+$_TI1H = comdat any
+
+$"_CT??_R0D@81" = comdat any
+
+$_CTA1D = comdat any
+
+$_TI1D = comdat any
+
+@"\01??_7type_info@@6B@" = external constant i8*
+@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat
+@llvm.eh.handlertype.H.0 = private unnamed_addr constant %eh.CatchHandlerType { i32 0, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i8*) }, section "llvm.metadata"
+@"\01??_R0D@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".D\00" }, comdat
+@llvm.eh.handlertype.D.0 = private unnamed_addr constant %eh.CatchHandlerType { i32 0, i8* bitcast (%rtti.TypeDescriptor2* @"\01??_R0D@8" to i8*) }, section "llvm.metadata"
+@__ImageBase = external constant i8
+@"_CT??_R0H@84" = linkonce_odr unnamed_addr constant %eh.CatchableType { i32 1, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor2* @"\01??_R0H@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32), i32 0, i32 -1, i32 0, i32 4, i32 0 }, section ".xdata", comdat
+@_CTA1H = linkonce_odr unnamed_addr constant %eh.CatchableTypeArray.1 { i32 1, [1 x i32] [i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableType* @"_CT??_R0H@84" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32)] }, section ".xdata", comdat
+@_TI1H = linkonce_odr unnamed_addr constant %eh.ThrowInfo { i32 0, i32 0, i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableTypeArray.1* @_CTA1H to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32) }, section ".xdata", comdat
+@"_CT??_R0D@81" = linkonce_odr unnamed_addr constant %eh.CatchableType { i32 1, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor2* @"\01??_R0D@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32), i32 0, i32 -1, i32 0, i32 1, i32 0 }, section ".xdata", comdat
+@_CTA1D = linkonce_odr unnamed_addr constant %eh.CatchableTypeArray.1 { i32 1, [1 x i32] [i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableType* @"_CT??_R0D@81" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32)] }, section ".xdata", comdat
+@_TI1D = linkonce_odr unnamed_addr constant %eh.ThrowInfo { i32 0, i32 0, i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableTypeArray.1* @_CTA1D to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32) }, section ".xdata", comdat
+
+; Function Attrs: nounwind uwtable
+define void @"\01?test@@YAXXZ"() #0 {
+entry:
+  %tmp = alloca i32, align 4
+  %x = alloca i32, align 4
+  %tmp2 = alloca i8, align 1
+  %c = alloca i8, align 1
+  %tmp11 = alloca i32, align 4
+  %x21 = alloca i32, align 4
+  call void @"\01?two@@YAXXZ"() #3
+  store i32 2, i32* %tmp
+  %0 = bitcast i32* %tmp to i8*
+  call void (...) @llvm.frameescape(i32* %x, i8* %c, i32* %x21)
+  invoke void @_CxxThrowException(i8* %0, %eh.ThrowInfo* @_TI1H) #5
+          to label %unreachable unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*)
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.D.0
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.H.0
+          catch i8* null
+  %recover = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*), i32 0, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch", i32 1, i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.D.0 to i8*), i32 1, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch1", i32 1, i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*), i32 2, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch2", i32 1, i8* null, i32 -1, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch3")
+  indirectbr i8* %recover, [label %try.cont, label %try.cont10, label %try.cont22]
+
+try.cont:                                         ; preds = %lpad
+  call void @"\01?a@@YAXXZ"() #3
+  store i8 97, i8* %tmp2
+  invoke void @_CxxThrowException(i8* %tmp2, %eh.ThrowInfo* @_TI1D) #5
+          to label %unreachable unwind label %lpad3
+
+lpad3:                                            ; preds = %try.cont
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.D.0
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.H.0
+          catch i8* null
+  %recover1 = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.D.0 to i8*), i32 1, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch1", i32 1, i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*), i32 2, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch2", i32 1, i8* null, i32 -1, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch3")
+  indirectbr i8* %recover1, [label %try.cont10, label %try.cont22]
+
+try.cont10:                                       ; preds = %lpad3, %lpad
+  call void @"\01?one@@YAXXZ"() #3
+  store i32 1, i32* %tmp11
+  %3 = bitcast i32* %tmp11 to i8*
+  invoke void @_CxxThrowException(i8* %3, %eh.ThrowInfo* @_TI1H) #5
+          to label %unreachable unwind label %lpad12
+
+lpad12:                                           ; preds = %try.cont10
+  %4 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          catch %eh.CatchHandlerType* @llvm.eh.handlertype.H.0
+          catch i8* null
+  %recover2 = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (%eh.CatchHandlerType* @llvm.eh.handlertype.H.0 to i8*), i32 2, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch2", i32 1, i8* null, i32 -1, i8* (i8*, i8*)* @"\01?test@@YAXXZ.catch3")
+  indirectbr i8* %recover2, [label %try.cont22]
+
+try.cont22:                                       ; preds = %lpad12, %lpad3, %lpad
+  ret void
+
+unreachable:                                      ; preds = %try.cont10, %try.cont, %entry
+  unreachable
+}
+
+; Function Attrs: nounwind
+declare void @"\01?two@@YAXXZ"() #1
+
+declare void @_CxxThrowException(i8*, %eh.ThrowInfo*)
+
+declare i32 @__CxxFrameHandler3(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #2
+
+; Function Attrs: nounwind
+declare void @llvm.eh.begincatch(i8* nocapture, i8* nocapture) #3
+
+; Function Attrs: nounwind
+declare void @"\01?catch_two@@YAXXZ"() #1
+
+; Function Attrs: nounwind
+declare void @llvm.eh.endcatch() #3
+
+; Function Attrs: nounwind
+declare void @"\01?a@@YAXXZ"() #1
+
+; Function Attrs: nounwind
+declare void @"\01?catch_a@@YAXXZ"() #1
+
+; Function Attrs: nounwind
+declare void @"\01?one@@YAXXZ"() #1
+
+; Function Attrs: nounwind
+declare void @"\01?catch_all@@YAXXZ"() #1
+
+; Function Attrs: nounwind
+declare void @"\01?catch_one@@YAXXZ"() #1
+
+; Function Attrs: nounwind
+declare i8* @llvm.eh.actions(...) #3
+
+define internal i8* @"\01?test@@YAXXZ.catch"(i8*, i8*) #4 {
+entry:
+  %x.i8 = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 0)
+  %x = bitcast i8* %x.i8 to i32*
+  %2 = bitcast i32* %x to i8*
+  call void @"\01?catch_two@@YAXXZ"() #3
+  invoke void @llvm.donothing()
+          to label %entry.split unwind label %stub
+
+entry.split:                                      ; preds = %entry
+  ret i8* blockaddress(@"\01?test@@YAXXZ", %try.cont)
+
+stub:                                             ; preds = %entry
+  %3 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %recover = call i8* (...) @llvm.eh.actions()
+  unreachable
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.donothing() #2
+
+define internal i8* @"\01?test@@YAXXZ.catch1"(i8*, i8*) #4 {
+entry:
+  call void @"\01?catch_a@@YAXXZ"() #3
+  invoke void @llvm.donothing()
+          to label %entry.split unwind label %stub
+
+entry.split:                                      ; preds = %entry
+  ret i8* blockaddress(@"\01?test@@YAXXZ", %try.cont10)
+
+stub:                                             ; preds = %entry
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %recover = call i8* (...) @llvm.eh.actions()
+  unreachable
+}
+
+define internal i8* @"\01?test@@YAXXZ.catch2"(i8*, i8*) #4 {
+entry:
+  %x21.i8 = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?test@@YAXXZ" to i8*), i8* %1, i32 2)
+  %x21 = bitcast i8* %x21.i8 to i32*
+  %2 = bitcast i32* %x21 to i8*
+  call void @"\01?catch_one@@YAXXZ"() #3
+  invoke void @llvm.donothing()
+          to label %entry.split unwind label %stub
+
+entry.split:                                      ; preds = %entry
+  ret i8* blockaddress(@"\01?test@@YAXXZ", %try.cont22)
+
+stub:                                             ; preds = %entry
+  %3 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %recover = call i8* (...) @llvm.eh.actions()
+  unreachable
+}
+
+define internal i8* @"\01?test@@YAXXZ.catch3"(i8*, i8*) #4 {
+entry:
+  call void @"\01?catch_all@@YAXXZ"() #3
+  invoke void @llvm.donothing()
+          to label %entry.split unwind label %stub
+
+entry.split:                                      ; preds = %entry
+  ret i8* blockaddress(@"\01?test@@YAXXZ", %try.cont22)
+
+stub:                                             ; preds = %entry
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+          cleanup
+  %recover = call i8* (...) @llvm.eh.actions()
+  unreachable
+}
+
+; Function Attrs: nounwind
+declare void @llvm.frameescape(...) #3
+
+; Function Attrs: nounwind readnone
+declare i8* @llvm.framerecover(i8*, i8*, i32) #2
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" "wineh-parent"="
?test@@YAXXZ" }
+attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind }
+attributes #4 = { "wineh-parent"="
?test@@YAXXZ" }
+attributes #5 = { noreturn }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 (trunk 236059)"}
+
+; CHECK-LABEL: "$cppxdata$?test@@YAXXZ":
+; CHECK-NEXT: 	.long	429065506
+; CHECK-NEXT: 	.long
+; CHECK-NEXT: 	.long	("$stateUnwindMap$?test@@YAXXZ")@IMGREL
+; CHECK-NEXT: 	.long
+; CHECK-NEXT: 	.long	("$tryMap$?test@@YAXXZ")@IMGREL
+; CHECK-NEXT: 	.long
+; CHECK-NEXT: 	.long	("$ip2state$?test@@YAXXZ")@IMGREL
+; CHECK-NEXT: 	.long	40
+; CHECK-NEXT: 	.long	0
+; CHECK-NEXT: 	.long	1
+; CHECK: "$stateUnwindMap$?test@@YAXXZ":
+; CHECK: "$tryMap$?test@@YAXXZ":
+; CHECK: "$handlerMap$0$?test@@YAXXZ":
+; CHECK: "$ip2state$?test@@YAXXZ":
+; CHECK-NEXT: 	.long	.Lfunc_begin0@IMGREL
+; CHECK-NEXT: 	.long	-1
+; CHECK-NEXT: 	.long	.Ltmp0@IMGREL
+; CHECK-NEXT: 	.long	2
+; CHECK-NEXT: 	.long	.Ltmp3@IMGREL
+; CHECK-NEXT: 	.long	1
+; CHECK-NEXT: 	.long	.Ltmp6@IMGREL
+; CHECK-NEXT: 	.long	0
+; CHECK-NEXT: 	.long	.Lfunc_begin1@IMGREL
+; CHECK-NEXT: 	.long	3
+; CHECK-NEXT: 	.long	.Lfunc_begin2@IMGREL
+; CHECK-NEXT: 	.long	4
+; CHECK-NEXT: 	.long	.Lfunc_begin3@IMGREL
+; CHECK-NEXT: 	.long	5
+; CHECK-NEXT: 	.long	.Lfunc_begin4@IMGREL
+; CHECK-NEXT: 	.long	6
diff --git a/test/CodeGen/WinEH/lit.local.cfg b/test/CodeGen/WinEH/lit.local.cfg
new file mode 100644
index 000000000000..67905d7e06e6
--- /dev/null
+++ b/test/CodeGen/WinEH/lit.local.cfg
@@ -0,0 +1,12 @@
+# FIXME: For now, override suffixes to exclude any .s tests, because some of the
+# buildbots have a stray misched-copy.s output file lying around that causes
+# failures. See misched-copy.s where we try and clean up that file.
+#
+# It should be possible to remove this override once all the bots have cycled
+# cleanly.
+config.suffixes = ['.ll', '.test', '.txt']
+
+# FIXME: Add Windows on ARM support to these tests.
+if not 'X86' in config.root.targets:
+    config.unsupported = True
+
diff --git a/test/CodeGen/WinEH/seh-catch-all.ll b/test/CodeGen/WinEH/seh-catch-all.ll
new file mode 100644
index 000000000000..c2a652b80990
--- /dev/null
+++ b/test/CodeGen/WinEH/seh-catch-all.ll
@@ -0,0 +1,59 @@
+; RUN: opt -S -winehprepare < %s | FileCheck %s
+
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+@str.__except = internal unnamed_addr constant [9 x i8] c"__except\00", align 1
+
+; Function Attrs: uwtable
+
+declare i32 @puts(i8*)
+
+define void @may_crash() {
+entry:
+  store volatile i32 42, i32* null, align 4
+  ret void
+}
+
+declare i32 @__C_specific_handler(...)
+
+; Function Attrs: nounwind readnone
+declare i8* @llvm.frameaddress(i32)
+
+; Function Attrs: uwtable
+define void @seh_catch_all() {
+entry:
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  invoke void @may_crash()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %entry
+  br label %__try.cont
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+          catch i8* null
+  %1 = extractvalue { i8*, i32 } %0, 0
+  store i8* %1, i8** %exn.slot
+  %2 = extractvalue { i8*, i32 } %0, 1
+  store i32 %2, i32* %ehselector.slot
+  br label %__except
+
+__except:                                         ; preds = %lpad
+  %call = call i32 @puts(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @str.__except, i32 0, i32 0))
+  br label %__try.cont
+
+__try.cont:                                       ; preds = %__except, %invoke.cont
+  ret void
+}
+
+; CHECK-LABEL: define void @seh_catch_all()
+; CHECK: landingpad
+; CHECK-NEXT: catch i8* null
+; CHECK-NEXT: call i8* (...) @llvm.eh.actions(i32 1, i8* null, i32 -1, i8* blockaddress(@seh_catch_all, %lpad.split))
+; CHECK-NEXT: indirectbr
+;
+; CHECK: lpad.split:
+; CHECK-NOT: extractvalue
+; CHECK: call i32 @puts
diff --git a/test/CodeGen/WinEH/seh-inlined-finally.ll b/test/CodeGen/WinEH/seh-inlined-finally.ll
new file mode 100644
index 000000000000..d2080cff79d4
--- /dev/null
+++ b/test/CodeGen/WinEH/seh-inlined-finally.ll
@@ -0,0 +1,83 @@
+; RUN: opt -S -winehprepare < %s | FileCheck %s
+
+; Check that things work when the mid-level optimizer inlines the finally
+; block.
+
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+%struct._RTL_CRITICAL_SECTION = type { %struct._RTL_CRITICAL_SECTION_DEBUG*, i32, i32, i8*, i8*, i64 }
+%struct._RTL_CRITICAL_SECTION_DEBUG = type { i16, i16, %struct._RTL_CRITICAL_SECTION*, %struct._LIST_ENTRY, i32, i32, i32, i16, i16 }
+%struct._LIST_ENTRY = type { %struct._LIST_ENTRY*, %struct._LIST_ENTRY* }
+
+declare i32 @puts(i8*)
+declare void @may_crash()
+declare i32 @__C_specific_handler(...)
+declare i8* @llvm.framerecover(i8*, i8*, i32) #1
+declare i8* @llvm.frameaddress(i32)
+declare void @llvm.frameescape(...)
+declare dllimport void @EnterCriticalSection(%struct._RTL_CRITICAL_SECTION*)
+declare dllimport void @LeaveCriticalSection(%struct._RTL_CRITICAL_SECTION*)
+
+define void @use_finally() {
+entry:
+  invoke void @may_crash()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %entry
+  %call.i = tail call i32 @puts(i8* null)
+  ret void
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+          cleanup
+  %call.i2 = tail call i32 @puts(i8* null)
+  resume { i8*, i32 } %0
+}
+
+; CHECK-LABEL: define void @use_finally()
+; CHECK: invoke void @may_crash()
+;
+; CHECK: landingpad
+; CHECK-NEXT: cleanup
+; CHECK-NEXT: call i8* (...) @llvm.eh.actions(i32 0, void (i8*, i8*)* @use_finally.cleanup)
+; CHECK-NEXT: indirectbr i8* %recover, []
+
+; Function Attrs: nounwind uwtable
+define i32 @call_may_crash_locked() {
+entry:
+  %p = alloca %struct._RTL_CRITICAL_SECTION, align 8
+  call void (...) @llvm.frameescape(%struct._RTL_CRITICAL_SECTION* %p)
+  call void @EnterCriticalSection(%struct._RTL_CRITICAL_SECTION* %p)
+  invoke void @may_crash()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %entry
+  %tmp2 = call i8* @llvm.frameaddress(i32 0)
+  %tmp3 = call i8* @llvm.framerecover(i8* bitcast (i32 ()* @call_may_crash_locked to i8*), i8* %tmp2, i32 0) #2
+  %tmp6 = bitcast i8* %tmp3 to %struct._RTL_CRITICAL_SECTION*
+  call void @LeaveCriticalSection(%struct._RTL_CRITICAL_SECTION* %tmp6)
+  ret i32 42
+
+lpad:                                             ; preds = %entry
+  %tmp7 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+            cleanup
+  %tmp8 = call i8* @llvm.frameaddress(i32 0)
+  %tmp9 = call i8* @llvm.framerecover(i8* bitcast (i32 ()* @call_may_crash_locked to i8*), i8* %tmp8, i32 0)
+  %tmp12 = bitcast i8* %tmp9 to %struct._RTL_CRITICAL_SECTION*
+  call void @LeaveCriticalSection(%struct._RTL_CRITICAL_SECTION* %tmp12)
+  resume { i8*, i32 } %tmp7
+}
+
+; CHECK-LABEL: define i32 @call_may_crash_locked()
+; CHECK: invoke void @may_crash()
+;
+; CHECK: landingpad
+; CHECK-NEXT: cleanup
+; CHECK-NEXT: call i8* (...) @llvm.eh.actions(i32 0, void (i8*, i8*)* @call_may_crash_locked.cleanup)
+; CHECK-NEXT: indirectbr i8* %recover, []
+
+; CHECK-LABEL: define internal void @call_may_crash_locked.cleanup(i8*, i8*)
+; CHECK: %tmp9 = call i8* @llvm.framerecover(i8* bitcast (i32 ()* @call_may_crash_locked to i8*), i8* %1, i32 0)
+; CHECK: %tmp12 = bitcast i8* %tmp9 to %struct._RTL_CRITICAL_SECTION*
+; CHECK: call void @LeaveCriticalSection(%struct._RTL_CRITICAL_SECTION* %tmp12)
diff --git a/test/CodeGen/WinEH/seh-outlined-finally.ll b/test/CodeGen/WinEH/seh-outlined-finally.ll
new file mode 100644
index 000000000000..19558b705308
--- /dev/null
+++ b/test/CodeGen/WinEH/seh-outlined-finally.ll
@@ -0,0 +1,155 @@
+; RUN: opt -S -winehprepare -mtriple=x86_64-windows-msvc < %s | FileCheck %s
+
+; Test case based on this code:
+;
+; extern "C" int _abnormal_termination();
+; #pragma intrinsic(_abnormal_termination)
+; extern "C" int printf(const char *, ...);
+; extern "C" void may_crash() {
+;   *(volatile int *)0 = 42;
+; }
+; int main() {
+;   int myres = 0;
+;   __try {
+;     __try {
+;       may_crash();
+;     } __finally {
+;       printf("inner finally %d\n", _abnormal_termination());
+;       may_crash();
+;     }
+;   } __finally {
+;     printf("outer finally %d\n", _abnormal_termination());
+;   }
+; }
+;
+; Note that if the inner finally crashes, the outer finally still runs. There
+; is nothing like a std::terminate call in this situation.
+
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+@str_outer_finally = linkonce_odr unnamed_addr constant [18 x i8] c"outer finally %d\0A\00", align 1
+@str_inner_finally = linkonce_odr unnamed_addr constant [18 x i8] c"inner finally %d\0A\00", align 1
+
+; Function Attrs: nounwind uwtable
+define void @may_crash() #0 {
+entry:
+  store volatile i32 42, i32* null, align 4
+  ret void
+}
+
+; Function Attrs: uwtable
+define i32 @main() #1 {
+entry:
+  %myres = alloca i32, align 4
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  store i32 0, i32* %myres, align 4
+  invoke void @may_crash() #4
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %entry
+  %0 = call i8* @llvm.frameaddress(i32 0)
+  invoke void @"\01?fin$1@0@main@@"(i1 zeroext false, i8* %0) #4
+          to label %invoke.cont2 unwind label %lpad1
+
+invoke.cont2:                                     ; preds = %invoke.cont
+  %1 = call i8* @llvm.frameaddress(i32 0)
+  call void @"\01?fin$0@0@main@@"(i1 zeroext false, i8* %1)
+  ret i32 0
+
+lpad:                                             ; preds = %entry
+  %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+          cleanup
+  %3 = extractvalue { i8*, i32 } %2, 0
+  store i8* %3, i8** %exn.slot
+  %4 = extractvalue { i8*, i32 } %2, 1
+  store i32 %4, i32* %ehselector.slot
+  %5 = call i8* @llvm.frameaddress(i32 0)
+  invoke void @"\01?fin$1@0@main@@"(i1 zeroext true, i8* %5) #4
+          to label %invoke.cont3 unwind label %lpad1
+
+lpad1:                                            ; preds = %lpad, %invoke.cont
+  %6 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+          cleanup
+  %7 = extractvalue { i8*, i32 } %6, 0
+  store i8* %7, i8** %exn.slot
+  %8 = extractvalue { i8*, i32 } %6, 1
+  store i32 %8, i32* %ehselector.slot
+  br label %ehcleanup
+
+invoke.cont3:                                     ; preds = %lpad
+  br label %ehcleanup
+
+ehcleanup:                                        ; preds = %invoke.cont3, %lpad1
+  %9 = call i8* @llvm.frameaddress(i32 0)
+  call void @"\01?fin$0@0@main@@"(i1 zeroext true, i8* %9)
+  br label %eh.resume
+
+eh.resume:                                        ; preds = %ehcleanup
+  %exn = load i8*, i8** %exn.slot
+  %sel = load i32, i32* %ehselector.slot
+  %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn, 0
+  %lpad.val4 = insertvalue { i8*, i32 } %lpad.val, i32 %sel, 1
+  resume { i8*, i32 } %lpad.val4
+}
+
+; CHECK-NOT: define internal void @
+
+; CHECK-LABEL: define i32 @main()
+; CHECK: invoke void @may_crash()
+;
+; CHECK: landingpad { i8*, i32 }
+; CHECK-NEXT: cleanup
+; CHECK-NEXT: call i8* (...) @llvm.eh.actions(i32 0, void (i1, i8*)* @"\01?fin$1@0@main@@", i32 0, void (i1, i8*)* @"\01?fin$0@0@main@@")
+; CHECK-NEXT: indirectbr
+;
+; CHECK: landingpad { i8*, i32 }
+; CHECK-NEXT: cleanup
+; CHECK-NEXT: call i8* (...) @llvm.eh.actions(i32 0, void (i1, i8*)* @"\01?fin$0@0@main@@")
+; CHECK-NEXT: indirectbr
+
+; There should not be any *new* cleanup helpers, just the existing ones.
+; CHECK-NOT: define internal void @
+; CHECK: define internal void @"\01?fin$0@0@main@@"(i1 zeroext %abnormal_termination, i8* %frame_pointer)
+; CHECK-NOT: define internal void @
+; CHECK: define internal void @"\01?fin$1@0@main@@"(i1 zeroext %abnormal_termination, i8* %frame_pointer)
+; CHECK-NOT: define internal void @
+
+define internal void @"\01?fin$0@0@main@@"(i1 zeroext %abnormal_termination, i8* %frame_pointer) #2 {
+entry:
+  %frame_pointer.addr = alloca i8*, align 8
+  %abnormal_termination.addr = alloca i8, align 1
+  store i8* %frame_pointer, i8** %frame_pointer.addr, align 8
+  %frombool = zext i1 %abnormal_termination to i8
+  store i8 %frombool, i8* %abnormal_termination.addr, align 1
+  %0 = zext i1 %abnormal_termination to i32
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([18 x i8], [18 x i8]* @str_outer_finally, i32 0, i32 0), i32 %0)
+  ret void
+}
+
+declare i32 @printf(i8*, ...) #2
+
+define internal void @"\01?fin$1@0@main@@"(i1 zeroext %abnormal_termination, i8* %frame_pointer) #2 {
+entry:
+  %frame_pointer.addr = alloca i8*, align 8
+  %abnormal_termination.addr = alloca i8, align 1
+  store i8* %frame_pointer, i8** %frame_pointer.addr, align 8
+  %frombool = zext i1 %abnormal_termination to i8
+  store i8 %frombool, i8* %abnormal_termination.addr, align 1
+  %0 = zext i1 %abnormal_termination to i32
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([18 x i8], [18 x i8]* @str_inner_finally, i32 0, i32 0), i32 %0)
+  call void @may_crash()
+  ret void
+}
+
+declare i32 @__C_specific_handler(...)
+
+; Function Attrs: nounwind readnone
+declare i8* @llvm.frameaddress(i32) #3
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { nounwind readnone }
+attributes #4 = { noinline }
diff --git a/test/CodeGen/WinEH/seh-prepared-basic.ll b/test/CodeGen/WinEH/seh-prepared-basic.ll
new file mode 100644
index 000000000000..880bb3c33a8d
--- /dev/null
+++ b/test/CodeGen/WinEH/seh-prepared-basic.ll
@@ -0,0 +1,83 @@
+; RUN: llc < %s | FileCheck %s
+
+; Test case based on this code:
+; extern "C" unsigned long _exception_code();
+; extern "C" int filt(unsigned long);
+; extern "C" void g();
+; extern "C" void do_except() {
+;   __try {
+;     g();
+;   } __except(filt(_exception_code())) {
+;   }
+; }
+
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+; Function Attrs: uwtable
+define void @do_except() #0 {
+entry:
+  call void (...) @llvm.frameescape()
+  invoke void @g() #5
+          to label %__try.cont unwind label %lpad1
+
+lpad1:                                            ; preds = %entry
+  %ehvals = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+          catch i8* bitcast (i32 (i8*, i8*)* @"\01?filt$0@0@do_except@@" to i8*)
+  %recover = call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (i32 (i8*, i8*)* @"\01?filt$0@0@do_except@@" to i8*), i32 -1, i8* blockaddress(@do_except, %__try.cont))
+  indirectbr i8* %recover, [label %__try.cont]
+
+__try.cont:                                       ; preds = %lpad1, %entry
+  ret void
+}
+
+; CHECK-LABEL: do_except:
+; CHECK: .seh_handler __C_specific_handler
+; CHECK-NOT: jmpq *
+; CHECK: .seh_handlerdata
+; CHECK-NEXT: .long 1
+; CHECK-NEXT: .long .Ltmp{{.*}}
+; CHECK-NEXT: .long .Ltmp{{.*}}
+; CHECK-NEXT: .long "?filt$0@0@do_except@@"@IMGREL
+; CHECK-NEXT: .long .Ltmp{{.*}}@IMGREL
+
+; Function Attrs: noinline nounwind
+define internal i32 @"\01?filt$0@0@do_except@@"(i8* nocapture readonly %exception_pointers, i8* nocapture readnone %frame_pointer) #1 {
+entry:
+  %0 = bitcast i8* %exception_pointers to i32**
+  %1 = load i32*, i32** %0, align 8
+  %2 = load i32, i32* %1, align 4
+  %call = tail call i32 @filt(i32 %2) #4
+  ret i32 %call
+}
+
+declare i32 @filt(i32) #2
+
+declare void @g() #2
+
+declare i32 @__C_specific_handler(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #3
+
+; Function Attrs: nounwind
+declare i8* @llvm.eh.actions(...) #4
+
+; Function Attrs: nounwind
+declare void @llvm.frameescape(...) #4
+
+; Function Attrs: nounwind readnone
+declare i8* @llvm.framerecover(i8*, i8*, i32) #3
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" "wineh-parent"="do_except" }
+attributes #1 = { noinline nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { nounwind readnone }
+attributes #4 = { nounwind }
+attributes #5 = { noinline }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 "}
diff --git a/test/CodeGen/WinEH/seh-resume-phi.ll b/test/CodeGen/WinEH/seh-resume-phi.ll
new file mode 100644
index 000000000000..256dd852d287
--- /dev/null
+++ b/test/CodeGen/WinEH/seh-resume-phi.ll
@@ -0,0 +1,66 @@
+; RUN: opt -S -winehprepare < %s | FileCheck %s
+
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+declare void @might_crash(i8* %ehptr)
+declare i32 @filt()
+declare void @cleanup()
+declare i32 @__C_specific_handler(...)
+declare i32 @llvm.eh.typeid.for(i8*)
+
+define void @resume_phi() {
+entry:
+  invoke void @might_crash(i8* null)
+          to label %return unwind label %lpad1
+
+lpad1:
+  %ehvals1 = landingpad { i8*, i32 } personality i32 (...)* @__C_specific_handler
+          catch i32 ()* @filt
+  %ehptr1 = extractvalue { i8*, i32 } %ehvals1, 0
+  %ehsel1 = extractvalue { i8*, i32 } %ehvals1, 1
+  %filt_sel = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i32 ()* @filt to i8*))
+  %matches = icmp eq i32 %ehsel1, %filt_sel
+  br i1 %matches, label %__except, label %eh.resume
+
+__except:
+  invoke void @might_crash(i8* %ehptr1)
+          to label %return unwind label %lpad2
+
+lpad2:
+  %ehvals2 = landingpad { i8*, i32 } personality i32 (...)* @__C_specific_handler
+          cleanup
+  %ehptr2 = extractvalue { i8*, i32 } %ehvals2, 0
+  %ehsel2 = extractvalue { i8*, i32 } %ehvals2, 1
+  call void @cleanup()
+  br label %eh.resume
+
+return:
+  ret void
+
+eh.resume:
+  %ehptr.phi = phi i8* [ %ehptr1, %lpad1 ], [ %ehptr2, %lpad2 ]
+  %ehsel.phi = phi i32 [ %ehsel1, %lpad1 ], [ %ehsel2, %lpad2 ]
+  %ehval.phi1 = insertvalue { i8*, i32 } undef, i8* %ehptr.phi, 0
+  %ehval.phi2 = insertvalue { i8*, i32 } %ehval.phi1, i32 %ehsel.phi, 1
+  resume { i8*, i32 } %ehval.phi2
+}
+
+; CHECK-LABEL: define void @resume_phi()
+; CHECK: invoke void @might_crash(i8* null)
+; CHECK: landingpad { i8*, i32 }
+; CHECK-NEXT: catch i32 ()* @filt
+; CHECK-NEXT: call i8* (...) @llvm.eh.actions(
+; CHECK-SAME: i32 1, i8* bitcast (i32 ()* @filt to i8*), i32 -1, i8* blockaddress(@resume_phi, %__except))
+; CHECK-NEXT: indirectbr {{.*}} [label %__except]
+;
+; CHECK: __except:
+; CHECK: call i32 @llvm.eh.exceptioncode()
+; CHECK: invoke void @might_crash(i8* %{{.*}})
+; CHECK: landingpad { i8*, i32 }
+; CHECK-NEXT: cleanup
+; CHECK-NEXT: call i8* (...) @llvm.eh.actions(i32 0, void (i8*, i8*)* @resume_phi.cleanup)
+; CHECK-NEXT: indirectbr {{.*}} []
+
+; CHECK-LABEL: define internal void @resume_phi.cleanup(i8*, i8*)
+; CHECK: call void @cleanup()
diff --git a/test/CodeGen/WinEH/seh-simple.ll b/test/CodeGen/WinEH/seh-simple.ll
new file mode 100644
index 000000000000..9a451874d587
--- /dev/null
+++ b/test/CodeGen/WinEH/seh-simple.ll
@@ -0,0 +1,201 @@
+; RUN: opt -S -winehprepare -mtriple=x86_64-windows-msvc < %s \
+; RUN: 		| FileCheck %s --check-prefix=CHECK --check-prefix=X64
+
+; This test should also pass in 32-bit using _except_handler3.
+; RUN: sed -e 's/__C_specific_handler/_except_handler3/' %s \
+; RUN: 		| opt -S -winehprepare -mtriple=i686-windows-msvc \
+; RUN: 		| FileCheck %s --check-prefix=CHECK --check-prefix=X86
+
+declare void @cleanup()
+declare i32 @filt()
+declare void @might_crash()
+declare i32 @__C_specific_handler(...)
+declare i32 @llvm.eh.typeid.for(i8*)
+
+define i32 @simple_except_store() {
+entry:
+  %retval = alloca i32
+  store i32 0, i32* %retval
+  invoke void @might_crash()
+          to label %return unwind label %lpad
+
+lpad:
+  %ehvals = landingpad { i8*, i32 } personality i32 (...)* @__C_specific_handler
+          catch i32 ()* @filt
+  %sel = extractvalue { i8*, i32 } %ehvals, 1
+  %filt_sel = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i32 ()* @filt to i8*))
+  %matches = icmp eq i32 %sel, %filt_sel
+  br i1 %matches, label %__except, label %eh.resume
+
+__except:
+  store i32 1, i32* %retval
+  br label %return
+
+return:
+  %r = load i32, i32* %retval
+  ret i32 %r
+
+eh.resume:
+  resume { i8*, i32 } %ehvals
+}
+
+; CHECK-LABEL: define i32 @simple_except_store()
+; CHECK: landingpad { i8*, i32 }
+; CHECK-NEXT: catch i32 ()* @filt
+; CHECK-NEXT: call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (i32 ()* @filt to i8*), i32 -1, i8* blockaddress(@simple_except_store, %__except))
+; CHECK-NEXT: indirectbr {{.*}} [label %__except]
+
+define i32 @catch_all() {
+entry:
+  %retval = alloca i32
+  store i32 0, i32* %retval
+  invoke void @might_crash()
+          to label %return unwind label %lpad
+
+lpad:
+  %ehvals = landingpad { i8*, i32 } personality i32 (...)* @__C_specific_handler
+          catch i8* null
+  store i32 1, i32* %retval
+  br label %return
+
+return:
+  %r = load i32, i32* %retval
+  ret i32 %r
+}
+
+; CHECK-LABEL: define i32 @catch_all()
+; CHECK: landingpad { i8*, i32 }
+; CHECK-NEXT: catch i8* null
+; CHECK-NEXT: call i8* (...) @llvm.eh.actions(i32 1, i8* null, i32 -1, i8* blockaddress(@catch_all, %lpad.split))
+; CHECK-NEXT: indirectbr {{.*}} [label %lpad.split]
+;
+; CHECK: lpad.split:
+; CHECK: store i32 1, i32* %retval
+
+
+define i32 @except_phi() {
+entry:
+  invoke void @might_crash()
+          to label %return unwind label %lpad
+
+lpad:
+  %ehvals = landingpad { i8*, i32 } personality i32 (...)* @__C_specific_handler
+          catch i32 ()* @filt
+  %sel = extractvalue { i8*, i32 } %ehvals, 1
+  %filt_sel = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i32 ()* @filt to i8*))
+  %matches = icmp eq i32 %sel, %filt_sel
+  br i1 %matches, label %return, label %eh.resume
+
+return:
+  %r = phi i32 [0, %entry], [1, %lpad]
+  ret i32 %r
+
+eh.resume:
+  resume { i8*, i32 } %ehvals
+}
+
+; CHECK-LABEL: define i32 @except_phi()
+; CHECK: landingpad { i8*, i32 }
+; CHECK-NEXT: catch i32 ()* @filt
+; CHECK-NEXT: call i8* (...) @llvm.eh.actions(i32 1, i8* bitcast (i32 ()* @filt to i8*), i32 -1, i8* blockaddress(@except_phi, %lpad.return_crit_edge))
+; CHECK-NEXT: indirectbr {{.*}} [label %lpad.return_crit_edge]
+;
+; CHECK: lpad.return_crit_edge:
+; CHECK: br label %return
+;
+; CHECK: return:
+; CHECK-NEXT: %r = phi i32 [ 0, %entry ], [ 1, %lpad.return_crit_edge ]
+; CHECK-NEXT: ret i32 %r
+
+define i32 @lpad_phi() {
+entry:
+  invoke void @might_crash()
+          to label %cont unwind label %lpad
+
+cont:
+  invoke void @might_crash()
+          to label %return unwind label %lpad
+
+lpad:
+  %ncalls.1 = phi i32 [ 0, %entry ], [ 1, %cont ]
+  %ehvals = landingpad { i8*, i32 } personality i32 (...)* @__C_specific_handler
+          catch i32 ()* @filt
+  %sel = extractvalue { i8*, i32 } %ehvals, 1
+  %filt_sel = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i32 ()* @filt to i8*))
+  %matches = icmp eq i32 %sel, %filt_sel
+  br i1 %matches, label %return, label %eh.resume
+
+return:
+  %r = phi i32 [2, %cont], [%ncalls.1, %lpad]
+  ret i32 %r
+
+eh.resume:
+  resume { i8*, i32 } %ehvals
+}
+
+; CHECK-LABEL: define i32 @lpad_phi()
+; CHECK: alloca i32
+; CHECK: store i32 0, i32*
+; CHECK: invoke void @might_crash()
+; CHECK: store i32 1, i32*
+; CHECK: invoke void @might_crash()
+; CHECK: landingpad { i8*, i32 }
+; CHECK-NEXT: cleanup
+; CHECK-NEXT: catch i32 ()* @filt
+; CHECK-NEXT: call i8* (...) @llvm.eh.actions(i32 0, void ({{.*}})* @lpad_phi.cleanup, i32 1, i8* bitcast (i32 ()* @filt to i8*), i32 -1, i8* blockaddress(@lpad_phi, %lpad.return_crit_edge))
+; CHECK-NEXT: indirectbr {{.*}} [label %lpad.return_crit_edge]
+;
+; CHECK: lpad.return_crit_edge:
+; CHECK: load i32, i32*
+; CHECK: br label %return
+;
+; CHECK: return:
+; CHECK-NEXT: %r = phi i32 [ 2, %cont ], [ %{{.*}}, %lpad.return_crit_edge ]
+; CHECK-NEXT: ret i32 %r
+
+define i32 @cleanup_and_except() {
+entry:
+  invoke void @might_crash()
+          to label %return unwind label %lpad
+
+lpad:
+  %ehvals = landingpad { i8*, i32 } personality i32 (...)* @__C_specific_handler
+          cleanup
+          catch i32 ()* @filt
+  call void @cleanup()
+  %sel = extractvalue { i8*, i32 } %ehvals, 1
+  %filt_sel = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i32 ()* @filt to i8*))
+  %matches = icmp eq i32 %sel, %filt_sel
+  br i1 %matches, label %return, label %eh.resume
+
+return:
+  %r = phi i32 [0, %entry], [1, %lpad]
+  ret i32 %r
+
+eh.resume:
+  resume { i8*, i32 } %ehvals
+}
+
+; CHECK-LABEL: define i32 @cleanup_and_except()
+; CHECK: landingpad { i8*, i32 }
+; CHECK-NEXT: cleanup
+; CHECK-NEXT: catch i32 ()* @filt
+; CHECK-NEXT: call i8* (...) @llvm.eh.actions(
+; CHECK: i32 0, void ({{.*}})* @cleanup_and_except.cleanup,
+; CHECK: i32 1, i8* bitcast (i32 ()* @filt to i8*), i32 -1, i8* blockaddress(@cleanup_and_except, %lpad.return_crit_edge))
+; CHECK-NEXT: indirectbr {{.*}} [label %lpad.return_crit_edge]
+;
+; CHECK: lpad.return_crit_edge:
+; CHECK: br label %return
+;
+; CHECK: return:
+; CHECK-NEXT: %r = phi i32 [ 0, %entry ], [ 1, %lpad.return_crit_edge ]
+; CHECK-NEXT: ret i32 %r
+
+; FIXME: This cleanup is an artifact of bad demotion.
+; X64-LABEL: define internal void @lpad_phi.cleanup(i8*, i8*)
+; X86-LABEL: define internal void @lpad_phi.cleanup()
+; X86: call i8* @llvm.frameaddress(i32 1)
+; CHECK: call i8* @llvm.framerecover({{.*}})
+; CHECK: load i32
+; CHECK: store i32 %{{.*}}, i32*
diff --git a/test/CodeGen/X86/2005-01-17-CycleInDAG.ll b/test/CodeGen/X86/2005-01-17-CycleInDAG.ll
index fe6674da041f..48236cd0c8fe 100644
--- a/test/CodeGen/X86/2005-01-17-CycleInDAG.ll
+++ b/test/CodeGen/X86/2005-01-17-CycleInDAG.ll
@@ -8,9 +8,9 @@
 @GLOBAL = external global i32           ; <i32*> [#uses=1]
 
 define i32 @test(i32* %P1, i32* %P2, i32* %P3) nounwind {
-        %L = load i32* @GLOBAL          ; <i32> [#uses=1]
+        %L = load i32, i32* @GLOBAL          ; <i32> [#uses=1]
         store i32 12, i32* %P2
-        %Y = load i32* %P3              ; <i32> [#uses=1]
+        %Y = load i32, i32* %P3              ; <i32> [#uses=1]
         %Z = sub i32 %Y, %L             ; <i32> [#uses=1]
         ret i32 %Z
 }
diff --git a/test/CodeGen/X86/2005-02-14-IllegalAssembler.ll b/test/CodeGen/X86/2005-02-14-IllegalAssembler.ll
index 30a6ac6fbdf1..a05fc840922f 100644
--- a/test/CodeGen/X86/2005-02-14-IllegalAssembler.ll
+++ b/test/CodeGen/X86/2005-02-14-IllegalAssembler.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -march=x86 | not grep 18446744073709551612
 
 @A = external global i32                ; <i32*> [#uses=1]
-@Y = global i32* getelementptr (i32* @A, i32 -1)                ; <i32**> [#uses=0]
+@Y = global i32* getelementptr (i32, i32* @A, i32 -1)                ; <i32**> [#uses=0]
 
diff --git a/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll b/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll
index 1b3fc382e890..f6b5b2c103fe 100644
--- a/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll
+++ b/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll
@@ -7,7 +7,7 @@
 @A = external global i32                ; <i32*> [#uses=2]
 
 define i32 @test5(i32 %B, i8 %C) {
-        %tmp.1 = load i32* @A           ; <i32> [#uses=1]
+        %tmp.1 = load i32, i32* @A           ; <i32> [#uses=1]
         %shift.upgrd.1 = zext i8 %C to i32              ; <i32> [#uses=1]
         %tmp.2 = shl i32 %tmp.1, %shift.upgrd.1         ; <i32> [#uses=1]
         %tmp.3 = sub i8 32, %C          ; <i8> [#uses=1]
diff --git a/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll b/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
index fb1262a37295..9f44bc348e37 100644
--- a/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
+++ b/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
@@ -13,14 +13,14 @@ label.0.no_exit.1_crit_edge.exitStub:           ; preds = %label.0
 codeRepl5.exitStub:             ; preds = %label.0
         ret i1 false
 label.0:                ; preds = %newFuncRoot
-        %tmp.35 = load i32* @last               ; <i32> [#uses=1]
+        %tmp.35 = load i32, i32* @last               ; <i32> [#uses=1]
         %inc.1 = add i32 %tmp.35, 1             ; <i32> [#uses=2]
         store i32 %inc.1, i32* @last
-        %tmp.36 = load i8** @block              ; <i8*> [#uses=1]
-        %tmp.38 = getelementptr i8* %tmp.36, i32 %inc.1         ; <i8*> [#uses=1]
+        %tmp.36 = load i8*, i8** @block              ; <i8*> [#uses=1]
+        %tmp.38 = getelementptr i8, i8* %tmp.36, i32 %inc.1         ; <i8*> [#uses=1]
         %tmp.40 = trunc i32 %tmp.21.reload to i8                ; <i8> [#uses=1]
         store i8 %tmp.40, i8* %tmp.38
-        %tmp.910 = load i32* @last              ; <i32> [#uses=1]
+        %tmp.910 = load i32, i32* @last              ; <i32> [#uses=1]
         %tmp.1111 = icmp slt i32 %tmp.910, %tmp.8               ; <i1> [#uses=1]
         %tmp.1412 = icmp ne i32 %tmp.21.reload, 257             ; <i1> [#uses=1]
         %tmp.1613 = and i1 %tmp.1111, %tmp.1412         ; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll b/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll
index faa3e21a934d..583877e66582 100644
--- a/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll
+++ b/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll
@@ -5,10 +5,10 @@
 
 
 define i32 @foo(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
-	%tmp44 = load <4 x float>* %a		; <<4 x float>> [#uses=9]
-	%tmp46 = load <4 x float>* %b		; <<4 x float>> [#uses=1]
-	%tmp48 = load <4 x float>* %c		; <<4 x float>> [#uses=1]
-	%tmp50 = load <4 x float>* %d		; <<4 x float>> [#uses=1]
+	%tmp44 = load <4 x float>, <4 x float>* %a		; <<4 x float>> [#uses=9]
+	%tmp46 = load <4 x float>, <4 x float>* %b		; <<4 x float>> [#uses=1]
+	%tmp48 = load <4 x float>, <4 x float>* %c		; <<4 x float>> [#uses=1]
+	%tmp50 = load <4 x float>, <4 x float>* %d		; <<4 x float>> [#uses=1]
 	%tmp51 = bitcast <4 x float> %tmp44 to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp = shufflevector <4 x i32> %tmp51, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >		; <<4 x i32>> [#uses=2]
 	%tmp52 = bitcast <4 x i32> %tmp to <4 x float>		; <<4 x float>> [#uses=1]
diff --git a/test/CodeGen/X86/2006-05-02-InstrSched1.ll b/test/CodeGen/X86/2006-05-02-InstrSched1.ll
index 69266dc4e44b..46c5e88955f4 100644
--- a/test/CodeGen/X86/2006-05-02-InstrSched1.ll
+++ b/test/CodeGen/X86/2006-05-02-InstrSched1.ll
@@ -11,14 +11,14 @@
 define i32 @compare(i8* %a, i8* %b) nounwind {
 	%tmp = bitcast i8* %a to i32*		; <i32*> [#uses=1]
 	%tmp1 = bitcast i8* %b to i32*		; <i32*> [#uses=1]
-	%tmp.upgrd.1 = load i32* @size20		; <i32> [#uses=1]
-	%tmp.upgrd.2 = load i8** @in5		; <i8*> [#uses=2]
-	%tmp3 = load i32* %tmp1		; <i32> [#uses=1]
+	%tmp.upgrd.1 = load i32, i32* @size20		; <i32> [#uses=1]
+	%tmp.upgrd.2 = load i8*, i8** @in5		; <i8*> [#uses=2]
+	%tmp3 = load i32, i32* %tmp1		; <i32> [#uses=1]
 	%gep.upgrd.3 = zext i32 %tmp3 to i64		; <i64> [#uses=1]
-	%tmp4 = getelementptr i8* %tmp.upgrd.2, i64 %gep.upgrd.3		; <i8*> [#uses=2]
-	%tmp7 = load i32* %tmp		; <i32> [#uses=1]
+	%tmp4 = getelementptr i8, i8* %tmp.upgrd.2, i64 %gep.upgrd.3		; <i8*> [#uses=2]
+	%tmp7 = load i32, i32* %tmp		; <i32> [#uses=1]
 	%gep.upgrd.4 = zext i32 %tmp7 to i64		; <i64> [#uses=1]
-	%tmp8 = getelementptr i8* %tmp.upgrd.2, i64 %gep.upgrd.4		; <i8*> [#uses=2]
+	%tmp8 = getelementptr i8, i8* %tmp.upgrd.2, i64 %gep.upgrd.4		; <i8*> [#uses=2]
 	%tmp.upgrd.5 = tail call i32 @memcmp( i8* %tmp8, i8* %tmp4, i32 %tmp.upgrd.1 )		; <i32> [#uses=1]
 	ret i32 %tmp.upgrd.5
 }
diff --git a/test/CodeGen/X86/2006-05-02-InstrSched2.ll b/test/CodeGen/X86/2006-05-02-InstrSched2.ll
index 222b7a0b41fd..3281c68e9334 100644
--- a/test/CodeGen/X86/2006-05-02-InstrSched2.ll
+++ b/test/CodeGen/X86/2006-05-02-InstrSched2.ll
@@ -12,13 +12,13 @@ cond_true456.i:		; preds = %cond_true456.i, %newFuncRoot
 	%__s441.2.4.i = phi i8* [ %tmp451.i.upgrd.1, %cond_true456.i ], [ %tmp435.i, %newFuncRoot ]		; <i8*> [#uses=2]
 	%__h.2.4.i = phi i32 [ %tmp449.i, %cond_true456.i ], [ 0, %newFuncRoot ]	; <i32> [#uses=1]
 	%tmp446.i = mul i32 %__h.2.4.i, 5		; <i32> [#uses=1]
-	%tmp.i = load i8* %__s441.2.4.i		; <i8> [#uses=1]
+	%tmp.i = load i8, i8* %__s441.2.4.i		; <i8> [#uses=1]
 	%tmp448.i = sext i8 %tmp.i to i32		; <i32> [#uses=1]
 	%tmp449.i = add i32 %tmp448.i, %tmp446.i		; <i32> [#uses=2]
 	%tmp450.i = ptrtoint i8* %__s441.2.4.i to i32		; <i32> [#uses=1]
 	%tmp451.i = add i32 %tmp450.i, 1		; <i32> [#uses=1]
 	%tmp451.i.upgrd.1 = inttoptr i32 %tmp451.i to i8*		; <i8*> [#uses=2]
-	%tmp45435.i = load i8* %tmp451.i.upgrd.1		; <i8> [#uses=1]
+	%tmp45435.i = load i8, i8* %tmp451.i.upgrd.1		; <i8> [#uses=1]
 	%tmp45536.i = icmp eq i8 %tmp45435.i, 0		; <i1> [#uses=1]
 	br i1 %tmp45536.i, label %bb459.i.exitStub, label %cond_true456.i
 }
diff --git a/test/CodeGen/X86/2006-05-08-CoalesceSubRegClass.ll b/test/CodeGen/X86/2006-05-08-CoalesceSubRegClass.ll
index 8421483ecb55..b70d375bf51a 100644
--- a/test/CodeGen/X86/2006-05-08-CoalesceSubRegClass.ll
+++ b/test/CodeGen/X86/2006-05-08-CoalesceSubRegClass.ll
@@ -9,13 +9,13 @@
 
 define void @test(i32 %A) {
 	%A.upgrd.1 = trunc i32 %A to i8		; <i8> [#uses=1]
-	%tmp2 = load i32* @B		; <i32> [#uses=1]
+	%tmp2 = load i32, i32* @B		; <i32> [#uses=1]
 	%tmp3 = and i8 %A.upgrd.1, 16		; <i8> [#uses=1]
 	%shift.upgrd.2 = zext i8 %tmp3 to i32		; <i32> [#uses=1]
 	%tmp4 = shl i32 %tmp2, %shift.upgrd.2		; <i32> [#uses=1]
 	store i32 %tmp4, i32* @B
 	%tmp6 = lshr i32 %A, 3		; <i32> [#uses=1]
-	%tmp = load i16** @C		; <i16*> [#uses=1]
+	%tmp = load i16*, i16** @C		; <i16*> [#uses=1]
 	%tmp8 = ptrtoint i16* %tmp to i32		; <i32> [#uses=1]
 	%tmp9 = add i32 %tmp8, %tmp6		; <i32> [#uses=1]
 	%tmp9.upgrd.3 = inttoptr i32 %tmp9 to i16*		; <i16*> [#uses=1]
diff --git a/test/CodeGen/X86/2006-05-08-InstrSched.ll b/test/CodeGen/X86/2006-05-08-InstrSched.ll
index 3419d01fa083..cd46ecfef525 100644
--- a/test/CodeGen/X86/2006-05-08-InstrSched.ll
+++ b/test/CodeGen/X86/2006-05-08-InstrSched.ll
@@ -5,13 +5,13 @@
 @C = external global i32		; <i32*> [#uses=2]
 
 define void @test() {
-	%tmp = load i16** @A		; <i16*> [#uses=1]
-	%tmp1 = getelementptr i16* %tmp, i32 1		; <i16*> [#uses=1]
-	%tmp.upgrd.1 = load i16* %tmp1		; <i16> [#uses=1]
+	%tmp = load i16*, i16** @A		; <i16*> [#uses=1]
+	%tmp1 = getelementptr i16, i16* %tmp, i32 1		; <i16*> [#uses=1]
+	%tmp.upgrd.1 = load i16, i16* %tmp1		; <i16> [#uses=1]
 	%tmp3 = zext i16 %tmp.upgrd.1 to i32		; <i32> [#uses=1]
-	%tmp.upgrd.2 = load i32* @B		; <i32> [#uses=1]
+	%tmp.upgrd.2 = load i32, i32* @B		; <i32> [#uses=1]
 	%tmp4 = and i32 %tmp.upgrd.2, 16		; <i32> [#uses=1]
-	%tmp5 = load i32* @C		; <i32> [#uses=1]
+	%tmp5 = load i32, i32* @C		; <i32> [#uses=1]
 	%tmp6 = trunc i32 %tmp4 to i8		; <i8> [#uses=2]
 	%shift.upgrd.3 = zext i8 %tmp6 to i32		; <i32> [#uses=1]
 	%tmp7 = shl i32 %tmp5, %shift.upgrd.3		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2006-05-11-InstrSched.ll b/test/CodeGen/X86/2006-05-11-InstrSched.ll
index 3d0946698500..b1deb2c5f567 100644
--- a/test/CodeGen/X86/2006-05-11-InstrSched.ll
+++ b/test/CodeGen/X86/2006-05-11-InstrSched.ll
@@ -13,21 +13,21 @@ cond_true:		; preds = %cond_true, %entry
 	%tmp. = shl i32 %indvar, 2		; <i32> [#uses=1]
 	%tmp.10 = add nsw i32 %tmp., 1		; <i32> [#uses=2]
 	%tmp31 = add nsw i32 %tmp.10, -1		; <i32> [#uses=4]
-	%tmp32 = getelementptr i32* %mpp, i32 %tmp31		; <i32*> [#uses=1]
+	%tmp32 = getelementptr i32, i32* %mpp, i32 %tmp31		; <i32*> [#uses=1]
 	%tmp34 = bitcast i32* %tmp32 to <16 x i8>*		; <i8*> [#uses=1]
-	%tmp = load <16 x i8>* %tmp34, align 1
-	%tmp42 = getelementptr i32* %tpmm, i32 %tmp31		; <i32*> [#uses=1]
+	%tmp = load <16 x i8>, <16 x i8>* %tmp34, align 1
+	%tmp42 = getelementptr i32, i32* %tpmm, i32 %tmp31		; <i32*> [#uses=1]
 	%tmp42.upgrd.1 = bitcast i32* %tmp42 to <4 x i32>*		; <<4 x i32>*> [#uses=1]
-	%tmp46 = load <4 x i32>* %tmp42.upgrd.1		; <<4 x i32>> [#uses=1]
+	%tmp46 = load <4 x i32>, <4 x i32>* %tmp42.upgrd.1		; <<4 x i32>> [#uses=1]
 	%tmp54 = bitcast <16 x i8> %tmp to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp55 = add <4 x i32> %tmp54, %tmp46		; <<4 x i32>> [#uses=2]
 	%tmp55.upgrd.2 = bitcast <4 x i32> %tmp55 to <2 x i64>		; <<2 x i64>> [#uses=1]
-	%tmp62 = getelementptr i32* %ip, i32 %tmp31		; <i32*> [#uses=1]
+	%tmp62 = getelementptr i32, i32* %ip, i32 %tmp31		; <i32*> [#uses=1]
 	%tmp65 = bitcast i32* %tmp62 to <16 x i8>*		; <i8*> [#uses=1]
-	%tmp66 = load <16 x i8>* %tmp65, align 1
-	%tmp73 = getelementptr i32* %tpim, i32 %tmp31		; <i32*> [#uses=1]
+	%tmp66 = load <16 x i8>, <16 x i8>* %tmp65, align 1
+	%tmp73 = getelementptr i32, i32* %tpim, i32 %tmp31		; <i32*> [#uses=1]
 	%tmp73.upgrd.3 = bitcast i32* %tmp73 to <4 x i32>*		; <<4 x i32>*> [#uses=1]
-	%tmp77 = load <4 x i32>* %tmp73.upgrd.3		; <<4 x i32>> [#uses=1]
+	%tmp77 = load <4 x i32>, <4 x i32>* %tmp73.upgrd.3		; <<4 x i32>> [#uses=1]
 	%tmp87 = bitcast <16 x i8> %tmp66 to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp88 = add <4 x i32> %tmp87, %tmp77		; <<4 x i32>> [#uses=2]
 	%tmp88.upgrd.4 = bitcast <4 x i32> %tmp88 to <2 x i64>		; <<2 x i64>> [#uses=1]
@@ -37,7 +37,7 @@ cond_true:		; preds = %cond_true, %entry
 	%tmp111 = and <2 x i64> %tmp110, %tmp55.upgrd.2		; <<2 x i64>> [#uses=1]
 	%tmp121 = and <2 x i64> %tmp99.upgrd.5, %tmp88.upgrd.4		; <<2 x i64>> [#uses=1]
 	%tmp131 = or <2 x i64> %tmp121, %tmp111		; <<2 x i64>> [#uses=1]
-	%tmp137 = getelementptr i32* %mc, i32 %tmp.10		; <i32*> [#uses=1]
+	%tmp137 = getelementptr i32, i32* %mc, i32 %tmp.10		; <i32*> [#uses=1]
 	%tmp137.upgrd.7 = bitcast i32* %tmp137 to <2 x i64>*		; <<2 x i64>*> [#uses=1]
 	store <2 x i64> %tmp131, <2 x i64>* %tmp137.upgrd.7
 	%tmp147 = add nsw i32 %tmp.10, 8		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2006-05-22-FPSetEQ.ll b/test/CodeGen/X86/2006-05-22-FPSetEQ.ll
index 6c5a4fb3bd5c..3be77f5c3099 100644
--- a/test/CodeGen/X86/2006-05-22-FPSetEQ.ll
+++ b/test/CodeGen/X86/2006-05-22-FPSetEQ.ll
@@ -1,7 +1,10 @@
-; RUN: llc < %s -march=x86 -mattr=-sse | grep setnp
-; RUN: llc < %s -march=x86 -mattr=-sse -enable-unsafe-fp-math -enable-no-nans-fp-math | \
-; RUN:   not grep setnp
+; RUN: llc < %s -march=x86 -mattr=-sse | FileCheck %s -check-prefix=WITHNANS
+; RUN: llc < %s -march=x86 -mattr=-sse -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck %s -check-prefix=NONANS
 
+; WITHNANS-LABEL: test:
+; WITHNANS: setnp
+; NONANS-LABEL: test:
+; NONANS-NOT: setnp
 define i32 @test(float %f) {
 	%tmp = fcmp oeq float %f, 0.000000e+00		; <i1> [#uses=1]
 	%tmp.upgrd.1 = zext i1 %tmp to i32		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2006-05-25-CycleInDAG.ll b/test/CodeGen/X86/2006-05-25-CycleInDAG.ll
index 0288278d626e..6ff879760ea0 100644
--- a/test/CodeGen/X86/2006-05-25-CycleInDAG.ll
+++ b/test/CodeGen/X86/2006-05-25-CycleInDAG.ll
@@ -6,7 +6,7 @@ cond_true12:		; preds = %0
 	ret i32 0
 cond_next33:		; preds = %0
 	%tmp44.i = call double @foo( double 0.000000e+00, i32 32 )		; <double> [#uses=1]
-	%tmp61.i = load i8* null		; <i8> [#uses=1]
+	%tmp61.i = load i8, i8* null		; <i8> [#uses=1]
 	%tmp61.i.upgrd.1 = zext i8 %tmp61.i to i32		; <i32> [#uses=1]
 	%tmp58.i = or i32 0, %tmp61.i.upgrd.1		; <i32> [#uses=1]
 	%tmp62.i = or i32 %tmp58.i, 0		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2006-07-20-InlineAsm.ll b/test/CodeGen/X86/2006-07-20-InlineAsm.ll
index 1facf15b9f40..795e898df347 100644
--- a/test/CodeGen/X86/2006-07-20-InlineAsm.ll
+++ b/test/CodeGen/X86/2006-07-20-InlineAsm.ll
@@ -8,7 +8,7 @@ entry:
 	%X_addr = alloca i32		; <i32*> [#uses=3]
 	store i32 %X, i32* %X_addr
 	call void asm sideeffect "xchg{l} {$0,$1|$1,$0}", "=*m,=*r,m,1,~{dirflag},~{fpsr},~{flags}"( i32* @G, i32* %X_addr, i32* @G, i32 %X )
-	%tmp1 = load i32* %X_addr		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* %X_addr		; <i32> [#uses=1]
 	ret i32 %tmp1
 }
 
@@ -17,7 +17,7 @@ entry:
 	%X_addr = alloca i32		; <i32*> [#uses=3]
 	store i32 %X, i32* %X_addr
 	call void asm sideeffect "xchg{l} {$0,$1|$1,$0}", "=*m,=*r,1,~{dirflag},~{fpsr},~{flags}"( i32* @G, i32* %X_addr, i32 %X )
-	%tmp1 = load i32* %X_addr		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* %X_addr		; <i32> [#uses=1]
 	ret i32 %tmp1
 }
 
diff --git a/test/CodeGen/X86/2006-08-07-CycleInDAG.ll b/test/CodeGen/X86/2006-08-07-CycleInDAG.ll
index aea707ee8fe4..397bc26dbecd 100644
--- a/test/CodeGen/X86/2006-08-07-CycleInDAG.ll
+++ b/test/CodeGen/X86/2006-08-07-CycleInDAG.ll
@@ -8,10 +8,10 @@ cond_true.i:		; preds = %0
 	ret i32 0
 
 ilog2.exit:		; preds = %0
-	%tmp24.i = load i32* null		; <i32> [#uses=1]
+	%tmp24.i = load i32, i32* null		; <i32> [#uses=1]
 	%tmp13.i12.i = tail call double @ldexp( double 0.000000e+00, i32 0 )		; <double> [#uses=1]
 	%tmp13.i13.i = fptrunc double %tmp13.i12.i to float		; <float> [#uses=1]
-	%tmp11.s = load i32* null		; <i32> [#uses=1]
+	%tmp11.s = load i32, i32* null		; <i32> [#uses=1]
 	%tmp11.i = bitcast i32 %tmp11.s to i32		; <i32> [#uses=1]
 	%n.i = bitcast i32 %tmp24.i to i32		; <i32> [#uses=1]
 	%tmp13.i7 = mul i32 %tmp11.i, %n.i		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2006-08-16-CycleInDAG.ll b/test/CodeGen/X86/2006-08-16-CycleInDAG.ll
index 5fee326d530d..2c44adf6829c 100644
--- a/test/CodeGen/X86/2006-08-16-CycleInDAG.ll
+++ b/test/CodeGen/X86/2006-08-16-CycleInDAG.ll
@@ -6,14 +6,14 @@
 	%struct.u = type { [1 x i64] }
 
 define void @test() {
-	%tmp = load i32* null		; <i32> [#uses=1]
+	%tmp = load i32, i32* null		; <i32> [#uses=1]
 	%tmp8 = call i32 @hash_rtx( )		; <i32> [#uses=1]
 	%tmp11 = urem i32 %tmp8, %tmp		; <i32> [#uses=1]
 	br i1 false, label %cond_next, label %return
 
 cond_next:		; preds = %0
 	%gep.upgrd.1 = zext i32 %tmp11 to i64		; <i64> [#uses=1]
-	%tmp17 = getelementptr %struct.expr** null, i64 %gep.upgrd.1		; <%struct.expr**> [#uses=0]
+	%tmp17 = getelementptr %struct.expr*, %struct.expr** null, i64 %gep.upgrd.1		; <%struct.expr**> [#uses=0]
 	ret void
 
 return:		; preds = %0
diff --git a/test/CodeGen/X86/2006-09-01-CycleInDAG.ll b/test/CodeGen/X86/2006-09-01-CycleInDAG.ll
index 1e890bbc02e5..a7a10afaae1d 100644
--- a/test/CodeGen/X86/2006-09-01-CycleInDAG.ll
+++ b/test/CodeGen/X86/2006-09-01-CycleInDAG.ll
@@ -111,21 +111,21 @@ bb3502.exitStub:		; preds = %cond_true3632
 	ret void
 
 cond_true3632:		; preds = %newFuncRoot
-	%tmp3378 = load i32* %tmp3629		; <i32> [#uses=1]
+	%tmp3378 = load i32, i32* %tmp3629		; <i32> [#uses=1]
 	%tmp3379 = add i32 %tmp3378, -1		; <i32> [#uses=1]
-	%tmp3381 = getelementptr %struct.varray_head_tag* %stack3023.6, i32 0, i32 4		; <%struct.varray_data*> [#uses=1]
+	%tmp3381 = getelementptr %struct.varray_head_tag, %struct.varray_head_tag* %stack3023.6, i32 0, i32 4		; <%struct.varray_data*> [#uses=1]
 	%tmp3382 = bitcast %struct.varray_data* %tmp3381 to [1 x i32]*		; <[1 x i32]*> [#uses=1]
 	%gep.upgrd.1 = zext i32 %tmp3379 to i64		; <i64> [#uses=1]
-	%tmp3383 = getelementptr [1 x i32]* %tmp3382, i32 0, i64 %gep.upgrd.1		; <i32*> [#uses=1]
-	%tmp3384 = load i32* %tmp3383		; <i32> [#uses=1]
-	%tmp3387 = load i32* %tmp3629		; <i32> [#uses=1]
+	%tmp3383 = getelementptr [1 x i32], [1 x i32]* %tmp3382, i32 0, i64 %gep.upgrd.1		; <i32*> [#uses=1]
+	%tmp3384 = load i32, i32* %tmp3383		; <i32> [#uses=1]
+	%tmp3387 = load i32, i32* %tmp3629		; <i32> [#uses=1]
 	%tmp3388 = add i32 %tmp3387, -1		; <i32> [#uses=1]
 	store i32 %tmp3388, i32* %tmp3629
-	%tmp3391 = load %struct.varray_head_tag** @basic_block_info		; <%struct.varray_head_tag*> [#uses=1]
-	%tmp3393 = getelementptr %struct.varray_head_tag* %tmp3391, i32 0, i32 4		; <%struct.varray_data*> [#uses=1]
+	%tmp3391 = load %struct.varray_head_tag*, %struct.varray_head_tag** @basic_block_info		; <%struct.varray_head_tag*> [#uses=1]
+	%tmp3393 = getelementptr %struct.varray_head_tag, %struct.varray_head_tag* %tmp3391, i32 0, i32 4		; <%struct.varray_data*> [#uses=1]
 	%tmp3394 = bitcast %struct.varray_data* %tmp3393 to [1 x %struct.basic_block_def*]*		; <[1 x %struct.basic_block_def*]*> [#uses=1]
-	%tmp3395 = getelementptr [1 x %struct.basic_block_def*]* %tmp3394, i32 0, i32 %tmp3384		; <%struct.basic_block_def**> [#uses=1]
-	%tmp3396 = load %struct.basic_block_def** %tmp3395		; <%struct.basic_block_def*> [#uses=1]
-	%tmp3397 = getelementptr %struct.basic_block_def* %tmp3396, i32 0, i32 3		; <%struct.VEC_edge**> [#uses=1]
+	%tmp3395 = getelementptr [1 x %struct.basic_block_def*], [1 x %struct.basic_block_def*]* %tmp3394, i32 0, i32 %tmp3384		; <%struct.basic_block_def**> [#uses=1]
+	%tmp3396 = load %struct.basic_block_def*, %struct.basic_block_def** %tmp3395		; <%struct.basic_block_def*> [#uses=1]
+	%tmp3397 = getelementptr %struct.basic_block_def, %struct.basic_block_def* %tmp3396, i32 0, i32 3		; <%struct.VEC_edge**> [#uses=1]
 	br label %bb3502.exitStub
 }
diff --git a/test/CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll b/test/CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll
deleted file mode 100644
index d09d06147696..000000000000
--- a/test/CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll
+++ /dev/null
@@ -1,15 +0,0 @@
-; RUN: llc < %s -march=x86 -mattr=sse | grep movaps
-; Test that the load is NOT folded into the intrinsic, which would zero the top
-; elts of the loaded vector.
-
-target datalayout = "e-p:32:32"
-target triple = "i686-apple-darwin8.7.2"
-
-define <4 x float> @test(<4 x float> %A, <4 x float>* %B) nounwind {
-        %BV = load <4 x float>* %B              ; <<4 x float>> [#uses=1]
-        %tmp28 = tail call <4 x float> @llvm.x86.sse.sub.ss( <4 x float> %A, <4 x float> %BV )       ; <<4 x float>> [#uses=1]
-        ret <4 x float> %tmp28
-}
-
-declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>)
-
diff --git a/test/CodeGen/X86/2006-10-09-CycleInDAG.ll b/test/CodeGen/X86/2006-10-09-CycleInDAG.ll
index fbb14ee16151..e2c84ea569e6 100644
--- a/test/CodeGen/X86/2006-10-09-CycleInDAG.ll
+++ b/test/CodeGen/X86/2006-10-09-CycleInDAG.ll
@@ -1,9 +1,9 @@
 ; RUN: llc < %s -march=x86
 
 define void @_ZN13QFSFileEngine4readEPcx() {
-	%tmp201 = load i32* null		; <i32> [#uses=1]
+	%tmp201 = load i32, i32* null		; <i32> [#uses=1]
 	%tmp201.upgrd.1 = sext i32 %tmp201 to i64		; <i64> [#uses=1]
-	%tmp202 = load i64* null		; <i64> [#uses=1]
+	%tmp202 = load i64, i64* null		; <i64> [#uses=1]
 	%tmp203 = add i64 %tmp201.upgrd.1, %tmp202		; <i64> [#uses=1]
 	store i64 %tmp203, i64* null
 	ret void
diff --git a/test/CodeGen/X86/2006-10-10-FindModifiedNodeSlotBug.ll b/test/CodeGen/X86/2006-10-10-FindModifiedNodeSlotBug.ll
index b1f04518acaa..435582587856 100644
--- a/test/CodeGen/X86/2006-10-10-FindModifiedNodeSlotBug.ll
+++ b/test/CodeGen/X86/2006-10-10-FindModifiedNodeSlotBug.ll
@@ -4,14 +4,14 @@
 @tree_code_type = external global [0 x i32]		; <[0 x i32]*> [#uses=1]
 
 define void @copy_if_shared_r() {
-	%tmp = load i32* null		; <i32> [#uses=1]
+	%tmp = load i32, i32* null		; <i32> [#uses=1]
 	%tmp56 = and i32 %tmp, 255		; <i32> [#uses=1]
 	%gep.upgrd.1 = zext i32 %tmp56 to i64		; <i64> [#uses=1]
-	%tmp8 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %gep.upgrd.1	; <i32*> [#uses=1]
-	%tmp9 = load i32* %tmp8		; <i32> [#uses=1]
+	%tmp8 = getelementptr [0 x i32], [0 x i32]* @tree_code_type, i32 0, i64 %gep.upgrd.1	; <i32*> [#uses=1]
+	%tmp9 = load i32, i32* %tmp8		; <i32> [#uses=1]
 	%tmp10 = add i32 %tmp9, -1		; <i32> [#uses=1]
 	%tmp.upgrd.2 = icmp ugt i32 %tmp10, 2		; <i1> [#uses=1]
-	%tmp14 = load i32* null		; <i32> [#uses=1]
+	%tmp14 = load i32, i32* null		; <i32> [#uses=1]
 	%tmp15 = lshr i32 %tmp14, 31		; <i32> [#uses=1]
 	%tmp15.upgrd.3 = trunc i32 %tmp15 to i8		; <i8> [#uses=1]
 	%tmp16 = icmp ne i8 %tmp15.upgrd.3, 0		; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/2006-10-12-CycleInDAG.ll b/test/CodeGen/X86/2006-10-12-CycleInDAG.ll
index 3b987ac79f94..7a32ef7801d9 100644
--- a/test/CodeGen/X86/2006-10-12-CycleInDAG.ll
+++ b/test/CodeGen/X86/2006-10-12-CycleInDAG.ll
@@ -29,10 +29,10 @@ bb441:		; preds = %cond_next330
 	ret void
 
 cond_next472:		; preds = %cond_next330
-	%tmp490 = load %struct.tree_node** null		; <%struct.tree_node*> [#uses=1]
-	%tmp492 = getelementptr %struct.tree_node* %tmp490, i32 0, i32 0, i32 0, i32 3		; <i8*> [#uses=1]
+	%tmp490 = load %struct.tree_node*, %struct.tree_node** null		; <%struct.tree_node*> [#uses=1]
+	%tmp492 = getelementptr %struct.tree_node, %struct.tree_node* %tmp490, i32 0, i32 0, i32 0, i32 3		; <i8*> [#uses=1]
 	%tmp492.upgrd.1 = bitcast i8* %tmp492 to i32*		; <i32*> [#uses=1]
-	%tmp493 = load i32* %tmp492.upgrd.1		; <i32> [#uses=1]
+	%tmp493 = load i32, i32* %tmp492.upgrd.1		; <i32> [#uses=1]
 	%tmp495 = trunc i32 %tmp493 to i8		; <i8> [#uses=1]
 	%tmp496 = icmp eq i8 %tmp495, 11		; <i1> [#uses=1]
 	%tmp496.upgrd.2 = zext i1 %tmp496 to i8		; <i8> [#uses=1]
diff --git a/test/CodeGen/X86/2006-10-13-CycleInDAG.ll b/test/CodeGen/X86/2006-10-13-CycleInDAG.ll
index 6ed2e7bb5751..c45469d4e3ee 100644
--- a/test/CodeGen/X86/2006-10-13-CycleInDAG.ll
+++ b/test/CodeGen/X86/2006-10-13-CycleInDAG.ll
@@ -3,9 +3,9 @@
 
 define void @test() {
 bb.i:
-	%tmp.i660 = load <4 x float>* null		; <<4 x float>> [#uses=1]
-	call void (i32, ...)* @printf( i32 0, i8* getelementptr ([18 x i8]* @str, i32 0, i64 0), double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00 )
-	%tmp152.i = load <4 x i32>* null		; <<4 x i32>> [#uses=1]
+	%tmp.i660 = load <4 x float>, <4 x float>* null		; <<4 x float>> [#uses=1]
+	call void (i32, ...) @printf( i32 0, i8* getelementptr ([18 x i8], [18 x i8]* @str, i32 0, i64 0), double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00 )
+	%tmp152.i = load <4 x i32>, <4 x i32>* null		; <<4 x i32>> [#uses=1]
 	%tmp156.i = bitcast <4 x i32> %tmp152.i to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp175.i = bitcast <4 x float> %tmp.i660 to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp176.i = xor <4 x i32> %tmp156.i, < i32 -1, i32 -1, i32 -1, i32 -1 >		; <<4 x i32>> [#uses=1]
diff --git a/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll b/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
index d583e5964dc2..dd670648daf6 100644
--- a/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
+++ b/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
@@ -15,11 +15,11 @@ entry:
 	]
 
 bb:		; preds = %entry
-	%tmp1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([14 x i8]* @str, i32 0, i64 0) )		; <i32> [#uses=0]
+	%tmp1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([14 x i8], [14 x i8]* @str, i32 0, i64 0) )		; <i32> [#uses=0]
 	ret i32 0
 
 bb2:		; preds = %entry
-	%tmp4 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([13 x i8]* @str.upgrd.1, i32 0, i64 0) )		; <i32> [#uses=0]
+	%tmp4 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([13 x i8], [13 x i8]* @str.upgrd.1, i32 0, i64 0) )		; <i32> [#uses=0]
 	ret i32 0
 
 UnifiedReturnBlock:		; preds = %entry
diff --git a/test/CodeGen/X86/2006-11-12-CSRetCC.ll b/test/CodeGen/X86/2006-11-12-CSRetCC.ll
index d7af1c3fdc71..b6a8fc0bb2f8 100644
--- a/test/CodeGen/X86/2006-11-12-CSRetCC.ll
+++ b/test/CodeGen/X86/2006-11-12-CSRetCC.ll
@@ -18,43 +18,43 @@ entry:
         %z = alloca { double, double }, align 16                ; <{ double, double }*> [#uses=4]
         %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
         store double 0x400921FB54442D18, double* %pi
-        %tmp.upgrd.1 = load double* %pi         ; <double> [#uses=1]
-        %real = getelementptr { double, double }* %tmp1, i64 0, i32 0           ; <double*> [#uses=1]
+        %tmp.upgrd.1 = load double, double* %pi         ; <double> [#uses=1]
+        %real = getelementptr { double, double }, { double, double }* %tmp1, i64 0, i32 0           ; <double*> [#uses=1]
         store double 0.000000e+00, double* %real
-        %real3 = getelementptr { double, double }* %tmp1, i64 0, i32 1          ; <double*> [#uses=1]
+        %real3 = getelementptr { double, double }, { double, double }* %tmp1, i64 0, i32 1          ; <double*> [#uses=1]
         store double %tmp.upgrd.1, double* %real3
-        %tmp.upgrd.2 = getelementptr { double, double }* %tmp, i64 0, i32 0             ; <double*> [#uses=1]
-        %tmp4 = getelementptr { double, double }* %tmp1, i64 0, i32 0           ; <double*> [#uses=1]
-        %tmp5 = load double* %tmp4              ; <double> [#uses=1]
+        %tmp.upgrd.2 = getelementptr { double, double }, { double, double }* %tmp, i64 0, i32 0             ; <double*> [#uses=1]
+        %tmp4 = getelementptr { double, double }, { double, double }* %tmp1, i64 0, i32 0           ; <double*> [#uses=1]
+        %tmp5 = load double, double* %tmp4              ; <double> [#uses=1]
         store double %tmp5, double* %tmp.upgrd.2
-        %tmp6 = getelementptr { double, double }* %tmp, i64 0, i32 1            ; <double*> [#uses=1]
-        %tmp7 = getelementptr { double, double }* %tmp1, i64 0, i32 1           ; <double*> [#uses=1]
-        %tmp8 = load double* %tmp7              ; <double> [#uses=1]
+        %tmp6 = getelementptr { double, double }, { double, double }* %tmp, i64 0, i32 1            ; <double*> [#uses=1]
+        %tmp7 = getelementptr { double, double }, { double, double }* %tmp1, i64 0, i32 1           ; <double*> [#uses=1]
+        %tmp8 = load double, double* %tmp7              ; <double> [#uses=1]
         store double %tmp8, double* %tmp6
         %tmp.upgrd.3 = bitcast { double, double }* %tmp to { i64, i64 }*                ; <{ i64, i64 }*> [#uses=1]
-        %tmp.upgrd.4 = getelementptr { i64, i64 }* %tmp.upgrd.3, i64 0, i32 0           ; <i64*> [#uses=1]
-        %tmp.upgrd.5 = load i64* %tmp.upgrd.4           ; <i64> [#uses=1]
+        %tmp.upgrd.4 = getelementptr { i64, i64 }, { i64, i64 }* %tmp.upgrd.3, i64 0, i32 0           ; <i64*> [#uses=1]
+        %tmp.upgrd.5 = load i64, i64* %tmp.upgrd.4           ; <i64> [#uses=1]
         %tmp9 = bitcast { double, double }* %tmp to { i64, i64 }*               ; <{ i64, i64 }*> [#uses=1]
-        %tmp10 = getelementptr { i64, i64 }* %tmp9, i64 0, i32 1                ; <i64*> [#uses=1]
-        %tmp11 = load i64* %tmp10               ; <i64> [#uses=1]
+        %tmp10 = getelementptr { i64, i64 }, { i64, i64 }* %tmp9, i64 0, i32 1                ; <i64*> [#uses=1]
+        %tmp11 = load i64, i64* %tmp10               ; <i64> [#uses=1]
         call void @cexp( { double, double }* sret  %tmp2, i64 %tmp.upgrd.5, i64 %tmp11 )
-        %tmp12 = getelementptr { double, double }* %z, i64 0, i32 0             ; <double*> [#uses=1]
-        %tmp13 = getelementptr { double, double }* %tmp2, i64 0, i32 0          ; <double*> [#uses=1]
-        %tmp14 = load double* %tmp13            ; <double> [#uses=1]
+        %tmp12 = getelementptr { double, double }, { double, double }* %z, i64 0, i32 0             ; <double*> [#uses=1]
+        %tmp13 = getelementptr { double, double }, { double, double }* %tmp2, i64 0, i32 0          ; <double*> [#uses=1]
+        %tmp14 = load double, double* %tmp13            ; <double> [#uses=1]
         store double %tmp14, double* %tmp12
-        %tmp15 = getelementptr { double, double }* %z, i64 0, i32 1             ; <double*> [#uses=1]
-        %tmp16 = getelementptr { double, double }* %tmp2, i64 0, i32 1          ; <double*> [#uses=1]
-        %tmp17 = load double* %tmp16            ; <double> [#uses=1]
+        %tmp15 = getelementptr { double, double }, { double, double }* %z, i64 0, i32 1             ; <double*> [#uses=1]
+        %tmp16 = getelementptr { double, double }, { double, double }* %tmp2, i64 0, i32 1          ; <double*> [#uses=1]
+        %tmp17 = load double, double* %tmp16            ; <double> [#uses=1]
         store double %tmp17, double* %tmp15
-        %tmp18 = getelementptr { double, double }* %z, i64 0, i32 1             ; <double*> [#uses=1]
-        %tmp19 = load double* %tmp18            ; <double> [#uses=1]
-        %tmp20 = getelementptr { double, double }* %z, i64 0, i32 0             ; <double*> [#uses=1]
-        %tmp21 = load double* %tmp20            ; <double> [#uses=1]
-        %tmp.upgrd.6 = getelementptr [9 x i8]* @str, i32 0, i64 0               ; <i8*> [#uses=1]
-        %tmp.upgrd.7 = call i32 (i8*, ...)* @printf( i8* %tmp.upgrd.6, double %tmp21, double %tmp19 )           ; <i32> [#uses=0]
+        %tmp18 = getelementptr { double, double }, { double, double }* %z, i64 0, i32 1             ; <double*> [#uses=1]
+        %tmp19 = load double, double* %tmp18            ; <double> [#uses=1]
+        %tmp20 = getelementptr { double, double }, { double, double }* %z, i64 0, i32 0             ; <double*> [#uses=1]
+        %tmp21 = load double, double* %tmp20            ; <double> [#uses=1]
+        %tmp.upgrd.6 = getelementptr [9 x i8], [9 x i8]* @str, i32 0, i64 0               ; <i8*> [#uses=1]
+        %tmp.upgrd.7 = call i32 (i8*, ...) @printf( i8* %tmp.upgrd.6, double %tmp21, double %tmp19 )           ; <i32> [#uses=0]
         br label %finish
 finish:
-        %retval.upgrd.8 = load i32* %retval             ; <i32> [#uses=1]
+        %retval.upgrd.8 = load i32, i32* %retval             ; <i32> [#uses=1]
         ret i32 %retval.upgrd.8
 }
 
diff --git a/test/CodeGen/X86/2006-11-17-IllegalMove.ll b/test/CodeGen/X86/2006-11-17-IllegalMove.ll
index 783d9f94caeb..c0bd6f728422 100644
--- a/test/CodeGen/X86/2006-11-17-IllegalMove.ll
+++ b/test/CodeGen/X86/2006-11-17-IllegalMove.ll
@@ -5,7 +5,7 @@
 
 define void @handle_vector_size_attribute() nounwind {
 entry:
-	%tmp69 = load i32* null		; <i32> [#uses=1]
+	%tmp69 = load i32, i32* null		; <i32> [#uses=1]
 	switch i32 %tmp69, label %bb84 [
 		 i32 2, label %bb77
 		 i32 1, label %bb77
@@ -13,7 +13,7 @@ entry:
 
 bb77:		; preds = %entry, %entry
 	%tmp99 = udiv i64 0, 0		; <i64> [#uses=1]
-	%tmp = load i8* null		; <i8> [#uses=1]
+	%tmp = load i8, i8* null		; <i8> [#uses=1]
 	%tmp114 = icmp eq i64 0, 0		; <i1> [#uses=1]
 	br label %cond_true115
 
@@ -21,7 +21,7 @@ bb84:		; preds = %entry
 	ret void
 
 cond_true115:		; preds = %bb77
-	%tmp118 = load i8* null		; <i8> [#uses=1]
+	%tmp118 = load i8, i8* null		; <i8> [#uses=1]
 	br label %cond_true120
 
 cond_true120:		; preds = %cond_true115
diff --git a/test/CodeGen/X86/2006-12-16-InlineAsmCrash.ll b/test/CodeGen/X86/2006-12-16-InlineAsmCrash.ll
index 50a244b9e05b..080de1fb553e 100644
--- a/test/CodeGen/X86/2006-12-16-InlineAsmCrash.ll
+++ b/test/CodeGen/X86/2006-12-16-InlineAsmCrash.ll
@@ -20,8 +20,8 @@ target triple = "i686-pc-linux-gnu"
 	%"struct.QString::Data" = type { %struct.QBasicAtomic, i32, i32, i16*, i8, i8, [1 x i16] }
 
 define i1 @_ZNK12QImageWriter8canWriteEv() {
-	%tmp62 = load %struct.QImageWriterPrivate** null		; <%struct.QImageWriterPrivate*> [#uses=1]
-	%tmp = getelementptr %struct.QImageWriterPrivate* %tmp62, i32 0, i32 9		; <%struct.QString*> [#uses=1]
+	%tmp62 = load %struct.QImageWriterPrivate*, %struct.QImageWriterPrivate** null		; <%struct.QImageWriterPrivate*> [#uses=1]
+	%tmp = getelementptr %struct.QImageWriterPrivate, %struct.QImageWriterPrivate* %tmp62, i32 0, i32 9		; <%struct.QString*> [#uses=1]
 	%tmp75 = call %struct.QString* @_ZN7QStringaSERKS_( %struct.QString* %tmp, %struct.QString* null )		; <%struct.QString*> [#uses=0]
 	call void asm sideeffect "lock\0Adecl $0\0Asetne 1", "=*m"( i32* null )
 	ret i1 false
diff --git a/test/CodeGen/X86/2006-12-19-IntelSyntax.ll b/test/CodeGen/X86/2006-12-19-IntelSyntax.ll
index f81b303e3b80..2c3c5c99c1b2 100644
--- a/test/CodeGen/X86/2006-12-19-IntelSyntax.ll
+++ b/test/CodeGen/X86/2006-12-19-IntelSyntax.ll
@@ -21,55 +21,55 @@ entry:
 	]
 
 bb:		; preds = %entry
-	call void (...)* @foo1( )
+	call void (...) @foo1( )
 	ret void
 
 bb1:		; preds = %entry
-	call void (...)* @foo2( )
+	call void (...) @foo2( )
 	ret void
 
 bb2:		; preds = %entry
-	call void (...)* @foo6( )
+	call void (...) @foo6( )
 	ret void
 
 bb3:		; preds = %entry
-	call void (...)* @foo3( )
+	call void (...) @foo3( )
 	ret void
 
 bb4:		; preds = %entry
-	call void (...)* @foo4( )
+	call void (...) @foo4( )
 	ret void
 
 bb5:		; preds = %entry
-	call void (...)* @foo5( )
+	call void (...) @foo5( )
 	ret void
 
 bb6:		; preds = %entry
-	call void (...)* @foo1( )
+	call void (...) @foo1( )
 	ret void
 
 bb7:		; preds = %entry
-	call void (...)* @foo2( )
+	call void (...) @foo2( )
 	ret void
 
 bb8:		; preds = %entry
-	call void (...)* @foo6( )
+	call void (...) @foo6( )
 	ret void
 
 bb9:		; preds = %entry
-	call void (...)* @foo3( )
+	call void (...) @foo3( )
 	ret void
 
 bb10:		; preds = %entry
-	call void (...)* @foo4( )
+	call void (...) @foo4( )
 	ret void
 
 bb11:		; preds = %entry
-	call void (...)* @foo5( )
+	call void (...) @foo5( )
 	ret void
 
 bb12:		; preds = %entry
-	call void (...)* @foo6( )
+	call void (...) @foo6( )
 	ret void
 }
 
diff --git a/test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll b/test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll
index 3458550aa103..67c4bcd5fb71 100644
--- a/test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll
+++ b/test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll
@@ -10,7 +10,7 @@ entry:
 
 bb:
         %i = phi i64 [ 0, %entry ], [ %k, %bb ]
-        %j = getelementptr double* %y, i64 %i
+        %j = getelementptr double, double* %y, i64 %i
         store double 0.000000e+00, double* %j
         %k = add i64 %i, 1
         %n = icmp eq i64 %k, 0
diff --git a/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll b/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
index 04d4b8ee57eb..f83eea179d6a 100644
--- a/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
+++ b/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
@@ -8,12 +8,12 @@ target datalayout = "e-p:64:64"
 
 define void @foo(i32* %a0, i32* %a1, i32* %a2, i32* %a3, i32* %a4, i32* %a5) {
 b:
-	%r = load i32* %a0
-	%r2 = load i32* %a1
-	%r4 = load i32* %a2
-	%r6 = load i32* %a3
-	%r8 = load i32* %a4
-	%r14 = load i32* %a5
+	%r = load i32, i32* %a0
+	%r2 = load i32, i32* %a1
+	%r4 = load i32, i32* %a2
+	%r6 = load i32, i32* %a3
+	%r8 = load i32, i32* %a4
+	%r14 = load i32, i32* %a5
 	%rx = sext i32 %r2 to i64
 	%r9 = sext i32 %r to i64
 	%r11 = add i64 %rx, 0
@@ -31,13 +31,13 @@ b:
 	%r24 = shl i32 %r23a, 0
 	%r25 = add i32 %r24, 0
 	%ras2 = alloca i8, i32 %r25, align 16
-	%r28 = getelementptr i8* %ras2, i32 0
+	%r28 = getelementptr i8, i8* %ras2, i32 0
 	%r38 = shl i64 %r12, 0
 	%s2013 = add i64 %r38, 0
-	%c22012 = getelementptr i8* %ras2, i64 %s2013
+	%c22012 = getelementptr i8, i8* %ras2, i64 %s2013
 	%r42 = shl i64 %r12, 0
 	%s2011 = add i64 %r42, 16
-	%c22010 = getelementptr i8* %ras2, i64 %s2011
+	%c22010 = getelementptr i8, i8* %ras2, i64 %s2011
 	%r50 = add i64 %r16, 0
 	%r51 = icmp slt i64 %r50, 0
 	%r50sh = shl i64 %r50, 0
@@ -45,7 +45,7 @@ b:
 	%r54 = select i1 %r51, i64 0, i64 %r50j
 	%r56 = mul i64 %r54, %r12
 	%r28s = add i64 %r56, 16
-	%c2 = getelementptr i8* %ras2, i64 %r28s
+	%c2 = getelementptr i8, i8* %ras2, i64 %r28s
 	%r60 = sub i32 %r2, %r
 	%r61 = icmp slt i32 %r60, 0
 	br i1 %r61, label %a29b, label %b63
@@ -132,14 +132,14 @@ b341:
 	%d753 = bitcast i64 %w1874 to i64
 	%r343 = add i64 %s661, 0
 	%r346 = add i64 %r343, 0
-	%r347 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r346
-	%r348 = load float* %r347
+	%r347 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r346
+	%r348 = load float, float* %r347
 	%r352 = add i64 %r343, 0
-	%r353 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r352
-	%r354 = load float* %r353
-	%r362 = load float* bitcast ([128 x i64]* @i6000 to float*)
+	%r353 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r352
+	%r354 = load float, float* %r353
+	%r362 = load float, float* bitcast ([128 x i64]* @i6000 to float*)
 	%r363 = fadd float 0.000000e+00, %r362
-	%r370 = load float* bitcast ([128 x i64]* @i6000 to float*)
+	%r370 = load float, float* bitcast ([128 x i64]* @i6000 to float*)
 	%r376 = icmp slt i64 %r16, 0
 	br i1 %r376, label %b377, label %a35b
 b377:
@@ -183,9 +183,9 @@ b535:
 	%s923 = phi i64 [ 0, %b514 ], [ %r799, %b712 ]
 	%s933 = phi i64 [ %r533, %b514 ], [ %r795, %b712 ]
 	%r538 = add i64 %w1855, 0
-	%r539 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r538
-	%r540 = load float* %r539
-	%r551 = load float* bitcast ([128 x i64]* @i6000 to float*)
+	%r539 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r538
+	%r540 = load float, float* %r539
+	%r551 = load float, float* bitcast ([128 x i64]* @i6000 to float*)
 	%r562 = sub i64 %s933, 0
 	%r564 = icmp slt i64 %r512, 0
 	br i1 %r564, label %b565, label %a45b
@@ -212,23 +212,23 @@ b712:
 a45b714:
 	%r717 = add i64 %e944, 0
 	%r720 = add i64 %r717, 0
-	%r721 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r720
-	%r722 = load float* %r721
+	%r721 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r720
+	%r722 = load float, float* %r721
 	%r726 = add i64 %r717, 0
-	%r727 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r726
-	%r728 = load float* %r727
+	%r727 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r726
+	%r728 = load float, float* %r727
 	%r732 = add i64 %r717, 0
-	%r733 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r732
-	%r734 = load float* %r733
+	%r733 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r732
+	%r734 = load float, float* %r733
 	%r738 = add i64 %r717, 0
-	%r739 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r738
-	%r740 = load float* %r739
+	%r739 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r738
+	%r740 = load float, float* %r739
 	%r744 = add i64 %r717, 0
-	%r745 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r744
-	%r746 = load float* %r745
+	%r745 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r744
+	%r746 = load float, float* %r745
 	%r750 = add i64 %r717, 0
-	%r751 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r750
-	%r752 = load float* %r751
+	%r751 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r750
+	%r752 = load float, float* %r751
 	%r753 = fadd float %r752, %r746
 	%r754 = fadd float %r728, %r722
 	%r755 = fadd float %r734, %r754
@@ -236,11 +236,11 @@ a45b714:
 	%r757 = fadd float %r753, %r756
 	%r759 = fadd float %r757, %r540
 	%r770 = add i64 %r717, 0
-	%r771 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r770
-	%r772 = load float* %r771
+	%r771 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r770
+	%r772 = load float, float* %r771
 	%r776 = add i64 %r717, 0
-	%r777 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r776
-	%r778 = load float* %r777
+	%r777 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r776
+	%r778 = load float, float* %r777
 	%r781 = fadd float %r363, %r772
 	%r782 = fadd float %r781, %r778
 	%r783 = fadd float %r551, %r782
@@ -253,7 +253,7 @@ b820:
 	%r844 = add i64 %r16, 0
 	%r846 = sext i32 %r60 to i64
 	%r847 = add i64 %r846, 0
-	%r851 = load float* bitcast ([128 x i64]* @i6000 to float*)
+	%r851 = load float, float* bitcast ([128 x i64]* @i6000 to float*)
 	%r856 = sub i64 %rx, 0
 	br label %b858
 b858:
@@ -265,11 +265,11 @@ b858:
 	%s1173 = add i64 %b1902, 0
 	%r859 = add i64 %r856, 0
 	%r862 = add i64 %w1891, 0
-	%r863 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r862
-	%r864 = load float* %r863
+	%r863 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r862
+	%r864 = load float, float* %r863
 	%r868 = add i64 %w1891, 0
-	%r869 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r868
-	%r870 = load float* %r869
+	%r869 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r868
+	%r870 = load float, float* %r869
 	%r873 = sub i64 %r859, 0
 	%r876 = sub i64 %s1173, 0
 	%r878 = icmp slt i64 %r847, 0
@@ -301,14 +301,14 @@ a53b1019:
 	%r1022 = add i64 %r876, 0
 	%r1024 = bitcast i8* %c2 to float*
 	%r1025 = add i64 %r1022, 0
-	%r1026 = getelementptr float* %r1024, i64 %r1025
-	%r1027 = load float* %r1026
+	%r1026 = getelementptr float, float* %r1024, i64 %r1025
+	%r1027 = load float, float* %r1026
 	%r1032 = add i64 %r873, 0
 	%r1033 = add i64 %r1032, 0
-	%r1034 = getelementptr float* %r1024, i64 %r1033
-	%r1035 = load float* %r1034
+	%r1034 = getelementptr float, float* %r1024, i64 %r1033
+	%r1035 = load float, float* %r1034
 	%r1037 = bitcast i8* %c22010 to float*
-	%r1040 = getelementptr float* %r1037, i64 %r1025
+	%r1040 = getelementptr float, float* %r1037, i64 %r1025
 	%r1044 = fadd float %r864, %r1035
 	%r1046 = fadd float %r870, %r1027
 	%r1047 = fadd float %r1044, %r1046
@@ -335,11 +335,11 @@ b1117:
 	%d1353 = bitcast i64 %w1915 to i64
 	%r1120 = add i64 %s661, 0
 	%r1121 = add i64 %r1120, 0
-	%r1122 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r1121
-	%r1123 = load float* %r1122
+	%r1122 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r1121
+	%r1123 = load float, float* %r1122
 	%r1132 = bitcast i8* %c22012 to float*
-	%r1134 = getelementptr float* %r1132, i64 %w1915
-	%r1135 = load float* %r1134
+	%r1134 = getelementptr float, float* %r1132, i64 %w1915
+	%r1135 = load float, float* %r1134
 	%r1136 = fadd float %r1123, %r1135
 	%r1138 = icmp slt i64 %r1114, 0
 	br i1 %r1138, label %b1139, label %a63b
@@ -409,8 +409,8 @@ b1342:
 	%r1352 = add i64 %s1523, 0
 	%r1355 = sub i64 %r1352, 0
 	%r1370 = add i64 %d1533, 0
-	%r1371 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r1370
-	%r1372 = load float* %r1371
+	%r1371 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r1370
+	%r1372 = load float, float* %r1371
 	br label %a74b
 a74b:
 	%w1958 = phi i64 [ 0, %b1342 ], [ %v1959, %a74b ]
@@ -440,13 +440,13 @@ a97b:
 	%r1614 = mul i64 %r1613, 0
 	%r1622 = add i64 %r1614, 0
 	%r1754 = bitcast i8* %r28 to float*
-	%r1756 = getelementptr float* %r1754, i64 %w1970
-	%r1757 = load float* %r1756
+	%r1756 = getelementptr float, float* %r1754, i64 %w1970
+	%r1757 = load float, float* %r1756
 	%r1761 = add i64 %r1622, 0
-	%r1762 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r1761
-	%r1763 = load float* %r1762
+	%r1762 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r1761
+	%r1763 = load float, float* %r1762
 	%r1767 = add i64 %r1622, 0
-	%r1768 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r1767
+	%r1768 = getelementptr float, float* bitcast ([128 x i64]* @i6000 to float*), i64 %r1767
 	%r1772 = fadd float %r1763, 0.000000e+00
 	%r1773 = fadd float %r1772, 0.000000e+00
 	%r1809 = fadd float %r1757, 0.000000e+00
diff --git a/test/CodeGen/X86/2007-02-04-OrAddrMode.ll b/test/CodeGen/X86/2007-02-04-OrAddrMode.ll
index cea4d9d272fc..f05175259c80 100644
--- a/test/CodeGen/X86/2007-02-04-OrAddrMode.ll
+++ b/test/CodeGen/X86/2007-02-04-OrAddrMode.ll
@@ -7,10 +7,10 @@ define i32 @test(float ** %tmp2, i32 %tmp12) nounwind {
 ; CHECK: orl $1, %{{.*}}
 ; CHECK: ret
 
-	%tmp3 = load float** %tmp2
+	%tmp3 = load float*, float** %tmp2
 	%tmp132 = shl i32 %tmp12, 2		; <i32> [#uses=1]
 	%tmp4 = bitcast float* %tmp3 to i8*		; <i8*> [#uses=1]
-	%ctg2 = getelementptr i8* %tmp4, i32 %tmp132		; <i8*> [#uses=1]
+	%ctg2 = getelementptr i8, i8* %tmp4, i32 %tmp132		; <i8*> [#uses=1]
 	%tmp6 = ptrtoint i8* %ctg2 to i32		; <i32> [#uses=1]
 	%tmp14 = or i32 %tmp6, 1		; <i32> [#uses=1]
 	ret i32 %tmp14
diff --git a/test/CodeGen/X86/2007-02-16-BranchFold.ll b/test/CodeGen/X86/2007-02-16-BranchFold.ll
index 6bf5631b4e34..22e0a4e806f9 100644
--- a/test/CodeGen/X86/2007-02-16-BranchFold.ll
+++ b/test/CodeGen/X86/2007-02-16-BranchFold.ll
@@ -54,15 +54,15 @@ bb28.i.i938.exitStub:		; preds = %LeafBlock3
 	ret i16 4
 
 bb.i9.i.i932.ce:		; preds = %newFuncRoot
-	%tmp1.i3.i.i930 = getelementptr %struct.list* %l_addr.01.0.i2.i.i929, i32 0, i32 0		; <i8**> [#uses=1]
-	%tmp2.i4.i.i931 = load i8** %tmp1.i3.i.i930		; <i8*> [#uses=1]
+	%tmp1.i3.i.i930 = getelementptr %struct.list, %struct.list* %l_addr.01.0.i2.i.i929, i32 0, i32 0		; <i8**> [#uses=1]
+	%tmp2.i4.i.i931 = load i8*, i8** %tmp1.i3.i.i930		; <i8*> [#uses=1]
 	%tmp66.i62.i = bitcast i8* %tmp2.i4.i.i931 to %struct.operator*		; <%struct.operator*> [#uses=7]
-	%tmp1.i6.i = getelementptr %struct.operator* %tmp66.i62.i, i32 0, i32 2		; <i32*> [#uses=1]
-	%tmp2.i7.i = load i32* %tmp1.i6.i		; <i32> [#uses=1]
-	%tmp3.i8.i = load %struct.FILE** @outfile		; <%struct.FILE*> [#uses=1]
-	%tmp5.i9.i = call i32 (%struct.FILE*, i8*, ...)* @fprintf( %struct.FILE* %tmp3.i8.i, i8* getelementptr ([11 x i8]* @str1, i32 0, i32 0), i32 %tmp2.i7.i )		; <i32> [#uses=0]
-	%tmp7.i10.i = getelementptr %struct.operator* %tmp66.i62.i, i32 0, i32 5		; <i32*> [#uses=1]
-	%tmp8.i11.i = load i32* %tmp7.i10.i		; <i32> [#uses=7]
+	%tmp1.i6.i = getelementptr %struct.operator, %struct.operator* %tmp66.i62.i, i32 0, i32 2		; <i32*> [#uses=1]
+	%tmp2.i7.i = load i32, i32* %tmp1.i6.i		; <i32> [#uses=1]
+	%tmp3.i8.i = load %struct.FILE*, %struct.FILE** @outfile		; <%struct.FILE*> [#uses=1]
+	%tmp5.i9.i = call i32 (%struct.FILE*, i8*, ...) @fprintf( %struct.FILE* %tmp3.i8.i, i8* getelementptr ([11 x i8], [11 x i8]* @str1, i32 0, i32 0), i32 %tmp2.i7.i )		; <i32> [#uses=0]
+	%tmp7.i10.i = getelementptr %struct.operator, %struct.operator* %tmp66.i62.i, i32 0, i32 5		; <i32*> [#uses=1]
+	%tmp8.i11.i = load i32, i32* %tmp7.i10.i		; <i32> [#uses=7]
 	br label %NodeBlock5
 
 NodeBlock5:		; preds = %bb.i9.i.i932.ce
diff --git a/test/CodeGen/X86/2007-02-19-LiveIntervalAssert.ll b/test/CodeGen/X86/2007-02-19-LiveIntervalAssert.ll
index 954c95d69611..a9b85b94cd41 100644
--- a/test/CodeGen/X86/2007-02-19-LiveIntervalAssert.ll
+++ b/test/CodeGen/X86/2007-02-19-LiveIntervalAssert.ll
@@ -6,9 +6,9 @@
 @stderr = external global %struct._IO_FILE*
 
 define void @__eprintf(i8* %string, i8* %expression, i32 %line, i8* %filename) {
-	%tmp = load %struct._IO_FILE** @stderr
-	%tmp5 = tail call i32 (%struct._IO_FILE*, i8*, ...)* @fprintf( %struct._IO_FILE* %tmp, i8* %string, i8* %expression, i32 %line, i8* %filename )
-	%tmp6 = load %struct._IO_FILE** @stderr
+	%tmp = load %struct._IO_FILE*, %struct._IO_FILE** @stderr
+	%tmp5 = tail call i32 (%struct._IO_FILE*, i8*, ...) @fprintf( %struct._IO_FILE* %tmp, i8* %string, i8* %expression, i32 %line, i8* %filename )
+	%tmp6 = load %struct._IO_FILE*, %struct._IO_FILE** @stderr
 	%tmp7 = tail call i32 @fflush( %struct._IO_FILE* %tmp6 )
 	tail call void @abort( )
 	unreachable
diff --git a/test/CodeGen/X86/2007-03-01-SpillerCrash.ll b/test/CodeGen/X86/2007-03-01-SpillerCrash.ll
index 112d1ab65e7b..dbbb611dc75a 100644
--- a/test/CodeGen/X86/2007-03-01-SpillerCrash.ll
+++ b/test/CodeGen/X86/2007-03-01-SpillerCrash.ll
@@ -4,7 +4,7 @@
 define void @test() nounwind {
 test.exit:
 	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:0 [#uses=4]
-	load <4 x float>* null		; <<4 x float>>:1 [#uses=1]
+	load <4 x float>, <4 x float>* null		; <<4 x float>>:1 [#uses=1]
 	shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >		; <<4 x float>>:2 [#uses=1]
 	fmul <4 x float> %0, %2		; <<4 x float>>:3 [#uses=1]
 	fsub <4 x float> zeroinitializer, %3		; <<4 x float>>:4 [#uses=1]
diff --git a/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll b/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll
index 4d7c3a185a8b..f159bcdee134 100644
--- a/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll
+++ b/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll
@@ -25,50 +25,50 @@ bb.preheader:		; preds = %entry
 bb:		; preds = %bb, %bb.preheader
 	%i.073.0 = phi i32 [ 0, %bb.preheader ], [ %indvar.next, %bb ]		; <i32> [#uses=3]
 	%p_addr.076.0.rec = mul i32 %i.073.0, 9		; <i32> [#uses=9]
-	%p_addr.076.0 = getelementptr i8* %p, i32 %p_addr.076.0.rec		; <i8*> [#uses=1]
-	%tmp2 = getelementptr i8** %buf, i32 %i.073.0		; <i8**> [#uses=1]
-	%tmp3 = load i8** %tmp2		; <i8*> [#uses=8]
-	%tmp5 = getelementptr i8* %tmp3, i32 %col		; <i8*> [#uses=1]
-	%tmp7 = load i8* %p_addr.076.0		; <i8> [#uses=1]
+	%p_addr.076.0 = getelementptr i8, i8* %p, i32 %p_addr.076.0.rec		; <i8*> [#uses=1]
+	%tmp2 = getelementptr i8*, i8** %buf, i32 %i.073.0		; <i8**> [#uses=1]
+	%tmp3 = load i8*, i8** %tmp2		; <i8*> [#uses=8]
+	%tmp5 = getelementptr i8, i8* %tmp3, i32 %col		; <i8*> [#uses=1]
+	%tmp7 = load i8, i8* %p_addr.076.0		; <i8> [#uses=1]
 	store i8 %tmp7, i8* %tmp5
 	%p_addr.076.0.sum93 = add i32 %p_addr.076.0.rec, 1		; <i32> [#uses=1]
-	%tmp11 = getelementptr i8* %p, i32 %p_addr.076.0.sum93		; <i8*> [#uses=1]
-	%tmp13 = load i8* %tmp11		; <i8> [#uses=1]
-	%tmp15 = getelementptr i8* %tmp3, i32 %tmp5.sum72		; <i8*> [#uses=1]
+	%tmp11 = getelementptr i8, i8* %p, i32 %p_addr.076.0.sum93		; <i8*> [#uses=1]
+	%tmp13 = load i8, i8* %tmp11		; <i8> [#uses=1]
+	%tmp15 = getelementptr i8, i8* %tmp3, i32 %tmp5.sum72		; <i8*> [#uses=1]
 	store i8 %tmp13, i8* %tmp15
 	%p_addr.076.0.sum92 = add i32 %p_addr.076.0.rec, 2		; <i32> [#uses=1]
-	%tmp17 = getelementptr i8* %p, i32 %p_addr.076.0.sum92		; <i8*> [#uses=1]
-	%tmp19 = load i8* %tmp17		; <i8> [#uses=1]
-	%tmp21 = getelementptr i8* %tmp3, i32 %tmp5.sum71		; <i8*> [#uses=1]
+	%tmp17 = getelementptr i8, i8* %p, i32 %p_addr.076.0.sum92		; <i8*> [#uses=1]
+	%tmp19 = load i8, i8* %tmp17		; <i8> [#uses=1]
+	%tmp21 = getelementptr i8, i8* %tmp3, i32 %tmp5.sum71		; <i8*> [#uses=1]
 	store i8 %tmp19, i8* %tmp21
 	%p_addr.076.0.sum91 = add i32 %p_addr.076.0.rec, 3		; <i32> [#uses=1]
-	%tmp23 = getelementptr i8* %p, i32 %p_addr.076.0.sum91		; <i8*> [#uses=1]
-	%tmp25 = load i8* %tmp23		; <i8> [#uses=1]
-	%tmp27 = getelementptr i8* %tmp3, i32 %tmp5.sum70		; <i8*> [#uses=1]
+	%tmp23 = getelementptr i8, i8* %p, i32 %p_addr.076.0.sum91		; <i8*> [#uses=1]
+	%tmp25 = load i8, i8* %tmp23		; <i8> [#uses=1]
+	%tmp27 = getelementptr i8, i8* %tmp3, i32 %tmp5.sum70		; <i8*> [#uses=1]
 	store i8 %tmp25, i8* %tmp27
 	%p_addr.076.0.sum90 = add i32 %p_addr.076.0.rec, 4		; <i32> [#uses=1]
-	%tmp29 = getelementptr i8* %p, i32 %p_addr.076.0.sum90		; <i8*> [#uses=1]
-	%tmp31 = load i8* %tmp29		; <i8> [#uses=1]
-	%tmp33 = getelementptr i8* %tmp3, i32 %tmp5.sum69		; <i8*> [#uses=2]
+	%tmp29 = getelementptr i8, i8* %p, i32 %p_addr.076.0.sum90		; <i8*> [#uses=1]
+	%tmp31 = load i8, i8* %tmp29		; <i8> [#uses=1]
+	%tmp33 = getelementptr i8, i8* %tmp3, i32 %tmp5.sum69		; <i8*> [#uses=2]
 	store i8 %tmp31, i8* %tmp33
 	%p_addr.076.0.sum89 = add i32 %p_addr.076.0.rec, 5		; <i32> [#uses=1]
-	%tmp35 = getelementptr i8* %p, i32 %p_addr.076.0.sum89		; <i8*> [#uses=1]
-	%tmp37 = load i8* %tmp35		; <i8> [#uses=1]
-	%tmp39 = getelementptr i8* %tmp3, i32 %tmp5.sum68		; <i8*> [#uses=1]
+	%tmp35 = getelementptr i8, i8* %p, i32 %p_addr.076.0.sum89		; <i8*> [#uses=1]
+	%tmp37 = load i8, i8* %tmp35		; <i8> [#uses=1]
+	%tmp39 = getelementptr i8, i8* %tmp3, i32 %tmp5.sum68		; <i8*> [#uses=1]
 	store i8 %tmp37, i8* %tmp39
 	%p_addr.076.0.sum88 = add i32 %p_addr.076.0.rec, 6		; <i32> [#uses=1]
-	%tmp41 = getelementptr i8* %p, i32 %p_addr.076.0.sum88		; <i8*> [#uses=1]
-	%tmp43 = load i8* %tmp41		; <i8> [#uses=1]
+	%tmp41 = getelementptr i8, i8* %p, i32 %p_addr.076.0.sum88		; <i8*> [#uses=1]
+	%tmp43 = load i8, i8* %tmp41		; <i8> [#uses=1]
 	store i8 %tmp43, i8* %tmp33
 	%p_addr.076.0.sum87 = add i32 %p_addr.076.0.rec, 7		; <i32> [#uses=1]
-	%tmp47 = getelementptr i8* %p, i32 %p_addr.076.0.sum87		; <i8*> [#uses=1]
-	%tmp49 = load i8* %tmp47		; <i8> [#uses=1]
-	%tmp51 = getelementptr i8* %tmp3, i32 %tmp5.sum66		; <i8*> [#uses=1]
+	%tmp47 = getelementptr i8, i8* %p, i32 %p_addr.076.0.sum87		; <i8*> [#uses=1]
+	%tmp49 = load i8, i8* %tmp47		; <i8> [#uses=1]
+	%tmp51 = getelementptr i8, i8* %tmp3, i32 %tmp5.sum66		; <i8*> [#uses=1]
 	store i8 %tmp49, i8* %tmp51
 	%p_addr.076.0.sum = add i32 %p_addr.076.0.rec, 8		; <i32> [#uses=1]
-	%tmp53 = getelementptr i8* %p, i32 %p_addr.076.0.sum		; <i8*> [#uses=1]
-	%tmp55 = load i8* %tmp53		; <i8> [#uses=1]
-	%tmp57 = getelementptr i8* %tmp3, i32 %tmp5.sum		; <i8*> [#uses=1]
+	%tmp53 = getelementptr i8, i8* %p, i32 %p_addr.076.0.sum		; <i8*> [#uses=1]
+	%tmp55 = load i8, i8* %tmp53		; <i8> [#uses=1]
+	%tmp57 = getelementptr i8, i8* %tmp3, i32 %tmp5.sum		; <i8*> [#uses=1]
 	store i8 %tmp55, i8* %tmp57
 	%indvar.next = add i32 %i.073.0, 1		; <i32> [#uses=2]
 	icmp eq i32 %indvar.next, %size		; <i1>:1 [#uses=1]
diff --git a/test/CodeGen/X86/2007-03-16-InlineAsm.ll b/test/CodeGen/X86/2007-03-16-InlineAsm.ll
index 3bd6d590efc1..61746814f9a0 100644
--- a/test/CodeGen/X86/2007-03-16-InlineAsm.ll
+++ b/test/CodeGen/X86/2007-03-16-InlineAsm.ll
@@ -11,16 +11,16 @@ entry:
 	%ret = alloca i32, align 4		; <i32*> [#uses=2]
 	store i32 %A, i32* %A_addr
 	store i32 %B, i32* %B_addr
-	%tmp1 = load i32* %A_addr		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* %A_addr		; <i32> [#uses=1]
 	%tmp2 = call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"( i32 7, i32 %tmp1 )		; <i32> [#uses=1]
 	store i32 %tmp2, i32* %ret
-	%tmp3 = load i32* %ret		; <i32> [#uses=1]
+	%tmp3 = load i32, i32* %ret		; <i32> [#uses=1]
 	store i32 %tmp3, i32* %tmp
-	%tmp4 = load i32* %tmp		; <i32> [#uses=1]
+	%tmp4 = load i32, i32* %tmp		; <i32> [#uses=1]
 	store i32 %tmp4, i32* %retval
 	br label %return
 
 return:		; preds = %entry
-	%retval5 = load i32* %retval		; <i32> [#uses=1]
+	%retval5 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval5
 }
diff --git a/test/CodeGen/X86/2007-03-26-CoalescerBug.ll b/test/CodeGen/X86/2007-03-26-CoalescerBug.ll
index 9676f143bca6..9a3d4cb3bee7 100644
--- a/test/CodeGen/X86/2007-03-26-CoalescerBug.ll
+++ b/test/CodeGen/X86/2007-03-26-CoalescerBug.ll
@@ -4,7 +4,7 @@
 
 define void @foo(...) {
 bb1:
-	%t43 = load i64* getelementptr ([339 x i64]* @data, i32 0, i64 212), align 4
+	%t43 = load i64, i64* getelementptr ([339 x i64], [339 x i64]* @data, i32 0, i64 212), align 4
 	br i1 false, label %bb80, label %bb6
 bb6:
 	br i1 false, label %bb38, label %bb265
diff --git a/test/CodeGen/X86/2007-04-08-InlineAsmCrash.ll b/test/CodeGen/X86/2007-04-08-InlineAsmCrash.ll
index 9f09e88664c6..176b566fe0ae 100644
--- a/test/CodeGen/X86/2007-04-08-InlineAsmCrash.ll
+++ b/test/CodeGen/X86/2007-04-08-InlineAsmCrash.ll
@@ -9,7 +9,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define fastcc i32 @bc_divide(%struct.bc_struct* %n1, %struct.bc_struct* %n2, %struct.bc_struct** %quot, i32 %scale) nounwind {
 entry:
-	%tmp7.i46 = tail call i64 asm sideeffect ".byte 0x0f,0x31", "={dx},=*{ax},~{dirflag},~{fpsr},~{flags}"( i64* getelementptr (%struct.CycleCount* @_programStartTime, i32 0, i32 1) )		; <i64> [#uses=0]
+	%tmp7.i46 = tail call i64 asm sideeffect ".byte 0x0f,0x31", "={dx},=*{ax},~{dirflag},~{fpsr},~{flags}"( i64* getelementptr (%struct.CycleCount, %struct.CycleCount* @_programStartTime, i32 0, i32 1) )		; <i64> [#uses=0]
 	%tmp221 = sdiv i32 10, 0		; <i32> [#uses=1]
 	tail call fastcc void @_one_mult( i8* null, i32 0, i32 %tmp221, i8* null )
 	ret i32 0
diff --git a/test/CodeGen/X86/2007-04-17-LiveIntervalAssert.ll b/test/CodeGen/X86/2007-04-17-LiveIntervalAssert.ll
index 4604f46c533f..31c6b532d8c7 100644
--- a/test/CodeGen/X86/2007-04-17-LiveIntervalAssert.ll
+++ b/test/CodeGen/X86/2007-04-17-LiveIntervalAssert.ll
@@ -19,8 +19,8 @@ cond_true:		; preds = %bb.preheader
 bb32:		; preds = %bb32, %cond_true
 	%i.2115.0 = phi i32 [ 0, %cond_true ], [ %indvar.next127, %bb32 ]		; <i32> [#uses=1]
 	%c.2112.0 = phi i32 [ 0, %cond_true ], [ %tmp49, %bb32 ]		; <i32> [#uses=1]
-	%tmp43 = getelementptr %struct.partition_def* %part, i32 0, i32 1, i32 %c.2112.0, i32 1		; <%struct.partition_elem**> [#uses=1]
-	%tmp44 = load %struct.partition_elem** %tmp43		; <%struct.partition_elem*> [#uses=1]
+	%tmp43 = getelementptr %struct.partition_def, %struct.partition_def* %part, i32 0, i32 1, i32 %c.2112.0, i32 1		; <%struct.partition_elem**> [#uses=1]
+	%tmp44 = load %struct.partition_elem*, %struct.partition_elem** %tmp43		; <%struct.partition_elem*> [#uses=1]
 	%tmp4445 = ptrtoint %struct.partition_elem* %tmp44 to i32		; <i32> [#uses=1]
 	%tmp48 = sub i32 %tmp4445, 0		; <i32> [#uses=1]
 	%tmp49 = sdiv i32 %tmp48, 12		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll b/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll
deleted file mode 100644
index 11c0bf957983..000000000000
--- a/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll
+++ /dev/null
@@ -1,64 +0,0 @@
-; RUN: llc < %s -o - -march=x86 -mattr=+mmx | FileCheck %s
-; There are no MMX instructions here.  We use add+adcl for the adds.
-
-define <1 x i64> @unsigned_add3(<1 x i64>* %a, <1 x i64>* %b, i32 %count) nounwind {
-entry:
-	%tmp2942 = icmp eq i32 %count, 0		; <i1> [#uses=1]
-	br i1 %tmp2942, label %bb31, label %bb26
-
-bb26:		; preds = %bb26, %entry
-
-; CHECK:  addl
-; CHECK:  adcl
-
-	%i.037.0 = phi i32 [ 0, %entry ], [ %tmp25, %bb26 ]		; <i32> [#uses=3]
-	%sum.035.0 = phi <1 x i64> [ zeroinitializer, %entry ], [ %tmp22, %bb26 ]		; <<1 x i64>> [#uses=1]
-	%tmp13 = getelementptr <1 x i64>* %b, i32 %i.037.0		; <<1 x i64>*> [#uses=1]
-	%tmp14 = load <1 x i64>* %tmp13		; <<1 x i64>> [#uses=1]
-	%tmp18 = getelementptr <1 x i64>* %a, i32 %i.037.0		; <<1 x i64>*> [#uses=1]
-	%tmp19 = load <1 x i64>* %tmp18		; <<1 x i64>> [#uses=1]
-	%tmp21 = add <1 x i64> %tmp19, %tmp14		; <<1 x i64>> [#uses=1]
-	%tmp22 = add <1 x i64> %tmp21, %sum.035.0		; <<1 x i64>> [#uses=2]
-	%tmp25 = add i32 %i.037.0, 1		; <i32> [#uses=2]
-	%tmp29 = icmp ult i32 %tmp25, %count		; <i1> [#uses=1]
-	br i1 %tmp29, label %bb26, label %bb31
-
-bb31:		; preds = %bb26, %entry
-	%sum.035.1 = phi <1 x i64> [ zeroinitializer, %entry ], [ %tmp22, %bb26 ]		; <<1 x i64>> [#uses=1]
-	ret <1 x i64> %sum.035.1
-}
-
-
-; This is the original test converted to use MMX intrinsics.
-
-define <1 x i64> @unsigned_add3a(x86_mmx* %a, x86_mmx* %b, i32 %count) nounwind {
-entry:
-        %tmp2943 = bitcast <1 x i64><i64 0> to x86_mmx
-	%tmp2942 = icmp eq i32 %count, 0		; <i1> [#uses=1]
-	br i1 %tmp2942, label %bb31, label %bb26
-
-bb26:		; preds = %bb26, %entry
-
-; CHECK:  movq	({{.*}},8), %mm
-; CHECK:  paddq	({{.*}},8), %mm
-; CHECK:  paddq	%mm{{[0-7]}}, %mm
-
-	%i.037.0 = phi i32 [ 0, %entry ], [ %tmp25, %bb26 ]		; <i32> [#uses=3]
-	%sum.035.0 = phi x86_mmx [ %tmp2943, %entry ], [ %tmp22, %bb26 ]		; <x86_mmx> [#uses=1]
-	%tmp13 = getelementptr x86_mmx* %b, i32 %i.037.0		; <x86_mmx*> [#uses=1]
-	%tmp14 = load x86_mmx* %tmp13		; <x86_mmx> [#uses=1]
-	%tmp18 = getelementptr x86_mmx* %a, i32 %i.037.0		; <x86_mmx*> [#uses=1]
-	%tmp19 = load x86_mmx* %tmp18		; <x86_mmx> [#uses=1]
-	%tmp21 = call x86_mmx @llvm.x86.mmx.padd.q (x86_mmx %tmp19, x86_mmx %tmp14)		; <x86_mmx> [#uses=1]
-	%tmp22 = call x86_mmx @llvm.x86.mmx.padd.q (x86_mmx %tmp21, x86_mmx %sum.035.0)		; <x86_mmx> [#uses=2]
-	%tmp25 = add i32 %i.037.0, 1		; <i32> [#uses=2]
-	%tmp29 = icmp ult i32 %tmp25, %count		; <i1> [#uses=1]
-	br i1 %tmp29, label %bb26, label %bb31
-
-bb31:		; preds = %bb26, %entry
-	%sum.035.1 = phi x86_mmx [ %tmp2943, %entry ], [ %tmp22, %bb26 ]		; <x86_mmx> [#uses=1]
-        %t = bitcast x86_mmx %sum.035.1 to <1 x i64>
-	ret <1 x i64> %t
-}
-
-declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx)
diff --git a/test/CodeGen/X86/2007-05-05-VecCastExpand.ll b/test/CodeGen/X86/2007-05-05-VecCastExpand.ll
index e58b1932197d..0edf1398295d 100644
--- a/test/CodeGen/X86/2007-05-05-VecCastExpand.ll
+++ b/test/CodeGen/X86/2007-05-05-VecCastExpand.ll
@@ -5,9 +5,9 @@
 
 define void @test() {
 bb.i:
-	%tmp.i660 = load <4 x float>* null		; <<4 x float>> [#uses=1]
-	call void (i32, ...)* @printf( i32 0, i8* getelementptr ([18 x i8]* @str, i32 0, i64 0), double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00 )
-	%tmp152.i = load <4 x i32>* null		; <<4 x i32>> [#uses=1]
+	%tmp.i660 = load <4 x float>, <4 x float>* null		; <<4 x float>> [#uses=1]
+	call void (i32, ...) @printf( i32 0, i8* getelementptr ([18 x i8], [18 x i8]* @str, i32 0, i64 0), double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00 )
+	%tmp152.i = load <4 x i32>, <4 x i32>* null		; <<4 x i32>> [#uses=1]
 	%tmp156.i = bitcast <4 x i32> %tmp152.i to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp175.i = bitcast <4 x float> %tmp.i660 to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp176.i = xor <4 x i32> %tmp156.i, < i32 -1, i32 -1, i32 -1, i32 -1 >		; <<4 x i32>> [#uses=1]
diff --git a/test/CodeGen/X86/2007-05-14-LiveIntervalAssert.ll b/test/CodeGen/X86/2007-05-14-LiveIntervalAssert.ll
index ecc5835405d7..9ce5f5ac63a1 100644
--- a/test/CodeGen/X86/2007-05-14-LiveIntervalAssert.ll
+++ b/test/CodeGen/X86/2007-05-14-LiveIntervalAssert.ll
@@ -19,7 +19,7 @@ cond_true109:		; preds = %entry
 
 cond_next164:		; preds = %cond_true109
 	%tmp176 = call signext i16 @GetParamDesc( %struct.XDesc* null, i32 1701999219, i32 1413830740, %struct.XDesc* null ) 
-	call void (i64, i8*, ...)* @r_raise( i64 0, i8* null )
+	call void (i64, i8*, ...) @r_raise( i64 0, i8* null )
 	unreachable
 
 cond_true239:		; preds = %cond_true109
diff --git a/test/CodeGen/X86/2007-06-04-X86-64-CtorAsmBugs.ll b/test/CodeGen/X86/2007-06-04-X86-64-CtorAsmBugs.ll
index 321e11651b60..1291dc9e6edc 100644
--- a/test/CodeGen/X86/2007-06-04-X86-64-CtorAsmBugs.ll
+++ b/test/CodeGen/X86/2007-06-04-X86-64-CtorAsmBugs.ll
@@ -12,7 +12,7 @@ entry:
 bb.i:		; preds = %bb.i, %entry
 	%i.1.i1.0 = phi i32 [ 0, %entry ], [ %indvar.next, %bb.i ]		; <i32> [#uses=2]
 	%tmp1012.i = sext i32 %i.1.i1.0 to i64		; <i64> [#uses=1]
-	%tmp13.i = getelementptr %struct.A* @_ZN1A1aE, i32 0, i32 0, i64 %tmp1012.i		; <i8*> [#uses=1]
+	%tmp13.i = getelementptr %struct.A, %struct.A* @_ZN1A1aE, i32 0, i32 0, i64 %tmp1012.i		; <i8*> [#uses=1]
 	store i8 0, i8* %tmp13.i
 	%indvar.next = add i32 %i.1.i1.0, 1		; <i32> [#uses=2]
 	%exitcond = icmp eq i32 %indvar.next, 1024		; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/2007-06-15-IntToMMX.ll b/test/CodeGen/X86/2007-06-15-IntToMMX.ll
deleted file mode 100644
index 5612d9eb282c..000000000000
--- a/test/CodeGen/X86/2007-06-15-IntToMMX.ll
+++ /dev/null
@@ -1,19 +0,0 @@
-; RUN: llc < %s -march=x86-64 -mattr=+mmx | FileCheck %s
-
-; CHECK: paddusw
-
-@R = external global x86_mmx          ; <x86_mmx*> [#uses=1]
-
-define void @foo(<1 x i64> %A, <1 x i64> %B) {
-entry:
-        %tmp2 = bitcast <1 x i64> %A to x86_mmx
-        %tmp3 = bitcast <1 x i64> %B to x86_mmx
-        %tmp7 = tail call x86_mmx @llvm.x86.mmx.paddus.w( x86_mmx %tmp2, x86_mmx %tmp3 )   ; <x86_mmx> [#uses=1]
-        store x86_mmx %tmp7, x86_mmx* @R
-        tail call void @llvm.x86.mmx.emms( )
-        ret void
-}
-
-declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx)
-
-declare void @llvm.x86.mmx.emms()
diff --git a/test/CodeGen/X86/2007-06-29-VecFPConstantCSEBug.ll b/test/CodeGen/X86/2007-06-29-VecFPConstantCSEBug.ll
index dc11eec9c17f..87edab77ac19 100644
--- a/test/CodeGen/X86/2007-06-29-VecFPConstantCSEBug.ll
+++ b/test/CodeGen/X86/2007-06-29-VecFPConstantCSEBug.ll
@@ -1,10 +1,10 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse2
 
 define void @test(<4 x float>* %arg) {
-	%tmp89 = getelementptr <4 x float>* %arg, i64 3
+	%tmp89 = getelementptr <4 x float>, <4 x float>* %arg, i64 3
 	%tmp1144 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, zeroinitializer
 	store <4 x float> %tmp1144, <4 x float>* null
-	%tmp1149 = load <4 x float>* %tmp89
+	%tmp1149 = load <4 x float>, <4 x float>* %tmp89
 	%tmp1150 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1149
 	store <4 x float> %tmp1150, <4 x float>* %tmp89
 	ret void
diff --git a/test/CodeGen/X86/2007-07-10-StackerAssert.ll b/test/CodeGen/X86/2007-07-10-StackerAssert.ll
index d611677942c2..c8660f797e2c 100644
--- a/test/CodeGen/X86/2007-07-10-StackerAssert.ll
+++ b/test/CodeGen/X86/2007-07-10-StackerAssert.ll
@@ -22,15 +22,15 @@ cond_true354:		; preds = %bb164
 	ret i32 0
 
 bb383:		; preds = %bb164
-	%tmp408 = load float* null		; <float> [#uses=2]
+	%tmp408 = load float, float* null		; <float> [#uses=2]
 	br i1 false, label %cond_true425, label %cond_next443
 
 cond_true425:		; preds = %bb383
-	%tmp430 = load float* null		; <float> [#uses=1]
+	%tmp430 = load float, float* null		; <float> [#uses=1]
 	%tmp432 = fsub float %tmp430, %tmp408		; <float> [#uses=1]
 	%tmp432433 = fpext float %tmp432 to double		; <double> [#uses=1]
 	%tmp434435 = fpext float %tmp408 to double		; <double> [#uses=1]
-	call void (i8*, ...)* @PR_LogPrint( i8* getelementptr ([56 x i8]* @.str97, i32 0, i32 0), double 0.000000e+00, double %tmp434435, double %tmp432433 )
+	call void (i8*, ...) @PR_LogPrint( i8* getelementptr ([56 x i8], [56 x i8]* @.str97, i32 0, i32 0), double 0.000000e+00, double %tmp434435, double %tmp432433 )
 	ret i32 0
 
 cond_next443:		; preds = %bb383
diff --git a/test/CodeGen/X86/2007-07-18-Vector-Extract.ll b/test/CodeGen/X86/2007-07-18-Vector-Extract.ll
index 6288c4a892c3..63ed4601a04a 100644
--- a/test/CodeGen/X86/2007-07-18-Vector-Extract.ll
+++ b/test/CodeGen/X86/2007-07-18-Vector-Extract.ll
@@ -4,14 +4,14 @@
 ; CHECK: movq 8([[A0]]), %rax
 define i64 @foo_0(<2 x i64>* %val) {
 entry:
-        %val12 = getelementptr <2 x i64>* %val, i32 0, i32 0            ; <i64*> [#uses=1]
-        %tmp7 = load i64* %val12                ; <i64> [#uses=1]
+        %val12 = getelementptr <2 x i64>, <2 x i64>* %val, i32 0, i32 0            ; <i64*> [#uses=1]
+        %tmp7 = load i64, i64* %val12                ; <i64> [#uses=1]
         ret i64 %tmp7
 }
 
 define i64 @foo_1(<2 x i64>* %val) {
 entry:
-        %tmp2.gep = getelementptr <2 x i64>* %val, i32 0, i32 1         ; <i64*> [#uses=1]
-        %tmp4 = load i64* %tmp2.gep             ; <i64> [#uses=1]
+        %tmp2.gep = getelementptr <2 x i64>, <2 x i64>* %val, i32 0, i32 1         ; <i64*> [#uses=1]
+        %tmp4 = load i64, i64* %tmp2.gep             ; <i64> [#uses=1]
         ret i64 %tmp4
 }
diff --git a/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll b/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
index 7768f36efae5..3bf8225abd0a 100644
--- a/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
+++ b/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
@@ -46,14 +46,14 @@ _ubyte_convert2_to_ctypes.exit:		; preds = %entry
 	]
 
 bb4:		; preds = %_ubyte_convert2_to_ctypes.exit, %cond_next.i
-	%tmp5 = load i8*** @PyArray_API, align 8		; <i8**> [#uses=1]
-	%tmp6 = getelementptr i8** %tmp5, i64 2		; <i8**> [#uses=1]
-	%tmp7 = load i8** %tmp6		; <i8*> [#uses=1]
+	%tmp5 = load i8**, i8*** @PyArray_API, align 8		; <i8**> [#uses=1]
+	%tmp6 = getelementptr i8*, i8** %tmp5, i64 2		; <i8**> [#uses=1]
+	%tmp7 = load i8*, i8** %tmp6		; <i8*> [#uses=1]
 	%tmp78 = bitcast i8* %tmp7 to %struct._typeobject*		; <%struct._typeobject*> [#uses=1]
-	%tmp9 = getelementptr %struct._typeobject* %tmp78, i32 0, i32 12		; <%struct.PyNumberMethods**> [#uses=1]
-	%tmp10 = load %struct.PyNumberMethods** %tmp9		; <%struct.PyNumberMethods*> [#uses=1]
-	%tmp11 = getelementptr %struct.PyNumberMethods* %tmp10, i32 0, i32 5		; <%struct.PyObject* (%struct.PyObject*, %struct.PyObject*)**> [#uses=1]
-	%tmp12 = load %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)** %tmp11		; <%struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*> [#uses=1]
+	%tmp9 = getelementptr %struct._typeobject, %struct._typeobject* %tmp78, i32 0, i32 12		; <%struct.PyNumberMethods**> [#uses=1]
+	%tmp10 = load %struct.PyNumberMethods*, %struct.PyNumberMethods** %tmp9		; <%struct.PyNumberMethods*> [#uses=1]
+	%tmp11 = getelementptr %struct.PyNumberMethods, %struct.PyNumberMethods* %tmp10, i32 0, i32 5		; <%struct.PyObject* (%struct.PyObject*, %struct.PyObject*)**> [#uses=1]
+	%tmp12 = load %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)** %tmp11		; <%struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*> [#uses=1]
 	%tmp15 = call %struct.PyObject* %tmp12( %struct.PyObject* %a, %struct.PyObject* %b )		; <%struct.PyObject*> [#uses=1]
 	ret %struct.PyObject* %tmp15
 
@@ -63,38 +63,38 @@ bb17:		; preds = %_ubyte_convert2_to_ctypes.exit, %cond_next.i
 	br i1 %tmp19, label %cond_next, label %UnifiedReturnBlock
 
 cond_next:		; preds = %bb17
-	%tmp22 = load i8*** @PyArray_API, align 8		; <i8**> [#uses=1]
-	%tmp23 = getelementptr i8** %tmp22, i64 10		; <i8**> [#uses=1]
-	%tmp24 = load i8** %tmp23		; <i8*> [#uses=1]
+	%tmp22 = load i8**, i8*** @PyArray_API, align 8		; <i8**> [#uses=1]
+	%tmp23 = getelementptr i8*, i8** %tmp22, i64 10		; <i8**> [#uses=1]
+	%tmp24 = load i8*, i8** %tmp23		; <i8*> [#uses=1]
 	%tmp2425 = bitcast i8* %tmp24 to %struct._typeobject*		; <%struct._typeobject*> [#uses=1]
-	%tmp26 = getelementptr %struct._typeobject* %tmp2425, i32 0, i32 12		; <%struct.PyNumberMethods**> [#uses=1]
-	%tmp27 = load %struct.PyNumberMethods** %tmp26		; <%struct.PyNumberMethods*> [#uses=1]
-	%tmp28 = getelementptr %struct.PyNumberMethods* %tmp27, i32 0, i32 5		; <%struct.PyObject* (%struct.PyObject*, %struct.PyObject*)**> [#uses=1]
-	%tmp29 = load %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)** %tmp28		; <%struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*> [#uses=1]
+	%tmp26 = getelementptr %struct._typeobject, %struct._typeobject* %tmp2425, i32 0, i32 12		; <%struct.PyNumberMethods**> [#uses=1]
+	%tmp27 = load %struct.PyNumberMethods*, %struct.PyNumberMethods** %tmp26		; <%struct.PyNumberMethods*> [#uses=1]
+	%tmp28 = getelementptr %struct.PyNumberMethods, %struct.PyNumberMethods* %tmp27, i32 0, i32 5		; <%struct.PyObject* (%struct.PyObject*, %struct.PyObject*)**> [#uses=1]
+	%tmp29 = load %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)** %tmp28		; <%struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*> [#uses=1]
 	%tmp32 = call %struct.PyObject* %tmp29( %struct.PyObject* %a, %struct.PyObject* %b )		; <%struct.PyObject*> [#uses=1]
 	ret %struct.PyObject* %tmp32
 
 bb35:		; preds = %_ubyte_convert2_to_ctypes.exit, %cond_next.i
-	%tmp36 = load i8*** @PyUFunc_API, align 8		; <i8**> [#uses=1]
-	%tmp37 = getelementptr i8** %tmp36, i64 27		; <i8**> [#uses=1]
-	%tmp38 = load i8** %tmp37		; <i8*> [#uses=1]
+	%tmp36 = load i8**, i8*** @PyUFunc_API, align 8		; <i8**> [#uses=1]
+	%tmp37 = getelementptr i8*, i8** %tmp36, i64 27		; <i8**> [#uses=1]
+	%tmp38 = load i8*, i8** %tmp37		; <i8*> [#uses=1]
 	%tmp3839 = bitcast i8* %tmp38 to void ()*		; <void ()*> [#uses=1]
 	call void %tmp3839( )
-	%tmp40 = load i8* %arg2, align 1		; <i8> [#uses=4]
+	%tmp40 = load i8, i8* %arg2, align 1		; <i8> [#uses=4]
 	%tmp1.i = icmp eq i8 %tmp40, 0		; <i1> [#uses=2]
 	br i1 %tmp1.i, label %cond_true.i, label %cond_false.i
 
 cond_true.i:		; preds = %bb35
 	%tmp3.i196 = call i32 @feraiseexcept( i32 4 )		; <i32> [#uses=0]
-	%tmp46207 = load i8* %arg2, align 1		; <i8> [#uses=3]
-	%tmp48208 = load i8* %arg1, align 1		; <i8> [#uses=2]
+	%tmp46207 = load i8, i8* %arg2, align 1		; <i8> [#uses=3]
+	%tmp48208 = load i8, i8* %arg1, align 1		; <i8> [#uses=2]
 	%tmp1.i197210 = icmp eq i8 %tmp48208, 0		; <i1> [#uses=1]
 	%tmp4.i212 = icmp eq i8 %tmp46207, 0		; <i1> [#uses=1]
 	%tmp7.i198213 = or i1 %tmp1.i197210, %tmp4.i212		; <i1> [#uses=1]
 	br i1 %tmp7.i198213, label %cond_true.i200, label %cond_next17.i
 
 cond_false.i:		; preds = %bb35
-	%tmp42 = load i8* %arg1, align 1		; <i8> [#uses=3]
+	%tmp42 = load i8, i8* %arg1, align 1		; <i8> [#uses=3]
 	%tmp7.i = udiv i8 %tmp42, %tmp40		; <i8> [#uses=2]
 	%tmp1.i197 = icmp eq i8 %tmp42, 0		; <i1> [#uses=1]
 	%tmp7.i198 = or i1 %tmp1.i197, %tmp1.i		; <i1> [#uses=1]
@@ -120,31 +120,31 @@ cond_next17.i:		; preds = %cond_false.i, %cond_true.i
 ubyte_ctype_remainder.exit:		; preds = %cond_next17.i, %cond_true14.i, %cond_true.i200
 	%out2.0 = phi i8 [ %tmp20.i, %cond_next17.i ], [ 0, %cond_true14.i ], [ 0, %cond_true.i200 ]		; <i8> [#uses=1]
 	%out.2 = phi i8 [ %out.1, %cond_next17.i ], [ %out.0, %cond_true14.i ], [ %out.0, %cond_true.i200 ]		; <i8> [#uses=1]
-	%tmp52 = load i8*** @PyUFunc_API, align 8		; <i8**> [#uses=1]
-	%tmp53 = getelementptr i8** %tmp52, i64 28		; <i8**> [#uses=1]
-	%tmp54 = load i8** %tmp53		; <i8*> [#uses=1]
+	%tmp52 = load i8**, i8*** @PyUFunc_API, align 8		; <i8**> [#uses=1]
+	%tmp53 = getelementptr i8*, i8** %tmp52, i64 28		; <i8**> [#uses=1]
+	%tmp54 = load i8*, i8** %tmp53		; <i8*> [#uses=1]
 	%tmp5455 = bitcast i8* %tmp54 to i32 ()*		; <i32 ()*> [#uses=1]
 	%tmp56 = call i32 %tmp5455( )		; <i32> [#uses=2]
 	%tmp58 = icmp eq i32 %tmp56, 0		; <i1> [#uses=1]
 	br i1 %tmp58, label %cond_next89, label %cond_true61
 
 cond_true61:		; preds = %ubyte_ctype_remainder.exit
-	%tmp62 = load i8*** @PyUFunc_API, align 8		; <i8**> [#uses=1]
-	%tmp63 = getelementptr i8** %tmp62, i64 25		; <i8**> [#uses=1]
-	%tmp64 = load i8** %tmp63		; <i8*> [#uses=1]
+	%tmp62 = load i8**, i8*** @PyUFunc_API, align 8		; <i8**> [#uses=1]
+	%tmp63 = getelementptr i8*, i8** %tmp62, i64 25		; <i8**> [#uses=1]
+	%tmp64 = load i8*, i8** %tmp63		; <i8*> [#uses=1]
 	%tmp6465 = bitcast i8* %tmp64 to i32 (i8*, i32*, i32*, %struct.PyObject**)*		; <i32 (i8*, i32*, i32*, %struct.PyObject**)*> [#uses=1]
-	%tmp67 = call i32 %tmp6465( i8* getelementptr ([14 x i8]* @.str5, i32 0, i64 0), i32* %bufsize, i32* %errmask, %struct.PyObject** %errobj )		; <i32> [#uses=1]
+	%tmp67 = call i32 %tmp6465( i8* getelementptr ([14 x i8], [14 x i8]* @.str5, i32 0, i64 0), i32* %bufsize, i32* %errmask, %struct.PyObject** %errobj )		; <i32> [#uses=1]
 	%tmp68 = icmp slt i32 %tmp67, 0		; <i1> [#uses=1]
 	br i1 %tmp68, label %UnifiedReturnBlock, label %cond_next73
 
 cond_next73:		; preds = %cond_true61
 	store i32 1, i32* %first, align 4
-	%tmp74 = load i8*** @PyUFunc_API, align 8		; <i8**> [#uses=1]
-	%tmp75 = getelementptr i8** %tmp74, i64 29		; <i8**> [#uses=1]
-	%tmp76 = load i8** %tmp75		; <i8*> [#uses=1]
+	%tmp74 = load i8**, i8*** @PyUFunc_API, align 8		; <i8**> [#uses=1]
+	%tmp75 = getelementptr i8*, i8** %tmp74, i64 29		; <i8**> [#uses=1]
+	%tmp76 = load i8*, i8** %tmp75		; <i8*> [#uses=1]
 	%tmp7677 = bitcast i8* %tmp76 to i32 (i32, %struct.PyObject*, i32, i32*)*		; <i32 (i32, %struct.PyObject*, i32, i32*)*> [#uses=1]
-	%tmp79 = load %struct.PyObject** %errobj, align 8		; <%struct.PyObject*> [#uses=1]
-	%tmp80 = load i32* %errmask, align 4		; <i32> [#uses=1]
+	%tmp79 = load %struct.PyObject*, %struct.PyObject** %errobj, align 8		; <%struct.PyObject*> [#uses=1]
+	%tmp80 = load i32, i32* %errmask, align 4		; <i32> [#uses=1]
 	%tmp82 = call i32 %tmp7677( i32 %tmp80, %struct.PyObject* %tmp79, i32 %tmp56, i32* %first )		; <i32> [#uses=1]
 	%tmp83 = icmp eq i32 %tmp82, 0		; <i1> [#uses=1]
 	br i1 %tmp83, label %cond_next89, label %UnifiedReturnBlock
@@ -155,70 +155,70 @@ cond_next89:		; preds = %cond_next73, %ubyte_ctype_remainder.exit
 	br i1 %tmp92, label %UnifiedReturnBlock, label %cond_next97
 
 cond_next97:		; preds = %cond_next89
-	%tmp98 = load i8*** @PyArray_API, align 8		; <i8**> [#uses=1]
-	%tmp99 = getelementptr i8** %tmp98, i64 25		; <i8**> [#uses=1]
-	%tmp100 = load i8** %tmp99		; <i8*> [#uses=1]
+	%tmp98 = load i8**, i8*** @PyArray_API, align 8		; <i8**> [#uses=1]
+	%tmp99 = getelementptr i8*, i8** %tmp98, i64 25		; <i8**> [#uses=1]
+	%tmp100 = load i8*, i8** %tmp99		; <i8*> [#uses=1]
 	%tmp100101 = bitcast i8* %tmp100 to %struct._typeobject*		; <%struct._typeobject*> [#uses=2]
-	%tmp102 = getelementptr %struct._typeobject* %tmp100101, i32 0, i32 38		; <%struct.PyObject* (%struct._typeobject*, i64)**> [#uses=1]
-	%tmp103 = load %struct.PyObject* (%struct._typeobject*, i64)** %tmp102		; <%struct.PyObject* (%struct._typeobject*, i64)*> [#uses=1]
+	%tmp102 = getelementptr %struct._typeobject, %struct._typeobject* %tmp100101, i32 0, i32 38		; <%struct.PyObject* (%struct._typeobject*, i64)**> [#uses=1]
+	%tmp103 = load %struct.PyObject* (%struct._typeobject*, i64)*, %struct.PyObject* (%struct._typeobject*, i64)** %tmp102		; <%struct.PyObject* (%struct._typeobject*, i64)*> [#uses=1]
 	%tmp108 = call %struct.PyObject* %tmp103( %struct._typeobject* %tmp100101, i64 0 )		; <%struct.PyObject*> [#uses=3]
 	%tmp110 = icmp eq %struct.PyObject* %tmp108, null		; <i1> [#uses=1]
 	br i1 %tmp110, label %cond_true113, label %cond_next135
 
 cond_true113:		; preds = %cond_next97
-	%tmp115 = getelementptr %struct.PyObject* %tmp90, i32 0, i32 0		; <i64*> [#uses=2]
-	%tmp116 = load i64* %tmp115		; <i64> [#uses=1]
+	%tmp115 = getelementptr %struct.PyObject, %struct.PyObject* %tmp90, i32 0, i32 0		; <i64*> [#uses=2]
+	%tmp116 = load i64, i64* %tmp115		; <i64> [#uses=1]
 	%tmp117 = add i64 %tmp116, -1		; <i64> [#uses=2]
 	store i64 %tmp117, i64* %tmp115
 	%tmp123 = icmp eq i64 %tmp117, 0		; <i1> [#uses=1]
 	br i1 %tmp123, label %cond_true126, label %UnifiedReturnBlock
 
 cond_true126:		; preds = %cond_true113
-	%tmp128 = getelementptr %struct.PyObject* %tmp90, i32 0, i32 1		; <%struct._typeobject**> [#uses=1]
-	%tmp129 = load %struct._typeobject** %tmp128		; <%struct._typeobject*> [#uses=1]
-	%tmp130 = getelementptr %struct._typeobject* %tmp129, i32 0, i32 6		; <void (%struct.PyObject*)**> [#uses=1]
-	%tmp131 = load void (%struct.PyObject*)** %tmp130		; <void (%struct.PyObject*)*> [#uses=1]
+	%tmp128 = getelementptr %struct.PyObject, %struct.PyObject* %tmp90, i32 0, i32 1		; <%struct._typeobject**> [#uses=1]
+	%tmp129 = load %struct._typeobject*, %struct._typeobject** %tmp128		; <%struct._typeobject*> [#uses=1]
+	%tmp130 = getelementptr %struct._typeobject, %struct._typeobject* %tmp129, i32 0, i32 6		; <void (%struct.PyObject*)**> [#uses=1]
+	%tmp131 = load void (%struct.PyObject*)*, void (%struct.PyObject*)** %tmp130		; <void (%struct.PyObject*)*> [#uses=1]
 	call void %tmp131( %struct.PyObject* %tmp90 )
 	ret %struct.PyObject* null
 
 cond_next135:		; preds = %cond_next97
 	%tmp136137 = bitcast %struct.PyObject* %tmp108 to %struct.PyBoolScalarObject*		; <%struct.PyBoolScalarObject*> [#uses=1]
-	%tmp139 = getelementptr %struct.PyBoolScalarObject* %tmp136137, i32 0, i32 2		; <i8*> [#uses=1]
+	%tmp139 = getelementptr %struct.PyBoolScalarObject, %struct.PyBoolScalarObject* %tmp136137, i32 0, i32 2		; <i8*> [#uses=1]
 	store i8 %out.2, i8* %tmp139
 	%tmp140141 = bitcast %struct.PyObject* %tmp90 to %struct.PyTupleObject*		; <%struct.PyTupleObject*> [#uses=2]
-	%tmp143 = getelementptr %struct.PyTupleObject* %tmp140141, i32 0, i32 3, i64 0		; <%struct.PyObject**> [#uses=1]
+	%tmp143 = getelementptr %struct.PyTupleObject, %struct.PyTupleObject* %tmp140141, i32 0, i32 3, i64 0		; <%struct.PyObject**> [#uses=1]
 	store %struct.PyObject* %tmp108, %struct.PyObject** %tmp143
-	%tmp145 = load i8*** @PyArray_API, align 8		; <i8**> [#uses=1]
-	%tmp146 = getelementptr i8** %tmp145, i64 25		; <i8**> [#uses=1]
-	%tmp147 = load i8** %tmp146		; <i8*> [#uses=1]
+	%tmp145 = load i8**, i8*** @PyArray_API, align 8		; <i8**> [#uses=1]
+	%tmp146 = getelementptr i8*, i8** %tmp145, i64 25		; <i8**> [#uses=1]
+	%tmp147 = load i8*, i8** %tmp146		; <i8*> [#uses=1]
 	%tmp147148 = bitcast i8* %tmp147 to %struct._typeobject*		; <%struct._typeobject*> [#uses=2]
-	%tmp149 = getelementptr %struct._typeobject* %tmp147148, i32 0, i32 38		; <%struct.PyObject* (%struct._typeobject*, i64)**> [#uses=1]
-	%tmp150 = load %struct.PyObject* (%struct._typeobject*, i64)** %tmp149		; <%struct.PyObject* (%struct._typeobject*, i64)*> [#uses=1]
+	%tmp149 = getelementptr %struct._typeobject, %struct._typeobject* %tmp147148, i32 0, i32 38		; <%struct.PyObject* (%struct._typeobject*, i64)**> [#uses=1]
+	%tmp150 = load %struct.PyObject* (%struct._typeobject*, i64)*, %struct.PyObject* (%struct._typeobject*, i64)** %tmp149		; <%struct.PyObject* (%struct._typeobject*, i64)*> [#uses=1]
 	%tmp155 = call %struct.PyObject* %tmp150( %struct._typeobject* %tmp147148, i64 0 )		; <%struct.PyObject*> [#uses=3]
 	%tmp157 = icmp eq %struct.PyObject* %tmp155, null		; <i1> [#uses=1]
 	br i1 %tmp157, label %cond_true160, label %cond_next182
 
 cond_true160:		; preds = %cond_next135
-	%tmp162 = getelementptr %struct.PyObject* %tmp90, i32 0, i32 0		; <i64*> [#uses=2]
-	%tmp163 = load i64* %tmp162		; <i64> [#uses=1]
+	%tmp162 = getelementptr %struct.PyObject, %struct.PyObject* %tmp90, i32 0, i32 0		; <i64*> [#uses=2]
+	%tmp163 = load i64, i64* %tmp162		; <i64> [#uses=1]
 	%tmp164 = add i64 %tmp163, -1		; <i64> [#uses=2]
 	store i64 %tmp164, i64* %tmp162
 	%tmp170 = icmp eq i64 %tmp164, 0		; <i1> [#uses=1]
 	br i1 %tmp170, label %cond_true173, label %UnifiedReturnBlock
 
 cond_true173:		; preds = %cond_true160
-	%tmp175 = getelementptr %struct.PyObject* %tmp90, i32 0, i32 1		; <%struct._typeobject**> [#uses=1]
-	%tmp176 = load %struct._typeobject** %tmp175		; <%struct._typeobject*> [#uses=1]
-	%tmp177 = getelementptr %struct._typeobject* %tmp176, i32 0, i32 6		; <void (%struct.PyObject*)**> [#uses=1]
-	%tmp178 = load void (%struct.PyObject*)** %tmp177		; <void (%struct.PyObject*)*> [#uses=1]
+	%tmp175 = getelementptr %struct.PyObject, %struct.PyObject* %tmp90, i32 0, i32 1		; <%struct._typeobject**> [#uses=1]
+	%tmp176 = load %struct._typeobject*, %struct._typeobject** %tmp175		; <%struct._typeobject*> [#uses=1]
+	%tmp177 = getelementptr %struct._typeobject, %struct._typeobject* %tmp176, i32 0, i32 6		; <void (%struct.PyObject*)**> [#uses=1]
+	%tmp178 = load void (%struct.PyObject*)*, void (%struct.PyObject*)** %tmp177		; <void (%struct.PyObject*)*> [#uses=1]
 	call void %tmp178( %struct.PyObject* %tmp90 )
 	ret %struct.PyObject* null
 
 cond_next182:		; preds = %cond_next135
 	%tmp183184 = bitcast %struct.PyObject* %tmp155 to %struct.PyBoolScalarObject*		; <%struct.PyBoolScalarObject*> [#uses=1]
-	%tmp186 = getelementptr %struct.PyBoolScalarObject* %tmp183184, i32 0, i32 2		; <i8*> [#uses=1]
+	%tmp186 = getelementptr %struct.PyBoolScalarObject, %struct.PyBoolScalarObject* %tmp183184, i32 0, i32 2		; <i8*> [#uses=1]
 	store i8 %out2.0, i8* %tmp186
-	%tmp190 = getelementptr %struct.PyTupleObject* %tmp140141, i32 0, i32 3, i64 1		; <%struct.PyObject**> [#uses=1]
+	%tmp190 = getelementptr %struct.PyTupleObject, %struct.PyTupleObject* %tmp140141, i32 0, i32 3, i64 1		; <%struct.PyObject**> [#uses=1]
 	store %struct.PyObject* %tmp155, %struct.PyObject** %tmp190
 	ret %struct.PyObject* %tmp90
 
diff --git a/test/CodeGen/X86/2007-08-13-AppendingLinkage.ll b/test/CodeGen/X86/2007-08-13-AppendingLinkage.ll
index c90a85f16949..e08a5c493b5c 100644
--- a/test/CodeGen/X86/2007-08-13-AppendingLinkage.ll
+++ b/test/CodeGen/X86/2007-08-13-AppendingLinkage.ll
@@ -7,6 +7,6 @@ zeroinitializer
 
 define %hlvm_programs_element* @hlvm_get_programs() {
 entry:
-  ret %hlvm_programs_element* getelementptr([1 x %hlvm_programs_element]*  
+  ret %hlvm_programs_element* getelementptr([1 x %hlvm_programs_element], [1 x %hlvm_programs_element]*  
                                             @hlvm_programs, i32 0, i32 0)
 }
diff --git a/test/CodeGen/X86/2007-09-05-InvalidAsm.ll b/test/CodeGen/X86/2007-09-05-InvalidAsm.ll
index e81534b0110b..eb715125b17d 100644
--- a/test/CodeGen/X86/2007-09-05-InvalidAsm.ll
+++ b/test/CodeGen/X86/2007-09-05-InvalidAsm.ll
@@ -13,33 +13,33 @@ entry:
 
 cond_true:		; preds = %entry
 	%tmp1415 = shl i16 %param, 3		; <i16> [#uses=1]
-	%tmp17 = getelementptr %struct.AGenericCall* %this, i32 0, i32 1		; <%struct.ComponentParameters**> [#uses=1]
-	%tmp18 = load %struct.ComponentParameters** %tmp17, align 8		; <%struct.ComponentParameters*> [#uses=1]
+	%tmp17 = getelementptr %struct.AGenericCall, %struct.AGenericCall* %this, i32 0, i32 1		; <%struct.ComponentParameters**> [#uses=1]
+	%tmp18 = load %struct.ComponentParameters*, %struct.ComponentParameters** %tmp17, align 8		; <%struct.ComponentParameters*> [#uses=1]
 	%tmp1920 = bitcast %struct.ComponentParameters* %tmp18 to i8*		; <i8*> [#uses=1]
 	%tmp212223 = sext i16 %tmp1415 to i64		; <i64> [#uses=1]
-	%tmp24 = getelementptr i8* %tmp1920, i64 %tmp212223		; <i8*> [#uses=1]
+	%tmp24 = getelementptr i8, i8* %tmp1920, i64 %tmp212223		; <i8*> [#uses=1]
 	%tmp2425 = bitcast i8* %tmp24 to i64*		; <i64*> [#uses=1]
-	%tmp28 = load i64* %tmp2425, align 8		; <i64> [#uses=1]
+	%tmp28 = load i64, i64* %tmp2425, align 8		; <i64> [#uses=1]
 	%tmp2829 = inttoptr i64 %tmp28 to i32*		; <i32*> [#uses=1]
-	%tmp31 = getelementptr %struct.AGenericCall* %this, i32 0, i32 2		; <i32**> [#uses=1]
+	%tmp31 = getelementptr %struct.AGenericCall, %struct.AGenericCall* %this, i32 0, i32 2		; <i32**> [#uses=1]
 	store i32* %tmp2829, i32** %tmp31, align 8
 	br label %cond_next
 
 cond_next:		; preds = %cond_true, %entry
 	%tmp4243 = shl i16 %param, 3		; <i16> [#uses=1]
-	%tmp46 = getelementptr %struct.AGenericCall* %this, i32 0, i32 1		; <%struct.ComponentParameters**> [#uses=1]
-	%tmp47 = load %struct.ComponentParameters** %tmp46, align 8		; <%struct.ComponentParameters*> [#uses=1]
+	%tmp46 = getelementptr %struct.AGenericCall, %struct.AGenericCall* %this, i32 0, i32 1		; <%struct.ComponentParameters**> [#uses=1]
+	%tmp47 = load %struct.ComponentParameters*, %struct.ComponentParameters** %tmp46, align 8		; <%struct.ComponentParameters*> [#uses=1]
 	%tmp4849 = bitcast %struct.ComponentParameters* %tmp47 to i8*		; <i8*> [#uses=1]
 	%tmp505152 = sext i16 %tmp4243 to i64		; <i64> [#uses=1]
-	%tmp53 = getelementptr i8* %tmp4849, i64 %tmp505152		; <i8*> [#uses=1]
+	%tmp53 = getelementptr i8, i8* %tmp4849, i64 %tmp505152		; <i8*> [#uses=1]
 	%tmp5354 = bitcast i8* %tmp53 to i64*		; <i64*> [#uses=1]
-	%tmp58 = load i64* %tmp5354, align 8		; <i64> [#uses=1]
+	%tmp58 = load i64, i64* %tmp5354, align 8		; <i64> [#uses=1]
 	%tmp59 = icmp eq i64 %tmp58, 0		; <i1> [#uses=1]
 	br i1 %tmp59, label %UnifiedReturnBlock, label %cond_true63
 
 cond_true63:		; preds = %cond_next
-	%tmp65 = getelementptr %struct.AGenericCall* %this, i32 0, i32 0		; <%struct.AGenericManager**> [#uses=1]
-	%tmp66 = load %struct.AGenericManager** %tmp65, align 8		; <%struct.AGenericManager*> [#uses=1]
+	%tmp65 = getelementptr %struct.AGenericCall, %struct.AGenericCall* %this, i32 0, i32 0		; <%struct.AGenericManager**> [#uses=1]
+	%tmp66 = load %struct.AGenericManager*, %struct.AGenericManager** %tmp65, align 8		; <%struct.AGenericManager*> [#uses=1]
 	%tmp69 = tail call i32 @_ZN15AGenericManager24DefaultComponentInstanceERP23ComponentInstanceRecord( %struct.AGenericManager* %tmp66, %struct.ComponentInstanceRecord** %instance )		; <i32> [#uses=1]
 	ret i32 %tmp69
 
diff --git a/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll b/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll
index 6fc8ec907eac..7eb018ce525f 100644
--- a/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll
+++ b/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll
@@ -5,7 +5,7 @@
 
 define fastcc void @sample_3d_linear(%struct.gl_texture_object* %tObj, %struct.gl_texture_image* %img, float %s, float %t, float %r, i8* %red, i8* %green, i8* %blue, i8* %alpha) {
 entry:
-	%tmp15 = load i32* null, align 4		; <i32> [#uses=1]
+	%tmp15 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	%tmp16 = icmp eq i32 %tmp15, 10497		; <i1> [#uses=1]
 	%tmp2152 = call float @floorf( float 0.000000e+00 )		; <float> [#uses=0]
 	br i1 %tmp16, label %cond_true, label %cond_false
diff --git a/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll b/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
index d3a47aefb7d0..c535392ffdfc 100644
--- a/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
+++ b/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
@@ -7,15 +7,15 @@ entry:
 cond_next127:		; preds = %cond_next391, %entry
 	%v.1 = phi i32 [ undef, %entry ], [ %tmp411, %cond_next391 ]		; <i32> [#uses=1]
 	%tmp149 = mul i32 0, %v.1		; <i32> [#uses=0]
-	%tmpss = load i32* %ss, align 4		; <i32> [#uses=1]
-	%tmpbp = load i32* %bp, align 4		; <i32> [#uses=2]
+	%tmpss = load i32, i32* %ss, align 4		; <i32> [#uses=1]
+	%tmpbp = load i32, i32* %bp, align 4		; <i32> [#uses=2]
 	%tmp254 = and i32 %tmpss, 15		; <i32> [#uses=1]
 	%tmp256 = and i32 %tmpbp, 15		; <i32> [#uses=2]
 	br label %cond_next391
 
 cond_next391:		; preds = %cond_next127
-	%tmp393 = load i32* %ss, align 4		; <i32> [#uses=1]
-	%tmp395 = load i32* %bp, align 4		; <i32> [#uses=2]
+	%tmp393 = load i32, i32* %ss, align 4		; <i32> [#uses=1]
+	%tmp395 = load i32, i32* %bp, align 4		; <i32> [#uses=2]
 	%tmp396 = shl i32 %tmp393, %tmp395		; <i32> [#uses=2]
 	%tmp398 = sub i32 32, %tmp256		; <i32> [#uses=2]
 	%tmp399 = lshr i32 %tmp396, %tmp398		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2007-10-12-SpillerUnfold1.ll b/test/CodeGen/X86/2007-10-12-SpillerUnfold1.ll
index ea1bbc464693..c4d5cb970c3f 100644
--- a/test/CodeGen/X86/2007-10-12-SpillerUnfold1.ll
+++ b/test/CodeGen/X86/2007-10-12-SpillerUnfold1.ll
@@ -6,20 +6,20 @@ entry:
 
 bb171.preheader:		; preds = %entry
 	%tmp176 = fadd float 0.000000e+00, 1.000000e+00		; <float> [#uses=2]
-	%gi.1 = getelementptr float* %fz, i32 0		; <float*> [#uses=2]
-	%tmp240 = load float* %gi.1, align 4		; <float> [#uses=1]
+	%gi.1 = getelementptr float, float* %fz, i32 0		; <float*> [#uses=2]
+	%tmp240 = load float, float* %gi.1, align 4		; <float> [#uses=1]
 	%tmp242 = fsub float %tmp240, 0.000000e+00		; <float> [#uses=2]
-	%tmp251 = getelementptr float* %fz, i32 0		; <float*> [#uses=1]
-	%tmp252 = load float* %tmp251, align 4		; <float> [#uses=1]
-	%tmp258 = getelementptr float* %fz, i32 0		; <float*> [#uses=2]
-	%tmp259 = load float* %tmp258, align 4		; <float> [#uses=2]
+	%tmp251 = getelementptr float, float* %fz, i32 0		; <float*> [#uses=1]
+	%tmp252 = load float, float* %tmp251, align 4		; <float> [#uses=1]
+	%tmp258 = getelementptr float, float* %fz, i32 0		; <float*> [#uses=2]
+	%tmp259 = load float, float* %tmp258, align 4		; <float> [#uses=2]
 	%tmp261 = fmul float %tmp259, %tmp176		; <float> [#uses=1]
 	%tmp262 = fsub float 0.000000e+00, %tmp261		; <float> [#uses=2]
 	%tmp269 = fmul float %tmp252, %tmp176		; <float> [#uses=1]
 	%tmp276 = fmul float %tmp259, 0.000000e+00		; <float> [#uses=1]
 	%tmp277 = fadd float %tmp269, %tmp276		; <float> [#uses=2]
-	%tmp281 = getelementptr float* %fz, i32 0		; <float*> [#uses=1]
-	%tmp282 = load float* %tmp281, align 4		; <float> [#uses=2]
+	%tmp281 = getelementptr float, float* %fz, i32 0		; <float*> [#uses=1]
+	%tmp282 = load float, float* %tmp281, align 4		; <float> [#uses=2]
 	%tmp284 = fsub float %tmp282, %tmp277		; <float> [#uses=1]
 	%tmp291 = fadd float %tmp282, %tmp277		; <float> [#uses=1]
 	%tmp298 = fsub float 0.000000e+00, %tmp262		; <float> [#uses=1]
diff --git a/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll b/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
index 1ec9c70d570c..4b1c1d77f7a0 100644
--- a/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
+++ b/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
@@ -22,13 +22,13 @@ cond_next245:		; preds = %cond_next127
 	br i1 false, label %cond_true267, label %cond_next391
 
 cond_true267:		; preds = %cond_next245
-	%tmp269 = load i8** %byteptr, align 4		; <i8*> [#uses=3]
-	%tmp270 = load i8* %tmp269, align 1		; <i8> [#uses=1]
+	%tmp269 = load i8*, i8** %byteptr, align 4		; <i8*> [#uses=3]
+	%tmp270 = load i8, i8* %tmp269, align 1		; <i8> [#uses=1]
 	%tmp270271 = zext i8 %tmp270 to i32		; <i32> [#uses=1]
-	%tmp272 = getelementptr i8* %tmp269, i32 1		; <i8*> [#uses=2]
+	%tmp272 = getelementptr i8, i8* %tmp269, i32 1		; <i8*> [#uses=2]
 	store i8* %tmp272, i8** %byteptr, align 4
-	%tmp276 = load i8* %tmp272, align 1		; <i8> [#uses=1]
-	%tmp278 = getelementptr i8* %tmp269, i32 2		; <i8*> [#uses=1]
+	%tmp276 = load i8, i8* %tmp272, align 1		; <i8> [#uses=1]
+	%tmp278 = getelementptr i8, i8* %tmp269, i32 2		; <i8*> [#uses=1]
 	store i8* %tmp278, i8** %byteptr, align 4
 	%tmp286 = icmp eq i32 %tmp270271, %markerPrefix		; <i1> [#uses=1]
 	%cond = icmp eq i8 %tmp276, 0		; <i1> [#uses=1]
@@ -42,7 +42,7 @@ cond_next327:		; preds = %cond_true267
 	br i1 false, label %cond_true343, label %cond_next391
 
 cond_true343:		; preds = %cond_next327
-	%tmp345 = load i8** %byteptr, align 4		; <i8*> [#uses=1]
+	%tmp345 = load i8*, i8** %byteptr, align 4		; <i8*> [#uses=1]
 	store i8* null, i8** %byteptr, align 4
 	store i8* %tmp345, i8** %byteptr, align 4
 	br label %cond_next391
diff --git a/test/CodeGen/X86/2007-10-14-CoalescerCrash.ll b/test/CodeGen/X86/2007-10-14-CoalescerCrash.ll
index 8a55935cc1f8..941925987fd4 100644
--- a/test/CodeGen/X86/2007-10-14-CoalescerCrash.ll
+++ b/test/CodeGen/X86/2007-10-14-CoalescerCrash.ll
@@ -10,8 +10,8 @@ bb:             ; preds = %bb31, %entry
         br i1 false, label %bb6, label %bb31
 
 bb6:            ; preds = %bb
-        %tmp10 = load i64* null, align 8                ; <i64> [#uses=1]
-        %tmp16 = load i64* null, align 8                ; <i64> [#uses=1]
+        %tmp10 = load i64, i64* null, align 8                ; <i64> [#uses=1]
+        %tmp16 = load i64, i64* null, align 8                ; <i64> [#uses=1]
         br i1 false, label %bb23, label %bb31
 
 bb23:           ; preds = %bb6
diff --git a/test/CodeGen/X86/2007-10-15-CoalescerCrash.ll b/test/CodeGen/X86/2007-10-15-CoalescerCrash.ll
index 2b56b4ea7129..c6eb6f0f0d7a 100644
--- a/test/CodeGen/X86/2007-10-15-CoalescerCrash.ll
+++ b/test/CodeGen/X86/2007-10-15-CoalescerCrash.ll
@@ -362,7 +362,7 @@ bb1159:		; preds = %cond_next1150
 
 cond_true1169:		; preds = %bb1159
 	%tmp11741175 = trunc i64 %lsum.11225.0 to i32		; <i32> [#uses=1]
-	%tmp1178 = tail call i32 (%struct._IO_FILE*  , i8*  , ...)* @fprintf( %struct._IO_FILE* noalias %file  , i8* getelementptr ([49 x i8]* @.str32, i32 0, i64 0)  , i32 %tmp11741175, i32 0 )		; <i32> [#uses=0]
+	%tmp1178 = tail call i32 (%struct._IO_FILE*  , i8*  , ...) @fprintf( %struct._IO_FILE* noalias %file  , i8* getelementptr ([49 x i8], [49 x i8]* @.str32, i32 0, i64 0)  , i32 %tmp11741175, i32 0 )		; <i32> [#uses=0]
 	ret void
 
 UnifiedReturnBlock:		; preds = %bb1159
diff --git a/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll b/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll
index 82052b13e18d..30e1f575caf0 100644
--- a/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll
+++ b/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll
@@ -25,7 +25,7 @@ cond_next127:		; preds = %cond_true, %bb
 	%tmp154155156 = sext i16 %tmp154155 to i32		; <i32> [#uses=1]
 	%tmp158 = xor i32 %tmp154155156, %tmp153		; <i32> [#uses=1]
 	%tmp160 = or i32 %tmp158, %cnt.0		; <i32> [#uses=1]
-	%tmp171 = load i32* %bitptr, align 4		; <i32> [#uses=1]
+	%tmp171 = load i32, i32* %bitptr, align 4		; <i32> [#uses=1]
 	%tmp180181 = sext i16 0 to i32		; <i32> [#uses=3]
 	%tmp183 = add i32 %tmp160, 1		; <i32> [#uses=1]
 	br i1 false, label %cond_true188, label %cond_next245
@@ -54,7 +54,7 @@ cond_next327:		; preds = %cond_true267
 	br i1 false, label %cond_true343, label %cond_next385
 
 cond_true343:		; preds = %cond_next327
-	%tmp345 = load i8** %byteptr, align 4		; <i8*> [#uses=1]
+	%tmp345 = load i8*, i8** %byteptr, align 4		; <i8*> [#uses=1]
 	store i8* null, i8** %byteptr, align 4
 	br i1 false, label %cond_next385, label %cond_true352
 
@@ -69,8 +69,8 @@ cond_next385:		; preds = %cond_true352, %cond_true343, %cond_next327
 	br label %cond_next391
 
 cond_next391:		; preds = %cond_next385, %cond_next245
-	%tmp393 = load i32* %source, align 4		; <i32> [#uses=1]
-	%tmp395 = load i32* %bitptr, align 4		; <i32> [#uses=2]
+	%tmp393 = load i32, i32* %source, align 4		; <i32> [#uses=1]
+	%tmp395 = load i32, i32* %bitptr, align 4		; <i32> [#uses=2]
 	%tmp396 = shl i32 %tmp393, %tmp395		; <i32> [#uses=1]
 	%tmp398 = sub i32 32, %tmp256		; <i32> [#uses=1]
 	%tmp405 = lshr i32 %tmp396, 31		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll b/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
index 573a2177b74e..9f57df87fe48 100644
--- a/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
+++ b/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
@@ -2,7 +2,7 @@
 
 define signext i16 @t()   {
 entry:
-	%tmp180 = load i16* null, align 2		; <i16> [#uses=3]
+	%tmp180 = load i16, i16* null, align 2		; <i16> [#uses=3]
 	%tmp180181 = sext i16 %tmp180 to i32		; <i32> [#uses=1]
 	%tmp185 = icmp slt i16 %tmp180, 0		; <i1> [#uses=1]
 	br i1 %tmp185, label %cond_true188, label %cond_next245
diff --git a/test/CodeGen/X86/2007-10-30-LSRCrash.ll b/test/CodeGen/X86/2007-10-30-LSRCrash.ll
index 42db98b44750..d945d57fad7c 100644
--- a/test/CodeGen/X86/2007-10-30-LSRCrash.ll
+++ b/test/CodeGen/X86/2007-10-30-LSRCrash.ll
@@ -19,7 +19,7 @@ bb76.split:		; preds = %bb69.outer.split.split, %bb69.us208
 bb69.outer:		; preds = %bb76.split, %bb98.preheader
 	%from.0.reg2mem.0.ph.rec = phi i32 [ %tmp75.rec, %bb76.split ], [ 0, %bb98.preheader ]		; <i32> [#uses=1]
 	%tmp75.rec = add i32 %from.0.reg2mem.0.ph.rec, 1		; <i32> [#uses=2]
-	%tmp75 = getelementptr i8* null, i32 %tmp75.rec		; <i8*> [#uses=6]
+	%tmp75 = getelementptr i8, i8* null, i32 %tmp75.rec		; <i8*> [#uses=6]
 	br i1 false, label %bb69.us208, label %bb69.outer.split.split
 
 bb69.us208:		; preds = %bb69.outer
diff --git a/test/CodeGen/X86/2007-10-31-extractelement-i64.ll b/test/CodeGen/X86/2007-10-31-extractelement-i64.ll
index 1b8e67dcc9b3..3d52b6cf7b3e 100644
--- a/test/CodeGen/X86/2007-10-31-extractelement-i64.ll
+++ b/test/CodeGen/X86/2007-10-31-extractelement-i64.ll
@@ -9,16 +9,16 @@ entry:
 	%retval = alloca <1 x i64>, align 8		; <<1 x i64>*> [#uses=3]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store <2 x i64> %__A, <2 x i64>* %__A_addr
-	%tmp = load <2 x i64>* %__A_addr, align 16		; <<2 x i64>> [#uses=1]
+	%tmp = load <2 x i64>, <2 x i64>* %__A_addr, align 16		; <<2 x i64>> [#uses=1]
 	%tmp1 = bitcast <2 x i64> %tmp to <2 x i64>		; <<2 x i64>> [#uses=1]
 	%tmp2 = extractelement <2 x i64> %tmp1, i32 0		; <i64> [#uses=1]
 	%tmp3 = bitcast i64 %tmp2 to <1 x i64>		; <<1 x i64>> [#uses=1]
 	store <1 x i64> %tmp3, <1 x i64>* %retval, align 8
-	%tmp4 = load <1 x i64>* %retval, align 8		; <<1 x i64>> [#uses=0]
+	%tmp4 = load <1 x i64>, <1 x i64>* %retval, align 8		; <<1 x i64>> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
-	%retval5 = load <1 x i64>* %retval		; <<1 x i64>> [#uses=1]
+	%retval5 = load <1 x i64>, <1 x i64>* %retval		; <<1 x i64>> [#uses=1]
 	ret <1 x i64> %retval5
 }
 
@@ -28,16 +28,16 @@ entry:
 	%retval = alloca <1 x i64>, align 8		; <<1 x i64>*> [#uses=3]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store <2 x i64> %__A, <2 x i64>* %__A_addr
-	%tmp = load <2 x i64>* %__A_addr, align 16		; <<2 x i64>> [#uses=1]
+	%tmp = load <2 x i64>, <2 x i64>* %__A_addr, align 16		; <<2 x i64>> [#uses=1]
 	%tmp1 = bitcast <2 x i64> %tmp to <2 x i64>		; <<2 x i64>> [#uses=1]
 	%tmp2 = extractelement <2 x i64> %tmp1, i32 1		; <i64> [#uses=1]
 	%tmp3 = bitcast i64 %tmp2 to <1 x i64>		; <<1 x i64>> [#uses=1]
 	store <1 x i64> %tmp3, <1 x i64>* %retval, align 8
-	%tmp4 = load <1 x i64>* %retval, align 8		; <<1 x i64>> [#uses=0]
+	%tmp4 = load <1 x i64>, <1 x i64>* %retval, align 8		; <<1 x i64>> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
-	%retval5 = load <1 x i64>* %retval		; <<1 x i64>> [#uses=1]
+	%retval5 = load <1 x i64>, <1 x i64>* %retval		; <<1 x i64>> [#uses=1]
 	ret <1 x i64> %retval5
 }
 
@@ -48,16 +48,16 @@ entry:
 	%tmp = alloca i64, align 8		; <i64*> [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store <2 x i64> %__A, <2 x i64>* %__A_addr
-	%tmp1 = load <2 x i64>* %__A_addr, align 16		; <<2 x i64>> [#uses=1]
+	%tmp1 = load <2 x i64>, <2 x i64>* %__A_addr, align 16		; <<2 x i64>> [#uses=1]
 	%tmp2 = bitcast <2 x i64> %tmp1 to <2 x i64>		; <<2 x i64>> [#uses=1]
 	%tmp3 = extractelement <2 x i64> %tmp2, i32 0		; <i64> [#uses=1]
 	store i64 %tmp3, i64* %tmp, align 8
-	%tmp4 = load i64* %tmp, align 8		; <i64> [#uses=1]
+	%tmp4 = load i64, i64* %tmp, align 8		; <i64> [#uses=1]
 	store i64 %tmp4, i64* %retval, align 8
 	br label %return
 
 return:		; preds = %entry
-	%retval5 = load i64* %retval		; <i64> [#uses=1]
+	%retval5 = load i64, i64* %retval		; <i64> [#uses=1]
 	ret i64 %retval5
 }
 
@@ -68,15 +68,15 @@ entry:
 	%tmp = alloca i64, align 8		; <i64*> [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store <2 x i64> %__A, <2 x i64>* %__A_addr
-	%tmp1 = load <2 x i64>* %__A_addr, align 16		; <<2 x i64>> [#uses=1]
+	%tmp1 = load <2 x i64>, <2 x i64>* %__A_addr, align 16		; <<2 x i64>> [#uses=1]
 	%tmp2 = bitcast <2 x i64> %tmp1 to <2 x i64>		; <<2 x i64>> [#uses=1]
 	%tmp3 = extractelement <2 x i64> %tmp2, i32 1		; <i64> [#uses=1]
 	store i64 %tmp3, i64* %tmp, align 8
-	%tmp4 = load i64* %tmp, align 8		; <i64> [#uses=1]
+	%tmp4 = load i64, i64* %tmp, align 8		; <i64> [#uses=1]
 	store i64 %tmp4, i64* %retval, align 8
 	br label %return
 
 return:		; preds = %entry
-	%retval5 = load i64* %retval		; <i64> [#uses=1]
+	%retval5 = load i64, i64* %retval		; <i64> [#uses=1]
 	ret i64 %retval5
 }
diff --git a/test/CodeGen/X86/2007-11-04-LiveIntervalCrash.ll b/test/CodeGen/X86/2007-11-04-LiveIntervalCrash.ll
index 404561848b71..a20fb47d7b10 100644
--- a/test/CodeGen/X86/2007-11-04-LiveIntervalCrash.ll
+++ b/test/CodeGen/X86/2007-11-04-LiveIntervalCrash.ll
@@ -12,7 +12,7 @@ entry:
 bb:             ; preds = %bb, %entry
         %name8.0.reg2mem.0.rec = phi i64 [ %indvar.next, %bb ], [ 0, %entry ]           ; <i64> [#uses=1]
         %hash.0.reg2mem.0 = phi i64 [ %tmp27, %bb ], [ 0, %entry ]              ; <i64> [#uses=1]
-        %tmp13 = load i8* null, align 1         ; <i8> [#uses=1]
+        %tmp13 = load i8, i8* null, align 1         ; <i8> [#uses=1]
         %tmp1314 = zext i8 %tmp13 to i64                ; <i64> [#uses=1]
         %tmp25 = lshr i64 %tmp1314, 4           ; <i64> [#uses=1]
         %tmp22 = add i64 %tmp25, %hash.0.reg2mem.0              ; <i64> [#uses=1]
@@ -30,7 +30,7 @@ bb37:           ; preds = %bb37.loopexit, %entry
         %hash.0.reg2mem.1 = phi i32 [ %phitmp, %bb37.loopexit ], [ 0, %entry ]          ; <i32> [#uses=1]
         store i32 %hash.0.reg2mem.1, i32* null, align 8
         %tmp75 = tail call i32 null( %struct.dentry* %dir, %struct.qstr* %name )                ; <i32> [#uses=0]
-        %tmp84 = tail call i32 (...)* @d_lookup( %struct.dentry* %dir, %struct.qstr* %name )            ; <i32> [#uses=0]
+        %tmp84 = tail call i32 (...) @d_lookup( %struct.dentry* %dir, %struct.qstr* %name )            ; <i32> [#uses=0]
         ret %struct.dentry* null
 }
 
diff --git a/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll b/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll
index d1699d557113..4618e4b68980 100644
--- a/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll
+++ b/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll
@@ -8,6 +8,6 @@ target triple = "x86_64-pc-linux"
 
 define i32 @unknown_bootoption() {
 entry:
-	tail call void asm sideeffect "foo ${0:c}\0A", "i,~{dirflag},~{fpsr},~{flags}"( i8* getelementptr ([12 x i8]* @str, i32 0, i64 0) )
+	tail call void asm sideeffect "foo ${0:c}\0A", "i,~{dirflag},~{fpsr},~{flags}"( i8* getelementptr ([12 x i8], [12 x i8]* @str, i32 0, i64 0) )
 	ret i32 undef
 }
diff --git a/test/CodeGen/X86/2007-11-06-InstrSched.ll b/test/CodeGen/X86/2007-11-06-InstrSched.ll
index 838a0c35646f..d88b45f68390 100644
--- a/test/CodeGen/X86/2007-11-06-InstrSched.ll
+++ b/test/CodeGen/X86/2007-11-06-InstrSched.ll
@@ -8,11 +8,11 @@ entry:
 bb18:		; preds = %bb18, %entry
 	%i.0.reg2mem.0 = phi i32 [ 0, %entry ], [ %tmp17, %bb18 ]		; <i32> [#uses=3]
 	%res.0.reg2mem.0 = phi float [ 0.000000e+00, %entry ], [ %tmp14, %bb18 ]		; <float> [#uses=1]
-	%tmp3 = getelementptr i32* %x, i32 %i.0.reg2mem.0		; <i32*> [#uses=1]
-	%tmp4 = load i32* %tmp3, align 4		; <i32> [#uses=1]
+	%tmp3 = getelementptr i32, i32* %x, i32 %i.0.reg2mem.0		; <i32*> [#uses=1]
+	%tmp4 = load i32, i32* %tmp3, align 4		; <i32> [#uses=1]
 	%tmp45 = sitofp i32 %tmp4 to float		; <float> [#uses=1]
-	%tmp8 = getelementptr float* %y, i32 %i.0.reg2mem.0		; <float*> [#uses=1]
-	%tmp9 = load float* %tmp8, align 4		; <float> [#uses=1]
+	%tmp8 = getelementptr float, float* %y, i32 %i.0.reg2mem.0		; <float*> [#uses=1]
+	%tmp9 = load float, float* %tmp8, align 4		; <float> [#uses=1]
 	%tmp11 = fmul float %tmp9, %tmp45		; <float> [#uses=1]
 	%tmp14 = fadd float %tmp11, %res.0.reg2mem.0		; <float> [#uses=2]
 	%tmp17 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=2]
diff --git a/test/CodeGen/X86/2007-11-07-MulBy4.ll b/test/CodeGen/X86/2007-11-07-MulBy4.ll
index d5b630b59d9f..06e0a779be1b 100644
--- a/test/CodeGen/X86/2007-11-07-MulBy4.ll
+++ b/test/CodeGen/X86/2007-11-07-MulBy4.ll
@@ -7,7 +7,7 @@
 
 define fastcc i32 @foo(i16* %eptr, i8* %ecode, %struct.foo_data* %md, i32 %ims) {
 entry:
-	%tmp36 = load i32* null, align 4		; <i32> [#uses=1]
+	%tmp36 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	%tmp37 = icmp ult i32 0, %tmp36		; <i1> [#uses=1]
 	br i1 %tmp37, label %cond_next79, label %cond_true
 
@@ -15,7 +15,7 @@ cond_true:		; preds = %entry
 	ret i32 0
 
 cond_next79:		; preds = %entry
-	%tmp85 = load i32* null, align 4		; <i32> [#uses=1]
+	%tmp85 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	%tmp86 = icmp ult i32 0, %tmp85		; <i1> [#uses=1]
 	br i1 %tmp86, label %cond_next130, label %cond_true89
 
diff --git a/test/CodeGen/X86/2007-12-16-BURRSchedCrash.ll b/test/CodeGen/X86/2007-12-16-BURRSchedCrash.ll
index 455de91d30ab..3404fe61fc12 100644
--- a/test/CodeGen/X86/2007-12-16-BURRSchedCrash.ll
+++ b/test/CodeGen/X86/2007-12-16-BURRSchedCrash.ll
@@ -13,14 +13,14 @@ bb848:		; preds = %entry
 	ret void
 
 bb1271:		; preds = %bb898
-	%tmp1272 = getelementptr %struct.c34007g__pkg__parent* %x8, i32 0, i32 0		; <i32**> [#uses=1]
+	%tmp1272 = getelementptr %struct.c34007g__pkg__parent, %struct.c34007g__pkg__parent* %x8, i32 0, i32 0		; <i32**> [#uses=1]
 	%x82167 = bitcast %struct.c34007g__pkg__parent* %x8 to i64*		; <i64*> [#uses=1]
 	br i1 true, label %bb4668, label %bb848
 
 bb4668:		; preds = %bb4648
-	%tmp5464 = load i64* %x82167, align 8		; <i64> [#uses=1]
+	%tmp5464 = load i64, i64* %x82167, align 8		; <i64> [#uses=1]
 	%tmp5467 = icmp ne i64 0, %tmp5464		; <i1> [#uses=1]
-	%tmp5470 = load i32** %tmp1272, align 8		; <i32*> [#uses=1]
+	%tmp5470 = load i32*, i32** %tmp1272, align 8		; <i32*> [#uses=1]
 	%tmp5471 = icmp eq i32* %tmp5470, null		; <i1> [#uses=1]
 	call fastcc void @c34007g__pkg__create.311( %struct.c34007g__pkg__parent* null, i32 7, i32 9, i32 2, i32 4, i32 1 )
 	%tmp5475 = or i1 %tmp5471, %tmp5467		; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll b/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll
index 99df20da2510..26d18273dd47 100644
--- a/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll
+++ b/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll
@@ -7,14 +7,14 @@
 define void @_ada_c34007g() {
 entry:
 	%x8 = alloca %struct.c34007g__pkg__parent, align 8		; <%struct.c34007g__pkg__parent*> [#uses=2]
-	%tmp1272 = getelementptr %struct.c34007g__pkg__parent* %x8, i32 0, i32 0		; <i32**> [#uses=1]
+	%tmp1272 = getelementptr %struct.c34007g__pkg__parent, %struct.c34007g__pkg__parent* %x8, i32 0, i32 0		; <i32**> [#uses=1]
 	%x82167 = bitcast %struct.c34007g__pkg__parent* %x8 to i64*		; <i64*> [#uses=1]
 	br i1 true, label %bb4668, label %bb848
 
 bb4668:		; preds = %bb4648
-	%tmp5464 = load i64* %x82167, align 8		; <i64> [#uses=1]
+	%tmp5464 = load i64, i64* %x82167, align 8		; <i64> [#uses=1]
 	%tmp5467 = icmp ne i64 0, %tmp5464		; <i1> [#uses=1]
-	%tmp5470 = load i32** %tmp1272, align 8		; <i32*> [#uses=1]
+	%tmp5470 = load i32*, i32** %tmp1272, align 8		; <i32*> [#uses=1]
 	%tmp5471 = icmp eq i32* %tmp5470, null		; <i1> [#uses=1]
 	%tmp5475 = or i1 %tmp5471, %tmp5467		; <i1> [#uses=1]
 	%tmp5497 = or i1 %tmp5475, false		; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll b/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll
index 9b9b781cfa2e..7da85d3a9a1d 100644
--- a/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll
+++ b/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll
@@ -20,14 +20,14 @@ bb917:		; preds = %entry
 
 bb951:		; preds = %bb986, %entry
 	%tmp955 = sdiv i32 %offset, 2		; <i32> [#uses=3]
-	%tmp961 = getelementptr %struct.indexentry* null, i32 %tmp955, i32 0		; <i32*> [#uses=1]
+	%tmp961 = getelementptr %struct.indexentry, %struct.indexentry* null, i32 %tmp955, i32 0		; <i32*> [#uses=1]
 	br i1 %cond, label %bb986, label %bb967
 
 bb967:		; preds = %bb951
 	ret i32 0
 
 bb986:		; preds = %bb951
-	%tmp993 = load i32* %tmp961, align 4		; <i32> [#uses=1]
+	%tmp993 = load i32, i32* %tmp961, align 4		; <i32> [#uses=1]
 	%tmp995 = icmp ugt i32 %tmp993, %tmp910		; <i1> [#uses=2]
 	%tmp1002 = add i32 %tmp955, 1		; <i32> [#uses=1]
 	%low.0 = select i1 %tmp995, i32 0, i32 %tmp1002		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll b/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll
index 9584b718fea0..6e98f9cb219a 100644
--- a/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll
+++ b/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll
@@ -2,29 +2,29 @@
 
 define void @SolveCubic(double %a, double %b, double %c, double %d, i32* %solutions, double* %x) {
 entry:
-	%tmp71 = load x86_fp80* null, align 16		; <x86_fp80> [#uses=1]
+	%tmp71 = load x86_fp80, x86_fp80* null, align 16		; <x86_fp80> [#uses=1]
 	%tmp72 = fdiv x86_fp80 %tmp71, 0xKC000C000000000000000		; <x86_fp80> [#uses=1]
 	%tmp73 = fadd x86_fp80 0xK00000000000000000000, %tmp72		; <x86_fp80> [#uses=1]
 	%tmp7374 = fptrunc x86_fp80 %tmp73 to double		; <double> [#uses=1]
 	store double %tmp7374, double* null, align 8
-	%tmp81 = load double* null, align 8		; <double> [#uses=1]
+	%tmp81 = load double, double* null, align 8		; <double> [#uses=1]
 	%tmp82 = fadd double %tmp81, 0x401921FB54442D18		; <double> [#uses=1]
 	%tmp83 = fdiv double %tmp82, 3.000000e+00		; <double> [#uses=1]
 	%tmp84 = call double @cos( double %tmp83 )		; <double> [#uses=1]
 	%tmp85 = fmul double 0.000000e+00, %tmp84		; <double> [#uses=1]
 	%tmp8586 = fpext double %tmp85 to x86_fp80		; <x86_fp80> [#uses=1]
-	%tmp87 = load x86_fp80* null, align 16		; <x86_fp80> [#uses=1]
+	%tmp87 = load x86_fp80, x86_fp80* null, align 16		; <x86_fp80> [#uses=1]
 	%tmp88 = fdiv x86_fp80 %tmp87, 0xKC000C000000000000000		; <x86_fp80> [#uses=1]
 	%tmp89 = fadd x86_fp80 %tmp8586, %tmp88		; <x86_fp80> [#uses=1]
 	%tmp8990 = fptrunc x86_fp80 %tmp89 to double		; <double> [#uses=1]
 	store double %tmp8990, double* null, align 8
-	%tmp97 = load double* null, align 8		; <double> [#uses=1]
+	%tmp97 = load double, double* null, align 8		; <double> [#uses=1]
 	%tmp98 = fadd double %tmp97, 0x402921FB54442D18		; <double> [#uses=1]
 	%tmp99 = fdiv double %tmp98, 3.000000e+00		; <double> [#uses=1]
 	%tmp100 = call double @cos( double %tmp99 )		; <double> [#uses=1]
 	%tmp101 = fmul double 0.000000e+00, %tmp100		; <double> [#uses=1]
 	%tmp101102 = fpext double %tmp101 to x86_fp80		; <x86_fp80> [#uses=1]
-	%tmp103 = load x86_fp80* null, align 16		; <x86_fp80> [#uses=1]
+	%tmp103 = load x86_fp80, x86_fp80* null, align 16		; <x86_fp80> [#uses=1]
 	%tmp104 = fdiv x86_fp80 %tmp103, 0xKC000C000000000000000		; <x86_fp80> [#uses=1]
 	%tmp105 = fadd x86_fp80 %tmp101102, %tmp104		; <x86_fp80> [#uses=1]
 	%tmp105106 = fptrunc x86_fp80 %tmp105 to double		; <double> [#uses=1]
diff --git a/test/CodeGen/X86/2008-01-16-InvalidDAGCombineXform.ll b/test/CodeGen/X86/2008-01-16-InvalidDAGCombineXform.ll
index e91f52ef0569..ffc5a1fb6d41 100644
--- a/test/CodeGen/X86/2008-01-16-InvalidDAGCombineXform.ll
+++ b/test/CodeGen/X86/2008-01-16-InvalidDAGCombineXform.ll
@@ -4,27 +4,27 @@
 
 define void @localize_local_bb19_bb(%struct.node_t** %cur_node) {
 newFuncRoot:
-	%tmp1 = load %struct.node_t** %cur_node, align 4		; <%struct.node_t*> [#uses=1]
-	%tmp2 = getelementptr %struct.node_t* %tmp1, i32 0, i32 4		; <double**> [#uses=1]
-	%tmp3 = load double** %tmp2, align 4		; <double*> [#uses=1]
-	%tmp4 = load %struct.node_t** %cur_node, align 4		; <%struct.node_t*> [#uses=1]
-	%tmp5 = getelementptr %struct.node_t* %tmp4, i32 0, i32 4		; <double**> [#uses=1]
+	%tmp1 = load %struct.node_t*, %struct.node_t** %cur_node, align 4		; <%struct.node_t*> [#uses=1]
+	%tmp2 = getelementptr %struct.node_t, %struct.node_t* %tmp1, i32 0, i32 4		; <double**> [#uses=1]
+	%tmp3 = load double*, double** %tmp2, align 4		; <double*> [#uses=1]
+	%tmp4 = load %struct.node_t*, %struct.node_t** %cur_node, align 4		; <%struct.node_t*> [#uses=1]
+	%tmp5 = getelementptr %struct.node_t, %struct.node_t* %tmp4, i32 0, i32 4		; <double**> [#uses=1]
 	store double* %tmp3, double** %tmp5, align 4
-	%tmp6 = load %struct.node_t** %cur_node, align 4		; <%struct.node_t*> [#uses=1]
-	%tmp7 = getelementptr %struct.node_t* %tmp6, i32 0, i32 3		; <double***> [#uses=1]
-	%tmp8 = load double*** %tmp7, align 4		; <double**> [#uses=1]
-	%tmp9 = load %struct.node_t** %cur_node, align 4		; <%struct.node_t*> [#uses=1]
-	%tmp10 = getelementptr %struct.node_t* %tmp9, i32 0, i32 3		; <double***> [#uses=1]
+	%tmp6 = load %struct.node_t*, %struct.node_t** %cur_node, align 4		; <%struct.node_t*> [#uses=1]
+	%tmp7 = getelementptr %struct.node_t, %struct.node_t* %tmp6, i32 0, i32 3		; <double***> [#uses=1]
+	%tmp8 = load double**, double*** %tmp7, align 4		; <double**> [#uses=1]
+	%tmp9 = load %struct.node_t*, %struct.node_t** %cur_node, align 4		; <%struct.node_t*> [#uses=1]
+	%tmp10 = getelementptr %struct.node_t, %struct.node_t* %tmp9, i32 0, i32 3		; <double***> [#uses=1]
 	store double** %tmp8, double*** %tmp10, align 4
-	%tmp11 = load %struct.node_t** %cur_node, align 4		; <%struct.node_t*> [#uses=1]
-	%tmp12 = getelementptr %struct.node_t* %tmp11, i32 0, i32 0		; <double**> [#uses=1]
-	%tmp13 = load double** %tmp12, align 4		; <double*> [#uses=1]
-	%tmp14 = load %struct.node_t** %cur_node, align 4		; <%struct.node_t*> [#uses=1]
-	%tmp15 = getelementptr %struct.node_t* %tmp14, i32 0, i32 0		; <double**> [#uses=1]
+	%tmp11 = load %struct.node_t*, %struct.node_t** %cur_node, align 4		; <%struct.node_t*> [#uses=1]
+	%tmp12 = getelementptr %struct.node_t, %struct.node_t* %tmp11, i32 0, i32 0		; <double**> [#uses=1]
+	%tmp13 = load double*, double** %tmp12, align 4		; <double*> [#uses=1]
+	%tmp14 = load %struct.node_t*, %struct.node_t** %cur_node, align 4		; <%struct.node_t*> [#uses=1]
+	%tmp15 = getelementptr %struct.node_t, %struct.node_t* %tmp14, i32 0, i32 0		; <double**> [#uses=1]
 	store double* %tmp13, double** %tmp15, align 4
-	%tmp16 = load %struct.node_t** %cur_node, align 4		; <%struct.node_t*> [#uses=1]
-	%tmp17 = getelementptr %struct.node_t* %tmp16, i32 0, i32 1		; <%struct.node_t**> [#uses=1]
-	%tmp18 = load %struct.node_t** %tmp17, align 4		; <%struct.node_t*> [#uses=1]
+	%tmp16 = load %struct.node_t*, %struct.node_t** %cur_node, align 4		; <%struct.node_t*> [#uses=1]
+	%tmp17 = getelementptr %struct.node_t, %struct.node_t* %tmp16, i32 0, i32 1		; <%struct.node_t**> [#uses=1]
+	%tmp18 = load %struct.node_t*, %struct.node_t** %tmp17, align 4		; <%struct.node_t*> [#uses=1]
 	store %struct.node_t* %tmp18, %struct.node_t** %cur_node, align 4
 	ret void
 }
diff --git a/test/CodeGen/X86/2008-02-05-ISelCrash.ll b/test/CodeGen/X86/2008-02-05-ISelCrash.ll
index 443a32de3b42..ce233a9a554a 100644
--- a/test/CodeGen/X86/2008-02-05-ISelCrash.ll
+++ b/test/CodeGen/X86/2008-02-05-ISelCrash.ll
@@ -5,7 +5,7 @@
 
 define fastcc i32 @ab(i32 %alpha, i32 %beta) nounwind  {
 entry:
-	%tmp1 = load i64* @nodes, align 8		; <i64> [#uses=1]
+	%tmp1 = load i64, i64* @nodes, align 8		; <i64> [#uses=1]
 	%tmp2 = add i64 %tmp1, 1		; <i64> [#uses=1]
 	store i64 %tmp2, i64* @nodes, align 8
 	ret i32 0
diff --git a/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll b/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll
index 35857b7e01e6..56b1c7836e12 100644
--- a/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll
+++ b/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll
@@ -6,14 +6,14 @@ entry:
 	%memtmp = alloca { double, double }, align 8		; <{ double, double }*> [#uses=3]
 	%tmp4 = fsub double -0.000000e+00, %z.1		; <double> [#uses=1]
 	call void @casinh( { double, double }* sret  %memtmp, double %tmp4, double %z.0 ) nounwind 
-	%tmp19 = getelementptr { double, double }* %memtmp, i32 0, i32 0		; <double*> [#uses=1]
-	%tmp20 = load double* %tmp19, align 8		; <double> [#uses=1]
-	%tmp22 = getelementptr { double, double }* %memtmp, i32 0, i32 1		; <double*> [#uses=1]
-	%tmp23 = load double* %tmp22, align 8		; <double> [#uses=1]
+	%tmp19 = getelementptr { double, double }, { double, double }* %memtmp, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp20 = load double, double* %tmp19, align 8		; <double> [#uses=1]
+	%tmp22 = getelementptr { double, double }, { double, double }* %memtmp, i32 0, i32 1		; <double*> [#uses=1]
+	%tmp23 = load double, double* %tmp22, align 8		; <double> [#uses=1]
 	%tmp32 = fsub double -0.000000e+00, %tmp20		; <double> [#uses=1]
-	%tmp37 = getelementptr { double, double }* %agg.result, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp37 = getelementptr { double, double }, { double, double }* %agg.result, i32 0, i32 0		; <double*> [#uses=1]
 	store double %tmp23, double* %tmp37, align 8
-	%tmp40 = getelementptr { double, double }* %agg.result, i32 0, i32 1		; <double*> [#uses=1]
+	%tmp40 = getelementptr { double, double }, { double, double }* %agg.result, i32 0, i32 1		; <double*> [#uses=1]
 	store double %tmp32, double* %tmp40, align 8
 	ret void
 }
diff --git a/test/CodeGen/X86/2008-02-18-TailMergingBug.ll b/test/CodeGen/X86/2008-02-18-TailMergingBug.ll
index 363a6008a00d..ef69bd01cb96 100644
--- a/test/CodeGen/X86/2008-02-18-TailMergingBug.ll
+++ b/test/CodeGen/X86/2008-02-18-TailMergingBug.ll
@@ -6,13 +6,13 @@
 
 define void @minmax(float* %result) nounwind optsize {
 entry:
-	%tmp2 = load float* %result, align 4		; <float> [#uses=6]
-	%tmp4 = getelementptr float* %result, i32 2		; <float*> [#uses=5]
-	%tmp5 = load float* %tmp4, align 4		; <float> [#uses=10]
-	%tmp7 = getelementptr float* %result, i32 4		; <float*> [#uses=5]
-	%tmp8 = load float* %tmp7, align 4		; <float> [#uses=8]
-	%tmp10 = getelementptr float* %result, i32 6		; <float*> [#uses=3]
-	%tmp11 = load float* %tmp10, align 4		; <float> [#uses=8]
+	%tmp2 = load float, float* %result, align 4		; <float> [#uses=6]
+	%tmp4 = getelementptr float, float* %result, i32 2		; <float*> [#uses=5]
+	%tmp5 = load float, float* %tmp4, align 4		; <float> [#uses=10]
+	%tmp7 = getelementptr float, float* %result, i32 4		; <float*> [#uses=5]
+	%tmp8 = load float, float* %tmp7, align 4		; <float> [#uses=8]
+	%tmp10 = getelementptr float, float* %result, i32 6		; <float*> [#uses=3]
+	%tmp11 = load float, float* %tmp10, align 4		; <float> [#uses=8]
 	%tmp12 = fcmp olt float %tmp8, %tmp11		; <i1> [#uses=5]
 	br i1 %tmp12, label %bb, label %bb21
 
@@ -59,7 +59,7 @@ bb103:		; preds = %bb80, %bb72
 
 bb111:		; preds = %bb103, %bb80, %bb72, %bb50, %bb40, %bb26
 	%iftmp.0.0.in = phi float* [ %tmp10, %bb103 ], [ %result, %bb26 ], [ %result, %bb40 ], [ %result, %bb50 ], [ %tmp4.mux, %bb80 ], [ %tmp4.mux787, %bb72 ]		; <float*> [#uses=1]
-	%iftmp.0.0 = load float* %iftmp.0.0.in		; <float> [#uses=1]
+	%iftmp.0.0 = load float, float* %iftmp.0.0.in		; <float> [#uses=1]
 	%tmp125 = fcmp ogt float %tmp8, %tmp11		; <i1> [#uses=5]
 	br i1 %tmp125, label %bb128, label %bb136
 
@@ -106,15 +106,15 @@ bb218:		; preds = %bb195, %bb187
 
 bb226:		; preds = %bb218, %bb195, %bb187, %bb165, %bb155, %bb141
 	%iftmp.7.0.in = phi float* [ %tmp10, %bb218 ], [ %result, %bb141 ], [ %result, %bb155 ], [ %result, %bb165 ], [ %tmp4.mux789, %bb195 ], [ %tmp4.mux791, %bb187 ]		; <float*> [#uses=1]
-	%iftmp.7.0 = load float* %iftmp.7.0.in		; <float> [#uses=1]
-	%tmp229 = getelementptr float* %result, i32 1		; <float*> [#uses=7]
-	%tmp230 = load float* %tmp229, align 4		; <float> [#uses=6]
-	%tmp232 = getelementptr float* %result, i32 3		; <float*> [#uses=5]
-	%tmp233 = load float* %tmp232, align 4		; <float> [#uses=10]
-	%tmp235 = getelementptr float* %result, i32 5		; <float*> [#uses=5]
-	%tmp236 = load float* %tmp235, align 4		; <float> [#uses=8]
-	%tmp238 = getelementptr float* %result, i32 7		; <float*> [#uses=3]
-	%tmp239 = load float* %tmp238, align 4		; <float> [#uses=8]
+	%iftmp.7.0 = load float, float* %iftmp.7.0.in		; <float> [#uses=1]
+	%tmp229 = getelementptr float, float* %result, i32 1		; <float*> [#uses=7]
+	%tmp230 = load float, float* %tmp229, align 4		; <float> [#uses=6]
+	%tmp232 = getelementptr float, float* %result, i32 3		; <float*> [#uses=5]
+	%tmp233 = load float, float* %tmp232, align 4		; <float> [#uses=10]
+	%tmp235 = getelementptr float, float* %result, i32 5		; <float*> [#uses=5]
+	%tmp236 = load float, float* %tmp235, align 4		; <float> [#uses=8]
+	%tmp238 = getelementptr float, float* %result, i32 7		; <float*> [#uses=3]
+	%tmp239 = load float, float* %tmp238, align 4		; <float> [#uses=8]
 	%tmp240 = fcmp olt float %tmp236, %tmp239		; <i1> [#uses=5]
 	br i1 %tmp240, label %bb243, label %bb251
 
@@ -161,7 +161,7 @@ bb333:		; preds = %bb310, %bb302
 
 bb341:		; preds = %bb333, %bb310, %bb302, %bb280, %bb270, %bb256
 	%iftmp.14.0.in = phi float* [ %tmp238, %bb333 ], [ %tmp229, %bb280 ], [ %tmp229, %bb270 ], [ %tmp229, %bb256 ], [ %tmp232.mux, %bb310 ], [ %tmp232.mux794, %bb302 ]		; <float*> [#uses=1]
-	%iftmp.14.0 = load float* %iftmp.14.0.in		; <float> [#uses=1]
+	%iftmp.14.0 = load float, float* %iftmp.14.0.in		; <float> [#uses=1]
 	%tmp355 = fcmp ogt float %tmp236, %tmp239		; <i1> [#uses=5]
 	br i1 %tmp355, label %bb358, label %bb366
 
@@ -208,12 +208,12 @@ bb448:		; preds = %bb425, %bb417
 
 bb456:		; preds = %bb448, %bb425, %bb417, %bb395, %bb385, %bb371
 	%iftmp.21.0.in = phi float* [ %tmp238, %bb448 ], [ %tmp229, %bb395 ], [ %tmp229, %bb385 ], [ %tmp229, %bb371 ], [ %tmp232.mux796, %bb425 ], [ %tmp232.mux798, %bb417 ]		; <float*> [#uses=1]
-	%iftmp.21.0 = load float* %iftmp.21.0.in		; <float> [#uses=1]
+	%iftmp.21.0 = load float, float* %iftmp.21.0.in		; <float> [#uses=1]
 	%tmp458459 = fpext float %iftmp.21.0 to double		; <double> [#uses=1]
 	%tmp460461 = fpext float %iftmp.7.0 to double		; <double> [#uses=1]
 	%tmp462463 = fpext float %iftmp.14.0 to double		; <double> [#uses=1]
 	%tmp464465 = fpext float %iftmp.0.0 to double		; <double> [#uses=1]
-	%tmp467 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([48 x i8]* @.str, i32 0, i32 0), double %tmp464465, double %tmp462463, double %tmp460461, double %tmp458459 ) nounwind 		; <i32> [#uses=0]
+	%tmp467 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([48 x i8], [48 x i8]* @.str, i32 0, i32 0), double %tmp464465, double %tmp462463, double %tmp460461, double %tmp458459 ) nounwind 		; <i32> [#uses=0]
 	ret void
 }
 
diff --git a/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll b/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll
index 319e884139ae..b3f303f8fd85 100644
--- a/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll
+++ b/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll
@@ -8,7 +8,7 @@ target triple = "i386-apple-darwin8"
 
 define void @test() nounwind  {
 entry:
-	%tmp = load i32* @pixels, align 4		; <i32> [#uses=1]
+	%tmp = load i32, i32* @pixels, align 4		; <i32> [#uses=1]
 	%tmp1 = tail call i32 asm sideeffect "a: $0 $1", "=r,0,~{dirflag},~{fpsr},~{flags},~{ax}"( i32 %tmp ) nounwind 		; <i32> [#uses=1]
 	store i32 %tmp1, i32* @pixels, align 4
 	ret void
@@ -20,7 +20,7 @@ entry:
 
 define void @test2(i16* %block, i8* %pixels, i32 %line_size) nounwind  {
 entry:
-	%tmp1 = getelementptr i16* %block, i32 64		; <i16*> [#uses=1]
+	%tmp1 = getelementptr i16, i16* %block, i32 64		; <i16*> [#uses=1]
 	%tmp3 = tail call i8* asm sideeffect "b: $0 $1 $2", "=r,r,0,~{dirflag},~{fpsr},~{flags},~{ax}"( i16* %tmp1, i8* %pixels ) nounwind 		; <i8*> [#uses=0]
 	ret void
 }
diff --git a/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll b/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll
index 9185a3671184..75f88b0e3811 100644
--- a/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll
+++ b/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll
@@ -13,39 +13,39 @@ entry:
 	store i8* %src, i8** %src_addr
 	store i32 %dst_stride, i32* %dst_stride_addr
 	store i32 %src_stride, i32* %src_stride_addr
-	%tmp = load i8** %dst_addr, align 4		; <i8*> [#uses=1]
-	%tmp1 = getelementptr i8* %tmp, i32 0		; <i8*> [#uses=1]
+	%tmp = load i8*, i8** %dst_addr, align 4		; <i8*> [#uses=1]
+	%tmp1 = getelementptr i8, i8* %tmp, i32 0		; <i8*> [#uses=1]
 	%tmp12 = bitcast i8* %tmp1 to i32*		; <i32*> [#uses=1]
-	%tmp3 = load i8** %dst_addr, align 4		; <i8*> [#uses=1]
-	%tmp4 = load i32* %dst_stride_addr, align 4		; <i32> [#uses=1]
-	%tmp5 = getelementptr i8* %tmp3, i32 %tmp4		; <i8*> [#uses=1]
+	%tmp3 = load i8*, i8** %dst_addr, align 4		; <i8*> [#uses=1]
+	%tmp4 = load i32, i32* %dst_stride_addr, align 4		; <i32> [#uses=1]
+	%tmp5 = getelementptr i8, i8* %tmp3, i32 %tmp4		; <i8*> [#uses=1]
 	%tmp56 = bitcast i8* %tmp5 to i32*		; <i32*> [#uses=1]
-	%tmp7 = load i32* %dst_stride_addr, align 4		; <i32> [#uses=1]
+	%tmp7 = load i32, i32* %dst_stride_addr, align 4		; <i32> [#uses=1]
 	%tmp8 = mul i32 %tmp7, 2		; <i32> [#uses=1]
-	%tmp9 = load i8** %dst_addr, align 4		; <i8*> [#uses=1]
-	%tmp10 = getelementptr i8* %tmp9, i32 %tmp8		; <i8*> [#uses=1]
+	%tmp9 = load i8*, i8** %dst_addr, align 4		; <i8*> [#uses=1]
+	%tmp10 = getelementptr i8, i8* %tmp9, i32 %tmp8		; <i8*> [#uses=1]
 	%tmp1011 = bitcast i8* %tmp10 to i32*		; <i32*> [#uses=1]
-	%tmp13 = load i32* %dst_stride_addr, align 4		; <i32> [#uses=1]
+	%tmp13 = load i32, i32* %dst_stride_addr, align 4		; <i32> [#uses=1]
 	%tmp14 = mul i32 %tmp13, 3		; <i32> [#uses=1]
-	%tmp15 = load i8** %dst_addr, align 4		; <i8*> [#uses=1]
-	%tmp16 = getelementptr i8* %tmp15, i32 %tmp14		; <i8*> [#uses=1]
+	%tmp15 = load i8*, i8** %dst_addr, align 4		; <i8*> [#uses=1]
+	%tmp16 = getelementptr i8, i8* %tmp15, i32 %tmp14		; <i8*> [#uses=1]
 	%tmp1617 = bitcast i8* %tmp16 to i32*		; <i32*> [#uses=1]
-	%tmp18 = load i8** %src_addr, align 4		; <i8*> [#uses=1]
-	%tmp19 = getelementptr i8* %tmp18, i32 0		; <i8*> [#uses=1]
+	%tmp18 = load i8*, i8** %src_addr, align 4		; <i8*> [#uses=1]
+	%tmp19 = getelementptr i8, i8* %tmp18, i32 0		; <i8*> [#uses=1]
 	%tmp1920 = bitcast i8* %tmp19 to i32*		; <i32*> [#uses=1]
-	%tmp21 = load i8** %src_addr, align 4		; <i8*> [#uses=1]
-	%tmp22 = load i32* %src_stride_addr, align 4		; <i32> [#uses=1]
-	%tmp23 = getelementptr i8* %tmp21, i32 %tmp22		; <i8*> [#uses=1]
+	%tmp21 = load i8*, i8** %src_addr, align 4		; <i8*> [#uses=1]
+	%tmp22 = load i32, i32* %src_stride_addr, align 4		; <i32> [#uses=1]
+	%tmp23 = getelementptr i8, i8* %tmp21, i32 %tmp22		; <i8*> [#uses=1]
 	%tmp2324 = bitcast i8* %tmp23 to i32*		; <i32*> [#uses=1]
-	%tmp25 = load i32* %src_stride_addr, align 4		; <i32> [#uses=1]
+	%tmp25 = load i32, i32* %src_stride_addr, align 4		; <i32> [#uses=1]
 	%tmp26 = mul i32 %tmp25, 2		; <i32> [#uses=1]
-	%tmp27 = load i8** %src_addr, align 4		; <i8*> [#uses=1]
-	%tmp28 = getelementptr i8* %tmp27, i32 %tmp26		; <i8*> [#uses=1]
+	%tmp27 = load i8*, i8** %src_addr, align 4		; <i8*> [#uses=1]
+	%tmp28 = getelementptr i8, i8* %tmp27, i32 %tmp26		; <i8*> [#uses=1]
 	%tmp2829 = bitcast i8* %tmp28 to i32*		; <i32*> [#uses=1]
-	%tmp30 = load i32* %src_stride_addr, align 4		; <i32> [#uses=1]
+	%tmp30 = load i32, i32* %src_stride_addr, align 4		; <i32> [#uses=1]
 	%tmp31 = mul i32 %tmp30, 3		; <i32> [#uses=1]
-	%tmp32 = load i8** %src_addr, align 4		; <i8*> [#uses=1]
-	%tmp33 = getelementptr i8* %tmp32, i32 %tmp31		; <i8*> [#uses=1]
+	%tmp32 = load i8*, i8** %src_addr, align 4		; <i8*> [#uses=1]
+	%tmp33 = getelementptr i8, i8* %tmp32, i32 %tmp31		; <i8*> [#uses=1]
 	%tmp3334 = bitcast i8* %tmp33 to i32*		; <i32*> [#uses=1]
 	call void asm sideeffect "movd  $4, %mm0                \0A\09movd  $5, %mm1                \0A\09movd  $6, %mm2                \0A\09movd  $7, %mm3                \0A\09punpcklbw %mm1, %mm0         \0A\09punpcklbw %mm3, %mm2         \0A\09movq %mm0, %mm1              \0A\09punpcklwd %mm2, %mm0         \0A\09punpckhwd %mm2, %mm1         \0A\09movd  %mm0, $0                \0A\09punpckhdq %mm0, %mm0         \0A\09movd  %mm0, $1                \0A\09movd  %mm1, $2                \0A\09punpckhdq %mm1, %mm1         \0A\09movd  %mm1, $3                \0A\09", "=*m,=*m,=*m,=*m,*m,*m,*m,*m,~{dirflag},~{fpsr},~{flags}"( i32* %tmp12, i32* %tmp56, i32* %tmp1011, i32* %tmp1617, i32* %tmp1920, i32* %tmp2324, i32* %tmp2829, i32* %tmp3334 ) nounwind 
 	br label %return
diff --git a/test/CodeGen/X86/2008-02-25-InlineAsmBug.ll b/test/CodeGen/X86/2008-02-25-InlineAsmBug.ll
index 1d31859f46cc..1251e3fda8c7 100644
--- a/test/CodeGen/X86/2008-02-25-InlineAsmBug.ll
+++ b/test/CodeGen/X86/2008-02-25-InlineAsmBug.ll
@@ -3,9 +3,9 @@
 
 define void @h264_h_loop_filter_luma_mmx2(i8* %pix, i32 %stride, i32 %alpha, i32 %beta, i8* %tc0) nounwind  {
 entry:
-	%tmp164 = getelementptr [16 x i32]* null, i32 0, i32 11		; <i32*> [#uses=1]
-	%tmp169 = getelementptr [16 x i32]* null, i32 0, i32 13		; <i32*> [#uses=1]
-	%tmp174 = getelementptr [16 x i32]* null, i32 0, i32 15		; <i32*> [#uses=1]
+	%tmp164 = getelementptr [16 x i32], [16 x i32]* null, i32 0, i32 11		; <i32*> [#uses=1]
+	%tmp169 = getelementptr [16 x i32], [16 x i32]* null, i32 0, i32 13		; <i32*> [#uses=1]
+	%tmp174 = getelementptr [16 x i32], [16 x i32]* null, i32 0, i32 15		; <i32*> [#uses=1]
 	%tmp154.sum317 = add i32 0, %stride		; <i32> [#uses=1]
 	%tmp154.sum315 = mul i32 %stride, 6		; <i32> [#uses=1]
 	%tmp154.sum = mul i32 %stride, 7		; <i32> [#uses=1]
@@ -14,16 +14,16 @@ entry:
 
 bb32:		; preds = %entry
 	%pix_addr.0327.sum340 = add i32 %pix_addr.0327.rec, 0		; <i32> [#uses=1]
-	%tmp154 = getelementptr i8* %pix, i32 %pix_addr.0327.sum340		; <i8*> [#uses=1]
+	%tmp154 = getelementptr i8, i8* %pix, i32 %pix_addr.0327.sum340		; <i8*> [#uses=1]
 	%tmp177178 = bitcast i8* %tmp154 to i32*		; <i32*> [#uses=1]
 	%pix_addr.0327.sum339 = add i32 %pix_addr.0327.rec, %tmp154.sum317		; <i32> [#uses=1]
-	%tmp181 = getelementptr i8* %pix, i32 %pix_addr.0327.sum339		; <i8*> [#uses=1]
+	%tmp181 = getelementptr i8, i8* %pix, i32 %pix_addr.0327.sum339		; <i8*> [#uses=1]
 	%tmp181182 = bitcast i8* %tmp181 to i32*		; <i32*> [#uses=1]
 	%pix_addr.0327.sum338 = add i32 %pix_addr.0327.rec, %tmp154.sum315		; <i32> [#uses=1]
-	%tmp186 = getelementptr i8* %pix, i32 %pix_addr.0327.sum338		; <i8*> [#uses=1]
+	%tmp186 = getelementptr i8, i8* %pix, i32 %pix_addr.0327.sum338		; <i8*> [#uses=1]
 	%tmp186187 = bitcast i8* %tmp186 to i32*		; <i32*> [#uses=1]
 	%pix_addr.0327.sum337 = add i32 %pix_addr.0327.rec, %tmp154.sum		; <i32> [#uses=1]
-	%tmp191 = getelementptr i8* %pix, i32 %pix_addr.0327.sum337		; <i8*> [#uses=1]
+	%tmp191 = getelementptr i8, i8* %pix, i32 %pix_addr.0327.sum337		; <i8*> [#uses=1]
 	%tmp191192 = bitcast i8* %tmp191 to i32*		; <i32*> [#uses=1]
 	call void asm sideeffect "movd  $4, %mm0                \0A\09movd  $5, %mm1                \0A\09movd  $6, %mm2                \0A\09movd  $7, %mm3                \0A\09punpcklbw %mm1, %mm0         \0A\09punpcklbw %mm3, %mm2         \0A\09movq %mm0, %mm1              \0A\09punpcklwd %mm2, %mm0         \0A\09punpckhwd %mm2, %mm1         \0A\09movd  %mm0, $0                \0A\09punpckhdq %mm0, %mm0         \0A\09movd  %mm0, $1                \0A\09movd  %mm1, $2                \0A\09punpckhdq %mm1, %mm1         \0A\09movd  %mm1, $3                \0A\09", "=*m,=*m,=*m,=*m,*m,*m,*m,*m,~{dirflag},~{fpsr},~{flags}"( i32* null, i32* %tmp164, i32* %tmp169, i32* %tmp174, i32* %tmp177178, i32* %tmp181182, i32* %tmp186187, i32* %tmp191192 ) nounwind 
 	unreachable
diff --git a/test/CodeGen/X86/2008-02-25-X86-64-CoalescerBug.ll b/test/CodeGen/X86/2008-02-25-X86-64-CoalescerBug.ll
index fd9c35e58b29..382fbed9b88e 100644
--- a/test/CodeGen/X86/2008-02-25-X86-64-CoalescerBug.ll
+++ b/test/CodeGen/X86/2008-02-25-X86-64-CoalescerBug.ll
@@ -11,10 +11,10 @@ entry:
 
 bb53:		; preds = %entry
 	%tmp55 = call %struct.YY** @AA( i64 1, %struct.XX* %uen )		; <%struct.YY**> [#uses=3]
-	%tmp2728128 = load %struct.XX** null		; <%struct.XX*> [#uses=1]
-	%tmp61 = load %struct.YY** %tmp55, align 8		; <%struct.YY*> [#uses=1]
-	%tmp62 = getelementptr %struct.YY* %tmp61, i32 0, i32 0		; <i64*> [#uses=1]
-	%tmp63 = load i64* %tmp62, align 8		; <i64> [#uses=1]
+	%tmp2728128 = load %struct.XX*, %struct.XX** null		; <%struct.XX*> [#uses=1]
+	%tmp61 = load %struct.YY*, %struct.YY** %tmp55, align 8		; <%struct.YY*> [#uses=1]
+	%tmp62 = getelementptr %struct.YY, %struct.YY* %tmp61, i32 0, i32 0		; <i64*> [#uses=1]
+	%tmp63 = load i64, i64* %tmp62, align 8		; <i64> [#uses=1]
 	%tmp6566 = zext i16 %tmp45 to i64		; <i64> [#uses=1]
 	%tmp67 = shl i64 %tmp6566, 1		; <i64> [#uses=1]
 	call void @BB( %struct.YY** %tmp55, i64 %tmp67, i8 signext  0, %struct.XX* %uen )
@@ -30,7 +30,7 @@ bb70:		; preds = %bb119, %bb70.preheader
 	%tmp.135 = trunc i64 %tmp63 to i32		; <i32> [#uses=1]
 	%tmp136 = shl i32 %indvar133, 1		; <i32> [#uses=1]
 	%DD = add i32 %tmp136, %tmp.135		; <i32> [#uses=1]
-	%tmp73 = load %struct.ZZ*** %tmp72, align 8		; <%struct.ZZ**> [#uses=0]
+	%tmp73 = load %struct.ZZ**, %struct.ZZ*** %tmp72, align 8		; <%struct.ZZ**> [#uses=0]
 	br i1 false, label %bb119, label %bb77
 
 bb77:		; preds = %bb70
diff --git a/test/CodeGen/X86/2008-02-27-DeadSlotElimBug.ll b/test/CodeGen/X86/2008-02-27-DeadSlotElimBug.ll
index ad7950ccd8e3..857e6237d14f 100644
--- a/test/CodeGen/X86/2008-02-27-DeadSlotElimBug.ll
+++ b/test/CodeGen/X86/2008-02-27-DeadSlotElimBug.ll
@@ -13,8 +13,8 @@ entry:
 
 bb24:		; preds = %bb24, %entry
 	%tmp9.0.reg2mem.0.rec = phi i32 [ %indvar.next, %bb24 ], [ 0, %entry ]		; <i32> [#uses=3]
-	%tmp3.i.i = getelementptr %struct.CompAtom* %tmp1819, i32 %tmp9.0.reg2mem.0.rec, i32 0, i32 1		; <double*> [#uses=0]
-	%tmp5.i.i = getelementptr %struct.CompAtom* %tmp1819, i32 %tmp9.0.reg2mem.0.rec, i32 0, i32 2		; <double*> [#uses=1]
+	%tmp3.i.i = getelementptr %struct.CompAtom, %struct.CompAtom* %tmp1819, i32 %tmp9.0.reg2mem.0.rec, i32 0, i32 1		; <double*> [#uses=0]
+	%tmp5.i.i = getelementptr %struct.CompAtom, %struct.CompAtom* %tmp1819, i32 %tmp9.0.reg2mem.0.rec, i32 0, i32 2		; <double*> [#uses=1]
 	store double -9.999900e+04, double* %tmp5.i.i, align 4
 	%indvar.next = add i32 %tmp9.0.reg2mem.0.rec, 1		; <i32> [#uses=2]
 	%exitcond = icmp eq i32 %indvar.next, %n		; <i1> [#uses=1]
@@ -33,8 +33,8 @@ bb35:		; preds = %bb24, %entry
 	%tmp55 = srem i32 %i, 3		; <i32> [#uses=1]
 	%tmp56 = add i32 %tmp55, -1		; <i32> [#uses=1]
 	%tmp5657 = sitofp i32 %tmp56 to double		; <double> [#uses=1]
-	%tmp15.i49 = getelementptr %struct.Lattice* %this, i32 0, i32 0, i32 0		; <double*> [#uses=1]
-	%tmp16.i50 = load double* %tmp15.i49, align 4		; <double> [#uses=1]
+	%tmp15.i49 = getelementptr %struct.Lattice, %struct.Lattice* %this, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp16.i50 = load double, double* %tmp15.i49, align 4		; <double> [#uses=1]
 	%tmp17.i = fmul double %tmp5657, %tmp16.i50		; <double> [#uses=1]
 	%tmp20.i39 = fadd double %tmp17.i, %tmp17.i63		; <double> [#uses=1]
 	%tmp20.i23 = fadd double %tmp20.i39, %tmp17.i76		; <double> [#uses=1]
@@ -45,13 +45,13 @@ bb58.preheader:		; preds = %bb35
 	br label %bb58
 
 bb58:		; preds = %bb58, %bb58.preheader
-	%tmp20.i7 = getelementptr %struct.CompAtom* %d, i32 0, i32 2		; <i32*> [#uses=2]
-	%tmp25.i = getelementptr %struct.CompAtom* %tmp1819, i32 0, i32 2		; <i32*> [#uses=2]
-	%tmp74.i = load i32* %tmp20.i7, align 1		; <i32> [#uses=1]
+	%tmp20.i7 = getelementptr %struct.CompAtom, %struct.CompAtom* %d, i32 0, i32 2		; <i32*> [#uses=2]
+	%tmp25.i = getelementptr %struct.CompAtom, %struct.CompAtom* %tmp1819, i32 0, i32 2		; <i32*> [#uses=2]
+	%tmp74.i = load i32, i32* %tmp20.i7, align 1		; <i32> [#uses=1]
 	%tmp82.i = and i32 %tmp74.i, 134217728		; <i32> [#uses=1]
 	%tmp85.i = or i32 0, %tmp82.i		; <i32> [#uses=1]
 	store i32 %tmp85.i, i32* %tmp25.i, align 1
-	%tmp88.i = load i32* %tmp20.i7, align 1		; <i32> [#uses=1]
+	%tmp88.i = load i32, i32* %tmp20.i7, align 1		; <i32> [#uses=1]
 	%tmp95.i = and i32 %tmp88.i, -268435456		; <i32> [#uses=1]
 	%tmp97.i = or i32 0, %tmp95.i		; <i32> [#uses=1]
 	store i32 %tmp97.i, i32* %tmp25.i, align 1
diff --git a/test/CodeGen/X86/2008-03-07-APIntBug.ll b/test/CodeGen/X86/2008-03-07-APIntBug.ll
index 84e4827d0416..409bcd51a13b 100644
--- a/test/CodeGen/X86/2008-03-07-APIntBug.ll
+++ b/test/CodeGen/X86/2008-03-07-APIntBug.ll
@@ -18,73 +18,73 @@ newFuncRoot:
 bb1233.exitStub:		; preds = %bb1163
 	ret void
 bb1163:		; preds = %newFuncRoot
-	%tmp1164 = load %struct.rec** %s, align 4		; <%struct.rec*> [#uses=1]
-	%tmp1165 = getelementptr %struct.rec* %tmp1164, i32 0, i32 0		; <%struct.head_type*> [#uses=1]
+	%tmp1164 = load %struct.rec*, %struct.rec** %s, align 4		; <%struct.rec*> [#uses=1]
+	%tmp1165 = getelementptr %struct.rec, %struct.rec* %tmp1164, i32 0, i32 0		; <%struct.head_type*> [#uses=1]
 	%tmp11651166 = bitcast %struct.head_type* %tmp1165 to %struct.symbol_type*		; <%struct.symbol_type*> [#uses=1]
-	%tmp1167 = getelementptr %struct.symbol_type* %tmp11651166, i32 0, i32 3		; <%struct.rec**> [#uses=1]
-	%tmp1168 = load %struct.rec** %tmp1167, align 1		; <%struct.rec*> [#uses=2]
-	%tmp1169 = load %struct.rec** %s, align 4		; <%struct.rec*> [#uses=1]
-	%tmp1170 = getelementptr %struct.rec* %tmp1169, i32 0, i32 0		; <%struct.head_type*> [#uses=1]
+	%tmp1167 = getelementptr %struct.symbol_type, %struct.symbol_type* %tmp11651166, i32 0, i32 3		; <%struct.rec**> [#uses=1]
+	%tmp1168 = load %struct.rec*, %struct.rec** %tmp1167, align 1		; <%struct.rec*> [#uses=2]
+	%tmp1169 = load %struct.rec*, %struct.rec** %s, align 4		; <%struct.rec*> [#uses=1]
+	%tmp1170 = getelementptr %struct.rec, %struct.rec* %tmp1169, i32 0, i32 0		; <%struct.head_type*> [#uses=1]
 	%tmp11701171 = bitcast %struct.head_type* %tmp1170 to %struct.symbol_type*		; <%struct.symbol_type*> [#uses=1]
-	%tmp1172 = getelementptr %struct.symbol_type* %tmp11701171, i32 0, i32 3		; <%struct.rec**> [#uses=1]
-	%tmp1173 = load %struct.rec** %tmp1172, align 1		; <%struct.rec*> [#uses=2]
-	%tmp1174 = getelementptr %struct.rec* %tmp1173, i32 0, i32 0		; <%struct.head_type*> [#uses=1]
+	%tmp1172 = getelementptr %struct.symbol_type, %struct.symbol_type* %tmp11701171, i32 0, i32 3		; <%struct.rec**> [#uses=1]
+	%tmp1173 = load %struct.rec*, %struct.rec** %tmp1172, align 1		; <%struct.rec*> [#uses=2]
+	%tmp1174 = getelementptr %struct.rec, %struct.rec* %tmp1173, i32 0, i32 0		; <%struct.head_type*> [#uses=1]
 	%tmp11741175 = bitcast %struct.head_type* %tmp1174 to %struct.word_type*		; <%struct.word_type*> [#uses=1]
-	%tmp1176 = getelementptr %struct.word_type* %tmp11741175, i32 0, i32 2		; <%struct.SECOND_UNION*> [#uses=1]
-	%tmp1177 = getelementptr %struct.SECOND_UNION* %tmp1176, i32 0, i32 0		; <{ i16, i8, i8 }*> [#uses=1]
+	%tmp1176 = getelementptr %struct.word_type, %struct.word_type* %tmp11741175, i32 0, i32 2		; <%struct.SECOND_UNION*> [#uses=1]
+	%tmp1177 = getelementptr %struct.SECOND_UNION, %struct.SECOND_UNION* %tmp1176, i32 0, i32 0		; <{ i16, i8, i8 }*> [#uses=1]
 	%tmp11771178 = bitcast { i16, i8, i8 }* %tmp1177 to <{ i8, i8, i8, i8 }>*		; <<{ i8, i8, i8, i8 }>*> [#uses=1]
-	%tmp1179 = getelementptr <{ i8, i8, i8, i8 }>* %tmp11771178, i32 0, i32 2		; <i8*> [#uses=2]
+	%tmp1179 = getelementptr <{ i8, i8, i8, i8 }>, <{ i8, i8, i8, i8 }>* %tmp11771178, i32 0, i32 2		; <i8*> [#uses=2]
 	%mask1180 = and i8 1, 1		; <i8> [#uses=2]
-	%tmp1181 = load i8* %tmp1179, align 1		; <i8> [#uses=1]
+	%tmp1181 = load i8, i8* %tmp1179, align 1		; <i8> [#uses=1]
 	%tmp1182 = shl i8 %mask1180, 7		; <i8> [#uses=1]
 	%tmp1183 = and i8 %tmp1181, 127		; <i8> [#uses=1]
 	%tmp1184 = or i8 %tmp1183, %tmp1182		; <i8> [#uses=1]
 	store i8 %tmp1184, i8* %tmp1179, align 1
 	%mask1185 = and i8 %mask1180, 1		; <i8> [#uses=0]
-	%tmp1186 = getelementptr %struct.rec* %tmp1173, i32 0, i32 0		; <%struct.head_type*> [#uses=1]
+	%tmp1186 = getelementptr %struct.rec, %struct.rec* %tmp1173, i32 0, i32 0		; <%struct.head_type*> [#uses=1]
 	%tmp11861187 = bitcast %struct.head_type* %tmp1186 to %struct.word_type*		; <%struct.word_type*> [#uses=1]
-	%tmp1188 = getelementptr %struct.word_type* %tmp11861187, i32 0, i32 2		; <%struct.SECOND_UNION*> [#uses=1]
-	%tmp1189 = getelementptr %struct.SECOND_UNION* %tmp1188, i32 0, i32 0		; <{ i16, i8, i8 }*> [#uses=1]
+	%tmp1188 = getelementptr %struct.word_type, %struct.word_type* %tmp11861187, i32 0, i32 2		; <%struct.SECOND_UNION*> [#uses=1]
+	%tmp1189 = getelementptr %struct.SECOND_UNION, %struct.SECOND_UNION* %tmp1188, i32 0, i32 0		; <{ i16, i8, i8 }*> [#uses=1]
 	%tmp11891190 = bitcast { i16, i8, i8 }* %tmp1189 to <{ i8, i8, i8, i8 }>*		; <<{ i8, i8, i8, i8 }>*> [#uses=1]
-	%tmp1191 = getelementptr <{ i8, i8, i8, i8 }>* %tmp11891190, i32 0, i32 2		; <i8*> [#uses=1]
-	%tmp1192 = load i8* %tmp1191, align 1		; <i8> [#uses=1]
+	%tmp1191 = getelementptr <{ i8, i8, i8, i8 }>, <{ i8, i8, i8, i8 }>* %tmp11891190, i32 0, i32 2		; <i8*> [#uses=1]
+	%tmp1192 = load i8, i8* %tmp1191, align 1		; <i8> [#uses=1]
 	%tmp1193 = lshr i8 %tmp1192, 7		; <i8> [#uses=1]
 	%mask1194 = and i8 %tmp1193, 1		; <i8> [#uses=2]
 	%mask1195 = and i8 %mask1194, 1		; <i8> [#uses=0]
-	%tmp1196 = getelementptr %struct.rec* %tmp1168, i32 0, i32 0		; <%struct.head_type*> [#uses=1]
+	%tmp1196 = getelementptr %struct.rec, %struct.rec* %tmp1168, i32 0, i32 0		; <%struct.head_type*> [#uses=1]
 	%tmp11961197 = bitcast %struct.head_type* %tmp1196 to %struct.word_type*		; <%struct.word_type*> [#uses=1]
-	%tmp1198 = getelementptr %struct.word_type* %tmp11961197, i32 0, i32 2		; <%struct.SECOND_UNION*> [#uses=1]
-	%tmp1199 = getelementptr %struct.SECOND_UNION* %tmp1198, i32 0, i32 0		; <{ i16, i8, i8 }*> [#uses=1]
+	%tmp1198 = getelementptr %struct.word_type, %struct.word_type* %tmp11961197, i32 0, i32 2		; <%struct.SECOND_UNION*> [#uses=1]
+	%tmp1199 = getelementptr %struct.SECOND_UNION, %struct.SECOND_UNION* %tmp1198, i32 0, i32 0		; <{ i16, i8, i8 }*> [#uses=1]
 	%tmp11991200 = bitcast { i16, i8, i8 }* %tmp1199 to <{ i8, i8, i8, i8 }>*		; <<{ i8, i8, i8, i8 }>*> [#uses=1]
-	%tmp1201 = getelementptr <{ i8, i8, i8, i8 }>* %tmp11991200, i32 0, i32 1		; <i8*> [#uses=2]
+	%tmp1201 = getelementptr <{ i8, i8, i8, i8 }>, <{ i8, i8, i8, i8 }>* %tmp11991200, i32 0, i32 1		; <i8*> [#uses=2]
 	%mask1202 = and i8 %mask1194, 1		; <i8> [#uses=2]
-	%tmp1203 = load i8* %tmp1201, align 1		; <i8> [#uses=1]
+	%tmp1203 = load i8, i8* %tmp1201, align 1		; <i8> [#uses=1]
 	%tmp1204 = shl i8 %mask1202, 1		; <i8> [#uses=1]
 	%tmp1205 = and i8 %tmp1204, 2		; <i8> [#uses=1]
 	%tmp1206 = and i8 %tmp1203, -3		; <i8> [#uses=1]
 	%tmp1207 = or i8 %tmp1206, %tmp1205		; <i8> [#uses=1]
 	store i8 %tmp1207, i8* %tmp1201, align 1
 	%mask1208 = and i8 %mask1202, 1		; <i8> [#uses=0]
-	%tmp1209 = getelementptr %struct.rec* %tmp1168, i32 0, i32 0		; <%struct.head_type*> [#uses=1]
+	%tmp1209 = getelementptr %struct.rec, %struct.rec* %tmp1168, i32 0, i32 0		; <%struct.head_type*> [#uses=1]
 	%tmp12091210 = bitcast %struct.head_type* %tmp1209 to %struct.word_type*		; <%struct.word_type*> [#uses=1]
-	%tmp1211 = getelementptr %struct.word_type* %tmp12091210, i32 0, i32 2		; <%struct.SECOND_UNION*> [#uses=1]
-	%tmp1212 = getelementptr %struct.SECOND_UNION* %tmp1211, i32 0, i32 0		; <{ i16, i8, i8 }*> [#uses=1]
+	%tmp1211 = getelementptr %struct.word_type, %struct.word_type* %tmp12091210, i32 0, i32 2		; <%struct.SECOND_UNION*> [#uses=1]
+	%tmp1212 = getelementptr %struct.SECOND_UNION, %struct.SECOND_UNION* %tmp1211, i32 0, i32 0		; <{ i16, i8, i8 }*> [#uses=1]
 	%tmp12121213 = bitcast { i16, i8, i8 }* %tmp1212 to <{ i8, i8, i8, i8 }>*		; <<{ i8, i8, i8, i8 }>*> [#uses=1]
-	%tmp1214 = getelementptr <{ i8, i8, i8, i8 }>* %tmp12121213, i32 0, i32 1		; <i8*> [#uses=1]
-	%tmp1215 = load i8* %tmp1214, align 1		; <i8> [#uses=1]
+	%tmp1214 = getelementptr <{ i8, i8, i8, i8 }>, <{ i8, i8, i8, i8 }>* %tmp12121213, i32 0, i32 1		; <i8*> [#uses=1]
+	%tmp1215 = load i8, i8* %tmp1214, align 1		; <i8> [#uses=1]
 	%tmp1216 = shl i8 %tmp1215, 6		; <i8> [#uses=1]
 	%tmp1217 = lshr i8 %tmp1216, 7		; <i8> [#uses=1]
 	%mask1218 = and i8 %tmp1217, 1		; <i8> [#uses=2]
 	%mask1219 = and i8 %mask1218, 1		; <i8> [#uses=0]
-	%tmp1220 = load %struct.rec** %s, align 4		; <%struct.rec*> [#uses=1]
-	%tmp1221 = getelementptr %struct.rec* %tmp1220, i32 0, i32 0		; <%struct.head_type*> [#uses=1]
+	%tmp1220 = load %struct.rec*, %struct.rec** %s, align 4		; <%struct.rec*> [#uses=1]
+	%tmp1221 = getelementptr %struct.rec, %struct.rec* %tmp1220, i32 0, i32 0		; <%struct.head_type*> [#uses=1]
 	%tmp12211222 = bitcast %struct.head_type* %tmp1221 to %struct.word_type*		; <%struct.word_type*> [#uses=1]
-	%tmp1223 = getelementptr %struct.word_type* %tmp12211222, i32 0, i32 2		; <%struct.SECOND_UNION*> [#uses=1]
-	%tmp1224 = getelementptr %struct.SECOND_UNION* %tmp1223, i32 0, i32 0		; <{ i16, i8, i8 }*> [#uses=1]
+	%tmp1223 = getelementptr %struct.word_type, %struct.word_type* %tmp12211222, i32 0, i32 2		; <%struct.SECOND_UNION*> [#uses=1]
+	%tmp1224 = getelementptr %struct.SECOND_UNION, %struct.SECOND_UNION* %tmp1223, i32 0, i32 0		; <{ i16, i8, i8 }*> [#uses=1]
 	%tmp12241225 = bitcast { i16, i8, i8 }* %tmp1224 to <{ i8, i8, i8, i8 }>*		; <<{ i8, i8, i8, i8 }>*> [#uses=1]
-	%tmp1226 = getelementptr <{ i8, i8, i8, i8 }>* %tmp12241225, i32 0, i32 1		; <i8*> [#uses=2]
+	%tmp1226 = getelementptr <{ i8, i8, i8, i8 }>, <{ i8, i8, i8, i8 }>* %tmp12241225, i32 0, i32 1		; <i8*> [#uses=2]
 	%mask1227 = and i8 %mask1218, 1		; <i8> [#uses=2]
-	%tmp1228 = load i8* %tmp1226, align 1		; <i8> [#uses=1]
+	%tmp1228 = load i8, i8* %tmp1226, align 1		; <i8> [#uses=1]
 	%tmp1229 = and i8 %mask1227, 1		; <i8> [#uses=1]
 	%tmp1230 = and i8 %tmp1228, -2		; <i8> [#uses=1]
 	%tmp1231 = or i8 %tmp1230, %tmp1229		; <i8> [#uses=1]
diff --git a/test/CodeGen/X86/2008-03-10-RegAllocInfLoop.ll b/test/CodeGen/X86/2008-03-10-RegAllocInfLoop.ll
index 40aafb4c54d5..9fb325c1223b 100644
--- a/test/CodeGen/X86/2008-03-10-RegAllocInfLoop.ll
+++ b/test/CodeGen/X86/2008-03-10-RegAllocInfLoop.ll
@@ -5,7 +5,7 @@ declare fastcc i8* @w_addchar(i8*, i32*, i32*, i8 signext ) nounwind
 
 define x86_stdcallcc i32 @parse_backslash(i8** inreg  %word, i32* inreg  %word_length, i32* inreg  %max_length) nounwind  {
 entry:
-	%tmp6 = load i8* null, align 1		; <i8> [#uses=1]
+	%tmp6 = load i8, i8* null, align 1		; <i8> [#uses=1]
 	br label %bb13
 bb13:		; preds = %entry
 	%tmp26 = call fastcc i8* @w_addchar( i8* null, i32* %word_length, i32* %max_length, i8 signext  %tmp6 ) nounwind 		; <i8*> [#uses=1]
diff --git a/test/CodeGen/X86/2008-03-12-ThreadLocalAlias.ll b/test/CodeGen/X86/2008-03-12-ThreadLocalAlias.ll
index a0106d7798d5..a9e3f33ec618 100644
--- a/test/CodeGen/X86/2008-03-12-ThreadLocalAlias.ll
+++ b/test/CodeGen/X86/2008-03-12-ThreadLocalAlias.ll
@@ -16,12 +16,12 @@ define i32 @foo() {
 entry:
 	%retval = alloca i32		; <i32*> [#uses=1]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
-	%tmp = load %struct.__res_state** @__libc_resp, align 4		; <%struct.__res_state*> [#uses=1]
-	%tmp1 = getelementptr %struct.__res_state* %tmp, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp = load %struct.__res_state*, %struct.__res_state** @__libc_resp, align 4		; <%struct.__res_state*> [#uses=1]
+	%tmp1 = getelementptr %struct.__res_state, %struct.__res_state* %tmp, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp1, align 4
 	br label %return
 return:		; preds = %entry
-	%retval2 = load i32* %retval		; <i32> [#uses=1]
+	%retval2 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval2
 }
 
@@ -31,11 +31,11 @@ define i32 @bar() {
 entry:
 	%retval = alloca i32		; <i32*> [#uses=1]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
-	%tmp = load %struct.__res_state** @__libc_resp, align 4		; <%struct.__res_state*> [#uses=1]
-	%tmp1 = getelementptr %struct.__res_state* %tmp, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp = load %struct.__res_state*, %struct.__res_state** @__libc_resp, align 4		; <%struct.__res_state*> [#uses=1]
+	%tmp1 = getelementptr %struct.__res_state, %struct.__res_state* %tmp, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 1, i32* %tmp1, align 4
 	br label %return
 return:		; preds = %entry
-	%retval2 = load i32* %retval		; <i32> [#uses=1]
+	%retval2 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval2
 }
diff --git a/test/CodeGen/X86/2008-03-14-SpillerCrash.ll b/test/CodeGen/X86/2008-03-14-SpillerCrash.ll
index 6b374a7f6f08..d60d0c2fb0bc 100644
--- a/test/CodeGen/X86/2008-03-14-SpillerCrash.ll
+++ b/test/CodeGen/X86/2008-03-14-SpillerCrash.ll
@@ -10,8 +10,8 @@
 
 define i64 @____wcstoll_l_internal(i32* %nptr, i32** %endptr, i32 %base, i32 %group, %struct.__locale_struct* %loc) nounwind  {
 entry:
-	%tmp27 = load i32* null, align 4		; <i32> [#uses=1]
-	%tmp83 = getelementptr i32* %nptr, i32 1		; <i32*> [#uses=1]
+	%tmp27 = load i32, i32* null, align 4		; <i32> [#uses=1]
+	%tmp83 = getelementptr i32, i32* %nptr, i32 1		; <i32*> [#uses=1]
 	%tmp233 = add i32 0, -48		; <i32> [#uses=1]
 	br label %bb271.us
 bb271.us:		; preds = %entry
@@ -31,8 +31,8 @@ bb374.outer:		; preds = %bb311.split, %bb271.us
 	%tmp373.reg2mem.0.ph = add i64 %tmp370371552.pn, %tmp369551.pn		; <i64> [#uses=1]
 	br label %bb374.us
 bb374.us:		; preds = %bb314.us, %bb374.outer
-	%tmp376.us = getelementptr i32* %s.5.ph, i32 0		; <i32*> [#uses=3]
-	%tmp378.us = load i32* %tmp376.us, align 4		; <i32> [#uses=2]
+	%tmp376.us = getelementptr i32, i32* %s.5.ph, i32 0		; <i32*> [#uses=3]
+	%tmp378.us = load i32, i32* %tmp376.us, align 4		; <i32> [#uses=2]
 	%tmp302.us = icmp eq i32* %tmp376.us, %tmp83		; <i1> [#uses=1]
 	%bothcond484.us = or i1 false, %tmp302.us		; <i1> [#uses=1]
 	br i1 %bothcond484.us, label %bb383, label %bb305.us
diff --git a/test/CodeGen/X86/2008-03-23-DarwinAsmComments.ll b/test/CodeGen/X86/2008-03-23-DarwinAsmComments.ll
index 5ca7e3ed3dbf..3e55390de9f1 100644
--- a/test/CodeGen/X86/2008-03-23-DarwinAsmComments.ll
+++ b/test/CodeGen/X86/2008-03-23-DarwinAsmComments.ll
@@ -12,33 +12,33 @@ entry:
 
 cond_true:		; preds = %entry
 	%tmp1415 = shl i16 %param, 3		; <i16> [#uses=1]
-	%tmp17 = getelementptr %struct.AGenericCall* %this, i32 0, i32 1		; <%struct.ComponentParameters**> [#uses=1]
-	%tmp18 = load %struct.ComponentParameters** %tmp17, align 8		; <%struct.ComponentParameters*> [#uses=1]
+	%tmp17 = getelementptr %struct.AGenericCall, %struct.AGenericCall* %this, i32 0, i32 1		; <%struct.ComponentParameters**> [#uses=1]
+	%tmp18 = load %struct.ComponentParameters*, %struct.ComponentParameters** %tmp17, align 8		; <%struct.ComponentParameters*> [#uses=1]
 	%tmp1920 = bitcast %struct.ComponentParameters* %tmp18 to i8*		; <i8*> [#uses=1]
 	%tmp212223 = sext i16 %tmp1415 to i64		; <i64> [#uses=1]
-	%tmp24 = getelementptr i8* %tmp1920, i64 %tmp212223		; <i8*> [#uses=1]
+	%tmp24 = getelementptr i8, i8* %tmp1920, i64 %tmp212223		; <i8*> [#uses=1]
 	%tmp2425 = bitcast i8* %tmp24 to i64*		; <i64*> [#uses=1]
-	%tmp28 = load i64* %tmp2425, align 8		; <i64> [#uses=1]
+	%tmp28 = load i64, i64* %tmp2425, align 8		; <i64> [#uses=1]
 	%tmp2829 = inttoptr i64 %tmp28 to i32*		; <i32*> [#uses=1]
-	%tmp31 = getelementptr %struct.AGenericCall* %this, i32 0, i32 2		; <i32**> [#uses=1]
+	%tmp31 = getelementptr %struct.AGenericCall, %struct.AGenericCall* %this, i32 0, i32 2		; <i32**> [#uses=1]
 	store i32* %tmp2829, i32** %tmp31, align 8
 	br label %cond_next
 
 cond_next:		; preds = %cond_true, %entry
 	%tmp4243 = shl i16 %param, 3		; <i16> [#uses=1]
-	%tmp46 = getelementptr %struct.AGenericCall* %this, i32 0, i32 1		; <%struct.ComponentParameters**> [#uses=1]
-	%tmp47 = load %struct.ComponentParameters** %tmp46, align 8		; <%struct.ComponentParameters*> [#uses=1]
+	%tmp46 = getelementptr %struct.AGenericCall, %struct.AGenericCall* %this, i32 0, i32 1		; <%struct.ComponentParameters**> [#uses=1]
+	%tmp47 = load %struct.ComponentParameters*, %struct.ComponentParameters** %tmp46, align 8		; <%struct.ComponentParameters*> [#uses=1]
 	%tmp4849 = bitcast %struct.ComponentParameters* %tmp47 to i8*		; <i8*> [#uses=1]
 	%tmp505152 = sext i16 %tmp4243 to i64		; <i64> [#uses=1]
-	%tmp53 = getelementptr i8* %tmp4849, i64 %tmp505152		; <i8*> [#uses=1]
+	%tmp53 = getelementptr i8, i8* %tmp4849, i64 %tmp505152		; <i8*> [#uses=1]
 	%tmp5354 = bitcast i8* %tmp53 to i64*		; <i64*> [#uses=1]
-	%tmp58 = load i64* %tmp5354, align 8		; <i64> [#uses=1]
+	%tmp58 = load i64, i64* %tmp5354, align 8		; <i64> [#uses=1]
 	%tmp59 = icmp eq i64 %tmp58, 0		; <i1> [#uses=1]
 	br i1 %tmp59, label %UnifiedReturnBlock, label %cond_true63
 
 cond_true63:		; preds = %cond_next
-	%tmp65 = getelementptr %struct.AGenericCall* %this, i32 0, i32 0		; <%struct.AGenericManager**> [#uses=1]
-	%tmp66 = load %struct.AGenericManager** %tmp65, align 8		; <%struct.AGenericManager*> [#uses=1]
+	%tmp65 = getelementptr %struct.AGenericCall, %struct.AGenericCall* %this, i32 0, i32 0		; <%struct.AGenericManager**> [#uses=1]
+	%tmp66 = load %struct.AGenericManager*, %struct.AGenericManager** %tmp65, align 8		; <%struct.AGenericManager*> [#uses=1]
 	%tmp69 = tail call i32 @_ZN15AGenericManager24DefaultComponentInstanceERP23ComponentInstanceRecord( %struct.AGenericManager* %tmp66, %struct.ComponentInstanceRecord** %instance )		; <i32> [#uses=1]
 	ret i32 %tmp69
 
diff --git a/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll b/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll
index 305968ac3778..3cc3b83a3405 100644
--- a/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll
+++ b/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll
@@ -15,21 +15,21 @@
 
 define void @_GLOBAL__I__ZN5Pooma5pinfoE() nounwind  {
 entry:
-	store i32 (...)** getelementptr ([10 x i32 (...)*]* @_ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE, i32 0, i32 8), i32 (...)*** null, align 4
+	store i32 (...)** getelementptr ([10 x i32 (...)*], [10 x i32 (...)*]* @_ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE, i32 0, i32 8), i32 (...)*** null, align 4
 	%tmp96.i.i142.i = call i8* @_Znwm( i32 180 ) nounwind 		; <i8*> [#uses=2]
 	call void @_ZNSt8ios_baseC2Ev( %"struct.std::ios_base"* null ) nounwind 
-	store i32 (...)** getelementptr ([4 x i32 (...)*]* @_ZTVSt9basic_iosIcSt11char_traitsIcEE, i32 0, i32 2), i32 (...)*** null, align 4
+	store i32 (...)** getelementptr ([4 x i32 (...)*], [4 x i32 (...)*]* @_ZTVSt9basic_iosIcSt11char_traitsIcEE, i32 0, i32 2), i32 (...)*** null, align 4
 	store i32 (...)** null, i32 (...)*** null, align 4
-	%ctg2242.i.i163.i = getelementptr i8* %tmp96.i.i142.i, i32 0		; <i8*> [#uses=1]
-	%tmp150.i.i164.i = load i8** getelementptr ([4 x i8*]* @_ZTTSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE, i32 0, i64 2), align 4		; <i8*> [#uses=1]
+	%ctg2242.i.i163.i = getelementptr i8, i8* %tmp96.i.i142.i, i32 0		; <i8*> [#uses=1]
+	%tmp150.i.i164.i = load i8*, i8** getelementptr ([4 x i8*], [4 x i8*]* @_ZTTSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE, i32 0, i64 2), align 4		; <i8*> [#uses=1]
 	%tmp150151.i.i165.i = bitcast i8* %tmp150.i.i164.i to i32 (...)**		; <i32 (...)**> [#uses=1]
 	%tmp153.i.i166.i = bitcast i8* %ctg2242.i.i163.i to i32 (...)***		; <i32 (...)***> [#uses=1]
 	store i32 (...)** %tmp150151.i.i165.i, i32 (...)*** %tmp153.i.i166.i, align 4
 	%tmp159.i.i167.i = bitcast i8* %tmp96.i.i142.i to i32 (...)***		; <i32 (...)***> [#uses=1]
-	store i32 (...)** getelementptr ([10 x i32 (...)*]* @_ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE, i32 0, i32 3), i32 (...)*** %tmp159.i.i167.i, align 4
-	store i32 (...)** getelementptr ([16 x i32 (...)*]* @_ZTVSt15basic_streambufIcSt11char_traitsIcEE, i32 0, i32 2), i32 (...)*** null, align 4
+	store i32 (...)** getelementptr ([10 x i32 (...)*], [10 x i32 (...)*]* @_ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE, i32 0, i32 3), i32 (...)*** %tmp159.i.i167.i, align 4
+	store i32 (...)** getelementptr ([16 x i32 (...)*], [16 x i32 (...)*]* @_ZTVSt15basic_streambufIcSt11char_traitsIcEE, i32 0, i32 2), i32 (...)*** null, align 4
 	call void @_ZNSt6localeC1Ev( %"struct.std::locale"* null ) nounwind 
-	store i32 (...)** getelementptr ([16 x i32 (...)*]* @_ZTVSt15basic_stringbufIcSt11char_traitsIcESaIcEE, i32 0, i32 2), i32 (...)*** null, align 4
+	store i32 (...)** getelementptr ([16 x i32 (...)*], [16 x i32 (...)*]* @_ZTVSt15basic_stringbufIcSt11char_traitsIcESaIcEE, i32 0, i32 2), i32 (...)*** null, align 4
 	unreachable
 }
 
diff --git a/test/CodeGen/X86/2008-04-09-BranchFolding.ll b/test/CodeGen/X86/2008-04-09-BranchFolding.ll
index f4b2d719ae14..f21a6f37f4b5 100644
--- a/test/CodeGen/X86/2008-04-09-BranchFolding.ll
+++ b/test/CodeGen/X86/2008-04-09-BranchFolding.ll
@@ -16,7 +16,7 @@ bb140:		; preds = %entry
 bb17.i:		; preds = %bb140
 	ret %struct.tree_node* null
 bb143:		; preds = %entry
-	%tmp8.i43 = load %struct.tree_node** null, align 4		; <%struct.tree_node*> [#uses=1]
+	%tmp8.i43 = load %struct.tree_node*, %struct.tree_node** null, align 4		; <%struct.tree_node*> [#uses=1]
 	br i1 %tmp3.i40, label %bb160, label %bb9.i48
 bb9.i48:		; preds = %bb143
 	ret %struct.tree_node* null
@@ -39,7 +39,7 @@ bb226.i:		; preds = %bb73.i
 bb273.i:		; preds = %bb226.i
 	ret %struct.tree_node* null
 bb260:		; preds = %bb226.i
-	tail call void (i8*, i32, ...)* @pedwarn_with_file_and_line( i8* %file.0, i32 %line.0, i8* null ) nounwind 
+	tail call void (i8*, i32, ...) @pedwarn_with_file_and_line( i8* %file.0, i32 %line.0, i8* null ) nounwind 
 	ret %struct.tree_node* null
 bb344:		; preds = %bb174
 	ret %struct.tree_node* null
diff --git a/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll b/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
index 0742371dc9ba..b52659134c1b 100644
--- a/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
+++ b/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
@@ -40,10 +40,10 @@
 
 define void @"-[AA BB:optionIndex:delegate:CC:contextInfo:]"(%struct.AA* %self, %struct._message_ref_t* %_cmd, %struct.NSError* %inError, i64 %inOptionIndex, %struct.NSObject* %inDelegate, %struct.objc_selector* %inDidRecoverSelector, i8* %inContextInfo) {
 entry:
-	%tmp105 = load %struct.NSArray** null, align 8		; <%struct.NSArray*> [#uses=1]
-	%tmp107 = load %struct.NSObject** null, align 8		; <%struct.NSObject*> [#uses=1]
+	%tmp105 = load %struct.NSArray*, %struct.NSArray** null, align 8		; <%struct.NSArray*> [#uses=1]
+	%tmp107 = load %struct.NSObject*, %struct.NSObject** null, align 8		; <%struct.NSObject*> [#uses=1]
 	call void null( %struct.NSObject* %tmp107, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_228", %struct.NSArray* %tmp105, i8 signext  0 )
-	%tmp111 = call %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...)* @objc_msgSend( %struct.NSObject* null, %struct.objc_selector* null, i32 0, i8* null )		; <%struct.NSObject*> [#uses=0]
+	%tmp111 = call %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...) @objc_msgSend( %struct.NSObject* null, %struct.objc_selector* null, i32 0, i8* null )		; <%struct.NSObject*> [#uses=0]
 	ret void
 }
 
diff --git a/test/CodeGen/X86/2008-04-16-CoalescerBug.ll b/test/CodeGen/X86/2008-04-16-CoalescerBug.ll
index 3ccc0fe16340..1488034f2eb9 100644
--- a/test/CodeGen/X86/2008-04-16-CoalescerBug.ll
+++ b/test/CodeGen/X86/2008-04-16-CoalescerBug.ll
@@ -22,7 +22,7 @@ bb94.us:		; preds = %bb71.us, %bb53.us
 	store i16 %tmp113.us, i16* null, align 2
 	br label %bb53.us
 bb71.us:		; preds = %bb53.us
-	%tmp80.us = load i8* null, align 1		; <i8> [#uses=1]
+	%tmp80.us = load i8, i8* null, align 1		; <i8> [#uses=1]
 	%tmp8081.us = zext i8 %tmp80.us to i32		; <i32> [#uses=1]
 	%tmp87.us = mul i32 %tmp8081.us, 0		; <i32> [#uses=1]
 	%tmp92.us = add i32 0, %tmp87.us		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2008-04-16-ReMatBug.ll b/test/CodeGen/X86/2008-04-16-ReMatBug.ll
index 3a1de11ea21b..9cae76f658d8 100644
--- a/test/CodeGen/X86/2008-04-16-ReMatBug.ll
+++ b/test/CodeGen/X86/2008-04-16-ReMatBug.ll
@@ -15,7 +15,7 @@ bb:		; preds = %entry
 bb28:		; preds = %entry
 	br i1 false, label %bb37, label %done
 bb37:		; preds = %bb28
-	%tmp46 = getelementptr %struct.GENV_t* %tmp12, i32 0, i32 10		; <i16*> [#uses=1]
+	%tmp46 = getelementptr %struct.GENV_t, %struct.GENV_t* %tmp12, i32 0, i32 10		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp46, align 4
 	br i1 false, label %bb74, label %bb92
 bb74:		; preds = %bb37
diff --git a/test/CodeGen/X86/2008-04-17-CoalescerBug.ll b/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
index f244793e7a95..d1cfb447a2c3 100644
--- a/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
+++ b/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
@@ -33,16 +33,16 @@ bb161.i:		; preds = %bb142.i
 bb182.i:		; preds = %bb142.i
 	ret void
 bb3261:		; preds = %bb7834, %bb161.i
-	%tmp3263 = load i32* null, align 4		; <i32> [#uses=1]
+	%tmp3263 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	%tmp3264 = icmp eq i32 %tmp3263, 37		; <i1> [#uses=1]
 	br i1 %tmp3264, label %bb3306, label %bb3267
 bb3267:		; preds = %bb3261
 	ret void
 bb3306:		; preds = %bb3261
-	%tmp3310 = invoke %struct.wxStringBase* @_ZN12wxStringBaseaSEPKw( %struct.wxStringBase* null, i32* getelementptr ([5 x i32]* @.str89, i32 0, i32 0) )
+	%tmp3310 = invoke %struct.wxStringBase* @_ZN12wxStringBaseaSEPKw( %struct.wxStringBase* null, i32* getelementptr ([5 x i32], [5 x i32]* @.str89, i32 0, i32 0) )
 			to label %bb3314 unwind label %lpad		; <%struct.wxStringBase*> [#uses=0]
 bb3314:		; preds = %bb3306
-	%tmp3316 = load i32* null, align 4		; <i32> [#uses=1]
+	%tmp3316 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	switch i32 %tmp3316, label %bb7595 [
 		 i32 0, label %bb7819
 		 i32 37, label %bb7806
@@ -108,7 +108,7 @@ bb278.i8617:		; preds = %bb182.i8560
 	%timeOnly50.0.i8622 = add i32 0, 0		; <i32> [#uses=1]
 	br i1 %foo, label %bb440.i8663, label %bb448.i8694
 bb440.i8663:		; preds = %bb278.i8617
-	invoke void @_Z10wxOnAssertPKwiPKcS0_S0_( i32* getelementptr ([27 x i32]* @.str, i32 0, i32 0), i32 1717, i8* getelementptr ([6 x i8]* @_ZZNK10wxDateTime5GetTmERKNS_8TimeZoneEE12__FUNCTION__, i32 0, i32 0), i32* getelementptr ([29 x i32]* @.str33, i32 0, i32 0), i32* getelementptr ([14 x i32]* @.str4, i32 0, i32 0) )
+	invoke void @_Z10wxOnAssertPKwiPKcS0_S0_( i32* getelementptr ([27 x i32], [27 x i32]* @.str, i32 0, i32 0), i32 1717, i8* getelementptr ([6 x i8], [6 x i8]* @_ZZNK10wxDateTime5GetTmERKNS_8TimeZoneEE12__FUNCTION__, i32 0, i32 0), i32* getelementptr ([29 x i32], [29 x i32]* @.str33, i32 0, i32 0), i32* getelementptr ([14 x i32], [14 x i32]* @.str4, i32 0, i32 0) )
 			to label %bb448.i8694 unwind label %lpad
 bb448.i8694:		; preds = %bb440.i8663, %bb278.i8617
 	%tmp477.i8669 = srem i32 %timeOnly50.0.i8622, 1000		; <i32> [#uses=1]
@@ -117,13 +117,13 @@ bb448.i8694:		; preds = %bb440.i8663, %bb278.i8617
 invcont5814:		; preds = %bb448.i8694, %bb265.i8606
 	%tmp812.0.0 = phi i16 [ %tmp477478.i8670, %bb448.i8694 ], [ %tmp273274.i8595, %bb265.i8606 ]		; <i16> [#uses=1]
 	%tmp58165817 = zext i16 %tmp812.0.0 to i32		; <i32> [#uses=1]
-	invoke void (%struct.wxString*, i32*, ...)* @_ZN8wxString6FormatEPKwz( %struct.wxString* noalias sret  null, i32* null, i32 %tmp58165817 )
+	invoke void (%struct.wxString*, i32*, ...) @_ZN8wxString6FormatEPKwz( %struct.wxString* noalias sret  null, i32* null, i32 %tmp58165817 )
 			to label %invcont5831 unwind label %lpad
 invcont5831:		; preds = %invcont5814
 	%tmp5862 = invoke zeroext  i8 @_ZN12wxStringBase10ConcatSelfEmPKwm( %struct.wxStringBase* null, i32 0, i32* null, i32 0 ) 
 			to label %bb7834 unwind label %lpad8185		; <i8> [#uses=0]
 bb5968:		; preds = %bb3314
-	invoke void (%struct.wxString*, i32*, ...)* @_ZN8wxString6FormatEPKwz( %struct.wxString* noalias sret  null, i32* null, i32 0 )
+	invoke void (%struct.wxString*, i32*, ...) @_ZN8wxString6FormatEPKwz( %struct.wxString* noalias sret  null, i32* null, i32 0 )
 			to label %invcont5981 unwind label %lpad
 invcont5981:		; preds = %bb5968
 	ret void
diff --git a/test/CodeGen/X86/2008-04-24-pblendw-fold-crash.ll b/test/CodeGen/X86/2008-04-24-pblendw-fold-crash.ll
index 86bce8e977ac..06f7907fec9e 100644
--- a/test/CodeGen/X86/2008-04-24-pblendw-fold-crash.ll
+++ b/test/CodeGen/X86/2008-04-24-pblendw-fold-crash.ll
@@ -6,7 +6,7 @@ target triple = "i386-apple-darwin8"
 
 define i32 @main() nounwind  {
 entry:
-	%tmp122 = load <2 x i64>* null, align 16		; <<2 x i64>> [#uses=1]
+	%tmp122 = load <2 x i64>, <2 x i64>* null, align 16		; <<2 x i64>> [#uses=1]
 	%tmp126 = bitcast <2 x i64> %tmp122 to <8 x i16>		; <<8 x i16>> [#uses=1]
 	%tmp129 = call <8 x i16> @llvm.x86.sse41.pblendw( <8 x i16> zeroinitializer, <8 x i16> %tmp126, i32 2 ) nounwind 		; <<8 x i16>> [#uses=0]
 	ret i32 0
diff --git a/test/CodeGen/X86/2008-04-28-CoalescerBug.ll b/test/CodeGen/X86/2008-04-28-CoalescerBug.ll
index 7c04206de72f..06bbd74e8bde 100644
--- a/test/CodeGen/X86/2008-04-28-CoalescerBug.ll
+++ b/test/CodeGen/X86/2008-04-28-CoalescerBug.ll
@@ -33,7 +33,7 @@ bb13101:		; preds = %bb13088
 
 bb13107:		; preds = %bb13101, %bb13088
 	%iftmp.684.0 = phi i32 [ 0, %bb13101 ], [ 65535, %bb13088 ]		; <i32> [#uses=2]
-	%tmp13111 = load i64* null, align 8		; <i64> [#uses=3]
+	%tmp13111 = load i64, i64* null, align 8		; <i64> [#uses=3]
 	%tmp13116 = lshr i64 %tmp13111, 16		; <i64> [#uses=1]
 	%tmp1311613117 = trunc i64 %tmp13116 to i32		; <i32> [#uses=1]
 	%tmp13118 = and i32 %tmp1311613117, 65535		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2008-05-09-PHIElimBug.ll b/test/CodeGen/X86/2008-05-09-PHIElimBug.ll
index cea0076076d6..8ed1b2a759b8 100644
--- a/test/CodeGen/X86/2008-05-09-PHIElimBug.ll
+++ b/test/CodeGen/X86/2008-05-09-PHIElimBug.ll
@@ -14,7 +14,7 @@ bb23821:		; preds = %entry
 	br i1 false, label %bb23830, label %bb23827
 
 bb23827:		; preds = %bb23821
-	%tmp23829 = getelementptr %struct.V* null, i32 0, i32 42		; <i32*> [#uses=0]
+	%tmp23829 = getelementptr %struct.V, %struct.V* null, i32 0, i32 42		; <i32*> [#uses=0]
 	br label %bb23830
 
 bb23830:		; preds = %bb23827, %bb23821, %bb23816.preheader
diff --git a/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll b/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll
index 5ceb5464d2b0..0e4ef1c3260a 100644
--- a/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll
+++ b/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse2
 
 define fastcc void @glgVectorFloatConversion() nounwind  {
-	%tmp12745 = load <4 x float>* null, align 16		; <<4 x float>> [#uses=1]
+	%tmp12745 = load <4 x float>, <4 x float>* null, align 16		; <<4 x float>> [#uses=1]
 	%tmp12773 = insertelement <4 x float> %tmp12745, float 1.000000e+00, i32 1		; <<4 x float>> [#uses=1]
 	%tmp12774 = insertelement <4 x float> %tmp12773, float 0.000000e+00, i32 2		; <<4 x float>> [#uses=1]
 	%tmp12775 = insertelement <4 x float> %tmp12774, float 1.000000e+00, i32 3		; <<4 x float>> [#uses=1]
diff --git a/test/CodeGen/X86/2008-05-12-tailmerge-5.ll b/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
index 4852e89c4d99..0669a3267180 100644
--- a/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
+++ b/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
@@ -17,36 +17,36 @@ entry:
 	%d_addr = alloca i8		; <i8*> [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	%tmp = bitcast %struct.BoundaryAlignment* %str_addr to { i64, i64 }*		; <{ i64, i64 }*> [#uses=1]
-	%tmp1 = getelementptr { i64, i64 }* %tmp, i32 0, i32 0		; <i64*> [#uses=1]
+	%tmp1 = getelementptr { i64, i64 }, { i64, i64 }* %tmp, i32 0, i32 0		; <i64*> [#uses=1]
 	store i64 %str.0, i64* %tmp1
 	%tmp2 = bitcast %struct.BoundaryAlignment* %str_addr to { i64, i64 }*		; <{ i64, i64 }*> [#uses=1]
-	%tmp3 = getelementptr { i64, i64 }* %tmp2, i32 0, i32 1		; <i64*> [#uses=1]
+	%tmp3 = getelementptr { i64, i64 }, { i64, i64 }* %tmp2, i32 0, i32 1		; <i64*> [#uses=1]
 	%bc = bitcast i64* %tmp3 to i8*		; <i8*> [#uses=2]
 	%byte = trunc i64 %str.1 to i8		; <i8> [#uses=1]
 	store i8 %byte, i8* %bc
 	%shft = lshr i64 %str.1, 8		; <i64> [#uses=2]
-	%Loc = getelementptr i8* %bc, i32 1		; <i8*> [#uses=2]
+	%Loc = getelementptr i8, i8* %bc, i32 1		; <i8*> [#uses=2]
 	%byte4 = trunc i64 %shft to i8		; <i8> [#uses=1]
 	store i8 %byte4, i8* %Loc
 	%shft5 = lshr i64 %shft, 8		; <i64> [#uses=2]
-	%Loc6 = getelementptr i8* %Loc, i32 1		; <i8*> [#uses=2]
+	%Loc6 = getelementptr i8, i8* %Loc, i32 1		; <i8*> [#uses=2]
 	%byte7 = trunc i64 %shft5 to i8		; <i8> [#uses=1]
 	store i8 %byte7, i8* %Loc6
 	%shft8 = lshr i64 %shft5, 8		; <i64> [#uses=2]
-	%Loc9 = getelementptr i8* %Loc6, i32 1		; <i8*> [#uses=2]
+	%Loc9 = getelementptr i8, i8* %Loc6, i32 1		; <i8*> [#uses=2]
 	%byte10 = trunc i64 %shft8 to i8		; <i8> [#uses=1]
 	store i8 %byte10, i8* %Loc9
 	%shft11 = lshr i64 %shft8, 8		; <i64> [#uses=0]
-	%Loc12 = getelementptr i8* %Loc9, i32 1		; <i8*> [#uses=0]
+	%Loc12 = getelementptr i8, i8* %Loc9, i32 1		; <i8*> [#uses=0]
 	store i16 %s, i16* %s_addr
 	store i32 %j, i32* %j_addr
 	store i8 %c, i8* %c_addr
 	store i16 %t, i16* %t_addr
 	store i16 %u, i16* %u_addr
 	store i8 %d, i8* %d_addr
-	%tmp13 = getelementptr %struct.BoundaryAlignment* %str_addr, i32 0, i32 0		; <[3 x i8]*> [#uses=1]
+	%tmp13 = getelementptr %struct.BoundaryAlignment, %struct.BoundaryAlignment* %str_addr, i32 0, i32 0		; <[3 x i8]*> [#uses=1]
 	%tmp1314 = bitcast [3 x i8]* %tmp13 to i32*		; <i32*> [#uses=1]
-	%tmp15 = load i32* %tmp1314, align 4		; <i32> [#uses=1]
+	%tmp15 = load i32, i32* %tmp1314, align 4		; <i32> [#uses=1]
 	%tmp16 = shl i32 %tmp15, 14		; <i32> [#uses=1]
 	%tmp17 = ashr i32 %tmp16, 23		; <i32> [#uses=1]
 	%tmp1718 = trunc i32 %tmp17 to i16		; <i16> [#uses=1]
@@ -57,32 +57,32 @@ entry:
 	%sextl21 = shl i16 %sextr, 7		; <i16> [#uses=1]
 	%sextr22 = ashr i16 %sextl21, 7		; <i16> [#uses=1]
 	%sextr2223 = sext i16 %sextr22 to i32		; <i32> [#uses=1]
-	%tmp24 = load i32* %j_addr, align 4		; <i32> [#uses=1]
+	%tmp24 = load i32, i32* %j_addr, align 4		; <i32> [#uses=1]
 	%tmp25 = icmp ne i32 %sextr2223, %tmp24		; <i1> [#uses=1]
 	%tmp2526 = zext i1 %tmp25 to i8		; <i8> [#uses=1]
 	%toBool = icmp ne i8 %tmp2526, 0		; <i1> [#uses=1]
 	br i1 %toBool, label %bb, label %bb27
 
 bb:		; preds = %entry
-	call void (...)* @abort( ) noreturn nounwind 
+	call void (...) @abort( ) noreturn nounwind 
 	unreachable
 
 bb27:		; preds = %entry
-	%tmp28 = getelementptr %struct.BoundaryAlignment* %str_addr, i32 0, i32 1		; <i8*> [#uses=1]
-	%tmp29 = load i8* %tmp28, align 4		; <i8> [#uses=1]
-	%tmp30 = load i8* %c_addr, align 1		; <i8> [#uses=1]
+	%tmp28 = getelementptr %struct.BoundaryAlignment, %struct.BoundaryAlignment* %str_addr, i32 0, i32 1		; <i8*> [#uses=1]
+	%tmp29 = load i8, i8* %tmp28, align 4		; <i8> [#uses=1]
+	%tmp30 = load i8, i8* %c_addr, align 1		; <i8> [#uses=1]
 	%tmp31 = icmp ne i8 %tmp29, %tmp30		; <i1> [#uses=1]
 	%tmp3132 = zext i1 %tmp31 to i8		; <i8> [#uses=1]
 	%toBool33 = icmp ne i8 %tmp3132, 0		; <i1> [#uses=1]
 	br i1 %toBool33, label %bb34, label %bb35
 
 bb34:		; preds = %bb27
-	call void (...)* @abort( ) noreturn nounwind 
+	call void (...) @abort( ) noreturn nounwind 
 	unreachable
 
 bb35:		; preds = %bb27
-	%tmp36 = getelementptr %struct.BoundaryAlignment* %str_addr, i32 0, i32 2		; <i16*> [#uses=1]
-	%tmp37 = load i16* %tmp36, align 4		; <i16> [#uses=1]
+	%tmp36 = getelementptr %struct.BoundaryAlignment, %struct.BoundaryAlignment* %str_addr, i32 0, i32 2		; <i16*> [#uses=1]
+	%tmp37 = load i16, i16* %tmp36, align 4		; <i16> [#uses=1]
 	%tmp38 = shl i16 %tmp37, 7		; <i16> [#uses=1]
 	%tmp39 = ashr i16 %tmp38, 7		; <i16> [#uses=1]
 	%sextl40 = shl i16 %tmp39, 7		; <i16> [#uses=1]
@@ -91,19 +91,19 @@ bb35:		; preds = %bb27
 	%sextr43 = ashr i16 %sextl42, 7		; <i16> [#uses=0]
 	%sextl44 = shl i16 %sextr41, 7		; <i16> [#uses=1]
 	%sextr45 = ashr i16 %sextl44, 7		; <i16> [#uses=1]
-	%tmp46 = load i16* %t_addr, align 2		; <i16> [#uses=1]
+	%tmp46 = load i16, i16* %t_addr, align 2		; <i16> [#uses=1]
 	%tmp47 = icmp ne i16 %sextr45, %tmp46		; <i1> [#uses=1]
 	%tmp4748 = zext i1 %tmp47 to i8		; <i8> [#uses=1]
 	%toBool49 = icmp ne i8 %tmp4748, 0		; <i1> [#uses=1]
 	br i1 %toBool49, label %bb50, label %bb51
 
 bb50:		; preds = %bb35
-	call void (...)* @abort( ) noreturn nounwind 
+	call void (...) @abort( ) noreturn nounwind 
 	unreachable
 
 bb51:		; preds = %bb35
-	%tmp52 = getelementptr %struct.BoundaryAlignment* %str_addr, i32 0, i32 3		; <i16*> [#uses=1]
-	%tmp53 = load i16* %tmp52, align 4		; <i16> [#uses=1]
+	%tmp52 = getelementptr %struct.BoundaryAlignment, %struct.BoundaryAlignment* %str_addr, i32 0, i32 3		; <i16*> [#uses=1]
+	%tmp53 = load i16, i16* %tmp52, align 4		; <i16> [#uses=1]
 	%tmp54 = shl i16 %tmp53, 7		; <i16> [#uses=1]
 	%tmp55 = ashr i16 %tmp54, 7		; <i16> [#uses=1]
 	%sextl56 = shl i16 %tmp55, 7		; <i16> [#uses=1]
@@ -112,27 +112,27 @@ bb51:		; preds = %bb35
 	%sextr59 = ashr i16 %sextl58, 7		; <i16> [#uses=0]
 	%sextl60 = shl i16 %sextr57, 7		; <i16> [#uses=1]
 	%sextr61 = ashr i16 %sextl60, 7		; <i16> [#uses=1]
-	%tmp62 = load i16* %u_addr, align 2		; <i16> [#uses=1]
+	%tmp62 = load i16, i16* %u_addr, align 2		; <i16> [#uses=1]
 	%tmp63 = icmp ne i16 %sextr61, %tmp62		; <i1> [#uses=1]
 	%tmp6364 = zext i1 %tmp63 to i8		; <i8> [#uses=1]
 	%toBool65 = icmp ne i8 %tmp6364, 0		; <i1> [#uses=1]
 	br i1 %toBool65, label %bb66, label %bb67
 
 bb66:		; preds = %bb51
-	call void (...)* @abort( ) noreturn nounwind 
+	call void (...) @abort( ) noreturn nounwind 
 	unreachable
 
 bb67:		; preds = %bb51
-	%tmp68 = getelementptr %struct.BoundaryAlignment* %str_addr, i32 0, i32 4		; <i8*> [#uses=1]
-	%tmp69 = load i8* %tmp68, align 4		; <i8> [#uses=1]
-	%tmp70 = load i8* %d_addr, align 1		; <i8> [#uses=1]
+	%tmp68 = getelementptr %struct.BoundaryAlignment, %struct.BoundaryAlignment* %str_addr, i32 0, i32 4		; <i8*> [#uses=1]
+	%tmp69 = load i8, i8* %tmp68, align 4		; <i8> [#uses=1]
+	%tmp70 = load i8, i8* %d_addr, align 1		; <i8> [#uses=1]
 	%tmp71 = icmp ne i8 %tmp69, %tmp70		; <i1> [#uses=1]
 	%tmp7172 = zext i1 %tmp71 to i8		; <i8> [#uses=1]
 	%toBool73 = icmp ne i8 %tmp7172, 0		; <i1> [#uses=1]
 	br i1 %toBool73, label %bb74, label %bb75
 
 bb74:		; preds = %bb67
-	call void (...)* @abort( ) noreturn nounwind 
+	call void (...) @abort( ) noreturn nounwind 
 	unreachable
 
 bb75:		; preds = %bb67
diff --git a/test/CodeGen/X86/2008-05-21-CoalescerBug.ll b/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
index ac167b009a8d..c6709a86d85b 100644
--- a/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
+++ b/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
@@ -74,7 +74,7 @@ entry:
 	br label %bb497
 
 bb483:		; preds = %bb497
-	%tmp496 = load %struct.tree_node** null, align 4		; <%struct.tree_node*> [#uses=1]
+	%tmp496 = load %struct.tree_node*, %struct.tree_node** null, align 4		; <%struct.tree_node*> [#uses=1]
 	br label %bb497
 
 bb497:		; preds = %bb483, %entry
@@ -87,9 +87,9 @@ bb502:		; preds = %bb497
 	br i1 %foo, label %bb507, label %bb841
 
 bb507:		; preds = %bb502
-	%tmp517 = getelementptr %struct.tree_node* %last.0, i32 0, i32 0		; <%struct.tree_function_decl*> [#uses=1]
+	%tmp517 = getelementptr %struct.tree_node, %struct.tree_node* %last.0, i32 0, i32 0		; <%struct.tree_function_decl*> [#uses=1]
 	%tmp517518 = bitcast %struct.tree_function_decl* %tmp517 to %struct.tree_common*		; <%struct.tree_common*> [#uses=1]
-	%tmp519 = getelementptr %struct.tree_common* %tmp517518, i32 0, i32 0		; <%struct.tree_node**> [#uses=1]
+	%tmp519 = getelementptr %struct.tree_common, %struct.tree_common* %tmp517518, i32 0, i32 0		; <%struct.tree_node**> [#uses=1]
 	store %struct.tree_node* null, %struct.tree_node** %tmp519, align 4
 	br label %bb841
 
diff --git a/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll b/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll
index da56ce7ab583..a91a422f55d1 100644
--- a/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll
+++ b/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll
@@ -2,7 +2,7 @@
 
 define void @a(<4 x float>* %x) nounwind  {
 entry:
-        %tmp2 = load <4 x float>* %x, align 1
+        %tmp2 = load <4 x float>, <4 x float>* %x, align 1
         %inv = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %tmp2)
         store <4 x float> %inv, <4 x float>* %x, align 1
         ret void
diff --git a/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll b/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll
index 4e73b5aa1cdb..fc7ddf0bc67a 100644
--- a/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll
+++ b/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll
@@ -24,7 +24,7 @@ lpad243:		; preds = %bb37
         %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
                  cleanup
 	%eh_ptr244 = extractvalue { i8*, i32 } %exn, 0
-	store i32 (...)** getelementptr ([5 x i32 (...)*]* @_ZTVN10Evaluation10GridOutputILi3EEE, i32 0, i32 2), i32 (...)*** null, align 8
+	store i32 (...)** getelementptr ([5 x i32 (...)*], [5 x i32 (...)*]* @_ZTVN10Evaluation10GridOutputILi3EEE, i32 0, i32 2), i32 (...)*** null, align 8
 	%tmp133 = call i8* @__cxa_begin_catch( i8* %eh_ptr244 ) nounwind 		; <i8*> [#uses=0]
 	unreachable
 }
diff --git a/test/CodeGen/X86/2008-06-13-NotVolatileLoadStore.ll b/test/CodeGen/X86/2008-06-13-NotVolatileLoadStore.ll
index a6234d377df3..422d68e7ff49 100644
--- a/test/CodeGen/X86/2008-06-13-NotVolatileLoadStore.ll
+++ b/test/CodeGen/X86/2008-06-13-NotVolatileLoadStore.ll
@@ -13,9 +13,9 @@ define i16 @f(i64 %x) {
 	%b = bitcast i64 %x to double		; <double> [#uses=1]
 	store double %b, double* @atomic
 	store double 0.000000e+00, double* @atomic2
-	%l = load i32* @ioport		; <i32> [#uses=1]
+	%l = load i32, i32* @ioport		; <i32> [#uses=1]
 	%t = trunc i32 %l to i16		; <i16> [#uses=1]
-	%l2 = load i32* @ioport2		; <i32> [#uses=1]
+	%l2 = load i32, i32* @ioport2		; <i32> [#uses=1]
 	%tmp = lshr i32 %l2, 16		; <i32> [#uses=1]
 	%t2 = trunc i32 %tmp to i16		; <i16> [#uses=1]
 	%f = add i16 %t, %t2		; <i16> [#uses=1]
diff --git a/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll b/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll
index 037559edaf57..5a05ec13f35b 100644
--- a/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll
+++ b/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll
@@ -12,9 +12,9 @@ define i16 @f(i64 %x, double %y) {
 	store volatile double 0.000000e+00, double* @atomic2 ; one processor operation only
 	%b2 = bitcast double %y to i64		; <i64> [#uses=1]
 	store volatile i64 %b2, i64* @anything ; may transform to store of double
-	%l = load volatile i32* @ioport		; must not narrow
+	%l = load volatile i32, i32* @ioport		; must not narrow
 	%t = trunc i32 %l to i16		; <i16> [#uses=1]
-	%l2 = load volatile i32* @ioport		; must not narrow
+	%l2 = load volatile i32, i32* @ioport		; must not narrow
 	%tmp = lshr i32 %l2, 16		; <i32> [#uses=1]
 	%t2 = trunc i32 %tmp to i16		; <i16> [#uses=1]
 	%f = add i16 %t, %t2		; <i16> [#uses=1]
diff --git a/test/CodeGen/X86/2008-06-16-SubregsBug.ll b/test/CodeGen/X86/2008-06-16-SubregsBug.ll
index 4d4819ab05d5..cdd1b0bfe607 100644
--- a/test/CodeGen/X86/2008-06-16-SubregsBug.ll
+++ b/test/CodeGen/X86/2008-06-16-SubregsBug.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=i386-apple-darwin | grep mov | count 4
 
 define i16 @test(i16* %tmp179) nounwind  {
-	%tmp180 = load i16* %tmp179, align 2		; <i16> [#uses=2]
+	%tmp180 = load i16, i16* %tmp179, align 2		; <i16> [#uses=2]
 	%tmp184 = and i16 %tmp180, -1024		; <i16> [#uses=1]
 	%tmp186 = icmp eq i16 %tmp184, -32768		; <i1> [#uses=1]
 	br i1 %tmp186, label %bb189, label %bb288
diff --git a/test/CodeGen/X86/2008-07-07-DanglingDeadInsts.ll b/test/CodeGen/X86/2008-07-07-DanglingDeadInsts.ll
index 46341fc87103..c92768c91d79 100644
--- a/test/CodeGen/X86/2008-07-07-DanglingDeadInsts.ll
+++ b/test/CodeGen/X86/2008-07-07-DanglingDeadInsts.ll
@@ -27,8 +27,8 @@ bb39:		; preds = %bb39, %bb40.preheader
 	br i1 false, label %bb39, label %bb49.outer
 
 bb49.outer:		; preds = %bb39, %bb40.preheader
-	getelementptr %struct.res_state* %state, i32 0, i32 3		; <i32*>:1 [#uses=0]
-	getelementptr %struct.res_state* %state, i32 0, i32 7		; <i32*>:2 [#uses=0]
+	getelementptr %struct.res_state, %struct.res_state* %state, i32 0, i32 3		; <i32*>:1 [#uses=0]
+	getelementptr %struct.res_state, %struct.res_state* %state, i32 0, i32 7		; <i32*>:2 [#uses=0]
 	%base10.1 = select i1 false, float* null, float* null		; <float*> [#uses=1]
 	br label %bb74
 
@@ -43,7 +43,7 @@ bb71:		; preds = %bb74, %bb69
 
 bb73:		; preds = %bb71
 	%.rec = add i32 %base10.2.ph.rec, 1		; <i32> [#uses=2]
-	getelementptr float* %base10.1, i32 %.rec		; <float*>:4 [#uses=1]
+	getelementptr float, float* %base10.1, i32 %.rec		; <float*>:4 [#uses=1]
 	br label %bb74
 
 bb74:		; preds = %bb73, %bb71, %bb49.outer
@@ -63,7 +63,7 @@ entry:
 	br i1 false, label %bb17.preheader, label %bb30
 
 bb17.preheader:		; preds = %entry
-	load i32* null, align 4		; <i32>:0 [#uses=0]
+	load i32, i32* null, align 4		; <i32>:0 [#uses=0]
 	br label %bb16
 
 bb16:		; preds = %bb16, %bb17.preheader
@@ -89,7 +89,7 @@ entry:
 define i32 @vorbis_comment_query_count(%struct.vorbis_comment* %vc, i8* %tag) nounwind  {
 entry:
 	%strlen = call i32 @strlen( i8* null )		; <i32> [#uses=1]
-	%endptr = getelementptr i8* null, i32 %strlen		; <i8*> [#uses=0]
+	%endptr = getelementptr i8, i8* null, i32 %strlen		; <i8*> [#uses=0]
 	unreachable
 }
 
diff --git a/test/CodeGen/X86/2008-07-16-CoalescerCrash.ll b/test/CodeGen/X86/2008-07-16-CoalescerCrash.ll
index f56604b75bd7..a1b9d9d5ab93 100644
--- a/test/CodeGen/X86/2008-07-16-CoalescerCrash.ll
+++ b/test/CodeGen/X86/2008-07-16-CoalescerCrash.ll
@@ -26,7 +26,7 @@ bb31:		; preds = %bb6
 	br label %bb33
 
 bb33:		; preds = %bb31, %bb
-	tail call void (%struct.SV*, i8*, ...)* @Perl_sv_catpvf( %struct.SV* %dsv, i8* getelementptr ([8 x i8]* @"\01LC25", i32 0, i64 0), i64 %0 ) nounwind 
+	tail call void (%struct.SV*, i8*, ...) @Perl_sv_catpvf( %struct.SV* %dsv, i8* getelementptr ([8 x i8], [8 x i8]* @"\01LC25", i32 0, i64 0), i64 %0 ) nounwind 
 	unreachable
 
 bb40:		; preds = %entry
diff --git a/test/CodeGen/X86/2008-07-19-movups-spills.ll b/test/CodeGen/X86/2008-07-19-movups-spills.ll
index cd86ee188949..45ea69943e87 100644
--- a/test/CodeGen/X86/2008-07-19-movups-spills.ll
+++ b/test/CodeGen/X86/2008-07-19-movups-spills.ll
@@ -75,38 +75,38 @@ define void @test1() {
 ; CHECK: movups
 ; CHECK: movups
 ; CHECK-NOT: movups
-	load <4 x float>* @0, align 1		; <<4 x float>>:1 [#uses=2]
-	load <4 x float>* @1, align 1		; <<4 x float>>:2 [#uses=3]
-	load <4 x float>* @2, align 1		; <<4 x float>>:3 [#uses=4]
-	load <4 x float>* @3, align 1		; <<4 x float>>:4 [#uses=5]
-	load <4 x float>* @4, align 1		; <<4 x float>>:5 [#uses=6]
-	load <4 x float>* @5, align 1		; <<4 x float>>:6 [#uses=7]
-	load <4 x float>* @6, align 1		; <<4 x float>>:7 [#uses=8]
-	load <4 x float>* @7, align 1		; <<4 x float>>:8 [#uses=9]
-	load <4 x float>* @8, align 1		; <<4 x float>>:9 [#uses=10]
-	load <4 x float>* @9, align 1		; <<4 x float>>:10 [#uses=11]
-	load <4 x float>* @10, align 1		; <<4 x float>>:11 [#uses=12]
-	load <4 x float>* @11, align 1		; <<4 x float>>:12 [#uses=13]
-	load <4 x float>* @12, align 1		; <<4 x float>>:13 [#uses=14]
-	load <4 x float>* @13, align 1		; <<4 x float>>:14 [#uses=15]
-	load <4 x float>* @14, align 1		; <<4 x float>>:15 [#uses=16]
-	load <4 x float>* @15, align 1		; <<4 x float>>:16 [#uses=17]
-	load <4 x float>* @16, align 1		; <<4 x float>>:17 [#uses=18]
-	load <4 x float>* @17, align 1		; <<4 x float>>:18 [#uses=19]
-	load <4 x float>* @18, align 1		; <<4 x float>>:19 [#uses=20]
-	load <4 x float>* @19, align 1		; <<4 x float>>:20 [#uses=21]
-	load <4 x float>* @20, align 1		; <<4 x float>>:21 [#uses=22]
-	load <4 x float>* @21, align 1		; <<4 x float>>:22 [#uses=23]
-	load <4 x float>* @22, align 1		; <<4 x float>>:23 [#uses=24]
-	load <4 x float>* @23, align 1		; <<4 x float>>:24 [#uses=25]
-	load <4 x float>* @24, align 1		; <<4 x float>>:25 [#uses=26]
-	load <4 x float>* @25, align 1		; <<4 x float>>:26 [#uses=27]
-	load <4 x float>* @26, align 1		; <<4 x float>>:27 [#uses=28]
-	load <4 x float>* @27, align 1		; <<4 x float>>:28 [#uses=29]
-	load <4 x float>* @28, align 1		; <<4 x float>>:29 [#uses=30]
-	load <4 x float>* @29, align 1		; <<4 x float>>:30 [#uses=31]
-	load <4 x float>* @30, align 1		; <<4 x float>>:31 [#uses=32]
-	load <4 x float>* @31, align 1		; <<4 x float>>:32 [#uses=33]
+	load <4 x float>, <4 x float>* @0, align 1		; <<4 x float>>:1 [#uses=2]
+	load <4 x float>, <4 x float>* @1, align 1		; <<4 x float>>:2 [#uses=3]
+	load <4 x float>, <4 x float>* @2, align 1		; <<4 x float>>:3 [#uses=4]
+	load <4 x float>, <4 x float>* @3, align 1		; <<4 x float>>:4 [#uses=5]
+	load <4 x float>, <4 x float>* @4, align 1		; <<4 x float>>:5 [#uses=6]
+	load <4 x float>, <4 x float>* @5, align 1		; <<4 x float>>:6 [#uses=7]
+	load <4 x float>, <4 x float>* @6, align 1		; <<4 x float>>:7 [#uses=8]
+	load <4 x float>, <4 x float>* @7, align 1		; <<4 x float>>:8 [#uses=9]
+	load <4 x float>, <4 x float>* @8, align 1		; <<4 x float>>:9 [#uses=10]
+	load <4 x float>, <4 x float>* @9, align 1		; <<4 x float>>:10 [#uses=11]
+	load <4 x float>, <4 x float>* @10, align 1		; <<4 x float>>:11 [#uses=12]
+	load <4 x float>, <4 x float>* @11, align 1		; <<4 x float>>:12 [#uses=13]
+	load <4 x float>, <4 x float>* @12, align 1		; <<4 x float>>:13 [#uses=14]
+	load <4 x float>, <4 x float>* @13, align 1		; <<4 x float>>:14 [#uses=15]
+	load <4 x float>, <4 x float>* @14, align 1		; <<4 x float>>:15 [#uses=16]
+	load <4 x float>, <4 x float>* @15, align 1		; <<4 x float>>:16 [#uses=17]
+	load <4 x float>, <4 x float>* @16, align 1		; <<4 x float>>:17 [#uses=18]
+	load <4 x float>, <4 x float>* @17, align 1		; <<4 x float>>:18 [#uses=19]
+	load <4 x float>, <4 x float>* @18, align 1		; <<4 x float>>:19 [#uses=20]
+	load <4 x float>, <4 x float>* @19, align 1		; <<4 x float>>:20 [#uses=21]
+	load <4 x float>, <4 x float>* @20, align 1		; <<4 x float>>:21 [#uses=22]
+	load <4 x float>, <4 x float>* @21, align 1		; <<4 x float>>:22 [#uses=23]
+	load <4 x float>, <4 x float>* @22, align 1		; <<4 x float>>:23 [#uses=24]
+	load <4 x float>, <4 x float>* @23, align 1		; <<4 x float>>:24 [#uses=25]
+	load <4 x float>, <4 x float>* @24, align 1		; <<4 x float>>:25 [#uses=26]
+	load <4 x float>, <4 x float>* @25, align 1		; <<4 x float>>:26 [#uses=27]
+	load <4 x float>, <4 x float>* @26, align 1		; <<4 x float>>:27 [#uses=28]
+	load <4 x float>, <4 x float>* @27, align 1		; <<4 x float>>:28 [#uses=29]
+	load <4 x float>, <4 x float>* @28, align 1		; <<4 x float>>:29 [#uses=30]
+	load <4 x float>, <4 x float>* @29, align 1		; <<4 x float>>:30 [#uses=31]
+	load <4 x float>, <4 x float>* @30, align 1		; <<4 x float>>:31 [#uses=32]
+	load <4 x float>, <4 x float>* @31, align 1		; <<4 x float>>:32 [#uses=33]
 	fmul <4 x float> %1, %1		; <<4 x float>>:33 [#uses=1]
 	fmul <4 x float> %33, %2		; <<4 x float>>:34 [#uses=1]
 	fmul <4 x float> %34, %3		; <<4 x float>>:35 [#uses=1]
@@ -708,38 +708,38 @@ define void @test2() "no-realign-stack" {
 ; CHECK: movups
 ; CHECK: movups
 ; CHECK-NOT: movups
-	load <4 x float>* @0, align 1
-	load <4 x float>* @1, align 1
-	load <4 x float>* @2, align 1
-	load <4 x float>* @3, align 1
-	load <4 x float>* @4, align 1
-	load <4 x float>* @5, align 1
-	load <4 x float>* @6, align 1
-	load <4 x float>* @7, align 1
-	load <4 x float>* @8, align 1
-	load <4 x float>* @9, align 1
-	load <4 x float>* @10, align 1
-	load <4 x float>* @11, align 1
-	load <4 x float>* @12, align 1
-	load <4 x float>* @13, align 1
-	load <4 x float>* @14, align 1
-	load <4 x float>* @15, align 1
-	load <4 x float>* @16, align 1
-	load <4 x float>* @17, align 1
-	load <4 x float>* @18, align 1
-	load <4 x float>* @19, align 1
-	load <4 x float>* @20, align 1
-	load <4 x float>* @21, align 1
-	load <4 x float>* @22, align 1
-	load <4 x float>* @23, align 1
-	load <4 x float>* @24, align 1
-	load <4 x float>* @25, align 1
-	load <4 x float>* @26, align 1
-	load <4 x float>* @27, align 1
-	load <4 x float>* @28, align 1
-	load <4 x float>* @29, align 1
-	load <4 x float>* @30, align 1
-	load <4 x float>* @31, align 1
+	load <4 x float>, <4 x float>* @0, align 1
+	load <4 x float>, <4 x float>* @1, align 1
+	load <4 x float>, <4 x float>* @2, align 1
+	load <4 x float>, <4 x float>* @3, align 1
+	load <4 x float>, <4 x float>* @4, align 1
+	load <4 x float>, <4 x float>* @5, align 1
+	load <4 x float>, <4 x float>* @6, align 1
+	load <4 x float>, <4 x float>* @7, align 1
+	load <4 x float>, <4 x float>* @8, align 1
+	load <4 x float>, <4 x float>* @9, align 1
+	load <4 x float>, <4 x float>* @10, align 1
+	load <4 x float>, <4 x float>* @11, align 1
+	load <4 x float>, <4 x float>* @12, align 1
+	load <4 x float>, <4 x float>* @13, align 1
+	load <4 x float>, <4 x float>* @14, align 1
+	load <4 x float>, <4 x float>* @15, align 1
+	load <4 x float>, <4 x float>* @16, align 1
+	load <4 x float>, <4 x float>* @17, align 1
+	load <4 x float>, <4 x float>* @18, align 1
+	load <4 x float>, <4 x float>* @19, align 1
+	load <4 x float>, <4 x float>* @20, align 1
+	load <4 x float>, <4 x float>* @21, align 1
+	load <4 x float>, <4 x float>* @22, align 1
+	load <4 x float>, <4 x float>* @23, align 1
+	load <4 x float>, <4 x float>* @24, align 1
+	load <4 x float>, <4 x float>* @25, align 1
+	load <4 x float>, <4 x float>* @26, align 1
+	load <4 x float>, <4 x float>* @27, align 1
+	load <4 x float>, <4 x float>* @28, align 1
+	load <4 x float>, <4 x float>* @29, align 1
+	load <4 x float>, <4 x float>* @30, align 1
+	load <4 x float>, <4 x float>* @31, align 1
 	fmul <4 x float> %1, %1
 	fmul <4 x float> %33, %2
 	fmul <4 x float> %34, %3
diff --git a/test/CodeGen/X86/2008-07-22-CombinerCrash.ll b/test/CodeGen/X86/2008-07-22-CombinerCrash.ll
index 0f6714579bcc..35bb5f054282 100644
--- a/test/CodeGen/X86/2008-07-22-CombinerCrash.ll
+++ b/test/CodeGen/X86/2008-07-22-CombinerCrash.ll
@@ -7,7 +7,7 @@ external global <4 x i16>		; <<4 x i16>*>:1 [#uses=1]
 declare void @abort()
 
 define void @t() nounwind {
-	load i16* @0		; <i16>:1 [#uses=1]
+	load i16, i16* @0		; <i16>:1 [#uses=1]
 	zext i16 %1 to i64		; <i64>:2 [#uses=1]
 	bitcast i64 %2 to <4 x i16>		; <<4 x i16>>:3 [#uses=1]
 	shufflevector <4 x i16> %3, <4 x i16> undef, <4 x i32> zeroinitializer		; <<4 x i16>>:4 [#uses=1]
diff --git a/test/CodeGen/X86/2008-08-06-CmpStride.ll b/test/CodeGen/X86/2008-08-06-CmpStride.ll
index bdac8fd48422..a030fbeed513 100644
--- a/test/CodeGen/X86/2008-08-06-CmpStride.ll
+++ b/test/CodeGen/X86/2008-08-06-CmpStride.ll
@@ -13,7 +13,7 @@ forbody:
         %sub14 = sub i32 1027, %i.0             ; <i32> [#uses=1]
         %mul15 = mul i32 %sub14, 10             ; <i32> [#uses=1]
         %add166 = or i32 %mul15, 1              ; <i32> [#uses=1] *
-        call i32 (i8*, ...)* @printf( i8* noalias  getelementptr ([4 x i8]* @.str, i32 0, i32 0), i32 %add166 ) nounwind
+        call i32 (i8*, ...) @printf( i8* noalias  getelementptr ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %add166 ) nounwind
         %inc = add i32 %i.0, 1          ; <i32> [#uses=3]
         %cmp = icmp ne i32 %inc, 1027          ; <i1> [#uses=1]
         br i1 %cmp, label %forbody, label %afterfor
diff --git a/test/CodeGen/X86/2008-08-06-RewriterBug.ll b/test/CodeGen/X86/2008-08-06-RewriterBug.ll
index 4428035cc827..f9c5467713fc 100644
--- a/test/CodeGen/X86/2008-08-06-RewriterBug.ll
+++ b/test/CodeGen/X86/2008-08-06-RewriterBug.ll
@@ -4,14 +4,14 @@
 @data = external global [400 x i64]		; <[400 x i64]*> [#uses=5]
 
 define void @foo(double* noalias, double* noalias) {
-	load i64* getelementptr ([400 x i64]* @data, i32 0, i64 200), align 4		; <i64>:3 [#uses=1]
-	load i64* getelementptr ([400 x i64]* @data, i32 0, i64 199), align 4		; <i64>:4 [#uses=1]
-	load i64* getelementptr ([400 x i64]* @data, i32 0, i64 198), align 4		; <i64>:5 [#uses=2]
-	load i64* getelementptr ([400 x i64]* @data, i32 0, i64 197), align 4		; <i64>:6 [#uses=1]
+	load i64, i64* getelementptr ([400 x i64], [400 x i64]* @data, i32 0, i64 200), align 4		; <i64>:3 [#uses=1]
+	load i64, i64* getelementptr ([400 x i64], [400 x i64]* @data, i32 0, i64 199), align 4		; <i64>:4 [#uses=1]
+	load i64, i64* getelementptr ([400 x i64], [400 x i64]* @data, i32 0, i64 198), align 4		; <i64>:5 [#uses=2]
+	load i64, i64* getelementptr ([400 x i64], [400 x i64]* @data, i32 0, i64 197), align 4		; <i64>:6 [#uses=1]
 	br i1 false, label %28, label %7
 
 ; <label>:7		; preds = %2
-	load double** getelementptr (double** bitcast ([400 x i64]* @data to double**), i64 180), align 8		; <double*>:8 [#uses=1]
+	load double*, double** getelementptr (double*, double** bitcast ([400 x i64]* @data to double**), i64 180), align 8		; <double*>:8 [#uses=1]
 	bitcast double* %8 to double*		; <double*>:9 [#uses=1]
 	ptrtoint double* %9 to i64		; <i64>:10 [#uses=1]
 	mul i64 %4, %3		; <i64>:11 [#uses=1]
diff --git a/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll b/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll
index 51064f1d2173..291090263a2f 100644
--- a/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll
+++ b/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll
@@ -29,7 +29,7 @@ declare void @llvm.eh.unwind.init()
 ; CHECK: _Unwind_Resume_or_Rethrow
 define i32 @_Unwind_Resume_or_Rethrow() nounwind uwtable ssp {
 entry:
-  %0 = load i32* @b, align 4
+  %0 = load i32, i32* @b, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %if.end, label %if.then
 
@@ -37,7 +37,7 @@ if.then:                                          ; preds = %entry
   ret i32 0
 
 if.end:                                           ; preds = %entry
-  %call = tail call i32 (...)* @_Unwind_ForcedUnwind_Phase2() nounwind
+  %call = tail call i32 (...) @_Unwind_ForcedUnwind_Phase2() nounwind
   store i32 %call, i32* @a, align 4
   %tobool1 = icmp eq i32 %call, 0
   br i1 %tobool1, label %cond.end, label %cond.true
diff --git a/test/CodeGen/X86/2008-09-09-LinearScanBug.ll b/test/CodeGen/X86/2008-09-09-LinearScanBug.ll
index b3312d9464d1..9a1a3ddeae72 100644
--- a/test/CodeGen/X86/2008-09-09-LinearScanBug.ll
+++ b/test/CodeGen/X86/2008-09-09-LinearScanBug.ll
@@ -5,7 +5,7 @@
 
 define i32 @func_125(i32 %p_126, i32 %p_128, i32 %p_129) nounwind {
 entry:
-	%tmp2.i = load i32* @g_3		; <i32> [#uses=2]
+	%tmp2.i = load i32, i32* @g_3		; <i32> [#uses=2]
 	%conv = trunc i32 %tmp2.i to i16		; <i16> [#uses=3]
 	br label %forcond1.preheader.i.i7
 
@@ -58,7 +58,7 @@ ifend.i:		; preds = %lor_rhs.i
 safe_mod_int16_t_s_s.exit:		; preds = %ifend.i, %lor_rhs.i, %func_106.exit27
 	%call31 = phi i16 [ %conv8.i, %ifend.i ], [ %conv, %func_106.exit27 ], [ %conv, %lor_rhs.i ]		; <i16> [#uses=1]
 	%conv4 = sext i16 %call31 to i32		; <i32> [#uses=1]
-	%call5 = tail call i32 (...)* @func_104( i32 %conv4 )		; <i32> [#uses=0]
+	%call5 = tail call i32 (...) @func_104( i32 %conv4 )		; <i32> [#uses=0]
 	ret i32 undef
 }
 
diff --git a/test/CodeGen/X86/2008-09-11-CoalescerBug.ll b/test/CodeGen/X86/2008-09-11-CoalescerBug.ll
index 108f24307ea9..8c46bb3ec8b7 100644
--- a/test/CodeGen/X86/2008-09-11-CoalescerBug.ll
+++ b/test/CodeGen/X86/2008-09-11-CoalescerBug.ll
@@ -6,18 +6,18 @@
 define i32 @func_3(i32 %p_5) nounwind {
 entry:
 	%0 = srem i32 1, 0		; <i32> [#uses=2]
-	%1 = load i16* @g_15, align 2		; <i16> [#uses=1]
+	%1 = load i16, i16* @g_15, align 2		; <i16> [#uses=1]
 	%2 = zext i16 %1 to i32		; <i32> [#uses=1]
 	%3 = and i32 %2, 1		; <i32> [#uses=1]
-	%4 = tail call i32 (...)* @rshift_u_s( i32 1 ) nounwind		; <i32> [#uses=1]
+	%4 = tail call i32 (...) @rshift_u_s( i32 1 ) nounwind		; <i32> [#uses=1]
 	%5 = icmp slt i32 %4, 2		; <i1> [#uses=1]
 	%6 = zext i1 %5 to i32		; <i32> [#uses=1]
 	%7 = icmp sge i32 %3, %6		; <i1> [#uses=1]
 	%8 = zext i1 %7 to i32		; <i32> [#uses=1]
-	%9 = load i16* @g_15, align 2		; <i16> [#uses=1]
+	%9 = load i16, i16* @g_15, align 2		; <i16> [#uses=1]
 	%10 = icmp eq i16 %9, 0		; <i1> [#uses=1]
 	%11 = zext i1 %10 to i32		; <i32> [#uses=1]
-	%12 = tail call i32 (...)* @func_20( i32 1 ) nounwind		; <i32> [#uses=1]
+	%12 = tail call i32 (...) @func_20( i32 1 ) nounwind		; <i32> [#uses=1]
 	%13 = icmp sge i32 %11, %12		; <i1> [#uses=1]
 	%14 = zext i1 %13 to i32		; <i32> [#uses=1]
 	%15 = sub i32 %8, %14		; <i32> [#uses=1]
@@ -27,7 +27,7 @@ entry:
 	%or.cond = or i1 false, %18		; <i1> [#uses=1]
 	%19 = select i1 %or.cond, i32 0, i32 %0		; <i32> [#uses=1]
 	%.0 = lshr i32 %17, %19		; <i32> [#uses=1]
-	%20 = tail call i32 (...)* @func_7( i32 %.0 ) nounwind		; <i32> [#uses=0]
+	%20 = tail call i32 (...) @func_7( i32 %.0 ) nounwind		; <i32> [#uses=0]
 	ret i32 undef
 }
 
diff --git a/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll b/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
index 59d1c7f77abf..757dff4230fc 100644
--- a/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
+++ b/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
@@ -18,11 +18,11 @@ entry:
 ; SOURCE-SCHED: subl
 ; SOURCE-SCHED: testb
 ; SOURCE-SCHED: jne
-	%0 = load i32* @g_5, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* @g_5, align 4		; <i32> [#uses=1]
 	%1 = ashr i32 %0, 1		; <i32> [#uses=1]
 	%2 = icmp sgt i32 %1, 1		; <i1> [#uses=1]
 	%3 = zext i1 %2 to i32		; <i32> [#uses=1]
-	%4 = load i32* @g_73, align 4		; <i32> [#uses=1]
+	%4 = load i32, i32* @g_73, align 4		; <i32> [#uses=1]
 	%5 = zext i16 %p_46 to i64		; <i64> [#uses=1]
 	%6 = sub i64 0, %5		; <i64> [#uses=1]
 	%7 = trunc i64 %6 to i8		; <i8> [#uses=2]
@@ -38,7 +38,7 @@ bb12:		; preds = %bb11, %entry
 	%.014.in = phi i8 [ %10, %bb11 ], [ %7, %entry ]		; <i8> [#uses=1]
 	%11 = icmp ne i8 %.014.in, 0		; <i1> [#uses=1]
 	%12 = zext i1 %11 to i32		; <i32> [#uses=1]
-	%13 = tail call i32 (...)* @func_48( i32 %12, i32 %3, i32 0 ) nounwind		; <i32> [#uses=0]
+	%13 = tail call i32 (...) @func_48( i32 %12, i32 %3, i32 0 ) nounwind		; <i32> [#uses=0]
 	ret i32 undef
 }
 
diff --git a/test/CodeGen/X86/2008-09-17-inline-asm-1.ll b/test/CodeGen/X86/2008-09-17-inline-asm-1.ll
index 4b2774b64b7b..3edd72bdba90 100644
--- a/test/CodeGen/X86/2008-09-17-inline-asm-1.ll
+++ b/test/CodeGen/X86/2008-09-17-inline-asm-1.ll
@@ -19,7 +19,7 @@ target triple = "i386-apple-darwin8"
 
 define i32 @aci(i32* %pw) nounwind {
 entry:
-	%0 = load i32* @x, align 4
+	%0 = load i32, i32* @x, align 4
 	%asmtmp = tail call { i32, i32 } asm "movl $0, %eax\0A\090:\0A\09test %eax, %eax\0A\09je 1f\0A\09movl %eax, $2\0A\09incl $2\0A\09lock\0A\09cmpxchgl $2, $0\0A\09jne 0b\0A\091:", "=*m,=&{ax},=&r,*m,~{dirflag},~{fpsr},~{flags},~{memory},~{cc}"(i32* %pw, i32* %pw) nounwind
 	%asmtmp2 = tail call { i32, i32 } asm "movl $0, %edx\0A\090:\0A\09test %edx, %edx\0A\09je 1f\0A\09movl %edx, $2\0A\09incl $2\0A\09lock\0A\09cmpxchgl $2, $0\0A\09jne 0b\0A\091:", "=*m,=&{dx},=&r,*m,~{dirflag},~{fpsr},~{flags},~{memory},~{cc}"(i32* %pw, i32* %pw) nounwind
 	%asmresult2 = extractvalue { i32, i32 } %asmtmp, 0
diff --git a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
index f4a43a1e978a..0058d979a2fa 100644
--- a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
+++ b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
@@ -32,12 +32,12 @@ target triple = "i386-apple-darwin8"
 
 define i32 @get(%struct.foo* %c, i8* %state) nounwind {
 entry:
-	%0 = getelementptr %struct.foo* %c, i32 0, i32 0		; <i32*> [#uses=2]
-	%1 = getelementptr %struct.foo* %c, i32 0, i32 1		; <i32*> [#uses=2]
-	%2 = getelementptr %struct.foo* %c, i32 0, i32 2		; <i8**> [#uses=2]
-	%3 = load i32* %0, align 4		; <i32> [#uses=1]
-	%4 = load i32* %1, align 4		; <i32> [#uses=1]
-	%5 = load i8* %state, align 1		; <i8> [#uses=1]
+	%0 = getelementptr %struct.foo, %struct.foo* %c, i32 0, i32 0		; <i32*> [#uses=2]
+	%1 = getelementptr %struct.foo, %struct.foo* %c, i32 0, i32 1		; <i32*> [#uses=2]
+	%2 = getelementptr %struct.foo, %struct.foo* %c, i32 0, i32 2		; <i8**> [#uses=2]
+	%3 = load i32, i32* %0, align 4		; <i32> [#uses=1]
+	%4 = load i32, i32* %1, align 4		; <i32> [#uses=1]
+	%5 = load i8, i8* %state, align 1		; <i8> [#uses=1]
 	%asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#1st=$0 $1 2nd=$1 $2 3rd=$2 $4 5th=$4 $3=4th 1$0 1%eXx 5$4 5%eXx 6th=$5", "=&r,=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %2, i8* %state, i32 %3, i32 %4, i8** %2, i8 %5) nounwind		; <{ i32, i32, i32, i32 }> [#uses=3]
 	%asmresult = extractvalue { i32, i32, i32, i32 } %asmtmp, 0		; <i32> [#uses=1]
 	%asmresult1 = extractvalue { i32, i32, i32, i32 } %asmtmp, 1		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2008-09-19-RegAllocBug.ll b/test/CodeGen/X86/2008-09-19-RegAllocBug.ll
index a8f2912a70af..83a1fac7f3ab 100644
--- a/test/CodeGen/X86/2008-09-19-RegAllocBug.ll
+++ b/test/CodeGen/X86/2008-09-19-RegAllocBug.ll
@@ -5,7 +5,7 @@
 
 define i32 @func_4() nounwind {
 entry:
-	%0 = load i32* @g_3, align 4		; <i32> [#uses=2]
+	%0 = load i32, i32* @g_3, align 4		; <i32> [#uses=2]
 	%1 = trunc i32 %0 to i8		; <i8> [#uses=1]
 	%2 = sub i8 1, %1		; <i8> [#uses=1]
 	%3 = sext i8 %2 to i32		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2008-09-29-ReMatBug.ll b/test/CodeGen/X86/2008-09-29-ReMatBug.ll
index c36cf39fb341..754fd8f0ab64 100644
--- a/test/CodeGen/X86/2008-09-29-ReMatBug.ll
+++ b/test/CodeGen/X86/2008-09-29-ReMatBug.ll
@@ -5,7 +5,7 @@
 	%struct.XCStringList = type { i32, %struct._XCStringListNode* }
 	%struct._XCStringListNode = type { [3 x i8], [0 x i8], i8 }
 	%struct.__builtin_CFString = type { i32*, i32, i8*, i32 }
-internal constant %struct.__builtin_CFString { i32* getelementptr ([0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr ([3 x i8]* @"\01LC", i32 0, i32 0), i32 2 }		; <%struct.__builtin_CFString*>:0 [#uses=1]
+internal constant %struct.__builtin_CFString { i32* getelementptr ([0 x i32], [0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr ([3 x i8], [3 x i8]* @"\01LC", i32 0, i32 0), i32 2 }		; <%struct.__builtin_CFString*>:0 [#uses=1]
 @__CFConstantStringClassReference = external global [0 x i32]		; <[0 x i32]*> [#uses=1]
 @"\01LC" = internal constant [3 x i8] c"NO\00"		; <[3 x i8]*> [#uses=1]
 @"\01LC1" = internal constant [1 x i8] zeroinitializer		; <[1 x i8]*> [#uses=1]
@@ -13,13 +13,13 @@ internal constant %struct.__builtin_CFString { i32* getelementptr ([0 x i32]* @_
 
 define %struct.NSString* @"-[XCStringList stringRepresentation]"(%struct.XCStringList* %self, %struct..0objc_selector* %_cmd) nounwind {
 entry:
-	%0 = load i32* null, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	%1 = and i32 %0, 16777215		; <i32> [#uses=1]
 	%2 = icmp eq i32 %1, 0		; <i1> [#uses=1]
 	br i1 %2, label %bb44, label %bb4
 
 bb4:		; preds = %entry
-	%3 = load %struct._XCStringListNode** null, align 4		; <%struct._XCStringListNode*> [#uses=2]
+	%3 = load %struct._XCStringListNode*, %struct._XCStringListNode** null, align 4		; <%struct._XCStringListNode*> [#uses=2]
 	%4 = icmp eq %struct._XCStringListNode* %3, null		; <i1> [#uses=1]
 	%5 = bitcast %struct._XCStringListNode* %3 to i32*		; <i32*> [#uses=1]
 	br label %bb37.outer
@@ -35,11 +35,11 @@ bb19:		; preds = %bb37, %bb6
 	br i1 %7, label %bb25.split, label %bb37
 
 bb25.split:		; preds = %bb19
-	call void @foo(i8* getelementptr ([1 x i8]* @"\01LC1", i32 0, i32 0)) nounwind nounwind
+	call void @foo(i8* getelementptr ([1 x i8], [1 x i8]* @"\01LC1", i32 0, i32 0)) nounwind nounwind
 	br label %bb35.outer
 
 bb34:		; preds = %bb35, %bb35, %bb35, %bb35
-	%8 = getelementptr i8* %bufptr.0.lcssa, i32 %totalLength.0.ph		; <i8*> [#uses=1]
+	%8 = getelementptr i8, i8* %bufptr.0.lcssa, i32 %totalLength.0.ph		; <i8*> [#uses=1]
 	store i8 92, i8* %8, align 1
 	br label %bb35.outer
 
@@ -48,7 +48,7 @@ bb35.outer:		; preds = %bb34, %bb25.split
 	br label %bb35
 
 bb35:		; preds = %bb35, %bb35.outer
-	%9 = load i8* null, align 1		; <i8> [#uses=1]
+	%9 = load i8, i8* null, align 1		; <i8> [#uses=1]
 	switch i8 %9, label %bb35 [
 		i8 0, label %bb37.outer
 		i8 32, label %bb34
@@ -63,7 +63,7 @@ bb37.outer:		; preds = %bb35, %bb4
 	br i1 %4, label %bb39.split, label %bb37
 
 bb37:		; preds = %bb37.outer, %bb19
-	%10 = load i32* %5, align 4		; <i32> [#uses=1]
+	%10 = load i32, i32* %5, align 4		; <i32> [#uses=1]
 	br i1 false, label %bb6, label %bb19
 
 bb39.split:		; preds = %bb37.outer
diff --git a/test/CodeGen/X86/2008-09-29-VolatileBug.ll b/test/CodeGen/X86/2008-09-29-VolatileBug.ll
index f35245bb2af7..6ee8cf2f5e33 100644
--- a/test/CodeGen/X86/2008-09-29-VolatileBug.ll
+++ b/test/CodeGen/X86/2008-09-29-VolatileBug.ll
@@ -6,7 +6,7 @@
 
 define i32 @main() nounwind {
 entry:
-	%0 = load volatile i32* @g_407, align 4		; <i32> [#uses=1]
+	%0 = load volatile i32, i32* @g_407, align 4		; <i32> [#uses=1]
 	%1 = trunc i32 %0 to i8		; <i8> [#uses=1]
 	%2 = tail call i32 @func_45(i8 zeroext %1) nounwind		; <i32> [#uses=0]
 	ret i32 0
diff --git a/test/CodeGen/X86/2008-10-06-MMXISelBug.ll b/test/CodeGen/X86/2008-10-06-MMXISelBug.ll
deleted file mode 100644
index 7f7b1a436d24..000000000000
--- a/test/CodeGen/X86/2008-10-06-MMXISelBug.ll
+++ /dev/null
@@ -1,12 +0,0 @@
-; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2
-; PR2850
-
-@tmp_V2i = common global <2 x i32> zeroinitializer		; <<2 x i32>*> [#uses=2]
-
-define void @f0() nounwind {
-entry:
-	%0 = load <2 x i32>* @tmp_V2i, align 8		; <<2 x i32>> [#uses=1]
-	%1 = shufflevector <2 x i32> %0, <2 x i32> undef, <2 x i32> zeroinitializer		; <<2 x i32>> [#uses=1]
-	store <2 x i32> %1, <2 x i32>* @tmp_V2i, align 8
-	ret void
-}
diff --git a/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll b/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll
index bd48105f129a..34c9857b00ea 100644
--- a/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll
+++ b/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll
@@ -10,7 +10,7 @@ declare x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 %f)
 
 define i32 @main() {
 entry_nan.main:
-  %tmp = load x86_fp80* @_D3nan4rvale   ; <x86_fp80> [#uses=1]
+  %tmp = load x86_fp80, x86_fp80* @_D3nan4rvale   ; <x86_fp80> [#uses=1]
   call x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 %tmp)
   call x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 0xK7FFF8001234000000000)
   call x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 0xK7FFFC001234000000400)
diff --git a/test/CodeGen/X86/2008-10-07-SSEISelBug.ll b/test/CodeGen/X86/2008-10-07-SSEISelBug.ll
index bc5761288c9b..26e802ac05f9 100644
--- a/test/CodeGen/X86/2008-10-07-SSEISelBug.ll
+++ b/test/CodeGen/X86/2008-10-07-SSEISelBug.ll
@@ -6,17 +6,17 @@ entry:
 	%w.addr = alloca float		; <float*> [#uses=2]
 	%.compoundliteral = alloca <4 x float>		; <<4 x float>*> [#uses=2]
 	store float %w, float* %w.addr
-	%tmp = load float* %w.addr		; <float> [#uses=1]
+	%tmp = load float, float* %w.addr		; <float> [#uses=1]
 	%0 = insertelement <4 x float> undef, float %tmp, i32 0		; <<4 x float>> [#uses=1]
 	%1 = insertelement <4 x float> %0, float 0.000000e+00, i32 1		; <<4 x float>> [#uses=1]
 	%2 = insertelement <4 x float> %1, float 0.000000e+00, i32 2		; <<4 x float>> [#uses=1]
 	%3 = insertelement <4 x float> %2, float 0.000000e+00, i32 3		; <<4 x float>> [#uses=1]
 	store <4 x float> %3, <4 x float>* %.compoundliteral
-	%tmp1 = load <4 x float>* %.compoundliteral		; <<4 x float>> [#uses=1]
+	%tmp1 = load <4 x float>, <4 x float>* %.compoundliteral		; <<4 x float>> [#uses=1]
 	store <4 x float> %tmp1, <4 x float>* %retval
 	br label %return
 
 return:		; preds = %entry
-	%4 = load <4 x float>* %retval		; <<4 x float>> [#uses=1]
+	%4 = load <4 x float>, <4 x float>* %retval		; <<4 x float>> [#uses=1]
 	ret <4 x float> %4
 }
diff --git a/test/CodeGen/X86/2008-10-11-CallCrash.ll b/test/CodeGen/X86/2008-10-11-CallCrash.ll
index efc6125cfc2d..9ad7ab268ad2 100644
--- a/test/CodeGen/X86/2008-10-11-CallCrash.ll
+++ b/test/CodeGen/X86/2008-10-11-CallCrash.ll
@@ -6,13 +6,13 @@ target triple = "i386-apple-darwin7"
 
 define i32 @func_45(i64 %p_46, i32 %p_48) nounwind {
 entry:
-	%0 = tail call i32 (...)* @lshift_s_u(i64 %p_46, i64 0) nounwind		; <i32> [#uses=0]
-	%1 = load i32* @g_385, align 4		; <i32> [#uses=1]
+	%0 = tail call i32 (...) @lshift_s_u(i64 %p_46, i64 0) nounwind		; <i32> [#uses=0]
+	%1 = load i32, i32* @g_385, align 4		; <i32> [#uses=1]
 	%2 = shl i32 %1, 1		; <i32> [#uses=1]
 	%3 = and i32 %2, 32		; <i32> [#uses=1]
-	%4 = tail call i32 (...)* @func_87(i32 undef, i32 %p_48, i32 1) nounwind		; <i32> [#uses=1]
+	%4 = tail call i32 (...) @func_87(i32 undef, i32 %p_48, i32 1) nounwind		; <i32> [#uses=1]
 	%5 = add i32 %3, %4		; <i32> [#uses=1]
-	%6 = tail call i32 (...)* @div_rhs(i32 %5) nounwind		; <i32> [#uses=0]
+	%6 = tail call i32 (...) @div_rhs(i32 %5) nounwind		; <i32> [#uses=0]
 	ret i32 undef
 }
 
diff --git a/test/CodeGen/X86/2008-10-13-CoalescerBug.ll b/test/CodeGen/X86/2008-10-13-CoalescerBug.ll
index 4d3f8c2071b5..c285ae4fdd28 100644
--- a/test/CodeGen/X86/2008-10-13-CoalescerBug.ll
+++ b/test/CodeGen/X86/2008-10-13-CoalescerBug.ll
@@ -3,7 +3,7 @@
 
 define i32 @func_77(i8 zeroext %p_79) nounwind {
 entry:
-	%0 = tail call i32 (...)* @func_43(i32 1) nounwind		; <i32> [#uses=1]
+	%0 = tail call i32 (...) @func_43(i32 1) nounwind		; <i32> [#uses=1]
 	%1 = icmp eq i32 %0, 0		; <i1> [#uses=1]
 	br i1 %1, label %bb3, label %bb
 
@@ -14,7 +14,7 @@ bb3:		; preds = %bb, %entry
 	%p_79_addr.0 = phi i8 [ 0, %bb ], [ %p_79, %entry ]		; <i8> [#uses=1]
 	%2 = zext i8 %p_79_addr.0 to i32		; <i32> [#uses=2]
 	%3 = zext i1 false to i32		; <i32> [#uses=2]
-	%4 = tail call i32 (...)* @rshift_u_s(i32 1) nounwind		; <i32> [#uses=0]
+	%4 = tail call i32 (...) @rshift_u_s(i32 1) nounwind		; <i32> [#uses=0]
 	%5 = lshr i32 %2, %2		; <i32> [#uses=3]
 	%6 = icmp eq i32 0, 0		; <i1> [#uses=1]
 	br i1 %6, label %bb6, label %bb9
diff --git a/test/CodeGen/X86/2008-10-16-VecUnaryOp.ll b/test/CodeGen/X86/2008-10-16-VecUnaryOp.ll
index de4c1e70b8d8..ac6fa0dc9b26 100644
--- a/test/CodeGen/X86/2008-10-16-VecUnaryOp.ll
+++ b/test/CodeGen/X86/2008-10-16-VecUnaryOp.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse2
 ; PR2762
 define void @foo(<4 x i32>* %p, <4 x double>* %q) {
-  %n = load <4 x i32>* %p
+  %n = load <4 x i32>, <4 x i32>* %p
   %z = sitofp <4 x i32> %n to <4 x double>
   store <4 x double> %z, <4 x double>* %q
   ret void
diff --git a/test/CodeGen/X86/2008-10-27-CoalescerBug.ll b/test/CodeGen/X86/2008-10-27-CoalescerBug.ll
index 0310a5dcb565..b1dcd031265b 100644
--- a/test/CodeGen/X86/2008-10-27-CoalescerBug.ll
+++ b/test/CodeGen/X86/2008-10-27-CoalescerBug.ll
@@ -20,7 +20,7 @@ bb:		; preds = %bb, %entry
 ; CHECK: movsd %xmm0, 16(%esp)
 ; CHECK: %bb3
 bb3:		; preds = %bb30.loopexit, %bb25, %bb3
-	%2 = load i32* null, align 4		; <i32> [#uses=1]
+	%2 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	%3 = mul i32 %2, 0		; <i32> [#uses=1]
 	%4 = icmp slt i32 0, %3		; <i1> [#uses=1]
 	br i1 %4, label %bb18, label %bb3
diff --git a/test/CodeGen/X86/2008-11-06-testb.ll b/test/CodeGen/X86/2008-11-06-testb.ll
index e7caa7a10670..c8fad0635828 100644
--- a/test/CodeGen/X86/2008-11-06-testb.ll
+++ b/test/CodeGen/X86/2008-11-06-testb.ll
@@ -9,16 +9,16 @@ target triple = "i386-apple-darwin9.5"
 
 define i32 @foo(%struct.x* %p) nounwind {
 entry:
-	%0 = getelementptr %struct.x* %p, i32 0, i32 0		; <i8*> [#uses=1]
+	%0 = getelementptr %struct.x, %struct.x* %p, i32 0, i32 0		; <i8*> [#uses=1]
 	store i8 55, i8* %0, align 1
 	%1 = bitcast %struct.x* %p to i32*		; <i32*> [#uses=1]
-	%2 = load i32* %1, align 1		; <i32> [#uses=1]
+	%2 = load i32, i32* %1, align 1		; <i32> [#uses=1]
 	%3 = and i32 %2, 512		; <i32> [#uses=1]
 	%4 = icmp eq i32 %3, 0		; <i1> [#uses=1]
 	br i1 %4, label %bb5, label %bb
 
 bb:		; preds = %entry
-	%5 = tail call i32 (...)* @xx() nounwind		; <i32> [#uses=1]
+	%5 = tail call i32 (...) @xx() nounwind		; <i32> [#uses=1]
 	ret i32 %5
 
 bb5:		; preds = %entry
diff --git a/test/CodeGen/X86/2008-11-29-ULT-Sign.ll b/test/CodeGen/X86/2008-11-29-ULT-Sign.ll
index 6dca141639e4..03442d631ac7 100644
--- a/test/CodeGen/X86/2008-11-29-ULT-Sign.ll
+++ b/test/CodeGen/X86/2008-11-29-ULT-Sign.ll
@@ -8,7 +8,7 @@ entry:
 	br i1 %cmp, label %if.end, label %if.then
 
 if.then:		; preds = %entry
-	%call = call i32 (...)* @b()		; <i32> [#uses=0]
+	%call = call i32 (...) @b()		; <i32> [#uses=0]
 	br label %if.end
 
 if.end:		; preds = %if.then, %entry
diff --git a/test/CodeGen/X86/2008-12-01-SpillerAssert.ll b/test/CodeGen/X86/2008-12-01-SpillerAssert.ll
index d96d806388c9..cf292e3c0c52 100644
--- a/test/CodeGen/X86/2008-12-01-SpillerAssert.ll
+++ b/test/CodeGen/X86/2008-12-01-SpillerAssert.ll
@@ -10,6 +10,6 @@ declare i32 @printk(i8*, ...)
 define void @display_cacheinfo(%struct.cpuinfo_x86* %c) nounwind section ".cpuinit.text" {
 entry:
         %asmtmp = tail call { i32, i32, i32, i32 } asm "cpuid", "={ax},={bx},={cx},={dx},0,2,~{dirflag},~{fpsr},~{flags}"(i32 -2147483643, i32 0) nounwind          ; <{ i32, i32, i32, i32 }> [#uses=0]
-        %0 = tail call i32 (i8*, ...)* @printk(i8* getelementptr ([70 x i8]* @.str10, i32 0, i64 0), i32 0, i32 0, i32 0, i32 0) nounwind           ; <i32> [#uses=0]
+        %0 = tail call i32 (i8*, ...) @printk(i8* getelementptr ([70 x i8], [70 x i8]* @.str10, i32 0, i64 0), i32 0, i32 0, i32 0, i32 0) nounwind           ; <i32> [#uses=0]
         unreachable
 }
diff --git a/test/CodeGen/X86/2008-12-01-loop-iv-used-outside-loop.ll b/test/CodeGen/X86/2008-12-01-loop-iv-used-outside-loop.ll
index 1f8bd45da14d..840b8ba0f8ce 100644
--- a/test/CodeGen/X86/2008-12-01-loop-iv-used-outside-loop.ll
+++ b/test/CodeGen/X86/2008-12-01-loop-iv-used-outside-loop.ll
@@ -15,8 +15,8 @@ bb:		; preds = %bb1, %bb1
 
 bb1:		; preds = %bb, %entry
 	%P.0.rec = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]		; <i32> [#uses=3]
-	%P.0 = getelementptr i8* %Q, i32 %P.0.rec		; <i8*> [#uses=2]
-	%0 = load i8* %P.0, align 1		; <i8> [#uses=1]
+	%P.0 = getelementptr i8, i8* %Q, i32 %P.0.rec		; <i8*> [#uses=2]
+	%0 = load i8, i8* %P.0, align 1		; <i8> [#uses=1]
 	switch i8 %0, label %bb3 [
 		i8 12, label %bb
 		i8 42, label %bb
@@ -24,7 +24,7 @@ bb1:		; preds = %bb, %entry
 
 bb3:		; preds = %bb1
 	%P.0.sum = add i32 %P.0.rec, 2		; <i32> [#uses=1]
-	%1 = getelementptr i8* %Q, i32 %P.0.sum		; <i8*> [#uses=1]
+	%1 = getelementptr i8, i8* %Q, i32 %P.0.sum		; <i8*> [#uses=1]
 	store i8 4, i8* %1, align 1
 	ret i8* %P.0
 }
diff --git a/test/CodeGen/X86/2008-12-02-IllegalResultType.ll b/test/CodeGen/X86/2008-12-02-IllegalResultType.ll
index 4b72cb919ffa..c828879e6b99 100644
--- a/test/CodeGen/X86/2008-12-02-IllegalResultType.ll
+++ b/test/CodeGen/X86/2008-12-02-IllegalResultType.ll
@@ -7,7 +7,7 @@ target triple = "i386-pc-linux-gnu"
 
 define i32 @func_73(i32 %p_74) nounwind {
 entry:
-	%0 = load i32* @g_7, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* @g_7, align 4		; <i32> [#uses=1]
 	%1 = or i8 0, 118		; <i8> [#uses=1]
 	%2 = zext i8 %1 to i64		; <i64> [#uses=1]
 	%3 = icmp ne i32 %0, 0		; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/2008-12-02-dagcombine-1.ll b/test/CodeGen/X86/2008-12-02-dagcombine-1.ll
index fe5bff3e3459..004adc08091e 100644
--- a/test/CodeGen/X86/2008-12-02-dagcombine-1.ll
+++ b/test/CodeGen/X86/2008-12-02-dagcombine-1.ll
@@ -11,7 +11,7 @@ entry:
         %4 = ptrtoint i8* %L to i32
         %5 = add i32 %4, %3
 	%6 = add i32 %5, %1         	; <i32> [#uses=1]
-	%7 = getelementptr i8* %a, i32 %6		; <i8*> [#uses=1]
+	%7 = getelementptr i8, i8* %a, i32 %6		; <i8*> [#uses=1]
 	br label %return
 
 return:		; preds = %bb3
diff --git a/test/CodeGen/X86/2008-12-02-dagcombine-2.ll b/test/CodeGen/X86/2008-12-02-dagcombine-2.ll
index 4cb1b42693b9..6622bc26692b 100644
--- a/test/CodeGen/X86/2008-12-02-dagcombine-2.ll
+++ b/test/CodeGen/X86/2008-12-02-dagcombine-2.ll
@@ -9,7 +9,7 @@ entry:
         %2 = sub i32 %1, %0
         %3 = ptrtoint i8* %L to i32
 	%4 = sub i32 %2, %3         	; <i32> [#uses=1]
-	%5 = getelementptr i8* %a, i32 %4		; <i8*> [#uses=1]
+	%5 = getelementptr i8, i8* %a, i32 %4		; <i8*> [#uses=1]
 	br label %return
 
 return:		; preds = %bb3
diff --git a/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll
index 435adbbebfad..6bb29fde8454 100644
--- a/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll
+++ b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll
@@ -16,7 +16,7 @@ entry:
 	%1 = trunc i64 %u to i32		; <i32> [#uses=4]
 	%2 = lshr i64 %u, 32		; <i64> [#uses=1]
 	%3 = trunc i64 %2 to i32		; <i32> [#uses=2]
-	%4 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([7 x i8]* @"\01LC", i32 0, i32 0), i32 %1) nounwind		; <i32> [#uses=0]
+	%4 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([7 x i8], [7 x i8]* @"\01LC", i32 0, i32 0), i32 %1) nounwind		; <i32> [#uses=0]
 	%5 = icmp ult i32 %1, %0		; <i1> [#uses=1]
 	br i1 %5, label %bb2, label %bb
 
diff --git a/test/CodeGen/X86/2008-12-23-crazy-address.ll b/test/CodeGen/X86/2008-12-23-crazy-address.ll
index 0e95c9e34e1c..b80f4731f8ab 100644
--- a/test/CodeGen/X86/2008-12-23-crazy-address.ll
+++ b/test/CodeGen/X86/2008-12-23-crazy-address.ll
@@ -7,7 +7,7 @@ entry:
 	%Y = alloca i32
 	call void @frob(i32* %Y) nounwind
 	%Y3 = bitcast i32* %Y to i8*
-	%ctg2 = getelementptr i8* %Y3, i32 ptrtoint ([0 x i32]* @X to i32)
+	%ctg2 = getelementptr i8, i8* %Y3, i32 ptrtoint ([0 x i32]* @X to i32)
 	%0 = ptrtoint i8* %ctg2 to i32
 	call void @borf(i32 %0) nounwind
 	ret void
@@ -16,13 +16,13 @@ entry:
 define void @bar(i32 %i) nounwind {
 entry:
 	%Y = alloca [10 x i32]
-	%0 = getelementptr [10 x i32]* %Y, i32 0, i32 0
+	%0 = getelementptr [10 x i32], [10 x i32]* %Y, i32 0, i32 0
 	call void @frob(i32* %0) nounwind
-	%1 = getelementptr [0 x i32]* @X, i32 0, i32 %i
-	%2 = getelementptr [10 x i32]* %Y, i32 0, i32 0
+	%1 = getelementptr [0 x i32], [0 x i32]* @X, i32 0, i32 %i
+	%2 = getelementptr [10 x i32], [10 x i32]* %Y, i32 0, i32 0
 	%3 = ptrtoint i32* %2 to i32
 	%4 = bitcast i32* %1 to i8*
-	%ctg2 = getelementptr i8* %4, i32 %3
+	%ctg2 = getelementptr i8, i8* %4, i32 %3
 	%5 = ptrtoint i8* %ctg2 to i32
 	call void @borf(i32 %5) nounwind
 	ret void
diff --git a/test/CodeGen/X86/2009-01-16-SchedulerBug.ll b/test/CodeGen/X86/2009-01-16-SchedulerBug.ll
index 99bef6ce3fc9..ac6d0a983e44 100644
--- a/test/CodeGen/X86/2009-01-16-SchedulerBug.ll
+++ b/test/CodeGen/X86/2009-01-16-SchedulerBug.ll
@@ -10,12 +10,12 @@ declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) nounwind
 
 define fastcc %XXV* @bar(%CF* %call_frame, %XXV** %exception) nounwind {
 prologue:
-	%param_x = load %XXV** null		; <%XXV*> [#uses=1]
+	%param_x = load %XXV*, %XXV** null		; <%XXV*> [#uses=1]
 	%unique_1.i = ptrtoint %XXV* %param_x to i1		; <i1> [#uses=1]
 	br i1 %unique_1.i, label %NextVerify42, label %FailedVerify
 
 NextVerify42:		; preds = %prologue
-	%param_y = load %XXV** null		; <%XXV*> [#uses=1]
+	%param_y = load %XXV*, %XXV** null		; <%XXV*> [#uses=1]
 	%unique_1.i58 = ptrtoint %XXV* %param_y to i1		; <i1> [#uses=1]
 	br i1 %unique_1.i58, label %function_setup.cont, label %FailedVerify
 
diff --git a/test/CodeGen/X86/2009-01-18-ConstantExprCrash.ll b/test/CodeGen/X86/2009-01-18-ConstantExprCrash.ll
index f895336491e2..9a4e6eeae189 100644
--- a/test/CodeGen/X86/2009-01-18-ConstantExprCrash.ll
+++ b/test/CodeGen/X86/2009-01-18-ConstantExprCrash.ll
@@ -25,7 +25,7 @@ bb4.i.i70:		; preds = %bb4.i.i70, %bb.i51
 	br i1 false, label %_ZN11xercesc_2_59XMLString9stringLenEPKt.exit.i73, label %bb4.i.i70
 
 _ZN11xercesc_2_59XMLString9stringLenEPKt.exit.i73:		; preds = %bb4.i.i70
-	%0 = load i16* getelementptr ([7 x i16]* @_ZN11xercesc_2_5L17gIdeographicCharsE, i32 0, i32 add (i32 ashr (i32 sub (i32 ptrtoint (i16* getelementptr ([7 x i16]* @_ZN11xercesc_2_5L17gIdeographicCharsE, i32 0, i32 4) to i32), i32 ptrtoint ([7 x i16]* @_ZN11xercesc_2_5L17gIdeographicCharsE to i32)), i32 1), i32 1)), align 4		; <i16> [#uses=0]
+	%0 = load i16, i16* getelementptr ([7 x i16], [7 x i16]* @_ZN11xercesc_2_5L17gIdeographicCharsE, i32 0, i32 add (i32 ashr (i32 sub (i32 ptrtoint (i16* getelementptr ([7 x i16], [7 x i16]* @_ZN11xercesc_2_5L17gIdeographicCharsE, i32 0, i32 4) to i32), i32 ptrtoint ([7 x i16]* @_ZN11xercesc_2_5L17gIdeographicCharsE to i32)), i32 1), i32 1)), align 4		; <i16> [#uses=0]
 	br label %bb4.i5.i141
 
 bb4.i5.i141:		; preds = %bb4.i5.i141, %_ZN11xercesc_2_59XMLString9stringLenEPKt.exit.i73
diff --git a/test/CodeGen/X86/2009-01-25-NoSSE.ll b/test/CodeGen/X86/2009-01-25-NoSSE.ll
index 8406c4a2cc83..c655f2c374ac 100644
--- a/test/CodeGen/X86/2009-01-25-NoSSE.ll
+++ b/test/CodeGen/X86/2009-01-25-NoSSE.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mattr=-sse,-sse2 | not grep xmm
+; RUN: llc < %s -march=x86-64 -mattr=-sse,-sse2 | FileCheck %s
 ; PR3402
 target datalayout =
 "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
@@ -6,6 +6,8 @@ target triple = "x86_64-unknown-linux-gnu"
 
 %struct.ktermios = type { i32, i32, i32, i32, i8, [19 x i8], i32, i32 }
 
+; CHECK-NOT: xmm
+; CHECK-NOT: ymm
 define void @foo() nounwind {
 entry:
   %termios = alloca %struct.ktermios, align 8
diff --git a/test/CodeGen/X86/2009-01-31-BigShift2.ll b/test/CodeGen/X86/2009-01-31-BigShift2.ll
index b478f27a95b9..90d14e7b707d 100644
--- a/test/CodeGen/X86/2009-01-31-BigShift2.ll
+++ b/test/CodeGen/X86/2009-01-31-BigShift2.ll
@@ -2,7 +2,7 @@
 ; PR3449
 
 define void @test(<8 x double>* %P, i64* %Q) nounwind {
-	%A = load <8 x double>* %P		; <<8 x double>> [#uses=1]
+	%A = load <8 x double>, <8 x double>* %P		; <<8 x double>> [#uses=1]
 	%B = bitcast <8 x double> %A to i512		; <i512> [#uses=1]
 	%C = lshr i512 %B, 448		; <i512> [#uses=1]
 	%D = trunc i512 %C to i64		; <i64> [#uses=1]
diff --git a/test/CodeGen/X86/2009-02-01-LargeMask.ll b/test/CodeGen/X86/2009-02-01-LargeMask.ll
index c4042e6c9c68..e91208d5b3a1 100644
--- a/test/CodeGen/X86/2009-02-01-LargeMask.ll
+++ b/test/CodeGen/X86/2009-02-01-LargeMask.ll
@@ -19,7 +19,7 @@ entry:
 
 bb.i49.i72:		; preds = %bb.i49.i72, %entry
 	%UNP.i1482.0 = phi i288 [ %.ins659, %bb.i49.i72 ], [ undef, %entry ]		; <i288> [#uses=1]
-	%0 = load i32* null, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	%1 = xor i32 %0, 17834		; <i32> [#uses=1]
 	%2 = zext i32 %1 to i288		; <i288> [#uses=1]
 	%3 = shl i288 %2, 160		; <i288> [#uses=1]
diff --git a/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll b/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll
index e75af13a600b..592a7e33b196 100644
--- a/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll
+++ b/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll
@@ -13,7 +13,7 @@ bb:		; preds = %entry
 	unreachable
 
 bb1:		; preds = %entry
-	%0 = load i32* @g_3, align 4		; <i32> [#uses=2]
+	%0 = load i32, i32* @g_3, align 4		; <i32> [#uses=2]
 	%1 = sext i32 %0 to i64		; <i64> [#uses=1]
 	%2 = or i64 %1, %p_66		; <i64> [#uses=1]
 	%3 = shl i64 %2, 0		; <i64> [#uses=1]
diff --git a/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll b/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll
index 4880f626d5da..04dfd846ad4a 100644
--- a/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll
+++ b/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll
@@ -5,5 +5,5 @@
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
 target triple = "i386-pc-linux-gnu"
 @p = common global [10 x i32] zeroinitializer, align 4          ; <[10 x i32]*>
-@g = global [1 x i32*] [ i32* bitcast (i8* getelementptr (i8* bitcast
+@g = global [1 x i32*] [ i32* bitcast (i8* getelementptr (i8, i8* bitcast
 ([10 x i32]* @p to i8*), i64 17179869092) to i32*) ], align 4 
diff --git a/test/CodeGen/X86/2009-02-09-ivs-different-sizes.ll b/test/CodeGen/X86/2009-02-09-ivs-different-sizes.ll
index 36cc53545103..040bcff1bb25 100644
--- a/test/CodeGen/X86/2009-02-09-ivs-different-sizes.ll
+++ b/test/CodeGen/X86/2009-02-09-ivs-different-sizes.ll
@@ -21,7 +21,7 @@ bb56:           ; preds = %bb62, %bb54
         %indvar202 = trunc i64 %p_addr.0.pn.rec to i32          ; <i32>[#uses=1]
         %frac_bits.0 = mul i32 %indvar202, %shift.0             ; <i32>[#uses=1]
         %p_addr.6.rec = add i64 %p_addr.0.pn.rec, 1             ; <i64>[#uses=2]
-        %p_addr.6 = getelementptr i8* null, i64 %p_addr.6.rec           ; <i8*>[#uses=1]
+        %p_addr.6 = getelementptr i8, i8* null, i64 %p_addr.6.rec           ; <i8*>[#uses=1]
         br i1 false, label %bb66, label %bb62
 
 bb62:           ; preds = %bb56
diff --git a/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll b/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll
index 1284b0d1b7b2..19c2dfd4ea87 100644
--- a/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll
+++ b/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll
@@ -6,10 +6,10 @@ target triple = "i386-apple-darwin9.6"
 
 define i32 @alac_decode_frame() nounwind {
 entry:
-	%tmp2 = load i8** null		; <i8*> [#uses=2]
-	%tmp34 = getelementptr i8* %tmp2, i32 4		; <i8*> [#uses=2]
+	%tmp2 = load i8*, i8** null		; <i8*> [#uses=2]
+	%tmp34 = getelementptr i8, i8* %tmp2, i32 4		; <i8*> [#uses=2]
 	%tmp5.i424 = bitcast i8* %tmp34 to i8**		; <i8**> [#uses=2]
-	%tmp15.i = getelementptr i8* %tmp2, i32 12		; <i8*> [#uses=1]
+	%tmp15.i = getelementptr i8, i8* %tmp2, i32 12		; <i8*> [#uses=1]
 	%0 = bitcast i8* %tmp15.i to i32*		; <i32*> [#uses=1]
 	br i1 false, label %if.then43, label %if.end47
 
@@ -17,9 +17,9 @@ if.then43:		; preds = %entry
 	ret i32 0
 
 if.end47:		; preds = %entry
-	%tmp5.i590 = load i8** %tmp5.i424		; <i8*> [#uses=0]
+	%tmp5.i590 = load i8*, i8** %tmp5.i424		; <i8*> [#uses=0]
 	store i32 19, i32* %0
-	%tmp6.i569 = load i8** %tmp5.i424		; <i8*> [#uses=0]
+	%tmp6.i569 = load i8*, i8** %tmp5.i424		; <i8*> [#uses=0]
 	%1 = call i32 asm "bswap   $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 0) nounwind		; <i32> [#uses=0]
 	br i1 false, label %bb.nph, label %if.then63
 
diff --git a/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll b/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll
index 6c8e3b5a8fdc..6c177e5b5f5a 100644
--- a/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll
+++ b/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll
@@ -1,9 +1,19 @@
 ; RUN: llc < %s
-; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -march=x86-64 -verify-machineinstrs | FileCheck %s
 ; PR3538
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin9"
 define signext i8 @foo(i8* %s1) nounwind ssp {
+
+; Make sure we generate:
+;  movq	-40(%rbp), %rsp
+; Instead of:
+;  movq	-40(%rbp), %rax
+;  movq	%rax, %rsp
+
+; CHECK-LABEL: @foo
+; CHECK: movq	-40(%rbp), %rsp
+
 entry:
   %s1_addr = alloca i8*                           ; <i8**> [#uses=2]
   %retval = alloca i32                            ; <i32*> [#uses=2]
@@ -14,46 +24,46 @@ entry:
   %2 = alloca i64                                 ; <i64*> [#uses=1]
   %3 = alloca i64                                 ; <i64*> [#uses=6]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.declare(metadata i8** %s1_addr, metadata !0, metadata !{!"0x102"}), !dbg !7
+  call void @llvm.dbg.declare(metadata i8** %s1_addr, metadata !0, metadata !DIExpression()), !dbg !7
   store i8* %s1, i8** %s1_addr
-  call void @llvm.dbg.declare(metadata [0 x i8]** %str.0, metadata !8, metadata !{!"0x102"}), !dbg !7
+  call void @llvm.dbg.declare(metadata [0 x i8]** %str.0, metadata !8, metadata !DIExpression()), !dbg !7
   %4 = call i8* @llvm.stacksave(), !dbg !7        ; <i8*> [#uses=1]
   store i8* %4, i8** %saved_stack.1, align 8, !dbg !7
-  %5 = load i8** %s1_addr, align 8, !dbg !13      ; <i8*> [#uses=1]
+  %5 = load i8*, i8** %s1_addr, align 8, !dbg !13      ; <i8*> [#uses=1]
   %6 = call i64 @strlen(i8* %5) nounwind readonly, !dbg !13 ; <i64> [#uses=1]
   %7 = add i64 %6, 1, !dbg !13                    ; <i64> [#uses=1]
   store i64 %7, i64* %3, align 8, !dbg !13
-  %8 = load i64* %3, align 8, !dbg !13            ; <i64> [#uses=1]
+  %8 = load i64, i64* %3, align 8, !dbg !13            ; <i64> [#uses=1]
   %9 = sub nsw i64 %8, 1, !dbg !13                ; <i64> [#uses=0]
-  %10 = load i64* %3, align 8, !dbg !13           ; <i64> [#uses=1]
+  %10 = load i64, i64* %3, align 8, !dbg !13           ; <i64> [#uses=1]
   %11 = mul i64 %10, 8, !dbg !13                  ; <i64> [#uses=0]
-  %12 = load i64* %3, align 8, !dbg !13           ; <i64> [#uses=1]
+  %12 = load i64, i64* %3, align 8, !dbg !13           ; <i64> [#uses=1]
   store i64 %12, i64* %2, align 8, !dbg !13
-  %13 = load i64* %3, align 8, !dbg !13           ; <i64> [#uses=1]
+  %13 = load i64, i64* %3, align 8, !dbg !13           ; <i64> [#uses=1]
   %14 = mul i64 %13, 8, !dbg !13                  ; <i64> [#uses=0]
-  %15 = load i64* %3, align 8, !dbg !13           ; <i64> [#uses=1]
+  %15 = load i64, i64* %3, align 8, !dbg !13           ; <i64> [#uses=1]
   store i64 %15, i64* %1, align 8, !dbg !13
-  %16 = load i64* %1, align 8, !dbg !13           ; <i64> [#uses=1]
+  %16 = load i64, i64* %1, align 8, !dbg !13           ; <i64> [#uses=1]
   %17 = trunc i64 %16 to i32, !dbg !13            ; <i32> [#uses=1]
   %18 = alloca i8, i32 %17, !dbg !13              ; <i8*> [#uses=1]
   %19 = bitcast i8* %18 to [0 x i8]*, !dbg !13    ; <[0 x i8]*> [#uses=1]
   store [0 x i8]* %19, [0 x i8]** %str.0, align 8, !dbg !13
-  %20 = load [0 x i8]** %str.0, align 8, !dbg !15 ; <[0 x i8]*> [#uses=1]
-  %21 = getelementptr inbounds [0 x i8]* %20, i64 0, i64 0, !dbg !15 ; <i8*> [#uses=1]
+  %20 = load [0 x i8]*, [0 x i8]** %str.0, align 8, !dbg !15 ; <[0 x i8]*> [#uses=1]
+  %21 = getelementptr inbounds [0 x i8], [0 x i8]* %20, i64 0, i64 0, !dbg !15 ; <i8*> [#uses=1]
   store i8 0, i8* %21, align 1, !dbg !15
-  %22 = load [0 x i8]** %str.0, align 8, !dbg !16 ; <[0 x i8]*> [#uses=1]
-  %23 = getelementptr inbounds [0 x i8]* %22, i64 0, i64 0, !dbg !16 ; <i8*> [#uses=1]
-  %24 = load i8* %23, align 1, !dbg !16           ; <i8> [#uses=1]
+  %22 = load [0 x i8]*, [0 x i8]** %str.0, align 8, !dbg !16 ; <[0 x i8]*> [#uses=1]
+  %23 = getelementptr inbounds [0 x i8], [0 x i8]* %22, i64 0, i64 0, !dbg !16 ; <i8*> [#uses=1]
+  %24 = load i8, i8* %23, align 1, !dbg !16           ; <i8> [#uses=1]
   %25 = sext i8 %24 to i32, !dbg !16              ; <i32> [#uses=1]
   store i32 %25, i32* %0, align 4, !dbg !16
-  %26 = load i8** %saved_stack.1, align 8, !dbg !16 ; <i8*> [#uses=1]
+  %26 = load i8*, i8** %saved_stack.1, align 8, !dbg !16 ; <i8*> [#uses=1]
   call void @llvm.stackrestore(i8* %26), !dbg !16
-  %27 = load i32* %0, align 4, !dbg !16           ; <i32> [#uses=1]
+  %27 = load i32, i32* %0, align 4, !dbg !16           ; <i32> [#uses=1]
   store i32 %27, i32* %retval, align 4, !dbg !16
   br label %return, !dbg !16
 
 return:                                           ; preds = %entry
-  %retval1 = load i32* %retval, !dbg !16          ; <i32> [#uses=1]
+  %retval1 = load i32, i32* %retval, !dbg !16          ; <i32> [#uses=1]
   %retval12 = trunc i32 %retval1 to i8, !dbg !16  ; <i8> [#uses=1]
   ret i8 %retval12, !dbg !16
 }
@@ -66,22 +76,22 @@ declare i64 @strlen(i8*) nounwind readonly
 
 declare void @llvm.stackrestore(i8*) nounwind
 
-!0 = !{!"0x101\00s1\002\000", !1, !2, !6} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00foo\00foo\00foo\002\000\001\000\006\000\000\000", i32 0, !2, !3, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\001\00\000\00\000", !17, !18, !18, null, null, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", null, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "s1", line: 2, arg: 0, scope: !1, file: !2, type: !6)
+!1 = !DISubprogram(name: "foo", linkageName: "foo", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !2, type: !3)
+!2 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 0, file: !17, enums: !18, retainedTypes: !18)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5, !6}
-!5 = !{!"0x24\00char\000\008\008\000\000\006", null, !2} ; [ DW_TAG_base_type ]
-!6 = !{!"0xf\00\000\0064\0064\000\000", null, !2, !5} ; [ DW_TAG_pointer_type ]
-!7 = !MDLocation(line: 2, scope: !1)
-!8 = !{!"0x100\00str.0\003\000", !1, !2, !9} ; [ DW_TAG_auto_variable ]
-!9 = !{!"0xf\00\000\0064\0064\000\0064", null, !2, !10} ; [ DW_TAG_pointer_type ]
-!10 = !{!"0x1\00\000\008\008\000\000", null, !2, !5, !11, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 8, align 8, offset 0] [from char]
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, scope: !2, baseType: !5)
+!7 = !DILocation(line: 2, scope: !1)
+!8 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "str.0", line: 3, scope: !1, file: !2, type: !9)
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, scope: !2, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_array_type, size: 8, align: 8, scope: !2, baseType: !5, elements: !11)
 !11 = !{!12}
-!12 = !{!"0x21\000\001"}        ; [ DW_TAG_subrange_type ]
-!13 = !MDLocation(line: 3, scope: !14)
-!14 = !{!"0xb\000\000\000", !17, !1} ; [ DW_TAG_lexical_block ]
-!15 = !MDLocation(line: 4, scope: !14)
-!16 = !MDLocation(line: 5, scope: !14)
-!17 = !{!"vla.c", !"/tmp/"}
+!12 = !DISubrange(count: 1)
+!13 = !DILocation(line: 3, scope: !14)
+!14 = distinct !DILexicalBlock(line: 0, column: 0, file: !17, scope: !1)
+!15 = !DILocation(line: 4, scope: !14)
+!16 = !DILocation(line: 5, scope: !14)
+!17 = !DIFile(filename: "vla.c", directory: "/tmp/")
 !18 = !{i32 0}
diff --git a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
index e046b966921f..172a00a7c86f 100644
--- a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
+++ b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
@@ -1,5 +1,5 @@
 ; REQUIRES: asserts
-; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse4.1 -mcpu=penryn -stats 2>&1 | grep "7 machine-licm"
+; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse4.1 -mcpu=penryn -stats 2>&1 | grep "9 machine-licm"
 ; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse4.1 -mcpu=penryn | FileCheck %s
 ; rdar://6627786
 ; rdar://7792037
@@ -21,9 +21,9 @@ bb4:		; preds = %bb.i, %bb26, %bb4, %entry
 ; CHECK: xorl
 ; CHECK: movq
 
-	%0 = call i32 (...)* @xxGetOffsetForCode(i32 undef) nounwind		; <i32> [#uses=0]
+	%0 = call i32 (...) @xxGetOffsetForCode(i32 undef) nounwind		; <i32> [#uses=0]
 	%ins = or i64 %p, 2097152		; <i64> [#uses=1]
-	%1 = call i32 (...)* @xxCalculateMidType(%struct.Key* %desc, i32 0) nounwind		; <i32> [#uses=1]
+	%1 = call i32 (...) @xxCalculateMidType(%struct.Key* %desc, i32 0) nounwind		; <i32> [#uses=1]
 	%cond = icmp eq i32 %1, 1		; <i1> [#uses=1]
 	br i1 %cond, label %bb26, label %bb4
 
@@ -33,17 +33,17 @@ bb26:		; preds = %bb4
 	br i1 %cond.i, label %bb.i, label %bb4
 
 bb.i:		; preds = %bb26
-	%3 = load i32* null, align 4		; <i32> [#uses=1]
+	%3 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	%4 = uitofp i32 %3 to float		; <float> [#uses=1]
 	%.sum13.i = add i64 0, 4		; <i64> [#uses=1]
-	%5 = getelementptr i8* null, i64 %.sum13.i		; <i8*> [#uses=1]
+	%5 = getelementptr i8, i8* null, i64 %.sum13.i		; <i8*> [#uses=1]
 	%6 = bitcast i8* %5 to i32*		; <i32*> [#uses=1]
-	%7 = load i32* %6, align 4		; <i32> [#uses=1]
+	%7 = load i32, i32* %6, align 4		; <i32> [#uses=1]
 	%8 = uitofp i32 %7 to float		; <float> [#uses=1]
 	%.sum.i = add i64 0, 8		; <i64> [#uses=1]
-	%9 = getelementptr i8* null, i64 %.sum.i		; <i8*> [#uses=1]
+	%9 = getelementptr i8, i8* null, i64 %.sum.i		; <i8*> [#uses=1]
 	%10 = bitcast i8* %9 to i32*		; <i32*> [#uses=1]
-	%11 = load i32* %10, align 4		; <i32> [#uses=1]
+	%11 = load i32, i32* %10, align 4		; <i32> [#uses=1]
 	%12 = uitofp i32 %11 to float		; <float> [#uses=1]
 	%13 = insertelement <4 x float> undef, float %4, i32 0		; <<4 x float>> [#uses=1]
 	%14 = insertelement <4 x float> %13, float %8, i32 1		; <<4 x float>> [#uses=1]
diff --git a/test/CodeGen/X86/2009-03-03-BTHang.ll b/test/CodeGen/X86/2009-03-03-BTHang.ll
index bb9592577435..d6d24cda295f 100644
--- a/test/CodeGen/X86/2009-03-03-BTHang.ll
+++ b/test/CodeGen/X86/2009-03-03-BTHang.ll
@@ -9,23 +9,23 @@ entry:
 	%0 = ptrtoint i8** %h to i32		; <i32> [#uses=2]
 	%1 = and i32 %0, -4096		; <i32> [#uses=1]
 	%2 = inttoptr i32 %1 to %struct.HandleBlock*		; <%struct.HandleBlock*> [#uses=3]
-	%3 = getelementptr %struct.HandleBlock* %2, i32 0, i32 0, i32 0		; <i32*> [#uses=1]
-	%4 = load i32* %3, align 4096		; <i32> [#uses=1]
+	%3 = getelementptr %struct.HandleBlock, %struct.HandleBlock* %2, i32 0, i32 0, i32 0		; <i32*> [#uses=1]
+	%4 = load i32, i32* %3, align 4096		; <i32> [#uses=1]
 	%5 = icmp eq i32 %4, 1751280747		; <i1> [#uses=1]
 	br i1 %5, label %bb, label %bb1
 
 bb:		; preds = %entry
-	%6 = getelementptr %struct.HandleBlock* %2, i32 0, i32 1		; <[990 x i8*]*> [#uses=1]
+	%6 = getelementptr %struct.HandleBlock, %struct.HandleBlock* %2, i32 0, i32 1		; <[990 x i8*]*> [#uses=1]
 	%7 = ptrtoint [990 x i8*]* %6 to i32		; <i32> [#uses=1]
 	%8 = sub i32 %0, %7		; <i32> [#uses=2]
 	%9 = lshr i32 %8, 2		; <i32> [#uses=1]
 	%10 = ashr i32 %8, 7		; <i32> [#uses=1]
 	%11 = and i32 %10, 134217727		; <i32> [#uses=1]
-	%12 = getelementptr %struct.HandleBlock* %2, i32 0, i32 0, i32 %11		; <i32*> [#uses=1]
+	%12 = getelementptr %struct.HandleBlock, %struct.HandleBlock* %2, i32 0, i32 0, i32 %11		; <i32*> [#uses=1]
 	%not.i = and i32 %9, 31		; <i32> [#uses=1]
 	%13 = xor i32 %not.i, 31		; <i32> [#uses=1]
 	%14 = shl i32 1, %13		; <i32> [#uses=1]
-	%15 = load i32* %12, align 4		; <i32> [#uses=1]
+	%15 = load i32, i32* %12, align 4		; <i32> [#uses=1]
 	%16 = and i32 %15, %14		; <i32> [#uses=1]
 	%17 = icmp eq i32 %16, 0		; <i1> [#uses=1]
 	%tmp = zext i1 %17 to i8		; <i8> [#uses=1]
diff --git a/test/CodeGen/X86/2009-03-05-burr-list-crash.ll b/test/CodeGen/X86/2009-03-05-burr-list-crash.ll
index 411a0c92830a..853bb16aa327 100644
--- a/test/CodeGen/X86/2009-03-05-burr-list-crash.ll
+++ b/test/CodeGen/X86/2009-03-05-burr-list-crash.ll
@@ -15,12 +15,12 @@ define fastcc i8* @1(i8*) nounwind {
 ; <label>:3		; preds = %1
 	%4 = call i64 @strlen(i8* %0) nounwind readonly		; <i64> [#uses=1]
 	%5 = trunc i64 %4 to i32		; <i32> [#uses=2]
-	%6 = load i32* @0, align 4		; <i32> [#uses=1]
+	%6 = load i32, i32* @0, align 4		; <i32> [#uses=1]
 	%7 = sub i32 %5, %6		; <i32> [#uses=2]
 	%8 = sext i32 %5 to i64		; <i64> [#uses=1]
 	%9 = sext i32 %7 to i64		; <i64> [#uses=1]
 	%10 = sub i64 %8, %9		; <i64> [#uses=1]
-	%11 = getelementptr i8* %0, i64 %10		; <i8*> [#uses=1]
+	%11 = getelementptr i8, i8* %0, i64 %10		; <i8*> [#uses=1]
 	%12 = icmp sgt i32 %7, 0		; <i1> [#uses=1]
 	br i1 %12, label %13, label %14
 
diff --git a/test/CodeGen/X86/2009-03-09-APIntCrash.ll b/test/CodeGen/X86/2009-03-09-APIntCrash.ll
index 896c9686cc4e..3bff7dc76561 100644
--- a/test/CodeGen/X86/2009-03-09-APIntCrash.ll
+++ b/test/CodeGen/X86/2009-03-09-APIntCrash.ll
@@ -7,7 +7,7 @@ entry:
 	br i1 false, label %if.then, label %return
 
 if.then:		; preds = %entry
-	%srcval18 = load i128* null, align 8		; <i128> [#uses=1]
+	%srcval18 = load i128, i128* null, align 8		; <i128> [#uses=1]
 	%tmp15 = lshr i128 %srcval18, 64		; <i128> [#uses=1]
 	%tmp9 = mul i128 %tmp15, 18446744073709551616000		; <i128> [#uses=1]
 	br label %return
diff --git a/test/CodeGen/X86/2009-03-10-CoalescerBug.ll b/test/CodeGen/X86/2009-03-10-CoalescerBug.ll
index 90dff8878a78..38dd2fa0b108 100644
--- a/test/CodeGen/X86/2009-03-10-CoalescerBug.ll
+++ b/test/CodeGen/X86/2009-03-10-CoalescerBug.ll
@@ -8,7 +8,7 @@
 
 define i32 @pnoutrefresh(%struct.WINDOW* %win, i32 %pminrow, i32 %pmincol, i32 %sminrow, i32 %smincol, i32 %smaxrow, i32 %smaxcol) nounwind optsize ssp {
 entry:
-	%0 = load i16* null, align 4		; <i16> [#uses=2]
+	%0 = load i16, i16* null, align 4		; <i16> [#uses=2]
 	%1 = icmp sgt i16 0, %0		; <i1> [#uses=1]
 	br i1 %1, label %bb12, label %bb13
 
diff --git a/test/CodeGen/X86/2009-03-23-LinearScanBug.ll b/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
index 06dfdc0c767f..584e4e63e4a9 100644
--- a/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
+++ b/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
@@ -2,9 +2,9 @@
 
 define fastcc void @optimize_bit_field() nounwind {
 bb4:
-        %a = load i32* null             ; <i32> [#uses=1]
-        %s = load i32* getelementptr (i32* null, i32 1)         ; <i32> [#uses=1]
-        %z = load i32* getelementptr (i32* null, i32 2)         ; <i32> [#uses=1]
+        %a = load i32, i32* null             ; <i32> [#uses=1]
+        %s = load i32, i32* getelementptr (i32, i32* null, i32 1)         ; <i32> [#uses=1]
+        %z = load i32, i32* getelementptr (i32, i32* null, i32 2)         ; <i32> [#uses=1]
         %r = bitcast i32 0 to i32          ; <i32> [#uses=1]
         %q = trunc i32 %z to i8            ; <i8> [#uses=1]
         %b = icmp eq i8 0, %q              ; <i1> [#uses=1]
@@ -16,7 +16,7 @@ bb72:      ; preds = %bb4
 
 bb73:         ; preds = %bb72, %bb4
         %y = phi i32 [ %f, %bb72 ], [ %s, %bb4 ]          ; <i32> [#uses=1]
-        store i32 %y, i32* getelementptr (i32* null, i32 3)
+        store i32 %y, i32* getelementptr (i32, i32* null, i32 3)
         unreachable
 }
 
diff --git a/test/CodeGen/X86/2009-03-23-MultiUseSched.ll b/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
index bbc1d341d4e0..276d52366ae8 100644
--- a/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
+++ b/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
@@ -10,30 +10,30 @@
 @X = external global i64		; <i64*> [#uses=25]
 
 define fastcc i64 @foo() nounwind {
-	%tmp = load volatile i64* @X		; <i64> [#uses=7]
-	%tmp1 = load volatile i64* @X		; <i64> [#uses=5]
-	%tmp2 = load volatile i64* @X		; <i64> [#uses=3]
-	%tmp3 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp4 = load volatile i64* @X		; <i64> [#uses=5]
-	%tmp5 = load volatile i64* @X		; <i64> [#uses=3]
-	%tmp6 = load volatile i64* @X		; <i64> [#uses=2]
-	%tmp7 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp8 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp9 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp10 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp11 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp12 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp13 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp14 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp15 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp16 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp17 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp18 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp19 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp20 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp21 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp22 = load volatile i64* @X		; <i64> [#uses=1]
-	%tmp23 = load volatile i64* @X		; <i64> [#uses=1]
+	%tmp = load volatile i64, i64* @X		; <i64> [#uses=7]
+	%tmp1 = load volatile i64, i64* @X		; <i64> [#uses=5]
+	%tmp2 = load volatile i64, i64* @X		; <i64> [#uses=3]
+	%tmp3 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp4 = load volatile i64, i64* @X		; <i64> [#uses=5]
+	%tmp5 = load volatile i64, i64* @X		; <i64> [#uses=3]
+	%tmp6 = load volatile i64, i64* @X		; <i64> [#uses=2]
+	%tmp7 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp8 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp9 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp10 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp11 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp12 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp13 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp14 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp15 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp16 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp17 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp18 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp19 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp20 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp21 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp22 = load volatile i64, i64* @X		; <i64> [#uses=1]
+	%tmp23 = load volatile i64, i64* @X		; <i64> [#uses=1]
 	%tmp24 = call i64 @llvm.bswap.i64(i64 %tmp8)		; <i64> [#uses=1]
 	%tmp25 = add i64 %tmp6, %tmp5		; <i64> [#uses=1]
 	%tmp26 = add i64 %tmp25, %tmp4		; <i64> [#uses=1]
diff --git a/test/CodeGen/X86/2009-03-25-TestBug.ll b/test/CodeGen/X86/2009-03-25-TestBug.ll
index cc1d73da05c5..367a6d2a3b84 100644
--- a/test/CodeGen/X86/2009-03-25-TestBug.ll
+++ b/test/CodeGen/X86/2009-03-25-TestBug.ll
@@ -9,17 +9,17 @@
 
 define void @func(i32* %b) nounwind {
 bb1579.i.i:		; preds = %bb1514.i.i, %bb191.i.i
-	%tmp176 = load i32* %b, align 4
+	%tmp176 = load i32, i32* %b, align 4
 	%tmp177 = and i32 %tmp176, 2
 	%tmp178 = icmp eq i32 %tmp177, 0
         br i1 %tmp178, label %hello, label %world
 
 hello:
-	%h = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8]* @hello, i32 0, i32 0))
+	%h = tail call i32 (i8*, ...) @printf( i8* getelementptr ([7 x i8], [7 x i8]* @hello, i32 0, i32 0))
         ret void
 
 world:
-	%w = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8]* @world, i32 0, i32 0))
+	%w = tail call i32 (i8*, ...) @printf( i8* getelementptr ([7 x i8], [7 x i8]* @world, i32 0, i32 0))
         ret void
 }
 
diff --git a/test/CodeGen/X86/2009-04-12-picrel.ll b/test/CodeGen/X86/2009-04-12-picrel.ll
index f1942801c7af..037dee95717f 100644
--- a/test/CodeGen/X86/2009-04-12-picrel.ll
+++ b/test/CodeGen/X86/2009-04-12-picrel.ll
@@ -7,7 +7,7 @@
 define void @off01(i64 %i) nounwind {
 entry:
 	%.sum = add i64 %i, 16
-	%0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %.sum
+	%0 = getelementptr [131072 x i32], [131072 x i32]* @dst, i64 0, i64 %.sum
 	store i32* %0, i32** @ptr, align 8
 	ret void
 }
diff --git a/test/CodeGen/X86/2009-04-13-2AddrAssert.ll b/test/CodeGen/X86/2009-04-13-2AddrAssert.ll
index 4362ba437541..a3607c6815ac 100644
--- a/test/CodeGen/X86/2009-04-13-2AddrAssert.ll
+++ b/test/CodeGen/X86/2009-04-13-2AddrAssert.ll
@@ -7,7 +7,7 @@ target triple = "x86_64-undermydesk-freebsd8.0"
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
 entry:
-        %call = tail call i32 (...)* @getpid()          ; <i32> [#uses=1]
+        %call = tail call i32 (...) @getpid()          ; <i32> [#uses=1]
         %conv = trunc i32 %call to i16          ; <i16> [#uses=1]
         %0 = tail call i16 asm "xchgb ${0:h}, ${0:b}","=Q,0,~{dirflag},~{fpsr},~{flags}"(i16 %conv) nounwind           ; <i16> [#uses=0]
         ret i32 undef
diff --git a/test/CodeGen/X86/2009-04-14-IllegalRegs.ll b/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
index bed863e405a8..8055ea880795 100644
--- a/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
+++ b/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
@@ -10,25 +10,25 @@ entry:
 	%xxx = alloca %struct.X		; <%struct.X*> [#uses=6]
 	%0 = alloca i32		; <i32*> [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
-	%1 = getelementptr %struct.X* %xxx, i32 0, i32 1		; <[32 x i8]*> [#uses=1]
-	%2 = getelementptr [32 x i8]* %1, i32 0, i32 31		; <i8*> [#uses=1]
+	%1 = getelementptr %struct.X, %struct.X* %xxx, i32 0, i32 1		; <[32 x i8]*> [#uses=1]
+	%2 = getelementptr [32 x i8], [32 x i8]* %1, i32 0, i32 31		; <i8*> [#uses=1]
 	store i8 48, i8* %2, align 1
-	%3 = getelementptr %struct.X* %xxx, i32 0, i32 1		; <[32 x i8]*> [#uses=1]
-	%4 = getelementptr [32 x i8]* %3, i32 0, i32 31		; <i8*> [#uses=1]
-	%5 = load i8* %4, align 1		; <i8> [#uses=1]
-	%6 = getelementptr %struct.X* %xxx, i32 0, i32 1		; <[32 x i8]*> [#uses=1]
-	%7 = getelementptr [32 x i8]* %6, i32 0, i32 0		; <i8*> [#uses=1]
+	%3 = getelementptr %struct.X, %struct.X* %xxx, i32 0, i32 1		; <[32 x i8]*> [#uses=1]
+	%4 = getelementptr [32 x i8], [32 x i8]* %3, i32 0, i32 31		; <i8*> [#uses=1]
+	%5 = load i8, i8* %4, align 1		; <i8> [#uses=1]
+	%6 = getelementptr %struct.X, %struct.X* %xxx, i32 0, i32 1		; <[32 x i8]*> [#uses=1]
+	%7 = getelementptr [32 x i8], [32 x i8]* %6, i32 0, i32 0		; <i8*> [#uses=1]
 	store i8 %5, i8* %7, align 1
-	%8 = getelementptr %struct.X* %xxx, i32 0, i32 0		; <i8*> [#uses=1]
+	%8 = getelementptr %struct.X, %struct.X* %xxx, i32 0, i32 0		; <i8*> [#uses=1]
 	store i8 15, i8* %8, align 1
-	%9 = call i32 (...)* bitcast (i32 (%struct.X*, %struct.X*)* @f to i32 (...)*)(%struct.X* byval align 4 %xxx, %struct.X* byval align 4 %xxx) nounwind		; <i32> [#uses=1]
+	%9 = call i32 (...) bitcast (i32 (%struct.X*, %struct.X*)* @f to i32 (...)*)(%struct.X* byval align 4 %xxx, %struct.X* byval align 4 %xxx) nounwind		; <i32> [#uses=1]
 	store i32 %9, i32* %0, align 4
-	%10 = load i32* %0, align 4		; <i32> [#uses=1]
+	%10 = load i32, i32* %0, align 4		; <i32> [#uses=1]
 	store i32 %10, i32* %retval, align 4
 	br label %return
 
 return:		; preds = %entry
-	%retval1 = load i32* %retval		; <i32> [#uses=1]
+	%retval1 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval1
 }
 
diff --git a/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll b/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll
index 679a65d93d09..1d03a1b20a34 100644
--- a/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll
+++ b/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll
@@ -47,7 +47,7 @@ bb349:		; preds = %bb349, %entry
 	%23 = add i32 0, 12		; <i32> [#uses=1]
 	%24 = and i32 %23, 12		; <i32> [#uses=1]
 	%25 = zext i32 %24 to i64		; <i64> [#uses=1]
-	%26 = getelementptr [16 x i64]* null, i64 0, i64 %25		; <i64*> [#uses=0]
+	%26 = getelementptr [16 x i64], [16 x i64]* null, i64 0, i64 %25		; <i64*> [#uses=0]
 	%27 = add i64 0, %e.0489		; <i64> [#uses=1]
 	%28 = add i64 %27, 0		; <i64> [#uses=1]
 	%29 = add i64 %28, 0		; <i64> [#uses=1]
@@ -67,12 +67,12 @@ bb349:		; preds = %bb349, %entry
 	%43 = or i32 0, 6		; <i32> [#uses=1]
 	%44 = and i32 %43, 14		; <i32> [#uses=1]
 	%45 = zext i32 %44 to i64		; <i64> [#uses=1]
-	%46 = getelementptr [16 x i64]* null, i64 0, i64 %45		; <i64*> [#uses=1]
+	%46 = getelementptr [16 x i64], [16 x i64]* null, i64 0, i64 %45		; <i64*> [#uses=1]
 	%not417 = xor i64 %42, -1		; <i64> [#uses=1]
 	%47 = and i64 %20, %not417		; <i64> [#uses=1]
 	%48 = xor i64 0, %47		; <i64> [#uses=1]
-	%49 = getelementptr [80 x i64]* @K512, i64 0, i64 0		; <i64*> [#uses=1]
-	%50 = load i64* %49, align 8		; <i64> [#uses=1]
+	%49 = getelementptr [80 x i64], [80 x i64]* @K512, i64 0, i64 0		; <i64*> [#uses=1]
+	%50 = load i64, i64* %49, align 8		; <i64> [#uses=1]
 	%51 = add i64 %48, 0		; <i64> [#uses=1]
 	%52 = add i64 %51, 0		; <i64> [#uses=1]
 	%53 = add i64 %52, 0		; <i64> [#uses=1]
@@ -87,13 +87,13 @@ bb349:		; preds = %bb349, %entry
 	%60 = or i32 0, 7		; <i32> [#uses=1]
 	%61 = and i32 %60, 15		; <i32> [#uses=1]
 	%62 = zext i32 %61 to i64		; <i64> [#uses=1]
-	%63 = getelementptr [16 x i64]* null, i64 0, i64 %62		; <i64*> [#uses=2]
-	%64 = load i64* null, align 8		; <i64> [#uses=1]
+	%63 = getelementptr [16 x i64], [16 x i64]* null, i64 0, i64 %62		; <i64*> [#uses=2]
+	%64 = load i64, i64* null, align 8		; <i64> [#uses=1]
 	%65 = lshr i64 %64, 6		; <i64> [#uses=1]
 	%66 = xor i64 0, %65		; <i64> [#uses=1]
 	%67 = xor i64 %66, 0		; <i64> [#uses=1]
-	%68 = load i64* %46, align 8		; <i64> [#uses=1]
-	%69 = load i64* null, align 8		; <i64> [#uses=1]
+	%68 = load i64, i64* %46, align 8		; <i64> [#uses=1]
+	%69 = load i64, i64* null, align 8		; <i64> [#uses=1]
 	%70 = add i64 %68, 0		; <i64> [#uses=1]
 	%71 = add i64 %70, %67		; <i64> [#uses=1]
 	%72 = add i64 %71, %69		; <i64> [#uses=1]
@@ -105,8 +105,8 @@ bb349:		; preds = %bb349, %entry
 	%not429 = xor i64 %57, -1		; <i64> [#uses=1]
 	%76 = and i64 %33, %not429		; <i64> [#uses=1]
 	%77 = xor i64 %75, %76		; <i64> [#uses=1]
-	%78 = getelementptr [80 x i64]* @K512, i64 0, i64 0		; <i64*> [#uses=1]
-	%79 = load i64* %78, align 16		; <i64> [#uses=1]
+	%78 = getelementptr [80 x i64], [80 x i64]* @K512, i64 0, i64 0		; <i64*> [#uses=1]
+	%79 = load i64, i64* %78, align 16		; <i64> [#uses=1]
 	%80 = add i64 %77, %20		; <i64> [#uses=1]
 	%81 = add i64 %80, %72		; <i64> [#uses=1]
 	%82 = add i64 %81, %74		; <i64> [#uses=1]
@@ -119,14 +119,14 @@ bb349:		; preds = %bb349, %entry
 	%87 = add i64 0, %85		; <i64> [#uses=1]
 	%asmtmp435 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 8, i64 0) nounwind		; <i64> [#uses=1]
 	%88 = xor i64 0, %asmtmp435		; <i64> [#uses=1]
-	%89 = load i64* null, align 8		; <i64> [#uses=3]
+	%89 = load i64, i64* null, align 8		; <i64> [#uses=3]
 	%asmtmp436 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 19, i64 %89) nounwind		; <i64> [#uses=1]
 	%asmtmp437 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 61, i64 %89) nounwind		; <i64> [#uses=1]
 	%90 = lshr i64 %89, 6		; <i64> [#uses=1]
 	%91 = xor i64 %asmtmp436, %90		; <i64> [#uses=1]
 	%92 = xor i64 %91, %asmtmp437		; <i64> [#uses=1]
-	%93 = load i64* %63, align 8		; <i64> [#uses=1]
-	%94 = load i64* null, align 8		; <i64> [#uses=1]
+	%93 = load i64, i64* %63, align 8		; <i64> [#uses=1]
+	%94 = load i64, i64* null, align 8		; <i64> [#uses=1]
 	%95 = add i64 %93, %88		; <i64> [#uses=1]
 	%96 = add i64 %95, %92		; <i64> [#uses=1]
 	%97 = add i64 %96, %94		; <i64> [#uses=2]
diff --git a/test/CodeGen/X86/2009-04-24.ll b/test/CodeGen/X86/2009-04-24.ll
index d104c875760a..7647dcc7febd 100644
--- a/test/CodeGen/X86/2009-04-24.ll
+++ b/test/CodeGen/X86/2009-04-24.ll
@@ -8,6 +8,6 @@
 
 define i32 @f() {
 entry:
-	%tmp1 = load i32* @i
+	%tmp1 = load i32, i32* @i
 	ret i32 %tmp1
 }
diff --git a/test/CodeGen/X86/2009-04-25-CoalescerBug.ll b/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
index 94d3eb21cecc..c687b6905b7d 100644
--- a/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
+++ b/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
@@ -6,7 +6,7 @@ entry:
 	br label %while.cond
 
 while.cond:		; preds = %while.cond, %entry
-	%tmp15 = load i32* %tmp13		; <i32> [#uses=2]
+	%tmp15 = load i32, i32* %tmp13		; <i32> [#uses=2]
 	%bf.lo = lshr i32 %tmp15, 1		; <i32> [#uses=1]
 	%bf.lo.cleared = and i32 %bf.lo, 2147483647		; <i32> [#uses=1]
 	%conv = zext i32 %bf.lo.cleared to i64		; <i64> [#uses=1]
diff --git a/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll b/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll
index 7981a52e740a..a364c89b5f49 100644
--- a/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll
+++ b/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll
@@ -22,24 +22,24 @@
 define void @getAffNeighbour(i32 %curr_mb_nr, i32 %xN, i32 %yN, i32 %is_chroma, %struct.PixelPos* %pix) nounwind {
 entry:
 	%Opq.sa.calc = add i32 0, 2		; <i32> [#uses=2]
-	%0 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=3]
-	%1 = getelementptr %struct.ImageParameters* %0, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
-	%2 = load %struct.Macroblock** %1, align 8		; <%struct.Macroblock*> [#uses=24]
+	%0 = load %struct.ImageParameters*, %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=3]
+	%1 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %0, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%2 = load %struct.Macroblock*, %struct.Macroblock** %1, align 8		; <%struct.Macroblock*> [#uses=24]
 	%3 = zext i32 %curr_mb_nr to i64		; <i64> [#uses=24]
 	%4 = sext i32 %is_chroma to i64		; <i64> [#uses=8]
 	br label %meshBB392
 
 entry.fragment:		; preds = %meshBB392
 	%Opq.sa.calc747 = add i32 %Opq.sa.calc921, 70		; <i32> [#uses=0]
-	%5 = getelementptr %struct.ImageParameters* %0, i64 0, i32 119, i64 %4, i64 0		; <i32*> [#uses=1]
-	%6 = load i32* %5, align 4		; <i32> [#uses=2]
-	%7 = getelementptr %struct.ImageParameters* %0, i64 0, i32 119, i64 %4, i64 1		; <i32*> [#uses=1]
-	%8 = load i32* %7, align 4		; <i32> [#uses=5]
+	%5 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %0, i64 0, i32 119, i64 %4, i64 0		; <i32*> [#uses=1]
+	%6 = load i32, i32* %5, align 4		; <i32> [#uses=2]
+	%7 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %0, i64 0, i32 119, i64 %4, i64 1		; <i32*> [#uses=1]
+	%8 = load i32, i32* %7, align 4		; <i32> [#uses=5]
 	br label %entry.fragment181
 
 entry.fragment181:		; preds = %entry.fragment
 	%Opq.sa.calc863 = add i32 %Opq.sa.calc921, -50		; <i32> [#uses=4]
-	%9 = getelementptr %struct.PixelPos* %pix, i64 0, i32 0		; <i32*> [#uses=4]
+	%9 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 0		; <i32*> [#uses=4]
 	store i32 0, i32* %9, align 4
 	%10 = add i32 %8, -1		; <i32> [#uses=6]
 	%11 = icmp slt i32 %10, %yN		; <i1> [#uses=1]
@@ -74,8 +74,8 @@ bb4:		; preds = %bb3
 
 bb5:		; preds = %meshBB428
 	%Opq.sa.calc470 = sub i32 %Opq.sa.calc897, -49		; <i32> [#uses=1]
-	%17 = getelementptr %struct.Macroblock* %2, i64 %3, i32 20		; <i32*> [#uses=1]
-	%18 = load i32* %17, align 4		; <i32> [#uses=1]
+	%17 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 20		; <i32*> [#uses=1]
+	%18 = load i32, i32* %17, align 4		; <i32> [#uses=1]
 	br label %bb5.fragment
 
 bb5.fragment:		; preds = %bb5
@@ -91,10 +91,10 @@ bb6:		; preds = %bb5.fragment
 
 bb7:		; preds = %bb6
 	%Opq.sa.calc476 = add i32 %Opq.sa.calc873, -58		; <i32> [#uses=1]
-	%22 = getelementptr %struct.Macroblock* %2, i64 %3, i32 25		; <i32*> [#uses=1]
-	%23 = load i32* %22, align 8		; <i32> [#uses=1]
+	%22 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 25		; <i32*> [#uses=1]
+	%23 = load i32, i32* %22, align 8		; <i32> [#uses=1]
 	%24 = add i32 %23, 1		; <i32> [#uses=1]
-	%25 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	%25 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
 	br label %meshBB388
 
 bb7.fragment:		; preds = %meshBB388
@@ -102,41 +102,41 @@ bb7.fragment:		; preds = %meshBB388
 	%Opq.sa.calc707 = add i32 %Opq.sa.calc709, %Opq.sa.calc886		; <i32> [#uses=1]
 	%Opq.sa.calc708 = xor i32 %Opq.sa.calc707, 474		; <i32> [#uses=0]
 	store i32 %.SV194.phi, i32* %.SV196.phi, align 4
-	%26 = getelementptr %struct.Macroblock* %.load17.SV.phi, i64 %.load36.SV.phi, i32 29		; <i32*> [#uses=1]
-	%27 = load i32* %26, align 8		; <i32> [#uses=2]
+	%26 = getelementptr %struct.Macroblock, %struct.Macroblock* %.load17.SV.phi, i64 %.load36.SV.phi, i32 29		; <i32*> [#uses=1]
+	%27 = load i32, i32* %26, align 8		; <i32> [#uses=2]
 	store i32 %27, i32* %.load67.SV.phi, align 4
 	br label %bb96
 
 bb8:		; preds = %meshBB348
 	%Opq.sa.calc479 = sub i32 %Opq.sa.calc805, 141		; <i32> [#uses=1]
-	%28 = getelementptr %struct.Macroblock* %2, i64 %3, i32 22		; <i32*> [#uses=2]
-	%29 = load i32* %28, align 4		; <i32> [#uses=2]
-	%30 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=2]
+	%28 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 22		; <i32*> [#uses=2]
+	%29 = load i32, i32* %28, align 4		; <i32> [#uses=2]
+	%30 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=2]
 	br label %meshBB368
 
 bb8.fragment:		; preds = %meshBB368
 	%Opq.sa.calc765 = sub i32 %Opq.sa.calc768, -115		; <i32> [#uses=2]
 	store i32 %.SV198.phi, i32* %.SV200.phi, align 4
-	%31 = getelementptr %struct.Macroblock* %.load16.SV.phi, i64 %.load35.SV.phi, i32 26		; <i32*> [#uses=2]
-	%32 = load i32* %31, align 4		; <i32> [#uses=4]
+	%31 = getelementptr %struct.Macroblock, %struct.Macroblock* %.load16.SV.phi, i64 %.load35.SV.phi, i32 26		; <i32*> [#uses=2]
+	%32 = load i32, i32* %31, align 4		; <i32> [#uses=4]
 	store i32 %32, i32* %.load66.SV.phi, align 4
-	%33 = load i32* %31, align 4		; <i32> [#uses=1]
+	%33 = load i32, i32* %31, align 4		; <i32> [#uses=1]
 	%34 = icmp eq i32 %33, 0		; <i1> [#uses=1]
 	br i1 %34, label %bb96, label %bb9
 
 bb9:		; preds = %bb8.fragment
 	%Opq.sa.calc482 = xor i32 %Opq.sa.calc765, 163		; <i32> [#uses=0]
-	%35 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
-	%36 = getelementptr %struct.ImageParameters* %35, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
-	%37 = load %struct.Macroblock** %36, align 8		; <%struct.Macroblock*> [#uses=1]
-	%38 = load i32* %.SV76.phi, align 4		; <i32> [#uses=1]
+	%35 = load %struct.ImageParameters*, %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%36 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %35, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%37 = load %struct.Macroblock*, %struct.Macroblock** %36, align 8		; <%struct.Macroblock*> [#uses=1]
+	%38 = load i32, i32* %.SV76.phi, align 4		; <i32> [#uses=1]
 	br label %bb9.fragment
 
 bb9.fragment:		; preds = %bb9
 	%Opq.sa.calc999 = add i32 %Opq.sa.calc765, -44		; <i32> [#uses=1]
 	%39 = sext i32 %38 to i64		; <i64> [#uses=1]
-	%40 = getelementptr %struct.Macroblock* %37, i64 %39, i32 20		; <i32*> [#uses=1]
-	%41 = load i32* %40, align 4		; <i32> [#uses=1]
+	%40 = getelementptr %struct.Macroblock, %struct.Macroblock* %37, i64 %39, i32 20		; <i32*> [#uses=1]
+	%41 = load i32, i32* %40, align 4		; <i32> [#uses=1]
 	%42 = icmp eq i32 %41, 0		; <i1> [#uses=1]
 	br i1 %42, label %bb96, label %bb11
 
@@ -156,42 +156,42 @@ bb13:		; preds = %bb5.fragment
 	%Opq.sa.calc490 = xor i32 %Opq.sa.calc873, 175		; <i32> [#uses=1]
 	%Opq.sa.calc488 = sub i32 %Opq.sa.calc490, %Opq.sa.calc873		; <i32> [#uses=1]
 	%Opq.sa.calc489 = sub i32 %Opq.sa.calc488, 133		; <i32> [#uses=1]
-	%46 = getelementptr %struct.Macroblock* %2, i64 %3, i32 25		; <i32*> [#uses=1]
+	%46 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 25		; <i32*> [#uses=1]
 	br label %meshBB360
 
 bb13.fragment:		; preds = %meshBB360
 	%Opq.sa.calc870 = add i32 %Opq.sa.calc866, -129		; <i32> [#uses=3]
-	%47 = load i32* %.SV208.phi, align 8		; <i32> [#uses=3]
+	%47 = load i32, i32* %.SV208.phi, align 8		; <i32> [#uses=3]
 	br i1 %.load74.SV.phi, label %bb14, label %meshBB412
 
 bb14:		; preds = %bb13.fragment
 	%Opq.sa.calc493 = add i32 %Opq.sa.calc870, 103		; <i32> [#uses=1]
-	%48 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=2]
+	%48 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=2]
 	store i32 %47, i32* %48, align 4
-	%49 = getelementptr %struct.Macroblock* %2, i64 %3, i32 29		; <i32*> [#uses=2]
+	%49 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 29		; <i32*> [#uses=2]
 	br label %bb14.fragment
 
 bb14.fragment:		; preds = %bb14
 	%Opq.sa.calc723 = sub i32 %Opq.sa.calc493, 117		; <i32> [#uses=4]
-	%50 = load i32* %49, align 8		; <i32> [#uses=4]
+	%50 = load i32, i32* %49, align 8		; <i32> [#uses=4]
 	store i32 %50, i32* %.SV52.phi1113, align 4
-	%51 = load i32* %49, align 8		; <i32> [#uses=1]
+	%51 = load i32, i32* %49, align 8		; <i32> [#uses=1]
 	%52 = icmp eq i32 %51, 0		; <i1> [#uses=1]
 	br i1 %52, label %meshBB, label %bb15
 
 bb15:		; preds = %bb14.fragment
 	%Opq.sa.calc496 = sub i32 %Opq.sa.calc723, -8		; <i32> [#uses=1]
-	%53 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
-	%54 = getelementptr %struct.ImageParameters* %53, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
-	%55 = load %struct.Macroblock** %54, align 8		; <%struct.Macroblock*> [#uses=1]
-	%56 = load i32* %.SV208.phi, align 8		; <i32> [#uses=1]
+	%53 = load %struct.ImageParameters*, %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%54 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %53, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%55 = load %struct.Macroblock*, %struct.Macroblock** %54, align 8		; <%struct.Macroblock*> [#uses=1]
+	%56 = load i32, i32* %.SV208.phi, align 8		; <i32> [#uses=1]
 	br label %meshBB324
 
 bb15.fragment:		; preds = %meshBB324
 	%Opq.sa.calc925 = xor i32 %Opq.sa.calc750, 215		; <i32> [#uses=2]
 	%57 = sext i32 %.SV214.phi to i64		; <i64> [#uses=1]
-	%58 = getelementptr %struct.Macroblock* %.SV212.phi, i64 %57, i32 20		; <i32*> [#uses=1]
-	%59 = load i32* %58, align 4		; <i32> [#uses=1]
+	%58 = getelementptr %struct.Macroblock, %struct.Macroblock* %.SV212.phi, i64 %57, i32 20		; <i32*> [#uses=1]
+	%59 = load i32, i32* %58, align 4		; <i32> [#uses=1]
 	%60 = icmp eq i32 %59, 0		; <i1> [#uses=1]
 	br i1 %60, label %bb16, label %bb96
 
@@ -209,14 +209,14 @@ bb16.fragment:		; preds = %bb16
 bb19:		; preds = %meshBB412
 	%Opq.sa.calc502 = sub i32 %Opq.sa.calc932, -94		; <i32> [#uses=0]
 	%63 = add i32 %.SV87.phi1030, 1		; <i32> [#uses=1]
-	%64 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	%64 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
 	br label %bb19.fragment
 
 bb19.fragment:		; preds = %bb19
 	%Opq.sa.calc880 = xor i32 %Opq.sa.calc932, 246		; <i32> [#uses=0]
 	store i32 %63, i32* %64, align 4
-	%65 = getelementptr %struct.Macroblock* %2, i64 %3, i32 29		; <i32*> [#uses=1]
-	%66 = load i32* %65, align 8		; <i32> [#uses=2]
+	%65 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 29		; <i32*> [#uses=1]
+	%66 = load i32, i32* %65, align 8		; <i32> [#uses=2]
 	store i32 %66, i32* %.SV52.phi1186, align 4
 	br label %bb96
 
@@ -227,8 +227,8 @@ bb21:		; preds = %meshBB392
 bb23:		; preds = %meshBB360
 	%Opq.sa.calc509 = xor i32 %Opq.sa.calc866, 70		; <i32> [#uses=1]
 	%Opq.sa.calc508 = sub i32 %Opq.sa.calc509, -19		; <i32> [#uses=0]
-	%67 = getelementptr %struct.Macroblock* %2, i64 %3, i32 20		; <i32*> [#uses=1]
-	%68 = load i32* %67, align 4		; <i32> [#uses=1]
+	%67 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 20		; <i32*> [#uses=1]
+	%68 = load i32, i32* %67, align 4		; <i32> [#uses=1]
 	%69 = icmp eq i32 %68, 0		; <i1> [#uses=1]
 	%70 = and i32 %curr_mb_nr, 1		; <i32> [#uses=1]
 	%71 = icmp eq i32 %70, 0		; <i1> [#uses=2]
@@ -236,9 +236,9 @@ bb23:		; preds = %meshBB360
 
 bb23.fragment:		; preds = %bb23
 	%Opq.sa.calc847 = sub i32 %Opq.sa.calc866, -9		; <i32> [#uses=2]
-	%72 = getelementptr %struct.Macroblock* %2, i64 %3, i32 22		; <i32*> [#uses=3]
-	%73 = load i32* %72, align 4		; <i32> [#uses=3]
-	%74 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=3]
+	%72 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 22		; <i32*> [#uses=3]
+	%73 = load i32, i32* %72, align 4		; <i32> [#uses=3]
+	%74 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=3]
 	store i32 %73, i32* %74, align 4
 	br label %bb23.fragment182
 
@@ -246,10 +246,10 @@ bb23.fragment182:		; preds = %bb23.fragment
 	%Opq.sa.calc744 = xor i32 %Opq.sa.calc847, 152		; <i32> [#uses=4]
 	%Opq.sa.calc742 = add i32 %Opq.sa.calc744, %Opq.sa.calc847		; <i32> [#uses=1]
 	%Opq.sa.calc743 = add i32 %Opq.sa.calc742, -149		; <i32> [#uses=2]
-	%75 = getelementptr %struct.Macroblock* %2, i64 %3, i32 26		; <i32*> [#uses=2]
-	%76 = load i32* %75, align 4		; <i32> [#uses=3]
+	%75 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 26		; <i32*> [#uses=2]
+	%76 = load i32, i32* %75, align 4		; <i32> [#uses=3]
 	store i32 %76, i32* %.SV52.phi1113, align 4
-	%77 = load i32* %75, align 4		; <i32> [#uses=1]
+	%77 = load i32, i32* %75, align 4		; <i32> [#uses=1]
 	%78 = icmp ne i32 %77, 0		; <i1> [#uses=2]
 	br i1 %69, label %meshBB344, label %meshBB432
 
@@ -264,10 +264,10 @@ bb25:		; preds = %bb24
 bb26:		; preds = %bb25
 	%Opq.sa.calc519 = xor i32 %Opq.sa.calc515, 23		; <i32> [#uses=2]
 	%Opq.sa.calc518 = xor i32 %Opq.sa.calc519, 84		; <i32> [#uses=1]
-	%79 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
-	%80 = getelementptr %struct.ImageParameters* %79, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
-	%81 = load %struct.Macroblock** %80, align 8		; <%struct.Macroblock*> [#uses=1]
-	%82 = load i32* %.SV99.phi, align 4		; <i32> [#uses=1]
+	%79 = load %struct.ImageParameters*, %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%80 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %79, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%81 = load %struct.Macroblock*, %struct.Macroblock** %80, align 8		; <%struct.Macroblock*> [#uses=1]
+	%82 = load i32, i32* %.SV99.phi, align 4		; <i32> [#uses=1]
 	br label %meshBB340
 
 bb26.fragment:		; preds = %meshBB340
@@ -275,8 +275,8 @@ bb26.fragment:		; preds = %meshBB340
 	%Opq.sa.calc916 = add i32 %Opq.sa.calc918, %Opq.sa.calc754		; <i32> [#uses=1]
 	%Opq.sa.calc917 = add i32 %Opq.sa.calc916, -237		; <i32> [#uses=1]
 	%83 = sext i32 %.SV230.phi to i64		; <i64> [#uses=1]
-	%84 = getelementptr %struct.Macroblock* %.SV228.phi, i64 %83, i32 20		; <i32*> [#uses=1]
-	%85 = load i32* %84, align 4		; <i32> [#uses=1]
+	%84 = getelementptr %struct.Macroblock, %struct.Macroblock* %.SV228.phi, i64 %83, i32 20		; <i32*> [#uses=1]
+	%85 = load i32, i32* %84, align 4		; <i32> [#uses=1]
 	%86 = icmp eq i32 %85, 0		; <i1> [#uses=1]
 	br i1 %86, label %meshBB420, label %meshBB356
 
@@ -308,17 +308,17 @@ bb32:		; preds = %bb24
 
 bb33:		; preds = %bb32
 	%Opq.sa.calc534 = sub i32 %Opq.sa.calc512, -75		; <i32> [#uses=2]
-	%92 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
-	%93 = getelementptr %struct.ImageParameters* %92, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
-	%94 = load %struct.Macroblock** %93, align 8		; <%struct.Macroblock*> [#uses=1]
-	%95 = load i32* %.SV99.phi, align 4		; <i32> [#uses=1]
+	%92 = load %struct.ImageParameters*, %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%93 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %92, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%94 = load %struct.Macroblock*, %struct.Macroblock** %93, align 8		; <%struct.Macroblock*> [#uses=1]
+	%95 = load i32, i32* %.SV99.phi, align 4		; <i32> [#uses=1]
 	br label %bb33.fragment
 
 bb33.fragment:		; preds = %bb33
 	%Opq.sa.calc712 = add i32 %Opq.sa.calc534, -109		; <i32> [#uses=3]
 	%96 = sext i32 %95 to i64		; <i64> [#uses=1]
-	%97 = getelementptr %struct.Macroblock* %94, i64 %96, i32 20		; <i32*> [#uses=1]
-	%98 = load i32* %97, align 4		; <i32> [#uses=1]
+	%97 = getelementptr %struct.Macroblock, %struct.Macroblock* %94, i64 %96, i32 20		; <i32*> [#uses=1]
+	%98 = load i32, i32* %97, align 4		; <i32> [#uses=1]
 	%99 = icmp eq i32 %98, 0		; <i1> [#uses=1]
 	br i1 %99, label %bb34, label %meshBB
 
@@ -372,17 +372,17 @@ bb40:		; preds = %bb39
 
 bb41:		; preds = %meshBB336
 	%Opq.sa.calc557 = sub i32 %Opq.sa.calc979, 143		; <i32> [#uses=1]
-	%108 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
-	%109 = getelementptr %struct.ImageParameters* %108, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
-	%110 = load %struct.Macroblock** %109, align 8		; <%struct.Macroblock*> [#uses=1]
-	%111 = load i32* %.SV99.phi1128, align 4		; <i32> [#uses=1]
+	%108 = load %struct.ImageParameters*, %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%109 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %108, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%110 = load %struct.Macroblock*, %struct.Macroblock** %109, align 8		; <%struct.Macroblock*> [#uses=1]
+	%111 = load i32, i32* %.SV99.phi1128, align 4		; <i32> [#uses=1]
 	br label %bb41.fragment
 
 bb41.fragment:		; preds = %bb41
 	%Opq.sa.calc987 = xor i32 %Opq.sa.calc557, 213		; <i32> [#uses=4]
 	%112 = sext i32 %111 to i64		; <i64> [#uses=1]
-	%113 = getelementptr %struct.Macroblock* %110, i64 %112, i32 20		; <i32*> [#uses=1]
-	%114 = load i32* %113, align 4		; <i32> [#uses=1]
+	%113 = getelementptr %struct.Macroblock, %struct.Macroblock* %110, i64 %112, i32 20		; <i32*> [#uses=1]
+	%114 = load i32, i32* %113, align 4		; <i32> [#uses=1]
 	%115 = icmp eq i32 %114, 0		; <i1> [#uses=1]
 	br i1 %115, label %bb42, label %bb96
 
@@ -415,17 +415,17 @@ bb48:		; preds = %bb39
 
 bb49:		; preds = %bb48
 	%Opq.sa.calc572 = add i32 %Opq.sa.calc798, 84		; <i32> [#uses=0]
-	%122 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
-	%123 = getelementptr %struct.ImageParameters* %122, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
-	%124 = load %struct.Macroblock** %123, align 8		; <%struct.Macroblock*> [#uses=1]
-	%125 = load i32* %.SV99.phi1037, align 4		; <i32> [#uses=1]
+	%122 = load %struct.ImageParameters*, %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%123 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %122, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%124 = load %struct.Macroblock*, %struct.Macroblock** %123, align 8		; <%struct.Macroblock*> [#uses=1]
+	%125 = load i32, i32* %.SV99.phi1037, align 4		; <i32> [#uses=1]
 	br label %bb49.fragment
 
 bb49.fragment:		; preds = %bb49
 	%Opq.sa.calc860 = sub i32 %Opq.sa.calc569, 114		; <i32> [#uses=5]
 	%126 = sext i32 %125 to i64		; <i64> [#uses=1]
-	%127 = getelementptr %struct.Macroblock* %124, i64 %126, i32 20		; <i32*> [#uses=1]
-	%128 = load i32* %127, align 4		; <i32> [#uses=1]
+	%127 = getelementptr %struct.Macroblock, %struct.Macroblock* %124, i64 %126, i32 20		; <i32*> [#uses=1]
+	%128 = load i32, i32* %127, align 4		; <i32> [#uses=1]
 	%129 = icmp eq i32 %128, 0		; <i1> [#uses=1]
 	br i1 %129, label %bb50, label %meshBB380
 
@@ -484,8 +484,8 @@ bb58:		; preds = %bb56.fragment
 
 bb59:		; preds = %bb58
 	%Opq.sa.calc599 = add i32 %Opq.sa.calc1002, 151		; <i32> [#uses=0]
-	%141 = getelementptr %struct.Macroblock* %2, i64 %3, i32 20		; <i32*> [#uses=1]
-	%142 = load i32* %141, align 4		; <i32> [#uses=1]
+	%141 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 20		; <i32*> [#uses=1]
+	%142 = load i32, i32* %141, align 4		; <i32> [#uses=1]
 	br label %bb59.fragment
 
 bb59.fragment:		; preds = %bb59
@@ -501,40 +501,40 @@ bb60:		; preds = %bb59.fragment
 
 bb61:		; preds = %bb60
 	%Opq.sa.calc605 = xor i32 %Opq.sa.calc731, 57		; <i32> [#uses=1]
-	%146 = getelementptr %struct.Macroblock* %2, i64 %3, i32 23		; <i32*> [#uses=2]
-	%147 = load i32* %146, align 8		; <i32> [#uses=3]
-	%148 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=3]
+	%146 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 23		; <i32*> [#uses=2]
+	%147 = load i32, i32* %146, align 8		; <i32> [#uses=3]
+	%148 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=3]
 	br label %bb61.fragment
 
 bb61.fragment:		; preds = %bb61
 	%Opq.sa.calc700 = sub i32 %Opq.sa.calc605, 108		; <i32> [#uses=3]
 	store i32 %147, i32* %148, align 4
-	%149 = getelementptr %struct.Macroblock* %2, i64 %3, i32 27		; <i32*> [#uses=4]
-	%150 = load i32* %149, align 8		; <i32> [#uses=1]
+	%149 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 27		; <i32*> [#uses=4]
+	%150 = load i32, i32* %149, align 8		; <i32> [#uses=1]
 	%151 = icmp eq i32 %150, 0		; <i1> [#uses=1]
 	br i1 %151, label %bb65, label %bb62
 
 bb62:		; preds = %bb61.fragment
 	%Opq.sa.calc608 = add i32 %Opq.sa.calc700, -94		; <i32> [#uses=1]
-	%152 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=2]
-	%153 = getelementptr %struct.ImageParameters* %152, i64 0, i32 45		; <i32*> [#uses=1]
-	%154 = load i32* %153, align 4		; <i32> [#uses=1]
+	%152 = load %struct.ImageParameters*, %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=2]
+	%153 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %152, i64 0, i32 45		; <i32*> [#uses=1]
+	%154 = load i32, i32* %153, align 4		; <i32> [#uses=1]
 	%155 = icmp eq i32 %154, 1		; <i1> [#uses=1]
 	br i1 %155, label %bb63, label %bb64
 
 bb63:		; preds = %bb62
 	%Opq.sa.calc611 = add i32 %Opq.sa.calc700, -101		; <i32> [#uses=2]
-	%156 = getelementptr %struct.ImageParameters* %152, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
-	%157 = load %struct.Macroblock** %156, align 8		; <%struct.Macroblock*> [#uses=1]
-	%158 = load i32* %146, align 8		; <i32> [#uses=1]
+	%156 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %152, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%157 = load %struct.Macroblock*, %struct.Macroblock** %156, align 8		; <%struct.Macroblock*> [#uses=1]
+	%158 = load i32, i32* %146, align 8		; <i32> [#uses=1]
 	br label %meshBB452
 
 bb63.fragment:		; preds = %meshBB452
 	%Opq.sa.calc891 = add i32 %Opq.link.mask823, 18		; <i32> [#uses=2]
 	%Opq.sa.calc890 = add i32 %Opq.sa.calc891, -3		; <i32> [#uses=2]
 	%159 = sext i32 %.SV266.phi to i64		; <i64> [#uses=1]
-	%160 = getelementptr %struct.Macroblock* %.SV264.phi, i64 %159, i32 20		; <i32*> [#uses=1]
-	%161 = load i32* %160, align 4		; <i32> [#uses=1]
+	%160 = getelementptr %struct.Macroblock, %struct.Macroblock* %.SV264.phi, i64 %159, i32 20		; <i32*> [#uses=1]
+	%161 = load i32, i32* %160, align 4		; <i32> [#uses=1]
 	%162 = icmp eq i32 %161, 0		; <i1> [#uses=1]
 	br i1 %162, label %bb64, label %meshBB456
 
@@ -562,7 +562,7 @@ bb65:		; preds = %meshBB456, %bb64, %bb61.fragment
 	%Opq.link.SV618.phi = phi i32 [ %Opq.sa.calc816, %meshBB456 ], [ %Opq.sa.calc700, %bb61.fragment ], [ %Opq.sa.calc614, %bb64 ]		; <i32> [#uses=1]
 	%Opq.link.mask620 = and i32 %Opq.link.SV618.phi, 40		; <i32> [#uses=1]
 	%Opq.sa.calc617 = add i32 %Opq.link.mask620, -35		; <i32> [#uses=2]
-	%164 = load i32* %.SV152.phi1058, align 8		; <i32> [#uses=1]
+	%164 = load i32, i32* %.SV152.phi1058, align 8		; <i32> [#uses=1]
 	br label %meshBB436
 
 bb65.fragment:		; preds = %meshBB436
@@ -573,7 +573,7 @@ bb65.fragment:		; preds = %meshBB436
 bb66:		; preds = %bb60
 	%Opq.sa.calc621 = add i32 %Opq.sa.calc602, -217		; <i32> [#uses=1]
 	%165 = add i32 %curr_mb_nr, -1		; <i32> [#uses=1]
-	%166 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	%166 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
 	br label %meshBB420
 
 bb66.fragment:		; preds = %meshBB420
@@ -585,45 +585,45 @@ bb66.fragment:		; preds = %meshBB420
 
 bb68:		; preds = %bb59.fragment
 	%Opq.sa.calc624 = sub i32 %Opq.sa.calc731, 229		; <i32> [#uses=3]
-	%167 = getelementptr %struct.Macroblock* %2, i64 %3, i32 23		; <i32*> [#uses=1]
+	%167 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 23		; <i32*> [#uses=1]
 	br label %meshBB344
 
 bb68.fragment:		; preds = %meshBB344
 	%Opq.sa.calc784 = sub i32 %Opq.link.mask722, 3		; <i32> [#uses=5]
-	%168 = load i32* %.SV274.phi, align 8		; <i32> [#uses=3]
+	%168 = load i32, i32* %.SV274.phi, align 8		; <i32> [#uses=3]
 	br i1 %.load144.SV.phi, label %bb69, label %meshBB412
 
 bb69:		; preds = %bb68.fragment
 	%Opq.sa.calc627 = add i32 %Opq.sa.calc784, 163		; <i32> [#uses=0]
-	%169 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=2]
+	%169 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=2]
 	store i32 %168, i32* %169, align 4
-	%170 = getelementptr %struct.Macroblock* %2, i64 %3, i32 27		; <i32*> [#uses=2]
+	%170 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 27		; <i32*> [#uses=2]
 	br label %bb69.fragment
 
 bb69.fragment:		; preds = %bb69
 	%Opq.sa.calc996 = sub i32 %Opq.sa.calc784, -9		; <i32> [#uses=3]
 	%Opq.sa.calc994 = sub i32 %Opq.sa.calc996, %Opq.sa.calc784		; <i32> [#uses=1]
 	%Opq.sa.calc995 = sub i32 %Opq.sa.calc994, 3		; <i32> [#uses=2]
-	%171 = load i32* %170, align 8		; <i32> [#uses=3]
+	%171 = load i32, i32* %170, align 8		; <i32> [#uses=3]
 	store i32 %171, i32* %.SV52.phi1170, align 4
-	%172 = load i32* %170, align 8		; <i32> [#uses=1]
+	%172 = load i32, i32* %170, align 8		; <i32> [#uses=1]
 	%173 = icmp eq i32 %172, 0		; <i1> [#uses=1]
 	br i1 %173, label %meshBB396, label %meshBB400
 
 bb70:		; preds = %meshBB400
 	%Opq.sa.calc630 = add i32 %Opq.sa.calc824, -203		; <i32> [#uses=2]
-	%174 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
-	%175 = getelementptr %struct.ImageParameters* %174, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
-	%176 = load %struct.Macroblock** %175, align 8		; <%struct.Macroblock*> [#uses=1]
-	%177 = load i32* %.SV156.phi, align 8		; <i32> [#uses=1]
+	%174 = load %struct.ImageParameters*, %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%175 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %174, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%176 = load %struct.Macroblock*, %struct.Macroblock** %175, align 8		; <%struct.Macroblock*> [#uses=1]
+	%177 = load i32, i32* %.SV156.phi, align 8		; <i32> [#uses=1]
 	br label %meshBB428
 
 bb70.fragment:		; preds = %meshBB428
 	%Opq.sa.calc739 = xor i32 %Opq.sa.calc897, 213		; <i32> [#uses=2]
 	%Opq.sa.calc738 = sub i32 %Opq.sa.calc739, 1		; <i32> [#uses=2]
 	%178 = sext i32 %.SV280.phi to i64		; <i64> [#uses=1]
-	%179 = getelementptr %struct.Macroblock* %.SV278.phi, i64 %178, i32 20		; <i32*> [#uses=1]
-	%180 = load i32* %179, align 4		; <i32> [#uses=1]
+	%179 = getelementptr %struct.Macroblock, %struct.Macroblock* %.SV278.phi, i64 %178, i32 20		; <i32*> [#uses=1]
+	%180 = load i32, i32* %179, align 4		; <i32> [#uses=1]
 	%181 = icmp eq i32 %180, 0		; <i1> [#uses=1]
 	br i1 %181, label %meshBB452, label %meshBB356
 
@@ -641,14 +641,14 @@ bb71.fragment:		; preds = %meshBB352
 bb74:		; preds = %meshBB412
 	%Opq.sa.calc636 = xor i32 %Opq.sa.calc932, 233		; <i32> [#uses=1]
 	%184 = add i32 %.SV158.phi1063, 1		; <i32> [#uses=1]
-	%185 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	%185 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
 	br label %bb74.fragment
 
 bb74.fragment:		; preds = %bb74
 	%Opq.sa.calc1011 = sub i32 %Opq.sa.calc636, -19		; <i32> [#uses=0]
 	store i32 %184, i32* %185, align 4
-	%186 = getelementptr %struct.Macroblock* %2, i64 %3, i32 27		; <i32*> [#uses=1]
-	%187 = load i32* %186, align 8		; <i32> [#uses=2]
+	%186 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 27		; <i32*> [#uses=1]
+	%187 = load i32, i32* %186, align 8		; <i32> [#uses=2]
 	store i32 %187, i32* %.SV52.phi1186, align 4
 	br label %bb96
 
@@ -660,23 +660,23 @@ bb76:		; preds = %bb58
 
 bb77:		; preds = %bb76
 	%Opq.sa.calc643 = add i32 %Opq.sa.calc640, 2		; <i32> [#uses=2]
-	%189 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
-	%190 = getelementptr %struct.ImageParameters* %189, i64 0, i32 45		; <i32*> [#uses=1]
-	%191 = load i32* %190, align 4		; <i32> [#uses=1]
+	%189 = load %struct.ImageParameters*, %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%190 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %189, i64 0, i32 45		; <i32*> [#uses=1]
+	%191 = load i32, i32* %190, align 4		; <i32> [#uses=1]
 	%192 = icmp eq i32 %191, 2		; <i1> [#uses=1]
 	br i1 %192, label %meshBB416, label %bb79
 
 bb78:		; preds = %meshBB416
 	%Opq.sa.calc647 = xor i32 %Opq.sa.calc971, 25		; <i32> [#uses=2]
 	%Opq.sa.calc646 = sub i32 %Opq.sa.calc647, 29		; <i32> [#uses=0]
-	%193 = getelementptr %struct.Macroblock* %2, i64 %3, i32 23		; <i32*> [#uses=1]
-	%194 = load i32* %193, align 8		; <i32> [#uses=1]
+	%193 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 23		; <i32*> [#uses=1]
+	%194 = load i32, i32* %193, align 8		; <i32> [#uses=1]
 	%195 = add i32 %194, 1		; <i32> [#uses=1]
 	br label %bb78.fragment
 
 bb78.fragment:		; preds = %bb78
 	%Opq.sa.calc850 = sub i32 %Opq.sa.calc647, -93		; <i32> [#uses=0]
-	%196 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	%196 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
 	store i32 %195, i32* %196, align 4
 	store i32 1, i32* %.SV52.phi1200, align 4
 	%197 = add i32 %yN, -1		; <i32> [#uses=1]
@@ -691,7 +691,7 @@ bb79:		; preds = %bb77, %bb76
 
 bb81:		; preds = %meshBB456
 	%Opq.sa.calc655 = add i32 %Opq.sa.calc816, 56		; <i32> [#uses=0]
-	%198 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	%198 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
 	store i32 %curr_mb_nr, i32* %198, align 4
 	store i32 1, i32* %.SV52.phi1136, align 4
 	br label %bb98
@@ -702,8 +702,8 @@ bb83:		; preds = %bb56.fragment
 
 bb84:		; preds = %bb83
 	%Opq.sa.calc661 = xor i32 %Opq.sa.calc658, 22		; <i32> [#uses=1]
-	%199 = getelementptr %struct.Macroblock* %2, i64 %3, i32 20		; <i32*> [#uses=1]
-	%200 = load i32* %199, align 4		; <i32> [#uses=1]
+	%199 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 20		; <i32*> [#uses=1]
+	%200 = load i32, i32* %199, align 4		; <i32> [#uses=1]
 	br label %meshBB400
 
 bb84.fragment:		; preds = %meshBB400
@@ -722,17 +722,17 @@ bb85:		; preds = %meshBB372
 
 bb86:		; preds = %meshBB336
 	%Opq.sa.calc670 = sub i32 %Opq.sa.calc979, 35		; <i32> [#uses=1]
-	%204 = getelementptr %struct.Macroblock* %2, i64 %3, i32 24		; <i32*> [#uses=1]
-	%205 = load i32* %204, align 4		; <i32> [#uses=1]
+	%204 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 24		; <i32*> [#uses=1]
+	%205 = load i32, i32* %204, align 4		; <i32> [#uses=1]
 	%206 = add i32 %205, 1		; <i32> [#uses=1]
-	%207 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	%207 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
 	br label %bb86.fragment
 
 bb86.fragment:		; preds = %bb86
 	%Opq.sa.calc943 = xor i32 %Opq.sa.calc670, 123		; <i32> [#uses=2]
 	store i32 %206, i32* %207, align 4
-	%208 = getelementptr %struct.Macroblock* %2, i64 %3, i32 28		; <i32*> [#uses=1]
-	%209 = load i32* %208, align 4		; <i32> [#uses=2]
+	%208 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 28		; <i32*> [#uses=1]
+	%209 = load i32, i32* %208, align 4		; <i32> [#uses=2]
 	store i32 %209, i32* %.SV52.phi1234, align 4
 	br label %meshBB424
 
@@ -744,43 +744,43 @@ bb87:		; preds = %meshBB440
 
 bb89:		; preds = %bb84.fragment
 	%Opq.sa.calc677 = sub i32 %Opq.sa.calc802, -183		; <i32> [#uses=1]
-	%210 = getelementptr %struct.Macroblock* %2, i64 %3, i32 24		; <i32*> [#uses=2]
+	%210 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 24		; <i32*> [#uses=2]
 	br label %bb89.fragment
 
 bb89.fragment:		; preds = %bb89
 	%Opq.sa.calc962 = add i32 %Opq.sa.calc677, -188		; <i32> [#uses=3]
-	%211 = load i32* %210, align 4		; <i32> [#uses=3]
+	%211 = load i32, i32* %210, align 4		; <i32> [#uses=3]
 	br i1 %203, label %bb90, label %meshBB408
 
 bb90:		; preds = %bb89.fragment
 	%Opq.sa.calc680 = xor i32 %Opq.sa.calc962, 92		; <i32> [#uses=1]
-	%212 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=2]
+	%212 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=2]
 	store i32 %211, i32* %212, align 4
-	%213 = getelementptr %struct.Macroblock* %2, i64 %3, i32 28		; <i32*> [#uses=2]
+	%213 = getelementptr %struct.Macroblock, %struct.Macroblock* %2, i64 %3, i32 28		; <i32*> [#uses=2]
 	br label %bb90.fragment
 
 bb90.fragment:		; preds = %bb90
 	%Opq.sa.calc773 = sub i32 %Opq.sa.calc680, 60		; <i32> [#uses=3]
 	%Opq.sa.calc772 = add i32 %Opq.sa.calc773, -25		; <i32> [#uses=2]
-	%214 = load i32* %213, align 4		; <i32> [#uses=3]
+	%214 = load i32, i32* %213, align 4		; <i32> [#uses=3]
 	store i32 %214, i32* %.SV52.phi1190, align 4
-	%215 = load i32* %213, align 4		; <i32> [#uses=1]
+	%215 = load i32, i32* %213, align 4		; <i32> [#uses=1]
 	%216 = icmp eq i32 %215, 0		; <i1> [#uses=1]
 	br i1 %216, label %meshBB416, label %meshBB368
 
 bb91:		; preds = %meshBB368
 	%Opq.sa.calc683 = sub i32 %Opq.sa.calc768, -7		; <i32> [#uses=0]
-	%217 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
-	%218 = getelementptr %struct.ImageParameters* %217, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
-	%219 = load %struct.Macroblock** %218, align 8		; <%struct.Macroblock*> [#uses=1]
-	%220 = load i32* %.SV170.phi, align 4		; <i32> [#uses=1]
+	%217 = load %struct.ImageParameters*, %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%218 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %217, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%219 = load %struct.Macroblock*, %struct.Macroblock** %218, align 8		; <%struct.Macroblock*> [#uses=1]
+	%220 = load i32, i32* %.SV170.phi, align 4		; <i32> [#uses=1]
 	br label %bb91.fragment
 
 bb91.fragment:		; preds = %bb91
 	%Opq.sa.calc853 = xor i32 %Opq.sa.calc768, 8		; <i32> [#uses=1]
 	%221 = sext i32 %220 to i64		; <i64> [#uses=1]
-	%222 = getelementptr %struct.Macroblock* %219, i64 %221, i32 20		; <i32*> [#uses=1]
-	%223 = load i32* %222, align 4		; <i32> [#uses=1]
+	%222 = getelementptr %struct.Macroblock, %struct.Macroblock* %219, i64 %221, i32 20		; <i32*> [#uses=1]
+	%223 = load i32, i32* %222, align 4		; <i32> [#uses=1]
 	%224 = icmp eq i32 %223, 0		; <i1> [#uses=1]
 	br i1 %224, label %bb92, label %bb96
 
@@ -798,14 +798,14 @@ bb92.fragment:		; preds = %bb92
 bb95:		; preds = %meshBB408
 	%Opq.sa.calc689 = xor i32 %Opq.sa.calc912, 207		; <i32> [#uses=3]
 	%227 = add i32 %.SV172.phi1074, 1		; <i32> [#uses=1]
-	%228 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	%228 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
 	br label %meshBB384
 
 bb95.fragment:		; preds = %meshBB384
 	%Opq.sa.calc841 = sub i32 %Opq.sa.calc901, 76		; <i32> [#uses=0]
 	store i32 %.SV306.phi, i32* %.SV308.phi, align 4
-	%229 = getelementptr %struct.Macroblock* %.load.SV.phi, i64 %.load20.SV.phi, i32 28		; <i32*> [#uses=1]
-	%230 = load i32* %229, align 4		; <i32> [#uses=2]
+	%229 = getelementptr %struct.Macroblock, %struct.Macroblock* %.load.SV.phi, i64 %.load20.SV.phi, i32 28		; <i32*> [#uses=1]
+	%230 = load i32, i32* %229, align 4		; <i32> [#uses=2]
 	store i32 %230, i32* %.load53.SV.phi, align 4
 	br label %bb96
 
@@ -826,13 +826,13 @@ bb97:		; preds = %meshBB424, %meshBB408, %meshBB352, %bb96, %bb21
 	%.SV70.phi1148 = phi i32 [ %.SV70.phi1195, %meshBB424 ], [ %.SV70.phi1215, %meshBB408 ], [ %.SV70.phi1138, %meshBB352 ], [ %.SV70.phi1085, %bb96 ], [ %.SV70.phi1027, %bb21 ]		; <i32> [#uses=1]
 	%yM.0.reg2mem.0.SV.phi = phi i32 [ -1, %meshBB424 ], [ -1, %meshBB408 ], [ -1, %meshBB352 ], [ %yM.0.SV.phi, %bb96 ], [ -1, %bb21 ]		; <i32> [#uses=1]
 	%Opq.sa.calc694 = xor i32 0, 243		; <i32> [#uses=1]
-	%232 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
-	%233 = getelementptr %struct.ImageParameters* %232, i64 0, i32 45		; <i32*> [#uses=1]
+	%232 = load %struct.ImageParameters*, %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%233 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %232, i64 0, i32 45		; <i32*> [#uses=1]
 	br label %bb97.fragment
 
 bb97.fragment:		; preds = %bb97
 	%Opq.sa.calc928 = xor i32 %Opq.sa.calc694, 128		; <i32> [#uses=1]
-	%234 = load i32* %233, align 4		; <i32> [#uses=1]
+	%234 = load i32, i32* %233, align 4		; <i32> [#uses=1]
 	%235 = icmp eq i32 %234, 0		; <i1> [#uses=1]
 	br i1 %235, label %return, label %bb98
 
@@ -843,25 +843,25 @@ bb98:		; preds = %meshBB444, %meshBB404, %bb97.fragment, %bb81, %bb78.fragment
 	%yM.0.reg2mem.1.SV.phi1068 = phi i32 [ %yN, %meshBB444 ], [ %yM.0.reg2mem.1.SV.phi1077, %meshBB404 ], [ %yM.0.reg2mem.0.SV.phi, %bb97.fragment ], [ %yN, %bb81 ], [ %197, %bb78.fragment ]		; <i32> [#uses=1]
 	%Opq.sa.calc695 = xor i32 0, 23		; <i32> [#uses=2]
 	%236 = and i32 %.SV70.phi1091, %xN		; <i32> [#uses=1]
-	%237 = getelementptr %struct.PixelPos* %pix, i64 0, i32 2		; <i32*> [#uses=2]
+	%237 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 2		; <i32*> [#uses=2]
 	store i32 %236, i32* %237, align 4
 	%238 = and i32 %yM.0.reg2mem.1.SV.phi1068, %.SV68.phi1092		; <i32> [#uses=1]
-	%239 = getelementptr %struct.PixelPos* %pix, i64 0, i32 3		; <i32*> [#uses=2]
+	%239 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 3		; <i32*> [#uses=2]
 	store i32 %238, i32* %239, align 4
-	%240 = getelementptr %struct.PixelPos* %pix, i64 0, i32 5		; <i32*> [#uses=1]
+	%240 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 5		; <i32*> [#uses=1]
 	br label %meshBB376
 
 bb98.fragment:		; preds = %meshBB376
 	%Opq.sa.calc1008 = sub i32 %Opq.link.mask911, 13		; <i32> [#uses=1]
-	%241 = getelementptr %struct.PixelPos* %pix, i64 0, i32 4		; <i32*> [#uses=4]
-	%242 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
-	%243 = load i32* %242, align 4		; <i32> [#uses=1]
-	%244 = load void (i32, i32*, i32*)** @get_mb_block_pos, align 8		; <void (i32, i32*, i32*)*> [#uses=1]
+	%241 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 4		; <i32*> [#uses=4]
+	%242 = getelementptr %struct.PixelPos, %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	%243 = load i32, i32* %242, align 4		; <i32> [#uses=1]
+	%244 = load void (i32, i32*, i32*)*, void (i32, i32*, i32*)** @get_mb_block_pos, align 8		; <void (i32, i32*, i32*)*> [#uses=1]
 	tail call void %244(i32 %243, i32* %241, i32* %.SV317.phi) nounwind
-	%245 = load i32* %241, align 4		; <i32> [#uses=1]
-	%246 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
-	%247 = getelementptr %struct.ImageParameters* %246, i64 0, i32 119, i64 %.load39.SV.phi, i64 0		; <i32*> [#uses=1]
-	%248 = load i32* %247, align 4		; <i32> [#uses=1]
+	%245 = load i32, i32* %241, align 4		; <i32> [#uses=1]
+	%246 = load %struct.ImageParameters*, %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%247 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %246, i64 0, i32 119, i64 %.load39.SV.phi, i64 0		; <i32*> [#uses=1]
+	%248 = load i32, i32* %247, align 4		; <i32> [#uses=1]
 	%249 = mul i32 %248, %245		; <i32> [#uses=2]
 	store i32 %249, i32* %241, align 4
 	br label %bb98.fragment183
@@ -869,15 +869,15 @@ bb98.fragment:		; preds = %meshBB376
 bb98.fragment183:		; preds = %bb98.fragment
 	%Opq.sa.calc777 = sub i32 %Opq.sa.calc1008, -158		; <i32> [#uses=1]
 	%Opq.sa.calc776 = sub i32 %Opq.sa.calc777, 46		; <i32> [#uses=0]
-	%250 = load i32* %.SV317.phi, align 4		; <i32> [#uses=1]
-	%251 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
-	%252 = getelementptr %struct.ImageParameters* %251, i64 0, i32 119, i64 %.load39.SV.phi, i64 1		; <i32*> [#uses=1]
-	%253 = load i32* %252, align 4		; <i32> [#uses=1]
+	%250 = load i32, i32* %.SV317.phi, align 4		; <i32> [#uses=1]
+	%251 = load %struct.ImageParameters*, %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%252 = getelementptr %struct.ImageParameters, %struct.ImageParameters* %251, i64 0, i32 119, i64 %.load39.SV.phi, i64 1		; <i32*> [#uses=1]
+	%253 = load i32, i32* %252, align 4		; <i32> [#uses=1]
 	%254 = mul i32 %253, %250		; <i32> [#uses=1]
-	%255 = load i32* %.SV313.phi, align 4		; <i32> [#uses=1]
+	%255 = load i32, i32* %.SV313.phi, align 4		; <i32> [#uses=1]
 	%256 = add i32 %255, %249		; <i32> [#uses=1]
 	store i32 %256, i32* %241, align 4
-	%257 = load i32* %.SV315.phi, align 4		; <i32> [#uses=1]
+	%257 = load i32, i32* %.SV315.phi, align 4		; <i32> [#uses=1]
 	%258 = add i32 %257, %254		; <i32> [#uses=1]
 	store i32 %258, i32* %.SV317.phi, align 4
 	ret void
diff --git a/test/CodeGen/X86/2009-04-29-IndirectDestOperands.ll b/test/CodeGen/X86/2009-04-29-IndirectDestOperands.ll
index a6ed74ba2ee9..5ddb5cae2966 100644
--- a/test/CodeGen/X86/2009-04-29-IndirectDestOperands.ll
+++ b/test/CodeGen/X86/2009-04-29-IndirectDestOperands.ll
@@ -4,18 +4,18 @@ target triple = "i386-apple-darwin9.0"
 
 define void @cpuid(i32* %data) nounwind {
 entry:
-	%arrayidx = getelementptr i32* %data, i32 1		; <i32*> [#uses=1]
-	%arrayidx2 = getelementptr i32* %data, i32 2		; <i32*> [#uses=1]
-	%arrayidx4 = getelementptr i32* %data, i32 3		; <i32*> [#uses=1]
-	%arrayidx6 = getelementptr i32* %data, i32 4		; <i32*> [#uses=1]
-	%arrayidx8 = getelementptr i32* %data, i32 5		; <i32*> [#uses=1]
-	%tmp9 = load i32* %arrayidx8		; <i32> [#uses=1]
-	%arrayidx11 = getelementptr i32* %data, i32 6		; <i32*> [#uses=1]
-	%tmp12 = load i32* %arrayidx11		; <i32> [#uses=1]
-	%arrayidx14 = getelementptr i32* %data, i32 7		; <i32*> [#uses=1]
-	%tmp15 = load i32* %arrayidx14		; <i32> [#uses=1]
-	%arrayidx17 = getelementptr i32* %data, i32 8		; <i32*> [#uses=1]
-	%tmp18 = load i32* %arrayidx17		; <i32> [#uses=1]
+	%arrayidx = getelementptr i32, i32* %data, i32 1		; <i32*> [#uses=1]
+	%arrayidx2 = getelementptr i32, i32* %data, i32 2		; <i32*> [#uses=1]
+	%arrayidx4 = getelementptr i32, i32* %data, i32 3		; <i32*> [#uses=1]
+	%arrayidx6 = getelementptr i32, i32* %data, i32 4		; <i32*> [#uses=1]
+	%arrayidx8 = getelementptr i32, i32* %data, i32 5		; <i32*> [#uses=1]
+	%tmp9 = load i32, i32* %arrayidx8		; <i32> [#uses=1]
+	%arrayidx11 = getelementptr i32, i32* %data, i32 6		; <i32*> [#uses=1]
+	%tmp12 = load i32, i32* %arrayidx11		; <i32> [#uses=1]
+	%arrayidx14 = getelementptr i32, i32* %data, i32 7		; <i32*> [#uses=1]
+	%tmp15 = load i32, i32* %arrayidx14		; <i32> [#uses=1]
+	%arrayidx17 = getelementptr i32, i32* %data, i32 8		; <i32*> [#uses=1]
+	%tmp18 = load i32, i32* %arrayidx17		; <i32> [#uses=1]
 	%0 = call i32 asm "cpuid", "={ax},=*{bx},=*{cx},=*{dx},{ax},{bx},{cx},{dx},~{dirflag},~{fpsr},~{flags}"(i32* %arrayidx2, i32* %arrayidx4, i32* %arrayidx6, i32 %tmp9, i32 %tmp12, i32 %tmp15, i32 %tmp18) nounwind		; <i32> [#uses=1]
 	store i32 %0, i32* %arrayidx
 	ret void
diff --git a/test/CodeGen/X86/2009-04-29-LinearScanBug.ll b/test/CodeGen/X86/2009-04-29-LinearScanBug.ll
index 2fbf7aa5ed1a..b4d202c168d6 100644
--- a/test/CodeGen/X86/2009-04-29-LinearScanBug.ll
+++ b/test/CodeGen/X86/2009-04-29-LinearScanBug.ll
@@ -105,17 +105,17 @@
 define fastcc i32 @pf_state_compare_ext_gwy(%struct.pf_state_key* nocapture %a, %struct.pf_state_key* nocapture %b) nounwind optsize ssp {
 entry:
 	%0 = zext i8 0 to i32		; <i32> [#uses=2]
-	%1 = load i8* null, align 1		; <i8> [#uses=2]
+	%1 = load i8, i8* null, align 1		; <i8> [#uses=2]
 	%2 = zext i8 %1 to i32		; <i32> [#uses=1]
 	%3 = sub i32 %0, %2		; <i32> [#uses=1]
 	%4 = icmp eq i8 0, %1		; <i1> [#uses=1]
 	br i1 %4, label %bb1, label %bb79
 
 bb1:		; preds = %entry
-	%5 = load i8* null, align 4		; <i8> [#uses=2]
+	%5 = load i8, i8* null, align 4		; <i8> [#uses=2]
 	%6 = zext i8 %5 to i32		; <i32> [#uses=2]
-	%7 = getelementptr %struct.pf_state_key* %b, i32 0, i32 3		; <i8*> [#uses=1]
-	%8 = load i8* %7, align 4		; <i8> [#uses=2]
+	%7 = getelementptr %struct.pf_state_key, %struct.pf_state_key* %b, i32 0, i32 3		; <i8*> [#uses=1]
+	%8 = load i8, i8* %7, align 4		; <i8> [#uses=2]
 	%9 = zext i8 %8 to i32		; <i32> [#uses=1]
 	%10 = sub i32 %6, %9		; <i32> [#uses=1]
 	%11 = icmp eq i8 %5, %8		; <i1> [#uses=1]
@@ -132,32 +132,32 @@ bb3:		; preds = %bb1
 	]
 
 bb4:		; preds = %bb3, %bb3
-	%12 = load i16* null, align 4		; <i16> [#uses=1]
+	%12 = load i16, i16* null, align 4		; <i16> [#uses=1]
 	%13 = zext i16 %12 to i32		; <i32> [#uses=1]
 	%14 = sub i32 0, %13		; <i32> [#uses=1]
 	br i1 false, label %bb23, label %bb79
 
 bb6:		; preds = %bb3
-	%15 = load i16* null, align 4		; <i16> [#uses=1]
+	%15 = load i16, i16* null, align 4		; <i16> [#uses=1]
 	%16 = zext i16 %15 to i32		; <i32> [#uses=1]
 	%17 = sub i32 0, %16		; <i32> [#uses=1]
 	ret i32 %17
 
 bb10:		; preds = %bb3
-	%18 = load i8* null, align 1		; <i8> [#uses=2]
+	%18 = load i8, i8* null, align 1		; <i8> [#uses=2]
 	%19 = zext i8 %18 to i32		; <i32> [#uses=1]
 	%20 = sub i32 0, %19		; <i32> [#uses=1]
 	%21 = icmp eq i8 0, %18		; <i1> [#uses=1]
 	br i1 %21, label %bb12, label %bb79
 
 bb12:		; preds = %bb10
-	%22 = load i16* null, align 4		; <i16> [#uses=1]
+	%22 = load i16, i16* null, align 4		; <i16> [#uses=1]
 	%23 = zext i16 %22 to i32		; <i32> [#uses=1]
 	%24 = sub i32 0, %23		; <i32> [#uses=1]
 	ret i32 %24
 
 bb17:		; preds = %bb3
-	%25 = load i8* null, align 1		; <i8> [#uses=2]
+	%25 = load i8, i8* null, align 1		; <i8> [#uses=2]
 	%26 = icmp eq i8 %25, 1		; <i1> [#uses=1]
 	br i1 %26, label %bb18, label %bb23
 
@@ -166,16 +166,16 @@ bb18:		; preds = %bb17
 	br i1 %27, label %bb19, label %bb23
 
 bb19:		; preds = %bb18
-	%28 = load i16* null, align 4		; <i16> [#uses=1]
+	%28 = load i16, i16* null, align 4		; <i16> [#uses=1]
 	%29 = zext i16 %28 to i32		; <i32> [#uses=1]
 	%30 = sub i32 0, %29		; <i32> [#uses=1]
 	br i1 false, label %bb23, label %bb79
 
 bb21:		; preds = %bb3
-	%31 = getelementptr %struct.pf_state_key* %a, i32 0, i32 1, i32 1, i32 0		; <i32*> [#uses=1]
-	%32 = load i32* %31, align 4		; <i32> [#uses=2]
-	%33 = getelementptr %struct.pf_state_key* %b, i32 0, i32 1, i32 1, i32 0		; <i32*> [#uses=1]
-	%34 = load i32* %33, align 4		; <i32> [#uses=2]
+	%31 = getelementptr %struct.pf_state_key, %struct.pf_state_key* %a, i32 0, i32 1, i32 1, i32 0		; <i32*> [#uses=1]
+	%32 = load i32, i32* %31, align 4		; <i32> [#uses=2]
+	%33 = getelementptr %struct.pf_state_key, %struct.pf_state_key* %b, i32 0, i32 1, i32 1, i32 0		; <i32*> [#uses=1]
+	%34 = load i32, i32* %33, align 4		; <i32> [#uses=2]
 	%35 = sub i32 %32, %34		; <i32> [#uses=1]
 	%36 = icmp eq i32 %32, %34		; <i1> [#uses=1]
 	br i1 %36, label %bb23, label %bb79
@@ -188,11 +188,11 @@ bb24:		; preds = %bb23
 	ret i32 1
 
 bb70:		; preds = %bb23
-	%37 = load i32 (%struct.pf_app_state*, %struct.pf_app_state*)** null, align 4		; <i32 (%struct.pf_app_state*, %struct.pf_app_state*)*> [#uses=3]
+	%37 = load i32 (%struct.pf_app_state*, %struct.pf_app_state*)*, i32 (%struct.pf_app_state*, %struct.pf_app_state*)** null, align 4		; <i32 (%struct.pf_app_state*, %struct.pf_app_state*)*> [#uses=3]
 	br i1 false, label %bb78, label %bb73
 
 bb73:		; preds = %bb70
-	%38 = load i32 (%struct.pf_app_state*, %struct.pf_app_state*)** null, align 4		; <i32 (%struct.pf_app_state*, %struct.pf_app_state*)*> [#uses=2]
+	%38 = load i32 (%struct.pf_app_state*, %struct.pf_app_state*)*, i32 (%struct.pf_app_state*, %struct.pf_app_state*)** null, align 4		; <i32 (%struct.pf_app_state*, %struct.pf_app_state*)*> [#uses=2]
 	%39 = icmp eq i32 (%struct.pf_app_state*, %struct.pf_app_state*)* %38, null		; <i1> [#uses=1]
 	br i1 %39, label %bb78, label %bb74
 
diff --git a/test/CodeGen/X86/2009-04-29-RegAllocAssert.ll b/test/CodeGen/X86/2009-04-29-RegAllocAssert.ll
index e803d6b56369..c291fede98eb 100644
--- a/test/CodeGen/X86/2009-04-29-RegAllocAssert.ll
+++ b/test/CodeGen/X86/2009-04-29-RegAllocAssert.ll
@@ -71,7 +71,7 @@
 
 define fastcc void @dropCell(%struct.MemPage* nocapture %pPage, i32 %idx, i32 %sz) nounwind ssp {
 entry:
-	%0 = load i8** null, align 8		; <i8*> [#uses=4]
+	%0 = load i8*, i8** null, align 8		; <i8*> [#uses=4]
 	%1 = or i32 0, 0		; <i32> [#uses=1]
 	%2 = icmp slt i32 %sz, 4		; <i1> [#uses=1]
 	%size_addr.0.i = select i1 %2, i32 4, i32 %sz		; <i32> [#uses=1]
@@ -83,18 +83,18 @@ bb3.i:		; preds = %bb3.i, %entry
 	br i1 %or.cond.i, label %bb5.i, label %bb3.i
 
 bb5.i:		; preds = %bb3.i
-	%4 = getelementptr i8* %0, i64 0		; <i8*> [#uses=1]
+	%4 = getelementptr i8, i8* %0, i64 0		; <i8*> [#uses=1]
 	store i8 0, i8* %4, align 1
-	%5 = getelementptr i8* %0, i64 0		; <i8*> [#uses=1]
+	%5 = getelementptr i8, i8* %0, i64 0		; <i8*> [#uses=1]
 	store i8 0, i8* %5, align 1
 	%6 = add i32 %1, 2		; <i32> [#uses=1]
 	%7 = zext i32 %6 to i64		; <i64> [#uses=2]
-	%8 = getelementptr i8* %0, i64 %7		; <i8*> [#uses=1]
+	%8 = getelementptr i8, i8* %0, i64 %7		; <i8*> [#uses=1]
 	%9 = lshr i32 %size_addr.0.i, 8		; <i32> [#uses=1]
 	%10 = trunc i32 %9 to i8		; <i8> [#uses=1]
 	store i8 %10, i8* %8, align 1
 	%.sum31.i = add i64 %7, 1		; <i64> [#uses=1]
-	%11 = getelementptr i8* %0, i64 %.sum31.i		; <i8*> [#uses=1]
+	%11 = getelementptr i8, i8* %0, i64 %.sum31.i		; <i8*> [#uses=1]
 	store i8 0, i8* %11, align 1
 	br label %bb11.outer.i
 
@@ -111,7 +111,7 @@ bb:		; preds = %bb12.i
 	br label %bb2
 
 bb2:		; preds = %bb, %bb12.i
-	%14 = getelementptr %struct.MemPage* %pPage, i64 0, i32 1		; <i8*> [#uses=1]
+	%14 = getelementptr %struct.MemPage, %struct.MemPage* %pPage, i64 0, i32 1		; <i8*> [#uses=1]
 	store i8 1, i8* %14, align 1
 	ret void
 }
diff --git a/test/CodeGen/X86/2009-04-scale.ll b/test/CodeGen/X86/2009-04-scale.ll
index e4c756cfdd44..1fc5f2b234fe 100644
--- a/test/CodeGen/X86/2009-04-scale.ll
+++ b/test/CodeGen/X86/2009-04-scale.ll
@@ -8,13 +8,13 @@
 
 define void @test() {
 entry:
-	%0 = load i32* null, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	%1 = lshr i32 %0, 8		; <i32> [#uses=1]
 	%2 = and i32 %1, 255		; <i32> [#uses=1]
-	%3 = getelementptr %struct.array* null, i32 0, i32 3		; <[256 x %struct.pair]*> [#uses=1]
-	%4 = getelementptr [256 x %struct.pair]* %3, i32 0, i32 %2		; <%struct.pair*> [#uses=1]
-	%5 = getelementptr %struct.pair* %4, i32 0, i32 1		; <i64*> [#uses=1]
-	%6 = load i64* %5, align 4		; <i64> [#uses=1]
+	%3 = getelementptr %struct.array, %struct.array* null, i32 0, i32 3		; <[256 x %struct.pair]*> [#uses=1]
+	%4 = getelementptr [256 x %struct.pair], [256 x %struct.pair]* %3, i32 0, i32 %2		; <%struct.pair*> [#uses=1]
+	%5 = getelementptr %struct.pair, %struct.pair* %4, i32 0, i32 1		; <i64*> [#uses=1]
+	%6 = load i64, i64* %5, align 4		; <i64> [#uses=1]
 	%7 = xor i64 0, %6		; <i64> [#uses=1]
 	%8 = xor i64 %7, 0		; <i64> [#uses=1]
 	%9 = xor i64 %8, 0		; <i64> [#uses=1]
diff --git a/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll b/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll
index fa240f64c300..dd073f09fd73 100644
--- a/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll
+++ b/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll
@@ -12,7 +12,7 @@ target triple = "i386-apple-darwin9.6"
 
 define void @x() nounwind {
 entry:
-	tail call void asm sideeffect "1: $0", "i,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr (%struct.pv_cpu_ops* @pv_cpu_ops, i32 0, i32 1, i32 1)) nounwind
+	tail call void asm sideeffect "1: $0", "i,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr (%struct.pv_cpu_ops, %struct.pv_cpu_ops* @pv_cpu_ops, i32 0, i32 1, i32 1)) nounwind
 	tail call void asm sideeffect "2: $0", "i,~{dirflag},~{fpsr},~{flags}"(i32* @G) nounwind
 	ret void
 }
diff --git a/test/CodeGen/X86/2009-05-11-tailmerge-crash.ll b/test/CodeGen/X86/2009-05-11-tailmerge-crash.ll
index c2cd89c33ee8..e9d15583e562 100644
--- a/test/CodeGen/X86/2009-05-11-tailmerge-crash.ll
+++ b/test/CodeGen/X86/2009-05-11-tailmerge-crash.ll
@@ -12,7 +12,7 @@ entry:
 	br label %bb
 
 bb:		; preds = %bb.i, %bb, %entry
-	%2 = load volatile i32* @g_9, align 4		; <i32> [#uses=2]
+	%2 = load volatile i32, i32* @g_9, align 4		; <i32> [#uses=2]
 	%3 = icmp sgt i32 %2, 1		; <i1> [#uses=1]
 	%4 = and i1 %3, %1		; <i1> [#uses=1]
 	br i1 %4, label %bb.i, label %bb
diff --git a/test/CodeGen/X86/2009-05-19-SingleElementExtractElement.ll b/test/CodeGen/X86/2009-05-19-SingleElementExtractElement.ll
index 6e062fb25089..89cd24d7dcfe 100644
--- a/test/CodeGen/X86/2009-05-19-SingleElementExtractElement.ll
+++ b/test/CodeGen/X86/2009-05-19-SingleElementExtractElement.ll
@@ -7,7 +7,7 @@ entry:
         %tmp5.i = extractelement <1 x i64> %a, i32 0
         %tmp11 = bitcast i64 %tmp5.i to <1 x i64>
         %tmp8 = extractelement <1 x i64> %tmp11, i32 0
-        %call6 = call i32 (i64)* @foo(i64 %tmp8)
+        %call6 = call i32 (i64) @foo(i64 %tmp8)
         ret i32 undef
 }
 
diff --git a/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll b/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll
index 1d1462075492..019d5dfb1fea 100644
--- a/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll
+++ b/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll
@@ -5,7 +5,7 @@ entry:
 	br label %bb14
 
 bb14:		; preds = %bb
-	%srcval16 = load i448* %P, align 8		; <i448> [#uses=1]
+	%srcval16 = load i448, i448* %P, align 8		; <i448> [#uses=1]
 	%tmp = zext i32 undef to i448		; <i448> [#uses=1]
 	%tmp15 = shl i448 %tmp, 288		; <i448> [#uses=1]
 	%mask = and i448 %srcval16, -2135987035423586845985235064014169866455883682256196619149693890381755748887481053010428711403521		; <i448> [#uses=1]
diff --git a/test/CodeGen/X86/2009-05-30-ISelBug.ll b/test/CodeGen/X86/2009-05-30-ISelBug.ll
index fe04272082c9..e01fe9f89308 100644
--- a/test/CodeGen/X86/2009-05-30-ISelBug.ll
+++ b/test/CodeGen/X86/2009-05-30-ISelBug.ll
@@ -13,14 +13,14 @@ bb35.i.backedge.exitStub:		; preds = %bb54.i
 
 bb54.i:		; preds = %newFuncRoot
 	%1 = zext i32 %.reload51 to i64		; <i64> [#uses=1]
-	%2 = getelementptr i32* %0, i64 %1		; <i32*> [#uses=1]
-	%3 = load i32* %2, align 4		; <i32> [#uses=2]
+	%2 = getelementptr i32, i32* %0, i64 %1		; <i32*> [#uses=1]
+	%3 = load i32, i32* %2, align 4		; <i32> [#uses=2]
 	%4 = lshr i32 %3, 8		; <i32> [#uses=1]
 	%5 = and i32 %3, 255		; <i32> [#uses=1]
 	%6 = add i32 %5, 4		; <i32> [#uses=1]
 	%7 = zext i32 %4 to i64		; <i64> [#uses=1]
-	%8 = getelementptr i32* %0, i64 %7		; <i32*> [#uses=1]
-	%9 = load i32* %8, align 4		; <i32> [#uses=2]
+	%8 = getelementptr i32, i32* %0, i64 %7		; <i32*> [#uses=1]
+	%9 = load i32, i32* %8, align 4		; <i32> [#uses=2]
 	%10 = and i32 %9, 255		; <i32> [#uses=1]
 	%11 = lshr i32 %9, 8		; <i32> [#uses=1]
 	%12 = add i32 %c_nblock_used.2.i, 5		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2009-06-02-RewriterBug.ll b/test/CodeGen/X86/2009-06-02-RewriterBug.ll
index 779f9857de7f..6ce7af632ee1 100644
--- a/test/CodeGen/X86/2009-06-02-RewriterBug.ll
+++ b/test/CodeGen/X86/2009-06-02-RewriterBug.ll
@@ -11,14 +11,14 @@ bb.nph:		; preds = %entry
 while.body:		; preds = %for.end, %bb.nph
 	%indvar2787 = phi i64 [ 0, %bb.nph ], [ %indvar.next2788, %for.end ]		; <i64> [#uses=2]
 	%tmp2791 = mul i64 %indvar2787, 44		; <i64> [#uses=0]
-	%ctg22996 = getelementptr i8* %in, i64 0		; <i8*> [#uses=1]
+	%ctg22996 = getelementptr i8, i8* %in, i64 0		; <i8*> [#uses=1]
 	%conv = zext i32 undef to i64		; <i64> [#uses=1]
 	%conv11 = zext i32 undef to i64		; <i64> [#uses=1]
-	%tmp18 = load i32* undef		; <i32> [#uses=1]
+	%tmp18 = load i32, i32* undef		; <i32> [#uses=1]
 	%conv19 = zext i32 %tmp18 to i64		; <i64> [#uses=1]
-	%tmp30 = load i32* undef		; <i32> [#uses=1]
+	%tmp30 = load i32, i32* undef		; <i32> [#uses=1]
 	%conv31 = zext i32 %tmp30 to i64		; <i64> [#uses=4]
-	%ptrincdec3065 = load i8* null		; <i8> [#uses=1]
+	%ptrincdec3065 = load i8, i8* null		; <i8> [#uses=1]
 	%conv442709 = zext i8 %ptrincdec3065 to i64		; <i64> [#uses=1]
 	%shl45 = shl i64 %conv442709, 16		; <i64> [#uses=1]
 	%conv632707 = zext i8 undef to i64		; <i64> [#uses=1]
@@ -68,10 +68,10 @@ while.body:		; preds = %for.end, %bb.nph
 	%add479 = add i64 %add473, %add441		; <i64> [#uses=3]
 	%conv4932682 = zext i8 undef to i64		; <i64> [#uses=1]
 	%shl494 = shl i64 %conv4932682, 16		; <i64> [#uses=1]
-	%ptrincdec4903012 = load i8* null		; <i8> [#uses=1]
+	%ptrincdec4903012 = load i8, i8* null		; <i8> [#uses=1]
 	%conv5032681 = zext i8 %ptrincdec4903012 to i64		; <i64> [#uses=1]
 	%shl504 = shl i64 %conv5032681, 8		; <i64> [#uses=1]
-	%ptrincdec5003009 = load i8* null		; <i8> [#uses=1]
+	%ptrincdec5003009 = load i8, i8* null		; <i8> [#uses=1]
 	%conv5132680 = zext i8 %ptrincdec5003009 to i64		; <i64> [#uses=1]
 	%or495 = or i64 %shl494, 0		; <i64> [#uses=1]
 	%or505 = or i64 %or495, %conv5132680		; <i64> [#uses=1]
@@ -91,10 +91,10 @@ while.body:		; preds = %for.end, %bb.nph
 	%xor575 = xor i64 %xor568, %or561		; <i64> [#uses=1]
 	%add587 = add i64 %xor575, 0		; <i64> [#uses=1]
 	%add593 = add i64 %add587, %add555		; <i64> [#uses=1]
-	%ptrincdec6043000 = load i8* null		; <i8> [#uses=1]
+	%ptrincdec6043000 = load i8, i8* null		; <i8> [#uses=1]
 	%conv6172676 = zext i8 %ptrincdec6043000 to i64		; <i64> [#uses=1]
 	%shl618 = shl i64 %conv6172676, 8		; <i64> [#uses=1]
-	%ptrincdec6142997 = load i8* %ctg22996		; <i8> [#uses=1]
+	%ptrincdec6142997 = load i8, i8* %ctg22996		; <i8> [#uses=1]
 	%conv6272675 = zext i8 %ptrincdec6142997 to i64		; <i64> [#uses=1]
 	%or619 = or i64 0, %conv6272675		; <i64> [#uses=1]
 	%or628 = or i64 %or619, %shl618		; <i64> [#uses=1]
@@ -106,7 +106,7 @@ while.body:		; preds = %for.end, %bb.nph
 	%xor700 = xor i64 0, %and699		; <i64> [#uses=1]
 	%add701 = add i64 0, %xor700		; <i64> [#uses=1]
 	%add707 = add i64 %add701, %add669		; <i64> [#uses=4]
-	%ptrincdec6242994 = load i8* null		; <i8> [#uses=1]
+	%ptrincdec6242994 = load i8, i8* null		; <i8> [#uses=1]
 	%conv7122673 = zext i8 %ptrincdec6242994 to i64		; <i64> [#uses=1]
 	%shl713 = shl i64 %conv7122673, 24		; <i64> [#uses=1]
 	%conv7412670 = zext i8 undef to i64		; <i64> [#uses=1]
@@ -132,7 +132,7 @@ while.body:		; preds = %for.end, %bb.nph
 	%add821 = add i64 %add815, %add783		; <i64> [#uses=1]
 	%add1160 = add i64 0, %add707		; <i64> [#uses=0]
 	%add1157 = add i64 undef, undef		; <i64> [#uses=0]
-	%ptrincdec11742940 = load i8* null		; <i8> [#uses=1]
+	%ptrincdec11742940 = load i8, i8* null		; <i8> [#uses=1]
 	%conv11872651 = zext i8 %ptrincdec11742940 to i64		; <i64> [#uses=1]
 	%shl1188 = shl i64 %conv11872651, 8		; <i64> [#uses=1]
 	%or1198 = or i64 0, %shl1188		; <i64> [#uses=1]
@@ -164,26 +164,26 @@ entry:
 	br i1 undef, label %while.end, label %bb.nph
 
 bb.nph:		; preds = %entry
-	%arrayidx5 = getelementptr i32* %arr, i64 1		; <i32*> [#uses=1]
-	%arrayidx9 = getelementptr i32* %arr, i64 2		; <i32*> [#uses=2]
-	%arrayidx13 = getelementptr i32* %arr, i64 3		; <i32*> [#uses=2]
-	%arrayidx25 = getelementptr i32* %arr, i64 6		; <i32*> [#uses=1]
-	%arrayidx29 = getelementptr i32* %arr, i64 7		; <i32*> [#uses=1]
+	%arrayidx5 = getelementptr i32, i32* %arr, i64 1		; <i32*> [#uses=1]
+	%arrayidx9 = getelementptr i32, i32* %arr, i64 2		; <i32*> [#uses=2]
+	%arrayidx13 = getelementptr i32, i32* %arr, i64 3		; <i32*> [#uses=2]
+	%arrayidx25 = getelementptr i32, i32* %arr, i64 6		; <i32*> [#uses=1]
+	%arrayidx29 = getelementptr i32, i32* %arr, i64 7		; <i32*> [#uses=1]
 	br label %while.body
 
 while.body:		; preds = %for.end, %bb.nph
-	%tmp3 = load i32* %arr		; <i32> [#uses=2]
+	%tmp3 = load i32, i32* %arr		; <i32> [#uses=2]
 	%conv = zext i32 %tmp3 to i64		; <i64> [#uses=1]
-	%tmp10 = load i32* %arrayidx9		; <i32> [#uses=1]
+	%tmp10 = load i32, i32* %arrayidx9		; <i32> [#uses=1]
 	%conv11 = zext i32 %tmp10 to i64		; <i64> [#uses=1]
-	%tmp14 = load i32* %arrayidx13		; <i32> [#uses=3]
+	%tmp14 = load i32, i32* %arrayidx13		; <i32> [#uses=3]
 	%conv15 = zext i32 %tmp14 to i64		; <i64> [#uses=2]
-	%tmp18 = load i32* undef		; <i32> [#uses=2]
+	%tmp18 = load i32, i32* undef		; <i32> [#uses=2]
 	%conv19 = zext i32 %tmp18 to i64		; <i64> [#uses=1]
 	%conv23 = zext i32 undef to i64		; <i64> [#uses=1]
-	%tmp26 = load i32* %arrayidx25		; <i32> [#uses=1]
+	%tmp26 = load i32, i32* %arrayidx25		; <i32> [#uses=1]
 	%conv27 = zext i32 %tmp26 to i64		; <i64> [#uses=1]
-	%tmp30 = load i32* %arrayidx29		; <i32> [#uses=2]
+	%tmp30 = load i32, i32* %arrayidx29		; <i32> [#uses=2]
 	%conv31 = zext i32 %tmp30 to i64		; <i64> [#uses=5]
 	%shl72 = shl i64 %conv31, 26		; <i64> [#uses=1]
 	%shr = lshr i64 %conv31, 6		; <i64> [#uses=1]
@@ -203,7 +203,7 @@ while.body:		; preds = %for.end, %bb.nph
 	%add137 = add i64 %add131, %add99		; <i64> [#uses=5]
 	%conv1422700 = zext i8 undef to i64		; <i64> [#uses=1]
 	%shl143 = shl i64 %conv1422700, 24		; <i64> [#uses=1]
-	%ptrincdec1393051 = load i8* undef		; <i8> [#uses=1]
+	%ptrincdec1393051 = load i8, i8* undef		; <i8> [#uses=1]
 	%conv1512699 = zext i8 %ptrincdec1393051 to i64		; <i64> [#uses=1]
 	%shl152 = shl i64 %conv1512699, 16		; <i64> [#uses=1]
 	%conv1712697 = zext i8 undef to i64		; <i64> [#uses=1]
@@ -283,7 +283,7 @@ for.body:		; preds = %for.cond
 	%add1427 = add i64 %add1392, %d.0		; <i64> [#uses=1]
 	%add1424 = add i64 %xor1412, 0		; <i64> [#uses=1]
 	%add1430 = add i64 %add1424, %add1392		; <i64> [#uses=5]
-	%tmp1438 = load i32* undef		; <i32> [#uses=1]
+	%tmp1438 = load i32, i32* undef		; <i32> [#uses=1]
 	%conv1439 = zext i32 %tmp1438 to i64		; <i64> [#uses=4]
 	%shl1441 = shl i64 %conv1439, 25		; <i64> [#uses=1]
 	%shr1444 = lshr i64 %conv1439, 7		; <i64> [#uses=1]
@@ -302,13 +302,13 @@ for.body:		; preds = %for.cond
 	%shr1479 = lshr i64 %conv1464, 10		; <i64> [#uses=1]
 	%xor1477 = xor i64 %or1476, %shr1479		; <i64> [#uses=1]
 	%xor1480 = xor i64 %xor1477, %or1470		; <i64> [#uses=1]
-	%tmp1499 = load i32* null		; <i32> [#uses=1]
+	%tmp1499 = load i32, i32* null		; <i32> [#uses=1]
 	%conv1500 = zext i32 %tmp1499 to i64		; <i64> [#uses=1]
 	%add1491 = add i64 %conv1500, 0		; <i64> [#uses=1]
 	%add1501 = add i64 %add1491, %xor1455		; <i64> [#uses=1]
 	%add1502 = add i64 %add1501, %xor1480		; <i64> [#uses=1]
 	%conv1504 = and i64 %add1502, 4294967295		; <i64> [#uses=1]
-	%tmp1541 = load i32* undef		; <i32> [#uses=1]
+	%tmp1541 = load i32, i32* undef		; <i32> [#uses=1]
 	%conv1542 = zext i32 %tmp1541 to i64		; <i64> [#uses=1]
 	%add1527 = add i64 %conv1542, %g.0		; <i64> [#uses=1]
 	%add1536 = add i64 %add1527, 0		; <i64> [#uses=1]
@@ -327,7 +327,7 @@ for.body:		; preds = %for.cond
 	%add1576 = add i64 %xor1564, 0		; <i64> [#uses=1]
 	%add1582 = add i64 %add1576, %add1544		; <i64> [#uses=3]
 	store i32 undef, i32* undef
-	%tmp1693 = load i32* undef		; <i32> [#uses=1]
+	%tmp1693 = load i32, i32* undef		; <i32> [#uses=1]
 	%conv1694 = zext i32 %tmp1693 to i64		; <i64> [#uses=1]
 	%add1679 = add i64 %conv1694, %f.0		; <i64> [#uses=1]
 	%add1688 = add i64 %add1679, 0		; <i64> [#uses=1]
diff --git a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
index 98b1e0ed2f42..8d387136da9c 100644
--- a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
+++ b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
@@ -1,7 +1,8 @@
 ; RUN: llc -mtriple=x86_64-mingw32 < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-linux < %s | FileCheck %s
 ; CHECK-NOT: -{{[1-9][0-9]*}}(%rsp)
 
-define x86_fp80 @a(i64 %x) nounwind readnone {
+define x86_64_win64cc x86_fp80 @a(i64 %x) nounwind readnone {
 entry:
         %conv = sitofp i64 %x to x86_fp80               ; <x86_fp80> [#uses=1]
         ret x86_fp80 %conv
diff --git a/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll b/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll
index 3dcc0d42e759..29795492d89c 100644
--- a/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll
+++ b/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll
@@ -17,7 +17,7 @@
 
 define fastcc void @MinSize(%struct.rec* %x) nounwind {
 entry:
-	%tmp13 = load i8* undef, align 4		; <i8> [#uses=3]
+	%tmp13 = load i8, i8* undef, align 4		; <i8> [#uses=3]
 	%tmp14 = zext i8 %tmp13 to i32		; <i32> [#uses=2]
 	switch i32 %tmp14, label %bb1109 [
 		i32 42, label %bb246
@@ -34,7 +34,7 @@ bb249:		; preds = %bb246
 	br i1 %tmp3240, label %bb974, label %bb269
 
 bb269:
-	%tmp3424 = getelementptr %struct.rec* %x, i32 0, i32 0, i32 0, i32 0, i32 1		; <%struct.rec**> [#uses=0]
+	%tmp3424 = getelementptr %struct.rec, %struct.rec* %x, i32 0, i32 0, i32 0, i32 0, i32 1		; <%struct.rec**> [#uses=0]
 	unreachable
 
 bb974:
diff --git a/test/CodeGen/X86/2009-06-05-ScalarToVectorByteMMX.ll b/test/CodeGen/X86/2009-06-05-ScalarToVectorByteMMX.ll
deleted file mode 100644
index 3061dc2c8275..000000000000
--- a/test/CodeGen/X86/2009-06-05-ScalarToVectorByteMMX.ll
+++ /dev/null
@@ -1,9 +0,0 @@
-; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mattr=+mmx,+sse2 | FileCheck %s
-
-; CHECK-NOT: movl
-
-define <8 x i8> @a(i8 zeroext %x) nounwind {
-  %r = insertelement <8 x i8> undef, i8 %x, i32 0
-  ret <8 x i8> %r
-}
-
diff --git a/test/CodeGen/X86/2009-06-05-VZextByteShort.ll b/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
index ffbe02c71356..9c7eb6d633db 100644
--- a/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
+++ b/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
@@ -6,7 +6,7 @@ define <4 x i16> @a(i32* %x1) nounwind {
 ; CHECK-NEXT:    movd %[[R]], %xmm0
 ; CHECK-NEXT:    retl
 
-  %x2 = load i32* %x1
+  %x2 = load i32, i32* %x1
   %x3 = lshr i32 %x2, 1
   %x = trunc i32 %x3 to i16
   %r = insertelement <4 x i16> zeroinitializer, i16 %x, i32 0
@@ -20,7 +20,7 @@ define <8 x i16> @b(i32* %x1) nounwind {
 ; CHECK-NEXT:    movd %e[[R]]x, %xmm0
 ; CHECK-NEXT:    retl
 
-  %x2 = load i32* %x1
+  %x2 = load i32, i32* %x1
   %x3 = lshr i32 %x2, 1
   %x = trunc i32 %x3 to i16
   %r = insertelement <8 x i16> zeroinitializer, i16 %x, i32 0
@@ -34,7 +34,7 @@ define <8 x i8> @c(i32* %x1) nounwind {
 ; CHECK-NEXT:    movd %e[[R]]x, %xmm0
 ; CHECK-NEXT:    retl
 
-  %x2 = load i32* %x1
+  %x2 = load i32, i32* %x1
   %x3 = lshr i32 %x2, 1
   %x = trunc i32 %x3 to i8
   %r = insertelement <8 x i8> zeroinitializer, i8 %x, i32 0
@@ -48,7 +48,7 @@ define <16 x i8> @d(i32* %x1) nounwind {
 ; CHECK-NEXT:    movd %e[[R]]x, %xmm0
 ; CHECK-NEXT:    retl
 
-  %x2 = load i32* %x1
+  %x2 = load i32, i32* %x1
   %x3 = lshr i32 %x2, 1
   %x = trunc i32 %x3 to i8
   %r = insertelement <16 x i8> zeroinitializer, i8 %x, i32 0
diff --git a/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll b/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll
deleted file mode 100644
index 66caedfc0692..000000000000
--- a/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll
+++ /dev/null
@@ -1,10 +0,0 @@
-; RUN: llc < %s -mtriple=x86_64-linux -mcpu=corei7 -mattr=+mmx | grep movd | count 2
-
-define i64 @a(i32 %a, i32 %b) nounwind readnone {
-entry:
-	%0 = insertelement <2 x i32> undef, i32 %a, i32 0		; <<2 x i32>> [#uses=1]
-	%1 = insertelement <2 x i32> %0, i32 %b, i32 1		; <<2 x i32>> [#uses=1]
-	%conv = bitcast <2 x i32> %1 to i64		; <i64> [#uses=1]
-	ret i64 %conv
-}
-
diff --git a/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll b/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll
index 8ea70b428007..4c4552da16a5 100644
--- a/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll
+++ b/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll
@@ -3,7 +3,7 @@
 
 define <4 x float> @f4523(<4 x float> %a,<4 x float> %b) nounwind {
 entry:
-; CHECK: shufps $-28, %xmm
+; CHECK: shufps $228, %xmm
 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4,i32
 5,i32 2,i32 3>
 ret <4 x float> %shuffle
diff --git a/test/CodeGen/X86/2009-07-15-CoalescerBug.ll b/test/CodeGen/X86/2009-07-15-CoalescerBug.ll
index eabaf775edef..beb57054dea2 100644
--- a/test/CodeGen/X86/2009-07-15-CoalescerBug.ll
+++ b/test/CodeGen/X86/2009-07-15-CoalescerBug.ll
@@ -237,7 +237,7 @@ bb1545:		; preds = %bb1544
 	br i1 undef, label %bb1563, label %bb1558
 
 bb1558:		; preds = %bb1545
-	%0 = load %struct.SV** undef		; <%struct.SV*> [#uses=1]
+	%0 = load %struct.SV*, %struct.SV** undef		; <%struct.SV*> [#uses=1]
 	%1 = bitcast %struct.SV* %0 to %struct.GV*		; <%struct.GV*> [#uses=5]
 	br i1 undef, label %bb1563, label %bb1559
 
diff --git a/test/CodeGen/X86/2009-07-20-CoalescerBug.ll b/test/CodeGen/X86/2009-07-20-CoalescerBug.ll
index e99edd60bd5e..1fa8da31b756 100644
--- a/test/CodeGen/X86/2009-07-20-CoalescerBug.ll
+++ b/test/CodeGen/X86/2009-07-20-CoalescerBug.ll
@@ -9,7 +9,7 @@ entry:
 	br i1 undef, label %return, label %if.end
 
 if.end:		; preds = %entry
-	%tmp35 = getelementptr %struct.re_pattern_buffer* %bufp, i64 0, i32 3		; <i64*> [#uses=1]
+	%tmp35 = getelementptr %struct.re_pattern_buffer, %struct.re_pattern_buffer* %bufp, i64 0, i32 3		; <i64*> [#uses=1]
 	store i64 %syntax, i64* %tmp35
 	store i32 undef, i32* undef
 	br i1 undef, label %if.then66, label %if.end102
@@ -80,7 +80,7 @@ while.cond979.preheader:		; preds = %if.then842, %land.lhs.true838, %cond.end834
 	%startoffset.0.ph = phi i32 [ 0, %cond.end834 ], [ 0, %land.lhs.true838 ], [ %conv851, %if.then842 ]		; <i32> [#uses=2]
 	%laststart.7.ph = phi i8* [ %laststart.2, %cond.end834 ], [ %laststart.2, %land.lhs.true838 ], [ %laststart.2, %if.then842 ]		; <i8*> [#uses=3]
 	%b.4.ph = phi i8* [ %b.1, %cond.end834 ], [ %b.1, %land.lhs.true838 ], [ %b.1, %if.then842 ]		; <i8*> [#uses=3]
-	%ctg29688 = getelementptr i8* %b.4.ph, i64 6		; <i8*> [#uses=1]
+	%ctg29688 = getelementptr i8, i8* %b.4.ph, i64 6		; <i8*> [#uses=1]
 	br label %while.cond979
 
 while.cond979:		; preds = %if.end1006, %while.cond979.preheader
@@ -102,21 +102,21 @@ while.end1088:		; preds = %while.cond979
 if.then1091:		; preds = %while.end1088
 	store i8 undef, i8* undef
 	%idx.ext1132.pre = zext i32 %startoffset.0.ph to i64		; <i64> [#uses=1]
-	%add.ptr1133.pre = getelementptr i8* %laststart.7.ph, i64 %idx.ext1132.pre		; <i8*> [#uses=1]
+	%add.ptr1133.pre = getelementptr i8, i8* %laststart.7.ph, i64 %idx.ext1132.pre		; <i8*> [#uses=1]
 	%sub.ptr.lhs.cast1135.pre = ptrtoint i8* %add.ptr1133.pre to i64		; <i64> [#uses=1]
 	br label %if.end1126
 
 if.else1101:		; preds = %while.end1088
 	%cond1109 = select i1 undef, i32 18, i32 14		; <i32> [#uses=1]
 	%idx.ext1112 = zext i32 %startoffset.0.ph to i64		; <i64> [#uses=1]
-	%add.ptr1113 = getelementptr i8* %laststart.7.ph, i64 %idx.ext1112		; <i8*> [#uses=2]
+	%add.ptr1113 = getelementptr i8, i8* %laststart.7.ph, i64 %idx.ext1112		; <i8*> [#uses=2]
 	%sub.ptr.rhs.cast1121 = ptrtoint i8* %add.ptr1113 to i64		; <i64> [#uses=1]
 	call fastcc void @insert_op1(i32 %cond1109, i8* %add.ptr1113, i32 undef, i8* %b.4.ph) ssp
 	br label %if.end1126
 
 if.end1126:		; preds = %if.else1101, %if.then1091
 	%sub.ptr.lhs.cast1135.pre-phi = phi i64 [ %sub.ptr.rhs.cast1121, %if.else1101 ], [ %sub.ptr.lhs.cast1135.pre, %if.then1091 ]		; <i64> [#uses=1]
-	%add.ptr1128 = getelementptr i8* %b.4.ph, i64 3		; <i8*> [#uses=1]
+	%add.ptr1128 = getelementptr i8, i8* %b.4.ph, i64 3		; <i8*> [#uses=1]
 	%sub.ptr.rhs.cast1136 = ptrtoint i8* %add.ptr1128 to i64		; <i64> [#uses=1]
 	%sub.ptr.sub1137 = sub i64 %sub.ptr.lhs.cast1135.pre-phi, %sub.ptr.rhs.cast1136		; <i64> [#uses=1]
 	%sub.ptr.sub11378527 = trunc i64 %sub.ptr.sub1137 to i32		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2009-07-20-DAGCombineBug.ll b/test/CodeGen/X86/2009-07-20-DAGCombineBug.ll
index e83b3a7db592..045e89e15856 100644
--- a/test/CodeGen/X86/2009-07-20-DAGCombineBug.ll
+++ b/test/CodeGen/X86/2009-07-20-DAGCombineBug.ll
@@ -5,7 +5,7 @@
 
 define fastcc i32 @bsGetUInt32() nounwind ssp {
 entry:
-	%bsBuff.promoted44 = load i32* @bsBuff		; <i32> [#uses=1]
+	%bsBuff.promoted44 = load i32, i32* @bsBuff		; <i32> [#uses=1]
 	%0 = add i32 0, -8		; <i32> [#uses=1]
 	%1 = lshr i32 %bsBuff.promoted44, %0		; <i32> [#uses=1]
 	%2 = shl i32 %1, 8		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll b/test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll
deleted file mode 100644
index 288eef4f6991..000000000000
--- a/test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll
+++ /dev/null
@@ -1,12 +0,0 @@
-; RUN: llc < %s -march=x86-64
-; PR4669
-declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
-
-define <1 x i64> @test(i64 %t) {
-entry:
-	%t1 = insertelement <1 x i64> undef, i64 %t, i32 0
-        %t0 = bitcast <1 x i64> %t1 to x86_mmx
-	%t2 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %t0, i32 48)
-        %t3 = bitcast x86_mmx %t2 to <1 x i64>
-	ret <1 x i64> %t3
-}
diff --git a/test/CodeGen/X86/2009-08-06-branchfolder-crash.ll b/test/CodeGen/X86/2009-08-06-branchfolder-crash.ll
index 2080c0ae2e0f..a70861dcf849 100644
--- a/test/CodeGen/X86/2009-08-06-branchfolder-crash.ll
+++ b/test/CodeGen/X86/2009-08-06-branchfolder-crash.ll
@@ -43,12 +43,12 @@ entry:
 	br i1 %tobool, label %lor.lhs.false, label %if.then
 
 lor.lhs.false:		; preds = %entry
-	%tmp1 = load i8* @g_3		; <i8> [#uses=1]
+	%tmp1 = load i8, i8* @g_3		; <i8> [#uses=1]
 	%tobool3 = icmp eq i8 %tmp1, 0		; <i1> [#uses=1]
 	br i1 %tobool3, label %return, label %if.then
 
 if.then:		; preds = %lor.lhs.false, %entry
-	%tmp4 = load i8* @g_3		; <i8> [#uses=1]
+	%tmp4 = load i8, i8* @g_3		; <i8> [#uses=1]
 	%conv5 = sext i8 %tmp4 to i32		; <i32> [#uses=1]
 	ret i32 %conv5
 
@@ -93,12 +93,12 @@ entry:
   br i1 %tobool, label %lor.lhs.false, label %if.then
 
 lor.lhs.false:                                    ; preds = %entry
-  %tmp1 = load i8* @g_3                           ; <i8> [#uses=1]
+  %tmp1 = load i8, i8* @g_3                           ; <i8> [#uses=1]
   %tobool3 = icmp eq i8 %tmp1, 0                  ; <i1> [#uses=1]
   br i1 %tobool3, label %return, label %if.then
 
 if.then:                                          ; preds = %lor.lhs.false, %entry
-  %tmp4 = load i8* @g_3                           ; <i8> [#uses=1]
+  %tmp4 = load i8, i8* @g_3                           ; <i8> [#uses=1]
   %conv5 = sext i8 %tmp4 to i32                   ; <i32> [#uses=1]
   ret i32 %conv5
 
diff --git a/test/CodeGen/X86/2009-08-06-inlineasm.ll b/test/CodeGen/X86/2009-08-06-inlineasm.ll
index f9b5f9e0b1fd..f548bc093026 100644
--- a/test/CodeGen/X86/2009-08-06-inlineasm.ll
+++ b/test/CodeGen/X86/2009-08-06-inlineasm.ll
@@ -19,12 +19,12 @@ if.then28:		; preds = %entry
 
 if.end78:		; preds = %if.then28, %entry
 	%level.1 = phi i32 [ %tmp, %if.then28 ], [ 0, %entry ]		; <i32> [#uses=1]
-	%add.ptr1 = getelementptr [64 x i16]* null, i32 0, i32 %qscale		; <i16*> [#uses=1]
-	%add.ptr2 = getelementptr [64 x i16]* null, i32 1, i32 %qscale		; <i16*> [#uses=1]
-	%add.ptr3 = getelementptr [64 x i16]* null, i32 2, i32 %qscale		; <i16*> [#uses=1]
-	%add.ptr4 = getelementptr [64 x i16]* null, i32 3, i32 %qscale		; <i16*> [#uses=1]
-	%add.ptr5 = getelementptr [64 x i16]* null, i32 4, i32 %qscale		; <i16*> [#uses=1]
-	%add.ptr6 = getelementptr [64 x i16]* null, i32 5, i32 %qscale		; <i16*> [#uses=1]
+	%add.ptr1 = getelementptr [64 x i16], [64 x i16]* null, i32 0, i32 %qscale		; <i16*> [#uses=1]
+	%add.ptr2 = getelementptr [64 x i16], [64 x i16]* null, i32 1, i32 %qscale		; <i16*> [#uses=1]
+	%add.ptr3 = getelementptr [64 x i16], [64 x i16]* null, i32 2, i32 %qscale		; <i16*> [#uses=1]
+	%add.ptr4 = getelementptr [64 x i16], [64 x i16]* null, i32 3, i32 %qscale		; <i16*> [#uses=1]
+	%add.ptr5 = getelementptr [64 x i16], [64 x i16]* null, i32 4, i32 %qscale		; <i16*> [#uses=1]
+	%add.ptr6 = getelementptr [64 x i16], [64 x i16]* null, i32 5, i32 %qscale		; <i16*> [#uses=1]
 	%tmp1 = call i32 asm sideeffect "nop", "={ax},r,r,r,r,r,0,~{dirflag},~{fpsr},~{flags}"(i16* %add.ptr6, i16* %add.ptr5, i16* %add.ptr4, i16* %add.ptr3, i16* %add.ptr2, i16* %add.ptr1) nounwind		; <i32> [#uses=0]
 	ret i32 %level.1
 }
diff --git a/test/CodeGen/X86/2009-08-14-Win64MemoryIndirectArg.ll b/test/CodeGen/X86/2009-08-14-Win64MemoryIndirectArg.ll
index bf668e304b28..f24c3f8171bf 100644
--- a/test/CodeGen/X86/2009-08-14-Win64MemoryIndirectArg.ll
+++ b/test/CodeGen/X86/2009-08-14-Win64MemoryIndirectArg.ll
@@ -12,14 +12,14 @@ indexCheckBlock:
 
 primitiveTextureFetchBlock:		; preds = %indexCheckBlock
 	%pointerArithmeticTmp = bitcast %0* %shaderExecutionStatePtr to i8*		; <i8*> [#uses=1]
-	%pointerArithmeticTmp1 = getelementptr i8* %pointerArithmeticTmp, i64 1808		; <i8*> [#uses=1]
+	%pointerArithmeticTmp1 = getelementptr i8, i8* %pointerArithmeticTmp, i64 1808		; <i8*> [#uses=1]
 	%pointerArithmeticTmp2 = bitcast i8* %pointerArithmeticTmp1 to %1**		; <%1**> [#uses=1]
-	%primitivePtr = load %1** %pointerArithmeticTmp2		; <%1*> [#uses=1]
+	%primitivePtr = load %1*, %1** %pointerArithmeticTmp2		; <%1*> [#uses=1]
 	%pointerArithmeticTmp3 = bitcast %1* %primitivePtr to i8*		; <i8*> [#uses=1]
-	%pointerArithmeticTmp4 = getelementptr i8* %pointerArithmeticTmp3, i64 19408		; <i8*> [#uses=1]
+	%pointerArithmeticTmp4 = getelementptr i8, i8* %pointerArithmeticTmp3, i64 19408		; <i8*> [#uses=1]
 	%pointerArithmeticTmp5 = bitcast i8* %pointerArithmeticTmp4 to %1**		; <%1**> [#uses=1]
-	%primitiveTexturePtr = getelementptr %1** %pointerArithmeticTmp5, i32 %index		; <%1**> [#uses=1]
-	%primitiveTexturePtr6 = load %1** %primitiveTexturePtr		; <%1*> [#uses=2]
+	%primitiveTexturePtr = getelementptr %1*, %1** %pointerArithmeticTmp5, i32 %index		; <%1**> [#uses=1]
+	%primitiveTexturePtr6 = load %1*, %1** %primitiveTexturePtr		; <%1*> [#uses=2]
 	br label %textureCheckBlock
 
 textureCheckBlock:		; preds = %primitiveTextureFetchBlock
@@ -29,9 +29,9 @@ textureCheckBlock:		; preds = %primitiveTextureFetchBlock
 
 rhoCalculateBlock:		; preds = %textureCheckBlock
 	%pointerArithmeticTmp7 = bitcast %1* %primitiveTexturePtr6 to i8*		; <i8*> [#uses=1]
-	%pointerArithmeticTmp8 = getelementptr i8* %pointerArithmeticTmp7, i64 640		; <i8*> [#uses=1]
+	%pointerArithmeticTmp8 = getelementptr i8, i8* %pointerArithmeticTmp7, i64 640		; <i8*> [#uses=1]
 	%pointerArithmeticTmp9 = bitcast i8* %pointerArithmeticTmp8 to <4 x float>*		; <<4 x float>*> [#uses=1]
-	%dimensionsPtr = load <4 x float>* %pointerArithmeticTmp9, align 1		; <<4 x float>> [#uses=2]
+	%dimensionsPtr = load <4 x float>, <4 x float>* %pointerArithmeticTmp9, align 1		; <<4 x float>> [#uses=2]
 	%texDiffDX = fsub <4 x float> %texCoordDX, %texCoord		; <<4 x float>> [#uses=1]
 	%texDiffDY = fsub <4 x float> %texCoordDY, %texCoord		; <<4 x float>> [#uses=1]
 	%ddx = fmul <4 x float> %texDiffDX, %dimensionsPtr		; <<4 x float>> [#uses=2]
diff --git a/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll b/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll
index 5f6cf3b9e0bb..5926ab4b5c72 100644
--- a/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll
+++ b/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll
@@ -5,7 +5,7 @@
 
 define void @c() nounwind {
 ; CHECK: movl a+8, %eax
-  %srcval1 = load i96* @a, align 4
+  %srcval1 = load i96, i96* @a, align 4
   %sroa.store.elt2 = lshr i96 %srcval1, 64
   %tmp = trunc i96 %sroa.store.elt2 to i64
 ; CHECK: movl %eax, b
diff --git a/test/CodeGen/X86/2009-08-23-SubRegReuseUndo.ll b/test/CodeGen/X86/2009-08-23-SubRegReuseUndo.ll
index 410a42a42878..45e770f8121b 100644
--- a/test/CodeGen/X86/2009-08-23-SubRegReuseUndo.ll
+++ b/test/CodeGen/X86/2009-08-23-SubRegReuseUndo.ll
@@ -41,19 +41,19 @@ bb3:                                              ; preds = %bb2, %bb
   br i1 undef, label %bb5, label %bb4
 
 bb4:                                              ; preds = %bb3
-  %17 = load volatile i32* @uint8, align 4        ; <i32> [#uses=0]
+  %17 = load volatile i32, i32* @uint8, align 4        ; <i32> [#uses=0]
   br label %bb5
 
 bb5:                                              ; preds = %bb4, %bb3
-  %18 = load volatile i32* @uint8, align 4        ; <i32> [#uses=0]
+  %18 = load volatile i32, i32* @uint8, align 4        ; <i32> [#uses=0]
   %19 = sext i8 undef to i16                      ; <i16> [#uses=1]
   %20 = tail call i32 @func_24(i16 zeroext %19, i8 signext 1) nounwind; <i32> [#uses=0]
   br i1 undef, label %return, label %bb6.preheader
 
 bb6.preheader:                                    ; preds = %bb5
   %21 = sext i8 %p_52 to i32                      ; <i32> [#uses=1]
-  %22 = load volatile i32* @uint8, align 4        ; <i32> [#uses=0]
-  %23 = tail call i32 (...)* @safefuncts(i32 %21, i32 1) nounwind; <i32> [#uses=0]
+  %22 = load volatile i32, i32* @uint8, align 4        ; <i32> [#uses=0]
+  %23 = tail call i32 (...) @safefuncts(i32 %21, i32 1) nounwind; <i32> [#uses=0]
   unreachable
 
 return:                                           ; preds = %bb5
diff --git a/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll b/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll
index 5483b73ecc8c..2ec49f486c99 100644
--- a/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll
+++ b/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll
@@ -25,8 +25,8 @@ invcont:                                          ; preds = %entry
           to label %invcont1 unwind label %lpad   ; <i8> [#uses=0]
 
 invcont1:                                         ; preds = %invcont
-  %6 = getelementptr inbounds %struct.ComplexType* %2, i64 0, i32 0 ; <i32*> [#uses=1]
-  %7 = load i32* %6, align 4                      ; <i32> [#uses=1]
+  %6 = getelementptr inbounds %struct.ComplexType, %struct.ComplexType* %2, i64 0, i32 0 ; <i32*> [#uses=1]
+  %7 = load i32, i32* %6, align 4                      ; <i32> [#uses=1]
   invoke void @booleanAndDataReply(i32 %7, i32 undef, i32 %requestID, i32 undef, i64 undef, i32 undef)
           to label %invcont2 unwind label %lpad
 
diff --git a/test/CodeGen/X86/2009-09-10-SpillComments.ll b/test/CodeGen/X86/2009-09-10-SpillComments.ll
index adac20336048..78ce1cefcd43 100644
--- a/test/CodeGen/X86/2009-09-10-SpillComments.ll
+++ b/test/CodeGen/X86/2009-09-10-SpillComments.ll
@@ -20,18 +20,18 @@ entry:
 	br i1 %tmp2, label %UnifiedReturnBlock, label %cond_next
 
 cond_next:		; preds = %entry
-	%tmp6 = getelementptr %struct.rtx_def* %x, i32 0, i32 0		; <i16*> [#uses=1]
-	%tmp7 = load i16* %tmp6		; <i16> [#uses=2]
+	%tmp6 = getelementptr %struct.rtx_def, %struct.rtx_def* %x, i32 0, i32 0		; <i16*> [#uses=1]
+	%tmp7 = load i16, i16* %tmp6		; <i16> [#uses=2]
 	%tmp78 = zext i16 %tmp7 to i32		; <i32> [#uses=2]
 	%tmp10 = icmp eq i16 %tmp7, 54		; <i1> [#uses=1]
 	br i1 %tmp10, label %cond_true13, label %cond_next32
 
 cond_true13:		; preds = %cond_next
-	%tmp15 = getelementptr %struct.rtx_def* %x, i32 0, i32 3		; <[1 x %struct..0anon]*> [#uses=1]
+	%tmp15 = getelementptr %struct.rtx_def, %struct.rtx_def* %x, i32 0, i32 3		; <[1 x %struct..0anon]*> [#uses=1]
 	%tmp1718 = bitcast [1 x %struct..0anon]* %tmp15 to %struct.rtx_def**		; <%struct.rtx_def**> [#uses=1]
-	%tmp19 = load %struct.rtx_def** %tmp1718		; <%struct.rtx_def*> [#uses=1]
-	%tmp20 = getelementptr %struct.rtx_def* %tmp19, i32 0, i32 0		; <i16*> [#uses=1]
-	%tmp21 = load i16* %tmp20		; <i16> [#uses=1]
+	%tmp19 = load %struct.rtx_def*, %struct.rtx_def** %tmp1718		; <%struct.rtx_def*> [#uses=1]
+	%tmp20 = getelementptr %struct.rtx_def, %struct.rtx_def* %tmp19, i32 0, i32 0		; <i16*> [#uses=1]
+	%tmp21 = load i16, i16* %tmp20		; <i16> [#uses=1]
 	%tmp22 = icmp eq i16 %tmp21, 57		; <i1> [#uses=1]
 	br i1 %tmp22, label %cond_true25, label %cond_next32
 
@@ -40,10 +40,10 @@ cond_true25:		; preds = %cond_true13
 	ret %struct.rtx_def* %tmp29
 
 cond_next32:		; preds = %cond_true13, %cond_next
-	%tmp34 = getelementptr [116 x i8*]* @rtx_format, i32 0, i32 %tmp78		; <i8**> [#uses=1]
-	%tmp35 = load i8** %tmp34, align 4		; <i8*> [#uses=1]
-	%tmp37 = getelementptr [117 x i32]* @rtx_length, i32 0, i32 %tmp78		; <i32*> [#uses=1]
-	%tmp38 = load i32* %tmp37, align 4		; <i32> [#uses=1]
+	%tmp34 = getelementptr [116 x i8*], [116 x i8*]* @rtx_format, i32 0, i32 %tmp78		; <i8**> [#uses=1]
+	%tmp35 = load i8*, i8** %tmp34, align 4		; <i8*> [#uses=1]
+	%tmp37 = getelementptr [117 x i32], [117 x i32]* @rtx_length, i32 0, i32 %tmp78		; <i32*> [#uses=1]
+	%tmp38 = load i32, i32* %tmp37, align 4		; <i32> [#uses=1]
 	%i.011 = add i32 %tmp38, -1		; <i32> [#uses=2]
 	%tmp12513 = icmp sgt i32 %i.011, -1		; <i1> [#uses=1]
 	br i1 %tmp12513, label %bb, label %UnifiedReturnBlock
@@ -51,48 +51,48 @@ cond_next32:		; preds = %cond_true13, %cond_next
 bb:		; preds = %bb123, %cond_next32
 	%indvar = phi i32 [ %indvar.next26, %bb123 ], [ 0, %cond_next32 ]		; <i32> [#uses=2]
 	%i.01.0 = sub i32 %i.011, %indvar		; <i32> [#uses=5]
-	%tmp42 = getelementptr i8* %tmp35, i32 %i.01.0		; <i8*> [#uses=2]
-	%tmp43 = load i8* %tmp42		; <i8> [#uses=1]
+	%tmp42 = getelementptr i8, i8* %tmp35, i32 %i.01.0		; <i8*> [#uses=2]
+	%tmp43 = load i8, i8* %tmp42		; <i8> [#uses=1]
 	switch i8 %tmp43, label %bb123 [
 		 i8 101, label %cond_true47
 		 i8 69, label %bb105.preheader
 	]
 
 cond_true47:		; preds = %bb
-	%tmp52 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0		; <%struct..0anon*> [#uses=1]
+	%tmp52 = getelementptr %struct.rtx_def, %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0		; <%struct..0anon*> [#uses=1]
 	%tmp5354 = bitcast %struct..0anon* %tmp52 to %struct.rtx_def**		; <%struct.rtx_def**> [#uses=1]
-	%tmp55 = load %struct.rtx_def** %tmp5354		; <%struct.rtx_def*> [#uses=1]
+	%tmp55 = load %struct.rtx_def*, %struct.rtx_def** %tmp5354		; <%struct.rtx_def*> [#uses=1]
 	%tmp58 = tail call  %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp55, %struct.rtx_def* %insn ) nounwind		; <%struct.rtx_def*> [#uses=1]
-	%tmp62 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0, i32 0		; <i32*> [#uses=1]
+	%tmp62 = getelementptr %struct.rtx_def, %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0, i32 0		; <i32*> [#uses=1]
 	%tmp58.c = ptrtoint %struct.rtx_def* %tmp58 to i32		; <i32> [#uses=1]
 	store i32 %tmp58.c, i32* %tmp62
-	%tmp6816 = load i8* %tmp42		; <i8> [#uses=1]
+	%tmp6816 = load i8, i8* %tmp42		; <i8> [#uses=1]
 	%tmp6917 = icmp eq i8 %tmp6816, 69		; <i1> [#uses=1]
 	br i1 %tmp6917, label %bb105.preheader, label %bb123
 
 bb105.preheader:		; preds = %cond_true47, %bb
-	%tmp11020 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0		; <%struct..0anon*> [#uses=1]
+	%tmp11020 = getelementptr %struct.rtx_def, %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0		; <%struct..0anon*> [#uses=1]
 	%tmp11111221 = bitcast %struct..0anon* %tmp11020 to %struct.rtvec_def**		; <%struct.rtvec_def**> [#uses=3]
-	%tmp11322 = load %struct.rtvec_def** %tmp11111221		; <%struct.rtvec_def*> [#uses=1]
-	%tmp11423 = getelementptr %struct.rtvec_def* %tmp11322, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp11524 = load i32* %tmp11423		; <i32> [#uses=1]
+	%tmp11322 = load %struct.rtvec_def*, %struct.rtvec_def** %tmp11111221		; <%struct.rtvec_def*> [#uses=1]
+	%tmp11423 = getelementptr %struct.rtvec_def, %struct.rtvec_def* %tmp11322, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp11524 = load i32, i32* %tmp11423		; <i32> [#uses=1]
 	%tmp11625 = icmp eq i32 %tmp11524, 0		; <i1> [#uses=1]
 	br i1 %tmp11625, label %bb123, label %bb73
 
 bb73:		; preds = %bb73, %bb105.preheader
 	%j.019 = phi i32 [ %tmp104, %bb73 ], [ 0, %bb105.preheader ]		; <i32> [#uses=3]
-	%tmp81 = load %struct.rtvec_def** %tmp11111221		; <%struct.rtvec_def*> [#uses=2]
-	%tmp92 = getelementptr %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019		; <%struct..0anon*> [#uses=1]
+	%tmp81 = load %struct.rtvec_def*, %struct.rtvec_def** %tmp11111221		; <%struct.rtvec_def*> [#uses=2]
+	%tmp92 = getelementptr %struct.rtvec_def, %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019		; <%struct..0anon*> [#uses=1]
 	%tmp9394 = bitcast %struct..0anon* %tmp92 to %struct.rtx_def**		; <%struct.rtx_def**> [#uses=1]
-	%tmp95 = load %struct.rtx_def** %tmp9394		; <%struct.rtx_def*> [#uses=1]
+	%tmp95 = load %struct.rtx_def*, %struct.rtx_def** %tmp9394		; <%struct.rtx_def*> [#uses=1]
 	%tmp98 = tail call  %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp95, %struct.rtx_def* %insn ) nounwind		; <%struct.rtx_def*> [#uses=1]
-	%tmp101 = getelementptr %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019, i32 0		; <i32*> [#uses=1]
+	%tmp101 = getelementptr %struct.rtvec_def, %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019, i32 0		; <i32*> [#uses=1]
 	%tmp98.c = ptrtoint %struct.rtx_def* %tmp98 to i32		; <i32> [#uses=1]
 	store i32 %tmp98.c, i32* %tmp101
 	%tmp104 = add i32 %j.019, 1		; <i32> [#uses=2]
-	%tmp113 = load %struct.rtvec_def** %tmp11111221		; <%struct.rtvec_def*> [#uses=1]
-	%tmp114 = getelementptr %struct.rtvec_def* %tmp113, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp115 = load i32* %tmp114		; <i32> [#uses=1]
+	%tmp113 = load %struct.rtvec_def*, %struct.rtvec_def** %tmp11111221		; <%struct.rtvec_def*> [#uses=1]
+	%tmp114 = getelementptr %struct.rtvec_def, %struct.rtvec_def* %tmp113, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp115 = load i32, i32* %tmp114		; <i32> [#uses=1]
 	%tmp116 = icmp ult i32 %tmp104, %tmp115		; <i1> [#uses=1]
 	br i1 %tmp116, label %bb73, label %bb123
 
diff --git a/test/CodeGen/X86/2009-09-16-CoalescerBug.ll b/test/CodeGen/X86/2009-09-16-CoalescerBug.ll
index 18b5a179c9ef..a18a30ad5cd8 100644
--- a/test/CodeGen/X86/2009-09-16-CoalescerBug.ll
+++ b/test/CodeGen/X86/2009-09-16-CoalescerBug.ll
@@ -32,7 +32,7 @@ lor.lhs.false:                                    ; preds = %for.body
   br i1 %cmp16, label %for.end41, label %for.cond17.preheader
 
 for.cond17.preheader:                             ; preds = %lor.lhs.false
-  %tmp24 = load i32* @boot_cpu_id                 ; <i32> [#uses=1]
+  %tmp24 = load i32, i32* @boot_cpu_id                 ; <i32> [#uses=1]
   %shr26 = ashr i32 %tmp24, %and                  ; <i32> [#uses=1]
   br label %for.body20
 
diff --git a/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll b/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll
index 0268d817c70d..840b3171f689 100644
--- a/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll
+++ b/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll
@@ -12,12 +12,12 @@ bb:		; preds = %bb, %entry
 	%i.03 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]		; <i32> [#uses=3]
 	%sum.04 = phi i32 [ 0, %entry ], [ %10, %bb ]		; <i32> [#uses=1]
 	%1 = mul i32 %i.03, %As		; <i32> [#uses=1]
-	%2 = getelementptr i16* %A, i32 %1		; <i16*> [#uses=1]
-	%3 = load i16* %2, align 2		; <i16> [#uses=1]
+	%2 = getelementptr i16, i16* %A, i32 %1		; <i16*> [#uses=1]
+	%3 = load i16, i16* %2, align 2		; <i16> [#uses=1]
 	%4 = sext i16 %3 to i32		; <i32> [#uses=1]
 	%5 = mul i32 %i.03, %Bs		; <i32> [#uses=1]
-	%6 = getelementptr i16* %B, i32 %5		; <i16*> [#uses=1]
-	%7 = load i16* %6, align 2		; <i16> [#uses=1]
+	%6 = getelementptr i16, i16* %B, i32 %5		; <i16*> [#uses=1]
+	%7 = load i16, i16* %6, align 2		; <i16> [#uses=1]
 	%8 = sext i16 %7 to i32		; <i32> [#uses=1]
 	%9 = mul i32 %8, %4		; <i32> [#uses=1]
 	%10 = add i32 %9, %sum.04		; <i32> [#uses=2]
diff --git a/test/CodeGen/X86/2009-09-22-CoalescerBug.ll b/test/CodeGen/X86/2009-09-22-CoalescerBug.ll
index 33f35f881e85..e469a6004323 100644
--- a/test/CodeGen/X86/2009-09-22-CoalescerBug.ll
+++ b/test/CodeGen/X86/2009-09-22-CoalescerBug.ll
@@ -54,7 +54,7 @@ bb9:                                              ; preds = %quantum_new_qureg.e
   unreachable
 
 bb.i37:                                           ; preds = %bb.i37, %bb11.thread
-  %0 = load i64* undef, align 8                   ; <i64> [#uses=1]
+  %0 = load i64, i64* undef, align 8                   ; <i64> [#uses=1]
   %1 = shl i64 %0, %.cast.i                       ; <i64> [#uses=1]
   store i64 %1, i64* undef, align 8
   br i1 undef, label %bb.i37, label %quantum_addscratch.exit
diff --git a/test/CodeGen/X86/2009-10-16-Scope.ll b/test/CodeGen/X86/2009-10-16-Scope.ll
index e75d594e6682..bda7340b3643 100644
--- a/test/CodeGen/X86/2009-10-16-Scope.ll
+++ b/test/CodeGen/X86/2009-10-16-Scope.ll
@@ -9,7 +9,7 @@ entry:
   br label %do.body, !dbg !0
 
 do.body:                                          ; preds = %entry
-  call void @llvm.dbg.declare(metadata i32* %count_, metadata !4, metadata !{!"0x102"})
+  call void @llvm.dbg.declare(metadata i32* %count_, metadata !4, metadata !DIExpression()), !dbg !DILocation(scope: !5)
   %conv = ptrtoint i32* %count_ to i32, !dbg !0   ; <i32> [#uses=1]
   %call = call i32 @foo(i32 %conv) ssp, !dbg !0   ; <i32> [#uses=0]
   br label %do.end, !dbg !0
@@ -22,13 +22,13 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 
 declare i32 @foo(i32) ssp
 
-!0 = !MDLocation(line: 5, column: 2, scope: !1)
-!1 = !{!"0xb\001\001\000", null, !2}; [DW_TAG_lexical_block ]
-!2 = !{!"0x2e\00bar\00bar\00bar\004\000\001\000\006\000\000\000", i32 0, !3, null, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!3 = !{!"0x11\0012\00clang 1.1\001\00\000\00\000", !8, null, !9, null, null, null}; [DW_TAG_compile_unit ]
-!4 = !{!"0x100\00count_\005\000", !5, !3, !6}; [ DW_TAG_auto_variable ]
-!5 = !{!"0xb\001\001\000", null, !1}; [DW_TAG_lexical_block ]
-!6 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !3}; [DW_TAG_base_type ]
-!7 = !MDLocation(line: 6, column: 1, scope: !2)
-!8 = !{!"genmodes.i", !"/Users/yash/Downloads"}
+!0 = !DILocation(line: 5, column: 2, scope: !1)
+!1 = distinct !DILexicalBlock(line: 1, column: 1, file: null, scope: !2)
+!2 = !DISubprogram(name: "bar", linkageName: "bar", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !3)
+!3 = !DICompileUnit(language: DW_LANG_C99, producer: "clang 1.1", isOptimized: true, emissionKind: 0, file: !8, retainedTypes: !9)
+!4 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "count_", line: 5, scope: !5, file: !3, type: !6)
+!5 = distinct !DILexicalBlock(line: 1, column: 1, file: null, scope: !1)
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!7 = !DILocation(line: 6, column: 1, scope: !2)
+!8 = !DIFile(filename: "genmodes.i", directory: "/Users/yash/Downloads")
 !9 = !{i32 0}
diff --git a/test/CodeGen/X86/2009-10-19-EmergencySpill.ll b/test/CodeGen/X86/2009-10-19-EmergencySpill.ll
index ba44a2e64feb..ec73f5a2c823 100644
--- a/test/CodeGen/X86/2009-10-19-EmergencySpill.ll
+++ b/test/CodeGen/X86/2009-10-19-EmergencySpill.ll
@@ -8,21 +8,21 @@
 
 define fastcc void @nodeOverwriteCell(%struct.Rtree* nocapture %pRtree, %struct.RtreeNode* nocapture %pNode, %struct.RtreeCell* nocapture %pCell, i32 %iCell) nounwind ssp {
 entry:
-  %0 = load i8** undef, align 8                   ; <i8*> [#uses=2]
-  %1 = load i32* undef, align 8                   ; <i32> [#uses=1]
+  %0 = load i8*, i8** undef, align 8                   ; <i8*> [#uses=2]
+  %1 = load i32, i32* undef, align 8                   ; <i32> [#uses=1]
   %2 = mul i32 %1, %iCell                         ; <i32> [#uses=1]
   %3 = add nsw i32 %2, 4                          ; <i32> [#uses=1]
   %4 = sext i32 %3 to i64                         ; <i64> [#uses=2]
-  %5 = load i64* null, align 8                    ; <i64> [#uses=2]
+  %5 = load i64, i64* null, align 8                    ; <i64> [#uses=2]
   %6 = lshr i64 %5, 48                            ; <i64> [#uses=1]
   %7 = trunc i64 %6 to i8                         ; <i8> [#uses=1]
   store i8 %7, i8* undef, align 1
   %8 = lshr i64 %5, 8                             ; <i64> [#uses=1]
   %9 = trunc i64 %8 to i8                         ; <i8> [#uses=1]
   %.sum4 = add i64 %4, 6                          ; <i64> [#uses=1]
-  %10 = getelementptr inbounds i8* %0, i64 %.sum4 ; <i8*> [#uses=1]
+  %10 = getelementptr inbounds i8, i8* %0, i64 %.sum4 ; <i8*> [#uses=1]
   store i8 %9, i8* %10, align 1
-  %11 = getelementptr inbounds %struct.Rtree* %pRtree, i64 0, i32 3 ; <i32*> [#uses=1]
+  %11 = getelementptr inbounds %struct.Rtree, %struct.Rtree* %pRtree, i64 0, i32 3 ; <i32*> [#uses=1]
   br i1 undef, label %bb.nph, label %bb2
 
 bb.nph:                                           ; preds = %entry
@@ -31,24 +31,24 @@ bb.nph:                                           ; preds = %entry
 
 bb:                                               ; preds = %bb, %bb.nph
   %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i64> [#uses=3]
-  %scevgep = getelementptr %struct.RtreeCell* %pCell, i64 0, i32 1, i64 %indvar ; <%union.RtreeCoord*> [#uses=1]
+  %scevgep = getelementptr %struct.RtreeCell, %struct.RtreeCell* %pCell, i64 0, i32 1, i64 %indvar ; <%union.RtreeCoord*> [#uses=1]
   %scevgep12 = bitcast %union.RtreeCoord* %scevgep to i32* ; <i32*> [#uses=1]
   %tmp = shl i64 %indvar, 2                       ; <i64> [#uses=1]
   %tmp26 = add i64 %tmp, %tmp25                   ; <i64> [#uses=1]
-  %scevgep27 = getelementptr i8* %0, i64 %tmp26   ; <i8*> [#uses=1]
-  %12 = load i32* %scevgep12, align 4             ; <i32> [#uses=1]
+  %scevgep27 = getelementptr i8, i8* %0, i64 %tmp26   ; <i8*> [#uses=1]
+  %12 = load i32, i32* %scevgep12, align 4             ; <i32> [#uses=1]
   %13 = lshr i32 %12, 24                          ; <i32> [#uses=1]
   %14 = trunc i32 %13 to i8                       ; <i8> [#uses=1]
   store i8 %14, i8* undef, align 1
   store i8 undef, i8* %scevgep27, align 1
-  %15 = load i32* %11, align 4                    ; <i32> [#uses=1]
+  %15 = load i32, i32* %11, align 4                    ; <i32> [#uses=1]
   %16 = shl i32 %15, 1                            ; <i32> [#uses=1]
   %17 = icmp sgt i32 %16, undef                   ; <i1> [#uses=1]
   %indvar.next = add i64 %indvar, 1               ; <i64> [#uses=1]
   br i1 %17, label %bb, label %bb2
 
 bb2:                                              ; preds = %bb, %entry
-  %18 = getelementptr inbounds %struct.RtreeNode* %pNode, i64 0, i32 3 ; <i32*> [#uses=1]
+  %18 = getelementptr inbounds %struct.RtreeNode, %struct.RtreeNode* %pNode, i64 0, i32 3 ; <i32*> [#uses=1]
   store i32 1, i32* %18, align 4
   ret void
 }
diff --git a/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll b/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll
index 006a02a43b17..e1ca3fd2a97d 100644
--- a/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll
+++ b/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll
@@ -23,7 +23,7 @@ entry:
   br i1 %tobool.i, label %if.then.i, label %if.end.i
 
 if.then.i:                                        ; preds = %entry
-  %call1.i = call i32 @warn_dlerror(i8* getelementptr inbounds ([45 x i8]* @.str76843, i32 0, i32 0)) nounwind ; <i32> [#uses=0]
+  %call1.i = call i32 @warn_dlerror(i8* getelementptr inbounds ([45 x i8], [45 x i8]* @.str76843, i32 0, i32 0)) nounwind ; <i32> [#uses=0]
   store i32 -1, i32* %retval.i
   br label %lt_init.exit
 
@@ -32,13 +32,12 @@ if.end.i:                                         ; preds = %entry
   br label %lt_init.exit
 
 lt_init.exit:                                     ; preds = %if.end.i, %if.then.i
-  %3 = load i32* %retval.i                        ; <i32> [#uses=1]
+  %3 = load i32, i32* %retval.i                        ; <i32> [#uses=1]
   call void asm sideeffect "cpuid", "~{ax},~{bx},~{cx},~{dx},~{memory},~{dirflag},~{fpsr},~{flags}"() nounwind
   %4 = call i64 @llvm.readcyclecounter() nounwind ; <i64> [#uses=1]
   %5 = sub i64 %4, %2                             ; <i64> [#uses=1]
-  %6 = atomicrmw add i64* getelementptr inbounds ([1216 x i64]* @__profiling_callsite_timestamps_live, i32 0, i32 51), i64 %5 monotonic
-;CHECK: lock
-;CHECK-NEXT: {{xadd|addq}} %rdx, __profiling_callsite_timestamps_live
+  %6 = atomicrmw add i64* getelementptr inbounds ([1216 x i64], [1216 x i64]* @__profiling_callsite_timestamps_live, i32 0, i32 51), i64 %5 monotonic
+;CHECK: lock {{xadd|addq}} %rdx, __profiling_callsite_timestamps_live
 ;CHECK-NEXT: cmpl $0,
 ;CHECK-NEXT: jne
   %cmp = icmp eq i32 %3, 0                        ; <i1> [#uses=1]
@@ -50,11 +49,11 @@ if.then:                                          ; preds = %lt_init.exit
 
 if.end:                                           ; preds = %if.then, %lt_init.exit
   store i32 0, i32* %retval
-  %7 = load i32* %retval                          ; <i32> [#uses=1]
+  %7 = load i32, i32* %retval                          ; <i32> [#uses=1]
   tail call void asm sideeffect "cpuid", "~{ax},~{bx},~{cx},~{dx},~{memory},~{dirflag},~{fpsr},~{flags}"() nounwind
   %8 = tail call i64 @llvm.readcyclecounter() nounwind ; <i64> [#uses=1]
   %9 = sub i64 %8, %0                             ; <i64> [#uses=1]
-  %10 = atomicrmw add i64* getelementptr inbounds ([1216 x i64]* @__profiling_callsite_timestamps_live, i32 0, i32 50), i64 %9 monotonic
+  %10 = atomicrmw add i64* getelementptr inbounds ([1216 x i64], [1216 x i64]* @__profiling_callsite_timestamps_live, i32 0, i32 50), i64 %9 monotonic
   ret i32 %7
 }
 
diff --git a/test/CodeGen/X86/2009-10-25-RewriterBug.ll b/test/CodeGen/X86/2009-10-25-RewriterBug.ll
index 5b4e818359e9..be18186463d4 100644
--- a/test/CodeGen/X86/2009-10-25-RewriterBug.ll
+++ b/test/CodeGen/X86/2009-10-25-RewriterBug.ll
@@ -6,7 +6,7 @@
 
 define fastcc void @insert_picture_in_dpb(%struct.FrameStore* nocapture %fs, %struct.StorablePicture* %p) nounwind ssp {
 entry:
-  %0 = getelementptr inbounds %struct.FrameStore* %fs, i64 0, i32 12 ; <%struct.StorablePicture**> [#uses=1]
+  %0 = getelementptr inbounds %struct.FrameStore, %struct.FrameStore* %fs, i64 0, i32 12 ; <%struct.StorablePicture**> [#uses=1]
   %1 = icmp eq i32 undef, 0                       ; <i1> [#uses=1]
   br i1 %1, label %bb.i, label %bb36.i
 
@@ -69,7 +69,7 @@ bb38.i:                                           ; preds = %bb66.i, %bb67.prehe
   %23 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %12, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1]
   %indvar248.i = phi i64 [ %indvar.next249.i, %bb66.i ], [ 0, %bb67.preheader.i ] ; <i64> [#uses=3]
   %storemerge52.i = trunc i64 %indvar248.i to i32 ; <i32> [#uses=1]
-  %24 = getelementptr inbounds %struct.StorablePicture* %23, i64 0, i32 19 ; <i32*> [#uses=0]
+  %24 = getelementptr inbounds %struct.StorablePicture, %struct.StorablePicture* %23, i64 0, i32 19 ; <i32*> [#uses=0]
   br i1 undef, label %bb.nph51.i, label %bb66.i
 
 bb.nph51.i:                                       ; preds = %bb38.i
@@ -94,13 +94,13 @@ bb41.i:                                           ; preds = %bb40.i
   br i1 undef, label %bb45.i, label %bb47.i
 
 bb45.i:                                           ; preds = %bb41.i
-  %33 = getelementptr inbounds %struct.StorablePicture* %26, i64 0, i32 5, i64 undef, i64 %32, i64 undef ; <i64*> [#uses=1]
-  %34 = load i64* %33, align 8                    ; <i64> [#uses=1]
+  %33 = getelementptr inbounds %struct.StorablePicture, %struct.StorablePicture* %26, i64 0, i32 5, i64 undef, i64 %32, i64 undef ; <i64*> [#uses=1]
+  %34 = load i64, i64* %33, align 8                    ; <i64> [#uses=1]
   br label %bb47.i
 
 bb47.i:                                           ; preds = %bb45.i, %bb41.i
   %storemerge11.i = phi i64 [ %34, %bb45.i ], [ 0, %bb41.i ] ; <i64> [#uses=0]
-  %scevgep246.i = getelementptr i64* undef, i64 undef ; <i64*> [#uses=0]
+  %scevgep246.i = getelementptr i64, i64* undef, i64 undef ; <i64*> [#uses=0]
   br label %bb64.i
 
 bb57.i:                                           ; preds = %bb40.i, %bb39.i
@@ -110,10 +110,10 @@ bb58.i:                                           ; preds = %bb57.i
   br label %bb60.i
 
 bb60.i:                                           ; preds = %bb58.i, %bb57.i
-  %35 = load i64*** undef, align 8                ; <i64**> [#uses=1]
-  %scevgep256.i = getelementptr i64** %35, i64 %indvar248.i ; <i64**> [#uses=1]
-  %36 = load i64** %scevgep256.i, align 8         ; <i64*> [#uses=1]
-  %scevgep243.i = getelementptr i64* %36, i64 undef ; <i64*> [#uses=1]
+  %35 = load i64**, i64*** undef, align 8                ; <i64**> [#uses=1]
+  %scevgep256.i = getelementptr i64*, i64** %35, i64 %indvar248.i ; <i64**> [#uses=1]
+  %36 = load i64*, i64** %scevgep256.i, align 8         ; <i64*> [#uses=1]
+  %scevgep243.i = getelementptr i64, i64* %36, i64 undef ; <i64*> [#uses=1]
   store i64 -1, i64* %scevgep243.i, align 8
   br label %bb64.i
 
@@ -160,7 +160,7 @@ bb101.i:                                          ; preds = %bb82.i
   br label %bb102.i
 
 bb102.i:                                          ; preds = %bb101.i, %bb83.i
-  %48 = load %struct.StorablePicture** %0, align 8 ; <%struct.StorablePicture*> [#uses=2]
+  %48 = load %struct.StorablePicture*, %struct.StorablePicture** %0, align 8 ; <%struct.StorablePicture*> [#uses=2]
   br i1 undef, label %bb81.i, label %bb104.i
 
 bb104.i:                                          ; preds = %bb102.i, %bb80.i
diff --git a/test/CodeGen/X86/2009-11-16-MachineLICM.ll b/test/CodeGen/X86/2009-11-16-MachineLICM.ll
index fedb2a51f357..3310775c2513 100644
--- a/test/CodeGen/X86/2009-11-16-MachineLICM.ll
+++ b/test/CodeGen/X86/2009-11-16-MachineLICM.ll
@@ -19,19 +19,19 @@ bb:                                               ; preds = %bb, %bb.nph
   %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i64> [#uses=2]
   %tmp9 = shl i64 %indvar, 2                      ; <i64> [#uses=4]
   %tmp1016 = or i64 %tmp9, 1                      ; <i64> [#uses=1]
-  %scevgep = getelementptr float* %x, i64 %tmp1016 ; <float*> [#uses=1]
+  %scevgep = getelementptr float, float* %x, i64 %tmp1016 ; <float*> [#uses=1]
   %tmp1117 = or i64 %tmp9, 2                      ; <i64> [#uses=1]
-  %scevgep12 = getelementptr float* %x, i64 %tmp1117 ; <float*> [#uses=1]
+  %scevgep12 = getelementptr float, float* %x, i64 %tmp1117 ; <float*> [#uses=1]
   %tmp1318 = or i64 %tmp9, 3                      ; <i64> [#uses=1]
-  %scevgep14 = getelementptr float* %x, i64 %tmp1318 ; <float*> [#uses=1]
-  %x_addr.03 = getelementptr float* %x, i64 %tmp9 ; <float*> [#uses=1]
-  %1 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 0), align 16 ; <float> [#uses=1]
+  %scevgep14 = getelementptr float, float* %x, i64 %tmp1318 ; <float*> [#uses=1]
+  %x_addr.03 = getelementptr float, float* %x, i64 %tmp9 ; <float*> [#uses=1]
+  %1 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @g, i64 0, i64 0), align 16 ; <float> [#uses=1]
   store float %1, float* %x_addr.03, align 4
-  %2 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 1), align 4 ; <float> [#uses=1]
+  %2 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @g, i64 0, i64 1), align 4 ; <float> [#uses=1]
   store float %2, float* %scevgep, align 4
-  %3 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 2), align 8 ; <float> [#uses=1]
+  %3 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @g, i64 0, i64 2), align 8 ; <float> [#uses=1]
   store float %3, float* %scevgep12, align 4
-  %4 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 3), align 4 ; <float> [#uses=1]
+  %4 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @g, i64 0, i64 3), align 4 ; <float> [#uses=1]
   store float %4, float* %scevgep14, align 4
   %indvar.next = add i64 %indvar, 1               ; <i64> [#uses=2]
   %exitcond = icmp eq i64 %indvar.next, %tmp      ; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll
index b828c27e7826..1cfd108db653 100644
--- a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll
+++ b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll
@@ -9,7 +9,7 @@ entry:
 ; CHECK: movups L_str+12(%rip), %xmm0
 ; CHECK: movups L_str(%rip), %xmm1
   %tmp0 = alloca [60 x i8], align 1
-  %tmp1 = getelementptr inbounds [60 x i8]* %tmp0, i64 0, i64 0
+  %tmp1 = getelementptr inbounds [60 x i8], [60 x i8]* %tmp0, i64 0, i64 0
   br label %bb1
 
 bb1:
@@ -17,7 +17,7 @@ bb1:
 ; CHECK: movups %xmm0, 12(%rsp)
 ; CHECK: movaps %xmm1, (%rsp)
   %tmp2 = phi i32 [ %tmp3, %bb1 ], [ 0, %entry ]
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp1, i8* getelementptr inbounds ([28 x i8]* @str, i64 0, i64 0), i64 28, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp1, i8* getelementptr inbounds ([28 x i8], [28 x i8]* @str, i64 0, i64 0), i64 28, i32 1, i1 false)
   %tmp3 = add i32 %tmp2, 1
   %tmp4 = icmp eq i32 %tmp3, %count
   br i1 %tmp4, label %bb2, label %bb1
diff --git a/test/CodeGen/X86/2009-11-17-UpdateTerminator.ll b/test/CodeGen/X86/2009-11-17-UpdateTerminator.ll
index 5c1a2bcee2ee..12ebe6336952 100644
--- a/test/CodeGen/X86/2009-11-17-UpdateTerminator.ll
+++ b/test/CodeGen/X86/2009-11-17-UpdateTerminator.ll
@@ -43,8 +43,8 @@ bb14:                                             ; preds = %bb8
   ret i8 1
 
 bb27.outer108:                                    ; preds = %bb13, %bb27.outer
-  %I.2.ph109 = getelementptr i8* %I.2.ph, i64 undef ; <i8*> [#uses=1]
-  %scevgep = getelementptr i8* %I.2.ph, i64 undef ; <i8*> [#uses=0]
+  %I.2.ph109 = getelementptr i8, i8* %I.2.ph, i64 undef ; <i8*> [#uses=1]
+  %scevgep = getelementptr i8, i8* %I.2.ph, i64 undef ; <i8*> [#uses=0]
   br label %bb8
 
 bb56:                                             ; preds = %bb10, %bb8, %bb8, %entry
diff --git a/test/CodeGen/X86/2009-11-25-ImpDefBug.ll b/test/CodeGen/X86/2009-11-25-ImpDefBug.ll
index 396638fb1dbd..0bf13de61275 100644
--- a/test/CodeGen/X86/2009-11-25-ImpDefBug.ll
+++ b/test/CodeGen/X86/2009-11-25-ImpDefBug.ll
@@ -48,7 +48,7 @@ lpad:                                             ; preds = %bb1.i.fragment.cl,
   %.SV10.phi807 = phi i8* [ undef, %bb1.i.fragment.cl ], [ undef, %bb1.i.fragment ], [ undef, %bb5 ] ; <i8*> [#uses=1]
   %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
             cleanup
-  %1 = load i8* %.SV10.phi807, align 8            ; <i8> [#uses=0]
+  %1 = load i8, i8* %.SV10.phi807, align 8            ; <i8> [#uses=0]
   br i1 undef, label %meshBB81.bbcl.disp, label %bb13.fragment.bbcl.disp
 
 bb.i1:                                            ; preds = %bb.i.i.bbcl.disp
diff --git a/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll b/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
index 5c10c55ea3ee..e191a8a3772f 100644
--- a/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
+++ b/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
@@ -9,8 +9,8 @@ entry:
   %b = alloca i32                                 ; <i32*> [#uses=2]
   %a = alloca i32                                 ; <i32*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  %0 = load i32* %b, align 4                      ; <i32> [#uses=1]
-  %1 = load i32* %b, align 4                      ; <i32> [#uses=1]
+  %0 = load i32, i32* %b, align 4                      ; <i32> [#uses=1]
+  %1 = load i32, i32* %b, align 4                      ; <i32> [#uses=1]
   %asmtmp = call i32 asm "$0 = foo ($1, $2)", "=&{ax},%0,r,~{dirflag},~{fpsr},~{flags}"(i32 %0, i32 %1) nounwind ; <i32> [#uses=1]
   store i32 %asmtmp, i32* %a
   br label %return
@@ -30,8 +30,8 @@ entry:
   %b = alloca i32                                 ; <i32*> [#uses=2]
   %a = alloca i32                                 ; <i32*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  %0 = load i32* %b, align 4                      ; <i32> [#uses=1]
-  %1 = load i32* %b, align 4                      ; <i32> [#uses=1]
+  %0 = load i32, i32* %b, align 4                      ; <i32> [#uses=1]
+  %1 = load i32, i32* %b, align 4                      ; <i32> [#uses=1]
   %asmtmp = call i32 asm "$0 = foo ($1, $2)", "=&r,%0,r,~{dirflag},~{fpsr},~{flags}"(i32 %0, i32 %1) nounwind ; <i32> [#uses=1]
   store i32 %asmtmp, i32* %a
   br label %return
diff --git a/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll b/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll
index 65b70a7d4936..97d97872aa63 100644
--- a/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll
+++ b/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll
@@ -30,29 +30,29 @@ define void @leaf() nounwind {
   br label %"@CFE_debug_label_0"
 
 "@CFE_debug_label_0":                             ; preds = %"file foo2.c, line 14, bb2"
-  %r = load %test** bitcast ([1 x i64]* @ptr to %test**), align 8 ; <%test*> [#uses=1]
+  %r = load %test*, %test** bitcast ([1 x i64]* @ptr to %test**), align 8 ; <%test*> [#uses=1]
   store %test* %r, %test** %p, align 8
   br label %"@CFE_debug_label_2"
 
 "@CFE_debug_label_2":                             ; preds = %"@CFE_debug_label_0"
-  %r1 = load %link** bitcast ([1 x i64]* @link_ptr to %link**), align 8 ; <%link*> [#uses=1]
-  %r2 = load %test** %p, align 8                  ; <%test*> [#uses=1]
+  %r1 = load %link*, %link** bitcast ([1 x i64]* @link_ptr to %link**), align 8 ; <%link*> [#uses=1]
+  %r2 = load %test*, %test** %p, align 8                  ; <%test*> [#uses=1]
   %r3 = ptrtoint %test* %r2 to i64                ; <i64> [#uses=1]
   %r4 = inttoptr i64 %r3 to %link**               ; <%link**> [#uses=1]
-  %r5 = getelementptr %link** %r4, i64 1          ; <%link**> [#uses=1]
+  %r5 = getelementptr %link*, %link** %r4, i64 1          ; <%link**> [#uses=1]
   store %link* %r1, %link** %r5, align 8
   br label %"@CFE_debug_label_3"
 
 "@CFE_debug_label_3":                             ; preds = %"@CFE_debug_label_2"
-  %r6 = load %test** %p, align 8                  ; <%test*> [#uses=1]
+  %r6 = load %test*, %test** %p, align 8                  ; <%test*> [#uses=1]
   %r7 = ptrtoint %test* %r6 to i64                ; <i64> [#uses=1]
   %r8 = inttoptr i64 %r7 to %link*                ; <%link*> [#uses=1]
-  %r9 = getelementptr %link* %r8, i64 1           ; <%link*> [#uses=1]
+  %r9 = getelementptr %link, %link* %r8, i64 1           ; <%link*> [#uses=1]
   store %link* %r9, %link** bitcast ([1 x i64]* @link_ptr to %link**), align 8
   br label %"@CFE_debug_label_4"
 
 "@CFE_debug_label_4":                             ; preds = %"@CFE_debug_label_3"
-  %r10 = load %test** %p, align 8                 ; <%test*> [#uses=1]
+  %r10 = load %test*, %test** %p, align 8                 ; <%test*> [#uses=1]
   %r11 = ptrtoint %test* %r10 to i64              ; <i64> [#uses=1]
   %r12 = inttoptr i64 %r11 to i32*                ; <i32*> [#uses=1]
   store i32 1, i32* %r12, align 4
diff --git a/test/CodeGen/X86/20090313-signext.ll b/test/CodeGen/X86/20090313-signext.ll
index b8effa677355..3ea13164112e 100644
--- a/test/CodeGen/X86/20090313-signext.ll
+++ b/test/CodeGen/X86/20090313-signext.ll
@@ -10,7 +10,7 @@ entry:
 	%0 = tail call signext i16 @h() nounwind
 	%1 = sext i16 %0 to i32
 	tail call void @g(i32 %1) nounwind
-	%2 = load i16* @x, align 2
+	%2 = load i16, i16* @x, align 2
 	ret i16 %2
 }
 
diff --git a/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll b/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
index 850f678c9c2c..3391f1f5ec41 100644
--- a/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
+++ b/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
@@ -14,8 +14,7 @@ entry:
 ; CHECK: addl $1, %ebx
 ; CHECK: movl %edx, %ecx
 ; CHECK: adcl $0, %ecx
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b ([[REG]])
+; CHECK: lock cmpxchg8b ([[REG]])
 ; CHECK-NEXT: jne
   %0 = atomicrmw add i64* %p, i64 1 seq_cst
   ret void
diff --git a/test/CodeGen/X86/2010-01-13-OptExtBug.ll b/test/CodeGen/X86/2010-01-13-OptExtBug.ll
index d49e2a8d0798..3ecf845f0933 100644
--- a/test/CodeGen/X86/2010-01-13-OptExtBug.ll
+++ b/test/CodeGen/X86/2010-01-13-OptExtBug.ll
@@ -7,23 +7,23 @@ define void @XX(%class.OlsonTimeZone* %this) align 2 {
 entry:
   %call = tail call i8* @_Z15uprv_malloc_4_2v()
   %0 = bitcast i8* %call to double*
-  %tmp = getelementptr inbounds %class.OlsonTimeZone* %this, i32 0, i32 3
-  %tmp2 = load i16* %tmp
-  %tmp525 = getelementptr inbounds %class.OlsonTimeZone* %this, i32 0, i32 0
-  %tmp626 = load i16* %tmp525
+  %tmp = getelementptr inbounds %class.OlsonTimeZone, %class.OlsonTimeZone* %this, i32 0, i32 3
+  %tmp2 = load i16, i16* %tmp
+  %tmp525 = getelementptr inbounds %class.OlsonTimeZone, %class.OlsonTimeZone* %this, i32 0, i32 0
+  %tmp626 = load i16, i16* %tmp525
   %cmp27 = icmp slt i16 %tmp2, %tmp626
   br i1 %cmp27, label %bb.nph, label %for.end
 
 for.cond:
-  %tmp6 = load i16* %tmp5
+  %tmp6 = load i16, i16* %tmp5
   %cmp = icmp slt i16 %inc, %tmp6
   %indvar.next = add i32 %indvar, 1
   br i1 %cmp, label %for.body, label %for.end
 
 bb.nph:
-  %tmp10 = getelementptr inbounds %class.OlsonTimeZone* %this, i32 0, i32 2
-  %tmp17 = getelementptr inbounds %class.OlsonTimeZone* %this, i32 0, i32 1
-  %tmp5 = getelementptr inbounds %class.OlsonTimeZone* %this, i32 0, i32 0
+  %tmp10 = getelementptr inbounds %class.OlsonTimeZone, %class.OlsonTimeZone* %this, i32 0, i32 2
+  %tmp17 = getelementptr inbounds %class.OlsonTimeZone, %class.OlsonTimeZone* %this, i32 0, i32 1
+  %tmp5 = getelementptr inbounds %class.OlsonTimeZone, %class.OlsonTimeZone* %this, i32 0, i32 0
   %tmp29 = sext i16 %tmp2 to i32
   %tmp31 = add i16 %tmp2, 1
   %tmp32 = zext i16 %tmp31 to i32
@@ -34,9 +34,9 @@ for.body:
   %tmp30 = add i32 %indvar, %tmp29
   %tmp33 = add i32 %indvar, %tmp32
   %inc = trunc i32 %tmp33 to i16
-  %tmp11 = load i8** %tmp10
-  %arrayidx = getelementptr i8* %tmp11, i32 %tmp30
-  %tmp12 = load i8* %arrayidx
+  %tmp11 = load i8*, i8** %tmp10
+  %arrayidx = getelementptr i8, i8* %tmp11, i32 %tmp30
+  %tmp12 = load i8, i8* %arrayidx
   br label %for.cond
 
 for.end:
diff --git a/test/CodeGen/X86/2010-01-15-SelectionDAGCycle.ll b/test/CodeGen/X86/2010-01-15-SelectionDAGCycle.ll
index 5d96e4a192f3..6aba39e04bca 100644
--- a/test/CodeGen/X86/2010-01-15-SelectionDAGCycle.ll
+++ b/test/CodeGen/X86/2010-01-15-SelectionDAGCycle.ll
@@ -11,12 +11,12 @@ define void @numvec_(i32* noalias %ncelet, i32* noalias %ncel, i32* noalias %nfa
 "file bug754399.f90, line 184, in inner vector loop at depth 0, bb164":		; preds = %"file bug754399.f90, line 184, in inner vector loop at depth 0, bb164", %"file bug754399.f90, line 1, bb1"
 	%tmp641 = add i64 0, 48		; <i64> [#uses=1]
 	%tmp641642 = inttoptr i64 %tmp641 to <4 x i32>*		; <<4 x i32>*> [#uses=1]
-	%r1258 = load <4 x i32>* %tmp641642, align 4		; <<4 x i32>> [#uses=2]
+	%r1258 = load <4 x i32>, <4 x i32>* %tmp641642, align 4		; <<4 x i32>> [#uses=2]
 	%r1295 = extractelement <4 x i32> %r1258, i32 3		; <i32> [#uses=1]
 	%r1296 = sext i32 %r1295 to i64		; <i64> [#uses=1]
 	%r1297 = add i64 %r1296, -1		; <i64> [#uses=1]
-	%r1298183 = getelementptr [0 x i32]* %ismbs, i64 0, i64 %r1297		; <i32*> [#uses=1]
-	%r1298184 = load i32* %r1298183, align 4		; <i32> [#uses=1]
+	%r1298183 = getelementptr [0 x i32], [0 x i32]* %ismbs, i64 0, i64 %r1297		; <i32*> [#uses=1]
+	%r1298184 = load i32, i32* %r1298183, align 4		; <i32> [#uses=1]
 	%r1301 = extractelement <4 x i32> %r1037, i32 3		; <i32> [#uses=1]
 	%r1302 = mul i32 %r1298184, %r1301		; <i32> [#uses=1]
 	%r1306 = insertelement <4 x i32> zeroinitializer, i32 %r1302, i32 3		; <<4 x i32>> [#uses=1]
diff --git a/test/CodeGen/X86/2010-01-18-DbgValue.ll b/test/CodeGen/X86/2010-01-18-DbgValue.ll
index b21846d39494..db56ae65d51e 100644
--- a/test/CodeGen/X86/2010-01-18-DbgValue.ll
+++ b/test/CodeGen/X86/2010-01-18-DbgValue.ll
@@ -12,17 +12,17 @@ entry:
   %retval = alloca double                         ; <double*> [#uses=2]
   %0 = alloca double                              ; <double*> [#uses=2]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.declare(metadata %struct.Rect* %my_r0, metadata !0, metadata !{!"0x102"}), !dbg !15
-  %1 = getelementptr inbounds %struct.Rect* %my_r0, i32 0, i32 0, !dbg !16 ; <%struct.Pt*> [#uses=1]
-  %2 = getelementptr inbounds %struct.Pt* %1, i32 0, i32 0, !dbg !16 ; <double*> [#uses=1]
-  %3 = load double* %2, align 8, !dbg !16         ; <double> [#uses=1]
+  call void @llvm.dbg.declare(metadata %struct.Rect* %my_r0, metadata !0, metadata !DIExpression()), !dbg !15
+  %1 = getelementptr inbounds %struct.Rect, %struct.Rect* %my_r0, i32 0, i32 0, !dbg !16 ; <%struct.Pt*> [#uses=1]
+  %2 = getelementptr inbounds %struct.Pt, %struct.Pt* %1, i32 0, i32 0, !dbg !16 ; <double*> [#uses=1]
+  %3 = load double, double* %2, align 8, !dbg !16         ; <double> [#uses=1]
   store double %3, double* %0, align 8, !dbg !16
-  %4 = load double* %0, align 8, !dbg !16         ; <double> [#uses=1]
+  %4 = load double, double* %0, align 8, !dbg !16         ; <double> [#uses=1]
   store double %4, double* %retval, align 8, !dbg !16
   br label %return, !dbg !16
 
 return:                                           ; preds = %entry
-  %retval1 = load double* %retval, !dbg !16       ; <double> [#uses=1]
+  %retval1 = load double, double* %retval, !dbg !16       ; <double> [#uses=1]
   ret double %retval1, !dbg !16
 }
 
@@ -31,25 +31,25 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!3}
 !llvm.module.flags = !{!21}
 
-!0 = !{!"0x101\00my_r0\0011\000", !1, !2, !7} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00foo\00foo\00foo\0011\000\001\000\006\000\000\0011", !19, !2, !4, null, double (%struct.Rect*)* @foo, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !19} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\000\00\000\00\000", !19, !20, !20, !18, null, null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !19, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "my_r0", line: 11, arg: 0, scope: !1, file: !2, type: !7)
+!1 = !DISubprogram(name: "foo", linkageName: "foo", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 11, file: !19, scope: !2, type: !4, function: double (%struct.Rect*)* @foo)
+!2 = !DIFile(filename: "b2.c", directory: "/tmp/")
+!3 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: false, emissionKind: 0, file: !19, enums: !20, retainedTypes: !20, subprograms: !18)
+!4 = !DISubroutineType(types: !5)
 !5 = !{!6, !7}
-!6 = !{!"0x24\00double\000\0064\0064\000\000\004", !19, !2} ; [ DW_TAG_base_type ]
-!7 = !{!"0x13\00Rect\006\00256\0064\000\000\000", !19, !2, null, !8, null, null, null} ; [ DW_TAG_structure_type ] [Rect] [line 6, size 256, align 64, offset 0] [def] [from ]
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 64, encoding: DW_ATE_float)
+!7 = !DICompositeType(tag: DW_TAG_structure_type, name: "Rect", line: 6, size: 256, align: 64, file: !19, scope: !2, elements: !8)
 !8 = !{!9, !14}
-!9 = !{!"0xd\00P1\007\00128\0064\000\000", !19, !7, !10} ; [ DW_TAG_member ]
-!10 = !{!"0x13\00Pt\001\00128\0064\000\000\000", !19, !2, null, !11, null, null, null} ; [ DW_TAG_structure_type ] [Pt] [line 1, size 128, align 64, offset 0] [def] [from ]
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "P1", line: 7, size: 128, align: 64, file: !19, scope: !7, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_structure_type, name: "Pt", line: 1, size: 128, align: 64, file: !19, scope: !2, elements: !11)
 !11 = !{!12, !13}
-!12 = !{!"0xd\00x\002\0064\0064\000\000", !19, !10, !6} ; [ DW_TAG_member ]
-!13 = !{!"0xd\00y\003\0064\0064\0064\000", !19, !10, !6} ; [ DW_TAG_member ]
-!14 = !{!"0xd\00P2\008\00128\0064\00128\000", !19, !7, !10} ; [ DW_TAG_member ]
-!15 = !MDLocation(line: 11, scope: !1)
-!16 = !MDLocation(line: 12, scope: !17)
-!17 = !{!"0xb\0011\000\000", !19, !1} ; [ DW_TAG_lexical_block ]
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 2, size: 64, align: 64, file: !19, scope: !10, baseType: !6)
+!13 = !DIDerivedType(tag: DW_TAG_member, name: "y", line: 3, size: 64, align: 64, offset: 64, file: !19, scope: !10, baseType: !6)
+!14 = !DIDerivedType(tag: DW_TAG_member, name: "P2", line: 8, size: 128, align: 64, offset: 128, file: !19, scope: !7, baseType: !10)
+!15 = !DILocation(line: 11, scope: !1)
+!16 = !DILocation(line: 12, scope: !17)
+!17 = distinct !DILexicalBlock(line: 11, column: 0, file: !19, scope: !1)
 !18 = !{!1}
-!19 = !{!"b2.c", !"/tmp/"}
-!20 = !{i32 0}
-!21 = !{i32 1, !"Debug Info Version", i32 2}
+!19 = !DIFile(filename: "b2.c", directory: "/tmp/")
+!20 = !{}
+!21 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/2010-01-19-OptExtBug.ll b/test/CodeGen/X86/2010-01-19-OptExtBug.ll
index ec24e73c34ac..def8dd31978b 100644
--- a/test/CodeGen/X86/2010-01-19-OptExtBug.ll
+++ b/test/CodeGen/X86/2010-01-19-OptExtBug.ll
@@ -21,7 +21,7 @@ bb7:                                              ; preds = %bb6
   unreachable
 
 bb9:                                              ; preds = %bb6
-  %0 = load i8* undef, align 1                    ; <i8> [#uses=3]
+  %0 = load i8, i8* undef, align 1                    ; <i8> [#uses=3]
   br i1 undef, label %bb12, label %bb10
 
 bb10:                                             ; preds = %bb9
diff --git a/test/CodeGen/X86/2010-02-01-DbgValueCrash.ll b/test/CodeGen/X86/2010-02-01-DbgValueCrash.ll
index b85f1afea0cf..e65edac86ecc 100644
--- a/test/CodeGen/X86/2010-02-01-DbgValueCrash.ll
+++ b/test/CodeGen/X86/2010-02-01-DbgValueCrash.ll
@@ -8,7 +8,7 @@
 
 define i32 @"main(tart.core.String[])->int32"(i32 %args) {
 entry:
-  tail call void @llvm.dbg.value(metadata %tart.reflect.ComplexType* @.type.SwitchStmtTest, i64 0, metadata !8, metadata !{!"0x102"})
+  tail call void @llvm.dbg.value(metadata %tart.reflect.ComplexType* @.type.SwitchStmtTest, i64 0, metadata !8, metadata !DIExpression()), !dbg !DILocation(scope: !9)
   tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2]
   ret i32 3
 }
@@ -16,20 +16,20 @@ entry:
 declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone
 declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone
 
-!0 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\001\00\000\00\000", !15, !16, !16, null, null, null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"0x26\00\000\00192\0064\000\000", !15, !0, !2} ; [ DW_TAG_const_type ]
-!2 = !{!"0x13\00C\001\00192\0064\000\000\000", !15, !0, null, !3, null, null, null} ; [ DW_TAG_structure_type ] [C] [line 1, size 192, align 64, offset 0] [def] [from ]
+!0 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 0, file: !15, enums: !16, retainedTypes: !16)
+!1 = !DIDerivedType(tag: DW_TAG_const_type, size: 192, align: 64, file: !15, scope: !0, baseType: !2)
+!2 = !DICompositeType(tag: DW_TAG_structure_type, name: "C", line: 1, size: 192, align: 64, file: !15, scope: !0, elements: !3)
 !3 = !{!4, !6, !7}
-!4 = !{!"0xd\00x\001\0064\0064\000\000", !15, !2, !5} ; [ DW_TAG_member ]
-!5 = !{!"0x24\00double\000\0064\0064\000\000\004", !15, !0} ; [ DW_TAG_base_type ]
-!6 = !{!"0xd\00y\001\0064\0064\0064\000", !15, !2, !5} ; [ DW_TAG_member ]
-!7 = !{!"0xd\00z\001\0064\0064\00128\000", !15, !2, !5} ; [ DW_TAG_member ]
-!8 = !{!"0x100\00t\005\000", !9, !0, !2} ; [ DW_TAG_auto_variable ]
-!9 = !{!"0xb\000\000\000", null, !10}        ; [ DW_TAG_lexical_block ]
-!10 = !{!"0x2e\00foo\00foo\00foo\004\000\001\000\006\000\000\000", i32 0, !0, !11, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!11 = !{!"0x15\00\000\000\000\000\000\000", !15, !0, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 1, size: 64, align: 64, file: !15, scope: !2, baseType: !5)
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 64, encoding: DW_ATE_float)
+!6 = !DIDerivedType(tag: DW_TAG_member, name: "y", line: 1, size: 64, align: 64, offset: 64, file: !15, scope: !2, baseType: !5)
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "z", line: 1, size: 64, align: 64, offset: 128, file: !15, scope: !2, baseType: !5)
+!8 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "t", line: 5, scope: !9, file: !0, type: !2)
+!9 = distinct !DILexicalBlock(line: 0, column: 0, file: null, scope: !10)
+!10 = !DISubprogram(name: "foo", linkageName: "foo", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !0, type: !11)
+!11 = !DISubroutineType(types: !12)
 !12 = !{!13}
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", !15, !0} ; [ DW_TAG_base_type ]
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !14 = !{%tart.reflect.ComplexType* @.type.SwitchStmtTest}
-!15 = !{!"sm.c", !""}
+!15 = !DIFile(filename: "sm.c", directory: "")
 !16 = !{i32 0}
diff --git a/test/CodeGen/X86/2010-02-04-SchedulerBug.ll b/test/CodeGen/X86/2010-02-04-SchedulerBug.ll
index c966e21d52df..51686ea3f775 100644
--- a/test/CodeGen/X86/2010-02-04-SchedulerBug.ll
+++ b/test/CodeGen/X86/2010-02-04-SchedulerBug.ll
@@ -6,13 +6,13 @@
 
 define void @t(i32 %cNum, i64 %max) nounwind optsize ssp noimplicitfloat {
 entry:
-  %0 = load %struct.b_t** null, align 4 ; <%struct.b_t*> [#uses=1]
-  %1 = getelementptr inbounds %struct.b_t* %0, i32 %cNum, i32 5 ; <i64*> [#uses=1]
-  %2 = load i64* %1, align 4                      ; <i64> [#uses=1]
+  %0 = load %struct.b_t*, %struct.b_t** null, align 4 ; <%struct.b_t*> [#uses=1]
+  %1 = getelementptr inbounds %struct.b_t, %struct.b_t* %0, i32 %cNum, i32 5 ; <i64*> [#uses=1]
+  %2 = load i64, i64* %1, align 4                      ; <i64> [#uses=1]
   %3 = icmp ult i64 %2, %max            ; <i1> [#uses=1]
-  %4 = getelementptr inbounds %struct.a_t* null, i32 0, i32 7 ; <i64**> [#uses=1]
-  %5 = load i64** %4, align 4                     ; <i64*> [#uses=0]
-  %6 = load i64* null, align 4                    ; <i64> [#uses=1]
+  %4 = getelementptr inbounds %struct.a_t, %struct.a_t* null, i32 0, i32 7 ; <i64**> [#uses=1]
+  %5 = load i64*, i64** %4, align 4                     ; <i64*> [#uses=0]
+  %6 = load i64, i64* null, align 4                    ; <i64> [#uses=1]
   br i1 %3, label %bb2, label %bb
 
 bb:                                               ; preds = %entry
diff --git a/test/CodeGen/X86/2010-02-11-NonTemporal.ll b/test/CodeGen/X86/2010-02-11-NonTemporal.ll
index f9cca8c70c76..5d74db1160c5 100644
--- a/test/CodeGen/X86/2010-02-11-NonTemporal.ll
+++ b/test/CodeGen/X86/2010-02-11-NonTemporal.ll
@@ -11,8 +11,8 @@ define void @sub_(i32* noalias %n) {
 	%i = alloca i32, align 4
 	%"$LCS_0" = alloca i64, align 8
 	%"$LCS_S2" = alloca <2 x double>, align 16
-	%r9 = load <2 x double>* %"$LCS_S2", align 8
-	%r10 = load i64* %"$LCS_0", align 8
+	%r9 = load <2 x double>, <2 x double>* %"$LCS_S2", align 8
+	%r10 = load i64, i64* %"$LCS_0", align 8
 	%r11 = inttoptr i64 %r10 to <2 x double>*
 	store <2 x double> %r9, <2 x double>* %r11, align 16, !nontemporal !0
 	br label %"file movnt.f90, line 18, bb5"
diff --git a/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll b/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll
index 739a27a3e17c..193f8cfcd52b 100644
--- a/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll
+++ b/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll
@@ -228,7 +228,7 @@ entry:
   unreachable
 
 "67":                                             ; preds = %"65"
-  %1 = load i32* undef, align 4                   ; <i32> [#uses=0]
+  %1 = load i32, i32* undef, align 4                   ; <i32> [#uses=0]
   br label %"100"
 
 "82":                                             ; preds = %"61", %"60", %"59"
diff --git a/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll b/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll
index 060c535dd778..c3b12edf4ceb 100644
--- a/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll
+++ b/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll
@@ -15,31 +15,31 @@
 ; Move return address from temporary register (%ebp) to new stack location (60(%esp))
 ; CHECK: movl [[REGISTER]], 60(%esp)
 
-%tupl_p = type [9 x i32]*
+%tupl = type [9 x i32]
 
 declare fastcc void @l297(i32 %r10, i32 %r9, i32 %r8, i32 %r7, i32 %r6, i32 %r5, i32 %r3, i32 %r2) noreturn nounwind
 declare fastcc void @l298(i32 %r10, i32 %r9, i32 %r4) noreturn nounwind
 
-define fastcc void @l186(%tupl_p %r1) noreturn nounwind {
+define fastcc void @l186(%tupl* %r1) noreturn nounwind {
 entry:
-  %ptr1 = getelementptr %tupl_p %r1, i32 0, i32 0
-  %r2 = load i32* %ptr1
-  %ptr3 = getelementptr %tupl_p %r1, i32 0, i32 1
-  %r3 = load i32* %ptr3
-  %ptr5 = getelementptr %tupl_p %r1, i32 0, i32 2
-  %r4 = load i32* %ptr5
-  %ptr7 = getelementptr %tupl_p %r1, i32 0, i32 3
-  %r5 = load i32* %ptr7
-  %ptr9 = getelementptr %tupl_p %r1, i32 0, i32 4
-  %r6 = load i32* %ptr9
-  %ptr11 = getelementptr %tupl_p %r1, i32 0, i32 5
-  %r7 = load i32* %ptr11
-  %ptr13 = getelementptr %tupl_p %r1, i32 0, i32 6
-  %r8 = load i32* %ptr13
-  %ptr15 = getelementptr %tupl_p %r1, i32 0, i32 7
-  %r9 = load i32* %ptr15
-  %ptr17 = getelementptr %tupl_p %r1, i32 0, i32 8
-  %r10 = load i32* %ptr17
+  %ptr1 = getelementptr %tupl, %tupl* %r1, i32 0, i32 0
+  %r2 = load i32, i32* %ptr1
+  %ptr3 = getelementptr %tupl, %tupl* %r1, i32 0, i32 1
+  %r3 = load i32, i32* %ptr3
+  %ptr5 = getelementptr %tupl, %tupl* %r1, i32 0, i32 2
+  %r4 = load i32, i32* %ptr5
+  %ptr7 = getelementptr %tupl, %tupl* %r1, i32 0, i32 3
+  %r5 = load i32, i32* %ptr7
+  %ptr9 = getelementptr %tupl, %tupl* %r1, i32 0, i32 4
+  %r6 = load i32, i32* %ptr9
+  %ptr11 = getelementptr %tupl, %tupl* %r1, i32 0, i32 5
+  %r7 = load i32, i32* %ptr11
+  %ptr13 = getelementptr %tupl, %tupl* %r1, i32 0, i32 6
+  %r8 = load i32, i32* %ptr13
+  %ptr15 = getelementptr %tupl, %tupl* %r1, i32 0, i32 7
+  %r9 = load i32, i32* %ptr15
+  %ptr17 = getelementptr %tupl, %tupl* %r1, i32 0, i32 8
+  %r10 = load i32, i32* %ptr17
   %cond = icmp eq i32 %r10, 3
   br i1 %cond, label %true, label %false
 
diff --git a/test/CodeGen/X86/2010-02-23-RematImplicitSubreg.ll b/test/CodeGen/X86/2010-02-23-RematImplicitSubreg.ll
index 4a26ba088e5c..6fe31b6d1672 100644
--- a/test/CodeGen/X86/2010-02-23-RematImplicitSubreg.ll
+++ b/test/CodeGen/X86/2010-02-23-RematImplicitSubreg.ll
@@ -16,25 +16,25 @@ entry:
   br i1 undef, label %for.end, label %for.body
 
 for.body:                                         ; preds = %if.end40, %entry
-  %tmp6 = load i8* undef, align 2                 ; <i8> [#uses=3]
+  %tmp6 = load i8, i8* undef, align 2                 ; <i8> [#uses=3]
   %conv11 = sext i8 %tmp6 to i64                  ; <i64> [#uses=1]
   %cmp15 = icmp slt i64 %conv11, undef            ; <i1> [#uses=1]
   br i1 %cmp15, label %if.end, label %if.then
 
 if.then:                                          ; preds = %for.body
   %conv18 = sext i8 %tmp6 to i32                  ; <i32> [#uses=1]
-  %call = tail call i32 (...)* @invalid(i32 0, i32 0, i32 %conv18) nounwind ; <i32> [#uses=0]
+  %call = tail call i32 (...) @invalid(i32 0, i32 0, i32 %conv18) nounwind ; <i32> [#uses=0]
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %for.body
   %index.0 = phi i8 [ 0, %if.then ], [ %tmp6, %for.body ] ; <i8> [#uses=1]
   store i8 %index.0, i8* undef
-  %tmp24 = load i8* undef                         ; <i8> [#uses=2]
+  %tmp24 = load i8, i8* undef                         ; <i8> [#uses=2]
   br i1 undef, label %if.end40, label %if.then36
 
 if.then36:                                        ; preds = %if.end
   %conv38 = sext i8 %tmp24 to i32                 ; <i32> [#uses=1]
-  %call39 = tail call i32 (...)* @invalid(i32 0, i32 0, i32 %conv38) nounwind ; <i32> [#uses=0]
+  %call39 = tail call i32 (...) @invalid(i32 0, i32 0, i32 %conv38) nounwind ; <i32> [#uses=0]
   br label %if.end40
 
 if.end40:                                         ; preds = %if.then36, %if.end
diff --git a/test/CodeGen/X86/2010-03-05-ConstantFoldCFG.ll b/test/CodeGen/X86/2010-03-05-ConstantFoldCFG.ll
index 5de19662fffb..5a9ce90155d2 100644
--- a/test/CodeGen/X86/2010-03-05-ConstantFoldCFG.ll
+++ b/test/CodeGen/X86/2010-03-05-ConstantFoldCFG.ll
@@ -22,7 +22,7 @@ bb2.outer.i:                                      ; preds = %bb9.i, %bb2
 bb1.i:                                            ; preds = %bb1.i, %bb2.outer.i
   %indvar5.i = phi i64 [ %tmp, %bb1.i ], [ 0, %bb2.outer.i ] ; <i64> [#uses=1]
   %tmp = add i64 %indvar5.i, 1                    ; <i64> [#uses=2]
-  %scevgep.i = getelementptr double* undef, i64 %tmp ; <double*> [#uses=0]
+  %scevgep.i = getelementptr double, double* undef, i64 %tmp ; <double*> [#uses=0]
   br i1 undef, label %bb1.i, label %bb5.preheader.i
 
 bb5.preheader.i:                                  ; preds = %bb1.i, %bb2.outer.i
diff --git a/test/CodeGen/X86/2010-03-17-ISelBug.ll b/test/CodeGen/X86/2010-03-17-ISelBug.ll
index ba21902f7d0a..e1d3c10a80ea 100644
--- a/test/CodeGen/X86/2010-03-17-ISelBug.ll
+++ b/test/CodeGen/X86/2010-03-17-ISelBug.ll
@@ -9,7 +9,7 @@
 define i32* @t() align 2 nounwind {
 entry:
   %operation = alloca %struct.PPOperation, align 8 ; <%struct.PPOperation*> [#uses=2]
-  %0 = load i32*** null, align 4  ; [#uses=1]
+  %0 = load i32**, i32*** null, align 4  ; [#uses=1]
   %1 = ptrtoint i32** %0 to i32   ; <i32> [#uses=1]
   %2 = sub nsw i32 %1, undef                      ; <i32> [#uses=2]
   br i1 false, label %bb20, label %bb.nph380
@@ -18,10 +18,10 @@ bb20:                                             ; preds = %entry
   ret i32* null
 
 bb.nph380:                                        ; preds = %entry
-  %scevgep403 = getelementptr %struct.PPOperation* %operation, i32 0, i32 1, i32 0, i32 2 ; <i32*> [#uses=1]
+  %scevgep403 = getelementptr %struct.PPOperation, %struct.PPOperation* %operation, i32 0, i32 1, i32 0, i32 2 ; <i32*> [#uses=1]
   %3 = ashr i32 %2, 1                             ; <i32> [#uses=1]
   %tmp405 = and i32 %3, -2                        ; <i32> [#uses=1]
-  %scevgep408 = getelementptr %struct.PPOperation* %operation, i32 0, i32 1, i32 0, i32 1 ; <i16*> [#uses=1]
+  %scevgep408 = getelementptr %struct.PPOperation, %struct.PPOperation* %operation, i32 0, i32 1, i32 0, i32 1 ; <i16*> [#uses=1]
   %tmp410 = and i32 %2, -4                        ; <i32> [#uses=1]
   br label %bb169
 
@@ -29,10 +29,10 @@ bb169:                                            ; preds = %bb169, %bb.nph380
   %index.6379 = phi i32 [ 0, %bb.nph380 ], [ %4, %bb169 ] ; <i32> [#uses=3]
   %tmp404 = mul i32 %index.6379, -2               ; <i32> [#uses=1]
   %tmp406 = add i32 %tmp405, %tmp404              ; <i32> [#uses=1]
-  %scevgep407 = getelementptr i32* %scevgep403, i32 %tmp406 ; <i32*> [#uses=1]
+  %scevgep407 = getelementptr i32, i32* %scevgep403, i32 %tmp406 ; <i32*> [#uses=1]
   %tmp409 = mul i32 %index.6379, -4               ; <i32> [#uses=1]
   %tmp411 = add i32 %tmp410, %tmp409              ; <i32> [#uses=1]
-  %scevgep412 = getelementptr i16* %scevgep408, i32 %tmp411 ; <i16*> [#uses=1]
+  %scevgep412 = getelementptr i16, i16* %scevgep408, i32 %tmp411 ; <i16*> [#uses=1]
   store i16 undef, i16* %scevgep412, align 2
   store i32 undef, i32* %scevgep407, align 4
   %4 = add nsw i32 %index.6379, 1                 ; <i32> [#uses=1]
@@ -50,18 +50,18 @@ entry:
 for.body261.i:                                    ; preds = %for.body261.i, %for.body190
   %line.3300.i = phi i32 [ undef, %for.body190 ], [ %add292.i, %for.body261.i ] ; <i32> [#uses=3]
   %conv268.i = and i32 %line.3300.i, 255          ; <i32> [#uses=1]
-  %tmp278.i = getelementptr [2 x [256 x %struct.bufBit_s]]* %colourLines, i32 undef, i32 %pen.1100, i32 %conv268.i, i32 0 ; <i8**> [#uses=1]
+  %tmp278.i = getelementptr [2 x [256 x %struct.bufBit_s]], [2 x [256 x %struct.bufBit_s]]* %colourLines, i32 undef, i32 %pen.1100, i32 %conv268.i, i32 0 ; <i8**> [#uses=1]
   store i8* undef, i8** %tmp278.i
   %tmp338 = shl i32 %line.3300.i, 3               ; <i32> [#uses=1]
   %tmp339 = and i32 %tmp338, 2040                 ; <i32> [#uses=1]
-  %tmp285.i = getelementptr i8* %scevgep328, i32 %tmp339 ; <i8*> [#uses=1]
+  %tmp285.i = getelementptr i8, i8* %scevgep328, i32 %tmp339 ; <i8*> [#uses=1]
   store i8 undef, i8* %tmp285.i
   %add292.i = add nsw i32 0, %line.3300.i         ; <i32> [#uses=1]
   br i1 undef, label %for.body190, label %for.body261.i
 
 for.body190:                                      ; preds = %for.body261.i, %for.body190, %bb.nph104
   %pen.1100 = phi i32 [ 0, %entry ], [ %inc230, %for.body261.i ], [ %inc230, %for.body190 ] ; <i32> [#uses=3]
-  %scevgep328 = getelementptr [2 x [256 x %struct.bufBit_s]]* %colourLines, i32 undef, i32 %pen.1100, i32 0, i32 1 ; <i8*> [#uses=1]
+  %scevgep328 = getelementptr [2 x [256 x %struct.bufBit_s]], [2 x [256 x %struct.bufBit_s]]* %colourLines, i32 undef, i32 %pen.1100, i32 0, i32 1 ; <i8*> [#uses=1]
   %inc230 = add i32 %pen.1100, 1                  ; <i32> [#uses=2]
   br i1 undef, label %for.body190, label %for.body261.i
 }
diff --git a/test/CodeGen/X86/2010-04-06-SSEDomainFixCrash.ll b/test/CodeGen/X86/2010-04-06-SSEDomainFixCrash.ll
index 864ebf120f6f..2ba4d9aaded8 100644
--- a/test/CodeGen/X86/2010-04-06-SSEDomainFixCrash.ll
+++ b/test/CodeGen/X86/2010-04-06-SSEDomainFixCrash.ll
@@ -19,7 +19,7 @@ invcont64:                                        ; preds = %bb58
   br i1 undef, label %invcont65, label %bb.i.i
 
 bb.i.i:                                           ; preds = %invcont64
-  %1 = load <4 x float>* undef, align 16          ; <<4 x float>> [#uses=5]
+  %1 = load <4 x float>, <4 x float>* undef, align 16          ; <<4 x float>> [#uses=5]
   br i1 undef, label %bb.nph.i.i, label %invcont65
 
 bb.nph.i.i:                                       ; preds = %bb.i.i
diff --git a/test/CodeGen/X86/2010-04-08-CoalescerBug.ll b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll
index 5e86ecf42b11..5adf99e3e47b 100644
--- a/test/CodeGen/X86/2010-04-08-CoalescerBug.ll
+++ b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll
@@ -14,9 +14,9 @@ entry:
 ; CHECK-LABEL: t:
 ; CHECK: addq $12, %rsi
   %BitValueArray = alloca [32 x i32], align 4
-  %tmp2 = getelementptr inbounds %struct.F* %this, i64 0, i32 0
-  %tmp3 = load %struct.FC** %tmp2, align 8
-  %tmp4 = getelementptr inbounds %struct.FC* %tmp3, i64 0, i32 1, i64 0
+  %tmp2 = getelementptr inbounds %struct.F, %struct.F* %this, i64 0, i32 0
+  %tmp3 = load %struct.FC*, %struct.FC** %tmp2, align 8
+  %tmp4 = getelementptr inbounds %struct.FC, %struct.FC* %tmp3, i64 0, i32 1, i64 0
   %tmp5 = bitcast [32 x i32]* %BitValueArray to i8*
   %tmp6 = bitcast i32* %tmp4 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp5, i8* %tmp6, i64 128, i32 4, i1 false)
diff --git a/test/CodeGen/X86/2010-04-13-AnalyzeBranchCrash.ll b/test/CodeGen/X86/2010-04-13-AnalyzeBranchCrash.ll
index fadbd2191989..6c8dbbe5eff5 100644
--- a/test/CodeGen/X86/2010-04-13-AnalyzeBranchCrash.ll
+++ b/test/CodeGen/X86/2010-04-13-AnalyzeBranchCrash.ll
@@ -12,7 +12,7 @@ entry:
   ]
 
 if.then:                                          ; preds = %entry, %entry
-  %tmp69 = load float* null, align 4              ; <float> [#uses=1]
+  %tmp69 = load float, float* null, align 4              ; <float> [#uses=1]
   %cmp19 = icmp eq %1* null, %scroller            ; <i1> [#uses=2]
   %cond = select i1 %cmp19, float %tmp69, float 0.000000e+00 ; <float> [#uses=1]
   %call36 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*)*)(i8* undef, i8* undef) nounwind optsize ; <i64> [#uses=2]
diff --git a/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll b/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll
deleted file mode 100644
index 60025bfcdc81..000000000000
--- a/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll
+++ /dev/null
@@ -1,100 +0,0 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | FileCheck %s
-; There are no MMX operations here, so we use XMM or i64.
-
-; CHECK: ti8
-define void @ti8(double %a, double %b) nounwind {
-entry:
-        %tmp1 = bitcast double %a to <8 x i8>
-        %tmp2 = bitcast double %b to <8 x i8>
-        %tmp3 = add <8 x i8> %tmp1, %tmp2
-; CHECK:  paddb
-        store <8 x i8> %tmp3, <8 x i8>* null
-        ret void
-}
-
-; CHECK: ti16
-define void @ti16(double %a, double %b) nounwind {
-entry:
-        %tmp1 = bitcast double %a to <4 x i16>
-        %tmp2 = bitcast double %b to <4 x i16>
-        %tmp3 = add <4 x i16> %tmp1, %tmp2
-; CHECK:  paddw
-        store <4 x i16> %tmp3, <4 x i16>* null
-        ret void
-}
-
-; CHECK: ti32
-define void @ti32(double %a, double %b) nounwind {
-entry:
-        %tmp1 = bitcast double %a to <2 x i32>
-        %tmp2 = bitcast double %b to <2 x i32>
-        %tmp3 = add <2 x i32> %tmp1, %tmp2
-; CHECK:  paddd
-        store <2 x i32> %tmp3, <2 x i32>* null
-        ret void
-}
-
-; CHECK: ti64
-define void @ti64(double %a, double %b) nounwind {
-entry:
-        %tmp1 = bitcast double %a to <1 x i64>
-        %tmp2 = bitcast double %b to <1 x i64>
-        %tmp3 = add <1 x i64> %tmp1, %tmp2
-; CHECK:  addq
-        store <1 x i64> %tmp3, <1 x i64>* null
-        ret void
-}
-
-; MMX intrinsics calls get us MMX instructions.
-; CHECK: ti8a
-define void @ti8a(double %a, double %b) nounwind {
-entry:
-        %tmp1 = bitcast double %a to x86_mmx
-; CHECK: movdq2q
-        %tmp2 = bitcast double %b to x86_mmx
-; CHECK: movdq2q
-        %tmp3 = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %tmp1, x86_mmx %tmp2)
-        store x86_mmx %tmp3, x86_mmx* null
-        ret void
-}
-
-; CHECK: ti16a
-define void @ti16a(double %a, double %b) nounwind {
-entry:
-        %tmp1 = bitcast double %a to x86_mmx
-; CHECK: movdq2q
-        %tmp2 = bitcast double %b to x86_mmx
-; CHECK: movdq2q
-        %tmp3 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %tmp1, x86_mmx %tmp2)
-        store x86_mmx %tmp3, x86_mmx* null
-        ret void
-}
-
-; CHECK: ti32a
-define void @ti32a(double %a, double %b) nounwind {
-entry:
-        %tmp1 = bitcast double %a to x86_mmx
-; CHECK: movdq2q
-        %tmp2 = bitcast double %b to x86_mmx
-; CHECK: movdq2q
-        %tmp3 = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %tmp1, x86_mmx %tmp2)
-        store x86_mmx %tmp3, x86_mmx* null
-        ret void
-}
-
-; CHECK: ti64a
-define void @ti64a(double %a, double %b) nounwind {
-entry:
-        %tmp1 = bitcast double %a to x86_mmx
-; CHECK: movdq2q
-        %tmp2 = bitcast double %b to x86_mmx
-; CHECK: movdq2q
-        %tmp3 = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %tmp1, x86_mmx %tmp2)
-        store x86_mmx %tmp3, x86_mmx* null
-        ret void
-}
- 
-declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx)
diff --git a/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll b/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll
index cbf5502e1c05..4711d5274675 100644
--- a/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll
+++ b/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll
@@ -47,9 +47,9 @@ try.handler:                                      ; preds = %entry
 match:                                            ; preds = %try.handler
   %4 = call i8* @__cxa_begin_catch(i8* %exc1)     ; <i8*> [#uses=1]
   %5 = bitcast i8* %4 to i32*                     ; <i32*> [#uses=1]
-  %6 = load i32* %5                               ; <i32> [#uses=1]
+  %6 = load i32, i32* %5                               ; <i32> [#uses=1]
   store i32 %6, i32* %0
-  %call = invoke i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), %struct.S* %s2)
+  %call = invoke i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), %struct.S* %s2)
           to label %invoke.cont2 unwind label %match.handler ; <i32> [#uses=0]
 
 invoke.cont2:                                     ; preds = %match
@@ -80,7 +80,7 @@ invoke.cont5:                                     ; preds = %match.end
   br label %cleanup.switch
 
 cleanup.switch:                                   ; preds = %invoke.cont5
-  %tmp = load i32* %cleanup.dst                   ; <i32> [#uses=1]
+  %tmp = load i32, i32* %cleanup.dst                   ; <i32> [#uses=1]
   switch i32 %tmp, label %cleanup.end [
     i32 1, label %cleanup.pad
     i32 2, label %cleanup.pad4
@@ -99,7 +99,7 @@ finally:                                          ; preds = %catch.next, %cleanu
   br label %cleanup.switch9
 
 cleanup.switch9:                                  ; preds = %finally
-  %tmp8 = load i32* %cleanup.dst7                 ; <i32> [#uses=1]
+  %tmp8 = load i32, i32* %cleanup.dst7                 ; <i32> [#uses=1]
   switch i32 %tmp8, label %cleanup.end10 [
     i32 1, label %finally.end
     i32 2, label %finally.throw
@@ -109,17 +109,17 @@ cleanup.end10:                                    ; preds = %cleanup.switch9
   br label %finally.end
 
 finally.throw:                                    ; preds = %cleanup.switch9
-  %8 = load i8** %_rethrow                        ; <i8*> [#uses=1]
+  %8 = load i8*, i8** %_rethrow                        ; <i8*> [#uses=1]
   call void @_Unwind_Resume_or_Rethrow(i8* %8)
   unreachable
 
 finally.end:                                      ; preds = %cleanup.end10, %cleanup.switch9
-  %tmp11 = getelementptr inbounds %struct.S* %s1, i32 0, i32 0 ; <[2 x i8*]*> [#uses=1]
-  %arraydecay = getelementptr inbounds [2 x i8*]* %tmp11, i32 0, i32 0 ; <i8**> [#uses=1]
-  %arrayidx = getelementptr inbounds i8** %arraydecay, i32 1 ; <i8**> [#uses=1]
-  %tmp12 = load i8** %arrayidx                    ; <i8*> [#uses=1]
+  %tmp11 = getelementptr inbounds %struct.S, %struct.S* %s1, i32 0, i32 0 ; <[2 x i8*]*> [#uses=1]
+  %arraydecay = getelementptr inbounds [2 x i8*], [2 x i8*]* %tmp11, i32 0, i32 0 ; <i8**> [#uses=1]
+  %arrayidx = getelementptr inbounds i8*, i8** %arraydecay, i32 1 ; <i8**> [#uses=1]
+  %tmp12 = load i8*, i8** %arrayidx                    ; <i8*> [#uses=1]
   store i8* %tmp12, i8** %retval
-  %9 = load i8** %retval                          ; <i8*> [#uses=1]
+  %9 = load i8*, i8** %retval                          ; <i8*> [#uses=1]
   ret i8* %9
 }
 
diff --git a/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll b/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll
index 86be390b8228..5a9c02109343 100644
--- a/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll
+++ b/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll
@@ -23,9 +23,9 @@ entry:
   store i8* %asmresult, i8** %ret
   store i8* %asmresult1, i8** %p
   store i32 %asmresult2, i32* %t
-  %tmp = load i8** %ret                           ; <i8*> [#uses=1]
+  %tmp = load i8*, i8** %ret                           ; <i8*> [#uses=1]
   store i8* %tmp, i8** %retval
-  %1 = load i8** %retval                          ; <i8*> [#uses=1]
+  %1 = load i8*, i8** %retval                          ; <i8*> [#uses=1]
   ret i8* %1
 }
 
diff --git a/test/CodeGen/X86/2010-05-07-ldconvert.ll b/test/CodeGen/X86/2010-05-07-ldconvert.ll
index 0ba6a8fd6d71..a0c3c95ef607 100644
--- a/test/CodeGen/X86/2010-05-07-ldconvert.ll
+++ b/test/CodeGen/X86/2010-05-07-ldconvert.ll
@@ -9,7 +9,7 @@ entry:
   %tmp = call x86_fp80 @llvm.powi.f80(x86_fp80 0xK3FFF8000000000000000, i32 -64) ; <x86_fp80> [#uses=1]
   %conv = fptosi x86_fp80 %tmp to i32             ; <i32> [#uses=1]
   store i32 %conv, i32* %r
-  %tmp1 = load i32* %r                            ; <i32> [#uses=1]
+  %tmp1 = load i32, i32* %r                            ; <i32> [#uses=1]
   %tobool = icmp ne i32 %tmp1, 0                  ; <i1> [#uses=1]
   br i1 %tobool, label %if.then, label %if.end
 
@@ -18,7 +18,7 @@ if.then:                                          ; preds = %entry
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
-  %0 = load i32* %retval                          ; <i32> [#uses=1]
+  %0 = load i32, i32* %retval                          ; <i32> [#uses=1]
   ret i32 %0
 }
 
diff --git a/test/CodeGen/X86/2010-05-10-DAGCombinerBug.ll b/test/CodeGen/X86/2010-05-10-DAGCombinerBug.ll
index e719da304c53..a6fe310bffa2 100644
--- a/test/CodeGen/X86/2010-05-10-DAGCombinerBug.ll
+++ b/test/CodeGen/X86/2010-05-10-DAGCombinerBug.ll
@@ -4,7 +4,7 @@
 
 define i32 @CXB30130(i32 %num1, i16* nocapture %num2, float* nocapture %num3, double* nocapture %num4) nounwind ssp {
 entry:
-  %0 = load i16* %num2, align 2                   ; <i16> [#uses=2]
+  %0 = load i16, i16* %num2, align 2                   ; <i16> [#uses=2]
   %1 = mul nsw i16 %0, %0                         ; <i16> [#uses=1]
   store i16 %1, i16* %num2, align 2
   ret i32 undef
diff --git a/test/CodeGen/X86/2010-05-16-nosseconversion.ll b/test/CodeGen/X86/2010-05-16-nosseconversion.ll
index 889575cea3ae..2d3f0eb1c5f2 100644
--- a/test/CodeGen/X86/2010-05-16-nosseconversion.ll
+++ b/test/CodeGen/X86/2010-05-16-nosseconversion.ll
@@ -5,7 +5,7 @@
 
 define i32 @foo() nounwind readonly ssp {
 entry:
-  %0 = load i64* @x, align 8                      ; <i64> [#uses=1]
+  %0 = load i64, i64* @x, align 8                      ; <i64> [#uses=1]
   %1 = uitofp i64 %0 to double                    ; <double> [#uses=1]
   %2 = fptosi double %1 to i32                    ; <i32> [#uses=1]
   ret i32 %2
diff --git a/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll b/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll
index 0d30a3f88eb9..3b99e91915f0 100644
--- a/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll
+++ b/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll
@@ -2,18 +2,17 @@
 ; RUN: llc -mtriple=x86_64-pc-linux -O2 -regalloc=basic < %s | FileCheck %s
 ; Test to check .debug_loc support. This test case emits many debug_loc entries.
 
-; CHECK: .short {{.*}} # Loc expr size
-; CHECK-NEXT: .Ltmp
+; CHECK: .short 1 # Loc expr size
 ; CHECK-NEXT: DW_OP_reg
 
 %0 = type { double }
 
 define hidden %0 @__divsc3(float %a, float %b, float %c, float %d) nounwind readnone {
 entry:
-  tail call void @llvm.dbg.value(metadata float %a, i64 0, metadata !0, metadata !{!"0x102"})
-  tail call void @llvm.dbg.value(metadata float %b, i64 0, metadata !11, metadata !{!"0x102"})
-  tail call void @llvm.dbg.value(metadata float %c, i64 0, metadata !12, metadata !{!"0x102"})
-  tail call void @llvm.dbg.value(metadata float %d, i64 0, metadata !13, metadata !{!"0x102"})
+  tail call void @llvm.dbg.value(metadata float %a, i64 0, metadata !0, metadata !DIExpression()), !dbg !DILocation(scope: !1)
+  tail call void @llvm.dbg.value(metadata float %b, i64 0, metadata !11, metadata !DIExpression()), !dbg !DILocation(scope: !1)
+  tail call void @llvm.dbg.value(metadata float %c, i64 0, metadata !12, metadata !DIExpression()), !dbg !DILocation(scope: !1)
+  tail call void @llvm.dbg.value(metadata float %d, i64 0, metadata !13, metadata !DIExpression()), !dbg !DILocation(scope: !1)
   %0 = tail call float @fabsf(float %c) nounwind readnone, !dbg !19 ; <float> [#uses=1]
   %1 = tail call float @fabsf(float %d) nounwind readnone, !dbg !19 ; <float> [#uses=1]
   %2 = fcmp olt float %0, %1, !dbg !19            ; <i1> [#uses=1]
@@ -21,34 +20,34 @@ entry:
 
 bb:                                               ; preds = %entry
   %3 = fdiv float %c, %d, !dbg !20                ; <float> [#uses=3]
-  tail call void @llvm.dbg.value(metadata float %3, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !20
+  tail call void @llvm.dbg.value(metadata float %3, i64 0, metadata !16, metadata !DIExpression()), !dbg !20
   %4 = fmul float %3, %c, !dbg !21                ; <float> [#uses=1]
   %5 = fadd float %4, %d, !dbg !21                ; <float> [#uses=2]
-  tail call void @llvm.dbg.value(metadata float %5, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !21
+  tail call void @llvm.dbg.value(metadata float %5, i64 0, metadata !14, metadata !DIExpression()), !dbg !21
   %6 = fmul float %3, %a, !dbg !22                ; <float> [#uses=1]
   %7 = fadd float %6, %b, !dbg !22                ; <float> [#uses=1]
   %8 = fdiv float %7, %5, !dbg !22                ; <float> [#uses=1]
-  tail call void @llvm.dbg.value(metadata float %8, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !22
+  tail call void @llvm.dbg.value(metadata float %8, i64 0, metadata !17, metadata !DIExpression()), !dbg !22
   %9 = fmul float %3, %b, !dbg !23                ; <float> [#uses=1]
   %10 = fsub float %9, %a, !dbg !23               ; <float> [#uses=1]
   %11 = fdiv float %10, %5, !dbg !23              ; <float> [#uses=1]
-  tail call void @llvm.dbg.value(metadata float %11, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !23
+  tail call void @llvm.dbg.value(metadata float %11, i64 0, metadata !18, metadata !DIExpression()), !dbg !23
   br label %bb2, !dbg !23
 
 bb1:                                              ; preds = %entry
   %12 = fdiv float %d, %c, !dbg !24               ; <float> [#uses=3]
-  tail call void @llvm.dbg.value(metadata float %12, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !24
+  tail call void @llvm.dbg.value(metadata float %12, i64 0, metadata !16, metadata !DIExpression()), !dbg !24
   %13 = fmul float %12, %d, !dbg !25              ; <float> [#uses=1]
   %14 = fadd float %13, %c, !dbg !25              ; <float> [#uses=2]
-  tail call void @llvm.dbg.value(metadata float %14, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !25
+  tail call void @llvm.dbg.value(metadata float %14, i64 0, metadata !14, metadata !DIExpression()), !dbg !25
   %15 = fmul float %12, %b, !dbg !26              ; <float> [#uses=1]
   %16 = fadd float %15, %a, !dbg !26              ; <float> [#uses=1]
   %17 = fdiv float %16, %14, !dbg !26             ; <float> [#uses=1]
-  tail call void @llvm.dbg.value(metadata float %17, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !26
+  tail call void @llvm.dbg.value(metadata float %17, i64 0, metadata !17, metadata !DIExpression()), !dbg !26
   %18 = fmul float %12, %a, !dbg !27              ; <float> [#uses=1]
   %19 = fsub float %b, %18, !dbg !27              ; <float> [#uses=1]
   %20 = fdiv float %19, %14, !dbg !27             ; <float> [#uses=1]
-  tail call void @llvm.dbg.value(metadata float %20, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !27
+  tail call void @llvm.dbg.value(metadata float %20, i64 0, metadata !18, metadata !DIExpression()), !dbg !27
   br label %bb2, !dbg !27
 
 bb2:                                              ; preds = %bb1, %bb
@@ -74,9 +73,9 @@ bb6:                                              ; preds = %bb4
 bb8:                                              ; preds = %bb6
   %27 = tail call float @copysignf(float 0x7FF0000000000000, float %c) nounwind readnone, !dbg !30 ; <float> [#uses=2]
   %28 = fmul float %27, %a, !dbg !30              ; <float> [#uses=1]
-  tail call void @llvm.dbg.value(metadata float %28, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !30
+  tail call void @llvm.dbg.value(metadata float %28, i64 0, metadata !17, metadata !DIExpression()), !dbg !30
   %29 = fmul float %27, %b, !dbg !31              ; <float> [#uses=1]
-  tail call void @llvm.dbg.value(metadata float %29, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !31
+  tail call void @llvm.dbg.value(metadata float %29, i64 0, metadata !18, metadata !DIExpression()), !dbg !31
   br label %bb46, !dbg !31
 
 bb9:                                              ; preds = %bb6, %bb4
@@ -106,24 +105,24 @@ bb15:                                             ; preds = %bb14
 bb16:                                             ; preds = %bb15
   %iftmp.0.0 = select i1 %33, float 1.000000e+00, float 0.000000e+00 ; <float> [#uses=1]
   %42 = tail call float @copysignf(float %iftmp.0.0, float %a) nounwind readnone, !dbg !33 ; <float> [#uses=2]
-  tail call void @llvm.dbg.value(metadata float %42, i64 0, metadata !0, metadata !{!"0x102"}), !dbg !33
+  tail call void @llvm.dbg.value(metadata float %42, i64 0, metadata !0, metadata !DIExpression()), !dbg !33
   %43 = fcmp ord float %b, 0.000000e+00           ; <i1> [#uses=1]
   %44 = fsub float %b, %b, !dbg !34               ; <float> [#uses=1]
   %45 = fcmp uno float %44, 0.000000e+00          ; <i1> [#uses=1]
   %46 = and i1 %43, %45, !dbg !34                 ; <i1> [#uses=1]
   %iftmp.1.0 = select i1 %46, float 1.000000e+00, float 0.000000e+00 ; <float> [#uses=1]
   %47 = tail call float @copysignf(float %iftmp.1.0, float %b) nounwind readnone, !dbg !34 ; <float> [#uses=2]
-  tail call void @llvm.dbg.value(metadata float %47, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !34
+  tail call void @llvm.dbg.value(metadata float %47, i64 0, metadata !11, metadata !DIExpression()), !dbg !34
   %48 = fmul float %42, %c, !dbg !35              ; <float> [#uses=1]
   %49 = fmul float %47, %d, !dbg !35              ; <float> [#uses=1]
   %50 = fadd float %48, %49, !dbg !35             ; <float> [#uses=1]
   %51 = fmul float %50, 0x7FF0000000000000, !dbg !35 ; <float> [#uses=1]
-  tail call void @llvm.dbg.value(metadata float %51, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !35
+  tail call void @llvm.dbg.value(metadata float %51, i64 0, metadata !17, metadata !DIExpression()), !dbg !35
   %52 = fmul float %47, %c, !dbg !36              ; <float> [#uses=1]
   %53 = fmul float %42, %d, !dbg !36              ; <float> [#uses=1]
   %54 = fsub float %52, %53, !dbg !36             ; <float> [#uses=1]
   %55 = fmul float %54, 0x7FF0000000000000, !dbg !36 ; <float> [#uses=1]
-  tail call void @llvm.dbg.value(metadata float %55, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !36
+  tail call void @llvm.dbg.value(metadata float %55, i64 0, metadata !18, metadata !DIExpression()), !dbg !36
   br label %bb46, !dbg !36
 
 bb27:                                             ; preds = %bb15, %bb14, %bb11
@@ -154,24 +153,24 @@ bb34:                                             ; preds = %bb33, %bb30
 bb35:                                             ; preds = %bb34
   %iftmp.2.0 = select i1 %59, float 1.000000e+00, float 0.000000e+00 ; <float> [#uses=1]
   %67 = tail call float @copysignf(float %iftmp.2.0, float %c) nounwind readnone, !dbg !38 ; <float> [#uses=2]
-  tail call void @llvm.dbg.value(metadata float %67, i64 0, metadata !12, metadata !{!"0x102"}), !dbg !38
+  tail call void @llvm.dbg.value(metadata float %67, i64 0, metadata !12, metadata !DIExpression()), !dbg !38
   %68 = fcmp ord float %d, 0.000000e+00           ; <i1> [#uses=1]
   %69 = fsub float %d, %d, !dbg !39               ; <float> [#uses=1]
   %70 = fcmp uno float %69, 0.000000e+00          ; <i1> [#uses=1]
   %71 = and i1 %68, %70, !dbg !39                 ; <i1> [#uses=1]
   %iftmp.3.0 = select i1 %71, float 1.000000e+00, float 0.000000e+00 ; <float> [#uses=1]
   %72 = tail call float @copysignf(float %iftmp.3.0, float %d) nounwind readnone, !dbg !39 ; <float> [#uses=2]
-  tail call void @llvm.dbg.value(metadata float %72, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !39
+  tail call void @llvm.dbg.value(metadata float %72, i64 0, metadata !13, metadata !DIExpression()), !dbg !39
   %73 = fmul float %67, %a, !dbg !40              ; <float> [#uses=1]
   %74 = fmul float %72, %b, !dbg !40              ; <float> [#uses=1]
   %75 = fadd float %73, %74, !dbg !40             ; <float> [#uses=1]
   %76 = fmul float %75, 0.000000e+00, !dbg !40    ; <float> [#uses=1]
-  tail call void @llvm.dbg.value(metadata float %76, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !40
+  tail call void @llvm.dbg.value(metadata float %76, i64 0, metadata !17, metadata !DIExpression()), !dbg !40
   %77 = fmul float %67, %b, !dbg !41              ; <float> [#uses=1]
   %78 = fmul float %72, %a, !dbg !41              ; <float> [#uses=1]
   %79 = fsub float %77, %78, !dbg !41             ; <float> [#uses=1]
   %80 = fmul float %79, 0.000000e+00, !dbg !41    ; <float> [#uses=1]
-  tail call void @llvm.dbg.value(metadata float %80, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !41
+  tail call void @llvm.dbg.value(metadata float %80, i64 0, metadata !18, metadata !DIExpression()), !dbg !41
   br label %bb46, !dbg !41
 
 bb46:                                             ; preds = %bb35, %bb34, %bb33, %bb30, %bb16, %bb8, %bb2
@@ -200,52 +199,52 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!3}
 !llvm.module.flags = !{!48}
 
-!0 = !{!"0x101\00a\001921\000", !1, !2, !9} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00__divsc3\00__divsc3\00__divsc3\001922\000\001\000\006\000\001\001922", !45, !2, !4, null, %0 (float, float, float, float)* @__divsc3, null, null, !43} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !45} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\001\00\000\00\001", !45, !47, !47, !44, null,  null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !45, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 1921, arg: 0, scope: !1, file: !2, type: !9)
+!1 = !DISubprogram(name: "__divsc3", linkageName: "__divsc3", line: 1922, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 1922, file: !45, scope: !2, type: !4, function: %0 (float, float, float, float)* @__divsc3, variables: !43)
+!2 = !DIFile(filename: "libgcc2.c", directory: "/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc")
+!3 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 1, file: !45, enums: !47, retainedTypes: !47, subprograms: !44, imports:  null)
+!4 = !DISubroutineType(types: !5)
 !5 = !{!6, !9, !9, !9, !9}
-!6 = !{!"0x16\00SCtype\00170\000\000\000\000", !46, !7, !8} ; [ DW_TAG_typedef ]
-!7 = !{!"0x29", !46} ; [ DW_TAG_file_type ]
-!8 = !{!"0x24\00complex float\000\0064\0032\000\000\003", !45, !2} ; [ DW_TAG_base_type ]
-!9 = !{!"0x16\00SFtype\00167\000\000\000\000", !46, !7, !10} ; [ DW_TAG_typedef ]
-!10 = !{!"0x24\00float\000\0032\0032\000\000\004", !45, !2} ; [ DW_TAG_base_type ]
-!11 = !{!"0x101\00b\001921\000", !1, !2, !9} ; [ DW_TAG_arg_variable ]
-!12 = !{!"0x101\00c\001921\000", !1, !2, !9} ; [ DW_TAG_arg_variable ]
-!13 = !{!"0x101\00d\001921\000", !1, !2, !9} ; [ DW_TAG_arg_variable ]
-!14 = !{!"0x100\00denom\001923\000", !15, !2, !9} ; [ DW_TAG_auto_variable ]
-!15 = !{!"0xb\001922\000\000", !45, !1} ; [ DW_TAG_lexical_block ]
-!16 = !{!"0x100\00ratio\001923\000", !15, !2, !9} ; [ DW_TAG_auto_variable ]
-!17 = !{!"0x100\00x\001923\000", !15, !2, !9} ; [ DW_TAG_auto_variable ]
-!18 = !{!"0x100\00y\001923\000", !15, !2, !9} ; [ DW_TAG_auto_variable ]
-!19 = !MDLocation(line: 1929, scope: !15)
-!20 = !MDLocation(line: 1931, scope: !15)
-!21 = !MDLocation(line: 1932, scope: !15)
-!22 = !MDLocation(line: 1933, scope: !15)
-!23 = !MDLocation(line: 1934, scope: !15)
-!24 = !MDLocation(line: 1938, scope: !15)
-!25 = !MDLocation(line: 1939, scope: !15)
-!26 = !MDLocation(line: 1940, scope: !15)
-!27 = !MDLocation(line: 1941, scope: !15)
-!28 = !MDLocation(line: 1946, scope: !15)
-!29 = !MDLocation(line: 1948, scope: !15)
-!30 = !MDLocation(line: 1950, scope: !15)
-!31 = !MDLocation(line: 1951, scope: !15)
-!32 = !MDLocation(line: 1953, scope: !15)
-!33 = !MDLocation(line: 1955, scope: !15)
-!34 = !MDLocation(line: 1956, scope: !15)
-!35 = !MDLocation(line: 1957, scope: !15)
-!36 = !MDLocation(line: 1958, scope: !15)
-!37 = !MDLocation(line: 1960, scope: !15)
-!38 = !MDLocation(line: 1962, scope: !15)
-!39 = !MDLocation(line: 1963, scope: !15)
-!40 = !MDLocation(line: 1964, scope: !15)
-!41 = !MDLocation(line: 1965, scope: !15)
-!42 = !MDLocation(line: 1969, scope: !15)
+!6 = !DIDerivedType(tag: DW_TAG_typedef, name: "SCtype", line: 170, file: !46, scope: !7, baseType: !8)
+!7 = !DIFile(filename: "libgcc2.h", directory: "/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc")
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "complex float", size: 64, align: 32, encoding: DW_ATE_complex_float)
+!9 = !DIDerivedType(tag: DW_TAG_typedef, name: "SFtype", line: 167, file: !46, scope: !7, baseType: !10)
+!10 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float)
+!11 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 1921, arg: 0, scope: !1, file: !2, type: !9)
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 1921, arg: 0, scope: !1, file: !2, type: !9)
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "d", line: 1921, arg: 0, scope: !1, file: !2, type: !9)
+!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "denom", line: 1923, scope: !15, file: !2, type: !9)
+!15 = distinct !DILexicalBlock(line: 1922, column: 0, file: !45, scope: !1)
+!16 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "ratio", line: 1923, scope: !15, file: !2, type: !9)
+!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 1923, scope: !15, file: !2, type: !9)
+!18 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y", line: 1923, scope: !15, file: !2, type: !9)
+!19 = !DILocation(line: 1929, scope: !15)
+!20 = !DILocation(line: 1931, scope: !15)
+!21 = !DILocation(line: 1932, scope: !15)
+!22 = !DILocation(line: 1933, scope: !15)
+!23 = !DILocation(line: 1934, scope: !15)
+!24 = !DILocation(line: 1938, scope: !15)
+!25 = !DILocation(line: 1939, scope: !15)
+!26 = !DILocation(line: 1940, scope: !15)
+!27 = !DILocation(line: 1941, scope: !15)
+!28 = !DILocation(line: 1946, scope: !15)
+!29 = !DILocation(line: 1948, scope: !15)
+!30 = !DILocation(line: 1950, scope: !15)
+!31 = !DILocation(line: 1951, scope: !15)
+!32 = !DILocation(line: 1953, scope: !15)
+!33 = !DILocation(line: 1955, scope: !15)
+!34 = !DILocation(line: 1956, scope: !15)
+!35 = !DILocation(line: 1957, scope: !15)
+!36 = !DILocation(line: 1958, scope: !15)
+!37 = !DILocation(line: 1960, scope: !15)
+!38 = !DILocation(line: 1962, scope: !15)
+!39 = !DILocation(line: 1963, scope: !15)
+!40 = !DILocation(line: 1964, scope: !15)
+!41 = !DILocation(line: 1965, scope: !15)
+!42 = !DILocation(line: 1969, scope: !15)
 !43 = !{!0, !11, !12, !13, !14, !16, !17, !18}
 !44 = !{!1}
-!45 = !{!"libgcc2.c", !"/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc"}
-!46 = !{!"libgcc2.h", !"/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc"}
-!47 = !{i32 0}
-!48 = !{i32 1, !"Debug Info Version", i32 2}
+!45 = !DIFile(filename: "libgcc2.c", directory: "/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc")
+!46 = !DIFile(filename: "libgcc2.h", directory: "/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc")
+!47 = !{}
+!48 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll
index 9915a706e5ee..3670c556aa79 100644
--- a/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll
+++ b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll
@@ -9,9 +9,9 @@ target triple = "x86_64-apple-darwin10"
 
 define i8* @bar(%struct.a* %myvar) nounwind optsize noinline ssp {
 entry:
-  tail call void @llvm.dbg.value(metadata %struct.a* %myvar, i64 0, metadata !8, metadata !{!"0x102"})
-  %0 = getelementptr inbounds %struct.a* %myvar, i64 0, i32 0, !dbg !28 ; <i32*> [#uses=1]
-  %1 = load i32* %0, align 8, !dbg !28            ; <i32> [#uses=1]
+  tail call void @llvm.dbg.value(metadata %struct.a* %myvar, i64 0, metadata !8, metadata !DIExpression()), !dbg !DILocation(scope: !9)
+  %0 = getelementptr inbounds %struct.a, %struct.a* %myvar, i64 0, i32 0, !dbg !28 ; <i32*> [#uses=1]
+  %1 = load i32, i32* %0, align 8, !dbg !28            ; <i32> [#uses=1]
   tail call void @foo(i32 %1) nounwind optsize noinline ssp, !dbg !28
   %2 = bitcast %struct.a* %myvar to i8*, !dbg !30 ; <i8*> [#uses=1]
   ret i8* %2, !dbg !30
@@ -24,43 +24,43 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!38}
 
-!0 = !{!"0x34\00ret\00ret\00\007\000\001", !1, !1, !3, null, null} ; [ DW_TAG_variable ]
-!1 = !{!"0x29", !36} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\001\00\000\00\001", !36, !37, !37, !32, !31,  !37} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x24\00int\000\0032\0032\000\000\005", !36, !1} ; [ DW_TAG_base_type ]
-!4 = !{!"0x101\00x\0012\000", !5, !1, !3} ; [ DW_TAG_arg_variable ]
-!5 = !{!"0x2e\00foo\00foo\00foo\0013\000\001\000\006\000\001\0013", !36, !1, !6, null, void (i32)* @foo, null, null, !33} ; [ DW_TAG_subprogram ]
-!6 = !{!"0x15\00\000\000\000\000\000\000", !36, !1, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DIGlobalVariable(name: "ret", line: 7, isLocal: false, isDefinition: true, scope: !1, file: !1, type: !3)
+!1 = !DIFile(filename: "foo.c", directory: "/tmp/")
+!2 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 1, file: !36, enums: !37, retainedTypes: !37, subprograms: !32, globals: !31, imports:  !37)
+!3 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!4 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 12, arg: 0, scope: !5, file: !1, type: !3)
+!5 = !DISubprogram(name: "foo", linkageName: "foo", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 13, file: !36, scope: !1, type: !6, function: void (i32)* @foo, variables: !33)
+!6 = !DISubroutineType(types: !7)
 !7 = !{null, !3}
-!8 = !{!"0x101\00myvar\0017\000", !9, !1, !13} ; [ DW_TAG_arg_variable ]
-!9 = !{!"0x2e\00bar\00bar\00bar\0017\000\001\000\006\000\001\0017", !36, !1, !10, null, i8* (%struct.a*)* @bar, null, null, !34} ; [ DW_TAG_subprogram ]
-!10 = !{!"0x15\00\000\000\000\000\000\000", !36, !1, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "myvar", line: 17, arg: 0, scope: !9, file: !1, type: !13)
+!9 = !DISubprogram(name: "bar", linkageName: "bar", line: 17, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 17, file: !36, scope: !1, type: !10, function: i8* (%struct.a*)* @bar, variables: !34)
+!10 = !DISubroutineType(types: !11)
 !11 = !{!12, !13}
-!12 = !{!"0xf\00\000\0064\0064\000\000", !36, !1, null} ; [ DW_TAG_pointer_type ]
-!13 = !{!"0xf\00\000\0064\0064\000\000", !36, !1, !14} ; [ DW_TAG_pointer_type ]
-!14 = !{!"0x13\00a\002\00128\0064\000\000\000", !36, !1, null, !15, null, null, null} ; [ DW_TAG_structure_type ] [a] [line 2, size 128, align 64, offset 0] [def] [from ]
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !36, scope: !1, baseType: null)
+!13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !36, scope: !1, baseType: !14)
+!14 = !DICompositeType(tag: DW_TAG_structure_type, name: "a", line: 2, size: 128, align: 64, file: !36, scope: !1, elements: !15)
 !15 = !{!16, !17}
-!16 = !{!"0xd\00c\003\0032\0032\000\000", !36, !14, !3} ; [ DW_TAG_member ]
-!17 = !{!"0xd\00d\004\0064\0064\0064\000", !36, !14, !13} ; [ DW_TAG_member ]
-!18 = !{!"0x101\00argc\0022\000", !19, !1, !3} ; [ DW_TAG_arg_variable ]
-!19 = !{!"0x2e\00main\00main\00main\0022\000\001\000\006\000\001\0022", !36, !1, !20, null, null, null, null, !35} ; [ DW_TAG_subprogram ]
-!20 = !{!"0x15\00\000\000\000\000\000\000", !36, !1, null, !21, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!16 = !DIDerivedType(tag: DW_TAG_member, name: "c", line: 3, size: 32, align: 32, file: !36, scope: !14, baseType: !3)
+!17 = !DIDerivedType(tag: DW_TAG_member, name: "d", line: 4, size: 64, align: 64, offset: 64, file: !36, scope: !14, baseType: !13)
+!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 22, arg: 0, scope: !19, file: !1, type: !3)
+!19 = !DISubprogram(name: "main", linkageName: "main", line: 22, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 22, file: !36, scope: !1, type: !20, variables: !35)
+!20 = !DISubroutineType(types: !21)
 !21 = !{!3, !3, !22}
-!22 = !{!"0xf\00\000\0064\0064\000\000", !36, !1, !23} ; [ DW_TAG_pointer_type ]
-!23 = !{!"0xf\00\000\0064\0064\000\000", !36, !1, !24} ; [ DW_TAG_pointer_type ]
-!24 = !{!"0x24\00char\000\008\008\000\000\006", !36, !1} ; [ DW_TAG_base_type ]
-!25 = !{!"0x101\00argv\0022\000", !19, !1, !22} ; [ DW_TAG_arg_variable ]
-!26 = !{!"0x100\00e\0023\000", !27, !1, !14} ; [ DW_TAG_auto_variable ]
-!27 = !{!"0xb\0022\000\000", !36, !19} ; [ DW_TAG_lexical_block ]
-!28 = !MDLocation(line: 18, scope: !29)
-!29 = !{!"0xb\0017\000\001", !36, !9} ; [ DW_TAG_lexical_block ]
-!30 = !MDLocation(line: 19, scope: !29)
+!22 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !36, scope: !1, baseType: !23)
+!23 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !36, scope: !1, baseType: !24)
+!24 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!25 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 22, arg: 0, scope: !19, file: !1, type: !22)
+!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "e", line: 23, scope: !27, file: !1, type: !14)
+!27 = distinct !DILexicalBlock(line: 22, column: 0, file: !36, scope: !19)
+!28 = !DILocation(line: 18, scope: !29)
+!29 = distinct !DILexicalBlock(line: 17, column: 0, file: !36, scope: !9)
+!30 = !DILocation(line: 19, scope: !29)
 !31 = !{!0}
 !32 = !{!5, !9, !19}
 !33 = !{!4}
 !34 = !{!8}
 !35 = !{!18, !25, !26}
-!36 = !{!"foo.c", !"/tmp/"}
+!36 = !DIFile(filename: "foo.c", directory: "/tmp/")
 !37 = !{}
 
 ; The variable bar:myvar changes registers after the first movq.
@@ -77,18 +77,12 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 ; CHECK-NEXT: .quad   [[SET1]]
 ; CHECK-NEXT: [[SET2:.*]] = [[LABEL]]-Lfunc_begin0
 ; CHECK-NEXT: .quad   [[SET2]]
-; CHECK-NEXT: Lset{{.*}} = Ltmp{{.*}}-Ltmp{{.*}}               ## Loc expr size
-; CHECK-NEXT: .short  Lset{{.*}}
-; CHECK-NEXT: Ltmp{{.*}}:
+; CHECK-NEXT: .short  1     ## Loc expr size
 ; CHECK-NEXT: .byte   85
-; CHECK-NEXT: Ltmp{{.*}}:
 ; CHECK-NEXT: [[SET3:.*]] = [[LABEL]]-Lfunc_begin0
 ; CHECK-NEXT: .quad   [[SET3]]
 ; CHECK-NEXT: [[SET4:.*]] = [[CLOBBER]]-Lfunc_begin0
 ; CHECK-NEXT: .quad   [[SET4]]
-; CHECK-NEXT: Lset{{.*}} = Ltmp{{.*}}-Ltmp{{.*}}               ## Loc expr size
-; CHECK-NEXT: .short  Lset{{.*}}
-; CHECK-NEXT: Ltmp{{.*}}:
+; CHECK-NEXT: .short  1     ## Loc expr size
 ; CHECK-NEXT: .byte   83
-; CHECK-NEXT: Ltmp{{.*}}:
-!38 = !{i32 1, !"Debug Info Version", i32 2}
+!38 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/2010-05-26-FP_TO_INT-crash.ll b/test/CodeGen/X86/2010-05-26-FP_TO_INT-crash.ll
index 38dcb806cc9d..ac18195dc5a3 100644
--- a/test/CodeGen/X86/2010-05-26-FP_TO_INT-crash.ll
+++ b/test/CodeGen/X86/2010-05-26-FP_TO_INT-crash.ll
@@ -7,7 +7,7 @@ module asm "\09.ident\09\22GCC: (GNU) 4.5.1 20100510 (prerelease) LLVM: 104604:1
 
 define i32 @f2(double %x) nounwind {
 entry:
-  %0 = load double* undef, align 64               ; <double> [#uses=1]
+  %0 = load double, double* undef, align 64               ; <double> [#uses=1]
   %1 = fptoui double %0 to i16                    ; <i16> [#uses=1]
   %2 = zext i16 %1 to i32                         ; <i32> [#uses=1]
   %3 = add nsw i32 0, %2                          ; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2010-05-28-Crash.ll b/test/CodeGen/X86/2010-05-28-Crash.ll
index 7adacf5e0176..c5201614fdd1 100644
--- a/test/CodeGen/X86/2010-05-28-Crash.ll
+++ b/test/CodeGen/X86/2010-05-28-Crash.ll
@@ -4,8 +4,8 @@
 
 define i32 @foo(i32 %y) nounwind optsize ssp {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 %y, i64 0, metadata !0, metadata !{!"0x102"})
-  %0 = tail call i32 (...)* @zoo(i32 %y) nounwind, !dbg !9 ; <i32> [#uses=1]
+  tail call void @llvm.dbg.value(metadata i32 %y, i64 0, metadata !0, metadata !DIExpression()), !dbg !DILocation(scope: !1)
+  %0 = tail call i32 (...) @zoo(i32 %y) nounwind, !dbg !9 ; <i32> [#uses=1]
   ret i32 %0, !dbg !9
 }
 
@@ -15,9 +15,9 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 
 define i32 @bar(i32 %x) nounwind optsize ssp {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !7, metadata !{!"0x102"})
-  tail call void @llvm.dbg.value(metadata i32 1, i64 0, metadata !0, metadata !{!"0x102"}) nounwind
-  %0 = tail call i32 (...)* @zoo(i32 1) nounwind, !dbg !12 ; <i32> [#uses=1]
+  tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !7, metadata !DIExpression()), !dbg !DILocation(scope: !8)
+  tail call void @llvm.dbg.value(metadata i32 1, i64 0, metadata !0, metadata !DIExpression()) nounwind, !dbg !DILocation(scope: !1)
+  %0 = tail call i32 (...) @zoo(i32 1) nounwind, !dbg !12 ; <i32> [#uses=1]
   %1 = add nsw i32 %0, %x, !dbg !13               ; <i32> [#uses=1]
   ret i32 %1, !dbg !13
 }
@@ -25,28 +25,28 @@ entry:
 !llvm.dbg.cu = !{!3}
 !llvm.module.flags = !{!20}
 
-!0 = !{!"0x101\00y\002\000", !1, !2, !6} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00foo\00foo\00foo\002\000\001\000\006\000\001\002", !18, !2, !4, null, i32 (i32)* @foo, null, null, !15} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !18} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\001\00\000\00\001", !18, !19, !19, !17, null,  null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !18, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "y", line: 2, arg: 0, scope: !1, file: !2, type: !6)
+!1 = !DISubprogram(name: "foo", linkageName: "foo", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 2, file: !18, scope: !2, type: !4, function: i32 (i32)* @foo, variables: !15)
+!2 = !DIFile(filename: "f.c", directory: "/tmp")
+!3 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 1, file: !18, enums: !19, retainedTypes: !19, subprograms: !17, imports:  null)
+!4 = !DISubroutineType(types: !5)
 !5 = !{!6, !6}
-!6 = !{!"0x24\00int\000\0032\0032\000\000\005", !18, !2} ; [ DW_TAG_base_type ]
-!7 = !{!"0x101\00x\006\000", !8, !2, !6} ; [ DW_TAG_arg_variable ]
-!8 = !{!"0x2e\00bar\00bar\00bar\006\000\001\000\006\000\001\006", !18, !2, !4, null, i32 (i32)* @bar, null, null, !16} ; [ DW_TAG_subprogram ]
-!9 = !MDLocation(line: 3, scope: !10)
-!10 = !{!"0xb\002\000\000", !18, !1} ; [ DW_TAG_lexical_block ]
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!7 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 6, arg: 0, scope: !8, file: !2, type: !6)
+!8 = !DISubprogram(name: "bar", linkageName: "bar", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 6, file: !18, scope: !2, type: !4, function: i32 (i32)* @bar, variables: !16)
+!9 = !DILocation(line: 3, scope: !10)
+!10 = distinct !DILexicalBlock(line: 2, column: 0, file: !18, scope: !1)
 !11 = !{i32 1}
-!12 = !MDLocation(line: 3, scope: !10, inlinedAt: !13)
-!13 = !MDLocation(line: 7, scope: !14)
-!14 = !{!"0xb\006\000\000", !18, !8} ; [ DW_TAG_lexical_block ]
+!12 = !DILocation(line: 3, scope: !10, inlinedAt: !13)
+!13 = !DILocation(line: 7, scope: !14)
+!14 = distinct !DILexicalBlock(line: 6, column: 0, file: !18, scope: !8)
 !15 = !{!0}
 !16 = !{!7}
 !17 = !{!1, !8}
-!18 = !{!"f.c", !"/tmp"}
-!19 = !{i32 0}
+!18 = !DIFile(filename: "f.c", directory: "/tmp")
+!19 = !{}
 
 ;CHECK: DEBUG_VALUE: bar:x <- E
 ;CHECK: Ltmp
 ;CHECK:	DEBUG_VALUE: foo:y <- 1{{$}}
-!20 = !{i32 1, !"Debug Info Version", i32 2}
+!20 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll b/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll
index 3687b828c4a4..757c92808e11 100644
--- a/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll
+++ b/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll
@@ -10,8 +10,8 @@ target triple = "x86_64-apple-darwin10.2"
 define i32 @_ZN3foo3bazEi(%struct.foo* nocapture %this, i32 %x) nounwind readnone optsize noinline ssp align 2 {
 ;CHECK: DEBUG_VALUE: baz:this <- RDI{{$}}
 entry:
-  tail call void @llvm.dbg.value(metadata %struct.foo* %this, i64 0, metadata !15, metadata !{!"0x102"})
-  tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !16, metadata !{!"0x102"})
+  tail call void @llvm.dbg.value(metadata %struct.foo* %this, i64 0, metadata !15, metadata !DIExpression()), !dbg !DILocation(scope: !8)
+  tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !16, metadata !DIExpression()), !dbg !DILocation(scope: !8)
   %0 = mul nsw i32 %x, 7, !dbg !29                ; <i32> [#uses=1]
   %1 = add nsw i32 %0, 1, !dbg !29                ; <i32> [#uses=1]
   ret i32 %1, !dbg !29
@@ -23,38 +23,38 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.module.flags = !{!34}
 !llvm.dbg.lv = !{!0, !14, !15, !16, !17, !24, !25, !28}
 
-!0 = !{!"0x101\00this\0011\000", !1, !3, !12} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00bar\00bar\00_ZN3foo3barEi\0011\000\001\000\006\000\001\0011", !31, !2, !9, null, i32 (%struct.foo*, i32)* null, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x13\00foo\003\0032\0032\000\000\000", !31, !3, null, !5, null, null, null} ; [ DW_TAG_structure_type ] [foo] [line 3, size 32, align 32, offset 0] [def] [from ]
-!3 = !{!"0x29", !31} ; [ DW_TAG_file_type ]
-!4 = !{!"0x11\004\004.2.1 LLVM build\001\00\000\00\000", !31, !32, !32, !33, null, null} ; [ DW_TAG_compile_unit ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 11, arg: 0, scope: !1, file: !3, type: !12)
+!1 = !DISubprogram(name: "bar", linkageName: "_ZN3foo3barEi", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 11, file: !31, scope: !2, type: !9, function: i32 (%struct.foo*, i32)* null)
+!2 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo", line: 3, size: 32, align: 32, file: !31, scope: !3, elements: !5)
+!3 = !DIFile(filename: "foo.cp", directory: "/tmp/")
+!4 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "4.2.1 LLVM build", isOptimized: true, emissionKind: 0, file: !31, enums: !32, retainedTypes: !32, subprograms: !33)
 !5 = !{!6, !1, !8}
-!6 = !{!"0xd\00y\008\0032\0032\000\000", !31, !2, !7} ; [ DW_TAG_member ]
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", !31, !3} ; [ DW_TAG_base_type ]
-!8 = !{!"0x2e\00baz\00baz\00_ZN3foo3bazEi\0015\000\001\000\006\000\001\0015", !31, !2, !9, null, i32 (%struct.foo*, i32)* @_ZN3foo3bazEi, null, null, null} ; [ DW_TAG_subprogram ]
-!9 = !{!"0x15\00\000\000\000\000\000\000", !31, !3, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DIDerivedType(tag: DW_TAG_member, name: "y", line: 8, size: 32, align: 32, file: !31, scope: !2, baseType: !7)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DISubprogram(name: "baz", linkageName: "_ZN3foo3bazEi", line: 15, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 15, file: !31, scope: !2, type: !9, function: i32 (%struct.foo*, i32)* @_ZN3foo3bazEi)
+!9 = !DISubroutineType(types: !10)
 !10 = !{!7, !11, !7}
-!11 = !{!"0xf\00\000\0064\0064\000\0064", !31, !3, !2} ; [ DW_TAG_pointer_type ]
-!12 = !{!"0x26\00\000\0064\0064\000\0064", !31, !3, !13} ; [ DW_TAG_const_type ]
-!13 = !{!"0xf\00\000\0064\0064\000\000", !31, !3, !2} ; [ DW_TAG_pointer_type ]
-!14 = !{!"0x101\00x\0011\000", !1, !3, !7} ; [ DW_TAG_arg_variable ]
-!15 = !{!"0x101\00this\0015\000", !8, !3, !12} ; [ DW_TAG_arg_variable ]
-!16 = !{!"0x101\00x\0015\000", !8, !3, !7} ; [ DW_TAG_arg_variable ]
-!17 = !{!"0x101\00argc\0019\000", !18, !3, !7} ; [ DW_TAG_arg_variable ]
-!18 = !{!"0x2e\00main\00main\00main\0019\000\001\000\006\000\001\0019", !31, !3, !19, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!19 = !{!"0x15\00\000\000\000\000\000\000", !31, !3, null, !20, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, file: !31, scope: !3, baseType: !2)
+!12 = !DIDerivedType(tag: DW_TAG_const_type, size: 64, align: 64, flags: DIFlagArtificial, file: !31, scope: !3, baseType: !13)
+!13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !31, scope: !3, baseType: !2)
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 11, arg: 0, scope: !1, file: !3, type: !7)
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 15, arg: 0, scope: !8, file: !3, type: !12)
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 15, arg: 0, scope: !8, file: !3, type: !7)
+!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 19, arg: 0, scope: !18, file: !3, type: !7)
+!18 = !DISubprogram(name: "main", linkageName: "main", line: 19, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 19, file: !31, scope: !3, type: !19)
+!19 = !DISubroutineType(types: !20)
 !20 = !{!7, !7, !21}
-!21 = !{!"0xf\00\000\0064\0064\000\000", !31, !3, !22} ; [ DW_TAG_pointer_type ]
-!22 = !{!"0xf\00\000\0064\0064\000\000", !31, !3, !23} ; [ DW_TAG_pointer_type ]
-!23 = !{!"0x24\00char\000\008\008\000\000\006", !31, !3} ; [ DW_TAG_base_type ]
-!24 = !{!"0x101\00argv\0019\000", !18, !3, !21} ; [ DW_TAG_arg_variable ]
-!25 = !{!"0x100\00a\0020\000", !26, !3, !2} ; [ DW_TAG_auto_variable ]
-!26 = !{!"0xb\0019\000\000", !31, !27} ; [ DW_TAG_lexical_block ]
-!27 = !{!"0xb\0019\000\000", !31, !18} ; [ DW_TAG_lexical_block ]
-!28 = !{!"0x100\00b\0021\000", !26, !3, !7} ; [ DW_TAG_auto_variable ]
-!29 = !MDLocation(line: 16, scope: !30)
-!30 = !{!"0xb\0015\000\000", !31, !8} ; [ DW_TAG_lexical_block ]
-!31 = !{!"foo.cp", !"/tmp/"}
-!32 = !{i32 0}
+!21 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !31, scope: !3, baseType: !22)
+!22 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !31, scope: !3, baseType: !23)
+!23 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 19, arg: 0, scope: !18, file: !3, type: !21)
+!25 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 20, scope: !26, file: !3, type: !2)
+!26 = distinct !DILexicalBlock(line: 19, column: 0, file: !31, scope: !27)
+!27 = distinct !DILexicalBlock(line: 19, column: 0, file: !31, scope: !18)
+!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 21, scope: !26, file: !3, type: !7)
+!29 = !DILocation(line: 16, scope: !30)
+!30 = distinct !DILexicalBlock(line: 15, column: 0, file: !31, scope: !8)
+!31 = !DIFile(filename: "foo.cp", directory: "/tmp/")
+!32 = !{}
 !33 = !{!1, !8, !18}
-!34 = !{i32 1, !"Debug Info Version", i32 2}
+!34 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll b/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll
index b5679e665696..5a4b389acb3d 100644
--- a/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll
+++ b/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll
@@ -2,6 +2,6 @@
 ; CHECK: %fs:
 
 define i32 @test1(i32 addrspace(257)* %arg) nounwind {
-       %tmp = load i32 addrspace(257)* %arg
+       %tmp = load i32, i32 addrspace(257)* %arg
        ret i32 %tmp
 }
diff --git a/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll b/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll
index 74a7610e6597..0b1c36f735a4 100644
--- a/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll
+++ b/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll
@@ -10,17 +10,17 @@ entry:
   %retval = alloca i32, align 4                   ; <i32*> [#uses=3]
   %v = alloca i32, align 4                        ; <i32*> [#uses=3]
   store i32 0, i32* %retval
-  %zero = load i32* %retval
+  %zero = load i32, i32* %retval
 ; The earlyclobber register EC0 should not be spilled before the inline asm.
 ; Yes, check-not can refer to FileCheck variables defined in the future.
 ; CHECK-NOT: [[EC0]]{{.*}}(%rsp)
 ; CHECK: bsr {{[^,]*}}, [[EC0:%...]]
   %0 = call i32 asm "bsr   $1, $0\0A\09cmovz $2, $0", "=&r,ro,r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %zero, i32 -1) nounwind, !srcloc !0 ; <i32> [#uses=1]
   store i32 %0, i32* %v
-  %tmp = load i32* %v                             ; <i32> [#uses=1]
-  %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([23 x i8]* @.str, i32 0, i32 0), i32 %tmp) ; <i32> [#uses=0]
+  %tmp = load i32, i32* %v                             ; <i32> [#uses=1]
+  %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([23 x i8], [23 x i8]* @.str, i32 0, i32 0), i32 %tmp) ; <i32> [#uses=0]
   store i32 0, i32* %retval
-  %1 = load i32* %retval                          ; <i32> [#uses=1]
+  %1 = load i32, i32* %retval                          ; <i32> [#uses=1]
   ret i32 %0
 }
 
diff --git a/test/CodeGen/X86/2010-06-24-g-constraint-crash.ll b/test/CodeGen/X86/2010-06-24-g-constraint-crash.ll
index 2a938d941e2d..905b34ff6f5c 100644
--- a/test/CodeGen/X86/2010-06-24-g-constraint-crash.ll
+++ b/test/CodeGen/X86/2010-06-24-g-constraint-crash.ll
@@ -10,6 +10,6 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 define void @bar() nounwind ssp {
 entry:
   %asmtmp.i.i = tail call %0 asm sideeffect "push %rbp; syscall; pop %rbp\0A", "={ax},={di},={si},={dx},={bx},{ax},{di},{si},{dx},{bx},~{dirflag},~{fpsr},~{flags},~{memory},~{r15},~{r14},~{r13},~{r12},~{r11},~{r10},~{r9},~{r8},~{rcx}"(i32 7, i64 -1, i64 0, i64 -1, i64 -1) nounwind ; <%0> [#uses=0]
-  %asmtmp.i1.i = tail call %0 asm sideeffect "mov $10, %r8;\0Amov $11, %r9;\0Amov $12, %r10;\0Apush %rbp; syscall; pop %rbp\0A", "={ax},={di},={si},={dx},={bx},{ax},{di},{si},{dx},{bx},imr,imr,imr,~{dirflag},~{fpsr},~{flags},~{memory},~{r15},~{r14},~{r13},~{r12},~{r11},~{r10},~{r9},~{r8},~{rcx}"(i32 8, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 0, i8* bitcast (i64* getelementptr inbounds ([3 x i64]* @utcbs.1559, i64 0, i64 2) to i8*)) nounwind ; <%0> [#uses=0]
+  %asmtmp.i1.i = tail call %0 asm sideeffect "mov $10, %r8;\0Amov $11, %r9;\0Amov $12, %r10;\0Apush %rbp; syscall; pop %rbp\0A", "={ax},={di},={si},={dx},={bx},{ax},{di},{si},{dx},{bx},imr,imr,imr,~{dirflag},~{fpsr},~{flags},~{memory},~{r15},~{r14},~{r13},~{r12},~{r11},~{r10},~{r9},~{r8},~{rcx}"(i32 8, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 0, i8* bitcast (i64* getelementptr inbounds ([3 x i64], [3 x i64]* @utcbs.1559, i64 0, i64 2) to i8*)) nounwind ; <%0> [#uses=0]
   ret void
 }
diff --git a/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll b/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll
index 05f581a08834..ffb51572a30c 100644
--- a/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll
+++ b/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll
@@ -6,10 +6,10 @@
 
 define i32 @func(%struct.type* %s) nounwind optsize ssp {
 entry:
-  %tmp1 = getelementptr inbounds %struct.type* %s, i32 0, i32 1
-  %tmp2 = load i32* %tmp1, align 8
+  %tmp1 = getelementptr inbounds %struct.type, %struct.type* %s, i32 0, i32 1
+  %tmp2 = load i32, i32* %tmp1, align 8
   %tmp3 = icmp eq i32 %tmp2, 10
-  %tmp4 = getelementptr inbounds %struct.type* %s, i32 0, i32 40
+  %tmp4 = getelementptr inbounds %struct.type, %struct.type* %s, i32 0, i32 40
   br i1 %tmp3, label %bb, label %entry.bb1_crit_edge
 
 entry.bb1_crit_edge:
@@ -27,7 +27,7 @@ bb:
 
   %tmp5 = bitcast i32* %tmp4 to i8*
   call void @llvm.memset.p0i8.i64(i8* %tmp5, i8 0, i64 84, i32 4, i1 false)
-  %tmp6 = getelementptr inbounds %struct.type* %s, i32 0, i32 62
+  %tmp6 = getelementptr inbounds %struct.type, %struct.type* %s, i32 0, i32 62
   store i32* null, i32** %tmp6, align 8
   br label %bb1
 
diff --git a/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll b/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll
index 3470a06a543b..8f5f083209b4 100644
--- a/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll
+++ b/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll
@@ -6,10 +6,10 @@ define void @_SEH2FrameHandler() nounwind {
 entry:
   %target.addr.i = alloca i8*, align 4            ; <i8**> [#uses=2]
   %frame = alloca %struct.__SEH2Frame*, align 4   ; <%struct.__SEH2Frame**> [#uses=1]
-  %tmp = load %struct.__SEH2Frame** %frame        ; <%struct.__SEH2Frame*> [#uses=1]
+  %tmp = load %struct.__SEH2Frame*, %struct.__SEH2Frame** %frame        ; <%struct.__SEH2Frame*> [#uses=1]
   %conv = bitcast %struct.__SEH2Frame* %tmp to i8* ; <i8*> [#uses=1]
   store i8* %conv, i8** %target.addr.i
-  %tmp.i = load i8** %target.addr.i               ; <i8*> [#uses=1]
+  %tmp.i = load i8*, i8** %target.addr.i               ; <i8*> [#uses=1]
   call void asm sideeffect "push %ebp\0Apush $$0\0Apush $$0\0Apush $$Return${:uid}\0Apush $0\0Acall ${1:c}\0AReturn${:uid}: pop %ebp\0A", "imr,imr,~{ax},~{bx},~{cx},~{dx},~{si},~{di},~{flags},~{memory},~{dirflag},~{fpsr},~{flags}"(i8* %tmp.i, void (...)* @RtlUnwind) nounwind, !srcloc !0
   ret void
 }
diff --git a/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll b/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll
index a0798ae10d7c..023c77aedd4a 100644
--- a/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll
+++ b/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll
@@ -6,6 +6,6 @@ entry:
 ; CHECK: GCROOT %eax
   %_r = alloca i32, align 4                       ; <i32*> [#uses=2]
   call void asm "/* GCROOT $0 */", "=*imr,0,~{dirflag},~{fpsr},~{flags}"(i32* %_r, i32 4) nounwind
-  %0 = load i32* %_r, align 4                     ; <i32> [#uses=1]
+  %0 = load i32, i32* %_r, align 4                     ; <i32> [#uses=1]
   ret i32 %0
 }
diff --git a/test/CodeGen/X86/2010-07-02-UnfoldBug.ll b/test/CodeGen/X86/2010-07-02-UnfoldBug.ll
index 79219dcfe60a..954f25f6e167 100644
--- a/test/CodeGen/X86/2010-07-02-UnfoldBug.ll
+++ b/test/CodeGen/X86/2010-07-02-UnfoldBug.ll
@@ -61,7 +61,7 @@ bb22:                                             ; preds = %bb24.preheader
   br i1 undef, label %bb2.i.i, label %bb.i.i49
 
 bb.i.i49:                                         ; preds = %bb22
-  %0 = load float* undef, align 4                 ; <float> [#uses=1]
+  %0 = load float, float* undef, align 4                 ; <float> [#uses=1]
   %1 = insertelement <4 x float> undef, float %0, i32 0 ; <<4 x float>> [#uses=1]
   %2 = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> <float 1.000000e+00, float undef, float undef, float undef>, <4 x float> %1) nounwind readnone ; <<4 x float>> [#uses=1]
   %3 = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %2, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>) nounwind readnone ; <<4 x float>> [#uses=1]
diff --git a/test/CodeGen/X86/2010-07-06-DbgCrash.ll b/test/CodeGen/X86/2010-07-06-DbgCrash.ll
index 457c49852dca..3ce36eec400a 100644
--- a/test/CodeGen/X86/2010-07-06-DbgCrash.ll
+++ b/test/CodeGen/X86/2010-07-06-DbgCrash.ll
@@ -2,28 +2,28 @@
 ; PR7545
 @.str = private constant [4 x i8] c"one\00", align 1 ; <[4 x i8]*> [#uses=1]
 @.str1 = private constant [4 x i8] c"two\00", align 1 ; <[5 x i8]*> [#uses=1]
-@C.9.2167 = internal constant [2 x i8*] [i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8]* @.str1, i64 0, i64 0)]
-!38 = !{!"0x29", !109} ; [ DW_TAG_file_type ]
-!39 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)\001\00\000\00\000", !109, !108, !108, null, null, null} ; [ DW_TAG_compile_unit ]
-!46 = !{!"0xf\00\000\0064\0064\000\000", !109, null, !47} ; [ DW_TAG_pointer_type ]
-!47 = !{!"0x24\00char\000\008\008\000\000\006", !109, null} ; [ DW_TAG_base_type ]
-!97 = !{!"0x2e\00main\00main\00main\0073\000\001\000\006\000\000\000", i32 0, !39, !98, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!98 = !{!"0x15\00\000\000\000\000\000\000", !109, null, null, !99, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+@C.9.2167 = internal constant [2 x i8*] [i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str1, i64 0, i64 0)]
+!38 = !DIFile(filename: "pbmsrch.c", directory: "/Users/grawp/LLVM/test-suite/MultiSource/Benchmarks/MiBench/office-stringsearch")
+!39 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)", isOptimized: true, emissionKind: 0, file: !109, enums: !108, retainedTypes: !108)
+!46 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !109, baseType: !47)
+!47 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!97 = !DISubprogram(name: "main", linkageName: "main", line: 73, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !39, type: !98)
+!98 = !DISubroutineType(types: !99)
 !99 = !{!100}
-!100 = !{!"0x24\00int\000\0032\0032\000\000\005", !109, null} ; [ DW_TAG_base_type ]
+!100 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !101 = !{[2 x i8*]* @C.9.2167}
-!102 = !{!"0x100\00find_strings\0075\000", !103, !38, !104} ; [ DW_TAG_auto_variable ]
-!103 = !{!"0xb\0073\000\000", null, !97} ; [ DW_TAG_lexical_block ]
-!104 = !{!"0x1\00\000\0085312\0064\000\000", !109, null, !46, !105, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 85312, align 64, offset 0] [from ]
+!102 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "find_strings", line: 75, scope: !103, file: !38, type: !104)
+!103 = distinct !DILexicalBlock(line: 73, column: 0, file: null, scope: !97)
+!104 = !DICompositeType(tag: DW_TAG_array_type, size: 85312, align: 64, file: !109, baseType: !46, elements: !105)
 !105 = !{!106}
-!106 = !{!"0x21\000\001333"}    ; [ DW_TAG_subrange_type ]
-!107 = !MDLocation(line: 73, scope: !103)
+!106 = !DISubrange(count: 1333)
+!107 = !DILocation(line: 73, scope: !103)
 !108 = !{i32 0}
-!109 = !{!"pbmsrch.c", !"/Users/grawp/LLVM/test-suite/MultiSource/Benchmarks/MiBench/office-stringsearch"}
+!109 = !DIFile(filename: "pbmsrch.c", directory: "/Users/grawp/LLVM/test-suite/MultiSource/Benchmarks/MiBench/office-stringsearch")
 
 define i32 @main() nounwind ssp {
 bb.nph:
-  tail call void @llvm.dbg.declare(metadata [2 x i8*]* @C.9.2167, metadata !102, metadata !{!"0x102"}), !dbg !107
+  tail call void @llvm.dbg.declare(metadata [2 x i8*]* @C.9.2167, metadata !102, metadata !DIExpression()), !dbg !107
   ret i32 0, !dbg !107
 }
 
diff --git a/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll b/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll
index e96da94f5a3a..33a89a04c7d4 100644
--- a/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll
+++ b/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll
@@ -10,7 +10,7 @@ target triple = "x86_64-apple-darwin10.0.0"
 
 define void @_ZN7QVectorIdE4fillERKdi(double* nocapture %t) nounwind ssp align 2 {
 entry:
-  %tmp2 = load double* %t                         ; <double> [#uses=1]
+  %tmp2 = load double, double* %t                         ; <double> [#uses=1]
   br i1 undef, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry
diff --git a/test/CodeGen/X86/2010-07-15-Crash.ll b/test/CodeGen/X86/2010-07-15-Crash.ll
index 3ac4cf5964c3..857dc3a3610f 100644
--- a/test/CodeGen/X86/2010-07-15-Crash.ll
+++ b/test/CodeGen/X86/2010-07-15-Crash.ll
@@ -6,7 +6,7 @@
 define void @foo() nounwind {
 entry:
   tail call void asm sideeffect "", "s,i,~{fpsr},~{flags}"(i8* getelementptr
-inbounds ([4 x i8]* @__FUNCTION__.1623, i64 0, i64 0), i8* getelementptr
-inbounds ([4 x i8]* @__FUNCTION__.1623, i64 0, i64 0)) nounwind
+inbounds ([4 x i8], [4 x i8]* @__FUNCTION__.1623, i64 0, i64 0), i8* getelementptr
+inbounds ([4 x i8], [4 x i8]* @__FUNCTION__.1623, i64 0, i64 0)) nounwind
   ret void
 }
diff --git a/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll b/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
index 12a8274fb56f..ab9715d22377 100644
--- a/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
+++ b/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
@@ -7,7 +7,7 @@
 
 define i32 @main() nounwind {
 entry:
-  %tmp = load i64* @g_16                          ; <i64> [#uses=1]
+  %tmp = load i64, i64* @g_16                          ; <i64> [#uses=1]
   %not.lnot = icmp ne i64 %tmp, 0                 ; <i1> [#uses=1]
   %conv = sext i1 %not.lnot to i64                ; <i64> [#uses=1]
   %and = and i64 %conv, 150                       ; <i64> [#uses=1]
@@ -20,7 +20,7 @@ entry:
 ; CHECK-NEXT: jle
 
 entry.if.end_crit_edge:                           ; preds = %entry
-  %tmp4.pre = load i32* @g_38                     ; <i32> [#uses=1]
+  %tmp4.pre = load i32, i32* @g_38                     ; <i32> [#uses=1]
   br label %if.end
 
 if.then:                                          ; preds = %entry
@@ -29,7 +29,7 @@ if.then:                                          ; preds = %entry
 
 if.end:                                           ; preds = %entry.if.end_crit_edge, %if.then
   %tmp4 = phi i32 [ %tmp4.pre, %entry.if.end_crit_edge ], [ 1, %if.then ] ; <i32> [#uses=1]
-  %call5 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32 %tmp4) nounwind ; <i32> [#uses=0]
+  %call5 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %tmp4) nounwind ; <i32> [#uses=0]
   ret i32 0
 }
 
diff --git a/test/CodeGen/X86/2010-08-04-StackVariable.ll b/test/CodeGen/X86/2010-08-04-StackVariable.ll
index e3decf0c889a..6129e78fd348 100644
--- a/test/CodeGen/X86/2010-08-04-StackVariable.ll
+++ b/test/CodeGen/X86/2010-08-04-StackVariable.ll
@@ -6,20 +6,20 @@
 define i32 @_Z3fooi4SVal(i32 %i, %struct.SVal* noalias %location) nounwind ssp {
 entry:
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !23, metadata !{!"0x102"}), !dbg !24
-  call void @llvm.dbg.value(metadata %struct.SVal* %location, i64 0, metadata !25, metadata !{!"0x102"}), !dbg !24
+  call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !23, metadata !DIExpression()), !dbg !24
+  call void @llvm.dbg.value(metadata %struct.SVal* %location, i64 0, metadata !25, metadata !DIExpression()), !dbg !24
   %0 = icmp ne i32 %i, 0, !dbg !27                ; <i1> [#uses=1]
   br i1 %0, label %bb, label %bb1, !dbg !27
 
 bb:                                               ; preds = %entry
-  %1 = getelementptr inbounds %struct.SVal* %location, i32 0, i32 1, !dbg !29 ; <i32*> [#uses=1]
-  %2 = load i32* %1, align 8, !dbg !29            ; <i32> [#uses=1]
+  %1 = getelementptr inbounds %struct.SVal, %struct.SVal* %location, i32 0, i32 1, !dbg !29 ; <i32*> [#uses=1]
+  %2 = load i32, i32* %1, align 8, !dbg !29            ; <i32> [#uses=1]
   %3 = add i32 %2, %i, !dbg !29                   ; <i32> [#uses=1]
   br label %bb2, !dbg !29
 
 bb1:                                              ; preds = %entry
-  %4 = getelementptr inbounds %struct.SVal* %location, i32 0, i32 1, !dbg !30 ; <i32*> [#uses=1]
-  %5 = load i32* %4, align 8, !dbg !30            ; <i32> [#uses=1]
+  %4 = getelementptr inbounds %struct.SVal, %struct.SVal* %location, i32 0, i32 1, !dbg !30 ; <i32*> [#uses=1]
+  %5 = load i32, i32* %4, align 8, !dbg !30            ; <i32> [#uses=1]
   %6 = sub i32 %5, 1, !dbg !30                    ; <i32> [#uses=1]
   br label %bb2, !dbg !30
 
@@ -34,10 +34,10 @@ return:                                           ; preds = %bb2
 define linkonce_odr void @_ZN4SValC1Ev(%struct.SVal* %this) nounwind ssp align 2 {
 entry:
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.value(metadata %struct.SVal* %this, i64 0, metadata !31, metadata !{!"0x102"}), !dbg !34
-  %0 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 0, !dbg !34 ; <i8**> [#uses=1]
+  call void @llvm.dbg.value(metadata %struct.SVal* %this, i64 0, metadata !31, metadata !DIExpression()), !dbg !34
+  %0 = getelementptr inbounds %struct.SVal, %struct.SVal* %this, i32 0, i32 0, !dbg !34 ; <i8**> [#uses=1]
   store i8* null, i8** %0, align 8, !dbg !34
-  %1 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 1, !dbg !34 ; <i32*> [#uses=1]
+  %1 = getelementptr inbounds %struct.SVal, %struct.SVal* %this, i32 0, i32 1, !dbg !34 ; <i32*> [#uses=1]
   store i32 0, i32* %1, align 8, !dbg !34
   br label %return, !dbg !34
 
@@ -52,20 +52,20 @@ entry:
   %0 = alloca %struct.SVal                        ; <%struct.SVal*> [#uses=3]
   %v = alloca %struct.SVal                        ; <%struct.SVal*> [#uses=4]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.declare(metadata %struct.SVal* %v, metadata !38, metadata !{!"0x102"}), !dbg !41
+  call void @llvm.dbg.declare(metadata %struct.SVal* %v, metadata !38, metadata !DIExpression()), !dbg !41
   call void @_ZN4SValC1Ev(%struct.SVal* %v) nounwind, !dbg !41
-  %1 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 1, !dbg !42 ; <i32*> [#uses=1]
+  %1 = getelementptr inbounds %struct.SVal, %struct.SVal* %v, i32 0, i32 1, !dbg !42 ; <i32*> [#uses=1]
   store i32 1, i32* %1, align 8, !dbg !42
-  %2 = getelementptr inbounds %struct.SVal* %0, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1]
-  %3 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1]
-  %4 = load i8** %3, align 8, !dbg !43            ; <i8*> [#uses=1]
+  %2 = getelementptr inbounds %struct.SVal, %struct.SVal* %0, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1]
+  %3 = getelementptr inbounds %struct.SVal, %struct.SVal* %v, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1]
+  %4 = load i8*, i8** %3, align 8, !dbg !43            ; <i8*> [#uses=1]
   store i8* %4, i8** %2, align 8, !dbg !43
-  %5 = getelementptr inbounds %struct.SVal* %0, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1]
-  %6 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1]
-  %7 = load i32* %6, align 8, !dbg !43            ; <i32> [#uses=1]
+  %5 = getelementptr inbounds %struct.SVal, %struct.SVal* %0, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1]
+  %6 = getelementptr inbounds %struct.SVal, %struct.SVal* %v, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1]
+  %7 = load i32, i32* %6, align 8, !dbg !43            ; <i32> [#uses=1]
   store i32 %7, i32* %5, align 8, !dbg !43
   %8 = call i32 @_Z3fooi4SVal(i32 2, %struct.SVal* noalias %0) nounwind, !dbg !43 ; <i32> [#uses=0]
-  call void @llvm.dbg.value(metadata i32 %8, i64 0, metadata !44, metadata !{!"0x102"}), !dbg !43
+  call void @llvm.dbg.value(metadata i32 %8, i64 0, metadata !44, metadata !DIExpression()), !dbg !43
   br label %return, !dbg !45
 
 return:                                           ; preds = %entry
@@ -78,52 +78,52 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.module.flags = !{!49}
 !46 = !{!16, !17, !20}
 
-!0 = !{!"0x2e\00SVal\00SVal\00\0011\000\000\000\006\000\000\0011", !47, !1, !14, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x13\00SVal\001\00128\0064\000\000\000", !47, !2, null, !4, null, null, null} ; [ DW_TAG_structure_type ] [SVal] [line 1, size 128, align 64, offset 0] [def] [from ]
-!2 = !{!"0x29", !47} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\004\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\000\00\000\00\001", !47, !48, !48, !46, null,  null} ; [ DW_TAG_compile_unit ]
+!0 = !DISubprogram(name: "SVal", line: 11, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, scopeLine: 11, file: !47, scope: !1, type: !14)
+!1 = !DICompositeType(tag: DW_TAG_structure_type, name: "SVal", line: 1, size: 128, align: 64, file: !47, scope: !2, elements: !4)
+!2 = !DIFile(filename: "small.cc", directory: "/Users/manav/R8248330")
+!3 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: false, emissionKind: 1, file: !47, enums: !48, retainedTypes: !48, subprograms: !46, imports:  null)
 !4 = !{!5, !7, !0, !9}
-!5 = !{!"0xd\00Data\007\0064\0064\000\000", !47, !1, !6} ; [ DW_TAG_member ]
-!6 = !{!"0xf\00\000\0064\0064\000\000", !47, !2, null} ; [ DW_TAG_pointer_type ]
-!7 = !{!"0xd\00Kind\008\0032\0032\0064\000", !47, !1, !8} ; [ DW_TAG_member ]
-!8 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", !47, !2} ; [ DW_TAG_base_type ]
-!9 = !{!"0x2e\00~SVal\00~SVal\00\0012\000\000\000\006\000\000\0012", !47, !1, !10, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!10 = !{!"0x15\00\000\000\000\000\000\000", !47, !2, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DIDerivedType(tag: DW_TAG_member, name: "Data", line: 7, size: 64, align: 64, file: !47, scope: !1, baseType: !6)
+!6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !47, scope: !2, baseType: null)
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "Kind", line: 8, size: 32, align: 32, offset: 64, file: !47, scope: !1, baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!9 = !DISubprogram(name: "~SVal", line: 12, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, scopeLine: 12, file: !47, scope: !1, type: !10)
+!10 = !DISubroutineType(types: !11)
 !11 = !{null, !12, !13}
-!12 = !{!"0xf\00\000\0064\0064\000\0064", !47, !2, !1} ; [ DW_TAG_pointer_type ]
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", !47, !2} ; [ DW_TAG_base_type ]
-!14 = !{!"0x15\00\000\000\000\000\000\000", !47, !2, null, !15, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, file: !47, scope: !2, baseType: !1)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!14 = !DISubroutineType(types: !15)
 !15 = !{null, !12}
-!16 = !{!"0x2e\00SVal\00SVal\00_ZN4SValC1Ev\0011\000\001\000\006\000\000\0011", !47, !1, !14, null, void (%struct.SVal*)* @_ZN4SValC1Ev, null, null, null} ; [ DW_TAG_subprogram ]
-!17 = !{!"0x2e\00foo\00foo\00_Z3fooi4SVal\0016\000\001\000\006\000\000\0016", !47, !2, !18, null, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal, null, null, null} ; [ DW_TAG_subprogram ]
-!18 = !{!"0x15\00\000\000\000\000\000\000", !47, !2, null, !19, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!16 = !DISubprogram(name: "SVal", linkageName: "_ZN4SValC1Ev", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 11, file: !47, scope: !1, type: !14, function: void (%struct.SVal*)* @_ZN4SValC1Ev)
+!17 = !DISubprogram(name: "foo", linkageName: "_Z3fooi4SVal", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 16, file: !47, scope: !2, type: !18, function: i32 (i32, %struct.SVal*)* @_Z3fooi4SVal)
+!18 = !DISubroutineType(types: !19)
 !19 = !{!13, !13, !1}
-!20 = !{!"0x2e\00main\00main\00main\0023\000\001\000\006\000\000\0023", !47, !2, !21, null, i32 ()* @main, null, null, null} ; [ DW_TAG_subprogram ]
-!21 = !{!"0x15\00\000\000\000\000\000\000", !47, !2, null, !22, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!20 = !DISubprogram(name: "main", linkageName: "main", line: 23, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 23, file: !47, scope: !2, type: !21, function: i32 ()* @main)
+!21 = !DISubroutineType(types: !22)
 !22 = !{!13}
-!23 = !{!"0x101\00i\0016\000", !17, !2, !13} ; [ DW_TAG_arg_variable ]
-!24 = !MDLocation(line: 16, scope: !17)
-!25 = !{!"0x101\00location\0016\000", !17, !2, !26} ; [ DW_TAG_arg_variable ]
-!26 = !{!"0x10\00SVal\000\0064\0064\000\000", !47, !2, !1} ; [ DW_TAG_reference_type ]
-!27 = !MDLocation(line: 17, scope: !28)
-!28 = !{!"0xb\0016\000\002", !47, !17} ; [ DW_TAG_lexical_block ]
-!29 = !MDLocation(line: 18, scope: !28)
-!30 = !MDLocation(line: 20, scope: !28)
-!31 = !{!"0x101\00this\0011\000", !16, !2, !32} ; [ DW_TAG_arg_variable ]
-!32 = !{!"0x26\00\000\0064\0064\000\0064", !47, !2, !33} ; [ DW_TAG_const_type ]
-!33 = !{!"0xf\00\000\0064\0064\000\000", !47, !2, !1} ; [ DW_TAG_pointer_type ]
-!34 = !MDLocation(line: 11, scope: !16)
-!35 = !MDLocation(line: 11, scope: !36)
-!36 = !{!"0xb\0011\000\001", !47, !37} ; [ DW_TAG_lexical_block ]
-!37 = !{!"0xb\0011\000\000", !47, !16} ; [ DW_TAG_lexical_block ]
-!38 = !{!"0x100\00v\0024\000", !39, !2, !1} ; [ DW_TAG_auto_variable ]
-!39 = !{!"0xb\0023\000\004", !47, !40} ; [ DW_TAG_lexical_block ]
-!40 = !{!"0xb\0023\000\003", !47, !20} ; [ DW_TAG_lexical_block ]
-!41 = !MDLocation(line: 24, scope: !39)
-!42 = !MDLocation(line: 25, scope: !39)
-!43 = !MDLocation(line: 26, scope: !39)
-!44 = !{!"0x100\00k\0026\000", !39, !2, !13} ; [ DW_TAG_auto_variable ]
-!45 = !MDLocation(line: 27, scope: !39)
-!47 = !{!"small.cc", !"/Users/manav/R8248330"}
-!48 = !{i32 0}
-!49 = !{i32 1, !"Debug Info Version", i32 2}
+!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 16, arg: 0, scope: !17, file: !2, type: !13)
+!24 = !DILocation(line: 16, scope: !17)
+!25 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "location", line: 16, arg: 0, scope: !17, file: !2, type: !26)
+!26 = !DIDerivedType(tag: DW_TAG_reference_type, name: "SVal", size: 64, align: 64, file: !47, scope: !2, baseType: !1)
+!27 = !DILocation(line: 17, scope: !28)
+!28 = distinct !DILexicalBlock(line: 16, column: 0, file: !47, scope: !17)
+!29 = !DILocation(line: 18, scope: !28)
+!30 = !DILocation(line: 20, scope: !28)
+!31 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 11, arg: 0, scope: !16, file: !2, type: !32)
+!32 = !DIDerivedType(tag: DW_TAG_const_type, size: 64, align: 64, flags: DIFlagArtificial, file: !47, scope: !2, baseType: !33)
+!33 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !47, scope: !2, baseType: !1)
+!34 = !DILocation(line: 11, scope: !16)
+!35 = !DILocation(line: 11, scope: !36)
+!36 = distinct !DILexicalBlock(line: 11, column: 0, file: !47, scope: !37)
+!37 = distinct !DILexicalBlock(line: 11, column: 0, file: !47, scope: !16)
+!38 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "v", line: 24, scope: !39, file: !2, type: !1)
+!39 = distinct !DILexicalBlock(line: 23, column: 0, file: !47, scope: !40)
+!40 = distinct !DILexicalBlock(line: 23, column: 0, file: !47, scope: !20)
+!41 = !DILocation(line: 24, scope: !39)
+!42 = !DILocation(line: 25, scope: !39)
+!43 = !DILocation(line: 26, scope: !39)
+!44 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 26, scope: !39, file: !2, type: !13)
+!45 = !DILocation(line: 27, scope: !39)
+!47 = !DIFile(filename: "small.cc", directory: "/Users/manav/R8248330")
+!48 = !{}
+!49 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/2010-09-01-RemoveCopyByCommutingDef.ll b/test/CodeGen/X86/2010-09-01-RemoveCopyByCommutingDef.ll
index e5542baf2ee8..b05664d758cf 100644
--- a/test/CodeGen/X86/2010-09-01-RemoveCopyByCommutingDef.ll
+++ b/test/CodeGen/X86/2010-09-01-RemoveCopyByCommutingDef.ll
@@ -8,7 +8,7 @@ define void @f(i32* %w, i32* %h, i8* %_this, i8* %image) nounwind ssp {
   %x1 = tail call i64 @g(i8* %_this, i8* %image) nounwind ; <i64> [#uses=3]
   %tmp1 = trunc i64 %x1 to i32                     ; <i32> [#uses=1]
 ; CHECK: movl (%r{{.*}}), %
-  %x4 = load i32* %h, align 4                      ; <i32> [#uses=1]
+  %x4 = load i32, i32* %h, align 4                      ; <i32> [#uses=1]
 
 ; The imull clobbers a 32-bit register.
 ; CHECK: imull %{{...}}, %e[[CLOBBER:..]]
diff --git a/test/CodeGen/X86/2010-09-16-EmptyFilename.ll b/test/CodeGen/X86/2010-09-16-EmptyFilename.ll
index cf9897ac03ad..d94bd1c79f91 100644
--- a/test/CodeGen/X86/2010-09-16-EmptyFilename.ll
+++ b/test/CodeGen/X86/2010-09-16-EmptyFilename.ll
@@ -15,21 +15,21 @@ entry:
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!17}
 
-!0 = !{!"0x2e\00foo\00foo\00foo\0053\000\001\000\006\000\000\000", !14, !1, !3, null, i32 ()* @foo, null, null, null} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !14} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 2.9 (trunk 114084)\000\00\000\00\000", !15, !16, !16, !13, null, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !14, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "foo", linkageName: "foo", line: 53, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !14, scope: !1, type: !3, function: i32 ()* @foo)
+!1 = !DIFile(filename: "", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 2.9 (trunk 114084)", isOptimized: false, emissionKind: 0, file: !15, enums: !16, retainedTypes: !16, subprograms: !13)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", !14, !1} ; [ DW_TAG_base_type ]
-!6 = !{!"0x2e\00bar\00bar\00bar\004\000\001\000\006\000\000\000", !15, !7, !3, null, i32 ()* @bar, null, null, null} ; [ DW_TAG_subprogram ]
-!7 = !{!"0x29", !15} ; [ DW_TAG_file_type ]
-!8 = !MDLocation(line: 53, column: 13, scope: !9)
-!9 = !{!"0xb\0053\0011\000", !14, !0} ; [ DW_TAG_lexical_block ]
-!10 = !MDLocation(line: 4, column: 13, scope: !11)
-!11 = !{!"0xb\004\0013\002", !15, !12} ; [ DW_TAG_lexical_block ]
-!12 = !{!"0xb\004\0011\001", !15, !6} ; [ DW_TAG_lexical_block ]
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DISubprogram(name: "bar", linkageName: "bar", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !15, scope: !7, type: !3, function: i32 ()* @bar)
+!7 = !DIFile(filename: "bug.c", directory: "/private/tmp")
+!8 = !DILocation(line: 53, column: 13, scope: !9)
+!9 = distinct !DILexicalBlock(line: 53, column: 11, file: !14, scope: !0)
+!10 = !DILocation(line: 4, column: 13, scope: !11)
+!11 = distinct !DILexicalBlock(line: 4, column: 13, file: !15, scope: !12)
+!12 = distinct !DILexicalBlock(line: 4, column: 11, file: !15, scope: !6)
 !13 = !{!0, !6}
-!14 = !{!"", !"/private/tmp"}
-!15 = !{!"bug.c", !"/private/tmp"}
-!16 = !{i32 0}
-!17 = !{i32 1, !"Debug Info Version", i32 2}
+!14 = !DIFile(filename: "", directory: "/private/tmp")
+!15 = !DIFile(filename: "bug.c", directory: "/private/tmp")
+!16 = !{}
+!17 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/2010-09-16-asmcrash.ll b/test/CodeGen/X86/2010-09-16-asmcrash.ll
index 7aa9f32d41c4..81b0fc560ee7 100644
--- a/test/CodeGen/X86/2010-09-16-asmcrash.ll
+++ b/test/CodeGen/X86/2010-09-16-asmcrash.ll
@@ -30,7 +30,7 @@ entry:
   br i1 undef, label %while.cond.preheader, label %sem_check_validity.exit
 
 while.cond.preheader:                             ; preds = %entry
-  %tmp4 = getelementptr inbounds %struct._sem* %sem, i64 0, i32 1, i32 1
+  %tmp4 = getelementptr inbounds %struct._sem, %struct._sem* %sem, i64 0, i32 1, i32 1
   br label %while.cond
 
 sem_check_validity.exit:                          ; preds = %entry
diff --git a/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll b/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll
index 39d89e3d8276..b7380196bd9b 100644
--- a/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll
+++ b/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll
@@ -7,10 +7,10 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
 define fastcc i32 @cli_magic_scandesc(i8* %in) nounwind ssp {
 entry:
   %a = alloca [64 x i8]
-  %b = getelementptr inbounds [64 x i8]* %a, i64 0, i32 0
-  %c = getelementptr inbounds [64 x i8]* %a, i64 0, i32 30
-  %d = load i8* %b, align 8
-  %e = load i8* %c, align 8
+  %b = getelementptr inbounds [64 x i8], [64 x i8]* %a, i64 0, i32 0
+  %c = getelementptr inbounds [64 x i8], [64 x i8]* %a, i64 0, i32 30
+  %d = load i8, i8* %b, align 8
+  %e = load i8, i8* %c, align 8
   %f = bitcast [64 x i8]* %a to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %f, i8* %in, i64 64, i32 8, i1 false) nounwind
   store i8 %d, i8* %b, align 8
diff --git a/test/CodeGen/X86/2010-09-30-CMOV-JumpTable-PHI.ll b/test/CodeGen/X86/2010-09-30-CMOV-JumpTable-PHI.ll
index 73e996c5d553..b8abd9c9e7d4 100644
--- a/test/CodeGen/X86/2010-09-30-CMOV-JumpTable-PHI.ll
+++ b/test/CodeGen/X86/2010-09-30-CMOV-JumpTable-PHI.ll
@@ -19,7 +19,7 @@ declare i32 @strlen(i8* nocapture) nounwind readonly
 define hidden zeroext i8 @f(i8* %this, i8* %Name.0, i32 %Name.1, i8* noalias %NameLoc, i8* %Operands) nounwind align 2 {
 bb.i:
   %0 = icmp eq i8 undef, 0
-  %iftmp.285.0 = select i1 %0, i8* getelementptr inbounds ([5 x i8]* @.str1189, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @.str706, i32 0, i32 0)
+  %iftmp.285.0 = select i1 %0, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str1189, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str706, i32 0, i32 0)
   %1 = call i32 @strlen(i8* %iftmp.285.0) nounwind readonly
   switch i32 %Name.1, label %_ZNK4llvm12StringSwitchINS_9StringRefES1_E7DefaultERKS1_.exit [
     i32 3, label %bb1.i
@@ -63,7 +63,7 @@ _ZNK4llvm12StringSwitchINS_9StringRefES1_E7DefaultERKS1_.exit: ; preds = %bb.i18
   br i1 undef, label %bb141, label %_ZNK4llvm9StringRef10startswithES0_.exit
 
 _ZNK4llvm9StringRef10startswithES0_.exit:         ; preds = %_ZNK4llvm12StringSwitchINS_9StringRefES1_E7DefaultERKS1_.exit
-  %2 = call i32 @memcmp(i8* %PatchedName.0.0, i8* getelementptr inbounds ([4 x i8]* @.str146, i32 0, i32 0), i32 3) nounwind readonly
+  %2 = call i32 @memcmp(i8* %PatchedName.0.0, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str146, i32 0, i32 0), i32 3) nounwind readonly
   unreachable
 
 bb141:                                            ; preds = %_ZNK4llvm12StringSwitchINS_9StringRefES1_E7DefaultERKS1_.exit
diff --git a/test/CodeGen/X86/2010-10-08-cmpxchg8b.ll b/test/CodeGen/X86/2010-10-08-cmpxchg8b.ll
index ebf51a5d660a..ee50cb13e634 100644
--- a/test/CodeGen/X86/2010-10-08-cmpxchg8b.ll
+++ b/test/CodeGen/X86/2010-10-08-cmpxchg8b.ll
@@ -16,8 +16,7 @@ define void @foo(i64* %ptr) nounwind inlinehint {
 entry:
   br label %loop
 loop:
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b
+; CHECK: lock cmpxchg8b
   %pair = cmpxchg i64* %ptr, i64 0, i64 1 monotonic monotonic
   %r = extractvalue { i64, i1 } %pair, 0
   %stored1  = icmp eq i64 %r, 0
diff --git a/test/CodeGen/X86/2010-11-02-DbgParameter.ll b/test/CodeGen/X86/2010-11-02-DbgParameter.ll
index df3aa1f2ab37..124cc9a430e8 100644
--- a/test/CodeGen/X86/2010-11-02-DbgParameter.ll
+++ b/test/CodeGen/X86/2010-11-02-DbgParameter.ll
@@ -9,7 +9,7 @@ target triple = "i386-apple-darwin11.0.0"
 define i32 @foo(%struct.bar* nocapture %i) nounwind readnone optsize noinline ssp {
 ; CHECK: TAG_formal_parameter
 entry:
-  tail call void @llvm.dbg.value(metadata %struct.bar* %i, i64 0, metadata !6, metadata !{!"0x102"}), !dbg !12
+  tail call void @llvm.dbg.value(metadata %struct.bar* %i, i64 0, metadata !6, metadata !DIExpression()), !dbg !12
   ret i32 1, !dbg !13
 }
 
@@ -18,23 +18,23 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!19}
 
-!0 = !{!"0x2e\00foo\00foo\00\003\000\001\000\006\00256\001\003", !17, !1, !3, null, i32 (%struct.bar*)* @foo, null, null, !16} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !17} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 2.9 (trunk 117922)\001\00\000\00\000", !17, !18, !18, !15, null,  null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !17, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "foo", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !17, scope: !1, type: !3, function: i32 (%struct.bar*)* @foo, variables: !16)
+!1 = !DIFile(filename: "one.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 2.9 (trunk 117922)", isOptimized: true, emissionKind: 0, file: !17, enums: !18, retainedTypes: !18, subprograms: !15, imports:  null)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", !17, !2} ; [ DW_TAG_base_type ]
-!6 = !{!"0x101\00i\003\000", !0, !1, !7} ; [ DW_TAG_arg_variable ]
-!7 = !{!"0xf\00\000\0032\0032\000\000", !17, !1, !8} ; [ DW_TAG_pointer_type ]
-!8 = !{!"0x13\00bar\002\0064\0032\000\000\000", !17, !1, null, !9, null, null, null} ; [ DW_TAG_structure_type ] [bar] [line 2, size 64, align 32, offset 0] [def] [from ]
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 3, arg: 0, scope: !0, file: !1, type: !7)
+!7 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !17, scope: !1, baseType: !8)
+!8 = !DICompositeType(tag: DW_TAG_structure_type, name: "bar", line: 2, size: 64, align: 32, file: !17, scope: !1, elements: !9)
 !9 = !{!10, !11}
-!10 = !{!"0xd\00x\002\0032\0032\000\000", !17,  !1, !5} ; [ DW_TAG_member ]
-!11 = !{!"0xd\00y\002\0032\0032\0032\000", !17, !1, !5} ; [ DW_TAG_member ]
-!12 = !MDLocation(line: 3, column: 47, scope: !0)
-!13 = !MDLocation(line: 4, column: 2, scope: !14)
-!14 = !{!"0xb\003\0050\000", !17, !0} ; [ DW_TAG_lexical_block ]
+!10 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 2, size: 32, align: 32, file: !17, scope:  !1, baseType: !5)
+!11 = !DIDerivedType(tag: DW_TAG_member, name: "y", line: 2, size: 32, align: 32, offset: 32, file: !17, scope: !1, baseType: !5)
+!12 = !DILocation(line: 3, column: 47, scope: !0)
+!13 = !DILocation(line: 4, column: 2, scope: !14)
+!14 = distinct !DILexicalBlock(line: 3, column: 50, file: !17, scope: !0)
 !15 = !{!0}
 !16 = !{!6}
-!17 = !{!"one.c", !"/private/tmp"}
-!18 = !{i32 0}
-!19 = !{i32 1, !"Debug Info Version", i32 2}
+!17 = !DIFile(filename: "one.c", directory: "/private/tmp")
+!18 = !{}
+!19 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/2010-11-09-MOVLPS.ll b/test/CodeGen/X86/2010-11-09-MOVLPS.ll
index 710cb86f5374..4b937333c8e9 100644
--- a/test/CodeGen/X86/2010-11-09-MOVLPS.ll
+++ b/test/CodeGen/X86/2010-11-09-MOVLPS.ll
@@ -21,42 +21,42 @@ entry:
   store i8* %a, i8** %a_addr
   store %0* %b, %0** %b_addr
   store %0* %c, %0** %c_addr
-  %0 = load i8** %a_addr, align 64
-  %1 = load %0** %b_addr, align 64
-  %2 = load %0** %c_addr, align 64
+  %0 = load i8*, i8** %a_addr, align 64
+  %1 = load %0*, %0** %b_addr, align 64
+  %2 = load %0*, %0** %c_addr, align 64
   %"ssa point" = bitcast i32 0 to i32
   br label %"2"
 
 "2":                                              ; preds = %entry
   %3 = bitcast i8* %0 to <2 x i32>*
-  %4 = getelementptr inbounds %0* %1, i32 0, i32 0
+  %4 = getelementptr inbounds %0, %0* %1, i32 0, i32 0
   %5 = bitcast %"int[]"* %4 to <4 x float>*
-  %6 = load <4 x float>* %5, align 16
+  %6 = load <4 x float>, <4 x float>* %5, align 16
   %7 = bitcast <2 x i32>* %3 to <2 x float>*
   %8 = bitcast <2 x float>* %7 to double*
-  %9 = load double* %8
+  %9 = load double, double* %8
   %10 = insertelement <2 x double> undef, double %9, i32 0
   %11 = insertelement <2 x double> %10, double undef, i32 1
   %12 = bitcast <2 x double> %11 to <4 x float>
   %13 = shufflevector <4 x float> %6, <4 x float> %12, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
-  %14 = getelementptr inbounds %0* %1, i32 0, i32 0
+  %14 = getelementptr inbounds %0, %0* %1, i32 0, i32 0
   %15 = bitcast %"int[]"* %14 to <4 x float>*
   store <4 x float> %13, <4 x float>* %15, align 16
   %16 = bitcast i8* %0 to <2 x i32>*
   %17 = bitcast <2 x i32>* %16 to i8*
-  %18 = getelementptr i8* %17, i64 8
+  %18 = getelementptr i8, i8* %17, i64 8
   %19 = bitcast i8* %18 to <2 x i32>*
-  %20 = getelementptr inbounds %0* %2, i32 0, i32 0
+  %20 = getelementptr inbounds %0, %0* %2, i32 0, i32 0
   %21 = bitcast %"int[]"* %20 to <4 x float>*
-  %22 = load <4 x float>* %21, align 16
+  %22 = load <4 x float>, <4 x float>* %21, align 16
   %23 = bitcast <2 x i32>* %19 to <2 x float>*
   %24 = bitcast <2 x float>* %23 to double*
-  %25 = load double* %24
+  %25 = load double, double* %24
   %26 = insertelement <2 x double> undef, double %25, i32 0
   %27 = insertelement <2 x double> %26, double undef, i32 1
   %28 = bitcast <2 x double> %27 to <4 x float>
   %29 = shufflevector <4 x float> %22, <4 x float> %28, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
-  %30 = getelementptr inbounds %0* %2, i32 0, i32 0
+  %30 = getelementptr inbounds %0, %0* %2, i32 0, i32 0
   %31 = bitcast %"int[]"* %30 to <4 x float>*
   store <4 x float> %29, <4 x float>* %31, align 16
   br label %return
diff --git a/test/CodeGen/X86/2010-11-18-SelectOfExtload.ll b/test/CodeGen/X86/2010-11-18-SelectOfExtload.ll
index 6d54c7e2982b..331e83bb5067 100644
--- a/test/CodeGen/X86/2010-11-18-SelectOfExtload.ll
+++ b/test/CodeGen/X86/2010-11-18-SelectOfExtload.ll
@@ -4,11 +4,11 @@
 @s = external global i8
 define i32 @foo(i1 %cond) {
 ; CHECK: @foo
-  %u_base = load i8* @u
+  %u_base = load i8, i8* @u
   %u_val = zext i8 %u_base to i32
 ; CHECK: movzbl
 ; CHECK: movsbl
-  %s_base = load i8* @s
+  %s_base = load i8, i8* @s
   %s_val = sext i8 %s_base to i32
   %val = select i1 %cond, i32 %u_val, i32 %s_val
   ret i32 %val
diff --git a/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll b/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll
index 8404020c91f1..0ded66fa3bf9 100644
--- a/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll
+++ b/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll
@@ -22,8 +22,8 @@ target triple = "x86_64-apple-darwin10.0.0"
 
 define i64 @gcd(i64 %a, i64 %b) nounwind readnone optsize noinline ssp {
 entry:
-  tail call void @llvm.dbg.value(metadata i64 %a, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !18
-  tail call void @llvm.dbg.value(metadata i64 %b, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !19
+  tail call void @llvm.dbg.value(metadata i64 %a, i64 0, metadata !10, metadata !DIExpression()), !dbg !18
+  tail call void @llvm.dbg.value(metadata i64 %b, i64 0, metadata !11, metadata !DIExpression()), !dbg !19
   br label %while.body, !dbg !20
 
 while.body:                                       ; preds = %while.body, %entry
@@ -34,14 +34,14 @@ while.body:                                       ; preds = %while.body, %entry
   br i1 %cmp, label %if.then, label %while.body, !dbg !23
 
 if.then:                                          ; preds = %while.body
-  tail call void @llvm.dbg.value(metadata i64 %rem, i64 0, metadata !12, metadata !{!"0x102"}), !dbg !21
+  tail call void @llvm.dbg.value(metadata i64 %rem, i64 0, metadata !12, metadata !DIExpression()), !dbg !21
   ret i64 %b.addr.0, !dbg !23
 }
 
 define i32 @main() nounwind optsize ssp {
 entry:
   %call = tail call i32 @rand() nounwind optsize, !dbg !24
-  tail call void @llvm.dbg.value(metadata i32 %call, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !24
+  tail call void @llvm.dbg.value(metadata i32 %call, i64 0, metadata !14, metadata !DIExpression()), !dbg !24
   %cmp = icmp ugt i32 %call, 21, !dbg !25
   br i1 %cmp, label %cond.true, label %cond.end, !dbg !25
 
@@ -51,7 +51,7 @@ cond.true:                                        ; preds = %entry
 
 cond.end:                                         ; preds = %entry, %cond.true
   %cond = phi i32 [ %call1, %cond.true ], [ %call, %entry ], !dbg !25
-  tail call void @llvm.dbg.value(metadata i32 %cond, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !25
+  tail call void @llvm.dbg.value(metadata i32 %cond, i64 0, metadata !17, metadata !DIExpression()), !dbg !25
   %conv = sext i32 %cond to i64, !dbg !26
   %conv5 = zext i32 %call to i64, !dbg !26
   %call6 = tail call i64 @gcd(i64 %conv, i64 %conv5) optsize, !dbg !26
@@ -59,8 +59,8 @@ cond.end:                                         ; preds = %entry, %cond.true
   br i1 %cmp7, label %return, label %if.then, !dbg !26
 
 if.then:                                          ; preds = %cond.end
-  %puts = tail call i32 @puts(i8* getelementptr inbounds ([21 x i8]* @str, i64 0, i64 0))
-  %call12 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str1, i64 0, i64 0), i32 %call, i32 %cond) nounwind optsize, !dbg !26
+  %puts = tail call i32 @puts(i8* getelementptr inbounds ([21 x i8], [21 x i8]* @str, i64 0, i64 0))
+  %call12 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str1, i64 0, i64 0), i32 %call, i32 %cond) nounwind optsize, !dbg !26
   ret i32 1, !dbg !27
 
 return:                                           ; preds = %cond.end
@@ -78,37 +78,37 @@ declare i32 @puts(i8* nocapture) nounwind
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!33}
 
-!0 = !{!"0x2e\00gcd\00gcd\00\005\000\001\000\006\00256\001\000", !31, !1, !3, null, i64 (i64, i64)* @gcd, null, null, !29} ; [ DW_TAG_subprogram ] [line 5] [def] [scope 0] [gcd]
-!1 = !{!"0x29", !31} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 2.9 (trunk 124117)\001\00\000\00\001", !31, !32, !32, !28, null,  null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !31, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "gcd", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !31, scope: !1, type: !3, function: i64 (i64, i64)* @gcd, variables: !29)
+!1 = !DIFile(filename: "rem_small.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 2.9 (trunk 124117)", isOptimized: true, emissionKind: 1, file: !31, enums: !32, retainedTypes: !32, subprograms: !28, imports:  null)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00long int\000\0064\0064\000\000\005", null, !2} ; [ DW_TAG_base_type ]
-!6 = !{!"0x2e\00main\00main\00\0025\000\001\000\006\000\001\000", !31, !1, !7, null, i32 ()* @main, null, null, !30} ; [ DW_TAG_subprogram ] [line 25] [def] [scope 0] [main]
-!7 = !{!"0x15\00\000\000\000\000\000\000", !31, !1, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "long int", size: 64, align: 64, encoding: DW_ATE_signed)
+!6 = !DISubprogram(name: "main", line: 25, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, file: !31, scope: !1, type: !7, function: i32 ()* @main, variables: !30)
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ]
-!10 = !{!"0x101\00a\005\000", !0, !1, !5} ; [ DW_TAG_arg_variable ]
-!11 = !{!"0x101\00b\005\000", !0, !1, !5} ; [ DW_TAG_arg_variable ]
-!12 = !{!"0x100\00c\006\000", !13, !1, !5} ; [ DW_TAG_auto_variable ]
-!13 = !{!"0xb\005\0052\000", !31, !0} ; [ DW_TAG_lexical_block ]
-!14 = !{!"0x100\00m\0026\000", !15, !1, !16} ; [ DW_TAG_auto_variable ]
-!15 = !{!"0xb\0025\0012\002", !31, !6} ; [ DW_TAG_lexical_block ]
-!16 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, !2} ; [ DW_TAG_base_type ]
-!17 = !{!"0x100\00z_s\0027\000", !15, !1, !9} ; [ DW_TAG_auto_variable ]
-!18 = !MDLocation(line: 5, column: 41, scope: !0)
-!19 = !MDLocation(line: 5, column: 49, scope: !0)
-!20 = !MDLocation(line: 7, column: 5, scope: !13)
-!21 = !MDLocation(line: 8, column: 9, scope: !22)
-!22 = !{!"0xb\007\0014\001", !31, !13} ; [ DW_TAG_lexical_block ]
-!23 = !MDLocation(line: 9, column: 9, scope: !22)
-!24 = !MDLocation(line: 26, column: 38, scope: !15)
-!25 = !MDLocation(line: 27, column: 38, scope: !15)
-!26 = !MDLocation(line: 28, column: 9, scope: !15)
-!27 = !MDLocation(line: 30, column: 1, scope: !15)
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 5, arg: 0, scope: !0, file: !1, type: !5)
+!11 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 5, arg: 0, scope: !0, file: !1, type: !5)
+!12 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "c", line: 6, scope: !13, file: !1, type: !5)
+!13 = distinct !DILexicalBlock(line: 5, column: 52, file: !31, scope: !0)
+!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 26, scope: !15, file: !1, type: !16)
+!15 = distinct !DILexicalBlock(line: 25, column: 12, file: !31, scope: !6)
+!16 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "z_s", line: 27, scope: !15, file: !1, type: !9)
+!18 = !DILocation(line: 5, column: 41, scope: !0)
+!19 = !DILocation(line: 5, column: 49, scope: !0)
+!20 = !DILocation(line: 7, column: 5, scope: !13)
+!21 = !DILocation(line: 8, column: 9, scope: !22)
+!22 = distinct !DILexicalBlock(line: 7, column: 14, file: !31, scope: !13)
+!23 = !DILocation(line: 9, column: 9, scope: !22)
+!24 = !DILocation(line: 26, column: 38, scope: !15)
+!25 = !DILocation(line: 27, column: 38, scope: !15)
+!26 = !DILocation(line: 28, column: 9, scope: !15)
+!27 = !DILocation(line: 30, column: 1, scope: !15)
 !28 = !{!0, !6}
 !29 = !{!10, !11, !12}
 !30 = !{!14, !17}
-!31 = !{!"rem_small.c", !"/private/tmp"}
-!32 = !{i32 0}
-!33 = !{i32 1, !"Debug Info Version", i32 2}
+!31 = !DIFile(filename: "rem_small.c", directory: "/private/tmp")
+!32 = !{}
+!33 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/2011-02-12-shuffle.ll b/test/CodeGen/X86/2011-02-12-shuffle.ll
index b4d56d193ca3..40e36678a557 100644
--- a/test/CodeGen/X86/2011-02-12-shuffle.ll
+++ b/test/CodeGen/X86/2011-02-12-shuffle.ll
@@ -9,7 +9,7 @@ entry:
   br i1 undef, label %if.end, label %UnifiedReturnBlock
 
 if.end:                                           ; preds = %entry
-  %tmp1067 = load <16 x i32> addrspace(1)* null, align 64
+  %tmp1067 = load <16 x i32>, <16 x i32> addrspace(1)* null, align 64
   %tmp1082 = shufflevector         <16 x i32> <i32 0, i32 0, i32 0, i32 undef, i32 undef, i32 0, i32 0, i32 undef, i32 0, i32 0, i32 undef, i32 undef, i32 0, i32 undef, i32 undef, i32 undef>, 
                                                                                                                 <16 x i32> %tmp1067, 
                                                                                                                 <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 26, i32 5, i32 6, i32 undef, i32 8, i32 9, i32 31, i32 30, i32 12, i32 undef, i32 undef, i32 undef>
diff --git a/test/CodeGen/X86/2011-02-21-VirtRegRewriter-KillSubReg.ll b/test/CodeGen/X86/2011-02-21-VirtRegRewriter-KillSubReg.ll
index f982723781ea..7821f0537e70 100644
--- a/test/CodeGen/X86/2011-02-21-VirtRegRewriter-KillSubReg.ll
+++ b/test/CodeGen/X86/2011-02-21-VirtRegRewriter-KillSubReg.ll
@@ -18,7 +18,7 @@ if.then751:
 if.then758:
   %add761 = add i32 %call747, 4
   %add763 = add i32 %add761, %call747
-  %add.ptr768 = getelementptr inbounds [516 x i8]* null, i32 0, i32 %add761
+  %add.ptr768 = getelementptr inbounds [516 x i8], [516 x i8]* null, i32 0, i32 %add761
   br i1 undef, label %cond.false783, label %cond.true771
 
 cond.true771:
@@ -33,7 +33,7 @@ cond.false783:
 cond.end791:
   %conv801 = trunc i32 %call747 to i8
   %add.ptr822.sum = add i32 %call747, 3
-  %arrayidx833 = getelementptr inbounds [516 x i8]* null, i32 0, i32 %add.ptr822.sum
+  %arrayidx833 = getelementptr inbounds [516 x i8], [516 x i8]* null, i32 0, i32 %add.ptr822.sum
   store i8 %conv801, i8* %arrayidx833, align 1
   %cmp841 = icmp eq i8* undef, null
   br i1 %cmp841, label %if.end849, label %if.then843
diff --git a/test/CodeGen/X86/2011-02-23-UnfoldBug.ll b/test/CodeGen/X86/2011-02-23-UnfoldBug.ll
index 900106aac351..90b90d7f9f6a 100644
--- a/test/CodeGen/X86/2011-02-23-UnfoldBug.ll
+++ b/test/CodeGen/X86/2011-02-23-UnfoldBug.ll
@@ -22,7 +22,7 @@ for.body33.lr.ph:                                 ; preds = %for.body
 for.end:                                          ; preds = %for.body
   %vecins.i94 = insertelement <2 x double> undef, double 0.000000e+00, i32 0
   %cmpsd.i = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %vecins.i94, <2 x double> <double 0x3FE984B204153B34, double 0x3FE984B204153B34>, i8 2) nounwind
-  tail call void (...)* @_mm_movemask_pd(<2 x double> %cmpsd.i) nounwind
+  tail call void (...) @_mm_movemask_pd(<2 x double> %cmpsd.i) nounwind
   br i1 undef, label %if.then67, label %if.end71
 
 if.then67:                                        ; preds = %for.end
diff --git a/test/CodeGen/X86/2011-03-02-DAGCombiner.ll b/test/CodeGen/X86/2011-03-02-DAGCombiner.ll
index be58cedfdaa7..d25fbf7b71f1 100644
--- a/test/CodeGen/X86/2011-03-02-DAGCombiner.ll
+++ b/test/CodeGen/X86/2011-03-02-DAGCombiner.ll
@@ -13,23 +13,23 @@ entry:
   %K = alloca %0, align 4
   store i32 0, i32* %retval
   %0 = bitcast %0* %K to i32*
-  %1 = load i32* %0, align 4
+  %1 = load i32, i32* %0, align 4
   %2 = and i32 %1, -121
   %3 = or i32 %2, 32
   store i32 %3, i32* %0, align 4
   %4 = bitcast %0* %K to i32*
-  %5 = load i32* %4, align 4
+  %5 = load i32, i32* %4, align 4
   %6 = lshr i32 %5, 3
   %bf.clear = and i32 %6, 15
   %conv = sitofp i32 %bf.clear to float
-  %f = getelementptr inbounds %struct.anon* %F, i32 0, i32 0
-  %tmp = load float* %f, align 4
+  %f = getelementptr inbounds %struct.anon, %struct.anon* %F, i32 0, i32 0
+  %tmp = load float, float* %f, align 4
   %sub = fsub float %tmp, %conv
   store float %sub, float* %f, align 4
-  %ld = getelementptr inbounds %struct.anon* %F, i32 0, i32 1
-  %tmp1 = load x86_fp80* %ld, align 16
+  %ld = getelementptr inbounds %struct.anon, %struct.anon* %F, i32 0, i32 1
+  %tmp1 = load x86_fp80, x86_fp80* %ld, align 16
   %7 = bitcast %0* %K to i32*
-  %8 = load i32* %7, align 4
+  %8 = load i32, i32* %7, align 4
   %9 = lshr i32 %8, 7
   %bf.clear2 = and i32 %9, 1
   %conv3 = uitofp i32 %bf.clear2 to x86_fp80
@@ -39,12 +39,12 @@ entry:
   %10 = bitcast %0* %K to i32*
   %11 = and i32 %bf.value, 1
   %12 = shl i32 %11, 7
-  %13 = load i32* %10, align 4
+  %13 = load i32, i32* %10, align 4
   %14 = and i32 %13, -129
   %15 = or i32 %14, %12
   store i32 %15, i32* %10, align 4
-  %call = call i32 (...)* @iequals(i32 1841, i32 %bf.value, i32 0)
-  %16 = load i32* %retval
+  %call = call i32 (...) @iequals(i32 1841, i32 %bf.value, i32 0)
+  %16 = load i32, i32* %retval
   ret i32 %16
 }
 
diff --git a/test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll b/test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll
index e48edf7e30b4..9fe6a774fbb7 100644
--- a/test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll
+++ b/test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll
@@ -12,10 +12,10 @@ declare fastcc i8* @save_string(i8* %d, i8* nocapture %s) nounwind
 
 define i32 @cvtchar(i8* nocapture %sp) nounwind {
   %temp.i = alloca [2 x i8], align 1
-  %tmp1 = load i8* %sp, align 1
+  %tmp1 = load i8, i8* %sp, align 1
   %div = udiv i8 %tmp1, 10
   %rem = urem i8 %div, 10
-  %arrayidx.i = getelementptr inbounds [2 x i8]* %temp.i, i32 0, i32 0
+  %arrayidx.i = getelementptr inbounds [2 x i8], [2 x i8]* %temp.i, i32 0, i32 0
   store i8 %rem, i8* %arrayidx.i, align 1
   %call.i = call fastcc i8* @save_string(i8* %sp, i8* %arrayidx.i) nounwind
   ret i32 undef
diff --git a/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll b/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll
index be10ad5cc206..ed64ea93b393 100644
--- a/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll
+++ b/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll
@@ -17,7 +17,7 @@ declare hidden fastcc void @_ZN3JSCL23returnToThrowTrampolineEPNS_12JSGlobalData
 ; CHECK: je
 define i32 @cti_op_eq(i8** nocapture %args) nounwind ssp {
 entry:
-  %0 = load i8** null, align 8
+  %0 = load i8*, i8** null, align 8
   %tmp13 = bitcast i8* %0 to %"class.JSC::CodeLocationCall"*
   %tobool.i.i.i = icmp ugt i8* undef, inttoptr (i64 281474976710655 to i8*)
   %or.cond.i = and i1 %tobool.i.i.i, undef
@@ -34,7 +34,7 @@ if.end.i:                                         ; preds = %entry
   br i1 undef, label %land.rhs.i121.i, label %_ZNK3JSC7JSValue8isStringEv.exit122.i
 
 land.rhs.i121.i:                                  ; preds = %if.end.i
-  %tmp.i.i117.i = load %"class.JSC::Structure"** undef, align 8
+  %tmp.i.i117.i = load %"class.JSC::Structure"*, %"class.JSC::Structure"** undef, align 8
   br label %_ZNK3JSC7JSValue8isStringEv.exit122.i
 
 _ZNK3JSC7JSValue8isStringEv.exit122.i:            ; preds = %land.rhs.i121.i, %if.end.i
@@ -48,12 +48,12 @@ if.then.i92.i:                                    ; preds = %_ZNK3JSC7JSValue8is
 
 _ZN3JSC7JSValue19equalSlowCaseInlineEPNS_9ExecStateES0_S0_.exit: ; preds = %_ZNK3JSC7JSValue8isStringEv.exit122.i, %if.then.i.i.i, %if.then.i
 
-  %1 = load i8** undef, align 8
+  %1 = load i8*, i8** undef, align 8
   br i1 undef, label %do.end39, label %do.body27
 
 do.body27:                                        ; preds = %_ZN3JSC7JSValue19equalSlowCaseInlineEPNS_9ExecStateES0_S0_.exit
   %tmp30 = bitcast i8* %1 to %"class.JSC::JSGlobalData"*
-  %2 = getelementptr inbounds i8** %args, i64 -1
+  %2 = getelementptr inbounds i8*, i8** %args, i64 -1
   %3 = bitcast i8** %2 to %"class.JSC::FunctionPtr"*
   tail call fastcc void @_ZN3JSCL23returnToThrowTrampolineEPNS_12JSGlobalDataENS_16ReturnAddressPtrERS2_(%"class.JSC::JSGlobalData"* %tmp30, i8* undef, %"class.JSC::FunctionPtr"* %3)
   unreachable
diff --git a/test/CodeGen/X86/2011-05-09-loaduse.ll b/test/CodeGen/X86/2011-05-09-loaduse.ll
index c772e4c7f4e4..a94a9812431e 100644
--- a/test/CodeGen/X86/2011-05-09-loaduse.ll
+++ b/test/CodeGen/X86/2011-05-09-loaduse.ll
@@ -5,7 +5,7 @@
 ;CHECK: ret
 define float @test(<4 x float>* %A) nounwind {
 entry:
-  %T = load <4 x float>* %A
+  %T = load <4 x float>, <4 x float>* %A
   %R = extractelement <4 x float> %T, i32 3
   store <4 x float><float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>* %A
   ret float %R
diff --git a/test/CodeGen/X86/2011-05-26-UnreachableBlockElim.ll b/test/CodeGen/X86/2011-05-26-UnreachableBlockElim.ll
index 91cd208f0167..68c0af4f752a 100644
--- a/test/CodeGen/X86/2011-05-26-UnreachableBlockElim.ll
+++ b/test/CodeGen/X86/2011-05-26-UnreachableBlockElim.ll
@@ -41,8 +41,8 @@ cond.false156.i:                                  ; preds = %for.end.i, %land.en
 
 cond.end166.i:                                    ; preds = %cond.false156.i, %cond.true138.i
   %idxprom1113.i = phi i64 [ %idxprom1114.i, %cond.false156.i ], [ undef, %cond.true138.i ]
-  %tmp235.i = load %struct.state** getelementptr inbounds (%struct.dfa* @aux_temp, i64 0, i32 2), align 8
-  %att.i = getelementptr inbounds %struct.state* %tmp235.i, i64 %idxprom1113.i, i32 0
+  %tmp235.i = load %struct.state*, %struct.state** getelementptr inbounds (%struct.dfa, %struct.dfa* @aux_temp, i64 0, i32 2), align 8
+  %att.i = getelementptr inbounds %struct.state, %struct.state* %tmp235.i, i64 %idxprom1113.i, i32 0
   store i32 0, i32* %att.i, align 4
   ret void
 }
diff --git a/test/CodeGen/X86/2011-05-27-CrossClassCoalescing.ll b/test/CodeGen/X86/2011-05-27-CrossClassCoalescing.ll
index c595bba3266c..414bd243ebce 100644
--- a/test/CodeGen/X86/2011-05-27-CrossClassCoalescing.ll
+++ b/test/CodeGen/X86/2011-05-27-CrossClassCoalescing.ll
@@ -20,15 +20,15 @@ land.lhs.true:                                    ; preds = %do.body.i
 
 for.body.i:                                       ; preds = %for.inc.i, %if.then
   %tmp3524.i = phi i32 [ 0, %land.lhs.true ], [ %tmp351.i, %for.inc.i ]
-  %tmp6.i12 = load i32* undef, align 4
+  %tmp6.i12 = load i32, i32* undef, align 4
   br i1 undef, label %for.inc.i, label %if.then.i17
 
 if.then.i17:                                      ; preds = %for.body.i
   %shr.i14 = lshr i32 %tmp6.i12, 8
   %and14.i = and i32 %shr.i14, 255
   %idxprom15.i = zext i32 %and14.i to i64
-  %arrayidx16.i = getelementptr inbounds [256 x i32]* @bit_count, i64 0, i64 %idxprom15.i
-  %tmp17.i15 = load i32* %arrayidx16.i, align 4
+  %arrayidx16.i = getelementptr inbounds [256 x i32], [256 x i32]* @bit_count, i64 0, i64 %idxprom15.i
+  %tmp17.i15 = load i32, i32* %arrayidx16.i, align 4
   %add.i = add i32 0, %tmp3524.i
   %add24.i = add i32 %add.i, %tmp17.i15
   %add31.i = add i32 %add24.i, 0
diff --git a/test/CodeGen/X86/2011-06-01-fildll.ll b/test/CodeGen/X86/2011-06-01-fildll.ll
index 3a0b05fce3ab..30c743441c36 100644
--- a/test/CodeGen/X86/2011-06-01-fildll.ll
+++ b/test/CodeGen/X86/2011-06-01-fildll.ll
@@ -7,7 +7,7 @@ define float @f(i64* nocapture %x) nounwind readonly ssp {
 entry:
 ; CHECK: movl
 ; CHECK-NOT: movl
-  %tmp1 = load i64* %x, align 4
+  %tmp1 = load i64, i64* %x, align 4
 ; CHECK: fildll
   %conv = sitofp i64 %tmp1 to float
   %add = fadd float %conv, 1.000000e+00
diff --git a/test/CodeGen/X86/2011-06-03-x87chain.ll b/test/CodeGen/X86/2011-06-03-x87chain.ll
index 5275b6889bff..c78e8e38a567 100644
--- a/test/CodeGen/X86/2011-06-03-x87chain.ll
+++ b/test/CodeGen/X86/2011-06-03-x87chain.ll
@@ -2,7 +2,7 @@
 
 define float @chainfail1(i64* nocapture %a, i64* nocapture %b, i32 %x, i32 %y, float* nocapture %f) nounwind uwtable noinline ssp {
 entry:
-  %tmp1 = load i64* %a, align 8
+  %tmp1 = load i64, i64* %a, align 8
 ; Insure x87 ops are properly chained, order preserved.
 ; CHECK: fildll
   %conv = sitofp i64 %tmp1 to float
@@ -22,8 +22,8 @@ entry:
   %mul = mul nsw i32 %y, %x
   %sub = add nsw i32 %mul, -1
   %idxprom = sext i32 %sub to i64
-  %arrayidx = getelementptr inbounds i64* %a, i64 %idxprom
-  %tmp4 = load i64* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds i64, i64* %a, i64 %idxprom
+  %tmp4 = load i64, i64* %arrayidx, align 8
 ; CHECK: fildll
   %conv = sitofp i64 %tmp4 to float
   store float %conv, float* %f, align 4
@@ -35,7 +35,7 @@ entry:
   br i1 undef, label %while.end, label %while.body
 
 while.body:                                       ; preds = %while.body, %entry
-  %x.1.copyload = load i24* undef, align 1
+  %x.1.copyload = load i24, i24* undef, align 1
   %conv = sitofp i24 %x.1.copyload to float
   %div = fmul float %conv, 0x3E80000000000000
   store float %div, float* undef, align 4
diff --git a/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll b/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll
index 6f43b94b264a..1285d20b8522 100644
--- a/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll
+++ b/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll
@@ -28,21 +28,21 @@ bb:
   br label %bb8
 
 bb8:                                              ; preds = %bb23, %bb
-  %tmp15 = getelementptr inbounds %3* %tmp7, i32 0, i32 4
+  %tmp15 = getelementptr inbounds %3, %3* %tmp7, i32 0, i32 4
   store i8* bitcast (%0* @0 to i8*), i8** %tmp15
   %tmp16 = bitcast %3* %tmp7 to void ()*
   store void ()* %tmp16, void ()** %tmp6, align 8
-  %tmp17 = load void ()** %tmp6, align 8
+  %tmp17 = load void ()*, void ()** %tmp6, align 8
   %tmp18 = bitcast void ()* %tmp17 to %6*
-  %tmp19 = getelementptr inbounds %6* %tmp18, i32 0, i32 3
+  %tmp19 = getelementptr inbounds %6, %6* %tmp18, i32 0, i32 3
   %tmp20 = bitcast %6* %tmp18 to i8*
-  %tmp21 = load i8** %tmp19
+  %tmp21 = load i8*, i8** %tmp19
   %tmp22 = bitcast i8* %tmp21 to void (i8*)*
   call void %tmp22(i8* %tmp20)
   br label %bb23
 
 bb23:                                             ; preds = %bb8
-  %tmp24 = load i64* %tmp5, align 8
+  %tmp24 = load i64, i64* %tmp5, align 8
   %tmp25 = add i64 %tmp24, 1
   store i64 %tmp25, i64* %tmp5, align 8
   %tmp26 = icmp ult i64 %tmp25, 10
diff --git a/test/CodeGen/X86/2011-06-19-QuicksortCoalescerBug.ll b/test/CodeGen/X86/2011-06-19-QuicksortCoalescerBug.ll
index 08178a302f23..489eb619b51e 100644
--- a/test/CodeGen/X86/2011-06-19-QuicksortCoalescerBug.ll
+++ b/test/CodeGen/X86/2011-06-19-QuicksortCoalescerBug.ll
@@ -10,7 +10,7 @@ tailrecurse:                                      ; preds = %do.cond, %entry
   %l.tr = phi i32 [ %l, %entry ], [ %i.1, %do.cond ]
   %r.tr = phi i32 [ %r, %entry ], [ %l.tr, %do.cond ]
   %idxprom12 = sext i32 %r.tr to i64
-  %arrayidx14 = getelementptr inbounds i32* %a, i64 %idxprom12
+  %arrayidx14 = getelementptr inbounds i32, i32* %a, i64 %idxprom12
   br label %do.body
 
 do.body:                                          ; preds = %do.cond, %tailrecurse
diff --git a/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll b/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll
index aea53b3b9855..f38ebf1da85a 100644
--- a/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll
+++ b/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll
@@ -11,8 +11,8 @@ entry:
   call void @bar([39 x i8]* %stack_main)
   %tmp6 = add i64 %a, -2147483647
   %.sum = add i64 %tmp6, %b
-  %tmp8 = getelementptr inbounds [39 x i8]* %stack_main, i64 0, i64 %.sum
-  %tmp9 = load i8* %tmp8, align 1
+  %tmp8 = getelementptr inbounds [39 x i8], [39 x i8]* %stack_main, i64 0, i64 %.sum
+  %tmp9 = load i8, i8* %tmp8, align 1
   %tmp10 = sext i8 %tmp9 to i32
   ret i32 %tmp10
 }
diff --git a/test/CodeGen/X86/2011-09-14-valcoalesce.ll b/test/CodeGen/X86/2011-09-14-valcoalesce.ll
index 4e84e84c1aa9..b8e5100c53bb 100644
--- a/test/CodeGen/X86/2011-09-14-valcoalesce.ll
+++ b/test/CodeGen/X86/2011-09-14-valcoalesce.ll
@@ -121,7 +121,7 @@ while.body.i188:                                  ; preds = %for.end173.i, %if.e
 while.body85.i:                                   ; preds = %while.body85.i, %while.body.i188
   %aFreq.0518.i = phi i32 [ %add93.i, %while.body85.i ], [ 0, %while.body.i188 ]
   %inc87.i = add nsw i32 0, 1
-  %tmp91.i = load i32* undef, align 4
+  %tmp91.i = load i32, i32* undef, align 4
   %add93.i = add nsw i32 %tmp91.i, %aFreq.0518.i
   %or.cond514.i = and i1 undef, false
   br i1 %or.cond514.i, label %while.body85.i, label %while.end.i
@@ -144,7 +144,7 @@ if.end117.i:                                      ; preds = %if.then108.i, %land
   br i1 undef, label %if.then122.i, label %for.cond138.preheader.i
 
 if.then122.i:                                     ; preds = %if.end117.i
-  call void (...)* @fprintf(i32 undef, i32 %gs.0526.i, i32 %ge.1.i, i32 %aFreq.1.i, double undef) nounwind
+  call void (...) @fprintf(i32 undef, i32 %gs.0526.i, i32 %ge.1.i, i32 %aFreq.1.i, double undef) nounwind
   br label %for.cond138.preheader.i
 
 for.cond138.preheader.i:                          ; preds = %if.then122.i, %if.end117.i
diff --git a/test/CodeGen/X86/2011-09-21-setcc-bug.ll b/test/CodeGen/X86/2011-09-21-setcc-bug.ll
index a67c3f338862..e61715a4813d 100644
--- a/test/CodeGen/X86/2011-09-21-setcc-bug.ll
+++ b/test/CodeGen/X86/2011-09-21-setcc-bug.ll
@@ -3,10 +3,10 @@
 ; Make sure we are not crashing on this code.
 
 define void @load_4_i8(<4 x i8>* %k, <4 x i8>* %y, <4 x double>* %A1, <4 x double>* %A0)  {
-   %A = load <4 x i8>* %k
-   %B = load <4 x i8>* %y
-   %C = load <4 x double>* %A0
-   %D= load <4 x double>* %A1
+   %A = load <4 x i8>, <4 x i8>* %k
+   %B = load <4 x i8>, <4 x i8>* %y
+   %C = load <4 x double>, <4 x double>* %A0
+   %D= load <4 x double>, <4 x double>* %A1
    %M = icmp uge <4 x i8> %A, %B
    %T = select <4 x i1> %M, <4 x double> %C, <4 x double> %D
    store <4 x double> %T, <4 x double>* undef
@@ -15,10 +15,10 @@ define void @load_4_i8(<4 x i8>* %k, <4 x i8>* %y, <4 x double>* %A1, <4 x doubl
 
 
 define void @load_256_i8(<256 x i8>* %k, <256 x i8>* %y, <256 x double>* %A1, <256 x double>* %A0)  {
-   %A = load <256 x i8>* %k
-   %B = load <256 x i8>* %y
-   %C = load <256 x double>* %A0
-   %D= load <256 x double>* %A1
+   %A = load <256 x i8>, <256 x i8>* %k
+   %B = load <256 x i8>, <256 x i8>* %y
+   %C = load <256 x double>, <256 x double>* %A0
+   %D= load <256 x double>, <256 x double>* %A1
    %M = icmp uge <256 x i8> %A, %B
    %T = select <256 x i1> %M, <256 x double> %C, <256 x double> %D
    store <256 x double> %T, <256 x double>* undef
diff --git a/test/CodeGen/X86/2011-10-11-srl.ll b/test/CodeGen/X86/2011-10-11-srl.ll
index 434f88c14b6a..ff58afca0417 100644
--- a/test/CodeGen/X86/2011-10-11-srl.ll
+++ b/test/CodeGen/X86/2011-10-11-srl.ll
@@ -3,7 +3,7 @@
 target triple = "x86_64-unknown-linux-gnu"
 
 define void @m387(<2 x i8>* %p, <2 x i16>* %q) {
-  %t = load <2 x i8>* %p
+  %t = load <2 x i8>, <2 x i8>* %p
   %r = sext <2 x i8> %t to <2 x i16>
   store <2 x i16> %r, <2 x i16>* %q
   ret void
diff --git a/test/CodeGen/X86/2011-10-12-MachineCSE.ll b/test/CodeGen/X86/2011-10-12-MachineCSE.ll
index 72e672ac4f1f..341a14b6d2a0 100644
--- a/test/CodeGen/X86/2011-10-12-MachineCSE.ll
+++ b/test/CodeGen/X86/2011-10-12-MachineCSE.ll
@@ -16,35 +16,35 @@ target triple = "x86_64-apple-macosx10.7.2"
 define %struct.rtx_def* @gen_add3_insn(%struct.rtx_def* %r0, %struct.rtx_def* %r1, %struct.rtx_def* %c) nounwind uwtable ssp {
 entry:
   %0 = bitcast %struct.rtx_def* %r0 to i32*
-  %1 = load i32* %0, align 8
+  %1 = load i32, i32* %0, align 8
   %2 = lshr i32 %1, 16
   %bf.clear = and i32 %2, 255
   %idxprom = sext i32 %bf.clear to i64
-  %3 = load %struct.optab** getelementptr inbounds ([49 x %struct.optab*]* @optab_table, i32 0, i64 0), align 8
-  %handlers = getelementptr inbounds %struct.optab* %3, i32 0, i32 1
-  %arrayidx = getelementptr inbounds [59 x %struct.anon.3]* %handlers, i32 0, i64 %idxprom
-  %insn_code = getelementptr inbounds %struct.anon.3* %arrayidx, i32 0, i32 0
-  %4 = load i32* %insn_code, align 4
+  %3 = load %struct.optab*, %struct.optab** getelementptr inbounds ([49 x %struct.optab*], [49 x %struct.optab*]* @optab_table, i32 0, i64 0), align 8
+  %handlers = getelementptr inbounds %struct.optab, %struct.optab* %3, i32 0, i32 1
+  %arrayidx = getelementptr inbounds [59 x %struct.anon.3], [59 x %struct.anon.3]* %handlers, i32 0, i64 %idxprom
+  %insn_code = getelementptr inbounds %struct.anon.3, %struct.anon.3* %arrayidx, i32 0, i32 0
+  %4 = load i32, i32* %insn_code, align 4
   %cmp = icmp eq i32 %4, 1317
   br i1 %cmp, label %if.then, label %lor.lhs.false
 
 lor.lhs.false:                                    ; preds = %entry
   %idxprom1 = sext i32 %4 to i64
-  %arrayidx2 = getelementptr inbounds [0 x %struct.insn_data]* @insn_data, i32 0, i64 %idxprom1
-  %operand = getelementptr inbounds %struct.insn_data* %arrayidx2, i32 0, i32 3
-  %5 = load %struct.insn_operand_data** %operand, align 8
-  %arrayidx3 = getelementptr inbounds %struct.insn_operand_data* %5, i64 0
-  %predicate = getelementptr inbounds %struct.insn_operand_data* %arrayidx3, i32 0, i32 0
-  %6 = load i32 (%struct.rtx_def*, i32)** %predicate, align 8
+  %arrayidx2 = getelementptr inbounds [0 x %struct.insn_data], [0 x %struct.insn_data]* @insn_data, i32 0, i64 %idxprom1
+  %operand = getelementptr inbounds %struct.insn_data, %struct.insn_data* %arrayidx2, i32 0, i32 3
+  %5 = load %struct.insn_operand_data*, %struct.insn_operand_data** %operand, align 8
+  %arrayidx3 = getelementptr inbounds %struct.insn_operand_data, %struct.insn_operand_data* %5, i64 0
+  %predicate = getelementptr inbounds %struct.insn_operand_data, %struct.insn_operand_data* %arrayidx3, i32 0, i32 0
+  %6 = load i32 (%struct.rtx_def*, i32)*, i32 (%struct.rtx_def*, i32)** %predicate, align 8
   %idxprom4 = sext i32 %4 to i64
-  %arrayidx5 = getelementptr inbounds [0 x %struct.insn_data]* @insn_data, i32 0, i64 %idxprom4
-  %operand6 = getelementptr inbounds %struct.insn_data* %arrayidx5, i32 0, i32 3
-  %7 = load %struct.insn_operand_data** %operand6, align 8
-  %arrayidx7 = getelementptr inbounds %struct.insn_operand_data* %7, i64 0
+  %arrayidx5 = getelementptr inbounds [0 x %struct.insn_data], [0 x %struct.insn_data]* @insn_data, i32 0, i64 %idxprom4
+  %operand6 = getelementptr inbounds %struct.insn_data, %struct.insn_data* %arrayidx5, i32 0, i32 3
+  %7 = load %struct.insn_operand_data*, %struct.insn_operand_data** %operand6, align 8
+  %arrayidx7 = getelementptr inbounds %struct.insn_operand_data, %struct.insn_operand_data* %7, i64 0
   %8 = bitcast %struct.insn_operand_data* %arrayidx7 to i8*
-  %bf.field.offs = getelementptr i8* %8, i32 16
+  %bf.field.offs = getelementptr i8, i8* %8, i32 16
   %9 = bitcast i8* %bf.field.offs to i32*
-  %10 = load i32* %9, align 8
+  %10 = load i32, i32* %9, align 8
   %bf.clear8 = and i32 %10, 65535
   %call = tail call i32 %6(%struct.rtx_def* %r0, i32 %bf.clear8)
   %tobool = icmp ne i32 %call, 0
@@ -52,21 +52,21 @@ lor.lhs.false:                                    ; preds = %entry
 
 lor.lhs.false9:                                   ; preds = %lor.lhs.false
   %idxprom10 = sext i32 %4 to i64
-  %arrayidx11 = getelementptr inbounds [0 x %struct.insn_data]* @insn_data, i32 0, i64 %idxprom10
-  %operand12 = getelementptr inbounds %struct.insn_data* %arrayidx11, i32 0, i32 3
-  %11 = load %struct.insn_operand_data** %operand12, align 8
-  %arrayidx13 = getelementptr inbounds %struct.insn_operand_data* %11, i64 1
-  %predicate14 = getelementptr inbounds %struct.insn_operand_data* %arrayidx13, i32 0, i32 0
-  %12 = load i32 (%struct.rtx_def*, i32)** %predicate14, align 8
+  %arrayidx11 = getelementptr inbounds [0 x %struct.insn_data], [0 x %struct.insn_data]* @insn_data, i32 0, i64 %idxprom10
+  %operand12 = getelementptr inbounds %struct.insn_data, %struct.insn_data* %arrayidx11, i32 0, i32 3
+  %11 = load %struct.insn_operand_data*, %struct.insn_operand_data** %operand12, align 8
+  %arrayidx13 = getelementptr inbounds %struct.insn_operand_data, %struct.insn_operand_data* %11, i64 1
+  %predicate14 = getelementptr inbounds %struct.insn_operand_data, %struct.insn_operand_data* %arrayidx13, i32 0, i32 0
+  %12 = load i32 (%struct.rtx_def*, i32)*, i32 (%struct.rtx_def*, i32)** %predicate14, align 8
   %idxprom15 = sext i32 %4 to i64
-  %arrayidx16 = getelementptr inbounds [0 x %struct.insn_data]* @insn_data, i32 0, i64 %idxprom15
-  %operand17 = getelementptr inbounds %struct.insn_data* %arrayidx16, i32 0, i32 3
-  %13 = load %struct.insn_operand_data** %operand17, align 8
-  %arrayidx18 = getelementptr inbounds %struct.insn_operand_data* %13, i64 1
+  %arrayidx16 = getelementptr inbounds [0 x %struct.insn_data], [0 x %struct.insn_data]* @insn_data, i32 0, i64 %idxprom15
+  %operand17 = getelementptr inbounds %struct.insn_data, %struct.insn_data* %arrayidx16, i32 0, i32 3
+  %13 = load %struct.insn_operand_data*, %struct.insn_operand_data** %operand17, align 8
+  %arrayidx18 = getelementptr inbounds %struct.insn_operand_data, %struct.insn_operand_data* %13, i64 1
   %14 = bitcast %struct.insn_operand_data* %arrayidx18 to i8*
-  %bf.field.offs19 = getelementptr i8* %14, i32 16
+  %bf.field.offs19 = getelementptr i8, i8* %14, i32 16
   %15 = bitcast i8* %bf.field.offs19 to i32*
-  %16 = load i32* %15, align 8
+  %16 = load i32, i32* %15, align 8
   %bf.clear20 = and i32 %16, 65535
   %call21 = tail call i32 %12(%struct.rtx_def* %r1, i32 %bf.clear20)
   %tobool22 = icmp ne i32 %call21, 0
@@ -74,21 +74,21 @@ lor.lhs.false9:                                   ; preds = %lor.lhs.false
 
 lor.lhs.false23:                                  ; preds = %lor.lhs.false9
   %idxprom24 = sext i32 %4 to i64
-  %arrayidx25 = getelementptr inbounds [0 x %struct.insn_data]* @insn_data, i32 0, i64 %idxprom24
-  %operand26 = getelementptr inbounds %struct.insn_data* %arrayidx25, i32 0, i32 3
-  %17 = load %struct.insn_operand_data** %operand26, align 8
-  %arrayidx27 = getelementptr inbounds %struct.insn_operand_data* %17, i64 2
-  %predicate28 = getelementptr inbounds %struct.insn_operand_data* %arrayidx27, i32 0, i32 0
-  %18 = load i32 (%struct.rtx_def*, i32)** %predicate28, align 8
+  %arrayidx25 = getelementptr inbounds [0 x %struct.insn_data], [0 x %struct.insn_data]* @insn_data, i32 0, i64 %idxprom24
+  %operand26 = getelementptr inbounds %struct.insn_data, %struct.insn_data* %arrayidx25, i32 0, i32 3
+  %17 = load %struct.insn_operand_data*, %struct.insn_operand_data** %operand26, align 8
+  %arrayidx27 = getelementptr inbounds %struct.insn_operand_data, %struct.insn_operand_data* %17, i64 2
+  %predicate28 = getelementptr inbounds %struct.insn_operand_data, %struct.insn_operand_data* %arrayidx27, i32 0, i32 0
+  %18 = load i32 (%struct.rtx_def*, i32)*, i32 (%struct.rtx_def*, i32)** %predicate28, align 8
   %idxprom29 = sext i32 %4 to i64
-  %arrayidx30 = getelementptr inbounds [0 x %struct.insn_data]* @insn_data, i32 0, i64 %idxprom29
-  %operand31 = getelementptr inbounds %struct.insn_data* %arrayidx30, i32 0, i32 3
-  %19 = load %struct.insn_operand_data** %operand31, align 8
-  %arrayidx32 = getelementptr inbounds %struct.insn_operand_data* %19, i64 2
+  %arrayidx30 = getelementptr inbounds [0 x %struct.insn_data], [0 x %struct.insn_data]* @insn_data, i32 0, i64 %idxprom29
+  %operand31 = getelementptr inbounds %struct.insn_data, %struct.insn_data* %arrayidx30, i32 0, i32 3
+  %19 = load %struct.insn_operand_data*, %struct.insn_operand_data** %operand31, align 8
+  %arrayidx32 = getelementptr inbounds %struct.insn_operand_data, %struct.insn_operand_data* %19, i64 2
   %20 = bitcast %struct.insn_operand_data* %arrayidx32 to i8*
-  %bf.field.offs33 = getelementptr i8* %20, i32 16
+  %bf.field.offs33 = getelementptr i8, i8* %20, i32 16
   %21 = bitcast i8* %bf.field.offs33 to i32*
-  %22 = load i32* %21, align 8
+  %22 = load i32, i32* %21, align 8
   %bf.clear34 = and i32 %22, 65535
   %call35 = tail call i32 %18(%struct.rtx_def* %c, i32 %bf.clear34)
   %tobool36 = icmp ne i32 %call35, 0
@@ -99,10 +99,10 @@ if.then:                                          ; preds = %lor.lhs.false23, %l
 
 if.end:                                           ; preds = %lor.lhs.false23
   %idxprom37 = sext i32 %4 to i64
-  %arrayidx38 = getelementptr inbounds [0 x %struct.insn_data]* @insn_data, i32 0, i64 %idxprom37
-  %genfun = getelementptr inbounds %struct.insn_data* %arrayidx38, i32 0, i32 2
-  %23 = load %struct.rtx_def* (%struct.rtx_def*, ...)** %genfun, align 8
-  %call39 = tail call %struct.rtx_def* (%struct.rtx_def*, ...)* %23(%struct.rtx_def* %r0, %struct.rtx_def* %r1, %struct.rtx_def* %c)
+  %arrayidx38 = getelementptr inbounds [0 x %struct.insn_data], [0 x %struct.insn_data]* @insn_data, i32 0, i64 %idxprom37
+  %genfun = getelementptr inbounds %struct.insn_data, %struct.insn_data* %arrayidx38, i32 0, i32 2
+  %23 = load %struct.rtx_def* (%struct.rtx_def*, ...)*, %struct.rtx_def* (%struct.rtx_def*, ...)** %genfun, align 8
+  %call39 = tail call %struct.rtx_def* (%struct.rtx_def*, ...) %23(%struct.rtx_def* %r0, %struct.rtx_def* %r1, %struct.rtx_def* %c)
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
diff --git a/test/CodeGen/X86/2011-10-18-FastISel-VectorParams.ll b/test/CodeGen/X86/2011-10-18-FastISel-VectorParams.ll
index e7d1e194d9cd..c9dc050d0b4e 100644
--- a/test/CodeGen/X86/2011-10-18-FastISel-VectorParams.ll
+++ b/test/CodeGen/X86/2011-10-18-FastISel-VectorParams.ll
@@ -15,11 +15,11 @@ entry:
   store <4 x float> <float 0x4008CCCCC0000000, float 0x40099999A0000000, float 0x400A666660000000, float 0x400B333340000000>, <4 x float>* %p3, align 16
   store <4 x float> <float 0x4010666660000000, float 0x4010CCCCC0000000, float 0x4011333340000000, float 0x40119999A0000000>, <4 x float>* %p4, align 16
   store <4 x float> <float 0x4014666660000000, float 0x4014CCCCC0000000, float 0x4015333340000000, float 0x40159999A0000000>, <4 x float>* %p5, align 16
-  %0 = load <4 x float>* %p1, align 16
-  %1 = load <4 x float>* %p2, align 16
-  %2 = load <4 x float>* %p3, align 16
-  %3 = load <4 x float>* %p4, align 16
-  %4 = load <4 x float>* %p5, align 16
+  %0 = load <4 x float>, <4 x float>* %p1, align 16
+  %1 = load <4 x float>, <4 x float>* %p2, align 16
+  %2 = load <4 x float>, <4 x float>* %p3, align 16
+  %3 = load <4 x float>, <4 x float>* %p4, align 16
+  %4 = load <4 x float>, <4 x float>* %p5, align 16
 ; CHECK:      movups {{%xmm[0-7]}}, (%esp)
 ; CHECK-NEXT: calll _dovectortest 
   call void @dovectortest(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3, <4 x float> %4)
diff --git a/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll b/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
index 07a6910c65e0..bf1f029847ea 100644
--- a/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
+++ b/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
@@ -18,10 +18,10 @@ define i32 @main() nounwind uwtable {
 entry:
 ; CHECK: pmovsxbq  i(%rip), %
 ; CHECK: pmovsxbq  j(%rip), %
-  %0 = load <2 x i8>* @i, align 8
-  %1 = load <2 x i8>* @j, align 8
+  %0 = load <2 x i8>, <2 x i8>* @i, align 8
+  %1 = load <2 x i8>, <2 x i8>* @j, align 8
   %div = sdiv <2 x i8> %1, %0
-  store <2 x i8> %div, <2 x i8>* getelementptr inbounds (%union.anon* @res, i32 0, i32 0), align 8
+  store <2 x i8> %div, <2 x i8>* getelementptr inbounds (%union.anon, %union.anon* @res, i32 0, i32 0), align 8
   ret i32 0
 ; CHECK: ret
 }
diff --git a/test/CodeGen/X86/2011-10-19-widen_vselect.ll b/test/CodeGen/X86/2011-10-19-widen_vselect.ll
index 222068dc579f..07dff9539cd0 100644
--- a/test/CodeGen/X86/2011-10-19-widen_vselect.ll
+++ b/test/CodeGen/X86/2011-10-19-widen_vselect.ll
@@ -26,7 +26,7 @@ entry:
 }
 
 ; CHECK-LABEL: zero_test
-; CHECK: xorps	%xmm0, %xmm0
+; CHECK: xorps %xmm0, %xmm0
 ; CHECK: ret
 
 define void @zero_test() {
@@ -49,7 +49,7 @@ define void @full_test() {
    br label %B1
 
  B1:                                               ; preds = %entry
-   %0 = load <2 x float>* %Cy119
+   %0 = load <2 x float>, <2 x float>* %Cy119
    %1 = fptosi <2 x float> %0 to <2 x i32>
    %2 = sitofp <2 x i32> %1 to <2 x float>
    %3 = fcmp ogt <2 x float> %0, zeroinitializer
@@ -58,7 +58,7 @@ define void @full_test() {
    %6 = fcmp oeq <2 x float> %2, %0
    %7 = select <2 x i1> %6, <2 x float> %0, <2 x float> %5
    store <2 x float> %7, <2 x float>* %Cy118
-   %8 = load <2 x float>* %Cy118
+   %8 = load <2 x float>, <2 x float>* %Cy118
    store <2 x float> %8, <2 x float>* %Cy11a
    ret void
 }
diff --git a/test/CodeGen/X86/2011-10-27-tstore.ll b/test/CodeGen/X86/2011-10-27-tstore.ll
index 6dea92b63071..290b4d0cb00b 100644
--- a/test/CodeGen/X86/2011-10-27-tstore.ll
+++ b/test/CodeGen/X86/2011-10-27-tstore.ll
@@ -8,7 +8,7 @@ target triple = "x86_64-unknown-linux-gnu"
 ;CHECK: ret
 define void @ltstore(<4 x i32>* %pA, <2 x i32>* %pB) {
 entry:
-  %in = load <4 x i32>* %pA
+  %in = load <4 x i32>, <4 x i32>* %pA
   %j = shufflevector <4 x i32> %in, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
   store <2 x i32> %j, <2 x i32>* %pB
   ret void
diff --git a/test/CodeGen/X86/2011-11-22-AVX2-Domains.ll b/test/CodeGen/X86/2011-11-22-AVX2-Domains.ll
index 8174109378de..dffd6d1cee51 100644
--- a/test/CodeGen/X86/2011-11-22-AVX2-Domains.ll
+++ b/test/CodeGen/X86/2011-11-22-AVX2-Domains.ll
@@ -18,9 +18,9 @@ if_else:                                          ; preds = %allocas
   br i1 undef, label %for_loop156.lr.ph, label %if_exit
 
 for_loop156.lr.ph:                                ; preds = %if_else
-  %val_6.i21244 = load i16* undef, align 2
+  %val_6.i21244 = load i16, i16* undef, align 2
   %0 = insertelement <8 x i16> undef, i16 %val_6.i21244, i32 6
-  %val_7.i21248 = load i16* undef, align 2
+  %val_7.i21248 = load i16, i16* undef, align 2
   %1 = insertelement <8 x i16> %0, i16 %val_7.i21248, i32 7
   %uint2uint32.i20206 = zext <8 x i16> %1 to <8 x i32>
   %bitop5.i20208 = and <8 x i32> %uint2uint32.i20206, <i32 31744, i32 31744, i32 31744, i32 31744, i32 31744, i32 31744, i32 31744, i32 31744>
@@ -39,26 +39,26 @@ for_loop156.lr.ph:                                ; preds = %if_else
   %binop407 = fadd <8 x float> %binop406, <float -2.000000e+00, float -2.000000e+00, float -2.000000e+00, float -2.000000e+00, float -2.000000e+00, float -2.000000e+00, float -2.000000e+00, float -2.000000e+00>
   %binop408 = fmul <8 x float> zeroinitializer, %binop407
   %binop411 = fsub <8 x float> <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00>, undef
-  %val_4.i21290 = load i16* undef, align 2
+  %val_4.i21290 = load i16, i16* undef, align 2
   %2 = insertelement <8 x i16> undef, i16 %val_4.i21290, i32 4
-  %val_5.i21294 = load i16* undef, align 2
+  %val_5.i21294 = load i16, i16* undef, align 2
   %3 = insertelement <8 x i16> %2, i16 %val_5.i21294, i32 5
-  %val_6.i21298 = load i16* undef, align 2
+  %val_6.i21298 = load i16, i16* undef, align 2
   %4 = insertelement <8 x i16> %3, i16 %val_6.i21298, i32 6
   %ptr_7.i21301 = inttoptr i64 undef to i16*
-  %val_7.i21302 = load i16* %ptr_7.i21301, align 2
+  %val_7.i21302 = load i16, i16* %ptr_7.i21301, align 2
   %5 = insertelement <8 x i16> %4, i16 %val_7.i21302, i32 7
   %uint2uint32.i20218 = zext <8 x i16> %5 to <8 x i32>
-  %structelement561 = load i8** undef, align 8
+  %structelement561 = load i8*, i8** undef, align 8
   %ptr2int563 = ptrtoint i8* %structelement561 to i64
   %smear.ptr_smear7571 = insertelement <8 x i64> undef, i64 %ptr2int563, i32 7
   %new_ptr582 = add <8 x i64> %smear.ptr_smear7571, zeroinitializer
-  %val_5.i21509 = load i8* null, align 1
+  %val_5.i21509 = load i8, i8* null, align 1
   %6 = insertelement <8 x i8> undef, i8 %val_5.i21509, i32 5
   %7 = insertelement <8 x i8> %6, i8 undef, i32 6
   %iptr_7.i21515 = extractelement <8 x i64> %new_ptr582, i32 7
   %ptr_7.i21516 = inttoptr i64 %iptr_7.i21515 to i8*
-  %val_7.i21517 = load i8* %ptr_7.i21516, align 1
+  %val_7.i21517 = load i8, i8* %ptr_7.i21516, align 1
   %8 = insertelement <8 x i8> %7, i8 %val_7.i21517, i32 7
   %uint2float.i20245 = uitofp <8 x i8> %8 to <8 x float>
   %binop.i20246 = fmul <8 x float> %uint2float.i20245, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
diff --git a/test/CodeGen/X86/2011-11-30-or.ll b/test/CodeGen/X86/2011-11-30-or.ll
index 8ac4632329b3..4260e817b415 100644
--- a/test/CodeGen/X86/2011-11-30-or.ll
+++ b/test/CodeGen/X86/2011-11-30-or.ll
@@ -2,13 +2,13 @@
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
 target triple = "x86_64-apple-macosx10.6.6"
-
-; Test that the order of operands is correct
-; CHECK: select_func
-; CHECK: pblendvb        %xmm1, %xmm2
-; CHECK: ret
-
-define void @select_func(<8 x i16> %in) {
+

+; Test that the order of operands is correct

+; CHECK: select_func

+; CHECK: pblendvb        {{LCPI0_[0-9]*}}(%rip), %xmm1

+; CHECK: ret

+

+define void @select_func(<8 x i16> %in) {

 entry:
   %c.lobit.i.i.i = ashr <8 x i16> %in, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
   %and.i56.i.i.i = and <8 x i16> %c.lobit.i.i.i, <i16 25, i16 8, i16 65, i16 25, i16 8, i16 95, i16 15, i16 45>
diff --git a/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll b/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll
index df9823aa3825..2a1a5c9fb3ea 100644
--- a/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll
+++ b/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s
 ; PR11494
 
 define void @test(<4 x i32>* nocapture %p) nounwind {
@@ -14,5 +14,4 @@ define void @test(<4 x i32>* nocapture %p) nounwind {
   ret void
 }
 
-declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone
 declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
diff --git a/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll b/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll
index 1561784dee32..ab1b46c99d97 100644
--- a/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll
+++ b/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll
@@ -13,7 +13,7 @@ loop:                                             ; preds = %loop.cond
   br i1 undef, label %0, label %t1.exit
 
 ; <label>:0                                       ; preds = %loop
-  %1 = load <16 x i32> addrspace(1)* undef, align 64
+  %1 = load <16 x i32>, <16 x i32> addrspace(1)* undef, align 64
   %2 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> %1, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 0, i32 0>
   store <16 x i32> %2, <16 x i32> addrspace(1)* undef, align 64
   br label %t1.exit
@@ -29,7 +29,7 @@ define void @t2() nounwind {
   br i1 undef, label %1, label %4
 
 ; <label>:1                                       ; preds = %0
-  %2 = load <16 x i32> addrspace(1)* undef, align 64
+  %2 = load <16 x i32>, <16 x i32> addrspace(1)* undef, align 64
   %3 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> %2, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 20, i32 0, i32 0, i32 0, i32 0>
   store <16 x i32> %3, <16 x i32> addrspace(1)* undef, align 64
   br label %4
@@ -50,7 +50,7 @@ loop:                                             ; preds = %loop.cond
 
 ; <label>:0                                       ; preds = %loop
   %1 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> undef, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 25, i32 0>
-  %2 = load <16 x i32> addrspace(1)* undef, align 64
+  %2 = load <16 x i32>, <16 x i32> addrspace(1)* undef, align 64
   %3 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> %2, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 28, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   store <16 x i32> %3, <16 x i32> addrspace(1)* undef, align 64
   br label %t2.exit
@@ -64,7 +64,7 @@ return:                                           ; preds = %loop.cond
 
 define <3 x i64> @t4() nounwind {
 entry:
-  %0 = load <2 x i64> addrspace(1)* undef, align 16
+  %0 = load <2 x i64>, <2 x i64> addrspace(1)* undef, align 16
   %1 = extractelement <2 x i64> %0, i32 0
   %2 = insertelement <3 x i64> <i64 undef, i64 0, i64 0>, i64 %1, i32 0
   ret <3 x i64> %2
diff --git a/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll b/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll
index 14643e4ba8b8..0944adb8b002 100644
--- a/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll
+++ b/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll
@@ -8,7 +8,7 @@
 ; CHECK-LABEL: test:
 ; CHECK: pextrd $2, %xmm
 define <4 x i32> @test(<4 x i32>* %p) {
-  %v = load <4 x i32>* %p
+  %v = load <4 x i32>, <4 x i32>* %p
   %e = extractelement <4 x i32> %v, i32 2
   %cmp = icmp eq i32 %e, 3
   %sel = select i1 %cmp, <4 x i32> %v, <4 x i32> zeroinitializer
diff --git a/test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll b/test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll
index 501a8101a3fe..21443441c9f3 100644
--- a/test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll
+++ b/test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll
@@ -34,8 +34,8 @@ bb11:                                             ; preds = %bb7
   %tmp12 = ptrtoint i8* %tmp10 to i32
   %tmp13 = bitcast i8* %tmp10 to i32*
   %tmp14 = shl i32 %tmp8, 2
-  %tmp15 = getelementptr i32* %tmp13, i32 undef
-  %tmp16 = getelementptr i32* %tmp13, i32 undef
+  %tmp15 = getelementptr i32, i32* %tmp13, i32 undef
+  %tmp16 = getelementptr i32, i32* %tmp13, i32 undef
   %tmp17 = zext i32 %tmp9 to i64
   %tmp18 = add i64 %tmp17, -1
   %tmp19 = icmp ugt i64 %tmp18, 4294967295
@@ -108,8 +108,8 @@ bb49:                                             ; preds = %bb49, %bb48
   %tmp50 = phi i32 [ %tmp55, %bb49 ], [ 0, %bb48 ]
   %tmp51 = add i32 %tmp50, undef
   %tmp52 = add i32 %tmp50, undef
-  %tmp53 = getelementptr i32* %tmp13, i32 %tmp52
-  %tmp54 = load i32* %tmp53, align 4
+  %tmp53 = getelementptr i32, i32* %tmp13, i32 %tmp52
+  %tmp54 = load i32, i32* %tmp53, align 4
   %tmp55 = add i32 %tmp50, 1
   %tmp56 = icmp eq i32 %tmp55, %tmp8
   br i1 %tmp56, label %bb57, label %bb49
@@ -126,7 +126,7 @@ bb59:                                             ; preds = %bb45
 bb61:                                             ; preds = %bb61, %bb59
   %tmp62 = phi i32 [ %tmp65, %bb61 ], [ 0, %bb59 ]
   %tmp63 = add i32 %tmp62, %tmp14
-  %tmp64 = getelementptr i32* %tmp13, i32 %tmp63
+  %tmp64 = getelementptr i32, i32* %tmp13, i32 %tmp63
   store i32 0, i32* %tmp64, align 4
   %tmp65 = add i32 %tmp62, 1
   %tmp66 = icmp eq i32 %tmp65, %tmp8
diff --git a/test/CodeGen/X86/2012-01-11-split-cv.ll b/test/CodeGen/X86/2012-01-11-split-cv.ll
index 69d4b93bb78d..cb39ed911976 100644
--- a/test/CodeGen/X86/2012-01-11-split-cv.ll
+++ b/test/CodeGen/X86/2012-01-11-split-cv.ll
@@ -3,7 +3,7 @@
 ;CHECK-LABEL: add18i16:
 define void @add18i16(<18 x i16>* nocapture sret %ret, <18 x i16>* %bp) nounwind {
 ;CHECK: vmovaps
-  %b = load <18 x i16>* %bp, align 16
+  %b = load <18 x i16>, <18 x i16>* %bp, align 16
   %x = add <18 x i16> zeroinitializer, %b
   store <18 x i16> %x, <18 x i16>* %ret, align 16
 ;CHECK: ret
diff --git a/test/CodeGen/X86/2012-01-12-extract-sv.ll b/test/CodeGen/X86/2012-01-12-extract-sv.ll
index fa8e80f0bdef..677c902668bc 100644
--- a/test/CodeGen/X86/2012-01-12-extract-sv.ll
+++ b/test/CodeGen/X86/2012-01-12-extract-sv.ll
@@ -1,12 +1,25 @@
-; RUN: llc < %s -march=x86 -mcpu=corei7-avx -mattr=+avx -mtriple=i686-pc-win32 | FileCheck %s
+; RUN: llc < %s -mattr=+avx -mtriple=i686-pc-win32 | FileCheck %s
 
-; CHECK: endless_loop
 define void @endless_loop() {
+; CHECK-LABEL: endless_loop:
+; CHECK-NEXT:     # BB#0:
+; CHECK-NEXT:	vmovaps	(%eax), %ymm0
+; CHECK-NEXT:	vextractf128	$1, %ymm0, %xmm0
+; CHECK-NEXT:	vmovsldup	%xmm0, %xmm0    # xmm0 = xmm0[0,0,2,2]
+; CHECK-NEXT:	vmovddup	%xmm0, %xmm1    # xmm1 = xmm0[0,0]
+; CHECK-NEXT:	vinsertf128	$1, %xmm1, %ymm0, %ymm1
+; CHECK-NEXT:	vxorps	%xmm2, %xmm2, %xmm2
+; CHECK-NEXT:	vblendps	$128, %ymm1, %ymm2, %ymm1 # ymm1 = ymm2[0,1,2,3,4,5,6],ymm1[7]
+; CHECK-NEXT:	vxorps	%ymm2, %ymm2, %ymm2
+; CHECK-NEXT:	vblendps	$1, %ymm0, %ymm2, %ymm0 # ymm0 = ymm0[0],ymm2[1,2,3,4,5,6,7]
+; CHECK-NEXT:	vmovaps	%ymm0, (%eax)
+; CHECK-NEXT:	vmovaps	%ymm1, (%eax)
+; CHECK-NEXT:	vzeroupper
+; CHECK-NEXT:	retl
 entry:
-  %0 = load <8 x i32> addrspace(1)* undef, align 32
+  %0 = load <8 x i32>, <8 x i32> addrspace(1)* undef, align 32
   %1 = shufflevector <8 x i32> %0, <8 x i32> undef, <16 x i32> <i32 4, i32 4, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %2 = shufflevector <16 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 undef>, <16 x i32> %1, <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 17>
   store <16 x i32> %2, <16 x i32> addrspace(1)* undef, align 64
   ret void
-; CHECK: ret
 }
diff --git a/test/CodeGen/X86/2012-01-16-mfence-nosse-flags.ll b/test/CodeGen/X86/2012-01-16-mfence-nosse-flags.ll
index b78c13f9d4e6..a6c34b8fffa1 100644
--- a/test/CodeGen/X86/2012-01-16-mfence-nosse-flags.ll
+++ b/test/CodeGen/X86/2012-01-16-mfence-nosse-flags.ll
@@ -5,7 +5,7 @@
 
 define void @baz() nounwind ssp {
 entry:
-  %0 = load i8** @ptr, align 4
+  %0 = load i8*, i8** @ptr, align 4
   %cmp = icmp eq i8* %0, null
   fence seq_cst
   br i1 %cmp, label %if.then, label %if.else
@@ -13,8 +13,7 @@ entry:
 ; Make sure the fence comes before the comparison, since it
 ; clobbers EFLAGS.
 
-; CHECK: lock
-; CHECK-NEXT: orl {{.*}}, (%esp)
+; CHECK: lock orl {{.*}}, (%esp)
 ; CHECK-NEXT: testl [[REG:%e[a-z]+]], [[REG]]
 
 if.then:                                          ; preds = %entry
diff --git a/test/CodeGen/X86/2012-02-12-dagco.ll b/test/CodeGen/X86/2012-02-12-dagco.ll
index 13723a229943..5d48c142dc1d 100644
--- a/test/CodeGen/X86/2012-02-12-dagco.ll
+++ b/test/CodeGen/X86/2012-02-12-dagco.ll
@@ -3,9 +3,9 @@ target triple = "x86_64-unknown-linux-gnu"
 ; Make sure we are not crashing on this one
 define void @dagco_crash() {
 entry:
-  %srcval.i411.i = load <4 x i64>* undef, align 1
+  %srcval.i411.i = load <4 x i64>, <4 x i64>* undef, align 1
   %0 = extractelement <4 x i64> %srcval.i411.i, i32 3
-  %srcval.i409.i = load <2 x i64>* undef, align 1
+  %srcval.i409.i = load <2 x i64>, <2 x i64>* undef, align 1
   %1 = extractelement <2 x i64> %srcval.i409.i, i32 0
   %2 = insertelement <8 x i64> undef, i64 %0, i32 5
   %3 = insertelement <8 x i64> %2, i64 %1, i32 6
diff --git a/test/CodeGen/X86/2012-02-29-CoalescerBug.ll b/test/CodeGen/X86/2012-02-29-CoalescerBug.ll
index bdce85325f37..bbeb2a022192 100644
--- a/test/CodeGen/X86/2012-02-29-CoalescerBug.ll
+++ b/test/CodeGen/X86/2012-02-29-CoalescerBug.ll
@@ -14,9 +14,9 @@ target triple = "i386-apple-macosx10.7.0"
 define void @fn2() nounwind optsize ssp {
 entry:
   store i64 0, i64* bitcast ([2 x [2 x %struct.S0]]* @d to i64*), align 4
-  %0 = load i32* @c, align 4
+  %0 = load i32, i32* @c, align 4
   %tobool2 = icmp eq i32 %0, 0
-  %1 = load i32* @a, align 4
+  %1 = load i32, i32* @a, align 4
   %tobool4 = icmp eq i32 %1, 0
   br label %for.cond
 
diff --git a/test/CodeGen/X86/2012-03-26-PostRALICMBug.ll b/test/CodeGen/X86/2012-03-26-PostRALICMBug.ll
index 90d8d3d2dd6d..260f059492ff 100644
--- a/test/CodeGen/X86/2012-03-26-PostRALICMBug.ll
+++ b/test/CodeGen/X86/2012-03-26-PostRALICMBug.ll
@@ -20,8 +20,8 @@ entry:
   indirectbr i8* undef, [label %return, label %if.end]
 
 if.end:                                           ; preds = %entry
-  %size5 = getelementptr inbounds %struct.ref_s* %op, i64 0, i32 2
-  %tmp6 = load i16* %size5, align 2
+  %size5 = getelementptr inbounds %struct.ref_s, %struct.ref_s* %op, i64 0, i32 2
+  %tmp6 = load i16, i16* %size5, align 2
   %tobool1 = icmp eq i16 %tmp6, 0
   %1 = select i1 %tobool1, i32 1396, i32 -1910
   %index10 = add i32 %index9, %1
@@ -29,19 +29,19 @@ if.end:                                           ; preds = %entry
 
 while.body.lr.ph:                                 ; preds = %if.end
   %refs = bitcast %struct.ref_s* %op to %struct.ref_s**
-  %tmp9 = load %struct.ref_s** %refs, align 8
+  %tmp9 = load %struct.ref_s*, %struct.ref_s** %refs, align 8
   %tmp4 = zext i16 %tmp6 to i64
   %index13 = add i32 %index10, 1658
   %2 = sext i32 %index13 to i64
-  %3 = getelementptr [3891 x i64]* @table, i64 0, i64 %2
-  %blockaddress14 = load i64* %3, align 8
+  %3 = getelementptr [3891 x i64], [3891 x i64]* @table, i64 0, i64 %2
+  %blockaddress14 = load i64, i64* %3, align 8
   %4 = inttoptr i64 %blockaddress14 to i8*
   indirectbr i8* %4, [label %while.body]
 
 while.body:                                       ; preds = %while.body, %while.body.lr.ph
   %index7 = phi i32 [ %index15, %while.body ], [ %index13, %while.body.lr.ph ]
   %indvar = phi i64 [ %indvar.next, %while.body ], [ 0, %while.body.lr.ph ]
-  %type_attrs = getelementptr %struct.ref_s* %tmp9, i64 %indvar, i32 1
+  %type_attrs = getelementptr %struct.ref_s, %struct.ref_s* %tmp9, i64 %indvar, i32 1
   store i16 32, i16* %type_attrs, align 2
   %indvar.next = add i64 %indvar, 1
   %exitcond5 = icmp eq i64 %indvar.next, %tmp4
@@ -49,8 +49,8 @@ while.body:                                       ; preds = %while.body, %while.
   %index15 = add i32 %index7, %tmp7
   %tmp8 = select i1 %exitcond5, i64 13, i64 0
   %5 = sext i32 %index15 to i64
-  %6 = getelementptr [3891 x i64]* @table, i64 0, i64 %5
-  %blockaddress16 = load i64* %6, align 8
+  %6 = getelementptr [3891 x i64], [3891 x i64]* @table, i64 0, i64 %5
+  %blockaddress16 = load i64, i64* %6, align 8
   %7 = inttoptr i64 %blockaddress16 to i8*
   indirectbr i8* %7, [label %return, label %while.body]
 
diff --git a/test/CodeGen/X86/2012-04-26-sdglue.ll b/test/CodeGen/X86/2012-04-26-sdglue.ll
index 6651af705551..4e3f1f4a6e4d 100644
--- a/test/CodeGen/X86/2012-04-26-sdglue.ll
+++ b/test/CodeGen/X86/2012-04-26-sdglue.ll
@@ -5,18 +5,18 @@
 ; It's hard to test for the ISEL condition because CodeGen optimizes
 ; away the bugpointed code. Just ensure the basics are still there.
 ;CHECK-LABEL: func:
-;CHECK: vpxor
-;CHECK: vinserti128
+;CHECK: vxorps
 ;CHECK: vpshufd
 ;CHECK: vpbroadcastd
+;CHECK: vinserti128
 ;CHECK: vmulps
 ;CHECK: vmulps
 ;CHECK: ret
 
 define void @func() nounwind ssp {
-  %tmp = load <4 x float>* null, align 1
-  %tmp14 = getelementptr <4 x float>* null, i32 2
-  %tmp15 = load <4 x float>* %tmp14, align 1
+  %tmp = load <4 x float>, <4 x float>* null, align 1
+  %tmp14 = getelementptr <4 x float>, <4 x float>* null, i32 2
+  %tmp15 = load <4 x float>, <4 x float>* %tmp14, align 1
   %tmp16 = shufflevector <4 x float> %tmp, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
   %tmp17 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %tmp16, <4 x float> undef, i8 1)
   %tmp18 = bitcast <4 x float> %tmp to <16 x i8>
diff --git a/test/CodeGen/X86/2012-07-10-extload64.ll b/test/CodeGen/X86/2012-07-10-extload64.ll
index 723302723b6b..a366102fbd74 100644
--- a/test/CodeGen/X86/2012-07-10-extload64.ll
+++ b/test/CodeGen/X86/2012-07-10-extload64.ll
@@ -4,9 +4,9 @@
 define void @load_store(<4 x i16>* %in) {
 entry:
 ; CHECK: pmovzxwd
-  %A27 = load <4 x i16>* %in, align 4
+  %A27 = load <4 x i16>, <4 x i16>* %in, align 4
   %A28 = add <4 x i16> %A27, %A27
-; CHECK: movlpd
+; CHECK: movq
   store <4 x i16> %A28, <4 x i16>* %in, align 4
   ret void
 ; CHECK: ret
@@ -18,14 +18,14 @@ define void @store_64(<2 x i32>* %ptr) {
 BB:
   store <2 x i32> zeroinitializer, <2 x i32>* %ptr
   ret void
-;CHECK: movlpd
+;CHECK: movlps
 ;CHECK: ret
 }
 
 ;CHECK-LABEL: load_64:
 define <2 x i32> @load_64(<2 x i32>* %ptr) {
 BB:
-  %t = load <2 x i32>* %ptr
+  %t = load <2 x i32>, <2 x i32>* %ptr
   ret <2 x i32> %t
 ;CHECK: pmovzxdq
 ;CHECK: ret
diff --git a/test/CodeGen/X86/2012-07-15-broadcastfold.ll b/test/CodeGen/X86/2012-07-15-broadcastfold.ll
index 519c7cac736f..7c8c2f28348a 100644
--- a/test/CodeGen/X86/2012-07-15-broadcastfold.ll
+++ b/test/CodeGen/X86/2012-07-15-broadcastfold.ll
@@ -1,5 +1,4 @@
 ; RUN: llc < %s -march=x86 -mcpu=corei7 -mattr=+avx2 | FileCheck %s
-; RUN: llc < %s -march=x86 -mcpu=corei7 -mattr=+avx2 -x86-experimental-vector-shuffle-lowering | FileCheck %s
 
 declare x86_fastcallcc i64 @barrier()
 
@@ -10,7 +9,7 @@ declare x86_fastcallcc i64 @barrier()
 ;CHECK: ret
 define <8 x float> @bcast_fold( float* %A) {
 BB:
-  %A0 = load float* %A
+  %A0 = load float, float* %A
   %tt3 = call x86_fastcallcc i64 @barrier()
   br i1 undef, label %work, label %exit
 
diff --git a/test/CodeGen/X86/2012-08-17-legalizer-crash.ll b/test/CodeGen/X86/2012-08-17-legalizer-crash.ll
index 0d18267fcde1..a19aa52f302f 100644
--- a/test/CodeGen/X86/2012-08-17-legalizer-crash.ll
+++ b/test/CodeGen/X86/2012-08-17-legalizer-crash.ll
@@ -12,9 +12,9 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 define void @fn1() nounwind uwtable ssp {
 entry:
-  %0 = load %struct._GtkSheetRow** @a, align 8
+  %0 = load %struct._GtkSheetRow*, %struct._GtkSheetRow** @a, align 8
   %1 = bitcast %struct._GtkSheetRow* %0 to i576*
-  %srcval2 = load i576* %1, align 8
+  %srcval2 = load i576, i576* %1, align 8
   %tobool = icmp ugt i576 %srcval2, 57586096570152913699974892898380567793532123114264532903689671329431521032595044740083720782129802971518987656109067457577065805510327036019308994315074097345724415
   br i1 %tobool, label %if.then, label %if.end
 
diff --git a/test/CodeGen/X86/2012-09-28-CGPBug.ll b/test/CodeGen/X86/2012-09-28-CGPBug.ll
index 32d7d012dd14..a8e0625e85c1 100644
--- a/test/CodeGen/X86/2012-09-28-CGPBug.ll
+++ b/test/CodeGen/X86/2012-09-28-CGPBug.ll
@@ -16,10 +16,10 @@
 define void @h(i8*) nounwind ssp {
   %2 = alloca i8*
   store i8* %0, i8** %2
-  %3 = load i8** %2
+  %3 = load i8*, i8** %2
   %4 = bitcast i8* %3 to { i32, i32 }*
-  %5 = getelementptr { i32, i32 }* %4, i32 0, i32 0
-  %6 = load i32* %5
+  %5 = getelementptr { i32, i32 }, { i32, i32 }* %4, i32 0, i32 0
+  %6 = load i32, i32* %5
   %7 = srem i32 %6, 2
   %8 = icmp slt i32 %6, 2
   %9 = select i1 %8, i32 %6, i32 %7
@@ -28,14 +28,14 @@ define void @h(i8*) nounwind ssp {
 
 ; <label>:11                                      ; preds = %1
   %12 = zext i1 %10 to i32
-  %13 = getelementptr [4 x i32]* @JT, i32 0, i32 %12
-  %14 = load i32* %13
+  %13 = getelementptr [4 x i32], [4 x i32]* @JT, i32 0, i32 %12
+  %14 = load i32, i32* %13
   %15 = add i32 %14, ptrtoint (i8* blockaddress(@h, %11) to i32)
   %16 = inttoptr i32 %15 to i8*
   indirectbr i8* %16, [label %17, label %18]
 
 ; <label>:17                                      ; preds = %11
-  tail call void (i8*, ...)* @g(i8* getelementptr inbounds ([35 x i8]* @.str40, i32 0, i32 0))
+  tail call void (i8*, ...) @g(i8* getelementptr inbounds ([35 x i8], [35 x i8]* @.str40, i32 0, i32 0))
   br label %22
 
 ; <label>:18                                      ; preds = %11
diff --git a/test/CodeGen/X86/2012-1-10-buildvector.ll b/test/CodeGen/X86/2012-1-10-buildvector.ll
index a5f64c5eaf55..d1c0266941fd 100644
--- a/test/CodeGen/X86/2012-1-10-buildvector.ll
+++ b/test/CodeGen/X86/2012-1-10-buildvector.ll
@@ -1,26 +1,28 @@
-; RUN: llc < %s -march=x86 -mcpu=corei7-avx -mattr=+avx -mtriple=i686-pc-win32 | FileCheck %s
+; RUN: llc < %s -mattr=+avx -mtriple=i686-unknown-unknown | FileCheck %s
 
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"
-target triple = "i686-pc-win32"
-
-;CHECK-LABEL: bad_cast:
 define void @bad_cast() {
-entry:
+; CHECK-LABEL: bad_cast:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    vmovaps %xmm0, (%eax)
+; CHECK-NEXT:    movl $0, (%eax)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %vext.i = shufflevector <2 x i64> undef, <2 x i64> undef, <3 x i32> <i32 0, i32 1, i32 undef>
   %vecinit8.i = shufflevector <3 x i64> zeroinitializer, <3 x i64> %vext.i, <3 x i32> <i32 0, i32 3, i32 4>
   store <3 x i64> %vecinit8.i, <3 x i64>* undef, align 32
-;CHECK: ret
   ret void
 }
 
-
-;CHECK-LABEL: bad_insert:
 define void @bad_insert(i32 %t) {
-entry:
-;CHECK: vpinsrd
+; CHECK-LABEL: bad_insert:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:    vmovaps %ymm0, (%eax)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %v2 = insertelement <8 x i32> zeroinitializer, i32 %t, i32 0
   store <8 x i32> %v2, <8 x i32> addrspace(1)* undef, align 32
-;CHECK: ret
   ret void
 }
 
diff --git a/test/CodeGen/X86/2012-10-02-DAGCycle.ll b/test/CodeGen/X86/2012-10-02-DAGCycle.ll
index 403d21ae9733..c43001eb8c21 100644
--- a/test/CodeGen/X86/2012-10-02-DAGCycle.ll
+++ b/test/CodeGen/X86/2012-10-02-DAGCycle.ll
@@ -8,10 +8,10 @@
 
 define i32 @t(%TRp* inreg %rp) nounwind optsize ssp {
 entry:
-  %handler = getelementptr inbounds %TRp* %rp, i32 0, i32 1
-  %0 = load %TRH** %handler, align 4
-  %sync = getelementptr inbounds %TRH* %0, i32 0, i32 4
-  %sync12 = load {}** %sync, align 4
+  %handler = getelementptr inbounds %TRp, %TRp* %rp, i32 0, i32 1
+  %0 = load %TRH*, %TRH** %handler, align 4
+  %sync = getelementptr inbounds %TRH, %TRH* %0, i32 0, i32 4
+  %sync12 = load {}*, {}** %sync, align 4
   %1 = bitcast {}* %sync12 to i32 (%TRp*)*
   %call = tail call i32 %1(%TRp* inreg %rp) nounwind optsize
   ret i32 %call
@@ -25,17 +25,17 @@ entry:
 
 define { <2 x float>, <2 x float> } @t2(%btConeShape* %this) unnamed_addr uwtable ssp align 2 {
 entry:
-  %0 = getelementptr inbounds %btConeShape* %this, i64 0, i32 0
+  %0 = getelementptr inbounds %btConeShape, %btConeShape* %this, i64 0, i32 0
   br i1 undef, label %if.then, label %if.end17
 
 if.then:                                          ; preds = %entry
-  %vecnorm.sroa.2.8.copyload = load float* undef, align 4
+  %vecnorm.sroa.2.8.copyload = load float, float* undef, align 4
   %cmp4 = fcmp olt float undef, 0x3D10000000000000
   %vecnorm.sroa.2.8.copyload36 = select i1 %cmp4, float -1.000000e+00, float %vecnorm.sroa.2.8.copyload
   %call.i.i.i = tail call float @sqrtf(float 0.000000e+00) nounwind readnone
   %div.i.i = fdiv float 1.000000e+00, %call.i.i.i
   %mul7.i.i.i = fmul float %div.i.i, %vecnorm.sroa.2.8.copyload36
-  %1 = load float (%btConvexInternalShape*)** undef, align 8
+  %1 = load float (%btConvexInternalShape*)*, float (%btConvexInternalShape*)** undef, align 8
   %call12 = tail call float %1(%btConvexInternalShape* %0)
   %mul7.i.i = fmul float %call12, %mul7.i.i.i
   %retval.sroa.0.4.insert = insertelement <2 x float> zeroinitializer, float undef, i32 1
diff --git a/test/CodeGen/X86/2012-10-03-DAGCycle.ll b/test/CodeGen/X86/2012-10-03-DAGCycle.ll
index 72083c7115e4..da92565708c8 100644
--- a/test/CodeGen/X86/2012-10-03-DAGCycle.ll
+++ b/test/CodeGen/X86/2012-10-03-DAGCycle.ll
@@ -12,14 +12,14 @@ target triple = "x86_64-apple-macosx10.8.0"
 define fastcc void @bar(%struct.pluto.0* %arg) nounwind uwtable ssp align 2 {
 bb:
   %tmp1 = alloca %struct.widget.375, align 8
-  %tmp2 = getelementptr inbounds %struct.pluto.0* %arg, i64 0, i32 1
-  %tmp3 = load %struct.hoge.368** %tmp2, align 8
+  %tmp2 = getelementptr inbounds %struct.pluto.0, %struct.pluto.0* %arg, i64 0, i32 1
+  %tmp3 = load %struct.hoge.368*, %struct.hoge.368** %tmp2, align 8
   store %struct.pluto.0* %arg, %struct.pluto.0** undef, align 8
-  %tmp = getelementptr inbounds %struct.widget.375* %tmp1, i64 0, i32 2
-  %tmp4 = getelementptr %struct.pluto.0* %arg, i64 0, i32 0, i32 0
-  %tmp5 = load %i8** %tmp4, align 8
+  %tmp = getelementptr inbounds %struct.widget.375, %struct.widget.375* %tmp1, i64 0, i32 2
+  %tmp4 = getelementptr %struct.pluto.0, %struct.pluto.0* %arg, i64 0, i32 0, i32 0
+  %tmp5 = load %i8*, %i8** %tmp4, align 8
   store %i8* %tmp5, %i8** %tmp, align 8
-  %tmp6 = getelementptr inbounds %struct.widget.375* %tmp1, i64 0, i32 3
+  %tmp6 = getelementptr inbounds %struct.widget.375, %struct.widget.375* %tmp1, i64 0, i32 3
   store %struct.hoge.368* %tmp3, %struct.hoge.368** %tmp6, align 8
   br i1 undef, label %bb8, label %bb7
 
diff --git a/test/CodeGen/X86/2012-10-18-crash-dagco.ll b/test/CodeGen/X86/2012-10-18-crash-dagco.ll
index 5b98624a37b8..fb29241035ef 100644
--- a/test/CodeGen/X86/2012-10-18-crash-dagco.ll
+++ b/test/CodeGen/X86/2012-10-18-crash-dagco.ll
@@ -22,23 +22,23 @@ bb27:                                             ; preds = %bb48, %bb
   ]
 
 bb28:                                             ; preds = %bb27, %bb26
-  %tmp = load i32* null
+  %tmp = load i32, i32* null
   %tmp29 = trunc i32 %tmp to i8
   store i8* undef, i8** undef
-  %tmp30 = load i32* null
+  %tmp30 = load i32, i32* null
   %tmp31 = icmp eq i32 %tmp30, 0
-  %tmp32 = getelementptr inbounds [411 x i8]* @global, i32 0, i32 undef
-  %tmp33 = load i8* %tmp32, align 1
-  %tmp34 = getelementptr inbounds [411 x i8]* @global, i32 0, i32 0
-  %tmp35 = load i8* %tmp34, align 1
+  %tmp32 = getelementptr inbounds [411 x i8], [411 x i8]* @global, i32 0, i32 undef
+  %tmp33 = load i8, i8* %tmp32, align 1
+  %tmp34 = getelementptr inbounds [411 x i8], [411 x i8]* @global, i32 0, i32 0
+  %tmp35 = load i8, i8* %tmp34, align 1
   %tmp36 = select i1 %tmp31, i8 %tmp35, i8 %tmp33
   %tmp37 = select i1 undef, i8 %tmp29, i8 %tmp36
   %tmp38 = zext i8 %tmp37 to i32
   %tmp39 = select i1 undef, i32 0, i32 %tmp38
-  %tmp40 = getelementptr inbounds i32* null, i32 %tmp39
-  %tmp41 = load i32* %tmp40, align 4
-  %tmp42 = load i32* undef, align 4
-  %tmp43 = load i32* undef
+  %tmp40 = getelementptr inbounds i32, i32* null, i32 %tmp39
+  %tmp41 = load i32, i32* %tmp40, align 4
+  %tmp42 = load i32, i32* undef, align 4
+  %tmp43 = load i32, i32* undef
   %tmp44 = xor i32 %tmp42, %tmp43
   %tmp45 = lshr i32 %tmp44, 8
   %tmp46 = lshr i32 %tmp44, 7
diff --git a/test/CodeGen/X86/2012-11-28-merge-store-alias.ll b/test/CodeGen/X86/2012-11-28-merge-store-alias.ll
index 756e86e0f801..ed1daadf6297 100644
--- a/test/CodeGen/X86/2012-11-28-merge-store-alias.ll
+++ b/test/CodeGen/X86/2012-11-28-merge-store-alias.ll
@@ -2,7 +2,7 @@
 
 ; CHECK: merge_stores_can
 ; CHECK: callq foo
-; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK: xorps %xmm0, %xmm0
 ; CHECK-NEXT: movups  %xmm0
 ; CHECK: callq foo
 ; CHECK: ret
@@ -13,15 +13,15 @@ define i32 @merge_stores_can() nounwind ssp {
 
   %ret0 = call i32 @foo([10 x i32]* %object1) nounwind
 
-  %O1_1 = getelementptr [10 x i32]* %object1, i64 0, i32 1
-  %O1_2 = getelementptr [10 x i32]* %object1, i64 0, i32 2
-  %O1_3 = getelementptr [10 x i32]* %object1, i64 0, i32 3
-  %O1_4 = getelementptr [10 x i32]* %object1, i64 0, i32 4
-  %ld_ptr = getelementptr [10 x i32]* %object1, i64 0, i32 9
+  %O1_1 = getelementptr [10 x i32], [10 x i32]* %object1, i64 0, i32 1
+  %O1_2 = getelementptr [10 x i32], [10 x i32]* %object1, i64 0, i32 2
+  %O1_3 = getelementptr [10 x i32], [10 x i32]* %object1, i64 0, i32 3
+  %O1_4 = getelementptr [10 x i32], [10 x i32]* %object1, i64 0, i32 4
+  %ld_ptr = getelementptr [10 x i32], [10 x i32]* %object1, i64 0, i32 9
 
   store i32 0, i32* %O1_1
   store i32 0, i32* %O1_2
-  %ret = load  i32* %ld_ptr  ; <--- does not alias.
+  %ret = load  i32,  i32* %ld_ptr  ; <--- does not alias.
   store i32 0, i32* %O1_3
   store i32 0, i32* %O1_4
 
@@ -36,15 +36,15 @@ define i32 @merge_stores_can() nounwind ssp {
 ; CHECK: ret
 define i32 @merge_stores_cant([10 x i32]* %in0, [10 x i32]* %in1) nounwind ssp {
 
-  %O1_1 = getelementptr [10 x i32]* %in1, i64 0, i32 1
-  %O1_2 = getelementptr [10 x i32]* %in1, i64 0, i32 2
-  %O1_3 = getelementptr [10 x i32]* %in1, i64 0, i32 3
-  %O1_4 = getelementptr [10 x i32]* %in1, i64 0, i32 4
-  %ld_ptr = getelementptr [10 x i32]* %in0, i64 0, i32 2
+  %O1_1 = getelementptr [10 x i32], [10 x i32]* %in1, i64 0, i32 1
+  %O1_2 = getelementptr [10 x i32], [10 x i32]* %in1, i64 0, i32 2
+  %O1_3 = getelementptr [10 x i32], [10 x i32]* %in1, i64 0, i32 3
+  %O1_4 = getelementptr [10 x i32], [10 x i32]* %in1, i64 0, i32 4
+  %ld_ptr = getelementptr [10 x i32], [10 x i32]* %in0, i64 0, i32 2
 
   store i32 0, i32* %O1_1
   store i32 0, i32* %O1_2
-  %ret = load  i32* %ld_ptr  ;  <--- may alias
+  %ret = load  i32,  i32* %ld_ptr  ;  <--- may alias
   store i32 0, i32* %O1_3
   store i32 0, i32* %O1_4
 
diff --git a/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll b/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll
index c33b48dfecb5..a27db95ba127 100644
--- a/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll
+++ b/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll
@@ -5,7 +5,7 @@
 ; rdar://12777252.
 ;
 ; CHECK: %entry
-; CHECK: DEBUG_VALUE: hg
+; CHECK: DEBUG_VALUE: subdivp:hg
 ; CHECK: j
 
 %struct.node.0.27 = type { i16, double, [3 x double], i32, i32 }
@@ -16,14 +16,14 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 
 define signext i16 @subdivp(%struct.node.0.27* nocapture %p, double %dsq, double %tolsq, %struct.hgstruct.2.29* nocapture byval align 8 %hg) nounwind uwtable readonly ssp {
 entry:
-  call void @llvm.dbg.declare(metadata %struct.hgstruct.2.29* %hg, metadata !4, metadata !{!"0x102"})
-  %type = getelementptr inbounds %struct.node.0.27* %p, i64 0, i32 0
-  %0 = load i16* %type, align 2
+  call void @llvm.dbg.declare(metadata %struct.hgstruct.2.29* %hg, metadata !4, metadata !DIExpression()), !dbg !DILocation(scope: !14)
+  %type = getelementptr inbounds %struct.node.0.27, %struct.node.0.27* %p, i64 0, i32 0
+  %0 = load i16, i16* %type, align 2
   %cmp = icmp eq i16 %0, 1
   br i1 %cmp, label %return, label %for.cond.preheader
 
 for.cond.preheader:                               ; preds = %entry
-  %arrayidx6.1 = getelementptr inbounds %struct.hgstruct.2.29* %hg, i64 0, i32 1, i64 1
+  %arrayidx6.1 = getelementptr inbounds %struct.hgstruct.2.29, %struct.hgstruct.2.29* %hg, i64 0, i32 1, i64 1
   %cmp22 = fcmp olt double 0.000000e+00, %dsq
   %conv24 = zext i1 %cmp22 to i16
   br label %return
@@ -38,15 +38,15 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!12}
 
-!0 = !{!"0x11\0012\00clang version 3.3 (trunk 168918) (llvm/trunk 168920)\001\00\000\00\000", !11, !2, !2, !13, !2, null} ; [ DW_TAG_compile_unit ] [MultiSource/Benchmarks/Olden/bh/newbh.c] [DW_LANG_C99]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.3 (trunk 168918) (llvm/trunk 168920)", isOptimized: true, emissionKind: 0, file: !11, enums: !2, retainedTypes: !2, subprograms: !13, globals: !2)
 !2 = !{}
-!4 = !{!"0x101\00hg\0067109589\000", null, !5, !6} ; [ DW_TAG_arg_variable ] [hg] [line 725]
-!5 = !{!"0x29", !11} ; [ DW_TAG_file_type ]
-!6 = !{!"0x16\00hgstruct\00492\000\000\000\000", !11, null, !7} ; [ DW_TAG_typedef ] [hgstruct] [line 492, size 0, align 0, offset 0] [from ]
-!7 = !{!"0x13\00\00487\00512\0064\000\000\000", !11, null, null, null, null, i32 0, null} ; [ DW_TAG_structure_type ] [line 487, size 512, align 64, offset 0] [def] [from ]
-!11 = !{!"MultiSource/Benchmarks/Olden/bh/newbh.c", !"MultiSource/Benchmarks/Olden/bh"}
-!12 = !{i32 1, !"Debug Info Version", i32 2}
+!4 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "hg", line: 725, arg: 4, scope: !14, file: !5, type: !6)
+!5 = !DIFile(filename: "MultiSource/Benchmarks/Olden/bh/newbh.c", directory: "MultiSource/Benchmarks/Olden/bh")
+!6 = !DIDerivedType(tag: DW_TAG_typedef, name: "hgstruct", line: 492, file: !11, baseType: !7)
+!7 = !DICompositeType(tag: DW_TAG_structure_type, line: 487, size: 512, align: 64, file: !11)
+!11 = !DIFile(filename: "MultiSource/Benchmarks/Olden/bh/newbh.c", directory: "MultiSource/Benchmarks/Olden/bh")
+!12 = !{i32 1, !"Debug Info Version", i32 3}
 !13 = !{!14}
-!14 = !{!"0x2e\00subdivp\00subdivp\00\000\000\001\000\006\00256\001\001", !11, !5, !15, null, i16 (%struct.node.0.27*, double, double, %struct.hgstruct.2.29* )* @subdivp, null, null, null} ; [ DW_TAG_subprogram ] [def] [subdivp]
-!15 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!14 = !DISubprogram(name: "subdivp", isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !11, scope: !5, type: !15, function: i16 (%struct.node.0.27*, double, double, %struct.hgstruct.2.29* )* @subdivp)
+!15 = !DISubroutineType(types: !16)
 !16 = !{null}
diff --git a/test/CodeGen/X86/2012-11-30-misched-dbg.ll b/test/CodeGen/X86/2012-11-30-misched-dbg.ll
index 28ceb2fad2fc..818c5ed56873 100644
--- a/test/CodeGen/X86/2012-11-30-misched-dbg.ll
+++ b/test/CodeGen/X86/2012-11-30-misched-dbg.ll
@@ -43,14 +43,14 @@ if.then3344:
   br label %if.then4073
 
 if.then4073:                                      ; preds = %if.then3344
-  call void @llvm.dbg.declare(metadata [20 x i8]* %num14075, metadata !4, metadata !{!"0x102"})
-  %arraydecay4078 = getelementptr inbounds [20 x i8]* %num14075, i64 0, i64 0
-  %0 = load i32* undef, align 4
+  call void @llvm.dbg.declare(metadata [20 x i8]* %num14075, metadata !4, metadata !DIExpression()), !dbg !DILocation(scope: !5)
+  %arraydecay4078 = getelementptr inbounds [20 x i8], [20 x i8]* %num14075, i64 0, i64 0
+  %0 = load i32, i32* undef, align 4
   %add4093 = add nsw i32 %0, 0
   %conv4094 = sitofp i32 %add4093 to float
   %div4095 = fdiv float %conv4094, 5.670000e+02
   %conv4096 = fpext float %div4095 to double
-  %call4097 = call i32 (i8*, i32, i64, i8*, ...)* @__sprintf_chk(i8* %arraydecay4078, i32 0, i64 20, i8* getelementptr inbounds ([6 x i8]* @.str15, i64 0, i64 0), double %conv4096) nounwind
+  %call4097 = call i32 (i8*, i32, i64, i8*, ...) @__sprintf_chk(i8* %arraydecay4078, i32 0, i64 20, i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str15, i64 0, i64 0), double %conv4096) nounwind
   br i1 %cmp1733, label %if.then4107, label %if.else4114
 
 if.then4107:                                      ; preds = %if.then4073
@@ -65,35 +65,35 @@ declare i32 @__sprintf_chk(i8*, i32, i64, i8*, ...)
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!35}
 
-!0 = !{!"0x11\0012\00clang version 3.3 (trunk 168918) (llvm/trunk 168920)\001\00\000\00\000", !19, !2, !2, !20, !2, null} ; [ DW_TAG_compile_unit ] [MultiSource/Benchmarks/MiBench/consumer-typeset/MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] [DW_LANG_C99]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.3 (trunk 168918) (llvm/trunk 168920)", isOptimized: true, emissionKind: 0, file: !19, enums: !2, retainedTypes: !2, subprograms: !20, globals: !2)
 !1 = !{!2}
 !2 = !{}
-!4 = !{!"0x100\00num1\00815\000", !5, !14, !15} ; [ DW_TAG_auto_variable ] [num1] [line 815]
-!5 = !{!"0xb\00815\000\00177", !14, !6} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c]
-!6 = !{!"0xb\00812\000\00176", !14, !7} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c]
-!7 = !{!"0xb\00807\000\00175", !14, !8} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c]
-!8 = !{!"0xb\00440\000\0094", !14, !9} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c]
-!9 = !{!"0xb\00435\000\0091", !14, !10} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c]
-!10 = !{!"0xb\00434\000\0090", !14, !11} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c]
-!11 = !{!"0xb\00250\000\0024", !14, !12} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c]
-!12 = !{!"0xb\00249\000\0023", !14, !13} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c]
-!13 = !{!"0xb\00221\000\0019", !14, !2} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c]
-!14 = !{!"0x29", !19} ; [ DW_TAG_file_type ]
-!15 = !{!"0x1\00\000\00160\008\000\000", null, null, !16, !17, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 160, align 8, offset 0] [from char]
-!16 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
+!4 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "num1", line: 815, scope: !5, file: !14, type: !15)
+!5 = distinct !DILexicalBlock(line: 815, column: 0, file: !14, scope: !6)
+!6 = distinct !DILexicalBlock(line: 812, column: 0, file: !14, scope: !7)
+!7 = distinct !DILexicalBlock(line: 807, column: 0, file: !14, scope: !8)
+!8 = distinct !DILexicalBlock(line: 440, column: 0, file: !14, scope: !9)
+!9 = distinct !DILexicalBlock(line: 435, column: 0, file: !14, scope: !10)
+!10 = distinct !DILexicalBlock(line: 434, column: 0, file: !14, scope: !11)
+!11 = distinct !DILexicalBlock(line: 250, column: 0, file: !14, scope: !12)
+!12 = distinct !DILexicalBlock(line: 249, column: 0, file: !14, scope: !13)
+!13 = distinct !DILexicalBlock(line: 221, column: 0, file: !14, scope: !21)
+!14 = !DIFile(filename: "MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c", directory: "MultiSource/Benchmarks/MiBench/consumer-typeset")
+!15 = !DICompositeType(tag: DW_TAG_array_type, size: 160, align: 8, baseType: !16, elements: !17)
+!16 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
 !17 = !{!18}
-!18 = !{!"0x21\000\0020"}       ; [ DW_TAG_subrange_type ] [0, 19]
-!19 = !{!"MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c", !"MultiSource/Benchmarks/MiBench/consumer-typeset"}
+!18 = !DISubrange(count: 20)
+!19 = !DIFile(filename: "MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c", directory: "MultiSource/Benchmarks/MiBench/consumer-typeset")
 
 !20 = !{!21}
-!21 = !{!"0x2e\00AttachGalley\00AttachGalley\00\000\000\001\000\006\00256\001\001", !19, !14, !22, null, i32 (%union.rec**)* @AttachGalley, null, null, null} ; [ DW_TAG_subprogram ] [def] [AttachGalley]
-!22 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !23, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!21 = !DISubprogram(name: "AttachGalley", isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !19, scope: !14, type: !22, function: i32 (%union.rec**)* @AttachGalley)
+!22 = !DISubroutineType(types: !23)
 !23 = !{null}
 
 ; Test DebugValue uses visited by RegisterPressureTracker findUseBetween().
 ;
 ; CHECK: @main
-; CHECK: DEBUG_VALUE: X
+; CHECK: DEBUG_VALUE: main:X
 ; CHECK: call
 
 %"class.__gnu_cxx::hash_map" = type { %"class.__gnu_cxx::hashtable" }
@@ -108,8 +108,8 @@ cond.true:                                        ; preds = %entry
   unreachable
 
 cond.end:                                         ; preds = %entry
-  call void @llvm.dbg.declare(metadata %"class.__gnu_cxx::hash_map"* %X, metadata !31, metadata !{!"0x102"})
-  %_M_num_elements.i.i.i.i = getelementptr inbounds %"class.__gnu_cxx::hash_map"* %X, i64 0, i32 0, i32 5
+  call void @llvm.dbg.declare(metadata %"class.__gnu_cxx::hash_map"* %X, metadata !31, metadata !DIExpression()), !dbg !DILocation(scope: !37)
+  %_M_num_elements.i.i.i.i = getelementptr inbounds %"class.__gnu_cxx::hash_map", %"class.__gnu_cxx::hash_map"* %X, i64 0, i32 0, i32 5
   invoke void @_Znwm()
           to label %exit.i unwind label %lpad2.i.i.i.i
 
@@ -134,11 +134,11 @@ declare void @_Znwm()
 
 !llvm.dbg.cu = !{!30}
 
-!30 = !{!"0x11\004\00clang version 3.3 (trunk 169129) (llvm/trunk 169135)\001\00\000\00\000", !34, !2, !2, !36, null, null} ; [ DW_TAG_compile_unit ] [SingleSource/Benchmarks/Shootout-C++/hash.cpp] [DW_LANG_C_plus_plus]
-!31 = !{!"0x100\00X\0029\000", null, null, !32} ; [ DW_TAG_auto_variable ] [X] [line 29]
-!32 = !{!"0x16\00HM\0028\000\000\000\000", !34, null, null} ; [ DW_TAG_typedef ] [HM] [line 28, size 0, align 0, offset 0] [from ]
-!33 = !{!"0x29", !34} ; [ DW_TAG_file_type ]
-!34 = !{!"SingleSource/Benchmarks/Shootout-C++/hash.cpp", !"SingleSource/Benchmarks/Shootout-C++"}
-!35 = !{i32 1, !"Debug Info Version", i32 2}
+!30 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 (trunk 169129) (llvm/trunk 169135)", isOptimized: true, emissionKind: 0, file: !34, enums: !2, retainedTypes: !2, subprograms: !36)
+!31 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "X", line: 29, scope: !37, type: !32)
+!32 = !DIDerivedType(tag: DW_TAG_typedef, name: "HM", line: 28, file: !34, baseType: null)
+!33 = !DIFile(filename: "SingleSource/Benchmarks/Shootout-C++/hash.cpp", directory: "SingleSource/Benchmarks/Shootout-C++")
+!34 = !DIFile(filename: "SingleSource/Benchmarks/Shootout-C++/hash.cpp", directory: "SingleSource/Benchmarks/Shootout-C++")
+!35 = !{i32 1, !"Debug Info Version", i32 3}
 !36 = !{!37}
-!37 = !{!"0x2e\00main\00main\00\000\000\001\000\006\00256\001\001", !19, !14, !22, null, void ()* @main, null, null, null} ; [ DW_TAG_subprogram ] [def] [main]
+!37 = !DISubprogram(name: "main", isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !19, scope: !14, type: !22, function: void ()* @main)
diff --git a/test/CodeGen/X86/2012-11-30-regpres-dbg.ll b/test/CodeGen/X86/2012-11-30-regpres-dbg.ll
index 04b31749ce58..77c017eb0e36 100644
--- a/test/CodeGen/X86/2012-11-30-regpres-dbg.ll
+++ b/test/CodeGen/X86/2012-11-30-regpres-dbg.ll
@@ -4,7 +4,7 @@
 ; Test RegisterPressure handling of DBG_VALUE.
 ;
 ; CHECK: %entry
-; CHECK: DEBUG_VALUE: callback
+; CHECK: DEBUG_VALUE: test:callback
 ; CHECK: ret
 
 %struct.btCompoundLeafCallback = type { i32, i32 }
@@ -20,8 +20,8 @@ if.then:                                          ; preds = %entry
   unreachable
 
 if.end:                                           ; preds = %entry
-  call void @llvm.dbg.declare(metadata %struct.btCompoundLeafCallback* %callback, metadata !3, metadata !{!"0x102"})
-  %m = getelementptr inbounds %struct.btCompoundLeafCallback* %callback, i64 0, i32 1
+  call void @llvm.dbg.declare(metadata %struct.btCompoundLeafCallback* %callback, metadata !3, metadata !DIExpression()), !dbg !DILocation(scope: !2)
+  %m = getelementptr inbounds %struct.btCompoundLeafCallback, %struct.btCompoundLeafCallback* %callback, i64 0, i32 1
   store i32 0, i32* undef, align 8
   %cmp12447 = icmp sgt i32 undef, 0
   br i1 %cmp12447, label %for.body.lr.ph, label %invoke.cont44
@@ -36,13 +36,13 @@ invoke.cont44:                                    ; preds = %if.end
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!8}
 
-!0 = !{!"0x11\004\00clang version 3.3 (trunk 168984) (llvm/trunk 168983)\001\00\000\00\000", !6, null, null, !1, null, null} ; [ DW_TAG_compile_unit ] [MultiSource/Benchmarks/Bullet/MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp] [DW_LANG_C_plus_plus]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 (trunk 168984) (llvm/trunk 168983)", isOptimized: true, emissionKind: 0, file: !6, subprograms: !1)
 !1 = !{!2}
-!2 = !{!"0x2e\00test\00test\00\000\000\001\000\006\00256\001\001", !6, !5, !7, null, void ()* @test, null, null, null} ; [ DW_TAG_subprogram ] [def] [test]
-!3 = !{!"0x100\00callback\00214\000", null, null, !4} ; [ DW_TAG_auto_variable ] [callback] [line 214]
-!4 = !{!"0x13\00btCompoundLeafCallback\0090\00512\0064\000\000\000", !6, null, null, null, null, null, null} ; [ DW_TAG_structure_type ] [btCompoundLeafCallback] [line 90, size 512, align 64, offset 0] [def] [from ]
-!5 = !{!"0x29", !6} ; [ DW_TAG_file_type ]
-!6 = !{!"MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp", !"MultiSource/Benchmarks/Bullet"}
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !9, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!8 = !{i32 1, !"Debug Info Version", i32 2}
+!2 = !DISubprogram(name: "test", isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !6, scope: !5, type: !7, function: void ()* @test)
+!3 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "callback", line: 214, scope: !2, type: !4)
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "btCompoundLeafCallback", line: 90, size: 512, align: 64, file: !6)
+!5 = !DIFile(filename: "MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp", directory: "MultiSource/Benchmarks/Bullet")
+!6 = !DIFile(filename: "MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp", directory: "MultiSource/Benchmarks/Bullet")
+!7 = !DISubroutineType(types: !9)
+!8 = !{i32 1, !"Debug Info Version", i32 3}
 !9 = !{null}
diff --git a/test/CodeGen/X86/2012-12-06-python27-miscompile.ll b/test/CodeGen/X86/2012-12-06-python27-miscompile.ll
index d9effc92fa92..b80ae3ae2b7f 100644
--- a/test/CodeGen/X86/2012-12-06-python27-miscompile.ll
+++ b/test/CodeGen/X86/2012-12-06-python27-miscompile.ll
@@ -12,10 +12,10 @@ target triple = "x86_64-apple-macosx10.8.0"
 ;CHECK: ret
 define i32 @foo (i64* %so) nounwind uwtable ssp {
 entry:
-  %used = getelementptr inbounds i64* %so, i32 3
+  %used = getelementptr inbounds i64, i64* %so, i32 3
   store i64 0, i64* %used, align 8
-  %fill = getelementptr inbounds i64* %so, i32 2
-  %L = load i64* %fill, align 8
+  %fill = getelementptr inbounds i64, i64* %so, i32 2
+  %L = load i64, i64* %fill, align 8
   store i64 0, i64* %fill, align 8
   %cmp28 = icmp sgt i64 %L, 0
   %R = sext i1 %cmp28 to i32
diff --git a/test/CodeGen/X86/2012-12-1-merge-multiple.ll b/test/CodeGen/X86/2012-12-1-merge-multiple.ll
index 5931c3d27be1..9be8b5bbb427 100644
--- a/test/CodeGen/X86/2012-12-1-merge-multiple.ll
+++ b/test/CodeGen/X86/2012-12-1-merge-multiple.ll
@@ -8,14 +8,14 @@
 ; CHECK: ret
 define void @multiple_stores_on_chain(i16 * %A) {
 entry:
-  %a0 = getelementptr inbounds i16* %A, i64 0
-  %a1 = getelementptr inbounds i16* %A, i64 1
-  %a2 = getelementptr inbounds i16* %A, i64 2
-  %a3 = getelementptr inbounds i16* %A, i64 3
-  %a4 = getelementptr inbounds i16* %A, i64 4
-  %a5 = getelementptr inbounds i16* %A, i64 5
-  %a6 = getelementptr inbounds i16* %A, i64 6
-  %a7 = getelementptr inbounds i16* %A, i64 7
+  %a0 = getelementptr inbounds i16, i16* %A, i64 0
+  %a1 = getelementptr inbounds i16, i16* %A, i64 1
+  %a2 = getelementptr inbounds i16, i16* %A, i64 2
+  %a3 = getelementptr inbounds i16, i16* %A, i64 3
+  %a4 = getelementptr inbounds i16, i16* %A, i64 4
+  %a5 = getelementptr inbounds i16, i16* %A, i64 5
+  %a6 = getelementptr inbounds i16, i16* %A, i64 6
+  %a7 = getelementptr inbounds i16, i16* %A, i64 7
 
   store i16 0, i16* %a0
   store i16 1, i16* %a1
diff --git a/test/CodeGen/X86/2012-12-19-NoImplicitFloat.ll b/test/CodeGen/X86/2012-12-19-NoImplicitFloat.ll
index 302566520671..e5a64b5ae87e 100644
--- a/test/CodeGen/X86/2012-12-19-NoImplicitFloat.ll
+++ b/test/CodeGen/X86/2012-12-19-NoImplicitFloat.ll
@@ -8,10 +8,10 @@ define void @test() nounwind noimplicitfloat {
 entry:
 ; CHECK-NOT: xmm
 ; CHECK: ret
-  %0 = load %struct1** undef, align 8
-  %1 = getelementptr inbounds %struct1* %0, i64 0, i32 0
+  %0 = load %struct1*, %struct1** undef, align 8
+  %1 = getelementptr inbounds %struct1, %struct1* %0, i64 0, i32 0
   store i32* null, i32** %1, align 8
-  %2 = getelementptr inbounds %struct1* %0, i64 0, i32 1
+  %2 = getelementptr inbounds %struct1, %struct1* %0, i64 0, i32 1
   store i32* null, i32** %2, align 8
   ret void
 }
diff --git a/test/CodeGen/X86/2013-02-12-ShuffleToZext.ll b/test/CodeGen/X86/2013-02-12-ShuffleToZext.ll
deleted file mode 100644
index 614ccda5e250..000000000000
--- a/test/CodeGen/X86/2013-02-12-ShuffleToZext.ll
+++ /dev/null
@@ -1,14 +0,0 @@
-; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx -mtriple=x86_64-pc-win32 | FileCheck %s
-
-; CHECK: test
-; CHECK: vpmovzxwd
-; CHECK: vpmovzxwd
-define void @test(<4 x i64> %a, <4 x i16>* %buf) {
-  %ex1 = extractelement <4 x i64> %a, i32 0
-  %ex2 = extractelement <4 x i64> %a, i32 1
-  %x1 = bitcast i64 %ex1 to <4 x i16>
-  %x2 = bitcast i64 %ex2 to <4 x i16>
-  %Sh = shufflevector <4 x i16> %x1, <4 x i16> %x2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
-  store <4 x i16> %Sh, <4 x i16>* %buf, align 1
-  ret void
-}
diff --git a/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll b/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll
index 0ff9d3951d5b..f6827c1c75a7 100644
--- a/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll
+++ b/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll
@@ -9,7 +9,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 define void @main() #0 {
 entry:
-  %0 = load <8 x float>* bitcast ([8 x float]* @b to <8 x float>*), align 32
+  %0 = load <8 x float>, <8 x float>* bitcast ([8 x float]* @b to <8 x float>*), align 32
   %bitcast.i = extractelement <8 x float> %0, i32 0
   %vecinit.i.i = insertelement <4 x float> undef, float %bitcast.i, i32 0
   %vecinit2.i.i = insertelement <4 x float> %vecinit.i.i, float 0.000000e+00, i32 1
@@ -17,7 +17,7 @@ entry:
   %vecinit4.i.i = insertelement <4 x float> %vecinit3.i.i, float 0.000000e+00, i32 3
   %1 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %vecinit4.i.i) #2
   %vecext.i.i = extractelement <4 x float> %1, i32 0
-  store float %vecext.i.i, float* getelementptr inbounds ([8 x float]* @e, i64 0, i64 0), align 16
+  store float %vecext.i.i, float* getelementptr inbounds ([8 x float], [8 x float]* @e, i64 0, i64 0), align 16
   unreachable
 }
 
diff --git a/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll b/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll
index 9cd150a2f56d..5ef867d4f9dc 100644
--- a/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll
+++ b/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll
@@ -34,7 +34,7 @@
 ; CHECK: ret
 define i64 @test_bitcast(i64 (i64, i64, i64)** %arg, i1 %bool, i64 %arg2) {
 entry:
-  %loaded_ptr = load i64 (i64, i64, i64)** %arg, align 8
+  %loaded_ptr = load i64 (i64, i64, i64)*, i64 (i64, i64, i64)** %arg, align 8
   %raw = bitcast i64 (i64, i64, i64)* %loaded_ptr to i8*
   switch i1 %bool, label %default [
     i1 true, label %label_true
@@ -73,7 +73,7 @@ label_end:
 ; CHECK: ret
 define i64 @test_inttoptr(i64 (i64, i64, i64)** %arg, i1 %bool, i64 %arg2) {
 entry:
-  %loaded_ptr = load i64 (i64, i64, i64)** %arg, align 8
+  %loaded_ptr = load i64 (i64, i64, i64)*, i64 (i64, i64, i64)** %arg, align 8
   %raw = ptrtoint i64 (i64, i64, i64)* %loaded_ptr to i64
   switch i1 %bool, label %default [
     i1 true, label %label_true
@@ -112,7 +112,7 @@ label_end:
 ; CHECK: ret
 define i64 @test_ptrtoint(i64 (i64, i64, i64)** %arg, i1 %bool, i64 %arg2) {
 entry:
-  %loaded_ptr = load i64 (i64, i64, i64)** %arg, align 8
+  %loaded_ptr = load i64 (i64, i64, i64)*, i64 (i64, i64, i64)** %arg, align 8
   %raw = bitcast i64 (i64, i64, i64)* %loaded_ptr to i8*
   switch i1 %bool, label %default [
     i1 true, label %label_true
diff --git a/test/CodeGen/X86/2014-08-29-CompactUnwind.ll b/test/CodeGen/X86/2014-08-29-CompactUnwind.ll
index f65d7c9d2e05..e7e8bb724fc0 100644
--- a/test/CodeGen/X86/2014-08-29-CompactUnwind.ll
+++ b/test/CodeGen/X86/2014-08-29-CompactUnwind.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -disable-fp-elim -mtriple x86_64-apple-darwin11 -mcpu corei7 -filetype=obj -o - | llvm-objdump -d -unwind-info -s - | FileCheck %s
+; RUN: llc < %s -mtriple x86_64-apple-darwin11 -mcpu corei7 -filetype=obj -o - | llvm-objdump -d -unwind-info -s - | FileCheck %s
 ; Regression test for http://llvm.org/bugs/show_bug.cgi?id=20800.
 
 ; ModuleID = 'asan_report.ii'
@@ -33,10 +33,10 @@ print_shadow_bytes.exit.i: ; preds = %print_shadow_bytes.exit.i, %0
   %iv.i = phi i64 [ -5, %0 ], [ %iv.next.i, %print_shadow_bytes.exit.i ]
   %reg15 = icmp eq i64 %iv.i, 0
   %.str..str1.i = select i1 %reg15, [3 x i8]* @.str, [3 x i8]* @.str1
-  %reg16 = getelementptr inbounds [3 x i8]* %.str..str1.i, i64 0, i64 0
+  %reg16 = getelementptr inbounds [3 x i8], [3 x i8]* %.str..str1.i, i64 0, i64 0
   %reg17 = shl i64 %iv.i, 1
   %reg19 = inttoptr i64 %reg17 to i8*
-  call void (i64*, i8*, ...)* @append(i64* %str.i, i8* getelementptr inbounds ([6 x i8]* @.str2, i64 0, i64 0), i8* %reg16, i8* %reg19)
+  call void (i64*, i8*, ...) @append(i64* %str.i, i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str2, i64 0, i64 0), i8* %reg16, i8* %reg19)
   %iv.next.i = add nsw i64 %iv.i, 0
   br label %print_shadow_bytes.exit.i
 }
diff --git a/test/CodeGen/X86/Atomics-64.ll b/test/CodeGen/X86/Atomics-64.ll
index c392e947407e..6d367a71d015 100644
--- a/test/CodeGen/X86/Atomics-64.ll
+++ b/test/CodeGen/X86/Atomics-64.ll
@@ -308,331 +308,331 @@ return:                                           ; preds = %entry
 
 define void @test_op_and_fetch() nounwind {
 entry:
-  %0 = load i8* @uc, align 1
+  %0 = load i8, i8* @uc, align 1
   %1 = zext i8 %0 to i32
   %2 = trunc i32 %1 to i8
   %3 = atomicrmw add i8* @sc, i8 %2 monotonic
   %4 = add i8 %3, %2
   store i8 %4, i8* @sc, align 1
-  %5 = load i8* @uc, align 1
+  %5 = load i8, i8* @uc, align 1
   %6 = zext i8 %5 to i32
   %7 = trunc i32 %6 to i8
   %8 = atomicrmw add i8* @uc, i8 %7 monotonic
   %9 = add i8 %8, %7
   store i8 %9, i8* @uc, align 1
-  %10 = load i8* @uc, align 1
+  %10 = load i8, i8* @uc, align 1
   %11 = zext i8 %10 to i32
   %12 = bitcast i8* bitcast (i16* @ss to i8*) to i16*
   %13 = trunc i32 %11 to i16
   %14 = atomicrmw add i16* %12, i16 %13 monotonic
   %15 = add i16 %14, %13
   store i16 %15, i16* @ss, align 2
-  %16 = load i8* @uc, align 1
+  %16 = load i8, i8* @uc, align 1
   %17 = zext i8 %16 to i32
   %18 = bitcast i8* bitcast (i16* @us to i8*) to i16*
   %19 = trunc i32 %17 to i16
   %20 = atomicrmw add i16* %18, i16 %19 monotonic
   %21 = add i16 %20, %19
   store i16 %21, i16* @us, align 2
-  %22 = load i8* @uc, align 1
+  %22 = load i8, i8* @uc, align 1
   %23 = zext i8 %22 to i32
   %24 = bitcast i8* bitcast (i32* @si to i8*) to i32*
   %25 = atomicrmw add i32* %24, i32 %23 monotonic
   %26 = add i32 %25, %23
   store i32 %26, i32* @si, align 4
-  %27 = load i8* @uc, align 1
+  %27 = load i8, i8* @uc, align 1
   %28 = zext i8 %27 to i32
   %29 = bitcast i8* bitcast (i32* @ui to i8*) to i32*
   %30 = atomicrmw add i32* %29, i32 %28 monotonic
   %31 = add i32 %30, %28
   store i32 %31, i32* @ui, align 4
-  %32 = load i8* @uc, align 1
+  %32 = load i8, i8* @uc, align 1
   %33 = zext i8 %32 to i64
   %34 = bitcast i8* bitcast (i64* @sl to i8*) to i64*
   %35 = atomicrmw add i64* %34, i64 %33 monotonic
   %36 = add i64 %35, %33
   store i64 %36, i64* @sl, align 8
-  %37 = load i8* @uc, align 1
+  %37 = load i8, i8* @uc, align 1
   %38 = zext i8 %37 to i64
   %39 = bitcast i8* bitcast (i64* @ul to i8*) to i64*
   %40 = atomicrmw add i64* %39, i64 %38 monotonic
   %41 = add i64 %40, %38
   store i64 %41, i64* @ul, align 8
-  %42 = load i8* @uc, align 1
+  %42 = load i8, i8* @uc, align 1
   %43 = zext i8 %42 to i64
   %44 = bitcast i8* bitcast (i64* @sll to i8*) to i64*
   %45 = atomicrmw add i64* %44, i64 %43 monotonic
   %46 = add i64 %45, %43
   store i64 %46, i64* @sll, align 8
-  %47 = load i8* @uc, align 1
+  %47 = load i8, i8* @uc, align 1
   %48 = zext i8 %47 to i64
   %49 = bitcast i8* bitcast (i64* @ull to i8*) to i64*
   %50 = atomicrmw add i64* %49, i64 %48 monotonic
   %51 = add i64 %50, %48
   store i64 %51, i64* @ull, align 8
-  %52 = load i8* @uc, align 1
+  %52 = load i8, i8* @uc, align 1
   %53 = zext i8 %52 to i32
   %54 = trunc i32 %53 to i8
   %55 = atomicrmw sub i8* @sc, i8 %54 monotonic
   %56 = sub i8 %55, %54
   store i8 %56, i8* @sc, align 1
-  %57 = load i8* @uc, align 1
+  %57 = load i8, i8* @uc, align 1
   %58 = zext i8 %57 to i32
   %59 = trunc i32 %58 to i8
   %60 = atomicrmw sub i8* @uc, i8 %59 monotonic
   %61 = sub i8 %60, %59
   store i8 %61, i8* @uc, align 1
-  %62 = load i8* @uc, align 1
+  %62 = load i8, i8* @uc, align 1
   %63 = zext i8 %62 to i32
   %64 = bitcast i8* bitcast (i16* @ss to i8*) to i16*
   %65 = trunc i32 %63 to i16
   %66 = atomicrmw sub i16* %64, i16 %65 monotonic
   %67 = sub i16 %66, %65
   store i16 %67, i16* @ss, align 2
-  %68 = load i8* @uc, align 1
+  %68 = load i8, i8* @uc, align 1
   %69 = zext i8 %68 to i32
   %70 = bitcast i8* bitcast (i16* @us to i8*) to i16*
   %71 = trunc i32 %69 to i16
   %72 = atomicrmw sub i16* %70, i16 %71 monotonic
   %73 = sub i16 %72, %71
   store i16 %73, i16* @us, align 2
-  %74 = load i8* @uc, align 1
+  %74 = load i8, i8* @uc, align 1
   %75 = zext i8 %74 to i32
   %76 = bitcast i8* bitcast (i32* @si to i8*) to i32*
   %77 = atomicrmw sub i32* %76, i32 %75 monotonic
   %78 = sub i32 %77, %75
   store i32 %78, i32* @si, align 4
-  %79 = load i8* @uc, align 1
+  %79 = load i8, i8* @uc, align 1
   %80 = zext i8 %79 to i32
   %81 = bitcast i8* bitcast (i32* @ui to i8*) to i32*
   %82 = atomicrmw sub i32* %81, i32 %80 monotonic
   %83 = sub i32 %82, %80
   store i32 %83, i32* @ui, align 4
-  %84 = load i8* @uc, align 1
+  %84 = load i8, i8* @uc, align 1
   %85 = zext i8 %84 to i64
   %86 = bitcast i8* bitcast (i64* @sl to i8*) to i64*
   %87 = atomicrmw sub i64* %86, i64 %85 monotonic
   %88 = sub i64 %87, %85
   store i64 %88, i64* @sl, align 8
-  %89 = load i8* @uc, align 1
+  %89 = load i8, i8* @uc, align 1
   %90 = zext i8 %89 to i64
   %91 = bitcast i8* bitcast (i64* @ul to i8*) to i64*
   %92 = atomicrmw sub i64* %91, i64 %90 monotonic
   %93 = sub i64 %92, %90
   store i64 %93, i64* @ul, align 8
-  %94 = load i8* @uc, align 1
+  %94 = load i8, i8* @uc, align 1
   %95 = zext i8 %94 to i64
   %96 = bitcast i8* bitcast (i64* @sll to i8*) to i64*
   %97 = atomicrmw sub i64* %96, i64 %95 monotonic
   %98 = sub i64 %97, %95
   store i64 %98, i64* @sll, align 8
-  %99 = load i8* @uc, align 1
+  %99 = load i8, i8* @uc, align 1
   %100 = zext i8 %99 to i64
   %101 = bitcast i8* bitcast (i64* @ull to i8*) to i64*
   %102 = atomicrmw sub i64* %101, i64 %100 monotonic
   %103 = sub i64 %102, %100
   store i64 %103, i64* @ull, align 8
-  %104 = load i8* @uc, align 1
+  %104 = load i8, i8* @uc, align 1
   %105 = zext i8 %104 to i32
   %106 = trunc i32 %105 to i8
   %107 = atomicrmw or i8* @sc, i8 %106 monotonic
   %108 = or i8 %107, %106
   store i8 %108, i8* @sc, align 1
-  %109 = load i8* @uc, align 1
+  %109 = load i8, i8* @uc, align 1
   %110 = zext i8 %109 to i32
   %111 = trunc i32 %110 to i8
   %112 = atomicrmw or i8* @uc, i8 %111 monotonic
   %113 = or i8 %112, %111
   store i8 %113, i8* @uc, align 1
-  %114 = load i8* @uc, align 1
+  %114 = load i8, i8* @uc, align 1
   %115 = zext i8 %114 to i32
   %116 = bitcast i8* bitcast (i16* @ss to i8*) to i16*
   %117 = trunc i32 %115 to i16
   %118 = atomicrmw or i16* %116, i16 %117 monotonic
   %119 = or i16 %118, %117
   store i16 %119, i16* @ss, align 2
-  %120 = load i8* @uc, align 1
+  %120 = load i8, i8* @uc, align 1
   %121 = zext i8 %120 to i32
   %122 = bitcast i8* bitcast (i16* @us to i8*) to i16*
   %123 = trunc i32 %121 to i16
   %124 = atomicrmw or i16* %122, i16 %123 monotonic
   %125 = or i16 %124, %123
   store i16 %125, i16* @us, align 2
-  %126 = load i8* @uc, align 1
+  %126 = load i8, i8* @uc, align 1
   %127 = zext i8 %126 to i32
   %128 = bitcast i8* bitcast (i32* @si to i8*) to i32*
   %129 = atomicrmw or i32* %128, i32 %127 monotonic
   %130 = or i32 %129, %127
   store i32 %130, i32* @si, align 4
-  %131 = load i8* @uc, align 1
+  %131 = load i8, i8* @uc, align 1
   %132 = zext i8 %131 to i32
   %133 = bitcast i8* bitcast (i32* @ui to i8*) to i32*
   %134 = atomicrmw or i32* %133, i32 %132 monotonic
   %135 = or i32 %134, %132
   store i32 %135, i32* @ui, align 4
-  %136 = load i8* @uc, align 1
+  %136 = load i8, i8* @uc, align 1
   %137 = zext i8 %136 to i64
   %138 = bitcast i8* bitcast (i64* @sl to i8*) to i64*
   %139 = atomicrmw or i64* %138, i64 %137 monotonic
   %140 = or i64 %139, %137
   store i64 %140, i64* @sl, align 8
-  %141 = load i8* @uc, align 1
+  %141 = load i8, i8* @uc, align 1
   %142 = zext i8 %141 to i64
   %143 = bitcast i8* bitcast (i64* @ul to i8*) to i64*
   %144 = atomicrmw or i64* %143, i64 %142 monotonic
   %145 = or i64 %144, %142
   store i64 %145, i64* @ul, align 8
-  %146 = load i8* @uc, align 1
+  %146 = load i8, i8* @uc, align 1
   %147 = zext i8 %146 to i64
   %148 = bitcast i8* bitcast (i64* @sll to i8*) to i64*
   %149 = atomicrmw or i64* %148, i64 %147 monotonic
   %150 = or i64 %149, %147
   store i64 %150, i64* @sll, align 8
-  %151 = load i8* @uc, align 1
+  %151 = load i8, i8* @uc, align 1
   %152 = zext i8 %151 to i64
   %153 = bitcast i8* bitcast (i64* @ull to i8*) to i64*
   %154 = atomicrmw or i64* %153, i64 %152 monotonic
   %155 = or i64 %154, %152
   store i64 %155, i64* @ull, align 8
-  %156 = load i8* @uc, align 1
+  %156 = load i8, i8* @uc, align 1
   %157 = zext i8 %156 to i32
   %158 = trunc i32 %157 to i8
   %159 = atomicrmw xor i8* @sc, i8 %158 monotonic
   %160 = xor i8 %159, %158
   store i8 %160, i8* @sc, align 1
-  %161 = load i8* @uc, align 1
+  %161 = load i8, i8* @uc, align 1
   %162 = zext i8 %161 to i32
   %163 = trunc i32 %162 to i8
   %164 = atomicrmw xor i8* @uc, i8 %163 monotonic
   %165 = xor i8 %164, %163
   store i8 %165, i8* @uc, align 1
-  %166 = load i8* @uc, align 1
+  %166 = load i8, i8* @uc, align 1
   %167 = zext i8 %166 to i32
   %168 = bitcast i8* bitcast (i16* @ss to i8*) to i16*
   %169 = trunc i32 %167 to i16
   %170 = atomicrmw xor i16* %168, i16 %169 monotonic
   %171 = xor i16 %170, %169
   store i16 %171, i16* @ss, align 2
-  %172 = load i8* @uc, align 1
+  %172 = load i8, i8* @uc, align 1
   %173 = zext i8 %172 to i32
   %174 = bitcast i8* bitcast (i16* @us to i8*) to i16*
   %175 = trunc i32 %173 to i16
   %176 = atomicrmw xor i16* %174, i16 %175 monotonic
   %177 = xor i16 %176, %175
   store i16 %177, i16* @us, align 2
-  %178 = load i8* @uc, align 1
+  %178 = load i8, i8* @uc, align 1
   %179 = zext i8 %178 to i32
   %180 = bitcast i8* bitcast (i32* @si to i8*) to i32*
   %181 = atomicrmw xor i32* %180, i32 %179 monotonic
   %182 = xor i32 %181, %179
   store i32 %182, i32* @si, align 4
-  %183 = load i8* @uc, align 1
+  %183 = load i8, i8* @uc, align 1
   %184 = zext i8 %183 to i32
   %185 = bitcast i8* bitcast (i32* @ui to i8*) to i32*
   %186 = atomicrmw xor i32* %185, i32 %184 monotonic
   %187 = xor i32 %186, %184
   store i32 %187, i32* @ui, align 4
-  %188 = load i8* @uc, align 1
+  %188 = load i8, i8* @uc, align 1
   %189 = zext i8 %188 to i64
   %190 = bitcast i8* bitcast (i64* @sl to i8*) to i64*
   %191 = atomicrmw xor i64* %190, i64 %189 monotonic
   %192 = xor i64 %191, %189
   store i64 %192, i64* @sl, align 8
-  %193 = load i8* @uc, align 1
+  %193 = load i8, i8* @uc, align 1
   %194 = zext i8 %193 to i64
   %195 = bitcast i8* bitcast (i64* @ul to i8*) to i64*
   %196 = atomicrmw xor i64* %195, i64 %194 monotonic
   %197 = xor i64 %196, %194
   store i64 %197, i64* @ul, align 8
-  %198 = load i8* @uc, align 1
+  %198 = load i8, i8* @uc, align 1
   %199 = zext i8 %198 to i64
   %200 = bitcast i8* bitcast (i64* @sll to i8*) to i64*
   %201 = atomicrmw xor i64* %200, i64 %199 monotonic
   %202 = xor i64 %201, %199
   store i64 %202, i64* @sll, align 8
-  %203 = load i8* @uc, align 1
+  %203 = load i8, i8* @uc, align 1
   %204 = zext i8 %203 to i64
   %205 = bitcast i8* bitcast (i64* @ull to i8*) to i64*
   %206 = atomicrmw xor i64* %205, i64 %204 monotonic
   %207 = xor i64 %206, %204
   store i64 %207, i64* @ull, align 8
-  %208 = load i8* @uc, align 1
+  %208 = load i8, i8* @uc, align 1
   %209 = zext i8 %208 to i32
   %210 = trunc i32 %209 to i8
   %211 = atomicrmw and i8* @sc, i8 %210 monotonic
   %212 = and i8 %211, %210
   store i8 %212, i8* @sc, align 1
-  %213 = load i8* @uc, align 1
+  %213 = load i8, i8* @uc, align 1
   %214 = zext i8 %213 to i32
   %215 = trunc i32 %214 to i8
   %216 = atomicrmw and i8* @uc, i8 %215 monotonic
   %217 = and i8 %216, %215
   store i8 %217, i8* @uc, align 1
-  %218 = load i8* @uc, align 1
+  %218 = load i8, i8* @uc, align 1
   %219 = zext i8 %218 to i32
   %220 = bitcast i8* bitcast (i16* @ss to i8*) to i16*
   %221 = trunc i32 %219 to i16
   %222 = atomicrmw and i16* %220, i16 %221 monotonic
   %223 = and i16 %222, %221
   store i16 %223, i16* @ss, align 2
-  %224 = load i8* @uc, align 1
+  %224 = load i8, i8* @uc, align 1
   %225 = zext i8 %224 to i32
   %226 = bitcast i8* bitcast (i16* @us to i8*) to i16*
   %227 = trunc i32 %225 to i16
   %228 = atomicrmw and i16* %226, i16 %227 monotonic
   %229 = and i16 %228, %227
   store i16 %229, i16* @us, align 2
-  %230 = load i8* @uc, align 1
+  %230 = load i8, i8* @uc, align 1
   %231 = zext i8 %230 to i32
   %232 = bitcast i8* bitcast (i32* @si to i8*) to i32*
   %233 = atomicrmw and i32* %232, i32 %231 monotonic
   %234 = and i32 %233, %231
   store i32 %234, i32* @si, align 4
-  %235 = load i8* @uc, align 1
+  %235 = load i8, i8* @uc, align 1
   %236 = zext i8 %235 to i32
   %237 = bitcast i8* bitcast (i32* @ui to i8*) to i32*
   %238 = atomicrmw and i32* %237, i32 %236 monotonic
   %239 = and i32 %238, %236
   store i32 %239, i32* @ui, align 4
-  %240 = load i8* @uc, align 1
+  %240 = load i8, i8* @uc, align 1
   %241 = zext i8 %240 to i64
   %242 = bitcast i8* bitcast (i64* @sl to i8*) to i64*
   %243 = atomicrmw and i64* %242, i64 %241 monotonic
   %244 = and i64 %243, %241
   store i64 %244, i64* @sl, align 8
-  %245 = load i8* @uc, align 1
+  %245 = load i8, i8* @uc, align 1
   %246 = zext i8 %245 to i64
   %247 = bitcast i8* bitcast (i64* @ul to i8*) to i64*
   %248 = atomicrmw and i64* %247, i64 %246 monotonic
   %249 = and i64 %248, %246
   store i64 %249, i64* @ul, align 8
-  %250 = load i8* @uc, align 1
+  %250 = load i8, i8* @uc, align 1
   %251 = zext i8 %250 to i64
   %252 = bitcast i8* bitcast (i64* @sll to i8*) to i64*
   %253 = atomicrmw and i64* %252, i64 %251 monotonic
   %254 = and i64 %253, %251
   store i64 %254, i64* @sll, align 8
-  %255 = load i8* @uc, align 1
+  %255 = load i8, i8* @uc, align 1
   %256 = zext i8 %255 to i64
   %257 = bitcast i8* bitcast (i64* @ull to i8*) to i64*
   %258 = atomicrmw and i64* %257, i64 %256 monotonic
   %259 = and i64 %258, %256
   store i64 %259, i64* @ull, align 8
-  %260 = load i8* @uc, align 1
+  %260 = load i8, i8* @uc, align 1
   %261 = zext i8 %260 to i32
   %262 = trunc i32 %261 to i8
   %263 = atomicrmw nand i8* @sc, i8 %262 monotonic
   %264 = xor i8 %263, -1
   %265 = and i8 %264, %262
   store i8 %265, i8* @sc, align 1
-  %266 = load i8* @uc, align 1
+  %266 = load i8, i8* @uc, align 1
   %267 = zext i8 %266 to i32
   %268 = trunc i32 %267 to i8
   %269 = atomicrmw nand i8* @uc, i8 %268 monotonic
   %270 = xor i8 %269, -1
   %271 = and i8 %270, %268
   store i8 %271, i8* @uc, align 1
-  %272 = load i8* @uc, align 1
+  %272 = load i8, i8* @uc, align 1
   %273 = zext i8 %272 to i32
   %274 = bitcast i8* bitcast (i16* @ss to i8*) to i16*
   %275 = trunc i32 %273 to i16
@@ -640,7 +640,7 @@ entry:
   %277 = xor i16 %276, -1
   %278 = and i16 %277, %275
   store i16 %278, i16* @ss, align 2
-  %279 = load i8* @uc, align 1
+  %279 = load i8, i8* @uc, align 1
   %280 = zext i8 %279 to i32
   %281 = bitcast i8* bitcast (i16* @us to i8*) to i16*
   %282 = trunc i32 %280 to i16
@@ -648,42 +648,42 @@ entry:
   %284 = xor i16 %283, -1
   %285 = and i16 %284, %282
   store i16 %285, i16* @us, align 2
-  %286 = load i8* @uc, align 1
+  %286 = load i8, i8* @uc, align 1
   %287 = zext i8 %286 to i32
   %288 = bitcast i8* bitcast (i32* @si to i8*) to i32*
   %289 = atomicrmw nand i32* %288, i32 %287 monotonic
   %290 = xor i32 %289, -1
   %291 = and i32 %290, %287
   store i32 %291, i32* @si, align 4
-  %292 = load i8* @uc, align 1
+  %292 = load i8, i8* @uc, align 1
   %293 = zext i8 %292 to i32
   %294 = bitcast i8* bitcast (i32* @ui to i8*) to i32*
   %295 = atomicrmw nand i32* %294, i32 %293 monotonic
   %296 = xor i32 %295, -1
   %297 = and i32 %296, %293
   store i32 %297, i32* @ui, align 4
-  %298 = load i8* @uc, align 1
+  %298 = load i8, i8* @uc, align 1
   %299 = zext i8 %298 to i64
   %300 = bitcast i8* bitcast (i64* @sl to i8*) to i64*
   %301 = atomicrmw nand i64* %300, i64 %299 monotonic
   %302 = xor i64 %301, -1
   %303 = and i64 %302, %299
   store i64 %303, i64* @sl, align 8
-  %304 = load i8* @uc, align 1
+  %304 = load i8, i8* @uc, align 1
   %305 = zext i8 %304 to i64
   %306 = bitcast i8* bitcast (i64* @ul to i8*) to i64*
   %307 = atomicrmw nand i64* %306, i64 %305 monotonic
   %308 = xor i64 %307, -1
   %309 = and i64 %308, %305
   store i64 %309, i64* @ul, align 8
-  %310 = load i8* @uc, align 1
+  %310 = load i8, i8* @uc, align 1
   %311 = zext i8 %310 to i64
   %312 = bitcast i8* bitcast (i64* @sll to i8*) to i64*
   %313 = atomicrmw nand i64* %312, i64 %311 monotonic
   %314 = xor i64 %313, -1
   %315 = and i64 %314, %311
   store i64 %315, i64* @sll, align 8
-  %316 = load i8* @uc, align 1
+  %316 = load i8, i8* @uc, align 1
   %317 = zext i8 %316 to i64
   %318 = bitcast i8* bitcast (i64* @ull to i8*) to i64*
   %319 = atomicrmw nand i64* %318, i64 %317 monotonic
@@ -698,28 +698,28 @@ return:                                           ; preds = %entry
 
 define void @test_compare_and_swap() nounwind {
 entry:
-  %0 = load i8* @sc, align 1
+  %0 = load i8, i8* @sc, align 1
   %1 = zext i8 %0 to i32
-  %2 = load i8* @uc, align 1
+  %2 = load i8, i8* @uc, align 1
   %3 = zext i8 %2 to i32
   %4 = trunc i32 %3 to i8
   %5 = trunc i32 %1 to i8
   %pair6 = cmpxchg i8* @sc, i8 %4, i8 %5 monotonic monotonic
   %6 = extractvalue { i8, i1 } %pair6, 0
   store i8 %6, i8* @sc, align 1
-  %7 = load i8* @sc, align 1
+  %7 = load i8, i8* @sc, align 1
   %8 = zext i8 %7 to i32
-  %9 = load i8* @uc, align 1
+  %9 = load i8, i8* @uc, align 1
   %10 = zext i8 %9 to i32
   %11 = trunc i32 %10 to i8
   %12 = trunc i32 %8 to i8
   %pair13 = cmpxchg i8* @uc, i8 %11, i8 %12 monotonic monotonic
   %13 = extractvalue { i8, i1 } %pair13, 0
   store i8 %13, i8* @uc, align 1
-  %14 = load i8* @sc, align 1
+  %14 = load i8, i8* @sc, align 1
   %15 = sext i8 %14 to i16
   %16 = zext i16 %15 to i32
-  %17 = load i8* @uc, align 1
+  %17 = load i8, i8* @uc, align 1
   %18 = zext i8 %17 to i32
   %19 = bitcast i8* bitcast (i16* @ss to i8*) to i16*
   %20 = trunc i32 %18 to i16
@@ -727,10 +727,10 @@ entry:
   %pair22 = cmpxchg i16* %19, i16 %20, i16 %21 monotonic monotonic
   %22 = extractvalue { i16, i1 } %pair22, 0
   store i16 %22, i16* @ss, align 2
-  %23 = load i8* @sc, align 1
+  %23 = load i8, i8* @sc, align 1
   %24 = sext i8 %23 to i16
   %25 = zext i16 %24 to i32
-  %26 = load i8* @uc, align 1
+  %26 = load i8, i8* @uc, align 1
   %27 = zext i8 %26 to i32
   %28 = bitcast i8* bitcast (i16* @us to i8*) to i16*
   %29 = trunc i32 %27 to i16
@@ -738,57 +738,57 @@ entry:
   %pair31 = cmpxchg i16* %28, i16 %29, i16 %30 monotonic monotonic
   %31 = extractvalue { i16, i1 } %pair31, 0
   store i16 %31, i16* @us, align 2
-  %32 = load i8* @sc, align 1
+  %32 = load i8, i8* @sc, align 1
   %33 = sext i8 %32 to i32
-  %34 = load i8* @uc, align 1
+  %34 = load i8, i8* @uc, align 1
   %35 = zext i8 %34 to i32
   %36 = bitcast i8* bitcast (i32* @si to i8*) to i32*
   %pair37 = cmpxchg i32* %36, i32 %35, i32 %33 monotonic monotonic
   %37 = extractvalue { i32, i1 } %pair37, 0
   store i32 %37, i32* @si, align 4
-  %38 = load i8* @sc, align 1
+  %38 = load i8, i8* @sc, align 1
   %39 = sext i8 %38 to i32
-  %40 = load i8* @uc, align 1
+  %40 = load i8, i8* @uc, align 1
   %41 = zext i8 %40 to i32
   %42 = bitcast i8* bitcast (i32* @ui to i8*) to i32*
   %pair43 = cmpxchg i32* %42, i32 %41, i32 %39 monotonic monotonic
   %43 = extractvalue { i32, i1 } %pair43, 0
   store i32 %43, i32* @ui, align 4
-  %44 = load i8* @sc, align 1
+  %44 = load i8, i8* @sc, align 1
   %45 = sext i8 %44 to i64
-  %46 = load i8* @uc, align 1
+  %46 = load i8, i8* @uc, align 1
   %47 = zext i8 %46 to i64
   %48 = bitcast i8* bitcast (i64* @sl to i8*) to i64*
   %pair49 = cmpxchg i64* %48, i64 %47, i64 %45 monotonic monotonic
   %49 = extractvalue { i64, i1 } %pair49, 0
   store i64 %49, i64* @sl, align 8
-  %50 = load i8* @sc, align 1
+  %50 = load i8, i8* @sc, align 1
   %51 = sext i8 %50 to i64
-  %52 = load i8* @uc, align 1
+  %52 = load i8, i8* @uc, align 1
   %53 = zext i8 %52 to i64
   %54 = bitcast i8* bitcast (i64* @ul to i8*) to i64*
   %pair55 = cmpxchg i64* %54, i64 %53, i64 %51 monotonic monotonic
   %55 = extractvalue { i64, i1 } %pair55, 0
   store i64 %55, i64* @ul, align 8
-  %56 = load i8* @sc, align 1
+  %56 = load i8, i8* @sc, align 1
   %57 = sext i8 %56 to i64
-  %58 = load i8* @uc, align 1
+  %58 = load i8, i8* @uc, align 1
   %59 = zext i8 %58 to i64
   %60 = bitcast i8* bitcast (i64* @sll to i8*) to i64*
   %pair61 = cmpxchg i64* %60, i64 %59, i64 %57 monotonic monotonic
   %61 = extractvalue { i64, i1 } %pair61, 0
   store i64 %61, i64* @sll, align 8
-  %62 = load i8* @sc, align 1
+  %62 = load i8, i8* @sc, align 1
   %63 = sext i8 %62 to i64
-  %64 = load i8* @uc, align 1
+  %64 = load i8, i8* @uc, align 1
   %65 = zext i8 %64 to i64
   %66 = bitcast i8* bitcast (i64* @ull to i8*) to i64*
   %pair67 = cmpxchg i64* %66, i64 %65, i64 %63 monotonic monotonic
   %67 = extractvalue { i64, i1 } %pair67, 0
   store i64 %67, i64* @ull, align 8
-  %68 = load i8* @sc, align 1
+  %68 = load i8, i8* @sc, align 1
   %69 = zext i8 %68 to i32
-  %70 = load i8* @uc, align 1
+  %70 = load i8, i8* @uc, align 1
   %71 = zext i8 %70 to i32
   %72 = trunc i32 %71 to i8
   %73 = trunc i32 %69 to i8
@@ -798,9 +798,9 @@ entry:
   %76 = zext i1 %75 to i8
   %77 = zext i8 %76 to i32
   store i32 %77, i32* @ui, align 4
-  %78 = load i8* @sc, align 1
+  %78 = load i8, i8* @sc, align 1
   %79 = zext i8 %78 to i32
-  %80 = load i8* @uc, align 1
+  %80 = load i8, i8* @uc, align 1
   %81 = zext i8 %80 to i32
   %82 = trunc i32 %81 to i8
   %83 = trunc i32 %79 to i8
@@ -810,10 +810,10 @@ entry:
   %86 = zext i1 %85 to i8
   %87 = zext i8 %86 to i32
   store i32 %87, i32* @ui, align 4
-  %88 = load i8* @sc, align 1
+  %88 = load i8, i8* @sc, align 1
   %89 = sext i8 %88 to i16
   %90 = zext i16 %89 to i32
-  %91 = load i8* @uc, align 1
+  %91 = load i8, i8* @uc, align 1
   %92 = zext i8 %91 to i32
   %93 = trunc i32 %92 to i8
   %94 = trunc i32 %90 to i8
@@ -823,10 +823,10 @@ entry:
   %97 = zext i1 %96 to i8
   %98 = zext i8 %97 to i32
   store i32 %98, i32* @ui, align 4
-  %99 = load i8* @sc, align 1
+  %99 = load i8, i8* @sc, align 1
   %100 = sext i8 %99 to i16
   %101 = zext i16 %100 to i32
-  %102 = load i8* @uc, align 1
+  %102 = load i8, i8* @uc, align 1
   %103 = zext i8 %102 to i32
   %104 = trunc i32 %103 to i8
   %105 = trunc i32 %101 to i8
@@ -836,9 +836,9 @@ entry:
   %108 = zext i1 %107 to i8
   %109 = zext i8 %108 to i32
   store i32 %109, i32* @ui, align 4
-  %110 = load i8* @sc, align 1
+  %110 = load i8, i8* @sc, align 1
   %111 = sext i8 %110 to i32
-  %112 = load i8* @uc, align 1
+  %112 = load i8, i8* @uc, align 1
   %113 = zext i8 %112 to i32
   %114 = trunc i32 %113 to i8
   %115 = trunc i32 %111 to i8
@@ -848,9 +848,9 @@ entry:
   %118 = zext i1 %117 to i8
   %119 = zext i8 %118 to i32
   store i32 %119, i32* @ui, align 4
-  %120 = load i8* @sc, align 1
+  %120 = load i8, i8* @sc, align 1
   %121 = sext i8 %120 to i32
-  %122 = load i8* @uc, align 1
+  %122 = load i8, i8* @uc, align 1
   %123 = zext i8 %122 to i32
   %124 = trunc i32 %123 to i8
   %125 = trunc i32 %121 to i8
@@ -860,9 +860,9 @@ entry:
   %128 = zext i1 %127 to i8
   %129 = zext i8 %128 to i32
   store i32 %129, i32* @ui, align 4
-  %130 = load i8* @sc, align 1
+  %130 = load i8, i8* @sc, align 1
   %131 = sext i8 %130 to i64
-  %132 = load i8* @uc, align 1
+  %132 = load i8, i8* @uc, align 1
   %133 = zext i8 %132 to i64
   %134 = trunc i64 %133 to i8
   %135 = trunc i64 %131 to i8
@@ -872,9 +872,9 @@ entry:
   %138 = zext i1 %137 to i8
   %139 = zext i8 %138 to i32
   store i32 %139, i32* @ui, align 4
-  %140 = load i8* @sc, align 1
+  %140 = load i8, i8* @sc, align 1
   %141 = sext i8 %140 to i64
-  %142 = load i8* @uc, align 1
+  %142 = load i8, i8* @uc, align 1
   %143 = zext i8 %142 to i64
   %144 = trunc i64 %143 to i8
   %145 = trunc i64 %141 to i8
@@ -884,9 +884,9 @@ entry:
   %148 = zext i1 %147 to i8
   %149 = zext i8 %148 to i32
   store i32 %149, i32* @ui, align 4
-  %150 = load i8* @sc, align 1
+  %150 = load i8, i8* @sc, align 1
   %151 = sext i8 %150 to i64
-  %152 = load i8* @uc, align 1
+  %152 = load i8, i8* @uc, align 1
   %153 = zext i8 %152 to i64
   %154 = trunc i64 %153 to i8
   %155 = trunc i64 %151 to i8
@@ -896,9 +896,9 @@ entry:
   %158 = zext i1 %157 to i8
   %159 = zext i8 %158 to i32
   store i32 %159, i32* @ui, align 4
-  %160 = load i8* @sc, align 1
+  %160 = load i8, i8* @sc, align 1
   %161 = sext i8 %160 to i64
-  %162 = load i8* @uc, align 1
+  %162 = load i8, i8* @uc, align 1
   %163 = zext i8 %162 to i64
   %164 = trunc i64 %163 to i8
   %165 = trunc i64 %161 to i8
diff --git a/test/CodeGen/X86/GC/alloc_loop.ll b/test/CodeGen/X86/GC/alloc_loop.ll
index fb78ba2cd10b..2a505e80aac8 100644
--- a/test/CodeGen/X86/GC/alloc_loop.ll
+++ b/test/CodeGen/X86/GC/alloc_loop.ll
@@ -31,8 +31,8 @@ entry:
 	store i8** %tmp.2, i8*** %B
 
 	;; *B = A;
-	%B.1 = load i8*** %B
-	%A.1 = load i8** %A
+	%B.1 = load i8**, i8*** %B
+	%A.1 = load i8*, i8** %A
 	call void @llvm.gcwrite(i8* %A.1, i8* %B.upgrd.1, i8** %B.1)
 	
 	br label %AllocLoop
diff --git a/test/CodeGen/X86/GC/argpromotion.ll b/test/CodeGen/X86/GC/argpromotion.ll
index c63ce222b869..37baf325007d 100644
--- a/test/CodeGen/X86/GC/argpromotion.ll
+++ b/test/CodeGen/X86/GC/argpromotion.ll
@@ -14,6 +14,6 @@ define internal i32 @f(i32* %xp) gc "example" {
 entry:
 	%var = alloca i8*
 	call void @llvm.gcroot(i8** %var, i8* null)
-	%x = load i32* %xp
+	%x = load i32, i32* %xp
 	ret i32 %x
 }
diff --git a/test/CodeGen/X86/GC/badreadproto.ll b/test/CodeGen/X86/GC/badreadproto.ll
index 4fe90b90833a..37672f804357 100644
--- a/test/CodeGen/X86/GC/badreadproto.ll
+++ b/test/CodeGen/X86/GC/badreadproto.ll
@@ -7,7 +7,7 @@
 declare %list* @llvm.gcread(%list*, %list**)
 
 define %list* @tl(%list* %l) gc "example" {
-	%hd.ptr = getelementptr %list* %l, i32 0, i32 0
+	%hd.ptr = getelementptr %list, %list* %l, i32 0, i32 0
 	%hd = call %list* @llvm.gcread(%list* %l, %list** %hd.ptr)
 	ret i32 %tmp
 }
diff --git a/test/CodeGen/X86/GC/badwriteproto.ll b/test/CodeGen/X86/GC/badwriteproto.ll
index be81f842672e..2544e40f81ff 100644
--- a/test/CodeGen/X86/GC/badwriteproto.ll
+++ b/test/CodeGen/X86/GC/badwriteproto.ll
@@ -7,13 +7,13 @@
 declare void @llvm.gcwrite(%list*, %list*, %list**)
 
 define %list* @cons(i32 %hd, %list* %tl) gc "example" {
-	%tmp = call i8* @gcalloc(i32 bitcast(%list* getelementptr(%list* null, i32 1) to i32))
+	%tmp = call i8* @gcalloc(i32 bitcast(%list* getelementptr(%list, %list* null, i32 1) to i32))
 	%cell = bitcast i8* %tmp to %list*
 	
-	%hd.ptr = getelementptr %list* %cell, i32 0, i32 0
+	%hd.ptr = getelementptr %list, %list* %cell, i32 0, i32 0
 	store i32 %hd, i32* %hd.ptr
 	
-	%tl.ptr = getelementptr %list* %cell, i32 0, i32 0
+	%tl.ptr = getelementptr %list, %list* %cell, i32 0, i32 0
 	call void @llvm.gcwrite(%list* %tl, %list* %cell, %list** %tl.ptr)
 	
 	ret %cell.2
diff --git a/test/CodeGen/X86/GC/dynamic-frame-size.ll b/test/CodeGen/X86/GC/dynamic-frame-size.ll
new file mode 100644
index 000000000000..a3583d46a29a
--- /dev/null
+++ b/test/CodeGen/X86/GC/dynamic-frame-size.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnu"
+
+declare void @use(<4 x i8*>*)
+
+; Test that a frame which requires dynamic relocation produces a stack map
+; with a size of UINT64_MAX.
+define void @test(i8* %ptr) gc "erlang" {
+   ; 32 byte alignment (for the alloca) is larger than the default
+   ; 16 byte alignment
+   %slot = alloca <4 x i8*>
+   call void @use(<4 x i8*>* %slot);
+   ret void
+}
+
+; CHECK: .note.gc
+; CHECK-NEXT: .align 8
+; safe point count
+; CHECK .short	1
+; CHECK .long	.Ltmp0
+; stack frame size (in words)
+; CHECK .short	-1
+; stack arity (arguments on the stack)
+; CHECK .short	0
+; live root count
+; CHECK .short	0
+
diff --git a/test/CodeGen/X86/GC/inline.ll b/test/CodeGen/X86/GC/inline.ll
index 9da33aef8dd3..9d74c1faa39d 100644
--- a/test/CodeGen/X86/GC/inline.ll
+++ b/test/CodeGen/X86/GC/inline.ll
@@ -15,8 +15,8 @@ define internal i32 @g() gc "example" {
 	%obj = call %IntArray* @h( )		; <%IntArray*> [#uses=2]
 	%obj.2 = bitcast %IntArray* %obj to i8*		; <i8*> [#uses=1]
 	store i8* %obj.2, i8** %root
-	%Length.ptr = getelementptr %IntArray* %obj, i32 0, i32 0		; <i32*> [#uses=1]
-	%Length = load i32* %Length.ptr		; <i32> [#uses=1]
+	%Length.ptr = getelementptr %IntArray, %IntArray* %obj, i32 0, i32 0		; <i32*> [#uses=1]
+	%Length = load i32, i32* %Length.ptr		; <i32> [#uses=1]
 	ret i32 %Length
 }
 
diff --git a/test/CodeGen/X86/GC/inline2.ll b/test/CodeGen/X86/GC/inline2.ll
index 15947056ee39..034c985a1df4 100644
--- a/test/CodeGen/X86/GC/inline2.ll
+++ b/test/CodeGen/X86/GC/inline2.ll
@@ -16,8 +16,8 @@ define internal i32 @g() gc "example" {
 	%obj = call %IntArray* @h( )		; <%IntArray*> [#uses=2]
 	%obj.2 = bitcast %IntArray* %obj to i8*		; <i8*> [#uses=1]
 	store i8* %obj.2, i8** %root
-	%Length.ptr = getelementptr %IntArray* %obj, i32 0, i32 0		; <i32*> [#uses=1]
-	%Length = load i32* %Length.ptr		; <i32> [#uses=1]
+	%Length.ptr = getelementptr %IntArray, %IntArray* %obj, i32 0, i32 0		; <i32*> [#uses=1]
+	%Length = load i32, i32* %Length.ptr		; <i32> [#uses=1]
 	ret i32 %Length
 }
 
diff --git a/test/CodeGen/X86/MachineBranchProb.ll b/test/CodeGen/X86/MachineBranchProb.ll
index cf41ef2ea3ad..408c6b9151c3 100644
--- a/test/CodeGen/X86/MachineBranchProb.ll
+++ b/test/CodeGen/X86/MachineBranchProb.ll
@@ -13,14 +13,14 @@ for.cond2:                                        ; preds = %for.inc, %for.cond
   %i.1 = phi i32 [ %inc19, %for.inc ], [ 0, %for.cond ]
   %bit.0 = phi i32 [ %shl, %for.inc ], [ 1, %for.cond ]
   %tobool = icmp eq i32 %bit.0, 0
-  %v3 = load i32* @max_regno, align 4
+  %v3 = load i32, i32* @max_regno, align 4
   %cmp4 = icmp eq i32 %i.1, %v3
   %or.cond = or i1 %tobool, %cmp4
   br i1 %or.cond, label %for.inc20, label %for.inc, !prof !0
 ; CHECK: BB#1: derived from LLVM BB %for.cond2
-; CHECK: Successors according to CFG: BB#3(56008718) BB#4(2203492365)
+; CHECK: Successors according to CFG: BB#3(56008718) BB#4(3615818718)
 ; CHECK: BB#4: derived from LLVM BB %for.cond2
-; CHECK: Successors according to CFG: BB#3(112017436) BB#2(4294967294)
+; CHECK: Successors according to CFG: BB#3(56008718) BB#2(3559810000)
 
 for.inc:                                          ; preds = %for.cond2
   %shl = shl i32 %bit.0, 1
diff --git a/test/CodeGen/X86/MachineSink-DbgValue.ll b/test/CodeGen/X86/MachineSink-DbgValue.ll
index 3a2c58f97e8c..6f057c5f18e6 100644
--- a/test/CodeGen/X86/MachineSink-DbgValue.ll
+++ b/test/CodeGen/X86/MachineSink-DbgValue.ll
@@ -4,10 +4,10 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-apple-macosx10.7.0"
 
 define i32 @foo(i32 %i, i32* nocapture %c) nounwind uwtable readonly ssp {
-  tail call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !6, metadata !{!"0x102"}), !dbg !12
-  %ab = load i32* %c, align 1, !dbg !14
-  tail call void @llvm.dbg.value(metadata i32* %c, i64 0, metadata !7, metadata !{!"0x102"}), !dbg !13
-  tail call void @llvm.dbg.value(metadata i32 %ab, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !14
+  tail call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !6, metadata !DIExpression()), !dbg !12
+  %ab = load i32, i32* %c, align 1, !dbg !14
+  tail call void @llvm.dbg.value(metadata i32* %c, i64 0, metadata !7, metadata !DIExpression()), !dbg !13
+  tail call void @llvm.dbg.value(metadata i32 %ab, i64 0, metadata !10, metadata !DIExpression()), !dbg !14
   %cd = icmp eq i32 %i, 42, !dbg !15
   br i1 %cd, label %bb1, label %bb2, !dbg !15
 
@@ -28,26 +28,26 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!22}
 
-!0 = !{!"0x11\0012\00Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)\001\00\000\00\001", !20, !21, !21, !18, null,  null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"0x2e\00foo\00foo\00\002\000\001\000\006\00256\001\000", !20, !2, !3, null, i32 (i32, i32*)* @foo, null, null, !19} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 0] [foo]
-!2 = !{!"0x29", !20} ; [ DW_TAG_file_type ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !20, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", isOptimized: true, emissionKind: 1, file: !20, enums: !21, retainedTypes: !21, subprograms: !18, imports:  null)
+!1 = !DISubprogram(name: "foo", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !20, scope: !2, type: !3, function: i32 (i32, i32*)* @foo, variables: !19)
+!2 = !DIFile(filename: "a.c", directory: "/private/tmp")
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ]
-!6 = !{!"0x101\00i\0016777218\000", !1, !2, !5} ; [ DW_TAG_arg_variable ]
-!7 = !{!"0x101\00c\0033554434\000", !1, !2, !8} ; [ DW_TAG_arg_variable ]
-!8 = !{!"0xf\00\000\0064\0064\000\000", null, !0, !9} ; [ DW_TAG_pointer_type ]
-!9 = !{!"0x24\00char\000\008\008\000\000\006", null, !0} ; [ DW_TAG_base_type ]
-!10 = !{!"0x100\00a\003\000", !11, !2, !9} ; [ DW_TAG_auto_variable ]
-!11 = !{!"0xb\002\0025\000", !20, !1} ; [ DW_TAG_lexical_block ]
-!12 = !MDLocation(line: 2, column: 13, scope: !1)
-!13 = !MDLocation(line: 2, column: 22, scope: !1)
-!14 = !MDLocation(line: 3, column: 14, scope: !11)
-!15 = !MDLocation(line: 4, column: 3, scope: !11)
-!16 = !MDLocation(line: 5, column: 5, scope: !11)
-!17 = !MDLocation(line: 7, column: 1, scope: !11)
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 2, arg: 1, scope: !1, file: !2, type: !5)
+!7 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 2, arg: 2, scope: !1, file: !2, type: !8)
+!8 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, scope: !0, baseType: !9)
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 3, scope: !11, file: !2, type: !9)
+!11 = distinct !DILexicalBlock(line: 2, column: 25, file: !20, scope: !1)
+!12 = !DILocation(line: 2, column: 13, scope: !1)
+!13 = !DILocation(line: 2, column: 22, scope: !1)
+!14 = !DILocation(line: 3, column: 14, scope: !11)
+!15 = !DILocation(line: 4, column: 3, scope: !11)
+!16 = !DILocation(line: 5, column: 5, scope: !11)
+!17 = !DILocation(line: 7, column: 1, scope: !11)
 !18 = !{!1}
 !19 = !{!6, !7, !10}
-!20 = !{!"a.c", !"/private/tmp"}
-!21 = !{i32 0}
-!22 = !{i32 1, !"Debug Info Version", i32 2}
+!20 = !DIFile(filename: "a.c", directory: "/private/tmp")
+!21 = !{}
+!22 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/MachineSink-eflags.ll b/test/CodeGen/X86/MachineSink-eflags.ll
index 5b8c7b205279..4e52c8c5f7d0 100644
--- a/test/CodeGen/X86/MachineSink-eflags.ll
+++ b/test/CodeGen/X86/MachineSink-eflags.ll
@@ -16,18 +16,18 @@ entry:
  %i2 = alloca i8*, align 8
  %b.i = alloca [16 x <2 x double>], align 16
  %conv = bitcast i8* %_stubArgs to i32*
- %tmp1 = load i32* %conv, align 4
- %ptr8 = getelementptr i8* %_stubArgs, i64 16
+ %tmp1 = load i32, i32* %conv, align 4
+ %ptr8 = getelementptr i8, i8* %_stubArgs, i64 16
  %i4 = bitcast i8* %ptr8 to <2 x double>*
- %ptr20 = getelementptr i8* %_stubArgs, i64 48
+ %ptr20 = getelementptr i8, i8* %_stubArgs, i64 48
  %i7 = bitcast i8* %ptr20 to <2 x double> addrspace(1)**
- %tmp21 = load <2 x double> addrspace(1)** %i7, align 8
- %ptr28 = getelementptr i8* %_stubArgs, i64 64
+ %tmp21 = load <2 x double> addrspace(1)*, <2 x double> addrspace(1)** %i7, align 8
+ %ptr28 = getelementptr i8, i8* %_stubArgs, i64 64
  %i9 = bitcast i8* %ptr28 to i32*
- %tmp29 = load i32* %i9, align 4
- %ptr32 = getelementptr i8* %_stubArgs, i64 68
+ %tmp29 = load i32, i32* %i9, align 4
+ %ptr32 = getelementptr i8, i8* %_stubArgs, i64 68
  %i10 = bitcast i8* %ptr32 to i32*
- %tmp33 = load i32* %i10, align 4
+ %tmp33 = load i32, i32* %i10, align 4
  %tmp17.i = mul i32 10, 20
  %tmp19.i = add i32 %tmp17.i, %tmp33
  %conv21.i = zext i32 %tmp19.i to i64
@@ -35,8 +35,8 @@ entry:
  %tmp42.i = add i32 %tmp6.i, 17
  %tmp44.i = insertelement <2 x i32> undef, i32 %tmp42.i, i32 1
  %tmp96676677.i = or i32 17, -4
- %ptr4438.i = getelementptr inbounds [16 x <2 x double>]* %b.i, i64 0, i64 0
- %arrayidx4506.i = getelementptr [16 x <2 x double>]* %b.i, i64 0, i64 4
+ %ptr4438.i = getelementptr inbounds [16 x <2 x double>], [16 x <2 x double>]* %b.i, i64 0, i64 0
+ %arrayidx4506.i = getelementptr [16 x <2 x double>], [16 x <2 x double>]* %b.i, i64 0, i64 4
  %tmp52.i = insertelement <2 x i32> %tmp44.i, i32 0, i32 0
  %tmp78.i = extractelement <2 x i32> %tmp44.i, i32 1
  %tmp97.i = add i32 %tmp78.i, %tmp96676677.i
@@ -48,15 +48,15 @@ entry:
  %i39 = add i32 %tmp158.i, %i38
  %conv160.i = zext i32 %i39 to i64
  %tmp22.sum652.i = add i64 %conv160.i, %conv21.i
- %arrayidx161.i = getelementptr <2 x double> addrspace(1)* %tmp21, i64 %tmp22.sum652.i
- %tmp162.i = load <2 x double> addrspace(1)* %arrayidx161.i, align 16
+ %arrayidx161.i = getelementptr <2 x double>, <2 x double> addrspace(1)* %tmp21, i64 %tmp22.sum652.i
+ %tmp162.i = load <2 x double>, <2 x double> addrspace(1)* %arrayidx161.i, align 16
  %tmp222.i = add i32 %tmp154.i, 1
  %i43 = mul i32 %tmp222.i, %tmp29
  %i44 = add i32 %tmp158.i, %i43
  %conv228.i = zext i32 %i44 to i64
  %tmp22.sum656.i = add i64 %conv228.i, %conv21.i
- %arrayidx229.i = getelementptr <2 x double> addrspace(1)* %tmp21, i64 %tmp22.sum656.i
- %tmp230.i = load <2 x double> addrspace(1)* %arrayidx229.i, align 16
+ %arrayidx229.i = getelementptr <2 x double>, <2 x double> addrspace(1)* %tmp21, i64 %tmp22.sum656.i
+ %tmp230.i = load <2 x double>, <2 x double> addrspace(1)* %arrayidx229.i, align 16
  %cmp432.i = icmp ult i32 %tmp156.i, %tmp1
 
 ; %shl.i should not be sinked below the compare.
diff --git a/test/CodeGen/X86/MergeConsecutiveStores.ll b/test/CodeGen/X86/MergeConsecutiveStores.ll
index dfdaea523fdf..275d4213bd2b 100644
--- a/test/CodeGen/X86/MergeConsecutiveStores.ll
+++ b/test/CodeGen/X86/MergeConsecutiveStores.ll
@@ -17,24 +17,24 @@ define void @merge_const_store(i32 %count, %struct.A* nocapture %p) nounwind uwt
 .lr.ph:
   %i.02 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ]
   %.01 = phi %struct.A* [ %11, %.lr.ph ], [ %p, %0 ]
-  %2 = getelementptr inbounds %struct.A* %.01, i64 0, i32 0
+  %2 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 0
   store i8 1, i8* %2, align 1
-  %3 = getelementptr inbounds %struct.A* %.01, i64 0, i32 1
+  %3 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 1
   store i8 2, i8* %3, align 1
-  %4 = getelementptr inbounds %struct.A* %.01, i64 0, i32 2
+  %4 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 2
   store i8 3, i8* %4, align 1
-  %5 = getelementptr inbounds %struct.A* %.01, i64 0, i32 3
+  %5 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 3
   store i8 4, i8* %5, align 1
-  %6 = getelementptr inbounds %struct.A* %.01, i64 0, i32 4
+  %6 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 4
   store i8 5, i8* %6, align 1
-  %7 = getelementptr inbounds %struct.A* %.01, i64 0, i32 5
+  %7 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 5
   store i8 6, i8* %7, align 1
-  %8 = getelementptr inbounds %struct.A* %.01, i64 0, i32 6
+  %8 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 6
   store i8 7, i8* %8, align 1
-  %9 = getelementptr inbounds %struct.A* %.01, i64 0, i32 7
+  %9 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 7
   store i8 8, i8* %9, align 1
   %10 = add nsw i32 %i.02, 1
-  %11 = getelementptr inbounds %struct.A* %.01, i64 1
+  %11 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 1
   %exitcond = icmp eq i32 %10, %count
   br i1 %exitcond, label %._crit_edge, label %.lr.ph
 ._crit_edge:
@@ -51,24 +51,24 @@ define void @merge_const_store_no_vec(i32 %count, %struct.B* nocapture %p) noimp
 .lr.ph:
   %i.02 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ]
   %.01 = phi %struct.B* [ %11, %.lr.ph ], [ %p, %0 ]
-  %2 = getelementptr inbounds %struct.B* %.01, i64 0, i32 0
+  %2 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 0
   store i32 0, i32* %2, align 4
-  %3 = getelementptr inbounds %struct.B* %.01, i64 0, i32 1
+  %3 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 1
   store i32 0, i32* %3, align 4
-  %4 = getelementptr inbounds %struct.B* %.01, i64 0, i32 2
+  %4 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 2
   store i32 0, i32* %4, align 4
-  %5 = getelementptr inbounds %struct.B* %.01, i64 0, i32 3
+  %5 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 3
   store i32 0, i32* %5, align 4
-  %6 = getelementptr inbounds %struct.B* %.01, i64 0, i32 4
+  %6 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 4
   store i32 0, i32* %6, align 4
-  %7 = getelementptr inbounds %struct.B* %.01, i64 0, i32 5
+  %7 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 5
   store i32 0, i32* %7, align 4
-  %8 = getelementptr inbounds %struct.B* %.01, i64 0, i32 6
+  %8 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 6
   store i32 0, i32* %8, align 4
-  %9 = getelementptr inbounds %struct.B* %.01, i64 0, i32 7
+  %9 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 7
   store i32 0, i32* %9, align 4
   %10 = add nsw i32 %i.02, 1
-  %11 = getelementptr inbounds %struct.B* %.01, i64 1
+  %11 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 1
   %exitcond = icmp eq i32 %10, %count
   br i1 %exitcond, label %._crit_edge, label %.lr.ph
 ._crit_edge:
@@ -85,24 +85,24 @@ define void @merge_const_store_vec(i32 %count, %struct.B* nocapture %p) nounwind
 .lr.ph:
   %i.02 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ]
   %.01 = phi %struct.B* [ %11, %.lr.ph ], [ %p, %0 ]
-  %2 = getelementptr inbounds %struct.B* %.01, i64 0, i32 0
+  %2 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 0
   store i32 0, i32* %2, align 4
-  %3 = getelementptr inbounds %struct.B* %.01, i64 0, i32 1
+  %3 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 1
   store i32 0, i32* %3, align 4
-  %4 = getelementptr inbounds %struct.B* %.01, i64 0, i32 2
+  %4 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 2
   store i32 0, i32* %4, align 4
-  %5 = getelementptr inbounds %struct.B* %.01, i64 0, i32 3
+  %5 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 3
   store i32 0, i32* %5, align 4
-  %6 = getelementptr inbounds %struct.B* %.01, i64 0, i32 4
+  %6 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 4
   store i32 0, i32* %6, align 4
-  %7 = getelementptr inbounds %struct.B* %.01, i64 0, i32 5
+  %7 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 5
   store i32 0, i32* %7, align 4
-  %8 = getelementptr inbounds %struct.B* %.01, i64 0, i32 6
+  %8 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 6
   store i32 0, i32* %8, align 4
-  %9 = getelementptr inbounds %struct.B* %.01, i64 0, i32 7
+  %9 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 7
   store i32 0, i32* %9, align 4
   %10 = add nsw i32 %i.02, 1
-  %11 = getelementptr inbounds %struct.B* %.01, i64 1
+  %11 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 1
   %exitcond = icmp eq i32 %10, %count
   br i1 %exitcond, label %._crit_edge, label %.lr.ph
 ._crit_edge:
@@ -123,24 +123,24 @@ define void @merge_nonconst_store(i32 %count, i8 %zz, %struct.A* nocapture %p) n
 .lr.ph:
   %i.02 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ]
   %.01 = phi %struct.A* [ %11, %.lr.ph ], [ %p, %0 ]
-  %2 = getelementptr inbounds %struct.A* %.01, i64 0, i32 0
+  %2 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 0
   store i8 1, i8* %2, align 1
-  %3 = getelementptr inbounds %struct.A* %.01, i64 0, i32 1
+  %3 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 1
   store i8 2, i8* %3, align 1
-  %4 = getelementptr inbounds %struct.A* %.01, i64 0, i32 2
+  %4 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 2
   store i8 3, i8* %4, align 1
-  %5 = getelementptr inbounds %struct.A* %.01, i64 0, i32 3
+  %5 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 3
   store i8 4, i8* %5, align 1
-  %6 = getelementptr inbounds %struct.A* %.01, i64 0, i32 4
+  %6 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 4
   store i8 %zz, i8* %6, align 1                     ;  <----------- Not a const;
-  %7 = getelementptr inbounds %struct.A* %.01, i64 0, i32 5
+  %7 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 5
   store i8 6, i8* %7, align 1
-  %8 = getelementptr inbounds %struct.A* %.01, i64 0, i32 6
+  %8 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 6
   store i8 7, i8* %8, align 1
-  %9 = getelementptr inbounds %struct.A* %.01, i64 0, i32 7
+  %9 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 7
   store i8 8, i8* %9, align 1
   %10 = add nsw i32 %i.02, 1
-  %11 = getelementptr inbounds %struct.A* %.01, i64 1
+  %11 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 1
   %exitcond = icmp eq i32 %10, %count
   br i1 %exitcond, label %._crit_edge, label %.lr.ph
 ._crit_edge:
@@ -159,21 +159,21 @@ define void @merge_loads_i16(i32 %count, %struct.A* noalias nocapture %q, %struc
   br i1 %1, label %.lr.ph, label %._crit_edge
 
 .lr.ph:                                           ; preds = %0
-  %2 = getelementptr inbounds %struct.A* %q, i64 0, i32 0
-  %3 = getelementptr inbounds %struct.A* %q, i64 0, i32 1
+  %2 = getelementptr inbounds %struct.A, %struct.A* %q, i64 0, i32 0
+  %3 = getelementptr inbounds %struct.A, %struct.A* %q, i64 0, i32 1
   br label %4
 
 ; <label>:4                                       ; preds = %4, %.lr.ph
   %i.02 = phi i32 [ 0, %.lr.ph ], [ %9, %4 ]
   %.01 = phi %struct.A* [ %p, %.lr.ph ], [ %10, %4 ]
-  %5 = load i8* %2, align 1
-  %6 = load i8* %3, align 1
-  %7 = getelementptr inbounds %struct.A* %.01, i64 0, i32 0
+  %5 = load i8, i8* %2, align 1
+  %6 = load i8, i8* %3, align 1
+  %7 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 0
   store i8 %5, i8* %7, align 1
-  %8 = getelementptr inbounds %struct.A* %.01, i64 0, i32 1
+  %8 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 1
   store i8 %6, i8* %8, align 1
   %9 = add nsw i32 %i.02, 1
-  %10 = getelementptr inbounds %struct.A* %.01, i64 1
+  %10 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 1
   %exitcond = icmp eq i32 %9, %count
   br i1 %exitcond, label %._crit_edge, label %4
 
@@ -193,21 +193,21 @@ define void @no_merge_loads(i32 %count, %struct.A* noalias nocapture %q, %struct
   br i1 %1, label %.lr.ph, label %._crit_edge
 
 .lr.ph:                                           ; preds = %0
-  %2 = getelementptr inbounds %struct.A* %q, i64 0, i32 0
-  %3 = getelementptr inbounds %struct.A* %q, i64 0, i32 1
+  %2 = getelementptr inbounds %struct.A, %struct.A* %q, i64 0, i32 0
+  %3 = getelementptr inbounds %struct.A, %struct.A* %q, i64 0, i32 1
   br label %a4
 
 a4:                                       ; preds = %4, %.lr.ph
   %i.02 = phi i32 [ 0, %.lr.ph ], [ %a9, %a4 ]
   %.01 = phi %struct.A* [ %p, %.lr.ph ], [ %a10, %a4 ]
-  %a5 = load i8* %2, align 1
-  %a7 = getelementptr inbounds %struct.A* %.01, i64 0, i32 0
+  %a5 = load i8, i8* %2, align 1
+  %a7 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 0
   store i8 %a5, i8* %a7, align 1
-  %a8 = getelementptr inbounds %struct.A* %.01, i64 0, i32 1
-  %a6 = load i8* %3, align 1
+  %a8 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 1
+  %a6 = load i8, i8* %3, align 1
   store i8 %a6, i8* %a8, align 1
   %a9 = add nsw i32 %i.02, 1
-  %a10 = getelementptr inbounds %struct.A* %.01, i64 1
+  %a10 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 1
   %exitcond = icmp eq i32 %a9, %count
   br i1 %exitcond, label %._crit_edge, label %a4
 
@@ -227,21 +227,21 @@ define void @merge_loads_integer(i32 %count, %struct.B* noalias nocapture %q, %s
   br i1 %1, label %.lr.ph, label %._crit_edge
 
 .lr.ph:                                           ; preds = %0
-  %2 = getelementptr inbounds %struct.B* %q, i64 0, i32 0
-  %3 = getelementptr inbounds %struct.B* %q, i64 0, i32 1
+  %2 = getelementptr inbounds %struct.B, %struct.B* %q, i64 0, i32 0
+  %3 = getelementptr inbounds %struct.B, %struct.B* %q, i64 0, i32 1
   br label %4
 
 ; <label>:4                                       ; preds = %4, %.lr.ph
   %i.02 = phi i32 [ 0, %.lr.ph ], [ %9, %4 ]
   %.01 = phi %struct.B* [ %p, %.lr.ph ], [ %10, %4 ]
-  %5 = load i32* %2
-  %6 = load i32* %3
-  %7 = getelementptr inbounds %struct.B* %.01, i64 0, i32 0
+  %5 = load i32, i32* %2
+  %6 = load i32, i32* %3
+  %7 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 0
   store i32 %5, i32* %7
-  %8 = getelementptr inbounds %struct.B* %.01, i64 0, i32 1
+  %8 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 1
   store i32 %6, i32* %8
   %9 = add nsw i32 %i.02, 1
-  %10 = getelementptr inbounds %struct.B* %.01, i64 1
+  %10 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 1
   %exitcond = icmp eq i32 %9, %count
   br i1 %exitcond, label %._crit_edge, label %4
 
@@ -261,29 +261,29 @@ define void @merge_loads_vector(i32 %count, %struct.B* noalias nocapture %q, %st
   br i1 %a1, label %.lr.ph, label %._crit_edge
 
 .lr.ph:                                           ; preds = %0
-  %a2 = getelementptr inbounds %struct.B* %q, i64 0, i32 0
-  %a3 = getelementptr inbounds %struct.B* %q, i64 0, i32 1
-  %a4 = getelementptr inbounds %struct.B* %q, i64 0, i32 2
-  %a5 = getelementptr inbounds %struct.B* %q, i64 0, i32 3
+  %a2 = getelementptr inbounds %struct.B, %struct.B* %q, i64 0, i32 0
+  %a3 = getelementptr inbounds %struct.B, %struct.B* %q, i64 0, i32 1
+  %a4 = getelementptr inbounds %struct.B, %struct.B* %q, i64 0, i32 2
+  %a5 = getelementptr inbounds %struct.B, %struct.B* %q, i64 0, i32 3
   br label %block4
 
 block4:                                       ; preds = %4, %.lr.ph
   %i.02 = phi i32 [ 0, %.lr.ph ], [ %c9, %block4 ]
   %.01 = phi %struct.B* [ %p, %.lr.ph ], [ %c10, %block4 ]
-  %a7 = getelementptr inbounds %struct.B* %.01, i64 0, i32 0
-  %a8 = getelementptr inbounds %struct.B* %.01, i64 0, i32 1
-  %a9 = getelementptr inbounds %struct.B* %.01, i64 0, i32 2
-  %a10 = getelementptr inbounds %struct.B* %.01, i64 0, i32 3
-  %b1 = load i32* %a2
-  %b2 = load i32* %a3
-  %b3 = load i32* %a4
-  %b4 = load i32* %a5
+  %a7 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 0
+  %a8 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 1
+  %a9 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 2
+  %a10 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 3
+  %b1 = load i32, i32* %a2
+  %b2 = load i32, i32* %a3
+  %b3 = load i32, i32* %a4
+  %b4 = load i32, i32* %a5
   store i32 %b1, i32* %a7
   store i32 %b2, i32* %a8
   store i32 %b3, i32* %a9
   store i32 %b4, i32* %a10
   %c9 = add nsw i32 %i.02, 1
-  %c10 = getelementptr inbounds %struct.B* %.01, i64 1
+  %c10 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 1
   %exitcond = icmp eq i32 %c9, %count
   br i1 %exitcond, label %._crit_edge, label %block4
 
@@ -291,46 +291,41 @@ block4:                                       ; preds = %4, %.lr.ph
   ret void
 }
 
+;; On x86, even unaligned copies can be merged to vector ops.
 ; CHECK-LABEL: merge_loads_no_align:
 ;  load:
-; CHECK: movl
-; CHECK: movl
-; CHECK: movl
-; CHECK: movl
+; CHECK: vmovups
 ;  store:
-; CHECK: movl
-; CHECK: movl
-; CHECK: movl
-; CHECK: movl
+; CHECK: vmovups
 ; CHECK: ret
 define void @merge_loads_no_align(i32 %count, %struct.B* noalias nocapture %q, %struct.B* noalias nocapture %p) nounwind uwtable noinline ssp {
   %a1 = icmp sgt i32 %count, 0
   br i1 %a1, label %.lr.ph, label %._crit_edge
 
 .lr.ph:                                           ; preds = %0
-  %a2 = getelementptr inbounds %struct.B* %q, i64 0, i32 0
-  %a3 = getelementptr inbounds %struct.B* %q, i64 0, i32 1
-  %a4 = getelementptr inbounds %struct.B* %q, i64 0, i32 2
-  %a5 = getelementptr inbounds %struct.B* %q, i64 0, i32 3
+  %a2 = getelementptr inbounds %struct.B, %struct.B* %q, i64 0, i32 0
+  %a3 = getelementptr inbounds %struct.B, %struct.B* %q, i64 0, i32 1
+  %a4 = getelementptr inbounds %struct.B, %struct.B* %q, i64 0, i32 2
+  %a5 = getelementptr inbounds %struct.B, %struct.B* %q, i64 0, i32 3
   br label %block4
 
 block4:                                       ; preds = %4, %.lr.ph
   %i.02 = phi i32 [ 0, %.lr.ph ], [ %c9, %block4 ]
   %.01 = phi %struct.B* [ %p, %.lr.ph ], [ %c10, %block4 ]
-  %a7 = getelementptr inbounds %struct.B* %.01, i64 0, i32 0
-  %a8 = getelementptr inbounds %struct.B* %.01, i64 0, i32 1
-  %a9 = getelementptr inbounds %struct.B* %.01, i64 0, i32 2
-  %a10 = getelementptr inbounds %struct.B* %.01, i64 0, i32 3
-  %b1 = load i32* %a2, align 1
-  %b2 = load i32* %a3, align 1
-  %b3 = load i32* %a4, align 1
-  %b4 = load i32* %a5, align 1
+  %a7 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 0
+  %a8 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 1
+  %a9 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 2
+  %a10 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 3
+  %b1 = load i32, i32* %a2, align 1
+  %b2 = load i32, i32* %a3, align 1
+  %b3 = load i32, i32* %a4, align 1
+  %b4 = load i32, i32* %a5, align 1
   store i32 %b1, i32* %a7, align 1
   store i32 %b2, i32* %a8, align 1
   store i32 %b3, i32* %a9, align 1
   store i32 %b4, i32* %a10, align 1
   %c9 = add nsw i32 %i.02, 1
-  %c10 = getelementptr inbounds %struct.B* %.01, i64 1
+  %c10 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 1
   %exitcond = icmp eq i32 %c9, %count
   br i1 %exitcond, label %._crit_edge, label %block4
 
@@ -350,17 +345,17 @@ define void @MergeLoadStoreBaseIndexOffset(i64* %a, i8* %b, i8* %c, i32 %n) {
   %.09 = phi i32 [ %n, %0 ], [ %11, %1 ]
   %.08 = phi i8* [ %b, %0 ], [ %10, %1 ]
   %.0 = phi i64* [ %a, %0 ], [ %2, %1 ]
-  %2 = getelementptr inbounds i64* %.0, i64 1
-  %3 = load i64* %.0, align 1
-  %4 = getelementptr inbounds i8* %c, i64 %3
-  %5 = load i8* %4, align 1
+  %2 = getelementptr inbounds i64, i64* %.0, i64 1
+  %3 = load i64, i64* %.0, align 1
+  %4 = getelementptr inbounds i8, i8* %c, i64 %3
+  %5 = load i8, i8* %4, align 1
   %6 = add i64 %3, 1
-  %7 = getelementptr inbounds i8* %c, i64 %6
-  %8 = load i8* %7, align 1
+  %7 = getelementptr inbounds i8, i8* %c, i64 %6
+  %8 = load i8, i8* %7, align 1
   store i8 %5, i8* %.08, align 1
-  %9 = getelementptr inbounds i8* %.08, i64 1
+  %9 = getelementptr inbounds i8, i8* %.08, i64 1
   store i8 %8, i8* %9, align 1
-  %10 = getelementptr inbounds i8* %.08, i64 2
+  %10 = getelementptr inbounds i8, i8* %.08, i64 2
   %11 = add nsw i32 %.09, -1
   %12 = icmp eq i32 %11, 0
   br i1 %12, label %13, label %1
@@ -382,18 +377,18 @@ define void @MergeLoadStoreBaseIndexOffsetSext(i8* %a, i8* %b, i8* %c, i32 %n) {
   %.09 = phi i32 [ %n, %0 ], [ %12, %1 ]
   %.08 = phi i8* [ %b, %0 ], [ %11, %1 ]
   %.0 = phi i8* [ %a, %0 ], [ %2, %1 ]
-  %2 = getelementptr inbounds i8* %.0, i64 1
-  %3 = load i8* %.0, align 1
+  %2 = getelementptr inbounds i8, i8* %.0, i64 1
+  %3 = load i8, i8* %.0, align 1
   %4 = sext i8 %3 to i64
-  %5 = getelementptr inbounds i8* %c, i64 %4
-  %6 = load i8* %5, align 1
+  %5 = getelementptr inbounds i8, i8* %c, i64 %4
+  %6 = load i8, i8* %5, align 1
   %7 = add i64 %4, 1
-  %8 = getelementptr inbounds i8* %c, i64 %7
-  %9 = load i8* %8, align 1
+  %8 = getelementptr inbounds i8, i8* %c, i64 %7
+  %9 = load i8, i8* %8, align 1
   store i8 %6, i8* %.08, align 1
-  %10 = getelementptr inbounds i8* %.08, i64 1
+  %10 = getelementptr inbounds i8, i8* %.08, i64 1
   store i8 %9, i8* %10, align 1
-  %11 = getelementptr inbounds i8* %.08, i64 2
+  %11 = getelementptr inbounds i8, i8* %.08, i64 2
   %12 = add nsw i32 %.09, -1
   %13 = icmp eq i32 %12, 0
   br i1 %13, label %14, label %1
@@ -414,19 +409,19 @@ define void @loadStoreBaseIndexOffsetSextNoSex(i8* %a, i8* %b, i8* %c, i32 %n) {
   %.09 = phi i32 [ %n, %0 ], [ %12, %1 ]
   %.08 = phi i8* [ %b, %0 ], [ %11, %1 ]
   %.0 = phi i8* [ %a, %0 ], [ %2, %1 ]
-  %2 = getelementptr inbounds i8* %.0, i64 1
-  %3 = load i8* %.0, align 1
+  %2 = getelementptr inbounds i8, i8* %.0, i64 1
+  %3 = load i8, i8* %.0, align 1
   %4 = sext i8 %3 to i64
-  %5 = getelementptr inbounds i8* %c, i64 %4
-  %6 = load i8* %5, align 1
+  %5 = getelementptr inbounds i8, i8* %c, i64 %4
+  %6 = load i8, i8* %5, align 1
   %7 = add i8 %3, 1
   %wrap.4 = sext i8 %7 to i64
-  %8 = getelementptr inbounds i8* %c, i64 %wrap.4
-  %9 = load i8* %8, align 1
+  %8 = getelementptr inbounds i8, i8* %c, i64 %wrap.4
+  %9 = load i8, i8* %8, align 1
   store i8 %6, i8* %.08, align 1
-  %10 = getelementptr inbounds i8* %.08, i64 1
+  %10 = getelementptr inbounds i8, i8* %.08, i64 1
   store i8 %9, i8* %10, align 1
-  %11 = getelementptr inbounds i8* %.08, i64 2
+  %11 = getelementptr inbounds i8, i8* %.08, i64 2
   %12 = add nsw i32 %.09, -1
   %13 = icmp eq i32 %12, 0
   br i1 %13, label %14, label %1
@@ -434,3 +429,62 @@ define void @loadStoreBaseIndexOffsetSextNoSex(i8* %a, i8* %b, i8* %c, i32 %n) {
 ; <label>:14
   ret void
 }
+
+; PR21711 ( http://llvm.org/bugs/show_bug.cgi?id=21711 )
+define void @merge_vec_element_store(<8 x float> %v, float* %ptr) {
+  %vecext0 = extractelement <8 x float> %v, i32 0
+  %vecext1 = extractelement <8 x float> %v, i32 1
+  %vecext2 = extractelement <8 x float> %v, i32 2
+  %vecext3 = extractelement <8 x float> %v, i32 3
+  %vecext4 = extractelement <8 x float> %v, i32 4
+  %vecext5 = extractelement <8 x float> %v, i32 5
+  %vecext6 = extractelement <8 x float> %v, i32 6
+  %vecext7 = extractelement <8 x float> %v, i32 7
+  %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1
+  %arrayidx2 = getelementptr inbounds float, float* %ptr, i64 2
+  %arrayidx3 = getelementptr inbounds float, float* %ptr, i64 3
+  %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 4
+  %arrayidx5 = getelementptr inbounds float, float* %ptr, i64 5
+  %arrayidx6 = getelementptr inbounds float, float* %ptr, i64 6
+  %arrayidx7 = getelementptr inbounds float, float* %ptr, i64 7
+  store float %vecext0, float* %ptr, align 4
+  store float %vecext1, float* %arrayidx1, align 4
+  store float %vecext2, float* %arrayidx2, align 4
+  store float %vecext3, float* %arrayidx3, align 4
+  store float %vecext4, float* %arrayidx4, align 4
+  store float %vecext5, float* %arrayidx5, align 4
+  store float %vecext6, float* %arrayidx6, align 4
+  store float %vecext7, float* %arrayidx7, align 4
+  ret void
+
+; CHECK-LABEL: merge_vec_element_store
+; CHECK: vmovups
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+}
+
+; This is a minimized test based on real code that was failing.
+; We could merge stores (and loads) like this...
+
+define void @merge_vec_element_and_scalar_load([6 x i64]* %array) {
+  %idx0 = getelementptr inbounds [6 x i64], [6 x i64]* %array, i64 0, i64 0
+  %idx1 = getelementptr inbounds [6 x i64], [6 x i64]* %array, i64 0, i64 1
+  %idx4 = getelementptr inbounds [6 x i64], [6 x i64]* %array, i64 0, i64 4
+  %idx5 = getelementptr inbounds [6 x i64], [6 x i64]* %array, i64 0, i64 5
+
+  %a0 = load i64, i64* %idx0, align 8
+  store i64 %a0, i64* %idx4, align 8
+
+  %b = bitcast i64* %idx1 to <2 x i64>*
+  %v = load <2 x i64>, <2 x i64>* %b, align 8
+  %a1 = extractelement <2 x i64> %v, i32 0
+  store i64 %a1, i64* %idx5, align 8
+  ret void
+
+; CHECK-LABEL: merge_vec_element_and_scalar_load
+; CHECK:      movq	(%rdi), %rax
+; CHECK-NEXT: movq	%rax, 32(%rdi)
+; CHECK-NEXT: movq	8(%rdi), %rax
+; CHECK-NEXT: movq	%rax, 40(%rdi)
+; CHECK-NEXT: retq
+}
diff --git a/test/CodeGen/X86/StackColoring-dbg.ll b/test/CodeGen/X86/StackColoring-dbg.ll
index 498ad7edaa9d..98c27f44fabc 100644
--- a/test/CodeGen/X86/StackColoring-dbg.ll
+++ b/test/CodeGen/X86/StackColoring-dbg.ll
@@ -11,13 +11,13 @@ define void @foo() nounwind uwtable ssp {
 entry:
   %x.i = alloca i8, align 1
   %y.i = alloca [256 x i8], align 16
-  %0 = getelementptr inbounds [256 x i8]* %y.i, i64 0, i64 0
+  %0 = getelementptr inbounds [256 x i8], [256 x i8]* %y.i, i64 0, i64 0
   br label %for.body
 
 for.body:
   call void @llvm.lifetime.end(i64 -1, i8* %0) nounwind
   call void @llvm.lifetime.start(i64 -1, i8* %x.i) nounwind
-  call void @llvm.dbg.declare(metadata i8* %x.i, metadata !22, metadata !{!"0x102"}) nounwind
+  call void @llvm.dbg.declare(metadata i8* %x.i, metadata !22, metadata !DIExpression()) nounwind, !dbg !DILocation(scope: !2)
   br label %for.body
 }
 
@@ -27,9 +27,9 @@ declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind
 
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!23}
-!0 = !{!"0x11\001\00clang\001\00\000\00\000", !1, !2, !2, null, null, null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"t.c", !""}
-!16 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ]
-!2 = !{i32 0}
-!22 = !{!"0x100\00x\0016\000", null, !2, !16} ; [ DW_TAG_auto_variable ]
-!23 = !{i32 1, !"Debug Info Version", i32 2}
+!0 = !DICompileUnit(language: DW_LANG_C89, producer: "clang", isOptimized: true, emissionKind: 0, file: !1, enums: !{}, retainedTypes: !{})
+!1 = !DIFile(filename: "t.c", directory: "")
+!16 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!2 = !DISubprogram()
+!22 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 16, scope: !2, file: !1, type: !16)
+!23 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/StackColoring.ll b/test/CodeGen/X86/StackColoring.ll
index a8e3537fabe3..414ccf469ebb 100644
--- a/test/CodeGen/X86/StackColoring.ll
+++ b/test/CodeGen/X86/StackColoring.ll
@@ -411,10 +411,10 @@ define i32 @shady_range(i32 %argc, i8** nocapture %argv) uwtable {
   %a8 = bitcast [4 x %struct.Klass]* %a.i to i8*
   %b8 = bitcast [4 x %struct.Klass]* %b.i to i8*
   ; I am used outside the lifetime zone below:
-  %z2 = getelementptr inbounds [4 x %struct.Klass]* %a.i, i64 0, i64 0, i32 0
+  %z2 = getelementptr inbounds [4 x %struct.Klass], [4 x %struct.Klass]* %a.i, i64 0, i64 0, i32 0
   call void @llvm.lifetime.start(i64 -1, i8* %a8)
   call void @llvm.lifetime.start(i64 -1, i8* %b8)
-  %z3 = load i32* %z2, align 16
+  %z3 = load i32, i32* %z2, align 16
   %r = call i32 @foo(i32 %z3, i8* %a8)
   %r2 = call i32 @foo(i32 %z3, i8* %b8)
   call void @llvm.lifetime.end(i64 -1, i8* %a8)
diff --git a/test/CodeGen/X86/SwitchLowering.ll b/test/CodeGen/X86/SwitchLowering.ll
index 29a0e82bf59f..5f17d9d85726 100644
--- a/test/CodeGen/X86/SwitchLowering.ll
+++ b/test/CodeGen/X86/SwitchLowering.ll
@@ -9,10 +9,10 @@ bb:             ; preds = %bb, %entry
         %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]          ; <i32> [#uses=3]
         %CurPtr_addr.0.rec = bitcast i32 %indvar to i32         ; <i32> [#uses=1]
         %gep.upgrd.1 = zext i32 %indvar to i64          ; <i64> [#uses=1]
-        %CurPtr_addr.0 = getelementptr i8* %CurPtr, i64 %gep.upgrd.1            ; <i8*> [#uses=1]
-        %tmp = load i8* %CurPtr_addr.0          ; <i8> [#uses=3]
+        %CurPtr_addr.0 = getelementptr i8, i8* %CurPtr, i64 %gep.upgrd.1            ; <i8*> [#uses=1]
+        %tmp = load i8, i8* %CurPtr_addr.0          ; <i8> [#uses=3]
         %tmp2.rec = add i32 %CurPtr_addr.0.rec, 1               ; <i32> [#uses=1]
-        %tmp2 = getelementptr i8* %CurPtr, i32 %tmp2.rec                ; <i8*> [#uses=1]
+        %tmp2 = getelementptr i8, i8* %CurPtr, i32 %tmp2.rec                ; <i8*> [#uses=1]
         %indvar.next = add i32 %indvar, 1               ; <i32> [#uses=1]
         switch i8 %tmp, label %bb [
                  i8 0, label %bb7
diff --git a/test/CodeGen/X86/SwizzleShuff.ll b/test/CodeGen/X86/SwizzleShuff.ll
index a435272dca44..e4c35c58210a 100644
--- a/test/CodeGen/X86/SwizzleShuff.ll
+++ b/test/CodeGen/X86/SwizzleShuff.ll
@@ -6,23 +6,24 @@
 ; CHECK: xorl
 ; CHECK: ret
 define void @pull_bitcast (<4 x i8>* %pA, <4 x i8>* %pB) {
-  %A = load <4 x i8>* %pA
-  %B = load <4 x i8>* %pB
+  %A = load <4 x i8>, <4 x i8>* %pA
+  %B = load <4 x i8>, <4 x i8>* %pB
   %C = xor <4 x i8> %A, %B
   store <4 x i8> %C, <4 x i8>* %pA
   ret void
 }
 
 ; CHECK: multi_use_swizzle
-; CHECK: mov
-; CHECK-NEXT: shuf
-; CHECK-NEXT: shuf
-; CHECK-NEXT: shuf
-; CHECK-NEXT: xor
+; CHECK: pshufd
+; CHECK-NEXT: pshufd
+; CHECK-NEXT: pblendw
+; CHECK-NEXT: pshufd
+; CHECK-NEXT: pshufd
+; CHECK-NEXT: pxor
 ; CHECK-NEXT: ret
 define <4 x i32> @multi_use_swizzle (<4 x i32>* %pA, <4 x i32>* %pB) {
-  %A = load <4 x i32>* %pA
-  %B = load <4 x i32>* %pB
+  %A = load <4 x i32>, <4 x i32>* %pA
+  %B = load <4 x i32>, <4 x i32>* %pB
   %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 6>
   %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 2, i32 2>
   %S2 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 2>
@@ -34,9 +35,9 @@ define <4 x i32> @multi_use_swizzle (<4 x i32>* %pA, <4 x i32>* %pB) {
 ; CHECK: xorl
 ; CHECK: ret
 define <4 x i8> @pull_bitcast2 (<4 x i8>* %pA, <4 x i8>* %pB, <4 x i8>* %pC) {
-  %A = load <4 x i8>* %pA
+  %A = load <4 x i8>, <4 x i8>* %pA
   store <4 x i8> %A, <4 x i8>* %pC
-  %B = load <4 x i8>* %pB
+  %B = load <4 x i8>, <4 x i8>* %pB
   %C = xor <4 x i8> %A, %B
   store <4 x i8> %C, <4 x i8>* %pA
   ret <4 x i8> %C
@@ -45,11 +46,11 @@ define <4 x i8> @pull_bitcast2 (<4 x i8>* %pA, <4 x i8>* %pB, <4 x i8>* %pC) {
 
 
 ; CHECK: reverse_1
-; CHECK-NOT: shuf
+; CHECK-NOT: pshufd
 ; CHECK: ret
 define <4 x i32> @reverse_1 (<4 x i32>* %pA, <4 x i32>* %pB) {
-  %A = load <4 x i32>* %pA
-  %B = load <4 x i32>* %pB
+  %A = load <4 x i32>, <4 x i32>* %pA
+  %B = load <4 x i32>, <4 x i32>* %pB
   %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
   %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
   ret <4 x i32> %S1
@@ -57,11 +58,11 @@ define <4 x i32> @reverse_1 (<4 x i32>* %pA, <4 x i32>* %pB) {
 
 
 ; CHECK: no_reverse_shuff
-; CHECK: shuf
+; CHECK: pshufd
 ; CHECK: ret
 define <4 x i32> @no_reverse_shuff (<4 x i32>* %pA, <4 x i32>* %pB) {
-  %A = load <4 x i32>* %pA
-  %B = load <4 x i32>* %pB
+  %A = load <4 x i32>, <4 x i32>* %pA
+  %B = load <4 x i32>, <4 x i32>* %pB
   %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
   %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
   ret <4 x i32> %S1
diff --git a/test/CodeGen/X86/abi-isel.ll b/test/CodeGen/X86/abi-isel.ll
index 633e70f0285a..f363b64386f5 100644
--- a/test/CodeGen/X86/abi-isel.ll
+++ b/test/CodeGen/X86/abi-isel.ll
@@ -33,8 +33,8 @@
 
 define void @foo00() nounwind {
 entry:
-	%0 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 0), align 4
-	store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 0), align 4
+	%0 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @src, i32 0, i64 0), align 4
+	store i32 %0, i32* getelementptr ([131072 x i32], [131072 x i32]* @dst, i32 0, i64 0), align 4
 	ret void
 
 ; LINUX-64-STATIC-LABEL: foo00:
@@ -105,8 +105,8 @@ entry:
 
 define void @fxo00() nounwind {
 entry:
-	%0 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 0), align 4
-	store i32 %0, i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 0), align 4
+	%0 = load i32, i32* getelementptr ([32 x i32], [32 x i32]* @xsrc, i32 0, i64 0), align 4
+	store i32 %0, i32* getelementptr ([32 x i32], [32 x i32]* @xdst, i32 0, i64 0), align 4
 	ret void
 
 ; LINUX-64-STATIC-LABEL: fxo00:
@@ -177,7 +177,7 @@ entry:
 
 define void @foo01() nounwind {
 entry:
-	store i32* getelementptr ([131072 x i32]* @dst, i32 0, i32 0), i32** @ptr, align 8
+	store i32* getelementptr ([131072 x i32], [131072 x i32]* @dst, i32 0, i32 0), i32** @ptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: foo01:
 ; LINUX-64-STATIC: movq	$dst, ptr
@@ -237,7 +237,7 @@ entry:
 
 define void @fxo01() nounwind {
 entry:
-	store i32* getelementptr ([32 x i32]* @xdst, i32 0, i32 0), i32** @ptr, align 8
+	store i32* getelementptr ([32 x i32], [32 x i32]* @xdst, i32 0, i32 0), i32** @ptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: fxo01:
 ; LINUX-64-STATIC: movq	$xdst, ptr
@@ -297,8 +297,8 @@ entry:
 
 define void @foo02() nounwind {
 entry:
-	%0 = load i32** @ptr, align 8
-	%1 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 0), align 4
+	%0 = load i32*, i32** @ptr, align 8
+	%1 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @src, i32 0, i64 0), align 4
 	store i32 %1, i32* %0, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: foo02:
@@ -379,8 +379,8 @@ entry:
 
 define void @fxo02() nounwind {
 entry:
-	%0 = load i32** @ptr, align 8
-	%1 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 0), align 4
+	%0 = load i32*, i32** @ptr, align 8
+	%1 = load i32, i32* getelementptr ([32 x i32], [32 x i32]* @xsrc, i32 0, i64 0), align 4
 	store i32 %1, i32* %0, align 4
 ; LINUX-64-STATIC-LABEL: fxo02:
 ; LINUX-64-STATIC: movl    xsrc(%rip), %
@@ -461,8 +461,8 @@ entry:
 
 define void @foo03() nounwind {
 entry:
-	%0 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 0), align 32
-	store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 0), align 32
+	%0 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @dsrc, i32 0, i64 0), align 32
+	store i32 %0, i32* getelementptr ([131072 x i32], [131072 x i32]* @ddst, i32 0, i64 0), align 32
 	ret void
 ; LINUX-64-STATIC-LABEL: foo03:
 ; LINUX-64-STATIC: movl    dsrc(%rip), [[EAX:%e.x]]
@@ -522,7 +522,7 @@ entry:
 
 define void @foo04() nounwind {
 entry:
-	store i32* getelementptr ([131072 x i32]* @ddst, i32 0, i32 0), i32** @dptr, align 8
+	store i32* getelementptr ([131072 x i32], [131072 x i32]* @ddst, i32 0, i32 0), i32** @dptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: foo04:
 ; LINUX-64-STATIC: movq    $ddst, dptr
@@ -576,8 +576,8 @@ entry:
 
 define void @foo05() nounwind {
 entry:
-	%0 = load i32** @dptr, align 8
-	%1 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 0), align 32
+	%0 = load i32*, i32** @dptr, align 8
+	%1 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @dsrc, i32 0, i64 0), align 32
 	store i32 %1, i32* %0, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: foo05:
@@ -648,8 +648,8 @@ entry:
 
 define void @foo06() nounwind {
 entry:
-	%0 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 0), align 4
-	store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 0), align 4
+	%0 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @lsrc, i32 0, i64 0), align 4
+	store i32 %0, i32* getelementptr ([131072 x i32], [131072 x i32]* @ldst, i32 0, i64 0), align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: foo06:
 ; LINUX-64-STATIC: movl    lsrc(%rip), [[EAX:%e.x]]
@@ -707,7 +707,7 @@ entry:
 
 define void @foo07() nounwind {
 entry:
-	store i32* getelementptr ([131072 x i32]* @ldst, i32 0, i32 0), i32** @lptr, align 8
+	store i32* getelementptr ([131072 x i32], [131072 x i32]* @ldst, i32 0, i32 0), i32** @lptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: foo07:
 ; LINUX-64-STATIC: movq    $ldst, lptr
@@ -760,8 +760,8 @@ entry:
 
 define void @foo08() nounwind {
 entry:
-	%0 = load i32** @lptr, align 8
-	%1 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 0), align 4
+	%0 = load i32*, i32** @lptr, align 8
+	%1 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @lsrc, i32 0, i64 0), align 4
 	store i32 %1, i32* %0, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: foo08:
@@ -830,8 +830,8 @@ entry:
 
 define void @qux00() nounwind {
 entry:
-	%0 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 16), align 4
-	store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16), align 4
+	%0 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @src, i32 0, i64 16), align 4
+	store i32 %0, i32* getelementptr ([131072 x i32], [131072 x i32]* @dst, i32 0, i64 16), align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: qux00:
 ; LINUX-64-STATIC: movl    src+64(%rip), [[EAX:%e.x]]
@@ -901,8 +901,8 @@ entry:
 
 define void @qxx00() nounwind {
 entry:
-	%0 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 16), align 4
-	store i32 %0, i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16), align 4
+	%0 = load i32, i32* getelementptr ([32 x i32], [32 x i32]* @xsrc, i32 0, i64 16), align 4
+	store i32 %0, i32* getelementptr ([32 x i32], [32 x i32]* @xdst, i32 0, i64 16), align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: qxx00:
 ; LINUX-64-STATIC: movl    xsrc+64(%rip), [[EAX:%e.x]]
@@ -972,7 +972,7 @@ entry:
 
 define void @qux01() nounwind {
 entry:
-	store i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16), i32** @ptr, align 8
+	store i32* getelementptr ([131072 x i32], [131072 x i32]* @dst, i32 0, i64 16), i32** @ptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: qux01:
 ; LINUX-64-STATIC: movq    $dst+64, ptr
@@ -1038,7 +1038,7 @@ entry:
 
 define void @qxx01() nounwind {
 entry:
-	store i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16), i32** @ptr, align 8
+	store i32* getelementptr ([32 x i32], [32 x i32]* @xdst, i32 0, i64 16), i32** @ptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: qxx01:
 ; LINUX-64-STATIC: movq    $xdst+64, ptr
@@ -1104,9 +1104,9 @@ entry:
 
 define void @qux02() nounwind {
 entry:
-	%0 = load i32** @ptr, align 8
-	%1 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 16), align 4
-	%2 = getelementptr i32* %0, i64 16
+	%0 = load i32*, i32** @ptr, align 8
+	%1 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @src, i32 0, i64 16), align 4
+	%2 = getelementptr i32, i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
 ; LINUX-64-STATIC-LABEL: qux02:
 ; LINUX-64-STATIC: movl    src+64(%rip), [[EAX:%e.x]]
@@ -1187,9 +1187,9 @@ entry:
 
 define void @qxx02() nounwind {
 entry:
-	%0 = load i32** @ptr, align 8
-	%1 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 16), align 4
-	%2 = getelementptr i32* %0, i64 16
+	%0 = load i32*, i32** @ptr, align 8
+	%1 = load i32, i32* getelementptr ([32 x i32], [32 x i32]* @xsrc, i32 0, i64 16), align 4
+	%2 = getelementptr i32, i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
 ; LINUX-64-STATIC-LABEL: qxx02:
 ; LINUX-64-STATIC: movl    xsrc+64(%rip), [[EAX:%e.x]]
@@ -1270,8 +1270,8 @@ entry:
 
 define void @qux03() nounwind {
 entry:
-	%0 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 16), align 32
-	store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16), align 32
+	%0 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @dsrc, i32 0, i64 16), align 32
+	store i32 %0, i32* getelementptr ([131072 x i32], [131072 x i32]* @ddst, i32 0, i64 16), align 32
 	ret void
 ; LINUX-64-STATIC-LABEL: qux03:
 ; LINUX-64-STATIC: movl    dsrc+64(%rip), [[EAX:%e.x]]
@@ -1331,7 +1331,7 @@ entry:
 
 define void @qux04() nounwind {
 entry:
-	store i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16), i32** @dptr, align 8
+	store i32* getelementptr ([131072 x i32], [131072 x i32]* @ddst, i32 0, i64 16), i32** @dptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: qux04:
 ; LINUX-64-STATIC: movq    $ddst+64, dptr(%rip)
@@ -1386,9 +1386,9 @@ entry:
 
 define void @qux05() nounwind {
 entry:
-	%0 = load i32** @dptr, align 8
-	%1 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 16), align 32
-	%2 = getelementptr i32* %0, i64 16
+	%0 = load i32*, i32** @dptr, align 8
+	%1 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @dsrc, i32 0, i64 16), align 32
+	%2 = getelementptr i32, i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
 ; LINUX-64-STATIC-LABEL: qux05:
 ; LINUX-64-STATIC: movl    dsrc+64(%rip), [[EAX:%e.x]]
@@ -1459,8 +1459,8 @@ entry:
 
 define void @qux06() nounwind {
 entry:
-	%0 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 16), align 4
-	store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16), align 4
+	%0 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @lsrc, i32 0, i64 16), align 4
+	store i32 %0, i32* getelementptr ([131072 x i32], [131072 x i32]* @ldst, i32 0, i64 16), align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: qux06:
 ; LINUX-64-STATIC: movl    lsrc+64(%rip), [[EAX:%e.x]]
@@ -1518,7 +1518,7 @@ entry:
 
 define void @qux07() nounwind {
 entry:
-	store i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16), i32** @lptr, align 8
+	store i32* getelementptr ([131072 x i32], [131072 x i32]* @ldst, i32 0, i64 16), i32** @lptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: qux07:
 ; LINUX-64-STATIC: movq    $ldst+64, lptr
@@ -1571,9 +1571,9 @@ entry:
 
 define void @qux08() nounwind {
 entry:
-	%0 = load i32** @lptr, align 8
-	%1 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 16), align 4
-	%2 = getelementptr i32* %0, i64 16
+	%0 = load i32*, i32** @lptr, align 8
+	%1 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @lsrc, i32 0, i64 16), align 4
+	%2 = getelementptr i32, i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
 ; LINUX-64-STATIC-LABEL: qux08:
 ; LINUX-64-STATIC: movl    lsrc+64(%rip), [[EAX:%e.x]]
@@ -1642,9 +1642,9 @@ entry:
 
 define void @ind00(i64 %i) nounwind {
 entry:
-	%0 = getelementptr [131072 x i32]* @src, i64 0, i64 %i
-	%1 = load i32* %0, align 4
-	%2 = getelementptr [131072 x i32]* @dst, i64 0, i64 %i
+	%0 = getelementptr [131072 x i32], [131072 x i32]* @src, i64 0, i64 %i
+	%1 = load i32, i32* %0, align 4
+	%2 = getelementptr [131072 x i32], [131072 x i32]* @dst, i64 0, i64 %i
 	store i32 %1, i32* %2, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: ind00:
@@ -1720,9 +1720,9 @@ entry:
 
 define void @ixd00(i64 %i) nounwind {
 entry:
-	%0 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %i
-	%1 = load i32* %0, align 4
-	%2 = getelementptr [32 x i32]* @xdst, i64 0, i64 %i
+	%0 = getelementptr [32 x i32], [32 x i32]* @xsrc, i64 0, i64 %i
+	%1 = load i32, i32* %0, align 4
+	%2 = getelementptr [32 x i32], [32 x i32]* @xdst, i64 0, i64 %i
 	store i32 %1, i32* %2, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: ixd00:
@@ -1798,7 +1798,7 @@ entry:
 
 define void @ind01(i64 %i) nounwind {
 entry:
-	%0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %i
+	%0 = getelementptr [131072 x i32], [131072 x i32]* @dst, i64 0, i64 %i
 	store i32* %0, i32** @ptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: ind01:
@@ -1874,7 +1874,7 @@ entry:
 
 define void @ixd01(i64 %i) nounwind {
 entry:
-	%0 = getelementptr [32 x i32]* @xdst, i64 0, i64 %i
+	%0 = getelementptr [32 x i32], [32 x i32]* @xdst, i64 0, i64 %i
 	store i32* %0, i32** @ptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: ixd01:
@@ -1950,10 +1950,10 @@ entry:
 
 define void @ind02(i64 %i) nounwind {
 entry:
-	%0 = load i32** @ptr, align 8
-	%1 = getelementptr [131072 x i32]* @src, i64 0, i64 %i
-	%2 = load i32* %1, align 4
-	%3 = getelementptr i32* %0, i64 %i
+	%0 = load i32*, i32** @ptr, align 8
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @src, i64 0, i64 %i
+	%2 = load i32, i32* %1, align 4
+	%3 = getelementptr i32, i32* %0, i64 %i
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: ind02:
@@ -2039,10 +2039,10 @@ entry:
 
 define void @ixd02(i64 %i) nounwind {
 entry:
-	%0 = load i32** @ptr, align 8
-	%1 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %i
-	%2 = load i32* %1, align 4
-	%3 = getelementptr i32* %0, i64 %i
+	%0 = load i32*, i32** @ptr, align 8
+	%1 = getelementptr [32 x i32], [32 x i32]* @xsrc, i64 0, i64 %i
+	%2 = load i32, i32* %1, align 4
+	%3 = getelementptr i32, i32* %0, i64 %i
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: ixd02:
@@ -2128,9 +2128,9 @@ entry:
 
 define void @ind03(i64 %i) nounwind {
 entry:
-	%0 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %i
-	%1 = load i32* %0, align 4
-	%2 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %i
+	%0 = getelementptr [131072 x i32], [131072 x i32]* @dsrc, i64 0, i64 %i
+	%1 = load i32, i32* %0, align 4
+	%2 = getelementptr [131072 x i32], [131072 x i32]* @ddst, i64 0, i64 %i
 	store i32 %1, i32* %2, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: ind03:
@@ -2202,7 +2202,7 @@ entry:
 
 define void @ind04(i64 %i) nounwind {
 entry:
-	%0 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %i
+	%0 = getelementptr [131072 x i32], [131072 x i32]* @ddst, i64 0, i64 %i
 	store i32* %0, i32** @dptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: ind04:
@@ -2271,10 +2271,10 @@ entry:
 
 define void @ind05(i64 %i) nounwind {
 entry:
-	%0 = load i32** @dptr, align 8
-	%1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %i
-	%2 = load i32* %1, align 4
-	%3 = getelementptr i32* %0, i64 %i
+	%0 = load i32*, i32** @dptr, align 8
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @dsrc, i64 0, i64 %i
+	%2 = load i32, i32* %1, align 4
+	%3 = getelementptr i32, i32* %0, i64 %i
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: ind05:
@@ -2353,9 +2353,9 @@ entry:
 
 define void @ind06(i64 %i) nounwind {
 entry:
-	%0 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %i
-	%1 = load i32* %0, align 4
-	%2 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %i
+	%0 = getelementptr [131072 x i32], [131072 x i32]* @lsrc, i64 0, i64 %i
+	%1 = load i32, i32* %0, align 4
+	%2 = getelementptr [131072 x i32], [131072 x i32]* @ldst, i64 0, i64 %i
 	store i32 %1, i32* %2, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: ind06:
@@ -2427,7 +2427,7 @@ entry:
 
 define void @ind07(i64 %i) nounwind {
 entry:
-	%0 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %i
+	%0 = getelementptr [131072 x i32], [131072 x i32]* @ldst, i64 0, i64 %i
 	store i32* %0, i32** @lptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: ind07:
@@ -2495,10 +2495,10 @@ entry:
 
 define void @ind08(i64 %i) nounwind {
 entry:
-	%0 = load i32** @lptr, align 8
-	%1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %i
-	%2 = load i32* %1, align 4
-	%3 = getelementptr i32* %0, i64 %i
+	%0 = load i32*, i32** @lptr, align 8
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @lsrc, i64 0, i64 %i
+	%2 = load i32, i32* %1, align 4
+	%3 = getelementptr i32, i32* %0, i64 %i
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: ind08:
@@ -2577,9 +2577,9 @@ entry:
 define void @off00(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 16
-	%1 = getelementptr [131072 x i32]* @src, i64 0, i64 %0
-	%2 = load i32* %1, align 4
-	%3 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @src, i64 0, i64 %0
+	%2 = load i32, i32* %1, align 4
+	%3 = getelementptr [131072 x i32], [131072 x i32]* @dst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: off00:
@@ -2656,9 +2656,9 @@ entry:
 define void @oxf00(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 16
-	%1 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %0
-	%2 = load i32* %1, align 4
-	%3 = getelementptr [32 x i32]* @xdst, i64 0, i64 %0
+	%1 = getelementptr [32 x i32], [32 x i32]* @xsrc, i64 0, i64 %0
+	%2 = load i32, i32* %1, align 4
+	%3 = getelementptr [32 x i32], [32 x i32]* @xdst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: oxf00:
@@ -2735,7 +2735,7 @@ entry:
 define void @off01(i64 %i) nounwind {
 entry:
 	%.sum = add i64 %i, 16
-	%0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %.sum
+	%0 = getelementptr [131072 x i32], [131072 x i32]* @dst, i64 0, i64 %.sum
 	store i32* %0, i32** @ptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: off01:
@@ -2812,7 +2812,7 @@ entry:
 define void @oxf01(i64 %i) nounwind {
 entry:
 	%.sum = add i64 %i, 16
-	%0 = getelementptr [32 x i32]* @xdst, i64 0, i64 %.sum
+	%0 = getelementptr [32 x i32], [32 x i32]* @xdst, i64 0, i64 %.sum
 	store i32* %0, i32** @ptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: oxf01:
@@ -2888,11 +2888,11 @@ entry:
 
 define void @off02(i64 %i) nounwind {
 entry:
-	%0 = load i32** @ptr, align 8
+	%0 = load i32*, i32** @ptr, align 8
 	%1 = add i64 %i, 16
-	%2 = getelementptr [131072 x i32]* @src, i64 0, i64 %1
-	%3 = load i32* %2, align 4
-	%4 = getelementptr i32* %0, i64 %1
+	%2 = getelementptr [131072 x i32], [131072 x i32]* @src, i64 0, i64 %1
+	%3 = load i32, i32* %2, align 4
+	%4 = getelementptr i32, i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: off02:
@@ -2978,11 +2978,11 @@ entry:
 
 define void @oxf02(i64 %i) nounwind {
 entry:
-	%0 = load i32** @ptr, align 8
+	%0 = load i32*, i32** @ptr, align 8
 	%1 = add i64 %i, 16
-	%2 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %1
-	%3 = load i32* %2, align 4
-	%4 = getelementptr i32* %0, i64 %1
+	%2 = getelementptr [32 x i32], [32 x i32]* @xsrc, i64 0, i64 %1
+	%3 = load i32, i32* %2, align 4
+	%4 = getelementptr i32, i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: oxf02:
@@ -3069,9 +3069,9 @@ entry:
 define void @off03(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 16
-	%1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %0
-	%2 = load i32* %1, align 4
-	%3 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @dsrc, i64 0, i64 %0
+	%2 = load i32, i32* %1, align 4
+	%3 = getelementptr [131072 x i32], [131072 x i32]* @ddst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: off03:
@@ -3144,7 +3144,7 @@ entry:
 define void @off04(i64 %i) nounwind {
 entry:
 	%.sum = add i64 %i, 16
-	%0 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %.sum
+	%0 = getelementptr [131072 x i32], [131072 x i32]* @ddst, i64 0, i64 %.sum
 	store i32* %0, i32** @dptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: off04:
@@ -3213,11 +3213,11 @@ entry:
 
 define void @off05(i64 %i) nounwind {
 entry:
-	%0 = load i32** @dptr, align 8
+	%0 = load i32*, i32** @dptr, align 8
 	%1 = add i64 %i, 16
-	%2 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %1
-	%3 = load i32* %2, align 4
-	%4 = getelementptr i32* %0, i64 %1
+	%2 = getelementptr [131072 x i32], [131072 x i32]* @dsrc, i64 0, i64 %1
+	%3 = load i32, i32* %2, align 4
+	%4 = getelementptr i32, i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: off05:
@@ -3297,9 +3297,9 @@ entry:
 define void @off06(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 16
-	%1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %0
-	%2 = load i32* %1, align 4
-	%3 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @lsrc, i64 0, i64 %0
+	%2 = load i32, i32* %1, align 4
+	%3 = getelementptr [131072 x i32], [131072 x i32]* @ldst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: off06:
@@ -3372,7 +3372,7 @@ entry:
 define void @off07(i64 %i) nounwind {
 entry:
 	%.sum = add i64 %i, 16
-	%0 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %.sum
+	%0 = getelementptr [131072 x i32], [131072 x i32]* @ldst, i64 0, i64 %.sum
 	store i32* %0, i32** @lptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: off07:
@@ -3440,11 +3440,11 @@ entry:
 
 define void @off08(i64 %i) nounwind {
 entry:
-	%0 = load i32** @lptr, align 8
+	%0 = load i32*, i32** @lptr, align 8
 	%1 = add i64 %i, 16
-	%2 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %1
-	%3 = load i32* %2, align 4
-	%4 = getelementptr i32* %0, i64 %1
+	%2 = getelementptr [131072 x i32], [131072 x i32]* @lsrc, i64 0, i64 %1
+	%3 = load i32, i32* %2, align 4
+	%4 = getelementptr i32, i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: off08:
@@ -3522,8 +3522,8 @@ entry:
 
 define void @moo00(i64 %i) nounwind {
 entry:
-	%0 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 65536), align 4
-	store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536), align 4
+	%0 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @src, i32 0, i64 65536), align 4
+	store i32 %0, i32* getelementptr ([131072 x i32], [131072 x i32]* @dst, i32 0, i64 65536), align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: moo00:
 ; LINUX-64-STATIC: movl    src+262144(%rip), [[EAX:%e.x]]
@@ -3593,7 +3593,7 @@ entry:
 
 define void @moo01(i64 %i) nounwind {
 entry:
-	store i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536), i32** @ptr, align 8
+	store i32* getelementptr ([131072 x i32], [131072 x i32]* @dst, i32 0, i64 65536), i32** @ptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: moo01:
 ; LINUX-64-STATIC: movq    $dst+262144, ptr(%rip)
@@ -3659,9 +3659,9 @@ entry:
 
 define void @moo02(i64 %i) nounwind {
 entry:
-	%0 = load i32** @ptr, align 8
-	%1 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 65536), align 4
-	%2 = getelementptr i32* %0, i64 65536
+	%0 = load i32*, i32** @ptr, align 8
+	%1 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @src, i32 0, i64 65536), align 4
+	%2 = getelementptr i32, i32* %0, i64 65536
 	store i32 %1, i32* %2, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: moo02:
@@ -3742,8 +3742,8 @@ entry:
 
 define void @moo03(i64 %i) nounwind {
 entry:
-	%0 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 65536), align 32
-	store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536), align 32
+	%0 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @dsrc, i32 0, i64 65536), align 32
+	store i32 %0, i32* getelementptr ([131072 x i32], [131072 x i32]* @ddst, i32 0, i64 65536), align 32
 	ret void
 ; LINUX-64-STATIC-LABEL: moo03:
 ; LINUX-64-STATIC: movl    dsrc+262144(%rip), [[EAX:%e.x]]
@@ -3803,7 +3803,7 @@ entry:
 
 define void @moo04(i64 %i) nounwind {
 entry:
-	store i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536), i32** @dptr, align 8
+	store i32* getelementptr ([131072 x i32], [131072 x i32]* @ddst, i32 0, i64 65536), i32** @dptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: moo04:
 ; LINUX-64-STATIC: movq    $ddst+262144, dptr
@@ -3858,9 +3858,9 @@ entry:
 
 define void @moo05(i64 %i) nounwind {
 entry:
-	%0 = load i32** @dptr, align 8
-	%1 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 65536), align 32
-	%2 = getelementptr i32* %0, i64 65536
+	%0 = load i32*, i32** @dptr, align 8
+	%1 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @dsrc, i32 0, i64 65536), align 32
+	%2 = getelementptr i32, i32* %0, i64 65536
 	store i32 %1, i32* %2, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: moo05:
@@ -3931,8 +3931,8 @@ entry:
 
 define void @moo06(i64 %i) nounwind {
 entry:
-	%0 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 65536), align 4
-	store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536), align 4
+	%0 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @lsrc, i32 0, i64 65536), align 4
+	store i32 %0, i32* getelementptr ([131072 x i32], [131072 x i32]* @ldst, i32 0, i64 65536), align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: moo06:
 ; LINUX-64-STATIC: movl    lsrc+262144(%rip), [[EAX:%e.x]]
@@ -3990,7 +3990,7 @@ entry:
 
 define void @moo07(i64 %i) nounwind {
 entry:
-	store i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536), i32** @lptr, align 8
+	store i32* getelementptr ([131072 x i32], [131072 x i32]* @ldst, i32 0, i64 65536), i32** @lptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: moo07:
 ; LINUX-64-STATIC: movq    $ldst+262144, lptr
@@ -4043,9 +4043,9 @@ entry:
 
 define void @moo08(i64 %i) nounwind {
 entry:
-	%0 = load i32** @lptr, align 8
-	%1 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 65536), align 4
-	%2 = getelementptr i32* %0, i64 65536
+	%0 = load i32*, i32** @lptr, align 8
+	%1 = load i32, i32* getelementptr ([131072 x i32], [131072 x i32]* @lsrc, i32 0, i64 65536), align 4
+	%2 = getelementptr i32, i32* %0, i64 65536
 	store i32 %1, i32* %2, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: moo08:
@@ -4115,9 +4115,9 @@ entry:
 define void @big00(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 65536
-	%1 = getelementptr [131072 x i32]* @src, i64 0, i64 %0
-	%2 = load i32* %1, align 4
-	%3 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @src, i64 0, i64 %0
+	%2 = load i32, i32* %1, align 4
+	%3 = getelementptr [131072 x i32], [131072 x i32]* @dst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: big00:
@@ -4194,7 +4194,7 @@ entry:
 define void @big01(i64 %i) nounwind {
 entry:
 	%.sum = add i64 %i, 65536
-	%0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %.sum
+	%0 = getelementptr [131072 x i32], [131072 x i32]* @dst, i64 0, i64 %.sum
 	store i32* %0, i32** @ptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: big01:
@@ -4270,11 +4270,11 @@ entry:
 
 define void @big02(i64 %i) nounwind {
 entry:
-	%0 = load i32** @ptr, align 8
+	%0 = load i32*, i32** @ptr, align 8
 	%1 = add i64 %i, 65536
-	%2 = getelementptr [131072 x i32]* @src, i64 0, i64 %1
-	%3 = load i32* %2, align 4
-	%4 = getelementptr i32* %0, i64 %1
+	%2 = getelementptr [131072 x i32], [131072 x i32]* @src, i64 0, i64 %1
+	%3 = load i32, i32* %2, align 4
+	%4 = getelementptr i32, i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: big02:
@@ -4361,9 +4361,9 @@ entry:
 define void @big03(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 65536
-	%1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %0
-	%2 = load i32* %1, align 4
-	%3 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @dsrc, i64 0, i64 %0
+	%2 = load i32, i32* %1, align 4
+	%3 = getelementptr [131072 x i32], [131072 x i32]* @ddst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: big03:
@@ -4436,7 +4436,7 @@ entry:
 define void @big04(i64 %i) nounwind {
 entry:
 	%.sum = add i64 %i, 65536
-	%0 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %.sum
+	%0 = getelementptr [131072 x i32], [131072 x i32]* @ddst, i64 0, i64 %.sum
 	store i32* %0, i32** @dptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: big04:
@@ -4505,11 +4505,11 @@ entry:
 
 define void @big05(i64 %i) nounwind {
 entry:
-	%0 = load i32** @dptr, align 8
+	%0 = load i32*, i32** @dptr, align 8
 	%1 = add i64 %i, 65536
-	%2 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %1
-	%3 = load i32* %2, align 4
-	%4 = getelementptr i32* %0, i64 %1
+	%2 = getelementptr [131072 x i32], [131072 x i32]* @dsrc, i64 0, i64 %1
+	%3 = load i32, i32* %2, align 4
+	%4 = getelementptr i32, i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: big05:
@@ -4589,9 +4589,9 @@ entry:
 define void @big06(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 65536
-	%1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %0
-	%2 = load i32* %1, align 4
-	%3 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @lsrc, i64 0, i64 %0
+	%2 = load i32, i32* %1, align 4
+	%3 = getelementptr [131072 x i32], [131072 x i32]* @ldst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: big06:
@@ -4664,7 +4664,7 @@ entry:
 define void @big07(i64 %i) nounwind {
 entry:
 	%.sum = add i64 %i, 65536
-	%0 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %.sum
+	%0 = getelementptr [131072 x i32], [131072 x i32]* @ldst, i64 0, i64 %.sum
 	store i32* %0, i32** @lptr, align 8
 	ret void
 ; LINUX-64-STATIC-LABEL: big07:
@@ -4732,11 +4732,11 @@ entry:
 
 define void @big08(i64 %i) nounwind {
 entry:
-	%0 = load i32** @lptr, align 8
+	%0 = load i32*, i32** @lptr, align 8
 	%1 = add i64 %i, 65536
-	%2 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %1
-	%3 = load i32* %2, align 4
-	%4 = getelementptr i32* %0, i64 %1
+	%2 = getelementptr [131072 x i32], [131072 x i32]* @lsrc, i64 0, i64 %1
+	%3 = load i32, i32* %2, align 4
+	%4 = getelementptr i32, i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
 ; LINUX-64-STATIC-LABEL: big08:
@@ -5519,7 +5519,7 @@ entry:
 
 define i8* @har02() nounwind {
 entry:
-	%0 = load i32** @ptr, align 8
+	%0 = load i32*, i32** @ptr, align 8
 	%1 = bitcast i32* %0 to i8*
 	ret i8* %1
 ; LINUX-64-STATIC-LABEL: har02:
@@ -5668,7 +5668,7 @@ entry:
 
 define i8* @har05() nounwind {
 entry:
-	%0 = load i32** @dptr, align 8
+	%0 = load i32*, i32** @dptr, align 8
 	%1 = bitcast i32* %0 to i8*
 	ret i8* %1
 ; LINUX-64-STATIC-LABEL: har05:
@@ -5812,7 +5812,7 @@ entry:
 
 define i8* @har08() nounwind {
 entry:
-	%0 = load i32** @lptr, align 8
+	%0 = load i32*, i32** @lptr, align 8
 	%1 = bitcast i32* %0 to i8*
 	ret i8* %1
 ; LINUX-64-STATIC-LABEL: har08:
@@ -5861,7 +5861,7 @@ entry:
 
 define i8* @bat00() nounwind {
 entry:
-	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @src, i32 0, i64 16) to i8*)
+	ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @src, i32 0, i64 16) to i8*)
 ; LINUX-64-STATIC-LABEL: bat00:
 ; LINUX-64-STATIC: movl    $src+64, %eax
 ; LINUX-64-STATIC: ret
@@ -5914,7 +5914,7 @@ entry:
 
 define i8* @bxt00() nounwind {
 entry:
-	ret i8* bitcast (i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 16) to i8*)
+	ret i8* bitcast (i32* getelementptr ([32 x i32], [32 x i32]* @xsrc, i32 0, i64 16) to i8*)
 ; LINUX-64-STATIC-LABEL: bxt00:
 ; LINUX-64-STATIC: movl    $xsrc+64, %eax
 ; LINUX-64-STATIC: ret
@@ -5967,7 +5967,7 @@ entry:
 
 define i8* @bat01() nounwind {
 entry:
-	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16) to i8*)
+	ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @dst, i32 0, i64 16) to i8*)
 ; LINUX-64-STATIC-LABEL: bat01:
 ; LINUX-64-STATIC: movl    $dst+64, %eax
 ; LINUX-64-STATIC: ret
@@ -6020,7 +6020,7 @@ entry:
 
 define i8* @bxt01() nounwind {
 entry:
-	ret i8* bitcast (i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16) to i8*)
+	ret i8* bitcast (i32* getelementptr ([32 x i32], [32 x i32]* @xdst, i32 0, i64 16) to i8*)
 ; LINUX-64-STATIC-LABEL: bxt01:
 ; LINUX-64-STATIC: movl    $xdst+64, %eax
 ; LINUX-64-STATIC: ret
@@ -6073,8 +6073,8 @@ entry:
 
 define i8* @bat02() nounwind {
 entry:
-	%0 = load i32** @ptr, align 8
-	%1 = getelementptr i32* %0, i64 16
+	%0 = load i32*, i32** @ptr, align 8
+	%1 = getelementptr i32, i32* %0, i64 16
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: bat02:
@@ -6139,7 +6139,7 @@ entry:
 
 define i8* @bat03() nounwind {
 entry:
-	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 16) to i8*)
+	ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @dsrc, i32 0, i64 16) to i8*)
 ; LINUX-64-STATIC-LABEL: bat03:
 ; LINUX-64-STATIC: movl    $dsrc+64, %eax
 ; LINUX-64-STATIC: ret
@@ -6187,7 +6187,7 @@ entry:
 
 define i8* @bat04() nounwind {
 entry:
-	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16) to i8*)
+	ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @ddst, i32 0, i64 16) to i8*)
 ; LINUX-64-STATIC-LABEL: bat04:
 ; LINUX-64-STATIC: movl    $ddst+64, %eax
 ; LINUX-64-STATIC: ret
@@ -6235,8 +6235,8 @@ entry:
 
 define i8* @bat05() nounwind {
 entry:
-	%0 = load i32** @dptr, align 8
-	%1 = getelementptr i32* %0, i64 16
+	%0 = load i32*, i32** @dptr, align 8
+	%1 = getelementptr i32, i32* %0, i64 16
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: bat05:
@@ -6296,7 +6296,7 @@ entry:
 
 define i8* @bat06() nounwind {
 entry:
-	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 16) to i8*)
+	ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @lsrc, i32 0, i64 16) to i8*)
 ; LINUX-64-STATIC-LABEL: bat06:
 ; LINUX-64-STATIC: movl    $lsrc+64, %eax
 ; LINUX-64-STATIC: ret
@@ -6343,7 +6343,7 @@ entry:
 
 define i8* @bat07() nounwind {
 entry:
-	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16) to i8*)
+	ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @ldst, i32 0, i64 16) to i8*)
 ; LINUX-64-STATIC-LABEL: bat07:
 ; LINUX-64-STATIC: movl    $ldst+64, %eax
 ; LINUX-64-STATIC: ret
@@ -6390,8 +6390,8 @@ entry:
 
 define i8* @bat08() nounwind {
 entry:
-	%0 = load i32** @lptr, align 8
-	%1 = getelementptr i32* %0, i64 16
+	%0 = load i32*, i32** @lptr, align 8
+	%1 = getelementptr i32, i32* %0, i64 16
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: bat08:
@@ -6450,7 +6450,7 @@ entry:
 
 define i8* @bam00() nounwind {
 entry:
-	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @src, i32 0, i64 65536) to i8*)
+	ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @src, i32 0, i64 65536) to i8*)
 ; LINUX-64-STATIC-LABEL: bam00:
 ; LINUX-64-STATIC: movl    $src+262144, %eax
 ; LINUX-64-STATIC: ret
@@ -6503,7 +6503,7 @@ entry:
 
 define i8* @bam01() nounwind {
 entry:
-	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536) to i8*)
+	ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @dst, i32 0, i64 65536) to i8*)
 ; LINUX-64-STATIC-LABEL: bam01:
 ; LINUX-64-STATIC: movl    $dst+262144, %eax
 ; LINUX-64-STATIC: ret
@@ -6556,7 +6556,7 @@ entry:
 
 define i8* @bxm01() nounwind {
 entry:
-	ret i8* bitcast (i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 65536) to i8*)
+	ret i8* bitcast (i32* getelementptr ([32 x i32], [32 x i32]* @xdst, i32 0, i64 65536) to i8*)
 ; LINUX-64-STATIC-LABEL: bxm01:
 ; LINUX-64-STATIC: movl    $xdst+262144, %eax
 ; LINUX-64-STATIC: ret
@@ -6609,8 +6609,8 @@ entry:
 
 define i8* @bam02() nounwind {
 entry:
-	%0 = load i32** @ptr, align 8
-	%1 = getelementptr i32* %0, i64 65536
+	%0 = load i32*, i32** @ptr, align 8
+	%1 = getelementptr i32, i32* %0, i64 65536
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: bam02:
@@ -6675,7 +6675,7 @@ entry:
 
 define i8* @bam03() nounwind {
 entry:
-	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 65536) to i8*)
+	ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @dsrc, i32 0, i64 65536) to i8*)
 ; LINUX-64-STATIC-LABEL: bam03:
 ; LINUX-64-STATIC: movl    $dsrc+262144, %eax
 ; LINUX-64-STATIC: ret
@@ -6723,7 +6723,7 @@ entry:
 
 define i8* @bam04() nounwind {
 entry:
-	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536) to i8*)
+	ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @ddst, i32 0, i64 65536) to i8*)
 ; LINUX-64-STATIC-LABEL: bam04:
 ; LINUX-64-STATIC: movl    $ddst+262144, %eax
 ; LINUX-64-STATIC: ret
@@ -6771,8 +6771,8 @@ entry:
 
 define i8* @bam05() nounwind {
 entry:
-	%0 = load i32** @dptr, align 8
-	%1 = getelementptr i32* %0, i64 65536
+	%0 = load i32*, i32** @dptr, align 8
+	%1 = getelementptr i32, i32* %0, i64 65536
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: bam05:
@@ -6832,7 +6832,7 @@ entry:
 
 define i8* @bam06() nounwind {
 entry:
-	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 65536) to i8*)
+	ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @lsrc, i32 0, i64 65536) to i8*)
 ; LINUX-64-STATIC-LABEL: bam06:
 ; LINUX-64-STATIC: movl    $lsrc+262144, %eax
 ; LINUX-64-STATIC: ret
@@ -6879,7 +6879,7 @@ entry:
 
 define i8* @bam07() nounwind {
 entry:
-	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536) to i8*)
+	ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @ldst, i32 0, i64 65536) to i8*)
 ; LINUX-64-STATIC-LABEL: bam07:
 ; LINUX-64-STATIC: movl    $ldst+262144, %eax
 ; LINUX-64-STATIC: ret
@@ -6926,8 +6926,8 @@ entry:
 
 define i8* @bam08() nounwind {
 entry:
-	%0 = load i32** @lptr, align 8
-	%1 = getelementptr i32* %0, i64 65536
+	%0 = load i32*, i32** @lptr, align 8
+	%1 = getelementptr i32, i32* %0, i64 65536
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: bam08:
@@ -6987,7 +6987,7 @@ entry:
 define i8* @cat00(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 16
-	%1 = getelementptr [131072 x i32]* @src, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @src, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cat00:
@@ -7048,7 +7048,7 @@ entry:
 define i8* @cxt00(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 16
-	%1 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %0
+	%1 = getelementptr [32 x i32], [32 x i32]* @xsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cxt00:
@@ -7109,7 +7109,7 @@ entry:
 define i8* @cat01(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 16
-	%1 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @dst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cat01:
@@ -7170,7 +7170,7 @@ entry:
 define i8* @cxt01(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 16
-	%1 = getelementptr [32 x i32]* @xdst, i64 0, i64 %0
+	%1 = getelementptr [32 x i32], [32 x i32]* @xdst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cxt01:
@@ -7230,9 +7230,9 @@ entry:
 
 define i8* @cat02(i64 %i) nounwind {
 entry:
-	%0 = load i32** @ptr, align 8
+	%0 = load i32*, i32** @ptr, align 8
 	%1 = add i64 %i, 16
-	%2 = getelementptr i32* %0, i64 %1
+	%2 = getelementptr i32, i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
 ; LINUX-64-STATIC-LABEL: cat02:
@@ -7303,7 +7303,7 @@ entry:
 define i8* @cat03(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 16
-	%1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @dsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cat03:
@@ -7362,7 +7362,7 @@ entry:
 define i8* @cat04(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 16
-	%1 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @ddst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cat04:
@@ -7420,9 +7420,9 @@ entry:
 
 define i8* @cat05(i64 %i) nounwind {
 entry:
-	%0 = load i32** @dptr, align 8
+	%0 = load i32*, i32** @dptr, align 8
 	%1 = add i64 %i, 16
-	%2 = getelementptr i32* %0, i64 %1
+	%2 = getelementptr i32, i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
 ; LINUX-64-STATIC-LABEL: cat05:
@@ -7488,7 +7488,7 @@ entry:
 define i8* @cat06(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 16
-	%1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @lsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cat06:
@@ -7547,7 +7547,7 @@ entry:
 define i8* @cat07(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 16
-	%1 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @ldst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cat07:
@@ -7605,9 +7605,9 @@ entry:
 
 define i8* @cat08(i64 %i) nounwind {
 entry:
-	%0 = load i32** @lptr, align 8
+	%0 = load i32*, i32** @lptr, align 8
 	%1 = add i64 %i, 16
-	%2 = getelementptr i32* %0, i64 %1
+	%2 = getelementptr i32, i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
 ; LINUX-64-STATIC-LABEL: cat08:
@@ -7672,7 +7672,7 @@ entry:
 define i8* @cam00(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 65536
-	%1 = getelementptr [131072 x i32]* @src, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @src, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cam00:
@@ -7733,7 +7733,7 @@ entry:
 define i8* @cxm00(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 65536
-	%1 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %0
+	%1 = getelementptr [32 x i32], [32 x i32]* @xsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cxm00:
@@ -7794,7 +7794,7 @@ entry:
 define i8* @cam01(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 65536
-	%1 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @dst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cam01:
@@ -7855,7 +7855,7 @@ entry:
 define i8* @cxm01(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 65536
-	%1 = getelementptr [32 x i32]* @xdst, i64 0, i64 %0
+	%1 = getelementptr [32 x i32], [32 x i32]* @xdst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cxm01:
@@ -7915,9 +7915,9 @@ entry:
 
 define i8* @cam02(i64 %i) nounwind {
 entry:
-	%0 = load i32** @ptr, align 8
+	%0 = load i32*, i32** @ptr, align 8
 	%1 = add i64 %i, 65536
-	%2 = getelementptr i32* %0, i64 %1
+	%2 = getelementptr i32, i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
 ; LINUX-64-STATIC-LABEL: cam02:
@@ -7988,7 +7988,7 @@ entry:
 define i8* @cam03(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 65536
-	%1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @dsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cam03:
@@ -8047,7 +8047,7 @@ entry:
 define i8* @cam04(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 65536
-	%1 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @ddst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cam04:
@@ -8105,9 +8105,9 @@ entry:
 
 define i8* @cam05(i64 %i) nounwind {
 entry:
-	%0 = load i32** @dptr, align 8
+	%0 = load i32*, i32** @dptr, align 8
 	%1 = add i64 %i, 65536
-	%2 = getelementptr i32* %0, i64 %1
+	%2 = getelementptr i32, i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
 ; LINUX-64-STATIC-LABEL: cam05:
@@ -8173,7 +8173,7 @@ entry:
 define i8* @cam06(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 65536
-	%1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @lsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cam06:
@@ -8232,7 +8232,7 @@ entry:
 define i8* @cam07(i64 %i) nounwind {
 entry:
 	%0 = add i64 %i, 65536
-	%1 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
+	%1 = getelementptr [131072 x i32], [131072 x i32]* @ldst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
 ; LINUX-64-STATIC-LABEL: cam07:
@@ -8290,9 +8290,9 @@ entry:
 
 define i8* @cam08(i64 %i) nounwind {
 entry:
-	%0 = load i32** @lptr, align 8
+	%0 = load i32*, i32** @lptr, align 8
 	%1 = add i64 %i, 65536
-	%2 = getelementptr i32* %0, i64 %1
+	%2 = getelementptr i32, i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
 ; LINUX-64-STATIC-LABEL: cam08:
@@ -9180,9 +9180,9 @@ entry:
 
 define void @icaller() nounwind {
 entry:
-	%0 = load void ()** @ifunc, align 8
+	%0 = load void ()*, void ()** @ifunc, align 8
 	call void %0() nounwind
-	%1 = load void ()** @ifunc, align 8
+	%1 = load void ()*, void ()** @ifunc, align 8
 	call void %1() nounwind
 	ret void
 ; LINUX-64-STATIC-LABEL: icaller:
@@ -9270,9 +9270,9 @@ entry:
 
 define void @dicaller() nounwind {
 entry:
-	%0 = load void ()** @difunc, align 8
+	%0 = load void ()*, void ()** @difunc, align 8
 	call void %0() nounwind
-	%1 = load void ()** @difunc, align 8
+	%1 = load void ()*, void ()** @difunc, align 8
 	call void %1() nounwind
 	ret void
 ; LINUX-64-STATIC-LABEL: dicaller:
@@ -9353,9 +9353,9 @@ entry:
 
 define void @licaller() nounwind {
 entry:
-	%0 = load void ()** @lifunc, align 8
+	%0 = load void ()*, void ()** @lifunc, align 8
 	call void %0() nounwind
-	%1 = load void ()** @lifunc, align 8
+	%1 = load void ()*, void ()** @lifunc, align 8
 	call void %1() nounwind
 	ret void
 ; LINUX-64-STATIC-LABEL: licaller:
@@ -9435,9 +9435,9 @@ entry:
 
 define void @itailcaller() nounwind {
 entry:
-	%0 = load void ()** @ifunc, align 8
+	%0 = load void ()*, void ()** @ifunc, align 8
 	call void %0() nounwind
-	%1 = load void ()** @ifunc, align 8
+	%1 = load void ()*, void ()** @ifunc, align 8
 	call void %1() nounwind
 	ret void
 ; LINUX-64-STATIC-LABEL: itailcaller:
@@ -9525,7 +9525,7 @@ entry:
 
 define void @ditailcaller() nounwind {
 entry:
-	%0 = load void ()** @difunc, align 8
+	%0 = load void ()*, void ()** @difunc, align 8
 	call void %0() nounwind
 	ret void
 ; LINUX-64-STATIC-LABEL: ditailcaller:
@@ -9593,7 +9593,7 @@ entry:
 
 define void @litailcaller() nounwind {
 entry:
-	%0 = load void ()** @lifunc, align 8
+	%0 = load void ()*, void ()** @lifunc, align 8
 	call void %0() nounwind
 	ret void
 ; LINUX-64-STATIC-LABEL: litailcaller:
diff --git a/test/CodeGen/X86/add-of-carry.ll b/test/CodeGen/X86/add-of-carry.ll
index 9c24be4289ff..44b587af3aaa 100644
--- a/test/CodeGen/X86/add-of-carry.ll
+++ b/test/CodeGen/X86/add-of-carry.ll
@@ -4,43 +4,26 @@
 define i32 @test1(i32 %sum, i32 %x) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: test1:
-; CHECK: cmpl %ecx, %eax 
-; CHECK-NOT: addl
-; CHECK: adcl $0, %eax
-  %add4 = add i32 %x, %sum
-  %cmp = icmp ult i32 %add4, %x
-  %inc = zext i1 %cmp to i32
-  %z.0 = add i32 %add4, %inc
-  ret i32 %z.0
-}
-
-; Instcombine transforms test1 into test2:
-; CHECK-LABEL: test2:
 ; CHECK: movl
 ; CHECK-NEXT: addl
 ; CHECK-NEXT: adcl $0
 ; CHECK-NEXT: ret
-define i32 @test2(i32 %sum, i32 %x) nounwind readnone ssp {
-entry:
-  %uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x, i32 %sum)
-  %0 = extractvalue { i32, i1 } %uadd, 0
-  %cmp = extractvalue { i32, i1 } %uadd, 1
+  %add4 = add i32 %x, %sum
+  %cmp = icmp ult i32 %add4, %x
   %inc = zext i1 %cmp to i32
-  %z.0 = add i32 %0, %inc
+  %z.0 = add i32 %add4, %inc
   ret i32 %z.0
 }
 
 ; <rdar://problem/12579915>
-define i32 @test3(i32 %x, i32 %y, i32 %res) nounwind uwtable readnone ssp {
+define i32 @test2(i32 %x, i32 %y, i32 %res) nounwind uwtable readnone ssp {
 entry:
   %cmp = icmp ugt i32 %x, %y
   %dec = sext i1 %cmp to i32
   %dec.res = add nsw i32 %dec, %res
   ret i32 %dec.res
-; CHECK-LABEL: test3:
+; CHECK-LABEL: test2:
 ; CHECK: cmpl
 ; CHECK: sbbl
 ; CHECK: ret
 }
-
-declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
diff --git a/test/CodeGen/X86/add32ri8.ll b/test/CodeGen/X86/add32ri8.ll
new file mode 100644
index 000000000000..a74c37280cdc
--- /dev/null
+++ b/test/CodeGen/X86/add32ri8.ll
@@ -0,0 +1,10 @@
+; RUN: llc -mtriple=x86_64-linux -fast-isel -show-mc-encoding < %s | FileCheck %s
+
+; pr22854
+; CHECK: addl	$42, %esi               # encoding: [0x83,0xc6,0x2a]
+
+define void @foo(i32 *%s, i32 %x) {
+  %y = add nsw i32 %x, 42
+  store i32 %y, i32* %s, align 4
+  ret void
+}
diff --git a/test/CodeGen/X86/addr-mode-matcher.ll b/test/CodeGen/X86/addr-mode-matcher.ll
index d5920910f289..83d6858bda1c 100644
--- a/test/CodeGen/X86/addr-mode-matcher.ll
+++ b/test/CodeGen/X86/addr-mode-matcher.ll
@@ -24,16 +24,16 @@ bb1692:
 ; %load1 = (load (and (shl %xor, 2), 1020))
   %tmp1701 = shl i32 %xor, 2
   %tmp1702 = and i32 %tmp1701, 1020
-  %tmp1703 = getelementptr inbounds [1028 x i8]* null, i32 0, i32 %tmp1702
+  %tmp1703 = getelementptr inbounds [1028 x i8], [1028 x i8]* null, i32 0, i32 %tmp1702
   %tmp1704 = bitcast i8* %tmp1703 to i32*
-  %load1 = load i32* %tmp1704, align 4
+  %load1 = load i32, i32* %tmp1704, align 4
 
 ; %load2 = (load (shl (and %xor, 255), 2))
   %tmp1698 = and i32 %xor, 255
   %tmp1706 = shl i32 %tmp1698, 2
-  %tmp1707 = getelementptr inbounds [1028 x i8]* null, i32 0, i32 %tmp1706
+  %tmp1707 = getelementptr inbounds [1028 x i8], [1028 x i8]* null, i32 0, i32 %tmp1706
   %tmp1708 = bitcast i8* %tmp1707 to i32*
-  %load2 = load i32* %tmp1708, align 4
+  %load2 = load i32, i32* %tmp1708, align 4
 
   %tmp1710 = or i32 %load2, %a
 
@@ -43,7 +43,7 @@ bb1692:
 ; references in MatchScope and RecordedNodes stale.
   %tmp1711 = xor i32 %load1, %tmp1710
 
-  %tmp1744 = getelementptr inbounds [256 x i32]* null, i32 0, i32 %tmp1711
+  %tmp1744 = getelementptr inbounds [256 x i32], [256 x i32]* null, i32 0, i32 %tmp1711
   store i32 0, i32* %tmp1744, align 4
   %tmp1745 = add i32 %tmp1694, 1
   indirectbr i8* undef, [label %bb1756, label %bb1692]
diff --git a/test/CodeGen/X86/address-type-promotion-constantexpr.ll b/test/CodeGen/X86/address-type-promotion-constantexpr.ll
index 32f29bd3cad9..fe115b9295da 100644
--- a/test/CodeGen/X86/address-type-promotion-constantexpr.ll
+++ b/test/CodeGen/X86/address-type-promotion-constantexpr.ll
@@ -10,7 +10,7 @@
 ; CHECK: xor %eax, %eax
 define i32 @main() {
 entry:
-  %foo = load i8* getelementptr ([2 x i8]* @b, i64 0, i64 sext (i8 or (i8 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32]* @c, i64 0, i64 1), i32* @a) to i8), i8 1) to i64)), align 1
+  %foo = load i8, i8* getelementptr ([2 x i8], [2 x i8]* @b, i64 0, i64 sext (i8 or (i8 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @c, i64 0, i64 1), i32* @a) to i8), i8 1) to i64)), align 1
   ret i32 0
 }
 
diff --git a/test/CodeGen/X86/aliases.ll b/test/CodeGen/X86/aliases.ll
index 82a8e482b7fa..3f19a064323c 100644
--- a/test/CodeGen/X86/aliases.ll
+++ b/test/CodeGen/X86/aliases.ll
@@ -49,7 +49,7 @@ define i32 @foo_f() {
 @bar_p = protected alias i32* @bar
 
 ; CHECK-DAG: test2 = bar+4
-@test2 = alias getelementptr(i32 *@bar, i32 1)
+@test2 = alias getelementptr(i32, i32 *@bar, i32 1)
 
 ; CHECK-DAG: test3 = 42
 @test3 = alias inttoptr(i32 42 to i32*)
@@ -64,12 +64,12 @@ define i32 @foo_f() {
 ; CHECK-DAG: .globl	test
 define i32 @test() {
 entry:
-   %tmp = load i32* @foo1
-   %tmp1 = load i32* @foo2
-   %tmp0 = load i32* @bar_i
+   %tmp = load i32, i32* @foo1
+   %tmp1 = load i32, i32* @foo2
+   %tmp0 = load i32, i32* @bar_i
    %tmp2 = call i32 @foo_f()
    %tmp3 = add i32 %tmp, %tmp2
-   %tmp4 = call %FunTy* @bar_f()
+   %tmp4 = call i32 @bar_f()
    %tmp5 = add i32 %tmp3, %tmp4
    %tmp6 = add i32 %tmp1, %tmp5
    %tmp7 = add i32 %tmp6, %tmp0
diff --git a/test/CodeGen/X86/aligned-variadic.ll b/test/CodeGen/X86/aligned-variadic.ll
index e2155fe4b373..294159220626 100644
--- a/test/CodeGen/X86/aligned-variadic.ll
+++ b/test/CodeGen/X86/aligned-variadic.ll
@@ -8,12 +8,12 @@
 define void @bar(%struct.Baz* byval nocapture readnone align 8 %x, ...) {
 entry:
   %va = alloca [1 x %struct.__va_list_tag], align 16
-  %arraydecay = getelementptr inbounds [1 x %struct.__va_list_tag]* %va, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %va, i64 0, i64 0
   %arraydecay1 = bitcast [1 x %struct.__va_list_tag]* %va to i8*
   call void @llvm.va_start(i8* %arraydecay1)
-  %overflow_arg_area_p = getelementptr inbounds [1 x %struct.__va_list_tag]* %va, i64 0, i64 0, i32 2
-  %overflow_arg_area = load i8** %overflow_arg_area_p, align 8
-  %overflow_arg_area.next = getelementptr i8* %overflow_arg_area, i64 24
+  %overflow_arg_area_p = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %va, i64 0, i64 0, i32 2
+  %overflow_arg_area = load i8*, i8** %overflow_arg_area_p, align 8
+  %overflow_arg_area.next = getelementptr i8, i8* %overflow_arg_area, i64 24
   store i8* %overflow_arg_area.next, i8** %overflow_arg_area_p, align 8
 ; X32: leal    68(%esp), [[REG:%.*]]
 ; X32: movl    [[REG]], 16(%esp)
diff --git a/test/CodeGen/X86/alignment-2.ll b/test/CodeGen/X86/alignment-2.ll
index 1f9e85cbb763..a38a3626702a 100644
--- a/test/CodeGen/X86/alignment-2.ll
+++ b/test/CodeGen/X86/alignment-2.ll
@@ -23,7 +23,7 @@ bb:
 ; CHECK-NOT: movaps {{[0-9]*}}(%{{[a-z]*}}), {{%xmm[0-9]}}
   %myopt = alloca %struct.printQueryOpt, align 4
   %tmp = bitcast %struct.printQueryOpt* %myopt to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp, i8* bitcast (%struct.printQueryOpt* getelementptr inbounds (%struct._psqlSettings* @pset, i32 0, i32 4) to i8*), i32 76, i32 4, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp, i8* bitcast (%struct.printQueryOpt* getelementptr inbounds (%struct._psqlSettings, %struct._psqlSettings* @pset, i32 0, i32 4) to i8*), i32 76, i32 4, i1 false)
   ret i8 0
 }
 
diff --git a/test/CodeGen/X86/and-load-fold.ll b/test/CodeGen/X86/and-load-fold.ll
index d6f68b3bc433..29ab3242ce26 100644
--- a/test/CodeGen/X86/and-load-fold.ll
+++ b/test/CodeGen/X86/and-load-fold.ll
@@ -8,7 +8,7 @@ define i8 @foo(<4 x i8>* %V) {
 ; CHECK: ret
 entry:
   %Vp = bitcast <4 x i8>* %V to <3 x i8>*
-  %V3i8 = load <3 x i8>* %Vp, align 4
+  %V3i8 = load <3 x i8>, <3 x i8>* %Vp, align 4
   %0 = and <3 x i8> %V3i8, <i8 undef, i8 undef, i8 95>
   %1 = extractelement <3 x i8> %0, i64 2
   ret i8 %1
diff --git a/test/CodeGen/X86/and-or-fold.ll b/test/CodeGen/X86/and-or-fold.ll
index 836b5f1551c7..ec39522e6b10 100644
--- a/test/CodeGen/X86/and-or-fold.ll
+++ b/test/CodeGen/X86/and-or-fold.ll
@@ -21,6 +21,6 @@ entry:
   %tmp1 = and i64 %x, 123127
   %tmp2 = or i64 %tmp1, 3
   ret i64 %tmp2
-; DARWIN-OPT:       andq $123124
+; DARWIN-OPT:       andl $123124
 ; DARWIN-OPT-NEXT:  leaq 3
 }
diff --git a/test/CodeGen/X86/and-su.ll b/test/CodeGen/X86/and-su.ll
index 70c24615a7e2..bdbab1535016 100644
--- a/test/CodeGen/X86/and-su.ll
+++ b/test/CodeGen/X86/and-su.ll
@@ -6,7 +6,7 @@ define fastcc i32 @foo(i32* %p) nounwind {
 ; CHECK-LABEL: foo:
 ; CHECK: andl $10, %eax
 ; CHECK: je
-	%t0 = load i32* %p
+	%t0 = load i32, i32* %p
 	%t2 = and i32 %t0, 10
 	%t3 = icmp ne i32 %t2, 0
 	br i1 %t3, label %bb63, label %bb76
diff --git a/test/CodeGen/X86/andimm8.ll b/test/CodeGen/X86/andimm8.ll
index 640237d0b504..d9e676aa66c5 100644
--- a/test/CodeGen/X86/andimm8.ll
+++ b/test/CodeGen/X86/andimm8.ll
@@ -17,3 +17,15 @@ define void @foo(i64 %zed, i64* %x) nounwind {
   store i64 %t2, i64* %x, align 8
   ret void
 }
+
+define i64 @bar(i64 %zed) nounwind {
+; CHECK:  andl     $42, %edi               # encoding: [0x83,0xe7,0x2a]
+  %t1 = and i64 %zed, 42
+  ret i64 %t1
+}
+
+define i64 @baz(i64 %zed) nounwind {
+; CHECK:  andl $2147483647, %edi      # encoding: [0x81,0xe7,0xff,0xff,0xff,0x7f]
+  %t1 = and i64 %zed, 2147483647
+  ret i64 %t1
+}
diff --git a/test/CodeGen/X86/anyregcc-crash.ll b/test/CodeGen/X86/anyregcc-crash.ll
index 3abe3d149a11..a7c104e3ba4c 100644
--- a/test/CodeGen/X86/anyregcc-crash.ll
+++ b/test/CodeGen/X86/anyregcc-crash.ll
@@ -7,7 +7,7 @@ define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6,
                         i64 %v7, i64 %v8, i64 %v9, i64 %v10, i64 %v11, i64 %v12,
                         i64 %v13, i64 %v14, i64 %v15, i64 %v16) {
 entry:
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 16,
+  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 16,
                 i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6,
                 i64 %v7, i64 %v8, i64 %v9, i64 %v10, i64 %v11, i64 %v12,
                 i64 %v13, i64 %v14, i64 %v15, i64 %v16)
diff --git a/test/CodeGen/X86/anyregcc.ll b/test/CodeGen/X86/anyregcc.ll
index 98ba17c74c82..129aadfae88d 100644
--- a/test/CodeGen/X86/anyregcc.ll
+++ b/test/CodeGen/X86/anyregcc.ll
@@ -60,7 +60,7 @@
 ; CHECK-NEXT:   .long 3
 define i64 @test() nounwind ssp uwtable {
 entry:
-  call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 0, i32 15, i8* null, i32 2, i32 1, i32 2, i64 3)
+  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 15, i8* null, i32 2, i32 1, i32 2, i64 3)
   ret i64 0
 }
 
@@ -82,7 +82,7 @@ entry:
 define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 12297829382473034410 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 1, i32 15, i8* %f, i32 1, i8* %obj)
+  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 15, i8* %f, i32 1, i8* %obj)
   ret i64 %ret
 }
 
@@ -105,7 +105,7 @@ define i64 @property_access2() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
   %f = inttoptr i64 12297829382473034410 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %f, i32 1, i64* %obj)
+  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %f, i32 1, i64* %obj)
   ret i64 %ret
 }
 
@@ -128,7 +128,7 @@ define i64 @property_access3() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
   %f = inttoptr i64 12297829382473034410 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 15, i8* %f, i32 0, i64* %obj)
+  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 15, i8* %f, i32 0, i64* %obj)
   ret i64 %ret
 }
 
@@ -210,7 +210,7 @@ entry:
 define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 12297829382473034410 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 4, i32 15, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
+  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 15, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
   ret i64 %ret
 }
 
@@ -292,7 +292,7 @@ entry:
 define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 12297829382473034410 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
+  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
   ret i64 %ret
 }
 
@@ -320,7 +320,7 @@ entry:
 ; CHECK-NEXT: .long  0
 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
+  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
   tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
   ret i64 %result
 }
@@ -360,7 +360,7 @@ entry:
 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
   tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 13, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
+  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
   ret i64 %result
 }
 
diff --git a/test/CodeGen/X86/asm-global-imm.ll b/test/CodeGen/X86/asm-global-imm.ll
index 9e79f6f78222..82610114ad34 100644
--- a/test/CodeGen/X86/asm-global-imm.ll
+++ b/test/CodeGen/X86/asm-global-imm.ll
@@ -21,6 +21,6 @@ define void @foo() {
 
 define void @unknown_bootoption() {
 entry:
-	call void asm sideeffect "ud2\0A\09.word ${0:c}\0A\09.long ${1:c}\0A", "i,i,~{dirflag},~{fpsr},~{flags}"( i32 235, i8* getelementptr ([12 x i8]* @str, i32 0, i64 0) )
+	call void asm sideeffect "ud2\0A\09.word ${0:c}\0A\09.long ${1:c}\0A", "i,i,~{dirflag},~{fpsr},~{flags}"( i32 235, i8* getelementptr ([12 x i8], [12 x i8]* @str, i32 0, i64 0) )
 	ret void
 }
diff --git a/test/CodeGen/X86/atom-call-reg-indirect-foldedreload32.ll b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload32.ll
index 6237b66a5ea6..2e144f87c338 100644
--- a/test/CodeGen/X86/atom-call-reg-indirect-foldedreload32.ll
+++ b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload32.ll
@@ -36,34 +36,34 @@
 define void @func() #0 {
 entry:
   store i32 0, i32* @sum, align 4
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   store i32 %0, i32* @i, align 4
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %1 = load i32* @i, align 4
-  %2 = load i32* @b, align 4
+  %1 = load i32, i32* @i, align 4
+  %2 = load i32, i32* @b, align 4
   %cmp = icmp slt i32 %1, %2
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %3 = load i32 (i32, i32, i32, i32, i32, i32, i32, i32)** @funcp, align 4
-  %4 = load i32* @i, align 4
-  %5 = load i32* @b, align 4
-  %6 = load i32* @c, align 4
-  %7 = load i32* @d, align 4
-  %8 = load i32* @e, align 4
-  %9 = load i32* @f, align 4
-  %10 = load i32* @g, align 4
-  %11 = load i32* @h, align 4
+  %3 = load i32 (i32, i32, i32, i32, i32, i32, i32, i32)*, i32 (i32, i32, i32, i32, i32, i32, i32, i32)** @funcp, align 4
+  %4 = load i32, i32* @i, align 4
+  %5 = load i32, i32* @b, align 4
+  %6 = load i32, i32* @c, align 4
+  %7 = load i32, i32* @d, align 4
+  %8 = load i32, i32* @e, align 4
+  %9 = load i32, i32* @f, align 4
+  %10 = load i32, i32* @g, align 4
+  %11 = load i32, i32* @h, align 4
   %call = call i32 %3(i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11)
-  %12 = load i32* @sum, align 4
+  %12 = load i32, i32* @sum, align 4
   %add = add nsw i32 %12, %call
   store i32 %add, i32* @sum, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %13 = load i32* @i, align 4
+  %13 = load i32, i32* @i, align 4
   %inc = add nsw i32 %13, 1
   store i32 %inc, i32* @i, align 4
   br label %for.cond
diff --git a/test/CodeGen/X86/atom-call-reg-indirect-foldedreload64.ll b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload64.ll
index a196d8175aa9..e82626ced206 100644
--- a/test/CodeGen/X86/atom-call-reg-indirect-foldedreload64.ll
+++ b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload64.ll
@@ -42,43 +42,43 @@
 define void @func() #0 {
 entry:
   store i32 0, i32* @sum, align 4
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   store i32 %0, i32* @i, align 4
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %1 = load i32* @i, align 4
-  %2 = load i32* @b, align 4
+  %1 = load i32, i32* @i, align 4
+  %2 = load i32, i32* @b, align 4
   %cmp = icmp slt i32 %1, %2
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %3 = load i32 (i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)** @funcp, align 8
-  %4 = load i32* @a, align 4
-  %5 = load i32* @i, align 4
-  %6 = load i32* @i, align 4
+  %3 = load i32 (i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)*, i32 (i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)** @funcp, align 8
+  %4 = load i32, i32* @a, align 4
+  %5 = load i32, i32* @i, align 4
+  %6 = load i32, i32* @i, align 4
   %mul = mul nsw i32 %6, 2
-  %7 = load i32* @i, align 4
-  %8 = load i32* @b, align 4
+  %7 = load i32, i32* @i, align 4
+  %8 = load i32, i32* @b, align 4
   %div = sdiv i32 %7, %8
-  %9 = load i32* @c, align 4
-  %10 = load i32* @d, align 4
-  %11 = load i32* @e, align 4
-  %12 = load i32* @f, align 4
-  %13 = load i32* @g, align 4
-  %14 = load i32* @h, align 4
-  %15 = load i32* @j, align 4
-  %16 = load i32* @k, align 4
-  %17 = load i32* @l, align 4
-  %18 = load i32* @n, align 4
+  %9 = load i32, i32* @c, align 4
+  %10 = load i32, i32* @d, align 4
+  %11 = load i32, i32* @e, align 4
+  %12 = load i32, i32* @f, align 4
+  %13 = load i32, i32* @g, align 4
+  %14 = load i32, i32* @h, align 4
+  %15 = load i32, i32* @j, align 4
+  %16 = load i32, i32* @k, align 4
+  %17 = load i32, i32* @l, align 4
+  %18 = load i32, i32* @n, align 4
   %call = call i32 %3(i32 %4, i32 %5, i32 %mul, i32 %div, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, i32 %14, i32 %15, i32 %16, i32 %17, i32 %18)
-  %19 = load i32* @sum, align 4
+  %19 = load i32, i32* @sum, align 4
   %add = add nsw i32 %19, %call
   store i32 %add, i32* @sum, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %20 = load i32* @i, align 4
+  %20 = load i32, i32* @i, align 4
   %inc = add nsw i32 %20, 1
   store i32 %inc, i32* @i, align 4
   br label %for.cond
diff --git a/test/CodeGen/X86/atom-call-reg-indirect.ll b/test/CodeGen/X86/atom-call-reg-indirect.ll
index 48f2d4c11346..663b6f1eee51 100644
--- a/test/CodeGen/X86/atom-call-reg-indirect.ll
+++ b/test/CodeGen/X86/atom-call-reg-indirect.ll
@@ -14,8 +14,8 @@ define i32 @test1() #0 {
 entry:
   %call = tail call %class.A* @_Z3facv()
   %0 = bitcast %class.A* %call to void (%class.A*)***
-  %vtable = load void (%class.A*)*** %0, align 8
-  %1 = load void (%class.A*)** %vtable, align 8
+  %vtable = load void (%class.A*)**, void (%class.A*)*** %0, align 8
+  %1 = load void (%class.A*)*, void (%class.A*)** %vtable, align 8
   ;ATOM32: movl (%ecx), %ecx
   ;ATOM32: calll *%ecx
   ;ATOM-NOT32: calll *(%ecx)
@@ -38,8 +38,8 @@ declare %class.A* @_Z3facv() #1
 define i32 @test2() #0 {
   ;ATOM-LABEL: test2:
 entry:
-  %0 = load void (i32)*** @p, align 8
-  %1 = load void (i32)** %0, align 8
+  %0 = load void (i32)**, void (i32)*** @p, align 8
+  %1 = load void (i32)*, void (i32)** %0, align 8
   ;ATOM32: movl (%eax), %eax
   ;ATOM32: calll *%eax
   ;ATOM-NOT: calll *(%eax)
diff --git a/test/CodeGen/X86/atom-cmpb.ll b/test/CodeGen/X86/atom-cmpb.ll
index 034bf2f27d25..baf0f5e87fc9 100644
--- a/test/CodeGen/X86/atom-cmpb.ll
+++ b/test/CodeGen/X86/atom-cmpb.ll
@@ -11,10 +11,10 @@
  
 define i8 @run_test(i8* %rd_p) {
 entry:
-  %incdec.ptr = getelementptr inbounds i8* %rd_p, i64 1
-  %ld1 = load i8* %rd_p, align 1
-  %incdec.ptr1 = getelementptr inbounds i8* %rd_p, i64 2
-  %ld2 = load i8* %incdec.ptr, align 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %rd_p, i64 1
+  %ld1 = load i8, i8* %rd_p, align 1
+  %incdec.ptr1 = getelementptr inbounds i8, i8* %rd_p, i64 2
+  %ld2 = load i8, i8* %incdec.ptr, align 1
   %x4 = xor i8 %ld1, -1
   %x5 = xor i8 %ld2, -1
   %cmp34 = icmp ult i8 %ld2, %ld1
diff --git a/test/CodeGen/X86/atom-fixup-lea1.ll b/test/CodeGen/X86/atom-fixup-lea1.ll
index 4651bf257fd4..f862fa6dfc35 100644
--- a/test/CodeGen/X86/atom-fixup-lea1.ll
+++ b/test/CodeGen/X86/atom-fixup-lea1.ll
@@ -25,8 +25,8 @@ entry:
 for.body:
   %i.06 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
   %sum.05 = phi i32 [ %add, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %array, i32 %i.06
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %array, i32 %i.06
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %sum.05
   %inc = add nsw i32 %i.06, 1
   %exitcond = icmp eq i32 %inc, %n
diff --git a/test/CodeGen/X86/atom-fixup-lea2.ll b/test/CodeGen/X86/atom-fixup-lea2.ll
index 1855ea1d024d..ec8261388734 100644
--- a/test/CodeGen/X86/atom-fixup-lea2.ll
+++ b/test/CodeGen/X86/atom-fixup-lea2.ll
@@ -37,32 +37,32 @@ define i32 @test() {
 entry:
   %n = alloca %struct.node_t, align 4
   call void bitcast (void (%struct.node_t*, ...)* @getnode to void (%struct.node_t*)*)(%struct.node_t* sret %n)
-  %array = getelementptr inbounds %struct.node_t* %n, i32 0, i32 4
-  %0 = load i32** %array, align 4
+  %array = getelementptr inbounds %struct.node_t, %struct.node_t* %n, i32 0, i32 4
+  %0 = load i32*, i32** %array, align 4
   %cmp = icmp eq i32* %0, null
   br i1 %cmp, label %if.end, label %land.lhs.true
 
 land.lhs.true:
-  %p = getelementptr inbounds %struct.node_t* %n, i32 0, i32 3
-  %1 = load i32* %p, align 4
+  %p = getelementptr inbounds %struct.node_t, %struct.node_t* %n, i32 0, i32 3
+  %1 = load i32, i32* %p, align 4
   %cmp1 = icmp sgt i32 %1, 0
   br i1 %cmp1, label %land.lhs.true2, label %if.end
 
 land.lhs.true2:
-  %k = getelementptr inbounds %struct.node_t* %n, i32 0, i32 0
-  %2 = load i32* %k, align 4
+  %k = getelementptr inbounds %struct.node_t, %struct.node_t* %n, i32 0, i32 0
+  %2 = load i32, i32* %k, align 4
   %cmp3 = icmp sgt i32 %2, 0
   br i1 %cmp3, label %land.lhs.true4, label %if.end
 
 land.lhs.true4:
-  %n5 = getelementptr inbounds %struct.node_t* %n, i32 0, i32 2
-  %3 = load i32* %n5, align 4
+  %n5 = getelementptr inbounds %struct.node_t, %struct.node_t* %n, i32 0, i32 2
+  %3 = load i32, i32* %n5, align 4
   %cmp6 = icmp sgt i32 %3, 0
   br i1 %cmp6, label %land.lhs.true7, label %if.end
 
 land.lhs.true7:
-  %m = getelementptr inbounds %struct.node_t* %n, i32 0, i32 1
-  %4 = load i32* %m, align 4
+  %m = getelementptr inbounds %struct.node_t, %struct.node_t* %n, i32 0, i32 1
+  %4 = load i32, i32* %m, align 4
   %cmp8 = icmp sgt i32 %4, 0
   br i1 %cmp8, label %if.then, label %if.end
 
@@ -72,8 +72,8 @@ if.then:
   %5 = ptrtoint i32* %0 to i32
   %add15 = add nsw i32 %1, %5
   %6 = inttoptr i32 %add15 to i32*
-  %arrayidx = getelementptr inbounds i32* %6, i32 %add12
-  %7 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %6, i32 %add12
+  %7 = load i32, i32* %arrayidx, align 4
   br label %if.end
 
 if.end:
diff --git a/test/CodeGen/X86/atom-fixup-lea3.ll b/test/CodeGen/X86/atom-fixup-lea3.ll
index 311b0b302163..ed2df277480e 100644
--- a/test/CodeGen/X86/atom-fixup-lea3.ll
+++ b/test/CodeGen/X86/atom-fixup-lea3.ll
@@ -26,7 +26,7 @@ entry:
   br i1 %cmp7, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry
-  %.pre = load i32* %m, align 4
+  %.pre = load i32, i32* %m, align 4
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %for.body.lr.ph
@@ -34,12 +34,12 @@ for.body:                                         ; preds = %for.body, %for.body
   %sum.010 = phi i32 [ 0, %for.body.lr.ph ], [ %add3, %for.body ]
   %j.09 = phi i32 [ 0, %for.body.lr.ph ], [ %inc1, %for.body ]
   %inc1 = add nsw i32 %j.09, 1
-  %arrayidx = getelementptr inbounds i32* %array2, i32 %j.09
-  %1 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %array2, i32 %j.09
+  %1 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %1
   store i32 %add, i32* %m, align 4
-  %arrayidx2 = getelementptr inbounds i32* %array, i32 %inc1
-  %2 = load i32* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %array, i32 %inc1
+  %2 = load i32, i32* %arrayidx2, align 4
   %add3 = add nsw i32 %2, %sum.010
   %exitcond = icmp eq i32 %inc1, %n
   br i1 %exitcond, label %for.end, label %for.body
diff --git a/test/CodeGen/X86/atom-fixup-lea4.ll b/test/CodeGen/X86/atom-fixup-lea4.ll
index 668574b968c8..f0da1d2015cc 100644
--- a/test/CodeGen/X86/atom-fixup-lea4.ll
+++ b/test/CodeGen/X86/atom-fixup-lea4.ll
@@ -10,8 +10,8 @@ define linkonce_odr void @_ZN12ValueWrapperIS_IS_IS_IdEEEEC2Ev(%struct.ValueWrap
 entry:
   %this.addr = alloca %struct.ValueWrapper.6*, align 8
   store %struct.ValueWrapper.6* %this, %struct.ValueWrapper.6** %this.addr, align 8
-  %this1 = load %struct.ValueWrapper.6** %this.addr
-  %value = getelementptr inbounds %struct.ValueWrapper.6* %this1, i32 0, i32 0
+  %this1 = load %struct.ValueWrapper.6*, %struct.ValueWrapper.6** %this.addr
+  %value = getelementptr inbounds %struct.ValueWrapper.6, %struct.ValueWrapper.6* %this1, i32 0, i32 0
   call void @_ZN12ValueWrapperIS_IS_IdEEEC2Ev(%struct.ValueWrapper.7* %value)
   ret void
 }
diff --git a/test/CodeGen/X86/atom-lea-addw-bug.ll b/test/CodeGen/X86/atom-lea-addw-bug.ll
index 5cda2df432fc..d8147e5fbef9 100644
--- a/test/CodeGen/X86/atom-lea-addw-bug.ll
+++ b/test/CodeGen/X86/atom-lea-addw-bug.ll
@@ -5,9 +5,9 @@ target triple = "x86_64-apple-darwin12.5.0"
 
 define i32 @DoLayout() {
 entry:
-  %tmp1 = load i16* undef, align 2
-  %tmp17 = load i16* null, align 2
-  %tmp19 = load i16* undef, align 2
+  %tmp1 = load i16, i16* undef, align 2
+  %tmp17 = load i16, i16* null, align 2
+  %tmp19 = load i16, i16* undef, align 2
   %shl = shl i16 %tmp19, 1
   %add55 = add i16 %tmp17, %tmp1
   %add57 = add i16 %add55, %shl
diff --git a/test/CodeGen/X86/atom-lea-sp.ll b/test/CodeGen/X86/atom-lea-sp.ll
index 1df1974dc494..1ee3b00ee87e 100644
--- a/test/CodeGen/X86/atom-lea-sp.ll
+++ b/test/CodeGen/X86/atom-lea-sp.ll
@@ -16,7 +16,7 @@ define void @test1() nounwind {
 ; CHECK: call
 ; CHECK-NOT: lea
   %arr = alloca [1024 x i8], align 16
-  %arr_ptr = getelementptr inbounds [1024 x i8]* %arr, i8 0, i8 0
+  %arr_ptr = getelementptr inbounds [1024 x i8], [1024 x i8]* %arr, i8 0, i8 0
   call void @use_arr(i8* %arr_ptr)
   ret void
 }
diff --git a/test/CodeGen/X86/atom-sched.ll b/test/CodeGen/X86/atom-sched.ll
index fd18472bff8a..b81359e2832b 100644
--- a/test/CodeGen/X86/atom-sched.ll
+++ b/test/CodeGen/X86/atom-sched.ll
@@ -21,12 +21,12 @@ define void @func() nounwind uwtable {
 ; CHECK: movl
 ; CHECK: imull
 entry:
-  %0 = load i32* @b, align 4
-  %1 = load i32* @c, align 4
+  %0 = load i32, i32* @b, align 4
+  %1 = load i32, i32* @c, align 4
   %mul = mul nsw i32 %0, %1
   store i32 %mul, i32* @a, align 4
-  %2 = load i32* @e, align 4
-  %3 = load i32* @f, align 4
+  %2 = load i32, i32* @e, align 4
+  %3 = load i32, i32* @f, align 4
   %mul1 = mul nsw i32 %2, %3
   store i32 %mul1, i32* @d, align 4
   ret void
diff --git a/test/CodeGen/X86/atomic-dagsched.ll b/test/CodeGen/X86/atomic-dagsched.ll
index aa057577a042..97bb1afa47a7 100644
--- a/test/CodeGen/X86/atomic-dagsched.ll
+++ b/test/CodeGen/X86/atomic-dagsched.ll
@@ -2,12 +2,12 @@
 
 define void @test(i8** %a, i64* %b, i64 %c, i64 %d) nounwind {
 entry:
-  %ptrtoarg4 = load i8** %a, align 8
-  %brglist1 = getelementptr i8** %a, i64 1
-  %ptrtoarg25 = load i8** %brglist1, align 8
-  %0 = load i64* %b, align 8
+  %ptrtoarg4 = load i8*, i8** %a, align 8
+  %brglist1 = getelementptr i8*, i8** %a, i64 1
+  %ptrtoarg25 = load i8*, i8** %brglist1, align 8
+  %0 = load i64, i64* %b, align 8
   %1 = mul i64 %0, 4
-  %scevgep = getelementptr i8* %ptrtoarg25, i64 %1
+  %scevgep = getelementptr i8, i8* %ptrtoarg25, i64 %1
   %2 = mul i64 %d, 4
   br label %loop.cond
 
@@ -18,8 +18,8 @@ loop.cond:                                        ; preds = %test.exit, %entry
   br i1 %3, label %return, label %loop
 
 loop:                                             ; preds = %loop.cond
-  %4 = load i64* addrspace(256)* inttoptr (i64 264 to i64* addrspace(256)*), align 8
-  %5 = load i64* %4, align 8
+  %4 = load i64*, i64* addrspace(256)* inttoptr (i64 264 to i64* addrspace(256)*), align 8
+  %5 = load i64, i64* %4, align 8
   %vector.size.i = ashr i64 %5, 3
   %num.vector.wi.i = shl i64 %vector.size.i, 3
   %6 = icmp eq i64 %vector.size.i, 0
@@ -36,7 +36,7 @@ vector_kernel_entry.i:                            ; preds = %vector_kernel_entry
   %asr.iv = phi i64 [ %asr.iv.next, %vector_kernel_entry.i ], [ %vector.size.i, %dim_0_vector_pre_head.i ]
   %8 = addrspacecast i8* %ptrtoarg4 to i32 addrspace(1)*
   %asr.iv911 = addrspacecast i8* %asr.iv9 to <8 x i32> addrspace(1)*
-  %9 = load <8 x i32> addrspace(1)* %asr.iv911, align 4
+  %9 = load <8 x i32>, <8 x i32> addrspace(1)* %asr.iv911, align 4
   %extract8vector_func.i = extractelement <8 x i32> %9, i32 0
   %extract9vector_func.i = extractelement <8 x i32> %9, i32 1
   %extract10vector_func.i = extractelement <8 x i32> %9, i32 2
@@ -55,7 +55,7 @@ vector_kernel_entry.i:                            ; preds = %vector_kernel_entry
   %17 = atomicrmw min i32 addrspace(1)* %8, i32 %extract15vector_func.i seq_cst
   store <8 x i32> %vectorvector_func.i, <8 x i32> addrspace(1)* %asr.iv911, align 4
   %asr.iv.next = add i64 %asr.iv, -1
-  %scevgep10 = getelementptr i8* %asr.iv9, i64 32
+  %scevgep10 = getelementptr i8, i8* %asr.iv9, i64 32
   %dim_0_vector_cmp.to.max.i = icmp eq i64 %asr.iv.next, 0
   br i1 %dim_0_vector_cmp.to.max.i, label %scalarIf.i, label %vector_kernel_entry.i
 
@@ -65,8 +65,8 @@ scalarIf.i:                                       ; preds = %vector_kernel_entry
   br i1 %18, label %test.exit, label %dim_0_pre_head.i
 
 dim_0_pre_head.i:                                 ; preds = %scalarIf.i
-  %19 = load i64* addrspace(256)* inttoptr (i64 264 to i64* addrspace(256)*), align 8
-  %20 = load i64* %19, align 8
+  %19 = load i64*, i64* addrspace(256)* inttoptr (i64 264 to i64* addrspace(256)*), align 8
+  %20 = load i64, i64* %19, align 8
   %21 = trunc i64 %20 to i32
   %22 = mul i64 %vector.size.i, 8
   br label %scalar_kernel_entry.i
@@ -75,10 +75,10 @@ scalar_kernel_entry.i:                            ; preds = %scalar_kernel_entry
   %asr.iv12 = phi i64 [ %asr.iv.next13, %scalar_kernel_entry.i ], [ %22, %dim_0_pre_head.i ]
   %23 = addrspacecast i8* %asr.iv6 to i32 addrspace(1)*
   %24 = addrspacecast i8* %ptrtoarg4 to i32 addrspace(1)*
-  %scevgep16 = getelementptr i32 addrspace(1)* %23, i64 %asr.iv12
-  %25 = load i32 addrspace(1)* %scevgep16, align 4
+  %scevgep16 = getelementptr i32, i32 addrspace(1)* %23, i64 %asr.iv12
+  %25 = load i32, i32 addrspace(1)* %scevgep16, align 4
   %26 = atomicrmw min i32 addrspace(1)* %24, i32 %25 seq_cst
-  %scevgep15 = getelementptr i32 addrspace(1)* %23, i64 %asr.iv12
+  %scevgep15 = getelementptr i32, i32 addrspace(1)* %23, i64 %asr.iv12
   store i32 %21, i32 addrspace(1)* %scevgep15, align 4
   %asr.iv.next13 = add i64 %asr.iv12, 1
   %dim_0_cmp.to.max.i = icmp eq i64 %5, %asr.iv.next13
@@ -88,7 +88,7 @@ test.exit:                     ; preds = %scalar_kernel_entry.i, %scalarIf.i
   %27 = bitcast i8* %asr.iv6 to i1*
   %28 = add i64 %iv, %d
   store i64 %28, i64* %b, align 8
-  %scevgep8 = getelementptr i1* %27, i64 %2
+  %scevgep8 = getelementptr i1, i1* %27, i64 %2
   %29 = bitcast i1* %scevgep8 to i8*
   br label %loop.cond
 
diff --git a/test/CodeGen/X86/atomic-load-store-wide.ll b/test/CodeGen/X86/atomic-load-store-wide.ll
index ad1a5c6d0267..df0af5f7f27d 100644
--- a/test/CodeGen/X86/atomic-load-store-wide.ll
+++ b/test/CodeGen/X86/atomic-load-store-wide.ll
@@ -5,8 +5,7 @@
 
 define void @test1(i64* %ptr, i64 %val1) {
 ; CHECK-LABEL: test1
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b
+; CHECK: lock cmpxchg8b
 ; CHECK-NEXT: jne
   store atomic i64 %val1, i64* %ptr seq_cst, align 8
   ret void
@@ -14,8 +13,7 @@ define void @test1(i64* %ptr, i64 %val1) {
 
 define i64 @test2(i64* %ptr) {
 ; CHECK-LABEL: test2
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b
-  %val = load atomic i64* %ptr seq_cst, align 8
+; CHECK: lock cmpxchg8b
+  %val = load atomic i64, i64* %ptr seq_cst, align 8
   ret i64 %val
 }
diff --git a/test/CodeGen/X86/atomic-load-store.ll b/test/CodeGen/X86/atomic-load-store.ll
index 86a744ed00f0..dab79bd274cf 100644
--- a/test/CodeGen/X86/atomic-load-store.ll
+++ b/test/CodeGen/X86/atomic-load-store.ll
@@ -18,6 +18,6 @@ define void @test2(i32* %ptr, i32 %val1) {
 define i32 @test3(i32* %ptr) {
 ; CHECK: test3
 ; CHECK: movl	(%rdi), %eax
-  %val = load atomic i32* %ptr seq_cst, align 4
+  %val = load atomic i32, i32* %ptr seq_cst, align 4
   ret i32 %val
 }
diff --git a/test/CodeGen/X86/atomic-minmax-i6432.ll b/test/CodeGen/X86/atomic-minmax-i6432.ll
index ffb7a3fd6f64..4989bc14ef86 100644
--- a/test/CodeGen/X86/atomic-minmax-i6432.ll
+++ b/test/CodeGen/X86/atomic-minmax-i6432.ll
@@ -11,8 +11,7 @@ define void @atomic_maxmin_i6432() {
 ; LINUX: seta
 ; LINUX: cmovne
 ; LINUX: cmovne
-; LINUX: lock
-; LINUX-NEXT: cmpxchg8b
+; LINUX: lock cmpxchg8b
 ; LINUX: jne [[LABEL]]
   %2 = atomicrmw min  i64* @sc64, i64 6 acquire
 ; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]]
@@ -20,8 +19,7 @@ define void @atomic_maxmin_i6432() {
 ; LINUX: setb
 ; LINUX: cmovne
 ; LINUX: cmovne
-; LINUX: lock
-; LINUX-NEXT: cmpxchg8b
+; LINUX: lock cmpxchg8b
 ; LINUX: jne [[LABEL]]
   %3 = atomicrmw umax i64* @sc64, i64 7 acquire
 ; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]]
@@ -29,8 +27,7 @@ define void @atomic_maxmin_i6432() {
 ; LINUX: seta
 ; LINUX: cmovne
 ; LINUX: cmovne
-; LINUX: lock
-; LINUX-NEXT: cmpxchg8b
+; LINUX: lock cmpxchg8b
 ; LINUX: jne [[LABEL]]
   %4 = atomicrmw umin i64* @sc64, i64 8 acquire
 ; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]]
@@ -38,8 +35,7 @@ define void @atomic_maxmin_i6432() {
 ; LINUX: setb
 ; LINUX: cmovne
 ; LINUX: cmovne
-; LINUX: lock
-; LINUX-NEXT: cmpxchg8b
+; LINUX: lock cmpxchg8b
 ; LINUX: jne [[LABEL]]
   ret void
 }
diff --git a/test/CodeGen/X86/atomic-or.ll b/test/CodeGen/X86/atomic-or.ll
index 1687e07d57e0..60e9968bdc71 100644
--- a/test/CodeGen/X86/atomic-or.ll
+++ b/test/CodeGen/X86/atomic-or.ll
@@ -6,11 +6,10 @@ define void @t1(i64* %p, i32 %b) nounwind {
 entry:
   %p.addr = alloca i64*, align 8
   store i64* %p, i64** %p.addr, align 8
-  %tmp = load i64** %p.addr, align 8
+  %tmp = load i64*, i64** %p.addr, align 8
 ; CHECK-LABEL: t1:
 ; CHECK: movl    $2147483648, %eax
-; CHECK: lock
-; CHECK-NEXT: orq %r{{.*}}, (%r{{.*}})
+; CHECK: lock orq %r{{.*}}, (%r{{.*}})
   %0 = atomicrmw or i64* %tmp, i64 2147483648 seq_cst
   ret void
 }
@@ -19,10 +18,9 @@ define void @t2(i64* %p, i32 %b) nounwind {
 entry:
   %p.addr = alloca i64*, align 8
   store i64* %p, i64** %p.addr, align 8
-  %tmp = load i64** %p.addr, align 8
+  %tmp = load i64*, i64** %p.addr, align 8
 ; CHECK-LABEL: t2:
-; CHECK: lock
-; CHECK-NEXT: orq $2147483644, (%r{{.*}})
+; CHECK: lock orq $2147483644, (%r{{.*}})
   %0 = atomicrmw or i64* %tmp, i64 2147483644 seq_cst
   ret void
 }
diff --git a/test/CodeGen/X86/atomic-pointer.ll b/test/CodeGen/X86/atomic-pointer.ll
index ec3e6c3a8c19..66e021742fc2 100644
--- a/test/CodeGen/X86/atomic-pointer.ll
+++ b/test/CodeGen/X86/atomic-pointer.ll
@@ -6,7 +6,7 @@ define i32* @test_atomic_ptr_load(i32** %a0) {
 ; CHECK: movl
 ; CHECK: ret
 0:
-  %0 = load atomic i32** %a0 seq_cst, align 4
+  %0 = load atomic i32*, i32** %a0 seq_cst, align 4
   ret i32* %0
 }
 
diff --git a/test/CodeGen/X86/atomic128.ll b/test/CodeGen/X86/atomic128.ll
index 741d2904229d..dea7d482f989 100644
--- a/test/CodeGen/X86/atomic128.ll
+++ b/test/CodeGen/X86/atomic128.ll
@@ -249,7 +249,7 @@ define i128 @atomic_load_seq_cst(i128* %p) {
 ; CHECK: lock
 ; CHECK: cmpxchg16b (%rdi)
 
-   %r = load atomic i128* %p seq_cst, align 16
+   %r = load atomic i128, i128* %p seq_cst, align 16
    ret i128 %r
 }
 
@@ -262,7 +262,7 @@ define i128 @atomic_load_relaxed(i128* %p) {
 ; CHECK: lock
 ; CHECK: cmpxchg16b (%rdi)
 
-   %r = load atomic i128* %p monotonic, align 16
+   %r = load atomic i128, i128* %p monotonic, align 16
    ret i128 %r
 }
 
diff --git a/test/CodeGen/X86/atomic32.ll b/test/CodeGen/X86/atomic32.ll
index 4f2cbe0ce2d3..d514ac7b3110 100644
--- a/test/CodeGen/X86/atomic32.ll
+++ b/test/CodeGen/X86/atomic32.ll
@@ -1,300 +1,207 @@
-; RUN: llc < %s -O0 -march=x86-64 -mcpu=corei7 -verify-machineinstrs | FileCheck %s --check-prefix X64
-; RUN: llc < %s -O0 -march=x86 -mcpu=corei7 -verify-machineinstrs | FileCheck %s --check-prefix X32
+; RUN: llc < %s -O0 -march=x86-64 -mcpu=corei7 -verify-machineinstrs | FileCheck %s -check-prefix=WITH-CMOV
+; RUN: llc < %s -O0 -march=x86 -mcpu=corei7 -verify-machineinstrs | FileCheck %s -check-prefix=WITH-CMOV
 ; RUN: llc < %s -O0 -march=x86 -mcpu=corei7 -mattr=-cmov -verify-machineinstrs | FileCheck %s --check-prefix NOCMOV
 
 @sc32 = external global i32
 
 define void @atomic_fetch_add32() nounwind {
-; X64-LABEL:   atomic_fetch_add32:
-; X32-LABEL:   atomic_fetch_add32:
+; WITH-CMOV-LABEL:   atomic_fetch_add32:
 entry:
 ; 32-bit
   %t1 = atomicrmw add  i32* @sc32, i32 1 acquire
-; X64:       lock
-; X64:       incl
-; X32:       lock
-; X32:       incl
+; WITH-CMOV:       lock
+; WITH-CMOV:       incl
   %t2 = atomicrmw add  i32* @sc32, i32 3 acquire
-; X64:       lock
-; X64:       addl $3
-; X32:       lock
-; X32:       addl $3
+; WITH-CMOV:       lock
+; WITH-CMOV:       addl $3
   %t3 = atomicrmw add  i32* @sc32, i32 5 acquire
-; X64:       lock
-; X64:       xaddl
-; X32:       lock
-; X32:       xaddl
+; WITH-CMOV:       lock
+; WITH-CMOV:       xaddl
   %t4 = atomicrmw add  i32* @sc32, i32 %t3 acquire
-; X64:       lock
-; X64:       addl
-; X32:       lock
-; X32:       addl
+; WITH-CMOV:       lock
+; WITH-CMOV:       addl
   ret void
-; X64:       ret
-; X32:       ret
+; WITH-CMOV:       ret
 }
 
 define void @atomic_fetch_sub32() nounwind {
-; X64-LABEL:   atomic_fetch_sub32:
-; X32-LABEL:   atomic_fetch_sub32:
+; WITH-CMOV-LABEL:   atomic_fetch_sub32:
   %t1 = atomicrmw sub  i32* @sc32, i32 1 acquire
-; X64:       lock
-; X64:       decl
-; X32:       lock
-; X32:       decl
+; WITH-CMOV:       lock
+; WITH-CMOV:       decl
   %t2 = atomicrmw sub  i32* @sc32, i32 3 acquire
-; X64:       lock
-; X64:       subl $3
-; X32:       lock
-; X32:       subl $3
+; WITH-CMOV:       lock
+; WITH-CMOV:       subl $3
   %t3 = atomicrmw sub  i32* @sc32, i32 5 acquire
-; X64:       lock
-; X64:       xaddl
-; X32:       lock
-; X32:       xaddl
+; WITH-CMOV:       lock
+; WITH-CMOV:       xaddl
   %t4 = atomicrmw sub  i32* @sc32, i32 %t3 acquire
-; X64:       lock
-; X64:       subl
-; X32:       lock
-; X32:       subl
+; WITH-CMOV:       lock
+; WITH-CMOV:       subl
   ret void
-; X64:       ret
-; X32:       ret
+; WITH-CMOV:       ret
 }
 
 define void @atomic_fetch_and32() nounwind {
-; X64-LABEL:   atomic_fetch_and32:
-; X32-LABEL:   atomic_fetch_and32:
+; WITH-CMOV-LABEL:   atomic_fetch_and32:
   %t1 = atomicrmw and  i32* @sc32, i32 3 acquire
-; X64:       lock
-; X64:       andl $3
-; X32:       lock
-; X32:       andl $3
+; WITH-CMOV:       lock
+; WITH-CMOV:       andl $3
   %t2 = atomicrmw and  i32* @sc32, i32 5 acquire
-; X64:       andl
-; X64:       lock
-; X64:       cmpxchgl
-; X32:       andl
-; X32:       lock
-; X32:       cmpxchgl
+; WITH-CMOV:       andl
+; WITH-CMOV:       lock
+; WITH-CMOV:       cmpxchgl
   %t3 = atomicrmw and  i32* @sc32, i32 %t2 acquire
-; X64:       lock
-; X64:       andl
-; X32:       lock
-; X32:       andl
+; WITH-CMOV:       lock
+; WITH-CMOV:       andl
   ret void
-; X64:       ret
-; X32:       ret
+; WITH-CMOV:       ret
 }
 
 define void @atomic_fetch_or32() nounwind {
-; X64-LABEL:   atomic_fetch_or32:
-; X32-LABEL:   atomic_fetch_or32:
+; WITH-CMOV-LABEL:   atomic_fetch_or32:
   %t1 = atomicrmw or   i32* @sc32, i32 3 acquire
-; X64:       lock
-; X64:       orl $3
-; X32:       lock
-; X32:       orl $3
+; WITH-CMOV:       lock
+; WITH-CMOV:       orl $3
   %t2 = atomicrmw or   i32* @sc32, i32 5 acquire
-; X64:       orl
-; X64:       lock
-; X64:       cmpxchgl
-; X32:       orl
-; X32:       lock
-; X32:       cmpxchgl
+; WITH-CMOV:       orl
+; WITH-CMOV:       lock
+; WITH-CMOV:       cmpxchgl
   %t3 = atomicrmw or   i32* @sc32, i32 %t2 acquire
-; X64:       lock
-; X64:       orl
-; X32:       lock
-; X32:       orl
+; WITH-CMOV:       lock
+; WITH-CMOV:       orl
   ret void
-; X64:       ret
-; X32:       ret
+; WITH-CMOV:       ret
 }
 
 define void @atomic_fetch_xor32() nounwind {
-; X64-LABEL:   atomic_fetch_xor32:
-; X32-LABEL:   atomic_fetch_xor32:
+; WITH-CMOV-LABEL:   atomic_fetch_xor32:
   %t1 = atomicrmw xor  i32* @sc32, i32 3 acquire
-; X64:       lock
-; X64:       xorl $3
-; X32:       lock
-; X32:       xorl $3
+; WITH-CMOV:       lock
+; WITH-CMOV:       xorl $3
   %t2 = atomicrmw xor  i32* @sc32, i32 5 acquire
-; X64:       xorl
-; X64:       lock
-; X64:       cmpxchgl
-; X32:       xorl
-; X32:       lock
-; X32:       cmpxchgl
+; WITH-CMOV:       xorl
+; WITH-CMOV:       lock
+; WITH-CMOV:       cmpxchgl
   %t3 = atomicrmw xor  i32* @sc32, i32 %t2 acquire
-; X64:       lock
-; X64:       xorl
-; X32:       lock
-; X32:       xorl
+; WITH-CMOV:       lock
+; WITH-CMOV:       xorl
   ret void
-; X64:       ret
-; X32:       ret
+; WITH-CMOV:       ret
 }
 
 define void @atomic_fetch_nand32(i32 %x) nounwind {
-; X64-LABEL:   atomic_fetch_nand32:
-; X32-LABEL:   atomic_fetch_nand32:
+; WITH-CMOV-LABEL:   atomic_fetch_nand32:
   %t1 = atomicrmw nand i32* @sc32, i32 %x acquire
-; X64:       andl
-; X64:       notl
-; X64:       lock
-; X64:       cmpxchgl
-; X32:       andl
-; X32:       notl
-; X32:       lock
-; X32:       cmpxchgl
+; WITH-CMOV:       andl
+; WITH-CMOV:       notl
+; WITH-CMOV:       lock
+; WITH-CMOV:       cmpxchgl
   ret void
-; X64:       ret
-; X32:       ret
+; WITH-CMOV:       ret
 }
 
 define void @atomic_fetch_max32(i32 %x) nounwind {
-; X64-LABEL: atomic_fetch_max32:
-; X32-LABEL: atomic_fetch_max32:
+; WITH-CMOV-LABEL: atomic_fetch_max32:
 
   %t1 = atomicrmw max  i32* @sc32, i32 %x acquire
-; X64:       subl
-; X64:       cmov
-; X64:       lock
-; X64:       cmpxchgl
-
-; X32:       subl
-; X32:       cmov
-; X32:       lock
-; X32:       cmpxchgl
+; WITH-CMOV:       subl
+; WITH-CMOV:       cmov
+; WITH-CMOV:       lock
+; WITH-CMOV:       cmpxchgl
 
 ; NOCMOV:    subl
 ; NOCMOV:    jge
 ; NOCMOV:    lock
 ; NOCMOV:    cmpxchgl
   ret void
-; X64:       ret
-; X32:       ret
+; WITH-CMOV:       ret
 ; NOCMOV:    ret
 }
 
 define void @atomic_fetch_min32(i32 %x) nounwind {
-; X64-LABEL: atomic_fetch_min32:
-; X32-LABEL: atomic_fetch_min32:
+; WITH-CMOV-LABEL: atomic_fetch_min32:
 ; NOCMOV-LABEL: atomic_fetch_min32:
 
   %t1 = atomicrmw min  i32* @sc32, i32 %x acquire
-; X64:       subl
-; X64:       cmov
-; X64:       lock
-; X64:       cmpxchgl
-
-; X32:       subl
-; X32:       cmov
-; X32:       lock
-; X32:       cmpxchgl
+; WITH-CMOV:       subl
+; WITH-CMOV:       cmov
+; WITH-CMOV:       lock
+; WITH-CMOV:       cmpxchgl
 
 ; NOCMOV:    subl
 ; NOCMOV:    jle
 ; NOCMOV:    lock
 ; NOCMOV:    cmpxchgl
   ret void
-; X64:       ret
-; X32:       ret
+; WITH-CMOV:       ret
 ; NOCMOV:    ret
 }
 
 define void @atomic_fetch_umax32(i32 %x) nounwind {
-; X64-LABEL: atomic_fetch_umax32:
-; X32-LABEL: atomic_fetch_umax32:
+; WITH-CMOV-LABEL: atomic_fetch_umax32:
 ; NOCMOV-LABEL: atomic_fetch_umax32:
 
   %t1 = atomicrmw umax i32* @sc32, i32 %x acquire
-; X64:       subl
-; X64:       cmov
-; X64:       lock
-; X64:       cmpxchgl
-
-; X32:       subl
-; X32:       cmov
-; X32:       lock
-; X32:       cmpxchgl
+; WITH-CMOV:       subl
+; WITH-CMOV:       cmov
+; WITH-CMOV:       lock
+; WITH-CMOV:       cmpxchgl
 
 ; NOCMOV:    subl
 ; NOCMOV:    ja
 ; NOCMOV:    lock
 ; NOCMOV:    cmpxchgl
   ret void
-; X64:       ret
-; X32:       ret
+; WITH-CMOV:       ret
 ; NOCMOV:    ret
 }
 
 define void @atomic_fetch_umin32(i32 %x) nounwind {
-; X64-LABEL: atomic_fetch_umin32:
-; X32-LABEL: atomic_fetch_umin32:
+; WITH-CMOV-LABEL: atomic_fetch_umin32:
 ; NOCMOV-LABEL: atomic_fetch_umin32:
 
   %t1 = atomicrmw umin i32* @sc32, i32 %x acquire
-; X64:       subl
-; X64:       cmov
-; X64:       lock
-; X64:       cmpxchgl
-
-; X32:       subl
-; X32:       cmov
-; X32:       lock
-; X32:       cmpxchgl
+; WITH-CMOV:       subl
+; WITH-CMOV:       cmov
+; WITH-CMOV:       lock
+; WITH-CMOV:       cmpxchgl
 
 ; NOCMOV:    subl
 ; NOCMOV:    jb
 ; NOCMOV:    lock
 ; NOCMOV:    cmpxchgl
   ret void
-; X64:       ret
-; X32:       ret
+; WITH-CMOV:       ret
 ; NOCMOV:    ret
 }
 
 define void @atomic_fetch_cmpxchg32() nounwind {
-; X64-LABEL: atomic_fetch_cmpxchg32:
-; X32-LABEL: atomic_fetch_cmpxchg32:
+; WITH-CMOV-LABEL: atomic_fetch_cmpxchg32:
 
   %t1 = cmpxchg i32* @sc32, i32 0, i32 1 acquire acquire
-; X64:       lock
-; X64:       cmpxchgl
-; X32:       lock
-; X32:       cmpxchgl
+; WITH-CMOV:       lock
+; WITH-CMOV:       cmpxchgl
   ret void
-; X64:       ret
-; X32:       ret
+; WITH-CMOV:       ret
 }
 
 define void @atomic_fetch_store32(i32 %x) nounwind {
-; X64-LABEL: atomic_fetch_store32:
-; X32-LABEL: atomic_fetch_store32:
+; WITH-CMOV-LABEL: atomic_fetch_store32:
 
   store atomic i32 %x, i32* @sc32 release, align 4
-; X64-NOT:   lock
-; X64:       movl
-; X32-NOT:   lock
-; X32:       movl
+; WITH-CMOV-NOT:   lock
+; WITH-CMOV:       movl
   ret void
-; X64:       ret
-; X32:       ret
+; WITH-CMOV:       ret
 }
 
 define void @atomic_fetch_swap32(i32 %x) nounwind {
-; X64-LABEL: atomic_fetch_swap32:
-; X32-LABEL: atomic_fetch_swap32:
+; WITH-CMOV-LABEL: atomic_fetch_swap32:
 
   %t1 = atomicrmw xchg i32* @sc32, i32 %x acquire
-; X64-NOT:   lock
-; X64:       xchgl
-; X32-NOT:   lock
-; X32:       xchgl
+; WITH-CMOV-NOT:   lock
+; WITH-CMOV:       xchgl
   ret void
-; X64:       ret
-; X32:       ret
+; WITH-CMOV:       ret
 }
diff --git a/test/CodeGen/X86/atomic64.ll b/test/CodeGen/X86/atomic64.ll
index 11b4e6864da6..c6b1c39d35dc 100644
--- a/test/CodeGen/X86/atomic64.ll
+++ b/test/CodeGen/X86/atomic64.ll
@@ -48,7 +48,7 @@ define void @atomic_fetch_and64() nounwind {
 ; X64:       lock
 ; X64:       andq $3
   %t2 = atomicrmw and  i64* @sc64, i64 5 acquire
-; X64:       andq
+; X64:       andl
 ; X64:       lock
 ; X64:       cmpxchgq
   %t3 = atomicrmw and  i64* @sc64, i64 %t2 acquire
diff --git a/test/CodeGen/X86/atomic6432.ll b/test/CodeGen/X86/atomic6432.ll
index 1c4b0f43bf76..5a78934eb3fd 100644
--- a/test/CodeGen/X86/atomic6432.ll
+++ b/test/CodeGen/X86/atomic6432.ll
@@ -3,7 +3,6 @@
 @sc64 = external global i64
 
 define void @atomic_fetch_add64() nounwind {
-; X64-LABEL:   atomic_fetch_add64:
 ; X32-LABEL:   atomic_fetch_add64:
 entry:
   %t1 = atomicrmw add  i64* @sc64, i64 1 acquire
@@ -31,7 +30,6 @@ entry:
 }
 
 define void @atomic_fetch_sub64() nounwind {
-; X64-LABEL:   atomic_fetch_sub64:
 ; X32-LABEL:   atomic_fetch_sub64:
   %t1 = atomicrmw sub  i64* @sc64, i64 1 acquire
 ; X32:       addl $-1
@@ -58,7 +56,6 @@ define void @atomic_fetch_sub64() nounwind {
 }
 
 define void @atomic_fetch_and64() nounwind {
-; X64-LABEL:   atomic_fetch_and:64
 ; X32-LABEL:   atomic_fetch_and64:
   %t1 = atomicrmw and  i64* @sc64, i64 3 acquire
 ; X32:       andl $3
@@ -80,7 +77,6 @@ define void @atomic_fetch_and64() nounwind {
 }
 
 define void @atomic_fetch_or64() nounwind {
-; X64-LABEL:   atomic_fetch_or64:
 ; X32-LABEL:   atomic_fetch_or64:
   %t1 = atomicrmw or   i64* @sc64, i64 3 acquire
 ; X32:       orl $3
@@ -102,7 +98,6 @@ define void @atomic_fetch_or64() nounwind {
 }
 
 define void @atomic_fetch_xor64() nounwind {
-; X64-LABEL:   atomic_fetch_xor:64
 ; X32-LABEL:   atomic_fetch_xor64:
   %t1 = atomicrmw xor  i64* @sc64, i64 3 acquire
 ; X32:       xorl
@@ -124,7 +119,6 @@ define void @atomic_fetch_xor64() nounwind {
 }
 
 define void @atomic_fetch_nand64(i64 %x) nounwind {
-; X64-LABEL:   atomic_fetch_nand64:
 ; X32-LABEL:   atomic_fetch_nand64:
   %t1 = atomicrmw nand i64* @sc64, i64 %x acquire
 ; X32:       andl
@@ -138,7 +132,6 @@ define void @atomic_fetch_nand64(i64 %x) nounwind {
 }
 
 define void @atomic_fetch_max64(i64 %x) nounwind {
-; X64-LABEL:   atomic_fetch_max:64
 ; X32-LABEL:   atomic_fetch_max64:
   %t1 = atomicrmw max  i64* @sc64, i64 %x acquire
 ; X32:       subl
@@ -152,7 +145,6 @@ define void @atomic_fetch_max64(i64 %x) nounwind {
 }
 
 define void @atomic_fetch_min64(i64 %x) nounwind {
-; X64-LABEL:   atomic_fetch_min64:
 ; X32-LABEL:   atomic_fetch_min64:
   %t1 = atomicrmw min  i64* @sc64, i64 %x acquire
 ; X32:       subl
@@ -166,7 +158,6 @@ define void @atomic_fetch_min64(i64 %x) nounwind {
 }
 
 define void @atomic_fetch_umax64(i64 %x) nounwind {
-; X64-LABEL:   atomic_fetch_umax:64
 ; X32-LABEL:   atomic_fetch_umax64:
   %t1 = atomicrmw umax i64* @sc64, i64 %x acquire
 ; X32:       subl
@@ -180,7 +171,6 @@ define void @atomic_fetch_umax64(i64 %x) nounwind {
 }
 
 define void @atomic_fetch_umin64(i64 %x) nounwind {
-; X64-LABEL:   atomic_fetch_umin64:
 ; X32-LABEL:   atomic_fetch_umin64:
   %t1 = atomicrmw umin i64* @sc64, i64 %x acquire
 ; X32:       subl
@@ -194,7 +184,6 @@ define void @atomic_fetch_umin64(i64 %x) nounwind {
 }
 
 define void @atomic_fetch_cmpxchg64() nounwind {
-; X64-LABEL:   atomic_fetch_cmpxchg:64
 ; X32-LABEL:   atomic_fetch_cmpxchg64:
   %t1 = cmpxchg i64* @sc64, i64 0, i64 1 acquire acquire
 ; X32:       lock
@@ -204,7 +193,6 @@ define void @atomic_fetch_cmpxchg64() nounwind {
 }
 
 define void @atomic_fetch_store64(i64 %x) nounwind {
-; X64-LABEL:   atomic_fetch_store64:
 ; X32-LABEL:   atomic_fetch_store64:
   store atomic i64 %x, i64* @sc64 release, align 8
 ; X32:       lock
@@ -214,7 +202,6 @@ define void @atomic_fetch_store64(i64 %x) nounwind {
 }
 
 define void @atomic_fetch_swap64(i64 %x) nounwind {
-; X64-LABEL:   atomic_fetch_swap64:
 ; X32-LABEL:   atomic_fetch_swap64:
   %t1 = atomicrmw xchg i64* @sc64, i64 %x acquire
 ; X32:       lock
diff --git a/test/CodeGen/X86/atomic_mi.ll b/test/CodeGen/X86/atomic_mi.ll
index 19e019eaddcd..7a6204fc8930 100644
--- a/test/CodeGen/X86/atomic_mi.ll
+++ b/test/CodeGen/X86/atomic_mi.ll
@@ -103,7 +103,7 @@ define void @add_8(i8* %p) {
 ; X32-NOT: lock
 ; X32: addb
 ; X32-NOT: movb
-  %1 = load atomic i8* %p seq_cst, align 1
+  %1 = load atomic i8, i8* %p seq_cst, align 1
   %2 = add i8 %1, 2
   store atomic i8 %2, i8* %p release, align 1
   ret void
@@ -116,7 +116,7 @@ define void @add_16(i16* %p) {
 ; X64-NOT: addw
 ; X32-LABEL: add_16
 ; X32-NOT: addw
-  %1 = load atomic i16* %p acquire, align 2
+  %1 = load atomic i16, i16* %p acquire, align 2
   %2 = add i16 %1, 2
   store atomic i16 %2, i16* %p release, align 2
   ret void
@@ -131,7 +131,7 @@ define void @add_32(i32* %p) {
 ; X32-NOT: lock
 ; X32: addl
 ; X32-NOT: movl
-  %1 = load atomic i32* %p acquire, align 4
+  %1 = load atomic i32, i32* %p acquire, align 4
   %2 = add i32 %1, 2
   store atomic i32 %2, i32* %p monotonic, align 4
   ret void
@@ -144,7 +144,7 @@ define void @add_64(i64* %p) {
 ; X64-NOT: movq
 ;   We do not check X86-32 as it cannot do 'addq'.
 ; X32-LABEL: add_64
-  %1 = load atomic i64* %p acquire, align 8
+  %1 = load atomic i64, i64* %p acquire, align 8
   %2 = add i64 %1, 2
   store atomic i64 %2, i64* %p release, align 8
   ret void
@@ -155,7 +155,7 @@ define void @add_32_seq_cst(i32* %p) {
 ; X64: xchgl
 ; X32-LABEL: add_32_seq_cst
 ; X32: xchgl
-  %1 = load atomic i32* %p monotonic, align 4
+  %1 = load atomic i32, i32* %p monotonic, align 4
   %2 = add i32 %1, 2
   store atomic i32 %2, i32* %p seq_cst, align 4
   ret void
@@ -172,7 +172,7 @@ define void @and_8(i8* %p) {
 ; X32-NOT: lock
 ; X32: andb
 ; X32-NOT: movb
-  %1 = load atomic i8* %p monotonic, align 1
+  %1 = load atomic i8, i8* %p monotonic, align 1
   %2 = and i8 %1, 2
   store atomic i8 %2, i8* %p release, align 1
   ret void
@@ -185,7 +185,7 @@ define void @and_16(i16* %p) {
 ; X64-NOT: andw
 ; X32-LABEL: and_16
 ; X32-NOT: andw
-  %1 = load atomic i16* %p acquire, align 2
+  %1 = load atomic i16, i16* %p acquire, align 2
   %2 = and i16 %1, 2
   store atomic i16 %2, i16* %p release, align 2
   ret void
@@ -200,7 +200,7 @@ define void @and_32(i32* %p) {
 ; X32-NOT: lock
 ; X32: andl
 ; X32-NOT: movl
-  %1 = load atomic i32* %p acquire, align 4
+  %1 = load atomic i32, i32* %p acquire, align 4
   %2 = and i32 %1, 2
   store atomic i32 %2, i32* %p release, align 4
   ret void
@@ -213,7 +213,7 @@ define void @and_64(i64* %p) {
 ; X64-NOT: movq
 ;   We do not check X86-32 as it cannot do 'andq'.
 ; X32-LABEL: and_64
-  %1 = load atomic i64* %p acquire, align 8
+  %1 = load atomic i64, i64* %p acquire, align 8
   %2 = and i64 %1, 2
   store atomic i64 %2, i64* %p release, align 8
   ret void
@@ -224,7 +224,7 @@ define void @and_32_seq_cst(i32* %p) {
 ; X64: xchgl
 ; X32-LABEL: and_32_seq_cst
 ; X32: xchgl
-  %1 = load atomic i32* %p monotonic, align 4
+  %1 = load atomic i32, i32* %p monotonic, align 4
   %2 = and i32 %1, 2
   store atomic i32 %2, i32* %p seq_cst, align 4
   ret void
@@ -241,7 +241,7 @@ define void @or_8(i8* %p) {
 ; X32-NOT: lock
 ; X32: orb
 ; X32-NOT: movb
-  %1 = load atomic i8* %p acquire, align 1
+  %1 = load atomic i8, i8* %p acquire, align 1
   %2 = or i8 %1, 2
   store atomic i8 %2, i8* %p release, align 1
   ret void
@@ -252,7 +252,7 @@ define void @or_16(i16* %p) {
 ; X64-NOT: orw
 ; X32-LABEL: or_16
 ; X32-NOT: orw
-  %1 = load atomic i16* %p acquire, align 2
+  %1 = load atomic i16, i16* %p acquire, align 2
   %2 = or i16 %1, 2
   store atomic i16 %2, i16* %p release, align 2
   ret void
@@ -267,7 +267,7 @@ define void @or_32(i32* %p) {
 ; X32-NOT: lock
 ; X32: orl
 ; X32-NOT: movl
-  %1 = load atomic i32* %p acquire, align 4
+  %1 = load atomic i32, i32* %p acquire, align 4
   %2 = or i32 %1, 2
   store atomic i32 %2, i32* %p release, align 4
   ret void
@@ -280,7 +280,7 @@ define void @or_64(i64* %p) {
 ; X64-NOT: movq
 ;   We do not check X86-32 as it cannot do 'orq'.
 ; X32-LABEL: or_64
-  %1 = load atomic i64* %p acquire, align 8
+  %1 = load atomic i64, i64* %p acquire, align 8
   %2 = or i64 %1, 2
   store atomic i64 %2, i64* %p release, align 8
   ret void
@@ -291,7 +291,7 @@ define void @or_32_seq_cst(i32* %p) {
 ; X64: xchgl
 ; X32-LABEL: or_32_seq_cst
 ; X32: xchgl
-  %1 = load atomic i32* %p monotonic, align 4
+  %1 = load atomic i32, i32* %p monotonic, align 4
   %2 = or i32 %1, 2
   store atomic i32 %2, i32* %p seq_cst, align 4
   ret void
@@ -308,7 +308,7 @@ define void @xor_8(i8* %p) {
 ; X32-NOT: lock
 ; X32: xorb
 ; X32-NOT: movb
-  %1 = load atomic i8* %p acquire, align 1
+  %1 = load atomic i8, i8* %p acquire, align 1
   %2 = xor i8 %1, 2
   store atomic i8 %2, i8* %p release, align 1
   ret void
@@ -319,7 +319,7 @@ define void @xor_16(i16* %p) {
 ; X64-NOT: xorw
 ; X32-LABEL: xor_16
 ; X32-NOT: xorw
-  %1 = load atomic i16* %p acquire, align 2
+  %1 = load atomic i16, i16* %p acquire, align 2
   %2 = xor i16 %1, 2
   store atomic i16 %2, i16* %p release, align 2
   ret void
@@ -334,7 +334,7 @@ define void @xor_32(i32* %p) {
 ; X32-NOT: lock
 ; X32: xorl
 ; X32-NOT: movl
-  %1 = load atomic i32* %p acquire, align 4
+  %1 = load atomic i32, i32* %p acquire, align 4
   %2 = xor i32 %1, 2
   store atomic i32 %2, i32* %p release, align 4
   ret void
@@ -347,7 +347,7 @@ define void @xor_64(i64* %p) {
 ; X64-NOT: movq
 ;   We do not check X86-32 as it cannot do 'xorq'.
 ; X32-LABEL: xor_64
-  %1 = load atomic i64* %p acquire, align 8
+  %1 = load atomic i64, i64* %p acquire, align 8
   %2 = xor i64 %1, 2
   store atomic i64 %2, i64* %p release, align 8
   ret void
@@ -358,7 +358,7 @@ define void @xor_32_seq_cst(i32* %p) {
 ; X64: xchgl
 ; X32-LABEL: xor_32_seq_cst
 ; X32: xchgl
-  %1 = load atomic i32* %p monotonic, align 4
+  %1 = load atomic i32, i32* %p monotonic, align 4
   %2 = xor i32 %1, 2
   store atomic i32 %2, i32* %p seq_cst, align 4
   ret void
@@ -378,7 +378,7 @@ define void @inc_8(i8* %p) {
 ; SLOW_INC-LABEL: inc_8
 ; SLOW_INC-NOT: incb
 ; SLOW_INC-NOT: movb
-  %1 = load atomic i8* %p seq_cst, align 1
+  %1 = load atomic i8, i8* %p seq_cst, align 1
   %2 = add i8 %1, 1
   store atomic i8 %2, i8* %p release, align 1
   ret void
@@ -393,7 +393,7 @@ define void @inc_16(i16* %p) {
 ; X32-NOT: incw
 ; SLOW_INC-LABEL: inc_16
 ; SLOW_INC-NOT: incw
-  %1 = load atomic i16* %p acquire, align 2
+  %1 = load atomic i16, i16* %p acquire, align 2
   %2 = add i16 %1, 1
   store atomic i16 %2, i16* %p release, align 2
   ret void
@@ -411,7 +411,7 @@ define void @inc_32(i32* %p) {
 ; SLOW_INC-LABEL: inc_32
 ; SLOW_INC-NOT: incl
 ; SLOW_INC-NOT: movl
-  %1 = load atomic i32* %p acquire, align 4
+  %1 = load atomic i32, i32* %p acquire, align 4
   %2 = add i32 %1, 1
   store atomic i32 %2, i32* %p monotonic, align 4
   ret void
@@ -427,7 +427,7 @@ define void @inc_64(i64* %p) {
 ; SLOW_INC-LABEL: inc_64
 ; SLOW_INC-NOT: incq
 ; SLOW_INC-NOT: movq
-  %1 = load atomic i64* %p acquire, align 8
+  %1 = load atomic i64, i64* %p acquire, align 8
   %2 = add i64 %1, 1
   store atomic i64 %2, i64* %p release, align 8
   ret void
@@ -438,7 +438,7 @@ define void @inc_32_seq_cst(i32* %p) {
 ; X64: xchgl
 ; X32-LABEL: inc_32_seq_cst
 ; X32: xchgl
-  %1 = load atomic i32* %p monotonic, align 4
+  %1 = load atomic i32, i32* %p monotonic, align 4
   %2 = add i32 %1, 1
   store atomic i32 %2, i32* %p seq_cst, align 4
   ret void
@@ -458,7 +458,7 @@ define void @dec_8(i8* %p) {
 ; SLOW_INC-LABEL: dec_8
 ; SLOW_INC-NOT: decb
 ; SLOW_INC-NOT: movb
-  %1 = load atomic i8* %p seq_cst, align 1
+  %1 = load atomic i8, i8* %p seq_cst, align 1
   %2 = sub i8 %1, 1
   store atomic i8 %2, i8* %p release, align 1
   ret void
@@ -473,7 +473,7 @@ define void @dec_16(i16* %p) {
 ; X32-NOT: decw
 ; SLOW_INC-LABEL: dec_16
 ; SLOW_INC-NOT: decw
-  %1 = load atomic i16* %p acquire, align 2
+  %1 = load atomic i16, i16* %p acquire, align 2
   %2 = sub i16 %1, 1
   store atomic i16 %2, i16* %p release, align 2
   ret void
@@ -491,7 +491,7 @@ define void @dec_32(i32* %p) {
 ; SLOW_INC-LABEL: dec_32
 ; SLOW_INC-NOT: decl
 ; SLOW_INC-NOT: movl
-  %1 = load atomic i32* %p acquire, align 4
+  %1 = load atomic i32, i32* %p acquire, align 4
   %2 = sub i32 %1, 1
   store atomic i32 %2, i32* %p monotonic, align 4
   ret void
@@ -507,7 +507,7 @@ define void @dec_64(i64* %p) {
 ; SLOW_INC-LABEL: dec_64
 ; SLOW_INC-NOT: decq
 ; SLOW_INC-NOT: movq
-  %1 = load atomic i64* %p acquire, align 8
+  %1 = load atomic i64, i64* %p acquire, align 8
   %2 = sub i64 %1, 1
   store atomic i64 %2, i64* %p release, align 8
   ret void
@@ -518,7 +518,7 @@ define void @dec_32_seq_cst(i32* %p) {
 ; X64: xchgl
 ; X32-LABEL: dec_32_seq_cst
 ; X32: xchgl
-  %1 = load atomic i32* %p monotonic, align 4
+  %1 = load atomic i32, i32* %p monotonic, align 4
   %2 = sub i32 %1, 1
   store atomic i32 %2, i32* %p seq_cst, align 4
   ret void
diff --git a/test/CodeGen/X86/atomic_op.ll b/test/CodeGen/X86/atomic_op.ll
index d0ab28aa61f9..aa895dedfe4c 100644
--- a/test/CodeGen/X86/atomic_op.ll
+++ b/test/CodeGen/X86/atomic_op.ll
@@ -22,7 +22,7 @@ entry:
 	store i32 3855, i32* %ort
 	store i32 3855, i32* %xort
 	store i32 4, i32* %temp
-	%tmp = load i32* %temp
+	%tmp = load i32, i32* %temp
         ; CHECK: lock
         ; CHECK: xaddl
   %0 = atomicrmw add i32* %val1, i32 %tmp monotonic
diff --git a/test/CodeGen/X86/avoid-loop-align-2.ll b/test/CodeGen/X86/avoid-loop-align-2.ll
index fc9d1f0428fb..e02f3569c89d 100644
--- a/test/CodeGen/X86/avoid-loop-align-2.ll
+++ b/test/CodeGen/X86/avoid-loop-align-2.ll
@@ -13,7 +13,7 @@ entry:
 
 bb.nph12:		; preds = %entry
 	%1 = icmp eq i32 %b, 0		; <i1> [#uses=1]
-	%2 = load i32** @x, align 8		; <i32*> [#uses=1]
+	%2 = load i32*, i32** @x, align 8		; <i32*> [#uses=1]
 	br i1 %1, label %bb2.preheader, label %bb2.preheader.us
 
 bb2.preheader.us:		; preds = %bb2.bb3_crit_edge.us, %bb.nph12
@@ -26,8 +26,8 @@ bb1.us:		; preds = %bb1.us, %bb2.preheader.us
 	%indvar = phi i32 [ 0, %bb2.preheader.us ], [ %indvar.next, %bb1.us ]		; <i32> [#uses=2]
 	%tmp17 = add i32 %indvar, %tmp16		; <i32> [#uses=1]
 	%tmp. = zext i32 %tmp17 to i64		; <i64> [#uses=1]
-	%3 = getelementptr i32* %2, i64 %tmp.		; <i32*> [#uses=1]
-	%4 = load i32* %3, align 4		; <i32> [#uses=2]
+	%3 = getelementptr i32, i32* %2, i64 %tmp.		; <i32*> [#uses=1]
+	%4 = load i32, i32* %3, align 4		; <i32> [#uses=2]
 	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=2]
 	%exitcond = icmp eq i32 %indvar.next, %b		; <i1> [#uses=1]
 	br i1 %exitcond, label %bb2.bb3_crit_edge.us, label %bb1.us
diff --git a/test/CodeGen/X86/avoid-loop-align.ll b/test/CodeGen/X86/avoid-loop-align.ll
index 7957db72fe6d..d82cf9418e64 100644
--- a/test/CodeGen/X86/avoid-loop-align.ll
+++ b/test/CodeGen/X86/avoid-loop-align.ll
@@ -11,7 +11,7 @@
 
 define i8* @test(i8* %Q, i32* %L) nounwind {
 entry:
-	%tmp = tail call i32 (...)* @foo() nounwind		; <i32> [#uses=2]
+	%tmp = tail call i32 (...) @foo() nounwind		; <i32> [#uses=2]
 	%tmp1 = inttoptr i32 %tmp to i8*		; <i8*> [#uses=1]
 	br label %bb1
 
@@ -21,8 +21,8 @@ bb:		; preds = %bb1, %bb1
 
 bb1:		; preds = %bb, %entry
 	%P.0.rec = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]		; <i32> [#uses=2]
-	%P.0 = getelementptr i8* %tmp1, i32 %P.0.rec		; <i8*> [#uses=3]
-	%tmp2 = load i8* %P.0, align 1		; <i8> [#uses=1]
+	%P.0 = getelementptr i8, i8* %tmp1, i32 %P.0.rec		; <i8*> [#uses=3]
+	%tmp2 = load i8, i8* %P.0, align 1		; <i8> [#uses=1]
 	switch i8 %tmp2, label %bb4 [
 		i8 12, label %bb
 		i8 42, label %bb
@@ -31,7 +31,7 @@ bb1:		; preds = %bb, %entry
 bb4:		; preds = %bb1
 	%tmp3 = ptrtoint i8* %P.0 to i32		; <i32> [#uses=1]
 	%tmp4 = sub i32 %tmp3, %tmp		; <i32> [#uses=1]
-	%tmp5 = getelementptr [100 x i32]* @A, i32 0, i32 %tmp4		; <i32*> [#uses=1]
+	%tmp5 = getelementptr [100 x i32], [100 x i32]* @A, i32 0, i32 %tmp4		; <i32*> [#uses=1]
 	store i32 4, i32* %tmp5, align 4
 	ret i8* %P.0
 }
diff --git a/test/CodeGen/X86/avoid_complex_am.ll b/test/CodeGen/X86/avoid_complex_am.ll
index e5e7bd23a641..fafa236b8dd4 100644
--- a/test/CodeGen/X86/avoid_complex_am.ll
+++ b/test/CodeGen/X86/avoid_complex_am.ll
@@ -19,15 +19,15 @@ for.body:                                         ; preds = %for.body, %entry
 ; CHECK-NOT: phi
   %indvars.iv = phi i64 [ 1, %entry ], [ %indvars.iv.next, %for.body ]
   %tmp = add nsw i64 %indvars.iv, -1
-  %arrayidx = getelementptr inbounds double* %b, i64 %tmp
-  %tmp1 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %b, i64 %tmp
+  %tmp1 = load double, double* %arrayidx, align 8
 ; The induction variable should carry the scaling factor: 1.
-; CHECK: [[IVNEXT]] = add nuw i64 [[IV]], 1
+; CHECK: [[IVNEXT]] = add nuw nsw i64 [[IV]], 1
   %indvars.iv.next = add i64 %indvars.iv, 1
-  %arrayidx2 = getelementptr inbounds double* %c, i64 %indvars.iv.next
-  %tmp2 = load double* %arrayidx2, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %c, i64 %indvars.iv.next
+  %tmp2 = load double, double* %arrayidx2, align 8
   %mul = fmul double %tmp1, %tmp2
-  %arrayidx4 = getelementptr inbounds double* %a, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds double, double* %a, i64 %indvars.iv
   store double %mul, double* %arrayidx4, align 8
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
 ; Comparison should be 19 * 1 = 19.
diff --git a/test/CodeGen/X86/avx-arith.ll b/test/CodeGen/X86/avx-arith.ll
index a9da1ec067ca..792a9987e107 100644
--- a/test/CodeGen/X86/avx-arith.ll
+++ b/test/CodeGen/X86/avx-arith.ll
@@ -38,7 +38,7 @@ entry:
 ; CHECK: vsubpd (%
 define <4 x double> @subpd256fold(<4 x double> %y, <4 x double>* nocapture %x) nounwind uwtable readonly ssp {
 entry:
-  %tmp2 = load <4 x double>* %x, align 32
+  %tmp2 = load <4 x double>, <4 x double>* %x, align 32
   %sub.i = fsub <4 x double> %y, %tmp2
   ret <4 x double> %sub.i
 }
@@ -53,7 +53,7 @@ entry:
 ; CHECK: vsubps (%
 define <8 x float> @subps256fold(<8 x float> %y, <8 x float>* nocapture %x) nounwind uwtable readonly ssp {
 entry:
-  %tmp2 = load <8 x float>* %x, align 32
+  %tmp2 = load <8 x float>, <8 x float>* %x, align 32
   %sub.i = fsub <8 x float> %y, %tmp2
   ret <8 x float> %sub.i
 }
@@ -264,7 +264,7 @@ declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
 define <4 x float> @int_sqrt_ss() {
 ; CHECK: int_sqrt_ss
 ; CHECK: vsqrtss
- %x0 = load float addrspace(1)* undef, align 8
+ %x0 = load float, float addrspace(1)* undef, align 8
  %x1 = insertelement <4 x float> undef, float %x0, i32 0
  %x2 = call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %x1) nounwind
  ret <4 x float> %x2
diff --git a/test/CodeGen/X86/avx-basic.ll b/test/CodeGen/X86/avx-basic.ll
index 02ea173c8032..6857bb8bd112 100644
--- a/test/CodeGen/X86/avx-basic.ll
+++ b/test/CodeGen/X86/avx-basic.ll
@@ -57,10 +57,10 @@ entry:
 define <8 x i32> @VMOVZQI2PQI([0 x float]* nocapture %aFOO) nounwind {
 allocas:
   %ptrcast.i33.i = bitcast [0 x float]* %aFOO to i32*
-  %val.i34.i = load i32* %ptrcast.i33.i, align 4
-  %ptroffset.i22.i992 = getelementptr [0 x float]* %aFOO, i64 0, i64 1
+  %val.i34.i = load i32, i32* %ptrcast.i33.i, align 4
+  %ptroffset.i22.i992 = getelementptr [0 x float], [0 x float]* %aFOO, i64 0, i64 1
   %ptrcast.i23.i = bitcast float* %ptroffset.i22.i992 to i32*
-  %val.i24.i = load i32* %ptrcast.i23.i, align 4
+  %val.i24.i = load i32, i32* %ptrcast.i23.i, align 4
   %updatedret.i30.i = insertelement <8 x i32> undef, i32 %val.i34.i, i32 1
   ret <8 x i32> %updatedret.i30.i
 }
@@ -91,3 +91,12 @@ entry:
   %vecext.i = extractelement <2 x i64> %a, i32 0
   ret i64 %vecext.i
 }
+
+; PR22685
+; CHECK: mov00
+; CHECK: vmovss
+define <8 x float> @mov00_8f32(float* %ptr) {
+  %val = load float, float* %ptr
+  %vec = insertelement <8 x float> zeroinitializer, float %val, i32 0
+  ret <8 x float> %vec
+}
diff --git a/test/CodeGen/X86/avx-bitcast.ll b/test/CodeGen/X86/avx-bitcast.ll
index c9d828c1f6e2..e34c20fcbd73 100644
--- a/test/CodeGen/X86/avx-bitcast.ll
+++ b/test/CodeGen/X86/avx-bitcast.ll
@@ -1,9 +1,12 @@
-; RUN: llc < %s -O0 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
+; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
 
-; CHECK: vmovsd (%
-; CHECK-NEXT: vmovq %xmm
 define i64 @bitcasti64tof64() {
-  %a = load double* undef
+; CHECK-LABEL: bitcasti64tof64:
+; CHECK:       # BB#0:
+; CHECK:         vmovsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT:    vmovq %xmm0, %rax
+; CHECK-NEXT:    retq
+  %a = load double, double* undef
   %b = bitcast double %a to i64
   ret i64 %b
 }
diff --git a/test/CodeGen/X86/avx-cast.ll b/test/CodeGen/X86/avx-cast.ll
index 32d450cac9f9..b4798f159455 100644
--- a/test/CodeGen/X86/avx-cast.ll
+++ b/test/CodeGen/X86/avx-cast.ll
@@ -1,45 +1,100 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx  | FileCheck %s --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=AVX2
+
+; Prefer a blend instruction to a vinsert128 instruction because blends
+; are simpler (no lane changes) and therefore will have equal or better
+; performance.
 
-; CHECK: vxorps
-; CHECK-NEXT: vinsertf128 $0
 define <8 x float> @castA(<4 x float> %m) nounwind uwtable readnone ssp {
+; AVX1-LABEL: castA:
+; AVX1:         vxorps %ymm1, %ymm1, %ymm1
+; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: castA:
+; AVX2:         vxorps %ymm1, %ymm1, %ymm1
+; AVX2-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
+; AVX2-NEXT:    retq
+
 entry:
   %shuffle.i = shufflevector <4 x float> %m, <4 x float> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
   ret <8 x float> %shuffle.i
 }
 
-; CHECK: vxorps
-; CHECK-NEXT: vinsertf128 $0
 define <4 x double> @castB(<2 x double> %m) nounwind uwtable readnone ssp {
+; AVX1-LABEL: castB:
+; AVX1:         vxorpd %ymm1, %ymm1, %ymm1
+; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: castB:
+; AVX2:         vxorpd %ymm1, %ymm1, %ymm1
+; AVX2-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
+; AVX2-NEXT:    retq
+
 entry:
   %shuffle.i = shufflevector <2 x double> %m, <2 x double> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
   ret <4 x double> %shuffle.i
 }
 
-; CHECK: vxorps
-; CHECK-NEXT: vinsertf128 $0
+; AVX2 is needed for integer types.
+
 define <4 x i64> @castC(<2 x i64> %m) nounwind uwtable readnone ssp {
+; AVX1-LABEL: castC:
+; AVX1:         vxorps %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: castC:
+; AVX2:         vpxor %ymm1, %ymm1, %ymm1
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
+; AVX2-NEXT:    retq
+
 entry:
   %shuffle.i = shufflevector <2 x i64> %m, <2 x i64> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
   ret <4 x i64> %shuffle.i
 }
 
-; CHECK-NOT: vextractf128 $0
+; The next three tests don't need any shuffling. There may or may not be a
+; vzeroupper before the return, so just check for the absence of shuffles.
+
 define <4 x float> @castD(<8 x float> %m) nounwind uwtable readnone ssp {
+; AVX1-LABEL: castD:
+; AVX1-NOT:    extract
+; AVX1-NOT:    blend
+;
+; AVX2-LABEL: castD:
+; AVX2-NOT:    extract
+; AVX2-NOT:    blend
+
 entry:
   %shuffle.i = shufflevector <8 x float> %m, <8 x float> %m, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x float> %shuffle.i
 }
 
-; CHECK-NOT: vextractf128 $0
 define <2 x i64> @castE(<4 x i64> %m) nounwind uwtable readnone ssp {
+; AVX1-LABEL: castE:
+; AVX1-NOT:    extract
+; AVX1-NOT:    blend
+;
+; AVX2-LABEL: castE:
+; AVX2-NOT:    extract
+; AVX2-NOT:    blend
+
 entry:
   %shuffle.i = shufflevector <4 x i64> %m, <4 x i64> %m, <2 x i32> <i32 0, i32 1>
   ret <2 x i64> %shuffle.i
 }
 
-; CHECK-NOT: vextractf128 $0
 define <2 x double> @castF(<4 x double> %m) nounwind uwtable readnone ssp {
+; AVX1-LABEL: castF:
+; AVX1-NOT:    extract
+; AVX1-NOT:    blend
+;
+; AVX2-LABEL: castF:
+; AVX2-NOT:    extract
+; AVX2-NOT:    blend
+
 entry:
   %shuffle.i = shufflevector <4 x double> %m, <4 x double> %m, <2 x i32> <i32 0, i32 1>
   ret <2 x double> %shuffle.i
diff --git a/test/CodeGen/X86/avx-cvt-2.ll b/test/CodeGen/X86/avx-cvt-2.ll
index 8cc7190fcc69..583c7d5947bf 100644
--- a/test/CodeGen/X86/avx-cvt-2.ll
+++ b/test/CodeGen/X86/avx-cvt-2.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s
 
 ; Check that we generate vector conversion from float to narrower int types
 
@@ -8,8 +8,16 @@
 
 define void @fptoui16(%f32vec_t %a, %i16vec_t *%p) {
 ; CHECK-LABEL: fptoui16:
-; CHECK: vcvttps2dq %ymm
-; CHECK-NOT: vcvttss2si
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvttps2dq %ymm0, %ymm0
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; CHECK-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT:    vmovdqa %xmm0, (%rdi)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
   %b = fptoui %f32vec_t %a to %i16vec_t
   store %i16vec_t %b, %i16vec_t * %p
   ret void
@@ -17,8 +25,16 @@ define void @fptoui16(%f32vec_t %a, %i16vec_t *%p) {
 
 define void @fptosi16(%f32vec_t %a, %i16vec_t *%p) {
 ; CHECK-LABEL: fptosi16:
-; CHECK: vcvttps2dq %ymm
-; CHECK-NOT: vcvttss2si
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvttps2dq %ymm0, %ymm0
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; CHECK-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT:    vmovdqa %xmm0, (%rdi)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
   %b = fptosi %f32vec_t %a to %i16vec_t
   store %i16vec_t %b, %i16vec_t * %p
   ret void
@@ -26,8 +42,17 @@ define void @fptosi16(%f32vec_t %a, %i16vec_t *%p) {
 
 define void @fptoui8(%f32vec_t %a, %i8vec_t *%p) {
 ; CHECK-LABEL: fptoui8:
-; CHECK: vcvttps2dq %ymm
-; CHECK-NOT: vcvttss2si
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvttps2dq %ymm0, %ymm0
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; CHECK-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; CHECK-NEXT:    vmovq %xmm0, (%rdi)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
   %b = fptoui %f32vec_t %a to %i8vec_t
   store %i8vec_t %b, %i8vec_t * %p
   ret void
@@ -35,8 +60,17 @@ define void @fptoui8(%f32vec_t %a, %i8vec_t *%p) {
 
 define void @fptosi8(%f32vec_t %a, %i8vec_t *%p) {
 ; CHECK-LABEL: fptosi8:
-; CHECK: vcvttps2dq %ymm
-; CHECK-NOT: vcvttss2si
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvttps2dq %ymm0, %ymm0
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; CHECK-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; CHECK-NEXT:    vmovq %xmm0, (%rdi)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
   %b = fptosi %f32vec_t %a to %i8vec_t
   store %i8vec_t %b, %i8vec_t * %p
   ret void
diff --git a/test/CodeGen/X86/avx-cvt.ll b/test/CodeGen/X86/avx-cvt.ll
index 22fad7ce4b7d..6df3e5324c11 100644
--- a/test/CodeGen/X86/avx-cvt.ll
+++ b/test/CodeGen/X86/avx-cvt.ll
@@ -1,89 +1,148 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
 
-; CHECK: vcvtdq2ps %ymm
 define <8 x float> @sitofp00(<8 x i32> %a) nounwind {
+; CHECK-LABEL: sitofp00:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %b = sitofp <8 x i32> %a to <8 x float>
   ret <8 x float> %b
 }
 
-; CHECK: vcvttps2dq %ymm
 define <8 x i32> @fptosi00(<8 x float> %a) nounwind {
+; CHECK-LABEL: fptosi00:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvttps2dq %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %b = fptosi <8 x float> %a to <8 x i32>
   ret <8 x i32> %b
 }
 
-; CHECK: vcvtdq2pd %xmm
 define <4 x double> @sitofp01(<4 x i32> %a) {
+; CHECK-LABEL: sitofp01:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtdq2pd %xmm0, %ymm0
+; CHECK-NEXT:    retq
   %b = sitofp <4 x i32> %a to <4 x double>
   ret <4 x double> %b
 }
 
-; CHECK: vcvtdq2ps %ymm
 define <8 x float> @sitofp02(<8 x i16> %a) {
+; CHECK-LABEL: sitofp02:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmovsxwd %xmm0, %xmm1
+; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; CHECK-NEXT:    vpmovsxwd %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %b = sitofp <8 x i16> %a to <8 x float>
   ret <8 x float> %b
 }
 
-; CHECK: vcvttpd2dqy %ymm
 define <4 x i32> @fptosi01(<4 x double> %a) {
+; CHECK-LABEL: fptosi01:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvttpd2dqy %ymm0, %xmm0
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
   %b = fptosi <4 x double> %a to <4 x i32>
   ret <4 x i32> %b
 }
 
-; CHECK: vcvtpd2psy %ymm
-; CHECK-NEXT: vcvtpd2psy %ymm
-; CHECK-NEXT: vinsertf128 $1
 define <8 x float> @fptrunc00(<8 x double> %b) nounwind {
+; CHECK-LABEL: fptrunc00:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtpd2psy %ymm0, %xmm0
+; CHECK-NEXT:    vcvtpd2psy %ymm1, %xmm1
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %a = fptrunc <8 x double> %b to <8 x float>
   ret <8 x float> %a
 }
 
-; CHECK: vcvtps2pd %xmm
 define <4 x double> @fpext00(<4 x float> %b) nounwind {
+; CHECK-LABEL: fpext00:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtps2pd %xmm0, %ymm0
+; CHECK-NEXT:    retq
   %a = fpext <4 x float> %b to <4 x double>
   ret <4 x double> %a
 }
 
-; CHECK: vcvtsi2sdq (%
 define double @funcA(i64* nocapture %e) nounwind uwtable readonly ssp {
-entry:
-  %tmp1 = load i64* %e, align 8
+; CHECK-LABEL: funcA:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtsi2sdq (%rdi), %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %tmp1 = load i64, i64* %e, align 8
   %conv = sitofp i64 %tmp1 to double
   ret double %conv
 }
 
-; CHECK: vcvtsi2sdl (%
 define double @funcB(i32* nocapture %e) nounwind uwtable readonly ssp {
-entry:
-  %tmp1 = load i32* %e, align 4
+; CHECK-LABEL: funcB:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtsi2sdl (%rdi), %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %tmp1 = load i32, i32* %e, align 4
   %conv = sitofp i32 %tmp1 to double
   ret double %conv
 }
 
-; CHECK: vcvtsi2ssl (%
 define float @funcC(i32* nocapture %e) nounwind uwtable readonly ssp {
-entry:
-  %tmp1 = load i32* %e, align 4
+; CHECK-LABEL: funcC:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtsi2ssl (%rdi), %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %tmp1 = load i32, i32* %e, align 4
   %conv = sitofp i32 %tmp1 to float
   ret float %conv
 }
 
-; CHECK: vcvtsi2ssq  (%
 define float @funcD(i64* nocapture %e) nounwind uwtable readonly ssp {
-entry:
-  %tmp1 = load i64* %e, align 8
+; CHECK-LABEL: funcD:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtsi2ssq (%rdi), %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %tmp1 = load i64, i64* %e, align 8
   %conv = sitofp i64 %tmp1 to float
   ret float %conv
 }
 
-; CHECK: vcvtss2sd
 define void @fpext() nounwind uwtable {
-entry:
+; CHECK-LABEL: fpext:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:    vcvtss2sd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    vmovsd %xmm0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    retq
   %f = alloca float, align 4
   %d = alloca double, align 8
-  %tmp = load float* %f, align 4
+  %tmp = load float, float* %f, align 4
   %conv = fpext float %tmp to double
   store double %conv, double* %d, align 8
   ret void
 }
 
+define double @nearbyint_f64(double %a) {
+; CHECK-LABEL: nearbyint_f64:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vroundsd $12, %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %res = call double @llvm.nearbyint.f64(double %a)
+  ret double %res
+}
+declare double @llvm.nearbyint.f64(double %p)
+
+define float @floor_f32(float %a) {
+; CHECK-LABEL: floor_f32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vroundss $1, %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %res = call float @llvm.floor.f32(float %a)
+  ret float %res
+}
+declare float @llvm.floor.f32(float %p)
+
+
diff --git a/test/CodeGen/X86/avx-insertelt.ll b/test/CodeGen/X86/avx-insertelt.ll
new file mode 100644
index 000000000000..c159d689451b
--- /dev/null
+++ b/test/CodeGen/X86/avx-insertelt.ll
@@ -0,0 +1,83 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx  | FileCheck %s --check-prefix=ALL --check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX2
+
+define <8 x float> @insert_f32(<8 x float> %y, float %f, <8 x float> %x) {
+; ALL-LABEL: insert_f32:
+; ALL:         vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7]
+; ALL-NEXT:    retq
+  %i0 = insertelement <8 x float> %y, float %f, i32 0
+  ret <8 x float> %i0
+}
+
+define <4 x double> @insert_f64(<4 x double> %y, double %f, <4 x double> %x) {
+; ALL-LABEL: insert_f64:
+; ALL:         vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3]
+; ALL-NEXT:    retq
+  %i0 = insertelement <4 x double> %y, double %f, i32 0
+  ret <4 x double> %i0
+}
+
+define <32 x i8> @insert_i8(<32 x i8> %y, i8 %f, <32 x i8> %x) {
+; AVX-LABEL: insert_i8:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpinsrb $0, %edi, %xmm0, %xmm1
+; AVX-NEXT:    vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
+; AVX-NEXT:    retq
+;
+; AVX2-LABEL: insert_i8:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpinsrb $0, %edi, %xmm0, %xmm1
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
+; AVX2-NEXT:    retq
+  %i0 = insertelement <32 x i8> %y, i8 %f, i32 0
+  ret <32 x i8> %i0
+}
+
+define <16 x i16> @insert_i16(<16 x i16> %y, i16 %f, <16 x i16> %x) {
+; AVX-LABEL: insert_i16:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpinsrw $0, %edi, %xmm0, %xmm1
+; AVX-NEXT:    vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
+; AVX-NEXT:    retq
+;
+; AVX2-LABEL: insert_i16:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpinsrw $0, %edi, %xmm0, %xmm1
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
+; AVX2-NEXT:    retq
+  %i0 = insertelement <16 x i16> %y, i16 %f, i32 0
+  ret <16 x i16> %i0
+}
+
+define <8 x i32> @insert_i32(<8 x i32> %y, i32 %f, <8 x i32> %x) {
+; AVX-LABEL: insert_i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpinsrd $0, %edi, %xmm0, %xmm1
+; AVX-NEXT:    vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
+; AVX-NEXT:    retq
+;
+; AVX2-LABEL: insert_i32:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vmovd %edi, %xmm1
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7]
+; AVX2-NEXT:    retq
+  %i0 = insertelement <8 x i32> %y, i32 %f, i32 0
+  ret <8 x i32> %i0
+}
+
+define <4 x i64> @insert_i64(<4 x i64> %y, i64 %f, <4 x i64> %x) {
+; AVX-LABEL: insert_i64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpinsrq $0, %rdi, %xmm0, %xmm1
+; AVX-NEXT:    vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
+; AVX-NEXT:    retq
+;
+; AVX2-LABEL: insert_i64:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpinsrq $0, %rdi, %xmm0, %xmm1
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
+; AVX2-NEXT:    retq
+  %i0 = insertelement <4 x i64> %y, i64 %f, i32 0
+  ret <4 x i64> %i0
+}
+
diff --git a/test/CodeGen/X86/avx-intel-ocl.ll b/test/CodeGen/X86/avx-intel-ocl.ll
index 70ec1248cdd7..3923ca850d1a 100644
--- a/test/CodeGen/X86/avx-intel-ocl.ll
+++ b/test/CodeGen/X86/avx-intel-ocl.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=X32 %s
-; RUN: llc < %s -mtriple=i386-pc-win32 -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=X32 %s
-; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=WIN64 %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=X64 %s
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx | FileCheck -check-prefix=X32 %s
+; RUN: llc < %s -mtriple=i386-pc-win32 -mattr=+avx | FileCheck -check-prefix=X32 %s
+; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+avx | FileCheck -check-prefix=WIN64 %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck -check-prefix=X64 %s
 
 declare <16 x float> @func_float16_ptr(<16 x float>, <16 x float> *)
 declare <16 x float> @func_float16(<16 x float>, <16 x float>)
@@ -33,7 +33,7 @@ define <16 x float> @testf16_inp(<16 x float> %a, <16 x float> %b) nounwind {
   %y = alloca <16 x float>, align 16
   %x = fadd <16 x float> %a, %b
   %1 = call intel_ocl_bicc <16 x float> @func_float16_ptr(<16 x float> %x, <16 x float>* %y)
-  %2 = load <16 x float>* %y, align 16
+  %2 = load <16 x float>, <16 x float>* %y, align 16
   %3 = fadd <16 x float> %2, %1
   ret <16 x float> %3
 }
@@ -58,7 +58,7 @@ define <16 x float> @testf16_regs(<16 x float> %a, <16 x float> %b) nounwind {
   %y = alloca <16 x float>, align 16
   %x = fadd <16 x float> %a, %b
   %1 = call intel_ocl_bicc <16 x float> @func_float16_ptr(<16 x float> %x, <16 x float>* %y)
-  %2 = load <16 x float>* %y, align 16
+  %2 = load <16 x float>, <16 x float>* %y, align 16
   %3 = fadd <16 x float> %1, %b
   %4 = fadd <16 x float> %2, %3
   ret <16 x float> %4
diff --git a/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll b/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll
index d2b44cd64efb..e2f690bff232 100644
--- a/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll
+++ b/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll
@@ -1,7 +1,81 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=corei7-avx | FileCheck %s
 
+; We don't check any vinsertf128 variant with immediate 0 because that's just a blend. 
+
+define <4 x double> @test_x86_avx_vinsertf128_pd_256_1(<4 x double> %a0, <2 x double> %a1) {
+; CHECK-LABEL:       test_x86_avx_vinsertf128_pd_256_1: 
+; CHECK:             vinsertf128 $1, %xmm1, %ymm0, %ymm0
+  %res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> %a0, <2 x double> %a1, i8 1)
+  ret <4 x double> %res
+}
+declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double>, i8) nounwind readnone
+
+define <8 x float> @test_x86_avx_vinsertf128_ps_256_1(<8 x float> %a0, <4 x float> %a1) {
+; CHECK-LABEL:      test_x86_avx_vinsertf128_ps_256_1: 
+; CHECK:            vinsertf128 $1, %xmm1, %ymm0, %ymm0
+  %res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %a0, <4 x float> %a1, i8 1)
+  ret <8 x float> %res
+}
+declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i8) nounwind readnone
+
+define <8 x i32> @test_x86_avx_vinsertf128_si_256_1(<8 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL:    test_x86_avx_vinsertf128_si_256_1: 
+; CHECK:          vinsertf128 $1, %xmm1, %ymm0, %ymm0
+  %res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> %a0, <4 x i32> %a1, i8 1)
+  ret <8 x i32> %res
+}
+
+; Verify that high bits of the immediate are masked off. This should be the equivalent
+; of a vinsertf128 $0 which should be optimized into a blend, so just check that it's
+; not a vinsertf128 $1.
+define <8 x i32> @test_x86_avx_vinsertf128_si_256_2(<8 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL:    test_x86_avx_vinsertf128_si_256_2: 
+; CHECK-NOT:      vinsertf128 $1, %xmm1, %ymm0, %ymm0
+  %res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> %a0, <4 x i32> %a1, i8 2)
+  ret <8 x i32> %res
+}
+declare <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32>, <4 x i32>, i8) nounwind readnone
+
+; We don't check any vextractf128 variant with immediate 0 because that's just a move. 
+
+define <2 x double> @test_x86_avx_vextractf128_pd_256_1(<4 x double> %a0) {
+; CHECK-LABEL:       test_x86_avx_vextractf128_pd_256_1: 
+; CHECK:             vextractf128 $1, %ymm0, %xmm0
+  %res = call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a0, i8 1)
+  ret <2 x double> %res
+}
+declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone
+
+define <4 x float> @test_x86_avx_vextractf128_ps_256_1(<8 x float> %a0) {
+; CHECK-LABEL:       test_x86_avx_vextractf128_ps_256_1: 
+; CHECK:             vextractf128 $1, %ymm0, %xmm0
+  %res = call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a0, i8 1)
+  ret <4 x float> %res
+}
+declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone
+
+define <4 x i32> @test_x86_avx_vextractf128_si_256_1(<8 x i32> %a0) {
+; CHECK-LABEL:    test_x86_avx_vextractf128_si_256_1: 
+; CHECK:          vextractf128 $1, %ymm0, %xmm0
+  %res = call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %a0, i8 1)
+  ret <4 x i32> %res
+}
+declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind readnone
+
+; Verify that high bits of the immediate are masked off. This should be the equivalent
+; of a vextractf128 $0 which should be optimized away, so just check that it's
+; not a vextractf128 of any kind.
+define <2 x double> @test_x86_avx_extractf128_pd_256_2(<4 x double> %a0) {
+; CHECK-LABEL:       test_x86_avx_extractf128_pd_256_2: 
+; CHECK-NOT:         vextractf128
+  %res = call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a0, i8 2)
+  ret <2 x double> %res
+}
+
+
 define <4 x double> @test_x86_avx_blend_pd_256(<4 x double> %a0, <4 x double> %a1) {
-  ; CHECK: vblendpd
+; CHECK-LABEL:       test_x86_avx_blend_pd_256: 
+; CHECK:             vblendpd
   %res = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a1, i32 7) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -9,7 +83,8 @@ declare <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double>, <4 x double>, i32)
 
 
 define <8 x float> @test_x86_avx_blend_ps_256(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vblendps
+; CHECK-LABEL:      test_x86_avx_blend_ps_256: 
+; CHECK:            vblendps
   %res = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a1, i32 7) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -17,10 +92,54 @@ declare <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float>, <8 x float>, i32) no
 
 
 define <8 x float> @test_x86_avx_dp_ps_256(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vdpps
+; CHECK-LABEL:      test_x86_avx_dp_ps_256: 
+; CHECK:            vdpps
   %res = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> %a0, <8 x float> %a1, i32 7) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
 declare <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float>, <8 x float>, i32) nounwind readnone
 
 
+define <2 x i64> @test_x86_sse2_psll_dq(<2 x i64> %a0) {
+; CHECK-LABEL:    test_x86_sse2_psll_dq: 
+; CHECK:          vpslldq {{.*#+}} xmm0 = zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
+  %res = call <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1]
+  ret <2 x i64> %res
+}
+declare <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64>, i32) nounwind readnone
+
+
+define <2 x i64> @test_x86_sse2_psrl_dq(<2 x i64> %a0) {
+; CHECK-LABEL:    test_x86_sse2_psrl_dq: 
+; CHECK:          vpsrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero
+  %res = call <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1]
+  ret <2 x i64> %res
+}
+declare <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64>, i32) nounwind readnone
+
+
+define <2 x double> @test_x86_sse41_blendpd(<2 x double> %a0, <2 x double> %a1) {
+; CHECK-LABEL:       test_x86_sse41_blendpd: 
+; CHECK:             vblendpd
+  %res = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %a0, <2 x double> %a1, i8 2) ; <<2 x double>> [#uses=1]
+  ret <2 x double> %res
+}
+declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i8) nounwind readnone
+
+
+define <4 x float> @test_x86_sse41_blendps(<4 x float> %a0, <4 x float> %a1) {
+; CHECK-LABEL:      test_x86_sse41_blendps: 
+; CHECK:            vblendps
+  %res = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
+  ret <4 x float> %res
+}
+declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i8) nounwind readnone
+
+
+define <8 x i16> @test_x86_sse41_pblendw(<8 x i16> %a0, <8 x i16> %a1) {
+; CHECK-LABEL:    test_x86_sse41_pblendw: 
+; CHECK:          vpblendw
+  %res = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %a0, <8 x i16> %a1, i8 7) ; <<8 x i16>> [#uses=1]
+  ret <8 x i16> %res
+}
+declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i8) nounwind readnone
diff --git a/test/CodeGen/X86/avx-intrinsics-x86.ll b/test/CodeGen/X86/avx-intrinsics-x86.ll
index bb9354cff038..28a0272ecf02 100644
--- a/test/CodeGen/X86/avx-intrinsics-x86.ll
+++ b/test/CodeGen/X86/avx-intrinsics-x86.ll
@@ -1,7 +1,10 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=corei7-avx | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mattr=avx,aes,pclmul | FileCheck %s
 
 define <2 x i64> @test_x86_aesni_aesdec(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vaesdec
+; CHECK-LABEL: test_x86_aesni_aesdec:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vaesdec %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -9,7 +12,10 @@ declare <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64>, <2 x i64>) nounwind readnone
 
 
 define <2 x i64> @test_x86_aesni_aesdeclast(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vaesdeclast
+; CHECK-LABEL: test_x86_aesni_aesdeclast:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vaesdeclast %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -17,7 +23,10 @@ declare <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64>, <2 x i64>) nounwind read
 
 
 define <2 x i64> @test_x86_aesni_aesenc(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vaesenc
+; CHECK-LABEL: test_x86_aesni_aesenc:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vaesenc %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -25,7 +34,10 @@ declare <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64>, <2 x i64>) nounwind readnone
 
 
 define <2 x i64> @test_x86_aesni_aesenclast(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vaesenclast
+; CHECK-LABEL: test_x86_aesni_aesenclast:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vaesenclast %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -33,7 +45,10 @@ declare <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64>, <2 x i64>) nounwind read
 
 
 define <2 x i64> @test_x86_aesni_aesimc(<2 x i64> %a0) {
-  ; CHECK: vaesimc
+; CHECK-LABEL: test_x86_aesni_aesimc:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vaesimc %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64> %a0) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -41,7 +56,10 @@ declare <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64>) nounwind readnone
 
 
 define <2 x i64> @test_x86_aesni_aeskeygenassist(<2 x i64> %a0) {
-  ; CHECK: vaeskeygenassist
+; CHECK-LABEL: test_x86_aesni_aeskeygenassist:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vaeskeygenassist $7, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64> %a0, i8 7) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -49,7 +67,10 @@ declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8) nounwind readno
 
 
 define <2 x double> @test_x86_sse2_add_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vaddsd
+; CHECK-LABEL: test_x86_sse2_add_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -57,7 +78,10 @@ declare <2 x double> @llvm.x86.sse2.add.sd(<2 x double>, <2 x double>) nounwind
 
 
 define <2 x double> @test_x86_sse2_cmp_pd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vcmpordpd
+; CHECK-LABEL: test_x86_sse2_cmp_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcmpordpd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -65,7 +89,10 @@ declare <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double>, <2 x double>, i8) nounw
 
 
 define <2 x double> @test_x86_sse2_cmp_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vcmpordsd
+; CHECK-LABEL: test_x86_sse2_cmp_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcmpordsd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -73,9 +100,12 @@ declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounw
 
 
 define i32 @test_x86_sse2_comieq_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vcomisd
-  ; CHECK: sete
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse2_comieq_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcomisd %xmm1, %xmm0
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -83,9 +113,12 @@ declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readno
 
 
 define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vcomisd
-  ; CHECK: setae
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse2_comige_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcomisd %xmm1, %xmm0
+; CHECK-NEXT:    setae %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -93,9 +126,12 @@ declare i32 @llvm.x86.sse2.comige.sd(<2 x double>, <2 x double>) nounwind readno
 
 
 define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vcomisd
-  ; CHECK: seta
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse2_comigt_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcomisd %xmm1, %xmm0
+; CHECK-NEXT:    seta %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -103,9 +139,12 @@ declare i32 @llvm.x86.sse2.comigt.sd(<2 x double>, <2 x double>) nounwind readno
 
 
 define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vcomisd
-  ; CHECK: setbe
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse2_comile_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcomisd %xmm1, %xmm0
+; CHECK-NEXT:    setbe %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.comile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -113,9 +152,12 @@ declare i32 @llvm.x86.sse2.comile.sd(<2 x double>, <2 x double>) nounwind readno
 
 
 define i32 @test_x86_sse2_comilt_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vcomisd
-  ; CHECK: sbbl    %eax, %eax
-  ; CHECK: andl    $1, %eax
+; CHECK-LABEL: test_x86_sse2_comilt_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcomisd %xmm1, %xmm0
+; CHECK-NEXT:    sbbl %eax, %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.comilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -123,9 +165,12 @@ declare i32 @llvm.x86.sse2.comilt.sd(<2 x double>, <2 x double>) nounwind readno
 
 
 define i32 @test_x86_sse2_comineq_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vcomisd
-  ; CHECK: setne
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse2_comineq_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcomisd %xmm1, %xmm0
+; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -133,7 +178,10 @@ declare i32 @llvm.x86.sse2.comineq.sd(<2 x double>, <2 x double>) nounwind readn
 
 
 define <2 x double> @test_x86_sse2_cvtdq2pd(<4 x i32> %a0) {
-  ; CHECK: vcvtdq2pd
+; CHECK-LABEL: test_x86_sse2_cvtdq2pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtdq2pd %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32> %a0) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -141,7 +189,10 @@ declare <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32>) nounwind readnone
 
 
 define <4 x float> @test_x86_sse2_cvtdq2ps(<4 x i32> %a0) {
-  ; CHECK: vcvtdq2ps
+; CHECK-LABEL: test_x86_sse2_cvtdq2ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtdq2ps %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %a0) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -149,7 +200,10 @@ declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse2_cvtpd2dq(<2 x double> %a0) {
-  ; CHECK: vcvtpd2dq
+; CHECK-LABEL: test_x86_sse2_cvtpd2dq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtpd2dq %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -157,7 +211,10 @@ declare <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double>) nounwind readnone
 
 
 define <4 x float> @test_x86_sse2_cvtpd2ps(<2 x double> %a0) {
-  ; CHECK: vcvtpd2ps
+; CHECK-LABEL: test_x86_sse2_cvtpd2ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtpd2ps %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -165,7 +222,10 @@ declare <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse2_cvtps2dq(<4 x float> %a0) {
-  ; CHECK: vcvtps2dq
+; CHECK-LABEL: test_x86_sse2_cvtps2dq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtps2dq %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -173,7 +233,10 @@ declare <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float>) nounwind readnone
 
 
 define <2 x double> @test_x86_sse2_cvtps2pd(<4 x float> %a0) {
-  ; CHECK: vcvtps2pd
+; CHECK-LABEL: test_x86_sse2_cvtps2pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtps2pd %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float> %a0) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -181,7 +244,10 @@ declare <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float>) nounwind readnone
 
 
 define i32 @test_x86_sse2_cvtsd2si(<2 x double> %a0) {
-  ; CHECK: vcvtsd2si
+; CHECK-LABEL: test_x86_sse2_cvtsd2si:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtsd2si %xmm0, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %a0) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -189,7 +255,10 @@ declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone
 
 
 define <4 x float> @test_x86_sse2_cvtsd2ss(<4 x float> %a0, <2 x double> %a1) {
-  ; CHECK: vcvtsd2ss
+; CHECK-LABEL: test_x86_sse2_cvtsd2ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtsd2ss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -197,8 +266,11 @@ declare <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float>, <2 x double>) nounwind
 
 
 define <2 x double> @test_x86_sse2_cvtsi2sd(<2 x double> %a0) {
-  ; CHECK: movl
-  ; CHECK: vcvtsi2sd
+; CHECK-LABEL: test_x86_sse2_cvtsi2sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl $7, %eax
+; CHECK-NEXT:    vcvtsi2sdl %eax, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double> %a0, i32 7) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -206,7 +278,10 @@ declare <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double>, i32) nounwind readnon
 
 
 define <2 x double> @test_x86_sse2_cvtss2sd(<2 x double> %a0, <4 x float> %a1) {
-  ; CHECK: vcvtss2sd
+; CHECK-LABEL: test_x86_sse2_cvtss2sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtss2sd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double> %a0, <4 x float> %a1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -214,7 +289,10 @@ declare <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double>, <4 x float>) nounwind
 
 
 define <4 x i32> @test_x86_sse2_cvttpd2dq(<2 x double> %a0) {
-  ; CHECK: vcvttpd2dq
+; CHECK-LABEL: test_x86_sse2_cvttpd2dq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvttpd2dq %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -222,7 +300,10 @@ declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse2_cvttps2dq(<4 x float> %a0) {
-  ; CHECK: vcvttps2dq
+; CHECK-LABEL: test_x86_sse2_cvttps2dq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -230,7 +311,10 @@ declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone
 
 
 define i32 @test_x86_sse2_cvttsd2si(<2 x double> %a0) {
-  ; CHECK: vcvttsd2si
+; CHECK-LABEL: test_x86_sse2_cvttsd2si:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvttsd2si %xmm0, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %a0) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -238,7 +322,10 @@ declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) nounwind readnone
 
 
 define <2 x double> @test_x86_sse2_div_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vdivsd
+; CHECK-LABEL: test_x86_sse2_div_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vdivsd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -247,7 +334,10 @@ declare <2 x double> @llvm.x86.sse2.div.sd(<2 x double>, <2 x double>) nounwind
 
 
 define <2 x double> @test_x86_sse2_max_pd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vmaxpd
+; CHECK-LABEL: test_x86_sse2_max_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmaxpd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -255,7 +345,10 @@ declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind
 
 
 define <2 x double> @test_x86_sse2_max_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vmaxsd
+; CHECK-LABEL: test_x86_sse2_max_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmaxsd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -263,7 +356,10 @@ declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind
 
 
 define <2 x double> @test_x86_sse2_min_pd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vminpd
+; CHECK-LABEL: test_x86_sse2_min_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vminpd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -271,7 +367,10 @@ declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind
 
 
 define <2 x double> @test_x86_sse2_min_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vminsd
+; CHECK-LABEL: test_x86_sse2_min_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vminsd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -279,7 +378,10 @@ declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind
 
 
 define i32 @test_x86_sse2_movmsk_pd(<2 x double> %a0) {
-  ; CHECK: vmovmskpd
+; CHECK-LABEL: test_x86_sse2_movmsk_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmovmskpd %xmm0, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %a0) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -289,8 +391,10 @@ declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>) nounwind readnone
 
 
 define <2 x double> @test_x86_sse2_mul_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: test_x86_sse2_mul_sd
-  ; CHECK: vmulsd
+; CHECK-LABEL: test_x86_sse2_mul_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmulsd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.mul.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -298,7 +402,10 @@ declare <2 x double> @llvm.x86.sse2.mul.sd(<2 x double>, <2 x double>) nounwind
 
 
 define <8 x i16> @test_x86_sse2_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpackssdw
+; CHECK-LABEL: test_x86_sse2_packssdw_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %a0, <4 x i32> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -306,7 +413,10 @@ declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>) nounwind rea
 
 
 define <16 x i8> @test_x86_sse2_packsswb_128(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpacksswb
+; CHECK-LABEL: test_x86_sse2_packsswb_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpacksswb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %a0, <8 x i16> %a1) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -314,7 +424,10 @@ declare <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16>, <8 x i16>) nounwind rea
 
 
 define <16 x i8> @test_x86_sse2_packuswb_128(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpackuswb
+; CHECK-LABEL: test_x86_sse2_packuswb_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpackuswb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %a0, <8 x i16> %a1) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -322,7 +435,10 @@ declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>) nounwind rea
 
 
 define <16 x i8> @test_x86_sse2_padds_b(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpaddsb
+; CHECK-LABEL: test_x86_sse2_padds_b:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpaddsb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -330,7 +446,10 @@ declare <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8>, <16 x i8>) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse2_padds_w(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpaddsw
+; CHECK-LABEL: test_x86_sse2_padds_w:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpaddsw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -338,7 +457,10 @@ declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16>, <8 x i16>) nounwind readnone
 
 
 define <16 x i8> @test_x86_sse2_paddus_b(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpaddusb
+; CHECK-LABEL: test_x86_sse2_paddus_b:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpaddusb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -346,7 +468,10 @@ declare <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8>, <16 x i8>) nounwind readnon
 
 
 define <8 x i16> @test_x86_sse2_paddus_w(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpaddusw
+; CHECK-LABEL: test_x86_sse2_paddus_w:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpaddusw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -354,7 +479,10 @@ declare <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16>, <8 x i16>) nounwind readnon
 
 
 define <16 x i8> @test_x86_sse2_pavg_b(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpavgb
+; CHECK-LABEL: test_x86_sse2_pavg_b:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpavgb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -362,7 +490,10 @@ declare <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8>, <16 x i8>) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse2_pavg_w(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpavgw
+; CHECK-LABEL: test_x86_sse2_pavg_w:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpavgw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -370,7 +501,10 @@ declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse2_pmadd_wd(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpmaddwd
+; CHECK-LABEL: test_x86_sse2_pmadd_wd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmaddwd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a0, <8 x i16> %a1) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -378,7 +512,10 @@ declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>) nounwind readnon
 
 
 define <8 x i16> @test_x86_sse2_pmaxs_w(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpmaxsw
+; CHECK-LABEL: test_x86_sse2_pmaxs_w:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -386,7 +523,10 @@ declare <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16>, <8 x i16>) nounwind readnone
 
 
 define <16 x i8> @test_x86_sse2_pmaxu_b(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpmaxub
+; CHECK-LABEL: test_x86_sse2_pmaxu_b:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmaxub %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -394,7 +534,10 @@ declare <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8>, <16 x i8>) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse2_pmins_w(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpminsw
+; CHECK-LABEL: test_x86_sse2_pmins_w:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -402,7 +545,10 @@ declare <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16>, <8 x i16>) nounwind readnone
 
 
 define <16 x i8> @test_x86_sse2_pminu_b(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpminub
+; CHECK-LABEL: test_x86_sse2_pminu_b:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpminub %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -410,7 +556,10 @@ declare <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8>, <16 x i8>) nounwind readnone
 
 
 define i32 @test_x86_sse2_pmovmskb_128(<16 x i8> %a0) {
-  ; CHECK: vpmovmskb
+; CHECK-LABEL: test_x86_sse2_pmovmskb_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmovmskb %xmm0, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %a0) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -418,7 +567,10 @@ declare i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8>) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse2_pmulh_w(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpmulhw
+; CHECK-LABEL: test_x86_sse2_pmulh_w:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmulhw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -426,7 +578,10 @@ declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse2_pmulhu_w(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpmulhuw
+; CHECK-LABEL: test_x86_sse2_pmulhu_w:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmulhuw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -434,7 +589,10 @@ declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>) nounwind readnon
 
 
 define <2 x i64> @test_x86_sse2_pmulu_dq(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpmuludq
+; CHECK-LABEL: test_x86_sse2_pmulu_dq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmuludq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %a0, <4 x i32> %a1) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -442,7 +600,10 @@ declare <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32>, <4 x i32>) nounwind readnon
 
 
 define <2 x i64> @test_x86_sse2_psad_bw(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpsadbw
+; CHECK-LABEL: test_x86_sse2_psad_bw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsadbw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %a0, <16 x i8> %a1) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -450,31 +611,21 @@ declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse2_psll_d(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpslld
+; CHECK-LABEL: test_x86_sse2_psll_d:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpslld %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone
 
 
-define <2 x i64> @test_x86_sse2_psll_dq(<2 x i64> %a0) {
-  ; CHECK: vpslldq {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
-  %res = call <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
-  ret <2 x i64> %res
-}
-declare <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64>, i32) nounwind readnone
-
-
-define <2 x i64> @test_x86_sse2_psll_dq_bs(<2 x i64> %a0) {
-  ; CHECK: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8]
-  %res = call <2 x i64> @llvm.x86.sse2.psll.dq.bs(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
-  ret <2 x i64> %res
-}
-declare <2 x i64> @llvm.x86.sse2.psll.dq.bs(<2 x i64>, i32) nounwind readnone
-
-
 define <2 x i64> @test_x86_sse2_psll_q(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpsllq
+; CHECK-LABEL: test_x86_sse2_psll_q:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsllq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -482,7 +633,10 @@ declare <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64>, <2 x i64>) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse2_psll_w(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpsllw
+; CHECK-LABEL: test_x86_sse2_psll_w:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsllw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -490,7 +644,10 @@ declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse2_pslli_d(<4 x i32> %a0) {
-  ; CHECK: vpslld
+; CHECK-LABEL: test_x86_sse2_pslli_d:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpslld $7, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -498,7 +655,10 @@ declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32) nounwind readnone
 
 
 define <2 x i64> @test_x86_sse2_pslli_q(<2 x i64> %a0) {
-  ; CHECK: vpsllq
+; CHECK-LABEL: test_x86_sse2_pslli_q:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsllq $7, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -506,7 +666,10 @@ declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse2_pslli_w(<8 x i16> %a0) {
-  ; CHECK: vpsllw
+; CHECK-LABEL: test_x86_sse2_pslli_w:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsllw $7, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -514,7 +677,10 @@ declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse2_psra_d(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpsrad
+; CHECK-LABEL: test_x86_sse2_psra_d:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsrad %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -522,7 +688,10 @@ declare <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32>, <4 x i32>) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse2_psra_w(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpsraw
+; CHECK-LABEL: test_x86_sse2_psra_w:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsraw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -530,7 +699,10 @@ declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse2_psrai_d(<4 x i32> %a0) {
-  ; CHECK: vpsrad
+; CHECK-LABEL: test_x86_sse2_psrai_d:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsrad $7, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -538,7 +710,10 @@ declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse2_psrai_w(<8 x i16> %a0) {
-  ; CHECK: vpsraw
+; CHECK-LABEL: test_x86_sse2_psrai_w:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsraw $7, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -546,31 +721,21 @@ declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse2_psrl_d(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpsrld
+; CHECK-LABEL: test_x86_sse2_psrl_d:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsrld %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32>, <4 x i32>) nounwind readnone
 
 
-define <2 x i64> @test_x86_sse2_psrl_dq(<2 x i64> %a0) {
-  ; CHECK: vpsrldq {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
-  %res = call <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
-  ret <2 x i64> %res
-}
-declare <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64>, i32) nounwind readnone
-
-
-define <2 x i64> @test_x86_sse2_psrl_dq_bs(<2 x i64> %a0) {
-  ; CHECK: vpsrldq {{.*#+}} xmm0 = xmm0[7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero
-  %res = call <2 x i64> @llvm.x86.sse2.psrl.dq.bs(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
-  ret <2 x i64> %res
-}
-declare <2 x i64> @llvm.x86.sse2.psrl.dq.bs(<2 x i64>, i32) nounwind readnone
-
-
 define <2 x i64> @test_x86_sse2_psrl_q(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpsrlq
+; CHECK-LABEL: test_x86_sse2_psrl_q:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsrlq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -578,7 +743,10 @@ declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse2_psrl_w(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpsrlw
+; CHECK-LABEL: test_x86_sse2_psrl_w:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsrlw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -586,7 +754,10 @@ declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse2_psrli_d(<4 x i32> %a0) {
-  ; CHECK: vpsrld
+; CHECK-LABEL: test_x86_sse2_psrli_d:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsrld $7, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -594,7 +765,10 @@ declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32) nounwind readnone
 
 
 define <2 x i64> @test_x86_sse2_psrli_q(<2 x i64> %a0) {
-  ; CHECK: vpsrlq
+; CHECK-LABEL: test_x86_sse2_psrli_q:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsrlq $7, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -602,7 +776,10 @@ declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse2_psrli_w(<8 x i16> %a0) {
-  ; CHECK: vpsrlw
+; CHECK-LABEL: test_x86_sse2_psrli_w:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsrlw $7, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -610,7 +787,10 @@ declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32) nounwind readnone
 
 
 define <16 x i8> @test_x86_sse2_psubs_b(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpsubsb
+; CHECK-LABEL: test_x86_sse2_psubs_b:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsubsb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -618,7 +798,10 @@ declare <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8>, <16 x i8>) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse2_psubs_w(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpsubsw
+; CHECK-LABEL: test_x86_sse2_psubs_w:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsubsw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -626,7 +809,10 @@ declare <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16>, <8 x i16>) nounwind readnone
 
 
 define <16 x i8> @test_x86_sse2_psubus_b(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpsubusb
+; CHECK-LABEL: test_x86_sse2_psubus_b:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsubusb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -634,7 +820,10 @@ declare <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8>, <16 x i8>) nounwind readnon
 
 
 define <8 x i16> @test_x86_sse2_psubus_w(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpsubusw
+; CHECK-LABEL: test_x86_sse2_psubus_w:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsubusw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -642,7 +831,10 @@ declare <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16>, <8 x i16>) nounwind readnon
 
 
 define <2 x double> @test_x86_sse2_sqrt_pd(<2 x double> %a0) {
-  ; CHECK: vsqrtpd
+; CHECK-LABEL: test_x86_sse2_sqrt_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vsqrtpd %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double> %a0) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -650,7 +842,10 @@ declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>) nounwind readnone
 
 
 define <2 x double> @test_x86_sse2_sqrt_sd(<2 x double> %a0) {
-  ; CHECK: vsqrtsd
+; CHECK-LABEL: test_x86_sse2_sqrt_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vsqrtsd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a0) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -658,9 +853,11 @@ declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
 
 
 define void @test_x86_sse2_storel_dq(i8* %a0, <4 x i32> %a1) {
-  ; CHECK: test_x86_sse2_storel_dq
-  ; CHECK: movl
-  ; CHECK: vmovq
+; CHECK-LABEL: test_x86_sse2_storel_dq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vmovlps %xmm0, (%eax)
+; CHECK-NEXT:    retl
   call void @llvm.x86.sse2.storel.dq(i8* %a0, <4 x i32> %a1)
   ret void
 }
@@ -668,10 +865,13 @@ declare void @llvm.x86.sse2.storel.dq(i8*, <4 x i32>) nounwind
 
 
 define void @test_x86_sse2_storeu_dq(i8* %a0, <16 x i8> %a1) {
-  ; CHECK: test_x86_sse2_storeu_dq
-  ; CHECK: movl
-  ; CHECK: vmovdqu
   ; add operation forces the execution domain.
+; CHECK-LABEL: test_x86_sse2_storeu_dq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vpaddb LCPI77_0, %xmm0, %xmm0
+; CHECK-NEXT:    vmovdqu %xmm0, (%eax)
+; CHECK-NEXT:    retl
   %a2 = add <16 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   call void @llvm.x86.sse2.storeu.dq(i8* %a0, <16 x i8> %a2)
   ret void
@@ -680,10 +880,15 @@ declare void @llvm.x86.sse2.storeu.dq(i8*, <16 x i8>) nounwind
 
 
 define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) {
-  ; CHECK: test_x86_sse2_storeu_pd
-  ; CHECK: movl
-  ; CHECK: vmovupd
   ; fadd operation forces the execution domain.
+; CHECK-LABEL: test_x86_sse2_storeu_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
+; CHECK-NEXT:    vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
+; CHECK-NEXT:    vaddpd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vmovupd %xmm0, (%eax)
+; CHECK-NEXT:    retl
   %a2 = fadd <2 x double> %a1, <double 0x0, double 0x4200000000000000>
   call void @llvm.x86.sse2.storeu.pd(i8* %a0, <2 x double> %a2)
   ret void
@@ -692,8 +897,10 @@ declare void @llvm.x86.sse2.storeu.pd(i8*, <2 x double>) nounwind
 
 
 define <2 x double> @test_x86_sse2_sub_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: test_x86_sse2_sub_sd
-  ; CHECK: vsubsd
+; CHECK-LABEL: test_x86_sse2_sub_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vsubsd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -701,9 +908,12 @@ declare <2 x double> @llvm.x86.sse2.sub.sd(<2 x double>, <2 x double>) nounwind
 
 
 define i32 @test_x86_sse2_ucomieq_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vucomisd
-  ; CHECK: sete
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse2_ucomieq_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vucomisd %xmm1, %xmm0
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -711,9 +921,12 @@ declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>) nounwind readn
 
 
 define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vucomisd
-  ; CHECK: setae
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse2_ucomige_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vucomisd %xmm1, %xmm0
+; CHECK-NEXT:    setae %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -721,9 +934,12 @@ declare i32 @llvm.x86.sse2.ucomige.sd(<2 x double>, <2 x double>) nounwind readn
 
 
 define i32 @test_x86_sse2_ucomigt_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vucomisd
-  ; CHECK: seta
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse2_ucomigt_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vucomisd %xmm1, %xmm0
+; CHECK-NEXT:    seta %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -731,9 +947,12 @@ declare i32 @llvm.x86.sse2.ucomigt.sd(<2 x double>, <2 x double>) nounwind readn
 
 
 define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vucomisd
-  ; CHECK: setbe
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse2_ucomile_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vucomisd %xmm1, %xmm0
+; CHECK-NEXT:    setbe %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -741,8 +960,12 @@ declare i32 @llvm.x86.sse2.ucomile.sd(<2 x double>, <2 x double>) nounwind readn
 
 
 define i32 @test_x86_sse2_ucomilt_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vucomisd
-  ; CHECK: sbbl
+; CHECK-LABEL: test_x86_sse2_ucomilt_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vucomisd %xmm1, %xmm0
+; CHECK-NEXT:    sbbl %eax, %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -750,9 +973,12 @@ declare i32 @llvm.x86.sse2.ucomilt.sd(<2 x double>, <2 x double>) nounwind readn
 
 
 define i32 @test_x86_sse2_ucomineq_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vucomisd
-  ; CHECK: setne
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse2_ucomineq_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vucomisd %xmm1, %xmm0
+; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -760,7 +986,10 @@ declare i32 @llvm.x86.sse2.ucomineq.sd(<2 x double>, <2 x double>) nounwind read
 
 
 define <2 x double> @test_x86_sse3_addsub_pd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vaddsubpd
+; CHECK-LABEL: test_x86_sse3_addsub_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vaddsubpd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -768,7 +997,10 @@ declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwi
 
 
 define <4 x float> @test_x86_sse3_addsub_ps(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vaddsubps
+; CHECK-LABEL: test_x86_sse3_addsub_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vaddsubps %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -776,7 +1008,10 @@ declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind
 
 
 define <2 x double> @test_x86_sse3_hadd_pd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vhaddpd
+; CHECK-LABEL: test_x86_sse3_hadd_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vhaddpd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -784,7 +1019,10 @@ declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>) nounwind
 
 
 define <4 x float> @test_x86_sse3_hadd_ps(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vhaddps
+; CHECK-LABEL: test_x86_sse3_hadd_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vhaddps %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -792,7 +1030,10 @@ declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind re
 
 
 define <2 x double> @test_x86_sse3_hsub_pd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vhsubpd
+; CHECK-LABEL: test_x86_sse3_hsub_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vhsubpd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -800,7 +1041,10 @@ declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind
 
 
 define <4 x float> @test_x86_sse3_hsub_ps(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vhsubps
+; CHECK-LABEL: test_x86_sse3_hsub_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vhsubps %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -808,32 +1052,22 @@ declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind re
 
 
 define <16 x i8> @test_x86_sse3_ldu_dq(i8* %a0) {
-  ; CHECK: movl
-  ; CHECK: vlddqu
+; CHECK-LABEL: test_x86_sse3_ldu_dq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vlddqu (%eax), %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %a0) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8*) nounwind readonly
 
 
-define <2 x double> @test_x86_sse41_blendpd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vblendpd
-  %res = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1]
-  ret <2 x double> %res
-}
-declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i8) nounwind readnone
-
-
-define <4 x float> @test_x86_sse41_blendps(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vblendps
-  %res = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
-  ret <4 x float> %res
-}
-declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i8) nounwind readnone
-
-
 define <2 x double> @test_x86_sse41_blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) {
-  ; CHECK: vblendvpd
+; CHECK-LABEL: test_x86_sse41_blendvpd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vblendvpd %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse41.blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -841,7 +1075,10 @@ declare <2 x double> @llvm.x86.sse41.blendvpd(<2 x double>, <2 x double>, <2 x d
 
 
 define <4 x float> @test_x86_sse41_blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
-  ; CHECK: vblendvps
+; CHECK-LABEL: test_x86_sse41_blendvps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vblendvps %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -849,7 +1086,10 @@ declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x floa
 
 
 define <2 x double> @test_x86_sse41_dppd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vdppd
+; CHECK-LABEL: test_x86_sse41_dppd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vdppd $7, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse41.dppd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -857,7 +1097,10 @@ declare <2 x double> @llvm.x86.sse41.dppd(<2 x double>, <2 x double>, i8) nounwi
 
 
 define <4 x float> @test_x86_sse41_dpps(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vdpps
+; CHECK-LABEL: test_x86_sse41_dpps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vdpps $7, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse41.dpps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -865,7 +1108,10 @@ declare <4 x float> @llvm.x86.sse41.dpps(<4 x float>, <4 x float>, i8) nounwind
 
 
 define <4 x float> @test_x86_sse41_insertps(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vinsertps
+; CHECK-LABEL: test_x86_sse41_insertps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vinsertps {{.*#+}} xmm0 = zero,zero,zero,xmm0[3]
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -874,7 +1120,10 @@ declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounw
 
 
 define <8 x i16> @test_x86_sse41_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vmpsadbw
+; CHECK-LABEL: test_x86_sse41_mpsadbw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmpsadbw $7, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -882,7 +1131,10 @@ declare <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8>, <16 x i8>, i8) nounwind rea
 
 
 define <8 x i16> @test_x86_sse41_packusdw(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpackusdw
+; CHECK-LABEL: test_x86_sse41_packusdw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpackusdw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -890,23 +1142,21 @@ declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>) nounwind readno
 
 
 define <16 x i8> @test_x86_sse41_pblendvb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) {
-  ; CHECK: vpblendvb
+; CHECK-LABEL: test_x86_sse41_pblendvb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
 
 
-define <8 x i16> @test_x86_sse41_pblendw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpblendw
-  %res = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %a0, <8 x i16> %a1, i8 7) ; <<8 x i16>> [#uses=1]
-  ret <8 x i16> %res
-}
-declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i8) nounwind readnone
-
-
 define <8 x i16> @test_x86_sse41_phminposuw(<8 x i16> %a0) {
-  ; CHECK: vphminposuw
+; CHECK-LABEL: test_x86_sse41_phminposuw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphminposuw %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16> %a0) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -914,7 +1164,10 @@ declare <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16>) nounwind readnone
 
 
 define <16 x i8> @test_x86_sse41_pmaxsb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpmaxsb
+; CHECK-LABEL: test_x86_sse41_pmaxsb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -922,7 +1175,10 @@ declare <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8>, <16 x i8>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse41_pmaxsd(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpmaxsd
+; CHECK-LABEL: test_x86_sse41_pmaxsd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -930,7 +1186,10 @@ declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse41_pmaxud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpmaxud
+; CHECK-LABEL: test_x86_sse41_pmaxud:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmaxud %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -938,7 +1197,10 @@ declare <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32>, <4 x i32>) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse41_pmaxuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpmaxuw
+; CHECK-LABEL: test_x86_sse41_pmaxuw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmaxuw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -946,7 +1208,10 @@ declare <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 
 define <16 x i8> @test_x86_sse41_pminsb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpminsb
+; CHECK-LABEL: test_x86_sse41_pminsb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -954,7 +1219,10 @@ declare <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8>, <16 x i8>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse41_pminsd(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpminsd
+; CHECK-LABEL: test_x86_sse41_pminsd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -962,7 +1230,10 @@ declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse41_pminud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpminud
+; CHECK-LABEL: test_x86_sse41_pminud:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpminud %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -970,7 +1241,10 @@ declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse41_pminuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpminuw
+; CHECK-LABEL: test_x86_sse41_pminuw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpminuw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -978,7 +1252,10 @@ declare <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse41_pmovsxbd(<16 x i8> %a0) {
-  ; CHECK: vpmovsxbd
+; CHECK-LABEL: test_x86_sse41_pmovsxbd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmovsxbd %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %a0) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -986,7 +1263,10 @@ declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
 
 
 define <2 x i64> @test_x86_sse41_pmovsxbq(<16 x i8> %a0) {
-  ; CHECK: vpmovsxbq
+; CHECK-LABEL: test_x86_sse41_pmovsxbq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmovsxbq %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8> %a0) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -994,7 +1274,10 @@ declare <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8>) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse41_pmovsxbw(<16 x i8> %a0) {
-  ; CHECK: vpmovsxbw
+; CHECK-LABEL: test_x86_sse41_pmovsxbw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmovsxbw %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8> %a0) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -1002,7 +1285,10 @@ declare <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8>) nounwind readnone
 
 
 define <2 x i64> @test_x86_sse41_pmovsxdq(<4 x i32> %a0) {
-  ; CHECK: vpmovsxdq
+; CHECK-LABEL: test_x86_sse41_pmovsxdq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmovsxdq %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32> %a0) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -1010,7 +1296,10 @@ declare <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse41_pmovsxwd(<8 x i16> %a0) {
-  ; CHECK: vpmovsxwd
+; CHECK-LABEL: test_x86_sse41_pmovsxwd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmovsxwd %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %a0) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -1018,7 +1307,10 @@ declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
 
 
 define <2 x i64> @test_x86_sse41_pmovsxwq(<8 x i16> %a0) {
-  ; CHECK: vpmovsxwq
+; CHECK-LABEL: test_x86_sse41_pmovsxwq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmovsxwq %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16> %a0) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -1026,7 +1318,10 @@ declare <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse41_pmovzxbd(<16 x i8> %a0) {
-  ; CHECK: vpmovzxbd
+; CHECK-LABEL: test_x86_sse41_pmovzxbd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8> %a0) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -1034,7 +1329,10 @@ declare <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8>) nounwind readnone
 
 
 define <2 x i64> @test_x86_sse41_pmovzxbq(<16 x i8> %a0) {
-  ; CHECK: vpmovzxbq
+; CHECK-LABEL: test_x86_sse41_pmovzxbq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %a0) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -1042,7 +1340,10 @@ declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse41_pmovzxbw(<16 x i8> %a0) {
-  ; CHECK: vpmovzxbw
+; CHECK-LABEL: test_x86_sse41_pmovzxbw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %a0) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -1050,7 +1351,10 @@ declare <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8>) nounwind readnone
 
 
 define <2 x i64> @test_x86_sse41_pmovzxdq(<4 x i32> %a0) {
-  ; CHECK: vpmovzxdq
+; CHECK-LABEL: test_x86_sse41_pmovzxdq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32> %a0) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -1058,7 +1362,10 @@ declare <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32>) nounwind readnone
 
 
 define <4 x i32> @test_x86_sse41_pmovzxwd(<8 x i16> %a0) {
-  ; CHECK: vpmovzxwd
+; CHECK-LABEL: test_x86_sse41_pmovzxwd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %a0) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -1066,7 +1373,10 @@ declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone
 
 
 define <2 x i64> @test_x86_sse41_pmovzxwq(<8 x i16> %a0) {
-  ; CHECK: vpmovzxwq
+; CHECK-LABEL: test_x86_sse41_pmovzxwq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16> %a0) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -1074,7 +1384,10 @@ declare <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16>) nounwind readnone
 
 
 define <2 x i64> @test_x86_sse41_pmuldq(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpmuldq
+; CHECK-LABEL: test_x86_sse41_pmuldq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmuldq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> %a0, <4 x i32> %a1) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
@@ -1082,8 +1395,12 @@ declare <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32>, <4 x i32>) nounwind readnone
 
 
 define i32 @test_x86_sse41_ptestc(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vptest 
-  ; CHECK: sbbl
+; CHECK-LABEL: test_x86_sse41_ptestc:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vptest %xmm1, %xmm0
+; CHECK-NEXT:    sbbl %eax, %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %a0, <2 x i64> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1091,9 +1408,12 @@ declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone
 
 
 define i32 @test_x86_sse41_ptestnzc(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vptest 
-  ; CHECK: seta
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse41_ptestnzc:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vptest %xmm1, %xmm0
+; CHECK-NEXT:    seta %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> %a0, <2 x i64> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1101,9 +1421,12 @@ declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone
 
 
 define i32 @test_x86_sse41_ptestz(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vptest 
-  ; CHECK: sete
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse41_ptestz:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vptest %xmm1, %xmm0
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %a0, <2 x i64> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1111,7 +1434,10 @@ declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
 
 
 define <2 x double> @test_x86_sse41_round_pd(<2 x double> %a0) {
-  ; CHECK: vroundpd
+; CHECK-LABEL: test_x86_sse41_round_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vroundpd $7, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse41.round.pd(<2 x double> %a0, i32 7) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -1119,7 +1445,10 @@ declare <2 x double> @llvm.x86.sse41.round.pd(<2 x double>, i32) nounwind readno
 
 
 define <4 x float> @test_x86_sse41_round_ps(<4 x float> %a0) {
-  ; CHECK: vroundps
+; CHECK-LABEL: test_x86_sse41_round_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vroundps $7, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %a0, i32 7) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1127,7 +1456,10 @@ declare <4 x float> @llvm.x86.sse41.round.ps(<4 x float>, i32) nounwind readnone
 
 
 define <2 x double> @test_x86_sse41_round_sd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vroundsd
+; CHECK-LABEL: test_x86_sse41_round_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vroundsd $7, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %a0, <2 x double> %a1, i32 7) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -1135,7 +1467,10 @@ declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) n
 
 
 define <4 x float> @test_x86_sse41_round_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vroundss
+; CHECK-LABEL: test_x86_sse41_round_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vroundss $7, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %a0, <4 x float> %a1, i32 7) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1143,10 +1478,13 @@ declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) noun
 
 
 define i32 @test_x86_sse42_pcmpestri128(<16 x i8> %a0, <16 x i8> %a2) {
-  ; CHECK: movl $7
-  ; CHECK: movl $7
-  ; CHECK: vpcmpestri $7
-  ; CHECK: movl
+; CHECK-LABEL: test_x86_sse42_pcmpestri128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl $7, %eax
+; CHECK-NEXT:    movl $7, %edx
+; CHECK-NEXT:    vpcmpestri $7, %xmm1, %xmm0
+; CHECK-NEXT:    movl %ecx, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse42.pcmpestri128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1154,22 +1492,32 @@ declare i32 @llvm.x86.sse42.pcmpestri128(<16 x i8>, i32, <16 x i8>, i32, i8) nou
 
 
 define i32 @test_x86_sse42_pcmpestri128_load(<16 x i8>* %a0, <16 x i8>* %a2) {
-  ; CHECK: movl $7
-  ; CHECK: movl $7
-  ; CHECK: vpcmpestri $7, (
-  ; CHECK: movl
-  %1 = load <16 x i8>* %a0
-  %2 = load <16 x i8>* %a2
+; CHECK-LABEL: test_x86_sse42_pcmpestri128_load:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vmovdqa (%eax), %xmm0
+; CHECK-NEXT:    movl $7, %eax
+; CHECK-NEXT:    movl $7, %edx
+; CHECK-NEXT:    vpcmpestri $7, (%ecx), %xmm0
+; CHECK-NEXT:    movl %ecx, %eax
+; CHECK-NEXT:    retl
+  %1 = load <16 x i8>, <16 x i8>* %a0
+  %2 = load <16 x i8>, <16 x i8>* %a2
   %res = call i32 @llvm.x86.sse42.pcmpestri128(<16 x i8> %1, i32 7, <16 x i8> %2, i32 7, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
 
 
 define i32 @test_x86_sse42_pcmpestria128(<16 x i8> %a0, <16 x i8> %a2) {
-  ; CHECK: movl
-  ; CHECK: movl
-  ; CHECK: vpcmpestri
-  ; CHECK: seta
+; CHECK-LABEL: test_x86_sse42_pcmpestria128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl $7, %eax
+; CHECK-NEXT:    movl $7, %edx
+; CHECK-NEXT:    vpcmpestri $7, %xmm1, %xmm0
+; CHECK-NEXT:    seta %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse42.pcmpestria128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1177,10 +1525,14 @@ declare i32 @llvm.x86.sse42.pcmpestria128(<16 x i8>, i32, <16 x i8>, i32, i8) no
 
 
 define i32 @test_x86_sse42_pcmpestric128(<16 x i8> %a0, <16 x i8> %a2) {
-  ; CHECK: movl
-  ; CHECK: movl
-  ; CHECK: vpcmpestri
-  ; CHECK: sbbl
+; CHECK-LABEL: test_x86_sse42_pcmpestric128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl $7, %eax
+; CHECK-NEXT:    movl $7, %edx
+; CHECK-NEXT:    vpcmpestri $7, %xmm1, %xmm0
+; CHECK-NEXT:    sbbl %eax, %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse42.pcmpestric128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1188,10 +1540,14 @@ declare i32 @llvm.x86.sse42.pcmpestric128(<16 x i8>, i32, <16 x i8>, i32, i8) no
 
 
 define i32 @test_x86_sse42_pcmpestrio128(<16 x i8> %a0, <16 x i8> %a2) {
-  ; CHECK: movl
-  ; CHECK: movl
-  ; CHECK: vpcmpestri
-  ; CHECK: seto
+; CHECK-LABEL: test_x86_sse42_pcmpestrio128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl $7, %eax
+; CHECK-NEXT:    movl $7, %edx
+; CHECK-NEXT:    vpcmpestri $7, %xmm1, %xmm0
+; CHECK-NEXT:    seto %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse42.pcmpestrio128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1199,10 +1555,14 @@ declare i32 @llvm.x86.sse42.pcmpestrio128(<16 x i8>, i32, <16 x i8>, i32, i8) no
 
 
 define i32 @test_x86_sse42_pcmpestris128(<16 x i8> %a0, <16 x i8> %a2) {
-  ; CHECK: movl
-  ; CHECK: movl
-  ; CHECK: vpcmpestri
-  ; CHECK: sets
+; CHECK-LABEL: test_x86_sse42_pcmpestris128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl $7, %eax
+; CHECK-NEXT:    movl $7, %edx
+; CHECK-NEXT:    vpcmpestri $7, %xmm1, %xmm0
+; CHECK-NEXT:    sets %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse42.pcmpestris128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1210,10 +1570,14 @@ declare i32 @llvm.x86.sse42.pcmpestris128(<16 x i8>, i32, <16 x i8>, i32, i8) no
 
 
 define i32 @test_x86_sse42_pcmpestriz128(<16 x i8> %a0, <16 x i8> %a2) {
-  ; CHECK: movl
-  ; CHECK: movl
-  ; CHECK: vpcmpestri
-  ; CHECK: sete
+; CHECK-LABEL: test_x86_sse42_pcmpestriz128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl $7, %eax
+; CHECK-NEXT:    movl $7, %edx
+; CHECK-NEXT:    vpcmpestri $7, %xmm1, %xmm0
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse42.pcmpestriz128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1221,10 +1585,12 @@ declare i32 @llvm.x86.sse42.pcmpestriz128(<16 x i8>, i32, <16 x i8>, i32, i8) no
 
 
 define <16 x i8> @test_x86_sse42_pcmpestrm128(<16 x i8> %a0, <16 x i8> %a2) {
-  ; CHECK: movl
-  ; CHECK: movl
-  ; CHECK: vpcmpestrm
-  ; CHECK-NOT: vmov
+; CHECK-LABEL: test_x86_sse42_pcmpestrm128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl $7, %eax
+; CHECK-NEXT:    movl $7, %edx
+; CHECK-NEXT:    vpcmpestrm $7, %xmm1, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -1232,19 +1598,25 @@ declare <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8>, i32, <16 x i8>, i32, i
 
 
 define <16 x i8> @test_x86_sse42_pcmpestrm128_load(<16 x i8> %a0, <16 x i8>* %a2) {
-  ; CHECK: movl $7
-  ; CHECK: movl $7
-  ; CHECK: vpcmpestrm $7,
-  ; CHECK-NOT: vmov
-  %1 = load <16 x i8>* %a2
+; CHECK-LABEL: test_x86_sse42_pcmpestrm128_load:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movl $7, %eax
+; CHECK-NEXT:    movl $7, %edx
+; CHECK-NEXT:    vpcmpestrm $7, (%ecx), %xmm0
+; CHECK-NEXT:    retl
+  %1 = load <16 x i8>, <16 x i8>* %a2
   %res = call <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8> %a0, i32 7, <16 x i8> %1, i32 7, i8 7) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
 
 
 define i32 @test_x86_sse42_pcmpistri128(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcmpistri $7
-  ; CHECK: movl
+; CHECK-LABEL: test_x86_sse42_pcmpistri128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcmpistri $7, %xmm1, %xmm0
+; CHECK-NEXT:    movl %ecx, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse42.pcmpistri128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1252,18 +1624,28 @@ declare i32 @llvm.x86.sse42.pcmpistri128(<16 x i8>, <16 x i8>, i8) nounwind read
 
 
 define i32 @test_x86_sse42_pcmpistri128_load(<16 x i8>* %a0, <16 x i8>* %a1) {
-  ; CHECK: vpcmpistri $7, (
-  ; CHECK: movl
-  %1 = load <16 x i8>* %a0
-  %2 = load <16 x i8>* %a1
+; CHECK-LABEL: test_x86_sse42_pcmpistri128_load:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    vmovdqa (%ecx), %xmm0
+; CHECK-NEXT:    vpcmpistri $7, (%eax), %xmm0
+; CHECK-NEXT:    movl %ecx, %eax
+; CHECK-NEXT:    retl
+  %1 = load <16 x i8>, <16 x i8>* %a0
+  %2 = load <16 x i8>, <16 x i8>* %a1
   %res = call i32 @llvm.x86.sse42.pcmpistri128(<16 x i8> %1, <16 x i8> %2, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
 
 
 define i32 @test_x86_sse42_pcmpistria128(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcmpistri
-  ; CHECK: seta
+; CHECK-LABEL: test_x86_sse42_pcmpistria128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcmpistri $7, %xmm1, %xmm0
+; CHECK-NEXT:    seta %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse42.pcmpistria128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1271,8 +1653,12 @@ declare i32 @llvm.x86.sse42.pcmpistria128(<16 x i8>, <16 x i8>, i8) nounwind rea
 
 
 define i32 @test_x86_sse42_pcmpistric128(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcmpistri
-  ; CHECK: sbbl
+; CHECK-LABEL: test_x86_sse42_pcmpistric128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcmpistri $7, %xmm1, %xmm0
+; CHECK-NEXT:    sbbl %eax, %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse42.pcmpistric128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1280,8 +1666,12 @@ declare i32 @llvm.x86.sse42.pcmpistric128(<16 x i8>, <16 x i8>, i8) nounwind rea
 
 
 define i32 @test_x86_sse42_pcmpistrio128(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcmpistri
-  ; CHECK: seto
+; CHECK-LABEL: test_x86_sse42_pcmpistrio128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcmpistri $7, %xmm1, %xmm0
+; CHECK-NEXT:    seto %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse42.pcmpistrio128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1289,8 +1679,12 @@ declare i32 @llvm.x86.sse42.pcmpistrio128(<16 x i8>, <16 x i8>, i8) nounwind rea
 
 
 define i32 @test_x86_sse42_pcmpistris128(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcmpistri
-  ; CHECK: sets
+; CHECK-LABEL: test_x86_sse42_pcmpistris128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcmpistri $7, %xmm1, %xmm0
+; CHECK-NEXT:    sets %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse42.pcmpistris128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1298,8 +1692,12 @@ declare i32 @llvm.x86.sse42.pcmpistris128(<16 x i8>, <16 x i8>, i8) nounwind rea
 
 
 define i32 @test_x86_sse42_pcmpistriz128(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcmpistri
-  ; CHECK: sete
+; CHECK-LABEL: test_x86_sse42_pcmpistriz128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcmpistri $7, %xmm1, %xmm0
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse42.pcmpistriz128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1307,8 +1705,10 @@ declare i32 @llvm.x86.sse42.pcmpistriz128(<16 x i8>, <16 x i8>, i8) nounwind rea
 
 
 define <16 x i8> @test_x86_sse42_pcmpistrm128(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcmpistrm $7
-  ; CHECK-NOT: vmov
+; CHECK-LABEL: test_x86_sse42_pcmpistrm128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcmpistrm $7, %xmm1, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -1316,16 +1716,22 @@ declare <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8>, <16 x i8>, i8) nounwin
 
 
 define <16 x i8> @test_x86_sse42_pcmpistrm128_load(<16 x i8> %a0, <16 x i8>* %a1) {
-  ; CHECK: vpcmpistrm $7, (
-  ; CHECK-NOT: vmov
-  %1 = load <16 x i8>* %a1
+; CHECK-LABEL: test_x86_sse42_pcmpistrm128_load:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vpcmpistrm $7, (%eax), %xmm0
+; CHECK-NEXT:    retl
+  %1 = load <16 x i8>, <16 x i8>* %a1
   %res = call <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8> %a0, <16 x i8> %1, i8 7) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
 
 
 define <4 x float> @test_x86_sse_add_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vaddss
+; CHECK-LABEL: test_x86_sse_add_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vaddss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1333,7 +1739,10 @@ declare <4 x float> @llvm.x86.sse.add.ss(<4 x float>, <4 x float>) nounwind read
 
 
 define <4 x float> @test_x86_sse_cmp_ps(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vcmpordps
+; CHECK-LABEL: test_x86_sse_cmp_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcmpordps %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1341,7 +1750,10 @@ declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind
 
 
 define <4 x float> @test_x86_sse_cmp_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vcmpordss
+; CHECK-LABEL: test_x86_sse_cmp_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcmpordss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1349,9 +1761,12 @@ declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8) nounwind
 
 
 define i32 @test_x86_sse_comieq_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vcomiss
-  ; CHECK: sete
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse_comieq_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcomiss %xmm1, %xmm0
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1359,9 +1774,12 @@ declare i32 @llvm.x86.sse.comieq.ss(<4 x float>, <4 x float>) nounwind readnone
 
 
 define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vcomiss
-  ; CHECK: setae
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse_comige_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcomiss %xmm1, %xmm0
+; CHECK-NEXT:    setae %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1369,9 +1787,12 @@ declare i32 @llvm.x86.sse.comige.ss(<4 x float>, <4 x float>) nounwind readnone
 
 
 define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vcomiss
-  ; CHECK: seta
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse_comigt_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcomiss %xmm1, %xmm0
+; CHECK-NEXT:    seta %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1379,9 +1800,12 @@ declare i32 @llvm.x86.sse.comigt.ss(<4 x float>, <4 x float>) nounwind readnone
 
 
 define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vcomiss
-  ; CHECK: setbe
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse_comile_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcomiss %xmm1, %xmm0
+; CHECK-NEXT:    setbe %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1389,8 +1813,12 @@ declare i32 @llvm.x86.sse.comile.ss(<4 x float>, <4 x float>) nounwind readnone
 
 
 define i32 @test_x86_sse_comilt_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vcomiss
-  ; CHECK: sbb
+; CHECK-LABEL: test_x86_sse_comilt_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcomiss %xmm1, %xmm0
+; CHECK-NEXT:    sbbl %eax, %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1398,9 +1826,12 @@ declare i32 @llvm.x86.sse.comilt.ss(<4 x float>, <4 x float>) nounwind readnone
 
 
 define i32 @test_x86_sse_comineq_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vcomiss
-  ; CHECK: setne
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse_comineq_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcomiss %xmm1, %xmm0
+; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse.comineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1408,8 +1839,11 @@ declare i32 @llvm.x86.sse.comineq.ss(<4 x float>, <4 x float>) nounwind readnone
 
 
 define <4 x float> @test_x86_sse_cvtsi2ss(<4 x float> %a0) {
-  ; CHECK: movl
-  ; CHECK: vcvtsi2ss
+; CHECK-LABEL: test_x86_sse_cvtsi2ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl $7, %eax
+; CHECK-NEXT:    vcvtsi2ssl %eax, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float> %a0, i32 7) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1417,7 +1851,10 @@ declare <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float>, i32) nounwind readnone
 
 
 define i32 @test_x86_sse_cvtss2si(<4 x float> %a0) {
-  ; CHECK: vcvtss2si
+; CHECK-LABEL: test_x86_sse_cvtss2si:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtss2si %xmm0, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse.cvtss2si(<4 x float> %a0) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1425,7 +1862,10 @@ declare i32 @llvm.x86.sse.cvtss2si(<4 x float>) nounwind readnone
 
 
 define i32 @test_x86_sse_cvttss2si(<4 x float> %a0) {
-  ; CHECK: vcvttss2si
+; CHECK-LABEL: test_x86_sse_cvttss2si:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvttss2si %xmm0, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %a0) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1433,7 +1873,10 @@ declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone
 
 
 define <4 x float> @test_x86_sse_div_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vdivss
+; CHECK-LABEL: test_x86_sse_div_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vdivss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1441,8 +1884,11 @@ declare <4 x float> @llvm.x86.sse.div.ss(<4 x float>, <4 x float>) nounwind read
 
 
 define void @test_x86_sse_ldmxcsr(i8* %a0) {
-  ; CHECK: movl
-  ; CHECK: vldmxcsr
+; CHECK-LABEL: test_x86_sse_ldmxcsr:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vldmxcsr (%eax)
+; CHECK-NEXT:    retl
   call void @llvm.x86.sse.ldmxcsr(i8* %a0)
   ret void
 }
@@ -1451,7 +1897,10 @@ declare void @llvm.x86.sse.ldmxcsr(i8*) nounwind
 
 
 define <4 x float> @test_x86_sse_max_ps(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vmaxps
+; CHECK-LABEL: test_x86_sse_max_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmaxps %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1459,7 +1908,10 @@ declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind read
 
 
 define <4 x float> @test_x86_sse_max_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vmaxss
+; CHECK-LABEL: test_x86_sse_max_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1467,7 +1919,10 @@ declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) nounwind read
 
 
 define <4 x float> @test_x86_sse_min_ps(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vminps
+; CHECK-LABEL: test_x86_sse_min_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vminps %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1475,7 +1930,10 @@ declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind read
 
 
 define <4 x float> @test_x86_sse_min_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vminss
+; CHECK-LABEL: test_x86_sse_min_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vminss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1483,7 +1941,10 @@ declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>) nounwind read
 
 
 define i32 @test_x86_sse_movmsk_ps(<4 x float> %a0) {
-  ; CHECK: vmovmskps
+; CHECK-LABEL: test_x86_sse_movmsk_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmovmskps %xmm0, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %a0) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1492,7 +1953,10 @@ declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone
 
 
 define <4 x float> @test_x86_sse_mul_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vmulss
+; CHECK-LABEL: test_x86_sse_mul_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmulss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1500,7 +1964,10 @@ declare <4 x float> @llvm.x86.sse.mul.ss(<4 x float>, <4 x float>) nounwind read
 
 
 define <4 x float> @test_x86_sse_rcp_ps(<4 x float> %a0) {
-  ; CHECK: vrcpps
+; CHECK-LABEL: test_x86_sse_rcp_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vrcpps %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1508,7 +1975,10 @@ declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>) nounwind readnone
 
 
 define <4 x float> @test_x86_sse_rcp_ss(<4 x float> %a0) {
-  ; CHECK: vrcpss
+; CHECK-LABEL: test_x86_sse_rcp_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vrcpss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1516,7 +1986,10 @@ declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
 
 
 define <4 x float> @test_x86_sse_rsqrt_ps(<4 x float> %a0) {
-  ; CHECK: vrsqrtps
+; CHECK-LABEL: test_x86_sse_rsqrt_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vrsqrtps %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1524,7 +1997,10 @@ declare <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float>) nounwind readnone
 
 
 define <4 x float> @test_x86_sse_rsqrt_ss(<4 x float> %a0) {
-  ; CHECK: vrsqrtss
+; CHECK-LABEL: test_x86_sse_rsqrt_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1532,7 +2008,10 @@ declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
 
 
 define <4 x float> @test_x86_sse_sqrt_ps(<4 x float> %a0) {
-  ; CHECK: vsqrtps
+; CHECK-LABEL: test_x86_sse_sqrt_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vsqrtps %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1540,7 +2019,10 @@ declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>) nounwind readnone
 
 
 define <4 x float> @test_x86_sse_sqrt_ss(<4 x float> %a0) {
-  ; CHECK: vsqrtss
+; CHECK-LABEL: test_x86_sse_sqrt_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1548,8 +2030,11 @@ declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
 
 
 define void @test_x86_sse_stmxcsr(i8* %a0) {
-  ; CHECK: movl
-  ; CHECK: vstmxcsr
+; CHECK-LABEL: test_x86_sse_stmxcsr:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vstmxcsr (%eax)
+; CHECK-NEXT:    retl
   call void @llvm.x86.sse.stmxcsr(i8* %a0)
   ret void
 }
@@ -1557,8 +2042,11 @@ declare void @llvm.x86.sse.stmxcsr(i8*) nounwind
 
 
 define void @test_x86_sse_storeu_ps(i8* %a0, <4 x float> %a1) {
-  ; CHECK: movl
-  ; CHECK: vmovups
+; CHECK-LABEL: test_x86_sse_storeu_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vmovups %xmm0, (%eax)
+; CHECK-NEXT:    retl
   call void @llvm.x86.sse.storeu.ps(i8* %a0, <4 x float> %a1)
   ret void
 }
@@ -1566,7 +2054,10 @@ declare void @llvm.x86.sse.storeu.ps(i8*, <4 x float>) nounwind
 
 
 define <4 x float> @test_x86_sse_sub_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vsubss
+; CHECK-LABEL: test_x86_sse_sub_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vsubss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1574,9 +2065,12 @@ declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>) nounwind read
 
 
 define i32 @test_x86_sse_ucomieq_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vucomiss
-  ; CHECK: sete
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse_ucomieq_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vucomiss %xmm1, %xmm0
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1584,9 +2078,12 @@ declare i32 @llvm.x86.sse.ucomieq.ss(<4 x float>, <4 x float>) nounwind readnone
 
 
 define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vucomiss
-  ; CHECK: setae
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse_ucomige_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vucomiss %xmm1, %xmm0
+; CHECK-NEXT:    setae %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1594,9 +2091,12 @@ declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone
 
 
 define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vucomiss
-  ; CHECK: seta
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse_ucomigt_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vucomiss %xmm1, %xmm0
+; CHECK-NEXT:    seta %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1604,9 +2104,12 @@ declare i32 @llvm.x86.sse.ucomigt.ss(<4 x float>, <4 x float>) nounwind readnone
 
 
 define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vucomiss
-  ; CHECK: setbe
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse_ucomile_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vucomiss %xmm1, %xmm0
+; CHECK-NEXT:    setbe %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1614,8 +2117,12 @@ declare i32 @llvm.x86.sse.ucomile.ss(<4 x float>, <4 x float>) nounwind readnone
 
 
 define i32 @test_x86_sse_ucomilt_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vucomiss
-  ; CHECK: sbbl
+; CHECK-LABEL: test_x86_sse_ucomilt_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vucomiss %xmm1, %xmm0
+; CHECK-NEXT:    sbbl %eax, %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1623,9 +2130,12 @@ declare i32 @llvm.x86.sse.ucomilt.ss(<4 x float>, <4 x float>) nounwind readnone
 
 
 define i32 @test_x86_sse_ucomineq_ss(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vucomiss
-  ; CHECK: setne
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_sse_ucomineq_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vucomiss %xmm1, %xmm0
+; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -1633,7 +2143,10 @@ declare i32 @llvm.x86.sse.ucomineq.ss(<4 x float>, <4 x float>) nounwind readnon
 
 
 define <16 x i8> @test_x86_ssse3_pabs_b_128(<16 x i8> %a0) {
-  ; CHECK: vpabsb
+; CHECK-LABEL: test_x86_ssse3_pabs_b_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpabsb %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %a0) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -1641,7 +2154,10 @@ declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone
 
 
 define <4 x i32> @test_x86_ssse3_pabs_d_128(<4 x i32> %a0) {
-  ; CHECK: vpabsd
+; CHECK-LABEL: test_x86_ssse3_pabs_d_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpabsd %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> %a0) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -1649,7 +2165,10 @@ declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone
 
 
 define <8 x i16> @test_x86_ssse3_pabs_w_128(<8 x i16> %a0) {
-  ; CHECK: vpabsw
+; CHECK-LABEL: test_x86_ssse3_pabs_w_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpabsw %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %a0) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -1657,7 +2176,10 @@ declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone
 
 
 define <4 x i32> @test_x86_ssse3_phadd_d_128(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vphaddd
+; CHECK-LABEL: test_x86_ssse3_phadd_d_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphaddd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -1665,7 +2187,10 @@ declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>) nounwind rea
 
 
 define <8 x i16> @test_x86_ssse3_phadd_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vphaddsw
+; CHECK-LABEL: test_x86_ssse3_phadd_sw_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphaddsw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -1673,7 +2198,10 @@ declare <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16>, <8 x i16>) nounwind re
 
 
 define <8 x i16> @test_x86_ssse3_phadd_w_128(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vphaddw
+; CHECK-LABEL: test_x86_ssse3_phadd_w_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphaddw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -1681,7 +2209,10 @@ declare <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16>, <8 x i16>) nounwind rea
 
 
 define <4 x i32> @test_x86_ssse3_phsub_d_128(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vphsubd
+; CHECK-LABEL: test_x86_ssse3_phsub_d_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphsubd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -1689,7 +2220,10 @@ declare <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32>, <4 x i32>) nounwind rea
 
 
 define <8 x i16> @test_x86_ssse3_phsub_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vphsubsw
+; CHECK-LABEL: test_x86_ssse3_phsub_sw_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphsubsw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -1697,7 +2231,10 @@ declare <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16>, <8 x i16>) nounwind re
 
 
 define <8 x i16> @test_x86_ssse3_phsub_w_128(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vphsubw
+; CHECK-LABEL: test_x86_ssse3_phsub_w_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphsubw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -1705,7 +2242,10 @@ declare <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16>, <8 x i16>) nounwind rea
 
 
 define <8 x i16> @test_x86_ssse3_pmadd_ub_sw_128(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpmaddubsw
+; CHECK-LABEL: test_x86_ssse3_pmadd_ub_sw_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmaddubsw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8> %a0, <16 x i8> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -1713,7 +2253,10 @@ declare <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8>, <16 x i8>) nounwind
 
 
 define <8 x i16> @test_x86_ssse3_pmul_hr_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpmulhrsw
+; CHECK-LABEL: test_x86_ssse3_pmul_hr_sw_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmulhrsw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -1721,7 +2264,10 @@ declare <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16>, <8 x i16>) nounwind
 
 
 define <16 x i8> @test_x86_ssse3_pshuf_b_128(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpshufb
+; CHECK-LABEL: test_x86_ssse3_pshuf_b_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpshufb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -1729,7 +2275,10 @@ declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) nounwind rea
 
 
 define <16 x i8> @test_x86_ssse3_psign_b_128(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpsignb
+; CHECK-LABEL: test_x86_ssse3_psign_b_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsignb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -1737,7 +2286,10 @@ declare <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8>, <16 x i8>) nounwind rea
 
 
 define <4 x i32> @test_x86_ssse3_psign_d_128(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpsignd
+; CHECK-LABEL: test_x86_ssse3_psign_d_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsignd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -1745,7 +2297,10 @@ declare <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32>, <4 x i32>) nounwind rea
 
 
 define <8 x i16> @test_x86_ssse3_psign_w_128(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpsignw
+; CHECK-LABEL: test_x86_ssse3_psign_w_128:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsignw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
@@ -1753,7 +2308,10 @@ declare <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16>, <8 x i16>) nounwind rea
 
 
 define <4 x double> @test_x86_avx_addsub_pd_256(<4 x double> %a0, <4 x double> %a1) {
-  ; CHECK: vaddsubpd
+; CHECK-LABEL: test_x86_avx_addsub_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vaddsubpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -1761,31 +2319,21 @@ declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>) nou
 
 
 define <8 x float> @test_x86_avx_addsub_ps_256(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vaddsubps
+; CHECK-LABEL: test_x86_avx_addsub_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vaddsubps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
 declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
 
 
-define <4 x double> @test_x86_avx_blend_pd_256(<4 x double> %a0, <4 x double> %a1) {
-  ; CHECK: vblendpd
-  %res = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a1, i8 7) ; <<4 x double>> [#uses=1]
-  ret <4 x double> %res
-}
-declare <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone
-
-
-define <8 x float> @test_x86_avx_blend_ps_256(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vblendps
-  %res = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1]
-  ret <8 x float> %res
-}
-declare <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone
-
-
 define <4 x double> @test_x86_avx_blendv_pd_256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) {
-  ; CHECK: vblendvpd
+; CHECK-LABEL: test_x86_avx_blendv_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vblendvpd %ymm2, %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -1793,7 +2341,10 @@ declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4
 
 
 define <8 x float> @test_x86_avx_blendv_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) {
-  ; CHECK: vblendvps
+; CHECK-LABEL: test_x86_avx_blendv_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vblendvps %ymm2, %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -1801,7 +2352,10 @@ declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x f
 
 
 define <4 x double> @test_x86_avx_cmp_pd_256(<4 x double> %a0, <4 x double> %a1) {
-  ; CHECK: vcmpordpd
+; CHECK-LABEL: test_x86_avx_cmp_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcmpordpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> %a0, <4 x double> %a1, i8 7) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -1809,75 +2363,81 @@ declare <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double>, <4 x double>, i8) no
 
 
 define <8 x float> @test_x86_avx_cmp_ps_256(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vcmpordps
+; CHECK-LABEL: test_x86_avx_cmp_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcmpordps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
 
 define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vcmpeqps
+; CHECK-LABEL: test_x86_avx_cmp_ps_256_pseudo_op:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcmpeqps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpltps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpleps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpunordps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpneqps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpnltps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpnleps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpordps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpeq_uqps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpngeps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpngtps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpfalseps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpneq_oqps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpgeps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpgtps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmptrueps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpeq_osps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmplt_oqps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmple_oqps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpunord_sps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpneq_usps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpnlt_uqps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpnle_uqps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpord_sps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpeq_usps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpnge_uqps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpngt_uqps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpfalse_osps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpneq_osps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpge_oqps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmpgt_oqps %ymm1, %ymm0, %ymm1
+; CHECK-NEXT:    vcmptrue_usps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %a2 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 0) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpltps
   %a3 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a2, i8 1) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpleps
   %a4 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a3, i8 2) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpunordps
   %a5 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a4, i8 3) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpneqps
   %a6 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a5, i8 4) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpnltps
   %a7 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a6, i8 5) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpnleps
   %a8 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a7, i8 6) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpordps
   %a9 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a8, i8 7) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpeq_uqps
   %a10 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a9, i8 8) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpngeps
   %a11 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a10, i8 9) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpngtps
   %a12 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a11, i8 10) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpfalseps
   %a13 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a12, i8 11) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpneq_oqps
   %a14 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a13, i8 12) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpgeps
   %a15 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a14, i8 13) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpgtps
   %a16 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a15, i8 14) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmptrueps
   %a17 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a16, i8 15) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpeq_osps
   %a18 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a17, i8 16) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmplt_oqps
   %a19 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a18, i8 17) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmple_oqps
   %a20 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a19, i8 18) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpunord_sps
   %a21 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a20, i8 19) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpneq_usps
   %a22 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a21, i8 20) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpnlt_uqps
   %a23 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a22, i8 21) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpnle_uqps
   %a24 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a23, i8 22) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpord_sps
   %a25 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a24, i8 23) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpeq_usps
   %a26 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a25, i8 24) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpnge_uqps
   %a27 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a26, i8 25) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpngt_uqps
   %a28 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a27, i8 26) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpfalse_osps
   %a29 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a28, i8 27) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpneq_osps
   %a30 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a29, i8 28) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpge_oqps
   %a31 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a30, i8 29) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmpgt_oqps
   %a32 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a31, i8 30) ; <<8 x float>> [#uses=1]
-  ; CHECK: vcmptrue_usps
   %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a32, i8 31) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -1885,7 +2445,11 @@ declare <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float>, <8 x float>, i8) nounw
 
 
 define <4 x float> @test_x86_avx_cvt_pd2_ps_256(<4 x double> %a0) {
-  ; CHECK: vcvtpd2psy
+; CHECK-LABEL: test_x86_avx_cvt_pd2_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtpd2psy %ymm0, %xmm0
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.avx.cvt.pd2.ps.256(<4 x double> %a0) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -1893,7 +2457,11 @@ declare <4 x float> @llvm.x86.avx.cvt.pd2.ps.256(<4 x double>) nounwind readnone
 
 
 define <4 x i32> @test_x86_avx_cvt_pd2dq_256(<4 x double> %a0) {
-  ; CHECK: vcvtpd2dqy
+; CHECK-LABEL: test_x86_avx_cvt_pd2dq_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtpd2dqy %ymm0, %xmm0
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double> %a0) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -1901,7 +2469,10 @@ declare <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double>) nounwind readnone
 
 
 define <4 x double> @test_x86_avx_cvt_ps2_pd_256(<4 x float> %a0) {
-  ; CHECK: vcvtps2pd
+; CHECK-LABEL: test_x86_avx_cvt_ps2_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtps2pd %xmm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.cvt.ps2.pd.256(<4 x float> %a0) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -1909,7 +2480,10 @@ declare <4 x double> @llvm.x86.avx.cvt.ps2.pd.256(<4 x float>) nounwind readnone
 
 
 define <8 x i32> @test_x86_avx_cvt_ps2dq_256(<8 x float> %a0) {
-  ; CHECK: vcvtps2dq
+; CHECK-LABEL: test_x86_avx_cvt_ps2dq_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtps2dq %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1]
   ret <8 x i32> %res
 }
@@ -1917,7 +2491,10 @@ declare <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float>) nounwind readnone
 
 
 define <4 x double> @test_x86_avx_cvtdq2_pd_256(<4 x i32> %a0) {
-  ; CHECK: vcvtdq2pd
+; CHECK-LABEL: test_x86_avx_cvtdq2_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtdq2pd %xmm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32> %a0) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -1925,7 +2502,10 @@ declare <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32>) nounwind readnone
 
 
 define <8 x float> @test_x86_avx_cvtdq2_ps_256(<8 x i32> %a0) {
-  ; CHECK: vcvtdq2ps
+; CHECK-LABEL: test_x86_avx_cvtdq2_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32> %a0) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -1933,7 +2513,11 @@ declare <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32>) nounwind readnone
 
 
 define <4 x i32> @test_x86_avx_cvtt_pd2dq_256(<4 x double> %a0) {
-  ; CHECK: vcvttpd2dqy
+; CHECK-LABEL: test_x86_avx_cvtt_pd2dq_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvttpd2dqy %ymm0, %xmm0
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %res = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %a0) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %res
 }
@@ -1941,7 +2525,10 @@ declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) nounwind readnone
 
 
 define <8 x i32> @test_x86_avx_cvtt_ps2dq_256(<8 x float> %a0) {
-  ; CHECK: vcvttps2dq
+; CHECK-LABEL: test_x86_avx_cvtt_ps2dq_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcvttps2dq %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1]
   ret <8 x i32> %res
 }
@@ -1949,7 +2536,10 @@ declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) nounwind readnone
 
 
 define <8 x float> @test_x86_avx_dp_ps_256(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vdpps
+; CHECK-LABEL: test_x86_avx_dp_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vdpps $7, %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -1957,7 +2547,10 @@ declare <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float>, <8 x float>, i8) nounwi
 
 
 define <4 x double> @test_x86_avx_hadd_pd_256(<4 x double> %a0, <4 x double> %a1) {
-  ; CHECK: vhaddpd
+; CHECK-LABEL: test_x86_avx_hadd_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vhaddpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -1965,7 +2558,10 @@ declare <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double>, <4 x double>) nounw
 
 
 define <8 x float> @test_x86_avx_hadd_ps_256(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vhaddps
+; CHECK-LABEL: test_x86_avx_hadd_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vhaddps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -1973,7 +2569,10 @@ declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>) nounwind
 
 
 define <4 x double> @test_x86_avx_hsub_pd_256(<4 x double> %a0, <4 x double> %a1) {
-  ; CHECK: vhsubpd
+; CHECK-LABEL: test_x86_avx_hsub_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vhsubpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -1981,7 +2580,10 @@ declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>) nounw
 
 
 define <8 x float> @test_x86_avx_hsub_ps_256(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vhsubps
+; CHECK-LABEL: test_x86_avx_hsub_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vhsubps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -1989,7 +2591,11 @@ declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) nounwind
 
 
 define <32 x i8> @test_x86_avx_ldu_dq_256(i8* %a0) {
-  ; CHECK: vlddqu
+; CHECK-LABEL: test_x86_avx_ldu_dq_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vlddqu (%eax), %ymm0
+; CHECK-NEXT:    retl
   %res = call <32 x i8> @llvm.x86.avx.ldu.dq.256(i8* %a0) ; <<32 x i8>> [#uses=1]
   ret <32 x i8> %res
 }
@@ -1997,7 +2603,11 @@ declare <32 x i8> @llvm.x86.avx.ldu.dq.256(i8*) nounwind readonly
 
 
 define <2 x double> @test_x86_avx_maskload_pd(i8* %a0, <2 x double> %a1) {
-  ; CHECK: vmaskmovpd
+; CHECK-LABEL: test_x86_avx_maskload_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vmaskmovpd (%eax), %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.avx.maskload.pd(i8* %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -2005,7 +2615,11 @@ declare <2 x double> @llvm.x86.avx.maskload.pd(i8*, <2 x double>) nounwind reado
 
 
 define <4 x double> @test_x86_avx_maskload_pd_256(i8* %a0, <4 x double> %a1) {
-  ; CHECK: vmaskmovpd
+; CHECK-LABEL: test_x86_avx_maskload_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vmaskmovpd (%eax), %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8* %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -2013,7 +2627,11 @@ declare <4 x double> @llvm.x86.avx.maskload.pd.256(i8*, <4 x double>) nounwind r
 
 
 define <4 x float> @test_x86_avx_maskload_ps(i8* %a0, <4 x float> %a1) {
-  ; CHECK: vmaskmovps
+; CHECK-LABEL: test_x86_avx_maskload_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vmaskmovps (%eax), %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.avx.maskload.ps(i8* %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -2021,7 +2639,11 @@ declare <4 x float> @llvm.x86.avx.maskload.ps(i8*, <4 x float>) nounwind readonl
 
 
 define <8 x float> @test_x86_avx_maskload_ps_256(i8* %a0, <8 x float> %a1) {
-  ; CHECK: vmaskmovps
+; CHECK-LABEL: test_x86_avx_maskload_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vmaskmovps (%eax), %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.maskload.ps.256(i8* %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -2029,7 +2651,11 @@ declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8*, <8 x float>) nounwind rea
 
 
 define void @test_x86_avx_maskstore_pd(i8* %a0, <2 x double> %a1, <2 x double> %a2) {
-  ; CHECK: vmaskmovpd
+; CHECK-LABEL: test_x86_avx_maskstore_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vmaskmovpd %xmm1, %xmm0, (%eax)
+; CHECK-NEXT:    retl
   call void @llvm.x86.avx.maskstore.pd(i8* %a0, <2 x double> %a1, <2 x double> %a2)
   ret void
 }
@@ -2037,7 +2663,12 @@ declare void @llvm.x86.avx.maskstore.pd(i8*, <2 x double>, <2 x double>) nounwin
 
 
 define void @test_x86_avx_maskstore_pd_256(i8* %a0, <4 x double> %a1, <4 x double> %a2) {
-  ; CHECK: vmaskmovpd
+; CHECK-LABEL: test_x86_avx_maskstore_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vmaskmovpd %ymm1, %ymm0, (%eax)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   call void @llvm.x86.avx.maskstore.pd.256(i8* %a0, <4 x double> %a1, <4 x double> %a2)
   ret void
 }
@@ -2045,7 +2676,11 @@ declare void @llvm.x86.avx.maskstore.pd.256(i8*, <4 x double>, <4 x double>) nou
 
 
 define void @test_x86_avx_maskstore_ps(i8* %a0, <4 x float> %a1, <4 x float> %a2) {
-  ; CHECK: vmaskmovps
+; CHECK-LABEL: test_x86_avx_maskstore_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vmaskmovps %xmm1, %xmm0, (%eax)
+; CHECK-NEXT:    retl
   call void @llvm.x86.avx.maskstore.ps(i8* %a0, <4 x float> %a1, <4 x float> %a2)
   ret void
 }
@@ -2053,7 +2688,12 @@ declare void @llvm.x86.avx.maskstore.ps(i8*, <4 x float>, <4 x float>) nounwind
 
 
 define void @test_x86_avx_maskstore_ps_256(i8* %a0, <8 x float> %a1, <8 x float> %a2) {
-  ; CHECK: vmaskmovps
+; CHECK-LABEL: test_x86_avx_maskstore_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vmaskmovps %ymm1, %ymm0, (%eax)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   call void @llvm.x86.avx.maskstore.ps.256(i8* %a0, <8 x float> %a1, <8 x float> %a2)
   ret void
 }
@@ -2061,7 +2701,10 @@ declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x float>, <8 x float>) nounw
 
 
 define <4 x double> @test_x86_avx_max_pd_256(<4 x double> %a0, <4 x double> %a1) {
-  ; CHECK: vmaxpd
+; CHECK-LABEL: test_x86_avx_max_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmaxpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.max.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -2069,7 +2712,10 @@ declare <4 x double> @llvm.x86.avx.max.pd.256(<4 x double>, <4 x double>) nounwi
 
 
 define <8 x float> @test_x86_avx_max_ps_256(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vmaxps
+; CHECK-LABEL: test_x86_avx_max_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmaxps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.max.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -2077,7 +2723,10 @@ declare <8 x float> @llvm.x86.avx.max.ps.256(<8 x float>, <8 x float>) nounwind
 
 
 define <4 x double> @test_x86_avx_min_pd_256(<4 x double> %a0, <4 x double> %a1) {
-  ; CHECK: vminpd
+; CHECK-LABEL: test_x86_avx_min_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vminpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.min.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -2085,7 +2734,10 @@ declare <4 x double> @llvm.x86.avx.min.pd.256(<4 x double>, <4 x double>) nounwi
 
 
 define <8 x float> @test_x86_avx_min_ps_256(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vminps
+; CHECK-LABEL: test_x86_avx_min_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vminps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -2093,7 +2745,11 @@ declare <8 x float> @llvm.x86.avx.min.ps.256(<8 x float>, <8 x float>) nounwind
 
 
 define i32 @test_x86_avx_movmsk_pd_256(<4 x double> %a0) {
-  ; CHECK: vmovmskpd
+; CHECK-LABEL: test_x86_avx_movmsk_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmovmskpd %ymm0, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %a0) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2101,7 +2757,11 @@ declare i32 @llvm.x86.avx.movmsk.pd.256(<4 x double>) nounwind readnone
 
 
 define i32 @test_x86_avx_movmsk_ps_256(<8 x float> %a0) {
-  ; CHECK: vmovmskps
+; CHECK-LABEL: test_x86_avx_movmsk_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmovmskps %ymm0, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %a0) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2114,8 +2774,13 @@ declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) nounwind readnone
 
 
 define i32 @test_x86_avx_ptestc_256(<4 x i64> %a0, <4 x i64> %a1) {
-  ; CHECK: vptest
-  ; CHECK: sbbl
+; CHECK-LABEL: test_x86_avx_ptestc_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vptest %ymm1, %ymm0
+; CHECK-NEXT:    sbbl %eax, %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2123,9 +2788,13 @@ declare i32 @llvm.x86.avx.ptestc.256(<4 x i64>, <4 x i64>) nounwind readnone
 
 
 define i32 @test_x86_avx_ptestnzc_256(<4 x i64> %a0, <4 x i64> %a1) {
-  ; CHECK: vptest
-  ; CHECK: seta
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_avx_ptestnzc_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vptest %ymm1, %ymm0
+; CHECK-NEXT:    seta %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2133,9 +2802,13 @@ declare i32 @llvm.x86.avx.ptestnzc.256(<4 x i64>, <4 x i64>) nounwind readnone
 
 
 define i32 @test_x86_avx_ptestz_256(<4 x i64> %a0, <4 x i64> %a1) {
-  ; CHECK: vptest
-  ; CHECK: sete
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_avx_ptestz_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vptest %ymm1, %ymm0
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2143,7 +2816,10 @@ declare i32 @llvm.x86.avx.ptestz.256(<4 x i64>, <4 x i64>) nounwind readnone
 
 
 define <8 x float> @test_x86_avx_rcp_ps_256(<8 x float> %a0) {
-  ; CHECK: vrcpps
+; CHECK-LABEL: test_x86_avx_rcp_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vrcpps %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -2151,7 +2827,10 @@ declare <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float>) nounwind readnone
 
 
 define <4 x double> @test_x86_avx_round_pd_256(<4 x double> %a0) {
-  ; CHECK: vroundpd
+; CHECK-LABEL: test_x86_avx_round_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vroundpd $7, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.round.pd.256(<4 x double> %a0, i32 7) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -2159,7 +2838,10 @@ declare <4 x double> @llvm.x86.avx.round.pd.256(<4 x double>, i32) nounwind read
 
 
 define <8 x float> @test_x86_avx_round_ps_256(<8 x float> %a0) {
-  ; CHECK: vroundps
+; CHECK-LABEL: test_x86_avx_round_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vroundps $7, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.round.ps.256(<8 x float> %a0, i32 7) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -2167,7 +2849,10 @@ declare <8 x float> @llvm.x86.avx.round.ps.256(<8 x float>, i32) nounwind readno
 
 
 define <8 x float> @test_x86_avx_rsqrt_ps_256(<8 x float> %a0) {
-  ; CHECK: vrsqrtps
+; CHECK-LABEL: test_x86_avx_rsqrt_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vrsqrtps %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -2175,7 +2860,10 @@ declare <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float>) nounwind readnone
 
 
 define <4 x double> @test_x86_avx_sqrt_pd_256(<4 x double> %a0) {
-  ; CHECK: vsqrtpd
+; CHECK-LABEL: test_x86_avx_sqrt_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vsqrtpd %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double> %a0) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -2183,7 +2871,10 @@ declare <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double>) nounwind readnone
 
 
 define <8 x float> @test_x86_avx_sqrt_ps_256(<8 x float> %a0) {
-  ; CHECK: vsqrtps
+; CHECK-LABEL: test_x86_avx_sqrt_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vsqrtps %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -2192,8 +2883,18 @@ declare <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float>) nounwind readnone
 
 define void @test_x86_avx_storeu_dq_256(i8* %a0, <32 x i8> %a1) {
   ; FIXME: unfortunately the execution domain fix pass changes this to vmovups and its hard to force with no 256-bit integer instructions
-  ; CHECK: vmovups
   ; add operation forces the execution domain.
+; CHECK-LABEL: test_x86_avx_storeu_dq_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT:    vmovdqa {{.*#+}} xmm2 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
+; CHECK-NEXT:    vpaddb %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vpaddb %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    vmovups %ymm0, (%eax)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %a2 = add <32 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   call void @llvm.x86.avx.storeu.dq.256(i8* %a0, <32 x i8> %a2)
   ret void
@@ -2202,8 +2903,15 @@ declare void @llvm.x86.avx.storeu.dq.256(i8*, <32 x i8>) nounwind
 
 
 define void @test_x86_avx_storeu_pd_256(i8* %a0, <4 x double> %a1) {
-  ; CHECK: vmovupd
   ; add operation forces the execution domain.
+; CHECK-LABEL: test_x86_avx_storeu_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
+; CHECK-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    vmovupd %ymm0, (%eax)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %a2 = fadd <4 x double> %a1, <double 0x0, double 0x0, double 0x0, double 0x0>
   call void @llvm.x86.avx.storeu.pd.256(i8* %a0, <4 x double> %a2)
   ret void
@@ -2212,7 +2920,12 @@ declare void @llvm.x86.avx.storeu.pd.256(i8*, <4 x double>) nounwind
 
 
 define void @test_x86_avx_storeu_ps_256(i8* %a0, <8 x float> %a1) {
-  ; CHECK: vmovups
+; CHECK-LABEL: test_x86_avx_storeu_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vmovups %ymm0, (%eax)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   call void @llvm.x86.avx.storeu.ps.256(i8* %a0, <8 x float> %a1)
   ret void
 }
@@ -2220,7 +2933,11 @@ declare void @llvm.x86.avx.storeu.ps.256(i8*, <8 x float>) nounwind
 
 
 define <4 x double> @test_x86_avx_vbroadcastf128_pd_256(i8* %a0) {
-  ; CHECK: vbroadcastf128
+; CHECK-LABEL: test_x86_avx_vbroadcastf128_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vbroadcastf128 (%eax), %ymm0
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.vbroadcastf128.pd.256(i8* %a0) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -2228,63 +2945,22 @@ declare <4 x double> @llvm.x86.avx.vbroadcastf128.pd.256(i8*) nounwind readonly
 
 
 define <8 x float> @test_x86_avx_vbroadcastf128_ps_256(i8* %a0) {
-  ; CHECK: vbroadcastf128
+; CHECK-LABEL: test_x86_avx_vbroadcastf128_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vbroadcastf128 (%eax), %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.vbroadcastf128.ps.256(i8* %a0) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
 declare <8 x float> @llvm.x86.avx.vbroadcastf128.ps.256(i8*) nounwind readonly
 
 
-define <2 x double> @test_x86_avx_vextractf128_pd_256(<4 x double> %a0) {
-  ; CHECK: vextractf128
-  %res = call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a0, i8 7) ; <<2 x double>> [#uses=1]
-  ret <2 x double> %res
-}
-declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone
-
-
-define <4 x float> @test_x86_avx_vextractf128_ps_256(<8 x float> %a0) {
-  ; CHECK: vextractf128
-  %res = call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a0, i8 7) ; <<4 x float>> [#uses=1]
-  ret <4 x float> %res
-}
-declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone
-
-
-define <4 x i32> @test_x86_avx_vextractf128_si_256(<8 x i32> %a0) {
-  ; CHECK: vextractf128
-  %res = call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %a0, i8 7) ; <<4 x i32>> [#uses=1]
-  ret <4 x i32> %res
-}
-declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind readnone
-
-
-define <4 x double> @test_x86_avx_vinsertf128_pd_256(<4 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vinsertf128
-  %res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> %a0, <2 x double> %a1, i8 7) ; <<4 x double>> [#uses=1]
-  ret <4 x double> %res
-}
-declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double>, i8) nounwind readnone
-
-
-define <8 x float> @test_x86_avx_vinsertf128_ps_256(<8 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vinsertf128
-  %res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %a0, <4 x float> %a1, i8 7) ; <<8 x float>> [#uses=1]
-  ret <8 x float> %res
-}
-declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i8) nounwind readnone
-
-
-define <8 x i32> @test_x86_avx_vinsertf128_si_256(<8 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vinsertf128
-  %res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> %a0, <4 x i32> %a1, i8 7) ; <<8 x i32>> [#uses=1]
-  ret <8 x i32> %res
-}
-declare <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32>, <4 x i32>, i8) nounwind readnone
-
-
 define <4 x double> @test_x86_avx_vperm2f128_pd_256(<4 x double> %a0, <4 x double> %a1) {
-  ; CHECK: vperm2f128
+; CHECK-LABEL: test_x86_avx_vperm2f128_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[0,1]
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 7) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -2292,7 +2968,10 @@ declare <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double>, <4 x double>,
 
 
 define <8 x float> @test_x86_avx_vperm2f128_ps_256(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vperm2f128
+; CHECK-LABEL: test_x86_avx_vperm2f128_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[0,1]
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -2300,7 +2979,10 @@ declare <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float>, <8 x float>, i8
 
 
 define <8 x i32> @test_x86_avx_vperm2f128_si_256(<8 x i32> %a0, <8 x i32> %a1) {
-  ; CHECK: vperm2f128
+; CHECK-LABEL: test_x86_avx_vperm2f128_si_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[0,1]
+; CHECK-NEXT:    retl
   %res = call <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32> %a0, <8 x i32> %a1, i8 7) ; <<8 x i32>> [#uses=1]
   ret <8 x i32> %res
 }
@@ -2308,7 +2990,10 @@ declare <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32>, <8 x i32>, i8) noun
 
 
 define <2 x double> @test_x86_avx_vpermil_pd(<2 x double> %a0) {
-  ; CHECK: vpermilpd
+; CHECK-LABEL: test_x86_avx_vpermil_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.avx.vpermil.pd(<2 x double> %a0, i8 1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -2316,7 +3001,10 @@ declare <2 x double> @llvm.x86.avx.vpermil.pd(<2 x double>, i8) nounwind readnon
 
 
 define <4 x double> @test_x86_avx_vpermil_pd_256(<4 x double> %a0) {
-  ; CHECK: vpermilpd
+; CHECK-LABEL: test_x86_avx_vpermil_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[1,1,3,2]
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double> %a0, i8 7) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -2324,7 +3012,10 @@ declare <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double>, i8) nounwind rea
 
 
 define <4 x float> @test_x86_avx_vpermil_ps(<4 x float> %a0) {
-  ; CHECK: vpermilps
+; CHECK-LABEL: test_x86_avx_vpermil_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[3,1,0,0]
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float> %a0, i8 7) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -2332,7 +3023,10 @@ declare <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float>, i8) nounwind readnone
 
 
 define <8 x float> @test_x86_avx_vpermil_ps_256(<8 x float> %a0) {
-  ; CHECK: vpermilps
+; CHECK-LABEL: test_x86_avx_vpermil_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[3,1,0,0,7,5,4,4]
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.vpermil.ps.256(<8 x float> %a0, i8 7) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -2340,7 +3034,10 @@ declare <8 x float> @llvm.x86.avx.vpermil.ps.256(<8 x float>, i8) nounwind readn
 
 
 define <2 x double> @test_x86_avx_vpermilvar_pd(<2 x double> %a0, <2 x i64> %a1) {
-  ; CHECK: vpermilpd
+; CHECK-LABEL: test_x86_avx_vpermilvar_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermilpd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> %a1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -2348,7 +3045,10 @@ declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i64>) nounwi
 
 
 define <4 x double> @test_x86_avx_vpermilvar_pd_256(<4 x double> %a0, <4 x i64> %a1) {
-  ; CHECK: vpermilpd
+; CHECK-LABEL: test_x86_avx_vpermilvar_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermilpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> %a1) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -2356,13 +3056,20 @@ declare <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double>, <4 x i64>) no
 
 
 define <4 x float> @test_x86_avx_vpermilvar_ps(<4 x float> %a0, <4 x i32> %a1) {
-  ; CHECK: vpermilps
+; CHECK-LABEL: test_x86_avx_vpermilvar_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermilps %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
 define <4 x float> @test_x86_avx_vpermilvar_ps_load(<4 x float> %a0, <4 x i32>* %a1) {
-  ; CHECK: vpermilps
-  %a2 = load <4 x i32>* %a1
+; CHECK-LABEL: test_x86_avx_vpermilvar_ps_load:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vpermilps (%eax), %xmm0, %xmm0
+; CHECK-NEXT:    retl
+  %a2 = load <4 x i32>, <4 x i32>* %a1
   %res = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %a2) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -2370,7 +3077,10 @@ declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>) nounwind
 
 
 define <8 x float> @test_x86_avx_vpermilvar_ps_256(<8 x float> %a0, <8 x i32> %a1) {
-  ; CHECK: vpermilps
+; CHECK-LABEL: test_x86_avx_vpermilvar_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermilps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
   %res = call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> %a1) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
@@ -2378,8 +3088,12 @@ declare <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float>, <8 x i32>) noun
 
 
 define i32 @test_x86_avx_vtestc_pd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vtestpd
-  ; CHECK: sbbl
+; CHECK-LABEL: test_x86_avx_vtestc_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vtestpd %xmm1, %xmm0
+; CHECK-NEXT:    sbbl %eax, %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.vtestc.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2387,8 +3101,13 @@ declare i32 @llvm.x86.avx.vtestc.pd(<2 x double>, <2 x double>) nounwind readnon
 
 
 define i32 @test_x86_avx_vtestc_pd_256(<4 x double> %a0, <4 x double> %a1) {
-  ; CHECK: vtestpd
-  ; CHECK: sbbl
+; CHECK-LABEL: test_x86_avx_vtestc_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vtestpd %ymm1, %ymm0
+; CHECK-NEXT:    sbbl %eax, %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.vtestc.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2396,8 +3115,12 @@ declare i32 @llvm.x86.avx.vtestc.pd.256(<4 x double>, <4 x double>) nounwind rea
 
 
 define i32 @test_x86_avx_vtestc_ps(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vtestps
-  ; CHECK: sbbl
+; CHECK-LABEL: test_x86_avx_vtestc_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vtestps %xmm1, %xmm0
+; CHECK-NEXT:    sbbl %eax, %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.vtestc.ps(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2405,8 +3128,13 @@ declare i32 @llvm.x86.avx.vtestc.ps(<4 x float>, <4 x float>) nounwind readnone
 
 
 define i32 @test_x86_avx_vtestc_ps_256(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vtestps
-  ; CHECK: sbbl
+; CHECK-LABEL: test_x86_avx_vtestc_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vtestps %ymm1, %ymm0
+; CHECK-NEXT:    sbbl %eax, %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.vtestc.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2414,9 +3142,12 @@ declare i32 @llvm.x86.avx.vtestc.ps.256(<8 x float>, <8 x float>) nounwind readn
 
 
 define i32 @test_x86_avx_vtestnzc_pd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vtestpd
-  ; CHECK: seta
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_avx_vtestnzc_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vtestpd %xmm1, %xmm0
+; CHECK-NEXT:    seta %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2424,9 +3155,13 @@ declare i32 @llvm.x86.avx.vtestnzc.pd(<2 x double>, <2 x double>) nounwind readn
 
 
 define i32 @test_x86_avx_vtestnzc_pd_256(<4 x double> %a0, <4 x double> %a1) {
-  ; CHECK: vtestpd
-  ; CHECK: seta
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_avx_vtestnzc_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vtestpd %ymm1, %ymm0
+; CHECK-NEXT:    seta %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2434,9 +3169,12 @@ declare i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double>, <4 x double>) nounwind r
 
 
 define i32 @test_x86_avx_vtestnzc_ps(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vtestps
-  ; CHECK: seta
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_avx_vtestnzc_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vtestps %xmm1, %xmm0
+; CHECK-NEXT:    seta %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.vtestnzc.ps(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2444,9 +3182,13 @@ declare i32 @llvm.x86.avx.vtestnzc.ps(<4 x float>, <4 x float>) nounwind readnon
 
 
 define i32 @test_x86_avx_vtestnzc_ps_256(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vtestps
-  ; CHECK: seta
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_avx_vtestnzc_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vtestps %ymm1, %ymm0
+; CHECK-NEXT:    seta %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2454,9 +3196,12 @@ declare i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float>, <8 x float>) nounwind rea
 
 
 define i32 @test_x86_avx_vtestz_pd(<2 x double> %a0, <2 x double> %a1) {
-  ; CHECK: vtestpd
-  ; CHECK: sete
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_avx_vtestz_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vtestpd %xmm1, %xmm0
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2464,9 +3209,13 @@ declare i32 @llvm.x86.avx.vtestz.pd(<2 x double>, <2 x double>) nounwind readnon
 
 
 define i32 @test_x86_avx_vtestz_pd_256(<4 x double> %a0, <4 x double> %a1) {
-  ; CHECK: vtestpd
-  ; CHECK: sete
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_avx_vtestz_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vtestpd %ymm1, %ymm0
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2474,9 +3223,12 @@ declare i32 @llvm.x86.avx.vtestz.pd.256(<4 x double>, <4 x double>) nounwind rea
 
 
 define i32 @test_x86_avx_vtestz_ps(<4 x float> %a0, <4 x float> %a1) {
-  ; CHECK: vtestps
-  ; CHECK: sete
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_avx_vtestz_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vtestps %xmm1, %xmm0
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.vtestz.ps(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2484,9 +3236,13 @@ declare i32 @llvm.x86.avx.vtestz.ps(<4 x float>, <4 x float>) nounwind readnone
 
 
 define i32 @test_x86_avx_vtestz_ps_256(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vtestps
-  ; CHECK: sete
-  ; CHECK: movzbl
+; CHECK-LABEL: test_x86_avx_vtestz_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vtestps %ymm1, %ymm0
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %res = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -2494,7 +3250,11 @@ declare i32 @llvm.x86.avx.vtestz.ps.256(<8 x float>, <8 x float>) nounwind readn
 
 
 define void @test_x86_avx_vzeroall() {
-  ; CHECK: vzeroall
+; CHECK-LABEL: test_x86_avx_vzeroall:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vzeroall
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   call void @llvm.x86.avx.vzeroall()
   ret void
 }
@@ -2502,7 +3262,11 @@ declare void @llvm.x86.avx.vzeroall() nounwind
 
 
 define void @test_x86_avx_vzeroupper() {
-  ; CHECK: vzeroupper
+; CHECK-LABEL: test_x86_avx_vzeroupper:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   call void @llvm.x86.avx.vzeroupper()
   ret void
 }
@@ -2510,93 +3274,143 @@ declare void @llvm.x86.avx.vzeroupper() nounwind
 
 ; Make sure instructions with no AVX equivalents, but are associated with SSEX feature flags still work
 
-; CHECK: monitor
 define void @monitor(i8* %P, i32 %E, i32 %H) nounwind {
-entry:
+; CHECK-LABEL: monitor:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    leal (%eax), %eax
+; CHECK-NEXT:    monitor
+; CHECK-NEXT:    retl
   tail call void @llvm.x86.sse3.monitor(i8* %P, i32 %E, i32 %H)
   ret void
 }
 declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind
 
-; CHECK: mwait
 define void @mwait(i32 %E, i32 %H) nounwind {
-entry:
+; CHECK-LABEL: mwait:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    mwait
+; CHECK-NEXT:    retl
   tail call void @llvm.x86.sse3.mwait(i32 %E, i32 %H)
   ret void
 }
 declare void @llvm.x86.sse3.mwait(i32, i32) nounwind
 
-; CHECK: sfence
 define void @sfence() nounwind {
-entry:
+; CHECK-LABEL: sfence:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    sfence
+; CHECK-NEXT:    retl
   tail call void @llvm.x86.sse.sfence()
   ret void
 }
 declare void @llvm.x86.sse.sfence() nounwind
 
-; CHECK: lfence
 define void @lfence() nounwind {
-entry:
+; CHECK-LABEL: lfence:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    lfence
+; CHECK-NEXT:    retl
   tail call void @llvm.x86.sse2.lfence()
   ret void
 }
 declare void @llvm.x86.sse2.lfence() nounwind
 
-; CHECK: mfence
 define void @mfence() nounwind {
-entry:
+; CHECK-LABEL: mfence:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    mfence
+; CHECK-NEXT:    retl
   tail call void @llvm.x86.sse2.mfence()
   ret void
 }
 declare void @llvm.x86.sse2.mfence() nounwind
 
-; CHECK: clflush
 define void @clflush(i8* %p) nounwind {
-entry:
+; CHECK-LABEL: clflush:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    clflush (%eax)
+; CHECK-NEXT:    retl
   tail call void @llvm.x86.sse2.clflush(i8* %p)
   ret void
 }
 declare void @llvm.x86.sse2.clflush(i8*) nounwind
 
-; CHECK: crc32b
 define i32 @crc32_32_8(i32 %a, i8 %b) nounwind {
+; CHECK-LABEL: crc32_32_8:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    crc32b {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    retl
   %tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b)
   ret i32 %tmp
 }
 declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind
 
-; CHECK: crc32w
 define i32 @crc32_32_16(i32 %a, i16 %b) nounwind {
+; CHECK-LABEL: crc32_32_16:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    crc32w {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    retl
   %tmp = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a, i16 %b)
   ret i32 %tmp
 }
 declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind
 
-; CHECK: crc32l
 define i32 @crc32_32_32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc32_32_32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    crc32l {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    retl
   %tmp = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a, i32 %b)
   ret i32 %tmp
 }
 declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind
 
-; CHECK: movntdq
-define void @movnt_dq(i8* %p, <4 x i64> %a1) nounwind {
-  %a2 = add <4 x i64> %a1, <i64 1, i64 1, i64 1, i64 1>
-  tail call void @llvm.x86.avx.movnt.dq.256(i8* %p, <4 x i64> %a2) nounwind
+define void @movnt_dq(i8* %p, <2 x i64> %a1) nounwind {
+; CHECK-LABEL: movnt_dq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vpaddq LCPI282_0, %xmm0, %xmm0
+; CHECK-NEXT:    vmovntdq %ymm0, (%eax)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
+  %a2 = add <2 x i64> %a1, <i64 1, i64 1>
+  %a3 = shufflevector <2 x i64> %a2, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  tail call void @llvm.x86.avx.movnt.dq.256(i8* %p, <4 x i64> %a3) nounwind
   ret void
 }
 declare void @llvm.x86.avx.movnt.dq.256(i8*, <4 x i64>) nounwind
 
-; CHECK: movntps
 define void @movnt_ps(i8* %p, <8 x float> %a) nounwind {
+; CHECK-LABEL: movnt_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vmovntps %ymm0, (%eax)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   tail call void @llvm.x86.avx.movnt.ps.256(i8* %p, <8 x float> %a) nounwind
   ret void
 }
 declare void @llvm.x86.avx.movnt.ps.256(i8*, <8 x float>) nounwind
 
-; CHECK: movntpd
 define void @movnt_pd(i8* %p, <4 x double> %a1) nounwind {
   ; add operation forces the execution domain.
+; CHECK-LABEL: movnt_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
+; CHECK-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    vmovntpd %ymm0, (%eax)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
   %a2 = fadd <4 x double> %a1, <double 0x0, double 0x0, double 0x0, double 0x0>
   tail call void @llvm.x86.avx.movnt.pd.256(i8* %p, <4 x double> %a2) nounwind
   ret void
@@ -2606,7 +3420,10 @@ declare void @llvm.x86.avx.movnt.pd.256(i8*, <4 x double>) nounwind
 
 ; Check for pclmulqdq
 define <2 x i64> @test_x86_pclmulqdq(<2 x i64> %a0, <2 x i64> %a1) {
-; CHECK: vpclmulqdq
+; CHECK-LABEL: test_x86_pclmulqdq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpclmulqdq $0, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retl
   %res = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a0, <2 x i64> %a1, i8 0) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %res
 }
diff --git a/test/CodeGen/X86/avx-load-store.ll b/test/CodeGen/X86/avx-load-store.ll
index a6775aba0989..d2f213bac7bb 100644
--- a/test/CodeGen/X86/avx-load-store.ll
+++ b/test/CodeGen/X86/avx-load-store.ll
@@ -10,10 +10,10 @@
 define void @test_256_load(double* nocapture %d, float* nocapture %f, <4 x i64>* nocapture %i) nounwind uwtable ssp {
 entry:
   %0 = bitcast double* %d to <4 x double>*
-  %tmp1.i = load <4 x double>* %0, align 32
+  %tmp1.i = load <4 x double>, <4 x double>* %0, align 32
   %1 = bitcast float* %f to <8 x float>*
-  %tmp1.i17 = load <8 x float>* %1, align 32
-  %tmp1.i16 = load <4 x i64>* %i, align 32
+  %tmp1.i17 = load <8 x float>, <8 x float>* %1, align 32
+  %tmp1.i16 = load <4 x i64>, <4 x i64>* %i, align 32
   tail call void @dummy(<4 x double> %tmp1.i, <8 x float> %tmp1.i17, <4 x i64> %tmp1.i16) nounwind
   store <4 x double> %tmp1.i, <4 x double>* %0, align 32
   store <8 x float> %tmp1.i17, <8 x float>* %1, align 32
@@ -29,9 +29,8 @@ declare void @dummy(<4 x double>, <8 x float>, <4 x i64>)
 
 ; CHECK: mov00
 define <8 x float> @mov00(<8 x float> %v, float * %ptr) nounwind {
-  %val = load float* %ptr
-; CHECK: vinsertps
-; CHECK: vinsertf128
+  %val = load float, float* %ptr
+; CHECK: vmovss (%
   %i0 = insertelement <8 x float> zeroinitializer, float %val, i32 0
   ret <8 x float> %i0
 ; CHECK: ret
@@ -39,9 +38,8 @@ define <8 x float> @mov00(<8 x float> %v, float * %ptr) nounwind {
 
 ; CHECK: mov01
 define <4 x double> @mov01(<4 x double> %v, double * %ptr) nounwind {
-  %val = load double* %ptr
-; CHECK: vmovlpd
-; CHECK: vinsertf128
+  %val = load double, double* %ptr
+; CHECK: vmovsd (%
   %i0 = insertelement <4 x double> zeroinitializer, double %val, i32 0
   ret <4 x double> %i0
 ; CHECK: ret
@@ -122,7 +120,7 @@ cif_mixed_test_any_check:                         ; preds = %cif_mask_mixed
 ; CHECK: vmovups
 ; CHECK: vmovups
 define void @add8i32(<8 x i32>* %ret, <8 x i32>* %bp) nounwind {
-  %b = load <8 x i32>* %bp, align 1
+  %b = load <8 x i32>, <8 x i32>* %bp, align 1
   %x = add <8 x i32> zeroinitializer, %b
   store <8 x i32> %x, <8 x i32>* %ret, align 1
   ret void
@@ -132,7 +130,7 @@ define void @add8i32(<8 x i32>* %ret, <8 x i32>* %bp) nounwind {
 ; CHECK: vmovaps ({{.*}}), %ymm{{.*}}
 ; CHECK: vmovaps %ymm{{.*}}, ({{.*}})
 define void @add4i64a64(<4 x i64>* %ret, <4 x i64>* %bp) nounwind {
-  %b = load <4 x i64>* %bp, align 64
+  %b = load <4 x i64>, <4 x i64>* %bp, align 64
   %x = add <4 x i64> zeroinitializer, %b
   store <4 x i64> %x, <4 x i64>* %ret, align 64
   ret void
@@ -144,7 +142,7 @@ define void @add4i64a64(<4 x i64>* %ret, <4 x i64>* %bp) nounwind {
 ; CHECK: vmovaps %xmm{{.*}}, {{.*}}({{.*}})
 ; CHECK: vmovaps %xmm{{.*}}, {{.*}}({{.*}})
 define void @add4i64a16(<4 x i64>* %ret, <4 x i64>* %bp) nounwind {
-  %b = load <4 x i64>* %bp, align 16
+  %b = load <4 x i64>, <4 x i64>* %bp, align 16
   %x = add <4 x i64> zeroinitializer, %b
   store <4 x i64> %x, <4 x i64>* %ret, align 16
   ret void
diff --git a/test/CodeGen/X86/avx-logic.ll b/test/CodeGen/X86/avx-logic.ll
index 115cefb1b5eb..e71ac473b44d 100644
--- a/test/CodeGen/X86/avx-logic.ll
+++ b/test/CodeGen/X86/avx-logic.ll
@@ -1,7 +1,12 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
 
-; CHECK: vandpd
 define <4 x double> @andpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
+; CHECK-LABEL: andpd256:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vandpd %ymm0, %ymm1, %ymm0
+; CHECK-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
+; CHECK-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <4 x double> %x to <4 x i64>
   %1 = bitcast <4 x double> %y to <4 x i64>
@@ -12,8 +17,13 @@ entry:
   ret <4 x double> %3
 }
 
-; CHECK: vandpd LCP{{.*}}(%rip)
 define <4 x double> @andpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
+; CHECK-LABEL: andpd256fold:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vandpd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
+; CHECK-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <4 x double> %y to <4 x i64>
   %and.i = and <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507>
@@ -23,8 +33,11 @@ entry:
   ret <4 x double> %2
 }
 
-; CHECK: vandps
 define <8 x float> @andps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp {
+; CHECK-LABEL: andps256:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vandps %ymm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <8 x float> %x to <8 x i32>
   %1 = bitcast <8 x float> %y to <8 x i32>
@@ -33,8 +46,11 @@ entry:
   ret <8 x float> %2
 }
 
-; CHECK: vandps LCP{{.*}}(%rip)
 define <8 x float> @andps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
+; CHECK-LABEL: andps256fold:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vandps {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <8 x float> %y to <8 x i32>
   %and.i = and <8 x i32> %0, <i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938, i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938>
@@ -42,8 +58,13 @@ entry:
   ret <8 x float> %1
 }
 
-; CHECK: vxorpd
 define <4 x double> @xorpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
+; CHECK-LABEL: xorpd256:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vxorpd %ymm0, %ymm1, %ymm0
+; CHECK-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
+; CHECK-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <4 x double> %x to <4 x i64>
   %1 = bitcast <4 x double> %y to <4 x i64>
@@ -54,8 +75,13 @@ entry:
   ret <4 x double> %3
 }
 
-; CHECK: vxorpd LCP{{.*}}(%rip)
 define <4 x double> @xorpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
+; CHECK-LABEL: xorpd256fold:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vxorpd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
+; CHECK-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <4 x double> %y to <4 x i64>
   %xor.i = xor <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507>
@@ -65,8 +91,11 @@ entry:
   ret <4 x double> %2
 }
 
-; CHECK: vxorps
 define <8 x float> @xorps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp {
+; CHECK-LABEL: xorps256:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vxorps %ymm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <8 x float> %x to <8 x i32>
   %1 = bitcast <8 x float> %y to <8 x i32>
@@ -75,8 +104,11 @@ entry:
   ret <8 x float> %2
 }
 
-; CHECK: vxorps LCP{{.*}}(%rip)
 define <8 x float> @xorps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
+; CHECK-LABEL: xorps256fold:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vxorps {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <8 x float> %y to <8 x i32>
   %xor.i = xor <8 x i32> %0, <i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938, i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938>
@@ -84,8 +116,13 @@ entry:
   ret <8 x float> %1
 }
 
-; CHECK: vorpd
 define <4 x double> @orpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
+; CHECK-LABEL: orpd256:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vorpd %ymm0, %ymm1, %ymm0
+; CHECK-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
+; CHECK-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <4 x double> %x to <4 x i64>
   %1 = bitcast <4 x double> %y to <4 x i64>
@@ -96,8 +133,13 @@ entry:
   ret <4 x double> %3
 }
 
-; CHECK: vorpd LCP{{.*}}(%rip)
 define <4 x double> @orpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
+; CHECK-LABEL: orpd256fold:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vorpd {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
+; CHECK-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <4 x double> %y to <4 x i64>
   %or.i = or <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507>
@@ -107,8 +149,11 @@ entry:
   ret <4 x double> %2
 }
 
-; CHECK: vorps
 define <8 x float> @orps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp {
+; CHECK-LABEL: orps256:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vorps %ymm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <8 x float> %x to <8 x i32>
   %1 = bitcast <8 x float> %y to <8 x i32>
@@ -117,8 +162,11 @@ entry:
   ret <8 x float> %2
 }
 
-; CHECK: vorps LCP{{.*}}(%rip)
 define <8 x float> @orps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
+; CHECK-LABEL: orps256fold:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vorps {{.*}}(%rip), %ymm0, %ymm0
+; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <8 x float> %y to <8 x i32>
   %or.i = or <8 x i32> %0, <i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938, i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938>
@@ -126,8 +174,13 @@ entry:
   ret <8 x float> %1
 }
 
-; CHECK: vandnpd
 define <4 x double> @andnotpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
+; CHECK-LABEL: andnotpd256:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vandnpd %ymm0, %ymm1, %ymm0
+; CHECK-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
+; CHECK-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <4 x double> %x to <4 x i64>
   %neg.i = xor <4 x i64> %0, <i64 -1, i64 -1, i64 -1, i64 -1>
@@ -139,10 +192,15 @@ entry:
   ret <4 x double> %3
 }
 
-; CHECK: vandnpd (%
 define <4 x double> @andnotpd256fold(<4 x double> %y, <4 x double>* nocapture %x) nounwind uwtable readonly ssp {
+; CHECK-LABEL: andnotpd256fold:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vandnpd (%rdi), %ymm0, %ymm0
+; CHECK-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
+; CHECK-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
 entry:
-  %tmp2 = load <4 x double>* %x, align 32
+  %tmp2 = load <4 x double>, <4 x double>* %x, align 32
   %0 = bitcast <4 x double> %y to <4 x i64>
   %neg.i = xor <4 x i64> %0, <i64 -1, i64 -1, i64 -1, i64 -1>
   %1 = bitcast <4 x double> %tmp2 to <4 x i64>
@@ -153,8 +211,11 @@ entry:
   ret <4 x double> %3
 }
 
-; CHECK: vandnps
 define <8 x float> @andnotps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp {
+; CHECK-LABEL: andnotps256:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vandnps %ymm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <8 x float> %x to <8 x i32>
   %neg.i = xor <8 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
@@ -164,10 +225,13 @@ entry:
   ret <8 x float> %2
 }
 
-; CHECK: vandnps (%
 define <8 x float> @andnotps256fold(<8 x float> %y, <8 x float>* nocapture %x) nounwind uwtable readonly ssp {
+; CHECK-LABEL: andnotps256fold:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vandnps (%rdi), %ymm0, %ymm0
+; CHECK-NEXT:    retq
 entry:
-  %tmp2 = load <8 x float>* %x, align 32
+  %tmp2 = load <8 x float>, <8 x float>* %x, align 32
   %0 = bitcast <8 x float> %y to <8 x i32>
   %neg.i = xor <8 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
   %1 = bitcast <8 x float> %tmp2 to <8 x i32>
@@ -178,8 +242,12 @@ entry:
 
 ;;; Test that basic 2 x i64 logic use the integer version on AVX
 
-; CHECK: vpandn  %xmm
 define <2 x i64> @vpandn(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpandn:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vpaddq {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT:    vpandn %xmm0, %xmm1, %xmm0
+; CHECK-NEXT:    retq
 entry:
   ; Force the execution domain with an add.
   %a2 = add <2 x i64> %a, <i64 1, i64 1>
@@ -188,8 +256,12 @@ entry:
   ret <2 x i64> %x
 }
 
-; CHECK: vpand %xmm
 define <2 x i64> @vpand(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
+; CHECK-LABEL: vpand:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vpaddq {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
 entry:
   ; Force the execution domain with an add.
   %a2 = add <2 x i64> %a, <i64 1, i64 1>
diff --git a/test/CodeGen/X86/avx-shift.ll b/test/CodeGen/X86/avx-shift.ll
index a70d45a7991a..83585b536095 100644
--- a/test/CodeGen/X86/avx-shift.ll
+++ b/test/CodeGen/X86/avx-shift.ll
@@ -1,147 +1,224 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
 
 ;;; Shift left
-; CHECK: vpslld
-; CHECK: vpslld
-define <8 x i32> @vshift00(<8 x i32> %a) nounwind readnone {
+define <8 x i32> @vshift00(<8 x i32> %a) {
+; CHECK-LABEL: vshift00:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpslld $2, %xmm0, %xmm1
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:    vpslld $2, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
   %s = shl <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
 2>
   ret <8 x i32> %s
 }
 
-; CHECK: vpsllw
-; CHECK: vpsllw
-define <16 x i16> @vshift01(<16 x i16> %a) nounwind readnone {
+define <16 x i16> @vshift01(<16 x i16> %a) {
+; CHECK-LABEL: vshift01:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsllw $2, %xmm0, %xmm1
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:    vpsllw $2, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
   %s = shl <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
   ret <16 x i16> %s
 }
 
-; CHECK: vpsllq
-; CHECK: vpsllq
-define <4 x i64> @vshift02(<4 x i64> %a) nounwind readnone {
+define <4 x i64> @vshift02(<4 x i64> %a) {
+; CHECK-LABEL: vshift02:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsllq $2, %xmm0, %xmm1
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:    vpsllq $2, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
   %s = shl <4 x i64> %a, <i64 2, i64 2, i64 2, i64 2>
   ret <4 x i64> %s
 }
 
 ;;; Logical Shift right
-; CHECK: vpsrld
-; CHECK: vpsrld
-define <8 x i32> @vshift03(<8 x i32> %a) nounwind readnone {
+define <8 x i32> @vshift03(<8 x i32> %a) {
+; CHECK-LABEL: vshift03:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsrld $2, %xmm0, %xmm1
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:    vpsrld $2, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
   %s = lshr <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
 2>
   ret <8 x i32> %s
 }
 
-; CHECK: vpsrlw
-; CHECK: vpsrlw
-define <16 x i16> @vshift04(<16 x i16> %a) nounwind readnone {
+define <16 x i16> @vshift04(<16 x i16> %a) {
+; CHECK-LABEL: vshift04:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsrlw $2, %xmm0, %xmm1
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:    vpsrlw $2, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
   %s = lshr <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
   ret <16 x i16> %s
 }
 
-; CHECK: vpsrlq
-; CHECK: vpsrlq
-define <4 x i64> @vshift05(<4 x i64> %a) nounwind readnone {
+define <4 x i64> @vshift05(<4 x i64> %a) {
+; CHECK-LABEL: vshift05:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsrlq $2, %xmm0, %xmm1
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:    vpsrlq $2, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
   %s = lshr <4 x i64> %a, <i64 2, i64 2, i64 2, i64 2>
   ret <4 x i64> %s
 }
 
 ;;; Arithmetic Shift right
-; CHECK: vpsrad
-; CHECK: vpsrad
-define <8 x i32> @vshift06(<8 x i32> %a) nounwind readnone {
+define <8 x i32> @vshift06(<8 x i32> %a) {
+; CHECK-LABEL: vshift06:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsrad $2, %xmm0, %xmm1
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:    vpsrad $2, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
   %s = ashr <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
 2>
   ret <8 x i32> %s
 }
 
-; CHECK: vpsraw
-; CHECK: vpsraw
-define <16 x i16> @vshift07(<16 x i16> %a) nounwind readnone {
+define <16 x i16> @vshift07(<16 x i16> %a) {
+; CHECK-LABEL: vshift07:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsraw $2, %xmm0, %xmm1
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:    vpsraw $2, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
   %s = ashr <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
   ret <16 x i16> %s
 }
 
-; CHECK: vpsrlw
-; CHECK: pand
-; CHECK: pxor
-; CHECK: psubb
-; CHECK: vpsrlw
-; CHECK: pand
-; CHECK: pxor
-; CHECK: psubb
-define <32 x i8> @vshift09(<32 x i8> %a) nounwind readnone {
+define <32 x i8> @vshift09(<32 x i8> %a) {
+; CHECK-LABEL: vshift09:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT:    vpsrlw $2, %xmm1, %xmm1
+; CHECK-NEXT:    vmovdqa {{.*#+}} xmm2 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
+; CHECK-NEXT:    vpand %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vmovdqa {{.*#+}} xmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; CHECK-NEXT:    vpxor %xmm3, %xmm1, %xmm1
+; CHECK-NEXT:    vpsubb %xmm3, %xmm1, %xmm1
+; CHECK-NEXT:    vpsrlw $2, %xmm0, %xmm0
+; CHECK-NEXT:    vpand %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:    vpxor %xmm3, %xmm0, %xmm0
+; CHECK-NEXT:    vpsubb %xmm3, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %s = ashr <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
   ret <32 x i8> %s
 }
 
-; CHECK: pxor
-; CHECK: pcmpgtb
-; CHECK: pcmpgtb
-define <32 x i8> @vshift10(<32 x i8> %a) nounwind readnone {
+define <32 x i8> @vshift10(<32 x i8> %a) {
+; CHECK-LABEL: vshift10:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vpcmpgtb %xmm1, %xmm2, %xmm1
+; CHECK-NEXT:    vpcmpgtb %xmm0, %xmm2, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %s = ashr <32 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
   ret <32 x i8> %s
 }
 
-; CHECK: vpsrlw
-; CHECK: pand
-; CHECK: vpsrlw
-; CHECK: pand
-define <32 x i8> @vshift11(<32 x i8> %a) nounwind readnone {
+define <32 x i8> @vshift11(<32 x i8> %a) {
+; CHECK-LABEL: vshift11:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT:    vpsrlw $2, %xmm1, %xmm1
+; CHECK-NEXT:    vmovdqa {{.*#+}} xmm2 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
+; CHECK-NEXT:    vpand %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vpsrlw $2, %xmm0, %xmm0
+; CHECK-NEXT:    vpand %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %s = lshr <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
   ret <32 x i8> %s
 }
 
-; CHECK: vpsllw
-; CHECK: pand
-; CHECK: vpsllw
-; CHECK: pand
-define <32 x i8> @vshift12(<32 x i8> %a) nounwind readnone {
+define <32 x i8> @vshift12(<32 x i8> %a) {
+; CHECK-LABEL: vshift12:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT:    vpsllw $2, %xmm1, %xmm1
+; CHECK-NEXT:    vmovdqa {{.*#+}} xmm2 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
+; CHECK-NEXT:    vpand %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vpsllw $2, %xmm0, %xmm0
+; CHECK-NEXT:    vpand %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %s = shl <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
   ret <32 x i8> %s
 }
 
 ;;; Support variable shifts
-; CHECK: _vshift08
-; CHECK: vpslld $23
-; CHECK: vextractf128 $1
-; CHECK: vpslld $23
-; CHECK: ret
-define <8 x i32> @vshift08(<8 x i32> %a) nounwind {
+define <8 x i32> @vshift08(<8 x i32> %a)  {
+; CHECK-LABEL: vshift08:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpslld $23, %xmm0, %xmm1
+; CHECK-NEXT:    vmovdqa {{.*#+}} xmm2 = [1065353216,1065353216,1065353216,1065353216]
+; CHECK-NEXT:    vpaddd %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vcvttps2dq %xmm1, %xmm1
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:    vpslld $23, %xmm0, %xmm0
+; CHECK-NEXT:    vpaddd %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
   %bitop = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %a
   ret <8 x i32> %bitop
 }
 
 ; PR15141
-; CHECK: _vshift13:
-; CHECK-NOT: vpsll
-; CHECK-NOT: vcvttps2dq
-; CHECK: vpmulld
 define <4 x i32> @vshift13(<4 x i32> %in) {
+; CHECK-LABEL: vshift13:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmulld {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %T = shl <4 x i32> %in, <i32 0, i32 1, i32 2, i32 4>
   ret <4 x i32> %T
 }
 
 ;;; Uses shifts for sign extension
-; CHECK: _sext_v16i16
-; CHECK: vpsllw
-; CHECK: vpsraw
-; CHECK: vpsllw
-; CHECK: vpsraw
-; CHECK: vinsertf128
-define <16 x i16> @sext_v16i16(<16 x i16> %a) nounwind {
+define <16 x i16> @sext_v16i16(<16 x i16> %a)  {
+; CHECK-LABEL: sext_v16i16:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsllw $8, %xmm0, %xmm1
+; CHECK-NEXT:    vpsraw $8, %xmm1, %xmm1
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:    vpsllw $8, %xmm0, %xmm0
+; CHECK-NEXT:    vpsraw $8, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
   %b = trunc <16 x i16> %a to <16 x i8>
   %c = sext <16 x i8> %b to <16 x i16>
   ret <16 x i16> %c
 }
 
-; CHECK: _sext_v8i32
-; CHECK: vpslld
-; CHECK: vpsrad
-; CHECK: vpslld
-; CHECK: vpsrad
-; CHECK: vinsertf128
-define <8 x i32> @sext_v8i32(<8 x i32> %a) nounwind {
+define <8 x i32> @sext_v8i32(<8 x i32> %a)  {
+; CHECK-LABEL: sext_v8i32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpslld $16, %xmm0, %xmm1
+; CHECK-NEXT:    vpsrad $16, %xmm1, %xmm1
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:    vpslld $16, %xmm0, %xmm0
+; CHECK-NEXT:    vpsrad $16, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
   %b = trunc <8 x i32> %a to <8 x i16>
   %c = sext <8 x i16> %b to <8 x i32>
   ret <8 x i32> %c
diff --git a/test/CodeGen/X86/avx-splat.ll b/test/CodeGen/X86/avx-splat.ll
index 98c1645b9080..3ea7e386c426 100644
--- a/test/CodeGen/X86/avx-splat.ll
+++ b/test/CodeGen/X86/avx-splat.ll
@@ -18,7 +18,7 @@ entry:
 }
 
 ; CHECK: vmovq
-; CHECK-NEXT: vunpcklpd %xmm
+; CHECK-NEXT: vmovddup %xmm
 ; CHECK-NEXT: vinsertf128 $1
 define <4 x i64> @funcC(i64 %q) nounwind uwtable readnone ssp {
 entry:
@@ -29,7 +29,7 @@ entry:
   ret <4 x i64> %vecinit6.i
 }
 
-; CHECK: vunpcklpd %xmm
+; CHECK: vmovddup %xmm
 ; CHECK-NEXT: vinsertf128 $1
 define <4 x double> @funcD(double %q) nounwind uwtable readnone ssp {
 entry:
@@ -42,7 +42,7 @@ entry:
 
 ; Test this turns into a broadcast:
 ;   shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
-;   
+;
 ; CHECK: vbroadcastss
 define <8 x float> @funcE() nounwind {
 allocas:
@@ -56,9 +56,9 @@ for_exit499:                                      ; preds = %for_test505.prehead
   br i1 undef, label %__load_and_broadcast_32.exit1249, label %load.i1247
 
 load.i1247:                                       ; preds = %for_exit499
-  %ptr1227 = getelementptr [18 x [18 x float]]* %udx495, i64 0, i64 1, i64 1
+  %ptr1227 = getelementptr [18 x [18 x float]], [18 x [18 x float]]* %udx495, i64 0, i64 1, i64 1
   %ptr.i1237 = bitcast float* %ptr1227 to i32*
-  %val.i1238 = load i32* %ptr.i1237, align 4
+  %val.i1238 = load i32, i32* %ptr.i1237, align 4
   %ret6.i1245 = insertelement <8 x i32> undef, i32 %val.i1238, i32 6
   %ret7.i1246 = insertelement <8 x i32> %ret6.i1245, i32 %val.i1238, i32 7
   %phitmp = bitcast <8 x i32> %ret7.i1246 to <8 x float>
diff --git a/test/CodeGen/X86/avx-trunc.ll b/test/CodeGen/X86/avx-trunc.ll
index bf8d9a7f1a40..27be9fd2fcd1 100755
--- a/test/CodeGen/X86/avx-trunc.ll
+++ b/test/CodeGen/X86/avx-trunc.ll
@@ -2,9 +2,9 @@
 
 define <4 x i32> @trunc_64_32(<4 x i64> %A) nounwind uwtable readnone ssp{
 ; CHECK-LABEL: trunc_64_32
-; CHECK: shufps
-; CHECK-NOT: pshufd
-; CHECK-NOT: movlhps 
+; CHECK: pshufd
+; CHECK: pshufd
+; CHECK: pblendw
   %B = trunc <4 x i64> %A to <4 x i32>
   ret <4 x i32>%B
 }
diff --git a/test/CodeGen/X86/avx-unpack.ll b/test/CodeGen/X86/avx-unpack.ll
index 20f534532263..6924d98b38b1 100644
--- a/test/CodeGen/X86/avx-unpack.ll
+++ b/test/CodeGen/X86/avx-unpack.ll
@@ -70,8 +70,8 @@ entry:
 ; CHECK: vunpckhps (%
 define <8 x i32> @unpackhips2(<8 x i32>* %src1, <8 x i32>* %src2) nounwind uwtable readnone ssp {
 entry:
-  %a = load <8 x i32>* %src1
-  %b = load <8 x i32>* %src2
+  %a = load <8 x i32>, <8 x i32>* %src1
+  %b = load <8 x i32>, <8 x i32>* %src2
   %shuffle.i = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15>
   ret <8 x i32> %shuffle.i
 }
@@ -86,8 +86,8 @@ entry:
 ; CHECK: vunpckhpd (%
 define <4 x i64> @unpackhipd2(<4 x i64>* %src1, <4 x i64>* %src2) nounwind uwtable readnone ssp {
 entry:
-  %a = load <4 x i64>* %src1
-  %b = load <4 x i64>* %src2
+  %a = load <4 x i64>, <4 x i64>* %src1
+  %b = load <4 x i64>, <4 x i64>* %src2
   %shuffle.i = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
   ret <4 x i64> %shuffle.i
 }
@@ -102,8 +102,8 @@ entry:
 ; CHECK: vunpcklps (%
 define <8 x i32> @unpacklops2(<8 x i32>* %src1, <8 x i32>* %src2) nounwind uwtable readnone ssp {
 entry:
-  %a = load <8 x i32>* %src1
-  %b = load <8 x i32>* %src2
+  %a = load <8 x i32>, <8 x i32>* %src1
+  %b = load <8 x i32>, <8 x i32>* %src2
   %shuffle.i = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13>
   ret <8 x i32> %shuffle.i
 }
@@ -118,8 +118,8 @@ entry:
 ; CHECK: vunpcklpd (%
 define <4 x i64> @unpacklopd2(<4 x i64>* %src1, <4 x i64>* %src2) nounwind uwtable readnone ssp {
 entry:
-  %a = load <4 x i64>* %src1
-  %b = load <4 x i64>* %src2
+  %a = load <4 x i64>, <4 x i64>* %src1
+  %b = load <4 x i64>, <4 x i64>* %src2
   %shuffle.i = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
   ret <4 x i64> %shuffle.i
 }
diff --git a/test/CodeGen/X86/avx-varargs-x86_64.ll b/test/CodeGen/X86/avx-varargs-x86_64.ll
index f73174dd2bc6..7ce5e19064ad 100644
--- a/test/CodeGen/X86/avx-varargs-x86_64.ll
+++ b/test/CodeGen/X86/avx-varargs-x86_64.ll
@@ -9,7 +9,7 @@ declare i32 @f(i32, ...)
 ; CHECK: vmovaps	%ymm0, (%rsp)
 define void @test1() nounwind uwtable ssp {
 entry:
-  %0 = load <8 x float>* @x, align 32
-  %call = call i32 (i32, ...)* @f(i32 1, <8 x float> %0)
+  %0 = load <8 x float>, <8 x float>* @x, align 32
+  %call = call i32 (i32, ...) @f(i32 1, <8 x float> %0)
   ret void
 }
diff --git a/test/CodeGen/X86/avx-vbroadcast.ll b/test/CodeGen/X86/avx-vbroadcast.ll
index 2ebe6fda37a3..8b8c11b85875 100644
--- a/test/CodeGen/X86/avx-vbroadcast.ll
+++ b/test/CodeGen/X86/avx-vbroadcast.ll
@@ -3,7 +3,7 @@
 ; CHECK: vbroadcastsd (%
 define <4 x i64> @A(i64* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load i64* %ptr, align 8
+  %q = load i64, i64* %ptr, align 8
   %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
   %vecinit2.i = insertelement <4 x i64> %vecinit.i, i64 %q, i32 1
   %vecinit4.i = insertelement <4 x i64> %vecinit2.i, i64 %q, i32 2
@@ -14,7 +14,7 @@ entry:
 ; CHECK: vbroadcastss (%
 define <8 x i32> @B(i32* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load i32* %ptr, align 4
+  %q = load i32, i32* %ptr, align 4
   %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
   %vecinit2.i = insertelement <8 x i32> %vecinit.i, i32 %q, i32 1
   %vecinit4.i = insertelement <8 x i32> %vecinit2.i, i32 %q, i32 2
@@ -25,7 +25,7 @@ entry:
 ; CHECK: vbroadcastsd (%
 define <4 x double> @C(double* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load double* %ptr, align 8
+  %q = load double, double* %ptr, align 8
   %vecinit.i = insertelement <4 x double> undef, double %q, i32 0
   %vecinit2.i = insertelement <4 x double> %vecinit.i, double %q, i32 1
   %vecinit4.i = insertelement <4 x double> %vecinit2.i, double %q, i32 2
@@ -36,7 +36,7 @@ entry:
 ; CHECK: vbroadcastss (%
 define <8 x float> @D(float* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load float* %ptr, align 4
+  %q = load float, float* %ptr, align 4
   %vecinit.i = insertelement <8 x float> undef, float %q, i32 0
   %vecinit2.i = insertelement <8 x float> %vecinit.i, float %q, i32 1
   %vecinit4.i = insertelement <8 x float> %vecinit2.i, float %q, i32 2
@@ -49,7 +49,7 @@ entry:
 ; CHECK: vbroadcastss (%
 define <4 x float> @e(float* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load float* %ptr, align 4
+  %q = load float, float* %ptr, align 4
   %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
   %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1
   %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2
@@ -73,7 +73,7 @@ define <4 x float> @_e2(float* %ptr) nounwind uwtable readnone ssp {
 ; CHECK: vbroadcastss (%
 define <4 x i32> @F(i32* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load i32* %ptr, align 4
+  %q = load i32, i32* %ptr, align 4
   %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
   %vecinit2.i = insertelement <4 x i32> %vecinit.i, i32 %q, i32 1
   %vecinit4.i = insertelement <4 x i32> %vecinit2.i, i32 %q, i32 2
@@ -88,7 +88,7 @@ entry:
 ; CHECK: ret
 define <2 x i64> @G(i64* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load i64* %ptr, align 8
+  %q = load i64, i64* %ptr, align 8
   %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
   %vecinit2.i = insertelement <2 x i64> %vecinit.i, i64 %q, i32 1
   ret <2 x i64> %vecinit2.i
@@ -107,7 +107,7 @@ define <4 x i32> @H(<4 x i32> %a) {
 ; CHECK: ret
 define <2 x double> @I(double* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load double* %ptr, align 4
+  %q = load double, double* %ptr, align 4
   %vecinit.i = insertelement <2 x double> undef, double %q, i32 0
   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %q, i32 1
   ret <2 x double> %vecinit2.i
@@ -118,13 +118,13 @@ entry:
 ; CHECK: ret
 define <4 x float> @_RR(float* %ptr, i32* %k) nounwind uwtable readnone ssp {
 entry:
-  %q = load float* %ptr, align 4
+  %q = load float, float* %ptr, align 4
   %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
   %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1
   %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2
   %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 3
   ; force a chain
-  %j = load i32* %k, align 4
+  %j = load i32, i32* %k, align 4
   store i32 %j, i32* undef
   ret <4 x float> %vecinit6.i
 }
@@ -135,7 +135,7 @@ entry:
 ; CHECK: ret
 define <4 x float> @_RR2(float* %ptr, i32* %k) nounwind uwtable readnone ssp {
 entry:
-  %q = load float* %ptr, align 4
+  %q = load float, float* %ptr, align 4
   %v = insertelement <4 x float> undef, float %q, i32 0
   %t = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> zeroinitializer
   ret <4 x float> %t
@@ -151,7 +151,7 @@ entry:
 ; CHECK: vbroadcastss (%
 ; CHECK-NEXT: ret
 define <8 x float> @splat_concat1(float* %p) {
-  %1 = load float* %p, align 4
+  %1 = load float, float* %p, align 4
   %2 = insertelement <4 x float> undef, float %1, i32 0
   %3 = insertelement <4 x float> %2, float %1, i32 1
   %4 = insertelement <4 x float> %3, float %1, i32 2
@@ -165,7 +165,7 @@ define <8 x float> @splat_concat1(float* %p) {
 ; CHECK: vbroadcastss (%
 ; CHECK-NEXT: ret
 define <8 x float> @splat_concat2(float* %p) {
-  %1 = load float* %p, align 4
+  %1 = load float, float* %p, align 4
   %2 = insertelement <4 x float> undef, float %1, i32 0
   %3 = insertelement <4 x float> %2, float %1, i32 1
   %4 = insertelement <4 x float> %3, float %1, i32 2
@@ -183,7 +183,7 @@ define <8 x float> @splat_concat2(float* %p) {
 ; CHECK: vbroadcastsd (%
 ; CHECK-NEXT: ret
 define <4 x double> @splat_concat3(double* %p) {
-  %1 = load double* %p, align 8
+  %1 = load double, double* %p, align 8
   %2 = insertelement <2 x double> undef, double %1, i32 0
   %3 = insertelement <2 x double> %2, double %1, i32 1
   %4 = shufflevector <2 x double> %3, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
@@ -195,7 +195,7 @@ define <4 x double> @splat_concat3(double* %p) {
 ; CHECK: vbroadcastsd (%
 ; CHECK-NEXT: ret
 define <4 x double> @splat_concat4(double* %p) {
-  %1 = load double* %p, align 8
+  %1 = load double, double* %p, align 8
   %2 = insertelement <2 x double> undef, double %1, i32 0
   %3 = insertelement <2 x double> %2, double %1, i32 1
   %4 = insertelement <2 x double> undef, double %1, i32 0
diff --git a/test/CodeGen/X86/avx-vextractf128.ll b/test/CodeGen/X86/avx-vextractf128.ll
index fa49f949b689..297fb250c5ff 100644
--- a/test/CodeGen/X86/avx-vextractf128.ll
+++ b/test/CodeGen/X86/avx-vextractf128.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s
 
-; CHECK: @A
+; CHECK-LABEL: A:
 ; CHECK-NOT: vunpck
 ; CHECK: vextractf128 $1
 define <8 x float> @A(<8 x float> %a) nounwind uwtable readnone ssp {
@@ -9,7 +9,7 @@ entry:
   ret <8 x float> %shuffle
 }
 
-; CHECK: @B
+; CHECK-LABEL: B:
 ; CHECK-NOT: vunpck
 ; CHECK: vextractf128 $1
 define <4 x double> @B(<4 x double> %a) nounwind uwtable readnone ssp {
@@ -18,7 +18,7 @@ entry:
   ret <4 x double> %shuffle
 }
 
-; CHECK: @t0
+; CHECK-LABEL: t0:
 ; CHECK-NOT: vextractf128 $1, %ymm0, %xmm0
 ; CHECK-NOT: vmovaps %xmm0, (%rdi)
 ; CHECK: vextractf128 $1, %ymm0, (%rdi)
@@ -32,7 +32,7 @@ entry:
 
 declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone
 
-; CHECK: @t2
+; CHECK-LABEL: t2:
 ; CHECK-NOT: vextractf128 $1, %ymm0, %xmm0
 ; CHECK-NOT: vmovaps %xmm0, (%rdi)
 ; CHECK: vextractf128 $1, %ymm0, (%rdi)
@@ -46,7 +46,7 @@ entry:
 
 declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone
 
-; CHECK: @t4
+; CHECK-LABEL: t4:
 ; CHECK-NOT: vextractf128 $1, %ymm0, %xmm0
 ; CHECK-NOT: vmovaps %xmm0, (%rdi)
 ; CHECK: vextractf128 $1, %ymm0, (%rdi)
@@ -61,7 +61,7 @@ entry:
 
 declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind readnone
 
-; CHECK: @t5
+; CHECK-LABEL: t5:
 ; CHECK: vmovaps %xmm0, (%rdi)
 define void @t5(float* nocapture %addr, <8 x float> %a) nounwind uwtable ssp {
 entry:
@@ -71,7 +71,7 @@ entry:
   ret void
 }
 
-; CHECK: @t6
+; CHECK-LABEL: t6:
 ; CHECK: vmovaps %xmm0, (%rdi)
 define void @t6(double* nocapture %addr, <4 x double> %a) nounwind uwtable ssp {
 entry:
@@ -81,7 +81,7 @@ entry:
   ret void
 }
 
-; CHECK: @t7
+; CHECK-LABEL: t7:
 ; CHECK: vmovaps %xmm0, (%rdi)
 define void @t7(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp {
 entry:
@@ -92,7 +92,7 @@ entry:
   ret void
 }
 
-; CHECK: @t8
+; CHECK-LABEL: t8:
 ; CHECK: vmovups %xmm0, (%rdi)
 define void @t8(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp {
 entry:
@@ -106,11 +106,11 @@ entry:
 ; PR15462
 define void @t9(i64* %p) {
  store i64 0, i64* %p
- %q = getelementptr i64* %p, i64 1
+ %q = getelementptr i64, i64* %p, i64 1
  store i64 0, i64* %q
- %r = getelementptr i64* %p, i64 2
+ %r = getelementptr i64, i64* %p, i64 2
  store i64 0, i64* %r
- %s = getelementptr i64* %p, i64 3
+ %s = getelementptr i64, i64* %p, i64 3
  store i64 0, i64* %s
  ret void
 
@@ -118,5 +118,4 @@ define void @t9(i64* %p) {
 ; CHECK: vxorps	%xmm
 ; CHECK-NOT: vextractf
 ; CHECK: vmovups
-; CHECK: vmovups
 }
diff --git a/test/CodeGen/X86/avx-vinsertf128.ll b/test/CodeGen/X86/avx-vinsertf128.ll
index 9a954fe8047e..38389de7a8a1 100644
--- a/test/CodeGen/X86/avx-vinsertf128.ll
+++ b/test/CodeGen/X86/avx-vinsertf128.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=CHECK-SSE %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s
 
+; CHECK-LABEL: A:
 ; CHECK-NOT: vunpck
 ; CHECK: vinsertf128 $1
 define <8 x float> @A(<8 x float> %a) nounwind uwtable readnone ssp {
@@ -9,6 +9,7 @@ entry:
   ret <8 x float> %shuffle
 }
 
+; CHECK-LABEL: B:
 ; CHECK-NOT: vunpck
 ; CHECK: vinsertf128 $1
 define <4 x double> @B(<4 x double> %a) nounwind uwtable readnone ssp {
@@ -22,7 +23,7 @@ declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind
 declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
 
 ; Just check that no crash happens
-; CHECK-SSE: _insert_crash
+; CHECK-LABEL: _insert_crash:
 define void @insert_crash() nounwind {
 allocas:
   %v1.i.i451 = shufflevector <4 x double> zeroinitializer, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
@@ -39,7 +40,7 @@ allocas:
 
 ;; DAG Combine must remove useless vinsertf128 instructions
 
-; CHECK: DAGCombineA
+; CHECK-LABEL: DAGCombineA:
 ; CHECK-NOT: vinsertf128 $1
 define <4 x i32> @DAGCombineA(<4 x i32> %v1) nounwind readonly {
   %1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -47,7 +48,7 @@ define <4 x i32> @DAGCombineA(<4 x i32> %v1) nounwind readonly {
   ret <4 x i32> %2
 }
 
-; CHECK: DAGCombineB
+; CHECK-LABEL: DAGCombineB:
 ; CHECK: vpaddd %xmm
 ; CHECK-NOT: vinsertf128  $1
 ; CHECK: vpaddd %xmm
@@ -57,14 +58,7 @@ define <8 x i32> @DAGCombineB(<8 x i32> %v1, <8 x i32> %v2) nounwind readonly {
   ret <8 x i32> %2
 }
 
-; CHECK: insert_pd
-define <4 x double> @insert_pd(<4 x double> %a0, <2 x double> %a1) {
-; CHECK: vinsertf128
-%res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> %a0, <2 x double> %a1, i8 0)
-ret <4 x double> %res
-}
-
-; CHECK: insert_undef_pd
+; CHECK-LABEL: insert_undef_pd:
 define <4 x double> @insert_undef_pd(<4 x double> %a0, <2 x double> %a1) {
 ; CHECK: vmovaps	%ymm1, %ymm0
 %res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> undef, <2 x double> %a1, i8 0)
@@ -73,14 +67,7 @@ ret <4 x double> %res
 declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double>, i8) nounwind readnone
 
 
-; CHECK: insert_ps
-define <8 x float> @insert_ps(<8 x float> %a0, <4 x float> %a1) {
-; CHECK: vinsertf128
-%res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %a0, <4 x float> %a1, i8 0)
-ret <8 x float> %res
-}
-
-; CHECK: insert_undef_ps
+; CHECK-LABEL: insert_undef_ps:
 define <8 x float> @insert_undef_ps(<8 x float> %a0, <4 x float> %a1) {
 ; CHECK: vmovaps	%ymm1, %ymm0
 %res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %a1, i8 0)
@@ -89,14 +76,7 @@ ret <8 x float> %res
 declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i8) nounwind readnone
 
 
-; CHECK: insert_si
-define <8 x i32> @insert_si(<8 x i32> %a0, <4 x i32> %a1) {
-; CHECK: vinsertf128
-%res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> %a0, <4 x i32> %a1, i8 0)
-ret <8 x i32> %res
-}
-
-; CHECK: insert_undef_si
+; CHECK-LABEL: insert_undef_si:
 define <8 x i32> @insert_undef_si(<8 x i32> %a0, <4 x i32> %a1) {
 ; CHECK: vmovaps	%ymm1, %ymm0
 %res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> undef, <4 x i32> %a1, i8 0)
@@ -105,27 +85,27 @@ ret <8 x i32> %res
 declare <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32>, <4 x i32>, i8) nounwind readnone
 
 ; rdar://10643481
-; CHECK: vinsertf128_combine
+; CHECK-LABEL: vinsertf128_combine:
 define <8 x float> @vinsertf128_combine(float* nocapture %f) nounwind uwtable readonly ssp {
 ; CHECK-NOT: vmovaps
 ; CHECK: vinsertf128
 entry:
-  %add.ptr = getelementptr inbounds float* %f, i64 4
+  %add.ptr = getelementptr inbounds float, float* %f, i64 4
   %0 = bitcast float* %add.ptr to <4 x float>*
-  %1 = load <4 x float>* %0, align 16
+  %1 = load <4 x float>, <4 x float>* %0, align 16
   %2 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %1, i8 1)
   ret <8 x float> %2
 }
 
 ; rdar://11076953
-; CHECK: vinsertf128_ucombine
+; CHECK-LABEL: vinsertf128_ucombine:
 define <8 x float> @vinsertf128_ucombine(float* nocapture %f) nounwind uwtable readonly ssp {
 ; CHECK-NOT: vmovups
 ; CHECK: vinsertf128
 entry:
-  %add.ptr = getelementptr inbounds float* %f, i64 4
+  %add.ptr = getelementptr inbounds float, float* %f, i64 4
   %0 = bitcast float* %add.ptr to <4 x float>*
-  %1 = load <4 x float>* %0, align 8
+  %1 = load <4 x float>, <4 x float>* %0, align 8
   %2 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %1, i8 1)
   ret <8 x float> %2
 }
diff --git a/test/CodeGen/X86/avx-vperm2x128.ll b/test/CodeGen/X86/avx-vperm2x128.ll
index 7ca5939fa74a..10ed079a264e 100644
--- a/test/CodeGen/X86/avx-vperm2x128.ll
+++ b/test/CodeGen/X86/avx-vperm2x128.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX1
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX2
 
 define <8 x float> @A(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
 ; ALL-LABEL: A:
@@ -160,8 +160,8 @@ define <16 x i16> @E5i(<16 x i16>* %a, <16 x i16>* %b) nounwind uwtable readnone
 ; AVX2-NEXT:    vinserti128 $1, %xmm0, %ymm1, %ymm0
 ; AVX2-NEXT:    retq
 entry:
-  %c = load <16 x i16>* %a
-  %d = load <16 x i16>* %b
+  %c = load <16 x i16>, <16 x i16>* %a
+  %d = load <16 x i16>, <16 x i16>* %b
   %c2 = add <16 x i16> %c, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %shuffle = shufflevector <16 x i16> %c2, <16 x i16> %d, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <16 x i16> %shuffle
@@ -261,3 +261,94 @@ entry:
   %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 12, i32 undef, i32 15>
   ret <8 x float> %shuffle
 }
+
+;; Test zero mask generation. 
+;; PR22984: https://llvm.org/bugs/show_bug.cgi?id=22984
+;; Prefer xor+vblendpd over vperm2f128 because that has better performance.
+
+define <4 x double> @vperm2z_0x08(<4 x double> %a) {
+; ALL-LABEL: vperm2z_0x08:
+; ALL:       # BB#0:
+; ALL-NEXT:    vperm2f128 $40, %ymm0, %ymm0, %ymm0
+; ALL-NEXT:    retq
+  %s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
+  ret <4 x double> %s
+}
+
+define <4 x double> @vperm2z_0x18(<4 x double> %a) {
+; ALL-LABEL: vperm2z_0x18:
+; ALL:       # BB#0:
+; ALL-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
+; ALL-NEXT:    vblendpd $12, %ymm0, %ymm1, %ymm0
+; ALL-NEXT:    retq
+  %s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+  ret <4 x double> %s
+}
+
+define <4 x double> @vperm2z_0x28(<4 x double> %a) {
+; ALL-LABEL: vperm2z_0x28:
+; ALL:       # BB#0:
+; ALL-NEXT:    vperm2f128 $40, %ymm0, %ymm0, %ymm0
+; ALL-NEXT:    retq
+  %s = shufflevector <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x double> %a, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+  ret <4 x double> %s
+}
+
+define <4 x double> @vperm2z_0x38(<4 x double> %a) {
+; ALL-LABEL: vperm2z_0x38:
+; ALL:       # BB#0:
+; ALL-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
+; ALL-NEXT:    vblendpd $12, %ymm0, %ymm1, %ymm0
+; ALL-NEXT:    retq
+  %s = shufflevector <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x double> %a, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+  ret <4 x double> %s
+}
+
+define <4 x double> @vperm2z_0x80(<4 x double> %a) {
+; ALL-LABEL: vperm2z_0x80:
+; ALL:       # BB#0:
+; ALL-NEXT:    vperm2f128 $128, %ymm0, %ymm0, %ymm0
+; ALL-NEXT:    retq
+  %s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+  ret <4 x double> %s
+}
+
+define <4 x double> @vperm2z_0x81(<4 x double> %a) {
+; ALL-LABEL: vperm2z_0x81:
+; ALL:       # BB#0:
+; ALL-NEXT:    vperm2f128 $129, %ymm0, %ymm0, %ymm0
+; ALL-NEXT:    retq
+  %s = shufflevector <4 x double> %a, <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
+  ret <4 x double> %s
+}
+
+define <4 x double> @vperm2z_0x82(<4 x double> %a) {
+; ALL-LABEL: vperm2z_0x82:
+; ALL:       # BB#0:
+; ALL-NEXT:    vperm2f128 $128, %ymm0, %ymm0, %ymm0
+; ALL-NEXT:    retq
+  %s = shufflevector <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x double> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
+  ret <4 x double> %s
+}
+
+define <4 x double> @vperm2z_0x83(<4 x double> %a) {
+; ALL-LABEL: vperm2z_0x83:
+; ALL:       # BB#0:
+; ALL-NEXT:    vperm2f128 $129, %ymm0, %ymm0, %ymm0
+; ALL-NEXT:    retq
+  %s = shufflevector <4 x double> <double 0.0, double 0.0, double undef, double undef>, <4 x double> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
+  ret <4 x double> %s
+}
+
+;; With AVX2 select the integer version of the instruction. Use an add to force the domain selection.
+
+define <4 x i64> @vperm2z_int_0x83(<4 x i64> %a, <4 x i64> %b) {
+; ALL-LABEL: vperm2z_int_0x83:
+; ALL:       # BB#0:
+; AVX1:    vperm2f128 $129, %ymm0, %ymm0, %ymm0
+; AVX2:    vperm2i128 $129, %ymm0, %ymm0, %ymm0
+  %s = shufflevector <4 x i64> <i64 0, i64 0, i64 undef, i64 undef>, <4 x i64> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
+  %c = add <4 x i64> %b, %s
+  ret <4 x i64> %c
+}
+
diff --git a/test/CodeGen/X86/avx-vzeroupper.ll b/test/CodeGen/X86/avx-vzeroupper.ll
index a2163a254e14..a16dc70e81c6 100644
--- a/test/CodeGen/X86/avx-vzeroupper.ll
+++ b/test/CodeGen/X86/avx-vzeroupper.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
+; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s
 
 declare i32 @foo()
 declare <4 x float> @do_sse(<4 x float>)
@@ -24,7 +24,7 @@ entry:
 ; CHECK: _test01
 define <8 x float> @test01(<4 x float> %a, <4 x float> %b, <8 x float> %c) nounwind uwtable ssp {
 entry:
-  %tmp = load <4 x float>* @x, align 16
+  %tmp = load <4 x float>, <4 x float>* @x, align 16
   ; CHECK: vzeroupper
   ; CHECK-NEXT: callq _do_sse
   %call = tail call <4 x float> @do_sse(<4 x float> %tmp) nounwind
@@ -73,7 +73,7 @@ for.body:
   %call5 = tail call <4 x float> @do_sse(<4 x float> %c.017) nounwind
   ; CHECK-NEXT: callq _do_sse
   %call7 = tail call <4 x float> @do_sse(<4 x float> %call5) nounwind
-  %tmp11 = load <8 x float>* @g, align 32
+  %tmp11 = load <8 x float>, <8 x float>* @g, align 32
   %0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %tmp11, i8 1) nounwind
   ; CHECK: vzeroupper
   ; CHECK-NEXT: callq _do_sse
diff --git a/test/CodeGen/X86/avx.ll b/test/CodeGen/X86/avx.ll
index cba6d98f5a84..f71ec5c10e69 100644
--- a/test/CodeGen/X86/avx.ll
+++ b/test/CodeGen/X86/avx.ll
@@ -34,7 +34,7 @@ define <4 x float> @insertps_from_vector_load(<4 x float> %a, <4 x float>* nocap
 ; CHECK-NOT: mov
 ; CHECK: insertps    $48
 ; CHECK-NEXT: ret
-  %1 = load <4 x float>* %pb, align 16
+  %1 = load <4 x float>, <4 x float>* %pb, align 16
   %2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 48)
   ret <4 x float> %2
 }
@@ -48,7 +48,7 @@ define <4 x float> @insertps_from_vector_load_offset(<4 x float> %a, <4 x float>
 ;; Try to match a bit more of the instr, since we need the load's offset.
 ; CHECK: insertps    $96, 4(%{{...}}), %
 ; CHECK-NEXT: ret
-  %1 = load <4 x float>* %pb, align 16
+  %1 = load <4 x float>, <4 x float>* %pb, align 16
   %2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 96)
   ret <4 x float> %2
 }
@@ -60,10 +60,10 @@ define <4 x float> @insertps_from_vector_load_offset_2(<4 x float> %a, <4 x floa
 ; X32: movl    8(%esp), %ecx
 ; CHECK-NOT: mov
 ;; Try to match a bit more of the instr, since we need the load's offset.
-; CHECK: vinsertps    $-64, 12(%{{...}},%{{...}}), %
+; CHECK: vinsertps    $192, 12(%{{...}},%{{...}}), %
 ; CHECK-NEXT: ret
-  %1 = getelementptr inbounds <4 x float>* %pb, i64 %index
-  %2 = load <4 x float>* %1, align 16
+  %1 = getelementptr inbounds <4 x float>, <4 x float>* %pb, i64 %index
+  %2 = load <4 x float>, <4 x float>* %1, align 16
   %3 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %2, i32 192)
   ret <4 x float> %3
 }
@@ -76,8 +76,8 @@ define <4 x float> @insertps_from_broadcast_loadf32(<4 x float> %a, float* nocap
 ; CHECK-NOT: mov
 ; CHECK: insertps    $48
 ; CHECK-NEXT: ret
-  %1 = getelementptr inbounds float* %fb, i64 %index
-  %2 = load float* %1, align 4
+  %1 = getelementptr inbounds float, float* %fb, i64 %index
+  %2 = load float, float* %1, align 4
   %3 = insertelement <4 x float> undef, float %2, i32 0
   %4 = insertelement <4 x float> %3, float %2, i32 1
   %5 = insertelement <4 x float> %4, float %2, i32 2
@@ -93,7 +93,7 @@ define <4 x float> @insertps_from_broadcast_loadv4f32(<4 x float> %a, <4 x float
 ; CHECK-NOT: mov
 ; CHECK: insertps    $48
 ; CHECK-NEXT: ret
-  %1 = load <4 x float>* %b, align 4
+  %1 = load <4 x float>, <4 x float>* %b, align 4
   %2 = extractelement <4 x float> %1, i32 0
   %3 = insertelement <4 x float> undef, float %2, i32 0
   %4 = insertelement <4 x float> %3, float %2, i32 1
@@ -119,8 +119,8 @@ define <4 x float> @insertps_from_broadcast_multiple_use(<4 x float> %a, <4 x fl
 ; CHECK: vaddps
 ; CHECK: vaddps
 ; CHECK-NEXT: ret
-  %1 = getelementptr inbounds float* %fb, i64 %index
-  %2 = load float* %1, align 4
+  %1 = getelementptr inbounds float, float* %fb, i64 %index
+  %2 = load float, float* %1, align 4
   %3 = insertelement <4 x float> undef, float %2, i32 0
   %4 = insertelement <4 x float> %3, float %2, i32 1
   %5 = insertelement <4 x float> %4, float %2, i32 2
diff --git a/test/CodeGen/X86/avx1-logical-load-folding.ll b/test/CodeGen/X86/avx1-logical-load-folding.ll
index 32301b1bf9e6..90e00c965391 100644
--- a/test/CodeGen/X86/avx1-logical-load-folding.ll
+++ b/test/CodeGen/X86/avx1-logical-load-folding.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-apple-macosx10.9.0"
 ; Function Attrs: nounwind ssp uwtable
 define void @test1(float* %A, float* %C) #0 {
   %tmp1 = bitcast float* %A to <8 x float>*
-  %tmp2 = load <8 x float>* %tmp1, align 32
+  %tmp2 = load <8 x float>, <8 x float>* %tmp1, align 32
   %tmp3 = bitcast <8 x float> %tmp2 to <8 x i32>
   %tmp4 = and <8 x i32> %tmp3, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
   %tmp5 = bitcast <8 x i32> %tmp4 to <8 x float>
@@ -20,7 +20,7 @@ define void @test1(float* %A, float* %C) #0 {
 ; Function Attrs: nounwind ssp uwtable
 define void @test2(float* %A, float* %C) #0 {
   %tmp1 = bitcast float* %A to <8 x float>*
-  %tmp2 = load <8 x float>* %tmp1, align 32
+  %tmp2 = load <8 x float>, <8 x float>* %tmp1, align 32
   %tmp3 = bitcast <8 x float> %tmp2 to <8 x i32>
   %tmp4 = or <8 x i32> %tmp3, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
   %tmp5 = bitcast <8 x i32> %tmp4 to <8 x float>
@@ -34,7 +34,7 @@ define void @test2(float* %A, float* %C) #0 {
 ; Function Attrs: nounwind ssp uwtable
 define void @test3(float* %A, float* %C) #0 {
   %tmp1 = bitcast float* %A to <8 x float>*
-  %tmp2 = load <8 x float>* %tmp1, align 32
+  %tmp2 = load <8 x float>, <8 x float>* %tmp1, align 32
   %tmp3 = bitcast <8 x float> %tmp2 to <8 x i32>
   %tmp4 = xor <8 x i32> %tmp3, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
   %tmp5 = bitcast <8 x i32> %tmp4 to <8 x float>
@@ -47,7 +47,7 @@ define void @test3(float* %A, float* %C) #0 {
 
 define void @test4(float* %A, float* %C) #0 {
   %tmp1 = bitcast float* %A to <8 x float>*
-  %tmp2 = load <8 x float>* %tmp1, align 32
+  %tmp2 = load <8 x float>, <8 x float>* %tmp1, align 32
   %tmp3 = bitcast <8 x float> %tmp2 to <8 x i32>
   %tmp4 = xor <8 x i32> %tmp3, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
   %tmp5 = and <8 x i32> %tmp4, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
diff --git a/test/CodeGen/X86/avx1-stack-reload-folding.ll b/test/CodeGen/X86/avx1-stack-reload-folding.ll
deleted file mode 100644
index 54c192583d6e..000000000000
--- a/test/CodeGen/X86/avx1-stack-reload-folding.ll
+++ /dev/null
@@ -1,83 +0,0 @@
-; RUN: llc -O3 -disable-peephole -mcpu=corei7-avx -mattr=+avx < %s | FileCheck %s
-
-target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
-target triple = "x86_64-unknown-unknown"
-
-; Stack reload folding tests - we use the 'big vectors' pattern to guarantee spilling to stack.
-;
-; Many of these tests are primarily to check memory folding with specific instructions. Using a basic
-; load/cvt/store pattern to test for this would mean that it wouldn't be the memory folding code thats
-; being tested - the load-execute version of the instruction from the tables would be matched instead.
-
-define void @stack_fold_vmulpd(<64 x double>* %a, <64 x double>* %b, <64 x double>* %c) {
-  ;CHECK-LABEL: stack_fold_vmulpd
-  ;CHECK:       vmulpd {{[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
-
-  %1 = load <64 x double>* %a
-  %2 = load <64 x double>* %b
-  %3 = fadd <64 x double> %1, %2
-  %4 = fsub <64 x double> %1, %2
-  %5 = fmul <64 x double> %3, %4
-  store <64 x double> %5, <64 x double>* %c
-  ret void
-}
-
-define void @stack_fold_cvtdq2ps(<128 x i32>* %a, <128 x i32>* %b, <128 x float>* %c) {
-  ;CHECK-LABEL: stack_fold_cvtdq2ps
-  ;CHECK:   vcvtdq2ps {{[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
-
-  %1 = load <128 x i32>* %a
-  %2 = load <128 x i32>* %b
-  %3 = and <128 x i32> %1, %2
-  %4 = xor <128 x i32> %1, %2
-  %5 = sitofp <128 x i32> %3 to <128 x float>
-  %6 = sitofp <128 x i32> %4 to <128 x float>
-  %7 = fadd <128 x float> %5, %6
-  store <128 x float> %7, <128 x float>* %c
-  ret void
-}
-
-define void @stack_fold_cvtpd2ps(<128 x double>* %a, <128 x double>* %b, <128 x float>* %c) {
-  ;CHECK-LABEL: stack_fold_cvtpd2ps
-  ;CHECK:   vcvtpd2psy {{[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
-
-  %1 = load <128 x double>* %a
-  %2 = load <128 x double>* %b
-  %3 = fadd <128 x double> %1, %2
-  %4 = fsub <128 x double> %1, %2
-  %5 = fptrunc <128 x double> %3 to <128 x float>
-  %6 = fptrunc <128 x double> %4 to <128 x float>
-  %7 = fadd <128 x float> %5, %6
-  store <128 x float> %7, <128 x float>* %c
-  ret void
-}
-
-define void @stack_fold_cvttpd2dq(<64 x double>* %a, <64 x double>* %b, <64 x i32>* %c) #0 {
-  ;CHECK-LABEL: stack_fold_cvttpd2dq
-  ;CHECK:  vcvttpd2dqy {{[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
-
-  %1 = load <64 x double>* %a
-  %2 = load <64 x double>* %b
-  %3 = fadd <64 x double> %1, %2
-  %4 = fsub <64 x double> %1, %2
-  %5 = fptosi <64 x double> %3 to <64 x i32>
-  %6 = fptosi <64 x double> %4 to <64 x i32>
-  %7 = or <64 x i32> %5, %6
-  store <64 x i32> %7, <64 x i32>* %c
-  ret void
-}
-
-define void @stack_fold_cvttps2dq(<128 x float>* %a, <128 x float>* %b, <128 x i32>* %c) #0 {
-  ;CHECK-LABEL: stack_fold_cvttps2dq
-  ;CHECK:   vcvttps2dq {{[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
-
-  %1 = load <128 x float>* %a
-  %2 = load <128 x float>* %b
-  %3 = fadd <128 x float> %1, %2
-  %4 = fsub <128 x float> %1, %2
-  %5 = fptosi <128 x float> %3 to <128 x i32>
-  %6 = fptosi <128 x float> %4 to <128 x i32>
-  %7 = or <128 x i32> %5, %6
-  store <128 x i32> %7, <128 x i32>* %c
-  ret void
-}
diff --git a/test/CodeGen/X86/avx2-arith.ll b/test/CodeGen/X86/avx2-arith.ll
index 72bdd9d04729..a205be1c0cd6 100644
--- a/test/CodeGen/X86/avx2-arith.ll
+++ b/test/CodeGen/X86/avx2-arith.ll
@@ -60,6 +60,49 @@ define <16 x i16> @test_vpmullw(<16 x i16> %i, <16 x i16> %j) nounwind readnone
   ret <16 x i16> %x
 }
 
+; CHECK: mul-v16i8
+; CHECK:       # BB#0:
+; CHECK-NEXT:  vpmovsxbw %xmm1, %ymm1
+; CHECK-NEXT:  vpmovsxbw %xmm0, %ymm0
+; CHECK-NEXT:  vpmullw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:  vextracti128 $1, %ymm0, %xmm1
+; CHECK-NEXT:  vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
+; CHECK-NEXT:  vpshufb %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:  vpshufb %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:  vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT:  vzeroupper
+; CHECK-NEXT:  retq
+define <16 x i8> @mul-v16i8(<16 x i8> %i, <16 x i8> %j) nounwind readnone {
+  %x = mul <16 x i8> %i, %j
+  ret <16 x i8> %x
+}
+
+; CHECK: mul-v32i8
+; CHECK:       # BB#0:
+; CHECK-NEXT:  vextracti128 $1, %ymm1, %xmm2
+; CHECK-NEXT:  vpmovsxbw %xmm2, %ymm2
+; CHECK-NEXT:  vextracti128 $1, %ymm0, %xmm3
+; CHECK-NEXT:  vpmovsxbw %xmm3, %ymm3
+; CHECK-NEXT:  vpmullw %ymm2, %ymm3, %ymm2
+; CHECK-NEXT:  vextracti128 $1, %ymm2, %xmm3
+; CHECK-NEXT:  vmovdqa {{.*#+}} xmm4 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
+; CHECK-NEXT:  vpshufb %xmm4, %xmm3, %xmm3
+; CHECK-NEXT:  vpshufb %xmm4, %xmm2, %xmm2
+; CHECK-NEXT:  vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
+; CHECK-NEXT:  vpmovsxbw %xmm1, %ymm1
+; CHECK-NEXT:  vpmovsxbw %xmm0, %ymm0
+; CHECK-NEXT:  vpmullw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:  vextracti128 $1, %ymm0, %xmm1
+; CHECK-NEXT:  vpshufb %xmm4, %xmm1, %xmm1
+; CHECK-NEXT:  vpshufb %xmm4, %xmm0, %xmm0
+; CHECK-NEXT:  vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT:  vinserti128 $1, %xmm2, %ymm0, %ymm0
+; CHECK-NEXT:  retq
+define <32 x i8> @mul-v32i8(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
+  %x = mul <32 x i8> %i, %j
+  ret <32 x i8> %x
+}
+
 ; CHECK: mul-v4i64
 ; CHECK: vpmuludq %ymm
 ; CHECK-NEXT: vpsrlq $32, %ymm
diff --git a/test/CodeGen/X86/avx2-conversions.ll b/test/CodeGen/X86/avx2-conversions.ll
index f49718e4c8b6..9b6d5aa5eeae 100755
--- a/test/CodeGen/X86/avx2-conversions.ll
+++ b/test/CodeGen/X86/avx2-conversions.ll
@@ -84,7 +84,7 @@ define <16 x i16> @sext_16i8_16i16(<16 x i8> %z) {
 ; CHECK-LABEL: trunc_16i16_16i8:
 ; CHECK: vpshufb
 ; CHECK: vpshufb
-; CHECK: vpor
+; CHECK: vpunpcklqdq
 ; CHECK: ret
 define <16 x i8> @trunc_16i16_16i8(<16 x i16> %z) {
   %t = trunc <16 x i16> %z to <16 x i8>
@@ -95,7 +95,7 @@ define <16 x i8> @trunc_16i16_16i8(<16 x i16> %z) {
 ; CHECK: vpmovsxdq (%r{{[^,]*}}), %ymm{{.*}}
 ; CHECK: ret 
 define <4 x i64> @load_sext_test1(<4 x i32> *%ptr) {
- %X = load <4 x i32>* %ptr
+ %X = load <4 x i32>, <4 x i32>* %ptr
  %Y = sext <4 x i32> %X to <4 x i64>
  ret <4 x i64>%Y
 }
@@ -104,7 +104,7 @@ define <4 x i64> @load_sext_test1(<4 x i32> *%ptr) {
 ; CHECK: vpmovsxbq (%r{{[^,]*}}), %ymm{{.*}}
 ; CHECK: ret 
 define <4 x i64> @load_sext_test2(<4 x i8> *%ptr) {
- %X = load <4 x i8>* %ptr
+ %X = load <4 x i8>, <4 x i8>* %ptr
  %Y = sext <4 x i8> %X to <4 x i64>
  ret <4 x i64>%Y
 }
@@ -113,7 +113,7 @@ define <4 x i64> @load_sext_test2(<4 x i8> *%ptr) {
 ; CHECK: vpmovsxwq (%r{{[^,]*}}), %ymm{{.*}}
 ; CHECK: ret 
 define <4 x i64> @load_sext_test3(<4 x i16> *%ptr) {
- %X = load <4 x i16>* %ptr
+ %X = load <4 x i16>, <4 x i16>* %ptr
  %Y = sext <4 x i16> %X to <4 x i64>
  ret <4 x i64>%Y
 }
@@ -122,7 +122,7 @@ define <4 x i64> @load_sext_test3(<4 x i16> *%ptr) {
 ; CHECK: vpmovsxwd (%r{{[^,]*}}), %ymm{{.*}}
 ; CHECK: ret 
 define <8 x i32> @load_sext_test4(<8 x i16> *%ptr) {
- %X = load <8 x i16>* %ptr
+ %X = load <8 x i16>, <8 x i16>* %ptr
  %Y = sext <8 x i16> %X to <8 x i32>
  ret <8 x i32>%Y
 }
@@ -131,7 +131,7 @@ define <8 x i32> @load_sext_test4(<8 x i16> *%ptr) {
 ; CHECK: vpmovsxbd (%r{{[^,]*}}), %ymm{{.*}}
 ; CHECK: ret 
 define <8 x i32> @load_sext_test5(<8 x i8> *%ptr) {
- %X = load <8 x i8>* %ptr
+ %X = load <8 x i8>, <8 x i8>* %ptr
  %Y = sext <8 x i8> %X to <8 x i32>
  ret <8 x i32>%Y
 }
diff --git a/test/CodeGen/X86/avx2-gather.ll b/test/CodeGen/X86/avx2-gather.ll
index a9ac0258975a..91fa20bc0af4 100644
--- a/test/CodeGen/X86/avx2-gather.ll
+++ b/test/CodeGen/X86/avx2-gather.ll
@@ -32,3 +32,30 @@ define <2 x double> @test_x86_avx2_gather_d_pd(i8* %a1,
 ; CHECK: vgatherdpd
 ; CHECK: vmovapd
 ; CHECK: ret
+
+declare <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float>, i8*,
+                      <8 x i32>, <8 x float>, i8) nounwind readonly
+
+define <8 x float> @test_x86_avx2_gather_d_ps_256(i8* %a1,
+                     <8 x i32> %idx, <8 x float> %mask) {
+  %res = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef,
+                            i8* %a1, <8 x i32> %idx, <8 x float> %mask, i8 4) ;
+  ret <8 x float> %res
+}
+; CHECK-LABEL: @test_x86_avx2_gather_d_ps_256
+; CHECK: vgatherdps %ymm
+; CHECK: ret
+
+declare <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double>, i8*,
+                      <4 x i32>, <4 x double>, i8) nounwind readonly
+
+define <4 x double> @test_x86_avx2_gather_d_pd_256(i8* %a1,
+                     <4 x i32> %idx, <4 x double> %mask) {
+  %res = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> undef,
+                            i8* %a1, <4 x i32> %idx, <4 x double> %mask, i8 8) ;
+  ret <4 x double> %res
+}
+
+; CHECK-LABEL: test_x86_avx2_gather_d_pd_256
+; CHECK: vgatherdpd %ymm
+; CHECK: ret
diff --git a/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll b/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll
index ac2c73bb9321..a30d8371775c 100644
--- a/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll
+++ b/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=core-avx2 -mattr=avx2 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mattr=avx2 | FileCheck %s
 
 define <16 x i16> @test_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) {
   ; CHECK: vpblendw
@@ -31,3 +31,55 @@ define <16 x i16> @test_x86_avx2_mpsadbw(<32 x i8> %a0, <32 x i8> %a1) {
 }
 declare <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8>, <32 x i8>, i32) nounwind readnone
 
+
+define <4 x i64> @test_x86_avx2_psll_dq_bs(<4 x i64> %a0) {
+  ; CHECK: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8],zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24]
+  %res = call <4 x i64> @llvm.x86.avx2.psll.dq.bs(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
+  ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.psll.dq.bs(<4 x i64>, i32) nounwind readnone
+
+
+define <4 x i64> @test_x86_avx2_psrl_dq_bs(<4 x i64> %a0) {
+  ; CHECK: vpsrldq {{.*#+}} ymm0 = ymm0[7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,ymm0[23,24,25,26,27,28,29,30,31],zero,zero,zero,zero,zero,zero,zero
+  %res = call <4 x i64> @llvm.x86.avx2.psrl.dq.bs(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
+  ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.psrl.dq.bs(<4 x i64>, i32) nounwind readnone
+
+
+define <4 x i64> @test_x86_avx2_psll_dq(<4 x i64> %a0) {
+  ; CHECK: vpslldq {{.*#+}} ymm0 = zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14],zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]
+  %res = call <4 x i64> @llvm.x86.avx2.psll.dq(<4 x i64> %a0, i32 8) ; <<4 x i64>> [#uses=1]
+  ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.psll.dq(<4 x i64>, i32) nounwind readnone
+
+
+define <4 x i64> @test_x86_avx2_psrl_dq(<4 x i64> %a0) {
+  ; CHECK: vpsrldq {{.*#+}} ymm0 = ymm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero,ymm0[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],zero
+  %res = call <4 x i64> @llvm.x86.avx2.psrl.dq(<4 x i64> %a0, i32 8) ; <<4 x i64>> [#uses=1]
+  ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.psrl.dq(<4 x i64>, i32) nounwind readnone
+
+
+define <2 x i64> @test_x86_avx2_vextracti128(<4 x i64> %a0) {
+; CHECK-LABEL:    test_x86_avx2_vextracti128:
+; CHECK:          vextracti128
+
+  %res = call <2 x i64> @llvm.x86.avx2.vextracti128(<4 x i64> %a0, i8 7)
+  ret <2 x i64> %res
+}
+declare <2 x i64> @llvm.x86.avx2.vextracti128(<4 x i64>, i8) nounwind readnone
+
+
+define <4 x i64> @test_x86_avx2_vinserti128(<4 x i64> %a0, <2 x i64> %a1) {
+; CHECK-LABEL:    test_x86_avx2_vinserti128:
+; CHECK:          vinserti128
+
+  %res = call <4 x i64> @llvm.x86.avx2.vinserti128(<4 x i64> %a0, <2 x i64> %a1, i8 7)
+  ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.vinserti128(<4 x i64>, <2 x i64>, i8) nounwind readnone
+
diff --git a/test/CodeGen/X86/avx2-intrinsics-x86.ll b/test/CodeGen/X86/avx2-intrinsics-x86.ll
index ca5ab3723c11..5b607afef91c 100644
--- a/test/CodeGen/X86/avx2-intrinsics-x86.ll
+++ b/test/CodeGen/X86/avx2-intrinsics-x86.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=core-avx2 -mattr=avx2 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mattr=avx2 | FileCheck %s
 
 define <16 x i16> @test_x86_avx2_packssdw(<8 x i32> %a0, <8 x i32> %a1) {
   ; CHECK: vpackssdw
@@ -160,22 +160,6 @@ define <8 x i32> @test_x86_avx2_psll_d(<8 x i32> %a0, <4 x i32> %a1) {
 declare <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32>, <4 x i32>) nounwind readnone
 
 
-define <4 x i64> @test_x86_avx2_psll_dq(<4 x i64> %a0) {
-  ; CHECK: vpslldq {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
-  %res = call <4 x i64> @llvm.x86.avx2.psll.dq(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
-  ret <4 x i64> %res
-}
-declare <4 x i64> @llvm.x86.avx2.psll.dq(<4 x i64>, i32) nounwind readnone
-
-
-define <4 x i64> @test_x86_avx2_psll_dq_bs(<4 x i64> %a0) {
-  ; CHECK: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8],zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24]
-  %res = call <4 x i64> @llvm.x86.avx2.psll.dq.bs(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
-  ret <4 x i64> %res
-}
-declare <4 x i64> @llvm.x86.avx2.psll.dq.bs(<4 x i64>, i32) nounwind readnone
-
-
 define <4 x i64> @test_x86_avx2_psll_q(<4 x i64> %a0, <2 x i64> %a1) {
   ; CHECK: vpsllq
   %res = call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1]
@@ -256,22 +240,6 @@ define <8 x i32> @test_x86_avx2_psrl_d(<8 x i32> %a0, <4 x i32> %a1) {
 declare <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32>, <4 x i32>) nounwind readnone
 
 
-define <4 x i64> @test_x86_avx2_psrl_dq(<4 x i64> %a0) {
-  ; CHECK: vpsrldq {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
-  %res = call <4 x i64> @llvm.x86.avx2.psrl.dq(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
-  ret <4 x i64> %res
-}
-declare <4 x i64> @llvm.x86.avx2.psrl.dq(<4 x i64>, i32) nounwind readnone
-
-
-define <4 x i64> @test_x86_avx2_psrl_dq_bs(<4 x i64> %a0) {
-  ; CHECK: vpsrldq {{.*#+}} ymm0 = ymm0[7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,ymm0[23,24,25,26,27,28,29,30,31],zero,zero,zero,zero,zero,zero,zero
-  %res = call <4 x i64> @llvm.x86.avx2.psrl.dq.bs(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
-  ret <4 x i64> %res
-}
-declare <4 x i64> @llvm.x86.avx2.psrl.dq.bs(<4 x i64>, i32) nounwind readnone
-
-
 define <4 x i64> @test_x86_avx2_psrl_q(<4 x i64> %a0, <2 x i64> %a1) {
   ; CHECK: vpsrlq
   %res = call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1]
@@ -673,13 +641,6 @@ define <4 x i64> @test_x86_avx2_pmul.dq(<8 x i32> %a0, <8 x i32> %a1) {
 declare <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32>, <8 x i32>) nounwind readnone
 
 
-define <4 x i64> @test_x86_avx2_vbroadcasti128(i8* %a0) {
-  ; CHECK: vbroadcasti128
-  %res = call <4 x i64> @llvm.x86.avx2.vbroadcasti128(i8* %a0) ; <<4 x i64>> [#uses=1]
-  ret <4 x i64> %res
-}
-declare <4 x i64> @llvm.x86.avx2.vbroadcasti128(i8*) nounwind readonly
-
 define <4 x double> @test_x86_avx2_vbroadcast_sd_pd_256(<2 x double> %a0) {
   ; CHECK: vbroadcastsd
   %res = call <4 x double> @llvm.x86.avx2.vbroadcast.sd.pd.256(<2 x double> %a0) ; <<4 x double>> [#uses=1]
@@ -814,22 +775,6 @@ define <4 x i64> @test_x86_avx2_vperm2i128(<4 x i64> %a0, <4 x i64> %a1) {
 declare <4 x i64> @llvm.x86.avx2.vperm2i128(<4 x i64>, <4 x i64>, i8) nounwind readonly
 
 
-define <2 x i64> @test_x86_avx2_vextracti128(<4 x i64> %a0) {
-  ; CHECK: vextracti128
-  %res = call <2 x i64> @llvm.x86.avx2.vextracti128(<4 x i64> %a0, i8 7) ; <<2 x i64>> [#uses=1]
-  ret <2 x i64> %res
-}
-declare <2 x i64> @llvm.x86.avx2.vextracti128(<4 x i64>, i8) nounwind readnone
-
-
-define <4 x i64> @test_x86_avx2_vinserti128(<4 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vinserti128
-  %res = call <4 x i64> @llvm.x86.avx2.vinserti128(<4 x i64> %a0, <2 x i64> %a1, i8 7) ; <<4 x i64>> [#uses=1]
-  ret <4 x i64> %res
-}
-declare <4 x i64> @llvm.x86.avx2.vinserti128(<4 x i64>, <2 x i64>, i8) nounwind readnone
-
-
 define <2 x i64> @test_x86_avx2_maskload_q(i8* %a0, <2 x i64> %a1) {
   ; CHECK: vpmaskmovq
   %res = call <2 x i64> @llvm.x86.avx2.maskload.q(i8* %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
diff --git a/test/CodeGen/X86/avx2-pmovx-256-old-shuffle.ll b/test/CodeGen/X86/avx2-pmovx-256-old-shuffle.ll
deleted file mode 100644
index 44eb42adb9f8..000000000000
--- a/test/CodeGen/X86/avx2-pmovx-256-old-shuffle.ll
+++ /dev/null
@@ -1,29 +0,0 @@
-; RUN: llc < %s -x86-experimental-vector-shuffle-lowering=false -mattr=+avx2 | FileCheck %s
-
-target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
-target triple = "x86_64-apple-darwin"
-
-; PR21876
-; The old shuffle lowering sometimes generates VZEXT nodes with both input
-; and output same-sized types, here 256-bits.  For instance, a v8i8 to v8i32
-; zero-extend would become a (v8i32 (VZEXT v32i8)) node, which can't happen
-; otherwise.  The companion commit r223996 added those patterns temporarily.
-; This test, along with the VR256 for AVX2 PMOVXrr instructions, should be
-; removed once the old vector shuffle lowering goes away.
-
-define void @test_avx2_pmovx_256(<8 x i8>* %tmp64, <8 x float>* %tmp75) {
-; CHECK-LABEL: test_avx2_pmovx_256
-; We really don't care about the generated code.
-; CHECK: vpmovzxbd
-; CHECK: vpbroadcastd
-; CHECK: vpand
-; CHECK: vcvtdq2ps
-; CHECK: vmovups
-; CHECK: vzeroupper
-; CHECK: retq
-
-  %wide.load458 = load <8 x i8>* %tmp64, align 1
-  %tmp68 = uitofp <8 x i8> %wide.load458 to <8 x float>
-  store <8 x float> %tmp68, <8 x float>* %tmp75, align 4
-  ret void
-}
diff --git a/test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll b/test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll
index 7301b7cbfc4e..6bd6a5041d41 100644
--- a/test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll
+++ b/test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll
@@ -3,7 +3,7 @@
 define <16 x i16> @test_lvm_x86_avx2_pmovsxbw(<16 x i8>* %a) {
 ; CHECK-LABEL: test_lvm_x86_avx2_pmovsxbw
 ; CHECK: vpmovsxbw (%rdi), %ymm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8> %1)
   ret <16 x i16> %2
 }
@@ -11,7 +11,7 @@ define <16 x i16> @test_lvm_x86_avx2_pmovsxbw(<16 x i8>* %a) {
 define <8 x i32> @test_llvm_x86_avx2_pmovsxbd(<16 x i8>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovsxbd
 ; CHECK: vpmovsxbd (%rdi), %ymm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <8 x i32> @llvm.x86.avx2.pmovsxbd(<16 x i8> %1)
   ret <8 x i32> %2
 }
@@ -19,7 +19,7 @@ define <8 x i32> @test_llvm_x86_avx2_pmovsxbd(<16 x i8>* %a) {
 define <4 x i64> @test_llvm_x86_avx2_pmovsxbq(<16 x i8>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovsxbq
 ; CHECK: vpmovsxbq (%rdi), %ymm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <4 x i64> @llvm.x86.avx2.pmovsxbq(<16 x i8> %1)
   ret <4 x i64> %2
 }
@@ -27,7 +27,7 @@ define <4 x i64> @test_llvm_x86_avx2_pmovsxbq(<16 x i8>* %a) {
 define <8 x i32> @test_llvm_x86_avx2_pmovsxwd(<8 x i16>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovsxwd
 ; CHECK: vpmovsxwd (%rdi), %ymm0
-  %1 = load <8 x i16>* %a, align 1
+  %1 = load <8 x i16>, <8 x i16>* %a, align 1
   %2 = call <8 x i32> @llvm.x86.avx2.pmovsxwd(<8 x i16> %1)
   ret <8 x i32> %2
 }
@@ -35,7 +35,7 @@ define <8 x i32> @test_llvm_x86_avx2_pmovsxwd(<8 x i16>* %a) {
 define <4 x i64> @test_llvm_x86_avx2_pmovsxwq(<8 x i16>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovsxwq
 ; CHECK: vpmovsxwq (%rdi), %ymm0
-  %1 = load <8 x i16>* %a, align 1
+  %1 = load <8 x i16>, <8 x i16>* %a, align 1
   %2 = call <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16> %1)
   ret <4 x i64> %2
 }
@@ -43,7 +43,7 @@ define <4 x i64> @test_llvm_x86_avx2_pmovsxwq(<8 x i16>* %a) {
 define <4 x i64> @test_llvm_x86_avx2_pmovsxdq(<4 x i32>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovsxdq
 ; CHECK: vpmovsxdq (%rdi), %ymm0
-  %1 = load <4 x i32>* %a, align 1
+  %1 = load <4 x i32>, <4 x i32>* %a, align 1
   %2 = call <4 x i64> @llvm.x86.avx2.pmovsxdq(<4 x i32> %1)
   ret <4 x i64> %2
 }
@@ -51,7 +51,7 @@ define <4 x i64> @test_llvm_x86_avx2_pmovsxdq(<4 x i32>* %a) {
 define <16 x i16> @test_lvm_x86_avx2_pmovzxbw(<16 x i8>* %a) {
 ; CHECK-LABEL: test_lvm_x86_avx2_pmovzxbw
 ; CHECK: vpmovzxbw (%rdi), %ymm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8> %1)
   ret <16 x i16> %2
 }
@@ -59,7 +59,7 @@ define <16 x i16> @test_lvm_x86_avx2_pmovzxbw(<16 x i8>* %a) {
 define <8 x i32> @test_llvm_x86_avx2_pmovzxbd(<16 x i8>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovzxbd
 ; CHECK: vpmovzxbd (%rdi), %ymm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8> %1)
   ret <8 x i32> %2
 }
@@ -67,7 +67,7 @@ define <8 x i32> @test_llvm_x86_avx2_pmovzxbd(<16 x i8>* %a) {
 define <4 x i64> @test_llvm_x86_avx2_pmovzxbq(<16 x i8>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovzxbq
 ; CHECK: vpmovzxbq (%rdi), %ymm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8> %1)
   ret <4 x i64> %2
 }
@@ -75,7 +75,7 @@ define <4 x i64> @test_llvm_x86_avx2_pmovzxbq(<16 x i8>* %a) {
 define <8 x i32> @test_llvm_x86_avx2_pmovzxwd(<8 x i16>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovzxwd
 ; CHECK: vpmovzxwd (%rdi), %ymm0
-  %1 = load <8 x i16>* %a, align 1
+  %1 = load <8 x i16>, <8 x i16>* %a, align 1
   %2 = call <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16> %1)
   ret <8 x i32> %2
 }
@@ -83,7 +83,7 @@ define <8 x i32> @test_llvm_x86_avx2_pmovzxwd(<8 x i16>* %a) {
 define <4 x i64> @test_llvm_x86_avx2_pmovzxwq(<8 x i16>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovzxwq
 ; CHECK: vpmovzxwq (%rdi), %ymm0
-  %1 = load <8 x i16>* %a, align 1
+  %1 = load <8 x i16>, <8 x i16>* %a, align 1
   %2 = call <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16> %1)
   ret <4 x i64> %2
 }
@@ -91,7 +91,7 @@ define <4 x i64> @test_llvm_x86_avx2_pmovzxwq(<8 x i16>* %a) {
 define <4 x i64> @test_llvm_x86_avx2_pmovzxdq(<4 x i32>* %a) {
 ; CHECK-LABEL: test_llvm_x86_avx2_pmovzxdq
 ; CHECK: vpmovzxdq (%rdi), %ymm0
-  %1 = load <4 x i32>* %a, align 1
+  %1 = load <4 x i32>, <4 x i32>* %a, align 1
   %2 = call <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32> %1)
   ret <4 x i64> %2
 }
diff --git a/test/CodeGen/X86/avx2-shift.ll b/test/CodeGen/X86/avx2-shift.ll
index 025d52ede0f4..5adbb2ef6651 100644
--- a/test/CodeGen/X86/avx2-shift.ll
+++ b/test/CodeGen/X86/avx2-shift.ll
@@ -130,7 +130,7 @@ define <16 x i16> @vshift07(<16 x i16> %a) nounwind readnone {
 ; CHECK: vpsravd (%
 ; CHECK: ret
 define <4 x i32> @variable_sra0_load(<4 x i32> %x, <4 x i32>* %y) {
-  %y1 = load <4 x i32>* %y
+  %y1 = load <4 x i32>, <4 x i32>* %y
   %k = ashr <4 x i32> %x, %y1
   ret <4 x i32> %k
 }
@@ -139,7 +139,7 @@ define <4 x i32> @variable_sra0_load(<4 x i32> %x, <4 x i32>* %y) {
 ; CHECK: vpsravd (%
 ; CHECK: ret
 define <8 x i32> @variable_sra1_load(<8 x i32> %x, <8 x i32>* %y) {
-  %y1 = load <8 x i32>* %y
+  %y1 = load <8 x i32>, <8 x i32>* %y
   %k = ashr <8 x i32> %x, %y1
   ret <8 x i32> %k
 }
@@ -148,7 +148,7 @@ define <8 x i32> @variable_sra1_load(<8 x i32> %x, <8 x i32>* %y) {
 ; CHECK: vpsllvd (%
 ; CHECK: ret
 define <4 x i32> @variable_shl0_load(<4 x i32> %x, <4 x i32>* %y) {
-  %y1 = load <4 x i32>* %y
+  %y1 = load <4 x i32>, <4 x i32>* %y
   %k = shl <4 x i32> %x, %y1
   ret <4 x i32> %k
 }
@@ -156,7 +156,7 @@ define <4 x i32> @variable_shl0_load(<4 x i32> %x, <4 x i32>* %y) {
 ; CHECK: vpsllvd (%
 ; CHECK: ret
 define <8 x i32> @variable_shl1_load(<8 x i32> %x, <8 x i32>* %y) {
-  %y1 = load <8 x i32>* %y
+  %y1 = load <8 x i32>, <8 x i32>* %y
   %k = shl <8 x i32> %x, %y1
   ret <8 x i32> %k
 }
@@ -164,7 +164,7 @@ define <8 x i32> @variable_shl1_load(<8 x i32> %x, <8 x i32>* %y) {
 ; CHECK: vpsllvq (%
 ; CHECK: ret
 define <2 x i64> @variable_shl2_load(<2 x i64> %x, <2 x i64>* %y) {
-  %y1 = load <2 x i64>* %y
+  %y1 = load <2 x i64>, <2 x i64>* %y
   %k = shl <2 x i64> %x, %y1
   ret <2 x i64> %k
 }
@@ -172,7 +172,7 @@ define <2 x i64> @variable_shl2_load(<2 x i64> %x, <2 x i64>* %y) {
 ; CHECK: vpsllvq (%
 ; CHECK: ret
 define <4 x i64> @variable_shl3_load(<4 x i64> %x, <4 x i64>* %y) {
-  %y1 = load <4 x i64>* %y
+  %y1 = load <4 x i64>, <4 x i64>* %y
   %k = shl <4 x i64> %x, %y1
   ret <4 x i64> %k
 }
@@ -180,7 +180,7 @@ define <4 x i64> @variable_shl3_load(<4 x i64> %x, <4 x i64>* %y) {
 ; CHECK: vpsrlvd (%
 ; CHECK: ret
 define <4 x i32> @variable_srl0_load(<4 x i32> %x, <4 x i32>* %y) {
-  %y1 = load <4 x i32>* %y
+  %y1 = load <4 x i32>, <4 x i32>* %y
   %k = lshr <4 x i32> %x, %y1
   ret <4 x i32> %k
 }
@@ -188,7 +188,7 @@ define <4 x i32> @variable_srl0_load(<4 x i32> %x, <4 x i32>* %y) {
 ; CHECK: vpsrlvd (%
 ; CHECK: ret
 define <8 x i32> @variable_srl1_load(<8 x i32> %x, <8 x i32>* %y) {
-  %y1 = load <8 x i32>* %y
+  %y1 = load <8 x i32>, <8 x i32>* %y
   %k = lshr <8 x i32> %x, %y1
   ret <8 x i32> %k
 }
@@ -196,7 +196,7 @@ define <8 x i32> @variable_srl1_load(<8 x i32> %x, <8 x i32>* %y) {
 ; CHECK: vpsrlvq (%
 ; CHECK: ret
 define <2 x i64> @variable_srl2_load(<2 x i64> %x, <2 x i64>* %y) {
-  %y1 = load <2 x i64>* %y
+  %y1 = load <2 x i64>, <2 x i64>* %y
   %k = lshr <2 x i64> %x, %y1
   ret <2 x i64> %k
 }
@@ -204,7 +204,7 @@ define <2 x i64> @variable_srl2_load(<2 x i64> %x, <2 x i64>* %y) {
 ; CHECK: vpsrlvq (%
 ; CHECK: ret
 define <4 x i64> @variable_srl3_load(<4 x i64> %x, <4 x i64>* %y) {
-  %y1 = load <4 x i64>* %y
+  %y1 = load <4 x i64>, <4 x i64>* %y
   %k = lshr <4 x i64> %x, %y1
   ret <4 x i64> %k
 }
diff --git a/test/CodeGen/X86/avx2-vbroadcast.ll b/test/CodeGen/X86/avx2-vbroadcast.ll
index 924c06eba768..94dcdcabdd33 100644
--- a/test/CodeGen/X86/avx2-vbroadcast.ll
+++ b/test/CodeGen/X86/avx2-vbroadcast.ll
@@ -3,7 +3,7 @@
 ; CHECK: vpbroadcastb (%
 define <16 x i8> @BB16(i8* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load i8* %ptr, align 4
+  %q = load i8, i8* %ptr, align 4
   %q0 = insertelement <16 x i8> undef, i8 %q, i32 0
   %q1 = insertelement <16 x i8> %q0, i8 %q, i32 1
   %q2 = insertelement <16 x i8> %q1, i8 %q, i32 2
@@ -25,7 +25,7 @@ entry:
 ; CHECK: vpbroadcastb (%
 define <32 x i8> @BB32(i8* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load i8* %ptr, align 4
+  %q = load i8, i8* %ptr, align 4
   %q0 = insertelement <32 x i8> undef, i8 %q, i32 0
   %q1 = insertelement <32 x i8> %q0, i8 %q, i32 1
   %q2 = insertelement <32 x i8> %q1, i8 %q, i32 2
@@ -65,7 +65,7 @@ entry:
 
 define <8 x i16> @W16(i16* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load i16* %ptr, align 4
+  %q = load i16, i16* %ptr, align 4
   %q0 = insertelement <8 x i16> undef, i16 %q, i32 0
   %q1 = insertelement <8 x i16> %q0, i16 %q, i32 1
   %q2 = insertelement <8 x i16> %q1, i16 %q, i32 2
@@ -79,7 +79,7 @@ entry:
 ; CHECK: vpbroadcastw (%
 define <16 x i16> @WW16(i16* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load i16* %ptr, align 4
+  %q = load i16, i16* %ptr, align 4
   %q0 = insertelement <16 x i16> undef, i16 %q, i32 0
   %q1 = insertelement <16 x i16> %q0, i16 %q, i32 1
   %q2 = insertelement <16 x i16> %q1, i16 %q, i32 2
@@ -101,7 +101,7 @@ entry:
 ; CHECK: vbroadcastss (%
 define <4 x i32> @D32(i32* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load i32* %ptr, align 4
+  %q = load i32, i32* %ptr, align 4
   %q0 = insertelement <4 x i32> undef, i32 %q, i32 0
   %q1 = insertelement <4 x i32> %q0, i32 %q, i32 1
   %q2 = insertelement <4 x i32> %q1, i32 %q, i32 2
@@ -111,7 +111,7 @@ entry:
 ; CHECK: vbroadcastss (%
 define <8 x i32> @DD32(i32* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load i32* %ptr, align 4
+  %q = load i32, i32* %ptr, align 4
   %q0 = insertelement <8 x i32> undef, i32 %q, i32 0
   %q1 = insertelement <8 x i32> %q0, i32 %q, i32 1
   %q2 = insertelement <8 x i32> %q1, i32 %q, i32 2
@@ -125,7 +125,7 @@ entry:
 ; CHECK: vpbroadcastq (%
 define <2 x i64> @Q64(i64* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load i64* %ptr, align 4
+  %q = load i64, i64* %ptr, align 4
   %q0 = insertelement <2 x i64> undef, i64 %q, i32 0
   %q1 = insertelement <2 x i64> %q0, i64 %q, i32 1
   ret <2 x i64> %q1
@@ -133,7 +133,7 @@ entry:
 ; CHECK: vbroadcastsd (%
 define <4 x i64> @QQ64(i64* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load i64* %ptr, align 4
+  %q = load i64, i64* %ptr, align 4
   %q0 = insertelement <4 x i64> undef, i64 %q, i32 0
   %q1 = insertelement <4 x i64> %q0, i64 %q, i32 1
   %q2 = insertelement <4 x i64> %q1, i64 %q, i32 2
@@ -145,7 +145,7 @@ entry:
 ; this used to crash
 define <2 x double> @I(double* %ptr) nounwind uwtable readnone ssp {
 entry:
-  %q = load double* %ptr, align 4
+  %q = load double, double* %ptr, align 4
   %vecinit.i = insertelement <2 x double> undef, double %q, i32 0
   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %q, i32 1
   ret <2 x double> %vecinit2.i
@@ -317,7 +317,7 @@ define   <4 x double> @_inreg4xdouble(<4 x double> %a) {
 }
 
 ;CHECK-LABEL: _inreg2xdouble:
-;CHECK: vunpcklpd
+;CHECK: vmovddup
 ;CHECK: ret
 define   <2 x double> @_inreg2xdouble(<2 x double> %a) {
   %b = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> zeroinitializer
@@ -431,8 +431,8 @@ eintry:
   %__b.addr.i = alloca <2 x i64>, align 16
   %vCr = alloca <2 x i64>, align 16
   store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
-  %tmp = load <2 x i64>* %vCr, align 16
-  %tmp2 = load i8* %cV_R.addr, align 4
+  %tmp = load <2 x i64>, <2 x i64>* %vCr, align 16
+  %tmp2 = load i8, i8* %cV_R.addr, align 4
   %splat.splatinsert = insertelement <16 x i8> undef, i8 %tmp2, i32 0
   %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
   %tmp3 = bitcast <16 x i8> %splat.splat to <2 x i64>
@@ -450,8 +450,8 @@ eintry:
   %__b.addr.i = alloca <4 x i64>, align 16
   %vCr = alloca <4 x i64>, align 16
   store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
-  %tmp = load <4 x i64>* %vCr, align 16
-  %tmp2 = load i8* %cV_R.addr, align 4
+  %tmp = load <4 x i64>, <4 x i64>* %vCr, align 16
+  %tmp2 = load i8, i8* %cV_R.addr, align 4
   %splat.splatinsert = insertelement <32 x i8> undef, i8 %tmp2, i32 0
   %splat.splat = shufflevector <32 x i8> %splat.splatinsert, <32 x i8> undef, <32 x i32> zeroinitializer
   %tmp3 = bitcast <32 x i8> %splat.splat to <4 x i64>
@@ -469,8 +469,8 @@ entry:
   %__b.addr.i = alloca <2 x i64>, align 16
   %vCr = alloca <2 x i64>, align 16
   store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
-  %tmp = load <2 x i64>* %vCr, align 16
-  %tmp2 = load i16* %cV_R.addr, align 4
+  %tmp = load <2 x i64>, <2 x i64>* %vCr, align 16
+  %tmp2 = load i16, i16* %cV_R.addr, align 4
   %splat.splatinsert = insertelement <8 x i16> undef, i16 %tmp2, i32 0
   %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
   %tmp3 = bitcast <8 x i16> %splat.splat to <2 x i64>
@@ -488,8 +488,8 @@ eintry:
   %__b.addr.i = alloca <4 x i64>, align 16
   %vCr = alloca <4 x i64>, align 16
   store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
-  %tmp = load <4 x i64>* %vCr, align 16
-  %tmp2 = load i16* %cV_R.addr, align 4
+  %tmp = load <4 x i64>, <4 x i64>* %vCr, align 16
+  %tmp2 = load i16, i16* %cV_R.addr, align 4
   %splat.splatinsert = insertelement <16 x i16> undef, i16 %tmp2, i32 0
   %splat.splat = shufflevector <16 x i16> %splat.splatinsert, <16 x i16> undef, <16 x i32> zeroinitializer
   %tmp3 = bitcast <16 x i16> %splat.splat to <4 x i64>
@@ -507,8 +507,8 @@ entry:
   %__b.addr.i = alloca <2 x i64>, align 16
   %vCr = alloca <2 x i64>, align 16
   store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
-  %tmp = load <2 x i64>* %vCr, align 16
-  %tmp2 = load i32* %cV_R.addr, align 4
+  %tmp = load <2 x i64>, <2 x i64>* %vCr, align 16
+  %tmp2 = load i32, i32* %cV_R.addr, align 4
   %splat.splatinsert = insertelement <4 x i32> undef, i32 %tmp2, i32 0
   %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
   %tmp3 = bitcast <4 x i32> %splat.splat to <2 x i64>
@@ -526,8 +526,8 @@ eintry:
   %__b.addr.i = alloca <4 x i64>, align 16
   %vCr = alloca <4 x i64>, align 16
   store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
-  %tmp = load <4 x i64>* %vCr, align 16
-  %tmp2 = load i32* %cV_R.addr, align 4
+  %tmp = load <4 x i64>, <4 x i64>* %vCr, align 16
+  %tmp2 = load i32, i32* %cV_R.addr, align 4
   %splat.splatinsert = insertelement <8 x i32> undef, i32 %tmp2, i32 0
   %splat.splat = shufflevector <8 x i32> %splat.splatinsert, <8 x i32> undef, <8 x i32> zeroinitializer
   %tmp3 = bitcast <8 x i32> %splat.splat to <4 x i64>
@@ -545,8 +545,8 @@ entry:
   %__b.addr.i = alloca <2 x i64>, align 16
   %vCr = alloca <2 x i64>, align 16
   store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
-  %tmp = load <2 x i64>* %vCr, align 16
-  %tmp2 = load i64* %cV_R.addr, align 4
+  %tmp = load <2 x i64>, <2 x i64>* %vCr, align 16
+  %tmp2 = load i64, i64* %cV_R.addr, align 4
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %tmp2, i32 0
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
@@ -563,8 +563,8 @@ eintry:
   %__b.addr.i = alloca <4 x i64>, align 16
   %vCr = alloca <4 x i64>, align 16
   store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
-  %tmp = load <4 x i64>* %vCr, align 16
-  %tmp2 = load i64* %cV_R.addr, align 4
+  %tmp = load <4 x i64>, <4 x i64>* %vCr, align 16
+  %tmp2 = load i64, i64* %cV_R.addr, align 4
   %splat.splatinsert = insertelement <4 x i64> undef, i64 %tmp2, i32 0
   %splat.splat = shufflevector <4 x i64> %splat.splatinsert, <4 x i64> undef, <4 x i32> zeroinitializer
   store <4 x i64> %tmp, <4 x i64>* %__a.addr.i, align 16
diff --git a/test/CodeGen/X86/avx2-vector-shifts.ll b/test/CodeGen/X86/avx2-vector-shifts.ll
index e355301dd051..8aae90c3c03d 100644
--- a/test/CodeGen/X86/avx2-vector-shifts.ll
+++ b/test/CodeGen/X86/avx2-vector-shifts.ll
@@ -266,3 +266,94 @@ define <4 x i32> @srl_trunc_and_v4i64(<4 x i32> %x, <4 x i64> %y) nounwind {
   %sra = lshr <4 x i32> %x, %trunc
   ret <4 x i32> %sra
 }
+
+;
+; Vectorized byte shifts
+;
+
+define <8 x i16> @shl_8i16(<8 x i16> %r, <8 x i16> %a) nounwind {
+; CHECK-LABEL:  shl_8i16
+; CHECK:        vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
+; CHECK-NEXT:   vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; CHECK-NEXT:   vpsllvd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:   vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,20,21,24,25,28,29],zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT:   vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
+; CHECK:        retq
+  %shl = shl <8 x i16> %r, %a
+  ret <8 x i16> %shl
+}
+
+define <16 x i16> @shl_16i16(<16 x i16> %r, <16 x i16> %a) nounwind {
+; CHECK-LABEL:  shl_16i16
+; CHECK:        vpxor %ymm2, %ymm2, %ymm2
+; CHECK-NEXT:   vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
+; CHECK-NEXT:   vpunpckhwd {{.*#+}} ymm4 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15]
+; CHECK-NEXT:   vpsllvd %ymm3, %ymm4, %ymm3
+; CHECK-NEXT:   vpsrld $16, %ymm3, %ymm3
+; CHECK-NEXT:   vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
+; CHECK-NEXT:   vpunpcklwd {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11]
+; CHECK-NEXT:   vpsllvd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:   vpsrld $16, %ymm0, %ymm0
+; CHECK-NEXT:   vpackusdw %ymm3, %ymm0, %ymm0
+; CHECK-NEXT:   retq
+  %shl = shl <16 x i16> %r, %a
+  ret <16 x i16> %shl
+}
+
+define <8 x i16> @ashr_8i16(<8 x i16> %r, <8 x i16> %a) nounwind {
+; CHECK-LABEL:  ashr_8i16
+; CHECK:        vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
+; CHECK-NEXT:   vpmovsxwd %xmm0, %ymm0
+; CHECK-NEXT:   vpsravd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:   vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,20,21,24,25,28,29],zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT:   vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
+; CHECK:        retq
+  %ashr = ashr <8 x i16> %r, %a
+  ret <8 x i16> %ashr
+}
+
+define <16 x i16> @ashr_16i16(<16 x i16> %r, <16 x i16> %a) nounwind {
+; CHECK-LABEL:  ashr_16i16
+; CHECK:        vpxor %ymm2, %ymm2, %ymm2
+; CHECK-NEXT:   vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
+; CHECK-NEXT:   vpunpckhwd {{.*#+}} ymm4 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15]
+; CHECK-NEXT:   vpsravd %ymm3, %ymm4, %ymm3
+; CHECK-NEXT:   vpsrld $16, %ymm3, %ymm3
+; CHECK-NEXT:   vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
+; CHECK-NEXT:   vpunpcklwd {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11]
+; CHECK-NEXT:   vpsravd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:   vpsrld $16, %ymm0, %ymm0
+; CHECK-NEXT:   vpackusdw %ymm3, %ymm0, %ymm0
+; CHECK-NEXT:   retq
+  %ashr = ashr <16 x i16> %r, %a
+  ret <16 x i16> %ashr
+}
+
+define <8 x i16> @lshr_8i16(<8 x i16> %r, <8 x i16> %a) nounwind {
+; CHECK-LABEL:  lshr_8i16
+; CHECK:        vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
+; CHECK-NEXT:   vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; CHECK-NEXT:   vpsrlvd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:   vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,20,21,24,25,28,29],zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT:   vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
+; CHECK:        retq
+  %lshr = lshr <8 x i16> %r, %a
+  ret <8 x i16> %lshr
+}
+
+define <16 x i16> @lshr_16i16(<16 x i16> %r, <16 x i16> %a) nounwind {
+; CHECK-LABEL:  lshr_16i16
+; CHECK:        vpxor %ymm2, %ymm2, %ymm2
+; CHECK-NEXT:   vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
+; CHECK-NEXT:   vpunpckhwd {{.*#+}} ymm4 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15]
+; CHECK-NEXT:   vpsrlvd %ymm3, %ymm4, %ymm3
+; CHECK-NEXT:   vpsrld $16, %ymm3, %ymm3
+; CHECK-NEXT:   vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
+; CHECK-NEXT:   vpunpcklwd {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11]
+; CHECK-NEXT:   vpsrlvd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:   vpsrld $16, %ymm0, %ymm0
+; CHECK-NEXT:   vpackusdw %ymm3, %ymm0, %ymm0
+; CHECK-NEXT:   retq
+  %lshr = lshr <16 x i16> %r, %a
+  ret <16 x i16> %lshr
+}
diff --git a/test/CodeGen/X86/avx512-arith.ll b/test/CodeGen/X86/avx512-arith.ll
index 94b08215b896..1ecd1007905a 100644
--- a/test/CodeGen/X86/avx512-arith.ll
+++ b/test/CodeGen/X86/avx512-arith.ll
@@ -56,7 +56,7 @@ define <8 x double> @subpd512fold(<8 x double> %y, <8 x double>* %x) {
 ; CHECK-NEXT:    vsubpd (%rdi), %zmm0, %zmm0
 ; CHECK-NEXT:    retq
 entry:
-  %tmp2 = load <8 x double>* %x, align 8
+  %tmp2 = load <8 x double>, <8 x double>* %x, align 8
   %sub.i = fsub <8 x double> %y, %tmp2
   ret <8 x double> %sub.i
 }
@@ -77,7 +77,7 @@ define <16 x float> @subps512fold(<16 x float> %y, <16 x float>* %x) {
 ; CHECK-NEXT:    vsubps (%rdi), %zmm0, %zmm0
 ; CHECK-NEXT:    retq
 entry:
-  %tmp2 = load <16 x float>* %x, align 4
+  %tmp2 = load <16 x float>, <16 x float>* %x, align 4
   %sub.i = fsub <16 x float> %y, %tmp2
   ret <16 x float> %sub.i
 }
@@ -193,7 +193,7 @@ define <8 x i64> @vpaddq_fold_test(<8 x i64> %i, <8 x i64>* %j) nounwind {
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    vpaddq (%rdi), %zmm0, %zmm0
 ; CHECK-NEXT:    retq
-  %tmp = load <8 x i64>* %j, align 4
+  %tmp = load <8 x i64>, <8 x i64>* %j, align 4
   %x = add <8 x i64> %i, %tmp
   ret <8 x i64> %x
 }
@@ -212,7 +212,7 @@ define <8 x i64> @vpaddq_broadcast2_test(<8 x i64> %i, i64* %j) nounwind {
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    vpaddq (%rdi){1to8}, %zmm0, %zmm0
 ; CHECK-NEXT:    retq
-  %tmp = load i64* %j
+  %tmp = load i64, i64* %j
   %j.0 = insertelement <8 x i64> undef, i64 %tmp, i32 0
   %j.1 = insertelement <8 x i64> %j.0, i64 %tmp, i32 1
   %j.2 = insertelement <8 x i64> %j.1, i64 %tmp, i32 2
@@ -239,7 +239,7 @@ define <16 x i32> @vpaddd_fold_test(<16 x i32> %i, <16 x i32>* %j) nounwind {
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    vpaddd (%rdi), %zmm0, %zmm0
 ; CHECK-NEXT:    retq
-  %tmp = load <16 x i32>* %j, align 4
+  %tmp = load <16 x i32>, <16 x i32>* %j, align 4
   %x = add <16 x i32> %i, %tmp
   ret <16 x i32> %x
 }
@@ -287,7 +287,7 @@ define <16 x i32> @vpaddd_mask_fold_test(<16 x i32> %i, <16 x i32>* %j.ptr, <16
 ; CHECK-NEXT:    vpaddd (%rdi), %zmm0, %zmm0 {%k1}
 ; CHECK-NEXT:    retq
   %mask = icmp ne <16 x i32> %mask1, zeroinitializer
-  %j = load <16 x i32>* %j.ptr
+  %j = load <16 x i32>, <16 x i32>* %j.ptr
   %x = add <16 x i32> %i, %j
   %r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %i
   ret <16 x i32> %r
@@ -314,7 +314,7 @@ define <16 x i32> @vpaddd_maskz_fold_test(<16 x i32> %i, <16 x i32>* %j.ptr, <16
 ; CHECK-NEXT:    vpaddd (%rdi), %zmm0, %zmm0 {%k1} {z}
 ; CHECK-NEXT:    retq
   %mask = icmp ne <16 x i32> %mask1, zeroinitializer
-  %j = load <16 x i32>* %j.ptr
+  %j = load <16 x i32>, <16 x i32>* %j.ptr
   %x = add <16 x i32> %i, %j
   %r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> zeroinitializer
   ret <16 x i32> %r
@@ -445,7 +445,7 @@ define <16 x i32> @andd512fold(<16 x i32> %y, <16 x i32>* %x) {
 ; CHECK-NEXT:    vpandd (%rdi), %zmm0, %zmm0
 ; CHECK-NEXT:    retq
 entry:
-  %a = load <16 x i32>* %x, align 4
+  %a = load <16 x i32>, <16 x i32>* %x, align 4
   %b = and <16 x i32> %y, %a
   ret <16 x i32> %b
 }
@@ -456,7 +456,7 @@ define <8 x i64> @andqbrst(<8 x i64> %p1, i64* %ap) {
 ; CHECK-NEXT:    vpandq (%rdi){1to8}, %zmm0, %zmm0
 ; CHECK-NEXT:    retq
 entry:
-  %a = load i64* %ap, align 8
+  %a = load i64, i64* %ap, align 8
   %b = insertelement <8 x i64> undef, i64 %a, i32 0
   %c = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
   %d = and <8 x i64> %p1, %c
@@ -593,7 +593,7 @@ define <8 x double> @test_mask_fold_vaddpd(<8 x double> %dst, <8 x double> %i,
                                      <8 x double>* %j,  <8 x i64> %mask1)
                                      nounwind {
   %mask = icmp ne <8 x i64> %mask1, zeroinitializer
-  %tmp = load <8 x double>* %j, align 8
+  %tmp = load <8 x double>, <8 x double>* %j, align 8
   %x = fadd <8 x double> %i, %tmp
   %r = select <8 x i1> %mask, <8 x double> %x, <8 x double> %dst
   ret <8 x double> %r
@@ -605,7 +605,7 @@ define <8 x double> @test_mask_fold_vaddpd(<8 x double> %dst, <8 x double> %i,
 define <8 x double> @test_maskz_fold_vaddpd(<8 x double> %i, <8 x double>* %j,
                                       <8 x i64> %mask1) nounwind {
   %mask = icmp ne <8 x i64> %mask1, zeroinitializer
-  %tmp = load <8 x double>* %j, align 8
+  %tmp = load <8 x double>, <8 x double>* %j, align 8
   %x = fadd <8 x double> %i, %tmp
   %r = select <8 x i1> %mask, <8 x double> %x, <8 x double> zeroinitializer
   ret <8 x double> %r
@@ -615,7 +615,7 @@ define <8 x double> @test_maskz_fold_vaddpd(<8 x double> %i, <8 x double>* %j,
 ; CHECK: vaddpd (%rdi){1to8}, %zmm{{.*}}
 ; CHECK: ret
 define <8 x double> @test_broadcast_vaddpd(<8 x double> %i, double* %j) nounwind {
-  %tmp = load double* %j
+  %tmp = load double, double* %j
   %b = insertelement <8 x double> undef, double %tmp, i32 0
   %c = shufflevector <8 x double> %b, <8 x double> undef,
                      <8 x i32> zeroinitializer
@@ -629,7 +629,7 @@ define <8 x double> @test_broadcast_vaddpd(<8 x double> %i, double* %j) nounwind
 define <8 x double> @test_mask_broadcast_vaddpd(<8 x double> %dst, <8 x double> %i,
                                       double* %j, <8 x i64> %mask1) nounwind {
   %mask = icmp ne <8 x i64> %mask1, zeroinitializer
-  %tmp = load double* %j
+  %tmp = load double, double* %j
   %b = insertelement <8 x double> undef, double %tmp, i32 0
   %c = shufflevector <8 x double> %b, <8 x double> undef,
                      <8 x i32> zeroinitializer
@@ -644,7 +644,7 @@ define <8 x double> @test_mask_broadcast_vaddpd(<8 x double> %dst, <8 x double>
 define <8 x double> @test_maskz_broadcast_vaddpd(<8 x double> %i, double* %j,
                                        <8 x i64> %mask1) nounwind {
   %mask = icmp ne <8 x i64> %mask1, zeroinitializer
-  %tmp = load double* %j
+  %tmp = load double, double* %j
   %b = insertelement <8 x double> undef, double %tmp, i32 0
   %c = shufflevector <8 x double> %b, <8 x double> undef,
                      <8 x i32> zeroinitializer
diff --git a/test/CodeGen/X86/avx512-bugfix-23634.ll b/test/CodeGen/X86/avx512-bugfix-23634.ll
new file mode 100644
index 000000000000..c31a13ad3114
--- /dev/null
+++ b/test/CodeGen/X86/avx512-bugfix-23634.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; CHECK-LABEL: f_fu
+; CHECK-NOT: vpblend
+; CHECK: vmovdqa32 {{.*}} {%k1}
+
+define void @f_fu(float* %ret, float*  %aa, float %b) {
+allocas:
+  %ptr_cast_for_load = bitcast float* %aa to <16 x float>*
+  %ptr_masked_load.39 = load <16 x float>, <16 x float>* %ptr_cast_for_load, align 4
+  %b_load_to_int32 = fptosi float %b to i32
+  %b_load_to_int32_broadcast_init = insertelement <16 x i32> undef, i32 %b_load_to_int32, i32 0
+  %b_load_to_int32_broadcast = shufflevector <16 x i32> %b_load_to_int32_broadcast_init, <16 x i32> undef, <16 x i32> zeroinitializer
+  %b_to_int32 = fptosi float %b to i32
+  %b_to_int32_broadcast_init = insertelement <16 x i32> undef, i32 %b_to_int32, i32 0
+  %b_to_int32_broadcast = shufflevector <16 x i32> %b_to_int32_broadcast_init, <16 x i32> undef, <16 x i32> zeroinitializer
+
+  %a_load_to_int32 = fptosi <16 x float> %ptr_masked_load.39 to <16 x i32>
+  %div_v019_load_ = sdiv <16 x i32> %b_to_int32_broadcast, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
+
+  %v1.i = select <16 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>, <16 x i32> %a_load_to_int32
+
+  %foo_test = add <16 x i32> %div_v019_load_, %b_load_to_int32_broadcast 
+
+
+  %add_struct_offset_y_struct_offset33_x = add <16 x i32> %foo_test, %v1.i 
+
+  %val = sitofp <16 x i32> %add_struct_offset_y_struct_offset33_x to <16 x float>
+  %ptrcast = bitcast float* %ret to <16 x float>*
+  store <16 x float> %val, <16 x float>* %ptrcast, align 4
+  ret void
+}
\ No newline at end of file
diff --git a/test/CodeGen/X86/avx512-build-vector.ll b/test/CodeGen/X86/avx512-build-vector.ll
index 9e9ad31c916f..8373c6da2619 100644
--- a/test/CodeGen/X86/avx512-build-vector.ll
+++ b/test/CodeGen/X86/avx512-build-vector.ll
@@ -9,7 +9,7 @@ define <16 x i32> @test1(i32* %x) {
 ; CHECK-NEXT:    vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4],ymm1[5,6,7]
 ; CHECK-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
 ; CHECK-NEXT:    retq
-   %y = load i32* %x, align 4
+   %y = load i32, i32* %x, align 4
    %res = insertelement <16 x i32>zeroinitializer, i32 %y, i32 4
    ret <16 x i32>%res
 }
diff --git a/test/CodeGen/X86/avx512-calling-conv.ll b/test/CodeGen/X86/avx512-calling-conv.ll
new file mode 100644
index 000000000000..edb6bef1a4ac
--- /dev/null
+++ b/test/CodeGen/X86/avx512-calling-conv.ll
@@ -0,0 +1,154 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s --check-prefix=KNL
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s --check-prefix=SKX
+; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=knl | FileCheck %s --check-prefix=KNL_X32
+
+; KNL-LABEL: test1
+; KNL: vxorps
+define <16 x i1> @test1() {
+  ret <16 x i1> zeroinitializer
+}
+
+; SKX-LABEL: test2
+; SKX: vpmovb2m
+; SKX: vpmovb2m
+; SKX: kandw
+; SKX: vpmovm2b
+; KNL-LABEL: test2
+; KNL: vpmovsxbd
+; KNL: vpmovsxbd
+; KNL: vpandd
+; KNL: vpmovdb
+define <16 x i1> @test2(<16 x i1>%a, <16 x i1>%b) {
+  %c = and <16 x i1>%a, %b
+  ret <16 x i1> %c
+}
+
+; SKX-LABEL: test3
+; SKX: vpmovw2m
+; SKX: vpmovw2m
+; SKX: kandb
+; SKX: vpmovm2w
+define <8 x i1> @test3(<8 x i1>%a, <8 x i1>%b) {
+  %c = and <8 x i1>%a, %b
+  ret <8 x i1> %c
+}
+
+; SKX-LABEL: test4
+; SKX: vpmovd2m
+; SKX: vpmovd2m
+; SKX: kandw
+; SKX: vpmovm2d
+define <4 x i1> @test4(<4 x i1>%a, <4 x i1>%b) {
+  %c = and <4 x i1>%a, %b
+  ret <4 x i1> %c
+}
+
+; SKX-LABEL: test5
+; SKX: vpcmpgtd
+; SKX: vpmovm2w
+; SKX: call
+; SKX: vpmovzxwd
+declare <8 x i1> @func8xi1(<8 x i1> %a)
+define <8 x i32> @test5(<8 x i32>%a, <8 x i32>%b) {
+  %cmpRes = icmp sgt <8 x i32>%a, %b
+  %resi = call <8 x i1> @func8xi1(<8 x i1> %cmpRes)
+  %res = sext <8 x i1>%resi to <8 x i32>
+  ret <8 x i32> %res
+}
+
+declare <16 x i1> @func16xi1(<16 x i1> %a)
+
+; KNL-LABEL: test6
+; KNL: vpbroadcastd
+; KNL: vpmovdb
+; KNL: call
+; KNL: vpmovzxbd
+; KNL: vpslld  $31, %zmm
+; KNL: vpsrad  $31, %zmm
+define <16 x i32> @test6(<16 x i32>%a, <16 x i32>%b) {
+  %cmpRes = icmp sgt <16 x i32>%a, %b
+  %resi = call <16 x i1> @func16xi1(<16 x i1> %cmpRes)
+  %res = sext <16 x i1>%resi to <16 x i32>
+  ret <16 x i32> %res
+}
+
+declare <4 x i1> @func4xi1(<4 x i1> %a)
+; SKX-LABEL: test7
+; SKX: vpmovm2d
+; SKX: call
+; SKX: vpslld  $31, %xmm
+; SKX: vpsrad  $31, %xmm
+
+define <4 x i32> @test7(<4 x i32>%a, <4 x i32>%b) {
+  %cmpRes = icmp sgt <4 x i32>%a, %b
+  %resi = call <4 x i1> @func4xi1(<4 x i1> %cmpRes)
+  %res = sext <4 x i1>%resi to <4 x i32>
+  ret <4 x i32> %res
+}
+
+; SKX-LABEL: test7a
+; SKX: call
+; SKX: vpmovw2m  %xmm0, %k0
+; SKX: kandb
+define <8 x i1> @test7a(<8 x i32>%a, <8 x i32>%b) {
+  %cmpRes = icmp sgt <8 x i32>%a, %b
+  %resi = call <8 x i1> @func8xi1(<8 x i1> %cmpRes)
+  %res = and <8 x i1>%resi,  <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>
+  ret <8 x i1> %res
+}
+
+
+; KNL_X32-LABEL: test8
+; KNL_X32: testb $1, 4(%esp)
+; KNL_X32:jne
+
+; KNL-LABEL: test8
+; KNL: testb   $1, %dil
+; KNL:jne
+
+define <16 x i8> @test8(<16 x i8> %a1, <16 x i8> %a2, i1 %cond) {
+  %res = select i1 %cond, <16 x i8> %a1, <16 x i8> %a2
+  ret <16 x i8> %res
+}
+
+; KNL-LABEL: test9
+; KNL: vucomisd
+; KNL: setb
+define i1 @test9(double %a, double %b) {
+  %c = fcmp ugt double %a, %b
+  ret i1 %c
+}
+
+; KNL_X32-LABEL: test10
+; KNL_X32: testb $1, 12(%esp)
+; KNL_X32: cmovnel
+
+; KNL-LABEL: test10
+; KNL: testb   $1, %dl
+; KNL: cmovel
+define i32 @test10(i32 %a, i32 %b, i1 %cond) {
+  %c = select i1 %cond, i32 %a, i32 %b
+  ret i32 %c
+}
+
+; KNL-LABEL: test11
+; KNL: cmp
+; KNL: setg
+define i1 @test11(i32 %a, i32 %b) {
+  %c = icmp sgt i32 %a, %b
+  ret i1 %c
+}
+
+; KNL-LABEL: test12
+; KNL: callq _test11
+;; return value in %al
+; KNL: movzbl	%al, %ebx
+; KNL: callq _test10
+; KNL: testb   $1, %bl
+
+define i32 @test12(i32 %a1, i32 %a2, i32 %b1) {
+  %cond = call i1 @test11(i32 %a1, i32 %b1)
+  %res = call i32 @test10(i32 %a1, i32 %a2, i1 %cond)
+  %res1 = select i1 %cond, i32 %res, i32 0
+  ret i32 %res1
+}
\ No newline at end of file
diff --git a/test/CodeGen/X86/avx512-cvt.ll b/test/CodeGen/X86/avx512-cvt.ll
index 2b672a72d539..a211bcd38c9c 100644
--- a/test/CodeGen/X86/avx512-cvt.ll
+++ b/test/CodeGen/X86/avx512-cvt.ll
@@ -87,7 +87,7 @@ define <8 x double> @fpext00(<8 x float> %b) nounwind {
 ; CHECK: ret
 define double @funcA(i64* nocapture %e) {
 entry:
-  %tmp1 = load i64* %e, align 8
+  %tmp1 = load i64, i64* %e, align 8
   %conv = sitofp i64 %tmp1 to double
   ret double %conv
 }
@@ -97,7 +97,7 @@ entry:
 ; CHECK: ret
 define double @funcB(i32* %e) {
 entry:
-  %tmp1 = load i32* %e, align 4
+  %tmp1 = load i32, i32* %e, align 4
   %conv = sitofp i32 %tmp1 to double
   ret double %conv
 }
@@ -107,7 +107,7 @@ entry:
 ; CHECK: ret
 define float @funcC(i32* %e) {
 entry:
-  %tmp1 = load i32* %e, align 4
+  %tmp1 = load i32, i32* %e, align 4
   %conv = sitofp i32 %tmp1 to float
   ret float %conv
 }
@@ -117,7 +117,7 @@ entry:
 ; CHECK: ret
 define float @i64tof32(i64* %e) {
 entry:
-  %tmp1 = load i64* %e, align 8
+  %tmp1 = load i64, i64* %e, align 8
   %conv = sitofp i64 %tmp1 to float
   ret float %conv
 }
@@ -129,7 +129,7 @@ define void @fpext() {
 entry:
   %f = alloca float, align 4
   %d = alloca double, align 8
-  %tmp = load float* %f, align 4
+  %tmp = load float, float* %f, align 4
   %conv = fpext float %tmp to double
   store double %conv, double* %d, align 8
   ret void
@@ -144,7 +144,7 @@ define void @fpround_scalar() nounwind uwtable {
 entry:
   %f = alloca float, align 4
   %d = alloca double, align 8
-  %tmp = load double* %d, align 8
+  %tmp = load double, double* %d, align 8
   %conv = fptrunc double %tmp to float
   store float %conv, float* %f, align 4
   ret void
@@ -308,3 +308,20 @@ define <8 x double> @sitofp_8i1_double(<8 x double> %a) {
   %1 = sitofp <8 x i1> %cmpres to <8 x double>
   ret <8 x double> %1
 }
+
+; CHECK-LABEL: @uitofp_16i8
+; CHECK:  vpmovzxbd  
+; CHECK: vcvtudq2ps
+define <16 x float> @uitofp_16i8(<16 x i8>%a) {
+  %b = uitofp <16 x i8> %a to <16 x float>
+  ret <16 x float>%b
+}
+
+; CHECK-LABEL: @uitofp_16i16
+; CHECK: vpmovzxwd
+; CHECK: vcvtudq2ps
+define <16 x float> @uitofp_16i16(<16 x i16>%a) {
+  %b = uitofp <16 x i16> %a to <16 x float>
+  ret <16 x float>%b
+}
+
diff --git a/test/CodeGen/X86/avx512-fma-intrinsics.ll b/test/CodeGen/X86/avx512-fma-intrinsics.ll
index 116531d5af9e..9814a6108272 100644
--- a/test/CodeGen/X86/avx512-fma-intrinsics.ll
+++ b/test/CodeGen/X86/avx512-fma-intrinsics.ll
@@ -1,50 +1,8 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding | FileCheck %s
 
-define <16 x float> @test_x86_vfmadd_ps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
-  ; CHECK-LABEL: test_x86_vfmadd_ps_z
-  ; CHECK: vfmadd213ps %zmm
-  %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind
-  ret <16 x float> %res
-}
-declare <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone
-
-define <16 x float> @test_mask_vfmadd_ps(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
-  ; CHECK-LABEL: test_mask_vfmadd_ps
-  ; CHECK: vfmadd213ps %zmm
-  %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind
-  ret <16 x float> %res
-}
-
-define <8 x double> @test_x86_vfmadd_pd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
-  ; CHECK-LABEL: test_x86_vfmadd_pd_z
-  ; CHECK: vfmadd213pd %zmm
-  %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind
-  ret <8 x double> %res
-}
-
-define <8 x double> @test_mask_fmadd_pd(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8 %mask) {
-; CHECK-LABEL: test_mask_fmadd_pd:
-; CHECK: vfmadd213pd %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x49,0xa8,0xc2]
-  %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8 %mask, i32 4)
-  ret <8 x double> %res
-}
-
+declare <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
 declare <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
-
-define <16 x float> @test_x86_vfmsubps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
-  ; CHECK-LABEL: test_x86_vfmsubps_z
-  ; CHECK: vfmsub213ps %zmm
-  %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind
-  ret <16 x float> %res
-}
-declare <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone
-
-define <16 x float> @test_mask_vfmsub_ps(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
-  ; CHECK-LABEL: test_mask_vfmsub_ps
-  ; CHECK: vfmsub213ps %zmm
-  %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind
-  ret <16 x float> %res
-}
+declare <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
 
 define <8 x double> @test_x86_vfmsubpd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
   ; CHECK-LABEL: test_x86_vfmsubpd_z
@@ -182,3 +140,283 @@ define <8 x double> @test_mask_vfmsubadd_pd(<8 x double> %a0, <8 x double> %a1,
   ret <8 x double> %res
 }
 
+define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rne(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rne
+  ; CHECK: vfmadd213ps  {rn-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x19,0xa8,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 0) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rtn(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rtn
+  ; CHECK: vfmadd213ps  {rd-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x39,0xa8,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 1) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rtp(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rtp
+  ; CHECK: vfmadd213ps  {ru-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x59,0xa8,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 2) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rtz(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rtz
+  ; CHECK: vfmadd213ps  {rz-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x79,0xa8,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 3) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmadd512_ps_rrb_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_current
+  ; CHECK: vfmadd213ps  %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x49,0xa8,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rne(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rne
+  ; CHECK: vfmadd213ps  {rn-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x18,0xa8,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 0) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rtn(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rtn
+  ; CHECK: vfmadd213ps  {rd-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x38,0xa8,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 1) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rtp(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rtp
+  ; CHECK: vfmadd213ps  {ru-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x58,0xa8,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 2) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rtz(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rtz
+  ; CHECK: vfmadd213ps  {rz-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x78,0xa8,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 3) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_current
+  ; CHECK: vfmadd213ps  %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x48,0xa8,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmsub512_ps_rrb_rne(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrb_rne
+  ; CHECK: vfmsub213ps  {rn-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x19,0xaa,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 0) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmsub512_ps_rrb_rtn(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrb_rtn
+  ; CHECK: vfmsub213ps  {rd-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x39,0xaa,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 1) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmsub512_ps_rrb_rtp(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrb_rtp
+  ; CHECK: vfmsub213ps  {ru-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x59,0xaa,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 2) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmsub512_ps_rrb_rtz(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrb_rtz
+  ; CHECK: vfmsub213ps  {rz-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x79,0xaa,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 3) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmsub512_ps_rrb_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrb_current
+  ; CHECK: vfmsub213ps  %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x49,0xaa,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmsub512_ps_rrbz_rne(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrbz_rne
+  ; CHECK: vfmsub213ps  {rn-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x18,0xaa,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 0) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmsub512_ps_rrbz_rtn(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrbz_rtn
+  ; CHECK: vfmsub213ps  {rd-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x38,0xaa,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 1) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmsub512_ps_rrbz_rtp(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrbz_rtp
+  ; CHECK: vfmsub213ps  {ru-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x58,0xaa,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 2) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmsub512_ps_rrbz_rtz(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrbz_rtz
+  ; CHECK: vfmsub213ps  {rz-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x78,0xaa,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 3) nounwind
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_round_vfmsub512_ps_rrbz_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrbz_current
+  ; CHECK: vfmsub213ps  %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x48,0xaa,0xc2]
+  %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind
+  ret <16 x float> %res
+}
+
+define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rne
+  ; CHECK: vfmadd213pd  {rn-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x19,0xa8,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 0) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rtn
+  ; CHECK: vfmadd213pd  {rd-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x39,0xa8,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 1) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rtp
+  ; CHECK: vfmadd213pd  {ru-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x59,0xa8,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 2) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rtz
+  ; CHECK: vfmadd213pd  {rz-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x79,0xa8,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 3) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfmadd512_pd_rrb_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_current
+  ; CHECK: vfmadd213pd  %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x49,0xa8,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rne
+  ; CHECK: vfmadd213pd  {rn-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x18,0xa8,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 0) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rtn
+  ; CHECK: vfmadd213pd  {rd-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x38,0xa8,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 1) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rtp
+  ; CHECK: vfmadd213pd  {ru-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x58,0xa8,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 2) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rtz
+  ; CHECK: vfmadd213pd  {rz-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x78,0xa8,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 3) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_current
+  ; CHECK: vfmadd213pd  %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x48,0xa8,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind
+  ret <8 x double> %res
+}
+
+
+define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rne
+  ; CHECK: vfnmsub213pd  {rn-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x19,0xae,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 0) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rtn
+  ; CHECK: vfnmsub213pd  {rd-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x39,0xae,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 1) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rtp
+  ; CHECK: vfnmsub213pd  {ru-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x59,0xae,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 2) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rtz
+  ; CHECK: vfnmsub213pd  {rz-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x79,0xae,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 3) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
+  ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_current
+  ; CHECK: vfnmsub213pd  %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x49,0xae,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rne
+  ; CHECK: vfnmsub213pd  {rn-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x18,0xae,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 0) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rtn
+  ; CHECK: vfnmsub213pd  {rd-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x38,0xae,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 1) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rtp
+  ; CHECK: vfnmsub213pd  {ru-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x58,0xae,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 2) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rtz
+  ; CHECK: vfnmsub213pd  {rz-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x78,0xae,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 3) nounwind
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
+  ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_current
+  ; CHECK: vfnmsub213pd  %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x48,0xae,0xc2]
+  %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind
+  ret <8 x double> %res
+}
diff --git a/test/CodeGen/X86/avx512-gather-scatter-intrin.ll b/test/CodeGen/X86/avx512-gather-scatter-intrin.ll
index 20bf7e4a16e0..0e32a1c28067 100644
--- a/test/CodeGen/X86/avx512-gather-scatter-intrin.ll
+++ b/test/CodeGen/X86/avx512-gather-scatter-intrin.ll
@@ -170,7 +170,7 @@ define <8 x float> @gather_mask_qps_execdomain(<8 x i64> %ind, <8 x float> %src,
 ;CHECK: vscatterdpd
 ;CHECK: ret
 define void @scatter_mask_dpd_execdomain(<8 x i32> %ind, <8 x double>* %src, i8 %mask, i8* %base, i8* %stbuf)  {
-  %x = load <8 x double>* %src, align 64 
+  %x = load <8 x double>, <8 x double>* %src, align 64 
   call void @llvm.x86.avx512.scatter.dpd.512 (i8* %stbuf, i8 %mask, <8 x i32>%ind, <8 x double> %x, i32 4)
   ret void
 }
@@ -180,7 +180,7 @@ define void @scatter_mask_dpd_execdomain(<8 x i32> %ind, <8 x double>* %src, i8
 ;CHECK: vscatterqpd
 ;CHECK: ret
 define void @scatter_mask_qpd_execdomain(<8 x i64> %ind, <8 x double>* %src, i8 %mask, i8* %base, i8* %stbuf)  {
-  %x = load <8 x double>* %src, align 64
+  %x = load <8 x double>, <8 x double>* %src, align 64
   call void @llvm.x86.avx512.scatter.qpd.512 (i8* %stbuf, i8 %mask, <8 x i64>%ind, <8 x double> %x, i32 4)
   ret void
 }
@@ -190,7 +190,7 @@ define void @scatter_mask_qpd_execdomain(<8 x i64> %ind, <8 x double>* %src, i8
 ;CHECK: vscatterdps
 ;CHECK: ret
 define void @scatter_mask_dps_execdomain(<16 x i32> %ind, <16 x float>* %src, i16 %mask, i8* %base, i8* %stbuf)  {
-  %x = load <16 x float>* %src, align 64
+  %x = load <16 x float>, <16 x float>* %src, align 64
   call void @llvm.x86.avx512.scatter.dps.512 (i8* %stbuf, i16 %mask, <16 x i32>%ind, <16 x float> %x, i32 4)
   ret void
 }
@@ -200,7 +200,7 @@ define void @scatter_mask_dps_execdomain(<16 x i32> %ind, <16 x float>* %src, i1
 ;CHECK: vscatterqps
 ;CHECK: ret
 define void @scatter_mask_qps_execdomain(<8 x i64> %ind, <8 x float>* %src, i8 %mask, i8* %base, i8* %stbuf)  {
-  %x = load <8 x float>* %src, align 32 
+  %x = load <8 x float>, <8 x float>* %src, align 32 
   call void @llvm.x86.avx512.scatter.qps.512 (i8* %stbuf, i8 %mask, <8 x i64>%ind, <8 x float> %x, i32 4)
   ret void
 }
diff --git a/test/CodeGen/X86/avx512-i1test.ll b/test/CodeGen/X86/avx512-i1test.ll
index 4814314a6442..ba2f49b79427 100755
--- a/test/CodeGen/X86/avx512-i1test.ll
+++ b/test/CodeGen/X86/avx512-i1test.ll
@@ -5,8 +5,8 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 ; CHECK-LABEL: func
-; CHECK: kortestw
-; CHECK: kortestw
+; CHECK: testb
+; CHECK: testb
 define void @func() {
 bb1:
   br i1 undef, label %L_10, label %L_10
@@ -18,7 +18,7 @@ bb56:                                             ; preds = %L_10
   br label %bb33
 
 bb33:                                             ; preds = %bb51, %bb56
-  %r111 = load i64* undef, align 8
+  %r111 = load i64, i64* undef, align 8
   br i1 undef, label %bb51, label %bb35
 
 bb35:                                             ; preds = %bb33
diff --git a/test/CodeGen/X86/avx512-insert-extract.ll b/test/CodeGen/X86/avx512-insert-extract.ll
index eba895ebf565..6f985f0bf3a7 100644
--- a/test/CodeGen/X86/avx512-insert-extract.ll
+++ b/test/CodeGen/X86/avx512-insert-extract.ll
@@ -6,7 +6,7 @@
 ;CHECK: vinsertf32x4
 ;CHECK: ret
 define <16 x float> @test1(<16 x float> %x, float* %br, float %y) nounwind {
-  %rrr = load float* %br
+  %rrr = load float, float* %br
   %rrr2 = insertelement <16 x float> %x, float %rrr, i32 1
   %rrr3 = insertelement <16 x float> %rrr2, float %y, i32 14
   ret <16 x float> %rrr3
@@ -20,7 +20,7 @@ define <16 x float> @test1(<16 x float> %x, float* %br, float %y) nounwind {
 ;SKX: vinsertf64x2 $3
 ;CHECK: ret
 define <8 x double> @test2(<8 x double> %x, double* %br, double %y) nounwind {
-  %rrr = load double* %br
+  %rrr = load double, double* %br
   %rrr2 = insertelement <8 x double> %x, double %rrr, i32 1
   %rrr3 = insertelement <8 x double> %rrr2, double %y, i32 6
   ret <8 x double> %rrr3
@@ -106,7 +106,7 @@ define i32 @test10(<16 x i32> %x, i32 %ind) nounwind {
 ;CHECK: vpcmpltud
 ;CHECK: kshiftlw $11
 ;CHECK: kshiftrw $15
-;CHECK: kortestw
+;CHECK: testb
 ;CHECK: je
 ;CHECK: ret
 ;CHECK: ret
@@ -125,7 +125,7 @@ define <16 x i32> @test11(<16 x i32>%a, <16 x i32>%b) {
 ;CHECK: vpcmpgtq
 ;CHECK: kshiftlw $15
 ;CHECK: kshiftrw $15
-;CHECK: kortestw
+;CHECK: testb
 ;CHECK: ret
 
 define i64 @test12(<16 x i64>%a, <16 x i64>%b, i64 %a1, i64 %b1) {
@@ -137,10 +137,12 @@ define i64 @test12(<16 x i64>%a, <16 x i64>%b, i64 %a1, i64 %b1) {
 }
 
 ;CHECK-LABEL: test13
-;CHECK: cmpl
-;CHECK: sbbl
-;CHECK: orl $65532
-;CHECK: ret
+;CHECK: cmpl    %esi, %edi
+;CHECK: setb    %al
+;CHECK: andl    $1, %eax
+;CHECK: kmovw   %eax, %k0
+;CHECK: movw    $-4
+;CHECK: korw    
 define i16 @test13(i32 %a, i32 %b) {
   %cmp_res = icmp ult i32 %a, %b
   %maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %cmp_res, i32 0
@@ -150,9 +152,12 @@ define i16 @test13(i32 %a, i32 %b) {
 
 ;CHECK-LABEL: test14
 ;CHECK: vpcmpgtq
-;CHECK: kshiftlw $11
-;CHECK: kshiftrw $15
-;CHECK: kortestw
+;KNL: kshiftlw $11
+;KNL: kshiftrw $15
+;KNL: testb
+;SKX: kshiftlb $3
+;SKX: kshiftrb $7
+;SKX: testb
 ;CHECK: ret
 
 define i64 @test14(<8 x i64>%a, <8 x i64>%b, i64 %a1, i64 %b1) {
@@ -164,23 +169,26 @@ define i64 @test14(<8 x i64>%a, <8 x i64>%b, i64 %a1, i64 %b1) {
 }
 
 ;CHECK-LABEL: test15
-;CHECK: kshiftlw
-;CHECK: kmovw
-;CHECK: ret
+;CHECK: movb (%rdi), %al
+;CHECK: andb $1, %al
+;CHECK: movw    $-1, %ax
+;CHECK: cmovew
 define i16 @test15(i1 *%addr) {
-  %x = load i1 * %addr, align 128
+  %x = load i1 , i1 * %addr, align 1
   %x1 = insertelement <16 x i1> undef, i1 %x, i32 10
   %x2 = bitcast <16 x i1>%x1 to i16
   ret i16 %x2
 }
 
 ;CHECK-LABEL: test16
-;CHECK: kshiftlw
-;CHECK: kshiftrw
+;CHECK: movb (%rdi), %al
+;CHECK: andw $1, %ax
+;CHECK: kmovw
+;CHECK: kshiftlw        $10
 ;CHECK: korw
 ;CHECK: ret
 define i16 @test16(i1 *%addr, i16 %a) {
-  %x = load i1 * %addr, align 128
+  %x = load i1 , i1 * %addr, align 128
   %a1 = bitcast i16 %a to <16 x i1>
   %x1 = insertelement <16 x i1> %a1, i1 %x, i32 10
   %x2 = bitcast <16 x i1>%x1 to i16
@@ -188,13 +196,15 @@ define i16 @test16(i1 *%addr, i16 %a) {
 }
 
 ;CHECK-LABEL: test17
-;CHECK: kshiftlw
-;CHECK: kshiftrw
+;KNL: movb (%rdi), %al
+;KNL: andw $1, %ax
+;KNL: kshiftlw $4
 ;KNL: korw
+;SKX: kshiftlb $4
 ;SKX: korb
 ;CHECK: ret
 define i8 @test17(i1 *%addr, i8 %a) {
-  %x = load i1 * %addr, align 128
+  %x = load i1 , i1 * %addr, align 128
   %a1 = bitcast i8 %a to <8 x i1>
   %x1 = insertelement <8 x i1> %a1, i1 %x, i32 4
   %x2 = bitcast <8 x i1>%x1 to i8
diff --git a/test/CodeGen/X86/avx512-intel-ocl.ll b/test/CodeGen/X86/avx512-intel-ocl.ll
new file mode 100644
index 000000000000..2e1b27e4aecf
--- /dev/null
+++ b/test/CodeGen/X86/avx512-intel-ocl.ll
@@ -0,0 +1,105 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=knl | FileCheck -check-prefix=X32 %s
+; RUN: llc < %s -mtriple=i386-pc-win32 -mcpu=knl | FileCheck -check-prefix=X32 %s
+; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=knl | FileCheck -check-prefix=WIN64 %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck -check-prefix=X64 %s
+
+declare <16 x float> @func_float16_ptr(<16 x float>, <16 x float> *)
+declare <16 x float> @func_float16(<16 x float>, <16 x float>)
+declare i32 @func_int(i32, i32)
+
+; WIN64-LABEL: testf16_inp
+; WIN64: vaddps  {{.*}}, {{%zmm[0-1]}}
+; WIN64: leaq    {{.*}}(%rsp), %rcx
+; WIN64: call
+; WIN64: ret
+
+; X32-LABEL: testf16_inp
+; X32: vaddps  {{.*}}, {{%zmm[0-1]}}
+; X32: movl    %eax, (%esp)
+; X32: call
+; X32: ret
+
+; X64-LABEL: testf16_inp
+; X64: vaddps  {{.*}}, {{%zmm[0-1]}}
+; X64: leaq    {{.*}}(%rsp), %rdi
+; X64: call
+; X64: ret
+
+;test calling conventions - input parameters
+define <16 x float> @testf16_inp(<16 x float> %a, <16 x float> %b) nounwind {
+  %y = alloca <16 x float>, align 16
+  %x = fadd <16 x float> %a, %b
+  %1 = call intel_ocl_bicc <16 x float> @func_float16_ptr(<16 x float> %x, <16 x float>* %y)
+  %2 = load <16 x float>, <16 x float>* %y, align 16
+  %3 = fadd <16 x float> %2, %1
+  ret <16 x float> %3
+}
+
+;test calling conventions - preserved registers
+
+; preserved zmm16-
+; WIN64-LABEL: testf16_regs
+; WIN64: call
+; WIN64: vaddps  %zmm16, %zmm0, %zmm0
+; WIN64: ret
+
+; preserved zmm16-
+; X64-LABEL: testf16_regs
+; X64: call
+; X64: vaddps  %zmm16, %zmm0, %zmm0
+; X64: ret
+
+define <16 x float> @testf16_regs(<16 x float> %a, <16 x float> %b) nounwind {
+  %y = alloca <16 x float>, align 16
+  %x = fadd <16 x float> %a, %b
+  %1 = call intel_ocl_bicc <16 x float> @func_float16_ptr(<16 x float> %x, <16 x float>* %y)
+  %2 = load <16 x float>, <16 x float>* %y, align 16
+  %3 = fadd <16 x float> %1, %b
+  %4 = fadd <16 x float> %2, %3
+  ret <16 x float> %4
+}
+
+; test calling conventions - prolog and epilog
+; WIN64-LABEL: test_prolog_epilog
+; WIN64: vmovups %zmm21, {{.*(%rbp).*}}     # 64-byte Spill
+; WIN64: vmovups %zmm6, {{.*(%rbp).*}}     # 64-byte Spill
+; WIN64: call
+; WIN64: vmovups {{.*(%rbp).*}}, %zmm6      # 64-byte Reload
+; WIN64: vmovups {{.*(%rbp).*}}, %zmm21     # 64-byte Reload
+
+; X64-LABEL: test_prolog_epilog
+; X64:  kmovw   %k7, {{.*}}(%rsp)         ## 8-byte Folded Spill
+; X64:  kmovw   %k6, {{.*}}(%rsp)         ## 8-byte Folded Spill
+; X64:  kmovw   %k5, {{.*}}(%rsp)         ## 8-byte Folded Spill
+; X64:  kmovw   %k4, {{.*}}(%rsp)         ## 8-byte Folded Spill
+; X64: vmovups %zmm31, {{.*}}(%rsp)  ## 64-byte Spill
+; X64: vmovups %zmm16, {{.*}}(%rsp)  ## 64-byte Spill
+; X64: call
+; X64: vmovups {{.*}}(%rsp), %zmm16 ## 64-byte Reload
+; X64: vmovups {{.*}}(%rsp), %zmm31 ## 64-byte Reload
+define intel_ocl_bicc <16 x float> @test_prolog_epilog(<16 x float> %a, <16 x float> %b) nounwind {
+   %c = call <16 x float> @func_float16(<16 x float> %a, <16 x float> %b)
+   ret <16 x float> %c
+}
+
+
+declare <16 x float> @func_float16_mask(<16 x float>, <16 x i1>)
+
+; X64-LABEL: testf16_inp_mask
+; X64: kmovw   %edi, %k1
+; X64: call
+define <16 x float> @testf16_inp_mask(<16 x float> %a, i16 %mask)  {
+  %imask = bitcast i16 %mask to <16 x i1>
+  %1 = call intel_ocl_bicc <16 x float> @func_float16_mask(<16 x float> %a, <16 x i1> %imask)
+  ret <16 x float> %1
+}
+
+; X64-LABEL: test_prolog_epilog_with_mask
+; X64: kxorw   %k{{.*}}, %k{{.*}}, %k1
+; X64: call
+define intel_ocl_bicc <16 x float> @test_prolog_epilog_with_mask(<16 x float> %a, <16 x i32> %x1, <16 x i32>%x2, <16 x i1> %mask) nounwind {
+   %cmp_res = icmp eq <16 x i32>%x1, %x2
+   %mask1 = xor <16 x i1> %cmp_res, %mask
+   %c = call intel_ocl_bicc <16 x float> @func_float16_mask(<16 x float> %a, <16 x i1>%mask1)
+   ret <16 x float> %c
+}
\ No newline at end of file
diff --git a/test/CodeGen/X86/avx512-intrinsics.ll b/test/CodeGen/X86/avx512-intrinsics.ll
index 7cd01683fa98..471e34cdedce 100644
--- a/test/CodeGen/X86/avx512-intrinsics.ll
+++ b/test/CodeGen/X86/avx512-intrinsics.ll
@@ -5,7 +5,7 @@ declare i32 @llvm.x86.avx512.kortestz.w(i16, i16) nounwind readnone
 ; CHECK: kortestw
 ; CHECK: sete
 define i32 @test_kortestz(i16 %a0, i16 %a1) {
-  %res = call i32 @llvm.x86.avx512.kortestz.w(i16 %a0, i16 %a1) 
+  %res = call i32 @llvm.x86.avx512.kortestz.w(i16 %a0, i16 %a1)
   ret i32 %res
 }
 
@@ -14,7 +14,7 @@ declare i32 @llvm.x86.avx512.kortestc.w(i16, i16) nounwind readnone
 ; CHECK: kortestw
 ; CHECK: sbbl
 define i32 @test_kortestc(i16 %a0, i16 %a1) {
-  %res = call i32 @llvm.x86.avx512.kortestc.w(i16 %a0, i16 %a1) 
+  %res = call i32 @llvm.x86.avx512.kortestc.w(i16 %a0, i16 %a1)
   ret i32 %res
 }
 
@@ -277,7 +277,7 @@ define <8 x i64> @test_conflict_q(<8 x i64> %a) {
 declare <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64>, <8 x i64>, i8) nounwind readonly
 
 define <16 x i32> @test_maskz_conflict_d(<16 x i32> %a, i16 %mask) {
-  ; CHECK: vpconflictd 
+  ; CHECK: vpconflictd
   %res = call <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32> %a, <16 x i32> zeroinitializer, i16 %mask)
   ret <16 x i32> %res
 }
@@ -356,7 +356,7 @@ define <8 x double> @test_x86_mask_blend_pd_512(i8 %a0, <8 x double> %a1, <8 x d
 define <8 x double> @test_x86_mask_blend_pd_512_memop(<8 x double> %a, <8 x double>* %ptr, i8 %mask) {
   ; CHECK-LABEL: test_x86_mask_blend_pd_512_memop
   ; CHECK: vblendmpd (%
-  %b = load <8 x double>* %ptr
+  %b = load <8 x double>, <8 x double>* %ptr
   %res = call <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double> %a, <8 x double> %b, i8 %mask) ; <<8 x double>> [#uses=1]
   ret <8 x double> %res
 }
@@ -382,7 +382,7 @@ declare <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i64>, <8 x i64>, i8) no
   ret <8 x i32>%res
  }
  declare <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double>, <8 x i32>, i8, i32)
- 
+
  define <16 x i32> @test_cvtps2udq(<16 x float> %a) {
  ;CHECK: vcvtps2udq {rd-sae}{{.*}}encoding: [0x62,0xf1,0x7c,0x38,0x79,0xc0]
   %res = call <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float> %a, <16 x i32>zeroinitializer, i16 -1, i32 1)
@@ -434,15 +434,6 @@ declare <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i64>, <8 x i64>, i8) no
  declare <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32>, <8 x double>, i8)
 
  ; fp min - max
-define <16 x float> @test_vmaxps(<16 x float> %a0, <16 x float> %a1) {
-  ; CHECK: vmaxps
-  %res = call <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float> %a0, <16 x float> %a1,
-                    <16 x float>zeroinitializer, i16 -1, i32 4)
-  ret <16 x float> %res
-}
-declare <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float>, <16 x float>,
-                    <16 x float>, i16, i32)
-
 define <8 x double> @test_vmaxpd(<8 x double> %a0, <8 x double> %a1) {
   ; CHECK: vmaxpd
   %res = call <8 x double> @llvm.x86.avx512.mask.max.pd.512(<8 x double> %a0, <8 x double> %a1,
@@ -452,15 +443,6 @@ define <8 x double> @test_vmaxpd(<8 x double> %a0, <8 x double> %a1) {
 declare <8 x double> @llvm.x86.avx512.mask.max.pd.512(<8 x double>, <8 x double>,
                     <8 x double>, i8, i32)
 
-define <16 x float> @test_vminps(<16 x float> %a0, <16 x float> %a1) {
-  ; CHECK: vminps
-  %res = call <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float> %a0, <16 x float> %a1,
-                    <16 x float>zeroinitializer, i16 -1, i32 4)
-  ret <16 x float> %res
-}
-declare <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float>, <16 x float>,
-                    <16 x float>, i16, i32)
-
 define <8 x double> @test_vminpd(<8 x double> %a0, <8 x double> %a1) {
   ; CHECK: vminpd
   %res = call <8 x double> @llvm.x86.avx512.mask.min.pd.512(<8 x double> %a0, <8 x double> %a1,
@@ -515,14 +497,6 @@ define <16 x i32> @test_vpmaxsd(<16 x i32> %a0, <16 x i32> %a1) {
 }
 declare <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
 
-define <8 x i64> @test_vpmuludq(<16 x i32> %a0, <16 x i32> %a1) {
-  ; CHECK: vpmuludq {{.*}}encoding: [0x62,0xf1,0xfd,0x48,0xf4,0xc1]
-  %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a0, <16 x i32> %a1,
-                    <8 x i64>zeroinitializer, i8 -1)
-  ret <8 x i64> %res
-}
-declare <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32>, <16 x i32>, <8 x i64>, i8)
-
 define i8 @test_vptestmq(<8 x i64> %a0, <8 x i64> %a1) {
   ; CHECK: vptestmq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x27,0xc1]
   %res = call i8 @llvm.x86.avx512.mask.ptestm.q.512(<8 x i64> %a0, <8 x i64> %a1, i8 -1)
@@ -551,7 +525,73 @@ define void @test_store2(<8 x double> %data, i8* %ptr, i8 %mask) {
   ret void
 }
 
-declare void @llvm.x86.avx512.mask.storeu.pd.512(i8*, <8 x double>, i8 )
+declare void @llvm.x86.avx512.mask.storeu.pd.512(i8*, <8 x double>, i8)
+
+define void @test_mask_store_aligned_ps(<16 x float> %data, i8* %ptr, i16 %mask) {
+; CHECK-LABEL: test_mask_store_aligned_ps:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    kmovw %esi, %k1
+; CHECK-NEXT:    vmovaps %zmm0, (%rdi) {%k1}
+; CHECK-NEXT:    retq
+  call void @llvm.x86.avx512.mask.store.ps.512(i8* %ptr, <16 x float> %data, i16 %mask)
+  ret void
+}
+
+declare void @llvm.x86.avx512.mask.store.ps.512(i8*, <16 x float>, i16 )
+
+define void @test_mask_store_aligned_pd(<8 x double> %data, i8* %ptr, i8 %mask) {
+; CHECK-LABEL: test_mask_store_aligned_pd:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    kmovw %esi, %k1
+; CHECK-NEXT:    vmovapd %zmm0, (%rdi) {%k1}
+; CHECK-NEXT:    retq
+  call void @llvm.x86.avx512.mask.store.pd.512(i8* %ptr, <8 x double> %data, i8 %mask)
+  ret void
+}
+
+declare void @llvm.x86.avx512.mask.store.pd.512(i8*, <8 x double>, i8)
+
+define <16 x float> @test_maskz_load_aligned_ps(<16 x float> %data, i8* %ptr, i16 %mask) {
+; CHECK-LABEL: test_maskz_load_aligned_ps:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    kmovw %esi, %k1
+; CHECK-NEXT:    vmovaps (%rdi), %zmm0 {%k1} {z}
+; CHECK-NEXT:    retq
+  %res = call <16 x float> @llvm.x86.avx512.mask.load.ps.512(i8* %ptr, <16 x float> zeroinitializer, i16 %mask)
+  ret <16 x float> %res
+}
+
+declare <16 x float> @llvm.x86.avx512.mask.load.ps.512(i8*, <16 x float>, i16)
+
+define <8 x double> @test_maskz_load_aligned_pd(<8 x double> %data, i8* %ptr, i8 %mask) {
+; CHECK-LABEL: test_maskz_load_aligned_pd:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    kmovw %esi, %k1
+; CHECK-NEXT:    vmovapd (%rdi), %zmm0 {%k1} {z}
+; CHECK-NEXT:    retq
+  %res = call <8 x double> @llvm.x86.avx512.mask.load.pd.512(i8* %ptr, <8 x double> zeroinitializer, i8 %mask)
+  ret <8 x double> %res
+}
+
+declare <8 x double> @llvm.x86.avx512.mask.load.pd.512(i8*, <8 x double>, i8)
+
+define <16 x float> @test_load_aligned_ps(<16 x float> %data, i8* %ptr, i16 %mask) {
+; CHECK-LABEL: test_load_aligned_ps:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    vmovaps (%rdi), %zmm0
+; CHECK-NEXT:    retq
+  %res = call <16 x float> @llvm.x86.avx512.mask.load.ps.512(i8* %ptr, <16 x float> zeroinitializer, i16 -1)
+  ret <16 x float> %res
+}
+
+define <8 x double> @test_load_aligned_pd(<8 x double> %data, i8* %ptr, i8 %mask) {
+; CHECK-LABEL: test_load_aligned_pd:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    vmovapd (%rdi), %zmm0
+; CHECK-NEXT:    retq
+  %res = call <8 x double> @llvm.x86.avx512.mask.load.pd.512(i8* %ptr, <8 x double> zeroinitializer, i8 -1)
+  ret <8 x double> %res
+}
 
 define <16 x float> @test_vpermt2ps(<16 x float>%x, <16 x float>%y, <16 x i32>%perm) {
 ; CHECK: vpermt2ps {{.*}}encoding: [0x62,0xf2,0x6d,0x48,0x7f,0xc1]
@@ -959,8 +999,8 @@ define <16 x i32> @test_x86_avx512_pslli_d(<16 x i32> %a0) {
 }
 
 define <16 x i32> @test_x86_avx512_mask_pslli_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
-  ; CHECK-LABEL: test_x86_avx512_mask_pslli_d 
-  ; CHECK: vpslld $7, %zmm0, %zmm1 {%k1}  
+  ; CHECK-LABEL: test_x86_avx512_mask_pslli_d
+  ; CHECK: vpslld $7, %zmm0, %zmm1 {%k1}
   %res = call <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32> %a0, i32 7, <16 x i32> %a1, i16 %mask)
   ret <16 x i32> %res
 }
@@ -983,14 +1023,14 @@ define <8 x i64> @test_x86_avx512_pslli_q(<8 x i64> %a0) {
 
 define <8 x i64> @test_x86_avx512_mask_pslli_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
   ; CHECK-LABEL: test_x86_avx512_mask_pslli_q
-  ; CHECK: vpsllq $7, %zmm0, %zmm1 {%k1}   
+  ; CHECK: vpsllq $7, %zmm0, %zmm1 {%k1}
   %res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)
   ret <8 x i64> %res
 }
 
 define <8 x i64> @test_x86_avx512_maskz_pslli_q(<8 x i64> %a0, i8 %mask) {
   ; CHECK-LABEL: test_x86_avx512_maskz_pslli_q
-  ; CHECK: vpsllq $7, %zmm0, %zmm0 {%k1} {z} 
+  ; CHECK: vpsllq $7, %zmm0, %zmm0 {%k1} {z}
   %res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)
   ret <8 x i64> %res
 }
@@ -1006,7 +1046,7 @@ define <16 x i32> @test_x86_avx512_psrli_d(<16 x i32> %a0) {
 
 define <16 x i32> @test_x86_avx512_mask_psrli_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
   ; CHECK-LABEL: test_x86_avx512_mask_psrli_d
-  ; CHECK: vpsrld $7, %zmm0, %zmm1 {%k1}  
+  ; CHECK: vpsrld $7, %zmm0, %zmm1 {%k1}
   %res = call <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32> %a0, i32 7, <16 x i32> %a1, i16 %mask)
   ret <16 x i32> %res
 }
@@ -1029,7 +1069,7 @@ define <8 x i64> @test_x86_avx512_psrli_q(<8 x i64> %a0) {
 
 define <8 x i64> @test_x86_avx512_mask_psrli_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
   ; CHECK-LABEL: test_x86_avx512_mask_psrli_q
-  ; CHECK: vpsrlq $7, %zmm0, %zmm1 {%k1}  
+  ; CHECK: vpsrlq $7, %zmm0, %zmm1 {%k1}
   %res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)
   ret <8 x i64> %res
 }
@@ -1052,7 +1092,7 @@ define <16 x i32> @test_x86_avx512_psrai_d(<16 x i32> %a0) {
 
 define <16 x i32> @test_x86_avx512_mask_psrai_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
   ; CHECK-LABEL: test_x86_avx512_mask_psrai_d
-  ; CHECK: vpsrad $7, %zmm0, %zmm1 {%k1}  
+  ; CHECK: vpsrad $7, %zmm0, %zmm1 {%k1}
   %res = call <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32> %a0, i32 7, <16 x i32> %a1, i16 %mask)
   ret <16 x i32> %res
 }
@@ -1075,7 +1115,7 @@ define <8 x i64> @test_x86_avx512_psrai_q(<8 x i64> %a0) {
 
 define <8 x i64> @test_x86_avx512_mask_psrai_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
   ; CHECK-LABEL: test_x86_avx512_mask_psrai_q
-  ; CHECK: vpsraq $7, %zmm0, %zmm1 {%k1}   
+  ; CHECK: vpsraq $7, %zmm0, %zmm1 {%k1}
   %res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)
   ret <8 x i64> %res
 }
@@ -1369,7 +1409,1364 @@ declare <8 x i64> @llvm.x86.avx512.mask.psrlv.q(<8 x i64>, <8 x i64>, <8 x i64>,
 define <8 x i64> @test_x86_avx512_psrlv_q_memop(<8 x i64> %a0, <8 x i64>* %ptr) {
   ; CHECK-LABEL: test_x86_avx512_psrlv_q_memop
   ; CHECK: vpsrlvq (%
-  %b = load <8 x i64>* %ptr
+  %b = load <8 x i64>, <8 x i64>* %ptr
   %res = call <8 x i64> @llvm.x86.avx512.mask.psrlv.q(<8 x i64> %a0, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
   ret <8 x i64> %res
 }
+
+declare <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
+declare <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
+declare <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
+
+define <16 x float> @test_vsubps_rn(<16 x float> %a0, <16 x float> %a1) {
+  ; CHECK-LABEL: test_vsubps_rn
+  ; CHECK: vsubps {rn-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x18,0x5c,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> zeroinitializer, i16 -1, i32 0)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_vsubps_rd(<16 x float> %a0, <16 x float> %a1) {
+  ; CHECK-LABEL: test_vsubps_rd
+  ; CHECK: vsubps {rd-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x38,0x5c,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> zeroinitializer, i16 -1, i32 1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_vsubps_ru(<16 x float> %a0, <16 x float> %a1) {
+  ; CHECK-LABEL: test_vsubps_ru
+  ; CHECK: vsubps {ru-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x58,0x5c,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> zeroinitializer, i16 -1, i32 2)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_vsubps_rz(<16 x float> %a0, <16 x float> %a1) {
+  ; CHECK-LABEL: test_vsubps_rz
+  ; CHECK: vsubps {rz-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x78,0x5c,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> zeroinitializer, i16 -1, i32 3)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_vmulps_rn(<16 x float> %a0, <16 x float> %a1) {
+  ; CHECK-LABEL: test_vmulps_rn
+  ; CHECK: vmulps {rn-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x18,0x59,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> zeroinitializer, i16 -1, i32 0)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_vmulps_rd(<16 x float> %a0, <16 x float> %a1) {
+  ; CHECK-LABEL: test_vmulps_rd
+  ; CHECK: vmulps {rd-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x38,0x59,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> zeroinitializer, i16 -1, i32 1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_vmulps_ru(<16 x float> %a0, <16 x float> %a1) {
+  ; CHECK-LABEL: test_vmulps_ru
+  ; CHECK: vmulps {ru-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x58,0x59,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> zeroinitializer, i16 -1, i32 2)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_vmulps_rz(<16 x float> %a0, <16 x float> %a1) {
+  ; CHECK-LABEL: test_vmulps_rz
+  ; CHECK: vmulps {rz-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x78,0x59,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> zeroinitializer, i16 -1, i32 3)
+  ret <16 x float> %res
+}
+
+;; mask float
+define <16 x float> @test_vmulps_mask_rn(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ; CHECK-LABEL: test_vmulps_mask_rn
+  ; CHECK: vmulps {rn-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0x7c,0x99,0x59,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> zeroinitializer, i16 %mask, i32 0)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_vmulps_mask_rd(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ; CHECK-LABEL: test_vmulps_mask_rd
+  ; CHECK: vmulps {rd-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xb9,0x59,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> zeroinitializer, i16 %mask, i32 1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_vmulps_mask_ru(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ; CHECK-LABEL: test_vmulps_mask_ru
+  ; CHECK: vmulps {ru-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xd9,0x59,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> zeroinitializer, i16 %mask, i32 2)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_vmulps_mask_rz(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ; CHECK-LABEL: test_vmulps_mask_rz
+  ; CHECK: vmulps {rz-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xf9,0x59,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> zeroinitializer, i16 %mask, i32 3)
+  ret <16 x float> %res
+}
+
+;; With Passthru value
+define <16 x float> @test_vmulps_mask_passthru_rn(<16 x float> %a0, <16 x float> %a1, <16 x float> %passthru, i16 %mask) {
+  ; CHECK-LABEL: test_vmulps_mask_passthru_rn
+  ; CHECK: vmulps {rn-sae}{{.*}}{%k1} ## encoding: [0x62,0xf1,0x7c,0x19,0x59,0xd1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> %passthru, i16 %mask, i32 0)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_vmulps_mask_passthru_rd(<16 x float> %a0, <16 x float> %a1, <16 x float> %passthru, i16 %mask) {
+  ; CHECK-LABEL: test_vmulps_mask_passthru_rd
+  ; CHECK: vmulps {rd-sae}{{.*}}{%k1} ## encoding: [0x62,0xf1,0x7c,0x39,0x59,0xd1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> %passthru, i16 %mask, i32 1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_vmulps_mask_passthru_ru(<16 x float> %a0, <16 x float> %a1, <16 x float> %passthru, i16 %mask) {
+  ; CHECK-LABEL: test_vmulps_mask_passthru_ru
+  ; CHECK: vmulps {ru-sae}{{.*}}{%k1} ## encoding: [0x62,0xf1,0x7c,0x59,0x59,0xd1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> %passthru, i16 %mask, i32 2)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_vmulps_mask_passthru_rz(<16 x float> %a0, <16 x float> %a1, <16 x float> %passthru, i16 %mask) {
+  ; CHECK-LABEL: test_vmulps_mask_passthru_rz
+  ; CHECK: vmulps {rz-sae}{{.*}}{%k1} ## encoding: [0x62,0xf1,0x7c,0x79,0x59,0xd1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
+                    <16 x float> %passthru, i16 %mask, i32 3)
+  ret <16 x float> %res
+}
+
+;; mask double
+define <8 x double> @test_vmulpd_mask_rn(<8 x double> %a0, <8 x double> %a1, i8 %mask) {
+  ; CHECK-LABEL: test_vmulpd_mask_rn
+  ; CHECK: vmulpd {rn-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x99,0x59,0xc1]
+  %res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1,
+                    <8 x double> zeroinitializer, i8 %mask, i32 0)
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_vmulpd_mask_rd(<8 x double> %a0, <8 x double> %a1, i8 %mask) {
+  ; CHECK-LABEL: test_vmulpd_mask_rd
+  ; CHECK: vmulpd {rd-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xb9,0x59,0xc1]
+  %res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1,
+                    <8 x double> zeroinitializer, i8 %mask, i32 1)
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_vmulpd_mask_ru(<8 x double> %a0, <8 x double> %a1, i8 %mask) {
+  ; CHECK-LABEL: test_vmulpd_mask_ru
+  ; CHECK: vmulpd {ru-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xd9,0x59,0xc1]
+  %res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1,
+                    <8 x double> zeroinitializer, i8 %mask, i32 2)
+  ret <8 x double> %res
+}
+
+define <8 x double> @test_vmulpd_mask_rz(<8 x double> %a0, <8 x double> %a1, i8 %mask) {
+  ; CHECK-LABEL: test_vmulpd_mask_rz
+  ; CHECK: vmulpd {rz-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xf9,0x59,0xc1]
+  %res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1,
+                    <8 x double> zeroinitializer, i8 %mask, i32 3)
+  ret <8 x double> %res
+}
+
+define <16 x i32> @test_xor_epi32(<16 x i32> %a, <16 x i32> %b) {
+  ;CHECK-LABEL: test_xor_epi32
+  ;CHECK: vpxord {{.*}}encoding: [0x62,0xf1,0x7d,0x48,0xef,0xc1]
+  %res = call <16 x i32> @llvm.x86.avx512.mask.pxor.d.512(<16 x i32> %a,<16 x i32> %b, <16 x i32>zeroinitializer, i16 -1)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_xor_epi32(<16 x i32> %a,<16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_xor_epi32
+  ;CHECK: vpxord %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xef,0xd1]
+  %res = call <16 x i32> @llvm.x86.avx512.mask.pxor.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+declare <16 x i32> @llvm.x86.avx512.mask.pxor.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
+
+define <16 x i32> @test_or_epi32(<16 x i32> %a, <16 x i32> %b) {
+  ;CHECK-LABEL: test_or_epi32
+  ;CHECK: vpord {{.*}}encoding: [0x62,0xf1,0x7d,0x48,0xeb,0xc1]
+  %res = call <16 x i32> @llvm.x86.avx512.mask.por.d.512(<16 x i32> %a,<16 x i32> %b, <16 x i32>zeroinitializer, i16 -1)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_or_epi32(<16 x i32> %a,<16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_or_epi32
+  ;CHECK: vpord %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xeb,0xd1]
+  %res = call <16 x i32> @llvm.x86.avx512.mask.por.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+declare <16 x i32> @llvm.x86.avx512.mask.por.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
+
+define <16 x i32> @test_and_epi32(<16 x i32> %a, <16 x i32> %b) {
+  ;CHECK-LABEL: test_and_epi32
+  ;CHECK: vpandd {{.*}}encoding: [0x62,0xf1,0x7d,0x48,0xdb,0xc1]
+  %res = call <16 x i32> @llvm.x86.avx512.mask.pand.d.512(<16 x i32> %a,<16 x i32> %b, <16 x i32>zeroinitializer, i16 -1)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_and_epi32(<16 x i32> %a,<16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_and_epi32
+  ;CHECK: vpandd %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xdb,0xd1]
+  %res = call <16 x i32> @llvm.x86.avx512.mask.pand.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+declare <16 x i32> @llvm.x86.avx512.mask.pand.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
+
+define <8 x i64> @test_xor_epi64(<8 x i64> %a, <8 x i64> %b) {
+  ;CHECK-LABEL: test_xor_epi64
+  ;CHECK: vpxorq {{.*}}encoding: [0x62,0xf1,0xfd,0x48,0xef,0xc1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_xor_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_epi64
+  ;CHECK: vpxorq %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xef,0xd1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+declare <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
+
+define <8 x i64> @test_or_epi64(<8 x i64> %a, <8 x i64> %b) {
+  ;CHECK-LABEL: test_or_epi64
+  ;CHECK: vporq {{.*}}encoding: [0x62,0xf1,0xfd,0x48,0xeb,0xc1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_or_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_epi64
+  ;CHECK: vporq %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xeb,0xd1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+declare <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
+
+define <8 x i64> @test_and_epi64(<8 x i64> %a, <8 x i64> %b) {
+  ;CHECK-LABEL: test_and_epi64
+  ;CHECK: vpandq {{.*}}encoding: [0x62,0xf1,0xfd,0x48,0xdb,0xc1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_and_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_epi64
+  ;CHECK: vpandq %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xdb,0xd1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+declare <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
+
+
+define <16 x i32> @test_mask_add_epi32_rr(<16 x i32> %a, <16 x i32> %b) {
+  ;CHECK-LABEL: test_mask_add_epi32_rr
+  ;CHECK: vpaddd %zmm1, %zmm0, %zmm0     ## encoding: [0x62,0xf1,0x7d,0x48,0xfe,0xc1]
+  %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_add_epi32_rrk(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rrk
+  ;CHECK: vpaddd %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xfe,0xd1]
+  %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_add_epi32_rrkz(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rrkz
+  ;CHECK: vpaddd %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0xfe,0xc1]
+  %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_add_epi32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_add_epi32_rm
+  ;CHECK: vpaddd (%rdi), %zmm0, %zmm0    ## encoding: [0x62,0xf1,0x7d,0x48,0xfe,0x07]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_add_epi32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <16 x i32> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rmk
+  ;CHECK: vpaddd (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xfe,0x0f]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_add_epi32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rmkz
+  ;CHECK: vpaddd (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0xfe,0x07]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_add_epi32_rmb(<16 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_add_epi32_rmb
+  ;CHECK: vpaddd (%rdi){1to16}, %zmm0, %zmm0  ## encoding: [0x62,0xf1,0x7d,0x58,0xfe,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_add_epi32_rmbk(<16 x i32> %a, i32* %ptr_b, <16 x i32> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rmbk
+  ;CHECK: vpaddd (%rdi){1to16}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x59,0xfe,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_add_epi32_rmbkz(<16 x i32> %a, i32* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rmbkz
+  ;CHECK: vpaddd (%rdi){1to16}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xd9,0xfe,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+declare <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
+
+define <16 x i32> @test_mask_sub_epi32_rr(<16 x i32> %a, <16 x i32> %b) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rr
+  ;CHECK: vpsubd %zmm1, %zmm0, %zmm0     ## encoding: [0x62,0xf1,0x7d,0x48,0xfa,0xc1]
+  %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_sub_epi32_rrk(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rrk
+  ;CHECK: vpsubd %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xfa,0xd1]
+  %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_sub_epi32_rrkz(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rrkz
+  ;CHECK: vpsubd %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0xfa,0xc1]
+  %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_sub_epi32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rm
+  ;CHECK: vpsubd (%rdi), %zmm0, %zmm0    ## encoding: [0x62,0xf1,0x7d,0x48,0xfa,0x07]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_sub_epi32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <16 x i32> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rmk
+  ;CHECK: vpsubd (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xfa,0x0f]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_sub_epi32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rmkz
+  ;CHECK: vpsubd (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0xfa,0x07]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_sub_epi32_rmb(<16 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rmb
+  ;CHECK: vpsubd (%rdi){1to16}, %zmm0, %zmm0  ## encoding: [0x62,0xf1,0x7d,0x58,0xfa,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_sub_epi32_rmbk(<16 x i32> %a, i32* %ptr_b, <16 x i32> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rmbk
+  ;CHECK: vpsubd (%rdi){1to16}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x59,0xfa,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_sub_epi32_rmbkz(<16 x i32> %a, i32* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rmbkz
+  ;CHECK: vpsubd (%rdi){1to16}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xd9,0xfa,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+declare <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
+
+define <8 x i64> @test_mask_add_epi64_rr(<8 x i64> %a, <8 x i64> %b) {
+  ;CHECK-LABEL: test_mask_add_epi64_rr
+  ;CHECK: vpaddq %zmm1, %zmm0, %zmm0     ## encoding: [0x62,0xf1,0xfd,0x48,0xd4,0xc1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_add_epi64_rrk(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi64_rrk
+  ;CHECK: vpaddq %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xd4,0xd1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_add_epi64_rrkz(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi64_rrkz
+  ;CHECK: vpaddq %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0xd4,0xc1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_add_epi64_rm(<8 x i64> %a, <8 x i64>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_add_epi64_rm
+  ;CHECK: vpaddq (%rdi), %zmm0, %zmm0    ## encoding: [0x62,0xf1,0xfd,0x48,0xd4,0x07]
+  %b = load <8 x i64>, <8 x i64>* %ptr_b
+  %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_add_epi64_rmk(<8 x i64> %a, <8 x i64>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi64_rmk
+  ;CHECK: vpaddq (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xd4,0x0f]
+  %b = load <8 x i64>, <8 x i64>* %ptr_b
+  %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_add_epi64_rmkz(<8 x i64> %a, <8 x i64>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi64_rmkz
+  ;CHECK: vpaddq (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0xd4,0x07]
+  %b = load <8 x i64>, <8 x i64>* %ptr_b
+  %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_add_epi64_rmb(<8 x i64> %a, i64* %ptr_b) {
+  ;CHECK-LABEL: test_mask_add_epi64_rmb
+  ;CHECK: vpaddq (%rdi){1to8}, %zmm0, %zmm0  ## encoding: [0x62,0xf1,0xfd,0x58,0xd4,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_add_epi64_rmbk(<8 x i64> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi64_rmbk
+  ;CHECK: vpaddq (%rdi){1to8}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x59,0xd4,0x0f]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_add_epi64_rmbkz(<8 x i64> %a, i64* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi64_rmbkz
+  ;CHECK: vpaddq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xd9,0xd4,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+declare <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
+
+define <8 x i64> @test_mask_sub_epi64_rr(<8 x i64> %a, <8 x i64> %b) {
+  ;CHECK-LABEL: test_mask_sub_epi64_rr
+  ;CHECK: vpsubq %zmm1, %zmm0, %zmm0     ## encoding: [0x62,0xf1,0xfd,0x48,0xfb,0xc1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_sub_epi64_rrk(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi64_rrk
+  ;CHECK: vpsubq %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xfb,0xd1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_sub_epi64_rrkz(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi64_rrkz
+  ;CHECK: vpsubq %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0xfb,0xc1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_sub_epi64_rm(<8 x i64> %a, <8 x i64>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_sub_epi64_rm
+  ;CHECK: vpsubq (%rdi), %zmm0, %zmm0    ## encoding: [0x62,0xf1,0xfd,0x48,0xfb,0x07]
+  %b = load <8 x i64>, <8 x i64>* %ptr_b
+  %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_sub_epi64_rmk(<8 x i64> %a, <8 x i64>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi64_rmk
+  ;CHECK: vpsubq (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xfb,0x0f]
+  %b = load <8 x i64>, <8 x i64>* %ptr_b
+  %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_sub_epi64_rmkz(<8 x i64> %a, <8 x i64>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi64_rmkz
+  ;CHECK: vpsubq (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0xfb,0x07]
+  %b = load <8 x i64>, <8 x i64>* %ptr_b
+  %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_sub_epi64_rmb(<8 x i64> %a, i64* %ptr_b) {
+  ;CHECK-LABEL: test_mask_sub_epi64_rmb
+  ;CHECK: vpsubq (%rdi){1to8}, %zmm0, %zmm0  ## encoding: [0x62,0xf1,0xfd,0x58,0xfb,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_sub_epi64_rmbk(<8 x i64> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi64_rmbk
+  ;CHECK: vpsubq (%rdi){1to8}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x59,0xfb,0x0f]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_sub_epi64_rmbkz(<8 x i64> %a, i64* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi64_rmbkz
+  ;CHECK: vpsubq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xd9,0xfb,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+declare <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
+
+define <8 x i64> @test_mask_mul_epi32_rr(<16 x i32> %a, <16 x i32> %b) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rr
+  ;CHECK: vpmuldq %zmm1, %zmm0, %zmm0     ## encoding: [0x62,0xf2,0xfd,0x48,0x28,0xc1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epi32_rrk(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rrk
+  ;CHECK: vpmuldq %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf2,0xfd,0x49,0x28,0xd1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epi32_rrkz(<16 x i32> %a, <16 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rrkz
+  ;CHECK: vpmuldq %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xc9,0x28,0xc1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epi32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rm
+  ;CHECK: vpmuldq (%rdi), %zmm0, %zmm0    ## encoding: [0x62,0xf2,0xfd,0x48,0x28,0x07]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epi32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rmk
+  ;CHECK: vpmuldq (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x49,0x28,0x0f]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epi32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rmkz
+  ;CHECK: vpmuldq (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xc9,0x28,0x07]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epi32_rmb(<16 x i32> %a, i64* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rmb
+  ;CHECK: vpmuldq (%rdi){1to8}, %zmm0, %zmm0  ## encoding: [0x62,0xf2,0xfd,0x58,0x28,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %b = bitcast <8 x i64> %b64 to <16 x i32>
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epi32_rmbk(<16 x i32> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rmbk
+  ;CHECK: vpmuldq (%rdi){1to8}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x59,0x28,0x0f]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %b = bitcast <8 x i64> %b64 to <16 x i32>
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epi32_rmbkz(<16 x i32> %a, i64* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rmbkz
+  ;CHECK: vpmuldq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xd9,0x28,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %b = bitcast <8 x i64> %b64 to <16 x i32>
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+declare <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32>, <16 x i32>, <8 x i64>, i8)
+
+define <8 x i64> @test_mask_mul_epu32_rr(<16 x i32> %a, <16 x i32> %b) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rr
+  ;CHECK: vpmuludq %zmm1, %zmm0, %zmm0  ## encoding: [0x62,0xf1,0xfd,0x48,0xf4,0xc1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epu32_rrk(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rrk
+  ;CHECK: vpmuludq %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xf4,0xd1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epu32_rrkz(<16 x i32> %a, <16 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rrkz
+  ;CHECK: vpmuludq %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0xf4,0xc1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epu32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rm
+  ;CHECK: vpmuludq (%rdi), %zmm0, %zmm0  ## encoding: [0x62,0xf1,0xfd,0x48,0xf4,0x07]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epu32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rmk
+  ;CHECK: vpmuludq (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xf4,0x0f]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epu32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rmkz
+  ;CHECK: vpmuludq (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0xf4,0x07]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epu32_rmb(<16 x i32> %a, i64* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rmb
+  ;CHECK: vpmuludq (%rdi){1to8}, %zmm0, %zmm0  ## encoding: [0x62,0xf1,0xfd,0x58,0xf4,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %b = bitcast <8 x i64> %b64 to <16 x i32>
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epu32_rmbk(<16 x i32> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rmbk
+  ;CHECK: vpmuludq (%rdi){1to8}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x59,0xf4,0x0f]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %b = bitcast <8 x i64> %b64 to <16 x i32>
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mul_epu32_rmbkz(<16 x i32> %a, i64* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rmbkz
+  ;CHECK: vpmuludq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xd9,0xf4,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %b = bitcast <8 x i64> %b64 to <16 x i32>
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
+  ret < 8 x i64> %res
+}
+
+declare <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32>, <16 x i32>, <8 x i64>, i8)
+
+define <16 x i32> @test_mask_mullo_epi32_rr_512(<16 x i32> %a, <16 x i32> %b) {
+  ;CHECK-LABEL: test_mask_mullo_epi32_rr_512
+  ;CHECK: vpmulld %zmm1, %zmm0, %zmm0 ## encoding: [0x62,0xf2,0x7d,0x48,0x40,0xc1]
+  %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
+  ret <16 x i32> %res
+}
+
+define <16 x i32> @test_mask_mullo_epi32_rrk_512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi32_rrk_512
+  ;CHECK: vpmulld %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf2,0x7d,0x49,0x40,0xd1]
+  %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_mullo_epi32_rrkz_512(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi32_rrkz_512
+  ;CHECK: vpmulld %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xc9,0x40,0xc1]
+  %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_mullo_epi32_rm_512(<16 x i32> %a, <16 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mullo_epi32_rm_512
+  ;CHECK: vpmulld (%rdi), %zmm0, %zmm0 ## encoding: [0x62,0xf2,0x7d,0x48,0x40,0x07]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_mullo_epi32_rmk_512(<16 x i32> %a, <16 x i32>* %ptr_b, <16 x i32> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi32_rmk_512
+  ;CHECK: vpmulld (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf2,0x7d,0x49,0x40,0x0f]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_mullo_epi32_rmkz_512(<16 x i32> %a, <16 x i32>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi32_rmkz_512
+  ;CHECK: vpmulld (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xc9,0x40,0x07]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_mullo_epi32_rmb_512(<16 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mullo_epi32_rmb_512
+  ;CHECK: vpmulld (%rdi){1to16}, %zmm0, %zmm0 ## encoding: [0x62,0xf2,0x7d,0x58,0x40,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_mullo_epi32_rmbk_512(<16 x i32> %a, i32* %ptr_b, <16 x i32> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi32_rmbk_512
+  ;CHECK: vpmulld (%rdi){1to16}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf2,0x7d,0x59,0x40,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+define <16 x i32> @test_mask_mullo_epi32_rmbkz_512(<16 x i32> %a, i32* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi32_rmbkz_512
+  ;CHECK: vpmulld (%rdi){1to16}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xd9,0x40,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
+  ret < 16 x i32> %res
+}
+
+declare <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
+
+define <16 x float> @test_mm512_maskz_add_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_add_round_ps_rn_sae
+  ;CHECK: vaddps {rn-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
+  %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 0)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_maskz_add_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_add_round_ps_rd_sae
+  ;CHECK: vaddps {rd-sae}, %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 1)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_maskz_add_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_add_round_ps_ru_sae
+  ;CHECK: vaddps  {ru-sae}, %zmm1, %zmm0, %zmm0  {%k1} {z}
+  %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 2)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_maskz_add_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_add_round_ps_rz_sae
+  ;CHECK: vaddps  {rz-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
+  %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 3)
+  ret <16 x float> %res
+}
+
+
+define <16 x float> @test_mm512_maskz_add_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_add_round_ps_current
+  ;CHECK: vaddps %zmm1, %zmm0, %zmm0 {%k1} {z}
+  %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 4)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_mask_add_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_add_round_ps_rn_sae
+  ;CHECK: vaddps {rn-sae}, %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 0)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_mask_add_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_add_round_ps_rd_sae
+  ;CHECK: vaddps {rd-sae}, %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 1)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_mask_add_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_add_round_ps_ru_sae
+  ;CHECK: vaddps  {ru-sae}, %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 2)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_mask_add_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_add_round_ps_rz_sae
+  ;CHECK: vaddps  {rz-sae}, %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 3)
+  ret <16 x float> %res
+}
+
+
+define <16 x float> @test_mm512_mask_add_round_ps_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_add_round_ps_current
+  ;CHECK: vaddps %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 4)
+  ret <16 x float> %res
+}
+
+
+define <16 x float> @test_mm512_add_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_add_round_ps_rn_sae
+  ;CHECK: vaddps {rn-sae}, %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 0)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_add_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_add_round_ps_rd_sae
+  ;CHECK: vaddps {rd-sae}, %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 1)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_add_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_add_round_ps_ru_sae
+  ;CHECK: vaddps  {ru-sae}, %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 2)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_add_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_add_round_ps_rz_sae
+  ;CHECK: vaddps  {rz-sae}, %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 3)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_add_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_add_round_ps_current
+  ;CHECK: vaddps %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 4)
+  ret <16 x float> %res
+}
+declare <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
+
+define <16 x float> @test_mm512_mask_sub_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_sub_round_ps_rn_sae
+  ;CHECK: vsubps {rn-sae}, %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 0)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_mask_sub_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_sub_round_ps_rd_sae
+  ;CHECK: vsubps {rd-sae}, %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 1)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_mask_sub_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_sub_round_ps_ru_sae
+  ;CHECK: vsubps  {ru-sae}, %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 2)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_mask_sub_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_sub_round_ps_rz_sae
+  ;CHECK: vsubps  {rz-sae}, %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 3)
+  ret <16 x float> %res
+}
+
+
+define <16 x float> @test_mm512_mask_sub_round_ps_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_sub_round_ps_current
+  ;CHECK: vsubps %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 4)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_sub_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_sub_round_ps_rn_sae
+  ;CHECK: vsubps {rn-sae}, %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 0)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_sub_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_sub_round_ps_rd_sae
+  ;CHECK: vsubps {rd-sae}, %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 1)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_sub_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_sub_round_ps_ru_sae
+  ;CHECK: vsubps  {ru-sae}, %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 2)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_sub_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_sub_round_ps_rz_sae
+  ;CHECK: vsubps  {rz-sae}, %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 3)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_sub_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_sub_round_ps_current
+  ;CHECK: vsubps %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 4)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_maskz_div_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_div_round_ps_rn_sae
+  ;CHECK: vdivps {rn-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
+  %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 0)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_maskz_div_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_div_round_ps_rd_sae
+  ;CHECK: vdivps {rd-sae}, %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 1)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_maskz_div_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_div_round_ps_ru_sae
+  ;CHECK: vdivps  {ru-sae}, %zmm1, %zmm0, %zmm0  {%k1} {z}
+  %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 2)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_maskz_div_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_div_round_ps_rz_sae
+  ;CHECK: vdivps  {rz-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
+  %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 3)
+  ret <16 x float> %res
+}
+
+
+define <16 x float> @test_mm512_maskz_div_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_div_round_ps_current
+  ;CHECK: vdivps %zmm1, %zmm0, %zmm0 {%k1} {z}
+  %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 4)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_mask_div_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_div_round_ps_rn_sae
+  ;CHECK: vdivps {rn-sae}, %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 0)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_mask_div_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_div_round_ps_rd_sae
+  ;CHECK: vdivps {rd-sae}, %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 1)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_mask_div_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_div_round_ps_ru_sae
+  ;CHECK: vdivps  {ru-sae}, %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 2)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_mask_div_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_div_round_ps_rz_sae
+  ;CHECK: vdivps  {rz-sae}, %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 3)
+  ret <16 x float> %res
+}
+
+
+define <16 x float> @test_mm512_mask_div_round_ps_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_div_round_ps_current
+  ;CHECK: vdivps %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 4)
+  ret <16 x float> %res
+}
+
+
+define <16 x float> @test_mm512_div_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_div_round_ps_rn_sae
+  ;CHECK: vdivps {rn-sae}, %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 0)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_div_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_div_round_ps_rd_sae
+  ;CHECK: vdivps {rd-sae}, %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 1)
+  ret <16 x float> %res
+}
+define <16 x float> @test_mm512_div_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_div_round_ps_ru_sae
+  ;CHECK: vdivps  {ru-sae}, %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 2)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_div_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_div_round_ps_rz_sae
+  ;CHECK: vdivps  {rz-sae}, %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 3)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_div_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_div_round_ps_current
+  ;CHECK: vdivps %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 4)
+  ret <16 x float> %res
+}
+declare <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
+
+define <16 x float> @test_mm512_maskz_min_round_ps_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_min_round_ps_sae
+  ;CHECK: vminps {sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
+  %res = call <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 8)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_maskz_min_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_min_round_ps_current
+  ;CHECK: vminps %zmm1, %zmm0, %zmm0 {%k1} {z}
+  %res = call <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 4)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_mask_min_round_ps_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_min_round_ps_sae
+  ;CHECK: vminps {sae}, %zmm1, %zmm0, %zmm2 {%k1}
+  %res = call <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 8)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_mask_min_round_ps_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_min_round_ps_current
+  ;CHECK: vminps %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 4)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_min_round_ps_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_min_round_ps_sae
+  ;CHECK: vminps {sae}, %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 8)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_min_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_min_round_ps_current
+  ;CHECK: vminps %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 4)
+  ret <16 x float> %res
+}
+declare <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
+
+define <16 x float> @test_mm512_maskz_max_round_ps_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_max_round_ps_sae
+  ;CHECK: vmaxps {sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
+  %res = call <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 8)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_maskz_max_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_max_round_ps_current
+  ;CHECK: vmaxps %zmm1, %zmm0, %zmm0 {%k1} {z}
+  %res = call <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 4)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_mask_max_round_ps_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_max_round_ps_sae
+  ;CHECK: vmaxps {sae}, %zmm1, %zmm0, %zmm2 {%k1}
+  %res = call <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 8)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_mask_max_round_ps_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_max_round_ps_current
+  ;CHECK: vmaxps %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 4)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_max_round_ps_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_max_round_ps_sae
+  ;CHECK: vmaxps {sae}, %zmm1, %zmm0, %zmm0 
+  %res = call <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 8)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mm512_max_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
+  ;CHECK-LABEL: test_mm512_max_round_ps_current
+  ;CHECK: vmaxps %zmm1, %zmm0, %zmm0
+  %res = call <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 4)
+  ret <16 x float> %res
+}
+declare <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
+
+declare <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone
+
+define <4 x float> @test_mask_add_ss_rn(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
+; CHECK-LABEL: test_mask_add_ss_rn
+; CHECK: vaddss  {rn-sae}, %xmm1, %xmm0, %xmm2 {%k1}
+  %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 0)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_add_ss_rd(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
+; CHECK-LABEL: test_mask_add_ss_rd
+; CHECK: vaddss  {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}
+  %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 1)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_add_ss_ru(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
+; CHECK-LABEL: test_mask_add_ss_ru
+; CHECK: vaddss  {ru-sae}, %xmm1, %xmm0, %xmm2 {%k1}
+  %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 2)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_add_ss_rz(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
+; CHECK-LABEL: test_mask_add_ss_rz
+; CHECK: vaddss  {rz-sae}, %xmm1, %xmm0, %xmm2 {%k1}
+  %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 3)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_add_ss_current(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
+; CHECK-LABEL: test_mask_add_ss_current
+; CHECK: vaddss %xmm1, %xmm0, %xmm2 {%k1}
+  %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 4)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_maskz_add_ss_rn(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
+; CHECK-LABEL: test_maskz_add_ss_rn
+; CHECK: vaddss  {rn-sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}
+  %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 0)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_add_ss_rn(<4 x float> %a0, <4 x float> %a1) {
+; CHECK-LABEL: test_add_ss_rn
+; CHECK: vaddss  {rn-sae}, %xmm1, %xmm0, %xmm0
+  %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 0)
+  ret <4 x float> %res
+}
+
+declare <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone
+
+define <2 x double> @test_mask_add_sd_rn(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
+; CHECK-LABEL: test_mask_add_sd_rn
+; CHECK: vaddsd  {rn-sae}, %xmm1, %xmm0, %xmm2 {%k1}
+  %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 0)
+  ret <2 x double> %res
+}
+
+define <2 x double> @test_mask_add_sd_rd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
+; CHECK-LABEL: test_mask_add_sd_rd
+; CHECK: vaddsd  {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}
+  %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 1)
+  ret <2 x double> %res
+}
+
+define <2 x double> @test_mask_add_sd_ru(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
+; CHECK-LABEL: test_mask_add_sd_ru
+; CHECK: vaddsd  {ru-sae}, %xmm1, %xmm0, %xmm2 {%k1}
+  %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 2)
+  ret <2 x double> %res
+}
+
+define <2 x double> @test_mask_add_sd_rz(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
+; CHECK-LABEL: test_mask_add_sd_rz
+; CHECK: vaddsd  {rz-sae}, %xmm1, %xmm0, %xmm2 {%k1}
+  %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 3)
+  ret <2 x double> %res
+}
+
+define <2 x double> @test_mask_add_sd_current(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
+; CHECK-LABEL: test_mask_add_sd_current
+; CHECK: vaddsd %xmm1, %xmm0, %xmm2 {%k1}
+  %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 4)
+  ret <2 x double> %res
+}
+
+define <2 x double> @test_maskz_add_sd_rn(<2 x double> %a0, <2 x double> %a1, i8 %mask) {
+; CHECK-LABEL: test_maskz_add_sd_rn
+; CHECK: vaddsd  {rn-sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}
+  %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 0)
+  ret <2 x double> %res
+}
+
+define <2 x double> @test_add_sd_rn(<2 x double> %a0, <2 x double> %a1) {
+; CHECK-LABEL: test_add_sd_rn
+; CHECK: vaddsd  {rn-sae}, %xmm1, %xmm0, %xmm0
+  %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 0)
+  ret <2 x double> %res
+}
+
+declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone
+
+define <4 x float> @test_mask_max_ss_sae(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
+; CHECK-LABEL: test_mask_max_ss_sae
+; CHECK: vmaxss  {sae}, %xmm1, %xmm0, %xmm2 {%k1}
+  %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 8)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_maskz_max_ss_sae(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
+; CHECK-LABEL: test_maskz_max_ss_sae
+; CHECK: vmaxss  {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}
+  %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 8)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_max_ss_sae(<4 x float> %a0, <4 x float> %a1) {
+; CHECK-LABEL: test_max_ss_sae
+; CHECK: vmaxss  {sae}, %xmm1, %xmm0, %xmm0
+  %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 8)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_max_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
+; CHECK-LABEL: test_mask_max_ss
+; CHECK: vmaxss  %xmm1, %xmm0, %xmm2 {%k1}
+  %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 4)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_maskz_max_ss(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
+; CHECK-LABEL: test_maskz_max_ss
+; CHECK: vmaxss  %xmm1, %xmm0, %xmm0 {%k1} {z}
+  %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 4)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_max_ss(<4 x float> %a0, <4 x float> %a1) {
+; CHECK-LABEL: test_max_ss
+; CHECK: vmaxss  %xmm1, %xmm0, %xmm0
+  %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 4)
+  ret <4 x float> %res
+}
+declare <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone
+
+define <2 x double> @test_mask_max_sd_sae(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
+; CHECK-LABEL: test_mask_max_sd_sae
+; CHECK: vmaxsd  {sae}, %xmm1, %xmm0, %xmm2 {%k1}
+  %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 8)
+  ret <2 x double> %res
+}
+
+define <2 x double> @test_maskz_max_sd_sae(<2 x double> %a0, <2 x double> %a1, i8 %mask) {
+; CHECK-LABEL: test_maskz_max_sd_sae
+; CHECK: vmaxsd  {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}
+  %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 8)
+  ret <2 x double> %res
+}
+
+define <2 x double> @test_max_sd_sae(<2 x double> %a0, <2 x double> %a1) {
+; CHECK-LABEL: test_max_sd_sae
+; CHECK: vmaxsd  {sae}, %xmm1, %xmm0, %xmm0
+  %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 8)
+  ret <2 x double> %res
+}
+
+define <2 x double> @test_mask_max_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
+; CHECK-LABEL: test_mask_max_sd
+; CHECK: vmaxsd  %xmm1, %xmm0, %xmm2 {%k1}
+  %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 4)
+  ret <2 x double> %res
+}
+
+define <2 x double> @test_maskz_max_sd(<2 x double> %a0, <2 x double> %a1, i8 %mask) {
+; CHECK-LABEL: test_maskz_max_sd
+; CHECK: vmaxsd  %xmm1, %xmm0, %xmm0 {%k1} {z}
+  %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 4)
+  ret <2 x double> %res
+}
+
+define <2 x double> @test_max_sd(<2 x double> %a0, <2 x double> %a1) {
+; CHECK-LABEL: test_max_sd
+; CHECK: vmaxsd  %xmm1, %xmm0, %xmm0
+  %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 4)
+  ret <2 x double> %res
+}
diff --git a/test/CodeGen/X86/avx512-logic.ll b/test/CodeGen/X86/avx512-logic.ll
index bee4f52b3216..140ce3b1ec56 100644
--- a/test/CodeGen/X86/avx512-logic.ll
+++ b/test/CodeGen/X86/avx512-logic.ll
@@ -83,7 +83,7 @@ define <8 x i64> @orq_broadcast(<8 x i64> %a) nounwind {
 ; CHECK: ret
 define <16 x i32> @andd512fold(<16 x i32> %y, <16 x i32>* %x) {
 entry:
-  %a = load <16 x i32>* %x, align 4
+  %a = load <16 x i32>, <16 x i32>* %x, align 4
   %b = and <16 x i32> %y, %a
   ret <16 x i32> %b
 }
@@ -93,7 +93,7 @@ entry:
 ; CHECK: ret
 define <8 x i64> @andqbrst(<8 x i64> %p1, i64* %ap) {
 entry:
-  %a = load i64* %ap, align 8
+  %a = load i64, i64* %ap, align 8
   %b = insertelement <8 x i64> undef, i64 %a, i32 0
   %c = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
   %d = and <8 x i64> %p1, %c
diff --git a/test/CodeGen/X86/avx512-mask-bugfix.ll b/test/CodeGen/X86/avx512-mask-bugfix.ll
new file mode 100755
index 000000000000..1940680f1c10
--- /dev/null
+++ b/test/CodeGen/X86/avx512-mask-bugfix.ll
@@ -0,0 +1,57 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl  | FileCheck %s
+
+; ModuleID = 'foo.ll'
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) #0
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.cttz.i64(i64, i1) #0
+
+; Function Attrs: nounwind
+define void @foo(float* noalias %aFOO, float %b, i32 %a) {
+allocas:
+  %full_mask_memory.i57 = alloca <8 x float>
+  %return_value_memory.i60 = alloca i1
+  %cmp.i = icmp eq i32 %a, 65535
+  br i1 %cmp.i, label %all_on, label %some_on
+
+all_on:
+  %mask0 = load <8 x float>, <8 x float>* %full_mask_memory.i57
+  %v0.i.i.i70 = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %mask0) #0
+  %allon.i.i76 = icmp eq i32 %v0.i.i.i70, 65535
+  br i1 %allon.i.i76, label %check_neighbors.i.i121, label %domixed.i.i100
+
+domixed.i.i100: 
+  br label %check_neighbors.i.i121
+
+check_neighbors.i.i121: 
+  %v1.i5.i.i116 = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %mask0) #0
+  %alleq.i.i120 = icmp eq i32 %v1.i5.i.i116, 65535
+  br i1 %alleq.i.i120, label %all_equal.i.i123, label %not_all_equal.i.i124
+
+; CHECK: kxnorw  %k0, %k0, %k0
+; CHECK: kshiftrw        $15, %k0, %k0
+; CHECK: jmp
+; CHECK: kxorw   %k0, %k0, %k0
+
+all_equal.i.i123:
+  br label %reduce_equal___vyi.exit128
+
+not_all_equal.i.i124:        
+  br label %reduce_equal___vyi.exit128
+
+reduce_equal___vyi.exit128:
+  %calltmp2.i125 = phi i1 [ true, %all_equal.i.i123 ], [ false, %not_all_equal.i.i124 ]
+  store i1 %calltmp2.i125, i1* %return_value_memory.i60
+  %return_value.i126 = load i1, i1* %return_value_memory.i60
+  %. = select i1 %return_value.i126, i32 1, i32 0
+  %select_to_float = sitofp i32 %. to float
+  ret void
+
+some_on:
+  ret void
+}
+
diff --git a/test/CodeGen/X86/avx512-mask-op.ll b/test/CodeGen/X86/avx512-mask-op.ll
index 35d334813fa8..d2efd7d6db6e 100644
--- a/test/CodeGen/X86/avx512-mask-op.ll
+++ b/test/CodeGen/X86/avx512-mask-op.ll
@@ -1,57 +1,68 @@
-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s --check-prefix=KNL --check-prefix=CHECK
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s --check-prefix=SKX --check-prefix=CHECK
 
+; CHECK-LABEL: mask16
+; CHECK: kmovw
+; CHECK-NEXT: knotw
+; CHECK-NEXT: kmovw
 define i16 @mask16(i16 %x) {
   %m0 = bitcast i16 %x to <16 x i1>
   %m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
   %ret = bitcast <16 x i1> %m1 to i16
   ret i16 %ret
-; CHECK-LABEL: mask16
-; CHECK: kmovw
-; CHECK-NEXT: knotw
-; CHECK-NEXT: kmovw
-; CHECK: ret
 }
 
+; CHECK-LABEL: mask8
+; KNL: kmovw
+; KNL-NEXT: knotw
+; KNL-NEXT: kmovw
+; SKX: kmovb
+; SKX-NEXT: knotb
+; SKX-NEXT: kmovb
+
 define i8 @mask8(i8 %x) {
   %m0 = bitcast i8 %x to <8 x i1>
   %m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
   %ret = bitcast <8 x i1> %m1 to i8
   ret i8 %ret
-; CHECK-LABEL: mask8
-; CHECK: kmovw
+}
+
+; CHECK-LABEL: mask16_mem
+; CHECK: kmovw ([[ARG1:%rdi|%rcx]]), %k{{[0-7]}}
 ; CHECK-NEXT: knotw
-; CHECK-NEXT: kmovw
+; CHECK-NEXT: kmovw %k{{[0-7]}}, ([[ARG1]])
 ; CHECK: ret
-}
 
 define void @mask16_mem(i16* %ptr) {
-  %x = load i16* %ptr, align 4
+  %x = load i16, i16* %ptr, align 4
   %m0 = bitcast i16 %x to <16 x i1>
   %m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
   %ret = bitcast <16 x i1> %m1 to i16
   store i16 %ret, i16* %ptr, align 4
   ret void
-; CHECK-LABEL: mask16_mem
-; CHECK: kmovw ([[ARG1:%rdi|%rcx]]), %k{{[0-7]}}
-; CHECK-NEXT: knotw
-; CHECK-NEXT: kmovw %k{{[0-7]}}, ([[ARG1]])
-; CHECK: ret
 }
 
+; CHECK-LABEL: mask8_mem
+; KNL: kmovw ([[ARG1]]), %k{{[0-7]}}
+; KNL-NEXT: knotw
+; KNL-NEXT: kmovw %k{{[0-7]}}, ([[ARG1]])
+; SKX: kmovb ([[ARG1]]), %k{{[0-7]}}
+; SKX-NEXT: knotb
+; SKX-NEXT: kmovb %k{{[0-7]}}, ([[ARG1]])
+
 define void @mask8_mem(i8* %ptr) {
-  %x = load i8* %ptr, align 4
+  %x = load i8, i8* %ptr, align 4
   %m0 = bitcast i8 %x to <8 x i1>
   %m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
   %ret = bitcast <8 x i1> %m1 to i8
   store i8 %ret, i8* %ptr, align 4
   ret void
-; CHECK-LABEL: mask8_mem
-; CHECK: kmovw ([[ARG1]]), %k{{[0-7]}}
-; CHECK-NEXT: knotw
-; CHECK-NEXT: kmovw %k{{[0-7]}}, ([[ARG1]])
-; CHECK: ret
 }
 
+; CHECK-LABEL: mand16
+; CHECK: kandw
+; CHECK: kxorw
+; CHECK: korw
 define i16 @mand16(i16 %x, i16 %y) {
   %ma = bitcast i16 %x to <16 x i1>
   %mb = bitcast i16 %y to <16 x i1>
@@ -59,15 +70,11 @@ define i16 @mand16(i16 %x, i16 %y) {
   %md = xor <16 x i1> %ma, %mb
   %me = or <16 x i1> %mc, %md
   %ret = bitcast <16 x i1> %me to i16
-; CHECK: kandw
-; CHECK: kxorw
-; CHECK: korw
   ret i16 %ret
 }
 
-; CHECK: shuf_test1
+; CHECK-LABEL: shuf_test1
 ; CHECK: kshiftrw        $8
-; CHECK:ret
 define i8 @shuf_test1(i16 %v) nounwind {
    %v1 = bitcast i16 %v to <16 x i1>
    %mask = shufflevector <16 x i1> %v1, <16 x i1> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -75,11 +82,11 @@ define i8 @shuf_test1(i16 %v) nounwind {
    ret i8 %mask1
 }
 
-; CHECK: zext_test1
+; CHECK-LABEL: zext_test1
 ; CHECK: kshiftlw
 ; CHECK: kshiftrw
 ; CHECK: kmovw
-; CHECK:ret
+
 define i32 @zext_test1(<16 x i32> %a, <16 x i32> %b) {
   %cmp_res = icmp ugt <16 x i32> %a, %b
   %cmp_res.i1 = extractelement <16 x i1> %cmp_res, i32 5
@@ -87,11 +94,11 @@ define i32 @zext_test1(<16 x i32> %a, <16 x i32> %b) {
   ret i32 %res
 }
 
-; CHECK: zext_test2
+; CHECK-LABEL: zext_test2
 ; CHECK: kshiftlw
 ; CHECK: kshiftrw
 ; CHECK: kmovw
-; CHECK:ret
+
 define i16 @zext_test2(<16 x i32> %a, <16 x i32> %b) {
   %cmp_res = icmp ugt <16 x i32> %a, %b
   %cmp_res.i1 = extractelement <16 x i1> %cmp_res, i32 5
@@ -99,14 +106,304 @@ define i16 @zext_test2(<16 x i32> %a, <16 x i32> %b) {
   ret i16 %res
 }
 
-; CHECK: zext_test3
+; CHECK-LABEL: zext_test3
 ; CHECK: kshiftlw
 ; CHECK: kshiftrw
 ; CHECK: kmovw
-; CHECK:ret
+
 define i8 @zext_test3(<16 x i32> %a, <16 x i32> %b) {
   %cmp_res = icmp ugt <16 x i32> %a, %b
   %cmp_res.i1 = extractelement <16 x i1> %cmp_res, i32 5
   %res = zext i1 %cmp_res.i1 to i8
   ret i8 %res
 }
+
+; CHECK-LABEL: conv1
+; KNL: kmovw   %k0, %eax
+; KNL: movb    %al, (%rdi)
+; SKX: kmovb   %k0, (%rdi)
+define i8 @conv1(<8 x i1>* %R) {
+entry:
+  store <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <8 x i1>* %R
+
+  %maskPtr = alloca <8 x i1>
+  store <8 x i1> <i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <8 x i1>* %maskPtr
+  %mask = load <8 x i1>, <8 x i1>* %maskPtr
+  %mask_convert = bitcast <8 x i1> %mask to i8
+  ret i8 %mask_convert
+}
+
+; SKX-LABEL: test4
+; SKX: vpcmpgt
+; SKX: knot
+; SKX: vpcmpgt
+; SKX: vpmovm2d
+define <4 x i32> @test4(<4 x i64> %x, <4 x i64> %y, <4 x i64> %x1, <4 x i64> %y1) {
+  %x_gt_y = icmp sgt <4 x i64> %x, %y
+  %x1_gt_y1 = icmp sgt <4 x i64> %x1, %y1
+  %res = icmp sgt <4 x i1>%x_gt_y, %x1_gt_y1
+  %resse = sext <4 x i1>%res to <4 x i32>
+  ret <4 x i32> %resse
+}
+
+; SKX-LABEL: test5
+; SKX: vpcmpgt
+; SKX: knot
+; SKX: vpcmpgt
+; SKX: vpmovm2q
+define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y, <2 x i64> %x1, <2 x i64> %y1) {
+  %x_gt_y = icmp slt <2 x i64> %x, %y
+  %x1_gt_y1 = icmp sgt <2 x i64> %x1, %y1
+  %res = icmp slt <2 x i1>%x_gt_y, %x1_gt_y1
+  %resse = sext <2 x i1>%res to <2 x i64>
+  ret <2 x i64> %resse
+}
+
+; KNL-LABEL: test6
+; KNL: vpmovsxbd
+; KNL: vpandd
+; KNL: kmovw   %eax, %k1
+; KNL vptestmd {{.*}}, %k0 {%k1}
+
+; SKX-LABEL: test6
+; SKX: vpmovb2m
+; SKX: kmovw   %eax, %k1
+; SKX: kandw
+define void @test6(<16 x i1> %mask)  {
+allocas:
+  %a= and <16 x i1> %mask, <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>
+  %b = bitcast <16 x i1> %a to i16
+  %c = icmp eq i16 %b, 0
+  br i1 %c, label %true, label %false
+
+true:
+  ret void
+
+false:
+  ret void
+}
+
+; KNL-LABEL: test7
+; KNL: vpmovsxwq
+; KNL: vpandq
+; KNL: vptestmq {{.*}}, %k0
+; KNL: korw
+
+; SKX-LABEL: test7
+; SKX: vpmovw2m
+; SKX: kmovb   %eax, %k1
+; SKX: korb
+
+define void @test7(<8 x i1> %mask)  {
+allocas:
+  %a= or <8 x i1> %mask, <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>
+  %b = bitcast <8 x i1> %a to i8
+  %c = icmp eq i8 %b, 0
+  br i1 %c, label %true, label %false
+
+true:
+  ret void
+
+false:
+  ret void
+}
+
+; KNL-LABEL: test8
+; KNL: vpxord  %zmm2, %zmm2, %zmm2
+; KNL: jg
+; KNL: vpcmpltud       %zmm2, %zmm1, %k1
+; KNL: jmp
+; KNL: vpcmpgtd        %zmm2, %zmm0, %k1
+
+; SKX-LABEL: test8
+; SKX: jg
+; SKX: vpcmpltud {{.*}}, %k0
+; SKX: vpmovm2b
+; SKX: vpcmpgtd {{.*}}, %k0
+; SKX: vpmovm2b
+
+define <16 x i8> @test8(<16 x i32>%a, <16 x i32>%b, i32 %a1, i32 %b1) {
+  %cond = icmp sgt i32 %a1, %b1
+  %cmp1 = icmp sgt <16 x i32> %a, zeroinitializer
+  %cmp2 = icmp ult <16 x i32> %b, zeroinitializer
+  %mix = select i1 %cond, <16 x i1> %cmp1, <16 x i1> %cmp2
+  %res = sext <16 x i1> %mix to <16 x i8>
+  ret <16 x i8> %res
+}
+
+; KNL-LABEL: test9
+; KNL: jg
+; KNL: vpmovsxbd       %xmm1, %zmm0
+; KNL: jmp
+; KNL: vpmovsxbd       %xmm0, %zmm0
+
+; SKX-LABEL: test9
+; SKX: vpmovb2m        %xmm1, %k0
+; SKX: vpmovm2b        %k0, %xmm0
+; SKX: retq
+; SKX: vpmovb2m        %xmm0, %k0
+; SKX: vpmovm2b        %k0, %xmm0
+
+define <16 x i1> @test9(<16 x i1>%a, <16 x i1>%b, i32 %a1, i32 %b1) {
+  %mask = icmp sgt i32 %a1, %b1
+  %c = select i1 %mask, <16 x i1>%a, <16 x i1>%b
+  ret <16 x i1>%c
+}
+
+; KNL-LABEL: test10
+; KNL: jg
+; KNL: vpmovsxwq       %xmm1, %zmm0
+; KNL: jmp
+; KNL: vpmovsxwq       %xmm0, %zmm0
+
+; SKX-LABEL: test10
+; SKX: jg
+; SKX: vpmovw2m        %xmm1, %k0
+; SKX: vpmovm2w        %k0, %xmm0
+; SKX: retq
+; SKX: vpmovw2m        %xmm0, %k0
+; SKX: vpmovm2w        %k0, %xmm0
+define <8 x i1> @test10(<8 x i1>%a, <8 x i1>%b, i32 %a1, i32 %b1) {
+  %mask = icmp sgt i32 %a1, %b1
+  %c = select i1 %mask, <8 x i1>%a, <8 x i1>%b
+  ret <8 x i1>%c
+}
+
+; SKX-LABEL: test11
+; SKX: jg
+; SKX: vpmovd2m        %xmm1, %k0
+; SKX: vpmovm2d        %k0, %xmm0
+; SKX: retq
+; SKX: vpmovd2m        %xmm0, %k0
+; SKX: vpmovm2d        %k0, %xmm0
+define <4 x i1> @test11(<4 x i1>%a, <4 x i1>%b, i32 %a1, i32 %b1) {
+  %mask = icmp sgt i32 %a1, %b1
+  %c = select i1 %mask, <4 x i1>%a, <4 x i1>%b
+  ret <4 x i1>%c
+}
+
+; KNL-LABEL: test12
+; KNL: movl    %edi, %eax
+define i32 @test12(i32 %x, i32 %y)  {
+  %a = bitcast i16 21845 to <16 x i1>
+  %b = extractelement <16 x i1> %a, i32 0
+  %c = select i1 %b, i32 %x, i32 %y
+  ret i32 %c
+}
+
+; KNL-LABEL: test13
+; KNL: movl    %esi, %eax
+define i32 @test13(i32 %x, i32 %y)  {
+  %a = bitcast i16 21845 to <16 x i1>
+  %b = extractelement <16 x i1> %a, i32 3
+  %c = select i1 %b, i32 %x, i32 %y
+  ret i32 %c
+}
+
+; SKX-LABEL: test14
+; SKX: movb     $11, %al
+; SKX: kmovb    %eax, %k0
+; SKX: vpmovm2d %k0, %xmm0
+
+define <4 x i1> @test14()  {
+  %a = bitcast i16 21845 to <16 x i1>
+  %b = extractelement <16 x i1> %a, i32 2
+  %c = insertelement <4 x i1> <i1 true, i1 false, i1 false, i1 true>, i1 %b, i32 1
+  ret <4 x i1> %c
+}
+
+; KNL-LABEL: test15
+; KNL: cmovgw
+define <16 x i1> @test15(i32 %x, i32 %y)  {
+  %a = bitcast i16 21845 to <16 x i1>
+  %b = bitcast i16 1 to <16 x i1>
+  %mask = icmp sgt i32 %x, %y
+  %c = select i1 %mask, <16 x i1> %a, <16 x i1> %b
+  ret <16 x i1> %c
+}
+
+; SKX-LABEL: test16
+; SKX: kxnorw  %k1, %k1, %k1
+; SKX: kshiftrw        $15, %k1, %k1
+; SKX: kshiftlq        $5, %k1, %k1
+; SKX: korq    %k1, %k0, %k0
+; SKX: vpmovm2b        %k0, %zmm0
+define <64 x i8> @test16(i64 %x) {
+  %a = bitcast i64 %x to <64 x i1>
+  %b = insertelement <64 x i1>%a, i1 true, i32 5
+  %c = sext <64 x i1>%b to <64 x i8>
+  ret <64 x i8>%c
+}
+
+; SKX-LABEL: test17
+; SKX: setg    %al
+; SKX: andl    $1, %eax
+; SKX: kmovw   %eax, %k1
+; SKX: kshiftlq        $5, %k1, %k1
+; SKX: korq    %k1, %k0, %k0
+; SKX: vpmovm2b        %k0, %zmm0
+define <64 x i8> @test17(i64 %x, i32 %y, i32 %z) {
+  %a = bitcast i64 %x to <64 x i1>
+  %b = icmp sgt i32 %y, %z
+  %c = insertelement <64 x i1>%a, i1 %b, i32 5
+  %d = sext <64 x i1>%c to <64 x i8>
+  ret <64 x i8>%d
+}
+
+; KNL-LABEL: test18
+define <8 x i1> @test18(i8 %a, i16 %y) {
+  %b = bitcast i8 %a to <8 x i1>
+  %b1 = bitcast i16 %y to <16 x i1>
+  %el1 = extractelement <16 x i1>%b1, i32 8
+  %el2 = extractelement <16 x i1>%b1, i32 9
+  %c = insertelement <8 x i1>%b, i1 %el1, i32 7
+  %d = insertelement <8 x i1>%c, i1 %el2, i32 6
+  ret <8 x i1>%d
+}
+
+; KNL-LABEL: test19
+; KNL: movzbl  %dil, %eax
+; KNL: kmovw   %eax, %k0
+; KNL: kshiftlw        $13, %k0, %k0
+; KNL: kshiftrw        $15, %k0, %k0
+; KNL: kmovw   %k0, %eax
+; KNL: andl    $1, %eax
+; KNL: testb   %al, %al
+
+define <8 x i1> @test19(i8 %a) {
+  %b = bitcast i8 %a to <8 x i1>
+  %c = shufflevector < 8 x i1>%b, <8 x i1>undef, <8 x i32> <i32 undef, i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 undef>
+  ret <8 x i1> %c
+}
+
+; KNL-LABEL: test20
+; KNL: movzbl  %dil, %eax
+; KNL: kmovw   %eax, %k0
+; KNL: kshiftlw        $13, %k0, %k1
+; KNL: kshiftrw        $15, %k1, %k1
+; KNL: kshiftlw        $12, %k0, %k0
+; KNL: kshiftrw        $15, %k0, %k0
+; KNL: kshiftlw        $4, %k0, %k0
+; KNL: kshiftlw        $1, %k1, %k2
+; KNL: korw    %k0, %k2, %k0
+; KNL: kshiftlw        $6, %k1, %k1
+; KNL: korw    %k1, %k0, %k1
+define <8 x i1> @test20(i8 %a, i16 %y) {
+  %b = bitcast i8 %a to <8 x i1>
+  %c = shufflevector < 8 x i1>%b, <8 x i1>undef, <8 x i32> <i32 undef, i32 2, i32 undef, i32 undef, i32 3, i32 undef, i32 2, i32 undef>
+  ret <8 x i1> %c
+}
+
+; KNL-LABEL: test21
+; KNL: vpand %ymm
+; KNL: vextracti128    $1, %ymm2
+; KNL: vpand %ymm
+
+; SKX-LABEL: test21
+; SKX: vpmovb2m
+; SKX: vmovdqu16 {{.*}}%k1
+
+define <32 x i16> @test21(<32 x i16> %x , <32 x i1> %mask) nounwind readnone {
+  %ret = select <32 x i1> %mask, <32 x i16> %x, <32 x i16> zeroinitializer
+  ret <32 x i16> %ret
+}
diff --git a/test/CodeGen/X86/avx512-mov.ll b/test/CodeGen/X86/avx512-mov.ll
index 93875e839e22..0cd8458f73f5 100644
--- a/test/CodeGen/X86/avx512-mov.ll
+++ b/test/CodeGen/X86/avx512-mov.ll
@@ -28,7 +28,7 @@ define <2 x i64> @test3(i64 %x) {
 ; CHECK: vmovd  (%rdi), %xmm0 ## encoding: [0x62
 ; CHECK: ret
 define <4 x i32> @test4(i32* %x) {
-   %y = load i32* %x
+   %y = load i32, i32* %x
    %res = insertelement <4 x i32>undef, i32 %y, i32 0
    ret <4 x i32>%res
 }
@@ -53,7 +53,7 @@ define void @test6(double %x, double* %y) {
 ; CHECK: vmovss  (%rdi), %xmm0 ## encoding: [0x62
 ; CHECK: ret
 define float @test7(i32* %x) {
-   %y = load i32* %x
+   %y = load i32, i32* %x
    %res = bitcast i32 %y to float
    ret float %res
 }
@@ -78,7 +78,7 @@ define i64 @test9(<2 x i64> %x) {
 ; CHECK: vmovd (%rdi), %xmm0 ## encoding: [0x62
 ; CHECK: ret
 define <4 x i32> @test10(i32* %x) {
-   %y = load i32* %x, align 4
+   %y = load i32, i32* %x, align 4
    %res = insertelement <4 x i32>zeroinitializer, i32 %y, i32 0
    ret <4 x i32>%res
 }
@@ -87,7 +87,7 @@ define <4 x i32> @test10(i32* %x) {
 ; CHECK: vmovss  (%rdi), %xmm0 ## encoding: [0x62
 ; CHECK: ret
 define <4 x float> @test11(float* %x) {
-   %y = load float* %x, align 4
+   %y = load float, float* %x, align 4
    %res = insertelement <4 x float>zeroinitializer, float %y, i32 0
    ret <4 x float>%res
 }
@@ -96,7 +96,7 @@ define <4 x float> @test11(float* %x) {
 ; CHECK: vmovsd  (%rdi), %xmm0 ## encoding: [0x62
 ; CHECK: ret
 define <2 x double> @test12(double* %x) {
-   %y = load double* %x, align 8
+   %y = load double, double* %x, align 8
    %res = insertelement <2 x double>zeroinitializer, double %y, i32 0
    ret <2 x double>%res
 }
@@ -121,7 +121,7 @@ define <4 x i32> @test14(i32 %x) {
 ; CHECK: vmovd  (%rdi), %xmm0 ## encoding: [0x62
 ; CHECK: ret
 define <4 x i32> @test15(i32* %x) {
-   %y = load i32* %x, align 4
+   %y = load i32, i32* %x, align 4
    %res = insertelement <4 x i32>zeroinitializer, i32 %y, i32 0
    ret <4 x i32>%res
 }
@@ -131,7 +131,7 @@ define <4 x i32> @test15(i32* %x) {
 ; CHECK: ret
 define <16 x i32> @test16(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <16 x i32>*
-  %res = load <16 x i32>* %vaddr, align 1
+  %res = load <16 x i32>, <16 x i32>* %vaddr, align 1
   ret <16 x i32>%res
 }
 
@@ -140,7 +140,7 @@ define <16 x i32> @test16(i8 * %addr) {
 ; CHECK: ret
 define <16 x i32> @test17(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <16 x i32>*
-  %res = load <16 x i32>* %vaddr, align 64
+  %res = load <16 x i32>, <16 x i32>* %vaddr, align 64
   ret <16 x i32>%res
 }
 
@@ -176,7 +176,7 @@ define void @test20(i8 * %addr, <16 x i32> %data) {
 ; CHECK: ret
 define  <8 x i64> @test21(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <8 x i64>*
-  %res = load <8 x i64>* %vaddr, align 64
+  %res = load <8 x i64>, <8 x i64>* %vaddr, align 64
   ret <8 x i64>%res
 }
 
@@ -194,7 +194,7 @@ define void @test22(i8 * %addr, <8 x i64> %data) {
 ; CHECK: ret
 define <8 x i64> @test23(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <8 x i64>*
-  %res = load <8 x i64>* %vaddr, align 1
+  %res = load <8 x i64>, <8 x i64>* %vaddr, align 1
   ret <8 x i64>%res
 }
 
@@ -212,7 +212,7 @@ define void @test24(i8 * %addr, <8 x double> %data) {
 ; CHECK: ret
 define <8 x double> @test25(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <8 x double>*
-  %res = load <8 x double>* %vaddr, align 64
+  %res = load <8 x double>, <8 x double>* %vaddr, align 64
   ret <8 x double>%res
 }
 
@@ -230,7 +230,7 @@ define void @test26(i8 * %addr, <16 x float> %data) {
 ; CHECK: ret
 define <16 x float> @test27(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <16 x float>*
-  %res = load <16 x float>* %vaddr, align 64
+  %res = load <16 x float>, <16 x float>* %vaddr, align 64
   ret <16 x float>%res
 }
 
@@ -248,7 +248,7 @@ define void @test28(i8 * %addr, <8 x double> %data) {
 ; CHECK: ret
 define <8 x double> @test29(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <8 x double>*
-  %res = load <8 x double>* %vaddr, align 1
+  %res = load <8 x double>, <8 x double>* %vaddr, align 1
   ret <8 x double>%res
 }
 
@@ -266,7 +266,7 @@ define void @test30(i8 * %addr, <16 x float> %data) {
 ; CHECK: ret
 define <16 x float> @test31(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <16 x float>*
-  %res = load <16 x float>* %vaddr, align 1
+  %res = load <16 x float>, <16 x float>* %vaddr, align 1
   ret <16 x float>%res
 }
 
@@ -276,7 +276,7 @@ define <16 x float> @test31(i8 * %addr) {
 define <16 x i32> @test32(i8 * %addr, <16 x i32> %old, <16 x i32> %mask1) {
   %mask = icmp ne <16 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <16 x i32>*
-  %r = load <16 x i32>* %vaddr, align 64
+  %r = load <16 x i32>, <16 x i32>* %vaddr, align 64
   %res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> %old
   ret <16 x i32>%res
 }
@@ -287,7 +287,7 @@ define <16 x i32> @test32(i8 * %addr, <16 x i32> %old, <16 x i32> %mask1) {
 define <16 x i32> @test33(i8 * %addr, <16 x i32> %old, <16 x i32> %mask1) {
   %mask = icmp ne <16 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <16 x i32>*
-  %r = load <16 x i32>* %vaddr, align 1
+  %r = load <16 x i32>, <16 x i32>* %vaddr, align 1
   %res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> %old
   ret <16 x i32>%res
 }
@@ -298,7 +298,7 @@ define <16 x i32> @test33(i8 * %addr, <16 x i32> %old, <16 x i32> %mask1) {
 define <16 x i32> @test34(i8 * %addr, <16 x i32> %mask1) {
   %mask = icmp ne <16 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <16 x i32>*
-  %r = load <16 x i32>* %vaddr, align 64
+  %r = load <16 x i32>, <16 x i32>* %vaddr, align 64
   %res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> zeroinitializer
   ret <16 x i32>%res
 }
@@ -309,7 +309,7 @@ define <16 x i32> @test34(i8 * %addr, <16 x i32> %mask1) {
 define <16 x i32> @test35(i8 * %addr, <16 x i32> %mask1) {
   %mask = icmp ne <16 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <16 x i32>*
-  %r = load <16 x i32>* %vaddr, align 1
+  %r = load <16 x i32>, <16 x i32>* %vaddr, align 1
   %res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> zeroinitializer
   ret <16 x i32>%res
 }
@@ -320,7 +320,7 @@ define <16 x i32> @test35(i8 * %addr, <16 x i32> %mask1) {
 define <8 x i64> @test36(i8 * %addr, <8 x i64> %old, <8 x i64> %mask1) {
   %mask = icmp ne <8 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x i64>*
-  %r = load <8 x i64>* %vaddr, align 64
+  %r = load <8 x i64>, <8 x i64>* %vaddr, align 64
   %res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> %old
   ret <8 x i64>%res
 }
@@ -331,7 +331,7 @@ define <8 x i64> @test36(i8 * %addr, <8 x i64> %old, <8 x i64> %mask1) {
 define <8 x i64> @test37(i8 * %addr, <8 x i64> %old, <8 x i64> %mask1) {
   %mask = icmp ne <8 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x i64>*
-  %r = load <8 x i64>* %vaddr, align 1
+  %r = load <8 x i64>, <8 x i64>* %vaddr, align 1
   %res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> %old
   ret <8 x i64>%res
 }
@@ -342,7 +342,7 @@ define <8 x i64> @test37(i8 * %addr, <8 x i64> %old, <8 x i64> %mask1) {
 define <8 x i64> @test38(i8 * %addr, <8 x i64> %mask1) {
   %mask = icmp ne <8 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x i64>*
-  %r = load <8 x i64>* %vaddr, align 64
+  %r = load <8 x i64>, <8 x i64>* %vaddr, align 64
   %res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> zeroinitializer
   ret <8 x i64>%res
 }
@@ -353,7 +353,7 @@ define <8 x i64> @test38(i8 * %addr, <8 x i64> %mask1) {
 define <8 x i64> @test39(i8 * %addr, <8 x i64> %mask1) {
   %mask = icmp ne <8 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x i64>*
-  %r = load <8 x i64>* %vaddr, align 1
+  %r = load <8 x i64>, <8 x i64>* %vaddr, align 1
   %res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> zeroinitializer
   ret <8 x i64>%res
 }
@@ -364,7 +364,7 @@ define <8 x i64> @test39(i8 * %addr, <8 x i64> %mask1) {
 define <16 x float> @test40(i8 * %addr, <16 x float> %old, <16 x float> %mask1) {
   %mask = fcmp one <16 x float> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <16 x float>*
-  %r = load <16 x float>* %vaddr, align 64
+  %r = load <16 x float>, <16 x float>* %vaddr, align 64
   %res = select <16 x i1> %mask, <16 x float> %r, <16 x float> %old
   ret <16 x float>%res
 }
@@ -375,7 +375,7 @@ define <16 x float> @test40(i8 * %addr, <16 x float> %old, <16 x float> %mask1)
 define <16 x float> @test41(i8 * %addr, <16 x float> %old, <16 x float> %mask1) {
   %mask = fcmp one <16 x float> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <16 x float>*
-  %r = load <16 x float>* %vaddr, align 1
+  %r = load <16 x float>, <16 x float>* %vaddr, align 1
   %res = select <16 x i1> %mask, <16 x float> %r, <16 x float> %old
   ret <16 x float>%res
 }
@@ -386,7 +386,7 @@ define <16 x float> @test41(i8 * %addr, <16 x float> %old, <16 x float> %mask1)
 define <16 x float> @test42(i8 * %addr, <16 x float> %mask1) {
   %mask = fcmp one <16 x float> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <16 x float>*
-  %r = load <16 x float>* %vaddr, align 64
+  %r = load <16 x float>, <16 x float>* %vaddr, align 64
   %res = select <16 x i1> %mask, <16 x float> %r, <16 x float> zeroinitializer
   ret <16 x float>%res
 }
@@ -397,7 +397,7 @@ define <16 x float> @test42(i8 * %addr, <16 x float> %mask1) {
 define <16 x float> @test43(i8 * %addr, <16 x float> %mask1) {
   %mask = fcmp one <16 x float> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <16 x float>*
-  %r = load <16 x float>* %vaddr, align 1
+  %r = load <16 x float>, <16 x float>* %vaddr, align 1
   %res = select <16 x i1> %mask, <16 x float> %r, <16 x float> zeroinitializer
   ret <16 x float>%res
 }
@@ -408,7 +408,7 @@ define <16 x float> @test43(i8 * %addr, <16 x float> %mask1) {
 define <8 x double> @test44(i8 * %addr, <8 x double> %old, <8 x double> %mask1) {
   %mask = fcmp one <8 x double> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x double>*
-  %r = load <8 x double>* %vaddr, align 64
+  %r = load <8 x double>, <8 x double>* %vaddr, align 64
   %res = select <8 x i1> %mask, <8 x double> %r, <8 x double> %old
   ret <8 x double>%res
 }
@@ -419,7 +419,7 @@ define <8 x double> @test44(i8 * %addr, <8 x double> %old, <8 x double> %mask1)
 define <8 x double> @test45(i8 * %addr, <8 x double> %old, <8 x double> %mask1) {
   %mask = fcmp one <8 x double> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x double>*
-  %r = load <8 x double>* %vaddr, align 1
+  %r = load <8 x double>, <8 x double>* %vaddr, align 1
   %res = select <8 x i1> %mask, <8 x double> %r, <8 x double> %old
   ret <8 x double>%res
 }
@@ -430,7 +430,7 @@ define <8 x double> @test45(i8 * %addr, <8 x double> %old, <8 x double> %mask1)
 define <8 x double> @test46(i8 * %addr, <8 x double> %mask1) {
   %mask = fcmp one <8 x double> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x double>*
-  %r = load <8 x double>* %vaddr, align 64
+  %r = load <8 x double>, <8 x double>* %vaddr, align 64
   %res = select <8 x i1> %mask, <8 x double> %r, <8 x double> zeroinitializer
   ret <8 x double>%res
 }
@@ -441,7 +441,7 @@ define <8 x double> @test46(i8 * %addr, <8 x double> %mask1) {
 define <8 x double> @test47(i8 * %addr, <8 x double> %mask1) {
   %mask = fcmp one <8 x double> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x double>*
-  %r = load <8 x double>* %vaddr, align 1
+  %r = load <8 x double>, <8 x double>* %vaddr, align 1
   %res = select <8 x i1> %mask, <8 x double> %r, <8 x double> zeroinitializer
   ret <8 x double>%res
 }
diff --git a/test/CodeGen/X86/avx512-round.ll b/test/CodeGen/X86/avx512-round.ll
new file mode 100644
index 000000000000..c4f417e75ab0
--- /dev/null
+++ b/test/CodeGen/X86/avx512-round.ll
@@ -0,0 +1,106 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s
+
+define <16 x float> @floor_v16f32(<16 x float> %a) {
+; CHECK-LABEL: floor_v16f32
+; CHECK: vrndscaleps $1, {{.*}}encoding: [0x62,0xf3,0x7d,0x48,0x08,0xc0,0x01]
+  %res = call <16 x float> @llvm.floor.v16f32(<16 x float> %a)
+  ret <16 x float> %res
+}
+declare <16 x float> @llvm.floor.v16f32(<16 x float> %p)
+
+define <8 x double> @floor_v8f64(<8 x double> %a) {
+; CHECK-LABEL: floor_v8f64
+; CHECK: vrndscalepd $1, {{.*}}encoding: [0x62,0xf3,0xfd,0x48,0x09,0xc0,0x01]
+  %res = call <8 x double> @llvm.floor.v8f64(<8 x double> %a)
+  ret <8 x double> %res
+}
+declare <8 x double> @llvm.floor.v8f64(<8 x double> %p)
+
+define <16 x float> @ceil_v16f32(<16 x float> %a) {
+; CHECK-LABEL: ceil_v16f32
+; CHECK: vrndscaleps $2, {{.*}}encoding: [0x62,0xf3,0x7d,0x48,0x08,0xc0,0x02]
+  %res = call <16 x float> @llvm.ceil.v16f32(<16 x float> %a)
+  ret <16 x float> %res
+}
+declare <16 x float> @llvm.ceil.v16f32(<16 x float> %p)
+
+define <8 x double> @ceil_v8f64(<8 x double> %a) {
+; CHECK-LABEL: ceil_v8f64
+; CHECK: vrndscalepd $2, {{.*}}encoding: [0x62,0xf3,0xfd,0x48,0x09,0xc0,0x02]
+  %res = call <8 x double> @llvm.ceil.v8f64(<8 x double> %a)
+  ret <8 x double> %res
+}
+declare <8 x double> @llvm.ceil.v8f64(<8 x double> %p)
+
+define <16 x float> @trunc_v16f32(<16 x float> %a) {
+; CHECK-LABEL: trunc_v16f32
+; CHECK: vrndscaleps $3, {{.*}}encoding: [0x62,0xf3,0x7d,0x48,0x08,0xc0,0x03]
+  %res = call <16 x float> @llvm.trunc.v16f32(<16 x float> %a)
+  ret <16 x float> %res
+}
+declare <16 x float> @llvm.trunc.v16f32(<16 x float> %p)
+
+define <8 x double> @trunc_v8f64(<8 x double> %a) {
+; CHECK-LABEL: trunc_v8f64
+; CHECK: vrndscalepd $3, {{.*}}encoding: [0x62,0xf3,0xfd,0x48,0x09,0xc0,0x03]
+  %res = call <8 x double> @llvm.trunc.v8f64(<8 x double> %a)
+  ret <8 x double> %res
+}
+declare <8 x double> @llvm.trunc.v8f64(<8 x double> %p)
+
+define <16 x float> @rint_v16f32(<16 x float> %a) {
+; CHECK-LABEL: rint_v16f32
+; CHECK: vrndscaleps $4, {{.*}}encoding: [0x62,0xf3,0x7d,0x48,0x08,0xc0,0x04]
+  %res = call <16 x float> @llvm.rint.v16f32(<16 x float> %a)
+  ret <16 x float> %res
+}
+declare <16 x float> @llvm.rint.v16f32(<16 x float> %p)
+
+define <8 x double> @rint_v8f64(<8 x double> %a) {
+; CHECK-LABEL: rint_v8f64
+; CHECK: vrndscalepd $4, {{.*}}encoding: [0x62,0xf3,0xfd,0x48,0x09,0xc0,0x04]
+  %res = call <8 x double> @llvm.rint.v8f64(<8 x double> %a)
+  ret <8 x double> %res
+}
+declare <8 x double> @llvm.rint.v8f64(<8 x double> %p)
+
+define <16 x float> @nearbyint_v16f32(<16 x float> %a) {
+; CHECK-LABEL: nearbyint_v16f32
+; CHECK: vrndscaleps $12, {{.*}}encoding: [0x62,0xf3,0x7d,0x48,0x08,0xc0,0x0c]
+  %res = call <16 x float> @llvm.nearbyint.v16f32(<16 x float> %a)
+  ret <16 x float> %res
+}
+declare <16 x float> @llvm.nearbyint.v16f32(<16 x float> %p)
+
+define <8 x double> @nearbyint_v8f64(<8 x double> %a) {
+; CHECK-LABEL: nearbyint_v8f64
+; CHECK: vrndscalepd $12, {{.*}}encoding: [0x62,0xf3,0xfd,0x48,0x09,0xc0,0x0c]
+  %res = call <8 x double> @llvm.nearbyint.v8f64(<8 x double> %a)
+  ret <8 x double> %res
+}
+declare <8 x double> @llvm.nearbyint.v8f64(<8 x double> %p)
+
+define double @nearbyint_f64(double %a) {
+; CHECK-LABEL: nearbyint_f64
+; CHECK: vrndscalesd $12, {{.*}}encoding: [0x62,0xf3,0xfd,0x08,0x0b,0xc0,0x0c]
+  %res = call double @llvm.nearbyint.f64(double %a)
+  ret double %res
+}
+declare double @llvm.nearbyint.f64(double %p)
+
+define float @floor_f32(float %a) {
+; CHECK-LABEL: floor_f32
+; CHECK: vrndscaless $1, {{.*}}encoding: [0x62,0xf3,0x7d,0x08,0x0a,0xc0,0x01]
+  %res = call float @llvm.floor.f32(float %a)
+  ret float %res
+}
+declare float @llvm.floor.f32(float %p)
+
+define float @floor_f32m(float* %aptr) {
+; CHECK-LABEL: floor_f32m
+; CHECK: vrndscaless $1, (%rdi), {{.*}}encoding: [0x62,0xf3,0x7d,0x08,0x0a,0x07,0x01]
+  %a = load float, float* %aptr, align 4
+  %res = call float @llvm.floor.f32(float %a)
+  ret float %res
+}
+
diff --git a/test/CodeGen/X86/avx512-scalar.ll b/test/CodeGen/X86/avx512-scalar.ll
new file mode 100644
index 000000000000..644fda415755
--- /dev/null
+++ b/test/CodeGen/X86/avx512-scalar.ll
@@ -0,0 +1,92 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding | FileCheck %s --check-prefix AVX512
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx --show-mc-encoding | FileCheck %s --check-prefix AVX
+
+; AVX512-LABEL: @test_fdiv
+; AVX512: vdivss %xmm{{.*}} ## encoding: [0x62
+; AVX-LABEL: @test_fdiv
+; AVX:    vdivss %xmm{{.*}} ## encoding: [0xc5
+
+define float @test_fdiv(float %a, float %b) {
+  %c = fdiv float %a, %b
+  ret float %c
+}
+
+; AVX512-LABEL: @test_fsub
+; AVX512: vsubss %xmm{{.*}} ## encoding: [0x62
+; AVX-LABEL: @test_fsub
+; AVX:    vsubss %xmm{{.*}} ## encoding: [0xc5
+
+define float @test_fsub(float %a, float %b) {
+  %c = fsub float %a, %b
+  ret float %c
+}
+
+; AVX512-LABEL: @test_fadd
+; AVX512: vaddsd %xmm{{.*}} ## encoding: [0x62
+; AVX-LABEL: @test_fadd
+; AVX:    vaddsd %xmm{{.*}} ## encoding: [0xc5
+
+define double @test_fadd(double %a, double %b) {
+  %c = fadd double %a, %b
+  ret double %c
+}
+
+declare float     @llvm.trunc.f32(float  %Val)
+declare double    @llvm.trunc.f64(double %Val)
+declare float     @llvm.rint.f32(float  %Val)
+declare double    @llvm.rint.f64(double %Val)
+declare double    @llvm.sqrt.f64(double %Val)
+declare float     @llvm.sqrt.f32(float  %Val)
+
+; AVX512-LABEL: @test_trunc
+; AVX512: vrndscaless
+; AVX-LABEL: @test_trunc
+; AVX:    vroundss
+
+define float @test_trunc(float %a) {
+  %c = call float @llvm.trunc.f32(float %a)
+  ret float %c
+}
+
+; AVX512-LABEL: @test_sqrt
+; AVX512: vsqrtsd %xmm{{.*}} ## encoding: [0x62
+; AVX-LABEL: @test_sqrt
+; AVX:    vsqrtsd %xmm{{.*}} ## encoding: [0xc5
+
+define double @test_sqrt(double %a) {
+  %c = call double @llvm.sqrt.f64(double %a)
+  ret double %c
+}
+
+; AVX512-LABEL: @test_rint
+; AVX512: vrndscaless
+; AVX-LABEL: @test_rint
+; AVX:    vroundss
+
+define float @test_rint(float %a) {
+  %c = call float @llvm.rint.f32(float %a)
+  ret float %c
+}
+
+; AVX512-LABEL: @test_vmax
+; AVX512: vmaxss %xmm{{.*}} ## encoding: [0x62
+; AVX-LABEL: @test_vmax
+; AVX:    vmaxss %xmm{{.*}} ## encoding: [0xc5
+
+define float @test_vmax(float %i, float %j) {
+  %cmp_res = fcmp ogt float %i, %j
+  %max = select i1 %cmp_res, float %i, float %j
+  ret float %max
+}
+
+; AVX512-LABEL: @test_mov
+; AVX512: vcmpltss %xmm{{.*}} ## encoding: [0x62
+; AVX-LABEL: @test_mov
+; AVX:    vcmpltss %xmm{{.*}} ## encoding: [0xc5
+
+define float @test_mov(float %a, float %b, float %i, float %j) {
+  %cmp_res = fcmp ogt float %i, %j
+  %max = select i1 %cmp_res, float %b, float %a
+  ret float %max
+}
+
diff --git a/test/CodeGen/X86/avx512-select.ll b/test/CodeGen/X86/avx512-select.ll
index 0dbf286d3c5d..b92e6f62813c 100644
--- a/test/CodeGen/X86/avx512-select.ll
+++ b/test/CodeGen/X86/avx512-select.ll
@@ -50,8 +50,10 @@ define <16 x double> @select04(<16 x double> %a, <16 x double> %b) {
 }
 
 ; CHECK-LABEL: select05
-; CHECK: kmovw   %esi, %k0
-; CHECK-NEXT: kmovw   %edi, %k1
+; CHECK: movzbl  %sil, %eax
+; CHECK: kmovw   %eax, %k0
+; CHECK: movzbl  %dil, %eax
+; CHECK: kmovw   %eax, %k1
 ; CHECK-NEXT: korw    %k1, %k0, %k0
 ; CHECK-NEXT: kmovw   %k0, %eax
 define i8 @select05(i8 %a.0, i8 %m) {
@@ -63,8 +65,10 @@ define i8 @select05(i8 %a.0, i8 %m) {
 }
 
 ; CHECK-LABEL: select06
-; CHECK: kmovw   %esi, %k0
-; CHECK-NEXT: kmovw   %edi, %k1
+; CHECK: movzbl  %sil, %eax
+; CHECK: kmovw   %eax, %k0
+; CHECK: movzbl  %dil, %eax
+; CHECK: kmovw   %eax, %k1
 ; CHECK-NEXT: kandw    %k1, %k0, %k0
 ; CHECK-NEXT: kmovw   %k0, %eax
 define i8 @select06(i8 %a.0, i8 %m) {
@@ -76,9 +80,12 @@ define i8 @select06(i8 %a.0, i8 %m) {
 }
 
 ; CHECK-LABEL: select07
-; CHECK-DAG:  kmovw   %edx, %k0
-; CHECK-DAG:  kmovw   %edi, %k1
-; CHECK-DAG:  kmovw   %esi, %k2
+; CHECK-DAG: movzbl  %dl, %eax
+; CHECK-DAG: kmovw   %eax, %k0
+; CHECK-DAG: movzbl  %dil, %eax
+; CHECK-DAG: kmovw   %eax, %k1
+; CHECK-DAG: movzbl  %sil, %eax
+; CHECK-DAG: kmovw   %eax, %k2
 ; CHECK: kandw %k0, %k1, %k1
 ; CHECK-NEXT: knotw    %k0, %k0
 ; CHECK-NEXT: kandw    %k0, %k2, %k0
diff --git a/test/CodeGen/X86/avx512-shift.ll b/test/CodeGen/X86/avx512-shift.ll
index 8cdcf8ad062f..10883a5a9a62 100644
--- a/test/CodeGen/X86/avx512-shift.ll
+++ b/test/CodeGen/X86/avx512-shift.ll
@@ -1,4 +1,5 @@
 ;RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
+;RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck --check-prefix=SKX %s
 
 ;CHECK-LABEL: shift_16_i32
 ;CHECK: vpsrld
@@ -24,6 +25,18 @@ define <8 x i64> @shift_8_i64(<8 x i64> %a) {
    ret <8 x i64> %d;
 }
 
+;SKX-LABEL: shift_4_i64
+;SKX: vpsrlq
+;SKX: vpsllq
+;SKX: vpsraq
+;SKX: ret
+define <4 x i64> @shift_4_i64(<4 x i64> %a) {
+   %b = lshr <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
+   %c = shl <4 x i64> %b,  <i64 12, i64 12, i64 12, i64 12>
+   %d = ashr <4 x i64> %c, <i64 12, i64 12, i64 12, i64 12>
+   ret <4 x i64> %d;
+}
+
 ; CHECK-LABEL: variable_shl4
 ; CHECK: vpsllvq %zmm
 ; CHECK: ret
@@ -72,11 +85,27 @@ define <8 x i64> @variable_sra2(<8 x i64> %x, <8 x i64> %y) {
   ret <8 x i64> %k
 }
 
+; SKX-LABEL: variable_sra3
+; SKX: vpsravq %ymm
+; SKX: ret
+define <4 x i64> @variable_sra3(<4 x i64> %x, <4 x i64> %y) {
+  %k = ashr <4 x i64> %x, %y
+  ret <4 x i64> %k
+}
+
+; SKX-LABEL: variable_sra4
+; SKX: vpsravw %xmm
+; SKX: ret
+define <8 x i16> @variable_sra4(<8 x i16> %x, <8 x i16> %y) {
+  %k = ashr <8 x i16> %x, %y
+  ret <8 x i16> %k
+}
+
 ; CHECK-LABEL: variable_sra01_load
 ; CHECK: vpsravd (%
 ; CHECK: ret
 define <16 x i32> @variable_sra01_load(<16 x i32> %x, <16 x i32>* %y) {
-  %y1 = load <16 x i32>* %y
+  %y1 = load <16 x i32>, <16 x i32>* %y
   %k = ashr <16 x i32> %x, %y1
   ret <16 x i32> %k
 }
@@ -85,7 +114,7 @@ define <16 x i32> @variable_sra01_load(<16 x i32> %x, <16 x i32>* %y) {
 ; CHECK: vpsllvd (%
 ; CHECK: ret
 define <16 x i32> @variable_shl1_load(<16 x i32> %x, <16 x i32>* %y) {
-  %y1 = load <16 x i32>* %y
+  %y1 = load <16 x i32>, <16 x i32>* %y
   %k = shl <16 x i32> %x, %y1
   ret <16 x i32> %k
 }
@@ -93,7 +122,7 @@ define <16 x i32> @variable_shl1_load(<16 x i32> %x, <16 x i32>* %y) {
 ; CHECK: vpsrlvd (%
 ; CHECK: ret
 define <16 x i32> @variable_srl0_load(<16 x i32> %x, <16 x i32>* %y) {
-  %y1 = load <16 x i32>* %y
+  %y1 = load <16 x i32>, <16 x i32>* %y
   %k = lshr <16 x i32> %x, %y1
   ret <16 x i32> %k
 }
@@ -102,7 +131,7 @@ define <16 x i32> @variable_srl0_load(<16 x i32> %x, <16 x i32>* %y) {
 ; CHECK: vpsrlvq (%
 ; CHECK: ret
 define <8 x i64> @variable_srl3_load(<8 x i64> %x, <8 x i64>* %y) {
-  %y1 = load <8 x i64>* %y
+  %y1 = load <8 x i64>, <8 x i64>* %y
   %k = lshr <8 x i64> %x, %y1
   ret <8 x i64> %k
 }
diff --git a/test/CodeGen/X86/avx512-trunc-ext.ll b/test/CodeGen/X86/avx512-trunc-ext.ll
index 91ef5d58f438..f25458972e42 100644
--- a/test/CodeGen/X86/avx512-trunc-ext.ll
+++ b/test/CodeGen/X86/avx512-trunc-ext.ll
@@ -1,126 +1,893 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck --check-prefix=SKX %s
-
-; CHECK-LABEL: trunc_16x32_to_16x8
-; CHECK: vpmovdb
-; CHECK: ret
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s --check-prefix=KNL
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s --check-prefix=SKX 
+ 
+ 
+; KNL-LABEL: trunc_16x32_to_16x8
+; KNL: vpmovdb
+; KNL: ret
 define <16 x i8> @trunc_16x32_to_16x8(<16 x i32> %i) nounwind readnone {
   %x = trunc <16 x i32> %i to <16 x i8>
   ret <16 x i8> %x
 }
 
-; CHECK-LABEL: trunc_8x64_to_8x16
-; CHECK: vpmovqw
-; CHECK: ret
+; KNL-LABEL: trunc_8x64_to_8x16
+; KNL: vpmovqw
+; KNL: ret
 define <8 x i16> @trunc_8x64_to_8x16(<8 x i64> %i) nounwind readnone {
   %x = trunc <8 x i64> %i to <8 x i16>
   ret <8 x i16> %x
 }
 
+;SKX-LABEL: zext_8x8mem_to_8x16:                  
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovw2m  %xmm0, %k1     
+;SKX-NEXT:  vpmovzxbw (%rdi), %xmm0 {%k1} {z} 
+;SKX-NEXT:  retq                            
+define <8 x i16> @zext_8x8mem_to_8x16(<8 x i8> *%i , <8 x i1> %mask) nounwind readnone {
+  %a   = load <8 x i8>,<8 x i8> *%i,align 1
+  %x   = zext <8 x i8> %a to <8 x i16>  
+  %ret = select <8 x i1> %mask, <8 x i16> %x, <8 x i16> zeroinitializer  
+  ret <8 x i16> %ret
+}
+
+;SKX-LABEL: sext_8x8mem_to_8x16:                  
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovw2m  %xmm0, %k1     
+;SKX-NEXT:  vpmovsxbw (%rdi), %xmm0 {%k1} {z} 
+;SKX-NEXT:  retq                       
+define <8 x i16> @sext_8x8mem_to_8x16(<8 x i8> *%i , <8 x i1> %mask) nounwind readnone {
+  %a   = load <8 x i8>,<8 x i8> *%i,align 1
+  %x   = sext <8 x i8> %a to <8 x i16>  
+  %ret = select <8 x i1> %mask, <8 x i16> %x, <8 x i16> zeroinitializer  
+  ret <8 x i16> %ret
+}
+
+;SKX-LABEL: zext_16x8mem_to_16x16:                
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovb2m  %xmm0, %k1     
+;SKX-NEXT:  vpmovzxbw (%rdi), %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq            
+define <16 x i16> @zext_16x8mem_to_16x16(<16 x i8> *%i , <16 x i1> %mask) nounwind readnone {
+  %a   = load <16 x i8>,<16 x i8> *%i,align 1
+  %x   = zext <16 x i8> %a to <16 x i16>  
+  %ret = select <16 x i1> %mask, <16 x i16> %x, <16 x i16> zeroinitializer  
+  ret <16 x i16> %ret
+}
+
+;SKX-LABEL: sext_16x8mem_to_16x16:                
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovb2m  %xmm0, %k1     
+;SKX-NEXT:  vpmovsxbw (%rdi), %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq  
+define <16 x i16> @sext_16x8mem_to_16x16(<16 x i8> *%i , <16 x i1> %mask) nounwind readnone {
+  %a   = load <16 x i8>,<16 x i8> *%i,align 1
+  %x   = sext <16 x i8> %a to <16 x i16>  
+  %ret = select <16 x i1> %mask, <16 x i16> %x, <16 x i16> zeroinitializer  
+  ret <16 x i16> %ret
+}
+
+;SKX-LABEL: zext_16x8_to_16x16:                   
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovzxbw %xmm0, %ymm0    
+;SKX-NEXT:  retq  
+define <16 x i16> @zext_16x8_to_16x16(<16 x i8> %a ) nounwind readnone {  
+  %x   = zext <16 x i8> %a to <16 x i16>  
+  ret <16 x i16> %x
+}
+
+;SKX-LABEL: zext_16x8_to_16x16_mask:              
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovb2m  %xmm1, %k1     
+;SKX-NEXT:  vpmovzxbw %xmm0, %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq 
+define <16 x i16> @zext_16x8_to_16x16_mask(<16 x i8> %a ,<16 x i1> %mask) nounwind readnone {  
+  %x   = zext <16 x i8> %a to <16 x i16> 
+  %ret = select <16 x i1> %mask, <16 x i16> %x, <16 x i16> zeroinitializer   
+  ret <16 x i16> %ret
+}
+
+;SKX-LABEL: sext_16x8_to_16x16:                   
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovsxbw %xmm0, %ymm0    
+;SKX-NEXT:  retq
+define <16 x i16> @sext_16x8_to_16x16(<16 x i8> %a ) nounwind readnone {  
+  %x   = sext <16 x i8> %a to <16 x i16>  
+  ret <16 x i16> %x
+}
+
+;SKX-LABEL: sext_16x8_to_16x16_mask:              
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovb2m  %xmm1, %k1     
+;SKX-NEXT:  vpmovsxbw %xmm0, %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq 
+define <16 x i16> @sext_16x8_to_16x16_mask(<16 x i8> %a ,<16 x i1> %mask) nounwind readnone {  
+  %x   = sext <16 x i8> %a to <16 x i16> 
+  %ret = select <16 x i1> %mask, <16 x i16> %x, <16 x i16> zeroinitializer   
+  ret <16 x i16> %ret
+}
+
+;SKX-LABEL: zext_32x8mem_to_32x16:                
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovb2m  %ymm0, %k1     
+;SKX-NEXT:  vpmovzxbw (%rdi), %zmm0 {%k1} {z} 
+;SKX-NEXT:  retq                       
+define <32 x i16> @zext_32x8mem_to_32x16(<32 x i8> *%i , <32 x i1> %mask) nounwind readnone {
+  %a   = load <32 x i8>,<32 x i8> *%i,align 1
+  %x   = zext <32 x i8> %a to <32 x i16>  
+  %ret = select <32 x i1> %mask, <32 x i16> %x, <32 x i16> zeroinitializer  
+  ret <32 x i16> %ret
+}
+
+;SKX-LABEL: sext_32x8mem_to_32x16:                
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovb2m  %ymm0, %k1     
+;SKX-NEXT:  vpmovsxbw (%rdi), %zmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <32 x i16> @sext_32x8mem_to_32x16(<32 x i8> *%i , <32 x i1> %mask) nounwind readnone {
+  %a   = load <32 x i8>,<32 x i8> *%i,align 1
+  %x   = sext <32 x i8> %a to <32 x i16>  
+  %ret = select <32 x i1> %mask, <32 x i16> %x, <32 x i16> zeroinitializer  
+  ret <32 x i16> %ret
+}
+
+;SKX-LABEL: zext_32x8_to_32x16:                   
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovzxbw %ymm0, %zmm0    
+;SKX-NEXT:  retq 
+define <32 x i16> @zext_32x8_to_32x16(<32 x i8> %a ) nounwind readnone {  
+  %x   = zext <32 x i8> %a to <32 x i16>  
+  ret <32 x i16> %x
+}
+
+;SKX-LABEL: zext_32x8_to_32x16_mask:              
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovb2m  %ymm1, %k1    
+;SKX-NEXT:  vpmovzxbw %ymm0, %zmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <32 x i16> @zext_32x8_to_32x16_mask(<32 x i8> %a ,<32 x i1> %mask) nounwind readnone {  
+  %x   = zext <32 x i8> %a to <32 x i16>
+  %ret = select <32 x i1> %mask, <32 x i16> %x, <32 x i16> zeroinitializer  
+  ret <32 x i16> %ret
+}
+
+;SKX-LABEL: sext_32x8_to_32x16:                   
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovsxbw %ymm0, %zmm0    
+;SKX-NEXT:  retq
+define <32 x i16> @sext_32x8_to_32x16(<32 x i8> %a ) nounwind readnone {  
+  %x   = sext <32 x i8> %a to <32 x i16>  
+  ret <32 x i16> %x
+}
+
+;SKX-LABEL: sext_32x8_to_32x16_mask:              
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovb2m  %ymm1, %k1     
+;SKX-NEXT:  vpmovsxbw %ymm0, %zmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <32 x i16> @sext_32x8_to_32x16_mask(<32 x i8> %a ,<32 x i1> %mask) nounwind readnone {  
+  %x   = sext <32 x i8> %a to <32 x i16>
+  %ret = select <32 x i1> %mask, <32 x i16> %x, <32 x i16> zeroinitializer  
+  ret <32 x i16> %ret
+}
+
+;SKX-LABEL: zext_4x8mem_to_4x32:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovd2m    %xmm0, %k1      
+;SKX-NEXT:  vpmovzxbd    (%rdi), %xmm0 {%k1} {z} 
+;SKX-NEXT:  retq                            
+define <4 x i32> @zext_4x8mem_to_4x32(<4 x i8> *%i , <4 x i1> %mask) nounwind readnone {
+  %a   = load <4 x i8>,<4 x i8> *%i,align 1
+  %x   = zext <4 x i8> %a to <4 x i32>  
+  %ret = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> zeroinitializer  
+  ret <4 x i32> %ret
+}
+
+;SKX-LABEL: sext_4x8mem_to_4x32:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovd2m    %xmm0, %k1      
+;SKX-NEXT:  vpmovsxbd    (%rdi), %xmm0 {%k1} {z} 
+;SKX-NEXT:  retq       
+define <4 x i32> @sext_4x8mem_to_4x32(<4 x i8> *%i , <4 x i1> %mask) nounwind readnone {
+  %a   = load <4 x i8>,<4 x i8> *%i,align 1
+  %x   = sext <4 x i8> %a to <4 x i32>  
+  %ret = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> zeroinitializer  
+  ret <4 x i32> %ret
+}
+
+;SKX-LABEL: zext_8x8mem_to_8x32:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovw2m    %xmm0, %k1      
+;SKX-NEXT:  vpmovzxbd    (%rdi), %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq    
+define <8 x i32> @zext_8x8mem_to_8x32(<8 x i8> *%i , <8 x i1> %mask) nounwind readnone {
+  %a   = load <8 x i8>,<8 x i8> *%i,align 1
+  %x   = zext <8 x i8> %a to <8 x i32>  
+  %ret = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer  
+  ret <8 x i32> %ret
+}
+
+;SKX-LABEL: sext_8x8mem_to_8x32:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovw2m    %xmm0, %k1      
+;SKX-NEXT:  vpmovsxbd    (%rdi), %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq         
+define <8 x i32> @sext_8x8mem_to_8x32(<8 x i8> *%i , <8 x i1> %mask) nounwind readnone {
+  %a   = load <8 x i8>,<8 x i8> *%i,align 1
+  %x   = sext <8 x i8> %a to <8 x i32>  
+  %ret = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer  
+  ret <8 x i32> %ret
+}
+
+;KNL-LABEL: zext_16x8mem_to_16x32:   
+;KNL:       vpmovzxbd    (%rdi), %zmm0 {%k1} {z} 
+;KNL-NEXT:  retq 
+define <16 x i32> @zext_16x8mem_to_16x32(<16 x i8> *%i , <16 x i1> %mask) nounwind readnone {
+  %a   = load <16 x i8>,<16 x i8> *%i,align 1
+  %x   = zext <16 x i8> %a to <16 x i32>
+  %ret = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> zeroinitializer
+  ret <16 x i32> %ret
+}
+
+;KNL-LABEL: sext_16x8mem_to_16x32:   
+;KNL:       vpmovsxbd    (%rdi), %zmm0 {%k1} {z} 
+;KNL-NEXT:  retq  
+define <16 x i32> @sext_16x8mem_to_16x32(<16 x i8> *%i , <16 x i1> %mask) nounwind readnone {
+  %a   = load <16 x i8>,<16 x i8> *%i,align 1
+  %x   = sext <16 x i8> %a to <16 x i32>
+  %ret = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> zeroinitializer
+  ret <16 x i32> %ret
+}
+
+;KNL-LABEL: zext_16x8_to_16x32_mask:                    
+;KNL:       vpmovzxbd %xmm0, %zmm0 {%k1} {z} 
+;KNL-NEXT:  retq                
+define <16 x i32> @zext_16x8_to_16x32_mask(<16 x i8> %a , <16 x i1> %mask) nounwind readnone {
+  %x   = zext <16 x i8> %a to <16 x i32>
+  %ret = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> zeroinitializer
+  ret <16 x i32> %ret
+}
+
+;KNL-LABEL: sext_16x8_to_16x32_mask:                    
+;KNL:       vpmovsxbd %xmm0, %zmm0 {%k1} {z} 
+;KNL-NEXT:  retq
+define <16 x i32> @sext_16x8_to_16x32_mask(<16 x i8> %a , <16 x i1> %mask) nounwind readnone {
+  %x   = sext <16 x i8> %a to <16 x i32>
+  %ret = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> zeroinitializer
+  ret <16 x i32> %ret
+}
 
-; CHECK-LABEL: zext_16x8_to_16x32
-; CHECK: vpmovzxbd {{.*}}%zmm
-; CHECK: ret
+; KNL-LABEL: zext_16x8_to_16x32
+; KNL: vpmovzxbd {{.*}}%zmm
+; KNL: ret
 define <16 x i32> @zext_16x8_to_16x32(<16 x i8> %i) nounwind readnone {
   %x = zext <16 x i8> %i to <16 x i32>
   ret <16 x i32> %x
 }
 
-; CHECK-LABEL: sext_16x8_to_16x32
-; CHECK: vpmovsxbd {{.*}}%zmm
-; CHECK: ret
+; KNL-LABEL: sext_16x8_to_16x32
+; KNL: vpmovsxbd {{.*}}%zmm
+; KNL: ret
 define <16 x i32> @sext_16x8_to_16x32(<16 x i8> %i) nounwind readnone {
   %x = sext <16 x i8> %i to <16 x i32>
   ret <16 x i32> %x
 }
 
+;SKX-LABEL: zext_2x8mem_to_2x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovq2m  %xmm0, %k1
+;SKX-NEXT:  vpmovzxbq (%rdi), %xmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <2 x i64> @zext_2x8mem_to_2x64(<2 x i8> *%i , <2 x i1> %mask) nounwind readnone {
+  %a   = load <2 x i8>,<2 x i8> *%i,align 1
+  %x   = zext <2 x i8> %a to <2 x i64>
+  %ret = select <2 x  i1> %mask, <2 x i64> %x, <2 x i64> zeroinitializer
+  ret <2 x i64> %ret
+}
+;SKX-LABEL: sext_2x8mem_to_2x64mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovq2m  %xmm0, %k1
+;SKX-NEXT:  vpmovsxbq (%rdi), %xmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <2 x i64> @sext_2x8mem_to_2x64mask(<2 x i8> *%i , <2 x i1> %mask) nounwind readnone {
+  %a   = load <2 x i8>,<2 x i8> *%i,align 1
+  %x   = sext <2 x i8> %a to <2 x i64>
+  %ret = select <2 x i1> %mask, <2 x i64> %x, <2 x i64> zeroinitializer
+  ret <2 x i64> %ret
+}
+;SKX-LABEL: sext_2x8mem_to_2x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovsxbq (%rdi), %xmm0   
+;SKX-NEXT:  retq
+define <2 x i64> @sext_2x8mem_to_2x64(<2 x i8> *%i) nounwind readnone {
+  %a   = load <2 x i8>,<2 x i8> *%i,align 1
+  %x   = sext <2 x i8> %a to <2 x i64>
+  ret <2 x i64> %x
+}
+
+;SKX-LABEL: zext_4x8mem_to_4x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovd2m  %xmm0, %k1
+;SKX-NEXT:  vpmovzxbq (%rdi), %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <4 x i64> @zext_4x8mem_to_4x64(<4 x i8> *%i , <4 x i1> %mask) nounwind readnone {
+  %a   = load <4 x i8>,<4 x i8> *%i,align 1
+  %x   = zext <4 x i8> %a to <4 x i64>
+  %ret = select <4 x  i1> %mask, <4 x i64> %x, <4 x i64> zeroinitializer
+  ret <4 x i64> %ret
+}
+
+;SKX-LABEL: sext_4x8mem_to_4x64mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovd2m  %xmm0, %k1
+;SKX-NEXT:  vpmovsxbq (%rdi), %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <4 x i64> @sext_4x8mem_to_4x64mask(<4 x i8> *%i , <4 x i1> %mask) nounwind readnone {
+  %a   = load <4 x i8>,<4 x i8> *%i,align 1
+  %x   = sext <4 x i8> %a to <4 x i64>
+  %ret = select <4 x i1> %mask, <4 x i64> %x, <4 x i64> zeroinitializer
+  ret <4 x i64> %ret
+}
+
+;SKX-LABEL: sext_4x8mem_to_4x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovsxbq (%rdi), %ymm0   
+;SKX-NEXT:  retq
+define <4 x i64> @sext_4x8mem_to_4x64(<4 x i8> *%i) nounwind readnone {
+  %a   = load <4 x i8>,<4 x i8> *%i,align 1
+  %x   = sext <4 x i8> %a to <4 x i64>
+  ret <4 x i64> %x
+}
+
+;KNL-LABEL: zext_8x8mem_to_8x64:
+;KNL:       vpmovzxbq (%rdi), %zmm0 {%k1} {z} 
+;KNL-NEXT:  retq
+define <8 x i64> @zext_8x8mem_to_8x64(<8 x i8> *%i , <8 x i1> %mask) nounwind readnone {
+  %a   = load <8 x i8>,<8 x i8> *%i,align 1
+  %x   = zext <8 x i8> %a to <8 x i64>
+  %ret = select <8 x  i1> %mask, <8 x i64> %x, <8 x i64> zeroinitializer
+  ret <8 x i64> %ret
+}
+
+;KNL-LABEL: sext_8x8mem_to_8x64mask:
+;KNL:       vpmovsxbq (%rdi), %zmm0 {%k1} {z} 
+;KNL-NEXT:  retq
+define <8 x i64> @sext_8x8mem_to_8x64mask(<8 x i8> *%i , <8 x i1> %mask) nounwind readnone {
+  %a   = load <8 x i8>,<8 x i8> *%i,align 1
+  %x   = sext <8 x i8> %a to <8 x i64>
+  %ret = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> zeroinitializer
+  ret <8 x i64> %ret
+}
+
+;KNL-LABEL: sext_8x8mem_to_8x64:
+;KNL:       vpmovsxbq (%rdi), %zmm0   
+;KNL-NEXT:  retq
+define <8 x i64> @sext_8x8mem_to_8x64(<8 x i8> *%i) nounwind readnone {
+  %a   = load <8 x i8>,<8 x i8> *%i,align 1
+  %x   = sext <8 x i8> %a to <8 x i64>
+  ret <8 x i64> %x
+}
+
+;SKX-LABEL: zext_4x16mem_to_4x32:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovd2m  %xmm0, %k1
+;SKX-NEXT:  vpmovzxwd (%rdi), %xmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <4 x i32> @zext_4x16mem_to_4x32(<4 x i16> *%i , <4 x i1> %mask) nounwind readnone {
+  %a   = load <4 x i16>,<4 x i16> *%i,align 1
+  %x   = zext <4 x i16> %a to <4 x i32>
+  %ret = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> zeroinitializer
+  ret <4 x i32> %ret
+}
+
+;SKX-LABEL: sext_4x16mem_to_4x32mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovd2m  %xmm0, %k1
+;SKX-NEXT:  vpmovsxwd (%rdi), %xmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <4 x i32> @sext_4x16mem_to_4x32mask(<4 x i16> *%i , <4 x i1> %mask) nounwind readnone {
+  %a   = load <4 x i16>,<4 x i16> *%i,align 1
+  %x   = sext <4 x i16> %a to <4 x i32>
+  %ret = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> zeroinitializer
+  ret <4 x i32> %ret
+}
+
+;SKX-LABEL: sext_4x16mem_to_4x32:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovsxwd (%rdi), %xmm0   
+;SKX-NEXT:  retq
+define <4 x i32> @sext_4x16mem_to_4x32(<4 x i16> *%i) nounwind readnone {
+  %a   = load <4 x i16>,<4 x i16> *%i,align 1
+  %x   = sext <4 x i16> %a to <4 x i32>
+  ret <4 x i32> %x
+}
+
+
+;SKX-LABEL: zext_8x16mem_to_8x32:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovw2m  %xmm0, %k1
+;SKX-NEXT:  vpmovzxwd (%rdi), %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <8 x i32> @zext_8x16mem_to_8x32(<8 x i16> *%i , <8 x i1> %mask) nounwind readnone {
+  %a   = load <8 x i16>,<8 x i16> *%i,align 1
+  %x   = zext <8 x i16> %a to <8 x i32>
+  %ret = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer
+  ret <8 x i32> %ret
+}
+
+;SKX-LABEL: sext_8x16mem_to_8x32mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovw2m  %xmm0, %k1
+;SKX-NEXT:  vpmovsxwd (%rdi), %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <8 x i32> @sext_8x16mem_to_8x32mask(<8 x i16> *%i , <8 x i1> %mask) nounwind readnone {
+  %a   = load <8 x i16>,<8 x i16> *%i,align 1
+  %x   = sext <8 x i16> %a to <8 x i32>
+  %ret = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer
+  ret <8 x i32> %ret
+}
+
+;SKX-LABEL: sext_8x16mem_to_8x32:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovsxwd (%rdi), %ymm0   
+;SKX-NEXT:  retq
+define <8 x i32> @sext_8x16mem_to_8x32(<8 x i16> *%i) nounwind readnone {
+  %a   = load <8 x i16>,<8 x i16> *%i,align 1
+  %x   = sext <8 x i16> %a to <8 x i32>
+  ret <8 x i32> %x
+}
+
+;SKX-LABEL: zext_8x16_to_8x32mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovw2m  %xmm1, %k1
+;SKX-NEXT:  vpmovzxwd %xmm0, %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <8 x i32> @zext_8x16_to_8x32mask(<8 x i16> %a , <8 x i1> %mask) nounwind readnone {
+  %x   = zext <8 x i16> %a to <8 x i32>
+  %ret = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer
+  ret <8 x i32> %ret
+}
+
+;SKX-LABEL: zext_8x16_to_8x32:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovzxwd %xmm0, %ymm0    
+;SKX-NEXT:  retq
+define <8 x i32> @zext_8x16_to_8x32(<8 x i16> %a ) nounwind readnone {
+  %x   = zext <8 x i16> %a to <8 x i32>
+  ret <8 x i32> %x
+}
+
+;SKX-LABEL: zext_16x16mem_to_16x32:
+;KNL-LABEL: zext_16x16mem_to_16x32:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovb2m  %xmm0, %k1
+;SKX-NEXT:  vpmovzxwd (%rdi), %zmm0 {%k1} {z} 
+;KNL:       vpmovzxwd (%rdi), %zmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <16 x i32> @zext_16x16mem_to_16x32(<16 x i16> *%i , <16 x i1> %mask) nounwind readnone {
+  %a   = load <16 x i16>,<16 x i16> *%i,align 1
+  %x   = zext <16 x i16> %a to <16 x i32>
+  %ret = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> zeroinitializer
+  ret <16 x i32> %ret
+}
 
-; CHECK-LABEL: zext_16x16_to_16x32
-; CHECK: vpmovzxwd {{.*}}%zmm
-; CHECK: ret
-define <16 x i32> @zext_16x16_to_16x32(<16 x i16> %i) nounwind readnone {
-  %x = zext <16 x i16> %i to <16 x i32>
+;SKX-LABEL: sext_16x16mem_to_16x32mask:
+;KNL-LABEL: sext_16x16mem_to_16x32mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovb2m  %xmm0, %k1
+;SKX-NEXT:  vpmovsxwd (%rdi), %zmm0 {%k1} {z} 
+;KNL:       vpmovsxwd (%rdi), %zmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <16 x i32> @sext_16x16mem_to_16x32mask(<16 x i16> *%i , <16 x i1> %mask) nounwind readnone {
+  %a   = load <16 x i16>,<16 x i16> *%i,align 1
+  %x   = sext <16 x i16> %a to <16 x i32>
+  %ret = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> zeroinitializer
+  ret <16 x i32> %ret
+}
+
+;SKX-LABEL: sext_16x16mem_to_16x32:
+;KNL-LABEL: sext_16x16mem_to_16x32:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovsxwd (%rdi), %zmm0   
+;KNL:       vpmovsxwd (%rdi), %zmm0   
+;SKX-NEXT:  retq
+define <16 x i32> @sext_16x16mem_to_16x32(<16 x i16> *%i) nounwind readnone {
+  %a   = load <16 x i16>,<16 x i16> *%i,align 1
+  %x   = sext <16 x i16> %a to <16 x i32>
   ret <16 x i32> %x
 }
+;SKX-LABEL: zext_16x16_to_16x32mask:
+;KNL-LABEL: zext_16x16_to_16x32mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovb2m  %xmm1, %k1
+;SKX-NEXT:  vpmovzxwd %ymm0, %zmm0 {%k1} {z} 
+;KNL:       vpmovzxwd %ymm0, %zmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <16 x i32> @zext_16x16_to_16x32mask(<16 x i16> %a , <16 x i1> %mask) nounwind readnone {
+  %x   = zext <16 x i16> %a to <16 x i32>
+  %ret = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> zeroinitializer
+  ret <16 x i32> %ret
+}
+
+;SKX-LABEL: zext_16x16_to_16x32:
+;KNL-LABEL: zext_16x16_to_16x32:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovzxwd %ymm0, %zmm0    
+;KNL:       vpmovzxwd %ymm0, %zmm0    
+;SKX-NEXT:  retq
+define <16 x i32> @zext_16x16_to_16x32(<16 x i16> %a ) nounwind readnone {
+  %x   = zext <16 x i16> %a to <16 x i32>
+  ret <16 x i32> %x
+}
+
+;SKX-LABEL: zext_2x16mem_to_2x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovq2m  %xmm0, %k1
+;SKX-NEXT:  vpmovzxwq (%rdi), %xmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <2 x i64> @zext_2x16mem_to_2x64(<2 x i16> *%i , <2 x i1> %mask) nounwind readnone {
+  %a   = load <2 x i16>,<2 x i16> *%i,align 1
+  %x   = zext <2 x i16> %a to <2 x i64>
+  %ret = select <2 x  i1> %mask, <2 x i64> %x, <2 x i64> zeroinitializer
+  ret <2 x i64> %ret
+}
+
+;SKX-LABEL: sext_2x16mem_to_2x64mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovq2m  %xmm0, %k1
+;SKX-NEXT:  vpmovsxwq (%rdi), %xmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <2 x i64> @sext_2x16mem_to_2x64mask(<2 x i16> *%i , <2 x i1> %mask) nounwind readnone {
+  %a   = load <2 x i16>,<2 x i16> *%i,align 1
+  %x   = sext <2 x i16> %a to <2 x i64>
+  %ret = select <2 x i1> %mask, <2 x i64> %x, <2 x i64> zeroinitializer
+  ret <2 x i64> %ret
+}
+
+;SKX-LABEL: sext_2x16mem_to_2x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovsxwq (%rdi), %xmm0   
+;SKX-NEXT:  retq
+define <2 x i64> @sext_2x16mem_to_2x64(<2 x i16> *%i) nounwind readnone {
+  %a   = load <2 x i16>,<2 x i16> *%i,align 1
+  %x   = sext <2 x i16> %a to <2 x i64>
+  ret <2 x i64> %x
+}
+
+;SKX-LABEL: zext_4x16mem_to_4x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovd2m  %xmm0, %k1
+;SKX-NEXT:  vpmovzxwq (%rdi), %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <4 x i64> @zext_4x16mem_to_4x64(<4 x i16> *%i , <4 x i1> %mask) nounwind readnone {
+  %a   = load <4 x i16>,<4 x i16> *%i,align 1
+  %x   = zext <4 x i16> %a to <4 x i64>
+  %ret = select <4 x  i1> %mask, <4 x i64> %x, <4 x i64> zeroinitializer
+  ret <4 x i64> %ret
+}
+
+;SKX-LABEL: sext_4x16mem_to_4x64mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovd2m  %xmm0, %k1
+;SKX-NEXT:  vpmovsxwq (%rdi), %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <4 x i64> @sext_4x16mem_to_4x64mask(<4 x i16> *%i , <4 x i1> %mask) nounwind readnone {
+  %a   = load <4 x i16>,<4 x i16> *%i,align 1
+  %x   = sext <4 x i16> %a to <4 x i64>
+  %ret = select <4 x i1> %mask, <4 x i64> %x, <4 x i64> zeroinitializer
+  ret <4 x i64> %ret
+}
+
+;SKX-LABEL: sext_4x16mem_to_4x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovsxwq (%rdi), %ymm0   
+;SKX-NEXT:  retq
+define <4 x i64> @sext_4x16mem_to_4x64(<4 x i16> *%i) nounwind readnone {
+  %a   = load <4 x i16>,<4 x i16> *%i,align 1
+  %x   = sext <4 x i16> %a to <4 x i64>
+  ret <4 x i64> %x
+}
+
+;SKX-LABEL: zext_8x16mem_to_8x64:
+;KNL-LABEL: zext_8x16mem_to_8x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovw2m  %xmm0, %k1
+;SKX-NEXT:  vpmovzxwq (%rdi), %zmm0 {%k1} {z} 
+;KNL:       vpmovzxwq (%rdi), %zmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <8 x i64> @zext_8x16mem_to_8x64(<8 x i16> *%i , <8 x i1> %mask) nounwind readnone {
+  %a   = load <8 x i16>,<8 x i16> *%i,align 1
+  %x   = zext <8 x i16> %a to <8 x i64>
+  %ret = select <8 x  i1> %mask, <8 x i64> %x, <8 x i64> zeroinitializer
+  ret <8 x i64> %ret
+}
+
+;SKX-LABEL: sext_8x16mem_to_8x64mask:
+;KNL-LABEL: sext_8x16mem_to_8x64mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovw2m  %xmm0, %k1
+;SKX-NEXT:  vpmovsxwq (%rdi), %zmm0 {%k1} {z} 
+;KNL:       vpmovsxwq (%rdi), %zmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <8 x i64> @sext_8x16mem_to_8x64mask(<8 x i16> *%i , <8 x i1> %mask) nounwind readnone {
+  %a   = load <8 x i16>,<8 x i16> *%i,align 1
+  %x   = sext <8 x i16> %a to <8 x i64>
+  %ret = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> zeroinitializer
+  ret <8 x i64> %ret
+}
+
+;SKX-LABEL: sext_8x16mem_to_8x64:
+;KNL-LABEL: sext_8x16mem_to_8x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovsxwq (%rdi), %zmm0   
+;KNL:       vpmovsxwq (%rdi), %zmm0   
+;SKX-NEXT:  retq
+define <8 x i64> @sext_8x16mem_to_8x64(<8 x i16> *%i) nounwind readnone {
+  %a   = load <8 x i16>,<8 x i16> *%i,align 1
+  %x   = sext <8 x i16> %a to <8 x i64>
+  ret <8 x i64> %x
+}
+
+;SKX-LABEL: zext_8x16_to_8x64mask:
+;KNL-LABEL: zext_8x16_to_8x64mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovw2m  %xmm1, %k1
+;SKX-NEXT:  vpmovzxwq %xmm0, %zmm0 {%k1} {z} 
+;KNL:       vpmovzxwq %xmm0, %zmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <8 x i64> @zext_8x16_to_8x64mask(<8 x i16> %a , <8 x i1> %mask) nounwind readnone {
+  %x   = zext <8 x i16> %a to <8 x i64>
+  %ret = select <8 x  i1> %mask, <8 x i64> %x, <8 x i64> zeroinitializer
+  ret <8 x i64> %ret
+}
+
+;SKX-LABEL: zext_8x16_to_8x64:
+;KNL-LABEL: zext_8x16_to_8x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovzxwq %xmm0, %zmm0    
+;KNL:       vpmovzxwq %xmm0, %zmm0    
+;SKX-NEXT:  retq
+; KNL: ret
+define <8 x i64> @zext_8x16_to_8x64(<8 x i16> %a) nounwind readnone {
+  %ret   = zext <8 x i16> %a to <8 x i64>
+  ret <8 x i64> %ret
+}
+
+;SKX-LABEL: zext_2x32mem_to_2x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovq2m  %xmm0, %k1
+;SKX-NEXT:  vpmovzxdq (%rdi), %xmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <2 x i64> @zext_2x32mem_to_2x64(<2 x i32> *%i , <2 x i1> %mask) nounwind readnone {
+  %a   = load <2 x i32>,<2 x i32> *%i,align 1
+  %x   = zext <2 x i32> %a to <2 x i64>
+  %ret = select <2 x  i1> %mask, <2 x i64> %x, <2 x i64> zeroinitializer
+  ret <2 x i64> %ret
+}
+
+;SKX-LABEL: sext_2x32mem_to_2x64mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovq2m  %xmm0, %k1
+;SKX-NEXT:  vpmovsxdq (%rdi), %xmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <2 x i64> @sext_2x32mem_to_2x64mask(<2 x i32> *%i , <2 x i1> %mask) nounwind readnone {
+  %a   = load <2 x i32>,<2 x i32> *%i,align 1
+  %x   = sext <2 x i32> %a to <2 x i64>
+  %ret = select <2 x i1> %mask, <2 x i64> %x, <2 x i64> zeroinitializer
+  ret <2 x i64> %ret
+}
+
+;SKX-LABEL: sext_2x32mem_to_2x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovsxdq (%rdi), %xmm0   
+;SKX-NEXT:  retq
+define <2 x i64> @sext_2x32mem_to_2x64(<2 x i32> *%i) nounwind readnone {
+  %a   = load <2 x i32>,<2 x i32> *%i,align 1
+  %x   = sext <2 x i32> %a to <2 x i64>
+  ret <2 x i64> %x
+}
 
-; CHECK-LABEL: zext_8x16_to_8x64
-; CHECK: vpmovzxwq
-; CHECK: ret
-define <8 x i64> @zext_8x16_to_8x64(<8 x i16> %i) nounwind readnone {
-  %x = zext <8 x i16> %i to <8 x i64>
+;SKX-LABEL: zext_4x32mem_to_4x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovd2m  %xmm0, %k1
+;SKX-NEXT:  vpmovzxdq (%rdi), %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <4 x i64> @zext_4x32mem_to_4x64(<4 x i32> *%i , <4 x i1> %mask) nounwind readnone {
+  %a   = load <4 x i32>,<4 x i32> *%i,align 1
+  %x   = zext <4 x i32> %a to <4 x i64>
+  %ret = select <4 x  i1> %mask, <4 x i64> %x, <4 x i64> zeroinitializer
+  ret <4 x i64> %ret
+}
+
+;SKX-LABEL: sext_4x32mem_to_4x64mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovd2m  %xmm0, %k1
+;SKX-NEXT:  vpmovsxdq (%rdi), %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <4 x i64> @sext_4x32mem_to_4x64mask(<4 x i32> *%i , <4 x i1> %mask) nounwind readnone {
+  %a   = load <4 x i32>,<4 x i32> *%i,align 1
+  %x   = sext <4 x i32> %a to <4 x i64>
+  %ret = select <4 x i1> %mask, <4 x i64> %x, <4 x i64> zeroinitializer
+  ret <4 x i64> %ret
+}
+
+;SKX-LABEL: sext_4x32mem_to_4x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovsxdq (%rdi), %ymm0   
+;SKX-NEXT:  retq
+define <4 x i64> @sext_4x32mem_to_4x64(<4 x i32> *%i) nounwind readnone {
+  %a   = load <4 x i32>,<4 x i32> *%i,align 1
+  %x   = sext <4 x i32> %a to <4 x i64>
+  ret <4 x i64> %x
+}
+
+;SKX-LABEL: sext_4x32_to_4x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovsxdq %xmm0, %ymm0    
+;SKX-NEXT:  retq
+define <4 x i64> @sext_4x32_to_4x64(<4 x i32> %a) nounwind readnone {
+  %x   = sext <4 x i32> %a to <4 x i64>
+  ret <4 x i64> %x
+}
+
+;SKX-LABEL: zext_4x32_to_4x64mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovd2m  %xmm1, %k1
+;SKX-NEXT:  vpmovzxdq %xmm0, %ymm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <4 x i64> @zext_4x32_to_4x64mask(<4 x i32> %a , <4 x i1> %mask) nounwind readnone {
+  %x   = zext <4 x i32> %a to <4 x i64>
+  %ret = select <4 x  i1> %mask, <4 x i64> %x, <4 x i64> zeroinitializer
+  ret <4 x i64> %ret
+}
+
+;SKX-LABEL: zext_8x32mem_to_8x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovw2m  %xmm0, %k1
+;SKX-NEXT:  vpmovzxdq (%rdi), %zmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <8 x i64> @zext_8x32mem_to_8x64(<8 x i32> *%i , <8 x i1> %mask) nounwind readnone {
+  %a   = load <8 x i32>,<8 x i32> *%i,align 1
+  %x   = zext <8 x i32> %a to <8 x i64>
+  %ret = select <8 x  i1> %mask, <8 x i64> %x, <8 x i64> zeroinitializer
+  ret <8 x i64> %ret
+}
+
+;SKX-LABEL: sext_8x32mem_to_8x64mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovw2m  %xmm0, %k1
+;SKX-NEXT:  vpmovsxdq (%rdi), %zmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <8 x i64> @sext_8x32mem_to_8x64mask(<8 x i32> *%i , <8 x i1> %mask) nounwind readnone {
+  %a   = load <8 x i32>,<8 x i32> *%i,align 1
+  %x   = sext <8 x i32> %a to <8 x i64>
+  %ret = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> zeroinitializer
+  ret <8 x i64> %ret
+}
+
+;SKX-LABEL: sext_8x32mem_to_8x64:
+;KNL-LABEL: sext_8x32mem_to_8x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovsxdq (%rdi), %zmm0   
+;KNL:       vpmovsxdq (%rdi), %zmm0   
+;SKX-NEXT:  retq
+define <8 x i64> @sext_8x32mem_to_8x64(<8 x i32> *%i) nounwind readnone {
+  %a   = load <8 x i32>,<8 x i32> *%i,align 1
+  %x   = sext <8 x i32> %a to <8 x i64>
   ret <8 x i64> %x
 }
 
-;CHECK-LABEL: fptrunc_test
-;CHECK: vcvtpd2ps {{.*}}%zmm
-;CHECK: ret
+;SKX-LABEL: sext_8x32_to_8x64:
+;KNL-LABEL: sext_8x32_to_8x64:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovsxdq %ymm0, %zmm0    
+;KNL:       vpmovsxdq %ymm0, %zmm0    
+;SKX-NEXT:  retq
+define <8 x i64> @sext_8x32_to_8x64(<8 x i32> %a) nounwind readnone {
+  %x   = sext <8 x i32> %a to <8 x i64>
+  ret <8 x i64> %x
+}
+
+;SKX-LABEL: zext_8x32_to_8x64mask:
+;KNL-LABEL: zext_8x32_to_8x64mask:
+;SKX:       ## BB#0:
+;SKX-NEXT:  vpmovw2m  %xmm1, %k1
+;SKX-NEXT:  vpmovzxdq %ymm0, %zmm0 {%k1} {z} 
+;KNL:       vpmovzxdq %ymm0, %zmm0 {%k1} {z} 
+;SKX-NEXT:  retq
+define <8 x i64> @zext_8x32_to_8x64mask(<8 x i32> %a , <8 x i1> %mask) nounwind readnone {
+  %x   = zext <8 x i32> %a to <8 x i64>
+  %ret = select <8 x  i1> %mask, <8 x i64> %x, <8 x i64> zeroinitializer
+  ret <8 x i64> %ret
+}
+;KNL-LABEL: fptrunc_test
+;KNL: vcvtpd2ps {{.*}}%zmm
+;KNL: ret
 define <8 x float> @fptrunc_test(<8 x double> %a) nounwind readnone {
   %b = fptrunc <8 x double> %a to <8 x float>
   ret <8 x float> %b
 }
 
-;CHECK-LABEL: fpext_test
-;CHECK: vcvtps2pd {{.*}}%zmm
-;CHECK: ret
+;KNL-LABEL: fpext_test
+;KNL: vcvtps2pd {{.*}}%zmm
+;KNL: ret
 define <8 x double> @fpext_test(<8 x float> %a) nounwind readnone {
   %b = fpext <8 x float> %a to <8 x double>
   ret <8 x double> %b
 }
 
-; CHECK-LABEL: zext_16i1_to_16xi32
-; CHECK: vpbroadcastd LCP{{.*}}(%rip), %zmm0 {%k1} {z}
-; CHECK: ret
+; KNL-LABEL: zext_16i1_to_16xi32
+; KNL: vpbroadcastd LCP{{.*}}(%rip), %zmm0 {%k1} {z}
+; KNL: ret
 define   <16 x i32> @zext_16i1_to_16xi32(i16 %b) {
   %a = bitcast i16 %b to <16 x i1>
   %c = zext <16 x i1> %a to <16 x i32>
   ret <16 x i32> %c
 }
 
-; CHECK-LABEL: zext_8i1_to_8xi64
-; CHECK: vpbroadcastq LCP{{.*}}(%rip), %zmm0 {%k1} {z}
-; CHECK: ret
+; KNL-LABEL: zext_8i1_to_8xi64
+; KNL: vpbroadcastq LCP{{.*}}(%rip), %zmm0 {%k1} {z}
+; KNL: ret
 define   <8 x i64> @zext_8i1_to_8xi64(i8 %b) {
   %a = bitcast i8 %b to <8 x i1>
   %c = zext <8 x i1> %a to <8 x i64>
   ret <8 x i64> %c
 }
 
-; CHECK-LABEL: trunc_16i8_to_16i1
-; CHECK: vpmovsxbd
-; CHECK: vpandd
-; CHECK: vptestmd
-; CHECK: ret
+; KNL-LABEL: trunc_16i8_to_16i1
+; KNL: vpmovsxbd
+; KNL: vpandd
+; KNL: vptestmd
+; KNL: ret
+; SKX-LABEL: trunc_16i8_to_16i1
+; SKX: vpmovb2m %xmm
 define i16 @trunc_16i8_to_16i1(<16 x i8> %a) {
   %mask_b = trunc <16 x i8>%a to <16 x i1>
   %mask = bitcast <16 x i1> %mask_b to i16
   ret i16 %mask
 }
 
-; CHECK-LABEL: trunc_16i32_to_16i1
-; CHECK: vpandd
-; CHECK: vptestmd
-; CHECK: ret
+; KNL-LABEL: trunc_16i32_to_16i1
+; KNL: vpandd
+; KNL: vptestmd
+; KNL: ret
+; SKX-LABEL: trunc_16i32_to_16i1
+; SKX: vpmovd2m %zmm
 define i16 @trunc_16i32_to_16i1(<16 x i32> %a) {
   %mask_b = trunc <16 x i32>%a to <16 x i1>
   %mask = bitcast <16 x i1> %mask_b to i16
   ret i16 %mask
 }
 
-; CHECK-LABEL: trunc_8i16_to_8i1
-; CHECK: vpmovsxwq
-; CHECK: vpandq LCP{{.*}}(%rip){1to8}
-; CHECK: vptestmq
-; CHECK: ret
+; SKX-LABEL: trunc_4i32_to_4i1
+; SKX: vpmovd2m        %xmm
+; SKX: kandw
+; SKX: vpmovm2d
+define <4 x i32> @trunc_4i32_to_4i1(<4 x i32> %a, <4 x i32> %b) {
+  %mask_a = trunc <4 x i32>%a to <4 x i1>
+  %mask_b = trunc <4 x i32>%b to <4 x i1>
+  %a_and_b = and <4 x i1>%mask_a, %mask_b
+  %res = sext <4 x i1>%a_and_b to <4 x i32>
+  ret <4 x i32>%res
+}
+
+; KNL-LABEL: trunc_8i16_to_8i1
+; KNL: vpmovsxwq
+; KNL: vpandq LCP{{.*}}(%rip){1to8}
+; KNL: vptestmq
+; KNL: ret
+
+; SKX-LABEL: trunc_8i16_to_8i1
+; SKX: vpmovw2m %xmm
 define i8 @trunc_8i16_to_8i1(<8 x i16> %a) {
   %mask_b = trunc <8 x i16>%a to <8 x i1>
   %mask = bitcast <8 x i1> %mask_b to i8
   ret i8 %mask
 }
 
-; CHECK-LABEL: sext_8i1_8i32
-; CHECK: vpbroadcastq  LCP{{.*}}(%rip), %zmm0 {%k1} {z}
+; KNL-LABEL: sext_8i1_8i32
+; KNL: vpbroadcastq  LCP{{.*}}(%rip), %zmm0 {%k1} {z}
 ; SKX: vpmovm2d
-; CHECK: ret
+; KNL: ret
 define <8 x i32> @sext_8i1_8i32(<8 x i32> %a1, <8 x i32> %a2) nounwind {
   %x = icmp slt <8 x i32> %a1, %a2
   %x1 = xor <8 x i1>%x, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
@@ -128,19 +895,18 @@ define <8 x i32> @sext_8i1_8i32(<8 x i32> %a1, <8 x i32> %a2) nounwind {
   ret <8 x i32> %y
 }
 
-; CHECK-LABEL: trunc_v16i32_to_v16i16
-; CHECK: vpmovdw
-; CHECK: ret
+; KNL-LABEL: trunc_v16i32_to_v16i16
+; KNL: vpmovdw
+; KNL: ret
 define <16 x i16> @trunc_v16i32_to_v16i16(<16 x i32> %x) {
   %1 = trunc <16 x i32> %x to <16 x i16>
   ret <16 x i16> %1
 }
 
-; CHECK-LABEL: trunc_i32_to_i1
-; CHECK: testb
-; CHECK: setne
-; CKECK: orl
-; CHECK: ret
+; KNL-LABEL: trunc_i32_to_i1
+; KNL: movw    $-4, %ax
+; KNL: kmovw   %eax, %k1
+; KNL: korw
 define i16 @trunc_i32_to_i1(i32 %a) {
   %a_i = trunc i32 %a to i1
   %maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %a_i, i32 0
@@ -148,29 +914,48 @@ define i16 @trunc_i32_to_i1(i32 %a) {
   ret i16 %res
 }
 
-; CHECK-LABEL: sext_8i1_8i16
+; KNL-LABEL: sext_8i1_8i16
 ; SKX: vpmovm2w
-; CHECK: ret
+; KNL: ret
 define <8 x i16> @sext_8i1_8i16(<8 x i32> %a1, <8 x i32> %a2) nounwind {
   %x = icmp slt <8 x i32> %a1, %a2
   %y = sext <8 x i1> %x to <8 x i16>
   ret <8 x i16> %y
 }
 
-; CHECK-LABEL: sext_16i1_16i32
+; KNL-LABEL: sext_16i1_16i32
 ; SKX: vpmovm2d
-; CHECK: ret
+; KNL: ret
 define <16 x i32> @sext_16i1_16i32(<16 x i32> %a1, <16 x i32> %a2) nounwind {
   %x = icmp slt <16 x i32> %a1, %a2
   %y = sext <16 x i1> %x to <16 x i32>
   ret <16 x i32> %y
 }
 
-; CHECK-LABEL: sext_8i1_8i64
+; KNL-LABEL: sext_8i1_8i64
 ; SKX: vpmovm2q
-; CHECK: ret
+; KNL: ret
 define <8 x i64> @sext_8i1_8i64(<8 x i32> %a1, <8 x i32> %a2) nounwind {
   %x = icmp slt <8 x i32> %a1, %a2
   %y = sext <8 x i1> %x to <8 x i64>
   ret <8 x i64> %y
 }
+
+; KNL-LABEL: @extload_v8i64
+; KNL: vpmovsxbq
+define void @extload_v8i64(<8 x i8>* %a, <8 x i64>* %res) {
+  %sign_load = load <8 x i8>, <8 x i8>* %a
+  %c = sext <8 x i8> %sign_load to <8 x i64>
+  store <8 x i64> %c, <8 x i64>* %res
+  ret void
+}
+
+;SKX-LABEL: test21:
+;SKX:       vmovdqu16 %zmm0, %zmm3 {%k1}
+;SKX-NEXT:  kshiftrq  $32, %k1, %k1
+;SKX-NEXT:  vmovdqu16 %zmm1, %zmm2 {%k1}
+define <64 x i16> @test21(<64 x i16> %x , <64 x i1> %mask) nounwind readnone {
+  %ret = select <64 x i1> %mask, <64 x i16> %x, <64 x i16> zeroinitializer
+  ret <64 x i16> %ret
+}  
+
diff --git a/test/CodeGen/X86/avx512-vbroadcast.ll b/test/CodeGen/X86/avx512-vbroadcast.ll
index 5bb82338d087..854f1019f0f8 100644
--- a/test/CodeGen/X86/avx512-vbroadcast.ll
+++ b/test/CodeGen/X86/avx512-vbroadcast.ll
@@ -64,7 +64,7 @@ define   <16 x float> @_ss16xfloat_maskz(float %a, <16 x i32> %mask1) {
 ;CHECK: vbroadcastss (%{{.*}}, %zmm
 ;CHECK: ret
 define   <16 x float> @_ss16xfloat_load(float* %a.ptr) {
-  %a = load float* %a.ptr
+  %a = load float, float* %a.ptr
   %b = insertelement <16 x float> undef, float %a, i32 0
   %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
   ret <16 x float> %c
@@ -74,7 +74,7 @@ define   <16 x float> @_ss16xfloat_load(float* %a.ptr) {
 ;CHECK: vbroadcastss (%rdi), %zmm0 {%k1}
 ;CHECK: ret
 define   <16 x float> @_ss16xfloat_mask_load(float* %a.ptr, <16 x float> %i, <16 x i32> %mask1) {
-  %a = load float* %a.ptr
+  %a = load float, float* %a.ptr
   %mask = icmp ne <16 x i32> %mask1, zeroinitializer
   %b = insertelement <16 x float> undef, float %a, i32 0
   %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
@@ -86,7 +86,7 @@ define   <16 x float> @_ss16xfloat_mask_load(float* %a.ptr, <16 x float> %i, <16
 ;CHECK: vbroadcastss (%rdi), %zmm0 {%k1} {z}
 ;CHECK: ret
 define   <16 x float> @_ss16xfloat_maskz_load(float* %a.ptr, <16 x i32> %mask1) {
-  %a = load float* %a.ptr
+  %a = load float, float* %a.ptr
   %mask = icmp ne <16 x i32> %mask1, zeroinitializer
   %b = insertelement <16 x float> undef, float %a, i32 0
   %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
@@ -130,7 +130,7 @@ define   <8 x double> @_sd8xdouble_maskz(double %a, <8 x i32> %mask1) {
 ;CHECK: vbroadcastsd (%rdi), %zmm
 ;CHECK: ret
 define   <8 x double> @_sd8xdouble_load(double* %a.ptr) {
-  %a = load double* %a.ptr
+  %a = load double, double* %a.ptr
   %b = insertelement <8 x double> undef, double %a, i32 0
   %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
   ret <8 x double> %c
@@ -140,7 +140,7 @@ define   <8 x double> @_sd8xdouble_load(double* %a.ptr) {
 ;CHECK: vbroadcastsd (%rdi), %zmm0 {%k1}
 ;CHECK: ret
 define   <8 x double> @_sd8xdouble_mask_load(double* %a.ptr, <8 x double> %i, <8 x i32> %mask1) {
-  %a = load double* %a.ptr
+  %a = load double, double* %a.ptr
   %mask = icmp ne <8 x i32> %mask1, zeroinitializer
   %b = insertelement <8 x double> undef, double %a, i32 0
   %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
@@ -152,7 +152,7 @@ define   <8 x double> @_sd8xdouble_maskz_load(double* %a.ptr, <8 x i32> %mask1)
 ; CHECK-LABEL: _sd8xdouble_maskz_load:
 ; CHECK:    vbroadcastsd (%rdi), %zmm0 {%k1} {z}
 ; CHECK:    ret
-  %a = load double* %a.ptr
+  %a = load double, double* %a.ptr
   %mask = icmp ne <8 x i32> %mask1, zeroinitializer
   %b = insertelement <8 x double> undef, double %a, i32 0
   %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
@@ -300,3 +300,31 @@ entry:
   %vecinit7.i = insertelement <8 x double> %vecinit6.i, double %0, i32 7
   ret <8 x double> %vecinit7.i
 }
+
+; CHECK-LABEL: test1
+; CHECK: vbroadcastss
+define <16 x float> @test1(<8 x float>%a)  {
+  %res = shufflevector <8 x float> %a, <8 x float> undef, <16 x i32> zeroinitializer
+  ret <16 x float>%res
+}
+
+; CHECK-LABEL: test2
+; CHECK: vbroadcastsd
+define <8 x double> @test2(<4 x double>%a)  {
+  %res = shufflevector <4 x double> %a, <4 x double> undef, <8 x i32> zeroinitializer
+  ret <8 x double>%res
+}
+
+; CHECK-LABEL: test3
+; CHECK: vpbroadcastd
+define <16 x i32> @test3(<8 x i32>%a)  {
+  %res = shufflevector <8 x i32> %a, <8 x i32> undef, <16 x i32> zeroinitializer
+  ret <16 x i32>%res
+}
+
+; CHECK-LABEL: test4
+; CHECK: vpbroadcastq
+define <8 x i64> @test4(<4 x i64>%a)  {
+  %res = shufflevector <4 x i64> %a, <4 x i64> undef, <8 x i32> zeroinitializer
+  ret <8 x i64>%res
+}
diff --git a/test/CodeGen/X86/avx512-vec-cmp.ll b/test/CodeGen/X86/avx512-vec-cmp.ll
index b16f5c9663c6..e1f6276c6ef4 100644
--- a/test/CodeGen/X86/avx512-vec-cmp.ll
+++ b/test/CodeGen/X86/avx512-vec-cmp.ll
@@ -1,135 +1,158 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s --check-prefix=KNL
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s --check-prefix=SKX
 
 define <16 x float> @test1(<16 x float> %x, <16 x float> %y) nounwind {
-; CHECK-LABEL: test1:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vcmpleps %zmm1, %zmm0, %k1
-; CHECK-NEXT:    vmovaps %zmm0, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test1:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vcmpleps %zmm1, %zmm0, %k1
+; KNL-NEXT:    vmovaps %zmm0, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
   %mask = fcmp ole <16 x float> %x, %y
   %max = select <16 x i1> %mask, <16 x float> %x, <16 x float> %y
   ret <16 x float> %max
 }
 
 define <8 x double> @test2(<8 x double> %x, <8 x double> %y) nounwind {
-; CHECK-LABEL: test2:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vcmplepd %zmm1, %zmm0, %k1
-; CHECK-NEXT:    vmovapd %zmm0, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test2:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vcmplepd %zmm1, %zmm0, %k1
+; KNL-NEXT:    vmovapd %zmm0, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
   %mask = fcmp ole <8 x double> %x, %y
   %max = select <8 x i1> %mask, <8 x double> %x, <8 x double> %y
   ret <8 x double> %max
 }
 
 define <16 x i32> @test3(<16 x i32> %x, <16 x i32> %x1, <16 x i32>* %yp) nounwind {
-; CHECK-LABEL: test3:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpeqd (%rdi), %zmm0, %k1
-; CHECK-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
-  %y = load <16 x i32>* %yp, align 4
+; KNL-LABEL: test3:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpeqd (%rdi), %zmm0, %k1
+; KNL-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
+  %y = load <16 x i32>, <16 x i32>* %yp, align 4
   %mask = icmp eq <16 x i32> %x, %y
   %max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
   ret <16 x i32> %max
 }
 
 define <16 x i32> @test4_unsigned(<16 x i32> %x, <16 x i32> %y, <16 x i32> %x1) nounwind {
-; CHECK-LABEL: test4_unsigned:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpnltud %zmm1, %zmm0, %k1
-; CHECK-NEXT:    vmovdqa32 %zmm2, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test4_unsigned:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpnltud %zmm1, %zmm0, %k1
+; KNL-NEXT:    vmovdqa32 %zmm2, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
   %mask = icmp uge <16 x i32> %x, %y
   %max = select <16 x i1> %mask, <16 x i32> %x1, <16 x i32> %y
   ret <16 x i32> %max
 }
 
 define <8 x i64> @test5(<8 x i64> %x, <8 x i64> %y) nounwind {
-; CHECK-LABEL: test5:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpeqq %zmm1, %zmm0, %k1
-; CHECK-NEXT:    vmovdqa64 %zmm0, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test5:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpeqq %zmm1, %zmm0, %k1
+; KNL-NEXT:    vmovdqa64 %zmm0, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
   %mask = icmp eq <8 x i64> %x, %y
   %max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %y
   ret <8 x i64> %max
 }
 
 define <8 x i64> @test6_unsigned(<8 x i64> %x, <8 x i64> %y, <8 x i64> %x1) nounwind {
-; CHECK-LABEL: test6_unsigned:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpnleuq %zmm1, %zmm0, %k1
-; CHECK-NEXT:    vmovdqa64 %zmm2, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test6_unsigned:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpnleuq %zmm1, %zmm0, %k1
+; KNL-NEXT:    vmovdqa64 %zmm2, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
   %mask = icmp ugt <8 x i64> %x, %y
   %max = select <8 x i1> %mask, <8 x i64> %x1, <8 x i64> %y
   ret <8 x i64> %max
 }
 
 define <4 x float> @test7(<4 x float> %a, <4 x float> %b) {
-; CHECK-LABEL: test7:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vcmpltps %xmm2, %xmm0, %xmm2
-; CHECK-NEXT:    vblendvps %xmm2, %xmm0, %xmm1, %xmm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test7:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vxorps %xmm2, %xmm2, %xmm2
+; KNL-NEXT:    vcmpltps %xmm2, %xmm0, %xmm2
+; KNL-NEXT:    vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; KNL-NEXT:    retq
+; SKX-LABEL: test7:
+; SKX:       ## BB#0:
+; SKX:    vxorps   %xmm2, %xmm2, %xmm2
+; SKX:    vcmpltps %xmm2, %xmm0, %k1 
+; SKX:    vmovaps  %xmm0, %xmm1 {%k1}
+; SKX:    vmovaps  %zmm1, %zmm0
+; SKX:    retq
+
   %mask = fcmp olt <4 x float> %a, zeroinitializer
   %c = select <4 x i1>%mask, <4 x float>%a, <4 x float>%b
   ret <4 x float>%c
 }
 
 define <2 x double> @test8(<2 x double> %a, <2 x double> %b) {
-; CHECK-LABEL: test8:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vxorpd %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vcmpltpd %xmm2, %xmm0, %xmm2
-; CHECK-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test8:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vxorpd %xmm2, %xmm2, %xmm2
+; KNL-NEXT:    vcmpltpd %xmm2, %xmm0, %xmm2
+; KNL-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; KNL-NEXT:    retq
+; SKX-LABEL: test8:
+; SKX:       ## BB#0:
+; SKX: vxorpd  %xmm2, %xmm2, %xmm2
+; SKX: vcmpltpd    %xmm2, %xmm0, %k1 
+; SKX: vmovapd %xmm0, %xmm1 {%k1}
+; SKX: vmovaps %zmm1, %zmm0
+; SKX: retq
   %mask = fcmp olt <2 x double> %a, zeroinitializer
   %c = select <2 x i1>%mask, <2 x double>%a, <2 x double>%b
   ret <2 x double>%c
 }
 
 define <8 x i32> @test9(<8 x i32> %x, <8 x i32> %y) nounwind {
-; CHECK-LABEL: test9:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:      ## kill: YMM1<def> YMM1<kill> ZMM1<def>
-; CHECK-NEXT:      ## kill: YMM0<def> YMM0<kill> ZMM0<def>
-; CHECK-NEXT:    vpcmpeqd %zmm1, %zmm0, %k1
-; CHECK-NEXT:    vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
-; CHECK-NEXT:      ## kill: YMM0<def> YMM0<kill> ZMM0<kill>
-; CHECK-NEXT:    retq
+; KNL-LABEL: test9:
+; KNL:       ## BB#0:
+; KNL-NEXT:      ## kill: YMM1<def> YMM1<kill> ZMM1<def>
+; KNL-NEXT:      ## kill: YMM0<def> YMM0<kill> ZMM0<def>
+; KNL-NEXT:    vpcmpeqd %zmm1, %zmm0, %k1
+; KNL-NEXT:    vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+; KNL-NEXT:      ## kill: YMM0<def> YMM0<kill> ZMM0<kill>
+; KNL-NEXT:    retq
   %mask = icmp eq <8 x i32> %x, %y
   %max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %y
   ret <8 x i32> %max
 }
 
 define <8 x float> @test10(<8 x float> %x, <8 x float> %y) nounwind {
-; CHECK-LABEL: test10:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:      ## kill: YMM1<def> YMM1<kill> ZMM1<def>
-; CHECK-NEXT:      ## kill: YMM0<def> YMM0<kill> ZMM0<def>
-; CHECK-NEXT:    vcmpeqps %zmm1, %zmm0, %k1
-; CHECK-NEXT:    vblendmps %zmm0, %zmm1, %zmm0 {%k1}
-; CHECK-NEXT:      ## kill: YMM0<def> YMM0<kill> ZMM0<kill>
-; CHECK-NEXT:    retq
+; KNL-LABEL: test10:
+; KNL:       ## BB#0:
+; KNL-NEXT:      ## kill: YMM1<def> YMM1<kill> ZMM1<def>
+; KNL-NEXT:      ## kill: YMM0<def> YMM0<kill> ZMM0<def>
+; KNL-NEXT:    vcmpeqps %zmm1, %zmm0, %k1
+; KNL-NEXT:    vblendmps %zmm0, %zmm1, %zmm0 {%k1}
+; KNL-NEXT:      ## kill: YMM0<def> YMM0<kill> ZMM0<kill>
+; KNL-NEXT:    retq
+; SKX-LABEL: test10:
+; SKX:       ## BB#0:
+; SKX: vcmpeqps    %ymm1, %ymm0, %k1 
+; SKX: vmovaps %ymm0, %ymm1 {%k1}
+; SKX: vmovaps %zmm1, %zmm0
+; SKX: retq
+
   %mask = fcmp oeq <8 x float> %x, %y
   %max = select <8 x i1> %mask, <8 x float> %x, <8 x float> %y
   ret <8 x float> %max
 }
 
 define <8 x i32> @test11_unsigned(<8 x i32> %x, <8 x i32> %y) nounwind {
-; CHECK-LABEL: test11_unsigned:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpmaxud %ymm1, %ymm0, %ymm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test11_unsigned:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpmaxud %ymm1, %ymm0, %ymm0
+; KNL-NEXT:    retq
   %mask = icmp ugt <8 x i32> %x, %y
   %max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %y
   ret <8 x i32> %max
@@ -137,25 +160,25 @@ define <8 x i32> @test11_unsigned(<8 x i32> %x, <8 x i32> %y) nounwind {
 
 
 define i16 @test12(<16 x i64> %a, <16 x i64> %b) nounwind {
-; CHECK-LABEL: test12:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpeqq %zmm2, %zmm0, %k0
-; CHECK-NEXT:    vpcmpeqq %zmm3, %zmm1, %k1
-; CHECK-NEXT:    kunpckbw %k0, %k1, %k0
-; CHECK-NEXT:    kmovw %k0, %eax
-; CHECK-NEXT:      ## kill: AX<def> AX<kill> EAX<kill>
-; CHECK-NEXT:    retq
+; KNL-LABEL: test12:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpeqq %zmm2, %zmm0, %k0
+; KNL-NEXT:    vpcmpeqq %zmm3, %zmm1, %k1
+; KNL-NEXT:    kunpckbw %k0, %k1, %k0
+; KNL-NEXT:    kmovw %k0, %eax
+; KNL-NEXT:      ## kill: AX<def> AX<kill> EAX<kill>
+; KNL-NEXT:    retq
   %res = icmp eq <16 x i64> %a, %b
   %res1 = bitcast <16 x i1> %res to i16
   ret i16 %res1
 }
 
 define <16 x i32> @test13(<16 x float>%a, <16 x float>%b)
-; CHECK-LABEL: test13:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vcmpeqps %zmm1, %zmm0, %k1
-; CHECK-NEXT:    vpbroadcastd {{.*}}(%rip), %zmm0 {%k1} {z}
-; CHECK-NEXT:    retq
+; KNL-LABEL: test13:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vcmpeqps %zmm1, %zmm0, %k1
+; KNL-NEXT:    vpbroadcastd {{.*}}(%rip), %zmm0 {%k1} {z}
+; KNL-NEXT:    retq
 {
   %cmpvector_i = fcmp oeq <16 x float> %a, %b
   %conv = zext <16 x i1> %cmpvector_i to <16 x i32>
@@ -163,14 +186,14 @@ define <16 x i32> @test13(<16 x float>%a, <16 x float>%b)
 }
 
 define <16 x i32> @test14(<16 x i32>%a, <16 x i32>%b) {
-; CHECK-LABEL: test14:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpsubd %zmm1, %zmm0, %zmm1
-; CHECK-NEXT:    vpcmpgtd %zmm0, %zmm1, %k0
-; CHECK-NEXT:    knotw %k0, %k0
-; CHECK-NEXT:    knotw %k0, %k1
-; CHECK-NEXT:    vmovdqu32 %zmm1, %zmm0 {%k1} {z}
-; CHECK-NEXT:    retq
+; KNL-LABEL: test14:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpsubd %zmm1, %zmm0, %zmm1
+; KNL-NEXT:    vpcmpgtd %zmm0, %zmm1, %k0
+; KNL-NEXT:    knotw %k0, %k0
+; KNL-NEXT:    knotw %k0, %k1
+; KNL-NEXT:    vmovdqu32 %zmm1, %zmm0 {%k1} {z}
+; KNL-NEXT:    retq
   %sub_r = sub <16 x i32> %a, %b
   %cmp.i2.i = icmp sgt <16 x i32> %sub_r, %a
   %sext.i3.i = sext <16 x i1> %cmp.i2.i to <16 x i32>
@@ -180,14 +203,14 @@ define <16 x i32> @test14(<16 x i32>%a, <16 x i32>%b) {
 }
 
 define <8 x i64> @test15(<8 x i64>%a, <8 x i64>%b) {
-; CHECK-LABEL: test15:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpsubq %zmm1, %zmm0, %zmm1
-; CHECK-NEXT:    vpcmpgtq %zmm0, %zmm1, %k0
-; CHECK-NEXT:    knotw %k0, %k0
-; CHECK-NEXT:    knotw %k0, %k1
-; CHECK-NEXT:    vmovdqu64 %zmm1, %zmm0 {%k1} {z}
-; CHECK-NEXT:    retq
+; KNL-LABEL: test15:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpsubq %zmm1, %zmm0, %zmm1
+; KNL-NEXT:    vpcmpgtq %zmm0, %zmm1, %k0
+; KNL-NEXT:    knotw %k0, %k0
+; KNL-NEXT:    knotw %k0, %k1
+; KNL-NEXT:    vmovdqu64 %zmm1, %zmm0 {%k1} {z}
+; KNL-NEXT:    retq
   %sub_r = sub <8 x i64> %a, %b
   %cmp.i2.i = icmp sgt <8 x i64> %sub_r, %a
   %sext.i3.i = sext <8 x i1> %cmp.i2.i to <8 x i64>
@@ -197,64 +220,64 @@ define <8 x i64> @test15(<8 x i64>%a, <8 x i64>%b) {
 }
 
 define <16 x i32> @test16(<16 x i32> %x, <16 x i32> %y, <16 x i32> %x1) nounwind {
-; CHECK-LABEL: test16:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpled %zmm0, %zmm1, %k1
-; CHECK-NEXT:    vmovdqa32 %zmm2, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test16:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpled %zmm0, %zmm1, %k1
+; KNL-NEXT:    vmovdqa32 %zmm2, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
   %mask = icmp sge <16 x i32> %x, %y
   %max = select <16 x i1> %mask, <16 x i32> %x1, <16 x i32> %y
   ret <16 x i32> %max
 }
 
 define <16 x i32> @test17(<16 x i32> %x, <16 x i32> %x1, <16 x i32>* %y.ptr) nounwind {
-; CHECK-LABEL: test17:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpgtd (%rdi), %zmm0, %k1
-; CHECK-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
-  %y = load <16 x i32>* %y.ptr, align 4
+; KNL-LABEL: test17:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpgtd (%rdi), %zmm0, %k1
+; KNL-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
+  %y = load <16 x i32>, <16 x i32>* %y.ptr, align 4
   %mask = icmp sgt <16 x i32> %x, %y
   %max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
   ret <16 x i32> %max
 }
 
 define <16 x i32> @test18(<16 x i32> %x, <16 x i32> %x1, <16 x i32>* %y.ptr) nounwind {
-; CHECK-LABEL: test18:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpled (%rdi), %zmm0, %k1
-; CHECK-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
-  %y = load <16 x i32>* %y.ptr, align 4
+; KNL-LABEL: test18:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpled (%rdi), %zmm0, %k1
+; KNL-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
+  %y = load <16 x i32>, <16 x i32>* %y.ptr, align 4
   %mask = icmp sle <16 x i32> %x, %y
   %max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
   ret <16 x i32> %max
 }
 
 define <16 x i32> @test19(<16 x i32> %x, <16 x i32> %x1, <16 x i32>* %y.ptr) nounwind {
-; CHECK-LABEL: test19:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpleud (%rdi), %zmm0, %k1
-; CHECK-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
-  %y = load <16 x i32>* %y.ptr, align 4
+; KNL-LABEL: test19:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpleud (%rdi), %zmm0, %k1
+; KNL-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
+  %y = load <16 x i32>, <16 x i32>* %y.ptr, align 4
   %mask = icmp ule <16 x i32> %x, %y
   %max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
   ret <16 x i32> %max
 }
 
 define <16 x i32> @test20(<16 x i32> %x, <16 x i32> %y, <16 x i32> %x1, <16 x i32> %y1) nounwind {
-; CHECK-LABEL: test20:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpeqd %zmm1, %zmm0, %k1
-; CHECK-NEXT:    vpcmpeqd %zmm3, %zmm2, %k1 {%k1}
-; CHECK-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test20:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpeqd %zmm1, %zmm0, %k1
+; KNL-NEXT:    vpcmpeqd %zmm3, %zmm2, %k1 {%k1}
+; KNL-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
   %mask1 = icmp eq <16 x i32> %x1, %y1
   %mask0 = icmp eq <16 x i32> %x, %y
   %mask = select <16 x i1> %mask0, <16 x i1> %mask1, <16 x i1> zeroinitializer
@@ -263,13 +286,13 @@ define <16 x i32> @test20(<16 x i32> %x, <16 x i32> %y, <16 x i32> %x1, <16 x i3
 }
 
 define <8 x i64> @test21(<8 x i64> %x, <8 x i64> %y, <8 x i64> %x1, <8 x i64> %y1) nounwind {
-; CHECK-LABEL: test21:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpleq %zmm1, %zmm0, %k1
-; CHECK-NEXT:    vpcmpleq %zmm2, %zmm3, %k1 {%k1}
-; CHECK-NEXT:    vmovdqa64 %zmm0, %zmm2 {%k1}
-; CHECK-NEXT:    vmovaps %zmm2, %zmm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test21:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpleq %zmm1, %zmm0, %k1
+; KNL-NEXT:    vpcmpleq %zmm2, %zmm3, %k1 {%k1}
+; KNL-NEXT:    vmovdqa64 %zmm0, %zmm2 {%k1}
+; KNL-NEXT:    vmovaps %zmm2, %zmm0
+; KNL-NEXT:    retq
   %mask1 = icmp sge <8 x i64> %x1, %y1
   %mask0 = icmp sle <8 x i64> %x, %y
   %mask = select <8 x i1> %mask0, <8 x i1> %mask1, <8 x i1> zeroinitializer
@@ -278,15 +301,15 @@ define <8 x i64> @test21(<8 x i64> %x, <8 x i64> %y, <8 x i64> %x1, <8 x i64> %y
 }
 
 define <8 x i64> @test22(<8 x i64> %x, <8 x i64>* %y.ptr, <8 x i64> %x1, <8 x i64> %y1) nounwind {
-; CHECK-LABEL: test22:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpgtq %zmm2, %zmm1, %k1
-; CHECK-NEXT:    vpcmpgtq (%rdi), %zmm0, %k1 {%k1}
-; CHECK-NEXT:    vmovdqa64 %zmm0, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test22:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpgtq %zmm2, %zmm1, %k1
+; KNL-NEXT:    vpcmpgtq (%rdi), %zmm0, %k1 {%k1}
+; KNL-NEXT:    vmovdqa64 %zmm0, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
   %mask1 = icmp sgt <8 x i64> %x1, %y1
-  %y = load <8 x i64>* %y.ptr, align 4
+  %y = load <8 x i64>, <8 x i64>* %y.ptr, align 4
   %mask0 = icmp sgt <8 x i64> %x, %y
   %mask = select <8 x i1> %mask0, <8 x i1> %mask1, <8 x i1> zeroinitializer
   %max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %x1
@@ -294,15 +317,15 @@ define <8 x i64> @test22(<8 x i64> %x, <8 x i64>* %y.ptr, <8 x i64> %x1, <8 x i6
 }
 
 define <16 x i32> @test23(<16 x i32> %x, <16 x i32>* %y.ptr, <16 x i32> %x1, <16 x i32> %y1) nounwind {
-; CHECK-LABEL: test23:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpled %zmm1, %zmm2, %k1
-; CHECK-NEXT:    vpcmpleud (%rdi), %zmm0, %k1 {%k1}
-; CHECK-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test23:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpled %zmm1, %zmm2, %k1
+; KNL-NEXT:    vpcmpleud (%rdi), %zmm0, %k1 {%k1}
+; KNL-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
   %mask1 = icmp sge <16 x i32> %x1, %y1
-  %y = load <16 x i32>* %y.ptr, align 4
+  %y = load <16 x i32>, <16 x i32>* %y.ptr, align 4
   %mask0 = icmp ule <16 x i32> %x, %y
   %mask = select <16 x i1> %mask0, <16 x i1> %mask1, <16 x i1> zeroinitializer
   %max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
@@ -310,13 +333,13 @@ define <16 x i32> @test23(<16 x i32> %x, <16 x i32>* %y.ptr, <16 x i32> %x1, <16
 }
 
 define <8 x i64> @test24(<8 x i64> %x, <8 x i64> %x1, i64* %yb.ptr) nounwind {
-; CHECK-LABEL: test24:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpeqq (%rdi){1to8}, %zmm0, %k1
-; CHECK-NEXT:    vmovdqa64 %zmm0, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
-  %yb = load i64* %yb.ptr, align 4
+; KNL-LABEL: test24:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpeqq (%rdi){1to8}, %zmm0, %k1
+; KNL-NEXT:    vmovdqa64 %zmm0, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
+  %yb = load i64, i64* %yb.ptr, align 4
   %y.0 = insertelement <8 x i64> undef, i64 %yb, i32 0
   %y = shufflevector <8 x i64> %y.0, <8 x i64> undef, <8 x i32> zeroinitializer
   %mask = icmp eq <8 x i64> %x, %y
@@ -325,13 +348,13 @@ define <8 x i64> @test24(<8 x i64> %x, <8 x i64> %x1, i64* %yb.ptr) nounwind {
 }
 
 define <16 x i32> @test25(<16 x i32> %x, i32* %yb.ptr, <16 x i32> %x1) nounwind {
-; CHECK-LABEL: test25:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpled (%rdi){1to16}, %zmm0, %k1
-; CHECK-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
-  %yb = load i32* %yb.ptr, align 4
+; KNL-LABEL: test25:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpled (%rdi){1to16}, %zmm0, %k1
+; KNL-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
+  %yb = load i32, i32* %yb.ptr, align 4
   %y.0 = insertelement <16 x i32> undef, i32 %yb, i32 0
   %y = shufflevector <16 x i32> %y.0, <16 x i32> undef, <16 x i32> zeroinitializer
   %mask = icmp sle <16 x i32> %x, %y
@@ -340,15 +363,15 @@ define <16 x i32> @test25(<16 x i32> %x, i32* %yb.ptr, <16 x i32> %x1) nounwind
 }
 
 define <16 x i32> @test26(<16 x i32> %x, i32* %yb.ptr, <16 x i32> %x1, <16 x i32> %y1) nounwind {
-; CHECK-LABEL: test26:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpled %zmm1, %zmm2, %k1
-; CHECK-NEXT:    vpcmpgtd (%rdi){1to16}, %zmm0, %k1 {%k1}
-; CHECK-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test26:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpled %zmm1, %zmm2, %k1
+; KNL-NEXT:    vpcmpgtd (%rdi){1to16}, %zmm0, %k1 {%k1}
+; KNL-NEXT:    vmovdqa32 %zmm0, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
   %mask1 = icmp sge <16 x i32> %x1, %y1
-  %yb = load i32* %yb.ptr, align 4
+  %yb = load i32, i32* %yb.ptr, align 4
   %y.0 = insertelement <16 x i32> undef, i32 %yb, i32 0
   %y = shufflevector <16 x i32> %y.0, <16 x i32> undef, <16 x i32> zeroinitializer
   %mask0 = icmp sgt <16 x i32> %x, %y
@@ -358,15 +381,15 @@ define <16 x i32> @test26(<16 x i32> %x, i32* %yb.ptr, <16 x i32> %x1, <16 x i32
 }
 
 define <8 x i64> @test27(<8 x i64> %x, i64* %yb.ptr, <8 x i64> %x1, <8 x i64> %y1) nounwind {
-; CHECK-LABEL: test27:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpcmpleq        %zmm1, %zmm2, %k1
-; CHECK-NEXT:    vpcmpleq        (%rdi){1to8}, %zmm0, %k1 {%k1}
-; CHECK-NEXT:    vmovdqa64 %zmm0, %zmm1 {%k1}
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test27:
+; KNL:       ## BB#0:
+; KNL-NEXT:    vpcmpleq        %zmm1, %zmm2, %k1
+; KNL-NEXT:    vpcmpleq        (%rdi){1to8}, %zmm0, %k1 {%k1}
+; KNL-NEXT:    vmovdqa64 %zmm0, %zmm1 {%k1}
+; KNL-NEXT:    vmovaps %zmm1, %zmm0
+; KNL-NEXT:    retq
   %mask1 = icmp sge <8 x i64> %x1, %y1
-  %yb = load i64* %yb.ptr, align 4
+  %yb = load i64, i64* %yb.ptr, align 4
   %y.0 = insertelement <8 x i64> undef, i64 %yb, i32 0
   %y = shufflevector <8 x i64> %y.0, <8 x i64> undef, <8 x i32> zeroinitializer
   %mask0 = icmp sle <8 x i64> %x, %y
@@ -374,3 +397,201 @@ define <8 x i64> @test27(<8 x i64> %x, i64* %yb.ptr, <8 x i64> %x1, <8 x i64> %y
   %max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %x1
   ret <8 x i64> %max
 }
+
+; KNL-LABEL: test28
+; KNL: vpcmpgtq
+; KNL: vpcmpgtq
+; KNL: kxorw
+define <8 x i32>@test28(<8 x i64> %x, <8 x i64> %y, <8 x i64> %x1, <8 x i64> %y1) {
+  %x_gt_y = icmp sgt <8 x i64> %x, %y
+  %x1_gt_y1 = icmp sgt <8 x i64> %x1, %y1
+  %res = icmp eq <8 x i1>%x_gt_y, %x1_gt_y1
+  %resse = sext <8 x i1>%res to <8 x i32>
+  ret <8 x i32> %resse
+}
+
+; KNL-LABEL: test29
+; KNL: vpcmpgtd
+; KNL: vpcmpgtd
+; KNL: kxnorw
+define <16 x i8>@test29(<16 x i32> %x, <16 x i32> %y, <16 x i32> %x1, <16 x i32> %y1) {
+  %x_gt_y = icmp sgt <16 x i32> %x, %y
+  %x1_gt_y1 = icmp sgt <16 x i32> %x1, %y1
+  %res = icmp ne <16 x i1>%x_gt_y, %x1_gt_y1
+  %resse = sext <16 x i1>%res to <16 x i8>
+  ret <16 x i8> %resse
+}
+
+define <4 x double> @test30(<4 x double> %x, <4 x double> %y) nounwind {
+; SKX-LABEL: test30:
+; SKX: vcmpeqpd   %ymm1, %ymm0, %k1 
+; SKX: vmovapd    %ymm0, %ymm1 {%k1}
+
+  %mask = fcmp oeq <4 x double> %x, %y
+  %max = select <4 x i1> %mask, <4 x double> %x, <4 x double> %y
+  ret <4 x double> %max
+}
+
+define <2 x double> @test31(<2 x double> %x, <2 x double> %x1, <2 x double>* %yp) nounwind {
+; SKX-LABEL: test31:     
+; SKX: vcmpltpd        (%rdi), %xmm0, %k1 
+; SKX: vmovapd %xmm0, %xmm1 {%k1}
+
+  %y = load <2 x double>, <2 x double>* %yp, align 4
+  %mask = fcmp olt <2 x double> %x, %y
+  %max = select <2 x i1> %mask, <2 x double> %x, <2 x double> %x1
+  ret <2 x double> %max
+}
+
+define <4 x double> @test32(<4 x double> %x, <4 x double> %x1, <4 x double>* %yp) nounwind {
+; SKX-LABEL: test32:
+; SKX: vcmpltpd        (%rdi), %ymm0, %k1 
+; SKX: vmovapd %ymm0, %ymm1 {%k1}
+
+  %y = load <4 x double>, <4 x double>* %yp, align 4
+  %mask = fcmp ogt <4 x double> %y, %x
+  %max = select <4 x i1> %mask, <4 x double> %x, <4 x double> %x1
+  ret <4 x double> %max
+}
+
+define <8 x double> @test33(<8 x double> %x, <8 x double> %x1, <8 x double>* %yp) nounwind {
+; SKX-LABEL: test33:     
+; SKX: vcmpltpd        (%rdi), %zmm0, %k1 
+; SKX: vmovapd %zmm0, %zmm1 {%k1}
+  %y = load <8 x double>, <8 x double>* %yp, align 4
+  %mask = fcmp olt <8 x double> %x, %y
+  %max = select <8 x i1> %mask, <8 x double> %x, <8 x double> %x1
+  ret <8 x double> %max
+}
+
+define <4 x float> @test34(<4 x float> %x, <4 x float> %x1, <4 x float>* %yp) nounwind {
+; SKX-LABEL: test34:     
+; SKX: vcmpltps        (%rdi), %xmm0, %k1 
+; SKX: vmovaps %xmm0, %xmm1 {%k1}
+  %y = load <4 x float>, <4 x float>* %yp, align 4
+  %mask = fcmp olt <4 x float> %x, %y
+  %max = select <4 x i1> %mask, <4 x float> %x, <4 x float> %x1
+  ret <4 x float> %max
+}
+
+define <8 x float> @test35(<8 x float> %x, <8 x float> %x1, <8 x float>* %yp) nounwind {
+; SKX-LABEL: test35:
+; SKX: vcmpltps        (%rdi), %ymm0, %k1 
+; SKX: vmovaps %ymm0, %ymm1 {%k1}
+
+  %y = load <8 x float>, <8 x float>* %yp, align 4
+  %mask = fcmp ogt <8 x float> %y, %x
+  %max = select <8 x i1> %mask, <8 x float> %x, <8 x float> %x1
+  ret <8 x float> %max
+}
+
+define <16 x float> @test36(<16 x float> %x, <16 x float> %x1, <16 x float>* %yp) nounwind {
+; SKX-LABEL: test36:     
+; SKX: vcmpltps        (%rdi), %zmm0, %k1 
+; SKX: vmovaps %zmm0, %zmm1 {%k1}
+  %y = load <16 x float>, <16 x float>* %yp, align 4
+  %mask = fcmp olt <16 x float> %x, %y
+  %max = select <16 x i1> %mask, <16 x float> %x, <16 x float> %x1
+  ret <16 x float> %max
+}
+
+define <8 x double> @test37(<8 x double> %x, <8 x double> %x1, double* %ptr) nounwind {
+; SKX-LABEL: test37:                                
+; SKX: vcmpltpd  (%rdi){1to8}, %zmm0, %k1 
+; SKX: vmovapd %zmm0, %zmm1 {%k1}
+
+  %a = load double, double* %ptr
+  %v = insertelement <8 x double> undef, double %a, i32 0
+  %shuffle = shufflevector <8 x double> %v, <8 x double> undef, <8 x i32> zeroinitializer
+
+  %mask = fcmp ogt <8 x double> %shuffle, %x
+  %max = select <8 x i1> %mask, <8 x double> %x, <8 x double> %x1
+  ret <8 x double> %max
+}
+
+define <4 x double> @test38(<4 x double> %x, <4 x double> %x1, double* %ptr) nounwind {
+; SKX-LABEL: test38:                                
+; SKX: vcmpltpd  (%rdi){1to4}, %ymm0, %k1 
+; SKX: vmovapd %ymm0, %ymm1 {%k1}
+
+  %a = load double, double* %ptr
+  %v = insertelement <4 x double> undef, double %a, i32 0
+  %shuffle = shufflevector <4 x double> %v, <4 x double> undef, <4 x i32> zeroinitializer
+  
+  %mask = fcmp ogt <4 x double> %shuffle, %x
+  %max = select <4 x i1> %mask, <4 x double> %x, <4 x double> %x1
+  ret <4 x double> %max
+}
+
+define <2 x double> @test39(<2 x double> %x, <2 x double> %x1, double* %ptr) nounwind {
+; SKX-LABEL: test39:                                
+; SKX: vcmpltpd  (%rdi){1to2}, %xmm0, %k1 
+; SKX: vmovapd %xmm0, %xmm1 {%k1}
+
+  %a = load double, double* %ptr
+  %v = insertelement <2 x double> undef, double %a, i32 0
+  %shuffle = shufflevector <2 x double> %v, <2 x double> undef, <2 x i32> <i32 0, i32 0>
+  
+  %mask = fcmp ogt <2 x double> %shuffle, %x
+  %max = select <2 x i1> %mask, <2 x double> %x, <2 x double> %x1
+  ret <2 x double> %max
+}
+
+
+define <16  x float> @test40(<16  x float> %x, <16  x float> %x1, float* %ptr) nounwind {
+; SKX-LABEL: test40:                                
+; SKX: vcmpltps  (%rdi){1to16}, %zmm0, %k1 
+; SKX: vmovaps %zmm0, %zmm1 {%k1}
+
+  %a = load float, float* %ptr
+  %v = insertelement <16  x float> undef, float %a, i32 0
+  %shuffle = shufflevector <16  x float> %v, <16  x float> undef, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+  
+  %mask = fcmp ogt <16  x float> %shuffle, %x
+  %max = select <16 x i1> %mask, <16  x float> %x, <16  x float> %x1
+  ret <16  x float> %max
+}
+
+define <8  x float> @test41(<8  x float> %x, <8  x float> %x1, float* %ptr) nounwind {
+; SKX-LABEL: test41:                                
+; SKX: vcmpltps  (%rdi){1to8}, %ymm0, %k1 
+; SKX: vmovaps %ymm0, %ymm1 {%k1}
+
+  %a = load float, float* %ptr
+  %v = insertelement <8  x float> undef, float %a, i32 0
+  %shuffle = shufflevector <8  x float> %v, <8  x float> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+  
+  %mask = fcmp ogt <8  x float> %shuffle, %x
+  %max = select <8 x i1> %mask, <8  x float> %x, <8  x float> %x1
+  ret <8  x float> %max
+}
+
+define <4  x float> @test42(<4  x float> %x, <4  x float> %x1, float* %ptr) nounwind {
+; SKX-LABEL: test42:                                
+; SKX: vcmpltps  (%rdi){1to4}, %xmm0, %k1 
+; SKX: vmovaps %xmm0, %xmm1 {%k1}
+  
+  %a = load float, float* %ptr
+  %v = insertelement <4  x float> undef, float %a, i32 0
+  %shuffle = shufflevector <4  x float> %v, <4  x float> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
+  
+  %mask = fcmp ogt <4  x float> %shuffle, %x
+  %max = select <4 x i1> %mask, <4  x float> %x, <4  x float> %x1
+  ret <4  x float> %max
+}
+
+define <8 x double> @test43(<8 x double> %x, <8 x double> %x1, double* %ptr,<8 x i1> %mask_in) nounwind {
+; SKX-LABEL: test43:                                
+; SKX: vpmovw2m  %xmm2, %k1
+; SKX: vcmpltpd  (%rdi){1to8}, %zmm0, %k1 {%k1}
+; SKX: vmovapd %zmm0, %zmm1 {%k1}
+
+  %a = load double, double* %ptr
+  %v = insertelement <8 x double> undef, double %a, i32 0
+  %shuffle = shufflevector <8 x double> %v, <8 x double> undef, <8 x i32> zeroinitializer
+  
+  %mask_cmp = fcmp ogt <8 x double> %shuffle, %x
+  %mask = and <8 x i1> %mask_cmp, %mask_in
+  %max = select <8 x i1> %mask, <8 x double> %x, <8 x double> %x1
+  ret <8 x double> %max
+}
diff --git a/test/CodeGen/X86/avx512bw-arith.ll b/test/CodeGen/X86/avx512bw-arith.ll
index 94f68a2ddc28..52ebf27b6b72 100644
--- a/test/CodeGen/X86/avx512bw-arith.ll
+++ b/test/CodeGen/X86/avx512bw-arith.ll
@@ -12,7 +12,7 @@ define <64 x i8> @vpaddb512_test(<64 x i8> %i, <64 x i8> %j) nounwind readnone {
 ; CHECK: vpaddb (%rdi), %zmm{{.*}}
 ; CHECK: ret
 define <64 x i8> @vpaddb512_fold_test(<64 x i8> %i, <64 x i8>* %j) nounwind {
-  %tmp = load <64 x i8>* %j, align 4
+  %tmp = load <64 x i8>, <64 x i8>* %j, align 4
   %x = add <64 x i8> %i, %tmp
   ret <64 x i8> %x
 }
@@ -29,7 +29,7 @@ define <32 x i16> @vpaddw512_test(<32 x i16> %i, <32 x i16> %j) nounwind readnon
 ; CHECK: vpaddw (%rdi), %zmm{{.*}}
 ; CHECK: ret
 define <32 x i16> @vpaddw512_fold_test(<32 x i16> %i, <32 x i16>* %j) nounwind {
-  %tmp = load <32 x i16>* %j, align 4
+  %tmp = load <32 x i16>, <32 x i16>* %j, align 4
   %x = add <32 x i16> %i, %tmp
   ret <32 x i16> %x
 }
@@ -59,7 +59,7 @@ define <32 x i16> @vpaddw512_maskz_test(<32 x i16> %i, <32 x i16> %j, <32 x i16>
 ; CHECK: ret
 define <32 x i16> @vpaddw512_mask_fold_test(<32 x i16> %i, <32 x i16>* %j.ptr, <32 x i16> %mask1) nounwind readnone {
   %mask = icmp ne <32 x i16> %mask1, zeroinitializer
-  %j = load <32 x i16>* %j.ptr
+  %j = load <32 x i16>, <32 x i16>* %j.ptr
   %x = add <32 x i16> %i, %j
   %r = select <32 x i1> %mask, <32 x i16> %x, <32 x i16> %i
   ret <32 x i16> %r
@@ -70,7 +70,7 @@ define <32 x i16> @vpaddw512_mask_fold_test(<32 x i16> %i, <32 x i16>* %j.ptr, <
 ; CHECK: ret
 define <32 x i16> @vpaddw512_maskz_fold_test(<32 x i16> %i, <32 x i16>* %j.ptr, <32 x i16> %mask1) nounwind readnone {
   %mask = icmp ne <32 x i16> %mask1, zeroinitializer
-  %j = load <32 x i16>* %j.ptr
+  %j = load <32 x i16>, <32 x i16>* %j.ptr
   %x = add <32 x i16> %i, %j
   %r = select <32 x i1> %mask, <32 x i16> %x, <32 x i16> zeroinitializer
   ret <32 x i16> %r
diff --git a/test/CodeGen/X86/avx512bw-intrinsics.ll b/test/CodeGen/X86/avx512bw-intrinsics.ll
index c807d222ce53..0db2941cac6f 100644
--- a/test/CodeGen/X86/avx512bw-intrinsics.ll
+++ b/test/CodeGen/X86/avx512bw-intrinsics.ll
@@ -351,3 +351,440 @@ define <8 x i16> @test_x86_mask_blend_w_128(i8 %mask, <8 x i16> %a1, <8 x i16> %
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.avx512.mask.blend.w.128(<8 x i16>, <8 x i16>, i8) nounwind readonly
+
+define <32 x i16> @test_mask_packs_epi32_rr_512(<16 x i32> %a, <16 x i32> %b) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rr_512
+  ;CHECK: vpackssdw       %zmm1, %zmm0, %zmm0  ## encoding: [0x62,0xf1,0x7d,0x48,0x6b,0xc1]
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packssdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packs_epi32_rrk_512(<16 x i32> %a, <16 x i32> %b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rrk_512
+  ;CHECK: vpackssdw       %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0x6b,0xd1]
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packssdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packs_epi32_rrkz_512(<16 x i32> %a, <16 x i32> %b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rrkz_512
+  ;CHECK: vpackssdw       %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0x6b,0xc1]
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packssdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packs_epi32_rm_512(<16 x i32> %a, <16 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rm_512
+  ;CHECK: vpackssdw       (%rdi), %zmm0, %zmm0  ## encoding: [0x62,0xf1,0x7d,0x48,0x6b,0x07]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packssdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packs_epi32_rmk_512(<16 x i32> %a, <16 x i32>* %ptr_b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rmk_512
+  ;CHECK: vpackssdw       (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0x6b,0x0f]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packssdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packs_epi32_rmkz_512(<16 x i32> %a, <16 x i32>* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rmkz_512
+  ;CHECK: vpackssdw       (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0x6b,0x07]
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packssdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packs_epi32_rmb_512(<16 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rmb_512
+  ;CHECK: vpackssdw       (%rdi){1to16}, %zmm0, %zmm0  ## encoding: [0x62,0xf1,0x7d,0x58,0x6b,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packssdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packs_epi32_rmbk_512(<16 x i32> %a, i32* %ptr_b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rmbk_512
+  ;CHECK: vpackssdw       (%rdi){1to16}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x59,0x6b,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packssdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packs_epi32_rmbkz_512(<16 x i32> %a, i32* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rmbkz_512
+  ;CHECK: vpackssdw       (%rdi){1to16}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xd9,0x6b,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packssdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+declare <32 x i16> @llvm.x86.avx512.mask.packssdw.512(<16 x i32>, <16 x i32>, <32 x i16>, i32)
+
+define <64 x i8> @test_mask_packs_epi16_rr_512(<32 x i16> %a, <32 x i16> %b) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rr_512
+  ;CHECK: vpacksswb       %zmm1, %zmm0, %zmm0  ## encoding: [0x62,0xf1,0xfd,0x48,0x63,0xc1]
+  %res = call <64 x i8> @llvm.x86.avx512.mask.packsswb.512(<32 x i16> %a, <32 x i16> %b, <64 x i8> zeroinitializer, i64 -1)
+  ret <64 x i8> %res
+}
+
+define <64 x i8> @test_mask_packs_epi16_rrk_512(<32 x i16> %a, <32 x i16> %b, <64 x i8> %passThru, i64 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rrk_512
+  ;CHECK: vpacksswb       %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0x63,0xd1]
+  %res = call <64 x i8> @llvm.x86.avx512.mask.packsswb.512(<32 x i16> %a, <32 x i16> %b, <64 x i8> %passThru, i64 %mask)
+  ret <64 x i8> %res
+}
+
+define <64 x i8> @test_mask_packs_epi16_rrkz_512(<32 x i16> %a, <32 x i16> %b, i64 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rrkz_512
+  ;CHECK: vpacksswb       %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0x63,0xc1]
+  %res = call <64 x i8> @llvm.x86.avx512.mask.packsswb.512(<32 x i16> %a, <32 x i16> %b, <64 x i8> zeroinitializer, i64 %mask)
+  ret <64 x i8> %res
+}
+
+define <64 x i8> @test_mask_packs_epi16_rm_512(<32 x i16> %a, <32 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rm_512
+  ;CHECK: vpacksswb       (%rdi), %zmm0, %zmm0  ## encoding: [0x62,0xf1,0xfd,0x48,0x63,0x07]
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <64 x i8> @llvm.x86.avx512.mask.packsswb.512(<32 x i16> %a, <32 x i16> %b, <64 x i8> zeroinitializer, i64 -1)
+  ret <64 x i8> %res
+}
+
+define <64 x i8> @test_mask_packs_epi16_rmk_512(<32 x i16> %a, <32 x i16>* %ptr_b, <64 x i8> %passThru, i64 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rmk_512
+  ;CHECK: vpacksswb       (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0x63,0x0f]
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <64 x i8> @llvm.x86.avx512.mask.packsswb.512(<32 x i16> %a, <32 x i16> %b, <64 x i8> %passThru, i64 %mask)
+  ret <64 x i8> %res
+}
+
+define <64 x i8> @test_mask_packs_epi16_rmkz_512(<32 x i16> %a, <32 x i16>* %ptr_b, i64 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rmkz_512
+  ;CHECK: vpacksswb       (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0x63,0x07]
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <64 x i8> @llvm.x86.avx512.mask.packsswb.512(<32 x i16> %a, <32 x i16> %b, <64 x i8> zeroinitializer, i64 %mask)
+  ret <64 x i8> %res
+}
+
+declare <64 x i8> @llvm.x86.avx512.mask.packsswb.512(<32 x i16>, <32 x i16>, <64 x i8>, i64)
+
+
+define <32 x i16> @test_mask_packus_epi32_rr_512(<16 x i32> %a, <16 x i32> %b) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rr_512
+  ;CHECK: vpackusdw       %zmm1, %zmm0, %zmm0  
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packusdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packus_epi32_rrk_512(<16 x i32> %a, <16 x i32> %b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rrk_512
+  ;CHECK: vpackusdw       %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packusdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packus_epi32_rrkz_512(<16 x i32> %a, <16 x i32> %b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rrkz_512
+  ;CHECK: vpackusdw       %zmm1, %zmm0, %zmm0 {%k1} {z} 
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packusdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packus_epi32_rm_512(<16 x i32> %a, <16 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rm_512
+  ;CHECK: vpackusdw       (%rdi), %zmm0, %zmm0  
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packusdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packus_epi32_rmk_512(<16 x i32> %a, <16 x i32>* %ptr_b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rmk_512
+  ;CHECK: vpackusdw       (%rdi), %zmm0, %zmm1 {%k1} 
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packusdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packus_epi32_rmkz_512(<16 x i32> %a, <16 x i32>* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rmkz_512
+  ;CHECK: vpackusdw       (%rdi), %zmm0, %zmm0 {%k1} {z} 
+  %b = load <16 x i32>, <16 x i32>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packusdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packus_epi32_rmb_512(<16 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rmb_512
+  ;CHECK: vpackusdw       (%rdi){1to16}, %zmm0, %zmm0  
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packusdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packus_epi32_rmbk_512(<16 x i32> %a, i32* %ptr_b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rmbk_512
+  ;CHECK: vpackusdw       (%rdi){1to16}, %zmm0, %zmm1 {%k1} 
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packusdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_packus_epi32_rmbkz_512(<16 x i32> %a, i32* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rmbkz_512
+  ;CHECK: vpackusdw       (%rdi){1to16}, %zmm0, %zmm0 {%k1} {z} 
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  %res = call <32 x i16> @llvm.x86.avx512.mask.packusdw.512(<16 x i32> %a, <16 x i32> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+declare <32 x i16> @llvm.x86.avx512.mask.packusdw.512(<16 x i32>, <16 x i32>, <32 x i16>, i32)
+
+define <64 x i8> @test_mask_packus_epi16_rr_512(<32 x i16> %a, <32 x i16> %b) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rr_512
+  ;CHECK: vpackuswb       %zmm1, %zmm0, %zmm0  
+  %res = call <64 x i8> @llvm.x86.avx512.mask.packuswb.512(<32 x i16> %a, <32 x i16> %b, <64 x i8> zeroinitializer, i64 -1)
+  ret <64 x i8> %res
+}
+
+define <64 x i8> @test_mask_packus_epi16_rrk_512(<32 x i16> %a, <32 x i16> %b, <64 x i8> %passThru, i64 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rrk_512
+  ;CHECK: vpackuswb       %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <64 x i8> @llvm.x86.avx512.mask.packuswb.512(<32 x i16> %a, <32 x i16> %b, <64 x i8> %passThru, i64 %mask)
+  ret <64 x i8> %res
+}
+
+define <64 x i8> @test_mask_packus_epi16_rrkz_512(<32 x i16> %a, <32 x i16> %b, i64 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rrkz_512
+  ;CHECK: vpackuswb       %zmm1, %zmm0, %zmm0 {%k1} {z} 
+  %res = call <64 x i8> @llvm.x86.avx512.mask.packuswb.512(<32 x i16> %a, <32 x i16> %b, <64 x i8> zeroinitializer, i64 %mask)
+  ret <64 x i8> %res
+}
+
+define <64 x i8> @test_mask_packus_epi16_rm_512(<32 x i16> %a, <32 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rm_512
+  ;CHECK: vpackuswb       (%rdi), %zmm0, %zmm0  
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <64 x i8> @llvm.x86.avx512.mask.packuswb.512(<32 x i16> %a, <32 x i16> %b, <64 x i8> zeroinitializer, i64 -1)
+  ret <64 x i8> %res
+}
+
+define <64 x i8> @test_mask_packus_epi16_rmk_512(<32 x i16> %a, <32 x i16>* %ptr_b, <64 x i8> %passThru, i64 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rmk_512
+  ;CHECK: vpackuswb       (%rdi), %zmm0, %zmm1 {%k1} 
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <64 x i8> @llvm.x86.avx512.mask.packuswb.512(<32 x i16> %a, <32 x i16> %b, <64 x i8> %passThru, i64 %mask)
+  ret <64 x i8> %res
+}
+
+define <64 x i8> @test_mask_packus_epi16_rmkz_512(<32 x i16> %a, <32 x i16>* %ptr_b, i64 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rmkz_512
+  ;CHECK: vpackuswb       (%rdi), %zmm0, %zmm0 {%k1} {z} 
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <64 x i8> @llvm.x86.avx512.mask.packuswb.512(<32 x i16> %a, <32 x i16> %b, <64 x i8> zeroinitializer, i64 %mask)
+  ret <64 x i8> %res
+}
+
+declare <64 x i8> @llvm.x86.avx512.mask.packuswb.512(<32 x i16>, <32 x i16>, <64 x i8>, i64)
+
+define <32 x i16> @test_mask_adds_epi16_rr_512(<32 x i16> %a, <32 x i16> %b) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rr_512
+  ;CHECK: vpaddsw %zmm1, %zmm0, %zmm0     
+  %res = call <32 x i16> @llvm.x86.avx512.mask.padds.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_adds_epi16_rrk_512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rrk_512
+  ;CHECK: vpaddsw %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <32 x i16> @llvm.x86.avx512.mask.padds.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_adds_epi16_rrkz_512(<32 x i16> %a, <32 x i16> %b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rrkz_512
+  ;CHECK: vpaddsw %zmm1, %zmm0, %zmm0 {%k1} {z} 
+  %res = call <32 x i16> @llvm.x86.avx512.mask.padds.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_adds_epi16_rm_512(<32 x i16> %a, <32 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rm_512
+  ;CHECK: vpaddsw (%rdi), %zmm0, %zmm0    
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.padds.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_adds_epi16_rmk_512(<32 x i16> %a, <32 x i16>* %ptr_b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rmk_512
+  ;CHECK: vpaddsw (%rdi), %zmm0, %zmm1 {%k1} 
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.padds.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_adds_epi16_rmkz_512(<32 x i16> %a, <32 x i16>* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rmkz_512
+  ;CHECK: vpaddsw (%rdi), %zmm0, %zmm0 {%k1} {z} 
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.padds.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+declare <32 x i16> @llvm.x86.avx512.mask.padds.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)
+
+define <32 x i16> @test_mask_subs_epi16_rr_512(<32 x i16> %a, <32 x i16> %b) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rr_512
+  ;CHECK: vpsubsw %zmm1, %zmm0, %zmm0     
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psubs.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_subs_epi16_rrk_512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rrk_512
+  ;CHECK: vpsubsw %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psubs.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_subs_epi16_rrkz_512(<32 x i16> %a, <32 x i16> %b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rrkz_512
+  ;CHECK: vpsubsw %zmm1, %zmm0, %zmm0 {%k1} {z} 
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psubs.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_subs_epi16_rm_512(<32 x i16> %a, <32 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rm_512
+  ;CHECK: vpsubsw (%rdi), %zmm0, %zmm0    
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psubs.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_subs_epi16_rmk_512(<32 x i16> %a, <32 x i16>* %ptr_b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rmk_512
+  ;CHECK: vpsubsw (%rdi), %zmm0, %zmm1 {%k1} 
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psubs.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_subs_epi16_rmkz_512(<32 x i16> %a, <32 x i16>* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rmkz_512
+  ;CHECK: vpsubsw (%rdi), %zmm0, %zmm0 {%k1} {z} 
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psubs.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+declare <32 x i16> @llvm.x86.avx512.mask.psubs.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)
+
+define <32 x i16> @test_mask_adds_epu16_rr_512(<32 x i16> %a, <32 x i16> %b) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rr_512
+  ;CHECK: vpaddusw %zmm1, %zmm0, %zmm0     
+  %res = call <32 x i16> @llvm.x86.avx512.mask.paddus.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_adds_epu16_rrk_512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rrk_512
+  ;CHECK: vpaddusw %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <32 x i16> @llvm.x86.avx512.mask.paddus.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_adds_epu16_rrkz_512(<32 x i16> %a, <32 x i16> %b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rrkz_512
+  ;CHECK: vpaddusw %zmm1, %zmm0, %zmm0 {%k1} {z} 
+  %res = call <32 x i16> @llvm.x86.avx512.mask.paddus.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_adds_epu16_rm_512(<32 x i16> %a, <32 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rm_512
+  ;CHECK: vpaddusw (%rdi), %zmm0, %zmm0    
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.paddus.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_adds_epu16_rmk_512(<32 x i16> %a, <32 x i16>* %ptr_b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rmk_512
+  ;CHECK: vpaddusw (%rdi), %zmm0, %zmm1 {%k1} 
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.paddus.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_adds_epu16_rmkz_512(<32 x i16> %a, <32 x i16>* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rmkz_512
+  ;CHECK: vpaddusw (%rdi), %zmm0, %zmm0 {%k1} {z} 
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.paddus.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+declare <32 x i16> @llvm.x86.avx512.mask.paddus.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)
+
+define <32 x i16> @test_mask_subs_epu16_rr_512(<32 x i16> %a, <32 x i16> %b) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rr_512
+  ;CHECK: vpsubusw %zmm1, %zmm0, %zmm0     
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psubus.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_subs_epu16_rrk_512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rrk_512
+  ;CHECK: vpsubusw %zmm1, %zmm0, %zmm2 {%k1} 
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psubus.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_subs_epu16_rrkz_512(<32 x i16> %a, <32 x i16> %b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rrkz_512
+  ;CHECK: vpsubusw %zmm1, %zmm0, %zmm0 {%k1} {z} 
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psubus.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_subs_epu16_rm_512(<32 x i16> %a, <32 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rm_512
+  ;CHECK: vpsubusw (%rdi), %zmm0, %zmm0    
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psubus.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_subs_epu16_rmk_512(<32 x i16> %a, <32 x i16>* %ptr_b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rmk_512
+  ;CHECK: vpsubusw (%rdi), %zmm0, %zmm1 {%k1} 
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psubus.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_subs_epu16_rmkz_512(<32 x i16> %a, <32 x i16>* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rmkz_512
+  ;CHECK: vpsubusw (%rdi), %zmm0, %zmm0 {%k1} {z} 
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psubus.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+declare <32 x i16> @llvm.x86.avx512.mask.psubus.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)
diff --git a/test/CodeGen/X86/avx512bw-mask-op.ll b/test/CodeGen/X86/avx512bw-mask-op.ll
index 9d7630c5d0ad..0208011cf89d 100644
--- a/test/CodeGen/X86/avx512bw-mask-op.ll
+++ b/test/CodeGen/X86/avx512bw-mask-op.ll
@@ -35,7 +35,7 @@ define i64 @mask64(i64 %x) {
 }
 
 define void @mask32_mem(i32* %ptr) {
-  %x = load i32* %ptr, align 4
+  %x = load i32, i32* %ptr, align 4
   %m0 = bitcast i32 %x to <32 x i1>
   %m1 = xor <32 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1,
                             i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1,
@@ -52,7 +52,7 @@ define void @mask32_mem(i32* %ptr) {
 }
 
 define void @mask64_mem(i64* %ptr) {
-  %x = load i64* %ptr, align 4
+  %x = load i64, i64* %ptr, align 4
   %m0 = bitcast i64 %x to <64 x i1>
   %m1 = xor <64 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1,
                             i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1,
diff --git a/test/CodeGen/X86/avx512bw-mov.ll b/test/CodeGen/X86/avx512bw-mov.ll
index 2ff6d280ab8f..519b649ff53a 100644
--- a/test/CodeGen/X86/avx512bw-mov.ll
+++ b/test/CodeGen/X86/avx512bw-mov.ll
@@ -5,7 +5,7 @@
 ; CHECK: ret
 define <64 x i8> @test1(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <64 x i8>*
-  %res = load <64 x i8>* %vaddr, align 1
+  %res = load <64 x i8>, <64 x i8>* %vaddr, align 1
   ret <64 x i8>%res
 }
 
@@ -24,7 +24,7 @@ define void @test2(i8 * %addr, <64 x i8> %data) {
 define <64 x i8> @test3(i8 * %addr, <64 x i8> %old, <64 x i8> %mask1) {
   %mask = icmp ne <64 x i8> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <64 x i8>*
-  %r = load <64 x i8>* %vaddr, align 1
+  %r = load <64 x i8>, <64 x i8>* %vaddr, align 1
   %res = select <64 x i1> %mask, <64 x i8> %r, <64 x i8> %old
   ret <64 x i8>%res
 }
@@ -35,7 +35,7 @@ define <64 x i8> @test3(i8 * %addr, <64 x i8> %old, <64 x i8> %mask1) {
 define <64 x i8> @test4(i8 * %addr, <64 x i8> %mask1) {
   %mask = icmp ne <64 x i8> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <64 x i8>*
-  %r = load <64 x i8>* %vaddr, align 1
+  %r = load <64 x i8>, <64 x i8>* %vaddr, align 1
   %res = select <64 x i1> %mask, <64 x i8> %r, <64 x i8> zeroinitializer
   ret <64 x i8>%res
 }
@@ -45,7 +45,7 @@ define <64 x i8> @test4(i8 * %addr, <64 x i8> %mask1) {
 ; CHECK: ret
 define <32 x i16> @test5(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <32 x i16>*
-  %res = load <32 x i16>* %vaddr, align 1
+  %res = load <32 x i16>, <32 x i16>* %vaddr, align 1
   ret <32 x i16>%res
 }
 
@@ -64,7 +64,7 @@ define void @test6(i8 * %addr, <32 x i16> %data) {
 define <32 x i16> @test7(i8 * %addr, <32 x i16> %old, <32 x i16> %mask1) {
   %mask = icmp ne <32 x i16> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <32 x i16>*
-  %r = load <32 x i16>* %vaddr, align 1
+  %r = load <32 x i16>, <32 x i16>* %vaddr, align 1
   %res = select <32 x i1> %mask, <32 x i16> %r, <32 x i16> %old
   ret <32 x i16>%res
 }
@@ -75,7 +75,7 @@ define <32 x i16> @test7(i8 * %addr, <32 x i16> %old, <32 x i16> %mask1) {
 define <32 x i16> @test8(i8 * %addr, <32 x i16> %mask1) {
   %mask = icmp ne <32 x i16> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <32 x i16>*
-  %r = load <32 x i16>* %vaddr, align 1
+  %r = load <32 x i16>, <32 x i16>* %vaddr, align 1
   %res = select <32 x i1> %mask, <32 x i16> %r, <32 x i16> zeroinitializer
   ret <32 x i16>%res
 }
diff --git a/test/CodeGen/X86/avx512bw-vec-cmp.ll b/test/CodeGen/X86/avx512bw-vec-cmp.ll
index 6ba4db68662e..141f5cc09219 100644
--- a/test/CodeGen/X86/avx512bw-vec-cmp.ll
+++ b/test/CodeGen/X86/avx512bw-vec-cmp.ll
@@ -45,7 +45,7 @@ define <64 x i8> @test4(<64 x i8> %x, <64 x i8> %y, <64 x i8> %x1) nounwind {
 ; CHECK: vmovdqu16
 ; CHECK: ret
 define <32 x i16> @test5(<32 x i16> %x, <32 x i16> %x1, <32 x i16>* %yp) nounwind {
-  %y = load <32 x i16>* %yp, align 4
+  %y = load <32 x i16>, <32 x i16>* %yp, align 4
   %mask = icmp eq <32 x i16> %x, %y
   %max = select <32 x i1> %mask, <32 x i16> %x, <32 x i16> %x1
   ret <32 x i16> %max
@@ -56,7 +56,7 @@ define <32 x i16> @test5(<32 x i16> %x, <32 x i16> %x1, <32 x i16>* %yp) nounwin
 ; CHECK: vmovdqu16
 ; CHECK: ret
 define <32 x i16> @test6(<32 x i16> %x, <32 x i16> %x1, <32 x i16>* %y.ptr) nounwind {
-  %y = load <32 x i16>* %y.ptr, align 4
+  %y = load <32 x i16>, <32 x i16>* %y.ptr, align 4
   %mask = icmp sgt <32 x i16> %x, %y
   %max = select <32 x i1> %mask, <32 x i16> %x, <32 x i16> %x1
   ret <32 x i16> %max
@@ -67,7 +67,7 @@ define <32 x i16> @test6(<32 x i16> %x, <32 x i16> %x1, <32 x i16>* %y.ptr) noun
 ; CHECK: vmovdqu16
 ; CHECK: ret
 define <32 x i16> @test7(<32 x i16> %x, <32 x i16> %x1, <32 x i16>* %y.ptr) nounwind {
-  %y = load <32 x i16>* %y.ptr, align 4
+  %y = load <32 x i16>, <32 x i16>* %y.ptr, align 4
   %mask = icmp sle <32 x i16> %x, %y
   %max = select <32 x i1> %mask, <32 x i16> %x, <32 x i16> %x1
   ret <32 x i16> %max
@@ -78,7 +78,7 @@ define <32 x i16> @test7(<32 x i16> %x, <32 x i16> %x1, <32 x i16>* %y.ptr) noun
 ; CHECK: vmovdqu16
 ; CHECK: ret
 define <32 x i16> @test8(<32 x i16> %x, <32 x i16> %x1, <32 x i16>* %y.ptr) nounwind {
-  %y = load <32 x i16>* %y.ptr, align 4
+  %y = load <32 x i16>, <32 x i16>* %y.ptr, align 4
   %mask = icmp ule <32 x i16> %x, %y
   %max = select <32 x i1> %mask, <32 x i16> %x, <32 x i16> %x1
   ret <32 x i16> %max
@@ -114,7 +114,7 @@ define <64 x i8> @test10(<64 x i8> %x, <64 x i8> %y, <64 x i8> %x1, <64 x i8> %y
 ; CHECK: ret
 define <64 x i8> @test11(<64 x i8> %x, <64 x i8>* %y.ptr, <64 x i8> %x1, <64 x i8> %y1) nounwind {
   %mask1 = icmp sgt <64 x i8> %x1, %y1
-  %y = load <64 x i8>* %y.ptr, align 4
+  %y = load <64 x i8>, <64 x i8>* %y.ptr, align 4
   %mask0 = icmp sgt <64 x i8> %x, %y
   %mask = select <64 x i1> %mask0, <64 x i1> %mask1, <64 x i1> zeroinitializer
   %max = select <64 x i1> %mask, <64 x i8> %x, <64 x i8> %x1
@@ -127,7 +127,7 @@ define <64 x i8> @test11(<64 x i8> %x, <64 x i8>* %y.ptr, <64 x i8> %x1, <64 x i
 ; CHECK: ret
 define <32 x i16> @test12(<32 x i16> %x, <32 x i16>* %y.ptr, <32 x i16> %x1, <32 x i16> %y1) nounwind {
   %mask1 = icmp sge <32 x i16> %x1, %y1
-  %y = load <32 x i16>* %y.ptr, align 4
+  %y = load <32 x i16>, <32 x i16>* %y.ptr, align 4
   %mask0 = icmp ule <32 x i16> %x, %y
   %mask = select <32 x i1> %mask0, <32 x i1> %mask1, <32 x i1> zeroinitializer
   %max = select <32 x i1> %mask, <32 x i16> %x, <32 x i16> %x1
diff --git a/test/CodeGen/X86/avx512bwvl-arith.ll b/test/CodeGen/X86/avx512bwvl-arith.ll
index 96f01409f5be..c0650e176101 100644
--- a/test/CodeGen/X86/avx512bwvl-arith.ll
+++ b/test/CodeGen/X86/avx512bwvl-arith.ll
@@ -14,7 +14,7 @@ define <32 x i8> @vpaddb256_test(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
 ; CHECK: vpaddb (%rdi), %ymm{{.*}}
 ; CHECK: ret
 define <32 x i8> @vpaddb256_fold_test(<32 x i8> %i, <32 x i8>* %j) nounwind {
-  %tmp = load <32 x i8>* %j, align 4
+  %tmp = load <32 x i8>, <32 x i8>* %j, align 4
   %x = add <32 x i8> %i, %tmp
   ret <32 x i8> %x
 }
@@ -31,7 +31,7 @@ define <16 x i16> @vpaddw256_test(<16 x i16> %i, <16 x i16> %j) nounwind readnon
 ; CHECK: vpaddw (%rdi), %ymm{{.*}}
 ; CHECK: ret
 define <16 x i16> @vpaddw256_fold_test(<16 x i16> %i, <16 x i16>* %j) nounwind {
-  %tmp = load <16 x i16>* %j, align 4
+  %tmp = load <16 x i16>, <16 x i16>* %j, align 4
   %x = add <16 x i16> %i, %tmp
   ret <16 x i16> %x
 }
@@ -61,7 +61,7 @@ define <16 x i16> @vpaddw256_maskz_test(<16 x i16> %i, <16 x i16> %j, <16 x i16>
 ; CHECK: ret
 define <16 x i16> @vpaddw256_mask_fold_test(<16 x i16> %i, <16 x i16>* %j.ptr, <16 x i16> %mask1) nounwind readnone {
   %mask = icmp ne <16 x i16> %mask1, zeroinitializer
-  %j = load <16 x i16>* %j.ptr
+  %j = load <16 x i16>, <16 x i16>* %j.ptr
   %x = add <16 x i16> %i, %j
   %r = select <16 x i1> %mask, <16 x i16> %x, <16 x i16> %i
   ret <16 x i16> %r
@@ -72,7 +72,7 @@ define <16 x i16> @vpaddw256_mask_fold_test(<16 x i16> %i, <16 x i16>* %j.ptr, <
 ; CHECK: ret
 define <16 x i16> @vpaddw256_maskz_fold_test(<16 x i16> %i, <16 x i16>* %j.ptr, <16 x i16> %mask1) nounwind readnone {
   %mask = icmp ne <16 x i16> %mask1, zeroinitializer
-  %j = load <16 x i16>* %j.ptr
+  %j = load <16 x i16>, <16 x i16>* %j.ptr
   %x = add <16 x i16> %i, %j
   %r = select <16 x i1> %mask, <16 x i16> %x, <16 x i16> zeroinitializer
   ret <16 x i16> %r
@@ -116,7 +116,7 @@ define <16 x i8> @vpaddb128_test(<16 x i8> %i, <16 x i8> %j) nounwind readnone {
 ; CHECK: vpaddb (%rdi), %xmm{{.*}}
 ; CHECK: ret
 define <16 x i8> @vpaddb128_fold_test(<16 x i8> %i, <16 x i8>* %j) nounwind {
-  %tmp = load <16 x i8>* %j, align 4
+  %tmp = load <16 x i8>, <16 x i8>* %j, align 4
   %x = add <16 x i8> %i, %tmp
   ret <16 x i8> %x
 }
@@ -133,7 +133,7 @@ define <8 x i16> @vpaddw128_test(<8 x i16> %i, <8 x i16> %j) nounwind readnone {
 ; CHECK: vpaddw (%rdi), %xmm{{.*}}
 ; CHECK: ret
 define <8 x i16> @vpaddw128_fold_test(<8 x i16> %i, <8 x i16>* %j) nounwind {
-  %tmp = load <8 x i16>* %j, align 4
+  %tmp = load <8 x i16>, <8 x i16>* %j, align 4
   %x = add <8 x i16> %i, %tmp
   ret <8 x i16> %x
 }
@@ -163,7 +163,7 @@ define <8 x i16> @vpaddw128_maskz_test(<8 x i16> %i, <8 x i16> %j, <8 x i16> %ma
 ; CHECK: ret
 define <8 x i16> @vpaddw128_mask_fold_test(<8 x i16> %i, <8 x i16>* %j.ptr, <8 x i16> %mask1) nounwind readnone {
   %mask = icmp ne <8 x i16> %mask1, zeroinitializer
-  %j = load <8 x i16>* %j.ptr
+  %j = load <8 x i16>, <8 x i16>* %j.ptr
   %x = add <8 x i16> %i, %j
   %r = select <8 x i1> %mask, <8 x i16> %x, <8 x i16> %i
   ret <8 x i16> %r
@@ -174,7 +174,7 @@ define <8 x i16> @vpaddw128_mask_fold_test(<8 x i16> %i, <8 x i16>* %j.ptr, <8 x
 ; CHECK: ret
 define <8 x i16> @vpaddw128_maskz_fold_test(<8 x i16> %i, <8 x i16>* %j.ptr, <8 x i16> %mask1) nounwind readnone {
   %mask = icmp ne <8 x i16> %mask1, zeroinitializer
-  %j = load <8 x i16>* %j.ptr
+  %j = load <8 x i16>, <8 x i16>* %j.ptr
   %x = add <8 x i16> %i, %j
   %r = select <8 x i1> %mask, <8 x i16> %x, <8 x i16> zeroinitializer
   ret <8 x i16> %r
diff --git a/test/CodeGen/X86/avx512bwvl-intrinsics.ll b/test/CodeGen/X86/avx512bwvl-intrinsics.ll
index 678f252dea42..f0efb2c947e9 100644
--- a/test/CodeGen/X86/avx512bwvl-intrinsics.ll
+++ b/test/CodeGen/X86/avx512bwvl-intrinsics.ll
@@ -830,7 +830,7 @@ define <2 x double> @test_mask_vfmsubadd128_pd(<2 x double> %a0, <2 x double> %a
 define <2 x double> @test_mask_vfmsubadd128rm_pd(<2 x double> %a0, <2 x double> %a1, <2 x double>* %ptr_a2, i8 %mask) {
   ; CHECK-LABEL: test_mask_vfmsubadd128rm_pd
   ; CHECK: vfmsubadd213pd (%rdi), %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x09,0xa7,0x07]
-  %a2 = load <2 x double>* %ptr_a2
+  %a2 = load <2 x double>, <2 x double>* %ptr_a2
   %res = call <2 x double> @llvm.x86.fma.mask.vfmsubadd.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind
   ret <2 x double> %res
 }
@@ -838,7 +838,7 @@ declare <8 x double> @llvm.x86.fma.mask.vfmsubadd.pd.512(<8 x double>, <8 x doub
 define <8 x double> @test_mask_vfmsubaddrm_pd(<8 x double> %a0, <8 x double> %a1, <8 x double>* %ptr_a2, i8 %mask) {
   ; CHECK-LABEL: test_mask_vfmsubaddrm_pd
   ; CHECK: vfmsubadd213pd  (%rdi), %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x49,0xa7,0x07]
-  %a2 = load <8 x double>* %ptr_a2, align 8
+  %a2 = load <8 x double>, <8 x double>* %ptr_a2, align 8
   %res = call <8 x double> @llvm.x86.fma.mask.vfmsubadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind
   ret <8 x double> %res
 }
@@ -860,7 +860,7 @@ define <4 x float> @test_mask_vfmadd128_ps_rz(<4 x float> %a0, <4 x float> %a1,
 define <4 x float> @test_mask_vfmadd128_ps_rmk(<4 x float> %a0, <4 x float> %a1, <4 x float>* %ptr_a2, i8 %mask) {
   ; CHECK-LABEL: test_mask_vfmadd128_ps_rmk
   ; CHECK: vfmadd213ps	(%rdi), %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x09,0xa8,0x07]
-  %a2 = load <4 x float>* %ptr_a2
+  %a2 = load <4 x float>, <4 x float>* %ptr_a2
   %res = call <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind
   ret <4 x float> %res
 }
@@ -868,7 +868,7 @@ define <4 x float> @test_mask_vfmadd128_ps_rmk(<4 x float> %a0, <4 x float> %a1,
 define <4 x float> @test_mask_vfmadd128_ps_rmka(<4 x float> %a0, <4 x float> %a1, <4 x float>* %ptr_a2, i8 %mask) {
   ; CHECK-LABEL: test_mask_vfmadd128_ps_rmka
   ; CHECK: vfmadd213ps     (%rdi), %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x09,0xa8,0x07]
-  %a2 = load <4 x float>* %ptr_a2, align 8
+  %a2 = load <4 x float>, <4 x float>* %ptr_a2, align 8
   %res = call <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind
   ret <4 x float> %res
 }
@@ -876,7 +876,7 @@ define <4 x float> @test_mask_vfmadd128_ps_rmka(<4 x float> %a0, <4 x float> %a1
 define <4 x float> @test_mask_vfmadd128_ps_rmkz(<4 x float> %a0, <4 x float> %a1, <4 x float>* %ptr_a2) {
   ; CHECK-LABEL: test_mask_vfmadd128_ps_rmkz
   ; CHECK: vfmadd213ps	(%rdi), %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x71,0xa8,0x07]
-  %a2 = load <4 x float>* %ptr_a2
+  %a2 = load <4 x float>, <4 x float>* %ptr_a2
   %res = call <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 -1) nounwind
   ret <4 x float> %res
 }
@@ -884,7 +884,7 @@ define <4 x float> @test_mask_vfmadd128_ps_rmkz(<4 x float> %a0, <4 x float> %a1
 define <4 x float> @test_mask_vfmadd128_ps_rmkza(<4 x float> %a0, <4 x float> %a1, <4 x float>* %ptr_a2) {
   ; CHECK-LABEL: test_mask_vfmadd128_ps_rmkza
   ; CHECK: vfmadd213ps	(%rdi), %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x71,0xa8,0x07]
-  %a2 = load <4 x float>* %ptr_a2, align 4
+  %a2 = load <4 x float>, <4 x float>* %ptr_a2, align 4
   %res = call <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 -1) nounwind
   ret <4 x float> %res
 }
@@ -892,7 +892,7 @@ define <4 x float> @test_mask_vfmadd128_ps_rmkza(<4 x float> %a0, <4 x float> %a
 define <4 x float> @test_mask_vfmadd128_ps_rmb(<4 x float> %a0, <4 x float> %a1, float* %ptr_a2, i8 %mask) {
   ; CHECK-LABEL: test_mask_vfmadd128_ps_rmb
   ; CHECK: vfmadd213ps	(%rdi){1to4}, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x19,0xa8,0x07]
-  %q = load float* %ptr_a2
+  %q = load float, float* %ptr_a2
   %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
   %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1
   %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2
@@ -904,7 +904,7 @@ define <4 x float> @test_mask_vfmadd128_ps_rmb(<4 x float> %a0, <4 x float> %a1,
 define <4 x float> @test_mask_vfmadd128_ps_rmba(<4 x float> %a0, <4 x float> %a1, float* %ptr_a2, i8 %mask) {
   ; CHECK-LABEL: test_mask_vfmadd128_ps_rmba
   ; CHECK: vfmadd213ps	(%rdi){1to4}, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x19,0xa8,0x07]
-  %q = load float* %ptr_a2, align 4
+  %q = load float, float* %ptr_a2, align 4
   %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
   %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1
   %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2
@@ -916,7 +916,7 @@ define <4 x float> @test_mask_vfmadd128_ps_rmba(<4 x float> %a0, <4 x float> %a1
 define <4 x float> @test_mask_vfmadd128_ps_rmbz(<4 x float> %a0, <4 x float> %a1, float* %ptr_a2) {
   ; CHECK-LABEL: test_mask_vfmadd128_ps_rmbz
   ; CHECK: vfmadd213ps	(%rdi){1to4}, %xmm1, %xmm0  ## encoding: [0x62,0xf2,0x75,0x18,0xa8,0x07]
-  %q = load float* %ptr_a2
+  %q = load float, float* %ptr_a2
   %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
   %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1
   %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2
@@ -928,7 +928,7 @@ define <4 x float> @test_mask_vfmadd128_ps_rmbz(<4 x float> %a0, <4 x float> %a1
 define <4 x float> @test_mask_vfmadd128_ps_rmbza(<4 x float> %a0, <4 x float> %a1, float* %ptr_a2) {
   ; CHECK-LABEL: test_mask_vfmadd128_ps_rmbza
   ; CHECK: vfmadd213ps	(%rdi){1to4}, %xmm1, %xmm0  ## encoding: [0x62,0xf2,0x75,0x18,0xa8,0x07]
-  %q = load float* %ptr_a2, align 4
+  %q = load float, float* %ptr_a2, align 4
   %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
   %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1
   %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2
@@ -954,7 +954,7 @@ define <2 x double> @test_mask_vfmadd128_pd_rz(<2 x double> %a0, <2 x double> %a
 define <2 x double> @test_mask_vfmadd128_pd_rmk(<2 x double> %a0, <2 x double> %a1, <2 x double>* %ptr_a2, i8 %mask) {
   ; CHECK-LABEL: test_mask_vfmadd128_pd_rmk
   ; CHECK: vfmadd213pd	(%rdi), %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x09,0xa8,0x07]
-  %a2 = load <2 x double>* %ptr_a2
+  %a2 = load <2 x double>, <2 x double>* %ptr_a2
   %res = call <2 x double> @llvm.x86.fma.mask.vfmadd.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind
   ret <2 x double> %res
 }
@@ -962,7 +962,7 @@ define <2 x double> @test_mask_vfmadd128_pd_rmk(<2 x double> %a0, <2 x double> %
 define <2 x double> @test_mask_vfmadd128_pd_rmkz(<2 x double> %a0, <2 x double> %a1, <2 x double>* %ptr_a2) {
   ; CHECK-LABEL: test_mask_vfmadd128_pd_rmkz
   ; CHECK: vfmadd213pd	(%rdi), %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0xf1,0xa8,0x07]
-  %a2 = load <2 x double>* %ptr_a2
+  %a2 = load <2 x double>, <2 x double>* %ptr_a2
   %res = call <2 x double> @llvm.x86.fma.mask.vfmadd.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 -1) nounwind
   ret <2 x double> %res
 }
@@ -984,7 +984,7 @@ define <4 x double> @test_mask_vfmadd256_pd_rz(<4 x double> %a0, <4 x double> %a
 define <4 x double> @test_mask_vfmadd256_pd_rmk(<4 x double> %a0, <4 x double> %a1, <4 x double>* %ptr_a2, i8 %mask) {
   ; CHECK-LABEL: test_mask_vfmadd256_pd_rmk
   ; CHECK: vfmadd213pd	(%rdi), %ymm1, %ymm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x29,0xa8,0x07]
-  %a2 = load <4 x double>* %ptr_a2
+  %a2 = load <4 x double>, <4 x double>* %ptr_a2
   %res = call <4 x double> @llvm.x86.fma.mask.vfmadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) nounwind
   ret <4 x double> %res
 }
@@ -992,7 +992,1679 @@ define <4 x double> @test_mask_vfmadd256_pd_rmk(<4 x double> %a0, <4 x double> %
 define <4 x double> @test_mask_vfmadd256_pd_rmkz(<4 x double> %a0, <4 x double> %a1, <4 x double>* %ptr_a2) {
   ; CHECK-LABEL: test_mask_vfmadd256_pd_rmkz
   ; CHECK: vfmadd213pd	(%rdi), %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0xf5,0xa8,0x07]
-  %a2 = load <4 x double>* %ptr_a2
+  %a2 = load <4 x double>, <4 x double>* %ptr_a2
   %res = call <4 x double> @llvm.x86.fma.mask.vfmadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 -1) nounwind
   ret <4 x double> %res
 }
+define <8 x i16> @test_mask_add_epi16_rr_128(<8 x i16> %a, <8 x i16> %b) {
+  ;CHECK-LABEL: test_mask_add_epi16_rr_128
+  ;CHECK: vpaddw %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf1,0x7d,0x08,0xfd,0xc1]
+  %res = call <8 x i16> @llvm.x86.avx512.mask.padd.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_add_epi16_rrk_128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi16_rrk_128
+  ;CHECK: vpaddw %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xfd,0xd1]
+  %res = call <8 x i16> @llvm.x86.avx512.mask.padd.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_add_epi16_rrkz_128(<8 x i16> %a, <8 x i16> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi16_rrkz_128
+  ;CHECK: vpaddw %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xfd,0xc1]
+  %res = call <8 x i16> @llvm.x86.avx512.mask.padd.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_add_epi16_rm_128(<8 x i16> %a, <8 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_add_epi16_rm_128
+  ;CHECK: vpaddw (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf1,0x7d,0x08,0xfd,0x07]
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.padd.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_add_epi16_rmk_128(<8 x i16> %a, <8 x i16>* %ptr_b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi16_rmk_128
+  ;CHECK: vpaddw (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xfd,0x0f]
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.padd.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_add_epi16_rmkz_128(<8 x i16> %a, <8 x i16>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi16_rmkz_128
+  ;CHECK: vpaddw (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xfd,0x07]
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.padd.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+declare <8 x i16> @llvm.x86.avx512.mask.padd.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)
+
+define <16 x i16> @test_mask_add_epi16_rr_256(<16 x i16> %a, <16 x i16> %b) {
+  ;CHECK-LABEL: test_mask_add_epi16_rr_256
+  ;CHECK: vpaddw %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf1,0x7d,0x28,0xfd,0xc1]
+  %res = call <16 x i16> @llvm.x86.avx512.mask.padd.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_add_epi16_rrk_256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi16_rrk_256
+  ;CHECK: vpaddw %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xfd,0xd1]
+  %res = call <16 x i16> @llvm.x86.avx512.mask.padd.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_add_epi16_rrkz_256(<16 x i16> %a, <16 x i16> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi16_rrkz_256
+  ;CHECK: vpaddw %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xfd,0xc1]
+  %res = call <16 x i16> @llvm.x86.avx512.mask.padd.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_add_epi16_rm_256(<16 x i16> %a, <16 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_add_epi16_rm_256
+  ;CHECK: vpaddw (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf1,0x7d,0x28,0xfd,0x07]
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.padd.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_add_epi16_rmk_256(<16 x i16> %a, <16 x i16>* %ptr_b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi16_rmk_256
+  ;CHECK: vpaddw (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xfd,0x0f]
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.padd.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_add_epi16_rmkz_256(<16 x i16> %a, <16 x i16>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi16_rmkz_256
+  ;CHECK: vpaddw (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xfd,0x07]
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.padd.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+declare <16 x i16> @llvm.x86.avx512.mask.padd.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)
+
+define <8 x i16> @test_mask_sub_epi16_rr_128(<8 x i16> %a, <8 x i16> %b) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rr_128
+  ;CHECK: vpsubw %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf1,0x7d,0x08,0xf9,0xc1]
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psub.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_sub_epi16_rrk_128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rrk_128
+  ;CHECK: vpsubw %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xf9,0xd1]
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psub.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_sub_epi16_rrkz_128(<8 x i16> %a, <8 x i16> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rrkz_128
+  ;CHECK: vpsubw %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xf9,0xc1]
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psub.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_sub_epi16_rm_128(<8 x i16> %a, <8 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rm_128
+  ;CHECK: vpsubw (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf1,0x7d,0x08,0xf9,0x07]
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psub.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_sub_epi16_rmk_128(<8 x i16> %a, <8 x i16>* %ptr_b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rmk_128
+  ;CHECK: vpsubw (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xf9,0x0f]
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psub.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_sub_epi16_rmkz_128(<8 x i16> %a, <8 x i16>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rmkz_128
+  ;CHECK: vpsubw (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xf9,0x07]
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psub.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+declare <8 x i16> @llvm.x86.avx512.mask.psub.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)
+
+define <16 x i16> @test_mask_sub_epi16_rr_256(<16 x i16> %a, <16 x i16> %b) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rr_256
+  ;CHECK: vpsubw %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf1,0x7d,0x28,0xf9,0xc1]
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psub.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_sub_epi16_rrk_256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rrk_256
+  ;CHECK: vpsubw %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xf9,0xd1]
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psub.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_sub_epi16_rrkz_256(<16 x i16> %a, <16 x i16> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rrkz_256
+  ;CHECK: vpsubw %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xf9,0xc1]
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psub.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_sub_epi16_rm_256(<16 x i16> %a, <16 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rm_256
+  ;CHECK: vpsubw (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf1,0x7d,0x28,0xf9,0x07]
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psub.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_sub_epi16_rmk_256(<16 x i16> %a, <16 x i16>* %ptr_b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rmk_256
+  ;CHECK: vpsubw (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xf9,0x0f]
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psub.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_sub_epi16_rmkz_256(<16 x i16> %a, <16 x i16>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rmkz_256
+  ;CHECK: vpsubw (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xf9,0x07]
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psub.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+declare <16 x i16> @llvm.x86.avx512.mask.psub.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)
+
+define <32 x i16> @test_mask_add_epi16_rr_512(<32 x i16> %a, <32 x i16> %b) {
+  ;CHECK-LABEL: test_mask_add_epi16_rr_512
+  ;CHECK: vpaddw %zmm1, %zmm0, %zmm0     ## encoding: [0x62,0xf1,0x7d,0x48,0xfd,0xc1]
+  %res = call <32 x i16> @llvm.x86.avx512.mask.padd.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_add_epi16_rrk_512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi16_rrk_512
+  ;CHECK: vpaddw %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xfd,0xd1]
+  %res = call <32 x i16> @llvm.x86.avx512.mask.padd.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_add_epi16_rrkz_512(<32 x i16> %a, <32 x i16> %b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi16_rrkz_512
+  ;CHECK: vpaddw %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0xfd,0xc1]
+  %res = call <32 x i16> @llvm.x86.avx512.mask.padd.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_add_epi16_rm_512(<32 x i16> %a, <32 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_add_epi16_rm_512
+  ;CHECK: vpaddw (%rdi), %zmm0, %zmm0    ## encoding: [0x62,0xf1,0x7d,0x48,0xfd,0x07]
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.padd.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_add_epi16_rmk_512(<32 x i16> %a, <32 x i16>* %ptr_b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi16_rmk_512
+  ;CHECK: vpaddw (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xfd,0x0f]
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.padd.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_add_epi16_rmkz_512(<32 x i16> %a, <32 x i16>* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi16_rmkz_512
+  ;CHECK: vpaddw (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0xfd,0x07]
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.padd.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+declare <32 x i16> @llvm.x86.avx512.mask.padd.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)
+
+define <32 x i16> @test_mask_sub_epi16_rr_512(<32 x i16> %a, <32 x i16> %b) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rr_512
+  ;CHECK: vpsubw %zmm1, %zmm0, %zmm0     ## encoding: [0x62,0xf1,0x7d,0x48,0xf9,0xc1]
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psub.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_sub_epi16_rrk_512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rrk_512
+  ;CHECK: vpsubw %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xf9,0xd1]
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psub.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_sub_epi16_rrkz_512(<32 x i16> %a, <32 x i16> %b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rrkz_512
+  ;CHECK: vpsubw %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0xf9,0xc1]
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psub.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_sub_epi16_rm_512(<32 x i16> %a, <32 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rm_512
+  ;CHECK: vpsubw (%rdi), %zmm0, %zmm0    ## encoding: [0x62,0xf1,0x7d,0x48,0xf9,0x07]
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psub.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_sub_epi16_rmk_512(<32 x i16> %a, <32 x i16>* %ptr_b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rmk_512
+  ;CHECK: vpsubw (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xf9,0x0f]
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psub.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_sub_epi16_rmkz_512(<32 x i16> %a, <32 x i16>* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi16_rmkz_512
+  ;CHECK: vpsubw (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0xf9,0x07]
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.psub.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+declare <32 x i16> @llvm.x86.avx512.mask.psub.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)
+
+define <32 x i16> @test_mask_mullo_epi16_rr_512(<32 x i16> %a, <32 x i16> %b) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rr_512
+  ;CHECK: vpmullw %zmm1, %zmm0, %zmm0     ## encoding: [0x62,0xf1,0x7d,0x48,0xd5,0xc1]
+  %res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_mullo_epi16_rrk_512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rrk_512
+  ;CHECK: vpmullw %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xd5,0xd1]
+  %res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_mullo_epi16_rrkz_512(<32 x i16> %a, <32 x i16> %b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rrkz_512
+  ;CHECK: vpmullw %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0xd5,0xc1]
+  %res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_mullo_epi16_rm_512(<32 x i16> %a, <32 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rm_512
+  ;CHECK: vpmullw (%rdi), %zmm0, %zmm0    ## encoding: [0x62,0xf1,0x7d,0x48,0xd5,0x07]
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 -1)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_mullo_epi16_rmk_512(<32 x i16> %a, <32 x i16>* %ptr_b, <32 x i16> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rmk_512
+  ;CHECK: vpmullw (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xd5,0x0f]
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> %passThru, i32 %mask)
+  ret <32 x i16> %res
+}
+
+define <32 x i16> @test_mask_mullo_epi16_rmkz_512(<32 x i16> %a, <32 x i16>* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rmkz_512
+  ;CHECK: vpmullw (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0xd5,0x07]
+  %b = load <32 x i16>, <32 x i16>* %ptr_b
+  %res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> zeroinitializer, i32 %mask)
+  ret <32 x i16> %res
+}
+
+declare <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)
+
+define <8 x i16> @test_mask_mullo_epi16_rr_128(<8 x i16> %a, <8 x i16> %b) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rr_128
+  ;CHECK: vpmullw %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf1,0x7d,0x08,0xd5,0xc1]
+  %res = call <8 x i16> @llvm.x86.avx512.mask.pmull.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_mullo_epi16_rrk_128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rrk_128
+  ;CHECK: vpmullw %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xd5,0xd1]
+  %res = call <8 x i16> @llvm.x86.avx512.mask.pmull.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_mullo_epi16_rrkz_128(<8 x i16> %a, <8 x i16> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rrkz_128
+  ;CHECK: vpmullw %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xd5,0xc1]
+  %res = call <8 x i16> @llvm.x86.avx512.mask.pmull.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_mullo_epi16_rm_128(<8 x i16> %a, <8 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rm_128
+  ;CHECK: vpmullw (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf1,0x7d,0x08,0xd5,0x07]
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.pmull.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_mullo_epi16_rmk_128(<8 x i16> %a, <8 x i16>* %ptr_b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rmk_128
+  ;CHECK: vpmullw (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xd5,0x0f]
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.pmull.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_mullo_epi16_rmkz_128(<8 x i16> %a, <8 x i16>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rmkz_128
+  ;CHECK: vpmullw (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xd5,0x07]
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.pmull.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+declare <8 x i16> @llvm.x86.avx512.mask.pmull.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)
+
+define <16 x i16> @test_mask_mullo_epi16_rr_256(<16 x i16> %a, <16 x i16> %b) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rr_256
+  ;CHECK: vpmullw %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf1,0x7d,0x28,0xd5,0xc1]
+  %res = call <16 x i16> @llvm.x86.avx512.mask.pmull.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_mullo_epi16_rrk_256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rrk_256
+  ;CHECK: vpmullw %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xd5,0xd1]
+  %res = call <16 x i16> @llvm.x86.avx512.mask.pmull.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_mullo_epi16_rrkz_256(<16 x i16> %a, <16 x i16> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rrkz_256
+  ;CHECK: vpmullw %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xd5,0xc1]
+  %res = call <16 x i16> @llvm.x86.avx512.mask.pmull.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_mullo_epi16_rm_256(<16 x i16> %a, <16 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rm_256
+  ;CHECK: vpmullw (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf1,0x7d,0x28,0xd5,0x07]
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.pmull.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_mullo_epi16_rmk_256(<16 x i16> %a, <16 x i16>* %ptr_b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rmk_256
+  ;CHECK: vpmullw (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xd5,0x0f]
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.pmull.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_mullo_epi16_rmkz_256(<16 x i16> %a, <16 x i16>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi16_rmkz_256
+  ;CHECK: vpmullw (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xd5,0x07]
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.pmull.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+declare <16 x i16> @llvm.x86.avx512.mask.pmull.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)
+
+
+define <8 x i16> @test_mask_packs_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rr_128
+  ;CHECK: vpackssdw       %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x6b,0xc1]
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packssdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packs_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rrk_128
+  ;CHECK: vpackssdw       %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0x6b,0xd1]
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packssdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packs_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rrkz_128
+  ;CHECK: vpackssdw       %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0x6b,0xc1]
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packssdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packs_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rm_128
+  ;CHECK: vpackssdw       (%rdi), %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x6b,0x07]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packssdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packs_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rmk_128
+  ;CHECK: vpackssdw       (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0x6b,0x0f]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packssdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packs_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rmkz_128
+  ;CHECK: vpackssdw       (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0x6b,0x07]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packssdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packs_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rmb_128
+  ;CHECK: vpackssdw       (%rdi){1to4}, %xmm0, %xmm0  ## encoding: [0x62,0xf1,0x7d,0x18,0x6b,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packssdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packs_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rmbk_128
+  ;CHECK: vpackssdw       (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0x6b,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packssdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packs_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rmbkz_128
+  ;CHECK: vpackssdw       (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0x6b,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packssdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+declare <8 x i16> @llvm.x86.avx512.mask.packssdw.128(<4 x i32>, <4 x i32>, <8 x i16>, i8)
+
+define <16 x i16> @test_mask_packs_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rr_256
+  ;CHECK: vpackssdw       %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x6b,0xc1]
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packssdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packs_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rrk_256
+  ;CHECK: vpackssdw       %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0x6b,0xd1]
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packssdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packs_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rrkz_256
+  ;CHECK: vpackssdw       %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0x6b,0xc1]
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packssdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packs_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rm_256
+  ;CHECK: vpackssdw       (%rdi), %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x6b,0x07]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packssdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packs_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rmk_256
+  ;CHECK: vpackssdw       (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0x6b,0x0f]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packssdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packs_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rmkz_256
+  ;CHECK: vpackssdw       (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0x6b,0x07]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packssdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packs_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rmb_256
+  ;CHECK: vpackssdw       (%rdi){1to8}, %ymm0, %ymm0  ## encoding: [0x62,0xf1,0x7d,0x38,0x6b,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packssdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packs_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rmbk_256
+  ;CHECK: vpackssdw       (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0x6b,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packssdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packs_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi32_rmbkz_256
+  ;CHECK: vpackssdw       (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0x6b,0x07]  
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packssdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+declare <16 x i16> @llvm.x86.avx512.mask.packssdw.256(<8 x i32>, <8 x i32>, <16 x i16>, i16)
+
+define <16 x i8> @test_mask_packs_epi16_rr_128(<8 x i16> %a, <8 x i16> %b) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rr_128
+  ;CHECK: vpacksswb       %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x63,0xc1]
+  %res = call <16 x i8> @llvm.x86.avx512.mask.packsswb.128(<8 x i16> %a, <8 x i16> %b, <16 x i8> zeroinitializer, i16 -1)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_packs_epi16_rrk_128(<8 x i16> %a, <8 x i16> %b, <16 x i8> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rrk_128
+  ;CHECK: vpacksswb       %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x09,0x63,0xd1]
+  %res = call <16 x i8> @llvm.x86.avx512.mask.packsswb.128(<8 x i16> %a, <8 x i16> %b, <16 x i8> %passThru, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_packs_epi16_rrkz_128(<8 x i16> %a, <8 x i16> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rrkz_128
+  ;CHECK: vpacksswb       %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x89,0x63,0xc1]
+  %res = call <16 x i8> @llvm.x86.avx512.mask.packsswb.128(<8 x i16> %a, <8 x i16> %b, <16 x i8> zeroinitializer, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_packs_epi16_rm_128(<8 x i16> %a, <8 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rm_128
+  ;CHECK: vpacksswb       (%rdi), %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x63,0x07]
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.packsswb.128(<8 x i16> %a, <8 x i16> %b, <16 x i8> zeroinitializer, i16 -1)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_packs_epi16_rmk_128(<8 x i16> %a, <8 x i16>* %ptr_b, <16 x i8> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rmk_128
+  ;CHECK: vpacksswb       (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x09,0x63,0x0f]
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.packsswb.128(<8 x i16> %a, <8 x i16> %b, <16 x i8> %passThru, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_packs_epi16_rmkz_128(<8 x i16> %a, <8 x i16>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rmkz_128
+  ;CHECK: vpacksswb       (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x89,0x63,0x07]
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.packsswb.128(<8 x i16> %a, <8 x i16> %b, <16 x i8> zeroinitializer, i16 %mask)
+  ret <16 x i8> %res
+}
+
+declare <16 x i8> @llvm.x86.avx512.mask.packsswb.128(<8 x i16>, <8 x i16>, <16 x i8>, i16)
+
+define <32 x i8> @test_mask_packs_epi16_rr_256(<16 x i16> %a, <16 x i16> %b) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rr_256
+  ;CHECK: vpacksswb       %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x63,0xc1]
+  %res = call <32 x i8> @llvm.x86.avx512.mask.packsswb.256(<16 x i16> %a, <16 x i16> %b, <32 x i8> zeroinitializer, i32 -1)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_packs_epi16_rrk_256(<16 x i16> %a, <16 x i16> %b, <32 x i8> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rrk_256
+  ;CHECK: vpacksswb       %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0x63,0xd1]
+  %res = call <32 x i8> @llvm.x86.avx512.mask.packsswb.256(<16 x i16> %a, <16 x i16> %b, <32 x i8> %passThru, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_packs_epi16_rrkz_256(<16 x i16> %a, <16 x i16> %b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rrkz_256
+  ;CHECK: vpacksswb       %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0x63,0xc1]
+  %res = call <32 x i8> @llvm.x86.avx512.mask.packsswb.256(<16 x i16> %a, <16 x i16> %b, <32 x i8> zeroinitializer, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_packs_epi16_rm_256(<16 x i16> %a, <16 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rm_256
+  ;CHECK: vpacksswb       (%rdi), %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x63,0x07]
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.packsswb.256(<16 x i16> %a, <16 x i16> %b, <32 x i8> zeroinitializer, i32 -1)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_packs_epi16_rmk_256(<16 x i16> %a, <16 x i16>* %ptr_b, <32 x i8> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rmk_256
+  ;CHECK: vpacksswb       (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0x63,0x0f]
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.packsswb.256(<16 x i16> %a, <16 x i16> %b, <32 x i8> %passThru, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_packs_epi16_rmkz_256(<16 x i16> %a, <16 x i16>* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packs_epi16_rmkz_256
+  ;CHECK: vpacksswb       (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0x63,0x07]
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.packsswb.256(<16 x i16> %a, <16 x i16> %b, <32 x i8> zeroinitializer, i32 %mask)
+  ret <32 x i8> %res
+}
+
+declare <32 x i8> @llvm.x86.avx512.mask.packsswb.256(<16 x i16>, <16 x i16>, <32 x i8>, i32)
+
+
+define <8 x i16> @test_mask_packus_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rr_128
+  ;CHECK: vpackusdw       %xmm1, %xmm0, %xmm0 
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packusdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packus_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rrk_128
+  ;CHECK: vpackusdw       %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packusdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packus_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rrkz_128
+  ;CHECK: vpackusdw       %xmm1, %xmm0, %xmm0 {%k1} {z} 
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packusdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packus_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rm_128
+  ;CHECK: vpackusdw       (%rdi), %xmm0, %xmm0 
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packusdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packus_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rmk_128
+  ;CHECK: vpackusdw       (%rdi), %xmm0, %xmm1 {%k1} 
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packusdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packus_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rmkz_128
+  ;CHECK: vpackusdw       (%rdi), %xmm0, %xmm0 {%k1} {z} 
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packusdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packus_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rmb_128
+  ;CHECK: vpackusdw       (%rdi){1to4}, %xmm0, %xmm0  
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packusdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packus_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rmbk_128
+  ;CHECK: vpackusdw       (%rdi){1to4}, %xmm0, %xmm1 {%k1} 
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packusdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_packus_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rmbkz_128
+  ;CHECK: vpackusdw       (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} 
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <8 x i16> @llvm.x86.avx512.mask.packusdw.128(<4 x i32> %a, <4 x i32> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+declare <8 x i16> @llvm.x86.avx512.mask.packusdw.128(<4 x i32>, <4 x i32>, <8 x i16>, i8)
+
+define <16 x i16> @test_mask_packus_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rr_256
+  ;CHECK: vpackusdw       %ymm1, %ymm0, %ymm0 
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packusdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packus_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rrk_256
+  ;CHECK: vpackusdw       %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packusdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packus_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rrkz_256
+  ;CHECK: vpackusdw       %ymm1, %ymm0, %ymm0 {%k1} {z} 
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packusdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packus_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rm_256
+  ;CHECK: vpackusdw       (%rdi), %ymm0, %ymm0 
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packusdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packus_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rmk_256
+  ;CHECK: vpackusdw       (%rdi), %ymm0, %ymm1 {%k1} 
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packusdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packus_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rmkz_256
+  ;CHECK: vpackusdw       (%rdi), %ymm0, %ymm0 {%k1} {z} 
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packusdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packus_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rmb_256
+  ;CHECK: vpackusdw       (%rdi){1to8}, %ymm0, %ymm0  
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packusdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packus_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rmbk_256
+  ;CHECK: vpackusdw       (%rdi){1to8}, %ymm0, %ymm1 {%k1} 
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packusdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_packus_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi32_rmbkz_256
+  ;CHECK: vpackusdw       (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} 
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <16 x i16> @llvm.x86.avx512.mask.packusdw.256(<8 x i32> %a, <8 x i32> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+declare <16 x i16> @llvm.x86.avx512.mask.packusdw.256(<8 x i32>, <8 x i32>, <16 x i16>, i16)
+
+define <16 x i8> @test_mask_packus_epi16_rr_128(<8 x i16> %a, <8 x i16> %b) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rr_128
+  ;CHECK: vpackuswb       %xmm1, %xmm0, %xmm0 
+  %res = call <16 x i8> @llvm.x86.avx512.mask.packuswb.128(<8 x i16> %a, <8 x i16> %b, <16 x i8> zeroinitializer, i16 -1)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_packus_epi16_rrk_128(<8 x i16> %a, <8 x i16> %b, <16 x i8> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rrk_128
+  ;CHECK: vpackuswb       %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <16 x i8> @llvm.x86.avx512.mask.packuswb.128(<8 x i16> %a, <8 x i16> %b, <16 x i8> %passThru, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_packus_epi16_rrkz_128(<8 x i16> %a, <8 x i16> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rrkz_128
+  ;CHECK: vpackuswb       %xmm1, %xmm0, %xmm0 {%k1} {z} 
+  %res = call <16 x i8> @llvm.x86.avx512.mask.packuswb.128(<8 x i16> %a, <8 x i16> %b, <16 x i8> zeroinitializer, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_packus_epi16_rm_128(<8 x i16> %a, <8 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rm_128
+  ;CHECK: vpackuswb       (%rdi), %xmm0, %xmm0 
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.packuswb.128(<8 x i16> %a, <8 x i16> %b, <16 x i8> zeroinitializer, i16 -1)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_packus_epi16_rmk_128(<8 x i16> %a, <8 x i16>* %ptr_b, <16 x i8> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rmk_128
+  ;CHECK: vpackuswb       (%rdi), %xmm0, %xmm1 {%k1} 
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.packuswb.128(<8 x i16> %a, <8 x i16> %b, <16 x i8> %passThru, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_packus_epi16_rmkz_128(<8 x i16> %a, <8 x i16>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rmkz_128
+  ;CHECK: vpackuswb       (%rdi), %xmm0, %xmm0 {%k1} {z} 
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.packuswb.128(<8 x i16> %a, <8 x i16> %b, <16 x i8> zeroinitializer, i16 %mask)
+  ret <16 x i8> %res
+}
+
+declare <16 x i8> @llvm.x86.avx512.mask.packuswb.128(<8 x i16>, <8 x i16>, <16 x i8>, i16)
+
+define <32 x i8> @test_mask_packus_epi16_rr_256(<16 x i16> %a, <16 x i16> %b) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rr_256
+  ;CHECK: vpackuswb       %ymm1, %ymm0, %ymm0 
+  %res = call <32 x i8> @llvm.x86.avx512.mask.packuswb.256(<16 x i16> %a, <16 x i16> %b, <32 x i8> zeroinitializer, i32 -1)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_packus_epi16_rrk_256(<16 x i16> %a, <16 x i16> %b, <32 x i8> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rrk_256
+  ;CHECK: vpackuswb       %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <32 x i8> @llvm.x86.avx512.mask.packuswb.256(<16 x i16> %a, <16 x i16> %b, <32 x i8> %passThru, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_packus_epi16_rrkz_256(<16 x i16> %a, <16 x i16> %b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rrkz_256
+  ;CHECK: vpackuswb       %ymm1, %ymm0, %ymm0 {%k1} {z} 
+  %res = call <32 x i8> @llvm.x86.avx512.mask.packuswb.256(<16 x i16> %a, <16 x i16> %b, <32 x i8> zeroinitializer, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_packus_epi16_rm_256(<16 x i16> %a, <16 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rm_256
+  ;CHECK: vpackuswb       (%rdi), %ymm0, %ymm0 
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.packuswb.256(<16 x i16> %a, <16 x i16> %b, <32 x i8> zeroinitializer, i32 -1)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_packus_epi16_rmk_256(<16 x i16> %a, <16 x i16>* %ptr_b, <32 x i8> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rmk_256
+  ;CHECK: vpackuswb       (%rdi), %ymm0, %ymm1 {%k1} 
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.packuswb.256(<16 x i16> %a, <16 x i16> %b, <32 x i8> %passThru, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_packus_epi16_rmkz_256(<16 x i16> %a, <16 x i16>* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_packus_epi16_rmkz_256
+  ;CHECK: vpackuswb       (%rdi), %ymm0, %ymm0 {%k1} {z} 
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.packuswb.256(<16 x i16> %a, <16 x i16> %b, <32 x i8> zeroinitializer, i32 %mask)
+  ret <32 x i8> %res
+}
+
+declare <32 x i8> @llvm.x86.avx512.mask.packuswb.256(<16 x i16>, <16 x i16>, <32 x i8>, i32)
+
+define <8 x i16> @test_mask_adds_epi16_rr_128(<8 x i16> %a, <8 x i16> %b) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rr_128
+  ;CHECK: vpaddsw %xmm1, %xmm0, %xmm0 
+  %res = call <8 x i16> @llvm.x86.avx512.mask.padds.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_adds_epi16_rrk_128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rrk_128
+  ;CHECK: vpaddsw %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <8 x i16> @llvm.x86.avx512.mask.padds.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_adds_epi16_rrkz_128(<8 x i16> %a, <8 x i16> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rrkz_128
+  ;CHECK: vpaddsw %xmm1, %xmm0, %xmm0 {%k1} {z} 
+  %res = call <8 x i16> @llvm.x86.avx512.mask.padds.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_adds_epi16_rm_128(<8 x i16> %a, <8 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rm_128
+  ;CHECK: vpaddsw (%rdi), %xmm0, %xmm0 
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.padds.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_adds_epi16_rmk_128(<8 x i16> %a, <8 x i16>* %ptr_b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rmk_128
+  ;CHECK: vpaddsw (%rdi), %xmm0, %xmm1 {%k1} 
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.padds.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_adds_epi16_rmkz_128(<8 x i16> %a, <8 x i16>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rmkz_128
+  ;CHECK: vpaddsw (%rdi), %xmm0, %xmm0 {%k1} {z} 
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.padds.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+declare <8 x i16> @llvm.x86.avx512.mask.padds.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)
+
+define <16 x i16> @test_mask_adds_epi16_rr_256(<16 x i16> %a, <16 x i16> %b) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rr_256
+  ;CHECK: vpaddsw %ymm1, %ymm0, %ymm0 
+  %res = call <16 x i16> @llvm.x86.avx512.mask.padds.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_adds_epi16_rrk_256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rrk_256
+  ;CHECK: vpaddsw %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <16 x i16> @llvm.x86.avx512.mask.padds.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_adds_epi16_rrkz_256(<16 x i16> %a, <16 x i16> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rrkz_256
+  ;CHECK: vpaddsw %ymm1, %ymm0, %ymm0 {%k1} {z} 
+  %res = call <16 x i16> @llvm.x86.avx512.mask.padds.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_adds_epi16_rm_256(<16 x i16> %a, <16 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rm_256
+  ;CHECK: vpaddsw (%rdi), %ymm0, %ymm0    
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.padds.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_adds_epi16_rmk_256(<16 x i16> %a, <16 x i16>* %ptr_b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rmk_256
+  ;CHECK: vpaddsw (%rdi), %ymm0, %ymm1 {%k1} 
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.padds.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_adds_epi16_rmkz_256(<16 x i16> %a, <16 x i16>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi16_rmkz_256
+  ;CHECK: vpaddsw (%rdi), %ymm0, %ymm0 {%k1} {z} 
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.padds.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+declare <16 x i16> @llvm.x86.avx512.mask.padds.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)
+
+define <8 x i16> @test_mask_subs_epi16_rr_128(<8 x i16> %a, <8 x i16> %b) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rr_128
+  ;CHECK: vpsubsw %xmm1, %xmm0, %xmm0     
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psubs.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_subs_epi16_rrk_128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rrk_128
+  ;CHECK: vpsubsw %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psubs.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_subs_epi16_rrkz_128(<8 x i16> %a, <8 x i16> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rrkz_128
+  ;CHECK: vpsubsw %xmm1, %xmm0, %xmm0 {%k1} {z} 
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psubs.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_subs_epi16_rm_128(<8 x i16> %a, <8 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rm_128
+  ;CHECK: vpsubsw (%rdi), %xmm0, %xmm0
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psubs.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_subs_epi16_rmk_128(<8 x i16> %a, <8 x i16>* %ptr_b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rmk_128
+  ;CHECK: vpsubsw (%rdi), %xmm0, %xmm1 {%k1} 
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psubs.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_subs_epi16_rmkz_128(<8 x i16> %a, <8 x i16>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rmkz_128
+  ;CHECK: vpsubsw (%rdi), %xmm0, %xmm0 {%k1} {z} 
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psubs.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+declare <8 x i16> @llvm.x86.avx512.mask.psubs.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)
+
+define <16 x i16> @test_mask_subs_epi16_rr_256(<16 x i16> %a, <16 x i16> %b) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rr_256
+  ;CHECK: vpsubsw %ymm1, %ymm0, %ymm0     
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psubs.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_subs_epi16_rrk_256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rrk_256
+  ;CHECK: vpsubsw %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psubs.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_subs_epi16_rrkz_256(<16 x i16> %a, <16 x i16> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rrkz_256
+  ;CHECK: vpsubsw %ymm1, %ymm0, %ymm0 {%k1} {z} 
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psubs.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_subs_epi16_rm_256(<16 x i16> %a, <16 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rm_256
+  ;CHECK: vpsubsw (%rdi), %ymm0, %ymm0    
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psubs.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_subs_epi16_rmk_256(<16 x i16> %a, <16 x i16>* %ptr_b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rmk_256
+  ;CHECK: vpsubsw (%rdi), %ymm0, %ymm1 {%k1} 
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psubs.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_subs_epi16_rmkz_256(<16 x i16> %a, <16 x i16>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi16_rmkz_256
+  ;CHECK: vpsubsw (%rdi), %ymm0, %ymm0 {%k1} {z} 
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psubs.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+declare <16 x i16> @llvm.x86.avx512.mask.psubs.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)
+
+define <8 x i16> @test_mask_adds_epu16_rr_128(<8 x i16> %a, <8 x i16> %b) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rr_128
+  ;CHECK: vpaddusw %xmm1, %xmm0, %xmm0 
+  %res = call <8 x i16> @llvm.x86.avx512.mask.paddus.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_adds_epu16_rrk_128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rrk_128
+  ;CHECK: vpaddusw %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <8 x i16> @llvm.x86.avx512.mask.paddus.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_adds_epu16_rrkz_128(<8 x i16> %a, <8 x i16> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rrkz_128
+  ;CHECK: vpaddusw %xmm1, %xmm0, %xmm0 {%k1} {z} 
+  %res = call <8 x i16> @llvm.x86.avx512.mask.paddus.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_adds_epu16_rm_128(<8 x i16> %a, <8 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rm_128
+  ;CHECK: vpaddusw (%rdi), %xmm0, %xmm0 
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.paddus.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_adds_epu16_rmk_128(<8 x i16> %a, <8 x i16>* %ptr_b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rmk_128
+  ;CHECK: vpaddusw (%rdi), %xmm0, %xmm1 {%k1} 
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.paddus.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_adds_epu16_rmkz_128(<8 x i16> %a, <8 x i16>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rmkz_128
+  ;CHECK: vpaddusw (%rdi), %xmm0, %xmm0 {%k1} {z} 
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.paddus.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+declare <8 x i16> @llvm.x86.avx512.mask.paddus.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)
+
+define <16 x i16> @test_mask_adds_epu16_rr_256(<16 x i16> %a, <16 x i16> %b) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rr_256
+  ;CHECK: vpaddusw %ymm1, %ymm0, %ymm0 
+  %res = call <16 x i16> @llvm.x86.avx512.mask.paddus.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_adds_epu16_rrk_256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rrk_256
+  ;CHECK: vpaddusw %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <16 x i16> @llvm.x86.avx512.mask.paddus.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_adds_epu16_rrkz_256(<16 x i16> %a, <16 x i16> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rrkz_256
+  ;CHECK: vpaddusw %ymm1, %ymm0, %ymm0 {%k1} {z} 
+  %res = call <16 x i16> @llvm.x86.avx512.mask.paddus.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_adds_epu16_rm_256(<16 x i16> %a, <16 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rm_256
+  ;CHECK: vpaddusw (%rdi), %ymm0, %ymm0    
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.paddus.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_adds_epu16_rmk_256(<16 x i16> %a, <16 x i16>* %ptr_b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rmk_256
+  ;CHECK: vpaddusw (%rdi), %ymm0, %ymm1 {%k1} 
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.paddus.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_adds_epu16_rmkz_256(<16 x i16> %a, <16 x i16>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu16_rmkz_256
+  ;CHECK: vpaddusw (%rdi), %ymm0, %ymm0 {%k1} {z} 
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.paddus.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+declare <16 x i16> @llvm.x86.avx512.mask.paddus.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)
+
+define <8 x i16> @test_mask_subs_epu16_rr_128(<8 x i16> %a, <8 x i16> %b) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rr_128
+  ;CHECK: vpsubusw %xmm1, %xmm0, %xmm0     
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psubus.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_subs_epu16_rrk_128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rrk_128
+  ;CHECK: vpsubusw %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psubus.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_subs_epu16_rrkz_128(<8 x i16> %a, <8 x i16> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rrkz_128
+  ;CHECK: vpsubusw %xmm1, %xmm0, %xmm0 {%k1} {z} 
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psubus.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_subs_epu16_rm_128(<8 x i16> %a, <8 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rm_128
+  ;CHECK: vpsubusw (%rdi), %xmm0, %xmm0
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psubus.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 -1)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_subs_epu16_rmk_128(<8 x i16> %a, <8 x i16>* %ptr_b, <8 x i16> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rmk_128
+  ;CHECK: vpsubusw (%rdi), %xmm0, %xmm1 {%k1} 
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psubus.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %passThru, i8 %mask)
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @test_mask_subs_epu16_rmkz_128(<8 x i16> %a, <8 x i16>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rmkz_128
+  ;CHECK: vpsubusw (%rdi), %xmm0, %xmm0 {%k1} {z} 
+  %b = load <8 x i16>, <8 x i16>* %ptr_b
+  %res = call <8 x i16> @llvm.x86.avx512.mask.psubus.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zeroinitializer, i8 %mask)
+  ret <8 x i16> %res
+}
+
+declare <8 x i16> @llvm.x86.avx512.mask.psubus.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)
+
+define <16 x i16> @test_mask_subs_epu16_rr_256(<16 x i16> %a, <16 x i16> %b) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rr_256
+  ;CHECK: vpsubusw %ymm1, %ymm0, %ymm0     
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psubus.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_subs_epu16_rrk_256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rrk_256
+  ;CHECK: vpsubusw %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psubus.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_subs_epu16_rrkz_256(<16 x i16> %a, <16 x i16> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rrkz_256
+  ;CHECK: vpsubusw %ymm1, %ymm0, %ymm0 {%k1} {z} 
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psubus.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_subs_epu16_rm_256(<16 x i16> %a, <16 x i16>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rm_256
+  ;CHECK: vpsubusw (%rdi), %ymm0, %ymm0    
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psubus.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 -1)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_subs_epu16_rmk_256(<16 x i16> %a, <16 x i16>* %ptr_b, <16 x i16> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rmk_256
+  ;CHECK: vpsubusw (%rdi), %ymm0, %ymm1 {%k1} 
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psubus.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> %passThru, i16 %mask)
+  ret <16 x i16> %res
+}
+
+define <16 x i16> @test_mask_subs_epu16_rmkz_256(<16 x i16> %a, <16 x i16>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu16_rmkz_256
+  ;CHECK: vpsubusw (%rdi), %ymm0, %ymm0 {%k1} {z} 
+  %b = load <16 x i16>, <16 x i16>* %ptr_b
+  %res = call <16 x i16> @llvm.x86.avx512.mask.psubus.w.256(<16 x i16> %a, <16 x i16> %b, <16 x i16> zeroinitializer, i16 %mask)
+  ret <16 x i16> %res
+}
+
+declare <16 x i16> @llvm.x86.avx512.mask.psubus.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)
+
+define <16 x i8> @test_mask_adds_epi8_rr_128(<16 x i8> %a, <16 x i8> %b) {
+  ;CHECK-LABEL: test_mask_adds_epi8_rr_128
+  ;CHECK: vpaddsb %xmm1, %xmm0, %xmm0 
+  %res = call <16 x i8> @llvm.x86.avx512.mask.padds.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 -1)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_adds_epi8_rrk_128(<16 x i8> %a, <16 x i8> %b, <16 x i8> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi8_rrk_128
+  ;CHECK: vpaddsb %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <16 x i8> @llvm.x86.avx512.mask.padds.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> %passThru, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_adds_epi8_rrkz_128(<16 x i8> %a, <16 x i8> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi8_rrkz_128
+  ;CHECK: vpaddsb %xmm1, %xmm0, %xmm0 {%k1} {z} 
+  %res = call <16 x i8> @llvm.x86.avx512.mask.padds.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_adds_epi8_rm_128(<16 x i8> %a, <16 x i8>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_adds_epi8_rm_128
+  ;CHECK: vpaddsb (%rdi), %xmm0, %xmm0 
+  %b = load <16 x i8>, <16 x i8>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.padds.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 -1)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_adds_epi8_rmk_128(<16 x i8> %a, <16 x i8>* %ptr_b, <16 x i8> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi8_rmk_128
+  ;CHECK: vpaddsb (%rdi), %xmm0, %xmm1 {%k1} 
+  %b = load <16 x i8>, <16 x i8>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.padds.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> %passThru, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_adds_epi8_rmkz_128(<16 x i8> %a, <16 x i8>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi8_rmkz_128
+  ;CHECK: vpaddsb (%rdi), %xmm0, %xmm0 {%k1} {z} 
+  %b = load <16 x i8>, <16 x i8>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.padds.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 %mask)
+  ret <16 x i8> %res
+}
+
+declare <16 x i8> @llvm.x86.avx512.mask.padds.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
+
+define <32 x i8> @test_mask_adds_epi8_rr_256(<32 x i8> %a, <32 x i8> %b) {
+  ;CHECK-LABEL: test_mask_adds_epi8_rr_256
+  ;CHECK: vpaddsb %ymm1, %ymm0, %ymm0 
+  %res = call <32 x i8> @llvm.x86.avx512.mask.padds.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 -1)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_adds_epi8_rrk_256(<32 x i8> %a, <32 x i8> %b, <32 x i8> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi8_rrk_256
+  ;CHECK: vpaddsb %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <32 x i8> @llvm.x86.avx512.mask.padds.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> %passThru, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_adds_epi8_rrkz_256(<32 x i8> %a, <32 x i8> %b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi8_rrkz_256
+  ;CHECK: vpaddsb %ymm1, %ymm0, %ymm0 {%k1} {z} 
+  %res = call <32 x i8> @llvm.x86.avx512.mask.padds.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_adds_epi8_rm_256(<32 x i8> %a, <32 x i8>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_adds_epi8_rm_256
+  ;CHECK: vpaddsb (%rdi), %ymm0, %ymm0    
+  %b = load <32 x i8>, <32 x i8>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.padds.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 -1)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_adds_epi8_rmk_256(<32 x i8> %a, <32 x i8>* %ptr_b, <32 x i8> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi8_rmk_256
+  ;CHECK: vpaddsb (%rdi), %ymm0, %ymm1 {%k1} 
+  %b = load <32 x i8>, <32 x i8>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.padds.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> %passThru, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_adds_epi8_rmkz_256(<32 x i8> %a, <32 x i8>* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epi8_rmkz_256
+  ;CHECK: vpaddsb (%rdi), %ymm0, %ymm0 {%k1} {z} 
+  %b = load <32 x i8>, <32 x i8>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.padds.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 %mask)
+  ret <32 x i8> %res
+}
+
+declare <32 x i8> @llvm.x86.avx512.mask.padds.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
+
+define <16 x i8> @test_mask_subs_epi8_rr_128(<16 x i8> %a, <16 x i8> %b) {
+  ;CHECK-LABEL: test_mask_subs_epi8_rr_128
+  ;CHECK: vpsubsb %xmm1, %xmm0, %xmm0     
+  %res = call <16 x i8> @llvm.x86.avx512.mask.psubs.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 -1)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_subs_epi8_rrk_128(<16 x i8> %a, <16 x i8> %b, <16 x i8> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi8_rrk_128
+  ;CHECK: vpsubsb %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <16 x i8> @llvm.x86.avx512.mask.psubs.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> %passThru, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_subs_epi8_rrkz_128(<16 x i8> %a, <16 x i8> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi8_rrkz_128
+  ;CHECK: vpsubsb %xmm1, %xmm0, %xmm0 {%k1} {z} 
+  %res = call <16 x i8> @llvm.x86.avx512.mask.psubs.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_subs_epi8_rm_128(<16 x i8> %a, <16 x i8>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_subs_epi8_rm_128
+  ;CHECK: vpsubsb (%rdi), %xmm0, %xmm0
+  %b = load <16 x i8>, <16 x i8>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.psubs.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 -1)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_subs_epi8_rmk_128(<16 x i8> %a, <16 x i8>* %ptr_b, <16 x i8> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi8_rmk_128
+  ;CHECK: vpsubsb (%rdi), %xmm0, %xmm1 {%k1} 
+  %b = load <16 x i8>, <16 x i8>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.psubs.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> %passThru, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_subs_epi8_rmkz_128(<16 x i8> %a, <16 x i8>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi8_rmkz_128
+  ;CHECK: vpsubsb (%rdi), %xmm0, %xmm0 {%k1} {z} 
+  %b = load <16 x i8>, <16 x i8>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.psubs.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 %mask)
+  ret <16 x i8> %res
+}
+
+declare <16 x i8> @llvm.x86.avx512.mask.psubs.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
+
+define <32 x i8> @test_mask_subs_epi8_rr_256(<32 x i8> %a, <32 x i8> %b) {
+  ;CHECK-LABEL: test_mask_subs_epi8_rr_256
+  ;CHECK: vpsubsb %ymm1, %ymm0, %ymm0     
+  %res = call <32 x i8> @llvm.x86.avx512.mask.psubs.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 -1)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_subs_epi8_rrk_256(<32 x i8> %a, <32 x i8> %b, <32 x i8> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi8_rrk_256
+  ;CHECK: vpsubsb %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <32 x i8> @llvm.x86.avx512.mask.psubs.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> %passThru, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_subs_epi8_rrkz_256(<32 x i8> %a, <32 x i8> %b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi8_rrkz_256
+  ;CHECK: vpsubsb %ymm1, %ymm0, %ymm0 {%k1} {z} 
+  %res = call <32 x i8> @llvm.x86.avx512.mask.psubs.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_subs_epi8_rm_256(<32 x i8> %a, <32 x i8>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_subs_epi8_rm_256
+  ;CHECK: vpsubsb (%rdi), %ymm0, %ymm0    
+  %b = load <32 x i8>, <32 x i8>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.psubs.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 -1)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_subs_epi8_rmk_256(<32 x i8> %a, <32 x i8>* %ptr_b, <32 x i8> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi8_rmk_256
+  ;CHECK: vpsubsb (%rdi), %ymm0, %ymm1 {%k1} 
+  %b = load <32 x i8>, <32 x i8>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.psubs.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> %passThru, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_subs_epi8_rmkz_256(<32 x i8> %a, <32 x i8>* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epi8_rmkz_256
+  ;CHECK: vpsubsb (%rdi), %ymm0, %ymm0 {%k1} {z} 
+  %b = load <32 x i8>, <32 x i8>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.psubs.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 %mask)
+  ret <32 x i8> %res
+}
+
+declare <32 x i8> @llvm.x86.avx512.mask.psubs.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
+
+define <16 x i8> @test_mask_adds_epu8_rr_128(<16 x i8> %a, <16 x i8> %b) {
+  ;CHECK-LABEL: test_mask_adds_epu8_rr_128
+  ;CHECK: vpaddusb %xmm1, %xmm0, %xmm0 
+  %res = call <16 x i8> @llvm.x86.avx512.mask.paddus.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 -1)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_adds_epu8_rrk_128(<16 x i8> %a, <16 x i8> %b, <16 x i8> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu8_rrk_128
+  ;CHECK: vpaddusb %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <16 x i8> @llvm.x86.avx512.mask.paddus.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> %passThru, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_adds_epu8_rrkz_128(<16 x i8> %a, <16 x i8> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu8_rrkz_128
+  ;CHECK: vpaddusb %xmm1, %xmm0, %xmm0 {%k1} {z} 
+  %res = call <16 x i8> @llvm.x86.avx512.mask.paddus.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_adds_epu8_rm_128(<16 x i8> %a, <16 x i8>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_adds_epu8_rm_128
+  ;CHECK: vpaddusb (%rdi), %xmm0, %xmm0 
+  %b = load <16 x i8>, <16 x i8>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.paddus.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 -1)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_adds_epu8_rmk_128(<16 x i8> %a, <16 x i8>* %ptr_b, <16 x i8> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu8_rmk_128
+  ;CHECK: vpaddusb (%rdi), %xmm0, %xmm1 {%k1} 
+  %b = load <16 x i8>, <16 x i8>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.paddus.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> %passThru, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_adds_epu8_rmkz_128(<16 x i8> %a, <16 x i8>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu8_rmkz_128
+  ;CHECK: vpaddusb (%rdi), %xmm0, %xmm0 {%k1} {z} 
+  %b = load <16 x i8>, <16 x i8>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.paddus.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 %mask)
+  ret <16 x i8> %res
+}
+
+declare <16 x i8> @llvm.x86.avx512.mask.paddus.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
+
+define <32 x i8> @test_mask_adds_epu8_rr_256(<32 x i8> %a, <32 x i8> %b) {
+  ;CHECK-LABEL: test_mask_adds_epu8_rr_256
+  ;CHECK: vpaddusb %ymm1, %ymm0, %ymm0 
+  %res = call <32 x i8> @llvm.x86.avx512.mask.paddus.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 -1)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_adds_epu8_rrk_256(<32 x i8> %a, <32 x i8> %b, <32 x i8> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu8_rrk_256
+  ;CHECK: vpaddusb %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <32 x i8> @llvm.x86.avx512.mask.paddus.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> %passThru, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_adds_epu8_rrkz_256(<32 x i8> %a, <32 x i8> %b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu8_rrkz_256
+  ;CHECK: vpaddusb %ymm1, %ymm0, %ymm0 {%k1} {z} 
+  %res = call <32 x i8> @llvm.x86.avx512.mask.paddus.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_adds_epu8_rm_256(<32 x i8> %a, <32 x i8>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_adds_epu8_rm_256
+  ;CHECK: vpaddusb (%rdi), %ymm0, %ymm0    
+  %b = load <32 x i8>, <32 x i8>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.paddus.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 -1)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_adds_epu8_rmk_256(<32 x i8> %a, <32 x i8>* %ptr_b, <32 x i8> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu8_rmk_256
+  ;CHECK: vpaddusb (%rdi), %ymm0, %ymm1 {%k1} 
+  %b = load <32 x i8>, <32 x i8>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.paddus.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> %passThru, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_adds_epu8_rmkz_256(<32 x i8> %a, <32 x i8>* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_adds_epu8_rmkz_256
+  ;CHECK: vpaddusb (%rdi), %ymm0, %ymm0 {%k1} {z} 
+  %b = load <32 x i8>, <32 x i8>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.paddus.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 %mask)
+  ret <32 x i8> %res
+}
+
+declare <32 x i8> @llvm.x86.avx512.mask.paddus.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
+
+define <16 x i8> @test_mask_subs_epu8_rr_128(<16 x i8> %a, <16 x i8> %b) {
+  ;CHECK-LABEL: test_mask_subs_epu8_rr_128
+  ;CHECK: vpsubusb %xmm1, %xmm0, %xmm0     
+  %res = call <16 x i8> @llvm.x86.avx512.mask.psubus.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 -1)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_subs_epu8_rrk_128(<16 x i8> %a, <16 x i8> %b, <16 x i8> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu8_rrk_128
+  ;CHECK: vpsubusb %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <16 x i8> @llvm.x86.avx512.mask.psubus.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> %passThru, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_subs_epu8_rrkz_128(<16 x i8> %a, <16 x i8> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu8_rrkz_128
+  ;CHECK: vpsubusb %xmm1, %xmm0, %xmm0 {%k1} {z} 
+  %res = call <16 x i8> @llvm.x86.avx512.mask.psubus.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_subs_epu8_rm_128(<16 x i8> %a, <16 x i8>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_subs_epu8_rm_128
+  ;CHECK: vpsubusb (%rdi), %xmm0, %xmm0
+  %b = load <16 x i8>, <16 x i8>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.psubus.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 -1)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_subs_epu8_rmk_128(<16 x i8> %a, <16 x i8>* %ptr_b, <16 x i8> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu8_rmk_128
+  ;CHECK: vpsubusb (%rdi), %xmm0, %xmm1 {%k1} 
+  %b = load <16 x i8>, <16 x i8>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.psubus.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> %passThru, i16 %mask)
+  ret <16 x i8> %res
+}
+
+define <16 x i8> @test_mask_subs_epu8_rmkz_128(<16 x i8> %a, <16 x i8>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu8_rmkz_128
+  ;CHECK: vpsubusb (%rdi), %xmm0, %xmm0 {%k1} {z} 
+  %b = load <16 x i8>, <16 x i8>* %ptr_b
+  %res = call <16 x i8> @llvm.x86.avx512.mask.psubus.b.128(<16 x i8> %a, <16 x i8> %b, <16 x i8> zeroinitializer, i16 %mask)
+  ret <16 x i8> %res
+}
+
+declare <16 x i8> @llvm.x86.avx512.mask.psubus.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
+
+define <32 x i8> @test_mask_subs_epu8_rr_256(<32 x i8> %a, <32 x i8> %b) {
+  ;CHECK-LABEL: test_mask_subs_epu8_rr_256
+  ;CHECK: vpsubusb %ymm1, %ymm0, %ymm0     
+  %res = call <32 x i8> @llvm.x86.avx512.mask.psubus.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 -1)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_subs_epu8_rrk_256(<32 x i8> %a, <32 x i8> %b, <32 x i8> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu8_rrk_256
+  ;CHECK: vpsubusb %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <32 x i8> @llvm.x86.avx512.mask.psubus.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> %passThru, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_subs_epu8_rrkz_256(<32 x i8> %a, <32 x i8> %b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu8_rrkz_256
+  ;CHECK: vpsubusb %ymm1, %ymm0, %ymm0 {%k1} {z} 
+  %res = call <32 x i8> @llvm.x86.avx512.mask.psubus.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_subs_epu8_rm_256(<32 x i8> %a, <32 x i8>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_subs_epu8_rm_256
+  ;CHECK: vpsubusb (%rdi), %ymm0, %ymm0    
+  %b = load <32 x i8>, <32 x i8>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.psubus.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 -1)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_subs_epu8_rmk_256(<32 x i8> %a, <32 x i8>* %ptr_b, <32 x i8> %passThru, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu8_rmk_256
+  ;CHECK: vpsubusb (%rdi), %ymm0, %ymm1 {%k1} 
+  %b = load <32 x i8>, <32 x i8>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.psubus.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> %passThru, i32 %mask)
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_mask_subs_epu8_rmkz_256(<32 x i8> %a, <32 x i8>* %ptr_b, i32 %mask) {
+  ;CHECK-LABEL: test_mask_subs_epu8_rmkz_256
+  ;CHECK: vpsubusb (%rdi), %ymm0, %ymm0 {%k1} {z} 
+  %b = load <32 x i8>, <32 x i8>* %ptr_b
+  %res = call <32 x i8> @llvm.x86.avx512.mask.psubus.b.256(<32 x i8> %a, <32 x i8> %b, <32 x i8> zeroinitializer, i32 %mask)
+  ret <32 x i8> %res
+}
+
+declare <32 x i8> @llvm.x86.avx512.mask.psubus.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
\ No newline at end of file
diff --git a/test/CodeGen/X86/avx512bwvl-mov.ll b/test/CodeGen/X86/avx512bwvl-mov.ll
index 835844fc821c..8a9a4fa5e5e2 100644
--- a/test/CodeGen/X86/avx512bwvl-mov.ll
+++ b/test/CodeGen/X86/avx512bwvl-mov.ll
@@ -5,7 +5,7 @@
 ; CHECK: ret
 define <32 x i8> @test_256_1(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <32 x i8>*
-  %res = load <32 x i8>* %vaddr, align 1
+  %res = load <32 x i8>, <32 x i8>* %vaddr, align 1
   ret <32 x i8>%res
 }
 
@@ -24,7 +24,7 @@ define void @test_256_2(i8 * %addr, <32 x i8> %data) {
 define <32 x i8> @test_256_3(i8 * %addr, <32 x i8> %old, <32 x i8> %mask1) {
   %mask = icmp ne <32 x i8> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <32 x i8>*
-  %r = load <32 x i8>* %vaddr, align 1
+  %r = load <32 x i8>, <32 x i8>* %vaddr, align 1
   %res = select <32 x i1> %mask, <32 x i8> %r, <32 x i8> %old
   ret <32 x i8>%res
 }
@@ -35,7 +35,7 @@ define <32 x i8> @test_256_3(i8 * %addr, <32 x i8> %old, <32 x i8> %mask1) {
 define <32 x i8> @test_256_4(i8 * %addr, <32 x i8> %mask1) {
   %mask = icmp ne <32 x i8> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <32 x i8>*
-  %r = load <32 x i8>* %vaddr, align 1
+  %r = load <32 x i8>, <32 x i8>* %vaddr, align 1
   %res = select <32 x i1> %mask, <32 x i8> %r, <32 x i8> zeroinitializer
   ret <32 x i8>%res
 }
@@ -45,7 +45,7 @@ define <32 x i8> @test_256_4(i8 * %addr, <32 x i8> %mask1) {
 ; CHECK: ret
 define <16 x i16> @test_256_5(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <16 x i16>*
-  %res = load <16 x i16>* %vaddr, align 1
+  %res = load <16 x i16>, <16 x i16>* %vaddr, align 1
   ret <16 x i16>%res
 }
 
@@ -64,7 +64,7 @@ define void @test_256_6(i8 * %addr, <16 x i16> %data) {
 define <16 x i16> @test_256_7(i8 * %addr, <16 x i16> %old, <16 x i16> %mask1) {
   %mask = icmp ne <16 x i16> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <16 x i16>*
-  %r = load <16 x i16>* %vaddr, align 1
+  %r = load <16 x i16>, <16 x i16>* %vaddr, align 1
   %res = select <16 x i1> %mask, <16 x i16> %r, <16 x i16> %old
   ret <16 x i16>%res
 }
@@ -75,7 +75,7 @@ define <16 x i16> @test_256_7(i8 * %addr, <16 x i16> %old, <16 x i16> %mask1) {
 define <16 x i16> @test_256_8(i8 * %addr, <16 x i16> %mask1) {
   %mask = icmp ne <16 x i16> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <16 x i16>*
-  %r = load <16 x i16>* %vaddr, align 1
+  %r = load <16 x i16>, <16 x i16>* %vaddr, align 1
   %res = select <16 x i1> %mask, <16 x i16> %r, <16 x i16> zeroinitializer
   ret <16 x i16>%res
 }
@@ -85,7 +85,7 @@ define <16 x i16> @test_256_8(i8 * %addr, <16 x i16> %mask1) {
 ; CHECK: ret
 define <16 x i8> @test_128_1(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <16 x i8>*
-  %res = load <16 x i8>* %vaddr, align 1
+  %res = load <16 x i8>, <16 x i8>* %vaddr, align 1
   ret <16 x i8>%res
 }
 
@@ -104,7 +104,7 @@ define void @test_128_2(i8 * %addr, <16 x i8> %data) {
 define <16 x i8> @test_128_3(i8 * %addr, <16 x i8> %old, <16 x i8> %mask1) {
   %mask = icmp ne <16 x i8> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <16 x i8>*
-  %r = load <16 x i8>* %vaddr, align 1
+  %r = load <16 x i8>, <16 x i8>* %vaddr, align 1
   %res = select <16 x i1> %mask, <16 x i8> %r, <16 x i8> %old
   ret <16 x i8>%res
 }
@@ -115,7 +115,7 @@ define <16 x i8> @test_128_3(i8 * %addr, <16 x i8> %old, <16 x i8> %mask1) {
 define <16 x i8> @test_128_4(i8 * %addr, <16 x i8> %mask1) {
   %mask = icmp ne <16 x i8> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <16 x i8>*
-  %r = load <16 x i8>* %vaddr, align 1
+  %r = load <16 x i8>, <16 x i8>* %vaddr, align 1
   %res = select <16 x i1> %mask, <16 x i8> %r, <16 x i8> zeroinitializer
   ret <16 x i8>%res
 }
@@ -125,7 +125,7 @@ define <16 x i8> @test_128_4(i8 * %addr, <16 x i8> %mask1) {
 ; CHECK: ret
 define <8 x i16> @test_128_5(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <8 x i16>*
-  %res = load <8 x i16>* %vaddr, align 1
+  %res = load <8 x i16>, <8 x i16>* %vaddr, align 1
   ret <8 x i16>%res
 }
 
@@ -144,7 +144,7 @@ define void @test_128_6(i8 * %addr, <8 x i16> %data) {
 define <8 x i16> @test_128_7(i8 * %addr, <8 x i16> %old, <8 x i16> %mask1) {
   %mask = icmp ne <8 x i16> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x i16>*
-  %r = load <8 x i16>* %vaddr, align 1
+  %r = load <8 x i16>, <8 x i16>* %vaddr, align 1
   %res = select <8 x i1> %mask, <8 x i16> %r, <8 x i16> %old
   ret <8 x i16>%res
 }
@@ -155,7 +155,7 @@ define <8 x i16> @test_128_7(i8 * %addr, <8 x i16> %old, <8 x i16> %mask1) {
 define <8 x i16> @test_128_8(i8 * %addr, <8 x i16> %mask1) {
   %mask = icmp ne <8 x i16> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x i16>*
-  %r = load <8 x i16>* %vaddr, align 1
+  %r = load <8 x i16>, <8 x i16>* %vaddr, align 1
   %res = select <8 x i1> %mask, <8 x i16> %r, <8 x i16> zeroinitializer
   ret <8 x i16>%res
 }
diff --git a/test/CodeGen/X86/avx512bwvl-vec-cmp.ll b/test/CodeGen/X86/avx512bwvl-vec-cmp.ll
index 2d13a166a725..9bf02fa41d9a 100644
--- a/test/CodeGen/X86/avx512bwvl-vec-cmp.ll
+++ b/test/CodeGen/X86/avx512bwvl-vec-cmp.ll
@@ -45,7 +45,7 @@ define <32 x i8> @test256_4(<32 x i8> %x, <32 x i8> %y, <32 x i8> %x1) nounwind
 ; CHECK: vmovdqu16
 ; CHECK: ret
 define <16 x i16> @test256_5(<16 x i16> %x, <16 x i16> %x1, <16 x i16>* %yp) nounwind {
-  %y = load <16 x i16>* %yp, align 4
+  %y = load <16 x i16>, <16 x i16>* %yp, align 4
   %mask = icmp eq <16 x i16> %x, %y
   %max = select <16 x i1> %mask, <16 x i16> %x, <16 x i16> %x1
   ret <16 x i16> %max
@@ -56,7 +56,7 @@ define <16 x i16> @test256_5(<16 x i16> %x, <16 x i16> %x1, <16 x i16>* %yp) nou
 ; CHECK: vmovdqu16
 ; CHECK: ret
 define <16 x i16> @test256_6(<16 x i16> %x, <16 x i16> %x1, <16 x i16>* %y.ptr) nounwind {
-  %y = load <16 x i16>* %y.ptr, align 4
+  %y = load <16 x i16>, <16 x i16>* %y.ptr, align 4
   %mask = icmp sgt <16 x i16> %x, %y
   %max = select <16 x i1> %mask, <16 x i16> %x, <16 x i16> %x1
   ret <16 x i16> %max
@@ -67,7 +67,7 @@ define <16 x i16> @test256_6(<16 x i16> %x, <16 x i16> %x1, <16 x i16>* %y.ptr)
 ; CHECK: vmovdqu16
 ; CHECK: ret
 define <16 x i16> @test256_7(<16 x i16> %x, <16 x i16> %x1, <16 x i16>* %y.ptr) nounwind {
-  %y = load <16 x i16>* %y.ptr, align 4
+  %y = load <16 x i16>, <16 x i16>* %y.ptr, align 4
   %mask = icmp sle <16 x i16> %x, %y
   %max = select <16 x i1> %mask, <16 x i16> %x, <16 x i16> %x1
   ret <16 x i16> %max
@@ -78,7 +78,7 @@ define <16 x i16> @test256_7(<16 x i16> %x, <16 x i16> %x1, <16 x i16>* %y.ptr)
 ; CHECK: vmovdqu16
 ; CHECK: ret
 define <16 x i16> @test256_8(<16 x i16> %x, <16 x i16> %x1, <16 x i16>* %y.ptr) nounwind {
-  %y = load <16 x i16>* %y.ptr, align 4
+  %y = load <16 x i16>, <16 x i16>* %y.ptr, align 4
   %mask = icmp ule <16 x i16> %x, %y
   %max = select <16 x i1> %mask, <16 x i16> %x, <16 x i16> %x1
   ret <16 x i16> %max
@@ -114,7 +114,7 @@ define <32 x i8> @test256_10(<32 x i8> %x, <32 x i8> %y, <32 x i8> %x1, <32 x i8
 ; CHECK: ret
 define <32 x i8> @test256_11(<32 x i8> %x, <32 x i8>* %y.ptr, <32 x i8> %x1, <32 x i8> %y1) nounwind {
   %mask1 = icmp sgt <32 x i8> %x1, %y1
-  %y = load <32 x i8>* %y.ptr, align 4
+  %y = load <32 x i8>, <32 x i8>* %y.ptr, align 4
   %mask0 = icmp sgt <32 x i8> %x, %y
   %mask = select <32 x i1> %mask0, <32 x i1> %mask1, <32 x i1> zeroinitializer
   %max = select <32 x i1> %mask, <32 x i8> %x, <32 x i8> %x1
@@ -127,7 +127,7 @@ define <32 x i8> @test256_11(<32 x i8> %x, <32 x i8>* %y.ptr, <32 x i8> %x1, <32
 ; CHECK: ret
 define <16 x i16> @test256_12(<16 x i16> %x, <16 x i16>* %y.ptr, <16 x i16> %x1, <16 x i16> %y1) nounwind {
   %mask1 = icmp sge <16 x i16> %x1, %y1
-  %y = load <16 x i16>* %y.ptr, align 4
+  %y = load <16 x i16>, <16 x i16>* %y.ptr, align 4
   %mask0 = icmp ule <16 x i16> %x, %y
   %mask = select <16 x i1> %mask0, <16 x i1> %mask1, <16 x i1> zeroinitializer
   %max = select <16 x i1> %mask, <16 x i16> %x, <16 x i16> %x1
@@ -179,7 +179,7 @@ define <16 x i8> @test128_4(<16 x i8> %x, <16 x i8> %y, <16 x i8> %x1) nounwind
 ; CHECK: vmovdqu16
 ; CHECK: ret
 define <8 x i16> @test128_5(<8 x i16> %x, <8 x i16> %x1, <8 x i16>* %yp) nounwind {
-  %y = load <8 x i16>* %yp, align 4
+  %y = load <8 x i16>, <8 x i16>* %yp, align 4
   %mask = icmp eq <8 x i16> %x, %y
   %max = select <8 x i1> %mask, <8 x i16> %x, <8 x i16> %x1
   ret <8 x i16> %max
@@ -190,7 +190,7 @@ define <8 x i16> @test128_5(<8 x i16> %x, <8 x i16> %x1, <8 x i16>* %yp) nounwin
 ; CHECK: vmovdqu16
 ; CHECK: ret
 define <8 x i16> @test128_6(<8 x i16> %x, <8 x i16> %x1, <8 x i16>* %y.ptr) nounwind {
-  %y = load <8 x i16>* %y.ptr, align 4
+  %y = load <8 x i16>, <8 x i16>* %y.ptr, align 4
   %mask = icmp sgt <8 x i16> %x, %y
   %max = select <8 x i1> %mask, <8 x i16> %x, <8 x i16> %x1
   ret <8 x i16> %max
@@ -201,7 +201,7 @@ define <8 x i16> @test128_6(<8 x i16> %x, <8 x i16> %x1, <8 x i16>* %y.ptr) noun
 ; CHECK: vmovdqu16
 ; CHECK: ret
 define <8 x i16> @test128_7(<8 x i16> %x, <8 x i16> %x1, <8 x i16>* %y.ptr) nounwind {
-  %y = load <8 x i16>* %y.ptr, align 4
+  %y = load <8 x i16>, <8 x i16>* %y.ptr, align 4
   %mask = icmp sle <8 x i16> %x, %y
   %max = select <8 x i1> %mask, <8 x i16> %x, <8 x i16> %x1
   ret <8 x i16> %max
@@ -212,7 +212,7 @@ define <8 x i16> @test128_7(<8 x i16> %x, <8 x i16> %x1, <8 x i16>* %y.ptr) noun
 ; CHECK: vmovdqu16
 ; CHECK: ret
 define <8 x i16> @test128_8(<8 x i16> %x, <8 x i16> %x1, <8 x i16>* %y.ptr) nounwind {
-  %y = load <8 x i16>* %y.ptr, align 4
+  %y = load <8 x i16>, <8 x i16>* %y.ptr, align 4
   %mask = icmp ule <8 x i16> %x, %y
   %max = select <8 x i1> %mask, <8 x i16> %x, <8 x i16> %x1
   ret <8 x i16> %max
@@ -248,7 +248,7 @@ define <16 x i8> @test128_10(<16 x i8> %x, <16 x i8> %y, <16 x i8> %x1, <16 x i8
 ; CHECK: ret
 define <16 x i8> @test128_11(<16 x i8> %x, <16 x i8>* %y.ptr, <16 x i8> %x1, <16 x i8> %y1) nounwind {
   %mask1 = icmp sgt <16 x i8> %x1, %y1
-  %y = load <16 x i8>* %y.ptr, align 4
+  %y = load <16 x i8>, <16 x i8>* %y.ptr, align 4
   %mask0 = icmp sgt <16 x i8> %x, %y
   %mask = select <16 x i1> %mask0, <16 x i1> %mask1, <16 x i1> zeroinitializer
   %max = select <16 x i1> %mask, <16 x i8> %x, <16 x i8> %x1
@@ -261,7 +261,7 @@ define <16 x i8> @test128_11(<16 x i8> %x, <16 x i8>* %y.ptr, <16 x i8> %x1, <16
 ; CHECK: ret
 define <8 x i16> @test128_12(<8 x i16> %x, <8 x i16>* %y.ptr, <8 x i16> %x1, <8 x i16> %y1) nounwind {
   %mask1 = icmp sge <8 x i16> %x1, %y1
-  %y = load <8 x i16>* %y.ptr, align 4
+  %y = load <8 x i16>, <8 x i16>* %y.ptr, align 4
   %mask0 = icmp ule <8 x i16> %x, %y
   %mask = select <8 x i1> %mask0, <8 x i1> %mask1, <8 x i1> zeroinitializer
   %max = select <8 x i1> %mask, <8 x i16> %x, <8 x i16> %x1
diff --git a/test/CodeGen/X86/avx512dq-mask-op.ll b/test/CodeGen/X86/avx512dq-mask-op.ll
index 32a2633f8d06..b4d11bc0b77b 100644
--- a/test/CodeGen/X86/avx512dq-mask-op.ll
+++ b/test/CodeGen/X86/avx512dq-mask-op.ll
@@ -11,7 +11,7 @@ define i8 @mask8(i8 %x) {
 }
 
 define void @mask8_mem(i8* %ptr) {
-  %x = load i8* %ptr, align 4
+  %x = load i8, i8* %ptr, align 4
   %m0 = bitcast i8 %x to <8 x i1>
   %m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
   %ret = bitcast <8 x i1> %m1 to i8
diff --git a/test/CodeGen/X86/avx512dqvl-intrinsics.ll b/test/CodeGen/X86/avx512dqvl-intrinsics.ll
new file mode 100644
index 000000000000..c577abee6640
--- /dev/null
+++ b/test/CodeGen/X86/avx512dqvl-intrinsics.ll
@@ -0,0 +1,1155 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512dq -mattr=+avx512vl --show-mc-encoding| FileCheck %s
+
+define <8 x i64> @test_mask_mullo_epi64_rr_512(<8 x i64> %a, <8 x i64> %b) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rr_512
+  ;CHECK: vpmullq %zmm1, %zmm0, %zmm0     ## encoding: [0x62,0xf2,0xfd,0x48,0x40,0xc1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
+  ret <8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mullo_epi64_rrk_512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rrk_512
+  ;CHECK: vpmullq %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf2,0xfd,0x49,0x40,0xd1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
+  ret <8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mullo_epi64_rrkz_512(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rrkz_512
+  ;CHECK: vpmullq %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xc9,0x40,0xc1]
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
+  ret <8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mullo_epi64_rm_512(<8 x i64> %a, <8 x i64>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rm_512
+  ;CHECK: vpmullq (%rdi), %zmm0, %zmm0    ## encoding: [0x62,0xf2,0xfd,0x48,0x40,0x07]
+  %b = load <8 x i64>, <8 x i64>* %ptr_b
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
+  ret <8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mullo_epi64_rmk_512(<8 x i64> %a, <8 x i64>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rmk_512
+  ;CHECK: vpmullq (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x49,0x40,0x0f]
+  %b = load <8 x i64>, <8 x i64>* %ptr_b
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
+  ret <8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mullo_epi64_rmkz_512(<8 x i64> %a, <8 x i64>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rmkz_512
+  ;CHECK: vpmullq (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xc9,0x40,0x07]
+  %b = load <8 x i64>, <8 x i64>* %ptr_b
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
+  ret <8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mullo_epi64_rmb_512(<8 x i64> %a, i64* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rmb_512
+  ;CHECK: vpmullq (%rdi){1to8}, %zmm0, %zmm0  ## encoding: [0x62,0xf2,0xfd,0x58,0x40,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
+  ret <8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mullo_epi64_rmbk_512(<8 x i64> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rmbk_512
+  ;CHECK: vpmullq (%rdi){1to8}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x59,0x40,0x0f]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
+  ret <8 x i64> %res
+}
+
+define <8 x i64> @test_mask_mullo_epi64_rmbkz_512(<8 x i64> %a, i64* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rmbkz_512
+  ;CHECK: vpmullq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xd9,0x40,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
+  ret <8 x i64> %res
+}
+declare <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
+
+define <4 x i64> @test_mask_mullo_epi64_rr_256(<4 x i64> %a, <4 x i64> %b) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rr_256
+  ;CHECK: vpmullq %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf2,0xfd,0x28,0x40,0xc1]
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pmull.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_mullo_epi64_rrk_256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rrk_256
+  ;CHECK: vpmullq %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x40,0xd1]
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pmull.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_mullo_epi64_rrkz_256(<4 x i64> %a, <4 x i64> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rrkz_256
+  ;CHECK: vpmullq %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xa9,0x40,0xc1]
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pmull.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 %mask)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_mullo_epi64_rm_256(<4 x i64> %a, <4 x i64>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rm_256
+  ;CHECK: vpmullq (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf2,0xfd,0x28,0x40,0x07]
+  %b = load <4 x i64>, <4 x i64>* %ptr_b
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pmull.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_mullo_epi64_rmk_256(<4 x i64> %a, <4 x i64>* %ptr_b, <4 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rmk_256
+  ;CHECK: vpmullq (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x40,0x0f]
+  %b = load <4 x i64>, <4 x i64>* %ptr_b
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pmull.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_mullo_epi64_rmkz_256(<4 x i64> %a, <4 x i64>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rmkz_256
+  ;CHECK: vpmullq (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xa9,0x40,0x07]
+  %b = load <4 x i64>, <4 x i64>* %ptr_b
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pmull.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 %mask)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_mullo_epi64_rmb_256(<4 x i64> %a, i64* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rmb_256
+  ;CHECK: vpmullq (%rdi){1to4}, %ymm0, %ymm0  ## encoding: [0x62,0xf2,0xfd,0x38,0x40,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <4 x i64> %vecinit.i, <4 x i64> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pmull.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_mullo_epi64_rmbk_256(<4 x i64> %a, i64* %ptr_b, <4 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rmbk_256
+  ;CHECK: vpmullq (%rdi){1to4}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x39,0x40,0x0f]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <4 x i64> %vecinit.i, <4 x i64> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pmull.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_mullo_epi64_rmbkz_256(<4 x i64> %a, i64* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rmbkz_256
+  ;CHECK: vpmullq (%rdi){1to4}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xb9,0x40,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <4 x i64> %vecinit.i, <4 x i64> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pmull.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 %mask)
+  ret <4 x i64> %res
+}
+
+declare <4 x i64> @llvm.x86.avx512.mask.pmull.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
+
+define <2 x i64> @test_mask_mullo_epi64_rr_128(<2 x i64> %a, <2 x i64> %b) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rr_128
+  ;CHECK: vpmullq %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf2,0xfd,0x08,0x40,0xc1]
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pmull.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_mullo_epi64_rrk_128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rrk_128
+  ;CHECK: vpmullq %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf2,0xfd,0x09,0x40,0xd1]
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pmull.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_mullo_epi64_rrkz_128(<2 x i64> %a, <2 x i64> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rrkz_128
+  ;CHECK: vpmullq %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0x89,0x40,0xc1]
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pmull.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 %mask)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_mullo_epi64_rm_128(<2 x i64> %a, <2 x i64>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rm_128
+  ;CHECK: vpmullq (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf2,0xfd,0x08,0x40,0x07]
+  %b = load <2 x i64>, <2 x i64>* %ptr_b
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pmull.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_mullo_epi64_rmk_128(<2 x i64> %a, <2 x i64>* %ptr_b, <2 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rmk_128
+  ;CHECK: vpmullq (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x09,0x40,0x0f]
+  %b = load <2 x i64>, <2 x i64>* %ptr_b
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pmull.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_mullo_epi64_rmkz_128(<2 x i64> %a, <2 x i64>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rmkz_128
+  ;CHECK: vpmullq (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0x89,0x40,0x07]
+  %b = load <2 x i64>, <2 x i64>* %ptr_b
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pmull.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 %mask)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_mullo_epi64_rmb_128(<2 x i64> %a, i64* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rmb_128
+  ;CHECK: vpmullq (%rdi){1to2}, %xmm0, %xmm0  ## encoding: [0x62,0xf2,0xfd,0x18,0x40,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <2 x i64> %vecinit.i, <2 x i64> undef, <2 x i32> zeroinitializer
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pmull.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_mullo_epi64_rmbk_128(<2 x i64> %a, i64* %ptr_b, <2 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rmbk_128
+  ;CHECK: vpmullq (%rdi){1to2}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x19,0x40,0x0f]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <2 x i64> %vecinit.i, <2 x i64> undef, <2 x i32> zeroinitializer
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pmull.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_mullo_epi64_rmbkz_128(<2 x i64> %a, i64* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mullo_epi64_rmbkz_128
+  ;CHECK: vpmullq (%rdi){1to2}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0x99,0x40,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <2 x i64> %vecinit.i, <2 x i64> undef, <2 x i32> zeroinitializer
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pmull.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 %mask)
+  ret <2 x i64> %res
+}
+
+declare <2 x i64> @llvm.x86.avx512.mask.pmull.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
+
+define <4 x float> @test_mask_andnot_ps_rr_128(<4 x float> %a, <4 x float> %b) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rr_128
+  ;CHECK: vandnps %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf1,0x7c,0x08,0x55,0xc1]
+  %res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_andnot_ps_rrk_128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rrk_128
+  ;CHECK: vandnps %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7c,0x09,0x55,0xd1]
+  %res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_andnot_ps_rrkz_128(<4 x float> %a, <4 x float> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rrkz_128
+  ;CHECK: vandnps %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0x89,0x55,0xc1]
+  %res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_andnot_ps_rm_128(<4 x float> %a, <4 x float>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rm_128
+  ;CHECK: vandnps (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf1,0x7c,0x08,0x55,0x07]
+  %b = load <4 x float>, <4 x float>* %ptr_b
+  %res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_andnot_ps_rmk_128(<4 x float> %a, <4 x float>* %ptr_b, <4 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rmk_128
+  ;CHECK: vandnps (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x09,0x55,0x0f]
+  %b = load <4 x float>, <4 x float>* %ptr_b
+  %res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_andnot_ps_rmkz_128(<4 x float> %a, <4 x float>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rmkz_128
+  ;CHECK: vandnps (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0x89,0x55,0x07]
+  %b = load <4 x float>, <4 x float>* %ptr_b
+  %res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_andnot_ps_rmb_128(<4 x float> %a, float* %ptr_b) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rmb_128
+  ;CHECK: vandnps (%rdi){1to4}, %xmm0, %xmm0  ## encoding: [0x62,0xf1,0x7c,0x18,0x55,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
+  %b = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
+  %res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_andnot_ps_rmbk_128(<4 x float> %a, float* %ptr_b, <4 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rmbk_128
+  ;CHECK: vandnps (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x19,0x55,0x0f]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
+  %b = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
+  %res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_andnot_ps_rmbkz_128(<4 x float> %a, float* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rmbkz_128
+  ;CHECK: vandnps (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0x99,0x55,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
+  %b = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
+  %res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+declare <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
+
+define <8 x float> @test_mask_andnot_ps_rr_256(<8 x float> %a, <8 x float> %b) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rr_256
+  ;CHECK: vandnps %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf1,0x7c,0x28,0x55,0xc1]
+  %res = call <8 x float> @llvm.x86.avx512.mask.andn.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_andnot_ps_rrk_256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rrk_256
+  ;CHECK: vandnps %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7c,0x29,0x55,0xd1]
+  %res = call <8 x float> @llvm.x86.avx512.mask.andn.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_andnot_ps_rrkz_256(<8 x float> %a, <8 x float> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rrkz_256
+  ;CHECK: vandnps %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xa9,0x55,0xc1]
+  %res = call <8 x float> @llvm.x86.avx512.mask.andn.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_andnot_ps_rm_256(<8 x float> %a, <8 x float>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rm_256
+  ;CHECK: vandnps (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf1,0x7c,0x28,0x55,0x07]
+  %b = load <8 x float>, <8 x float>* %ptr_b
+  %res = call <8 x float> @llvm.x86.avx512.mask.andn.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_andnot_ps_rmk_256(<8 x float> %a, <8 x float>* %ptr_b, <8 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rmk_256
+  ;CHECK: vandnps (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x29,0x55,0x0f]
+  %b = load <8 x float>, <8 x float>* %ptr_b
+  %res = call <8 x float> @llvm.x86.avx512.mask.andn.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_andnot_ps_rmkz_256(<8 x float> %a, <8 x float>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rmkz_256
+  ;CHECK: vandnps (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xa9,0x55,0x07]
+  %b = load <8 x float>, <8 x float>* %ptr_b
+  %res = call <8 x float> @llvm.x86.avx512.mask.andn.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_andnot_ps_rmb_256(<8 x float> %a, float* %ptr_b) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rmb_256
+  ;CHECK: vandnps (%rdi){1to8}, %ymm0, %ymm0  ## encoding: [0x62,0xf1,0x7c,0x38,0x55,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <8 x float> undef, float %q, i32 0
+  %b = shufflevector <8 x float> %vecinit.i, <8 x float> undef, <8 x i32> zeroinitializer
+  %res = call <8 x float> @llvm.x86.avx512.mask.andn.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_andnot_ps_rmbk_256(<8 x float> %a, float* %ptr_b, <8 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rmbk_256
+  ;CHECK: vandnps (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x39,0x55,0x0f]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <8 x float> undef, float %q, i32 0
+  %b = shufflevector <8 x float> %vecinit.i, <8 x float> undef, <8 x i32> zeroinitializer
+  %res = call <8 x float> @llvm.x86.avx512.mask.andn.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_andnot_ps_rmbkz_256(<8 x float> %a, float* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rmbkz_256
+  ;CHECK: vandnps (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xb9,0x55,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <8 x float> undef, float %q, i32 0
+  %b = shufflevector <8 x float> %vecinit.i, <8 x float> undef, <8 x i32> zeroinitializer
+  %res = call <8 x float> @llvm.x86.avx512.mask.andn.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+declare <8 x float> @llvm.x86.avx512.mask.andn.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
+
+define <16 x float> @test_mask_andnot_ps_rr_512(<16 x float> %a, <16 x float> %b) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rr_512
+  ;CHECK: vandnps %zmm1, %zmm0, %zmm0     ## encoding: [0x62,0xf1,0x7c,0x48,0x55,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.andn.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 -1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_andnot_ps_rrk_512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rrk_512
+  ;CHECK: vandnps %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7c,0x49,0x55,0xd1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.andn.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_andnot_ps_rrkz_512(<16 x float> %a, <16 x float> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rrkz_512
+  ;CHECK: vandnps %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xc9,0x55,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.andn.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_andnot_ps_rm_512(<16 x float> %a, <16 x float>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rm_512
+  ;CHECK: vandnps (%rdi), %zmm0, %zmm0    ## encoding: [0x62,0xf1,0x7c,0x48,0x55,0x07]
+  %b = load <16 x float>, <16 x float>* %ptr_b
+  %res = call <16 x float> @llvm.x86.avx512.mask.andn.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 -1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_andnot_ps_rmk_512(<16 x float> %a, <16 x float>* %ptr_b, <16 x float> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rmk_512
+  ;CHECK: vandnps (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x49,0x55,0x0f]
+  %b = load <16 x float>, <16 x float>* %ptr_b
+  %res = call <16 x float> @llvm.x86.avx512.mask.andn.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_andnot_ps_rmkz_512(<16 x float> %a, <16 x float>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rmkz_512
+  ;CHECK: vandnps (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xc9,0x55,0x07]
+  %b = load <16 x float>, <16 x float>* %ptr_b
+  %res = call <16 x float> @llvm.x86.avx512.mask.andn.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_andnot_ps_rmb_512(<16 x float> %a, float* %ptr_b) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rmb_512
+  ;CHECK: vandnps (%rdi){1to16}, %zmm0, %zmm0  ## encoding: [0x62,0xf1,0x7c,0x58,0x55,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <16 x float> undef, float %q, i32 0
+  %b = shufflevector <16 x float> %vecinit.i, <16 x float> undef, <16 x i32> zeroinitializer
+  %res = call <16 x float> @llvm.x86.avx512.mask.andn.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 -1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_andnot_ps_rmbk_512(<16 x float> %a, float* %ptr_b, <16 x float> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rmbk_512
+  ;CHECK: vandnps (%rdi){1to16}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x59,0x55,0x0f]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <16 x float> undef, float %q, i32 0
+  %b = shufflevector <16 x float> %vecinit.i, <16 x float> undef, <16 x i32> zeroinitializer
+  %res = call <16 x float> @llvm.x86.avx512.mask.andn.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_andnot_ps_rmbkz_512(<16 x float> %a, float* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_ps_rmbkz_512
+  ;CHECK: vandnps (%rdi){1to16}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xd9,0x55,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <16 x float> undef, float %q, i32 0
+  %b = shufflevector <16 x float> %vecinit.i, <16 x float> undef, <16 x i32> zeroinitializer
+  %res = call <16 x float> @llvm.x86.avx512.mask.andn.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 %mask)
+  ret <16 x float> %res
+}
+
+declare <16 x float> @llvm.x86.avx512.mask.andn.ps.512(<16 x float>, <16 x float>, <16 x float>, i16)
+
+define <4 x float> @test_mask_and_ps_rr_128(<4 x float> %a, <4 x float> %b) {
+  ;CHECK-LABEL: test_mask_and_ps_rr_128
+  ;CHECK: vandps  %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf1,0x7c,0x08,0x54,0xc1]
+  %res = call <4 x float> @llvm.x86.avx512.mask.and.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_and_ps_rrk_128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rrk_128
+  ;CHECK: vandps %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7c,0x09,0x54,0xd1]
+  %res = call <4 x float> @llvm.x86.avx512.mask.and.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_and_ps_rrkz_128(<4 x float> %a, <4 x float> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rrkz_128
+  ;CHECK: vandps %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0x89,0x54,0xc1]
+  %res = call <4 x float> @llvm.x86.avx512.mask.and.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_and_ps_rm_128(<4 x float> %a, <4 x float>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_and_ps_rm_128
+  ;CHECK: vandps (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf1,0x7c,0x08,0x54,0x07]
+  %b = load <4 x float>, <4 x float>* %ptr_b
+  %res = call <4 x float> @llvm.x86.avx512.mask.and.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_and_ps_rmk_128(<4 x float> %a, <4 x float>* %ptr_b, <4 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rmk_128
+  ;CHECK: vandps (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x09,0x54,0x0f]
+  %b = load <4 x float>, <4 x float>* %ptr_b
+  %res = call <4 x float> @llvm.x86.avx512.mask.and.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_and_ps_rmkz_128(<4 x float> %a, <4 x float>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rmkz_128
+  ;CHECK: vandps (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0x89,0x54,0x07]
+  %b = load <4 x float>, <4 x float>* %ptr_b
+  %res = call <4 x float> @llvm.x86.avx512.mask.and.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_and_ps_rmb_128(<4 x float> %a, float* %ptr_b) {
+  ;CHECK-LABEL: test_mask_and_ps_rmb_128
+  ;CHECK: vandps (%rdi){1to4}, %xmm0, %xmm0  ## encoding: [0x62,0xf1,0x7c,0x18,0x54,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
+  %b = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
+  %res = call <4 x float> @llvm.x86.avx512.mask.and.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_and_ps_rmbk_128(<4 x float> %a, float* %ptr_b, <4 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rmbk_128
+  ;CHECK: vandps (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x19,0x54,0x0f]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
+  %b = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
+  %res = call <4 x float> @llvm.x86.avx512.mask.and.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_and_ps_rmbkz_128(<4 x float> %a, float* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rmbkz_128
+  ;CHECK: vandps (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0x99,0x54,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
+  %b = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
+  %res = call <4 x float> @llvm.x86.avx512.mask.and.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+declare <4 x float> @llvm.x86.avx512.mask.and.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
+
+define <8 x float> @test_mask_and_ps_rr_256(<8 x float> %a, <8 x float> %b) {
+  ;CHECK-LABEL: test_mask_and_ps_rr_256
+  ;CHECK: vandps %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf1,0x7c,0x28,0x54,0xc1]
+  %res = call <8 x float> @llvm.x86.avx512.mask.and.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_and_ps_rrk_256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rrk_256
+  ;CHECK: vandps %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7c,0x29,0x54,0xd1]
+  %res = call <8 x float> @llvm.x86.avx512.mask.and.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_and_ps_rrkz_256(<8 x float> %a, <8 x float> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rrkz_256
+  ;CHECK: vandps %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xa9,0x54,0xc1]
+  %res = call <8 x float> @llvm.x86.avx512.mask.and.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_and_ps_rm_256(<8 x float> %a, <8 x float>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_and_ps_rm_256
+  ;CHECK: vandps (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf1,0x7c,0x28,0x54,0x07]
+  %b = load <8 x float>, <8 x float>* %ptr_b
+  %res = call <8 x float> @llvm.x86.avx512.mask.and.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_and_ps_rmk_256(<8 x float> %a, <8 x float>* %ptr_b, <8 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rmk_256
+  ;CHECK: vandps (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x29,0x54,0x0f]
+  %b = load <8 x float>, <8 x float>* %ptr_b
+  %res = call <8 x float> @llvm.x86.avx512.mask.and.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_and_ps_rmkz_256(<8 x float> %a, <8 x float>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rmkz_256
+  ;CHECK: vandps (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xa9,0x54,0x07]
+  %b = load <8 x float>, <8 x float>* %ptr_b
+  %res = call <8 x float> @llvm.x86.avx512.mask.and.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_and_ps_rmb_256(<8 x float> %a, float* %ptr_b) {
+  ;CHECK-LABEL: test_mask_and_ps_rmb_256
+  ;CHECK: vandps (%rdi){1to8}, %ymm0, %ymm0  ## encoding: [0x62,0xf1,0x7c,0x38,0x54,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <8 x float> undef, float %q, i32 0
+  %b = shufflevector <8 x float> %vecinit.i, <8 x float> undef, <8 x i32> zeroinitializer
+  %res = call <8 x float> @llvm.x86.avx512.mask.and.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_and_ps_rmbk_256(<8 x float> %a, float* %ptr_b, <8 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rmbk_256
+  ;CHECK: vandps (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x39,0x54,0x0f]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <8 x float> undef, float %q, i32 0
+  %b = shufflevector <8 x float> %vecinit.i, <8 x float> undef, <8 x i32> zeroinitializer
+  %res = call <8 x float> @llvm.x86.avx512.mask.and.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_and_ps_rmbkz_256(<8 x float> %a, float* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rmbkz_256
+  ;CHECK: vandps (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xb9,0x54,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <8 x float> undef, float %q, i32 0
+  %b = shufflevector <8 x float> %vecinit.i, <8 x float> undef, <8 x i32> zeroinitializer
+  %res = call <8 x float> @llvm.x86.avx512.mask.and.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+declare <8 x float> @llvm.x86.avx512.mask.and.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
+
+define <16 x float> @test_mask_and_ps_rr_512(<16 x float> %a, <16 x float> %b) {
+  ;CHECK-LABEL: test_mask_and_ps_rr_512
+  ;CHECK: vandps %zmm1, %zmm0, %zmm0     ## encoding: [0x62,0xf1,0x7c,0x48,0x54,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.and.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 -1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_and_ps_rrk_512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rrk_512
+  ;CHECK: vandps %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7c,0x49,0x54,0xd1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.and.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_and_ps_rrkz_512(<16 x float> %a, <16 x float> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rrkz_512
+  ;CHECK: vandps %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xc9,0x54,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.and.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_and_ps_rm_512(<16 x float> %a, <16 x float>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_and_ps_rm_512
+  ;CHECK: vandps (%rdi), %zmm0, %zmm0    ## encoding: [0x62,0xf1,0x7c,0x48,0x54,0x07]
+  %b = load <16 x float>, <16 x float>* %ptr_b
+  %res = call <16 x float> @llvm.x86.avx512.mask.and.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 -1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_and_ps_rmk_512(<16 x float> %a, <16 x float>* %ptr_b, <16 x float> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rmk_512
+  ;CHECK: vandps (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x49,0x54,0x0f]
+  %b = load <16 x float>, <16 x float>* %ptr_b
+  %res = call <16 x float> @llvm.x86.avx512.mask.and.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_and_ps_rmkz_512(<16 x float> %a, <16 x float>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rmkz_512
+  ;CHECK: vandps (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xc9,0x54,0x07]
+  %b = load <16 x float>, <16 x float>* %ptr_b
+  %res = call <16 x float> @llvm.x86.avx512.mask.and.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_and_ps_rmb_512(<16 x float> %a, float* %ptr_b) {
+  ;CHECK-LABEL: test_mask_and_ps_rmb_512
+  ;CHECK: vandps (%rdi){1to16}, %zmm0, %zmm0  ## encoding: [0x62,0xf1,0x7c,0x58,0x54,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <16 x float> undef, float %q, i32 0
+  %b = shufflevector <16 x float> %vecinit.i, <16 x float> undef, <16 x i32> zeroinitializer
+  %res = call <16 x float> @llvm.x86.avx512.mask.and.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 -1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_and_ps_rmbk_512(<16 x float> %a, float* %ptr_b, <16 x float> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rmbk_512
+  ;CHECK: vandps (%rdi){1to16}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x59,0x54,0x0f]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <16 x float> undef, float %q, i32 0
+  %b = shufflevector <16 x float> %vecinit.i, <16 x float> undef, <16 x i32> zeroinitializer
+  %res = call <16 x float> @llvm.x86.avx512.mask.and.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_and_ps_rmbkz_512(<16 x float> %a, float* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_and_ps_rmbkz_512
+  ;CHECK: vandps (%rdi){1to16}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xd9,0x54,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <16 x float> undef, float %q, i32 0
+  %b = shufflevector <16 x float> %vecinit.i, <16 x float> undef, <16 x i32> zeroinitializer
+  %res = call <16 x float> @llvm.x86.avx512.mask.and.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 %mask)
+  ret <16 x float> %res
+}
+
+declare <16 x float> @llvm.x86.avx512.mask.and.ps.512(<16 x float>, <16 x float>, <16 x float>, i16)
+
+define <4 x float> @test_mask_or_ps_rr_128(<4 x float> %a, <4 x float> %b) {
+  ;CHECK-LABEL: test_mask_or_ps_rr_128
+  ;CHECK: vorps  %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf1,0x7c,0x08,0x56,0xc1]
+  %res = call <4 x float> @llvm.x86.avx512.mask.or.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_or_ps_rrk_128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rrk_128
+  ;CHECK: vorps %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7c,0x09,0x56,0xd1]
+  %res = call <4 x float> @llvm.x86.avx512.mask.or.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_or_ps_rrkz_128(<4 x float> %a, <4 x float> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rrkz_128
+  ;CHECK: vorps %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0x89,0x56,0xc1]
+  %res = call <4 x float> @llvm.x86.avx512.mask.or.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_or_ps_rm_128(<4 x float> %a, <4 x float>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_or_ps_rm_128
+  ;CHECK: vorps (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf1,0x7c,0x08,0x56,0x07]
+  %b = load <4 x float>, <4 x float>* %ptr_b
+  %res = call <4 x float> @llvm.x86.avx512.mask.or.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_or_ps_rmk_128(<4 x float> %a, <4 x float>* %ptr_b, <4 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rmk_128
+  ;CHECK: vorps (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x09,0x56,0x0f]
+  %b = load <4 x float>, <4 x float>* %ptr_b
+  %res = call <4 x float> @llvm.x86.avx512.mask.or.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_or_ps_rmkz_128(<4 x float> %a, <4 x float>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rmkz_128
+  ;CHECK: vorps (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0x89,0x56,0x07]
+  %b = load <4 x float>, <4 x float>* %ptr_b
+  %res = call <4 x float> @llvm.x86.avx512.mask.or.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_or_ps_rmb_128(<4 x float> %a, float* %ptr_b) {
+  ;CHECK-LABEL: test_mask_or_ps_rmb_128
+  ;CHECK: vorps (%rdi){1to4}, %xmm0, %xmm0  ## encoding: [0x62,0xf1,0x7c,0x18,0x56,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
+  %b = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
+  %res = call <4 x float> @llvm.x86.avx512.mask.or.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_or_ps_rmbk_128(<4 x float> %a, float* %ptr_b, <4 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rmbk_128
+  ;CHECK: vorps (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x19,0x56,0x0f]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
+  %b = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
+  %res = call <4 x float> @llvm.x86.avx512.mask.or.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_or_ps_rmbkz_128(<4 x float> %a, float* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rmbkz_128
+  ;CHECK: vorps (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0x99,0x56,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
+  %b = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
+  %res = call <4 x float> @llvm.x86.avx512.mask.or.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+declare <4 x float> @llvm.x86.avx512.mask.or.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
+
+define <8 x float> @test_mask_or_ps_rr_256(<8 x float> %a, <8 x float> %b) {
+  ;CHECK-LABEL: test_mask_or_ps_rr_256
+  ;CHECK: vorps %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf1,0x7c,0x28,0x56,0xc1]
+  %res = call <8 x float> @llvm.x86.avx512.mask.or.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_or_ps_rrk_256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rrk_256
+  ;CHECK: vorps %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7c,0x29,0x56,0xd1]
+  %res = call <8 x float> @llvm.x86.avx512.mask.or.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_or_ps_rrkz_256(<8 x float> %a, <8 x float> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rrkz_256
+  ;CHECK: vorps %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xa9,0x56,0xc1]
+  %res = call <8 x float> @llvm.x86.avx512.mask.or.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_or_ps_rm_256(<8 x float> %a, <8 x float>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_or_ps_rm_256
+  ;CHECK: vorps (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf1,0x7c,0x28,0x56,0x07]
+  %b = load <8 x float>, <8 x float>* %ptr_b
+  %res = call <8 x float> @llvm.x86.avx512.mask.or.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_or_ps_rmk_256(<8 x float> %a, <8 x float>* %ptr_b, <8 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rmk_256
+  ;CHECK: vorps (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x29,0x56,0x0f]
+  %b = load <8 x float>, <8 x float>* %ptr_b
+  %res = call <8 x float> @llvm.x86.avx512.mask.or.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_or_ps_rmkz_256(<8 x float> %a, <8 x float>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rmkz_256
+  ;CHECK: vorps (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xa9,0x56,0x07]
+  %b = load <8 x float>, <8 x float>* %ptr_b
+  %res = call <8 x float> @llvm.x86.avx512.mask.or.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_or_ps_rmb_256(<8 x float> %a, float* %ptr_b) {
+  ;CHECK-LABEL: test_mask_or_ps_rmb_256
+  ;CHECK: vorps (%rdi){1to8}, %ymm0, %ymm0  ## encoding: [0x62,0xf1,0x7c,0x38,0x56,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <8 x float> undef, float %q, i32 0
+  %b = shufflevector <8 x float> %vecinit.i, <8 x float> undef, <8 x i32> zeroinitializer
+  %res = call <8 x float> @llvm.x86.avx512.mask.or.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_or_ps_rmbk_256(<8 x float> %a, float* %ptr_b, <8 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rmbk_256
+  ;CHECK: vorps (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x39,0x56,0x0f]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <8 x float> undef, float %q, i32 0
+  %b = shufflevector <8 x float> %vecinit.i, <8 x float> undef, <8 x i32> zeroinitializer
+  %res = call <8 x float> @llvm.x86.avx512.mask.or.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_or_ps_rmbkz_256(<8 x float> %a, float* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rmbkz_256
+  ;CHECK: vorps (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xb9,0x56,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <8 x float> undef, float %q, i32 0
+  %b = shufflevector <8 x float> %vecinit.i, <8 x float> undef, <8 x i32> zeroinitializer
+  %res = call <8 x float> @llvm.x86.avx512.mask.or.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+declare <8 x float> @llvm.x86.avx512.mask.or.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
+
+define <16 x float> @test_mask_or_ps_rr_512(<16 x float> %a, <16 x float> %b) {
+  ;CHECK-LABEL: test_mask_or_ps_rr_512
+  ;CHECK: vorps %zmm1, %zmm0, %zmm0     ## encoding: [0x62,0xf1,0x7c,0x48,0x56,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.or.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 -1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_or_ps_rrk_512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rrk_512
+  ;CHECK: vorps %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7c,0x49,0x56,0xd1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.or.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_or_ps_rrkz_512(<16 x float> %a, <16 x float> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rrkz_512
+  ;CHECK: vorps %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xc9,0x56,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.or.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_or_ps_rm_512(<16 x float> %a, <16 x float>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_or_ps_rm_512
+  ;CHECK: vorps (%rdi), %zmm0, %zmm0    ## encoding: [0x62,0xf1,0x7c,0x48,0x56,0x07]
+  %b = load <16 x float>, <16 x float>* %ptr_b
+  %res = call <16 x float> @llvm.x86.avx512.mask.or.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 -1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_or_ps_rmk_512(<16 x float> %a, <16 x float>* %ptr_b, <16 x float> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rmk_512
+  ;CHECK: vorps (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x49,0x56,0x0f]
+  %b = load <16 x float>, <16 x float>* %ptr_b
+  %res = call <16 x float> @llvm.x86.avx512.mask.or.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_or_ps_rmkz_512(<16 x float> %a, <16 x float>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rmkz_512
+  ;CHECK: vorps (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xc9,0x56,0x07]
+  %b = load <16 x float>, <16 x float>* %ptr_b
+  %res = call <16 x float> @llvm.x86.avx512.mask.or.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_or_ps_rmb_512(<16 x float> %a, float* %ptr_b) {
+  ;CHECK-LABEL: test_mask_or_ps_rmb_512
+  ;CHECK: vorps (%rdi){1to16}, %zmm0, %zmm0  ## encoding: [0x62,0xf1,0x7c,0x58,0x56,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <16 x float> undef, float %q, i32 0
+  %b = shufflevector <16 x float> %vecinit.i, <16 x float> undef, <16 x i32> zeroinitializer
+  %res = call <16 x float> @llvm.x86.avx512.mask.or.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 -1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_or_ps_rmbk_512(<16 x float> %a, float* %ptr_b, <16 x float> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rmbk_512
+  ;CHECK: vorps (%rdi){1to16}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x59,0x56,0x0f]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <16 x float> undef, float %q, i32 0
+  %b = shufflevector <16 x float> %vecinit.i, <16 x float> undef, <16 x i32> zeroinitializer
+  %res = call <16 x float> @llvm.x86.avx512.mask.or.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_or_ps_rmbkz_512(<16 x float> %a, float* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_or_ps_rmbkz_512
+  ;CHECK: vorps (%rdi){1to16}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xd9,0x56,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <16 x float> undef, float %q, i32 0
+  %b = shufflevector <16 x float> %vecinit.i, <16 x float> undef, <16 x i32> zeroinitializer
+  %res = call <16 x float> @llvm.x86.avx512.mask.or.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 %mask)
+  ret <16 x float> %res
+}
+
+declare <16 x float> @llvm.x86.avx512.mask.or.ps.512(<16 x float>, <16 x float>, <16 x float>, i16)
+
+define <4 x float> @test_mask_xor_ps_rr_128(<4 x float> %a, <4 x float> %b) {
+  ;CHECK-LABEL: test_mask_xor_ps_rr_128
+  ;CHECK: vxorps  %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf1,0x7c,0x08,0x57,0xc1]
+  %res = call <4 x float> @llvm.x86.avx512.mask.xor.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_xor_ps_rrk_128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rrk_128
+  ;CHECK: vxorps %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7c,0x09,0x57,0xd1]
+  %res = call <4 x float> @llvm.x86.avx512.mask.xor.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_xor_ps_rrkz_128(<4 x float> %a, <4 x float> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rrkz_128
+  ;CHECK: vxorps %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0x89,0x57,0xc1]
+  %res = call <4 x float> @llvm.x86.avx512.mask.xor.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_xor_ps_rm_128(<4 x float> %a, <4 x float>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_xor_ps_rm_128
+  ;CHECK: vxorps (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf1,0x7c,0x08,0x57,0x07]
+  %b = load <4 x float>, <4 x float>* %ptr_b
+  %res = call <4 x float> @llvm.x86.avx512.mask.xor.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_xor_ps_rmk_128(<4 x float> %a, <4 x float>* %ptr_b, <4 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rmk_128
+  ;CHECK: vxorps (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x09,0x57,0x0f]
+  %b = load <4 x float>, <4 x float>* %ptr_b
+  %res = call <4 x float> @llvm.x86.avx512.mask.xor.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_xor_ps_rmkz_128(<4 x float> %a, <4 x float>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rmkz_128
+  ;CHECK: vxorps (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0x89,0x57,0x07]
+  %b = load <4 x float>, <4 x float>* %ptr_b
+  %res = call <4 x float> @llvm.x86.avx512.mask.xor.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_xor_ps_rmb_128(<4 x float> %a, float* %ptr_b) {
+  ;CHECK-LABEL: test_mask_xor_ps_rmb_128
+  ;CHECK: vxorps (%rdi){1to4}, %xmm0, %xmm0  ## encoding: [0x62,0xf1,0x7c,0x18,0x57,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
+  %b = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
+  %res = call <4 x float> @llvm.x86.avx512.mask.xor.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_xor_ps_rmbk_128(<4 x float> %a, float* %ptr_b, <4 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rmbk_128
+  ;CHECK: vxorps (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x19,0x57,0x0f]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
+  %b = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
+  %res = call <4 x float> @llvm.x86.avx512.mask.xor.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> %passThru, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mask_xor_ps_rmbkz_128(<4 x float> %a, float* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rmbkz_128
+  ;CHECK: vxorps (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0x99,0x57,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
+  %b = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
+  %res = call <4 x float> @llvm.x86.avx512.mask.xor.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+declare <4 x float> @llvm.x86.avx512.mask.xor.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
+
+define <8 x float> @test_mask_xor_ps_rr_256(<8 x float> %a, <8 x float> %b) {
+  ;CHECK-LABEL: test_mask_xor_ps_rr_256
+  ;CHECK: vxorps %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf1,0x7c,0x28,0x57,0xc1]
+  %res = call <8 x float> @llvm.x86.avx512.mask.xor.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_xor_ps_rrk_256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rrk_256
+  ;CHECK: vxorps %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7c,0x29,0x57,0xd1]
+  %res = call <8 x float> @llvm.x86.avx512.mask.xor.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_xor_ps_rrkz_256(<8 x float> %a, <8 x float> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rrkz_256
+  ;CHECK: vxorps %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xa9,0x57,0xc1]
+  %res = call <8 x float> @llvm.x86.avx512.mask.xor.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_xor_ps_rm_256(<8 x float> %a, <8 x float>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_xor_ps_rm_256
+  ;CHECK: vxorps (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf1,0x7c,0x28,0x57,0x07]
+  %b = load <8 x float>, <8 x float>* %ptr_b
+  %res = call <8 x float> @llvm.x86.avx512.mask.xor.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_xor_ps_rmk_256(<8 x float> %a, <8 x float>* %ptr_b, <8 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rmk_256
+  ;CHECK: vxorps (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x29,0x57,0x0f]
+  %b = load <8 x float>, <8 x float>* %ptr_b
+  %res = call <8 x float> @llvm.x86.avx512.mask.xor.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_xor_ps_rmkz_256(<8 x float> %a, <8 x float>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rmkz_256
+  ;CHECK: vxorps (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xa9,0x57,0x07]
+  %b = load <8 x float>, <8 x float>* %ptr_b
+  %res = call <8 x float> @llvm.x86.avx512.mask.xor.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_xor_ps_rmb_256(<8 x float> %a, float* %ptr_b) {
+  ;CHECK-LABEL: test_mask_xor_ps_rmb_256
+  ;CHECK: vxorps (%rdi){1to8}, %ymm0, %ymm0  ## encoding: [0x62,0xf1,0x7c,0x38,0x57,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <8 x float> undef, float %q, i32 0
+  %b = shufflevector <8 x float> %vecinit.i, <8 x float> undef, <8 x i32> zeroinitializer
+  %res = call <8 x float> @llvm.x86.avx512.mask.xor.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_xor_ps_rmbk_256(<8 x float> %a, float* %ptr_b, <8 x float> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rmbk_256
+  ;CHECK: vxorps (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x39,0x57,0x0f]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <8 x float> undef, float %q, i32 0
+  %b = shufflevector <8 x float> %vecinit.i, <8 x float> undef, <8 x i32> zeroinitializer
+  %res = call <8 x float> @llvm.x86.avx512.mask.xor.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %passThru, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mask_xor_ps_rmbkz_256(<8 x float> %a, float* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rmbkz_256
+  ;CHECK: vxorps (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xb9,0x57,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <8 x float> undef, float %q, i32 0
+  %b = shufflevector <8 x float> %vecinit.i, <8 x float> undef, <8 x i32> zeroinitializer
+  %res = call <8 x float> @llvm.x86.avx512.mask.xor.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+declare <8 x float> @llvm.x86.avx512.mask.xor.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
+
+define <16 x float> @test_mask_xor_ps_rr_512(<16 x float> %a, <16 x float> %b) {
+  ;CHECK-LABEL: test_mask_xor_ps_rr_512
+  ;CHECK: vxorps %zmm1, %zmm0, %zmm0     ## encoding: [0x62,0xf1,0x7c,0x48,0x57,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.xor.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 -1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_xor_ps_rrk_512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rrk_512
+  ;CHECK: vxorps %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7c,0x49,0x57,0xd1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.xor.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_xor_ps_rrkz_512(<16 x float> %a, <16 x float> %b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rrkz_512
+  ;CHECK: vxorps %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xc9,0x57,0xc1]
+  %res = call <16 x float> @llvm.x86.avx512.mask.xor.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_xor_ps_rm_512(<16 x float> %a, <16 x float>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_xor_ps_rm_512
+  ;CHECK: vxorps (%rdi), %zmm0, %zmm0    ## encoding: [0x62,0xf1,0x7c,0x48,0x57,0x07]
+  %b = load <16 x float>, <16 x float>* %ptr_b
+  %res = call <16 x float> @llvm.x86.avx512.mask.xor.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 -1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_xor_ps_rmk_512(<16 x float> %a, <16 x float>* %ptr_b, <16 x float> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rmk_512
+  ;CHECK: vxorps (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x49,0x57,0x0f]
+  %b = load <16 x float>, <16 x float>* %ptr_b
+  %res = call <16 x float> @llvm.x86.avx512.mask.xor.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_xor_ps_rmkz_512(<16 x float> %a, <16 x float>* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rmkz_512
+  ;CHECK: vxorps (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xc9,0x57,0x07]
+  %b = load <16 x float>, <16 x float>* %ptr_b
+  %res = call <16 x float> @llvm.x86.avx512.mask.xor.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_xor_ps_rmb_512(<16 x float> %a, float* %ptr_b) {
+  ;CHECK-LABEL: test_mask_xor_ps_rmb_512
+  ;CHECK: vxorps (%rdi){1to16}, %zmm0, %zmm0  ## encoding: [0x62,0xf1,0x7c,0x58,0x57,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <16 x float> undef, float %q, i32 0
+  %b = shufflevector <16 x float> %vecinit.i, <16 x float> undef, <16 x i32> zeroinitializer
+  %res = call <16 x float> @llvm.x86.avx512.mask.xor.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 -1)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_xor_ps_rmbk_512(<16 x float> %a, float* %ptr_b, <16 x float> %passThru, i16 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rmbk_512
+  ;CHECK: vxorps (%rdi){1to16}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x59,0x57,0x0f]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <16 x float> undef, float %q, i32 0
+  %b = shufflevector <16 x float> %vecinit.i, <16 x float> undef, <16 x i32> zeroinitializer
+  %res = call <16 x float> @llvm.x86.avx512.mask.xor.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %passThru, i16 %mask)
+  ret <16 x float> %res
+}
+
+define <16 x float> @test_mask_xor_ps_rmbkz_512(<16 x float> %a, float* %ptr_b, i16 %mask) {
+  ;CHECK-LABEL: test_mask_xor_ps_rmbkz_512
+  ;CHECK: vxorps (%rdi){1to16}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xd9,0x57,0x07]
+  %q = load float, float* %ptr_b
+  %vecinit.i = insertelement <16 x float> undef, float %q, i32 0
+  %b = shufflevector <16 x float> %vecinit.i, <16 x float> undef, <16 x i32> zeroinitializer
+  %res = call <16 x float> @llvm.x86.avx512.mask.xor.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> zeroinitializer, i16 %mask)
+  ret <16 x float> %res
+}
+
+declare <16 x float> @llvm.x86.avx512.mask.xor.ps.512(<16 x float>, <16 x float>, <16 x float>, i16)
\ No newline at end of file
diff --git a/test/CodeGen/X86/avx512er-intrinsics.ll b/test/CodeGen/X86/avx512er-intrinsics.ll
index fa4352e64dce..827a56d76ae1 100644
--- a/test/CodeGen/X86/avx512er-intrinsics.ll
+++ b/test/CodeGen/X86/avx512er-intrinsics.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=knl --show-mc-encoding| FileCheck %s
 
 define <16 x float> @test_rsqrt28_ps(<16 x float> %a0) {
-  ; CHECK: vrsqrt28ps %zmm0, %zmm0 {sae} # encoding: [0x62,0xf2,0x7d,0x18,0xcc,0xc0]
+  ; CHECK: vrsqrt28ps {sae}, %zmm0, %zmm0 # encoding: [0x62,0xf2,0x7d,0x18,0xcc,0xc0]
   %res = call <16 x float> @llvm.x86.avx512.rsqrt28.ps(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1, i32 8)
   ret <16 x float> %res
 }
 
 define <16 x float> @test1_rsqrt28_ps(<16 x float> %a0, <16 x float> %a1) {
   ; CHECK: kmovw
-  ; CHECK: vrsqrt28ps %zmm0, %zmm1 {%k1}{sae} # encoding: [0x62,0xf2,0x7d,0x19,0xcc,0xc8]
+  ; CHECK: vrsqrt28ps {sae}, %zmm0, %zmm1 {%k1} # encoding: [0x62,0xf2,0x7d,0x19,0xcc,0xc8]
   %res = call <16 x float> @llvm.x86.avx512.rsqrt28.ps(<16 x float> %a0, <16 x float> %a1, i16 6, i32 8)
   ret <16 x float> %res
 }
@@ -27,7 +27,7 @@ define <16 x float> @test3_rsqrt28_ps(<16 x float> %a0) {
 }
 
 define <16 x float> @test4_rsqrt28_ps(<16 x float> %a0) {
-  ; CHECK: vrsqrt28ps %zmm0, %zmm0 {%k1} {z}{sae} # encoding: [0x62,0xf2,0x7d,0x99,0xcc,0xc0]
+  ; CHECK: vrsqrt28ps {sae}, %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf2,0x7d,0x99,0xcc,0xc0]
   %res = call <16 x float> @llvm.x86.avx512.rsqrt28.ps(<16 x float> %a0, <16 x float> undef, i16 6, i32 8) 
   ret <16 x float> %res
 }
@@ -36,61 +36,61 @@ define <16 x float> @test4_rsqrt28_ps(<16 x float> %a0) {
 declare <16 x float> @llvm.x86.avx512.rsqrt28.ps(<16 x float>, <16 x float>, i16, i32) nounwind readnone
 
 define <16 x float> @test_rcp28_ps_512(<16 x float> %a0) {
-  ; CHECK: vrcp28ps %zmm0, %zmm0 {sae} # encoding: [0x62,0xf2,0x7d,0x18,0xca,0xc0]
+  ; CHECK: vrcp28ps {sae}, %zmm0, %zmm0 # encoding: [0x62,0xf2,0x7d,0x18,0xca,0xc0]
   %res = call <16 x float> @llvm.x86.avx512.rcp28.ps(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1, i32 8)
   ret <16 x float> %res
 }
 declare <16 x float> @llvm.x86.avx512.rcp28.ps(<16 x float>, <16 x float>, i16, i32) nounwind readnone
 
 define <8 x double> @test_rcp28_pd_512(<8 x double> %a0) {
-  ; CHECK: vrcp28pd %zmm0, %zmm0 {sae} # encoding: [0x62,0xf2,0xfd,0x18,0xca,0xc0]
+  ; CHECK: vrcp28pd {sae}, %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x18,0xca,0xc0]
   %res = call <8 x double> @llvm.x86.avx512.rcp28.pd(<8 x double> %a0, <8 x double> zeroinitializer, i8 -1, i32 8) 
   ret <8 x double> %res
 }
 declare <8 x double> @llvm.x86.avx512.rcp28.pd(<8 x double>, <8 x double>, i8, i32) nounwind readnone
 
 define <16 x float> @test_exp2_ps_512(<16 x float> %a0) {
-  ; CHECK: vexp2ps %zmm0, %zmm0 {sae}      # encoding: [0x62,0xf2,0x7d,0x18,0xc8,0xc0]
+  ; CHECK: vexp2ps {sae}, %zmm0, %zmm0     # encoding: [0x62,0xf2,0x7d,0x18,0xc8,0xc0]
   %res = call <16 x float> @llvm.x86.avx512.exp2.ps(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1, i32 8)
   ret <16 x float> %res
 }
 declare <16 x float> @llvm.x86.avx512.exp2.ps(<16 x float>, <16 x float>, i16, i32) nounwind readnone
 
 define <8 x double> @test_exp2_pd_512(<8 x double> %a0) {
-  ; CHECK: vexp2pd %zmm0, %zmm0 {sae}      # encoding: [0x62,0xf2,0xfd,0x18,0xc8,0xc0]
+  ; CHECK: vexp2pd {sae}, %zmm0, %zmm0      # encoding: [0x62,0xf2,0xfd,0x18,0xc8,0xc0]
   %res = call <8 x double> @llvm.x86.avx512.exp2.pd(<8 x double> %a0, <8 x double> zeroinitializer, i8 -1, i32 8)
   ret <8 x double> %res
 }
 declare <8 x double> @llvm.x86.avx512.exp2.pd(<8 x double>, <8 x double>, i8, i32) nounwind readnone
 
 define <4 x float> @test_rsqrt28_ss(<4 x float> %a0) {
-  ; CHECK: vrsqrt28ss %xmm0, %xmm0, %xmm0 {sae} # encoding: [0x62,0xf2,0x7d,0x18,0xcd,0xc0]
+  ; CHECK: vrsqrt28ss {sae}, %xmm0, %xmm0, %xmm0 # encoding: [0x62,0xf2,0x7d,0x18,0xcd,0xc0]
   %res = call <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 -1, i32 8) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
 declare <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone
 
 define <4 x float> @test_rcp28_ss(<4 x float> %a0) {
-  ; CHECK: vrcp28ss %xmm0, %xmm0, %xmm0 {sae} # encoding: [0x62,0xf2,0x7d,0x18,0xcb,0xc0]
+  ; CHECK: vrcp28ss {sae}, %xmm0, %xmm0, %xmm0 # encoding: [0x62,0xf2,0x7d,0x18,0xcb,0xc0]
   %res = call <4 x float> @llvm.x86.avx512.rcp28.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 -1, i32 8) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
 declare <4 x float> @llvm.x86.avx512.rcp28.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone
 
 define <4 x float> @test_rsqrt28_ss_maskz(<4 x float> %a0) {
-  ; CHECK: vrsqrt28ss %xmm0, %xmm0, %xmm0 {%k1} {z}{sae} # encoding: [0x62,0xf2,0x7d,0x99,0xcd,0xc0]
+  ; CHECK: vrsqrt28ss {sae}, %xmm0, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0x7d,0x99,0xcd,0xc0]
   %res = call <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 7, i32 8) ; 
   ret <4 x float> %res
 }
 
 define <4 x float> @test_rsqrt28_ss_mask(<4 x float> %a0, <4 x float> %b0, <4 x float> %c0) {
-  ; CHECK: vrsqrt28ss %xmm1, %xmm0, %xmm2 {%k1}{sae} # encoding: [0x62,0xf2,0x7d,0x19,0xcd,0xd1]
+  ; CHECK: vrsqrt28ss {sae}, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf2,0x7d,0x19,0xcd,0xd1]
   %res = call <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float> %a0, <4 x float> %b0, <4 x float> %c0, i8 7, i32 8) ;
   ret <4 x float> %res
 }
 
 define <2 x double> @test_rsqrt28_sd_maskz(<2 x double> %a0) {
-  ; CHECK: vrsqrt28sd %xmm0, %xmm0, %xmm0 {%k1} {z}{sae} # encoding: [0x62,0xf2,0xfd,0x99,0xcd,0xc0]
+  ; CHECK: vrsqrt28sd {sae}, %xmm0, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0xfd,0x99,0xcd,0xc0]
   %res = call <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double> %a0, <2 x double> %a0, <2 x double> zeroinitializer, i8 7, i32 8) ; 
   ret <2 x double> %res
 }
@@ -99,7 +99,7 @@ declare <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double>, <2 x double>, <2
 
 define <2 x double> @test_rsqrt28_sd_maskz_mem(<2 x double> %a0, double* %ptr ) {
   ; CHECK: vrsqrt28sd (%rdi), %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0xfd,0x89,0xcd,0x07]
-  %mem = load double * %ptr, align 8
+  %mem = load double , double * %ptr, align 8
   %mem_v = insertelement <2 x double> undef, double %mem, i32 0
   %res = call <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double> %a0, <2 x double> %mem_v, <2 x double> zeroinitializer, i8 7, i32 4) ; 
   ret <2 x double> %res
@@ -107,8 +107,8 @@ define <2 x double> @test_rsqrt28_sd_maskz_mem(<2 x double> %a0, double* %ptr )
 
 define <2 x double> @test_rsqrt28_sd_maskz_mem_offset(<2 x double> %a0, double* %ptr ) {
   ; CHECK: vrsqrt28sd 144(%rdi), %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0xfd,0x89,0xcd,0x47,0x12]
-  %ptr1 = getelementptr double* %ptr, i32 18
-  %mem = load double * %ptr1, align 8
+  %ptr1 = getelementptr double, double* %ptr, i32 18
+  %mem = load double , double * %ptr1, align 8
   %mem_v = insertelement <2 x double> undef, double %mem, i32 0
   %res = call <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double> %a0, <2 x double> %mem_v, <2 x double> zeroinitializer, i8 7, i32 4) ;
   ret <2 x double> %res
diff --git a/test/CodeGen/X86/avx512vl-arith.ll b/test/CodeGen/X86/avx512vl-arith.ll
index 1f7da7814cc9..ef01d8656dac 100644
--- a/test/CodeGen/X86/avx512vl-arith.ll
+++ b/test/CodeGen/X86/avx512vl-arith.ll
@@ -14,7 +14,7 @@ define <4 x i64> @vpaddq256_test(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
 ; CHECK: vpaddq (%rdi), %ymm{{.*}}
 ; CHECK: ret
 define <4 x i64> @vpaddq256_fold_test(<4 x i64> %i, <4 x i64>* %j) nounwind {
-  %tmp = load <4 x i64>* %j, align 4
+  %tmp = load <4 x i64>, <4 x i64>* %j, align 4
   %x = add <4 x i64> %i, %tmp
   ret <4 x i64> %x
 }
@@ -31,7 +31,7 @@ define <4 x i64> @vpaddq256_broadcast_test(<4 x i64> %i) nounwind {
 ; CHECK: vpaddq (%rdi){1to4}, %ymm{{.*}}
 ; CHECK: ret
 define <4 x i64> @vpaddq256_broadcast2_test(<4 x i64> %i, i64* %j.ptr) nounwind {
-  %j = load i64* %j.ptr
+  %j = load i64, i64* %j.ptr
   %j.0 = insertelement <4 x i64> undef, i64 %j, i32 0
   %j.v = shufflevector <4 x i64> %j.0, <4 x i64> undef, <4 x i32> zeroinitializer
   %x = add <4 x i64> %i, %j.v
@@ -50,7 +50,7 @@ define <8 x i32> @vpaddd256_test(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
 ; CHECK: vpaddd (%rdi), %ymm{{.*}}
 ; CHECK: ret
 define <8 x i32> @vpaddd256_fold_test(<8 x i32> %i, <8 x i32>* %j) nounwind {
-  %tmp = load <8 x i32>* %j, align 4
+  %tmp = load <8 x i32>, <8 x i32>* %j, align 4
   %x = add <8 x i32> %i, %tmp
   ret <8 x i32> %x
 }
@@ -88,7 +88,7 @@ define <8 x i32> @vpaddd256_maskz_test(<8 x i32> %i, <8 x i32> %j, <8 x i32> %ma
 ; CHECK: ret
 define <8 x i32> @vpaddd256_mask_fold_test(<8 x i32> %i, <8 x i32>* %j.ptr, <8 x i32> %mask1) nounwind readnone {
   %mask = icmp ne <8 x i32> %mask1, zeroinitializer
-  %j = load <8 x i32>* %j.ptr
+  %j = load <8 x i32>, <8 x i32>* %j.ptr
   %x = add <8 x i32> %i, %j
   %r = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %i
   ret <8 x i32> %r
@@ -109,7 +109,7 @@ define <8 x i32> @vpaddd256_mask_broadcast_test(<8 x i32> %i, <8 x i32> %mask1)
 ; CHECK: ret
 define <8 x i32> @vpaddd256_maskz_fold_test(<8 x i32> %i, <8 x i32>* %j.ptr, <8 x i32> %mask1) nounwind readnone {
   %mask = icmp ne <8 x i32> %mask1, zeroinitializer
-  %j = load <8 x i32>* %j.ptr
+  %j = load <8 x i32>, <8 x i32>* %j.ptr
   %x = add <8 x i32> %i, %j
   %r = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer
   ret <8 x i32> %r
@@ -341,7 +341,7 @@ define <4 x double> @test_mask_fold_vaddpd_256(<4 x double> %dst, <4 x double> %
                                          <4 x double>* %j,  <4 x i64> %mask1)
                                          nounwind {
   %mask = icmp ne <4 x i64> %mask1, zeroinitializer
-  %tmp = load <4 x double>* %j
+  %tmp = load <4 x double>, <4 x double>* %j
   %x = fadd <4 x double> %i, %tmp
   %r = select <4 x i1> %mask, <4 x double> %x, <4 x double> %dst
   ret <4 x double> %r
@@ -353,7 +353,7 @@ define <4 x double> @test_mask_fold_vaddpd_256(<4 x double> %dst, <4 x double> %
 define <4 x double> @test_maskz_fold_vaddpd_256(<4 x double> %i, <4 x double>* %j,
                                           <4 x i64> %mask1) nounwind {
   %mask = icmp ne <4 x i64> %mask1, zeroinitializer
-  %tmp = load <4 x double>* %j
+  %tmp = load <4 x double>, <4 x double>* %j
   %x = fadd <4 x double> %i, %tmp
   %r = select <4 x i1> %mask, <4 x double> %x, <4 x double> zeroinitializer
   ret <4 x double> %r
@@ -363,7 +363,7 @@ define <4 x double> @test_maskz_fold_vaddpd_256(<4 x double> %i, <4 x double>* %
 ; CHECK: vaddpd (%rdi){1to4}, %ymm{{.*}}
 ; CHECK: ret
 define <4 x double> @test_broadcast2_vaddpd_256(<4 x double> %i, double* %j) nounwind {
-  %tmp = load double* %j
+  %tmp = load double, double* %j
   %b = insertelement <4 x double> undef, double %tmp, i32 0
   %c = shufflevector <4 x double> %b, <4 x double> undef,
                      <4 x i32> zeroinitializer
@@ -377,7 +377,7 @@ define <4 x double> @test_broadcast2_vaddpd_256(<4 x double> %i, double* %j) nou
 define <4 x double> @test_mask_broadcast_vaddpd_256(<4 x double> %dst, <4 x double> %i,
                                           double* %j, <4 x i64> %mask1) nounwind {
   %mask = icmp ne <4 x i64> %mask1, zeroinitializer
-  %tmp = load double* %j
+  %tmp = load double, double* %j
   %b = insertelement <4 x double> undef, double %tmp, i32 0
   %c = shufflevector <4 x double> %b, <4 x double> undef,
                      <4 x i32> zeroinitializer
@@ -392,7 +392,7 @@ define <4 x double> @test_mask_broadcast_vaddpd_256(<4 x double> %dst, <4 x doub
 define <4 x double> @test_maskz_broadcast_vaddpd_256(<4 x double> %i, double* %j,
                                            <4 x i64> %mask1) nounwind {
   %mask = icmp ne <4 x i64> %mask1, zeroinitializer
-  %tmp = load double* %j
+  %tmp = load double, double* %j
   %b = insertelement <4 x double> undef, double %tmp, i32 0
   %c = shufflevector <4 x double> %b, <4 x double> undef,
                      <4 x i32> zeroinitializer
@@ -415,7 +415,7 @@ define <2 x i64> @vpaddq128_test(<2 x i64> %i, <2 x i64> %j) nounwind readnone {
 ; CHECK: vpaddq (%rdi), %xmm{{.*}}
 ; CHECK: ret
 define <2 x i64> @vpaddq128_fold_test(<2 x i64> %i, <2 x i64>* %j) nounwind {
-  %tmp = load <2 x i64>* %j, align 4
+  %tmp = load <2 x i64>, <2 x i64>* %j, align 4
   %x = add <2 x i64> %i, %tmp
   ret <2 x i64> %x
 }
@@ -424,7 +424,7 @@ define <2 x i64> @vpaddq128_fold_test(<2 x i64> %i, <2 x i64>* %j) nounwind {
 ; CHECK: vpaddq (%rdi){1to2}, %xmm{{.*}}
 ; CHECK: ret
 define <2 x i64> @vpaddq128_broadcast2_test(<2 x i64> %i, i64* %j) nounwind {
-  %tmp = load i64* %j
+  %tmp = load i64, i64* %j
   %j.0 = insertelement <2 x i64> undef, i64 %tmp, i32 0
   %j.1 = insertelement <2 x i64> %j.0, i64 %tmp, i32 1
   %x = add <2 x i64> %i, %j.1
@@ -443,7 +443,7 @@ define <4 x i32> @vpaddd128_test(<4 x i32> %i, <4 x i32> %j) nounwind readnone {
 ; CHECK: vpaddd (%rdi), %xmm{{.*}}
 ; CHECK: ret
 define <4 x i32> @vpaddd128_fold_test(<4 x i32> %i, <4 x i32>* %j) nounwind {
-  %tmp = load <4 x i32>* %j, align 4
+  %tmp = load <4 x i32>, <4 x i32>* %j, align 4
   %x = add <4 x i32> %i, %tmp
   ret <4 x i32> %x
 }
@@ -481,7 +481,7 @@ define <4 x i32> @vpaddd128_maskz_test(<4 x i32> %i, <4 x i32> %j, <4 x i32> %ma
 ; CHECK: ret
 define <4 x i32> @vpaddd128_mask_fold_test(<4 x i32> %i, <4 x i32>* %j.ptr, <4 x i32> %mask1) nounwind readnone {
   %mask = icmp ne <4 x i32> %mask1, zeroinitializer
-  %j = load <4 x i32>* %j.ptr
+  %j = load <4 x i32>, <4 x i32>* %j.ptr
   %x = add <4 x i32> %i, %j
   %r = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %i
   ret <4 x i32> %r
@@ -502,7 +502,7 @@ define <4 x i32> @vpaddd128_mask_broadcast_test(<4 x i32> %i, <4 x i32> %mask1)
 ; CHECK: ret
 define <4 x i32> @vpaddd128_maskz_fold_test(<4 x i32> %i, <4 x i32>* %j.ptr, <4 x i32> %mask1) nounwind readnone {
   %mask = icmp ne <4 x i32> %mask1, zeroinitializer
-  %j = load <4 x i32>* %j.ptr
+  %j = load <4 x i32>, <4 x i32>* %j.ptr
   %x = add <4 x i32> %i, %j
   %r = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> zeroinitializer
   ret <4 x i32> %r
@@ -735,7 +735,7 @@ define <2 x double> @test_mask_fold_vaddpd_128(<2 x double> %dst, <2 x double> %
                                          <2 x double>* %j,  <2 x i64> %mask1)
                                          nounwind {
   %mask = icmp ne <2 x i64> %mask1, zeroinitializer
-  %tmp = load <2 x double>* %j
+  %tmp = load <2 x double>, <2 x double>* %j
   %x = fadd <2 x double> %i, %tmp
   %r = select <2 x i1> %mask, <2 x double> %x, <2 x double> %dst
   ret <2 x double> %r
@@ -747,7 +747,7 @@ define <2 x double> @test_mask_fold_vaddpd_128(<2 x double> %dst, <2 x double> %
 define <2 x double> @test_maskz_fold_vaddpd_128(<2 x double> %i, <2 x double>* %j,
                                           <2 x i64> %mask1) nounwind {
   %mask = icmp ne <2 x i64> %mask1, zeroinitializer
-  %tmp = load <2 x double>* %j
+  %tmp = load <2 x double>, <2 x double>* %j
   %x = fadd <2 x double> %i, %tmp
   %r = select <2 x i1> %mask, <2 x double> %x, <2 x double> zeroinitializer
   ret <2 x double> %r
@@ -757,7 +757,7 @@ define <2 x double> @test_maskz_fold_vaddpd_128(<2 x double> %i, <2 x double>* %
 ; CHECK: vaddpd (%rdi){1to2}, %xmm{{.*}}
 ; CHECK: ret
 define <2 x double> @test_broadcast2_vaddpd_128(<2 x double> %i, double* %j) nounwind {
-  %tmp = load double* %j
+  %tmp = load double, double* %j
   %j.0 = insertelement <2 x double> undef, double %tmp, i64 0
   %j.1 = insertelement <2 x double> %j.0, double %tmp, i64 1
   %x = fadd <2 x double> %j.1, %i
@@ -771,7 +771,7 @@ define <2 x double> @test_mask_broadcast_vaddpd_128(<2 x double> %dst, <2 x doub
                                           double* %j, <2 x i64> %mask1)
                                           nounwind {
   %mask = icmp ne <2 x i64> %mask1, zeroinitializer
-  %tmp = load double* %j
+  %tmp = load double, double* %j
   %j.0 = insertelement <2 x double> undef, double %tmp, i64 0
   %j.1 = insertelement <2 x double> %j.0, double %tmp, i64 1
   %x = fadd <2 x double> %j.1, %i
@@ -785,7 +785,7 @@ define <2 x double> @test_mask_broadcast_vaddpd_128(<2 x double> %dst, <2 x doub
 define <2 x double> @test_maskz_broadcast_vaddpd_128(<2 x double> %i, double* %j,
                                            <2 x i64> %mask1) nounwind {
   %mask = icmp ne <2 x i64> %mask1, zeroinitializer
-  %tmp = load double* %j
+  %tmp = load double, double* %j
   %j.0 = insertelement <2 x double> undef, double %tmp, i64 0
   %j.1 = insertelement <2 x double> %j.0, double %tmp, i64 1
   %x = fadd <2 x double> %j.1, %i
diff --git a/test/CodeGen/X86/avx512vl-intrinsics.ll b/test/CodeGen/X86/avx512vl-intrinsics.ll
index d349f4f53786..fd76ed5d0dbd 100644
--- a/test/CodeGen/X86/avx512vl-intrinsics.ll
+++ b/test/CodeGen/X86/avx512vl-intrinsics.ll
@@ -805,7 +805,7 @@ define <4 x double> @test_x86_mask_blend_pd_256(i8 %a0, <4 x double> %a1, <4 x d
 define <4 x double> @test_x86_mask_blend_pd_256_memop(<4 x double> %a, <4 x double>* %ptr, i8 %mask) {
   ; CHECK-LABEL: test_x86_mask_blend_pd_256_memop
   ; CHECK: vblendmpd (%
-  %b = load <4 x double>* %ptr
+  %b = load <4 x double>, <4 x double>* %ptr
   %res = call <4 x double> @llvm.x86.avx512.mask.blend.pd.256(<4 x double> %a, <4 x double> %b, i8 %mask) ; <<4 x double>> [#uses=1]
   ret <4 x double> %res
 }
@@ -843,7 +843,7 @@ define <2 x double> @test_x86_mask_blend_pd_128(i8 %a0, <2 x double> %a1, <2 x d
 define <2 x double> @test_x86_mask_blend_pd_128_memop(<2 x double> %a, <2 x double>* %ptr, i8 %mask) {
   ; CHECK-LABEL: test_x86_mask_blend_pd_128_memop
   ; CHECK: vblendmpd (%
-  %b = load <2 x double>* %ptr
+  %b = load <2 x double>, <2 x double>* %ptr
   %res = call <2 x double> @llvm.x86.avx512.mask.blend.pd.128(<2 x double> %a, <2 x double> %b, i8 %mask) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
@@ -862,3 +862,1694 @@ define <2 x i64> @test_x86_mask_blend_q_128(i8 %a0, <2 x i64> %a1, <2 x i64> %a2
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.avx512.mask.blend.q.128(<2 x i64>, <2 x i64>, i8) nounwind readonly
+
+
+define < 2 x i64> @test_mask_mul_epi32_rr_128(< 4 x i32> %a, < 4 x i32> %b) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rr_128
+  ;CHECK: vpmuldq %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf2,0xfd,0x08,0x28,0xc1]
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rrk_128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rrk_128
+  ;CHECK: vpmuldq %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf2,0xfd,0x09,0x28,0xd1]
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rrkz_128(< 4 x i32> %a, < 4 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rrkz_128
+  ;CHECK: vpmuldq %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0x89,0x28,0xc1]
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rm_128(< 4 x i32> %a, < 4 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rm_128
+  ;CHECK: vpmuldq (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf2,0xfd,0x08,0x28,0x07]
+  %b = load < 4 x i32>, < 4 x i32>* %ptr_b
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rmk_128(< 4 x i32> %a, < 4 x i32>* %ptr_b, < 2 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rmk_128
+  ;CHECK: vpmuldq (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x09,0x28,0x0f]
+  %b = load < 4 x i32>, < 4 x i32>* %ptr_b
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rmkz_128(< 4 x i32> %a, < 4 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rmkz_128
+  ;CHECK: vpmuldq (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0x89,0x28,0x07]
+  %b = load < 4 x i32>, < 4 x i32>* %ptr_b
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rmb_128(< 4 x i32> %a, i64* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rmb_128
+  ;CHECK: vpmuldq (%rdi){1to2}, %xmm0, %xmm0  ## encoding: [0x62,0xf2,0xfd,0x18,0x28,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, <2 x i32> zeroinitializer
+  %b = bitcast < 2 x i64> %b64 to < 4 x i32>
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rmbk_128(< 4 x i32> %a, i64* %ptr_b, < 2 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rmbk_128
+  ;CHECK: vpmuldq (%rdi){1to2}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x19,0x28,0x0f]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, <2 x i32> zeroinitializer
+  %b = bitcast < 2 x i64> %b64 to < 4 x i32>
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rmbkz_128(< 4 x i32> %a, i64* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rmbkz_128
+  ;CHECK: vpmuldq (%rdi){1to2}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0x99,0x28,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, < 2 x i32> zeroinitializer
+  %b = bitcast < 2 x i64> %b64 to < 4 x i32>
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
+  ret < 2 x i64> %res
+}
+
+declare < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32>, < 4 x i32>, < 2 x i64>, i8)
+
+define < 4 x i64> @test_mask_mul_epi32_rr_256(< 8 x i32> %a, < 8 x i32> %b) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rr_256
+  ;CHECK: vpmuldq %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf2,0xfd,0x28,0x28,0xc1]
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rrk_256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rrk_256
+  ;CHECK: vpmuldq %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x28,0xd1]
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rrkz_256(< 8 x i32> %a, < 8 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rrkz_256
+  ;CHECK: vpmuldq %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xa9,0x28,0xc1]
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rm_256(< 8 x i32> %a, < 8 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rm_256
+  ;CHECK: vpmuldq (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf2,0xfd,0x28,0x28,0x07]
+  %b = load < 8 x i32>, < 8 x i32>* %ptr_b
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rmk_256(< 8 x i32> %a, < 8 x i32>* %ptr_b, < 4 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rmk_256
+  ;CHECK: vpmuldq (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x28,0x0f]
+  %b = load < 8 x i32>, < 8 x i32>* %ptr_b
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rmkz_256(< 8 x i32> %a, < 8 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rmkz_256
+  ;CHECK: vpmuldq (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xa9,0x28,0x07]
+  %b = load < 8 x i32>, < 8 x i32>* %ptr_b
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rmb_256(< 8 x i32> %a, i64* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rmb_256
+  ;CHECK: vpmuldq (%rdi){1to4}, %ymm0, %ymm0  ## encoding: [0x62,0xf2,0xfd,0x38,0x28,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
+  %b = bitcast < 4 x i64> %b64 to < 8 x i32>
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rmbk_256(< 8 x i32> %a, i64* %ptr_b, < 4 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rmbk_256
+  ;CHECK: vpmuldq (%rdi){1to4}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x39,0x28,0x0f]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
+  %b = bitcast < 4 x i64> %b64 to < 8 x i32>
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rmbkz_256(< 8 x i32> %a, i64* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epi32_rmbkz_256
+  ;CHECK: vpmuldq (%rdi){1to4}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xb9,0x28,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
+  %b = bitcast < 4 x i64> %b64 to < 8 x i32>
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
+  ret < 4 x i64> %res
+}
+
+declare < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32>, < 8 x i32>, < 4 x i64>, i8)
+
+define < 2 x i64> @test_mask_mul_epu32_rr_128(< 4 x i32> %a, < 4 x i32> %b) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rr_128
+  ;CHECK: vpmuludq %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xf4,0xc1]
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rrk_128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rrk_128
+  ;CHECK: vpmuludq %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x09,0xf4,0xd1]
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rrkz_128(< 4 x i32> %a, < 4 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rrkz_128
+  ;CHECK: vpmuludq %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x89,0xf4,0xc1]
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rm_128(< 4 x i32> %a, < 4 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rm_128
+  ;CHECK: vpmuludq (%rdi), %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xf4,0x07]
+  %b = load < 4 x i32>, < 4 x i32>* %ptr_b
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rmk_128(< 4 x i32> %a, < 4 x i32>* %ptr_b, < 2 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rmk_128
+  ;CHECK: vpmuludq (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x09,0xf4,0x0f]
+  %b = load < 4 x i32>, < 4 x i32>* %ptr_b
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rmkz_128(< 4 x i32> %a, < 4 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rmkz_128
+  ;CHECK: vpmuludq (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x89,0xf4,0x07]
+  %b = load < 4 x i32>, < 4 x i32>* %ptr_b
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rmb_128(< 4 x i32> %a, i64* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rmb_128
+  ;CHECK: vpmuludq (%rdi){1to2}, %xmm0, %xmm0  ## encoding: [0x62,0xf1,0xfd,0x18,0xf4,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, <2 x i32> zeroinitializer
+  %b = bitcast < 2 x i64> %b64 to < 4 x i32>
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rmbk_128(< 4 x i32> %a, i64* %ptr_b, < 2 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rmbk_128
+  ;CHECK: vpmuludq (%rdi){1to2}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x19,0xf4,0x0f]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, <2 x i32> zeroinitializer
+  %b = bitcast < 2 x i64> %b64 to < 4 x i32>
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
+  ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rmbkz_128(< 4 x i32> %a, i64* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rmbkz_128
+  ;CHECK: vpmuludq (%rdi){1to2}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x99,0xf4,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, < 2 x i32> zeroinitializer
+  %b = bitcast < 2 x i64> %b64 to < 4 x i32>
+  %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
+  ret < 2 x i64> %res
+}
+
+declare < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32>, < 4 x i32>, < 2 x i64>, i8)
+
+define < 4 x i64> @test_mask_mul_epu32_rr_256(< 8 x i32> %a, < 8 x i32> %b) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rr_256
+  ;CHECK: vpmuludq %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf4,0xc1]
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rrk_256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rrk_256
+  ;CHECK: vpmuludq %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0xf4,0xd1]
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rrkz_256(< 8 x i32> %a, < 8 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rrkz_256
+  ;CHECK: vpmuludq %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0xf4,0xc1]
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rm_256(< 8 x i32> %a, < 8 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rm_256
+  ;CHECK: vpmuludq (%rdi), %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf4,0x07]
+  %b = load < 8 x i32>, < 8 x i32>* %ptr_b
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rmk_256(< 8 x i32> %a, < 8 x i32>* %ptr_b, < 4 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rmk_256
+  ;CHECK: vpmuludq (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0xf4,0x0f]
+  %b = load < 8 x i32>, < 8 x i32>* %ptr_b
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rmkz_256(< 8 x i32> %a, < 8 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rmkz_256
+  ;CHECK: vpmuludq (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0xf4,0x07]
+  %b = load < 8 x i32>, < 8 x i32>* %ptr_b
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rmb_256(< 8 x i32> %a, i64* %ptr_b) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rmb_256
+  ;CHECK: vpmuludq (%rdi){1to4}, %ymm0, %ymm0  ## encoding: [0x62,0xf1,0xfd,0x38,0xf4,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
+  %b = bitcast < 4 x i64> %b64 to < 8 x i32>
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rmbk_256(< 8 x i32> %a, i64* %ptr_b, < 4 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rmbk_256
+  ;CHECK: vpmuludq (%rdi){1to4}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x39,0xf4,0x0f]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
+  %b = bitcast < 4 x i64> %b64 to < 8 x i32>
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
+  ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rmbkz_256(< 8 x i32> %a, i64* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_mul_epu32_rmbkz_256
+  ;CHECK: vpmuludq (%rdi){1to4}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xb9,0xf4,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
+  %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
+  %b = bitcast < 4 x i64> %b64 to < 8 x i32>
+  %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
+  ret < 4 x i64> %res
+}
+
+declare < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32>, < 8 x i32>, < 4 x i64>, i8)
+
+define <4 x i32> @test_mask_add_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
+  ;CHECK-LABEL: test_mask_add_epi32_rr_128
+  ;CHECK: vpaddd %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf1,0x7d,0x08,0xfe,0xc1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.padd.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_add_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rrk_128
+  ;CHECK: vpaddd %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xfe,0xd1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.padd.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_add_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rrkz_128
+  ;CHECK: vpaddd %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xfe,0xc1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.padd.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_add_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_add_epi32_rm_128
+  ;CHECK: vpaddd (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf1,0x7d,0x08,0xfe,0x07]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.padd.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_add_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rmk_128
+  ;CHECK: vpaddd (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xfe,0x0f]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.padd.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_add_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rmkz_128
+  ;CHECK: vpaddd (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xfe,0x07]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.padd.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_add_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_add_epi32_rmb_128
+  ;CHECK: vpaddd (%rdi){1to4}, %xmm0, %xmm0  ## encoding: [0x62,0xf1,0x7d,0x18,0xfe,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.padd.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_add_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rmbk_128
+  ;CHECK: vpaddd (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xfe,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.padd.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_add_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rmbkz_128
+  ;CHECK: vpaddd (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xfe,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.padd.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+declare <4 x i32> @llvm.x86.avx512.mask.padd.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
+
+define <4 x i32> @test_mask_sub_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rr_128
+  ;CHECK: vpsubd %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf1,0x7d,0x08,0xfa,0xc1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.psub.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_sub_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rrk_128
+  ;CHECK: vpsubd %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xfa,0xd1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.psub.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_sub_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rrkz_128
+  ;CHECK: vpsubd %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xfa,0xc1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.psub.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_sub_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rm_128
+  ;CHECK: (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf1,0x7d,0x08,0xfa,0x07]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.psub.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_sub_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rmk_128
+  ;CHECK: vpsubd (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xfa,0x0f]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.psub.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_sub_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rmkz_128
+  ;CHECK: vpsubd (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xfa,0x07]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.psub.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_sub_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rmb_128
+  ;CHECK: vpsubd (%rdi){1to4}, %xmm0, %xmm0  ## encoding: [0x62,0xf1,0x7d,0x18,0xfa,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.psub.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_sub_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rmbk_128
+  ;CHECK: vpsubd (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xfa,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.psub.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_sub_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rmbkz_128
+  ;CHECK: vpsubd (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xfa,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.psub.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+declare <4 x i32> @llvm.x86.avx512.mask.psub.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
+
+define <8 x i32> @test_mask_sub_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rr_256
+  ;CHECK: vpsubd %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf1,0x7d,0x28,0xfa,0xc1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.psub.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_sub_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rrk_256
+  ;CHECK: vpsubd %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xfa,0xd1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.psub.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_sub_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rrkz_256
+  ;CHECK: vpsubd %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xfa,0xc1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.psub.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_sub_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rm_256
+  ;CHECK: vpsubd (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf1,0x7d,0x28,0xfa,0x07]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.psub.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_sub_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rmk_256
+  ;CHECK: vpsubd (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xfa,0x0f]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.psub.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_sub_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rmkz_256
+  ;CHECK: vpsubd (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xfa,0x07]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.psub.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_sub_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rmb_256
+  ;CHECK: vpsubd (%rdi){1to8}, %ymm0, %ymm0  ## encoding: [0x62,0xf1,0x7d,0x38,0xfa,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.psub.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_sub_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rmbk_256
+  ;CHECK: vpsubd (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xfa,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.psub.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_sub_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_sub_epi32_rmbkz_256
+  ;CHECK: vpsubd (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xfa,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.psub.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+declare <8 x i32> @llvm.x86.avx512.mask.psub.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
+
+define <8 x i32> @test_mask_add_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
+  ;CHECK-LABEL: test_mask_add_epi32_rr_256
+  ;CHECK: vpaddd %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf1,0x7d,0x28,0xfe,0xc1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.padd.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_add_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rrk_256
+  ;CHECK: vpaddd %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xfe,0xd1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.padd.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_add_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rrkz_256
+  ;CHECK: vpaddd %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xfe,0xc1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.padd.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_add_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_add_epi32_rm_256
+  ;CHECK: vpaddd (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf1,0x7d,0x28,0xfe,0x07]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.padd.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_add_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rmk_256
+  ;CHECK: vpaddd (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xfe,0x0f]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.padd.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_add_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rmkz_256
+  ;CHECK: vpaddd (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xfe,0x07]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.padd.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_add_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_add_epi32_rmb_256
+  ;CHECK: vpaddd (%rdi){1to8}, %ymm0, %ymm0  ## encoding: [0x62,0xf1,0x7d,0x38,0xfe,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.padd.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_add_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rmbk_256
+  ;CHECK: vpaddd (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xfe,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.padd.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_add_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_add_epi32_rmbkz_256
+  ;CHECK: vpaddd (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xfe,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.padd.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+declare <8 x i32> @llvm.x86.avx512.mask.padd.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
+
+define <4 x i32> @test_mask_and_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
+  ;CHECK-LABEL: test_mask_and_epi32_rr_128
+  ;CHECK: vpandd  %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf1,0x7d,0x08,0xdb,0xc1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_and_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_epi32_rrk_128
+  ;CHECK: vpandd  %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xdb,0xd1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_and_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_epi32_rrkz_128
+  ;CHECK: vpandd  %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xdb,0xc1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_and_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_and_epi32_rm_128
+  ;CHECK: vpandd  (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf1,0x7d,0x08,0xdb,0x07]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_and_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_epi32_rmk_128
+  ;CHECK: vpandd  (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xdb,0x0f]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_and_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_epi32_rmkz_128
+  ;CHECK: vpandd  (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xdb,0x07]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_and_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_and_epi32_rmb_128
+  ;CHECK: vpandd  (%rdi){1to4}, %xmm0, %xmm0  ## encoding: [0x62,0xf1,0x7d,0x18,0xdb,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_and_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_epi32_rmbk_128
+  ;CHECK: vpandd  (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xdb,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_and_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_epi32_rmbkz_128
+  ;CHECK: vpandd  (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xdb,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+declare <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
+
+define <8 x i32> @test_mask_and_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
+  ;CHECK-LABEL: test_mask_and_epi32_rr_256
+  ;CHECK: vpandd  %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf1,0x7d,0x28,0xdb,0xc1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_and_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_epi32_rrk_256
+  ;CHECK: vpandd  %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xdb,0xd1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_and_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_epi32_rrkz_256
+  ;CHECK: vpandd  %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xdb,0xc1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_and_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_and_epi32_rm_256
+  ;CHECK: vpandd  (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf1,0x7d,0x28,0xdb,0x07]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_and_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_epi32_rmk_256
+  ;CHECK: vpandd  (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xdb,0x0f]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_and_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_epi32_rmkz_256
+  ;CHECK: vpandd  (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xdb,0x07]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_and_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_and_epi32_rmb_256
+  ;CHECK: vpandd  (%rdi){1to8}, %ymm0, %ymm0  ## encoding: [0x62,0xf1,0x7d,0x38,0xdb,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_and_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_epi32_rmbk_256
+  ;CHECK: vpandd  (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xdb,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_and_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_and_epi32_rmbkz_256
+  ;CHECK: vpandd  (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xdb,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+declare <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
+
+define <4 x i32> @test_mask_or_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
+  ;CHECK-LABEL: test_mask_or_epi32_rr_128
+  ;CHECK: vpord   %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf1,0x7d,0x08,0xeb,0xc1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_or_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_epi32_rrk_128
+  ;CHECK: vpord   %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xeb,0xd1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_or_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_epi32_rrkz_128
+  ;CHECK: vpord   %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xeb,0xc1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_or_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_or_epi32_rm_128
+  ;CHECK: vpord   (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf1,0x7d,0x08,0xeb,0x07]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_or_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_epi32_rmk_128
+  ;CHECK: vpord   (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xeb,0x0f]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_or_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_epi32_rmkz_128
+  ;CHECK: vpord   (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xeb,0x07]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_or_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_or_epi32_rmb_128
+  ;CHECK: vpord   (%rdi){1to4}, %xmm0, %xmm0  ## encoding: [0x62,0xf1,0x7d,0x18,0xeb,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_or_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_epi32_rmbk_128
+  ;CHECK: vpord   (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xeb,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_or_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_epi32_rmbkz_128
+  ;CHECK: vpord   (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xeb,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+declare <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
+
+define <8 x i32> @test_mask_or_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
+  ;CHECK-LABEL: test_mask_or_epi32_rr_256
+  ;CHECK: vpord   %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf1,0x7d,0x28,0xeb,0xc1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_or_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_epi32_rrk_256
+  ;CHECK: vpord   %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xeb,0xd1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_or_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_epi32_rrkz_256
+  ;CHECK: vpord   %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xeb,0xc1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_or_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_or_epi32_rm_256
+  ;CHECK: vpord   (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf1,0x7d,0x28,0xeb,0x07]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_or_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_epi32_rmk_256
+  ;CHECK: vpord   (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xeb,0x0f]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_or_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_epi32_rmkz_256
+  ;CHECK: vpord   (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xeb,0x07]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_or_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_or_epi32_rmb_256
+  ;CHECK: vpord   (%rdi){1to8}, %ymm0, %ymm0  ## encoding: [0x62,0xf1,0x7d,0x38,0xeb,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_or_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_epi32_rmbk_256
+  ;CHECK: vpord   (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xeb,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_or_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_or_epi32_rmbkz_256
+  ;CHECK: vpord   (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xeb,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+declare <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
+
+define <4 x i32> @test_mask_xor_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rr_128
+  ;CHECK: vpxord  %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf1,0x7d,0x08,0xef,0xc1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_xor_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rrk_128
+  ;CHECK: vpxord  %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xef,0xd1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_xor_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rrkz_128
+  ;CHECK: vpxord  %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xef,0xc1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_xor_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rm_128
+  ;CHECK: vpxord  (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf1,0x7d,0x08,0xef,0x07]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_xor_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rmk_128
+  ;CHECK: vpxord  (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xef,0x0f]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_xor_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rmkz_128
+  ;CHECK: vpxord  (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xef,0x07]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_xor_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rmb_128
+  ;CHECK: vpxord  (%rdi){1to4}, %xmm0, %xmm0  ## encoding: [0x62,0xf1,0x7d,0x18,0xef,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_xor_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rmbk_128
+  ;CHECK: vpxord  (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xef,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_xor_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rmbkz_128
+  ;CHECK: vpxord  (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xef,0x07]  
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+declare <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
+
+define <8 x i32> @test_mask_xor_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rr_256
+  ;CHECK: vpxord  %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf1,0x7d,0x28,0xef,0xc1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_xor_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rrk_256
+  ;CHECK: vpxord  %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xef,0xd1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_xor_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rrkz_256
+  ;CHECK: vpxord  %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xef,0xc1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_xor_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rm_256
+  ;CHECK: vpxord  (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf1,0x7d,0x28,0xef,0x07]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_xor_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rmk_256
+  ;CHECK: vpxord  (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xef,0x0f]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_xor_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rmkz_256
+  ;CHECK: vpxord  (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xef,0x07]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_xor_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rmb_256
+  ;CHECK: vpxord  (%rdi){1to8}, %ymm0, %ymm0  ## encoding: [0x62,0xf1,0x7d,0x38,0xef,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_xor_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rmbk_256
+  ;CHECK: vpxord  (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xef,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_xor_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_xor_epi32_rmbkz_256
+  ;CHECK: vpxord  (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xef,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+declare <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
+
+define <4 x i32> @test_mask_andnot_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rr_128
+  ;CHECK: vpandnd  %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf1,0x7d,0x08,0xdf,0xc1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_andnot_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rrk_128
+  ;CHECK: vpandnd  %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xdf,0xd1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_andnot_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rrkz_128
+  ;CHECK: vpandnd  %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xdf,0xc1]
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_andnot_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rm_128
+  ;CHECK: vpandnd  (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf1,0x7d,0x08,0xdf,0x07]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_andnot_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rmk_128
+  ;CHECK: vpandnd  (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xdf,0x0f]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_andnot_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rmkz_128
+  ;CHECK: vpandnd  (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xdf,0x07]
+  %b = load <4 x i32>, <4 x i32>* %ptr_b
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_andnot_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rmb_128
+  ;CHECK: vpandnd  (%rdi){1to4}, %xmm0, %xmm0  ## encoding: [0x62,0xf1,0x7d,0x18,0xdf,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_andnot_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <4 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rmbk_128
+  ;CHECK: vpandnd  (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xdf,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_mask_andnot_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rmbkz_128
+  ;CHECK: vpandnd  (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xdf,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
+  ret <4 x i32> %res
+}
+
+declare <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
+
+define <8 x i32> @test_mask_andnot_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rr_256
+  ;CHECK: vpandnd  %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf1,0x7d,0x28,0xdf,0xc1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_andnot_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rrk_256
+  ;CHECK: vpandnd  %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xdf,0xd1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_andnot_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rrkz_256
+  ;CHECK: vpandnd  %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xdf,0xc1]
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_andnot_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rm_256
+  ;CHECK: vpandnd  (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf1,0x7d,0x28,0xdf,0x07]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_andnot_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rmk_256
+  ;CHECK: vpandnd  (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xdf,0x0f]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_andnot_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rmkz_256
+  ;CHECK: vpandnd  (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xdf,0x07]
+  %b = load <8 x i32>, <8 x i32>* %ptr_b
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_andnot_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rmb_256
+  ;CHECK: vpandnd  (%rdi){1to8}, %ymm0, %ymm0  ## encoding: [0x62,0xf1,0x7d,0x38,0xdf,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_andnot_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <8 x i32> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rmbk_256
+  ;CHECK: vpandnd  (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xdf,0x0f]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
+  ret <8 x i32> %res
+}
+
+define <8 x i32> @test_mask_andnot_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi32_rmbkz_256
+  ;CHECK: vpandnd  (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xdf,0x07]
+  %q = load i32, i32* %ptr_b
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
+  ret <8 x i32> %res
+}
+
+declare <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
+
+define <2 x i64> @test_mask_andnot_epi64_rr_128(<2 x i64> %a, <2 x i64> %b) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rr_128
+  ;CHECK: vpandnq  %xmm1, %xmm0, %xmm0     ## encoding: [0x62,0xf1,0xfd,0x08,0xdf,0xc1]
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_andnot_epi64_rrk_128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rrk_128
+  ;CHECK: vpandnq  %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x09,0xdf,0xd1]
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_andnot_epi64_rrkz_128(<2 x i64> %a, <2 x i64> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rrkz_128
+  ;CHECK: vpandnq  %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x89,0xdf,0xc1]
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 %mask)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_andnot_epi64_rm_128(<2 x i64> %a, <2 x i64>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rm_128
+  ;CHECK: vpandnq  (%rdi), %xmm0, %xmm0    ## encoding: [0x62,0xf1,0xfd,0x08,0xdf,0x07]
+  %b = load <2 x i64>, <2 x i64>* %ptr_b
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_andnot_epi64_rmk_128(<2 x i64> %a, <2 x i64>* %ptr_b, <2 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rmk_128
+  ;CHECK: vpandnq  (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x09,0xdf,0x0f]
+  %b = load <2 x i64>, <2 x i64>* %ptr_b
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_andnot_epi64_rmkz_128(<2 x i64> %a, <2 x i64>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rmkz_128
+  ;CHECK: vpandnq  (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x89,0xdf,0x07]
+  %b = load <2 x i64>, <2 x i64>* %ptr_b
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 %mask)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_andnot_epi64_rmb_128(<2 x i64> %a, i64* %ptr_b) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rmb_128
+  ;CHECK: vpandnq  (%rdi){1to2}, %xmm0, %xmm0  ## encoding: [0x62,0xf1,0xfd,0x18,0xdf,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <2 x i64> %vecinit.i, <2 x i64> undef, <2 x i32> zeroinitializer
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_andnot_epi64_rmbk_128(<2 x i64> %a, i64* %ptr_b, <2 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rmbk_128
+  ;CHECK: vpandnq  (%rdi){1to2}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x19,0xdf,0x0f]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <2 x i64> %vecinit.i, <2 x i64> undef, <2 x i32> zeroinitializer
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask)
+  ret <2 x i64> %res
+}
+
+define <2 x i64> @test_mask_andnot_epi64_rmbkz_128(<2 x i64> %a, i64* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rmbkz_128
+  ;CHECK: vpandnq  (%rdi){1to2}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x99,0xdf,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <2 x i64> %vecinit.i, <2 x i64> undef, <2 x i32> zeroinitializer
+  %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 %mask)
+  ret <2 x i64> %res
+}
+
+declare <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
+
+define <4 x i64> @test_mask_andnot_epi64_rr_256(<4 x i64> %a, <4 x i64> %b) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rr_256
+  ;CHECK: vpandnq  %ymm1, %ymm0, %ymm0     ## encoding: [0x62,0xf1,0xfd,0x28,0xdf,0xc1]
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_andnot_epi64_rrk_256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rrk_256
+  ;CHECK: vpandnq  %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0xdf,0xd1]
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_andnot_epi64_rrkz_256(<4 x i64> %a, <4 x i64> %b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rrkz_256
+  ;CHECK: vpandnq  %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0xdf,0xc1]
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 %mask)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_andnot_epi64_rm_256(<4 x i64> %a, <4 x i64>* %ptr_b) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rm_256
+  ;CHECK: vpandnq  (%rdi), %ymm0, %ymm0    ## encoding: [0x62,0xf1,0xfd,0x28,0xdf,0x07]
+  %b = load <4 x i64>, <4 x i64>* %ptr_b
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_andnot_epi64_rmk_256(<4 x i64> %a, <4 x i64>* %ptr_b, <4 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rmk_256
+  ;CHECK: vpandnq  (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0xdf,0x0f]
+  %b = load <4 x i64>, <4 x i64>* %ptr_b
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_andnot_epi64_rmkz_256(<4 x i64> %a, <4 x i64>* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rmkz_256
+  ;CHECK: vpandnq  (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0xdf,0x07]
+  %b = load <4 x i64>, <4 x i64>* %ptr_b
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 %mask)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_andnot_epi64_rmb_256(<4 x i64> %a, i64* %ptr_b) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rmb_256
+  ;CHECK: vpandnq  (%rdi){1to4}, %ymm0, %ymm0  ## encoding: [0x62,0xf1,0xfd,0x38,0xdf,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <4 x i64> %vecinit.i, <4 x i64> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_andnot_epi64_rmbk_256(<4 x i64> %a, i64* %ptr_b, <4 x i64> %passThru, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rmbk_256
+  ;CHECK: vpandnq  (%rdi){1to4}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x39,0xdf,0x0f]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <4 x i64> %vecinit.i, <4 x i64> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask)
+  ret <4 x i64> %res
+}
+
+define <4 x i64> @test_mask_andnot_epi64_rmbkz_256(<4 x i64> %a, i64* %ptr_b, i8 %mask) {
+  ;CHECK-LABEL: test_mask_andnot_epi64_rmbkz_256
+  ;CHECK: vpandnq  (%rdi){1to4}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xb9,0xdf,0x07]
+  %q = load i64, i64* %ptr_b
+  %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
+  %b = shufflevector <4 x i64> %vecinit.i, <4 x i64> undef, <4 x i32> zeroinitializer
+  %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 %mask)
+  ret <4 x i64> %res
+}
+
+declare <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
+
+define i8 @test_cmpps_256(<8 x float> %a, <8 x float> %b) {
+ ;CHECK: vcmpleps  %ymm1, %ymm0, %k0  ## encoding: [0x62,0xf1,0x7c,0x28,0xc2,0xc1,0x02]
+   %res = call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %a, <8 x float> %b, i32 2, i8 -1)
+   ret i8 %res
+ }
+ declare i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> , <8 x float> , i32, i8)
+
+define i8 @test_cmpps_128(<4 x float> %a, <4 x float> %b) {
+ ;CHECK: vcmpleps  %xmm1, %xmm0, %k0  ## encoding: [0x62,0xf1,0x7c,0x08,0xc2,0xc1,0x02]
+   %res = call i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %a, <4 x float> %b, i32 2, i8 -1)
+   ret i8 %res
+ }
+ declare i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> , <4 x float> , i32, i8)
+
+define i8 @test_cmppd_256(<4 x double> %a, <4 x double> %b) {
+ ;CHECK: vcmplepd  %ymm1, %ymm0, %k0  ## encoding: [0x62,0xf1,0xfd,0x28,0xc2,0xc1,0x02]
+   %res = call i8 @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %a, <4 x double> %b, i32 2, i8 -1)
+   ret i8 %res
+ }
+ declare i8 @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> , <4 x double> , i32, i8)
+
+define i8 @test_cmppd_128(<2 x double> %a, <2 x double> %b) {
+ ;CHECK: vcmplepd  %xmm1, %xmm0, %k0  ## encoding: [0x62,0xf1,0xfd,0x08,0xc2,0xc1,0x02]
+   %res = call i8 @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %a, <2 x double> %b, i32 2, i8 -1)
+   ret i8 %res
+ }
+ declare i8 @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> , <2 x double> , i32, i8)
+
+define <8 x float> @test_mm512_maskz_add_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_add_ps_256
+  ;CHECK: vaddps %ymm1, %ymm0, %ymm0 {%k1} {z}
+  %res = call <8 x float> @llvm.x86.avx512.mask.add.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float>zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mm512_mask_add_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %src, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_add_ps_256
+  ;CHECK: vaddps %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <8 x float> @llvm.x86.avx512.mask.add.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %src, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mm512_add_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_add_ps_256
+  ;CHECK: vaddps %ymm1, %ymm0, %ymm0
+  %res = call <8 x float> @llvm.x86.avx512.mask.add.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float>zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+declare <8 x float> @llvm.x86.avx512.mask.add.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
+
+define <4 x float> @test_mm512_maskz_add_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_add_ps_128
+  ;CHECK: vaddps %xmm1, %xmm0, %xmm0 {%k1} {z}
+  %res = call <4 x float> @llvm.x86.avx512.mask.add.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float>zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mm512_mask_add_ps_128(<4 x float> %a0, <4 x float> %a1, <4 x float> %src, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_add_ps_128
+  ;CHECK: vaddps %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <4 x float> @llvm.x86.avx512.mask.add.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %src, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mm512_add_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_add_ps_128
+  ;CHECK: vaddps %xmm1, %xmm0, %xmm0
+  %res = call <4 x float> @llvm.x86.avx512.mask.add.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float>zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+declare <4 x float> @llvm.x86.avx512.mask.add.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
+
+define <8 x float> @test_mm512_maskz_sub_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_sub_ps_256
+  ;CHECK: vsubps %ymm1, %ymm0, %ymm0 {%k1} {z}
+  %res = call <8 x float> @llvm.x86.avx512.mask.sub.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float>zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mm512_mask_sub_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %src, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_sub_ps_256
+  ;CHECK: vsubps %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <8 x float> @llvm.x86.avx512.mask.sub.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %src, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mm512_sub_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_sub_ps_256
+  ;CHECK: vsubps %ymm1, %ymm0, %ymm0
+  %res = call <8 x float> @llvm.x86.avx512.mask.sub.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float>zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+declare <8 x float> @llvm.x86.avx512.mask.sub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
+
+define <4 x float> @test_mm512_maskz_sub_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_sub_ps_128
+  ;CHECK: vsubps %xmm1, %xmm0, %xmm0 {%k1} {z}
+  %res = call <4 x float> @llvm.x86.avx512.mask.sub.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float>zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mm512_mask_sub_ps_128(<4 x float> %a0, <4 x float> %a1, <4 x float> %src, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_sub_ps_128
+  ;CHECK: vsubps %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <4 x float> @llvm.x86.avx512.mask.sub.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %src, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mm512_sub_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_sub_ps_128
+  ;CHECK: vsubps %xmm1, %xmm0, %xmm0
+  %res = call <4 x float> @llvm.x86.avx512.mask.sub.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float>zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+declare <4 x float> @llvm.x86.avx512.mask.sub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
+
+define <8 x float> @test_mm512_maskz_mul_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_mul_ps_256
+  ;CHECK: vmulps %ymm1, %ymm0, %ymm0 {%k1} {z}
+  %res = call <8 x float> @llvm.x86.avx512.mask.mul.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float>zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mm512_mask_mul_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %src, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_mul_ps_256
+  ;CHECK: vmulps %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <8 x float> @llvm.x86.avx512.mask.mul.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %src, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mm512_mul_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_mul_ps_256
+  ;CHECK: vmulps %ymm1, %ymm0, %ymm0
+  %res = call <8 x float> @llvm.x86.avx512.mask.mul.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float>zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+declare <8 x float> @llvm.x86.avx512.mask.mul.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
+
+define <4 x float> @test_mm512_maskz_mul_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_mul_ps_128
+  ;CHECK: vmulps %xmm1, %xmm0, %xmm0 {%k1} {z}
+  %res = call <4 x float> @llvm.x86.avx512.mask.mul.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float>zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mm512_mask_mul_ps_128(<4 x float> %a0, <4 x float> %a1, <4 x float> %src, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_mul_ps_128
+  ;CHECK: vmulps %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <4 x float> @llvm.x86.avx512.mask.mul.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %src, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mm512_mul_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_mul_ps_128
+  ;CHECK: vmulps %xmm1, %xmm0, %xmm0
+  %res = call <4 x float> @llvm.x86.avx512.mask.mul.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float>zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+declare <4 x float> @llvm.x86.avx512.mask.mul.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
+
+define <8 x float> @test_mm512_maskz_div_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_div_ps_256
+  ;CHECK: vdivps %ymm1, %ymm0, %ymm0 {%k1} {z}
+  %res = call <8 x float> @llvm.x86.avx512.mask.div.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float>zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mm512_mask_div_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %src, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_div_ps_256
+  ;CHECK: vdivps %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <8 x float> @llvm.x86.avx512.mask.div.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %src, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mm512_div_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_div_ps_256
+  ;CHECK: vdivps %ymm1, %ymm0, %ymm0
+  %res = call <8 x float> @llvm.x86.avx512.mask.div.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float>zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+declare <8 x float> @llvm.x86.avx512.mask.div.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
+
+define <4 x float> @test_mm512_maskz_div_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_div_ps_128
+  ;CHECK: vdivps %xmm1, %xmm0, %xmm0 {%k1} {z}
+  %res = call <4 x float> @llvm.x86.avx512.mask.div.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float>zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mm512_mask_div_ps_128(<4 x float> %a0, <4 x float> %a1, <4 x float> %src, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_div_ps_128
+  ;CHECK: vdivps %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <4 x float> @llvm.x86.avx512.mask.div.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %src, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mm512_div_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_div_ps_128
+  ;CHECK: vdivps %xmm1, %xmm0, %xmm0
+  %res = call <4 x float> @llvm.x86.avx512.mask.div.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float>zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+declare <4 x float> @llvm.x86.avx512.mask.div.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
+
+define <8 x float> @test_mm512_maskz_max_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_max_ps_256
+  ;CHECK: vmaxps %ymm1, %ymm0, %ymm0 {%k1} {z}
+  %res = call <8 x float> @llvm.x86.avx512.mask.max.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float>zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mm512_mask_max_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %src, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_max_ps_256
+  ;CHECK: vmaxps %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <8 x float> @llvm.x86.avx512.mask.max.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %src, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mm512_max_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_max_ps_256
+  ;CHECK: vmaxps %ymm1, %ymm0, %ymm0
+  %res = call <8 x float> @llvm.x86.avx512.mask.max.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float>zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+declare <8 x float> @llvm.x86.avx512.mask.max.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
+
+define <4 x float> @test_mm512_maskz_max_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_max_ps_128
+  ;CHECK: vmaxps %xmm1, %xmm0, %xmm0 {%k1} {z}
+  %res = call <4 x float> @llvm.x86.avx512.mask.max.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float>zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mm512_mask_max_ps_128(<4 x float> %a0, <4 x float> %a1, <4 x float> %src, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_max_ps_128
+  ;CHECK: vmaxps %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <4 x float> @llvm.x86.avx512.mask.max.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %src, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mm512_max_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_max_ps_128
+  ;CHECK: vmaxps %xmm1, %xmm0, %xmm0
+  %res = call <4 x float> @llvm.x86.avx512.mask.max.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float>zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+declare <4 x float> @llvm.x86.avx512.mask.max.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
+
+define <8 x float> @test_mm512_maskz_min_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_min_ps_256
+  ;CHECK: vminps %ymm1, %ymm0, %ymm0 {%k1} {z}
+  %res = call <8 x float> @llvm.x86.avx512.mask.min.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float>zeroinitializer, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mm512_mask_min_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %src, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_min_ps_256
+  ;CHECK: vminps %ymm1, %ymm0, %ymm2 {%k1} 
+  %res = call <8 x float> @llvm.x86.avx512.mask.min.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %src, i8 %mask)
+  ret <8 x float> %res
+}
+
+define <8 x float> @test_mm512_min_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_min_ps_256
+  ;CHECK: vminps %ymm1, %ymm0, %ymm0
+  %res = call <8 x float> @llvm.x86.avx512.mask.min.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float>zeroinitializer, i8 -1)
+  ret <8 x float> %res
+}
+declare <8 x float> @llvm.x86.avx512.mask.min.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
+
+define <4 x float> @test_mm512_maskz_min_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_maskz_min_ps_128
+  ;CHECK: vminps %xmm1, %xmm0, %xmm0 {%k1} {z}
+  %res = call <4 x float> @llvm.x86.avx512.mask.min.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float>zeroinitializer, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mm512_mask_min_ps_128(<4 x float> %a0, <4 x float> %a1, <4 x float> %src, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_mask_min_ps_128
+  ;CHECK: vminps %xmm1, %xmm0, %xmm2 {%k1} 
+  %res = call <4 x float> @llvm.x86.avx512.mask.min.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %src, i8 %mask)
+  ret <4 x float> %res
+}
+
+define <4 x float> @test_mm512_min_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
+  ;CHECK-LABEL: test_mm512_min_ps_128
+  ;CHECK: vminps %xmm1, %xmm0, %xmm0
+  %res = call <4 x float> @llvm.x86.avx512.mask.min.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float>zeroinitializer, i8 -1)
+  ret <4 x float> %res
+}
+declare <4 x float> @llvm.x86.avx512.mask.min.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
\ No newline at end of file
diff --git a/test/CodeGen/X86/avx512vl-mov.ll b/test/CodeGen/X86/avx512vl-mov.ll
index 32246568ac2e..18fa0a142a2d 100644
--- a/test/CodeGen/X86/avx512vl-mov.ll
+++ b/test/CodeGen/X86/avx512vl-mov.ll
@@ -5,7 +5,7 @@
 ; CHECK: ret
 define <8 x i32> @test_256_1(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <8 x i32>*
-  %res = load <8 x i32>* %vaddr, align 1
+  %res = load <8 x i32>, <8 x i32>* %vaddr, align 1
   ret <8 x i32>%res
 }
 
@@ -14,7 +14,7 @@ define <8 x i32> @test_256_1(i8 * %addr) {
 ; CHECK: ret
 define <8 x i32> @test_256_2(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <8 x i32>*
-  %res = load <8 x i32>* %vaddr, align 32
+  %res = load <8 x i32>, <8 x i32>* %vaddr, align 32
   ret <8 x i32>%res
 }
 
@@ -50,7 +50,7 @@ define void @test_256_5(i8 * %addr, <8 x i32> %data) {
 ; CHECK: ret
 define  <4 x i64> @test_256_6(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <4 x i64>*
-  %res = load <4 x i64>* %vaddr, align 32
+  %res = load <4 x i64>, <4 x i64>* %vaddr, align 32
   ret <4 x i64>%res
 }
 
@@ -68,7 +68,7 @@ define void @test_256_7(i8 * %addr, <4 x i64> %data) {
 ; CHECK: ret
 define <4 x i64> @test_256_8(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <4 x i64>*
-  %res = load <4 x i64>* %vaddr, align 1
+  %res = load <4 x i64>, <4 x i64>* %vaddr, align 1
   ret <4 x i64>%res
 }
 
@@ -86,7 +86,7 @@ define void @test_256_9(i8 * %addr, <4 x double> %data) {
 ; CHECK: ret
 define <4 x double> @test_256_10(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <4 x double>*
-  %res = load <4 x double>* %vaddr, align 32
+  %res = load <4 x double>, <4 x double>* %vaddr, align 32
   ret <4 x double>%res
 }
 
@@ -104,7 +104,7 @@ define void @test_256_11(i8 * %addr, <8 x float> %data) {
 ; CHECK: ret
 define <8 x float> @test_256_12(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <8 x float>*
-  %res = load <8 x float>* %vaddr, align 32
+  %res = load <8 x float>, <8 x float>* %vaddr, align 32
   ret <8 x float>%res
 }
 
@@ -122,7 +122,7 @@ define void @test_256_13(i8 * %addr, <4 x double> %data) {
 ; CHECK: ret
 define <4 x double> @test_256_14(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <4 x double>*
-  %res = load <4 x double>* %vaddr, align 1
+  %res = load <4 x double>, <4 x double>* %vaddr, align 1
   ret <4 x double>%res
 }
 
@@ -140,7 +140,7 @@ define void @test_256_15(i8 * %addr, <8 x float> %data) {
 ; CHECK: ret
 define <8 x float> @test_256_16(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <8 x float>*
-  %res = load <8 x float>* %vaddr, align 1
+  %res = load <8 x float>, <8 x float>* %vaddr, align 1
   ret <8 x float>%res
 }
 
@@ -150,7 +150,7 @@ define <8 x float> @test_256_16(i8 * %addr) {
 define <8 x i32> @test_256_17(i8 * %addr, <8 x i32> %old, <8 x i32> %mask1) {
   %mask = icmp ne <8 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x i32>*
-  %r = load <8 x i32>* %vaddr, align 32
+  %r = load <8 x i32>, <8 x i32>* %vaddr, align 32
   %res = select <8 x i1> %mask, <8 x i32> %r, <8 x i32> %old
   ret <8 x i32>%res
 }
@@ -161,7 +161,7 @@ define <8 x i32> @test_256_17(i8 * %addr, <8 x i32> %old, <8 x i32> %mask1) {
 define <8 x i32> @test_256_18(i8 * %addr, <8 x i32> %old, <8 x i32> %mask1) {
   %mask = icmp ne <8 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x i32>*
-  %r = load <8 x i32>* %vaddr, align 1
+  %r = load <8 x i32>, <8 x i32>* %vaddr, align 1
   %res = select <8 x i1> %mask, <8 x i32> %r, <8 x i32> %old
   ret <8 x i32>%res
 }
@@ -172,7 +172,7 @@ define <8 x i32> @test_256_18(i8 * %addr, <8 x i32> %old, <8 x i32> %mask1) {
 define <8 x i32> @test_256_19(i8 * %addr, <8 x i32> %mask1) {
   %mask = icmp ne <8 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x i32>*
-  %r = load <8 x i32>* %vaddr, align 32
+  %r = load <8 x i32>, <8 x i32>* %vaddr, align 32
   %res = select <8 x i1> %mask, <8 x i32> %r, <8 x i32> zeroinitializer
   ret <8 x i32>%res
 }
@@ -183,7 +183,7 @@ define <8 x i32> @test_256_19(i8 * %addr, <8 x i32> %mask1) {
 define <8 x i32> @test_256_20(i8 * %addr, <8 x i32> %mask1) {
   %mask = icmp ne <8 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x i32>*
-  %r = load <8 x i32>* %vaddr, align 1
+  %r = load <8 x i32>, <8 x i32>* %vaddr, align 1
   %res = select <8 x i1> %mask, <8 x i32> %r, <8 x i32> zeroinitializer
   ret <8 x i32>%res
 }
@@ -194,7 +194,7 @@ define <8 x i32> @test_256_20(i8 * %addr, <8 x i32> %mask1) {
 define <4 x i64> @test_256_21(i8 * %addr, <4 x i64> %old, <4 x i64> %mask1) {
   %mask = icmp ne <4 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x i64>*
-  %r = load <4 x i64>* %vaddr, align 32
+  %r = load <4 x i64>, <4 x i64>* %vaddr, align 32
   %res = select <4 x i1> %mask, <4 x i64> %r, <4 x i64> %old
   ret <4 x i64>%res
 }
@@ -205,7 +205,7 @@ define <4 x i64> @test_256_21(i8 * %addr, <4 x i64> %old, <4 x i64> %mask1) {
 define <4 x i64> @test_256_22(i8 * %addr, <4 x i64> %old, <4 x i64> %mask1) {
   %mask = icmp ne <4 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x i64>*
-  %r = load <4 x i64>* %vaddr, align 1
+  %r = load <4 x i64>, <4 x i64>* %vaddr, align 1
   %res = select <4 x i1> %mask, <4 x i64> %r, <4 x i64> %old
   ret <4 x i64>%res
 }
@@ -216,7 +216,7 @@ define <4 x i64> @test_256_22(i8 * %addr, <4 x i64> %old, <4 x i64> %mask1) {
 define <4 x i64> @test_256_23(i8 * %addr, <4 x i64> %mask1) {
   %mask = icmp ne <4 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x i64>*
-  %r = load <4 x i64>* %vaddr, align 32
+  %r = load <4 x i64>, <4 x i64>* %vaddr, align 32
   %res = select <4 x i1> %mask, <4 x i64> %r, <4 x i64> zeroinitializer
   ret <4 x i64>%res
 }
@@ -227,7 +227,7 @@ define <4 x i64> @test_256_23(i8 * %addr, <4 x i64> %mask1) {
 define <4 x i64> @test_256_24(i8 * %addr, <4 x i64> %mask1) {
   %mask = icmp ne <4 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x i64>*
-  %r = load <4 x i64>* %vaddr, align 1
+  %r = load <4 x i64>, <4 x i64>* %vaddr, align 1
   %res = select <4 x i1> %mask, <4 x i64> %r, <4 x i64> zeroinitializer
   ret <4 x i64>%res
 }
@@ -238,7 +238,7 @@ define <4 x i64> @test_256_24(i8 * %addr, <4 x i64> %mask1) {
 define <8 x float> @test_256_25(i8 * %addr, <8 x float> %old, <8 x float> %mask1) {
   %mask = fcmp one <8 x float> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x float>*
-  %r = load <8 x float>* %vaddr, align 32
+  %r = load <8 x float>, <8 x float>* %vaddr, align 32
   %res = select <8 x i1> %mask, <8 x float> %r, <8 x float> %old
   ret <8 x float>%res
 }
@@ -249,7 +249,7 @@ define <8 x float> @test_256_25(i8 * %addr, <8 x float> %old, <8 x float> %mask1
 define <8 x float> @test_256_26(i8 * %addr, <8 x float> %old, <8 x float> %mask1) {
   %mask = fcmp one <8 x float> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x float>*
-  %r = load <8 x float>* %vaddr, align 1
+  %r = load <8 x float>, <8 x float>* %vaddr, align 1
   %res = select <8 x i1> %mask, <8 x float> %r, <8 x float> %old
   ret <8 x float>%res
 }
@@ -260,7 +260,7 @@ define <8 x float> @test_256_26(i8 * %addr, <8 x float> %old, <8 x float> %mask1
 define <8 x float> @test_256_27(i8 * %addr, <8 x float> %mask1) {
   %mask = fcmp one <8 x float> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x float>*
-  %r = load <8 x float>* %vaddr, align 32
+  %r = load <8 x float>, <8 x float>* %vaddr, align 32
   %res = select <8 x i1> %mask, <8 x float> %r, <8 x float> zeroinitializer
   ret <8 x float>%res
 }
@@ -271,7 +271,7 @@ define <8 x float> @test_256_27(i8 * %addr, <8 x float> %mask1) {
 define <8 x float> @test_256_28(i8 * %addr, <8 x float> %mask1) {
   %mask = fcmp one <8 x float> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <8 x float>*
-  %r = load <8 x float>* %vaddr, align 1
+  %r = load <8 x float>, <8 x float>* %vaddr, align 1
   %res = select <8 x i1> %mask, <8 x float> %r, <8 x float> zeroinitializer
   ret <8 x float>%res
 }
@@ -282,7 +282,7 @@ define <8 x float> @test_256_28(i8 * %addr, <8 x float> %mask1) {
 define <4 x double> @test_256_29(i8 * %addr, <4 x double> %old, <4 x i64> %mask1) {
   %mask = icmp ne <4 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x double>*
-  %r = load <4 x double>* %vaddr, align 32
+  %r = load <4 x double>, <4 x double>* %vaddr, align 32
   %res = select <4 x i1> %mask, <4 x double> %r, <4 x double> %old
   ret <4 x double>%res
 }
@@ -293,7 +293,7 @@ define <4 x double> @test_256_29(i8 * %addr, <4 x double> %old, <4 x i64> %mask1
 define <4 x double> @test_256_30(i8 * %addr, <4 x double> %old, <4 x i64> %mask1) {
   %mask = icmp ne <4 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x double>*
-  %r = load <4 x double>* %vaddr, align 1
+  %r = load <4 x double>, <4 x double>* %vaddr, align 1
   %res = select <4 x i1> %mask, <4 x double> %r, <4 x double> %old
   ret <4 x double>%res
 }
@@ -304,7 +304,7 @@ define <4 x double> @test_256_30(i8 * %addr, <4 x double> %old, <4 x i64> %mask1
 define <4 x double> @test_256_31(i8 * %addr, <4 x i64> %mask1) {
   %mask = icmp ne <4 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x double>*
-  %r = load <4 x double>* %vaddr, align 32
+  %r = load <4 x double>, <4 x double>* %vaddr, align 32
   %res = select <4 x i1> %mask, <4 x double> %r, <4 x double> zeroinitializer
   ret <4 x double>%res
 }
@@ -315,7 +315,7 @@ define <4 x double> @test_256_31(i8 * %addr, <4 x i64> %mask1) {
 define <4 x double> @test_256_32(i8 * %addr, <4 x i64> %mask1) {
   %mask = icmp ne <4 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x double>*
-  %r = load <4 x double>* %vaddr, align 1
+  %r = load <4 x double>, <4 x double>* %vaddr, align 1
   %res = select <4 x i1> %mask, <4 x double> %r, <4 x double> zeroinitializer
   ret <4 x double>%res
 }
@@ -325,7 +325,7 @@ define <4 x double> @test_256_32(i8 * %addr, <4 x i64> %mask1) {
 ; CHECK: ret
 define <4 x i32> @test_128_1(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <4 x i32>*
-  %res = load <4 x i32>* %vaddr, align 1
+  %res = load <4 x i32>, <4 x i32>* %vaddr, align 1
   ret <4 x i32>%res
 }
 
@@ -334,7 +334,7 @@ define <4 x i32> @test_128_1(i8 * %addr) {
 ; CHECK: ret
 define <4 x i32> @test_128_2(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <4 x i32>*
-  %res = load <4 x i32>* %vaddr, align 16
+  %res = load <4 x i32>, <4 x i32>* %vaddr, align 16
   ret <4 x i32>%res
 }
 
@@ -370,7 +370,7 @@ define void @test_128_5(i8 * %addr, <4 x i32> %data) {
 ; CHECK: ret
 define  <2 x i64> @test_128_6(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <2 x i64>*
-  %res = load <2 x i64>* %vaddr, align 16
+  %res = load <2 x i64>, <2 x i64>* %vaddr, align 16
   ret <2 x i64>%res
 }
 
@@ -388,7 +388,7 @@ define void @test_128_7(i8 * %addr, <2 x i64> %data) {
 ; CHECK: ret
 define <2 x i64> @test_128_8(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <2 x i64>*
-  %res = load <2 x i64>* %vaddr, align 1
+  %res = load <2 x i64>, <2 x i64>* %vaddr, align 1
   ret <2 x i64>%res
 }
 
@@ -406,7 +406,7 @@ define void @test_128_9(i8 * %addr, <2 x double> %data) {
 ; CHECK: ret
 define <2 x double> @test_128_10(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <2 x double>*
-  %res = load <2 x double>* %vaddr, align 16
+  %res = load <2 x double>, <2 x double>* %vaddr, align 16
   ret <2 x double>%res
 }
 
@@ -424,7 +424,7 @@ define void @test_128_11(i8 * %addr, <4 x float> %data) {
 ; CHECK: ret
 define <4 x float> @test_128_12(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <4 x float>*
-  %res = load <4 x float>* %vaddr, align 16
+  %res = load <4 x float>, <4 x float>* %vaddr, align 16
   ret <4 x float>%res
 }
 
@@ -442,7 +442,7 @@ define void @test_128_13(i8 * %addr, <2 x double> %data) {
 ; CHECK: ret
 define <2 x double> @test_128_14(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <2 x double>*
-  %res = load <2 x double>* %vaddr, align 1
+  %res = load <2 x double>, <2 x double>* %vaddr, align 1
   ret <2 x double>%res
 }
 
@@ -460,7 +460,7 @@ define void @test_128_15(i8 * %addr, <4 x float> %data) {
 ; CHECK: ret
 define <4 x float> @test_128_16(i8 * %addr) {
   %vaddr = bitcast i8* %addr to <4 x float>*
-  %res = load <4 x float>* %vaddr, align 1
+  %res = load <4 x float>, <4 x float>* %vaddr, align 1
   ret <4 x float>%res
 }
 
@@ -470,7 +470,7 @@ define <4 x float> @test_128_16(i8 * %addr) {
 define <4 x i32> @test_128_17(i8 * %addr, <4 x i32> %old, <4 x i32> %mask1) {
   %mask = icmp ne <4 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x i32>*
-  %r = load <4 x i32>* %vaddr, align 16
+  %r = load <4 x i32>, <4 x i32>* %vaddr, align 16
   %res = select <4 x i1> %mask, <4 x i32> %r, <4 x i32> %old
   ret <4 x i32>%res
 }
@@ -481,7 +481,7 @@ define <4 x i32> @test_128_17(i8 * %addr, <4 x i32> %old, <4 x i32> %mask1) {
 define <4 x i32> @test_128_18(i8 * %addr, <4 x i32> %old, <4 x i32> %mask1) {
   %mask = icmp ne <4 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x i32>*
-  %r = load <4 x i32>* %vaddr, align 1
+  %r = load <4 x i32>, <4 x i32>* %vaddr, align 1
   %res = select <4 x i1> %mask, <4 x i32> %r, <4 x i32> %old
   ret <4 x i32>%res
 }
@@ -492,7 +492,7 @@ define <4 x i32> @test_128_18(i8 * %addr, <4 x i32> %old, <4 x i32> %mask1) {
 define <4 x i32> @test_128_19(i8 * %addr, <4 x i32> %mask1) {
   %mask = icmp ne <4 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x i32>*
-  %r = load <4 x i32>* %vaddr, align 16
+  %r = load <4 x i32>, <4 x i32>* %vaddr, align 16
   %res = select <4 x i1> %mask, <4 x i32> %r, <4 x i32> zeroinitializer
   ret <4 x i32>%res
 }
@@ -503,7 +503,7 @@ define <4 x i32> @test_128_19(i8 * %addr, <4 x i32> %mask1) {
 define <4 x i32> @test_128_20(i8 * %addr, <4 x i32> %mask1) {
   %mask = icmp ne <4 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x i32>*
-  %r = load <4 x i32>* %vaddr, align 1
+  %r = load <4 x i32>, <4 x i32>* %vaddr, align 1
   %res = select <4 x i1> %mask, <4 x i32> %r, <4 x i32> zeroinitializer
   ret <4 x i32>%res
 }
@@ -514,7 +514,7 @@ define <4 x i32> @test_128_20(i8 * %addr, <4 x i32> %mask1) {
 define <2 x i64> @test_128_21(i8 * %addr, <2 x i64> %old, <2 x i64> %mask1) {
   %mask = icmp ne <2 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <2 x i64>*
-  %r = load <2 x i64>* %vaddr, align 16
+  %r = load <2 x i64>, <2 x i64>* %vaddr, align 16
   %res = select <2 x i1> %mask, <2 x i64> %r, <2 x i64> %old
   ret <2 x i64>%res
 }
@@ -525,7 +525,7 @@ define <2 x i64> @test_128_21(i8 * %addr, <2 x i64> %old, <2 x i64> %mask1) {
 define <2 x i64> @test_128_22(i8 * %addr, <2 x i64> %old, <2 x i64> %mask1) {
   %mask = icmp ne <2 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <2 x i64>*
-  %r = load <2 x i64>* %vaddr, align 1
+  %r = load <2 x i64>, <2 x i64>* %vaddr, align 1
   %res = select <2 x i1> %mask, <2 x i64> %r, <2 x i64> %old
   ret <2 x i64>%res
 }
@@ -536,7 +536,7 @@ define <2 x i64> @test_128_22(i8 * %addr, <2 x i64> %old, <2 x i64> %mask1) {
 define <2 x i64> @test_128_23(i8 * %addr, <2 x i64> %mask1) {
   %mask = icmp ne <2 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <2 x i64>*
-  %r = load <2 x i64>* %vaddr, align 16
+  %r = load <2 x i64>, <2 x i64>* %vaddr, align 16
   %res = select <2 x i1> %mask, <2 x i64> %r, <2 x i64> zeroinitializer
   ret <2 x i64>%res
 }
@@ -547,7 +547,7 @@ define <2 x i64> @test_128_23(i8 * %addr, <2 x i64> %mask1) {
 define <2 x i64> @test_128_24(i8 * %addr, <2 x i64> %mask1) {
   %mask = icmp ne <2 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <2 x i64>*
-  %r = load <2 x i64>* %vaddr, align 1
+  %r = load <2 x i64>, <2 x i64>* %vaddr, align 1
   %res = select <2 x i1> %mask, <2 x i64> %r, <2 x i64> zeroinitializer
   ret <2 x i64>%res
 }
@@ -558,7 +558,7 @@ define <2 x i64> @test_128_24(i8 * %addr, <2 x i64> %mask1) {
 define <4 x float> @test_128_25(i8 * %addr, <4 x float> %old, <4 x i32> %mask1) {
   %mask = icmp ne <4 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x float>*
-  %r = load <4 x float>* %vaddr, align 16
+  %r = load <4 x float>, <4 x float>* %vaddr, align 16
   %res = select <4 x i1> %mask, <4 x float> %r, <4 x float> %old
   ret <4 x float>%res
 }
@@ -569,7 +569,7 @@ define <4 x float> @test_128_25(i8 * %addr, <4 x float> %old, <4 x i32> %mask1)
 define <4 x float> @test_128_26(i8 * %addr, <4 x float> %old, <4 x i32> %mask1) {
   %mask = icmp ne <4 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x float>*
-  %r = load <4 x float>* %vaddr, align 1
+  %r = load <4 x float>, <4 x float>* %vaddr, align 1
   %res = select <4 x i1> %mask, <4 x float> %r, <4 x float> %old
   ret <4 x float>%res
 }
@@ -580,7 +580,7 @@ define <4 x float> @test_128_26(i8 * %addr, <4 x float> %old, <4 x i32> %mask1)
 define <4 x float> @test_128_27(i8 * %addr, <4 x i32> %mask1) {
   %mask = icmp ne <4 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x float>*
-  %r = load <4 x float>* %vaddr, align 16
+  %r = load <4 x float>, <4 x float>* %vaddr, align 16
   %res = select <4 x i1> %mask, <4 x float> %r, <4 x float> zeroinitializer
   ret <4 x float>%res
 }
@@ -591,7 +591,7 @@ define <4 x float> @test_128_27(i8 * %addr, <4 x i32> %mask1) {
 define <4 x float> @test_128_28(i8 * %addr, <4 x i32> %mask1) {
   %mask = icmp ne <4 x i32> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <4 x float>*
-  %r = load <4 x float>* %vaddr, align 1
+  %r = load <4 x float>, <4 x float>* %vaddr, align 1
   %res = select <4 x i1> %mask, <4 x float> %r, <4 x float> zeroinitializer
   ret <4 x float>%res
 }
@@ -602,7 +602,7 @@ define <4 x float> @test_128_28(i8 * %addr, <4 x i32> %mask1) {
 define <2 x double> @test_128_29(i8 * %addr, <2 x double> %old, <2 x i64> %mask1) {
   %mask = icmp ne <2 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <2 x double>*
-  %r = load <2 x double>* %vaddr, align 16
+  %r = load <2 x double>, <2 x double>* %vaddr, align 16
   %res = select <2 x i1> %mask, <2 x double> %r, <2 x double> %old
   ret <2 x double>%res
 }
@@ -613,7 +613,7 @@ define <2 x double> @test_128_29(i8 * %addr, <2 x double> %old, <2 x i64> %mask1
 define <2 x double> @test_128_30(i8 * %addr, <2 x double> %old, <2 x i64> %mask1) {
   %mask = icmp ne <2 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <2 x double>*
-  %r = load <2 x double>* %vaddr, align 1
+  %r = load <2 x double>, <2 x double>* %vaddr, align 1
   %res = select <2 x i1> %mask, <2 x double> %r, <2 x double> %old
   ret <2 x double>%res
 }
@@ -624,7 +624,7 @@ define <2 x double> @test_128_30(i8 * %addr, <2 x double> %old, <2 x i64> %mask1
 define <2 x double> @test_128_31(i8 * %addr, <2 x i64> %mask1) {
   %mask = icmp ne <2 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <2 x double>*
-  %r = load <2 x double>* %vaddr, align 16
+  %r = load <2 x double>, <2 x double>* %vaddr, align 16
   %res = select <2 x i1> %mask, <2 x double> %r, <2 x double> zeroinitializer
   ret <2 x double>%res
 }
@@ -635,7 +635,7 @@ define <2 x double> @test_128_31(i8 * %addr, <2 x i64> %mask1) {
 define <2 x double> @test_128_32(i8 * %addr, <2 x i64> %mask1) {
   %mask = icmp ne <2 x i64> %mask1, zeroinitializer
   %vaddr = bitcast i8* %addr to <2 x double>*
-  %r = load <2 x double>* %vaddr, align 1
+  %r = load <2 x double>, <2 x double>* %vaddr, align 1
   %res = select <2 x i1> %mask, <2 x double> %r, <2 x double> zeroinitializer
   ret <2 x double>%res
 }
diff --git a/test/CodeGen/X86/avx512vl-vec-cmp.ll b/test/CodeGen/X86/avx512vl-vec-cmp.ll
index b6b508559ca3..aed8cb1cf559 100644
--- a/test/CodeGen/X86/avx512vl-vec-cmp.ll
+++ b/test/CodeGen/X86/avx512vl-vec-cmp.ll
@@ -45,7 +45,7 @@ define <4 x i64> @test256_4(<4 x i64> %x, <4 x i64> %y, <4 x i64> %x1) nounwind
 ; CHECK: vmovdqa32
 ; CHECK: ret
 define <8 x i32> @test256_5(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %yp) nounwind {
-  %y = load <8 x i32>* %yp, align 4
+  %y = load <8 x i32>, <8 x i32>* %yp, align 4
   %mask = icmp eq <8 x i32> %x, %y
   %max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %x1
   ret <8 x i32> %max
@@ -56,7 +56,7 @@ define <8 x i32> @test256_5(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %yp) nounwin
 ; CHECK: vmovdqa32
 ; CHECK: ret
 define <8 x i32> @test256_6(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %y.ptr) nounwind {
-  %y = load <8 x i32>* %y.ptr, align 4
+  %y = load <8 x i32>, <8 x i32>* %y.ptr, align 4
   %mask = icmp sgt <8 x i32> %x, %y
   %max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %x1
   ret <8 x i32> %max
@@ -67,7 +67,7 @@ define <8 x i32> @test256_6(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %y.ptr) noun
 ; CHECK: vmovdqa32
 ; CHECK: ret
 define <8 x i32> @test256_7(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %y.ptr) nounwind {
-  %y = load <8 x i32>* %y.ptr, align 4
+  %y = load <8 x i32>, <8 x i32>* %y.ptr, align 4
   %mask = icmp sle <8 x i32> %x, %y
   %max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %x1
   ret <8 x i32> %max
@@ -78,7 +78,7 @@ define <8 x i32> @test256_7(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %y.ptr) noun
 ; CHECK: vmovdqa32
 ; CHECK: ret
 define <8 x i32> @test256_8(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %y.ptr) nounwind {
-  %y = load <8 x i32>* %y.ptr, align 4
+  %y = load <8 x i32>, <8 x i32>* %y.ptr, align 4
   %mask = icmp ule <8 x i32> %x, %y
   %max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %x1
   ret <8 x i32> %max
@@ -114,7 +114,7 @@ define <4 x i64> @test256_10(<4 x i64> %x, <4 x i64> %y, <4 x i64> %x1, <4 x i64
 ; CHECK: ret
 define <4 x i64> @test256_11(<4 x i64> %x, <4 x i64>* %y.ptr, <4 x i64> %x1, <4 x i64> %y1) nounwind {
   %mask1 = icmp sgt <4 x i64> %x1, %y1
-  %y = load <4 x i64>* %y.ptr, align 4
+  %y = load <4 x i64>, <4 x i64>* %y.ptr, align 4
   %mask0 = icmp sgt <4 x i64> %x, %y
   %mask = select <4 x i1> %mask0, <4 x i1> %mask1, <4 x i1> zeroinitializer
   %max = select <4 x i1> %mask, <4 x i64> %x, <4 x i64> %x1
@@ -127,7 +127,7 @@ define <4 x i64> @test256_11(<4 x i64> %x, <4 x i64>* %y.ptr, <4 x i64> %x1, <4
 ; CHECK: ret
 define <8 x i32> @test256_12(<8 x i32> %x, <8 x i32>* %y.ptr, <8 x i32> %x1, <8 x i32> %y1) nounwind {
   %mask1 = icmp sge <8 x i32> %x1, %y1
-  %y = load <8 x i32>* %y.ptr, align 4
+  %y = load <8 x i32>, <8 x i32>* %y.ptr, align 4
   %mask0 = icmp ule <8 x i32> %x, %y
   %mask = select <8 x i1> %mask0, <8 x i1> %mask1, <8 x i1> zeroinitializer
   %max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %x1
@@ -139,7 +139,7 @@ define <8 x i32> @test256_12(<8 x i32> %x, <8 x i32>* %y.ptr, <8 x i32> %x1, <8
 ; CHECK: vmovdqa64
 ; CHECK: ret
 define <4 x i64> @test256_13(<4 x i64> %x, <4 x i64> %x1, i64* %yb.ptr) nounwind {
-  %yb = load i64* %yb.ptr, align 4
+  %yb = load i64, i64* %yb.ptr, align 4
   %y.0 = insertelement <4 x i64> undef, i64 %yb, i32 0
   %y = shufflevector <4 x i64> %y.0, <4 x i64> undef, <4 x i32> zeroinitializer
   %mask = icmp eq <4 x i64> %x, %y
@@ -152,7 +152,7 @@ define <4 x i64> @test256_13(<4 x i64> %x, <4 x i64> %x1, i64* %yb.ptr) nounwind
 ; CHECK: vmovdqa32
 ; CHECK: ret
 define <8 x i32> @test256_14(<8 x i32> %x, i32* %yb.ptr, <8 x i32> %x1) nounwind {
-  %yb = load i32* %yb.ptr, align 4
+  %yb = load i32, i32* %yb.ptr, align 4
   %y.0 = insertelement <8 x i32> undef, i32 %yb, i32 0
   %y = shufflevector <8 x i32> %y.0, <8 x i32> undef, <8 x i32> zeroinitializer
   %mask = icmp sle <8 x i32> %x, %y
@@ -166,7 +166,7 @@ define <8 x i32> @test256_14(<8 x i32> %x, i32* %yb.ptr, <8 x i32> %x1) nounwind
 ; CHECK: ret
 define <8 x i32> @test256_15(<8 x i32> %x, i32* %yb.ptr, <8 x i32> %x1, <8 x i32> %y1) nounwind {
   %mask1 = icmp sge <8 x i32> %x1, %y1
-  %yb = load i32* %yb.ptr, align 4
+  %yb = load i32, i32* %yb.ptr, align 4
   %y.0 = insertelement <8 x i32> undef, i32 %yb, i32 0
   %y = shufflevector <8 x i32> %y.0, <8 x i32> undef, <8 x i32> zeroinitializer
   %mask0 = icmp sgt <8 x i32> %x, %y
@@ -181,7 +181,7 @@ define <8 x i32> @test256_15(<8 x i32> %x, i32* %yb.ptr, <8 x i32> %x1, <8 x i32
 ; CHECK: ret
 define <4 x i64> @test256_16(<4 x i64> %x, i64* %yb.ptr, <4 x i64> %x1, <4 x i64> %y1) nounwind {
   %mask1 = icmp sge <4 x i64> %x1, %y1
-  %yb = load i64* %yb.ptr, align 4
+  %yb = load i64, i64* %yb.ptr, align 4
   %y.0 = insertelement <4 x i64> undef, i64 %yb, i32 0
   %y = shufflevector <4 x i64> %y.0, <4 x i64> undef, <4 x i32> zeroinitializer
   %mask0 = icmp sgt <4 x i64> %x, %y
@@ -235,7 +235,7 @@ define <2 x i64> @test128_4(<2 x i64> %x, <2 x i64> %y, <2 x i64> %x1) nounwind
 ; CHECK: vmovdqa32
 ; CHECK: ret
 define <4 x i32> @test128_5(<4 x i32> %x, <4 x i32> %x1, <4 x i32>* %yp) nounwind {
-  %y = load <4 x i32>* %yp, align 4
+  %y = load <4 x i32>, <4 x i32>* %yp, align 4
   %mask = icmp eq <4 x i32> %x, %y
   %max = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %x1
   ret <4 x i32> %max
@@ -246,7 +246,7 @@ define <4 x i32> @test128_5(<4 x i32> %x, <4 x i32> %x1, <4 x i32>* %yp) nounwin
 ; CHECK: vmovdqa32
 ; CHECK: ret
 define <4 x i32> @test128_6(<4 x i32> %x, <4 x i32> %x1, <4 x i32>* %y.ptr) nounwind {
-  %y = load <4 x i32>* %y.ptr, align 4
+  %y = load <4 x i32>, <4 x i32>* %y.ptr, align 4
   %mask = icmp sgt <4 x i32> %x, %y
   %max = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %x1
   ret <4 x i32> %max
@@ -257,7 +257,7 @@ define <4 x i32> @test128_6(<4 x i32> %x, <4 x i32> %x1, <4 x i32>* %y.ptr) noun
 ; CHECK: vmovdqa32
 ; CHECK: ret
 define <4 x i32> @test128_7(<4 x i32> %x, <4 x i32> %x1, <4 x i32>* %y.ptr) nounwind {
-  %y = load <4 x i32>* %y.ptr, align 4
+  %y = load <4 x i32>, <4 x i32>* %y.ptr, align 4
   %mask = icmp sle <4 x i32> %x, %y
   %max = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %x1
   ret <4 x i32> %max
@@ -268,7 +268,7 @@ define <4 x i32> @test128_7(<4 x i32> %x, <4 x i32> %x1, <4 x i32>* %y.ptr) noun
 ; CHECK: vmovdqa32
 ; CHECK: ret
 define <4 x i32> @test128_8(<4 x i32> %x, <4 x i32> %x1, <4 x i32>* %y.ptr) nounwind {
-  %y = load <4 x i32>* %y.ptr, align 4
+  %y = load <4 x i32>, <4 x i32>* %y.ptr, align 4
   %mask = icmp ule <4 x i32> %x, %y
   %max = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %x1
   ret <4 x i32> %max
@@ -304,7 +304,7 @@ define <2 x i64> @test128_10(<2 x i64> %x, <2 x i64> %y, <2 x i64> %x1, <2 x i64
 ; CHECK: ret
 define <2 x i64> @test128_11(<2 x i64> %x, <2 x i64>* %y.ptr, <2 x i64> %x1, <2 x i64> %y1) nounwind {
   %mask1 = icmp sgt <2 x i64> %x1, %y1
-  %y = load <2 x i64>* %y.ptr, align 4
+  %y = load <2 x i64>, <2 x i64>* %y.ptr, align 4
   %mask0 = icmp sgt <2 x i64> %x, %y
   %mask = select <2 x i1> %mask0, <2 x i1> %mask1, <2 x i1> zeroinitializer
   %max = select <2 x i1> %mask, <2 x i64> %x, <2 x i64> %x1
@@ -317,7 +317,7 @@ define <2 x i64> @test128_11(<2 x i64> %x, <2 x i64>* %y.ptr, <2 x i64> %x1, <2
 ; CHECK: ret
 define <4 x i32> @test128_12(<4 x i32> %x, <4 x i32>* %y.ptr, <4 x i32> %x1, <4 x i32> %y1) nounwind {
   %mask1 = icmp sge <4 x i32> %x1, %y1
-  %y = load <4 x i32>* %y.ptr, align 4
+  %y = load <4 x i32>, <4 x i32>* %y.ptr, align 4
   %mask0 = icmp ule <4 x i32> %x, %y
   %mask = select <4 x i1> %mask0, <4 x i1> %mask1, <4 x i1> zeroinitializer
   %max = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %x1
@@ -329,7 +329,7 @@ define <4 x i32> @test128_12(<4 x i32> %x, <4 x i32>* %y.ptr, <4 x i32> %x1, <4
 ; CHECK: vmovdqa64
 ; CHECK: ret
 define <2 x i64> @test128_13(<2 x i64> %x, <2 x i64> %x1, i64* %yb.ptr) nounwind {
-  %yb = load i64* %yb.ptr, align 4
+  %yb = load i64, i64* %yb.ptr, align 4
   %y.0 = insertelement <2 x i64> undef, i64 %yb, i32 0
   %y = insertelement <2 x i64> %y.0, i64 %yb, i32 1
   %mask = icmp eq <2 x i64> %x, %y
@@ -342,7 +342,7 @@ define <2 x i64> @test128_13(<2 x i64> %x, <2 x i64> %x1, i64* %yb.ptr) nounwind
 ; CHECK: vmovdqa32
 ; CHECK: ret
 define <4 x i32> @test128_14(<4 x i32> %x, i32* %yb.ptr, <4 x i32> %x1) nounwind {
-  %yb = load i32* %yb.ptr, align 4
+  %yb = load i32, i32* %yb.ptr, align 4
   %y.0 = insertelement <4 x i32> undef, i32 %yb, i32 0
   %y = shufflevector <4 x i32> %y.0, <4 x i32> undef, <4 x i32> zeroinitializer
   %mask = icmp sle <4 x i32> %x, %y
@@ -356,7 +356,7 @@ define <4 x i32> @test128_14(<4 x i32> %x, i32* %yb.ptr, <4 x i32> %x1) nounwind
 ; CHECK: ret
 define <4 x i32> @test128_15(<4 x i32> %x, i32* %yb.ptr, <4 x i32> %x1, <4 x i32> %y1) nounwind {
   %mask1 = icmp sge <4 x i32> %x1, %y1
-  %yb = load i32* %yb.ptr, align 4
+  %yb = load i32, i32* %yb.ptr, align 4
   %y.0 = insertelement <4 x i32> undef, i32 %yb, i32 0
   %y = shufflevector <4 x i32> %y.0, <4 x i32> undef, <4 x i32> zeroinitializer
   %mask0 = icmp sgt <4 x i32> %x, %y
@@ -371,7 +371,7 @@ define <4 x i32> @test128_15(<4 x i32> %x, i32* %yb.ptr, <4 x i32> %x1, <4 x i32
 ; CHECK: ret
 define <2 x i64> @test128_16(<2 x i64> %x, i64* %yb.ptr, <2 x i64> %x1, <2 x i64> %y1) nounwind {
   %mask1 = icmp sge <2 x i64> %x1, %y1
-  %yb = load i64* %yb.ptr, align 4
+  %yb = load i64, i64* %yb.ptr, align 4
   %y.0 = insertelement <2 x i64> undef, i64 %yb, i32 0
   %y = insertelement <2 x i64> %y.0, i64 %yb, i32 1
   %mask0 = icmp sgt <2 x i64> %x, %y
diff --git a/test/CodeGen/X86/barrier.ll b/test/CodeGen/X86/barrier.ll
index 4769b39964a0..1f60131f33ca 100644
--- a/test/CodeGen/X86/barrier.ll
+++ b/test/CodeGen/X86/barrier.ll
@@ -1,6 +1,7 @@
-; RUN: llc < %s -march=x86 -mattr=-sse2 | grep lock
+; RUN: llc < %s -march=x86 -mattr=-sse2 | FileCheck %s
 
 define void @test() {
+; CHECK: lock
 	fence seq_cst
 	ret void
 }
diff --git a/test/CodeGen/X86/bitcast-mmx.ll b/test/CodeGen/X86/bitcast-mmx.ll
new file mode 100644
index 000000000000..4107f3914f81
--- /dev/null
+++ b/test/CodeGen/X86/bitcast-mmx.ll
@@ -0,0 +1,77 @@
+; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | FileCheck %s
+
+define i32 @t0(i64 %x) {
+; CHECK-LABEL: t0:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    movd %[[REG1:[a-z]+]], %mm0
+; CHECK-NEXT:    pshufw $238, %mm0, %mm0
+; CHECK-NEXT:    movd %mm0, %eax
+; CHECK-NEXT:    retq
+entry:
+  %0 = bitcast i64 %x to <4 x i16>
+  %1 = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -18)
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  %6 = bitcast i64 %5 to <2 x i32>
+  %7 = extractelement <2 x i32> %6, i32 0
+  ret i32 %7
+}
+
+define i64 @t1(i64 %x, i32 %n) {
+; CHECK-LABEL: t1:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    movd %[[REG2:[a-z]+]], %mm0
+; CHECK-NEXT:    movd %[[REG1]], %mm1
+; CHECK-NEXT:    psllq %mm0, %mm1
+; CHECK-NEXT:    movd %mm1, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = bitcast i64 %x to x86_mmx
+  %1 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %0, i32 %n)
+  %2 = bitcast x86_mmx %1 to i64
+  ret i64 %2
+}
+
+define i64 @t2(i64 %x, i32 %n, i32 %w) {
+; CHECK-LABEL: t2:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:  movd %[[REG4:[a-z]+]], %mm0
+; CHECK-NEXT:  movd %[[REG6:[a-z0-9]+]], %mm1
+; CHECK-NEXT:  psllq %mm0, %mm1
+; CHECK-NEXT:  movd %[[REG1]], %mm0
+; CHECK-NEXT:  por %mm1, %mm0
+; CHECK-NEXT:  movd %mm0, %rax
+; CHECK-NEXT:  retq
+entry:
+  %0 = insertelement <2 x i32> undef, i32 %w, i32 0
+  %1 = insertelement <2 x i32> %0, i32 0, i32 1
+  %2 = bitcast <2 x i32> %1 to x86_mmx
+  %3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %2, i32 %n)
+  %4 = bitcast i64 %x to x86_mmx
+  %5 = tail call x86_mmx @llvm.x86.mmx.por(x86_mmx %4, x86_mmx %3)
+  %6 = bitcast x86_mmx %5 to i64
+  ret i64 %6
+}
+
+define i64 @t3(<1 x i64>* %y, i32* %n) {
+; CHECK-LABEL: t3:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    movq (%[[REG1]]), %mm0
+; CHECK-NEXT:    psllq (%[[REG3:[a-z]+]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = bitcast <1 x i64>* %y to x86_mmx*
+  %1 = load x86_mmx, x86_mmx* %0, align 8
+  %2 = load i32, i32* %n, align 4
+  %3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %1, i32 %2)
+  %4 = bitcast x86_mmx %3 to i64
+  ret i64 %4
+}
+
+declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)
+declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
+declare x86_mmx @llvm.x86.mmx.por(x86_mmx, x86_mmx)
+
diff --git a/test/CodeGen/X86/block-placement.ll b/test/CodeGen/X86/block-placement.ll
index e35be6ae654f..e0276e42d4d2 100644
--- a/test/CodeGen/X86/block-placement.ll
+++ b/test/CodeGen/X86/block-placement.ll
@@ -24,8 +24,8 @@ define i32 @test_ifchains(i32 %i, i32* %a, i32 %b) {
 ; CHECK: %then5
 
 entry:
-  %gep1 = getelementptr i32* %a, i32 1
-  %val1 = load i32* %gep1
+  %gep1 = getelementptr i32, i32* %a, i32 1
+  %val1 = load i32, i32* %gep1
   %cond1 = icmp ugt i32 %val1, 1
   br i1 %cond1, label %then1, label %else1, !prof !0
 
@@ -34,8 +34,8 @@ then1:
   br label %else1
 
 else1:
-  %gep2 = getelementptr i32* %a, i32 2
-  %val2 = load i32* %gep2
+  %gep2 = getelementptr i32, i32* %a, i32 2
+  %val2 = load i32, i32* %gep2
   %cond2 = icmp ugt i32 %val2, 2
   br i1 %cond2, label %then2, label %else2, !prof !0
 
@@ -44,8 +44,8 @@ then2:
   br label %else2
 
 else2:
-  %gep3 = getelementptr i32* %a, i32 3
-  %val3 = load i32* %gep3
+  %gep3 = getelementptr i32, i32* %a, i32 3
+  %val3 = load i32, i32* %gep3
   %cond3 = icmp ugt i32 %val3, 3
   br i1 %cond3, label %then3, label %else3, !prof !0
 
@@ -54,8 +54,8 @@ then3:
   br label %else3
 
 else3:
-  %gep4 = getelementptr i32* %a, i32 4
-  %val4 = load i32* %gep4
+  %gep4 = getelementptr i32, i32* %a, i32 4
+  %val4 = load i32, i32* %gep4
   %cond4 = icmp ugt i32 %val4, 4
   br i1 %cond4, label %then4, label %else4, !prof !0
 
@@ -64,8 +64,8 @@ then4:
   br label %else4
 
 else4:
-  %gep5 = getelementptr i32* %a, i32 3
-  %val5 = load i32* %gep5
+  %gep5 = getelementptr i32, i32* %a, i32 3
+  %val5 = load i32, i32* %gep5
   %cond5 = icmp ugt i32 %val5, 3
   br i1 %cond5, label %then5, label %exit, !prof !0
 
@@ -113,8 +113,8 @@ unlikely2:
   br label %body3
 
 body3:
-  %arrayidx = getelementptr inbounds i32* %a, i32 %iv
-  %0 = load i32* %arrayidx
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %iv
+  %0 = load i32, i32* %arrayidx
   %sum = add nsw i32 %0, %base
   %next = add i32 %iv, 1
   %exitcond = icmp eq i32 %next, %i
@@ -166,8 +166,8 @@ bail3:
   ret i32 -3
 
 body4:
-  %arrayidx = getelementptr inbounds i32* %a, i32 %iv
-  %0 = load i32* %arrayidx
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %iv
+  %0 = load i32, i32* %arrayidx
   %sum = add nsw i32 %0, %base
   %next = add i32 %iv, 1
   %exitcond = icmp eq i32 %next, %i
@@ -197,8 +197,8 @@ body0:
   br i1 %exitcond, label %exit, label %body1
 
 body1:
-  %arrayidx = getelementptr inbounds i32* %a, i32 %iv
-  %0 = load i32* %arrayidx
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %iv
+  %0 = load i32, i32* %arrayidx
   %sum = add nsw i32 %0, %base
   %bailcond1 = icmp eq i32 %sum, 42
   br label %body0
@@ -222,8 +222,8 @@ entry:
 body0:
   %iv = phi i32 [ 0, %entry ], [ %next, %body1 ]
   %base = phi i32 [ 0, %entry ], [ %sum, %body1 ]
-  %arrayidx = getelementptr inbounds i32* %a, i32 %iv
-  %0 = load i32* %arrayidx
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %iv
+  %0 = load i32, i32* %arrayidx
   %sum = add nsw i32 %0, %base
   %bailcond1 = icmp eq i32 %sum, 42
   br i1 %bailcond1, label %exit, label %body1
@@ -252,8 +252,8 @@ entry:
 body:
   %iv = phi i32 [ 0, %entry ], [ %next, %body ]
   %base = phi i32 [ 0, %entry ], [ %sum, %body ]
-  %arrayidx = getelementptr inbounds i32* %a, i32 %iv
-  %0 = load i32* %arrayidx
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %iv
+  %0 = load i32, i32* %arrayidx
   %sum = add nsw i32 %0, %base
   %next = add i32 %iv, 1
   %exitcond = icmp eq i32 %next, %i
@@ -279,16 +279,16 @@ entry:
 
 loop.body.1:
   %iv = phi i32 [ 0, %entry ], [ %next, %loop.body.2 ]
-  %arrayidx = getelementptr inbounds i32* %a, i32 %iv
-  %bidx = load i32* %arrayidx
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %iv
+  %bidx = load i32, i32* %arrayidx
   br label %inner.loop.body
 
 inner.loop.body:
   %inner.iv = phi i32 [ 0, %loop.body.1 ], [ %inner.next, %inner.loop.body ]
   %base = phi i32 [ 0, %loop.body.1 ], [ %sum, %inner.loop.body ]
   %scaled_idx = mul i32 %bidx, %iv
-  %inner.arrayidx = getelementptr inbounds i32* %b, i32 %scaled_idx
-  %0 = load i32* %inner.arrayidx
+  %inner.arrayidx = getelementptr inbounds i32, i32* %b, i32 %scaled_idx
+  %0 = load i32, i32* %inner.arrayidx
   %sum = add nsw i32 %0, %base
   %inner.next = add i32 %iv, 1
   %inner.exitcond = icmp eq i32 %inner.next, %i
@@ -322,13 +322,13 @@ loop.body1:
   br i1 undef, label %loop.body3, label %loop.body2
 
 loop.body2:
-  %ptr = load i32** undef, align 4
+  %ptr = load i32*, i32** undef, align 4
   br label %loop.body3
 
 loop.body3:
   %myptr = phi i32* [ %ptr2, %loop.body5 ], [ %ptr, %loop.body2 ], [ undef, %loop.body1 ]
   %bcmyptr = bitcast i32* %myptr to i32*
-  %val = load i32* %bcmyptr, align 4
+  %val = load i32, i32* %bcmyptr, align 4
   %comp = icmp eq i32 %val, 48
   br i1 %comp, label %loop.body4, label %loop.body5
 
@@ -336,7 +336,7 @@ loop.body4:
   br i1 undef, label %loop.header, label %loop.body5
 
 loop.body5:
-  %ptr2 = load i32** undef, align 4
+  %ptr2 = load i32*, i32** undef, align 4
   br label %loop.body3
 }
 
@@ -366,16 +366,16 @@ loop.header:
   br i1 %comp0, label %bail, label %loop.body1
 
 loop.body1:
-  %val0 = load i32** undef, align 4
+  %val0 = load i32*, i32** undef, align 4
   br i1 undef, label %loop.body2, label %loop.inner1.begin
 
 loop.body2:
   br i1 undef, label %loop.body4, label %loop.body3
 
 loop.body3:
-  %ptr1 = getelementptr inbounds i32* %val0, i32 0
+  %ptr1 = getelementptr inbounds i32, i32* %val0, i32 0
   %castptr1 = bitcast i32* %ptr1 to i32**
-  %val1 = load i32** %castptr1, align 4
+  %val1 = load i32*, i32** %castptr1, align 4
   br label %loop.inner1.begin
 
 loop.inner1.begin:
@@ -385,9 +385,9 @@ loop.inner1.begin:
   br i1 %comp1, label %loop.inner1.end, label %loop.body4
 
 loop.inner1.end:
-  %ptr2 = getelementptr inbounds i32* %valphi, i32 0
+  %ptr2 = getelementptr inbounds i32, i32* %valphi, i32 0
   %castptr2 = bitcast i32* %ptr2 to i32**
-  %val2 = load i32** %castptr2, align 4
+  %val2 = load i32*, i32** %castptr2, align 4
   br label %loop.inner1.begin
 
 loop.body4.dead:
@@ -486,7 +486,7 @@ entry:
   br i1 %cond, label %entry.if.then_crit_edge, label %lor.lhs.false, !prof !1
 
 entry.if.then_crit_edge:
-  %.pre14 = load i8* undef, align 1
+  %.pre14 = load i8, i8* undef, align 1
   br label %if.then
 
 lor.lhs.false:
@@ -616,7 +616,7 @@ body:
   br label %loop2a
 
 loop1:
-  %next.load = load i32** undef
+  %next.load = load i32*, i32** undef
   br i1 %comp.a, label %loop2a, label %loop2b
 
 loop2a:
@@ -626,7 +626,7 @@ loop2a:
   br label %loop3
 
 loop2b:
-  %gep = getelementptr inbounds i32* %var.phi, i32 0
+  %gep = getelementptr inbounds i32, i32* %var.phi, i32 0
   %next.ptr = bitcast i32* %gep to i32**
   store i32* %next.phi, i32** %next.ptr
   br label %loop3
@@ -728,199 +728,199 @@ define void @many_unanalyzable_branches() {
 entry:
   br label %0
 
-  %val0 = load volatile float* undef
+  %val0 = load volatile float, float* undef
   %cmp0 = fcmp une float %val0, undef
   br i1 %cmp0, label %1, label %0
-  %val1 = load volatile float* undef
+  %val1 = load volatile float, float* undef
   %cmp1 = fcmp une float %val1, undef
   br i1 %cmp1, label %2, label %1
-  %val2 = load volatile float* undef
+  %val2 = load volatile float, float* undef
   %cmp2 = fcmp une float %val2, undef
   br i1 %cmp2, label %3, label %2
-  %val3 = load volatile float* undef
+  %val3 = load volatile float, float* undef
   %cmp3 = fcmp une float %val3, undef
   br i1 %cmp3, label %4, label %3
-  %val4 = load volatile float* undef
+  %val4 = load volatile float, float* undef
   %cmp4 = fcmp une float %val4, undef
   br i1 %cmp4, label %5, label %4
-  %val5 = load volatile float* undef
+  %val5 = load volatile float, float* undef
   %cmp5 = fcmp une float %val5, undef
   br i1 %cmp5, label %6, label %5
-  %val6 = load volatile float* undef
+  %val6 = load volatile float, float* undef
   %cmp6 = fcmp une float %val6, undef
   br i1 %cmp6, label %7, label %6
-  %val7 = load volatile float* undef
+  %val7 = load volatile float, float* undef
   %cmp7 = fcmp une float %val7, undef
   br i1 %cmp7, label %8, label %7
-  %val8 = load volatile float* undef
+  %val8 = load volatile float, float* undef
   %cmp8 = fcmp une float %val8, undef
   br i1 %cmp8, label %9, label %8
-  %val9 = load volatile float* undef
+  %val9 = load volatile float, float* undef
   %cmp9 = fcmp une float %val9, undef
   br i1 %cmp9, label %10, label %9
-  %val10 = load volatile float* undef
+  %val10 = load volatile float, float* undef
   %cmp10 = fcmp une float %val10, undef
   br i1 %cmp10, label %11, label %10
-  %val11 = load volatile float* undef
+  %val11 = load volatile float, float* undef
   %cmp11 = fcmp une float %val11, undef
   br i1 %cmp11, label %12, label %11
-  %val12 = load volatile float* undef
+  %val12 = load volatile float, float* undef
   %cmp12 = fcmp une float %val12, undef
   br i1 %cmp12, label %13, label %12
-  %val13 = load volatile float* undef
+  %val13 = load volatile float, float* undef
   %cmp13 = fcmp une float %val13, undef
   br i1 %cmp13, label %14, label %13
-  %val14 = load volatile float* undef
+  %val14 = load volatile float, float* undef
   %cmp14 = fcmp une float %val14, undef
   br i1 %cmp14, label %15, label %14
-  %val15 = load volatile float* undef
+  %val15 = load volatile float, float* undef
   %cmp15 = fcmp une float %val15, undef
   br i1 %cmp15, label %16, label %15
-  %val16 = load volatile float* undef
+  %val16 = load volatile float, float* undef
   %cmp16 = fcmp une float %val16, undef
   br i1 %cmp16, label %17, label %16
-  %val17 = load volatile float* undef
+  %val17 = load volatile float, float* undef
   %cmp17 = fcmp une float %val17, undef
   br i1 %cmp17, label %18, label %17
-  %val18 = load volatile float* undef
+  %val18 = load volatile float, float* undef
   %cmp18 = fcmp une float %val18, undef
   br i1 %cmp18, label %19, label %18
-  %val19 = load volatile float* undef
+  %val19 = load volatile float, float* undef
   %cmp19 = fcmp une float %val19, undef
   br i1 %cmp19, label %20, label %19
-  %val20 = load volatile float* undef
+  %val20 = load volatile float, float* undef
   %cmp20 = fcmp une float %val20, undef
   br i1 %cmp20, label %21, label %20
-  %val21 = load volatile float* undef
+  %val21 = load volatile float, float* undef
   %cmp21 = fcmp une float %val21, undef
   br i1 %cmp21, label %22, label %21
-  %val22 = load volatile float* undef
+  %val22 = load volatile float, float* undef
   %cmp22 = fcmp une float %val22, undef
   br i1 %cmp22, label %23, label %22
-  %val23 = load volatile float* undef
+  %val23 = load volatile float, float* undef
   %cmp23 = fcmp une float %val23, undef
   br i1 %cmp23, label %24, label %23
-  %val24 = load volatile float* undef
+  %val24 = load volatile float, float* undef
   %cmp24 = fcmp une float %val24, undef
   br i1 %cmp24, label %25, label %24
-  %val25 = load volatile float* undef
+  %val25 = load volatile float, float* undef
   %cmp25 = fcmp une float %val25, undef
   br i1 %cmp25, label %26, label %25
-  %val26 = load volatile float* undef
+  %val26 = load volatile float, float* undef
   %cmp26 = fcmp une float %val26, undef
   br i1 %cmp26, label %27, label %26
-  %val27 = load volatile float* undef
+  %val27 = load volatile float, float* undef
   %cmp27 = fcmp une float %val27, undef
   br i1 %cmp27, label %28, label %27
-  %val28 = load volatile float* undef
+  %val28 = load volatile float, float* undef
   %cmp28 = fcmp une float %val28, undef
   br i1 %cmp28, label %29, label %28
-  %val29 = load volatile float* undef
+  %val29 = load volatile float, float* undef
   %cmp29 = fcmp une float %val29, undef
   br i1 %cmp29, label %30, label %29
-  %val30 = load volatile float* undef
+  %val30 = load volatile float, float* undef
   %cmp30 = fcmp une float %val30, undef
   br i1 %cmp30, label %31, label %30
-  %val31 = load volatile float* undef
+  %val31 = load volatile float, float* undef
   %cmp31 = fcmp une float %val31, undef
   br i1 %cmp31, label %32, label %31
-  %val32 = load volatile float* undef
+  %val32 = load volatile float, float* undef
   %cmp32 = fcmp une float %val32, undef
   br i1 %cmp32, label %33, label %32
-  %val33 = load volatile float* undef
+  %val33 = load volatile float, float* undef
   %cmp33 = fcmp une float %val33, undef
   br i1 %cmp33, label %34, label %33
-  %val34 = load volatile float* undef
+  %val34 = load volatile float, float* undef
   %cmp34 = fcmp une float %val34, undef
   br i1 %cmp34, label %35, label %34
-  %val35 = load volatile float* undef
+  %val35 = load volatile float, float* undef
   %cmp35 = fcmp une float %val35, undef
   br i1 %cmp35, label %36, label %35
-  %val36 = load volatile float* undef
+  %val36 = load volatile float, float* undef
   %cmp36 = fcmp une float %val36, undef
   br i1 %cmp36, label %37, label %36
-  %val37 = load volatile float* undef
+  %val37 = load volatile float, float* undef
   %cmp37 = fcmp une float %val37, undef
   br i1 %cmp37, label %38, label %37
-  %val38 = load volatile float* undef
+  %val38 = load volatile float, float* undef
   %cmp38 = fcmp une float %val38, undef
   br i1 %cmp38, label %39, label %38
-  %val39 = load volatile float* undef
+  %val39 = load volatile float, float* undef
   %cmp39 = fcmp une float %val39, undef
   br i1 %cmp39, label %40, label %39
-  %val40 = load volatile float* undef
+  %val40 = load volatile float, float* undef
   %cmp40 = fcmp une float %val40, undef
   br i1 %cmp40, label %41, label %40
-  %val41 = load volatile float* undef
+  %val41 = load volatile float, float* undef
   %cmp41 = fcmp une float %val41, undef
   br i1 %cmp41, label %42, label %41
-  %val42 = load volatile float* undef
+  %val42 = load volatile float, float* undef
   %cmp42 = fcmp une float %val42, undef
   br i1 %cmp42, label %43, label %42
-  %val43 = load volatile float* undef
+  %val43 = load volatile float, float* undef
   %cmp43 = fcmp une float %val43, undef
   br i1 %cmp43, label %44, label %43
-  %val44 = load volatile float* undef
+  %val44 = load volatile float, float* undef
   %cmp44 = fcmp une float %val44, undef
   br i1 %cmp44, label %45, label %44
-  %val45 = load volatile float* undef
+  %val45 = load volatile float, float* undef
   %cmp45 = fcmp une float %val45, undef
   br i1 %cmp45, label %46, label %45
-  %val46 = load volatile float* undef
+  %val46 = load volatile float, float* undef
   %cmp46 = fcmp une float %val46, undef
   br i1 %cmp46, label %47, label %46
-  %val47 = load volatile float* undef
+  %val47 = load volatile float, float* undef
   %cmp47 = fcmp une float %val47, undef
   br i1 %cmp47, label %48, label %47
-  %val48 = load volatile float* undef
+  %val48 = load volatile float, float* undef
   %cmp48 = fcmp une float %val48, undef
   br i1 %cmp48, label %49, label %48
-  %val49 = load volatile float* undef
+  %val49 = load volatile float, float* undef
   %cmp49 = fcmp une float %val49, undef
   br i1 %cmp49, label %50, label %49
-  %val50 = load volatile float* undef
+  %val50 = load volatile float, float* undef
   %cmp50 = fcmp une float %val50, undef
   br i1 %cmp50, label %51, label %50
-  %val51 = load volatile float* undef
+  %val51 = load volatile float, float* undef
   %cmp51 = fcmp une float %val51, undef
   br i1 %cmp51, label %52, label %51
-  %val52 = load volatile float* undef
+  %val52 = load volatile float, float* undef
   %cmp52 = fcmp une float %val52, undef
   br i1 %cmp52, label %53, label %52
-  %val53 = load volatile float* undef
+  %val53 = load volatile float, float* undef
   %cmp53 = fcmp une float %val53, undef
   br i1 %cmp53, label %54, label %53
-  %val54 = load volatile float* undef
+  %val54 = load volatile float, float* undef
   %cmp54 = fcmp une float %val54, undef
   br i1 %cmp54, label %55, label %54
-  %val55 = load volatile float* undef
+  %val55 = load volatile float, float* undef
   %cmp55 = fcmp une float %val55, undef
   br i1 %cmp55, label %56, label %55
-  %val56 = load volatile float* undef
+  %val56 = load volatile float, float* undef
   %cmp56 = fcmp une float %val56, undef
   br i1 %cmp56, label %57, label %56
-  %val57 = load volatile float* undef
+  %val57 = load volatile float, float* undef
   %cmp57 = fcmp une float %val57, undef
   br i1 %cmp57, label %58, label %57
-  %val58 = load volatile float* undef
+  %val58 = load volatile float, float* undef
   %cmp58 = fcmp une float %val58, undef
   br i1 %cmp58, label %59, label %58
-  %val59 = load volatile float* undef
+  %val59 = load volatile float, float* undef
   %cmp59 = fcmp une float %val59, undef
   br i1 %cmp59, label %60, label %59
-  %val60 = load volatile float* undef
+  %val60 = load volatile float, float* undef
   %cmp60 = fcmp une float %val60, undef
   br i1 %cmp60, label %61, label %60
-  %val61 = load volatile float* undef
+  %val61 = load volatile float, float* undef
   %cmp61 = fcmp une float %val61, undef
   br i1 %cmp61, label %62, label %61
-  %val62 = load volatile float* undef
+  %val62 = load volatile float, float* undef
   %cmp62 = fcmp une float %val62, undef
   br i1 %cmp62, label %63, label %62
-  %val63 = load volatile float* undef
+  %val63 = load volatile float, float* undef
   %cmp63 = fcmp une float %val63, undef
   br i1 %cmp63, label %64, label %63
-  %val64 = load volatile float* undef
+  %val64 = load volatile float, float* undef
   %cmp64 = fcmp une float %val64, undef
   br i1 %cmp64, label %65, label %64
 
@@ -966,7 +966,7 @@ define void @benchmark_heapsort(i32 %n, double* nocapture %ra) {
 entry:
   %shr = ashr i32 %n, 1
   %add = add nsw i32 %shr, 1
-  %arrayidx3 = getelementptr inbounds double* %ra, i64 1
+  %arrayidx3 = getelementptr inbounds double, double* %ra, i64 1
   br label %for.cond
 
 for.cond:
@@ -978,15 +978,15 @@ for.cond:
 if.then:
   %dec = add nsw i32 %l.0, -1
   %idxprom = sext i32 %dec to i64
-  %arrayidx = getelementptr inbounds double* %ra, i64 %idxprom
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %ra, i64 %idxprom
+  %0 = load double, double* %arrayidx, align 8
   br label %if.end10
 
 if.else:
   %idxprom1 = sext i32 %ir.0 to i64
-  %arrayidx2 = getelementptr inbounds double* %ra, i64 %idxprom1
-  %1 = load double* %arrayidx2, align 8
-  %2 = load double* %arrayidx3, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %ra, i64 %idxprom1
+  %1 = load double, double* %arrayidx2, align 8
+  %2 = load double, double* %arrayidx3, align 8
   store double %2, double* %arrayidx2, align 8
   %dec6 = add nsw i32 %ir.0, -1
   %cmp7 = icmp eq i32 %dec6, 1
@@ -1019,12 +1019,12 @@ while.body:
 
 land.lhs.true:
   %idxprom13 = sext i32 %j.0 to i64
-  %arrayidx14 = getelementptr inbounds double* %ra, i64 %idxprom13
-  %3 = load double* %arrayidx14, align 8
+  %arrayidx14 = getelementptr inbounds double, double* %ra, i64 %idxprom13
+  %3 = load double, double* %arrayidx14, align 8
   %add15 = add nsw i32 %j.0, 1
   %idxprom16 = sext i32 %add15 to i64
-  %arrayidx17 = getelementptr inbounds double* %ra, i64 %idxprom16
-  %4 = load double* %arrayidx17, align 8
+  %arrayidx17 = getelementptr inbounds double, double* %ra, i64 %idxprom16
+  %4 = load double, double* %arrayidx17, align 8
   %cmp18 = fcmp olt double %3, %4
   br i1 %cmp18, label %if.then19, label %if.end20
 
@@ -1034,20 +1034,20 @@ if.then19:
 if.end20:
   %j.1 = phi i32 [ %add15, %if.then19 ], [ %j.0, %land.lhs.true ], [ %j.0, %while.body ]
   %idxprom21 = sext i32 %j.1 to i64
-  %arrayidx22 = getelementptr inbounds double* %ra, i64 %idxprom21
-  %5 = load double* %arrayidx22, align 8
+  %arrayidx22 = getelementptr inbounds double, double* %ra, i64 %idxprom21
+  %5 = load double, double* %arrayidx22, align 8
   %cmp23 = fcmp olt double %rra.0, %5
   br i1 %cmp23, label %if.then24, label %while.cond
 
 if.then24:
   %idxprom27 = sext i32 %j.0.ph.in to i64
-  %arrayidx28 = getelementptr inbounds double* %ra, i64 %idxprom27
+  %arrayidx28 = getelementptr inbounds double, double* %ra, i64 %idxprom27
   store double %5, double* %arrayidx28, align 8
   br label %while.cond.outer
 
 while.end:
   %idxprom33 = sext i32 %j.0.ph.in to i64
-  %arrayidx34 = getelementptr inbounds double* %ra, i64 %idxprom33
+  %arrayidx34 = getelementptr inbounds double, double* %ra, i64 %idxprom33
   store double %rra.0, double* %arrayidx34, align 8
   br label %for.cond
 }
@@ -1065,8 +1065,8 @@ define i32 @test_cold_calls(i32* %a) {
 ; CHECK: %then
 
 entry:
-  %gep1 = getelementptr i32* %a, i32 1
-  %val1 = load i32* %gep1
+  %gep1 = getelementptr i32, i32* %a, i32 1
+  %val1 = load i32, i32* %gep1
   %cond1 = icmp ugt i32 %val1, 1
   br i1 %cond1, label %then, label %else
 
@@ -1075,8 +1075,8 @@ then:
   br label %exit
 
 else:
-  %gep2 = getelementptr i32* %a, i32 2
-  %val2 = load i32* %gep2
+  %gep2 = getelementptr i32, i32* %a, i32 2
+  %val2 = load i32, i32* %gep2
   br label %exit
 
 exit:
diff --git a/test/CodeGen/X86/bmi.ll b/test/CodeGen/X86/bmi.ll
index a70720926de0..8b13e960cd8f 100644
--- a/test/CodeGen/X86/bmi.ll
+++ b/test/CodeGen/X86/bmi.ll
@@ -27,7 +27,7 @@ define i32 @t3(i32 %x) nounwind  {
 }
 
 define i32 @tzcnt32_load(i32* %x) nounwind  {
-  %x1 = load i32* %x
+  %x1 = load i32, i32* %x
   %tmp = tail call i32 @llvm.cttz.i32(i32 %x1, i1 false )
   ret i32 %tmp
 ; CHECK-LABEL: tzcnt32_load:
@@ -78,7 +78,7 @@ define i32 @andn32(i32 %x, i32 %y) nounwind readnone {
 }
 
 define i32 @andn32_load(i32 %x, i32* %y) nounwind readnone {
-  %y1 = load i32* %y
+  %y1 = load i32, i32* %y
   %tmp1 = xor i32 %x, -1
   %tmp2 = and i32 %y1, %tmp1
   ret i32 %tmp2
@@ -102,7 +102,7 @@ define i32 @bextr32(i32 %x, i32 %y) nounwind readnone {
 }
 
 define i32 @bextr32_load(i32* %x, i32 %y) nounwind readnone {
-  %x1 = load i32* %x
+  %x1 = load i32, i32* %x
   %tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x1, i32 %y)
   ret i32 %tmp
 ; CHECK-LABEL: bextr32_load:
@@ -120,7 +120,7 @@ define i32 @bextr32b(i32 %x) nounwind uwtable readnone ssp {
 }
 
 define i32 @bextr32b_load(i32* %x) nounwind uwtable readnone ssp {
-  %1 = load i32* %x
+  %1 = load i32, i32* %x
   %2 = lshr i32 %1, 4
   %3 = and i32 %2, 4095
   ret i32 %3
@@ -145,6 +145,36 @@ define i64 @bextr64b(i64 %x) nounwind uwtable readnone ssp {
 ; CHECK: bextrq
 }
 
+define i64 @bextr64b_load(i64* %x) {
+  %1 = load i64, i64* %x, align 8
+  %2 = lshr i64 %1, 4
+  %3 = and i64 %2, 4095
+  ret i64 %3
+; CHECK-LABEL: bextr64b_load:
+; CHECK: bextrq {{.*}}, ({{.*}}), {{.*}}
+}
+
+define i32 @non_bextr32(i32 %x) {
+entry:
+  %shr = lshr i32 %x, 2
+  %and = and i32 %shr, 111
+  ret i32 %and
+; CHECK-LABEL: non_bextr32:
+; CHECK: shrl $2
+; CHECK: andl $111
+}
+
+define i64 @non_bextr64(i64 %x) {
+entry:
+  %shr = lshr i64 %x, 2
+  %and = and i64 %shr, 8589934590
+  ret i64 %and
+; CHECK-LABEL: non_bextr64:
+; CHECK: shrq $2
+; CHECK: movabsq $8589934590
+; CHECK: andq 
+}
+
 define i32 @bzhi32(i32 %x, i32 %y) nounwind readnone {
   %tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x, i32 %y)
   ret i32 %tmp
@@ -153,7 +183,7 @@ define i32 @bzhi32(i32 %x, i32 %y) nounwind readnone {
 }
 
 define i32 @bzhi32_load(i32* %x, i32 %y) nounwind readnone {
-  %x1 = load i32* %x
+  %x1 = load i32, i32* %x
   %tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x1, i32 %y)
   ret i32 %tmp
 ; CHECK-LABEL: bzhi32_load:
@@ -184,7 +214,7 @@ entry:
 
 define i32 @bzhi32b_load(i32* %w, i8 zeroext %index) #0 {
 entry:
-  %x = load i32* %w
+  %x = load i32, i32* %w
   %conv = zext i8 %index to i32
   %shl = shl i32 1, %conv
   %sub = add nsw i32 %shl, -1
@@ -230,7 +260,7 @@ entry:
   %and = and i64 %x, 2147483647
   ret i64 %and
 ; CHECK-LABEL: bzhi64_small_constant_mask:
-; CHECK: andq  $2147483647, %r[[ARG1]]
+; CHECK: andl  $2147483647, %e[[ARG1]]
 }
 
 define i32 @blsi32(i32 %x) nounwind readnone {
@@ -242,7 +272,7 @@ define i32 @blsi32(i32 %x) nounwind readnone {
 }
 
 define i32 @blsi32_load(i32* %x) nounwind readnone {
-  %x1 = load i32* %x
+  %x1 = load i32, i32* %x
   %tmp = sub i32 0, %x1
   %tmp2 = and i32 %x1, %tmp
   ret i32 %tmp2
@@ -267,7 +297,7 @@ define i32 @blsmsk32(i32 %x) nounwind readnone {
 }
 
 define i32 @blsmsk32_load(i32* %x) nounwind readnone {
-  %x1 = load i32* %x
+  %x1 = load i32, i32* %x
   %tmp = sub i32 %x1, 1
   %tmp2 = xor i32 %x1, %tmp
   ret i32 %tmp2
@@ -292,7 +322,7 @@ define i32 @blsr32(i32 %x) nounwind readnone {
 }
 
 define i32 @blsr32_load(i32* %x) nounwind readnone {
-  %x1 = load i32* %x
+  %x1 = load i32, i32* %x
   %tmp = sub i32 %x1, 1
   %tmp2 = and i32 %x1, %tmp
   ret i32 %tmp2
@@ -316,7 +346,7 @@ define i32 @pdep32(i32 %x, i32 %y) nounwind readnone {
 }
 
 define i32 @pdep32_load(i32 %x, i32* %y) nounwind readnone {
-  %y1 = load i32* %y
+  %y1 = load i32, i32* %y
   %tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y1)
   ret i32 %tmp
 ; CHECK-LABEL: pdep32_load:
@@ -342,7 +372,7 @@ define i32 @pext32(i32 %x, i32 %y) nounwind readnone {
 }
 
 define i32 @pext32_load(i32 %x, i32* %y) nounwind readnone {
-  %y1 = load i32* %y
+  %y1 = load i32, i32* %y
   %tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y1)
   ret i32 %tmp
 ; CHECK-LABEL: pext32_load:
diff --git a/test/CodeGen/X86/bool-zext.ll b/test/CodeGen/X86/bool-zext.ll
index 3558376dfce6..c98ad9e36d7e 100644
--- a/test/CodeGen/X86/bool-zext.ll
+++ b/test/CodeGen/X86/bool-zext.ll
@@ -10,7 +10,7 @@
 define void @bar1(i1 zeroext %v1) nounwind ssp {
 entry:
   %conv = zext i1 %v1 to i32
-  %call = tail call i32 (...)* @foo1(i32 %conv) nounwind
+  %call = tail call i32 (...) @foo1(i32 %conv) nounwind
   ret void
 }
 
@@ -23,7 +23,7 @@ entry:
 define void @bar2(i8 zeroext %v1) nounwind ssp {
 entry:
   %conv = zext i8 %v1 to i32
-  %call = tail call i32 (...)* @foo1(i32 %conv) nounwind
+  %call = tail call i32 (...) @foo1(i32 %conv) nounwind
   ret void
 }
 
diff --git a/test/CodeGen/X86/branchfolding-landingpads.ll b/test/CodeGen/X86/branchfolding-landingpads.ll
new file mode 100644
index 000000000000..40ec92ea0d7f
--- /dev/null
+++ b/test/CodeGen/X86/branchfolding-landingpads.ll
@@ -0,0 +1,45 @@
+; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-unknown"
+
+; The machine level BranchFolding pass will try to remove the 'unreachable' block
+; and rewrite 'entry' to jump to the block 'unreachable' falls through to.
+; That will be a landing pad and result in 'entry' jumping to 2 landing pads.
+; This tests that we don't do this change when the fallthrough is itself a landing
+; pad.
+
+declare i32 @__gxx_personality_v0(...)
+declare void @foo()
+
+; Function Attrs: noreturn
+declare void @_throw()
+
+; CHECK-LABEL: @main
+; CHECK: %unreachable
+
+define i32 @main(i8* %cleanup) {
+entry:
+  invoke void @_throw() #0
+          to label %unreachable unwind label %catch.dispatch9
+
+catch.dispatch9:                                  ; preds = %entry
+  %tmp13 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+          catch i8* null
+  invoke void @_throw() #0
+          to label %unreachable unwind label %lpad31
+
+lpad31:                                           ; preds = %catch.dispatch9
+  %tmp20 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+          catch i8* null
+  call void @foo()
+  unreachable
+
+unreachable:                                      ; preds = %catch.dispatch9, %entry
+  unreachable
+}
+
+attributes #0 = { noreturn }
+
diff --git a/test/CodeGen/X86/brcond.ll b/test/CodeGen/X86/brcond.ll
index 3ebe1a1d2357..f4db3ba7fecb 100644
--- a/test/CodeGen/X86/brcond.ll
+++ b/test/CodeGen/X86/brcond.ll
@@ -17,11 +17,11 @@ entry:
   br i1 %4, label %bb1, label %bb
 
 bb:                                               ; preds = %entry
-  %5 = tail call i32 (...)* @foo() nounwind       ; <i32> [#uses=1]
+  %5 = tail call i32 (...) @foo() nounwind       ; <i32> [#uses=1]
   ret i32 %5
 
 bb1:                                              ; preds = %entry
-  %6 = tail call i32 (...)* @bar() nounwind       ; <i32> [#uses=1]
+  %6 = tail call i32 (...) @bar() nounwind       ; <i32> [#uses=1]
   ret i32 %6
 }
 
diff --git a/test/CodeGen/X86/break-anti-dependencies.ll b/test/CodeGen/X86/break-anti-dependencies.ll
index 614d0adc7271..c54ac108819e 100644
--- a/test/CodeGen/X86/break-anti-dependencies.ll
+++ b/test/CodeGen/X86/break-anti-dependencies.ll
@@ -10,14 +10,14 @@
 
 define void @goo(double* %r, double* %p, double* %q) nounwind {
 entry:
-	%0 = load double* %p, align 8
+	%0 = load double, double* %p, align 8
 	%1 = fadd double %0, 1.100000e+00
 	%2 = fmul double %1, 1.200000e+00
 	%3 = fadd double %2, 1.300000e+00
 	%4 = fmul double %3, 1.400000e+00
 	%5 = fadd double %4, 1.500000e+00
 	%6 = fptosi double %5 to i32
-	%7 = load double* %r, align 8
+	%7 = load double, double* %r, align 8
 	%8 = fadd double %7, 7.100000e+00
 	%9 = fmul double %8, 7.200000e+00
 	%10 = fadd double %9, 7.300000e+00
diff --git a/test/CodeGen/X86/break-false-dep.ll b/test/CodeGen/X86/break-false-dep.ll
index 7034fae5e8bd..699de22d5b56 100644
--- a/test/CodeGen/X86/break-false-dep.ll
+++ b/test/CodeGen/X86/break-false-dep.ll
@@ -8,7 +8,7 @@ entry:
 ; SSE: movss ([[A0:%rdi|%rcx]]), %xmm0
 ; SSE: cvtss2sd %xmm0, %xmm0
 
-  %0 = load float* %x, align 4
+  %0 = load float, float* %x, align 4
   %1 = fpext float %0 to double
   ret double %1
 }
@@ -17,7 +17,7 @@ define float @t2(double* nocapture %x) nounwind readonly ssp optsize {
 entry:
 ; SSE-LABEL: t2:
 ; SSE: cvtsd2ss ([[A0]]), %xmm0
-  %0 = load double* %x, align 8
+  %0 = load double, double* %x, align 8
   %1 = fptrunc double %0 to float
   ret float %1
 }
@@ -27,7 +27,7 @@ entry:
 ; SSE-LABEL: squirtf:
 ; SSE: movss ([[A0]]), %xmm0
 ; SSE: sqrtss %xmm0, %xmm0
-  %z = load float* %x
+  %z = load float, float* %x
   %t = call float @llvm.sqrt.f32(float %z)
   ret float %t
 }
@@ -37,7 +37,7 @@ entry:
 ; SSE-LABEL: squirt:
 ; SSE: movsd ([[A0]]), %xmm0
 ; SSE: sqrtsd %xmm0, %xmm0
-  %z = load double* %x
+  %z = load double, double* %x
   %t = call double @llvm.sqrt.f64(double %z)
   ret double %t
 }
@@ -46,7 +46,7 @@ define float @squirtf_size(float* %x) nounwind optsize {
 entry:
 ; SSE-LABEL: squirtf_size:
 ; SSE: sqrtss ([[A0]]), %xmm0
-  %z = load float* %x
+  %z = load float, float* %x
   %t = call float @llvm.sqrt.f32(float %z)
   ret float %t
 }
@@ -55,7 +55,7 @@ define double @squirt_size(double* %x) nounwind optsize {
 entry:
 ; SSE-LABEL: squirt_size:
 ; SSE: sqrtsd ([[A0]]), %xmm0
-  %z = load double* %x
+  %z = load double, double* %x
   %t = call double @llvm.sqrt.f64(double %z)
   ret double %t
 }
@@ -120,13 +120,13 @@ for.end:                                          ; preds = %for.body, %entry
 ; SSE: cvtsi2sdq %{{r[0-9a-x]+}}, %[[REG]]
 define i64 @loopdep2(i64* nocapture %x, double* nocapture %y) nounwind {
 entry:
-  %vx = load i64* %x
+  %vx = load i64, i64* %x
   br label %loop
 loop:
   %i = phi i64 [ 1, %entry ], [ %inc, %loop ]
   %s1 = phi i64 [ %vx, %entry ], [ %s2, %loop ]
   %fi = sitofp i64 %i to double
-  %vy = load double* %y
+  %vy = load double, double* %y
   %fipy = fadd double %fi, %vy
   %iipy = fptosi double %fipy to i64
   %s2 = add i64 %s1, %iipy
@@ -158,19 +158,19 @@ for.cond1.preheader:                              ; preds = %for.inc14, %entry
 
 for.body3:
   %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.body3 ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @v, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @v, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %conv = sitofp i32 %0 to double
-  %arrayidx5 = getelementptr inbounds [1024 x double]* @x, i64 0, i64 %indvars.iv
-  %1 = load double* %arrayidx5, align 8
+  %arrayidx5 = getelementptr inbounds [1024 x double], [1024 x double]* @x, i64 0, i64 %indvars.iv
+  %1 = load double, double* %arrayidx5, align 8
   %mul = fmul double %conv, %1
-  %arrayidx7 = getelementptr inbounds [1024 x double]* @y, i64 0, i64 %indvars.iv
-  %2 = load double* %arrayidx7, align 8
+  %arrayidx7 = getelementptr inbounds [1024 x double], [1024 x double]* @y, i64 0, i64 %indvars.iv
+  %2 = load double, double* %arrayidx7, align 8
   %mul8 = fmul double %mul, %2
-  %arrayidx10 = getelementptr inbounds [1024 x double]* @z, i64 0, i64 %indvars.iv
-  %3 = load double* %arrayidx10, align 8
+  %arrayidx10 = getelementptr inbounds [1024 x double], [1024 x double]* @z, i64 0, i64 %indvars.iv
+  %3 = load double, double* %arrayidx10, align 8
   %mul11 = fmul double %mul8, %3
-  %arrayidx13 = getelementptr inbounds [1024 x double]* @w, i64 0, i64 %indvars.iv
+  %arrayidx13 = getelementptr inbounds [1024 x double], [1024 x double]* @w, i64 0, i64 %indvars.iv
   store double %mul11, double* %arrayidx13, align 8
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 1024
diff --git a/test/CodeGen/X86/bswap-vector.ll b/test/CodeGen/X86/bswap-vector.ll
index 9dc960d7779f..7d5f380c1e28 100644
--- a/test/CodeGen/X86/bswap-vector.ll
+++ b/test/CodeGen/X86/bswap-vector.ll
@@ -1,7 +1,8 @@
-; RUN: llc < %s -mcpu=x86-64 | FileCheck %s -check-prefix=CHECK-NOSSSE3
-; RUN: llc < %s -mcpu=core2 | FileCheck %s -check-prefix=CHECK-SSSE3
-; RUN: llc < %s -mcpu=core-avx2 | FileCheck %s -check-prefix=CHECK-AVX2
-; RUN: llc < %s -mcpu=core-avx2 -x86-experimental-vector-widening-legalization | FileCheck %s -check-prefix=CHECK-WIDE-AVX2
+; RUN: llc < %s -mcpu=x86-64 | FileCheck %s --check-prefix=CHECK-NOSSSE3
+; RUN: llc < %s -mcpu=core2 | FileCheck %s --check-prefix=CHECK-SSSE3
+; RUN: llc < %s -mcpu=core-avx2 | FileCheck %s --check-prefix=CHECK-AVX2
+; RUN: llc < %s -mcpu=core-avx2 -x86-experimental-vector-widening-legalization | FileCheck %s --check-prefix=CHECK-WIDE-AVX2
+
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
@@ -9,165 +10,278 @@ declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)
 declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
 declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
 
-define <8 x i16> @test1(<8 x i16> %v) #0 {
+define <8 x i16> @test1(<8 x i16> %v) {
+; CHECK-NOSSSE3-LABEL: test1:
+; CHECK-NOSSSE3:       # BB#0: # %entry
+; CHECK-NOSSSE3-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NOSSSE3-NEXT:    movdqa %xmm0, %xmm2
+; CHECK-NOSSSE3-NEXT:    punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,4,7,6]
+; CHECK-NOSSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6]
+; CHECK-NOSSSE3-NEXT:    packuswb %xmm2, %xmm0
+; CHECK-NOSSSE3-NEXT:    retq
+;
+; CHECK-SSSE3-LABEL: test1:
+; CHECK-SSSE3:       # BB#0: # %entry
+; CHECK-SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
+; CHECK-SSSE3-NEXT:    retq
+;
+; CHECK-AVX2-LABEL: test1:
+; CHECK-AVX2:       # BB#0: # %entry
+; CHECK-AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
+; CHECK-AVX2-NEXT:    retq
+;
+; CHECK-WIDE-AVX2-LABEL: test1:
+; CHECK-WIDE-AVX2:       # BB#0: # %entry
+; CHECK-WIDE-AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
+; CHECK-WIDE-AVX2-NEXT:    retq
 entry:
   %r = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %v)
   ret <8 x i16> %r
-
-; CHECK-NOSSSE3-LABEL: @test1
-; CHECK-NOSSSE3: rolw
-; CHECK-NOSSSE3: rolw
-; CHECK-NOSSSE3: rolw
-; CHECK-NOSSSE3: rolw
-; CHECK-NOSSSE3: rolw
-; CHECK-NOSSSE3: rolw
-; CHECK-NOSSSE3: rolw
-; CHECK-NOSSSE3: rolw
-; CHECK-NOSSSE3: retq
-
-; CHECK-SSSE3-LABEL: @test1
-; CHECK-SSSE3: pshufb
-; CHECK-SSSE3-NEXT: retq
-
-; CHECK-AVX2-LABEL: @test1
-; CHECK-AVX2: vpshufb
-; CHECK-AVX2-NEXT: retq
-
-; CHECK-WIDE-AVX2-LABEL: @test1
-; CHECK-WIDE-AVX2: vpshufb
-; CHECK-WIDE-AVX2-NEXT: retq
 }
 
-define <4 x i32> @test2(<4 x i32> %v) #0 {
+define <4 x i32> @test2(<4 x i32> %v) {
+; CHECK-NOSSSE3-LABEL: test2:
+; CHECK-NOSSSE3:       # BB#0: # %entry
+; CHECK-NOSSSE3-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NOSSSE3-NEXT:    movdqa %xmm0, %xmm2
+; CHECK-NOSSSE3-NEXT:    punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4]
+; CHECK-NOSSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
+; CHECK-NOSSSE3-NEXT:    packuswb %xmm2, %xmm0
+; CHECK-NOSSSE3-NEXT:    retq
+;
+; CHECK-SSSE3-LABEL: test2:
+; CHECK-SSSE3:       # BB#0: # %entry
+; CHECK-SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
+; CHECK-SSSE3-NEXT:    retq
+;
+; CHECK-AVX2-LABEL: test2:
+; CHECK-AVX2:       # BB#0: # %entry
+; CHECK-AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
+; CHECK-AVX2-NEXT:    retq
+;
+; CHECK-WIDE-AVX2-LABEL: test2:
+; CHECK-WIDE-AVX2:       # BB#0: # %entry
+; CHECK-WIDE-AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
+; CHECK-WIDE-AVX2-NEXT:    retq
 entry:
   %r = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %v)
   ret <4 x i32> %r
-
-; CHECK-NOSSSE3-LABEL: @test2
-; CHECK-NOSSSE3: bswapl
-; CHECK-NOSSSE3: bswapl
-; CHECK-NOSSSE3: bswapl
-; CHECK-NOSSSE3: bswapl
-; CHECK-NOSSSE3: retq
-
-; CHECK-SSSE3-LABEL: @test2
-; CHECK-SSSE3: pshufb
-; CHECK-SSSE3-NEXT: retq
-
-; CHECK-AVX2-LABEL: @test2
-; CHECK-AVX2: vpshufb
-; CHECK-AVX2-NEXT: retq
-
-; CHECK-WIDE-AVX2-LABEL: @test2
-; CHECK-WIDE-AVX2: vpshufb
-; CHECK-WIDE-AVX2-NEXT: retq
 }
 
-define <2 x i64> @test3(<2 x i64> %v) #0 {
+define <2 x i64> @test3(<2 x i64> %v) {
+; CHECK-NOSSSE3-LABEL: test3:
+; CHECK-NOSSSE3:       # BB#0: # %entry
+; CHECK-NOSSSE3-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NOSSSE3-NEXT:    movdqa %xmm0, %xmm2
+; CHECK-NOSSSE3-NEXT:    punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
+; CHECK-NOSSSE3-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4]
+; CHECK-NOSSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; CHECK-NOSSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
+; CHECK-NOSSSE3-NEXT:    packuswb %xmm2, %xmm0
+; CHECK-NOSSSE3-NEXT:    retq
+;
+; CHECK-SSSE3-LABEL: test3:
+; CHECK-SSSE3:       # BB#0: # %entry
+; CHECK-SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8]
+; CHECK-SSSE3-NEXT:    retq
+;
+; CHECK-AVX2-LABEL: test3:
+; CHECK-AVX2:       # BB#0: # %entry
+; CHECK-AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8]
+; CHECK-AVX2-NEXT:    retq
+;
+; CHECK-WIDE-AVX2-LABEL: test3:
+; CHECK-WIDE-AVX2:       # BB#0: # %entry
+; CHECK-WIDE-AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8]
+; CHECK-WIDE-AVX2-NEXT:    retq
 entry:
   %r = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %v)
   ret <2 x i64> %r
-
-; CHECK-NOSSSE3-LABEL: @test3
-; CHECK-NOSSSE3: bswapq
-; CHECK-NOSSSE3: bswapq
-; CHECK-NOSSSE3: retq
-
-; CHECK-SSSE3-LABEL: @test3
-; CHECK-SSSE3: pshufb
-; CHECK-SSSE3-NEXT: retq
-
-; CHECK-AVX2-LABEL: @test3
-; CHECK-AVX2: vpshufb
-; CHECK-AVX2-NEXT: retq
-
-; CHECK-WIDE-AVX2-LABEL: @test3
-; CHECK-WIDE-AVX2: vpshufb
-; CHECK-WIDE-AVX2-NEXT: retq
 }
 
 declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
 declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>)
 declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)
 
-define <16 x i16> @test4(<16 x i16> %v) #0 {
+define <16 x i16> @test4(<16 x i16> %v) {
+; CHECK-NOSSSE3-LABEL: test4:
+; CHECK-NOSSSE3:       # BB#0: # %entry
+; CHECK-NOSSSE3-NEXT:    pxor %xmm2, %xmm2
+; CHECK-NOSSSE3-NEXT:    movdqa %xmm0, %xmm3
+; CHECK-NOSSSE3-NEXT:    punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm3 = xmm3[1,0,3,2,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,5,4,7,6]
+; CHECK-NOSSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6]
+; CHECK-NOSSSE3-NEXT:    packuswb %xmm3, %xmm0
+; CHECK-NOSSSE3-NEXT:    movdqa %xmm1, %xmm3
+; CHECK-NOSSSE3-NEXT:    punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm3 = xmm3[1,0,3,2,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,5,4,7,6]
+; CHECK-NOSSSE3-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[1,0,3,2,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,5,4,7,6]
+; CHECK-NOSSSE3-NEXT:    packuswb %xmm3, %xmm1
+; CHECK-NOSSSE3-NEXT:    retq
+;
+; CHECK-SSSE3-LABEL: test4:
+; CHECK-SSSE3:       # BB#0: # %entry
+; CHECK-SSSE3-NEXT:    movdqa {{.*#+}} xmm2 = [1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
+; CHECK-SSSE3-NEXT:    pshufb %xmm2, %xmm0
+; CHECK-SSSE3-NEXT:    pshufb %xmm2, %xmm1
+; CHECK-SSSE3-NEXT:    retq
+;
+; CHECK-AVX2-LABEL: test4:
+; CHECK-AVX2:       # BB#0: # %entry
+; CHECK-AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14,17,16,19,18,21,20,23,22,25,24,27,26,29,28,31,30]
+; CHECK-AVX2-NEXT:    retq
+;
+; CHECK-WIDE-AVX2-LABEL: test4:
+; CHECK-WIDE-AVX2:       # BB#0: # %entry
+; CHECK-WIDE-AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14,17,16,19,18,21,20,23,22,25,24,27,26,29,28,31,30]
+; CHECK-WIDE-AVX2-NEXT:    retq
 entry:
   %r = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %v)
   ret <16 x i16> %r
-
-; CHECK-SSSE3-LABEL: @test4
-; CHECK-SSSE3: pshufb
-; CHECK-SSSE3: pshufb
-; CHECK-SSSE3-NEXT: retq
-
-; CHECK-AVX2-LABEL: @test4
-; CHECK-AVX2: vpshufb
-; CHECK-AVX2-NEXT: retq
-
-; CHECK-WIDE-AVX2-LABEL: @test4
-; CHECK-WIDE-AVX2: vpshufb
-; CHECK-WIDE-AVX2-NEXT: retq
 }
 
-define <8 x i32> @test5(<8 x i32> %v) #0 {
+define <8 x i32> @test5(<8 x i32> %v) {
+; CHECK-NOSSSE3-LABEL: test5:
+; CHECK-NOSSSE3:       # BB#0: # %entry
+; CHECK-NOSSSE3-NEXT:    pxor %xmm2, %xmm2
+; CHECK-NOSSSE3-NEXT:    movdqa %xmm0, %xmm3
+; CHECK-NOSSSE3-NEXT:    punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm3 = xmm3[3,2,1,0,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,7,6,5,4]
+; CHECK-NOSSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
+; CHECK-NOSSSE3-NEXT:    packuswb %xmm3, %xmm0
+; CHECK-NOSSSE3-NEXT:    movdqa %xmm1, %xmm3
+; CHECK-NOSSSE3-NEXT:    punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm3 = xmm3[3,2,1,0,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,7,6,5,4]
+; CHECK-NOSSSE3-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[3,2,1,0,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,6,5,4]
+; CHECK-NOSSSE3-NEXT:    packuswb %xmm3, %xmm1
+; CHECK-NOSSSE3-NEXT:    retq
+;
+; CHECK-SSSE3-LABEL: test5:
+; CHECK-SSSE3:       # BB#0: # %entry
+; CHECK-SSSE3-NEXT:    movdqa {{.*#+}} xmm2 = [3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
+; CHECK-SSSE3-NEXT:    pshufb %xmm2, %xmm0
+; CHECK-SSSE3-NEXT:    pshufb %xmm2, %xmm1
+; CHECK-SSSE3-NEXT:    retq
+;
+; CHECK-AVX2-LABEL: test5:
+; CHECK-AVX2:       # BB#0: # %entry
+; CHECK-AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12,19,18,17,16,23,22,21,20,27,26,25,24,31,30,29,28]
+; CHECK-AVX2-NEXT:    retq
+;
+; CHECK-WIDE-AVX2-LABEL: test5:
+; CHECK-WIDE-AVX2:       # BB#0: # %entry
+; CHECK-WIDE-AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12,19,18,17,16,23,22,21,20,27,26,25,24,31,30,29,28]
+; CHECK-WIDE-AVX2-NEXT:    retq
 entry:
   %r = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %v)
   ret <8 x i32> %r
-
-; CHECK-SSSE3-LABEL: @test5
-; CHECK-SSSE3: pshufb
-; CHECK-SSSE3: pshufb
-; CHECK-SSSE3-NEXT: retq
-
-; CHECK-AVX2-LABEL: @test5
-; CHECK-AVX2: vpshufb
-; CHECK-AVX2-NEXT: retq
-
-; CHECK-WIDE-AVX2-LABEL: @test5
-; CHECK-WIDE-AVX2: vpshufb
-; CHECK-WIDE-AVX2-NEXT: retq
 }
 
-define <4 x i64> @test6(<4 x i64> %v) #0 {
+define <4 x i64> @test6(<4 x i64> %v) {
+; CHECK-NOSSSE3-LABEL: test6:
+; CHECK-NOSSSE3:       # BB#0: # %entry
+; CHECK-NOSSSE3-NEXT:    pxor %xmm2, %xmm2
+; CHECK-NOSSSE3-NEXT:    movdqa %xmm0, %xmm3
+; CHECK-NOSSSE3-NEXT:    punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
+; CHECK-NOSSSE3-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[2,3,0,1]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm3 = xmm3[3,2,1,0,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,7,6,5,4]
+; CHECK-NOSSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; CHECK-NOSSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
+; CHECK-NOSSSE3-NEXT:    packuswb %xmm3, %xmm0
+; CHECK-NOSSSE3-NEXT:    movdqa %xmm1, %xmm3
+; CHECK-NOSSSE3-NEXT:    punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
+; CHECK-NOSSSE3-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[2,3,0,1]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm3 = xmm3[3,2,1,0,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,7,6,5,4]
+; CHECK-NOSSSE3-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; CHECK-NOSSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[3,2,1,0,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,6,5,4]
+; CHECK-NOSSSE3-NEXT:    packuswb %xmm3, %xmm1
+; CHECK-NOSSSE3-NEXT:    retq
+;
+; CHECK-SSSE3-LABEL: test6:
+; CHECK-SSSE3:       # BB#0: # %entry
+; CHECK-SSSE3-NEXT:    movdqa {{.*#+}} xmm2 = [7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8]
+; CHECK-SSSE3-NEXT:    pshufb %xmm2, %xmm0
+; CHECK-SSSE3-NEXT:    pshufb %xmm2, %xmm1
+; CHECK-SSSE3-NEXT:    retq
+;
+; CHECK-AVX2-LABEL: test6:
+; CHECK-AVX2:       # BB#0: # %entry
+; CHECK-AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8,23,22,21,20,19,18,17,16,31,30,29,28,27,26,25,24]
+; CHECK-AVX2-NEXT:    retq
+;
+; CHECK-WIDE-AVX2-LABEL: test6:
+; CHECK-WIDE-AVX2:       # BB#0: # %entry
+; CHECK-WIDE-AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8,23,22,21,20,19,18,17,16,31,30,29,28,27,26,25,24]
+; CHECK-WIDE-AVX2-NEXT:    retq
 entry:
   %r = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %v)
   ret <4 x i64> %r
-
-; CHECK-SSSE3-LABEL: @test6
-; CHECK-SSSE3: pshufb
-; CHECK-SSSE3: pshufb
-; CHECK-SSSE3-NEXT: retq
-
-; CHECK-AVX2-LABEL: @test6
-; CHECK-AVX2: vpshufb
-; CHECK-AVX2-NEXT: retq
-
-; CHECK-WIDE-AVX2-LABEL: @test6
-; CHECK-WIDE-AVX2: vpshufb
-; CHECK-WIDE-AVX2-NEXT: retq
 }
 
 declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>)
 
-define <4 x i16> @test7(<4 x i16> %v) #0 {
+define <4 x i16> @test7(<4 x i16> %v) {
+; CHECK-NOSSSE3-LABEL: test7:
+; CHECK-NOSSSE3:       # BB#0: # %entry
+; CHECK-NOSSSE3-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NOSSSE3-NEXT:    movdqa %xmm0, %xmm2
+; CHECK-NOSSSE3-NEXT:    punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4]
+; CHECK-NOSSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; CHECK-NOSSSE3-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
+; CHECK-NOSSSE3-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
+; CHECK-NOSSSE3-NEXT:    packuswb %xmm2, %xmm0
+; CHECK-NOSSSE3-NEXT:    psrld $16, %xmm0
+; CHECK-NOSSSE3-NEXT:    retq
+;
+; CHECK-SSSE3-LABEL: test7:
+; CHECK-SSSE3:       # BB#0: # %entry
+; CHECK-SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
+; CHECK-SSSE3-NEXT:    psrld $16, %xmm0
+; CHECK-SSSE3-NEXT:    retq
+;
+; CHECK-AVX2-LABEL: test7:
+; CHECK-AVX2:       # BB#0: # %entry
+; CHECK-AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
+; CHECK-AVX2-NEXT:    vpsrld $16, %xmm0, %xmm0
+; CHECK-AVX2-NEXT:    retq
+;
+; CHECK-WIDE-AVX2-LABEL: test7:
+; CHECK-WIDE-AVX2:       # BB#0: # %entry
+; CHECK-WIDE-AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
+; CHECK-WIDE-AVX2-NEXT:    retq
 entry:
   %r = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %v)
   ret <4 x i16> %r
-
-; CHECK-SSSE3-LABEL: @test7
-; CHECK-SSSE3: pshufb
-; CHECK-SSSE3: psrld $16
-; CHECK-SSSE3-NEXT: retq
-
-; CHECK-AVX2-LABEL: @test7
-; CHECK-AVX2: vpshufb
-; CHECK-AVX2: vpsrld $16
-; CHECK-AVX2-NEXT: retq
-
-; CHECK-WIDE-AVX2-LABEL: @test7
-; CHECK-WIDE-AVX2: vpshufb
-; CHECK-WIDE-AVX2-NEXT: retq
 }
-
-attributes #0 = { nounwind uwtable }
-
diff --git a/test/CodeGen/X86/bswap.ll b/test/CodeGen/X86/bswap.ll
index e6a456c39ddd..48dc18e0ac14 100644
--- a/test/CodeGen/X86/bswap.ll
+++ b/test/CodeGen/X86/bswap.ll
@@ -91,7 +91,7 @@ define i64 @not_bswap() {
 ; CHECK64-LABEL: not_bswap:
 ; CHECK64-NOT: bswapq
 ; CHECK64: ret
-  %init = load i16* @var16
+  %init = load i16, i16* @var16
   %big = zext i16 %init to i64
 
   %hishifted = lshr i64 %big, 8
@@ -115,7 +115,7 @@ define i64 @not_useful_bswap() {
 ; CHECK64-NOT: bswapq
 ; CHECK64: ret
 
-  %init = load i8* @var8
+  %init = load i8, i8* @var8
   %big = zext i8 %init to i64
 
   %hishifted = lshr i64 %big, 8
@@ -140,7 +140,7 @@ define i64 @finally_useful_bswap() {
 ; CHECK64: shrq $48, [[REG]]
 ; CHECK64: ret
 
-  %init = load i16* @var16
+  %init = load i16, i16* @var16
   %big = zext i16 %init to i64
 
   %hishifted = lshr i64 %big, 8
diff --git a/test/CodeGen/X86/byval-align.ll b/test/CodeGen/X86/byval-align.ll
index c62a1814ba7f..8366ae38333f 100644
--- a/test/CodeGen/X86/byval-align.ll
+++ b/test/CodeGen/X86/byval-align.ll
@@ -14,20 +14,20 @@ entry:
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   %obj1 = bitcast %struct.S* %obj to i8*          ; <i8*> [#uses=1]
   store i8* %obj1, i8** %ptr, align 8
-  %0 = load i8** %ptr, align 8                    ; <i8*> [#uses=1]
+  %0 = load i8*, i8** %ptr, align 8                    ; <i8*> [#uses=1]
   %1 = ptrtoint i8* %0 to i64                     ; <i64> [#uses=1]
   store i64 %1, i64* %p, align 8
-  %2 = load i8** %ptr, align 8                    ; <i8*> [#uses=1]
-  %3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i64 0, i64 0), i8* %2) nounwind ; <i32> [#uses=0]
-  %4 = load i64* %p, align 8                      ; <i64> [#uses=1]
+  %2 = load i8*, i8** %ptr, align 8                    ; <i8*> [#uses=1]
+  %3 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str, i64 0, i64 0), i8* %2) nounwind ; <i32> [#uses=0]
+  %4 = load i64, i64* %p, align 8                      ; <i64> [#uses=1]
   %5 = and i64 %4, 140737488355264                ; <i64> [#uses=1]
-  %6 = load i64* %p, align 8                      ; <i64> [#uses=1]
+  %6 = load i64, i64* %p, align 8                      ; <i64> [#uses=1]
   %7 = icmp ne i64 %5, %6                         ; <i1> [#uses=1]
   br i1 %7, label %bb, label %bb2
 
 bb:                                               ; preds = %entry
-  %8 = call i32 @puts(i8* getelementptr inbounds ([8 x i8]* @.str1, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
-  call void @__assert_fail(i8* getelementptr inbounds ([2 x i8]* @.str2, i64 0, i64 0), i8* getelementptr inbounds ([7 x i8]* @.str3, i64 0, i64 0), i32 18, i8* getelementptr inbounds ([13 x i8]* @__PRETTY_FUNCTION__.2067, i64 0, i64 0)) noreturn nounwind
+  %8 = call i32 @puts(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str1, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+  call void @__assert_fail(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str2, i64 0, i64 0), i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str3, i64 0, i64 0), i32 18, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @__PRETTY_FUNCTION__.2067, i64 0, i64 0)) noreturn nounwind
   unreachable
 
 bb2:                                              ; preds = %entry
@@ -49,7 +49,7 @@ entry:
 ; CHECK: andq    $-64, %rsp
   %s1 = alloca %struct.S                          ; <%struct.S*> [#uses=4]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  %0 = getelementptr inbounds %struct.S* %s1, i32 0, i32 0 ; <i32*> [#uses=1]
+  %0 = getelementptr inbounds %struct.S, %struct.S* %s1, i32 0, i32 0 ; <i32*> [#uses=1]
   store i32 1, i32* %0, align 4
   call void @aligned_func(%struct.S* byval align 64 %s1) nounwind
   br label %return
diff --git a/test/CodeGen/X86/byval.ll b/test/CodeGen/X86/byval.ll
index 185eda1566d4..f29511a54c41 100644
--- a/test/CodeGen/X86/byval.ll
+++ b/test/CodeGen/X86/byval.ll
@@ -11,7 +11,7 @@
 
 define i64 @f(%struct.s* byval %a) {
 entry:
-	%tmp2 = getelementptr %struct.s* %a, i32 0, i32 0
-	%tmp3 = load i64* %tmp2, align 8
+	%tmp2 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 0
+	%tmp3 = load i64, i64* %tmp2, align 8
 	ret i64 %tmp3
 }
diff --git a/test/CodeGen/X86/byval2.ll b/test/CodeGen/X86/byval2.ll
index c5187db6de4b..cc72a8699a9c 100644
--- a/test/CodeGen/X86/byval2.ll
+++ b/test/CodeGen/X86/byval2.ll
@@ -31,11 +31,11 @@
 define void @g(i64 %a, i64 %b, i64 %c) {
 entry:
 	%d = alloca %struct.s, align 16
-	%tmp = getelementptr %struct.s* %d, i32 0, i32 0
+	%tmp = getelementptr %struct.s, %struct.s* %d, i32 0, i32 0
 	store i64 %a, i64* %tmp, align 16
-	%tmp2 = getelementptr %struct.s* %d, i32 0, i32 1
+	%tmp2 = getelementptr %struct.s, %struct.s* %d, i32 0, i32 1
 	store i64 %b, i64* %tmp2, align 16
-	%tmp4 = getelementptr %struct.s* %d, i32 0, i32 2
+	%tmp4 = getelementptr %struct.s, %struct.s* %d, i32 0, i32 2
 	store i64 %c, i64* %tmp4, align 16
 	call void @f( %struct.s*byval %d )
 	call void @f( %struct.s*byval %d )
diff --git a/test/CodeGen/X86/byval3.ll b/test/CodeGen/X86/byval3.ll
index d06fd8898e7f..85ecdaf1c67d 100644
--- a/test/CodeGen/X86/byval3.ll
+++ b/test/CodeGen/X86/byval3.ll
@@ -33,17 +33,17 @@
 define void @g(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6) nounwind {
 entry:
         %d = alloca %struct.s, align 16
-        %tmp = getelementptr %struct.s* %d, i32 0, i32 0
+        %tmp = getelementptr %struct.s, %struct.s* %d, i32 0, i32 0
         store i32 %a1, i32* %tmp, align 16
-        %tmp2 = getelementptr %struct.s* %d, i32 0, i32 1
+        %tmp2 = getelementptr %struct.s, %struct.s* %d, i32 0, i32 1
         store i32 %a2, i32* %tmp2, align 16
-        %tmp4 = getelementptr %struct.s* %d, i32 0, i32 2
+        %tmp4 = getelementptr %struct.s, %struct.s* %d, i32 0, i32 2
         store i32 %a3, i32* %tmp4, align 16
-        %tmp6 = getelementptr %struct.s* %d, i32 0, i32 3
+        %tmp6 = getelementptr %struct.s, %struct.s* %d, i32 0, i32 3
         store i32 %a4, i32* %tmp6, align 16
-        %tmp8 = getelementptr %struct.s* %d, i32 0, i32 4
+        %tmp8 = getelementptr %struct.s, %struct.s* %d, i32 0, i32 4
         store i32 %a5, i32* %tmp8, align 16
-        %tmp10 = getelementptr %struct.s* %d, i32 0, i32 5
+        %tmp10 = getelementptr %struct.s, %struct.s* %d, i32 0, i32 5
         store i32 %a6, i32* %tmp10, align 16
         call void @f( %struct.s* byval %d)
         call void @f( %struct.s* byval %d)
diff --git a/test/CodeGen/X86/byval4.ll b/test/CodeGen/X86/byval4.ll
index 4711e4511112..1e436f7903ac 100644
--- a/test/CodeGen/X86/byval4.ll
+++ b/test/CodeGen/X86/byval4.ll
@@ -39,17 +39,17 @@ define void @g(i16 signext  %a1, i16 signext  %a2, i16 signext  %a3,
 	 i16 signext  %a4, i16 signext  %a5, i16 signext  %a6) nounwind {
 entry:
         %a = alloca %struct.s, align 16
-        %tmp = getelementptr %struct.s* %a, i32 0, i32 0
+        %tmp = getelementptr %struct.s, %struct.s* %a, i32 0, i32 0
         store i16 %a1, i16* %tmp, align 16
-        %tmp2 = getelementptr %struct.s* %a, i32 0, i32 1
+        %tmp2 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 1
         store i16 %a2, i16* %tmp2, align 16
-        %tmp4 = getelementptr %struct.s* %a, i32 0, i32 2
+        %tmp4 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 2
         store i16 %a3, i16* %tmp4, align 16
-        %tmp6 = getelementptr %struct.s* %a, i32 0, i32 3
+        %tmp6 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 3
         store i16 %a4, i16* %tmp6, align 16
-        %tmp8 = getelementptr %struct.s* %a, i32 0, i32 4
+        %tmp8 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 4
         store i16 %a5, i16* %tmp8, align 16
-        %tmp10 = getelementptr %struct.s* %a, i32 0, i32 5
+        %tmp10 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 5
         store i16 %a6, i16* %tmp10, align 16
         call void @f( %struct.s* byval %a )
         call void @f( %struct.s* byval %a )
diff --git a/test/CodeGen/X86/byval5.ll b/test/CodeGen/X86/byval5.ll
index f24a5f9aa3b4..6d734a44b3c3 100644
--- a/test/CodeGen/X86/byval5.ll
+++ b/test/CodeGen/X86/byval5.ll
@@ -47,17 +47,17 @@ define void @g(i8 signext  %a1, i8 signext  %a2, i8 signext  %a3,
 	 i8 signext  %a4, i8 signext  %a5, i8 signext  %a6) {
 entry:
         %a = alloca %struct.s
-        %tmp = getelementptr %struct.s* %a, i32 0, i32 0
+        %tmp = getelementptr %struct.s, %struct.s* %a, i32 0, i32 0
         store i8 %a1, i8* %tmp, align 8
-        %tmp2 = getelementptr %struct.s* %a, i32 0, i32 1
+        %tmp2 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 1
         store i8 %a2, i8* %tmp2, align 8
-        %tmp4 = getelementptr %struct.s* %a, i32 0, i32 2
+        %tmp4 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 2
         store i8 %a3, i8* %tmp4, align 8
-        %tmp6 = getelementptr %struct.s* %a, i32 0, i32 3
+        %tmp6 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 3
         store i8 %a4, i8* %tmp6, align 8
-        %tmp8 = getelementptr %struct.s* %a, i32 0, i32 4
+        %tmp8 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 4
         store i8 %a5, i8* %tmp8, align 8
-        %tmp10 = getelementptr %struct.s* %a, i32 0, i32 5
+        %tmp10 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 5
         store i8 %a6, i8* %tmp10, align 8
         call void @f( %struct.s* byval %a )
         call void @f( %struct.s* byval %a )
diff --git a/test/CodeGen/X86/byval6.ll b/test/CodeGen/X86/byval6.ll
index 2d3990167f2e..c3e7b7ef435a 100644
--- a/test/CodeGen/X86/byval6.ll
+++ b/test/CodeGen/X86/byval6.ll
@@ -6,8 +6,8 @@
 
 define i32 @main() nounwind  {
 entry:
-	tail call void (i32, ...)* @bar( i32 3, %struct.W* byval  @.cpx ) nounwind 
-	tail call void (i32, ...)* @baz( i32 3, %struct.W* byval  @B ) nounwind 
+	tail call void (i32, ...) @bar( i32 3, %struct.W* byval  @.cpx ) nounwind 
+	tail call void (i32, ...) @baz( i32 3, %struct.W* byval  @B ) nounwind 
 	ret i32 undef
 }
 
diff --git a/test/CodeGen/X86/byval7.ll b/test/CodeGen/X86/byval7.ll
index 42751d7dbc93..8d5dd8c5887e 100644
--- a/test/CodeGen/X86/byval7.ll
+++ b/test/CodeGen/X86/byval7.ll
@@ -12,7 +12,7 @@ entry:
 ; CHECK: rep;movsl
 ; CHECK: movl $1, (%esp)
 	%s = alloca %struct.S		; <%struct.S*> [#uses=2]
-	%tmp15 = getelementptr %struct.S* %s, i32 0, i32 0		; <<2 x i64>*> [#uses=1]
+	%tmp15 = getelementptr %struct.S, %struct.S* %s, i32 0, i32 0		; <<2 x i64>*> [#uses=1]
 	store <2 x i64> < i64 8589934595, i64 1 >, <2 x i64>* %tmp15, align 16
 	call void @t( i32 1, %struct.S* byval  %s ) nounwind
 	ret i32 0
diff --git a/test/CodeGen/X86/cache-intrinsic.ll b/test/CodeGen/X86/cache-intrinsic.ll
index 3091b5ff3118..0b9d77ac993e 100644
--- a/test/CodeGen/X86/cache-intrinsic.ll
+++ b/test/CodeGen/X86/cache-intrinsic.ll
@@ -10,10 +10,10 @@ define i32 @main() {
 entry:
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0))
-  %call1 = call i8* @strcpy(i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds ([25 x i8]* @.str1, i32 0, i32 0)) #3
-  call void @llvm.clear_cache(i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds (i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0), i32 32)) #3
-  %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0))
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0))
+  %call1 = call i8* @strcpy(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str1, i32 0, i32 0)) #3
+  call void @llvm.clear_cache(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds (i8, i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i32 32)) #3
+  %call3 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0))
   ret i32 0
 }
 
diff --git a/test/CodeGen/X86/call-push.ll b/test/CodeGen/X86/call-push.ll
index ccb98fefae2a..6bcb5d665618 100644
--- a/test/CodeGen/X86/call-push.ll
+++ b/test/CodeGen/X86/call-push.ll
@@ -10,9 +10,9 @@ define i32 @decode_byte(%struct.decode_t* %decode) nounwind {
 ; CHECK: jmp
 ; CHECK: popl
 entry:
-        %tmp2 = getelementptr %struct.decode_t* %decode, i32 0, i32 4           ; <i16*> [#uses=1]
+        %tmp2 = getelementptr %struct.decode_t, %struct.decode_t* %decode, i32 0, i32 4           ; <i16*> [#uses=1]
         %tmp23 = bitcast i16* %tmp2 to i32*             ; <i32*> [#uses=1]
-        %tmp4 = load i32* %tmp23                ; <i32> [#uses=1]
+        %tmp4 = load i32, i32* %tmp23                ; <i32> [#uses=1]
         %tmp514 = lshr i32 %tmp4, 24            ; <i32> [#uses=1]
         %tmp56 = trunc i32 %tmp514 to i8                ; <i8> [#uses=1]
         %tmp7 = icmp eq i8 %tmp56, 0            ; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/cas.ll b/test/CodeGen/X86/cas.ll
index ec519c646f69..7807bb97f5b9 100644
--- a/test/CodeGen/X86/cas.ll
+++ b/test/CodeGen/X86/cas.ll
@@ -24,14 +24,14 @@ entry:
   store float* %p, float** %p.addr, align 8
   store float* %expected, float** %expected.addr, align 8
   store float %desired, float* %desired.addr, align 4
-  %0 = load float** %expected.addr, align 8
-  %1 = load float** %expected.addr, align 8
-  %2 = load float* %1, align 4
-  %3 = load float* %desired.addr, align 4
-  %4 = load float** %p.addr, align 8
+  %0 = load float*, float** %expected.addr, align 8
+  %1 = load float*, float** %expected.addr, align 8
+  %2 = load float, float* %1, align 4
+  %3 = load float, float* %desired.addr, align 4
+  %4 = load float*, float** %p.addr, align 8
   %5 = call i8 asm sideeffect "lock; cmpxchg $3, $4; mov $2, $1; sete $0", "={ax},=*rm,{ax},q,*m,~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(float* %0, float %2, float %3, float* %4) nounwind
   store i8 %5, i8* %success, align 1
-  %6 = load i8* %success, align 1
+  %6 = load i8, i8* %success, align 1
   %tobool = trunc i8 %6 to i1
   ret i1 %tobool
 }
@@ -52,16 +52,16 @@ entry:
   store i8* %expected, i8** %expected.addr, align 8
   %frombool = zext i1 %desired to i8
   store i8 %frombool, i8* %desired.addr, align 1
-  %0 = load i8** %expected.addr, align 8
-  %1 = load i8** %expected.addr, align 8
-  %2 = load i8* %1, align 1
+  %0 = load i8*, i8** %expected.addr, align 8
+  %1 = load i8*, i8** %expected.addr, align 8
+  %2 = load i8, i8* %1, align 1
   %tobool = trunc i8 %2 to i1
-  %3 = load i8* %desired.addr, align 1
+  %3 = load i8, i8* %desired.addr, align 1
   %tobool1 = trunc i8 %3 to i1
-  %4 = load i8** %p.addr, align 8
+  %4 = load i8*, i8** %p.addr, align 8
   %5 = call i8 asm sideeffect "lock; cmpxchg $3, $4; mov $2, $1; sete $0", "={ax},=*rm,{ax},q,*m,~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(i8* %0, i1 %tobool, i1 %tobool1, i8* %4) nounwind
   store i8 %5, i8* %success, align 1
-  %6 = load i8* %success, align 1
+  %6 = load i8, i8* %success, align 1
   %tobool2 = trunc i8 %6 to i1
   ret i1 %tobool2
 }
diff --git a/test/CodeGen/X86/catch.ll b/test/CodeGen/X86/catch.ll
index 6f7021360e1f..64e92783ac98 100644
--- a/test/CodeGen/X86/catch.ll
+++ b/test/CodeGen/X86/catch.ll
@@ -14,7 +14,7 @@ invoke.cont:
   ret void
 lpad:
   %tmp14 = landingpad { i8*, i32 } personality i8* bitcast (void ()* @h to i8*)
-           catch i8* getelementptr inbounds ([12 x i8]* @str, i64 0, i64 0)
+           catch i8* getelementptr inbounds ([12 x i8], [12 x i8]* @str, i64 0, i64 0)
   ret void
 }
 declare void @g()
diff --git a/test/CodeGen/X86/cfi_enforcing.ll b/test/CodeGen/X86/cfi_enforcing.ll
deleted file mode 100644
index bcad8c168f24..000000000000
--- a/test/CodeGen/X86/cfi_enforcing.ll
+++ /dev/null
@@ -1,34 +0,0 @@
-; RUN: llc -mtriple=i386-unknown-linux-gnu -fcfi -cfi-enforcing <%s | FileCheck --check-prefix=X86 %s
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu -fcfi -cfi-enforcing <%s | FileCheck --check-prefix=X86-64 %s
-
-define void @indirect_fun() unnamed_addr jumptable {
-  ret void
-}
-
-define i32 @m(void ()* %fun) {
-  call void ()* %fun()
-; CHECK: subl
-; X86-64: andq    $8,
-; X86-64: leaq    __llvm_jump_instr_table_0_1({{%[a-z0-9]+}}), [[REG:%[a-z0-9]+]]
-; X86-64-NOT: callq __llvm_cfi_pointer_warning
-; X86-64: callq   *[[REG]]
-; X86: andl    $8,
-; X86: leal    __llvm_jump_instr_table_0_1({{%[a-z0-9]+}}), [[REG:%[a-z0-9]+]]
-; X86-NOT: calll __llvm_cfi_pointer_warning
-; X86: calll   *[[REG]]
-  ret i32 0
-}
-
-define void ()* @get_fun() {
-  ret void ()* @indirect_fun
-}
-
-define i32 @main(i32 %argc, i8** %argv) {
-  %f = call void ()* ()* @get_fun()
-  %a = call i32 @m(void ()* %f)
-  ret i32 %a
-}
-
-; CHECK: .align 8
-; CHECK: __llvm_jump_instr_table_0_1:
-; CHECK: jmp indirect_fun@PLT
diff --git a/test/CodeGen/X86/cfi_invoke.ll b/test/CodeGen/X86/cfi_invoke.ll
deleted file mode 100644
index dd0d42a59c3a..000000000000
--- a/test/CodeGen/X86/cfi_invoke.ll
+++ /dev/null
@@ -1,35 +0,0 @@
-; RUN: llc <%s -fcfi -cfi-type=sub | FileCheck %s
-; ModuleID = 'test.cc'
-target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
-target triple = "x86_64-unknown-linux-gnu"
-
-declare i32 @__gxx_personality_v0(...)
-
-@_ZTIPKc = external constant i8*
-@_ZTIi = external constant i8*
-
-define void @f() unnamed_addr jumptable {
-  ret void
-}
-
-@a = global void ()* @f
-
-; Make sure invoke gets targeted as well as regular calls
-define void @_Z3foov(void ()* %f) uwtable ssp {
-; CHECK-LABEL: _Z3foov:
- entry:
-   invoke void %f()
-           to label %try.cont unwind label %lpad
-; CHECK: callq __llvm_cfi_pointer_warning
-; CHECK: callq *%rbx
-
- lpad:
-   %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
-                                  catch i8* bitcast (i8** @_ZTIi to i8*)
-                                  filter [1 x i8*] [i8* bitcast (i8** @_ZTIPKc to i8*)]
-   ret void
-
- try.cont:
-   ret void
-}
-
diff --git a/test/CodeGen/X86/cfi_non_default_function.ll b/test/CodeGen/X86/cfi_non_default_function.ll
deleted file mode 100644
index 29774a1d4425..000000000000
--- a/test/CodeGen/X86/cfi_non_default_function.ll
+++ /dev/null
@@ -1,27 +0,0 @@
-; RUN: llc -fcfi -cfi-func-name=cfi_new_failure <%s | FileCheck %s
-
-target triple = "x86_64-unknown-linux-gnu"
-define void @indirect_fun() unnamed_addr jumptable {
-  ret void
-}
-
-define i32 @m(void ()* %fun) {
-; CHECK-LABEL: @m
-  call void ()* %fun()
-; CHECK: callq cfi_new_failure
-  ret i32 0
-}
-
-define void ()* @get_fun() {
-  ret void ()* @indirect_fun
-}
-
-define i32 @main(i32 %argc, i8** %argv) {
-  %f = call void ()* ()* @get_fun()
-  %a = call i32 @m(void ()* %f)
-  ret i32 %a
-}
-
-; CHECK: .align 8
-; CHECK: __llvm_jump_instr_table_0_1:
-; CHECK: jmp indirect_fun@PLT
diff --git a/test/CodeGen/X86/cfi_simple_indirect_call.ll b/test/CodeGen/X86/cfi_simple_indirect_call.ll
deleted file mode 100644
index 0ee118d984ea..000000000000
--- a/test/CodeGen/X86/cfi_simple_indirect_call.ll
+++ /dev/null
@@ -1,43 +0,0 @@
-; RUN: llc -fcfi -cfi-type=sub <%s | FileCheck --check-prefix=SUB %s
-; RUN: llc -fcfi -cfi-type=add <%s | FileCheck --check-prefix=ADD %s
-; RUN: llc -fcfi -cfi-type=ror <%s | FileCheck --check-prefix=ROR %s
-
-target triple = "x86_64-unknown-linux-gnu"
-
-define void @indirect_fun() unnamed_addr jumptable {
-  ret void
-}
-
-define i32 @m(void ()* %fun) {
-  call void ()* %fun()
-; SUB: subl    
-; SUB: andq    $8
-; SUB-LABEL: leaq    __llvm_jump_instr_table_0_1
-; SUB-LABEL: callq   __llvm_cfi_pointer_warning
-
-; ROR: subq
-; ROR: rolq    $61
-; ROR: testq
-; ROR-LABEL: callq   __llvm_cfi_pointer_warning
-
-; ADD: andq    $8
-; ADD-LABEL: leaq    __llvm_jump_instr_table_0_1
-; ADD: cmpq
-; ADD-LABEL: callq   __llvm_cfi_pointer_warning
-ret i32 0
-}
-
-define void ()* @get_fun() {
-  ret void ()* @indirect_fun
-}
-
-define i32 @main(i32 %argc, i8** %argv) {
-  %f = call void ()* ()* @get_fun()
-  %a = call i32 @m(void ()* %f)
-  ret i32 %a
-}
-; SUB: .text
-; SUB: .align 8
-; SUB-LABEL: .type __llvm_jump_instr_table_0_1,@function
-; SUB-LABEL:__llvm_jump_instr_table_0_1:
-; SUB-LABEL: jmp indirect_fun@PLT
diff --git a/test/CodeGen/X86/cfstring.ll b/test/CodeGen/X86/cfstring.ll
index cae432098907..3eeb8d2890cc 100644
--- a/test/CodeGen/X86/cfstring.ll
+++ b/test/CodeGen/X86/cfstring.ll
@@ -22,14 +22,14 @@
 @isLogVisible = global i8 0, align 1
 @__CFConstantStringClassReference = external global [0 x i32]
 @.str3 = private unnamed_addr constant [1 x i8] zeroinitializer, align 1
-@_unnamed_cfstring_4 = private constant %struct.NSConstantString { i32* getelementptr inbounds ([0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr inbounds ([1 x i8]* @.str3, i32 0, i32 0), i32 0 }, section "__DATA,__cfstring"
+@_unnamed_cfstring_4 = private constant %struct.NSConstantString { i32* getelementptr inbounds ([0 x i32], [0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str3, i32 0, i32 0), i32 0 }, section "__DATA,__cfstring"
 @null.array = weak_odr constant [1 x i8] zeroinitializer, align 1
 
 define linkonce_odr void @bar() nounwind ssp align 2 {
 entry:
   %stack = alloca i8*, align 4
   %call = call %0* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %0* (i8*, i8*, %0*)*)(i8* null, i8* null, %0* bitcast (%struct.NSConstantString* @_unnamed_cfstring_4 to %0*))
-  store i8* getelementptr inbounds ([1 x i8]* @null.array, i32 0, i32 0), i8** %stack, align 4
+  store i8* getelementptr inbounds ([1 x i8], [1 x i8]* @null.array, i32 0, i32 0), i8** %stack, align 4
   ret void
 }
 
diff --git a/test/CodeGen/X86/chain_order.ll b/test/CodeGen/X86/chain_order.ll
index 72e6f78bdef7..442786a47cac 100644
--- a/test/CodeGen/X86/chain_order.ll
+++ b/test/CodeGen/X86/chain_order.ll
@@ -12,13 +12,13 @@
 ; A test from pifft (after SLP-vectorization) that fails when we drop the chain on newly merged loads.
 define void @cftx020(double* nocapture %a) {
 entry:
-  %0 = load double* %a, align 8
-  %arrayidx1 = getelementptr inbounds double* %a, i64 2
-  %1 = load double* %arrayidx1, align 8
-  %arrayidx2 = getelementptr inbounds double* %a, i64 1
-  %2 = load double* %arrayidx2, align 8
-  %arrayidx3 = getelementptr inbounds double* %a, i64 3
-  %3 = load double* %arrayidx3, align 8
+  %0 = load double, double* %a, align 8
+  %arrayidx1 = getelementptr inbounds double, double* %a, i64 2
+  %1 = load double, double* %arrayidx1, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %a, i64 1
+  %2 = load double, double* %arrayidx2, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 3
+  %3 = load double, double* %arrayidx3, align 8
   %4 = insertelement <2 x double> undef, double %0, i32 0
   %5 = insertelement <2 x double> %4, double %3, i32 1
   %6 = insertelement <2 x double> undef, double %1, i32 0
diff --git a/test/CodeGen/X86/change-compare-stride-1.ll b/test/CodeGen/X86/change-compare-stride-1.ll
index b45b404c0f3c..c5480ba2b490 100644
--- a/test/CodeGen/X86/change-compare-stride-1.ll
+++ b/test/CodeGen/X86/change-compare-stride-1.ll
@@ -31,7 +31,7 @@ bb2.outer:		; preds = %bb4, %bb4.thread
 bb2:		; preds = %bb2, %bb2.outer
 	%indvar = phi i64 [ 0, %bb2.outer ], [ %indvar.next, %bb2 ]		; <i64> [#uses=3]
 	%indvar16 = trunc i64 %indvar to i16		; <i16> [#uses=1]
-	%ctg2 = getelementptr i8* %out, i64 %tmp21		; <i8*> [#uses=1]
+	%ctg2 = getelementptr i8, i8* %out, i64 %tmp21		; <i8*> [#uses=1]
 	%tmp22 = ptrtoint i8* %ctg2 to i64		; <i64> [#uses=1]
 	%tmp24 = sub i64 %tmp22, %indvar		; <i64> [#uses=1]
 	%out_addr.0.reg2mem.0 = inttoptr i64 %tmp24 to i8*		; <i8*> [#uses=1]
@@ -40,39 +40,39 @@ bb2:		; preds = %bb2, %bb2.outer
 	%3 = add i32 %1, %2		; <i32> [#uses=9]
 	%4 = add i32 %3, -481		; <i32> [#uses=1]
 	%5 = zext i32 %4 to i64		; <i64> [#uses=1]
-	%6 = getelementptr i8* %in, i64 %5		; <i8*> [#uses=1]
-	%7 = load i8* %6, align 1		; <i8> [#uses=1]
+	%6 = getelementptr i8, i8* %in, i64 %5		; <i8*> [#uses=1]
+	%7 = load i8, i8* %6, align 1		; <i8> [#uses=1]
 	%8 = add i32 %3, -480		; <i32> [#uses=1]
 	%9 = zext i32 %8 to i64		; <i64> [#uses=1]
-	%10 = getelementptr i8* %in, i64 %9		; <i8*> [#uses=1]
-	%11 = load i8* %10, align 1		; <i8> [#uses=1]
+	%10 = getelementptr i8, i8* %in, i64 %9		; <i8*> [#uses=1]
+	%11 = load i8, i8* %10, align 1		; <i8> [#uses=1]
 	%12 = add i32 %3, -479		; <i32> [#uses=1]
 	%13 = zext i32 %12 to i64		; <i64> [#uses=1]
-	%14 = getelementptr i8* %in, i64 %13		; <i8*> [#uses=1]
-	%15 = load i8* %14, align 1		; <i8> [#uses=1]
+	%14 = getelementptr i8, i8* %in, i64 %13		; <i8*> [#uses=1]
+	%15 = load i8, i8* %14, align 1		; <i8> [#uses=1]
 	%16 = add i32 %3, -1		; <i32> [#uses=1]
 	%17 = zext i32 %16 to i64		; <i64> [#uses=1]
-	%18 = getelementptr i8* %in, i64 %17		; <i8*> [#uses=1]
-	%19 = load i8* %18, align 1		; <i8> [#uses=1]
+	%18 = getelementptr i8, i8* %in, i64 %17		; <i8*> [#uses=1]
+	%19 = load i8, i8* %18, align 1		; <i8> [#uses=1]
 	%20 = zext i32 %3 to i64		; <i64> [#uses=1]
-	%21 = getelementptr i8* %in, i64 %20		; <i8*> [#uses=1]
-	%22 = load i8* %21, align 1		; <i8> [#uses=1]
+	%21 = getelementptr i8, i8* %in, i64 %20		; <i8*> [#uses=1]
+	%22 = load i8, i8* %21, align 1		; <i8> [#uses=1]
 	%23 = add i32 %3, 1		; <i32> [#uses=1]
 	%24 = zext i32 %23 to i64		; <i64> [#uses=1]
-	%25 = getelementptr i8* %in, i64 %24		; <i8*> [#uses=1]
-	%26 = load i8* %25, align 1		; <i8> [#uses=1]
+	%25 = getelementptr i8, i8* %in, i64 %24		; <i8*> [#uses=1]
+	%26 = load i8, i8* %25, align 1		; <i8> [#uses=1]
 	%27 = add i32 %3, 481		; <i32> [#uses=1]
 	%28 = zext i32 %27 to i64		; <i64> [#uses=1]
-	%29 = getelementptr i8* %in, i64 %28		; <i8*> [#uses=1]
-	%30 = load i8* %29, align 1		; <i8> [#uses=1]
+	%29 = getelementptr i8, i8* %in, i64 %28		; <i8*> [#uses=1]
+	%30 = load i8, i8* %29, align 1		; <i8> [#uses=1]
 	%31 = add i32 %3, 480		; <i32> [#uses=1]
 	%32 = zext i32 %31 to i64		; <i64> [#uses=1]
-	%33 = getelementptr i8* %in, i64 %32		; <i8*> [#uses=1]
-	%34 = load i8* %33, align 1		; <i8> [#uses=1]
+	%33 = getelementptr i8, i8* %in, i64 %32		; <i8*> [#uses=1]
+	%34 = load i8, i8* %33, align 1		; <i8> [#uses=1]
 	%35 = add i32 %3, 479		; <i32> [#uses=1]
 	%36 = zext i32 %35 to i64		; <i64> [#uses=1]
-	%37 = getelementptr i8* %in, i64 %36		; <i8*> [#uses=1]
-	%38 = load i8* %37, align 1		; <i8> [#uses=1]
+	%37 = getelementptr i8, i8* %in, i64 %36		; <i8*> [#uses=1]
+	%38 = load i8, i8* %37, align 1		; <i8> [#uses=1]
 	%39 = add i8 %11, %7		; <i8> [#uses=1]
 	%40 = add i8 %39, %15		; <i8> [#uses=1]
 	%41 = add i8 %40, %19		; <i8> [#uses=1]
diff --git a/test/CodeGen/X86/clobber-fi0.ll b/test/CodeGen/X86/clobber-fi0.ll
index 4876c351a413..02f1a1616db2 100644
--- a/test/CodeGen/X86/clobber-fi0.ll
+++ b/test/CodeGen/X86/clobber-fi0.ll
@@ -20,17 +20,17 @@ bb:
   br label %bb4
 
 bb4:                                              ; preds = %bb4, %bb
-  %tmp6 = load i32* %tmp2, align 4                ; [#uses=1 type=i32]
+  %tmp6 = load i32, i32* %tmp2, align 4                ; [#uses=1 type=i32]
   %tmp7 = add i32 %tmp6, -1                       ; [#uses=2 type=i32]
   store i32 %tmp7, i32* %tmp2, align 4
   %tmp8 = icmp eq i32 %tmp7, 0                    ; [#uses=1 type=i1]
-  %tmp9 = load i32* %tmp                          ; [#uses=1 type=i32]
+  %tmp9 = load i32, i32* %tmp                          ; [#uses=1 type=i32]
   %tmp10 = add i32 %tmp9, -1              ; [#uses=1 type=i32]
   store i32 %tmp10, i32* %tmp3
   br i1 %tmp8, label %bb11, label %bb4
 
 bb11:                                             ; preds = %bb4
-  %tmp12 = load i32* %tmp, align 4                ; [#uses=1 type=i32]
+  %tmp12 = load i32, i32* %tmp, align 4                ; [#uses=1 type=i32]
   ret i32 %tmp12
 }
 
diff --git a/test/CodeGen/X86/cmov-double.ll b/test/CodeGen/X86/cmov-double.ll
new file mode 100644
index 000000000000..994a027596c6
--- /dev/null
+++ b/test/CodeGen/X86/cmov-double.ll
@@ -0,0 +1,52 @@
+; RUN: llc -o - %s | FileCheck %s
+target triple = "x86_64-unknown-unknown"
+
+; select with and i1/or i1 condition should be implemented as a series of 2
+; cmovs, not by producing two conditions and using and on them.
+
+define i32 @select_and(i32 %a0, i32 %a1, float %a2, float %a3, i32 %a4, i32 %a5) {
+; CHECK-LABEL: select_and
+; CHECK-NOT: set
+; CHECK-NOT: and[lb]
+; CHECK-NOT: test
+; CHECK: cmov
+; CHECK: cmov
+  %cmp0 = icmp ult i32 %a0, %a1
+  %cmp1 = fcmp olt float %a2, %a3
+  %and = and i1 %cmp0, %cmp1
+  %res = select i1 %and, i32 %a4, i32 %a5
+  ret i32 %res
+}
+
+define i32 @select_or(i32 %a0, i32 %a1, float %a2, float %a3, i32 %a4, i32 %a5) {
+; select with and i1 condition should be implemented as a series of 2 cmovs, not
+; by producing two conditions and using and on them.
+; CHECK-LABEL: select_or
+; CHECK-NOT: set
+; CHECK-NOT: or[lb]
+; CHECK-NOT: test
+; CHECK: cmov
+; CHECK: cmov
+  %cmp0 = icmp ult i32 %a0, %a1
+  %cmp1 = fcmp olt float %a2, %a3
+  %and = or i1 %cmp0, %cmp1
+  %res = select i1 %and, i32 %a4, i32 %a5
+  ret i32 %res
+}
+
+; If one of the conditions is materialized as a 0/1 value anyway, then the
+; sequence of 2 cmovs should not be used.
+
+@var32 = global i32 0
+define i32 @select_noopt(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
+; CHECK-LABEL: select_noopt
+; CHECK: cmov
+; CHECK-NOT: cmov
+  %cmp0 = icmp ult i32 %a0, %a1
+  %cmp1 = icmp ult i32 %a1, %a2
+  %or = or i1 %cmp0, %cmp1
+  %zero_one = zext i1 %or to i32
+  store volatile i32 %zero_one, i32* @var32
+  %res = select i1 %or, i32 %a3, i32 %a4
+  ret i32 %res
+}
diff --git a/test/CodeGen/X86/cmov-into-branch.ll b/test/CodeGen/X86/cmov-into-branch.ll
index cad8dd307b34..909440800a56 100644
--- a/test/CodeGen/X86/cmov-into-branch.ll
+++ b/test/CodeGen/X86/cmov-into-branch.ll
@@ -2,7 +2,7 @@
 
 ; cmp with single-use load, should not form cmov.
 define i32 @test1(double %a, double* nocapture %b, i32 %x, i32 %y)  {
-  %load = load double* %b, align 8
+  %load = load double, double* %b, align 8
   %cmp = fcmp olt double %load, %a
   %cond = select i1 %cmp, i32 %x, i32 %y
   ret i32 %cond
@@ -25,7 +25,7 @@ define i32 @test2(double %a, double %b, i32 %x, i32 %y)  {
 
 ; Multiple uses of %a, should not form cmov.
 define i32 @test3(i32 %a, i32* nocapture %b, i32 %x)  {
-  %load = load i32* %b, align 4
+  %load = load i32, i32* %b, align 4
   %cmp = icmp ult i32 %load, %a
   %cond = select i1 %cmp, i32 %a, i32 %x
   ret i32 %cond
@@ -38,7 +38,7 @@ define i32 @test3(i32 %a, i32* nocapture %b, i32 %x)  {
 
 ; Multiple uses of the load.
 define i32 @test4(i32 %a, i32* nocapture %b, i32 %x, i32 %y)  {
-  %load = load i32* %b, align 4
+  %load = load i32, i32* %b, align 4
   %cmp = icmp ult i32 %load, %a
   %cond = select i1 %cmp, i32 %x, i32 %y
   %add = add i32 %cond, %load
@@ -50,7 +50,7 @@ define i32 @test4(i32 %a, i32* nocapture %b, i32 %x, i32 %y)  {
 
 ; Multiple uses of the cmp.
 define i32 @test5(i32 %a, i32* nocapture %b, i32 %x, i32 %y) {
-  %load = load i32* %b, align 4
+  %load = load i32, i32* %b, align 4
   %cmp = icmp ult i32 %load, %a
   %cmp1 = icmp ugt i32 %load, %a
   %cond = select i1 %cmp1, i32 %a, i32 %y
diff --git a/test/CodeGen/X86/cmov.ll b/test/CodeGen/X86/cmov.ll
index 355c6b4165b9..f2f36b15d0c5 100644
--- a/test/CodeGen/X86/cmov.ll
+++ b/test/CodeGen/X86/cmov.ll
@@ -12,7 +12,7 @@ entry:
 	%0 = lshr i32 %x, %n		; <i32> [#uses=1]
 	%1 = and i32 %0, 1		; <i32> [#uses=1]
 	%toBool = icmp eq i32 %1, 0		; <i1> [#uses=1]
-        %v = load i32* %vp
+        %v = load i32, i32* %vp
 	%.0 = select i1 %toBool, i32 %v, i32 12		; <i32> [#uses=1]
 	ret i32 %.0
 }
@@ -27,7 +27,7 @@ entry:
 	%0 = lshr i32 %x, %n		; <i32> [#uses=1]
 	%1 = and i32 %0, 1		; <i32> [#uses=1]
 	%toBool = icmp eq i32 %1, 0		; <i1> [#uses=1]
-        %v = load i32* %vp
+        %v = load i32, i32* %vp
 	%.0 = select i1 %toBool, i32 12, i32 %v		; <i32> [#uses=1]
 	ret i32 %.0
 }
@@ -71,7 +71,7 @@ define void @test3(i64 %a, i64 %b, i1 %p) nounwind {
 
 define i32 @test4() nounwind {
 entry:
-  %0 = load i8* @g_3, align 1                     ; <i8> [#uses=2]
+  %0 = load i8, i8* @g_3, align 1                     ; <i8> [#uses=2]
   %1 = sext i8 %0 to i32                          ; <i32> [#uses=1]
   %.lobit.i = lshr i8 %0, 7                       ; <i8> [#uses=1]
   %tmp.i = zext i8 %.lobit.i to i32               ; <i32> [#uses=1]
@@ -79,12 +79,12 @@ entry:
   %iftmp.17.0.i.i = ashr i32 %1, %tmp.not.i       ; <i32> [#uses=1]
   %retval56.i.i = trunc i32 %iftmp.17.0.i.i to i8 ; <i8> [#uses=1]
   %2 = icmp eq i8 %retval56.i.i, 0                ; <i1> [#uses=2]
-  %g_96.promoted.i = load i8* @g_96               ; <i8> [#uses=3]
+  %g_96.promoted.i = load i8, i8* @g_96               ; <i8> [#uses=3]
   %3 = icmp eq i8 %g_96.promoted.i, 0             ; <i1> [#uses=2]
   br i1 %3, label %func_4.exit.i, label %bb.i.i.i
 
 bb.i.i.i:                                         ; preds = %entry
-  %4 = load volatile i8* @g_100, align 1          ; <i8> [#uses=0]
+  %4 = load volatile i8, i8* @g_100, align 1          ; <i8> [#uses=0]
   br label %func_4.exit.i
 
 ; CHECK-LABEL: test4:
@@ -101,14 +101,14 @@ func_4.exit.i:                                    ; preds = %bb.i.i.i, %entry
   br i1 %brmerge.i, label %func_1.exit, label %bb.i.i
 
 bb.i.i:                                           ; preds = %func_4.exit.i
-  %5 = load volatile i8* @g_100, align 1          ; <i8> [#uses=0]
+  %5 = load volatile i8, i8* @g_100, align 1          ; <i8> [#uses=0]
   br label %func_1.exit
 
 func_1.exit:                                      ; preds = %bb.i.i, %func_4.exit.i
   %g_96.tmp.0.i = phi i8 [ %g_96.promoted.i, %bb.i.i ], [ %.mux.i, %func_4.exit.i ] ; <i8> [#uses=2]
   store i8 %g_96.tmp.0.i, i8* @g_96
   %6 = zext i8 %g_96.tmp.0.i to i32               ; <i32> [#uses=1]
-  %7 = tail call i32 (i8*, ...)* @printf(i8* noalias getelementptr ([15 x i8]* @_2E_str, i64 0, i64 0), i32 %6) nounwind ; <i32> [#uses=0]
+  %7 = tail call i32 (i8*, ...) @printf(i8* noalias getelementptr ([15 x i8], [15 x i8]* @_2E_str, i64 0, i64 0), i32 %6) nounwind ; <i32> [#uses=0]
   ret i32 0
 }
 
@@ -125,7 +125,7 @@ entry:
 ; CHECK:	orl	$-2, %eax
 ; CHECK:	ret
 
-	%0 = load i32* %P, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* %P, align 4		; <i32> [#uses=1]
 	%1 = icmp sgt i32 %0, 41		; <i1> [#uses=1]
 	%iftmp.0.0 = select i1 %1, i32 -1, i32 -2		; <i32> [#uses=1]
 	ret i32 %iftmp.0.0
@@ -138,7 +138,7 @@ entry:
 ; CHECK:	movzbl	%al, %eax
 ; CHECK:	leal	4(%rax,%rax,8), %eax
 ; CHECK:        ret
-	%0 = load i32* %P, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* %P, align 4		; <i32> [#uses=1]
 	%1 = icmp sgt i32 %0, 41		; <i1> [#uses=1]
 	%iftmp.0.0 = select i1 %1, i32 4, i32 13		; <i32> [#uses=1]
 	ret i32 %iftmp.0.0
diff --git a/test/CodeGen/X86/cmovcmov.ll b/test/CodeGen/X86/cmovcmov.ll
new file mode 100644
index 000000000000..d3d9748d6530
--- /dev/null
+++ b/test/CodeGen/X86/cmovcmov.ll
@@ -0,0 +1,226 @@
+; RUN: llc < %s -asm-verbose=false -mtriple=x86_64-unknown-linux | FileCheck %s --check-prefix=CHECK --check-prefix=CMOV
+; RUN: llc < %s -asm-verbose=false -mtriple=i686-unknown-linux | FileCheck %s --check-prefix=CHECK --check-prefix=NOCMOV
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+
+; Test 2xCMOV patterns exposed after legalization.
+; One way to do that is with (select (fcmp une/oeq)), which gets
+; legalized to setp/setne.
+
+; CHECK-LABEL: test_select_fcmp_oeq_i32:
+
+; CMOV-NEXT: ucomiss  %xmm1, %xmm0
+; CMOV-NEXT: cmovnel  %esi, %edi
+; CMOV-NEXT: cmovpl  %esi, %edi
+; CMOV-NEXT: movl  %edi, %eax
+; CMOV-NEXT: retq
+
+; NOCMOV-NEXT:  flds  8(%esp)
+; NOCMOV-NEXT:  flds  4(%esp)
+; NOCMOV-NEXT:  fucompp
+; NOCMOV-NEXT:  fnstsw  %ax
+; NOCMOV-NEXT:  sahf
+; NOCMOV-NEXT:  leal  16(%esp), %eax
+; NOCMOV-NEXT:  jne  [[TBB:.LBB[0-9_]+]]
+; NOCMOV-NEXT:  jp  [[TBB]]
+; NOCMOV-NEXT:  leal  12(%esp), %eax
+; NOCMOV-NEXT:[[TBB]]:
+; NOCMOV-NEXT:  movl  (%eax), %eax
+; NOCMOV-NEXT:  retl
+define i32 @test_select_fcmp_oeq_i32(float %a, float %b, i32 %c, i32 %d) #0 {
+entry:
+  %cmp = fcmp oeq float %a, %b
+  %r = select i1 %cmp, i32 %c, i32 %d
+  ret i32 %r
+}
+
+; CHECK-LABEL: test_select_fcmp_oeq_i64:
+
+; CMOV-NEXT:   ucomiss  %xmm1, %xmm0
+; CMOV-NEXT:   cmovneq  %rsi, %rdi
+; CMOV-NEXT:   cmovpq  %rsi, %rdi
+; CMOV-NEXT:   movq  %rdi, %rax
+; CMOV-NEXT:   retq
+
+; NOCMOV-NEXT:   flds  8(%esp)
+; NOCMOV-NEXT:   flds  4(%esp)
+; NOCMOV-NEXT:   fucompp
+; NOCMOV-NEXT:   fnstsw  %ax
+; NOCMOV-NEXT:   sahf
+; NOCMOV-NEXT:   leal  20(%esp), %ecx
+; NOCMOV-NEXT:   jne  [[TBB:.LBB[0-9_]+]]
+; NOCMOV-NEXT:   jp  [[TBB]]
+; NOCMOV-NEXT:   leal  12(%esp), %ecx
+; NOCMOV-NEXT: [[TBB]]:
+; NOCMOV-NEXT:   movl  (%ecx), %eax
+; NOCMOV-NEXT:   orl  $4, %ecx
+; NOCMOV-NEXT:   movl  (%ecx), %edx
+; NOCMOV-NEXT:   retl
+define i64 @test_select_fcmp_oeq_i64(float %a, float %b, i64 %c, i64 %d) #0 {
+entry:
+  %cmp = fcmp oeq float %a, %b
+  %r = select i1 %cmp, i64 %c, i64 %d
+  ret i64 %r
+}
+
+; CHECK-LABEL: test_select_fcmp_une_i64:
+
+; CMOV-NEXT:   ucomiss  %xmm1, %xmm0
+; CMOV-NEXT:   cmovneq  %rdi, %rsi
+; CMOV-NEXT:   cmovpq  %rdi, %rsi
+; CMOV-NEXT:   movq  %rsi, %rax
+; CMOV-NEXT:   retq
+
+; NOCMOV-NEXT:   flds  8(%esp)
+; NOCMOV-NEXT:   flds  4(%esp)
+; NOCMOV-NEXT:   fucompp
+; NOCMOV-NEXT:   fnstsw  %ax
+; NOCMOV-NEXT:   sahf
+; NOCMOV-NEXT:   leal  12(%esp), %ecx
+; NOCMOV-NEXT:   jne  [[TBB:.LBB[0-9_]+]]
+; NOCMOV-NEXT:   jp  [[TBB]]
+; NOCMOV-NEXT:   leal  20(%esp), %ecx
+; NOCMOV-NEXT: [[TBB]]:
+; NOCMOV-NEXT:   movl  (%ecx), %eax
+; NOCMOV-NEXT:   orl  $4, %ecx
+; NOCMOV-NEXT:   movl  (%ecx), %edx
+; NOCMOV-NEXT:   retl
+define i64 @test_select_fcmp_une_i64(float %a, float %b, i64 %c, i64 %d) #0 {
+entry:
+  %cmp = fcmp une float %a, %b
+  %r = select i1 %cmp, i64 %c, i64 %d
+  ret i64 %r
+}
+
+; CHECK-LABEL: test_select_fcmp_oeq_f64:
+
+; CMOV-NEXT:   ucomiss  %xmm1, %xmm0
+; CMOV-NEXT:   jne  [[TBB:.LBB[0-9_]+]]
+; CMOV-NEXT:   jp  [[TBB]]
+; CMOV-NEXT:   movaps  %xmm2, %xmm3
+; CMOV-NEXT: [[TBB]]:
+; CMOV-NEXT:   movaps  %xmm3, %xmm0
+; CMOV-NEXT:   retq
+
+; NOCMOV-NEXT:   flds  8(%esp)
+; NOCMOV-NEXT:   flds  4(%esp)
+; NOCMOV-NEXT:   fucompp
+; NOCMOV-NEXT:   fnstsw  %ax
+; NOCMOV-NEXT:   sahf
+; NOCMOV-NEXT:   leal  20(%esp), %eax
+; NOCMOV-NEXT:   jne  [[TBB:.LBB[0-9_]+]]
+; NOCMOV-NEXT:   jp  [[TBB]]
+; NOCMOV-NEXT:   leal  12(%esp), %eax
+; NOCMOV-NEXT: [[TBB]]:
+; NOCMOV-NEXT:   fldl  (%eax)
+; NOCMOV-NEXT:   retl
+define double @test_select_fcmp_oeq_f64(float %a, float %b, double %c, double %d) #0 {
+entry:
+  %cmp = fcmp oeq float %a, %b
+  %r = select i1 %cmp, double %c, double %d
+  ret double %r
+}
+
+; CHECK-LABEL: test_select_fcmp_oeq_v4i32:
+
+; CMOV-NEXT:   ucomiss  %xmm1, %xmm0
+; CMOV-NEXT:   jne  [[TBB:.LBB[0-9_]+]]
+; CMOV-NEXT:   jp  [[TBB]]
+; CMOV-NEXT:   movaps  %xmm2, %xmm3
+; CMOV-NEXT: [[TBB]]:
+; CMOV-NEXT:   movaps  %xmm3, %xmm0
+; CMOV-NEXT:   retq
+
+; NOCMOV-NEXT:   pushl  %edi
+; NOCMOV-NEXT:   pushl  %esi
+; NOCMOV-NEXT:   flds  20(%esp)
+; NOCMOV-NEXT:   flds  16(%esp)
+; NOCMOV-NEXT:   fucompp
+; NOCMOV-NEXT:   fnstsw  %ax
+; NOCMOV-NEXT:   sahf
+; NOCMOV-NEXT:   leal  40(%esp), %eax
+; NOCMOV-NEXT:   jne  [[TBB:.LBB[0-9_]+]]
+; NOCMOV-NEXT:   jp  [[TBB]]
+; NOCMOV-NEXT:   leal  24(%esp), %eax
+; NOCMOV-NEXT: [[TBB]]:
+; NOCMOV-NEXT:   movl  (%eax), %ecx
+; NOCMOV-NEXT:   leal  44(%esp), %edx
+; NOCMOV-NEXT:   jne  [[TBB:.LBB[0-9_]+]]
+; NOCMOV-NEXT:   jp  [[TBB]]
+; NOCMOV-NEXT:   leal  28(%esp), %edx
+; NOCMOV-NEXT: [[TBB]]:
+; NOCMOV-NEXT:   movl  12(%esp), %eax
+; NOCMOV-NEXT:   movl  (%edx), %edx
+; NOCMOV-NEXT:   leal  48(%esp), %esi
+; NOCMOV-NEXT:   jne  [[TBB:.LBB[0-9_]+]]
+; NOCMOV-NEXT:   jp  [[TBB]]
+; NOCMOV-NEXT:   leal  32(%esp), %esi
+; NOCMOV-NEXT: [[TBB]]:
+; NOCMOV-NEXT:   movl  (%esi), %esi
+; NOCMOV-NEXT:   leal  52(%esp), %edi
+; NOCMOV-NEXT:   jne  [[TBB:.LBB[0-9_]+]]
+; NOCMOV-NEXT:   jp  [[TBB]]
+; NOCMOV-NEXT:   leal  36(%esp), %edi
+; NOCMOV-NEXT: [[TBB]]:
+; NOCMOV-NEXT:   movl  (%edi), %edi
+; NOCMOV-NEXT:   movl  %edi, 12(%eax)
+; NOCMOV-NEXT:   movl  %esi, 8(%eax)
+; NOCMOV-NEXT:   movl  %edx, 4(%eax)
+; NOCMOV-NEXT:   movl  %ecx, (%eax)
+; NOCMOV-NEXT:   popl  %esi
+; NOCMOV-NEXT:   popl  %edi
+; NOCMOV-NEXT:   retl  $4
+define <4 x i32> @test_select_fcmp_oeq_v4i32(float %a, float %b, <4 x i32> %c, <4 x i32> %d) #0 {
+entry:
+  %cmp = fcmp oeq float %a, %b
+  %r = select i1 %cmp, <4 x i32> %c, <4 x i32> %d
+  ret <4 x i32> %r
+}
+
+; Also make sure we catch the original code-sequence of interest:
+
+; CMOV: [[ONE_F32_LCPI:.LCPI.*]]:
+; CMOV-NEXT:   .long  1065353216
+
+; CHECK-LABEL: test_zext_fcmp_une:
+; CMOV-NEXT:   ucomiss  %xmm1, %xmm0
+; CMOV-NEXT:   movss  [[ONE_F32_LCPI]](%rip), %xmm0
+; CMOV-NEXT:   jne  [[TBB:.LBB[0-9_]+]]
+; CMOV-NEXT:   jp  [[TBB]]
+; CMOV-NEXT:   xorps  %xmm0, %xmm0
+; CMOV-NEXT: [[TBB]]:
+; CMOV-NEXT:   retq
+
+; NOCMOV:        jne
+; NOCMOV-NEXT:   jp
+define float @test_zext_fcmp_une(float %a, float %b) #0 {
+entry:
+  %cmp = fcmp une float %a, %b
+  %conv1 = zext i1 %cmp to i32
+  %conv2 = sitofp i32 %conv1 to float
+  ret float %conv2
+}
+
+; CMOV: [[ONE_F32_LCPI:.LCPI.*]]:
+; CMOV-NEXT:   .long  1065353216
+
+; CHECK-LABEL: test_zext_fcmp_oeq:
+; CMOV-NEXT:   ucomiss  %xmm1, %xmm0
+; CMOV-NEXT:   xorps  %xmm0, %xmm0
+; CMOV-NEXT:   jne  [[TBB:.LBB[0-9_]+]]
+; CMOV-NEXT:   jp  [[TBB]]
+; CMOV-NEXT:   movss  [[ONE_F32_LCPI]](%rip), %xmm0
+; CMOV-NEXT: [[TBB]]:
+; CMOV-NEXT:   retq
+
+; NOCMOV:        jne
+; NOCMOV-NEXT:   jp
+define float @test_zext_fcmp_oeq(float %a, float %b) #0 {
+entry:
+  %cmp = fcmp oeq float %a, %b
+  %conv1 = zext i1 %cmp to i32
+  %conv2 = sitofp i32 %conv1 to float
+  ret float %conv2
+}
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/X86/cmp-fast-isel.ll b/test/CodeGen/X86/cmp-fast-isel.ll
new file mode 100644
index 000000000000..39738fae12d1
--- /dev/null
+++ b/test/CodeGen/X86/cmp-fast-isel.ll
@@ -0,0 +1,45 @@
+; RUN: llc -mtriple=x86_64-linux -fast-isel -show-mc-encoding < %s | FileCheck %s
+
+; pr22854
+
+define i32 @f1(i16 %x) {
+; CHECK-LABEL: f1:
+; CHECK: cmpw	$42, %di               # encoding: [0x66,0x83,0xff,0x2a]
+bb0:
+  %cmp = icmp ne i16 %x, 42
+  br i1 %cmp, label %bb3, label %bb7
+
+bb3:
+  ret i32 1
+
+bb7:
+  ret i32 2
+}
+
+define i32 @f2(i32 %x) {
+; CHECK-LABEL: f2:
+; CHECK: cmpl	$42, %edi               # encoding: [0x83,0xff,0x2a]
+bb0:
+  %cmp = icmp ne i32 %x, 42
+  br i1 %cmp, label %bb3, label %bb7
+
+bb3:
+  ret i32 1
+
+bb7:
+  ret i32 2
+}
+
+define i32 @f3(i64 %x) {
+; CHECK-LABEL: f3:
+; CHECK: cmpq	$42, %rdi               # encoding: [0x48,0x83,0xff,0x2a]
+bb0:
+  %cmp = icmp ne i64 %x, 42
+  br i1 %cmp, label %bb3, label %bb7
+
+bb3:
+  ret i32 1
+
+bb7:
+  ret i32 2
+}
diff --git a/test/CodeGen/X86/cmp.ll b/test/CodeGen/X86/cmp.ll
index 149d53759fe2..584179aacbc9 100644
--- a/test/CodeGen/X86/cmp.ll
+++ b/test/CodeGen/X86/cmp.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -show-mc-encoding | FileCheck %s
 
 define i32 @test1(i32 %X, i32* %y) nounwind {
-	%tmp = load i32* %y		; <i32> [#uses=1]
+	%tmp = load i32, i32* %y		; <i32> [#uses=1]
 	%tmp.upgrd.1 = icmp eq i32 %tmp, 0		; <i1> [#uses=1]
 	br i1 %tmp.upgrd.1, label %ReturnBlock, label %cond_true
 
@@ -15,7 +15,7 @@ ReturnBlock:		; preds = %0
 }
 
 define i32 @test2(i32 %X, i32* %y) nounwind {
-	%tmp = load i32* %y		; <i32> [#uses=1]
+	%tmp = load i32, i32* %y		; <i32> [#uses=1]
 	%tmp1 = shl i32 %tmp, 3		; <i32> [#uses=1]
 	%tmp1.upgrd.2 = icmp eq i32 %tmp1, 0		; <i1> [#uses=1]
 	br i1 %tmp1.upgrd.2, label %ReturnBlock, label %cond_true
@@ -30,7 +30,7 @@ ReturnBlock:		; preds = %0
 }
 
 define i8 @test2b(i8 %X, i8* %y) nounwind {
-	%tmp = load i8* %y		; <i8> [#uses=1]
+	%tmp = load i8, i8* %y		; <i8> [#uses=1]
 	%tmp1 = shl i8 %tmp, 3		; <i8> [#uses=1]
 	%tmp1.upgrd.2 = icmp eq i8 %tmp1, 0		; <i1> [#uses=1]
 	br i1 %tmp1.upgrd.2, label %ReturnBlock, label %cond_true
@@ -75,7 +75,7 @@ define i32 @test5(double %A) nounwind  {
  br i1 %bothcond, label %bb8, label %bb12
 
  bb8:; preds = %entry
- %tmp9 = tail call i32 (...)* @foo( ) nounwind ; <i32> [#uses=1]
+ %tmp9 = tail call i32 (...) @foo( ) nounwind ; <i32> [#uses=1]
  ret i32 %tmp9
 
  bb12:; preds = %entry
@@ -89,8 +89,8 @@ declare i32 @foo(...)
 
 define i32 @test6() nounwind align 2 {
   %A = alloca {i64, i64}, align 8
-  %B = getelementptr inbounds {i64, i64}* %A, i64 0, i32 1
-  %C = load i64* %B
+  %B = getelementptr inbounds {i64, i64}, {i64, i64}* %A, i64 0, i32 1
+  %C = load i64, i64* %B
   %D = icmp eq i64 %C, 0
   br i1 %D, label %T, label %F
 T:
diff --git a/test/CodeGen/X86/cmpxchg-clobber-flags.ll b/test/CodeGen/X86/cmpxchg-clobber-flags.ll
index b7995dbdf259..61123930887b 100644
--- a/test/CodeGen/X86/cmpxchg-clobber-flags.ll
+++ b/test/CodeGen/X86/cmpxchg-clobber-flags.ll
@@ -42,7 +42,7 @@ loop_start:
   br label %while.condthread-pre-split.i
 
 while.condthread-pre-split.i:
-  %.pr.i = load i32* %p, align 4
+  %.pr.i = load i32, i32* %p, align 4
   br label %while.cond.i
 
 while.cond.i:
diff --git a/test/CodeGen/X86/cmpxchg-i1.ll b/test/CodeGen/X86/cmpxchg-i1.ll
index a21ab593b078..5f5869f78bba 100644
--- a/test/CodeGen/X86/cmpxchg-i1.ll
+++ b/test/CodeGen/X86/cmpxchg-i1.ll
@@ -68,7 +68,7 @@ define i32 @cmpxchg_use_eflags_and_val(i32* %addr, i32 %offset) {
   ; Result already in %eax
 ; CHECK: retq
 entry:
-  %init = load atomic i32* %addr seq_cst, align 4
+  %init = load atomic i32, i32* %addr seq_cst, align 4
   br label %loop
 
 loop:
diff --git a/test/CodeGen/X86/cmpxchg-i128-i1.ll b/test/CodeGen/X86/cmpxchg-i128-i1.ll
index 4dd30013ecab..278e6a4ed75e 100644
--- a/test/CodeGen/X86/cmpxchg-i128-i1.ll
+++ b/test/CodeGen/X86/cmpxchg-i128-i1.ll
@@ -62,7 +62,7 @@ define i128 @cmpxchg_use_eflags_and_val(i128* %addr, i128 %offset) {
 ; CHECK-NOT: cmpq
 ; CHECK: jne
 entry:
-  %init = load atomic i128* %addr seq_cst, align 16
+  %init = load atomic i128, i128* %addr seq_cst, align 16
   br label %loop
 
 loop:
diff --git a/test/CodeGen/X86/cmpxchg16b.ll b/test/CodeGen/X86/cmpxchg16b.ll
index 1d5bb85f8d20..d514c0a35f5b 100644
--- a/test/CodeGen/X86/cmpxchg16b.ll
+++ b/test/CodeGen/X86/cmpxchg16b.ll
@@ -4,8 +4,7 @@
 define void @t1(i128* nocapture %p) nounwind ssp {
 entry:
 ; CHECK: movl	$1, %ebx
-; CHECK: lock
-; CHECK-NEXT: cmpxchg16b
+; CHECK: lock cmpxchg16b
   %r = cmpxchg i128* %p, i128 0, i128 1 seq_cst seq_cst
   ret void
 }
diff --git a/test/CodeGen/X86/coalesce-esp.ll b/test/CodeGen/X86/coalesce-esp.ll
index 400437993879..e0257e68f0f2 100644
--- a/test/CodeGen/X86/coalesce-esp.ll
+++ b/test/CodeGen/X86/coalesce-esp.ll
@@ -18,9 +18,9 @@ entry:
 bb4:		; preds = %bb7.backedge, %entry
 	%indvar = phi i32 [ %indvar.next, %bb7.backedge ], [ 0, %entry ]		; <i32> [#uses=2]
 	%scevgep24.sum = sub i32 undef, %indvar		; <i32> [#uses=2]
-	%scevgep25 = getelementptr i32* %0, i32 %scevgep24.sum		; <i32*> [#uses=1]
-	%scevgep27 = getelementptr i32* undef, i32 %scevgep24.sum		; <i32*> [#uses=1]
-	%1 = load i32* %scevgep27, align 4		; <i32> [#uses=0]
+	%scevgep25 = getelementptr i32, i32* %0, i32 %scevgep24.sum		; <i32*> [#uses=1]
+	%scevgep27 = getelementptr i32, i32* undef, i32 %scevgep24.sum		; <i32*> [#uses=1]
+	%1 = load i32, i32* %scevgep27, align 4		; <i32> [#uses=0]
 	br i1 undef, label %bb7.backedge, label %bb5
 
 bb5:		; preds = %bb4
diff --git a/test/CodeGen/X86/coalesce-implicitdef.ll b/test/CodeGen/X86/coalesce-implicitdef.ll
index 9be045271d8d..a0766f99496c 100644
--- a/test/CodeGen/X86/coalesce-implicitdef.ll
+++ b/test/CodeGen/X86/coalesce-implicitdef.ll
@@ -71,7 +71,7 @@ for.inc27.backedge:                               ; preds = %while.end, %if.then
   br i1 %tobool17, label %for.inc27.if.end30.loopexit56_crit_edge, label %while.condthread-pre-split
 
 if.then22:                                        ; preds = %while.end
-  %1 = load i16* %p2.1, align 2
+  %1 = load i16, i16* %p2.1, align 2
   %tobool23 = icmp eq i16 %1, 0
   br i1 %tobool23, label %for.inc27.backedge, label %label.loopexit
 
@@ -89,7 +89,7 @@ for.inc27.if.end30.loopexit56_crit_edge:          ; preds = %for.inc27.backedge
 if.end30:                                         ; preds = %for.inc27.if.end30.loopexit56_crit_edge, %label.loopexit, %label.preheader, %for.inc
   %i.0.load46 = phi i32 [ 0, %for.inc ], [ %i.0.load4669, %label.preheader ], [ %i.0.load4669, %label.loopexit ], [ %i.0.load4669, %for.inc27.if.end30.loopexit56_crit_edge ]
   %pi.4 = phi i32* [ %i, %for.inc ], [ %pi.3.ph, %label.preheader ], [ %pi.3.ph, %label.loopexit ], [ %pi.3.ph, %for.inc27.if.end30.loopexit56_crit_edge ]
-  %2 = load i32* %pi.4, align 4
+  %2 = load i32, i32* %pi.4, align 4
   %tobool31 = icmp eq i32 %2, 0
   br i1 %tobool31, label %for.inc34, label %label.preheader
 
@@ -100,7 +100,7 @@ for.inc34:                                        ; preds = %if.end30
 
 for.end36:                                        ; preds = %for.cond
   store i32 1, i32* %i, align 4
-  %3 = load i32* @c, align 4
+  %3 = load i32, i32* @c, align 4
   %tobool37 = icmp eq i32 %3, 0
   br i1 %tobool37, label %label.preheader, label %land.rhs
 
@@ -111,15 +111,15 @@ land.rhs:                                         ; preds = %for.end36
 label.preheader:                                  ; preds = %for.end36, %if.end30, %land.rhs
   %i.0.load4669 = phi i32 [ 1, %land.rhs ], [ %i.0.load46, %if.end30 ], [ 1, %for.end36 ]
   %pi.3.ph = phi i32* [ %pi.0, %land.rhs ], [ %pi.4, %if.end30 ], [ %pi.0, %for.end36 ]
-  %4 = load i32* @b, align 4
+  %4 = load i32, i32* @b, align 4
   %inc285863 = add nsw i32 %4, 1
   store i32 %inc285863, i32* @b, align 4
   %tobool175964 = icmp eq i32 %inc285863, 0
   br i1 %tobool175964, label %if.end30, label %while.condthread-pre-split.lr.ph.lr.ph
 
 while.condthread-pre-split.lr.ph.lr.ph:           ; preds = %label.preheader
-  %.pr50 = load i32* @d, align 4
+  %.pr50 = load i32, i32* @d, align 4
   %tobool19 = icmp eq i32 %.pr50, 0
-  %a.promoted.pre = load i32* @a, align 4
+  %a.promoted.pre = load i32, i32* @a, align 4
   br label %while.condthread-pre-split
 }
diff --git a/test/CodeGen/X86/coalescer-commute1.ll b/test/CodeGen/X86/coalescer-commute1.ll
index cbcb89031b5b..dccf3b906fd9 100644
--- a/test/CodeGen/X86/coalescer-commute1.ll
+++ b/test/CodeGen/X86/coalescer-commute1.ll
@@ -6,14 +6,14 @@
 
 define void @runcont(i32* %source) nounwind  {
 entry:
-	%tmp10 = load i32* @NNTOT, align 4		; <i32> [#uses=1]
+	%tmp10 = load i32, i32* @NNTOT, align 4		; <i32> [#uses=1]
 	br label %bb
 
 bb:		; preds = %bb, %entry
 	%neuron.0 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]		; <i32> [#uses=2]
 	%thesum.0 = phi float [ 0.000000e+00, %entry ], [ %tmp6, %bb ]		; <float> [#uses=1]
-	%tmp2 = getelementptr i32* %source, i32 %neuron.0		; <i32*> [#uses=1]
-	%tmp3 = load i32* %tmp2, align 4		; <i32> [#uses=1]
+	%tmp2 = getelementptr i32, i32* %source, i32 %neuron.0		; <i32*> [#uses=1]
+	%tmp3 = load i32, i32* %tmp2, align 4		; <i32> [#uses=1]
 	%tmp34 = sitofp i32 %tmp3 to float		; <float> [#uses=1]
 	%tmp6 = fadd float %tmp34, %thesum.0		; <float> [#uses=2]
 	%indvar.next = add i32 %neuron.0, 1		; <i32> [#uses=2]
diff --git a/test/CodeGen/X86/coalescer-commute4.ll b/test/CodeGen/X86/coalescer-commute4.ll
index 02a97813fdcd..d4af1a62dca7 100644
--- a/test/CodeGen/X86/coalescer-commute4.ll
+++ b/test/CodeGen/X86/coalescer-commute4.ll
@@ -13,11 +13,11 @@ bb.preheader:		; preds = %entry
 bb:		; preds = %bb, %bb.preheader
 	%i.0.reg2mem.0 = phi i32 [ 0, %bb.preheader ], [ %indvar.next, %bb ]		; <i32> [#uses=3]
 	%res.0.reg2mem.0 = phi float [ 0.000000e+00, %bb.preheader ], [ %tmp14, %bb ]		; <float> [#uses=1]
-	%tmp3 = getelementptr i32* %x, i32 %i.0.reg2mem.0		; <i32*> [#uses=1]
-	%tmp4 = load i32* %tmp3, align 4		; <i32> [#uses=1]
+	%tmp3 = getelementptr i32, i32* %x, i32 %i.0.reg2mem.0		; <i32*> [#uses=1]
+	%tmp4 = load i32, i32* %tmp3, align 4		; <i32> [#uses=1]
 	%tmp45 = sitofp i32 %tmp4 to float		; <float> [#uses=1]
-	%tmp8 = getelementptr float* %y, i32 %i.0.reg2mem.0		; <float*> [#uses=1]
-	%tmp9 = load float* %tmp8, align 4		; <float> [#uses=1]
+	%tmp8 = getelementptr float, float* %y, i32 %i.0.reg2mem.0		; <float*> [#uses=1]
+	%tmp9 = load float, float* %tmp8, align 4		; <float> [#uses=1]
 	%tmp11 = fmul float %tmp9, %tmp45		; <float> [#uses=1]
 	%tmp14 = fadd float %tmp11, %res.0.reg2mem.0		; <float> [#uses=2]
 	%indvar.next = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=2]
diff --git a/test/CodeGen/X86/coalescer-cross.ll b/test/CodeGen/X86/coalescer-cross.ll
index 3f1fec131214..92aedbef5dd4 100644
--- a/test/CodeGen/X86/coalescer-cross.ll
+++ b/test/CodeGen/X86/coalescer-cross.ll
@@ -30,14 +30,14 @@ entry:
 	%0 = tail call i32 @"\01_clock$UNIX2003"() nounwind		; <i32> [#uses=1]
 	%1 = uitofp i32 %0 to double		; <double> [#uses=1]
 	%2 = fdiv double %1, 1.000000e+06		; <double> [#uses=1]
-	%3 = getelementptr %struct.lua_State* %L, i32 0, i32 4		; <%struct.TValue**> [#uses=3]
-	%4 = load %struct.TValue** %3, align 4		; <%struct.TValue*> [#uses=2]
-	%5 = getelementptr %struct.TValue* %4, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%3 = getelementptr %struct.lua_State, %struct.lua_State* %L, i32 0, i32 4		; <%struct.TValue**> [#uses=3]
+	%4 = load %struct.TValue*, %struct.TValue** %3, align 4		; <%struct.TValue*> [#uses=2]
+	%5 = getelementptr %struct.TValue, %struct.TValue* %4, i32 0, i32 0, i32 0		; <double*> [#uses=1]
 	store double %2, double* %5, align 4
-	%6 = getelementptr %struct.TValue* %4, i32 0, i32 1		; <i32*> [#uses=1]
+	%6 = getelementptr %struct.TValue, %struct.TValue* %4, i32 0, i32 1		; <i32*> [#uses=1]
 	store i32 3, i32* %6, align 4
-	%7 = load %struct.TValue** %3, align 4		; <%struct.TValue*> [#uses=1]
-	%8 = getelementptr %struct.TValue* %7, i32 1		; <%struct.TValue*> [#uses=1]
+	%7 = load %struct.TValue*, %struct.TValue** %3, align 4		; <%struct.TValue*> [#uses=1]
+	%8 = getelementptr %struct.TValue, %struct.TValue* %7, i32 1		; <%struct.TValue*> [#uses=1]
 	store %struct.TValue* %8, %struct.TValue** %3, align 4
 	ret i32 1
 }
diff --git a/test/CodeGen/X86/coalescer-dce2.ll b/test/CodeGen/X86/coalescer-dce2.ll
index bbbf09b267b9..116a70484363 100644
--- a/test/CodeGen/X86/coalescer-dce2.ll
+++ b/test/CodeGen/X86/coalescer-dce2.ll
@@ -14,19 +14,19 @@ target triple = "x86_64-apple-macosx10.7.0"
 
 define void @fn1() nounwind uwtable ssp {
 entry:
-  %0 = load i32* @d, align 4
+  %0 = load i32, i32* @d, align 4
   %tobool72 = icmp eq i32 %0, 0
   br i1 %tobool72, label %for.end32, label %for.cond1.preheader.lr.ph
 
 for.cond1.preheader.lr.ph:                        ; preds = %entry
-  %1 = load i32* @c, align 4
+  %1 = load i32, i32* @c, align 4
   %tobool2 = icmp eq i32 %1, 0
-  %2 = load i32* @b, align 4
+  %2 = load i32, i32* @b, align 4
   %cmp = icmp sgt i32 %2, 0
   %conv = zext i1 %cmp to i32
-  %3 = load i32* @g, align 4
+  %3 = load i32, i32* @g, align 4
   %tobool4 = icmp eq i32 %3, 0
-  %4 = load i16* @a, align 2
+  %4 = load i16, i16* @a, align 2
   %tobool9 = icmp eq i16 %4, 0
   br label %for.cond1.preheader
 
@@ -41,7 +41,7 @@ for.cond1.preheader.split.us:                     ; preds = %for.cond1.preheader
   br i1 %tobool9, label %cond.end.us.us, label %cond.end.us
 
 cond.false18.us.us:                               ; preds = %if.end.us.us
-  %5 = load i32* @f, align 4
+  %5 = load i32, i32* @f, align 4
   %sext76 = shl i32 %5, 16
   %phitmp75 = ashr exact i32 %sext76, 16
   br label %cond.end.us.us
@@ -74,7 +74,7 @@ land.lhs.true12.us:                               ; preds = %if.end6.us
   br i1 %cmp14.us, label %cond.end21.us, label %cond.false18.us
 
 if.end6.us:                                       ; preds = %if.end.us
-  %6 = load i32* @f, align 4
+  %6 = load i32, i32* @f, align 4
   %conv7.us = trunc i32 %6 to i16
   %tobool11.us = icmp eq i16 %conv7.us, 0
   br i1 %tobool11.us, label %cond.false18.us, label %land.lhs.true12.us
@@ -95,7 +95,7 @@ for.cond1.preheader.split.for.cond1.preheader.split.split_crit_edge: ; preds = %
   br i1 %tobool4, label %if.end6.us65, label %for.cond25.loopexit.us-lcssa.us-lcssa
 
 cond.false18.us40:                                ; preds = %if.end.us50
-  %7 = load i32* @f, align 4
+  %7 = load i32, i32* @f, align 4
   %sext = shl i32 %7, 16
   %phitmp = ashr exact i32 %sext, 16
   br label %if.end.us50
diff --git a/test/CodeGen/X86/coalescer-identity.ll b/test/CodeGen/X86/coalescer-identity.ll
index 1aac09594c43..8d581160aa80 100644
--- a/test/CodeGen/X86/coalescer-identity.ll
+++ b/test/CodeGen/X86/coalescer-identity.ll
@@ -12,10 +12,10 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 define void @func() nounwind uwtable ssp {
 for.body.lr.ph:
-  %0 = load i32* @g2, align 4
+  %0 = load i32, i32* @g2, align 4
   %tobool6 = icmp eq i32 %0, 0
-  %s.promoted = load i16* @s, align 2
-  %.pre = load i32* @g1, align 4
+  %s.promoted = load i16, i16* @s, align 2
+  %.pre = load i32, i32* @g1, align 4
   br i1 %tobool6, label %for.body.us, label %for.body
 
 for.body.us:                                      ; preds = %for.body.lr.ph, %for.inc.us
diff --git a/test/CodeGen/X86/coalescer-remat.ll b/test/CodeGen/X86/coalescer-remat.ll
index bb08a0ec52cd..62e0562fd500 100644
--- a/test/CodeGen/X86/coalescer-remat.ll
+++ b/test/CodeGen/X86/coalescer-remat.ll
@@ -7,7 +7,7 @@ define i32 @main() nounwind {
 entry:
   %t0 = cmpxchg i64* @val, i64 0, i64 1 monotonic monotonic
   %0 = extractvalue { i64, i1 } %t0, 0
-  %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([7 x i8]* @"\01LC", i32 0, i64 0), i64 %0) nounwind
+  %1 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([7 x i8], [7 x i8]* @"\01LC", i32 0, i64 0), i64 %0) nounwind
   ret i32 0
 }
 
diff --git a/test/CodeGen/X86/coalescer-subreg.ll b/test/CodeGen/X86/coalescer-subreg.ll
new file mode 100644
index 000000000000..be80dff779c9
--- /dev/null
+++ b/test/CodeGen/X86/coalescer-subreg.ll
@@ -0,0 +1,29 @@
+; RUN: llc -o - %s -verify-machineinstrs
+; This used to crash when coalescing a regclass like GR16 which did not support
+; the sub_8bit_hi subregister with a class like GR16_ABCD that did.
+target triple = "x86_64-apple-macosx10.10.0"
+
+define void @test() #0 {
+entry:
+  br i1 undef, label %loop, label %for.end597
+
+loop:
+  %0 = load i16, i16* null, align 4
+  %1 = load i16, i16* undef, align 4
+  %or1 = or i16 %1, %0
+  %or2 = trunc i16 %or1 to i8
+  store i8 %or2, i8* undef, align 4
+  %2 = or i16 %1, %0
+  %or3 = lshr i16 %2, 8
+  %or4 = trunc i16 %or3 to i8
+  store i8 %or4, i8* undef, align 1
+  %3 = load i32, i32* undef, align 4
+  %4 = load i32, i32* undef, align 4
+  %or5 = or i32 %4, %3
+  store i32 %or5, i32* undef, align 4
+  store i32 0, i32* undef, align 4
+  br label %loop
+
+for.end597:
+  ret void
+}
diff --git a/test/CodeGen/X86/code_placement.ll b/test/CodeGen/X86/code_placement.ll
index 97471835a4c9..7d2358480051 100644
--- a/test/CodeGen/X86/code_placement.ll
+++ b/test/CodeGen/X86/code_placement.ll
@@ -6,9 +6,9 @@
 
 define void @t(i8* nocapture %in, i8* nocapture %out, i32* nocapture %rk, i32 %r) nounwind ssp {
 entry:
-	%0 = load i32* %rk, align 4		; <i32> [#uses=1]
-	%1 = getelementptr i32* %rk, i64 1		; <i32*> [#uses=1]
-	%2 = load i32* %1, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* %rk, align 4		; <i32> [#uses=1]
+	%1 = getelementptr i32, i32* %rk, i64 1		; <i32*> [#uses=1]
+	%2 = load i32, i32* %1, align 4		; <i32> [#uses=1]
 	%tmp15 = add i32 %r, -1		; <i32> [#uses=1]
 	%tmp.16 = zext i32 %tmp15 to i64		; <i64> [#uses=2]
 	br label %bb
@@ -23,64 +23,64 @@ bb:		; preds = %bb1, %entry
 	%rk26 = bitcast i32* %rk to i8*		; <i8*> [#uses=6]
 	%3 = lshr i32 %s0.0, 24		; <i32> [#uses=1]
 	%4 = zext i32 %3 to i64		; <i64> [#uses=1]
-	%5 = getelementptr [256 x i32]* @Te0, i64 0, i64 %4		; <i32*> [#uses=1]
-	%6 = load i32* %5, align 4		; <i32> [#uses=1]
+	%5 = getelementptr [256 x i32], [256 x i32]* @Te0, i64 0, i64 %4		; <i32*> [#uses=1]
+	%6 = load i32, i32* %5, align 4		; <i32> [#uses=1]
 	%7 = lshr i32 %s1.0, 16		; <i32> [#uses=1]
 	%8 = and i32 %7, 255		; <i32> [#uses=1]
 	%9 = zext i32 %8 to i64		; <i64> [#uses=1]
-	%10 = getelementptr [256 x i32]* @Te1, i64 0, i64 %9		; <i32*> [#uses=1]
-	%11 = load i32* %10, align 4		; <i32> [#uses=1]
+	%10 = getelementptr [256 x i32], [256 x i32]* @Te1, i64 0, i64 %9		; <i32*> [#uses=1]
+	%11 = load i32, i32* %10, align 4		; <i32> [#uses=1]
 	%ctg2.sum2728 = or i64 %tmp18, 8		; <i64> [#uses=1]
-	%12 = getelementptr i8* %rk26, i64 %ctg2.sum2728		; <i8*> [#uses=1]
+	%12 = getelementptr i8, i8* %rk26, i64 %ctg2.sum2728		; <i8*> [#uses=1]
 	%13 = bitcast i8* %12 to i32*		; <i32*> [#uses=1]
-	%14 = load i32* %13, align 4		; <i32> [#uses=1]
+	%14 = load i32, i32* %13, align 4		; <i32> [#uses=1]
 	%15 = xor i32 %11, %6		; <i32> [#uses=1]
 	%16 = xor i32 %15, %14		; <i32> [#uses=3]
 	%17 = lshr i32 %s1.0, 24		; <i32> [#uses=1]
 	%18 = zext i32 %17 to i64		; <i64> [#uses=1]
-	%19 = getelementptr [256 x i32]* @Te0, i64 0, i64 %18		; <i32*> [#uses=1]
-	%20 = load i32* %19, align 4		; <i32> [#uses=1]
+	%19 = getelementptr [256 x i32], [256 x i32]* @Te0, i64 0, i64 %18		; <i32*> [#uses=1]
+	%20 = load i32, i32* %19, align 4		; <i32> [#uses=1]
 	%21 = and i32 %s0.0, 255		; <i32> [#uses=1]
 	%22 = zext i32 %21 to i64		; <i64> [#uses=1]
-	%23 = getelementptr [256 x i32]* @Te3, i64 0, i64 %22		; <i32*> [#uses=1]
-	%24 = load i32* %23, align 4		; <i32> [#uses=1]
+	%23 = getelementptr [256 x i32], [256 x i32]* @Te3, i64 0, i64 %22		; <i32*> [#uses=1]
+	%24 = load i32, i32* %23, align 4		; <i32> [#uses=1]
 	%ctg2.sum2930 = or i64 %tmp18, 12		; <i64> [#uses=1]
-	%25 = getelementptr i8* %rk26, i64 %ctg2.sum2930		; <i8*> [#uses=1]
+	%25 = getelementptr i8, i8* %rk26, i64 %ctg2.sum2930		; <i8*> [#uses=1]
 	%26 = bitcast i8* %25 to i32*		; <i32*> [#uses=1]
-	%27 = load i32* %26, align 4		; <i32> [#uses=1]
+	%27 = load i32, i32* %26, align 4		; <i32> [#uses=1]
 	%28 = xor i32 %24, %20		; <i32> [#uses=1]
 	%29 = xor i32 %28, %27		; <i32> [#uses=4]
 	%30 = lshr i32 %16, 24		; <i32> [#uses=1]
 	%31 = zext i32 %30 to i64		; <i64> [#uses=1]
-	%32 = getelementptr [256 x i32]* @Te0, i64 0, i64 %31		; <i32*> [#uses=1]
-	%33 = load i32* %32, align 4		; <i32> [#uses=2]
+	%32 = getelementptr [256 x i32], [256 x i32]* @Te0, i64 0, i64 %31		; <i32*> [#uses=1]
+	%33 = load i32, i32* %32, align 4		; <i32> [#uses=2]
 	%exitcond = icmp eq i64 %indvar, %tmp.16		; <i1> [#uses=1]
 	br i1 %exitcond, label %bb2, label %bb1
 
 bb1:		; preds = %bb
 	%ctg2.sum31 = add i64 %tmp18, 16		; <i64> [#uses=1]
-	%34 = getelementptr i8* %rk26, i64 %ctg2.sum31		; <i8*> [#uses=1]
+	%34 = getelementptr i8, i8* %rk26, i64 %ctg2.sum31		; <i8*> [#uses=1]
 	%35 = bitcast i8* %34 to i32*		; <i32*> [#uses=1]
 	%36 = lshr i32 %29, 16		; <i32> [#uses=1]
 	%37 = and i32 %36, 255		; <i32> [#uses=1]
 	%38 = zext i32 %37 to i64		; <i64> [#uses=1]
-	%39 = getelementptr [256 x i32]* @Te1, i64 0, i64 %38		; <i32*> [#uses=1]
-	%40 = load i32* %39, align 4		; <i32> [#uses=1]
-	%41 = load i32* %35, align 4		; <i32> [#uses=1]
+	%39 = getelementptr [256 x i32], [256 x i32]* @Te1, i64 0, i64 %38		; <i32*> [#uses=1]
+	%40 = load i32, i32* %39, align 4		; <i32> [#uses=1]
+	%41 = load i32, i32* %35, align 4		; <i32> [#uses=1]
 	%42 = xor i32 %40, %33		; <i32> [#uses=1]
 	%43 = xor i32 %42, %41		; <i32> [#uses=1]
 	%44 = lshr i32 %29, 24		; <i32> [#uses=1]
 	%45 = zext i32 %44 to i64		; <i64> [#uses=1]
-	%46 = getelementptr [256 x i32]* @Te0, i64 0, i64 %45		; <i32*> [#uses=1]
-	%47 = load i32* %46, align 4		; <i32> [#uses=1]
+	%46 = getelementptr [256 x i32], [256 x i32]* @Te0, i64 0, i64 %45		; <i32*> [#uses=1]
+	%47 = load i32, i32* %46, align 4		; <i32> [#uses=1]
 	%48 = and i32 %16, 255		; <i32> [#uses=1]
 	%49 = zext i32 %48 to i64		; <i64> [#uses=1]
-	%50 = getelementptr [256 x i32]* @Te3, i64 0, i64 %49		; <i32*> [#uses=1]
-	%51 = load i32* %50, align 4		; <i32> [#uses=1]
+	%50 = getelementptr [256 x i32], [256 x i32]* @Te3, i64 0, i64 %49		; <i32*> [#uses=1]
+	%51 = load i32, i32* %50, align 4		; <i32> [#uses=1]
 	%ctg2.sum32 = add i64 %tmp18, 20		; <i64> [#uses=1]
-	%52 = getelementptr i8* %rk26, i64 %ctg2.sum32		; <i8*> [#uses=1]
+	%52 = getelementptr i8, i8* %rk26, i64 %ctg2.sum32		; <i8*> [#uses=1]
 	%53 = bitcast i8* %52 to i32*		; <i32*> [#uses=1]
-	%54 = load i32* %53, align 4		; <i32> [#uses=1]
+	%54 = load i32, i32* %53, align 4		; <i32> [#uses=1]
 	%55 = xor i32 %51, %47		; <i32> [#uses=1]
 	%56 = xor i32 %55, %54		; <i32> [#uses=1]
 	%indvar.next = add i64 %indvar, 1		; <i64> [#uses=1]
@@ -89,48 +89,48 @@ bb1:		; preds = %bb
 bb2:		; preds = %bb
 	%tmp10 = shl i64 %tmp.16, 4		; <i64> [#uses=2]
 	%ctg2.sum = add i64 %tmp10, 16		; <i64> [#uses=1]
-	%tmp1213 = getelementptr i8* %rk26, i64 %ctg2.sum		; <i8*> [#uses=1]
+	%tmp1213 = getelementptr i8, i8* %rk26, i64 %ctg2.sum		; <i8*> [#uses=1]
 	%57 = bitcast i8* %tmp1213 to i32*		; <i32*> [#uses=1]
 	%58 = and i32 %33, -16777216		; <i32> [#uses=1]
 	%59 = lshr i32 %29, 16		; <i32> [#uses=1]
 	%60 = and i32 %59, 255		; <i32> [#uses=1]
 	%61 = zext i32 %60 to i64		; <i64> [#uses=1]
-	%62 = getelementptr [256 x i32]* @Te1, i64 0, i64 %61		; <i32*> [#uses=1]
-	%63 = load i32* %62, align 4		; <i32> [#uses=1]
+	%62 = getelementptr [256 x i32], [256 x i32]* @Te1, i64 0, i64 %61		; <i32*> [#uses=1]
+	%63 = load i32, i32* %62, align 4		; <i32> [#uses=1]
 	%64 = and i32 %63, 16711680		; <i32> [#uses=1]
 	%65 = or i32 %64, %58		; <i32> [#uses=1]
-	%66 = load i32* %57, align 4		; <i32> [#uses=1]
+	%66 = load i32, i32* %57, align 4		; <i32> [#uses=1]
 	%67 = xor i32 %65, %66		; <i32> [#uses=2]
 	%68 = lshr i32 %29, 8		; <i32> [#uses=1]
 	%69 = zext i32 %68 to i64		; <i64> [#uses=1]
-	%70 = getelementptr [256 x i32]* @Te0, i64 0, i64 %69		; <i32*> [#uses=1]
-	%71 = load i32* %70, align 4		; <i32> [#uses=1]
+	%70 = getelementptr [256 x i32], [256 x i32]* @Te0, i64 0, i64 %69		; <i32*> [#uses=1]
+	%71 = load i32, i32* %70, align 4		; <i32> [#uses=1]
 	%72 = and i32 %71, -16777216		; <i32> [#uses=1]
 	%73 = and i32 %16, 255		; <i32> [#uses=1]
 	%74 = zext i32 %73 to i64		; <i64> [#uses=1]
-	%75 = getelementptr [256 x i32]* @Te1, i64 0, i64 %74		; <i32*> [#uses=1]
-	%76 = load i32* %75, align 4		; <i32> [#uses=1]
+	%75 = getelementptr [256 x i32], [256 x i32]* @Te1, i64 0, i64 %74		; <i32*> [#uses=1]
+	%76 = load i32, i32* %75, align 4		; <i32> [#uses=1]
 	%77 = and i32 %76, 16711680		; <i32> [#uses=1]
 	%78 = or i32 %77, %72		; <i32> [#uses=1]
 	%ctg2.sum25 = add i64 %tmp10, 20		; <i64> [#uses=1]
-	%79 = getelementptr i8* %rk26, i64 %ctg2.sum25		; <i8*> [#uses=1]
+	%79 = getelementptr i8, i8* %rk26, i64 %ctg2.sum25		; <i8*> [#uses=1]
 	%80 = bitcast i8* %79 to i32*		; <i32*> [#uses=1]
-	%81 = load i32* %80, align 4		; <i32> [#uses=1]
+	%81 = load i32, i32* %80, align 4		; <i32> [#uses=1]
 	%82 = xor i32 %78, %81		; <i32> [#uses=2]
 	%83 = lshr i32 %67, 24		; <i32> [#uses=1]
 	%84 = trunc i32 %83 to i8		; <i8> [#uses=1]
 	store i8 %84, i8* %out, align 1
 	%85 = lshr i32 %67, 16		; <i32> [#uses=1]
 	%86 = trunc i32 %85 to i8		; <i8> [#uses=1]
-	%87 = getelementptr i8* %out, i64 1		; <i8*> [#uses=1]
+	%87 = getelementptr i8, i8* %out, i64 1		; <i8*> [#uses=1]
 	store i8 %86, i8* %87, align 1
-	%88 = getelementptr i8* %out, i64 4		; <i8*> [#uses=1]
+	%88 = getelementptr i8, i8* %out, i64 4		; <i8*> [#uses=1]
 	%89 = lshr i32 %82, 24		; <i32> [#uses=1]
 	%90 = trunc i32 %89 to i8		; <i8> [#uses=1]
 	store i8 %90, i8* %88, align 1
 	%91 = lshr i32 %82, 16		; <i32> [#uses=1]
 	%92 = trunc i32 %91 to i8		; <i8> [#uses=1]
-	%93 = getelementptr i8* %out, i64 5		; <i8*> [#uses=1]
+	%93 = getelementptr i8, i8* %out, i64 5		; <i8*> [#uses=1]
 	store i8 %92, i8* %93, align 1
 	ret void
 }
diff --git a/test/CodeGen/X86/code_placement_outline_optional_branches.ll b/test/CodeGen/X86/code_placement_outline_optional_branches.ll
new file mode 100644
index 000000000000..3364915fd1b7
--- /dev/null
+++ b/test/CodeGen/X86/code_placement_outline_optional_branches.ll
@@ -0,0 +1,77 @@
+; RUN: llc -mcpu=corei7 -mtriple=x86_64-linux < %s | FileCheck %s -check-prefix=CHECK
+; RUN: llc -mcpu=corei7 -mtriple=x86_64-linux -outline-optional-branches < %s | FileCheck %s -check-prefix=CHECK-OUTLINE
+
+define void @foo(i32 %t1, i32 %t2, i32 %t3) {
+; Test that we lift the call to 'c' up to immediately follow the call to 'b'
+; when we disable the cfg conflict check.
+;
+; CHECK-LABEL: foo:
+; CHECK: callq a
+; CHECK: callq a
+; CHECK: callq a
+; CHECK: callq a
+; CHECK: callq b
+; CHECK: callq c
+; CHECK: callq d
+; CHECK: callq e
+; CHECK: callq f
+;
+; CHECK-OUTLINE-LABEL: foo:
+; CHECK-OUTLINE: callq b
+; CHECK-OUTLINE: callq c
+; CHECK-OUTLINE: callq d
+; CHECK-OUTLINE: callq e
+; CHECK-OUTLINE: callq f
+; CHECK-OUTLINE: callq a
+; CHECK-OUTLINE: callq a
+; CHECK-OUTLINE: callq a
+; CHECK-OUTLINE: callq a
+
+entry:
+  %cmp = icmp eq i32 %t1, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  call void @a()
+  call void @a()
+  call void @a()
+  call void @a()
+  br label %if.end
+
+if.end:
+  call void @b()
+  br label %hotbranch
+
+hotbranch:
+  %cmp2 = icmp eq i32 %t2, 0
+  br i1 %cmp2, label %if.then2, label %if.end2, !prof !1
+
+if.then2:
+  call void @c()
+  br label %if.end2
+
+if.end2:
+  call void @d()
+  br label %shortbranch
+
+shortbranch:
+  %cmp3 = icmp eq i32 %t3, 0
+  br i1 %cmp3, label %if.then3, label %if.end3
+
+if.then3:
+  call void @e()
+  br label %if.end3
+
+if.end3:
+  call void @f()
+  ret void
+}
+
+declare void @a()
+declare void @b()
+declare void @c()
+declare void @d()
+declare void @e()
+declare void @f()
+
+!1 = !{!"branch_weights", i32 64, i32 4}
diff --git a/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll b/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll
index 85bfff2757e6..f00c40ba3a92 100644
--- a/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll
+++ b/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll
@@ -20,7 +20,7 @@ define i8 @twoArgsPromotion(i32 %arg1, i32 %arg2) {
   %add = add nsw i32 %arg1, %arg2 
   %sextadd = sext i32 %add to i64
   %base = inttoptr i64 %sextadd to i8*
-  %res = load i8* %base
+  %res = load i8, i8* %base
   ret i8 %res
 }
 
@@ -35,8 +35,8 @@ define i8 @twoArgsPromotion(i32 %arg1, i32 %arg2) {
 define i8 @twoArgsNoPromotion(i32 %arg1, i32 %arg2, i8* %base) {
   %add = add nsw i32 %arg1, %arg2 
   %sextadd = sext i32 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %sextadd
+  %res = load i8, i8* %arrayidx
   ret i8 %res
 }
 
@@ -48,8 +48,8 @@ define i8 @twoArgsNoPromotion(i32 %arg1, i32 %arg2, i8* %base) {
 define i8 @noPromotion(i32 %arg1, i32 %arg2, i8* %base) {
   %add = add i32 %arg1, %arg2 
   %sextadd = sext i32 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %sextadd
+  %res = load i8, i8* %arrayidx
   ret i8 %res
 }
 
@@ -57,13 +57,13 @@ define i8 @noPromotion(i32 %arg1, i32 %arg2, i8* %base) {
 ; CHECK-LABEL: @oneArgPromotion
 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg1 to i64
 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
-; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
+; CHECK: getelementptr inbounds i8, i8* %base, i64 [[PROMOTED]]
 ; CHECK: ret
 define i8 @oneArgPromotion(i32 %arg1, i8* %base) {
   %add = add nsw i32 %arg1, 1 
   %sextadd = sext i32 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %sextadd
+  %res = load i8, i8* %arrayidx
   ret i8 %res
 }
 
@@ -71,14 +71,14 @@ define i8 @oneArgPromotion(i32 %arg1, i8* %base) {
 ; CHECK-LABEL: @oneArgPromotionZExt
 ; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 %arg1 to i64
 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1ZEXT]], 1
-; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
+; CHECK: getelementptr inbounds i8, i8* %base, i64 [[PROMOTED]]
 ; CHECK: ret
 define i8 @oneArgPromotionZExt(i8 %arg1, i8* %base) {
   %zext = zext i8 %arg1 to i32
   %add = add nsw i32 %zext, 1 
   %sextadd = sext i32 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %sextadd
+  %res = load i8, i8* %arrayidx
   ret i8 %res
 }
 
@@ -90,17 +90,15 @@ define i8 @oneArgPromotionZExt(i8 %arg1, i8* %base) {
 ; rolled back.
 ; Still, this test case exercises the desired code path.
 ; CHECK-LABEL: @oneArgPromotionCstZExt
-; CHECK: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i16 undef to i32
-; CHECK: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i32 [[ZEXT]] to i64
-; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXT]], 1
-; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
+; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 0, 1
+; CHECK: getelementptr inbounds i8, i8* %base, i64 [[PROMOTED]]
 ; CHECK: ret
 define i8 @oneArgPromotionCstZExt(i8* %base) {
   %cst = zext i16 undef to i32
   %add = add nsw i32 %cst, 1
   %sextadd = sext i32 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %sextadd
+  %res = load i8, i8* %arrayidx
   ret i8 %res
 }
 
@@ -110,14 +108,14 @@ define i8 @oneArgPromotionCstZExt(i8* %base) {
 ; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 %arg1 to i8
 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64
 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
-; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
+; CHECK: getelementptr inbounds i8, i8* %base, i64 [[PROMOTED]]
 ; CHECK: ret
 define i8 @oneArgPromotionBlockTrunc1(i32 %arg1, i8* %base) {
   %trunc = trunc i32 %arg1 to i8
   %add = add nsw i8 %trunc, 1 
   %sextadd = sext i8 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %sextadd
+  %res = load i8, i8* %arrayidx
   ret i8 %res
 }
 
@@ -128,15 +126,15 @@ define i8 @oneArgPromotionBlockTrunc1(i32 %arg1, i8* %base) {
 ; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 [[ARG1SEXT]] to i8
 ; CHECK: [[ARG1SEXT64:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64
 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT64]], 1
-; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
+; CHECK: getelementptr inbounds i8, i8* %base, i64 [[PROMOTED]]
 ; CHECK: ret
 define i8 @oneArgPromotionBlockTrunc2(i16 %arg1, i8* %base) {
   %sextarg1 = sext i16 %arg1 to i32
   %trunc = trunc i32 %sextarg1 to i8
   %add = add nsw i8 %trunc, 1 
   %sextadd = sext i8 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %sextadd
+  %res = load i8, i8* %arrayidx
   ret i8 %res
 }
 
@@ -145,15 +143,15 @@ define i8 @oneArgPromotionBlockTrunc2(i16 %arg1, i8* %base) {
 ; CHECK-LABEL: @oneArgPromotionPassTruncKeepSExt
 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i1 %arg1 to i64
 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
-; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
+; CHECK: getelementptr inbounds i8, i8* %base, i64 [[PROMOTED]]
 ; CHECK: ret
 define i8 @oneArgPromotionPassTruncKeepSExt(i1 %arg1, i8* %base) {
   %sextarg1 = sext i1 %arg1 to i32
   %trunc = trunc i32 %sextarg1 to i8
   %add = add nsw i8 %trunc, 1 
   %sextadd = sext i8 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %sextadd
+  %res = load i8, i8* %arrayidx
   ret i8 %res
 }
 
@@ -164,15 +162,15 @@ define i8 @oneArgPromotionPassTruncKeepSExt(i1 %arg1, i8* %base) {
 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 %arg1 to i64
 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
 ; CHECK: [[TRUNC:%[a-zA-Z_0-9-]+]] = trunc i64 [[PROMOTED]] to i8
-; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8* %base, i64 [[PROMOTED]]
-; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8* [[GEP]]
+; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8, i8* %base, i64 [[PROMOTED]]
+; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8, i8* [[GEP]]
 ; CHECK: add i8 [[LOAD]], [[TRUNC]]
 ; CHECK: ret
 define i8 @oneArgPromotionTruncInsert(i8 %arg1, i8* %base) {
   %add = add nsw i8 %arg1, 1 
   %sextadd = sext i8 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %sextadd
+  %res = load i8, i8* %arrayidx
   %finalres = add i8 %res, %add
   ret i8 %finalres
 }
@@ -182,14 +180,14 @@ define i8 @oneArgPromotionTruncInsert(i8 %arg1, i8* %base) {
 ; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i128 %arg1 to i8
 ; CHECK: [[ARG1SEXT64:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64
 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT64]], 1
-; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
+; CHECK: getelementptr inbounds i8, i8* %base, i64 [[PROMOTED]]
 ; CHECK: ret
 define i8 @oneArgPromotionLargerType(i128 %arg1, i8* %base) {
   %trunc = trunc i128 %arg1 to i8
   %add = add nsw i8 %trunc, 1 
   %sextadd = sext i8 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %sextadd
+  %res = load i8, i8* %arrayidx
   %finalres = add i8 %res, %add
   ret i8 %finalres
 }
@@ -202,16 +200,16 @@ define i8 @oneArgPromotionLargerType(i128 %arg1, i8* %base) {
 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 %arg1 to i64
 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
 ; CHECK: [[TRUNC:%[a-zA-Z_0-9-]+]] = trunc i64 [[PROMOTED]] to i8
-; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8* %base, i64 [[PROMOTED]]
-; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8* [[GEP]]
+; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8, i8* %base, i64 [[PROMOTED]]
+; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8, i8* [[GEP]]
 ; CHECK: [[ADDRES:%[a-zA-Z_0-9-]+]] = add i8 [[LOAD]], [[TRUNC]]
 ; CHECK: add i8 [[ADDRES]], [[TRUNC]]
 ; CHECK: ret
 define i8 @oneArgPromotionTruncInsertSeveralUse(i8 %arg1, i8* %base) {
   %add = add nsw i8 %arg1, 1 
   %sextadd = sext i8 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %sextadd
+  %res = load i8, i8* %arrayidx
   %almostfinalres = add i8 %res, %add
   %finalres = add i8 %almostfinalres, %add
   ret i8 %finalres
@@ -222,16 +220,16 @@ define i8 @oneArgPromotionTruncInsertSeveralUse(i8 %arg1, i8* %base) {
 ; CHECK-LABEL: @oneArgPromotionSExtSeveralUse
 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 %arg1 to i64
 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
-; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8* %base, i64 [[PROMOTED]]
-; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8* [[GEP]]
+; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8, i8* %base, i64 [[PROMOTED]]
+; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8, i8* [[GEP]]
 ; CHECK: [[ADDRES:%[a-zA-Z_0-9-]+]] = zext i8 [[LOAD]] to i64
 ; CHECK: add i64 [[ADDRES]], [[PROMOTED]]
 ; CHECK: ret
 define i64 @oneArgPromotionSExtSeveralUse(i8 %arg1, i8* %base) {
   %add = add nsw i8 %arg1, 1 
   %sextadd = sext i8 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %sextadd
+  %res = load i8, i8* %arrayidx
   %almostfinalres = zext i8 %res to i64
   %finalres = add i64 %almostfinalres, %sextadd
   ret i64 %finalres
@@ -257,14 +255,14 @@ define i64 @oneArgPromotionSExtSeveralUse(i8 %arg1, i8* %base) {
 ; CHECK: [[ORIG:%[a-zA-Z_0-9-]+]] = add nsw i32 %arg1, %arg2
 ; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ORIG]], [[ORIG]]
 ; CHECK: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64
-; CHECK: getelementptr inbounds i8* %base, i64 [[SEXT]]
+; CHECK: getelementptr inbounds i8, i8* %base, i64 [[SEXT]]
 ; CHECK: ret
 define i8 @twoArgsPromotionNest(i32 %arg1, i32 %arg2, i8* %base) {
   %promotableadd1 = add nsw i32 %arg1, %arg2
   %promotableadd2 = add nsw i32 %promotableadd1, %promotableadd1 
   %sextadd = sext i32 %promotableadd2 to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %sextadd
+  %res = load i8, i8* %arrayidx
   ret i8 %res
 }
 
@@ -279,15 +277,15 @@ define i8 @twoArgsPromotionNest(i32 %arg1, i32 %arg2, i8* %base) {
 ; CHECK: [[TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 [[SEXTARG1]] to i8
 ; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[TRUNC]], %arg2
 ; CHECK: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i64
-; CHECK: getelementptr inbounds i8* %base, i64 [[SEXT]]
+; CHECK: getelementptr inbounds i8, i8* %base, i64 [[SEXT]]
 ; CHECK: ret
 define i8 @twoArgsNoPromotionRemove(i1 %arg1, i8 %arg2, i8* %base) {
   %sextarg1 = sext i1 %arg1 to i32
   %trunc = trunc i32 %sextarg1 to i8
   %add = add nsw i8 %trunc, %arg2 
   %sextadd = sext i8 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %sextadd
+  %res = load i8, i8* %arrayidx
   ret i8 %res
 }
 
@@ -313,11 +311,11 @@ define i8 @twoArgsNoPromotionRemove(i1 %arg1, i8 %arg2, i8* %base) {
 ; BB then
 ; CHECK: [[BASE1:%[a-zA-Z_0-9-]+]] = add i64 [[SEXTADD]], 48
 ; CHECK: [[ADDR1:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[BASE1]] to i32*
-; CHECK: load i32* [[ADDR1]]
+; CHECK: load i32, i32* [[ADDR1]]
 ; BB else
 ; CHECK: [[BASE2:%[a-zA-Z_0-9-]+]] = add i64 [[SEXTADD]], 48
 ; CHECK: [[ADDR2:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[BASE2]] to i32*
-; CHECK: load i32* [[ADDR2]]
+; CHECK: load i32, i32* [[ADDR2]]
 ; CHECK: ret
 ; CHECK-GEP-LABEL: @checkProfitability
 ; CHECK-GEP-NOT: {{%[a-zA-Z_0-9-]+}} = sext i32 %arg1 to i64
@@ -328,34 +326,34 @@ define i8 @twoArgsNoPromotionRemove(i1 %arg1, i8 %arg2, i8* %base) {
 ; BB then
 ; CHECK-GEP: [[BASE1:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[SEXTADD]] to i32*
 ; CHECK-GEP: [[BCC1:%[a-zA-Z_0-9-]+]] = bitcast i32* [[BASE1]] to i8*
-; CHECK-GEP: [[FULL1:%[a-zA-Z_0-9-]+]] = getelementptr i8* [[BCC1]], i64 48
+; CHECK-GEP: [[FULL1:%[a-zA-Z_0-9-]+]] = getelementptr i8, i8* [[BCC1]], i64 48
 ; CHECK-GEP: [[ADDR1:%[a-zA-Z_0-9-]+]] = bitcast i8* [[FULL1]] to i32*
-; CHECK-GEP: load i32* [[ADDR1]]
+; CHECK-GEP: load i32, i32* [[ADDR1]]
 ; BB else
 ; CHECK-GEP: [[BASE2:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[SEXTADD]] to i32*
 ; CHECK-GEP: [[BCC2:%[a-zA-Z_0-9-]+]] = bitcast i32* [[BASE2]] to i8*
-; CHECK-GEP: [[FULL2:%[a-zA-Z_0-9-]+]] = getelementptr i8* [[BCC2]], i64 48
+; CHECK-GEP: [[FULL2:%[a-zA-Z_0-9-]+]] = getelementptr i8, i8* [[BCC2]], i64 48
 ; CHECK-GEP: [[ADDR2:%[a-zA-Z_0-9-]+]] = bitcast i8* [[FULL2]] to i32*
-; CHECK-GEP: load i32* [[ADDR2]]
+; CHECK-GEP: load i32, i32* [[ADDR2]]
 ; CHECK-GEP: ret
 define i32 @checkProfitability(i32 %arg1, i32 %arg2, i1 %test) {
   %shl = shl nsw i32 %arg1, 1
   %add1 = add nsw i32 %shl, %arg2
   %sextidx1 = sext i32 %add1 to i64
   %tmpptr = inttoptr i64 %sextidx1 to i32*
-  %arrayidx1 = getelementptr i32* %tmpptr, i64 12
+  %arrayidx1 = getelementptr i32, i32* %tmpptr, i64 12
   br i1 %test, label %then, label %else
 then: 
-  %res1 = load i32* %arrayidx1
+  %res1 = load i32, i32* %arrayidx1
   br label %end
 else:
-  %res2 = load i32* %arrayidx1
+  %res2 = load i32, i32* %arrayidx1
   br label %end
 end:
   %tmp = phi i32 [%res1, %then], [%res2, %else]
   %res = add i32 %tmp, %add1
   %addr = inttoptr i32 %res to i32*
-  %final = load i32* %addr
+  %final = load i32, i32* %addr
   ret i32 %final
 }
 
@@ -377,10 +375,10 @@ end:
 ; CHECK-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = add i64 [[BASE]], [[PROMOTED_CONV]]
 ; CHECK-NEXT: [[ADDR:%[a-zA-Z_0-9-]+]] = add i64 [[ADD]], 7
 ; CHECK-NEXT: [[CAST:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[ADDR]] to i8*
-; CHECK-NEXT: load i8* [[CAST]], align 1
+; CHECK-NEXT: load i8, i8* [[CAST]], align 1
 define signext i16 @fn3(%struct.dns_packet* nocapture readonly %P) {
 entry:
-  %tmp = getelementptr inbounds %struct.dns_packet* %P, i64 0, i32 2
+  %tmp = getelementptr inbounds %struct.dns_packet, %struct.dns_packet* %P, i64 0, i32 2
   %data.i.i = bitcast %union.anon* %tmp to [0 x i8]*
   br label %while.body.i.i
 
@@ -388,8 +386,8 @@ while.body.i.i:                                   ; preds = %while.body.i.i, %en
   %src.addr.0.i.i = phi i16 [ 0, %entry ], [ %inc.i.i, %while.body.i.i ]
   %inc.i.i = add i16 %src.addr.0.i.i, 1
   %idxprom.i.i = sext i16 %src.addr.0.i.i to i64
-  %arrayidx.i.i = getelementptr inbounds [0 x i8]* %data.i.i, i64 0, i64 %idxprom.i.i
-  %tmp1 = load i8* %arrayidx.i.i, align 1
+  %arrayidx.i.i = getelementptr inbounds [0 x i8], [0 x i8]* %data.i.i, i64 0, i64 %idxprom.i.i
+  %tmp1 = load i8, i8* %arrayidx.i.i, align 1
   %conv2.i.i = zext i8 %tmp1 to i32
   %and.i.i = and i32 %conv2.i.i, 15
   store i32 %and.i.i, i32* @a, align 4
@@ -401,8 +399,8 @@ fn1.exit.i:                                       ; preds = %while.body.i.i
   %conv.i = zext i16 %inc.i.i.lcssa to i32
   %sub.i = add nsw i32 %conv.i, -1
   %idxprom.i = sext i32 %sub.i to i64
-  %arrayidx.i = getelementptr inbounds [0 x i8]* %data.i.i, i64 0, i64 %idxprom.i
-  %tmp2 = load i8* %arrayidx.i, align 1
+  %arrayidx.i = getelementptr inbounds [0 x i8], [0 x i8]* %data.i.i, i64 0, i64 %idxprom.i
+  %tmp2 = load i8, i8* %arrayidx.i, align 1
   %conv2.i = sext i8 %tmp2 to i16
   store i16 %conv2.i, i16* @b, align 2
   %sub4.i = sub nsw i32 0, %conv.i
@@ -411,8 +409,8 @@ fn1.exit.i:                                       ; preds = %while.body.i.i
   br i1 %cmp.i, label %if.then.i, label %fn2.exit
 
 if.then.i:                                        ; preds = %fn1.exit.i
-  %end.i = getelementptr inbounds %struct.dns_packet* %P, i64 0, i32 1
-  %tmp3 = load i32* %end.i, align 4
+  %end.i = getelementptr inbounds %struct.dns_packet, %struct.dns_packet* %P, i64 0, i32 1
+  %tmp3 = load i32, i32* %end.i, align 4
   %sub7.i = add i32 %tmp3, 65535
   %conv8.i = trunc i32 %sub7.i to i16
   br label %fn2.exit
@@ -433,7 +431,7 @@ define i8 @noPromotionFlag(i32 %arg1, i32 %arg2) {
   %add = add nsw i32 %arg1, %arg2 
   %zextadd = zext i32 %add to i64
   %base = inttoptr i64 %zextadd to i8*
-  %res = load i8* %base
+  %res = load i8, i8* %base
   ret i8 %res
 }
 
@@ -448,7 +446,7 @@ define i8 @twoArgsPromotionZExt(i32 %arg1, i32 %arg2) {
   %add = add nuw i32 %arg1, %arg2 
   %zextadd = zext i32 %add to i64
   %base = inttoptr i64 %zextadd to i8*
-  %res = load i8* %base
+  %res = load i8, i8* %base
   ret i8 %res
 }
 
@@ -456,13 +454,13 @@ define i8 @twoArgsPromotionZExt(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: @oneArgPromotionNegativeCstZExt
 ; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 %arg1 to i64
 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], 255
-; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
+; CHECK: getelementptr inbounds i8, i8* %base, i64 [[PROMOTED]]
 ; CHECK: ret
 define i8 @oneArgPromotionNegativeCstZExt(i8 %arg1, i8* %base) {
   %add = add nuw i8 %arg1, -1 
   %zextadd = zext i8 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %zextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %zextadd
+  %res = load i8, i8* %arrayidx
   ret i8 %res
 }
 
@@ -470,14 +468,14 @@ define i8 @oneArgPromotionNegativeCstZExt(i8 %arg1, i8* %base) {
 ; CHECK-LABEL: @oneArgPromotionZExtZExt
 ; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 %arg1 to i64
 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], 1
-; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
+; CHECK: getelementptr inbounds i8, i8* %base, i64 [[PROMOTED]]
 ; CHECK: ret
 define i8 @oneArgPromotionZExtZExt(i8 %arg1, i8* %base) {
   %zext = zext i8 %arg1 to i32
   %add = add nuw i32 %zext, 1 
   %zextadd = zext i32 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %zextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %zextadd
+  %res = load i8, i8* %arrayidx
   ret i8 %res
 }
 
@@ -488,15 +486,15 @@ define i8 @oneArgPromotionZExtZExt(i8 %arg1, i8* %base) {
 ; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 [[ARG1SEXT]] to i8
 ; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[ARG1TRUNC]] to i64
 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], 1
-; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
+; CHECK: getelementptr inbounds i8, i8* %base, i64 [[PROMOTED]]
 ; CHECK: ret
 define i8 @oneArgPromotionBlockTruncZExt(i1 %arg1, i8* %base) {
   %sextarg1 = sext i1 %arg1 to i32
   %trunc = trunc i32 %sextarg1 to i8
   %add = add nuw i8 %trunc, 1 
   %zextadd = zext i8 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %zextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %zextadd
+  %res = load i8, i8* %arrayidx
   ret i8 %res
 }
 
@@ -505,15 +503,15 @@ define i8 @oneArgPromotionBlockTruncZExt(i1 %arg1, i8* %base) {
 ; CHECK-LABEL: @oneArgPromotionPassTruncZExt
 ; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i1 %arg1 to i64
 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], 1
-; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
+; CHECK: getelementptr inbounds i8, i8* %base, i64 [[PROMOTED]]
 ; CHECK: ret
 define i8 @oneArgPromotionPassTruncZExt(i1 %arg1, i8* %base) {
   %sextarg1 = zext i1 %arg1 to i32
   %trunc = trunc i32 %sextarg1 to i8
   %add = add nuw i8 %trunc, 1 
   %zextadd = zext i8 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %zextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %zextadd
+  %res = load i8, i8* %arrayidx
   ret i8 %res
 }
 
@@ -522,13 +520,13 @@ define i8 @oneArgPromotionPassTruncZExt(i1 %arg1, i8* %base) {
 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i1 %arg1 to i8
 ; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[ARG1SEXT]] to i64
 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], 1
-; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
+; CHECK: getelementptr inbounds i8, i8* %base, i64 [[PROMOTED]]
 ; CHECK: ret
 define i8 @oneArgPromotionBlockSExtZExt(i1 %arg1, i8* %base) {
   %sextarg1 = sext i1 %arg1 to i8
   %add = add nuw i8 %sextarg1, 1 
   %zextadd = zext i8 %add to i64
-  %arrayidx = getelementptr inbounds i8* %base, i64 %zextadd
-  %res = load i8* %arrayidx
+  %arrayidx = getelementptr inbounds i8, i8* %base, i64 %zextadd
+  %res = load i8, i8* %arrayidx
   ret i8 %res
 }
diff --git a/test/CodeGen/X86/codegen-prepare-cast.ll b/test/CodeGen/X86/codegen-prepare-cast.ll
index 59c513385f76..1ab8017e8858 100644
--- a/test/CodeGen/X86/codegen-prepare-cast.ll
+++ b/test/CodeGen/X86/codegen-prepare-cast.ll
@@ -10,16 +10,16 @@ target triple = "x86_64-unknown-linux-gnu"
 @.str = external constant [7 x i8]              ; <[7 x i8]*> [#uses=1]
 
 ; CHECK-LABEL: @_Dmain
-; CHECK: load i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0)
+; CHECK: load i8, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0)
 ; CHECK ret
 define fastcc i32 @_Dmain(%"char[][]" %unnamed) {
 entry:
-        %tmp = getelementptr [7 x i8]* @.str, i32 0, i32 0              ; <i8*> [#uses=1]
+        %tmp = getelementptr [7 x i8], [7 x i8]* @.str, i32 0, i32 0              ; <i8*> [#uses=1]
         br i1 undef, label %foreachbody, label %foreachend
 
 foreachbody:            ; preds = %entry
-        %tmp4 = getelementptr i8* %tmp, i32 undef               ; <i8*> [#uses=1]
-        %tmp5 = load i8* %tmp4          ; <i8> [#uses=0]
+        %tmp4 = getelementptr i8, i8* %tmp, i32 undef               ; <i8*> [#uses=1]
+        %tmp5 = load i8, i8* %tmp4          ; <i8> [#uses=0]
         unreachable
 
 foreachend:             ; preds = %entry
diff --git a/test/CodeGen/X86/codegen-prepare-crash.ll b/test/CodeGen/X86/codegen-prepare-crash.ll
index c3288170cc4f..01bcad96d93f 100644
--- a/test/CodeGen/X86/codegen-prepare-crash.ll
+++ b/test/CodeGen/X86/codegen-prepare-crash.ll
@@ -8,7 +8,7 @@ define void @f(i32 %u) {
   br label %P.Proc8.exit
 
 P.Proc8.exit:
-  %valueindex35.i = getelementptr [10 x i32]* @g, i32 0, i32 %1
+  %valueindex35.i = getelementptr [10 x i32], [10 x i32]* @g, i32 0, i32 %1
   store i32 %u, i32* %valueindex35.i
   ret void
 }
diff --git a/test/CodeGen/X86/codegen-prepare-extload.ll b/test/CodeGen/X86/codegen-prepare-extload.ll
index 9b27c33a80f9..65502b312b04 100644
--- a/test/CodeGen/X86/codegen-prepare-extload.ll
+++ b/test/CodeGen/X86/codegen-prepare-extload.ll
@@ -12,13 +12,13 @@
 ; CHECK: movsbl ({{%rdi|%rcx}}), %eax
 ;
 ; OPTALL-LABEL: @foo
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
 ; OPTALL-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
 ; OPTALL: store i32 [[ZEXT]], i32* %q
 ; OPTALL: ret
 define void @foo(i8* %p, i32* %q) {
 entry:
-  %t = load i8* %p
+  %t = load i8, i8* %p
   %a = icmp slt i8 %t, 20
   br i1 %a, label %true, label %false
 true:
@@ -32,7 +32,7 @@ false:
 ; Check that we manage to form a zextload is an operation with only one
 ; argument to explicitly extend is in the the way.
 ; OPTALL-LABEL: @promoteOneArg
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
 ; OPT-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT]], 2
 ; Make sure the operation is not promoted when the promotion pass is disabled.
@@ -42,7 +42,7 @@ false:
 ; OPTALL: ret
 define void @promoteOneArg(i8* %p, i32* %q) {
 entry:
-  %t = load i8* %p
+  %t = load i8, i8* %p
   %add = add nuw i8 %t, 2
   %a = icmp slt i8 %t, 20
   br i1 %a, label %true, label %false
@@ -58,7 +58,7 @@ false:
 ; argument to explicitly extend is in the the way.
 ; Version with sext.
 ; OPTALL-LABEL: @promoteOneArgSExt
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
 ; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2
 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], 2
@@ -67,7 +67,7 @@ false:
 ; OPTALL: ret
 define void @promoteOneArgSExt(i8* %p, i32* %q) {
 entry:
-  %t = load i8* %p
+  %t = load i8, i8* %p
   %add = add nsw i8 %t, 2
   %a = icmp slt i8 %t, 20
   br i1 %a, label %true, label %false
@@ -90,7 +90,7 @@ false:
 ; transformation, the regular heuristic does not apply the optimization. 
 ; 
 ; OPTALL-LABEL: @promoteTwoArgZext
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
 ;
 ; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
 ; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32
@@ -106,7 +106,7 @@ false:
 ; OPTALL: ret
 define void @promoteTwoArgZext(i8* %p, i32* %q, i8 %b) {
 entry:
-  %t = load i8* %p
+  %t = load i8, i8* %p
   %add = add nuw i8 %t, %b
   %a = icmp slt i8 %t, 20
   br i1 %a, label %true, label %false
@@ -122,7 +122,7 @@ false:
 ; arguments to explicitly extend is in the the way.
 ; Version with sext.
 ; OPTALL-LABEL: @promoteTwoArgSExt
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
 ;
 ; STRESS-NEXT: [[SEXTLD:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
 ; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i8 %b to i32
@@ -137,7 +137,7 @@ false:
 ; OPTALL: ret
 define void @promoteTwoArgSExt(i8* %p, i32* %q, i8 %b) {
 entry:
-  %t = load i8* %p
+  %t = load i8, i8* %p
   %add = add nsw i8 %t, %b
   %a = icmp slt i8 %t, 20
   br i1 %a, label %true, label %false
@@ -152,7 +152,7 @@ false:
 ; Check that we do not a zextload if we need to introduce more than
 ; one additional extension.
 ; OPTALL-LABEL: @promoteThreeArgZext
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
 ;
 ; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
 ; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32
@@ -172,7 +172,7 @@ false:
 ; OPTALL: ret
 define void @promoteThreeArgZext(i8* %p, i32* %q, i8 %b, i8 %c) {
 entry:
-  %t = load i8* %p
+  %t = load i8, i8* %p
   %tmp = add nuw i8 %t, %b
   %add = add nuw i8 %tmp, %c
   %a = icmp slt i8 %t, 20
@@ -188,7 +188,7 @@ false:
 ; Check that we manage to form a zextload after promoting and merging
 ; two extensions.
 ; OPTALL-LABEL: @promoteMergeExtArgZExt
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
 ;
 ; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
 ; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i16 %b to i32
@@ -206,7 +206,7 @@ false:
 ; OPTALL: ret
 define void @promoteMergeExtArgZExt(i8* %p, i32* %q, i16 %b) {
 entry:
-  %t = load i8* %p
+  %t = load i8, i8* %p
   %ext = zext i8 %t to i16
   %add = add nuw i16 %ext, %b
   %a = icmp slt i8 %t, 20
@@ -223,7 +223,7 @@ false:
 ; two extensions.
 ; Version with sext.
 ; OPTALL-LABEL: @promoteMergeExtArgSExt
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
 ;
 ; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
 ; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = sext i16 %b to i32
@@ -240,7 +240,7 @@ false:
 ; OPTALL: ret
 define void @promoteMergeExtArgSExt(i8* %p, i32* %q, i16 %b) {
 entry:
-  %t = load i8* %p
+  %t = load i8, i8* %p
   %ext = zext i8 %t to i16
   %add = add nsw i16 %ext, %b
   %a = icmp slt i8 %t, 20
@@ -284,11 +284,11 @@ false:
 ; 3 identical zext of %ld. The extensions will be CSE'ed by SDag.
 ;
 ; OPTALL-LABEL: @severalPromotions
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %addr1
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %addr1
 ; OPT-NEXT: [[ZEXTLD1_1:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
 ; OPT-NEXT: [[ZEXTLD1_2:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
 ; OPT-NEXT: [[ZEXTLD1_3:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
-; OPT-NEXT: [[LD2:%[a-zA-Z_0-9-]+]] = load i32* %addr2
+; OPT-NEXT: [[LD2:%[a-zA-Z_0-9-]+]] = load i32, i32* %addr2
 ; OPT-NEXT: [[SEXTLD2:%[a-zA-Z_0-9-]+]] = sext i32 [[LD2]] to i64
 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTLD2]], [[ZEXTLD1_1]]
 ; We do not combine this one: see 2.b.
@@ -308,9 +308,9 @@ false:
 ; OPTALL: call void @dummy(i64 [[RES]], i64 [[RESZA]], i64 [[RESB]])
 ; OPTALL: ret
 define void @severalPromotions(i8* %addr1, i32* %addr2, i8 %a, i32 %b) {
-  %ld = load i8* %addr1
+  %ld = load i8, i8* %addr1
   %zextld = zext i8 %ld to i32
-  %ld2 = load i32* %addr2
+  %ld2 = load i32, i32* %addr2
   %add = add nsw i32 %ld2, %zextld
   %sextadd = sext i32 %add to i64
   %zexta = zext i8 %a to i32
@@ -345,19 +345,50 @@ entry:
 ; to an instruction.
 ; This used to cause a crash.
 ; OPTALL-LABEL: @promotionOfArgEndsUpInValue
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i16* %addr
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i16, i16* %addr
 
 ; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i16 [[LD]] to i32
-; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw nsw i32 [[SEXT]], zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32]* @c, i64 0, i64 1), i32* @a) to i32)
+; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw nsw i32 [[SEXT]], zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @c, i64 0, i64 1), i32* @a) to i32)
 ;
-; DISABLE-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw nsw i16 [[LD]], zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32]* @c, i64 0, i64 1), i32* @a) to i16)
+; DISABLE-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw nsw i16 [[LD]], zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @c, i64 0, i64 1), i32* @a) to i16)
 ; DISABLE-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32
 ;
 ; OPTALL-NEXT: ret i32 [[RES]]
 define i32 @promotionOfArgEndsUpInValue(i16* %addr) {
 entry:
-  %val = load i16* %addr
-  %add = add nuw nsw i16 %val, zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32]* @c, i64 0, i64 1), i32* @a) to i16)
+  %val = load i16, i16* %addr
+  %add = add nuw nsw i16 %val, zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @c, i64 0, i64 1), i32* @a) to i16)
   %conv3 = sext i16 %add to i32
   ret i32 %conv3
 }
+
+; Check that we see that one zext can be derived from the other for free.
+; OPTALL-LABEL: @promoteTwoArgZextWithSourceExtendedTwice
+; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
+
+; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
+; OPT-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; OPT-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
+; OPT-NEXT: [[RES64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], 12
+; OPT-NEXT: store i32 [[RES32]], i32* %addr
+; OPT-NEXT: store i64 [[RES64]], i64* %q
+;
+; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
+; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
+; DISABLE-NEXT: [[RES2_32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], 12
+; DISABLE-NEXT: store i32 [[RES32]], i32* %addr
+; DISABLE-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i32 [[RES2_32]] to i64
+; DISABLE-NEXT: store i64 [[ZEXT64]], i64* %q
+;
+; OPTALL-NEXT: ret void
+define void @promoteTwoArgZextWithSourceExtendedTwice(i8* %p, i64* %q, i32 %b, i32* %addr) {
+entry:
+  %t = load i8, i8* %p
+  %zextt = zext i8 %t to i32
+  %add = add nuw i32 %zextt, %b
+  %add2 = add nuw i32 %zextt, 12
+  store i32 %add, i32 *%addr
+  %s = zext i32 %add2 to i64
+  store i64 %s, i64* %q
+  ret void
+}
diff --git a/test/CodeGen/X86/codegen-prepare.ll b/test/CodeGen/X86/codegen-prepare.ll
index 4ff0f1c0ba24..e58bc22ef142 100644
--- a/test/CodeGen/X86/codegen-prepare.ll
+++ b/test/CodeGen/X86/codegen-prepare.ll
@@ -19,16 +19,16 @@
 define linkonce_odr void @foo(%class.A* nocapture %this, i32 %BoolValue) nounwind uwtable {
 entry:
   %cmp = icmp eq i32 %BoolValue, 0
-  %address1 = getelementptr inbounds %class.A* %this, i64 0, i32 0, i32 3
-  %address2 = getelementptr inbounds %class.A* %this, i64 0, i32 0, i32 1
+  %address1 = getelementptr inbounds %class.A, %class.A* %this, i64 0, i32 0, i32 3
+  %address2 = getelementptr inbounds %class.A, %class.A* %this, i64 0, i32 0, i32 1
   br i1 %cmp, label %if.else, label %if.then
 
 if.then:                                         ; preds = %entry
-  %0 = getelementptr inbounds %class.D* %address2, i64 0, i32 0, i64 0, i32 0
-  %1 = load float* %0, align 4 
-  %2 = getelementptr inbounds float* %0, i64 3
-  %3 = load float* %2, align 4 
-  %4 = getelementptr inbounds %class.D* %address1, i64 0, i32 0, i64 0, i32 0
+  %0 = getelementptr inbounds %class.D, %class.D* %address2, i64 0, i32 0, i64 0, i32 0
+  %1 = load float, float* %0, align 4 
+  %2 = getelementptr inbounds float, float* %0, i64 3
+  %3 = load float, float* %2, align 4 
+  %4 = getelementptr inbounds %class.D, %class.D* %address1, i64 0, i32 0, i64 0, i32 0
   store float %1, float* %4, align 4
   br label %if.end
 
diff --git a/test/CodeGen/X86/codemodel.ll b/test/CodeGen/X86/codemodel.ll
index 3aebc13f8740..edea63260270 100644
--- a/test/CodeGen/X86/codemodel.ll
+++ b/test/CodeGen/X86/codemodel.ll
@@ -11,7 +11,7 @@ entry:
 ; CHECK-SMALL:   movl data(%rip), %eax
 ; CHECK-KERNEL-LABEL: foo:
 ; CHECK-KERNEL:  movl data, %eax
-	%0 = load i32* getelementptr ([0 x i32]* @data, i64 0, i64 0), align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0), align 4		; <i32> [#uses=1]
 	ret i32 %0
 }
 
@@ -21,7 +21,7 @@ entry:
 ; CHECK-SMALL:   movl data+40(%rip), %eax
 ; CHECK-KERNEL-LABEL: foo2:
 ; CHECK-KERNEL:  movl data+40, %eax
-	%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 10), align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @data, i32 0, i64 10), align 4		; <i32> [#uses=1]
 	ret i32 %0
 }
 
@@ -31,7 +31,7 @@ entry:
 ; CHECK-SMALL:   movl data-40(%rip), %eax
 ; CHECK-KERNEL-LABEL: foo3:
 ; CHECK-KERNEL:  movq $-40, %rax
-	%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 -10), align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @data, i32 0, i64 -10), align 4		; <i32> [#uses=1]
 	ret i32 %0
 }
 
@@ -43,7 +43,7 @@ entry:
 ; CHECK-SMALL:   movl data(%rax), %eax
 ; CHECK-KERNEL-LABEL: foo4:
 ; CHECK-KERNEL:  movl data+16777216, %eax
-	%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 4194304), align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @data, i32 0, i64 4194304), align 4		; <i32> [#uses=1]
 	ret i32 %0
 }
 
@@ -53,7 +53,7 @@ entry:
 ; CHECK-SMALL:   movl data+16777212(%rip), %eax
 ; CHECK-KERNEL-LABEL: foo1:
 ; CHECK-KERNEL:  movl data+16777212, %eax
-        %0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 4194303), align 4            ; <i32> [#uses=1]
+        %0 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @data, i32 0, i64 4194303), align 4            ; <i32> [#uses=1]
         ret i32 %0
 }
 define i32 @foo5() nounwind readonly {
@@ -62,6 +62,6 @@ entry:
 ; CHECK-SMALL:   movl data-16777216(%rip), %eax
 ; CHECK-KERNEL-LABEL: foo5:
 ; CHECK-KERNEL:  movq $-16777216, %rax
-	%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 -4194304), align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @data, i32 0, i64 -4194304), align 4		; <i32> [#uses=1]
 	ret i32 %0
 }
diff --git a/test/CodeGen/X86/coff-comdat.ll b/test/CodeGen/X86/coff-comdat.ll
index 44e1cb236e91..18f418959ec9 100644
--- a/test/CodeGen/X86/coff-comdat.ll
+++ b/test/CodeGen/X86/coff-comdat.ll
@@ -53,7 +53,7 @@ define x86_fastcallcc void @f8() comdat($f8) {
 $vftable = comdat largest
 
 @some_name = private unnamed_addr constant [2 x i8*] zeroinitializer, comdat($vftable)
-@vftable = alias getelementptr([2 x i8*]* @some_name, i32 0, i32 1)
+@vftable = alias getelementptr([2 x i8*], [2 x i8*]* @some_name, i32 0, i32 1)
 
 ; CHECK: .section        .text,"xr",discard,_f1
 ; CHECK: .globl  _f1
diff --git a/test/CodeGen/X86/combine-and.ll b/test/CodeGen/X86/combine-and.ll
index dace806b4bb9..bb46ac539171 100644
--- a/test/CodeGen/X86/combine-and.ll
+++ b/test/CodeGen/X86/combine-and.ll
@@ -6,159 +6,173 @@
 
 
 define <4 x i32> @test1(<4 x i32> %A) {
+; CHECK-LABEL: test1:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 0, i32 0>
   ret <4 x i32> %1
 }
-; CHECK-LABEL: test1
-; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test2(<4 x i32> %A) {
+; CHECK-LABEL: test2:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 0>
   ret <4 x i32> %1
 }
-; CHECK-LABEL: test2
-; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test3(<4 x i32> %A) {
+; CHECK-LABEL: test3:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 0, i32 0, i32 -1, i32 0>
   ret <4 x i32> %1
 }
-; CHECK-LABEL: test3
-; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7]
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test4(<4 x i32> %A) {
+; CHECK-LABEL: test4:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1>
   ret <4 x i32> %1
 }
-; CHECK-LABEL: test4
-; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test5(<4 x i32> %A) {
+; CHECK-LABEL: test5:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 0>
   ret <4 x i32> %1
 }
-; CHECK-LABEL: test5
-; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test6(<4 x i32> %A) {
+; CHECK-LABEL: test6:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 -1>
   ret <4 x i32> %1
 }
-; CHECK-LABEL: test6
-; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test7(<4 x i32> %A) {
+; CHECK-LABEL: test7:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 0, i32 0, i32 -1, i32 -1>
   ret <4 x i32> %1
 }
-; CHECK-LABEL: test7
-; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test8(<4 x i32> %A) {
+; CHECK-LABEL: test8:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5],xmm0[6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 0, i32 -1>
   ret <4 x i32> %1
 }
-; CHECK-LABEL: test8
-; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5],xmm0[6,7]
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test9(<4 x i32> %A) {
+; CHECK-LABEL: test9:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 0, i32 0>
   ret <4 x i32> %1
 }
-; CHECK-LABEL: test9
-; CHECK: movq %xmm0, %xmm0
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test10(<4 x i32> %A) {
+; CHECK-LABEL: test10:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 -1, i32 0>
   ret <4 x i32> %1
 }
-; CHECK-LABEL: test10
-; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test11(<4 x i32> %A) {
+; CHECK-LABEL: test11:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 -1, i32 -1>
   ret <4 x i32> %1
 }
-; CHECK-LABEL: test11
-; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test12(<4 x i32> %A) {
+; CHECK-LABEL: test12:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 0>
   ret <4 x i32> %1
 }
-; CHECK-LABEL: test12
-; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test13(<4 x i32> %A) {
+; CHECK-LABEL: test13:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 0, i32 -1>
   ret <4 x i32> %1
 }
-; CHECK-LABEL: test13
-; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test14(<4 x i32> %A) {
+; CHECK-LABEL: test14:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 -1>
   ret <4 x i32> %1
 }
-; CHECK-LABEL: test14
-; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test15(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test15:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 -1>
   %2 = and <4 x i32> %B, <i32 0, i32 -1, i32 0, i32 0>
   %3 = or <4 x i32> %1, %2
   ret <4 x i32> %3
 }
-; CHECK-LABEL: test15
-; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test16(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test16:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 0>
   %2 = and <4 x i32> %B, <i32 0, i32 -1, i32 0, i32 -1>
   %3 = or <4 x i32> %1, %2
   ret <4 x i32> %3
 }
-; CHECK-LABEL: test16
-; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
-; CHECK-NEXT: retq
-
 
 define <4 x i32> @test17(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test17:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
+; CHECK-NEXT:    retq
   %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 -1>
   %2 = and <4 x i32> %B, <i32 -1, i32 0, i32 -1, i32 0>
   %3 = or <4 x i32> %1, %2
   ret <4 x i32> %3
 }
-; CHECK-LABEL: test17
-; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
-; CHECK-NEXT: retq
diff --git a/test/CodeGen/X86/combine-or.ll b/test/CodeGen/X86/combine-or.ll
index 280fcbc7a3a7..970f1762c1b8 100644
--- a/test/CodeGen/X86/combine-or.ll
+++ b/test/CodeGen/X86/combine-or.ll
@@ -153,7 +153,8 @@ define <4 x i32> @test12(<4 x i32> %a, <4 x i32> %b) {
 define <4 x i32> @test13(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test13:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[2,3]
+; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
 ; CHECK-NEXT:    retq
   %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 1, i32 1, i32 4, i32 4>
   %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
@@ -177,8 +178,9 @@ define <2 x i64> @test14(<2 x i64> %a, <2 x i64> %b) {
 define <4 x i32> @test15(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test15:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,1],xmm0[2,1]
-; CHECK-NEXT:    movaps %xmm1, %xmm0
+; CHECK-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[0,1,2,1]
+; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[2,1,2,3]
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
 ; CHECK-NEXT:    retq
   %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 1>
   %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 2, i32 1, i32 4, i32 4>
@@ -206,12 +208,9 @@ define <2 x i64> @test16(<2 x i64> %a, <2 x i64> %b) {
 define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test17:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    xorps %xmm2, %xmm2
-; CHECK-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,0]
-; CHECK-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[0,2]
-; CHECK-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
-; CHECK-NEXT:    orps %xmm1, %xmm2
-; CHECK-NEXT:    movaps %xmm2, %xmm0
+; CHECK-NEXT:    psllq $32, %xmm0
+; CHECK-NEXT:    movq {{.*#+}} xmm1 = xmm1[0],zero
+; CHECK-NEXT:    por %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 2>
   %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
@@ -239,12 +238,12 @@ define <4 x i32> @test18(<4 x i32> %a, <4 x i32> %b) {
 define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test19:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    xorps %xmm2, %xmm2
-; CHECK-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[0,3]
-; CHECK-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
-; CHECK-NEXT:    insertps {{.*#+}} xmm1 = xmm1[0],zero,xmm1[2,2]
-; CHECK-NEXT:    orps %xmm1, %xmm2
-; CHECK-NEXT:    movaps %xmm2, %xmm0
+; CHECK-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[0,0,2,3]
+; CHECK-NEXT:    pxor %xmm3, %xmm3
+; CHECK-NEXT:    pblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
+; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[0,1,2,2]
+; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,3],xmm0[4,5,6,7]
+; CHECK-NEXT:    por %xmm2, %xmm0
 ; CHECK-NEXT:    retq
   %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 3>
   %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 2, i32 2>
@@ -256,8 +255,8 @@ define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
 define <2 x i64> @test20(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test20:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    orps %xmm1, %xmm0
-; CHECK-NEXT:    movq %xmm0, %xmm0
+; CHECK-NEXT:    por %xmm1, %xmm0
+; CHECK-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
 ; CHECK-NEXT:    retq
   %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
   %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
@@ -278,6 +277,70 @@ define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
   ret <2 x i64> %or
 }
 
+
+; Verify that the dag-combiner keeps the correct domain for float/double vectors
+; bitcast to use the mask-or blend combine.
+
+define <2 x double> @test22(<2 x double> %a0, <2 x double> %a1) {
+; CHECK-LABEL: test22:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
+; CHECK-NEXT:    retq
+  %bc1 = bitcast <2 x double> %a0 to <2 x i64>
+  %bc2 = bitcast <2 x double> %a1 to <2 x i64>
+  %and1 = and <2 x i64> %bc1, <i64 0, i64 -1>
+  %and2 = and <2 x i64> %bc2, <i64 -1, i64 0>
+  %or = or <2 x i64> %and1, %and2
+  %bc3 = bitcast <2 x i64> %or to <2 x double>
+  ret <2 x double> %bc3
+}
+
+
+define <4 x float> @test23(<4 x float> %a0, <4 x float> %a1) {
+; CHECK-LABEL: test23:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3]
+; CHECK-NEXT:    retq
+  %bc1 = bitcast <4 x float> %a0 to <4 x i32>
+  %bc2 = bitcast <4 x float> %a1 to <4 x i32>
+  %and1 = and <4 x i32> %bc1, <i32 0, i32 -1, i32 -1, i32 0>
+  %and2 = and <4 x i32> %bc2, <i32 -1, i32 0, i32 0, i32 -1>
+  %or = or <4 x i32> %and1, %and2
+  %bc3 = bitcast <4 x i32> %or to <4 x float>
+  ret <4 x float> %bc3
+}
+
+
+define <4 x float> @test24(<4 x float> %a0, <4 x float> %a1) {
+; CHECK-LABEL: test24:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
+; CHECK-NEXT:    retq
+  %bc1 = bitcast <4 x float> %a0 to <2 x i64>
+  %bc2 = bitcast <4 x float> %a1 to <2 x i64>
+  %and1 = and <2 x i64> %bc1, <i64 0, i64 -1>
+  %and2 = and <2 x i64> %bc2, <i64 -1, i64 0>
+  %or = or <2 x i64> %and1, %and2
+  %bc3 = bitcast <2 x i64> %or to <4 x float>
+  ret <4 x float> %bc3
+}
+
+
+define <4 x float> @test25(<4 x float> %a0) {
+; CHECK-LABEL: test25:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    blendps {{.*#+}} xmm0 = mem[0],xmm0[1,2],mem[3]
+; CHECK-NEXT:    retq
+  %bc1 = bitcast <4 x float> %a0 to <4 x i32>
+  %bc2 = bitcast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0> to <4 x i32>
+  %and1 = and <4 x i32> %bc1, <i32 0, i32 -1, i32 -1, i32 0>
+  %and2 = and <4 x i32> %bc2, <i32 -1, i32 0, i32 0, i32 -1>
+  %or = or <4 x i32> %and1, %and2
+  %bc3 = bitcast <4 x i32> %or to <4 x float>
+  ret <4 x float> %bc3
+}
+
+
 ; Verify that the DAGCombiner doesn't crash in the attempt to check if a shuffle
 ; with illegal type has a legal mask. Method 'isShuffleMaskLegal' only knows how to
 ; handle legal vector value types.
diff --git a/test/CodeGen/X86/combiner-aa-0.ll b/test/CodeGen/X86/combiner-aa-0.ll
index a61ef7acd13c..403059d90ab1 100644
--- a/test/CodeGen/X86/combiner-aa-0.ll
+++ b/test/CodeGen/X86/combiner-aa-0.ll
@@ -5,14 +5,14 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 @g_flipV_hashkey = external global %struct.Hash_Key, align 16		; <%struct.Hash_Key*> [#uses=1]
 
 define void @foo() nounwind {
-	%t0 = load i32* undef, align 16		; <i32> [#uses=1]
-	%t1 = load i32* null, align 4		; <i32> [#uses=1]
+	%t0 = load i32, i32* undef, align 16		; <i32> [#uses=1]
+	%t1 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	%t2 = srem i32 %t0, 32		; <i32> [#uses=1]
 	%t3 = shl i32 1, %t2		; <i32> [#uses=1]
 	%t4 = xor i32 %t3, %t1		; <i32> [#uses=1]
 	store i32 %t4, i32* null, align 4
-	%t5 = getelementptr %struct.Hash_Key* @g_flipV_hashkey, i64 0, i32 0, i64 0		; <i32*> [#uses=2]
-	%t6 = load i32* %t5, align 4		; <i32> [#uses=1]
+	%t5 = getelementptr %struct.Hash_Key, %struct.Hash_Key* @g_flipV_hashkey, i64 0, i32 0, i64 0		; <i32*> [#uses=2]
+	%t6 = load i32, i32* %t5, align 4		; <i32> [#uses=1]
 	%t7 = shl i32 1, undef		; <i32> [#uses=1]
 	%t8 = xor i32 %t7, %t6		; <i32> [#uses=1]
 	store i32 %t8, i32* %t5, align 4
diff --git a/test/CodeGen/X86/combiner-aa-1.ll b/test/CodeGen/X86/combiner-aa-1.ll
index 58a7129b6005..cc3e5ca12602 100644
--- a/test/CodeGen/X86/combiner-aa-1.ll
+++ b/test/CodeGen/X86/combiner-aa-1.ll
@@ -13,9 +13,9 @@ target triple = "i386-pc-linux-gnu"
 define i32 @._ZN8lam_node18resolve_name_clashEP8arg_nodeP9alst_node._ZNK8lam_nodeeqERK8exp_node._ZN11arglst_nodeD0Ev(%struct.lam_node* %this.this, %struct.arg_node* %outer_arg, %struct.alst_node* %env.cmp, %struct.arglst_node* %this, i32 %functionID) {
 comb_entry:
   %.SV59 = alloca %struct.node*                   ; <%struct.node**> [#uses=1]
-  %0 = load i32 (...)*** null, align 4            ; <i32 (...)**> [#uses=1]
-  %1 = getelementptr inbounds i32 (...)** %0, i32 3 ; <i32 (...)**> [#uses=1]
-  %2 = load i32 (...)** %1, align 4               ; <i32 (...)*> [#uses=1]
+  %0 = load i32 (...)**, i32 (...)*** null, align 4            ; <i32 (...)**> [#uses=1]
+  %1 = getelementptr inbounds i32 (...)*, i32 (...)** %0, i32 3 ; <i32 (...)**> [#uses=1]
+  %2 = load i32 (...)*, i32 (...)** %1, align 4               ; <i32 (...)*> [#uses=1]
   store %struct.node* undef, %struct.node** %.SV59
   %3 = bitcast i32 (...)* %2 to i32 (%struct.node*)* ; <i32 (%struct.node*)*> [#uses=1]
   %4 = tail call i32 %3(%struct.node* undef)      ; <i32> [#uses=0]
diff --git a/test/CodeGen/X86/commute-blend-avx2.ll b/test/CodeGen/X86/commute-blend-avx2.ll
index d06c6dad8dbf..bd497ba40767 100644
--- a/test/CodeGen/X86/commute-blend-avx2.ll
+++ b/test/CodeGen/X86/commute-blend-avx2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -O3 -mtriple=x86_64-unknown -mcpu=core-avx2 -mattr=avx2 < %s | FileCheck %s
 
 define <8 x i16> @commute_fold_vpblendw_128(<8 x i16> %a, <8 x i16>* %b) #0 {
-  %1 = load <8 x i16>* %b
+  %1 = load <8 x i16>, <8 x i16>* %b
   %2 = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %1, <8 x i16> %a, i8 17)
   ret <8 x i16> %2
 
@@ -12,7 +12,7 @@ define <8 x i16> @commute_fold_vpblendw_128(<8 x i16> %a, <8 x i16>* %b) #0 {
 declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i8) nounwind readnone
 
 define <16 x i16> @commute_fold_vpblendw_256(<16 x i16> %a, <16 x i16>* %b) #0 {
-  %1 = load <16 x i16>* %b
+  %1 = load <16 x i16>, <16 x i16>* %b
   %2 = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %1, <16 x i16> %a, i8 17)
   ret <16 x i16> %2
 
@@ -23,7 +23,7 @@ define <16 x i16> @commute_fold_vpblendw_256(<16 x i16> %a, <16 x i16>* %b) #0 {
 declare <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16>, <16 x i16>, i8) nounwind readnone
 
 define <4 x i32> @commute_fold_vpblendd_128(<4 x i32> %a, <4 x i32>* %b) #0 {
-  %1 = load <4 x i32>* %b
+  %1 = load <4 x i32>, <4 x i32>* %b
   %2 = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %1, <4 x i32> %a, i8 1)
   ret <4 x i32> %2
 
@@ -34,7 +34,7 @@ define <4 x i32> @commute_fold_vpblendd_128(<4 x i32> %a, <4 x i32>* %b) #0 {
 declare <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32>, <4 x i32>, i8) nounwind readnone
 
 define <8 x i32> @commute_fold_vpblendd_256(<8 x i32> %a, <8 x i32>* %b) #0 {
-  %1 = load <8 x i32>* %b
+  %1 = load <8 x i32>, <8 x i32>* %b
   %2 = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %1, <8 x i32> %a, i8 129)
   ret <8 x i32> %2
 
@@ -45,18 +45,18 @@ define <8 x i32> @commute_fold_vpblendd_256(<8 x i32> %a, <8 x i32>* %b) #0 {
 declare <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32>, <8 x i32>, i8) nounwind readnone
 
 define <4 x float> @commute_fold_vblendps_128(<4 x float> %a, <4 x float>* %b) #0 {
-  %1 = load <4 x float>* %b
-  %2 = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %1, <4 x float> %a, i8 3)
+  %1 = load <4 x float>, <4 x float>* %b
+  %2 = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %1, <4 x float> %a, i8 5)
   ret <4 x float> %2
 
   ;LABEL:      commute_fold_vblendps_128
-  ;CHECK:      vblendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3]
+  ;CHECK:      vblendps {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3]
   ;CHECK-NEXT: retq
 }
 declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i8) nounwind readnone
 
 define <8 x float> @commute_fold_vblendps_256(<8 x float> %a, <8 x float>* %b) #0 {
-  %1 = load <8 x float>* %b
+  %1 = load <8 x float>, <8 x float>* %b
   %2 = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %1, <8 x float> %a, i8 7)
   ret <8 x float> %2
 
@@ -67,7 +67,7 @@ define <8 x float> @commute_fold_vblendps_256(<8 x float> %a, <8 x float>* %b) #
 declare <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone
 
 define <2 x double> @commute_fold_vblendpd_128(<2 x double> %a, <2 x double>* %b) #0 {
-  %1 = load <2 x double>* %b
+  %1 = load <2 x double>, <2 x double>* %b
   %2 = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %1, <2 x double> %a, i8 1)
   ret <2 x double> %2
 
@@ -78,7 +78,7 @@ define <2 x double> @commute_fold_vblendpd_128(<2 x double> %a, <2 x double>* %b
 declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i8) nounwind readnone
 
 define <4 x double> @commute_fold_vblendpd_256(<4 x double> %a, <4 x double>* %b) #0 {
-  %1 = load <4 x double>* %b
+  %1 = load <4 x double>, <4 x double>* %b
   %2 = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %1, <4 x double> %a, i8 7)
   ret <4 x double> %2
 
diff --git a/test/CodeGen/X86/commute-blend-sse41.ll b/test/CodeGen/X86/commute-blend-sse41.ll
index 59fef8c3a29f..8cebcdb8eeae 100644
--- a/test/CodeGen/X86/commute-blend-sse41.ll
+++ b/test/CodeGen/X86/commute-blend-sse41.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -O3 -mtriple=x86_64-unknown -mcpu=corei7 < %s | FileCheck %s
 
 define <8 x i16> @commute_fold_pblendw(<8 x i16> %a, <8 x i16>* %b) #0 {
-  %1 = load <8 x i16>* %b
+  %1 = load <8 x i16>, <8 x i16>* %b
   %2 = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %1, <8 x i16> %a, i8 17)
   ret <8 x i16> %2
 
@@ -12,18 +12,18 @@ define <8 x i16> @commute_fold_pblendw(<8 x i16> %a, <8 x i16>* %b) #0 {
 declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i8) nounwind readnone
 
 define <4 x float> @commute_fold_blendps(<4 x float> %a, <4 x float>* %b) #0 {
-  %1 = load <4 x float>* %b
-  %2 = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %1, <4 x float> %a, i8 3)
+  %1 = load <4 x float>, <4 x float>* %b
+  %2 = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %1, <4 x float> %a, i8 5)
   ret <4 x float> %2
 
   ;LABEL:      commute_fold_blendps
-  ;CHECK:      blendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3]
+  ;CHECK:      blendps {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3]
   ;CHECK-NEXT: retq
 }
 declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i8) nounwind readnone
 
 define <2 x double> @commute_fold_blendpd(<2 x double> %a, <2 x double>* %b) #0 {
-  %1 = load <2 x double>* %b
+  %1 = load <2 x double>, <2 x double>* %b
   %2 = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %1, <2 x double> %a, i8 1)
   ret <2 x double> %2
 
diff --git a/test/CodeGen/X86/commute-clmul.ll b/test/CodeGen/X86/commute-clmul.ll
new file mode 100644
index 000000000000..d13911abc864
--- /dev/null
+++ b/test/CodeGen/X86/commute-clmul.ll
@@ -0,0 +1,60 @@
+; RUN: llc -O3 -mtriple=x86_64-unknown -mcpu=x86-64 -mattr=+sse2,+pclmul < %s | FileCheck %s --check-prefix=SSE
+; RUN: llc -O3 -mtriple=x86_64-unknown -mcpu=x86-64 -mattr=+avx2,+pclmul < %s | FileCheck %s --check-prefix=AVX
+
+declare <2 x i64> @llvm.x86.pclmulqdq(<2 x i64>, <2 x i64>, i8) nounwind readnone
+
+define <2 x i64> @commute_lq_lq(<2 x i64>* %a0, <2 x i64> %a1) #0 {
+  ;SSE-LABEL: commute_lq_lq
+  ;SSE:       pclmulqdq $0, (%rdi), %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_lq_lq
+  ;AVX:       vpclmulqdq $0, (%rdi), %xmm0, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <2 x i64>, <2 x i64>* %a0
+  %2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 0)
+  ret <2 x i64> %2
+}
+
+define <2 x i64> @commute_lq_hq(<2 x i64>* %a0, <2 x i64> %a1) #0 {
+  ;SSE-LABEL: commute_lq_hq
+  ;SSE:       pclmulqdq $1, (%rdi), %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_lq_hq
+  ;AVX:       vpclmulqdq $1, (%rdi), %xmm0, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <2 x i64>, <2 x i64>* %a0
+  %2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 16)
+  ret <2 x i64> %2
+}
+
+define <2 x i64> @commute_hq_lq(<2 x i64>* %a0, <2 x i64> %a1) #0 {
+  ;SSE-LABEL: commute_hq_lq
+  ;SSE:       pclmulqdq $16, (%rdi), %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_hq_lq
+  ;AVX:       vpclmulqdq $16, (%rdi), %xmm0, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <2 x i64>, <2 x i64>* %a0
+  %2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 1)
+  ret <2 x i64> %2
+}
+
+define <2 x i64> @commute_hq_hq(<2 x i64>* %a0, <2 x i64> %a1) #0 {
+  ;SSE-LABEL: commute_hq_hq
+  ;SSE:       pclmulqdq $17, (%rdi), %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_hq_hq
+  ;AVX:       vpclmulqdq $17, (%rdi), %xmm0, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <2 x i64>, <2 x i64>* %a0
+  %2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 17)
+  ret <2 x i64> %2
+}
diff --git a/test/CodeGen/X86/commute-fcmp.ll b/test/CodeGen/X86/commute-fcmp.ll
new file mode 100644
index 000000000000..6f43ebe1fcd7
--- /dev/null
+++ b/test/CodeGen/X86/commute-fcmp.ll
@@ -0,0 +1,340 @@
+; RUN: llc -O3 -mtriple=x86_64-unknown -mcpu=x86-64 -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE
+; RUN: llc -O3 -mtriple=x86_64-unknown -mcpu=x86-64 -mattr=+avx2 < %s | FileCheck %s --check-prefix=AVX
+
+;
+; Float Comparisons
+; Only equal/not-equal/ordered/unordered can be safely commuted
+;
+
+define <4 x i32> @commute_cmpps_eq(<4 x float>* %a0, <4 x float> %a1) #0 {
+  ;SSE-LABEL: commute_cmpps_eq
+  ;SSE:       cmpeqps (%rdi), %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_cmpps_eq
+  ;AVX:       vcmpeqps (%rdi), %xmm0, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <4 x float>, <4 x float>* %a0
+  %2 = fcmp oeq <4 x float> %1, %a1
+  %3 = sext <4 x i1> %2 to <4 x i32>
+  ret <4 x i32> %3
+}
+
+define <4 x i32> @commute_cmpps_ne(<4 x float>* %a0, <4 x float> %a1) #0 {
+  ;SSE-LABEL: commute_cmpps_ne
+  ;SSE:       cmpneqps (%rdi), %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_cmpps_ne
+  ;AVX:       vcmpneqps (%rdi), %xmm0, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <4 x float>, <4 x float>* %a0
+  %2 = fcmp une <4 x float> %1, %a1
+  %3 = sext <4 x i1> %2 to <4 x i32>
+  ret <4 x i32> %3
+}
+
+define <4 x i32> @commute_cmpps_ord(<4 x float>* %a0, <4 x float> %a1) #0 {
+  ;SSE-LABEL: commute_cmpps_ord
+  ;SSE:       cmpordps (%rdi), %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_cmpps_ord
+  ;AVX:       vcmpordps (%rdi), %xmm0, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <4 x float>, <4 x float>* %a0
+  %2 = fcmp ord <4 x float> %1, %a1
+  %3 = sext <4 x i1> %2 to <4 x i32>
+  ret <4 x i32> %3
+}
+
+define <4 x i32> @commute_cmpps_uno(<4 x float>* %a0, <4 x float> %a1) #0 {
+  ;SSE-LABEL: commute_cmpps_uno
+  ;SSE:       cmpunordps (%rdi), %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_cmpps_uno
+  ;AVX:       vcmpunordps (%rdi), %xmm0, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <4 x float>, <4 x float>* %a0
+  %2 = fcmp uno <4 x float> %1, %a1
+  %3 = sext <4 x i1> %2 to <4 x i32>
+  ret <4 x i32> %3
+}
+
+define <4 x i32> @commute_cmpps_lt(<4 x float>* %a0, <4 x float> %a1) #0 {
+  ;SSE-LABEL: commute_cmpps_lt
+  ;SSE:       movaps (%rdi), %xmm1
+  ;SSE-NEXT:  cmpltps %xmm0, %xmm1
+  ;SSE-NEXT:  movaps %xmm1, %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_cmpps_lt
+  ;AVX:       vmovaps (%rdi), %xmm1
+  ;AVX-NEXT:  vcmpltps %xmm0, %xmm1, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <4 x float>, <4 x float>* %a0
+  %2 = fcmp olt <4 x float> %1, %a1
+  %3 = sext <4 x i1> %2 to <4 x i32>
+  ret <4 x i32> %3
+}
+
+define <4 x i32> @commute_cmpps_le(<4 x float>* %a0, <4 x float> %a1) #0 {
+  ;SSE-LABEL: commute_cmpps_le
+  ;SSE:       movaps (%rdi), %xmm1
+  ;SSE-NEXT:  cmpleps %xmm0, %xmm1
+  ;SSE-NEXT:  movaps %xmm1, %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_cmpps_le
+  ;AVX:       vmovaps (%rdi), %xmm1
+  ;AVX-NEXT:  vcmpleps %xmm0, %xmm1, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <4 x float>, <4 x float>* %a0
+  %2 = fcmp ole <4 x float> %1, %a1
+  %3 = sext <4 x i1> %2 to <4 x i32>
+  ret <4 x i32> %3
+}
+
+define <8 x i32> @commute_cmpps_eq_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
+  ;AVX-LABEL: commute_cmpps_eq_ymm
+  ;AVX:       vcmpeqps (%rdi), %ymm0, %ymm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <8 x float>, <8 x float>* %a0
+  %2 = fcmp oeq <8 x float> %1, %a1
+  %3 = sext <8 x i1> %2 to <8 x i32>
+  ret <8 x i32> %3
+}
+
+define <8 x i32> @commute_cmpps_ne_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
+  ;AVX-LABEL: commute_cmpps_ne_ymm
+  ;AVX:       vcmpneqps (%rdi), %ymm0, %ymm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <8 x float>, <8 x float>* %a0
+  %2 = fcmp une <8 x float> %1, %a1
+  %3 = sext <8 x i1> %2 to <8 x i32>
+  ret <8 x i32> %3
+}
+
+define <8 x i32> @commute_cmpps_ord_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
+  ;AVX-LABEL: commute_cmpps_ord_ymm
+  ;AVX:       vcmpordps (%rdi), %ymm0, %ymm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <8 x float>, <8 x float>* %a0
+  %2 = fcmp ord <8 x float> %1, %a1
+  %3 = sext <8 x i1> %2 to <8 x i32>
+  ret <8 x i32> %3
+}
+
+define <8 x i32> @commute_cmpps_uno_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
+  ;AVX-LABEL: commute_cmpps_uno_ymm
+  ;AVX:       vcmpunordps (%rdi), %ymm0, %ymm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <8 x float>, <8 x float>* %a0
+  %2 = fcmp uno <8 x float> %1, %a1
+  %3 = sext <8 x i1> %2 to <8 x i32>
+  ret <8 x i32> %3
+}
+
+define <8 x i32> @commute_cmpps_lt_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
+  ;AVX-LABEL: commute_cmpps_lt_ymm
+  ;AVX:       vmovaps (%rdi), %ymm1
+  ;AVX-NEXT:  vcmpltps %ymm0, %ymm1, %ymm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <8 x float>, <8 x float>* %a0
+  %2 = fcmp olt <8 x float> %1, %a1
+  %3 = sext <8 x i1> %2 to <8 x i32>
+  ret <8 x i32> %3
+}
+
+define <8 x i32> @commute_cmpps_le_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
+  ;AVX-LABEL: commute_cmpps_le_ymm
+  ;AVX:       vmovaps (%rdi), %ymm1
+  ;AVX-NEXT:  vcmpleps %ymm0, %ymm1, %ymm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <8 x float>, <8 x float>* %a0
+  %2 = fcmp ole <8 x float> %1, %a1
+  %3 = sext <8 x i1> %2 to <8 x i32>
+  ret <8 x i32> %3
+}
+
+;
+; Double Comparisons
+; Only equal/not-equal/ordered/unordered can be safely commuted
+;
+
+define <2 x i64> @commute_cmppd_eq(<2 x double>* %a0, <2 x double> %a1) #0 {
+  ;SSE-LABEL: commute_cmppd_eq
+  ;SSE:       cmpeqpd (%rdi), %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_cmppd_eq
+  ;AVX:       vcmpeqpd (%rdi), %xmm0, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <2 x double>, <2 x double>* %a0
+  %2 = fcmp oeq <2 x double> %1, %a1
+  %3 = sext <2 x i1> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <2 x i64> @commute_cmppd_ne(<2 x double>* %a0, <2 x double> %a1) #0 {
+  ;SSE-LABEL: commute_cmppd_ne
+  ;SSE:       cmpneqpd (%rdi), %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_cmppd_ne
+  ;AVX:       vcmpneqpd (%rdi), %xmm0, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <2 x double>, <2 x double>* %a0
+  %2 = fcmp une <2 x double> %1, %a1
+  %3 = sext <2 x i1> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <2 x i64> @commute_cmppd_ord(<2 x double>* %a0, <2 x double> %a1) #0 {
+  ;SSE-LABEL: commute_cmppd_ord
+  ;SSE:       cmpordpd (%rdi), %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_cmppd_ord
+  ;AVX:       vcmpordpd (%rdi), %xmm0, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <2 x double>, <2 x double>* %a0
+  %2 = fcmp ord <2 x double> %1, %a1
+  %3 = sext <2 x i1> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <2 x i64> @commute_cmppd_uno(<2 x double>* %a0, <2 x double> %a1) #0 {
+  ;SSE-LABEL: commute_cmppd_uno
+  ;SSE:       cmpunordpd (%rdi), %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_cmppd_uno
+  ;AVX:       vcmpunordpd (%rdi), %xmm0, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <2 x double>, <2 x double>* %a0
+  %2 = fcmp uno <2 x double> %1, %a1
+  %3 = sext <2 x i1> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <2 x i64> @commute_cmppd_lt(<2 x double>* %a0, <2 x double> %a1) #0 {
+  ;SSE-LABEL: commute_cmppd_lt
+  ;SSE:       movapd (%rdi), %xmm1
+  ;SSE-NEXT:  cmpltpd %xmm0, %xmm1
+  ;SSE-NEXT:  movapd %xmm1, %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_cmppd_lt
+  ;AVX:       vmovapd (%rdi), %xmm1
+  ;AVX-NEXT:  vcmpltpd %xmm0, %xmm1, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <2 x double>, <2 x double>* %a0
+  %2 = fcmp olt <2 x double> %1, %a1
+  %3 = sext <2 x i1> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <2 x i64> @commute_cmppd_le(<2 x double>* %a0, <2 x double> %a1) #0 {
+  ;SSE-LABEL: commute_cmppd_le
+  ;SSE:       movapd (%rdi), %xmm1
+  ;SSE-NEXT:  cmplepd %xmm0, %xmm1
+  ;SSE-NEXT:  movapd %xmm1, %xmm0
+  ;SSE-NEXT:  retq
+
+  ;AVX-LABEL: commute_cmppd_le
+  ;AVX:       vmovapd (%rdi), %xmm1
+  ;AVX-NEXT:  vcmplepd %xmm0, %xmm1, %xmm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <2 x double>, <2 x double>* %a0
+  %2 = fcmp ole <2 x double> %1, %a1
+  %3 = sext <2 x i1> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <4 x i64> @commute_cmppd_eq_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
+  ;AVX-LABEL: commute_cmppd_eq
+  ;AVX:       vcmpeqpd (%rdi), %ymm0, %ymm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <4 x double>, <4 x double>* %a0
+  %2 = fcmp oeq <4 x double> %1, %a1
+  %3 = sext <4 x i1> %2 to <4 x i64>
+  ret <4 x i64> %3
+}
+
+define <4 x i64> @commute_cmppd_ne_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
+  ;AVX-LABEL: commute_cmppd_ne
+  ;AVX:       vcmpneqpd (%rdi), %ymm0, %ymm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <4 x double>, <4 x double>* %a0
+  %2 = fcmp une <4 x double> %1, %a1
+  %3 = sext <4 x i1> %2 to <4 x i64>
+  ret <4 x i64> %3
+}
+
+define <4 x i64> @commute_cmppd_ord_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
+  ;AVX-LABEL: commute_cmppd_ord
+  ;AVX:       vcmpordpd (%rdi), %ymm0, %ymm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <4 x double>, <4 x double>* %a0
+  %2 = fcmp ord <4 x double> %1, %a1
+  %3 = sext <4 x i1> %2 to <4 x i64>
+  ret <4 x i64> %3
+}
+
+define <4 x i64> @commute_cmppd_uno_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
+  ;AVX-LABEL: commute_cmppd_uno
+  ;AVX:       vcmpunordpd (%rdi), %ymm0, %ymm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <4 x double>, <4 x double>* %a0
+  %2 = fcmp uno <4 x double> %1, %a1
+  %3 = sext <4 x i1> %2 to <4 x i64>
+  ret <4 x i64> %3
+}
+
+define <4 x i64> @commute_cmppd_lt_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
+  ;AVX-LABEL: commute_cmppd_lt
+  ;AVX:       vmovapd (%rdi), %ymm1
+  ;AVX-NEXT:  vcmpltpd %ymm0, %ymm1, %ymm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <4 x double>, <4 x double>* %a0
+  %2 = fcmp olt <4 x double> %1, %a1
+  %3 = sext <4 x i1> %2 to <4 x i64>
+  ret <4 x i64> %3
+}
+
+define <4 x i64> @commute_cmppd_le_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
+  ;AVX-LABEL: commute_cmppd_le
+  ;AVX:       vmovapd (%rdi), %ymm1
+  ;AVX-NEXT:  vcmplepd %ymm0, %ymm1, %ymm0
+  ;AVX-NEXT:  retq
+
+  %1 = load <4 x double>, <4 x double>* %a0
+  %2 = fcmp ole <4 x double> %1, %a1
+  %3 = sext <4 x i1> %2 to <4 x i64>
+  ret <4 x i64> %3
+}
diff --git a/test/CodeGen/X86/commute-intrinsic.ll b/test/CodeGen/X86/commute-intrinsic.ll
index 7d5ca4766892..ff9049cf96da 100644
--- a/test/CodeGen/X86/commute-intrinsic.ll
+++ b/test/CodeGen/X86/commute-intrinsic.ll
@@ -6,7 +6,7 @@
 
 define <2 x i64> @madd(<2 x i64> %b) nounwind  {
 entry:
-	%tmp2 = load <2 x i64>* @a, align 16		; <<2 x i64>> [#uses=1]
+	%tmp2 = load <2 x i64>, <2 x i64>* @a, align 16		; <<2 x i64>> [#uses=1]
 	%tmp6 = bitcast <2 x i64> %b to <8 x i16>		; <<8 x i16>> [#uses=1]
 	%tmp9 = bitcast <2 x i64> %tmp2 to <8 x i16>		; <<8 x i16>> [#uses=1]
 	%tmp11 = tail call <4 x i32> @llvm.x86.sse2.pmadd.wd( <8 x i16> %tmp9, <8 x i16> %tmp6 ) nounwind readnone 		; <<4 x i32>> [#uses=1]
diff --git a/test/CodeGen/X86/commute-xop.ll b/test/CodeGen/X86/commute-xop.ll
new file mode 100644
index 000000000000..e551d9bfc78f
--- /dev/null
+++ b/test/CodeGen/X86/commute-xop.ll
@@ -0,0 +1,184 @@
+; RUN: llc -O3 -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx,+xop < %s | FileCheck %s
+
+define <16 x i8> @commute_fold_vpcomb(<16 x i8>* %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: commute_fold_vpcomb
+  ;CHECK:       vpcomgtb (%rdi), %xmm0, %xmm0
+  %1 = load <16 x i8>, <16 x i8>* %a0
+  %2 = call <16 x i8> @llvm.x86.xop.vpcomb(<16 x i8> %1, <16 x i8> %a1, i8 0) ; vpcomltb
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.xop.vpcomb(<16 x i8>, <16 x i8>, i8) nounwind readnone
+
+define <4 x i32> @commute_fold_vpcomd(<4 x i32>* %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: commute_fold_vpcomd
+  ;CHECK:       vpcomged (%rdi), %xmm0, %xmm0
+  %1 = load <4 x i32>, <4 x i32>* %a0
+  %2 = call <4 x i32> @llvm.x86.xop.vpcomd(<4 x i32> %1, <4 x i32> %a1, i8 1) ; vpcomled
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpcomd(<4 x i32>, <4 x i32>, i8) nounwind readnone
+
+define <2 x i64> @commute_fold_vpcomq(<2 x i64>* %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: commute_fold_vpcomq
+  ;CHECK:       vpcomltq (%rdi), %xmm0, %xmm0
+  %1 = load <2 x i64>, <2 x i64>* %a0
+  %2 = call <2 x i64> @llvm.x86.xop.vpcomq(<2 x i64> %1, <2 x i64> %a1, i8 2) ; vpcomgtq
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vpcomq(<2 x i64>, <2 x i64>, i8) nounwind readnone
+
+define <16 x i8> @commute_fold_vpcomub(<16 x i8>* %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: commute_fold_vpcomub
+  ;CHECK:       vpcomleub (%rdi), %xmm0, %xmm0
+  %1 = load <16 x i8>, <16 x i8>* %a0
+  %2 = call <16 x i8> @llvm.x86.xop.vpcomub(<16 x i8> %1, <16 x i8> %a1, i8 3) ; vpcomgeub
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.xop.vpcomub(<16 x i8>, <16 x i8>, i8) nounwind readnone
+
+define <4 x i32> @commute_fold_vpcomud(<4 x i32>* %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: commute_fold_vpcomud
+  ;CHECK:       vpcomequd (%rdi), %xmm0, %xmm0
+  %1 = load <4 x i32>, <4 x i32>* %a0
+  %2 = call <4 x i32> @llvm.x86.xop.vpcomud(<4 x i32> %1, <4 x i32> %a1, i8 4) ; vpcomequd
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpcomud(<4 x i32>, <4 x i32>, i8) nounwind readnone
+
+define <2 x i64> @commute_fold_vpcomuq(<2 x i64>* %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: commute_fold_vpcomuq
+  ;CHECK:       vpcomnequq (%rdi), %xmm0, %xmm0
+  %1 = load <2 x i64>, <2 x i64>* %a0
+  %2 = call <2 x i64> @llvm.x86.xop.vpcomuq(<2 x i64> %1, <2 x i64> %a1, i8 5) ; vpcomnequq
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vpcomuq(<2 x i64>, <2 x i64>, i8) nounwind readnone
+
+define <8 x i16> @commute_fold_vpcomuw(<8 x i16>* %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: commute_fold_vpcomuw
+  ;CHECK:       vpcomfalseuw (%rdi), %xmm0, %xmm0
+  %1 = load <8 x i16>, <8 x i16>* %a0
+  %2 = call <8 x i16> @llvm.x86.xop.vpcomuw(<8 x i16> %1, <8 x i16> %a1, i8 6) ; vpcomfalseuw
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.xop.vpcomuw(<8 x i16>, <8 x i16>, i8) nounwind readnone
+
+define <8 x i16> @commute_fold_vpcomw(<8 x i16>* %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: commute_fold_vpcomw
+  ;CHECK:       vpcomtruew (%rdi), %xmm0, %xmm0
+  %1 = load <8 x i16>, <8 x i16>* %a0
+  %2 = call <8 x i16> @llvm.x86.xop.vpcomw(<8 x i16> %1, <8 x i16> %a1, i8 7) ; vpcomtruew
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.xop.vpcomw(<8 x i16>, <8 x i16>, i8) nounwind readnone
+
+define <4 x i32> @commute_fold_vpmacsdd(<4 x i32>* %a0, <4 x i32> %a1, <4 x i32> %a2) {
+  ;CHECK-LABEL: commute_fold_vpmacsdd
+  ;CHECK:       vpmacsdd %xmm1, (%rdi), %xmm0, %xmm0
+  %1 = load <4 x i32>, <4 x i32>* %a0
+  %2 = call <4 x i32> @llvm.x86.xop.vpmacsdd(<4 x i32> %1, <4 x i32> %a1, <4 x i32> %a2)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpmacsdd(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
+
+define <2 x i64> @commute_fold_vpmacsdqh(<4 x i32>* %a0, <4 x i32> %a1, <2 x i64> %a2) {
+  ;CHECK-LABEL: commute_fold_vpmacsdqh
+  ;CHECK:       vpmacsdqh %xmm1, (%rdi), %xmm0, %xmm0
+  %1 = load <4 x i32>, <4 x i32>* %a0
+  %2 = call <2 x i64> @llvm.x86.xop.vpmacsdqh(<4 x i32> %1, <4 x i32> %a1, <2 x i64> %a2)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vpmacsdqh(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
+
+define <2 x i64> @commute_fold_vpmacsdql(<4 x i32>* %a0, <4 x i32> %a1, <2 x i64> %a2) {
+  ;CHECK-LABEL: commute_fold_vpmacsdql
+  ;CHECK:       vpmacsdql %xmm1, (%rdi), %xmm0, %xmm0
+  %1 = load <4 x i32>, <4 x i32>* %a0
+  %2 = call <2 x i64> @llvm.x86.xop.vpmacsdql(<4 x i32> %1, <4 x i32> %a1, <2 x i64> %a2)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vpmacsdql(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
+
+define <4 x i32> @commute_fold_vpmacssdd(<4 x i32>* %a0, <4 x i32> %a1, <4 x i32> %a2) {
+  ;CHECK-LABEL: commute_fold_vpmacssdd
+  ;CHECK:       vpmacssdd %xmm1, (%rdi), %xmm0, %xmm0
+  %1 = load <4 x i32>, <4 x i32>* %a0
+  %2 = call <4 x i32> @llvm.x86.xop.vpmacssdd(<4 x i32> %1, <4 x i32> %a1, <4 x i32> %a2)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpmacssdd(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
+
+define <2 x i64> @commute_fold_vpmacssdqh(<4 x i32>* %a0, <4 x i32> %a1, <2 x i64> %a2) {
+  ;CHECK-LABEL: commute_fold_vpmacssdqh
+  ;CHECK:       vpmacssdqh %xmm1, (%rdi), %xmm0, %xmm0
+  %1 = load <4 x i32>, <4 x i32>* %a0
+  %2 = call <2 x i64> @llvm.x86.xop.vpmacssdqh(<4 x i32> %1, <4 x i32> %a1, <2 x i64> %a2)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vpmacssdqh(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
+
+define <2 x i64> @commute_fold_vpmacssdql(<4 x i32>* %a0, <4 x i32> %a1, <2 x i64> %a2) {
+  ;CHECK-LABEL: commute_fold_vpmacssdql
+  ;CHECK:       vpmacssdql %xmm1, (%rdi), %xmm0, %xmm0
+  %1 = load <4 x i32>, <4 x i32>* %a0
+  %2 = call <2 x i64> @llvm.x86.xop.vpmacssdql(<4 x i32> %1, <4 x i32> %a1, <2 x i64> %a2)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vpmacssdql(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
+
+define <4 x i32> @commute_fold_vpmacsswd(<8 x i16>* %a0, <8 x i16> %a1, <4 x i32> %a2) {
+  ;CHECK-LABEL: commute_fold_vpmacsswd
+  ;CHECK:       vpmacsswd %xmm1, (%rdi), %xmm0, %xmm0
+  %1 = load <8 x i16>, <8 x i16>* %a0
+  %2 = call <4 x i32> @llvm.x86.xop.vpmacsswd(<8 x i16> %1, <8 x i16> %a1, <4 x i32> %a2)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpmacsswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @commute_fold_vpmacssww(<8 x i16>* %a0, <8 x i16> %a1, <8 x i16> %a2) {
+  ;CHECK-LABEL: commute_fold_vpmacssww
+  ;CHECK:       vpmacssww %xmm1, (%rdi), %xmm0, %xmm0
+  %1 = load <8 x i16>, <8 x i16>* %a0
+  %2 = call <8 x i16> @llvm.x86.xop.vpmacssww(<8 x i16> %1, <8 x i16> %a1, <8 x i16> %a2)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.xop.vpmacssww(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
+
+define <4 x i32> @commute_fold_vpmacswd(<8 x i16>* %a0, <8 x i16> %a1, <4 x i32> %a2) {
+  ;CHECK-LABEL: commute_fold_vpmacswd
+  ;CHECK:       vpmacswd %xmm1, (%rdi), %xmm0, %xmm0
+  %1 = load <8 x i16>, <8 x i16>* %a0
+  %2 = call <4 x i32> @llvm.x86.xop.vpmacswd(<8 x i16> %1, <8 x i16> %a1, <4 x i32> %a2)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpmacswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @commute_fold_vpmacsww(<8 x i16>* %a0, <8 x i16> %a1, <8 x i16> %a2) {
+  ;CHECK-LABEL: commute_fold_vpmacsww
+  ;CHECK:       vpmacsww %xmm1, (%rdi), %xmm0, %xmm0
+  %1 = load <8 x i16>, <8 x i16>* %a0
+  %2 = call <8 x i16> @llvm.x86.xop.vpmacsww(<8 x i16> %1, <8 x i16> %a1, <8 x i16> %a2)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.xop.vpmacsww(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
+
+define <4 x i32> @commute_fold_vpmadcsswd(<8 x i16>* %a0, <8 x i16> %a1, <4 x i32> %a2) {
+  ;CHECK-LABEL: commute_fold_vpmadcsswd
+  ;CHECK:       vpmadcsswd %xmm1, (%rdi), %xmm0, %xmm0
+  %1 = load <8 x i16>, <8 x i16>* %a0
+  %2 = call <4 x i32> @llvm.x86.xop.vpmadcsswd(<8 x i16> %1, <8 x i16> %a1, <4 x i32> %a2)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpmadcsswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
+
+define <4 x i32> @commute_fold_vpmadcswd(<8 x i16>* %a0, <8 x i16> %a1, <4 x i32> %a2) {
+  ;CHECK-LABEL: commute_fold_vpmadcswd
+  ;CHECK:       vpmadcswd %xmm1, (%rdi), %xmm0, %xmm0
+  %1 = load <8 x i16>, <8 x i16>* %a0
+  %2 = call <4 x i32> @llvm.x86.xop.vpmadcswd(<8 x i16> %1, <8 x i16> %a1, <4 x i32> %a2)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpmadcswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
+
+
+
diff --git a/test/CodeGen/X86/compact-unwind.ll b/test/CodeGen/X86/compact-unwind.ll
index d3b89a54e0b8..f8266a10cfb5 100644
--- a/test/CodeGen/X86/compact-unwind.ll
+++ b/test/CodeGen/X86/compact-unwind.ll
@@ -39,13 +39,13 @@
 
 define i8* @test0(i64 %size) {
   %addr = alloca i64, align 8
-  %tmp20 = load i32* @gv, align 4
+  %tmp20 = load i32, i32* @gv, align 4
   %tmp21 = call i32 @bar()
-  %tmp25 = load i64* %addr, align 8
+  %tmp25 = load i64, i64* %addr, align 8
   %tmp26 = inttoptr i64 %tmp25 to %ty*
-  %tmp29 = getelementptr inbounds %ty* %tmp26, i64 0, i32 0
-  %tmp34 = load i8** %tmp29, align 8
-  %tmp35 = getelementptr inbounds i8* %tmp34, i64 %size
+  %tmp29 = getelementptr inbounds %ty, %ty* %tmp26, i64 0, i32 0
+  %tmp34 = load i8*, i8** %tmp29, align 8
+  %tmp35 = getelementptr inbounds i8, i8* %tmp34, i64 %size
   store i8* %tmp35, i8** %tmp29, align 8
   ret i8* null
 }
@@ -84,8 +84,8 @@ for.cond1.preheader:                              ; preds = %for.inc10, %entry
 
 for.body3:                                        ; preds = %for.inc, %for.cond1.preheader
   %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.inc ]
-  %image4 = getelementptr inbounds %"struct.dyld::MappedRanges"* %p.019, i64 0, i32 0, i64 %indvars.iv, i32 0
-  %0 = load %class.ImageLoader** %image4, align 8
+  %image4 = getelementptr inbounds %"struct.dyld::MappedRanges", %"struct.dyld::MappedRanges"* %p.019, i64 0, i32 0, i64 %indvars.iv, i32 0
+  %0 = load %class.ImageLoader*, %class.ImageLoader** %image4, align 8
   %cmp5 = icmp eq %class.ImageLoader* %0, %image
   br i1 %cmp5, label %if.then, label %for.inc
 
@@ -101,8 +101,8 @@ for.inc:                                          ; preds = %if.then, %for.body3
   br i1 %exitcond, label %for.inc10, label %for.body3
 
 for.inc10:                                        ; preds = %for.inc
-  %next = getelementptr inbounds %"struct.dyld::MappedRanges"* %p.019, i64 0, i32 1
-  %1 = load %"struct.dyld::MappedRanges"** %next, align 8
+  %next = getelementptr inbounds %"struct.dyld::MappedRanges", %"struct.dyld::MappedRanges"* %p.019, i64 0, i32 1
+  %1 = load %"struct.dyld::MappedRanges"*, %"struct.dyld::MappedRanges"** %next, align 8
   %cmp = icmp eq %"struct.dyld::MappedRanges"* %1, null
   br i1 %cmp, label %for.end11, label %for.cond1.preheader
 
diff --git a/test/CodeGen/X86/complex-asm.ll b/test/CodeGen/X86/complex-asm.ll
index 49878b982db3..d7b5879309da 100644
--- a/test/CodeGen/X86/complex-asm.ll
+++ b/test/CodeGen/X86/complex-asm.ll
@@ -7,10 +7,10 @@ define %0 @f() nounwind ssp {
 entry:
   %v = alloca %0, align 8
   call void asm sideeffect "", "=*r,r,r,0,~{dirflag},~{fpsr},~{flags}"(%0* %v, i32 0, i32 1, i128 undef) nounwind
-  %0 = getelementptr inbounds %0* %v, i64 0, i32 0
-  %1 = load i64* %0, align 8
-  %2 = getelementptr inbounds %0* %v, i64 0, i32 1
-  %3 = load i64* %2, align 8
+  %0 = getelementptr inbounds %0, %0* %v, i64 0, i32 0
+  %1 = load i64, i64* %0, align 8
+  %2 = getelementptr inbounds %0, %0* %v, i64 0, i32 1
+  %3 = load i64, i64* %2, align 8
   %mrv4 = insertvalue %0 undef, i64 %1, 0
   %mrv5 = insertvalue %0 %mrv4, i64 %3, 1
   ret %0 %mrv5
diff --git a/test/CodeGen/X86/complex-fca.ll b/test/CodeGen/X86/complex-fca.ll
index 8ad38a4ee5c0..78b27b7dc3f5 100644
--- a/test/CodeGen/X86/complex-fca.ll
+++ b/test/CodeGen/X86/complex-fca.ll
@@ -1,17 +1,21 @@
-; RUN: llc < %s -march=x86 | grep mov | count 2
-
-; Skip this on Windows as there is no ccosl and sret behaves differently.
-; XFAIL: pc-win32
+; RUN: llc < %s -march=x86 | FileCheck %s
 
 define void @ccosl({ x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 } %z) nounwind {
 entry:
-	%z8 = extractvalue { x86_fp80, x86_fp80 } %z, 0
-	%z9 = extractvalue { x86_fp80, x86_fp80 } %z, 1
-	%0 = fsub x86_fp80 0xK80000000000000000000, %z9
-	%insert = insertvalue { x86_fp80, x86_fp80 } undef, x86_fp80 %0, 0
-	%insert7 = insertvalue { x86_fp80, x86_fp80 } %insert, x86_fp80 %z8, 1
-	call void @ccoshl({ x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 } %insert7) nounwind
-	ret void
+  %z8 = extractvalue { x86_fp80, x86_fp80 } %z, 0
+  %z9 = extractvalue { x86_fp80, x86_fp80 } %z, 1
+  %0 = fsub x86_fp80 0xK80000000000000000000, %z9
+  %insert = insertvalue { x86_fp80, x86_fp80 } undef, x86_fp80 %0, 0
+  %insert7 = insertvalue { x86_fp80, x86_fp80 } %insert, x86_fp80 %z8, 1
+  call void @ccoshl({ x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 } %insert7) nounwind
+  ret void
 }
 
+; CHECK-LABEL: ccosl:
+; CHECK:         movl    {{[0-9]+}}(%esp), %[[sret_reg:[^ ]+]]
+; CHECK:         movl    %[[sret_reg]], (%esp)
+; CHECK:         calll   {{.*ccoshl.*}}
+; CHECK:         movl    %[[sret_reg]], %eax
+; CHECK:         retl
+
 declare void @ccoshl({ x86_fp80, x86_fp80 }* noalias sret, { x86_fp80, x86_fp80 }) nounwind
diff --git a/test/CodeGen/X86/computeKnownBits_urem.ll b/test/CodeGen/X86/computeKnownBits_urem.ll
index 9902e6f2597b..a72740e19572 100644
--- a/test/CodeGen/X86/computeKnownBits_urem.ll
+++ b/test/CodeGen/X86/computeKnownBits_urem.ll
@@ -3,7 +3,7 @@ define i32 @main() #0 {
 entry:
   %a = alloca i32, align 4
   store i32 1, i32* %a, align 4
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %or = or i32 1, %0
   %and = and i32 1, %or
   %rem = urem i32 %and, 1
diff --git a/test/CodeGen/X86/const-base-addr.ll b/test/CodeGen/X86/const-base-addr.ll
index f859d7fafff3..42647136fe30 100644
--- a/test/CodeGen/X86/const-base-addr.ll
+++ b/test/CodeGen/X86/const-base-addr.ll
@@ -11,12 +11,12 @@ define i32 @test1() nounwind {
 ; CHECK-NEXT:   movl  4(%rcx), %eax
 ; CHECK-NEXT:   addl  8(%rcx), %eax
 ; CHECK-NEXT:   addl  12(%rcx), %eax
-  %addr1 = getelementptr %T* inttoptr (i64 123456789012345678 to %T*), i32 0, i32 1
-  %tmp1 = load i32* %addr1
-  %addr2 = getelementptr %T* inttoptr (i64 123456789012345678 to %T*), i32 0, i32 2
-  %tmp2 = load i32* %addr2
-  %addr3 = getelementptr %T* inttoptr (i64 123456789012345678 to %T*), i32 0, i32 3
-  %tmp3 = load i32* %addr3
+  %addr1 = getelementptr %T, %T* inttoptr (i64 123456789012345678 to %T*), i32 0, i32 1
+  %tmp1 = load i32, i32* %addr1
+  %addr2 = getelementptr %T, %T* inttoptr (i64 123456789012345678 to %T*), i32 0, i32 2
+  %tmp2 = load i32, i32* %addr2
+  %addr3 = getelementptr %T, %T* inttoptr (i64 123456789012345678 to %T*), i32 0, i32 3
+  %tmp3 = load i32, i32* %addr3
   %tmp4 = add i32 %tmp1, %tmp2
   %tmp5 = add i32 %tmp3, %tmp4
   ret i32 %tmp5
diff --git a/test/CodeGen/X86/constant-combines.ll b/test/CodeGen/X86/constant-combines.ll
index d2a6ef4f5d25..5ea736e92c78 100644
--- a/test/CodeGen/X86/constant-combines.ll
+++ b/test/CodeGen/X86/constant-combines.ll
@@ -14,13 +14,13 @@ define void @PR22524({ float, float }* %arg) {
 ; 
 ; CHECK-LABEL: PR22524:
 entry:
-  %0 = getelementptr inbounds { float, float }* %arg,  i32 0, i32 1
+  %0 = getelementptr inbounds { float, float }, { float, float }* %arg,  i32 0, i32 1
   store float 0.000000e+00, float* %0, align 4
 ; CHECK: movl $0, 4(%rdi)
 
-  %1 = getelementptr inbounds { float, float }* %arg, i64 0,  i32 0
+  %1 = getelementptr inbounds { float, float }, { float, float }* %arg, i64 0,  i32 0
   %2 = bitcast float* %1 to i64*
-  %3 = load i64* %2, align 8
+  %3 = load i64, i64* %2, align 8
   %4 = trunc i64 %3 to i32
   %5 = lshr i64 %3, 32
   %6 = trunc i64 %5 to i32
diff --git a/test/CodeGen/X86/constant-hoisting-optnone.ll b/test/CodeGen/X86/constant-hoisting-optnone.ll
new file mode 100644
index 000000000000..4d8a06c444da
--- /dev/null
+++ b/test/CodeGen/X86/constant-hoisting-optnone.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=generic | FileCheck %s
+;
+; Verify that pass 'Constant Hoisting' is not run on optnone functions.
+; Without optnone, Pass 'Constant Hoisting' would firstly hoist
+; constant 0xBEEBEEBEC, and then rebase the other constant
+; (i.e. constant 0xBEEBEEBF4) with respect to the previous one.
+; With optnone, we check that constants are not coalesced.
+
+define i64 @constant_hoisting_optnone() #0 {
+; CHECK-LABEL: @constant_hoisting_optnone
+; CHECK-DAG: movabsq {{.*#+}} imm = 0xBEEBEEBF4
+; CHECK-DAG: movabsq {{.*#+}} imm = 0xBEEBEEBEC
+; CHECK: ret
+entry:
+  %0 = load i64, i64* inttoptr (i64 51250129900 to i64*)
+  %1 = load i64, i64* inttoptr (i64 51250129908 to i64*)
+  %2 = add i64 %0, %1
+  ret i64 %2
+}
+
+attributes #0 = { optnone noinline }
diff --git a/test/CodeGen/X86/constant-hoisting-shift-immediate.ll b/test/CodeGen/X86/constant-hoisting-shift-immediate.ll
index 883be355bd36..65c26f818a6a 100644
--- a/test/CodeGen/X86/constant-hoisting-shift-immediate.ll
+++ b/test/CodeGen/X86/constant-hoisting-shift-immediate.ll
@@ -6,7 +6,7 @@ define i64 @foo(i1 %z, i192* %p, i192* %q)
 ; be in another basic block. As a result, a very inefficient code might be
 ; produced. Here we check that this doesn't occur.
 entry:
-  %data1 = load i192* %p, align 8
+  %data1 = load i192, i192* %p, align 8
   %lshr1 = lshr i192 %data1, 128
   %val1  = trunc i192 %lshr1 to i64
   br i1 %z, label %End, label %L_val2
@@ -14,7 +14,7 @@ entry:
 ; CHECK: movq    16(%rdx), %rax
 ; CHECK-NEXT: retq
 L_val2:
-  %data2 = load i192* %q, align 8
+  %data2 = load i192, i192* %q, align 8
   %lshr2 = lshr i192 %data2, 128
   %val2  = trunc i192 %lshr2 to i64
   br label %End
diff --git a/test/CodeGen/X86/constructor.ll b/test/CodeGen/X86/constructor.ll
index 7160dcc614c0..e7c846045f01 100644
--- a/test/CodeGen/X86/constructor.ll
+++ b/test/CodeGen/X86/constructor.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -mtriple x86_64-pc-linux -use-ctors < %s | FileCheck --check-prefix=CTOR %s
 ; RUN: llc -mtriple x86_64-pc-linux < %s | FileCheck --check-prefix=INIT-ARRAY %s
+; RUN: llc -mtriple x86_64-unknown-nacl < %s | FileCheck --check-prefix=NACL %s
 @llvm.global_ctors = appending global [2 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @f, i8* null}, { i32, void ()*, i8* } { i32 15, void ()* @g, i8* @v }]
 
 @v = weak_odr global i8 0
@@ -27,3 +28,10 @@ entry:
 ; INIT-ARRAY-NEXT:	.section	.init_array,"aw",@init_array
 ; INIT-ARRAY-NEXT:	.align	8
 ; INIT-ARRAY-NEXT:	.quad	f
+
+; NACL:		.section	.init_array.15,"aGw",@init_array,v,comdat
+; NACL-NEXT:	.align	4
+; NACL-NEXT:	.long	g
+; NACL-NEXT:	.section	.init_array,"aw",@init_array
+; NACL-NEXT:	.align	4
+; NACL-NEXT:	.long	f
diff --git a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
index 74a7240c8190..7fc56f5accc2 100644
--- a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
+++ b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
@@ -11,8 +11,8 @@ define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2, i8* %ptr) nounwind optsize {
 entry:
   %0 = add i32 %i2, 1           ; <i32> [#uses=1]
   %1 = sext i32 %0 to i64               ; <i64> [#uses=1]
-  %2 = getelementptr i8* %ptr, i64 %1           ; <i8*> [#uses=1]
-  %3 = load i8* %2, align 1             ; <i8> [#uses=1]
+  %2 = getelementptr i8, i8* %ptr, i64 %1           ; <i8*> [#uses=1]
+  %3 = load i8, i8* %2, align 1             ; <i8> [#uses=1]
   %4 = icmp eq i8 0, %3         ; <i1> [#uses=1]
   br i1 %4, label %bb3, label %bb34
 
diff --git a/test/CodeGen/X86/copy-propagation.ll b/test/CodeGen/X86/copy-propagation.ll
new file mode 100644
index 000000000000..19421a06fa82
--- /dev/null
+++ b/test/CodeGen/X86/copy-propagation.ll
@@ -0,0 +1,44 @@
+; RUN: llc %s -mattr=+avx -o - | FileCheck %s
+; PR21743.
+
+target triple = "x86_64-pc-win32-elf"
+
+; Check that copy propagation conservatively assumes that undef register
+; can be rewritten by the backend to break false dependencies for the
+; hardware.
+; In this function we are in this situation:
+; reg1 = copy reg2
+; = inst reg2<undef>
+; reg2 = copy reg1
+; Copy propagation used to remove the last copy.
+; This is incorrect because the undef flag on reg2 in inst, allows next
+; passes to put whatever trashed value in reg2 that may help.
+; In practice we end up with this code:
+; reg1 = copy reg2
+; reg2 = 0
+; = inst reg2<undef>
+; reg2 = copy reg1
+; Therefore, removing the last copy is wrong.
+;
+; CHECK-LABEL: foo:
+; CHECK: movl	$339752784, %e[[INDIRECT_CALL1:[a-z]+]]
+; CHECK: callq *%r[[INDIRECT_CALL1]]
+; Copy the result in a temporary.
+; Note: Technically the regalloc could have been smarter and this move not required,
+; which would have hidden the bug.
+; CHECK-NEXT: vmovapd	%xmm0, [[TMP:%xmm[0-9]+]]
+; Crush xmm0.
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK: movl	$339772768, %e[[INDIRECT_CALL2:[a-z]+]]
+; Set TMP in the first argument of the second call.
+; CHECK-NEXT: vmovapd	[[TMP]], %xmm0
+; CHECK: callq *%r[[INDIRECT_CALL2]]
+; CHECK: retq
+define double @foo(i64 %arg) {
+top:
+  %tmp = call double inttoptr (i64 339752784 to double (double, double)*)(double 1.000000e+00, double 0.000000e+00)
+  %tmp1 = sitofp i64 %arg to double
+  call void inttoptr (i64 339772768 to void (double, double)*)(double %tmp, double %tmp1)
+  %tmp3 = fadd double %tmp1, %tmp
+  ret double %tmp3
+}
diff --git a/test/CodeGen/X86/crash-O0.ll b/test/CodeGen/X86/crash-O0.ll
index df8eaaf442b7..dab15c19c69e 100644
--- a/test/CodeGen/X86/crash-O0.ll
+++ b/test/CodeGen/X86/crash-O0.ll
@@ -44,8 +44,8 @@ entry:
 ; CHECK-NEXT: idivq
 ; CHECK: retq
 define i64 @addressModeWith32bitIndex(i32 %V) {
-  %gep = getelementptr i64* null, i32 %V
-  %load = load i64* %gep
+  %gep = getelementptr i64, i64* null, i32 %V
+  %load = load i64, i64* %gep
   %sdiv = sdiv i64 0, %load
   ret i64 %sdiv
 }
diff --git a/test/CodeGen/X86/crash-nosse.ll b/test/CodeGen/X86/crash-nosse.ll
index b1e01f94c9e6..aff120dbb842 100644
--- a/test/CodeGen/X86/crash-nosse.ll
+++ b/test/CodeGen/X86/crash-nosse.ll
@@ -11,7 +11,7 @@ BB:
   br label %CF
 
 CF:                                               ; preds = %CF, %BB
-  %L19 = load <8 x float>* %S17
+  %L19 = load <8 x float>, <8 x float>* %S17
   %BC = bitcast <32 x i32> %Shuff6 to <32 x float>
   %S28 = fcmp ord double 0x3ED1A1F787BB2185, 0x3EE59DE55A8DF890
   br i1 %S28, label %CF, label %CF39
diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll
index 6b3dd3675750..a95b84d4c3b0 100644
--- a/test/CodeGen/X86/crash.ll
+++ b/test/CodeGen/X86/crash.ll
@@ -7,9 +7,9 @@
 ; Chain and flag folding issues.
 define i32 @test1() nounwind ssp {
 entry:
-  %tmp5.i = load volatile i32* undef              ; <i32> [#uses=1]
+  %tmp5.i = load volatile i32, i32* undef              ; <i32> [#uses=1]
   %conv.i = zext i32 %tmp5.i to i64               ; <i64> [#uses=1]
-  %tmp12.i = load volatile i32* undef             ; <i32> [#uses=1]
+  %tmp12.i = load volatile i32, i32* undef             ; <i32> [#uses=1]
   %conv13.i = zext i32 %tmp12.i to i64            ; <i64> [#uses=1]
   %shl.i = shl i64 %conv13.i, 32                  ; <i64> [#uses=1]
   %or.i = or i64 %shl.i, %conv.i                  ; <i64> [#uses=1]
@@ -40,7 +40,7 @@ if.end:                                           ; preds = %land.end
 
 define void @test3() {
 dependentGraph243.exit:
-  %subject19 = load %pair* undef                     ; <%1> [#uses=1]
+  %subject19 = load %pair, %pair* undef                     ; <%1> [#uses=1]
   %0 = extractvalue %pair %subject19, 1              ; <double> [#uses=2]
   %1 = select i1 undef, double %0, double undef   ; <double> [#uses=1]
   %2 = select i1 undef, double %1, double %0      ; <double> [#uses=1]
@@ -52,7 +52,7 @@ dependentGraph243.exit:
 ; PR6605
 define i64 @test4(i8* %P) nounwind ssp {
 entry:
-  %tmp1 = load i8* %P                           ; <i8> [#uses=3]
+  %tmp1 = load i8, i8* %P                           ; <i8> [#uses=3]
   %tobool = icmp eq i8 %tmp1, 0                   ; <i1> [#uses=1]
   %tmp58 = sext i1 %tobool to i8                  ; <i8> [#uses=1]
   %mul.i = and i8 %tmp58, %tmp1                   ; <i8> [#uses=1]
@@ -76,7 +76,7 @@ declare i32 @safe(i32)
 ; PR6607
 define fastcc void @test5(i32 %FUNC) nounwind {
 foo:
-  %0 = load i8* undef, align 1                    ; <i8> [#uses=3]
+  %0 = load i8, i8* undef, align 1                    ; <i8> [#uses=3]
   %1 = sext i8 %0 to i32                          ; <i32> [#uses=2]
   %2 = zext i8 %0 to i32                          ; <i32> [#uses=1]
   %tmp1.i5037 = urem i32 %2, 10                   ; <i32> [#uses=1]
@@ -121,7 +121,7 @@ entry:
 
 bb14:
   %tmp0 = trunc i16 undef to i1
-  %tmp1 = load i8* undef, align 8
+  %tmp1 = load i8, i8* undef, align 8
   %tmp2 = shl i8 %tmp1, 4
   %tmp3 = lshr i8 %tmp2, 7
   %tmp4 = trunc i8 %tmp3 to i1
@@ -174,12 +174,12 @@ for.body22:                                       ; preds = %for.body22, %bb.nph
   %l_75.077 = phi i64 [ %ins, %for.body22 ], [ undef, %bb.nph81 ]
   %tmp110 = trunc i64 %l_75.077 to i32
   %tmp111 = and i32 %tmp110, 65535
-  %arrayidx32.0 = getelementptr [9 x [5 x [2 x %struct.S0]]]* undef, i32 0, i32 %l_74.0, i32 %tmp98, i32 %tmp111, i32 0
+  %arrayidx32.0 = getelementptr [9 x [5 x [2 x %struct.S0]]], [9 x [5 x [2 x %struct.S0]]]* undef, i32 0, i32 %l_74.0, i32 %tmp98, i32 %tmp111, i32 0
   store i8 1, i8* %arrayidx32.0, align 4
   %tmp106 = shl i32 %tmp110, 2
   %tmp107 = and i32 %tmp106, 262140
   %scevgep99.sum114 = or i32 %tmp107, 1
-  %arrayidx32.1.1 = getelementptr [9 x [5 x [2 x %struct.S0]]]* undef, i32 0, i32 %l_74.0, i32 %tmp98, i32 0, i32 1, i32 %scevgep99.sum114
+  %arrayidx32.1.1 = getelementptr [9 x [5 x [2 x %struct.S0]]], [9 x [5 x [2 x %struct.S0]]]* undef, i32 0, i32 %l_74.0, i32 %tmp98, i32 0, i32 1, i32 %scevgep99.sum114
   store i8 0, i8* %arrayidx32.1.1, align 1
   %ins = or i64 undef, undef
   br label %for.body22
@@ -239,9 +239,9 @@ declare i64 @llvm.objectsize.i64.p0i8(i8*, i1) nounwind readnone
 
 define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE() ssp align 2 {
 bb:
-  %tmp = load %t9** undef, align 4
-  %tmp2 = getelementptr inbounds %t9* %tmp, i32 0, i32 0
-  %tmp3 = getelementptr inbounds %t9* %tmp, i32 0, i32 0, i32 0, i32 0, i32 1
+  %tmp = load %t9*, %t9** undef, align 4
+  %tmp2 = getelementptr inbounds %t9, %t9* %tmp, i32 0, i32 0
+  %tmp3 = getelementptr inbounds %t9, %t9* %tmp, i32 0, i32 0, i32 0, i32 0, i32 1
   br label %bb4
 
 bb4:                                              ; preds = %bb37, %bb
@@ -250,25 +250,25 @@ bb4:                                              ; preds = %bb37, %bb
   br i1 undef, label %bb34, label %bb7
 
 bb7:                                              ; preds = %bb4
-  %tmp8 = load i32* undef, align 4
+  %tmp8 = load i32, i32* undef, align 4
   %tmp9 = and i96 %tmp6, 4294967040
   %tmp10 = zext i32 %tmp8 to i96
   %tmp11 = shl nuw nsw i96 %tmp10, 32
   %tmp12 = or i96 %tmp9, %tmp11
   %tmp13 = or i96 %tmp12, 1
-  %tmp14 = load i32* undef, align 4
+  %tmp14 = load i32, i32* undef, align 4
   %tmp15 = and i96 %tmp5, 4294967040
   %tmp16 = zext i32 %tmp14 to i96
   %tmp17 = shl nuw nsw i96 %tmp16, 32
   %tmp18 = or i96 %tmp15, %tmp17
   %tmp19 = or i96 %tmp18, 1
-  %tmp20 = load i8* undef, align 1
+  %tmp20 = load i8, i8* undef, align 1
   %tmp21 = and i8 %tmp20, 1
   %tmp22 = icmp ne i8 %tmp21, 0
   %tmp23 = select i1 %tmp22, i96 %tmp19, i96 %tmp13
   %tmp24 = select i1 %tmp22, i96 %tmp13, i96 %tmp19
   store i96 %tmp24, i96* undef, align 4
-  %tmp25 = load %t13** %tmp3, align 4
+  %tmp25 = load %t13*, %t13** %tmp3, align 4
   %tmp26 = icmp eq %t13* %tmp25, undef
   br i1 %tmp26, label %bb28, label %bb27
 
@@ -281,11 +281,11 @@ bb28:                                             ; preds = %bb7
 
 bb29:                                             ; preds = %bb28, %bb27
   store i96 %tmp23, i96* undef, align 4
-  %tmp30 = load %t13** %tmp3, align 4
+  %tmp30 = load %t13*, %t13** %tmp3, align 4
   br i1 false, label %bb33, label %bb31
 
 bb31:                                             ; preds = %bb29
-  %tmp32 = getelementptr inbounds %t13* %tmp30, i32 1
+  %tmp32 = getelementptr inbounds %t13, %t13* %tmp30, i32 1
   store %t13* %tmp32, %t13** %tmp3, align 4
   br label %bb37
 
@@ -348,13 +348,13 @@ entry:
   br label %"4"
 
 "3":
-  %0 = load <2 x i32>* null, align 8
+  %0 = load <2 x i32>, <2 x i32>* null, align 8
   %1 = xor <2 x i32> zeroinitializer, %0
   %2 = and <2 x i32> %1, %6
   %3 = or <2 x i32> undef, %2
   %4 = and <2 x i32> %3, undef
   store <2 x i32> %4, <2 x i32>* undef
-  %5 = load <2 x i32>* undef, align 1
+  %5 = load <2 x i32>, <2 x i32>* undef, align 1
   br label %"4"
 
 "4":
@@ -378,7 +378,7 @@ entry:
 @__force_order = external hidden global i32, align 4
 define void @pr11078(i32* %pgd) nounwind {
 entry:
-  %t0 = load i32* %pgd, align 4
+  %t0 = load i32, i32* %pgd, align 4
   %and2 = and i32 %t0, 1
   %tobool = icmp eq i32 %and2, 0
   br i1 %tobool, label %if.then, label %if.end
@@ -405,7 +405,7 @@ while.body.preheader:                             ; preds = %entry
   br i1 undef, label %if.then3, label %if.end7
 
 if.then3:                                         ; preds = %while.body.preheader
-  %0 = load i32* undef, align 4
+  %0 = load i32, i32* undef, align 4
   br i1 undef, label %land.lhs.true.i255, label %if.end7
 
 land.lhs.true.i255:                               ; preds = %if.then3
@@ -434,12 +434,12 @@ return:                                           ; preds = %entry
 @.str = private unnamed_addr constant { [1 x i8], [63 x i8] } zeroinitializer, align 32
 define void @pr13188(i64* nocapture %this) uwtable ssp sanitize_address align 2 {
 entry:
-  %x7 = load i64* %this, align 8
+  %x7 = load i64, i64* %this, align 8
   %sub = add i64 %x7, -1
   %conv = uitofp i64 %sub to float
   %div = fmul float %conv, 5.000000e-01
   %conv2 = fpext float %div to double
-  tail call void (...)* @_Z6PrintFz(i8* getelementptr inbounds ({ [1 x i8], [63 x i8] }* @.str, i64 0, i32 0, i64 0), double %conv2)
+  tail call void (...) @_Z6PrintFz(i8* getelementptr inbounds ({ [1 x i8], [63 x i8] }, { [1 x i8], [63 x i8] }* @.str, i64 0, i32 0, i64 0), double %conv2)
   ret void
 }
 declare void @_Z6PrintFz(...)
@@ -450,19 +450,19 @@ declare void @_Z6PrintFz(...)
 
 define void @pr13943() nounwind uwtable ssp {
 entry:
-  %srcval = load i576* bitcast ([9 x i32*]* @fn1.g to i576*), align 16
+  %srcval = load i576, i576* bitcast ([9 x i32*]* @fn1.g to i576*), align 16
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
   %g.0 = phi i576 [ %srcval, %entry ], [ %ins, %for.inc ]
-  %0 = load i32* @e, align 4
+  %0 = load i32, i32* @e, align 4
   %1 = lshr i576 %g.0, 64
   %2 = trunc i576 %1 to i64
   %3 = inttoptr i64 %2 to i32*
   %cmp = icmp eq i32* undef, %3
   %conv2 = zext i1 %cmp to i32
   %and = and i32 %conv2, %0
-  tail call void (...)* @fn3(i32 %and) nounwind
+  tail call void (...) @fn3(i32 %and) nounwind
   %tobool = icmp eq i32 undef, 0
   br i1 %tobool, label %for.inc, label %if.then
 
@@ -510,9 +510,9 @@ bb4:                                              ; preds = %bb3
   unreachable
 
 bb5:                                              ; preds = %bb3
-  %tmp = load <4 x float>* undef, align 1
+  %tmp = load <4 x float>, <4 x float>* undef, align 1
   %tmp6 = bitcast <4 x float> %tmp to i128
-  %tmp7 = load <4 x float>* undef, align 1
+  %tmp7 = load <4 x float>, <4 x float>* undef, align 1
   %tmp8 = bitcast <4 x float> %tmp7 to i128
   br label %bb10
 
@@ -583,7 +583,7 @@ bb29:                                             ; preds = %bb28, %bb26, %bb25,
 }
 
 define void @pr14194() nounwind uwtable {
-  %tmp = load i64* undef, align 16
+  %tmp = load i64, i64* undef, align 16
   %tmp1 = trunc i64 %tmp to i32
   %tmp2 = lshr i64 %tmp, 32
   %tmp3 = trunc i64 %tmp2 to i32
diff --git a/test/CodeGen/X86/critical-anti-dep-breaker.ll b/test/CodeGen/X86/critical-anti-dep-breaker.ll
index 32d3f49c79cc..86afc1f245ad 100644
--- a/test/CodeGen/X86/critical-anti-dep-breaker.ll
+++ b/test/CodeGen/X86/critical-anti-dep-breaker.ll
@@ -16,9 +16,9 @@
 define i32 @Part_Create(i64* %Anchor, i32 %TypeNum, i32 %F, i32 %Z, i32* %Status, i64* %PartTkn) {
   %PartObj = alloca i64*, align 8
   %Vchunk = alloca i64, align 8
-  %1 = load i64* @NullToken, align 4
+  %1 = load i64, i64* @NullToken, align 4
   store i64 %1, i64* %Vchunk, align 8
-  %2 = load i32* @PartClass, align 4
+  %2 = load i32, i32* @PartClass, align 4
   call i32 @Image(i64* %Anchor, i32 %2, i32 0, i32 0, i32* %Status, i64* %PartTkn, i64** %PartObj)
   call i32 @Create(i64* %Anchor)
   ret i32 %2
diff --git a/test/CodeGen/X86/critical-edge-split-2.ll b/test/CodeGen/X86/critical-edge-split-2.ll
index 44205d6829dd..d5878bd1a748 100644
--- a/test/CodeGen/X86/critical-edge-split-2.ll
+++ b/test/CodeGen/X86/critical-edge-split-2.ll
@@ -18,7 +18,7 @@ cond.false.i:                                     ; preds = %entry
   br label %cond.end.i
 
 cond.end.i:                                       ; preds = %entry
-  %call1 = phi i16 [ trunc (i32 srem (i32 1, i32 zext (i1 icmp eq (%1* bitcast (i8* getelementptr inbounds (%0* @g_2, i64 0, i32 1, i32 0) to %1*), %1* @g_4) to i32)) to i16), %cond.false.i ], [ 1, %entry ]
+  %call1 = phi i16 [ trunc (i32 srem (i32 1, i32 zext (i1 icmp eq (%1* bitcast (i8* getelementptr inbounds (%0, %0* @g_2, i64 0, i32 1, i32 0) to %1*), %1* @g_4) to i32)) to i16), %cond.false.i ], [ 1, %entry ]
   ret i16 %call1
 }
 
diff --git a/test/CodeGen/X86/cse-add-with-overflow.ll b/test/CodeGen/X86/cse-add-with-overflow.ll
index 1fcc03f117d3..dc02fe915840 100644
--- a/test/CodeGen/X86/cse-add-with-overflow.ll
+++ b/test/CodeGen/X86/cse-add-with-overflow.ll
@@ -15,8 +15,8 @@
 
 define i64 @redundantadd(i64* %a0, i64* %a1) {
 entry:
-  %tmp8 = load i64* %a0, align 8
-  %tmp12 = load i64* %a1, align 8
+  %tmp8 = load i64, i64* %a0, align 8
+  %tmp12 = load i64, i64* %a1, align 8
   %tmp13 = icmp ult i64 %tmp12, -281474976710656
   br i1 %tmp13, label %exit1, label %body
 
diff --git a/test/CodeGen/X86/cttz-ctlz.ll b/test/CodeGen/X86/cttz-ctlz.ll
deleted file mode 100644
index 8717d4015954..000000000000
--- a/test/CodeGen/X86/cttz-ctlz.ll
+++ /dev/null
@@ -1,422 +0,0 @@
-; RUN: opt -S -codegenprepare -mtriple=x86_64-unknown-unknown -mattr=+bmi < %s | FileCheck %s --check-prefix=ALL --check-prefix=BMI
-; RUN: opt -S -codegenprepare -mtriple=x86_64-unknown-unknown -mattr=+lzcnt < %s | FileCheck %s --check-prefix=ALL --check-prefix=LZCNT
-; RUN: opt -S -codegenprepare -mtriple=x86_64-unknown-unknown < %s | FileCheck %s --check-prefix=ALL --check-prefix=GENERIC
-
-
-define i64 @test1(i64 %A) {
-; ALL-LABEL: @test1(
-; LZCNT: [[CTLZ:%[A-Za-z0-9]+]] = call i64 @llvm.ctlz.i64(i64 %A, i1 false)
-; LZCNT-NEXT: ret i64 [[CTLZ]]
-; BMI: icmp eq i64 %A, 0
-; BMI: call i64 @llvm.ctlz.i64(i64 %A, i1 true)
-; GENERIC: icmp eq i64 %A, 0
-; GENERIC: call i64 @llvm.ctlz.i64(i64 %A, i1 true)
-entry:
-  %tobool = icmp eq i64 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i64 [ %0, %cond.true ], [ 64, %entry ]
-  ret i64 %cond
-}
-
-
-define i32 @test2(i32 %A) {
-; ALL-LABEL: @test2(
-; LZCNT: [[CTLZ:%[A-Za-z0-9]+]] = call i32 @llvm.ctlz.i32(i32 %A, i1 false)
-; LZCNT-NEXT: ret i32 [[CTLZ]]
-; BMI: icmp eq i32 %A, 0
-; BMI: call i32 @llvm.ctlz.i32(i32 %A, i1 true)
-; GENERIC: icmp eq i32 %A, 0
-; GENERIC: call i32 @llvm.ctlz.i32(i32 %A, i1 true)
-entry:
-  %tobool = icmp eq i32 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i32 [ %0, %cond.true ], [ 32, %entry ]
-  ret i32 %cond
-}
-
-
-define signext i16 @test3(i16 signext %A) {
-; ALL-LABEL: @test3(
-; LZCNT: [[CTLZ:%[A-Za-z0-9]+]] = call i16 @llvm.ctlz.i16(i16 %A, i1 false)
-; LZCNT-NEXT: ret i16 [[CTLZ]]
-; BMI: icmp eq i16 %A, 0
-; BMI: call i16 @llvm.ctlz.i16(i16 %A, i1 true)
-; GENERIC: icmp eq i16 %A, 0
-; GENERIC: call i16 @llvm.ctlz.i16(i16 %A, i1 true)
-entry:
-  %tobool = icmp eq i16 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i16 [ %0, %cond.true ], [ 16, %entry ]
-  ret i16 %cond
-}
-
-
-define i64 @test1b(i64 %A) {
-; ALL-LABEL: @test1b(
-; LZCNT: icmp eq i64 %A, 0
-; LZCNT: call i64 @llvm.cttz.i64(i64 %A, i1 true)
-; BMI: [[CTTZ:%[A-Za-z0-9]+]] = call i64 @llvm.cttz.i64(i64 %A, i1 false)
-; BMI-NEXT: ret i64 [[CTTZ]]
-; GENERIC: icmp eq i64 %A, 0
-; GENERIC: call i64 @llvm.cttz.i64(i64 %A, i1 true)
-entry:
-  %tobool = icmp eq i64 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i64 [ %0, %cond.true ], [ 64, %entry ]
-  ret i64 %cond
-}
-
-
-define i32 @test2b(i32 %A) {
-; ALL-LABEL: @test2b(
-; LZCNT: icmp eq i32 %A, 0
-; LZCNT: call i32 @llvm.cttz.i32(i32 %A, i1 true)
-; BMI: [[CTTZ:%[A-Za-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %A, i1 false)
-; BMI-NEXT: ret i32 [[CTTZ]]
-; GENERIC: icmp eq i32 %A, 0
-; GENERIC: call i32 @llvm.cttz.i32(i32 %A, i1 true)
-entry:
-  %tobool = icmp eq i32 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i32 [ %0, %cond.true ], [ 32, %entry ]
-  ret i32 %cond
-}
-
-
-define signext i16 @test3b(i16 signext %A) {
-; ALL-LABEL: @test3b(
-; LZCNT: icmp eq i16 %A, 0
-; LZCNT: call i16 @llvm.cttz.i16(i16 %A, i1 true)
-; BMI: [[CTTZ:%[A-Za-z0-9]+]] = call i16 @llvm.cttz.i16(i16 %A, i1 false)
-; BMI-NEXT: ret i16 [[CTTZ]]
-; GENERIC: icmp eq i16 %A, 0
-; GENERIC: call i16 @llvm.cttz.i16(i16 %A, i1 true)
-entry:
-  %tobool = icmp eq i16 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i16 [ %0, %cond.true ], [ 16, %entry ]
-  ret i16 %cond
-}
-
-
-define i64 @test1c(i64 %A) {
-; ALL-LABEL: @test1c(
-; ALL: icmp eq i64 %A, 0
-; ALL: call i64 @llvm.ctlz.i64(i64 %A, i1 true)
-entry:
-  %tobool = icmp eq i64 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i64 [ %0, %cond.true ], [ 63, %entry ]
-  ret i64 %cond
-}
-
-define i32 @test2c(i32 %A) {
-; ALL-LABEL: @test2c(
-; ALL: icmp eq i32 %A, 0
-; ALL: call i32 @llvm.ctlz.i32(i32 %A, i1 true)
-entry:
-  %tobool = icmp eq i32 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i32 [ %0, %cond.true ], [ 31, %entry ]
-  ret i32 %cond
-}
-
-
-define signext i16 @test3c(i16 signext %A) {
-; ALL-LABEL: @test3c(
-; ALL: icmp eq i16 %A, 0
-; ALL: call i16 @llvm.ctlz.i16(i16 %A, i1 true)
-entry:
-  %tobool = icmp eq i16 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i16 [ %0, %cond.true ], [ 15, %entry ]
-  ret i16 %cond
-}
-
-
-define i64 @test1d(i64 %A) {
-; ALL-LABEL: @test1d(
-; ALL: icmp eq i64 %A, 0
-; ALL: call i64 @llvm.cttz.i64(i64 %A, i1 true)
-entry:
-  %tobool = icmp eq i64 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i64 [ %0, %cond.true ], [ 63, %entry ]
-  ret i64 %cond
-}
-
-
-define i32 @test2d(i32 %A) {
-; ALL-LABEL: @test2d(
-; ALL: icmp eq i32 %A, 0
-; ALL: call i32 @llvm.cttz.i32(i32 %A, i1 true)
-entry:
-  %tobool = icmp eq i32 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i32 [ %0, %cond.true ], [ 31, %entry ]
-  ret i32 %cond
-}
-
-
-define signext i16 @test3d(i16 signext %A) {
-; ALL-LABEL: @test3d(
-; ALL: icmp eq i16 %A, 0
-; ALL: call i16 @llvm.cttz.i16(i16 %A, i1 true)
-entry:
-  %tobool = icmp eq i16 %A, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i16 [ %0, %cond.true ], [ 15, %entry ]
-  ret i16 %cond
-}
-
-; The following tests verify that calls to cttz/ctlz are speculated even if
-; basic block %cond.true has an extra zero extend/truncate which is "free"
-; for the target.
-
-define i64 @test1e(i32 %x) {
-; ALL-LABEL: @test1e(
-; LZCNT: icmp eq i32 %x, 0
-; LZCNT: call i32 @llvm.cttz.i32(i32 %x, i1 true)
-; BMI: call i32 @llvm.cttz.i32(i32 %x, i1 false)
-; GENERIC: icmp eq i32 %x, 0
-; GENERIC: call i32 @llvm.cttz.i32(i32 %x, i1 true)
-entry:
-  %tobool = icmp eq i32 %x, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
-  %phitmp2 = zext i32 %0 to i64
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i64 [ %phitmp2, %cond.true ], [ 32, %entry ]
-  ret i64 %cond
-}
-
-define i32 @test2e(i64 %x) {
-; ALL-LABEL: @test2e(
-; LZCNT: icmp eq i64 %x, 0
-; LZCNT: call i64 @llvm.cttz.i64(i64 %x, i1 true)
-; BMI: call i64 @llvm.cttz.i64(i64 %x, i1 false)
-; GENERIC: icmp eq i64 %x, 0
-; GENERIC: call i64 @llvm.cttz.i64(i64 %x, i1 true)
-entry:
-  %tobool = icmp eq i64 %x, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
-  %cast = trunc i64 %0 to i32
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i32 [ %cast, %cond.true ], [ 64, %entry ]
-  ret i32 %cond
-}
-
-define i64 @test3e(i32 %x) {
-; ALL-LABEL: @test3e(
-; BMI: icmp eq i32 %x, 0
-; BMI: call i32 @llvm.ctlz.i32(i32 %x, i1 true)
-; LZCNT: call i32 @llvm.ctlz.i32(i32 %x, i1 false)
-; GENERIC: icmp eq i32 %x, 0
-; GENERIC: call i32 @llvm.ctlz.i32(i32 %x, i1 true)
-entry:
-  %tobool = icmp eq i32 %x, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
-  %phitmp2 = zext i32 %0 to i64
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i64 [ %phitmp2, %cond.true ], [ 32, %entry ]
-  ret i64 %cond
-}
-
-define i32 @test4e(i64 %x) {
-; ALL-LABEL: @test4e(
-; BMI: icmp eq i64 %x, 0
-; BMI: call i64 @llvm.ctlz.i64(i64 %x, i1 true)
-; LZCNT: call i64 @llvm.ctlz.i64(i64 %x, i1 false)
-; GENERIC: icmp eq i64 %x, 0
-; GENERIC: call i64 @llvm.ctlz.i64(i64 %x, i1 true)
-entry:
-  %tobool = icmp eq i64 %x, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
-  %cast = trunc i64 %0 to i32
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i32 [ %cast, %cond.true ], [ 64, %entry ]
-  ret i32 %cond
-}
-
-define i16 @test5e(i64 %x) {
-; ALL-LABEL: @test5e(
-; BMI: icmp eq i64 %x, 0
-; BMI: call i64 @llvm.ctlz.i64(i64 %x, i1 true)
-; LZCNT: call i64 @llvm.ctlz.i64(i64 %x, i1 false)
-; GENERIC: icmp eq i64 %x, 0
-; GENERIC: call i64 @llvm.ctlz.i64(i64 %x, i1 true)
-entry:
-  %tobool = icmp eq i64 %x, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
-  %cast = trunc i64 %0 to i16
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i16 [ %cast, %cond.true ], [ 64, %entry ]
-  ret i16 %cond
-}
-
-define i16 @test6e(i32 %x) {
-; ALL-LABEL: @test6e(
-; BMI: icmp eq i32 %x, 0
-; BMI: call i32 @llvm.ctlz.i32(i32 %x, i1 true)
-; LZCNT: call i32 @llvm.ctlz.i32(i32 %x, i1 false)
-; GENERIC: icmp eq i32 %x, 0
-; GENERIC: call i32 @llvm.ctlz.i32(i32 %x, i1 true)
-entry:
-  %tobool = icmp eq i32 %x, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
-  %cast = trunc i32 %0 to i16
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i16 [ %cast, %cond.true ], [ 32, %entry ]
-  ret i16 %cond
-}
-
-define i16 @test7e(i64 %x) {
-; ALL-LABEL: @test7e(
-; LZCNT: icmp eq i64 %x, 0
-; LZCNT: call i64 @llvm.cttz.i64(i64 %x, i1 true)
-; BMI: call i64 @llvm.cttz.i64(i64 %x, i1 false)
-; GENERIC: icmp eq i64 %x, 0
-; GENERIC: call i64 @llvm.cttz.i64(i64 %x, i1 true)
-entry:
-  %tobool = icmp eq i64 %x, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
-  %cast = trunc i64 %0 to i16
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i16 [ %cast, %cond.true ], [ 64, %entry ]
-  ret i16 %cond
-}
-
-define i16 @test8e(i32 %x) {
-; ALL-LABEL: @test8e(
-; LZCNT: icmp eq i32 %x, 0
-; LZCNT: call i32 @llvm.cttz.i32(i32 %x, i1 true)
-; BMI: call i32 @llvm.cttz.i32(i32 %x, i1 false)
-; GENERIC: icmp eq i32 %x, 0
-; GENERIC: call i32 @llvm.cttz.i32(i32 %x, i1 true)
-entry:
-  %tobool = icmp eq i32 %x, 0
-  br i1 %tobool, label %cond.end, label %cond.true
-
-cond.true:                                        ; preds = %entry
-  %0 = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
-  %cast = trunc i32 %0 to i16
-  br label %cond.end
-
-cond.end:                                         ; preds = %entry, %cond.true
-  %cond = phi i16 [ %cast, %cond.true ], [ 32, %entry ]
-  ret i16 %cond
-}
-
-
-declare i64 @llvm.ctlz.i64(i64, i1)
-declare i32 @llvm.ctlz.i32(i32, i1)
-declare i16 @llvm.ctlz.i16(i16, i1)
-declare i64 @llvm.cttz.i64(i64, i1)
-declare i32 @llvm.cttz.i32(i32, i1)
-declare i16 @llvm.cttz.i16(i16, i1)
diff --git a/test/CodeGen/X86/cvt16.ll b/test/CodeGen/X86/cvt16.ll
index 4d920e2d23d2..5ee399fc137a 100644
--- a/test/CodeGen/X86/cvt16.ll
+++ b/test/CodeGen/X86/cvt16.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c | FileCheck %s -check-prefix=CHECK -check-prefix=LIBCALL
 ; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+f16c | FileCheck %s -check-prefix=CHECK -check-prefix=F16C
-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -soft-float=1 -mattr=-f16c | FileCheck %s -check-prefix=CHECK -check-prefix=SOFTFLOAT
-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -soft-float=1 -mattr=+f16c | FileCheck %s -check-prefix=CHECK -check-prefix=SOFTFLOAT
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c,+soft-float | FileCheck %s -check-prefix=CHECK -check-prefix=SOFTFLOAT
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+f16c,+soft-float | FileCheck %s -check-prefix=CHECK -check-prefix=SOFTFLOAT
 
 ; This is a test for float to half float conversions on x86-64.
 ;
@@ -33,7 +33,7 @@ define void @test1(float %src, i16* %dest) {
 
 
 define float @test2(i16* nocapture %src) {
-  %1 = load i16* %src, align 2
+  %1 = load i16, i16* %src, align 2
   %2 = tail call float @llvm.convert.from.fp16.f32(i16 %1)
   ret float %2
 }
@@ -60,7 +60,7 @@ define float @test3(float %src) nounwind uwtable readnone {
 ; F16C: ret
 
 define double @test4(i16* nocapture %src) {
-  %1 = load i16* %src, align 2
+  %1 = load i16, i16* %src, align 2
   %2 = tail call double @llvm.convert.from.fp16.f64(i16 %1)
   ret double %2
 }
diff --git a/test/CodeGen/X86/dag-optnone.ll b/test/CodeGen/X86/dag-optnone.ll
index 897de31a6fd3..f7774e6e8c54 100644
--- a/test/CodeGen/X86/dag-optnone.ll
+++ b/test/CodeGen/X86/dag-optnone.ll
@@ -63,7 +63,7 @@ entry:
 define void @bar() #1 {
 entry:
   %id83 = alloca <16 x i8>, align 16
-  %0 = load <16 x i32>* @id84, align 64
+  %0 = load <16 x i32>, <16 x i32>* @id84, align 64
   %conv = trunc <16 x i32> %0 to <16 x i8>
   store <16 x i8> %conv, <16 x i8>* %id83, align 16
   ret void
diff --git a/test/CodeGen/X86/dagcombine-and-setcc.ll b/test/CodeGen/X86/dagcombine-and-setcc.ll
index e7336a90dbdd..57adc8bc5daa 100644
--- a/test/CodeGen/X86/dagcombine-and-setcc.ll
+++ b/test/CodeGen/X86/dagcombine-and-setcc.ll
@@ -39,7 +39,7 @@ ret2:
 define i32 @main(i32 %argc, i8** nocapture readnone %argv) {
   %res = alloca i32, align 4
   %t = call i32 @foo(i32 1, i32 2, i32* %res) #3
-  %v = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32 %t)
+  %v = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %t)
   ret i32 0
 }
 
diff --git a/test/CodeGen/X86/dagcombine-buildvector.ll b/test/CodeGen/X86/dagcombine-buildvector.ll
index cf631c353fce..3a6231ade1ab 100644
--- a/test/CodeGen/X86/dagcombine-buildvector.ll
+++ b/test/CodeGen/X86/dagcombine-buildvector.ll
@@ -17,7 +17,7 @@ entry:
 ; CHECK: movdqa
 define void @test2(<4 x i16>* %src, <4 x i32>* %dest) nounwind {
 entry:
-        %tmp1 = load <4 x i16>* %src
+        %tmp1 = load <4 x i16>, <4 x i16>* %src
         %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
         %0 = tail call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3)
         store <4 x i32> %0, <4 x i32>* %dest
diff --git a/test/CodeGen/X86/dagcombine-cse.ll b/test/CodeGen/X86/dagcombine-cse.ll
index 75d3d93ddb89..be1dcff7ae85 100644
--- a/test/CodeGen/X86/dagcombine-cse.ll
+++ b/test/CodeGen/X86/dagcombine-cse.ll
@@ -5,14 +5,14 @@ define i32 @t(i8* %ref_frame_ptr, i32 %ref_frame_stride, i32 %idxX, i32 %idxY) n
 entry:
 	%tmp7 = mul i32 %idxY, %ref_frame_stride		; <i32> [#uses=2]
 	%tmp9 = add i32 %tmp7, %idxX		; <i32> [#uses=1]
-	%tmp11 = getelementptr i8* %ref_frame_ptr, i32 %tmp9		; <i8*> [#uses=1]
+	%tmp11 = getelementptr i8, i8* %ref_frame_ptr, i32 %tmp9		; <i8*> [#uses=1]
 	%tmp1112 = bitcast i8* %tmp11 to i32*		; <i32*> [#uses=1]
-	%tmp13 = load i32* %tmp1112, align 4		; <i32> [#uses=1]
+	%tmp13 = load i32, i32* %tmp1112, align 4		; <i32> [#uses=1]
 	%tmp18 = add i32 %idxX, 4		; <i32> [#uses=1]
 	%tmp20.sum = add i32 %tmp18, %tmp7		; <i32> [#uses=1]
-	%tmp21 = getelementptr i8* %ref_frame_ptr, i32 %tmp20.sum		; <i8*> [#uses=1]
+	%tmp21 = getelementptr i8, i8* %ref_frame_ptr, i32 %tmp20.sum		; <i8*> [#uses=1]
 	%tmp2122 = bitcast i8* %tmp21 to i16*		; <i16*> [#uses=1]
-	%tmp23 = load i16* %tmp2122, align 2		; <i16> [#uses=1]
+	%tmp23 = load i16, i16* %tmp2122, align 2		; <i16> [#uses=1]
 	%tmp2425 = zext i16 %tmp23 to i64		; <i64> [#uses=1]
 	%tmp26 = shl i64 %tmp2425, 32		; <i64> [#uses=1]
 	%tmp2728 = zext i32 %tmp13 to i64		; <i64> [#uses=1]
diff --git a/test/CodeGen/X86/darwin-quote.ll b/test/CodeGen/X86/darwin-quote.ll
index 8fddc118f61e..c912c92e1e8b 100644
--- a/test/CodeGen/X86/darwin-quote.ll
+++ b/test/CodeGen/X86/darwin-quote.ll
@@ -2,7 +2,7 @@
 
 
 define internal i64 @baz() nounwind {
-  %tmp = load i64* @"+x"
+  %tmp = load i64, i64* @"+x"
   ret i64 %tmp
 ; CHECK: _baz:
 ; CHECK:    movl "L_+x$non_lazy_ptr", %ecx
diff --git a/test/CodeGen/X86/darwin-stub.ll b/test/CodeGen/X86/darwin-stub.ll
index b4d2e1aa566d..607f56fdd60b 100644
--- a/test/CodeGen/X86/darwin-stub.ll
+++ b/test/CodeGen/X86/darwin-stub.ll
@@ -5,7 +5,7 @@
 
 define i32 @main() nounwind {
 entry:
-	%0 = tail call i32 @puts(i8* getelementptr ([13 x i8]* @"\01LC", i32 0, i32 0)) nounwind		; <i32> [#uses=0]
+	%0 = tail call i32 @puts(i8* getelementptr ([13 x i8], [13 x i8]* @"\01LC", i32 0, i32 0)) nounwind		; <i32> [#uses=0]
 	ret i32 0
 }
 
diff --git a/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll b/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll
index 16d8f97c3a21..20d0129c3e89 100644
--- a/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll
+++ b/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll
@@ -52,49 +52,49 @@ define void @_Z3barii(i32 %param1, i32 %param2) #0 {
 entry:
   %var1 = alloca %struct.AAA3, align 1
   %var2 = alloca %struct.AAA3, align 1
-  tail call void @llvm.dbg.value(metadata i32 %param1, i64 0, metadata !30, metadata !{!"0x102"}), !dbg !47
-  tail call void @llvm.dbg.value(metadata i32 %param2, i64 0, metadata !31, metadata !{!"0x102"}), !dbg !47
-  tail call void @llvm.dbg.value(metadata i8* null, i64 0, metadata !32, metadata !{!"0x102"}), !dbg !49
+  tail call void @llvm.dbg.value(metadata i32 %param1, i64 0, metadata !30, metadata !DIExpression()), !dbg !47
+  tail call void @llvm.dbg.value(metadata i32 %param2, i64 0, metadata !31, metadata !DIExpression()), !dbg !47
+  tail call void @llvm.dbg.value(metadata i8* null, i64 0, metadata !32, metadata !DIExpression()), !dbg !49
   %tobool = icmp eq i32 %param2, 0, !dbg !50
   br i1 %tobool, label %if.end, label %if.then, !dbg !50
 
 if.then:                                          ; preds = %entry
   %call = tail call i8* @_Z5i2stri(i32 %param2), !dbg !52
-  tail call void @llvm.dbg.value(metadata i8* %call, i64 0, metadata !32, metadata !{!"0x102"}), !dbg !49
+  tail call void @llvm.dbg.value(metadata i8* %call, i64 0, metadata !32, metadata !DIExpression()), !dbg !49
   br label %if.end, !dbg !54
 
 if.end:                                           ; preds = %entry, %if.then
-  tail call void @llvm.dbg.value(metadata %struct.AAA3* %var1, i64 0, metadata !33, metadata !{!"0x102"}), !dbg !55
-  tail call void @llvm.dbg.value(metadata %struct.AAA3* %var1, i64 0, metadata !56, metadata !{!"0x102"}), !dbg !57
-  tail call void @llvm.dbg.value(metadata !58, i64 0, metadata !59, metadata !{!"0x102"}), !dbg !60
-  %arraydecay.i = getelementptr inbounds %struct.AAA3* %var1, i64 0, i32 0, i64 0, !dbg !61
-  call void @_Z3fooPcjPKc(i8* %arraydecay.i, i32 4, i8* getelementptr inbounds ([1 x i8]* @.str, i64 0, i64 0)), !dbg !61
-  call void @llvm.dbg.value(metadata %struct.AAA3* %var2, i64 0, metadata !34, metadata !{!"0x102"}), !dbg !63
-  call void @llvm.dbg.value(metadata %struct.AAA3* %var2, i64 0, metadata !64, metadata !{!"0x102"}), !dbg !65
-  call void @llvm.dbg.value(metadata !58, i64 0, metadata !66, metadata !{!"0x102"}), !dbg !67
-  %arraydecay.i5 = getelementptr inbounds %struct.AAA3* %var2, i64 0, i32 0, i64 0, !dbg !68
-  call void @_Z3fooPcjPKc(i8* %arraydecay.i5, i32 4, i8* getelementptr inbounds ([1 x i8]* @.str, i64 0, i64 0)), !dbg !68
+  tail call void @llvm.dbg.value(metadata %struct.AAA3* %var1, i64 0, metadata !33, metadata !DIExpression()), !dbg !55
+  tail call void @llvm.dbg.value(metadata %struct.AAA3* %var1, i64 0, metadata !56, metadata !DIExpression()), !dbg !57
+  tail call void @llvm.dbg.value(metadata !58, i64 0, metadata !59, metadata !DIExpression()), !dbg !60
+  %arraydecay.i = getelementptr inbounds %struct.AAA3, %struct.AAA3* %var1, i64 0, i32 0, i64 0, !dbg !61
+  call void @_Z3fooPcjPKc(i8* %arraydecay.i, i32 4, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i64 0, i64 0)), !dbg !61
+  call void @llvm.dbg.value(metadata %struct.AAA3* %var2, i64 0, metadata !34, metadata !DIExpression()), !dbg !63
+  call void @llvm.dbg.value(metadata %struct.AAA3* %var2, i64 0, metadata !64, metadata !DIExpression()), !dbg !65
+  call void @llvm.dbg.value(metadata !58, i64 0, metadata !66, metadata !DIExpression()), !dbg !67
+  %arraydecay.i5 = getelementptr inbounds %struct.AAA3, %struct.AAA3* %var2, i64 0, i32 0, i64 0, !dbg !68
+  call void @_Z3fooPcjPKc(i8* %arraydecay.i5, i32 4, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i64 0, i64 0)), !dbg !68
   %tobool1 = icmp eq i32 %param1, 0, !dbg !69
-  call void @llvm.dbg.value(metadata %struct.AAA3* %var2, i64 0, metadata !34, metadata !{!"0x102"}), !dbg !63
+  call void @llvm.dbg.value(metadata %struct.AAA3* %var2, i64 0, metadata !34, metadata !DIExpression()), !dbg !63
   br i1 %tobool1, label %if.else, label %if.then2, !dbg !69
 
 if.then2:                                         ; preds = %if.end
-  call void @llvm.dbg.value(metadata %struct.AAA3* %var2, i64 0, metadata !71, metadata !{!"0x102"}), !dbg !73
-  call void @llvm.dbg.value(metadata !74, i64 0, metadata !75, metadata !{!"0x102"}), !dbg !76
-  call void @_Z3fooPcjPKc(i8* %arraydecay.i5, i32 4, i8* getelementptr inbounds ([2 x i8]* @.str1, i64 0, i64 0)), !dbg !76
+  call void @llvm.dbg.value(metadata %struct.AAA3* %var2, i64 0, metadata !71, metadata !DIExpression()), !dbg !73
+  call void @llvm.dbg.value(metadata !74, i64 0, metadata !75, metadata !DIExpression()), !dbg !76
+  call void @_Z3fooPcjPKc(i8* %arraydecay.i5, i32 4, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str1, i64 0, i64 0)), !dbg !76
   br label %if.end3, !dbg !72
 
 if.else:                                          ; preds = %if.end
-  call void @llvm.dbg.value(metadata %struct.AAA3* %var2, i64 0, metadata !77, metadata !{!"0x102"}), !dbg !79
-  call void @llvm.dbg.value(metadata !80, i64 0, metadata !81, metadata !{!"0x102"}), !dbg !82
-  call void @_Z3fooPcjPKc(i8* %arraydecay.i5, i32 4, i8* getelementptr inbounds ([2 x i8]* @.str2, i64 0, i64 0)), !dbg !82
+  call void @llvm.dbg.value(metadata %struct.AAA3* %var2, i64 0, metadata !77, metadata !DIExpression()), !dbg !79
+  call void @llvm.dbg.value(metadata !80, i64 0, metadata !81, metadata !DIExpression()), !dbg !82
+  call void @_Z3fooPcjPKc(i8* %arraydecay.i5, i32 4, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str2, i64 0, i64 0)), !dbg !82
   br label %if.end3
 
 if.end3:                                          ; preds = %if.else, %if.then2
-  call void @llvm.dbg.value(metadata %struct.AAA3* %var1, i64 0, metadata !33, metadata !{!"0x102"}), !dbg !55
-  call void @llvm.dbg.value(metadata %struct.AAA3* %var1, i64 0, metadata !83, metadata !{!"0x102"}), !dbg !85
-  call void @llvm.dbg.value(metadata !58, i64 0, metadata !86, metadata !{!"0x102"}), !dbg !87
-  call void @_Z3fooPcjPKc(i8* %arraydecay.i, i32 4, i8* getelementptr inbounds ([1 x i8]* @.str, i64 0, i64 0)), !dbg !87
+  call void @llvm.dbg.value(metadata %struct.AAA3* %var1, i64 0, metadata !33, metadata !DIExpression()), !dbg !55
+  call void @llvm.dbg.value(metadata %struct.AAA3* %var1, i64 0, metadata !83, metadata !DIExpression()), !dbg !85
+  call void @llvm.dbg.value(metadata !58, i64 0, metadata !86, metadata !DIExpression()), !dbg !87
+  call void @_Z3fooPcjPKc(i8* %arraydecay.i, i32 4, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i64 0, i64 0)), !dbg !87
   ret void, !dbg !88
 }
 
@@ -113,92 +113,92 @@ attributes #2 = { nounwind readnone }
 !llvm.module.flags = !{!44, !45}
 !llvm.ident = !{!46}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \001\00\000\00\001", !1, !2, !3, !23, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/dbg-changes-codegen-branch-folding.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"dbg-changes-codegen-branch-folding.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !23, globals: !2, imports: !2)
+!1 = !DIFile(filename: "dbg-changes-codegen-branch-folding.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00AAA3\004\0032\008\000\000\000", !1, null, null, !5, null, null, !"_ZTS4AAA3"} ; [ DW_TAG_structure_type ] [AAA3] [line 4, size 32, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "AAA3", line: 4, size: 32, align: 8, file: !1, elements: !5, identifier: "_ZTS4AAA3")
 !5 = !{!6, !11, !17, !18}
-!6 = !{!"0xd\00text\008\0032\008\000\000", !1, !"_ZTS4AAA3", !7} ; [ DW_TAG_member ] [text] [line 8, size 32, align 8, offset 0] [from ]
-!7 = !{!"0x1\00\000\0032\008\000\000", null, null, !8, !9, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 32, align 8, offset 0] [from char]
-!8 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
+!6 = !DIDerivedType(tag: DW_TAG_member, name: "text", line: 8, size: 32, align: 8, file: !1, scope: !"_ZTS4AAA3", baseType: !7)
+!7 = !DICompositeType(tag: DW_TAG_array_type, size: 32, align: 8, baseType: !8, elements: !9)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
 !9 = !{!10}
-!10 = !{!"0x21\000\004"}        ; [ DW_TAG_subrange_type ] [0, 3]
-!11 = !{!"0x2e\00AAA3\00AAA3\00\005\000\000\000\006\00256\001\005", !1, !"_ZTS4AAA3", !12, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 5] [AAA3]
-!12 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !13, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!10 = !DISubrange(count: 4)
+!11 = !DISubprogram(name: "AAA3", line: 5, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !1, scope: !"_ZTS4AAA3", type: !12)
+!12 = !DISubroutineType(types: !13)
 !13 = !{null, !14, !15}
-!14 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS4AAA3"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS4AAA3]
-!15 = !{!"0xf\00\000\0064\0064\000\000", null, null, !16} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!16 = !{!"0x26\00\000\000\000\000\000", null, null, !8} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from char]
-!17 = !{!"0x2e\00operator=\00operator=\00_ZN4AAA3aSEPKc\006\000\000\000\006\00256\001\006", !1, !"_ZTS4AAA3", !12, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 6] [operator=]
-!18 = !{!"0x2e\00operator const char *\00operator const char *\00_ZNK4AAA3cvPKcEv\007\000\000\000\006\00256\001\007", !1, !"_ZTS4AAA3", !19, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 7] [operator const char *]
-!19 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !20, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!14 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS4AAA3")
+!15 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !16)
+!16 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !8)
+!17 = !DISubprogram(name: "operator=", linkageName: "_ZN4AAA3aSEPKc", line: 6, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 6, file: !1, scope: !"_ZTS4AAA3", type: !12)
+!18 = !DISubprogram(name: "operator const char *", linkageName: "_ZNK4AAA3cvPKcEv", line: 7, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 7, file: !1, scope: !"_ZTS4AAA3", type: !19)
+!19 = !DISubroutineType(types: !20)
 !20 = !{!15, !21}
-!21 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !22} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from ]
-!22 = !{!"0x26\00\000\000\000\000\000", null, null, !"_ZTS4AAA3"} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from _ZTS4AAA3]
+!21 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !22)
+!22 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !"_ZTS4AAA3")
 !23 = !{!24, !35, !40}
-!24 = !{!"0x2e\00bar\00bar\00_Z3barii\0011\000\001\000\006\00256\001\0011", !1, !25, !26, null, void (i32, i32)* @_Z3barii, null, null, !29} ; [ DW_TAG_subprogram ] [line 11] [def] [bar]
-!25 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/tmp/dbginfo/dbg-changes-codegen-branch-folding.cpp]
-!26 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !27, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!24 = !DISubprogram(name: "bar", linkageName: "_Z3barii", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !1, scope: !25, type: !26, function: void (i32, i32)* @_Z3barii, variables: !29)
+!25 = !DIFile(filename: "dbg-changes-codegen-branch-folding.cpp", directory: "/tmp/dbginfo")
+!26 = !DISubroutineType(types: !27)
 !27 = !{null, !28, !28}
-!28 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!28 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !29 = !{!30, !31, !32, !33, !34}
-!30 = !{!"0x101\00param1\0016777227\000", !24, !25, !28} ; [ DW_TAG_arg_variable ] [param1] [line 11]
-!31 = !{!"0x101\00param2\0033554443\000", !24, !25, !28} ; [ DW_TAG_arg_variable ] [param2] [line 11]
-!32 = !{!"0x100\00temp\0012\000", !24, !25, !15} ; [ DW_TAG_auto_variable ] [temp] [line 12]
-!33 = !{!"0x100\00var1\0017\000", !24, !25, !"_ZTS4AAA3"} ; [ DW_TAG_auto_variable ] [var1] [line 17]
-!34 = !{!"0x100\00var2\0018\000", !24, !25, !"_ZTS4AAA3"} ; [ DW_TAG_auto_variable ] [var2] [line 18]
-!35 = !{!"0x2e\00operator=\00operator=\00_ZN4AAA3aSEPKc\006\000\001\000\006\00256\001\006", !1, !"_ZTS4AAA3", !12, null, null, null, !17, !36} ; [ DW_TAG_subprogram ] [line 6] [def] [operator=]
+!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "param1", line: 11, arg: 1, scope: !24, file: !25, type: !28)
+!31 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "param2", line: 11, arg: 2, scope: !24, file: !25, type: !28)
+!32 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "temp", line: 12, scope: !24, file: !25, type: !15)
+!33 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "var1", line: 17, scope: !24, file: !25, type: !"_ZTS4AAA3")
+!34 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "var2", line: 18, scope: !24, file: !25, type: !"_ZTS4AAA3")
+!35 = !DISubprogram(name: "operator=", linkageName: "_ZN4AAA3aSEPKc", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 6, file: !1, scope: !"_ZTS4AAA3", type: !12, declaration: !17, variables: !36)
 !36 = !{!37, !39}
-!37 = !{!"0x101\00this\0016777216\001088", !35, null, !38} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!38 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS4AAA3"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS4AAA3]
-!39 = !{!"0x101\00value\0033554438\000", !35, !25, !15} ; [ DW_TAG_arg_variable ] [value] [line 6]
-!40 = !{!"0x2e\00AAA3\00AAA3\00_ZN4AAA3C2EPKc\005\000\001\000\006\00256\001\005", !1, !"_ZTS4AAA3", !12, null, null, null, !11, !41} ; [ DW_TAG_subprogram ] [line 5] [def] [AAA3]
+!37 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !35, type: !38)
+!38 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS4AAA3")
+!39 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "value", line: 6, arg: 2, scope: !35, file: !25, type: !15)
+!40 = !DISubprogram(name: "AAA3", linkageName: "_ZN4AAA3C2EPKc", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !1, scope: !"_ZTS4AAA3", type: !12, declaration: !11, variables: !41)
 !41 = !{!42, !43}
-!42 = !{!"0x101\00this\0016777216\001088", !40, null, !38} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!43 = !{!"0x101\00value\0033554437\000", !40, !25, !15} ; [ DW_TAG_arg_variable ] [value] [line 5]
+!42 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !40, type: !38)
+!43 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "value", line: 5, arg: 2, scope: !40, file: !25, type: !15)
 !44 = !{i32 2, !"Dwarf Version", i32 4}
-!45 = !{i32 2, !"Debug Info Version", i32 2}
+!45 = !{i32 2, !"Debug Info Version", i32 3}
 !46 = !{!"clang version 3.5.0 "}
-!47 = !MDLocation(line: 11, scope: !24)
+!47 = !DILocation(line: 11, scope: !24)
 !48 = !{i8* null}
-!49 = !MDLocation(line: 12, scope: !24)
-!50 = !MDLocation(line: 14, scope: !51)
-!51 = !{!"0xb\0014\000\000", !1, !24} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/dbg-changes-codegen-branch-folding.cpp]
-!52 = !MDLocation(line: 15, scope: !53)
-!53 = !{!"0xb\0014\000\000", !1, !51} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/dbg-changes-codegen-branch-folding.cpp]
-!54 = !MDLocation(line: 16, scope: !53)
-!55 = !MDLocation(line: 17, scope: !24)
-!56 = !{!"0x101\00this\0016777216\001088", !40, null, !38, !55} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!57 = !MDLocation(line: 0, scope: !40, inlinedAt: !55)
-!58 = !{i8* getelementptr inbounds ([1 x i8]* @.str, i64 0, i64 0)}
-!59 = !{!"0x101\00value\0033554437\000", !40, !25, !15, !55} ; [ DW_TAG_arg_variable ] [value] [line 5]
-!60 = !MDLocation(line: 5, scope: !40, inlinedAt: !55)
-!61 = !MDLocation(line: 5, scope: !62, inlinedAt: !55)
-!62 = !{!"0xb\005\000\000", !1, !40} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/dbg-changes-codegen-branch-folding.cpp]
-!63 = !MDLocation(line: 18, scope: !24)
-!64 = !{!"0x101\00this\0016777216\001088", !40, null, !38, !63} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!65 = !MDLocation(line: 0, scope: !40, inlinedAt: !63)
-!66 = !{!"0x101\00value\0033554437\000", !40, !25, !15, !63} ; [ DW_TAG_arg_variable ] [value] [line 5]
-!67 = !MDLocation(line: 5, scope: !40, inlinedAt: !63)
-!68 = !MDLocation(line: 5, scope: !62, inlinedAt: !63)
-!69 = !MDLocation(line: 20, scope: !70)
-!70 = !{!"0xb\0020\000\000", !1, !24} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/dbg-changes-codegen-branch-folding.cpp]
-!71 = !{!"0x101\00this\0016777216\001088", !35, null, !38, !72} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!72 = !MDLocation(line: 21, scope: !70)
-!73 = !MDLocation(line: 0, scope: !35, inlinedAt: !72)
-!74 = !{i8* getelementptr inbounds ([2 x i8]* @.str1, i64 0, i64 0)}
-!75 = !{!"0x101\00value\0033554438\000", !35, !25, !15, !72} ; [ DW_TAG_arg_variable ] [value] [line 6]
-!76 = !MDLocation(line: 6, scope: !35, inlinedAt: !72)
-!77 = !{!"0x101\00this\0016777216\001088", !35, null, !38, !78} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!78 = !MDLocation(line: 23, scope: !70)
-!79 = !MDLocation(line: 0, scope: !35, inlinedAt: !78)
-!80 = !{i8* getelementptr inbounds ([2 x i8]* @.str2, i64 0, i64 0)}
-!81 = !{!"0x101\00value\0033554438\000", !35, !25, !15, !78} ; [ DW_TAG_arg_variable ] [value] [line 6]
-!82 = !MDLocation(line: 6, scope: !35, inlinedAt: !78)
-!83 = !{!"0x101\00this\0016777216\001088", !35, null, !38, !84} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!84 = !MDLocation(line: 24, scope: !24)
-!85 = !MDLocation(line: 0, scope: !35, inlinedAt: !84)
-!86 = !{!"0x101\00value\0033554438\000", !35, !25, !15, !84} ; [ DW_TAG_arg_variable ] [value] [line 6]
-!87 = !MDLocation(line: 6, scope: !35, inlinedAt: !84)
-!88 = !MDLocation(line: 25, scope: !24)
+!49 = !DILocation(line: 12, scope: !24)
+!50 = !DILocation(line: 14, scope: !51)
+!51 = distinct !DILexicalBlock(line: 14, column: 0, file: !1, scope: !24)
+!52 = !DILocation(line: 15, scope: !53)
+!53 = distinct !DILexicalBlock(line: 14, column: 0, file: !1, scope: !51)
+!54 = !DILocation(line: 16, scope: !53)
+!55 = !DILocation(line: 17, scope: !24)
+!56 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !40, type: !38)
+!57 = !DILocation(line: 0, scope: !40, inlinedAt: !55)
+!58 = !{i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i64 0, i64 0)}
+!59 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "value", line: 5, arg: 2, scope: !40, file: !25, type: !15)
+!60 = !DILocation(line: 5, scope: !40, inlinedAt: !55)
+!61 = !DILocation(line: 5, scope: !62, inlinedAt: !55)
+!62 = distinct !DILexicalBlock(line: 5, column: 0, file: !1, scope: !40)
+!63 = !DILocation(line: 18, scope: !24)
+!64 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !40, type: !38)
+!65 = !DILocation(line: 0, scope: !40, inlinedAt: !63)
+!66 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "value", line: 5, arg: 2, scope: !40, file: !25, type: !15)
+!67 = !DILocation(line: 5, scope: !40, inlinedAt: !63)
+!68 = !DILocation(line: 5, scope: !62, inlinedAt: !63)
+!69 = !DILocation(line: 20, scope: !70)
+!70 = distinct !DILexicalBlock(line: 20, column: 0, file: !1, scope: !24)
+!71 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !35, type: !38)
+!72 = !DILocation(line: 21, scope: !70)
+!73 = !DILocation(line: 0, scope: !35, inlinedAt: !72)
+!74 = !{i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str1, i64 0, i64 0)}
+!75 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "value", line: 6, arg: 2, scope: !35, file: !25, type: !15)
+!76 = !DILocation(line: 6, scope: !35, inlinedAt: !72)
+!77 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !35, type: !38)
+!78 = !DILocation(line: 23, scope: !70)
+!79 = !DILocation(line: 0, scope: !35, inlinedAt: !78)
+!80 = !{i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str2, i64 0, i64 0)}
+!81 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "value", line: 6, arg: 2, scope: !35, file: !25, type: !15)
+!82 = !DILocation(line: 6, scope: !35, inlinedAt: !78)
+!83 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !35, type: !38)
+!84 = !DILocation(line: 24, scope: !24)
+!85 = !DILocation(line: 0, scope: !35, inlinedAt: !84)
+!86 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "value", line: 6, arg: 2, scope: !35, file: !25, type: !15)
+!87 = !DILocation(line: 6, scope: !35, inlinedAt: !84)
+!88 = !DILocation(line: 25, scope: !24)
diff --git a/test/CodeGen/X86/dbg-changes-codegen.ll b/test/CodeGen/X86/dbg-changes-codegen.ll
index 2179667245f1..b15e4bd4bf2d 100644
--- a/test/CodeGen/X86/dbg-changes-codegen.ll
+++ b/test/CodeGen/X86/dbg-changes-codegen.ll
@@ -43,8 +43,8 @@
 ; Function Attrs: nounwind readonly uwtable
 define zeroext i1 @_ZN3Foo3batEv(%struct.Foo* %this) #0 align 2 {
 entry:
-  %0 = load %struct.Foo** @pfoo, align 8
-  tail call void @llvm.dbg.value(metadata %struct.Foo* %0, i64 0, metadata !62, metadata !{!"0x102"})
+  %0 = load %struct.Foo*, %struct.Foo** @pfoo, align 8
+  tail call void @llvm.dbg.value(metadata %struct.Foo* %0, i64 0, metadata !62, metadata !DIExpression()), !dbg !DILocation(scope: !DISubprogram())
   %cmp.i = icmp eq %struct.Foo* %0, %this
   ret i1 %cmp.i
 }
@@ -52,9 +52,9 @@ entry:
 ; Function Attrs: nounwind uwtable
 define void @_Z3bazv() #1 {
 entry:
-  %0 = load %struct.Wibble** @wibble1, align 8
-  tail call void @llvm.dbg.value(metadata %struct.Flibble* undef, i64 0, metadata !65, metadata !{!"0x102"})
-  %1 = load %struct.Wibble** @wibble2, align 8
+  %0 = load %struct.Wibble*, %struct.Wibble** @wibble1, align 8
+  tail call void @llvm.dbg.value(metadata %struct.Flibble* undef, i64 0, metadata !65, metadata !DIExpression()), !dbg !DILocation(scope: !DISubprogram())
+  %1 = load %struct.Wibble*, %struct.Wibble** @wibble2, align 8
   %cmp.i = icmp ugt %struct.Wibble* %1, %0
   br i1 %cmp.i, label %if.then.i, label %_ZN7Flibble3barEP6Wibble.exit
 
@@ -63,7 +63,7 @@ if.then.i:                                        ; preds = %entry
   br label %_ZN7Flibble3barEP6Wibble.exit
 
 _ZN7Flibble3barEP6Wibble.exit:                    ; preds = %entry, %if.then.i
-  %x.i = getelementptr inbounds %struct.Wibble* %0, i64 0, i32 0
+  %x.i = getelementptr inbounds %struct.Wibble, %struct.Wibble* %0, i64 0, i32 0
   store i32 0, i32* %x.i, align 4
   ret void
 }
@@ -76,8 +76,8 @@ attributes #1 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointe
 attributes #2 = { nounwind readnone }
 
 
-!17 = !{!"0x10\00\000\000\000\000\000", null, null, null} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from Foo]
-!45 = !{!"0xf\00\000\0064\0064\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from Flibble]
-!62 = !{!"0x101\00arg\0033554436\000", null, null, !17} ; [ DW_TAG_arg_variable ] [arg] [line 4]
+!17 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: null)
+!45 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: null)
+!62 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "arg", line: 4, arg: 2, scope: !DISubprogram(), type: !17)
 !64 = !{%struct.Flibble* undef}
-!65 = !{!"0x101\00this\0016777229\001088", null, null, !45} ; [ DW_TAG_arg_variable ] [this] [line 13]
+!65 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 13, arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !DISubprogram(), type: !45)
diff --git a/test/CodeGen/X86/dbg-combine.ll b/test/CodeGen/X86/dbg-combine.ll
new file mode 100644
index 000000000000..5eb2ea9df513
--- /dev/null
+++ b/test/CodeGen/X86/dbg-combine.ll
@@ -0,0 +1,113 @@
+; RUN: llc -mtriple x86_64-pc-linux -O0 < %s | FileCheck %s
+
+; Make sure that the sequence of debug locations for function foo is correctly
+; generated. More specifically, .loc entries for lines 4,5,6,7 must appear in
+; the correct sequence.
+
+; $ clang -emit-llvm -S -g dbg-combine.c
+; 1.  int foo()
+; 2.  {
+; 3.     int elems = 3;
+; 4.     int array1[elems];
+; 5.     array1[0]=0;
+; 6.     array1[1]=1;
+; 7.     array1[2]=2;
+; 8.     int array2[elems];
+; 9.     array2[0]=1;
+; 10.    return array2[0];
+; 11. }
+
+; CHECK: .loc    1 4
+; CHECK: .loc    1 5
+; CHECK: .loc    1 6
+; CHECK: .loc    1 7
+
+; ModuleID = 'dbg-combine.c'
+; Function Attrs: nounwind uwtable
+define i32 @foo() #0 {
+entry:
+  %elems = alloca i32, align 4
+  %saved_stack = alloca i8*
+  %cleanup.dest.slot = alloca i32
+  call void @llvm.dbg.declare(metadata i32* %elems, metadata !12, metadata !13), !dbg !14
+  store i32 3, i32* %elems, align 4, !dbg !14
+  %0 = load i32, i32* %elems, align 4, !dbg !15
+  %1 = zext i32 %0 to i64, !dbg !16
+  %2 = call i8* @llvm.stacksave(), !dbg !16
+  store i8* %2, i8** %saved_stack, !dbg !16
+  %vla = alloca i32, i64 %1, align 16, !dbg !16
+  call void @llvm.dbg.declare(metadata i32* %vla, metadata !17, metadata !21), !dbg !22
+  %arrayidx = getelementptr inbounds i32, i32* %vla, i64 0, !dbg !23
+  store i32 0, i32* %arrayidx, align 4, !dbg !24
+  %arrayidx1 = getelementptr inbounds i32, i32* %vla, i64 1, !dbg !25
+  store i32 1, i32* %arrayidx1, align 4, !dbg !26
+  %arrayidx2 = getelementptr inbounds i32, i32* %vla, i64 2, !dbg !27
+  store i32 2, i32* %arrayidx2, align 4, !dbg !28
+  %3 = load i32, i32* %elems, align 4, !dbg !29
+  %4 = zext i32 %3 to i64, !dbg !30
+  %vla3 = alloca i32, i64 %4, align 16, !dbg !30
+  call void @llvm.dbg.declare(metadata i32* %vla3, metadata !31, metadata !21), !dbg !32
+  %arrayidx4 = getelementptr inbounds i32, i32* %vla3, i64 0, !dbg !33
+  store i32 1, i32* %arrayidx4, align 4, !dbg !34
+  %arrayidx5 = getelementptr inbounds i32, i32* %vla3, i64 0, !dbg !35
+  %5 = load i32, i32* %arrayidx5, align 4, !dbg !35
+  store i32 1, i32* %cleanup.dest.slot
+  %6 = load i8*, i8** %saved_stack, !dbg !36
+  call void @llvm.stackrestore(i8* %6), !dbg !36
+  ret i32 %5, !dbg !36
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+; Function Attrs: nounwind
+declare i8* @llvm.stacksave() #2
+
+; Function Attrs: nounwind
+declare void @llvm.stackrestore(i8*) #2
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!9, !10}
+!llvm.ident = !{!11}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.7.0 (trunk 227074)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "dbg-combine.c", directory: "/home/probinson/projects/scratch")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !6, function: i32 ()* @foo, variables: !2)
+!5 = !DIFile(filename: "dbg-combine.c", directory: "/home/probinson/projects/scratch")
+!6 = !DISubroutineType(types: !7)
+!7 = !{!8}
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !{i32 2, !"Dwarf Version", i32 4}
+!10 = !{i32 2, !"Debug Info Version", i32 3}
+!11 = !{!"clang version 3.7.0 (trunk 227074)"}
+!12 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "elems", line: 3, scope: !4, file: !5, type: !8)
+!13 = !DIExpression()
+!14 = !DILocation(line: 3, column: 8, scope: !4)
+!15 = !DILocation(line: 4, column: 15, scope: !4)
+!16 = !DILocation(line: 4, column: 4, scope: !4)
+!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "array1", line: 4, scope: !4, file: !5, type: !18)
+!18 = !DICompositeType(tag: DW_TAG_array_type, align: 32, baseType: !8, elements: !19)
+!19 = !{!20}
+!20 = !DISubrange(count: -1)
+!21 = !DIExpression(DW_OP_deref)
+!22 = !DILocation(line: 4, column: 8, scope: !4)
+!23 = !DILocation(line: 5, column: 4, scope: !4)
+!24 = !DILocation(line: 5, column: 13, scope: !4)
+!25 = !DILocation(line: 6, column: 4, scope: !4)
+!26 = !DILocation(line: 6, column: 13, scope: !4)
+!27 = !DILocation(line: 7, column: 4, scope: !4)
+!28 = !DILocation(line: 7, column: 13, scope: !4)
+!29 = !DILocation(line: 8, column: 15, scope: !4)
+!30 = !DILocation(line: 8, column: 4, scope: !4)
+!31 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "array2", line: 8, scope: !4, file: !5, type: !18)
+!32 = !DILocation(line: 8, column: 8, scope: !4)
+!33 = !DILocation(line: 9, column: 4, scope: !4)
+!34 = !DILocation(line: 9, column: 13, scope: !4)
+!35 = !DILocation(line: 10, column: 11, scope: !4)
+!36 = !DILocation(line: 11, column: 1, scope: !4)
diff --git a/test/CodeGen/X86/discontiguous-loops.ll b/test/CodeGen/X86/discontiguous-loops.ll
index 479c450ca20f..20db750d206b 100644
--- a/test/CodeGen/X86/discontiguous-loops.ll
+++ b/test/CodeGen/X86/discontiguous-loops.ll
@@ -39,8 +39,8 @@ ybb8:                                              ; preds = %ybb1
   br i1 %tmp9, label %bb10, label %ybb12
 
 bb10:                                             ; preds = %ybb8
-  %tmp11 = load i8** undef, align 8               ; <i8*> [#uses=1]
-  call void (i8*, ...)* @fatal(i8* getelementptr inbounds ([37 x i8]* @.str96, i64 0, i64 0), i8* %tmp11) nounwind
+  %tmp11 = load i8*, i8** undef, align 8               ; <i8*> [#uses=1]
+  call void (i8*, ...) @fatal(i8* getelementptr inbounds ([37 x i8], [37 x i8]* @.str96, i64 0, i64 0), i8* %tmp11) nounwind
   unreachable
 
 ybb12:                                             ; preds = %ybb8
@@ -51,7 +51,7 @@ ybb13:                                             ; preds = %ybb12
   br i1 %tmp14, label %bb16, label %ybb1
 
 bb15:                                             ; preds = %ybb12
-  call void (i8*, ...)* @fatal(i8* getelementptr inbounds ([37 x i8]* @.str96, i64 0, i64 0), i8* undef) nounwind
+  call void (i8*, ...) @fatal(i8* getelementptr inbounds ([37 x i8], [37 x i8]* @.str96, i64 0, i64 0), i8* undef) nounwind
   unreachable
 
 bb16:                                             ; preds = %ybb13
diff --git a/test/CodeGen/X86/div8.ll b/test/CodeGen/X86/div8.ll
index 0825f79e3240..f4f50e5a494c 100644
--- a/test/CodeGen/X86/div8.ll
+++ b/test/CodeGen/X86/div8.ll
@@ -10,13 +10,13 @@ entry:
   %quotient = alloca i8, align 1
   store i8 %dividend, i8* %dividend.addr, align 2
   store i8 %divisor, i8* %divisor.addr, align 1
-  %tmp = load i8* %dividend.addr, align 2
-  %tmp1 = load i8* %divisor.addr, align 1
+  %tmp = load i8, i8* %dividend.addr, align 2
+  %tmp1 = load i8, i8* %divisor.addr, align 1
 ; Insist on i8->i32 zero extension, even though divb demands only i16:
 ; CHECK: movzbl {{.*}}%eax
 ; CHECK: divb
   %div = udiv i8 %tmp, %tmp1
   store i8 %div, i8* %quotient, align 1
-  %tmp4 = load i8* %quotient, align 1
+  %tmp4 = load i8, i8* %quotient, align 1
   ret i8 %tmp4
 }
diff --git a/test/CodeGen/X86/dllexport-x86_64.ll b/test/CodeGen/X86/dllexport-x86_64.ll
index cf4557d12716..629a5572977f 100644
--- a/test/CodeGen/X86/dllexport-x86_64.ll
+++ b/test/CodeGen/X86/dllexport-x86_64.ll
@@ -17,19 +17,16 @@ define dllexport void @f2() unnamed_addr {
 	ret void
 }
 
-; CHECK: .section .text,"xr",discard,lnk1
 ; CHECK: .globl lnk1
 define linkonce_odr dllexport void @lnk1() {
 	ret void
 }
 
-; CHECK: .section .text,"xr",discard,lnk2
 ; CHECK: .globl lnk2
 define linkonce_odr dllexport void @lnk2() alwaysinline {
 	ret void
 }
 
-; CHECK: .section .text,"xr",discard,weak1
 ; CHECK: .globl weak1
 define weak_odr dllexport void @weak1() {
 	ret void
@@ -47,11 +44,9 @@ define weak_odr dllexport void @weak1() {
 ; CHECK: .comm Var3
 @Var3 = common dllexport global i32 0, align 4
 
-; CHECK: .section .data,"dw",discard,WeakVar1
 ; CHECK: .globl WeakVar1
 @WeakVar1 = weak_odr dllexport global i32 1, align 4
 
-; CHECK: .section .rdata,"dr",discard,WeakVar2
 ; CHECK: .globl WeakVar2
 @WeakVar2 = weak_odr dllexport unnamed_addr constant i32 1
 
diff --git a/test/CodeGen/X86/dllexport.ll b/test/CodeGen/X86/dllexport.ll
index 145b48aaf635..02a83ae7b191 100644
--- a/test/CodeGen/X86/dllexport.ll
+++ b/test/CodeGen/X86/dllexport.ll
@@ -38,19 +38,16 @@ define dllexport x86_thiscallcc void @thisfun() nounwind {
 	ret void
 }
 
-; CHECK: .section .text,"xr",discard,_lnk1
 ; CHECK: .globl _lnk1
 define linkonce_odr dllexport void @lnk1() {
 	ret void
 }
 
-; CHECK: .section .text,"xr",discard,_lnk2
 ; CHECK: .globl _lnk2
 define linkonce_odr dllexport void @lnk2() alwaysinline {
 	ret void
 }
 
-; CHECK: .section .text,"xr",discard,_weak1
 ; CHECK: .globl _weak1
 define weak_odr dllexport void @weak1() {
 	ret void
@@ -68,11 +65,9 @@ define weak_odr dllexport void @weak1() {
 ; CHECK: .comm _Var3
 @Var3 = common dllexport global i32 0, align 4
 
-; CHECK: .section .data,"dw",discard,_WeakVar1
 ; CHECK: .globl _WeakVar1
 @WeakVar1 = weak_odr dllexport global i32 1, align 4
 
-; CHECK: .section .rdata,"dr",discard,_WeakVar2
 ; CHECK: .globl _WeakVar2
 @WeakVar2 = weak_odr dllexport unnamed_addr constant i32 1
 
diff --git a/test/CodeGen/X86/dllimport-x86_64.ll b/test/CodeGen/X86/dllimport-x86_64.ll
index 839bca4f3c31..7ee6b4323d15 100644
--- a/test/CodeGen/X86/dllimport-x86_64.ll
+++ b/test/CodeGen/X86/dllimport-x86_64.ll
@@ -35,14 +35,14 @@ define void @use() nounwind {
 ; available_externally uses go away
 ; OPT-NOT: call void @inline1()
 ; OPT-NOT: call void @inline2()
-; OPT-NOT: load i32* @Var2
-; OPT: call void (...)* @dummy(i32 %1, i32 1)
+; OPT-NOT: load i32, i32* @Var2
+; OPT: call void (...) @dummy(i32 %1, i32 1)
 
 ; CHECK-DAG: movq __imp_Var1(%rip), [[R1:%[a-z]{3}]]
 ; CHECK-DAG: movq __imp_Var2(%rip), [[R2:%[a-z]{3}]]
-  %1 = load i32* @Var1
-  %2 = load i32* @Var2
-  call void(...)* @dummy(i32 %1, i32 %2)
+  %1 = load i32, i32* @Var1
+  %2 = load i32, i32* @Var2
+  call void(...) @dummy(i32 %1, i32 %2)
 
   ret void
 }
diff --git a/test/CodeGen/X86/dllimport.ll b/test/CodeGen/X86/dllimport.ll
index 231ad65740b8..9db654f22712 100644
--- a/test/CodeGen/X86/dllimport.ll
+++ b/test/CodeGen/X86/dllimport.ll
@@ -46,14 +46,14 @@ define void @use() nounwind {
 ; available_externally uses go away
 ; OPT-NOT: call void @inline1()
 ; OPT-NOT: call void @inline2()
-; OPT-NOT: load i32* @Var2
-; OPT: call void (...)* @dummy(i32 %1, i32 1)
+; OPT-NOT: load i32, i32* @Var2
+; OPT: call void (...) @dummy(i32 %1, i32 1)
 
 ; CHECK-DAG: movl __imp__Var1, [[R1:%[a-z]{3}]]
 ; CHECK-DAG: movl __imp__Var2, [[R2:%[a-z]{3}]]
-  %1 = load i32* @Var1
-  %2 = load i32* @Var2
-  call void(...)* @dummy(i32 %1, i32 %2)
+  %1 = load i32, i32* @Var1
+  %2 = load i32, i32* @Var2
+  call void(...) @dummy(i32 %1, i32 %2)
 
   ret void
 }
diff --git a/test/CodeGen/X86/dollar-name.ll b/test/CodeGen/X86/dollar-name.ll
index 2ecd72909cb1..a31b806c031f 100644
--- a/test/CodeGen/X86/dollar-name.ll
+++ b/test/CodeGen/X86/dollar-name.ll
@@ -8,8 +8,8 @@ define i32 @"$foo"() nounwind {
 ; CHECK: movl	($bar),
 ; CHECK: addl	($qux),
 ; CHECK: calll	($hen)
-  %m = load i32* @"$bar"
-  %n = load i32* @"$qux"
+  %m = load i32, i32* @"$bar"
+  %n = load i32, i32* @"$qux"
   %t = add i32 %m, %n
   %u = call i32 @"$hen"(i32 %t)
   ret i32 %u
diff --git a/test/CodeGen/X86/dont-trunc-store-double-to-float.ll b/test/CodeGen/X86/dont-trunc-store-double-to-float.ll
index 24d9533eba4a..8a334d21631a 100644
--- a/test/CodeGen/X86/dont-trunc-store-double-to-float.ll
+++ b/test/CodeGen/X86/dont-trunc-store-double-to-float.ll
@@ -10,7 +10,7 @@ entry-block:
   %b = alloca float
 
   store double 3.140000e+00, double* %a
-  %0 = load double* %a
+  %0 = load double, double* %a
 
   %1 = fptrunc double %0 to float
 
diff --git a/test/CodeGen/X86/dwarf-comp-dir.ll b/test/CodeGen/X86/dwarf-comp-dir.ll
index 77eba63a83ec..27b8b1552ec1 100644
--- a/test/CodeGen/X86/dwarf-comp-dir.ll
+++ b/test/CodeGen/X86/dwarf-comp-dir.ll
@@ -7,15 +7,15 @@ target triple = "x86_64-unknown-linux-gnu"
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!5}
 
-!0 = !{!"0x11\0012\00clang version 3.1 (trunk 143523)\001\00\000\00\000", !4, !2, !7, !2, !2, null} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.1 (trunk 143523)", isOptimized: true, emissionKind: 0, file: !4, enums: !2, retainedTypes: !7, subprograms: !2, globals: !2)
 !2 = !{}
-!3 = !{!"0x29", !4} ; [ DW_TAG_file_type ]
-!4 = !{!"empty.c", !"/home/nlewycky"}
-!6 = !{!"0x13\00foo\001\008\008\000\000\000", !4, null, null, !2, null, null, !"_ZTS3foo"} ; [ DW_TAG_structure_type ] [foo] [line 1, size 8, align 8, offset 0] [def] [from ]
+!3 = !DIFile(filename: "empty.c", directory: "/home/nlewycky")
+!4 = !DIFile(filename: "empty.c", directory: "/home/nlewycky")
+!6 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo", line: 1, size: 8, align: 8, file: !4, elements: !2, identifier: "_ZTS3foo")
 !7 = !{!6}
 
 ; The important part of the following check is that dir = #0.
 ;                        Dir  Mod Time   File Len   File Name
 ;                        ---- ---------- ---------- ---------------------------
 ; CHECK: file_names[  1]    0 0x00000000 0x00000000 empty.c
-!5 = !{i32 1, !"Debug Info Version", i32 2}
+!5 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/dwarf-eh-prepare.ll b/test/CodeGen/X86/dwarf-eh-prepare.ll
new file mode 100644
index 000000000000..25572d868da0
--- /dev/null
+++ b/test/CodeGen/X86/dwarf-eh-prepare.ll
@@ -0,0 +1,158 @@
+; RUN: opt -mtriple=x86_64-linux-gnu -dwarfehprepare < %s -S | FileCheck %s
+
+; Check basic functionality of IR-to-IR DWARF EH preparation. This should
+; eliminate resumes. This pass requires a TargetMachine, so we put it under X86
+; and provide an x86 triple.
+
+@int_typeinfo = global i8 0
+
+declare void @might_throw()
+declare void @cleanup()
+
+define i32 @simple_cleanup_catch() {
+  invoke void @might_throw()
+          to label %cont unwind label %lpad
+
+; CHECK-LABEL: define i32 @simple_cleanup_catch()
+; CHECK: invoke void @might_throw()
+
+cont:
+  ret i32 0
+
+; CHECK: ret i32 0
+
+lpad:
+  %ehvals = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
+      cleanup
+      catch i8* @int_typeinfo
+  %ehptr = extractvalue { i8*, i32 } %ehvals, 0
+  %ehsel = extractvalue { i8*, i32 } %ehvals, 1
+  call void @cleanup()
+  %int_sel = call i32 @llvm.eh.typeid.for(i8* @int_typeinfo)
+  %int_match = icmp eq i32 %ehsel, %int_sel
+  br i1 %int_match, label %catch_int, label %eh.resume
+
+; CHECK: lpad:
+; CHECK: landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
+; CHECK: call void @cleanup()
+; CHECK: call i32 @llvm.eh.typeid.for
+; CHECK: br i1
+
+catch_int:
+  ret i32 1
+
+; CHECK: catch_int:
+; CHECK: ret i32 1
+
+eh.resume:
+  %tmp_ehvals = insertvalue { i8*, i32 } undef, i8* %ehptr, 0
+  %new_ehvals = insertvalue { i8*, i32 } %tmp_ehvals, i32 %ehsel, 1
+  resume { i8*, i32 } %new_ehvals
+
+; CHECK: eh.resume:
+; CHECK-NEXT: call void @_Unwind_Resume(i8* %ehptr)
+}
+
+
+define i32 @catch_no_resume() {
+  invoke void @might_throw()
+          to label %cont unwind label %lpad
+
+cont:
+  ret i32 0
+
+lpad:
+  %ehvals = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
+      catch i8* @int_typeinfo
+  %ehptr = extractvalue { i8*, i32 } %ehvals, 0
+  %ehsel = extractvalue { i8*, i32 } %ehvals, 1
+  %int_sel = call i32 @llvm.eh.typeid.for(i8* @int_typeinfo)
+  %int_match = icmp eq i32 %ehsel, %int_sel
+  br i1 %int_match, label %catch_int, label %eh.resume
+
+catch_int:
+  ret i32 1
+
+eh.resume:
+  %tmp_ehvals = insertvalue { i8*, i32 } undef, i8* %ehptr, 0
+  %new_ehvals = insertvalue { i8*, i32 } %tmp_ehvals, i32 %ehsel, 1
+  resume { i8*, i32 } %new_ehvals
+}
+
+; Check that we can prune the unreachable resume instruction.
+
+; CHECK-LABEL: define i32 @catch_no_resume() {
+; CHECK: invoke void @might_throw()
+; CHECK: ret i32 0
+; CHECK: lpad:
+; CHECK: landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
+; CHECK-NOT: br i1
+; CHECK: ret i32 1
+; CHECK-NOT: call void @_Unwind_Resume
+; CHECK: {{^[}]}}
+
+
+define i32 @catch_cleanup_merge() {
+  invoke void @might_throw()
+          to label %inner_invoke unwind label %outer_lpad
+inner_invoke:
+  invoke void @might_throw()
+          to label %cont unwind label %inner_lpad
+cont:
+  ret i32 0
+
+outer_lpad:
+  %ehvals1 = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
+      catch i8* @int_typeinfo
+  br label %catch.dispatch
+
+inner_lpad:
+  %ehvals2 = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
+      cleanup
+      catch i8* @int_typeinfo
+  call void @cleanup()
+  br label %catch.dispatch
+
+catch.dispatch:
+  %ehvals = phi { i8*, i32 } [ %ehvals1, %outer_lpad ], [ %ehvals2, %inner_lpad ]
+  %ehptr = extractvalue { i8*, i32 } %ehvals, 0
+  %ehsel = extractvalue { i8*, i32 } %ehvals, 1
+  %int_sel = call i32 @llvm.eh.typeid.for(i8* @int_typeinfo)
+  %int_match = icmp eq i32 %ehsel, %int_sel
+  br i1 %int_match, label %catch_int, label %eh.resume
+
+catch_int:
+  ret i32 1
+
+eh.resume:
+  %tmp_ehvals = insertvalue { i8*, i32 } undef, i8* %ehptr, 0
+  %new_ehvals = insertvalue { i8*, i32 } %tmp_ehvals, i32 %ehsel, 1
+  resume { i8*, i32 } %new_ehvals
+}
+
+; We can't prune this merge because one landingpad is a cleanup pad.
+
+; CHECK-LABEL: define i32 @catch_cleanup_merge()
+; CHECK: invoke void @might_throw()
+; CHECK: invoke void @might_throw()
+; CHECK: ret i32 0
+;
+; CHECK: outer_lpad:
+; CHECK: landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
+; CHECK: br label %catch.dispatch
+;
+; CHECK: inner_lpad:
+; CHECK: landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
+; CHECK: call void @cleanup()
+; CHECK: br label %catch.dispatch
+;
+; CHECK: catch.dispatch:
+; CHECK: call i32 @llvm.eh.typeid.for
+; CHECK: br i1
+; CHECK: catch_int:
+; CHECK: ret i32 1
+; CHECK: eh.resume:
+; CHECK-NEXT: call void @_Unwind_Resume(i8* %ehptr)
+
+declare i32 @__gxx_personality_v0(...)
+declare i32 @llvm.eh.typeid.for(i8*)
diff --git a/test/CodeGen/X86/dynamic-alloca-lifetime.ll b/test/CodeGen/X86/dynamic-alloca-lifetime.ll
index f019bed858c2..034b074ef9bd 100644
--- a/test/CodeGen/X86/dynamic-alloca-lifetime.ll
+++ b/test/CodeGen/X86/dynamic-alloca-lifetime.ll
@@ -29,10 +29,10 @@ end1:
   ret void
 
 if.else130:                                       ; preds = %bb1
-  %tmp = getelementptr inbounds [8192 x i8]* %bitmapBuffer, i32 0, i32 0
+  %tmp = getelementptr inbounds [8192 x i8], [8192 x i8]* %bitmapBuffer, i32 0, i32 0
   call void @llvm.lifetime.start(i64 8192, i8* %tmp) #0
   call void @llvm.lifetime.end(i64 8192, i8* %tmp) #0
-  %tmp25 = getelementptr inbounds [8192 x i8]* %bitmapBuffer229, i32 0, i32 0
+  %tmp25 = getelementptr inbounds [8192 x i8], [8192 x i8]* %bitmapBuffer229, i32 0, i32 0
   call void @llvm.lifetime.start(i64 8192, i8* %tmp25) #0
   call void @llvm.lifetime.end(i64 8192, i8* %tmp25) #0
   br label %end1
diff --git a/test/CodeGen/X86/dynamic-allocas-VLAs.ll b/test/CodeGen/X86/dynamic-allocas-VLAs.ll
index 9405f76cbed0..2925f243b0e3 100644
--- a/test/CodeGen/X86/dynamic-allocas-VLAs.ll
+++ b/test/CodeGen/X86/dynamic-allocas-VLAs.ll
@@ -7,7 +7,7 @@ define i32 @t1() nounwind uwtable ssp {
 entry:
   %a = alloca i32, align 4
   call void @t1_helper(i32* %a) nounwind
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %add = add nsw i32 %0, 13
   ret i32 %add
 
@@ -27,7 +27,7 @@ entry:
   %a = alloca i32, align 4
   %v = alloca <8 x float>, align 32
   call void @t2_helper(i32* %a, <8 x float>* %v) nounwind
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %add = add nsw i32 %0, 13
   ret i32 %add
 
@@ -53,7 +53,7 @@ entry:
   %a = alloca i32, align 4
   %vla = alloca i32, i64 %sz, align 16
   call void @t3_helper(i32* %a, i32* %vla) nounwind
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %add = add nsw i32 %0, 13
   ret i32 %add
 
@@ -78,7 +78,7 @@ entry:
   %v = alloca <8 x float>, align 32
   %vla = alloca i32, i64 %sz, align 16
   call void @t4_helper(i32* %a, i32* %vla, <8 x float>* %v) nounwind
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %add = add nsw i32 %0, 13
   ret i32 %add
 
@@ -108,10 +108,10 @@ define i32 @t5(float* nocapture %f) nounwind uwtable ssp {
 entry:
   %a = alloca i32, align 4
   %0 = bitcast float* %f to <8 x float>*
-  %1 = load <8 x float>* %0, align 32
+  %1 = load <8 x float>, <8 x float>* %0, align 32
   call void @t5_helper1(i32* %a) nounwind
   call void @t5_helper2(<8 x float> %1) nounwind
-  %2 = load i32* %a, align 4
+  %2 = load i32, i32* %a, align 4
   %add = add nsw i32 %2, 13
   ret i32 %add
 
@@ -138,11 +138,11 @@ entry:
 ; CHECK: _t6
   %a = alloca i32, align 4
   %0 = bitcast float* %f to <8 x float>*
-  %1 = load <8 x float>* %0, align 32
+  %1 = load <8 x float>, <8 x float>* %0, align 32
   %vla = alloca i32, i64 %sz, align 16
   call void @t6_helper1(i32* %a, i32* %vla) nounwind
   call void @t6_helper2(<8 x float> %1) nounwind
-  %2 = load i32* %a, align 4
+  %2 = load i32, i32* %a, align 4
   %add = add nsw i32 %2, 13
   ret i32 %add
 }
@@ -162,7 +162,7 @@ entry:
   store i32 0, i32* %x, align 32
   %0 = zext i32 %size to i64
   %vla = alloca i32, i64 %0, align 16
-  %1 = load i32* %x, align 32
+  %1 = load i32, i32* %x, align 32
   call void @bar(i32 %1, i32* %vla, %struct.struct_t* byval align 8 %arg1)
   ret void
 
@@ -195,7 +195,7 @@ define i32 @t8() nounwind uwtable {
 entry:
   %a = alloca i32, align 4
   call void @t1_helper(i32* %a) nounwind
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %add = add nsw i32 %0, 13
   ret i32 %add
 
@@ -213,7 +213,7 @@ entry:
   %a = alloca i32, align 4
   %vla = alloca i32, i64 %sz, align 16
   call void @t3_helper(i32* %a, i32* %vla) nounwind
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %add = add nsw i32 %0, 13
   ret i32 %add
 
diff --git a/test/CodeGen/X86/early-ifcvt.ll b/test/CodeGen/X86/early-ifcvt.ll
index 2606bd28d5fc..7fcd530b62aa 100644
--- a/test/CodeGen/X86/early-ifcvt.ll
+++ b/test/CodeGen/X86/early-ifcvt.ll
@@ -14,8 +14,8 @@ do.body:
   %min.0 = phi i32 [ 0, %entry ], [ %min.1, %do.cond ]
   %n.addr.0 = phi i32 [ %n, %entry ], [ %dec, %do.cond ]
   %p.addr.0 = phi i32* [ %p, %entry ], [ %incdec.ptr, %do.cond ]
-  %incdec.ptr = getelementptr inbounds i32* %p.addr.0, i64 1
-  %0 = load i32* %p.addr.0, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %p.addr.0, i64 1
+  %0 = load i32, i32* %p.addr.0, align 4
   %cmp = icmp sgt i32 %0, %max.0
   br i1 %cmp, label %do.cond, label %if.else
 
@@ -62,7 +62,7 @@ if.then37:
 
 if.end41:
   %exit_status.0 = phi i32 [ 2, %if.then29 ], [ 0, %if.then37 ], [ 66, %entry ]
-  call void (...)* @fprintf(i32 %exit_status.0) nounwind
+  call void (...) @fprintf(i32 %exit_status.0) nounwind
   unreachable
 }
 
@@ -108,7 +108,7 @@ if.end2042:                                       ; preds = %while.body2038
   br i1 undef, label %if.end2048, label %while.end2104
 
 if.end2048:                                       ; preds = %if.end2042
-  %bsLive2054.pre = getelementptr inbounds i8* %s, i32 8
+  %bsLive2054.pre = getelementptr inbounds i8, i8* %s, i32 8
   br label %sw.bb2050
 
 sw.bb2050:                                        ; preds = %if.end2048, %if.end.sw.bb2050_crit_edge
diff --git a/test/CodeGen/X86/eh-label.ll b/test/CodeGen/X86/eh-label.ll
new file mode 100644
index 000000000000..aff0bcfffcfe
--- /dev/null
+++ b/test/CodeGen/X86/eh-label.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s
+; Test that we don't crashe if the .Lfunc_end0 name is taken.
+
+declare void @g()
+
+define void @f() {
+bb0:
+  call void asm ".Lfunc_end0:", ""()
+; CHECK: #APP
+; CHECK-NEXT: .Lfunc_end0:
+; CHECK-NEXT: #NO_APP
+
+  invoke void @g() to label %bb2 unwind label %bb1
+bb1:
+  landingpad { i8*, i32 } personality i8* bitcast (void ()* @g to i8*)
+          catch i8* null
+  call void @g()
+  ret void
+bb2:
+  ret void
+
+; CHECK: [[END:.Lfunc_end.*]]:
+; CHECK: .long	[[END]]-
+}
diff --git a/test/CodeGen/X86/emit-big-cst.ll b/test/CodeGen/X86/emit-big-cst.ll
index 96c15d4a3658..51852d00f823 100644
--- a/test/CodeGen/X86/emit-big-cst.ll
+++ b/test/CodeGen/X86/emit-big-cst.ll
@@ -10,7 +10,7 @@
 
 define void @accessBig(i64* %storage) {
   %addr = bitcast i64* %storage to i82*
-  %bigLoadedCst = load volatile i82* @bigCst
+  %bigLoadedCst = load volatile i82, i82* @bigCst
   %tmp = add i82 %bigLoadedCst, 1
   store i82 %tmp, i82* %addr
   ret void
diff --git a/test/CodeGen/X86/empty-functions.ll b/test/CodeGen/X86/empty-functions.ll
index 42349688a710..735df2a4196d 100644
--- a/test/CodeGen/X86/empty-functions.ll
+++ b/test/CodeGen/X86/empty-functions.ll
@@ -50,5 +50,5 @@ entry:
 ; LINUX-FP-NEXT:{{^}}.L{{.*}}:{{$}}
 ; LINUX-FP-NEXT: .cfi_def_cfa_register %rbp
 ; LINUX-FP-NEXT:{{^}}.L{{.*}}:{{$}}
-; LINUX-FP-NEXT: .size   func, .Ltmp3-func
+; LINUX-FP-NEXT: .size   func, .Lfunc_end0-func
 ; LINUX-FP-NEXT: .cfi_endproc
diff --git a/test/CodeGen/X86/exception-label.ll b/test/CodeGen/X86/exception-label.ll
new file mode 100644
index 000000000000..cafa1e630b96
--- /dev/null
+++ b/test/CodeGen/X86/exception-label.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s
+
+; Test that we can handle .Lexception0 being defined. We used to crash.
+
+; CHECK: .cfi_lsda 3, [[LABEL:.*]]
+; CHECK: [[LABEL]]:
+; CHECK-NEXT: .byte   255                     # @LPStart Encoding = omit
+
+declare void @g()
+
+define void @f() {
+bb0:
+  call void asm ".Lexception0:", ""()
+  invoke void @g()
+          to label %bb2 unwind label %bb1
+bb1:
+  landingpad { i8*, i32 } personality i8* bitcast (void ()* @g to i8*)
+          catch i8* null
+  br label %bb2
+
+bb2:
+  ret void
+}
diff --git a/test/CodeGen/X86/exedeps-movq.ll b/test/CodeGen/X86/exedeps-movq.ll
new file mode 100644
index 000000000000..a5873be6f27f
--- /dev/null
+++ b/test/CodeGen/X86/exedeps-movq.ll
@@ -0,0 +1,68 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=AVX
+
+; Verify that we select the correct version of the instruction that stores the low 64-bits
+; of a 128-bit vector. We want to avoid int/fp domain crossing penalties, so ignore the
+; bitcast ops and choose:
+;
+; movlps for floats
+; movlpd for doubles
+; movq for integers
+
+define void @store_floats(<4 x float> %x, i64* %p) {
+; SSE-LABEL: store_floats:
+; SSE:       # BB#0:
+; SSE-NEXT:    addps %xmm0, %xmm0
+; SSE-NEXT:    movlps %xmm0, (%rdi)
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: store_floats:
+; AVX:       # BB#0:
+; AVX-NEXT:    vaddps %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vmovlps %xmm0, (%rdi)
+; AVX-NEXT:    retq
+  %a = fadd <4 x float> %x, %x
+  %b = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  %c = bitcast <2 x float> %b to i64
+  store i64 %c, i64* %p
+  ret void
+}
+
+define void @store_double(<2 x double> %x, i64* %p) {
+; SSE-LABEL: store_double:
+; SSE:       # BB#0:
+; SSE-NEXT:    addpd %xmm0, %xmm0
+; SSE-NEXT:    movlpd %xmm0, (%rdi)
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: store_double:
+; AVX:       # BB#0:
+; AVX-NEXT:    vaddpd %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vmovlpd %xmm0, (%rdi)
+; AVX-NEXT:    retq
+  %a = fadd <2 x double> %x, %x
+  %b = extractelement <2 x double> %a, i32 0
+  %c = bitcast double %b to i64
+  store i64 %c, i64* %p
+  ret void
+}
+
+define void @store_int(<4 x i32> %x, <2 x float>* %p) {
+; SSE-LABEL: store_int:
+; SSE:       # BB#0:
+; SSE-NEXT:    paddd %xmm0, %xmm0
+; SSE-NEXT:    movq %xmm0, (%rdi)
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: store_int:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpaddd %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vmovq %xmm0, (%rdi)
+; AVX-NEXT:    retq
+  %a = add <4 x i32> %x, %x
+  %b = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
+  %c = bitcast <2 x i32> %b to <2 x float>
+  store <2 x float> %c, <2 x float>* %p
+  ret void
+}
+
diff --git a/test/CodeGen/X86/expand-opaque-const.ll b/test/CodeGen/X86/expand-opaque-const.ll
index 6e461cf8c30b..1e39cd88308c 100644
--- a/test/CodeGen/X86/expand-opaque-const.ll
+++ b/test/CodeGen/X86/expand-opaque-const.ll
@@ -11,11 +11,11 @@ entry:
   %op2 = alloca i64
   store i64 -6687208052682386272, i64* %op1
   store i64 7106745059734980448, i64* %op2
-  %tmp1 = load i64* %op1
-  %tmp2 = load i64* %op2
+  %tmp1 = load i64, i64* %op1
+  %tmp2 = load i64, i64* %op2
   %tmp = xor i64 %tmp2, 7106745059734980448
   %tmp3 = lshr i64 %tmp1, %tmp
   store i64 %tmp3, i64* %retval
-  %tmp4 = load i64* %retval
+  %tmp4 = load i64, i64* %retval
   ret i64 %tmp4
 }
diff --git a/test/CodeGen/X86/extend.ll b/test/CodeGen/X86/extend.ll
index 9553b1b578b1..d349e782d5d0 100644
--- a/test/CodeGen/X86/extend.ll
+++ b/test/CodeGen/X86/extend.ll
@@ -5,13 +5,13 @@
 @G2 = internal global i8 0              ; <i8*> [#uses=1]
 
 define i16 @test1() {
-        %tmp.0 = load i8* @G1           ; <i8> [#uses=1]
+        %tmp.0 = load i8, i8* @G1           ; <i8> [#uses=1]
         %tmp.3 = zext i8 %tmp.0 to i16          ; <i16> [#uses=1]
         ret i16 %tmp.3
 }
 
 define i16 @test2() {
-        %tmp.0 = load i8* @G2           ; <i8> [#uses=1]
+        %tmp.0 = load i8, i8* @G2           ; <i8> [#uses=1]
         %tmp.3 = sext i8 %tmp.0 to i16          ; <i16> [#uses=1]
         ret i16 %tmp.3
 }
diff --git a/test/CodeGen/X86/extern_weak.ll b/test/CodeGen/X86/extern_weak.ll
index 01e32aae08ca..c2ff09f21e80 100644
--- a/test/CodeGen/X86/extern_weak.ll
+++ b/test/CodeGen/X86/extern_weak.ll
@@ -5,7 +5,7 @@
 declare extern_weak i32 @X(i8*)
 
 define void @bar() {
-        tail call void (...)* @foo( )
+        tail call void (...) @foo( )
         ret void
 }
 
diff --git a/test/CodeGen/X86/extract-extract.ll b/test/CodeGen/X86/extract-extract.ll
index ad79ab9ae20f..9f1516356203 100644
--- a/test/CodeGen/X86/extract-extract.ll
+++ b/test/CodeGen/X86/extract-extract.ll
@@ -11,11 +11,11 @@
 
 define fastcc void @foo(%pp* nocapture byval %p_arg) {
 entry:
-        %tmp2 = getelementptr %pp* %p_arg, i64 0, i32 0         ; <%cc*> [#uses=
-        %tmp3 = load %cc* %tmp2         ; <%cc> [#uses=1]
+        %tmp2 = getelementptr %pp, %pp* %p_arg, i64 0, i32 0         ; <%cc*> [#uses=
+        %tmp3 = load %cc, %cc* %tmp2         ; <%cc> [#uses=1]
         %tmp34 = extractvalue %cc %tmp3, 0              ; <%crd> [#uses=1]
         %tmp345 = extractvalue %crd %tmp34, 0           ; <i64> [#uses=1]
-        %.ptr.i = load %cr** undef              ; <%cr*> [#uses=0]
+        %.ptr.i = load %cr*, %cr** undef              ; <%cr*> [#uses=0]
         %tmp15.i = shl i64 %tmp345, 3           ; <i64> [#uses=0]
         store %cr* undef, %cr** undef
         ret void
diff --git a/test/CodeGen/X86/extract-store.ll b/test/CodeGen/X86/extract-store.ll
index 27d93804ba60..801ecc9ada6c 100644
--- a/test/CodeGen/X86/extract-store.ll
+++ b/test/CodeGen/X86/extract-store.ll
@@ -1,7 +1,8 @@
 ; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+sse4.1 | FileCheck %s -check-prefix=SSE41
 ; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+avx | FileCheck %s -check-prefix=AVX
 
-define void @pextrb(i8* nocapture %dst, <16 x i8> %foo) {
+; CHECK-LABEL: extract_i8
+define void @extract_i8(i8* nocapture %dst, <16 x i8> %foo) {
 ; AVX: vpextrb
 ; SSE41: pextrb
 ; AVX-NOT: movb
@@ -11,12 +12,35 @@ define void @pextrb(i8* nocapture %dst, <16 x i8> %foo) {
   ret void
 }
 
-define void @pextrw(i16* nocapture %dst, <8 x i16> %foo) {
+; CHECK-LABEL: extract_i16
+define void @extract_i16(i16* nocapture %dst, <8 x i16> %foo) {
 ; AVX: vpextrw
 ; SSE41: pextrw
 ; AVX-NOT: movw
 ; SSE41-NOT: movw
-  %vecext = extractelement <8 x i16> %foo, i32 15
+  %vecext = extractelement <8 x i16> %foo, i32 7
+  store i16 %vecext, i16* %dst, align 1
+  ret void
+}
+
+; CHECK-LABEL: extract_i8_undef
+define void @extract_i8_undef(i8* nocapture %dst, <16 x i8> %foo) {
+; AVX-NOT: vpextrb
+; SSE41-NOT: pextrb
+; AVX-NOT: movb
+; SSE41-NOT: movb
+  %vecext = extractelement <16 x i8> %foo, i32 16 ; undef
+  store i8 %vecext, i8* %dst, align 1
+  ret void
+}
+
+; CHECK-LABEL: extract_i16_undef
+define void @extract_i16_undef(i16* nocapture %dst, <8 x i16> %foo) {
+; AVX-NOT: vpextrw
+; SSE41-NOT: pextrw
+; AVX-NOT: movw
+; SSE41-NOT: movw
+  %vecext = extractelement <8 x i16> %foo, i32 9 ; undef
   store i16 %vecext, i16* %dst, align 1
   ret void
 }
diff --git a/test/CodeGen/X86/extractelement-index.ll b/test/CodeGen/X86/extractelement-index.ll
new file mode 100644
index 000000000000..ab3ff8ed435e
--- /dev/null
+++ b/test/CodeGen/X86/extractelement-index.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux             | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx | FileCheck %s -check-prefix=AVX
+
+
+; CHECK-LABEL: extractelement_index_1:
+define i8 @extractelement_index_1(<32 x i8> %a) nounwind {
+  ; X64:       movaps
+  ; AVX:       vpextrb $1
+  %b = extractelement <32 x i8> %a, i256 1
+  ret i8 %b
+}
+
+; CHECK-LABEL: extractelement_index_2:
+define i32 @extractelement_index_2(<8 x i32> %a) nounwind {
+  ; X64:       pshufd
+  ; AVX:       vextractf128 $1
+  ; AVX-NEXT:  vpextrd      $3
+  %b = extractelement <8 x i32> %a, i64 7
+  ret i32 %b
+}
+
+; CHECK-LABEL: extractelement_index_3:
+define i32 @extractelement_index_3(<8 x i32> %a) nounwind {
+  ; CHECK-NOT: pextr
+  %b = extractelement <8 x i32> %a, i64 15
+  ret i32 %b
+}
+
+; CHECK-LABEL: extractelement_index_4:
+define i32 @extractelement_index_4(<8 x i32> %a) nounwind {
+  ; X64:       movd
+  ; AVX:       vextractf128 $1
+  ; AVX-NEXT:  vmovd
+  %b = extractelement <8 x i32> %a, i256 4
+  ret i32 %b
+}
+
+; CHECK-LABEL: extractelement_index_5:
+define i8 @extractelement_index_5(<32 x i8> %a, i256 %i) nounwind {
+  ; X64:       movaps
+  ; AVX:       vmovaps
+  %b = extractelement <32 x i8> %a, i256 %i
+  ret i8 %b
+}
+
+; CHECK-LABEL: extractelement_index_6:
+define i8 @extractelement_index_6(<32 x i8> %a) nounwind {
+  ; CHECK-NOT: pextr
+  %b = extractelement <32 x i8> %a, i256 -1
+  ret i8 %b
+}
\ No newline at end of file
diff --git a/test/CodeGen/X86/extractelement-legalization-store-ordering.ll b/test/CodeGen/X86/extractelement-legalization-store-ordering.ll
new file mode 100644
index 000000000000..946516c8a46d
--- /dev/null
+++ b/test/CodeGen/X86/extractelement-legalization-store-ordering.ll
@@ -0,0 +1,57 @@
+; RUN: llc < %s -mtriple i386-apple-darwin -mcpu=yonah | FileCheck %s
+
+target datalayout = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"
+
+; Make sure we don't break load/store ordering when turning an extractelement
+; into loads, off the stack or a previous store.
+; Be very explicit about the ordering/stack offsets.
+
+; CHECK-LABEL: test_extractelement_legalization_storereuse:
+; CHECK:      # BB#0
+; CHECK-NEXT: pushl %ebx
+; CHECK-NEXT: pushl %edi
+; CHECK-NEXT: pushl %esi
+; CHECK-NEXT: movl 16(%esp), %eax
+; CHECK-NEXT: movl 24(%esp), %ecx
+; CHECK-NEXT: movl 20(%esp), %edx
+; CHECK-NEXT: paddd (%edx), %xmm0
+; CHECK-NEXT: movdqa %xmm0, (%edx)
+; CHECK-NEXT: shll $4, %ecx
+; CHECK-NEXT: movl (%ecx,%edx), %esi
+; CHECK-NEXT: movl 12(%ecx,%edx), %edi
+; CHECK-NEXT: movl 8(%ecx,%edx), %ebx
+; CHECK-NEXT: movl 4(%ecx,%edx), %edx
+; CHECK-NEXT: movl %esi, 12(%eax,%ecx)
+; CHECK-NEXT: movl %edx, (%eax,%ecx)
+; CHECK-NEXT: movl %ebx, 8(%eax,%ecx)
+; CHECK-NEXT: movl %edi, 4(%eax,%ecx)
+; CHECK-NEXT: popl %esi
+; CHECK-NEXT: popl %edi
+; CHECK-NEXT: popl %ebx
+; CHECK-NEXT: retl
+define void @test_extractelement_legalization_storereuse(<4 x i32> %a, i32* nocapture %x, i32* nocapture readonly %y, i32 %i) #0 {
+entry:
+  %0 = bitcast i32* %y to <4 x i32>*
+  %1 = load <4 x i32>, <4 x i32>* %0, align 16
+  %am = add <4 x i32> %a, %1
+  store <4 x i32> %am, <4 x i32>* %0, align 16
+  %ip0 = shl nsw i32 %i, 2
+  %ip1 = or i32 %ip0, 1
+  %ip2 = or i32 %ip0, 2
+  %ip3 = or i32 %ip0, 3
+  %vecext = extractelement <4 x i32> %am, i32 %ip0
+  %arrayidx = getelementptr inbounds i32, i32* %x, i32 %ip3
+  store i32 %vecext, i32* %arrayidx, align 4
+  %vecext5 = extractelement <4 x i32> %am, i32 %ip1
+  %arrayidx8 = getelementptr inbounds i32, i32* %x, i32 %ip0
+  store i32 %vecext5, i32* %arrayidx8, align 4
+  %vecext11 = extractelement <4 x i32> %am, i32 %ip2
+  %arrayidx14 = getelementptr inbounds i32, i32* %x, i32 %ip2
+  store i32 %vecext11, i32* %arrayidx14, align 4
+  %vecext17 = extractelement <4 x i32> %am, i32 %ip3
+  %arrayidx20 = getelementptr inbounds i32, i32* %x, i32 %ip1
+  store i32 %vecext17, i32* %arrayidx20, align 4
+  ret void
+}
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/X86/extractelement-load.ll b/test/CodeGen/X86/extractelement-load.ll
index 732f698f59ff..e50d353797a0 100644
--- a/test/CodeGen/X86/extractelement-load.ll
+++ b/test/CodeGen/X86/extractelement-load.ll
@@ -9,7 +9,7 @@ define i32 @t(<2 x i64>* %val) nounwind  {
 ; CHECK-NOT: movd
 ; CHECK: movl 8(
 ; CHECK-NEXT: ret
-	%tmp2 = load <2 x i64>* %val, align 16		; <<2 x i64>> [#uses=1]
+	%tmp2 = load <2 x i64>, <2 x i64>* %val, align 16		; <<2 x i64>> [#uses=1]
 	%tmp3 = bitcast <2 x i64> %tmp2 to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp4 = extractelement <4 x i32> %tmp3, i32 2		; <i32> [#uses=1]
 	ret i32 %tmp4
@@ -20,7 +20,7 @@ define i32 @t(<2 x i64>* %val) nounwind  {
 define i32 @t2(<8 x i32>* %xp) {
 ; CHECK-LABEL: t2:
 ; CHECK: ret
-  %x = load <8 x i32>* %xp
+  %x = load <8 x i32>, <8 x i32>* %xp
   %Shuff68 = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32
 undef, i32 7, i32 9, i32 undef, i32 13, i32 15, i32 1, i32 3>
   %y = extractelement <8 x i32> %Shuff68, i32 0
@@ -41,7 +41,7 @@ define void @t3() {
 ; CHECK: movhpd
 
 bb:
-  %tmp13 = load <2 x double>* undef, align 1
+  %tmp13 = load <2 x double>, <2 x double>* undef, align 1
   %.sroa.3.24.vec.extract = extractelement <2 x double> %tmp13, i32 1
   store double %.sroa.3.24.vec.extract, double* undef, align 8
   unreachable
@@ -55,7 +55,7 @@ define i64 @t4(<2 x double>* %a) {
 ; CHECK-LABEL: t4:
 ; CHECK: mov
 ; CHECK: ret
-  %b = load <2 x double>* %a, align 16
+  %b = load <2 x double>, <2 x double>* %a, align 16
   %c = shufflevector <2 x double> %b, <2 x double> %b, <2 x i32> <i32 1, i32 0>
   %d = bitcast <2 x double> %c to <2 x i64>
   %e = extractelement <2 x i64> %d, i32 1
diff --git a/test/CodeGen/X86/extractps.ll b/test/CodeGen/X86/extractps.ll
index 9e1a3754d0f0..fecd2faed321 100644
--- a/test/CodeGen/X86/extractps.ll
+++ b/test/CodeGen/X86/extractps.ll
@@ -7,7 +7,7 @@
 external global float, align 16         ; <float*>:0 [#uses=2]
 
 define internal void @""() nounwind {
-        load float* @0, align 16                ; <float>:1 [#uses=1]
+        load float, float* @0, align 16                ; <float>:1 [#uses=1]
         insertelement <4 x float> undef, float %1, i32 0                ; <<4 x float>>:2 [#uses=1]
         call <4 x float> @llvm.x86.sse.rsqrt.ss( <4 x float> %2 )              ; <<4 x float>>:3 [#uses=1]
         extractelement <4 x float> %3, i32 0            ; <float>:4 [#uses=1]
@@ -15,7 +15,7 @@ define internal void @""() nounwind {
         ret void
 }
 define internal void @""() nounwind {
-        load float* @0, align 16                ; <float>:1 [#uses=1]
+        load float, float* @0, align 16                ; <float>:1 [#uses=1]
         insertelement <4 x float> undef, float %1, i32 1                ; <<4 x float>>:2 [#uses=1]
         call <4 x float> @llvm.x86.sse.rsqrt.ss( <4 x float> %2 )              ; <<4 x float>>:3 [#uses=1]
         extractelement <4 x float> %3, i32 1            ; <float>:4 [#uses=1]
diff --git a/test/CodeGen/X86/f16c-intrinsics.ll b/test/CodeGen/X86/f16c-intrinsics.ll
index 514d929f4432..485592aeac38 100644
--- a/test/CodeGen/X86/f16c-intrinsics.ll
+++ b/test/CodeGen/X86/f16c-intrinsics.ll
@@ -1,7 +1,9 @@
-; RUN: llc < %s -march=x86 -mattr=+avx,+f16c | FileCheck %s
-; RUN: llc < %s -march=x86-64 -mattr=+avx,+f16c | FileCheck %s
+; RUN: llc < %s -mtriple=i686-unknown-unknown   -mattr=+avx,+f16c | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+f16c | FileCheck %s
 
 define <4 x float> @test_x86_vcvtph2ps_128(<8 x i16> %a0) {
+  ; CHECK-LABEL: test_x86_vcvtph2ps_128:
+  ; CHECK-NOT: vmov
   ; CHECK: vcvtph2ps
   %res = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %a0) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
@@ -10,22 +12,36 @@ declare <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16>) nounwind readonly
 
 
 define <8 x float> @test_x86_vcvtph2ps_256(<8 x i16> %a0) {
+  ; CHECK-LABEL: test_x86_vcvtph2ps_256:
+  ; CHECK-NOT: vmov
   ; CHECK: vcvtph2ps
   %res = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %a0) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
 declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>) nounwind readonly
 
+define <8 x float> @test_x86_vcvtph2ps_256_m(<8 x i16>* nocapture %a) nounwind {
+entry:
+  ; CHECK-LABEL: test_x86_vcvtph2ps_256_m:
+  ; CHECK-NOT: vmov
+  ; CHECK: vcvtph2ps  (%
+  %tmp1 = load <8 x i16>, <8 x i16>* %a, align 16
+  %0 = tail call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %tmp1)
+  ret <8 x float> %0
+}
 
 define <8 x i16> @test_x86_vcvtps2ph_128(<4 x float> %a0) {
+  ; CHECK-LABEL: test_x86_vcvtps2ph_128:
+  ; CHECK-NOT: vmov
   ; CHECK: vcvtps2ph
   %res = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float>, i32) nounwind readonly
 
-
 define <8 x i16> @test_x86_vcvtps2ph_256(<8 x float> %a0) {
+  ; CHECK-LABEL: test_x86_vcvtps2ph_256:
+  ; CHECK-NOT: vmov
   ; CHECK: vcvtps2ph
   %res = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0) ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %res
@@ -33,14 +49,59 @@ define <8 x i16> @test_x86_vcvtps2ph_256(<8 x float> %a0) {
 declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32) nounwind readonly
 
 define <4 x float> @test_x86_vcvtps2ph_128_scalar(i64* %ptr) {
-; CHECK-LABEL: test_x86_vcvtps2ph_128_scalar
+; CHECK-LABEL: test_x86_vcvtps2ph_128_scalar:
 ; CHECK-NOT: vmov
 ; CHECK: vcvtph2ps (%
 
-  %load = load i64* %ptr
+  %load = load i64, i64* %ptr
   %ins1 = insertelement <2 x i64> undef, i64 %load, i32 0
   %ins2 = insertelement <2 x i64> %ins1, i64 0, i32 1
   %bc = bitcast <2 x i64> %ins2 to <8 x i16>
   %res = tail call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %bc) #2
   ret <4 x float> %res
 }
+
+define void @test_x86_vcvtps2ph_256_m(<8 x i16>* nocapture %d, <8 x float> %a) nounwind {
+entry:
+  ; CHECK-LABEL: test_x86_vcvtps2ph_256_m:
+  ; CHECK-NOT: vmov
+  ; CHECK: vcvtps2ph  $3, %ymm0, (%
+  %0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a, i32 3)
+  store <8 x i16> %0, <8 x i16>* %d, align 16
+  ret void
+}
+
+define void @test_x86_vcvtps2ph_128_m(<4 x i16>* nocapture %d, <4 x float> %a) nounwind {
+entry:
+  ; CHECK-LABEL: test_x86_vcvtps2ph_128_m:
+  ; CHECK-NOT: vmov
+  ; CHECK: vcvtps2ph  $3, %xmm0, (%
+  %0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a, i32 3)
+  %1 = shufflevector <8 x i16> %0, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  store <4 x i16> %1, <4 x i16>* %d, align 8
+  ret void
+}
+
+define void @test_x86_vcvtps2ph_128_m2(double* nocapture %hf4x16, <4 x float> %f4x32) #0 {
+entry:
+  ; CHECK-LABEL: test_x86_vcvtps2ph_128_m2:
+  ; CHECK-NOT: vmov
+  ; CHECK: vcvtps2ph  $3, %xmm0, (%
+  %0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %f4x32, i32 3)
+  %1 = bitcast <8 x i16> %0 to <2 x double>
+  %vecext = extractelement <2 x double> %1, i32 0
+  store double %vecext, double* %hf4x16, align 8
+  ret void
+}
+
+define void @test_x86_vcvtps2ph_128_m3(i64* nocapture %hf4x16, <4 x float> %f4x32) #0 {
+entry:
+  ; CHECK-LABEL: test_x86_vcvtps2ph_128_m3:
+  ; CHECK-NOT: vmov
+  ; CHECK: vcvtps2ph  $3, %xmm0, (%
+  %0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %f4x32, i32 3)
+  %1 = bitcast <8 x i16> %0 to <2 x i64>
+  %vecext = extractelement <2 x i64> %1, i32 0
+  store i64 %vecext, i64* %hf4x16, align 8
+  ret void
+}
diff --git a/test/CodeGen/X86/fast-isel-args-fail.ll b/test/CodeGen/X86/fast-isel-args-fail.ll
index 7e783d2891d4..0026832ed281 100644
--- a/test/CodeGen/X86/fast-isel-args-fail.ll
+++ b/test/CodeGen/X86/fast-isel-args-fail.ll
@@ -17,6 +17,6 @@ entry:
 ; WIN32: movl (%rcx), %eax
 ; WIN64: foo
 ; WIN64: movl (%rdi), %eax
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   ret i32 %0
 }
diff --git a/test/CodeGen/X86/fast-isel-args-fail2.ll b/test/CodeGen/X86/fast-isel-args-fail2.ll
index 08de472c2a54..f7066577f2de 100644
--- a/test/CodeGen/X86/fast-isel-args-fail2.ll
+++ b/test/CodeGen/X86/fast-isel-args-fail2.ll
@@ -1,4 +1,4 @@
-; RUN: not --crash llc < %s -fast-isel -fast-isel-abort-args -mtriple=x86_64-apple-darwin10
+; RUN: not llc < %s -fast-isel -fast-isel-abort=2 -mtriple=x86_64-apple-darwin10
 ; REQUIRES: asserts
 
 %struct.s0 = type { x86_fp80, x86_fp80 }
diff --git a/test/CodeGen/X86/fast-isel-args.ll b/test/CodeGen/X86/fast-isel-args.ll
index 8c86a9cc01d6..bcd41b7a2bfe 100644
--- a/test/CodeGen/X86/fast-isel-args.ll
+++ b/test/CodeGen/X86/fast-isel-args.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -fast-isel -fast-isel-abort -fast-isel-abort-args -verify-machineinstrs -mtriple=x86_64-apple-darwin10
+; RUN: llc < %s -fast-isel -fast-isel-abort=2 -verify-machineinstrs -mtriple=x86_64-apple-darwin10
 
 ; Just make sure these don't abort when lowering the arguments.
 define i32 @t1(i32 %a, i32 %b, i32 %c) {
diff --git a/test/CodeGen/X86/fast-isel-avoid-unnecessary-pic-base.ll b/test/CodeGen/X86/fast-isel-avoid-unnecessary-pic-base.ll
index 21fae4a82051..3310e6113f1e 100644
--- a/test/CodeGen/X86/fast-isel-avoid-unnecessary-pic-base.ll
+++ b/test/CodeGen/X86/fast-isel-avoid-unnecessary-pic-base.ll
@@ -15,10 +15,10 @@ entry:
   store i32 %x, i32* %x.addr, align 4
   store i32 %y, i32* %y.addr, align 4
   store i32 %z, i32* %z.addr, align 4
-  %tmp = load i32* %x.addr, align 4
-  %tmp1 = load i32* %y.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
+  %tmp1 = load i32, i32* %y.addr, align 4
   %add = add nsw i32 %tmp, %tmp1
-  %tmp2 = load i32* %z.addr, align 4
+  %tmp2 = load i32, i32* %z.addr, align 4
   %add3 = add nsw i32 %add, %tmp2
   ret i32 %add3
 }
diff --git a/test/CodeGen/X86/fast-isel-branch_weights.ll b/test/CodeGen/X86/fast-isel-branch_weights.ll
index d2b02aad182d..feb240f05863 100644
--- a/test/CodeGen/X86/fast-isel-branch_weights.ll
+++ b/test/CodeGen/X86/fast-isel-branch_weights.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s                             -mtriple=x86_64-apple-darwin10 | FileCheck %s
-; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 | FileCheck %s
+; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s
 
 ; Test if the BBs are reordred according to their branch weights.
 define i64 @branch_weights_test(i64 %a, i64 %b) {
diff --git a/test/CodeGen/X86/fast-isel-call-bool.ll b/test/CodeGen/X86/fast-isel-call-bool.ll
index 5cdb2c941161..aaa8ef4f644c 100644
--- a/test/CodeGen/X86/fast-isel-call-bool.ll
+++ b/test/CodeGen/X86/fast-isel-call-bool.ll
@@ -8,7 +8,7 @@ declare i64 @bar(i1)
 define i64 @foo(i8* %arg) {
 ; CHECK-LABEL: foo:
 top:
-  %0 = load i8* %arg
+  %0 = load i8, i8* %arg
 ; CHECK: movb
   %1 = trunc i8 %0 to i1
 ; CHECK: andb $1,
diff --git a/test/CodeGen/X86/fast-isel-call.ll b/test/CodeGen/X86/fast-isel-call.ll
index 42d2b8bed654..9fd07b521ab2 100644
--- a/test/CodeGen/X86/fast-isel-call.ll
+++ b/test/CodeGen/X86/fast-isel-call.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -fast-isel-abort -march=x86 | FileCheck %s
+; RUN: llc < %s -O0 -fast-isel-abort=1 -march=x86 | FileCheck %s
 
 %struct.s = type {i32, i32, i32}
 
diff --git a/test/CodeGen/X86/fast-isel-cmp-branch2.ll b/test/CodeGen/X86/fast-isel-cmp-branch2.ll
index 7e45c49f48f7..04dbac07690a 100644
--- a/test/CodeGen/X86/fast-isel-cmp-branch2.ll
+++ b/test/CodeGen/X86/fast-isel-cmp-branch2.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s                             -mtriple=x86_64-apple-darwin10 | FileCheck %s
-; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 | FileCheck %s
+; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s
 
 define i32 @fcmp_oeq(float %x, float %y) {
 ; CHECK-LABEL: fcmp_oeq
diff --git a/test/CodeGen/X86/fast-isel-cmp-branch3.ll b/test/CodeGen/X86/fast-isel-cmp-branch3.ll
index 0df782d18ecf..e54d0ca40078 100644
--- a/test/CodeGen/X86/fast-isel-cmp-branch3.ll
+++ b/test/CodeGen/X86/fast-isel-cmp-branch3.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 | FileCheck %s
+; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s
 
 define i32 @fcmp_oeq1(float %x) {
 ; CHECK-LABEL: fcmp_oeq1
diff --git a/test/CodeGen/X86/fast-isel-cmp.ll b/test/CodeGen/X86/fast-isel-cmp.ll
index 1b72cfcde657..d15dd50a4554 100644
--- a/test/CodeGen/X86/fast-isel-cmp.ll
+++ b/test/CodeGen/X86/fast-isel-cmp.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s                             -mtriple=x86_64-apple-darwin10 | FileCheck %s --check-prefix=SDAG
-; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 | FileCheck %s --check-prefix=FAST
+; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s --check-prefix=FAST
 
 define zeroext i1 @fcmp_oeq(float %x, float %y) {
 ; SDAG-LABEL: fcmp_oeq
diff --git a/test/CodeGen/X86/fast-isel-constrain-store-indexreg.ll b/test/CodeGen/X86/fast-isel-constrain-store-indexreg.ll
new file mode 100644
index 000000000000..c2534f72bd0d
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-constrain-store-indexreg.ll
@@ -0,0 +1,25 @@
+; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-unknown"
+
+@TheArray = external global [100000 x double], align 16
+
+; This test ensures, via the machine verifier, that the register class for the
+; index of the double store is correctly constrained to not include SP.
+
+; CHECK: movsd
+
+define i32 @main(i32* %i, double %tmpv) {
+bb:
+  br label %bb7
+
+bb7:                                              ; preds = %bb7, %bb
+  %storemerge = phi i32 [ 0, %bb ], [ %tmp19, %bb7 ]
+  %tmp15 = zext i32 %storemerge to i64
+  %tmp16 = getelementptr inbounds [100000 x double], [100000 x double]* @TheArray, i64 0, i64 %tmp15
+  store double %tmpv, double* %tmp16, align 8
+  %tmp18 = load i32, i32* %i, align 4
+  %tmp19 = add i32 %tmp18, 1
+  br label %bb7
+}
diff --git a/test/CodeGen/X86/fast-isel-divrem-x86-64.ll b/test/CodeGen/X86/fast-isel-divrem-x86-64.ll
index 0fd0561e2046..9c04ea67d519 100644
--- a/test/CodeGen/X86/fast-isel-divrem-x86-64.ll
+++ b/test/CodeGen/X86/fast-isel-divrem-x86-64.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 define i64 @test_sdiv64(i64 %dividend, i64 %divisor) nounwind {
 entry:
diff --git a/test/CodeGen/X86/fast-isel-divrem.ll b/test/CodeGen/X86/fast-isel-divrem.ll
index 5828becb3c33..3e649ca9a603 100644
--- a/test/CodeGen/X86/fast-isel-divrem.ll
+++ b/test/CodeGen/X86/fast-isel-divrem.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 define i8 @test_sdiv8(i8 %dividend, i8 %divisor) nounwind {
 entry:
diff --git a/test/CodeGen/X86/fast-isel-double-half-convertion.ll b/test/CodeGen/X86/fast-isel-double-half-convertion.ll
new file mode 100644
index 000000000000..d17ce101d090
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-double-half-convertion.ll
@@ -0,0 +1,23 @@
+; RUN: llc -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+f16c < %s
+
+; XFAIL: *
+
+; In the future, we might want to teach fast-isel how to expand a double-to-half
+; conversion into a double-to-float conversion immediately followed by a
+; float-to-half conversion. For now, fast-isel is expected to fail.
+
+define double @test_fp16_to_fp64(i32 %a) {
+entry:
+  %0 = trunc i32 %a to i16
+  %1 = call double @llvm.convert.from.fp16.f64(i16 %0)
+  ret float %0
+}
+
+define i16 @test_fp64_to_fp16(double %a) {
+entry:
+  %0 = call i16 @llvm.convert.to.fp16.f64(double %a)
+  ret i16 %0
+}
+
+declare i16 @llvm.convert.to.fp16.f64(double)
+declare double @llvm.convert.from.fp16.f64(i16)
diff --git a/test/CodeGen/X86/fast-isel-extract.ll b/test/CodeGen/X86/fast-isel-extract.ll
index 3a4b2a685504..fb20fdd0d36f 100644
--- a/test/CodeGen/X86/fast-isel-extract.ll
+++ b/test/CodeGen/X86/fast-isel-extract.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple x86_64-apple-darwin11 -O0 -fast-isel-abort | FileCheck %s
+; RUN: llc < %s -mtriple x86_64-apple-darwin11 -O0 -fast-isel-abort=1 | FileCheck %s
 
 %struct.x = type { i64, i64 }
 %addovf = type { i32, i1 }
diff --git a/test/CodeGen/X86/fast-isel-float-half-convertion.ll b/test/CodeGen/X86/fast-isel-float-half-convertion.ll
new file mode 100644
index 000000000000..707a325bf41d
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-float-half-convertion.ll
@@ -0,0 +1,28 @@
+; RUN: llc -fast-isel -fast-isel-abort=1 -asm-verbose=false -mtriple=x86_64-unknown-unknown -mattr=+f16c < %s | FileCheck %s
+
+; Verify that fast-isel correctly expands float-half conversions.
+
+define i16 @test_fp32_to_fp16(float %a) {
+; CHECK-LABEL: test_fp32_to_fp16:
+; CHECK: vcvtps2ph $0, %xmm0, %xmm0
+; CHECK-NEXT: vmovd %xmm0, %eax
+; CHECK-NEXT: retq
+entry:
+  %0 = call i16 @llvm.convert.to.fp16.f32(float %a)
+  ret i16 %0
+}
+
+define float @test_fp16_to_fp32(i32 %a) {
+; CHECK-LABEL: test_fp16_to_fp32:
+; CHECK: movswl %di, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: retq
+entry:
+  %0 = trunc i32 %a to i16
+  %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
+  ret float %1
+}
+
+declare i16 @llvm.convert.to.fp16.f32(float)
+declare float @llvm.convert.from.fp16.f32(i16)
diff --git a/test/CodeGen/X86/fast-isel-fneg.ll b/test/CodeGen/X86/fast-isel-fneg.ll
index 8b38587164fe..e3bc7faae3ce 100644
--- a/test/CodeGen/X86/fast-isel-fneg.ll
+++ b/test/CodeGen/X86/fast-isel-fneg.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 | FileCheck %s
+; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s
 ; RUN: llc < %s -fast-isel -march=x86 -mattr=+sse2 | FileCheck --check-prefix=SSE2 %s
 
 ; SSE2: xor
diff --git a/test/CodeGen/X86/fast-isel-fold-mem.ll b/test/CodeGen/X86/fast-isel-fold-mem.ll
index a94577962e91..5686484ef935 100644
--- a/test/CodeGen/X86/fast-isel-fold-mem.ll
+++ b/test/CodeGen/X86/fast-isel-fold-mem.ll
@@ -1,11 +1,11 @@
 ; RUN: llc < %s                             -mtriple=x86_64-apple-darwin | FileCheck %s
-; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin | FileCheck %s
 
 define i64 @fold_load(i64* %a, i64 %b) {
 ; CHECK-LABEL: fold_load
 ; CHECK:       addq  (%rdi), %rsi
 ; CHECK-NEXT:  movq  %rsi, %rax
-  %1 = load i64* %a, align 8
+  %1 = load i64, i64* %a, align 8
   %2 = add i64 %1, %b
   ret i64 %2
 }
diff --git a/test/CodeGen/X86/fast-isel-fptrunc-fpext.ll b/test/CodeGen/X86/fast-isel-fptrunc-fpext.ll
new file mode 100644
index 000000000000..e4e9aeaa262e
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-fptrunc-fpext.ll
@@ -0,0 +1,65 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=ALL --check-prefix=AVX
+;
+; Verify that fast-isel doesn't select legacy SSE instructions on targets that
+; feature AVX.
+;
+; Test cases are obtained from the following code snippet:
+; ///
+; double single_to_double_rr(float x) {
+;   return (double)x;
+; }
+; float double_to_single_rr(double x) {
+;   return (float)x;
+; }
+; double single_to_double_rm(float *x) {
+;   return (double)*x;
+; }
+; float double_to_single_rm(double *x) {
+;   return (float)*x;
+; }
+; ///
+
+define double @single_to_double_rr(float %x) {
+; ALL-LABEL: single_to_double_rr:
+; SSE-NOT: vcvtss2sd
+; AVX: vcvtss2sd %xmm0, %xmm0, %xmm0
+; ALL: ret
+entry:
+  %conv = fpext float %x to double
+  ret double %conv
+}
+
+define float @double_to_single_rr(double %x) {
+; ALL-LABEL: double_to_single_rr:
+; SSE-NOT: vcvtsd2ss
+; AVX: vcvtsd2ss %xmm0, %xmm0, %xmm0
+; ALL: ret
+entry:
+  %conv = fptrunc double %x to float
+  ret float %conv
+}
+
+define double @single_to_double_rm(float* %x) {
+; ALL-LABEL: single_to_double_rm:
+; SSE: cvtss2sd (%rdi), %xmm0
+; AVX: vmovss (%rdi), %xmm0
+; AVX-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0
+; ALL-NEXT: ret
+entry:
+  %0 = load float, float* %x, align 4
+  %conv = fpext float %0 to double
+  ret double %conv
+}
+
+define float @double_to_single_rm(double* %x) {
+; ALL-LABEL: double_to_single_rm:
+; SSE: cvtsd2ss (%rdi), %xmm0
+; AVX: vmovsd (%rdi), %xmm0
+; AVX-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0
+; ALL-NEXT: ret
+entry:
+  %0 = load double, double* %x, align 8
+  %conv = fptrunc double %0 to float
+  ret float %conv
+}
diff --git a/test/CodeGen/X86/fast-isel-gep.ll b/test/CodeGen/X86/fast-isel-gep.ll
index a65e0705f2b2..67b30292be3c 100644
--- a/test/CodeGen/X86/fast-isel-gep.ll
+++ b/test/CodeGen/X86/fast-isel-gep.ll
@@ -6,8 +6,8 @@
 ; should be sign-extended to 64 bits on 64-bit targets.
 ; PR3181
 define i32 @test1(i32 %t3, i32* %t1) nounwind {
-       %t9 = getelementptr i32* %t1, i32 %t3           ; <i32*> [#uses=1]
-       %t15 = load i32* %t9            ; <i32> [#uses=1]
+       %t9 = getelementptr i32, i32* %t1, i32 %t3           ; <i32*> [#uses=1]
+       %t15 = load i32, i32* %t9            ; <i32> [#uses=1]
        ret i32 %t15
 ; X32-LABEL: test1:
 ; X32:  	movl	(%eax,%ecx,4), %eax
@@ -20,8 +20,8 @@ define i32 @test1(i32 %t3, i32* %t1) nounwind {
 
 }
 define i32 @test2(i64 %t3, i32* %t1) nounwind {
-       %t9 = getelementptr i32* %t1, i64 %t3           ; <i32*> [#uses=1]
-       %t15 = load i32* %t9            ; <i32> [#uses=1]
+       %t9 = getelementptr i32, i32* %t1, i64 %t3           ; <i32*> [#uses=1]
+       %t15 = load i32, i32* %t9            ; <i32> [#uses=1]
        ret i32 %t15
 ; X32-LABEL: test2:
 ; X32:  	movl	(%edx,%ecx,4), %e
@@ -37,8 +37,8 @@ define i32 @test2(i64 %t3, i32* %t1) nounwind {
 ; PR4984
 define i8 @test3(i8* %start) nounwind {
 entry:
-  %A = getelementptr i8* %start, i64 -2               ; <i8*> [#uses=1]
-  %B = load i8* %A, align 1                       ; <i8> [#uses=1]
+  %A = getelementptr i8, i8* %start, i64 -2               ; <i8*> [#uses=1]
+  %B = load i8, i8* %A, align 1                       ; <i8> [#uses=1]
   ret i8 %B
   
   
@@ -59,11 +59,11 @@ entry:
   %p.addr = alloca double*, align 8               ; <double**> [#uses=2]
   store i64 %x, i64* %x.addr
   store double* %p, double** %p.addr
-  %tmp = load i64* %x.addr                        ; <i64> [#uses=1]
+  %tmp = load i64, i64* %x.addr                        ; <i64> [#uses=1]
   %add = add nsw i64 %tmp, 16                     ; <i64> [#uses=1]
-  %tmp1 = load double** %p.addr                   ; <double*> [#uses=1]
-  %arrayidx = getelementptr inbounds double* %tmp1, i64 %add ; <double*> [#uses=1]
-  %tmp2 = load double* %arrayidx                  ; <double> [#uses=1]
+  %tmp1 = load double*, double** %p.addr                   ; <double*> [#uses=1]
+  %arrayidx = getelementptr inbounds double, double* %tmp1, i64 %add ; <double*> [#uses=1]
+  %tmp2 = load double, double* %arrayidx                  ; <double> [#uses=1]
   ret double %tmp2
 
 ; X32-LABEL: test4:
@@ -75,9 +75,9 @@ entry:
 ; PR8961 - Make sure the sext for the GEP addressing comes before the load that
 ; is folded.
 define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind {
-  %v8 = getelementptr i8* %A, i32 %I
+  %v8 = getelementptr i8, i8* %A, i32 %I
   %v9 = bitcast i8* %v8 to i64*
-  %v10 = load i64* %v9
+  %v10 = load i64, i64* %v9
   %v11 = add i64 %B, %v10
   ret i64 %v11
 ; X64-LABEL: test5:
@@ -91,14 +91,14 @@ define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind {
 ; of their blocks.
 define void @test6() {
 if.end:                                           ; preds = %if.then, %invoke.cont
-  %tmp15 = load i64* undef
+  %tmp15 = load i64, i64* undef
   %dec = add i64 %tmp15, 13
   store i64 %dec, i64* undef
   %call17 = invoke i8* @_ZNK18G__FastAllocString4dataEv()
           to label %invoke.cont16 unwind label %lpad
 
 invoke.cont16:                                    ; preds = %if.then14
-  %arrayidx18 = getelementptr inbounds i8* %call17, i64 %dec
+  %arrayidx18 = getelementptr inbounds i8, i8* %call17, i64 %dec
   store i8 0, i8* %arrayidx18
   unreachable
 
@@ -118,10 +118,10 @@ define i32 @test7({i32,i32,i32}* %tmp1, i32 %tmp71, i32 %tmp63) nounwind  {
 ; X64:     movl	$4, 8({{%rdi|%rcx}})
 
 
-  %tmp29 = getelementptr inbounds {i32,i32,i32}* %tmp1, i32 0, i32 2
-  %tmp30 = load i32* %tmp29, align 4
+  %tmp29 = getelementptr inbounds {i32,i32,i32}, {i32,i32,i32}* %tmp1, i32 0, i32 2
+  %tmp30 = load i32, i32* %tmp29, align 4
 
-  %p2 = getelementptr inbounds {i32,i32,i32}* %tmp1, i32 0, i32 2
+  %p2 = getelementptr inbounds {i32,i32,i32}, {i32,i32,i32}* %tmp1, i32 0, i32 2
   store i32 4, i32* %p2
   
   %tmp72 = or i32 %tmp71, %tmp30
diff --git a/test/CodeGen/X86/fast-isel-gv.ll b/test/CodeGen/X86/fast-isel-gv.ll
index de7509568907..b3955d6e4f81 100644
--- a/test/CodeGen/X86/fast-isel-gv.ll
+++ b/test/CodeGen/X86/fast-isel-gv.ll
@@ -12,15 +12,15 @@ entry:
 	%retval = alloca i32		; <i32*> [#uses=2]
 	%0 = alloca i32		; <i32*> [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
-	%1 = load i8 (...)** @f, align 8		; <i8 (...)*> [#uses=1]
+	%1 = load i8 (...)*, i8 (...)** @f, align 8		; <i8 (...)*> [#uses=1]
 	%2 = icmp ne i8 (...)* %1, @kill		; <i1> [#uses=1]
 	%3 = zext i1 %2 to i32		; <i32> [#uses=1]
 	store i32 %3, i32* %0, align 4
-	%4 = load i32* %0, align 4		; <i32> [#uses=1]
+	%4 = load i32, i32* %0, align 4		; <i32> [#uses=1]
 	store i32 %4, i32* %retval, align 4
 	br label %return
 
 return:		; preds = %entry
-	%retval1 = load i32* %retval		; <i32> [#uses=1]
+	%retval1 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval1
 }
diff --git a/test/CodeGen/X86/fast-isel-i1.ll b/test/CodeGen/X86/fast-isel-i1.ll
index 9c042d30e78c..589de76617a0 100644
--- a/test/CodeGen/X86/fast-isel-i1.ll
+++ b/test/CodeGen/X86/fast-isel-i1.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=i686-apple-darwin10 -fast-isel -fast-isel-abort | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort | FileCheck %s
+; RUN: llc < %s -mtriple=i686-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 declare i32 @test1a(i32)
 
@@ -23,14 +23,15 @@ exit:		; preds = %next
 
 define void @test2(i8* %a) nounwind {
 entry:
+; clang uses i8 constants for booleans, so we test with an i8 1.
 ; CHECK-LABEL: test2:
 ; CHECK: movb {{.*}} %al
 ; CHECK-NEXT: xorb $1, %al
 ; CHECK-NEXT: testb $1
-  %tmp = load i8* %a, align 1
-  %tobool = trunc i8 %tmp to i1
-  %tobool2 = xor i1 %tobool, true
-  br i1 %tobool2, label %if.then, label %if.end
+  %tmp = load i8, i8* %a, align 1
+  %xor = xor i8 %tmp, 1
+  %tobool = trunc i8 %xor to i1
+  br i1 %tobool, label %if.then, label %if.end
 
 if.then:
   call void @test2(i8* null)
diff --git a/test/CodeGen/X86/fast-isel-int-float-conversion.ll b/test/CodeGen/X86/fast-isel-int-float-conversion.ll
new file mode 100644
index 000000000000..afa6ee9aa7a2
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-int-float-conversion.ll
@@ -0,0 +1,45 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+sse2 -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
+; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX
+
+
+define double @int_to_double_rr(i32 %a) {
+; ALL-LABEL: int_to_double_rr:
+; SSE2: cvtsi2sdl %edi, %xmm0
+; AVX: vcvtsi2sdl %edi, %xmm0, %xmm0
+; ALL-NEXT: ret
+entry:
+  %0 = sitofp i32 %a to double
+  ret double %0
+}
+
+define double @int_to_double_rm(i32* %a) {
+; ALL-LABEL: int_to_double_rm:
+; SSE2: cvtsi2sdl (%rdi), %xmm0
+; AVX: vcvtsi2sdl (%rdi), %xmm0, %xmm0
+; ALL-NEXT: ret
+entry:
+  %0 = load i32, i32* %a
+  %1 = sitofp i32 %0 to double
+  ret double %1
+}
+
+define float @int_to_float_rr(i32 %a) {
+; ALL-LABEL: int_to_float_rr:
+; SSE2: cvtsi2ssl %edi, %xmm0
+; AVX: vcvtsi2ssl %edi, %xmm0, %xmm0
+; ALL-NEXT: ret
+entry:
+  %0 = sitofp i32 %a to float
+  ret float %0
+}
+
+define float @int_to_float_rm(i32* %a) {
+; ALL-LABEL: int_to_float_rm:
+; SSE2: cvtsi2ssl (%rdi), %xmm0
+; AVX: vcvtsi2ssl (%rdi), %xmm0, %xmm0
+; ALL-NEXT: ret
+entry:
+  %0 = load i32, i32* %a
+  %1 = sitofp i32 %0 to float
+  ret float %1
+}
diff --git a/test/CodeGen/X86/fast-isel-mem.ll b/test/CodeGen/X86/fast-isel-mem.ll
index eca1ae9f02a3..3f1d9cae9340 100644
--- a/test/CodeGen/X86/fast-isel-mem.ll
+++ b/test/CodeGen/X86/fast-isel-mem.ll
@@ -6,8 +6,8 @@
 ; rdar://6653118
 define i32 @loadgv() nounwind {
 entry:
-	%0 = load i32* @src, align 4
-	%1 = load i32* @src, align 4
+	%0 = load i32, i32* @src, align 4
+	%1 = load i32, i32* @src, align 4
         %2 = add i32 %0, %1
         store i32 %2, i32* @src
 	ret i32 %2
@@ -33,7 +33,7 @@ entry:
 
 define void @t(%stuff* %this) nounwind {
 entry:
-	store i32 (...)** getelementptr ([4 x i32 (...)*]* @LotsStuff, i32 0, i32 2), i32 (...)*** null, align 4
+	store i32 (...)** getelementptr ([4 x i32 (...)*], [4 x i32 (...)*]* @LotsStuff, i32 0, i32 2), i32 (...)*** null, align 4
 	ret void
 ; CHECK: _t:
 ; CHECK:	xorl    %eax, %eax
diff --git a/test/CodeGen/X86/fast-isel-movsbl-indexreg.ll b/test/CodeGen/X86/fast-isel-movsbl-indexreg.ll
new file mode 100644
index 000000000000..100c3297ec4e
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-movsbl-indexreg.ll
@@ -0,0 +1,20 @@
+; RUN: llc %s -o - -verify-machineinstrs -fast-isel=true | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-unknown"
+
+; The index register on the folded memory operand was incorrect.  Ensure we generate
+; movsbl in fast-isel, but also that it passes verification which will check the register
+; class.
+
+; CHECK: movsbl
+
+@table = external hidden global [64 x i8], align 16
+
+define i32 @test(i32 %x, i64 %offset) {
+bb:
+  %tmp37 = getelementptr inbounds [64 x i8], [64 x i8]* @table, i64 0, i64 %offset
+  %tmp38 = load i8, i8* %tmp37, align 1
+  %tmp39 = sext i8 %tmp38 to i32
+  ret i32 %tmp39
+}
diff --git a/test/CodeGen/X86/fast-isel-ret-ext.ll b/test/CodeGen/X86/fast-isel-ret-ext.ll
index 0370d99f906c..06bcb50850f6 100644
--- a/test/CodeGen/X86/fast-isel-ret-ext.ll
+++ b/test/CodeGen/X86/fast-isel-ret-ext.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s  -O0 -fast-isel-abort -mtriple i686-apple-darwin10 | FileCheck %s
-; RUN: llc < %s  -O0 -fast-isel-abort -mtriple x86_64-apple-darwin10 | FileCheck %s
+; RUN: llc < %s  -O0 -fast-isel-abort=1 -mtriple i686-apple-darwin10 | FileCheck %s
+; RUN: llc < %s  -O0 -fast-isel-abort=1 -mtriple x86_64-apple-darwin10 | FileCheck %s
 
 define zeroext i8 @test1(i32 %y) nounwind {
   %conv = trunc i32 %y to i8
diff --git a/test/CodeGen/X86/fast-isel-select-cmov.ll b/test/CodeGen/X86/fast-isel-select-cmov.ll
index 8008e283ad60..879cd2f95ba6 100644
--- a/test/CodeGen/X86/fast-isel-select-cmov.ll
+++ b/test/CodeGen/X86/fast-isel-select-cmov.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10                  | FileCheck %s
+; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10                  | FileCheck %s
 
 ; Test conditional move for the supported types (i16, i32, and i32) and
 ; conditon input (argument or cmp). Currently i8 is not supported.
diff --git a/test/CodeGen/X86/fast-isel-select-cmov2.ll b/test/CodeGen/X86/fast-isel-select-cmov2.ll
index 658098fe7c7a..8556ff21021a 100644
--- a/test/CodeGen/X86/fast-isel-select-cmov2.ll
+++ b/test/CodeGen/X86/fast-isel-select-cmov2.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10                             | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10                               | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
 
 ; Test all the cmp predicates that can feed an integer conditional move.
 
@@ -15,10 +15,13 @@ define i64 @select_fcmp_false_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_oeq_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; CHECK-LABEL: select_fcmp_oeq_cmov
 ; CHECK:       ucomisd %xmm1, %xmm0
-; CHECK-NEXT:  setnp %al
-; CHECK-NEXT:  sete %cl
-; CHECK-NEXT:  testb %al, %cl
-; CHECK-NEXT:  cmoveq %rsi, %rdi
+; SDAG-NEXT:   cmovneq %rsi, %rdi
+; SDAG-NEXT:   cmovpq %rsi, %rdi
+; SDAG-NEXT:   movq %rdi, %rax
+; FAST-NEXT:   setnp %al
+; FAST-NEXT:   sete %cl
+; FAST-NEXT:   testb %al, %cl
+; FAST-NEXT:   cmoveq %rsi, %rdi
   %1 = fcmp oeq double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
   ret i64 %2
@@ -135,10 +138,13 @@ define i64 @select_fcmp_ule_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_une_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; CHECK-LABEL: select_fcmp_une_cmov
 ; CHECK:       ucomisd %xmm1, %xmm0
-; CHECK-NEXT:  setp %al
-; CHECK-NEXT:  setne %cl
-; CHECK-NEXT:  orb %al, %cl
-; CHECK-NEXT:  cmoveq %rsi, %rdi
+; SDAG-NEXT:   cmovneq %rdi, %rsi
+; SDAG-NEXT:   cmovpq %rdi, %rsi
+; SDAG-NEXT:   movq %rsi, %rax
+; FAST-NEXT:   setp %al
+; FAST-NEXT:   setne %cl
+; FAST-NEXT:   orb %al, %cl
+; FAST-NEXT:   cmoveq %rsi, %rdi
   %1 = fcmp une double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
   ret i64 %2
diff --git a/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll b/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll
index 1ec4d64fe209..8147035b4385 100644
--- a/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll
+++ b/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10                                              | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort                  | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1                  | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10                             -mcpu=corei7-avx | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort -mcpu=corei7-avx | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 -mcpu=corei7-avx | FileCheck %s
 
 
 define float @select_fcmp_one_f32(float %a, float %b, float %c, float %d) {
diff --git a/test/CodeGen/X86/fast-isel-select-sse.ll b/test/CodeGen/X86/fast-isel-select-sse.ll
index 3c03a0312f5e..6761be6d4e1f 100644
--- a/test/CodeGen/X86/fast-isel-select-sse.ll
+++ b/test/CodeGen/X86/fast-isel-select-sse.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10                                              | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort                  | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1                  | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10                             -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX
 
 ; Test all cmp predicates that can be used with SSE.
 
@@ -13,9 +13,7 @@ define float @select_fcmp_oeq_f32(float %a, float %b, float %c, float %d) {
 ; CHECK-NEXT:  orps    %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_oeq_f32
 ; AVX:       vcmpeqss %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandps   %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnps  %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorps    %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvps %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp oeq float %a, %b
   %2 = select i1 %1, float %c, float %d
   ret float %2
@@ -29,9 +27,7 @@ define double @select_fcmp_oeq_f64(double %a, double %b, double %c, double %d) {
 ; CHECK-NEXT:  orpd    %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_oeq_f64
 ; AVX:       vcmpeqsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandpd   %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnpd  %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorpd    %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp oeq double %a, %b
   %2 = select i1 %1, double %c, double %d
   ret double %2
@@ -45,9 +41,7 @@ define float @select_fcmp_ogt_f32(float %a, float %b, float %c, float %d) {
 ; CHECK-NEXT:  orps    %xmm2, %xmm1
 ; AVX-LABEL: select_fcmp_ogt_f32
 ; AVX:       vcmpltss %xmm0, %xmm1, %xmm0
-; AVX-NEXT:  vandps   %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnps  %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorps    %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvps %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp ogt float %a, %b
   %2 = select i1 %1, float %c, float %d
   ret float %2
@@ -61,9 +55,7 @@ define double @select_fcmp_ogt_f64(double %a, double %b, double %c, double %d) {
 ; CHECK-NEXT:  orpd    %xmm2, %xmm1
 ; AVX-LABEL: select_fcmp_ogt_f64
 ; AVX:       vcmpltsd %xmm0, %xmm1, %xmm0
-; AVX-NEXT:  vandpd   %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnpd  %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorpd    %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp ogt double %a, %b
   %2 = select i1 %1, double %c, double %d
   ret double %2
@@ -77,9 +69,7 @@ define float @select_fcmp_oge_f32(float %a, float %b, float %c, float %d) {
 ; CHECK-NEXT:  orps    %xmm2, %xmm1
 ; AVX-LABEL: select_fcmp_oge_f32
 ; AVX:       vcmpless %xmm0, %xmm1, %xmm0
-; AVX-NEXT:  vandps   %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnps  %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorps    %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvps %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp oge float %a, %b
   %2 = select i1 %1, float %c, float %d
   ret float %2
@@ -93,9 +83,7 @@ define double @select_fcmp_oge_f64(double %a, double %b, double %c, double %d) {
 ; CHECK-NEXT:  orpd    %xmm2, %xmm1
 ; AVX-LABEL: select_fcmp_oge_f64
 ; AVX:       vcmplesd %xmm0, %xmm1, %xmm0
-; AVX-NEXT:  vandpd   %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnpd  %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorpd    %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp oge double %a, %b
   %2 = select i1 %1, double %c, double %d
   ret double %2
@@ -109,9 +97,7 @@ define float @select_fcmp_olt_f32(float %a, float %b, float %c, float %d) {
 ; CHECK-NEXT:  orps    %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_olt_f32
 ; AVX:       vcmpltss %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandps   %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnps  %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorps    %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvps %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp olt float %a, %b
   %2 = select i1 %1, float %c, float %d
   ret float %2
@@ -125,9 +111,7 @@ define double @select_fcmp_olt_f64(double %a, double %b, double %c, double %d) {
 ; CHECK-NEXT:  orpd    %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_olt_f64
 ; AVX:       vcmpltsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandpd   %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnpd  %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorpd    %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp olt double %a, %b
   %2 = select i1 %1, double %c, double %d
   ret double %2
@@ -141,9 +125,7 @@ define float @select_fcmp_ole_f32(float %a, float %b, float %c, float %d) {
 ; CHECK-NEXT:  orps    %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_ole_f32
 ; AVX:       vcmpless %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandps   %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnps  %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorps    %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvps %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp ole float %a, %b
   %2 = select i1 %1, float %c, float %d
   ret float %2
@@ -157,9 +139,7 @@ define double @select_fcmp_ole_f64(double %a, double %b, double %c, double %d) {
 ; CHECK-NEXT:  orpd    %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_ole_f64
 ; AVX:       vcmplesd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandpd   %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnpd  %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorpd    %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp ole double %a, %b
   %2 = select i1 %1, double %c, double %d
   ret double %2
@@ -173,9 +153,7 @@ define float @select_fcmp_ord_f32(float %a, float %b, float %c, float %d) {
 ; CHECK-NEXT:  orps     %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_ord_f32
 ; AVX:       vcmpordss %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandps    %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnps   %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorps     %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvps %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp ord float %a, %b
   %2 = select i1 %1, float %c, float %d
   ret float %2
@@ -189,9 +167,7 @@ define double @select_fcmp_ord_f64(double %a, double %b, double %c, double %d) {
 ; CHECK-NEXT:  orpd     %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_ord_f64
 ; AVX:       vcmpordsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandpd    %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnpd   %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorpd     %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp ord double %a, %b
   %2 = select i1 %1, double %c, double %d
   ret double %2
@@ -205,9 +181,7 @@ define float @select_fcmp_uno_f32(float %a, float %b, float %c, float %d) {
 ; CHECK-NEXT:  orps       %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_uno_f32
 ; AVX:       vcmpunordss %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandps      %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnps     %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorps       %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvps %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp uno float %a, %b
   %2 = select i1 %1, float %c, float %d
   ret float %2
@@ -221,9 +195,7 @@ define double @select_fcmp_uno_f64(double %a, double %b, double %c, double %d) {
 ; CHECK-NEXT:  orpd       %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_uno_f64
 ; AVX:       vcmpunordsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandpd      %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnpd     %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorpd       %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp uno double %a, %b
   %2 = select i1 %1, double %c, double %d
   ret double %2
@@ -237,9 +209,7 @@ define float @select_fcmp_ugt_f32(float %a, float %b, float %c, float %d) {
 ; CHECK-NEXT:  orps     %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_ugt_f32
 ; AVX:       vcmpnless %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandps    %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnps   %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorps     %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvps %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp ugt float %a, %b
   %2 = select i1 %1, float %c, float %d
   ret float %2
@@ -253,9 +223,7 @@ define double @select_fcmp_ugt_f64(double %a, double %b, double %c, double %d) {
 ; CHECK-NEXT:  orpd     %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_ugt_f64
 ; AVX:       vcmpnlesd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandpd    %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnpd   %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorpd     %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp ugt double %a, %b
   %2 = select i1 %1, double %c, double %d
   ret double %2
@@ -269,9 +237,7 @@ define float @select_fcmp_uge_f32(float %a, float %b, float %c, float %d) {
 ; CHECK-NEXT:  orps     %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_uge_f32
 ; AVX:       vcmpnltss %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandps    %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnps   %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorps     %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvps %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp uge float %a, %b
   %2 = select i1 %1, float %c, float %d
   ret float %2
@@ -285,9 +251,7 @@ define double @select_fcmp_uge_f64(double %a, double %b, double %c, double %d) {
 ; CHECK-NEXT:  orpd     %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_uge_f64
 ; AVX:       vcmpnltsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandpd    %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnpd   %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorpd     %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp uge double %a, %b
   %2 = select i1 %1, double %c, double %d
   ret double %2
@@ -301,9 +265,7 @@ define float @select_fcmp_ult_f32(float %a, float %b, float %c, float %d) {
 ; CHECK-NEXT:  orps     %xmm2, %xmm1
 ; AVX-LABEL: select_fcmp_ult_f32
 ; AVX:       vcmpnless %xmm0, %xmm1, %xmm0
-; AVX-NEXT:  vandps    %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnps   %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorps     %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvps %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp ult float %a, %b
   %2 = select i1 %1, float %c, float %d
   ret float %2
@@ -317,9 +279,7 @@ define double @select_fcmp_ult_f64(double %a, double %b, double %c, double %d) {
 ; CHECK-NEXT:  orpd     %xmm2, %xmm1
 ; AVX-LABEL: select_fcmp_ult_f64
 ; AVX:       vcmpnlesd %xmm0, %xmm1, %xmm0
-; AVX-NEXT:  vandpd    %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnpd   %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorpd     %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp ult double %a, %b
   %2 = select i1 %1, double %c, double %d
   ret double %2
@@ -333,9 +293,7 @@ define float @select_fcmp_ule_f32(float %a, float %b, float %c, float %d) {
 ; CHECK-NEXT:  orps     %xmm2, %xmm1
 ; AVX-LABEL: select_fcmp_ule_f32
 ; AVX:       vcmpnltss %xmm0, %xmm1, %xmm0
-; AVX-NEXT:  vandps    %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnps   %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorps     %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvps %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp ule float %a, %b
   %2 = select i1 %1, float %c, float %d
   ret float %2
@@ -349,9 +307,7 @@ define double @select_fcmp_ule_f64(double %a, double %b, double %c, double %d) {
 ; CHECK-NEXT:  orpd     %xmm2, %xmm1
 ; AVX-LABEL: select_fcmp_ule_f64
 ; AVX:       vcmpnltsd %xmm0, %xmm1, %xmm0
-; AVX-NEXT:  vandpd    %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnpd   %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorpd     %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp ule double %a, %b
   %2 = select i1 %1, double %c, double %d
   ret double %2
@@ -365,9 +321,7 @@ define float @select_fcmp_une_f32(float %a, float %b, float %c, float %d) {
 ; CHECK-NEXT:  orps     %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_une_f32
 ; AVX:       vcmpneqss %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandps    %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnps   %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorps     %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvps %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp une float %a, %b
   %2 = select i1 %1, float %c, float %d
   ret float %2
@@ -381,9 +335,7 @@ define double @select_fcmp_une_f64(double %a, double %b, double %c, double %d) {
 ; CHECK-NEXT:  orpd     %xmm2, %xmm0
 ; AVX-LABEL: select_fcmp_une_f64
 ; AVX:       vcmpneqsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:  vandpd    %xmm2, %xmm0, %xmm1
-; AVX-NEXT:  vandnpd   %xmm3, %xmm0, %xmm0
-; AVX-NEXT:  vorpd     %xmm1, %xmm0, %xmm0
+; AVX-NEXT:  vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
   %1 = fcmp une double %a, %b
   %2 = select i1 %1, double %c, double %d
   ret double %2
diff --git a/test/CodeGen/X86/fast-isel-sext.ll b/test/CodeGen/X86/fast-isel-sext.ll
new file mode 100644
index 000000000000..ca1558e3c844
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-sext.ll
@@ -0,0 +1,9 @@
+; RUN: llc -mtriple=x86_64-linux -fast-isel -show-mc-encoding < %s | FileCheck %s
+
+; CHECK-LABEL: f:
+; CHECK:       addl $-2, %eax         # encoding: [0x83,0xc0,0xfe]
+define i32 @f(i32* %y) {
+  %x = load i32, i32* %y
+  %dec = add i32 %x, -2
+  ret i32 %dec
+}
diff --git a/test/CodeGen/X86/fast-isel-sse12-fptoint.ll b/test/CodeGen/X86/fast-isel-sse12-fptoint.ll
index 769c987e604a..2fbacbfdeae5 100644
--- a/test/CodeGen/X86/fast-isel-sse12-fptoint.ll
+++ b/test/CodeGen/X86/fast-isel-sse12-fptoint.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=SSE
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=AVX
 
 define i32 @cvt_test1(float %a) {
 ; SSE-LABEL: cvt_test1
diff --git a/test/CodeGen/X86/fast-isel-store.ll b/test/CodeGen/X86/fast-isel-store.ll
index 3d2a46c2bd1b..8fb6356be9a6 100644
--- a/test/CodeGen/X86/fast-isel-store.ll
+++ b/test/CodeGen/X86/fast-isel-store.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort -mattr=+sse2 < %s | FileCheck %s
-; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort -mattr=+sse2 < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort=1 -mattr=+sse2 < %s | FileCheck %s
+; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort=1 -mattr=+sse2 < %s | FileCheck %s
 
 define i32 @test_store_32(i32* nocapture %addr, i32 %value) {
 entry:
diff --git a/test/CodeGen/X86/fast-isel-tailcall.ll b/test/CodeGen/X86/fast-isel-tailcall.ll
index 79ff79d4bca5..88ad05e8e1a7 100644
--- a/test/CodeGen/X86/fast-isel-tailcall.ll
+++ b/test/CodeGen/X86/fast-isel-tailcall.ll
@@ -7,7 +7,7 @@
 
 define i32 @stub(i8* %t0) nounwind {
 entry:
-        %t1 = load i32* inttoptr (i32 139708680 to i32*)         ; <i32> [#uses=1]
+        %t1 = load i32, i32* inttoptr (i32 139708680 to i32*)         ; <i32> [#uses=1]
         %t2 = bitcast i8* %t0 to i32 (i32)*               ; <i32 (i32)*> [#uses=1]
         %t3 = call fastcc i32 %t2(i32 %t1)         ; <i32> [#uses=1]
         ret i32 %t3
diff --git a/test/CodeGen/X86/fast-isel-tls.ll b/test/CodeGen/X86/fast-isel-tls.ll
index 686df43ac504..18bb9c13ff01 100644
--- a/test/CodeGen/X86/fast-isel-tls.ll
+++ b/test/CodeGen/X86/fast-isel-tls.ll
@@ -4,7 +4,7 @@
 @v = thread_local global i32 0
 define i32 @f() nounwind {
 entry:
-          %t = load i32* @v
+          %t = load i32, i32* @v
           %s = add i32 %t, 1
           ret i32 %s
 }
@@ -16,7 +16,7 @@ entry:
 @alias = internal alias i32* @v
 define i32 @f_alias() nounwind {
 entry:
-          %t = load i32* @v
+          %t = load i32, i32* @v
           %s = add i32 %t, 1
           ret i32 %s
 }
diff --git a/test/CodeGen/X86/fast-isel-trunc-kill-subreg.ll b/test/CodeGen/X86/fast-isel-trunc-kill-subreg.ll
new file mode 100644
index 000000000000..96a1a2dea179
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-trunc-kill-subreg.ll
@@ -0,0 +1,40 @@
+; RUN: llc %s -o - -fast-isel=true -O1 -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-unknown"
+
+; This test failed the machine verifier because the trunc at the start of the
+; method was extracing a subreg and killing the source register.  The kill flag was
+; invalid here as the source of the trunc could still be used elsewhere.
+
+; CHECK-LABEL: @test
+
+define i32 @test(i32 %block8x8) {
+bb:
+  %tmp9 = trunc i32 %block8x8 to i1
+  %tmp10 = zext i1 %tmp9 to i32
+  %tmp11 = mul i32 %tmp10, 8
+  %tmp12 = zext i32 %tmp11 to i64
+  br label %bb241
+
+bb241:                                            ; preds = %bb241, %bb
+  %lsr.iv3 = phi i64 [ %lsr.iv.next4, %bb241 ], [ %tmp12, %bb ]
+  %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb241 ], [ 0, %bb ]
+  %lsr.iv.next2 = add nuw nsw i32 %lsr.iv1, 1
+  %lsr.iv.next4 = add i64 %lsr.iv3, 32
+  %exitcond = icmp eq i32 %lsr.iv.next2, 8
+  br i1 %exitcond, label %.preheader.preheader, label %bb241
+
+.preheader.preheader:                             ; preds = %bb241
+  %tmp18 = lshr i32 %block8x8, 1
+  br label %bb270
+
+bb270:                                            ; preds = %bb270, %.preheader.preheader
+  %lsr.iv = phi i32 [ %lsr.iv.next, %bb270 ], [ %tmp18, %.preheader.preheader ]
+  %lsr.iv.next = add i32 %lsr.iv, 4
+  %tmp272 = icmp slt i32 %lsr.iv.next, 100
+  br i1 %tmp272, label %bb270, label %.loopexit
+
+.loopexit:                                        ; preds = %bb270
+  ret i32 0
+}
diff --git a/test/CodeGen/X86/fast-isel-vecload.ll b/test/CodeGen/X86/fast-isel-vecload.ll
new file mode 100644
index 000000000000..48eebf526f19
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-vecload.ll
@@ -0,0 +1,185 @@
+; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE --check-prefix=ALL
+; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX --check-prefix=ALL
+
+; Verify that fast-isel knows how to select aligned/unaligned vector loads.
+; Also verify that the selected load instruction is in the correct domain.
+
+define <16 x i8> @test_v16i8(<16 x i8>* %V) {
+; ALL-LABEL: test_v16i8:
+; SSE: movdqa  (%rdi), %xmm0
+; AVX: vmovdqa  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %V, align 16
+  ret <16 x i8> %0
+}
+
+define <8 x i16> @test_v8i16(<8 x i16>* %V) {
+; ALL-LABEL: test_v8i16:
+; SSE: movdqa  (%rdi), %xmm0
+; AVX: vmovdqa  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <8 x i16>, <8 x i16>* %V, align 16
+  ret <8 x i16> %0
+}
+
+define <4 x i32> @test_v4i32(<4 x i32>* %V) {
+; ALL-LABEL: test_v4i32:
+; SSE: movdqa  (%rdi), %xmm0
+; AVX: vmovdqa  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <4 x i32>, <4 x i32>* %V, align 16
+  ret <4 x i32> %0
+}
+
+define <2 x i64> @test_v2i64(<2 x i64>* %V) {
+; ALL-LABEL: test_v2i64:
+; SSE: movdqa  (%rdi), %xmm0
+; AVX: vmovdqa  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <2 x i64>, <2 x i64>* %V, align 16
+  ret <2 x i64> %0
+}
+
+define <16 x i8> @test_v16i8_unaligned(<16 x i8>* %V) {
+; ALL-LABEL: test_v16i8_unaligned:
+; SSE: movdqu  (%rdi), %xmm0
+; AVX: vmovdqu  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %V, align 4
+  ret <16 x i8> %0
+}
+
+define <8 x i16> @test_v8i16_unaligned(<8 x i16>* %V) {
+; ALL-LABEL: test_v8i16_unaligned:
+; SSE: movdqu  (%rdi), %xmm0
+; AVX: vmovdqu  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <8 x i16>, <8 x i16>* %V, align 4
+  ret <8 x i16> %0
+}
+
+define <4 x i32> @test_v4i32_unaligned(<4 x i32>* %V) {
+; ALL-LABEL: test_v4i32_unaligned:
+; SSE: movdqu  (%rdi), %xmm0
+; AVX: vmovdqu  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <4 x i32>, <4 x i32>* %V, align 4
+  ret <4 x i32> %0
+}
+
+define <2 x i64> @test_v2i64_unaligned(<2 x i64>* %V) {
+; ALL-LABEL: test_v2i64_unaligned:
+; SSE: movdqu  (%rdi), %xmm0
+; AVX: vmovdqu  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <2 x i64>, <2 x i64>* %V, align 4
+  ret <2 x i64> %0
+}
+
+define <4 x float> @test_v4f32(<4 x float>* %V) {
+; ALL-LABEL: test_v4f32:
+; SSE: movaps  (%rdi), %xmm0
+; AVX: vmovaps  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <4 x float>, <4 x float>* %V, align 16
+  ret <4 x float> %0
+}
+
+define <2 x double> @test_v2f64(<2 x double>* %V) {
+; ALL-LABEL: test_v2f64:
+; SSE: movapd  (%rdi), %xmm0
+; AVX: vmovapd  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <2 x double>, <2 x double>* %V, align 16
+  ret <2 x double> %0
+}
+
+define <4 x float> @test_v4f32_unaligned(<4 x float>* %V) {
+; ALL-LABEL: test_v4f32_unaligned:
+; SSE: movups  (%rdi), %xmm0
+; AVX: vmovups  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <4 x float>, <4 x float>* %V, align 4
+  ret <4 x float> %0
+}
+
+define <2 x double> @test_v2f64_unaligned(<2 x double>* %V) {
+; ALL-LABEL: test_v2f64_unaligned:
+; SSE: movupd  (%rdi), %xmm0
+; AVX: vmovupd  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <2 x double>, <2 x double>* %V, align 4
+  ret <2 x double> %0
+}
+
+define <16 x i8> @test_v16i8_abi_alignment(<16 x i8>* %V) {
+; ALL-LABEL: test_v16i8_abi_alignment:
+; SSE: movdqa  (%rdi), %xmm0
+; AVX: vmovdqa  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %V
+  ret <16 x i8> %0
+}
+
+define <8 x i16> @test_v8i16_abi_alignment(<8 x i16>* %V) {
+; ALL-LABEL: test_v8i16_abi_alignment:
+; SSE: movdqa  (%rdi), %xmm0
+; AVX: vmovdqa  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <8 x i16>, <8 x i16>* %V
+  ret <8 x i16> %0
+}
+
+define <4 x i32> @test_v4i32_abi_alignment(<4 x i32>* %V) {
+; ALL-LABEL: test_v4i32_abi_alignment:
+; SSE: movdqa  (%rdi), %xmm0
+; AVX: vmovdqa  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <4 x i32>, <4 x i32>* %V
+  ret <4 x i32> %0
+}
+
+define <2 x i64> @test_v2i64_abi_alignment(<2 x i64>* %V) {
+; ALL-LABEL: test_v2i64_abi_alignment:
+; SSE: movdqa  (%rdi), %xmm0
+; AVX: vmovdqa  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <2 x i64>, <2 x i64>* %V
+  ret <2 x i64> %0
+}
+
+define <4 x float> @test_v4f32_abi_alignment(<4 x float>* %V) {
+; ALL-LABEL: test_v4f32_abi_alignment:
+; SSE: movaps  (%rdi), %xmm0
+; AVX: vmovaps  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <4 x float>, <4 x float>* %V
+  ret <4 x float> %0
+}
+
+define <2 x double> @test_v2f64_abi_alignment(<2 x double>* %V) {
+; ALL-LABEL: test_v2f64_abi_alignment:
+; SSE: movapd  (%rdi), %xmm0
+; AVX: vmovapd  (%rdi), %xmm0
+; ALL-NEXT: retq
+entry:
+  %0 = load <2 x double>, <2 x double>* %V
+  ret <2 x double> %0
+}
diff --git a/test/CodeGen/X86/fast-isel-x32.ll b/test/CodeGen/X86/fast-isel-x32.ll
index d49a10801065..7b95325f562d 100644
--- a/test/CodeGen/X86/fast-isel-x32.ll
+++ b/test/CodeGen/X86/fast-isel-x32.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -fast-isel -fast-isel-abort | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -fast-isel -fast-isel-abort=1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; Test that alloca addresses are materialized with the right size instruction.
 
diff --git a/test/CodeGen/X86/fast-isel-x86-64.ll b/test/CodeGen/X86/fast-isel-x86-64.ll
index 3747d049424d..d748cba2f8f8 100644
--- a/test/CodeGen/X86/fast-isel-x86-64.ll
+++ b/test/CodeGen/X86/fast-isel-x86-64.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mattr=-avx -fast-isel -mcpu=core2 -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort | FileCheck %s
-; RUN: llc < %s -mattr=+avx -fast-isel -mcpu=core2 -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort | FileCheck %s --check-prefix=AVX
+; RUN: llc < %s -mattr=-avx -fast-isel -mcpu=core2 -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort=1 | FileCheck %s
+; RUN: llc < %s -mattr=+avx -fast-isel -mcpu=core2 -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort=1 | FileCheck %s --check-prefix=AVX
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10.0.0"
@@ -20,7 +20,7 @@ define void @test2(i64 %x) nounwind ssp {
 entry:
   %x.addr = alloca i64, align 8
   store i64 %x, i64* %x.addr, align 8
-  %tmp = load i64* %x.addr, align 8
+  %tmp = load i64, i64* %x.addr, align 8
   %cmp = icmp sgt i64 %tmp, 42
   br i1 %cmp, label %if.then, label %if.end
 
@@ -52,8 +52,8 @@ define i64 @test3() nounwind {
 @rtx_length = external global [153 x i8]
 
 define i32 @test4(i64 %idxprom9) nounwind {
-  %arrayidx10 = getelementptr inbounds [153 x i8]* @rtx_length, i32 0, i64 %idxprom9
-  %tmp11 = load i8* %arrayidx10, align 1
+  %arrayidx10 = getelementptr inbounds [153 x i8], [153 x i8]* @rtx_length, i32 0, i64 %idxprom9
+  %tmp11 = load i8, i8* %arrayidx10, align 1
   %conv = zext i8 %tmp11 to i32
   ret i32 %conv
 
@@ -190,7 +190,7 @@ define void @test16() nounwind {
 ; CHECK: movl $1, %edi
 ; CHECK: movb $0, %al
 ; CHECK: callq _test16callee
-  call void (...)* @test16callee(i32 1)
+  call void (...) @test16callee(i32 1)
   br label %block2
 
 block2:
@@ -201,7 +201,7 @@ block2:
 ; AVX: vmovsd LCP{{.*}}_{{.*}}(%rip), %xmm0
 ; AVX: movb $1, %al
 ; AVX: callq _test16callee
-  call void (...)* @test16callee(double 1.000000e+00)
+  call void (...) @test16callee(double 1.000000e+00)
   ret void
 }
 
@@ -212,7 +212,7 @@ declare void @foo() unnamed_addr ssp align 2
 ; w.r.t. the call.
 define i32 @test17(i32 *%P) ssp nounwind {
 entry:
-  %tmp = load i32* %P
+  %tmp = load i32, i32* %P
   %cmp = icmp ne i32 %tmp, 5
   call void @foo()
   br i1 %cmp, label %if.then, label %if.else
diff --git a/test/CodeGen/X86/fast-isel-x86.ll b/test/CodeGen/X86/fast-isel-x86.ll
index 61e9b98f6e7e..8049c72ec018 100644
--- a/test/CodeGen/X86/fast-isel-x86.ll
+++ b/test/CodeGen/X86/fast-isel-x86.ll
@@ -6,7 +6,7 @@
 ; CHECK: retl
 @G = external global float
 define float @test0() nounwind {
-  %t = load float* @G
+  %t = load float, float* @G
   ret float %t
 }
 
@@ -28,7 +28,7 @@ define void @test1({i32, i32, i32, i32}* sret %p) nounwind {
 ; CHECK: retl
 @HHH = external global i32
 define i32 @test2() nounwind {
-  %t = load i32* @HHH
+  %t = load i32, i32* @HHH
   ret i32 %t
 }
 
diff --git a/test/CodeGen/X86/fast-isel.ll b/test/CodeGen/X86/fast-isel.ll
index bc7918421603..36183e48c299 100644
--- a/test/CodeGen/X86/fast-isel.ll
+++ b/test/CodeGen/X86/fast-isel.ll
@@ -1,13 +1,13 @@
-; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -march=x86 -mattr=sse2 -no-integrated-as
-; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=x86_64-apple-darwin10 -no-integrated-as
+; RUN: llc < %s -fast-isel -fast-isel-abort=1 -verify-machineinstrs -march=x86 -mattr=sse2 -no-integrated-as
+; RUN: llc < %s -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=x86_64-apple-darwin10 -no-integrated-as
 
 ; This tests very minimal fast-isel functionality.
 
 define i32* @foo(i32* %p, i32* %q, i32** %z) nounwind {
 entry:
-  %r = load i32* %p
-  %s = load i32* %q
-  %y = load i32** %z
+  %r = load i32, i32* %p
+  %s = load i32, i32* %q
+  %y = load i32*, i32** %z
   br label %fast
 
 fast:
@@ -18,8 +18,8 @@ fast:
   %t4 = xor i32 %t3, 3
   %t5 = xor i32 %t4, %s
   %t6 = add i32 %t5, 2
-  %t7 = getelementptr i32* %y, i32 1
-  %t8 = getelementptr i32* %t7, i32 %t6
+  %t7 = getelementptr i32, i32* %y, i32 1
+  %t8 = getelementptr i32, i32* %t7, i32 %t6
   call void asm sideeffect "hello world", ""()
   br label %exit
 
@@ -29,8 +29,8 @@ exit:
 
 define void @bar(double* %p, double* %q) nounwind {
 entry:
-  %r = load double* %p
-  %s = load double* %q
+  %r = load double, double* %p
+  %s = load double, double* %q
   br label %fast
 
 fast:
@@ -94,7 +94,7 @@ define void @mul_i8(i8 %a, i8* %p) nounwind {
 }
 
 define void @load_store_i1(i1* %p, i1* %q) nounwind {
-  %t = load i1* %p
+  %t = load i1, i1* %p
   store i1 %t, i1* %q
   ret void
 }
@@ -102,7 +102,7 @@ define void @load_store_i1(i1* %p, i1* %q) nounwind {
 @crash_test1x = external global <2 x i32>, align 8
 
 define void @crash_test1() nounwind ssp {
-  %tmp = load <2 x i32>* @crash_test1x, align 8
+  %tmp = load <2 x i32>, <2 x i32>* @crash_test1x, align 8
   %neg = xor <2 x i32> %tmp, <i32 -1, i32 -1>
   ret void
 }
@@ -113,7 +113,7 @@ define i64* @life() nounwind {
   %a1 = alloca i64*, align 8
   %a2 = bitcast i64** %a1 to i8*
   call void @llvm.lifetime.start(i64 -1, i8* %a2) nounwind      
-  %a3 = load i64** %a1, align 8
+  %a3 = load i64*, i64** %a1, align 8
   ret i64* %a3
 }
 
diff --git a/test/CodeGen/X86/fastcall-correct-mangling.ll b/test/CodeGen/X86/fastcall-correct-mangling.ll
index 00dc44e75e8f..bc53fe8aa4ec 100644
--- a/test/CodeGen/X86/fastcall-correct-mangling.ll
+++ b/test/CodeGen/X86/fastcall-correct-mangling.ll
@@ -28,6 +28,6 @@ entry:
 define private x86_fastcallcc void @dontCrash() {
 ; The name is fairly arbitrary since it is private. Just don't crash.
 ; CHECK32-LABEL: {{^}}L@dontCrash@0:
-; CHECK64-LABEL: {{^}}.LdontCrash:
+; CHECK64-LABEL: {{^}}LdontCrash:
   ret void
 }
diff --git a/test/CodeGen/X86/fastcc-byval.ll b/test/CodeGen/X86/fastcc-byval.ll
index e6828e42827c..1706de461116 100644
--- a/test/CodeGen/X86/fastcc-byval.ll
+++ b/test/CodeGen/X86/fastcc-byval.ll
@@ -14,10 +14,10 @@ target triple = "i386-apple-darwin9.5"
 
 define fastcc i32 @bar() nounwind {
 	%V = alloca %struct.MVT
-	%a = getelementptr %struct.MVT* %V, i32 0, i32 0
+	%a = getelementptr %struct.MVT, %struct.MVT* %V, i32 0, i32 0
 	store i32 1, i32* %a
 	call fastcc void @foo(%struct.MVT* byval %V) nounwind
-	%t = load i32* %a
+	%t = load i32, i32* %a
 	ret i32 %t
 }
 
diff --git a/test/CodeGen/X86/fastcc-sret.ll b/test/CodeGen/X86/fastcc-sret.ll
index 97814dbabdcc..499aadda44fa 100644
--- a/test/CodeGen/X86/fastcc-sret.ll
+++ b/test/CodeGen/X86/fastcc-sret.ll
@@ -4,8 +4,8 @@
 
 define fastcc void @bar(%struct.foo* noalias sret %agg.result) nounwind  {
 entry:
-	%tmp1 = getelementptr %struct.foo* %agg.result, i32 0, i32 0
-	%tmp3 = getelementptr [4 x i32]* %tmp1, i32 0, i32 0
+	%tmp1 = getelementptr %struct.foo, %struct.foo* %agg.result, i32 0, i32 0
+	%tmp3 = getelementptr [4 x i32], [4 x i32]* %tmp1, i32 0, i32 0
 	store i32 1, i32* %tmp3, align 8
         ret void
 }
@@ -17,9 +17,9 @@ entry:
 define void @foo() nounwind {
 	%memtmp = alloca %struct.foo, align 4
         call fastcc void @bar( %struct.foo* sret %memtmp ) nounwind
-        %tmp4 = getelementptr %struct.foo* %memtmp, i32 0, i32 0
-	%tmp5 = getelementptr [4 x i32]* %tmp4, i32 0, i32 0
-        %tmp6 = load i32* %tmp5
+        %tmp4 = getelementptr %struct.foo, %struct.foo* %memtmp, i32 0, i32 0
+	%tmp5 = getelementptr [4 x i32], [4 x i32]* %tmp4, i32 0, i32 0
+        %tmp6 = load i32, i32* %tmp5
         store i32 %tmp6, i32* @dst
         ret void
 }
diff --git a/test/CodeGen/X86/fastcc.ll b/test/CodeGen/X86/fastcc.ll
index a362f8d1ca7e..020e7f9d3532 100644
--- a/test/CodeGen/X86/fastcc.ll
+++ b/test/CodeGen/X86/fastcc.ll
@@ -9,10 +9,10 @@
 
 define i32 @foo() nounwind {
 entry:
-	%0 = load double* @d, align 8		; <double> [#uses=1]
-	%1 = load double* @c, align 8		; <double> [#uses=1]
-	%2 = load double* @b, align 8		; <double> [#uses=1]
-	%3 = load double* @a, align 8		; <double> [#uses=1]
+	%0 = load double, double* @d, align 8		; <double> [#uses=1]
+	%1 = load double, double* @c, align 8		; <double> [#uses=1]
+	%2 = load double, double* @b, align 8		; <double> [#uses=1]
+	%3 = load double, double* @a, align 8		; <double> [#uses=1]
 	tail call fastcc void @bar( i32 0, i32 1, i32 2, double 1.000000e+00, double %3, double %2, double %1, double %0 ) nounwind
 	ret i32 0
 }
diff --git a/test/CodeGen/X86/fastisel-gep-promote-before-add.ll b/test/CodeGen/X86/fastisel-gep-promote-before-add.ll
index f87a34c4abde..1f67299a8045 100644
--- a/test/CodeGen/X86/fastisel-gep-promote-before-add.ll
+++ b/test/CodeGen/X86/fastisel-gep-promote-before-add.ll
@@ -6,13 +6,13 @@ define zeroext i8 @gep_promotion(i8* %ptr) nounwind uwtable ssp {
 entry:
   %ptr.addr = alloca i8*, align 8
   %add = add i8 64, 64 ; 0x40 + 0x40
-  %0 = load i8** %ptr.addr, align 8
+  %0 = load i8*, i8** %ptr.addr, align 8
 
   ; CHECK-LABEL: _gep_promotion:
   ; CHECK: movzbl ({{.*}})
-  %arrayidx = getelementptr inbounds i8* %0, i8 %add
+  %arrayidx = getelementptr inbounds i8, i8* %0, i8 %add
 
-  %1 = load i8* %arrayidx, align 1
+  %1 = load i8, i8* %arrayidx, align 1
   ret i8 %1
 }
 
@@ -22,16 +22,16 @@ entry:
   %ptr.addr = alloca i8*, align 8
   store i8 %i, i8* %i.addr, align 4
   store i8* %ptr, i8** %ptr.addr, align 8
-  %0 = load i8* %i.addr, align 4
+  %0 = load i8, i8* %i.addr, align 4
   ; CHECK-LABEL: _gep_promotion_nonconst:
   ; CHECK: movzbl ({{.*}})
   %xor = xor i8 %0, -128   ; %0   ^ 0x80
   %add = add i8 %xor, -127 ; %xor + 0x81
-  %1 = load i8** %ptr.addr, align 8
+  %1 = load i8*, i8** %ptr.addr, align 8
 
-  %arrayidx = getelementptr inbounds i8* %1, i8 %add
+  %arrayidx = getelementptr inbounds i8, i8* %1, i8 %add
 
-  %2 = load i8* %arrayidx, align 1
+  %2 = load i8, i8* %arrayidx, align 1
   ret i8 %2
 }
 
diff --git a/test/CodeGen/X86/fastmath-float-half-conversion.ll b/test/CodeGen/X86/fastmath-float-half-conversion.ll
new file mode 100644
index 000000000000..29308735cca2
--- /dev/null
+++ b/test/CodeGen/X86/fastmath-float-half-conversion.ll
@@ -0,0 +1,52 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+f16c < %s | FileCheck %s --check-prefix=ALL --check-prefix=F16C
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX
+
+define zeroext i16 @test1_fast(double %d) #0 {
+; ALL-LABEL: test1_fast:
+; F16C-NOT: callq {{_+}}truncdfhf2
+; F16C: vcvtsd2ss %xmm0, %xmm0, %xmm0
+; F16C-NEXT: vcvtps2ph $0, %xmm0, %xmm0
+; AVX: callq {{_+}}truncdfhf2
+; ALL: ret
+entry:
+  %0 = tail call i16 @llvm.convert.to.fp16.f64(double %d)
+  ret i16 %0
+}
+
+define zeroext i16 @test2_fast(x86_fp80 %d) #0 {
+; ALL-LABEL: test2_fast:
+; F16C-NOT: callq {{_+}}truncxfhf2
+; F16C: fldt
+; F16C-NEXT: fstps
+; F16C-NEXT: vmovss
+; F16C-NEXT: vcvtps2ph $0, %xmm0, %xmm0
+; AVX: callq {{_+}}truncxfhf2
+; ALL: ret
+entry:
+  %0 = tail call i16 @llvm.convert.to.fp16.f80(x86_fp80 %d)
+  ret i16 %0
+}
+
+define zeroext i16 @test1(double %d) #1 {
+; ALL-LABEL: test1:
+; ALL: callq  {{_+}}truncdfhf2
+; ALL: ret
+entry:
+  %0 = tail call i16 @llvm.convert.to.fp16.f64(double %d)
+  ret i16 %0
+}
+
+define zeroext i16 @test2(x86_fp80 %d) #1 {
+; ALL-LABEL: test2:
+; ALL: callq  {{_+}}truncxfhf2
+; ALL: ret
+entry:
+  %0 = tail call i16 @llvm.convert.to.fp16.f80(x86_fp80 %d)
+  ret i16 %0
+}
+
+declare i16 @llvm.convert.to.fp16.f64(double)
+declare i16 @llvm.convert.to.fp16.f80(x86_fp80)
+
+attributes #0 = { nounwind readnone uwtable "unsafe-fp-math"="true" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone uwtable "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/CodeGen/X86/fcmove.ll b/test/CodeGen/X86/fcmove.ll
new file mode 100644
index 000000000000..21cc683f734f
--- /dev/null
+++ b/test/CodeGen/X86/fcmove.ll
@@ -0,0 +1,15 @@
+; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-unknown"
+
+; Test that we can generate an fcmove, and also that it passes verification.
+
+; CHECK-LABEL: cmove_f
+; CHECK: fcmove %st({{[0-7]}}), %st(0)
+define x86_fp80 @cmove_f(x86_fp80 %a, x86_fp80 %b, i32 %c) {
+  %test = icmp eq i32 %c, 0
+  %add = fadd x86_fp80 %a, %b
+  %ret = select i1 %test, x86_fp80 %add, x86_fp80 %b
+  ret x86_fp80 %ret
+}
\ No newline at end of file
diff --git a/test/CodeGen/X86/fdiv-combine.ll b/test/CodeGen/X86/fdiv-combine.ll
new file mode 100644
index 000000000000..279bb0624ace
--- /dev/null
+++ b/test/CodeGen/X86/fdiv-combine.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+; Anything more than one division using a single divisor operand
+; should be converted into a reciprocal and multiplication.
+
+define float @div1_arcp(float %x, float %y, float %z) #0 {
+; CHECK-LABEL: div1_arcp:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    divss %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %div1 = fdiv arcp float %x, %y
+  ret float %div1
+}
+
+define float @div2_arcp(float %x, float %y, float %z) #0 {
+; CHECK-LABEL: div2_arcp:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; CHECK-NEXT:    divss %xmm2, %xmm3
+; CHECK-NEXT:    mulss %xmm3, %xmm0
+; CHECK-NEXT:    mulss %xmm1, %xmm0
+; CHECK-NEXT:    mulss %xmm3, %xmm0
+; CHECK-NEXT:    retq
+  %div1 = fdiv arcp float %x, %z
+  %mul = fmul arcp float %div1, %y
+  %div2 = fdiv arcp float %mul, %z
+  ret float %div2
+}
+
+; FIXME: If the backend understands 'arcp', then this attribute is unnecessary.
+attributes #0 = { "unsafe-fp-math"="true" }
diff --git a/test/CodeGen/X86/float-conv-elim.ll b/test/CodeGen/X86/float-conv-elim.ll
new file mode 100644
index 000000000000..3feff851d91a
--- /dev/null
+++ b/test/CodeGen/X86/float-conv-elim.ll
@@ -0,0 +1,32 @@
+; RUN: llc -march=x86-64 -mcpu=x86-64 < %s | FileCheck %s
+
+; Make sure the float conversion is folded away as it should be.
+; CHECK-LABEL: foo
+; CHECK-NOT: cvt
+; CHECK: movzbl
+define i32 @foo(i8 %a) #0 {
+  %conv = uitofp i8 %a to float
+  %conv1 = fptosi float %conv to i32
+  ret i32 %conv1
+}
+
+; CHECK-LABEL: foo2
+; CHECK-NOT: cvt
+; CHECK: movsbl
+define i32 @foo2(i8 %a) #0 {
+  %conv = sitofp i8 %a to float
+  %conv1 = fptosi float %conv to i32
+  ret i32 %conv1
+}
+
+; CHECK-LABEL: bar
+; CHECK-NOT: cvt
+; CHECK: movl
+define zeroext i8 @bar(i8 zeroext %a) #0 {
+  %conv = uitofp i8 %a to float
+  %conv1 = fptoui float %conv to i8
+  ret i8 %conv1
+}
+
+attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
diff --git a/test/CodeGen/X86/floor-soft-float.ll b/test/CodeGen/X86/floor-soft-float.ll
index 5644509a86f7..7bb738513f54 100644
--- a/test/CodeGen/X86/floor-soft-float.ll
+++ b/test/CodeGen/X86/floor-soft-float.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=x86-64 -mattr=+sse4.1,-avx -soft-float=0 | FileCheck %s --check-prefix=CHECK-HARD-FLOAT
-; RUN: llc < %s -march=x86-64 -mattr=+sse4.1,-avx -soft-float=1 | FileCheck %s --check-prefix=CHECK-SOFT-FLOAT
+; RUN: llc < %s -march=x86-64 -mattr=+sse4.1,-avx | FileCheck %s --check-prefix=CHECK-HARD-FLOAT
+; RUN: llc < %s -march=x86-64 -mattr=+sse4.1,-avx,+soft-float | FileCheck %s --check-prefix=CHECK-SOFT-FLOAT
 
 target triple = "x86_64-unknown-linux-gnu"
 
diff --git a/test/CodeGen/X86/fltused.ll b/test/CodeGen/X86/fltused.ll
index 81511a33f5cb..6c5d8cefeba9 100644
--- a/test/CodeGen/X86/fltused.ll
+++ b/test/CodeGen/X86/fltused.ll
@@ -11,7 +11,7 @@
 
 define i32 @main() nounwind {
 entry:
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), double 1.000000e+000) nounwind
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), double 1.000000e+000) nounwind
   ret i32 0
 }
 
diff --git a/test/CodeGen/X86/fltused_function_pointer.ll b/test/CodeGen/X86/fltused_function_pointer.ll
index cfe484a8c258..a41ae48a5fb7 100644
--- a/test/CodeGen/X86/fltused_function_pointer.ll
+++ b/test/CodeGen/X86/fltused_function_pointer.ll
@@ -11,7 +11,7 @@
 
 define i32 @foo(i32 (i8*, ...)* %f) nounwind {
 entry:
-  %call = tail call i32 (i8*, ...)* %f(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), double 1.000000e+000) nounwind
+  %call = tail call i32 (i8*, ...) %f(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), double 1.000000e+000) nounwind
   ret i32 0
 }
 
diff --git a/test/CodeGen/X86/fma-do-not-commute.ll b/test/CodeGen/X86/fma-do-not-commute.ll
index 4e211721a382..1f6a19cfff83 100644
--- a/test/CodeGen/X86/fma-do-not-commute.ll
+++ b/test/CodeGen/X86/fma-do-not-commute.ll
@@ -18,8 +18,8 @@ entry:
 
 loop:
   %sum0 = phi float [ %fma, %loop ], [ %arg, %entry ]
-  %addrVal = load float* %addr, align 4
-  %addr2Val = load float* %addr2, align 4
+  %addrVal = load float, float* %addr, align 4
+  %addr2Val = load float, float* %addr2, align 4
   %fmul = fmul float %addrVal, %addr2Val
   %fma = fadd float %sum0, %fmul
   br i1 true, label %exit, label %loop
diff --git a/test/CodeGen/X86/fma3-intrinsics.ll b/test/CodeGen/X86/fma3-intrinsics.ll
index 9a25096c7a52..fa9c252f30b4 100755
--- a/test/CodeGen/X86/fma3-intrinsics.ll
+++ b/test/CodeGen/X86/fma3-intrinsics.ll
@@ -3,7 +3,9 @@
 ; RUN: llc < %s -mcpu=bdver2 -mtriple=x86_64-pc-win32 -mattr=-fma4 | FileCheck %s
 
 define <4 x float> @test_x86_fmadd_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
-  ; CHECK: fmadd213ss (%r8), %xmm
+  ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]]
+  ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]]
+  ; CHECK: fmadd213ss (%r8), [[XMM1]], [[XMM0]]
   %res = call <4 x float> @llvm.x86.fma.vfmadd.ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) nounwind
   ret <4 x float> %res
 }
@@ -24,7 +26,9 @@ define <8 x float> @test_x86_fmadd_ps_y(<8 x float> %a0, <8 x float> %a1, <8 x f
 declare <8 x float> @llvm.x86.fma.vfmadd.ps.256(<8 x float>, <8 x float>, <8 x float>) nounwind readnone
 
 define <4 x float> @test_x86_fnmadd_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
-  ; CHECK: fnmadd213ss (%r8), %xmm
+  ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]]
+  ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]]
+  ; CHECK: fnmadd213ss (%r8), [[XMM1]], [[XMM0]]
   %res = call <4 x float> @llvm.x86.fma.vfnmadd.ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) nounwind
   ret <4 x float> %res
 }
@@ -46,7 +50,9 @@ declare <8 x float> @llvm.x86.fma.vfnmadd.ps.256(<8 x float>, <8 x float>, <8 x
 
 
 define <4 x float> @test_x86_fmsub_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
-  ; CHECK: fmsub213ss
+  ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]]
+  ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]]
+  ; CHECK: fmsub213ss (%r8), [[XMM1]], [[XMM0]]
   %res = call <4 x float> @llvm.x86.fma.vfmsub.ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) nounwind
   ret <4 x float> %res
 }
@@ -60,7 +66,9 @@ define <4 x float> @test_x86_fmsub_ps(<4 x float> %a0, <4 x float> %a1, <4 x flo
 declare <4 x float> @llvm.x86.fma.vfmsub.ps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
 
 define <4 x float> @test_x86_fnmsub_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
-  ; CHECK: fnmsub213ss
+  ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]]
+  ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]]
+  ; CHECK: fnmsub213ss (%r8), [[XMM1]], [[XMM0]]
   %res = call <4 x float> @llvm.x86.fma.vfnmsub.ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) nounwind
   ret <4 x float> %res
 }
@@ -76,7 +84,9 @@ declare <4 x float> @llvm.x86.fma.vfnmsub.ps(<4 x float>, <4 x float>, <4 x floa
 ;;;;
 
 define <2 x double> @test_x86_fmadd_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) {
-  ; CHECK: fmadd213sd
+  ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]]
+  ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]]
+  ; CHECK: fmadd213sd (%r8), [[XMM1]], [[XMM0]]
   %res = call <2 x double> @llvm.x86.fma.vfmadd.sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) nounwind
   ret <2 x double> %res
 }
@@ -90,7 +100,9 @@ define <2 x double> @test_x86_fmadd_pd(<2 x double> %a0, <2 x double> %a1, <2 x
 declare <2 x double> @llvm.x86.fma.vfmadd.pd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone
 
 define <2 x double> @test_x86_fnmadd_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) {
-  ; CHECK: fnmadd213sd
+  ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]]
+  ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]]
+  ; CHECK: fnmadd213sd (%r8), [[XMM1]], [[XMM0]]
   %res = call <2 x double> @llvm.x86.fma.vfnmadd.sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) nounwind
   ret <2 x double> %res
 }
@@ -106,7 +118,9 @@ declare <2 x double> @llvm.x86.fma.vfnmadd.pd(<2 x double>, <2 x double>, <2 x d
 
 
 define <2 x double> @test_x86_fmsub_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) {
-  ; CHECK: fmsub213sd
+  ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]]
+  ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]]
+  ; CHECK: fmsub213sd (%r8), [[XMM1]], [[XMM0]]
   %res = call <2 x double> @llvm.x86.fma.vfmsub.sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) nounwind
   ret <2 x double> %res
 }
@@ -120,7 +134,9 @@ define <2 x double> @test_x86_fmsub_pd(<2 x double> %a0, <2 x double> %a1, <2 x
 declare <2 x double> @llvm.x86.fma.vfmsub.pd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone
 
 define <2 x double> @test_x86_fnmsub_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) {
-  ; CHECK: fnmsub213sd
+  ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]]
+  ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]]
+  ; CHECK: fnmsub213sd (%r8), [[XMM1]], [[XMM0]]
   %res = call <2 x double> @llvm.x86.fma.vfnmsub.sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) nounwind
   ret <2 x double> %res
 }
diff --git a/test/CodeGen/X86/fma4-intrinsics-x86_64-folded-load.ll b/test/CodeGen/X86/fma4-intrinsics-x86_64-folded-load.ll
index 64a2068aea43..85de1ef5c9dc 100644
--- a/test/CodeGen/X86/fma4-intrinsics-x86_64-folded-load.ll
+++ b/test/CodeGen/X86/fma4-intrinsics-x86_64-folded-load.ll
@@ -4,14 +4,14 @@
 ; VFMADD
 define < 4 x float > @test_x86_fma_vfmadd_ss_load(< 4 x float > %a0, < 4 x float > %a1, float* %a2) {
   ; CHECK: vfmaddss (%{{.*}})
-  %x = load float *%a2
+  %x = load float , float *%a2
   %y = insertelement <4 x float> undef, float %x, i32 0
   %res = call < 4 x float > @llvm.x86.fma.vfmadd.ss(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %y)
   ret < 4 x float > %res
 }
 define < 4 x float > @test_x86_fma_vfmadd_ss_load2(< 4 x float > %a0, float* %a1, < 4 x float > %a2) {
   ; CHECK: vfmaddss %{{.*}}, (%{{.*}})
-  %x = load float *%a1
+  %x = load float , float *%a1
   %y = insertelement <4 x float> undef, float %x, i32 0
   %res = call < 4 x float > @llvm.x86.fma.vfmadd.ss(< 4 x float > %a0, < 4 x float > %y, < 4 x float > %a2)
   ret < 4 x float > %res
@@ -21,14 +21,14 @@ declare < 4 x float > @llvm.x86.fma.vfmadd.ss(< 4 x float >, < 4 x float >, < 4
 
 define < 2 x double > @test_x86_fma_vfmadd_sd_load(< 2 x double > %a0, < 2 x double > %a1, double* %a2) {
   ; CHECK: vfmaddsd (%{{.*}})
-  %x = load double *%a2
+  %x = load double , double *%a2
   %y = insertelement <2 x double> undef, double %x, i32 0
   %res = call < 2 x double > @llvm.x86.fma.vfmadd.sd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %y)
   ret < 2 x double > %res
 }
 define < 2 x double > @test_x86_fma_vfmadd_sd_load2(< 2 x double > %a0, double* %a1, < 2 x double > %a2) {
   ; CHECK: vfmaddsd %{{.*}}, (%{{.*}})
-  %x = load double *%a1
+  %x = load double , double *%a1
   %y = insertelement <2 x double> undef, double %x, i32 0
   %res = call < 2 x double > @llvm.x86.fma.vfmadd.sd(< 2 x double > %a0, < 2 x double > %y, < 2 x double > %a2)
   ret < 2 x double > %res
@@ -36,13 +36,13 @@ define < 2 x double > @test_x86_fma_vfmadd_sd_load2(< 2 x double > %a0, double*
 declare < 2 x double > @llvm.x86.fma.vfmadd.sd(< 2 x double >, < 2 x double >, < 2 x double >) nounwind readnone
 define < 4 x float > @test_x86_fma_vfmadd_ps_load(< 4 x float > %a0, < 4 x float > %a1, < 4 x float >* %a2) {
   ; CHECK: vfmaddps (%{{.*}})
-  %x = load <4 x float>* %a2
+  %x = load <4 x float>, <4 x float>* %a2
   %res = call < 4 x float > @llvm.x86.fma.vfmadd.ps(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %x)
   ret < 4 x float > %res
 }
 define < 4 x float > @test_x86_fma_vfmadd_ps_load2(< 4 x float > %a0, < 4 x float >* %a1, < 4 x float > %a2) {
   ; CHECK: vfmaddps %{{.*}}, (%{{.*}})
-  %x = load <4 x float>* %a1
+  %x = load <4 x float>, <4 x float>* %a1
   %res = call < 4 x float > @llvm.x86.fma.vfmadd.ps(< 4 x float > %a0, < 4 x float > %x, < 4 x float > %a2)
   ret < 4 x float > %res
 }
@@ -52,21 +52,21 @@ declare < 4 x float > @llvm.x86.fma.vfmadd.ps(< 4 x float >, < 4 x float >, < 4
 define < 4 x float > @test_x86_fma_vfmadd_ps_load3(< 4 x float >* %a0, < 4 x float >* %a1, < 4 x float > %a2) {
   ; CHECK: vmovaps
   ; CHECK: vfmaddps %{{.*}}, (%{{.*}})
-  %x = load <4 x float>* %a0
-  %y = load <4 x float>* %a1
+  %x = load <4 x float>, <4 x float>* %a0
+  %y = load <4 x float>, <4 x float>* %a1
   %res = call < 4 x float > @llvm.x86.fma.vfmadd.ps(< 4 x float > %x, < 4 x float > %y, < 4 x float > %a2)
   ret < 4 x float > %res
 }
 
 define < 2 x double > @test_x86_fma_vfmadd_pd_load(< 2 x double > %a0, < 2 x double > %a1, < 2 x double >* %a2) {
   ; CHECK: vfmaddpd (%{{.*}})
-  %x = load <2 x double>* %a2
+  %x = load <2 x double>, <2 x double>* %a2
   %res = call < 2 x double > @llvm.x86.fma.vfmadd.pd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %x)
   ret < 2 x double > %res
 }
 define < 2 x double > @test_x86_fma_vfmadd_pd_load2(< 2 x double > %a0, < 2 x double >* %a1, < 2 x double > %a2) {
   ; CHECK: vfmaddpd %{{.*}}, (%{{.*}})
-  %x = load <2 x double>* %a1
+  %x = load <2 x double>, <2 x double>* %a1
   %res = call < 2 x double > @llvm.x86.fma.vfmadd.pd(< 2 x double > %a0, < 2 x double > %x, < 2 x double > %a2)
   ret < 2 x double > %res
 }
@@ -76,8 +76,8 @@ declare < 2 x double > @llvm.x86.fma.vfmadd.pd(< 2 x double >, < 2 x double >, <
 define < 2 x double > @test_x86_fma_vfmadd_pd_load3(< 2 x double >* %a0, < 2 x double >* %a1, < 2 x double > %a2) {
   ; CHECK: vmovapd
   ; CHECK: vfmaddpd %{{.*}}, (%{{.*}})
-  %x = load <2 x double>* %a0
-  %y = load <2 x double>* %a1
+  %x = load <2 x double>, <2 x double>* %a0
+  %y = load <2 x double>, <2 x double>* %a1
   %res = call < 2 x double > @llvm.x86.fma.vfmadd.pd(< 2 x double > %x, < 2 x double > %y, < 2 x double > %a2)
   ret < 2 x double > %res
 }
diff --git a/test/CodeGen/X86/fma_patterns.ll b/test/CodeGen/X86/fma_patterns.ll
index 9b52db9f14e9..a27b760face7 100644
--- a/test/CodeGen/X86/fma_patterns.ll
+++ b/test/CodeGen/X86/fma_patterns.ll
@@ -190,7 +190,7 @@ define float @test_x86_fnmsub_ss(float %a0, float %a1, float %a2) {
 ; CHECK_FMA4: vfmaddps     %xmm1, (%rdi), %xmm0, %xmm0
 ; CHECK_FMA4: ret
 define <4 x float> @test_x86_fmadd_ps_load(<4 x float>* %a0, <4 x float> %a1, <4 x float> %a2) {
-  %x = load <4 x float>* %a0
+  %x = load <4 x float>, <4 x float>* %a0
   %y = fmul <4 x float> %x, %a1
   %res = fadd <4 x float> %y, %a2
   ret <4 x float> %res
@@ -204,7 +204,7 @@ define <4 x float> @test_x86_fmadd_ps_load(<4 x float>* %a0, <4 x float> %a1, <4
 ; CHECK_FMA4: vfmsubps     %xmm1, (%rdi), %xmm0, %xmm0
 ; CHECK_FMA4: ret
 define <4 x float> @test_x86_fmsub_ps_load(<4 x float>* %a0, <4 x float> %a1, <4 x float> %a2) {
-  %x = load <4 x float>* %a0
+  %x = load <4 x float>, <4 x float>* %a0
   %y = fmul <4 x float> %x, %a1
   %res = fsub <4 x float> %y, %a2
   ret <4 x float> %res
diff --git a/test/CodeGen/X86/fmul-combines.ll b/test/CodeGen/X86/fmul-combines.ll
index 703651153c11..7d75611e1330 100644
--- a/test/CodeGen/X86/fmul-combines.ll
+++ b/test/CodeGen/X86/fmul-combines.ll
@@ -103,6 +103,40 @@ define <4 x float> @fmul_v4f32_two_consts_no_splat_multiple_use(<4 x float> %x)
   ret <4 x float> %a
 }
 
+; PR22698 - http://llvm.org/bugs/show_bug.cgi?id=22698
+; Make sure that we don't infinite loop swapping constants back and forth.
+
+define <4 x float> @PR22698_splats(<4 x float> %a) #0 {
+  %mul1 = fmul fast <4 x float> <float 2.0, float 2.0, float 2.0, float 2.0>, <float 3.0, float 3.0, float 3.0, float 3.0>
+  %mul2 = fmul fast <4 x float> <float 4.0, float 4.0, float 4.0, float 4.0>, %mul1
+  %mul3 = fmul fast <4 x float> %a, %mul2
+  ret <4 x float> %mul3
+
+; CHECK: float 2.400000e+01
+; CHECK: float 2.400000e+01
+; CHECK: float 2.400000e+01
+; CHECK: float 2.400000e+01
+; CHECK-LABEL: PR22698_splats:
+; CHECK: mulps
+; CHECK: ret
+}
+
+; Same as above, but verify that non-splat vectors are handled correctly too.
+define <4 x float> @PR22698_no_splats(<4 x float> %a) #0 {
+  %mul1 = fmul fast <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, <float 5.0, float 6.0, float 7.0, float 8.0>
+  %mul2 = fmul fast <4 x float> <float 9.0, float 10.0, float 11.0, float 12.0>, %mul1
+  %mul3 = fmul fast <4 x float> %a, %mul2
+  ret <4 x float> %mul3
+
+; CHECK: float 4.500000e+01
+; CHECK: float 1.200000e+02
+; CHECK: float 2.310000e+02
+; CHECK: float 3.840000e+02
+; CHECK-LABEL: PR22698_no_splats:
+; CHECK: mulps
+; CHECK: ret
+}
+
 ; CHECK-LABEL: fmul_c2_c4_f32:
 ; CHECK-NOT: addss
 ; CHECK: mulss
diff --git a/test/CodeGen/X86/fmul-zero.ll b/test/CodeGen/X86/fmul-zero.ll
index 03bad6594128..bc139f88534f 100644
--- a/test/CodeGen/X86/fmul-zero.ll
+++ b/test/CodeGen/X86/fmul-zero.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=x86-64 | grep mulps
 
 define void @test14(<4 x float>*) nounwind {
-        load <4 x float>* %0, align 1
+        load <4 x float>, <4 x float>* %0, align 1
         fmul <4 x float> %2, zeroinitializer
         store <4 x float> %3, <4 x float>* %0, align 1
         ret void
diff --git a/test/CodeGen/X86/fnabs.ll b/test/CodeGen/X86/fnabs.ll
index 19718d3ff926..a3ddfb970dc4 100644
--- a/test/CodeGen/X86/fnabs.ll
+++ b/test/CodeGen/X86/fnabs.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx| FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx| FileCheck %s
 
 ; Verify that we generate a single OR instruction for a scalar, vec128, and vec256
 ; FNABS(x) operation -> FNEG (FABS(x)).
diff --git a/test/CodeGen/X86/fold-add.ll b/test/CodeGen/X86/fold-add.ll
index 0b27387b73bf..7d2740074082 100644
--- a/test/CodeGen/X86/fold-add.ll
+++ b/test/CodeGen/X86/fold-add.ll
@@ -13,12 +13,12 @@ define fastcc i32 @longest_match(i32 %cur_match) nounwind {
 ; CHECK: ret
 
 entry:
-	%0 = load i32* @prev_length, align 4		; <i32> [#uses=3]
+	%0 = load i32, i32* @prev_length, align 4		; <i32> [#uses=3]
 	%1 = zext i32 %cur_match to i64		; <i64> [#uses=1]
 	%2 = sext i32 %0 to i64		; <i64> [#uses=1]
 	%.sum3 = add i64 %1, %2		; <i64> [#uses=1]
-	%3 = getelementptr [65536 x i8]* @window, i64 0, i64 %.sum3		; <i8*> [#uses=1]
-	%4 = load i8* %3, align 1		; <i8> [#uses=1]
+	%3 = getelementptr [65536 x i8], [65536 x i8]* @window, i64 0, i64 %.sum3		; <i8*> [#uses=1]
+	%4 = load i8, i8* %3, align 1		; <i8> [#uses=1]
 	%5 = icmp eq i8 %4, 0		; <i1> [#uses=1]
 	br i1 %5, label %bb5, label %bb23
 
diff --git a/test/CodeGen/X86/fold-and-shift.ll b/test/CodeGen/X86/fold-and-shift.ll
index a5eb8b5de3a4..00173efff69b 100644
--- a/test/CodeGen/X86/fold-and-shift.ll
+++ b/test/CodeGen/X86/fold-and-shift.ll
@@ -10,9 +10,9 @@ define i32 @t1(i8* %X, i32 %i) {
 entry:
   %tmp2 = shl i32 %i, 2
   %tmp4 = and i32 %tmp2, 1020
-  %tmp7 = getelementptr i8* %X, i32 %tmp4
+  %tmp7 = getelementptr i8, i8* %X, i32 %tmp4
   %tmp78 = bitcast i8* %tmp7 to i32*
-  %tmp9 = load i32* %tmp78
+  %tmp9 = load i32, i32* %tmp78
   ret i32 %tmp9
 }
 
@@ -26,9 +26,9 @@ define i32 @t2(i16* %X, i32 %i) {
 entry:
   %tmp2 = shl i32 %i, 1
   %tmp4 = and i32 %tmp2, 131070
-  %tmp7 = getelementptr i16* %X, i32 %tmp4
+  %tmp7 = getelementptr i16, i16* %X, i32 %tmp4
   %tmp78 = bitcast i16* %tmp7 to i32*
-  %tmp9 = load i32* %tmp78
+  %tmp9 = load i32, i32* %tmp78
   ret i32 %tmp9
 }
 
@@ -46,11 +46,11 @@ define i32 @t3(i16* %i.ptr, i32* %arr) {
 ; CHECK: ret
 
 entry:
-  %i = load i16* %i.ptr
+  %i = load i16, i16* %i.ptr
   %i.zext = zext i16 %i to i32
   %index = lshr i32 %i.zext, 11
-  %val.ptr = getelementptr inbounds i32* %arr, i32 %index
-  %val = load i32* %val.ptr
+  %val.ptr = getelementptr inbounds i32, i32* %arr, i32 %index
+  %val = load i32, i32* %val.ptr
   %sum = add i32 %val, %i.zext
   ret i32 %sum
 }
@@ -65,12 +65,12 @@ define i32 @t4(i16* %i.ptr, i32* %arr) {
 ; CHECK: ret
 
 entry:
-  %i = load i16* %i.ptr
+  %i = load i16, i16* %i.ptr
   %i.zext = zext i16 %i to i32
   %index = lshr i32 %i.zext, 11
   %index.zext = zext i32 %index to i64
-  %val.ptr = getelementptr inbounds i32* %arr, i64 %index.zext
-  %val = load i32* %val.ptr
+  %val.ptr = getelementptr inbounds i32, i32* %arr, i64 %index.zext
+  %val = load i32, i32* %val.ptr
   %sum.1 = add i32 %val, %i.zext
   %sum.2 = add i32 %sum.1, %index
   ret i32 %sum.2
diff --git a/test/CodeGen/X86/fold-call-2.ll b/test/CodeGen/X86/fold-call-2.ll
index 7a2b03833ae9..b5e2606410f0 100644
--- a/test/CodeGen/X86/fold-call-2.ll
+++ b/test/CodeGen/X86/fold-call-2.ll
@@ -4,7 +4,7 @@
 
 define i32 @main() nounwind {
 entry:
-	load void ()** @f, align 8		; <void ()*>:0 [#uses=1]
+	load void ()*, void ()** @f, align 8		; <void ()*>:0 [#uses=1]
 	tail call void %0( ) nounwind
 	ret i32 0
 }
diff --git a/test/CodeGen/X86/fold-call-3.ll b/test/CodeGen/X86/fold-call-3.ll
index 337a7edb1736..e7e81b9422a1 100644
--- a/test/CodeGen/X86/fold-call-3.ll
+++ b/test/CodeGen/X86/fold-call-3.ll
@@ -10,33 +10,33 @@
 define void @_Z25RawPointerPerformanceTestPvRN5clang6ActionE(i8* %Val, %"struct.clang::Action"* %Actions) nounwind {
 entry:
 	%0 = alloca %"struct.clang::ActionBase::ActionResult<0u>", align 8		; <%"struct.clang::ActionBase::ActionResult<0u>"*> [#uses=3]
-	%1 = load i32* @NumTrials, align 4		; <i32> [#uses=1]
+	%1 = load i32, i32* @NumTrials, align 4		; <i32> [#uses=1]
 	%2 = icmp eq i32 %1, 0		; <i1> [#uses=1]
 	br i1 %2, label %return, label %bb.nph
 
 bb.nph:		; preds = %entry
-	%3 = getelementptr %"struct.clang::Action"* %Actions, i64 0, i32 0, i32 0		; <i32 (...)***> [#uses=1]
+	%3 = getelementptr %"struct.clang::Action", %"struct.clang::Action"* %Actions, i64 0, i32 0, i32 0		; <i32 (...)***> [#uses=1]
 	%mrv_gep = bitcast %"struct.clang::ActionBase::ActionResult<0u>"* %0 to i64*		; <i64*> [#uses=1]
-	%mrv_gep1 = getelementptr %"struct.clang::ActionBase::ActionResult<0u>"* %0, i64 0, i32 1		; <i8*> [#uses=1]
+	%mrv_gep1 = getelementptr %"struct.clang::ActionBase::ActionResult<0u>", %"struct.clang::ActionBase::ActionResult<0u>"* %0, i64 0, i32 1		; <i8*> [#uses=1]
 	%4 = bitcast i8* %mrv_gep1 to i64*		; <i64*> [#uses=1]
-	%5 = getelementptr %"struct.clang::ActionBase::ActionResult<0u>"* %0, i64 0, i32 0		; <i8**> [#uses=1]
+	%5 = getelementptr %"struct.clang::ActionBase::ActionResult<0u>", %"struct.clang::ActionBase::ActionResult<0u>"* %0, i64 0, i32 0		; <i8**> [#uses=1]
 	br label %bb
 
 bb:		; preds = %bb, %bb.nph
 	%Trial.01 = phi i32 [ 0, %bb.nph ], [ %12, %bb ]		; <i32> [#uses=1]
 	%Val_addr.02 = phi i8* [ %Val, %bb.nph ], [ %11, %bb ]		; <i8*> [#uses=1]
-	%6 = load i32 (...)*** %3, align 8		; <i32 (...)**> [#uses=1]
-	%7 = getelementptr i32 (...)** %6, i64 70		; <i32 (...)**> [#uses=1]
-	%8 = load i32 (...)** %7, align 8		; <i32 (...)*> [#uses=1]
+	%6 = load i32 (...)**, i32 (...)*** %3, align 8		; <i32 (...)**> [#uses=1]
+	%7 = getelementptr i32 (...)*, i32 (...)** %6, i64 70		; <i32 (...)**> [#uses=1]
+	%8 = load i32 (...)*, i32 (...)** %7, align 8		; <i32 (...)*> [#uses=1]
 	%9 = bitcast i32 (...)* %8 to { i64, i64 } (%"struct.clang::Action"*, i8*)*		; <{ i64, i64 } (%"struct.clang::Action"*, i8*)*> [#uses=1]
 	%10 = call { i64, i64 } %9(%"struct.clang::Action"* %Actions, i8* %Val_addr.02) nounwind		; <{ i64, i64 }> [#uses=2]
 	%mrv_gr = extractvalue { i64, i64 } %10, 0		; <i64> [#uses=1]
 	store i64 %mrv_gr, i64* %mrv_gep
 	%mrv_gr2 = extractvalue { i64, i64 } %10, 1		; <i64> [#uses=1]
 	store i64 %mrv_gr2, i64* %4
-	%11 = load i8** %5, align 8		; <i8*> [#uses=1]
+	%11 = load i8*, i8** %5, align 8		; <i8*> [#uses=1]
 	%12 = add i32 %Trial.01, 1		; <i32> [#uses=2]
-	%13 = load i32* @NumTrials, align 4		; <i32> [#uses=1]
+	%13 = load i32, i32* @NumTrials, align 4		; <i32> [#uses=1]
 	%14 = icmp ult i32 %12, %13		; <i1> [#uses=1]
 	br i1 %14, label %bb, label %return
 
diff --git a/test/CodeGen/X86/fold-call-oper.ll b/test/CodeGen/X86/fold-call-oper.ll
index 94e2a6f70506..1e3e58ddc6cd 100644
--- a/test/CodeGen/X86/fold-call-oper.ll
+++ b/test/CodeGen/X86/fold-call-oper.ll
@@ -14,7 +14,7 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 ; CHECK: callq *{{.*}}(%rbp)
 define void @foldCallOper(i32 (i32*, i32, i32**)* nocapture %p1) #0 {
 entry:
-  %0 = load i32*** @a, align 8
+  %0 = load i32**, i32*** @a, align 8
   br label %for.body.i
 
 for.body.i:                                       ; preds = %for.body.i, %entry
@@ -33,14 +33,14 @@ for.body3.i:                                      ; preds = %for.inc8.i, %for.bo
   br i1 %tobool.i, label %for.inc8.i, label %if.then.i
 
 if.then.i:                                        ; preds = %for.body3.i
-  %2 = load i32* %1, align 4
+  %2 = load i32, i32* %1, align 4
   store i32 %2, i32* @b, align 4
   br label %for.inc8.i
 
 for.inc8.i:                                       ; preds = %if.then.i, %for.body3.i
   %lftr.wideiv.i = trunc i64 %indvars.iv.i to i32
-  %arrayidx4.phi.trans.insert.i = getelementptr inbounds [0 x i32*]* undef, i64 0, i64 %indvars.iv.i
-  %.pre.i = load i32** %arrayidx4.phi.trans.insert.i, align 8
+  %arrayidx4.phi.trans.insert.i = getelementptr inbounds [0 x i32*], [0 x i32*]* undef, i64 0, i64 %indvars.iv.i
+  %.pre.i = load i32*, i32** %arrayidx4.phi.trans.insert.i, align 8
   %phitmp.i = add i64 %indvars.iv.i, 1
   br label %for.body3.i
 }
diff --git a/test/CodeGen/X86/fold-call.ll b/test/CodeGen/X86/fold-call.ll
index 35327faa6486..00839943f678 100644
--- a/test/CodeGen/X86/fold-call.ll
+++ b/test/CodeGen/X86/fold-call.ll
@@ -19,8 +19,8 @@ define void @test1(i32 %i0, i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, void()*
 %struct.X = type { void ()* }
 define void @test2(%struct.X* nocapture %x) {
 entry:
-  %f = getelementptr inbounds %struct.X* %x, i64 0, i32 0
-  %0 = load void ()** %f
+  %f = getelementptr inbounds %struct.X, %struct.X* %x, i64 0, i32 0
+  %0 = load void ()*, void ()** %f
   store void ()* null, void ()** %f
   tail call void %0()
   ret void
diff --git a/test/CodeGen/X86/fold-load-unops.ll b/test/CodeGen/X86/fold-load-unops.ll
new file mode 100644
index 000000000000..fcde0218158a
--- /dev/null
+++ b/test/CodeGen/X86/fold-load-unops.ll
@@ -0,0 +1,79 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX
+
+; Verify that we're folding the load into the math instruction.
+
+define float @rcpss(float* %a) {
+; SSE-LABEL: rcpss:
+; SSE:       # BB#0:
+; SSE-NEXT:    rcpss (%rdi), %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: rcpss:
+; AVX:       # BB#0:
+; AVX-NEXT:    vrcpss (%rdi), %xmm0, %xmm0
+; AVX-NEXT:    retq
+    %ld = load float, float* %a
+    %ins = insertelement <4 x float> undef, float %ld, i32 0
+    %res = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %ins)
+    %ext = extractelement <4 x float> %res, i32 0
+    ret float %ext
+}
+
+define float @rsqrtss(float* %a) {
+; SSE-LABEL: rsqrtss:
+; SSE:       # BB#0:
+; SSE-NEXT:    rsqrtss (%rdi), %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: rsqrtss:
+; AVX:       # BB#0:
+; AVX-NEXT:    vrsqrtss (%rdi), %xmm0, %xmm0
+; AVX-NEXT:    retq
+    %ld = load float, float* %a
+    %ins = insertelement <4 x float> undef, float %ld, i32 0
+    %res = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %ins)
+    %ext = extractelement <4 x float> %res, i32 0
+    ret float %ext
+}
+
+define float @sqrtss(float* %a) {
+; SSE-LABEL: sqrtss:
+; SSE:       # BB#0:
+; SSE-NEXT:    sqrtss (%rdi), %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: sqrtss:
+; AVX:       # BB#0:
+; AVX-NEXT:    vsqrtss (%rdi), %xmm0, %xmm0
+; AVX-NEXT:    retq
+    %ld = load float, float* %a
+    %ins = insertelement <4 x float> undef, float %ld, i32 0
+    %res = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %ins)
+    %ext = extractelement <4 x float> %res, i32 0
+    ret float %ext
+}
+
+define double @sqrtsd(double* %a) {
+; SSE-LABEL: sqrtsd:
+; SSE:       # BB#0:
+; SSE-NEXT:    sqrtsd (%rdi), %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: sqrtsd:
+; AVX:       # BB#0:
+; AVX-NEXT:    vsqrtsd (%rdi), %xmm0, %xmm0
+; AVX-NEXT:    retq
+    %ld = load double, double* %a
+    %ins = insertelement <2 x double> undef, double %ld, i32 0
+    %res = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %ins)
+    %ext = extractelement <2 x double> %res, i32 0
+    ret double %ext
+}
+
+
+declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
+declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
+declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
+declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
+
diff --git a/test/CodeGen/X86/fold-load-vec.ll b/test/CodeGen/X86/fold-load-vec.ll
index 96c5be4f752f..657b7bdd24ff 100644
--- a/test/CodeGen/X86/fold-load-vec.ll
+++ b/test/CodeGen/X86/fold-load-vec.ll
@@ -14,24 +14,24 @@ entry:
   store <4 x float>* %source, <4 x float>** %source.addr, align 8
   store <2 x float>* %dest, <2 x float>** %dest.addr, align 8
   store <2 x float> zeroinitializer, <2 x float>* %tmp, align 8
-  %0 = load <4 x float>** %source.addr, align 8
-  %arrayidx = getelementptr inbounds <4 x float>* %0, i64 0
-  %1 = load <4 x float>* %arrayidx, align 16
+  %0 = load <4 x float>*, <4 x float>** %source.addr, align 8
+  %arrayidx = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0
+  %1 = load <4 x float>, <4 x float>* %arrayidx, align 16
   %2 = extractelement <4 x float> %1, i32 0
-  %3 = load <2 x float>* %tmp, align 8
+  %3 = load <2 x float>, <2 x float>* %tmp, align 8
   %4 = insertelement <2 x float> %3, float %2, i32 1
   store <2 x float> %4, <2 x float>* %tmp, align 8
-  %5 = load <2 x float>* %tmp, align 8
-  %6 = load <2 x float>** %dest.addr, align 8
-  %arrayidx1 = getelementptr inbounds <2 x float>* %6, i64 0
+  %5 = load <2 x float>, <2 x float>* %tmp, align 8
+  %6 = load <2 x float>*, <2 x float>** %dest.addr, align 8
+  %arrayidx1 = getelementptr inbounds <2 x float>, <2 x float>* %6, i64 0
   store <2 x float> %5, <2 x float>* %arrayidx1, align 8
-  %7 = load <2 x float>** %dest.addr, align 8
-  %arrayidx2 = getelementptr inbounds <2 x float>* %7, i64 0
-  %8 = load <2 x float>* %arrayidx2, align 8
+  %7 = load <2 x float>*, <2 x float>** %dest.addr, align 8
+  %arrayidx2 = getelementptr inbounds <2 x float>, <2 x float>* %7, i64 0
+  %8 = load <2 x float>, <2 x float>* %arrayidx2, align 8
   %vecext = extractelement <2 x float> %8, i32 0
-  %9 = load <2 x float>** %dest.addr, align 8
-  %arrayidx3 = getelementptr inbounds <2 x float>* %9, i64 0
-  %10 = load <2 x float>* %arrayidx3, align 8
+  %9 = load <2 x float>*, <2 x float>** %dest.addr, align 8
+  %arrayidx3 = getelementptr inbounds <2 x float>, <2 x float>* %9, i64 0
+  %10 = load <2 x float>, <2 x float>* %arrayidx3, align 8
   %vecext4 = extractelement <2 x float> %10, i32 1
   call void @ext(float %vecext, float %vecext4)
   ret void
diff --git a/test/CodeGen/X86/fold-load.ll b/test/CodeGen/X86/fold-load.ll
index dde0a2d1c5d3..8cdc58bb75e0 100644
--- a/test/CodeGen/X86/fold-load.ll
+++ b/test/CodeGen/X86/fold-load.ll
@@ -10,7 +10,7 @@ entry:
 
 cond_true:		; preds = %entry
 	%new_size.0.i = select i1 false, i32 0, i32 0		; <i32> [#uses=1]
-	%tmp.i = load i32* bitcast (i8* getelementptr (%struct.obstack* @stmt_obstack, i32 0, i32 10) to i32*)		; <i32> [#uses=1]
+	%tmp.i = load i32, i32* bitcast (i8* getelementptr (%struct.obstack, %struct.obstack* @stmt_obstack, i32 0, i32 10) to i32*)		; <i32> [#uses=1]
 	%tmp.i.upgrd.1 = trunc i32 %tmp.i to i8		; <i8> [#uses=1]
 	%tmp21.i = and i8 %tmp.i.upgrd.1, 1		; <i8> [#uses=1]
 	%tmp22.i = icmp eq i8 %tmp21.i, 0		; <i1> [#uses=1]
@@ -30,7 +30,7 @@ cond_next:		; preds = %entry
 
 
 define i32 @test2(i16* %P, i16* %Q) nounwind {
-  %A = load i16* %P, align 4                      ; <i16> [#uses=11]
+  %A = load i16, i16* %P, align 4                      ; <i16> [#uses=11]
   %C = zext i16 %A to i32                         ; <i32> [#uses=1]
   %D = and i32 %C, 255                            ; <i32> [#uses=1]
   br label %L
@@ -54,8 +54,8 @@ define i1 @test3(i32* %P, i32* %Q) nounwind {
 ; CHECK: xorl (%e
 ; CHECK: j
 entry:
-  %0 = load i32* %P, align 4
-  %1 = load i32* %Q, align 4
+  %0 = load i32, i32* %P, align 4
+  %1 = load i32, i32* %Q, align 4
   %2 = xor i32 %0, %1
   %3 = and i32 %2, 89947
   %4 = icmp eq i32 %3, 0
diff --git a/test/CodeGen/X86/fold-mul-lohi.ll b/test/CodeGen/X86/fold-mul-lohi.ll
index 5614c808d0e6..8d4c5ef9eb22 100644
--- a/test/CodeGen/X86/fold-mul-lohi.ll
+++ b/test/CodeGen/X86/fold-mul-lohi.ll
@@ -13,13 +13,13 @@ entry:
 
 bb:
 	%i.019.0 = phi i32 [ %indvar.next, %bb ], [ 0, %entry ]
-	%tmp2 = getelementptr [1000 x i8]* @B, i32 0, i32 %i.019.0
-	%tmp3 = load i8* %tmp2, align 4
+	%tmp2 = getelementptr [1000 x i8], [1000 x i8]* @B, i32 0, i32 %i.019.0
+	%tmp3 = load i8, i8* %tmp2, align 4
 	%tmp4 = mul i8 %tmp3, 2
-	%tmp5 = getelementptr [1000 x i8]* @A, i32 0, i32 %i.019.0
+	%tmp5 = getelementptr [1000 x i8], [1000 x i8]* @A, i32 0, i32 %i.019.0
 	store i8 %tmp4, i8* %tmp5, align 4
 	%tmp8 = mul i32 %i.019.0, 9
-	%tmp10 = getelementptr [1000 x i8]* @P, i32 0, i32 %tmp8
+	%tmp10 = getelementptr [1000 x i8], [1000 x i8]* @P, i32 0, i32 %tmp8
 	store i8 17, i8* %tmp10, align 4
 	%indvar.next = add i32 %i.019.0, 1
 	%exitcond = icmp eq i32 %indvar.next, %m
diff --git a/test/CodeGen/X86/fold-pcmpeqd-2.ll b/test/CodeGen/X86/fold-pcmpeqd-2.ll
index 60a6844b39b2..d95c6323de4e 100644
--- a/test/CodeGen/X86/fold-pcmpeqd-2.ll
+++ b/test/CodeGen/X86/fold-pcmpeqd-2.ll
@@ -20,7 +20,7 @@
 
 define void @program_1(%struct._image2d_t* %dest, %struct._image2d_t* %t0, <4 x float> %p0, <4 x float> %p1, <4 x float> %p4, <4 x float> %p5, <4 x float> %p6) nounwind {
 entry:
-	%tmp3.i = load i32* null		; <i32> [#uses=1]
+	%tmp3.i = load i32, i32* null		; <i32> [#uses=1]
 	%cmp = icmp slt i32 0, %tmp3.i		; <i1> [#uses=1]
 	br i1 %cmp, label %forcond, label %ifthen
 
@@ -28,7 +28,7 @@ ifthen:		; preds = %entry
 	ret void
 
 forcond:		; preds = %entry
-	%tmp3.i536 = load i32* null		; <i32> [#uses=1]
+	%tmp3.i536 = load i32, i32* null		; <i32> [#uses=1]
 	%cmp12 = icmp slt i32 0, %tmp3.i536		; <i1> [#uses=1]
 	br i1 %cmp12, label %forbody, label %afterfor
 
diff --git a/test/CodeGen/X86/fold-sext-trunc.ll b/test/CodeGen/X86/fold-sext-trunc.ll
index b453310608ec..df06e70b0c24 100644
--- a/test/CodeGen/X86/fold-sext-trunc.ll
+++ b/test/CodeGen/X86/fold-sext-trunc.ll
@@ -9,8 +9,8 @@ declare void @func_28(i64, i64)
 
 define void @int322(i32 %foo) nounwind {
 entry:
-	%val = load i64* getelementptr (%0* bitcast (%struct.S1* @g_10 to %0*), i32 0, i32 0)		; <i64> [#uses=1]
-	%0 = load i32* getelementptr (%struct.S1* @g_10, i32 0, i32 1), align 4		; <i32> [#uses=1]
+	%val = load i64, i64* getelementptr (%0, %0* bitcast (%struct.S1* @g_10 to %0*), i32 0, i32 0)		; <i64> [#uses=1]
+	%0 = load i32, i32* getelementptr (%struct.S1, %struct.S1* @g_10, i32 0, i32 1), align 4		; <i32> [#uses=1]
 	%1 = sext i32 %0 to i64		; <i64> [#uses=1]
 	%tmp4.i = lshr i64 %val, 32		; <i64> [#uses=1]
 	%tmp5.i = trunc i64 %tmp4.i to i32		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/fold-tied-op.ll b/test/CodeGen/X86/fold-tied-op.ll
index 5bf5dbd1a9ce..62fed4219387 100644
--- a/test/CodeGen/X86/fold-tied-op.ll
+++ b/test/CodeGen/X86/fold-tied-op.ll
@@ -23,20 +23,20 @@ target triple = "i386--netbsd"
 ; Function Attrs: nounwind uwtable
 define i64 @fn1() #0 {
 entry:
-  %0 = load i32* @a, align 4, !tbaa !1
+  %0 = load i32, i32* @a, align 4, !tbaa !1
   %1 = inttoptr i32 %0 to %struct.XXH_state64_t*
-  %total_len = getelementptr inbounds %struct.XXH_state64_t* %1, i32 0, i32 0
-  %2 = load i32* %total_len, align 4, !tbaa !5
+  %total_len = getelementptr inbounds %struct.XXH_state64_t, %struct.XXH_state64_t* %1, i32 0, i32 0
+  %2 = load i32, i32* %total_len, align 4, !tbaa !5
   %tobool = icmp eq i32 %2, 0
   br i1 %tobool, label %if.else, label %if.then
 
 if.then:                                          ; preds = %entry
-  %v3 = getelementptr inbounds %struct.XXH_state64_t* %1, i32 0, i32 3
-  %3 = load i64* %v3, align 4, !tbaa !8
-  %v4 = getelementptr inbounds %struct.XXH_state64_t* %1, i32 0, i32 4
-  %4 = load i64* %v4, align 4, !tbaa !9
-  %v2 = getelementptr inbounds %struct.XXH_state64_t* %1, i32 0, i32 2
-  %5 = load i64* %v2, align 4, !tbaa !10
+  %v3 = getelementptr inbounds %struct.XXH_state64_t, %struct.XXH_state64_t* %1, i32 0, i32 3
+  %3 = load i64, i64* %v3, align 4, !tbaa !8
+  %v4 = getelementptr inbounds %struct.XXH_state64_t, %struct.XXH_state64_t* %1, i32 0, i32 4
+  %4 = load i64, i64* %v4, align 4, !tbaa !9
+  %v2 = getelementptr inbounds %struct.XXH_state64_t, %struct.XXH_state64_t* %1, i32 0, i32 2
+  %5 = load i64, i64* %v2, align 4, !tbaa !10
   %shl = shl i64 %5, 1
   %or = or i64 %shl, %5
   %shl2 = shl i64 %3, 2
@@ -54,7 +54,7 @@ if.then:                                          ; preds = %entry
   br label %if.end
 
 if.else:                                          ; preds = %entry
-  %6 = load i64* @b, align 8, !tbaa !11
+  %6 = load i64, i64* @b, align 8, !tbaa !11
   %xor10 = xor i64 %6, -4417276706812531889
   %mul11 = mul nsw i64 %xor10, 400714785074694791
   br label %if.end
diff --git a/test/CodeGen/X86/fold-vector-bv-crash.ll b/test/CodeGen/X86/fold-vector-bv-crash.ll
new file mode 100644
index 000000000000..8c72afb7e970
--- /dev/null
+++ b/test/CodeGen/X86/fold-vector-bv-crash.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx
+
+;
+; llvm-stress generated crash case due to build_vector implicit
+; truncation bug from constant folding after legalization.
+;
+
+@G = external global i32
+
+define void @bv_crash_test() {
+  %I = insertelement <4 x i64> zeroinitializer, i64 15910, i32 0
+  %Tr = trunc <4 x i64> %I to <4 x i8>
+  %Bc = bitcast <4 x i8> %Tr to i32
+  store volatile i32 %Bc, i32* @G
+  ret void
+}
diff --git a/test/CodeGen/X86/fold-vector-shuffle-crash.ll b/test/CodeGen/X86/fold-vector-shuffle-crash.ll
new file mode 100644
index 000000000000..df9c6924b272
--- /dev/null
+++ b/test/CodeGen/X86/fold-vector-shuffle-crash.ll
@@ -0,0 +1,386 @@
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=corei7
+
+define void @autogen_SD13708(i32) {
+BB:
+ %Shuff7 = shufflevector <8 x i32> zeroinitializer, <8 x i32> zeroinitializer, <8 x i32> <i32 8, i32 10, i32 12, i32 14, i32 undef, i32 2, i32 4, i32 undef>
+ br label %CF
+
+CF:
+ %Tr = trunc <8 x i64> zeroinitializer to <8 x i32>
+ %Shuff20 = shufflevector <8 x i32> %Shuff7, <8 x i32> %Tr, <8 x i32> <i32 13, i32 15, i32 1, i32 3, i32 5, i32 7, i32 undef, i32 11>
+ br i1 undef, label %CF, label %CF247
+
+CF247:
+ %I171 = insertelement <8 x i32> %Shuff20, i32 %0, i32 0
+ br i1 undef, label %CF, label %CF247
+}
+
+define void @autogen_SD13800(i8*, i32*, i64*, i32, i64, i8) {
+BB:
+  %A4 = alloca <8 x i1>
+  %A3 = alloca i32
+  %A2 = alloca <2 x float>
+  %A1 = alloca <2 x double>
+  %A = alloca <8 x float>
+  %L = load <8 x i1>, <8 x i1>* %A4
+  store i8 %5, i8* %0
+  %E = extractelement <2 x i64> zeroinitializer, i32 0
+  %Shuff = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 7, i32 undef, i32 undef, i32 5>
+  %I = insertelement <8 x i64> zeroinitializer, i64 419346, i32 1
+  %B = shl i64 426618, 419346
+  %Tr = trunc <8 x i64> %I to <8 x i16>
+  %Sl = select i1 false, <4 x i64> zeroinitializer, <4 x i64> zeroinitializer
+  %Cmp = icmp eq <16 x i64> zeroinitializer, zeroinitializer
+  %L5 = load i8, i8* %0
+  store i8 17, i8* %0
+  %E6 = extractelement <4 x i64> zeroinitializer, i32 1
+  %Shuff7 = shufflevector <2 x i64> zeroinitializer, <2 x i64> <i64 -1, i64 -1>, <2 x i32> <i32 0, i32 2>
+  %I8 = insertelement <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, i8 %L5, i32 2
+  %B9 = mul <8 x i16> %Tr, %Tr
+  %FC = fptosi float 0xBDF7B90B80000000 to i32
+  %Sl10 = select i1 false, float 0xBDF7B90B80000000, float 0xB875A90980000000
+  %Cmp11 = icmp slt <2 x i64> zeroinitializer, %Shuff7
+  %L12 = load <8 x float>, <8 x float>* %A
+  store <2 x double> <double 0xFFFFFFFFFFFFFFFF, double 0.000000e+00>, <2 x double>* %A1
+  %E13 = extractelement <4 x i64> zeroinitializer, i32 2
+  %Shuff14 = shufflevector <2 x i32> zeroinitializer, <2 x i32> zeroinitializer, <2 x i32> <i32 1, i32 3>
+  %I15 = insertelement <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, i8 %L5, i32 15
+  %B16 = add <2 x i64> zeroinitializer, <i64 -1, i64 -1>
+  %BC = bitcast i64 426618 to double
+  %Sl17 = select i1 false, <2 x i32> zeroinitializer, <2 x i32> zeroinitializer
+  %Cmp18 = icmp slt <8 x i1> %L, %L
+  %L19 = load i8, i8* %0
+  store i8 %L5, i8* %0
+  %E20 = extractelement <16 x i8> %I8, i32 1
+  %Shuff21 = shufflevector <8 x i64> zeroinitializer, <8 x i64> %I, <8 x i32> <i32 undef, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2>
+  %I22 = insertelement <8 x i16> %Tr, i16 18460, i32 6
+  %B23 = sub i64 419346, %4
+  %FC24 = fptosi double 0xE603EE221901D6A0 to i32
+  %Sl25 = select i1 false, i8 %L5, i8 %5
+  %Cmp26 = icmp ugt i64 %B, %B23
+  br label %CF253
+
+CF253:                                            ; preds = %CF253, %CF271, %CF260, %BB
+  %L27 = load i8, i8* %0
+  store i8 %L5, i8* %0
+  %E28 = extractelement <2 x i64> zeroinitializer, i32 0
+  %Shuff29 = shufflevector <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %I8, <16 x i32> <i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 undef, i32 31, i32 undef, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13>
+  %I30 = insertelement <8 x i1> %Cmp18, i1 false, i32 1
+  %B31 = fsub double 0xE603EE221901D6A0, %BC
+  %Tr32 = trunc <2 x i64> <i64 -1, i64 -1> to <2 x i32>
+  %Sl33 = select i1 false, double %BC, double %B31
+  %Cmp34 = icmp sgt <2 x i32> zeroinitializer, %Shuff14
+  %L35 = load i8, i8* %0
+  store i8 %L5, i8* %0
+  %E36 = extractelement <16 x i8> %Shuff29, i32 5
+  %Shuff37 = shufflevector <8 x i64> zeroinitializer, <8 x i64> %I, <8 x i32> <i32 8, i32 undef, i32 undef, i32 14, i32 0, i32 undef, i32 4, i32 6>
+  %I38 = insertelement <4 x i64> zeroinitializer, i64 %E28, i32 2
+  %FC39 = uitofp i8 %5 to double
+  %Sl40 = select i1 %Cmp26, i32 %3, i32 %FC
+  %Cmp41 = icmp sgt <2 x i64> zeroinitializer, <i64 -1, i64 -1>
+  %L42 = load i8, i8* %0
+  store i8 17, i8* %0
+  %E43 = extractelement <2 x i1> %Cmp41, i32 1
+  br i1 %E43, label %CF253, label %CF256
+
+CF256:                                            ; preds = %CF256, %CF253
+  %Shuff44 = shufflevector <8 x i64> zeroinitializer, <8 x i64> zeroinitializer, <8 x i32> <i32 14, i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 12>
+  %I45 = insertelement <8 x i32> zeroinitializer, i32 %FC, i32 0
+  %ZE = zext i8 %L19 to i32
+  %Sl46 = select i1 %E43, i8 %L35, i8 %L35
+  %Cmp47 = icmp ult i64 %E6, 426618
+  br i1 %Cmp47, label %CF256, label %CF271
+
+CF271:                                            ; preds = %CF256
+  %L48 = load i8, i8* %0
+  store i8 %L27, i8* %0
+  %E49 = extractelement <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, i32 2
+  %Shuff50 = shufflevector <8 x i64> zeroinitializer, <8 x i64> zeroinitializer, <8 x i32> <i32 undef, i32 7, i32 undef, i32 11, i32 13, i32 15, i32 1, i32 3>
+  %I51 = insertelement <8 x i64> zeroinitializer, i64 %4, i32 7
+  %B52 = xor <8 x i32> %I45, zeroinitializer
+  %BC53 = bitcast <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> to <4 x float>
+  %Sl54 = select i1 false, <2 x i64> <i64 -1, i64 -1>, <2 x i64> <i64 -1, i64 -1>
+  %Cmp55 = icmp sgt i16 0, 18460
+  br i1 %Cmp55, label %CF253, label %CF255
+
+CF255:                                            ; preds = %CF255, %CF266, %CF270, %CF271
+  %L56 = load i8, i8* %0
+  store i8 %L35, i8* %0
+  %E57 = extractelement <4 x i64> zeroinitializer, i32 3
+  %Shuff58 = shufflevector <8 x i64> zeroinitializer, <8 x i64> %Shuff37, <8 x i32> <i32 undef, i32 undef, i32 10, i32 12, i32 14, i32 0, i32 2, i32 4>
+  %I59 = insertelement <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, i32 %FC, i32 0
+  %B60 = lshr <4 x i64> %I38, zeroinitializer
+  %FC61 = sitofp <8 x i1> %L to <8 x float>
+  %Sl62 = select i1 false, i8 %L19, i8 17
+  %Cmp63 = icmp ult i64 %E6, %E57
+  br i1 %Cmp63, label %CF255, label %CF266
+
+CF266:                                            ; preds = %CF255
+  %L64 = load i64, i64* %2
+  store i8 17, i8* %0
+  %E65 = extractelement <8 x i64> %Shuff21, i32 6
+  %Shuff66 = shufflevector <2 x i1> %Cmp11, <2 x i1> %Cmp41, <2 x i32> <i32 1, i32 3>
+  %I67 = insertelement <8 x i1> %I30, i1 false, i32 7
+  %FC68 = uitofp i8 %Sl62 to float
+  %Sl69 = select i1 false, i8 %L42, i8 17
+  %Cmp70 = icmp eq <2 x i32> zeroinitializer, zeroinitializer
+  %L71 = load i8, i8* %0
+  store i8 %5, i8* %0
+  %E72 = extractelement <2 x i64> <i64 -1, i64 -1>, i32 1
+  %Shuff73 = shufflevector <8 x i64> zeroinitializer, <8 x i64> %Shuff44, <8 x i32> <i32 undef, i32 14, i32 0, i32 2, i32 4, i32 6, i32 undef, i32 10>
+  %I74 = insertelement <2 x i1> %Cmp70, i1 %Cmp55, i32 0
+  %B75 = add <16 x i8> %I15, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %FC76 = sitofp i8 33 to double
+  %Sl77 = select i1 %E43, double %BC, double %B31
+  %Cmp78 = icmp ult <8 x i64> %Shuff44, %I
+  %L79 = load i8, i8* %0
+  store i8 17, i8* %0
+  %E80 = extractelement <2 x i64> %Shuff7, i32 0
+  %Shuff81 = shufflevector <8 x i64> zeroinitializer, <8 x i64> %Shuff73, <8 x i32> <i32 undef, i32 5, i32 7, i32 9, i32 undef, i32 13, i32 15, i32 1>
+  %I82 = insertelement <8 x i64> %Shuff81, i64 %E57, i32 5
+  %FC83 = fptosi float %FC68 to i32
+  %Sl84 = select i1 %Cmp26, <2 x i64> <i64 -1, i64 -1>, <2 x i64> <i64 -1, i64 -1>
+  %Cmp85 = icmp ugt i64 %E6, %E57
+  br i1 %Cmp85, label %CF255, label %CF261
+
+CF261:                                            ; preds = %CF261, %CF266
+  %L86 = load i8, i8* %0
+  store i8 %L42, i8* %0
+  %E87 = extractelement <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, i32 7
+  %Shuff88 = shufflevector <16 x i8> %Shuff29, <16 x i8> %I15, <16 x i32> <i32 26, i32 28, i32 30, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24>
+  %I89 = insertelement <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, i8 %L35, i32 12
+  %B90 = shl i32 %3, %E49
+  %BC91 = bitcast <2 x i64> %Sl84 to <2 x double>
+  %Sl92 = select i1 false, i8 %L5, i8 %L19
+  %Cmp93 = icmp ugt i32 -1, %FC24
+  br i1 %Cmp93, label %CF261, label %CF268
+
+CF268:                                            ; preds = %CF268, %CF261
+  %L94 = load i8, i8* %0
+  store i8 %L5, i8* %0
+  %E95 = extractelement <8 x i64> %Shuff58, i32 0
+  %Shuff96 = shufflevector <8 x i64> %Shuff73, <8 x i64> %Shuff73, <8 x i32> <i32 3, i32 5, i32 undef, i32 9, i32 undef, i32 undef, i32 15, i32 1>
+  %I97 = insertelement <4 x i64> zeroinitializer, i64 %B23, i32 1
+  %B98 = or <8 x i64> %Shuff58, %Shuff50
+  %FC99 = sitofp <2 x i1> %Cmp34 to <2 x float>
+  %Sl100 = select i1 %Cmp85, i64 %4, i64 %E
+  %Cmp101 = icmp ne <2 x i64> %B16, zeroinitializer
+  %L102 = load i8, i8* %0
+  store i8 %L56, i8* %0
+  %E103 = extractelement <8 x i16> %I22, i32 6
+  %Shuff104 = shufflevector <2 x double> %BC91, <2 x double> %BC91, <2 x i32> <i32 1, i32 3>
+  %I105 = insertelement <8 x i64> %Shuff96, i64 198384, i32 7
+  %B106 = sdiv <8 x i32> %B52, %I45
+  %ZE107 = zext i16 0 to i32
+  %Sl108 = select i1 %E43, <16 x i8> %Shuff29, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %Cmp109 = icmp slt <16 x i64> zeroinitializer, zeroinitializer
+  %L110 = load <8 x float>, <8 x float>* %A
+  store i8 %L56, i8* %0
+  %E111 = extractelement <8 x i64> zeroinitializer, i32 3
+  %Shuff112 = shufflevector <2 x i1> %Shuff66, <2 x i1> %Cmp11, <2 x i32> <i32 2, i32 0>
+  %I113 = insertelement <2 x i64> %B16, i64 %E95, i32 0
+  %B114 = mul i8 %E20, %Sl25
+  %Tr115 = trunc <8 x i64> %I105 to <8 x i16>
+  %Sl116 = select i1 %Cmp26, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
+  %Cmp117 = icmp ult <8 x i16> %Tr, %Tr115
+  %L118 = load i8, i8* %0
+  store i8 %L19, i8* %0
+  %E119 = extractelement <4 x i32> %I59, i32 3
+  %Shuff120 = shufflevector <2 x i64> <i64 -1, i64 -1>, <2 x i64> %I113, <2 x i32> <i32 2, i32 0>
+  %I121 = insertelement <2 x i1> %Shuff66, i1 %Cmp26, i32 0
+  %B122 = fmul double 0.000000e+00, 0xE603EE221901D6A0
+  %FC123 = sitofp i64 %E6 to float
+  %Sl124 = select i1 false, <2 x i1> %Cmp41, <2 x i1> %Shuff66
+  %Cmp125 = icmp ult <4 x i64> %I38, %I38
+  %L126 = load i8, i8* %0
+  store i8 %L126, i8* %0
+  %E127 = extractelement <8 x i64> zeroinitializer, i32 7
+  %Shuff128 = shufflevector <2 x i1> %Cmp101, <2 x i1> %Cmp11, <2 x i32> <i32 undef, i32 0>
+  %I129 = insertelement <8 x i1> %Cmp18, i1 %E43, i32 0
+  %B130 = lshr i8 %L71, %L56
+  %FC131 = sitofp i32 %3 to float
+  %Sl132 = select i1 false, <2 x i64> %Shuff7, <2 x i64> %Sl84
+  %Cmp133 = icmp sge <8 x i16> %Tr, %Tr115
+  %L134 = load i8, i8* %0
+  store i8 %L102, i8* %0
+  %E135 = extractelement <16 x i8> %Shuff88, i32 3
+  %Shuff136 = shufflevector <8 x i64> %Shuff21, <8 x i64> zeroinitializer, <8 x i32> <i32 6, i32 8, i32 undef, i32 12, i32 14, i32 0, i32 2, i32 4>
+  %I137 = insertelement <2 x i64> zeroinitializer, i64 %E111, i32 0
+  %B138 = shl <8 x i64> %I51, %Shuff136
+  %Se = sext <2 x i32> %Tr32 to <2 x i64>
+  %Sl139 = select i1 %E43, <8 x i16> %Tr, <8 x i16> %Tr115
+  %Cmp140 = icmp sge <2 x i32> %Sl17, %Tr32
+  %L141 = load i8, i8* %0
+  store i8 17, i8* %0
+  %E142 = extractelement <8 x i16> %Tr115, i32 6
+  %Shuff143 = shufflevector <8 x i64> zeroinitializer, <8 x i64> %Shuff21, <8 x i32> <i32 1, i32 3, i32 undef, i32 7, i32 undef, i32 11, i32 13, i32 15>
+  %I144 = insertelement <4 x i64> %Shuff, i64 %4, i32 3
+  %B145 = sub <2 x i64> <i64 -1, i64 -1>, %I113
+  %Se146 = sext i8 %E135 to i32
+  %Sl147 = select i1 %Cmp55, <2 x i32> %Tr32, <2 x i32> zeroinitializer
+  %Cmp148 = icmp eq <8 x i1> %I30, %Cmp18
+  %L149 = load i8, i8* %0
+  store i8 %L56, i8* %0
+  %E150 = extractelement <2 x i64> %I113, i32 0
+  %Shuff151 = shufflevector <8 x i64> zeroinitializer, <8 x i64> %I, <8 x i32> <i32 9, i32 11, i32 13, i32 15, i32 1, i32 3, i32 undef, i32 7>
+  %I152 = insertelement <8 x i64> %Shuff136, i64 %E6, i32 3
+  %B153 = frem float %FC68, %FC123
+  %Se154 = sext i1 false to i32
+  %Sl155 = select i1 %Cmp26, i8 %E20, i8 %L19
+  %Cmp156 = icmp eq i64 198384, %4
+  br i1 %Cmp156, label %CF268, label %CF270
+
+CF270:                                            ; preds = %CF268
+  %L157 = load i8, i8* %0
+  store i8 %L157, i8* %0
+  %E158 = extractelement <8 x i1> %Cmp78, i32 1
+  br i1 %E158, label %CF255, label %CF260
+
+CF260:                                            ; preds = %CF270
+  %Shuff159 = shufflevector <8 x i64> zeroinitializer, <8 x i64> %Shuff81, <8 x i32> <i32 undef, i32 6, i32 8, i32 undef, i32 12, i32 14, i32 0, i32 2>
+  %I160 = insertelement <2 x i1> %Cmp11, i1 %Cmp156, i32 0
+  %B161 = urem <2 x i32> zeroinitializer, %Sl147
+  %Se162 = sext i8 %L48 to i16
+  %Sl163 = select i1 %Cmp93, i32 %FC83, i32 378892
+  %Cmp164 = fcmp uge double 0xE603EE221901D6A0, 0xE603EE221901D6A0
+  br i1 %Cmp164, label %CF253, label %CF254
+
+CF254:                                            ; preds = %CF254, %CF265, %CF263, %CF260
+  %L165 = load i8, i8* %0
+  store i8 %Sl62, i8* %0
+  %E166 = extractelement <8 x i64> %Shuff58, i32 1
+  %Shuff167 = shufflevector <8 x i64> %Shuff58, <8 x i64> %Shuff96, <8 x i32> <i32 12, i32 14, i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10>
+  %I168 = insertelement <2 x double> %BC91, double %BC, i32 0
+  %B169 = ashr i16 %E142, %E103
+  %FC170 = sitofp <2 x i64> %Sl84 to <2 x float>
+  %Sl171 = select i1 %Cmp156, i8 %L165, i8 %5
+  %Cmp172 = icmp ugt i8 %E20, %L102
+  br i1 %Cmp172, label %CF254, label %CF262
+
+CF262:                                            ; preds = %CF262, %CF254
+  %L173 = load i8, i8* %0
+  store i8 %L94, i8* %0
+  %E174 = extractelement <2 x i1> %Cmp70, i32 0
+  br i1 %E174, label %CF262, label %CF264
+
+CF264:                                            ; preds = %CF264, %CF262
+  %Shuff175 = shufflevector <16 x i1> %Cmp, <16 x i1> %Cmp, <16 x i32> <i32 undef, i32 9, i32 undef, i32 13, i32 undef, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 undef, i32 1, i32 3, i32 5>
+  %I176 = insertelement <8 x i64> %Shuff21, i64 419346, i32 1
+  %B177 = lshr <2 x i32> %Sl17, zeroinitializer
+  %FC178 = sitofp <8 x i32> %B106 to <8 x float>
+  %Sl179 = select i1 %Cmp156, i8 %B114, i8 %Sl171
+  %Cmp180 = icmp ugt <4 x i64> %B60, zeroinitializer
+  %L181 = load i8, i8* %0
+  store i8 %L102, i8* %0
+  %E182 = extractelement <8 x i64> zeroinitializer, i32 0
+  %Shuff183 = shufflevector <8 x i64> zeroinitializer, <8 x i64> %I176, <8 x i32> <i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 undef, i32 1>
+  %I184 = insertelement <2 x i1> %Cmp34, i1 %Cmp63, i32 1
+  %B185 = urem i32 %Sl163, %Se146
+  %FC186 = sitofp i64 %E166 to float
+  %Sl187 = select i1 %Cmp156, i1 %E43, i1 %Cmp26
+  br i1 %Sl187, label %CF264, label %CF265
+
+CF265:                                            ; preds = %CF264
+  %Cmp188 = icmp uge <16 x i1> %Shuff175, %Cmp
+  %L189 = load i8, i8* %0
+  store i8 %L19, i8* %0
+  %E190 = extractelement <2 x i1> %Cmp11, i32 0
+  br i1 %E190, label %CF254, label %CF259
+
+CF259:                                            ; preds = %CF259, %CF265
+  %Shuff191 = shufflevector <8 x i1> %Cmp117, <8 x i1> %I30, <8 x i32> <i32 11, i32 13, i32 15, i32 1, i32 3, i32 5, i32 7, i32 9>
+  %I192 = insertelement <16 x i1> %Cmp188, i1 %Cmp85, i32 13
+  %B193 = urem <2 x i64> %Sl132, %Sl54
+  %Tr194 = trunc i64 %E166 to i8
+  %Sl195 = select i1 %Cmp93, <2 x i1> %I160, <2 x i1> %Shuff66
+  %Cmp196 = icmp ult <2 x i1> %Shuff66, %Cmp11
+  %L197 = load i8, i8* %0
+  store i8 %L5, i8* %0
+  %E198 = extractelement <8 x i64> %Shuff183, i32 0
+  %Shuff199 = shufflevector <8 x i16> %I22, <8 x i16> %Tr115, <8 x i32> <i32 3, i32 5, i32 undef, i32 9, i32 11, i32 13, i32 15, i32 undef>
+  %I200 = insertelement <16 x i8> %Shuff29, i8 %L197, i32 5
+  %B201 = and <2 x i64> %B145, %I113
+  %ZE202 = zext <2 x i1> %I74 to <2 x i64>
+  %Sl203 = select i1 %Cmp26, i8 %L126, i8 %L102
+  %Cmp204 = fcmp oeq <4 x float> %BC53, %BC53
+  %L205 = load i8, i8* %0
+  store i8 %5, i8* %0
+  %E206 = extractelement <2 x double> %Shuff104, i32 0
+  %Shuff207 = shufflevector <4 x i64> %I38, <4 x i64> zeroinitializer, <4 x i32> <i32 7, i32 undef, i32 3, i32 5>
+  %I208 = insertelement <8 x i64> %I82, i64 323142, i32 1
+  %B209 = lshr i8 %L56, %L5
+  %FC210 = fptoui double 0xE603EE221901D6A0 to i1
+  br i1 %FC210, label %CF259, label %CF263
+
+CF263:                                            ; preds = %CF259
+  %Sl211 = select i1 %E174, i32 %ZE, i32 %ZE107
+  %Cmp212 = icmp ne i32 %Se154, %Sl163
+  br i1 %Cmp212, label %CF254, label %CF257
+
+CF257:                                            ; preds = %CF263
+  %L213 = load i8, i8* %0
+  store i8 %L213, i8* %0
+  %E214 = extractelement <8 x i64> %Shuff81, i32 3
+  %Shuff215 = shufflevector <8 x i64> %Shuff159, <8 x i64> %Shuff136, <8 x i32> <i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12>
+  %I216 = insertelement <8 x i64> %Shuff215, i64 323142, i32 0
+  %Se217 = sext i8 %L71 to i64
+  %Sl218 = select i1 %Cmp156, <8 x i16> %Tr115, <8 x i16> %Tr115
+  %Cmp219 = fcmp ole <2 x float> %FC170, %FC99
+  %L220 = load i8, i8* %0
+  store i8 %L19, i8* %0
+  %E221 = extractelement <8 x i64> zeroinitializer, i32 6
+  %Shuff222 = shufflevector <4 x i1> %Cmp204, <4 x i1> %Cmp125, <4 x i32> <i32 1, i32 undef, i32 5, i32 7>
+  %I223 = insertelement <8 x i1> %Cmp18, i1 %FC210, i32 3
+  %B224 = lshr i32 %E49, %FC24
+  %FC225 = sitofp <4 x i1> %Cmp180 to <4 x float>
+  %Sl226 = select i1 %Cmp93, i64 %E28, i64 %B23
+  %Cmp227 = icmp ugt <4 x i64> zeroinitializer, %B60
+  %L228 = load i8, i8* %0
+  store i8 %Sl46, i8* %0
+  %E229 = extractelement <1 x i32> zeroinitializer, i32 0
+  %Shuff230 = shufflevector <16 x i8> %Shuff29, <16 x i8> %I200, <16 x i32> <i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 undef, i32 undef, i32 29, i32 31, i32 1, i32 undef, i32 5, i32 undef, i32 9>
+  %I231 = insertelement <8 x i64> %Shuff183, i64 %L64, i32 5
+  %B232 = fadd float %FC68, %FC68
+  %Se233 = sext i1 %Cmp172 to i64
+  %Sl234 = select i1 false, i1 %Cmp164, i1 %E43
+  br label %CF
+
+CF:                                               ; preds = %CF, %CF257
+  %Cmp235 = icmp ule i32 %Sl163, %Sl211
+  br i1 %Cmp235, label %CF, label %CF252
+
+CF252:                                            ; preds = %CF252, %CF269, %CF
+  %L236 = load i8, i8* %0
+  store i8 %L19, i8* %0
+  %E237 = extractelement <16 x i1> %Shuff175, i32 15
+  br i1 %E237, label %CF252, label %CF269
+
+CF269:                                            ; preds = %CF252
+  %Shuff238 = shufflevector <2 x i1> %I160, <2 x i1> %Cmp101, <2 x i32> undef
+  %I239 = insertelement <8 x i64> zeroinitializer, i64 %4, i32 0
+  %B240 = add i8 %L56, %Sl155
+  %Tr241 = trunc <2 x i32> %Sl147 to <2 x i1>
+  %Sl242 = select i1 %Sl234, <2 x float> %FC99, <2 x float> %FC99
+  %Cmp243 = icmp eq i8 %L5, %L118
+  br i1 %Cmp243, label %CF252, label %CF258
+
+CF258:                                            ; preds = %CF258, %CF269
+  %L244 = load i8, i8* %0
+  store i8 %L19, i8* %0
+  %E245 = extractelement <2 x i64> %B201, i32 1
+  %Shuff246 = shufflevector <4 x i64> zeroinitializer, <4 x i64> %I144, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+  %I247 = insertelement <8 x i64> %Shuff73, i64 %E182, i32 2
+  %B248 = or i64 %Sl226, %E245
+  %Tr249 = trunc <2 x i64> <i64 -1, i64 -1> to <2 x i16>
+  %Sl250 = select i1 %FC210, i64 %E57, i64 %L64
+  %Cmp251 = icmp eq i32 %FC24, %FC
+  br i1 %Cmp251, label %CF258, label %CF267
+
+CF267:                                            ; preds = %CF258
+  store i8 %L42, i8* %0
+  store i8 %Sl69, i8* %0
+  store i8 %L5, i8* %0
+  store i8 %L134, i8* %0
+  store i8 %L141, i8* %0
+  ret void
+}
diff --git a/test/CodeGen/X86/fold-vector-trunc-sitofp.ll b/test/CodeGen/X86/fold-vector-trunc-sitofp.ll
new file mode 100644
index 000000000000..6a3be7aace13
--- /dev/null
+++ b/test/CodeGen/X86/fold-vector-trunc-sitofp.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s
+
+; Check that constant integers are correctly being truncated before float conversion
+
+define <4 x float> @test1() {
+; CHECK-LABEL: test1
+; CHECK: movaps {{.*#+}} xmm0 = [-1.000000e+00,0.000000e+00,-1.000000e+00,0.000000e+00]
+; CHECK-NEXT: ret
+  %1 = trunc <4 x i3> <i3 -1, i3 -22, i3 7, i3 8> to <4 x i1>
+  %2 = sitofp <4 x i1> %1 to <4 x float>
+  ret <4 x float> %2
+}
diff --git a/test/CodeGen/X86/fold-vex.ll b/test/CodeGen/X86/fold-vex.ll
index 5a8b1d8cbfdf..006db6effdf6 100644
--- a/test/CodeGen/X86/fold-vex.ll
+++ b/test/CodeGen/X86/fold-vex.ll
@@ -14,7 +14,7 @@
 ; unless specially configured on some CPUs such as AMD Family 10H.
 
 define <4 x i32> @test1(<4 x i32>* %p0, <4 x i32> %in1) nounwind {
-  %in0 = load <4 x i32>* %p0, align 2
+  %in0 = load <4 x i32>, <4 x i32>* %p0, align 2
   %a = and <4 x i32> %in0, %in1
   ret <4 x i32> %a
 
diff --git a/test/CodeGen/X86/fold-zext-trunc.ll b/test/CodeGen/X86/fold-zext-trunc.ll
index f901ad280b50..e36e8abdc3be 100644
--- a/test/CodeGen/X86/fold-zext-trunc.ll
+++ b/test/CodeGen/X86/fold-zext-trunc.ll
@@ -12,9 +12,9 @@ define void @foo() nounwind {
 ; CHECK-NOT: movzbl
 ; CHECK: calll
 entry:
-  %tmp17 = load i8* getelementptr inbounds (%struct.S0* @g_98, i32 0, i32 1, i32 0), align 4
+  %tmp17 = load i8, i8* getelementptr inbounds (%struct.S0, %struct.S0* @g_98, i32 0, i32 1, i32 0), align 4
   %tmp54 = zext i8 %tmp17 to i32
-  %foo = load i32* bitcast (i8* getelementptr inbounds (%struct.S0* @g_98, i32 0, i32 1, i32 0) to i32*), align 4
+  %foo = load i32, i32* bitcast (i8* getelementptr inbounds (%struct.S0, %struct.S0* @g_98, i32 0, i32 1, i32 0) to i32*), align 4
   %conv.i = trunc i32 %foo to i8
   tail call void @func_12(i32 %tmp54, i8 zeroext %conv.i) nounwind
   ret void
diff --git a/test/CodeGen/X86/force-align-stack-alloca.ll b/test/CodeGen/X86/force-align-stack-alloca.ll
index bd9806943920..a9ba20f45e84 100644
--- a/test/CodeGen/X86/force-align-stack-alloca.ll
+++ b/test/CodeGen/X86/force-align-stack-alloca.ll
@@ -10,7 +10,7 @@ target triple = "i386-unknown-linux-gnu"
 
 define i32 @f(i8* %p) nounwind {
 entry:
-  %0 = load i8* %p
+  %0 = load i8, i8* %p
   %conv = sext i8 %0 to i32
   ret i32 %conv
 }
diff --git a/test/CodeGen/X86/fp-double-rounding.ll b/test/CodeGen/X86/fp-double-rounding.ll
new file mode 100644
index 000000000000..c7578acbec27
--- /dev/null
+++ b/test/CodeGen/X86/fp-double-rounding.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SAFE
+; RUN: llc < %s -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK --check-prefix=UNSAFE
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64--"
+
+; CHECK-LABEL: double_rounding:
+; SAFE: callq __trunctfdf2
+; SAFE-NEXT: cvtsd2ss %xmm0
+; UNSAFE: callq __trunctfsf2
+; UNSAFE-NOT: cvt
+define void @double_rounding(fp128* %x, float* %f) {
+entry:
+  %0 = load fp128, fp128* %x, align 16
+  %1 = fptrunc fp128 %0 to double
+  %2 = fptrunc double %1 to float
+  store float %2, float* %f, align 4
+  ret void
+}
+
+; CHECK-LABEL: double_rounding_precise_first:
+; CHECK: fstps (%
+; CHECK-NOT: fstpl
+define void @double_rounding_precise_first(float* %f) {
+entry:
+  ; Hack, to generate a precise FP_ROUND to double
+  %precise = call double asm sideeffect "fld %st(0)", "={st(0)}"()
+  %0 = fptrunc double %precise to float
+  store float %0, float* %f, align 4
+  ret void
+}
diff --git a/test/CodeGen/X86/fp-fast.ll b/test/CodeGen/X86/fp-fast.ll
index 7b08ad67220b..27af5738ca3e 100644
--- a/test/CodeGen/X86/fp-fast.ll
+++ b/test/CodeGen/X86/fp-fast.ll
@@ -1,126 +1,116 @@
-; RUN: llc -march=x86-64 -mcpu=corei7-avx -enable-unsafe-fp-math < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx -enable-unsafe-fp-math < %s | FileCheck %s
 
-; CHECK-LABEL: test1
 define float @test1(float %a) {
-; CHECK-NOT: addss
-; CHECK: mulss
-; CHECK-NOT: addss
-; CHECK: ret
+; CHECK-LABEL: test1:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %t1 = fadd float %a, %a
   %r = fadd float %t1, %t1
   ret float %r
 }
 
-; CHECK-LABEL: test2
 define float @test2(float %a) {
-; CHECK-NOT: addss
-; CHECK: mulss
-; CHECK-NOT: addss
-; CHECK: ret
+; CHECK-LABEL: test2:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %t1 = fmul float 4.0, %a
   %t2 = fadd float %a, %a
   %r = fadd float %t1, %t2
   ret float %r
 }
 
-; CHECK-LABEL: test3
 define float @test3(float %a) {
-; CHECK-NOT: addss
-; CHECK: mulss
-; CHECK-NOT: addss
-; CHECK: ret
+; CHECK-LABEL: test3:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %t1 = fmul float %a, 4.0
   %t2 = fadd float %a, %a
   %r = fadd float %t1, %t2
   ret float %r
 }
 
-; CHECK-LABEL: test4
 define float @test4(float %a) {
-; CHECK-NOT: addss
-; CHECK: mulss
-; CHECK-NOT: addss
-; CHECK: ret
+; CHECK-LABEL: test4:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %t1 = fadd float %a, %a
   %t2 = fmul float 4.0, %a
   %r = fadd float %t1, %t2
   ret float %r
 }
 
-; CHECK-LABEL: test5
 define float @test5(float %a) {
-; CHECK-NOT: addss
-; CHECK: mulss
-; CHECK-NOT: addss
-; CHECK: ret
+; CHECK-LABEL: test5:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %t1 = fadd float %a, %a
   %t2 = fmul float %a, 4.0
   %r = fadd float %t1, %t2
   ret float %r
 }
 
-; CHECK-LABEL: test6
 define float @test6(float %a) {
-; CHECK-NOT: addss
-; CHECK: xorps
-; CHECK-NOT: addss
-; CHECK: ret
+; CHECK-LABEL: test6:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %t1 = fmul float 2.0, %a
   %t2 = fadd float %a, %a
   %r = fsub float %t1, %t2
   ret float %r
 }
 
-; CHECK-LABEL: test7
 define float @test7(float %a) {
-; CHECK-NOT: addss
-; CHECK: xorps
-; CHECK-NOT: addss
-; CHECK: ret
+; CHECK-LABEL: test7:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %t1 = fmul float %a, 2.0
   %t2 = fadd float %a, %a
   %r = fsub float %t1, %t2
   ret float %r
 }
 
-; CHECK-LABEL: test8
 define float @test8(float %a) {
-; CHECK-NOT: fma
-; CHECK-NOT: mul
-; CHECK-NOT: add
-; CHECK: ret
+; CHECK-LABEL: test8:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    retq
   %t1 = fmul float %a, 0.0
   %t2 = fadd float %a, %t1
   ret float %t2
 }
 
-; CHECK-LABEL: test9
 define float @test9(float %a) {
-; CHECK-NOT: fma
-; CHECK-NOT: mul
-; CHECK-NOT: add
-; CHECK: ret
+; CHECK-LABEL: test9:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    retq
   %t1 = fmul float 0.0, %a
   %t2 = fadd float %t1, %a
   ret float %t2
 }
 
-; CHECK-LABEL: test10
 define float @test10(float %a) {
-; CHECK-NOT: add
-; CHECK: vxorps
-; CHECK: ret
+; CHECK-LABEL: test10:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %t1 = fsub float -0.0, %a
   %t2 = fadd float %a, %t1
   ret float %t2
 }
 
-; CHECK-LABEL: test11
 define float @test11(float %a) {
-; CHECK-NOT: add
-; CHECK: vxorps
-; CHECK: ret
+; CHECK-LABEL: test11:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %t1 = fsub float -0.0, %a
   %t2 = fadd float %a, %t1
   ret float %t2
 }
+
diff --git a/test/CodeGen/X86/fp-load-trunc.ll b/test/CodeGen/X86/fp-load-trunc.ll
index e6c1e1adb59e..3896913857de 100644
--- a/test/CodeGen/X86/fp-load-trunc.ll
+++ b/test/CodeGen/X86/fp-load-trunc.ll
@@ -23,7 +23,7 @@ define <1 x float> @test1(<1 x double>* %p) nounwind {
 ; AVX-NEXT:    flds (%esp)
 ; AVX-NEXT:    popl %eax
 ; AVX-NEXT:    retl
-  %x = load <1 x double>* %p
+  %x = load <1 x double>, <1 x double>* %p
   %y = fptrunc <1 x double> %x to <1 x float>
   ret <1 x float> %y
 }
@@ -40,7 +40,7 @@ define <2 x float> @test2(<2 x double>* %p) nounwind {
 ; AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; AVX-NEXT:    vcvtpd2psx (%eax), %xmm0
 ; AVX-NEXT:    retl
-  %x = load <2 x double>* %p
+  %x = load <2 x double>, <2 x double>* %p
   %y = fptrunc <2 x double> %x to <2 x float>
   ret <2 x float> %y
 }
@@ -59,7 +59,7 @@ define <4 x float> @test3(<4 x double>* %p) nounwind {
 ; AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; AVX-NEXT:    vcvtpd2psy (%eax), %xmm0
 ; AVX-NEXT:    retl
-  %x = load <4 x double>* %p
+  %x = load <4 x double>, <4 x double>* %p
   %y = fptrunc <4 x double> %x to <4 x float>
   ret <4 x float> %y
 }
@@ -83,7 +83,7 @@ define <8 x float> @test4(<8 x double>* %p) nounwind {
 ; AVX-NEXT:    vcvtpd2psy 32(%eax), %xmm1
 ; AVX-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX-NEXT:    retl
-  %x = load <8 x double>* %p
+  %x = load <8 x double>, <8 x double>* %p
   %y = fptrunc <8 x double> %x to <8 x float>
   ret <8 x float> %y
 }
diff --git a/test/CodeGen/X86/fp-stack-O0-crash.ll b/test/CodeGen/X86/fp-stack-O0-crash.ll
index ae83a02c6744..5acfd5d3b618 100644
--- a/test/CodeGen/X86/fp-stack-O0-crash.ll
+++ b/test/CodeGen/X86/fp-stack-O0-crash.ll
@@ -11,14 +11,14 @@ entry:
   br i1 false, label %cond.true, label %cond.false
 
 cond.true:                                        ; preds = %entry
-  %tmp = load x86_fp80* %x.addr                   ; <x86_fp80> [#uses=1]
-  %tmp1 = load x86_fp80* %x.addr                  ; <x86_fp80> [#uses=1]
+  %tmp = load x86_fp80, x86_fp80* %x.addr                   ; <x86_fp80> [#uses=1]
+  %tmp1 = load x86_fp80, x86_fp80* %x.addr                  ; <x86_fp80> [#uses=1]
   %cmp = fcmp oeq x86_fp80 %tmp, %tmp1            ; <i1> [#uses=1]
   br i1 %cmp, label %if.then, label %if.end
 
 cond.false:                                       ; preds = %entry
-  %tmp2 = load x86_fp80* %x.addr                  ; <x86_fp80> [#uses=1]
-  %tmp3 = load x86_fp80* %x.addr                  ; <x86_fp80> [#uses=1]
+  %tmp2 = load x86_fp80, x86_fp80* %x.addr                  ; <x86_fp80> [#uses=1]
+  %tmp3 = load x86_fp80, x86_fp80* %x.addr                  ; <x86_fp80> [#uses=1]
   %cmp4 = fcmp une x86_fp80 %tmp2, %tmp3          ; <i1> [#uses=1]
   br i1 %cmp4, label %if.then, label %if.end
 
diff --git a/test/CodeGen/X86/fp-stack-O0.ll b/test/CodeGen/X86/fp-stack-O0.ll
index df90254dbd27..79ef28b163cd 100644
--- a/test/CodeGen/X86/fp-stack-O0.ll
+++ b/test/CodeGen/X86/fp-stack-O0.ll
@@ -17,7 +17,7 @@ declare i32 @x2(x86_fp80, x86_fp80) nounwind
 ; CHECK-NEXT: x2
 define i32 @test1() nounwind uwtable ssp {
 entry:
-  %call = call x86_fp80 (...)* bitcast (x86_fp80 (i32)* @x1 to x86_fp80 (...)*)(i32 -1)
+  %call = call x86_fp80 (...) bitcast (x86_fp80 (i32)* @x1 to x86_fp80 (...)*)(i32 -1)
   %call1 = call i32 @x2(x86_fp80 %call, x86_fp80 0xK401EFFFFFFFF00000000)
   ret i32 %call1
 }
diff --git a/test/CodeGen/X86/fp-stack-compare-cmov.ll b/test/CodeGen/X86/fp-stack-compare-cmov.ll
index b457fbc1a332..1d3548816b72 100644
--- a/test/CodeGen/X86/fp-stack-compare-cmov.ll
+++ b/test/CodeGen/X86/fp-stack-compare-cmov.ll
@@ -4,7 +4,7 @@
 define float @foo(float* %col.2.0) {
 ; CHECK: fucompi
 ; CHECK: fcmov
-  %tmp = load float* %col.2.0
+  %tmp = load float, float* %col.2.0
   %tmp16 = fcmp olt float %tmp, 0.000000e+00
   %tmp20 = fsub float -0.000000e+00, %tmp
   %iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp
diff --git a/test/CodeGen/X86/fp-stack-compare.ll b/test/CodeGen/X86/fp-stack-compare.ll
index a8557adeaf74..96088d759234 100644
--- a/test/CodeGen/X86/fp-stack-compare.ll
+++ b/test/CodeGen/X86/fp-stack-compare.ll
@@ -6,7 +6,7 @@ define float @foo(float* %col.2.0) {
 ; CHECK-NOT: fucompi
 ; CHECK: j
 ; CHECK-NOT: fcmov
-  %tmp = load float* %col.2.0
+  %tmp = load float, float* %col.2.0
   %tmp16 = fcmp olt float %tmp, 0.000000e+00
   %tmp20 = fsub float -0.000000e+00, %tmp
   %iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp
diff --git a/test/CodeGen/X86/fp-stack-ret-store.ll b/test/CodeGen/X86/fp-stack-ret-store.ll
index 05dfc545db17..c7cbb2a0561f 100644
--- a/test/CodeGen/X86/fp-stack-ret-store.ll
+++ b/test/CodeGen/X86/fp-stack-ret-store.ll
@@ -7,7 +7,7 @@ target triple = "i686-apple-darwin8"
 
 define void @bar(double* %P) {
 entry:
-	%tmp = tail call double (...)* @foo( )		; <double> [#uses=1]
+	%tmp = tail call double (...) @foo( )		; <double> [#uses=1]
 	store double %tmp, double* %P, align 8
 	ret void
 }
@@ -16,7 +16,7 @@ declare double @foo(...)
 
 define void @bar2(float* %P) {
 entry:
-	%tmp = tail call double (...)* @foo2( )		; <double> [#uses=1]
+	%tmp = tail call double (...) @foo2( )		; <double> [#uses=1]
 	%tmp1 = fptrunc double %tmp to float		; <float> [#uses=1]
 	store float %tmp1, float* %P, align 4
 	ret void
diff --git a/test/CodeGen/X86/fp-stack-ret.ll b/test/CodeGen/X86/fp-stack-ret.ll
index 2733117a1f02..9635e2d2511a 100644
--- a/test/CodeGen/X86/fp-stack-ret.ll
+++ b/test/CodeGen/X86/fp-stack-ret.ll
@@ -7,7 +7,7 @@
 ; CHECK: fldl
 ; CHECK-NEXT: ret
 define double @test1(double *%P) {
-        %A = load double* %P
+        %A = load double, double* %P
         ret double %A
 }
 
diff --git a/test/CodeGen/X86/fp-stack.ll b/test/CodeGen/X86/fp-stack.ll
index dca644de667e..44c039633886 100644
--- a/test/CodeGen/X86/fp-stack.ll
+++ b/test/CodeGen/X86/fp-stack.ll
@@ -5,9 +5,9 @@ target triple = "i386-pc-linux-gnu"
 
 define void @foo() nounwind {
 entry:
-  %tmp6 = load x86_fp80* undef                       ; <x86_fp80> [#uses=2]
-  %tmp15 = load x86_fp80* undef                      ; <x86_fp80> [#uses=2]
-  %tmp24 = load x86_fp80* undef                      ; <x86_fp80> [#uses=1]
+  %tmp6 = load x86_fp80, x86_fp80* undef                       ; <x86_fp80> [#uses=2]
+  %tmp15 = load x86_fp80, x86_fp80* undef                      ; <x86_fp80> [#uses=2]
+  %tmp24 = load x86_fp80, x86_fp80* undef                      ; <x86_fp80> [#uses=1]
   br i1 undef, label %return, label %bb.nph
 
 bb.nph:                                           ; preds = %entry
diff --git a/test/CodeGen/X86/fp-trunc.ll b/test/CodeGen/X86/fp-trunc.ll
index 6424bfc9c219..807a8c8fe5e3 100644
--- a/test/CodeGen/X86/fp-trunc.ll
+++ b/test/CodeGen/X86/fp-trunc.ll
@@ -1,6 +1,8 @@
 ; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
 ; RUN: llc < %s -march=x86 -mcpu=core-avx-i | FileCheck %s --check-prefix=AVX
 
+target triple = "i686-pc-linux-gnu"
+
 define <1 x float> @test1(<1 x double> %x) nounwind {
 ; CHECK-LABEL: test1:
 ; CHECK:       # BB#0:
@@ -59,12 +61,14 @@ define <4 x float> @test3(<4 x double> %x) nounwind {
 define <8 x float> @test4(<8 x double> %x) nounwind {
 ; CHECK-LABEL: test4:
 ; CHECK:       # BB#0:
+; CHECK-NEXT:    subl $12, %esp
 ; CHECK-NEXT:    cvtpd2ps %xmm1, %xmm1
 ; CHECK-NEXT:    cvtpd2ps %xmm0, %xmm0
 ; CHECK-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; CHECK-NEXT:    cvtpd2ps %xmm3, %xmm3
 ; CHECK-NEXT:    cvtpd2ps %xmm2, %xmm1
-; CHECK-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm3[0]
+; CHECK-NEXT:    cvtpd2ps 16(%esp), %xmm2
+; CHECK-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; CHECK-NEXT:    addl $12, %esp
 ; CHECK-NEXT:    retl
 ;
 ; AVX-LABEL: test4:
diff --git a/test/CodeGen/X86/fp2sint.ll b/test/CodeGen/X86/fp2sint.ll
index 167544488713..b41f56f9f41e 100644
--- a/test/CodeGen/X86/fp2sint.ll
+++ b/test/CodeGen/X86/fp2sint.ll
@@ -4,10 +4,10 @@
 
 define i32 @main(i32 %argc, i8** %argv) {
 cond_false.i.i.i:               ; preds = %bb.i5
-       %tmp35.i = load double* null, align 8           ; <double> [#uses=1]
+       %tmp35.i = load double, double* null, align 8           ; <double> [#uses=1]
        %tmp3536.i = fptosi double %tmp35.i to i32              ; <i32> [#uses=1]
        %tmp3536140.i = zext i32 %tmp3536.i to i64              ; <i64> [#uses=1]
-       %tmp39.i = load double* null, align 4           ; <double> [#uses=1]
+       %tmp39.i = load double, double* null, align 4           ; <double> [#uses=1]
        %tmp3940.i = fptosi double %tmp39.i to i32              ; <i32> [#uses=1]
        %tmp3940137.i = zext i32 %tmp3940.i to i64              ; <i64> [#uses=1]
        %tmp3940137138.i = shl i64 %tmp3940137.i, 32            ; <i64> [#uses=1]
diff --git a/test/CodeGen/X86/fp_load_cast_fold.ll b/test/CodeGen/X86/fp_load_cast_fold.ll
index 72ea12f9430e..5fd22e3fa6e5 100644
--- a/test/CodeGen/X86/fp_load_cast_fold.ll
+++ b/test/CodeGen/X86/fp_load_cast_fold.ll
@@ -1,19 +1,19 @@
 ; RUN: llc < %s -march=x86 | FileCheck %s
 
 define double @short(i16* %P) {
-        %V = load i16* %P               ; <i16> [#uses=1]
+        %V = load i16, i16* %P               ; <i16> [#uses=1]
         %V2 = sitofp i16 %V to double           ; <double> [#uses=1]
         ret double %V2
 }
 
 define double @int(i32* %P) {
-        %V = load i32* %P               ; <i32> [#uses=1]
+        %V = load i32, i32* %P               ; <i32> [#uses=1]
         %V2 = sitofp i32 %V to double           ; <double> [#uses=1]
         ret double %V2
 }
 
 define double @long(i64* %P) {
-        %V = load i64* %P               ; <i64> [#uses=1]
+        %V = load i64, i64* %P               ; <i64> [#uses=1]
         %V2 = sitofp i64 %V to double           ; <double> [#uses=1]
         ret double %V2
 }
diff --git a/test/CodeGen/X86/fp_load_fold.ll b/test/CodeGen/X86/fp_load_fold.ll
index a2cea5e57f64..57497454792b 100644
--- a/test/CodeGen/X86/fp_load_fold.ll
+++ b/test/CodeGen/X86/fp_load_fold.ll
@@ -4,37 +4,37 @@
 ; Test that the load of the memory location is folded into the operation.
 
 define double @test_add(double %X, double* %P) {
-	%Y = load double* %P		; <double> [#uses=1]
+	%Y = load double, double* %P		; <double> [#uses=1]
 	%R = fadd double %X, %Y		; <double> [#uses=1]
 	ret double %R
 }
 
 define double @test_mul(double %X, double* %P) {
-	%Y = load double* %P		; <double> [#uses=1]
+	%Y = load double, double* %P		; <double> [#uses=1]
 	%R = fmul double %X, %Y		; <double> [#uses=1]
 	ret double %R
 }
 
 define double @test_sub(double %X, double* %P) {
-	%Y = load double* %P		; <double> [#uses=1]
+	%Y = load double, double* %P		; <double> [#uses=1]
 	%R = fsub double %X, %Y		; <double> [#uses=1]
 	ret double %R
 }
 
 define double @test_subr(double %X, double* %P) {
-	%Y = load double* %P		; <double> [#uses=1]
+	%Y = load double, double* %P		; <double> [#uses=1]
 	%R = fsub double %Y, %X		; <double> [#uses=1]
 	ret double %R
 }
 
 define double @test_div(double %X, double* %P) {
-	%Y = load double* %P		; <double> [#uses=1]
+	%Y = load double, double* %P		; <double> [#uses=1]
 	%R = fdiv double %X, %Y		; <double> [#uses=1]
 	ret double %R
 }
 
 define double @test_divr(double %X, double* %P) {
-	%Y = load double* %P		; <double> [#uses=1]
+	%Y = load double, double* %P		; <double> [#uses=1]
 	%R = fdiv double %Y, %X		; <double> [#uses=1]
 	ret double %R
 }
diff --git a/test/CodeGen/X86/fpstack-debuginstr-kill.ll b/test/CodeGen/X86/fpstack-debuginstr-kill.ll
index e3180f4e68a2..34398414a76c 100644
--- a/test/CodeGen/X86/fpstack-debuginstr-kill.ll
+++ b/test/CodeGen/X86/fpstack-debuginstr-kill.ll
@@ -32,7 +32,7 @@ sw.bb735:                                         ; preds = %if.end511
   unreachable
 
 if.end41.i2210:                                   ; preds = %if.end511
-  call void @llvm.dbg.value(metadata x86_fp80 %src.sroa.0.0.src.sroa.0.0.2280, i64 0, metadata !20, metadata !{!"0x102"})
+  call void @llvm.dbg.value(metadata x86_fp80 %src.sroa.0.0.src.sroa.0.0.2280, i64 0, metadata !20, metadata !DIExpression()), !dbg !DILocation(scope: !4)
   unreachable
 
 sw.bb992:                                         ; preds = %if.end511
@@ -43,29 +43,29 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
 
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!24, !25}
-!0 = !{!"0x11\004\00clang version 3.6.0 (http://llvm.org/git/clang 8444ae7cfeaefae031f8fedf0d1435ca3b14d90b) (http://llvm.org/git/llvm 886f0101a7d176543b831f5efb74c03427244a55)\001\00\000\00\001", !1, !2, !2, !3, !21, !2} ; [ DW_TAG_compile_unit ] [x87stackifier/fpu_ieee.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"fpu_ieee.cpp", !"x87stackifier"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 (http://llvm.org/git/clang 8444ae7cfeaefae031f8fedf0d1435ca3b14d90b) (http://llvm.org/git/llvm 886f0101a7d176543b831f5efb74c03427244a55)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !21, imports: !2)
+!1 = !DIFile(filename: "fpu_ieee.cpp", directory: "x87stackifier")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00fpuop_arithmetic\00fpuop_arithmetic\00_Z16fpuop_arithmeticjj\0011\000\001\000\006\00256\001\0013", !5, !6, !7, null, void (i32, i32)* @_Z16fpuop_arithmeticjj, null, null, !10} ; [ DW_TAG_subprogram ] [line 11] [def] [scope 13] [fpuop_arithmetic]
-!5 = !{!"f1.cpp", !"x87stackifier"}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [x87stackifier/f1.cpp]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "fpuop_arithmetic", linkageName: "_Z16fpuop_arithmeticjj", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 13, file: !5, scope: !6, type: !7, function: void (i32, i32)* @_Z16fpuop_arithmeticjj, variables: !10)
+!5 = !DIFile(filename: "f1.cpp", directory: "x87stackifier")
+!6 = !DIFile(filename: "f1.cpp", directory: "x87stackifier")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9, !9}
-!9 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, null} ; [ DW_TAG_base_type ] [unsigned int] [line 0, size 32, align 32, offset 0, enc DW_ATE_unsigned]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
 !10 = !{!11, !12, !13, !18, !20}
-!11 = !{!"0x101\00\0016777227\000", !4, !6, !9} ; [ DW_TAG_arg_variable ] [line 11]
-!12 = !{!"0x101\00\0033554443\000", !4, !6, !9} ; [ DW_TAG_arg_variable ] [line 11]
-!13 = !{!"0x100\00x\0014\000", !4, !6, !14} ; [ DW_TAG_auto_variable ] [x] [line 14]
-!14 = !{!"0x16\00fpu_extended\003\000\000\000\000", !5, null, !15} ; [ DW_TAG_typedef ] [fpu_extended] [line 3, size 0, align 0, offset 0] [from fpu_register]
-!15 = !{!"0x16\00fpu_register\002\000\000\000\000", !5, null, !16} ; [ DW_TAG_typedef ] [fpu_register] [line 2, size 0, align 0, offset 0] [from uae_f64]
-!16 = !{!"0x16\00uae_f64\001\000\000\000\000", !5, null, !17} ; [ DW_TAG_typedef ] [uae_f64] [line 1, size 0, align 0, offset 0] [from double]
-!17 = !{!"0x24\00double\000\0064\0064\000\000\004", null, null} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float]
-!18 = !{!"0x100\00a\0015\000", !4, !6, !19} ; [ DW_TAG_auto_variable ] [a] [line 15]
-!19 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!20 = !{!"0x100\00value\0016\000", !4, !6, !14} ; [ DW_TAG_auto_variable ] [value] [line 16]
+!11 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "", line: 11, arg: 1, scope: !4, file: !6, type: !9)
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "", line: 11, arg: 2, scope: !4, file: !6, type: !9)
+!13 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 14, scope: !4, file: !6, type: !14)
+!14 = !DIDerivedType(tag: DW_TAG_typedef, name: "fpu_extended", line: 3, file: !5, baseType: !15)
+!15 = !DIDerivedType(tag: DW_TAG_typedef, name: "fpu_register", line: 2, file: !5, baseType: !16)
+!16 = !DIDerivedType(tag: DW_TAG_typedef, name: "uae_f64", line: 1, file: !5, baseType: !17)
+!17 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 64, encoding: DW_ATE_float)
+!18 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 15, scope: !4, file: !6, type: !19)
+!19 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!20 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "value", line: 16, scope: !4, file: !6, type: !14)
 !21 = !{!22, !23}
-!22 = !{!"0x34\00g1\00g1\00\005\000\001", null, !6, !14, double* @g1, null} ; [ DW_TAG_variable ] [g1] [line 5] [def]
-!23 = !{!"0x34\00g2\00g2\00\006\000\001", null, !6, !19, i32* @g2, null} ; [ DW_TAG_variable ] [g2] [line 6] [def]
+!22 = !DIGlobalVariable(name: "g1", line: 5, isLocal: false, isDefinition: true, scope: null, file: !6, type: !14, variable: double* @g1)
+!23 = !DIGlobalVariable(name: "g2", line: 6, isLocal: false, isDefinition: true, scope: null, file: !6, type: !19, variable: i32* @g2)
 !24 = !{i32 2, !"Dwarf Version", i32 2}
-!25 = !{i32 2, !"Debug Info Version", i32 2}
+!25 = !{i32 2, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/frameaddr.ll b/test/CodeGen/X86/frameaddr.ll
index 3e0f8bc34d64..5ed2ba0f4314 100644
--- a/test/CodeGen/X86/frameaddr.ll
+++ b/test/CodeGen/X86/frameaddr.ll
@@ -1,11 +1,12 @@
 ; RUN: llc < %s -march=x86                                | FileCheck %s --check-prefix=CHECK-32
-; RUN: llc < %s -march=x86    -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-32
-; RUN: llc < %s -march=x86-64                             | FileCheck %s --check-prefix=CHECK-64
-; RUN: llc < %s -march=x86-64 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc < %s -march=x86    -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc < %s -mtriple=x86_64-pc-win32 -fast-isel | FileCheck %s --check-prefix=CHECK-W64
+; RUN: llc < %s -mtriple=x86_64-unknown                             | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc < %s -mtriple=x86_64-unknown -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-64
 ; RUN: llc < %s -mtriple=x86_64-gnux32                    | FileCheck %s --check-prefix=CHECK-X32ABI
-; RUN: llc < %s -mtriple=x86_64-gnux32 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-X32ABI
+; RUN: llc < %s -mtriple=x86_64-gnux32 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-X32ABI
 ; RUN: llc < %s -mtriple=x86_64-nacl                    | FileCheck %s --check-prefix=CHECK-NACL64
-; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-NACL64
+; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-NACL64
 
 define i8* @test1() nounwind {
 entry:
@@ -15,6 +16,12 @@ entry:
 ; CHECK-32-NEXT:  movl %ebp, %eax
 ; CHECK-32-NEXT:  pop
 ; CHECK-32-NEXT:  ret
+; CHECK-W64-LABEL: test1
+; CHECK-W64:       push
+; CHECK-W64-NEXT:  movq %rsp, %rbp
+; CHECK-W64-NEXT:  leaq (%rbp), %rax
+; CHECK-W64-NEXT:  pop
+; CHECK-W64-NEXT:  ret
 ; CHECK-64-LABEL: test1
 ; CHECK-64:       push
 ; CHECK-64-NEXT:  movq %rsp, %rbp
@@ -44,6 +51,12 @@ entry:
 ; CHECK-32-NEXT:  movl (%eax), %eax
 ; CHECK-32-NEXT:  pop
 ; CHECK-32-NEXT:  ret
+; CHECK-W64-LABEL: test2
+; CHECK-W64:       push
+; CHECK-W64-NEXT:  movq %rsp, %rbp
+; CHECK-W64-NEXT:  leaq (%rbp), %rax
+; CHECK-W64-NEXT:  pop
+; CHECK-W64-NEXT:  ret
 ; CHECK-64-LABEL: test2
 ; CHECK-64:       push
 ; CHECK-64-NEXT:  movq %rsp, %rbp
diff --git a/test/CodeGen/X86/frameallocate.ll b/test/CodeGen/X86/frameallocate.ll
deleted file mode 100644
index 13d35b91937d..000000000000
--- a/test/CodeGen/X86/frameallocate.ll
+++ /dev/null
@@ -1,39 +0,0 @@
-; RUN: llc -mtriple=x86_64-windows-msvc < %s | FileCheck %s
-
-declare i8* @llvm.frameallocate(i32)
-declare i8* @llvm.frameaddress(i32)
-declare i8* @llvm.framerecover(i8*, i8*)
-declare i32 @printf(i8*, ...)
-
-@str = internal constant [10 x i8] c"asdf: %d\0A\00"
-
-define void @print_framealloc_from_fp(i8* %fp) {
-  %alloc = call i8* @llvm.framerecover(i8* bitcast (void(i32*, i32*)* @alloc_func to i8*), i8* %fp)
-  %alloc_i32 = bitcast i8* %alloc to i32*
-  %r = load i32* %alloc_i32
-  call i32 (i8*, ...)* @printf(i8* getelementptr ([10 x i8]* @str, i32 0, i32 0), i32 %r)
-  ret void
-}
-
-; CHECK-LABEL: print_framealloc_from_fp:
-; CHECK: movabsq $.Lframeallocation_alloc_func, %[[offs:[a-z]+]]
-; CHECK: movl (%rcx,%[[offs]]), %edx
-; CHECK: leaq {{.*}}(%rip), %rcx
-; CHECK: callq printf
-; CHECK: retq
-
-define void @alloc_func(i32* %s, i32* %d) {
-  %alloc = call i8* @llvm.frameallocate(i32 16)
-  %alloc_i32 = bitcast i8* %alloc to i32*
-  store i32 42, i32* %alloc_i32
-  %fp = call i8* @llvm.frameaddress(i32 0)
-  call void @print_framealloc_from_fp(i8* %fp)
-  ret void
-}
-
-; CHECK-LABEL: alloc_func:
-; CHECK: .Lframeallocation_alloc_func = -[[offs:[0-9]+]]
-; CHECK: movl $42, -[[offs]](%rbp)
-; CHECK: movq %rbp, %rcx
-; CHECK: callq print_framealloc_from_fp
-; CHECK: retq
diff --git a/test/CodeGen/X86/frameescape.ll b/test/CodeGen/X86/frameescape.ll
new file mode 100644
index 000000000000..00bc55d24878
--- /dev/null
+++ b/test/CodeGen/X86/frameescape.ll
@@ -0,0 +1,128 @@
+; RUN: llc -mtriple=i686-windows-msvc < %s | FileCheck %s --check-prefix=X86
+; RUN: llc -mtriple=x86_64-windows-msvc < %s | FileCheck %s --check-prefix=X64
+
+declare void @llvm.frameescape(...)
+declare i8* @llvm.frameaddress(i32)
+declare i8* @llvm.framerecover(i8*, i8*, i32)
+declare i32 @printf(i8*, ...)
+
+@str = internal constant [10 x i8] c"asdf: %d\0A\00"
+
+define void @print_framealloc_from_fp(i8* %fp) {
+  %a.i8 = call i8* @llvm.framerecover(i8* bitcast (void()* @alloc_func to i8*), i8* %fp, i32 0)
+  %a = bitcast i8* %a.i8 to i32*
+  %a.val = load i32, i32* %a
+  call i32 (i8*, ...) @printf(i8* getelementptr ([10 x i8], [10 x i8]* @str, i32 0, i32 0), i32 %a.val)
+  %b.i8 = call i8* @llvm.framerecover(i8* bitcast (void()* @alloc_func to i8*), i8* %fp, i32 1)
+  %b = bitcast i8* %b.i8 to i32*
+  %b.val = load i32, i32* %b
+  call i32 (i8*, ...) @printf(i8* getelementptr ([10 x i8], [10 x i8]* @str, i32 0, i32 0), i32 %b.val)
+  store i32 42, i32* %b
+  %b2 = getelementptr i32, i32* %b, i32 1
+  %b2.val = load i32, i32* %b2
+  call i32 (i8*, ...) @printf(i8* getelementptr ([10 x i8], [10 x i8]* @str, i32 0, i32 0), i32 %b2.val)
+  ret void
+}
+
+; X64-LABEL: print_framealloc_from_fp:
+; X64: movq %rcx, %[[parent_fp:[a-z]+]]
+; X64: movl .Lalloc_func$frame_escape_0(%[[parent_fp]]), %edx
+; X64: leaq {{.*}}(%rip), %[[str:[a-z]+]]
+; X64: movq %[[str]], %rcx
+; X64: callq printf
+; X64: movl .Lalloc_func$frame_escape_1(%[[parent_fp]]), %edx
+; X64: movq %[[str]], %rcx
+; X64: callq printf
+; X64: movl    $42, .Lalloc_func$frame_escape_1(%[[parent_fp]])
+; X64: retq
+
+; X86-LABEL: print_framealloc_from_fp:
+; X86: pushl   %esi
+; X86: subl    $8, %esp
+; X86: movl    16(%esp), %esi
+; X86: movl    Lalloc_func$frame_escape_0(%esi), %eax
+; X86: movl    %eax, 4(%esp)
+; X86: movl    $_str, (%esp)
+; X86: calll   _printf
+; X86: movl    Lalloc_func$frame_escape_1(%esi), %eax
+; X86: movl    %eax, 4(%esp)
+; X86: movl    $_str, (%esp)
+; X86: calll   _printf
+; X86: movl    $42, Lalloc_func$frame_escape_1(%esi)
+; X86: movl    $4, %eax
+; X86: movl    Lalloc_func$frame_escape_1(%esi,%eax), %eax
+; X86: movl    %eax, 4(%esp)
+; X86: movl    $_str, (%esp)
+; X86: calll   _printf
+; X86: addl    $8, %esp
+; X86: popl    %esi
+; X86: retl
+
+define void @alloc_func() {
+  %a = alloca i32
+  %b = alloca i32, i32 2
+  call void (...) @llvm.frameescape(i32* %a, i32* %b)
+  store i32 42, i32* %a
+  store i32 13, i32* %b
+  %fp = call i8* @llvm.frameaddress(i32 0)
+  call void @print_framealloc_from_fp(i8* %fp)
+  ret void
+}
+
+; X64-LABEL: alloc_func:
+; X64: subq    $48, %rsp
+; X64: .seh_stackalloc 48
+; X64: leaq    48(%rsp), %rbp
+; X64: .seh_setframe 5, 48
+; X64: .Lalloc_func$frame_escape_0 = 44
+; X64: .Lalloc_func$frame_escape_1 = 36
+; X64: movl $42, -4(%rbp)
+; X64: movl $13, -12(%rbp)
+; X64: leaq    -48(%rbp), %rcx
+; X64: callq print_framealloc_from_fp
+; X64: retq
+
+; X86-LABEL: alloc_func:
+; X86: pushl   %ebp
+; X86: movl    %esp, %ebp
+; X86: subl    $16, %esp
+; X86: Lalloc_func$frame_escape_0 = -4
+; X86: Lalloc_func$frame_escape_1 = -12
+; X86: movl    $42, -4(%ebp)
+; X86: movl    $13, -12(%ebp)
+; X86: movl    %ebp, (%esp)
+; X86: calll   _print_framealloc_from_fp
+; X86: addl    $16, %esp
+; X86: popl    %ebp
+; X86: retl
+
+; Helper to make this a complete program so it can be compiled and tested.
+define i32 @main() {
+  call void @alloc_func()
+  ret i32 0
+}
+
+define void @alloc_func_no_frameaddr() {
+  %a = alloca i32
+  %b = alloca i32
+  call void (...) @llvm.frameescape(i32* %a, i32* %b)
+  store i32 42, i32* %a
+  store i32 13, i32* %b
+  call void @print_framealloc_from_fp(i8* null)
+  ret void
+}
+
+; X64-LABEL: alloc_func_no_frameaddr:
+; X64: subq    $40, %rsp
+; X64: .seh_stackalloc 40
+; X64: .seh_endprologue
+; X64: .Lalloc_func_no_frameaddr$frame_escape_0 = 36
+; X64: .Lalloc_func_no_frameaddr$frame_escape_1 = 32
+; X64: movl $42, 36(%rsp)
+; X64: movl $13, 32(%rsp)
+; X64: xorl %ecx, %ecx
+; X64: callq print_framealloc_from_fp
+; X64: addq $40, %rsp
+; X64: retq
+
+; X86-LABEL: alloc_func_no_frameaddr:
diff --git a/test/CodeGen/X86/full-lsr.ll b/test/CodeGen/X86/full-lsr.ll
index cbcc62a7011a..85b2b41fa191 100644
--- a/test/CodeGen/X86/full-lsr.ll
+++ b/test/CodeGen/X86/full-lsr.ll
@@ -18,20 +18,20 @@ entry:
 
 bb:		; preds = %bb, %entry
 	%i.03 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]		; <i32> [#uses=5]
-	%1 = getelementptr float* %A, i32 %i.03		; <float*> [#uses=1]
-	%2 = load float* %1, align 4		; <float> [#uses=1]
-	%3 = getelementptr float* %B, i32 %i.03		; <float*> [#uses=1]
-	%4 = load float* %3, align 4		; <float> [#uses=1]
+	%1 = getelementptr float, float* %A, i32 %i.03		; <float*> [#uses=1]
+	%2 = load float, float* %1, align 4		; <float> [#uses=1]
+	%3 = getelementptr float, float* %B, i32 %i.03		; <float*> [#uses=1]
+	%4 = load float, float* %3, align 4		; <float> [#uses=1]
 	%5 = fadd float %2, %4		; <float> [#uses=1]
-	%6 = getelementptr float* %C, i32 %i.03		; <float*> [#uses=1]
+	%6 = getelementptr float, float* %C, i32 %i.03		; <float*> [#uses=1]
 	store float %5, float* %6, align 4
 	%7 = add i32 %i.03, 10		; <i32> [#uses=3]
-	%8 = getelementptr float* %A, i32 %7		; <float*> [#uses=1]
-	%9 = load float* %8, align 4		; <float> [#uses=1]
-	%10 = getelementptr float* %B, i32 %7		; <float*> [#uses=1]
-	%11 = load float* %10, align 4		; <float> [#uses=1]
+	%8 = getelementptr float, float* %A, i32 %7		; <float*> [#uses=1]
+	%9 = load float, float* %8, align 4		; <float> [#uses=1]
+	%10 = getelementptr float, float* %B, i32 %7		; <float*> [#uses=1]
+	%11 = load float, float* %10, align 4		; <float> [#uses=1]
 	%12 = fadd float %9, %11		; <float> [#uses=1]
-	%13 = getelementptr float* %C, i32 %7		; <float*> [#uses=1]
+	%13 = getelementptr float, float* %C, i32 %7		; <float*> [#uses=1]
 	store float %12, float* %13, align 4
 	%indvar.next = add i32 %i.03, 1		; <i32> [#uses=2]
 	%exitcond = icmp eq i32 %indvar.next, %N		; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/function-subtarget-features-2.ll b/test/CodeGen/X86/function-subtarget-features-2.ll
new file mode 100644
index 000000000000..d7c7c2fdb6fe
--- /dev/null
+++ b/test/CodeGen/X86/function-subtarget-features-2.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86-64 -filetype=obj -o - | llvm-objdump -d - | FileCheck %s
+
+; This test verifies that we assemble code for different architectures
+; based on target-cpu and target-features attributes.
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+define void @foo() #0 {
+entry:
+  call void asm sideeffect "aeskeygenassist  $$0x4, %xmm0, %xmm1", "~{dirflag},~{fpsr},~{flags}"()
+  ret void
+}
+
+; CHECK: foo
+; CHECK: aeskeygenassist
+
+define void @bar() #2 {
+entry:
+  call void asm sideeffect "crc32b 4(%rbx), %eax", "~{dirflag},~{fpsr},~{flags}"()
+  ret void
+}
+
+; CHECK: bar
+; CHECK: crc32b
+
+attributes #0 = { "target-cpu"="x86-64" "target-features"="+avx2" }
+attributes #2 = { "target-cpu"="corei7" "target-features"="+sse4.2" }
diff --git a/test/CodeGen/X86/function-subtarget-features.ll b/test/CodeGen/X86/function-subtarget-features.ll
new file mode 100644
index 000000000000..b1e2585be004
--- /dev/null
+++ b/test/CodeGen/X86/function-subtarget-features.ll
@@ -0,0 +1,81 @@
+; RUN: llc < %s -march=x86-64 -o - | FileCheck %s
+
+; This test verifies that we produce different code for different architectures
+; based on target-cpu and target-features attributes.
+; In this case avx has a vmovss instruction and otherwise we should be using movss
+; to materialize constants.
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+define float @_Z3barv() #0 {
+entry:
+  ret float 4.000000e+00
+}
+
+; CHECK: barv
+; CHECK: vmovss
+
+define float @_Z4testv() #1 {
+entry:
+  ret float 1.000000e+00
+}
+
+; CHECK: testv
+; CHECK: movss
+
+define float @_Z3foov() #2 {
+entry:
+  ret float 4.000000e+00
+}
+
+; CHECK: foov
+; CHECK: movss
+
+define float @_Z3bazv() #0 {
+entry:
+  ret float 4.000000e+00
+}
+
+; CHECK: bazv
+; CHECK: vmovss
+
+define <2 x i64> @foo(<2 x i64> %a) #3 {
+entry:
+  %a.addr = alloca <2 x i64>, align 16
+  store <2 x i64> %a, <2 x i64>* %a.addr, align 16
+  %0 = load <2 x i64>, <2 x i64>* %a.addr, align 16
+  %1 = call <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64> %0, i8 4)
+  ret <2 x i64> %1
+}
+
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8)
+
+; CHECK: foo
+; CHECK: aeskeygenassist
+
+; Function Attrs: nounwind uwtable
+define i32 @bar(i32 %crc, i8* %a) #3 {
+entry:
+  %crc.addr = alloca i32, align 4
+  %a.addr = alloca i8*, align 8
+  store i32 %crc, i32* %crc.addr, align 4
+  store i8* %a, i8** %a.addr, align 8
+  %0 = load i32, i32* %crc.addr, align 4
+  %1 = load i8*, i8** %a.addr, align 8
+  %incdec.ptr = getelementptr inbounds i8, i8* %1, i32 1
+  store i8* %incdec.ptr, i8** %a.addr, align 8
+  %2 = load i8, i8* %1, align 1
+  %3 = call i32 @llvm.x86.sse42.crc32.32.8(i32 %0, i8 %2)
+  ret i32 %3
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8)
+
+; CHECK: bar
+; CHECK: crc32b
+
+attributes #0 = { "target-cpu"="x86-64" "target-features"="+avx2" }
+attributes #1 = { "target-cpu"="x86-64" }
+attributes #2 = { "target-cpu"="corei7" "target-features"="+sse4.2" }
+attributes #3 = { "target-cpu"="x86-64" "target-features"="+avx2,+aes" }
diff --git a/test/CodeGen/X86/ga-offset.ll b/test/CodeGen/X86/ga-offset.ll
index 9f6d3f75cf84..934c14921e99 100644
--- a/test/CodeGen/X86/ga-offset.ll
+++ b/test/CodeGen/X86/ga-offset.ll
@@ -13,6 +13,6 @@
 @dst = global [131072 x i32] zeroinitializer
 
 define void @foo() nounwind {
-  store i32* getelementptr ([131072 x i32]* @dst, i32 0, i32 16), i32** @ptr
+  store i32* getelementptr ([131072 x i32], [131072 x i32]* @dst, i32 0, i32 16), i32** @ptr
   ret void
 }
diff --git a/test/CodeGen/X86/gather-addresses.ll b/test/CodeGen/X86/gather-addresses.ll
index 6d397b211481..f7d4eb380d57 100644
--- a/test/CodeGen/X86/gather-addresses.ll
+++ b/test/CodeGen/X86/gather-addresses.ll
@@ -35,21 +35,21 @@
 ; WIN: movhpd	(%rcx,%r[[REG4]],8), %xmm1
 
 define <4 x double> @foo(double* %p, <4 x i32>* %i, <4 x i32>* %h) nounwind {
-  %a = load <4 x i32>* %i
-  %b = load <4 x i32>* %h
+  %a = load <4 x i32>, <4 x i32>* %i
+  %b = load <4 x i32>, <4 x i32>* %h
   %j = and <4 x i32> %a, %b
   %d0 = extractelement <4 x i32> %j, i32 0
   %d1 = extractelement <4 x i32> %j, i32 1
   %d2 = extractelement <4 x i32> %j, i32 2
   %d3 = extractelement <4 x i32> %j, i32 3
-  %q0 = getelementptr double* %p, i32 %d0
-  %q1 = getelementptr double* %p, i32 %d1
-  %q2 = getelementptr double* %p, i32 %d2
-  %q3 = getelementptr double* %p, i32 %d3
-  %r0 = load double* %q0
-  %r1 = load double* %q1
-  %r2 = load double* %q2
-  %r3 = load double* %q3
+  %q0 = getelementptr double, double* %p, i32 %d0
+  %q1 = getelementptr double, double* %p, i32 %d1
+  %q2 = getelementptr double, double* %p, i32 %d2
+  %q3 = getelementptr double, double* %p, i32 %d3
+  %r0 = load double, double* %q0
+  %r1 = load double, double* %q1
+  %r2 = load double, double* %q2
+  %r3 = load double, double* %q3
   %v0 = insertelement <4 x double> undef, double %r0, i32 0
   %v1 = insertelement <4 x double> %v0, double %r1, i32 1
   %v2 = insertelement <4 x double> %v1, double %r2, i32 2
@@ -67,8 +67,8 @@ define <4 x double> @foo(double* %p, <4 x i32>* %i, <4 x i32>* %h) nounwind {
 ; LIN32-DAG: {{(mov|and)}}l	8(%esp),
 ; LIN32-DAG: {{(mov|and)}}l	12(%esp),
 define <4 x i64> @old(double* %p, <4 x i32>* %i, <4 x i32>* %h, i64 %f) nounwind {
-  %a = load <4 x i32>* %i
-  %b = load <4 x i32>* %h
+  %a = load <4 x i32>, <4 x i32>* %i
+  %b = load <4 x i32>, <4 x i32>* %h
   %j = and <4 x i32> %a, %b
   %d0 = extractelement <4 x i32> %j, i32 0
   %d1 = extractelement <4 x i32> %j, i32 1
diff --git a/test/CodeGen/X86/gcc_except_table.ll b/test/CodeGen/X86/gcc_except_table.ll
index a732eb1efbd7..b656dc9d68e2 100644
--- a/test/CodeGen/X86/gcc_except_table.ll
+++ b/test/CodeGen/X86/gcc_except_table.ll
@@ -15,7 +15,7 @@ define i32 @main() uwtable optsize ssp {
 
 ; MINGW64: .seh_proc
 ; MINGW64: .seh_handler __gxx_personality_v0
-; MINGW64: .seh_setframe 5, 0
+; MINGW64: .seh_setframe 5, 32
 ; MINGW64: callq _Unwind_Resume
 ; MINGW64: .seh_handlerdata
 ; MINGW64: GCC_except_table0:
@@ -37,6 +37,7 @@ entry:
 
 lpad:
   %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
           catch i8* bitcast (i8** @_ZTIi to i8*)
   br label %eh.resume
 
diff --git a/test/CodeGen/X86/gcc_except_table_functions.ll b/test/CodeGen/X86/gcc_except_table_functions.ll
index 4a8168050e56..7a64a01fa38d 100644
--- a/test/CodeGen/X86/gcc_except_table_functions.ll
+++ b/test/CodeGen/X86/gcc_except_table_functions.ll
@@ -20,6 +20,7 @@ try.cont:
 
 lpad:
   %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
           catch i8* bitcast (void ()* @filt0 to i8*)
           catch i8* bitcast (void ()* @filt1 to i8*)
   %sel = extractvalue { i8*, i32 } %0, 1
diff --git a/test/CodeGen/X86/getelementptr.ll b/test/CodeGen/X86/getelementptr.ll
index f403212700a6..e260e7d7b74a 100644
--- a/test/CodeGen/X86/getelementptr.ll
+++ b/test/CodeGen/X86/getelementptr.ll
@@ -9,35 +9,35 @@
 define i8* @test_trunc65(i8* %ptr) nounwind {
 ; CHECK-LABEL: test_trunc65
 ; CHECK: 3
-  %d = getelementptr i8* %ptr, i65 18446744073709551619 ; 2^64 + 3
+  %d = getelementptr i8, i8* %ptr, i65 18446744073709551619 ; 2^64 + 3
   ret i8* %d
 }
 
 define i8* @test_trunc128(i8* %ptr) nounwind {
 ; CHECK-LABEL: test_trunc128
 ; CHECK: 5
-  %d = getelementptr i8* %ptr, i128 18446744073709551621 ; 2^64 + 5
+  %d = getelementptr i8, i8* %ptr, i128 18446744073709551621 ; 2^64 + 5
   ret i8* %d
 }
 
 define i8* @test_trunc160(i8* %ptr) nounwind {
 ; CHECK-LABEL: test_trunc160
 ; CHECK: 8
-  %d = getelementptr i8* %ptr, i160 18446744073709551624 ; 2^64 + 8
+  %d = getelementptr i8, i8* %ptr, i160 18446744073709551624 ; 2^64 + 8
   ret i8* %d
 }
 
 define i8* @test_trunc256(i8* %ptr) nounwind {
 ; CHECK-LABEL: test_trunc256
 ; CHECK: 13
-  %d = getelementptr i8* %ptr, i256 18446744073709551629 ; 2^64 + 13
+  %d = getelementptr i8, i8* %ptr, i256 18446744073709551629 ; 2^64 + 13
   ret i8* %d
 }
 
 define i8* @test_trunc2048(i8* %ptr) nounwind {
 ; CHECK-LABEL: test_trunc2048
 ; CHECK: 21
-  %d = getelementptr i8* %ptr, i2048 18446744073709551637 ; 2^64 + 21
+  %d = getelementptr i8, i8* %ptr, i2048 18446744073709551637 ; 2^64 + 21
   ret i8* %d
 }
 
@@ -47,34 +47,34 @@ define i8* @test_trunc2048(i8* %ptr) nounwind {
 define i8* @test_sext3(i8* %ptr) nounwind {
 ; CHECK-LABEL: test_sext3
 ; CHECK: -3
-  %d = getelementptr i8* %ptr, i3 -3
+  %d = getelementptr i8, i8* %ptr, i3 -3
   ret i8* %d
 }
 
 define i8* @test_sext5(i8* %ptr) nounwind {
 ; CHECK-LABEL: test_sext5
 ; CHECK: -5
-  %d = getelementptr i8* %ptr, i5 -5
+  %d = getelementptr i8, i8* %ptr, i5 -5
   ret i8* %d
 }
 
 define i8* @test_sext8(i8* %ptr) nounwind {
 ; CHECK-LABEL: test_sext8
 ; CHECK: -8
-  %d = getelementptr i8* %ptr, i8 -8
+  %d = getelementptr i8, i8* %ptr, i8 -8
   ret i8* %d
 }
 
 define i8* @test_sext13(i8* %ptr) nounwind {
 ; CHECK-LABEL: test_sext13
 ; CHECK: -13
-  %d = getelementptr i8* %ptr, i8 -13
+  %d = getelementptr i8, i8* %ptr, i8 -13
   ret i8* %d
 }
 
 define i8* @test_sext16(i8* %ptr) nounwind {
 ; CHECK-LABEL: test_sext16
 ; CHECK: -21
-  %d = getelementptr i8* %ptr, i8 -21
+  %d = getelementptr i8, i8* %ptr, i8 -21
   ret i8* %d
 }
diff --git a/test/CodeGen/X86/ghc-cc.ll b/test/CodeGen/X86/ghc-cc.ll
index 3ada8c8ce98e..16e4db60502d 100644
--- a/test/CodeGen/X86/ghc-cc.ll
+++ b/test/CodeGen/X86/ghc-cc.ll
@@ -32,10 +32,10 @@ entry:
   ; CHECK-NEXT: movl hp, %edi
   ; CHECK-NEXT: movl sp, %ebp
   ; CHECK-NEXT: movl base, %ebx
-  %0 = load i32* @r1
-  %1 = load i32* @hp
-  %2 = load i32* @sp
-  %3 = load i32* @base
+  %0 = load i32, i32* @r1
+  %1 = load i32, i32* @hp
+  %2 = load i32, i32* @sp
+  %3 = load i32, i32* @base
   ; CHECK: jmp bar
   tail call ghccc void @bar( i32 %3, i32 %2, i32 %1, i32 %0 ) nounwind
   ret void
diff --git a/test/CodeGen/X86/ghc-cc64.ll b/test/CodeGen/X86/ghc-cc64.ll
index 7251dd673b30..c4ce8cfdef13 100644
--- a/test/CodeGen/X86/ghc-cc64.ll
+++ b/test/CodeGen/X86/ghc-cc64.ll
@@ -57,22 +57,22 @@ entry:
   ; CHECK-NEXT: movq hp(%rip), %r12
   ; CHECK-NEXT: movq sp(%rip), %rbp
   ; CHECK-NEXT: movq base(%rip), %r13
-  %0 = load double* @d2
-  %1 = load double* @d1
-  %2 = load float* @f4
-  %3 = load float* @f3
-  %4 = load float* @f2
-  %5 = load float* @f1
-  %6 = load i64* @splim
-  %7 = load i64* @r6
-  %8 = load i64* @r5
-  %9 = load i64* @r4
-  %10 = load i64* @r3
-  %11 = load i64* @r2
-  %12 = load i64* @r1
-  %13 = load i64* @hp
-  %14 = load i64* @sp
-  %15 = load i64* @base
+  %0 = load double, double* @d2
+  %1 = load double, double* @d1
+  %2 = load float, float* @f4
+  %3 = load float, float* @f3
+  %4 = load float, float* @f2
+  %5 = load float, float* @f1
+  %6 = load i64, i64* @splim
+  %7 = load i64, i64* @r6
+  %8 = load i64, i64* @r5
+  %9 = load i64, i64* @r4
+  %10 = load i64, i64* @r3
+  %11 = load i64, i64* @r2
+  %12 = load i64, i64* @r1
+  %13 = load i64, i64* @hp
+  %14 = load i64, i64* @sp
+  %15 = load i64, i64* @base
   ; CHECK: jmp bar
   tail call ghccc void @bar( i64 %15, i64 %14, i64 %13, i64 %12, i64 %11,
                              i64 %10, i64 %9, i64 %8, i64 %7, i64 %6,
diff --git a/test/CodeGen/X86/global-sections-comdat.ll b/test/CodeGen/X86/global-sections-comdat.ll
new file mode 100644
index 000000000000..730050dda5f3
--- /dev/null
+++ b/test/CodeGen/X86/global-sections-comdat.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s -mtriple=i386-unknown-linux | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=i386-unknown-linux -data-sections -function-sections | FileCheck %s -check-prefix=LINUX-SECTIONS
+; RUN: llc < %s -mtriple=i386-unknown-linux -data-sections -function-sections -unique-section-names=false | FileCheck %s -check-prefix=LINUX-SECTIONS-SHORT
+
+$F1 = comdat any
+define void @F1(i32 %y) comdat {
+bb0:
+switch i32 %y, label %bb5 [
+    i32 1, label %bb1
+    i32 2, label %bb2
+    i32 3, label %bb3
+    i32 4, label %bb4
+  ]
+bb1:
+  ret void
+bb2:
+  ret void
+bb3:
+  ret void
+bb4:
+  ret void
+bb5:
+  ret void
+}
+
+; LINUX: .section        .text.F1,"axG",@progbits,F1,comdat
+; LINUX: .size   F1,
+; LINUX-NEXT: .cfi_endproc
+; LINUX-NEXT: .section        .rodata.F1,"aG",@progbits,F1,comdat
+
+; LINUX-SECTIONS: .section        .text.F1,"axG",@progbits,F1,comdat
+; LINUX-SECTIONS: .size   F1,
+; LINUX-SECTIONS-NEXT: .cfi_endproc
+; LINUX-SECTIONS-NEXT: .section        .rodata.F1,"aG",@progbits,F1,comdat
+
+; LINUX-SECTIONS-SHORT: .section        .text,"axG",@progbits,F1,comdat
+; LINUX-SECTIONS-SHORT: .size   F1,
+; LINUX-SECTIONS-SHORT-NEXT: .cfi_endproc
+; LINUX-SECTIONS-SHORT-NEXT: .section        .rodata,"aG",@progbits,F1,comdat
+
+$G16 = comdat any
+@G16 = unnamed_addr constant i32 42, comdat
+
+; LINUX: .section	.rodata.cst4.G16,"aGM",@progbits,4,G16,comdat
+; LINUX-SECTIONS: .section	.rodata.cst4.G16,"aGM",@progbits,4,G16,comdat
+; LINUX-SECTIONS-SHORT: .section	.rodata.cst4,"aGM",@progbits,4,G16,comdat
diff --git a/test/CodeGen/X86/global-sections.ll b/test/CodeGen/X86/global-sections.ll
index d6e45ad79ea9..8c61411e53eb 100644
--- a/test/CodeGen/X86/global-sections.ll
+++ b/test/CodeGen/X86/global-sections.ll
@@ -2,8 +2,11 @@
 ; RUN: llc < %s -mtriple=i386-apple-darwin9.7 | FileCheck %s -check-prefix=DARWIN
 ; RUN: llc < %s -mtriple=i386-apple-darwin10 -relocation-model=static | FileCheck %s -check-prefix=DARWIN-STATIC
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s -check-prefix=DARWIN64
-; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -data-sections | FileCheck %s -check-prefix=LINUX-SECTIONS
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -data-sections -function-sections | FileCheck %s -check-prefix=LINUX-SECTIONS
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -function-sections | FileCheck %s -check-prefix=LINUX-FUNC-SECTIONS
+; RUN: llc < %s -mtriple=x86_64-pc-linux -data-sections -function-sections -relocation-model=pic | FileCheck %s -check-prefix=LINUX-SECTIONS-PIC
 ; RUN: llc < %s -mtriple=i686-pc-win32 -data-sections -function-sections | FileCheck %s -check-prefix=WIN32-SECTIONS
+; RUN: llc < %s -mtriple=i686-pc-win32 -function-sections | FileCheck %s -check-prefix=WIN32-FUNC-SECTIONS
 
 define void @F1() {
   ret void
@@ -12,6 +15,91 @@ define void @F1() {
 ; WIN32-SECTIONS: .section        .text,"xr",one_only,_F1
 ; WIN32-SECTIONS: .globl _F1
 
+define void @F2(i32 %y) {
+bb0:
+switch i32 %y, label %bb5 [
+    i32 1, label %bb1
+    i32 2, label %bb2
+    i32 3, label %bb3
+    i32 4, label %bb4
+  ]
+bb1:
+  ret void
+bb2:
+  ret void
+bb3:
+  ret void
+bb4:
+  ret void
+bb5:
+  ret void
+}
+
+; LINUX:     .size   F2,
+; LINUX-NEX: .cfi_endproc
+; LINUX-NEX: .section        .rodata,"a",@progbits
+
+; LINUX-SECTIONS: .section        .text.F2,"ax",@progbits
+; LINUX-SECTIONS: .size   F2,
+; LINUX-SECTIONS-NEXT: .cfi_endproc
+; LINUX-SECTIONS-NEXT: .section        .rodata.F2,"a",@progbits
+
+; LINUX-FUNC-SECTIONS: .section        .text.F2,"ax",@progbits
+; LINUX-FUNC-SECTIONS: .size   F2,
+; LINUX-FUNC-SECTIONS-NEXT: .cfi_endproc
+; LINUX-FUNC-SECTIONS-NEXT: .section        .rodata.F2,"a",@progbits
+
+; WIN32-FUNC-SECTIONS: .section        .text,"xr",one_only,_F2
+; WIN32-FUNC-SECTIONS-NOT: .section
+; WIN32-FUNC-SECTIONS: .section        .rdata,"dr",associative,_F2
+
+
+; LINUX-SECTIONS-PIC: .section        .text.F2,"ax",@progbits
+; LINUX-SECTIONS-PIC: .size   F2,
+; LINUX-SECTIONS-PIC-NEXT: .cfi_endproc
+; LINUX-SECTIONS-PIC-NEXT: .section        .rodata.F2,"a",@progbits
+
+declare void @G()
+
+define void @F3(i32 %y) {
+bb0:
+  invoke void @G()
+          to label %bb2 unwind label %bb1
+bb1:
+  landingpad { i8*, i32 } personality i8* bitcast (void ()* @G to i8*)
+          catch i8* null
+  br label %bb2
+bb2:
+
+switch i32 %y, label %bb7 [
+    i32 1, label %bb3
+    i32 2, label %bb4
+    i32 3, label %bb5
+    i32 4, label %bb6
+  ]
+bb3:
+  ret void
+bb4:
+  ret void
+bb5:
+  ret void
+bb6:
+  ret void
+bb7:
+  ret void
+}
+
+; DARWIN64: _F3:
+; DARWIN64: Lfunc_end
+; DARWIN64-NEXT: .cfi_endproc
+; DARWIN64-NOT: .section
+; DARWIN64: LJTI{{.*}}:
+; DARWIN64-NEXT: .long
+; DARWIN64-NEXT: .long
+; DARWIN64-NEXT: .long
+; DARWIN64-NEXT: .long
+; DARWIN64-NEXT: .section        __TEXT,__gcc_except_tab
+
 ; int G1;
 @G1 = common global i32 0
 
@@ -85,7 +173,6 @@ define void @F1() {
 @"foo bar" = linkonce global i32 42
 
 ; LINUX: .type  "foo bar",@object
-; LINUX: .section ".data.foo bar","aGw",@progbits,"foo bar",comdat
 ; LINUX: .weak  "foo bar"
 ; LINUX: "foo bar":
 
@@ -98,7 +185,6 @@ define void @F1() {
 @G6 = weak_odr unnamed_addr constant [1 x i8] c"\01"
 
 ; LINUX:   .type        G6,@object
-; LINUX:   .section     .rodata.G6,"aG",@progbits,G6,comdat
 ; LINUX:   .weak        G6
 ; LINUX: G6:
 ; LINUX:   .byte        1
@@ -123,7 +209,7 @@ define void @F1() {
 ; LINUX: G7:
 ; LINUX:        .asciz  "abcdefghi"
 
-; LINUX-SECTIONS: .section        .rodata.G7,"aMS",@progbits,1
+; LINUX-SECTIONS: .section        .rodata.str1.1,"aMS",@progbits,1
 ; LINUX-SECTIONS:       .globl G7
 
 ; WIN32-SECTIONS: .section        .rdata,"dr",one_only,_G7
@@ -184,13 +270,13 @@ define void @F1() {
 @G14 = private unnamed_addr constant [4 x i8] c"foo\00", align 1
 
 ; LINUX-SECTIONS:        .type   .LG14,@object           # @G14
-; LINUX-SECTIONS:        .section        .rodata..LG14,"aMS",@progbits,1
+; LINUX-SECTIONS:        .section        .rodata.str1.1,"aMS",@progbits,1
 ; LINUX-SECTIONS: .LG14:
 ; LINUX-SECTIONS:        .asciz  "foo"
 ; LINUX-SECTIONS:        .size   .LG14, 4
 
-; WIN32-SECTIONS:        .section        .rdata,"dr"
-; WIN32-SECTIONS: L_G14:
+; WIN32-SECTIONS:        .section        .rdata,"dr",one_only,_G14
+; WIN32-SECTIONS: _G14:
 ; WIN32-SECTIONS:        .asciz  "foo"
 
 ; cannot be merged on MachO, but can on other formats.
@@ -208,7 +294,7 @@ define void @F1() {
 ; DARWIN64: .section       __TEXT,__const
 ; DARWIN64: _G15:
 
-; LINUX-SECTIONS: .section      .rodata.G15,"aM",@progbits,8
+; LINUX-SECTIONS: .section      .rodata.cst8,"aM",@progbits,8
 ; LINUX-SECTIONS: G15:
 
 ; WIN32-SECTIONS: .section      .rdata,"dr",one_only,_G15
diff --git a/test/CodeGen/X86/gs-fold.ll b/test/CodeGen/X86/gs-fold.ll
index dbec76ba52c4..bbdd0339f366 100644
--- a/test/CodeGen/X86/gs-fold.ll
+++ b/test/CodeGen/X86/gs-fold.ll
@@ -6,9 +6,9 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 define i32 @test() nounwind uwtable {
 entry:
-  %0 = load volatile %struct.thread* addrspace(256)* null
-  %c = getelementptr inbounds %struct.thread* %0, i64 0, i32 2
-  %1 = load i32* %c, align 4
+  %0 = load volatile %struct.thread*, %struct.thread* addrspace(256)* null
+  %c = getelementptr inbounds %struct.thread, %struct.thread* %0, i64 0, i32 2
+  %1 = load i32, i32* %c, align 4
   ret i32 %1
 }
 
diff --git a/test/CodeGen/X86/h-register-addressing-32.ll b/test/CodeGen/X86/h-register-addressing-32.ll
index 68e8c605f678..d0214137b0e4 100644
--- a/test/CodeGen/X86/h-register-addressing-32.ll
+++ b/test/CodeGen/X86/h-register-addressing-32.ll
@@ -5,8 +5,8 @@
 define double @foo8(double* nocapture inreg %p, i32 inreg %x) nounwind readonly {
   %t0 = lshr i32 %x, 8
   %t1 = and i32 %t0, 255
-  %t2 = getelementptr double* %p, i32 %t1
-  %t3 = load double* %t2, align 8
+  %t2 = getelementptr double, double* %p, i32 %t1
+  %t3 = load double, double* %t2, align 8
   ret double %t3
 }
 ; CHECK: foo8:
@@ -15,8 +15,8 @@ define double @foo8(double* nocapture inreg %p, i32 inreg %x) nounwind readonly
 define float @foo4(float* nocapture inreg %p, i32 inreg %x) nounwind readonly {
   %t0 = lshr i32 %x, 8
   %t1 = and i32 %t0, 255
-  %t2 = getelementptr float* %p, i32 %t1
-  %t3 = load float* %t2, align 8
+  %t2 = getelementptr float, float* %p, i32 %t1
+  %t3 = load float, float* %t2, align 8
   ret float %t3
 }
 ; CHECK: foo4:
@@ -25,8 +25,8 @@ define float @foo4(float* nocapture inreg %p, i32 inreg %x) nounwind readonly {
 define i16 @foo2(i16* nocapture inreg %p, i32 inreg %x) nounwind readonly {
   %t0 = lshr i32 %x, 8
   %t1 = and i32 %t0, 255
-  %t2 = getelementptr i16* %p, i32 %t1
-  %t3 = load i16* %t2, align 8
+  %t2 = getelementptr i16, i16* %p, i32 %t1
+  %t3 = load i16, i16* %t2, align 8
   ret i16 %t3
 }
 ; CHECK: foo2:
@@ -35,8 +35,8 @@ define i16 @foo2(i16* nocapture inreg %p, i32 inreg %x) nounwind readonly {
 define i8 @foo1(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
   %t0 = lshr i32 %x, 8
   %t1 = and i32 %t0, 255
-  %t2 = getelementptr i8* %p, i32 %t1
-  %t3 = load i8* %t2, align 8
+  %t2 = getelementptr i8, i8* %p, i32 %t1
+  %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
 ; CHECK: foo1:
@@ -45,8 +45,8 @@ define i8 @foo1(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
 define i8 @bar8(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
   %t0 = lshr i32 %x, 5
   %t1 = and i32 %t0, 2040
-  %t2 = getelementptr i8* %p, i32 %t1
-  %t3 = load i8* %t2, align 8
+  %t2 = getelementptr i8, i8* %p, i32 %t1
+  %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
 ; CHECK: bar8:
@@ -55,8 +55,8 @@ define i8 @bar8(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
 define i8 @bar4(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
   %t0 = lshr i32 %x, 6
   %t1 = and i32 %t0, 1020
-  %t2 = getelementptr i8* %p, i32 %t1
-  %t3 = load i8* %t2, align 8
+  %t2 = getelementptr i8, i8* %p, i32 %t1
+  %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
 ; CHECK: bar4:
@@ -65,8 +65,8 @@ define i8 @bar4(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
 define i8 @bar2(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
   %t0 = lshr i32 %x, 7
   %t1 = and i32 %t0, 510
-  %t2 = getelementptr i8* %p, i32 %t1
-  %t3 = load i8* %t2, align 8
+  %t2 = getelementptr i8, i8* %p, i32 %t1
+  %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
 ; CHECK: bar2:
diff --git a/test/CodeGen/X86/h-register-addressing-64.ll b/test/CodeGen/X86/h-register-addressing-64.ll
index 3f549d26c2fe..b3159f4896a8 100644
--- a/test/CodeGen/X86/h-register-addressing-64.ll
+++ b/test/CodeGen/X86/h-register-addressing-64.ll
@@ -5,8 +5,8 @@
 define double @foo8(double* nocapture inreg %p, i64 inreg %x) nounwind readonly {
   %t0 = lshr i64 %x, 8
   %t1 = and i64 %t0, 255
-  %t2 = getelementptr double* %p, i64 %t1
-  %t3 = load double* %t2, align 8
+  %t2 = getelementptr double, double* %p, i64 %t1
+  %t3 = load double, double* %t2, align 8
   ret double %t3
 }
 ; CHECK: foo8:
@@ -15,8 +15,8 @@ define double @foo8(double* nocapture inreg %p, i64 inreg %x) nounwind readonly
 define float @foo4(float* nocapture inreg %p, i64 inreg %x) nounwind readonly {
   %t0 = lshr i64 %x, 8
   %t1 = and i64 %t0, 255
-  %t2 = getelementptr float* %p, i64 %t1
-  %t3 = load float* %t2, align 8
+  %t2 = getelementptr float, float* %p, i64 %t1
+  %t3 = load float, float* %t2, align 8
   ret float %t3
 }
 ; CHECK: foo4:
@@ -25,8 +25,8 @@ define float @foo4(float* nocapture inreg %p, i64 inreg %x) nounwind readonly {
 define i16 @foo2(i16* nocapture inreg %p, i64 inreg %x) nounwind readonly {
   %t0 = lshr i64 %x, 8
   %t1 = and i64 %t0, 255
-  %t2 = getelementptr i16* %p, i64 %t1
-  %t3 = load i16* %t2, align 8
+  %t2 = getelementptr i16, i16* %p, i64 %t1
+  %t3 = load i16, i16* %t2, align 8
   ret i16 %t3
 }
 ; CHECK: foo2:
@@ -35,8 +35,8 @@ define i16 @foo2(i16* nocapture inreg %p, i64 inreg %x) nounwind readonly {
 define i8 @foo1(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
   %t0 = lshr i64 %x, 8
   %t1 = and i64 %t0, 255
-  %t2 = getelementptr i8* %p, i64 %t1
-  %t3 = load i8* %t2, align 8
+  %t2 = getelementptr i8, i8* %p, i64 %t1
+  %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
 ; CHECK: foo1:
@@ -45,8 +45,8 @@ define i8 @foo1(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
 define i8 @bar8(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
   %t0 = lshr i64 %x, 5
   %t1 = and i64 %t0, 2040
-  %t2 = getelementptr i8* %p, i64 %t1
-  %t3 = load i8* %t2, align 8
+  %t2 = getelementptr i8, i8* %p, i64 %t1
+  %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
 ; CHECK: bar8:
@@ -55,8 +55,8 @@ define i8 @bar8(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
 define i8 @bar4(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
   %t0 = lshr i64 %x, 6
   %t1 = and i64 %t0, 1020
-  %t2 = getelementptr i8* %p, i64 %t1
-  %t3 = load i8* %t2, align 8
+  %t2 = getelementptr i8, i8* %p, i64 %t1
+  %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
 ; CHECK: bar4:
@@ -65,8 +65,8 @@ define i8 @bar4(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
 define i8 @bar2(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
   %t0 = lshr i64 %x, 7
   %t1 = and i64 %t0, 510
-  %t2 = getelementptr i8* %p, i64 %t1
-  %t3 = load i8* %t2, align 8
+  %t2 = getelementptr i8, i8* %p, i64 %t1
+  %t3 = load i8, i8* %t2, align 8
   ret i8 %t3
 }
 ; CHECK: bar2:
diff --git a/test/CodeGen/X86/h-registers-2.ll b/test/CodeGen/X86/h-registers-2.ll
index 91acb7d5bb1c..d244ab48a2cd 100644
--- a/test/CodeGen/X86/h-registers-2.ll
+++ b/test/CodeGen/X86/h-registers-2.ll
@@ -14,7 +14,7 @@ define i32 @foo(i8* %x, i32 %y) nounwind {
 	%t0 = lshr i32 %y, 8		; <i32> [#uses=1]
 	%t1 = and i32 %t0, 255		; <i32> [#uses=2]
   %t2 = shl i32 %t1, 3
-	%t3 = getelementptr i8* %x, i32 %t2		; <i8*> [#uses=1]
+	%t3 = getelementptr i8, i8* %x, i32 %t2		; <i8*> [#uses=1]
 	store i8 77, i8* %t3, align 4
 	ret i32 %t2
 }
diff --git a/test/CodeGen/X86/h-registers-3.ll b/test/CodeGen/X86/h-registers-3.ll
index 8a0b07b31c27..29d0c280c4fb 100644
--- a/test/CodeGen/X86/h-registers-3.ll
+++ b/test/CodeGen/X86/h-registers-3.ll
@@ -3,7 +3,7 @@
 
 define zeroext i8 @foo() nounwind ssp {
 entry:
-  %0 = tail call zeroext i16 (...)* @bar() nounwind
+  %0 = tail call zeroext i16 (...) @bar() nounwind
   %1 = lshr i16 %0, 8
   %2 = trunc i16 %1 to i8
   ret i8 %2
diff --git a/test/CodeGen/X86/haddsub-2.ll b/test/CodeGen/X86/haddsub-2.ll
index ff939a99427e..c6bac5858807 100644
--- a/test/CodeGen/X86/haddsub-2.ll
+++ b/test/CodeGen/X86/haddsub-2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+sse2,+sse3 | FileCheck %s -check-prefix=CHECK -check-prefix=SSE3
 ; RUN: llc < %s -march=x86-64 -mattr=+sse2,+sse3,+ssse3 | FileCheck %s -check-prefix=CHECK -check-prefix=SSSE3
-; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck %s -check-prefix=CHECK -check-prefix=AVX
-; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s -check-prefix=CHECK -check-prefix=AVX2
+; RUN: llc < %s -march=x86-64 -mattr=+avx | FileCheck %s -check-prefix=CHECK -check-prefix=AVX
+; RUN: llc < %s -march=x86-64 -mattr=+avx2 | FileCheck %s -check-prefix=CHECK -check-prefix=AVX2
 
 
 
diff --git a/test/CodeGen/X86/haddsub-undef.ll b/test/CodeGen/X86/haddsub-undef.ll
index 954a9d994e61..dfe5fff72d07 100644
--- a/test/CodeGen/X86/haddsub-undef.ll
+++ b/test/CodeGen/X86/haddsub-undef.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mattr=+ssse3 | FileCheck %s -check-prefix=CHECK -check-prefix=SSE
-; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck %s -check-prefix=CHECK -check-prefix=AVX
-; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s -check-prefix=CHECK -check-prefix=AVX2
+; RUN: llc < %s -march=x86-64 -mattr=ssse3 | FileCheck %s -check-prefix=CHECK -check-prefix=SSE
+; RUN: llc < %s -march=x86-64 -mattr=avx | FileCheck %s -check-prefix=CHECK -check-prefix=AVX
+; RUN: llc < %s -march=x86-64 -mattr=avx2 | FileCheck %s -check-prefix=CHECK -check-prefix=AVX2
 
 ; Verify that we correctly fold horizontal binop even in the presence of UNDEFs.
 
diff --git a/test/CodeGen/X86/haddsub.ll b/test/CodeGen/X86/haddsub.ll
index 9feb5f6ea6e7..6e65c6c739ca 100644
--- a/test/CodeGen/X86/haddsub.ll
+++ b/test/CodeGen/X86/haddsub.ll
@@ -283,3 +283,18 @@ define <4 x double> @vhsubpd1(<4 x double> %x, <4 x double> %y) {
   %r = fsub <4 x double> %a, %b
   ret <4 x double> %r
 }
+
+; CHECK-LABEL: haddps_v2f32
+; CHECK: haddps %xmm{{[0-9]+}}, %xmm0
+; CHECK-NEXT: retq
+define <2 x float> @haddps_v2f32(<4 x float> %v0) {
+  %v0.0 = extractelement <4 x float> %v0, i32 0
+  %v0.1 = extractelement <4 x float> %v0, i32 1
+  %v0.2 = extractelement <4 x float> %v0, i32 2
+  %v0.3 = extractelement <4 x float> %v0, i32 3
+  %op0 = fadd float %v0.0, %v0.1
+  %op1 = fadd float %v0.2, %v0.3
+  %res0 = insertelement <2 x float> undef, float %op0, i32 0
+  %res1 = insertelement <2 x float> %res0, float %op1, i32 1
+  ret <2 x float> %res1
+}
diff --git a/test/CodeGen/X86/half.ll b/test/CodeGen/X86/half.ll
index 1dcf93939b8b..8a726370f19a 100644
--- a/test/CodeGen/X86/half.ll
+++ b/test/CodeGen/X86/half.ll
@@ -1,11 +1,13 @@
-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LIBCALL
-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+f16c | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-F16C
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c -asm-verbose=false \
+; RUN:   | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LIBCALL
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+f16c -asm-verbose=false \
+; RUN:    | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-F16C
 
 define void @test_load_store(half* %in, half* %out) {
 ; CHECK-LABEL: test_load_store:
 ; CHECK: movw (%rdi), [[TMP:%[a-z0-9]+]]
 ; CHECK: movw [[TMP]], (%rsi)
-  %val = load half* %in
+  %val = load half, half* %in
   store half %val, half* %out
   ret void
 }
@@ -13,7 +15,7 @@ define void @test_load_store(half* %in, half* %out) {
 define i16 @test_bitcast_from_half(half* %addr) {
 ; CHECK-LABEL: test_bitcast_from_half:
 ; CHECK: movzwl (%rdi), %eax
-  %val = load half* %addr
+  %val = load half, half* %addr
   %val_int = bitcast half %val to i16
   ret i16 %val_int
 }
@@ -30,8 +32,8 @@ define float @test_extend32(half* %addr) {
 ; CHECK-LABEL: test_extend32:
 
 ; CHECK-LIBCALL: jmp __gnu_h2f_ieee
-; CHECK-FP16: vcvtph2ps
-  %val16 = load half* %addr
+; CHECK-F16C: vcvtph2ps
+  %val16 = load half, half* %addr
   %val32 = fpext half %val16 to float
   ret float %val32
 }
@@ -41,9 +43,9 @@ define double @test_extend64(half* %addr) {
 
 ; CHECK-LIBCALL: callq __gnu_h2f_ieee
 ; CHECK-LIBCALL: cvtss2sd
-; CHECK-FP16: vcvtph2ps
-; CHECK-FP16: vcvtss2sd
-  %val16 = load half* %addr
+; CHECK-F16C: vcvtph2ps
+; CHECK-F16C: vcvtss2sd
+  %val16 = load half, half* %addr
   %val32 = fpext half %val16 to double
   ret double %val32
 }
@@ -52,7 +54,7 @@ define void @test_trunc32(float %in, half* %addr) {
 ; CHECK-LABEL: test_trunc32:
 
 ; CHECK-LIBCALL: callq __gnu_f2h_ieee
-; CHECK-FP16: vcvtps2ph
+; CHECK-F16C: vcvtps2ph
   %val16 = fptrunc float %in to half
   store half %val16, half* %addr
   ret void
@@ -62,8 +64,200 @@ define void @test_trunc64(double %in, half* %addr) {
 ; CHECK-LABEL: test_trunc64:
 
 ; CHECK-LIBCALL: callq __truncdfhf2
-; CHECK-FP16: callq __truncdfhf2
+; CHECK-F16C: callq __truncdfhf2
   %val16 = fptrunc double %in to half
   store half %val16, half* %addr
   ret void
 }
+
+define i64 @test_fptosi_i64(half* %p) #0 {
+; CHECK-LABEL: test_fptosi_i64:
+
+; CHECK-LIBCALL-NEXT: pushq %rax
+; CHECK-LIBCALL-NEXT: movzwl (%rdi), %edi
+; CHECK-LIBCALL-NEXT: callq __gnu_h2f_ieee
+; CHECK-LIBCALL-NEXT: cvttss2si %xmm0, %rax
+; CHECK-LIBCALL-NEXT: popq %rdx
+; CHECK-LIBCALL-NEXT: retq
+
+; CHECK-F16C-NEXT: movswl (%rdi), [[REG0:%[a-z0-9]+]]
+; CHECK-F16C-NEXT: vmovd [[REG0]], [[REG1:%[a-z0-9]+]]
+; CHECK-F16C-NEXT: vcvtph2ps [[REG1]], [[REG2:%[a-z0-9]+]]
+; CHECK-F16C-NEXT: vcvttss2si [[REG2]], %rax
+; CHECK-F16C-NEXT: retq
+  %a = load half, half* %p, align 2
+  %r = fptosi half %a to i64
+  ret i64 %r
+}
+
+define void @test_sitofp_i64(i64 %a, half* %p) #0 {
+; CHECK-LABEL: test_sitofp_i64:
+
+; CHECK-LIBCALL-NEXT: pushq [[ADDR:%[a-z]+]]
+; CHECK-LIBCALL-NEXT: movq %rsi, [[ADDR]]
+; CHECK-LIBCALL-NEXT: cvtsi2ssq %rdi, %xmm0
+; CHECK-LIBCALL-NEXT: callq __gnu_f2h_ieee
+; CHECK-LIBCALL-NEXT: movw %ax, ([[ADDR]])
+; CHECK_LIBCALL-NEXT: popq [[ADDR]]
+; CHECK_LIBCALL-NEXT: retq
+
+; CHECK-F16C-NEXT: vcvtsi2ssq %rdi, [[REG0:%[a-z0-9]+]], [[REG0]]
+; CHECK-F16C-NEXT: vcvtps2ph $0, [[REG0]], [[REG0]]
+; CHECK-F16C-NEXT: vmovd [[REG0]], %eax
+; CHECK-F16C-NEXT: movw %ax, (%rsi)
+; CHECK-F16C-NEXT: retq
+  %r = sitofp i64 %a to half
+  store half %r, half* %p
+  ret void
+}
+
+define i64 @test_fptoui_i64(half* %p) #0 {
+; CHECK-LABEL: test_fptoui_i64:
+
+; FP_TO_UINT is expanded using FP_TO_SINT
+; CHECK-LIBCALL-NEXT: pushq %rax
+; CHECK-LIBCALL-NEXT: movzwl (%rdi), %edi
+; CHECK-LIBCALL-NEXT: callq __gnu_h2f_ieee
+; CHECK-LIBCALL-NEXT: movss {{.[A-Z_0-9]+}}(%rip), [[REG1:%[a-z0-9]+]]
+; CHECK-LIBCALL-NEXT: movaps %xmm0, [[REG2:%[a-z0-9]+]]
+; CHECK-LIBCALL-NEXT: subss [[REG1]], [[REG2]]
+; CHECK-LIBCALL-NEXT: cvttss2si [[REG2]], [[REG3:%[a-z0-9]+]]
+; CHECK-LIBCALL-NEXT: movabsq  $-9223372036854775808, [[REG4:%[a-z0-9]+]]
+; CHECK-LIBCALL-NEXT: xorq [[REG3]], [[REG4]]
+; CHECK-LIBCALL-NEXT: cvttss2si %xmm0, [[REG5:%[a-z0-9]+]]
+; CHECK-LIBCALL-NEXT: ucomiss [[REG1]], %xmm0
+; CHECK-LIBCALL-NEXT: cmovaeq [[REG4]], [[REG5]]
+; CHECK-LIBCALL-NEXT: popq %rdx
+; CHECK-LIBCALL-NEXT: retq
+
+; CHECK-F16C-NEXT: movswl (%rdi), [[REG0:%[a-z0-9]+]]
+; CHECK-F16C-NEXT: vmovd [[REG0]], [[REG1:%[a-z0-9]+]]
+; CHECK-F16C-NEXT: vcvtph2ps [[REG1]], [[REG2:%[a-z0-9]+]]
+; CHECK-F16C-NEXT: vmovss {{.[A-Z_0-9]+}}(%rip), [[REG3:%[a-z0-9]+]]
+; CHECK-F16C-NEXT: vsubss [[REG3]], [[REG2]], [[REG4:%[a-z0-9]+]]
+; CHECK-F16C-NEXT: vcvttss2si [[REG4]], [[REG5:%[a-z0-9]+]]
+; CHECK-F16C-NEXT: movabsq $-9223372036854775808, [[REG6:%[a-z0-9]+]]
+; CHECK-F16C-NEXT: xorq [[REG5]], [[REG6:%[a-z0-9]+]]
+; CHECK-F16C-NEXT: vcvttss2si [[REG2]], [[REG7:%[a-z0-9]+]]
+; CHECK-F16C-NEXT: vucomiss [[REG3]], [[REG2]]
+; CHECK-F16C-NEXT: cmovaeq [[REG6]], %rax
+; CHECK-F16C-NEXT: retq
+  %a = load half, half* %p, align 2
+  %r = fptoui half %a to i64
+  ret i64 %r
+}
+
+define void @test_uitofp_i64(i64 %a, half* %p) #0 {
+; CHECK-LABEL: test_uitofp_i64:
+; CHECK-LIBCALL-NEXT: pushq [[ADDR:%[a-z0-9]+]]
+; CHECK-LIBCALL-NEXT: movq %rsi, [[ADDR]]
+; CHECK-NEXT: movl %edi, [[REG0:%[a-z0-9]+]]
+; CHECK-NEXT: andl $1, [[REG0]]
+; CHECK-NEXT: testq %rdi, %rdi
+; CHECK-NEXT: js [[LABEL1:.LBB[0-9_]+]]
+
+; simple conversion to float if non-negative
+; CHECK-LIBCALL-NEXT: cvtsi2ssq %rdi, [[REG1:%[a-z0-9]+]]
+; CHECK-F16C-NEXT: vcvtsi2ssq %rdi, [[REG1:%[a-z0-9]+]], [[REG1]]
+; CHECK-NEXT: jmp [[LABEL2:.LBB[0-9_]+]]
+
+; convert using shift+or if negative
+; CHECK-NEXT: [[LABEL1]]:
+; CHECK-NEXT: shrq %rdi
+; CHECK-NEXT: orq %rdi, [[REG2:%[a-z0-9]+]]
+; CHECK-LIBCALL-NEXT: cvtsi2ssq [[REG2]], [[REG3:%[a-z0-9]+]]
+; CHECK-LIBCALL-NEXT: addss [[REG3]], [[REG1]]
+; CHECK-F16C-NEXT: vcvtsi2ssq [[REG2]], [[REG3:%[a-z0-9]+]], [[REG3]]
+; CHECK-F16C-NEXT: vaddss [[REG3]], [[REG3]], [[REG1:[%a-z0-9]+]]
+
+; convert float to half
+; CHECK-NEXT: [[LABEL2]]:
+; CHECK-LIBCALL-NEXT: callq __gnu_f2h_ieee
+; CHECK-LIBCALL-NEXT: movw %ax, ([[ADDR]])
+; CHECK-LIBCALL-NEXT: popq [[ADDR]]
+; CHECK-F16C-NEXT: vcvtps2ph $0, [[REG1]], [[REG4:%[a-z0-9]+]]
+; CHECK-F16C-NEXT: vmovd [[REG4]], %eax
+; CHECK-F16C-NEXT: movw %ax, (%rsi)
+; CHECK-NEXT: retq
+
+  %r = uitofp i64 %a to half
+  store half %r, half* %p
+  ret void
+}
+
+define <4 x float> @test_extend32_vec4(<4 x half>* %p) #0 {
+; CHECK-LABEL: test_extend32_vec4:
+
+; CHECK-LIBCALL: callq __gnu_h2f_ieee
+; CHECK-LIBCALL: callq __gnu_h2f_ieee
+; CHECK-LIBCALL: callq __gnu_h2f_ieee
+; CHECK-LIBCALL: callq __gnu_h2f_ieee
+; CHECK-F16C: vcvtph2ps
+; CHECK-F16C: vcvtph2ps
+; CHECK-F16C: vcvtph2ps
+; CHECK-F16C: vcvtph2ps
+  %a = load <4 x half>, <4 x half>* %p, align 8
+  %b = fpext <4 x half> %a to <4 x float>
+  ret <4 x float> %b
+}
+
+define <4 x double> @test_extend64_vec4(<4 x half>* %p) #0 {
+; CHECK-LABEL: test_extend64_vec4
+
+; CHECK-LIBCALL: callq __gnu_h2f_ieee
+; CHECK-LIBCALL-DAG: callq __gnu_h2f_ieee
+; CHECK-LIBCALL-DAG: callq __gnu_h2f_ieee
+; CHECK-LIBCALL-DAG: callq __gnu_h2f_ieee
+; CHECK-LIBCALL-DAG: cvtss2sd
+; CHECK-LIBCALL-DAG: cvtss2sd
+; CHECK-LIBCALL-DAG: cvtss2sd
+; CHECK-LIBCALL: cvtss2sd
+; CHECK-F16C: vcvtph2ps
+; CHECK-F16C-DAG: vcvtph2ps
+; CHECK-F16C-DAG: vcvtph2ps
+; CHECK-F16C-DAG: vcvtph2ps
+; CHECK-F16C-DAG: vcvtss2sd
+; CHECK-F16C-DAG: vcvtss2sd
+; CHECK-F16C-DAG: vcvtss2sd
+; CHECK-F16C: vcvtss2sd
+  %a = load <4 x half>, <4 x half>* %p, align 8
+  %b = fpext <4 x half> %a to <4 x double>
+  ret <4 x double> %b
+}
+
+define void @test_trunc32_vec4(<4 x float> %a, <4 x half>* %p) {
+; CHECK-LABEL: test_trunc32_vec4:
+
+; CHECK-LIBCALL: callq __gnu_f2h_ieee
+; CHECK-LIBCALL: callq __gnu_f2h_ieee
+; CHECK-LIBCALL: callq __gnu_f2h_ieee
+; CHECK-LIBCALL: callq __gnu_f2h_ieee
+; CHECK-F16C: vcvtps2ph
+; CHECK-F16C: vcvtps2ph
+; CHECK-F16C: vcvtps2ph
+; CHECK-F16C: vcvtps2ph
+; CHECK: movw
+; CHECK: movw
+; CHECK: movw
+; CHECK: movw
+  %v = fptrunc <4 x float> %a to <4 x half>
+  store <4 x half> %v, <4 x half>* %p
+  ret void
+}
+
+define void @test_trunc64_vec4(<4 x double> %a, <4 x half>* %p) {
+; CHECK-LABEL: test_trunc64_vec4:
+; CHECK: callq  __truncdfhf2
+; CHECK: callq  __truncdfhf2
+; CHECK: callq  __truncdfhf2
+; CHECK: callq  __truncdfhf2
+; CHECK: movw
+; CHECK: movw
+; CHECK: movw
+; CHECK: movw
+  %v = fptrunc <4 x double> %a to <4 x half>
+  store <4 x half> %v, <4 x half>* %p
+  ret void
+}
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/X86/hidden-vis-2.ll b/test/CodeGen/X86/hidden-vis-2.ll
index 74554d15e2f6..62e143d61c67 100644
--- a/test/CodeGen/X86/hidden-vis-2.ll
+++ b/test/CodeGen/X86/hidden-vis-2.ll
@@ -5,6 +5,6 @@
 
 define i32 @t() nounwind readonly {
 entry:
-	%0 = load i32* @x, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* @x, align 4		; <i32> [#uses=1]
 	ret i32 %0
 }
diff --git a/test/CodeGen/X86/hidden-vis-3.ll b/test/CodeGen/X86/hidden-vis-3.ll
index 4be881e84d68..5d9ef44a4d49 100644
--- a/test/CodeGen/X86/hidden-vis-3.ll
+++ b/test/CodeGen/X86/hidden-vis-3.ll
@@ -12,8 +12,8 @@ entry:
 ; X64: _t:
 ; X64: movl _y(%rip), %eax
 
-	%0 = load i32* @x, align 4		; <i32> [#uses=1]
-	%1 = load i32* @y, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* @x, align 4		; <i32> [#uses=1]
+	%1 = load i32, i32* @y, align 4		; <i32> [#uses=1]
 	%2 = add i32 %1, %0		; <i32> [#uses=1]
 	ret i32 %2
 }
diff --git a/test/CodeGen/X86/hidden-vis-4.ll b/test/CodeGen/X86/hidden-vis-4.ll
index 25a87b905bc1..17d44d0e42f1 100644
--- a/test/CodeGen/X86/hidden-vis-4.ll
+++ b/test/CodeGen/X86/hidden-vis-4.ll
@@ -7,6 +7,6 @@ entry:
 ; CHECK-LABEL: t:
 ; CHECK: movl _x, %eax
 ; CHECK: .comm _x,4
-	%0 = load i32* @x, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* @x, align 4		; <i32> [#uses=1]
 	ret i32 %0
 }
diff --git a/test/CodeGen/X86/hidden-vis-pic.ll b/test/CodeGen/X86/hidden-vis-pic.ll
index 1caab7a6a00e..96adf621752f 100644
--- a/test/CodeGen/X86/hidden-vis-pic.ll
+++ b/test/CodeGen/X86/hidden-vis-pic.ll
@@ -28,7 +28,7 @@ entry:
 
 define hidden void @func() nounwind ssp uwtable {
 entry:
-  %0 = call i32 @puts(i8* getelementptr inbounds ([12 x i8]* @.str, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+  %0 = call i32 @puts(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
   br label %return
 
 return:                                           ; preds = %entry
@@ -45,6 +45,6 @@ entry:
   br label %return
 
 return:                                           ; preds = %entry
-  %retval1 = load i32* %retval                    ; <i32> [#uses=1]
+  %retval1 = load i32, i32* %retval                    ; <i32> [#uses=1]
   ret i32 %retval1
 }
diff --git a/test/CodeGen/X86/hipe-cc.ll b/test/CodeGen/X86/hipe-cc.ll
index b34417ebf69b..e3808e754228 100644
--- a/test/CodeGen/X86/hipe-cc.ll
+++ b/test/CodeGen/X86/hipe-cc.ll
@@ -53,18 +53,18 @@ entry:
   ; CHECK-NEXT: movl  12(%esp), %ebp
   ; CHECK-NEXT: movl   8(%esp), %eax
   ; CHECK-NEXT: movl   4(%esp), %edx
-  %0 = load i32* %hp_var
-  %1 = load i32* %p_var
-  %2 = load i32* %arg0_var
-  %3 = load i32* %arg1_var
-  %4 = load i32* %arg2_var
+  %0 = load i32, i32* %hp_var
+  %1 = load i32, i32* %p_var
+  %2 = load i32, i32* %arg0_var
+  %3 = load i32, i32* %arg1_var
+  %4 = load i32, i32* %arg2_var
   ; CHECK:      jmp bar
   tail call cc 11 void @bar(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4) nounwind
   ret void
 }
 
 define cc 11 void @baz() nounwind {
-  %tmp_clos = load i32* @clos
+  %tmp_clos = load i32, i32* @clos
   %tmp_clos2 = inttoptr i32 %tmp_clos to i32*
   %indirect_call = bitcast i32* %tmp_clos2 to void (i32, i32, i32)*
   ; CHECK:      movl $42, %eax
diff --git a/test/CodeGen/X86/hipe-cc64.ll b/test/CodeGen/X86/hipe-cc64.ll
index 27e1c723a8f7..28d90399d857 100644
--- a/test/CodeGen/X86/hipe-cc64.ll
+++ b/test/CodeGen/X86/hipe-cc64.ll
@@ -62,19 +62,19 @@ entry:
   ; CHECK-NEXT: movq  24(%rsp), %rsi
   ; CHECK-NEXT: movq  16(%rsp), %rdx
   ; CHECK-NEXT: movq  8(%rsp), %rcx
-  %0 = load i64* %hp_var
-  %1 = load i64* %p_var
-  %2 = load i64* %arg0_var
-  %3 = load i64* %arg1_var
-  %4 = load i64* %arg2_var
-  %5 = load i64* %arg3_var
+  %0 = load i64, i64* %hp_var
+  %1 = load i64, i64* %p_var
+  %2 = load i64, i64* %arg0_var
+  %3 = load i64, i64* %arg1_var
+  %4 = load i64, i64* %arg2_var
+  %5 = load i64, i64* %arg3_var
   ; CHECK:      jmp bar
   tail call cc 11 void @bar(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5) nounwind
   ret void
 }
 
 define cc 11 void @baz() nounwind {
-  %tmp_clos = load i64* @clos
+  %tmp_clos = load i64, i64* @clos
   %tmp_clos2 = inttoptr i64 %tmp_clos to i64*
   %indirect_call = bitcast i64* %tmp_clos2 to void (i64, i64, i64)*
   ; CHECK:      movl $42, %esi
diff --git a/test/CodeGen/X86/hoist-common.ll b/test/CodeGen/X86/hoist-common.ll
index 01d1b8c034e3..65f834081077 100644
--- a/test/CodeGen/X86/hoist-common.ll
+++ b/test/CodeGen/X86/hoist-common.ll
@@ -26,7 +26,7 @@ entry:
 
 if.then:
 ; CHECK: callq
-  %call = tail call zeroext i1 (...)* @foo() nounwind
+  %call = tail call zeroext i1 (...) @foo() nounwind
   br label %return
 
 return:
diff --git a/test/CodeGen/X86/hoist-invariant-load.ll b/test/CodeGen/X86/hoist-invariant-load.ll
index c9e52903c79e..6798c2b30c3b 100644
--- a/test/CodeGen/X86/hoist-invariant-load.ll
+++ b/test/CodeGen/X86/hoist-invariant-load.ll
@@ -5,9 +5,9 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-apple-macosx10.7.2"
 
 @"\01L_OBJC_METH_VAR_NAME_" = internal global [4 x i8] c"foo\00", section "__TEXT,__objc_methname,cstring_literals", align 1
-@"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i64 0, i64 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
+@"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i64 0, i64 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
 @"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] [i32 0, i32 16], section "__DATA, __objc_imageinfo, regular, no_dead_strip"
-@llvm.used = appending global [3 x i8*] [i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*)], section "llvm.metadata"
+@llvm.used = appending global [3 x i8*] [i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*)], section "llvm.metadata"
 
 define void @test(i8* %x) uwtable ssp {
 entry:
@@ -15,7 +15,7 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
-  %0 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8, !invariant.load !0
+  %0 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8, !invariant.load !0
   %call = tail call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %x, i8* %0)
   %inc = add i32 %i.01, 1
   %exitcond = icmp eq i32 %inc, 10000
diff --git a/test/CodeGen/X86/huge-stack-offset.ll b/test/CodeGen/X86/huge-stack-offset.ll
new file mode 100644
index 000000000000..eea389b027ba
--- /dev/null
+++ b/test/CodeGen/X86/huge-stack-offset.ll
@@ -0,0 +1,59 @@
+; RUN: llc < %s -mtriple=x86_64-linux-unknown | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc < %s -mtriple=i386-linux-unknown | FileCheck %s --check-prefix=CHECK-32
+
+; Test that a large stack offset uses a single add/sub instruction to
+; adjust the stack pointer.
+
+define void @foo() nounwind {
+; CHECK-64-LABEL: foo:
+; CHECK-64:      movabsq $50000000{{..}}, %rax
+; CHECK-64-NEXT: subq    %rax, %rsp
+; CHECK-64-NOT:  subq    $2147483647, %rsp
+; CHECK-64:      movabsq $50000000{{..}}, [[RAX:%r..]]
+; CHECK-64-NEXT: addq    [[RAX]], %rsp
+
+; CHECK-32-LABEL: foo:
+; CHECK-32:      movl    $50000000{{..}}, %eax
+; CHECK-32-NEXT: subl    %eax, %esp
+; CHECK-32-NOT:  subl    $2147483647, %esp
+; CHECK-32:      movl    $50000000{{..}}, [[EAX:%e..]]
+; CHECK-32-NEXT: addl    [[EAX]], %esp
+  %1 = alloca [5000000000 x i8], align 16
+  %2 = getelementptr inbounds [5000000000 x i8], [5000000000 x i8]* %1, i32 0, i32 0
+  call void @bar(i8* %2)
+  ret void
+}
+
+; Verify that we do not clobber the return value.
+
+define i32 @foo2() nounwind {
+; CHECK-64-LABEL: foo2:
+; CHECK-64:     movl    $10, %eax
+; CHECK-64-NOT: movabsq ${{.*}}, %rax
+
+; CHECK-32-LABEL: foo2:
+; CHECK-32:     movl    $10, %eax
+; CHECK-32-NOT: movl    ${{.*}}, %eax
+  %1 = alloca [5000000000 x i8], align 16
+  %2 = getelementptr inbounds [5000000000 x i8], [5000000000 x i8]* %1, i32 0, i32 0
+  call void @bar(i8* %2)
+  ret i32 10
+}
+
+; Verify that we do not clobber EAX when using inreg attribute
+
+define i32 @foo3(i32 inreg %x) nounwind {
+; CHECK-64-LABEL: foo3:
+; CHECK-64:      movabsq $50000000{{..}}, %rax
+; CHECK-64-NEXT: subq    %rax, %rsp
+
+; CHECK-32-LABEL: foo3:
+; CHECK-32:      subl $2147483647, %esp
+; CHECK-32-NOT:  movl ${{.*}}, %eax
+  %1 = alloca [5000000000 x i8], align 16
+  %2 = getelementptr inbounds [5000000000 x i8], [5000000000 x i8]* %1, i32 0, i32 0
+  call void @bar(i8* %2)
+  ret i32 %x
+}
+
+declare void @bar(i8*)
diff --git a/test/CodeGen/X86/i128-mul.ll b/test/CodeGen/X86/i128-mul.ll
index 8cfda85ce46d..21bca028888a 100644
--- a/test/CodeGen/X86/i128-mul.ll
+++ b/test/CodeGen/X86/i128-mul.ll
@@ -26,14 +26,14 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %carry.013 = phi i64 [ %conv6, %for.body ], [ 0, %entry ]
   %i.012 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i64* %x, i64 %i.012
-  %0 = load i64* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds i64, i64* %x, i64 %i.012
+  %0 = load i64, i64* %arrayidx, align 8
   %conv2 = zext i64 %0 to i128
   %mul = mul i128 %conv2, %conv
   %conv3 = zext i64 %carry.013 to i128
   %add = add i128 %mul, %conv3
   %conv4 = trunc i128 %add to i64
-  %arrayidx5 = getelementptr inbounds i64* %z, i64 %i.012
+  %arrayidx5 = getelementptr inbounds i64, i64* %z, i64 %i.012
   store i64 %conv4, i64* %arrayidx5, align 8
   %shr = lshr i128 %add, 64
   %conv6 = trunc i128 %shr to i64
diff --git a/test/CodeGen/X86/i128-ret.ll b/test/CodeGen/X86/i128-ret.ll
index 264f07ceb4c8..1d76471225e2 100644
--- a/test/CodeGen/X86/i128-ret.ll
+++ b/test/CodeGen/X86/i128-ret.ll
@@ -4,7 +4,7 @@
 ; CHECK: movq 8([[A0]]), %rdx
 
 define i128 @test(i128 *%P) {
-        %A = load i128* %P
+        %A = load i128, i128* %P
         ret i128 %A
 }
 
diff --git a/test/CodeGen/X86/i1narrowfail.ll b/test/CodeGen/X86/i1narrowfail.ll
new file mode 100644
index 000000000000..4f9a75672bfc
--- /dev/null
+++ b/test/CodeGen/X86/i1narrowfail.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
+
+; CHECK-LABEL: @foo
+; CHECK: orb     $16
+define void @foo(i64* %ptr) {
+  %r11 = load i64, i64* %ptr, align 8
+  %r12 = or i64 16, %r11
+  store i64 %r12, i64* %ptr, align 8
+  ret void
+}
diff --git a/test/CodeGen/X86/i256-add.ll b/test/CodeGen/X86/i256-add.ll
index 5a7a7a7fe84a..6164d898ca11 100644
--- a/test/CodeGen/X86/i256-add.ll
+++ b/test/CodeGen/X86/i256-add.ll
@@ -3,15 +3,15 @@
 ; RUN: grep sbbl %t | count 7
 
 define void @add(i256* %p, i256* %q) nounwind {
-  %a = load i256* %p
-  %b = load i256* %q
+  %a = load i256, i256* %p
+  %b = load i256, i256* %q
   %c = add i256 %a, %b
   store i256 %c, i256* %p
   ret void
 }
 define void @sub(i256* %p, i256* %q) nounwind {
-  %a = load i256* %p
-  %b = load i256* %q
+  %a = load i256, i256* %p
+  %b = load i256, i256* %q
   %c = sub i256 %a, %b
   store i256 %c, i256* %p
   ret void
diff --git a/test/CodeGen/X86/i2k.ll b/test/CodeGen/X86/i2k.ll
index 6116c2e71658..83c10a58a3a8 100644
--- a/test/CodeGen/X86/i2k.ll
+++ b/test/CodeGen/X86/i2k.ll
@@ -1,8 +1,8 @@
 ; RUN: llc < %s -march=x86
 
 define void @foo(i2011* %x, i2011* %y, i2011* %p) nounwind {
-  %a = load i2011* %x
-  %b = load i2011* %y
+  %a = load i2011, i2011* %x
+  %b = load i2011, i2011* %y
   %c = add i2011 %a, %b
   store i2011 %c, i2011* %p
   ret void
diff --git a/test/CodeGen/X86/i486-fence-loop.ll b/test/CodeGen/X86/i486-fence-loop.ll
index d8096197b0df..936e54eddafa 100644
--- a/test/CodeGen/X86/i486-fence-loop.ll
+++ b/test/CodeGen/X86/i486-fence-loop.ll
@@ -7,8 +7,7 @@
 define void @gst_atomic_queue_push(i32* %addr) {
 ; CHECK-LABEL: gst_atomic_queue_push:
 ; CHECK: movl (%eax), [[LHS:%e[a-z]+]]
-; CHECK: lock
-; CHECK-NEXT: orl
+; CHECK: lock orl
 ; CHECK: movl (%eax), [[RHS:%e[a-z]+]]
 ; CHECK: cmpl [[LHS]], [[RHS]]
 
@@ -16,9 +15,9 @@ entry:
   br label %while.body
 
 while.body:
-  %0 = load volatile i32* %addr, align 4
+  %0 = load volatile i32, i32* %addr, align 4
   fence seq_cst
-  %1 = load volatile i32* %addr, align 4
+  %1 = load volatile i32, i32* %addr, align 4
   %cmp = icmp sgt i32 %1, %0
   br i1 %cmp, label %while.body, label %if.then
 
diff --git a/test/CodeGen/X86/i64-mem-copy.ll b/test/CodeGen/X86/i64-mem-copy.ll
index bf778968c89a..69ec3fd806b4 100644
--- a/test/CodeGen/X86/i64-mem-copy.ll
+++ b/test/CodeGen/X86/i64-mem-copy.ll
@@ -1,17 +1,76 @@
-; RUN: llc < %s -mtriple=x86_64-linux   | FileCheck %s -check-prefix=X64
-; RUN: llc < %s -mtriple=x86_64-win32   | FileCheck %s -check-prefix=X64
-; X64: movq ({{%rsi|%rdx}}), %r
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefix=X32AVX
 
-; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=X32
-; X32: movsd ({{%ecx|%eax}}), %xmm
+; Use movq or movsd to load / store i64 values if sse2 is available.
+; rdar://6659858
+
+define void @foo(i64* %x, i64* %y) {
+; X64-LABEL: foo:
+; X64:       # BB#0:
+; X64-NEXT:    movq (%rsi), %rax
+; X64-NEXT:    movq %rax, (%rdi)
+; X64-NEXT:    retq
+;
+; X32-LABEL: foo:
+; X32:       # BB#0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; X32-NEXT:    movsd %xmm0, (%eax)
+; X32-NEXT:    retl
+  %tmp1 = load i64, i64* %y, align 8
+  store i64 %tmp1, i64* %x, align 8
+  ret void
+}
 
-; Uses movsd to load / store i64 values if sse2 is available.
+; Verify that a 64-bit chunk extracted from a vector is stored with a movq
+; regardless of whether the system is 64-bit.
 
-; rdar://6659858
+define void @store_i64_from_vector(<8 x i16> %x, <8 x i16> %y, i64* %i) {
+; X64-LABEL: store_i64_from_vector:
+; X64:       # BB#0:
+; X64-NEXT:    paddw %xmm1, %xmm0
+; X64-NEXT:    movq %xmm0, (%rdi)
+; X64-NEXT:    retq
+;
+; X32-LABEL: store_i64_from_vector:
+; X32:       # BB#0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    paddw %xmm1, %xmm0
+; X32-NEXT:    movq %xmm0, (%eax)
+; X32-NEXT:    retl
+  %z = add <8 x i16> %x, %y                          ; force execution domain
+  %bc = bitcast <8 x i16> %z to <2 x i64>
+  %vecext = extractelement <2 x i64> %bc, i32 0
+  store i64 %vecext, i64* %i, align 8
+  ret void
+}
+
+define void @store_i64_from_vector256(<16 x i16> %x, <16 x i16> %y, i64* %i) {
+; X32AVX-LABEL: store_i64_from_vector256:
+; X32AVX:       # BB#0:
+; X32AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32AVX-NEXT:    vpaddw %ymm1, %ymm0, %ymm0
+; X32AVX-NEXT:    vextracti128 $1, %ymm0, %xmm0
+; X32AVX-NEXT:    vmovq %xmm0, (%eax)
+; X32AVX-NEXT:    vzeroupper
+; X32AVX-NEXT:    retl
+  %z = add <16 x i16> %x, %y                          ; force execution domain
+  %bc = bitcast <16 x i16> %z to <4 x i64>
+  %vecext = extractelement <4 x i64> %bc, i32 2
+  store i64 %vecext, i64* %i, align 8
+  ret void
+}
+
+; PR23476
+; Handle extraction from a non-simple / pre-legalization type.
 
-define void @foo(i64* %x, i64* %y) nounwind  {
-entry:
-	%tmp1 = load i64* %y, align 8		; <i64> [#uses=1]
-	store i64 %tmp1, i64* %x, align 8
-	ret void
+define void @PR23476(<5 x i64> %in, i64* %out, i32 %index) {
+; X32-LABEL: PR23476:
+; X32:         movsd {{.*#+}} xmm0 = mem[0],zero
+; X32-NEXT:    movsd %xmm0, (%eax)
+  %ext = extractelement <5 x i64> %in, i32 %index
+  store i64 %ext, i64* %out, align 8
+  ret void
 }
diff --git a/test/CodeGen/X86/illegal-vector-args-return.ll b/test/CodeGen/X86/illegal-vector-args-return.ll
index 62a21f4c5aad..d783d4fa1b49 100644
--- a/test/CodeGen/X86/illegal-vector-args-return.ll
+++ b/test/CodeGen/X86/illegal-vector-args-return.ll
@@ -3,6 +3,8 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=nehalem | grep "addps	%xmm3, %xmm1"
 ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=nehalem | grep "addps	%xmm2, %xmm0"
 
+target triple = "i686-apple-darwin8"
+
 define <4 x double> @foo(<4 x double> %x, <4 x double> %z) {
   %y = fmul <4 x double> %x, %z
   ret <4 x double> %y
diff --git a/test/CodeGen/X86/imul.ll b/test/CodeGen/X86/imul.ll
new file mode 100644
index 000000000000..c64b4e302b92
--- /dev/null
+++ b/test/CodeGen/X86/imul.ll
@@ -0,0 +1,110 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-pc-linux-gnux32 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i686-pc-linux | FileCheck %s --check-prefix=X86
+
+define i32 @mul4_32(i32 %A) {
+; X64-LABEL: mul4_32:
+; X64: leal
+; X86-LABEL: mul4_32:
+; X86: shll
+    %mul = mul i32 %A, 4
+    ret i32 %mul
+}
+
+define i64 @mul4_64(i64 %A) {
+; X64-LABEL: mul4_64:
+; X64: leaq
+; X86-LABEL: mul4_64:
+; X86: shldl
+; X86: shll
+    %mul = mul i64 %A, 4
+    ret i64 %mul
+}
+
+define i32 @mul4096_32(i32 %A) {
+; X64-LABEL: mul4096_32:
+; X64: shll
+; X86-LABEL: mul4096_32:
+; X86: shll
+    %mul = mul i32 %A, 4096
+    ret i32 %mul
+}
+
+define i64 @mul4096_64(i64 %A) {
+; X64-LABEL: mul4096_64:
+; X64: shlq
+; X86-LABEL: mul4096_64:
+; X86: shldl
+; X86: shll
+    %mul = mul i64 %A, 4096
+    ret i64 %mul
+}
+
+define i32 @mulmin4096_32(i32 %A) {
+; X64-LABEL: mulmin4096_32:
+; X64: shll
+; X64-NEXT: negl
+; X86-LABEL: mulmin4096_32:
+; X86: shll
+; X86-NEXT: negl
+    %mul = mul i32 %A, -4096
+    ret i32 %mul
+}
+
+define i64 @mulmin4096_64(i64 %A) {
+; X64-LABEL: mulmin4096_64:
+; X64: shlq
+; X64-NEXT: negq
+; X86-LABEL: mulmin4096_64:
+; X86: shldl
+; X86-NEXT: shll
+; X86-NEXT: xorl
+; X86-NEXT: negl
+; X86-NEXT: sbbl
+    %mul = mul i64 %A, -4096
+    ret i64 %mul
+}
+
+define i32 @mul3_32(i32 %A) {
+; X64-LABEL: mul3_32:
+; X64: leal
+; X86-LABEL: mul3_32:
+; But why?!
+; X86: imull
+    %mul = mul i32 %A, 3
+    ret i32 %mul
+}
+
+define i64 @mul3_64(i64 %A) {
+; X64-LABEL: mul3_64:
+; X64: leaq
+; X86-LABEL: mul3_64:
+; X86: mull
+; X86-NEXT: imull
+    %mul = mul i64 %A, 3
+    ret i64 %mul
+}
+
+define i32 @mul40_32(i32 %A) {
+; X64-LABEL: mul40_32:
+; X64: shll
+; X64-NEXT: leal
+; X86-LABEL: mul40_32:
+; X86: shll
+; X86-NEXT: leal
+    %mul = mul i32 %A, 40
+    ret i32 %mul
+}
+
+define i64 @mul40_64(i64 %A) {
+; X64-LABEL: mul40_64:
+; X64: shlq
+; X64-NEXT: leaq
+; X86-LABEL: mul40_64:
+; X86: leal
+; X86-NEXT: movl
+; X86-NEXT: mull
+; X86-NEXT: leal
+    %mul = mul i64 %A, 40
+    ret i64 %mul
+}
diff --git a/test/CodeGen/X86/imul64-lea.ll b/test/CodeGen/X86/imul64-lea.ll
deleted file mode 100644
index 047c129ddb33..000000000000
--- a/test/CodeGen/X86/imul64-lea.ll
+++ /dev/null
@@ -1,25 +0,0 @@
-; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-pc-linux-gnux32 | FileCheck %s
-
-; Test that 64-bit LEAs are generated for both LP64 and ILP32 in 64-bit mode.
-declare i64 @foo64()
-
-define i64 @test64() {
-  %tmp.0 = tail call i64 @foo64( )
-  %tmp.1 = mul i64 %tmp.0, 9
-; CHECK-NOT: mul
-; CHECK: leaq
-  ret i64 %tmp.1
-}
-
-; Test that 32-bit LEAs are generated for both LP64 and ILP32 in 64-bit mode.
-declare i32 @foo32()
-
-define i32 @test32() {
-  %tmp.0 = tail call i32 @foo32( )
-  %tmp.1 = mul i32 %tmp.0, 9
-; CHECK-NOT: mul
-; CHECK: leal
-  ret i32 %tmp.1
-}
-
diff --git a/test/CodeGen/X86/inalloca-ctor.ll b/test/CodeGen/X86/inalloca-ctor.ll
index b1781d30f913..eba4e72f9330 100644
--- a/test/CodeGen/X86/inalloca-ctor.ll
+++ b/test/CodeGen/X86/inalloca-ctor.ll
@@ -11,7 +11,7 @@ declare void @Foo_ctor(%Foo* %this)
 define void @g() {
 entry:
   %args = alloca inalloca %frame
-  %c = getelementptr %frame* %args, i32 0, i32 2
+  %c = getelementptr %frame, %frame* %args, i32 0, i32 2
 ; CHECK: movl    $20, %eax
 ; CHECK: calll   __chkstk
 ; CHECK: movl %esp,
@@ -20,10 +20,10 @@ entry:
 ; CHECK-NEXT: pushl
 ; CHECK-NEXT: calll _Foo_ctor
 ; CHECK: addl $4, %esp
-  %b = getelementptr %frame* %args, i32 0, i32 1
+  %b = getelementptr %frame, %frame* %args, i32 0, i32 1
   store i32 42, i32* %b
 ; CHECK: movl $42,
-  %a = getelementptr %frame* %args, i32 0, i32 0
+  %a = getelementptr %frame, %frame* %args, i32 0, i32 0
   call void @Foo_ctor(%Foo* %a)
 ; CHECK-NEXT: pushl
 ; CHECK-NEXT: calll _Foo_ctor
diff --git a/test/CodeGen/X86/inalloca-invoke.ll b/test/CodeGen/X86/inalloca-invoke.ll
index b56f24d99628..cf5cbe142ec7 100644
--- a/test/CodeGen/X86/inalloca-invoke.ll
+++ b/test/CodeGen/X86/inalloca-invoke.ll
@@ -4,6 +4,7 @@
 
 %frame.reverse = type { %Iter, %Iter }
 
+declare i32 @pers(...)
 declare void @llvm.stackrestore(i8*)
 declare i8* @llvm.stacksave()
 declare void @begin(%Iter* sret)
@@ -17,12 +18,12 @@ define i32 @main() {
 blah:
   %inalloca.save = call i8* @llvm.stacksave()
   %rev_args = alloca inalloca %frame.reverse, align 4
-  %beg = getelementptr %frame.reverse* %rev_args, i32 0, i32 0
-  %end = getelementptr %frame.reverse* %rev_args, i32 0, i32 1
+  %beg = getelementptr %frame.reverse, %frame.reverse* %rev_args, i32 0, i32 0
+  %end = getelementptr %frame.reverse, %frame.reverse* %rev_args, i32 0, i32 1
 
 ; CHECK:  calll   __chkstk
-; CHECK:  movl    %[[beg:[^,]*]], %esp
-; CHECK:  leal    12(%[[beg]]), %[[end:[^ ]*]]
+; CHECK:  movl %esp, %[[beg:[^ ]*]]
+; CHECK:  leal 12(%[[beg]]), %[[end:[^ ]*]]
 
   call void @begin(%Iter* sret %temp.lvalue)
 ; CHECK:  calll _begin
@@ -31,7 +32,7 @@ blah:
           to label %invoke.cont unwind label %lpad
 
 ;  Uses end as sret param.
-; CHECK:  movl %[[end]], (%esp)
+; CHECK:  pushl %[[end]]
 ; CHECK:  calll _plus
 
 invoke.cont:
@@ -48,7 +49,7 @@ invoke.cont5:                                     ; preds = %invoke.cont
   ret i32 0
 
 lpad:                                             ; preds = %invoke.cont, %entry
-  %lp = landingpad { i8*, i32 } personality i8* null
+  %lp = landingpad { i8*, i32 } personality i32 (...)* @pers
           cleanup
   unreachable
 }
diff --git a/test/CodeGen/X86/inalloca-stdcall.ll b/test/CodeGen/X86/inalloca-stdcall.ll
index 65a0f77c9a6f..e5f6ea70e9cb 100644
--- a/test/CodeGen/X86/inalloca-stdcall.ll
+++ b/test/CodeGen/X86/inalloca-stdcall.ll
@@ -10,13 +10,12 @@ define void @g() {
   %b = alloca inalloca %Foo
 ; CHECK: movl    $8, %eax
 ; CHECK: calll   __chkstk
-; CHECK: movl   %[[REG:[^,]*]], %esp
-  %f1 = getelementptr %Foo* %b, i32 0, i32 0
-  %f2 = getelementptr %Foo* %b, i32 0, i32 1
+  %f1 = getelementptr %Foo, %Foo* %b, i32 0, i32 0
+  %f2 = getelementptr %Foo, %Foo* %b, i32 0, i32 1
   store i32 13, i32* %f1
   store i32 42, i32* %f2
-; CHECK: movl    $13, (%[[REG]])
-; CHECK: movl    $42, 4(%[[REG]])
+; CHECK: movl    $13, (%esp)
+; CHECK: movl    $42, 4(%esp)
   call x86_stdcallcc void @f(%Foo* inalloca %b)
 ; CHECK: calll   _f@8
 ; CHECK-NOT: %esp
diff --git a/test/CodeGen/X86/inalloca.ll b/test/CodeGen/X86/inalloca.ll
index 12643f9d0d50..904366219ab7 100644
--- a/test/CodeGen/X86/inalloca.ll
+++ b/test/CodeGen/X86/inalloca.ll
@@ -10,13 +10,12 @@ entry:
   %b = alloca inalloca %Foo
 ; CHECK: movl    $8, %eax
 ; CHECK: calll   __chkstk
-; CHECK: movl   %[[REG:[^,]*]], %esp
-  %f1 = getelementptr %Foo* %b, i32 0, i32 0
-  %f2 = getelementptr %Foo* %b, i32 0, i32 1
+  %f1 = getelementptr %Foo, %Foo* %b, i32 0, i32 0
+  %f2 = getelementptr %Foo, %Foo* %b, i32 0, i32 1
   store i32 13, i32* %f1
   store i32 42, i32* %f2
-; CHECK: movl    $13, (%[[REG]])
-; CHECK: movl    $42, 4(%[[REG]])
+; CHECK: movl    $13, (%esp)
+; CHECK: movl    $42, 4(%esp)
   call void @f(%Foo* inalloca %b)
 ; CHECK: calll   _f
   ret void
@@ -30,13 +29,12 @@ entry:
   %b = alloca inalloca %Foo
 ; CHECK: movl    $8, %eax
 ; CHECK: calll   __chkstk
-; CHECK: movl   %[[REG:[^,]*]], %esp
-  %f1 = getelementptr %Foo* %b, i32 0, i32 0
-  %f2 = getelementptr %Foo* %b, i32 0, i32 1
+  %f1 = getelementptr %Foo, %Foo* %b, i32 0, i32 0
+  %f2 = getelementptr %Foo, %Foo* %b, i32 0, i32 1
   store i32 13, i32* %f1
   store i32 42, i32* %f2
-; CHECK: movl    $13, (%[[REG]])
-; CHECK: movl    $42, 4(%[[REG]])
+; CHECK: movl    $13, (%esp)
+; CHECK: movl    $42, 4(%esp)
   call void @inreg_with_inalloca(i32 inreg 1, %Foo* inalloca %b)
 ; CHECK: movl    $1, %eax
 ; CHECK: calll   _inreg_with_inalloca
@@ -51,13 +49,12 @@ entry:
   %b = alloca inalloca %Foo
 ; CHECK: movl    $8, %eax
 ; CHECK: calll   __chkstk
-; CHECK: movl   %[[REG:[^,]*]], %esp
-  %f1 = getelementptr %Foo* %b, i32 0, i32 0
-  %f2 = getelementptr %Foo* %b, i32 0, i32 1
+  %f1 = getelementptr %Foo, %Foo* %b, i32 0, i32 0
+  %f2 = getelementptr %Foo, %Foo* %b, i32 0, i32 1
   store i32 13, i32* %f1
   store i32 42, i32* %f2
-; CHECK-DAG: movl    $13, (%[[REG]])
-; CHECK-DAG: movl    $42, 4(%[[REG]])
+; CHECK-DAG: movl    $13, (%esp)
+; CHECK-DAG: movl    $42, 4(%esp)
   call x86_thiscallcc void @thiscall_with_inalloca(i8* null, %Foo* inalloca %b)
 ; CHECK-DAG: xorl    %ecx, %ecx
 ; CHECK: calll   _thiscall_with_inalloca
diff --git a/test/CodeGen/X86/init-priority.ll b/test/CodeGen/X86/init-priority.ll
new file mode 100644
index 000000000000..a0cff237f188
--- /dev/null
+++ b/test/CodeGen/X86/init-priority.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-freebsd9 | FileCheck %s
+
+; Check that our compiler never emits global constructors
+; inside the .init_array section when building for a non-Linux ELF target.
+; Because of this, the test depends on UseInitArray behavior under FreeBSD
+; as found in Generic_ELF::addClangTargetOptions().
+
+; This is to workaround a Visual Studio bug which causes field
+; UseInitArray to be left uninitialized instead of being 
+; zero-initialized (as specified in [dcl.init]p7).
+; This workaround consists in providing a user default constructor
+; that explicitly initializes field UseInitArray.
+
+%class.C = type { i8 }
+%class.D = type { i8 }
+
+@c1 = global %class.C zeroinitializer, align 1
+@d1 = global %class.D zeroinitializer, align 1
+@llvm.global_ctors = appending global [2 x { i32, void ()* }] [{ i32, void ()* } { i32 101, void ()* @_GLOBAL__I_000101 }, { i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }]
+
+define linkonce_odr void @_ZN1CC1Ev(%class.C* nocapture %this) {
+entry:
+  ret void
+}
+
+define linkonce_odr void @_ZN1DC1Ev(%class.D* nocapture %this) {
+entry:
+  ret void
+}
+
+define linkonce_odr void @_ZN1DC2Ev(%class.D* nocapture %this) {
+entry:
+  ret void
+}
+
+define linkonce_odr void @_ZN1CC2Ev(%class.C* nocapture %this) {
+entry:
+  ret void
+}
+
+define internal void @_GLOBAL__I_000101() nounwind readnone {
+entry:
+  ret void
+}
+
+define internal void @_GLOBAL__I_a() nounwind readnone {
+entry:
+  ret void
+}
+
+; CHECK-NOT: .init_array
diff --git a/test/CodeGen/X86/inline-asm-duplicated-constraint.ll b/test/CodeGen/X86/inline-asm-duplicated-constraint.ll
new file mode 100644
index 000000000000..2ef54749739f
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-duplicated-constraint.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86-64 -no-integrated-as -mtriple=x86_64-linux-gnu | FileCheck %s
+
+; CHECK-LABEL: test1:
+; CHECK: movl	(%rdi), %eax
+; CHECK: nop
+; CHECK: movl	%eax, (%rdi)
+; CHECK: ret
+define void @test1(i32* %l) {
+  %load = load i32, i32* %l
+  call void asm "nop", "=*rmrm,0m0m,~{dirflag},~{fpsr},~{flags}"(i32* %l, i32 %load)
+  ret void
+}
diff --git a/test/CodeGen/X86/inline-asm-fpstack.ll b/test/CodeGen/X86/inline-asm-fpstack.ll
index bb3778a28116..972355cffc15 100644
--- a/test/CodeGen/X86/inline-asm-fpstack.ll
+++ b/test/CodeGen/X86/inline-asm-fpstack.ll
@@ -169,11 +169,11 @@ entry:
 ; CHECK: testPR4485
 define void @testPR4485(x86_fp80* %a) {
 entry:
-	%0 = load x86_fp80* %a, align 16
+	%0 = load x86_fp80, x86_fp80* %a, align 16
 	%1 = fmul x86_fp80 %0, 0xK4006B400000000000000
 	%2 = fmul x86_fp80 %1, 0xK4012F424000000000000
 	tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %2)
-	%3 = load x86_fp80* %a, align 16
+	%3 = load x86_fp80, x86_fp80* %a, align 16
 	%4 = fmul x86_fp80 %3, 0xK4006B400000000000000
 	%5 = fmul x86_fp80 %4, 0xK4012F424000000000000
 	tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %5)
@@ -367,7 +367,7 @@ entry:
 ; Function Attrs: ssp
 define void @test_live_st(i32 %a1) {
 entry:
-  %0 = load x86_fp80* undef, align 16
+  %0 = load x86_fp80, x86_fp80* undef, align 16
   %cond = icmp eq i32 %a1, 1
   br i1 %cond, label %sw.bb4.i, label %_Z5tointRKe.exit
 
@@ -380,7 +380,7 @@ _Z5tointRKe.exit:
   %result.0.i = phi x86_fp80 [ %1, %sw.bb4.i ], [ %0, %entry ]
   %conv.i1814 = fptosi x86_fp80 %result.0.i to i32
   %conv626 = sitofp i32 %conv.i1814 to x86_fp80
-  store x86_fp80 %conv626, x86_fp80* getelementptr inbounds (%struct.fpu_t* @fpu, i32 0, i32 1)
+  store x86_fp80 %conv626, x86_fp80* getelementptr inbounds (%struct.fpu_t, %struct.fpu_t* @fpu, i32 0, i32 1)
   br label %return
 
 return:
diff --git a/test/CodeGen/X86/inline-asm-out-regs.ll b/test/CodeGen/X86/inline-asm-out-regs.ll
index 46966f5370d3..8e47f81a5e06 100644
--- a/test/CodeGen/X86/inline-asm-out-regs.ll
+++ b/test/CodeGen/X86/inline-asm-out-regs.ll
@@ -9,7 +9,7 @@ entry:
         br label %bb1.i
 
 bb1.i:          ; preds = %bb6.i.i, %bb1.i, %entry
-        %0 = load i32* null, align 8            ; <i32> [#uses=1]
+        %0 = load i32, i32* null, align 8            ; <i32> [#uses=1]
         %1 = icmp ugt i32 %0, 1048575           ; <i1> [#uses=1]
         br i1 %1, label %bb2.i, label %bb1.i
 
@@ -19,7 +19,7 @@ bb2.i:          ; preds = %bb1.i
         ; <i32> [#uses=1]
         %2 = lshr i32 %asmresult2.i.i, 8                ; <i32> [#uses=1]
         %3 = trunc i32 %2 to i8         ; <i8> [#uses=1]
-        %4 = load i32* @pcibios_last_bus, align 4               ; <i32> [#uses=1]
+        %4 = load i32, i32* @pcibios_last_bus, align 4               ; <i32> [#uses=1]
         %5 = icmp slt i32 %4, 0         ; <i1> [#uses=1]
         br i1 %5, label %bb5.i.i, label %bb6.i.i
 
diff --git a/test/CodeGen/X86/inline-asm-ptr-cast.ll b/test/CodeGen/X86/inline-asm-ptr-cast.ll
index 50e302101814..21353468b1fc 100644
--- a/test/CodeGen/X86/inline-asm-ptr-cast.ll
+++ b/test/CodeGen/X86/inline-asm-ptr-cast.ll
@@ -16,12 +16,12 @@ entry:
   store i64 1, i64* %flags, align 8
   store i64 -1, i64* %newflags, align 8
   %0 = bitcast i32* %dst to i8*
-  %tmp = load i64* %flags, align 8
+  %tmp = load i64, i64* %flags, align 8
   %and = and i64 %tmp, 1
   %1 = bitcast i32* %src to i8*
-  %tmp1 = load i8* %1
+  %tmp1 = load i8, i8* %1
   %2 = bitcast i32* %dst to i8*
-  %tmp2 = load i8* %2
+  %tmp2 = load i8, i8* %2
   call void asm "pushfq \0Aandq $2, (%rsp) \0Aorq  $3, (%rsp) \0Apopfq \0Aaddb $4, $1 \0Apushfq \0Apopq $0 \0A", "=*&rm,=*&rm,i,r,r,1,~{cc},~{dirflag},~{fpsr},~{flags}"(i64* %newflags, i8* %0, i64 -2, i64 %and, i8 %tmp1, i8 %tmp2) nounwind
   ret void
 }
diff --git a/test/CodeGen/X86/inline-asm-stack-realign.ll b/test/CodeGen/X86/inline-asm-stack-realign.ll
index f2ac0f451bb0..cfbe260a33a0 100644
--- a/test/CodeGen/X86/inline-asm-stack-realign.ll
+++ b/test/CodeGen/X86/inline-asm-stack-realign.ll
@@ -11,6 +11,6 @@ entry:
   %r = alloca i32, align 16
   store i32 -1, i32* %r, align 16
   call void asm sideeffect inteldialect "push esi\0A\09xor esi, esi\0A\09mov dword ptr $0, esi\0A\09pop esi", "=*m,~{flags},~{esi},~{esp},~{dirflag},~{fpsr},~{flags}"(i32* %r)
-  %0 = load i32* %r, align 16
+  %0 = load i32, i32* %r, align 16
   ret i32 %0
 }
diff --git a/test/CodeGen/X86/inline-asm-stack-realign2.ll b/test/CodeGen/X86/inline-asm-stack-realign2.ll
index 0e4e7e1a6776..3dfae113cf63 100644
--- a/test/CodeGen/X86/inline-asm-stack-realign2.ll
+++ b/test/CodeGen/X86/inline-asm-stack-realign2.ll
@@ -11,6 +11,6 @@ entry:
   %r = alloca i32, align 16
   store i32 -1, i32* %r, align 16
   call void asm sideeffect "push %esi\0A\09xor %esi, %esi\0A\09mov %esi, $0\0A\09pop %esi", "=*m,~{flags},~{esi},~{esp},~{dirflag},~{fpsr},~{flags}"(i32* %r)
-  %0 = load i32* %r, align 16
+  %0 = load i32, i32* %r, align 16
   ret i32 %0
 }
diff --git a/test/CodeGen/X86/inline-asm-stack-realign3.ll b/test/CodeGen/X86/inline-asm-stack-realign3.ll
index 3baaaaa7d93d..be0c6f51112d 100644
--- a/test/CodeGen/X86/inline-asm-stack-realign3.ll
+++ b/test/CodeGen/X86/inline-asm-stack-realign3.ll
@@ -15,7 +15,7 @@ doit:
   br label %skip
 
 skip:
-  %0 = load i32* %r, align 128
+  %0 = load i32, i32* %r, align 128
   ret i32 %0
 }
 
diff --git a/test/CodeGen/X86/inline-asm-tied.ll b/test/CodeGen/X86/inline-asm-tied.ll
index fb5896b0ad6d..9ceb0e8b4b7d 100644
--- a/test/CodeGen/X86/inline-asm-tied.ll
+++ b/test/CodeGen/X86/inline-asm-tied.ll
@@ -11,12 +11,12 @@ entry:
 	%retval = alloca i64		; <i64*> [#uses=2]
 	%_data.addr = alloca i64		; <i64*> [#uses=4]
 	store i64 %_data, i64* %_data.addr
-	%tmp = load i64* %_data.addr		; <i64> [#uses=1]
+	%tmp = load i64, i64* %_data.addr		; <i64> [#uses=1]
 	%0 = call i64 asm "bswap   %eax\0A\09bswap   %edx\0A\09xchgl   %eax, %edx", "=A,0,~{dirflag},~{fpsr},~{flags}"(i64 %tmp) nounwind		; <i64> [#uses=1]
 	store i64 %0, i64* %_data.addr
-	%tmp1 = load i64* %_data.addr		; <i64> [#uses=1]
+	%tmp1 = load i64, i64* %_data.addr		; <i64> [#uses=1]
 	store i64 %tmp1, i64* %retval
-	%1 = load i64* %retval		; <i64> [#uses=1]
+	%1 = load i64, i64* %retval		; <i64> [#uses=1]
 	ret i64 %1
 }
 
diff --git a/test/CodeGen/X86/ins_split_regalloc.ll b/test/CodeGen/X86/ins_split_regalloc.ll
index f5c5254fcec3..f04d088ce687 100644
--- a/test/CodeGen/X86/ins_split_regalloc.ll
+++ b/test/CodeGen/X86/ins_split_regalloc.ll
@@ -25,7 +25,7 @@ target datalayout = "e-i64:64-f80:128-s:64-n8:16:32:64-S128"
 ; CHECK: jmpq *[[F_ADDR_TC]]
 define void @test(i32 %a, i32 %b, i32 %c) {
 entry:
-  %fct_f = load void (i32)** @f, align 8
+  %fct_f = load void (i32)*, void (i32)** @f, align 8
   tail call void %fct_f(i32 %a)
   tail call void %fct_f(i32 %b)
   tail call void %fct_f(i32 %c)
diff --git a/test/CodeGen/X86/ins_subreg_coalesce-1.ll b/test/CodeGen/X86/ins_subreg_coalesce-1.ll
index a74e3f20c41a..4a5d8dfaf688 100644
--- a/test/CodeGen/X86/ins_subreg_coalesce-1.ll
+++ b/test/CodeGen/X86/ins_subreg_coalesce-1.ll
@@ -18,7 +18,7 @@ bb22:		; preds = %bb4
 bb4.i:		; preds = %bb22
 	ret i32 0
 walkExprTree.exit:		; preds = %bb22
-	%tmp83 = load i16* null, align 4		; <i16> [#uses=1]
+	%tmp83 = load i16, i16* null, align 4		; <i16> [#uses=1]
 	%tmp84 = or i16 %tmp83, 2		; <i16> [#uses=2]
 	store i16 %tmp84, i16* null, align 4
 	%tmp98993 = zext i16 %tmp84 to i32		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/ins_subreg_coalesce-3.ll b/test/CodeGen/X86/ins_subreg_coalesce-3.ll
index 63881e0ccb57..71890bc23b61 100644
--- a/test/CodeGen/X86/ins_subreg_coalesce-3.ll
+++ b/test/CodeGen/X86/ins_subreg_coalesce-3.ll
@@ -35,7 +35,7 @@ bb428:		; preds = %bb366, %bb304
 bb433:		; preds = %bb428
 	ret void
 bb650:		; preds = %bb650, %bb428
-	%tmp658 = load i8* null, align 8		; <i8> [#uses=1]
+	%tmp658 = load i8, i8* null, align 8		; <i8> [#uses=1]
 	%tmp659 = icmp eq i8 %tmp658, 0		; <i1> [#uses=1]
 	br i1 %tmp659, label %bb650, label %bb662
 bb662:		; preds = %bb650
@@ -43,7 +43,7 @@ bb662:		; preds = %bb650
 bb688:		; preds = %bb662
 	ret void
 bb761:		; preds = %bb662
-	%tmp487248736542 = load i32* null, align 4		; <i32> [#uses=2]
+	%tmp487248736542 = load i32, i32* null, align 4		; <i32> [#uses=2]
 	%tmp487648776541 = and i32 %tmp487248736542, 57344		; <i32> [#uses=1]
 	%tmp4881 = icmp eq i32 %tmp487648776541, 8192		; <i1> [#uses=1]
 	br i1 %tmp4881, label %bb4884, label %bb4897
@@ -54,10 +54,10 @@ bb4884:		; preds = %bb761
 bb4897:		; preds = %bb4884, %bb761
 	ret void
 bb4932:		; preds = %bb4884
-	%tmp4933 = load i32* null, align 4		; <i32> [#uses=1]
+	%tmp4933 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	br i1 %foo, label %bb5054, label %bb4940
 bb4940:		; preds = %bb4932
-	%tmp4943 = load i32* null, align 4		; <i32> [#uses=2]
+	%tmp4943 = load i32, i32* null, align 4		; <i32> [#uses=2]
 	switch i32 %tmp4933, label %bb5054 [
 		 i32 159, label %bb4970
 		 i32 160, label %bb5002
@@ -66,11 +66,11 @@ bb4970:		; preds = %bb4940
 	%tmp49746536 = trunc i32 %tmp4943 to i16		; <i16> [#uses=1]
 	%tmp49764977 = and i16 %tmp49746536, 4095		; <i16> [#uses=1]
 	%mask498049814982 = zext i16 %tmp49764977 to i64		; <i64> [#uses=1]
-	%tmp4984 = getelementptr %struct.FONT_INFO* null, i64 %mask498049814982, i32 5		; <%struct.rec**> [#uses=1]
-	%tmp4985 = load %struct.rec** %tmp4984, align 8		; <%struct.rec*> [#uses=1]
-	%tmp4988 = getelementptr %struct.rec* %tmp4985, i64 0, i32 0, i32 3		; <%struct.THIRD_UNION*> [#uses=1]
+	%tmp4984 = getelementptr %struct.FONT_INFO, %struct.FONT_INFO* null, i64 %mask498049814982, i32 5		; <%struct.rec**> [#uses=1]
+	%tmp4985 = load %struct.rec*, %struct.rec** %tmp4984, align 8		; <%struct.rec*> [#uses=1]
+	%tmp4988 = getelementptr %struct.rec, %struct.rec* %tmp4985, i64 0, i32 0, i32 3		; <%struct.THIRD_UNION*> [#uses=1]
 	%tmp4991 = bitcast %struct.THIRD_UNION* %tmp4988 to i32*		; <i32*> [#uses=1]
-	%tmp4992 = load i32* %tmp4991, align 8		; <i32> [#uses=1]
+	%tmp4992 = load i32, i32* %tmp4991, align 8		; <i32> [#uses=1]
 	%tmp49924993 = trunc i32 %tmp4992 to i16		; <i16> [#uses=1]
 	%tmp4996 = add i16 %tmp49924993, 0		; <i16> [#uses=1]
 	br label %bb5054
@@ -78,11 +78,11 @@ bb5002:		; preds = %bb4940
 	%tmp50066537 = trunc i32 %tmp4943 to i16		; <i16> [#uses=1]
 	%tmp50085009 = and i16 %tmp50066537, 4095		; <i16> [#uses=1]
 	%mask501250135014 = zext i16 %tmp50085009 to i64		; <i64> [#uses=1]
-	%tmp5016 = getelementptr %struct.FONT_INFO* null, i64 %mask501250135014, i32 5		; <%struct.rec**> [#uses=1]
-	%tmp5017 = load %struct.rec** %tmp5016, align 8		; <%struct.rec*> [#uses=1]
-	%tmp5020 = getelementptr %struct.rec* %tmp5017, i64 0, i32 0, i32 3		; <%struct.THIRD_UNION*> [#uses=1]
+	%tmp5016 = getelementptr %struct.FONT_INFO, %struct.FONT_INFO* null, i64 %mask501250135014, i32 5		; <%struct.rec**> [#uses=1]
+	%tmp5017 = load %struct.rec*, %struct.rec** %tmp5016, align 8		; <%struct.rec*> [#uses=1]
+	%tmp5020 = getelementptr %struct.rec, %struct.rec* %tmp5017, i64 0, i32 0, i32 3		; <%struct.THIRD_UNION*> [#uses=1]
 	%tmp5023 = bitcast %struct.THIRD_UNION* %tmp5020 to i32*		; <i32*> [#uses=1]
-	%tmp5024 = load i32* %tmp5023, align 8		; <i32> [#uses=1]
+	%tmp5024 = load i32, i32* %tmp5023, align 8		; <i32> [#uses=1]
 	%tmp50245025 = trunc i32 %tmp5024 to i16		; <i16> [#uses=1]
 	%tmp5028 = sub i16 %tmp50245025, 0		; <i16> [#uses=1]
 	br label %bb5054
diff --git a/test/CodeGen/X86/insert-positions.ll b/test/CodeGen/X86/insert-positions.ll
index 1a695f35e3b0..aa68579d22e0 100644
--- a/test/CodeGen/X86/insert-positions.ll
+++ b/test/CodeGen/X86/insert-positions.ll
@@ -41,7 +41,7 @@ for.end.i.i.i:                                    ; preds = %land.rhs.i.i.i, %fo
   %idx.ext.i.i.i = sext i32 %i.0.i.i.i to i64     ; <i64> [#uses=1]
   %sub.ptr72.sum.i.i.i = xor i64 %idx.ext.i.i.i, -1 ; <i64> [#uses=1]
   %pos.addr.1.sum155.i.i.i = add i64 %tmp154.i.i.i, %sub.ptr72.sum.i.i.i ; <i64> [#uses=1]
-  %arrayidx76.i.i.i = getelementptr inbounds i8* undef, i64 %pos.addr.1.sum155.i.i.i ; <i8*> [#uses=0]
+  %arrayidx76.i.i.i = getelementptr inbounds i8, i8* undef, i64 %pos.addr.1.sum155.i.i.i ; <i8*> [#uses=0]
   br label %while.cond.backedge.i.i.i
 }
 
diff --git a/test/CodeGen/X86/insertps-O0-bug.ll b/test/CodeGen/X86/insertps-O0-bug.ll
new file mode 100644
index 000000000000..73748ee7e52a
--- /dev/null
+++ b/test/CodeGen/X86/insertps-O0-bug.ll
@@ -0,0 +1,52 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 -O0 < %s | FileCheck %s
+
+; Check that at -O0, the backend doesn't attempt to canonicalize a vector load
+; used by an INSERTPS into a scalar load plus scalar_to_vector.
+;
+; In order to fold a load into the memory operand of an INSERTPSrm, the backend
+; tries to canonicalize a vector load in input to an INSERTPS node into a
+; scalar load plus scalar_to_vector. This would allow ISel to match the
+; INSERTPSrm variant rather than a load plus INSERTPSrr.
+;
+; However, ISel can only select an INSERTPSrm if folding a load into the operand
+; of an insertps is considered to be profitable.
+;
+; In the example below:
+;
+; __m128 test(__m128 a, __m128 *b) {
+;   __m128 c = _mm_insert_ps(a, *b, 1 << 6);
+;   return c;
+; }
+;
+; At -O0, the backend would attempt to canonicalize the load to 'b' into
+; a scalar load in the hope of matching an INSERTPSrm.
+; However, ISel would fail to recognize an INSERTPSrm since load folding is
+; always considered unprofitable at -O0. This would leave the insertps mask
+; in an invalid state.
+;
+; The problem with the canonicalization rule performed by the backend is that
+; it assumes ISel to always be able to match an INSERTPSrm. This assumption is
+; not always correct at -O0. In this example, FastISel fails to lower the
+; arguments needed by the entry block. This is enough to enable the DAGCombiner
+; and eventually trigger the canonicalization on the INSERTPS node.
+;
+; This test checks that the vector load in input to the insertps is not
+; canonicalized into a scalar load plus scalar_to_vector (a movss).
+
+define <4 x float> @test(<4 x float> %a, <4 x float>* %b) {
+; CHECK-LABEL: test:
+; CHECK: movaps (%rdi), [[REG:%[a-z0-9]+]]
+; CHECK-NOT: movss
+; CHECK: insertps $64, [[REG]],
+; CHECK: ret
+entry:
+  %0 = load <4 x float>, <4 x float>* %b, align 16
+  %1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %0, i32 64)
+  %2 = alloca <4 x float>, align 16
+  store <4 x float> %1, <4 x float>* %2, align 16
+  %3 = load <4 x float>, <4 x float>* %2, align 16
+  ret <4 x float> %3
+}
+
+
+declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32)
diff --git a/test/CodeGen/X86/invalid-shift-immediate.ll b/test/CodeGen/X86/invalid-shift-immediate.ll
index 77a9f7eda783..1fb80c7dba7f 100644
--- a/test/CodeGen/X86/invalid-shift-immediate.ll
+++ b/test/CodeGen/X86/invalid-shift-immediate.ll
@@ -9,7 +9,7 @@ entry:
 	%x_addr = alloca i32		; <i32*> [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store i32 %x, i32* %x_addr
-	%tmp = load i32* %x_addr, align 4		; <i32> [#uses=1]
+	%tmp = load i32, i32* %x_addr, align 4		; <i32> [#uses=1]
 	%tmp1 = ashr i32 %tmp, -2		; <i32> [#uses=1]
 	%tmp2 = and i32 %tmp1, 1		; <i32> [#uses=1]
 	%tmp23 = trunc i32 %tmp2 to i8		; <i8> [#uses=1]
@@ -17,7 +17,7 @@ entry:
 	br i1 %toBool, label %bb, label %bb5
 
 bb:		; preds = %entry
-	%tmp4 = call i32 (...)* @bar( ) nounwind 		; <i32> [#uses=0]
+	%tmp4 = call i32 (...) @bar( ) nounwind 		; <i32> [#uses=0]
 	br label %bb5
 
 bb5:		; preds = %bb, %entry
diff --git a/test/CodeGen/X86/isel-optnone.ll b/test/CodeGen/X86/isel-optnone.ll
index d2f062832e0c..831ad3837d96 100644
--- a/test/CodeGen/X86/isel-optnone.ll
+++ b/test/CodeGen/X86/isel-optnone.ll
@@ -2,14 +2,14 @@
 
 define i32* @fooOptnone(i32* %p, i32* %q, i32** %z) #0 {
 entry:
-  %r = load i32* %p
-  %s = load i32* %q
-  %y = load i32** %z
+  %r = load i32, i32* %p
+  %s = load i32, i32* %q
+  %y = load i32*, i32** %z
 
   %t0 = add i32 %r, %s
   %t1 = add i32 %t0, 1
-  %t2 = getelementptr i32* %y, i32 1
-  %t3 = getelementptr i32* %t2, i32 %t1
+  %t2 = getelementptr i32, i32* %y, i32 1
+  %t3 = getelementptr i32, i32* %t2, i32 %t1
 
   ret i32* %t3
 
@@ -21,14 +21,14 @@ entry:
 
 define i32* @fooNormal(i32* %p, i32* %q, i32** %z) #1 {
 entry:
-  %r = load i32* %p
-  %s = load i32* %q
-  %y = load i32** %z
+  %r = load i32, i32* %p
+  %s = load i32, i32* %q
+  %y = load i32*, i32** %z
 
   %t0 = add i32 %r, %s
   %t1 = add i32 %t0, 1
-  %t2 = getelementptr i32* %y, i32 1
-  %t3 = getelementptr i32* %t2, i32 %t1
+  %t2 = getelementptr i32, i32* %y, i32 1
+  %t3 = getelementptr i32, i32* %t2, i32 %t1
 
   ret i32* %t3
 
diff --git a/test/CodeGen/X86/isel-sink.ll b/test/CodeGen/X86/isel-sink.ll
index e4af9b67f95e..27abe051a9b3 100644
--- a/test/CodeGen/X86/isel-sink.ll
+++ b/test/CodeGen/X86/isel-sink.ll
@@ -11,13 +11,13 @@ define i32 @test(i32* %X, i32 %B) {
 ; CHECK: ret
 
 	; This gep should be sunk out of this block into the load/store users.
-	%P = getelementptr i32* %X, i32 %B
+	%P = getelementptr i32, i32* %X, i32 %B
 	%G = icmp ult i32 %B, 1234
 	br i1 %G, label %T, label %F
 T:
 	store i32 4, i32* %P
 	ret i32 141
 F:
-	%V = load i32* %P
+	%V = load i32, i32* %P
 	ret i32 %V
 }
diff --git a/test/CodeGen/X86/isel-sink2.ll b/test/CodeGen/X86/isel-sink2.ll
index b162666362aa..65f1994b9fe1 100644
--- a/test/CodeGen/X86/isel-sink2.ll
+++ b/test/CodeGen/X86/isel-sink2.ll
@@ -3,15 +3,15 @@
 ; RUN: not grep leal %t
 
 define i8 @test(i32 *%P) nounwind {
-  %Q = getelementptr i32* %P, i32 1
+  %Q = getelementptr i32, i32* %P, i32 1
   %R = bitcast i32* %Q to i8*
-  %S = load i8* %R
+  %S = load i8, i8* %R
   %T = icmp eq i8 %S, 0
   br i1 %T, label %TB, label %F
 TB:
   ret i8 4
 F:
-  %U = getelementptr i8* %R, i32 3
-  %V = load i8* %U
+  %U = getelementptr i8, i8* %R, i32 3
+  %V = load i8, i8* %U
   ret i8 %V
 }
diff --git a/test/CodeGen/X86/isel-sink3.ll b/test/CodeGen/X86/isel-sink3.ll
index 7012ccefaadb..fa633dc25aef 100644
--- a/test/CodeGen/X86/isel-sink3.ll
+++ b/test/CodeGen/X86/isel-sink3.ll
@@ -11,8 +11,8 @@ target triple = "i386-apple-darwin7"
 
 define i32 @bar(i32** %P) nounwind {
 entry:
-	%0 = load i32** %P, align 4		; <i32*> [#uses=2]
-	%1 = getelementptr i32* %0, i32 1		; <i32*> [#uses=1]
+	%0 = load i32*, i32** %P, align 4		; <i32*> [#uses=2]
+	%1 = getelementptr i32, i32* %0, i32 1		; <i32*> [#uses=1]
 	%2 = icmp ugt i32* %1, inttoptr (i64 1233 to i32*)		; <i1> [#uses=1]
 	br i1 %2, label %bb1, label %bb
 
@@ -21,7 +21,7 @@ bb:		; preds = %entry
 	br label %bb1
 
 bb1:		; preds = %entry, %bb
-	%3 = getelementptr i32* %1, i32 1		; <i32*> [#uses=1]
-	%4 = load i32* %3, align 4		; <i32> [#uses=1]
+	%3 = getelementptr i32, i32* %1, i32 1		; <i32*> [#uses=1]
+	%4 = load i32, i32* %3, align 4		; <i32> [#uses=1]
 	ret i32 %4
 }
diff --git a/test/CodeGen/X86/isint.ll b/test/CodeGen/X86/isint.ll
index 38d05c662bd5..ea38d9e4ec29 100644
--- a/test/CodeGen/X86/isint.ll
+++ b/test/CodeGen/X86/isint.ll
@@ -1,8 +1,8 @@
-; RUN: llc < %s -mtriple=x86_64-pc-unknown -mattr=+sse2 -mcpu=penryn | FileCheck %s
-; RUN: llc < %s -mtriple=i686-pc-unknown -mattr=+sse2 -mcpu=penryn | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-pc-unknown -mattr=+sse2 | FileCheck %s
+; RUN: llc < %s -mtriple=i686-pc-unknown -mattr=+sse2 | FileCheck %s
 
 ; PR19059
-; RUN: llc < %s -mtriple=i686-pc-unknown -mattr=+sse2 -mcpu=penryn | FileCheck -check-prefix=CHECK32 %s
+; RUN: llc < %s -mtriple=i686-pc-unknown -mattr=+sse2 | FileCheck -check-prefix=CHECK32 %s
 
 define i32 @isint_return(double %d) nounwind {
 ; CHECK-LABEL: isint_return:
diff --git a/test/CodeGen/X86/jump_sign.ll b/test/CodeGen/X86/jump_sign.ll
index dfa8aed46463..ca3e8bf71eba 100644
--- a/test/CodeGen/X86/jump_sign.ll
+++ b/test/CodeGen/X86/jump_sign.ll
@@ -9,11 +9,11 @@ entry:
 	br i1 %tmp, label %cond_true, label %cond_next
 
 cond_true:		; preds = %entry
-	%tmp2 = tail call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp2 = tail call i32 (...) @bar( )		; <i32> [#uses=0]
 	br label %cond_next
 
 cond_next:		; preds = %cond_true, %entry
-	%tmp3 = tail call i32 (...)* @baz( )		; <i32> [#uses=0]
+	%tmp3 = tail call i32 (...) @baz( )		; <i32> [#uses=0]
 	ret i32 undef
 }
 
@@ -164,7 +164,7 @@ entry:
 ; PR://13046
 define void @func_o() nounwind uwtable {
 entry:
-  %0 = load i16* undef, align 2
+  %0 = load i16, i16* undef, align 2
   br i1 undef, label %if.then.i, label %if.end.i
 
 if.then.i:                                        ; preds = %entry
@@ -217,17 +217,15 @@ entry:
 ; PR13475
 ; If we have sub a, b and cmp b, a and the result of cmp is used
 ; by sbb, we should not optimize cmp away.
-define i32 @func_q(i32 %j.4, i32 %w, i32 %el) {
+define i32 @func_q(i32 %a0, i32 %a1, i32 %a2) {
 ; CHECK-LABEL: func_q:
 ; CHECK: cmp
 ; CHECK-NEXT: sbb
-  %tmp532 = add i32 %j.4, %w
-  %tmp533 = icmp ugt i32 %tmp532, %el
-  %tmp534 = icmp ult i32 %w, %el
-  %or.cond = and i1 %tmp533, %tmp534
-  %tmp535 = sub i32 %el, %w
-  %j.5 = select i1 %or.cond, i32 %tmp535, i32 %j.4
-  ret i32 %j.5
+  %1 = icmp ult i32 %a0, %a1
+  %2 = sub i32 %a1, %a0
+  %3 = select i1 %1, i32 -1, i32 0
+  %4 = xor i32 %2, %3
+  ret i32 %4
 }
 ; rdar://11873276
 define i8* @func_r(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
@@ -238,14 +236,14 @@ entry:
 ; CHECK: j
 ; CHECK-NOT: sub
 ; CHECK: ret
-  %0 = load i32* %offset, align 8
+  %0 = load i32, i32* %offset, align 8
   %cmp = icmp slt i32 %0, %size
   br i1 %cmp, label %return, label %if.end
 
 if.end:
   %sub = sub nsw i32 %0, %size
   store i32 %sub, i32* %offset, align 8
-  %add.ptr = getelementptr inbounds i8* %base, i32 %sub
+  %add.ptr = getelementptr inbounds i8, i8* %base, i32 %sub
   br label %return
 
 return:
@@ -287,10 +285,10 @@ entry:
 ; CHECK: andb
 ; CHECK: j
 ; CHECK: ret
-  %0 = load i32* @b, align 4
+  %0 = load i32, i32* @b, align 4
   %cmp = icmp ult i32 %0, %p1
   %conv = zext i1 %cmp to i32
-  %1 = load i32* @a, align 4
+  %1 = load i32, i32* @a, align 4
   %and = and i32 %conv, %1
   %conv1 = trunc i32 %and to i8
   %2 = urem i8 %conv1, 3
diff --git a/test/CodeGen/X86/jump_table_alias.ll b/test/CodeGen/X86/jump_table_alias.ll
deleted file mode 100644
index 20622009e376..000000000000
--- a/test/CodeGen/X86/jump_table_alias.ll
+++ /dev/null
@@ -1,32 +0,0 @@
-; RUN: llc <%s -jump-table-type=single | FileCheck %s
-target triple = "x86_64-unknown-linux-gnu"
-define i32 @f() unnamed_addr jumptable {
-entry:
-  ret i32 0
-}
-
-@i = internal alias i32 ()* @f
-@j = alias i32 ()* @f
-
-define i32 @main(i32 %argc, i8** %argv) {
-  %temp = alloca i32 ()*, align 8
-  store i32 ()* @i, i32()** %temp, align 8
-; CHECK: movq    $__llvm_jump_instr_table_0_1
-  %1 = load i32 ()** %temp, align 8
-; CHECK: movl    $__llvm_jump_instr_table_0_1
-  %2 = call i32 ()* %1()
-  %3 = call i32 ()* @i()
-; CHECK: callq   i
-  %4 = call i32 ()* @j()
-; CHECK: callq   j
-  ret i32 %3
-}
-
-; There should only be one table, even though there are two GlobalAliases,
-; because they both alias the same value.
-
-; CHECK:         .align  8, 0x90
-; CHECK:         .type   __llvm_jump_instr_table_0_1,@function
-; CHECK: __llvm_jump_instr_table_0_1:
-; CHECK:         jmp     f@PLT
-
diff --git a/test/CodeGen/X86/jump_table_align.ll b/test/CodeGen/X86/jump_table_align.ll
deleted file mode 100644
index 6ad48d1f54f7..000000000000
--- a/test/CodeGen/X86/jump_table_align.ll
+++ /dev/null
@@ -1,29 +0,0 @@
-; RUN: llc -filetype=obj <%s -jump-table-type=single -o %t1
-; RUN: llvm-objdump -triple=x86_64-unknown-linux-gnu -d %t1 | FileCheck %s
-target triple = "x86_64-unknown-linux-gnu"
-define i32 @f() unnamed_addr jumptable {
-  ret i32 0
-}
-
-define i32 @g(i8* %a) unnamed_addr jumptable {
-  ret i32 0
-}
-
-define void @h(void ()* %func) unnamed_addr jumptable {
-  ret void
-}
-
-define i32 @main() {
-  %g = alloca i32 (...)*, align 8
-  store i32 (...)* bitcast (i32 ()* @f to i32 (...)*), i32 (...)** %g, align 8
-  %1 = load i32 (...)** %g, align 8
-  %call = call i32 (...)* %1()
-  call void (void ()*)* @h(void ()* bitcast (void (void ()*)* @h to void ()*))
-  %a = call i32 (i32*)* bitcast (i32 (i8*)* @g to i32(i32*)*)(i32* null)
-  ret i32 %a
-}
-
-; Make sure that the padding from getJumpInstrTableEntryBound is right.
-; CHECK: __llvm_jump_instr_table_0_1:
-; CHECK-NEXT: e9 00 00 00 00                                  jmp     0
-; CHECK-NEXT: 0f 1f 00                                        nopl    (%rax)
diff --git a/test/CodeGen/X86/jump_table_bitcast.ll b/test/CodeGen/X86/jump_table_bitcast.ll
deleted file mode 100644
index 749b77a166ea..000000000000
--- a/test/CodeGen/X86/jump_table_bitcast.ll
+++ /dev/null
@@ -1,43 +0,0 @@
-; RUN: llc <%s -jump-table-type=single | FileCheck %s
-target triple = "x86_64-unknown-linux-gnu"
-define i32 @f() unnamed_addr jumptable {
-  ret i32 0
-}
-
-define i32 @g(i8* %a) unnamed_addr jumptable {
-  ret i32 0
-}
-
-define void @h(void ()* %func) unnamed_addr jumptable {
-  ret void
-}
-
-define i32 @main() {
-  %g = alloca i32 (...)*, align 8
-  store i32 (...)* bitcast (i32 ()* @f to i32 (...)*), i32 (...)** %g, align 8
-; CHECK: movq    $__llvm_jump_instr_table_0_[[ENTRY:1|2|3]],
-; CHECK: movl    $__llvm_jump_instr_table_0_[[ENTRY]],
-  %1 = load i32 (...)** %g, align 8
-  %call = call i32 (...)* %1()
-  call void (void ()*)* @h(void ()* bitcast (void (void ()*)* @h to void ()*))
-; CHECK: movl    $__llvm_jump_instr_table_0_{{1|2|3}},
-; CHECK: callq   h
-
-  %a = call i32 (i32*)* bitcast (i32 (i8*)* @g to i32(i32*)*)(i32* null)
-; CHECK: callq g
-  ret i32 %a
-}
-
-; CHECK:         .align  8, 0x90
-; CHECK:         .type   __llvm_jump_instr_table_0_1,@function
-; CHECK: __llvm_jump_instr_table_0_1:
-; CHECK:         jmp     {{f|g|h}}@PLT
-; CHECK:         .align  8, 0x90
-; CHECK:         .type   __llvm_jump_instr_table_0_2,@function
-; CHECK: __llvm_jump_instr_table_0_2:
-; CHECK:         jmp     {{f|g|h}}@PLT
-; CHECK:         .align  8, 0x90
-; CHECK:         .type   __llvm_jump_instr_table_0_3,@function
-; CHECK: __llvm_jump_instr_table_0_3:
-; CHECK:         jmp     {{f|g|h}}@PLT
-
diff --git a/test/CodeGen/X86/jump_tables.ll b/test/CodeGen/X86/jump_tables.ll
deleted file mode 100644
index 485154eaa2a9..000000000000
--- a/test/CodeGen/X86/jump_tables.ll
+++ /dev/null
@@ -1,255 +0,0 @@
-; RUN: llc <%s -jump-table-type=single | FileCheck --check-prefix=SINGLE %s
-; RUN: llc <%s -jump-table-type=arity | FileCheck --check-prefix=ARITY %s
-; RUN: llc <%s -jump-table-type=simplified | FileCheck --check-prefix=SIMPL %s
-; RUN: llc <%s -jump-table-type=full | FileCheck --check-prefix=FULL %s
-
-target triple = "x86_64-unknown-linux-gnu"
-
-%struct.fun_struct = type { i32 (...)* }
-
-@a = global [12 x i32 () *] [ i32 ()* bitcast (void ()* @indirect_fun to i32 ()*),
-			      i32 ()* bitcast (void ()* @indirect_fun_match to i32 ()*),
-			      i32 ()* bitcast (i32 ()* @indirect_fun_i32 to i32 ()*),
-			      i32 ()* bitcast (i32 (i32)* @indirect_fun_i32_1 to i32 ()*),
-			      i32 ()* bitcast (i32 (i32, i32)* @indirect_fun_i32_2 to i32 ()*),
-			      i32 ()* bitcast (i32* (i32*, i32)* @indirect_fun_i32S_2 to i32 ()*),
-			      i32 ()* bitcast (void (%struct.fun_struct)* @indirect_fun_struct to i32 ()*),
-			      i32 ()* bitcast (void (i32 (...)*, i32)* @indirect_fun_fun to i32 ()*),
-			      i32 ()* bitcast (i32 (i32 (...)*, i32)* @indirect_fun_fun_ret to i32 ()*),
-			      i32 ()* bitcast (void ([19 x i8])* @indirect_fun_array to i32 ()*),
-			      i32 ()* bitcast (void (<3 x i32>)* @indirect_fun_vec to i32 ()*),
-			      i32 ()* bitcast (void (<4 x float>)* @indirect_fun_vec_2 to i32 ()*)
-			    ]
-
-define void @indirect_fun() unnamed_addr jumptable {
-  ret void
-}
-
-define void @indirect_fun_match() unnamed_addr jumptable {
-  ret void
-}
-
-define i32 @indirect_fun_i32() unnamed_addr jumptable {
-  ret i32 0
-}
-
-define i32 @indirect_fun_i32_1(i32 %a) unnamed_addr jumptable {
-  ret i32 %a
-}
-
-define i32 @indirect_fun_i32_2(i32 %a, i32 %b) unnamed_addr jumptable {
-  ret i32 %a
-}
-
-define i32* @indirect_fun_i32S_2(i32* %a, i32 %b) unnamed_addr jumptable {
-  ret i32* %a
-}
-
-define void @indirect_fun_struct(%struct.fun_struct %fs) unnamed_addr jumptable {
-  ret void
-}
-
-define void @indirect_fun_fun(i32 (...)* %fun, i32 %a) unnamed_addr jumptable {
-  ret void
-}
-
-define i32 @indirect_fun_fun_ret(i32 (...)* %fun, i32 %a) unnamed_addr jumptable {
-  ret i32 %a
-}
-
-define void @indirect_fun_array([19 x i8] %a) unnamed_addr jumptable {
-  ret void
-}
-
-define void @indirect_fun_vec(<3 x i32> %a) unnamed_addr jumptable {
-  ret void
-}
-
-define void @indirect_fun_vec_2(<4 x float> %a) unnamed_addr jumptable {
-  ret void
-}
-
-define i32 @m(void ()* %fun) {
-  call void ()* %fun()
-  ret i32 0
-}
-
-define void ()* @get_fun() {
-  ret void ()* @indirect_fun
-; SINGLE: movl    $__llvm_jump_instr_table_0_
-; ARITY: movl    $__llvm_jump_instr_table_
-; SIMPL: movl    $__llvm_jump_instr_table_
-; FULL: movl    $__llvm_jump_instr_table_
-}
-
-define i32 @main(i32 %argc, i8** %argv) {
-  %f = call void ()* ()* @get_fun()
-  %a = call i32 @m(void ()* %f)
-  ret i32 %a
-}
-
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         .type   __llvm_jump_instr_table_0_1,@function
-; SINGLE-DAG: __llvm_jump_instr_table_0_1:
-; SINGLE-DAG:         jmp     indirect_fun_array@PLT
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         .type   __llvm_jump_instr_table_0_2,@function
-; SINGLE-DAG: __llvm_jump_instr_table_0_2:
-; SINGLE-DAG:         jmp     indirect_fun_i32_2@PLT
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         .type   __llvm_jump_instr_table_0_3,@function
-; SINGLE-DAG: __llvm_jump_instr_table_0_3:
-; SINGLE-DAG:         jmp     indirect_fun_vec_2@PLT
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         .type   __llvm_jump_instr_table_0_4,@function
-; SINGLE-DAG: __llvm_jump_instr_table_0_4:
-; SINGLE-DAG:         jmp     indirect_fun_i32S_2@PLT
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         .type   __llvm_jump_instr_table_0_5,@function
-; SINGLE-DAG: __llvm_jump_instr_table_0_5:
-; SINGLE-DAG:         jmp     indirect_fun_struct@PLT
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         .type   __llvm_jump_instr_table_0_6,@function
-; SINGLE-DAG: __llvm_jump_instr_table_0_6:
-; SINGLE-DAG:         jmp     indirect_fun_i32_1@PLT
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         .type   __llvm_jump_instr_table_0_7,@function
-; SINGLE-DAG: __llvm_jump_instr_table_0_7:
-; SINGLE-DAG:         jmp     indirect_fun_i32@PLT
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         .type   __llvm_jump_instr_table_0_8,@function
-; SINGLE-DAG: __llvm_jump_instr_table_0_8:
-; SINGLE-DAG:         jmp     indirect_fun_fun@PLT
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         .type   __llvm_jump_instr_table_0_9,@function
-; SINGLE-DAG: __llvm_jump_instr_table_0_9:
-; SINGLE-DAG:         jmp     indirect_fun_fun_ret@PLT
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         .type   __llvm_jump_instr_table_0_10,@function
-; SINGLE-DAG: __llvm_jump_instr_table_0_10:
-; SINGLE-DAG:         jmp     indirect_fun@PLT
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         .type   __llvm_jump_instr_table_0_11,@function
-; SINGLE-DAG: __llvm_jump_instr_table_0_11:
-; SINGLE-DAG:         jmp     indirect_fun_match@PLT
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         .type   __llvm_jump_instr_table_0_12,@function
-; SINGLE-DAG: __llvm_jump_instr_table_0_12:
-; SINGLE-DAG:         jmp     indirect_fun_vec@PLT
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         ud2
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         ud2
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         ud2
-; SINGLE-DAG:         .align  8, 0x90
-; SINGLE-DAG:         ud2
-
-
-; ARITY-DAG:         .align  8, 0x90
-; ARITY-DAG:         .type   __llvm_jump_instr_table_2_1,@function
-; ARITY-DAG: __llvm_jump_instr_table_2_1:
-; ARITY-DAG:         jmp     indirect_fun{{.*}}@PLT
-; ARITY-DAG:         .align  8, 0x90
-; ARITY-DAG:         ud2
-; ARITY-DAG:         .align  8, 0x90
-; ARITY-DAG:         .type   __llvm_jump_instr_table_0_1,@function
-; ARITY-DAG: __llvm_jump_instr_table_0_1:
-; ARITY-DAG:         jmp     indirect_fun{{.*}}@PLT
-; ARITY-DAG:         .align  8, 0x90
-; ARITY-DAG:         .type   __llvm_jump_instr_table_1_1,@function
-; ARITY-DAG: __llvm_jump_instr_table_1_1:
-; ARITY-DAG:         jmp     indirect_fun{{.*}}@PLT
-
-; SIMPL-DAG:         .align  8, 0x90
-; SIMPL-DAG:         .type   __llvm_jump_instr_table_2_1,@function
-; SIMPL-DAG: __llvm_jump_instr_table_2_1:
-; SIMPL-DAG:         jmp     indirect_fun{{.*}}@PLT
-; SIMPL-DAG:         .align  8, 0x90
-; SIMPL-DAG:         ud2
-; SIMPL-DAG:         .align  8, 0x90
-; SIMPL-DAG:         .type   __llvm_jump_instr_table_0_1,@function
-; SIMPL-DAG: __llvm_jump_instr_table_0_1:
-; SIMPL-DAG:         jmp     indirect_fun{{.*}}@PLT
-; SIMPL-DAG:         .align  8, 0x90
-; SIMPL-DAG:         .type   __llvm_jump_instr_table_1_1,@function
-; SIMPL-DAG: __llvm_jump_instr_table_1_1:
-; SIMPL-DAG:         jmp     indirect_fun{{.*}}@PLT
-; SIMPL-DAG:         .align  8, 0x90
-; SIMPL-DAG:         .type   __llvm_jump_instr_table_3_1,@function
-; SIMPL-DAG: __llvm_jump_instr_table_3_1:
-; SIMPL-DAG:         jmp     indirect_fun{{.*}}@PLT
-; SIMPL-DAG:         .align  8, 0x90
-; SIMPL-DAG:         .type   __llvm_jump_instr_table_4_1,@function
-; SIMPL-DAG: __llvm_jump_instr_table_4_1:
-; SIMPL-DAG:         jmp     indirect_fun{{.*}}@PLT
-
-
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        .type   __llvm_jump_instr_table_10_1,@function
-; FULL-DAG:__llvm_jump_instr_table_10_1:
-; FULL-DAG:        jmp     indirect_fun_i32_1@PLT
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        ud2
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        .type   __llvm_jump_instr_table_9_1,@function
-; FULL-DAG:__llvm_jump_instr_table_9_1:
-; FULL-DAG:        jmp     indirect_fun_i32_2@PLT
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        ud2
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        .type   __llvm_jump_instr_table_7_1,@function
-; FULL-DAG:__llvm_jump_instr_table_7_1:
-; FULL-DAG:        jmp     indirect_fun_i32S_2@PLT
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        ud2
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        .type   __llvm_jump_instr_table_3_1,@function
-; FULL-DAG:__llvm_jump_instr_table_3_1:
-; FULL-DAG:        jmp     indirect_fun_vec_2@PLT
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        ud2
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        .type   __llvm_jump_instr_table_2_1,@function
-; FULL-DAG:__llvm_jump_instr_table_2_1:
-; FULL-DAG:        jmp     indirect_fun@PLT
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        ud2
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        ud2
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        .type   __llvm_jump_instr_table_8_1,@function
-; FULL-DAG:__llvm_jump_instr_table_8_1:
-; FULL-DAG:        jmp     indirect_fun_i32@PLT
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        ud2
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        .type   __llvm_jump_instr_table_1_1,@function
-; FULL-DAG:__llvm_jump_instr_table_1_1:
-; FULL-DAG:        jmp     indirect_fun_array@PLT
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        ud2
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        .type   __llvm_jump_instr_table_0_1,@function
-; FULL-DAG:__llvm_jump_instr_table_0_1:
-; FULL-DAG:        jmp     indirect_fun_vec@PLT
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        ud2
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        .type   __llvm_jump_instr_table_6_1,@function
-; FULL-DAG:__llvm_jump_instr_table_6_1:
-; FULL-DAG:        jmp     indirect_fun_struct@PLT
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        ud2
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        .type   __llvm_jump_instr_table_5_1,@function
-; FULL-DAG:__llvm_jump_instr_table_5_1:
-; FULL-DAG:        jmp     indirect_fun_fun@PLT
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        ud2
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        .type   __llvm_jump_instr_table_4_1,@function
-; FULL-DAG:__llvm_jump_instr_table_4_1:
-; FULL-DAG:        jmp     indirect_fun_fun_ret@PLT
-; FULL-DAG:        .align  8, 0x90
-; FULL-DAG:        ud2
diff --git a/test/CodeGen/X86/large-code-model-isel.ll b/test/CodeGen/X86/large-code-model-isel.ll
index 3c283d934949..9edabcd0520d 100644
--- a/test/CodeGen/X86/large-code-model-isel.ll
+++ b/test/CodeGen/X86/large-code-model-isel.ll
@@ -8,6 +8,6 @@ define void @foo() {
 ; CHECK-LABEL: foo:
 entry:
 ; CHECK: callq
-  %call = call i64* undef(i64* undef, i8* getelementptr inbounds ([2 x i8]* @.str10, i32 0, i32 0))
+  %call = call i64* undef(i64* undef, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str10, i32 0, i32 0))
   ret void
 }
diff --git a/test/CodeGen/X86/large-constants.ll b/test/CodeGen/X86/large-constants.ll
index 157ecc4af66b..945d633eec12 100644
--- a/test/CodeGen/X86/large-constants.ll
+++ b/test/CodeGen/X86/large-constants.ll
@@ -40,10 +40,10 @@ fail:
 
 define void @constant_expressions() {
 entry:
-  %0 = load i64* inttoptr (i64 add (i64 51250129900, i64 0) to i64*)
-  %1 = load i64* inttoptr (i64 add (i64 51250129900, i64 8) to i64*)
-  %2 = load i64* inttoptr (i64 add (i64 51250129900, i64 16) to i64*)
-  %3 = load i64* inttoptr (i64 add (i64 51250129900, i64 24) to i64*)
+  %0 = load i64, i64* inttoptr (i64 add (i64 51250129900, i64 0) to i64*)
+  %1 = load i64, i64* inttoptr (i64 add (i64 51250129900, i64 8) to i64*)
+  %2 = load i64, i64* inttoptr (i64 add (i64 51250129900, i64 16) to i64*)
+  %3 = load i64, i64* inttoptr (i64 add (i64 51250129900, i64 24) to i64*)
   %4 = add i64 %0, %1
   %5 = add i64 %2, %3
   %6 = add i64 %4, %5
@@ -54,10 +54,10 @@ entry:
 
 define void @constant_expressions2() {
 entry:
-  %0 = load i64* inttoptr (i64 51250129900 to i64*)
-  %1 = load i64* inttoptr (i64 51250129908 to i64*)
-  %2 = load i64* inttoptr (i64 51250129916 to i64*)
-  %3 = load i64* inttoptr (i64 51250129924 to i64*)
+  %0 = load i64, i64* inttoptr (i64 51250129900 to i64*)
+  %1 = load i64, i64* inttoptr (i64 51250129908 to i64*)
+  %2 = load i64, i64* inttoptr (i64 51250129916 to i64*)
+  %3 = load i64, i64* inttoptr (i64 51250129924 to i64*)
   %4 = add i64 %0, %1
   %5 = add i64 %2, %3
   %6 = add i64 %4, %5
diff --git a/test/CodeGen/X86/large-gep-chain.ll b/test/CodeGen/X86/large-gep-chain.ll
index 5cf4661f8ff9..44247b8658a7 100644
--- a/test/CodeGen/X86/large-gep-chain.ll
+++ b/test/CodeGen/X86/large-gep-chain.ll
@@ -21,25275 +21,25275 @@ bb1:                                              ; preds = %bb
   br label %bb25362
 
 bb2:                                              ; preds = %bb
-  %tmp = getelementptr inbounds float* null, i64 1
-  %tmp3 = getelementptr inbounds float* %tmp, i64 1
-  %tmp4 = getelementptr inbounds float* %tmp3, i64 1
-  %tmp5 = getelementptr inbounds float* %tmp4, i64 1
-  %tmp6 = getelementptr inbounds float* %tmp5, i64 1
-  %tmp7 = getelementptr inbounds float* %tmp6, i64 1
-  %tmp8 = getelementptr inbounds float* %tmp7, i64 1
-  %tmp9 = getelementptr inbounds float* %tmp8, i64 1
-  %tmp10 = getelementptr inbounds float* %tmp9, i64 1
-  %tmp11 = getelementptr inbounds float* %tmp10, i64 1
-  %tmp12 = getelementptr inbounds float* %tmp11, i64 1
-  %tmp13 = getelementptr inbounds float* %tmp12, i64 1
-  %tmp14 = getelementptr inbounds float* %tmp13, i64 1
-  %tmp15 = getelementptr inbounds float* %tmp14, i64 1
-  %tmp16 = getelementptr inbounds float* %tmp15, i64 1
-  %tmp17 = getelementptr inbounds float* %tmp16, i64 1
-  %tmp18 = getelementptr inbounds float* %tmp17, i64 1
-  %tmp19 = getelementptr inbounds float* %tmp18, i64 1
-  %tmp20 = getelementptr inbounds float* %tmp19, i64 1
-  %tmp21 = getelementptr inbounds float* %tmp20, i64 1
-  %tmp22 = getelementptr inbounds float* %tmp21, i64 1
-  %tmp23 = getelementptr inbounds float* %tmp22, i64 1
-  %tmp24 = getelementptr inbounds float* %tmp23, i64 1
-  %tmp25 = getelementptr inbounds float* %tmp24, i64 1
-  %tmp26 = getelementptr inbounds float* %tmp25, i64 1
-  %tmp27 = getelementptr inbounds float* %tmp26, i64 1
-  %tmp28 = getelementptr inbounds float* %tmp27, i64 1
-  %tmp29 = getelementptr inbounds float* %tmp28, i64 1
-  %tmp30 = getelementptr inbounds float* %tmp29, i64 1
-  %tmp31 = getelementptr inbounds float* %tmp30, i64 1
-  %tmp32 = getelementptr inbounds float* %tmp31, i64 1
-  %tmp33 = getelementptr inbounds float* %tmp32, i64 1
-  %tmp34 = getelementptr inbounds float* %tmp33, i64 1
-  %tmp35 = getelementptr inbounds float* %tmp34, i64 1
-  %tmp36 = getelementptr inbounds float* %tmp35, i64 1
-  %tmp37 = getelementptr inbounds float* %tmp36, i64 1
-  %tmp38 = getelementptr inbounds float* %tmp37, i64 1
-  %tmp39 = getelementptr inbounds float* %tmp38, i64 1
-  %tmp40 = getelementptr inbounds float* %tmp39, i64 1
-  %tmp41 = getelementptr inbounds float* %tmp40, i64 1
-  %tmp42 = getelementptr inbounds float* %tmp41, i64 1
-  %tmp43 = getelementptr inbounds float* %tmp42, i64 1
-  %tmp44 = getelementptr inbounds float* %tmp43, i64 1
-  %tmp45 = getelementptr inbounds float* %tmp44, i64 1
-  %tmp46 = getelementptr inbounds float* %tmp45, i64 1
-  %tmp47 = getelementptr inbounds float* %tmp46, i64 1
-  %tmp48 = getelementptr inbounds float* %tmp47, i64 1
-  %tmp49 = getelementptr inbounds float* %tmp48, i64 1
-  %tmp50 = getelementptr inbounds float* %tmp49, i64 1
-  %tmp51 = getelementptr inbounds float* %tmp50, i64 1
-  %tmp52 = getelementptr inbounds float* %tmp51, i64 1
-  %tmp53 = getelementptr inbounds float* %tmp52, i64 1
-  %tmp54 = getelementptr inbounds float* %tmp53, i64 1
-  %tmp55 = getelementptr inbounds float* %tmp54, i64 1
-  %tmp56 = getelementptr inbounds float* %tmp55, i64 1
-  %tmp57 = getelementptr inbounds float* %tmp56, i64 1
-  %tmp58 = getelementptr inbounds float* %tmp57, i64 1
-  %tmp59 = getelementptr inbounds float* %tmp58, i64 1
-  %tmp60 = getelementptr inbounds float* %tmp59, i64 1
-  %tmp61 = getelementptr inbounds float* %tmp60, i64 1
-  %tmp62 = getelementptr inbounds float* %tmp61, i64 1
-  %tmp63 = getelementptr inbounds float* %tmp62, i64 1
-  %tmp64 = getelementptr inbounds float* %tmp63, i64 1
-  %tmp65 = getelementptr inbounds float* %tmp64, i64 1
-  %tmp66 = getelementptr inbounds float* %tmp65, i64 1
-  %tmp67 = getelementptr inbounds float* %tmp66, i64 1
-  %tmp68 = getelementptr inbounds float* %tmp67, i64 1
-  %tmp69 = getelementptr inbounds float* %tmp68, i64 1
-  %tmp70 = getelementptr inbounds float* %tmp69, i64 1
-  %tmp71 = getelementptr inbounds float* %tmp70, i64 1
-  %tmp72 = getelementptr inbounds float* %tmp71, i64 1
-  %tmp73 = getelementptr inbounds float* %tmp72, i64 1
-  %tmp74 = getelementptr inbounds float* %tmp73, i64 1
-  %tmp75 = getelementptr inbounds float* %tmp74, i64 1
-  %tmp76 = getelementptr inbounds float* %tmp75, i64 1
-  %tmp77 = getelementptr inbounds float* %tmp76, i64 1
-  %tmp78 = getelementptr inbounds float* %tmp77, i64 1
-  %tmp79 = getelementptr inbounds float* %tmp78, i64 1
-  %tmp80 = getelementptr inbounds float* %tmp79, i64 1
-  %tmp81 = getelementptr inbounds float* %tmp80, i64 1
-  %tmp82 = getelementptr inbounds float* %tmp81, i64 1
-  %tmp83 = getelementptr inbounds float* %tmp82, i64 1
-  %tmp84 = getelementptr inbounds float* %tmp83, i64 1
-  %tmp85 = getelementptr inbounds float* %tmp84, i64 1
-  %tmp86 = getelementptr inbounds float* %tmp85, i64 1
-  %tmp87 = getelementptr inbounds float* %tmp86, i64 1
-  %tmp88 = getelementptr inbounds float* %tmp87, i64 1
-  %tmp89 = getelementptr inbounds float* %tmp88, i64 1
-  %tmp90 = getelementptr inbounds float* %tmp89, i64 1
-  %tmp91 = getelementptr inbounds float* %tmp90, i64 1
-  %tmp92 = getelementptr inbounds float* %tmp91, i64 1
-  %tmp93 = getelementptr inbounds float* %tmp92, i64 1
-  %tmp94 = getelementptr inbounds float* %tmp93, i64 1
-  %tmp95 = getelementptr inbounds float* %tmp94, i64 1
-  %tmp96 = getelementptr inbounds float* %tmp95, i64 1
-  %tmp97 = getelementptr inbounds float* %tmp96, i64 1
-  %tmp98 = getelementptr inbounds float* %tmp97, i64 1
-  %tmp99 = getelementptr inbounds float* %tmp98, i64 1
-  %tmp100 = getelementptr inbounds float* %tmp99, i64 1
-  %tmp101 = getelementptr inbounds float* %tmp100, i64 1
-  %tmp102 = getelementptr inbounds float* %tmp101, i64 1
-  %tmp103 = getelementptr inbounds float* %tmp102, i64 1
-  %tmp104 = getelementptr inbounds float* %tmp103, i64 1
-  %tmp105 = getelementptr inbounds float* %tmp104, i64 1
-  %tmp106 = getelementptr inbounds float* %tmp105, i64 1
-  %tmp107 = getelementptr inbounds float* %tmp106, i64 1
-  %tmp108 = getelementptr inbounds float* %tmp107, i64 1
-  %tmp109 = getelementptr inbounds float* %tmp108, i64 1
-  %tmp110 = getelementptr inbounds float* %tmp109, i64 1
-  %tmp111 = getelementptr inbounds float* %tmp110, i64 1
-  %tmp112 = getelementptr inbounds float* %tmp111, i64 1
-  %tmp113 = getelementptr inbounds float* %tmp112, i64 1
-  %tmp114 = getelementptr inbounds float* %tmp113, i64 1
-  %tmp115 = getelementptr inbounds float* %tmp114, i64 1
-  %tmp116 = getelementptr inbounds float* %tmp115, i64 1
-  %tmp117 = getelementptr inbounds float* %tmp116, i64 1
-  %tmp118 = getelementptr inbounds float* %tmp117, i64 1
-  %tmp119 = getelementptr inbounds float* %tmp118, i64 1
-  %tmp120 = getelementptr inbounds float* %tmp119, i64 1
-  %tmp121 = getelementptr inbounds float* %tmp120, i64 1
-  %tmp122 = getelementptr inbounds float* %tmp121, i64 1
-  %tmp123 = getelementptr inbounds float* %tmp122, i64 1
-  %tmp124 = getelementptr inbounds float* %tmp123, i64 1
-  %tmp125 = getelementptr inbounds float* %tmp124, i64 1
-  %tmp126 = getelementptr inbounds float* %tmp125, i64 1
-  %tmp127 = getelementptr inbounds float* %tmp126, i64 1
-  %tmp128 = getelementptr inbounds float* %tmp127, i64 1
-  %tmp129 = getelementptr inbounds float* %tmp128, i64 1
-  %tmp130 = getelementptr inbounds float* %tmp129, i64 1
-  %tmp131 = getelementptr inbounds float* %tmp130, i64 1
-  %tmp132 = getelementptr inbounds float* %tmp131, i64 1
-  %tmp133 = getelementptr inbounds float* %tmp132, i64 1
-  %tmp134 = getelementptr inbounds float* %tmp133, i64 1
-  %tmp135 = getelementptr inbounds float* %tmp134, i64 1
-  %tmp136 = getelementptr inbounds float* %tmp135, i64 1
-  %tmp137 = getelementptr inbounds float* %tmp136, i64 1
-  %tmp138 = getelementptr inbounds float* %tmp137, i64 1
-  %tmp139 = getelementptr inbounds float* %tmp138, i64 1
-  %tmp140 = getelementptr inbounds float* %tmp139, i64 1
-  %tmp141 = getelementptr inbounds float* %tmp140, i64 1
-  %tmp142 = getelementptr inbounds float* %tmp141, i64 1
-  %tmp143 = getelementptr inbounds float* %tmp142, i64 1
-  %tmp144 = getelementptr inbounds float* %tmp143, i64 1
-  %tmp145 = getelementptr inbounds float* %tmp144, i64 1
-  %tmp146 = getelementptr inbounds float* %tmp145, i64 1
-  %tmp147 = getelementptr inbounds float* %tmp146, i64 1
-  %tmp148 = getelementptr inbounds float* %tmp147, i64 1
-  %tmp149 = getelementptr inbounds float* %tmp148, i64 1
-  %tmp150 = getelementptr inbounds float* %tmp149, i64 1
-  %tmp151 = getelementptr inbounds float* %tmp150, i64 1
-  %tmp152 = getelementptr inbounds float* %tmp151, i64 1
-  %tmp153 = getelementptr inbounds float* %tmp152, i64 1
-  %tmp154 = getelementptr inbounds float* %tmp153, i64 1
-  %tmp155 = getelementptr inbounds float* %tmp154, i64 1
-  %tmp156 = getelementptr inbounds float* %tmp155, i64 1
-  %tmp157 = getelementptr inbounds float* %tmp156, i64 1
-  %tmp158 = getelementptr inbounds float* %tmp157, i64 1
-  %tmp159 = getelementptr inbounds float* %tmp158, i64 1
-  %tmp160 = getelementptr inbounds float* %tmp159, i64 1
-  %tmp161 = getelementptr inbounds float* %tmp160, i64 1
-  %tmp162 = getelementptr inbounds float* %tmp161, i64 1
-  %tmp163 = getelementptr inbounds float* %tmp162, i64 1
-  %tmp164 = getelementptr inbounds float* %tmp163, i64 1
-  %tmp165 = getelementptr inbounds float* %tmp164, i64 1
-  %tmp166 = getelementptr inbounds float* %tmp165, i64 1
-  %tmp167 = getelementptr inbounds float* %tmp166, i64 1
-  %tmp168 = getelementptr inbounds float* %tmp167, i64 1
-  %tmp169 = getelementptr inbounds float* %tmp168, i64 1
-  %tmp170 = getelementptr inbounds float* %tmp169, i64 1
-  %tmp171 = getelementptr inbounds float* %tmp170, i64 1
-  %tmp172 = getelementptr inbounds float* %tmp171, i64 1
-  %tmp173 = getelementptr inbounds float* %tmp172, i64 1
-  %tmp174 = getelementptr inbounds float* %tmp173, i64 1
-  %tmp175 = getelementptr inbounds float* %tmp174, i64 1
-  %tmp176 = getelementptr inbounds float* %tmp175, i64 1
-  %tmp177 = getelementptr inbounds float* %tmp176, i64 1
-  %tmp178 = getelementptr inbounds float* %tmp177, i64 1
-  %tmp179 = getelementptr inbounds float* %tmp178, i64 1
-  %tmp180 = getelementptr inbounds float* %tmp179, i64 1
-  %tmp181 = getelementptr inbounds float* %tmp180, i64 1
-  %tmp182 = getelementptr inbounds float* %tmp181, i64 1
-  %tmp183 = getelementptr inbounds float* %tmp182, i64 1
-  %tmp184 = getelementptr inbounds float* %tmp183, i64 1
-  %tmp185 = getelementptr inbounds float* %tmp184, i64 1
-  %tmp186 = getelementptr inbounds float* %tmp185, i64 1
-  %tmp187 = getelementptr inbounds float* %tmp186, i64 1
-  %tmp188 = getelementptr inbounds float* %tmp187, i64 1
-  %tmp189 = getelementptr inbounds float* %tmp188, i64 1
-  %tmp190 = getelementptr inbounds float* %tmp189, i64 1
-  %tmp191 = getelementptr inbounds float* %tmp190, i64 1
-  %tmp192 = getelementptr inbounds float* %tmp191, i64 1
-  %tmp193 = getelementptr inbounds float* %tmp192, i64 1
-  %tmp194 = getelementptr inbounds float* %tmp193, i64 1
-  %tmp195 = getelementptr inbounds float* %tmp194, i64 1
-  %tmp196 = getelementptr inbounds float* %tmp195, i64 1
-  %tmp197 = getelementptr inbounds float* %tmp196, i64 1
-  %tmp198 = getelementptr inbounds float* %tmp197, i64 1
-  %tmp199 = getelementptr inbounds float* %tmp198, i64 1
-  %tmp200 = getelementptr inbounds float* %tmp199, i64 1
-  %tmp201 = getelementptr inbounds float* %tmp200, i64 1
-  %tmp202 = getelementptr inbounds float* %tmp201, i64 1
-  %tmp203 = getelementptr inbounds float* %tmp202, i64 1
-  %tmp204 = getelementptr inbounds float* %tmp203, i64 1
-  %tmp205 = getelementptr inbounds float* %tmp204, i64 1
-  %tmp206 = getelementptr inbounds float* %tmp205, i64 1
-  %tmp207 = getelementptr inbounds float* %tmp206, i64 1
-  %tmp208 = getelementptr inbounds float* %tmp207, i64 1
-  %tmp209 = getelementptr inbounds float* %tmp208, i64 1
-  %tmp210 = getelementptr inbounds float* %tmp209, i64 1
-  %tmp211 = getelementptr inbounds float* %tmp210, i64 1
-  %tmp212 = getelementptr inbounds float* %tmp211, i64 1
-  %tmp213 = getelementptr inbounds float* %tmp212, i64 1
-  %tmp214 = getelementptr inbounds float* %tmp213, i64 1
-  %tmp215 = getelementptr inbounds float* %tmp214, i64 1
-  %tmp216 = getelementptr inbounds float* %tmp215, i64 1
-  %tmp217 = getelementptr inbounds float* %tmp216, i64 1
-  %tmp218 = getelementptr inbounds float* %tmp217, i64 1
-  %tmp219 = getelementptr inbounds float* %tmp218, i64 1
-  %tmp220 = getelementptr inbounds float* %tmp219, i64 1
-  %tmp221 = getelementptr inbounds float* %tmp220, i64 1
-  %tmp222 = getelementptr inbounds float* %tmp221, i64 1
-  %tmp223 = getelementptr inbounds float* %tmp222, i64 1
-  %tmp224 = getelementptr inbounds float* %tmp223, i64 1
-  %tmp225 = getelementptr inbounds float* %tmp224, i64 1
-  %tmp226 = getelementptr inbounds float* %tmp225, i64 1
-  %tmp227 = getelementptr inbounds float* %tmp226, i64 1
-  %tmp228 = getelementptr inbounds float* %tmp227, i64 1
-  %tmp229 = getelementptr inbounds float* %tmp228, i64 1
-  %tmp230 = getelementptr inbounds float* %tmp229, i64 1
-  %tmp231 = getelementptr inbounds float* %tmp230, i64 1
-  %tmp232 = getelementptr inbounds float* %tmp231, i64 1
-  %tmp233 = getelementptr inbounds float* %tmp232, i64 1
-  %tmp234 = getelementptr inbounds float* %tmp233, i64 1
-  %tmp235 = getelementptr inbounds float* %tmp234, i64 1
-  %tmp236 = getelementptr inbounds float* %tmp235, i64 1
-  %tmp237 = getelementptr inbounds float* %tmp236, i64 1
-  %tmp238 = getelementptr inbounds float* %tmp237, i64 1
-  %tmp239 = getelementptr inbounds float* %tmp238, i64 1
-  %tmp240 = getelementptr inbounds float* %tmp239, i64 1
-  %tmp241 = getelementptr inbounds float* %tmp240, i64 1
-  %tmp242 = getelementptr inbounds float* %tmp241, i64 1
-  %tmp243 = getelementptr inbounds float* %tmp242, i64 1
-  %tmp244 = getelementptr inbounds float* %tmp243, i64 1
-  %tmp245 = getelementptr inbounds float* %tmp244, i64 1
-  %tmp246 = getelementptr inbounds float* %tmp245, i64 1
-  %tmp247 = getelementptr inbounds float* %tmp246, i64 1
-  %tmp248 = getelementptr inbounds float* %tmp247, i64 1
-  %tmp249 = getelementptr inbounds float* %tmp248, i64 1
-  %tmp250 = getelementptr inbounds float* %tmp249, i64 1
-  %tmp251 = getelementptr inbounds float* %tmp250, i64 1
-  %tmp252 = getelementptr inbounds float* %tmp251, i64 1
-  %tmp253 = getelementptr inbounds float* %tmp252, i64 1
-  %tmp254 = getelementptr inbounds float* %tmp253, i64 1
-  %tmp255 = getelementptr inbounds float* %tmp254, i64 1
-  %tmp256 = getelementptr inbounds float* %tmp255, i64 1
-  %tmp257 = getelementptr inbounds float* %tmp256, i64 1
-  %tmp258 = getelementptr inbounds float* %tmp257, i64 1
-  %tmp259 = getelementptr inbounds float* %tmp258, i64 1
-  %tmp260 = getelementptr inbounds float* %tmp259, i64 1
-  %tmp261 = getelementptr inbounds float* %tmp260, i64 1
-  %tmp262 = getelementptr inbounds float* %tmp261, i64 1
-  %tmp263 = getelementptr inbounds float* %tmp262, i64 1
-  %tmp264 = getelementptr inbounds float* %tmp263, i64 1
-  %tmp265 = getelementptr inbounds float* %tmp264, i64 1
-  %tmp266 = getelementptr inbounds float* %tmp265, i64 1
-  %tmp267 = getelementptr inbounds float* %tmp266, i64 1
-  %tmp268 = getelementptr inbounds float* %tmp267, i64 1
-  %tmp269 = getelementptr inbounds float* %tmp268, i64 1
-  %tmp270 = getelementptr inbounds float* %tmp269, i64 1
-  %tmp271 = getelementptr inbounds float* %tmp270, i64 1
-  %tmp272 = getelementptr inbounds float* %tmp271, i64 1
-  %tmp273 = getelementptr inbounds float* %tmp272, i64 1
-  %tmp274 = getelementptr inbounds float* %tmp273, i64 1
-  %tmp275 = getelementptr inbounds float* %tmp274, i64 1
-  %tmp276 = getelementptr inbounds float* %tmp275, i64 1
-  %tmp277 = getelementptr inbounds float* %tmp276, i64 1
-  %tmp278 = getelementptr inbounds float* %tmp277, i64 1
-  %tmp279 = getelementptr inbounds float* %tmp278, i64 1
-  %tmp280 = getelementptr inbounds float* %tmp279, i64 1
-  %tmp281 = getelementptr inbounds float* %tmp280, i64 1
-  %tmp282 = getelementptr inbounds float* %tmp281, i64 1
-  %tmp283 = getelementptr inbounds float* %tmp282, i64 1
-  %tmp284 = getelementptr inbounds float* %tmp283, i64 1
-  %tmp285 = getelementptr inbounds float* %tmp284, i64 1
-  %tmp286 = getelementptr inbounds float* %tmp285, i64 1
-  %tmp287 = getelementptr inbounds float* %tmp286, i64 1
-  %tmp288 = getelementptr inbounds float* %tmp287, i64 1
-  %tmp289 = getelementptr inbounds float* %tmp288, i64 1
-  %tmp290 = getelementptr inbounds float* %tmp289, i64 1
-  %tmp291 = getelementptr inbounds float* %tmp290, i64 1
-  %tmp292 = getelementptr inbounds float* %tmp291, i64 1
-  %tmp293 = getelementptr inbounds float* %tmp292, i64 1
-  %tmp294 = getelementptr inbounds float* %tmp293, i64 1
-  %tmp295 = getelementptr inbounds float* %tmp294, i64 1
-  %tmp296 = getelementptr inbounds float* %tmp295, i64 1
-  %tmp297 = getelementptr inbounds float* %tmp296, i64 1
-  %tmp298 = getelementptr inbounds float* %tmp297, i64 1
-  %tmp299 = getelementptr inbounds float* %tmp298, i64 1
-  %tmp300 = getelementptr inbounds float* %tmp299, i64 1
-  %tmp301 = getelementptr inbounds float* %tmp300, i64 1
-  %tmp302 = getelementptr inbounds float* %tmp301, i64 1
-  %tmp303 = getelementptr inbounds float* %tmp302, i64 1
-  %tmp304 = getelementptr inbounds float* %tmp303, i64 1
-  %tmp305 = getelementptr inbounds float* %tmp304, i64 1
-  %tmp306 = getelementptr inbounds float* %tmp305, i64 1
-  %tmp307 = getelementptr inbounds float* %tmp306, i64 1
-  %tmp308 = getelementptr inbounds float* %tmp307, i64 1
-  %tmp309 = getelementptr inbounds float* %tmp308, i64 1
-  %tmp310 = getelementptr inbounds float* %tmp309, i64 1
-  %tmp311 = getelementptr inbounds float* %tmp310, i64 1
-  %tmp312 = getelementptr inbounds float* %tmp311, i64 1
-  %tmp313 = getelementptr inbounds float* %tmp312, i64 1
-  %tmp314 = getelementptr inbounds float* %tmp313, i64 1
-  %tmp315 = getelementptr inbounds float* %tmp314, i64 1
-  %tmp316 = getelementptr inbounds float* %tmp315, i64 1
-  %tmp317 = getelementptr inbounds float* %tmp316, i64 1
-  %tmp318 = getelementptr inbounds float* %tmp317, i64 1
-  %tmp319 = getelementptr inbounds float* %tmp318, i64 1
-  %tmp320 = getelementptr inbounds float* %tmp319, i64 1
-  %tmp321 = getelementptr inbounds float* %tmp320, i64 1
-  %tmp322 = getelementptr inbounds float* %tmp321, i64 1
-  %tmp323 = getelementptr inbounds float* %tmp322, i64 1
-  %tmp324 = getelementptr inbounds float* %tmp323, i64 1
-  %tmp325 = getelementptr inbounds float* %tmp324, i64 1
-  %tmp326 = getelementptr inbounds float* %tmp325, i64 1
-  %tmp327 = getelementptr inbounds float* %tmp326, i64 1
-  %tmp328 = getelementptr inbounds float* %tmp327, i64 1
-  %tmp329 = getelementptr inbounds float* %tmp328, i64 1
-  %tmp330 = getelementptr inbounds float* %tmp329, i64 1
-  %tmp331 = getelementptr inbounds float* %tmp330, i64 1
-  %tmp332 = getelementptr inbounds float* %tmp331, i64 1
-  %tmp333 = getelementptr inbounds float* %tmp332, i64 1
-  %tmp334 = getelementptr inbounds float* %tmp333, i64 1
-  %tmp335 = getelementptr inbounds float* %tmp334, i64 1
-  %tmp336 = getelementptr inbounds float* %tmp335, i64 1
-  %tmp337 = getelementptr inbounds float* %tmp336, i64 1
-  %tmp338 = getelementptr inbounds float* %tmp337, i64 1
-  %tmp339 = getelementptr inbounds float* %tmp338, i64 1
-  %tmp340 = getelementptr inbounds float* %tmp339, i64 1
-  %tmp341 = getelementptr inbounds float* %tmp340, i64 1
-  %tmp342 = getelementptr inbounds float* %tmp341, i64 1
-  %tmp343 = getelementptr inbounds float* %tmp342, i64 1
-  %tmp344 = getelementptr inbounds float* %tmp343, i64 1
-  %tmp345 = getelementptr inbounds float* %tmp344, i64 1
-  %tmp346 = getelementptr inbounds float* %tmp345, i64 1
-  %tmp347 = getelementptr inbounds float* %tmp346, i64 1
-  %tmp348 = getelementptr inbounds float* %tmp347, i64 1
-  %tmp349 = getelementptr inbounds float* %tmp348, i64 1
-  %tmp350 = getelementptr inbounds float* %tmp349, i64 1
-  %tmp351 = getelementptr inbounds float* %tmp350, i64 1
-  %tmp352 = getelementptr inbounds float* %tmp351, i64 1
-  %tmp353 = getelementptr inbounds float* %tmp352, i64 1
-  %tmp354 = getelementptr inbounds float* %tmp353, i64 1
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-  %tmp1077 = getelementptr inbounds float* %tmp1076, i64 1
-  %tmp1078 = getelementptr inbounds float* %tmp1077, i64 1
-  %tmp1079 = getelementptr inbounds float* %tmp1078, i64 1
-  %tmp1080 = getelementptr inbounds float* %tmp1079, i64 1
-  %tmp1081 = getelementptr inbounds float* %tmp1080, i64 1
-  %tmp1082 = getelementptr inbounds float* %tmp1081, i64 1
-  %tmp1083 = getelementptr inbounds float* %tmp1082, i64 1
-  %tmp1084 = getelementptr inbounds float* %tmp1083, i64 1
-  %tmp1085 = getelementptr inbounds float* %tmp1084, i64 1
-  %tmp1086 = getelementptr inbounds float* %tmp1085, i64 1
-  %tmp1087 = getelementptr inbounds float* %tmp1086, i64 1
-  %tmp1088 = getelementptr inbounds float* %tmp1087, i64 1
-  %tmp1089 = getelementptr inbounds float* %tmp1088, i64 1
-  %tmp1090 = getelementptr inbounds float* %tmp1089, i64 1
-  %tmp1091 = getelementptr inbounds float* %tmp1090, i64 1
-  %tmp1092 = getelementptr inbounds float* %tmp1091, i64 1
-  %tmp1093 = getelementptr inbounds float* %tmp1092, i64 1
-  %tmp1094 = getelementptr inbounds float* %tmp1093, i64 1
-  %tmp1095 = getelementptr inbounds float* %tmp1094, i64 1
-  %tmp1096 = getelementptr inbounds float* %tmp1095, i64 1
-  %tmp1097 = getelementptr inbounds float* %tmp1096, i64 1
-  %tmp1098 = getelementptr inbounds float* %tmp1097, i64 1
-  %tmp1099 = getelementptr inbounds float* %tmp1098, i64 1
-  %tmp1100 = getelementptr inbounds float* %tmp1099, i64 1
-  %tmp1101 = getelementptr inbounds float* %tmp1100, i64 1
-  %tmp1102 = getelementptr inbounds float* %tmp1101, i64 1
-  %tmp1103 = getelementptr inbounds float* %tmp1102, i64 1
-  %tmp1104 = getelementptr inbounds float* %tmp1103, i64 1
-  %tmp1105 = getelementptr inbounds float* %tmp1104, i64 1
-  %tmp1106 = getelementptr inbounds float* %tmp1105, i64 1
-  %tmp1107 = getelementptr inbounds float* %tmp1106, i64 1
-  %tmp1108 = getelementptr inbounds float* %tmp1107, i64 1
-  %tmp1109 = getelementptr inbounds float* %tmp1108, i64 1
-  %tmp1110 = getelementptr inbounds float* %tmp1109, i64 1
-  %tmp1111 = getelementptr inbounds float* %tmp1110, i64 1
-  %tmp1112 = getelementptr inbounds float* %tmp1111, i64 1
-  %tmp1113 = getelementptr inbounds float* %tmp1112, i64 1
-  %tmp1114 = getelementptr inbounds float* %tmp1113, i64 1
-  %tmp1115 = getelementptr inbounds float* %tmp1114, i64 1
-  %tmp1116 = getelementptr inbounds float* %tmp1115, i64 1
-  %tmp1117 = getelementptr inbounds float* %tmp1116, i64 1
-  %tmp1118 = getelementptr inbounds float* %tmp1117, i64 1
-  %tmp1119 = getelementptr inbounds float* %tmp1118, i64 1
-  %tmp1120 = getelementptr inbounds float* %tmp1119, i64 1
-  %tmp1121 = getelementptr inbounds float* %tmp1120, i64 1
-  %tmp1122 = getelementptr inbounds float* %tmp1121, i64 1
-  %tmp1123 = getelementptr inbounds float* %tmp1122, i64 1
-  %tmp1124 = getelementptr inbounds float* %tmp1123, i64 1
-  %tmp1125 = getelementptr inbounds float* %tmp1124, i64 1
-  %tmp1126 = getelementptr inbounds float* %tmp1125, i64 1
-  %tmp1127 = getelementptr inbounds float* %tmp1126, i64 1
-  %tmp1128 = getelementptr inbounds float* %tmp1127, i64 1
-  %tmp1129 = getelementptr inbounds float* %tmp1128, i64 1
-  %tmp1130 = getelementptr inbounds float* %tmp1129, i64 1
-  %tmp1131 = getelementptr inbounds float* %tmp1130, i64 1
-  %tmp1132 = getelementptr inbounds float* %tmp1131, i64 1
-  %tmp1133 = getelementptr inbounds float* %tmp1132, i64 1
-  %tmp1134 = getelementptr inbounds float* %tmp1133, i64 1
-  %tmp1135 = getelementptr inbounds float* %tmp1134, i64 1
-  %tmp1136 = getelementptr inbounds float* %tmp1135, i64 1
-  %tmp1137 = getelementptr inbounds float* %tmp1136, i64 1
-  %tmp1138 = getelementptr inbounds float* %tmp1137, i64 1
-  %tmp1139 = getelementptr inbounds float* %tmp1138, i64 1
-  %tmp1140 = getelementptr inbounds float* %tmp1139, i64 1
-  %tmp1141 = getelementptr inbounds float* %tmp1140, i64 1
-  %tmp1142 = getelementptr inbounds float* %tmp1141, i64 1
-  %tmp1143 = getelementptr inbounds float* %tmp1142, i64 1
-  %tmp1144 = getelementptr inbounds float* %tmp1143, i64 1
-  %tmp1145 = getelementptr inbounds float* %tmp1144, i64 1
-  %tmp1146 = getelementptr inbounds float* %tmp1145, i64 1
-  %tmp1147 = getelementptr inbounds float* %tmp1146, i64 1
-  %tmp1148 = getelementptr inbounds float* %tmp1147, i64 1
-  %tmp1149 = getelementptr inbounds float* %tmp1148, i64 1
-  %tmp1150 = getelementptr inbounds float* %tmp1149, i64 1
-  %tmp1151 = getelementptr inbounds float* %tmp1150, i64 1
-  %tmp1152 = getelementptr inbounds float* %tmp1151, i64 1
-  %tmp1153 = getelementptr inbounds float* %tmp1152, i64 1
-  %tmp1154 = getelementptr inbounds float* %tmp1153, i64 1
-  %tmp1155 = getelementptr inbounds float* %tmp1154, i64 1
-  %tmp1156 = getelementptr inbounds float* %tmp1155, i64 1
-  %tmp1157 = getelementptr inbounds float* %tmp1156, i64 1
-  %tmp1158 = getelementptr inbounds float* %tmp1157, i64 1
-  %tmp1159 = getelementptr inbounds float* %tmp1158, i64 1
-  %tmp1160 = getelementptr inbounds float* %tmp1159, i64 1
-  %tmp1161 = getelementptr inbounds float* %tmp1160, i64 1
-  %tmp1162 = getelementptr inbounds float* %tmp1161, i64 1
-  %tmp1163 = getelementptr inbounds float* %tmp1162, i64 1
-  %tmp1164 = getelementptr inbounds float* %tmp1163, i64 1
-  %tmp1165 = getelementptr inbounds float* %tmp1164, i64 1
-  %tmp1166 = getelementptr inbounds float* %tmp1165, i64 1
-  %tmp1167 = getelementptr inbounds float* %tmp1166, i64 1
-  %tmp1168 = getelementptr inbounds float* %tmp1167, i64 1
-  %tmp1169 = getelementptr inbounds float* %tmp1168, i64 1
-  %tmp1170 = getelementptr inbounds float* %tmp1169, i64 1
-  %tmp1171 = getelementptr inbounds float* %tmp1170, i64 1
-  %tmp1172 = getelementptr inbounds float* %tmp1171, i64 1
-  %tmp1173 = getelementptr inbounds float* %tmp1172, i64 1
-  %tmp1174 = getelementptr inbounds float* %tmp1173, i64 1
-  %tmp1175 = getelementptr inbounds float* %tmp1174, i64 1
-  %tmp1176 = getelementptr inbounds float* %tmp1175, i64 1
-  %tmp1177 = getelementptr inbounds float* %tmp1176, i64 1
-  %tmp1178 = getelementptr inbounds float* %tmp1177, i64 1
-  %tmp1179 = getelementptr inbounds float* %tmp1178, i64 1
-  %tmp1180 = getelementptr inbounds float* %tmp1179, i64 1
-  %tmp1181 = getelementptr inbounds float* %tmp1180, i64 1
-  %tmp1182 = getelementptr inbounds float* %tmp1181, i64 1
-  %tmp1183 = getelementptr inbounds float* %tmp1182, i64 1
-  %tmp1184 = getelementptr inbounds float* %tmp1183, i64 1
-  %tmp1185 = getelementptr inbounds float* %tmp1184, i64 1
-  %tmp1186 = getelementptr inbounds float* %tmp1185, i64 1
-  %tmp1187 = getelementptr inbounds float* %tmp1186, i64 1
-  %tmp1188 = getelementptr inbounds float* %tmp1187, i64 1
-  %tmp1189 = getelementptr inbounds float* %tmp1188, i64 1
-  %tmp1190 = getelementptr inbounds float* %tmp1189, i64 1
-  %tmp1191 = getelementptr inbounds float* %tmp1190, i64 1
-  %tmp1192 = getelementptr inbounds float* %tmp1191, i64 1
-  %tmp1193 = getelementptr inbounds float* %tmp1192, i64 1
-  %tmp1194 = getelementptr inbounds float* %tmp1193, i64 1
-  %tmp1195 = getelementptr inbounds float* %tmp1194, i64 1
-  %tmp1196 = getelementptr inbounds float* %tmp1195, i64 1
-  %tmp1197 = getelementptr inbounds float* %tmp1196, i64 1
-  %tmp1198 = getelementptr inbounds float* %tmp1197, i64 1
-  %tmp1199 = getelementptr inbounds float* %tmp1198, i64 1
-  %tmp1200 = getelementptr inbounds float* %tmp1199, i64 1
-  %tmp1201 = getelementptr inbounds float* %tmp1200, i64 1
-  %tmp1202 = getelementptr inbounds float* %tmp1201, i64 1
-  %tmp1203 = getelementptr inbounds float* %tmp1202, i64 1
-  %tmp1204 = getelementptr inbounds float* %tmp1203, i64 1
-  %tmp1205 = getelementptr inbounds float* %tmp1204, i64 1
-  %tmp1206 = getelementptr inbounds float* %tmp1205, i64 1
-  %tmp1207 = getelementptr inbounds float* %tmp1206, i64 1
-  %tmp1208 = getelementptr inbounds float* %tmp1207, i64 1
-  %tmp1209 = getelementptr inbounds float* %tmp1208, i64 1
-  %tmp1210 = getelementptr inbounds float* %tmp1209, i64 1
-  %tmp1211 = getelementptr inbounds float* %tmp1210, i64 1
-  %tmp1212 = getelementptr inbounds float* %tmp1211, i64 1
-  %tmp1213 = getelementptr inbounds float* %tmp1212, i64 1
-  %tmp1214 = getelementptr inbounds float* %tmp1213, i64 1
-  %tmp1215 = getelementptr inbounds float* %tmp1214, i64 1
-  %tmp1216 = getelementptr inbounds float* %tmp1215, i64 1
-  %tmp1217 = getelementptr inbounds float* %tmp1216, i64 1
-  %tmp1218 = getelementptr inbounds float* %tmp1217, i64 1
-  %tmp1219 = getelementptr inbounds float* %tmp1218, i64 1
-  %tmp1220 = getelementptr inbounds float* %tmp1219, i64 1
-  %tmp1221 = getelementptr inbounds float* %tmp1220, i64 1
-  %tmp1222 = getelementptr inbounds float* %tmp1221, i64 1
-  %tmp1223 = getelementptr inbounds float* %tmp1222, i64 1
-  %tmp1224 = getelementptr inbounds float* %tmp1223, i64 1
-  %tmp1225 = getelementptr inbounds float* %tmp1224, i64 1
-  %tmp1226 = getelementptr inbounds float* %tmp1225, i64 1
-  %tmp1227 = getelementptr inbounds float* %tmp1226, i64 1
-  %tmp1228 = getelementptr inbounds float* %tmp1227, i64 1
-  %tmp1229 = getelementptr inbounds float* %tmp1228, i64 1
-  %tmp1230 = getelementptr inbounds float* %tmp1229, i64 1
-  %tmp1231 = getelementptr inbounds float* %tmp1230, i64 1
-  %tmp1232 = getelementptr inbounds float* %tmp1231, i64 1
-  %tmp1233 = getelementptr inbounds float* %tmp1232, i64 1
-  %tmp1234 = getelementptr inbounds float* %tmp1233, i64 1
-  %tmp1235 = getelementptr inbounds float* %tmp1234, i64 1
-  %tmp1236 = getelementptr inbounds float* %tmp1235, i64 1
-  %tmp1237 = getelementptr inbounds float* %tmp1236, i64 1
-  %tmp1238 = getelementptr inbounds float* %tmp1237, i64 1
-  %tmp1239 = getelementptr inbounds float* %tmp1238, i64 1
-  %tmp1240 = getelementptr inbounds float* %tmp1239, i64 1
-  %tmp1241 = getelementptr inbounds float* %tmp1240, i64 1
-  %tmp1242 = getelementptr inbounds float* %tmp1241, i64 1
-  %tmp1243 = getelementptr inbounds float* %tmp1242, i64 1
-  %tmp1244 = getelementptr inbounds float* %tmp1243, i64 1
-  %tmp1245 = getelementptr inbounds float* %tmp1244, i64 1
-  %tmp1246 = getelementptr inbounds float* %tmp1245, i64 1
-  %tmp1247 = getelementptr inbounds float* %tmp1246, i64 1
-  %tmp1248 = getelementptr inbounds float* %tmp1247, i64 1
-  %tmp1249 = getelementptr inbounds float* %tmp1248, i64 1
-  %tmp1250 = getelementptr inbounds float* %tmp1249, i64 1
-  %tmp1251 = getelementptr inbounds float* %tmp1250, i64 1
-  %tmp1252 = getelementptr inbounds float* %tmp1251, i64 1
-  %tmp1253 = getelementptr inbounds float* %tmp1252, i64 1
-  %tmp1254 = getelementptr inbounds float* %tmp1253, i64 1
-  %tmp1255 = getelementptr inbounds float* %tmp1254, i64 1
-  %tmp1256 = getelementptr inbounds float* %tmp1255, i64 1
-  %tmp1257 = getelementptr inbounds float* %tmp1256, i64 1
-  %tmp1258 = getelementptr inbounds float* %tmp1257, i64 1
-  %tmp1259 = getelementptr inbounds float* %tmp1258, i64 1
-  %tmp1260 = getelementptr inbounds float* %tmp1259, i64 1
-  %tmp1261 = getelementptr inbounds float* %tmp1260, i64 1
-  %tmp1262 = getelementptr inbounds float* %tmp1261, i64 1
-  %tmp1263 = getelementptr inbounds float* %tmp1262, i64 1
-  %tmp1264 = getelementptr inbounds float* %tmp1263, i64 1
-  %tmp1265 = getelementptr inbounds float* %tmp1264, i64 1
-  %tmp1266 = getelementptr inbounds float* %tmp1265, i64 1
-  %tmp1267 = getelementptr inbounds float* %tmp1266, i64 1
-  %tmp1268 = getelementptr inbounds float* %tmp1267, i64 1
-  %tmp1269 = getelementptr inbounds float* %tmp1268, i64 1
-  %tmp1270 = getelementptr inbounds float* %tmp1269, i64 1
-  %tmp1271 = getelementptr inbounds float* %tmp1270, i64 1
-  %tmp1272 = getelementptr inbounds float* %tmp1271, i64 1
-  %tmp1273 = getelementptr inbounds float* %tmp1272, i64 1
-  %tmp1274 = getelementptr inbounds float* %tmp1273, i64 1
-  %tmp1275 = getelementptr inbounds float* %tmp1274, i64 1
-  %tmp1276 = getelementptr inbounds float* %tmp1275, i64 1
-  %tmp1277 = getelementptr inbounds float* %tmp1276, i64 1
-  %tmp1278 = getelementptr inbounds float* %tmp1277, i64 1
-  %tmp1279 = getelementptr inbounds float* %tmp1278, i64 1
-  %tmp1280 = getelementptr inbounds float* %tmp1279, i64 1
-  %tmp1281 = getelementptr inbounds float* %tmp1280, i64 1
-  %tmp1282 = getelementptr inbounds float* %tmp1281, i64 1
-  %tmp1283 = getelementptr inbounds float* %tmp1282, i64 1
-  %tmp1284 = getelementptr inbounds float* %tmp1283, i64 1
-  %tmp1285 = getelementptr inbounds float* %tmp1284, i64 1
-  %tmp1286 = getelementptr inbounds float* %tmp1285, i64 1
-  %tmp1287 = getelementptr inbounds float* %tmp1286, i64 1
-  %tmp1288 = getelementptr inbounds float* %tmp1287, i64 1
-  %tmp1289 = getelementptr inbounds float* %tmp1288, i64 1
-  %tmp1290 = getelementptr inbounds float* %tmp1289, i64 1
-  %tmp1291 = getelementptr inbounds float* %tmp1290, i64 1
-  %tmp1292 = getelementptr inbounds float* %tmp1291, i64 1
-  %tmp1293 = getelementptr inbounds float* %tmp1292, i64 1
-  %tmp1294 = getelementptr inbounds float* %tmp1293, i64 1
-  %tmp1295 = getelementptr inbounds float* %tmp1294, i64 1
-  %tmp1296 = getelementptr inbounds float* %tmp1295, i64 1
-  %tmp1297 = getelementptr inbounds float* %tmp1296, i64 1
-  %tmp1298 = getelementptr inbounds float* %tmp1297, i64 1
-  %tmp1299 = getelementptr inbounds float* %tmp1298, i64 1
-  %tmp1300 = getelementptr inbounds float* %tmp1299, i64 1
-  %tmp1301 = getelementptr inbounds float* %tmp1300, i64 1
-  %tmp1302 = getelementptr inbounds float* %tmp1301, i64 1
-  %tmp1303 = getelementptr inbounds float* %tmp1302, i64 1
-  %tmp1304 = getelementptr inbounds float* %tmp1303, i64 1
-  %tmp1305 = getelementptr inbounds float* %tmp1304, i64 1
-  %tmp1306 = getelementptr inbounds float* %tmp1305, i64 1
-  %tmp1307 = getelementptr inbounds float* %tmp1306, i64 1
-  %tmp1308 = getelementptr inbounds float* %tmp1307, i64 1
-  %tmp1309 = getelementptr inbounds float* %tmp1308, i64 1
-  %tmp1310 = getelementptr inbounds float* %tmp1309, i64 1
-  %tmp1311 = getelementptr inbounds float* %tmp1310, i64 1
-  %tmp1312 = getelementptr inbounds float* %tmp1311, i64 1
-  %tmp1313 = getelementptr inbounds float* %tmp1312, i64 1
-  %tmp1314 = getelementptr inbounds float* %tmp1313, i64 1
-  %tmp1315 = getelementptr inbounds float* %tmp1314, i64 1
-  %tmp1316 = getelementptr inbounds float* %tmp1315, i64 1
-  %tmp1317 = getelementptr inbounds float* %tmp1316, i64 1
-  %tmp1318 = getelementptr inbounds float* %tmp1317, i64 1
-  %tmp1319 = getelementptr inbounds float* %tmp1318, i64 1
-  %tmp1320 = getelementptr inbounds float* %tmp1319, i64 1
-  %tmp1321 = getelementptr inbounds float* %tmp1320, i64 1
-  %tmp1322 = getelementptr inbounds float* %tmp1321, i64 1
-  %tmp1323 = getelementptr inbounds float* %tmp1322, i64 1
-  %tmp1324 = getelementptr inbounds float* %tmp1323, i64 1
-  %tmp1325 = getelementptr inbounds float* %tmp1324, i64 1
-  %tmp1326 = getelementptr inbounds float* %tmp1325, i64 1
-  %tmp1327 = getelementptr inbounds float* %tmp1326, i64 1
-  %tmp1328 = getelementptr inbounds float* %tmp1327, i64 1
-  %tmp1329 = getelementptr inbounds float* %tmp1328, i64 1
-  %tmp1330 = getelementptr inbounds float* %tmp1329, i64 1
-  %tmp1331 = getelementptr inbounds float* %tmp1330, i64 1
-  %tmp1332 = getelementptr inbounds float* %tmp1331, i64 1
-  %tmp1333 = getelementptr inbounds float* %tmp1332, i64 1
-  %tmp1334 = getelementptr inbounds float* %tmp1333, i64 1
-  %tmp1335 = getelementptr inbounds float* %tmp1334, i64 1
-  %tmp1336 = getelementptr inbounds float* %tmp1335, i64 1
-  %tmp1337 = getelementptr inbounds float* %tmp1336, i64 1
-  %tmp1338 = getelementptr inbounds float* %tmp1337, i64 1
-  %tmp1339 = getelementptr inbounds float* %tmp1338, i64 1
-  %tmp1340 = getelementptr inbounds float* %tmp1339, i64 1
-  %tmp1341 = getelementptr inbounds float* %tmp1340, i64 1
-  %tmp1342 = getelementptr inbounds float* %tmp1341, i64 1
-  %tmp1343 = getelementptr inbounds float* %tmp1342, i64 1
-  %tmp1344 = getelementptr inbounds float* %tmp1343, i64 1
-  %tmp1345 = getelementptr inbounds float* %tmp1344, i64 1
-  %tmp1346 = getelementptr inbounds float* %tmp1345, i64 1
-  %tmp1347 = getelementptr inbounds float* %tmp1346, i64 1
-  %tmp1348 = getelementptr inbounds float* %tmp1347, i64 1
-  %tmp1349 = getelementptr inbounds float* %tmp1348, i64 1
-  %tmp1350 = getelementptr inbounds float* %tmp1349, i64 1
-  %tmp1351 = getelementptr inbounds float* %tmp1350, i64 1
-  %tmp1352 = getelementptr inbounds float* %tmp1351, i64 1
-  %tmp1353 = getelementptr inbounds float* %tmp1352, i64 1
-  %tmp1354 = getelementptr inbounds float* %tmp1353, i64 1
-  %tmp1355 = getelementptr inbounds float* %tmp1354, i64 1
-  %tmp1356 = getelementptr inbounds float* %tmp1355, i64 1
-  %tmp1357 = getelementptr inbounds float* %tmp1356, i64 1
-  %tmp1358 = getelementptr inbounds float* %tmp1357, i64 1
-  %tmp1359 = getelementptr inbounds float* %tmp1358, i64 1
-  %tmp1360 = getelementptr inbounds float* %tmp1359, i64 1
-  %tmp1361 = getelementptr inbounds float* %tmp1360, i64 1
-  %tmp1362 = getelementptr inbounds float* %tmp1361, i64 1
-  %tmp1363 = getelementptr inbounds float* %tmp1362, i64 1
-  %tmp1364 = getelementptr inbounds float* %tmp1363, i64 1
-  %tmp1365 = getelementptr inbounds float* %tmp1364, i64 1
-  %tmp1366 = getelementptr inbounds float* %tmp1365, i64 1
-  %tmp1367 = getelementptr inbounds float* %tmp1366, i64 1
-  %tmp1368 = getelementptr inbounds float* %tmp1367, i64 1
-  %tmp1369 = getelementptr inbounds float* %tmp1368, i64 1
-  %tmp1370 = getelementptr inbounds float* %tmp1369, i64 1
-  %tmp1371 = getelementptr inbounds float* %tmp1370, i64 1
-  %tmp1372 = getelementptr inbounds float* %tmp1371, i64 1
-  %tmp1373 = getelementptr inbounds float* %tmp1372, i64 1
-  %tmp1374 = getelementptr inbounds float* %tmp1373, i64 1
-  %tmp1375 = getelementptr inbounds float* %tmp1374, i64 1
-  %tmp1376 = getelementptr inbounds float* %tmp1375, i64 1
-  %tmp1377 = getelementptr inbounds float* %tmp1376, i64 1
-  %tmp1378 = getelementptr inbounds float* %tmp1377, i64 1
-  %tmp1379 = getelementptr inbounds float* %tmp1378, i64 1
-  %tmp1380 = getelementptr inbounds float* %tmp1379, i64 1
-  %tmp1381 = getelementptr inbounds float* %tmp1380, i64 1
-  %tmp1382 = getelementptr inbounds float* %tmp1381, i64 1
-  %tmp1383 = getelementptr inbounds float* %tmp1382, i64 1
-  %tmp1384 = getelementptr inbounds float* %tmp1383, i64 1
-  %tmp1385 = getelementptr inbounds float* %tmp1384, i64 1
-  %tmp1386 = getelementptr inbounds float* %tmp1385, i64 1
-  %tmp1387 = getelementptr inbounds float* %tmp1386, i64 1
-  %tmp1388 = getelementptr inbounds float* %tmp1387, i64 1
-  %tmp1389 = getelementptr inbounds float* %tmp1388, i64 1
-  %tmp1390 = getelementptr inbounds float* %tmp1389, i64 1
-  %tmp1391 = getelementptr inbounds float* %tmp1390, i64 1
-  %tmp1392 = getelementptr inbounds float* %tmp1391, i64 1
-  %tmp1393 = getelementptr inbounds float* %tmp1392, i64 1
-  %tmp1394 = getelementptr inbounds float* %tmp1393, i64 1
-  %tmp1395 = getelementptr inbounds float* %tmp1394, i64 1
-  %tmp1396 = getelementptr inbounds float* %tmp1395, i64 1
-  %tmp1397 = getelementptr inbounds float* %tmp1396, i64 1
-  %tmp1398 = getelementptr inbounds float* %tmp1397, i64 1
-  %tmp1399 = getelementptr inbounds float* %tmp1398, i64 1
-  %tmp1400 = getelementptr inbounds float* %tmp1399, i64 1
-  %tmp1401 = getelementptr inbounds float* %tmp1400, i64 1
-  %tmp1402 = getelementptr inbounds float* %tmp1401, i64 1
-  %tmp1403 = getelementptr inbounds float* %tmp1402, i64 1
-  %tmp1404 = getelementptr inbounds float* %tmp1403, i64 1
-  %tmp1405 = getelementptr inbounds float* %tmp1404, i64 1
-  %tmp1406 = getelementptr inbounds float* %tmp1405, i64 1
-  %tmp1407 = getelementptr inbounds float* %tmp1406, i64 1
-  %tmp1408 = getelementptr inbounds float* %tmp1407, i64 1
-  %tmp1409 = getelementptr inbounds float* %tmp1408, i64 1
-  %tmp1410 = getelementptr inbounds float* %tmp1409, i64 1
-  %tmp1411 = getelementptr inbounds float* %tmp1410, i64 1
-  %tmp1412 = getelementptr inbounds float* %tmp1411, i64 1
-  %tmp1413 = getelementptr inbounds float* %tmp1412, i64 1
-  %tmp1414 = getelementptr inbounds float* %tmp1413, i64 1
-  %tmp1415 = getelementptr inbounds float* %tmp1414, i64 1
-  %tmp1416 = getelementptr inbounds float* %tmp1415, i64 1
-  %tmp1417 = getelementptr inbounds float* %tmp1416, i64 1
-  %tmp1418 = getelementptr inbounds float* %tmp1417, i64 1
-  %tmp1419 = getelementptr inbounds float* %tmp1418, i64 1
-  %tmp1420 = getelementptr inbounds float* %tmp1419, i64 1
-  %tmp1421 = getelementptr inbounds float* %tmp1420, i64 1
-  %tmp1422 = getelementptr inbounds float* %tmp1421, i64 1
-  %tmp1423 = getelementptr inbounds float* %tmp1422, i64 1
-  %tmp1424 = getelementptr inbounds float* %tmp1423, i64 1
-  %tmp1425 = getelementptr inbounds float* %tmp1424, i64 1
-  %tmp1426 = getelementptr inbounds float* %tmp1425, i64 1
-  %tmp1427 = getelementptr inbounds float* %tmp1426, i64 1
-  %tmp1428 = getelementptr inbounds float* %tmp1427, i64 1
-  %tmp1429 = getelementptr inbounds float* %tmp1428, i64 1
-  %tmp1430 = getelementptr inbounds float* %tmp1429, i64 1
-  %tmp1431 = getelementptr inbounds float* %tmp1430, i64 1
-  %tmp1432 = getelementptr inbounds float* %tmp1431, i64 1
-  %tmp1433 = getelementptr inbounds float* %tmp1432, i64 1
-  %tmp1434 = getelementptr inbounds float* %tmp1433, i64 1
-  %tmp1435 = getelementptr inbounds float* %tmp1434, i64 1
-  %tmp1436 = getelementptr inbounds float* %tmp1435, i64 1
-  %tmp1437 = getelementptr inbounds float* %tmp1436, i64 1
-  %tmp1438 = getelementptr inbounds float* %tmp1437, i64 1
-  %tmp1439 = getelementptr inbounds float* %tmp1438, i64 1
-  %tmp1440 = getelementptr inbounds float* %tmp1439, i64 1
-  %tmp1441 = getelementptr inbounds float* %tmp1440, i64 1
-  %tmp1442 = getelementptr inbounds float* %tmp1441, i64 1
-  %tmp1443 = getelementptr inbounds float* %tmp1442, i64 1
-  %tmp1444 = getelementptr inbounds float* %tmp1443, i64 1
-  %tmp1445 = getelementptr inbounds float* %tmp1444, i64 1
-  %tmp1446 = getelementptr inbounds float* %tmp1445, i64 1
-  %tmp1447 = getelementptr inbounds float* %tmp1446, i64 1
-  %tmp1448 = getelementptr inbounds float* %tmp1447, i64 1
-  %tmp1449 = getelementptr inbounds float* %tmp1448, i64 1
-  %tmp1450 = getelementptr inbounds float* %tmp1449, i64 1
-  %tmp1451 = getelementptr inbounds float* %tmp1450, i64 1
-  %tmp1452 = getelementptr inbounds float* %tmp1451, i64 1
-  %tmp1453 = getelementptr inbounds float* %tmp1452, i64 1
-  %tmp1454 = getelementptr inbounds float* %tmp1453, i64 1
-  %tmp1455 = getelementptr inbounds float* %tmp1454, i64 1
-  %tmp1456 = getelementptr inbounds float* %tmp1455, i64 1
-  %tmp1457 = getelementptr inbounds float* %tmp1456, i64 1
-  %tmp1458 = getelementptr inbounds float* %tmp1457, i64 1
-  %tmp1459 = getelementptr inbounds float* %tmp1458, i64 1
-  %tmp1460 = getelementptr inbounds float* %tmp1459, i64 1
-  %tmp1461 = getelementptr inbounds float* %tmp1460, i64 1
-  %tmp1462 = getelementptr inbounds float* %tmp1461, i64 1
-  %tmp1463 = getelementptr inbounds float* %tmp1462, i64 1
-  %tmp1464 = getelementptr inbounds float* %tmp1463, i64 1
-  %tmp1465 = getelementptr inbounds float* %tmp1464, i64 1
-  %tmp1466 = getelementptr inbounds float* %tmp1465, i64 1
-  %tmp1467 = getelementptr inbounds float* %tmp1466, i64 1
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-  %tmp1470 = getelementptr inbounds float* %tmp1469, i64 1
-  %tmp1471 = getelementptr inbounds float* %tmp1470, i64 1
-  %tmp1472 = getelementptr inbounds float* %tmp1471, i64 1
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-  %tmp1475 = getelementptr inbounds float* %tmp1474, i64 1
-  %tmp1476 = getelementptr inbounds float* %tmp1475, i64 1
-  %tmp1477 = getelementptr inbounds float* %tmp1476, i64 1
-  %tmp1478 = getelementptr inbounds float* %tmp1477, i64 1
-  %tmp1479 = getelementptr inbounds float* %tmp1478, i64 1
-  %tmp1480 = getelementptr inbounds float* %tmp1479, i64 1
-  %tmp1481 = getelementptr inbounds float* %tmp1480, i64 1
-  %tmp1482 = getelementptr inbounds float* %tmp1481, i64 1
-  %tmp1483 = getelementptr inbounds float* %tmp1482, i64 1
-  %tmp1484 = getelementptr inbounds float* %tmp1483, i64 1
-  %tmp1485 = getelementptr inbounds float* %tmp1484, i64 1
-  %tmp1486 = getelementptr inbounds float* %tmp1485, i64 1
-  %tmp1487 = getelementptr inbounds float* %tmp1486, i64 1
-  %tmp1488 = getelementptr inbounds float* %tmp1487, i64 1
-  %tmp1489 = getelementptr inbounds float* %tmp1488, i64 1
-  %tmp1490 = getelementptr inbounds float* %tmp1489, i64 1
-  %tmp1491 = getelementptr inbounds float* %tmp1490, i64 1
-  %tmp1492 = getelementptr inbounds float* %tmp1491, i64 1
-  %tmp1493 = getelementptr inbounds float* %tmp1492, i64 1
-  %tmp1494 = getelementptr inbounds float* %tmp1493, i64 1
-  %tmp1495 = getelementptr inbounds float* %tmp1494, i64 1
-  %tmp1496 = getelementptr inbounds float* %tmp1495, i64 1
-  %tmp1497 = getelementptr inbounds float* %tmp1496, i64 1
-  %tmp1498 = getelementptr inbounds float* %tmp1497, i64 1
-  %tmp1499 = getelementptr inbounds float* %tmp1498, i64 1
-  %tmp1500 = getelementptr inbounds float* %tmp1499, i64 1
-  %tmp1501 = getelementptr inbounds float* %tmp1500, i64 1
-  %tmp1502 = getelementptr inbounds float* %tmp1501, i64 1
-  %tmp1503 = getelementptr inbounds float* %tmp1502, i64 1
-  %tmp1504 = getelementptr inbounds float* %tmp1503, i64 1
-  %tmp1505 = getelementptr inbounds float* %tmp1504, i64 1
-  %tmp1506 = getelementptr inbounds float* %tmp1505, i64 1
-  %tmp1507 = getelementptr inbounds float* %tmp1506, i64 1
-  %tmp1508 = getelementptr inbounds float* %tmp1507, i64 1
-  %tmp1509 = getelementptr inbounds float* %tmp1508, i64 1
-  %tmp1510 = getelementptr inbounds float* %tmp1509, i64 1
-  %tmp1511 = getelementptr inbounds float* %tmp1510, i64 1
-  %tmp1512 = getelementptr inbounds float* %tmp1511, i64 1
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-  %tmp1515 = getelementptr inbounds float* %tmp1514, i64 1
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-  %tmp1517 = getelementptr inbounds float* %tmp1516, i64 1
-  %tmp1518 = getelementptr inbounds float* %tmp1517, i64 1
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-  %tmp1520 = getelementptr inbounds float* %tmp1519, i64 1
-  %tmp1521 = getelementptr inbounds float* %tmp1520, i64 1
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-  %tmp1525 = getelementptr inbounds float* %tmp1524, i64 1
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-  %tmp1538 = getelementptr inbounds float* %tmp1537, i64 1
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-  %tmp1586 = getelementptr inbounds float* %tmp1585, i64 1
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-  %tmp1599 = getelementptr inbounds float* %tmp1598, i64 1
-  %tmp1600 = getelementptr inbounds float* %tmp1599, i64 1
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-  %tmp2101 = getelementptr inbounds float* %tmp2100, i64 1
-  %tmp2102 = getelementptr inbounds float* %tmp2101, i64 1
-  %tmp2103 = getelementptr inbounds float* %tmp2102, i64 1
-  %tmp2104 = getelementptr inbounds float* %tmp2103, i64 1
-  %tmp2105 = getelementptr inbounds float* %tmp2104, i64 1
-  %tmp2106 = getelementptr inbounds float* %tmp2105, i64 1
-  %tmp2107 = getelementptr inbounds float* %tmp2106, i64 1
-  %tmp2108 = getelementptr inbounds float* %tmp2107, i64 1
-  %tmp2109 = getelementptr inbounds float* %tmp2108, i64 1
-  %tmp2110 = getelementptr inbounds float* %tmp2109, i64 1
-  %tmp2111 = getelementptr inbounds float* %tmp2110, i64 1
-  %tmp2112 = getelementptr inbounds float* %tmp2111, i64 1
-  %tmp2113 = getelementptr inbounds float* %tmp2112, i64 1
-  %tmp2114 = getelementptr inbounds float* %tmp2113, i64 1
-  %tmp2115 = getelementptr inbounds float* %tmp2114, i64 1
-  %tmp2116 = getelementptr inbounds float* %tmp2115, i64 1
-  %tmp2117 = getelementptr inbounds float* %tmp2116, i64 1
-  %tmp2118 = getelementptr inbounds float* %tmp2117, i64 1
-  %tmp2119 = getelementptr inbounds float* %tmp2118, i64 1
-  %tmp2120 = getelementptr inbounds float* %tmp2119, i64 1
-  %tmp2121 = getelementptr inbounds float* %tmp2120, i64 1
-  %tmp2122 = getelementptr inbounds float* %tmp2121, i64 1
-  %tmp2123 = getelementptr inbounds float* %tmp2122, i64 1
-  %tmp2124 = getelementptr inbounds float* %tmp2123, i64 1
-  %tmp2125 = getelementptr inbounds float* %tmp2124, i64 1
-  %tmp2126 = getelementptr inbounds float* %tmp2125, i64 1
-  %tmp2127 = getelementptr inbounds float* %tmp2126, i64 1
-  %tmp2128 = getelementptr inbounds float* %tmp2127, i64 1
-  %tmp2129 = getelementptr inbounds float* %tmp2128, i64 1
-  %tmp2130 = getelementptr inbounds float* %tmp2129, i64 1
-  %tmp2131 = getelementptr inbounds float* %tmp2130, i64 1
-  %tmp2132 = getelementptr inbounds float* %tmp2131, i64 1
-  %tmp2133 = getelementptr inbounds float* %tmp2132, i64 1
-  %tmp2134 = getelementptr inbounds float* %tmp2133, i64 1
-  %tmp2135 = getelementptr inbounds float* %tmp2134, i64 1
-  %tmp2136 = getelementptr inbounds float* %tmp2135, i64 1
-  %tmp2137 = getelementptr inbounds float* %tmp2136, i64 1
-  %tmp2138 = getelementptr inbounds float* %tmp2137, i64 1
-  %tmp2139 = getelementptr inbounds float* %tmp2138, i64 1
-  %tmp2140 = getelementptr inbounds float* %tmp2139, i64 1
-  %tmp2141 = getelementptr inbounds float* %tmp2140, i64 1
-  %tmp2142 = getelementptr inbounds float* %tmp2141, i64 1
-  %tmp2143 = getelementptr inbounds float* %tmp2142, i64 1
-  %tmp2144 = getelementptr inbounds float* %tmp2143, i64 1
-  %tmp2145 = getelementptr inbounds float* %tmp2144, i64 1
-  %tmp2146 = getelementptr inbounds float* %tmp2145, i64 1
-  %tmp2147 = getelementptr inbounds float* %tmp2146, i64 1
-  %tmp2148 = getelementptr inbounds float* %tmp2147, i64 1
-  %tmp2149 = getelementptr inbounds float* %tmp2148, i64 1
-  %tmp2150 = getelementptr inbounds float* %tmp2149, i64 1
-  %tmp2151 = getelementptr inbounds float* %tmp2150, i64 1
-  %tmp2152 = getelementptr inbounds float* %tmp2151, i64 1
-  %tmp2153 = getelementptr inbounds float* %tmp2152, i64 1
-  %tmp2154 = getelementptr inbounds float* %tmp2153, i64 1
-  %tmp2155 = getelementptr inbounds float* %tmp2154, i64 1
-  %tmp2156 = getelementptr inbounds float* %tmp2155, i64 1
-  %tmp2157 = getelementptr inbounds float* %tmp2156, i64 1
-  %tmp2158 = getelementptr inbounds float* %tmp2157, i64 1
-  %tmp2159 = getelementptr inbounds float* %tmp2158, i64 1
-  %tmp2160 = getelementptr inbounds float* %tmp2159, i64 1
-  %tmp2161 = getelementptr inbounds float* %tmp2160, i64 1
-  %tmp2162 = getelementptr inbounds float* %tmp2161, i64 1
-  %tmp2163 = getelementptr inbounds float* %tmp2162, i64 1
-  %tmp2164 = getelementptr inbounds float* %tmp2163, i64 1
-  %tmp2165 = getelementptr inbounds float* %tmp2164, i64 1
-  %tmp2166 = getelementptr inbounds float* %tmp2165, i64 1
-  %tmp2167 = getelementptr inbounds float* %tmp2166, i64 1
-  %tmp2168 = getelementptr inbounds float* %tmp2167, i64 1
-  %tmp2169 = getelementptr inbounds float* %tmp2168, i64 1
-  %tmp2170 = getelementptr inbounds float* %tmp2169, i64 1
-  %tmp2171 = getelementptr inbounds float* %tmp2170, i64 1
-  %tmp2172 = getelementptr inbounds float* %tmp2171, i64 1
-  %tmp2173 = getelementptr inbounds float* %tmp2172, i64 1
-  %tmp2174 = getelementptr inbounds float* %tmp2173, i64 1
-  %tmp2175 = getelementptr inbounds float* %tmp2174, i64 1
-  %tmp2176 = getelementptr inbounds float* %tmp2175, i64 1
-  %tmp2177 = getelementptr inbounds float* %tmp2176, i64 1
-  %tmp2178 = getelementptr inbounds float* %tmp2177, i64 1
-  %tmp2179 = getelementptr inbounds float* %tmp2178, i64 1
-  %tmp2180 = getelementptr inbounds float* %tmp2179, i64 1
-  %tmp2181 = getelementptr inbounds float* %tmp2180, i64 1
-  %tmp2182 = getelementptr inbounds float* %tmp2181, i64 1
-  %tmp2183 = getelementptr inbounds float* %tmp2182, i64 1
-  %tmp2184 = getelementptr inbounds float* %tmp2183, i64 1
-  %tmp2185 = getelementptr inbounds float* %tmp2184, i64 1
-  %tmp2186 = getelementptr inbounds float* %tmp2185, i64 1
-  %tmp2187 = getelementptr inbounds float* %tmp2186, i64 1
-  %tmp2188 = getelementptr inbounds float* %tmp2187, i64 1
-  %tmp2189 = getelementptr inbounds float* %tmp2188, i64 1
-  %tmp2190 = getelementptr inbounds float* %tmp2189, i64 1
-  %tmp2191 = getelementptr inbounds float* %tmp2190, i64 1
-  %tmp2192 = getelementptr inbounds float* %tmp2191, i64 1
-  %tmp2193 = getelementptr inbounds float* %tmp2192, i64 1
-  %tmp2194 = getelementptr inbounds float* %tmp2193, i64 1
-  %tmp2195 = getelementptr inbounds float* %tmp2194, i64 1
-  %tmp2196 = getelementptr inbounds float* %tmp2195, i64 1
-  %tmp2197 = getelementptr inbounds float* %tmp2196, i64 1
-  %tmp2198 = getelementptr inbounds float* %tmp2197, i64 1
-  %tmp2199 = getelementptr inbounds float* %tmp2198, i64 1
-  %tmp2200 = getelementptr inbounds float* %tmp2199, i64 1
-  %tmp2201 = getelementptr inbounds float* %tmp2200, i64 1
-  %tmp2202 = getelementptr inbounds float* %tmp2201, i64 1
-  %tmp2203 = getelementptr inbounds float* %tmp2202, i64 1
-  %tmp2204 = getelementptr inbounds float* %tmp2203, i64 1
-  %tmp2205 = getelementptr inbounds float* %tmp2204, i64 1
-  %tmp2206 = getelementptr inbounds float* %tmp2205, i64 1
-  %tmp2207 = getelementptr inbounds float* %tmp2206, i64 1
-  %tmp2208 = getelementptr inbounds float* %tmp2207, i64 1
-  %tmp2209 = getelementptr inbounds float* %tmp2208, i64 1
-  %tmp2210 = getelementptr inbounds float* %tmp2209, i64 1
-  %tmp2211 = getelementptr inbounds float* %tmp2210, i64 1
-  %tmp2212 = getelementptr inbounds float* %tmp2211, i64 1
-  %tmp2213 = getelementptr inbounds float* %tmp2212, i64 1
-  %tmp2214 = getelementptr inbounds float* %tmp2213, i64 1
-  %tmp2215 = getelementptr inbounds float* %tmp2214, i64 1
-  %tmp2216 = getelementptr inbounds float* %tmp2215, i64 1
-  %tmp2217 = getelementptr inbounds float* %tmp2216, i64 1
-  %tmp2218 = getelementptr inbounds float* %tmp2217, i64 1
-  %tmp2219 = getelementptr inbounds float* %tmp2218, i64 1
-  %tmp2220 = getelementptr inbounds float* %tmp2219, i64 1
-  %tmp2221 = getelementptr inbounds float* %tmp2220, i64 1
-  %tmp2222 = getelementptr inbounds float* %tmp2221, i64 1
-  %tmp2223 = getelementptr inbounds float* %tmp2222, i64 1
-  %tmp2224 = getelementptr inbounds float* %tmp2223, i64 1
-  %tmp2225 = getelementptr inbounds float* %tmp2224, i64 1
-  %tmp2226 = getelementptr inbounds float* %tmp2225, i64 1
-  %tmp2227 = getelementptr inbounds float* %tmp2226, i64 1
-  %tmp2228 = getelementptr inbounds float* %tmp2227, i64 1
-  %tmp2229 = getelementptr inbounds float* %tmp2228, i64 1
-  %tmp2230 = getelementptr inbounds float* %tmp2229, i64 1
-  %tmp2231 = getelementptr inbounds float* %tmp2230, i64 1
-  %tmp2232 = getelementptr inbounds float* %tmp2231, i64 1
-  %tmp2233 = getelementptr inbounds float* %tmp2232, i64 1
-  %tmp2234 = getelementptr inbounds float* %tmp2233, i64 1
-  %tmp2235 = getelementptr inbounds float* %tmp2234, i64 1
-  %tmp2236 = getelementptr inbounds float* %tmp2235, i64 1
-  %tmp2237 = getelementptr inbounds float* %tmp2236, i64 1
-  %tmp2238 = getelementptr inbounds float* %tmp2237, i64 1
-  %tmp2239 = getelementptr inbounds float* %tmp2238, i64 1
-  %tmp2240 = getelementptr inbounds float* %tmp2239, i64 1
-  %tmp2241 = getelementptr inbounds float* %tmp2240, i64 1
-  %tmp2242 = getelementptr inbounds float* %tmp2241, i64 1
-  %tmp2243 = getelementptr inbounds float* %tmp2242, i64 1
-  %tmp2244 = getelementptr inbounds float* %tmp2243, i64 1
-  %tmp2245 = getelementptr inbounds float* %tmp2244, i64 1
-  %tmp2246 = getelementptr inbounds float* %tmp2245, i64 1
-  %tmp2247 = getelementptr inbounds float* %tmp2246, i64 1
-  %tmp2248 = getelementptr inbounds float* %tmp2247, i64 1
-  %tmp2249 = getelementptr inbounds float* %tmp2248, i64 1
-  %tmp2250 = getelementptr inbounds float* %tmp2249, i64 1
-  %tmp2251 = getelementptr inbounds float* %tmp2250, i64 1
-  %tmp2252 = getelementptr inbounds float* %tmp2251, i64 1
-  %tmp2253 = getelementptr inbounds float* %tmp2252, i64 1
-  %tmp2254 = getelementptr inbounds float* %tmp2253, i64 1
-  %tmp2255 = getelementptr inbounds float* %tmp2254, i64 1
-  %tmp2256 = getelementptr inbounds float* %tmp2255, i64 1
-  %tmp2257 = getelementptr inbounds float* %tmp2256, i64 1
-  %tmp2258 = getelementptr inbounds float* %tmp2257, i64 1
-  %tmp2259 = getelementptr inbounds float* %tmp2258, i64 1
-  %tmp2260 = getelementptr inbounds float* %tmp2259, i64 1
-  %tmp2261 = getelementptr inbounds float* %tmp2260, i64 1
-  %tmp2262 = getelementptr inbounds float* %tmp2261, i64 1
-  %tmp2263 = getelementptr inbounds float* %tmp2262, i64 1
-  %tmp2264 = getelementptr inbounds float* %tmp2263, i64 1
-  %tmp2265 = getelementptr inbounds float* %tmp2264, i64 1
-  %tmp2266 = getelementptr inbounds float* %tmp2265, i64 1
-  %tmp2267 = getelementptr inbounds float* %tmp2266, i64 1
-  %tmp2268 = getelementptr inbounds float* %tmp2267, i64 1
-  %tmp2269 = getelementptr inbounds float* %tmp2268, i64 1
-  %tmp2270 = getelementptr inbounds float* %tmp2269, i64 1
-  %tmp2271 = getelementptr inbounds float* %tmp2270, i64 1
-  %tmp2272 = getelementptr inbounds float* %tmp2271, i64 1
-  %tmp2273 = getelementptr inbounds float* %tmp2272, i64 1
-  %tmp2274 = getelementptr inbounds float* %tmp2273, i64 1
-  %tmp2275 = getelementptr inbounds float* %tmp2274, i64 1
-  %tmp2276 = getelementptr inbounds float* %tmp2275, i64 1
-  %tmp2277 = getelementptr inbounds float* %tmp2276, i64 1
-  %tmp2278 = getelementptr inbounds float* %tmp2277, i64 1
-  %tmp2279 = getelementptr inbounds float* %tmp2278, i64 1
-  %tmp2280 = getelementptr inbounds float* %tmp2279, i64 1
-  %tmp2281 = getelementptr inbounds float* %tmp2280, i64 1
-  %tmp2282 = getelementptr inbounds float* %tmp2281, i64 1
-  %tmp2283 = getelementptr inbounds float* %tmp2282, i64 1
-  %tmp2284 = getelementptr inbounds float* %tmp2283, i64 1
-  %tmp2285 = getelementptr inbounds float* %tmp2284, i64 1
-  %tmp2286 = getelementptr inbounds float* %tmp2285, i64 1
-  %tmp2287 = getelementptr inbounds float* %tmp2286, i64 1
-  %tmp2288 = getelementptr inbounds float* %tmp2287, i64 1
-  %tmp2289 = getelementptr inbounds float* %tmp2288, i64 1
-  %tmp2290 = getelementptr inbounds float* %tmp2289, i64 1
-  %tmp2291 = getelementptr inbounds float* %tmp2290, i64 1
-  %tmp2292 = getelementptr inbounds float* %tmp2291, i64 1
-  %tmp2293 = getelementptr inbounds float* %tmp2292, i64 1
-  %tmp2294 = getelementptr inbounds float* %tmp2293, i64 1
-  %tmp2295 = getelementptr inbounds float* %tmp2294, i64 1
-  %tmp2296 = getelementptr inbounds float* %tmp2295, i64 1
-  %tmp2297 = getelementptr inbounds float* %tmp2296, i64 1
-  %tmp2298 = getelementptr inbounds float* %tmp2297, i64 1
-  %tmp2299 = getelementptr inbounds float* %tmp2298, i64 1
-  %tmp2300 = getelementptr inbounds float* %tmp2299, i64 1
-  %tmp2301 = getelementptr inbounds float* %tmp2300, i64 1
-  %tmp2302 = getelementptr inbounds float* %tmp2301, i64 1
-  %tmp2303 = getelementptr inbounds float* %tmp2302, i64 1
-  %tmp2304 = getelementptr inbounds float* %tmp2303, i64 1
-  %tmp2305 = getelementptr inbounds float* %tmp2304, i64 1
-  %tmp2306 = getelementptr inbounds float* %tmp2305, i64 1
-  %tmp2307 = getelementptr inbounds float* %tmp2306, i64 1
-  %tmp2308 = getelementptr inbounds float* %tmp2307, i64 1
-  %tmp2309 = getelementptr inbounds float* %tmp2308, i64 1
-  %tmp2310 = getelementptr inbounds float* %tmp2309, i64 1
-  %tmp2311 = getelementptr inbounds float* %tmp2310, i64 1
-  %tmp2312 = getelementptr inbounds float* %tmp2311, i64 1
-  %tmp2313 = getelementptr inbounds float* %tmp2312, i64 1
-  %tmp2314 = getelementptr inbounds float* %tmp2313, i64 1
-  %tmp2315 = getelementptr inbounds float* %tmp2314, i64 1
-  %tmp2316 = getelementptr inbounds float* %tmp2315, i64 1
-  %tmp2317 = getelementptr inbounds float* %tmp2316, i64 1
-  %tmp2318 = getelementptr inbounds float* %tmp2317, i64 1
-  %tmp2319 = getelementptr inbounds float* %tmp2318, i64 1
-  %tmp2320 = getelementptr inbounds float* %tmp2319, i64 1
-  %tmp2321 = getelementptr inbounds float* %tmp2320, i64 1
-  %tmp2322 = getelementptr inbounds float* %tmp2321, i64 1
-  %tmp2323 = getelementptr inbounds float* %tmp2322, i64 1
-  %tmp2324 = getelementptr inbounds float* %tmp2323, i64 1
-  %tmp2325 = getelementptr inbounds float* %tmp2324, i64 1
-  %tmp2326 = getelementptr inbounds float* %tmp2325, i64 1
-  %tmp2327 = getelementptr inbounds float* %tmp2326, i64 1
-  %tmp2328 = getelementptr inbounds float* %tmp2327, i64 1
-  %tmp2329 = getelementptr inbounds float* %tmp2328, i64 1
-  %tmp2330 = getelementptr inbounds float* %tmp2329, i64 1
-  %tmp2331 = getelementptr inbounds float* %tmp2330, i64 1
-  %tmp2332 = getelementptr inbounds float* %tmp2331, i64 1
-  %tmp2333 = getelementptr inbounds float* %tmp2332, i64 1
-  %tmp2334 = getelementptr inbounds float* %tmp2333, i64 1
-  %tmp2335 = getelementptr inbounds float* %tmp2334, i64 1
-  %tmp2336 = getelementptr inbounds float* %tmp2335, i64 1
-  %tmp2337 = getelementptr inbounds float* %tmp2336, i64 1
-  %tmp2338 = getelementptr inbounds float* %tmp2337, i64 1
-  %tmp2339 = getelementptr inbounds float* %tmp2338, i64 1
-  %tmp2340 = getelementptr inbounds float* %tmp2339, i64 1
-  %tmp2341 = getelementptr inbounds float* %tmp2340, i64 1
-  %tmp2342 = getelementptr inbounds float* %tmp2341, i64 1
-  %tmp2343 = getelementptr inbounds float* %tmp2342, i64 1
-  %tmp2344 = getelementptr inbounds float* %tmp2343, i64 1
-  %tmp2345 = getelementptr inbounds float* %tmp2344, i64 1
-  %tmp2346 = getelementptr inbounds float* %tmp2345, i64 1
-  %tmp2347 = getelementptr inbounds float* %tmp2346, i64 1
-  %tmp2348 = getelementptr inbounds float* %tmp2347, i64 1
-  %tmp2349 = getelementptr inbounds float* %tmp2348, i64 1
-  %tmp2350 = getelementptr inbounds float* %tmp2349, i64 1
-  %tmp2351 = getelementptr inbounds float* %tmp2350, i64 1
-  %tmp2352 = getelementptr inbounds float* %tmp2351, i64 1
-  %tmp2353 = getelementptr inbounds float* %tmp2352, i64 1
-  %tmp2354 = getelementptr inbounds float* %tmp2353, i64 1
-  %tmp2355 = getelementptr inbounds float* %tmp2354, i64 1
-  %tmp2356 = getelementptr inbounds float* %tmp2355, i64 1
-  %tmp2357 = getelementptr inbounds float* %tmp2356, i64 1
-  %tmp2358 = getelementptr inbounds float* %tmp2357, i64 1
-  %tmp2359 = getelementptr inbounds float* %tmp2358, i64 1
-  %tmp2360 = getelementptr inbounds float* %tmp2359, i64 1
-  %tmp2361 = getelementptr inbounds float* %tmp2360, i64 1
-  %tmp2362 = getelementptr inbounds float* %tmp2361, i64 1
-  %tmp2363 = getelementptr inbounds float* %tmp2362, i64 1
-  %tmp2364 = getelementptr inbounds float* %tmp2363, i64 1
-  %tmp2365 = getelementptr inbounds float* %tmp2364, i64 1
-  %tmp2366 = getelementptr inbounds float* %tmp2365, i64 1
-  %tmp2367 = getelementptr inbounds float* %tmp2366, i64 1
-  %tmp2368 = getelementptr inbounds float* %tmp2367, i64 1
-  %tmp2369 = getelementptr inbounds float* %tmp2368, i64 1
-  %tmp2370 = getelementptr inbounds float* %tmp2369, i64 1
-  %tmp2371 = getelementptr inbounds float* %tmp2370, i64 1
-  %tmp2372 = getelementptr inbounds float* %tmp2371, i64 1
-  %tmp2373 = getelementptr inbounds float* %tmp2372, i64 1
-  %tmp2374 = getelementptr inbounds float* %tmp2373, i64 1
-  %tmp2375 = getelementptr inbounds float* %tmp2374, i64 1
-  %tmp2376 = getelementptr inbounds float* %tmp2375, i64 1
-  %tmp2377 = getelementptr inbounds float* %tmp2376, i64 1
-  %tmp2378 = getelementptr inbounds float* %tmp2377, i64 1
-  %tmp2379 = getelementptr inbounds float* %tmp2378, i64 1
-  %tmp2380 = getelementptr inbounds float* %tmp2379, i64 1
-  %tmp2381 = getelementptr inbounds float* %tmp2380, i64 1
-  %tmp2382 = getelementptr inbounds float* %tmp2381, i64 1
-  %tmp2383 = getelementptr inbounds float* %tmp2382, i64 1
-  %tmp2384 = getelementptr inbounds float* %tmp2383, i64 1
-  %tmp2385 = getelementptr inbounds float* %tmp2384, i64 1
-  %tmp2386 = getelementptr inbounds float* %tmp2385, i64 1
-  %tmp2387 = getelementptr inbounds float* %tmp2386, i64 1
-  %tmp2388 = getelementptr inbounds float* %tmp2387, i64 1
-  %tmp2389 = getelementptr inbounds float* %tmp2388, i64 1
-  %tmp2390 = getelementptr inbounds float* %tmp2389, i64 1
-  %tmp2391 = getelementptr inbounds float* %tmp2390, i64 1
-  %tmp2392 = getelementptr inbounds float* %tmp2391, i64 1
-  %tmp2393 = getelementptr inbounds float* %tmp2392, i64 1
-  %tmp2394 = getelementptr inbounds float* %tmp2393, i64 1
-  %tmp2395 = getelementptr inbounds float* %tmp2394, i64 1
-  %tmp2396 = getelementptr inbounds float* %tmp2395, i64 1
-  %tmp2397 = getelementptr inbounds float* %tmp2396, i64 1
-  %tmp2398 = getelementptr inbounds float* %tmp2397, i64 1
-  %tmp2399 = getelementptr inbounds float* %tmp2398, i64 1
-  %tmp2400 = getelementptr inbounds float* %tmp2399, i64 1
-  %tmp2401 = getelementptr inbounds float* %tmp2400, i64 1
-  %tmp2402 = getelementptr inbounds float* %tmp2401, i64 1
-  %tmp2403 = getelementptr inbounds float* %tmp2402, i64 1
-  %tmp2404 = getelementptr inbounds float* %tmp2403, i64 1
-  %tmp2405 = getelementptr inbounds float* %tmp2404, i64 1
-  %tmp2406 = getelementptr inbounds float* %tmp2405, i64 1
-  %tmp2407 = getelementptr inbounds float* %tmp2406, i64 1
-  %tmp2408 = getelementptr inbounds float* %tmp2407, i64 1
-  %tmp2409 = getelementptr inbounds float* %tmp2408, i64 1
-  %tmp2410 = getelementptr inbounds float* %tmp2409, i64 1
-  %tmp2411 = getelementptr inbounds float* %tmp2410, i64 1
-  %tmp2412 = getelementptr inbounds float* %tmp2411, i64 1
-  %tmp2413 = getelementptr inbounds float* %tmp2412, i64 1
-  %tmp2414 = getelementptr inbounds float* %tmp2413, i64 1
-  %tmp2415 = getelementptr inbounds float* %tmp2414, i64 1
-  %tmp2416 = getelementptr inbounds float* %tmp2415, i64 1
-  %tmp2417 = getelementptr inbounds float* %tmp2416, i64 1
-  %tmp2418 = getelementptr inbounds float* %tmp2417, i64 1
-  %tmp2419 = getelementptr inbounds float* %tmp2418, i64 1
-  %tmp2420 = getelementptr inbounds float* %tmp2419, i64 1
-  %tmp2421 = getelementptr inbounds float* %tmp2420, i64 1
-  %tmp2422 = getelementptr inbounds float* %tmp2421, i64 1
-  %tmp2423 = getelementptr inbounds float* %tmp2422, i64 1
-  %tmp2424 = getelementptr inbounds float* %tmp2423, i64 1
-  %tmp2425 = getelementptr inbounds float* %tmp2424, i64 1
-  %tmp2426 = getelementptr inbounds float* %tmp2425, i64 1
-  %tmp2427 = getelementptr inbounds float* %tmp2426, i64 1
-  %tmp2428 = getelementptr inbounds float* %tmp2427, i64 1
-  %tmp2429 = getelementptr inbounds float* %tmp2428, i64 1
-  %tmp2430 = getelementptr inbounds float* %tmp2429, i64 1
-  %tmp2431 = getelementptr inbounds float* %tmp2430, i64 1
-  %tmp2432 = getelementptr inbounds float* %tmp2431, i64 1
-  %tmp2433 = getelementptr inbounds float* %tmp2432, i64 1
-  %tmp2434 = getelementptr inbounds float* %tmp2433, i64 1
-  %tmp2435 = getelementptr inbounds float* %tmp2434, i64 1
-  %tmp2436 = getelementptr inbounds float* %tmp2435, i64 1
-  %tmp2437 = getelementptr inbounds float* %tmp2436, i64 1
-  %tmp2438 = getelementptr inbounds float* %tmp2437, i64 1
-  %tmp2439 = getelementptr inbounds float* %tmp2438, i64 1
-  %tmp2440 = getelementptr inbounds float* %tmp2439, i64 1
-  %tmp2441 = getelementptr inbounds float* %tmp2440, i64 1
-  %tmp2442 = getelementptr inbounds float* %tmp2441, i64 1
-  %tmp2443 = getelementptr inbounds float* %tmp2442, i64 1
-  %tmp2444 = getelementptr inbounds float* %tmp2443, i64 1
-  %tmp2445 = getelementptr inbounds float* %tmp2444, i64 1
-  %tmp2446 = getelementptr inbounds float* %tmp2445, i64 1
-  %tmp2447 = getelementptr inbounds float* %tmp2446, i64 1
-  %tmp2448 = getelementptr inbounds float* %tmp2447, i64 1
-  %tmp2449 = getelementptr inbounds float* %tmp2448, i64 1
-  %tmp2450 = getelementptr inbounds float* %tmp2449, i64 1
-  %tmp2451 = getelementptr inbounds float* %tmp2450, i64 1
-  %tmp2452 = getelementptr inbounds float* %tmp2451, i64 1
-  %tmp2453 = getelementptr inbounds float* %tmp2452, i64 1
-  %tmp2454 = getelementptr inbounds float* %tmp2453, i64 1
-  %tmp2455 = getelementptr inbounds float* %tmp2454, i64 1
-  %tmp2456 = getelementptr inbounds float* %tmp2455, i64 1
-  %tmp2457 = getelementptr inbounds float* %tmp2456, i64 1
-  %tmp2458 = getelementptr inbounds float* %tmp2457, i64 1
-  %tmp2459 = getelementptr inbounds float* %tmp2458, i64 1
-  %tmp2460 = getelementptr inbounds float* %tmp2459, i64 1
-  %tmp2461 = getelementptr inbounds float* %tmp2460, i64 1
-  %tmp2462 = getelementptr inbounds float* %tmp2461, i64 1
-  %tmp2463 = getelementptr inbounds float* %tmp2462, i64 1
-  %tmp2464 = getelementptr inbounds float* %tmp2463, i64 1
-  %tmp2465 = getelementptr inbounds float* %tmp2464, i64 1
-  %tmp2466 = getelementptr inbounds float* %tmp2465, i64 1
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-  %tmp2475 = getelementptr inbounds float* %tmp2474, i64 1
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-  %tmp2477 = getelementptr inbounds float* %tmp2476, i64 1
-  %tmp2478 = getelementptr inbounds float* %tmp2477, i64 1
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-  %tmp2480 = getelementptr inbounds float* %tmp2479, i64 1
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-  %tmp2482 = getelementptr inbounds float* %tmp2481, i64 1
-  %tmp2483 = getelementptr inbounds float* %tmp2482, i64 1
-  %tmp2484 = getelementptr inbounds float* %tmp2483, i64 1
-  %tmp2485 = getelementptr inbounds float* %tmp2484, i64 1
-  %tmp2486 = getelementptr inbounds float* %tmp2485, i64 1
-  %tmp2487 = getelementptr inbounds float* %tmp2486, i64 1
-  %tmp2488 = getelementptr inbounds float* %tmp2487, i64 1
-  %tmp2489 = getelementptr inbounds float* %tmp2488, i64 1
-  %tmp2490 = getelementptr inbounds float* %tmp2489, i64 1
-  %tmp2491 = getelementptr inbounds float* %tmp2490, i64 1
-  %tmp2492 = getelementptr inbounds float* %tmp2491, i64 1
-  %tmp2493 = getelementptr inbounds float* %tmp2492, i64 1
-  %tmp2494 = getelementptr inbounds float* %tmp2493, i64 1
-  %tmp2495 = getelementptr inbounds float* %tmp2494, i64 1
-  %tmp2496 = getelementptr inbounds float* %tmp2495, i64 1
-  %tmp2497 = getelementptr inbounds float* %tmp2496, i64 1
-  %tmp2498 = getelementptr inbounds float* %tmp2497, i64 1
-  %tmp2499 = getelementptr inbounds float* %tmp2498, i64 1
-  %tmp2500 = getelementptr inbounds float* %tmp2499, i64 1
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-  %tmp2506 = getelementptr inbounds float* %tmp2505, i64 1
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-  %tmp2510 = getelementptr inbounds float* %tmp2509, i64 1
-  %tmp2511 = getelementptr inbounds float* %tmp2510, i64 1
-  %tmp2512 = getelementptr inbounds float* %tmp2511, i64 1
-  %tmp2513 = getelementptr inbounds float* %tmp2512, i64 1
-  %tmp2514 = getelementptr inbounds float* %tmp2513, i64 1
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-  %tmp2517 = getelementptr inbounds float* %tmp2516, i64 1
-  %tmp2518 = getelementptr inbounds float* %tmp2517, i64 1
-  %tmp2519 = getelementptr inbounds float* %tmp2518, i64 1
-  %tmp2520 = getelementptr inbounds float* %tmp2519, i64 1
-  %tmp2521 = getelementptr inbounds float* %tmp2520, i64 1
-  %tmp2522 = getelementptr inbounds float* %tmp2521, i64 1
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-  %tmp2525 = getelementptr inbounds float* %tmp2524, i64 1
-  %tmp2526 = getelementptr inbounds float* %tmp2525, i64 1
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-  %tmp2532 = getelementptr inbounds float* %tmp2531, i64 1
-  %tmp2533 = getelementptr inbounds float* %tmp2532, i64 1
-  %tmp2534 = getelementptr inbounds float* %tmp2533, i64 1
-  %tmp2535 = getelementptr inbounds float* %tmp2534, i64 1
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-  %tmp2538 = getelementptr inbounds float* %tmp2537, i64 1
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-  %tmp2542 = getelementptr inbounds float* %tmp2541, i64 1
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-  %tmp2545 = getelementptr inbounds float* %tmp2544, i64 1
-  %tmp2546 = getelementptr inbounds float* %tmp2545, i64 1
-  %tmp2547 = getelementptr inbounds float* %tmp2546, i64 1
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-  %tmp2549 = getelementptr inbounds float* %tmp2548, i64 1
-  %tmp2550 = getelementptr inbounds float* %tmp2549, i64 1
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-  %tmp2552 = getelementptr inbounds float* %tmp2551, i64 1
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-  %tmp2555 = getelementptr inbounds float* %tmp2554, i64 1
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-  %tmp2557 = getelementptr inbounds float* %tmp2556, i64 1
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-  %tmp2559 = getelementptr inbounds float* %tmp2558, i64 1
-  %tmp2560 = getelementptr inbounds float* %tmp2559, i64 1
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-  %tmp2582 = getelementptr inbounds float* %tmp2581, i64 1
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-  %tmp2585 = getelementptr inbounds float* %tmp2584, i64 1
-  %tmp2586 = getelementptr inbounds float* %tmp2585, i64 1
-  %tmp2587 = getelementptr inbounds float* %tmp2586, i64 1
-  %tmp2588 = getelementptr inbounds float* %tmp2587, i64 1
-  %tmp2589 = getelementptr inbounds float* %tmp2588, i64 1
-  %tmp2590 = getelementptr inbounds float* %tmp2589, i64 1
-  %tmp2591 = getelementptr inbounds float* %tmp2590, i64 1
-  %tmp2592 = getelementptr inbounds float* %tmp2591, i64 1
-  %tmp2593 = getelementptr inbounds float* %tmp2592, i64 1
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-  %tmp2596 = getelementptr inbounds float* %tmp2595, i64 1
-  %tmp2597 = getelementptr inbounds float* %tmp2596, i64 1
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-  %tmp2602 = getelementptr inbounds float* %tmp2601, i64 1
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-  %tmp2606 = getelementptr inbounds float* %tmp2605, i64 1
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-  %tmp2620 = getelementptr inbounds float* %tmp2619, i64 1
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-  %tmp2649 = getelementptr inbounds float* %tmp2648, i64 1
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-  %tmp2685 = getelementptr inbounds float* %tmp2684, i64 1
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-  %tmp2690 = getelementptr inbounds float* %tmp2689, i64 1
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-  %tmp2779 = getelementptr inbounds float* %tmp2778, i64 1
-  %tmp2780 = getelementptr inbounds float* %tmp2779, i64 1
-  %tmp2781 = getelementptr inbounds float* %tmp2780, i64 1
-  %tmp2782 = getelementptr inbounds float* %tmp2781, i64 1
-  %tmp2783 = getelementptr inbounds float* %tmp2782, i64 1
-  %tmp2784 = getelementptr inbounds float* %tmp2783, i64 1
-  %tmp2785 = getelementptr inbounds float* %tmp2784, i64 1
-  %tmp2786 = getelementptr inbounds float* %tmp2785, i64 1
-  %tmp2787 = getelementptr inbounds float* %tmp2786, i64 1
-  %tmp2788 = getelementptr inbounds float* %tmp2787, i64 1
-  %tmp2789 = getelementptr inbounds float* %tmp2788, i64 1
-  %tmp2790 = getelementptr inbounds float* %tmp2789, i64 1
-  %tmp2791 = getelementptr inbounds float* %tmp2790, i64 1
-  %tmp2792 = getelementptr inbounds float* %tmp2791, i64 1
-  %tmp2793 = getelementptr inbounds float* %tmp2792, i64 1
-  %tmp2794 = getelementptr inbounds float* %tmp2793, i64 1
-  %tmp2795 = getelementptr inbounds float* %tmp2794, i64 1
-  %tmp2796 = getelementptr inbounds float* %tmp2795, i64 1
-  %tmp2797 = getelementptr inbounds float* %tmp2796, i64 1
-  %tmp2798 = getelementptr inbounds float* %tmp2797, i64 1
-  %tmp2799 = getelementptr inbounds float* %tmp2798, i64 1
-  %tmp2800 = getelementptr inbounds float* %tmp2799, i64 1
-  %tmp2801 = getelementptr inbounds float* %tmp2800, i64 1
-  %tmp2802 = getelementptr inbounds float* %tmp2801, i64 1
-  %tmp2803 = getelementptr inbounds float* %tmp2802, i64 1
-  %tmp2804 = getelementptr inbounds float* %tmp2803, i64 1
-  %tmp2805 = getelementptr inbounds float* %tmp2804, i64 1
-  %tmp2806 = getelementptr inbounds float* %tmp2805, i64 1
-  %tmp2807 = getelementptr inbounds float* %tmp2806, i64 1
-  %tmp2808 = getelementptr inbounds float* %tmp2807, i64 1
-  %tmp2809 = getelementptr inbounds float* %tmp2808, i64 1
-  %tmp2810 = getelementptr inbounds float* %tmp2809, i64 1
-  %tmp2811 = getelementptr inbounds float* %tmp2810, i64 1
-  %tmp2812 = getelementptr inbounds float* %tmp2811, i64 1
-  %tmp2813 = getelementptr inbounds float* %tmp2812, i64 1
-  %tmp2814 = getelementptr inbounds float* %tmp2813, i64 1
-  %tmp2815 = getelementptr inbounds float* %tmp2814, i64 1
-  %tmp2816 = getelementptr inbounds float* %tmp2815, i64 1
-  %tmp2817 = getelementptr inbounds float* %tmp2816, i64 1
-  %tmp2818 = getelementptr inbounds float* %tmp2817, i64 1
-  %tmp2819 = getelementptr inbounds float* %tmp2818, i64 1
-  %tmp2820 = getelementptr inbounds float* %tmp2819, i64 1
-  %tmp2821 = getelementptr inbounds float* %tmp2820, i64 1
-  %tmp2822 = getelementptr inbounds float* %tmp2821, i64 1
-  %tmp2823 = getelementptr inbounds float* %tmp2822, i64 1
-  %tmp2824 = getelementptr inbounds float* %tmp2823, i64 1
-  %tmp2825 = getelementptr inbounds float* %tmp2824, i64 1
-  %tmp2826 = getelementptr inbounds float* %tmp2825, i64 1
-  %tmp2827 = getelementptr inbounds float* %tmp2826, i64 1
-  %tmp2828 = getelementptr inbounds float* %tmp2827, i64 1
-  %tmp2829 = getelementptr inbounds float* %tmp2828, i64 1
-  %tmp2830 = getelementptr inbounds float* %tmp2829, i64 1
-  %tmp2831 = getelementptr inbounds float* %tmp2830, i64 1
-  %tmp2832 = getelementptr inbounds float* %tmp2831, i64 1
-  %tmp2833 = getelementptr inbounds float* %tmp2832, i64 1
-  %tmp2834 = getelementptr inbounds float* %tmp2833, i64 1
-  %tmp2835 = getelementptr inbounds float* %tmp2834, i64 1
-  %tmp2836 = getelementptr inbounds float* %tmp2835, i64 1
-  %tmp2837 = getelementptr inbounds float* %tmp2836, i64 1
-  %tmp2838 = getelementptr inbounds float* %tmp2837, i64 1
-  %tmp2839 = getelementptr inbounds float* %tmp2838, i64 1
-  %tmp2840 = getelementptr inbounds float* %tmp2839, i64 1
-  %tmp2841 = getelementptr inbounds float* %tmp2840, i64 1
-  %tmp2842 = getelementptr inbounds float* %tmp2841, i64 1
-  %tmp2843 = getelementptr inbounds float* %tmp2842, i64 1
-  %tmp2844 = getelementptr inbounds float* %tmp2843, i64 1
-  %tmp2845 = getelementptr inbounds float* %tmp2844, i64 1
-  %tmp2846 = getelementptr inbounds float* %tmp2845, i64 1
-  %tmp2847 = getelementptr inbounds float* %tmp2846, i64 1
-  %tmp2848 = getelementptr inbounds float* %tmp2847, i64 1
-  %tmp2849 = getelementptr inbounds float* %tmp2848, i64 1
-  %tmp2850 = getelementptr inbounds float* %tmp2849, i64 1
-  %tmp2851 = getelementptr inbounds float* %tmp2850, i64 1
-  %tmp2852 = getelementptr inbounds float* %tmp2851, i64 1
-  %tmp2853 = getelementptr inbounds float* %tmp2852, i64 1
-  %tmp2854 = getelementptr inbounds float* %tmp2853, i64 1
-  %tmp2855 = getelementptr inbounds float* %tmp2854, i64 1
-  %tmp2856 = getelementptr inbounds float* %tmp2855, i64 1
-  %tmp2857 = getelementptr inbounds float* %tmp2856, i64 1
-  %tmp2858 = getelementptr inbounds float* %tmp2857, i64 1
-  %tmp2859 = getelementptr inbounds float* %tmp2858, i64 1
-  %tmp2860 = getelementptr inbounds float* %tmp2859, i64 1
-  %tmp2861 = getelementptr inbounds float* %tmp2860, i64 1
-  %tmp2862 = getelementptr inbounds float* %tmp2861, i64 1
-  %tmp2863 = getelementptr inbounds float* %tmp2862, i64 1
-  %tmp2864 = getelementptr inbounds float* %tmp2863, i64 1
-  %tmp2865 = getelementptr inbounds float* %tmp2864, i64 1
-  %tmp2866 = getelementptr inbounds float* %tmp2865, i64 1
-  %tmp2867 = getelementptr inbounds float* %tmp2866, i64 1
-  %tmp2868 = getelementptr inbounds float* %tmp2867, i64 1
-  %tmp2869 = getelementptr inbounds float* %tmp2868, i64 1
-  %tmp2870 = getelementptr inbounds float* %tmp2869, i64 1
-  %tmp2871 = getelementptr inbounds float* %tmp2870, i64 1
-  %tmp2872 = getelementptr inbounds float* %tmp2871, i64 1
-  %tmp2873 = getelementptr inbounds float* %tmp2872, i64 1
-  %tmp2874 = getelementptr inbounds float* %tmp2873, i64 1
-  %tmp2875 = getelementptr inbounds float* %tmp2874, i64 1
-  %tmp2876 = getelementptr inbounds float* %tmp2875, i64 1
-  %tmp2877 = getelementptr inbounds float* %tmp2876, i64 1
-  %tmp2878 = getelementptr inbounds float* %tmp2877, i64 1
-  %tmp2879 = getelementptr inbounds float* %tmp2878, i64 1
-  %tmp2880 = getelementptr inbounds float* %tmp2879, i64 1
-  %tmp2881 = getelementptr inbounds float* %tmp2880, i64 1
-  %tmp2882 = getelementptr inbounds float* %tmp2881, i64 1
-  %tmp2883 = getelementptr inbounds float* %tmp2882, i64 1
-  %tmp2884 = getelementptr inbounds float* %tmp2883, i64 1
-  %tmp2885 = getelementptr inbounds float* %tmp2884, i64 1
-  %tmp2886 = getelementptr inbounds float* %tmp2885, i64 1
-  %tmp2887 = getelementptr inbounds float* %tmp2886, i64 1
-  %tmp2888 = getelementptr inbounds float* %tmp2887, i64 1
-  %tmp2889 = getelementptr inbounds float* %tmp2888, i64 1
-  %tmp2890 = getelementptr inbounds float* %tmp2889, i64 1
-  %tmp2891 = getelementptr inbounds float* %tmp2890, i64 1
-  %tmp2892 = getelementptr inbounds float* %tmp2891, i64 1
-  %tmp2893 = getelementptr inbounds float* %tmp2892, i64 1
-  %tmp2894 = getelementptr inbounds float* %tmp2893, i64 1
-  %tmp2895 = getelementptr inbounds float* %tmp2894, i64 1
-  %tmp2896 = getelementptr inbounds float* %tmp2895, i64 1
-  %tmp2897 = getelementptr inbounds float* %tmp2896, i64 1
-  %tmp2898 = getelementptr inbounds float* %tmp2897, i64 1
-  %tmp2899 = getelementptr inbounds float* %tmp2898, i64 1
-  %tmp2900 = getelementptr inbounds float* %tmp2899, i64 1
-  %tmp2901 = getelementptr inbounds float* %tmp2900, i64 1
-  %tmp2902 = getelementptr inbounds float* %tmp2901, i64 1
-  %tmp2903 = getelementptr inbounds float* %tmp2902, i64 1
-  %tmp2904 = getelementptr inbounds float* %tmp2903, i64 1
-  %tmp2905 = getelementptr inbounds float* %tmp2904, i64 1
-  %tmp2906 = getelementptr inbounds float* %tmp2905, i64 1
-  %tmp2907 = getelementptr inbounds float* %tmp2906, i64 1
-  %tmp2908 = getelementptr inbounds float* %tmp2907, i64 1
-  %tmp2909 = getelementptr inbounds float* %tmp2908, i64 1
-  %tmp2910 = getelementptr inbounds float* %tmp2909, i64 1
-  %tmp2911 = getelementptr inbounds float* %tmp2910, i64 1
-  %tmp2912 = getelementptr inbounds float* %tmp2911, i64 1
-  %tmp2913 = getelementptr inbounds float* %tmp2912, i64 1
-  %tmp2914 = getelementptr inbounds float* %tmp2913, i64 1
-  %tmp2915 = getelementptr inbounds float* %tmp2914, i64 1
-  %tmp2916 = getelementptr inbounds float* %tmp2915, i64 1
-  %tmp2917 = getelementptr inbounds float* %tmp2916, i64 1
-  %tmp2918 = getelementptr inbounds float* %tmp2917, i64 1
-  %tmp2919 = getelementptr inbounds float* %tmp2918, i64 1
-  %tmp2920 = getelementptr inbounds float* %tmp2919, i64 1
-  %tmp2921 = getelementptr inbounds float* %tmp2920, i64 1
-  %tmp2922 = getelementptr inbounds float* %tmp2921, i64 1
-  %tmp2923 = getelementptr inbounds float* %tmp2922, i64 1
-  %tmp2924 = getelementptr inbounds float* %tmp2923, i64 1
-  %tmp2925 = getelementptr inbounds float* %tmp2924, i64 1
-  %tmp2926 = getelementptr inbounds float* %tmp2925, i64 1
-  %tmp2927 = getelementptr inbounds float* %tmp2926, i64 1
-  %tmp2928 = getelementptr inbounds float* %tmp2927, i64 1
-  %tmp2929 = getelementptr inbounds float* %tmp2928, i64 1
-  %tmp2930 = getelementptr inbounds float* %tmp2929, i64 1
-  %tmp2931 = getelementptr inbounds float* %tmp2930, i64 1
-  %tmp2932 = getelementptr inbounds float* %tmp2931, i64 1
-  %tmp2933 = getelementptr inbounds float* %tmp2932, i64 1
-  %tmp2934 = getelementptr inbounds float* %tmp2933, i64 1
-  %tmp2935 = getelementptr inbounds float* %tmp2934, i64 1
-  %tmp2936 = getelementptr inbounds float* %tmp2935, i64 1
-  %tmp2937 = getelementptr inbounds float* %tmp2936, i64 1
-  %tmp2938 = getelementptr inbounds float* %tmp2937, i64 1
-  %tmp2939 = getelementptr inbounds float* %tmp2938, i64 1
-  %tmp2940 = getelementptr inbounds float* %tmp2939, i64 1
-  %tmp2941 = getelementptr inbounds float* %tmp2940, i64 1
-  %tmp2942 = getelementptr inbounds float* %tmp2941, i64 1
-  %tmp2943 = getelementptr inbounds float* %tmp2942, i64 1
-  %tmp2944 = getelementptr inbounds float* %tmp2943, i64 1
-  %tmp2945 = getelementptr inbounds float* %tmp2944, i64 1
-  %tmp2946 = getelementptr inbounds float* %tmp2945, i64 1
-  %tmp2947 = getelementptr inbounds float* %tmp2946, i64 1
-  %tmp2948 = getelementptr inbounds float* %tmp2947, i64 1
-  %tmp2949 = getelementptr inbounds float* %tmp2948, i64 1
-  %tmp2950 = getelementptr inbounds float* %tmp2949, i64 1
-  %tmp2951 = getelementptr inbounds float* %tmp2950, i64 1
-  %tmp2952 = getelementptr inbounds float* %tmp2951, i64 1
-  %tmp2953 = getelementptr inbounds float* %tmp2952, i64 1
-  %tmp2954 = getelementptr inbounds float* %tmp2953, i64 1
-  %tmp2955 = getelementptr inbounds float* %tmp2954, i64 1
-  %tmp2956 = getelementptr inbounds float* %tmp2955, i64 1
-  %tmp2957 = getelementptr inbounds float* %tmp2956, i64 1
-  %tmp2958 = getelementptr inbounds float* %tmp2957, i64 1
-  %tmp2959 = getelementptr inbounds float* %tmp2958, i64 1
-  %tmp2960 = getelementptr inbounds float* %tmp2959, i64 1
-  %tmp2961 = getelementptr inbounds float* %tmp2960, i64 1
-  %tmp2962 = getelementptr inbounds float* %tmp2961, i64 1
-  %tmp2963 = getelementptr inbounds float* %tmp2962, i64 1
-  %tmp2964 = getelementptr inbounds float* %tmp2963, i64 1
-  %tmp2965 = getelementptr inbounds float* %tmp2964, i64 1
-  %tmp2966 = getelementptr inbounds float* %tmp2965, i64 1
-  %tmp2967 = getelementptr inbounds float* %tmp2966, i64 1
-  %tmp2968 = getelementptr inbounds float* %tmp2967, i64 1
-  %tmp2969 = getelementptr inbounds float* %tmp2968, i64 1
-  %tmp2970 = getelementptr inbounds float* %tmp2969, i64 1
-  %tmp2971 = getelementptr inbounds float* %tmp2970, i64 1
-  %tmp2972 = getelementptr inbounds float* %tmp2971, i64 1
-  %tmp2973 = getelementptr inbounds float* %tmp2972, i64 1
-  %tmp2974 = getelementptr inbounds float* %tmp2973, i64 1
-  %tmp2975 = getelementptr inbounds float* %tmp2974, i64 1
-  %tmp2976 = getelementptr inbounds float* %tmp2975, i64 1
-  %tmp2977 = getelementptr inbounds float* %tmp2976, i64 1
-  %tmp2978 = getelementptr inbounds float* %tmp2977, i64 1
-  %tmp2979 = getelementptr inbounds float* %tmp2978, i64 1
-  %tmp2980 = getelementptr inbounds float* %tmp2979, i64 1
-  %tmp2981 = getelementptr inbounds float* %tmp2980, i64 1
-  %tmp2982 = getelementptr inbounds float* %tmp2981, i64 1
-  %tmp2983 = getelementptr inbounds float* %tmp2982, i64 1
-  %tmp2984 = getelementptr inbounds float* %tmp2983, i64 1
-  %tmp2985 = getelementptr inbounds float* %tmp2984, i64 1
-  %tmp2986 = getelementptr inbounds float* %tmp2985, i64 1
-  %tmp2987 = getelementptr inbounds float* %tmp2986, i64 1
-  %tmp2988 = getelementptr inbounds float* %tmp2987, i64 1
-  %tmp2989 = getelementptr inbounds float* %tmp2988, i64 1
-  %tmp2990 = getelementptr inbounds float* %tmp2989, i64 1
-  %tmp2991 = getelementptr inbounds float* %tmp2990, i64 1
-  %tmp2992 = getelementptr inbounds float* %tmp2991, i64 1
-  %tmp2993 = getelementptr inbounds float* %tmp2992, i64 1
-  %tmp2994 = getelementptr inbounds float* %tmp2993, i64 1
-  %tmp2995 = getelementptr inbounds float* %tmp2994, i64 1
-  %tmp2996 = getelementptr inbounds float* %tmp2995, i64 1
-  %tmp2997 = getelementptr inbounds float* %tmp2996, i64 1
-  %tmp2998 = getelementptr inbounds float* %tmp2997, i64 1
-  %tmp2999 = getelementptr inbounds float* %tmp2998, i64 1
-  %tmp3000 = getelementptr inbounds float* %tmp2999, i64 1
-  %tmp3001 = getelementptr inbounds float* %tmp3000, i64 1
-  %tmp3002 = getelementptr inbounds float* %tmp3001, i64 1
-  %tmp3003 = getelementptr inbounds float* %tmp3002, i64 1
-  %tmp3004 = getelementptr inbounds float* %tmp3003, i64 1
-  %tmp3005 = getelementptr inbounds float* %tmp3004, i64 1
-  %tmp3006 = getelementptr inbounds float* %tmp3005, i64 1
-  %tmp3007 = getelementptr inbounds float* %tmp3006, i64 1
-  %tmp3008 = getelementptr inbounds float* %tmp3007, i64 1
-  %tmp3009 = getelementptr inbounds float* %tmp3008, i64 1
-  %tmp3010 = getelementptr inbounds float* %tmp3009, i64 1
-  %tmp3011 = getelementptr inbounds float* %tmp3010, i64 1
-  %tmp3012 = getelementptr inbounds float* %tmp3011, i64 1
-  %tmp3013 = getelementptr inbounds float* %tmp3012, i64 1
-  %tmp3014 = getelementptr inbounds float* %tmp3013, i64 1
-  %tmp3015 = getelementptr inbounds float* %tmp3014, i64 1
-  %tmp3016 = getelementptr inbounds float* %tmp3015, i64 1
-  %tmp3017 = getelementptr inbounds float* %tmp3016, i64 1
-  %tmp3018 = getelementptr inbounds float* %tmp3017, i64 1
-  %tmp3019 = getelementptr inbounds float* %tmp3018, i64 1
-  %tmp3020 = getelementptr inbounds float* %tmp3019, i64 1
-  %tmp3021 = getelementptr inbounds float* %tmp3020, i64 1
-  %tmp3022 = getelementptr inbounds float* %tmp3021, i64 1
-  %tmp3023 = getelementptr inbounds float* %tmp3022, i64 1
-  %tmp3024 = getelementptr inbounds float* %tmp3023, i64 1
-  %tmp3025 = getelementptr inbounds float* %tmp3024, i64 1
-  %tmp3026 = getelementptr inbounds float* %tmp3025, i64 1
-  %tmp3027 = getelementptr inbounds float* %tmp3026, i64 1
-  %tmp3028 = getelementptr inbounds float* %tmp3027, i64 1
-  %tmp3029 = getelementptr inbounds float* %tmp3028, i64 1
-  %tmp3030 = getelementptr inbounds float* %tmp3029, i64 1
-  %tmp3031 = getelementptr inbounds float* %tmp3030, i64 1
-  %tmp3032 = getelementptr inbounds float* %tmp3031, i64 1
-  %tmp3033 = getelementptr inbounds float* %tmp3032, i64 1
-  %tmp3034 = getelementptr inbounds float* %tmp3033, i64 1
-  %tmp3035 = getelementptr inbounds float* %tmp3034, i64 1
-  %tmp3036 = getelementptr inbounds float* %tmp3035, i64 1
-  %tmp3037 = getelementptr inbounds float* %tmp3036, i64 1
-  %tmp3038 = getelementptr inbounds float* %tmp3037, i64 1
-  %tmp3039 = getelementptr inbounds float* %tmp3038, i64 1
-  %tmp3040 = getelementptr inbounds float* %tmp3039, i64 1
-  %tmp3041 = getelementptr inbounds float* %tmp3040, i64 1
-  %tmp3042 = getelementptr inbounds float* %tmp3041, i64 1
-  %tmp3043 = getelementptr inbounds float* %tmp3042, i64 1
-  %tmp3044 = getelementptr inbounds float* %tmp3043, i64 1
-  %tmp3045 = getelementptr inbounds float* %tmp3044, i64 1
-  %tmp3046 = getelementptr inbounds float* %tmp3045, i64 1
-  %tmp3047 = getelementptr inbounds float* %tmp3046, i64 1
-  %tmp3048 = getelementptr inbounds float* %tmp3047, i64 1
-  %tmp3049 = getelementptr inbounds float* %tmp3048, i64 1
-  %tmp3050 = getelementptr inbounds float* %tmp3049, i64 1
-  %tmp3051 = getelementptr inbounds float* %tmp3050, i64 1
-  %tmp3052 = getelementptr inbounds float* %tmp3051, i64 1
-  %tmp3053 = getelementptr inbounds float* %tmp3052, i64 1
-  %tmp3054 = getelementptr inbounds float* %tmp3053, i64 1
-  %tmp3055 = getelementptr inbounds float* %tmp3054, i64 1
-  %tmp3056 = getelementptr inbounds float* %tmp3055, i64 1
-  %tmp3057 = getelementptr inbounds float* %tmp3056, i64 1
-  %tmp3058 = getelementptr inbounds float* %tmp3057, i64 1
-  %tmp3059 = getelementptr inbounds float* %tmp3058, i64 1
-  %tmp3060 = getelementptr inbounds float* %tmp3059, i64 1
-  %tmp3061 = getelementptr inbounds float* %tmp3060, i64 1
-  %tmp3062 = getelementptr inbounds float* %tmp3061, i64 1
-  %tmp3063 = getelementptr inbounds float* %tmp3062, i64 1
-  %tmp3064 = getelementptr inbounds float* %tmp3063, i64 1
-  %tmp3065 = getelementptr inbounds float* %tmp3064, i64 1
-  %tmp3066 = getelementptr inbounds float* %tmp3065, i64 1
-  %tmp3067 = getelementptr inbounds float* %tmp3066, i64 1
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-  %tmp3069 = getelementptr inbounds float* %tmp3068, i64 1
-  %tmp3070 = getelementptr inbounds float* %tmp3069, i64 1
-  %tmp3071 = getelementptr inbounds float* %tmp3070, i64 1
-  %tmp3072 = getelementptr inbounds float* %tmp3071, i64 1
-  %tmp3073 = getelementptr inbounds float* %tmp3072, i64 1
-  %tmp3074 = getelementptr inbounds float* %tmp3073, i64 1
-  %tmp3075 = getelementptr inbounds float* %tmp3074, i64 1
-  %tmp3076 = getelementptr inbounds float* %tmp3075, i64 1
-  %tmp3077 = getelementptr inbounds float* %tmp3076, i64 1
-  %tmp3078 = getelementptr inbounds float* %tmp3077, i64 1
-  %tmp3079 = getelementptr inbounds float* %tmp3078, i64 1
-  %tmp3080 = getelementptr inbounds float* %tmp3079, i64 1
-  %tmp3081 = getelementptr inbounds float* %tmp3080, i64 1
-  %tmp3082 = getelementptr inbounds float* %tmp3081, i64 1
-  %tmp3083 = getelementptr inbounds float* %tmp3082, i64 1
-  %tmp3084 = getelementptr inbounds float* %tmp3083, i64 1
-  %tmp3085 = getelementptr inbounds float* %tmp3084, i64 1
-  %tmp3086 = getelementptr inbounds float* %tmp3085, i64 1
-  %tmp3087 = getelementptr inbounds float* %tmp3086, i64 1
-  %tmp3088 = getelementptr inbounds float* %tmp3087, i64 1
-  %tmp3089 = getelementptr inbounds float* %tmp3088, i64 1
-  %tmp3090 = getelementptr inbounds float* %tmp3089, i64 1
-  %tmp3091 = getelementptr inbounds float* %tmp3090, i64 1
-  %tmp3092 = getelementptr inbounds float* %tmp3091, i64 1
-  %tmp3093 = getelementptr inbounds float* %tmp3092, i64 1
-  %tmp3094 = getelementptr inbounds float* %tmp3093, i64 1
-  %tmp3095 = getelementptr inbounds float* %tmp3094, i64 1
-  %tmp3096 = getelementptr inbounds float* %tmp3095, i64 1
-  %tmp3097 = getelementptr inbounds float* %tmp3096, i64 1
-  %tmp3098 = getelementptr inbounds float* %tmp3097, i64 1
-  %tmp3099 = getelementptr inbounds float* %tmp3098, i64 1
-  %tmp3100 = getelementptr inbounds float* %tmp3099, i64 1
-  %tmp3101 = getelementptr inbounds float* %tmp3100, i64 1
-  %tmp3102 = getelementptr inbounds float* %tmp3101, i64 1
-  %tmp3103 = getelementptr inbounds float* %tmp3102, i64 1
-  %tmp3104 = getelementptr inbounds float* %tmp3103, i64 1
-  %tmp3105 = getelementptr inbounds float* %tmp3104, i64 1
-  %tmp3106 = getelementptr inbounds float* %tmp3105, i64 1
-  %tmp3107 = getelementptr inbounds float* %tmp3106, i64 1
-  %tmp3108 = getelementptr inbounds float* %tmp3107, i64 1
-  %tmp3109 = getelementptr inbounds float* %tmp3108, i64 1
-  %tmp3110 = getelementptr inbounds float* %tmp3109, i64 1
-  %tmp3111 = getelementptr inbounds float* %tmp3110, i64 1
-  %tmp3112 = getelementptr inbounds float* %tmp3111, i64 1
-  %tmp3113 = getelementptr inbounds float* %tmp3112, i64 1
-  %tmp3114 = getelementptr inbounds float* %tmp3113, i64 1
-  %tmp3115 = getelementptr inbounds float* %tmp3114, i64 1
-  %tmp3116 = getelementptr inbounds float* %tmp3115, i64 1
-  %tmp3117 = getelementptr inbounds float* %tmp3116, i64 1
-  %tmp3118 = getelementptr inbounds float* %tmp3117, i64 1
-  %tmp3119 = getelementptr inbounds float* %tmp3118, i64 1
-  %tmp3120 = getelementptr inbounds float* %tmp3119, i64 1
-  %tmp3121 = getelementptr inbounds float* %tmp3120, i64 1
-  %tmp3122 = getelementptr inbounds float* %tmp3121, i64 1
-  %tmp3123 = getelementptr inbounds float* %tmp3122, i64 1
-  %tmp3124 = getelementptr inbounds float* %tmp3123, i64 1
-  %tmp3125 = getelementptr inbounds float* %tmp3124, i64 1
-  %tmp3126 = getelementptr inbounds float* %tmp3125, i64 1
-  %tmp3127 = getelementptr inbounds float* %tmp3126, i64 1
-  %tmp3128 = getelementptr inbounds float* %tmp3127, i64 1
-  %tmp3129 = getelementptr inbounds float* %tmp3128, i64 1
-  %tmp3130 = getelementptr inbounds float* %tmp3129, i64 1
-  %tmp3131 = getelementptr inbounds float* %tmp3130, i64 1
-  %tmp3132 = getelementptr inbounds float* %tmp3131, i64 1
-  %tmp3133 = getelementptr inbounds float* %tmp3132, i64 1
-  %tmp3134 = getelementptr inbounds float* %tmp3133, i64 1
-  %tmp3135 = getelementptr inbounds float* %tmp3134, i64 1
-  %tmp3136 = getelementptr inbounds float* %tmp3135, i64 1
-  %tmp3137 = getelementptr inbounds float* %tmp3136, i64 1
-  %tmp3138 = getelementptr inbounds float* %tmp3137, i64 1
-  %tmp3139 = getelementptr inbounds float* %tmp3138, i64 1
-  %tmp3140 = getelementptr inbounds float* %tmp3139, i64 1
-  %tmp3141 = getelementptr inbounds float* %tmp3140, i64 1
-  %tmp3142 = getelementptr inbounds float* %tmp3141, i64 1
-  %tmp3143 = getelementptr inbounds float* %tmp3142, i64 1
-  %tmp3144 = getelementptr inbounds float* %tmp3143, i64 1
-  %tmp3145 = getelementptr inbounds float* %tmp3144, i64 1
-  %tmp3146 = getelementptr inbounds float* %tmp3145, i64 1
-  %tmp3147 = getelementptr inbounds float* %tmp3146, i64 1
-  %tmp3148 = getelementptr inbounds float* %tmp3147, i64 1
-  %tmp3149 = getelementptr inbounds float* %tmp3148, i64 1
-  %tmp3150 = getelementptr inbounds float* %tmp3149, i64 1
-  %tmp3151 = getelementptr inbounds float* %tmp3150, i64 1
-  %tmp3152 = getelementptr inbounds float* %tmp3151, i64 1
-  %tmp3153 = getelementptr inbounds float* %tmp3152, i64 1
-  %tmp3154 = getelementptr inbounds float* %tmp3153, i64 1
-  %tmp3155 = getelementptr inbounds float* %tmp3154, i64 1
-  %tmp3156 = getelementptr inbounds float* %tmp3155, i64 1
-  %tmp3157 = getelementptr inbounds float* %tmp3156, i64 1
-  %tmp3158 = getelementptr inbounds float* %tmp3157, i64 1
-  %tmp3159 = getelementptr inbounds float* %tmp3158, i64 1
-  %tmp3160 = getelementptr inbounds float* %tmp3159, i64 1
-  %tmp3161 = getelementptr inbounds float* %tmp3160, i64 1
-  %tmp3162 = getelementptr inbounds float* %tmp3161, i64 1
-  %tmp3163 = getelementptr inbounds float* %tmp3162, i64 1
-  %tmp3164 = getelementptr inbounds float* %tmp3163, i64 1
-  %tmp3165 = getelementptr inbounds float* %tmp3164, i64 1
-  %tmp3166 = getelementptr inbounds float* %tmp3165, i64 1
-  %tmp3167 = getelementptr inbounds float* %tmp3166, i64 1
-  %tmp3168 = getelementptr inbounds float* %tmp3167, i64 1
-  %tmp3169 = getelementptr inbounds float* %tmp3168, i64 1
-  %tmp3170 = getelementptr inbounds float* %tmp3169, i64 1
-  %tmp3171 = getelementptr inbounds float* %tmp3170, i64 1
-  %tmp3172 = getelementptr inbounds float* %tmp3171, i64 1
-  %tmp3173 = getelementptr inbounds float* %tmp3172, i64 1
-  %tmp3174 = getelementptr inbounds float* %tmp3173, i64 1
-  %tmp3175 = getelementptr inbounds float* %tmp3174, i64 1
-  %tmp3176 = getelementptr inbounds float* %tmp3175, i64 1
-  %tmp3177 = getelementptr inbounds float* %tmp3176, i64 1
-  %tmp3178 = getelementptr inbounds float* %tmp3177, i64 1
-  %tmp3179 = getelementptr inbounds float* %tmp3178, i64 1
-  %tmp3180 = getelementptr inbounds float* %tmp3179, i64 1
-  %tmp3181 = getelementptr inbounds float* %tmp3180, i64 1
-  %tmp3182 = getelementptr inbounds float* %tmp3181, i64 1
-  %tmp3183 = getelementptr inbounds float* %tmp3182, i64 1
-  %tmp3184 = getelementptr inbounds float* %tmp3183, i64 1
-  %tmp3185 = getelementptr inbounds float* %tmp3184, i64 1
-  %tmp3186 = getelementptr inbounds float* %tmp3185, i64 1
-  %tmp3187 = getelementptr inbounds float* %tmp3186, i64 1
-  %tmp3188 = getelementptr inbounds float* %tmp3187, i64 1
-  %tmp3189 = getelementptr inbounds float* %tmp3188, i64 1
-  %tmp3190 = getelementptr inbounds float* %tmp3189, i64 1
-  %tmp3191 = getelementptr inbounds float* %tmp3190, i64 1
-  %tmp3192 = getelementptr inbounds float* %tmp3191, i64 1
-  %tmp3193 = getelementptr inbounds float* %tmp3192, i64 1
-  %tmp3194 = getelementptr inbounds float* %tmp3193, i64 1
-  %tmp3195 = getelementptr inbounds float* %tmp3194, i64 1
-  %tmp3196 = getelementptr inbounds float* %tmp3195, i64 1
-  %tmp3197 = getelementptr inbounds float* %tmp3196, i64 1
-  %tmp3198 = getelementptr inbounds float* %tmp3197, i64 1
-  %tmp3199 = getelementptr inbounds float* %tmp3198, i64 1
-  %tmp3200 = getelementptr inbounds float* %tmp3199, i64 1
-  %tmp3201 = getelementptr inbounds float* %tmp3200, i64 1
-  %tmp3202 = getelementptr inbounds float* %tmp3201, i64 1
-  %tmp3203 = getelementptr inbounds float* %tmp3202, i64 1
-  %tmp3204 = getelementptr inbounds float* %tmp3203, i64 1
-  %tmp3205 = getelementptr inbounds float* %tmp3204, i64 1
-  %tmp3206 = getelementptr inbounds float* %tmp3205, i64 1
-  %tmp3207 = getelementptr inbounds float* %tmp3206, i64 1
-  %tmp3208 = getelementptr inbounds float* %tmp3207, i64 1
-  %tmp3209 = getelementptr inbounds float* %tmp3208, i64 1
-  %tmp3210 = getelementptr inbounds float* %tmp3209, i64 1
-  %tmp3211 = getelementptr inbounds float* %tmp3210, i64 1
-  %tmp3212 = getelementptr inbounds float* %tmp3211, i64 1
-  %tmp3213 = getelementptr inbounds float* %tmp3212, i64 1
-  %tmp3214 = getelementptr inbounds float* %tmp3213, i64 1
-  %tmp3215 = getelementptr inbounds float* %tmp3214, i64 1
-  %tmp3216 = getelementptr inbounds float* %tmp3215, i64 1
-  %tmp3217 = getelementptr inbounds float* %tmp3216, i64 1
-  %tmp3218 = getelementptr inbounds float* %tmp3217, i64 1
-  %tmp3219 = getelementptr inbounds float* %tmp3218, i64 1
-  %tmp3220 = getelementptr inbounds float* %tmp3219, i64 1
-  %tmp3221 = getelementptr inbounds float* %tmp3220, i64 1
-  %tmp3222 = getelementptr inbounds float* %tmp3221, i64 1
-  %tmp3223 = getelementptr inbounds float* %tmp3222, i64 1
-  %tmp3224 = getelementptr inbounds float* %tmp3223, i64 1
-  %tmp3225 = getelementptr inbounds float* %tmp3224, i64 1
-  %tmp3226 = getelementptr inbounds float* %tmp3225, i64 1
-  %tmp3227 = getelementptr inbounds float* %tmp3226, i64 1
-  %tmp3228 = getelementptr inbounds float* %tmp3227, i64 1
-  %tmp3229 = getelementptr inbounds float* %tmp3228, i64 1
-  %tmp3230 = getelementptr inbounds float* %tmp3229, i64 1
-  %tmp3231 = getelementptr inbounds float* %tmp3230, i64 1
-  %tmp3232 = getelementptr inbounds float* %tmp3231, i64 1
-  %tmp3233 = getelementptr inbounds float* %tmp3232, i64 1
-  %tmp3234 = getelementptr inbounds float* %tmp3233, i64 1
-  %tmp3235 = getelementptr inbounds float* %tmp3234, i64 1
-  %tmp3236 = getelementptr inbounds float* %tmp3235, i64 1
-  %tmp3237 = getelementptr inbounds float* %tmp3236, i64 1
-  %tmp3238 = getelementptr inbounds float* %tmp3237, i64 1
-  %tmp3239 = getelementptr inbounds float* %tmp3238, i64 1
-  %tmp3240 = getelementptr inbounds float* %tmp3239, i64 1
-  %tmp3241 = getelementptr inbounds float* %tmp3240, i64 1
-  %tmp3242 = getelementptr inbounds float* %tmp3241, i64 1
-  %tmp3243 = getelementptr inbounds float* %tmp3242, i64 1
-  %tmp3244 = getelementptr inbounds float* %tmp3243, i64 1
-  %tmp3245 = getelementptr inbounds float* %tmp3244, i64 1
-  %tmp3246 = getelementptr inbounds float* %tmp3245, i64 1
-  %tmp3247 = getelementptr inbounds float* %tmp3246, i64 1
-  %tmp3248 = getelementptr inbounds float* %tmp3247, i64 1
-  %tmp3249 = getelementptr inbounds float* %tmp3248, i64 1
-  %tmp3250 = getelementptr inbounds float* %tmp3249, i64 1
-  %tmp3251 = getelementptr inbounds float* %tmp3250, i64 1
-  %tmp3252 = getelementptr inbounds float* %tmp3251, i64 1
-  %tmp3253 = getelementptr inbounds float* %tmp3252, i64 1
-  %tmp3254 = getelementptr inbounds float* %tmp3253, i64 1
-  %tmp3255 = getelementptr inbounds float* %tmp3254, i64 1
-  %tmp3256 = getelementptr inbounds float* %tmp3255, i64 1
-  %tmp3257 = getelementptr inbounds float* %tmp3256, i64 1
-  %tmp3258 = getelementptr inbounds float* %tmp3257, i64 1
-  %tmp3259 = getelementptr inbounds float* %tmp3258, i64 1
-  %tmp3260 = getelementptr inbounds float* %tmp3259, i64 1
-  %tmp3261 = getelementptr inbounds float* %tmp3260, i64 1
-  %tmp3262 = getelementptr inbounds float* %tmp3261, i64 1
-  %tmp3263 = getelementptr inbounds float* %tmp3262, i64 1
-  %tmp3264 = getelementptr inbounds float* %tmp3263, i64 1
-  %tmp3265 = getelementptr inbounds float* %tmp3264, i64 1
-  %tmp3266 = getelementptr inbounds float* %tmp3265, i64 1
-  %tmp3267 = getelementptr inbounds float* %tmp3266, i64 1
-  %tmp3268 = getelementptr inbounds float* %tmp3267, i64 1
-  %tmp3269 = getelementptr inbounds float* %tmp3268, i64 1
-  %tmp3270 = getelementptr inbounds float* %tmp3269, i64 1
-  %tmp3271 = getelementptr inbounds float* %tmp3270, i64 1
-  %tmp3272 = getelementptr inbounds float* %tmp3271, i64 1
-  %tmp3273 = getelementptr inbounds float* %tmp3272, i64 1
-  %tmp3274 = getelementptr inbounds float* %tmp3273, i64 1
-  %tmp3275 = getelementptr inbounds float* %tmp3274, i64 1
-  %tmp3276 = getelementptr inbounds float* %tmp3275, i64 1
-  %tmp3277 = getelementptr inbounds float* %tmp3276, i64 1
-  %tmp3278 = getelementptr inbounds float* %tmp3277, i64 1
-  %tmp3279 = getelementptr inbounds float* %tmp3278, i64 1
-  %tmp3280 = getelementptr inbounds float* %tmp3279, i64 1
-  %tmp3281 = getelementptr inbounds float* %tmp3280, i64 1
-  %tmp3282 = getelementptr inbounds float* %tmp3281, i64 1
-  %tmp3283 = getelementptr inbounds float* %tmp3282, i64 1
-  %tmp3284 = getelementptr inbounds float* %tmp3283, i64 1
-  %tmp3285 = getelementptr inbounds float* %tmp3284, i64 1
-  %tmp3286 = getelementptr inbounds float* %tmp3285, i64 1
-  %tmp3287 = getelementptr inbounds float* %tmp3286, i64 1
-  %tmp3288 = getelementptr inbounds float* %tmp3287, i64 1
-  %tmp3289 = getelementptr inbounds float* %tmp3288, i64 1
-  %tmp3290 = getelementptr inbounds float* %tmp3289, i64 1
-  %tmp3291 = getelementptr inbounds float* %tmp3290, i64 1
-  %tmp3292 = getelementptr inbounds float* %tmp3291, i64 1
-  %tmp3293 = getelementptr inbounds float* %tmp3292, i64 1
-  %tmp3294 = getelementptr inbounds float* %tmp3293, i64 1
-  %tmp3295 = getelementptr inbounds float* %tmp3294, i64 1
-  %tmp3296 = getelementptr inbounds float* %tmp3295, i64 1
-  %tmp3297 = getelementptr inbounds float* %tmp3296, i64 1
-  %tmp3298 = getelementptr inbounds float* %tmp3297, i64 1
-  %tmp3299 = getelementptr inbounds float* %tmp3298, i64 1
-  %tmp3300 = getelementptr inbounds float* %tmp3299, i64 1
-  %tmp3301 = getelementptr inbounds float* %tmp3300, i64 1
-  %tmp3302 = getelementptr inbounds float* %tmp3301, i64 1
-  %tmp3303 = getelementptr inbounds float* %tmp3302, i64 1
-  %tmp3304 = getelementptr inbounds float* %tmp3303, i64 1
-  %tmp3305 = getelementptr inbounds float* %tmp3304, i64 1
-  %tmp3306 = getelementptr inbounds float* %tmp3305, i64 1
-  %tmp3307 = getelementptr inbounds float* %tmp3306, i64 1
-  %tmp3308 = getelementptr inbounds float* %tmp3307, i64 1
-  %tmp3309 = getelementptr inbounds float* %tmp3308, i64 1
-  %tmp3310 = getelementptr inbounds float* %tmp3309, i64 1
-  %tmp3311 = getelementptr inbounds float* %tmp3310, i64 1
-  %tmp3312 = getelementptr inbounds float* %tmp3311, i64 1
-  %tmp3313 = getelementptr inbounds float* %tmp3312, i64 1
-  %tmp3314 = getelementptr inbounds float* %tmp3313, i64 1
-  %tmp3315 = getelementptr inbounds float* %tmp3314, i64 1
-  %tmp3316 = getelementptr inbounds float* %tmp3315, i64 1
-  %tmp3317 = getelementptr inbounds float* %tmp3316, i64 1
-  %tmp3318 = getelementptr inbounds float* %tmp3317, i64 1
-  %tmp3319 = getelementptr inbounds float* %tmp3318, i64 1
-  %tmp3320 = getelementptr inbounds float* %tmp3319, i64 1
-  %tmp3321 = getelementptr inbounds float* %tmp3320, i64 1
-  %tmp3322 = getelementptr inbounds float* %tmp3321, i64 1
-  %tmp3323 = getelementptr inbounds float* %tmp3322, i64 1
-  %tmp3324 = getelementptr inbounds float* %tmp3323, i64 1
-  %tmp3325 = getelementptr inbounds float* %tmp3324, i64 1
-  %tmp3326 = getelementptr inbounds float* %tmp3325, i64 1
-  %tmp3327 = getelementptr inbounds float* %tmp3326, i64 1
-  %tmp3328 = getelementptr inbounds float* %tmp3327, i64 1
-  %tmp3329 = getelementptr inbounds float* %tmp3328, i64 1
-  %tmp3330 = getelementptr inbounds float* %tmp3329, i64 1
-  %tmp3331 = getelementptr inbounds float* %tmp3330, i64 1
-  %tmp3332 = getelementptr inbounds float* %tmp3331, i64 1
-  %tmp3333 = getelementptr inbounds float* %tmp3332, i64 1
-  %tmp3334 = getelementptr inbounds float* %tmp3333, i64 1
-  %tmp3335 = getelementptr inbounds float* %tmp3334, i64 1
-  %tmp3336 = getelementptr inbounds float* %tmp3335, i64 1
-  %tmp3337 = getelementptr inbounds float* %tmp3336, i64 1
-  %tmp3338 = getelementptr inbounds float* %tmp3337, i64 1
-  %tmp3339 = getelementptr inbounds float* %tmp3338, i64 1
-  %tmp3340 = getelementptr inbounds float* %tmp3339, i64 1
-  %tmp3341 = getelementptr inbounds float* %tmp3340, i64 1
-  %tmp3342 = getelementptr inbounds float* %tmp3341, i64 1
-  %tmp3343 = getelementptr inbounds float* %tmp3342, i64 1
-  %tmp3344 = getelementptr inbounds float* %tmp3343, i64 1
-  %tmp3345 = getelementptr inbounds float* %tmp3344, i64 1
-  %tmp3346 = getelementptr inbounds float* %tmp3345, i64 1
-  %tmp3347 = getelementptr inbounds float* %tmp3346, i64 1
-  %tmp3348 = getelementptr inbounds float* %tmp3347, i64 1
-  %tmp3349 = getelementptr inbounds float* %tmp3348, i64 1
-  %tmp3350 = getelementptr inbounds float* %tmp3349, i64 1
-  %tmp3351 = getelementptr inbounds float* %tmp3350, i64 1
-  %tmp3352 = getelementptr inbounds float* %tmp3351, i64 1
-  %tmp3353 = getelementptr inbounds float* %tmp3352, i64 1
-  %tmp3354 = getelementptr inbounds float* %tmp3353, i64 1
-  %tmp3355 = getelementptr inbounds float* %tmp3354, i64 1
-  %tmp3356 = getelementptr inbounds float* %tmp3355, i64 1
-  %tmp3357 = getelementptr inbounds float* %tmp3356, i64 1
-  %tmp3358 = getelementptr inbounds float* %tmp3357, i64 1
-  %tmp3359 = getelementptr inbounds float* %tmp3358, i64 1
-  %tmp3360 = getelementptr inbounds float* %tmp3359, i64 1
-  %tmp3361 = getelementptr inbounds float* %tmp3360, i64 1
-  %tmp3362 = getelementptr inbounds float* %tmp3361, i64 1
-  %tmp3363 = getelementptr inbounds float* %tmp3362, i64 1
-  %tmp3364 = getelementptr inbounds float* %tmp3363, i64 1
-  %tmp3365 = getelementptr inbounds float* %tmp3364, i64 1
-  %tmp3366 = getelementptr inbounds float* %tmp3365, i64 1
-  %tmp3367 = getelementptr inbounds float* %tmp3366, i64 1
-  %tmp3368 = getelementptr inbounds float* %tmp3367, i64 1
-  %tmp3369 = getelementptr inbounds float* %tmp3368, i64 1
-  %tmp3370 = getelementptr inbounds float* %tmp3369, i64 1
-  %tmp3371 = getelementptr inbounds float* %tmp3370, i64 1
-  %tmp3372 = getelementptr inbounds float* %tmp3371, i64 1
-  %tmp3373 = getelementptr inbounds float* %tmp3372, i64 1
-  %tmp3374 = getelementptr inbounds float* %tmp3373, i64 1
-  %tmp3375 = getelementptr inbounds float* %tmp3374, i64 1
-  %tmp3376 = getelementptr inbounds float* %tmp3375, i64 1
-  %tmp3377 = getelementptr inbounds float* %tmp3376, i64 1
-  %tmp3378 = getelementptr inbounds float* %tmp3377, i64 1
-  %tmp3379 = getelementptr inbounds float* %tmp3378, i64 1
-  %tmp3380 = getelementptr inbounds float* %tmp3379, i64 1
-  %tmp3381 = getelementptr inbounds float* %tmp3380, i64 1
-  %tmp3382 = getelementptr inbounds float* %tmp3381, i64 1
-  %tmp3383 = getelementptr inbounds float* %tmp3382, i64 1
-  %tmp3384 = getelementptr inbounds float* %tmp3383, i64 1
-  %tmp3385 = getelementptr inbounds float* %tmp3384, i64 1
-  %tmp3386 = getelementptr inbounds float* %tmp3385, i64 1
-  %tmp3387 = getelementptr inbounds float* %tmp3386, i64 1
-  %tmp3388 = getelementptr inbounds float* %tmp3387, i64 1
-  %tmp3389 = getelementptr inbounds float* %tmp3388, i64 1
-  %tmp3390 = getelementptr inbounds float* %tmp3389, i64 1
-  %tmp3391 = getelementptr inbounds float* %tmp3390, i64 1
-  %tmp3392 = getelementptr inbounds float* %tmp3391, i64 1
-  %tmp3393 = getelementptr inbounds float* %tmp3392, i64 1
-  %tmp3394 = getelementptr inbounds float* %tmp3393, i64 1
-  %tmp3395 = getelementptr inbounds float* %tmp3394, i64 1
-  %tmp3396 = getelementptr inbounds float* %tmp3395, i64 1
-  %tmp3397 = getelementptr inbounds float* %tmp3396, i64 1
-  %tmp3398 = getelementptr inbounds float* %tmp3397, i64 1
-  %tmp3399 = getelementptr inbounds float* %tmp3398, i64 1
-  %tmp3400 = getelementptr inbounds float* %tmp3399, i64 1
-  %tmp3401 = getelementptr inbounds float* %tmp3400, i64 1
-  %tmp3402 = getelementptr inbounds float* %tmp3401, i64 1
-  %tmp3403 = getelementptr inbounds float* %tmp3402, i64 1
-  %tmp3404 = getelementptr inbounds float* %tmp3403, i64 1
-  %tmp3405 = getelementptr inbounds float* %tmp3404, i64 1
-  %tmp3406 = getelementptr inbounds float* %tmp3405, i64 1
-  %tmp3407 = getelementptr inbounds float* %tmp3406, i64 1
-  %tmp3408 = getelementptr inbounds float* %tmp3407, i64 1
-  %tmp3409 = getelementptr inbounds float* %tmp3408, i64 1
-  %tmp3410 = getelementptr inbounds float* %tmp3409, i64 1
-  %tmp3411 = getelementptr inbounds float* %tmp3410, i64 1
-  %tmp3412 = getelementptr inbounds float* %tmp3411, i64 1
-  %tmp3413 = getelementptr inbounds float* %tmp3412, i64 1
-  %tmp3414 = getelementptr inbounds float* %tmp3413, i64 1
-  %tmp3415 = getelementptr inbounds float* %tmp3414, i64 1
-  %tmp3416 = getelementptr inbounds float* %tmp3415, i64 1
-  %tmp3417 = getelementptr inbounds float* %tmp3416, i64 1
-  %tmp3418 = getelementptr inbounds float* %tmp3417, i64 1
-  %tmp3419 = getelementptr inbounds float* %tmp3418, i64 1
-  %tmp3420 = getelementptr inbounds float* %tmp3419, i64 1
-  %tmp3421 = getelementptr inbounds float* %tmp3420, i64 1
-  %tmp3422 = getelementptr inbounds float* %tmp3421, i64 1
-  %tmp3423 = getelementptr inbounds float* %tmp3422, i64 1
-  %tmp3424 = getelementptr inbounds float* %tmp3423, i64 1
-  %tmp3425 = getelementptr inbounds float* %tmp3424, i64 1
-  %tmp3426 = getelementptr inbounds float* %tmp3425, i64 1
-  %tmp3427 = getelementptr inbounds float* %tmp3426, i64 1
-  %tmp3428 = getelementptr inbounds float* %tmp3427, i64 1
-  %tmp3429 = getelementptr inbounds float* %tmp3428, i64 1
-  %tmp3430 = getelementptr inbounds float* %tmp3429, i64 1
-  %tmp3431 = getelementptr inbounds float* %tmp3430, i64 1
-  %tmp3432 = getelementptr inbounds float* %tmp3431, i64 1
-  %tmp3433 = getelementptr inbounds float* %tmp3432, i64 1
-  %tmp3434 = getelementptr inbounds float* %tmp3433, i64 1
-  %tmp3435 = getelementptr inbounds float* %tmp3434, i64 1
-  %tmp3436 = getelementptr inbounds float* %tmp3435, i64 1
-  %tmp3437 = getelementptr inbounds float* %tmp3436, i64 1
-  %tmp3438 = getelementptr inbounds float* %tmp3437, i64 1
-  %tmp3439 = getelementptr inbounds float* %tmp3438, i64 1
-  %tmp3440 = getelementptr inbounds float* %tmp3439, i64 1
-  %tmp3441 = getelementptr inbounds float* %tmp3440, i64 1
-  %tmp3442 = getelementptr inbounds float* %tmp3441, i64 1
-  %tmp3443 = getelementptr inbounds float* %tmp3442, i64 1
-  %tmp3444 = getelementptr inbounds float* %tmp3443, i64 1
-  %tmp3445 = getelementptr inbounds float* %tmp3444, i64 1
-  %tmp3446 = getelementptr inbounds float* %tmp3445, i64 1
-  %tmp3447 = getelementptr inbounds float* %tmp3446, i64 1
-  %tmp3448 = getelementptr inbounds float* %tmp3447, i64 1
-  %tmp3449 = getelementptr inbounds float* %tmp3448, i64 1
-  %tmp3450 = getelementptr inbounds float* %tmp3449, i64 1
-  %tmp3451 = getelementptr inbounds float* %tmp3450, i64 1
-  %tmp3452 = getelementptr inbounds float* %tmp3451, i64 1
-  %tmp3453 = getelementptr inbounds float* %tmp3452, i64 1
-  %tmp3454 = getelementptr inbounds float* %tmp3453, i64 1
-  %tmp3455 = getelementptr inbounds float* %tmp3454, i64 1
-  %tmp3456 = getelementptr inbounds float* %tmp3455, i64 1
-  %tmp3457 = getelementptr inbounds float* %tmp3456, i64 1
-  %tmp3458 = getelementptr inbounds float* %tmp3457, i64 1
-  %tmp3459 = getelementptr inbounds float* %tmp3458, i64 1
-  %tmp3460 = getelementptr inbounds float* %tmp3459, i64 1
-  %tmp3461 = getelementptr inbounds float* %tmp3460, i64 1
-  %tmp3462 = getelementptr inbounds float* %tmp3461, i64 1
-  %tmp3463 = getelementptr inbounds float* %tmp3462, i64 1
-  %tmp3464 = getelementptr inbounds float* %tmp3463, i64 1
-  %tmp3465 = getelementptr inbounds float* %tmp3464, i64 1
-  %tmp3466 = getelementptr inbounds float* %tmp3465, i64 1
-  %tmp3467 = getelementptr inbounds float* %tmp3466, i64 1
-  %tmp3468 = getelementptr inbounds float* %tmp3467, i64 1
-  %tmp3469 = getelementptr inbounds float* %tmp3468, i64 1
-  %tmp3470 = getelementptr inbounds float* %tmp3469, i64 1
-  %tmp3471 = getelementptr inbounds float* %tmp3470, i64 1
-  %tmp3472 = getelementptr inbounds float* %tmp3471, i64 1
-  %tmp3473 = getelementptr inbounds float* %tmp3472, i64 1
-  %tmp3474 = getelementptr inbounds float* %tmp3473, i64 1
-  %tmp3475 = getelementptr inbounds float* %tmp3474, i64 1
-  %tmp3476 = getelementptr inbounds float* %tmp3475, i64 1
-  %tmp3477 = getelementptr inbounds float* %tmp3476, i64 1
-  %tmp3478 = getelementptr inbounds float* %tmp3477, i64 1
-  %tmp3479 = getelementptr inbounds float* %tmp3478, i64 1
-  %tmp3480 = getelementptr inbounds float* %tmp3479, i64 1
-  %tmp3481 = getelementptr inbounds float* %tmp3480, i64 1
-  %tmp3482 = getelementptr inbounds float* %tmp3481, i64 1
-  %tmp3483 = getelementptr inbounds float* %tmp3482, i64 1
-  %tmp3484 = getelementptr inbounds float* %tmp3483, i64 1
-  %tmp3485 = getelementptr inbounds float* %tmp3484, i64 1
-  %tmp3486 = getelementptr inbounds float* %tmp3485, i64 1
-  %tmp3487 = getelementptr inbounds float* %tmp3486, i64 1
-  %tmp3488 = getelementptr inbounds float* %tmp3487, i64 1
-  %tmp3489 = getelementptr inbounds float* %tmp3488, i64 1
-  %tmp3490 = getelementptr inbounds float* %tmp3489, i64 1
-  %tmp3491 = getelementptr inbounds float* %tmp3490, i64 1
-  %tmp3492 = getelementptr inbounds float* %tmp3491, i64 1
-  %tmp3493 = getelementptr inbounds float* %tmp3492, i64 1
-  %tmp3494 = getelementptr inbounds float* %tmp3493, i64 1
-  %tmp3495 = getelementptr inbounds float* %tmp3494, i64 1
-  %tmp3496 = getelementptr inbounds float* %tmp3495, i64 1
-  %tmp3497 = getelementptr inbounds float* %tmp3496, i64 1
-  %tmp3498 = getelementptr inbounds float* %tmp3497, i64 1
-  %tmp3499 = getelementptr inbounds float* %tmp3498, i64 1
-  %tmp3500 = getelementptr inbounds float* %tmp3499, i64 1
-  %tmp3501 = getelementptr inbounds float* %tmp3500, i64 1
-  %tmp3502 = getelementptr inbounds float* %tmp3501, i64 1
-  %tmp3503 = getelementptr inbounds float* %tmp3502, i64 1
-  %tmp3504 = getelementptr inbounds float* %tmp3503, i64 1
-  %tmp3505 = getelementptr inbounds float* %tmp3504, i64 1
-  %tmp3506 = getelementptr inbounds float* %tmp3505, i64 1
-  %tmp3507 = getelementptr inbounds float* %tmp3506, i64 1
-  %tmp3508 = getelementptr inbounds float* %tmp3507, i64 1
-  %tmp3509 = getelementptr inbounds float* %tmp3508, i64 1
-  %tmp3510 = getelementptr inbounds float* %tmp3509, i64 1
-  %tmp3511 = getelementptr inbounds float* %tmp3510, i64 1
-  %tmp3512 = getelementptr inbounds float* %tmp3511, i64 1
-  %tmp3513 = getelementptr inbounds float* %tmp3512, i64 1
-  %tmp3514 = getelementptr inbounds float* %tmp3513, i64 1
-  %tmp3515 = getelementptr inbounds float* %tmp3514, i64 1
-  %tmp3516 = getelementptr inbounds float* %tmp3515, i64 1
-  %tmp3517 = getelementptr inbounds float* %tmp3516, i64 1
-  %tmp3518 = getelementptr inbounds float* %tmp3517, i64 1
-  %tmp3519 = getelementptr inbounds float* %tmp3518, i64 1
-  %tmp3520 = getelementptr inbounds float* %tmp3519, i64 1
-  %tmp3521 = getelementptr inbounds float* %tmp3520, i64 1
-  %tmp3522 = getelementptr inbounds float* %tmp3521, i64 1
-  %tmp3523 = getelementptr inbounds float* %tmp3522, i64 1
-  %tmp3524 = getelementptr inbounds float* %tmp3523, i64 1
-  %tmp3525 = getelementptr inbounds float* %tmp3524, i64 1
-  %tmp3526 = getelementptr inbounds float* %tmp3525, i64 1
-  %tmp3527 = getelementptr inbounds float* %tmp3526, i64 1
-  %tmp3528 = getelementptr inbounds float* %tmp3527, i64 1
-  %tmp3529 = getelementptr inbounds float* %tmp3528, i64 1
-  %tmp3530 = getelementptr inbounds float* %tmp3529, i64 1
-  %tmp3531 = getelementptr inbounds float* %tmp3530, i64 1
-  %tmp3532 = getelementptr inbounds float* %tmp3531, i64 1
-  %tmp3533 = getelementptr inbounds float* %tmp3532, i64 1
-  %tmp3534 = getelementptr inbounds float* %tmp3533, i64 1
-  %tmp3535 = getelementptr inbounds float* %tmp3534, i64 1
-  %tmp3536 = getelementptr inbounds float* %tmp3535, i64 1
-  %tmp3537 = getelementptr inbounds float* %tmp3536, i64 1
-  %tmp3538 = getelementptr inbounds float* %tmp3537, i64 1
-  %tmp3539 = getelementptr inbounds float* %tmp3538, i64 1
-  %tmp3540 = getelementptr inbounds float* %tmp3539, i64 1
-  %tmp3541 = getelementptr inbounds float* %tmp3540, i64 1
-  %tmp3542 = getelementptr inbounds float* %tmp3541, i64 1
-  %tmp3543 = getelementptr inbounds float* %tmp3542, i64 1
-  %tmp3544 = getelementptr inbounds float* %tmp3543, i64 1
-  %tmp3545 = getelementptr inbounds float* %tmp3544, i64 1
-  %tmp3546 = getelementptr inbounds float* %tmp3545, i64 1
-  %tmp3547 = getelementptr inbounds float* %tmp3546, i64 1
-  %tmp3548 = getelementptr inbounds float* %tmp3547, i64 1
-  %tmp3549 = getelementptr inbounds float* %tmp3548, i64 1
-  %tmp3550 = getelementptr inbounds float* %tmp3549, i64 1
-  %tmp3551 = getelementptr inbounds float* %tmp3550, i64 1
-  %tmp3552 = getelementptr inbounds float* %tmp3551, i64 1
-  %tmp3553 = getelementptr inbounds float* %tmp3552, i64 1
-  %tmp3554 = getelementptr inbounds float* %tmp3553, i64 1
-  %tmp3555 = getelementptr inbounds float* %tmp3554, i64 1
-  %tmp3556 = getelementptr inbounds float* %tmp3555, i64 1
-  %tmp3557 = getelementptr inbounds float* %tmp3556, i64 1
-  %tmp3558 = getelementptr inbounds float* %tmp3557, i64 1
-  %tmp3559 = getelementptr inbounds float* %tmp3558, i64 1
-  %tmp3560 = getelementptr inbounds float* %tmp3559, i64 1
-  %tmp3561 = getelementptr inbounds float* %tmp3560, i64 1
-  %tmp3562 = getelementptr inbounds float* %tmp3561, i64 1
-  %tmp3563 = getelementptr inbounds float* %tmp3562, i64 1
-  %tmp3564 = getelementptr inbounds float* %tmp3563, i64 1
-  %tmp3565 = getelementptr inbounds float* %tmp3564, i64 1
-  %tmp3566 = getelementptr inbounds float* %tmp3565, i64 1
-  %tmp3567 = getelementptr inbounds float* %tmp3566, i64 1
-  %tmp3568 = getelementptr inbounds float* %tmp3567, i64 1
-  %tmp3569 = getelementptr inbounds float* %tmp3568, i64 1
-  %tmp3570 = getelementptr inbounds float* %tmp3569, i64 1
-  %tmp3571 = getelementptr inbounds float* %tmp3570, i64 1
-  %tmp3572 = getelementptr inbounds float* %tmp3571, i64 1
-  %tmp3573 = getelementptr inbounds float* %tmp3572, i64 1
-  %tmp3574 = getelementptr inbounds float* %tmp3573, i64 1
-  %tmp3575 = getelementptr inbounds float* %tmp3574, i64 1
-  %tmp3576 = getelementptr inbounds float* %tmp3575, i64 1
-  %tmp3577 = getelementptr inbounds float* %tmp3576, i64 1
-  %tmp3578 = getelementptr inbounds float* %tmp3577, i64 1
-  %tmp3579 = getelementptr inbounds float* %tmp3578, i64 1
-  %tmp3580 = getelementptr inbounds float* %tmp3579, i64 1
-  %tmp3581 = getelementptr inbounds float* %tmp3580, i64 1
-  %tmp3582 = getelementptr inbounds float* %tmp3581, i64 1
-  %tmp3583 = getelementptr inbounds float* %tmp3582, i64 1
-  %tmp3584 = getelementptr inbounds float* %tmp3583, i64 1
-  %tmp3585 = getelementptr inbounds float* %tmp3584, i64 1
-  %tmp3586 = getelementptr inbounds float* %tmp3585, i64 1
-  %tmp3587 = getelementptr inbounds float* %tmp3586, i64 1
-  %tmp3588 = getelementptr inbounds float* %tmp3587, i64 1
-  %tmp3589 = getelementptr inbounds float* %tmp3588, i64 1
-  %tmp3590 = getelementptr inbounds float* %tmp3589, i64 1
-  %tmp3591 = getelementptr inbounds float* %tmp3590, i64 1
-  %tmp3592 = getelementptr inbounds float* %tmp3591, i64 1
-  %tmp3593 = getelementptr inbounds float* %tmp3592, i64 1
-  %tmp3594 = getelementptr inbounds float* %tmp3593, i64 1
-  %tmp3595 = getelementptr inbounds float* %tmp3594, i64 1
-  %tmp3596 = getelementptr inbounds float* %tmp3595, i64 1
-  %tmp3597 = getelementptr inbounds float* %tmp3596, i64 1
-  %tmp3598 = getelementptr inbounds float* %tmp3597, i64 1
-  %tmp3599 = getelementptr inbounds float* %tmp3598, i64 1
-  %tmp3600 = getelementptr inbounds float* %tmp3599, i64 1
-  %tmp3601 = getelementptr inbounds float* %tmp3600, i64 1
-  %tmp3602 = getelementptr inbounds float* %tmp3601, i64 1
-  %tmp3603 = getelementptr inbounds float* %tmp3602, i64 1
-  %tmp3604 = getelementptr inbounds float* %tmp3603, i64 1
-  %tmp3605 = getelementptr inbounds float* %tmp3604, i64 1
-  %tmp3606 = getelementptr inbounds float* %tmp3605, i64 1
-  %tmp3607 = getelementptr inbounds float* %tmp3606, i64 1
-  %tmp3608 = getelementptr inbounds float* %tmp3607, i64 1
-  %tmp3609 = getelementptr inbounds float* %tmp3608, i64 1
-  %tmp3610 = getelementptr inbounds float* %tmp3609, i64 1
-  %tmp3611 = getelementptr inbounds float* %tmp3610, i64 1
-  %tmp3612 = getelementptr inbounds float* %tmp3611, i64 1
-  %tmp3613 = getelementptr inbounds float* %tmp3612, i64 1
-  %tmp3614 = getelementptr inbounds float* %tmp3613, i64 1
-  %tmp3615 = getelementptr inbounds float* %tmp3614, i64 1
-  %tmp3616 = getelementptr inbounds float* %tmp3615, i64 1
-  %tmp3617 = getelementptr inbounds float* %tmp3616, i64 1
-  %tmp3618 = getelementptr inbounds float* %tmp3617, i64 1
-  %tmp3619 = getelementptr inbounds float* %tmp3618, i64 1
-  %tmp3620 = getelementptr inbounds float* %tmp3619, i64 1
-  %tmp3621 = getelementptr inbounds float* %tmp3620, i64 1
-  %tmp3622 = getelementptr inbounds float* %tmp3621, i64 1
-  %tmp3623 = getelementptr inbounds float* %tmp3622, i64 1
-  %tmp3624 = getelementptr inbounds float* %tmp3623, i64 1
-  %tmp3625 = getelementptr inbounds float* %tmp3624, i64 1
-  %tmp3626 = getelementptr inbounds float* %tmp3625, i64 1
-  %tmp3627 = getelementptr inbounds float* %tmp3626, i64 1
-  %tmp3628 = getelementptr inbounds float* %tmp3627, i64 1
-  %tmp3629 = getelementptr inbounds float* %tmp3628, i64 1
-  %tmp3630 = getelementptr inbounds float* %tmp3629, i64 1
-  %tmp3631 = getelementptr inbounds float* %tmp3630, i64 1
-  %tmp3632 = getelementptr inbounds float* %tmp3631, i64 1
-  %tmp3633 = getelementptr inbounds float* %tmp3632, i64 1
-  %tmp3634 = getelementptr inbounds float* %tmp3633, i64 1
-  %tmp3635 = getelementptr inbounds float* %tmp3634, i64 1
-  %tmp3636 = getelementptr inbounds float* %tmp3635, i64 1
-  %tmp3637 = getelementptr inbounds float* %tmp3636, i64 1
-  %tmp3638 = getelementptr inbounds float* %tmp3637, i64 1
-  %tmp3639 = getelementptr inbounds float* %tmp3638, i64 1
-  %tmp3640 = getelementptr inbounds float* %tmp3639, i64 1
-  %tmp3641 = getelementptr inbounds float* %tmp3640, i64 1
-  %tmp3642 = getelementptr inbounds float* %tmp3641, i64 1
-  %tmp3643 = getelementptr inbounds float* %tmp3642, i64 1
-  %tmp3644 = getelementptr inbounds float* %tmp3643, i64 1
-  %tmp3645 = getelementptr inbounds float* %tmp3644, i64 1
-  %tmp3646 = getelementptr inbounds float* %tmp3645, i64 1
-  %tmp3647 = getelementptr inbounds float* %tmp3646, i64 1
-  %tmp3648 = getelementptr inbounds float* %tmp3647, i64 1
-  %tmp3649 = getelementptr inbounds float* %tmp3648, i64 1
-  %tmp3650 = getelementptr inbounds float* %tmp3649, i64 1
-  %tmp3651 = getelementptr inbounds float* %tmp3650, i64 1
-  %tmp3652 = getelementptr inbounds float* %tmp3651, i64 1
-  %tmp3653 = getelementptr inbounds float* %tmp3652, i64 1
-  %tmp3654 = getelementptr inbounds float* %tmp3653, i64 1
-  %tmp3655 = getelementptr inbounds float* %tmp3654, i64 1
-  %tmp3656 = getelementptr inbounds float* %tmp3655, i64 1
-  %tmp3657 = getelementptr inbounds float* %tmp3656, i64 1
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-  %tmp3659 = getelementptr inbounds float* %tmp3658, i64 1
-  %tmp3660 = getelementptr inbounds float* %tmp3659, i64 1
-  %tmp3661 = getelementptr inbounds float* %tmp3660, i64 1
-  %tmp3662 = getelementptr inbounds float* %tmp3661, i64 1
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-  %tmp3665 = getelementptr inbounds float* %tmp3664, i64 1
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-  %tmp3667 = getelementptr inbounds float* %tmp3666, i64 1
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-  %tmp3669 = getelementptr inbounds float* %tmp3668, i64 1
-  %tmp3670 = getelementptr inbounds float* %tmp3669, i64 1
-  %tmp3671 = getelementptr inbounds float* %tmp3670, i64 1
-  %tmp3672 = getelementptr inbounds float* %tmp3671, i64 1
-  %tmp3673 = getelementptr inbounds float* %tmp3672, i64 1
-  %tmp3674 = getelementptr inbounds float* %tmp3673, i64 1
-  %tmp3675 = getelementptr inbounds float* %tmp3674, i64 1
-  %tmp3676 = getelementptr inbounds float* %tmp3675, i64 1
-  %tmp3677 = getelementptr inbounds float* %tmp3676, i64 1
-  %tmp3678 = getelementptr inbounds float* %tmp3677, i64 1
-  %tmp3679 = getelementptr inbounds float* %tmp3678, i64 1
-  %tmp3680 = getelementptr inbounds float* %tmp3679, i64 1
-  %tmp3681 = getelementptr inbounds float* %tmp3680, i64 1
-  %tmp3682 = getelementptr inbounds float* %tmp3681, i64 1
-  %tmp3683 = getelementptr inbounds float* %tmp3682, i64 1
-  %tmp3684 = getelementptr inbounds float* %tmp3683, i64 1
-  %tmp3685 = getelementptr inbounds float* %tmp3684, i64 1
-  %tmp3686 = getelementptr inbounds float* %tmp3685, i64 1
-  %tmp3687 = getelementptr inbounds float* %tmp3686, i64 1
-  %tmp3688 = getelementptr inbounds float* %tmp3687, i64 1
-  %tmp3689 = getelementptr inbounds float* %tmp3688, i64 1
-  %tmp3690 = getelementptr inbounds float* %tmp3689, i64 1
-  %tmp3691 = getelementptr inbounds float* %tmp3690, i64 1
-  %tmp3692 = getelementptr inbounds float* %tmp3691, i64 1
-  %tmp3693 = getelementptr inbounds float* %tmp3692, i64 1
-  %tmp3694 = getelementptr inbounds float* %tmp3693, i64 1
-  %tmp3695 = getelementptr inbounds float* %tmp3694, i64 1
-  %tmp3696 = getelementptr inbounds float* %tmp3695, i64 1
-  %tmp3697 = getelementptr inbounds float* %tmp3696, i64 1
-  %tmp3698 = getelementptr inbounds float* %tmp3697, i64 1
-  %tmp3699 = getelementptr inbounds float* %tmp3698, i64 1
-  %tmp3700 = getelementptr inbounds float* %tmp3699, i64 1
-  %tmp3701 = getelementptr inbounds float* %tmp3700, i64 1
-  %tmp3702 = getelementptr inbounds float* %tmp3701, i64 1
-  %tmp3703 = getelementptr inbounds float* %tmp3702, i64 1
-  %tmp3704 = getelementptr inbounds float* %tmp3703, i64 1
-  %tmp3705 = getelementptr inbounds float* %tmp3704, i64 1
-  %tmp3706 = getelementptr inbounds float* %tmp3705, i64 1
-  %tmp3707 = getelementptr inbounds float* %tmp3706, i64 1
-  %tmp3708 = getelementptr inbounds float* %tmp3707, i64 1
-  %tmp3709 = getelementptr inbounds float* %tmp3708, i64 1
-  %tmp3710 = getelementptr inbounds float* %tmp3709, i64 1
-  %tmp3711 = getelementptr inbounds float* %tmp3710, i64 1
-  %tmp3712 = getelementptr inbounds float* %tmp3711, i64 1
-  %tmp3713 = getelementptr inbounds float* %tmp3712, i64 1
-  %tmp3714 = getelementptr inbounds float* %tmp3713, i64 1
-  %tmp3715 = getelementptr inbounds float* %tmp3714, i64 1
-  %tmp3716 = getelementptr inbounds float* %tmp3715, i64 1
-  %tmp3717 = getelementptr inbounds float* %tmp3716, i64 1
-  %tmp3718 = getelementptr inbounds float* %tmp3717, i64 1
-  %tmp3719 = getelementptr inbounds float* %tmp3718, i64 1
-  %tmp3720 = getelementptr inbounds float* %tmp3719, i64 1
-  %tmp3721 = getelementptr inbounds float* %tmp3720, i64 1
-  %tmp3722 = getelementptr inbounds float* %tmp3721, i64 1
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-  %tmp3724 = getelementptr inbounds float* %tmp3723, i64 1
-  %tmp3725 = getelementptr inbounds float* %tmp3724, i64 1
-  %tmp3726 = getelementptr inbounds float* %tmp3725, i64 1
-  %tmp3727 = getelementptr inbounds float* %tmp3726, i64 1
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-  %tmp3738 = getelementptr inbounds float* %tmp3737, i64 1
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-  %tmp3742 = getelementptr inbounds float* %tmp3741, i64 1
-  %tmp3743 = getelementptr inbounds float* %tmp3742, i64 1
-  %tmp3744 = getelementptr inbounds float* %tmp3743, i64 1
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-  %tmp3746 = getelementptr inbounds float* %tmp3745, i64 1
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-  %tmp3789 = getelementptr inbounds float* %tmp3788, i64 1
-  %tmp3790 = getelementptr inbounds float* %tmp3789, i64 1
-  %tmp3791 = getelementptr inbounds float* %tmp3790, i64 1
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-  %tmp3793 = getelementptr inbounds float* %tmp3792, i64 1
-  %tmp3794 = getelementptr inbounds float* %tmp3793, i64 1
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-  %tmp3796 = getelementptr inbounds float* %tmp3795, i64 1
-  %tmp3797 = getelementptr inbounds float* %tmp3796, i64 1
-  %tmp3798 = getelementptr inbounds float* %tmp3797, i64 1
-  %tmp3799 = getelementptr inbounds float* %tmp3798, i64 1
-  %tmp3800 = getelementptr inbounds float* %tmp3799, i64 1
-  %tmp3801 = getelementptr inbounds float* %tmp3800, i64 1
-  %tmp3802 = getelementptr inbounds float* %tmp3801, i64 1
-  %tmp3803 = getelementptr inbounds float* %tmp3802, i64 1
-  %tmp3804 = getelementptr inbounds float* %tmp3803, i64 1
-  %tmp3805 = getelementptr inbounds float* %tmp3804, i64 1
-  %tmp3806 = getelementptr inbounds float* %tmp3805, i64 1
-  %tmp3807 = getelementptr inbounds float* %tmp3806, i64 1
-  %tmp3808 = getelementptr inbounds float* %tmp3807, i64 1
-  %tmp3809 = getelementptr inbounds float* %tmp3808, i64 1
-  %tmp3810 = getelementptr inbounds float* %tmp3809, i64 1
-  %tmp3811 = getelementptr inbounds float* %tmp3810, i64 1
-  %tmp3812 = getelementptr inbounds float* %tmp3811, i64 1
-  %tmp3813 = getelementptr inbounds float* %tmp3812, i64 1
-  %tmp3814 = getelementptr inbounds float* %tmp3813, i64 1
-  %tmp3815 = getelementptr inbounds float* %tmp3814, i64 1
-  %tmp3816 = getelementptr inbounds float* %tmp3815, i64 1
-  %tmp3817 = getelementptr inbounds float* %tmp3816, i64 1
-  %tmp3818 = getelementptr inbounds float* %tmp3817, i64 1
-  %tmp3819 = getelementptr inbounds float* %tmp3818, i64 1
-  %tmp3820 = getelementptr inbounds float* %tmp3819, i64 1
-  %tmp3821 = getelementptr inbounds float* %tmp3820, i64 1
-  %tmp3822 = getelementptr inbounds float* %tmp3821, i64 1
-  %tmp3823 = getelementptr inbounds float* %tmp3822, i64 1
-  %tmp3824 = getelementptr inbounds float* %tmp3823, i64 1
-  %tmp3825 = getelementptr inbounds float* %tmp3824, i64 1
-  %tmp3826 = getelementptr inbounds float* %tmp3825, i64 1
-  %tmp3827 = getelementptr inbounds float* %tmp3826, i64 1
-  %tmp3828 = getelementptr inbounds float* %tmp3827, i64 1
-  %tmp3829 = getelementptr inbounds float* %tmp3828, i64 1
-  %tmp3830 = getelementptr inbounds float* %tmp3829, i64 1
-  %tmp3831 = getelementptr inbounds float* %tmp3830, i64 1
-  %tmp3832 = getelementptr inbounds float* %tmp3831, i64 1
-  %tmp3833 = getelementptr inbounds float* %tmp3832, i64 1
-  %tmp3834 = getelementptr inbounds float* %tmp3833, i64 1
-  %tmp3835 = getelementptr inbounds float* %tmp3834, i64 1
-  %tmp3836 = getelementptr inbounds float* %tmp3835, i64 1
-  %tmp3837 = getelementptr inbounds float* %tmp3836, i64 1
-  %tmp3838 = getelementptr inbounds float* %tmp3837, i64 1
-  %tmp3839 = getelementptr inbounds float* %tmp3838, i64 1
-  %tmp3840 = getelementptr inbounds float* %tmp3839, i64 1
-  %tmp3841 = getelementptr inbounds float* %tmp3840, i64 1
-  %tmp3842 = getelementptr inbounds float* %tmp3841, i64 1
-  %tmp3843 = getelementptr inbounds float* %tmp3842, i64 1
-  %tmp3844 = getelementptr inbounds float* %tmp3843, i64 1
-  %tmp3845 = getelementptr inbounds float* %tmp3844, i64 1
-  %tmp3846 = getelementptr inbounds float* %tmp3845, i64 1
-  %tmp3847 = getelementptr inbounds float* %tmp3846, i64 1
-  %tmp3848 = getelementptr inbounds float* %tmp3847, i64 1
-  %tmp3849 = getelementptr inbounds float* %tmp3848, i64 1
-  %tmp3850 = getelementptr inbounds float* %tmp3849, i64 1
-  %tmp3851 = getelementptr inbounds float* %tmp3850, i64 1
-  %tmp3852 = getelementptr inbounds float* %tmp3851, i64 1
-  %tmp3853 = getelementptr inbounds float* %tmp3852, i64 1
-  %tmp3854 = getelementptr inbounds float* %tmp3853, i64 1
-  %tmp3855 = getelementptr inbounds float* %tmp3854, i64 1
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-  %tmp3857 = getelementptr inbounds float* %tmp3856, i64 1
-  %tmp3858 = getelementptr inbounds float* %tmp3857, i64 1
-  %tmp3859 = getelementptr inbounds float* %tmp3858, i64 1
-  %tmp3860 = getelementptr inbounds float* %tmp3859, i64 1
-  %tmp3861 = getelementptr inbounds float* %tmp3860, i64 1
-  %tmp3862 = getelementptr inbounds float* %tmp3861, i64 1
-  %tmp3863 = getelementptr inbounds float* %tmp3862, i64 1
-  %tmp3864 = getelementptr inbounds float* %tmp3863, i64 1
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-  %tmp3866 = getelementptr inbounds float* %tmp3865, i64 1
-  %tmp3867 = getelementptr inbounds float* %tmp3866, i64 1
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-  %tmp3869 = getelementptr inbounds float* %tmp3868, i64 1
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-  %tmp3872 = getelementptr inbounds float* %tmp3871, i64 1
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-  %tmp3874 = getelementptr inbounds float* %tmp3873, i64 1
-  %tmp3875 = getelementptr inbounds float* %tmp3874, i64 1
-  %tmp3876 = getelementptr inbounds float* %tmp3875, i64 1
-  %tmp3877 = getelementptr inbounds float* %tmp3876, i64 1
-  %tmp3878 = getelementptr inbounds float* %tmp3877, i64 1
-  %tmp3879 = getelementptr inbounds float* %tmp3878, i64 1
-  %tmp3880 = getelementptr inbounds float* %tmp3879, i64 1
-  %tmp3881 = getelementptr inbounds float* %tmp3880, i64 1
-  %tmp3882 = getelementptr inbounds float* %tmp3881, i64 1
-  %tmp3883 = getelementptr inbounds float* %tmp3882, i64 1
-  %tmp3884 = getelementptr inbounds float* %tmp3883, i64 1
-  %tmp3885 = getelementptr inbounds float* %tmp3884, i64 1
-  %tmp3886 = getelementptr inbounds float* %tmp3885, i64 1
-  %tmp3887 = getelementptr inbounds float* %tmp3886, i64 1
-  %tmp3888 = getelementptr inbounds float* %tmp3887, i64 1
-  %tmp3889 = getelementptr inbounds float* %tmp3888, i64 1
-  %tmp3890 = getelementptr inbounds float* %tmp3889, i64 1
-  %tmp3891 = getelementptr inbounds float* %tmp3890, i64 1
-  %tmp3892 = getelementptr inbounds float* %tmp3891, i64 1
-  %tmp3893 = getelementptr inbounds float* %tmp3892, i64 1
-  %tmp3894 = getelementptr inbounds float* %tmp3893, i64 1
-  %tmp3895 = getelementptr inbounds float* %tmp3894, i64 1
-  %tmp3896 = getelementptr inbounds float* %tmp3895, i64 1
-  %tmp3897 = getelementptr inbounds float* %tmp3896, i64 1
-  %tmp3898 = getelementptr inbounds float* %tmp3897, i64 1
-  %tmp3899 = getelementptr inbounds float* %tmp3898, i64 1
-  %tmp3900 = getelementptr inbounds float* %tmp3899, i64 1
-  %tmp3901 = getelementptr inbounds float* %tmp3900, i64 1
-  %tmp3902 = getelementptr inbounds float* %tmp3901, i64 1
-  %tmp3903 = getelementptr inbounds float* %tmp3902, i64 1
-  %tmp3904 = getelementptr inbounds float* %tmp3903, i64 1
-  %tmp3905 = getelementptr inbounds float* %tmp3904, i64 1
-  %tmp3906 = getelementptr inbounds float* %tmp3905, i64 1
-  %tmp3907 = getelementptr inbounds float* %tmp3906, i64 1
-  %tmp3908 = getelementptr inbounds float* %tmp3907, i64 1
-  %tmp3909 = getelementptr inbounds float* %tmp3908, i64 1
-  %tmp3910 = getelementptr inbounds float* %tmp3909, i64 1
-  %tmp3911 = getelementptr inbounds float* %tmp3910, i64 1
-  %tmp3912 = getelementptr inbounds float* %tmp3911, i64 1
-  %tmp3913 = getelementptr inbounds float* %tmp3912, i64 1
-  %tmp3914 = getelementptr inbounds float* %tmp3913, i64 1
-  %tmp3915 = getelementptr inbounds float* %tmp3914, i64 1
-  %tmp3916 = getelementptr inbounds float* %tmp3915, i64 1
-  %tmp3917 = getelementptr inbounds float* %tmp3916, i64 1
-  %tmp3918 = getelementptr inbounds float* %tmp3917, i64 1
-  %tmp3919 = getelementptr inbounds float* %tmp3918, i64 1
-  %tmp3920 = getelementptr inbounds float* %tmp3919, i64 1
-  %tmp3921 = getelementptr inbounds float* %tmp3920, i64 1
-  %tmp3922 = getelementptr inbounds float* %tmp3921, i64 1
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-  %tmp3925 = getelementptr inbounds float* %tmp3924, i64 1
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-  %tmp3938 = getelementptr inbounds float* %tmp3937, i64 1
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-  %tmp3941 = getelementptr inbounds float* %tmp3940, i64 1
-  %tmp3942 = getelementptr inbounds float* %tmp3941, i64 1
-  %tmp3943 = getelementptr inbounds float* %tmp3942, i64 1
-  %tmp3944 = getelementptr inbounds float* %tmp3943, i64 1
-  %tmp3945 = getelementptr inbounds float* %tmp3944, i64 1
-  %tmp3946 = getelementptr inbounds float* %tmp3945, i64 1
-  %tmp3947 = getelementptr inbounds float* %tmp3946, i64 1
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-  %tmp3949 = getelementptr inbounds float* %tmp3948, i64 1
-  %tmp3950 = getelementptr inbounds float* %tmp3949, i64 1
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-  %tmp3978 = getelementptr inbounds float* %tmp3977, i64 1
-  %tmp3979 = getelementptr inbounds float* %tmp3978, i64 1
-  %tmp3980 = getelementptr inbounds float* %tmp3979, i64 1
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-  %tmp3985 = getelementptr inbounds float* %tmp3984, i64 1
-  %tmp3986 = getelementptr inbounds float* %tmp3985, i64 1
-  %tmp3987 = getelementptr inbounds float* %tmp3986, i64 1
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-  %tmp3989 = getelementptr inbounds float* %tmp3988, i64 1
-  %tmp3990 = getelementptr inbounds float* %tmp3989, i64 1
-  %tmp3991 = getelementptr inbounds float* %tmp3990, i64 1
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-  %tmp3999 = getelementptr inbounds float* %tmp3998, i64 1
-  %tmp4000 = getelementptr inbounds float* %tmp3999, i64 1
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-  %tmp4008 = getelementptr inbounds float* %tmp4007, i64 1
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-  %tmp4010 = getelementptr inbounds float* %tmp4009, i64 1
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-  %tmp4012 = getelementptr inbounds float* %tmp4011, i64 1
-  %tmp4013 = getelementptr inbounds float* %tmp4012, i64 1
-  %tmp4014 = getelementptr inbounds float* %tmp4013, i64 1
-  %tmp4015 = getelementptr inbounds float* %tmp4014, i64 1
-  %tmp4016 = getelementptr inbounds float* %tmp4015, i64 1
-  %tmp4017 = getelementptr inbounds float* %tmp4016, i64 1
-  %tmp4018 = getelementptr inbounds float* %tmp4017, i64 1
-  %tmp4019 = getelementptr inbounds float* %tmp4018, i64 1
-  %tmp4020 = getelementptr inbounds float* %tmp4019, i64 1
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-  %tmp4026 = getelementptr inbounds float* %tmp4025, i64 1
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-  %tmp4162 = getelementptr inbounds float* %tmp4161, i64 1
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-  %tmp4165 = getelementptr inbounds float* %tmp4164, i64 1
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-  %tmp4172 = getelementptr inbounds float* %tmp4171, i64 1
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-  %tmp4208 = getelementptr inbounds float* %tmp4207, i64 1
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-  %tmp4228 = getelementptr inbounds float* %tmp4227, i64 1
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-  %tmp4230 = getelementptr inbounds float* %tmp4229, i64 1
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-  %tmp4237 = getelementptr inbounds float* %tmp4236, i64 1
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-  %tmp4476 = getelementptr inbounds float* %tmp4475, i64 1
-  %tmp4477 = getelementptr inbounds float* %tmp4476, i64 1
-  %tmp4478 = getelementptr inbounds float* %tmp4477, i64 1
-  %tmp4479 = getelementptr inbounds float* %tmp4478, i64 1
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-  %tmp4482 = getelementptr inbounds float* %tmp4481, i64 1
-  %tmp4483 = getelementptr inbounds float* %tmp4482, i64 1
-  %tmp4484 = getelementptr inbounds float* %tmp4483, i64 1
-  %tmp4485 = getelementptr inbounds float* %tmp4484, i64 1
-  %tmp4486 = getelementptr inbounds float* %tmp4485, i64 1
-  %tmp4487 = getelementptr inbounds float* %tmp4486, i64 1
-  %tmp4488 = getelementptr inbounds float* %tmp4487, i64 1
-  %tmp4489 = getelementptr inbounds float* %tmp4488, i64 1
-  %tmp4490 = getelementptr inbounds float* %tmp4489, i64 1
-  %tmp4491 = getelementptr inbounds float* %tmp4490, i64 1
-  %tmp4492 = getelementptr inbounds float* %tmp4491, i64 1
-  %tmp4493 = getelementptr inbounds float* %tmp4492, i64 1
-  %tmp4494 = getelementptr inbounds float* %tmp4493, i64 1
-  %tmp4495 = getelementptr inbounds float* %tmp4494, i64 1
-  %tmp4496 = getelementptr inbounds float* %tmp4495, i64 1
-  %tmp4497 = getelementptr inbounds float* %tmp4496, i64 1
-  %tmp4498 = getelementptr inbounds float* %tmp4497, i64 1
-  %tmp4499 = getelementptr inbounds float* %tmp4498, i64 1
-  %tmp4500 = getelementptr inbounds float* %tmp4499, i64 1
-  %tmp4501 = getelementptr inbounds float* %tmp4500, i64 1
-  %tmp4502 = getelementptr inbounds float* %tmp4501, i64 1
-  %tmp4503 = getelementptr inbounds float* %tmp4502, i64 1
-  %tmp4504 = getelementptr inbounds float* %tmp4503, i64 1
-  %tmp4505 = getelementptr inbounds float* %tmp4504, i64 1
-  %tmp4506 = getelementptr inbounds float* %tmp4505, i64 1
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-  %tmp4517 = getelementptr inbounds float* %tmp4516, i64 1
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-  %tmp4520 = getelementptr inbounds float* %tmp4519, i64 1
-  %tmp4521 = getelementptr inbounds float* %tmp4520, i64 1
-  %tmp4522 = getelementptr inbounds float* %tmp4521, i64 1
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-  %tmp4525 = getelementptr inbounds float* %tmp4524, i64 1
-  %tmp4526 = getelementptr inbounds float* %tmp4525, i64 1
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-  %tmp4542 = getelementptr inbounds float* %tmp4541, i64 1
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-  %tmp4544 = getelementptr inbounds float* %tmp4543, i64 1
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-  %tmp4547 = getelementptr inbounds float* %tmp4546, i64 1
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-  %tmp4552 = getelementptr inbounds float* %tmp4551, i64 1
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-  %tmp4554 = getelementptr inbounds float* %tmp4553, i64 1
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-  %tmp4559 = getelementptr inbounds float* %tmp4558, i64 1
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-  %tmp10239 = getelementptr inbounds float* %tmp10238, i64 1
-  %tmp10240 = getelementptr inbounds float* %tmp10239, i64 1
-  %tmp10241 = getelementptr inbounds float* %tmp10240, i64 1
-  %tmp10242 = getelementptr inbounds float* %tmp10241, i64 1
-  %tmp10243 = getelementptr inbounds float* %tmp10242, i64 1
-  %tmp10244 = getelementptr inbounds float* %tmp10243, i64 1
-  %tmp10245 = getelementptr inbounds float* %tmp10244, i64 1
-  %tmp10246 = getelementptr inbounds float* %tmp10245, i64 1
-  %tmp10247 = getelementptr inbounds float* %tmp10246, i64 1
-  %tmp10248 = getelementptr inbounds float* %tmp10247, i64 1
-  %tmp10249 = getelementptr inbounds float* %tmp10248, i64 1
-  %tmp10250 = getelementptr inbounds float* %tmp10249, i64 1
-  %tmp10251 = getelementptr inbounds float* %tmp10250, i64 1
-  %tmp10252 = getelementptr inbounds float* %tmp10251, i64 1
-  %tmp10253 = getelementptr inbounds float* %tmp10252, i64 1
-  %tmp10254 = getelementptr inbounds float* %tmp10253, i64 1
-  %tmp10255 = getelementptr inbounds float* %tmp10254, i64 1
-  %tmp10256 = getelementptr inbounds float* %tmp10255, i64 1
-  %tmp10257 = getelementptr inbounds float* %tmp10256, i64 1
-  %tmp10258 = getelementptr inbounds float* %tmp10257, i64 1
-  %tmp10259 = getelementptr inbounds float* %tmp10258, i64 1
-  %tmp10260 = getelementptr inbounds float* %tmp10259, i64 1
-  %tmp10261 = getelementptr inbounds float* %tmp10260, i64 1
-  %tmp10262 = getelementptr inbounds float* %tmp10261, i64 1
-  %tmp10263 = getelementptr inbounds float* %tmp10262, i64 1
-  %tmp10264 = getelementptr inbounds float* %tmp10263, i64 1
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-  %tmp10266 = getelementptr inbounds float* %tmp10265, i64 1
-  %tmp10267 = getelementptr inbounds float* %tmp10266, i64 1
-  %tmp10268 = getelementptr inbounds float* %tmp10267, i64 1
-  %tmp10269 = getelementptr inbounds float* %tmp10268, i64 1
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-  %tmp10272 = getelementptr inbounds float* %tmp10271, i64 1
-  %tmp10273 = getelementptr inbounds float* %tmp10272, i64 1
-  %tmp10274 = getelementptr inbounds float* %tmp10273, i64 1
-  %tmp10275 = getelementptr inbounds float* %tmp10274, i64 1
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-  %tmp10284 = getelementptr inbounds float* %tmp10283, i64 1
-  %tmp10285 = getelementptr inbounds float* %tmp10284, i64 1
-  %tmp10286 = getelementptr inbounds float* %tmp10285, i64 1
-  %tmp10287 = getelementptr inbounds float* %tmp10286, i64 1
-  %tmp10288 = getelementptr inbounds float* %tmp10287, i64 1
-  %tmp10289 = getelementptr inbounds float* %tmp10288, i64 1
-  %tmp10290 = getelementptr inbounds float* %tmp10289, i64 1
-  %tmp10291 = getelementptr inbounds float* %tmp10290, i64 1
-  %tmp10292 = getelementptr inbounds float* %tmp10291, i64 1
-  %tmp10293 = getelementptr inbounds float* %tmp10292, i64 1
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-  %tmp10295 = getelementptr inbounds float* %tmp10294, i64 1
-  %tmp10296 = getelementptr inbounds float* %tmp10295, i64 1
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-  %tmp10303 = getelementptr inbounds float* %tmp10302, i64 1
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-  %tmp10306 = getelementptr inbounds float* %tmp10305, i64 1
-  %tmp10307 = getelementptr inbounds float* %tmp10306, i64 1
-  %tmp10308 = getelementptr inbounds float* %tmp10307, i64 1
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-  %tmp10313 = getelementptr inbounds float* %tmp10312, i64 1
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-  %tmp10317 = getelementptr inbounds float* %tmp10316, i64 1
-  %tmp10318 = getelementptr inbounds float* %tmp10317, i64 1
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-  %tmp10320 = getelementptr inbounds float* %tmp10319, i64 1
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-  %tmp10322 = getelementptr inbounds float* %tmp10321, i64 1
-  %tmp10323 = getelementptr inbounds float* %tmp10322, i64 1
-  %tmp10324 = getelementptr inbounds float* %tmp10323, i64 1
-  %tmp10325 = getelementptr inbounds float* %tmp10324, i64 1
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-  %tmp10328 = getelementptr inbounds float* %tmp10327, i64 1
-  %tmp10329 = getelementptr inbounds float* %tmp10328, i64 1
-  %tmp10330 = getelementptr inbounds float* %tmp10329, i64 1
-  %tmp10331 = getelementptr inbounds float* %tmp10330, i64 1
-  %tmp10332 = getelementptr inbounds float* %tmp10331, i64 1
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-  %tmp10334 = getelementptr inbounds float* %tmp10333, i64 1
-  %tmp10335 = getelementptr inbounds float* %tmp10334, i64 1
-  %tmp10336 = getelementptr inbounds float* %tmp10335, i64 1
-  %tmp10337 = getelementptr inbounds float* %tmp10336, i64 1
-  %tmp10338 = getelementptr inbounds float* %tmp10337, i64 1
-  %tmp10339 = getelementptr inbounds float* %tmp10338, i64 1
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-  %tmp10342 = getelementptr inbounds float* %tmp10341, i64 1
-  %tmp10343 = getelementptr inbounds float* %tmp10342, i64 1
-  %tmp10344 = getelementptr inbounds float* %tmp10343, i64 1
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-  %tmp10346 = getelementptr inbounds float* %tmp10345, i64 1
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-  %tmp10352 = getelementptr inbounds float* %tmp10351, i64 1
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-  %tmp10354 = getelementptr inbounds float* %tmp10353, i64 1
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-  %tmp10357 = getelementptr inbounds float* %tmp10356, i64 1
-  %tmp10358 = getelementptr inbounds float* %tmp10357, i64 1
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-  %tmp10576 = getelementptr inbounds float* %tmp10575, i64 1
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-  %tmp10578 = getelementptr inbounds float* %tmp10577, i64 1
-  %tmp10579 = getelementptr inbounds float* %tmp10578, i64 1
-  %tmp10580 = getelementptr inbounds float* %tmp10579, i64 1
-  %tmp10581 = getelementptr inbounds float* %tmp10580, i64 1
-  %tmp10582 = getelementptr inbounds float* %tmp10581, i64 1
-  %tmp10583 = getelementptr inbounds float* %tmp10582, i64 1
-  %tmp10584 = getelementptr inbounds float* %tmp10583, i64 1
-  %tmp10585 = getelementptr inbounds float* %tmp10584, i64 1
-  %tmp10586 = getelementptr inbounds float* %tmp10585, i64 1
-  %tmp10587 = getelementptr inbounds float* %tmp10586, i64 1
-  %tmp10588 = getelementptr inbounds float* %tmp10587, i64 1
-  %tmp10589 = getelementptr inbounds float* %tmp10588, i64 1
-  %tmp10590 = getelementptr inbounds float* %tmp10589, i64 1
-  %tmp10591 = getelementptr inbounds float* %tmp10590, i64 1
-  %tmp10592 = getelementptr inbounds float* %tmp10591, i64 1
-  %tmp10593 = getelementptr inbounds float* %tmp10592, i64 1
-  %tmp10594 = getelementptr inbounds float* %tmp10593, i64 1
-  %tmp10595 = getelementptr inbounds float* %tmp10594, i64 1
-  %tmp10596 = getelementptr inbounds float* %tmp10595, i64 1
-  %tmp10597 = getelementptr inbounds float* %tmp10596, i64 1
-  %tmp10598 = getelementptr inbounds float* %tmp10597, i64 1
-  %tmp10599 = getelementptr inbounds float* %tmp10598, i64 1
-  %tmp10600 = getelementptr inbounds float* %tmp10599, i64 1
-  %tmp10601 = getelementptr inbounds float* %tmp10600, i64 1
-  %tmp10602 = getelementptr inbounds float* %tmp10601, i64 1
-  %tmp10603 = getelementptr inbounds float* %tmp10602, i64 1
-  %tmp10604 = getelementptr inbounds float* %tmp10603, i64 1
-  %tmp10605 = getelementptr inbounds float* %tmp10604, i64 1
-  %tmp10606 = getelementptr inbounds float* %tmp10605, i64 1
-  %tmp10607 = getelementptr inbounds float* %tmp10606, i64 1
-  %tmp10608 = getelementptr inbounds float* %tmp10607, i64 1
-  %tmp10609 = getelementptr inbounds float* %tmp10608, i64 1
-  %tmp10610 = getelementptr inbounds float* %tmp10609, i64 1
-  %tmp10611 = getelementptr inbounds float* %tmp10610, i64 1
-  %tmp10612 = getelementptr inbounds float* %tmp10611, i64 1
-  %tmp10613 = getelementptr inbounds float* %tmp10612, i64 1
-  %tmp10614 = getelementptr inbounds float* %tmp10613, i64 1
-  %tmp10615 = getelementptr inbounds float* %tmp10614, i64 1
-  %tmp10616 = getelementptr inbounds float* %tmp10615, i64 1
-  %tmp10617 = getelementptr inbounds float* %tmp10616, i64 1
-  %tmp10618 = getelementptr inbounds float* %tmp10617, i64 1
-  %tmp10619 = getelementptr inbounds float* %tmp10618, i64 1
-  %tmp10620 = getelementptr inbounds float* %tmp10619, i64 1
-  %tmp10621 = getelementptr inbounds float* %tmp10620, i64 1
-  %tmp10622 = getelementptr inbounds float* %tmp10621, i64 1
-  %tmp10623 = getelementptr inbounds float* %tmp10622, i64 1
-  %tmp10624 = getelementptr inbounds float* %tmp10623, i64 1
-  %tmp10625 = getelementptr inbounds float* %tmp10624, i64 1
-  %tmp10626 = getelementptr inbounds float* %tmp10625, i64 1
-  %tmp10627 = getelementptr inbounds float* %tmp10626, i64 1
-  %tmp10628 = getelementptr inbounds float* %tmp10627, i64 1
-  %tmp10629 = getelementptr inbounds float* %tmp10628, i64 1
-  %tmp10630 = getelementptr inbounds float* %tmp10629, i64 1
-  %tmp10631 = getelementptr inbounds float* %tmp10630, i64 1
-  %tmp10632 = getelementptr inbounds float* %tmp10631, i64 1
-  %tmp10633 = getelementptr inbounds float* %tmp10632, i64 1
-  %tmp10634 = getelementptr inbounds float* %tmp10633, i64 1
-  %tmp10635 = getelementptr inbounds float* %tmp10634, i64 1
-  %tmp10636 = getelementptr inbounds float* %tmp10635, i64 1
-  %tmp10637 = getelementptr inbounds float* %tmp10636, i64 1
-  %tmp10638 = getelementptr inbounds float* %tmp10637, i64 1
-  %tmp10639 = getelementptr inbounds float* %tmp10638, i64 1
-  %tmp10640 = getelementptr inbounds float* %tmp10639, i64 1
-  %tmp10641 = getelementptr inbounds float* %tmp10640, i64 1
-  %tmp10642 = getelementptr inbounds float* %tmp10641, i64 1
-  %tmp10643 = getelementptr inbounds float* %tmp10642, i64 1
-  %tmp10644 = getelementptr inbounds float* %tmp10643, i64 1
-  %tmp10645 = getelementptr inbounds float* %tmp10644, i64 1
-  %tmp10646 = getelementptr inbounds float* %tmp10645, i64 1
-  %tmp10647 = getelementptr inbounds float* %tmp10646, i64 1
-  %tmp10648 = getelementptr inbounds float* %tmp10647, i64 1
-  %tmp10649 = getelementptr inbounds float* %tmp10648, i64 1
-  %tmp10650 = getelementptr inbounds float* %tmp10649, i64 1
-  %tmp10651 = getelementptr inbounds float* %tmp10650, i64 1
-  %tmp10652 = getelementptr inbounds float* %tmp10651, i64 1
-  %tmp10653 = getelementptr inbounds float* %tmp10652, i64 1
-  %tmp10654 = getelementptr inbounds float* %tmp10653, i64 1
-  %tmp10655 = getelementptr inbounds float* %tmp10654, i64 1
-  %tmp10656 = getelementptr inbounds float* %tmp10655, i64 1
-  %tmp10657 = getelementptr inbounds float* %tmp10656, i64 1
-  %tmp10658 = getelementptr inbounds float* %tmp10657, i64 1
-  %tmp10659 = getelementptr inbounds float* %tmp10658, i64 1
-  %tmp10660 = getelementptr inbounds float* %tmp10659, i64 1
-  %tmp10661 = getelementptr inbounds float* %tmp10660, i64 1
-  %tmp10662 = getelementptr inbounds float* %tmp10661, i64 1
-  %tmp10663 = getelementptr inbounds float* %tmp10662, i64 1
-  %tmp10664 = getelementptr inbounds float* %tmp10663, i64 1
-  %tmp10665 = getelementptr inbounds float* %tmp10664, i64 1
-  %tmp10666 = getelementptr inbounds float* %tmp10665, i64 1
-  %tmp10667 = getelementptr inbounds float* %tmp10666, i64 1
-  %tmp10668 = getelementptr inbounds float* %tmp10667, i64 1
-  %tmp10669 = getelementptr inbounds float* %tmp10668, i64 1
-  %tmp10670 = getelementptr inbounds float* %tmp10669, i64 1
-  %tmp10671 = getelementptr inbounds float* %tmp10670, i64 1
-  %tmp10672 = getelementptr inbounds float* %tmp10671, i64 1
-  %tmp10673 = getelementptr inbounds float* %tmp10672, i64 1
-  %tmp10674 = getelementptr inbounds float* %tmp10673, i64 1
-  %tmp10675 = getelementptr inbounds float* %tmp10674, i64 1
-  %tmp10676 = getelementptr inbounds float* %tmp10675, i64 1
-  %tmp10677 = getelementptr inbounds float* %tmp10676, i64 1
-  %tmp10678 = getelementptr inbounds float* %tmp10677, i64 1
-  %tmp10679 = getelementptr inbounds float* %tmp10678, i64 1
-  %tmp10680 = getelementptr inbounds float* %tmp10679, i64 1
-  %tmp10681 = getelementptr inbounds float* %tmp10680, i64 1
-  %tmp10682 = getelementptr inbounds float* %tmp10681, i64 1
-  %tmp10683 = getelementptr inbounds float* %tmp10682, i64 1
-  %tmp10684 = getelementptr inbounds float* %tmp10683, i64 1
-  %tmp10685 = getelementptr inbounds float* %tmp10684, i64 1
-  %tmp10686 = getelementptr inbounds float* %tmp10685, i64 1
-  %tmp10687 = getelementptr inbounds float* %tmp10686, i64 1
-  %tmp10688 = getelementptr inbounds float* %tmp10687, i64 1
-  %tmp10689 = getelementptr inbounds float* %tmp10688, i64 1
-  %tmp10690 = getelementptr inbounds float* %tmp10689, i64 1
-  %tmp10691 = getelementptr inbounds float* %tmp10690, i64 1
-  %tmp10692 = getelementptr inbounds float* %tmp10691, i64 1
-  %tmp10693 = getelementptr inbounds float* %tmp10692, i64 1
-  %tmp10694 = getelementptr inbounds float* %tmp10693, i64 1
-  %tmp10695 = getelementptr inbounds float* %tmp10694, i64 1
-  %tmp10696 = getelementptr inbounds float* %tmp10695, i64 1
-  %tmp10697 = getelementptr inbounds float* %tmp10696, i64 1
-  %tmp10698 = getelementptr inbounds float* %tmp10697, i64 1
-  %tmp10699 = getelementptr inbounds float* %tmp10698, i64 1
-  %tmp10700 = getelementptr inbounds float* %tmp10699, i64 1
-  %tmp10701 = getelementptr inbounds float* %tmp10700, i64 1
-  %tmp10702 = getelementptr inbounds float* %tmp10701, i64 1
-  %tmp10703 = getelementptr inbounds float* %tmp10702, i64 1
-  %tmp10704 = getelementptr inbounds float* %tmp10703, i64 1
-  %tmp10705 = getelementptr inbounds float* %tmp10704, i64 1
-  %tmp10706 = getelementptr inbounds float* %tmp10705, i64 1
-  %tmp10707 = getelementptr inbounds float* %tmp10706, i64 1
-  %tmp10708 = getelementptr inbounds float* %tmp10707, i64 1
-  %tmp10709 = getelementptr inbounds float* %tmp10708, i64 1
-  %tmp10710 = getelementptr inbounds float* %tmp10709, i64 1
-  %tmp10711 = getelementptr inbounds float* %tmp10710, i64 1
-  %tmp10712 = getelementptr inbounds float* %tmp10711, i64 1
-  %tmp10713 = getelementptr inbounds float* %tmp10712, i64 1
-  %tmp10714 = getelementptr inbounds float* %tmp10713, i64 1
-  %tmp10715 = getelementptr inbounds float* %tmp10714, i64 1
-  %tmp10716 = getelementptr inbounds float* %tmp10715, i64 1
-  %tmp10717 = getelementptr inbounds float* %tmp10716, i64 1
-  %tmp10718 = getelementptr inbounds float* %tmp10717, i64 1
-  %tmp10719 = getelementptr inbounds float* %tmp10718, i64 1
-  %tmp10720 = getelementptr inbounds float* %tmp10719, i64 1
-  %tmp10721 = getelementptr inbounds float* %tmp10720, i64 1
-  %tmp10722 = getelementptr inbounds float* %tmp10721, i64 1
-  %tmp10723 = getelementptr inbounds float* %tmp10722, i64 1
-  %tmp10724 = getelementptr inbounds float* %tmp10723, i64 1
-  %tmp10725 = getelementptr inbounds float* %tmp10724, i64 1
-  %tmp10726 = getelementptr inbounds float* %tmp10725, i64 1
-  %tmp10727 = getelementptr inbounds float* %tmp10726, i64 1
-  %tmp10728 = getelementptr inbounds float* %tmp10727, i64 1
-  %tmp10729 = getelementptr inbounds float* %tmp10728, i64 1
-  %tmp10730 = getelementptr inbounds float* %tmp10729, i64 1
-  %tmp10731 = getelementptr inbounds float* %tmp10730, i64 1
-  %tmp10732 = getelementptr inbounds float* %tmp10731, i64 1
-  %tmp10733 = getelementptr inbounds float* %tmp10732, i64 1
-  %tmp10734 = getelementptr inbounds float* %tmp10733, i64 1
-  %tmp10735 = getelementptr inbounds float* %tmp10734, i64 1
-  %tmp10736 = getelementptr inbounds float* %tmp10735, i64 1
-  %tmp10737 = getelementptr inbounds float* %tmp10736, i64 1
-  %tmp10738 = getelementptr inbounds float* %tmp10737, i64 1
-  %tmp10739 = getelementptr inbounds float* %tmp10738, i64 1
-  %tmp10740 = getelementptr inbounds float* %tmp10739, i64 1
-  %tmp10741 = getelementptr inbounds float* %tmp10740, i64 1
-  %tmp10742 = getelementptr inbounds float* %tmp10741, i64 1
-  %tmp10743 = getelementptr inbounds float* %tmp10742, i64 1
-  %tmp10744 = getelementptr inbounds float* %tmp10743, i64 1
-  %tmp10745 = getelementptr inbounds float* %tmp10744, i64 1
-  %tmp10746 = getelementptr inbounds float* %tmp10745, i64 1
-  %tmp10747 = getelementptr inbounds float* %tmp10746, i64 1
-  %tmp10748 = getelementptr inbounds float* %tmp10747, i64 1
-  %tmp10749 = getelementptr inbounds float* %tmp10748, i64 1
-  %tmp10750 = getelementptr inbounds float* %tmp10749, i64 1
-  %tmp10751 = getelementptr inbounds float* %tmp10750, i64 1
-  %tmp10752 = getelementptr inbounds float* %tmp10751, i64 1
-  %tmp10753 = getelementptr inbounds float* %tmp10752, i64 1
-  %tmp10754 = getelementptr inbounds float* %tmp10753, i64 1
-  %tmp10755 = getelementptr inbounds float* %tmp10754, i64 1
-  %tmp10756 = getelementptr inbounds float* %tmp10755, i64 1
-  %tmp10757 = getelementptr inbounds float* %tmp10756, i64 1
-  %tmp10758 = getelementptr inbounds float* %tmp10757, i64 1
-  %tmp10759 = getelementptr inbounds float* %tmp10758, i64 1
-  %tmp10760 = getelementptr inbounds float* %tmp10759, i64 1
-  %tmp10761 = getelementptr inbounds float* %tmp10760, i64 1
-  %tmp10762 = getelementptr inbounds float* %tmp10761, i64 1
-  %tmp10763 = getelementptr inbounds float* %tmp10762, i64 1
-  %tmp10764 = getelementptr inbounds float* %tmp10763, i64 1
-  %tmp10765 = getelementptr inbounds float* %tmp10764, i64 1
-  %tmp10766 = getelementptr inbounds float* %tmp10765, i64 1
-  %tmp10767 = getelementptr inbounds float* %tmp10766, i64 1
-  %tmp10768 = getelementptr inbounds float* %tmp10767, i64 1
-  %tmp10769 = getelementptr inbounds float* %tmp10768, i64 1
-  %tmp10770 = getelementptr inbounds float* %tmp10769, i64 1
-  %tmp10771 = getelementptr inbounds float* %tmp10770, i64 1
-  %tmp10772 = getelementptr inbounds float* %tmp10771, i64 1
-  %tmp10773 = getelementptr inbounds float* %tmp10772, i64 1
-  %tmp10774 = getelementptr inbounds float* %tmp10773, i64 1
-  %tmp10775 = getelementptr inbounds float* %tmp10774, i64 1
-  %tmp10776 = getelementptr inbounds float* %tmp10775, i64 1
-  %tmp10777 = getelementptr inbounds float* %tmp10776, i64 1
-  %tmp10778 = getelementptr inbounds float* %tmp10777, i64 1
-  %tmp10779 = getelementptr inbounds float* %tmp10778, i64 1
-  %tmp10780 = getelementptr inbounds float* %tmp10779, i64 1
-  %tmp10781 = getelementptr inbounds float* %tmp10780, i64 1
-  %tmp10782 = getelementptr inbounds float* %tmp10781, i64 1
-  %tmp10783 = getelementptr inbounds float* %tmp10782, i64 1
-  %tmp10784 = getelementptr inbounds float* %tmp10783, i64 1
-  %tmp10785 = getelementptr inbounds float* %tmp10784, i64 1
-  %tmp10786 = getelementptr inbounds float* %tmp10785, i64 1
-  %tmp10787 = getelementptr inbounds float* %tmp10786, i64 1
-  %tmp10788 = getelementptr inbounds float* %tmp10787, i64 1
-  %tmp10789 = getelementptr inbounds float* %tmp10788, i64 1
-  %tmp10790 = getelementptr inbounds float* %tmp10789, i64 1
-  %tmp10791 = getelementptr inbounds float* %tmp10790, i64 1
-  %tmp10792 = getelementptr inbounds float* %tmp10791, i64 1
-  %tmp10793 = getelementptr inbounds float* %tmp10792, i64 1
-  %tmp10794 = getelementptr inbounds float* %tmp10793, i64 1
-  %tmp10795 = getelementptr inbounds float* %tmp10794, i64 1
-  %tmp10796 = getelementptr inbounds float* %tmp10795, i64 1
-  %tmp10797 = getelementptr inbounds float* %tmp10796, i64 1
-  %tmp10798 = getelementptr inbounds float* %tmp10797, i64 1
-  %tmp10799 = getelementptr inbounds float* %tmp10798, i64 1
-  %tmp10800 = getelementptr inbounds float* %tmp10799, i64 1
-  %tmp10801 = getelementptr inbounds float* %tmp10800, i64 1
-  %tmp10802 = getelementptr inbounds float* %tmp10801, i64 1
-  %tmp10803 = getelementptr inbounds float* %tmp10802, i64 1
-  %tmp10804 = getelementptr inbounds float* %tmp10803, i64 1
-  %tmp10805 = getelementptr inbounds float* %tmp10804, i64 1
-  %tmp10806 = getelementptr inbounds float* %tmp10805, i64 1
-  %tmp10807 = getelementptr inbounds float* %tmp10806, i64 1
-  %tmp10808 = getelementptr inbounds float* %tmp10807, i64 1
-  %tmp10809 = getelementptr inbounds float* %tmp10808, i64 1
-  %tmp10810 = getelementptr inbounds float* %tmp10809, i64 1
-  %tmp10811 = getelementptr inbounds float* %tmp10810, i64 1
-  %tmp10812 = getelementptr inbounds float* %tmp10811, i64 1
-  %tmp10813 = getelementptr inbounds float* %tmp10812, i64 1
-  %tmp10814 = getelementptr inbounds float* %tmp10813, i64 1
-  %tmp10815 = getelementptr inbounds float* %tmp10814, i64 1
-  %tmp10816 = getelementptr inbounds float* %tmp10815, i64 1
-  %tmp10817 = getelementptr inbounds float* %tmp10816, i64 1
-  %tmp10818 = getelementptr inbounds float* %tmp10817, i64 1
-  %tmp10819 = getelementptr inbounds float* %tmp10818, i64 1
-  %tmp10820 = getelementptr inbounds float* %tmp10819, i64 1
-  %tmp10821 = getelementptr inbounds float* %tmp10820, i64 1
-  %tmp10822 = getelementptr inbounds float* %tmp10821, i64 1
-  %tmp10823 = getelementptr inbounds float* %tmp10822, i64 1
-  %tmp10824 = getelementptr inbounds float* %tmp10823, i64 1
-  %tmp10825 = getelementptr inbounds float* %tmp10824, i64 1
-  %tmp10826 = getelementptr inbounds float* %tmp10825, i64 1
-  %tmp10827 = getelementptr inbounds float* %tmp10826, i64 1
-  %tmp10828 = getelementptr inbounds float* %tmp10827, i64 1
-  %tmp10829 = getelementptr inbounds float* %tmp10828, i64 1
-  %tmp10830 = getelementptr inbounds float* %tmp10829, i64 1
-  %tmp10831 = getelementptr inbounds float* %tmp10830, i64 1
-  %tmp10832 = getelementptr inbounds float* %tmp10831, i64 1
-  %tmp10833 = getelementptr inbounds float* %tmp10832, i64 1
-  %tmp10834 = getelementptr inbounds float* %tmp10833, i64 1
-  %tmp10835 = getelementptr inbounds float* %tmp10834, i64 1
-  %tmp10836 = getelementptr inbounds float* %tmp10835, i64 1
-  %tmp10837 = getelementptr inbounds float* %tmp10836, i64 1
-  %tmp10838 = getelementptr inbounds float* %tmp10837, i64 1
-  %tmp10839 = getelementptr inbounds float* %tmp10838, i64 1
-  %tmp10840 = getelementptr inbounds float* %tmp10839, i64 1
-  %tmp10841 = getelementptr inbounds float* %tmp10840, i64 1
-  %tmp10842 = getelementptr inbounds float* %tmp10841, i64 1
-  %tmp10843 = getelementptr inbounds float* %tmp10842, i64 1
-  %tmp10844 = getelementptr inbounds float* %tmp10843, i64 1
-  %tmp10845 = getelementptr inbounds float* %tmp10844, i64 1
-  %tmp10846 = getelementptr inbounds float* %tmp10845, i64 1
-  %tmp10847 = getelementptr inbounds float* %tmp10846, i64 1
-  %tmp10848 = getelementptr inbounds float* %tmp10847, i64 1
-  %tmp10849 = getelementptr inbounds float* %tmp10848, i64 1
-  %tmp10850 = getelementptr inbounds float* %tmp10849, i64 1
-  %tmp10851 = getelementptr inbounds float* %tmp10850, i64 1
-  %tmp10852 = getelementptr inbounds float* %tmp10851, i64 1
-  %tmp10853 = getelementptr inbounds float* %tmp10852, i64 1
-  %tmp10854 = getelementptr inbounds float* %tmp10853, i64 1
-  %tmp10855 = getelementptr inbounds float* %tmp10854, i64 1
-  %tmp10856 = getelementptr inbounds float* %tmp10855, i64 1
-  %tmp10857 = getelementptr inbounds float* %tmp10856, i64 1
-  %tmp10858 = getelementptr inbounds float* %tmp10857, i64 1
-  %tmp10859 = getelementptr inbounds float* %tmp10858, i64 1
-  %tmp10860 = getelementptr inbounds float* %tmp10859, i64 1
-  %tmp10861 = getelementptr inbounds float* %tmp10860, i64 1
-  %tmp10862 = getelementptr inbounds float* %tmp10861, i64 1
-  %tmp10863 = getelementptr inbounds float* %tmp10862, i64 1
-  %tmp10864 = getelementptr inbounds float* %tmp10863, i64 1
-  %tmp10865 = getelementptr inbounds float* %tmp10864, i64 1
-  %tmp10866 = getelementptr inbounds float* %tmp10865, i64 1
-  %tmp10867 = getelementptr inbounds float* %tmp10866, i64 1
-  %tmp10868 = getelementptr inbounds float* %tmp10867, i64 1
-  %tmp10869 = getelementptr inbounds float* %tmp10868, i64 1
-  %tmp10870 = getelementptr inbounds float* %tmp10869, i64 1
-  %tmp10871 = getelementptr inbounds float* %tmp10870, i64 1
-  %tmp10872 = getelementptr inbounds float* %tmp10871, i64 1
-  %tmp10873 = getelementptr inbounds float* %tmp10872, i64 1
-  %tmp10874 = getelementptr inbounds float* %tmp10873, i64 1
-  %tmp10875 = getelementptr inbounds float* %tmp10874, i64 1
-  %tmp10876 = getelementptr inbounds float* %tmp10875, i64 1
-  %tmp10877 = getelementptr inbounds float* %tmp10876, i64 1
-  %tmp10878 = getelementptr inbounds float* %tmp10877, i64 1
-  %tmp10879 = getelementptr inbounds float* %tmp10878, i64 1
-  %tmp10880 = getelementptr inbounds float* %tmp10879, i64 1
-  %tmp10881 = getelementptr inbounds float* %tmp10880, i64 1
-  %tmp10882 = getelementptr inbounds float* %tmp10881, i64 1
-  %tmp10883 = getelementptr inbounds float* %tmp10882, i64 1
-  %tmp10884 = getelementptr inbounds float* %tmp10883, i64 1
-  %tmp10885 = getelementptr inbounds float* %tmp10884, i64 1
-  %tmp10886 = getelementptr inbounds float* %tmp10885, i64 1
-  %tmp10887 = getelementptr inbounds float* %tmp10886, i64 1
-  %tmp10888 = getelementptr inbounds float* %tmp10887, i64 1
-  %tmp10889 = getelementptr inbounds float* %tmp10888, i64 1
-  %tmp10890 = getelementptr inbounds float* %tmp10889, i64 1
-  %tmp10891 = getelementptr inbounds float* %tmp10890, i64 1
-  %tmp10892 = getelementptr inbounds float* %tmp10891, i64 1
-  %tmp10893 = getelementptr inbounds float* %tmp10892, i64 1
-  %tmp10894 = getelementptr inbounds float* %tmp10893, i64 1
-  %tmp10895 = getelementptr inbounds float* %tmp10894, i64 1
-  %tmp10896 = getelementptr inbounds float* %tmp10895, i64 1
-  %tmp10897 = getelementptr inbounds float* %tmp10896, i64 1
-  %tmp10898 = getelementptr inbounds float* %tmp10897, i64 1
-  %tmp10899 = getelementptr inbounds float* %tmp10898, i64 1
-  %tmp10900 = getelementptr inbounds float* %tmp10899, i64 1
-  %tmp10901 = getelementptr inbounds float* %tmp10900, i64 1
-  %tmp10902 = getelementptr inbounds float* %tmp10901, i64 1
-  %tmp10903 = getelementptr inbounds float* %tmp10902, i64 1
-  %tmp10904 = getelementptr inbounds float* %tmp10903, i64 1
-  %tmp10905 = getelementptr inbounds float* %tmp10904, i64 1
-  %tmp10906 = getelementptr inbounds float* %tmp10905, i64 1
-  %tmp10907 = getelementptr inbounds float* %tmp10906, i64 1
-  %tmp10908 = getelementptr inbounds float* %tmp10907, i64 1
-  %tmp10909 = getelementptr inbounds float* %tmp10908, i64 1
-  %tmp10910 = getelementptr inbounds float* %tmp10909, i64 1
-  %tmp10911 = getelementptr inbounds float* %tmp10910, i64 1
-  %tmp10912 = getelementptr inbounds float* %tmp10911, i64 1
-  %tmp10913 = getelementptr inbounds float* %tmp10912, i64 1
-  %tmp10914 = getelementptr inbounds float* %tmp10913, i64 1
-  %tmp10915 = getelementptr inbounds float* %tmp10914, i64 1
-  %tmp10916 = getelementptr inbounds float* %tmp10915, i64 1
-  %tmp10917 = getelementptr inbounds float* %tmp10916, i64 1
-  %tmp10918 = getelementptr inbounds float* %tmp10917, i64 1
-  %tmp10919 = getelementptr inbounds float* %tmp10918, i64 1
-  %tmp10920 = getelementptr inbounds float* %tmp10919, i64 1
-  %tmp10921 = getelementptr inbounds float* %tmp10920, i64 1
-  %tmp10922 = getelementptr inbounds float* %tmp10921, i64 1
-  %tmp10923 = getelementptr inbounds float* %tmp10922, i64 1
-  %tmp10924 = getelementptr inbounds float* %tmp10923, i64 1
-  %tmp10925 = getelementptr inbounds float* %tmp10924, i64 1
-  %tmp10926 = getelementptr inbounds float* %tmp10925, i64 1
-  %tmp10927 = getelementptr inbounds float* %tmp10926, i64 1
-  %tmp10928 = getelementptr inbounds float* %tmp10927, i64 1
-  %tmp10929 = getelementptr inbounds float* %tmp10928, i64 1
-  %tmp10930 = getelementptr inbounds float* %tmp10929, i64 1
-  %tmp10931 = getelementptr inbounds float* %tmp10930, i64 1
-  %tmp10932 = getelementptr inbounds float* %tmp10931, i64 1
-  %tmp10933 = getelementptr inbounds float* %tmp10932, i64 1
-  %tmp10934 = getelementptr inbounds float* %tmp10933, i64 1
-  %tmp10935 = getelementptr inbounds float* %tmp10934, i64 1
-  %tmp10936 = getelementptr inbounds float* %tmp10935, i64 1
-  %tmp10937 = getelementptr inbounds float* %tmp10936, i64 1
-  %tmp10938 = getelementptr inbounds float* %tmp10937, i64 1
-  %tmp10939 = getelementptr inbounds float* %tmp10938, i64 1
-  %tmp10940 = getelementptr inbounds float* %tmp10939, i64 1
-  %tmp10941 = getelementptr inbounds float* %tmp10940, i64 1
-  %tmp10942 = getelementptr inbounds float* %tmp10941, i64 1
-  %tmp10943 = getelementptr inbounds float* %tmp10942, i64 1
-  %tmp10944 = getelementptr inbounds float* %tmp10943, i64 1
-  %tmp10945 = getelementptr inbounds float* %tmp10944, i64 1
-  %tmp10946 = getelementptr inbounds float* %tmp10945, i64 1
-  %tmp10947 = getelementptr inbounds float* %tmp10946, i64 1
-  %tmp10948 = getelementptr inbounds float* %tmp10947, i64 1
-  %tmp10949 = getelementptr inbounds float* %tmp10948, i64 1
-  %tmp10950 = getelementptr inbounds float* %tmp10949, i64 1
-  %tmp10951 = getelementptr inbounds float* %tmp10950, i64 1
-  %tmp10952 = getelementptr inbounds float* %tmp10951, i64 1
-  %tmp10953 = getelementptr inbounds float* %tmp10952, i64 1
-  %tmp10954 = getelementptr inbounds float* %tmp10953, i64 1
-  %tmp10955 = getelementptr inbounds float* %tmp10954, i64 1
-  %tmp10956 = getelementptr inbounds float* %tmp10955, i64 1
-  %tmp10957 = getelementptr inbounds float* %tmp10956, i64 1
-  %tmp10958 = getelementptr inbounds float* %tmp10957, i64 1
-  %tmp10959 = getelementptr inbounds float* %tmp10958, i64 1
-  %tmp10960 = getelementptr inbounds float* %tmp10959, i64 1
-  %tmp10961 = getelementptr inbounds float* %tmp10960, i64 1
-  %tmp10962 = getelementptr inbounds float* %tmp10961, i64 1
-  %tmp10963 = getelementptr inbounds float* %tmp10962, i64 1
-  %tmp10964 = getelementptr inbounds float* %tmp10963, i64 1
-  %tmp10965 = getelementptr inbounds float* %tmp10964, i64 1
-  %tmp10966 = getelementptr inbounds float* %tmp10965, i64 1
-  %tmp10967 = getelementptr inbounds float* %tmp10966, i64 1
-  %tmp10968 = getelementptr inbounds float* %tmp10967, i64 1
-  %tmp10969 = getelementptr inbounds float* %tmp10968, i64 1
-  %tmp10970 = getelementptr inbounds float* %tmp10969, i64 1
-  %tmp10971 = getelementptr inbounds float* %tmp10970, i64 1
-  %tmp10972 = getelementptr inbounds float* %tmp10971, i64 1
-  %tmp10973 = getelementptr inbounds float* %tmp10972, i64 1
-  %tmp10974 = getelementptr inbounds float* %tmp10973, i64 1
-  %tmp10975 = getelementptr inbounds float* %tmp10974, i64 1
-  %tmp10976 = getelementptr inbounds float* %tmp10975, i64 1
-  %tmp10977 = getelementptr inbounds float* %tmp10976, i64 1
-  %tmp10978 = getelementptr inbounds float* %tmp10977, i64 1
-  %tmp10979 = getelementptr inbounds float* %tmp10978, i64 1
-  %tmp10980 = getelementptr inbounds float* %tmp10979, i64 1
-  %tmp10981 = getelementptr inbounds float* %tmp10980, i64 1
-  %tmp10982 = getelementptr inbounds float* %tmp10981, i64 1
-  %tmp10983 = getelementptr inbounds float* %tmp10982, i64 1
-  %tmp10984 = getelementptr inbounds float* %tmp10983, i64 1
-  %tmp10985 = getelementptr inbounds float* %tmp10984, i64 1
-  %tmp10986 = getelementptr inbounds float* %tmp10985, i64 1
-  %tmp10987 = getelementptr inbounds float* %tmp10986, i64 1
-  %tmp10988 = getelementptr inbounds float* %tmp10987, i64 1
-  %tmp10989 = getelementptr inbounds float* %tmp10988, i64 1
-  %tmp10990 = getelementptr inbounds float* %tmp10989, i64 1
-  %tmp10991 = getelementptr inbounds float* %tmp10990, i64 1
-  %tmp10992 = getelementptr inbounds float* %tmp10991, i64 1
-  %tmp10993 = getelementptr inbounds float* %tmp10992, i64 1
-  %tmp10994 = getelementptr inbounds float* %tmp10993, i64 1
-  %tmp10995 = getelementptr inbounds float* %tmp10994, i64 1
-  %tmp10996 = getelementptr inbounds float* %tmp10995, i64 1
-  %tmp10997 = getelementptr inbounds float* %tmp10996, i64 1
-  %tmp10998 = getelementptr inbounds float* %tmp10997, i64 1
-  %tmp10999 = getelementptr inbounds float* %tmp10998, i64 1
-  %tmp11000 = getelementptr inbounds float* %tmp10999, i64 1
-  %tmp11001 = getelementptr inbounds float* %tmp11000, i64 1
-  %tmp11002 = getelementptr inbounds float* %tmp11001, i64 1
-  %tmp11003 = getelementptr inbounds float* %tmp11002, i64 1
-  %tmp11004 = getelementptr inbounds float* %tmp11003, i64 1
-  %tmp11005 = getelementptr inbounds float* %tmp11004, i64 1
-  %tmp11006 = getelementptr inbounds float* %tmp11005, i64 1
-  %tmp11007 = getelementptr inbounds float* %tmp11006, i64 1
-  %tmp11008 = getelementptr inbounds float* %tmp11007, i64 1
-  %tmp11009 = getelementptr inbounds float* %tmp11008, i64 1
-  %tmp11010 = getelementptr inbounds float* %tmp11009, i64 1
-  %tmp11011 = getelementptr inbounds float* %tmp11010, i64 1
-  %tmp11012 = getelementptr inbounds float* %tmp11011, i64 1
-  %tmp11013 = getelementptr inbounds float* %tmp11012, i64 1
-  %tmp11014 = getelementptr inbounds float* %tmp11013, i64 1
-  %tmp11015 = getelementptr inbounds float* %tmp11014, i64 1
-  %tmp11016 = getelementptr inbounds float* %tmp11015, i64 1
-  %tmp11017 = getelementptr inbounds float* %tmp11016, i64 1
-  %tmp11018 = getelementptr inbounds float* %tmp11017, i64 1
-  %tmp11019 = getelementptr inbounds float* %tmp11018, i64 1
-  %tmp11020 = getelementptr inbounds float* %tmp11019, i64 1
-  %tmp11021 = getelementptr inbounds float* %tmp11020, i64 1
-  %tmp11022 = getelementptr inbounds float* %tmp11021, i64 1
-  %tmp11023 = getelementptr inbounds float* %tmp11022, i64 1
-  %tmp11024 = getelementptr inbounds float* %tmp11023, i64 1
-  %tmp11025 = getelementptr inbounds float* %tmp11024, i64 1
-  %tmp11026 = getelementptr inbounds float* %tmp11025, i64 1
-  %tmp11027 = getelementptr inbounds float* %tmp11026, i64 1
-  %tmp11028 = getelementptr inbounds float* %tmp11027, i64 1
-  %tmp11029 = getelementptr inbounds float* %tmp11028, i64 1
-  %tmp11030 = getelementptr inbounds float* %tmp11029, i64 1
-  %tmp11031 = getelementptr inbounds float* %tmp11030, i64 1
-  %tmp11032 = getelementptr inbounds float* %tmp11031, i64 1
-  %tmp11033 = getelementptr inbounds float* %tmp11032, i64 1
-  %tmp11034 = getelementptr inbounds float* %tmp11033, i64 1
-  %tmp11035 = getelementptr inbounds float* %tmp11034, i64 1
-  %tmp11036 = getelementptr inbounds float* %tmp11035, i64 1
-  %tmp11037 = getelementptr inbounds float* %tmp11036, i64 1
-  %tmp11038 = getelementptr inbounds float* %tmp11037, i64 1
-  %tmp11039 = getelementptr inbounds float* %tmp11038, i64 1
-  %tmp11040 = getelementptr inbounds float* %tmp11039, i64 1
-  %tmp11041 = getelementptr inbounds float* %tmp11040, i64 1
-  %tmp11042 = getelementptr inbounds float* %tmp11041, i64 1
-  %tmp11043 = getelementptr inbounds float* %tmp11042, i64 1
-  %tmp11044 = getelementptr inbounds float* %tmp11043, i64 1
-  %tmp11045 = getelementptr inbounds float* %tmp11044, i64 1
-  %tmp11046 = getelementptr inbounds float* %tmp11045, i64 1
-  %tmp11047 = getelementptr inbounds float* %tmp11046, i64 1
-  %tmp11048 = getelementptr inbounds float* %tmp11047, i64 1
-  %tmp11049 = getelementptr inbounds float* %tmp11048, i64 1
-  %tmp11050 = getelementptr inbounds float* %tmp11049, i64 1
-  %tmp11051 = getelementptr inbounds float* %tmp11050, i64 1
-  %tmp11052 = getelementptr inbounds float* %tmp11051, i64 1
-  %tmp11053 = getelementptr inbounds float* %tmp11052, i64 1
-  %tmp11054 = getelementptr inbounds float* %tmp11053, i64 1
-  %tmp11055 = getelementptr inbounds float* %tmp11054, i64 1
-  %tmp11056 = getelementptr inbounds float* %tmp11055, i64 1
-  %tmp11057 = getelementptr inbounds float* %tmp11056, i64 1
-  %tmp11058 = getelementptr inbounds float* %tmp11057, i64 1
-  %tmp11059 = getelementptr inbounds float* %tmp11058, i64 1
-  %tmp11060 = getelementptr inbounds float* %tmp11059, i64 1
-  %tmp11061 = getelementptr inbounds float* %tmp11060, i64 1
-  %tmp11062 = getelementptr inbounds float* %tmp11061, i64 1
-  %tmp11063 = getelementptr inbounds float* %tmp11062, i64 1
-  %tmp11064 = getelementptr inbounds float* %tmp11063, i64 1
-  %tmp11065 = getelementptr inbounds float* %tmp11064, i64 1
-  %tmp11066 = getelementptr inbounds float* %tmp11065, i64 1
-  %tmp11067 = getelementptr inbounds float* %tmp11066, i64 1
-  %tmp11068 = getelementptr inbounds float* %tmp11067, i64 1
-  %tmp11069 = getelementptr inbounds float* %tmp11068, i64 1
-  %tmp11070 = getelementptr inbounds float* %tmp11069, i64 1
-  %tmp11071 = getelementptr inbounds float* %tmp11070, i64 1
-  %tmp11072 = getelementptr inbounds float* %tmp11071, i64 1
-  %tmp11073 = getelementptr inbounds float* %tmp11072, i64 1
-  %tmp11074 = getelementptr inbounds float* %tmp11073, i64 1
-  %tmp11075 = getelementptr inbounds float* %tmp11074, i64 1
-  %tmp11076 = getelementptr inbounds float* %tmp11075, i64 1
-  %tmp11077 = getelementptr inbounds float* %tmp11076, i64 1
-  %tmp11078 = getelementptr inbounds float* %tmp11077, i64 1
-  %tmp11079 = getelementptr inbounds float* %tmp11078, i64 1
-  %tmp11080 = getelementptr inbounds float* %tmp11079, i64 1
-  %tmp11081 = getelementptr inbounds float* %tmp11080, i64 1
-  %tmp11082 = getelementptr inbounds float* %tmp11081, i64 1
-  %tmp11083 = getelementptr inbounds float* %tmp11082, i64 1
-  %tmp11084 = getelementptr inbounds float* %tmp11083, i64 1
-  %tmp11085 = getelementptr inbounds float* %tmp11084, i64 1
-  %tmp11086 = getelementptr inbounds float* %tmp11085, i64 1
-  %tmp11087 = getelementptr inbounds float* %tmp11086, i64 1
-  %tmp11088 = getelementptr inbounds float* %tmp11087, i64 1
-  %tmp11089 = getelementptr inbounds float* %tmp11088, i64 1
-  %tmp11090 = getelementptr inbounds float* %tmp11089, i64 1
-  %tmp11091 = getelementptr inbounds float* %tmp11090, i64 1
-  %tmp11092 = getelementptr inbounds float* %tmp11091, i64 1
-  %tmp11093 = getelementptr inbounds float* %tmp11092, i64 1
-  %tmp11094 = getelementptr inbounds float* %tmp11093, i64 1
-  %tmp11095 = getelementptr inbounds float* %tmp11094, i64 1
-  %tmp11096 = getelementptr inbounds float* %tmp11095, i64 1
-  %tmp11097 = getelementptr inbounds float* %tmp11096, i64 1
-  %tmp11098 = getelementptr inbounds float* %tmp11097, i64 1
-  %tmp11099 = getelementptr inbounds float* %tmp11098, i64 1
-  %tmp11100 = getelementptr inbounds float* %tmp11099, i64 1
-  %tmp11101 = getelementptr inbounds float* %tmp11100, i64 1
-  %tmp11102 = getelementptr inbounds float* %tmp11101, i64 1
-  %tmp11103 = getelementptr inbounds float* %tmp11102, i64 1
-  %tmp11104 = getelementptr inbounds float* %tmp11103, i64 1
-  %tmp11105 = getelementptr inbounds float* %tmp11104, i64 1
-  %tmp11106 = getelementptr inbounds float* %tmp11105, i64 1
-  %tmp11107 = getelementptr inbounds float* %tmp11106, i64 1
-  %tmp11108 = getelementptr inbounds float* %tmp11107, i64 1
-  %tmp11109 = getelementptr inbounds float* %tmp11108, i64 1
-  %tmp11110 = getelementptr inbounds float* %tmp11109, i64 1
-  %tmp11111 = getelementptr inbounds float* %tmp11110, i64 1
-  %tmp11112 = getelementptr inbounds float* %tmp11111, i64 1
-  %tmp11113 = getelementptr inbounds float* %tmp11112, i64 1
-  %tmp11114 = getelementptr inbounds float* %tmp11113, i64 1
-  %tmp11115 = getelementptr inbounds float* %tmp11114, i64 1
-  %tmp11116 = getelementptr inbounds float* %tmp11115, i64 1
-  %tmp11117 = getelementptr inbounds float* %tmp11116, i64 1
-  %tmp11118 = getelementptr inbounds float* %tmp11117, i64 1
-  %tmp11119 = getelementptr inbounds float* %tmp11118, i64 1
-  %tmp11120 = getelementptr inbounds float* %tmp11119, i64 1
-  %tmp11121 = getelementptr inbounds float* %tmp11120, i64 1
-  %tmp11122 = getelementptr inbounds float* %tmp11121, i64 1
-  %tmp11123 = getelementptr inbounds float* %tmp11122, i64 1
-  %tmp11124 = getelementptr inbounds float* %tmp11123, i64 1
-  %tmp11125 = getelementptr inbounds float* %tmp11124, i64 1
-  %tmp11126 = getelementptr inbounds float* %tmp11125, i64 1
-  %tmp11127 = getelementptr inbounds float* %tmp11126, i64 1
-  %tmp11128 = getelementptr inbounds float* %tmp11127, i64 1
-  %tmp11129 = getelementptr inbounds float* %tmp11128, i64 1
-  %tmp11130 = getelementptr inbounds float* %tmp11129, i64 1
-  %tmp11131 = getelementptr inbounds float* %tmp11130, i64 1
-  %tmp11132 = getelementptr inbounds float* %tmp11131, i64 1
-  %tmp11133 = getelementptr inbounds float* %tmp11132, i64 1
-  %tmp11134 = getelementptr inbounds float* %tmp11133, i64 1
-  %tmp11135 = getelementptr inbounds float* %tmp11134, i64 1
-  %tmp11136 = getelementptr inbounds float* %tmp11135, i64 1
-  %tmp11137 = getelementptr inbounds float* %tmp11136, i64 1
-  %tmp11138 = getelementptr inbounds float* %tmp11137, i64 1
-  %tmp11139 = getelementptr inbounds float* %tmp11138, i64 1
-  %tmp11140 = getelementptr inbounds float* %tmp11139, i64 1
-  %tmp11141 = getelementptr inbounds float* %tmp11140, i64 1
-  %tmp11142 = getelementptr inbounds float* %tmp11141, i64 1
-  %tmp11143 = getelementptr inbounds float* %tmp11142, i64 1
-  %tmp11144 = getelementptr inbounds float* %tmp11143, i64 1
-  %tmp11145 = getelementptr inbounds float* %tmp11144, i64 1
-  %tmp11146 = getelementptr inbounds float* %tmp11145, i64 1
-  %tmp11147 = getelementptr inbounds float* %tmp11146, i64 1
-  %tmp11148 = getelementptr inbounds float* %tmp11147, i64 1
-  %tmp11149 = getelementptr inbounds float* %tmp11148, i64 1
-  %tmp11150 = getelementptr inbounds float* %tmp11149, i64 1
-  %tmp11151 = getelementptr inbounds float* %tmp11150, i64 1
-  %tmp11152 = getelementptr inbounds float* %tmp11151, i64 1
-  %tmp11153 = getelementptr inbounds float* %tmp11152, i64 1
-  %tmp11154 = getelementptr inbounds float* %tmp11153, i64 1
-  %tmp11155 = getelementptr inbounds float* %tmp11154, i64 1
-  %tmp11156 = getelementptr inbounds float* %tmp11155, i64 1
-  %tmp11157 = getelementptr inbounds float* %tmp11156, i64 1
-  %tmp11158 = getelementptr inbounds float* %tmp11157, i64 1
-  %tmp11159 = getelementptr inbounds float* %tmp11158, i64 1
-  %tmp11160 = getelementptr inbounds float* %tmp11159, i64 1
-  %tmp11161 = getelementptr inbounds float* %tmp11160, i64 1
-  %tmp11162 = getelementptr inbounds float* %tmp11161, i64 1
-  %tmp11163 = getelementptr inbounds float* %tmp11162, i64 1
-  %tmp11164 = getelementptr inbounds float* %tmp11163, i64 1
-  %tmp11165 = getelementptr inbounds float* %tmp11164, i64 1
-  %tmp11166 = getelementptr inbounds float* %tmp11165, i64 1
-  %tmp11167 = getelementptr inbounds float* %tmp11166, i64 1
-  %tmp11168 = getelementptr inbounds float* %tmp11167, i64 1
-  %tmp11169 = getelementptr inbounds float* %tmp11168, i64 1
-  %tmp11170 = getelementptr inbounds float* %tmp11169, i64 1
-  %tmp11171 = getelementptr inbounds float* %tmp11170, i64 1
-  %tmp11172 = getelementptr inbounds float* %tmp11171, i64 1
-  %tmp11173 = getelementptr inbounds float* %tmp11172, i64 1
-  %tmp11174 = getelementptr inbounds float* %tmp11173, i64 1
-  %tmp11175 = getelementptr inbounds float* %tmp11174, i64 1
-  %tmp11176 = getelementptr inbounds float* %tmp11175, i64 1
-  %tmp11177 = getelementptr inbounds float* %tmp11176, i64 1
-  %tmp11178 = getelementptr inbounds float* %tmp11177, i64 1
-  %tmp11179 = getelementptr inbounds float* %tmp11178, i64 1
-  %tmp11180 = getelementptr inbounds float* %tmp11179, i64 1
-  %tmp11181 = getelementptr inbounds float* %tmp11180, i64 1
-  %tmp11182 = getelementptr inbounds float* %tmp11181, i64 1
-  %tmp11183 = getelementptr inbounds float* %tmp11182, i64 1
-  %tmp11184 = getelementptr inbounds float* %tmp11183, i64 1
-  %tmp11185 = getelementptr inbounds float* %tmp11184, i64 1
-  %tmp11186 = getelementptr inbounds float* %tmp11185, i64 1
-  %tmp11187 = getelementptr inbounds float* %tmp11186, i64 1
-  %tmp11188 = getelementptr inbounds float* %tmp11187, i64 1
-  %tmp11189 = getelementptr inbounds float* %tmp11188, i64 1
-  %tmp11190 = getelementptr inbounds float* %tmp11189, i64 1
-  %tmp11191 = getelementptr inbounds float* %tmp11190, i64 1
-  %tmp11192 = getelementptr inbounds float* %tmp11191, i64 1
-  %tmp11193 = getelementptr inbounds float* %tmp11192, i64 1
-  %tmp11194 = getelementptr inbounds float* %tmp11193, i64 1
-  %tmp11195 = getelementptr inbounds float* %tmp11194, i64 1
-  %tmp11196 = getelementptr inbounds float* %tmp11195, i64 1
-  %tmp11197 = getelementptr inbounds float* %tmp11196, i64 1
-  %tmp11198 = getelementptr inbounds float* %tmp11197, i64 1
-  %tmp11199 = getelementptr inbounds float* %tmp11198, i64 1
-  %tmp11200 = getelementptr inbounds float* %tmp11199, i64 1
-  %tmp11201 = getelementptr inbounds float* %tmp11200, i64 1
-  %tmp11202 = getelementptr inbounds float* %tmp11201, i64 1
-  %tmp11203 = getelementptr inbounds float* %tmp11202, i64 1
-  %tmp11204 = getelementptr inbounds float* %tmp11203, i64 1
-  %tmp11205 = getelementptr inbounds float* %tmp11204, i64 1
-  %tmp11206 = getelementptr inbounds float* %tmp11205, i64 1
-  %tmp11207 = getelementptr inbounds float* %tmp11206, i64 1
-  %tmp11208 = getelementptr inbounds float* %tmp11207, i64 1
-  %tmp11209 = getelementptr inbounds float* %tmp11208, i64 1
-  %tmp11210 = getelementptr inbounds float* %tmp11209, i64 1
-  %tmp11211 = getelementptr inbounds float* %tmp11210, i64 1
-  %tmp11212 = getelementptr inbounds float* %tmp11211, i64 1
-  %tmp11213 = getelementptr inbounds float* %tmp11212, i64 1
-  %tmp11214 = getelementptr inbounds float* %tmp11213, i64 1
-  %tmp11215 = getelementptr inbounds float* %tmp11214, i64 1
-  %tmp11216 = getelementptr inbounds float* %tmp11215, i64 1
-  %tmp11217 = getelementptr inbounds float* %tmp11216, i64 1
-  %tmp11218 = getelementptr inbounds float* %tmp11217, i64 1
-  %tmp11219 = getelementptr inbounds float* %tmp11218, i64 1
-  %tmp11220 = getelementptr inbounds float* %tmp11219, i64 1
-  %tmp11221 = getelementptr inbounds float* %tmp11220, i64 1
-  %tmp11222 = getelementptr inbounds float* %tmp11221, i64 1
-  %tmp11223 = getelementptr inbounds float* %tmp11222, i64 1
-  %tmp11224 = getelementptr inbounds float* %tmp11223, i64 1
-  %tmp11225 = getelementptr inbounds float* %tmp11224, i64 1
-  %tmp11226 = getelementptr inbounds float* %tmp11225, i64 1
-  %tmp11227 = getelementptr inbounds float* %tmp11226, i64 1
-  %tmp11228 = getelementptr inbounds float* %tmp11227, i64 1
-  %tmp11229 = getelementptr inbounds float* %tmp11228, i64 1
-  %tmp11230 = getelementptr inbounds float* %tmp11229, i64 1
-  %tmp11231 = getelementptr inbounds float* %tmp11230, i64 1
-  %tmp11232 = getelementptr inbounds float* %tmp11231, i64 1
-  %tmp11233 = getelementptr inbounds float* %tmp11232, i64 1
-  %tmp11234 = getelementptr inbounds float* %tmp11233, i64 1
-  %tmp11235 = getelementptr inbounds float* %tmp11234, i64 1
-  %tmp11236 = getelementptr inbounds float* %tmp11235, i64 1
-  %tmp11237 = getelementptr inbounds float* %tmp11236, i64 1
-  %tmp11238 = getelementptr inbounds float* %tmp11237, i64 1
-  %tmp11239 = getelementptr inbounds float* %tmp11238, i64 1
-  %tmp11240 = getelementptr inbounds float* %tmp11239, i64 1
-  %tmp11241 = getelementptr inbounds float* %tmp11240, i64 1
-  %tmp11242 = getelementptr inbounds float* %tmp11241, i64 1
-  %tmp11243 = getelementptr inbounds float* %tmp11242, i64 1
-  %tmp11244 = getelementptr inbounds float* %tmp11243, i64 1
-  %tmp11245 = getelementptr inbounds float* %tmp11244, i64 1
-  %tmp11246 = getelementptr inbounds float* %tmp11245, i64 1
-  %tmp11247 = getelementptr inbounds float* %tmp11246, i64 1
-  %tmp11248 = getelementptr inbounds float* %tmp11247, i64 1
-  %tmp11249 = getelementptr inbounds float* %tmp11248, i64 1
-  %tmp11250 = getelementptr inbounds float* %tmp11249, i64 1
-  %tmp11251 = getelementptr inbounds float* %tmp11250, i64 1
-  %tmp11252 = getelementptr inbounds float* %tmp11251, i64 1
-  %tmp11253 = getelementptr inbounds float* %tmp11252, i64 1
-  %tmp11254 = getelementptr inbounds float* %tmp11253, i64 1
-  %tmp11255 = getelementptr inbounds float* %tmp11254, i64 1
-  %tmp11256 = getelementptr inbounds float* %tmp11255, i64 1
-  %tmp11257 = getelementptr inbounds float* %tmp11256, i64 1
-  %tmp11258 = getelementptr inbounds float* %tmp11257, i64 1
-  %tmp11259 = getelementptr inbounds float* %tmp11258, i64 1
-  %tmp11260 = getelementptr inbounds float* %tmp11259, i64 1
-  %tmp11261 = getelementptr inbounds float* %tmp11260, i64 1
-  %tmp11262 = getelementptr inbounds float* %tmp11261, i64 1
-  %tmp11263 = getelementptr inbounds float* %tmp11262, i64 1
-  %tmp11264 = getelementptr inbounds float* %tmp11263, i64 1
-  %tmp11265 = getelementptr inbounds float* %tmp11264, i64 1
-  %tmp11266 = getelementptr inbounds float* %tmp11265, i64 1
-  %tmp11267 = getelementptr inbounds float* %tmp11266, i64 1
-  %tmp11268 = getelementptr inbounds float* %tmp11267, i64 1
-  %tmp11269 = getelementptr inbounds float* %tmp11268, i64 1
-  %tmp11270 = getelementptr inbounds float* %tmp11269, i64 1
-  %tmp11271 = getelementptr inbounds float* %tmp11270, i64 1
-  %tmp11272 = getelementptr inbounds float* %tmp11271, i64 1
-  %tmp11273 = getelementptr inbounds float* %tmp11272, i64 1
-  %tmp11274 = getelementptr inbounds float* %tmp11273, i64 1
-  %tmp11275 = getelementptr inbounds float* %tmp11274, i64 1
-  %tmp11276 = getelementptr inbounds float* %tmp11275, i64 1
-  %tmp11277 = getelementptr inbounds float* %tmp11276, i64 1
-  %tmp11278 = getelementptr inbounds float* %tmp11277, i64 1
-  %tmp11279 = getelementptr inbounds float* %tmp11278, i64 1
-  %tmp11280 = getelementptr inbounds float* %tmp11279, i64 1
-  %tmp11281 = getelementptr inbounds float* %tmp11280, i64 1
-  %tmp11282 = getelementptr inbounds float* %tmp11281, i64 1
-  %tmp11283 = getelementptr inbounds float* %tmp11282, i64 1
-  %tmp11284 = getelementptr inbounds float* %tmp11283, i64 1
-  %tmp11285 = getelementptr inbounds float* %tmp11284, i64 1
-  %tmp11286 = getelementptr inbounds float* %tmp11285, i64 1
-  %tmp11287 = getelementptr inbounds float* %tmp11286, i64 1
-  %tmp11288 = getelementptr inbounds float* %tmp11287, i64 1
-  %tmp11289 = getelementptr inbounds float* %tmp11288, i64 1
-  %tmp11290 = getelementptr inbounds float* %tmp11289, i64 1
-  %tmp11291 = getelementptr inbounds float* %tmp11290, i64 1
-  %tmp11292 = getelementptr inbounds float* %tmp11291, i64 1
-  %tmp11293 = getelementptr inbounds float* %tmp11292, i64 1
-  %tmp11294 = getelementptr inbounds float* %tmp11293, i64 1
-  %tmp11295 = getelementptr inbounds float* %tmp11294, i64 1
-  %tmp11296 = getelementptr inbounds float* %tmp11295, i64 1
-  %tmp11297 = getelementptr inbounds float* %tmp11296, i64 1
-  %tmp11298 = getelementptr inbounds float* %tmp11297, i64 1
-  %tmp11299 = getelementptr inbounds float* %tmp11298, i64 1
-  %tmp11300 = getelementptr inbounds float* %tmp11299, i64 1
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-  %tmp11302 = getelementptr inbounds float* %tmp11301, i64 1
-  %tmp11303 = getelementptr inbounds float* %tmp11302, i64 1
-  %tmp11304 = getelementptr inbounds float* %tmp11303, i64 1
-  %tmp11305 = getelementptr inbounds float* %tmp11304, i64 1
-  %tmp11306 = getelementptr inbounds float* %tmp11305, i64 1
-  %tmp11307 = getelementptr inbounds float* %tmp11306, i64 1
-  %tmp11308 = getelementptr inbounds float* %tmp11307, i64 1
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-  %tmp11312 = getelementptr inbounds float* %tmp11311, i64 1
-  %tmp11313 = getelementptr inbounds float* %tmp11312, i64 1
-  %tmp11314 = getelementptr inbounds float* %tmp11313, i64 1
-  %tmp11315 = getelementptr inbounds float* %tmp11314, i64 1
-  %tmp11316 = getelementptr inbounds float* %tmp11315, i64 1
-  %tmp11317 = getelementptr inbounds float* %tmp11316, i64 1
-  %tmp11318 = getelementptr inbounds float* %tmp11317, i64 1
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-  %tmp11320 = getelementptr inbounds float* %tmp11319, i64 1
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-  %tmp11322 = getelementptr inbounds float* %tmp11321, i64 1
-  %tmp11323 = getelementptr inbounds float* %tmp11322, i64 1
-  %tmp11324 = getelementptr inbounds float* %tmp11323, i64 1
-  %tmp11325 = getelementptr inbounds float* %tmp11324, i64 1
-  %tmp11326 = getelementptr inbounds float* %tmp11325, i64 1
-  %tmp11327 = getelementptr inbounds float* %tmp11326, i64 1
-  %tmp11328 = getelementptr inbounds float* %tmp11327, i64 1
-  %tmp11329 = getelementptr inbounds float* %tmp11328, i64 1
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-  %tmp11331 = getelementptr inbounds float* %tmp11330, i64 1
-  %tmp11332 = getelementptr inbounds float* %tmp11331, i64 1
-  %tmp11333 = getelementptr inbounds float* %tmp11332, i64 1
-  %tmp11334 = getelementptr inbounds float* %tmp11333, i64 1
-  %tmp11335 = getelementptr inbounds float* %tmp11334, i64 1
-  %tmp11336 = getelementptr inbounds float* %tmp11335, i64 1
-  %tmp11337 = getelementptr inbounds float* %tmp11336, i64 1
-  %tmp11338 = getelementptr inbounds float* %tmp11337, i64 1
-  %tmp11339 = getelementptr inbounds float* %tmp11338, i64 1
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-  %tmp11341 = getelementptr inbounds float* %tmp11340, i64 1
-  %tmp11342 = getelementptr inbounds float* %tmp11341, i64 1
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-  %tmp11344 = getelementptr inbounds float* %tmp11343, i64 1
-  %tmp11345 = getelementptr inbounds float* %tmp11344, i64 1
-  %tmp11346 = getelementptr inbounds float* %tmp11345, i64 1
-  %tmp11347 = getelementptr inbounds float* %tmp11346, i64 1
-  %tmp11348 = getelementptr inbounds float* %tmp11347, i64 1
-  %tmp11349 = getelementptr inbounds float* %tmp11348, i64 1
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-  %tmp11351 = getelementptr inbounds float* %tmp11350, i64 1
-  %tmp11352 = getelementptr inbounds float* %tmp11351, i64 1
-  %tmp11353 = getelementptr inbounds float* %tmp11352, i64 1
-  %tmp11354 = getelementptr inbounds float* %tmp11353, i64 1
-  %tmp11355 = getelementptr inbounds float* %tmp11354, i64 1
-  %tmp11356 = getelementptr inbounds float* %tmp11355, i64 1
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-  %tmp11358 = getelementptr inbounds float* %tmp11357, i64 1
-  %tmp11359 = getelementptr inbounds float* %tmp11358, i64 1
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-  %tmp11368 = getelementptr inbounds float* %tmp11367, i64 1
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-  %tmp11372 = getelementptr inbounds float* %tmp11371, i64 1
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-  %tmp11374 = getelementptr inbounds float* %tmp11373, i64 1
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-  %tmp11385 = getelementptr inbounds float* %tmp11384, i64 1
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-  %tmp11390 = getelementptr inbounds float* %tmp11389, i64 1
-  %tmp11391 = getelementptr inbounds float* %tmp11390, i64 1
-  %tmp11392 = getelementptr inbounds float* %tmp11391, i64 1
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-  %tmp11394 = getelementptr inbounds float* %tmp11393, i64 1
-  %tmp11395 = getelementptr inbounds float* %tmp11394, i64 1
-  %tmp11396 = getelementptr inbounds float* %tmp11395, i64 1
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-  %tmp11404 = getelementptr inbounds float* %tmp11403, i64 1
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-  %tmp11420 = getelementptr inbounds float* %tmp11419, i64 1
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-  %tmp11422 = getelementptr inbounds float* %tmp11421, i64 1
-  %tmp11423 = getelementptr inbounds float* %tmp11422, i64 1
-  %tmp11424 = getelementptr inbounds float* %tmp11423, i64 1
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-  %tmp11448 = getelementptr inbounds float* %tmp11447, i64 1
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-  %tmp11469 = getelementptr inbounds float* %tmp11468, i64 1
-  %tmp11470 = getelementptr inbounds float* %tmp11469, i64 1
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-  %tmp11472 = getelementptr inbounds float* %tmp11471, i64 1
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-  %tmp11488 = getelementptr inbounds float* %tmp11487, i64 1
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-  %tmp11493 = getelementptr inbounds float* %tmp11492, i64 1
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-  %tmp11498 = getelementptr inbounds float* %tmp11497, i64 1
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-  %tmp11513 = getelementptr inbounds float* %tmp11512, i64 1
-  %tmp11514 = getelementptr inbounds float* %tmp11513, i64 1
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-  %tmp11593 = getelementptr inbounds float* %tmp11592, i64 1
-  %tmp11594 = getelementptr inbounds float* %tmp11593, i64 1
-  %tmp11595 = getelementptr inbounds float* %tmp11594, i64 1
-  %tmp11596 = getelementptr inbounds float* %tmp11595, i64 1
-  %tmp11597 = getelementptr inbounds float* %tmp11596, i64 1
-  %tmp11598 = getelementptr inbounds float* %tmp11597, i64 1
-  %tmp11599 = getelementptr inbounds float* %tmp11598, i64 1
-  %tmp11600 = getelementptr inbounds float* %tmp11599, i64 1
-  %tmp11601 = getelementptr inbounds float* %tmp11600, i64 1
-  %tmp11602 = getelementptr inbounds float* %tmp11601, i64 1
-  %tmp11603 = getelementptr inbounds float* %tmp11602, i64 1
-  %tmp11604 = getelementptr inbounds float* %tmp11603, i64 1
-  %tmp11605 = getelementptr inbounds float* %tmp11604, i64 1
-  %tmp11606 = getelementptr inbounds float* %tmp11605, i64 1
-  %tmp11607 = getelementptr inbounds float* %tmp11606, i64 1
-  %tmp11608 = getelementptr inbounds float* %tmp11607, i64 1
-  %tmp11609 = getelementptr inbounds float* %tmp11608, i64 1
-  %tmp11610 = getelementptr inbounds float* %tmp11609, i64 1
-  %tmp11611 = getelementptr inbounds float* %tmp11610, i64 1
-  %tmp11612 = getelementptr inbounds float* %tmp11611, i64 1
-  %tmp11613 = getelementptr inbounds float* %tmp11612, i64 1
-  %tmp11614 = getelementptr inbounds float* %tmp11613, i64 1
-  %tmp11615 = getelementptr inbounds float* %tmp11614, i64 1
-  %tmp11616 = getelementptr inbounds float* %tmp11615, i64 1
-  %tmp11617 = getelementptr inbounds float* %tmp11616, i64 1
-  %tmp11618 = getelementptr inbounds float* %tmp11617, i64 1
-  %tmp11619 = getelementptr inbounds float* %tmp11618, i64 1
-  %tmp11620 = getelementptr inbounds float* %tmp11619, i64 1
-  %tmp11621 = getelementptr inbounds float* %tmp11620, i64 1
-  %tmp11622 = getelementptr inbounds float* %tmp11621, i64 1
-  %tmp11623 = getelementptr inbounds float* %tmp11622, i64 1
-  %tmp11624 = getelementptr inbounds float* %tmp11623, i64 1
-  %tmp11625 = getelementptr inbounds float* %tmp11624, i64 1
-  %tmp11626 = getelementptr inbounds float* %tmp11625, i64 1
-  %tmp11627 = getelementptr inbounds float* %tmp11626, i64 1
-  %tmp11628 = getelementptr inbounds float* %tmp11627, i64 1
-  %tmp11629 = getelementptr inbounds float* %tmp11628, i64 1
-  %tmp11630 = getelementptr inbounds float* %tmp11629, i64 1
-  %tmp11631 = getelementptr inbounds float* %tmp11630, i64 1
-  %tmp11632 = getelementptr inbounds float* %tmp11631, i64 1
-  %tmp11633 = getelementptr inbounds float* %tmp11632, i64 1
-  %tmp11634 = getelementptr inbounds float* %tmp11633, i64 1
-  %tmp11635 = getelementptr inbounds float* %tmp11634, i64 1
-  %tmp11636 = getelementptr inbounds float* %tmp11635, i64 1
-  %tmp11637 = getelementptr inbounds float* %tmp11636, i64 1
-  %tmp11638 = getelementptr inbounds float* %tmp11637, i64 1
-  %tmp11639 = getelementptr inbounds float* %tmp11638, i64 1
-  %tmp11640 = getelementptr inbounds float* %tmp11639, i64 1
-  %tmp11641 = getelementptr inbounds float* %tmp11640, i64 1
-  %tmp11642 = getelementptr inbounds float* %tmp11641, i64 1
-  %tmp11643 = getelementptr inbounds float* %tmp11642, i64 1
-  %tmp11644 = getelementptr inbounds float* %tmp11643, i64 1
-  %tmp11645 = getelementptr inbounds float* %tmp11644, i64 1
-  %tmp11646 = getelementptr inbounds float* %tmp11645, i64 1
-  %tmp11647 = getelementptr inbounds float* %tmp11646, i64 1
-  %tmp11648 = getelementptr inbounds float* %tmp11647, i64 1
-  %tmp11649 = getelementptr inbounds float* %tmp11648, i64 1
-  %tmp11650 = getelementptr inbounds float* %tmp11649, i64 1
-  %tmp11651 = getelementptr inbounds float* %tmp11650, i64 1
-  %tmp11652 = getelementptr inbounds float* %tmp11651, i64 1
-  %tmp11653 = getelementptr inbounds float* %tmp11652, i64 1
-  %tmp11654 = getelementptr inbounds float* %tmp11653, i64 1
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-  %tmp11656 = getelementptr inbounds float* %tmp11655, i64 1
-  %tmp11657 = getelementptr inbounds float* %tmp11656, i64 1
-  %tmp11658 = getelementptr inbounds float* %tmp11657, i64 1
-  %tmp11659 = getelementptr inbounds float* %tmp11658, i64 1
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-  %tmp11662 = getelementptr inbounds float* %tmp11661, i64 1
-  %tmp11663 = getelementptr inbounds float* %tmp11662, i64 1
-  %tmp11664 = getelementptr inbounds float* %tmp11663, i64 1
-  %tmp11665 = getelementptr inbounds float* %tmp11664, i64 1
-  %tmp11666 = getelementptr inbounds float* %tmp11665, i64 1
-  %tmp11667 = getelementptr inbounds float* %tmp11666, i64 1
-  %tmp11668 = getelementptr inbounds float* %tmp11667, i64 1
-  %tmp11669 = getelementptr inbounds float* %tmp11668, i64 1
-  %tmp11670 = getelementptr inbounds float* %tmp11669, i64 1
-  %tmp11671 = getelementptr inbounds float* %tmp11670, i64 1
-  %tmp11672 = getelementptr inbounds float* %tmp11671, i64 1
-  %tmp11673 = getelementptr inbounds float* %tmp11672, i64 1
-  %tmp11674 = getelementptr inbounds float* %tmp11673, i64 1
-  %tmp11675 = getelementptr inbounds float* %tmp11674, i64 1
-  %tmp11676 = getelementptr inbounds float* %tmp11675, i64 1
-  %tmp11677 = getelementptr inbounds float* %tmp11676, i64 1
-  %tmp11678 = getelementptr inbounds float* %tmp11677, i64 1
-  %tmp11679 = getelementptr inbounds float* %tmp11678, i64 1
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-  %tmp11683 = getelementptr inbounds float* %tmp11682, i64 1
-  %tmp11684 = getelementptr inbounds float* %tmp11683, i64 1
-  %tmp11685 = getelementptr inbounds float* %tmp11684, i64 1
-  %tmp11686 = getelementptr inbounds float* %tmp11685, i64 1
-  %tmp11687 = getelementptr inbounds float* %tmp11686, i64 1
-  %tmp11688 = getelementptr inbounds float* %tmp11687, i64 1
-  %tmp11689 = getelementptr inbounds float* %tmp11688, i64 1
-  %tmp11690 = getelementptr inbounds float* %tmp11689, i64 1
-  %tmp11691 = getelementptr inbounds float* %tmp11690, i64 1
-  %tmp11692 = getelementptr inbounds float* %tmp11691, i64 1
-  %tmp11693 = getelementptr inbounds float* %tmp11692, i64 1
-  %tmp11694 = getelementptr inbounds float* %tmp11693, i64 1
-  %tmp11695 = getelementptr inbounds float* %tmp11694, i64 1
-  %tmp11696 = getelementptr inbounds float* %tmp11695, i64 1
-  %tmp11697 = getelementptr inbounds float* %tmp11696, i64 1
-  %tmp11698 = getelementptr inbounds float* %tmp11697, i64 1
-  %tmp11699 = getelementptr inbounds float* %tmp11698, i64 1
-  %tmp11700 = getelementptr inbounds float* %tmp11699, i64 1
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-  %tmp11702 = getelementptr inbounds float* %tmp11701, i64 1
-  %tmp11703 = getelementptr inbounds float* %tmp11702, i64 1
-  %tmp11704 = getelementptr inbounds float* %tmp11703, i64 1
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-  %tmp11707 = getelementptr inbounds float* %tmp11706, i64 1
-  %tmp11708 = getelementptr inbounds float* %tmp11707, i64 1
-  %tmp11709 = getelementptr inbounds float* %tmp11708, i64 1
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-  %tmp11712 = getelementptr inbounds float* %tmp11711, i64 1
-  %tmp11713 = getelementptr inbounds float* %tmp11712, i64 1
-  %tmp11714 = getelementptr inbounds float* %tmp11713, i64 1
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-  %tmp11717 = getelementptr inbounds float* %tmp11716, i64 1
-  %tmp11718 = getelementptr inbounds float* %tmp11717, i64 1
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-  %tmp11720 = getelementptr inbounds float* %tmp11719, i64 1
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-  %tmp11725 = getelementptr inbounds float* %tmp11724, i64 1
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-  %tmp11738 = getelementptr inbounds float* %tmp11737, i64 1
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-  %tmp11741 = getelementptr inbounds float* %tmp11740, i64 1
-  %tmp11742 = getelementptr inbounds float* %tmp11741, i64 1
-  %tmp11743 = getelementptr inbounds float* %tmp11742, i64 1
-  %tmp11744 = getelementptr inbounds float* %tmp11743, i64 1
-  %tmp11745 = getelementptr inbounds float* %tmp11744, i64 1
-  %tmp11746 = getelementptr inbounds float* %tmp11745, i64 1
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-  %tmp11749 = getelementptr inbounds float* %tmp11748, i64 1
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-  %tmp11761 = getelementptr inbounds float* %tmp11760, i64 1
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-  %tmp11792 = getelementptr inbounds float* %tmp11791, i64 1
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-  %tmp11807 = getelementptr inbounds float* %tmp11806, i64 1
-  %tmp11808 = getelementptr inbounds float* %tmp11807, i64 1
-  %tmp11809 = getelementptr inbounds float* %tmp11808, i64 1
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-  %tmp11812 = getelementptr inbounds float* %tmp11811, i64 1
-  %tmp11813 = getelementptr inbounds float* %tmp11812, i64 1
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-  %tmp11817 = getelementptr inbounds float* %tmp11816, i64 1
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-  %tmp11820 = getelementptr inbounds float* %tmp11819, i64 1
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-  %tmp11822 = getelementptr inbounds float* %tmp11821, i64 1
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-  %tmp11826 = getelementptr inbounds float* %tmp11825, i64 1
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-  %tmp11842 = getelementptr inbounds float* %tmp11841, i64 1
-  %tmp11843 = getelementptr inbounds float* %tmp11842, i64 1
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-  %tmp11846 = getelementptr inbounds float* %tmp11845, i64 1
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-  %tmp11932 = getelementptr inbounds float* %tmp11931, i64 1
-  %tmp11933 = getelementptr inbounds float* %tmp11932, i64 1
-  %tmp11934 = getelementptr inbounds float* %tmp11933, i64 1
-  %tmp11935 = getelementptr inbounds float* %tmp11934, i64 1
-  %tmp11936 = getelementptr inbounds float* %tmp11935, i64 1
-  %tmp11937 = getelementptr inbounds float* %tmp11936, i64 1
-  %tmp11938 = getelementptr inbounds float* %tmp11937, i64 1
-  %tmp11939 = getelementptr inbounds float* %tmp11938, i64 1
-  %tmp11940 = getelementptr inbounds float* %tmp11939, i64 1
-  %tmp11941 = getelementptr inbounds float* %tmp11940, i64 1
-  %tmp11942 = getelementptr inbounds float* %tmp11941, i64 1
-  %tmp11943 = getelementptr inbounds float* %tmp11942, i64 1
-  %tmp11944 = getelementptr inbounds float* %tmp11943, i64 1
-  %tmp11945 = getelementptr inbounds float* %tmp11944, i64 1
-  %tmp11946 = getelementptr inbounds float* %tmp11945, i64 1
-  %tmp11947 = getelementptr inbounds float* %tmp11946, i64 1
-  %tmp11948 = getelementptr inbounds float* %tmp11947, i64 1
-  %tmp11949 = getelementptr inbounds float* %tmp11948, i64 1
-  %tmp11950 = getelementptr inbounds float* %tmp11949, i64 1
-  %tmp11951 = getelementptr inbounds float* %tmp11950, i64 1
-  %tmp11952 = getelementptr inbounds float* %tmp11951, i64 1
-  %tmp11953 = getelementptr inbounds float* %tmp11952, i64 1
-  %tmp11954 = getelementptr inbounds float* %tmp11953, i64 1
-  %tmp11955 = getelementptr inbounds float* %tmp11954, i64 1
-  %tmp11956 = getelementptr inbounds float* %tmp11955, i64 1
-  %tmp11957 = getelementptr inbounds float* %tmp11956, i64 1
-  %tmp11958 = getelementptr inbounds float* %tmp11957, i64 1
-  %tmp11959 = getelementptr inbounds float* %tmp11958, i64 1
-  %tmp11960 = getelementptr inbounds float* %tmp11959, i64 1
-  %tmp11961 = getelementptr inbounds float* %tmp11960, i64 1
-  %tmp11962 = getelementptr inbounds float* %tmp11961, i64 1
-  %tmp11963 = getelementptr inbounds float* %tmp11962, i64 1
-  %tmp11964 = getelementptr inbounds float* %tmp11963, i64 1
-  %tmp11965 = getelementptr inbounds float* %tmp11964, i64 1
-  %tmp11966 = getelementptr inbounds float* %tmp11965, i64 1
-  %tmp11967 = getelementptr inbounds float* %tmp11966, i64 1
-  %tmp11968 = getelementptr inbounds float* %tmp11967, i64 1
-  %tmp11969 = getelementptr inbounds float* %tmp11968, i64 1
-  %tmp11970 = getelementptr inbounds float* %tmp11969, i64 1
-  %tmp11971 = getelementptr inbounds float* %tmp11970, i64 1
-  %tmp11972 = getelementptr inbounds float* %tmp11971, i64 1
-  %tmp11973 = getelementptr inbounds float* %tmp11972, i64 1
-  %tmp11974 = getelementptr inbounds float* %tmp11973, i64 1
-  %tmp11975 = getelementptr inbounds float* %tmp11974, i64 1
-  %tmp11976 = getelementptr inbounds float* %tmp11975, i64 1
-  %tmp11977 = getelementptr inbounds float* %tmp11976, i64 1
-  %tmp11978 = getelementptr inbounds float* %tmp11977, i64 1
-  %tmp11979 = getelementptr inbounds float* %tmp11978, i64 1
-  %tmp11980 = getelementptr inbounds float* %tmp11979, i64 1
-  %tmp11981 = getelementptr inbounds float* %tmp11980, i64 1
-  %tmp11982 = getelementptr inbounds float* %tmp11981, i64 1
-  %tmp11983 = getelementptr inbounds float* %tmp11982, i64 1
-  %tmp11984 = getelementptr inbounds float* %tmp11983, i64 1
-  %tmp11985 = getelementptr inbounds float* %tmp11984, i64 1
-  %tmp11986 = getelementptr inbounds float* %tmp11985, i64 1
-  %tmp11987 = getelementptr inbounds float* %tmp11986, i64 1
-  %tmp11988 = getelementptr inbounds float* %tmp11987, i64 1
-  %tmp11989 = getelementptr inbounds float* %tmp11988, i64 1
-  %tmp11990 = getelementptr inbounds float* %tmp11989, i64 1
-  %tmp11991 = getelementptr inbounds float* %tmp11990, i64 1
-  %tmp11992 = getelementptr inbounds float* %tmp11991, i64 1
-  %tmp11993 = getelementptr inbounds float* %tmp11992, i64 1
-  %tmp11994 = getelementptr inbounds float* %tmp11993, i64 1
-  %tmp11995 = getelementptr inbounds float* %tmp11994, i64 1
-  %tmp11996 = getelementptr inbounds float* %tmp11995, i64 1
-  %tmp11997 = getelementptr inbounds float* %tmp11996, i64 1
-  %tmp11998 = getelementptr inbounds float* %tmp11997, i64 1
-  %tmp11999 = getelementptr inbounds float* %tmp11998, i64 1
-  %tmp12000 = getelementptr inbounds float* %tmp11999, i64 1
-  %tmp12001 = getelementptr inbounds float* %tmp12000, i64 1
-  %tmp12002 = getelementptr inbounds float* %tmp12001, i64 1
-  %tmp12003 = getelementptr inbounds float* %tmp12002, i64 1
-  %tmp12004 = getelementptr inbounds float* %tmp12003, i64 1
-  %tmp12005 = getelementptr inbounds float* %tmp12004, i64 1
-  %tmp12006 = getelementptr inbounds float* %tmp12005, i64 1
-  %tmp12007 = getelementptr inbounds float* %tmp12006, i64 1
-  %tmp12008 = getelementptr inbounds float* %tmp12007, i64 1
-  %tmp12009 = getelementptr inbounds float* %tmp12008, i64 1
-  %tmp12010 = getelementptr inbounds float* %tmp12009, i64 1
-  %tmp12011 = getelementptr inbounds float* %tmp12010, i64 1
-  %tmp12012 = getelementptr inbounds float* %tmp12011, i64 1
-  %tmp12013 = getelementptr inbounds float* %tmp12012, i64 1
-  %tmp12014 = getelementptr inbounds float* %tmp12013, i64 1
-  %tmp12015 = getelementptr inbounds float* %tmp12014, i64 1
-  %tmp12016 = getelementptr inbounds float* %tmp12015, i64 1
-  %tmp12017 = getelementptr inbounds float* %tmp12016, i64 1
-  %tmp12018 = getelementptr inbounds float* %tmp12017, i64 1
-  %tmp12019 = getelementptr inbounds float* %tmp12018, i64 1
-  %tmp12020 = getelementptr inbounds float* %tmp12019, i64 1
-  %tmp12021 = getelementptr inbounds float* %tmp12020, i64 1
-  %tmp12022 = getelementptr inbounds float* %tmp12021, i64 1
-  %tmp12023 = getelementptr inbounds float* %tmp12022, i64 1
-  %tmp12024 = getelementptr inbounds float* %tmp12023, i64 1
-  %tmp12025 = getelementptr inbounds float* %tmp12024, i64 1
-  %tmp12026 = getelementptr inbounds float* %tmp12025, i64 1
-  %tmp12027 = getelementptr inbounds float* %tmp12026, i64 1
-  %tmp12028 = getelementptr inbounds float* %tmp12027, i64 1
-  %tmp12029 = getelementptr inbounds float* %tmp12028, i64 1
-  %tmp12030 = getelementptr inbounds float* %tmp12029, i64 1
-  %tmp12031 = getelementptr inbounds float* %tmp12030, i64 1
-  %tmp12032 = getelementptr inbounds float* %tmp12031, i64 1
-  %tmp12033 = getelementptr inbounds float* %tmp12032, i64 1
-  %tmp12034 = getelementptr inbounds float* %tmp12033, i64 1
-  %tmp12035 = getelementptr inbounds float* %tmp12034, i64 1
-  %tmp12036 = getelementptr inbounds float* %tmp12035, i64 1
-  %tmp12037 = getelementptr inbounds float* %tmp12036, i64 1
-  %tmp12038 = getelementptr inbounds float* %tmp12037, i64 1
-  %tmp12039 = getelementptr inbounds float* %tmp12038, i64 1
-  %tmp12040 = getelementptr inbounds float* %tmp12039, i64 1
-  %tmp12041 = getelementptr inbounds float* %tmp12040, i64 1
-  %tmp12042 = getelementptr inbounds float* %tmp12041, i64 1
-  %tmp12043 = getelementptr inbounds float* %tmp12042, i64 1
-  %tmp12044 = getelementptr inbounds float* %tmp12043, i64 1
-  %tmp12045 = getelementptr inbounds float* %tmp12044, i64 1
-  %tmp12046 = getelementptr inbounds float* %tmp12045, i64 1
-  %tmp12047 = getelementptr inbounds float* %tmp12046, i64 1
-  %tmp12048 = getelementptr inbounds float* %tmp12047, i64 1
-  %tmp12049 = getelementptr inbounds float* %tmp12048, i64 1
-  %tmp12050 = getelementptr inbounds float* %tmp12049, i64 1
-  %tmp12051 = getelementptr inbounds float* %tmp12050, i64 1
-  %tmp12052 = getelementptr inbounds float* %tmp12051, i64 1
-  %tmp12053 = getelementptr inbounds float* %tmp12052, i64 1
-  %tmp12054 = getelementptr inbounds float* %tmp12053, i64 1
-  %tmp12055 = getelementptr inbounds float* %tmp12054, i64 1
-  %tmp12056 = getelementptr inbounds float* %tmp12055, i64 1
-  %tmp12057 = getelementptr inbounds float* %tmp12056, i64 1
-  %tmp12058 = getelementptr inbounds float* %tmp12057, i64 1
-  %tmp12059 = getelementptr inbounds float* %tmp12058, i64 1
-  %tmp12060 = getelementptr inbounds float* %tmp12059, i64 1
-  %tmp12061 = getelementptr inbounds float* %tmp12060, i64 1
-  %tmp12062 = getelementptr inbounds float* %tmp12061, i64 1
-  %tmp12063 = getelementptr inbounds float* %tmp12062, i64 1
-  %tmp12064 = getelementptr inbounds float* %tmp12063, i64 1
-  %tmp12065 = getelementptr inbounds float* %tmp12064, i64 1
-  %tmp12066 = getelementptr inbounds float* %tmp12065, i64 1
-  %tmp12067 = getelementptr inbounds float* %tmp12066, i64 1
-  %tmp12068 = getelementptr inbounds float* %tmp12067, i64 1
-  %tmp12069 = getelementptr inbounds float* %tmp12068, i64 1
-  %tmp12070 = getelementptr inbounds float* %tmp12069, i64 1
-  %tmp12071 = getelementptr inbounds float* %tmp12070, i64 1
-  %tmp12072 = getelementptr inbounds float* %tmp12071, i64 1
-  %tmp12073 = getelementptr inbounds float* %tmp12072, i64 1
-  %tmp12074 = getelementptr inbounds float* %tmp12073, i64 1
-  %tmp12075 = getelementptr inbounds float* %tmp12074, i64 1
-  %tmp12076 = getelementptr inbounds float* %tmp12075, i64 1
-  %tmp12077 = getelementptr inbounds float* %tmp12076, i64 1
-  %tmp12078 = getelementptr inbounds float* %tmp12077, i64 1
-  %tmp12079 = getelementptr inbounds float* %tmp12078, i64 1
-  %tmp12080 = getelementptr inbounds float* %tmp12079, i64 1
-  %tmp12081 = getelementptr inbounds float* %tmp12080, i64 1
-  %tmp12082 = getelementptr inbounds float* %tmp12081, i64 1
-  %tmp12083 = getelementptr inbounds float* %tmp12082, i64 1
-  %tmp12084 = getelementptr inbounds float* %tmp12083, i64 1
-  %tmp12085 = getelementptr inbounds float* %tmp12084, i64 1
-  %tmp12086 = getelementptr inbounds float* %tmp12085, i64 1
-  %tmp12087 = getelementptr inbounds float* %tmp12086, i64 1
-  %tmp12088 = getelementptr inbounds float* %tmp12087, i64 1
-  %tmp12089 = getelementptr inbounds float* %tmp12088, i64 1
-  %tmp12090 = getelementptr inbounds float* %tmp12089, i64 1
-  %tmp12091 = getelementptr inbounds float* %tmp12090, i64 1
-  %tmp12092 = getelementptr inbounds float* %tmp12091, i64 1
-  %tmp12093 = getelementptr inbounds float* %tmp12092, i64 1
-  %tmp12094 = getelementptr inbounds float* %tmp12093, i64 1
-  %tmp12095 = getelementptr inbounds float* %tmp12094, i64 1
-  %tmp12096 = getelementptr inbounds float* %tmp12095, i64 1
-  %tmp12097 = getelementptr inbounds float* %tmp12096, i64 1
-  %tmp12098 = getelementptr inbounds float* %tmp12097, i64 1
-  %tmp12099 = getelementptr inbounds float* %tmp12098, i64 1
-  %tmp12100 = getelementptr inbounds float* %tmp12099, i64 1
-  %tmp12101 = getelementptr inbounds float* %tmp12100, i64 1
-  %tmp12102 = getelementptr inbounds float* %tmp12101, i64 1
-  %tmp12103 = getelementptr inbounds float* %tmp12102, i64 1
-  %tmp12104 = getelementptr inbounds float* %tmp12103, i64 1
-  %tmp12105 = getelementptr inbounds float* %tmp12104, i64 1
-  %tmp12106 = getelementptr inbounds float* %tmp12105, i64 1
-  %tmp12107 = getelementptr inbounds float* %tmp12106, i64 1
-  %tmp12108 = getelementptr inbounds float* %tmp12107, i64 1
-  %tmp12109 = getelementptr inbounds float* %tmp12108, i64 1
-  %tmp12110 = getelementptr inbounds float* %tmp12109, i64 1
-  %tmp12111 = getelementptr inbounds float* %tmp12110, i64 1
-  %tmp12112 = getelementptr inbounds float* %tmp12111, i64 1
-  %tmp12113 = getelementptr inbounds float* %tmp12112, i64 1
-  %tmp12114 = getelementptr inbounds float* %tmp12113, i64 1
-  %tmp12115 = getelementptr inbounds float* %tmp12114, i64 1
-  %tmp12116 = getelementptr inbounds float* %tmp12115, i64 1
-  %tmp12117 = getelementptr inbounds float* %tmp12116, i64 1
-  %tmp12118 = getelementptr inbounds float* %tmp12117, i64 1
-  %tmp12119 = getelementptr inbounds float* %tmp12118, i64 1
-  %tmp12120 = getelementptr inbounds float* %tmp12119, i64 1
-  %tmp12121 = getelementptr inbounds float* %tmp12120, i64 1
-  %tmp12122 = getelementptr inbounds float* %tmp12121, i64 1
-  %tmp12123 = getelementptr inbounds float* %tmp12122, i64 1
-  %tmp12124 = getelementptr inbounds float* %tmp12123, i64 1
-  %tmp12125 = getelementptr inbounds float* %tmp12124, i64 1
-  %tmp12126 = getelementptr inbounds float* %tmp12125, i64 1
-  %tmp12127 = getelementptr inbounds float* %tmp12126, i64 1
-  %tmp12128 = getelementptr inbounds float* %tmp12127, i64 1
-  %tmp12129 = getelementptr inbounds float* %tmp12128, i64 1
-  %tmp12130 = getelementptr inbounds float* %tmp12129, i64 1
-  %tmp12131 = getelementptr inbounds float* %tmp12130, i64 1
-  %tmp12132 = getelementptr inbounds float* %tmp12131, i64 1
-  %tmp12133 = getelementptr inbounds float* %tmp12132, i64 1
-  %tmp12134 = getelementptr inbounds float* %tmp12133, i64 1
-  %tmp12135 = getelementptr inbounds float* %tmp12134, i64 1
-  %tmp12136 = getelementptr inbounds float* %tmp12135, i64 1
-  %tmp12137 = getelementptr inbounds float* %tmp12136, i64 1
-  %tmp12138 = getelementptr inbounds float* %tmp12137, i64 1
-  %tmp12139 = getelementptr inbounds float* %tmp12138, i64 1
-  %tmp12140 = getelementptr inbounds float* %tmp12139, i64 1
-  %tmp12141 = getelementptr inbounds float* %tmp12140, i64 1
-  %tmp12142 = getelementptr inbounds float* %tmp12141, i64 1
-  %tmp12143 = getelementptr inbounds float* %tmp12142, i64 1
-  %tmp12144 = getelementptr inbounds float* %tmp12143, i64 1
-  %tmp12145 = getelementptr inbounds float* %tmp12144, i64 1
-  %tmp12146 = getelementptr inbounds float* %tmp12145, i64 1
-  %tmp12147 = getelementptr inbounds float* %tmp12146, i64 1
-  %tmp12148 = getelementptr inbounds float* %tmp12147, i64 1
-  %tmp12149 = getelementptr inbounds float* %tmp12148, i64 1
-  %tmp12150 = getelementptr inbounds float* %tmp12149, i64 1
-  %tmp12151 = getelementptr inbounds float* %tmp12150, i64 1
-  %tmp12152 = getelementptr inbounds float* %tmp12151, i64 1
-  %tmp12153 = getelementptr inbounds float* %tmp12152, i64 1
-  %tmp12154 = getelementptr inbounds float* %tmp12153, i64 1
-  %tmp12155 = getelementptr inbounds float* %tmp12154, i64 1
-  %tmp12156 = getelementptr inbounds float* %tmp12155, i64 1
-  %tmp12157 = getelementptr inbounds float* %tmp12156, i64 1
-  %tmp12158 = getelementptr inbounds float* %tmp12157, i64 1
-  %tmp12159 = getelementptr inbounds float* %tmp12158, i64 1
-  %tmp12160 = getelementptr inbounds float* %tmp12159, i64 1
-  %tmp12161 = getelementptr inbounds float* %tmp12160, i64 1
-  %tmp12162 = getelementptr inbounds float* %tmp12161, i64 1
-  %tmp12163 = getelementptr inbounds float* %tmp12162, i64 1
-  %tmp12164 = getelementptr inbounds float* %tmp12163, i64 1
-  %tmp12165 = getelementptr inbounds float* %tmp12164, i64 1
-  %tmp12166 = getelementptr inbounds float* %tmp12165, i64 1
-  %tmp12167 = getelementptr inbounds float* %tmp12166, i64 1
-  %tmp12168 = getelementptr inbounds float* %tmp12167, i64 1
-  %tmp12169 = getelementptr inbounds float* %tmp12168, i64 1
-  %tmp12170 = getelementptr inbounds float* %tmp12169, i64 1
-  %tmp12171 = getelementptr inbounds float* %tmp12170, i64 1
-  %tmp12172 = getelementptr inbounds float* %tmp12171, i64 1
-  %tmp12173 = getelementptr inbounds float* %tmp12172, i64 1
-  %tmp12174 = getelementptr inbounds float* %tmp12173, i64 1
-  %tmp12175 = getelementptr inbounds float* %tmp12174, i64 1
-  %tmp12176 = getelementptr inbounds float* %tmp12175, i64 1
-  %tmp12177 = getelementptr inbounds float* %tmp12176, i64 1
-  %tmp12178 = getelementptr inbounds float* %tmp12177, i64 1
-  %tmp12179 = getelementptr inbounds float* %tmp12178, i64 1
-  %tmp12180 = getelementptr inbounds float* %tmp12179, i64 1
-  %tmp12181 = getelementptr inbounds float* %tmp12180, i64 1
-  %tmp12182 = getelementptr inbounds float* %tmp12181, i64 1
-  %tmp12183 = getelementptr inbounds float* %tmp12182, i64 1
-  %tmp12184 = getelementptr inbounds float* %tmp12183, i64 1
-  %tmp12185 = getelementptr inbounds float* %tmp12184, i64 1
-  %tmp12186 = getelementptr inbounds float* %tmp12185, i64 1
-  %tmp12187 = getelementptr inbounds float* %tmp12186, i64 1
-  %tmp12188 = getelementptr inbounds float* %tmp12187, i64 1
-  %tmp12189 = getelementptr inbounds float* %tmp12188, i64 1
-  %tmp12190 = getelementptr inbounds float* %tmp12189, i64 1
-  %tmp12191 = getelementptr inbounds float* %tmp12190, i64 1
-  %tmp12192 = getelementptr inbounds float* %tmp12191, i64 1
-  %tmp12193 = getelementptr inbounds float* %tmp12192, i64 1
-  %tmp12194 = getelementptr inbounds float* %tmp12193, i64 1
-  %tmp12195 = getelementptr inbounds float* %tmp12194, i64 1
-  %tmp12196 = getelementptr inbounds float* %tmp12195, i64 1
-  %tmp12197 = getelementptr inbounds float* %tmp12196, i64 1
-  %tmp12198 = getelementptr inbounds float* %tmp12197, i64 1
-  %tmp12199 = getelementptr inbounds float* %tmp12198, i64 1
-  %tmp12200 = getelementptr inbounds float* %tmp12199, i64 1
-  %tmp12201 = getelementptr inbounds float* %tmp12200, i64 1
-  %tmp12202 = getelementptr inbounds float* %tmp12201, i64 1
-  %tmp12203 = getelementptr inbounds float* %tmp12202, i64 1
-  %tmp12204 = getelementptr inbounds float* %tmp12203, i64 1
-  %tmp12205 = getelementptr inbounds float* %tmp12204, i64 1
-  %tmp12206 = getelementptr inbounds float* %tmp12205, i64 1
-  %tmp12207 = getelementptr inbounds float* %tmp12206, i64 1
-  %tmp12208 = getelementptr inbounds float* %tmp12207, i64 1
-  %tmp12209 = getelementptr inbounds float* %tmp12208, i64 1
-  %tmp12210 = getelementptr inbounds float* %tmp12209, i64 1
-  %tmp12211 = getelementptr inbounds float* %tmp12210, i64 1
-  %tmp12212 = getelementptr inbounds float* %tmp12211, i64 1
-  %tmp12213 = getelementptr inbounds float* %tmp12212, i64 1
-  %tmp12214 = getelementptr inbounds float* %tmp12213, i64 1
-  %tmp12215 = getelementptr inbounds float* %tmp12214, i64 1
-  %tmp12216 = getelementptr inbounds float* %tmp12215, i64 1
-  %tmp12217 = getelementptr inbounds float* %tmp12216, i64 1
-  %tmp12218 = getelementptr inbounds float* %tmp12217, i64 1
-  %tmp12219 = getelementptr inbounds float* %tmp12218, i64 1
-  %tmp12220 = getelementptr inbounds float* %tmp12219, i64 1
-  %tmp12221 = getelementptr inbounds float* %tmp12220, i64 1
-  %tmp12222 = getelementptr inbounds float* %tmp12221, i64 1
-  %tmp12223 = getelementptr inbounds float* %tmp12222, i64 1
-  %tmp12224 = getelementptr inbounds float* %tmp12223, i64 1
-  %tmp12225 = getelementptr inbounds float* %tmp12224, i64 1
-  %tmp12226 = getelementptr inbounds float* %tmp12225, i64 1
-  %tmp12227 = getelementptr inbounds float* %tmp12226, i64 1
-  %tmp12228 = getelementptr inbounds float* %tmp12227, i64 1
-  %tmp12229 = getelementptr inbounds float* %tmp12228, i64 1
-  %tmp12230 = getelementptr inbounds float* %tmp12229, i64 1
-  %tmp12231 = getelementptr inbounds float* %tmp12230, i64 1
-  %tmp12232 = getelementptr inbounds float* %tmp12231, i64 1
-  %tmp12233 = getelementptr inbounds float* %tmp12232, i64 1
-  %tmp12234 = getelementptr inbounds float* %tmp12233, i64 1
-  %tmp12235 = getelementptr inbounds float* %tmp12234, i64 1
-  %tmp12236 = getelementptr inbounds float* %tmp12235, i64 1
-  %tmp12237 = getelementptr inbounds float* %tmp12236, i64 1
-  %tmp12238 = getelementptr inbounds float* %tmp12237, i64 1
-  %tmp12239 = getelementptr inbounds float* %tmp12238, i64 1
-  %tmp12240 = getelementptr inbounds float* %tmp12239, i64 1
-  %tmp12241 = getelementptr inbounds float* %tmp12240, i64 1
-  %tmp12242 = getelementptr inbounds float* %tmp12241, i64 1
-  %tmp12243 = getelementptr inbounds float* %tmp12242, i64 1
-  %tmp12244 = getelementptr inbounds float* %tmp12243, i64 1
-  %tmp12245 = getelementptr inbounds float* %tmp12244, i64 1
-  %tmp12246 = getelementptr inbounds float* %tmp12245, i64 1
-  %tmp12247 = getelementptr inbounds float* %tmp12246, i64 1
-  %tmp12248 = getelementptr inbounds float* %tmp12247, i64 1
-  %tmp12249 = getelementptr inbounds float* %tmp12248, i64 1
-  %tmp12250 = getelementptr inbounds float* %tmp12249, i64 1
-  %tmp12251 = getelementptr inbounds float* %tmp12250, i64 1
-  %tmp12252 = getelementptr inbounds float* %tmp12251, i64 1
-  %tmp12253 = getelementptr inbounds float* %tmp12252, i64 1
-  %tmp12254 = getelementptr inbounds float* %tmp12253, i64 1
-  %tmp12255 = getelementptr inbounds float* %tmp12254, i64 1
-  %tmp12256 = getelementptr inbounds float* %tmp12255, i64 1
-  %tmp12257 = getelementptr inbounds float* %tmp12256, i64 1
-  %tmp12258 = getelementptr inbounds float* %tmp12257, i64 1
-  %tmp12259 = getelementptr inbounds float* %tmp12258, i64 1
-  %tmp12260 = getelementptr inbounds float* %tmp12259, i64 1
-  %tmp12261 = getelementptr inbounds float* %tmp12260, i64 1
-  %tmp12262 = getelementptr inbounds float* %tmp12261, i64 1
-  %tmp12263 = getelementptr inbounds float* %tmp12262, i64 1
-  %tmp12264 = getelementptr inbounds float* %tmp12263, i64 1
-  %tmp12265 = getelementptr inbounds float* %tmp12264, i64 1
-  %tmp12266 = getelementptr inbounds float* %tmp12265, i64 1
-  %tmp12267 = getelementptr inbounds float* %tmp12266, i64 1
-  %tmp12268 = getelementptr inbounds float* %tmp12267, i64 1
-  %tmp12269 = getelementptr inbounds float* %tmp12268, i64 1
-  %tmp12270 = getelementptr inbounds float* %tmp12269, i64 1
-  %tmp12271 = getelementptr inbounds float* %tmp12270, i64 1
-  %tmp12272 = getelementptr inbounds float* %tmp12271, i64 1
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-  %tmp12275 = getelementptr inbounds float* %tmp12274, i64 1
-  %tmp12276 = getelementptr inbounds float* %tmp12275, i64 1
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-  %tmp12283 = getelementptr inbounds float* %tmp12282, i64 1
-  %tmp12284 = getelementptr inbounds float* %tmp12283, i64 1
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-  %tmp12286 = getelementptr inbounds float* %tmp12285, i64 1
-  %tmp12287 = getelementptr inbounds float* %tmp12286, i64 1
-  %tmp12288 = getelementptr inbounds float* %tmp12287, i64 1
-  %tmp12289 = getelementptr inbounds float* %tmp12288, i64 1
-  %tmp12290 = getelementptr inbounds float* %tmp12289, i64 1
-  %tmp12291 = getelementptr inbounds float* %tmp12290, i64 1
-  %tmp12292 = getelementptr inbounds float* %tmp12291, i64 1
-  %tmp12293 = getelementptr inbounds float* %tmp12292, i64 1
-  %tmp12294 = getelementptr inbounds float* %tmp12293, i64 1
-  %tmp12295 = getelementptr inbounds float* %tmp12294, i64 1
-  %tmp12296 = getelementptr inbounds float* %tmp12295, i64 1
-  %tmp12297 = getelementptr inbounds float* %tmp12296, i64 1
-  %tmp12298 = getelementptr inbounds float* %tmp12297, i64 1
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-  %tmp12303 = getelementptr inbounds float* %tmp12302, i64 1
-  %tmp12304 = getelementptr inbounds float* %tmp12303, i64 1
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-  %tmp12308 = getelementptr inbounds float* %tmp12307, i64 1
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-  %tmp12317 = getelementptr inbounds float* %tmp12316, i64 1
-  %tmp12318 = getelementptr inbounds float* %tmp12317, i64 1
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-  %tmp12320 = getelementptr inbounds float* %tmp12319, i64 1
-  %tmp12321 = getelementptr inbounds float* %tmp12320, i64 1
-  %tmp12322 = getelementptr inbounds float* %tmp12321, i64 1
-  %tmp12323 = getelementptr inbounds float* %tmp12322, i64 1
-  %tmp12324 = getelementptr inbounds float* %tmp12323, i64 1
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-  %tmp12337 = getelementptr inbounds float* %tmp12336, i64 1
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-  %tmp12343 = getelementptr inbounds float* %tmp12342, i64 1
-  %tmp12344 = getelementptr inbounds float* %tmp12343, i64 1
-  %tmp12345 = getelementptr inbounds float* %tmp12344, i64 1
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-  %tmp12348 = getelementptr inbounds float* %tmp12347, i64 1
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-  %tmp12352 = getelementptr inbounds float* %tmp12351, i64 1
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-  %tmp12354 = getelementptr inbounds float* %tmp12353, i64 1
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-  %tmp12356 = getelementptr inbounds float* %tmp12355, i64 1
-  %tmp12357 = getelementptr inbounds float* %tmp12356, i64 1
-  %tmp12358 = getelementptr inbounds float* %tmp12357, i64 1
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-  %tmp12363 = getelementptr inbounds float* %tmp12362, i64 1
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-  %tmp12378 = getelementptr inbounds float* %tmp12377, i64 1
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-  %tmp12383 = getelementptr inbounds float* %tmp12382, i64 1
-  %tmp12384 = getelementptr inbounds float* %tmp12383, i64 1
-  %tmp12385 = getelementptr inbounds float* %tmp12384, i64 1
-  %tmp12386 = getelementptr inbounds float* %tmp12385, i64 1
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-  %tmp12388 = getelementptr inbounds float* %tmp12387, i64 1
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-  %tmp12390 = getelementptr inbounds float* %tmp12389, i64 1
-  %tmp12391 = getelementptr inbounds float* %tmp12390, i64 1
-  %tmp12392 = getelementptr inbounds float* %tmp12391, i64 1
-  %tmp12393 = getelementptr inbounds float* %tmp12392, i64 1
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-  %tmp12610 = getelementptr inbounds float* %tmp12609, i64 1
-  %tmp12611 = getelementptr inbounds float* %tmp12610, i64 1
-  %tmp12612 = getelementptr inbounds float* %tmp12611, i64 1
-  %tmp12613 = getelementptr inbounds float* %tmp12612, i64 1
-  %tmp12614 = getelementptr inbounds float* %tmp12613, i64 1
-  %tmp12615 = getelementptr inbounds float* %tmp12614, i64 1
-  %tmp12616 = getelementptr inbounds float* %tmp12615, i64 1
-  %tmp12617 = getelementptr inbounds float* %tmp12616, i64 1
-  %tmp12618 = getelementptr inbounds float* %tmp12617, i64 1
-  %tmp12619 = getelementptr inbounds float* %tmp12618, i64 1
-  %tmp12620 = getelementptr inbounds float* %tmp12619, i64 1
-  %tmp12621 = getelementptr inbounds float* %tmp12620, i64 1
-  %tmp12622 = getelementptr inbounds float* %tmp12621, i64 1
-  %tmp12623 = getelementptr inbounds float* %tmp12622, i64 1
-  %tmp12624 = getelementptr inbounds float* %tmp12623, i64 1
-  %tmp12625 = getelementptr inbounds float* %tmp12624, i64 1
-  %tmp12626 = getelementptr inbounds float* %tmp12625, i64 1
-  %tmp12627 = getelementptr inbounds float* %tmp12626, i64 1
-  %tmp12628 = getelementptr inbounds float* %tmp12627, i64 1
-  %tmp12629 = getelementptr inbounds float* %tmp12628, i64 1
-  %tmp12630 = getelementptr inbounds float* %tmp12629, i64 1
-  %tmp12631 = getelementptr inbounds float* %tmp12630, i64 1
-  %tmp12632 = getelementptr inbounds float* %tmp12631, i64 1
-  %tmp12633 = getelementptr inbounds float* %tmp12632, i64 1
-  %tmp12634 = getelementptr inbounds float* %tmp12633, i64 1
-  %tmp12635 = getelementptr inbounds float* %tmp12634, i64 1
-  %tmp12636 = getelementptr inbounds float* %tmp12635, i64 1
-  %tmp12637 = getelementptr inbounds float* %tmp12636, i64 1
-  %tmp12638 = getelementptr inbounds float* %tmp12637, i64 1
-  %tmp12639 = getelementptr inbounds float* %tmp12638, i64 1
-  %tmp12640 = getelementptr inbounds float* %tmp12639, i64 1
-  %tmp12641 = getelementptr inbounds float* %tmp12640, i64 1
-  %tmp12642 = getelementptr inbounds float* %tmp12641, i64 1
-  %tmp12643 = getelementptr inbounds float* %tmp12642, i64 1
-  %tmp12644 = getelementptr inbounds float* %tmp12643, i64 1
-  %tmp12645 = getelementptr inbounds float* %tmp12644, i64 1
-  %tmp12646 = getelementptr inbounds float* %tmp12645, i64 1
-  %tmp12647 = getelementptr inbounds float* %tmp12646, i64 1
-  %tmp12648 = getelementptr inbounds float* %tmp12647, i64 1
-  %tmp12649 = getelementptr inbounds float* %tmp12648, i64 1
-  %tmp12650 = getelementptr inbounds float* %tmp12649, i64 1
-  %tmp12651 = getelementptr inbounds float* %tmp12650, i64 1
-  %tmp12652 = getelementptr inbounds float* %tmp12651, i64 1
-  %tmp12653 = getelementptr inbounds float* %tmp12652, i64 1
-  %tmp12654 = getelementptr inbounds float* %tmp12653, i64 1
-  %tmp12655 = getelementptr inbounds float* %tmp12654, i64 1
-  %tmp12656 = getelementptr inbounds float* %tmp12655, i64 1
-  %tmp12657 = getelementptr inbounds float* %tmp12656, i64 1
-  %tmp12658 = getelementptr inbounds float* %tmp12657, i64 1
-  %tmp12659 = getelementptr inbounds float* %tmp12658, i64 1
-  %tmp12660 = getelementptr inbounds float* %tmp12659, i64 1
-  %tmp12661 = getelementptr inbounds float* %tmp12660, i64 1
-  %tmp12662 = getelementptr inbounds float* %tmp12661, i64 1
-  %tmp12663 = getelementptr inbounds float* %tmp12662, i64 1
-  %tmp12664 = getelementptr inbounds float* %tmp12663, i64 1
-  %tmp12665 = getelementptr inbounds float* %tmp12664, i64 1
-  %tmp12666 = getelementptr inbounds float* %tmp12665, i64 1
-  %tmp12667 = getelementptr inbounds float* %tmp12666, i64 1
-  %tmp12668 = getelementptr inbounds float* %tmp12667, i64 1
-  %tmp12669 = getelementptr inbounds float* %tmp12668, i64 1
-  %tmp12670 = getelementptr inbounds float* %tmp12669, i64 1
-  %tmp12671 = getelementptr inbounds float* %tmp12670, i64 1
-  %tmp12672 = getelementptr inbounds float* %tmp12671, i64 1
-  %tmp12673 = getelementptr inbounds float* %tmp12672, i64 1
-  %tmp12674 = getelementptr inbounds float* %tmp12673, i64 1
-  %tmp12675 = getelementptr inbounds float* %tmp12674, i64 1
-  %tmp12676 = getelementptr inbounds float* %tmp12675, i64 1
-  %tmp12677 = getelementptr inbounds float* %tmp12676, i64 1
-  %tmp12678 = getelementptr inbounds float* %tmp12677, i64 1
-  %tmp12679 = getelementptr inbounds float* %tmp12678, i64 1
-  %tmp12680 = getelementptr inbounds float* %tmp12679, i64 1
-  %tmp12681 = getelementptr inbounds float* %tmp12680, i64 1
-  %tmp12682 = getelementptr inbounds float* %tmp12681, i64 1
-  %tmp12683 = getelementptr inbounds float* %tmp12682, i64 1
-  %tmp12684 = getelementptr inbounds float* %tmp12683, i64 1
-  %tmp12685 = getelementptr inbounds float* %tmp12684, i64 1
-  %tmp12686 = getelementptr inbounds float* %tmp12685, i64 1
-  %tmp12687 = getelementptr inbounds float* %tmp12686, i64 1
-  %tmp12688 = getelementptr inbounds float* %tmp12687, i64 1
-  %tmp12689 = getelementptr inbounds float* %tmp12688, i64 1
-  %tmp12690 = getelementptr inbounds float* %tmp12689, i64 1
-  %tmp12691 = getelementptr inbounds float* %tmp12690, i64 1
-  %tmp12692 = getelementptr inbounds float* %tmp12691, i64 1
-  %tmp12693 = getelementptr inbounds float* %tmp12692, i64 1
-  %tmp12694 = getelementptr inbounds float* %tmp12693, i64 1
-  %tmp12695 = getelementptr inbounds float* %tmp12694, i64 1
-  %tmp12696 = getelementptr inbounds float* %tmp12695, i64 1
-  %tmp12697 = getelementptr inbounds float* %tmp12696, i64 1
-  %tmp12698 = getelementptr inbounds float* %tmp12697, i64 1
-  %tmp12699 = getelementptr inbounds float* %tmp12698, i64 1
-  %tmp12700 = getelementptr inbounds float* %tmp12699, i64 1
-  %tmp12701 = getelementptr inbounds float* %tmp12700, i64 1
-  %tmp12702 = getelementptr inbounds float* %tmp12701, i64 1
-  %tmp12703 = getelementptr inbounds float* %tmp12702, i64 1
-  %tmp12704 = getelementptr inbounds float* %tmp12703, i64 1
-  %tmp12705 = getelementptr inbounds float* %tmp12704, i64 1
-  %tmp12706 = getelementptr inbounds float* %tmp12705, i64 1
-  %tmp12707 = getelementptr inbounds float* %tmp12706, i64 1
-  %tmp12708 = getelementptr inbounds float* %tmp12707, i64 1
-  %tmp12709 = getelementptr inbounds float* %tmp12708, i64 1
-  %tmp12710 = getelementptr inbounds float* %tmp12709, i64 1
-  %tmp12711 = getelementptr inbounds float* %tmp12710, i64 1
-  %tmp12712 = getelementptr inbounds float* %tmp12711, i64 1
-  %tmp12713 = getelementptr inbounds float* %tmp12712, i64 1
-  %tmp12714 = getelementptr inbounds float* %tmp12713, i64 1
-  %tmp12715 = getelementptr inbounds float* %tmp12714, i64 1
-  %tmp12716 = getelementptr inbounds float* %tmp12715, i64 1
-  %tmp12717 = getelementptr inbounds float* %tmp12716, i64 1
-  %tmp12718 = getelementptr inbounds float* %tmp12717, i64 1
-  %tmp12719 = getelementptr inbounds float* %tmp12718, i64 1
-  %tmp12720 = getelementptr inbounds float* %tmp12719, i64 1
-  %tmp12721 = getelementptr inbounds float* %tmp12720, i64 1
-  %tmp12722 = getelementptr inbounds float* %tmp12721, i64 1
-  %tmp12723 = getelementptr inbounds float* %tmp12722, i64 1
-  %tmp12724 = getelementptr inbounds float* %tmp12723, i64 1
-  %tmp12725 = getelementptr inbounds float* %tmp12724, i64 1
-  %tmp12726 = getelementptr inbounds float* %tmp12725, i64 1
-  %tmp12727 = getelementptr inbounds float* %tmp12726, i64 1
-  %tmp12728 = getelementptr inbounds float* %tmp12727, i64 1
-  %tmp12729 = getelementptr inbounds float* %tmp12728, i64 1
-  %tmp12730 = getelementptr inbounds float* %tmp12729, i64 1
-  %tmp12731 = getelementptr inbounds float* %tmp12730, i64 1
-  %tmp12732 = getelementptr inbounds float* %tmp12731, i64 1
-  %tmp12733 = getelementptr inbounds float* %tmp12732, i64 1
-  %tmp12734 = getelementptr inbounds float* %tmp12733, i64 1
-  %tmp12735 = getelementptr inbounds float* %tmp12734, i64 1
-  %tmp12736 = getelementptr inbounds float* %tmp12735, i64 1
-  %tmp12737 = getelementptr inbounds float* %tmp12736, i64 1
-  %tmp12738 = getelementptr inbounds float* %tmp12737, i64 1
-  %tmp12739 = getelementptr inbounds float* %tmp12738, i64 1
-  %tmp12740 = getelementptr inbounds float* %tmp12739, i64 1
-  %tmp12741 = getelementptr inbounds float* %tmp12740, i64 1
-  %tmp12742 = getelementptr inbounds float* %tmp12741, i64 1
-  %tmp12743 = getelementptr inbounds float* %tmp12742, i64 1
-  %tmp12744 = getelementptr inbounds float* %tmp12743, i64 1
-  %tmp12745 = getelementptr inbounds float* %tmp12744, i64 1
-  %tmp12746 = getelementptr inbounds float* %tmp12745, i64 1
-  %tmp12747 = getelementptr inbounds float* %tmp12746, i64 1
-  %tmp12748 = getelementptr inbounds float* %tmp12747, i64 1
-  %tmp12749 = getelementptr inbounds float* %tmp12748, i64 1
-  %tmp12750 = getelementptr inbounds float* %tmp12749, i64 1
-  %tmp12751 = getelementptr inbounds float* %tmp12750, i64 1
-  %tmp12752 = getelementptr inbounds float* %tmp12751, i64 1
-  %tmp12753 = getelementptr inbounds float* %tmp12752, i64 1
-  %tmp12754 = getelementptr inbounds float* %tmp12753, i64 1
-  %tmp12755 = getelementptr inbounds float* %tmp12754, i64 1
-  %tmp12756 = getelementptr inbounds float* %tmp12755, i64 1
-  %tmp12757 = getelementptr inbounds float* %tmp12756, i64 1
-  %tmp12758 = getelementptr inbounds float* %tmp12757, i64 1
-  %tmp12759 = getelementptr inbounds float* %tmp12758, i64 1
-  %tmp12760 = getelementptr inbounds float* %tmp12759, i64 1
-  %tmp12761 = getelementptr inbounds float* %tmp12760, i64 1
-  %tmp12762 = getelementptr inbounds float* %tmp12761, i64 1
-  %tmp12763 = getelementptr inbounds float* %tmp12762, i64 1
-  %tmp12764 = getelementptr inbounds float* %tmp12763, i64 1
-  %tmp12765 = getelementptr inbounds float* %tmp12764, i64 1
-  %tmp12766 = getelementptr inbounds float* %tmp12765, i64 1
-  %tmp12767 = getelementptr inbounds float* %tmp12766, i64 1
-  %tmp12768 = getelementptr inbounds float* %tmp12767, i64 1
-  %tmp12769 = getelementptr inbounds float* %tmp12768, i64 1
-  %tmp12770 = getelementptr inbounds float* %tmp12769, i64 1
-  %tmp12771 = getelementptr inbounds float* %tmp12770, i64 1
-  %tmp12772 = getelementptr inbounds float* %tmp12771, i64 1
-  %tmp12773 = getelementptr inbounds float* %tmp12772, i64 1
-  %tmp12774 = getelementptr inbounds float* %tmp12773, i64 1
-  %tmp12775 = getelementptr inbounds float* %tmp12774, i64 1
-  %tmp12776 = getelementptr inbounds float* %tmp12775, i64 1
-  %tmp12777 = getelementptr inbounds float* %tmp12776, i64 1
-  %tmp12778 = getelementptr inbounds float* %tmp12777, i64 1
-  %tmp12779 = getelementptr inbounds float* %tmp12778, i64 1
-  %tmp12780 = getelementptr inbounds float* %tmp12779, i64 1
-  %tmp12781 = getelementptr inbounds float* %tmp12780, i64 1
-  %tmp12782 = getelementptr inbounds float* %tmp12781, i64 1
-  %tmp12783 = getelementptr inbounds float* %tmp12782, i64 1
-  %tmp12784 = getelementptr inbounds float* %tmp12783, i64 1
-  %tmp12785 = getelementptr inbounds float* %tmp12784, i64 1
-  %tmp12786 = getelementptr inbounds float* %tmp12785, i64 1
-  %tmp12787 = getelementptr inbounds float* %tmp12786, i64 1
-  %tmp12788 = getelementptr inbounds float* %tmp12787, i64 1
-  %tmp12789 = getelementptr inbounds float* %tmp12788, i64 1
-  %tmp12790 = getelementptr inbounds float* %tmp12789, i64 1
-  %tmp12791 = getelementptr inbounds float* %tmp12790, i64 1
-  %tmp12792 = getelementptr inbounds float* %tmp12791, i64 1
-  %tmp12793 = getelementptr inbounds float* %tmp12792, i64 1
-  %tmp12794 = getelementptr inbounds float* %tmp12793, i64 1
-  %tmp12795 = getelementptr inbounds float* %tmp12794, i64 1
-  %tmp12796 = getelementptr inbounds float* %tmp12795, i64 1
-  %tmp12797 = getelementptr inbounds float* %tmp12796, i64 1
-  %tmp12798 = getelementptr inbounds float* %tmp12797, i64 1
-  %tmp12799 = getelementptr inbounds float* %tmp12798, i64 1
-  %tmp12800 = getelementptr inbounds float* %tmp12799, i64 1
-  %tmp12801 = getelementptr inbounds float* %tmp12800, i64 1
-  %tmp12802 = getelementptr inbounds float* %tmp12801, i64 1
-  %tmp12803 = getelementptr inbounds float* %tmp12802, i64 1
-  %tmp12804 = getelementptr inbounds float* %tmp12803, i64 1
-  %tmp12805 = getelementptr inbounds float* %tmp12804, i64 1
-  %tmp12806 = getelementptr inbounds float* %tmp12805, i64 1
-  %tmp12807 = getelementptr inbounds float* %tmp12806, i64 1
-  %tmp12808 = getelementptr inbounds float* %tmp12807, i64 1
-  %tmp12809 = getelementptr inbounds float* %tmp12808, i64 1
-  %tmp12810 = getelementptr inbounds float* %tmp12809, i64 1
-  %tmp12811 = getelementptr inbounds float* %tmp12810, i64 1
-  %tmp12812 = getelementptr inbounds float* %tmp12811, i64 1
-  %tmp12813 = getelementptr inbounds float* %tmp12812, i64 1
-  %tmp12814 = getelementptr inbounds float* %tmp12813, i64 1
-  %tmp12815 = getelementptr inbounds float* %tmp12814, i64 1
-  %tmp12816 = getelementptr inbounds float* %tmp12815, i64 1
-  %tmp12817 = getelementptr inbounds float* %tmp12816, i64 1
-  %tmp12818 = getelementptr inbounds float* %tmp12817, i64 1
-  %tmp12819 = getelementptr inbounds float* %tmp12818, i64 1
-  %tmp12820 = getelementptr inbounds float* %tmp12819, i64 1
-  %tmp12821 = getelementptr inbounds float* %tmp12820, i64 1
-  %tmp12822 = getelementptr inbounds float* %tmp12821, i64 1
-  %tmp12823 = getelementptr inbounds float* %tmp12822, i64 1
-  %tmp12824 = getelementptr inbounds float* %tmp12823, i64 1
-  %tmp12825 = getelementptr inbounds float* %tmp12824, i64 1
-  %tmp12826 = getelementptr inbounds float* %tmp12825, i64 1
-  %tmp12827 = getelementptr inbounds float* %tmp12826, i64 1
-  %tmp12828 = getelementptr inbounds float* %tmp12827, i64 1
-  %tmp12829 = getelementptr inbounds float* %tmp12828, i64 1
-  %tmp12830 = getelementptr inbounds float* %tmp12829, i64 1
-  %tmp12831 = getelementptr inbounds float* %tmp12830, i64 1
-  %tmp12832 = getelementptr inbounds float* %tmp12831, i64 1
-  %tmp12833 = getelementptr inbounds float* %tmp12832, i64 1
-  %tmp12834 = getelementptr inbounds float* %tmp12833, i64 1
-  %tmp12835 = getelementptr inbounds float* %tmp12834, i64 1
-  %tmp12836 = getelementptr inbounds float* %tmp12835, i64 1
-  %tmp12837 = getelementptr inbounds float* %tmp12836, i64 1
-  %tmp12838 = getelementptr inbounds float* %tmp12837, i64 1
-  %tmp12839 = getelementptr inbounds float* %tmp12838, i64 1
-  %tmp12840 = getelementptr inbounds float* %tmp12839, i64 1
-  %tmp12841 = getelementptr inbounds float* %tmp12840, i64 1
-  %tmp12842 = getelementptr inbounds float* %tmp12841, i64 1
-  %tmp12843 = getelementptr inbounds float* %tmp12842, i64 1
-  %tmp12844 = getelementptr inbounds float* %tmp12843, i64 1
-  %tmp12845 = getelementptr inbounds float* %tmp12844, i64 1
-  %tmp12846 = getelementptr inbounds float* %tmp12845, i64 1
-  %tmp12847 = getelementptr inbounds float* %tmp12846, i64 1
-  %tmp12848 = getelementptr inbounds float* %tmp12847, i64 1
-  %tmp12849 = getelementptr inbounds float* %tmp12848, i64 1
-  %tmp12850 = getelementptr inbounds float* %tmp12849, i64 1
-  %tmp12851 = getelementptr inbounds float* %tmp12850, i64 1
-  %tmp12852 = getelementptr inbounds float* %tmp12851, i64 1
-  %tmp12853 = getelementptr inbounds float* %tmp12852, i64 1
-  %tmp12854 = getelementptr inbounds float* %tmp12853, i64 1
-  %tmp12855 = getelementptr inbounds float* %tmp12854, i64 1
-  %tmp12856 = getelementptr inbounds float* %tmp12855, i64 1
-  %tmp12857 = getelementptr inbounds float* %tmp12856, i64 1
-  %tmp12858 = getelementptr inbounds float* %tmp12857, i64 1
-  %tmp12859 = getelementptr inbounds float* %tmp12858, i64 1
-  %tmp12860 = getelementptr inbounds float* %tmp12859, i64 1
-  %tmp12861 = getelementptr inbounds float* %tmp12860, i64 1
-  %tmp12862 = getelementptr inbounds float* %tmp12861, i64 1
-  %tmp12863 = getelementptr inbounds float* %tmp12862, i64 1
-  %tmp12864 = getelementptr inbounds float* %tmp12863, i64 1
-  %tmp12865 = getelementptr inbounds float* %tmp12864, i64 1
-  %tmp12866 = getelementptr inbounds float* %tmp12865, i64 1
-  %tmp12867 = getelementptr inbounds float* %tmp12866, i64 1
-  %tmp12868 = getelementptr inbounds float* %tmp12867, i64 1
-  %tmp12869 = getelementptr inbounds float* %tmp12868, i64 1
-  %tmp12870 = getelementptr inbounds float* %tmp12869, i64 1
-  %tmp12871 = getelementptr inbounds float* %tmp12870, i64 1
-  %tmp12872 = getelementptr inbounds float* %tmp12871, i64 1
-  %tmp12873 = getelementptr inbounds float* %tmp12872, i64 1
-  %tmp12874 = getelementptr inbounds float* %tmp12873, i64 1
-  %tmp12875 = getelementptr inbounds float* %tmp12874, i64 1
-  %tmp12876 = getelementptr inbounds float* %tmp12875, i64 1
-  %tmp12877 = getelementptr inbounds float* %tmp12876, i64 1
-  %tmp12878 = getelementptr inbounds float* %tmp12877, i64 1
-  %tmp12879 = getelementptr inbounds float* %tmp12878, i64 1
-  %tmp12880 = getelementptr inbounds float* %tmp12879, i64 1
-  %tmp12881 = getelementptr inbounds float* %tmp12880, i64 1
-  %tmp12882 = getelementptr inbounds float* %tmp12881, i64 1
-  %tmp12883 = getelementptr inbounds float* %tmp12882, i64 1
-  %tmp12884 = getelementptr inbounds float* %tmp12883, i64 1
-  %tmp12885 = getelementptr inbounds float* %tmp12884, i64 1
-  %tmp12886 = getelementptr inbounds float* %tmp12885, i64 1
-  %tmp12887 = getelementptr inbounds float* %tmp12886, i64 1
-  %tmp12888 = getelementptr inbounds float* %tmp12887, i64 1
-  %tmp12889 = getelementptr inbounds float* %tmp12888, i64 1
-  %tmp12890 = getelementptr inbounds float* %tmp12889, i64 1
-  %tmp12891 = getelementptr inbounds float* %tmp12890, i64 1
-  %tmp12892 = getelementptr inbounds float* %tmp12891, i64 1
-  %tmp12893 = getelementptr inbounds float* %tmp12892, i64 1
-  %tmp12894 = getelementptr inbounds float* %tmp12893, i64 1
-  %tmp12895 = getelementptr inbounds float* %tmp12894, i64 1
-  %tmp12896 = getelementptr inbounds float* %tmp12895, i64 1
-  %tmp12897 = getelementptr inbounds float* %tmp12896, i64 1
-  %tmp12898 = getelementptr inbounds float* %tmp12897, i64 1
-  %tmp12899 = getelementptr inbounds float* %tmp12898, i64 1
-  %tmp12900 = getelementptr inbounds float* %tmp12899, i64 1
-  %tmp12901 = getelementptr inbounds float* %tmp12900, i64 1
-  %tmp12902 = getelementptr inbounds float* %tmp12901, i64 1
-  %tmp12903 = getelementptr inbounds float* %tmp12902, i64 1
-  %tmp12904 = getelementptr inbounds float* %tmp12903, i64 1
-  %tmp12905 = getelementptr inbounds float* %tmp12904, i64 1
-  %tmp12906 = getelementptr inbounds float* %tmp12905, i64 1
-  %tmp12907 = getelementptr inbounds float* %tmp12906, i64 1
-  %tmp12908 = getelementptr inbounds float* %tmp12907, i64 1
-  %tmp12909 = getelementptr inbounds float* %tmp12908, i64 1
-  %tmp12910 = getelementptr inbounds float* %tmp12909, i64 1
-  %tmp12911 = getelementptr inbounds float* %tmp12910, i64 1
-  %tmp12912 = getelementptr inbounds float* %tmp12911, i64 1
-  %tmp12913 = getelementptr inbounds float* %tmp12912, i64 1
-  %tmp12914 = getelementptr inbounds float* %tmp12913, i64 1
-  %tmp12915 = getelementptr inbounds float* %tmp12914, i64 1
-  %tmp12916 = getelementptr inbounds float* %tmp12915, i64 1
-  %tmp12917 = getelementptr inbounds float* %tmp12916, i64 1
-  %tmp12918 = getelementptr inbounds float* %tmp12917, i64 1
-  %tmp12919 = getelementptr inbounds float* %tmp12918, i64 1
-  %tmp12920 = getelementptr inbounds float* %tmp12919, i64 1
-  %tmp12921 = getelementptr inbounds float* %tmp12920, i64 1
-  %tmp12922 = getelementptr inbounds float* %tmp12921, i64 1
-  %tmp12923 = getelementptr inbounds float* %tmp12922, i64 1
-  %tmp12924 = getelementptr inbounds float* %tmp12923, i64 1
-  %tmp12925 = getelementptr inbounds float* %tmp12924, i64 1
-  %tmp12926 = getelementptr inbounds float* %tmp12925, i64 1
-  %tmp12927 = getelementptr inbounds float* %tmp12926, i64 1
-  %tmp12928 = getelementptr inbounds float* %tmp12927, i64 1
-  %tmp12929 = getelementptr inbounds float* %tmp12928, i64 1
-  %tmp12930 = getelementptr inbounds float* %tmp12929, i64 1
-  %tmp12931 = getelementptr inbounds float* %tmp12930, i64 1
-  %tmp12932 = getelementptr inbounds float* %tmp12931, i64 1
-  %tmp12933 = getelementptr inbounds float* %tmp12932, i64 1
-  %tmp12934 = getelementptr inbounds float* %tmp12933, i64 1
-  %tmp12935 = getelementptr inbounds float* %tmp12934, i64 1
-  %tmp12936 = getelementptr inbounds float* %tmp12935, i64 1
-  %tmp12937 = getelementptr inbounds float* %tmp12936, i64 1
-  %tmp12938 = getelementptr inbounds float* %tmp12937, i64 1
-  %tmp12939 = getelementptr inbounds float* %tmp12938, i64 1
-  %tmp12940 = getelementptr inbounds float* %tmp12939, i64 1
-  %tmp12941 = getelementptr inbounds float* %tmp12940, i64 1
-  %tmp12942 = getelementptr inbounds float* %tmp12941, i64 1
-  %tmp12943 = getelementptr inbounds float* %tmp12942, i64 1
-  %tmp12944 = getelementptr inbounds float* %tmp12943, i64 1
-  %tmp12945 = getelementptr inbounds float* %tmp12944, i64 1
-  %tmp12946 = getelementptr inbounds float* %tmp12945, i64 1
-  %tmp12947 = getelementptr inbounds float* %tmp12946, i64 1
-  %tmp12948 = getelementptr inbounds float* %tmp12947, i64 1
-  %tmp12949 = getelementptr inbounds float* %tmp12948, i64 1
-  %tmp12950 = getelementptr inbounds float* %tmp12949, i64 1
-  %tmp12951 = getelementptr inbounds float* %tmp12950, i64 1
-  %tmp12952 = getelementptr inbounds float* %tmp12951, i64 1
-  %tmp12953 = getelementptr inbounds float* %tmp12952, i64 1
-  %tmp12954 = getelementptr inbounds float* %tmp12953, i64 1
-  %tmp12955 = getelementptr inbounds float* %tmp12954, i64 1
-  %tmp12956 = getelementptr inbounds float* %tmp12955, i64 1
-  %tmp12957 = getelementptr inbounds float* %tmp12956, i64 1
-  %tmp12958 = getelementptr inbounds float* %tmp12957, i64 1
-  %tmp12959 = getelementptr inbounds float* %tmp12958, i64 1
-  %tmp12960 = getelementptr inbounds float* %tmp12959, i64 1
-  %tmp12961 = getelementptr inbounds float* %tmp12960, i64 1
-  %tmp12962 = getelementptr inbounds float* %tmp12961, i64 1
-  %tmp12963 = getelementptr inbounds float* %tmp12962, i64 1
-  %tmp12964 = getelementptr inbounds float* %tmp12963, i64 1
-  %tmp12965 = getelementptr inbounds float* %tmp12964, i64 1
-  %tmp12966 = getelementptr inbounds float* %tmp12965, i64 1
-  %tmp12967 = getelementptr inbounds float* %tmp12966, i64 1
-  %tmp12968 = getelementptr inbounds float* %tmp12967, i64 1
-  %tmp12969 = getelementptr inbounds float* %tmp12968, i64 1
-  %tmp12970 = getelementptr inbounds float* %tmp12969, i64 1
-  %tmp12971 = getelementptr inbounds float* %tmp12970, i64 1
-  %tmp12972 = getelementptr inbounds float* %tmp12971, i64 1
-  %tmp12973 = getelementptr inbounds float* %tmp12972, i64 1
-  %tmp12974 = getelementptr inbounds float* %tmp12973, i64 1
-  %tmp12975 = getelementptr inbounds float* %tmp12974, i64 1
-  %tmp12976 = getelementptr inbounds float* %tmp12975, i64 1
-  %tmp12977 = getelementptr inbounds float* %tmp12976, i64 1
-  %tmp12978 = getelementptr inbounds float* %tmp12977, i64 1
-  %tmp12979 = getelementptr inbounds float* %tmp12978, i64 1
-  %tmp12980 = getelementptr inbounds float* %tmp12979, i64 1
-  %tmp12981 = getelementptr inbounds float* %tmp12980, i64 1
-  %tmp12982 = getelementptr inbounds float* %tmp12981, i64 1
-  %tmp12983 = getelementptr inbounds float* %tmp12982, i64 1
-  %tmp12984 = getelementptr inbounds float* %tmp12983, i64 1
-  %tmp12985 = getelementptr inbounds float* %tmp12984, i64 1
-  %tmp12986 = getelementptr inbounds float* %tmp12985, i64 1
-  %tmp12987 = getelementptr inbounds float* %tmp12986, i64 1
-  %tmp12988 = getelementptr inbounds float* %tmp12987, i64 1
-  %tmp12989 = getelementptr inbounds float* %tmp12988, i64 1
-  %tmp12990 = getelementptr inbounds float* %tmp12989, i64 1
-  %tmp12991 = getelementptr inbounds float* %tmp12990, i64 1
-  %tmp12992 = getelementptr inbounds float* %tmp12991, i64 1
-  %tmp12993 = getelementptr inbounds float* %tmp12992, i64 1
-  %tmp12994 = getelementptr inbounds float* %tmp12993, i64 1
-  %tmp12995 = getelementptr inbounds float* %tmp12994, i64 1
-  %tmp12996 = getelementptr inbounds float* %tmp12995, i64 1
-  %tmp12997 = getelementptr inbounds float* %tmp12996, i64 1
-  %tmp12998 = getelementptr inbounds float* %tmp12997, i64 1
-  %tmp12999 = getelementptr inbounds float* %tmp12998, i64 1
-  %tmp13000 = getelementptr inbounds float* %tmp12999, i64 1
-  %tmp13001 = getelementptr inbounds float* %tmp13000, i64 1
-  %tmp13002 = getelementptr inbounds float* %tmp13001, i64 1
-  %tmp13003 = getelementptr inbounds float* %tmp13002, i64 1
-  %tmp13004 = getelementptr inbounds float* %tmp13003, i64 1
-  %tmp13005 = getelementptr inbounds float* %tmp13004, i64 1
-  %tmp13006 = getelementptr inbounds float* %tmp13005, i64 1
-  %tmp13007 = getelementptr inbounds float* %tmp13006, i64 1
-  %tmp13008 = getelementptr inbounds float* %tmp13007, i64 1
-  %tmp13009 = getelementptr inbounds float* %tmp13008, i64 1
-  %tmp13010 = getelementptr inbounds float* %tmp13009, i64 1
-  %tmp13011 = getelementptr inbounds float* %tmp13010, i64 1
-  %tmp13012 = getelementptr inbounds float* %tmp13011, i64 1
-  %tmp13013 = getelementptr inbounds float* %tmp13012, i64 1
-  %tmp13014 = getelementptr inbounds float* %tmp13013, i64 1
-  %tmp13015 = getelementptr inbounds float* %tmp13014, i64 1
-  %tmp13016 = getelementptr inbounds float* %tmp13015, i64 1
-  %tmp13017 = getelementptr inbounds float* %tmp13016, i64 1
-  %tmp13018 = getelementptr inbounds float* %tmp13017, i64 1
-  %tmp13019 = getelementptr inbounds float* %tmp13018, i64 1
-  %tmp13020 = getelementptr inbounds float* %tmp13019, i64 1
-  %tmp13021 = getelementptr inbounds float* %tmp13020, i64 1
-  %tmp13022 = getelementptr inbounds float* %tmp13021, i64 1
-  %tmp13023 = getelementptr inbounds float* %tmp13022, i64 1
-  %tmp13024 = getelementptr inbounds float* %tmp13023, i64 1
-  %tmp13025 = getelementptr inbounds float* %tmp13024, i64 1
-  %tmp13026 = getelementptr inbounds float* %tmp13025, i64 1
-  %tmp13027 = getelementptr inbounds float* %tmp13026, i64 1
-  %tmp13028 = getelementptr inbounds float* %tmp13027, i64 1
-  %tmp13029 = getelementptr inbounds float* %tmp13028, i64 1
-  %tmp13030 = getelementptr inbounds float* %tmp13029, i64 1
-  %tmp13031 = getelementptr inbounds float* %tmp13030, i64 1
-  %tmp13032 = getelementptr inbounds float* %tmp13031, i64 1
-  %tmp13033 = getelementptr inbounds float* %tmp13032, i64 1
-  %tmp13034 = getelementptr inbounds float* %tmp13033, i64 1
-  %tmp13035 = getelementptr inbounds float* %tmp13034, i64 1
-  %tmp13036 = getelementptr inbounds float* %tmp13035, i64 1
-  %tmp13037 = getelementptr inbounds float* %tmp13036, i64 1
-  %tmp13038 = getelementptr inbounds float* %tmp13037, i64 1
-  %tmp13039 = getelementptr inbounds float* %tmp13038, i64 1
-  %tmp13040 = getelementptr inbounds float* %tmp13039, i64 1
-  %tmp13041 = getelementptr inbounds float* %tmp13040, i64 1
-  %tmp13042 = getelementptr inbounds float* %tmp13041, i64 1
-  %tmp13043 = getelementptr inbounds float* %tmp13042, i64 1
-  %tmp13044 = getelementptr inbounds float* %tmp13043, i64 1
-  %tmp13045 = getelementptr inbounds float* %tmp13044, i64 1
-  %tmp13046 = getelementptr inbounds float* %tmp13045, i64 1
-  %tmp13047 = getelementptr inbounds float* %tmp13046, i64 1
-  %tmp13048 = getelementptr inbounds float* %tmp13047, i64 1
-  %tmp13049 = getelementptr inbounds float* %tmp13048, i64 1
-  %tmp13050 = getelementptr inbounds float* %tmp13049, i64 1
-  %tmp13051 = getelementptr inbounds float* %tmp13050, i64 1
-  %tmp13052 = getelementptr inbounds float* %tmp13051, i64 1
-  %tmp13053 = getelementptr inbounds float* %tmp13052, i64 1
-  %tmp13054 = getelementptr inbounds float* %tmp13053, i64 1
-  %tmp13055 = getelementptr inbounds float* %tmp13054, i64 1
-  %tmp13056 = getelementptr inbounds float* %tmp13055, i64 1
-  %tmp13057 = getelementptr inbounds float* %tmp13056, i64 1
-  %tmp13058 = getelementptr inbounds float* %tmp13057, i64 1
-  %tmp13059 = getelementptr inbounds float* %tmp13058, i64 1
-  %tmp13060 = getelementptr inbounds float* %tmp13059, i64 1
-  %tmp13061 = getelementptr inbounds float* %tmp13060, i64 1
-  %tmp13062 = getelementptr inbounds float* %tmp13061, i64 1
-  %tmp13063 = getelementptr inbounds float* %tmp13062, i64 1
-  %tmp13064 = getelementptr inbounds float* %tmp13063, i64 1
-  %tmp13065 = getelementptr inbounds float* %tmp13064, i64 1
-  %tmp13066 = getelementptr inbounds float* %tmp13065, i64 1
-  %tmp13067 = getelementptr inbounds float* %tmp13066, i64 1
-  %tmp13068 = getelementptr inbounds float* %tmp13067, i64 1
-  %tmp13069 = getelementptr inbounds float* %tmp13068, i64 1
-  %tmp13070 = getelementptr inbounds float* %tmp13069, i64 1
-  %tmp13071 = getelementptr inbounds float* %tmp13070, i64 1
-  %tmp13072 = getelementptr inbounds float* %tmp13071, i64 1
-  %tmp13073 = getelementptr inbounds float* %tmp13072, i64 1
-  %tmp13074 = getelementptr inbounds float* %tmp13073, i64 1
-  %tmp13075 = getelementptr inbounds float* %tmp13074, i64 1
-  %tmp13076 = getelementptr inbounds float* %tmp13075, i64 1
-  %tmp13077 = getelementptr inbounds float* %tmp13076, i64 1
-  %tmp13078 = getelementptr inbounds float* %tmp13077, i64 1
-  %tmp13079 = getelementptr inbounds float* %tmp13078, i64 1
-  %tmp13080 = getelementptr inbounds float* %tmp13079, i64 1
-  %tmp13081 = getelementptr inbounds float* %tmp13080, i64 1
-  %tmp13082 = getelementptr inbounds float* %tmp13081, i64 1
-  %tmp13083 = getelementptr inbounds float* %tmp13082, i64 1
-  %tmp13084 = getelementptr inbounds float* %tmp13083, i64 1
-  %tmp13085 = getelementptr inbounds float* %tmp13084, i64 1
-  %tmp13086 = getelementptr inbounds float* %tmp13085, i64 1
-  %tmp13087 = getelementptr inbounds float* %tmp13086, i64 1
-  %tmp13088 = getelementptr inbounds float* %tmp13087, i64 1
-  %tmp13089 = getelementptr inbounds float* %tmp13088, i64 1
-  %tmp13090 = getelementptr inbounds float* %tmp13089, i64 1
-  %tmp13091 = getelementptr inbounds float* %tmp13090, i64 1
-  %tmp13092 = getelementptr inbounds float* %tmp13091, i64 1
-  %tmp13093 = getelementptr inbounds float* %tmp13092, i64 1
-  %tmp13094 = getelementptr inbounds float* %tmp13093, i64 1
-  %tmp13095 = getelementptr inbounds float* %tmp13094, i64 1
-  %tmp13096 = getelementptr inbounds float* %tmp13095, i64 1
-  %tmp13097 = getelementptr inbounds float* %tmp13096, i64 1
-  %tmp13098 = getelementptr inbounds float* %tmp13097, i64 1
-  %tmp13099 = getelementptr inbounds float* %tmp13098, i64 1
-  %tmp13100 = getelementptr inbounds float* %tmp13099, i64 1
-  %tmp13101 = getelementptr inbounds float* %tmp13100, i64 1
-  %tmp13102 = getelementptr inbounds float* %tmp13101, i64 1
-  %tmp13103 = getelementptr inbounds float* %tmp13102, i64 1
-  %tmp13104 = getelementptr inbounds float* %tmp13103, i64 1
-  %tmp13105 = getelementptr inbounds float* %tmp13104, i64 1
-  %tmp13106 = getelementptr inbounds float* %tmp13105, i64 1
-  %tmp13107 = getelementptr inbounds float* %tmp13106, i64 1
-  %tmp13108 = getelementptr inbounds float* %tmp13107, i64 1
-  %tmp13109 = getelementptr inbounds float* %tmp13108, i64 1
-  %tmp13110 = getelementptr inbounds float* %tmp13109, i64 1
-  %tmp13111 = getelementptr inbounds float* %tmp13110, i64 1
-  %tmp13112 = getelementptr inbounds float* %tmp13111, i64 1
-  %tmp13113 = getelementptr inbounds float* %tmp13112, i64 1
-  %tmp13114 = getelementptr inbounds float* %tmp13113, i64 1
-  %tmp13115 = getelementptr inbounds float* %tmp13114, i64 1
-  %tmp13116 = getelementptr inbounds float* %tmp13115, i64 1
-  %tmp13117 = getelementptr inbounds float* %tmp13116, i64 1
-  %tmp13118 = getelementptr inbounds float* %tmp13117, i64 1
-  %tmp13119 = getelementptr inbounds float* %tmp13118, i64 1
-  %tmp13120 = getelementptr inbounds float* %tmp13119, i64 1
-  %tmp13121 = getelementptr inbounds float* %tmp13120, i64 1
-  %tmp13122 = getelementptr inbounds float* %tmp13121, i64 1
-  %tmp13123 = getelementptr inbounds float* %tmp13122, i64 1
-  %tmp13124 = getelementptr inbounds float* %tmp13123, i64 1
-  %tmp13125 = getelementptr inbounds float* %tmp13124, i64 1
-  %tmp13126 = getelementptr inbounds float* %tmp13125, i64 1
-  %tmp13127 = getelementptr inbounds float* %tmp13126, i64 1
-  %tmp13128 = getelementptr inbounds float* %tmp13127, i64 1
-  %tmp13129 = getelementptr inbounds float* %tmp13128, i64 1
-  %tmp13130 = getelementptr inbounds float* %tmp13129, i64 1
-  %tmp13131 = getelementptr inbounds float* %tmp13130, i64 1
-  %tmp13132 = getelementptr inbounds float* %tmp13131, i64 1
-  %tmp13133 = getelementptr inbounds float* %tmp13132, i64 1
-  %tmp13134 = getelementptr inbounds float* %tmp13133, i64 1
-  %tmp13135 = getelementptr inbounds float* %tmp13134, i64 1
-  %tmp13136 = getelementptr inbounds float* %tmp13135, i64 1
-  %tmp13137 = getelementptr inbounds float* %tmp13136, i64 1
-  %tmp13138 = getelementptr inbounds float* %tmp13137, i64 1
-  %tmp13139 = getelementptr inbounds float* %tmp13138, i64 1
-  %tmp13140 = getelementptr inbounds float* %tmp13139, i64 1
-  %tmp13141 = getelementptr inbounds float* %tmp13140, i64 1
-  %tmp13142 = getelementptr inbounds float* %tmp13141, i64 1
-  %tmp13143 = getelementptr inbounds float* %tmp13142, i64 1
-  %tmp13144 = getelementptr inbounds float* %tmp13143, i64 1
-  %tmp13145 = getelementptr inbounds float* %tmp13144, i64 1
-  %tmp13146 = getelementptr inbounds float* %tmp13145, i64 1
-  %tmp13147 = getelementptr inbounds float* %tmp13146, i64 1
-  %tmp13148 = getelementptr inbounds float* %tmp13147, i64 1
-  %tmp13149 = getelementptr inbounds float* %tmp13148, i64 1
-  %tmp13150 = getelementptr inbounds float* %tmp13149, i64 1
-  %tmp13151 = getelementptr inbounds float* %tmp13150, i64 1
-  %tmp13152 = getelementptr inbounds float* %tmp13151, i64 1
-  %tmp13153 = getelementptr inbounds float* %tmp13152, i64 1
-  %tmp13154 = getelementptr inbounds float* %tmp13153, i64 1
-  %tmp13155 = getelementptr inbounds float* %tmp13154, i64 1
-  %tmp13156 = getelementptr inbounds float* %tmp13155, i64 1
-  %tmp13157 = getelementptr inbounds float* %tmp13156, i64 1
-  %tmp13158 = getelementptr inbounds float* %tmp13157, i64 1
-  %tmp13159 = getelementptr inbounds float* %tmp13158, i64 1
-  %tmp13160 = getelementptr inbounds float* %tmp13159, i64 1
-  %tmp13161 = getelementptr inbounds float* %tmp13160, i64 1
-  %tmp13162 = getelementptr inbounds float* %tmp13161, i64 1
-  %tmp13163 = getelementptr inbounds float* %tmp13162, i64 1
-  %tmp13164 = getelementptr inbounds float* %tmp13163, i64 1
-  %tmp13165 = getelementptr inbounds float* %tmp13164, i64 1
-  %tmp13166 = getelementptr inbounds float* %tmp13165, i64 1
-  %tmp13167 = getelementptr inbounds float* %tmp13166, i64 1
-  %tmp13168 = getelementptr inbounds float* %tmp13167, i64 1
-  %tmp13169 = getelementptr inbounds float* %tmp13168, i64 1
-  %tmp13170 = getelementptr inbounds float* %tmp13169, i64 1
-  %tmp13171 = getelementptr inbounds float* %tmp13170, i64 1
-  %tmp13172 = getelementptr inbounds float* %tmp13171, i64 1
-  %tmp13173 = getelementptr inbounds float* %tmp13172, i64 1
-  %tmp13174 = getelementptr inbounds float* %tmp13173, i64 1
-  %tmp13175 = getelementptr inbounds float* %tmp13174, i64 1
-  %tmp13176 = getelementptr inbounds float* %tmp13175, i64 1
-  %tmp13177 = getelementptr inbounds float* %tmp13176, i64 1
-  %tmp13178 = getelementptr inbounds float* %tmp13177, i64 1
-  %tmp13179 = getelementptr inbounds float* %tmp13178, i64 1
-  %tmp13180 = getelementptr inbounds float* %tmp13179, i64 1
-  %tmp13181 = getelementptr inbounds float* %tmp13180, i64 1
-  %tmp13182 = getelementptr inbounds float* %tmp13181, i64 1
-  %tmp13183 = getelementptr inbounds float* %tmp13182, i64 1
-  %tmp13184 = getelementptr inbounds float* %tmp13183, i64 1
-  %tmp13185 = getelementptr inbounds float* %tmp13184, i64 1
-  %tmp13186 = getelementptr inbounds float* %tmp13185, i64 1
-  %tmp13187 = getelementptr inbounds float* %tmp13186, i64 1
-  %tmp13188 = getelementptr inbounds float* %tmp13187, i64 1
-  %tmp13189 = getelementptr inbounds float* %tmp13188, i64 1
-  %tmp13190 = getelementptr inbounds float* %tmp13189, i64 1
-  %tmp13191 = getelementptr inbounds float* %tmp13190, i64 1
-  %tmp13192 = getelementptr inbounds float* %tmp13191, i64 1
-  %tmp13193 = getelementptr inbounds float* %tmp13192, i64 1
-  %tmp13194 = getelementptr inbounds float* %tmp13193, i64 1
-  %tmp13195 = getelementptr inbounds float* %tmp13194, i64 1
-  %tmp13196 = getelementptr inbounds float* %tmp13195, i64 1
-  %tmp13197 = getelementptr inbounds float* %tmp13196, i64 1
-  %tmp13198 = getelementptr inbounds float* %tmp13197, i64 1
-  %tmp13199 = getelementptr inbounds float* %tmp13198, i64 1
-  %tmp13200 = getelementptr inbounds float* %tmp13199, i64 1
-  %tmp13201 = getelementptr inbounds float* %tmp13200, i64 1
-  %tmp13202 = getelementptr inbounds float* %tmp13201, i64 1
-  %tmp13203 = getelementptr inbounds float* %tmp13202, i64 1
-  %tmp13204 = getelementptr inbounds float* %tmp13203, i64 1
-  %tmp13205 = getelementptr inbounds float* %tmp13204, i64 1
-  %tmp13206 = getelementptr inbounds float* %tmp13205, i64 1
-  %tmp13207 = getelementptr inbounds float* %tmp13206, i64 1
-  %tmp13208 = getelementptr inbounds float* %tmp13207, i64 1
-  %tmp13209 = getelementptr inbounds float* %tmp13208, i64 1
-  %tmp13210 = getelementptr inbounds float* %tmp13209, i64 1
-  %tmp13211 = getelementptr inbounds float* %tmp13210, i64 1
-  %tmp13212 = getelementptr inbounds float* %tmp13211, i64 1
-  %tmp13213 = getelementptr inbounds float* %tmp13212, i64 1
-  %tmp13214 = getelementptr inbounds float* %tmp13213, i64 1
-  %tmp13215 = getelementptr inbounds float* %tmp13214, i64 1
-  %tmp13216 = getelementptr inbounds float* %tmp13215, i64 1
-  %tmp13217 = getelementptr inbounds float* %tmp13216, i64 1
-  %tmp13218 = getelementptr inbounds float* %tmp13217, i64 1
-  %tmp13219 = getelementptr inbounds float* %tmp13218, i64 1
-  %tmp13220 = getelementptr inbounds float* %tmp13219, i64 1
-  %tmp13221 = getelementptr inbounds float* %tmp13220, i64 1
-  %tmp13222 = getelementptr inbounds float* %tmp13221, i64 1
-  %tmp13223 = getelementptr inbounds float* %tmp13222, i64 1
-  %tmp13224 = getelementptr inbounds float* %tmp13223, i64 1
-  %tmp13225 = getelementptr inbounds float* %tmp13224, i64 1
-  %tmp13226 = getelementptr inbounds float* %tmp13225, i64 1
-  %tmp13227 = getelementptr inbounds float* %tmp13226, i64 1
-  %tmp13228 = getelementptr inbounds float* %tmp13227, i64 1
-  %tmp13229 = getelementptr inbounds float* %tmp13228, i64 1
-  %tmp13230 = getelementptr inbounds float* %tmp13229, i64 1
-  %tmp13231 = getelementptr inbounds float* %tmp13230, i64 1
-  %tmp13232 = getelementptr inbounds float* %tmp13231, i64 1
-  %tmp13233 = getelementptr inbounds float* %tmp13232, i64 1
-  %tmp13234 = getelementptr inbounds float* %tmp13233, i64 1
-  %tmp13235 = getelementptr inbounds float* %tmp13234, i64 1
-  %tmp13236 = getelementptr inbounds float* %tmp13235, i64 1
-  %tmp13237 = getelementptr inbounds float* %tmp13236, i64 1
-  %tmp13238 = getelementptr inbounds float* %tmp13237, i64 1
-  %tmp13239 = getelementptr inbounds float* %tmp13238, i64 1
-  %tmp13240 = getelementptr inbounds float* %tmp13239, i64 1
-  %tmp13241 = getelementptr inbounds float* %tmp13240, i64 1
-  %tmp13242 = getelementptr inbounds float* %tmp13241, i64 1
-  %tmp13243 = getelementptr inbounds float* %tmp13242, i64 1
-  %tmp13244 = getelementptr inbounds float* %tmp13243, i64 1
-  %tmp13245 = getelementptr inbounds float* %tmp13244, i64 1
-  %tmp13246 = getelementptr inbounds float* %tmp13245, i64 1
-  %tmp13247 = getelementptr inbounds float* %tmp13246, i64 1
-  %tmp13248 = getelementptr inbounds float* %tmp13247, i64 1
-  %tmp13249 = getelementptr inbounds float* %tmp13248, i64 1
-  %tmp13250 = getelementptr inbounds float* %tmp13249, i64 1
-  %tmp13251 = getelementptr inbounds float* %tmp13250, i64 1
-  %tmp13252 = getelementptr inbounds float* %tmp13251, i64 1
-  %tmp13253 = getelementptr inbounds float* %tmp13252, i64 1
-  %tmp13254 = getelementptr inbounds float* %tmp13253, i64 1
-  %tmp13255 = getelementptr inbounds float* %tmp13254, i64 1
-  %tmp13256 = getelementptr inbounds float* %tmp13255, i64 1
-  %tmp13257 = getelementptr inbounds float* %tmp13256, i64 1
-  %tmp13258 = getelementptr inbounds float* %tmp13257, i64 1
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-  %tmp13260 = getelementptr inbounds float* %tmp13259, i64 1
-  %tmp13261 = getelementptr inbounds float* %tmp13260, i64 1
-  %tmp13262 = getelementptr inbounds float* %tmp13261, i64 1
-  %tmp13263 = getelementptr inbounds float* %tmp13262, i64 1
-  %tmp13264 = getelementptr inbounds float* %tmp13263, i64 1
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-  %tmp13266 = getelementptr inbounds float* %tmp13265, i64 1
-  %tmp13267 = getelementptr inbounds float* %tmp13266, i64 1
-  %tmp13268 = getelementptr inbounds float* %tmp13267, i64 1
-  %tmp13269 = getelementptr inbounds float* %tmp13268, i64 1
-  %tmp13270 = getelementptr inbounds float* %tmp13269, i64 1
-  %tmp13271 = getelementptr inbounds float* %tmp13270, i64 1
-  %tmp13272 = getelementptr inbounds float* %tmp13271, i64 1
-  %tmp13273 = getelementptr inbounds float* %tmp13272, i64 1
-  %tmp13274 = getelementptr inbounds float* %tmp13273, i64 1
-  %tmp13275 = getelementptr inbounds float* %tmp13274, i64 1
-  %tmp13276 = getelementptr inbounds float* %tmp13275, i64 1
-  %tmp13277 = getelementptr inbounds float* %tmp13276, i64 1
-  %tmp13278 = getelementptr inbounds float* %tmp13277, i64 1
-  %tmp13279 = getelementptr inbounds float* %tmp13278, i64 1
-  %tmp13280 = getelementptr inbounds float* %tmp13279, i64 1
-  %tmp13281 = getelementptr inbounds float* %tmp13280, i64 1
-  %tmp13282 = getelementptr inbounds float* %tmp13281, i64 1
-  %tmp13283 = getelementptr inbounds float* %tmp13282, i64 1
-  %tmp13284 = getelementptr inbounds float* %tmp13283, i64 1
-  %tmp13285 = getelementptr inbounds float* %tmp13284, i64 1
-  %tmp13286 = getelementptr inbounds float* %tmp13285, i64 1
-  %tmp13287 = getelementptr inbounds float* %tmp13286, i64 1
-  %tmp13288 = getelementptr inbounds float* %tmp13287, i64 1
-  %tmp13289 = getelementptr inbounds float* %tmp13288, i64 1
-  %tmp13290 = getelementptr inbounds float* %tmp13289, i64 1
-  %tmp13291 = getelementptr inbounds float* %tmp13290, i64 1
-  %tmp13292 = getelementptr inbounds float* %tmp13291, i64 1
-  %tmp13293 = getelementptr inbounds float* %tmp13292, i64 1
-  %tmp13294 = getelementptr inbounds float* %tmp13293, i64 1
-  %tmp13295 = getelementptr inbounds float* %tmp13294, i64 1
-  %tmp13296 = getelementptr inbounds float* %tmp13295, i64 1
-  %tmp13297 = getelementptr inbounds float* %tmp13296, i64 1
-  %tmp13298 = getelementptr inbounds float* %tmp13297, i64 1
-  %tmp13299 = getelementptr inbounds float* %tmp13298, i64 1
-  %tmp13300 = getelementptr inbounds float* %tmp13299, i64 1
-  %tmp13301 = getelementptr inbounds float* %tmp13300, i64 1
-  %tmp13302 = getelementptr inbounds float* %tmp13301, i64 1
-  %tmp13303 = getelementptr inbounds float* %tmp13302, i64 1
-  %tmp13304 = getelementptr inbounds float* %tmp13303, i64 1
-  %tmp13305 = getelementptr inbounds float* %tmp13304, i64 1
-  %tmp13306 = getelementptr inbounds float* %tmp13305, i64 1
-  %tmp13307 = getelementptr inbounds float* %tmp13306, i64 1
-  %tmp13308 = getelementptr inbounds float* %tmp13307, i64 1
-  %tmp13309 = getelementptr inbounds float* %tmp13308, i64 1
-  %tmp13310 = getelementptr inbounds float* %tmp13309, i64 1
-  %tmp13311 = getelementptr inbounds float* %tmp13310, i64 1
-  %tmp13312 = getelementptr inbounds float* %tmp13311, i64 1
-  %tmp13313 = getelementptr inbounds float* %tmp13312, i64 1
-  %tmp13314 = getelementptr inbounds float* %tmp13313, i64 1
-  %tmp13315 = getelementptr inbounds float* %tmp13314, i64 1
-  %tmp13316 = getelementptr inbounds float* %tmp13315, i64 1
-  %tmp13317 = getelementptr inbounds float* %tmp13316, i64 1
-  %tmp13318 = getelementptr inbounds float* %tmp13317, i64 1
-  %tmp13319 = getelementptr inbounds float* %tmp13318, i64 1
-  %tmp13320 = getelementptr inbounds float* %tmp13319, i64 1
-  %tmp13321 = getelementptr inbounds float* %tmp13320, i64 1
-  %tmp13322 = getelementptr inbounds float* %tmp13321, i64 1
-  %tmp13323 = getelementptr inbounds float* %tmp13322, i64 1
-  %tmp13324 = getelementptr inbounds float* %tmp13323, i64 1
-  %tmp13325 = getelementptr inbounds float* %tmp13324, i64 1
-  %tmp13326 = getelementptr inbounds float* %tmp13325, i64 1
-  %tmp13327 = getelementptr inbounds float* %tmp13326, i64 1
-  %tmp13328 = getelementptr inbounds float* %tmp13327, i64 1
-  %tmp13329 = getelementptr inbounds float* %tmp13328, i64 1
-  %tmp13330 = getelementptr inbounds float* %tmp13329, i64 1
-  %tmp13331 = getelementptr inbounds float* %tmp13330, i64 1
-  %tmp13332 = getelementptr inbounds float* %tmp13331, i64 1
-  %tmp13333 = getelementptr inbounds float* %tmp13332, i64 1
-  %tmp13334 = getelementptr inbounds float* %tmp13333, i64 1
-  %tmp13335 = getelementptr inbounds float* %tmp13334, i64 1
-  %tmp13336 = getelementptr inbounds float* %tmp13335, i64 1
-  %tmp13337 = getelementptr inbounds float* %tmp13336, i64 1
-  %tmp13338 = getelementptr inbounds float* %tmp13337, i64 1
-  %tmp13339 = getelementptr inbounds float* %tmp13338, i64 1
-  %tmp13340 = getelementptr inbounds float* %tmp13339, i64 1
-  %tmp13341 = getelementptr inbounds float* %tmp13340, i64 1
-  %tmp13342 = getelementptr inbounds float* %tmp13341, i64 1
-  %tmp13343 = getelementptr inbounds float* %tmp13342, i64 1
-  %tmp13344 = getelementptr inbounds float* %tmp13343, i64 1
-  %tmp13345 = getelementptr inbounds float* %tmp13344, i64 1
-  %tmp13346 = getelementptr inbounds float* %tmp13345, i64 1
-  %tmp13347 = getelementptr inbounds float* %tmp13346, i64 1
-  %tmp13348 = getelementptr inbounds float* %tmp13347, i64 1
-  %tmp13349 = getelementptr inbounds float* %tmp13348, i64 1
-  %tmp13350 = getelementptr inbounds float* %tmp13349, i64 1
-  %tmp13351 = getelementptr inbounds float* %tmp13350, i64 1
-  %tmp13352 = getelementptr inbounds float* %tmp13351, i64 1
-  %tmp13353 = getelementptr inbounds float* %tmp13352, i64 1
-  %tmp13354 = getelementptr inbounds float* %tmp13353, i64 1
-  %tmp13355 = getelementptr inbounds float* %tmp13354, i64 1
-  %tmp13356 = getelementptr inbounds float* %tmp13355, i64 1
-  %tmp13357 = getelementptr inbounds float* %tmp13356, i64 1
-  %tmp13358 = getelementptr inbounds float* %tmp13357, i64 1
-  %tmp13359 = getelementptr inbounds float* %tmp13358, i64 1
-  %tmp13360 = getelementptr inbounds float* %tmp13359, i64 1
-  %tmp13361 = getelementptr inbounds float* %tmp13360, i64 1
-  %tmp13362 = getelementptr inbounds float* %tmp13361, i64 1
-  %tmp13363 = getelementptr inbounds float* %tmp13362, i64 1
-  %tmp13364 = getelementptr inbounds float* %tmp13363, i64 1
-  %tmp13365 = getelementptr inbounds float* %tmp13364, i64 1
-  %tmp13366 = getelementptr inbounds float* %tmp13365, i64 1
-  %tmp13367 = getelementptr inbounds float* %tmp13366, i64 1
-  %tmp13368 = getelementptr inbounds float* %tmp13367, i64 1
-  %tmp13369 = getelementptr inbounds float* %tmp13368, i64 1
-  %tmp13370 = getelementptr inbounds float* %tmp13369, i64 1
-  %tmp13371 = getelementptr inbounds float* %tmp13370, i64 1
-  %tmp13372 = getelementptr inbounds float* %tmp13371, i64 1
-  %tmp13373 = getelementptr inbounds float* %tmp13372, i64 1
-  %tmp13374 = getelementptr inbounds float* %tmp13373, i64 1
-  %tmp13375 = getelementptr inbounds float* %tmp13374, i64 1
-  %tmp13376 = getelementptr inbounds float* %tmp13375, i64 1
-  %tmp13377 = getelementptr inbounds float* %tmp13376, i64 1
-  %tmp13378 = getelementptr inbounds float* %tmp13377, i64 1
-  %tmp13379 = getelementptr inbounds float* %tmp13378, i64 1
-  %tmp13380 = getelementptr inbounds float* %tmp13379, i64 1
-  %tmp13381 = getelementptr inbounds float* %tmp13380, i64 1
-  %tmp13382 = getelementptr inbounds float* %tmp13381, i64 1
-  %tmp13383 = getelementptr inbounds float* %tmp13382, i64 1
-  %tmp13384 = getelementptr inbounds float* %tmp13383, i64 1
-  %tmp13385 = getelementptr inbounds float* %tmp13384, i64 1
-  %tmp13386 = getelementptr inbounds float* %tmp13385, i64 1
-  %tmp13387 = getelementptr inbounds float* %tmp13386, i64 1
-  %tmp13388 = getelementptr inbounds float* %tmp13387, i64 1
-  %tmp13389 = getelementptr inbounds float* %tmp13388, i64 1
-  %tmp13390 = getelementptr inbounds float* %tmp13389, i64 1
-  %tmp13391 = getelementptr inbounds float* %tmp13390, i64 1
-  %tmp13392 = getelementptr inbounds float* %tmp13391, i64 1
-  %tmp13393 = getelementptr inbounds float* %tmp13392, i64 1
-  %tmp13394 = getelementptr inbounds float* %tmp13393, i64 1
-  %tmp13395 = getelementptr inbounds float* %tmp13394, i64 1
-  %tmp13396 = getelementptr inbounds float* %tmp13395, i64 1
-  %tmp13397 = getelementptr inbounds float* %tmp13396, i64 1
-  %tmp13398 = getelementptr inbounds float* %tmp13397, i64 1
-  %tmp13399 = getelementptr inbounds float* %tmp13398, i64 1
-  %tmp13400 = getelementptr inbounds float* %tmp13399, i64 1
-  %tmp13401 = getelementptr inbounds float* %tmp13400, i64 1
-  %tmp13402 = getelementptr inbounds float* %tmp13401, i64 1
-  %tmp13403 = getelementptr inbounds float* %tmp13402, i64 1
-  %tmp13404 = getelementptr inbounds float* %tmp13403, i64 1
-  %tmp13405 = getelementptr inbounds float* %tmp13404, i64 1
-  %tmp13406 = getelementptr inbounds float* %tmp13405, i64 1
-  %tmp13407 = getelementptr inbounds float* %tmp13406, i64 1
-  %tmp13408 = getelementptr inbounds float* %tmp13407, i64 1
-  %tmp13409 = getelementptr inbounds float* %tmp13408, i64 1
-  %tmp13410 = getelementptr inbounds float* %tmp13409, i64 1
-  %tmp13411 = getelementptr inbounds float* %tmp13410, i64 1
-  %tmp13412 = getelementptr inbounds float* %tmp13411, i64 1
-  %tmp13413 = getelementptr inbounds float* %tmp13412, i64 1
-  %tmp13414 = getelementptr inbounds float* %tmp13413, i64 1
-  %tmp13415 = getelementptr inbounds float* %tmp13414, i64 1
-  %tmp13416 = getelementptr inbounds float* %tmp13415, i64 1
-  %tmp13417 = getelementptr inbounds float* %tmp13416, i64 1
-  %tmp13418 = getelementptr inbounds float* %tmp13417, i64 1
-  %tmp13419 = getelementptr inbounds float* %tmp13418, i64 1
-  %tmp13420 = getelementptr inbounds float* %tmp13419, i64 1
-  %tmp13421 = getelementptr inbounds float* %tmp13420, i64 1
-  %tmp13422 = getelementptr inbounds float* %tmp13421, i64 1
-  %tmp13423 = getelementptr inbounds float* %tmp13422, i64 1
-  %tmp13424 = getelementptr inbounds float* %tmp13423, i64 1
-  %tmp13425 = getelementptr inbounds float* %tmp13424, i64 1
-  %tmp13426 = getelementptr inbounds float* %tmp13425, i64 1
-  %tmp13427 = getelementptr inbounds float* %tmp13426, i64 1
-  %tmp13428 = getelementptr inbounds float* %tmp13427, i64 1
-  %tmp13429 = getelementptr inbounds float* %tmp13428, i64 1
-  %tmp13430 = getelementptr inbounds float* %tmp13429, i64 1
-  %tmp13431 = getelementptr inbounds float* %tmp13430, i64 1
-  %tmp13432 = getelementptr inbounds float* %tmp13431, i64 1
-  %tmp13433 = getelementptr inbounds float* %tmp13432, i64 1
-  %tmp13434 = getelementptr inbounds float* %tmp13433, i64 1
-  %tmp13435 = getelementptr inbounds float* %tmp13434, i64 1
-  %tmp13436 = getelementptr inbounds float* %tmp13435, i64 1
-  %tmp13437 = getelementptr inbounds float* %tmp13436, i64 1
-  %tmp13438 = getelementptr inbounds float* %tmp13437, i64 1
-  %tmp13439 = getelementptr inbounds float* %tmp13438, i64 1
-  %tmp13440 = getelementptr inbounds float* %tmp13439, i64 1
-  %tmp13441 = getelementptr inbounds float* %tmp13440, i64 1
-  %tmp13442 = getelementptr inbounds float* %tmp13441, i64 1
-  %tmp13443 = getelementptr inbounds float* %tmp13442, i64 1
-  %tmp13444 = getelementptr inbounds float* %tmp13443, i64 1
-  %tmp13445 = getelementptr inbounds float* %tmp13444, i64 1
-  %tmp13446 = getelementptr inbounds float* %tmp13445, i64 1
-  %tmp13447 = getelementptr inbounds float* %tmp13446, i64 1
-  %tmp13448 = getelementptr inbounds float* %tmp13447, i64 1
-  %tmp13449 = getelementptr inbounds float* %tmp13448, i64 1
-  %tmp13450 = getelementptr inbounds float* %tmp13449, i64 1
-  %tmp13451 = getelementptr inbounds float* %tmp13450, i64 1
-  %tmp13452 = getelementptr inbounds float* %tmp13451, i64 1
-  %tmp13453 = getelementptr inbounds float* %tmp13452, i64 1
-  %tmp13454 = getelementptr inbounds float* %tmp13453, i64 1
-  %tmp13455 = getelementptr inbounds float* %tmp13454, i64 1
-  %tmp13456 = getelementptr inbounds float* %tmp13455, i64 1
-  %tmp13457 = getelementptr inbounds float* %tmp13456, i64 1
-  %tmp13458 = getelementptr inbounds float* %tmp13457, i64 1
-  %tmp13459 = getelementptr inbounds float* %tmp13458, i64 1
-  %tmp13460 = getelementptr inbounds float* %tmp13459, i64 1
-  %tmp13461 = getelementptr inbounds float* %tmp13460, i64 1
-  %tmp13462 = getelementptr inbounds float* %tmp13461, i64 1
-  %tmp13463 = getelementptr inbounds float* %tmp13462, i64 1
-  %tmp13464 = getelementptr inbounds float* %tmp13463, i64 1
-  %tmp13465 = getelementptr inbounds float* %tmp13464, i64 1
-  %tmp13466 = getelementptr inbounds float* %tmp13465, i64 1
-  %tmp13467 = getelementptr inbounds float* %tmp13466, i64 1
-  %tmp13468 = getelementptr inbounds float* %tmp13467, i64 1
-  %tmp13469 = getelementptr inbounds float* %tmp13468, i64 1
-  %tmp13470 = getelementptr inbounds float* %tmp13469, i64 1
-  %tmp13471 = getelementptr inbounds float* %tmp13470, i64 1
-  %tmp13472 = getelementptr inbounds float* %tmp13471, i64 1
-  %tmp13473 = getelementptr inbounds float* %tmp13472, i64 1
-  %tmp13474 = getelementptr inbounds float* %tmp13473, i64 1
-  %tmp13475 = getelementptr inbounds float* %tmp13474, i64 1
-  %tmp13476 = getelementptr inbounds float* %tmp13475, i64 1
-  %tmp13477 = getelementptr inbounds float* %tmp13476, i64 1
-  %tmp13478 = getelementptr inbounds float* %tmp13477, i64 1
-  %tmp13479 = getelementptr inbounds float* %tmp13478, i64 1
-  %tmp13480 = getelementptr inbounds float* %tmp13479, i64 1
-  %tmp13481 = getelementptr inbounds float* %tmp13480, i64 1
-  %tmp13482 = getelementptr inbounds float* %tmp13481, i64 1
-  %tmp13483 = getelementptr inbounds float* %tmp13482, i64 1
-  %tmp13484 = getelementptr inbounds float* %tmp13483, i64 1
-  %tmp13485 = getelementptr inbounds float* %tmp13484, i64 1
-  %tmp13486 = getelementptr inbounds float* %tmp13485, i64 1
-  %tmp13487 = getelementptr inbounds float* %tmp13486, i64 1
-  %tmp13488 = getelementptr inbounds float* %tmp13487, i64 1
-  %tmp13489 = getelementptr inbounds float* %tmp13488, i64 1
-  %tmp13490 = getelementptr inbounds float* %tmp13489, i64 1
-  %tmp13491 = getelementptr inbounds float* %tmp13490, i64 1
-  %tmp13492 = getelementptr inbounds float* %tmp13491, i64 1
-  %tmp13493 = getelementptr inbounds float* %tmp13492, i64 1
-  %tmp13494 = getelementptr inbounds float* %tmp13493, i64 1
-  %tmp13495 = getelementptr inbounds float* %tmp13494, i64 1
-  %tmp13496 = getelementptr inbounds float* %tmp13495, i64 1
-  %tmp13497 = getelementptr inbounds float* %tmp13496, i64 1
-  %tmp13498 = getelementptr inbounds float* %tmp13497, i64 1
-  %tmp13499 = getelementptr inbounds float* %tmp13498, i64 1
-  %tmp13500 = getelementptr inbounds float* %tmp13499, i64 1
-  %tmp13501 = getelementptr inbounds float* %tmp13500, i64 1
-  %tmp13502 = getelementptr inbounds float* %tmp13501, i64 1
-  %tmp13503 = getelementptr inbounds float* %tmp13502, i64 1
-  %tmp13504 = getelementptr inbounds float* %tmp13503, i64 1
-  %tmp13505 = getelementptr inbounds float* %tmp13504, i64 1
-  %tmp13506 = getelementptr inbounds float* %tmp13505, i64 1
-  %tmp13507 = getelementptr inbounds float* %tmp13506, i64 1
-  %tmp13508 = getelementptr inbounds float* %tmp13507, i64 1
-  %tmp13509 = getelementptr inbounds float* %tmp13508, i64 1
-  %tmp13510 = getelementptr inbounds float* %tmp13509, i64 1
-  %tmp13511 = getelementptr inbounds float* %tmp13510, i64 1
-  %tmp13512 = getelementptr inbounds float* %tmp13511, i64 1
-  %tmp13513 = getelementptr inbounds float* %tmp13512, i64 1
-  %tmp13514 = getelementptr inbounds float* %tmp13513, i64 1
-  %tmp13515 = getelementptr inbounds float* %tmp13514, i64 1
-  %tmp13516 = getelementptr inbounds float* %tmp13515, i64 1
-  %tmp13517 = getelementptr inbounds float* %tmp13516, i64 1
-  %tmp13518 = getelementptr inbounds float* %tmp13517, i64 1
-  %tmp13519 = getelementptr inbounds float* %tmp13518, i64 1
-  %tmp13520 = getelementptr inbounds float* %tmp13519, i64 1
-  %tmp13521 = getelementptr inbounds float* %tmp13520, i64 1
-  %tmp13522 = getelementptr inbounds float* %tmp13521, i64 1
-  %tmp13523 = getelementptr inbounds float* %tmp13522, i64 1
-  %tmp13524 = getelementptr inbounds float* %tmp13523, i64 1
-  %tmp13525 = getelementptr inbounds float* %tmp13524, i64 1
-  %tmp13526 = getelementptr inbounds float* %tmp13525, i64 1
-  %tmp13527 = getelementptr inbounds float* %tmp13526, i64 1
-  %tmp13528 = getelementptr inbounds float* %tmp13527, i64 1
-  %tmp13529 = getelementptr inbounds float* %tmp13528, i64 1
-  %tmp13530 = getelementptr inbounds float* %tmp13529, i64 1
-  %tmp13531 = getelementptr inbounds float* %tmp13530, i64 1
-  %tmp13532 = getelementptr inbounds float* %tmp13531, i64 1
-  %tmp13533 = getelementptr inbounds float* %tmp13532, i64 1
-  %tmp13534 = getelementptr inbounds float* %tmp13533, i64 1
-  %tmp13535 = getelementptr inbounds float* %tmp13534, i64 1
-  %tmp13536 = getelementptr inbounds float* %tmp13535, i64 1
-  %tmp13537 = getelementptr inbounds float* %tmp13536, i64 1
-  %tmp13538 = getelementptr inbounds float* %tmp13537, i64 1
-  %tmp13539 = getelementptr inbounds float* %tmp13538, i64 1
-  %tmp13540 = getelementptr inbounds float* %tmp13539, i64 1
-  %tmp13541 = getelementptr inbounds float* %tmp13540, i64 1
-  %tmp13542 = getelementptr inbounds float* %tmp13541, i64 1
-  %tmp13543 = getelementptr inbounds float* %tmp13542, i64 1
-  %tmp13544 = getelementptr inbounds float* %tmp13543, i64 1
-  %tmp13545 = getelementptr inbounds float* %tmp13544, i64 1
-  %tmp13546 = getelementptr inbounds float* %tmp13545, i64 1
-  %tmp13547 = getelementptr inbounds float* %tmp13546, i64 1
-  %tmp13548 = getelementptr inbounds float* %tmp13547, i64 1
-  %tmp13549 = getelementptr inbounds float* %tmp13548, i64 1
-  %tmp13550 = getelementptr inbounds float* %tmp13549, i64 1
-  %tmp13551 = getelementptr inbounds float* %tmp13550, i64 1
-  %tmp13552 = getelementptr inbounds float* %tmp13551, i64 1
-  %tmp13553 = getelementptr inbounds float* %tmp13552, i64 1
-  %tmp13554 = getelementptr inbounds float* %tmp13553, i64 1
-  %tmp13555 = getelementptr inbounds float* %tmp13554, i64 1
-  %tmp13556 = getelementptr inbounds float* %tmp13555, i64 1
-  %tmp13557 = getelementptr inbounds float* %tmp13556, i64 1
-  %tmp13558 = getelementptr inbounds float* %tmp13557, i64 1
-  %tmp13559 = getelementptr inbounds float* %tmp13558, i64 1
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-  %tmp13562 = getelementptr inbounds float* %tmp13561, i64 1
-  %tmp13563 = getelementptr inbounds float* %tmp13562, i64 1
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-  %tmp13565 = getelementptr inbounds float* %tmp13564, i64 1
-  %tmp13566 = getelementptr inbounds float* %tmp13565, i64 1
-  %tmp13567 = getelementptr inbounds float* %tmp13566, i64 1
-  %tmp13568 = getelementptr inbounds float* %tmp13567, i64 1
-  %tmp13569 = getelementptr inbounds float* %tmp13568, i64 1
-  %tmp13570 = getelementptr inbounds float* %tmp13569, i64 1
-  %tmp13571 = getelementptr inbounds float* %tmp13570, i64 1
-  %tmp13572 = getelementptr inbounds float* %tmp13571, i64 1
-  %tmp13573 = getelementptr inbounds float* %tmp13572, i64 1
-  %tmp13574 = getelementptr inbounds float* %tmp13573, i64 1
-  %tmp13575 = getelementptr inbounds float* %tmp13574, i64 1
-  %tmp13576 = getelementptr inbounds float* %tmp13575, i64 1
-  %tmp13577 = getelementptr inbounds float* %tmp13576, i64 1
-  %tmp13578 = getelementptr inbounds float* %tmp13577, i64 1
-  %tmp13579 = getelementptr inbounds float* %tmp13578, i64 1
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-  %tmp13581 = getelementptr inbounds float* %tmp13580, i64 1
-  %tmp13582 = getelementptr inbounds float* %tmp13581, i64 1
-  %tmp13583 = getelementptr inbounds float* %tmp13582, i64 1
-  %tmp13584 = getelementptr inbounds float* %tmp13583, i64 1
-  %tmp13585 = getelementptr inbounds float* %tmp13584, i64 1
-  %tmp13586 = getelementptr inbounds float* %tmp13585, i64 1
-  %tmp13587 = getelementptr inbounds float* %tmp13586, i64 1
-  %tmp13588 = getelementptr inbounds float* %tmp13587, i64 1
-  %tmp13589 = getelementptr inbounds float* %tmp13588, i64 1
-  %tmp13590 = getelementptr inbounds float* %tmp13589, i64 1
-  %tmp13591 = getelementptr inbounds float* %tmp13590, i64 1
-  %tmp13592 = getelementptr inbounds float* %tmp13591, i64 1
-  %tmp13593 = getelementptr inbounds float* %tmp13592, i64 1
-  %tmp13594 = getelementptr inbounds float* %tmp13593, i64 1
-  %tmp13595 = getelementptr inbounds float* %tmp13594, i64 1
-  %tmp13596 = getelementptr inbounds float* %tmp13595, i64 1
-  %tmp13597 = getelementptr inbounds float* %tmp13596, i64 1
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-  %tmp13599 = getelementptr inbounds float* %tmp13598, i64 1
-  %tmp13600 = getelementptr inbounds float* %tmp13599, i64 1
-  %tmp13601 = getelementptr inbounds float* %tmp13600, i64 1
-  %tmp13602 = getelementptr inbounds float* %tmp13601, i64 1
-  %tmp13603 = getelementptr inbounds float* %tmp13602, i64 1
-  %tmp13604 = getelementptr inbounds float* %tmp13603, i64 1
-  %tmp13605 = getelementptr inbounds float* %tmp13604, i64 1
-  %tmp13606 = getelementptr inbounds float* %tmp13605, i64 1
-  %tmp13607 = getelementptr inbounds float* %tmp13606, i64 1
-  %tmp13608 = getelementptr inbounds float* %tmp13607, i64 1
-  %tmp13609 = getelementptr inbounds float* %tmp13608, i64 1
-  %tmp13610 = getelementptr inbounds float* %tmp13609, i64 1
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-  %tmp13612 = getelementptr inbounds float* %tmp13611, i64 1
-  %tmp13613 = getelementptr inbounds float* %tmp13612, i64 1
-  %tmp13614 = getelementptr inbounds float* %tmp13613, i64 1
-  %tmp13615 = getelementptr inbounds float* %tmp13614, i64 1
-  %tmp13616 = getelementptr inbounds float* %tmp13615, i64 1
-  %tmp13617 = getelementptr inbounds float* %tmp13616, i64 1
-  %tmp13618 = getelementptr inbounds float* %tmp13617, i64 1
-  %tmp13619 = getelementptr inbounds float* %tmp13618, i64 1
-  %tmp13620 = getelementptr inbounds float* %tmp13619, i64 1
-  %tmp13621 = getelementptr inbounds float* %tmp13620, i64 1
-  %tmp13622 = getelementptr inbounds float* %tmp13621, i64 1
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-  %tmp13624 = getelementptr inbounds float* %tmp13623, i64 1
-  %tmp13625 = getelementptr inbounds float* %tmp13624, i64 1
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-  %tmp13627 = getelementptr inbounds float* %tmp13626, i64 1
-  %tmp13628 = getelementptr inbounds float* %tmp13627, i64 1
-  %tmp13629 = getelementptr inbounds float* %tmp13628, i64 1
-  %tmp13630 = getelementptr inbounds float* %tmp13629, i64 1
-  %tmp13631 = getelementptr inbounds float* %tmp13630, i64 1
-  %tmp13632 = getelementptr inbounds float* %tmp13631, i64 1
-  %tmp13633 = getelementptr inbounds float* %tmp13632, i64 1
-  %tmp13634 = getelementptr inbounds float* %tmp13633, i64 1
-  %tmp13635 = getelementptr inbounds float* %tmp13634, i64 1
-  %tmp13636 = getelementptr inbounds float* %tmp13635, i64 1
-  %tmp13637 = getelementptr inbounds float* %tmp13636, i64 1
-  %tmp13638 = getelementptr inbounds float* %tmp13637, i64 1
-  %tmp13639 = getelementptr inbounds float* %tmp13638, i64 1
-  %tmp13640 = getelementptr inbounds float* %tmp13639, i64 1
-  %tmp13641 = getelementptr inbounds float* %tmp13640, i64 1
-  %tmp13642 = getelementptr inbounds float* %tmp13641, i64 1
-  %tmp13643 = getelementptr inbounds float* %tmp13642, i64 1
-  %tmp13644 = getelementptr inbounds float* %tmp13643, i64 1
-  %tmp13645 = getelementptr inbounds float* %tmp13644, i64 1
-  %tmp13646 = getelementptr inbounds float* %tmp13645, i64 1
-  %tmp13647 = getelementptr inbounds float* %tmp13646, i64 1
-  %tmp13648 = getelementptr inbounds float* %tmp13647, i64 1
-  %tmp13649 = getelementptr inbounds float* %tmp13648, i64 1
-  %tmp13650 = getelementptr inbounds float* %tmp13649, i64 1
-  %tmp13651 = getelementptr inbounds float* %tmp13650, i64 1
-  %tmp13652 = getelementptr inbounds float* %tmp13651, i64 1
-  %tmp13653 = getelementptr inbounds float* %tmp13652, i64 1
-  %tmp13654 = getelementptr inbounds float* %tmp13653, i64 1
-  %tmp13655 = getelementptr inbounds float* %tmp13654, i64 1
-  %tmp13656 = getelementptr inbounds float* %tmp13655, i64 1
-  %tmp13657 = getelementptr inbounds float* %tmp13656, i64 1
-  %tmp13658 = getelementptr inbounds float* %tmp13657, i64 1
-  %tmp13659 = getelementptr inbounds float* %tmp13658, i64 1
-  %tmp13660 = getelementptr inbounds float* %tmp13659, i64 1
-  %tmp13661 = getelementptr inbounds float* %tmp13660, i64 1
-  %tmp13662 = getelementptr inbounds float* %tmp13661, i64 1
-  %tmp13663 = getelementptr inbounds float* %tmp13662, i64 1
-  %tmp13664 = getelementptr inbounds float* %tmp13663, i64 1
-  %tmp13665 = getelementptr inbounds float* %tmp13664, i64 1
-  %tmp13666 = getelementptr inbounds float* %tmp13665, i64 1
-  %tmp13667 = getelementptr inbounds float* %tmp13666, i64 1
-  %tmp13668 = getelementptr inbounds float* %tmp13667, i64 1
-  %tmp13669 = getelementptr inbounds float* %tmp13668, i64 1
-  %tmp13670 = getelementptr inbounds float* %tmp13669, i64 1
-  %tmp13671 = getelementptr inbounds float* %tmp13670, i64 1
-  %tmp13672 = getelementptr inbounds float* %tmp13671, i64 1
-  %tmp13673 = getelementptr inbounds float* %tmp13672, i64 1
-  %tmp13674 = getelementptr inbounds float* %tmp13673, i64 1
-  %tmp13675 = getelementptr inbounds float* %tmp13674, i64 1
-  %tmp13676 = getelementptr inbounds float* %tmp13675, i64 1
-  %tmp13677 = getelementptr inbounds float* %tmp13676, i64 1
-  %tmp13678 = getelementptr inbounds float* %tmp13677, i64 1
-  %tmp13679 = getelementptr inbounds float* %tmp13678, i64 1
-  %tmp13680 = getelementptr inbounds float* %tmp13679, i64 1
-  %tmp13681 = getelementptr inbounds float* %tmp13680, i64 1
-  %tmp13682 = getelementptr inbounds float* %tmp13681, i64 1
-  %tmp13683 = getelementptr inbounds float* %tmp13682, i64 1
-  %tmp13684 = getelementptr inbounds float* %tmp13683, i64 1
-  %tmp13685 = getelementptr inbounds float* %tmp13684, i64 1
-  %tmp13686 = getelementptr inbounds float* %tmp13685, i64 1
-  %tmp13687 = getelementptr inbounds float* %tmp13686, i64 1
-  %tmp13688 = getelementptr inbounds float* %tmp13687, i64 1
-  %tmp13689 = getelementptr inbounds float* %tmp13688, i64 1
-  %tmp13690 = getelementptr inbounds float* %tmp13689, i64 1
-  %tmp13691 = getelementptr inbounds float* %tmp13690, i64 1
-  %tmp13692 = getelementptr inbounds float* %tmp13691, i64 1
-  %tmp13693 = getelementptr inbounds float* %tmp13692, i64 1
-  %tmp13694 = getelementptr inbounds float* %tmp13693, i64 1
-  %tmp13695 = getelementptr inbounds float* %tmp13694, i64 1
-  %tmp13696 = getelementptr inbounds float* %tmp13695, i64 1
-  %tmp13697 = getelementptr inbounds float* %tmp13696, i64 1
-  %tmp13698 = getelementptr inbounds float* %tmp13697, i64 1
-  %tmp13699 = getelementptr inbounds float* %tmp13698, i64 1
-  %tmp13700 = getelementptr inbounds float* %tmp13699, i64 1
-  %tmp13701 = getelementptr inbounds float* %tmp13700, i64 1
-  %tmp13702 = getelementptr inbounds float* %tmp13701, i64 1
-  %tmp13703 = getelementptr inbounds float* %tmp13702, i64 1
-  %tmp13704 = getelementptr inbounds float* %tmp13703, i64 1
-  %tmp13705 = getelementptr inbounds float* %tmp13704, i64 1
-  %tmp13706 = getelementptr inbounds float* %tmp13705, i64 1
-  %tmp13707 = getelementptr inbounds float* %tmp13706, i64 1
-  %tmp13708 = getelementptr inbounds float* %tmp13707, i64 1
-  %tmp13709 = getelementptr inbounds float* %tmp13708, i64 1
-  %tmp13710 = getelementptr inbounds float* %tmp13709, i64 1
-  %tmp13711 = getelementptr inbounds float* %tmp13710, i64 1
-  %tmp13712 = getelementptr inbounds float* %tmp13711, i64 1
-  %tmp13713 = getelementptr inbounds float* %tmp13712, i64 1
-  %tmp13714 = getelementptr inbounds float* %tmp13713, i64 1
-  %tmp13715 = getelementptr inbounds float* %tmp13714, i64 1
-  %tmp13716 = getelementptr inbounds float* %tmp13715, i64 1
-  %tmp13717 = getelementptr inbounds float* %tmp13716, i64 1
-  %tmp13718 = getelementptr inbounds float* %tmp13717, i64 1
-  %tmp13719 = getelementptr inbounds float* %tmp13718, i64 1
-  %tmp13720 = getelementptr inbounds float* %tmp13719, i64 1
-  %tmp13721 = getelementptr inbounds float* %tmp13720, i64 1
-  %tmp13722 = getelementptr inbounds float* %tmp13721, i64 1
-  %tmp13723 = getelementptr inbounds float* %tmp13722, i64 1
-  %tmp13724 = getelementptr inbounds float* %tmp13723, i64 1
-  %tmp13725 = getelementptr inbounds float* %tmp13724, i64 1
-  %tmp13726 = getelementptr inbounds float* %tmp13725, i64 1
-  %tmp13727 = getelementptr inbounds float* %tmp13726, i64 1
-  %tmp13728 = getelementptr inbounds float* %tmp13727, i64 1
-  %tmp13729 = getelementptr inbounds float* %tmp13728, i64 1
-  %tmp13730 = getelementptr inbounds float* %tmp13729, i64 1
-  %tmp13731 = getelementptr inbounds float* %tmp13730, i64 1
-  %tmp13732 = getelementptr inbounds float* %tmp13731, i64 1
-  %tmp13733 = getelementptr inbounds float* %tmp13732, i64 1
-  %tmp13734 = getelementptr inbounds float* %tmp13733, i64 1
-  %tmp13735 = getelementptr inbounds float* %tmp13734, i64 1
-  %tmp13736 = getelementptr inbounds float* %tmp13735, i64 1
-  %tmp13737 = getelementptr inbounds float* %tmp13736, i64 1
-  %tmp13738 = getelementptr inbounds float* %tmp13737, i64 1
-  %tmp13739 = getelementptr inbounds float* %tmp13738, i64 1
-  %tmp13740 = getelementptr inbounds float* %tmp13739, i64 1
-  %tmp13741 = getelementptr inbounds float* %tmp13740, i64 1
-  %tmp13742 = getelementptr inbounds float* %tmp13741, i64 1
-  %tmp13743 = getelementptr inbounds float* %tmp13742, i64 1
-  %tmp13744 = getelementptr inbounds float* %tmp13743, i64 1
-  %tmp13745 = getelementptr inbounds float* %tmp13744, i64 1
-  %tmp13746 = getelementptr inbounds float* %tmp13745, i64 1
-  %tmp13747 = getelementptr inbounds float* %tmp13746, i64 1
-  %tmp13748 = getelementptr inbounds float* %tmp13747, i64 1
-  %tmp13749 = getelementptr inbounds float* %tmp13748, i64 1
-  %tmp13750 = getelementptr inbounds float* %tmp13749, i64 1
-  %tmp13751 = getelementptr inbounds float* %tmp13750, i64 1
-  %tmp13752 = getelementptr inbounds float* %tmp13751, i64 1
-  %tmp13753 = getelementptr inbounds float* %tmp13752, i64 1
-  %tmp13754 = getelementptr inbounds float* %tmp13753, i64 1
-  %tmp13755 = getelementptr inbounds float* %tmp13754, i64 1
-  %tmp13756 = getelementptr inbounds float* %tmp13755, i64 1
-  %tmp13757 = getelementptr inbounds float* %tmp13756, i64 1
-  %tmp13758 = getelementptr inbounds float* %tmp13757, i64 1
-  %tmp13759 = getelementptr inbounds float* %tmp13758, i64 1
-  %tmp13760 = getelementptr inbounds float* %tmp13759, i64 1
-  %tmp13761 = getelementptr inbounds float* %tmp13760, i64 1
-  %tmp13762 = getelementptr inbounds float* %tmp13761, i64 1
-  %tmp13763 = getelementptr inbounds float* %tmp13762, i64 1
-  %tmp13764 = getelementptr inbounds float* %tmp13763, i64 1
-  %tmp13765 = getelementptr inbounds float* %tmp13764, i64 1
-  %tmp13766 = getelementptr inbounds float* %tmp13765, i64 1
-  %tmp13767 = getelementptr inbounds float* %tmp13766, i64 1
-  %tmp13768 = getelementptr inbounds float* %tmp13767, i64 1
-  %tmp13769 = getelementptr inbounds float* %tmp13768, i64 1
-  %tmp13770 = getelementptr inbounds float* %tmp13769, i64 1
-  %tmp13771 = getelementptr inbounds float* %tmp13770, i64 1
-  %tmp13772 = getelementptr inbounds float* %tmp13771, i64 1
-  %tmp13773 = getelementptr inbounds float* %tmp13772, i64 1
-  %tmp13774 = getelementptr inbounds float* %tmp13773, i64 1
-  %tmp13775 = getelementptr inbounds float* %tmp13774, i64 1
-  %tmp13776 = getelementptr inbounds float* %tmp13775, i64 1
-  %tmp13777 = getelementptr inbounds float* %tmp13776, i64 1
-  %tmp13778 = getelementptr inbounds float* %tmp13777, i64 1
-  %tmp13779 = getelementptr inbounds float* %tmp13778, i64 1
-  %tmp13780 = getelementptr inbounds float* %tmp13779, i64 1
-  %tmp13781 = getelementptr inbounds float* %tmp13780, i64 1
-  %tmp13782 = getelementptr inbounds float* %tmp13781, i64 1
-  %tmp13783 = getelementptr inbounds float* %tmp13782, i64 1
-  %tmp13784 = getelementptr inbounds float* %tmp13783, i64 1
-  %tmp13785 = getelementptr inbounds float* %tmp13784, i64 1
-  %tmp13786 = getelementptr inbounds float* %tmp13785, i64 1
-  %tmp13787 = getelementptr inbounds float* %tmp13786, i64 1
-  %tmp13788 = getelementptr inbounds float* %tmp13787, i64 1
-  %tmp13789 = getelementptr inbounds float* %tmp13788, i64 1
-  %tmp13790 = getelementptr inbounds float* %tmp13789, i64 1
-  %tmp13791 = getelementptr inbounds float* %tmp13790, i64 1
-  %tmp13792 = getelementptr inbounds float* %tmp13791, i64 1
-  %tmp13793 = getelementptr inbounds float* %tmp13792, i64 1
-  %tmp13794 = getelementptr inbounds float* %tmp13793, i64 1
-  %tmp13795 = getelementptr inbounds float* %tmp13794, i64 1
-  %tmp13796 = getelementptr inbounds float* %tmp13795, i64 1
-  %tmp13797 = getelementptr inbounds float* %tmp13796, i64 1
-  %tmp13798 = getelementptr inbounds float* %tmp13797, i64 1
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-  %tmp13800 = getelementptr inbounds float* %tmp13799, i64 1
-  %tmp13801 = getelementptr inbounds float* %tmp13800, i64 1
-  %tmp13802 = getelementptr inbounds float* %tmp13801, i64 1
-  %tmp13803 = getelementptr inbounds float* %tmp13802, i64 1
-  %tmp13804 = getelementptr inbounds float* %tmp13803, i64 1
-  %tmp13805 = getelementptr inbounds float* %tmp13804, i64 1
-  %tmp13806 = getelementptr inbounds float* %tmp13805, i64 1
-  %tmp13807 = getelementptr inbounds float* %tmp13806, i64 1
-  %tmp13808 = getelementptr inbounds float* %tmp13807, i64 1
-  %tmp13809 = getelementptr inbounds float* %tmp13808, i64 1
-  %tmp13810 = getelementptr inbounds float* %tmp13809, i64 1
-  %tmp13811 = getelementptr inbounds float* %tmp13810, i64 1
-  %tmp13812 = getelementptr inbounds float* %tmp13811, i64 1
-  %tmp13813 = getelementptr inbounds float* %tmp13812, i64 1
-  %tmp13814 = getelementptr inbounds float* %tmp13813, i64 1
-  %tmp13815 = getelementptr inbounds float* %tmp13814, i64 1
-  %tmp13816 = getelementptr inbounds float* %tmp13815, i64 1
-  %tmp13817 = getelementptr inbounds float* %tmp13816, i64 1
-  %tmp13818 = getelementptr inbounds float* %tmp13817, i64 1
-  %tmp13819 = getelementptr inbounds float* %tmp13818, i64 1
-  %tmp13820 = getelementptr inbounds float* %tmp13819, i64 1
-  %tmp13821 = getelementptr inbounds float* %tmp13820, i64 1
-  %tmp13822 = getelementptr inbounds float* %tmp13821, i64 1
-  %tmp13823 = getelementptr inbounds float* %tmp13822, i64 1
-  %tmp13824 = getelementptr inbounds float* %tmp13823, i64 1
-  %tmp13825 = getelementptr inbounds float* %tmp13824, i64 1
-  %tmp13826 = getelementptr inbounds float* %tmp13825, i64 1
-  %tmp13827 = getelementptr inbounds float* %tmp13826, i64 1
-  %tmp13828 = getelementptr inbounds float* %tmp13827, i64 1
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-  %tmp13831 = getelementptr inbounds float* %tmp13830, i64 1
-  %tmp13832 = getelementptr inbounds float* %tmp13831, i64 1
-  %tmp13833 = getelementptr inbounds float* %tmp13832, i64 1
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-  %tmp13836 = getelementptr inbounds float* %tmp13835, i64 1
-  %tmp13837 = getelementptr inbounds float* %tmp13836, i64 1
-  %tmp13838 = getelementptr inbounds float* %tmp13837, i64 1
-  %tmp13839 = getelementptr inbounds float* %tmp13838, i64 1
-  %tmp13840 = getelementptr inbounds float* %tmp13839, i64 1
-  %tmp13841 = getelementptr inbounds float* %tmp13840, i64 1
-  %tmp13842 = getelementptr inbounds float* %tmp13841, i64 1
-  %tmp13843 = getelementptr inbounds float* %tmp13842, i64 1
-  %tmp13844 = getelementptr inbounds float* %tmp13843, i64 1
-  %tmp13845 = getelementptr inbounds float* %tmp13844, i64 1
-  %tmp13846 = getelementptr inbounds float* %tmp13845, i64 1
-  %tmp13847 = getelementptr inbounds float* %tmp13846, i64 1
-  %tmp13848 = getelementptr inbounds float* %tmp13847, i64 1
-  %tmp13849 = getelementptr inbounds float* %tmp13848, i64 1
-  %tmp13850 = getelementptr inbounds float* %tmp13849, i64 1
-  %tmp13851 = getelementptr inbounds float* %tmp13850, i64 1
-  %tmp13852 = getelementptr inbounds float* %tmp13851, i64 1
-  %tmp13853 = getelementptr inbounds float* %tmp13852, i64 1
-  %tmp13854 = getelementptr inbounds float* %tmp13853, i64 1
-  %tmp13855 = getelementptr inbounds float* %tmp13854, i64 1
-  %tmp13856 = getelementptr inbounds float* %tmp13855, i64 1
-  %tmp13857 = getelementptr inbounds float* %tmp13856, i64 1
-  %tmp13858 = getelementptr inbounds float* %tmp13857, i64 1
-  %tmp13859 = getelementptr inbounds float* %tmp13858, i64 1
-  %tmp13860 = getelementptr inbounds float* %tmp13859, i64 1
-  %tmp13861 = getelementptr inbounds float* %tmp13860, i64 1
-  %tmp13862 = getelementptr inbounds float* %tmp13861, i64 1
-  %tmp13863 = getelementptr inbounds float* %tmp13862, i64 1
-  %tmp13864 = getelementptr inbounds float* %tmp13863, i64 1
-  %tmp13865 = getelementptr inbounds float* %tmp13864, i64 1
-  %tmp13866 = getelementptr inbounds float* %tmp13865, i64 1
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-  %tmp13868 = getelementptr inbounds float* %tmp13867, i64 1
-  %tmp13869 = getelementptr inbounds float* %tmp13868, i64 1
-  %tmp13870 = getelementptr inbounds float* %tmp13869, i64 1
-  %tmp13871 = getelementptr inbounds float* %tmp13870, i64 1
-  %tmp13872 = getelementptr inbounds float* %tmp13871, i64 1
-  %tmp13873 = getelementptr inbounds float* %tmp13872, i64 1
-  %tmp13874 = getelementptr inbounds float* %tmp13873, i64 1
-  %tmp13875 = getelementptr inbounds float* %tmp13874, i64 1
-  %tmp13876 = getelementptr inbounds float* %tmp13875, i64 1
-  %tmp13877 = getelementptr inbounds float* %tmp13876, i64 1
-  %tmp13878 = getelementptr inbounds float* %tmp13877, i64 1
-  %tmp13879 = getelementptr inbounds float* %tmp13878, i64 1
-  %tmp13880 = getelementptr inbounds float* %tmp13879, i64 1
-  %tmp13881 = getelementptr inbounds float* %tmp13880, i64 1
-  %tmp13882 = getelementptr inbounds float* %tmp13881, i64 1
-  %tmp13883 = getelementptr inbounds float* %tmp13882, i64 1
-  %tmp13884 = getelementptr inbounds float* %tmp13883, i64 1
-  %tmp13885 = getelementptr inbounds float* %tmp13884, i64 1
-  %tmp13886 = getelementptr inbounds float* %tmp13885, i64 1
-  %tmp13887 = getelementptr inbounds float* %tmp13886, i64 1
-  %tmp13888 = getelementptr inbounds float* %tmp13887, i64 1
-  %tmp13889 = getelementptr inbounds float* %tmp13888, i64 1
-  %tmp13890 = getelementptr inbounds float* %tmp13889, i64 1
-  %tmp13891 = getelementptr inbounds float* %tmp13890, i64 1
-  %tmp13892 = getelementptr inbounds float* %tmp13891, i64 1
-  %tmp13893 = getelementptr inbounds float* %tmp13892, i64 1
-  %tmp13894 = getelementptr inbounds float* %tmp13893, i64 1
-  %tmp13895 = getelementptr inbounds float* %tmp13894, i64 1
-  %tmp13896 = getelementptr inbounds float* %tmp13895, i64 1
-  %tmp13897 = getelementptr inbounds float* %tmp13896, i64 1
-  %tmp13898 = getelementptr inbounds float* %tmp13897, i64 1
-  %tmp13899 = getelementptr inbounds float* %tmp13898, i64 1
-  %tmp13900 = getelementptr inbounds float* %tmp13899, i64 1
-  %tmp13901 = getelementptr inbounds float* %tmp13900, i64 1
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-  %tmp13911 = getelementptr inbounds float* %tmp13910, i64 1
-  %tmp13912 = getelementptr inbounds float* %tmp13911, i64 1
-  %tmp13913 = getelementptr inbounds float* %tmp13912, i64 1
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-  %tmp13916 = getelementptr inbounds float* %tmp13915, i64 1
-  %tmp13917 = getelementptr inbounds float* %tmp13916, i64 1
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-  %tmp13921 = getelementptr inbounds float* %tmp13920, i64 1
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-  %tmp14647 = getelementptr inbounds float* %tmp14646, i64 1
-  %tmp14648 = getelementptr inbounds float* %tmp14647, i64 1
-  %tmp14649 = getelementptr inbounds float* %tmp14648, i64 1
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-  %tmp14651 = getelementptr inbounds float* %tmp14650, i64 1
-  %tmp14652 = getelementptr inbounds float* %tmp14651, i64 1
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-  %tmp14654 = getelementptr inbounds float* %tmp14653, i64 1
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-  %tmp14658 = getelementptr inbounds float* %tmp14657, i64 1
-  %tmp14659 = getelementptr inbounds float* %tmp14658, i64 1
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-  %tmp14662 = getelementptr inbounds float* %tmp14661, i64 1
-  %tmp14663 = getelementptr inbounds float* %tmp14662, i64 1
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-  %tmp14666 = getelementptr inbounds float* %tmp14665, i64 1
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-  %tmp14688 = getelementptr inbounds float* %tmp14687, i64 1
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-  %tmp14692 = getelementptr inbounds float* %tmp14691, i64 1
-  %tmp14693 = getelementptr inbounds float* %tmp14692, i64 1
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-  %tmp14717 = getelementptr inbounds float* %tmp14716, i64 1
-  %tmp14718 = getelementptr inbounds float* %tmp14717, i64 1
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-  %tmp14721 = getelementptr inbounds float* %tmp14720, i64 1
-  %tmp14722 = getelementptr inbounds float* %tmp14721, i64 1
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-  %tmp14724 = getelementptr inbounds float* %tmp14723, i64 1
-  %tmp14725 = getelementptr inbounds float* %tmp14724, i64 1
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-  %tmp14739 = getelementptr inbounds float* %tmp14738, i64 1
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-  %tmp14742 = getelementptr inbounds float* %tmp14741, i64 1
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-  %tmp14746 = getelementptr inbounds float* %tmp14745, i64 1
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-  %tmp14758 = getelementptr inbounds float* %tmp14757, i64 1
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-  %tmp14793 = getelementptr inbounds float* %tmp14792, i64 1
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-  %tmp14986 = getelementptr inbounds float* %tmp14985, i64 1
-  %tmp14987 = getelementptr inbounds float* %tmp14986, i64 1
-  %tmp14988 = getelementptr inbounds float* %tmp14987, i64 1
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-  %tmp14990 = getelementptr inbounds float* %tmp14989, i64 1
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-  %tmp14992 = getelementptr inbounds float* %tmp14991, i64 1
-  %tmp14993 = getelementptr inbounds float* %tmp14992, i64 1
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-  %tmp16003 = getelementptr inbounds float* %tmp16002, i64 1
-  %tmp16004 = getelementptr inbounds float* %tmp16003, i64 1
-  %tmp16005 = getelementptr inbounds float* %tmp16004, i64 1
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-  %tmp16008 = getelementptr inbounds float* %tmp16007, i64 1
-  %tmp16009 = getelementptr inbounds float* %tmp16008, i64 1
-  %tmp16010 = getelementptr inbounds float* %tmp16009, i64 1
-  %tmp16011 = getelementptr inbounds float* %tmp16010, i64 1
-  %tmp16012 = getelementptr inbounds float* %tmp16011, i64 1
-  %tmp16013 = getelementptr inbounds float* %tmp16012, i64 1
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-  %tmp16015 = getelementptr inbounds float* %tmp16014, i64 1
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-  %tmp16017 = getelementptr inbounds float* %tmp16016, i64 1
-  %tmp16018 = getelementptr inbounds float* %tmp16017, i64 1
-  %tmp16019 = getelementptr inbounds float* %tmp16018, i64 1
-  %tmp16020 = getelementptr inbounds float* %tmp16019, i64 1
-  %tmp16021 = getelementptr inbounds float* %tmp16020, i64 1
-  %tmp16022 = getelementptr inbounds float* %tmp16021, i64 1
-  %tmp16023 = getelementptr inbounds float* %tmp16022, i64 1
-  %tmp16024 = getelementptr inbounds float* %tmp16023, i64 1
-  %tmp16025 = getelementptr inbounds float* %tmp16024, i64 1
-  %tmp16026 = getelementptr inbounds float* %tmp16025, i64 1
-  %tmp16027 = getelementptr inbounds float* %tmp16026, i64 1
-  %tmp16028 = getelementptr inbounds float* %tmp16027, i64 1
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-  %tmp16030 = getelementptr inbounds float* %tmp16029, i64 1
-  %tmp16031 = getelementptr inbounds float* %tmp16030, i64 1
-  %tmp16032 = getelementptr inbounds float* %tmp16031, i64 1
-  %tmp16033 = getelementptr inbounds float* %tmp16032, i64 1
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-  %tmp16037 = getelementptr inbounds float* %tmp16036, i64 1
-  %tmp16038 = getelementptr inbounds float* %tmp16037, i64 1
-  %tmp16039 = getelementptr inbounds float* %tmp16038, i64 1
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-  %tmp16042 = getelementptr inbounds float* %tmp16041, i64 1
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-  %tmp16044 = getelementptr inbounds float* %tmp16043, i64 1
-  %tmp16045 = getelementptr inbounds float* %tmp16044, i64 1
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-  %tmp16049 = getelementptr inbounds float* %tmp16048, i64 1
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-  %tmp16052 = getelementptr inbounds float* %tmp16051, i64 1
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-  %tmp16072 = getelementptr inbounds float* %tmp16071, i64 1
-  %tmp16073 = getelementptr inbounds float* %tmp16072, i64 1
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-  %tmp16075 = getelementptr inbounds float* %tmp16074, i64 1
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-  %tmp16078 = getelementptr inbounds float* %tmp16077, i64 1
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-  %tmp16080 = getelementptr inbounds float* %tmp16079, i64 1
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-  %tmp16085 = getelementptr inbounds float* %tmp16084, i64 1
-  %tmp16086 = getelementptr inbounds float* %tmp16085, i64 1
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-  %tmp16088 = getelementptr inbounds float* %tmp16087, i64 1
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-  %tmp16090 = getelementptr inbounds float* %tmp16089, i64 1
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-  %tmp16093 = getelementptr inbounds float* %tmp16092, i64 1
-  %tmp16094 = getelementptr inbounds float* %tmp16093, i64 1
-  %tmp16095 = getelementptr inbounds float* %tmp16094, i64 1
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-  %tmp16100 = getelementptr inbounds float* %tmp16099, i64 1
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-  %tmp16119 = getelementptr inbounds float* %tmp16118, i64 1
-  %tmp16120 = getelementptr inbounds float* %tmp16119, i64 1
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-  %tmp16213 = getelementptr inbounds float* %tmp16212, i64 1
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-  %tmp16215 = getelementptr inbounds float* %tmp16214, i64 1
-  %tmp16216 = getelementptr inbounds float* %tmp16215, i64 1
-  %tmp16217 = getelementptr inbounds float* %tmp16216, i64 1
-  %tmp16218 = getelementptr inbounds float* %tmp16217, i64 1
-  %tmp16219 = getelementptr inbounds float* %tmp16218, i64 1
-  %tmp16220 = getelementptr inbounds float* %tmp16219, i64 1
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-  %tmp17019 = getelementptr inbounds float* %tmp17018, i64 1
-  %tmp17020 = getelementptr inbounds float* %tmp17019, i64 1
-  %tmp17021 = getelementptr inbounds float* %tmp17020, i64 1
-  %tmp17022 = getelementptr inbounds float* %tmp17021, i64 1
-  %tmp17023 = getelementptr inbounds float* %tmp17022, i64 1
-  %tmp17024 = getelementptr inbounds float* %tmp17023, i64 1
-  %tmp17025 = getelementptr inbounds float* %tmp17024, i64 1
-  %tmp17026 = getelementptr inbounds float* %tmp17025, i64 1
-  %tmp17027 = getelementptr inbounds float* %tmp17026, i64 1
-  %tmp17028 = getelementptr inbounds float* %tmp17027, i64 1
-  %tmp17029 = getelementptr inbounds float* %tmp17028, i64 1
-  %tmp17030 = getelementptr inbounds float* %tmp17029, i64 1
-  %tmp17031 = getelementptr inbounds float* %tmp17030, i64 1
-  %tmp17032 = getelementptr inbounds float* %tmp17031, i64 1
-  %tmp17033 = getelementptr inbounds float* %tmp17032, i64 1
-  %tmp17034 = getelementptr inbounds float* %tmp17033, i64 1
-  %tmp17035 = getelementptr inbounds float* %tmp17034, i64 1
-  %tmp17036 = getelementptr inbounds float* %tmp17035, i64 1
-  %tmp17037 = getelementptr inbounds float* %tmp17036, i64 1
-  %tmp17038 = getelementptr inbounds float* %tmp17037, i64 1
-  %tmp17039 = getelementptr inbounds float* %tmp17038, i64 1
-  %tmp17040 = getelementptr inbounds float* %tmp17039, i64 1
-  %tmp17041 = getelementptr inbounds float* %tmp17040, i64 1
-  %tmp17042 = getelementptr inbounds float* %tmp17041, i64 1
-  %tmp17043 = getelementptr inbounds float* %tmp17042, i64 1
-  %tmp17044 = getelementptr inbounds float* %tmp17043, i64 1
-  %tmp17045 = getelementptr inbounds float* %tmp17044, i64 1
-  %tmp17046 = getelementptr inbounds float* %tmp17045, i64 1
-  %tmp17047 = getelementptr inbounds float* %tmp17046, i64 1
-  %tmp17048 = getelementptr inbounds float* %tmp17047, i64 1
-  %tmp17049 = getelementptr inbounds float* %tmp17048, i64 1
-  %tmp17050 = getelementptr inbounds float* %tmp17049, i64 1
-  %tmp17051 = getelementptr inbounds float* %tmp17050, i64 1
-  %tmp17052 = getelementptr inbounds float* %tmp17051, i64 1
-  %tmp17053 = getelementptr inbounds float* %tmp17052, i64 1
-  %tmp17054 = getelementptr inbounds float* %tmp17053, i64 1
-  %tmp17055 = getelementptr inbounds float* %tmp17054, i64 1
-  %tmp17056 = getelementptr inbounds float* %tmp17055, i64 1
-  %tmp17057 = getelementptr inbounds float* %tmp17056, i64 1
-  %tmp17058 = getelementptr inbounds float* %tmp17057, i64 1
-  %tmp17059 = getelementptr inbounds float* %tmp17058, i64 1
-  %tmp17060 = getelementptr inbounds float* %tmp17059, i64 1
-  %tmp17061 = getelementptr inbounds float* %tmp17060, i64 1
-  %tmp17062 = getelementptr inbounds float* %tmp17061, i64 1
-  %tmp17063 = getelementptr inbounds float* %tmp17062, i64 1
-  %tmp17064 = getelementptr inbounds float* %tmp17063, i64 1
-  %tmp17065 = getelementptr inbounds float* %tmp17064, i64 1
-  %tmp17066 = getelementptr inbounds float* %tmp17065, i64 1
-  %tmp17067 = getelementptr inbounds float* %tmp17066, i64 1
-  %tmp17068 = getelementptr inbounds float* %tmp17067, i64 1
-  %tmp17069 = getelementptr inbounds float* %tmp17068, i64 1
-  %tmp17070 = getelementptr inbounds float* %tmp17069, i64 1
-  %tmp17071 = getelementptr inbounds float* %tmp17070, i64 1
-  %tmp17072 = getelementptr inbounds float* %tmp17071, i64 1
-  %tmp17073 = getelementptr inbounds float* %tmp17072, i64 1
-  %tmp17074 = getelementptr inbounds float* %tmp17073, i64 1
-  %tmp17075 = getelementptr inbounds float* %tmp17074, i64 1
-  %tmp17076 = getelementptr inbounds float* %tmp17075, i64 1
-  %tmp17077 = getelementptr inbounds float* %tmp17076, i64 1
-  %tmp17078 = getelementptr inbounds float* %tmp17077, i64 1
-  %tmp17079 = getelementptr inbounds float* %tmp17078, i64 1
-  %tmp17080 = getelementptr inbounds float* %tmp17079, i64 1
-  %tmp17081 = getelementptr inbounds float* %tmp17080, i64 1
-  %tmp17082 = getelementptr inbounds float* %tmp17081, i64 1
-  %tmp17083 = getelementptr inbounds float* %tmp17082, i64 1
-  %tmp17084 = getelementptr inbounds float* %tmp17083, i64 1
-  %tmp17085 = getelementptr inbounds float* %tmp17084, i64 1
-  %tmp17086 = getelementptr inbounds float* %tmp17085, i64 1
-  %tmp17087 = getelementptr inbounds float* %tmp17086, i64 1
-  %tmp17088 = getelementptr inbounds float* %tmp17087, i64 1
-  %tmp17089 = getelementptr inbounds float* %tmp17088, i64 1
-  %tmp17090 = getelementptr inbounds float* %tmp17089, i64 1
-  %tmp17091 = getelementptr inbounds float* %tmp17090, i64 1
-  %tmp17092 = getelementptr inbounds float* %tmp17091, i64 1
-  %tmp17093 = getelementptr inbounds float* %tmp17092, i64 1
-  %tmp17094 = getelementptr inbounds float* %tmp17093, i64 1
-  %tmp17095 = getelementptr inbounds float* %tmp17094, i64 1
-  %tmp17096 = getelementptr inbounds float* %tmp17095, i64 1
-  %tmp17097 = getelementptr inbounds float* %tmp17096, i64 1
-  %tmp17098 = getelementptr inbounds float* %tmp17097, i64 1
-  %tmp17099 = getelementptr inbounds float* %tmp17098, i64 1
-  %tmp17100 = getelementptr inbounds float* %tmp17099, i64 1
-  %tmp17101 = getelementptr inbounds float* %tmp17100, i64 1
-  %tmp17102 = getelementptr inbounds float* %tmp17101, i64 1
-  %tmp17103 = getelementptr inbounds float* %tmp17102, i64 1
-  %tmp17104 = getelementptr inbounds float* %tmp17103, i64 1
-  %tmp17105 = getelementptr inbounds float* %tmp17104, i64 1
-  %tmp17106 = getelementptr inbounds float* %tmp17105, i64 1
-  %tmp17107 = getelementptr inbounds float* %tmp17106, i64 1
-  %tmp17108 = getelementptr inbounds float* %tmp17107, i64 1
-  %tmp17109 = getelementptr inbounds float* %tmp17108, i64 1
-  %tmp17110 = getelementptr inbounds float* %tmp17109, i64 1
-  %tmp17111 = getelementptr inbounds float* %tmp17110, i64 1
-  %tmp17112 = getelementptr inbounds float* %tmp17111, i64 1
-  %tmp17113 = getelementptr inbounds float* %tmp17112, i64 1
-  %tmp17114 = getelementptr inbounds float* %tmp17113, i64 1
-  %tmp17115 = getelementptr inbounds float* %tmp17114, i64 1
-  %tmp17116 = getelementptr inbounds float* %tmp17115, i64 1
-  %tmp17117 = getelementptr inbounds float* %tmp17116, i64 1
-  %tmp17118 = getelementptr inbounds float* %tmp17117, i64 1
-  %tmp17119 = getelementptr inbounds float* %tmp17118, i64 1
-  %tmp17120 = getelementptr inbounds float* %tmp17119, i64 1
-  %tmp17121 = getelementptr inbounds float* %tmp17120, i64 1
-  %tmp17122 = getelementptr inbounds float* %tmp17121, i64 1
-  %tmp17123 = getelementptr inbounds float* %tmp17122, i64 1
-  %tmp17124 = getelementptr inbounds float* %tmp17123, i64 1
-  %tmp17125 = getelementptr inbounds float* %tmp17124, i64 1
-  %tmp17126 = getelementptr inbounds float* %tmp17125, i64 1
-  %tmp17127 = getelementptr inbounds float* %tmp17126, i64 1
-  %tmp17128 = getelementptr inbounds float* %tmp17127, i64 1
-  %tmp17129 = getelementptr inbounds float* %tmp17128, i64 1
-  %tmp17130 = getelementptr inbounds float* %tmp17129, i64 1
-  %tmp17131 = getelementptr inbounds float* %tmp17130, i64 1
-  %tmp17132 = getelementptr inbounds float* %tmp17131, i64 1
-  %tmp17133 = getelementptr inbounds float* %tmp17132, i64 1
-  %tmp17134 = getelementptr inbounds float* %tmp17133, i64 1
-  %tmp17135 = getelementptr inbounds float* %tmp17134, i64 1
-  %tmp17136 = getelementptr inbounds float* %tmp17135, i64 1
-  %tmp17137 = getelementptr inbounds float* %tmp17136, i64 1
-  %tmp17138 = getelementptr inbounds float* %tmp17137, i64 1
-  %tmp17139 = getelementptr inbounds float* %tmp17138, i64 1
-  %tmp17140 = getelementptr inbounds float* %tmp17139, i64 1
-  %tmp17141 = getelementptr inbounds float* %tmp17140, i64 1
-  %tmp17142 = getelementptr inbounds float* %tmp17141, i64 1
-  %tmp17143 = getelementptr inbounds float* %tmp17142, i64 1
-  %tmp17144 = getelementptr inbounds float* %tmp17143, i64 1
-  %tmp17145 = getelementptr inbounds float* %tmp17144, i64 1
-  %tmp17146 = getelementptr inbounds float* %tmp17145, i64 1
-  %tmp17147 = getelementptr inbounds float* %tmp17146, i64 1
-  %tmp17148 = getelementptr inbounds float* %tmp17147, i64 1
-  %tmp17149 = getelementptr inbounds float* %tmp17148, i64 1
-  %tmp17150 = getelementptr inbounds float* %tmp17149, i64 1
-  %tmp17151 = getelementptr inbounds float* %tmp17150, i64 1
-  %tmp17152 = getelementptr inbounds float* %tmp17151, i64 1
-  %tmp17153 = getelementptr inbounds float* %tmp17152, i64 1
-  %tmp17154 = getelementptr inbounds float* %tmp17153, i64 1
-  %tmp17155 = getelementptr inbounds float* %tmp17154, i64 1
-  %tmp17156 = getelementptr inbounds float* %tmp17155, i64 1
-  %tmp17157 = getelementptr inbounds float* %tmp17156, i64 1
-  %tmp17158 = getelementptr inbounds float* %tmp17157, i64 1
-  %tmp17159 = getelementptr inbounds float* %tmp17158, i64 1
-  %tmp17160 = getelementptr inbounds float* %tmp17159, i64 1
-  %tmp17161 = getelementptr inbounds float* %tmp17160, i64 1
-  %tmp17162 = getelementptr inbounds float* %tmp17161, i64 1
-  %tmp17163 = getelementptr inbounds float* %tmp17162, i64 1
-  %tmp17164 = getelementptr inbounds float* %tmp17163, i64 1
-  %tmp17165 = getelementptr inbounds float* %tmp17164, i64 1
-  %tmp17166 = getelementptr inbounds float* %tmp17165, i64 1
-  %tmp17167 = getelementptr inbounds float* %tmp17166, i64 1
-  %tmp17168 = getelementptr inbounds float* %tmp17167, i64 1
-  %tmp17169 = getelementptr inbounds float* %tmp17168, i64 1
-  %tmp17170 = getelementptr inbounds float* %tmp17169, i64 1
-  %tmp17171 = getelementptr inbounds float* %tmp17170, i64 1
-  %tmp17172 = getelementptr inbounds float* %tmp17171, i64 1
-  %tmp17173 = getelementptr inbounds float* %tmp17172, i64 1
-  %tmp17174 = getelementptr inbounds float* %tmp17173, i64 1
-  %tmp17175 = getelementptr inbounds float* %tmp17174, i64 1
-  %tmp17176 = getelementptr inbounds float* %tmp17175, i64 1
-  %tmp17177 = getelementptr inbounds float* %tmp17176, i64 1
-  %tmp17178 = getelementptr inbounds float* %tmp17177, i64 1
-  %tmp17179 = getelementptr inbounds float* %tmp17178, i64 1
-  %tmp17180 = getelementptr inbounds float* %tmp17179, i64 1
-  %tmp17181 = getelementptr inbounds float* %tmp17180, i64 1
-  %tmp17182 = getelementptr inbounds float* %tmp17181, i64 1
-  %tmp17183 = getelementptr inbounds float* %tmp17182, i64 1
-  %tmp17184 = getelementptr inbounds float* %tmp17183, i64 1
-  %tmp17185 = getelementptr inbounds float* %tmp17184, i64 1
-  %tmp17186 = getelementptr inbounds float* %tmp17185, i64 1
-  %tmp17187 = getelementptr inbounds float* %tmp17186, i64 1
-  %tmp17188 = getelementptr inbounds float* %tmp17187, i64 1
-  %tmp17189 = getelementptr inbounds float* %tmp17188, i64 1
-  %tmp17190 = getelementptr inbounds float* %tmp17189, i64 1
-  %tmp17191 = getelementptr inbounds float* %tmp17190, i64 1
-  %tmp17192 = getelementptr inbounds float* %tmp17191, i64 1
-  %tmp17193 = getelementptr inbounds float* %tmp17192, i64 1
-  %tmp17194 = getelementptr inbounds float* %tmp17193, i64 1
-  %tmp17195 = getelementptr inbounds float* %tmp17194, i64 1
-  %tmp17196 = getelementptr inbounds float* %tmp17195, i64 1
-  %tmp17197 = getelementptr inbounds float* %tmp17196, i64 1
-  %tmp17198 = getelementptr inbounds float* %tmp17197, i64 1
-  %tmp17199 = getelementptr inbounds float* %tmp17198, i64 1
-  %tmp17200 = getelementptr inbounds float* %tmp17199, i64 1
-  %tmp17201 = getelementptr inbounds float* %tmp17200, i64 1
-  %tmp17202 = getelementptr inbounds float* %tmp17201, i64 1
-  %tmp17203 = getelementptr inbounds float* %tmp17202, i64 1
-  %tmp17204 = getelementptr inbounds float* %tmp17203, i64 1
-  %tmp17205 = getelementptr inbounds float* %tmp17204, i64 1
-  %tmp17206 = getelementptr inbounds float* %tmp17205, i64 1
-  %tmp17207 = getelementptr inbounds float* %tmp17206, i64 1
-  %tmp17208 = getelementptr inbounds float* %tmp17207, i64 1
-  %tmp17209 = getelementptr inbounds float* %tmp17208, i64 1
-  %tmp17210 = getelementptr inbounds float* %tmp17209, i64 1
-  %tmp17211 = getelementptr inbounds float* %tmp17210, i64 1
-  %tmp17212 = getelementptr inbounds float* %tmp17211, i64 1
-  %tmp17213 = getelementptr inbounds float* %tmp17212, i64 1
-  %tmp17214 = getelementptr inbounds float* %tmp17213, i64 1
-  %tmp17215 = getelementptr inbounds float* %tmp17214, i64 1
-  %tmp17216 = getelementptr inbounds float* %tmp17215, i64 1
-  %tmp17217 = getelementptr inbounds float* %tmp17216, i64 1
-  %tmp17218 = getelementptr inbounds float* %tmp17217, i64 1
-  %tmp17219 = getelementptr inbounds float* %tmp17218, i64 1
-  %tmp17220 = getelementptr inbounds float* %tmp17219, i64 1
-  %tmp17221 = getelementptr inbounds float* %tmp17220, i64 1
-  %tmp17222 = getelementptr inbounds float* %tmp17221, i64 1
-  %tmp17223 = getelementptr inbounds float* %tmp17222, i64 1
-  %tmp17224 = getelementptr inbounds float* %tmp17223, i64 1
-  %tmp17225 = getelementptr inbounds float* %tmp17224, i64 1
-  %tmp17226 = getelementptr inbounds float* %tmp17225, i64 1
-  %tmp17227 = getelementptr inbounds float* %tmp17226, i64 1
-  %tmp17228 = getelementptr inbounds float* %tmp17227, i64 1
-  %tmp17229 = getelementptr inbounds float* %tmp17228, i64 1
-  %tmp17230 = getelementptr inbounds float* %tmp17229, i64 1
-  %tmp17231 = getelementptr inbounds float* %tmp17230, i64 1
-  %tmp17232 = getelementptr inbounds float* %tmp17231, i64 1
-  %tmp17233 = getelementptr inbounds float* %tmp17232, i64 1
-  %tmp17234 = getelementptr inbounds float* %tmp17233, i64 1
-  %tmp17235 = getelementptr inbounds float* %tmp17234, i64 1
-  %tmp17236 = getelementptr inbounds float* %tmp17235, i64 1
-  %tmp17237 = getelementptr inbounds float* %tmp17236, i64 1
-  %tmp17238 = getelementptr inbounds float* %tmp17237, i64 1
-  %tmp17239 = getelementptr inbounds float* %tmp17238, i64 1
-  %tmp17240 = getelementptr inbounds float* %tmp17239, i64 1
-  %tmp17241 = getelementptr inbounds float* %tmp17240, i64 1
-  %tmp17242 = getelementptr inbounds float* %tmp17241, i64 1
-  %tmp17243 = getelementptr inbounds float* %tmp17242, i64 1
-  %tmp17244 = getelementptr inbounds float* %tmp17243, i64 1
-  %tmp17245 = getelementptr inbounds float* %tmp17244, i64 1
-  %tmp17246 = getelementptr inbounds float* %tmp17245, i64 1
-  %tmp17247 = getelementptr inbounds float* %tmp17246, i64 1
-  %tmp17248 = getelementptr inbounds float* %tmp17247, i64 1
-  %tmp17249 = getelementptr inbounds float* %tmp17248, i64 1
-  %tmp17250 = getelementptr inbounds float* %tmp17249, i64 1
-  %tmp17251 = getelementptr inbounds float* %tmp17250, i64 1
-  %tmp17252 = getelementptr inbounds float* %tmp17251, i64 1
-  %tmp17253 = getelementptr inbounds float* %tmp17252, i64 1
-  %tmp17254 = getelementptr inbounds float* %tmp17253, i64 1
-  %tmp17255 = getelementptr inbounds float* %tmp17254, i64 1
-  %tmp17256 = getelementptr inbounds float* %tmp17255, i64 1
-  %tmp17257 = getelementptr inbounds float* %tmp17256, i64 1
-  %tmp17258 = getelementptr inbounds float* %tmp17257, i64 1
-  %tmp17259 = getelementptr inbounds float* %tmp17258, i64 1
-  %tmp17260 = getelementptr inbounds float* %tmp17259, i64 1
-  %tmp17261 = getelementptr inbounds float* %tmp17260, i64 1
-  %tmp17262 = getelementptr inbounds float* %tmp17261, i64 1
-  %tmp17263 = getelementptr inbounds float* %tmp17262, i64 1
-  %tmp17264 = getelementptr inbounds float* %tmp17263, i64 1
-  %tmp17265 = getelementptr inbounds float* %tmp17264, i64 1
-  %tmp17266 = getelementptr inbounds float* %tmp17265, i64 1
-  %tmp17267 = getelementptr inbounds float* %tmp17266, i64 1
-  %tmp17268 = getelementptr inbounds float* %tmp17267, i64 1
-  %tmp17269 = getelementptr inbounds float* %tmp17268, i64 1
-  %tmp17270 = getelementptr inbounds float* %tmp17269, i64 1
-  %tmp17271 = getelementptr inbounds float* %tmp17270, i64 1
-  %tmp17272 = getelementptr inbounds float* %tmp17271, i64 1
-  %tmp17273 = getelementptr inbounds float* %tmp17272, i64 1
-  %tmp17274 = getelementptr inbounds float* %tmp17273, i64 1
-  %tmp17275 = getelementptr inbounds float* %tmp17274, i64 1
-  %tmp17276 = getelementptr inbounds float* %tmp17275, i64 1
-  %tmp17277 = getelementptr inbounds float* %tmp17276, i64 1
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-  %tmp17280 = getelementptr inbounds float* %tmp17279, i64 1
-  %tmp17281 = getelementptr inbounds float* %tmp17280, i64 1
-  %tmp17282 = getelementptr inbounds float* %tmp17281, i64 1
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-  %tmp17284 = getelementptr inbounds float* %tmp17283, i64 1
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-  %tmp17287 = getelementptr inbounds float* %tmp17286, i64 1
-  %tmp17288 = getelementptr inbounds float* %tmp17287, i64 1
-  %tmp17289 = getelementptr inbounds float* %tmp17288, i64 1
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-  %tmp17292 = getelementptr inbounds float* %tmp17291, i64 1
-  %tmp17293 = getelementptr inbounds float* %tmp17292, i64 1
-  %tmp17294 = getelementptr inbounds float* %tmp17293, i64 1
-  %tmp17295 = getelementptr inbounds float* %tmp17294, i64 1
-  %tmp17296 = getelementptr inbounds float* %tmp17295, i64 1
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-  %tmp17299 = getelementptr inbounds float* %tmp17298, i64 1
-  %tmp17300 = getelementptr inbounds float* %tmp17299, i64 1
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-  %tmp17302 = getelementptr inbounds float* %tmp17301, i64 1
-  %tmp17303 = getelementptr inbounds float* %tmp17302, i64 1
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-  %tmp17311 = getelementptr inbounds float* %tmp17310, i64 1
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-  %tmp17313 = getelementptr inbounds float* %tmp17312, i64 1
-  %tmp17314 = getelementptr inbounds float* %tmp17313, i64 1
-  %tmp17315 = getelementptr inbounds float* %tmp17314, i64 1
-  %tmp17316 = getelementptr inbounds float* %tmp17315, i64 1
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-  %tmp17318 = getelementptr inbounds float* %tmp17317, i64 1
-  %tmp17319 = getelementptr inbounds float* %tmp17318, i64 1
-  %tmp17320 = getelementptr inbounds float* %tmp17319, i64 1
-  %tmp17321 = getelementptr inbounds float* %tmp17320, i64 1
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-  %tmp17324 = getelementptr inbounds float* %tmp17323, i64 1
-  %tmp17325 = getelementptr inbounds float* %tmp17324, i64 1
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-  %tmp17328 = getelementptr inbounds float* %tmp17327, i64 1
-  %tmp17329 = getelementptr inbounds float* %tmp17328, i64 1
-  %tmp17330 = getelementptr inbounds float* %tmp17329, i64 1
-  %tmp17331 = getelementptr inbounds float* %tmp17330, i64 1
-  %tmp17332 = getelementptr inbounds float* %tmp17331, i64 1
-  %tmp17333 = getelementptr inbounds float* %tmp17332, i64 1
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-  %tmp17338 = getelementptr inbounds float* %tmp17337, i64 1
-  %tmp17339 = getelementptr inbounds float* %tmp17338, i64 1
-  %tmp17340 = getelementptr inbounds float* %tmp17339, i64 1
-  %tmp17341 = getelementptr inbounds float* %tmp17340, i64 1
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-  %tmp17348 = getelementptr inbounds float* %tmp17347, i64 1
-  %tmp17349 = getelementptr inbounds float* %tmp17348, i64 1
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-  %tmp17352 = getelementptr inbounds float* %tmp17351, i64 1
-  %tmp17353 = getelementptr inbounds float* %tmp17352, i64 1
-  %tmp17354 = getelementptr inbounds float* %tmp17353, i64 1
-  %tmp17355 = getelementptr inbounds float* %tmp17354, i64 1
-  %tmp17356 = getelementptr inbounds float* %tmp17355, i64 1
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-  %tmp17358 = getelementptr inbounds float* %tmp17357, i64 1
-  %tmp17359 = getelementptr inbounds float* %tmp17358, i64 1
-  %tmp17360 = getelementptr inbounds float* %tmp17359, i64 1
-  %tmp17361 = getelementptr inbounds float* %tmp17360, i64 1
-  %tmp17362 = getelementptr inbounds float* %tmp17361, i64 1
-  %tmp17363 = getelementptr inbounds float* %tmp17362, i64 1
-  %tmp17364 = getelementptr inbounds float* %tmp17363, i64 1
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-  %tmp17366 = getelementptr inbounds float* %tmp17365, i64 1
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-  %tmp17368 = getelementptr inbounds float* %tmp17367, i64 1
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-  %tmp17371 = getelementptr inbounds float* %tmp17370, i64 1
-  %tmp17372 = getelementptr inbounds float* %tmp17371, i64 1
-  %tmp17373 = getelementptr inbounds float* %tmp17372, i64 1
-  %tmp17374 = getelementptr inbounds float* %tmp17373, i64 1
-  %tmp17375 = getelementptr inbounds float* %tmp17374, i64 1
-  %tmp17376 = getelementptr inbounds float* %tmp17375, i64 1
-  %tmp17377 = getelementptr inbounds float* %tmp17376, i64 1
-  %tmp17378 = getelementptr inbounds float* %tmp17377, i64 1
-  %tmp17379 = getelementptr inbounds float* %tmp17378, i64 1
-  %tmp17380 = getelementptr inbounds float* %tmp17379, i64 1
-  %tmp17381 = getelementptr inbounds float* %tmp17380, i64 1
-  %tmp17382 = getelementptr inbounds float* %tmp17381, i64 1
-  %tmp17383 = getelementptr inbounds float* %tmp17382, i64 1
-  %tmp17384 = getelementptr inbounds float* %tmp17383, i64 1
-  %tmp17385 = getelementptr inbounds float* %tmp17384, i64 1
-  %tmp17386 = getelementptr inbounds float* %tmp17385, i64 1
-  %tmp17387 = getelementptr inbounds float* %tmp17386, i64 1
-  %tmp17388 = getelementptr inbounds float* %tmp17387, i64 1
-  %tmp17389 = getelementptr inbounds float* %tmp17388, i64 1
-  %tmp17390 = getelementptr inbounds float* %tmp17389, i64 1
-  %tmp17391 = getelementptr inbounds float* %tmp17390, i64 1
-  %tmp17392 = getelementptr inbounds float* %tmp17391, i64 1
-  %tmp17393 = getelementptr inbounds float* %tmp17392, i64 1
-  %tmp17394 = getelementptr inbounds float* %tmp17393, i64 1
-  %tmp17395 = getelementptr inbounds float* %tmp17394, i64 1
-  %tmp17396 = getelementptr inbounds float* %tmp17395, i64 1
-  %tmp17397 = getelementptr inbounds float* %tmp17396, i64 1
-  %tmp17398 = getelementptr inbounds float* %tmp17397, i64 1
-  %tmp17399 = getelementptr inbounds float* %tmp17398, i64 1
-  %tmp17400 = getelementptr inbounds float* %tmp17399, i64 1
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-  %tmp17402 = getelementptr inbounds float* %tmp17401, i64 1
-  %tmp17403 = getelementptr inbounds float* %tmp17402, i64 1
-  %tmp17404 = getelementptr inbounds float* %tmp17403, i64 1
-  %tmp17405 = getelementptr inbounds float* %tmp17404, i64 1
-  %tmp17406 = getelementptr inbounds float* %tmp17405, i64 1
-  %tmp17407 = getelementptr inbounds float* %tmp17406, i64 1
-  %tmp17408 = getelementptr inbounds float* %tmp17407, i64 1
-  %tmp17409 = getelementptr inbounds float* %tmp17408, i64 1
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-  %tmp17414 = getelementptr inbounds float* %tmp17413, i64 1
-  %tmp17415 = getelementptr inbounds float* %tmp17414, i64 1
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-  %tmp17417 = getelementptr inbounds float* %tmp17416, i64 1
-  %tmp17418 = getelementptr inbounds float* %tmp17417, i64 1
-  %tmp17419 = getelementptr inbounds float* %tmp17418, i64 1
-  %tmp17420 = getelementptr inbounds float* %tmp17419, i64 1
-  %tmp17421 = getelementptr inbounds float* %tmp17420, i64 1
-  %tmp17422 = getelementptr inbounds float* %tmp17421, i64 1
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-  %tmp17424 = getelementptr inbounds float* %tmp17423, i64 1
-  %tmp17425 = getelementptr inbounds float* %tmp17424, i64 1
-  %tmp17426 = getelementptr inbounds float* %tmp17425, i64 1
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-  %tmp17429 = getelementptr inbounds float* %tmp17428, i64 1
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-  %tmp17436 = getelementptr inbounds float* %tmp17435, i64 1
-  %tmp17437 = getelementptr inbounds float* %tmp17436, i64 1
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-  %tmp17442 = getelementptr inbounds float* %tmp17441, i64 1
-  %tmp17443 = getelementptr inbounds float* %tmp17442, i64 1
-  %tmp17444 = getelementptr inbounds float* %tmp17443, i64 1
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-  %tmp17446 = getelementptr inbounds float* %tmp17445, i64 1
-  %tmp17447 = getelementptr inbounds float* %tmp17446, i64 1
-  %tmp17448 = getelementptr inbounds float* %tmp17447, i64 1
-  %tmp17449 = getelementptr inbounds float* %tmp17448, i64 1
-  %tmp17450 = getelementptr inbounds float* %tmp17449, i64 1
-  %tmp17451 = getelementptr inbounds float* %tmp17450, i64 1
-  %tmp17452 = getelementptr inbounds float* %tmp17451, i64 1
-  %tmp17453 = getelementptr inbounds float* %tmp17452, i64 1
-  %tmp17454 = getelementptr inbounds float* %tmp17453, i64 1
-  %tmp17455 = getelementptr inbounds float* %tmp17454, i64 1
-  %tmp17456 = getelementptr inbounds float* %tmp17455, i64 1
-  %tmp17457 = getelementptr inbounds float* %tmp17456, i64 1
-  %tmp17458 = getelementptr inbounds float* %tmp17457, i64 1
-  %tmp17459 = getelementptr inbounds float* %tmp17458, i64 1
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-  %tmp17461 = getelementptr inbounds float* %tmp17460, i64 1
-  %tmp17462 = getelementptr inbounds float* %tmp17461, i64 1
-  %tmp17463 = getelementptr inbounds float* %tmp17462, i64 1
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-  %tmp17476 = getelementptr inbounds float* %tmp17475, i64 1
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-  %tmp17498 = getelementptr inbounds float* %tmp17497, i64 1
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-  %tmp17695 = getelementptr inbounds float* %tmp17694, i64 1
-  %tmp17696 = getelementptr inbounds float* %tmp17695, i64 1
-  %tmp17697 = getelementptr inbounds float* %tmp17696, i64 1
-  %tmp17698 = getelementptr inbounds float* %tmp17697, i64 1
-  %tmp17699 = getelementptr inbounds float* %tmp17698, i64 1
-  %tmp17700 = getelementptr inbounds float* %tmp17699, i64 1
-  %tmp17701 = getelementptr inbounds float* %tmp17700, i64 1
-  %tmp17702 = getelementptr inbounds float* %tmp17701, i64 1
-  %tmp17703 = getelementptr inbounds float* %tmp17702, i64 1
-  %tmp17704 = getelementptr inbounds float* %tmp17703, i64 1
-  %tmp17705 = getelementptr inbounds float* %tmp17704, i64 1
-  %tmp17706 = getelementptr inbounds float* %tmp17705, i64 1
-  %tmp17707 = getelementptr inbounds float* %tmp17706, i64 1
-  %tmp17708 = getelementptr inbounds float* %tmp17707, i64 1
-  %tmp17709 = getelementptr inbounds float* %tmp17708, i64 1
-  %tmp17710 = getelementptr inbounds float* %tmp17709, i64 1
-  %tmp17711 = getelementptr inbounds float* %tmp17710, i64 1
-  %tmp17712 = getelementptr inbounds float* %tmp17711, i64 1
-  %tmp17713 = getelementptr inbounds float* %tmp17712, i64 1
-  %tmp17714 = getelementptr inbounds float* %tmp17713, i64 1
-  %tmp17715 = getelementptr inbounds float* %tmp17714, i64 1
-  %tmp17716 = getelementptr inbounds float* %tmp17715, i64 1
-  %tmp17717 = getelementptr inbounds float* %tmp17716, i64 1
-  %tmp17718 = getelementptr inbounds float* %tmp17717, i64 1
-  %tmp17719 = getelementptr inbounds float* %tmp17718, i64 1
-  %tmp17720 = getelementptr inbounds float* %tmp17719, i64 1
-  %tmp17721 = getelementptr inbounds float* %tmp17720, i64 1
-  %tmp17722 = getelementptr inbounds float* %tmp17721, i64 1
-  %tmp17723 = getelementptr inbounds float* %tmp17722, i64 1
-  %tmp17724 = getelementptr inbounds float* %tmp17723, i64 1
-  %tmp17725 = getelementptr inbounds float* %tmp17724, i64 1
-  %tmp17726 = getelementptr inbounds float* %tmp17725, i64 1
-  %tmp17727 = getelementptr inbounds float* %tmp17726, i64 1
-  %tmp17728 = getelementptr inbounds float* %tmp17727, i64 1
-  %tmp17729 = getelementptr inbounds float* %tmp17728, i64 1
-  %tmp17730 = getelementptr inbounds float* %tmp17729, i64 1
-  %tmp17731 = getelementptr inbounds float* %tmp17730, i64 1
-  %tmp17732 = getelementptr inbounds float* %tmp17731, i64 1
-  %tmp17733 = getelementptr inbounds float* %tmp17732, i64 1
-  %tmp17734 = getelementptr inbounds float* %tmp17733, i64 1
-  %tmp17735 = getelementptr inbounds float* %tmp17734, i64 1
-  %tmp17736 = getelementptr inbounds float* %tmp17735, i64 1
-  %tmp17737 = getelementptr inbounds float* %tmp17736, i64 1
-  %tmp17738 = getelementptr inbounds float* %tmp17737, i64 1
-  %tmp17739 = getelementptr inbounds float* %tmp17738, i64 1
-  %tmp17740 = getelementptr inbounds float* %tmp17739, i64 1
-  %tmp17741 = getelementptr inbounds float* %tmp17740, i64 1
-  %tmp17742 = getelementptr inbounds float* %tmp17741, i64 1
-  %tmp17743 = getelementptr inbounds float* %tmp17742, i64 1
-  %tmp17744 = getelementptr inbounds float* %tmp17743, i64 1
-  %tmp17745 = getelementptr inbounds float* %tmp17744, i64 1
-  %tmp17746 = getelementptr inbounds float* %tmp17745, i64 1
-  %tmp17747 = getelementptr inbounds float* %tmp17746, i64 1
-  %tmp17748 = getelementptr inbounds float* %tmp17747, i64 1
-  %tmp17749 = getelementptr inbounds float* %tmp17748, i64 1
-  %tmp17750 = getelementptr inbounds float* %tmp17749, i64 1
-  %tmp17751 = getelementptr inbounds float* %tmp17750, i64 1
-  %tmp17752 = getelementptr inbounds float* %tmp17751, i64 1
-  %tmp17753 = getelementptr inbounds float* %tmp17752, i64 1
-  %tmp17754 = getelementptr inbounds float* %tmp17753, i64 1
-  %tmp17755 = getelementptr inbounds float* %tmp17754, i64 1
-  %tmp17756 = getelementptr inbounds float* %tmp17755, i64 1
-  %tmp17757 = getelementptr inbounds float* %tmp17756, i64 1
-  %tmp17758 = getelementptr inbounds float* %tmp17757, i64 1
-  %tmp17759 = getelementptr inbounds float* %tmp17758, i64 1
-  %tmp17760 = getelementptr inbounds float* %tmp17759, i64 1
-  %tmp17761 = getelementptr inbounds float* %tmp17760, i64 1
-  %tmp17762 = getelementptr inbounds float* %tmp17761, i64 1
-  %tmp17763 = getelementptr inbounds float* %tmp17762, i64 1
-  %tmp17764 = getelementptr inbounds float* %tmp17763, i64 1
-  %tmp17765 = getelementptr inbounds float* %tmp17764, i64 1
-  %tmp17766 = getelementptr inbounds float* %tmp17765, i64 1
-  %tmp17767 = getelementptr inbounds float* %tmp17766, i64 1
-  %tmp17768 = getelementptr inbounds float* %tmp17767, i64 1
-  %tmp17769 = getelementptr inbounds float* %tmp17768, i64 1
-  %tmp17770 = getelementptr inbounds float* %tmp17769, i64 1
-  %tmp17771 = getelementptr inbounds float* %tmp17770, i64 1
-  %tmp17772 = getelementptr inbounds float* %tmp17771, i64 1
-  %tmp17773 = getelementptr inbounds float* %tmp17772, i64 1
-  %tmp17774 = getelementptr inbounds float* %tmp17773, i64 1
-  %tmp17775 = getelementptr inbounds float* %tmp17774, i64 1
-  %tmp17776 = getelementptr inbounds float* %tmp17775, i64 1
-  %tmp17777 = getelementptr inbounds float* %tmp17776, i64 1
-  %tmp17778 = getelementptr inbounds float* %tmp17777, i64 1
-  %tmp17779 = getelementptr inbounds float* %tmp17778, i64 1
-  %tmp17780 = getelementptr inbounds float* %tmp17779, i64 1
-  %tmp17781 = getelementptr inbounds float* %tmp17780, i64 1
-  %tmp17782 = getelementptr inbounds float* %tmp17781, i64 1
-  %tmp17783 = getelementptr inbounds float* %tmp17782, i64 1
-  %tmp17784 = getelementptr inbounds float* %tmp17783, i64 1
-  %tmp17785 = getelementptr inbounds float* %tmp17784, i64 1
-  %tmp17786 = getelementptr inbounds float* %tmp17785, i64 1
-  %tmp17787 = getelementptr inbounds float* %tmp17786, i64 1
-  %tmp17788 = getelementptr inbounds float* %tmp17787, i64 1
-  %tmp17789 = getelementptr inbounds float* %tmp17788, i64 1
-  %tmp17790 = getelementptr inbounds float* %tmp17789, i64 1
-  %tmp17791 = getelementptr inbounds float* %tmp17790, i64 1
-  %tmp17792 = getelementptr inbounds float* %tmp17791, i64 1
-  %tmp17793 = getelementptr inbounds float* %tmp17792, i64 1
-  %tmp17794 = getelementptr inbounds float* %tmp17793, i64 1
-  %tmp17795 = getelementptr inbounds float* %tmp17794, i64 1
-  %tmp17796 = getelementptr inbounds float* %tmp17795, i64 1
-  %tmp17797 = getelementptr inbounds float* %tmp17796, i64 1
-  %tmp17798 = getelementptr inbounds float* %tmp17797, i64 1
-  %tmp17799 = getelementptr inbounds float* %tmp17798, i64 1
-  %tmp17800 = getelementptr inbounds float* %tmp17799, i64 1
-  %tmp17801 = getelementptr inbounds float* %tmp17800, i64 1
-  %tmp17802 = getelementptr inbounds float* %tmp17801, i64 1
-  %tmp17803 = getelementptr inbounds float* %tmp17802, i64 1
-  %tmp17804 = getelementptr inbounds float* %tmp17803, i64 1
-  %tmp17805 = getelementptr inbounds float* %tmp17804, i64 1
-  %tmp17806 = getelementptr inbounds float* %tmp17805, i64 1
-  %tmp17807 = getelementptr inbounds float* %tmp17806, i64 1
-  %tmp17808 = getelementptr inbounds float* %tmp17807, i64 1
-  %tmp17809 = getelementptr inbounds float* %tmp17808, i64 1
-  %tmp17810 = getelementptr inbounds float* %tmp17809, i64 1
-  %tmp17811 = getelementptr inbounds float* %tmp17810, i64 1
-  %tmp17812 = getelementptr inbounds float* %tmp17811, i64 1
-  %tmp17813 = getelementptr inbounds float* %tmp17812, i64 1
-  %tmp17814 = getelementptr inbounds float* %tmp17813, i64 1
-  %tmp17815 = getelementptr inbounds float* %tmp17814, i64 1
-  %tmp17816 = getelementptr inbounds float* %tmp17815, i64 1
-  %tmp17817 = getelementptr inbounds float* %tmp17816, i64 1
-  %tmp17818 = getelementptr inbounds float* %tmp17817, i64 1
-  %tmp17819 = getelementptr inbounds float* %tmp17818, i64 1
-  %tmp17820 = getelementptr inbounds float* %tmp17819, i64 1
-  %tmp17821 = getelementptr inbounds float* %tmp17820, i64 1
-  %tmp17822 = getelementptr inbounds float* %tmp17821, i64 1
-  %tmp17823 = getelementptr inbounds float* %tmp17822, i64 1
-  %tmp17824 = getelementptr inbounds float* %tmp17823, i64 1
-  %tmp17825 = getelementptr inbounds float* %tmp17824, i64 1
-  %tmp17826 = getelementptr inbounds float* %tmp17825, i64 1
-  %tmp17827 = getelementptr inbounds float* %tmp17826, i64 1
-  %tmp17828 = getelementptr inbounds float* %tmp17827, i64 1
-  %tmp17829 = getelementptr inbounds float* %tmp17828, i64 1
-  %tmp17830 = getelementptr inbounds float* %tmp17829, i64 1
-  %tmp17831 = getelementptr inbounds float* %tmp17830, i64 1
-  %tmp17832 = getelementptr inbounds float* %tmp17831, i64 1
-  %tmp17833 = getelementptr inbounds float* %tmp17832, i64 1
-  %tmp17834 = getelementptr inbounds float* %tmp17833, i64 1
-  %tmp17835 = getelementptr inbounds float* %tmp17834, i64 1
-  %tmp17836 = getelementptr inbounds float* %tmp17835, i64 1
-  %tmp17837 = getelementptr inbounds float* %tmp17836, i64 1
-  %tmp17838 = getelementptr inbounds float* %tmp17837, i64 1
-  %tmp17839 = getelementptr inbounds float* %tmp17838, i64 1
-  %tmp17840 = getelementptr inbounds float* %tmp17839, i64 1
-  %tmp17841 = getelementptr inbounds float* %tmp17840, i64 1
-  %tmp17842 = getelementptr inbounds float* %tmp17841, i64 1
-  %tmp17843 = getelementptr inbounds float* %tmp17842, i64 1
-  %tmp17844 = getelementptr inbounds float* %tmp17843, i64 1
-  %tmp17845 = getelementptr inbounds float* %tmp17844, i64 1
-  %tmp17846 = getelementptr inbounds float* %tmp17845, i64 1
-  %tmp17847 = getelementptr inbounds float* %tmp17846, i64 1
-  %tmp17848 = getelementptr inbounds float* %tmp17847, i64 1
-  %tmp17849 = getelementptr inbounds float* %tmp17848, i64 1
-  %tmp17850 = getelementptr inbounds float* %tmp17849, i64 1
-  %tmp17851 = getelementptr inbounds float* %tmp17850, i64 1
-  %tmp17852 = getelementptr inbounds float* %tmp17851, i64 1
-  %tmp17853 = getelementptr inbounds float* %tmp17852, i64 1
-  %tmp17854 = getelementptr inbounds float* %tmp17853, i64 1
-  %tmp17855 = getelementptr inbounds float* %tmp17854, i64 1
-  %tmp17856 = getelementptr inbounds float* %tmp17855, i64 1
-  %tmp17857 = getelementptr inbounds float* %tmp17856, i64 1
-  %tmp17858 = getelementptr inbounds float* %tmp17857, i64 1
-  %tmp17859 = getelementptr inbounds float* %tmp17858, i64 1
-  %tmp17860 = getelementptr inbounds float* %tmp17859, i64 1
-  %tmp17861 = getelementptr inbounds float* %tmp17860, i64 1
-  %tmp17862 = getelementptr inbounds float* %tmp17861, i64 1
-  %tmp17863 = getelementptr inbounds float* %tmp17862, i64 1
-  %tmp17864 = getelementptr inbounds float* %tmp17863, i64 1
-  %tmp17865 = getelementptr inbounds float* %tmp17864, i64 1
-  %tmp17866 = getelementptr inbounds float* %tmp17865, i64 1
-  %tmp17867 = getelementptr inbounds float* %tmp17866, i64 1
-  %tmp17868 = getelementptr inbounds float* %tmp17867, i64 1
-  %tmp17869 = getelementptr inbounds float* %tmp17868, i64 1
-  %tmp17870 = getelementptr inbounds float* %tmp17869, i64 1
-  %tmp17871 = getelementptr inbounds float* %tmp17870, i64 1
-  %tmp17872 = getelementptr inbounds float* %tmp17871, i64 1
-  %tmp17873 = getelementptr inbounds float* %tmp17872, i64 1
-  %tmp17874 = getelementptr inbounds float* %tmp17873, i64 1
-  %tmp17875 = getelementptr inbounds float* %tmp17874, i64 1
-  %tmp17876 = getelementptr inbounds float* %tmp17875, i64 1
-  %tmp17877 = getelementptr inbounds float* %tmp17876, i64 1
-  %tmp17878 = getelementptr inbounds float* %tmp17877, i64 1
-  %tmp17879 = getelementptr inbounds float* %tmp17878, i64 1
-  %tmp17880 = getelementptr inbounds float* %tmp17879, i64 1
-  %tmp17881 = getelementptr inbounds float* %tmp17880, i64 1
-  %tmp17882 = getelementptr inbounds float* %tmp17881, i64 1
-  %tmp17883 = getelementptr inbounds float* %tmp17882, i64 1
-  %tmp17884 = getelementptr inbounds float* %tmp17883, i64 1
-  %tmp17885 = getelementptr inbounds float* %tmp17884, i64 1
-  %tmp17886 = getelementptr inbounds float* %tmp17885, i64 1
-  %tmp17887 = getelementptr inbounds float* %tmp17886, i64 1
-  %tmp17888 = getelementptr inbounds float* %tmp17887, i64 1
-  %tmp17889 = getelementptr inbounds float* %tmp17888, i64 1
-  %tmp17890 = getelementptr inbounds float* %tmp17889, i64 1
-  %tmp17891 = getelementptr inbounds float* %tmp17890, i64 1
-  %tmp17892 = getelementptr inbounds float* %tmp17891, i64 1
-  %tmp17893 = getelementptr inbounds float* %tmp17892, i64 1
-  %tmp17894 = getelementptr inbounds float* %tmp17893, i64 1
-  %tmp17895 = getelementptr inbounds float* %tmp17894, i64 1
-  %tmp17896 = getelementptr inbounds float* %tmp17895, i64 1
-  %tmp17897 = getelementptr inbounds float* %tmp17896, i64 1
-  %tmp17898 = getelementptr inbounds float* %tmp17897, i64 1
-  %tmp17899 = getelementptr inbounds float* %tmp17898, i64 1
-  %tmp17900 = getelementptr inbounds float* %tmp17899, i64 1
-  %tmp17901 = getelementptr inbounds float* %tmp17900, i64 1
-  %tmp17902 = getelementptr inbounds float* %tmp17901, i64 1
-  %tmp17903 = getelementptr inbounds float* %tmp17902, i64 1
-  %tmp17904 = getelementptr inbounds float* %tmp17903, i64 1
-  %tmp17905 = getelementptr inbounds float* %tmp17904, i64 1
-  %tmp17906 = getelementptr inbounds float* %tmp17905, i64 1
-  %tmp17907 = getelementptr inbounds float* %tmp17906, i64 1
-  %tmp17908 = getelementptr inbounds float* %tmp17907, i64 1
-  %tmp17909 = getelementptr inbounds float* %tmp17908, i64 1
-  %tmp17910 = getelementptr inbounds float* %tmp17909, i64 1
-  %tmp17911 = getelementptr inbounds float* %tmp17910, i64 1
-  %tmp17912 = getelementptr inbounds float* %tmp17911, i64 1
-  %tmp17913 = getelementptr inbounds float* %tmp17912, i64 1
-  %tmp17914 = getelementptr inbounds float* %tmp17913, i64 1
-  %tmp17915 = getelementptr inbounds float* %tmp17914, i64 1
-  %tmp17916 = getelementptr inbounds float* %tmp17915, i64 1
-  %tmp17917 = getelementptr inbounds float* %tmp17916, i64 1
-  %tmp17918 = getelementptr inbounds float* %tmp17917, i64 1
-  %tmp17919 = getelementptr inbounds float* %tmp17918, i64 1
-  %tmp17920 = getelementptr inbounds float* %tmp17919, i64 1
-  %tmp17921 = getelementptr inbounds float* %tmp17920, i64 1
-  %tmp17922 = getelementptr inbounds float* %tmp17921, i64 1
-  %tmp17923 = getelementptr inbounds float* %tmp17922, i64 1
-  %tmp17924 = getelementptr inbounds float* %tmp17923, i64 1
-  %tmp17925 = getelementptr inbounds float* %tmp17924, i64 1
-  %tmp17926 = getelementptr inbounds float* %tmp17925, i64 1
-  %tmp17927 = getelementptr inbounds float* %tmp17926, i64 1
-  %tmp17928 = getelementptr inbounds float* %tmp17927, i64 1
-  %tmp17929 = getelementptr inbounds float* %tmp17928, i64 1
-  %tmp17930 = getelementptr inbounds float* %tmp17929, i64 1
-  %tmp17931 = getelementptr inbounds float* %tmp17930, i64 1
-  %tmp17932 = getelementptr inbounds float* %tmp17931, i64 1
-  %tmp17933 = getelementptr inbounds float* %tmp17932, i64 1
-  %tmp17934 = getelementptr inbounds float* %tmp17933, i64 1
-  %tmp17935 = getelementptr inbounds float* %tmp17934, i64 1
-  %tmp17936 = getelementptr inbounds float* %tmp17935, i64 1
-  %tmp17937 = getelementptr inbounds float* %tmp17936, i64 1
-  %tmp17938 = getelementptr inbounds float* %tmp17937, i64 1
-  %tmp17939 = getelementptr inbounds float* %tmp17938, i64 1
-  %tmp17940 = getelementptr inbounds float* %tmp17939, i64 1
-  %tmp17941 = getelementptr inbounds float* %tmp17940, i64 1
-  %tmp17942 = getelementptr inbounds float* %tmp17941, i64 1
-  %tmp17943 = getelementptr inbounds float* %tmp17942, i64 1
-  %tmp17944 = getelementptr inbounds float* %tmp17943, i64 1
-  %tmp17945 = getelementptr inbounds float* %tmp17944, i64 1
-  %tmp17946 = getelementptr inbounds float* %tmp17945, i64 1
-  %tmp17947 = getelementptr inbounds float* %tmp17946, i64 1
-  %tmp17948 = getelementptr inbounds float* %tmp17947, i64 1
-  %tmp17949 = getelementptr inbounds float* %tmp17948, i64 1
-  %tmp17950 = getelementptr inbounds float* %tmp17949, i64 1
-  %tmp17951 = getelementptr inbounds float* %tmp17950, i64 1
-  %tmp17952 = getelementptr inbounds float* %tmp17951, i64 1
-  %tmp17953 = getelementptr inbounds float* %tmp17952, i64 1
-  %tmp17954 = getelementptr inbounds float* %tmp17953, i64 1
-  %tmp17955 = getelementptr inbounds float* %tmp17954, i64 1
-  %tmp17956 = getelementptr inbounds float* %tmp17955, i64 1
-  %tmp17957 = getelementptr inbounds float* %tmp17956, i64 1
-  %tmp17958 = getelementptr inbounds float* %tmp17957, i64 1
-  %tmp17959 = getelementptr inbounds float* %tmp17958, i64 1
-  %tmp17960 = getelementptr inbounds float* %tmp17959, i64 1
-  %tmp17961 = getelementptr inbounds float* %tmp17960, i64 1
-  %tmp17962 = getelementptr inbounds float* %tmp17961, i64 1
-  %tmp17963 = getelementptr inbounds float* %tmp17962, i64 1
-  %tmp17964 = getelementptr inbounds float* %tmp17963, i64 1
-  %tmp17965 = getelementptr inbounds float* %tmp17964, i64 1
-  %tmp17966 = getelementptr inbounds float* %tmp17965, i64 1
-  %tmp17967 = getelementptr inbounds float* %tmp17966, i64 1
-  %tmp17968 = getelementptr inbounds float* %tmp17967, i64 1
-  %tmp17969 = getelementptr inbounds float* %tmp17968, i64 1
-  %tmp17970 = getelementptr inbounds float* %tmp17969, i64 1
-  %tmp17971 = getelementptr inbounds float* %tmp17970, i64 1
-  %tmp17972 = getelementptr inbounds float* %tmp17971, i64 1
-  %tmp17973 = getelementptr inbounds float* %tmp17972, i64 1
-  %tmp17974 = getelementptr inbounds float* %tmp17973, i64 1
-  %tmp17975 = getelementptr inbounds float* %tmp17974, i64 1
-  %tmp17976 = getelementptr inbounds float* %tmp17975, i64 1
-  %tmp17977 = getelementptr inbounds float* %tmp17976, i64 1
-  %tmp17978 = getelementptr inbounds float* %tmp17977, i64 1
-  %tmp17979 = getelementptr inbounds float* %tmp17978, i64 1
-  %tmp17980 = getelementptr inbounds float* %tmp17979, i64 1
-  %tmp17981 = getelementptr inbounds float* %tmp17980, i64 1
-  %tmp17982 = getelementptr inbounds float* %tmp17981, i64 1
-  %tmp17983 = getelementptr inbounds float* %tmp17982, i64 1
-  %tmp17984 = getelementptr inbounds float* %tmp17983, i64 1
-  %tmp17985 = getelementptr inbounds float* %tmp17984, i64 1
-  %tmp17986 = getelementptr inbounds float* %tmp17985, i64 1
-  %tmp17987 = getelementptr inbounds float* %tmp17986, i64 1
-  %tmp17988 = getelementptr inbounds float* %tmp17987, i64 1
-  %tmp17989 = getelementptr inbounds float* %tmp17988, i64 1
-  %tmp17990 = getelementptr inbounds float* %tmp17989, i64 1
-  %tmp17991 = getelementptr inbounds float* %tmp17990, i64 1
-  %tmp17992 = getelementptr inbounds float* %tmp17991, i64 1
-  %tmp17993 = getelementptr inbounds float* %tmp17992, i64 1
-  %tmp17994 = getelementptr inbounds float* %tmp17993, i64 1
-  %tmp17995 = getelementptr inbounds float* %tmp17994, i64 1
-  %tmp17996 = getelementptr inbounds float* %tmp17995, i64 1
-  %tmp17997 = getelementptr inbounds float* %tmp17996, i64 1
-  %tmp17998 = getelementptr inbounds float* %tmp17997, i64 1
-  %tmp17999 = getelementptr inbounds float* %tmp17998, i64 1
-  %tmp18000 = getelementptr inbounds float* %tmp17999, i64 1
-  %tmp18001 = getelementptr inbounds float* %tmp18000, i64 1
-  %tmp18002 = getelementptr inbounds float* %tmp18001, i64 1
-  %tmp18003 = getelementptr inbounds float* %tmp18002, i64 1
-  %tmp18004 = getelementptr inbounds float* %tmp18003, i64 1
-  %tmp18005 = getelementptr inbounds float* %tmp18004, i64 1
-  %tmp18006 = getelementptr inbounds float* %tmp18005, i64 1
-  %tmp18007 = getelementptr inbounds float* %tmp18006, i64 1
-  %tmp18008 = getelementptr inbounds float* %tmp18007, i64 1
-  %tmp18009 = getelementptr inbounds float* %tmp18008, i64 1
-  %tmp18010 = getelementptr inbounds float* %tmp18009, i64 1
-  %tmp18011 = getelementptr inbounds float* %tmp18010, i64 1
-  %tmp18012 = getelementptr inbounds float* %tmp18011, i64 1
-  %tmp18013 = getelementptr inbounds float* %tmp18012, i64 1
-  %tmp18014 = getelementptr inbounds float* %tmp18013, i64 1
-  %tmp18015 = getelementptr inbounds float* %tmp18014, i64 1
-  %tmp18016 = getelementptr inbounds float* %tmp18015, i64 1
-  %tmp18017 = getelementptr inbounds float* %tmp18016, i64 1
-  %tmp18018 = getelementptr inbounds float* %tmp18017, i64 1
-  %tmp18019 = getelementptr inbounds float* %tmp18018, i64 1
-  %tmp18020 = getelementptr inbounds float* %tmp18019, i64 1
-  %tmp18021 = getelementptr inbounds float* %tmp18020, i64 1
-  %tmp18022 = getelementptr inbounds float* %tmp18021, i64 1
-  %tmp18023 = getelementptr inbounds float* %tmp18022, i64 1
-  %tmp18024 = getelementptr inbounds float* %tmp18023, i64 1
-  %tmp18025 = getelementptr inbounds float* %tmp18024, i64 1
-  %tmp18026 = getelementptr inbounds float* %tmp18025, i64 1
-  %tmp18027 = getelementptr inbounds float* %tmp18026, i64 1
-  %tmp18028 = getelementptr inbounds float* %tmp18027, i64 1
-  %tmp18029 = getelementptr inbounds float* %tmp18028, i64 1
-  %tmp18030 = getelementptr inbounds float* %tmp18029, i64 1
-  %tmp18031 = getelementptr inbounds float* %tmp18030, i64 1
-  %tmp18032 = getelementptr inbounds float* %tmp18031, i64 1
-  %tmp18033 = getelementptr inbounds float* %tmp18032, i64 1
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-  %tmp18714 = getelementptr inbounds float* %tmp18713, i64 1
-  %tmp18715 = getelementptr inbounds float* %tmp18714, i64 1
-  %tmp18716 = getelementptr inbounds float* %tmp18715, i64 1
-  %tmp18717 = getelementptr inbounds float* %tmp18716, i64 1
-  %tmp18718 = getelementptr inbounds float* %tmp18717, i64 1
-  %tmp18719 = getelementptr inbounds float* %tmp18718, i64 1
-  %tmp18720 = getelementptr inbounds float* %tmp18719, i64 1
-  %tmp18721 = getelementptr inbounds float* %tmp18720, i64 1
-  %tmp18722 = getelementptr inbounds float* %tmp18721, i64 1
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-  %tmp18724 = getelementptr inbounds float* %tmp18723, i64 1
-  %tmp18725 = getelementptr inbounds float* %tmp18724, i64 1
-  %tmp18726 = getelementptr inbounds float* %tmp18725, i64 1
-  %tmp18727 = getelementptr inbounds float* %tmp18726, i64 1
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-  %tmp18731 = getelementptr inbounds float* %tmp18730, i64 1
-  %tmp18732 = getelementptr inbounds float* %tmp18731, i64 1
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-  %tmp18737 = getelementptr inbounds float* %tmp18736, i64 1
-  %tmp18738 = getelementptr inbounds float* %tmp18737, i64 1
-  %tmp18739 = getelementptr inbounds float* %tmp18738, i64 1
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-  %tmp18741 = getelementptr inbounds float* %tmp18740, i64 1
-  %tmp18742 = getelementptr inbounds float* %tmp18741, i64 1
-  %tmp18743 = getelementptr inbounds float* %tmp18742, i64 1
-  %tmp18744 = getelementptr inbounds float* %tmp18743, i64 1
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-  %tmp18746 = getelementptr inbounds float* %tmp18745, i64 1
-  %tmp18747 = getelementptr inbounds float* %tmp18746, i64 1
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-  %tmp18758 = getelementptr inbounds float* %tmp18757, i64 1
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-  %tmp18761 = getelementptr inbounds float* %tmp18760, i64 1
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-  %tmp18782 = getelementptr inbounds float* %tmp18781, i64 1
-  %tmp18783 = getelementptr inbounds float* %tmp18782, i64 1
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-  %tmp18785 = getelementptr inbounds float* %tmp18784, i64 1
-  %tmp18786 = getelementptr inbounds float* %tmp18785, i64 1
-  %tmp18787 = getelementptr inbounds float* %tmp18786, i64 1
-  %tmp18788 = getelementptr inbounds float* %tmp18787, i64 1
-  %tmp18789 = getelementptr inbounds float* %tmp18788, i64 1
-  %tmp18790 = getelementptr inbounds float* %tmp18789, i64 1
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-  %tmp18792 = getelementptr inbounds float* %tmp18791, i64 1
-  %tmp18793 = getelementptr inbounds float* %tmp18792, i64 1
-  %tmp18794 = getelementptr inbounds float* %tmp18793, i64 1
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-  %tmp18796 = getelementptr inbounds float* %tmp18795, i64 1
-  %tmp18797 = getelementptr inbounds float* %tmp18796, i64 1
-  %tmp18798 = getelementptr inbounds float* %tmp18797, i64 1
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-  %tmp18802 = getelementptr inbounds float* %tmp18801, i64 1
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-  %tmp18804 = getelementptr inbounds float* %tmp18803, i64 1
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-  %tmp18806 = getelementptr inbounds float* %tmp18805, i64 1
-  %tmp18807 = getelementptr inbounds float* %tmp18806, i64 1
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-  %tmp18817 = getelementptr inbounds float* %tmp18816, i64 1
-  %tmp18818 = getelementptr inbounds float* %tmp18817, i64 1
-  %tmp18819 = getelementptr inbounds float* %tmp18818, i64 1
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-  %tmp18826 = getelementptr inbounds float* %tmp18825, i64 1
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-  %tmp18853 = getelementptr inbounds float* %tmp18852, i64 1
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-  %tmp18859 = getelementptr inbounds float* %tmp18858, i64 1
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-  %tmp18863 = getelementptr inbounds float* %tmp18862, i64 1
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-  %tmp18894 = getelementptr inbounds float* %tmp18893, i64 1
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-  %tmp20409 = getelementptr inbounds float* %tmp20408, i64 1
-  %tmp20410 = getelementptr inbounds float* %tmp20409, i64 1
-  %tmp20411 = getelementptr inbounds float* %tmp20410, i64 1
-  %tmp20412 = getelementptr inbounds float* %tmp20411, i64 1
-  %tmp20413 = getelementptr inbounds float* %tmp20412, i64 1
-  %tmp20414 = getelementptr inbounds float* %tmp20413, i64 1
-  %tmp20415 = getelementptr inbounds float* %tmp20414, i64 1
-  %tmp20416 = getelementptr inbounds float* %tmp20415, i64 1
-  %tmp20417 = getelementptr inbounds float* %tmp20416, i64 1
-  %tmp20418 = getelementptr inbounds float* %tmp20417, i64 1
-  %tmp20419 = getelementptr inbounds float* %tmp20418, i64 1
-  %tmp20420 = getelementptr inbounds float* %tmp20419, i64 1
-  %tmp20421 = getelementptr inbounds float* %tmp20420, i64 1
-  %tmp20422 = getelementptr inbounds float* %tmp20421, i64 1
-  %tmp20423 = getelementptr inbounds float* %tmp20422, i64 1
-  %tmp20424 = getelementptr inbounds float* %tmp20423, i64 1
-  %tmp20425 = getelementptr inbounds float* %tmp20424, i64 1
-  %tmp20426 = getelementptr inbounds float* %tmp20425, i64 1
-  %tmp20427 = getelementptr inbounds float* %tmp20426, i64 1
-  %tmp20428 = getelementptr inbounds float* %tmp20427, i64 1
-  %tmp20429 = getelementptr inbounds float* %tmp20428, i64 1
-  %tmp20430 = getelementptr inbounds float* %tmp20429, i64 1
-  %tmp20431 = getelementptr inbounds float* %tmp20430, i64 1
-  %tmp20432 = getelementptr inbounds float* %tmp20431, i64 1
-  %tmp20433 = getelementptr inbounds float* %tmp20432, i64 1
-  %tmp20434 = getelementptr inbounds float* %tmp20433, i64 1
-  %tmp20435 = getelementptr inbounds float* %tmp20434, i64 1
-  %tmp20436 = getelementptr inbounds float* %tmp20435, i64 1
-  %tmp20437 = getelementptr inbounds float* %tmp20436, i64 1
-  %tmp20438 = getelementptr inbounds float* %tmp20437, i64 1
-  %tmp20439 = getelementptr inbounds float* %tmp20438, i64 1
-  %tmp20440 = getelementptr inbounds float* %tmp20439, i64 1
-  %tmp20441 = getelementptr inbounds float* %tmp20440, i64 1
-  %tmp20442 = getelementptr inbounds float* %tmp20441, i64 1
-  %tmp20443 = getelementptr inbounds float* %tmp20442, i64 1
-  %tmp20444 = getelementptr inbounds float* %tmp20443, i64 1
-  %tmp20445 = getelementptr inbounds float* %tmp20444, i64 1
-  %tmp20446 = getelementptr inbounds float* %tmp20445, i64 1
-  %tmp20447 = getelementptr inbounds float* %tmp20446, i64 1
-  %tmp20448 = getelementptr inbounds float* %tmp20447, i64 1
-  %tmp20449 = getelementptr inbounds float* %tmp20448, i64 1
-  %tmp20450 = getelementptr inbounds float* %tmp20449, i64 1
-  %tmp20451 = getelementptr inbounds float* %tmp20450, i64 1
-  %tmp20452 = getelementptr inbounds float* %tmp20451, i64 1
-  %tmp20453 = getelementptr inbounds float* %tmp20452, i64 1
-  %tmp20454 = getelementptr inbounds float* %tmp20453, i64 1
-  %tmp20455 = getelementptr inbounds float* %tmp20454, i64 1
-  %tmp20456 = getelementptr inbounds float* %tmp20455, i64 1
-  %tmp20457 = getelementptr inbounds float* %tmp20456, i64 1
-  %tmp20458 = getelementptr inbounds float* %tmp20457, i64 1
-  %tmp20459 = getelementptr inbounds float* %tmp20458, i64 1
-  %tmp20460 = getelementptr inbounds float* %tmp20459, i64 1
-  %tmp20461 = getelementptr inbounds float* %tmp20460, i64 1
-  %tmp20462 = getelementptr inbounds float* %tmp20461, i64 1
-  %tmp20463 = getelementptr inbounds float* %tmp20462, i64 1
-  %tmp20464 = getelementptr inbounds float* %tmp20463, i64 1
-  %tmp20465 = getelementptr inbounds float* %tmp20464, i64 1
-  %tmp20466 = getelementptr inbounds float* %tmp20465, i64 1
-  %tmp20467 = getelementptr inbounds float* %tmp20466, i64 1
-  %tmp20468 = getelementptr inbounds float* %tmp20467, i64 1
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-  %tmp20470 = getelementptr inbounds float* %tmp20469, i64 1
-  %tmp20471 = getelementptr inbounds float* %tmp20470, i64 1
-  %tmp20472 = getelementptr inbounds float* %tmp20471, i64 1
-  %tmp20473 = getelementptr inbounds float* %tmp20472, i64 1
-  %tmp20474 = getelementptr inbounds float* %tmp20473, i64 1
-  %tmp20475 = getelementptr inbounds float* %tmp20474, i64 1
-  %tmp20476 = getelementptr inbounds float* %tmp20475, i64 1
-  %tmp20477 = getelementptr inbounds float* %tmp20476, i64 1
-  %tmp20478 = getelementptr inbounds float* %tmp20477, i64 1
-  %tmp20479 = getelementptr inbounds float* %tmp20478, i64 1
-  %tmp20480 = getelementptr inbounds float* %tmp20479, i64 1
-  %tmp20481 = getelementptr inbounds float* %tmp20480, i64 1
-  %tmp20482 = getelementptr inbounds float* %tmp20481, i64 1
-  %tmp20483 = getelementptr inbounds float* %tmp20482, i64 1
-  %tmp20484 = getelementptr inbounds float* %tmp20483, i64 1
-  %tmp20485 = getelementptr inbounds float* %tmp20484, i64 1
-  %tmp20486 = getelementptr inbounds float* %tmp20485, i64 1
-  %tmp20487 = getelementptr inbounds float* %tmp20486, i64 1
-  %tmp20488 = getelementptr inbounds float* %tmp20487, i64 1
-  %tmp20489 = getelementptr inbounds float* %tmp20488, i64 1
-  %tmp20490 = getelementptr inbounds float* %tmp20489, i64 1
-  %tmp20491 = getelementptr inbounds float* %tmp20490, i64 1
-  %tmp20492 = getelementptr inbounds float* %tmp20491, i64 1
-  %tmp20493 = getelementptr inbounds float* %tmp20492, i64 1
-  %tmp20494 = getelementptr inbounds float* %tmp20493, i64 1
-  %tmp20495 = getelementptr inbounds float* %tmp20494, i64 1
-  %tmp20496 = getelementptr inbounds float* %tmp20495, i64 1
-  %tmp20497 = getelementptr inbounds float* %tmp20496, i64 1
-  %tmp20498 = getelementptr inbounds float* %tmp20497, i64 1
-  %tmp20499 = getelementptr inbounds float* %tmp20498, i64 1
-  %tmp20500 = getelementptr inbounds float* %tmp20499, i64 1
-  %tmp20501 = getelementptr inbounds float* %tmp20500, i64 1
-  %tmp20502 = getelementptr inbounds float* %tmp20501, i64 1
-  %tmp20503 = getelementptr inbounds float* %tmp20502, i64 1
-  %tmp20504 = getelementptr inbounds float* %tmp20503, i64 1
-  %tmp20505 = getelementptr inbounds float* %tmp20504, i64 1
-  %tmp20506 = getelementptr inbounds float* %tmp20505, i64 1
-  %tmp20507 = getelementptr inbounds float* %tmp20506, i64 1
-  %tmp20508 = getelementptr inbounds float* %tmp20507, i64 1
-  %tmp20509 = getelementptr inbounds float* %tmp20508, i64 1
-  %tmp20510 = getelementptr inbounds float* %tmp20509, i64 1
-  %tmp20511 = getelementptr inbounds float* %tmp20510, i64 1
-  %tmp20512 = getelementptr inbounds float* %tmp20511, i64 1
-  %tmp20513 = getelementptr inbounds float* %tmp20512, i64 1
-  %tmp20514 = getelementptr inbounds float* %tmp20513, i64 1
-  %tmp20515 = getelementptr inbounds float* %tmp20514, i64 1
-  %tmp20516 = getelementptr inbounds float* %tmp20515, i64 1
-  %tmp20517 = getelementptr inbounds float* %tmp20516, i64 1
-  %tmp20518 = getelementptr inbounds float* %tmp20517, i64 1
-  %tmp20519 = getelementptr inbounds float* %tmp20518, i64 1
-  %tmp20520 = getelementptr inbounds float* %tmp20519, i64 1
-  %tmp20521 = getelementptr inbounds float* %tmp20520, i64 1
-  %tmp20522 = getelementptr inbounds float* %tmp20521, i64 1
-  %tmp20523 = getelementptr inbounds float* %tmp20522, i64 1
-  %tmp20524 = getelementptr inbounds float* %tmp20523, i64 1
-  %tmp20525 = getelementptr inbounds float* %tmp20524, i64 1
-  %tmp20526 = getelementptr inbounds float* %tmp20525, i64 1
-  %tmp20527 = getelementptr inbounds float* %tmp20526, i64 1
-  %tmp20528 = getelementptr inbounds float* %tmp20527, i64 1
-  %tmp20529 = getelementptr inbounds float* %tmp20528, i64 1
-  %tmp20530 = getelementptr inbounds float* %tmp20529, i64 1
-  %tmp20531 = getelementptr inbounds float* %tmp20530, i64 1
-  %tmp20532 = getelementptr inbounds float* %tmp20531, i64 1
-  %tmp20533 = getelementptr inbounds float* %tmp20532, i64 1
-  %tmp20534 = getelementptr inbounds float* %tmp20533, i64 1
-  %tmp20535 = getelementptr inbounds float* %tmp20534, i64 1
-  %tmp20536 = getelementptr inbounds float* %tmp20535, i64 1
-  %tmp20537 = getelementptr inbounds float* %tmp20536, i64 1
-  %tmp20538 = getelementptr inbounds float* %tmp20537, i64 1
-  %tmp20539 = getelementptr inbounds float* %tmp20538, i64 1
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-  %tmp20541 = getelementptr inbounds float* %tmp20540, i64 1
-  %tmp20542 = getelementptr inbounds float* %tmp20541, i64 1
-  %tmp20543 = getelementptr inbounds float* %tmp20542, i64 1
-  %tmp20544 = getelementptr inbounds float* %tmp20543, i64 1
-  %tmp20545 = getelementptr inbounds float* %tmp20544, i64 1
-  %tmp20546 = getelementptr inbounds float* %tmp20545, i64 1
-  %tmp20547 = getelementptr inbounds float* %tmp20546, i64 1
-  %tmp20548 = getelementptr inbounds float* %tmp20547, i64 1
-  %tmp20549 = getelementptr inbounds float* %tmp20548, i64 1
-  %tmp20550 = getelementptr inbounds float* %tmp20549, i64 1
-  %tmp20551 = getelementptr inbounds float* %tmp20550, i64 1
-  %tmp20552 = getelementptr inbounds float* %tmp20551, i64 1
-  %tmp20553 = getelementptr inbounds float* %tmp20552, i64 1
-  %tmp20554 = getelementptr inbounds float* %tmp20553, i64 1
-  %tmp20555 = getelementptr inbounds float* %tmp20554, i64 1
-  %tmp20556 = getelementptr inbounds float* %tmp20555, i64 1
-  %tmp20557 = getelementptr inbounds float* %tmp20556, i64 1
-  %tmp20558 = getelementptr inbounds float* %tmp20557, i64 1
-  %tmp20559 = getelementptr inbounds float* %tmp20558, i64 1
-  %tmp20560 = getelementptr inbounds float* %tmp20559, i64 1
-  %tmp20561 = getelementptr inbounds float* %tmp20560, i64 1
-  %tmp20562 = getelementptr inbounds float* %tmp20561, i64 1
-  %tmp20563 = getelementptr inbounds float* %tmp20562, i64 1
-  %tmp20564 = getelementptr inbounds float* %tmp20563, i64 1
-  %tmp20565 = getelementptr inbounds float* %tmp20564, i64 1
-  %tmp20566 = getelementptr inbounds float* %tmp20565, i64 1
-  %tmp20567 = getelementptr inbounds float* %tmp20566, i64 1
-  %tmp20568 = getelementptr inbounds float* %tmp20567, i64 1
-  %tmp20569 = getelementptr inbounds float* %tmp20568, i64 1
-  %tmp20570 = getelementptr inbounds float* %tmp20569, i64 1
-  %tmp20571 = getelementptr inbounds float* %tmp20570, i64 1
-  %tmp20572 = getelementptr inbounds float* %tmp20571, i64 1
-  %tmp20573 = getelementptr inbounds float* %tmp20572, i64 1
-  %tmp20574 = getelementptr inbounds float* %tmp20573, i64 1
-  %tmp20575 = getelementptr inbounds float* %tmp20574, i64 1
-  %tmp20576 = getelementptr inbounds float* %tmp20575, i64 1
-  %tmp20577 = getelementptr inbounds float* %tmp20576, i64 1
-  %tmp20578 = getelementptr inbounds float* %tmp20577, i64 1
-  %tmp20579 = getelementptr inbounds float* %tmp20578, i64 1
-  %tmp20580 = getelementptr inbounds float* %tmp20579, i64 1
-  %tmp20581 = getelementptr inbounds float* %tmp20580, i64 1
-  %tmp20582 = getelementptr inbounds float* %tmp20581, i64 1
-  %tmp20583 = getelementptr inbounds float* %tmp20582, i64 1
-  %tmp20584 = getelementptr inbounds float* %tmp20583, i64 1
-  %tmp20585 = getelementptr inbounds float* %tmp20584, i64 1
-  %tmp20586 = getelementptr inbounds float* %tmp20585, i64 1
-  %tmp20587 = getelementptr inbounds float* %tmp20586, i64 1
-  %tmp20588 = getelementptr inbounds float* %tmp20587, i64 1
-  %tmp20589 = getelementptr inbounds float* %tmp20588, i64 1
-  %tmp20590 = getelementptr inbounds float* %tmp20589, i64 1
-  %tmp20591 = getelementptr inbounds float* %tmp20590, i64 1
-  %tmp20592 = getelementptr inbounds float* %tmp20591, i64 1
-  %tmp20593 = getelementptr inbounds float* %tmp20592, i64 1
-  %tmp20594 = getelementptr inbounds float* %tmp20593, i64 1
-  %tmp20595 = getelementptr inbounds float* %tmp20594, i64 1
-  %tmp20596 = getelementptr inbounds float* %tmp20595, i64 1
-  %tmp20597 = getelementptr inbounds float* %tmp20596, i64 1
-  %tmp20598 = getelementptr inbounds float* %tmp20597, i64 1
-  %tmp20599 = getelementptr inbounds float* %tmp20598, i64 1
-  %tmp20600 = getelementptr inbounds float* %tmp20599, i64 1
-  %tmp20601 = getelementptr inbounds float* %tmp20600, i64 1
-  %tmp20602 = getelementptr inbounds float* %tmp20601, i64 1
-  %tmp20603 = getelementptr inbounds float* %tmp20602, i64 1
-  %tmp20604 = getelementptr inbounds float* %tmp20603, i64 1
-  %tmp20605 = getelementptr inbounds float* %tmp20604, i64 1
-  %tmp20606 = getelementptr inbounds float* %tmp20605, i64 1
-  %tmp20607 = getelementptr inbounds float* %tmp20606, i64 1
-  %tmp20608 = getelementptr inbounds float* %tmp20607, i64 1
-  %tmp20609 = getelementptr inbounds float* %tmp20608, i64 1
-  %tmp20610 = getelementptr inbounds float* %tmp20609, i64 1
-  %tmp20611 = getelementptr inbounds float* %tmp20610, i64 1
-  %tmp20612 = getelementptr inbounds float* %tmp20611, i64 1
-  %tmp20613 = getelementptr inbounds float* %tmp20612, i64 1
-  %tmp20614 = getelementptr inbounds float* %tmp20613, i64 1
-  %tmp20615 = getelementptr inbounds float* %tmp20614, i64 1
-  %tmp20616 = getelementptr inbounds float* %tmp20615, i64 1
-  %tmp20617 = getelementptr inbounds float* %tmp20616, i64 1
-  %tmp20618 = getelementptr inbounds float* %tmp20617, i64 1
-  %tmp20619 = getelementptr inbounds float* %tmp20618, i64 1
-  %tmp20620 = getelementptr inbounds float* %tmp20619, i64 1
-  %tmp20621 = getelementptr inbounds float* %tmp20620, i64 1
-  %tmp20622 = getelementptr inbounds float* %tmp20621, i64 1
-  %tmp20623 = getelementptr inbounds float* %tmp20622, i64 1
-  %tmp20624 = getelementptr inbounds float* %tmp20623, i64 1
-  %tmp20625 = getelementptr inbounds float* %tmp20624, i64 1
-  %tmp20626 = getelementptr inbounds float* %tmp20625, i64 1
-  %tmp20627 = getelementptr inbounds float* %tmp20626, i64 1
-  %tmp20628 = getelementptr inbounds float* %tmp20627, i64 1
-  %tmp20629 = getelementptr inbounds float* %tmp20628, i64 1
-  %tmp20630 = getelementptr inbounds float* %tmp20629, i64 1
-  %tmp20631 = getelementptr inbounds float* %tmp20630, i64 1
-  %tmp20632 = getelementptr inbounds float* %tmp20631, i64 1
-  %tmp20633 = getelementptr inbounds float* %tmp20632, i64 1
-  %tmp20634 = getelementptr inbounds float* %tmp20633, i64 1
-  %tmp20635 = getelementptr inbounds float* %tmp20634, i64 1
-  %tmp20636 = getelementptr inbounds float* %tmp20635, i64 1
-  %tmp20637 = getelementptr inbounds float* %tmp20636, i64 1
-  %tmp20638 = getelementptr inbounds float* %tmp20637, i64 1
-  %tmp20639 = getelementptr inbounds float* %tmp20638, i64 1
-  %tmp20640 = getelementptr inbounds float* %tmp20639, i64 1
-  %tmp20641 = getelementptr inbounds float* %tmp20640, i64 1
-  %tmp20642 = getelementptr inbounds float* %tmp20641, i64 1
-  %tmp20643 = getelementptr inbounds float* %tmp20642, i64 1
-  %tmp20644 = getelementptr inbounds float* %tmp20643, i64 1
-  %tmp20645 = getelementptr inbounds float* %tmp20644, i64 1
-  %tmp20646 = getelementptr inbounds float* %tmp20645, i64 1
-  %tmp20647 = getelementptr inbounds float* %tmp20646, i64 1
-  %tmp20648 = getelementptr inbounds float* %tmp20647, i64 1
-  %tmp20649 = getelementptr inbounds float* %tmp20648, i64 1
-  %tmp20650 = getelementptr inbounds float* %tmp20649, i64 1
-  %tmp20651 = getelementptr inbounds float* %tmp20650, i64 1
-  %tmp20652 = getelementptr inbounds float* %tmp20651, i64 1
-  %tmp20653 = getelementptr inbounds float* %tmp20652, i64 1
-  %tmp20654 = getelementptr inbounds float* %tmp20653, i64 1
-  %tmp20655 = getelementptr inbounds float* %tmp20654, i64 1
-  %tmp20656 = getelementptr inbounds float* %tmp20655, i64 1
-  %tmp20657 = getelementptr inbounds float* %tmp20656, i64 1
-  %tmp20658 = getelementptr inbounds float* %tmp20657, i64 1
-  %tmp20659 = getelementptr inbounds float* %tmp20658, i64 1
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-  %tmp20661 = getelementptr inbounds float* %tmp20660, i64 1
-  %tmp20662 = getelementptr inbounds float* %tmp20661, i64 1
-  %tmp20663 = getelementptr inbounds float* %tmp20662, i64 1
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-  %tmp20666 = getelementptr inbounds float* %tmp20665, i64 1
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-  %tmp20669 = getelementptr inbounds float* %tmp20668, i64 1
-  %tmp20670 = getelementptr inbounds float* %tmp20669, i64 1
-  %tmp20671 = getelementptr inbounds float* %tmp20670, i64 1
-  %tmp20672 = getelementptr inbounds float* %tmp20671, i64 1
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-  %tmp20674 = getelementptr inbounds float* %tmp20673, i64 1
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-  %tmp20720 = getelementptr inbounds float* %tmp20719, i64 1
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-  %tmp20722 = getelementptr inbounds float* %tmp20721, i64 1
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-  %tmp20746 = getelementptr inbounds float* %tmp20745, i64 1
-  %tmp20747 = getelementptr inbounds float* %tmp20746, i64 1
-  %tmp20748 = getelementptr inbounds float* %tmp20747, i64 1
-  %tmp20749 = getelementptr inbounds float* %tmp20748, i64 1
-  %tmp20750 = getelementptr inbounds float* %tmp20749, i64 1
-  %tmp20751 = getelementptr inbounds float* %tmp20750, i64 1
-  %tmp20752 = getelementptr inbounds float* %tmp20751, i64 1
-  %tmp20753 = getelementptr inbounds float* %tmp20752, i64 1
-  %tmp20754 = getelementptr inbounds float* %tmp20753, i64 1
-  %tmp20755 = getelementptr inbounds float* %tmp20754, i64 1
-  %tmp20756 = getelementptr inbounds float* %tmp20755, i64 1
-  %tmp20757 = getelementptr inbounds float* %tmp20756, i64 1
-  %tmp20758 = getelementptr inbounds float* %tmp20757, i64 1
-  %tmp20759 = getelementptr inbounds float* %tmp20758, i64 1
-  %tmp20760 = getelementptr inbounds float* %tmp20759, i64 1
-  %tmp20761 = getelementptr inbounds float* %tmp20760, i64 1
-  %tmp20762 = getelementptr inbounds float* %tmp20761, i64 1
-  %tmp20763 = getelementptr inbounds float* %tmp20762, i64 1
-  %tmp20764 = getelementptr inbounds float* %tmp20763, i64 1
-  %tmp20765 = getelementptr inbounds float* %tmp20764, i64 1
-  %tmp20766 = getelementptr inbounds float* %tmp20765, i64 1
-  %tmp20767 = getelementptr inbounds float* %tmp20766, i64 1
-  %tmp20768 = getelementptr inbounds float* %tmp20767, i64 1
-  %tmp20769 = getelementptr inbounds float* %tmp20768, i64 1
-  %tmp20770 = getelementptr inbounds float* %tmp20769, i64 1
-  %tmp20771 = getelementptr inbounds float* %tmp20770, i64 1
-  %tmp20772 = getelementptr inbounds float* %tmp20771, i64 1
-  %tmp20773 = getelementptr inbounds float* %tmp20772, i64 1
-  %tmp20774 = getelementptr inbounds float* %tmp20773, i64 1
-  %tmp20775 = getelementptr inbounds float* %tmp20774, i64 1
-  %tmp20776 = getelementptr inbounds float* %tmp20775, i64 1
-  %tmp20777 = getelementptr inbounds float* %tmp20776, i64 1
-  %tmp20778 = getelementptr inbounds float* %tmp20777, i64 1
-  %tmp20779 = getelementptr inbounds float* %tmp20778, i64 1
-  %tmp20780 = getelementptr inbounds float* %tmp20779, i64 1
-  %tmp20781 = getelementptr inbounds float* %tmp20780, i64 1
-  %tmp20782 = getelementptr inbounds float* %tmp20781, i64 1
-  %tmp20783 = getelementptr inbounds float* %tmp20782, i64 1
-  %tmp20784 = getelementptr inbounds float* %tmp20783, i64 1
-  %tmp20785 = getelementptr inbounds float* %tmp20784, i64 1
-  %tmp20786 = getelementptr inbounds float* %tmp20785, i64 1
-  %tmp20787 = getelementptr inbounds float* %tmp20786, i64 1
-  %tmp20788 = getelementptr inbounds float* %tmp20787, i64 1
-  %tmp20789 = getelementptr inbounds float* %tmp20788, i64 1
-  %tmp20790 = getelementptr inbounds float* %tmp20789, i64 1
-  %tmp20791 = getelementptr inbounds float* %tmp20790, i64 1
-  %tmp20792 = getelementptr inbounds float* %tmp20791, i64 1
-  %tmp20793 = getelementptr inbounds float* %tmp20792, i64 1
-  %tmp20794 = getelementptr inbounds float* %tmp20793, i64 1
-  %tmp20795 = getelementptr inbounds float* %tmp20794, i64 1
-  %tmp20796 = getelementptr inbounds float* %tmp20795, i64 1
-  %tmp20797 = getelementptr inbounds float* %tmp20796, i64 1
-  %tmp20798 = getelementptr inbounds float* %tmp20797, i64 1
-  %tmp20799 = getelementptr inbounds float* %tmp20798, i64 1
-  %tmp20800 = getelementptr inbounds float* %tmp20799, i64 1
-  %tmp20801 = getelementptr inbounds float* %tmp20800, i64 1
-  %tmp20802 = getelementptr inbounds float* %tmp20801, i64 1
-  %tmp20803 = getelementptr inbounds float* %tmp20802, i64 1
-  %tmp20804 = getelementptr inbounds float* %tmp20803, i64 1
-  %tmp20805 = getelementptr inbounds float* %tmp20804, i64 1
-  %tmp20806 = getelementptr inbounds float* %tmp20805, i64 1
-  %tmp20807 = getelementptr inbounds float* %tmp20806, i64 1
-  %tmp20808 = getelementptr inbounds float* %tmp20807, i64 1
-  %tmp20809 = getelementptr inbounds float* %tmp20808, i64 1
-  %tmp20810 = getelementptr inbounds float* %tmp20809, i64 1
-  %tmp20811 = getelementptr inbounds float* %tmp20810, i64 1
-  %tmp20812 = getelementptr inbounds float* %tmp20811, i64 1
-  %tmp20813 = getelementptr inbounds float* %tmp20812, i64 1
-  %tmp20814 = getelementptr inbounds float* %tmp20813, i64 1
-  %tmp20815 = getelementptr inbounds float* %tmp20814, i64 1
-  %tmp20816 = getelementptr inbounds float* %tmp20815, i64 1
-  %tmp20817 = getelementptr inbounds float* %tmp20816, i64 1
-  %tmp20818 = getelementptr inbounds float* %tmp20817, i64 1
-  %tmp20819 = getelementptr inbounds float* %tmp20818, i64 1
-  %tmp20820 = getelementptr inbounds float* %tmp20819, i64 1
-  %tmp20821 = getelementptr inbounds float* %tmp20820, i64 1
-  %tmp20822 = getelementptr inbounds float* %tmp20821, i64 1
-  %tmp20823 = getelementptr inbounds float* %tmp20822, i64 1
-  %tmp20824 = getelementptr inbounds float* %tmp20823, i64 1
-  %tmp20825 = getelementptr inbounds float* %tmp20824, i64 1
-  %tmp20826 = getelementptr inbounds float* %tmp20825, i64 1
-  %tmp20827 = getelementptr inbounds float* %tmp20826, i64 1
-  %tmp20828 = getelementptr inbounds float* %tmp20827, i64 1
-  %tmp20829 = getelementptr inbounds float* %tmp20828, i64 1
-  %tmp20830 = getelementptr inbounds float* %tmp20829, i64 1
-  %tmp20831 = getelementptr inbounds float* %tmp20830, i64 1
-  %tmp20832 = getelementptr inbounds float* %tmp20831, i64 1
-  %tmp20833 = getelementptr inbounds float* %tmp20832, i64 1
-  %tmp20834 = getelementptr inbounds float* %tmp20833, i64 1
-  %tmp20835 = getelementptr inbounds float* %tmp20834, i64 1
-  %tmp20836 = getelementptr inbounds float* %tmp20835, i64 1
-  %tmp20837 = getelementptr inbounds float* %tmp20836, i64 1
-  %tmp20838 = getelementptr inbounds float* %tmp20837, i64 1
-  %tmp20839 = getelementptr inbounds float* %tmp20838, i64 1
-  %tmp20840 = getelementptr inbounds float* %tmp20839, i64 1
-  %tmp20841 = getelementptr inbounds float* %tmp20840, i64 1
-  %tmp20842 = getelementptr inbounds float* %tmp20841, i64 1
-  %tmp20843 = getelementptr inbounds float* %tmp20842, i64 1
-  %tmp20844 = getelementptr inbounds float* %tmp20843, i64 1
-  %tmp20845 = getelementptr inbounds float* %tmp20844, i64 1
-  %tmp20846 = getelementptr inbounds float* %tmp20845, i64 1
-  %tmp20847 = getelementptr inbounds float* %tmp20846, i64 1
-  %tmp20848 = getelementptr inbounds float* %tmp20847, i64 1
-  %tmp20849 = getelementptr inbounds float* %tmp20848, i64 1
-  %tmp20850 = getelementptr inbounds float* %tmp20849, i64 1
-  %tmp20851 = getelementptr inbounds float* %tmp20850, i64 1
-  %tmp20852 = getelementptr inbounds float* %tmp20851, i64 1
-  %tmp20853 = getelementptr inbounds float* %tmp20852, i64 1
-  %tmp20854 = getelementptr inbounds float* %tmp20853, i64 1
-  %tmp20855 = getelementptr inbounds float* %tmp20854, i64 1
-  %tmp20856 = getelementptr inbounds float* %tmp20855, i64 1
-  %tmp20857 = getelementptr inbounds float* %tmp20856, i64 1
-  %tmp20858 = getelementptr inbounds float* %tmp20857, i64 1
-  %tmp20859 = getelementptr inbounds float* %tmp20858, i64 1
-  %tmp20860 = getelementptr inbounds float* %tmp20859, i64 1
-  %tmp20861 = getelementptr inbounds float* %tmp20860, i64 1
-  %tmp20862 = getelementptr inbounds float* %tmp20861, i64 1
-  %tmp20863 = getelementptr inbounds float* %tmp20862, i64 1
-  %tmp20864 = getelementptr inbounds float* %tmp20863, i64 1
-  %tmp20865 = getelementptr inbounds float* %tmp20864, i64 1
-  %tmp20866 = getelementptr inbounds float* %tmp20865, i64 1
-  %tmp20867 = getelementptr inbounds float* %tmp20866, i64 1
-  %tmp20868 = getelementptr inbounds float* %tmp20867, i64 1
-  %tmp20869 = getelementptr inbounds float* %tmp20868, i64 1
-  %tmp20870 = getelementptr inbounds float* %tmp20869, i64 1
-  %tmp20871 = getelementptr inbounds float* %tmp20870, i64 1
-  %tmp20872 = getelementptr inbounds float* %tmp20871, i64 1
-  %tmp20873 = getelementptr inbounds float* %tmp20872, i64 1
-  %tmp20874 = getelementptr inbounds float* %tmp20873, i64 1
-  %tmp20875 = getelementptr inbounds float* %tmp20874, i64 1
-  %tmp20876 = getelementptr inbounds float* %tmp20875, i64 1
-  %tmp20877 = getelementptr inbounds float* %tmp20876, i64 1
-  %tmp20878 = getelementptr inbounds float* %tmp20877, i64 1
-  %tmp20879 = getelementptr inbounds float* %tmp20878, i64 1
-  %tmp20880 = getelementptr inbounds float* %tmp20879, i64 1
-  %tmp20881 = getelementptr inbounds float* %tmp20880, i64 1
-  %tmp20882 = getelementptr inbounds float* %tmp20881, i64 1
-  %tmp20883 = getelementptr inbounds float* %tmp20882, i64 1
-  %tmp20884 = getelementptr inbounds float* %tmp20883, i64 1
-  %tmp20885 = getelementptr inbounds float* %tmp20884, i64 1
-  %tmp20886 = getelementptr inbounds float* %tmp20885, i64 1
-  %tmp20887 = getelementptr inbounds float* %tmp20886, i64 1
-  %tmp20888 = getelementptr inbounds float* %tmp20887, i64 1
-  %tmp20889 = getelementptr inbounds float* %tmp20888, i64 1
-  %tmp20890 = getelementptr inbounds float* %tmp20889, i64 1
-  %tmp20891 = getelementptr inbounds float* %tmp20890, i64 1
-  %tmp20892 = getelementptr inbounds float* %tmp20891, i64 1
-  %tmp20893 = getelementptr inbounds float* %tmp20892, i64 1
-  %tmp20894 = getelementptr inbounds float* %tmp20893, i64 1
-  %tmp20895 = getelementptr inbounds float* %tmp20894, i64 1
-  %tmp20896 = getelementptr inbounds float* %tmp20895, i64 1
-  %tmp20897 = getelementptr inbounds float* %tmp20896, i64 1
-  %tmp20898 = getelementptr inbounds float* %tmp20897, i64 1
-  %tmp20899 = getelementptr inbounds float* %tmp20898, i64 1
-  %tmp20900 = getelementptr inbounds float* %tmp20899, i64 1
-  %tmp20901 = getelementptr inbounds float* %tmp20900, i64 1
-  %tmp20902 = getelementptr inbounds float* %tmp20901, i64 1
-  %tmp20903 = getelementptr inbounds float* %tmp20902, i64 1
-  %tmp20904 = getelementptr inbounds float* %tmp20903, i64 1
-  %tmp20905 = getelementptr inbounds float* %tmp20904, i64 1
-  %tmp20906 = getelementptr inbounds float* %tmp20905, i64 1
-  %tmp20907 = getelementptr inbounds float* %tmp20906, i64 1
-  %tmp20908 = getelementptr inbounds float* %tmp20907, i64 1
-  %tmp20909 = getelementptr inbounds float* %tmp20908, i64 1
-  %tmp20910 = getelementptr inbounds float* %tmp20909, i64 1
-  %tmp20911 = getelementptr inbounds float* %tmp20910, i64 1
-  %tmp20912 = getelementptr inbounds float* %tmp20911, i64 1
-  %tmp20913 = getelementptr inbounds float* %tmp20912, i64 1
-  %tmp20914 = getelementptr inbounds float* %tmp20913, i64 1
-  %tmp20915 = getelementptr inbounds float* %tmp20914, i64 1
-  %tmp20916 = getelementptr inbounds float* %tmp20915, i64 1
-  %tmp20917 = getelementptr inbounds float* %tmp20916, i64 1
-  %tmp20918 = getelementptr inbounds float* %tmp20917, i64 1
-  %tmp20919 = getelementptr inbounds float* %tmp20918, i64 1
-  %tmp20920 = getelementptr inbounds float* %tmp20919, i64 1
-  %tmp20921 = getelementptr inbounds float* %tmp20920, i64 1
-  %tmp20922 = getelementptr inbounds float* %tmp20921, i64 1
-  %tmp20923 = getelementptr inbounds float* %tmp20922, i64 1
-  %tmp20924 = getelementptr inbounds float* %tmp20923, i64 1
-  %tmp20925 = getelementptr inbounds float* %tmp20924, i64 1
-  %tmp20926 = getelementptr inbounds float* %tmp20925, i64 1
-  %tmp20927 = getelementptr inbounds float* %tmp20926, i64 1
-  %tmp20928 = getelementptr inbounds float* %tmp20927, i64 1
-  %tmp20929 = getelementptr inbounds float* %tmp20928, i64 1
-  %tmp20930 = getelementptr inbounds float* %tmp20929, i64 1
-  %tmp20931 = getelementptr inbounds float* %tmp20930, i64 1
-  %tmp20932 = getelementptr inbounds float* %tmp20931, i64 1
-  %tmp20933 = getelementptr inbounds float* %tmp20932, i64 1
-  %tmp20934 = getelementptr inbounds float* %tmp20933, i64 1
-  %tmp20935 = getelementptr inbounds float* %tmp20934, i64 1
-  %tmp20936 = getelementptr inbounds float* %tmp20935, i64 1
-  %tmp20937 = getelementptr inbounds float* %tmp20936, i64 1
-  %tmp20938 = getelementptr inbounds float* %tmp20937, i64 1
-  %tmp20939 = getelementptr inbounds float* %tmp20938, i64 1
-  %tmp20940 = getelementptr inbounds float* %tmp20939, i64 1
-  %tmp20941 = getelementptr inbounds float* %tmp20940, i64 1
-  %tmp20942 = getelementptr inbounds float* %tmp20941, i64 1
-  %tmp20943 = getelementptr inbounds float* %tmp20942, i64 1
-  %tmp20944 = getelementptr inbounds float* %tmp20943, i64 1
-  %tmp20945 = getelementptr inbounds float* %tmp20944, i64 1
-  %tmp20946 = getelementptr inbounds float* %tmp20945, i64 1
-  %tmp20947 = getelementptr inbounds float* %tmp20946, i64 1
-  %tmp20948 = getelementptr inbounds float* %tmp20947, i64 1
-  %tmp20949 = getelementptr inbounds float* %tmp20948, i64 1
-  %tmp20950 = getelementptr inbounds float* %tmp20949, i64 1
-  %tmp20951 = getelementptr inbounds float* %tmp20950, i64 1
-  %tmp20952 = getelementptr inbounds float* %tmp20951, i64 1
-  %tmp20953 = getelementptr inbounds float* %tmp20952, i64 1
-  %tmp20954 = getelementptr inbounds float* %tmp20953, i64 1
-  %tmp20955 = getelementptr inbounds float* %tmp20954, i64 1
-  %tmp20956 = getelementptr inbounds float* %tmp20955, i64 1
-  %tmp20957 = getelementptr inbounds float* %tmp20956, i64 1
-  %tmp20958 = getelementptr inbounds float* %tmp20957, i64 1
-  %tmp20959 = getelementptr inbounds float* %tmp20958, i64 1
-  %tmp20960 = getelementptr inbounds float* %tmp20959, i64 1
-  %tmp20961 = getelementptr inbounds float* %tmp20960, i64 1
-  %tmp20962 = getelementptr inbounds float* %tmp20961, i64 1
-  %tmp20963 = getelementptr inbounds float* %tmp20962, i64 1
-  %tmp20964 = getelementptr inbounds float* %tmp20963, i64 1
-  %tmp20965 = getelementptr inbounds float* %tmp20964, i64 1
-  %tmp20966 = getelementptr inbounds float* %tmp20965, i64 1
-  %tmp20967 = getelementptr inbounds float* %tmp20966, i64 1
-  %tmp20968 = getelementptr inbounds float* %tmp20967, i64 1
-  %tmp20969 = getelementptr inbounds float* %tmp20968, i64 1
-  %tmp20970 = getelementptr inbounds float* %tmp20969, i64 1
-  %tmp20971 = getelementptr inbounds float* %tmp20970, i64 1
-  %tmp20972 = getelementptr inbounds float* %tmp20971, i64 1
-  %tmp20973 = getelementptr inbounds float* %tmp20972, i64 1
-  %tmp20974 = getelementptr inbounds float* %tmp20973, i64 1
-  %tmp20975 = getelementptr inbounds float* %tmp20974, i64 1
-  %tmp20976 = getelementptr inbounds float* %tmp20975, i64 1
-  %tmp20977 = getelementptr inbounds float* %tmp20976, i64 1
-  %tmp20978 = getelementptr inbounds float* %tmp20977, i64 1
-  %tmp20979 = getelementptr inbounds float* %tmp20978, i64 1
-  %tmp20980 = getelementptr inbounds float* %tmp20979, i64 1
-  %tmp20981 = getelementptr inbounds float* %tmp20980, i64 1
-  %tmp20982 = getelementptr inbounds float* %tmp20981, i64 1
-  %tmp20983 = getelementptr inbounds float* %tmp20982, i64 1
-  %tmp20984 = getelementptr inbounds float* %tmp20983, i64 1
-  %tmp20985 = getelementptr inbounds float* %tmp20984, i64 1
-  %tmp20986 = getelementptr inbounds float* %tmp20985, i64 1
-  %tmp20987 = getelementptr inbounds float* %tmp20986, i64 1
-  %tmp20988 = getelementptr inbounds float* %tmp20987, i64 1
-  %tmp20989 = getelementptr inbounds float* %tmp20988, i64 1
-  %tmp20990 = getelementptr inbounds float* %tmp20989, i64 1
-  %tmp20991 = getelementptr inbounds float* %tmp20990, i64 1
-  %tmp20992 = getelementptr inbounds float* %tmp20991, i64 1
-  %tmp20993 = getelementptr inbounds float* %tmp20992, i64 1
-  %tmp20994 = getelementptr inbounds float* %tmp20993, i64 1
-  %tmp20995 = getelementptr inbounds float* %tmp20994, i64 1
-  %tmp20996 = getelementptr inbounds float* %tmp20995, i64 1
-  %tmp20997 = getelementptr inbounds float* %tmp20996, i64 1
-  %tmp20998 = getelementptr inbounds float* %tmp20997, i64 1
-  %tmp20999 = getelementptr inbounds float* %tmp20998, i64 1
-  %tmp21000 = getelementptr inbounds float* %tmp20999, i64 1
-  %tmp21001 = getelementptr inbounds float* %tmp21000, i64 1
-  %tmp21002 = getelementptr inbounds float* %tmp21001, i64 1
-  %tmp21003 = getelementptr inbounds float* %tmp21002, i64 1
-  %tmp21004 = getelementptr inbounds float* %tmp21003, i64 1
-  %tmp21005 = getelementptr inbounds float* %tmp21004, i64 1
-  %tmp21006 = getelementptr inbounds float* %tmp21005, i64 1
-  %tmp21007 = getelementptr inbounds float* %tmp21006, i64 1
-  %tmp21008 = getelementptr inbounds float* %tmp21007, i64 1
-  %tmp21009 = getelementptr inbounds float* %tmp21008, i64 1
-  %tmp21010 = getelementptr inbounds float* %tmp21009, i64 1
-  %tmp21011 = getelementptr inbounds float* %tmp21010, i64 1
-  %tmp21012 = getelementptr inbounds float* %tmp21011, i64 1
-  %tmp21013 = getelementptr inbounds float* %tmp21012, i64 1
-  %tmp21014 = getelementptr inbounds float* %tmp21013, i64 1
-  %tmp21015 = getelementptr inbounds float* %tmp21014, i64 1
-  %tmp21016 = getelementptr inbounds float* %tmp21015, i64 1
-  %tmp21017 = getelementptr inbounds float* %tmp21016, i64 1
-  %tmp21018 = getelementptr inbounds float* %tmp21017, i64 1
-  %tmp21019 = getelementptr inbounds float* %tmp21018, i64 1
-  %tmp21020 = getelementptr inbounds float* %tmp21019, i64 1
-  %tmp21021 = getelementptr inbounds float* %tmp21020, i64 1
-  %tmp21022 = getelementptr inbounds float* %tmp21021, i64 1
-  %tmp21023 = getelementptr inbounds float* %tmp21022, i64 1
-  %tmp21024 = getelementptr inbounds float* %tmp21023, i64 1
-  %tmp21025 = getelementptr inbounds float* %tmp21024, i64 1
-  %tmp21026 = getelementptr inbounds float* %tmp21025, i64 1
-  %tmp21027 = getelementptr inbounds float* %tmp21026, i64 1
-  %tmp21028 = getelementptr inbounds float* %tmp21027, i64 1
-  %tmp21029 = getelementptr inbounds float* %tmp21028, i64 1
-  %tmp21030 = getelementptr inbounds float* %tmp21029, i64 1
-  %tmp21031 = getelementptr inbounds float* %tmp21030, i64 1
-  %tmp21032 = getelementptr inbounds float* %tmp21031, i64 1
-  %tmp21033 = getelementptr inbounds float* %tmp21032, i64 1
-  %tmp21034 = getelementptr inbounds float* %tmp21033, i64 1
-  %tmp21035 = getelementptr inbounds float* %tmp21034, i64 1
-  %tmp21036 = getelementptr inbounds float* %tmp21035, i64 1
-  %tmp21037 = getelementptr inbounds float* %tmp21036, i64 1
-  %tmp21038 = getelementptr inbounds float* %tmp21037, i64 1
-  %tmp21039 = getelementptr inbounds float* %tmp21038, i64 1
-  %tmp21040 = getelementptr inbounds float* %tmp21039, i64 1
-  %tmp21041 = getelementptr inbounds float* %tmp21040, i64 1
-  %tmp21042 = getelementptr inbounds float* %tmp21041, i64 1
-  %tmp21043 = getelementptr inbounds float* %tmp21042, i64 1
-  %tmp21044 = getelementptr inbounds float* %tmp21043, i64 1
-  %tmp21045 = getelementptr inbounds float* %tmp21044, i64 1
-  %tmp21046 = getelementptr inbounds float* %tmp21045, i64 1
-  %tmp21047 = getelementptr inbounds float* %tmp21046, i64 1
-  %tmp21048 = getelementptr inbounds float* %tmp21047, i64 1
-  %tmp21049 = getelementptr inbounds float* %tmp21048, i64 1
-  %tmp21050 = getelementptr inbounds float* %tmp21049, i64 1
-  %tmp21051 = getelementptr inbounds float* %tmp21050, i64 1
-  %tmp21052 = getelementptr inbounds float* %tmp21051, i64 1
-  %tmp21053 = getelementptr inbounds float* %tmp21052, i64 1
-  %tmp21054 = getelementptr inbounds float* %tmp21053, i64 1
-  %tmp21055 = getelementptr inbounds float* %tmp21054, i64 1
-  %tmp21056 = getelementptr inbounds float* %tmp21055, i64 1
-  %tmp21057 = getelementptr inbounds float* %tmp21056, i64 1
-  %tmp21058 = getelementptr inbounds float* %tmp21057, i64 1
-  %tmp21059 = getelementptr inbounds float* %tmp21058, i64 1
-  %tmp21060 = getelementptr inbounds float* %tmp21059, i64 1
-  %tmp21061 = getelementptr inbounds float* %tmp21060, i64 1
-  %tmp21062 = getelementptr inbounds float* %tmp21061, i64 1
-  %tmp21063 = getelementptr inbounds float* %tmp21062, i64 1
-  %tmp21064 = getelementptr inbounds float* %tmp21063, i64 1
-  %tmp21065 = getelementptr inbounds float* %tmp21064, i64 1
-  %tmp21066 = getelementptr inbounds float* %tmp21065, i64 1
-  %tmp21067 = getelementptr inbounds float* %tmp21066, i64 1
-  %tmp21068 = getelementptr inbounds float* %tmp21067, i64 1
-  %tmp21069 = getelementptr inbounds float* %tmp21068, i64 1
-  %tmp21070 = getelementptr inbounds float* %tmp21069, i64 1
-  %tmp21071 = getelementptr inbounds float* %tmp21070, i64 1
-  %tmp21072 = getelementptr inbounds float* %tmp21071, i64 1
-  %tmp21073 = getelementptr inbounds float* %tmp21072, i64 1
-  %tmp21074 = getelementptr inbounds float* %tmp21073, i64 1
-  %tmp21075 = getelementptr inbounds float* %tmp21074, i64 1
-  %tmp21076 = getelementptr inbounds float* %tmp21075, i64 1
-  %tmp21077 = getelementptr inbounds float* %tmp21076, i64 1
-  %tmp21078 = getelementptr inbounds float* %tmp21077, i64 1
-  %tmp21079 = getelementptr inbounds float* %tmp21078, i64 1
-  %tmp21080 = getelementptr inbounds float* %tmp21079, i64 1
-  %tmp21081 = getelementptr inbounds float* %tmp21080, i64 1
-  %tmp21082 = getelementptr inbounds float* %tmp21081, i64 1
-  %tmp21083 = getelementptr inbounds float* %tmp21082, i64 1
-  %tmp21084 = getelementptr inbounds float* %tmp21083, i64 1
-  %tmp21085 = getelementptr inbounds float* %tmp21084, i64 1
-  %tmp21086 = getelementptr inbounds float* %tmp21085, i64 1
-  %tmp21087 = getelementptr inbounds float* %tmp21086, i64 1
-  %tmp21088 = getelementptr inbounds float* %tmp21087, i64 1
-  %tmp21089 = getelementptr inbounds float* %tmp21088, i64 1
-  %tmp21090 = getelementptr inbounds float* %tmp21089, i64 1
-  %tmp21091 = getelementptr inbounds float* %tmp21090, i64 1
-  %tmp21092 = getelementptr inbounds float* %tmp21091, i64 1
-  %tmp21093 = getelementptr inbounds float* %tmp21092, i64 1
-  %tmp21094 = getelementptr inbounds float* %tmp21093, i64 1
-  %tmp21095 = getelementptr inbounds float* %tmp21094, i64 1
-  %tmp21096 = getelementptr inbounds float* %tmp21095, i64 1
-  %tmp21097 = getelementptr inbounds float* %tmp21096, i64 1
-  %tmp21098 = getelementptr inbounds float* %tmp21097, i64 1
-  %tmp21099 = getelementptr inbounds float* %tmp21098, i64 1
-  %tmp21100 = getelementptr inbounds float* %tmp21099, i64 1
-  %tmp21101 = getelementptr inbounds float* %tmp21100, i64 1
-  %tmp21102 = getelementptr inbounds float* %tmp21101, i64 1
-  %tmp21103 = getelementptr inbounds float* %tmp21102, i64 1
-  %tmp21104 = getelementptr inbounds float* %tmp21103, i64 1
-  %tmp21105 = getelementptr inbounds float* %tmp21104, i64 1
-  %tmp21106 = getelementptr inbounds float* %tmp21105, i64 1
-  %tmp21107 = getelementptr inbounds float* %tmp21106, i64 1
-  %tmp21108 = getelementptr inbounds float* %tmp21107, i64 1
-  %tmp21109 = getelementptr inbounds float* %tmp21108, i64 1
-  %tmp21110 = getelementptr inbounds float* %tmp21109, i64 1
-  %tmp21111 = getelementptr inbounds float* %tmp21110, i64 1
-  %tmp21112 = getelementptr inbounds float* %tmp21111, i64 1
-  %tmp21113 = getelementptr inbounds float* %tmp21112, i64 1
-  %tmp21114 = getelementptr inbounds float* %tmp21113, i64 1
-  %tmp21115 = getelementptr inbounds float* %tmp21114, i64 1
-  %tmp21116 = getelementptr inbounds float* %tmp21115, i64 1
-  %tmp21117 = getelementptr inbounds float* %tmp21116, i64 1
-  %tmp21118 = getelementptr inbounds float* %tmp21117, i64 1
-  %tmp21119 = getelementptr inbounds float* %tmp21118, i64 1
-  %tmp21120 = getelementptr inbounds float* %tmp21119, i64 1
-  %tmp21121 = getelementptr inbounds float* %tmp21120, i64 1
-  %tmp21122 = getelementptr inbounds float* %tmp21121, i64 1
-  %tmp21123 = getelementptr inbounds float* %tmp21122, i64 1
-  %tmp21124 = getelementptr inbounds float* %tmp21123, i64 1
-  %tmp21125 = getelementptr inbounds float* %tmp21124, i64 1
-  %tmp21126 = getelementptr inbounds float* %tmp21125, i64 1
-  %tmp21127 = getelementptr inbounds float* %tmp21126, i64 1
-  %tmp21128 = getelementptr inbounds float* %tmp21127, i64 1
-  %tmp21129 = getelementptr inbounds float* %tmp21128, i64 1
-  %tmp21130 = getelementptr inbounds float* %tmp21129, i64 1
-  %tmp21131 = getelementptr inbounds float* %tmp21130, i64 1
-  %tmp21132 = getelementptr inbounds float* %tmp21131, i64 1
-  %tmp21133 = getelementptr inbounds float* %tmp21132, i64 1
-  %tmp21134 = getelementptr inbounds float* %tmp21133, i64 1
-  %tmp21135 = getelementptr inbounds float* %tmp21134, i64 1
-  %tmp21136 = getelementptr inbounds float* %tmp21135, i64 1
-  %tmp21137 = getelementptr inbounds float* %tmp21136, i64 1
-  %tmp21138 = getelementptr inbounds float* %tmp21137, i64 1
-  %tmp21139 = getelementptr inbounds float* %tmp21138, i64 1
-  %tmp21140 = getelementptr inbounds float* %tmp21139, i64 1
-  %tmp21141 = getelementptr inbounds float* %tmp21140, i64 1
-  %tmp21142 = getelementptr inbounds float* %tmp21141, i64 1
-  %tmp21143 = getelementptr inbounds float* %tmp21142, i64 1
-  %tmp21144 = getelementptr inbounds float* %tmp21143, i64 1
-  %tmp21145 = getelementptr inbounds float* %tmp21144, i64 1
-  %tmp21146 = getelementptr inbounds float* %tmp21145, i64 1
-  %tmp21147 = getelementptr inbounds float* %tmp21146, i64 1
-  %tmp21148 = getelementptr inbounds float* %tmp21147, i64 1
-  %tmp21149 = getelementptr inbounds float* %tmp21148, i64 1
-  %tmp21150 = getelementptr inbounds float* %tmp21149, i64 1
-  %tmp21151 = getelementptr inbounds float* %tmp21150, i64 1
-  %tmp21152 = getelementptr inbounds float* %tmp21151, i64 1
-  %tmp21153 = getelementptr inbounds float* %tmp21152, i64 1
-  %tmp21154 = getelementptr inbounds float* %tmp21153, i64 1
-  %tmp21155 = getelementptr inbounds float* %tmp21154, i64 1
-  %tmp21156 = getelementptr inbounds float* %tmp21155, i64 1
-  %tmp21157 = getelementptr inbounds float* %tmp21156, i64 1
-  %tmp21158 = getelementptr inbounds float* %tmp21157, i64 1
-  %tmp21159 = getelementptr inbounds float* %tmp21158, i64 1
-  %tmp21160 = getelementptr inbounds float* %tmp21159, i64 1
-  %tmp21161 = getelementptr inbounds float* %tmp21160, i64 1
-  %tmp21162 = getelementptr inbounds float* %tmp21161, i64 1
-  %tmp21163 = getelementptr inbounds float* %tmp21162, i64 1
-  %tmp21164 = getelementptr inbounds float* %tmp21163, i64 1
-  %tmp21165 = getelementptr inbounds float* %tmp21164, i64 1
-  %tmp21166 = getelementptr inbounds float* %tmp21165, i64 1
-  %tmp21167 = getelementptr inbounds float* %tmp21166, i64 1
-  %tmp21168 = getelementptr inbounds float* %tmp21167, i64 1
-  %tmp21169 = getelementptr inbounds float* %tmp21168, i64 1
-  %tmp21170 = getelementptr inbounds float* %tmp21169, i64 1
-  %tmp21171 = getelementptr inbounds float* %tmp21170, i64 1
-  %tmp21172 = getelementptr inbounds float* %tmp21171, i64 1
-  %tmp21173 = getelementptr inbounds float* %tmp21172, i64 1
-  %tmp21174 = getelementptr inbounds float* %tmp21173, i64 1
-  %tmp21175 = getelementptr inbounds float* %tmp21174, i64 1
-  %tmp21176 = getelementptr inbounds float* %tmp21175, i64 1
-  %tmp21177 = getelementptr inbounds float* %tmp21176, i64 1
-  %tmp21178 = getelementptr inbounds float* %tmp21177, i64 1
-  %tmp21179 = getelementptr inbounds float* %tmp21178, i64 1
-  %tmp21180 = getelementptr inbounds float* %tmp21179, i64 1
-  %tmp21181 = getelementptr inbounds float* %tmp21180, i64 1
-  %tmp21182 = getelementptr inbounds float* %tmp21181, i64 1
-  %tmp21183 = getelementptr inbounds float* %tmp21182, i64 1
-  %tmp21184 = getelementptr inbounds float* %tmp21183, i64 1
-  %tmp21185 = getelementptr inbounds float* %tmp21184, i64 1
-  %tmp21186 = getelementptr inbounds float* %tmp21185, i64 1
-  %tmp21187 = getelementptr inbounds float* %tmp21186, i64 1
-  %tmp21188 = getelementptr inbounds float* %tmp21187, i64 1
-  %tmp21189 = getelementptr inbounds float* %tmp21188, i64 1
-  %tmp21190 = getelementptr inbounds float* %tmp21189, i64 1
-  %tmp21191 = getelementptr inbounds float* %tmp21190, i64 1
-  %tmp21192 = getelementptr inbounds float* %tmp21191, i64 1
-  %tmp21193 = getelementptr inbounds float* %tmp21192, i64 1
-  %tmp21194 = getelementptr inbounds float* %tmp21193, i64 1
-  %tmp21195 = getelementptr inbounds float* %tmp21194, i64 1
-  %tmp21196 = getelementptr inbounds float* %tmp21195, i64 1
-  %tmp21197 = getelementptr inbounds float* %tmp21196, i64 1
-  %tmp21198 = getelementptr inbounds float* %tmp21197, i64 1
-  %tmp21199 = getelementptr inbounds float* %tmp21198, i64 1
-  %tmp21200 = getelementptr inbounds float* %tmp21199, i64 1
-  %tmp21201 = getelementptr inbounds float* %tmp21200, i64 1
-  %tmp21202 = getelementptr inbounds float* %tmp21201, i64 1
-  %tmp21203 = getelementptr inbounds float* %tmp21202, i64 1
-  %tmp21204 = getelementptr inbounds float* %tmp21203, i64 1
-  %tmp21205 = getelementptr inbounds float* %tmp21204, i64 1
-  %tmp21206 = getelementptr inbounds float* %tmp21205, i64 1
-  %tmp21207 = getelementptr inbounds float* %tmp21206, i64 1
-  %tmp21208 = getelementptr inbounds float* %tmp21207, i64 1
-  %tmp21209 = getelementptr inbounds float* %tmp21208, i64 1
-  %tmp21210 = getelementptr inbounds float* %tmp21209, i64 1
-  %tmp21211 = getelementptr inbounds float* %tmp21210, i64 1
-  %tmp21212 = getelementptr inbounds float* %tmp21211, i64 1
-  %tmp21213 = getelementptr inbounds float* %tmp21212, i64 1
-  %tmp21214 = getelementptr inbounds float* %tmp21213, i64 1
-  %tmp21215 = getelementptr inbounds float* %tmp21214, i64 1
-  %tmp21216 = getelementptr inbounds float* %tmp21215, i64 1
-  %tmp21217 = getelementptr inbounds float* %tmp21216, i64 1
-  %tmp21218 = getelementptr inbounds float* %tmp21217, i64 1
-  %tmp21219 = getelementptr inbounds float* %tmp21218, i64 1
-  %tmp21220 = getelementptr inbounds float* %tmp21219, i64 1
-  %tmp21221 = getelementptr inbounds float* %tmp21220, i64 1
-  %tmp21222 = getelementptr inbounds float* %tmp21221, i64 1
-  %tmp21223 = getelementptr inbounds float* %tmp21222, i64 1
-  %tmp21224 = getelementptr inbounds float* %tmp21223, i64 1
-  %tmp21225 = getelementptr inbounds float* %tmp21224, i64 1
-  %tmp21226 = getelementptr inbounds float* %tmp21225, i64 1
-  %tmp21227 = getelementptr inbounds float* %tmp21226, i64 1
-  %tmp21228 = getelementptr inbounds float* %tmp21227, i64 1
-  %tmp21229 = getelementptr inbounds float* %tmp21228, i64 1
-  %tmp21230 = getelementptr inbounds float* %tmp21229, i64 1
-  %tmp21231 = getelementptr inbounds float* %tmp21230, i64 1
-  %tmp21232 = getelementptr inbounds float* %tmp21231, i64 1
-  %tmp21233 = getelementptr inbounds float* %tmp21232, i64 1
-  %tmp21234 = getelementptr inbounds float* %tmp21233, i64 1
-  %tmp21235 = getelementptr inbounds float* %tmp21234, i64 1
-  %tmp21236 = getelementptr inbounds float* %tmp21235, i64 1
-  %tmp21237 = getelementptr inbounds float* %tmp21236, i64 1
-  %tmp21238 = getelementptr inbounds float* %tmp21237, i64 1
-  %tmp21239 = getelementptr inbounds float* %tmp21238, i64 1
-  %tmp21240 = getelementptr inbounds float* %tmp21239, i64 1
-  %tmp21241 = getelementptr inbounds float* %tmp21240, i64 1
-  %tmp21242 = getelementptr inbounds float* %tmp21241, i64 1
-  %tmp21243 = getelementptr inbounds float* %tmp21242, i64 1
-  %tmp21244 = getelementptr inbounds float* %tmp21243, i64 1
-  %tmp21245 = getelementptr inbounds float* %tmp21244, i64 1
-  %tmp21246 = getelementptr inbounds float* %tmp21245, i64 1
-  %tmp21247 = getelementptr inbounds float* %tmp21246, i64 1
-  %tmp21248 = getelementptr inbounds float* %tmp21247, i64 1
-  %tmp21249 = getelementptr inbounds float* %tmp21248, i64 1
-  %tmp21250 = getelementptr inbounds float* %tmp21249, i64 1
-  %tmp21251 = getelementptr inbounds float* %tmp21250, i64 1
-  %tmp21252 = getelementptr inbounds float* %tmp21251, i64 1
-  %tmp21253 = getelementptr inbounds float* %tmp21252, i64 1
-  %tmp21254 = getelementptr inbounds float* %tmp21253, i64 1
-  %tmp21255 = getelementptr inbounds float* %tmp21254, i64 1
-  %tmp21256 = getelementptr inbounds float* %tmp21255, i64 1
-  %tmp21257 = getelementptr inbounds float* %tmp21256, i64 1
-  %tmp21258 = getelementptr inbounds float* %tmp21257, i64 1
-  %tmp21259 = getelementptr inbounds float* %tmp21258, i64 1
-  %tmp21260 = getelementptr inbounds float* %tmp21259, i64 1
-  %tmp21261 = getelementptr inbounds float* %tmp21260, i64 1
-  %tmp21262 = getelementptr inbounds float* %tmp21261, i64 1
-  %tmp21263 = getelementptr inbounds float* %tmp21262, i64 1
-  %tmp21264 = getelementptr inbounds float* %tmp21263, i64 1
-  %tmp21265 = getelementptr inbounds float* %tmp21264, i64 1
-  %tmp21266 = getelementptr inbounds float* %tmp21265, i64 1
-  %tmp21267 = getelementptr inbounds float* %tmp21266, i64 1
-  %tmp21268 = getelementptr inbounds float* %tmp21267, i64 1
-  %tmp21269 = getelementptr inbounds float* %tmp21268, i64 1
-  %tmp21270 = getelementptr inbounds float* %tmp21269, i64 1
-  %tmp21271 = getelementptr inbounds float* %tmp21270, i64 1
-  %tmp21272 = getelementptr inbounds float* %tmp21271, i64 1
-  %tmp21273 = getelementptr inbounds float* %tmp21272, i64 1
-  %tmp21274 = getelementptr inbounds float* %tmp21273, i64 1
-  %tmp21275 = getelementptr inbounds float* %tmp21274, i64 1
-  %tmp21276 = getelementptr inbounds float* %tmp21275, i64 1
-  %tmp21277 = getelementptr inbounds float* %tmp21276, i64 1
-  %tmp21278 = getelementptr inbounds float* %tmp21277, i64 1
-  %tmp21279 = getelementptr inbounds float* %tmp21278, i64 1
-  %tmp21280 = getelementptr inbounds float* %tmp21279, i64 1
-  %tmp21281 = getelementptr inbounds float* %tmp21280, i64 1
-  %tmp21282 = getelementptr inbounds float* %tmp21281, i64 1
-  %tmp21283 = getelementptr inbounds float* %tmp21282, i64 1
-  %tmp21284 = getelementptr inbounds float* %tmp21283, i64 1
-  %tmp21285 = getelementptr inbounds float* %tmp21284, i64 1
-  %tmp21286 = getelementptr inbounds float* %tmp21285, i64 1
-  %tmp21287 = getelementptr inbounds float* %tmp21286, i64 1
-  %tmp21288 = getelementptr inbounds float* %tmp21287, i64 1
-  %tmp21289 = getelementptr inbounds float* %tmp21288, i64 1
-  %tmp21290 = getelementptr inbounds float* %tmp21289, i64 1
-  %tmp21291 = getelementptr inbounds float* %tmp21290, i64 1
-  %tmp21292 = getelementptr inbounds float* %tmp21291, i64 1
-  %tmp21293 = getelementptr inbounds float* %tmp21292, i64 1
-  %tmp21294 = getelementptr inbounds float* %tmp21293, i64 1
-  %tmp21295 = getelementptr inbounds float* %tmp21294, i64 1
-  %tmp21296 = getelementptr inbounds float* %tmp21295, i64 1
-  %tmp21297 = getelementptr inbounds float* %tmp21296, i64 1
-  %tmp21298 = getelementptr inbounds float* %tmp21297, i64 1
-  %tmp21299 = getelementptr inbounds float* %tmp21298, i64 1
-  %tmp21300 = getelementptr inbounds float* %tmp21299, i64 1
-  %tmp21301 = getelementptr inbounds float* %tmp21300, i64 1
-  %tmp21302 = getelementptr inbounds float* %tmp21301, i64 1
-  %tmp21303 = getelementptr inbounds float* %tmp21302, i64 1
-  %tmp21304 = getelementptr inbounds float* %tmp21303, i64 1
-  %tmp21305 = getelementptr inbounds float* %tmp21304, i64 1
-  %tmp21306 = getelementptr inbounds float* %tmp21305, i64 1
-  %tmp21307 = getelementptr inbounds float* %tmp21306, i64 1
-  %tmp21308 = getelementptr inbounds float* %tmp21307, i64 1
-  %tmp21309 = getelementptr inbounds float* %tmp21308, i64 1
-  %tmp21310 = getelementptr inbounds float* %tmp21309, i64 1
-  %tmp21311 = getelementptr inbounds float* %tmp21310, i64 1
-  %tmp21312 = getelementptr inbounds float* %tmp21311, i64 1
-  %tmp21313 = getelementptr inbounds float* %tmp21312, i64 1
-  %tmp21314 = getelementptr inbounds float* %tmp21313, i64 1
-  %tmp21315 = getelementptr inbounds float* %tmp21314, i64 1
-  %tmp21316 = getelementptr inbounds float* %tmp21315, i64 1
-  %tmp21317 = getelementptr inbounds float* %tmp21316, i64 1
-  %tmp21318 = getelementptr inbounds float* %tmp21317, i64 1
-  %tmp21319 = getelementptr inbounds float* %tmp21318, i64 1
-  %tmp21320 = getelementptr inbounds float* %tmp21319, i64 1
-  %tmp21321 = getelementptr inbounds float* %tmp21320, i64 1
-  %tmp21322 = getelementptr inbounds float* %tmp21321, i64 1
-  %tmp21323 = getelementptr inbounds float* %tmp21322, i64 1
-  %tmp21324 = getelementptr inbounds float* %tmp21323, i64 1
-  %tmp21325 = getelementptr inbounds float* %tmp21324, i64 1
-  %tmp21326 = getelementptr inbounds float* %tmp21325, i64 1
-  %tmp21327 = getelementptr inbounds float* %tmp21326, i64 1
-  %tmp21328 = getelementptr inbounds float* %tmp21327, i64 1
-  %tmp21329 = getelementptr inbounds float* %tmp21328, i64 1
-  %tmp21330 = getelementptr inbounds float* %tmp21329, i64 1
-  %tmp21331 = getelementptr inbounds float* %tmp21330, i64 1
-  %tmp21332 = getelementptr inbounds float* %tmp21331, i64 1
-  %tmp21333 = getelementptr inbounds float* %tmp21332, i64 1
-  %tmp21334 = getelementptr inbounds float* %tmp21333, i64 1
-  %tmp21335 = getelementptr inbounds float* %tmp21334, i64 1
-  %tmp21336 = getelementptr inbounds float* %tmp21335, i64 1
-  %tmp21337 = getelementptr inbounds float* %tmp21336, i64 1
-  %tmp21338 = getelementptr inbounds float* %tmp21337, i64 1
-  %tmp21339 = getelementptr inbounds float* %tmp21338, i64 1
-  %tmp21340 = getelementptr inbounds float* %tmp21339, i64 1
-  %tmp21341 = getelementptr inbounds float* %tmp21340, i64 1
-  %tmp21342 = getelementptr inbounds float* %tmp21341, i64 1
-  %tmp21343 = getelementptr inbounds float* %tmp21342, i64 1
-  %tmp21344 = getelementptr inbounds float* %tmp21343, i64 1
-  %tmp21345 = getelementptr inbounds float* %tmp21344, i64 1
-  %tmp21346 = getelementptr inbounds float* %tmp21345, i64 1
-  %tmp21347 = getelementptr inbounds float* %tmp21346, i64 1
-  %tmp21348 = getelementptr inbounds float* %tmp21347, i64 1
-  %tmp21349 = getelementptr inbounds float* %tmp21348, i64 1
-  %tmp21350 = getelementptr inbounds float* %tmp21349, i64 1
-  %tmp21351 = getelementptr inbounds float* %tmp21350, i64 1
-  %tmp21352 = getelementptr inbounds float* %tmp21351, i64 1
-  %tmp21353 = getelementptr inbounds float* %tmp21352, i64 1
-  %tmp21354 = getelementptr inbounds float* %tmp21353, i64 1
-  %tmp21355 = getelementptr inbounds float* %tmp21354, i64 1
-  %tmp21356 = getelementptr inbounds float* %tmp21355, i64 1
-  %tmp21357 = getelementptr inbounds float* %tmp21356, i64 1
-  %tmp21358 = getelementptr inbounds float* %tmp21357, i64 1
-  %tmp21359 = getelementptr inbounds float* %tmp21358, i64 1
-  %tmp21360 = getelementptr inbounds float* %tmp21359, i64 1
-  %tmp21361 = getelementptr inbounds float* %tmp21360, i64 1
-  %tmp21362 = getelementptr inbounds float* %tmp21361, i64 1
-  %tmp21363 = getelementptr inbounds float* %tmp21362, i64 1
-  %tmp21364 = getelementptr inbounds float* %tmp21363, i64 1
-  %tmp21365 = getelementptr inbounds float* %tmp21364, i64 1
-  %tmp21366 = getelementptr inbounds float* %tmp21365, i64 1
-  %tmp21367 = getelementptr inbounds float* %tmp21366, i64 1
-  %tmp21368 = getelementptr inbounds float* %tmp21367, i64 1
-  %tmp21369 = getelementptr inbounds float* %tmp21368, i64 1
-  %tmp21370 = getelementptr inbounds float* %tmp21369, i64 1
-  %tmp21371 = getelementptr inbounds float* %tmp21370, i64 1
-  %tmp21372 = getelementptr inbounds float* %tmp21371, i64 1
-  %tmp21373 = getelementptr inbounds float* %tmp21372, i64 1
-  %tmp21374 = getelementptr inbounds float* %tmp21373, i64 1
-  %tmp21375 = getelementptr inbounds float* %tmp21374, i64 1
-  %tmp21376 = getelementptr inbounds float* %tmp21375, i64 1
-  %tmp21377 = getelementptr inbounds float* %tmp21376, i64 1
-  %tmp21378 = getelementptr inbounds float* %tmp21377, i64 1
-  %tmp21379 = getelementptr inbounds float* %tmp21378, i64 1
-  %tmp21380 = getelementptr inbounds float* %tmp21379, i64 1
-  %tmp21381 = getelementptr inbounds float* %tmp21380, i64 1
-  %tmp21382 = getelementptr inbounds float* %tmp21381, i64 1
-  %tmp21383 = getelementptr inbounds float* %tmp21382, i64 1
-  %tmp21384 = getelementptr inbounds float* %tmp21383, i64 1
-  %tmp21385 = getelementptr inbounds float* %tmp21384, i64 1
-  %tmp21386 = getelementptr inbounds float* %tmp21385, i64 1
-  %tmp21387 = getelementptr inbounds float* %tmp21386, i64 1
-  %tmp21388 = getelementptr inbounds float* %tmp21387, i64 1
-  %tmp21389 = getelementptr inbounds float* %tmp21388, i64 1
-  %tmp21390 = getelementptr inbounds float* %tmp21389, i64 1
-  %tmp21391 = getelementptr inbounds float* %tmp21390, i64 1
-  %tmp21392 = getelementptr inbounds float* %tmp21391, i64 1
-  %tmp21393 = getelementptr inbounds float* %tmp21392, i64 1
-  %tmp21394 = getelementptr inbounds float* %tmp21393, i64 1
-  %tmp21395 = getelementptr inbounds float* %tmp21394, i64 1
-  %tmp21396 = getelementptr inbounds float* %tmp21395, i64 1
-  %tmp21397 = getelementptr inbounds float* %tmp21396, i64 1
-  %tmp21398 = getelementptr inbounds float* %tmp21397, i64 1
-  %tmp21399 = getelementptr inbounds float* %tmp21398, i64 1
-  %tmp21400 = getelementptr inbounds float* %tmp21399, i64 1
-  %tmp21401 = getelementptr inbounds float* %tmp21400, i64 1
-  %tmp21402 = getelementptr inbounds float* %tmp21401, i64 1
-  %tmp21403 = getelementptr inbounds float* %tmp21402, i64 1
-  %tmp21404 = getelementptr inbounds float* %tmp21403, i64 1
-  %tmp21405 = getelementptr inbounds float* %tmp21404, i64 1
-  %tmp21406 = getelementptr inbounds float* %tmp21405, i64 1
-  %tmp21407 = getelementptr inbounds float* %tmp21406, i64 1
-  %tmp21408 = getelementptr inbounds float* %tmp21407, i64 1
-  %tmp21409 = getelementptr inbounds float* %tmp21408, i64 1
-  %tmp21410 = getelementptr inbounds float* %tmp21409, i64 1
-  %tmp21411 = getelementptr inbounds float* %tmp21410, i64 1
-  %tmp21412 = getelementptr inbounds float* %tmp21411, i64 1
-  %tmp21413 = getelementptr inbounds float* %tmp21412, i64 1
-  %tmp21414 = getelementptr inbounds float* %tmp21413, i64 1
-  %tmp21415 = getelementptr inbounds float* %tmp21414, i64 1
-  %tmp21416 = getelementptr inbounds float* %tmp21415, i64 1
-  %tmp21417 = getelementptr inbounds float* %tmp21416, i64 1
-  %tmp21418 = getelementptr inbounds float* %tmp21417, i64 1
-  %tmp21419 = getelementptr inbounds float* %tmp21418, i64 1
-  %tmp21420 = getelementptr inbounds float* %tmp21419, i64 1
-  %tmp21421 = getelementptr inbounds float* %tmp21420, i64 1
-  %tmp21422 = getelementptr inbounds float* %tmp21421, i64 1
-  %tmp21423 = getelementptr inbounds float* %tmp21422, i64 1
-  %tmp21424 = getelementptr inbounds float* %tmp21423, i64 1
-  %tmp21425 = getelementptr inbounds float* %tmp21424, i64 1
-  %tmp21426 = getelementptr inbounds float* %tmp21425, i64 1
-  %tmp21427 = getelementptr inbounds float* %tmp21426, i64 1
-  %tmp21428 = getelementptr inbounds float* %tmp21427, i64 1
-  %tmp21429 = getelementptr inbounds float* %tmp21428, i64 1
-  %tmp21430 = getelementptr inbounds float* %tmp21429, i64 1
-  %tmp21431 = getelementptr inbounds float* %tmp21430, i64 1
-  %tmp21432 = getelementptr inbounds float* %tmp21431, i64 1
-  %tmp21433 = getelementptr inbounds float* %tmp21432, i64 1
-  %tmp21434 = getelementptr inbounds float* %tmp21433, i64 1
-  %tmp21435 = getelementptr inbounds float* %tmp21434, i64 1
-  %tmp21436 = getelementptr inbounds float* %tmp21435, i64 1
-  %tmp21437 = getelementptr inbounds float* %tmp21436, i64 1
-  %tmp21438 = getelementptr inbounds float* %tmp21437, i64 1
-  %tmp21439 = getelementptr inbounds float* %tmp21438, i64 1
-  %tmp21440 = getelementptr inbounds float* %tmp21439, i64 1
-  %tmp21441 = getelementptr inbounds float* %tmp21440, i64 1
-  %tmp21442 = getelementptr inbounds float* %tmp21441, i64 1
-  %tmp21443 = getelementptr inbounds float* %tmp21442, i64 1
-  %tmp21444 = getelementptr inbounds float* %tmp21443, i64 1
-  %tmp21445 = getelementptr inbounds float* %tmp21444, i64 1
-  %tmp21446 = getelementptr inbounds float* %tmp21445, i64 1
-  %tmp21447 = getelementptr inbounds float* %tmp21446, i64 1
-  %tmp21448 = getelementptr inbounds float* %tmp21447, i64 1
-  %tmp21449 = getelementptr inbounds float* %tmp21448, i64 1
-  %tmp21450 = getelementptr inbounds float* %tmp21449, i64 1
-  %tmp21451 = getelementptr inbounds float* %tmp21450, i64 1
-  %tmp21452 = getelementptr inbounds float* %tmp21451, i64 1
-  %tmp21453 = getelementptr inbounds float* %tmp21452, i64 1
-  %tmp21454 = getelementptr inbounds float* %tmp21453, i64 1
-  %tmp21455 = getelementptr inbounds float* %tmp21454, i64 1
-  %tmp21456 = getelementptr inbounds float* %tmp21455, i64 1
-  %tmp21457 = getelementptr inbounds float* %tmp21456, i64 1
-  %tmp21458 = getelementptr inbounds float* %tmp21457, i64 1
-  %tmp21459 = getelementptr inbounds float* %tmp21458, i64 1
-  %tmp21460 = getelementptr inbounds float* %tmp21459, i64 1
-  %tmp21461 = getelementptr inbounds float* %tmp21460, i64 1
-  %tmp21462 = getelementptr inbounds float* %tmp21461, i64 1
-  %tmp21463 = getelementptr inbounds float* %tmp21462, i64 1
-  %tmp21464 = getelementptr inbounds float* %tmp21463, i64 1
-  %tmp21465 = getelementptr inbounds float* %tmp21464, i64 1
-  %tmp21466 = getelementptr inbounds float* %tmp21465, i64 1
-  %tmp21467 = getelementptr inbounds float* %tmp21466, i64 1
-  %tmp21468 = getelementptr inbounds float* %tmp21467, i64 1
-  %tmp21469 = getelementptr inbounds float* %tmp21468, i64 1
-  %tmp21470 = getelementptr inbounds float* %tmp21469, i64 1
-  %tmp21471 = getelementptr inbounds float* %tmp21470, i64 1
-  %tmp21472 = getelementptr inbounds float* %tmp21471, i64 1
-  %tmp21473 = getelementptr inbounds float* %tmp21472, i64 1
-  %tmp21474 = getelementptr inbounds float* %tmp21473, i64 1
-  %tmp21475 = getelementptr inbounds float* %tmp21474, i64 1
-  %tmp21476 = getelementptr inbounds float* %tmp21475, i64 1
-  %tmp21477 = getelementptr inbounds float* %tmp21476, i64 1
-  %tmp21478 = getelementptr inbounds float* %tmp21477, i64 1
-  %tmp21479 = getelementptr inbounds float* %tmp21478, i64 1
-  %tmp21480 = getelementptr inbounds float* %tmp21479, i64 1
-  %tmp21481 = getelementptr inbounds float* %tmp21480, i64 1
-  %tmp21482 = getelementptr inbounds float* %tmp21481, i64 1
-  %tmp21483 = getelementptr inbounds float* %tmp21482, i64 1
-  %tmp21484 = getelementptr inbounds float* %tmp21483, i64 1
-  %tmp21485 = getelementptr inbounds float* %tmp21484, i64 1
-  %tmp21486 = getelementptr inbounds float* %tmp21485, i64 1
-  %tmp21487 = getelementptr inbounds float* %tmp21486, i64 1
-  %tmp21488 = getelementptr inbounds float* %tmp21487, i64 1
-  %tmp21489 = getelementptr inbounds float* %tmp21488, i64 1
-  %tmp21490 = getelementptr inbounds float* %tmp21489, i64 1
-  %tmp21491 = getelementptr inbounds float* %tmp21490, i64 1
-  %tmp21492 = getelementptr inbounds float* %tmp21491, i64 1
-  %tmp21493 = getelementptr inbounds float* %tmp21492, i64 1
-  %tmp21494 = getelementptr inbounds float* %tmp21493, i64 1
-  %tmp21495 = getelementptr inbounds float* %tmp21494, i64 1
-  %tmp21496 = getelementptr inbounds float* %tmp21495, i64 1
-  %tmp21497 = getelementptr inbounds float* %tmp21496, i64 1
-  %tmp21498 = getelementptr inbounds float* %tmp21497, i64 1
-  %tmp21499 = getelementptr inbounds float* %tmp21498, i64 1
-  %tmp21500 = getelementptr inbounds float* %tmp21499, i64 1
-  %tmp21501 = getelementptr inbounds float* %tmp21500, i64 1
-  %tmp21502 = getelementptr inbounds float* %tmp21501, i64 1
-  %tmp21503 = getelementptr inbounds float* %tmp21502, i64 1
-  %tmp21504 = getelementptr inbounds float* %tmp21503, i64 1
-  %tmp21505 = getelementptr inbounds float* %tmp21504, i64 1
-  %tmp21506 = getelementptr inbounds float* %tmp21505, i64 1
-  %tmp21507 = getelementptr inbounds float* %tmp21506, i64 1
-  %tmp21508 = getelementptr inbounds float* %tmp21507, i64 1
-  %tmp21509 = getelementptr inbounds float* %tmp21508, i64 1
-  %tmp21510 = getelementptr inbounds float* %tmp21509, i64 1
-  %tmp21511 = getelementptr inbounds float* %tmp21510, i64 1
-  %tmp21512 = getelementptr inbounds float* %tmp21511, i64 1
-  %tmp21513 = getelementptr inbounds float* %tmp21512, i64 1
-  %tmp21514 = getelementptr inbounds float* %tmp21513, i64 1
-  %tmp21515 = getelementptr inbounds float* %tmp21514, i64 1
-  %tmp21516 = getelementptr inbounds float* %tmp21515, i64 1
-  %tmp21517 = getelementptr inbounds float* %tmp21516, i64 1
-  %tmp21518 = getelementptr inbounds float* %tmp21517, i64 1
-  %tmp21519 = getelementptr inbounds float* %tmp21518, i64 1
-  %tmp21520 = getelementptr inbounds float* %tmp21519, i64 1
-  %tmp21521 = getelementptr inbounds float* %tmp21520, i64 1
-  %tmp21522 = getelementptr inbounds float* %tmp21521, i64 1
-  %tmp21523 = getelementptr inbounds float* %tmp21522, i64 1
-  %tmp21524 = getelementptr inbounds float* %tmp21523, i64 1
-  %tmp21525 = getelementptr inbounds float* %tmp21524, i64 1
-  %tmp21526 = getelementptr inbounds float* %tmp21525, i64 1
-  %tmp21527 = getelementptr inbounds float* %tmp21526, i64 1
-  %tmp21528 = getelementptr inbounds float* %tmp21527, i64 1
-  %tmp21529 = getelementptr inbounds float* %tmp21528, i64 1
-  %tmp21530 = getelementptr inbounds float* %tmp21529, i64 1
-  %tmp21531 = getelementptr inbounds float* %tmp21530, i64 1
-  %tmp21532 = getelementptr inbounds float* %tmp21531, i64 1
-  %tmp21533 = getelementptr inbounds float* %tmp21532, i64 1
-  %tmp21534 = getelementptr inbounds float* %tmp21533, i64 1
-  %tmp21535 = getelementptr inbounds float* %tmp21534, i64 1
-  %tmp21536 = getelementptr inbounds float* %tmp21535, i64 1
-  %tmp21537 = getelementptr inbounds float* %tmp21536, i64 1
-  %tmp21538 = getelementptr inbounds float* %tmp21537, i64 1
-  %tmp21539 = getelementptr inbounds float* %tmp21538, i64 1
-  %tmp21540 = getelementptr inbounds float* %tmp21539, i64 1
-  %tmp21541 = getelementptr inbounds float* %tmp21540, i64 1
-  %tmp21542 = getelementptr inbounds float* %tmp21541, i64 1
-  %tmp21543 = getelementptr inbounds float* %tmp21542, i64 1
-  %tmp21544 = getelementptr inbounds float* %tmp21543, i64 1
-  %tmp21545 = getelementptr inbounds float* %tmp21544, i64 1
-  %tmp21546 = getelementptr inbounds float* %tmp21545, i64 1
-  %tmp21547 = getelementptr inbounds float* %tmp21546, i64 1
-  %tmp21548 = getelementptr inbounds float* %tmp21547, i64 1
-  %tmp21549 = getelementptr inbounds float* %tmp21548, i64 1
-  %tmp21550 = getelementptr inbounds float* %tmp21549, i64 1
-  %tmp21551 = getelementptr inbounds float* %tmp21550, i64 1
-  %tmp21552 = getelementptr inbounds float* %tmp21551, i64 1
-  %tmp21553 = getelementptr inbounds float* %tmp21552, i64 1
-  %tmp21554 = getelementptr inbounds float* %tmp21553, i64 1
-  %tmp21555 = getelementptr inbounds float* %tmp21554, i64 1
-  %tmp21556 = getelementptr inbounds float* %tmp21555, i64 1
-  %tmp21557 = getelementptr inbounds float* %tmp21556, i64 1
-  %tmp21558 = getelementptr inbounds float* %tmp21557, i64 1
-  %tmp21559 = getelementptr inbounds float* %tmp21558, i64 1
-  %tmp21560 = getelementptr inbounds float* %tmp21559, i64 1
-  %tmp21561 = getelementptr inbounds float* %tmp21560, i64 1
-  %tmp21562 = getelementptr inbounds float* %tmp21561, i64 1
-  %tmp21563 = getelementptr inbounds float* %tmp21562, i64 1
-  %tmp21564 = getelementptr inbounds float* %tmp21563, i64 1
-  %tmp21565 = getelementptr inbounds float* %tmp21564, i64 1
-  %tmp21566 = getelementptr inbounds float* %tmp21565, i64 1
-  %tmp21567 = getelementptr inbounds float* %tmp21566, i64 1
-  %tmp21568 = getelementptr inbounds float* %tmp21567, i64 1
-  %tmp21569 = getelementptr inbounds float* %tmp21568, i64 1
-  %tmp21570 = getelementptr inbounds float* %tmp21569, i64 1
-  %tmp21571 = getelementptr inbounds float* %tmp21570, i64 1
-  %tmp21572 = getelementptr inbounds float* %tmp21571, i64 1
-  %tmp21573 = getelementptr inbounds float* %tmp21572, i64 1
-  %tmp21574 = getelementptr inbounds float* %tmp21573, i64 1
-  %tmp21575 = getelementptr inbounds float* %tmp21574, i64 1
-  %tmp21576 = getelementptr inbounds float* %tmp21575, i64 1
-  %tmp21577 = getelementptr inbounds float* %tmp21576, i64 1
-  %tmp21578 = getelementptr inbounds float* %tmp21577, i64 1
-  %tmp21579 = getelementptr inbounds float* %tmp21578, i64 1
-  %tmp21580 = getelementptr inbounds float* %tmp21579, i64 1
-  %tmp21581 = getelementptr inbounds float* %tmp21580, i64 1
-  %tmp21582 = getelementptr inbounds float* %tmp21581, i64 1
-  %tmp21583 = getelementptr inbounds float* %tmp21582, i64 1
-  %tmp21584 = getelementptr inbounds float* %tmp21583, i64 1
-  %tmp21585 = getelementptr inbounds float* %tmp21584, i64 1
-  %tmp21586 = getelementptr inbounds float* %tmp21585, i64 1
-  %tmp21587 = getelementptr inbounds float* %tmp21586, i64 1
-  %tmp21588 = getelementptr inbounds float* %tmp21587, i64 1
-  %tmp21589 = getelementptr inbounds float* %tmp21588, i64 1
-  %tmp21590 = getelementptr inbounds float* %tmp21589, i64 1
-  %tmp21591 = getelementptr inbounds float* %tmp21590, i64 1
-  %tmp21592 = getelementptr inbounds float* %tmp21591, i64 1
-  %tmp21593 = getelementptr inbounds float* %tmp21592, i64 1
-  %tmp21594 = getelementptr inbounds float* %tmp21593, i64 1
-  %tmp21595 = getelementptr inbounds float* %tmp21594, i64 1
-  %tmp21596 = getelementptr inbounds float* %tmp21595, i64 1
-  %tmp21597 = getelementptr inbounds float* %tmp21596, i64 1
-  %tmp21598 = getelementptr inbounds float* %tmp21597, i64 1
-  %tmp21599 = getelementptr inbounds float* %tmp21598, i64 1
-  %tmp21600 = getelementptr inbounds float* %tmp21599, i64 1
-  %tmp21601 = getelementptr inbounds float* %tmp21600, i64 1
-  %tmp21602 = getelementptr inbounds float* %tmp21601, i64 1
-  %tmp21603 = getelementptr inbounds float* %tmp21602, i64 1
-  %tmp21604 = getelementptr inbounds float* %tmp21603, i64 1
-  %tmp21605 = getelementptr inbounds float* %tmp21604, i64 1
-  %tmp21606 = getelementptr inbounds float* %tmp21605, i64 1
-  %tmp21607 = getelementptr inbounds float* %tmp21606, i64 1
-  %tmp21608 = getelementptr inbounds float* %tmp21607, i64 1
-  %tmp21609 = getelementptr inbounds float* %tmp21608, i64 1
-  %tmp21610 = getelementptr inbounds float* %tmp21609, i64 1
-  %tmp21611 = getelementptr inbounds float* %tmp21610, i64 1
-  %tmp21612 = getelementptr inbounds float* %tmp21611, i64 1
-  %tmp21613 = getelementptr inbounds float* %tmp21612, i64 1
-  %tmp21614 = getelementptr inbounds float* %tmp21613, i64 1
-  %tmp21615 = getelementptr inbounds float* %tmp21614, i64 1
-  %tmp21616 = getelementptr inbounds float* %tmp21615, i64 1
-  %tmp21617 = getelementptr inbounds float* %tmp21616, i64 1
-  %tmp21618 = getelementptr inbounds float* %tmp21617, i64 1
-  %tmp21619 = getelementptr inbounds float* %tmp21618, i64 1
-  %tmp21620 = getelementptr inbounds float* %tmp21619, i64 1
-  %tmp21621 = getelementptr inbounds float* %tmp21620, i64 1
-  %tmp21622 = getelementptr inbounds float* %tmp21621, i64 1
-  %tmp21623 = getelementptr inbounds float* %tmp21622, i64 1
-  %tmp21624 = getelementptr inbounds float* %tmp21623, i64 1
-  %tmp21625 = getelementptr inbounds float* %tmp21624, i64 1
-  %tmp21626 = getelementptr inbounds float* %tmp21625, i64 1
-  %tmp21627 = getelementptr inbounds float* %tmp21626, i64 1
-  %tmp21628 = getelementptr inbounds float* %tmp21627, i64 1
-  %tmp21629 = getelementptr inbounds float* %tmp21628, i64 1
-  %tmp21630 = getelementptr inbounds float* %tmp21629, i64 1
-  %tmp21631 = getelementptr inbounds float* %tmp21630, i64 1
-  %tmp21632 = getelementptr inbounds float* %tmp21631, i64 1
-  %tmp21633 = getelementptr inbounds float* %tmp21632, i64 1
-  %tmp21634 = getelementptr inbounds float* %tmp21633, i64 1
-  %tmp21635 = getelementptr inbounds float* %tmp21634, i64 1
-  %tmp21636 = getelementptr inbounds float* %tmp21635, i64 1
-  %tmp21637 = getelementptr inbounds float* %tmp21636, i64 1
-  %tmp21638 = getelementptr inbounds float* %tmp21637, i64 1
-  %tmp21639 = getelementptr inbounds float* %tmp21638, i64 1
-  %tmp21640 = getelementptr inbounds float* %tmp21639, i64 1
-  %tmp21641 = getelementptr inbounds float* %tmp21640, i64 1
-  %tmp21642 = getelementptr inbounds float* %tmp21641, i64 1
-  %tmp21643 = getelementptr inbounds float* %tmp21642, i64 1
-  %tmp21644 = getelementptr inbounds float* %tmp21643, i64 1
-  %tmp21645 = getelementptr inbounds float* %tmp21644, i64 1
-  %tmp21646 = getelementptr inbounds float* %tmp21645, i64 1
-  %tmp21647 = getelementptr inbounds float* %tmp21646, i64 1
-  %tmp21648 = getelementptr inbounds float* %tmp21647, i64 1
-  %tmp21649 = getelementptr inbounds float* %tmp21648, i64 1
-  %tmp21650 = getelementptr inbounds float* %tmp21649, i64 1
-  %tmp21651 = getelementptr inbounds float* %tmp21650, i64 1
-  %tmp21652 = getelementptr inbounds float* %tmp21651, i64 1
-  %tmp21653 = getelementptr inbounds float* %tmp21652, i64 1
-  %tmp21654 = getelementptr inbounds float* %tmp21653, i64 1
-  %tmp21655 = getelementptr inbounds float* %tmp21654, i64 1
-  %tmp21656 = getelementptr inbounds float* %tmp21655, i64 1
-  %tmp21657 = getelementptr inbounds float* %tmp21656, i64 1
-  %tmp21658 = getelementptr inbounds float* %tmp21657, i64 1
-  %tmp21659 = getelementptr inbounds float* %tmp21658, i64 1
-  %tmp21660 = getelementptr inbounds float* %tmp21659, i64 1
-  %tmp21661 = getelementptr inbounds float* %tmp21660, i64 1
-  %tmp21662 = getelementptr inbounds float* %tmp21661, i64 1
-  %tmp21663 = getelementptr inbounds float* %tmp21662, i64 1
-  %tmp21664 = getelementptr inbounds float* %tmp21663, i64 1
-  %tmp21665 = getelementptr inbounds float* %tmp21664, i64 1
-  %tmp21666 = getelementptr inbounds float* %tmp21665, i64 1
-  %tmp21667 = getelementptr inbounds float* %tmp21666, i64 1
-  %tmp21668 = getelementptr inbounds float* %tmp21667, i64 1
-  %tmp21669 = getelementptr inbounds float* %tmp21668, i64 1
-  %tmp21670 = getelementptr inbounds float* %tmp21669, i64 1
-  %tmp21671 = getelementptr inbounds float* %tmp21670, i64 1
-  %tmp21672 = getelementptr inbounds float* %tmp21671, i64 1
-  %tmp21673 = getelementptr inbounds float* %tmp21672, i64 1
-  %tmp21674 = getelementptr inbounds float* %tmp21673, i64 1
-  %tmp21675 = getelementptr inbounds float* %tmp21674, i64 1
-  %tmp21676 = getelementptr inbounds float* %tmp21675, i64 1
-  %tmp21677 = getelementptr inbounds float* %tmp21676, i64 1
-  %tmp21678 = getelementptr inbounds float* %tmp21677, i64 1
-  %tmp21679 = getelementptr inbounds float* %tmp21678, i64 1
-  %tmp21680 = getelementptr inbounds float* %tmp21679, i64 1
-  %tmp21681 = getelementptr inbounds float* %tmp21680, i64 1
-  %tmp21682 = getelementptr inbounds float* %tmp21681, i64 1
-  %tmp21683 = getelementptr inbounds float* %tmp21682, i64 1
-  %tmp21684 = getelementptr inbounds float* %tmp21683, i64 1
-  %tmp21685 = getelementptr inbounds float* %tmp21684, i64 1
-  %tmp21686 = getelementptr inbounds float* %tmp21685, i64 1
-  %tmp21687 = getelementptr inbounds float* %tmp21686, i64 1
-  %tmp21688 = getelementptr inbounds float* %tmp21687, i64 1
-  %tmp21689 = getelementptr inbounds float* %tmp21688, i64 1
-  %tmp21690 = getelementptr inbounds float* %tmp21689, i64 1
-  %tmp21691 = getelementptr inbounds float* %tmp21690, i64 1
-  %tmp21692 = getelementptr inbounds float* %tmp21691, i64 1
-  %tmp21693 = getelementptr inbounds float* %tmp21692, i64 1
-  %tmp21694 = getelementptr inbounds float* %tmp21693, i64 1
-  %tmp21695 = getelementptr inbounds float* %tmp21694, i64 1
-  %tmp21696 = getelementptr inbounds float* %tmp21695, i64 1
-  %tmp21697 = getelementptr inbounds float* %tmp21696, i64 1
-  %tmp21698 = getelementptr inbounds float* %tmp21697, i64 1
-  %tmp21699 = getelementptr inbounds float* %tmp21698, i64 1
-  %tmp21700 = getelementptr inbounds float* %tmp21699, i64 1
-  %tmp21701 = getelementptr inbounds float* %tmp21700, i64 1
-  %tmp21702 = getelementptr inbounds float* %tmp21701, i64 1
-  %tmp21703 = getelementptr inbounds float* %tmp21702, i64 1
-  %tmp21704 = getelementptr inbounds float* %tmp21703, i64 1
-  %tmp21705 = getelementptr inbounds float* %tmp21704, i64 1
-  %tmp21706 = getelementptr inbounds float* %tmp21705, i64 1
-  %tmp21707 = getelementptr inbounds float* %tmp21706, i64 1
-  %tmp21708 = getelementptr inbounds float* %tmp21707, i64 1
-  %tmp21709 = getelementptr inbounds float* %tmp21708, i64 1
-  %tmp21710 = getelementptr inbounds float* %tmp21709, i64 1
-  %tmp21711 = getelementptr inbounds float* %tmp21710, i64 1
-  %tmp21712 = getelementptr inbounds float* %tmp21711, i64 1
-  %tmp21713 = getelementptr inbounds float* %tmp21712, i64 1
-  %tmp21714 = getelementptr inbounds float* %tmp21713, i64 1
-  %tmp21715 = getelementptr inbounds float* %tmp21714, i64 1
-  %tmp21716 = getelementptr inbounds float* %tmp21715, i64 1
-  %tmp21717 = getelementptr inbounds float* %tmp21716, i64 1
-  %tmp21718 = getelementptr inbounds float* %tmp21717, i64 1
-  %tmp21719 = getelementptr inbounds float* %tmp21718, i64 1
-  %tmp21720 = getelementptr inbounds float* %tmp21719, i64 1
-  %tmp21721 = getelementptr inbounds float* %tmp21720, i64 1
-  %tmp21722 = getelementptr inbounds float* %tmp21721, i64 1
-  %tmp21723 = getelementptr inbounds float* %tmp21722, i64 1
-  %tmp21724 = getelementptr inbounds float* %tmp21723, i64 1
-  %tmp21725 = getelementptr inbounds float* %tmp21724, i64 1
-  %tmp21726 = getelementptr inbounds float* %tmp21725, i64 1
-  %tmp21727 = getelementptr inbounds float* %tmp21726, i64 1
-  %tmp21728 = getelementptr inbounds float* %tmp21727, i64 1
-  %tmp21729 = getelementptr inbounds float* %tmp21728, i64 1
-  %tmp21730 = getelementptr inbounds float* %tmp21729, i64 1
-  %tmp21731 = getelementptr inbounds float* %tmp21730, i64 1
-  %tmp21732 = getelementptr inbounds float* %tmp21731, i64 1
-  %tmp21733 = getelementptr inbounds float* %tmp21732, i64 1
-  %tmp21734 = getelementptr inbounds float* %tmp21733, i64 1
-  %tmp21735 = getelementptr inbounds float* %tmp21734, i64 1
-  %tmp21736 = getelementptr inbounds float* %tmp21735, i64 1
-  %tmp21737 = getelementptr inbounds float* %tmp21736, i64 1
-  %tmp21738 = getelementptr inbounds float* %tmp21737, i64 1
-  %tmp21739 = getelementptr inbounds float* %tmp21738, i64 1
-  %tmp21740 = getelementptr inbounds float* %tmp21739, i64 1
-  %tmp21741 = getelementptr inbounds float* %tmp21740, i64 1
-  %tmp21742 = getelementptr inbounds float* %tmp21741, i64 1
-  %tmp21743 = getelementptr inbounds float* %tmp21742, i64 1
-  %tmp21744 = getelementptr inbounds float* %tmp21743, i64 1
-  %tmp21745 = getelementptr inbounds float* %tmp21744, i64 1
-  %tmp21746 = getelementptr inbounds float* %tmp21745, i64 1
-  %tmp21747 = getelementptr inbounds float* %tmp21746, i64 1
-  %tmp21748 = getelementptr inbounds float* %tmp21747, i64 1
-  %tmp21749 = getelementptr inbounds float* %tmp21748, i64 1
-  %tmp21750 = getelementptr inbounds float* %tmp21749, i64 1
-  %tmp21751 = getelementptr inbounds float* %tmp21750, i64 1
-  %tmp21752 = getelementptr inbounds float* %tmp21751, i64 1
-  %tmp21753 = getelementptr inbounds float* %tmp21752, i64 1
-  %tmp21754 = getelementptr inbounds float* %tmp21753, i64 1
-  %tmp21755 = getelementptr inbounds float* %tmp21754, i64 1
-  %tmp21756 = getelementptr inbounds float* %tmp21755, i64 1
-  %tmp21757 = getelementptr inbounds float* %tmp21756, i64 1
-  %tmp21758 = getelementptr inbounds float* %tmp21757, i64 1
-  %tmp21759 = getelementptr inbounds float* %tmp21758, i64 1
-  %tmp21760 = getelementptr inbounds float* %tmp21759, i64 1
-  %tmp21761 = getelementptr inbounds float* %tmp21760, i64 1
-  %tmp21762 = getelementptr inbounds float* %tmp21761, i64 1
-  %tmp21763 = getelementptr inbounds float* %tmp21762, i64 1
-  %tmp21764 = getelementptr inbounds float* %tmp21763, i64 1
-  %tmp21765 = getelementptr inbounds float* %tmp21764, i64 1
-  %tmp21766 = getelementptr inbounds float* %tmp21765, i64 1
-  %tmp21767 = getelementptr inbounds float* %tmp21766, i64 1
-  %tmp21768 = getelementptr inbounds float* %tmp21767, i64 1
-  %tmp21769 = getelementptr inbounds float* %tmp21768, i64 1
-  %tmp21770 = getelementptr inbounds float* %tmp21769, i64 1
-  %tmp21771 = getelementptr inbounds float* %tmp21770, i64 1
-  %tmp21772 = getelementptr inbounds float* %tmp21771, i64 1
-  %tmp21773 = getelementptr inbounds float* %tmp21772, i64 1
-  %tmp21774 = getelementptr inbounds float* %tmp21773, i64 1
-  %tmp21775 = getelementptr inbounds float* %tmp21774, i64 1
-  %tmp21776 = getelementptr inbounds float* %tmp21775, i64 1
-  %tmp21777 = getelementptr inbounds float* %tmp21776, i64 1
-  %tmp21778 = getelementptr inbounds float* %tmp21777, i64 1
-  %tmp21779 = getelementptr inbounds float* %tmp21778, i64 1
-  %tmp21780 = getelementptr inbounds float* %tmp21779, i64 1
-  %tmp21781 = getelementptr inbounds float* %tmp21780, i64 1
-  %tmp21782 = getelementptr inbounds float* %tmp21781, i64 1
-  %tmp21783 = getelementptr inbounds float* %tmp21782, i64 1
-  %tmp21784 = getelementptr inbounds float* %tmp21783, i64 1
-  %tmp21785 = getelementptr inbounds float* %tmp21784, i64 1
-  %tmp21786 = getelementptr inbounds float* %tmp21785, i64 1
-  %tmp21787 = getelementptr inbounds float* %tmp21786, i64 1
-  %tmp21788 = getelementptr inbounds float* %tmp21787, i64 1
-  %tmp21789 = getelementptr inbounds float* %tmp21788, i64 1
-  %tmp21790 = getelementptr inbounds float* %tmp21789, i64 1
-  %tmp21791 = getelementptr inbounds float* %tmp21790, i64 1
-  %tmp21792 = getelementptr inbounds float* %tmp21791, i64 1
-  %tmp21793 = getelementptr inbounds float* %tmp21792, i64 1
-  %tmp21794 = getelementptr inbounds float* %tmp21793, i64 1
-  %tmp21795 = getelementptr inbounds float* %tmp21794, i64 1
-  %tmp21796 = getelementptr inbounds float* %tmp21795, i64 1
-  %tmp21797 = getelementptr inbounds float* %tmp21796, i64 1
-  %tmp21798 = getelementptr inbounds float* %tmp21797, i64 1
-  %tmp21799 = getelementptr inbounds float* %tmp21798, i64 1
-  %tmp21800 = getelementptr inbounds float* %tmp21799, i64 1
-  %tmp21801 = getelementptr inbounds float* %tmp21800, i64 1
-  %tmp21802 = getelementptr inbounds float* %tmp21801, i64 1
-  %tmp21803 = getelementptr inbounds float* %tmp21802, i64 1
-  %tmp21804 = getelementptr inbounds float* %tmp21803, i64 1
-  %tmp21805 = getelementptr inbounds float* %tmp21804, i64 1
-  %tmp21806 = getelementptr inbounds float* %tmp21805, i64 1
-  %tmp21807 = getelementptr inbounds float* %tmp21806, i64 1
-  %tmp21808 = getelementptr inbounds float* %tmp21807, i64 1
-  %tmp21809 = getelementptr inbounds float* %tmp21808, i64 1
-  %tmp21810 = getelementptr inbounds float* %tmp21809, i64 1
-  %tmp21811 = getelementptr inbounds float* %tmp21810, i64 1
-  %tmp21812 = getelementptr inbounds float* %tmp21811, i64 1
-  %tmp21813 = getelementptr inbounds float* %tmp21812, i64 1
-  %tmp21814 = getelementptr inbounds float* %tmp21813, i64 1
-  %tmp21815 = getelementptr inbounds float* %tmp21814, i64 1
-  %tmp21816 = getelementptr inbounds float* %tmp21815, i64 1
-  %tmp21817 = getelementptr inbounds float* %tmp21816, i64 1
-  %tmp21818 = getelementptr inbounds float* %tmp21817, i64 1
-  %tmp21819 = getelementptr inbounds float* %tmp21818, i64 1
-  %tmp21820 = getelementptr inbounds float* %tmp21819, i64 1
-  %tmp21821 = getelementptr inbounds float* %tmp21820, i64 1
-  %tmp21822 = getelementptr inbounds float* %tmp21821, i64 1
-  %tmp21823 = getelementptr inbounds float* %tmp21822, i64 1
-  %tmp21824 = getelementptr inbounds float* %tmp21823, i64 1
-  %tmp21825 = getelementptr inbounds float* %tmp21824, i64 1
-  %tmp21826 = getelementptr inbounds float* %tmp21825, i64 1
-  %tmp21827 = getelementptr inbounds float* %tmp21826, i64 1
-  %tmp21828 = getelementptr inbounds float* %tmp21827, i64 1
-  %tmp21829 = getelementptr inbounds float* %tmp21828, i64 1
-  %tmp21830 = getelementptr inbounds float* %tmp21829, i64 1
-  %tmp21831 = getelementptr inbounds float* %tmp21830, i64 1
-  %tmp21832 = getelementptr inbounds float* %tmp21831, i64 1
-  %tmp21833 = getelementptr inbounds float* %tmp21832, i64 1
-  %tmp21834 = getelementptr inbounds float* %tmp21833, i64 1
-  %tmp21835 = getelementptr inbounds float* %tmp21834, i64 1
-  %tmp21836 = getelementptr inbounds float* %tmp21835, i64 1
-  %tmp21837 = getelementptr inbounds float* %tmp21836, i64 1
-  %tmp21838 = getelementptr inbounds float* %tmp21837, i64 1
-  %tmp21839 = getelementptr inbounds float* %tmp21838, i64 1
-  %tmp21840 = getelementptr inbounds float* %tmp21839, i64 1
-  %tmp21841 = getelementptr inbounds float* %tmp21840, i64 1
-  %tmp21842 = getelementptr inbounds float* %tmp21841, i64 1
-  %tmp21843 = getelementptr inbounds float* %tmp21842, i64 1
-  %tmp21844 = getelementptr inbounds float* %tmp21843, i64 1
-  %tmp21845 = getelementptr inbounds float* %tmp21844, i64 1
-  %tmp21846 = getelementptr inbounds float* %tmp21845, i64 1
-  %tmp21847 = getelementptr inbounds float* %tmp21846, i64 1
-  %tmp21848 = getelementptr inbounds float* %tmp21847, i64 1
-  %tmp21849 = getelementptr inbounds float* %tmp21848, i64 1
-  %tmp21850 = getelementptr inbounds float* %tmp21849, i64 1
-  %tmp21851 = getelementptr inbounds float* %tmp21850, i64 1
-  %tmp21852 = getelementptr inbounds float* %tmp21851, i64 1
-  %tmp21853 = getelementptr inbounds float* %tmp21852, i64 1
-  %tmp21854 = getelementptr inbounds float* %tmp21853, i64 1
-  %tmp21855 = getelementptr inbounds float* %tmp21854, i64 1
-  %tmp21856 = getelementptr inbounds float* %tmp21855, i64 1
-  %tmp21857 = getelementptr inbounds float* %tmp21856, i64 1
-  %tmp21858 = getelementptr inbounds float* %tmp21857, i64 1
-  %tmp21859 = getelementptr inbounds float* %tmp21858, i64 1
-  %tmp21860 = getelementptr inbounds float* %tmp21859, i64 1
-  %tmp21861 = getelementptr inbounds float* %tmp21860, i64 1
-  %tmp21862 = getelementptr inbounds float* %tmp21861, i64 1
-  %tmp21863 = getelementptr inbounds float* %tmp21862, i64 1
-  %tmp21864 = getelementptr inbounds float* %tmp21863, i64 1
-  %tmp21865 = getelementptr inbounds float* %tmp21864, i64 1
-  %tmp21866 = getelementptr inbounds float* %tmp21865, i64 1
-  %tmp21867 = getelementptr inbounds float* %tmp21866, i64 1
-  %tmp21868 = getelementptr inbounds float* %tmp21867, i64 1
-  %tmp21869 = getelementptr inbounds float* %tmp21868, i64 1
-  %tmp21870 = getelementptr inbounds float* %tmp21869, i64 1
-  %tmp21871 = getelementptr inbounds float* %tmp21870, i64 1
-  %tmp21872 = getelementptr inbounds float* %tmp21871, i64 1
-  %tmp21873 = getelementptr inbounds float* %tmp21872, i64 1
-  %tmp21874 = getelementptr inbounds float* %tmp21873, i64 1
-  %tmp21875 = getelementptr inbounds float* %tmp21874, i64 1
-  %tmp21876 = getelementptr inbounds float* %tmp21875, i64 1
-  %tmp21877 = getelementptr inbounds float* %tmp21876, i64 1
-  %tmp21878 = getelementptr inbounds float* %tmp21877, i64 1
-  %tmp21879 = getelementptr inbounds float* %tmp21878, i64 1
-  %tmp21880 = getelementptr inbounds float* %tmp21879, i64 1
-  %tmp21881 = getelementptr inbounds float* %tmp21880, i64 1
-  %tmp21882 = getelementptr inbounds float* %tmp21881, i64 1
-  %tmp21883 = getelementptr inbounds float* %tmp21882, i64 1
-  %tmp21884 = getelementptr inbounds float* %tmp21883, i64 1
-  %tmp21885 = getelementptr inbounds float* %tmp21884, i64 1
-  %tmp21886 = getelementptr inbounds float* %tmp21885, i64 1
-  %tmp21887 = getelementptr inbounds float* %tmp21886, i64 1
-  %tmp21888 = getelementptr inbounds float* %tmp21887, i64 1
-  %tmp21889 = getelementptr inbounds float* %tmp21888, i64 1
-  %tmp21890 = getelementptr inbounds float* %tmp21889, i64 1
-  %tmp21891 = getelementptr inbounds float* %tmp21890, i64 1
-  %tmp21892 = getelementptr inbounds float* %tmp21891, i64 1
-  %tmp21893 = getelementptr inbounds float* %tmp21892, i64 1
-  %tmp21894 = getelementptr inbounds float* %tmp21893, i64 1
-  %tmp21895 = getelementptr inbounds float* %tmp21894, i64 1
-  %tmp21896 = getelementptr inbounds float* %tmp21895, i64 1
-  %tmp21897 = getelementptr inbounds float* %tmp21896, i64 1
-  %tmp21898 = getelementptr inbounds float* %tmp21897, i64 1
-  %tmp21899 = getelementptr inbounds float* %tmp21898, i64 1
-  %tmp21900 = getelementptr inbounds float* %tmp21899, i64 1
-  %tmp21901 = getelementptr inbounds float* %tmp21900, i64 1
-  %tmp21902 = getelementptr inbounds float* %tmp21901, i64 1
-  %tmp21903 = getelementptr inbounds float* %tmp21902, i64 1
-  %tmp21904 = getelementptr inbounds float* %tmp21903, i64 1
-  %tmp21905 = getelementptr inbounds float* %tmp21904, i64 1
-  %tmp21906 = getelementptr inbounds float* %tmp21905, i64 1
-  %tmp21907 = getelementptr inbounds float* %tmp21906, i64 1
-  %tmp21908 = getelementptr inbounds float* %tmp21907, i64 1
-  %tmp21909 = getelementptr inbounds float* %tmp21908, i64 1
-  %tmp21910 = getelementptr inbounds float* %tmp21909, i64 1
-  %tmp21911 = getelementptr inbounds float* %tmp21910, i64 1
-  %tmp21912 = getelementptr inbounds float* %tmp21911, i64 1
-  %tmp21913 = getelementptr inbounds float* %tmp21912, i64 1
-  %tmp21914 = getelementptr inbounds float* %tmp21913, i64 1
-  %tmp21915 = getelementptr inbounds float* %tmp21914, i64 1
-  %tmp21916 = getelementptr inbounds float* %tmp21915, i64 1
-  %tmp21917 = getelementptr inbounds float* %tmp21916, i64 1
-  %tmp21918 = getelementptr inbounds float* %tmp21917, i64 1
-  %tmp21919 = getelementptr inbounds float* %tmp21918, i64 1
-  %tmp21920 = getelementptr inbounds float* %tmp21919, i64 1
-  %tmp21921 = getelementptr inbounds float* %tmp21920, i64 1
-  %tmp21922 = getelementptr inbounds float* %tmp21921, i64 1
-  %tmp21923 = getelementptr inbounds float* %tmp21922, i64 1
-  %tmp21924 = getelementptr inbounds float* %tmp21923, i64 1
-  %tmp21925 = getelementptr inbounds float* %tmp21924, i64 1
-  %tmp21926 = getelementptr inbounds float* %tmp21925, i64 1
-  %tmp21927 = getelementptr inbounds float* %tmp21926, i64 1
-  %tmp21928 = getelementptr inbounds float* %tmp21927, i64 1
-  %tmp21929 = getelementptr inbounds float* %tmp21928, i64 1
-  %tmp21930 = getelementptr inbounds float* %tmp21929, i64 1
-  %tmp21931 = getelementptr inbounds float* %tmp21930, i64 1
-  %tmp21932 = getelementptr inbounds float* %tmp21931, i64 1
-  %tmp21933 = getelementptr inbounds float* %tmp21932, i64 1
-  %tmp21934 = getelementptr inbounds float* %tmp21933, i64 1
-  %tmp21935 = getelementptr inbounds float* %tmp21934, i64 1
-  %tmp21936 = getelementptr inbounds float* %tmp21935, i64 1
-  %tmp21937 = getelementptr inbounds float* %tmp21936, i64 1
-  %tmp21938 = getelementptr inbounds float* %tmp21937, i64 1
-  %tmp21939 = getelementptr inbounds float* %tmp21938, i64 1
-  %tmp21940 = getelementptr inbounds float* %tmp21939, i64 1
-  %tmp21941 = getelementptr inbounds float* %tmp21940, i64 1
-  %tmp21942 = getelementptr inbounds float* %tmp21941, i64 1
-  %tmp21943 = getelementptr inbounds float* %tmp21942, i64 1
-  %tmp21944 = getelementptr inbounds float* %tmp21943, i64 1
-  %tmp21945 = getelementptr inbounds float* %tmp21944, i64 1
-  %tmp21946 = getelementptr inbounds float* %tmp21945, i64 1
-  %tmp21947 = getelementptr inbounds float* %tmp21946, i64 1
-  %tmp21948 = getelementptr inbounds float* %tmp21947, i64 1
-  %tmp21949 = getelementptr inbounds float* %tmp21948, i64 1
-  %tmp21950 = getelementptr inbounds float* %tmp21949, i64 1
-  %tmp21951 = getelementptr inbounds float* %tmp21950, i64 1
-  %tmp21952 = getelementptr inbounds float* %tmp21951, i64 1
-  %tmp21953 = getelementptr inbounds float* %tmp21952, i64 1
-  %tmp21954 = getelementptr inbounds float* %tmp21953, i64 1
-  %tmp21955 = getelementptr inbounds float* %tmp21954, i64 1
-  %tmp21956 = getelementptr inbounds float* %tmp21955, i64 1
-  %tmp21957 = getelementptr inbounds float* %tmp21956, i64 1
-  %tmp21958 = getelementptr inbounds float* %tmp21957, i64 1
-  %tmp21959 = getelementptr inbounds float* %tmp21958, i64 1
-  %tmp21960 = getelementptr inbounds float* %tmp21959, i64 1
-  %tmp21961 = getelementptr inbounds float* %tmp21960, i64 1
-  %tmp21962 = getelementptr inbounds float* %tmp21961, i64 1
-  %tmp21963 = getelementptr inbounds float* %tmp21962, i64 1
-  %tmp21964 = getelementptr inbounds float* %tmp21963, i64 1
-  %tmp21965 = getelementptr inbounds float* %tmp21964, i64 1
-  %tmp21966 = getelementptr inbounds float* %tmp21965, i64 1
-  %tmp21967 = getelementptr inbounds float* %tmp21966, i64 1
-  %tmp21968 = getelementptr inbounds float* %tmp21967, i64 1
-  %tmp21969 = getelementptr inbounds float* %tmp21968, i64 1
-  %tmp21970 = getelementptr inbounds float* %tmp21969, i64 1
-  %tmp21971 = getelementptr inbounds float* %tmp21970, i64 1
-  %tmp21972 = getelementptr inbounds float* %tmp21971, i64 1
-  %tmp21973 = getelementptr inbounds float* %tmp21972, i64 1
-  %tmp21974 = getelementptr inbounds float* %tmp21973, i64 1
-  %tmp21975 = getelementptr inbounds float* %tmp21974, i64 1
-  %tmp21976 = getelementptr inbounds float* %tmp21975, i64 1
-  %tmp21977 = getelementptr inbounds float* %tmp21976, i64 1
-  %tmp21978 = getelementptr inbounds float* %tmp21977, i64 1
-  %tmp21979 = getelementptr inbounds float* %tmp21978, i64 1
-  %tmp21980 = getelementptr inbounds float* %tmp21979, i64 1
-  %tmp21981 = getelementptr inbounds float* %tmp21980, i64 1
-  %tmp21982 = getelementptr inbounds float* %tmp21981, i64 1
-  %tmp21983 = getelementptr inbounds float* %tmp21982, i64 1
-  %tmp21984 = getelementptr inbounds float* %tmp21983, i64 1
-  %tmp21985 = getelementptr inbounds float* %tmp21984, i64 1
-  %tmp21986 = getelementptr inbounds float* %tmp21985, i64 1
-  %tmp21987 = getelementptr inbounds float* %tmp21986, i64 1
-  %tmp21988 = getelementptr inbounds float* %tmp21987, i64 1
-  %tmp21989 = getelementptr inbounds float* %tmp21988, i64 1
-  %tmp21990 = getelementptr inbounds float* %tmp21989, i64 1
-  %tmp21991 = getelementptr inbounds float* %tmp21990, i64 1
-  %tmp21992 = getelementptr inbounds float* %tmp21991, i64 1
-  %tmp21993 = getelementptr inbounds float* %tmp21992, i64 1
-  %tmp21994 = getelementptr inbounds float* %tmp21993, i64 1
-  %tmp21995 = getelementptr inbounds float* %tmp21994, i64 1
-  %tmp21996 = getelementptr inbounds float* %tmp21995, i64 1
-  %tmp21997 = getelementptr inbounds float* %tmp21996, i64 1
-  %tmp21998 = getelementptr inbounds float* %tmp21997, i64 1
-  %tmp21999 = getelementptr inbounds float* %tmp21998, i64 1
-  %tmp22000 = getelementptr inbounds float* %tmp21999, i64 1
-  %tmp22001 = getelementptr inbounds float* %tmp22000, i64 1
-  %tmp22002 = getelementptr inbounds float* %tmp22001, i64 1
-  %tmp22003 = getelementptr inbounds float* %tmp22002, i64 1
-  %tmp22004 = getelementptr inbounds float* %tmp22003, i64 1
-  %tmp22005 = getelementptr inbounds float* %tmp22004, i64 1
-  %tmp22006 = getelementptr inbounds float* %tmp22005, i64 1
-  %tmp22007 = getelementptr inbounds float* %tmp22006, i64 1
-  %tmp22008 = getelementptr inbounds float* %tmp22007, i64 1
-  %tmp22009 = getelementptr inbounds float* %tmp22008, i64 1
-  %tmp22010 = getelementptr inbounds float* %tmp22009, i64 1
-  %tmp22011 = getelementptr inbounds float* %tmp22010, i64 1
-  %tmp22012 = getelementptr inbounds float* %tmp22011, i64 1
-  %tmp22013 = getelementptr inbounds float* %tmp22012, i64 1
-  %tmp22014 = getelementptr inbounds float* %tmp22013, i64 1
-  %tmp22015 = getelementptr inbounds float* %tmp22014, i64 1
-  %tmp22016 = getelementptr inbounds float* %tmp22015, i64 1
-  %tmp22017 = getelementptr inbounds float* %tmp22016, i64 1
-  %tmp22018 = getelementptr inbounds float* %tmp22017, i64 1
-  %tmp22019 = getelementptr inbounds float* %tmp22018, i64 1
-  %tmp22020 = getelementptr inbounds float* %tmp22019, i64 1
-  %tmp22021 = getelementptr inbounds float* %tmp22020, i64 1
-  %tmp22022 = getelementptr inbounds float* %tmp22021, i64 1
-  %tmp22023 = getelementptr inbounds float* %tmp22022, i64 1
-  %tmp22024 = getelementptr inbounds float* %tmp22023, i64 1
-  %tmp22025 = getelementptr inbounds float* %tmp22024, i64 1
-  %tmp22026 = getelementptr inbounds float* %tmp22025, i64 1
-  %tmp22027 = getelementptr inbounds float* %tmp22026, i64 1
-  %tmp22028 = getelementptr inbounds float* %tmp22027, i64 1
-  %tmp22029 = getelementptr inbounds float* %tmp22028, i64 1
-  %tmp22030 = getelementptr inbounds float* %tmp22029, i64 1
-  %tmp22031 = getelementptr inbounds float* %tmp22030, i64 1
-  %tmp22032 = getelementptr inbounds float* %tmp22031, i64 1
-  %tmp22033 = getelementptr inbounds float* %tmp22032, i64 1
-  %tmp22034 = getelementptr inbounds float* %tmp22033, i64 1
-  %tmp22035 = getelementptr inbounds float* %tmp22034, i64 1
-  %tmp22036 = getelementptr inbounds float* %tmp22035, i64 1
-  %tmp22037 = getelementptr inbounds float* %tmp22036, i64 1
-  %tmp22038 = getelementptr inbounds float* %tmp22037, i64 1
-  %tmp22039 = getelementptr inbounds float* %tmp22038, i64 1
-  %tmp22040 = getelementptr inbounds float* %tmp22039, i64 1
-  %tmp22041 = getelementptr inbounds float* %tmp22040, i64 1
-  %tmp22042 = getelementptr inbounds float* %tmp22041, i64 1
-  %tmp22043 = getelementptr inbounds float* %tmp22042, i64 1
-  %tmp22044 = getelementptr inbounds float* %tmp22043, i64 1
-  %tmp22045 = getelementptr inbounds float* %tmp22044, i64 1
-  %tmp22046 = getelementptr inbounds float* %tmp22045, i64 1
-  %tmp22047 = getelementptr inbounds float* %tmp22046, i64 1
-  %tmp22048 = getelementptr inbounds float* %tmp22047, i64 1
-  %tmp22049 = getelementptr inbounds float* %tmp22048, i64 1
-  %tmp22050 = getelementptr inbounds float* %tmp22049, i64 1
-  %tmp22051 = getelementptr inbounds float* %tmp22050, i64 1
-  %tmp22052 = getelementptr inbounds float* %tmp22051, i64 1
-  %tmp22053 = getelementptr inbounds float* %tmp22052, i64 1
-  %tmp22054 = getelementptr inbounds float* %tmp22053, i64 1
-  %tmp22055 = getelementptr inbounds float* %tmp22054, i64 1
-  %tmp22056 = getelementptr inbounds float* %tmp22055, i64 1
-  %tmp22057 = getelementptr inbounds float* %tmp22056, i64 1
-  %tmp22058 = getelementptr inbounds float* %tmp22057, i64 1
-  %tmp22059 = getelementptr inbounds float* %tmp22058, i64 1
-  %tmp22060 = getelementptr inbounds float* %tmp22059, i64 1
-  %tmp22061 = getelementptr inbounds float* %tmp22060, i64 1
-  %tmp22062 = getelementptr inbounds float* %tmp22061, i64 1
-  %tmp22063 = getelementptr inbounds float* %tmp22062, i64 1
-  %tmp22064 = getelementptr inbounds float* %tmp22063, i64 1
-  %tmp22065 = getelementptr inbounds float* %tmp22064, i64 1
-  %tmp22066 = getelementptr inbounds float* %tmp22065, i64 1
-  %tmp22067 = getelementptr inbounds float* %tmp22066, i64 1
-  %tmp22068 = getelementptr inbounds float* %tmp22067, i64 1
-  %tmp22069 = getelementptr inbounds float* %tmp22068, i64 1
-  %tmp22070 = getelementptr inbounds float* %tmp22069, i64 1
-  %tmp22071 = getelementptr inbounds float* %tmp22070, i64 1
-  %tmp22072 = getelementptr inbounds float* %tmp22071, i64 1
-  %tmp22073 = getelementptr inbounds float* %tmp22072, i64 1
-  %tmp22074 = getelementptr inbounds float* %tmp22073, i64 1
-  %tmp22075 = getelementptr inbounds float* %tmp22074, i64 1
-  %tmp22076 = getelementptr inbounds float* %tmp22075, i64 1
-  %tmp22077 = getelementptr inbounds float* %tmp22076, i64 1
-  %tmp22078 = getelementptr inbounds float* %tmp22077, i64 1
-  %tmp22079 = getelementptr inbounds float* %tmp22078, i64 1
-  %tmp22080 = getelementptr inbounds float* %tmp22079, i64 1
-  %tmp22081 = getelementptr inbounds float* %tmp22080, i64 1
-  %tmp22082 = getelementptr inbounds float* %tmp22081, i64 1
-  %tmp22083 = getelementptr inbounds float* %tmp22082, i64 1
-  %tmp22084 = getelementptr inbounds float* %tmp22083, i64 1
-  %tmp22085 = getelementptr inbounds float* %tmp22084, i64 1
-  %tmp22086 = getelementptr inbounds float* %tmp22085, i64 1
-  %tmp22087 = getelementptr inbounds float* %tmp22086, i64 1
-  %tmp22088 = getelementptr inbounds float* %tmp22087, i64 1
-  %tmp22089 = getelementptr inbounds float* %tmp22088, i64 1
-  %tmp22090 = getelementptr inbounds float* %tmp22089, i64 1
-  %tmp22091 = getelementptr inbounds float* %tmp22090, i64 1
-  %tmp22092 = getelementptr inbounds float* %tmp22091, i64 1
-  %tmp22093 = getelementptr inbounds float* %tmp22092, i64 1
-  %tmp22094 = getelementptr inbounds float* %tmp22093, i64 1
-  %tmp22095 = getelementptr inbounds float* %tmp22094, i64 1
-  %tmp22096 = getelementptr inbounds float* %tmp22095, i64 1
-  %tmp22097 = getelementptr inbounds float* %tmp22096, i64 1
-  %tmp22098 = getelementptr inbounds float* %tmp22097, i64 1
-  %tmp22099 = getelementptr inbounds float* %tmp22098, i64 1
-  %tmp22100 = getelementptr inbounds float* %tmp22099, i64 1
-  %tmp22101 = getelementptr inbounds float* %tmp22100, i64 1
-  %tmp22102 = getelementptr inbounds float* %tmp22101, i64 1
-  %tmp22103 = getelementptr inbounds float* %tmp22102, i64 1
-  %tmp22104 = getelementptr inbounds float* %tmp22103, i64 1
-  %tmp22105 = getelementptr inbounds float* %tmp22104, i64 1
-  %tmp22106 = getelementptr inbounds float* %tmp22105, i64 1
-  %tmp22107 = getelementptr inbounds float* %tmp22106, i64 1
-  %tmp22108 = getelementptr inbounds float* %tmp22107, i64 1
-  %tmp22109 = getelementptr inbounds float* %tmp22108, i64 1
-  %tmp22110 = getelementptr inbounds float* %tmp22109, i64 1
-  %tmp22111 = getelementptr inbounds float* %tmp22110, i64 1
-  %tmp22112 = getelementptr inbounds float* %tmp22111, i64 1
-  %tmp22113 = getelementptr inbounds float* %tmp22112, i64 1
-  %tmp22114 = getelementptr inbounds float* %tmp22113, i64 1
-  %tmp22115 = getelementptr inbounds float* %tmp22114, i64 1
-  %tmp22116 = getelementptr inbounds float* %tmp22115, i64 1
-  %tmp22117 = getelementptr inbounds float* %tmp22116, i64 1
-  %tmp22118 = getelementptr inbounds float* %tmp22117, i64 1
-  %tmp22119 = getelementptr inbounds float* %tmp22118, i64 1
-  %tmp22120 = getelementptr inbounds float* %tmp22119, i64 1
-  %tmp22121 = getelementptr inbounds float* %tmp22120, i64 1
-  %tmp22122 = getelementptr inbounds float* %tmp22121, i64 1
-  %tmp22123 = getelementptr inbounds float* %tmp22122, i64 1
-  %tmp22124 = getelementptr inbounds float* %tmp22123, i64 1
-  %tmp22125 = getelementptr inbounds float* %tmp22124, i64 1
-  %tmp22126 = getelementptr inbounds float* %tmp22125, i64 1
-  %tmp22127 = getelementptr inbounds float* %tmp22126, i64 1
-  %tmp22128 = getelementptr inbounds float* %tmp22127, i64 1
-  %tmp22129 = getelementptr inbounds float* %tmp22128, i64 1
-  %tmp22130 = getelementptr inbounds float* %tmp22129, i64 1
-  %tmp22131 = getelementptr inbounds float* %tmp22130, i64 1
-  %tmp22132 = getelementptr inbounds float* %tmp22131, i64 1
-  %tmp22133 = getelementptr inbounds float* %tmp22132, i64 1
-  %tmp22134 = getelementptr inbounds float* %tmp22133, i64 1
-  %tmp22135 = getelementptr inbounds float* %tmp22134, i64 1
-  %tmp22136 = getelementptr inbounds float* %tmp22135, i64 1
-  %tmp22137 = getelementptr inbounds float* %tmp22136, i64 1
-  %tmp22138 = getelementptr inbounds float* %tmp22137, i64 1
-  %tmp22139 = getelementptr inbounds float* %tmp22138, i64 1
-  %tmp22140 = getelementptr inbounds float* %tmp22139, i64 1
-  %tmp22141 = getelementptr inbounds float* %tmp22140, i64 1
-  %tmp22142 = getelementptr inbounds float* %tmp22141, i64 1
-  %tmp22143 = getelementptr inbounds float* %tmp22142, i64 1
-  %tmp22144 = getelementptr inbounds float* %tmp22143, i64 1
-  %tmp22145 = getelementptr inbounds float* %tmp22144, i64 1
-  %tmp22146 = getelementptr inbounds float* %tmp22145, i64 1
-  %tmp22147 = getelementptr inbounds float* %tmp22146, i64 1
-  %tmp22148 = getelementptr inbounds float* %tmp22147, i64 1
-  %tmp22149 = getelementptr inbounds float* %tmp22148, i64 1
-  %tmp22150 = getelementptr inbounds float* %tmp22149, i64 1
-  %tmp22151 = getelementptr inbounds float* %tmp22150, i64 1
-  %tmp22152 = getelementptr inbounds float* %tmp22151, i64 1
-  %tmp22153 = getelementptr inbounds float* %tmp22152, i64 1
-  %tmp22154 = getelementptr inbounds float* %tmp22153, i64 1
-  %tmp22155 = getelementptr inbounds float* %tmp22154, i64 1
-  %tmp22156 = getelementptr inbounds float* %tmp22155, i64 1
-  %tmp22157 = getelementptr inbounds float* %tmp22156, i64 1
-  %tmp22158 = getelementptr inbounds float* %tmp22157, i64 1
-  %tmp22159 = getelementptr inbounds float* %tmp22158, i64 1
-  %tmp22160 = getelementptr inbounds float* %tmp22159, i64 1
-  %tmp22161 = getelementptr inbounds float* %tmp22160, i64 1
-  %tmp22162 = getelementptr inbounds float* %tmp22161, i64 1
-  %tmp22163 = getelementptr inbounds float* %tmp22162, i64 1
-  %tmp22164 = getelementptr inbounds float* %tmp22163, i64 1
-  %tmp22165 = getelementptr inbounds float* %tmp22164, i64 1
-  %tmp22166 = getelementptr inbounds float* %tmp22165, i64 1
-  %tmp22167 = getelementptr inbounds float* %tmp22166, i64 1
-  %tmp22168 = getelementptr inbounds float* %tmp22167, i64 1
-  %tmp22169 = getelementptr inbounds float* %tmp22168, i64 1
-  %tmp22170 = getelementptr inbounds float* %tmp22169, i64 1
-  %tmp22171 = getelementptr inbounds float* %tmp22170, i64 1
-  %tmp22172 = getelementptr inbounds float* %tmp22171, i64 1
-  %tmp22173 = getelementptr inbounds float* %tmp22172, i64 1
-  %tmp22174 = getelementptr inbounds float* %tmp22173, i64 1
-  %tmp22175 = getelementptr inbounds float* %tmp22174, i64 1
-  %tmp22176 = getelementptr inbounds float* %tmp22175, i64 1
-  %tmp22177 = getelementptr inbounds float* %tmp22176, i64 1
-  %tmp22178 = getelementptr inbounds float* %tmp22177, i64 1
-  %tmp22179 = getelementptr inbounds float* %tmp22178, i64 1
-  %tmp22180 = getelementptr inbounds float* %tmp22179, i64 1
-  %tmp22181 = getelementptr inbounds float* %tmp22180, i64 1
-  %tmp22182 = getelementptr inbounds float* %tmp22181, i64 1
-  %tmp22183 = getelementptr inbounds float* %tmp22182, i64 1
-  %tmp22184 = getelementptr inbounds float* %tmp22183, i64 1
-  %tmp22185 = getelementptr inbounds float* %tmp22184, i64 1
-  %tmp22186 = getelementptr inbounds float* %tmp22185, i64 1
-  %tmp22187 = getelementptr inbounds float* %tmp22186, i64 1
-  %tmp22188 = getelementptr inbounds float* %tmp22187, i64 1
-  %tmp22189 = getelementptr inbounds float* %tmp22188, i64 1
-  %tmp22190 = getelementptr inbounds float* %tmp22189, i64 1
-  %tmp22191 = getelementptr inbounds float* %tmp22190, i64 1
-  %tmp22192 = getelementptr inbounds float* %tmp22191, i64 1
-  %tmp22193 = getelementptr inbounds float* %tmp22192, i64 1
-  %tmp22194 = getelementptr inbounds float* %tmp22193, i64 1
-  %tmp22195 = getelementptr inbounds float* %tmp22194, i64 1
-  %tmp22196 = getelementptr inbounds float* %tmp22195, i64 1
-  %tmp22197 = getelementptr inbounds float* %tmp22196, i64 1
-  %tmp22198 = getelementptr inbounds float* %tmp22197, i64 1
-  %tmp22199 = getelementptr inbounds float* %tmp22198, i64 1
-  %tmp22200 = getelementptr inbounds float* %tmp22199, i64 1
-  %tmp22201 = getelementptr inbounds float* %tmp22200, i64 1
-  %tmp22202 = getelementptr inbounds float* %tmp22201, i64 1
-  %tmp22203 = getelementptr inbounds float* %tmp22202, i64 1
-  %tmp22204 = getelementptr inbounds float* %tmp22203, i64 1
-  %tmp22205 = getelementptr inbounds float* %tmp22204, i64 1
-  %tmp22206 = getelementptr inbounds float* %tmp22205, i64 1
-  %tmp22207 = getelementptr inbounds float* %tmp22206, i64 1
-  %tmp22208 = getelementptr inbounds float* %tmp22207, i64 1
-  %tmp22209 = getelementptr inbounds float* %tmp22208, i64 1
-  %tmp22210 = getelementptr inbounds float* %tmp22209, i64 1
-  %tmp22211 = getelementptr inbounds float* %tmp22210, i64 1
-  %tmp22212 = getelementptr inbounds float* %tmp22211, i64 1
-  %tmp22213 = getelementptr inbounds float* %tmp22212, i64 1
-  %tmp22214 = getelementptr inbounds float* %tmp22213, i64 1
-  %tmp22215 = getelementptr inbounds float* %tmp22214, i64 1
-  %tmp22216 = getelementptr inbounds float* %tmp22215, i64 1
-  %tmp22217 = getelementptr inbounds float* %tmp22216, i64 1
-  %tmp22218 = getelementptr inbounds float* %tmp22217, i64 1
-  %tmp22219 = getelementptr inbounds float* %tmp22218, i64 1
-  %tmp22220 = getelementptr inbounds float* %tmp22219, i64 1
-  %tmp22221 = getelementptr inbounds float* %tmp22220, i64 1
-  %tmp22222 = getelementptr inbounds float* %tmp22221, i64 1
-  %tmp22223 = getelementptr inbounds float* %tmp22222, i64 1
-  %tmp22224 = getelementptr inbounds float* %tmp22223, i64 1
-  %tmp22225 = getelementptr inbounds float* %tmp22224, i64 1
-  %tmp22226 = getelementptr inbounds float* %tmp22225, i64 1
-  %tmp22227 = getelementptr inbounds float* %tmp22226, i64 1
-  %tmp22228 = getelementptr inbounds float* %tmp22227, i64 1
-  %tmp22229 = getelementptr inbounds float* %tmp22228, i64 1
-  %tmp22230 = getelementptr inbounds float* %tmp22229, i64 1
-  %tmp22231 = getelementptr inbounds float* %tmp22230, i64 1
-  %tmp22232 = getelementptr inbounds float* %tmp22231, i64 1
-  %tmp22233 = getelementptr inbounds float* %tmp22232, i64 1
-  %tmp22234 = getelementptr inbounds float* %tmp22233, i64 1
-  %tmp22235 = getelementptr inbounds float* %tmp22234, i64 1
-  %tmp22236 = getelementptr inbounds float* %tmp22235, i64 1
-  %tmp22237 = getelementptr inbounds float* %tmp22236, i64 1
-  %tmp22238 = getelementptr inbounds float* %tmp22237, i64 1
-  %tmp22239 = getelementptr inbounds float* %tmp22238, i64 1
-  %tmp22240 = getelementptr inbounds float* %tmp22239, i64 1
-  %tmp22241 = getelementptr inbounds float* %tmp22240, i64 1
-  %tmp22242 = getelementptr inbounds float* %tmp22241, i64 1
-  %tmp22243 = getelementptr inbounds float* %tmp22242, i64 1
-  %tmp22244 = getelementptr inbounds float* %tmp22243, i64 1
-  %tmp22245 = getelementptr inbounds float* %tmp22244, i64 1
-  %tmp22246 = getelementptr inbounds float* %tmp22245, i64 1
-  %tmp22247 = getelementptr inbounds float* %tmp22246, i64 1
-  %tmp22248 = getelementptr inbounds float* %tmp22247, i64 1
-  %tmp22249 = getelementptr inbounds float* %tmp22248, i64 1
-  %tmp22250 = getelementptr inbounds float* %tmp22249, i64 1
-  %tmp22251 = getelementptr inbounds float* %tmp22250, i64 1
-  %tmp22252 = getelementptr inbounds float* %tmp22251, i64 1
-  %tmp22253 = getelementptr inbounds float* %tmp22252, i64 1
-  %tmp22254 = getelementptr inbounds float* %tmp22253, i64 1
-  %tmp22255 = getelementptr inbounds float* %tmp22254, i64 1
-  %tmp22256 = getelementptr inbounds float* %tmp22255, i64 1
-  %tmp22257 = getelementptr inbounds float* %tmp22256, i64 1
-  %tmp22258 = getelementptr inbounds float* %tmp22257, i64 1
-  %tmp22259 = getelementptr inbounds float* %tmp22258, i64 1
-  %tmp22260 = getelementptr inbounds float* %tmp22259, i64 1
-  %tmp22261 = getelementptr inbounds float* %tmp22260, i64 1
-  %tmp22262 = getelementptr inbounds float* %tmp22261, i64 1
-  %tmp22263 = getelementptr inbounds float* %tmp22262, i64 1
-  %tmp22264 = getelementptr inbounds float* %tmp22263, i64 1
-  %tmp22265 = getelementptr inbounds float* %tmp22264, i64 1
-  %tmp22266 = getelementptr inbounds float* %tmp22265, i64 1
-  %tmp22267 = getelementptr inbounds float* %tmp22266, i64 1
-  %tmp22268 = getelementptr inbounds float* %tmp22267, i64 1
-  %tmp22269 = getelementptr inbounds float* %tmp22268, i64 1
-  %tmp22270 = getelementptr inbounds float* %tmp22269, i64 1
-  %tmp22271 = getelementptr inbounds float* %tmp22270, i64 1
-  %tmp22272 = getelementptr inbounds float* %tmp22271, i64 1
-  %tmp22273 = getelementptr inbounds float* %tmp22272, i64 1
-  %tmp22274 = getelementptr inbounds float* %tmp22273, i64 1
-  %tmp22275 = getelementptr inbounds float* %tmp22274, i64 1
-  %tmp22276 = getelementptr inbounds float* %tmp22275, i64 1
-  %tmp22277 = getelementptr inbounds float* %tmp22276, i64 1
-  %tmp22278 = getelementptr inbounds float* %tmp22277, i64 1
-  %tmp22279 = getelementptr inbounds float* %tmp22278, i64 1
-  %tmp22280 = getelementptr inbounds float* %tmp22279, i64 1
-  %tmp22281 = getelementptr inbounds float* %tmp22280, i64 1
-  %tmp22282 = getelementptr inbounds float* %tmp22281, i64 1
-  %tmp22283 = getelementptr inbounds float* %tmp22282, i64 1
-  %tmp22284 = getelementptr inbounds float* %tmp22283, i64 1
-  %tmp22285 = getelementptr inbounds float* %tmp22284, i64 1
-  %tmp22286 = getelementptr inbounds float* %tmp22285, i64 1
-  %tmp22287 = getelementptr inbounds float* %tmp22286, i64 1
-  %tmp22288 = getelementptr inbounds float* %tmp22287, i64 1
-  %tmp22289 = getelementptr inbounds float* %tmp22288, i64 1
-  %tmp22290 = getelementptr inbounds float* %tmp22289, i64 1
-  %tmp22291 = getelementptr inbounds float* %tmp22290, i64 1
-  %tmp22292 = getelementptr inbounds float* %tmp22291, i64 1
-  %tmp22293 = getelementptr inbounds float* %tmp22292, i64 1
-  %tmp22294 = getelementptr inbounds float* %tmp22293, i64 1
-  %tmp22295 = getelementptr inbounds float* %tmp22294, i64 1
-  %tmp22296 = getelementptr inbounds float* %tmp22295, i64 1
-  %tmp22297 = getelementptr inbounds float* %tmp22296, i64 1
-  %tmp22298 = getelementptr inbounds float* %tmp22297, i64 1
-  %tmp22299 = getelementptr inbounds float* %tmp22298, i64 1
-  %tmp22300 = getelementptr inbounds float* %tmp22299, i64 1
-  %tmp22301 = getelementptr inbounds float* %tmp22300, i64 1
-  %tmp22302 = getelementptr inbounds float* %tmp22301, i64 1
-  %tmp22303 = getelementptr inbounds float* %tmp22302, i64 1
-  %tmp22304 = getelementptr inbounds float* %tmp22303, i64 1
-  %tmp22305 = getelementptr inbounds float* %tmp22304, i64 1
-  %tmp22306 = getelementptr inbounds float* %tmp22305, i64 1
-  %tmp22307 = getelementptr inbounds float* %tmp22306, i64 1
-  %tmp22308 = getelementptr inbounds float* %tmp22307, i64 1
-  %tmp22309 = getelementptr inbounds float* %tmp22308, i64 1
-  %tmp22310 = getelementptr inbounds float* %tmp22309, i64 1
-  %tmp22311 = getelementptr inbounds float* %tmp22310, i64 1
-  %tmp22312 = getelementptr inbounds float* %tmp22311, i64 1
-  %tmp22313 = getelementptr inbounds float* %tmp22312, i64 1
-  %tmp22314 = getelementptr inbounds float* %tmp22313, i64 1
-  %tmp22315 = getelementptr inbounds float* %tmp22314, i64 1
-  %tmp22316 = getelementptr inbounds float* %tmp22315, i64 1
-  %tmp22317 = getelementptr inbounds float* %tmp22316, i64 1
-  %tmp22318 = getelementptr inbounds float* %tmp22317, i64 1
-  %tmp22319 = getelementptr inbounds float* %tmp22318, i64 1
-  %tmp22320 = getelementptr inbounds float* %tmp22319, i64 1
-  %tmp22321 = getelementptr inbounds float* %tmp22320, i64 1
-  %tmp22322 = getelementptr inbounds float* %tmp22321, i64 1
-  %tmp22323 = getelementptr inbounds float* %tmp22322, i64 1
-  %tmp22324 = getelementptr inbounds float* %tmp22323, i64 1
-  %tmp22325 = getelementptr inbounds float* %tmp22324, i64 1
-  %tmp22326 = getelementptr inbounds float* %tmp22325, i64 1
-  %tmp22327 = getelementptr inbounds float* %tmp22326, i64 1
-  %tmp22328 = getelementptr inbounds float* %tmp22327, i64 1
-  %tmp22329 = getelementptr inbounds float* %tmp22328, i64 1
-  %tmp22330 = getelementptr inbounds float* %tmp22329, i64 1
-  %tmp22331 = getelementptr inbounds float* %tmp22330, i64 1
-  %tmp22332 = getelementptr inbounds float* %tmp22331, i64 1
-  %tmp22333 = getelementptr inbounds float* %tmp22332, i64 1
-  %tmp22334 = getelementptr inbounds float* %tmp22333, i64 1
-  %tmp22335 = getelementptr inbounds float* %tmp22334, i64 1
-  %tmp22336 = getelementptr inbounds float* %tmp22335, i64 1
-  %tmp22337 = getelementptr inbounds float* %tmp22336, i64 1
-  %tmp22338 = getelementptr inbounds float* %tmp22337, i64 1
-  %tmp22339 = getelementptr inbounds float* %tmp22338, i64 1
-  %tmp22340 = getelementptr inbounds float* %tmp22339, i64 1
-  %tmp22341 = getelementptr inbounds float* %tmp22340, i64 1
-  %tmp22342 = getelementptr inbounds float* %tmp22341, i64 1
-  %tmp22343 = getelementptr inbounds float* %tmp22342, i64 1
-  %tmp22344 = getelementptr inbounds float* %tmp22343, i64 1
-  %tmp22345 = getelementptr inbounds float* %tmp22344, i64 1
-  %tmp22346 = getelementptr inbounds float* %tmp22345, i64 1
-  %tmp22347 = getelementptr inbounds float* %tmp22346, i64 1
-  %tmp22348 = getelementptr inbounds float* %tmp22347, i64 1
-  %tmp22349 = getelementptr inbounds float* %tmp22348, i64 1
-  %tmp22350 = getelementptr inbounds float* %tmp22349, i64 1
-  %tmp22351 = getelementptr inbounds float* %tmp22350, i64 1
-  %tmp22352 = getelementptr inbounds float* %tmp22351, i64 1
-  %tmp22353 = getelementptr inbounds float* %tmp22352, i64 1
-  %tmp22354 = getelementptr inbounds float* %tmp22353, i64 1
-  %tmp22355 = getelementptr inbounds float* %tmp22354, i64 1
-  %tmp22356 = getelementptr inbounds float* %tmp22355, i64 1
-  %tmp22357 = getelementptr inbounds float* %tmp22356, i64 1
-  %tmp22358 = getelementptr inbounds float* %tmp22357, i64 1
-  %tmp22359 = getelementptr inbounds float* %tmp22358, i64 1
-  %tmp22360 = getelementptr inbounds float* %tmp22359, i64 1
-  %tmp22361 = getelementptr inbounds float* %tmp22360, i64 1
-  %tmp22362 = getelementptr inbounds float* %tmp22361, i64 1
-  %tmp22363 = getelementptr inbounds float* %tmp22362, i64 1
-  %tmp22364 = getelementptr inbounds float* %tmp22363, i64 1
-  %tmp22365 = getelementptr inbounds float* %tmp22364, i64 1
-  %tmp22366 = getelementptr inbounds float* %tmp22365, i64 1
-  %tmp22367 = getelementptr inbounds float* %tmp22366, i64 1
-  %tmp22368 = getelementptr inbounds float* %tmp22367, i64 1
-  %tmp22369 = getelementptr inbounds float* %tmp22368, i64 1
-  %tmp22370 = getelementptr inbounds float* %tmp22369, i64 1
-  %tmp22371 = getelementptr inbounds float* %tmp22370, i64 1
-  %tmp22372 = getelementptr inbounds float* %tmp22371, i64 1
-  %tmp22373 = getelementptr inbounds float* %tmp22372, i64 1
-  %tmp22374 = getelementptr inbounds float* %tmp22373, i64 1
-  %tmp22375 = getelementptr inbounds float* %tmp22374, i64 1
-  %tmp22376 = getelementptr inbounds float* %tmp22375, i64 1
-  %tmp22377 = getelementptr inbounds float* %tmp22376, i64 1
-  %tmp22378 = getelementptr inbounds float* %tmp22377, i64 1
-  %tmp22379 = getelementptr inbounds float* %tmp22378, i64 1
-  %tmp22380 = getelementptr inbounds float* %tmp22379, i64 1
-  %tmp22381 = getelementptr inbounds float* %tmp22380, i64 1
-  %tmp22382 = getelementptr inbounds float* %tmp22381, i64 1
-  %tmp22383 = getelementptr inbounds float* %tmp22382, i64 1
-  %tmp22384 = getelementptr inbounds float* %tmp22383, i64 1
-  %tmp22385 = getelementptr inbounds float* %tmp22384, i64 1
-  %tmp22386 = getelementptr inbounds float* %tmp22385, i64 1
-  %tmp22387 = getelementptr inbounds float* %tmp22386, i64 1
-  %tmp22388 = getelementptr inbounds float* %tmp22387, i64 1
-  %tmp22389 = getelementptr inbounds float* %tmp22388, i64 1
-  %tmp22390 = getelementptr inbounds float* %tmp22389, i64 1
-  %tmp22391 = getelementptr inbounds float* %tmp22390, i64 1
-  %tmp22392 = getelementptr inbounds float* %tmp22391, i64 1
-  %tmp22393 = getelementptr inbounds float* %tmp22392, i64 1
-  %tmp22394 = getelementptr inbounds float* %tmp22393, i64 1
-  %tmp22395 = getelementptr inbounds float* %tmp22394, i64 1
-  %tmp22396 = getelementptr inbounds float* %tmp22395, i64 1
-  %tmp22397 = getelementptr inbounds float* %tmp22396, i64 1
-  %tmp22398 = getelementptr inbounds float* %tmp22397, i64 1
-  %tmp22399 = getelementptr inbounds float* %tmp22398, i64 1
-  %tmp22400 = getelementptr inbounds float* %tmp22399, i64 1
-  %tmp22401 = getelementptr inbounds float* %tmp22400, i64 1
-  %tmp22402 = getelementptr inbounds float* %tmp22401, i64 1
-  %tmp22403 = getelementptr inbounds float* %tmp22402, i64 1
-  %tmp22404 = getelementptr inbounds float* %tmp22403, i64 1
-  %tmp22405 = getelementptr inbounds float* %tmp22404, i64 1
-  %tmp22406 = getelementptr inbounds float* %tmp22405, i64 1
-  %tmp22407 = getelementptr inbounds float* %tmp22406, i64 1
-  %tmp22408 = getelementptr inbounds float* %tmp22407, i64 1
-  %tmp22409 = getelementptr inbounds float* %tmp22408, i64 1
-  %tmp22410 = getelementptr inbounds float* %tmp22409, i64 1
-  %tmp22411 = getelementptr inbounds float* %tmp22410, i64 1
-  %tmp22412 = getelementptr inbounds float* %tmp22411, i64 1
-  %tmp22413 = getelementptr inbounds float* %tmp22412, i64 1
-  %tmp22414 = getelementptr inbounds float* %tmp22413, i64 1
-  %tmp22415 = getelementptr inbounds float* %tmp22414, i64 1
-  %tmp22416 = getelementptr inbounds float* %tmp22415, i64 1
-  %tmp22417 = getelementptr inbounds float* %tmp22416, i64 1
-  %tmp22418 = getelementptr inbounds float* %tmp22417, i64 1
-  %tmp22419 = getelementptr inbounds float* %tmp22418, i64 1
-  %tmp22420 = getelementptr inbounds float* %tmp22419, i64 1
-  %tmp22421 = getelementptr inbounds float* %tmp22420, i64 1
-  %tmp22422 = getelementptr inbounds float* %tmp22421, i64 1
-  %tmp22423 = getelementptr inbounds float* %tmp22422, i64 1
-  %tmp22424 = getelementptr inbounds float* %tmp22423, i64 1
-  %tmp22425 = getelementptr inbounds float* %tmp22424, i64 1
-  %tmp22426 = getelementptr inbounds float* %tmp22425, i64 1
-  %tmp22427 = getelementptr inbounds float* %tmp22426, i64 1
-  %tmp22428 = getelementptr inbounds float* %tmp22427, i64 1
-  %tmp22429 = getelementptr inbounds float* %tmp22428, i64 1
-  %tmp22430 = getelementptr inbounds float* %tmp22429, i64 1
-  %tmp22431 = getelementptr inbounds float* %tmp22430, i64 1
-  %tmp22432 = getelementptr inbounds float* %tmp22431, i64 1
-  %tmp22433 = getelementptr inbounds float* %tmp22432, i64 1
-  %tmp22434 = getelementptr inbounds float* %tmp22433, i64 1
-  %tmp22435 = getelementptr inbounds float* %tmp22434, i64 1
-  %tmp22436 = getelementptr inbounds float* %tmp22435, i64 1
-  %tmp22437 = getelementptr inbounds float* %tmp22436, i64 1
-  %tmp22438 = getelementptr inbounds float* %tmp22437, i64 1
-  %tmp22439 = getelementptr inbounds float* %tmp22438, i64 1
-  %tmp22440 = getelementptr inbounds float* %tmp22439, i64 1
-  %tmp22441 = getelementptr inbounds float* %tmp22440, i64 1
-  %tmp22442 = getelementptr inbounds float* %tmp22441, i64 1
-  %tmp22443 = getelementptr inbounds float* %tmp22442, i64 1
-  %tmp22444 = getelementptr inbounds float* %tmp22443, i64 1
-  %tmp22445 = getelementptr inbounds float* %tmp22444, i64 1
-  %tmp22446 = getelementptr inbounds float* %tmp22445, i64 1
-  %tmp22447 = getelementptr inbounds float* %tmp22446, i64 1
-  %tmp22448 = getelementptr inbounds float* %tmp22447, i64 1
-  %tmp22449 = getelementptr inbounds float* %tmp22448, i64 1
-  %tmp22450 = getelementptr inbounds float* %tmp22449, i64 1
-  %tmp22451 = getelementptr inbounds float* %tmp22450, i64 1
-  %tmp22452 = getelementptr inbounds float* %tmp22451, i64 1
-  %tmp22453 = getelementptr inbounds float* %tmp22452, i64 1
-  %tmp22454 = getelementptr inbounds float* %tmp22453, i64 1
-  %tmp22455 = getelementptr inbounds float* %tmp22454, i64 1
-  %tmp22456 = getelementptr inbounds float* %tmp22455, i64 1
-  %tmp22457 = getelementptr inbounds float* %tmp22456, i64 1
-  %tmp22458 = getelementptr inbounds float* %tmp22457, i64 1
-  %tmp22459 = getelementptr inbounds float* %tmp22458, i64 1
-  %tmp22460 = getelementptr inbounds float* %tmp22459, i64 1
-  %tmp22461 = getelementptr inbounds float* %tmp22460, i64 1
-  %tmp22462 = getelementptr inbounds float* %tmp22461, i64 1
-  %tmp22463 = getelementptr inbounds float* %tmp22462, i64 1
-  %tmp22464 = getelementptr inbounds float* %tmp22463, i64 1
-  %tmp22465 = getelementptr inbounds float* %tmp22464, i64 1
-  %tmp22466 = getelementptr inbounds float* %tmp22465, i64 1
-  %tmp22467 = getelementptr inbounds float* %tmp22466, i64 1
-  %tmp22468 = getelementptr inbounds float* %tmp22467, i64 1
-  %tmp22469 = getelementptr inbounds float* %tmp22468, i64 1
-  %tmp22470 = getelementptr inbounds float* %tmp22469, i64 1
-  %tmp22471 = getelementptr inbounds float* %tmp22470, i64 1
-  %tmp22472 = getelementptr inbounds float* %tmp22471, i64 1
-  %tmp22473 = getelementptr inbounds float* %tmp22472, i64 1
-  %tmp22474 = getelementptr inbounds float* %tmp22473, i64 1
-  %tmp22475 = getelementptr inbounds float* %tmp22474, i64 1
-  %tmp22476 = getelementptr inbounds float* %tmp22475, i64 1
-  %tmp22477 = getelementptr inbounds float* %tmp22476, i64 1
-  %tmp22478 = getelementptr inbounds float* %tmp22477, i64 1
-  %tmp22479 = getelementptr inbounds float* %tmp22478, i64 1
-  %tmp22480 = getelementptr inbounds float* %tmp22479, i64 1
-  %tmp22481 = getelementptr inbounds float* %tmp22480, i64 1
-  %tmp22482 = getelementptr inbounds float* %tmp22481, i64 1
-  %tmp22483 = getelementptr inbounds float* %tmp22482, i64 1
-  %tmp22484 = getelementptr inbounds float* %tmp22483, i64 1
-  %tmp22485 = getelementptr inbounds float* %tmp22484, i64 1
-  %tmp22486 = getelementptr inbounds float* %tmp22485, i64 1
-  %tmp22487 = getelementptr inbounds float* %tmp22486, i64 1
-  %tmp22488 = getelementptr inbounds float* %tmp22487, i64 1
-  %tmp22489 = getelementptr inbounds float* %tmp22488, i64 1
-  %tmp22490 = getelementptr inbounds float* %tmp22489, i64 1
-  %tmp22491 = getelementptr inbounds float* %tmp22490, i64 1
-  %tmp22492 = getelementptr inbounds float* %tmp22491, i64 1
-  %tmp22493 = getelementptr inbounds float* %tmp22492, i64 1
-  %tmp22494 = getelementptr inbounds float* %tmp22493, i64 1
-  %tmp22495 = getelementptr inbounds float* %tmp22494, i64 1
-  %tmp22496 = getelementptr inbounds float* %tmp22495, i64 1
-  %tmp22497 = getelementptr inbounds float* %tmp22496, i64 1
-  %tmp22498 = getelementptr inbounds float* %tmp22497, i64 1
-  %tmp22499 = getelementptr inbounds float* %tmp22498, i64 1
-  %tmp22500 = getelementptr inbounds float* %tmp22499, i64 1
-  %tmp22501 = getelementptr inbounds float* %tmp22500, i64 1
-  %tmp22502 = getelementptr inbounds float* %tmp22501, i64 1
-  %tmp22503 = getelementptr inbounds float* %tmp22502, i64 1
-  %tmp22504 = getelementptr inbounds float* %tmp22503, i64 1
-  %tmp22505 = getelementptr inbounds float* %tmp22504, i64 1
-  %tmp22506 = getelementptr inbounds float* %tmp22505, i64 1
-  %tmp22507 = getelementptr inbounds float* %tmp22506, i64 1
-  %tmp22508 = getelementptr inbounds float* %tmp22507, i64 1
-  %tmp22509 = getelementptr inbounds float* %tmp22508, i64 1
-  %tmp22510 = getelementptr inbounds float* %tmp22509, i64 1
-  %tmp22511 = getelementptr inbounds float* %tmp22510, i64 1
-  %tmp22512 = getelementptr inbounds float* %tmp22511, i64 1
-  %tmp22513 = getelementptr inbounds float* %tmp22512, i64 1
-  %tmp22514 = getelementptr inbounds float* %tmp22513, i64 1
-  %tmp22515 = getelementptr inbounds float* %tmp22514, i64 1
-  %tmp22516 = getelementptr inbounds float* %tmp22515, i64 1
-  %tmp22517 = getelementptr inbounds float* %tmp22516, i64 1
-  %tmp22518 = getelementptr inbounds float* %tmp22517, i64 1
-  %tmp22519 = getelementptr inbounds float* %tmp22518, i64 1
-  %tmp22520 = getelementptr inbounds float* %tmp22519, i64 1
-  %tmp22521 = getelementptr inbounds float* %tmp22520, i64 1
-  %tmp22522 = getelementptr inbounds float* %tmp22521, i64 1
-  %tmp22523 = getelementptr inbounds float* %tmp22522, i64 1
-  %tmp22524 = getelementptr inbounds float* %tmp22523, i64 1
-  %tmp22525 = getelementptr inbounds float* %tmp22524, i64 1
-  %tmp22526 = getelementptr inbounds float* %tmp22525, i64 1
-  %tmp22527 = getelementptr inbounds float* %tmp22526, i64 1
-  %tmp22528 = getelementptr inbounds float* %tmp22527, i64 1
-  %tmp22529 = getelementptr inbounds float* %tmp22528, i64 1
-  %tmp22530 = getelementptr inbounds float* %tmp22529, i64 1
-  %tmp22531 = getelementptr inbounds float* %tmp22530, i64 1
-  %tmp22532 = getelementptr inbounds float* %tmp22531, i64 1
-  %tmp22533 = getelementptr inbounds float* %tmp22532, i64 1
-  %tmp22534 = getelementptr inbounds float* %tmp22533, i64 1
-  %tmp22535 = getelementptr inbounds float* %tmp22534, i64 1
-  %tmp22536 = getelementptr inbounds float* %tmp22535, i64 1
-  %tmp22537 = getelementptr inbounds float* %tmp22536, i64 1
-  %tmp22538 = getelementptr inbounds float* %tmp22537, i64 1
-  %tmp22539 = getelementptr inbounds float* %tmp22538, i64 1
-  %tmp22540 = getelementptr inbounds float* %tmp22539, i64 1
-  %tmp22541 = getelementptr inbounds float* %tmp22540, i64 1
-  %tmp22542 = getelementptr inbounds float* %tmp22541, i64 1
-  %tmp22543 = getelementptr inbounds float* %tmp22542, i64 1
-  %tmp22544 = getelementptr inbounds float* %tmp22543, i64 1
-  %tmp22545 = getelementptr inbounds float* %tmp22544, i64 1
-  %tmp22546 = getelementptr inbounds float* %tmp22545, i64 1
-  %tmp22547 = getelementptr inbounds float* %tmp22546, i64 1
-  %tmp22548 = getelementptr inbounds float* %tmp22547, i64 1
-  %tmp22549 = getelementptr inbounds float* %tmp22548, i64 1
-  %tmp22550 = getelementptr inbounds float* %tmp22549, i64 1
-  %tmp22551 = getelementptr inbounds float* %tmp22550, i64 1
-  %tmp22552 = getelementptr inbounds float* %tmp22551, i64 1
-  %tmp22553 = getelementptr inbounds float* %tmp22552, i64 1
-  %tmp22554 = getelementptr inbounds float* %tmp22553, i64 1
-  %tmp22555 = getelementptr inbounds float* %tmp22554, i64 1
-  %tmp22556 = getelementptr inbounds float* %tmp22555, i64 1
-  %tmp22557 = getelementptr inbounds float* %tmp22556, i64 1
-  %tmp22558 = getelementptr inbounds float* %tmp22557, i64 1
-  %tmp22559 = getelementptr inbounds float* %tmp22558, i64 1
-  %tmp22560 = getelementptr inbounds float* %tmp22559, i64 1
-  %tmp22561 = getelementptr inbounds float* %tmp22560, i64 1
-  %tmp22562 = getelementptr inbounds float* %tmp22561, i64 1
-  %tmp22563 = getelementptr inbounds float* %tmp22562, i64 1
-  %tmp22564 = getelementptr inbounds float* %tmp22563, i64 1
-  %tmp22565 = getelementptr inbounds float* %tmp22564, i64 1
-  %tmp22566 = getelementptr inbounds float* %tmp22565, i64 1
-  %tmp22567 = getelementptr inbounds float* %tmp22566, i64 1
-  %tmp22568 = getelementptr inbounds float* %tmp22567, i64 1
-  %tmp22569 = getelementptr inbounds float* %tmp22568, i64 1
-  %tmp22570 = getelementptr inbounds float* %tmp22569, i64 1
-  %tmp22571 = getelementptr inbounds float* %tmp22570, i64 1
-  %tmp22572 = getelementptr inbounds float* %tmp22571, i64 1
-  %tmp22573 = getelementptr inbounds float* %tmp22572, i64 1
-  %tmp22574 = getelementptr inbounds float* %tmp22573, i64 1
-  %tmp22575 = getelementptr inbounds float* %tmp22574, i64 1
-  %tmp22576 = getelementptr inbounds float* %tmp22575, i64 1
-  %tmp22577 = getelementptr inbounds float* %tmp22576, i64 1
-  %tmp22578 = getelementptr inbounds float* %tmp22577, i64 1
-  %tmp22579 = getelementptr inbounds float* %tmp22578, i64 1
-  %tmp22580 = getelementptr inbounds float* %tmp22579, i64 1
-  %tmp22581 = getelementptr inbounds float* %tmp22580, i64 1
-  %tmp22582 = getelementptr inbounds float* %tmp22581, i64 1
-  %tmp22583 = getelementptr inbounds float* %tmp22582, i64 1
-  %tmp22584 = getelementptr inbounds float* %tmp22583, i64 1
-  %tmp22585 = getelementptr inbounds float* %tmp22584, i64 1
-  %tmp22586 = getelementptr inbounds float* %tmp22585, i64 1
-  %tmp22587 = getelementptr inbounds float* %tmp22586, i64 1
-  %tmp22588 = getelementptr inbounds float* %tmp22587, i64 1
-  %tmp22589 = getelementptr inbounds float* %tmp22588, i64 1
-  %tmp22590 = getelementptr inbounds float* %tmp22589, i64 1
-  %tmp22591 = getelementptr inbounds float* %tmp22590, i64 1
-  %tmp22592 = getelementptr inbounds float* %tmp22591, i64 1
-  %tmp22593 = getelementptr inbounds float* %tmp22592, i64 1
-  %tmp22594 = getelementptr inbounds float* %tmp22593, i64 1
-  %tmp22595 = getelementptr inbounds float* %tmp22594, i64 1
-  %tmp22596 = getelementptr inbounds float* %tmp22595, i64 1
-  %tmp22597 = getelementptr inbounds float* %tmp22596, i64 1
-  %tmp22598 = getelementptr inbounds float* %tmp22597, i64 1
-  %tmp22599 = getelementptr inbounds float* %tmp22598, i64 1
-  %tmp22600 = getelementptr inbounds float* %tmp22599, i64 1
-  %tmp22601 = getelementptr inbounds float* %tmp22600, i64 1
-  %tmp22602 = getelementptr inbounds float* %tmp22601, i64 1
-  %tmp22603 = getelementptr inbounds float* %tmp22602, i64 1
-  %tmp22604 = getelementptr inbounds float* %tmp22603, i64 1
-  %tmp22605 = getelementptr inbounds float* %tmp22604, i64 1
-  %tmp22606 = getelementptr inbounds float* %tmp22605, i64 1
-  %tmp22607 = getelementptr inbounds float* %tmp22606, i64 1
-  %tmp22608 = getelementptr inbounds float* %tmp22607, i64 1
-  %tmp22609 = getelementptr inbounds float* %tmp22608, i64 1
-  %tmp22610 = getelementptr inbounds float* %tmp22609, i64 1
-  %tmp22611 = getelementptr inbounds float* %tmp22610, i64 1
-  %tmp22612 = getelementptr inbounds float* %tmp22611, i64 1
-  %tmp22613 = getelementptr inbounds float* %tmp22612, i64 1
-  %tmp22614 = getelementptr inbounds float* %tmp22613, i64 1
-  %tmp22615 = getelementptr inbounds float* %tmp22614, i64 1
-  %tmp22616 = getelementptr inbounds float* %tmp22615, i64 1
-  %tmp22617 = getelementptr inbounds float* %tmp22616, i64 1
-  %tmp22618 = getelementptr inbounds float* %tmp22617, i64 1
-  %tmp22619 = getelementptr inbounds float* %tmp22618, i64 1
-  %tmp22620 = getelementptr inbounds float* %tmp22619, i64 1
-  %tmp22621 = getelementptr inbounds float* %tmp22620, i64 1
-  %tmp22622 = getelementptr inbounds float* %tmp22621, i64 1
-  %tmp22623 = getelementptr inbounds float* %tmp22622, i64 1
-  %tmp22624 = getelementptr inbounds float* %tmp22623, i64 1
-  %tmp22625 = getelementptr inbounds float* %tmp22624, i64 1
-  %tmp22626 = getelementptr inbounds float* %tmp22625, i64 1
-  %tmp22627 = getelementptr inbounds float* %tmp22626, i64 1
-  %tmp22628 = getelementptr inbounds float* %tmp22627, i64 1
-  %tmp22629 = getelementptr inbounds float* %tmp22628, i64 1
-  %tmp22630 = getelementptr inbounds float* %tmp22629, i64 1
-  %tmp22631 = getelementptr inbounds float* %tmp22630, i64 1
-  %tmp22632 = getelementptr inbounds float* %tmp22631, i64 1
-  %tmp22633 = getelementptr inbounds float* %tmp22632, i64 1
-  %tmp22634 = getelementptr inbounds float* %tmp22633, i64 1
-  %tmp22635 = getelementptr inbounds float* %tmp22634, i64 1
-  %tmp22636 = getelementptr inbounds float* %tmp22635, i64 1
-  %tmp22637 = getelementptr inbounds float* %tmp22636, i64 1
-  %tmp22638 = getelementptr inbounds float* %tmp22637, i64 1
-  %tmp22639 = getelementptr inbounds float* %tmp22638, i64 1
-  %tmp22640 = getelementptr inbounds float* %tmp22639, i64 1
-  %tmp22641 = getelementptr inbounds float* %tmp22640, i64 1
-  %tmp22642 = getelementptr inbounds float* %tmp22641, i64 1
-  %tmp22643 = getelementptr inbounds float* %tmp22642, i64 1
-  %tmp22644 = getelementptr inbounds float* %tmp22643, i64 1
-  %tmp22645 = getelementptr inbounds float* %tmp22644, i64 1
-  %tmp22646 = getelementptr inbounds float* %tmp22645, i64 1
-  %tmp22647 = getelementptr inbounds float* %tmp22646, i64 1
-  %tmp22648 = getelementptr inbounds float* %tmp22647, i64 1
-  %tmp22649 = getelementptr inbounds float* %tmp22648, i64 1
-  %tmp22650 = getelementptr inbounds float* %tmp22649, i64 1
-  %tmp22651 = getelementptr inbounds float* %tmp22650, i64 1
-  %tmp22652 = getelementptr inbounds float* %tmp22651, i64 1
-  %tmp22653 = getelementptr inbounds float* %tmp22652, i64 1
-  %tmp22654 = getelementptr inbounds float* %tmp22653, i64 1
-  %tmp22655 = getelementptr inbounds float* %tmp22654, i64 1
-  %tmp22656 = getelementptr inbounds float* %tmp22655, i64 1
-  %tmp22657 = getelementptr inbounds float* %tmp22656, i64 1
-  %tmp22658 = getelementptr inbounds float* %tmp22657, i64 1
-  %tmp22659 = getelementptr inbounds float* %tmp22658, i64 1
-  %tmp22660 = getelementptr inbounds float* %tmp22659, i64 1
-  %tmp22661 = getelementptr inbounds float* %tmp22660, i64 1
-  %tmp22662 = getelementptr inbounds float* %tmp22661, i64 1
-  %tmp22663 = getelementptr inbounds float* %tmp22662, i64 1
-  %tmp22664 = getelementptr inbounds float* %tmp22663, i64 1
-  %tmp22665 = getelementptr inbounds float* %tmp22664, i64 1
-  %tmp22666 = getelementptr inbounds float* %tmp22665, i64 1
-  %tmp22667 = getelementptr inbounds float* %tmp22666, i64 1
-  %tmp22668 = getelementptr inbounds float* %tmp22667, i64 1
-  %tmp22669 = getelementptr inbounds float* %tmp22668, i64 1
-  %tmp22670 = getelementptr inbounds float* %tmp22669, i64 1
-  %tmp22671 = getelementptr inbounds float* %tmp22670, i64 1
-  %tmp22672 = getelementptr inbounds float* %tmp22671, i64 1
-  %tmp22673 = getelementptr inbounds float* %tmp22672, i64 1
-  %tmp22674 = getelementptr inbounds float* %tmp22673, i64 1
-  %tmp22675 = getelementptr inbounds float* %tmp22674, i64 1
-  %tmp22676 = getelementptr inbounds float* %tmp22675, i64 1
-  %tmp22677 = getelementptr inbounds float* %tmp22676, i64 1
-  %tmp22678 = getelementptr inbounds float* %tmp22677, i64 1
-  %tmp22679 = getelementptr inbounds float* %tmp22678, i64 1
-  %tmp22680 = getelementptr inbounds float* %tmp22679, i64 1
-  %tmp22681 = getelementptr inbounds float* %tmp22680, i64 1
-  %tmp22682 = getelementptr inbounds float* %tmp22681, i64 1
-  %tmp22683 = getelementptr inbounds float* %tmp22682, i64 1
-  %tmp22684 = getelementptr inbounds float* %tmp22683, i64 1
-  %tmp22685 = getelementptr inbounds float* %tmp22684, i64 1
-  %tmp22686 = getelementptr inbounds float* %tmp22685, i64 1
-  %tmp22687 = getelementptr inbounds float* %tmp22686, i64 1
-  %tmp22688 = getelementptr inbounds float* %tmp22687, i64 1
-  %tmp22689 = getelementptr inbounds float* %tmp22688, i64 1
-  %tmp22690 = getelementptr inbounds float* %tmp22689, i64 1
-  %tmp22691 = getelementptr inbounds float* %tmp22690, i64 1
-  %tmp22692 = getelementptr inbounds float* %tmp22691, i64 1
-  %tmp22693 = getelementptr inbounds float* %tmp22692, i64 1
-  %tmp22694 = getelementptr inbounds float* %tmp22693, i64 1
-  %tmp22695 = getelementptr inbounds float* %tmp22694, i64 1
-  %tmp22696 = getelementptr inbounds float* %tmp22695, i64 1
-  %tmp22697 = getelementptr inbounds float* %tmp22696, i64 1
-  %tmp22698 = getelementptr inbounds float* %tmp22697, i64 1
-  %tmp22699 = getelementptr inbounds float* %tmp22698, i64 1
-  %tmp22700 = getelementptr inbounds float* %tmp22699, i64 1
-  %tmp22701 = getelementptr inbounds float* %tmp22700, i64 1
-  %tmp22702 = getelementptr inbounds float* %tmp22701, i64 1
-  %tmp22703 = getelementptr inbounds float* %tmp22702, i64 1
-  %tmp22704 = getelementptr inbounds float* %tmp22703, i64 1
-  %tmp22705 = getelementptr inbounds float* %tmp22704, i64 1
-  %tmp22706 = getelementptr inbounds float* %tmp22705, i64 1
-  %tmp22707 = getelementptr inbounds float* %tmp22706, i64 1
-  %tmp22708 = getelementptr inbounds float* %tmp22707, i64 1
-  %tmp22709 = getelementptr inbounds float* %tmp22708, i64 1
-  %tmp22710 = getelementptr inbounds float* %tmp22709, i64 1
-  %tmp22711 = getelementptr inbounds float* %tmp22710, i64 1
-  %tmp22712 = getelementptr inbounds float* %tmp22711, i64 1
-  %tmp22713 = getelementptr inbounds float* %tmp22712, i64 1
-  %tmp22714 = getelementptr inbounds float* %tmp22713, i64 1
-  %tmp22715 = getelementptr inbounds float* %tmp22714, i64 1
-  %tmp22716 = getelementptr inbounds float* %tmp22715, i64 1
-  %tmp22717 = getelementptr inbounds float* %tmp22716, i64 1
-  %tmp22718 = getelementptr inbounds float* %tmp22717, i64 1
-  %tmp22719 = getelementptr inbounds float* %tmp22718, i64 1
-  %tmp22720 = getelementptr inbounds float* %tmp22719, i64 1
-  %tmp22721 = getelementptr inbounds float* %tmp22720, i64 1
-  %tmp22722 = getelementptr inbounds float* %tmp22721, i64 1
-  %tmp22723 = getelementptr inbounds float* %tmp22722, i64 1
-  %tmp22724 = getelementptr inbounds float* %tmp22723, i64 1
-  %tmp22725 = getelementptr inbounds float* %tmp22724, i64 1
-  %tmp22726 = getelementptr inbounds float* %tmp22725, i64 1
-  %tmp22727 = getelementptr inbounds float* %tmp22726, i64 1
-  %tmp22728 = getelementptr inbounds float* %tmp22727, i64 1
-  %tmp22729 = getelementptr inbounds float* %tmp22728, i64 1
-  %tmp22730 = getelementptr inbounds float* %tmp22729, i64 1
-  %tmp22731 = getelementptr inbounds float* %tmp22730, i64 1
-  %tmp22732 = getelementptr inbounds float* %tmp22731, i64 1
-  %tmp22733 = getelementptr inbounds float* %tmp22732, i64 1
-  %tmp22734 = getelementptr inbounds float* %tmp22733, i64 1
-  %tmp22735 = getelementptr inbounds float* %tmp22734, i64 1
-  %tmp22736 = getelementptr inbounds float* %tmp22735, i64 1
-  %tmp22737 = getelementptr inbounds float* %tmp22736, i64 1
-  %tmp22738 = getelementptr inbounds float* %tmp22737, i64 1
-  %tmp22739 = getelementptr inbounds float* %tmp22738, i64 1
-  %tmp22740 = getelementptr inbounds float* %tmp22739, i64 1
-  %tmp22741 = getelementptr inbounds float* %tmp22740, i64 1
-  %tmp22742 = getelementptr inbounds float* %tmp22741, i64 1
-  %tmp22743 = getelementptr inbounds float* %tmp22742, i64 1
-  %tmp22744 = getelementptr inbounds float* %tmp22743, i64 1
-  %tmp22745 = getelementptr inbounds float* %tmp22744, i64 1
-  %tmp22746 = getelementptr inbounds float* %tmp22745, i64 1
-  %tmp22747 = getelementptr inbounds float* %tmp22746, i64 1
-  %tmp22748 = getelementptr inbounds float* %tmp22747, i64 1
-  %tmp22749 = getelementptr inbounds float* %tmp22748, i64 1
-  %tmp22750 = getelementptr inbounds float* %tmp22749, i64 1
-  %tmp22751 = getelementptr inbounds float* %tmp22750, i64 1
-  %tmp22752 = getelementptr inbounds float* %tmp22751, i64 1
-  %tmp22753 = getelementptr inbounds float* %tmp22752, i64 1
-  %tmp22754 = getelementptr inbounds float* %tmp22753, i64 1
-  %tmp22755 = getelementptr inbounds float* %tmp22754, i64 1
-  %tmp22756 = getelementptr inbounds float* %tmp22755, i64 1
-  %tmp22757 = getelementptr inbounds float* %tmp22756, i64 1
-  %tmp22758 = getelementptr inbounds float* %tmp22757, i64 1
-  %tmp22759 = getelementptr inbounds float* %tmp22758, i64 1
-  %tmp22760 = getelementptr inbounds float* %tmp22759, i64 1
-  %tmp22761 = getelementptr inbounds float* %tmp22760, i64 1
-  %tmp22762 = getelementptr inbounds float* %tmp22761, i64 1
-  %tmp22763 = getelementptr inbounds float* %tmp22762, i64 1
-  %tmp22764 = getelementptr inbounds float* %tmp22763, i64 1
-  %tmp22765 = getelementptr inbounds float* %tmp22764, i64 1
-  %tmp22766 = getelementptr inbounds float* %tmp22765, i64 1
-  %tmp22767 = getelementptr inbounds float* %tmp22766, i64 1
-  %tmp22768 = getelementptr inbounds float* %tmp22767, i64 1
-  %tmp22769 = getelementptr inbounds float* %tmp22768, i64 1
-  %tmp22770 = getelementptr inbounds float* %tmp22769, i64 1
-  %tmp22771 = getelementptr inbounds float* %tmp22770, i64 1
-  %tmp22772 = getelementptr inbounds float* %tmp22771, i64 1
-  %tmp22773 = getelementptr inbounds float* %tmp22772, i64 1
-  %tmp22774 = getelementptr inbounds float* %tmp22773, i64 1
-  %tmp22775 = getelementptr inbounds float* %tmp22774, i64 1
-  %tmp22776 = getelementptr inbounds float* %tmp22775, i64 1
-  %tmp22777 = getelementptr inbounds float* %tmp22776, i64 1
-  %tmp22778 = getelementptr inbounds float* %tmp22777, i64 1
-  %tmp22779 = getelementptr inbounds float* %tmp22778, i64 1
-  %tmp22780 = getelementptr inbounds float* %tmp22779, i64 1
-  %tmp22781 = getelementptr inbounds float* %tmp22780, i64 1
-  %tmp22782 = getelementptr inbounds float* %tmp22781, i64 1
-  %tmp22783 = getelementptr inbounds float* %tmp22782, i64 1
-  %tmp22784 = getelementptr inbounds float* %tmp22783, i64 1
-  %tmp22785 = getelementptr inbounds float* %tmp22784, i64 1
-  %tmp22786 = getelementptr inbounds float* %tmp22785, i64 1
-  %tmp22787 = getelementptr inbounds float* %tmp22786, i64 1
-  %tmp22788 = getelementptr inbounds float* %tmp22787, i64 1
-  %tmp22789 = getelementptr inbounds float* %tmp22788, i64 1
-  %tmp22790 = getelementptr inbounds float* %tmp22789, i64 1
-  %tmp22791 = getelementptr inbounds float* %tmp22790, i64 1
-  %tmp22792 = getelementptr inbounds float* %tmp22791, i64 1
-  %tmp22793 = getelementptr inbounds float* %tmp22792, i64 1
-  %tmp22794 = getelementptr inbounds float* %tmp22793, i64 1
-  %tmp22795 = getelementptr inbounds float* %tmp22794, i64 1
-  %tmp22796 = getelementptr inbounds float* %tmp22795, i64 1
-  %tmp22797 = getelementptr inbounds float* %tmp22796, i64 1
-  %tmp22798 = getelementptr inbounds float* %tmp22797, i64 1
-  %tmp22799 = getelementptr inbounds float* %tmp22798, i64 1
-  %tmp22800 = getelementptr inbounds float* %tmp22799, i64 1
-  %tmp22801 = getelementptr inbounds float* %tmp22800, i64 1
-  %tmp22802 = getelementptr inbounds float* %tmp22801, i64 1
-  %tmp22803 = getelementptr inbounds float* %tmp22802, i64 1
-  %tmp22804 = getelementptr inbounds float* %tmp22803, i64 1
-  %tmp22805 = getelementptr inbounds float* %tmp22804, i64 1
-  %tmp22806 = getelementptr inbounds float* %tmp22805, i64 1
-  %tmp22807 = getelementptr inbounds float* %tmp22806, i64 1
-  %tmp22808 = getelementptr inbounds float* %tmp22807, i64 1
-  %tmp22809 = getelementptr inbounds float* %tmp22808, i64 1
-  %tmp22810 = getelementptr inbounds float* %tmp22809, i64 1
-  %tmp22811 = getelementptr inbounds float* %tmp22810, i64 1
-  %tmp22812 = getelementptr inbounds float* %tmp22811, i64 1
-  %tmp22813 = getelementptr inbounds float* %tmp22812, i64 1
-  %tmp22814 = getelementptr inbounds float* %tmp22813, i64 1
-  %tmp22815 = getelementptr inbounds float* %tmp22814, i64 1
-  %tmp22816 = getelementptr inbounds float* %tmp22815, i64 1
-  %tmp22817 = getelementptr inbounds float* %tmp22816, i64 1
-  %tmp22818 = getelementptr inbounds float* %tmp22817, i64 1
-  %tmp22819 = getelementptr inbounds float* %tmp22818, i64 1
-  %tmp22820 = getelementptr inbounds float* %tmp22819, i64 1
-  %tmp22821 = getelementptr inbounds float* %tmp22820, i64 1
-  %tmp22822 = getelementptr inbounds float* %tmp22821, i64 1
-  %tmp22823 = getelementptr inbounds float* %tmp22822, i64 1
-  %tmp22824 = getelementptr inbounds float* %tmp22823, i64 1
-  %tmp22825 = getelementptr inbounds float* %tmp22824, i64 1
-  %tmp22826 = getelementptr inbounds float* %tmp22825, i64 1
-  %tmp22827 = getelementptr inbounds float* %tmp22826, i64 1
-  %tmp22828 = getelementptr inbounds float* %tmp22827, i64 1
-  %tmp22829 = getelementptr inbounds float* %tmp22828, i64 1
-  %tmp22830 = getelementptr inbounds float* %tmp22829, i64 1
-  %tmp22831 = getelementptr inbounds float* %tmp22830, i64 1
-  %tmp22832 = getelementptr inbounds float* %tmp22831, i64 1
-  %tmp22833 = getelementptr inbounds float* %tmp22832, i64 1
-  %tmp22834 = getelementptr inbounds float* %tmp22833, i64 1
-  %tmp22835 = getelementptr inbounds float* %tmp22834, i64 1
-  %tmp22836 = getelementptr inbounds float* %tmp22835, i64 1
-  %tmp22837 = getelementptr inbounds float* %tmp22836, i64 1
-  %tmp22838 = getelementptr inbounds float* %tmp22837, i64 1
-  %tmp22839 = getelementptr inbounds float* %tmp22838, i64 1
-  %tmp22840 = getelementptr inbounds float* %tmp22839, i64 1
-  %tmp22841 = getelementptr inbounds float* %tmp22840, i64 1
-  %tmp22842 = getelementptr inbounds float* %tmp22841, i64 1
-  %tmp22843 = getelementptr inbounds float* %tmp22842, i64 1
-  %tmp22844 = getelementptr inbounds float* %tmp22843, i64 1
-  %tmp22845 = getelementptr inbounds float* %tmp22844, i64 1
-  %tmp22846 = getelementptr inbounds float* %tmp22845, i64 1
-  %tmp22847 = getelementptr inbounds float* %tmp22846, i64 1
-  %tmp22848 = getelementptr inbounds float* %tmp22847, i64 1
-  %tmp22849 = getelementptr inbounds float* %tmp22848, i64 1
-  %tmp22850 = getelementptr inbounds float* %tmp22849, i64 1
-  %tmp22851 = getelementptr inbounds float* %tmp22850, i64 1
-  %tmp22852 = getelementptr inbounds float* %tmp22851, i64 1
-  %tmp22853 = getelementptr inbounds float* %tmp22852, i64 1
-  %tmp22854 = getelementptr inbounds float* %tmp22853, i64 1
-  %tmp22855 = getelementptr inbounds float* %tmp22854, i64 1
-  %tmp22856 = getelementptr inbounds float* %tmp22855, i64 1
-  %tmp22857 = getelementptr inbounds float* %tmp22856, i64 1
-  %tmp22858 = getelementptr inbounds float* %tmp22857, i64 1
-  %tmp22859 = getelementptr inbounds float* %tmp22858, i64 1
-  %tmp22860 = getelementptr inbounds float* %tmp22859, i64 1
-  %tmp22861 = getelementptr inbounds float* %tmp22860, i64 1
-  %tmp22862 = getelementptr inbounds float* %tmp22861, i64 1
-  %tmp22863 = getelementptr inbounds float* %tmp22862, i64 1
-  %tmp22864 = getelementptr inbounds float* %tmp22863, i64 1
-  %tmp22865 = getelementptr inbounds float* %tmp22864, i64 1
-  %tmp22866 = getelementptr inbounds float* %tmp22865, i64 1
-  %tmp22867 = getelementptr inbounds float* %tmp22866, i64 1
-  %tmp22868 = getelementptr inbounds float* %tmp22867, i64 1
-  %tmp22869 = getelementptr inbounds float* %tmp22868, i64 1
-  %tmp22870 = getelementptr inbounds float* %tmp22869, i64 1
-  %tmp22871 = getelementptr inbounds float* %tmp22870, i64 1
-  %tmp22872 = getelementptr inbounds float* %tmp22871, i64 1
-  %tmp22873 = getelementptr inbounds float* %tmp22872, i64 1
-  %tmp22874 = getelementptr inbounds float* %tmp22873, i64 1
-  %tmp22875 = getelementptr inbounds float* %tmp22874, i64 1
-  %tmp22876 = getelementptr inbounds float* %tmp22875, i64 1
-  %tmp22877 = getelementptr inbounds float* %tmp22876, i64 1
-  %tmp22878 = getelementptr inbounds float* %tmp22877, i64 1
-  %tmp22879 = getelementptr inbounds float* %tmp22878, i64 1
-  %tmp22880 = getelementptr inbounds float* %tmp22879, i64 1
-  %tmp22881 = getelementptr inbounds float* %tmp22880, i64 1
-  %tmp22882 = getelementptr inbounds float* %tmp22881, i64 1
-  %tmp22883 = getelementptr inbounds float* %tmp22882, i64 1
-  %tmp22884 = getelementptr inbounds float* %tmp22883, i64 1
-  %tmp22885 = getelementptr inbounds float* %tmp22884, i64 1
-  %tmp22886 = getelementptr inbounds float* %tmp22885, i64 1
-  %tmp22887 = getelementptr inbounds float* %tmp22886, i64 1
-  %tmp22888 = getelementptr inbounds float* %tmp22887, i64 1
-  %tmp22889 = getelementptr inbounds float* %tmp22888, i64 1
-  %tmp22890 = getelementptr inbounds float* %tmp22889, i64 1
-  %tmp22891 = getelementptr inbounds float* %tmp22890, i64 1
-  %tmp22892 = getelementptr inbounds float* %tmp22891, i64 1
-  %tmp22893 = getelementptr inbounds float* %tmp22892, i64 1
-  %tmp22894 = getelementptr inbounds float* %tmp22893, i64 1
-  %tmp22895 = getelementptr inbounds float* %tmp22894, i64 1
-  %tmp22896 = getelementptr inbounds float* %tmp22895, i64 1
-  %tmp22897 = getelementptr inbounds float* %tmp22896, i64 1
-  %tmp22898 = getelementptr inbounds float* %tmp22897, i64 1
-  %tmp22899 = getelementptr inbounds float* %tmp22898, i64 1
-  %tmp22900 = getelementptr inbounds float* %tmp22899, i64 1
-  %tmp22901 = getelementptr inbounds float* %tmp22900, i64 1
-  %tmp22902 = getelementptr inbounds float* %tmp22901, i64 1
-  %tmp22903 = getelementptr inbounds float* %tmp22902, i64 1
-  %tmp22904 = getelementptr inbounds float* %tmp22903, i64 1
-  %tmp22905 = getelementptr inbounds float* %tmp22904, i64 1
-  %tmp22906 = getelementptr inbounds float* %tmp22905, i64 1
-  %tmp22907 = getelementptr inbounds float* %tmp22906, i64 1
-  %tmp22908 = getelementptr inbounds float* %tmp22907, i64 1
-  %tmp22909 = getelementptr inbounds float* %tmp22908, i64 1
-  %tmp22910 = getelementptr inbounds float* %tmp22909, i64 1
-  %tmp22911 = getelementptr inbounds float* %tmp22910, i64 1
-  %tmp22912 = getelementptr inbounds float* %tmp22911, i64 1
-  %tmp22913 = getelementptr inbounds float* %tmp22912, i64 1
-  %tmp22914 = getelementptr inbounds float* %tmp22913, i64 1
-  %tmp22915 = getelementptr inbounds float* %tmp22914, i64 1
-  %tmp22916 = getelementptr inbounds float* %tmp22915, i64 1
-  %tmp22917 = getelementptr inbounds float* %tmp22916, i64 1
-  %tmp22918 = getelementptr inbounds float* %tmp22917, i64 1
-  %tmp22919 = getelementptr inbounds float* %tmp22918, i64 1
-  %tmp22920 = getelementptr inbounds float* %tmp22919, i64 1
-  %tmp22921 = getelementptr inbounds float* %tmp22920, i64 1
-  %tmp22922 = getelementptr inbounds float* %tmp22921, i64 1
-  %tmp22923 = getelementptr inbounds float* %tmp22922, i64 1
-  %tmp22924 = getelementptr inbounds float* %tmp22923, i64 1
-  %tmp22925 = getelementptr inbounds float* %tmp22924, i64 1
-  %tmp22926 = getelementptr inbounds float* %tmp22925, i64 1
-  %tmp22927 = getelementptr inbounds float* %tmp22926, i64 1
-  %tmp22928 = getelementptr inbounds float* %tmp22927, i64 1
-  %tmp22929 = getelementptr inbounds float* %tmp22928, i64 1
-  %tmp22930 = getelementptr inbounds float* %tmp22929, i64 1
-  %tmp22931 = getelementptr inbounds float* %tmp22930, i64 1
-  %tmp22932 = getelementptr inbounds float* %tmp22931, i64 1
-  %tmp22933 = getelementptr inbounds float* %tmp22932, i64 1
-  %tmp22934 = getelementptr inbounds float* %tmp22933, i64 1
-  %tmp22935 = getelementptr inbounds float* %tmp22934, i64 1
-  %tmp22936 = getelementptr inbounds float* %tmp22935, i64 1
-  %tmp22937 = getelementptr inbounds float* %tmp22936, i64 1
-  %tmp22938 = getelementptr inbounds float* %tmp22937, i64 1
-  %tmp22939 = getelementptr inbounds float* %tmp22938, i64 1
-  %tmp22940 = getelementptr inbounds float* %tmp22939, i64 1
-  %tmp22941 = getelementptr inbounds float* %tmp22940, i64 1
-  %tmp22942 = getelementptr inbounds float* %tmp22941, i64 1
-  %tmp22943 = getelementptr inbounds float* %tmp22942, i64 1
-  %tmp22944 = getelementptr inbounds float* %tmp22943, i64 1
-  %tmp22945 = getelementptr inbounds float* %tmp22944, i64 1
-  %tmp22946 = getelementptr inbounds float* %tmp22945, i64 1
-  %tmp22947 = getelementptr inbounds float* %tmp22946, i64 1
-  %tmp22948 = getelementptr inbounds float* %tmp22947, i64 1
-  %tmp22949 = getelementptr inbounds float* %tmp22948, i64 1
-  %tmp22950 = getelementptr inbounds float* %tmp22949, i64 1
-  %tmp22951 = getelementptr inbounds float* %tmp22950, i64 1
-  %tmp22952 = getelementptr inbounds float* %tmp22951, i64 1
-  %tmp22953 = getelementptr inbounds float* %tmp22952, i64 1
-  %tmp22954 = getelementptr inbounds float* %tmp22953, i64 1
-  %tmp22955 = getelementptr inbounds float* %tmp22954, i64 1
-  %tmp22956 = getelementptr inbounds float* %tmp22955, i64 1
-  %tmp22957 = getelementptr inbounds float* %tmp22956, i64 1
-  %tmp22958 = getelementptr inbounds float* %tmp22957, i64 1
-  %tmp22959 = getelementptr inbounds float* %tmp22958, i64 1
-  %tmp22960 = getelementptr inbounds float* %tmp22959, i64 1
-  %tmp22961 = getelementptr inbounds float* %tmp22960, i64 1
-  %tmp22962 = getelementptr inbounds float* %tmp22961, i64 1
-  %tmp22963 = getelementptr inbounds float* %tmp22962, i64 1
-  %tmp22964 = getelementptr inbounds float* %tmp22963, i64 1
-  %tmp22965 = getelementptr inbounds float* %tmp22964, i64 1
-  %tmp22966 = getelementptr inbounds float* %tmp22965, i64 1
-  %tmp22967 = getelementptr inbounds float* %tmp22966, i64 1
-  %tmp22968 = getelementptr inbounds float* %tmp22967, i64 1
-  %tmp22969 = getelementptr inbounds float* %tmp22968, i64 1
-  %tmp22970 = getelementptr inbounds float* %tmp22969, i64 1
-  %tmp22971 = getelementptr inbounds float* %tmp22970, i64 1
-  %tmp22972 = getelementptr inbounds float* %tmp22971, i64 1
-  %tmp22973 = getelementptr inbounds float* %tmp22972, i64 1
-  %tmp22974 = getelementptr inbounds float* %tmp22973, i64 1
-  %tmp22975 = getelementptr inbounds float* %tmp22974, i64 1
-  %tmp22976 = getelementptr inbounds float* %tmp22975, i64 1
-  %tmp22977 = getelementptr inbounds float* %tmp22976, i64 1
-  %tmp22978 = getelementptr inbounds float* %tmp22977, i64 1
-  %tmp22979 = getelementptr inbounds float* %tmp22978, i64 1
-  %tmp22980 = getelementptr inbounds float* %tmp22979, i64 1
-  %tmp22981 = getelementptr inbounds float* %tmp22980, i64 1
-  %tmp22982 = getelementptr inbounds float* %tmp22981, i64 1
-  %tmp22983 = getelementptr inbounds float* %tmp22982, i64 1
-  %tmp22984 = getelementptr inbounds float* %tmp22983, i64 1
-  %tmp22985 = getelementptr inbounds float* %tmp22984, i64 1
-  %tmp22986 = getelementptr inbounds float* %tmp22985, i64 1
-  %tmp22987 = getelementptr inbounds float* %tmp22986, i64 1
-  %tmp22988 = getelementptr inbounds float* %tmp22987, i64 1
-  %tmp22989 = getelementptr inbounds float* %tmp22988, i64 1
-  %tmp22990 = getelementptr inbounds float* %tmp22989, i64 1
-  %tmp22991 = getelementptr inbounds float* %tmp22990, i64 1
-  %tmp22992 = getelementptr inbounds float* %tmp22991, i64 1
-  %tmp22993 = getelementptr inbounds float* %tmp22992, i64 1
-  %tmp22994 = getelementptr inbounds float* %tmp22993, i64 1
-  %tmp22995 = getelementptr inbounds float* %tmp22994, i64 1
-  %tmp22996 = getelementptr inbounds float* %tmp22995, i64 1
-  %tmp22997 = getelementptr inbounds float* %tmp22996, i64 1
-  %tmp22998 = getelementptr inbounds float* %tmp22997, i64 1
-  %tmp22999 = getelementptr inbounds float* %tmp22998, i64 1
-  %tmp23000 = getelementptr inbounds float* %tmp22999, i64 1
-  %tmp23001 = getelementptr inbounds float* %tmp23000, i64 1
-  %tmp23002 = getelementptr inbounds float* %tmp23001, i64 1
-  %tmp23003 = getelementptr inbounds float* %tmp23002, i64 1
-  %tmp23004 = getelementptr inbounds float* %tmp23003, i64 1
-  %tmp23005 = getelementptr inbounds float* %tmp23004, i64 1
-  %tmp23006 = getelementptr inbounds float* %tmp23005, i64 1
-  %tmp23007 = getelementptr inbounds float* %tmp23006, i64 1
-  %tmp23008 = getelementptr inbounds float* %tmp23007, i64 1
-  %tmp23009 = getelementptr inbounds float* %tmp23008, i64 1
-  %tmp23010 = getelementptr inbounds float* %tmp23009, i64 1
-  %tmp23011 = getelementptr inbounds float* %tmp23010, i64 1
-  %tmp23012 = getelementptr inbounds float* %tmp23011, i64 1
-  %tmp23013 = getelementptr inbounds float* %tmp23012, i64 1
-  %tmp23014 = getelementptr inbounds float* %tmp23013, i64 1
-  %tmp23015 = getelementptr inbounds float* %tmp23014, i64 1
-  %tmp23016 = getelementptr inbounds float* %tmp23015, i64 1
-  %tmp23017 = getelementptr inbounds float* %tmp23016, i64 1
-  %tmp23018 = getelementptr inbounds float* %tmp23017, i64 1
-  %tmp23019 = getelementptr inbounds float* %tmp23018, i64 1
-  %tmp23020 = getelementptr inbounds float* %tmp23019, i64 1
-  %tmp23021 = getelementptr inbounds float* %tmp23020, i64 1
-  %tmp23022 = getelementptr inbounds float* %tmp23021, i64 1
-  %tmp23023 = getelementptr inbounds float* %tmp23022, i64 1
-  %tmp23024 = getelementptr inbounds float* %tmp23023, i64 1
-  %tmp23025 = getelementptr inbounds float* %tmp23024, i64 1
-  %tmp23026 = getelementptr inbounds float* %tmp23025, i64 1
-  %tmp23027 = getelementptr inbounds float* %tmp23026, i64 1
-  %tmp23028 = getelementptr inbounds float* %tmp23027, i64 1
-  %tmp23029 = getelementptr inbounds float* %tmp23028, i64 1
-  %tmp23030 = getelementptr inbounds float* %tmp23029, i64 1
-  %tmp23031 = getelementptr inbounds float* %tmp23030, i64 1
-  %tmp23032 = getelementptr inbounds float* %tmp23031, i64 1
-  %tmp23033 = getelementptr inbounds float* %tmp23032, i64 1
-  %tmp23034 = getelementptr inbounds float* %tmp23033, i64 1
-  %tmp23035 = getelementptr inbounds float* %tmp23034, i64 1
-  %tmp23036 = getelementptr inbounds float* %tmp23035, i64 1
-  %tmp23037 = getelementptr inbounds float* %tmp23036, i64 1
-  %tmp23038 = getelementptr inbounds float* %tmp23037, i64 1
-  %tmp23039 = getelementptr inbounds float* %tmp23038, i64 1
-  %tmp23040 = getelementptr inbounds float* %tmp23039, i64 1
-  %tmp23041 = getelementptr inbounds float* %tmp23040, i64 1
-  %tmp23042 = getelementptr inbounds float* %tmp23041, i64 1
-  %tmp23043 = getelementptr inbounds float* %tmp23042, i64 1
-  %tmp23044 = getelementptr inbounds float* %tmp23043, i64 1
-  %tmp23045 = getelementptr inbounds float* %tmp23044, i64 1
-  %tmp23046 = getelementptr inbounds float* %tmp23045, i64 1
-  %tmp23047 = getelementptr inbounds float* %tmp23046, i64 1
-  %tmp23048 = getelementptr inbounds float* %tmp23047, i64 1
-  %tmp23049 = getelementptr inbounds float* %tmp23048, i64 1
-  %tmp23050 = getelementptr inbounds float* %tmp23049, i64 1
-  %tmp23051 = getelementptr inbounds float* %tmp23050, i64 1
-  %tmp23052 = getelementptr inbounds float* %tmp23051, i64 1
-  %tmp23053 = getelementptr inbounds float* %tmp23052, i64 1
-  %tmp23054 = getelementptr inbounds float* %tmp23053, i64 1
-  %tmp23055 = getelementptr inbounds float* %tmp23054, i64 1
-  %tmp23056 = getelementptr inbounds float* %tmp23055, i64 1
-  %tmp23057 = getelementptr inbounds float* %tmp23056, i64 1
-  %tmp23058 = getelementptr inbounds float* %tmp23057, i64 1
-  %tmp23059 = getelementptr inbounds float* %tmp23058, i64 1
-  %tmp23060 = getelementptr inbounds float* %tmp23059, i64 1
-  %tmp23061 = getelementptr inbounds float* %tmp23060, i64 1
-  %tmp23062 = getelementptr inbounds float* %tmp23061, i64 1
-  %tmp23063 = getelementptr inbounds float* %tmp23062, i64 1
-  %tmp23064 = getelementptr inbounds float* %tmp23063, i64 1
-  %tmp23065 = getelementptr inbounds float* %tmp23064, i64 1
-  %tmp23066 = getelementptr inbounds float* %tmp23065, i64 1
-  %tmp23067 = getelementptr inbounds float* %tmp23066, i64 1
-  %tmp23068 = getelementptr inbounds float* %tmp23067, i64 1
-  %tmp23069 = getelementptr inbounds float* %tmp23068, i64 1
-  %tmp23070 = getelementptr inbounds float* %tmp23069, i64 1
-  %tmp23071 = getelementptr inbounds float* %tmp23070, i64 1
-  %tmp23072 = getelementptr inbounds float* %tmp23071, i64 1
-  %tmp23073 = getelementptr inbounds float* %tmp23072, i64 1
-  %tmp23074 = getelementptr inbounds float* %tmp23073, i64 1
-  %tmp23075 = getelementptr inbounds float* %tmp23074, i64 1
-  %tmp23076 = getelementptr inbounds float* %tmp23075, i64 1
-  %tmp23077 = getelementptr inbounds float* %tmp23076, i64 1
-  %tmp23078 = getelementptr inbounds float* %tmp23077, i64 1
-  %tmp23079 = getelementptr inbounds float* %tmp23078, i64 1
-  %tmp23080 = getelementptr inbounds float* %tmp23079, i64 1
-  %tmp23081 = getelementptr inbounds float* %tmp23080, i64 1
-  %tmp23082 = getelementptr inbounds float* %tmp23081, i64 1
-  %tmp23083 = getelementptr inbounds float* %tmp23082, i64 1
-  %tmp23084 = getelementptr inbounds float* %tmp23083, i64 1
-  %tmp23085 = getelementptr inbounds float* %tmp23084, i64 1
-  %tmp23086 = getelementptr inbounds float* %tmp23085, i64 1
-  %tmp23087 = getelementptr inbounds float* %tmp23086, i64 1
-  %tmp23088 = getelementptr inbounds float* %tmp23087, i64 1
-  %tmp23089 = getelementptr inbounds float* %tmp23088, i64 1
-  %tmp23090 = getelementptr inbounds float* %tmp23089, i64 1
-  %tmp23091 = getelementptr inbounds float* %tmp23090, i64 1
-  %tmp23092 = getelementptr inbounds float* %tmp23091, i64 1
-  %tmp23093 = getelementptr inbounds float* %tmp23092, i64 1
-  %tmp23094 = getelementptr inbounds float* %tmp23093, i64 1
-  %tmp23095 = getelementptr inbounds float* %tmp23094, i64 1
-  %tmp23096 = getelementptr inbounds float* %tmp23095, i64 1
-  %tmp23097 = getelementptr inbounds float* %tmp23096, i64 1
-  %tmp23098 = getelementptr inbounds float* %tmp23097, i64 1
-  %tmp23099 = getelementptr inbounds float* %tmp23098, i64 1
-  %tmp23100 = getelementptr inbounds float* %tmp23099, i64 1
-  %tmp23101 = getelementptr inbounds float* %tmp23100, i64 1
-  %tmp23102 = getelementptr inbounds float* %tmp23101, i64 1
-  %tmp23103 = getelementptr inbounds float* %tmp23102, i64 1
-  %tmp23104 = getelementptr inbounds float* %tmp23103, i64 1
-  %tmp23105 = getelementptr inbounds float* %tmp23104, i64 1
-  %tmp23106 = getelementptr inbounds float* %tmp23105, i64 1
-  %tmp23107 = getelementptr inbounds float* %tmp23106, i64 1
-  %tmp23108 = getelementptr inbounds float* %tmp23107, i64 1
-  %tmp23109 = getelementptr inbounds float* %tmp23108, i64 1
-  %tmp23110 = getelementptr inbounds float* %tmp23109, i64 1
-  %tmp23111 = getelementptr inbounds float* %tmp23110, i64 1
-  %tmp23112 = getelementptr inbounds float* %tmp23111, i64 1
-  %tmp23113 = getelementptr inbounds float* %tmp23112, i64 1
-  %tmp23114 = getelementptr inbounds float* %tmp23113, i64 1
-  %tmp23115 = getelementptr inbounds float* %tmp23114, i64 1
-  %tmp23116 = getelementptr inbounds float* %tmp23115, i64 1
-  %tmp23117 = getelementptr inbounds float* %tmp23116, i64 1
-  %tmp23118 = getelementptr inbounds float* %tmp23117, i64 1
-  %tmp23119 = getelementptr inbounds float* %tmp23118, i64 1
-  %tmp23120 = getelementptr inbounds float* %tmp23119, i64 1
-  %tmp23121 = getelementptr inbounds float* %tmp23120, i64 1
-  %tmp23122 = getelementptr inbounds float* %tmp23121, i64 1
-  %tmp23123 = getelementptr inbounds float* %tmp23122, i64 1
-  %tmp23124 = getelementptr inbounds float* %tmp23123, i64 1
-  %tmp23125 = getelementptr inbounds float* %tmp23124, i64 1
-  %tmp23126 = getelementptr inbounds float* %tmp23125, i64 1
-  %tmp23127 = getelementptr inbounds float* %tmp23126, i64 1
-  %tmp23128 = getelementptr inbounds float* %tmp23127, i64 1
-  %tmp23129 = getelementptr inbounds float* %tmp23128, i64 1
-  %tmp23130 = getelementptr inbounds float* %tmp23129, i64 1
-  %tmp23131 = getelementptr inbounds float* %tmp23130, i64 1
-  %tmp23132 = getelementptr inbounds float* %tmp23131, i64 1
-  %tmp23133 = getelementptr inbounds float* %tmp23132, i64 1
-  %tmp23134 = getelementptr inbounds float* %tmp23133, i64 1
-  %tmp23135 = getelementptr inbounds float* %tmp23134, i64 1
-  %tmp23136 = getelementptr inbounds float* %tmp23135, i64 1
-  %tmp23137 = getelementptr inbounds float* %tmp23136, i64 1
-  %tmp23138 = getelementptr inbounds float* %tmp23137, i64 1
-  %tmp23139 = getelementptr inbounds float* %tmp23138, i64 1
-  %tmp23140 = getelementptr inbounds float* %tmp23139, i64 1
-  %tmp23141 = getelementptr inbounds float* %tmp23140, i64 1
-  %tmp23142 = getelementptr inbounds float* %tmp23141, i64 1
-  %tmp23143 = getelementptr inbounds float* %tmp23142, i64 1
-  %tmp23144 = getelementptr inbounds float* %tmp23143, i64 1
-  %tmp23145 = getelementptr inbounds float* %tmp23144, i64 1
-  %tmp23146 = getelementptr inbounds float* %tmp23145, i64 1
-  %tmp23147 = getelementptr inbounds float* %tmp23146, i64 1
-  %tmp23148 = getelementptr inbounds float* %tmp23147, i64 1
-  %tmp23149 = getelementptr inbounds float* %tmp23148, i64 1
-  %tmp23150 = getelementptr inbounds float* %tmp23149, i64 1
-  %tmp23151 = getelementptr inbounds float* %tmp23150, i64 1
-  %tmp23152 = getelementptr inbounds float* %tmp23151, i64 1
-  %tmp23153 = getelementptr inbounds float* %tmp23152, i64 1
-  %tmp23154 = getelementptr inbounds float* %tmp23153, i64 1
-  %tmp23155 = getelementptr inbounds float* %tmp23154, i64 1
-  %tmp23156 = getelementptr inbounds float* %tmp23155, i64 1
-  %tmp23157 = getelementptr inbounds float* %tmp23156, i64 1
-  %tmp23158 = getelementptr inbounds float* %tmp23157, i64 1
-  %tmp23159 = getelementptr inbounds float* %tmp23158, i64 1
-  %tmp23160 = getelementptr inbounds float* %tmp23159, i64 1
-  %tmp23161 = getelementptr inbounds float* %tmp23160, i64 1
-  %tmp23162 = getelementptr inbounds float* %tmp23161, i64 1
-  %tmp23163 = getelementptr inbounds float* %tmp23162, i64 1
-  %tmp23164 = getelementptr inbounds float* %tmp23163, i64 1
-  %tmp23165 = getelementptr inbounds float* %tmp23164, i64 1
-  %tmp23166 = getelementptr inbounds float* %tmp23165, i64 1
-  %tmp23167 = getelementptr inbounds float* %tmp23166, i64 1
-  %tmp23168 = getelementptr inbounds float* %tmp23167, i64 1
-  %tmp23169 = getelementptr inbounds float* %tmp23168, i64 1
-  %tmp23170 = getelementptr inbounds float* %tmp23169, i64 1
-  %tmp23171 = getelementptr inbounds float* %tmp23170, i64 1
-  %tmp23172 = getelementptr inbounds float* %tmp23171, i64 1
-  %tmp23173 = getelementptr inbounds float* %tmp23172, i64 1
-  %tmp23174 = getelementptr inbounds float* %tmp23173, i64 1
-  %tmp23175 = getelementptr inbounds float* %tmp23174, i64 1
-  %tmp23176 = getelementptr inbounds float* %tmp23175, i64 1
-  %tmp23177 = getelementptr inbounds float* %tmp23176, i64 1
-  %tmp23178 = getelementptr inbounds float* %tmp23177, i64 1
-  %tmp23179 = getelementptr inbounds float* %tmp23178, i64 1
-  %tmp23180 = getelementptr inbounds float* %tmp23179, i64 1
-  %tmp23181 = getelementptr inbounds float* %tmp23180, i64 1
-  %tmp23182 = getelementptr inbounds float* %tmp23181, i64 1
-  %tmp23183 = getelementptr inbounds float* %tmp23182, i64 1
-  %tmp23184 = getelementptr inbounds float* %tmp23183, i64 1
-  %tmp23185 = getelementptr inbounds float* %tmp23184, i64 1
-  %tmp23186 = getelementptr inbounds float* %tmp23185, i64 1
-  %tmp23187 = getelementptr inbounds float* %tmp23186, i64 1
-  %tmp23188 = getelementptr inbounds float* %tmp23187, i64 1
-  %tmp23189 = getelementptr inbounds float* %tmp23188, i64 1
-  %tmp23190 = getelementptr inbounds float* %tmp23189, i64 1
-  %tmp23191 = getelementptr inbounds float* %tmp23190, i64 1
-  %tmp23192 = getelementptr inbounds float* %tmp23191, i64 1
-  %tmp23193 = getelementptr inbounds float* %tmp23192, i64 1
-  %tmp23194 = getelementptr inbounds float* %tmp23193, i64 1
-  %tmp23195 = getelementptr inbounds float* %tmp23194, i64 1
-  %tmp23196 = getelementptr inbounds float* %tmp23195, i64 1
-  %tmp23197 = getelementptr inbounds float* %tmp23196, i64 1
-  %tmp23198 = getelementptr inbounds float* %tmp23197, i64 1
-  %tmp23199 = getelementptr inbounds float* %tmp23198, i64 1
-  %tmp23200 = getelementptr inbounds float* %tmp23199, i64 1
-  %tmp23201 = getelementptr inbounds float* %tmp23200, i64 1
-  %tmp23202 = getelementptr inbounds float* %tmp23201, i64 1
-  %tmp23203 = getelementptr inbounds float* %tmp23202, i64 1
-  %tmp23204 = getelementptr inbounds float* %tmp23203, i64 1
-  %tmp23205 = getelementptr inbounds float* %tmp23204, i64 1
-  %tmp23206 = getelementptr inbounds float* %tmp23205, i64 1
-  %tmp23207 = getelementptr inbounds float* %tmp23206, i64 1
-  %tmp23208 = getelementptr inbounds float* %tmp23207, i64 1
-  %tmp23209 = getelementptr inbounds float* %tmp23208, i64 1
-  %tmp23210 = getelementptr inbounds float* %tmp23209, i64 1
-  %tmp23211 = getelementptr inbounds float* %tmp23210, i64 1
-  %tmp23212 = getelementptr inbounds float* %tmp23211, i64 1
-  %tmp23213 = getelementptr inbounds float* %tmp23212, i64 1
-  %tmp23214 = getelementptr inbounds float* %tmp23213, i64 1
-  %tmp23215 = getelementptr inbounds float* %tmp23214, i64 1
-  %tmp23216 = getelementptr inbounds float* %tmp23215, i64 1
-  %tmp23217 = getelementptr inbounds float* %tmp23216, i64 1
-  %tmp23218 = getelementptr inbounds float* %tmp23217, i64 1
-  %tmp23219 = getelementptr inbounds float* %tmp23218, i64 1
-  %tmp23220 = getelementptr inbounds float* %tmp23219, i64 1
-  %tmp23221 = getelementptr inbounds float* %tmp23220, i64 1
-  %tmp23222 = getelementptr inbounds float* %tmp23221, i64 1
-  %tmp23223 = getelementptr inbounds float* %tmp23222, i64 1
-  %tmp23224 = getelementptr inbounds float* %tmp23223, i64 1
-  %tmp23225 = getelementptr inbounds float* %tmp23224, i64 1
-  %tmp23226 = getelementptr inbounds float* %tmp23225, i64 1
-  %tmp23227 = getelementptr inbounds float* %tmp23226, i64 1
-  %tmp23228 = getelementptr inbounds float* %tmp23227, i64 1
-  %tmp23229 = getelementptr inbounds float* %tmp23228, i64 1
-  %tmp23230 = getelementptr inbounds float* %tmp23229, i64 1
-  %tmp23231 = getelementptr inbounds float* %tmp23230, i64 1
-  %tmp23232 = getelementptr inbounds float* %tmp23231, i64 1
-  %tmp23233 = getelementptr inbounds float* %tmp23232, i64 1
-  %tmp23234 = getelementptr inbounds float* %tmp23233, i64 1
-  %tmp23235 = getelementptr inbounds float* %tmp23234, i64 1
-  %tmp23236 = getelementptr inbounds float* %tmp23235, i64 1
-  %tmp23237 = getelementptr inbounds float* %tmp23236, i64 1
-  %tmp23238 = getelementptr inbounds float* %tmp23237, i64 1
-  %tmp23239 = getelementptr inbounds float* %tmp23238, i64 1
-  %tmp23240 = getelementptr inbounds float* %tmp23239, i64 1
-  %tmp23241 = getelementptr inbounds float* %tmp23240, i64 1
-  %tmp23242 = getelementptr inbounds float* %tmp23241, i64 1
-  %tmp23243 = getelementptr inbounds float* %tmp23242, i64 1
-  %tmp23244 = getelementptr inbounds float* %tmp23243, i64 1
-  %tmp23245 = getelementptr inbounds float* %tmp23244, i64 1
-  %tmp23246 = getelementptr inbounds float* %tmp23245, i64 1
-  %tmp23247 = getelementptr inbounds float* %tmp23246, i64 1
-  %tmp23248 = getelementptr inbounds float* %tmp23247, i64 1
-  %tmp23249 = getelementptr inbounds float* %tmp23248, i64 1
-  %tmp23250 = getelementptr inbounds float* %tmp23249, i64 1
-  %tmp23251 = getelementptr inbounds float* %tmp23250, i64 1
-  %tmp23252 = getelementptr inbounds float* %tmp23251, i64 1
-  %tmp23253 = getelementptr inbounds float* %tmp23252, i64 1
-  %tmp23254 = getelementptr inbounds float* %tmp23253, i64 1
-  %tmp23255 = getelementptr inbounds float* %tmp23254, i64 1
-  %tmp23256 = getelementptr inbounds float* %tmp23255, i64 1
-  %tmp23257 = getelementptr inbounds float* %tmp23256, i64 1
-  %tmp23258 = getelementptr inbounds float* %tmp23257, i64 1
-  %tmp23259 = getelementptr inbounds float* %tmp23258, i64 1
-  %tmp23260 = getelementptr inbounds float* %tmp23259, i64 1
-  %tmp23261 = getelementptr inbounds float* %tmp23260, i64 1
-  %tmp23262 = getelementptr inbounds float* %tmp23261, i64 1
-  %tmp23263 = getelementptr inbounds float* %tmp23262, i64 1
-  %tmp23264 = getelementptr inbounds float* %tmp23263, i64 1
-  %tmp23265 = getelementptr inbounds float* %tmp23264, i64 1
-  %tmp23266 = getelementptr inbounds float* %tmp23265, i64 1
-  %tmp23267 = getelementptr inbounds float* %tmp23266, i64 1
-  %tmp23268 = getelementptr inbounds float* %tmp23267, i64 1
-  %tmp23269 = getelementptr inbounds float* %tmp23268, i64 1
-  %tmp23270 = getelementptr inbounds float* %tmp23269, i64 1
-  %tmp23271 = getelementptr inbounds float* %tmp23270, i64 1
-  %tmp23272 = getelementptr inbounds float* %tmp23271, i64 1
-  %tmp23273 = getelementptr inbounds float* %tmp23272, i64 1
-  %tmp23274 = getelementptr inbounds float* %tmp23273, i64 1
-  %tmp23275 = getelementptr inbounds float* %tmp23274, i64 1
-  %tmp23276 = getelementptr inbounds float* %tmp23275, i64 1
-  %tmp23277 = getelementptr inbounds float* %tmp23276, i64 1
-  %tmp23278 = getelementptr inbounds float* %tmp23277, i64 1
-  %tmp23279 = getelementptr inbounds float* %tmp23278, i64 1
-  %tmp23280 = getelementptr inbounds float* %tmp23279, i64 1
-  %tmp23281 = getelementptr inbounds float* %tmp23280, i64 1
-  %tmp23282 = getelementptr inbounds float* %tmp23281, i64 1
-  %tmp23283 = getelementptr inbounds float* %tmp23282, i64 1
-  %tmp23284 = getelementptr inbounds float* %tmp23283, i64 1
-  %tmp23285 = getelementptr inbounds float* %tmp23284, i64 1
-  %tmp23286 = getelementptr inbounds float* %tmp23285, i64 1
-  %tmp23287 = getelementptr inbounds float* %tmp23286, i64 1
-  %tmp23288 = getelementptr inbounds float* %tmp23287, i64 1
-  %tmp23289 = getelementptr inbounds float* %tmp23288, i64 1
-  %tmp23290 = getelementptr inbounds float* %tmp23289, i64 1
-  %tmp23291 = getelementptr inbounds float* %tmp23290, i64 1
-  %tmp23292 = getelementptr inbounds float* %tmp23291, i64 1
-  %tmp23293 = getelementptr inbounds float* %tmp23292, i64 1
-  %tmp23294 = getelementptr inbounds float* %tmp23293, i64 1
-  %tmp23295 = getelementptr inbounds float* %tmp23294, i64 1
-  %tmp23296 = getelementptr inbounds float* %tmp23295, i64 1
-  %tmp23297 = getelementptr inbounds float* %tmp23296, i64 1
-  %tmp23298 = getelementptr inbounds float* %tmp23297, i64 1
-  %tmp23299 = getelementptr inbounds float* %tmp23298, i64 1
-  %tmp23300 = getelementptr inbounds float* %tmp23299, i64 1
-  %tmp23301 = getelementptr inbounds float* %tmp23300, i64 1
-  %tmp23302 = getelementptr inbounds float* %tmp23301, i64 1
-  %tmp23303 = getelementptr inbounds float* %tmp23302, i64 1
-  %tmp23304 = getelementptr inbounds float* %tmp23303, i64 1
-  %tmp23305 = getelementptr inbounds float* %tmp23304, i64 1
-  %tmp23306 = getelementptr inbounds float* %tmp23305, i64 1
-  %tmp23307 = getelementptr inbounds float* %tmp23306, i64 1
-  %tmp23308 = getelementptr inbounds float* %tmp23307, i64 1
-  %tmp23309 = getelementptr inbounds float* %tmp23308, i64 1
-  %tmp23310 = getelementptr inbounds float* %tmp23309, i64 1
-  %tmp23311 = getelementptr inbounds float* %tmp23310, i64 1
-  %tmp23312 = getelementptr inbounds float* %tmp23311, i64 1
-  %tmp23313 = getelementptr inbounds float* %tmp23312, i64 1
-  %tmp23314 = getelementptr inbounds float* %tmp23313, i64 1
-  %tmp23315 = getelementptr inbounds float* %tmp23314, i64 1
-  %tmp23316 = getelementptr inbounds float* %tmp23315, i64 1
-  %tmp23317 = getelementptr inbounds float* %tmp23316, i64 1
-  %tmp23318 = getelementptr inbounds float* %tmp23317, i64 1
-  %tmp23319 = getelementptr inbounds float* %tmp23318, i64 1
-  %tmp23320 = getelementptr inbounds float* %tmp23319, i64 1
-  %tmp23321 = getelementptr inbounds float* %tmp23320, i64 1
-  %tmp23322 = getelementptr inbounds float* %tmp23321, i64 1
-  %tmp23323 = getelementptr inbounds float* %tmp23322, i64 1
-  %tmp23324 = getelementptr inbounds float* %tmp23323, i64 1
-  %tmp23325 = getelementptr inbounds float* %tmp23324, i64 1
-  %tmp23326 = getelementptr inbounds float* %tmp23325, i64 1
-  %tmp23327 = getelementptr inbounds float* %tmp23326, i64 1
-  %tmp23328 = getelementptr inbounds float* %tmp23327, i64 1
-  %tmp23329 = getelementptr inbounds float* %tmp23328, i64 1
-  %tmp23330 = getelementptr inbounds float* %tmp23329, i64 1
-  %tmp23331 = getelementptr inbounds float* %tmp23330, i64 1
-  %tmp23332 = getelementptr inbounds float* %tmp23331, i64 1
-  %tmp23333 = getelementptr inbounds float* %tmp23332, i64 1
-  %tmp23334 = getelementptr inbounds float* %tmp23333, i64 1
-  %tmp23335 = getelementptr inbounds float* %tmp23334, i64 1
-  %tmp23336 = getelementptr inbounds float* %tmp23335, i64 1
-  %tmp23337 = getelementptr inbounds float* %tmp23336, i64 1
-  %tmp23338 = getelementptr inbounds float* %tmp23337, i64 1
-  %tmp23339 = getelementptr inbounds float* %tmp23338, i64 1
-  %tmp23340 = getelementptr inbounds float* %tmp23339, i64 1
-  %tmp23341 = getelementptr inbounds float* %tmp23340, i64 1
-  %tmp23342 = getelementptr inbounds float* %tmp23341, i64 1
-  %tmp23343 = getelementptr inbounds float* %tmp23342, i64 1
-  %tmp23344 = getelementptr inbounds float* %tmp23343, i64 1
-  %tmp23345 = getelementptr inbounds float* %tmp23344, i64 1
-  %tmp23346 = getelementptr inbounds float* %tmp23345, i64 1
-  %tmp23347 = getelementptr inbounds float* %tmp23346, i64 1
-  %tmp23348 = getelementptr inbounds float* %tmp23347, i64 1
-  %tmp23349 = getelementptr inbounds float* %tmp23348, i64 1
-  %tmp23350 = getelementptr inbounds float* %tmp23349, i64 1
-  %tmp23351 = getelementptr inbounds float* %tmp23350, i64 1
-  %tmp23352 = getelementptr inbounds float* %tmp23351, i64 1
-  %tmp23353 = getelementptr inbounds float* %tmp23352, i64 1
-  %tmp23354 = getelementptr inbounds float* %tmp23353, i64 1
-  %tmp23355 = getelementptr inbounds float* %tmp23354, i64 1
-  %tmp23356 = getelementptr inbounds float* %tmp23355, i64 1
-  %tmp23357 = getelementptr inbounds float* %tmp23356, i64 1
-  %tmp23358 = getelementptr inbounds float* %tmp23357, i64 1
-  %tmp23359 = getelementptr inbounds float* %tmp23358, i64 1
-  %tmp23360 = getelementptr inbounds float* %tmp23359, i64 1
-  %tmp23361 = getelementptr inbounds float* %tmp23360, i64 1
-  %tmp23362 = getelementptr inbounds float* %tmp23361, i64 1
-  %tmp23363 = getelementptr inbounds float* %tmp23362, i64 1
-  %tmp23364 = getelementptr inbounds float* %tmp23363, i64 1
-  %tmp23365 = getelementptr inbounds float* %tmp23364, i64 1
-  %tmp23366 = getelementptr inbounds float* %tmp23365, i64 1
-  %tmp23367 = getelementptr inbounds float* %tmp23366, i64 1
-  %tmp23368 = getelementptr inbounds float* %tmp23367, i64 1
-  %tmp23369 = getelementptr inbounds float* %tmp23368, i64 1
-  %tmp23370 = getelementptr inbounds float* %tmp23369, i64 1
-  %tmp23371 = getelementptr inbounds float* %tmp23370, i64 1
-  %tmp23372 = getelementptr inbounds float* %tmp23371, i64 1
-  %tmp23373 = getelementptr inbounds float* %tmp23372, i64 1
-  %tmp23374 = getelementptr inbounds float* %tmp23373, i64 1
-  %tmp23375 = getelementptr inbounds float* %tmp23374, i64 1
-  %tmp23376 = getelementptr inbounds float* %tmp23375, i64 1
-  %tmp23377 = getelementptr inbounds float* %tmp23376, i64 1
-  %tmp23378 = getelementptr inbounds float* %tmp23377, i64 1
-  %tmp23379 = getelementptr inbounds float* %tmp23378, i64 1
-  %tmp23380 = getelementptr inbounds float* %tmp23379, i64 1
-  %tmp23381 = getelementptr inbounds float* %tmp23380, i64 1
-  %tmp23382 = getelementptr inbounds float* %tmp23381, i64 1
-  %tmp23383 = getelementptr inbounds float* %tmp23382, i64 1
-  %tmp23384 = getelementptr inbounds float* %tmp23383, i64 1
-  %tmp23385 = getelementptr inbounds float* %tmp23384, i64 1
-  %tmp23386 = getelementptr inbounds float* %tmp23385, i64 1
-  %tmp23387 = getelementptr inbounds float* %tmp23386, i64 1
-  %tmp23388 = getelementptr inbounds float* %tmp23387, i64 1
-  %tmp23389 = getelementptr inbounds float* %tmp23388, i64 1
-  %tmp23390 = getelementptr inbounds float* %tmp23389, i64 1
-  %tmp23391 = getelementptr inbounds float* %tmp23390, i64 1
-  %tmp23392 = getelementptr inbounds float* %tmp23391, i64 1
-  %tmp23393 = getelementptr inbounds float* %tmp23392, i64 1
-  %tmp23394 = getelementptr inbounds float* %tmp23393, i64 1
-  %tmp23395 = getelementptr inbounds float* %tmp23394, i64 1
-  %tmp23396 = getelementptr inbounds float* %tmp23395, i64 1
-  %tmp23397 = getelementptr inbounds float* %tmp23396, i64 1
-  %tmp23398 = getelementptr inbounds float* %tmp23397, i64 1
-  %tmp23399 = getelementptr inbounds float* %tmp23398, i64 1
-  %tmp23400 = getelementptr inbounds float* %tmp23399, i64 1
-  %tmp23401 = getelementptr inbounds float* %tmp23400, i64 1
-  %tmp23402 = getelementptr inbounds float* %tmp23401, i64 1
-  %tmp23403 = getelementptr inbounds float* %tmp23402, i64 1
-  %tmp23404 = getelementptr inbounds float* %tmp23403, i64 1
-  %tmp23405 = getelementptr inbounds float* %tmp23404, i64 1
-  %tmp23406 = getelementptr inbounds float* %tmp23405, i64 1
-  %tmp23407 = getelementptr inbounds float* %tmp23406, i64 1
-  %tmp23408 = getelementptr inbounds float* %tmp23407, i64 1
-  %tmp23409 = getelementptr inbounds float* %tmp23408, i64 1
-  %tmp23410 = getelementptr inbounds float* %tmp23409, i64 1
-  %tmp23411 = getelementptr inbounds float* %tmp23410, i64 1
-  %tmp23412 = getelementptr inbounds float* %tmp23411, i64 1
-  %tmp23413 = getelementptr inbounds float* %tmp23412, i64 1
-  %tmp23414 = getelementptr inbounds float* %tmp23413, i64 1
-  %tmp23415 = getelementptr inbounds float* %tmp23414, i64 1
-  %tmp23416 = getelementptr inbounds float* %tmp23415, i64 1
-  %tmp23417 = getelementptr inbounds float* %tmp23416, i64 1
-  %tmp23418 = getelementptr inbounds float* %tmp23417, i64 1
-  %tmp23419 = getelementptr inbounds float* %tmp23418, i64 1
-  %tmp23420 = getelementptr inbounds float* %tmp23419, i64 1
-  %tmp23421 = getelementptr inbounds float* %tmp23420, i64 1
-  %tmp23422 = getelementptr inbounds float* %tmp23421, i64 1
-  %tmp23423 = getelementptr inbounds float* %tmp23422, i64 1
-  %tmp23424 = getelementptr inbounds float* %tmp23423, i64 1
-  %tmp23425 = getelementptr inbounds float* %tmp23424, i64 1
-  %tmp23426 = getelementptr inbounds float* %tmp23425, i64 1
-  %tmp23427 = getelementptr inbounds float* %tmp23426, i64 1
-  %tmp23428 = getelementptr inbounds float* %tmp23427, i64 1
-  %tmp23429 = getelementptr inbounds float* %tmp23428, i64 1
-  %tmp23430 = getelementptr inbounds float* %tmp23429, i64 1
-  %tmp23431 = getelementptr inbounds float* %tmp23430, i64 1
-  %tmp23432 = getelementptr inbounds float* %tmp23431, i64 1
-  %tmp23433 = getelementptr inbounds float* %tmp23432, i64 1
-  %tmp23434 = getelementptr inbounds float* %tmp23433, i64 1
-  %tmp23435 = getelementptr inbounds float* %tmp23434, i64 1
-  %tmp23436 = getelementptr inbounds float* %tmp23435, i64 1
-  %tmp23437 = getelementptr inbounds float* %tmp23436, i64 1
-  %tmp23438 = getelementptr inbounds float* %tmp23437, i64 1
-  %tmp23439 = getelementptr inbounds float* %tmp23438, i64 1
-  %tmp23440 = getelementptr inbounds float* %tmp23439, i64 1
-  %tmp23441 = getelementptr inbounds float* %tmp23440, i64 1
-  %tmp23442 = getelementptr inbounds float* %tmp23441, i64 1
-  %tmp23443 = getelementptr inbounds float* %tmp23442, i64 1
-  %tmp23444 = getelementptr inbounds float* %tmp23443, i64 1
-  %tmp23445 = getelementptr inbounds float* %tmp23444, i64 1
-  %tmp23446 = getelementptr inbounds float* %tmp23445, i64 1
-  %tmp23447 = getelementptr inbounds float* %tmp23446, i64 1
-  %tmp23448 = getelementptr inbounds float* %tmp23447, i64 1
-  %tmp23449 = getelementptr inbounds float* %tmp23448, i64 1
-  %tmp23450 = getelementptr inbounds float* %tmp23449, i64 1
-  %tmp23451 = getelementptr inbounds float* %tmp23450, i64 1
-  %tmp23452 = getelementptr inbounds float* %tmp23451, i64 1
-  %tmp23453 = getelementptr inbounds float* %tmp23452, i64 1
-  %tmp23454 = getelementptr inbounds float* %tmp23453, i64 1
-  %tmp23455 = getelementptr inbounds float* %tmp23454, i64 1
-  %tmp23456 = getelementptr inbounds float* %tmp23455, i64 1
-  %tmp23457 = getelementptr inbounds float* %tmp23456, i64 1
-  %tmp23458 = getelementptr inbounds float* %tmp23457, i64 1
-  %tmp23459 = getelementptr inbounds float* %tmp23458, i64 1
-  %tmp23460 = getelementptr inbounds float* %tmp23459, i64 1
-  %tmp23461 = getelementptr inbounds float* %tmp23460, i64 1
-  %tmp23462 = getelementptr inbounds float* %tmp23461, i64 1
-  %tmp23463 = getelementptr inbounds float* %tmp23462, i64 1
-  %tmp23464 = getelementptr inbounds float* %tmp23463, i64 1
-  %tmp23465 = getelementptr inbounds float* %tmp23464, i64 1
-  %tmp23466 = getelementptr inbounds float* %tmp23465, i64 1
-  %tmp23467 = getelementptr inbounds float* %tmp23466, i64 1
-  %tmp23468 = getelementptr inbounds float* %tmp23467, i64 1
-  %tmp23469 = getelementptr inbounds float* %tmp23468, i64 1
-  %tmp23470 = getelementptr inbounds float* %tmp23469, i64 1
-  %tmp23471 = getelementptr inbounds float* %tmp23470, i64 1
-  %tmp23472 = getelementptr inbounds float* %tmp23471, i64 1
-  %tmp23473 = getelementptr inbounds float* %tmp23472, i64 1
-  %tmp23474 = getelementptr inbounds float* %tmp23473, i64 1
-  %tmp23475 = getelementptr inbounds float* %tmp23474, i64 1
-  %tmp23476 = getelementptr inbounds float* %tmp23475, i64 1
-  %tmp23477 = getelementptr inbounds float* %tmp23476, i64 1
-  %tmp23478 = getelementptr inbounds float* %tmp23477, i64 1
-  %tmp23479 = getelementptr inbounds float* %tmp23478, i64 1
-  %tmp23480 = getelementptr inbounds float* %tmp23479, i64 1
-  %tmp23481 = getelementptr inbounds float* %tmp23480, i64 1
-  %tmp23482 = getelementptr inbounds float* %tmp23481, i64 1
-  %tmp23483 = getelementptr inbounds float* %tmp23482, i64 1
-  %tmp23484 = getelementptr inbounds float* %tmp23483, i64 1
-  %tmp23485 = getelementptr inbounds float* %tmp23484, i64 1
-  %tmp23486 = getelementptr inbounds float* %tmp23485, i64 1
-  %tmp23487 = getelementptr inbounds float* %tmp23486, i64 1
-  %tmp23488 = getelementptr inbounds float* %tmp23487, i64 1
-  %tmp23489 = getelementptr inbounds float* %tmp23488, i64 1
-  %tmp23490 = getelementptr inbounds float* %tmp23489, i64 1
-  %tmp23491 = getelementptr inbounds float* %tmp23490, i64 1
-  %tmp23492 = getelementptr inbounds float* %tmp23491, i64 1
-  %tmp23493 = getelementptr inbounds float* %tmp23492, i64 1
-  %tmp23494 = getelementptr inbounds float* %tmp23493, i64 1
-  %tmp23495 = getelementptr inbounds float* %tmp23494, i64 1
-  %tmp23496 = getelementptr inbounds float* %tmp23495, i64 1
-  %tmp23497 = getelementptr inbounds float* %tmp23496, i64 1
-  %tmp23498 = getelementptr inbounds float* %tmp23497, i64 1
-  %tmp23499 = getelementptr inbounds float* %tmp23498, i64 1
-  %tmp23500 = getelementptr inbounds float* %tmp23499, i64 1
-  %tmp23501 = getelementptr inbounds float* %tmp23500, i64 1
-  %tmp23502 = getelementptr inbounds float* %tmp23501, i64 1
-  %tmp23503 = getelementptr inbounds float* %tmp23502, i64 1
-  %tmp23504 = getelementptr inbounds float* %tmp23503, i64 1
-  %tmp23505 = getelementptr inbounds float* %tmp23504, i64 1
-  %tmp23506 = getelementptr inbounds float* %tmp23505, i64 1
-  %tmp23507 = getelementptr inbounds float* %tmp23506, i64 1
-  %tmp23508 = getelementptr inbounds float* %tmp23507, i64 1
-  %tmp23509 = getelementptr inbounds float* %tmp23508, i64 1
-  %tmp23510 = getelementptr inbounds float* %tmp23509, i64 1
-  %tmp23511 = getelementptr inbounds float* %tmp23510, i64 1
-  %tmp23512 = getelementptr inbounds float* %tmp23511, i64 1
-  %tmp23513 = getelementptr inbounds float* %tmp23512, i64 1
-  %tmp23514 = getelementptr inbounds float* %tmp23513, i64 1
-  %tmp23515 = getelementptr inbounds float* %tmp23514, i64 1
-  %tmp23516 = getelementptr inbounds float* %tmp23515, i64 1
-  %tmp23517 = getelementptr inbounds float* %tmp23516, i64 1
-  %tmp23518 = getelementptr inbounds float* %tmp23517, i64 1
-  %tmp23519 = getelementptr inbounds float* %tmp23518, i64 1
-  %tmp23520 = getelementptr inbounds float* %tmp23519, i64 1
-  %tmp23521 = getelementptr inbounds float* %tmp23520, i64 1
-  %tmp23522 = getelementptr inbounds float* %tmp23521, i64 1
-  %tmp23523 = getelementptr inbounds float* %tmp23522, i64 1
-  %tmp23524 = getelementptr inbounds float* %tmp23523, i64 1
-  %tmp23525 = getelementptr inbounds float* %tmp23524, i64 1
-  %tmp23526 = getelementptr inbounds float* %tmp23525, i64 1
-  %tmp23527 = getelementptr inbounds float* %tmp23526, i64 1
-  %tmp23528 = getelementptr inbounds float* %tmp23527, i64 1
-  %tmp23529 = getelementptr inbounds float* %tmp23528, i64 1
-  %tmp23530 = getelementptr inbounds float* %tmp23529, i64 1
-  %tmp23531 = getelementptr inbounds float* %tmp23530, i64 1
-  %tmp23532 = getelementptr inbounds float* %tmp23531, i64 1
-  %tmp23533 = getelementptr inbounds float* %tmp23532, i64 1
-  %tmp23534 = getelementptr inbounds float* %tmp23533, i64 1
-  %tmp23535 = getelementptr inbounds float* %tmp23534, i64 1
-  %tmp23536 = getelementptr inbounds float* %tmp23535, i64 1
-  %tmp23537 = getelementptr inbounds float* %tmp23536, i64 1
-  %tmp23538 = getelementptr inbounds float* %tmp23537, i64 1
-  %tmp23539 = getelementptr inbounds float* %tmp23538, i64 1
-  %tmp23540 = getelementptr inbounds float* %tmp23539, i64 1
-  %tmp23541 = getelementptr inbounds float* %tmp23540, i64 1
-  %tmp23542 = getelementptr inbounds float* %tmp23541, i64 1
-  %tmp23543 = getelementptr inbounds float* %tmp23542, i64 1
-  %tmp23544 = getelementptr inbounds float* %tmp23543, i64 1
-  %tmp23545 = getelementptr inbounds float* %tmp23544, i64 1
-  %tmp23546 = getelementptr inbounds float* %tmp23545, i64 1
-  %tmp23547 = getelementptr inbounds float* %tmp23546, i64 1
-  %tmp23548 = getelementptr inbounds float* %tmp23547, i64 1
-  %tmp23549 = getelementptr inbounds float* %tmp23548, i64 1
-  %tmp23550 = getelementptr inbounds float* %tmp23549, i64 1
-  %tmp23551 = getelementptr inbounds float* %tmp23550, i64 1
-  %tmp23552 = getelementptr inbounds float* %tmp23551, i64 1
-  %tmp23553 = getelementptr inbounds float* %tmp23552, i64 1
-  %tmp23554 = getelementptr inbounds float* %tmp23553, i64 1
-  %tmp23555 = getelementptr inbounds float* %tmp23554, i64 1
-  %tmp23556 = getelementptr inbounds float* %tmp23555, i64 1
-  %tmp23557 = getelementptr inbounds float* %tmp23556, i64 1
-  %tmp23558 = getelementptr inbounds float* %tmp23557, i64 1
-  %tmp23559 = getelementptr inbounds float* %tmp23558, i64 1
-  %tmp23560 = getelementptr inbounds float* %tmp23559, i64 1
-  %tmp23561 = getelementptr inbounds float* %tmp23560, i64 1
-  %tmp23562 = getelementptr inbounds float* %tmp23561, i64 1
-  %tmp23563 = getelementptr inbounds float* %tmp23562, i64 1
-  %tmp23564 = getelementptr inbounds float* %tmp23563, i64 1
-  %tmp23565 = getelementptr inbounds float* %tmp23564, i64 1
-  %tmp23566 = getelementptr inbounds float* %tmp23565, i64 1
-  %tmp23567 = getelementptr inbounds float* %tmp23566, i64 1
-  %tmp23568 = getelementptr inbounds float* %tmp23567, i64 1
-  %tmp23569 = getelementptr inbounds float* %tmp23568, i64 1
-  %tmp23570 = getelementptr inbounds float* %tmp23569, i64 1
-  %tmp23571 = getelementptr inbounds float* %tmp23570, i64 1
-  %tmp23572 = getelementptr inbounds float* %tmp23571, i64 1
-  %tmp23573 = getelementptr inbounds float* %tmp23572, i64 1
-  %tmp23574 = getelementptr inbounds float* %tmp23573, i64 1
-  %tmp23575 = getelementptr inbounds float* %tmp23574, i64 1
-  %tmp23576 = getelementptr inbounds float* %tmp23575, i64 1
-  %tmp23577 = getelementptr inbounds float* %tmp23576, i64 1
-  %tmp23578 = getelementptr inbounds float* %tmp23577, i64 1
-  %tmp23579 = getelementptr inbounds float* %tmp23578, i64 1
-  %tmp23580 = getelementptr inbounds float* %tmp23579, i64 1
-  %tmp23581 = getelementptr inbounds float* %tmp23580, i64 1
-  %tmp23582 = getelementptr inbounds float* %tmp23581, i64 1
-  %tmp23583 = getelementptr inbounds float* %tmp23582, i64 1
-  %tmp23584 = getelementptr inbounds float* %tmp23583, i64 1
-  %tmp23585 = getelementptr inbounds float* %tmp23584, i64 1
-  %tmp23586 = getelementptr inbounds float* %tmp23585, i64 1
-  %tmp23587 = getelementptr inbounds float* %tmp23586, i64 1
-  %tmp23588 = getelementptr inbounds float* %tmp23587, i64 1
-  %tmp23589 = getelementptr inbounds float* %tmp23588, i64 1
-  %tmp23590 = getelementptr inbounds float* %tmp23589, i64 1
-  %tmp23591 = getelementptr inbounds float* %tmp23590, i64 1
-  %tmp23592 = getelementptr inbounds float* %tmp23591, i64 1
-  %tmp23593 = getelementptr inbounds float* %tmp23592, i64 1
-  %tmp23594 = getelementptr inbounds float* %tmp23593, i64 1
-  %tmp23595 = getelementptr inbounds float* %tmp23594, i64 1
-  %tmp23596 = getelementptr inbounds float* %tmp23595, i64 1
-  %tmp23597 = getelementptr inbounds float* %tmp23596, i64 1
-  %tmp23598 = getelementptr inbounds float* %tmp23597, i64 1
-  %tmp23599 = getelementptr inbounds float* %tmp23598, i64 1
-  %tmp23600 = getelementptr inbounds float* %tmp23599, i64 1
-  %tmp23601 = getelementptr inbounds float* %tmp23600, i64 1
-  %tmp23602 = getelementptr inbounds float* %tmp23601, i64 1
-  %tmp23603 = getelementptr inbounds float* %tmp23602, i64 1
-  %tmp23604 = getelementptr inbounds float* %tmp23603, i64 1
-  %tmp23605 = getelementptr inbounds float* %tmp23604, i64 1
-  %tmp23606 = getelementptr inbounds float* %tmp23605, i64 1
-  %tmp23607 = getelementptr inbounds float* %tmp23606, i64 1
-  %tmp23608 = getelementptr inbounds float* %tmp23607, i64 1
-  %tmp23609 = getelementptr inbounds float* %tmp23608, i64 1
-  %tmp23610 = getelementptr inbounds float* %tmp23609, i64 1
-  %tmp23611 = getelementptr inbounds float* %tmp23610, i64 1
-  %tmp23612 = getelementptr inbounds float* %tmp23611, i64 1
-  %tmp23613 = getelementptr inbounds float* %tmp23612, i64 1
-  %tmp23614 = getelementptr inbounds float* %tmp23613, i64 1
-  %tmp23615 = getelementptr inbounds float* %tmp23614, i64 1
-  %tmp23616 = getelementptr inbounds float* %tmp23615, i64 1
-  %tmp23617 = getelementptr inbounds float* %tmp23616, i64 1
-  %tmp23618 = getelementptr inbounds float* %tmp23617, i64 1
-  %tmp23619 = getelementptr inbounds float* %tmp23618, i64 1
-  %tmp23620 = getelementptr inbounds float* %tmp23619, i64 1
-  %tmp23621 = getelementptr inbounds float* %tmp23620, i64 1
-  %tmp23622 = getelementptr inbounds float* %tmp23621, i64 1
-  %tmp23623 = getelementptr inbounds float* %tmp23622, i64 1
-  %tmp23624 = getelementptr inbounds float* %tmp23623, i64 1
-  %tmp23625 = getelementptr inbounds float* %tmp23624, i64 1
-  %tmp23626 = getelementptr inbounds float* %tmp23625, i64 1
-  %tmp23627 = getelementptr inbounds float* %tmp23626, i64 1
-  %tmp23628 = getelementptr inbounds float* %tmp23627, i64 1
-  %tmp23629 = getelementptr inbounds float* %tmp23628, i64 1
-  %tmp23630 = getelementptr inbounds float* %tmp23629, i64 1
-  %tmp23631 = getelementptr inbounds float* %tmp23630, i64 1
-  %tmp23632 = getelementptr inbounds float* %tmp23631, i64 1
-  %tmp23633 = getelementptr inbounds float* %tmp23632, i64 1
-  %tmp23634 = getelementptr inbounds float* %tmp23633, i64 1
-  %tmp23635 = getelementptr inbounds float* %tmp23634, i64 1
-  %tmp23636 = getelementptr inbounds float* %tmp23635, i64 1
-  %tmp23637 = getelementptr inbounds float* %tmp23636, i64 1
-  %tmp23638 = getelementptr inbounds float* %tmp23637, i64 1
-  %tmp23639 = getelementptr inbounds float* %tmp23638, i64 1
-  %tmp23640 = getelementptr inbounds float* %tmp23639, i64 1
-  %tmp23641 = getelementptr inbounds float* %tmp23640, i64 1
-  %tmp23642 = getelementptr inbounds float* %tmp23641, i64 1
-  %tmp23643 = getelementptr inbounds float* %tmp23642, i64 1
-  %tmp23644 = getelementptr inbounds float* %tmp23643, i64 1
-  %tmp23645 = getelementptr inbounds float* %tmp23644, i64 1
-  %tmp23646 = getelementptr inbounds float* %tmp23645, i64 1
-  %tmp23647 = getelementptr inbounds float* %tmp23646, i64 1
-  %tmp23648 = getelementptr inbounds float* %tmp23647, i64 1
-  %tmp23649 = getelementptr inbounds float* %tmp23648, i64 1
-  %tmp23650 = getelementptr inbounds float* %tmp23649, i64 1
-  %tmp23651 = getelementptr inbounds float* %tmp23650, i64 1
-  %tmp23652 = getelementptr inbounds float* %tmp23651, i64 1
-  %tmp23653 = getelementptr inbounds float* %tmp23652, i64 1
-  %tmp23654 = getelementptr inbounds float* %tmp23653, i64 1
-  %tmp23655 = getelementptr inbounds float* %tmp23654, i64 1
-  %tmp23656 = getelementptr inbounds float* %tmp23655, i64 1
-  %tmp23657 = getelementptr inbounds float* %tmp23656, i64 1
-  %tmp23658 = getelementptr inbounds float* %tmp23657, i64 1
-  %tmp23659 = getelementptr inbounds float* %tmp23658, i64 1
-  %tmp23660 = getelementptr inbounds float* %tmp23659, i64 1
-  %tmp23661 = getelementptr inbounds float* %tmp23660, i64 1
-  %tmp23662 = getelementptr inbounds float* %tmp23661, i64 1
-  %tmp23663 = getelementptr inbounds float* %tmp23662, i64 1
-  %tmp23664 = getelementptr inbounds float* %tmp23663, i64 1
-  %tmp23665 = getelementptr inbounds float* %tmp23664, i64 1
-  %tmp23666 = getelementptr inbounds float* %tmp23665, i64 1
-  %tmp23667 = getelementptr inbounds float* %tmp23666, i64 1
-  %tmp23668 = getelementptr inbounds float* %tmp23667, i64 1
-  %tmp23669 = getelementptr inbounds float* %tmp23668, i64 1
-  %tmp23670 = getelementptr inbounds float* %tmp23669, i64 1
-  %tmp23671 = getelementptr inbounds float* %tmp23670, i64 1
-  %tmp23672 = getelementptr inbounds float* %tmp23671, i64 1
-  %tmp23673 = getelementptr inbounds float* %tmp23672, i64 1
-  %tmp23674 = getelementptr inbounds float* %tmp23673, i64 1
-  %tmp23675 = getelementptr inbounds float* %tmp23674, i64 1
-  %tmp23676 = getelementptr inbounds float* %tmp23675, i64 1
-  %tmp23677 = getelementptr inbounds float* %tmp23676, i64 1
-  %tmp23678 = getelementptr inbounds float* %tmp23677, i64 1
-  %tmp23679 = getelementptr inbounds float* %tmp23678, i64 1
-  %tmp23680 = getelementptr inbounds float* %tmp23679, i64 1
-  %tmp23681 = getelementptr inbounds float* %tmp23680, i64 1
-  %tmp23682 = getelementptr inbounds float* %tmp23681, i64 1
-  %tmp23683 = getelementptr inbounds float* %tmp23682, i64 1
-  %tmp23684 = getelementptr inbounds float* %tmp23683, i64 1
-  %tmp23685 = getelementptr inbounds float* %tmp23684, i64 1
-  %tmp23686 = getelementptr inbounds float* %tmp23685, i64 1
-  %tmp23687 = getelementptr inbounds float* %tmp23686, i64 1
-  %tmp23688 = getelementptr inbounds float* %tmp23687, i64 1
-  %tmp23689 = getelementptr inbounds float* %tmp23688, i64 1
-  %tmp23690 = getelementptr inbounds float* %tmp23689, i64 1
-  %tmp23691 = getelementptr inbounds float* %tmp23690, i64 1
-  %tmp23692 = getelementptr inbounds float* %tmp23691, i64 1
-  %tmp23693 = getelementptr inbounds float* %tmp23692, i64 1
-  %tmp23694 = getelementptr inbounds float* %tmp23693, i64 1
-  %tmp23695 = getelementptr inbounds float* %tmp23694, i64 1
-  %tmp23696 = getelementptr inbounds float* %tmp23695, i64 1
-  %tmp23697 = getelementptr inbounds float* %tmp23696, i64 1
-  %tmp23698 = getelementptr inbounds float* %tmp23697, i64 1
-  %tmp23699 = getelementptr inbounds float* %tmp23698, i64 1
-  %tmp23700 = getelementptr inbounds float* %tmp23699, i64 1
-  %tmp23701 = getelementptr inbounds float* %tmp23700, i64 1
-  %tmp23702 = getelementptr inbounds float* %tmp23701, i64 1
-  %tmp23703 = getelementptr inbounds float* %tmp23702, i64 1
-  %tmp23704 = getelementptr inbounds float* %tmp23703, i64 1
-  %tmp23705 = getelementptr inbounds float* %tmp23704, i64 1
-  %tmp23706 = getelementptr inbounds float* %tmp23705, i64 1
-  %tmp23707 = getelementptr inbounds float* %tmp23706, i64 1
-  %tmp23708 = getelementptr inbounds float* %tmp23707, i64 1
-  %tmp23709 = getelementptr inbounds float* %tmp23708, i64 1
-  %tmp23710 = getelementptr inbounds float* %tmp23709, i64 1
-  %tmp23711 = getelementptr inbounds float* %tmp23710, i64 1
-  %tmp23712 = getelementptr inbounds float* %tmp23711, i64 1
-  %tmp23713 = getelementptr inbounds float* %tmp23712, i64 1
-  %tmp23714 = getelementptr inbounds float* %tmp23713, i64 1
-  %tmp23715 = getelementptr inbounds float* %tmp23714, i64 1
-  %tmp23716 = getelementptr inbounds float* %tmp23715, i64 1
-  %tmp23717 = getelementptr inbounds float* %tmp23716, i64 1
-  %tmp23718 = getelementptr inbounds float* %tmp23717, i64 1
-  %tmp23719 = getelementptr inbounds float* %tmp23718, i64 1
-  %tmp23720 = getelementptr inbounds float* %tmp23719, i64 1
-  %tmp23721 = getelementptr inbounds float* %tmp23720, i64 1
-  %tmp23722 = getelementptr inbounds float* %tmp23721, i64 1
-  %tmp23723 = getelementptr inbounds float* %tmp23722, i64 1
-  %tmp23724 = getelementptr inbounds float* %tmp23723, i64 1
-  %tmp23725 = getelementptr inbounds float* %tmp23724, i64 1
-  %tmp23726 = getelementptr inbounds float* %tmp23725, i64 1
-  %tmp23727 = getelementptr inbounds float* %tmp23726, i64 1
-  %tmp23728 = getelementptr inbounds float* %tmp23727, i64 1
-  %tmp23729 = getelementptr inbounds float* %tmp23728, i64 1
-  %tmp23730 = getelementptr inbounds float* %tmp23729, i64 1
-  %tmp23731 = getelementptr inbounds float* %tmp23730, i64 1
-  %tmp23732 = getelementptr inbounds float* %tmp23731, i64 1
-  %tmp23733 = getelementptr inbounds float* %tmp23732, i64 1
-  %tmp23734 = getelementptr inbounds float* %tmp23733, i64 1
-  %tmp23735 = getelementptr inbounds float* %tmp23734, i64 1
-  %tmp23736 = getelementptr inbounds float* %tmp23735, i64 1
-  %tmp23737 = getelementptr inbounds float* %tmp23736, i64 1
-  %tmp23738 = getelementptr inbounds float* %tmp23737, i64 1
-  %tmp23739 = getelementptr inbounds float* %tmp23738, i64 1
-  %tmp23740 = getelementptr inbounds float* %tmp23739, i64 1
-  %tmp23741 = getelementptr inbounds float* %tmp23740, i64 1
-  %tmp23742 = getelementptr inbounds float* %tmp23741, i64 1
-  %tmp23743 = getelementptr inbounds float* %tmp23742, i64 1
-  %tmp23744 = getelementptr inbounds float* %tmp23743, i64 1
-  %tmp23745 = getelementptr inbounds float* %tmp23744, i64 1
-  %tmp23746 = getelementptr inbounds float* %tmp23745, i64 1
-  %tmp23747 = getelementptr inbounds float* %tmp23746, i64 1
-  %tmp23748 = getelementptr inbounds float* %tmp23747, i64 1
-  %tmp23749 = getelementptr inbounds float* %tmp23748, i64 1
-  %tmp23750 = getelementptr inbounds float* %tmp23749, i64 1
-  %tmp23751 = getelementptr inbounds float* %tmp23750, i64 1
-  %tmp23752 = getelementptr inbounds float* %tmp23751, i64 1
-  %tmp23753 = getelementptr inbounds float* %tmp23752, i64 1
-  %tmp23754 = getelementptr inbounds float* %tmp23753, i64 1
-  %tmp23755 = getelementptr inbounds float* %tmp23754, i64 1
-  %tmp23756 = getelementptr inbounds float* %tmp23755, i64 1
-  %tmp23757 = getelementptr inbounds float* %tmp23756, i64 1
-  %tmp23758 = getelementptr inbounds float* %tmp23757, i64 1
-  %tmp23759 = getelementptr inbounds float* %tmp23758, i64 1
-  %tmp23760 = getelementptr inbounds float* %tmp23759, i64 1
-  %tmp23761 = getelementptr inbounds float* %tmp23760, i64 1
-  %tmp23762 = getelementptr inbounds float* %tmp23761, i64 1
-  %tmp23763 = getelementptr inbounds float* %tmp23762, i64 1
-  %tmp23764 = getelementptr inbounds float* %tmp23763, i64 1
-  %tmp23765 = getelementptr inbounds float* %tmp23764, i64 1
-  %tmp23766 = getelementptr inbounds float* %tmp23765, i64 1
-  %tmp23767 = getelementptr inbounds float* %tmp23766, i64 1
-  %tmp23768 = getelementptr inbounds float* %tmp23767, i64 1
-  %tmp23769 = getelementptr inbounds float* %tmp23768, i64 1
-  %tmp23770 = getelementptr inbounds float* %tmp23769, i64 1
-  %tmp23771 = getelementptr inbounds float* %tmp23770, i64 1
-  %tmp23772 = getelementptr inbounds float* %tmp23771, i64 1
-  %tmp23773 = getelementptr inbounds float* %tmp23772, i64 1
-  %tmp23774 = getelementptr inbounds float* %tmp23773, i64 1
-  %tmp23775 = getelementptr inbounds float* %tmp23774, i64 1
-  %tmp23776 = getelementptr inbounds float* %tmp23775, i64 1
-  %tmp23777 = getelementptr inbounds float* %tmp23776, i64 1
-  %tmp23778 = getelementptr inbounds float* %tmp23777, i64 1
-  %tmp23779 = getelementptr inbounds float* %tmp23778, i64 1
-  %tmp23780 = getelementptr inbounds float* %tmp23779, i64 1
-  %tmp23781 = getelementptr inbounds float* %tmp23780, i64 1
-  %tmp23782 = getelementptr inbounds float* %tmp23781, i64 1
-  %tmp23783 = getelementptr inbounds float* %tmp23782, i64 1
-  %tmp23784 = getelementptr inbounds float* %tmp23783, i64 1
-  %tmp23785 = getelementptr inbounds float* %tmp23784, i64 1
-  %tmp23786 = getelementptr inbounds float* %tmp23785, i64 1
-  %tmp23787 = getelementptr inbounds float* %tmp23786, i64 1
-  %tmp23788 = getelementptr inbounds float* %tmp23787, i64 1
-  %tmp23789 = getelementptr inbounds float* %tmp23788, i64 1
-  %tmp23790 = getelementptr inbounds float* %tmp23789, i64 1
-  %tmp23791 = getelementptr inbounds float* %tmp23790, i64 1
-  %tmp23792 = getelementptr inbounds float* %tmp23791, i64 1
-  %tmp23793 = getelementptr inbounds float* %tmp23792, i64 1
-  %tmp23794 = getelementptr inbounds float* %tmp23793, i64 1
-  %tmp23795 = getelementptr inbounds float* %tmp23794, i64 1
-  %tmp23796 = getelementptr inbounds float* %tmp23795, i64 1
-  %tmp23797 = getelementptr inbounds float* %tmp23796, i64 1
-  %tmp23798 = getelementptr inbounds float* %tmp23797, i64 1
-  %tmp23799 = getelementptr inbounds float* %tmp23798, i64 1
-  %tmp23800 = getelementptr inbounds float* %tmp23799, i64 1
-  %tmp23801 = getelementptr inbounds float* %tmp23800, i64 1
-  %tmp23802 = getelementptr inbounds float* %tmp23801, i64 1
-  %tmp23803 = getelementptr inbounds float* %tmp23802, i64 1
-  %tmp23804 = getelementptr inbounds float* %tmp23803, i64 1
-  %tmp23805 = getelementptr inbounds float* %tmp23804, i64 1
-  %tmp23806 = getelementptr inbounds float* %tmp23805, i64 1
-  %tmp23807 = getelementptr inbounds float* %tmp23806, i64 1
-  %tmp23808 = getelementptr inbounds float* %tmp23807, i64 1
-  %tmp23809 = getelementptr inbounds float* %tmp23808, i64 1
-  %tmp23810 = getelementptr inbounds float* %tmp23809, i64 1
-  %tmp23811 = getelementptr inbounds float* %tmp23810, i64 1
-  %tmp23812 = getelementptr inbounds float* %tmp23811, i64 1
-  %tmp23813 = getelementptr inbounds float* %tmp23812, i64 1
-  %tmp23814 = getelementptr inbounds float* %tmp23813, i64 1
-  %tmp23815 = getelementptr inbounds float* %tmp23814, i64 1
-  %tmp23816 = getelementptr inbounds float* %tmp23815, i64 1
-  %tmp23817 = getelementptr inbounds float* %tmp23816, i64 1
-  %tmp23818 = getelementptr inbounds float* %tmp23817, i64 1
-  %tmp23819 = getelementptr inbounds float* %tmp23818, i64 1
-  %tmp23820 = getelementptr inbounds float* %tmp23819, i64 1
-  %tmp23821 = getelementptr inbounds float* %tmp23820, i64 1
-  %tmp23822 = getelementptr inbounds float* %tmp23821, i64 1
-  %tmp23823 = getelementptr inbounds float* %tmp23822, i64 1
-  %tmp23824 = getelementptr inbounds float* %tmp23823, i64 1
-  %tmp23825 = getelementptr inbounds float* %tmp23824, i64 1
-  %tmp23826 = getelementptr inbounds float* %tmp23825, i64 1
-  %tmp23827 = getelementptr inbounds float* %tmp23826, i64 1
-  %tmp23828 = getelementptr inbounds float* %tmp23827, i64 1
-  %tmp23829 = getelementptr inbounds float* %tmp23828, i64 1
-  %tmp23830 = getelementptr inbounds float* %tmp23829, i64 1
-  %tmp23831 = getelementptr inbounds float* %tmp23830, i64 1
-  %tmp23832 = getelementptr inbounds float* %tmp23831, i64 1
-  %tmp23833 = getelementptr inbounds float* %tmp23832, i64 1
-  %tmp23834 = getelementptr inbounds float* %tmp23833, i64 1
-  %tmp23835 = getelementptr inbounds float* %tmp23834, i64 1
-  %tmp23836 = getelementptr inbounds float* %tmp23835, i64 1
-  %tmp23837 = getelementptr inbounds float* %tmp23836, i64 1
-  %tmp23838 = getelementptr inbounds float* %tmp23837, i64 1
-  %tmp23839 = getelementptr inbounds float* %tmp23838, i64 1
-  %tmp23840 = getelementptr inbounds float* %tmp23839, i64 1
-  %tmp23841 = getelementptr inbounds float* %tmp23840, i64 1
-  %tmp23842 = getelementptr inbounds float* %tmp23841, i64 1
-  %tmp23843 = getelementptr inbounds float* %tmp23842, i64 1
-  %tmp23844 = getelementptr inbounds float* %tmp23843, i64 1
-  %tmp23845 = getelementptr inbounds float* %tmp23844, i64 1
-  %tmp23846 = getelementptr inbounds float* %tmp23845, i64 1
-  %tmp23847 = getelementptr inbounds float* %tmp23846, i64 1
-  %tmp23848 = getelementptr inbounds float* %tmp23847, i64 1
-  %tmp23849 = getelementptr inbounds float* %tmp23848, i64 1
-  %tmp23850 = getelementptr inbounds float* %tmp23849, i64 1
-  %tmp23851 = getelementptr inbounds float* %tmp23850, i64 1
-  %tmp23852 = getelementptr inbounds float* %tmp23851, i64 1
-  %tmp23853 = getelementptr inbounds float* %tmp23852, i64 1
-  %tmp23854 = getelementptr inbounds float* %tmp23853, i64 1
-  %tmp23855 = getelementptr inbounds float* %tmp23854, i64 1
-  %tmp23856 = getelementptr inbounds float* %tmp23855, i64 1
-  %tmp23857 = getelementptr inbounds float* %tmp23856, i64 1
-  %tmp23858 = getelementptr inbounds float* %tmp23857, i64 1
-  %tmp23859 = getelementptr inbounds float* %tmp23858, i64 1
-  %tmp23860 = getelementptr inbounds float* %tmp23859, i64 1
-  %tmp23861 = getelementptr inbounds float* %tmp23860, i64 1
-  %tmp23862 = getelementptr inbounds float* %tmp23861, i64 1
-  %tmp23863 = getelementptr inbounds float* %tmp23862, i64 1
-  %tmp23864 = getelementptr inbounds float* %tmp23863, i64 1
-  %tmp23865 = getelementptr inbounds float* %tmp23864, i64 1
-  %tmp23866 = getelementptr inbounds float* %tmp23865, i64 1
-  %tmp23867 = getelementptr inbounds float* %tmp23866, i64 1
-  %tmp23868 = getelementptr inbounds float* %tmp23867, i64 1
-  %tmp23869 = getelementptr inbounds float* %tmp23868, i64 1
-  %tmp23870 = getelementptr inbounds float* %tmp23869, i64 1
-  %tmp23871 = getelementptr inbounds float* %tmp23870, i64 1
-  %tmp23872 = getelementptr inbounds float* %tmp23871, i64 1
-  %tmp23873 = getelementptr inbounds float* %tmp23872, i64 1
-  %tmp23874 = getelementptr inbounds float* %tmp23873, i64 1
-  %tmp23875 = getelementptr inbounds float* %tmp23874, i64 1
-  %tmp23876 = getelementptr inbounds float* %tmp23875, i64 1
-  %tmp23877 = getelementptr inbounds float* %tmp23876, i64 1
-  %tmp23878 = getelementptr inbounds float* %tmp23877, i64 1
-  %tmp23879 = getelementptr inbounds float* %tmp23878, i64 1
-  %tmp23880 = getelementptr inbounds float* %tmp23879, i64 1
-  %tmp23881 = getelementptr inbounds float* %tmp23880, i64 1
-  %tmp23882 = getelementptr inbounds float* %tmp23881, i64 1
-  %tmp23883 = getelementptr inbounds float* %tmp23882, i64 1
-  %tmp23884 = getelementptr inbounds float* %tmp23883, i64 1
-  %tmp23885 = getelementptr inbounds float* %tmp23884, i64 1
-  %tmp23886 = getelementptr inbounds float* %tmp23885, i64 1
-  %tmp23887 = getelementptr inbounds float* %tmp23886, i64 1
-  %tmp23888 = getelementptr inbounds float* %tmp23887, i64 1
-  %tmp23889 = getelementptr inbounds float* %tmp23888, i64 1
-  %tmp23890 = getelementptr inbounds float* %tmp23889, i64 1
-  %tmp23891 = getelementptr inbounds float* %tmp23890, i64 1
-  %tmp23892 = getelementptr inbounds float* %tmp23891, i64 1
-  %tmp23893 = getelementptr inbounds float* %tmp23892, i64 1
-  %tmp23894 = getelementptr inbounds float* %tmp23893, i64 1
-  %tmp23895 = getelementptr inbounds float* %tmp23894, i64 1
-  %tmp23896 = getelementptr inbounds float* %tmp23895, i64 1
-  %tmp23897 = getelementptr inbounds float* %tmp23896, i64 1
-  %tmp23898 = getelementptr inbounds float* %tmp23897, i64 1
-  %tmp23899 = getelementptr inbounds float* %tmp23898, i64 1
-  %tmp23900 = getelementptr inbounds float* %tmp23899, i64 1
-  %tmp23901 = getelementptr inbounds float* %tmp23900, i64 1
-  %tmp23902 = getelementptr inbounds float* %tmp23901, i64 1
-  %tmp23903 = getelementptr inbounds float* %tmp23902, i64 1
-  %tmp23904 = getelementptr inbounds float* %tmp23903, i64 1
-  %tmp23905 = getelementptr inbounds float* %tmp23904, i64 1
-  %tmp23906 = getelementptr inbounds float* %tmp23905, i64 1
-  %tmp23907 = getelementptr inbounds float* %tmp23906, i64 1
-  %tmp23908 = getelementptr inbounds float* %tmp23907, i64 1
-  %tmp23909 = getelementptr inbounds float* %tmp23908, i64 1
-  %tmp23910 = getelementptr inbounds float* %tmp23909, i64 1
-  %tmp23911 = getelementptr inbounds float* %tmp23910, i64 1
-  %tmp23912 = getelementptr inbounds float* %tmp23911, i64 1
-  %tmp23913 = getelementptr inbounds float* %tmp23912, i64 1
-  %tmp23914 = getelementptr inbounds float* %tmp23913, i64 1
-  %tmp23915 = getelementptr inbounds float* %tmp23914, i64 1
-  %tmp23916 = getelementptr inbounds float* %tmp23915, i64 1
-  %tmp23917 = getelementptr inbounds float* %tmp23916, i64 1
-  %tmp23918 = getelementptr inbounds float* %tmp23917, i64 1
-  %tmp23919 = getelementptr inbounds float* %tmp23918, i64 1
-  %tmp23920 = getelementptr inbounds float* %tmp23919, i64 1
-  %tmp23921 = getelementptr inbounds float* %tmp23920, i64 1
-  %tmp23922 = getelementptr inbounds float* %tmp23921, i64 1
-  %tmp23923 = getelementptr inbounds float* %tmp23922, i64 1
-  %tmp23924 = getelementptr inbounds float* %tmp23923, i64 1
-  %tmp23925 = getelementptr inbounds float* %tmp23924, i64 1
-  %tmp23926 = getelementptr inbounds float* %tmp23925, i64 1
-  %tmp23927 = getelementptr inbounds float* %tmp23926, i64 1
-  %tmp23928 = getelementptr inbounds float* %tmp23927, i64 1
-  %tmp23929 = getelementptr inbounds float* %tmp23928, i64 1
-  %tmp23930 = getelementptr inbounds float* %tmp23929, i64 1
-  %tmp23931 = getelementptr inbounds float* %tmp23930, i64 1
-  %tmp23932 = getelementptr inbounds float* %tmp23931, i64 1
-  %tmp23933 = getelementptr inbounds float* %tmp23932, i64 1
-  %tmp23934 = getelementptr inbounds float* %tmp23933, i64 1
-  %tmp23935 = getelementptr inbounds float* %tmp23934, i64 1
-  %tmp23936 = getelementptr inbounds float* %tmp23935, i64 1
-  %tmp23937 = getelementptr inbounds float* %tmp23936, i64 1
-  %tmp23938 = getelementptr inbounds float* %tmp23937, i64 1
-  %tmp23939 = getelementptr inbounds float* %tmp23938, i64 1
-  %tmp23940 = getelementptr inbounds float* %tmp23939, i64 1
-  %tmp23941 = getelementptr inbounds float* %tmp23940, i64 1
-  %tmp23942 = getelementptr inbounds float* %tmp23941, i64 1
-  %tmp23943 = getelementptr inbounds float* %tmp23942, i64 1
-  %tmp23944 = getelementptr inbounds float* %tmp23943, i64 1
-  %tmp23945 = getelementptr inbounds float* %tmp23944, i64 1
-  %tmp23946 = getelementptr inbounds float* %tmp23945, i64 1
-  %tmp23947 = getelementptr inbounds float* %tmp23946, i64 1
-  %tmp23948 = getelementptr inbounds float* %tmp23947, i64 1
-  %tmp23949 = getelementptr inbounds float* %tmp23948, i64 1
-  %tmp23950 = getelementptr inbounds float* %tmp23949, i64 1
-  %tmp23951 = getelementptr inbounds float* %tmp23950, i64 1
-  %tmp23952 = getelementptr inbounds float* %tmp23951, i64 1
-  %tmp23953 = getelementptr inbounds float* %tmp23952, i64 1
-  %tmp23954 = getelementptr inbounds float* %tmp23953, i64 1
-  %tmp23955 = getelementptr inbounds float* %tmp23954, i64 1
-  %tmp23956 = getelementptr inbounds float* %tmp23955, i64 1
-  %tmp23957 = getelementptr inbounds float* %tmp23956, i64 1
-  %tmp23958 = getelementptr inbounds float* %tmp23957, i64 1
-  %tmp23959 = getelementptr inbounds float* %tmp23958, i64 1
-  %tmp23960 = getelementptr inbounds float* %tmp23959, i64 1
-  %tmp23961 = getelementptr inbounds float* %tmp23960, i64 1
-  %tmp23962 = getelementptr inbounds float* %tmp23961, i64 1
-  %tmp23963 = getelementptr inbounds float* %tmp23962, i64 1
-  %tmp23964 = getelementptr inbounds float* %tmp23963, i64 1
-  %tmp23965 = getelementptr inbounds float* %tmp23964, i64 1
-  %tmp23966 = getelementptr inbounds float* %tmp23965, i64 1
-  %tmp23967 = getelementptr inbounds float* %tmp23966, i64 1
-  %tmp23968 = getelementptr inbounds float* %tmp23967, i64 1
-  %tmp23969 = getelementptr inbounds float* %tmp23968, i64 1
-  %tmp23970 = getelementptr inbounds float* %tmp23969, i64 1
-  %tmp23971 = getelementptr inbounds float* %tmp23970, i64 1
-  %tmp23972 = getelementptr inbounds float* %tmp23971, i64 1
-  %tmp23973 = getelementptr inbounds float* %tmp23972, i64 1
-  %tmp23974 = getelementptr inbounds float* %tmp23973, i64 1
-  %tmp23975 = getelementptr inbounds float* %tmp23974, i64 1
-  %tmp23976 = getelementptr inbounds float* %tmp23975, i64 1
-  %tmp23977 = getelementptr inbounds float* %tmp23976, i64 1
-  %tmp23978 = getelementptr inbounds float* %tmp23977, i64 1
-  %tmp23979 = getelementptr inbounds float* %tmp23978, i64 1
-  %tmp23980 = getelementptr inbounds float* %tmp23979, i64 1
-  %tmp23981 = getelementptr inbounds float* %tmp23980, i64 1
-  %tmp23982 = getelementptr inbounds float* %tmp23981, i64 1
-  %tmp23983 = getelementptr inbounds float* %tmp23982, i64 1
-  %tmp23984 = getelementptr inbounds float* %tmp23983, i64 1
-  %tmp23985 = getelementptr inbounds float* %tmp23984, i64 1
-  %tmp23986 = getelementptr inbounds float* %tmp23985, i64 1
-  %tmp23987 = getelementptr inbounds float* %tmp23986, i64 1
-  %tmp23988 = getelementptr inbounds float* %tmp23987, i64 1
-  %tmp23989 = getelementptr inbounds float* %tmp23988, i64 1
-  %tmp23990 = getelementptr inbounds float* %tmp23989, i64 1
-  %tmp23991 = getelementptr inbounds float* %tmp23990, i64 1
-  %tmp23992 = getelementptr inbounds float* %tmp23991, i64 1
-  %tmp23993 = getelementptr inbounds float* %tmp23992, i64 1
-  %tmp23994 = getelementptr inbounds float* %tmp23993, i64 1
-  %tmp23995 = getelementptr inbounds float* %tmp23994, i64 1
-  %tmp23996 = getelementptr inbounds float* %tmp23995, i64 1
-  %tmp23997 = getelementptr inbounds float* %tmp23996, i64 1
-  %tmp23998 = getelementptr inbounds float* %tmp23997, i64 1
-  %tmp23999 = getelementptr inbounds float* %tmp23998, i64 1
-  %tmp24000 = getelementptr inbounds float* %tmp23999, i64 1
-  %tmp24001 = getelementptr inbounds float* %tmp24000, i64 1
-  %tmp24002 = getelementptr inbounds float* %tmp24001, i64 1
-  %tmp24003 = getelementptr inbounds float* %tmp24002, i64 1
-  %tmp24004 = getelementptr inbounds float* %tmp24003, i64 1
-  %tmp24005 = getelementptr inbounds float* %tmp24004, i64 1
-  %tmp24006 = getelementptr inbounds float* %tmp24005, i64 1
-  %tmp24007 = getelementptr inbounds float* %tmp24006, i64 1
-  %tmp24008 = getelementptr inbounds float* %tmp24007, i64 1
-  %tmp24009 = getelementptr inbounds float* %tmp24008, i64 1
-  %tmp24010 = getelementptr inbounds float* %tmp24009, i64 1
-  %tmp24011 = getelementptr inbounds float* %tmp24010, i64 1
-  %tmp24012 = getelementptr inbounds float* %tmp24011, i64 1
-  %tmp24013 = getelementptr inbounds float* %tmp24012, i64 1
-  %tmp24014 = getelementptr inbounds float* %tmp24013, i64 1
-  %tmp24015 = getelementptr inbounds float* %tmp24014, i64 1
-  %tmp24016 = getelementptr inbounds float* %tmp24015, i64 1
-  %tmp24017 = getelementptr inbounds float* %tmp24016, i64 1
-  %tmp24018 = getelementptr inbounds float* %tmp24017, i64 1
-  %tmp24019 = getelementptr inbounds float* %tmp24018, i64 1
-  %tmp24020 = getelementptr inbounds float* %tmp24019, i64 1
-  %tmp24021 = getelementptr inbounds float* %tmp24020, i64 1
-  %tmp24022 = getelementptr inbounds float* %tmp24021, i64 1
-  %tmp24023 = getelementptr inbounds float* %tmp24022, i64 1
-  %tmp24024 = getelementptr inbounds float* %tmp24023, i64 1
-  %tmp24025 = getelementptr inbounds float* %tmp24024, i64 1
-  %tmp24026 = getelementptr inbounds float* %tmp24025, i64 1
-  %tmp24027 = getelementptr inbounds float* %tmp24026, i64 1
-  %tmp24028 = getelementptr inbounds float* %tmp24027, i64 1
-  %tmp24029 = getelementptr inbounds float* %tmp24028, i64 1
-  %tmp24030 = getelementptr inbounds float* %tmp24029, i64 1
-  %tmp24031 = getelementptr inbounds float* %tmp24030, i64 1
-  %tmp24032 = getelementptr inbounds float* %tmp24031, i64 1
-  %tmp24033 = getelementptr inbounds float* %tmp24032, i64 1
-  %tmp24034 = getelementptr inbounds float* %tmp24033, i64 1
-  %tmp24035 = getelementptr inbounds float* %tmp24034, i64 1
-  %tmp24036 = getelementptr inbounds float* %tmp24035, i64 1
-  %tmp24037 = getelementptr inbounds float* %tmp24036, i64 1
-  %tmp24038 = getelementptr inbounds float* %tmp24037, i64 1
-  %tmp24039 = getelementptr inbounds float* %tmp24038, i64 1
-  %tmp24040 = getelementptr inbounds float* %tmp24039, i64 1
-  %tmp24041 = getelementptr inbounds float* %tmp24040, i64 1
-  %tmp24042 = getelementptr inbounds float* %tmp24041, i64 1
-  %tmp24043 = getelementptr inbounds float* %tmp24042, i64 1
-  %tmp24044 = getelementptr inbounds float* %tmp24043, i64 1
-  %tmp24045 = getelementptr inbounds float* %tmp24044, i64 1
-  %tmp24046 = getelementptr inbounds float* %tmp24045, i64 1
-  %tmp24047 = getelementptr inbounds float* %tmp24046, i64 1
-  %tmp24048 = getelementptr inbounds float* %tmp24047, i64 1
-  %tmp24049 = getelementptr inbounds float* %tmp24048, i64 1
-  %tmp24050 = getelementptr inbounds float* %tmp24049, i64 1
-  %tmp24051 = getelementptr inbounds float* %tmp24050, i64 1
-  %tmp24052 = getelementptr inbounds float* %tmp24051, i64 1
-  %tmp24053 = getelementptr inbounds float* %tmp24052, i64 1
-  %tmp24054 = getelementptr inbounds float* %tmp24053, i64 1
-  %tmp24055 = getelementptr inbounds float* %tmp24054, i64 1
-  %tmp24056 = getelementptr inbounds float* %tmp24055, i64 1
-  %tmp24057 = getelementptr inbounds float* %tmp24056, i64 1
-  %tmp24058 = getelementptr inbounds float* %tmp24057, i64 1
-  %tmp24059 = getelementptr inbounds float* %tmp24058, i64 1
-  %tmp24060 = getelementptr inbounds float* %tmp24059, i64 1
-  %tmp24061 = getelementptr inbounds float* %tmp24060, i64 1
-  %tmp24062 = getelementptr inbounds float* %tmp24061, i64 1
-  %tmp24063 = getelementptr inbounds float* %tmp24062, i64 1
-  %tmp24064 = getelementptr inbounds float* %tmp24063, i64 1
-  %tmp24065 = getelementptr inbounds float* %tmp24064, i64 1
-  %tmp24066 = getelementptr inbounds float* %tmp24065, i64 1
-  %tmp24067 = getelementptr inbounds float* %tmp24066, i64 1
-  %tmp24068 = getelementptr inbounds float* %tmp24067, i64 1
-  %tmp24069 = getelementptr inbounds float* %tmp24068, i64 1
-  %tmp24070 = getelementptr inbounds float* %tmp24069, i64 1
-  %tmp24071 = getelementptr inbounds float* %tmp24070, i64 1
-  %tmp24072 = getelementptr inbounds float* %tmp24071, i64 1
-  %tmp24073 = getelementptr inbounds float* %tmp24072, i64 1
-  %tmp24074 = getelementptr inbounds float* %tmp24073, i64 1
-  %tmp24075 = getelementptr inbounds float* %tmp24074, i64 1
-  %tmp24076 = getelementptr inbounds float* %tmp24075, i64 1
-  %tmp24077 = getelementptr inbounds float* %tmp24076, i64 1
-  %tmp24078 = getelementptr inbounds float* %tmp24077, i64 1
-  %tmp24079 = getelementptr inbounds float* %tmp24078, i64 1
-  %tmp24080 = getelementptr inbounds float* %tmp24079, i64 1
-  %tmp24081 = getelementptr inbounds float* %tmp24080, i64 1
-  %tmp24082 = getelementptr inbounds float* %tmp24081, i64 1
-  %tmp24083 = getelementptr inbounds float* %tmp24082, i64 1
-  %tmp24084 = getelementptr inbounds float* %tmp24083, i64 1
-  %tmp24085 = getelementptr inbounds float* %tmp24084, i64 1
-  %tmp24086 = getelementptr inbounds float* %tmp24085, i64 1
-  %tmp24087 = getelementptr inbounds float* %tmp24086, i64 1
-  %tmp24088 = getelementptr inbounds float* %tmp24087, i64 1
-  %tmp24089 = getelementptr inbounds float* %tmp24088, i64 1
-  %tmp24090 = getelementptr inbounds float* %tmp24089, i64 1
-  %tmp24091 = getelementptr inbounds float* %tmp24090, i64 1
-  %tmp24092 = getelementptr inbounds float* %tmp24091, i64 1
-  %tmp24093 = getelementptr inbounds float* %tmp24092, i64 1
-  %tmp24094 = getelementptr inbounds float* %tmp24093, i64 1
-  %tmp24095 = getelementptr inbounds float* %tmp24094, i64 1
-  %tmp24096 = getelementptr inbounds float* %tmp24095, i64 1
-  %tmp24097 = getelementptr inbounds float* %tmp24096, i64 1
-  %tmp24098 = getelementptr inbounds float* %tmp24097, i64 1
-  %tmp24099 = getelementptr inbounds float* %tmp24098, i64 1
-  %tmp24100 = getelementptr inbounds float* %tmp24099, i64 1
-  %tmp24101 = getelementptr inbounds float* %tmp24100, i64 1
-  %tmp24102 = getelementptr inbounds float* %tmp24101, i64 1
-  %tmp24103 = getelementptr inbounds float* %tmp24102, i64 1
-  %tmp24104 = getelementptr inbounds float* %tmp24103, i64 1
-  %tmp24105 = getelementptr inbounds float* %tmp24104, i64 1
-  %tmp24106 = getelementptr inbounds float* %tmp24105, i64 1
-  %tmp24107 = getelementptr inbounds float* %tmp24106, i64 1
-  %tmp24108 = getelementptr inbounds float* %tmp24107, i64 1
-  %tmp24109 = getelementptr inbounds float* %tmp24108, i64 1
-  %tmp24110 = getelementptr inbounds float* %tmp24109, i64 1
-  %tmp24111 = getelementptr inbounds float* %tmp24110, i64 1
-  %tmp24112 = getelementptr inbounds float* %tmp24111, i64 1
-  %tmp24113 = getelementptr inbounds float* %tmp24112, i64 1
-  %tmp24114 = getelementptr inbounds float* %tmp24113, i64 1
-  %tmp24115 = getelementptr inbounds float* %tmp24114, i64 1
-  %tmp24116 = getelementptr inbounds float* %tmp24115, i64 1
-  %tmp24117 = getelementptr inbounds float* %tmp24116, i64 1
-  %tmp24118 = getelementptr inbounds float* %tmp24117, i64 1
-  %tmp24119 = getelementptr inbounds float* %tmp24118, i64 1
-  %tmp24120 = getelementptr inbounds float* %tmp24119, i64 1
-  %tmp24121 = getelementptr inbounds float* %tmp24120, i64 1
-  %tmp24122 = getelementptr inbounds float* %tmp24121, i64 1
-  %tmp24123 = getelementptr inbounds float* %tmp24122, i64 1
-  %tmp24124 = getelementptr inbounds float* %tmp24123, i64 1
-  %tmp24125 = getelementptr inbounds float* %tmp24124, i64 1
-  %tmp24126 = getelementptr inbounds float* %tmp24125, i64 1
-  %tmp24127 = getelementptr inbounds float* %tmp24126, i64 1
-  %tmp24128 = getelementptr inbounds float* %tmp24127, i64 1
-  %tmp24129 = getelementptr inbounds float* %tmp24128, i64 1
-  %tmp24130 = getelementptr inbounds float* %tmp24129, i64 1
-  %tmp24131 = getelementptr inbounds float* %tmp24130, i64 1
-  %tmp24132 = getelementptr inbounds float* %tmp24131, i64 1
-  %tmp24133 = getelementptr inbounds float* %tmp24132, i64 1
-  %tmp24134 = getelementptr inbounds float* %tmp24133, i64 1
-  %tmp24135 = getelementptr inbounds float* %tmp24134, i64 1
-  %tmp24136 = getelementptr inbounds float* %tmp24135, i64 1
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-  %tmp24816 = getelementptr inbounds float* %tmp24815, i64 1
-  %tmp24817 = getelementptr inbounds float* %tmp24816, i64 1
-  %tmp24818 = getelementptr inbounds float* %tmp24817, i64 1
-  %tmp24819 = getelementptr inbounds float* %tmp24818, i64 1
-  %tmp24820 = getelementptr inbounds float* %tmp24819, i64 1
-  %tmp24821 = getelementptr inbounds float* %tmp24820, i64 1
-  %tmp24822 = getelementptr inbounds float* %tmp24821, i64 1
-  %tmp24823 = getelementptr inbounds float* %tmp24822, i64 1
-  %tmp24824 = getelementptr inbounds float* %tmp24823, i64 1
-  %tmp24825 = getelementptr inbounds float* %tmp24824, i64 1
-  %tmp24826 = getelementptr inbounds float* %tmp24825, i64 1
-  %tmp24827 = getelementptr inbounds float* %tmp24826, i64 1
-  %tmp24828 = getelementptr inbounds float* %tmp24827, i64 1
-  %tmp24829 = getelementptr inbounds float* %tmp24828, i64 1
-  %tmp24830 = getelementptr inbounds float* %tmp24829, i64 1
-  %tmp24831 = getelementptr inbounds float* %tmp24830, i64 1
-  %tmp24832 = getelementptr inbounds float* %tmp24831, i64 1
-  %tmp24833 = getelementptr inbounds float* %tmp24832, i64 1
-  %tmp24834 = getelementptr inbounds float* %tmp24833, i64 1
-  %tmp24835 = getelementptr inbounds float* %tmp24834, i64 1
-  %tmp24836 = getelementptr inbounds float* %tmp24835, i64 1
-  %tmp24837 = getelementptr inbounds float* %tmp24836, i64 1
-  %tmp24838 = getelementptr inbounds float* %tmp24837, i64 1
-  %tmp24839 = getelementptr inbounds float* %tmp24838, i64 1
-  %tmp24840 = getelementptr inbounds float* %tmp24839, i64 1
-  %tmp24841 = getelementptr inbounds float* %tmp24840, i64 1
-  %tmp24842 = getelementptr inbounds float* %tmp24841, i64 1
-  %tmp24843 = getelementptr inbounds float* %tmp24842, i64 1
-  %tmp24844 = getelementptr inbounds float* %tmp24843, i64 1
-  %tmp24845 = getelementptr inbounds float* %tmp24844, i64 1
-  %tmp24846 = getelementptr inbounds float* %tmp24845, i64 1
-  %tmp24847 = getelementptr inbounds float* %tmp24846, i64 1
-  %tmp24848 = getelementptr inbounds float* %tmp24847, i64 1
-  %tmp24849 = getelementptr inbounds float* %tmp24848, i64 1
-  %tmp24850 = getelementptr inbounds float* %tmp24849, i64 1
-  %tmp24851 = getelementptr inbounds float* %tmp24850, i64 1
-  %tmp24852 = getelementptr inbounds float* %tmp24851, i64 1
-  %tmp24853 = getelementptr inbounds float* %tmp24852, i64 1
-  %tmp24854 = getelementptr inbounds float* %tmp24853, i64 1
-  %tmp24855 = getelementptr inbounds float* %tmp24854, i64 1
-  %tmp24856 = getelementptr inbounds float* %tmp24855, i64 1
-  %tmp24857 = getelementptr inbounds float* %tmp24856, i64 1
-  %tmp24858 = getelementptr inbounds float* %tmp24857, i64 1
-  %tmp24859 = getelementptr inbounds float* %tmp24858, i64 1
-  %tmp24860 = getelementptr inbounds float* %tmp24859, i64 1
-  %tmp24861 = getelementptr inbounds float* %tmp24860, i64 1
-  %tmp24862 = getelementptr inbounds float* %tmp24861, i64 1
-  %tmp24863 = getelementptr inbounds float* %tmp24862, i64 1
-  %tmp24864 = getelementptr inbounds float* %tmp24863, i64 1
-  %tmp24865 = getelementptr inbounds float* %tmp24864, i64 1
-  %tmp24866 = getelementptr inbounds float* %tmp24865, i64 1
-  %tmp24867 = getelementptr inbounds float* %tmp24866, i64 1
-  %tmp24868 = getelementptr inbounds float* %tmp24867, i64 1
-  %tmp24869 = getelementptr inbounds float* %tmp24868, i64 1
-  %tmp24870 = getelementptr inbounds float* %tmp24869, i64 1
-  %tmp24871 = getelementptr inbounds float* %tmp24870, i64 1
-  %tmp24872 = getelementptr inbounds float* %tmp24871, i64 1
-  %tmp24873 = getelementptr inbounds float* %tmp24872, i64 1
-  %tmp24874 = getelementptr inbounds float* %tmp24873, i64 1
-  %tmp24875 = getelementptr inbounds float* %tmp24874, i64 1
-  %tmp24876 = getelementptr inbounds float* %tmp24875, i64 1
-  %tmp24877 = getelementptr inbounds float* %tmp24876, i64 1
-  %tmp24878 = getelementptr inbounds float* %tmp24877, i64 1
-  %tmp24879 = getelementptr inbounds float* %tmp24878, i64 1
-  %tmp24880 = getelementptr inbounds float* %tmp24879, i64 1
-  %tmp24881 = getelementptr inbounds float* %tmp24880, i64 1
-  %tmp24882 = getelementptr inbounds float* %tmp24881, i64 1
-  %tmp24883 = getelementptr inbounds float* %tmp24882, i64 1
-  %tmp24884 = getelementptr inbounds float* %tmp24883, i64 1
-  %tmp24885 = getelementptr inbounds float* %tmp24884, i64 1
-  %tmp24886 = getelementptr inbounds float* %tmp24885, i64 1
-  %tmp24887 = getelementptr inbounds float* %tmp24886, i64 1
-  %tmp24888 = getelementptr inbounds float* %tmp24887, i64 1
-  %tmp24889 = getelementptr inbounds float* %tmp24888, i64 1
-  %tmp24890 = getelementptr inbounds float* %tmp24889, i64 1
-  %tmp24891 = getelementptr inbounds float* %tmp24890, i64 1
-  %tmp24892 = getelementptr inbounds float* %tmp24891, i64 1
-  %tmp24893 = getelementptr inbounds float* %tmp24892, i64 1
-  %tmp24894 = getelementptr inbounds float* %tmp24893, i64 1
-  %tmp24895 = getelementptr inbounds float* %tmp24894, i64 1
-  %tmp24896 = getelementptr inbounds float* %tmp24895, i64 1
-  %tmp24897 = getelementptr inbounds float* %tmp24896, i64 1
-  %tmp24898 = getelementptr inbounds float* %tmp24897, i64 1
-  %tmp24899 = getelementptr inbounds float* %tmp24898, i64 1
-  %tmp24900 = getelementptr inbounds float* %tmp24899, i64 1
-  %tmp24901 = getelementptr inbounds float* %tmp24900, i64 1
-  %tmp24902 = getelementptr inbounds float* %tmp24901, i64 1
-  %tmp24903 = getelementptr inbounds float* %tmp24902, i64 1
-  %tmp24904 = getelementptr inbounds float* %tmp24903, i64 1
-  %tmp24905 = getelementptr inbounds float* %tmp24904, i64 1
-  %tmp24906 = getelementptr inbounds float* %tmp24905, i64 1
-  %tmp24907 = getelementptr inbounds float* %tmp24906, i64 1
-  %tmp24908 = getelementptr inbounds float* %tmp24907, i64 1
-  %tmp24909 = getelementptr inbounds float* %tmp24908, i64 1
-  %tmp24910 = getelementptr inbounds float* %tmp24909, i64 1
-  %tmp24911 = getelementptr inbounds float* %tmp24910, i64 1
-  %tmp24912 = getelementptr inbounds float* %tmp24911, i64 1
-  %tmp24913 = getelementptr inbounds float* %tmp24912, i64 1
-  %tmp24914 = getelementptr inbounds float* %tmp24913, i64 1
-  %tmp24915 = getelementptr inbounds float* %tmp24914, i64 1
-  %tmp24916 = getelementptr inbounds float* %tmp24915, i64 1
-  %tmp24917 = getelementptr inbounds float* %tmp24916, i64 1
-  %tmp24918 = getelementptr inbounds float* %tmp24917, i64 1
-  %tmp24919 = getelementptr inbounds float* %tmp24918, i64 1
-  %tmp24920 = getelementptr inbounds float* %tmp24919, i64 1
-  %tmp24921 = getelementptr inbounds float* %tmp24920, i64 1
-  %tmp24922 = getelementptr inbounds float* %tmp24921, i64 1
-  %tmp24923 = getelementptr inbounds float* %tmp24922, i64 1
-  %tmp24924 = getelementptr inbounds float* %tmp24923, i64 1
-  %tmp24925 = getelementptr inbounds float* %tmp24924, i64 1
-  %tmp24926 = getelementptr inbounds float* %tmp24925, i64 1
-  %tmp24927 = getelementptr inbounds float* %tmp24926, i64 1
-  %tmp24928 = getelementptr inbounds float* %tmp24927, i64 1
-  %tmp24929 = getelementptr inbounds float* %tmp24928, i64 1
-  %tmp24930 = getelementptr inbounds float* %tmp24929, i64 1
-  %tmp24931 = getelementptr inbounds float* %tmp24930, i64 1
-  %tmp24932 = getelementptr inbounds float* %tmp24931, i64 1
-  %tmp24933 = getelementptr inbounds float* %tmp24932, i64 1
-  %tmp24934 = getelementptr inbounds float* %tmp24933, i64 1
-  %tmp24935 = getelementptr inbounds float* %tmp24934, i64 1
-  %tmp24936 = getelementptr inbounds float* %tmp24935, i64 1
-  %tmp24937 = getelementptr inbounds float* %tmp24936, i64 1
-  %tmp24938 = getelementptr inbounds float* %tmp24937, i64 1
-  %tmp24939 = getelementptr inbounds float* %tmp24938, i64 1
-  %tmp24940 = getelementptr inbounds float* %tmp24939, i64 1
-  %tmp24941 = getelementptr inbounds float* %tmp24940, i64 1
-  %tmp24942 = getelementptr inbounds float* %tmp24941, i64 1
-  %tmp24943 = getelementptr inbounds float* %tmp24942, i64 1
-  %tmp24944 = getelementptr inbounds float* %tmp24943, i64 1
-  %tmp24945 = getelementptr inbounds float* %tmp24944, i64 1
-  %tmp24946 = getelementptr inbounds float* %tmp24945, i64 1
+  %tmp = getelementptr inbounds float, float* null, i64 1
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+  %tmp1201 = getelementptr inbounds float, float* %tmp1200, i64 1
+  %tmp1202 = getelementptr inbounds float, float* %tmp1201, i64 1
+  %tmp1203 = getelementptr inbounds float, float* %tmp1202, i64 1
+  %tmp1204 = getelementptr inbounds float, float* %tmp1203, i64 1
+  %tmp1205 = getelementptr inbounds float, float* %tmp1204, i64 1
+  %tmp1206 = getelementptr inbounds float, float* %tmp1205, i64 1
+  %tmp1207 = getelementptr inbounds float, float* %tmp1206, i64 1
+  %tmp1208 = getelementptr inbounds float, float* %tmp1207, i64 1
+  %tmp1209 = getelementptr inbounds float, float* %tmp1208, i64 1
+  %tmp1210 = getelementptr inbounds float, float* %tmp1209, i64 1
+  %tmp1211 = getelementptr inbounds float, float* %tmp1210, i64 1
+  %tmp1212 = getelementptr inbounds float, float* %tmp1211, i64 1
+  %tmp1213 = getelementptr inbounds float, float* %tmp1212, i64 1
+  %tmp1214 = getelementptr inbounds float, float* %tmp1213, i64 1
+  %tmp1215 = getelementptr inbounds float, float* %tmp1214, i64 1
+  %tmp1216 = getelementptr inbounds float, float* %tmp1215, i64 1
+  %tmp1217 = getelementptr inbounds float, float* %tmp1216, i64 1
+  %tmp1218 = getelementptr inbounds float, float* %tmp1217, i64 1
+  %tmp1219 = getelementptr inbounds float, float* %tmp1218, i64 1
+  %tmp1220 = getelementptr inbounds float, float* %tmp1219, i64 1
+  %tmp1221 = getelementptr inbounds float, float* %tmp1220, i64 1
+  %tmp1222 = getelementptr inbounds float, float* %tmp1221, i64 1
+  %tmp1223 = getelementptr inbounds float, float* %tmp1222, i64 1
+  %tmp1224 = getelementptr inbounds float, float* %tmp1223, i64 1
+  %tmp1225 = getelementptr inbounds float, float* %tmp1224, i64 1
+  %tmp1226 = getelementptr inbounds float, float* %tmp1225, i64 1
+  %tmp1227 = getelementptr inbounds float, float* %tmp1226, i64 1
+  %tmp1228 = getelementptr inbounds float, float* %tmp1227, i64 1
+  %tmp1229 = getelementptr inbounds float, float* %tmp1228, i64 1
+  %tmp1230 = getelementptr inbounds float, float* %tmp1229, i64 1
+  %tmp1231 = getelementptr inbounds float, float* %tmp1230, i64 1
+  %tmp1232 = getelementptr inbounds float, float* %tmp1231, i64 1
+  %tmp1233 = getelementptr inbounds float, float* %tmp1232, i64 1
+  %tmp1234 = getelementptr inbounds float, float* %tmp1233, i64 1
+  %tmp1235 = getelementptr inbounds float, float* %tmp1234, i64 1
+  %tmp1236 = getelementptr inbounds float, float* %tmp1235, i64 1
+  %tmp1237 = getelementptr inbounds float, float* %tmp1236, i64 1
+  %tmp1238 = getelementptr inbounds float, float* %tmp1237, i64 1
+  %tmp1239 = getelementptr inbounds float, float* %tmp1238, i64 1
+  %tmp1240 = getelementptr inbounds float, float* %tmp1239, i64 1
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+  %tmp2147 = getelementptr inbounds float, float* %tmp2146, i64 1
+  %tmp2148 = getelementptr inbounds float, float* %tmp2147, i64 1
+  %tmp2149 = getelementptr inbounds float, float* %tmp2148, i64 1
+  %tmp2150 = getelementptr inbounds float, float* %tmp2149, i64 1
+  %tmp2151 = getelementptr inbounds float, float* %tmp2150, i64 1
+  %tmp2152 = getelementptr inbounds float, float* %tmp2151, i64 1
+  %tmp2153 = getelementptr inbounds float, float* %tmp2152, i64 1
+  %tmp2154 = getelementptr inbounds float, float* %tmp2153, i64 1
+  %tmp2155 = getelementptr inbounds float, float* %tmp2154, i64 1
+  %tmp2156 = getelementptr inbounds float, float* %tmp2155, i64 1
+  %tmp2157 = getelementptr inbounds float, float* %tmp2156, i64 1
+  %tmp2158 = getelementptr inbounds float, float* %tmp2157, i64 1
+  %tmp2159 = getelementptr inbounds float, float* %tmp2158, i64 1
+  %tmp2160 = getelementptr inbounds float, float* %tmp2159, i64 1
+  %tmp2161 = getelementptr inbounds float, float* %tmp2160, i64 1
+  %tmp2162 = getelementptr inbounds float, float* %tmp2161, i64 1
+  %tmp2163 = getelementptr inbounds float, float* %tmp2162, i64 1
+  %tmp2164 = getelementptr inbounds float, float* %tmp2163, i64 1
+  %tmp2165 = getelementptr inbounds float, float* %tmp2164, i64 1
+  %tmp2166 = getelementptr inbounds float, float* %tmp2165, i64 1
+  %tmp2167 = getelementptr inbounds float, float* %tmp2166, i64 1
+  %tmp2168 = getelementptr inbounds float, float* %tmp2167, i64 1
+  %tmp2169 = getelementptr inbounds float, float* %tmp2168, i64 1
+  %tmp2170 = getelementptr inbounds float, float* %tmp2169, i64 1
+  %tmp2171 = getelementptr inbounds float, float* %tmp2170, i64 1
+  %tmp2172 = getelementptr inbounds float, float* %tmp2171, i64 1
+  %tmp2173 = getelementptr inbounds float, float* %tmp2172, i64 1
+  %tmp2174 = getelementptr inbounds float, float* %tmp2173, i64 1
+  %tmp2175 = getelementptr inbounds float, float* %tmp2174, i64 1
+  %tmp2176 = getelementptr inbounds float, float* %tmp2175, i64 1
+  %tmp2177 = getelementptr inbounds float, float* %tmp2176, i64 1
+  %tmp2178 = getelementptr inbounds float, float* %tmp2177, i64 1
+  %tmp2179 = getelementptr inbounds float, float* %tmp2178, i64 1
+  %tmp2180 = getelementptr inbounds float, float* %tmp2179, i64 1
+  %tmp2181 = getelementptr inbounds float, float* %tmp2180, i64 1
+  %tmp2182 = getelementptr inbounds float, float* %tmp2181, i64 1
+  %tmp2183 = getelementptr inbounds float, float* %tmp2182, i64 1
+  %tmp2184 = getelementptr inbounds float, float* %tmp2183, i64 1
+  %tmp2185 = getelementptr inbounds float, float* %tmp2184, i64 1
+  %tmp2186 = getelementptr inbounds float, float* %tmp2185, i64 1
+  %tmp2187 = getelementptr inbounds float, float* %tmp2186, i64 1
+  %tmp2188 = getelementptr inbounds float, float* %tmp2187, i64 1
+  %tmp2189 = getelementptr inbounds float, float* %tmp2188, i64 1
+  %tmp2190 = getelementptr inbounds float, float* %tmp2189, i64 1
+  %tmp2191 = getelementptr inbounds float, float* %tmp2190, i64 1
+  %tmp2192 = getelementptr inbounds float, float* %tmp2191, i64 1
+  %tmp2193 = getelementptr inbounds float, float* %tmp2192, i64 1
+  %tmp2194 = getelementptr inbounds float, float* %tmp2193, i64 1
+  %tmp2195 = getelementptr inbounds float, float* %tmp2194, i64 1
+  %tmp2196 = getelementptr inbounds float, float* %tmp2195, i64 1
+  %tmp2197 = getelementptr inbounds float, float* %tmp2196, i64 1
+  %tmp2198 = getelementptr inbounds float, float* %tmp2197, i64 1
+  %tmp2199 = getelementptr inbounds float, float* %tmp2198, i64 1
+  %tmp2200 = getelementptr inbounds float, float* %tmp2199, i64 1
+  %tmp2201 = getelementptr inbounds float, float* %tmp2200, i64 1
+  %tmp2202 = getelementptr inbounds float, float* %tmp2201, i64 1
+  %tmp2203 = getelementptr inbounds float, float* %tmp2202, i64 1
+  %tmp2204 = getelementptr inbounds float, float* %tmp2203, i64 1
+  %tmp2205 = getelementptr inbounds float, float* %tmp2204, i64 1
+  %tmp2206 = getelementptr inbounds float, float* %tmp2205, i64 1
+  %tmp2207 = getelementptr inbounds float, float* %tmp2206, i64 1
+  %tmp2208 = getelementptr inbounds float, float* %tmp2207, i64 1
+  %tmp2209 = getelementptr inbounds float, float* %tmp2208, i64 1
+  %tmp2210 = getelementptr inbounds float, float* %tmp2209, i64 1
+  %tmp2211 = getelementptr inbounds float, float* %tmp2210, i64 1
+  %tmp2212 = getelementptr inbounds float, float* %tmp2211, i64 1
+  %tmp2213 = getelementptr inbounds float, float* %tmp2212, i64 1
+  %tmp2214 = getelementptr inbounds float, float* %tmp2213, i64 1
+  %tmp2215 = getelementptr inbounds float, float* %tmp2214, i64 1
+  %tmp2216 = getelementptr inbounds float, float* %tmp2215, i64 1
+  %tmp2217 = getelementptr inbounds float, float* %tmp2216, i64 1
+  %tmp2218 = getelementptr inbounds float, float* %tmp2217, i64 1
+  %tmp2219 = getelementptr inbounds float, float* %tmp2218, i64 1
+  %tmp2220 = getelementptr inbounds float, float* %tmp2219, i64 1
+  %tmp2221 = getelementptr inbounds float, float* %tmp2220, i64 1
+  %tmp2222 = getelementptr inbounds float, float* %tmp2221, i64 1
+  %tmp2223 = getelementptr inbounds float, float* %tmp2222, i64 1
+  %tmp2224 = getelementptr inbounds float, float* %tmp2223, i64 1
+  %tmp2225 = getelementptr inbounds float, float* %tmp2224, i64 1
+  %tmp2226 = getelementptr inbounds float, float* %tmp2225, i64 1
+  %tmp2227 = getelementptr inbounds float, float* %tmp2226, i64 1
+  %tmp2228 = getelementptr inbounds float, float* %tmp2227, i64 1
+  %tmp2229 = getelementptr inbounds float, float* %tmp2228, i64 1
+  %tmp2230 = getelementptr inbounds float, float* %tmp2229, i64 1
+  %tmp2231 = getelementptr inbounds float, float* %tmp2230, i64 1
+  %tmp2232 = getelementptr inbounds float, float* %tmp2231, i64 1
+  %tmp2233 = getelementptr inbounds float, float* %tmp2232, i64 1
+  %tmp2234 = getelementptr inbounds float, float* %tmp2233, i64 1
+  %tmp2235 = getelementptr inbounds float, float* %tmp2234, i64 1
+  %tmp2236 = getelementptr inbounds float, float* %tmp2235, i64 1
+  %tmp2237 = getelementptr inbounds float, float* %tmp2236, i64 1
+  %tmp2238 = getelementptr inbounds float, float* %tmp2237, i64 1
+  %tmp2239 = getelementptr inbounds float, float* %tmp2238, i64 1
+  %tmp2240 = getelementptr inbounds float, float* %tmp2239, i64 1
+  %tmp2241 = getelementptr inbounds float, float* %tmp2240, i64 1
+  %tmp2242 = getelementptr inbounds float, float* %tmp2241, i64 1
+  %tmp2243 = getelementptr inbounds float, float* %tmp2242, i64 1
+  %tmp2244 = getelementptr inbounds float, float* %tmp2243, i64 1
+  %tmp2245 = getelementptr inbounds float, float* %tmp2244, i64 1
+  %tmp2246 = getelementptr inbounds float, float* %tmp2245, i64 1
+  %tmp2247 = getelementptr inbounds float, float* %tmp2246, i64 1
+  %tmp2248 = getelementptr inbounds float, float* %tmp2247, i64 1
+  %tmp2249 = getelementptr inbounds float, float* %tmp2248, i64 1
+  %tmp2250 = getelementptr inbounds float, float* %tmp2249, i64 1
+  %tmp2251 = getelementptr inbounds float, float* %tmp2250, i64 1
+  %tmp2252 = getelementptr inbounds float, float* %tmp2251, i64 1
+  %tmp2253 = getelementptr inbounds float, float* %tmp2252, i64 1
+  %tmp2254 = getelementptr inbounds float, float* %tmp2253, i64 1
+  %tmp2255 = getelementptr inbounds float, float* %tmp2254, i64 1
+  %tmp2256 = getelementptr inbounds float, float* %tmp2255, i64 1
+  %tmp2257 = getelementptr inbounds float, float* %tmp2256, i64 1
+  %tmp2258 = getelementptr inbounds float, float* %tmp2257, i64 1
+  %tmp2259 = getelementptr inbounds float, float* %tmp2258, i64 1
+  %tmp2260 = getelementptr inbounds float, float* %tmp2259, i64 1
+  %tmp2261 = getelementptr inbounds float, float* %tmp2260, i64 1
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+  %tmp2264 = getelementptr inbounds float, float* %tmp2263, i64 1
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+  %tmp2269 = getelementptr inbounds float, float* %tmp2268, i64 1
+  %tmp2270 = getelementptr inbounds float, float* %tmp2269, i64 1
+  %tmp2271 = getelementptr inbounds float, float* %tmp2270, i64 1
+  %tmp2272 = getelementptr inbounds float, float* %tmp2271, i64 1
+  %tmp2273 = getelementptr inbounds float, float* %tmp2272, i64 1
+  %tmp2274 = getelementptr inbounds float, float* %tmp2273, i64 1
+  %tmp2275 = getelementptr inbounds float, float* %tmp2274, i64 1
+  %tmp2276 = getelementptr inbounds float, float* %tmp2275, i64 1
+  %tmp2277 = getelementptr inbounds float, float* %tmp2276, i64 1
+  %tmp2278 = getelementptr inbounds float, float* %tmp2277, i64 1
+  %tmp2279 = getelementptr inbounds float, float* %tmp2278, i64 1
+  %tmp2280 = getelementptr inbounds float, float* %tmp2279, i64 1
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+  %tmp2282 = getelementptr inbounds float, float* %tmp2281, i64 1
+  %tmp2283 = getelementptr inbounds float, float* %tmp2282, i64 1
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+  %tmp2289 = getelementptr inbounds float, float* %tmp2288, i64 1
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+  %tmp2296 = getelementptr inbounds float, float* %tmp2295, i64 1
+  %tmp2297 = getelementptr inbounds float, float* %tmp2296, i64 1
+  %tmp2298 = getelementptr inbounds float, float* %tmp2297, i64 1
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+  %tmp2321 = getelementptr inbounds float, float* %tmp2320, i64 1
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+  %tmp2323 = getelementptr inbounds float, float* %tmp2322, i64 1
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+  %tmp2366 = getelementptr inbounds float, float* %tmp2365, i64 1
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+  %tmp2378 = getelementptr inbounds float, float* %tmp2377, i64 1
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+  %tmp2380 = getelementptr inbounds float, float* %tmp2379, i64 1
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+  %tmp2455 = getelementptr inbounds float, float* %tmp2454, i64 1
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+  %tmp2458 = getelementptr inbounds float, float* %tmp2457, i64 1
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+  %tmp2773 = getelementptr inbounds float, float* %tmp2772, i64 1
+  %tmp2774 = getelementptr inbounds float, float* %tmp2773, i64 1
+  %tmp2775 = getelementptr inbounds float, float* %tmp2774, i64 1
+  %tmp2776 = getelementptr inbounds float, float* %tmp2775, i64 1
+  %tmp2777 = getelementptr inbounds float, float* %tmp2776, i64 1
+  %tmp2778 = getelementptr inbounds float, float* %tmp2777, i64 1
+  %tmp2779 = getelementptr inbounds float, float* %tmp2778, i64 1
+  %tmp2780 = getelementptr inbounds float, float* %tmp2779, i64 1
+  %tmp2781 = getelementptr inbounds float, float* %tmp2780, i64 1
+  %tmp2782 = getelementptr inbounds float, float* %tmp2781, i64 1
+  %tmp2783 = getelementptr inbounds float, float* %tmp2782, i64 1
+  %tmp2784 = getelementptr inbounds float, float* %tmp2783, i64 1
+  %tmp2785 = getelementptr inbounds float, float* %tmp2784, i64 1
+  %tmp2786 = getelementptr inbounds float, float* %tmp2785, i64 1
+  %tmp2787 = getelementptr inbounds float, float* %tmp2786, i64 1
+  %tmp2788 = getelementptr inbounds float, float* %tmp2787, i64 1
+  %tmp2789 = getelementptr inbounds float, float* %tmp2788, i64 1
+  %tmp2790 = getelementptr inbounds float, float* %tmp2789, i64 1
+  %tmp2791 = getelementptr inbounds float, float* %tmp2790, i64 1
+  %tmp2792 = getelementptr inbounds float, float* %tmp2791, i64 1
+  %tmp2793 = getelementptr inbounds float, float* %tmp2792, i64 1
+  %tmp2794 = getelementptr inbounds float, float* %tmp2793, i64 1
+  %tmp2795 = getelementptr inbounds float, float* %tmp2794, i64 1
+  %tmp2796 = getelementptr inbounds float, float* %tmp2795, i64 1
+  %tmp2797 = getelementptr inbounds float, float* %tmp2796, i64 1
+  %tmp2798 = getelementptr inbounds float, float* %tmp2797, i64 1
+  %tmp2799 = getelementptr inbounds float, float* %tmp2798, i64 1
+  %tmp2800 = getelementptr inbounds float, float* %tmp2799, i64 1
+  %tmp2801 = getelementptr inbounds float, float* %tmp2800, i64 1
+  %tmp2802 = getelementptr inbounds float, float* %tmp2801, i64 1
+  %tmp2803 = getelementptr inbounds float, float* %tmp2802, i64 1
+  %tmp2804 = getelementptr inbounds float, float* %tmp2803, i64 1
+  %tmp2805 = getelementptr inbounds float, float* %tmp2804, i64 1
+  %tmp2806 = getelementptr inbounds float, float* %tmp2805, i64 1
+  %tmp2807 = getelementptr inbounds float, float* %tmp2806, i64 1
+  %tmp2808 = getelementptr inbounds float, float* %tmp2807, i64 1
+  %tmp2809 = getelementptr inbounds float, float* %tmp2808, i64 1
+  %tmp2810 = getelementptr inbounds float, float* %tmp2809, i64 1
+  %tmp2811 = getelementptr inbounds float, float* %tmp2810, i64 1
+  %tmp2812 = getelementptr inbounds float, float* %tmp2811, i64 1
+  %tmp2813 = getelementptr inbounds float, float* %tmp2812, i64 1
+  %tmp2814 = getelementptr inbounds float, float* %tmp2813, i64 1
+  %tmp2815 = getelementptr inbounds float, float* %tmp2814, i64 1
+  %tmp2816 = getelementptr inbounds float, float* %tmp2815, i64 1
+  %tmp2817 = getelementptr inbounds float, float* %tmp2816, i64 1
+  %tmp2818 = getelementptr inbounds float, float* %tmp2817, i64 1
+  %tmp2819 = getelementptr inbounds float, float* %tmp2818, i64 1
+  %tmp2820 = getelementptr inbounds float, float* %tmp2819, i64 1
+  %tmp2821 = getelementptr inbounds float, float* %tmp2820, i64 1
+  %tmp2822 = getelementptr inbounds float, float* %tmp2821, i64 1
+  %tmp2823 = getelementptr inbounds float, float* %tmp2822, i64 1
+  %tmp2824 = getelementptr inbounds float, float* %tmp2823, i64 1
+  %tmp2825 = getelementptr inbounds float, float* %tmp2824, i64 1
+  %tmp2826 = getelementptr inbounds float, float* %tmp2825, i64 1
+  %tmp2827 = getelementptr inbounds float, float* %tmp2826, i64 1
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+  %tmp2829 = getelementptr inbounds float, float* %tmp2828, i64 1
+  %tmp2830 = getelementptr inbounds float, float* %tmp2829, i64 1
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+  %tmp2832 = getelementptr inbounds float, float* %tmp2831, i64 1
+  %tmp2833 = getelementptr inbounds float, float* %tmp2832, i64 1
+  %tmp2834 = getelementptr inbounds float, float* %tmp2833, i64 1
+  %tmp2835 = getelementptr inbounds float, float* %tmp2834, i64 1
+  %tmp2836 = getelementptr inbounds float, float* %tmp2835, i64 1
+  %tmp2837 = getelementptr inbounds float, float* %tmp2836, i64 1
+  %tmp2838 = getelementptr inbounds float, float* %tmp2837, i64 1
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+  %tmp2841 = getelementptr inbounds float, float* %tmp2840, i64 1
+  %tmp2842 = getelementptr inbounds float, float* %tmp2841, i64 1
+  %tmp2843 = getelementptr inbounds float, float* %tmp2842, i64 1
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+  %tmp2845 = getelementptr inbounds float, float* %tmp2844, i64 1
+  %tmp2846 = getelementptr inbounds float, float* %tmp2845, i64 1
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+  %tmp2849 = getelementptr inbounds float, float* %tmp2848, i64 1
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+  %tmp2859 = getelementptr inbounds float, float* %tmp2858, i64 1
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+  %tmp2975 = getelementptr inbounds float, float* %tmp2974, i64 1
+  %tmp2976 = getelementptr inbounds float, float* %tmp2975, i64 1
+  %tmp2977 = getelementptr inbounds float, float* %tmp2976, i64 1
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+  %tmp2999 = getelementptr inbounds float, float* %tmp2998, i64 1
+  %tmp3000 = getelementptr inbounds float, float* %tmp2999, i64 1
+  %tmp3001 = getelementptr inbounds float, float* %tmp3000, i64 1
+  %tmp3002 = getelementptr inbounds float, float* %tmp3001, i64 1
+  %tmp3003 = getelementptr inbounds float, float* %tmp3002, i64 1
+  %tmp3004 = getelementptr inbounds float, float* %tmp3003, i64 1
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+  %tmp3006 = getelementptr inbounds float, float* %tmp3005, i64 1
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+  %tmp3018 = getelementptr inbounds float, float* %tmp3017, i64 1
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+  %tmp3032 = getelementptr inbounds float, float* %tmp3031, i64 1
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+  %tmp3077 = getelementptr inbounds float, float* %tmp3076, i64 1
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+  %tmp10600 = getelementptr inbounds float, float* %tmp10599, i64 1
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+  %tmp10612 = getelementptr inbounds float, float* %tmp10611, i64 1
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+  %tmp10615 = getelementptr inbounds float, float* %tmp10614, i64 1
+  %tmp10616 = getelementptr inbounds float, float* %tmp10615, i64 1
+  %tmp10617 = getelementptr inbounds float, float* %tmp10616, i64 1
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+  %tmp10620 = getelementptr inbounds float, float* %tmp10619, i64 1
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+  %tmp10625 = getelementptr inbounds float, float* %tmp10624, i64 1
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+  %tmp10630 = getelementptr inbounds float, float* %tmp10629, i64 1
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+  %tmp12789 = getelementptr inbounds float, float* %tmp12788, i64 1
+  %tmp12790 = getelementptr inbounds float, float* %tmp12789, i64 1
+  %tmp12791 = getelementptr inbounds float, float* %tmp12790, i64 1
+  %tmp12792 = getelementptr inbounds float, float* %tmp12791, i64 1
+  %tmp12793 = getelementptr inbounds float, float* %tmp12792, i64 1
+  %tmp12794 = getelementptr inbounds float, float* %tmp12793, i64 1
+  %tmp12795 = getelementptr inbounds float, float* %tmp12794, i64 1
+  %tmp12796 = getelementptr inbounds float, float* %tmp12795, i64 1
+  %tmp12797 = getelementptr inbounds float, float* %tmp12796, i64 1
+  %tmp12798 = getelementptr inbounds float, float* %tmp12797, i64 1
+  %tmp12799 = getelementptr inbounds float, float* %tmp12798, i64 1
+  %tmp12800 = getelementptr inbounds float, float* %tmp12799, i64 1
+  %tmp12801 = getelementptr inbounds float, float* %tmp12800, i64 1
+  %tmp12802 = getelementptr inbounds float, float* %tmp12801, i64 1
+  %tmp12803 = getelementptr inbounds float, float* %tmp12802, i64 1
+  %tmp12804 = getelementptr inbounds float, float* %tmp12803, i64 1
+  %tmp12805 = getelementptr inbounds float, float* %tmp12804, i64 1
+  %tmp12806 = getelementptr inbounds float, float* %tmp12805, i64 1
+  %tmp12807 = getelementptr inbounds float, float* %tmp12806, i64 1
+  %tmp12808 = getelementptr inbounds float, float* %tmp12807, i64 1
+  %tmp12809 = getelementptr inbounds float, float* %tmp12808, i64 1
+  %tmp12810 = getelementptr inbounds float, float* %tmp12809, i64 1
+  %tmp12811 = getelementptr inbounds float, float* %tmp12810, i64 1
+  %tmp12812 = getelementptr inbounds float, float* %tmp12811, i64 1
+  %tmp12813 = getelementptr inbounds float, float* %tmp12812, i64 1
+  %tmp12814 = getelementptr inbounds float, float* %tmp12813, i64 1
+  %tmp12815 = getelementptr inbounds float, float* %tmp12814, i64 1
+  %tmp12816 = getelementptr inbounds float, float* %tmp12815, i64 1
+  %tmp12817 = getelementptr inbounds float, float* %tmp12816, i64 1
+  %tmp12818 = getelementptr inbounds float, float* %tmp12817, i64 1
+  %tmp12819 = getelementptr inbounds float, float* %tmp12818, i64 1
+  %tmp12820 = getelementptr inbounds float, float* %tmp12819, i64 1
+  %tmp12821 = getelementptr inbounds float, float* %tmp12820, i64 1
+  %tmp12822 = getelementptr inbounds float, float* %tmp12821, i64 1
+  %tmp12823 = getelementptr inbounds float, float* %tmp12822, i64 1
+  %tmp12824 = getelementptr inbounds float, float* %tmp12823, i64 1
+  %tmp12825 = getelementptr inbounds float, float* %tmp12824, i64 1
+  %tmp12826 = getelementptr inbounds float, float* %tmp12825, i64 1
+  %tmp12827 = getelementptr inbounds float, float* %tmp12826, i64 1
+  %tmp12828 = getelementptr inbounds float, float* %tmp12827, i64 1
+  %tmp12829 = getelementptr inbounds float, float* %tmp12828, i64 1
+  %tmp12830 = getelementptr inbounds float, float* %tmp12829, i64 1
+  %tmp12831 = getelementptr inbounds float, float* %tmp12830, i64 1
+  %tmp12832 = getelementptr inbounds float, float* %tmp12831, i64 1
+  %tmp12833 = getelementptr inbounds float, float* %tmp12832, i64 1
+  %tmp12834 = getelementptr inbounds float, float* %tmp12833, i64 1
+  %tmp12835 = getelementptr inbounds float, float* %tmp12834, i64 1
+  %tmp12836 = getelementptr inbounds float, float* %tmp12835, i64 1
+  %tmp12837 = getelementptr inbounds float, float* %tmp12836, i64 1
+  %tmp12838 = getelementptr inbounds float, float* %tmp12837, i64 1
+  %tmp12839 = getelementptr inbounds float, float* %tmp12838, i64 1
+  %tmp12840 = getelementptr inbounds float, float* %tmp12839, i64 1
+  %tmp12841 = getelementptr inbounds float, float* %tmp12840, i64 1
+  %tmp12842 = getelementptr inbounds float, float* %tmp12841, i64 1
+  %tmp12843 = getelementptr inbounds float, float* %tmp12842, i64 1
+  %tmp12844 = getelementptr inbounds float, float* %tmp12843, i64 1
+  %tmp12845 = getelementptr inbounds float, float* %tmp12844, i64 1
+  %tmp12846 = getelementptr inbounds float, float* %tmp12845, i64 1
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+  %tmp12852 = getelementptr inbounds float, float* %tmp12851, i64 1
+  %tmp12853 = getelementptr inbounds float, float* %tmp12852, i64 1
+  %tmp12854 = getelementptr inbounds float, float* %tmp12853, i64 1
+  %tmp12855 = getelementptr inbounds float, float* %tmp12854, i64 1
+  %tmp12856 = getelementptr inbounds float, float* %tmp12855, i64 1
+  %tmp12857 = getelementptr inbounds float, float* %tmp12856, i64 1
+  %tmp12858 = getelementptr inbounds float, float* %tmp12857, i64 1
+  %tmp12859 = getelementptr inbounds float, float* %tmp12858, i64 1
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+  %tmp12861 = getelementptr inbounds float, float* %tmp12860, i64 1
+  %tmp12862 = getelementptr inbounds float, float* %tmp12861, i64 1
+  %tmp12863 = getelementptr inbounds float, float* %tmp12862, i64 1
+  %tmp12864 = getelementptr inbounds float, float* %tmp12863, i64 1
+  %tmp12865 = getelementptr inbounds float, float* %tmp12864, i64 1
+  %tmp12866 = getelementptr inbounds float, float* %tmp12865, i64 1
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+  %tmp12869 = getelementptr inbounds float, float* %tmp12868, i64 1
+  %tmp12870 = getelementptr inbounds float, float* %tmp12869, i64 1
+  %tmp12871 = getelementptr inbounds float, float* %tmp12870, i64 1
+  %tmp12872 = getelementptr inbounds float, float* %tmp12871, i64 1
+  %tmp12873 = getelementptr inbounds float, float* %tmp12872, i64 1
+  %tmp12874 = getelementptr inbounds float, float* %tmp12873, i64 1
+  %tmp12875 = getelementptr inbounds float, float* %tmp12874, i64 1
+  %tmp12876 = getelementptr inbounds float, float* %tmp12875, i64 1
+  %tmp12877 = getelementptr inbounds float, float* %tmp12876, i64 1
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+  %tmp12881 = getelementptr inbounds float, float* %tmp12880, i64 1
+  %tmp12882 = getelementptr inbounds float, float* %tmp12881, i64 1
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+  %tmp12884 = getelementptr inbounds float, float* %tmp12883, i64 1
+  %tmp12885 = getelementptr inbounds float, float* %tmp12884, i64 1
+  %tmp12886 = getelementptr inbounds float, float* %tmp12885, i64 1
+  %tmp12887 = getelementptr inbounds float, float* %tmp12886, i64 1
+  %tmp12888 = getelementptr inbounds float, float* %tmp12887, i64 1
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+  %tmp12892 = getelementptr inbounds float, float* %tmp12891, i64 1
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+  %tmp12896 = getelementptr inbounds float, float* %tmp12895, i64 1
+  %tmp12897 = getelementptr inbounds float, float* %tmp12896, i64 1
+  %tmp12898 = getelementptr inbounds float, float* %tmp12897, i64 1
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+  %tmp12902 = getelementptr inbounds float, float* %tmp12901, i64 1
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+  %tmp13415 = getelementptr inbounds float, float* %tmp13414, i64 1
+  %tmp13416 = getelementptr inbounds float, float* %tmp13415, i64 1
+  %tmp13417 = getelementptr inbounds float, float* %tmp13416, i64 1
+  %tmp13418 = getelementptr inbounds float, float* %tmp13417, i64 1
+  %tmp13419 = getelementptr inbounds float, float* %tmp13418, i64 1
+  %tmp13420 = getelementptr inbounds float, float* %tmp13419, i64 1
+  %tmp13421 = getelementptr inbounds float, float* %tmp13420, i64 1
+  %tmp13422 = getelementptr inbounds float, float* %tmp13421, i64 1
+  %tmp13423 = getelementptr inbounds float, float* %tmp13422, i64 1
+  %tmp13424 = getelementptr inbounds float, float* %tmp13423, i64 1
+  %tmp13425 = getelementptr inbounds float, float* %tmp13424, i64 1
+  %tmp13426 = getelementptr inbounds float, float* %tmp13425, i64 1
+  %tmp13427 = getelementptr inbounds float, float* %tmp13426, i64 1
+  %tmp13428 = getelementptr inbounds float, float* %tmp13427, i64 1
+  %tmp13429 = getelementptr inbounds float, float* %tmp13428, i64 1
+  %tmp13430 = getelementptr inbounds float, float* %tmp13429, i64 1
+  %tmp13431 = getelementptr inbounds float, float* %tmp13430, i64 1
+  %tmp13432 = getelementptr inbounds float, float* %tmp13431, i64 1
+  %tmp13433 = getelementptr inbounds float, float* %tmp13432, i64 1
+  %tmp13434 = getelementptr inbounds float, float* %tmp13433, i64 1
+  %tmp13435 = getelementptr inbounds float, float* %tmp13434, i64 1
+  %tmp13436 = getelementptr inbounds float, float* %tmp13435, i64 1
+  %tmp13437 = getelementptr inbounds float, float* %tmp13436, i64 1
+  %tmp13438 = getelementptr inbounds float, float* %tmp13437, i64 1
+  %tmp13439 = getelementptr inbounds float, float* %tmp13438, i64 1
+  %tmp13440 = getelementptr inbounds float, float* %tmp13439, i64 1
+  %tmp13441 = getelementptr inbounds float, float* %tmp13440, i64 1
+  %tmp13442 = getelementptr inbounds float, float* %tmp13441, i64 1
+  %tmp13443 = getelementptr inbounds float, float* %tmp13442, i64 1
+  %tmp13444 = getelementptr inbounds float, float* %tmp13443, i64 1
+  %tmp13445 = getelementptr inbounds float, float* %tmp13444, i64 1
+  %tmp13446 = getelementptr inbounds float, float* %tmp13445, i64 1
+  %tmp13447 = getelementptr inbounds float, float* %tmp13446, i64 1
+  %tmp13448 = getelementptr inbounds float, float* %tmp13447, i64 1
+  %tmp13449 = getelementptr inbounds float, float* %tmp13448, i64 1
+  %tmp13450 = getelementptr inbounds float, float* %tmp13449, i64 1
+  %tmp13451 = getelementptr inbounds float, float* %tmp13450, i64 1
+  %tmp13452 = getelementptr inbounds float, float* %tmp13451, i64 1
+  %tmp13453 = getelementptr inbounds float, float* %tmp13452, i64 1
+  %tmp13454 = getelementptr inbounds float, float* %tmp13453, i64 1
+  %tmp13455 = getelementptr inbounds float, float* %tmp13454, i64 1
+  %tmp13456 = getelementptr inbounds float, float* %tmp13455, i64 1
+  %tmp13457 = getelementptr inbounds float, float* %tmp13456, i64 1
+  %tmp13458 = getelementptr inbounds float, float* %tmp13457, i64 1
+  %tmp13459 = getelementptr inbounds float, float* %tmp13458, i64 1
+  %tmp13460 = getelementptr inbounds float, float* %tmp13459, i64 1
+  %tmp13461 = getelementptr inbounds float, float* %tmp13460, i64 1
+  %tmp13462 = getelementptr inbounds float, float* %tmp13461, i64 1
+  %tmp13463 = getelementptr inbounds float, float* %tmp13462, i64 1
+  %tmp13464 = getelementptr inbounds float, float* %tmp13463, i64 1
+  %tmp13465 = getelementptr inbounds float, float* %tmp13464, i64 1
+  %tmp13466 = getelementptr inbounds float, float* %tmp13465, i64 1
+  %tmp13467 = getelementptr inbounds float, float* %tmp13466, i64 1
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+  %tmp13469 = getelementptr inbounds float, float* %tmp13468, i64 1
+  %tmp13470 = getelementptr inbounds float, float* %tmp13469, i64 1
+  %tmp13471 = getelementptr inbounds float, float* %tmp13470, i64 1
+  %tmp13472 = getelementptr inbounds float, float* %tmp13471, i64 1
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+  %tmp13475 = getelementptr inbounds float, float* %tmp13474, i64 1
+  %tmp13476 = getelementptr inbounds float, float* %tmp13475, i64 1
+  %tmp13477 = getelementptr inbounds float, float* %tmp13476, i64 1
+  %tmp13478 = getelementptr inbounds float, float* %tmp13477, i64 1
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+  %tmp13480 = getelementptr inbounds float, float* %tmp13479, i64 1
+  %tmp13481 = getelementptr inbounds float, float* %tmp13480, i64 1
+  %tmp13482 = getelementptr inbounds float, float* %tmp13481, i64 1
+  %tmp13483 = getelementptr inbounds float, float* %tmp13482, i64 1
+  %tmp13484 = getelementptr inbounds float, float* %tmp13483, i64 1
+  %tmp13485 = getelementptr inbounds float, float* %tmp13484, i64 1
+  %tmp13486 = getelementptr inbounds float, float* %tmp13485, i64 1
+  %tmp13487 = getelementptr inbounds float, float* %tmp13486, i64 1
+  %tmp13488 = getelementptr inbounds float, float* %tmp13487, i64 1
+  %tmp13489 = getelementptr inbounds float, float* %tmp13488, i64 1
+  %tmp13490 = getelementptr inbounds float, float* %tmp13489, i64 1
+  %tmp13491 = getelementptr inbounds float, float* %tmp13490, i64 1
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+  %tmp13494 = getelementptr inbounds float, float* %tmp13493, i64 1
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+  %tmp13496 = getelementptr inbounds float, float* %tmp13495, i64 1
+  %tmp13497 = getelementptr inbounds float, float* %tmp13496, i64 1
+  %tmp13498 = getelementptr inbounds float, float* %tmp13497, i64 1
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+  %tmp13500 = getelementptr inbounds float, float* %tmp13499, i64 1
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+  %tmp13502 = getelementptr inbounds float, float* %tmp13501, i64 1
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+  %tmp13526 = getelementptr inbounds float, float* %tmp13525, i64 1
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+  %tmp13718 = getelementptr inbounds float, float* %tmp13717, i64 1
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+  %tmp13720 = getelementptr inbounds float, float* %tmp13719, i64 1
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+  %tmp13725 = getelementptr inbounds float, float* %tmp13724, i64 1
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+  %tmp17797 = getelementptr inbounds float, float* %tmp17796, i64 1
+  %tmp17798 = getelementptr inbounds float, float* %tmp17797, i64 1
+  %tmp17799 = getelementptr inbounds float, float* %tmp17798, i64 1
+  %tmp17800 = getelementptr inbounds float, float* %tmp17799, i64 1
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+  %tmp17802 = getelementptr inbounds float, float* %tmp17801, i64 1
+  %tmp17803 = getelementptr inbounds float, float* %tmp17802, i64 1
+  %tmp17804 = getelementptr inbounds float, float* %tmp17803, i64 1
+  %tmp17805 = getelementptr inbounds float, float* %tmp17804, i64 1
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+  %tmp17810 = getelementptr inbounds float, float* %tmp17809, i64 1
+  %tmp17811 = getelementptr inbounds float, float* %tmp17810, i64 1
+  %tmp17812 = getelementptr inbounds float, float* %tmp17811, i64 1
+  %tmp17813 = getelementptr inbounds float, float* %tmp17812, i64 1
+  %tmp17814 = getelementptr inbounds float, float* %tmp17813, i64 1
+  %tmp17815 = getelementptr inbounds float, float* %tmp17814, i64 1
+  %tmp17816 = getelementptr inbounds float, float* %tmp17815, i64 1
+  %tmp17817 = getelementptr inbounds float, float* %tmp17816, i64 1
+  %tmp17818 = getelementptr inbounds float, float* %tmp17817, i64 1
+  %tmp17819 = getelementptr inbounds float, float* %tmp17818, i64 1
+  %tmp17820 = getelementptr inbounds float, float* %tmp17819, i64 1
+  %tmp17821 = getelementptr inbounds float, float* %tmp17820, i64 1
+  %tmp17822 = getelementptr inbounds float, float* %tmp17821, i64 1
+  %tmp17823 = getelementptr inbounds float, float* %tmp17822, i64 1
+  %tmp17824 = getelementptr inbounds float, float* %tmp17823, i64 1
+  %tmp17825 = getelementptr inbounds float, float* %tmp17824, i64 1
+  %tmp17826 = getelementptr inbounds float, float* %tmp17825, i64 1
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+  %tmp17828 = getelementptr inbounds float, float* %tmp17827, i64 1
+  %tmp17829 = getelementptr inbounds float, float* %tmp17828, i64 1
+  %tmp17830 = getelementptr inbounds float, float* %tmp17829, i64 1
+  %tmp17831 = getelementptr inbounds float, float* %tmp17830, i64 1
+  %tmp17832 = getelementptr inbounds float, float* %tmp17831, i64 1
+  %tmp17833 = getelementptr inbounds float, float* %tmp17832, i64 1
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+  %tmp17837 = getelementptr inbounds float, float* %tmp17836, i64 1
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+  %tmp20925 = getelementptr inbounds float, float* %tmp20924, i64 1
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+  %tmp20927 = getelementptr inbounds float, float* %tmp20926, i64 1
+  %tmp20928 = getelementptr inbounds float, float* %tmp20927, i64 1
+  %tmp20929 = getelementptr inbounds float, float* %tmp20928, i64 1
+  %tmp20930 = getelementptr inbounds float, float* %tmp20929, i64 1
+  %tmp20931 = getelementptr inbounds float, float* %tmp20930, i64 1
+  %tmp20932 = getelementptr inbounds float, float* %tmp20931, i64 1
+  %tmp20933 = getelementptr inbounds float, float* %tmp20932, i64 1
+  %tmp20934 = getelementptr inbounds float, float* %tmp20933, i64 1
+  %tmp20935 = getelementptr inbounds float, float* %tmp20934, i64 1
+  %tmp20936 = getelementptr inbounds float, float* %tmp20935, i64 1
+  %tmp20937 = getelementptr inbounds float, float* %tmp20936, i64 1
+  %tmp20938 = getelementptr inbounds float, float* %tmp20937, i64 1
+  %tmp20939 = getelementptr inbounds float, float* %tmp20938, i64 1
+  %tmp20940 = getelementptr inbounds float, float* %tmp20939, i64 1
+  %tmp20941 = getelementptr inbounds float, float* %tmp20940, i64 1
+  %tmp20942 = getelementptr inbounds float, float* %tmp20941, i64 1
+  %tmp20943 = getelementptr inbounds float, float* %tmp20942, i64 1
+  %tmp20944 = getelementptr inbounds float, float* %tmp20943, i64 1
+  %tmp20945 = getelementptr inbounds float, float* %tmp20944, i64 1
+  %tmp20946 = getelementptr inbounds float, float* %tmp20945, i64 1
+  %tmp20947 = getelementptr inbounds float, float* %tmp20946, i64 1
+  %tmp20948 = getelementptr inbounds float, float* %tmp20947, i64 1
+  %tmp20949 = getelementptr inbounds float, float* %tmp20948, i64 1
+  %tmp20950 = getelementptr inbounds float, float* %tmp20949, i64 1
+  %tmp20951 = getelementptr inbounds float, float* %tmp20950, i64 1
+  %tmp20952 = getelementptr inbounds float, float* %tmp20951, i64 1
+  %tmp20953 = getelementptr inbounds float, float* %tmp20952, i64 1
+  %tmp20954 = getelementptr inbounds float, float* %tmp20953, i64 1
+  %tmp20955 = getelementptr inbounds float, float* %tmp20954, i64 1
+  %tmp20956 = getelementptr inbounds float, float* %tmp20955, i64 1
+  %tmp20957 = getelementptr inbounds float, float* %tmp20956, i64 1
+  %tmp20958 = getelementptr inbounds float, float* %tmp20957, i64 1
+  %tmp20959 = getelementptr inbounds float, float* %tmp20958, i64 1
+  %tmp20960 = getelementptr inbounds float, float* %tmp20959, i64 1
+  %tmp20961 = getelementptr inbounds float, float* %tmp20960, i64 1
+  %tmp20962 = getelementptr inbounds float, float* %tmp20961, i64 1
+  %tmp20963 = getelementptr inbounds float, float* %tmp20962, i64 1
+  %tmp20964 = getelementptr inbounds float, float* %tmp20963, i64 1
+  %tmp20965 = getelementptr inbounds float, float* %tmp20964, i64 1
+  %tmp20966 = getelementptr inbounds float, float* %tmp20965, i64 1
+  %tmp20967 = getelementptr inbounds float, float* %tmp20966, i64 1
+  %tmp20968 = getelementptr inbounds float, float* %tmp20967, i64 1
+  %tmp20969 = getelementptr inbounds float, float* %tmp20968, i64 1
+  %tmp20970 = getelementptr inbounds float, float* %tmp20969, i64 1
+  %tmp20971 = getelementptr inbounds float, float* %tmp20970, i64 1
+  %tmp20972 = getelementptr inbounds float, float* %tmp20971, i64 1
+  %tmp20973 = getelementptr inbounds float, float* %tmp20972, i64 1
+  %tmp20974 = getelementptr inbounds float, float* %tmp20973, i64 1
+  %tmp20975 = getelementptr inbounds float, float* %tmp20974, i64 1
+  %tmp20976 = getelementptr inbounds float, float* %tmp20975, i64 1
+  %tmp20977 = getelementptr inbounds float, float* %tmp20976, i64 1
+  %tmp20978 = getelementptr inbounds float, float* %tmp20977, i64 1
+  %tmp20979 = getelementptr inbounds float, float* %tmp20978, i64 1
+  %tmp20980 = getelementptr inbounds float, float* %tmp20979, i64 1
+  %tmp20981 = getelementptr inbounds float, float* %tmp20980, i64 1
+  %tmp20982 = getelementptr inbounds float, float* %tmp20981, i64 1
+  %tmp20983 = getelementptr inbounds float, float* %tmp20982, i64 1
+  %tmp20984 = getelementptr inbounds float, float* %tmp20983, i64 1
+  %tmp20985 = getelementptr inbounds float, float* %tmp20984, i64 1
+  %tmp20986 = getelementptr inbounds float, float* %tmp20985, i64 1
+  %tmp20987 = getelementptr inbounds float, float* %tmp20986, i64 1
+  %tmp20988 = getelementptr inbounds float, float* %tmp20987, i64 1
+  %tmp20989 = getelementptr inbounds float, float* %tmp20988, i64 1
+  %tmp20990 = getelementptr inbounds float, float* %tmp20989, i64 1
+  %tmp20991 = getelementptr inbounds float, float* %tmp20990, i64 1
+  %tmp20992 = getelementptr inbounds float, float* %tmp20991, i64 1
+  %tmp20993 = getelementptr inbounds float, float* %tmp20992, i64 1
+  %tmp20994 = getelementptr inbounds float, float* %tmp20993, i64 1
+  %tmp20995 = getelementptr inbounds float, float* %tmp20994, i64 1
+  %tmp20996 = getelementptr inbounds float, float* %tmp20995, i64 1
+  %tmp20997 = getelementptr inbounds float, float* %tmp20996, i64 1
+  %tmp20998 = getelementptr inbounds float, float* %tmp20997, i64 1
+  %tmp20999 = getelementptr inbounds float, float* %tmp20998, i64 1
+  %tmp21000 = getelementptr inbounds float, float* %tmp20999, i64 1
+  %tmp21001 = getelementptr inbounds float, float* %tmp21000, i64 1
+  %tmp21002 = getelementptr inbounds float, float* %tmp21001, i64 1
+  %tmp21003 = getelementptr inbounds float, float* %tmp21002, i64 1
+  %tmp21004 = getelementptr inbounds float, float* %tmp21003, i64 1
+  %tmp21005 = getelementptr inbounds float, float* %tmp21004, i64 1
+  %tmp21006 = getelementptr inbounds float, float* %tmp21005, i64 1
+  %tmp21007 = getelementptr inbounds float, float* %tmp21006, i64 1
+  %tmp21008 = getelementptr inbounds float, float* %tmp21007, i64 1
+  %tmp21009 = getelementptr inbounds float, float* %tmp21008, i64 1
+  %tmp21010 = getelementptr inbounds float, float* %tmp21009, i64 1
+  %tmp21011 = getelementptr inbounds float, float* %tmp21010, i64 1
+  %tmp21012 = getelementptr inbounds float, float* %tmp21011, i64 1
+  %tmp21013 = getelementptr inbounds float, float* %tmp21012, i64 1
+  %tmp21014 = getelementptr inbounds float, float* %tmp21013, i64 1
+  %tmp21015 = getelementptr inbounds float, float* %tmp21014, i64 1
+  %tmp21016 = getelementptr inbounds float, float* %tmp21015, i64 1
+  %tmp21017 = getelementptr inbounds float, float* %tmp21016, i64 1
+  %tmp21018 = getelementptr inbounds float, float* %tmp21017, i64 1
+  %tmp21019 = getelementptr inbounds float, float* %tmp21018, i64 1
+  %tmp21020 = getelementptr inbounds float, float* %tmp21019, i64 1
+  %tmp21021 = getelementptr inbounds float, float* %tmp21020, i64 1
+  %tmp21022 = getelementptr inbounds float, float* %tmp21021, i64 1
+  %tmp21023 = getelementptr inbounds float, float* %tmp21022, i64 1
+  %tmp21024 = getelementptr inbounds float, float* %tmp21023, i64 1
+  %tmp21025 = getelementptr inbounds float, float* %tmp21024, i64 1
+  %tmp21026 = getelementptr inbounds float, float* %tmp21025, i64 1
+  %tmp21027 = getelementptr inbounds float, float* %tmp21026, i64 1
+  %tmp21028 = getelementptr inbounds float, float* %tmp21027, i64 1
+  %tmp21029 = getelementptr inbounds float, float* %tmp21028, i64 1
+  %tmp21030 = getelementptr inbounds float, float* %tmp21029, i64 1
+  %tmp21031 = getelementptr inbounds float, float* %tmp21030, i64 1
+  %tmp21032 = getelementptr inbounds float, float* %tmp21031, i64 1
+  %tmp21033 = getelementptr inbounds float, float* %tmp21032, i64 1
+  %tmp21034 = getelementptr inbounds float, float* %tmp21033, i64 1
+  %tmp21035 = getelementptr inbounds float, float* %tmp21034, i64 1
+  %tmp21036 = getelementptr inbounds float, float* %tmp21035, i64 1
+  %tmp21037 = getelementptr inbounds float, float* %tmp21036, i64 1
+  %tmp21038 = getelementptr inbounds float, float* %tmp21037, i64 1
+  %tmp21039 = getelementptr inbounds float, float* %tmp21038, i64 1
+  %tmp21040 = getelementptr inbounds float, float* %tmp21039, i64 1
+  %tmp21041 = getelementptr inbounds float, float* %tmp21040, i64 1
+  %tmp21042 = getelementptr inbounds float, float* %tmp21041, i64 1
+  %tmp21043 = getelementptr inbounds float, float* %tmp21042, i64 1
+  %tmp21044 = getelementptr inbounds float, float* %tmp21043, i64 1
+  %tmp21045 = getelementptr inbounds float, float* %tmp21044, i64 1
+  %tmp21046 = getelementptr inbounds float, float* %tmp21045, i64 1
+  %tmp21047 = getelementptr inbounds float, float* %tmp21046, i64 1
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+  %tmp21049 = getelementptr inbounds float, float* %tmp21048, i64 1
+  %tmp21050 = getelementptr inbounds float, float* %tmp21049, i64 1
+  %tmp21051 = getelementptr inbounds float, float* %tmp21050, i64 1
+  %tmp21052 = getelementptr inbounds float, float* %tmp21051, i64 1
+  %tmp21053 = getelementptr inbounds float, float* %tmp21052, i64 1
+  %tmp21054 = getelementptr inbounds float, float* %tmp21053, i64 1
+  %tmp21055 = getelementptr inbounds float, float* %tmp21054, i64 1
+  %tmp21056 = getelementptr inbounds float, float* %tmp21055, i64 1
+  %tmp21057 = getelementptr inbounds float, float* %tmp21056, i64 1
+  %tmp21058 = getelementptr inbounds float, float* %tmp21057, i64 1
+  %tmp21059 = getelementptr inbounds float, float* %tmp21058, i64 1
+  %tmp21060 = getelementptr inbounds float, float* %tmp21059, i64 1
+  %tmp21061 = getelementptr inbounds float, float* %tmp21060, i64 1
+  %tmp21062 = getelementptr inbounds float, float* %tmp21061, i64 1
+  %tmp21063 = getelementptr inbounds float, float* %tmp21062, i64 1
+  %tmp21064 = getelementptr inbounds float, float* %tmp21063, i64 1
+  %tmp21065 = getelementptr inbounds float, float* %tmp21064, i64 1
+  %tmp21066 = getelementptr inbounds float, float* %tmp21065, i64 1
+  %tmp21067 = getelementptr inbounds float, float* %tmp21066, i64 1
+  %tmp21068 = getelementptr inbounds float, float* %tmp21067, i64 1
+  %tmp21069 = getelementptr inbounds float, float* %tmp21068, i64 1
+  %tmp21070 = getelementptr inbounds float, float* %tmp21069, i64 1
+  %tmp21071 = getelementptr inbounds float, float* %tmp21070, i64 1
+  %tmp21072 = getelementptr inbounds float, float* %tmp21071, i64 1
+  %tmp21073 = getelementptr inbounds float, float* %tmp21072, i64 1
+  %tmp21074 = getelementptr inbounds float, float* %tmp21073, i64 1
+  %tmp21075 = getelementptr inbounds float, float* %tmp21074, i64 1
+  %tmp21076 = getelementptr inbounds float, float* %tmp21075, i64 1
+  %tmp21077 = getelementptr inbounds float, float* %tmp21076, i64 1
+  %tmp21078 = getelementptr inbounds float, float* %tmp21077, i64 1
+  %tmp21079 = getelementptr inbounds float, float* %tmp21078, i64 1
+  %tmp21080 = getelementptr inbounds float, float* %tmp21079, i64 1
+  %tmp21081 = getelementptr inbounds float, float* %tmp21080, i64 1
+  %tmp21082 = getelementptr inbounds float, float* %tmp21081, i64 1
+  %tmp21083 = getelementptr inbounds float, float* %tmp21082, i64 1
+  %tmp21084 = getelementptr inbounds float, float* %tmp21083, i64 1
+  %tmp21085 = getelementptr inbounds float, float* %tmp21084, i64 1
+  %tmp21086 = getelementptr inbounds float, float* %tmp21085, i64 1
+  %tmp21087 = getelementptr inbounds float, float* %tmp21086, i64 1
+  %tmp21088 = getelementptr inbounds float, float* %tmp21087, i64 1
+  %tmp21089 = getelementptr inbounds float, float* %tmp21088, i64 1
+  %tmp21090 = getelementptr inbounds float, float* %tmp21089, i64 1
+  %tmp21091 = getelementptr inbounds float, float* %tmp21090, i64 1
+  %tmp21092 = getelementptr inbounds float, float* %tmp21091, i64 1
+  %tmp21093 = getelementptr inbounds float, float* %tmp21092, i64 1
+  %tmp21094 = getelementptr inbounds float, float* %tmp21093, i64 1
+  %tmp21095 = getelementptr inbounds float, float* %tmp21094, i64 1
+  %tmp21096 = getelementptr inbounds float, float* %tmp21095, i64 1
+  %tmp21097 = getelementptr inbounds float, float* %tmp21096, i64 1
+  %tmp21098 = getelementptr inbounds float, float* %tmp21097, i64 1
+  %tmp21099 = getelementptr inbounds float, float* %tmp21098, i64 1
+  %tmp21100 = getelementptr inbounds float, float* %tmp21099, i64 1
+  %tmp21101 = getelementptr inbounds float, float* %tmp21100, i64 1
+  %tmp21102 = getelementptr inbounds float, float* %tmp21101, i64 1
+  %tmp21103 = getelementptr inbounds float, float* %tmp21102, i64 1
+  %tmp21104 = getelementptr inbounds float, float* %tmp21103, i64 1
+  %tmp21105 = getelementptr inbounds float, float* %tmp21104, i64 1
+  %tmp21106 = getelementptr inbounds float, float* %tmp21105, i64 1
+  %tmp21107 = getelementptr inbounds float, float* %tmp21106, i64 1
+  %tmp21108 = getelementptr inbounds float, float* %tmp21107, i64 1
+  %tmp21109 = getelementptr inbounds float, float* %tmp21108, i64 1
+  %tmp21110 = getelementptr inbounds float, float* %tmp21109, i64 1
+  %tmp21111 = getelementptr inbounds float, float* %tmp21110, i64 1
+  %tmp21112 = getelementptr inbounds float, float* %tmp21111, i64 1
+  %tmp21113 = getelementptr inbounds float, float* %tmp21112, i64 1
+  %tmp21114 = getelementptr inbounds float, float* %tmp21113, i64 1
+  %tmp21115 = getelementptr inbounds float, float* %tmp21114, i64 1
+  %tmp21116 = getelementptr inbounds float, float* %tmp21115, i64 1
+  %tmp21117 = getelementptr inbounds float, float* %tmp21116, i64 1
+  %tmp21118 = getelementptr inbounds float, float* %tmp21117, i64 1
+  %tmp21119 = getelementptr inbounds float, float* %tmp21118, i64 1
+  %tmp21120 = getelementptr inbounds float, float* %tmp21119, i64 1
+  %tmp21121 = getelementptr inbounds float, float* %tmp21120, i64 1
+  %tmp21122 = getelementptr inbounds float, float* %tmp21121, i64 1
+  %tmp21123 = getelementptr inbounds float, float* %tmp21122, i64 1
+  %tmp21124 = getelementptr inbounds float, float* %tmp21123, i64 1
+  %tmp21125 = getelementptr inbounds float, float* %tmp21124, i64 1
+  %tmp21126 = getelementptr inbounds float, float* %tmp21125, i64 1
+  %tmp21127 = getelementptr inbounds float, float* %tmp21126, i64 1
+  %tmp21128 = getelementptr inbounds float, float* %tmp21127, i64 1
+  %tmp21129 = getelementptr inbounds float, float* %tmp21128, i64 1
+  %tmp21130 = getelementptr inbounds float, float* %tmp21129, i64 1
+  %tmp21131 = getelementptr inbounds float, float* %tmp21130, i64 1
+  %tmp21132 = getelementptr inbounds float, float* %tmp21131, i64 1
+  %tmp21133 = getelementptr inbounds float, float* %tmp21132, i64 1
+  %tmp21134 = getelementptr inbounds float, float* %tmp21133, i64 1
+  %tmp21135 = getelementptr inbounds float, float* %tmp21134, i64 1
+  %tmp21136 = getelementptr inbounds float, float* %tmp21135, i64 1
+  %tmp21137 = getelementptr inbounds float, float* %tmp21136, i64 1
+  %tmp21138 = getelementptr inbounds float, float* %tmp21137, i64 1
+  %tmp21139 = getelementptr inbounds float, float* %tmp21138, i64 1
+  %tmp21140 = getelementptr inbounds float, float* %tmp21139, i64 1
+  %tmp21141 = getelementptr inbounds float, float* %tmp21140, i64 1
+  %tmp21142 = getelementptr inbounds float, float* %tmp21141, i64 1
+  %tmp21143 = getelementptr inbounds float, float* %tmp21142, i64 1
+  %tmp21144 = getelementptr inbounds float, float* %tmp21143, i64 1
+  %tmp21145 = getelementptr inbounds float, float* %tmp21144, i64 1
+  %tmp21146 = getelementptr inbounds float, float* %tmp21145, i64 1
+  %tmp21147 = getelementptr inbounds float, float* %tmp21146, i64 1
+  %tmp21148 = getelementptr inbounds float, float* %tmp21147, i64 1
+  %tmp21149 = getelementptr inbounds float, float* %tmp21148, i64 1
+  %tmp21150 = getelementptr inbounds float, float* %tmp21149, i64 1
+  %tmp21151 = getelementptr inbounds float, float* %tmp21150, i64 1
+  %tmp21152 = getelementptr inbounds float, float* %tmp21151, i64 1
+  %tmp21153 = getelementptr inbounds float, float* %tmp21152, i64 1
+  %tmp21154 = getelementptr inbounds float, float* %tmp21153, i64 1
+  %tmp21155 = getelementptr inbounds float, float* %tmp21154, i64 1
+  %tmp21156 = getelementptr inbounds float, float* %tmp21155, i64 1
+  %tmp21157 = getelementptr inbounds float, float* %tmp21156, i64 1
+  %tmp21158 = getelementptr inbounds float, float* %tmp21157, i64 1
+  %tmp21159 = getelementptr inbounds float, float* %tmp21158, i64 1
+  %tmp21160 = getelementptr inbounds float, float* %tmp21159, i64 1
+  %tmp21161 = getelementptr inbounds float, float* %tmp21160, i64 1
+  %tmp21162 = getelementptr inbounds float, float* %tmp21161, i64 1
+  %tmp21163 = getelementptr inbounds float, float* %tmp21162, i64 1
+  %tmp21164 = getelementptr inbounds float, float* %tmp21163, i64 1
+  %tmp21165 = getelementptr inbounds float, float* %tmp21164, i64 1
+  %tmp21166 = getelementptr inbounds float, float* %tmp21165, i64 1
+  %tmp21167 = getelementptr inbounds float, float* %tmp21166, i64 1
+  %tmp21168 = getelementptr inbounds float, float* %tmp21167, i64 1
+  %tmp21169 = getelementptr inbounds float, float* %tmp21168, i64 1
+  %tmp21170 = getelementptr inbounds float, float* %tmp21169, i64 1
+  %tmp21171 = getelementptr inbounds float, float* %tmp21170, i64 1
+  %tmp21172 = getelementptr inbounds float, float* %tmp21171, i64 1
+  %tmp21173 = getelementptr inbounds float, float* %tmp21172, i64 1
+  %tmp21174 = getelementptr inbounds float, float* %tmp21173, i64 1
+  %tmp21175 = getelementptr inbounds float, float* %tmp21174, i64 1
+  %tmp21176 = getelementptr inbounds float, float* %tmp21175, i64 1
+  %tmp21177 = getelementptr inbounds float, float* %tmp21176, i64 1
+  %tmp21178 = getelementptr inbounds float, float* %tmp21177, i64 1
+  %tmp21179 = getelementptr inbounds float, float* %tmp21178, i64 1
+  %tmp21180 = getelementptr inbounds float, float* %tmp21179, i64 1
+  %tmp21181 = getelementptr inbounds float, float* %tmp21180, i64 1
+  %tmp21182 = getelementptr inbounds float, float* %tmp21181, i64 1
+  %tmp21183 = getelementptr inbounds float, float* %tmp21182, i64 1
+  %tmp21184 = getelementptr inbounds float, float* %tmp21183, i64 1
+  %tmp21185 = getelementptr inbounds float, float* %tmp21184, i64 1
+  %tmp21186 = getelementptr inbounds float, float* %tmp21185, i64 1
+  %tmp21187 = getelementptr inbounds float, float* %tmp21186, i64 1
+  %tmp21188 = getelementptr inbounds float, float* %tmp21187, i64 1
+  %tmp21189 = getelementptr inbounds float, float* %tmp21188, i64 1
+  %tmp21190 = getelementptr inbounds float, float* %tmp21189, i64 1
+  %tmp21191 = getelementptr inbounds float, float* %tmp21190, i64 1
+  %tmp21192 = getelementptr inbounds float, float* %tmp21191, i64 1
+  %tmp21193 = getelementptr inbounds float, float* %tmp21192, i64 1
+  %tmp21194 = getelementptr inbounds float, float* %tmp21193, i64 1
+  %tmp21195 = getelementptr inbounds float, float* %tmp21194, i64 1
+  %tmp21196 = getelementptr inbounds float, float* %tmp21195, i64 1
+  %tmp21197 = getelementptr inbounds float, float* %tmp21196, i64 1
+  %tmp21198 = getelementptr inbounds float, float* %tmp21197, i64 1
+  %tmp21199 = getelementptr inbounds float, float* %tmp21198, i64 1
+  %tmp21200 = getelementptr inbounds float, float* %tmp21199, i64 1
+  %tmp21201 = getelementptr inbounds float, float* %tmp21200, i64 1
+  %tmp21202 = getelementptr inbounds float, float* %tmp21201, i64 1
+  %tmp21203 = getelementptr inbounds float, float* %tmp21202, i64 1
+  %tmp21204 = getelementptr inbounds float, float* %tmp21203, i64 1
+  %tmp21205 = getelementptr inbounds float, float* %tmp21204, i64 1
+  %tmp21206 = getelementptr inbounds float, float* %tmp21205, i64 1
+  %tmp21207 = getelementptr inbounds float, float* %tmp21206, i64 1
+  %tmp21208 = getelementptr inbounds float, float* %tmp21207, i64 1
+  %tmp21209 = getelementptr inbounds float, float* %tmp21208, i64 1
+  %tmp21210 = getelementptr inbounds float, float* %tmp21209, i64 1
+  %tmp21211 = getelementptr inbounds float, float* %tmp21210, i64 1
+  %tmp21212 = getelementptr inbounds float, float* %tmp21211, i64 1
+  %tmp21213 = getelementptr inbounds float, float* %tmp21212, i64 1
+  %tmp21214 = getelementptr inbounds float, float* %tmp21213, i64 1
+  %tmp21215 = getelementptr inbounds float, float* %tmp21214, i64 1
+  %tmp21216 = getelementptr inbounds float, float* %tmp21215, i64 1
+  %tmp21217 = getelementptr inbounds float, float* %tmp21216, i64 1
+  %tmp21218 = getelementptr inbounds float, float* %tmp21217, i64 1
+  %tmp21219 = getelementptr inbounds float, float* %tmp21218, i64 1
+  %tmp21220 = getelementptr inbounds float, float* %tmp21219, i64 1
+  %tmp21221 = getelementptr inbounds float, float* %tmp21220, i64 1
+  %tmp21222 = getelementptr inbounds float, float* %tmp21221, i64 1
+  %tmp21223 = getelementptr inbounds float, float* %tmp21222, i64 1
+  %tmp21224 = getelementptr inbounds float, float* %tmp21223, i64 1
+  %tmp21225 = getelementptr inbounds float, float* %tmp21224, i64 1
+  %tmp21226 = getelementptr inbounds float, float* %tmp21225, i64 1
+  %tmp21227 = getelementptr inbounds float, float* %tmp21226, i64 1
+  %tmp21228 = getelementptr inbounds float, float* %tmp21227, i64 1
+  %tmp21229 = getelementptr inbounds float, float* %tmp21228, i64 1
+  %tmp21230 = getelementptr inbounds float, float* %tmp21229, i64 1
+  %tmp21231 = getelementptr inbounds float, float* %tmp21230, i64 1
+  %tmp21232 = getelementptr inbounds float, float* %tmp21231, i64 1
+  %tmp21233 = getelementptr inbounds float, float* %tmp21232, i64 1
+  %tmp21234 = getelementptr inbounds float, float* %tmp21233, i64 1
+  %tmp21235 = getelementptr inbounds float, float* %tmp21234, i64 1
+  %tmp21236 = getelementptr inbounds float, float* %tmp21235, i64 1
+  %tmp21237 = getelementptr inbounds float, float* %tmp21236, i64 1
+  %tmp21238 = getelementptr inbounds float, float* %tmp21237, i64 1
+  %tmp21239 = getelementptr inbounds float, float* %tmp21238, i64 1
+  %tmp21240 = getelementptr inbounds float, float* %tmp21239, i64 1
+  %tmp21241 = getelementptr inbounds float, float* %tmp21240, i64 1
+  %tmp21242 = getelementptr inbounds float, float* %tmp21241, i64 1
+  %tmp21243 = getelementptr inbounds float, float* %tmp21242, i64 1
+  %tmp21244 = getelementptr inbounds float, float* %tmp21243, i64 1
+  %tmp21245 = getelementptr inbounds float, float* %tmp21244, i64 1
+  %tmp21246 = getelementptr inbounds float, float* %tmp21245, i64 1
+  %tmp21247 = getelementptr inbounds float, float* %tmp21246, i64 1
+  %tmp21248 = getelementptr inbounds float, float* %tmp21247, i64 1
+  %tmp21249 = getelementptr inbounds float, float* %tmp21248, i64 1
+  %tmp21250 = getelementptr inbounds float, float* %tmp21249, i64 1
+  %tmp21251 = getelementptr inbounds float, float* %tmp21250, i64 1
+  %tmp21252 = getelementptr inbounds float, float* %tmp21251, i64 1
+  %tmp21253 = getelementptr inbounds float, float* %tmp21252, i64 1
+  %tmp21254 = getelementptr inbounds float, float* %tmp21253, i64 1
+  %tmp21255 = getelementptr inbounds float, float* %tmp21254, i64 1
+  %tmp21256 = getelementptr inbounds float, float* %tmp21255, i64 1
+  %tmp21257 = getelementptr inbounds float, float* %tmp21256, i64 1
+  %tmp21258 = getelementptr inbounds float, float* %tmp21257, i64 1
+  %tmp21259 = getelementptr inbounds float, float* %tmp21258, i64 1
+  %tmp21260 = getelementptr inbounds float, float* %tmp21259, i64 1
+  %tmp21261 = getelementptr inbounds float, float* %tmp21260, i64 1
+  %tmp21262 = getelementptr inbounds float, float* %tmp21261, i64 1
+  %tmp21263 = getelementptr inbounds float, float* %tmp21262, i64 1
+  %tmp21264 = getelementptr inbounds float, float* %tmp21263, i64 1
+  %tmp21265 = getelementptr inbounds float, float* %tmp21264, i64 1
+  %tmp21266 = getelementptr inbounds float, float* %tmp21265, i64 1
+  %tmp21267 = getelementptr inbounds float, float* %tmp21266, i64 1
+  %tmp21268 = getelementptr inbounds float, float* %tmp21267, i64 1
+  %tmp21269 = getelementptr inbounds float, float* %tmp21268, i64 1
+  %tmp21270 = getelementptr inbounds float, float* %tmp21269, i64 1
+  %tmp21271 = getelementptr inbounds float, float* %tmp21270, i64 1
+  %tmp21272 = getelementptr inbounds float, float* %tmp21271, i64 1
+  %tmp21273 = getelementptr inbounds float, float* %tmp21272, i64 1
+  %tmp21274 = getelementptr inbounds float, float* %tmp21273, i64 1
+  %tmp21275 = getelementptr inbounds float, float* %tmp21274, i64 1
+  %tmp21276 = getelementptr inbounds float, float* %tmp21275, i64 1
+  %tmp21277 = getelementptr inbounds float, float* %tmp21276, i64 1
+  %tmp21278 = getelementptr inbounds float, float* %tmp21277, i64 1
+  %tmp21279 = getelementptr inbounds float, float* %tmp21278, i64 1
+  %tmp21280 = getelementptr inbounds float, float* %tmp21279, i64 1
+  %tmp21281 = getelementptr inbounds float, float* %tmp21280, i64 1
+  %tmp21282 = getelementptr inbounds float, float* %tmp21281, i64 1
+  %tmp21283 = getelementptr inbounds float, float* %tmp21282, i64 1
+  %tmp21284 = getelementptr inbounds float, float* %tmp21283, i64 1
+  %tmp21285 = getelementptr inbounds float, float* %tmp21284, i64 1
+  %tmp21286 = getelementptr inbounds float, float* %tmp21285, i64 1
+  %tmp21287 = getelementptr inbounds float, float* %tmp21286, i64 1
+  %tmp21288 = getelementptr inbounds float, float* %tmp21287, i64 1
+  %tmp21289 = getelementptr inbounds float, float* %tmp21288, i64 1
+  %tmp21290 = getelementptr inbounds float, float* %tmp21289, i64 1
+  %tmp21291 = getelementptr inbounds float, float* %tmp21290, i64 1
+  %tmp21292 = getelementptr inbounds float, float* %tmp21291, i64 1
+  %tmp21293 = getelementptr inbounds float, float* %tmp21292, i64 1
+  %tmp21294 = getelementptr inbounds float, float* %tmp21293, i64 1
+  %tmp21295 = getelementptr inbounds float, float* %tmp21294, i64 1
+  %tmp21296 = getelementptr inbounds float, float* %tmp21295, i64 1
+  %tmp21297 = getelementptr inbounds float, float* %tmp21296, i64 1
+  %tmp21298 = getelementptr inbounds float, float* %tmp21297, i64 1
+  %tmp21299 = getelementptr inbounds float, float* %tmp21298, i64 1
+  %tmp21300 = getelementptr inbounds float, float* %tmp21299, i64 1
+  %tmp21301 = getelementptr inbounds float, float* %tmp21300, i64 1
+  %tmp21302 = getelementptr inbounds float, float* %tmp21301, i64 1
+  %tmp21303 = getelementptr inbounds float, float* %tmp21302, i64 1
+  %tmp21304 = getelementptr inbounds float, float* %tmp21303, i64 1
+  %tmp21305 = getelementptr inbounds float, float* %tmp21304, i64 1
+  %tmp21306 = getelementptr inbounds float, float* %tmp21305, i64 1
+  %tmp21307 = getelementptr inbounds float, float* %tmp21306, i64 1
+  %tmp21308 = getelementptr inbounds float, float* %tmp21307, i64 1
+  %tmp21309 = getelementptr inbounds float, float* %tmp21308, i64 1
+  %tmp21310 = getelementptr inbounds float, float* %tmp21309, i64 1
+  %tmp21311 = getelementptr inbounds float, float* %tmp21310, i64 1
+  %tmp21312 = getelementptr inbounds float, float* %tmp21311, i64 1
+  %tmp21313 = getelementptr inbounds float, float* %tmp21312, i64 1
+  %tmp21314 = getelementptr inbounds float, float* %tmp21313, i64 1
+  %tmp21315 = getelementptr inbounds float, float* %tmp21314, i64 1
+  %tmp21316 = getelementptr inbounds float, float* %tmp21315, i64 1
+  %tmp21317 = getelementptr inbounds float, float* %tmp21316, i64 1
+  %tmp21318 = getelementptr inbounds float, float* %tmp21317, i64 1
+  %tmp21319 = getelementptr inbounds float, float* %tmp21318, i64 1
+  %tmp21320 = getelementptr inbounds float, float* %tmp21319, i64 1
+  %tmp21321 = getelementptr inbounds float, float* %tmp21320, i64 1
+  %tmp21322 = getelementptr inbounds float, float* %tmp21321, i64 1
+  %tmp21323 = getelementptr inbounds float, float* %tmp21322, i64 1
+  %tmp21324 = getelementptr inbounds float, float* %tmp21323, i64 1
+  %tmp21325 = getelementptr inbounds float, float* %tmp21324, i64 1
+  %tmp21326 = getelementptr inbounds float, float* %tmp21325, i64 1
+  %tmp21327 = getelementptr inbounds float, float* %tmp21326, i64 1
+  %tmp21328 = getelementptr inbounds float, float* %tmp21327, i64 1
+  %tmp21329 = getelementptr inbounds float, float* %tmp21328, i64 1
+  %tmp21330 = getelementptr inbounds float, float* %tmp21329, i64 1
+  %tmp21331 = getelementptr inbounds float, float* %tmp21330, i64 1
+  %tmp21332 = getelementptr inbounds float, float* %tmp21331, i64 1
+  %tmp21333 = getelementptr inbounds float, float* %tmp21332, i64 1
+  %tmp21334 = getelementptr inbounds float, float* %tmp21333, i64 1
+  %tmp21335 = getelementptr inbounds float, float* %tmp21334, i64 1
+  %tmp21336 = getelementptr inbounds float, float* %tmp21335, i64 1
+  %tmp21337 = getelementptr inbounds float, float* %tmp21336, i64 1
+  %tmp21338 = getelementptr inbounds float, float* %tmp21337, i64 1
+  %tmp21339 = getelementptr inbounds float, float* %tmp21338, i64 1
+  %tmp21340 = getelementptr inbounds float, float* %tmp21339, i64 1
+  %tmp21341 = getelementptr inbounds float, float* %tmp21340, i64 1
+  %tmp21342 = getelementptr inbounds float, float* %tmp21341, i64 1
+  %tmp21343 = getelementptr inbounds float, float* %tmp21342, i64 1
+  %tmp21344 = getelementptr inbounds float, float* %tmp21343, i64 1
+  %tmp21345 = getelementptr inbounds float, float* %tmp21344, i64 1
+  %tmp21346 = getelementptr inbounds float, float* %tmp21345, i64 1
+  %tmp21347 = getelementptr inbounds float, float* %tmp21346, i64 1
+  %tmp21348 = getelementptr inbounds float, float* %tmp21347, i64 1
+  %tmp21349 = getelementptr inbounds float, float* %tmp21348, i64 1
+  %tmp21350 = getelementptr inbounds float, float* %tmp21349, i64 1
+  %tmp21351 = getelementptr inbounds float, float* %tmp21350, i64 1
+  %tmp21352 = getelementptr inbounds float, float* %tmp21351, i64 1
+  %tmp21353 = getelementptr inbounds float, float* %tmp21352, i64 1
+  %tmp21354 = getelementptr inbounds float, float* %tmp21353, i64 1
+  %tmp21355 = getelementptr inbounds float, float* %tmp21354, i64 1
+  %tmp21356 = getelementptr inbounds float, float* %tmp21355, i64 1
+  %tmp21357 = getelementptr inbounds float, float* %tmp21356, i64 1
+  %tmp21358 = getelementptr inbounds float, float* %tmp21357, i64 1
+  %tmp21359 = getelementptr inbounds float, float* %tmp21358, i64 1
+  %tmp21360 = getelementptr inbounds float, float* %tmp21359, i64 1
+  %tmp21361 = getelementptr inbounds float, float* %tmp21360, i64 1
+  %tmp21362 = getelementptr inbounds float, float* %tmp21361, i64 1
+  %tmp21363 = getelementptr inbounds float, float* %tmp21362, i64 1
+  %tmp21364 = getelementptr inbounds float, float* %tmp21363, i64 1
+  %tmp21365 = getelementptr inbounds float, float* %tmp21364, i64 1
+  %tmp21366 = getelementptr inbounds float, float* %tmp21365, i64 1
+  %tmp21367 = getelementptr inbounds float, float* %tmp21366, i64 1
+  %tmp21368 = getelementptr inbounds float, float* %tmp21367, i64 1
+  %tmp21369 = getelementptr inbounds float, float* %tmp21368, i64 1
+  %tmp21370 = getelementptr inbounds float, float* %tmp21369, i64 1
+  %tmp21371 = getelementptr inbounds float, float* %tmp21370, i64 1
+  %tmp21372 = getelementptr inbounds float, float* %tmp21371, i64 1
+  %tmp21373 = getelementptr inbounds float, float* %tmp21372, i64 1
+  %tmp21374 = getelementptr inbounds float, float* %tmp21373, i64 1
+  %tmp21375 = getelementptr inbounds float, float* %tmp21374, i64 1
+  %tmp21376 = getelementptr inbounds float, float* %tmp21375, i64 1
+  %tmp21377 = getelementptr inbounds float, float* %tmp21376, i64 1
+  %tmp21378 = getelementptr inbounds float, float* %tmp21377, i64 1
+  %tmp21379 = getelementptr inbounds float, float* %tmp21378, i64 1
+  %tmp21380 = getelementptr inbounds float, float* %tmp21379, i64 1
+  %tmp21381 = getelementptr inbounds float, float* %tmp21380, i64 1
+  %tmp21382 = getelementptr inbounds float, float* %tmp21381, i64 1
+  %tmp21383 = getelementptr inbounds float, float* %tmp21382, i64 1
+  %tmp21384 = getelementptr inbounds float, float* %tmp21383, i64 1
+  %tmp21385 = getelementptr inbounds float, float* %tmp21384, i64 1
+  %tmp21386 = getelementptr inbounds float, float* %tmp21385, i64 1
+  %tmp21387 = getelementptr inbounds float, float* %tmp21386, i64 1
+  %tmp21388 = getelementptr inbounds float, float* %tmp21387, i64 1
+  %tmp21389 = getelementptr inbounds float, float* %tmp21388, i64 1
+  %tmp21390 = getelementptr inbounds float, float* %tmp21389, i64 1
+  %tmp21391 = getelementptr inbounds float, float* %tmp21390, i64 1
+  %tmp21392 = getelementptr inbounds float, float* %tmp21391, i64 1
+  %tmp21393 = getelementptr inbounds float, float* %tmp21392, i64 1
+  %tmp21394 = getelementptr inbounds float, float* %tmp21393, i64 1
+  %tmp21395 = getelementptr inbounds float, float* %tmp21394, i64 1
+  %tmp21396 = getelementptr inbounds float, float* %tmp21395, i64 1
+  %tmp21397 = getelementptr inbounds float, float* %tmp21396, i64 1
+  %tmp21398 = getelementptr inbounds float, float* %tmp21397, i64 1
+  %tmp21399 = getelementptr inbounds float, float* %tmp21398, i64 1
+  %tmp21400 = getelementptr inbounds float, float* %tmp21399, i64 1
+  %tmp21401 = getelementptr inbounds float, float* %tmp21400, i64 1
+  %tmp21402 = getelementptr inbounds float, float* %tmp21401, i64 1
+  %tmp21403 = getelementptr inbounds float, float* %tmp21402, i64 1
+  %tmp21404 = getelementptr inbounds float, float* %tmp21403, i64 1
+  %tmp21405 = getelementptr inbounds float, float* %tmp21404, i64 1
+  %tmp21406 = getelementptr inbounds float, float* %tmp21405, i64 1
+  %tmp21407 = getelementptr inbounds float, float* %tmp21406, i64 1
+  %tmp21408 = getelementptr inbounds float, float* %tmp21407, i64 1
+  %tmp21409 = getelementptr inbounds float, float* %tmp21408, i64 1
+  %tmp21410 = getelementptr inbounds float, float* %tmp21409, i64 1
+  %tmp21411 = getelementptr inbounds float, float* %tmp21410, i64 1
+  %tmp21412 = getelementptr inbounds float, float* %tmp21411, i64 1
+  %tmp21413 = getelementptr inbounds float, float* %tmp21412, i64 1
+  %tmp21414 = getelementptr inbounds float, float* %tmp21413, i64 1
+  %tmp21415 = getelementptr inbounds float, float* %tmp21414, i64 1
+  %tmp21416 = getelementptr inbounds float, float* %tmp21415, i64 1
+  %tmp21417 = getelementptr inbounds float, float* %tmp21416, i64 1
+  %tmp21418 = getelementptr inbounds float, float* %tmp21417, i64 1
+  %tmp21419 = getelementptr inbounds float, float* %tmp21418, i64 1
+  %tmp21420 = getelementptr inbounds float, float* %tmp21419, i64 1
+  %tmp21421 = getelementptr inbounds float, float* %tmp21420, i64 1
+  %tmp21422 = getelementptr inbounds float, float* %tmp21421, i64 1
+  %tmp21423 = getelementptr inbounds float, float* %tmp21422, i64 1
+  %tmp21424 = getelementptr inbounds float, float* %tmp21423, i64 1
+  %tmp21425 = getelementptr inbounds float, float* %tmp21424, i64 1
+  %tmp21426 = getelementptr inbounds float, float* %tmp21425, i64 1
+  %tmp21427 = getelementptr inbounds float, float* %tmp21426, i64 1
+  %tmp21428 = getelementptr inbounds float, float* %tmp21427, i64 1
+  %tmp21429 = getelementptr inbounds float, float* %tmp21428, i64 1
+  %tmp21430 = getelementptr inbounds float, float* %tmp21429, i64 1
+  %tmp21431 = getelementptr inbounds float, float* %tmp21430, i64 1
+  %tmp21432 = getelementptr inbounds float, float* %tmp21431, i64 1
+  %tmp21433 = getelementptr inbounds float, float* %tmp21432, i64 1
+  %tmp21434 = getelementptr inbounds float, float* %tmp21433, i64 1
+  %tmp21435 = getelementptr inbounds float, float* %tmp21434, i64 1
+  %tmp21436 = getelementptr inbounds float, float* %tmp21435, i64 1
+  %tmp21437 = getelementptr inbounds float, float* %tmp21436, i64 1
+  %tmp21438 = getelementptr inbounds float, float* %tmp21437, i64 1
+  %tmp21439 = getelementptr inbounds float, float* %tmp21438, i64 1
+  %tmp21440 = getelementptr inbounds float, float* %tmp21439, i64 1
+  %tmp21441 = getelementptr inbounds float, float* %tmp21440, i64 1
+  %tmp21442 = getelementptr inbounds float, float* %tmp21441, i64 1
+  %tmp21443 = getelementptr inbounds float, float* %tmp21442, i64 1
+  %tmp21444 = getelementptr inbounds float, float* %tmp21443, i64 1
+  %tmp21445 = getelementptr inbounds float, float* %tmp21444, i64 1
+  %tmp21446 = getelementptr inbounds float, float* %tmp21445, i64 1
+  %tmp21447 = getelementptr inbounds float, float* %tmp21446, i64 1
+  %tmp21448 = getelementptr inbounds float, float* %tmp21447, i64 1
+  %tmp21449 = getelementptr inbounds float, float* %tmp21448, i64 1
+  %tmp21450 = getelementptr inbounds float, float* %tmp21449, i64 1
+  %tmp21451 = getelementptr inbounds float, float* %tmp21450, i64 1
+  %tmp21452 = getelementptr inbounds float, float* %tmp21451, i64 1
+  %tmp21453 = getelementptr inbounds float, float* %tmp21452, i64 1
+  %tmp21454 = getelementptr inbounds float, float* %tmp21453, i64 1
+  %tmp21455 = getelementptr inbounds float, float* %tmp21454, i64 1
+  %tmp21456 = getelementptr inbounds float, float* %tmp21455, i64 1
+  %tmp21457 = getelementptr inbounds float, float* %tmp21456, i64 1
+  %tmp21458 = getelementptr inbounds float, float* %tmp21457, i64 1
+  %tmp21459 = getelementptr inbounds float, float* %tmp21458, i64 1
+  %tmp21460 = getelementptr inbounds float, float* %tmp21459, i64 1
+  %tmp21461 = getelementptr inbounds float, float* %tmp21460, i64 1
+  %tmp21462 = getelementptr inbounds float, float* %tmp21461, i64 1
+  %tmp21463 = getelementptr inbounds float, float* %tmp21462, i64 1
+  %tmp21464 = getelementptr inbounds float, float* %tmp21463, i64 1
+  %tmp21465 = getelementptr inbounds float, float* %tmp21464, i64 1
+  %tmp21466 = getelementptr inbounds float, float* %tmp21465, i64 1
+  %tmp21467 = getelementptr inbounds float, float* %tmp21466, i64 1
+  %tmp21468 = getelementptr inbounds float, float* %tmp21467, i64 1
+  %tmp21469 = getelementptr inbounds float, float* %tmp21468, i64 1
+  %tmp21470 = getelementptr inbounds float, float* %tmp21469, i64 1
+  %tmp21471 = getelementptr inbounds float, float* %tmp21470, i64 1
+  %tmp21472 = getelementptr inbounds float, float* %tmp21471, i64 1
+  %tmp21473 = getelementptr inbounds float, float* %tmp21472, i64 1
+  %tmp21474 = getelementptr inbounds float, float* %tmp21473, i64 1
+  %tmp21475 = getelementptr inbounds float, float* %tmp21474, i64 1
+  %tmp21476 = getelementptr inbounds float, float* %tmp21475, i64 1
+  %tmp21477 = getelementptr inbounds float, float* %tmp21476, i64 1
+  %tmp21478 = getelementptr inbounds float, float* %tmp21477, i64 1
+  %tmp21479 = getelementptr inbounds float, float* %tmp21478, i64 1
+  %tmp21480 = getelementptr inbounds float, float* %tmp21479, i64 1
+  %tmp21481 = getelementptr inbounds float, float* %tmp21480, i64 1
+  %tmp21482 = getelementptr inbounds float, float* %tmp21481, i64 1
+  %tmp21483 = getelementptr inbounds float, float* %tmp21482, i64 1
+  %tmp21484 = getelementptr inbounds float, float* %tmp21483, i64 1
+  %tmp21485 = getelementptr inbounds float, float* %tmp21484, i64 1
+  %tmp21486 = getelementptr inbounds float, float* %tmp21485, i64 1
+  %tmp21487 = getelementptr inbounds float, float* %tmp21486, i64 1
+  %tmp21488 = getelementptr inbounds float, float* %tmp21487, i64 1
+  %tmp21489 = getelementptr inbounds float, float* %tmp21488, i64 1
+  %tmp21490 = getelementptr inbounds float, float* %tmp21489, i64 1
+  %tmp21491 = getelementptr inbounds float, float* %tmp21490, i64 1
+  %tmp21492 = getelementptr inbounds float, float* %tmp21491, i64 1
+  %tmp21493 = getelementptr inbounds float, float* %tmp21492, i64 1
+  %tmp21494 = getelementptr inbounds float, float* %tmp21493, i64 1
+  %tmp21495 = getelementptr inbounds float, float* %tmp21494, i64 1
+  %tmp21496 = getelementptr inbounds float, float* %tmp21495, i64 1
+  %tmp21497 = getelementptr inbounds float, float* %tmp21496, i64 1
+  %tmp21498 = getelementptr inbounds float, float* %tmp21497, i64 1
+  %tmp21499 = getelementptr inbounds float, float* %tmp21498, i64 1
+  %tmp21500 = getelementptr inbounds float, float* %tmp21499, i64 1
+  %tmp21501 = getelementptr inbounds float, float* %tmp21500, i64 1
+  %tmp21502 = getelementptr inbounds float, float* %tmp21501, i64 1
+  %tmp21503 = getelementptr inbounds float, float* %tmp21502, i64 1
+  %tmp21504 = getelementptr inbounds float, float* %tmp21503, i64 1
+  %tmp21505 = getelementptr inbounds float, float* %tmp21504, i64 1
+  %tmp21506 = getelementptr inbounds float, float* %tmp21505, i64 1
+  %tmp21507 = getelementptr inbounds float, float* %tmp21506, i64 1
+  %tmp21508 = getelementptr inbounds float, float* %tmp21507, i64 1
+  %tmp21509 = getelementptr inbounds float, float* %tmp21508, i64 1
+  %tmp21510 = getelementptr inbounds float, float* %tmp21509, i64 1
+  %tmp21511 = getelementptr inbounds float, float* %tmp21510, i64 1
+  %tmp21512 = getelementptr inbounds float, float* %tmp21511, i64 1
+  %tmp21513 = getelementptr inbounds float, float* %tmp21512, i64 1
+  %tmp21514 = getelementptr inbounds float, float* %tmp21513, i64 1
+  %tmp21515 = getelementptr inbounds float, float* %tmp21514, i64 1
+  %tmp21516 = getelementptr inbounds float, float* %tmp21515, i64 1
+  %tmp21517 = getelementptr inbounds float, float* %tmp21516, i64 1
+  %tmp21518 = getelementptr inbounds float, float* %tmp21517, i64 1
+  %tmp21519 = getelementptr inbounds float, float* %tmp21518, i64 1
+  %tmp21520 = getelementptr inbounds float, float* %tmp21519, i64 1
+  %tmp21521 = getelementptr inbounds float, float* %tmp21520, i64 1
+  %tmp21522 = getelementptr inbounds float, float* %tmp21521, i64 1
+  %tmp21523 = getelementptr inbounds float, float* %tmp21522, i64 1
+  %tmp21524 = getelementptr inbounds float, float* %tmp21523, i64 1
+  %tmp21525 = getelementptr inbounds float, float* %tmp21524, i64 1
+  %tmp21526 = getelementptr inbounds float, float* %tmp21525, i64 1
+  %tmp21527 = getelementptr inbounds float, float* %tmp21526, i64 1
+  %tmp21528 = getelementptr inbounds float, float* %tmp21527, i64 1
+  %tmp21529 = getelementptr inbounds float, float* %tmp21528, i64 1
+  %tmp21530 = getelementptr inbounds float, float* %tmp21529, i64 1
+  %tmp21531 = getelementptr inbounds float, float* %tmp21530, i64 1
+  %tmp21532 = getelementptr inbounds float, float* %tmp21531, i64 1
+  %tmp21533 = getelementptr inbounds float, float* %tmp21532, i64 1
+  %tmp21534 = getelementptr inbounds float, float* %tmp21533, i64 1
+  %tmp21535 = getelementptr inbounds float, float* %tmp21534, i64 1
+  %tmp21536 = getelementptr inbounds float, float* %tmp21535, i64 1
+  %tmp21537 = getelementptr inbounds float, float* %tmp21536, i64 1
+  %tmp21538 = getelementptr inbounds float, float* %tmp21537, i64 1
+  %tmp21539 = getelementptr inbounds float, float* %tmp21538, i64 1
+  %tmp21540 = getelementptr inbounds float, float* %tmp21539, i64 1
+  %tmp21541 = getelementptr inbounds float, float* %tmp21540, i64 1
+  %tmp21542 = getelementptr inbounds float, float* %tmp21541, i64 1
+  %tmp21543 = getelementptr inbounds float, float* %tmp21542, i64 1
+  %tmp21544 = getelementptr inbounds float, float* %tmp21543, i64 1
+  %tmp21545 = getelementptr inbounds float, float* %tmp21544, i64 1
+  %tmp21546 = getelementptr inbounds float, float* %tmp21545, i64 1
+  %tmp21547 = getelementptr inbounds float, float* %tmp21546, i64 1
+  %tmp21548 = getelementptr inbounds float, float* %tmp21547, i64 1
+  %tmp21549 = getelementptr inbounds float, float* %tmp21548, i64 1
+  %tmp21550 = getelementptr inbounds float, float* %tmp21549, i64 1
+  %tmp21551 = getelementptr inbounds float, float* %tmp21550, i64 1
+  %tmp21552 = getelementptr inbounds float, float* %tmp21551, i64 1
+  %tmp21553 = getelementptr inbounds float, float* %tmp21552, i64 1
+  %tmp21554 = getelementptr inbounds float, float* %tmp21553, i64 1
+  %tmp21555 = getelementptr inbounds float, float* %tmp21554, i64 1
+  %tmp21556 = getelementptr inbounds float, float* %tmp21555, i64 1
+  %tmp21557 = getelementptr inbounds float, float* %tmp21556, i64 1
+  %tmp21558 = getelementptr inbounds float, float* %tmp21557, i64 1
+  %tmp21559 = getelementptr inbounds float, float* %tmp21558, i64 1
+  %tmp21560 = getelementptr inbounds float, float* %tmp21559, i64 1
+  %tmp21561 = getelementptr inbounds float, float* %tmp21560, i64 1
+  %tmp21562 = getelementptr inbounds float, float* %tmp21561, i64 1
+  %tmp21563 = getelementptr inbounds float, float* %tmp21562, i64 1
+  %tmp21564 = getelementptr inbounds float, float* %tmp21563, i64 1
+  %tmp21565 = getelementptr inbounds float, float* %tmp21564, i64 1
+  %tmp21566 = getelementptr inbounds float, float* %tmp21565, i64 1
+  %tmp21567 = getelementptr inbounds float, float* %tmp21566, i64 1
+  %tmp21568 = getelementptr inbounds float, float* %tmp21567, i64 1
+  %tmp21569 = getelementptr inbounds float, float* %tmp21568, i64 1
+  %tmp21570 = getelementptr inbounds float, float* %tmp21569, i64 1
+  %tmp21571 = getelementptr inbounds float, float* %tmp21570, i64 1
+  %tmp21572 = getelementptr inbounds float, float* %tmp21571, i64 1
+  %tmp21573 = getelementptr inbounds float, float* %tmp21572, i64 1
+  %tmp21574 = getelementptr inbounds float, float* %tmp21573, i64 1
+  %tmp21575 = getelementptr inbounds float, float* %tmp21574, i64 1
+  %tmp21576 = getelementptr inbounds float, float* %tmp21575, i64 1
+  %tmp21577 = getelementptr inbounds float, float* %tmp21576, i64 1
+  %tmp21578 = getelementptr inbounds float, float* %tmp21577, i64 1
+  %tmp21579 = getelementptr inbounds float, float* %tmp21578, i64 1
+  %tmp21580 = getelementptr inbounds float, float* %tmp21579, i64 1
+  %tmp21581 = getelementptr inbounds float, float* %tmp21580, i64 1
+  %tmp21582 = getelementptr inbounds float, float* %tmp21581, i64 1
+  %tmp21583 = getelementptr inbounds float, float* %tmp21582, i64 1
+  %tmp21584 = getelementptr inbounds float, float* %tmp21583, i64 1
+  %tmp21585 = getelementptr inbounds float, float* %tmp21584, i64 1
+  %tmp21586 = getelementptr inbounds float, float* %tmp21585, i64 1
+  %tmp21587 = getelementptr inbounds float, float* %tmp21586, i64 1
+  %tmp21588 = getelementptr inbounds float, float* %tmp21587, i64 1
+  %tmp21589 = getelementptr inbounds float, float* %tmp21588, i64 1
+  %tmp21590 = getelementptr inbounds float, float* %tmp21589, i64 1
+  %tmp21591 = getelementptr inbounds float, float* %tmp21590, i64 1
+  %tmp21592 = getelementptr inbounds float, float* %tmp21591, i64 1
+  %tmp21593 = getelementptr inbounds float, float* %tmp21592, i64 1
+  %tmp21594 = getelementptr inbounds float, float* %tmp21593, i64 1
+  %tmp21595 = getelementptr inbounds float, float* %tmp21594, i64 1
+  %tmp21596 = getelementptr inbounds float, float* %tmp21595, i64 1
+  %tmp21597 = getelementptr inbounds float, float* %tmp21596, i64 1
+  %tmp21598 = getelementptr inbounds float, float* %tmp21597, i64 1
+  %tmp21599 = getelementptr inbounds float, float* %tmp21598, i64 1
+  %tmp21600 = getelementptr inbounds float, float* %tmp21599, i64 1
+  %tmp21601 = getelementptr inbounds float, float* %tmp21600, i64 1
+  %tmp21602 = getelementptr inbounds float, float* %tmp21601, i64 1
+  %tmp21603 = getelementptr inbounds float, float* %tmp21602, i64 1
+  %tmp21604 = getelementptr inbounds float, float* %tmp21603, i64 1
+  %tmp21605 = getelementptr inbounds float, float* %tmp21604, i64 1
+  %tmp21606 = getelementptr inbounds float, float* %tmp21605, i64 1
+  %tmp21607 = getelementptr inbounds float, float* %tmp21606, i64 1
+  %tmp21608 = getelementptr inbounds float, float* %tmp21607, i64 1
+  %tmp21609 = getelementptr inbounds float, float* %tmp21608, i64 1
+  %tmp21610 = getelementptr inbounds float, float* %tmp21609, i64 1
+  %tmp21611 = getelementptr inbounds float, float* %tmp21610, i64 1
+  %tmp21612 = getelementptr inbounds float, float* %tmp21611, i64 1
+  %tmp21613 = getelementptr inbounds float, float* %tmp21612, i64 1
+  %tmp21614 = getelementptr inbounds float, float* %tmp21613, i64 1
+  %tmp21615 = getelementptr inbounds float, float* %tmp21614, i64 1
+  %tmp21616 = getelementptr inbounds float, float* %tmp21615, i64 1
+  %tmp21617 = getelementptr inbounds float, float* %tmp21616, i64 1
+  %tmp21618 = getelementptr inbounds float, float* %tmp21617, i64 1
+  %tmp21619 = getelementptr inbounds float, float* %tmp21618, i64 1
+  %tmp21620 = getelementptr inbounds float, float* %tmp21619, i64 1
+  %tmp21621 = getelementptr inbounds float, float* %tmp21620, i64 1
+  %tmp21622 = getelementptr inbounds float, float* %tmp21621, i64 1
+  %tmp21623 = getelementptr inbounds float, float* %tmp21622, i64 1
+  %tmp21624 = getelementptr inbounds float, float* %tmp21623, i64 1
+  %tmp21625 = getelementptr inbounds float, float* %tmp21624, i64 1
+  %tmp21626 = getelementptr inbounds float, float* %tmp21625, i64 1
+  %tmp21627 = getelementptr inbounds float, float* %tmp21626, i64 1
+  %tmp21628 = getelementptr inbounds float, float* %tmp21627, i64 1
+  %tmp21629 = getelementptr inbounds float, float* %tmp21628, i64 1
+  %tmp21630 = getelementptr inbounds float, float* %tmp21629, i64 1
+  %tmp21631 = getelementptr inbounds float, float* %tmp21630, i64 1
+  %tmp21632 = getelementptr inbounds float, float* %tmp21631, i64 1
+  %tmp21633 = getelementptr inbounds float, float* %tmp21632, i64 1
+  %tmp21634 = getelementptr inbounds float, float* %tmp21633, i64 1
+  %tmp21635 = getelementptr inbounds float, float* %tmp21634, i64 1
+  %tmp21636 = getelementptr inbounds float, float* %tmp21635, i64 1
+  %tmp21637 = getelementptr inbounds float, float* %tmp21636, i64 1
+  %tmp21638 = getelementptr inbounds float, float* %tmp21637, i64 1
+  %tmp21639 = getelementptr inbounds float, float* %tmp21638, i64 1
+  %tmp21640 = getelementptr inbounds float, float* %tmp21639, i64 1
+  %tmp21641 = getelementptr inbounds float, float* %tmp21640, i64 1
+  %tmp21642 = getelementptr inbounds float, float* %tmp21641, i64 1
+  %tmp21643 = getelementptr inbounds float, float* %tmp21642, i64 1
+  %tmp21644 = getelementptr inbounds float, float* %tmp21643, i64 1
+  %tmp21645 = getelementptr inbounds float, float* %tmp21644, i64 1
+  %tmp21646 = getelementptr inbounds float, float* %tmp21645, i64 1
+  %tmp21647 = getelementptr inbounds float, float* %tmp21646, i64 1
+  %tmp21648 = getelementptr inbounds float, float* %tmp21647, i64 1
+  %tmp21649 = getelementptr inbounds float, float* %tmp21648, i64 1
+  %tmp21650 = getelementptr inbounds float, float* %tmp21649, i64 1
+  %tmp21651 = getelementptr inbounds float, float* %tmp21650, i64 1
+  %tmp21652 = getelementptr inbounds float, float* %tmp21651, i64 1
+  %tmp21653 = getelementptr inbounds float, float* %tmp21652, i64 1
+  %tmp21654 = getelementptr inbounds float, float* %tmp21653, i64 1
+  %tmp21655 = getelementptr inbounds float, float* %tmp21654, i64 1
+  %tmp21656 = getelementptr inbounds float, float* %tmp21655, i64 1
+  %tmp21657 = getelementptr inbounds float, float* %tmp21656, i64 1
+  %tmp21658 = getelementptr inbounds float, float* %tmp21657, i64 1
+  %tmp21659 = getelementptr inbounds float, float* %tmp21658, i64 1
+  %tmp21660 = getelementptr inbounds float, float* %tmp21659, i64 1
+  %tmp21661 = getelementptr inbounds float, float* %tmp21660, i64 1
+  %tmp21662 = getelementptr inbounds float, float* %tmp21661, i64 1
+  %tmp21663 = getelementptr inbounds float, float* %tmp21662, i64 1
+  %tmp21664 = getelementptr inbounds float, float* %tmp21663, i64 1
+  %tmp21665 = getelementptr inbounds float, float* %tmp21664, i64 1
+  %tmp21666 = getelementptr inbounds float, float* %tmp21665, i64 1
+  %tmp21667 = getelementptr inbounds float, float* %tmp21666, i64 1
+  %tmp21668 = getelementptr inbounds float, float* %tmp21667, i64 1
+  %tmp21669 = getelementptr inbounds float, float* %tmp21668, i64 1
+  %tmp21670 = getelementptr inbounds float, float* %tmp21669, i64 1
+  %tmp21671 = getelementptr inbounds float, float* %tmp21670, i64 1
+  %tmp21672 = getelementptr inbounds float, float* %tmp21671, i64 1
+  %tmp21673 = getelementptr inbounds float, float* %tmp21672, i64 1
+  %tmp21674 = getelementptr inbounds float, float* %tmp21673, i64 1
+  %tmp21675 = getelementptr inbounds float, float* %tmp21674, i64 1
+  %tmp21676 = getelementptr inbounds float, float* %tmp21675, i64 1
+  %tmp21677 = getelementptr inbounds float, float* %tmp21676, i64 1
+  %tmp21678 = getelementptr inbounds float, float* %tmp21677, i64 1
+  %tmp21679 = getelementptr inbounds float, float* %tmp21678, i64 1
+  %tmp21680 = getelementptr inbounds float, float* %tmp21679, i64 1
+  %tmp21681 = getelementptr inbounds float, float* %tmp21680, i64 1
+  %tmp21682 = getelementptr inbounds float, float* %tmp21681, i64 1
+  %tmp21683 = getelementptr inbounds float, float* %tmp21682, i64 1
+  %tmp21684 = getelementptr inbounds float, float* %tmp21683, i64 1
+  %tmp21685 = getelementptr inbounds float, float* %tmp21684, i64 1
+  %tmp21686 = getelementptr inbounds float, float* %tmp21685, i64 1
+  %tmp21687 = getelementptr inbounds float, float* %tmp21686, i64 1
+  %tmp21688 = getelementptr inbounds float, float* %tmp21687, i64 1
+  %tmp21689 = getelementptr inbounds float, float* %tmp21688, i64 1
+  %tmp21690 = getelementptr inbounds float, float* %tmp21689, i64 1
+  %tmp21691 = getelementptr inbounds float, float* %tmp21690, i64 1
+  %tmp21692 = getelementptr inbounds float, float* %tmp21691, i64 1
+  %tmp21693 = getelementptr inbounds float, float* %tmp21692, i64 1
+  %tmp21694 = getelementptr inbounds float, float* %tmp21693, i64 1
+  %tmp21695 = getelementptr inbounds float, float* %tmp21694, i64 1
+  %tmp21696 = getelementptr inbounds float, float* %tmp21695, i64 1
+  %tmp21697 = getelementptr inbounds float, float* %tmp21696, i64 1
+  %tmp21698 = getelementptr inbounds float, float* %tmp21697, i64 1
+  %tmp21699 = getelementptr inbounds float, float* %tmp21698, i64 1
+  %tmp21700 = getelementptr inbounds float, float* %tmp21699, i64 1
+  %tmp21701 = getelementptr inbounds float, float* %tmp21700, i64 1
+  %tmp21702 = getelementptr inbounds float, float* %tmp21701, i64 1
+  %tmp21703 = getelementptr inbounds float, float* %tmp21702, i64 1
+  %tmp21704 = getelementptr inbounds float, float* %tmp21703, i64 1
+  %tmp21705 = getelementptr inbounds float, float* %tmp21704, i64 1
+  %tmp21706 = getelementptr inbounds float, float* %tmp21705, i64 1
+  %tmp21707 = getelementptr inbounds float, float* %tmp21706, i64 1
+  %tmp21708 = getelementptr inbounds float, float* %tmp21707, i64 1
+  %tmp21709 = getelementptr inbounds float, float* %tmp21708, i64 1
+  %tmp21710 = getelementptr inbounds float, float* %tmp21709, i64 1
+  %tmp21711 = getelementptr inbounds float, float* %tmp21710, i64 1
+  %tmp21712 = getelementptr inbounds float, float* %tmp21711, i64 1
+  %tmp21713 = getelementptr inbounds float, float* %tmp21712, i64 1
+  %tmp21714 = getelementptr inbounds float, float* %tmp21713, i64 1
+  %tmp21715 = getelementptr inbounds float, float* %tmp21714, i64 1
+  %tmp21716 = getelementptr inbounds float, float* %tmp21715, i64 1
+  %tmp21717 = getelementptr inbounds float, float* %tmp21716, i64 1
+  %tmp21718 = getelementptr inbounds float, float* %tmp21717, i64 1
+  %tmp21719 = getelementptr inbounds float, float* %tmp21718, i64 1
+  %tmp21720 = getelementptr inbounds float, float* %tmp21719, i64 1
+  %tmp21721 = getelementptr inbounds float, float* %tmp21720, i64 1
+  %tmp21722 = getelementptr inbounds float, float* %tmp21721, i64 1
+  %tmp21723 = getelementptr inbounds float, float* %tmp21722, i64 1
+  %tmp21724 = getelementptr inbounds float, float* %tmp21723, i64 1
+  %tmp21725 = getelementptr inbounds float, float* %tmp21724, i64 1
+  %tmp21726 = getelementptr inbounds float, float* %tmp21725, i64 1
+  %tmp21727 = getelementptr inbounds float, float* %tmp21726, i64 1
+  %tmp21728 = getelementptr inbounds float, float* %tmp21727, i64 1
+  %tmp21729 = getelementptr inbounds float, float* %tmp21728, i64 1
+  %tmp21730 = getelementptr inbounds float, float* %tmp21729, i64 1
+  %tmp21731 = getelementptr inbounds float, float* %tmp21730, i64 1
+  %tmp21732 = getelementptr inbounds float, float* %tmp21731, i64 1
+  %tmp21733 = getelementptr inbounds float, float* %tmp21732, i64 1
+  %tmp21734 = getelementptr inbounds float, float* %tmp21733, i64 1
+  %tmp21735 = getelementptr inbounds float, float* %tmp21734, i64 1
+  %tmp21736 = getelementptr inbounds float, float* %tmp21735, i64 1
+  %tmp21737 = getelementptr inbounds float, float* %tmp21736, i64 1
+  %tmp21738 = getelementptr inbounds float, float* %tmp21737, i64 1
+  %tmp21739 = getelementptr inbounds float, float* %tmp21738, i64 1
+  %tmp21740 = getelementptr inbounds float, float* %tmp21739, i64 1
+  %tmp21741 = getelementptr inbounds float, float* %tmp21740, i64 1
+  %tmp21742 = getelementptr inbounds float, float* %tmp21741, i64 1
+  %tmp21743 = getelementptr inbounds float, float* %tmp21742, i64 1
+  %tmp21744 = getelementptr inbounds float, float* %tmp21743, i64 1
+  %tmp21745 = getelementptr inbounds float, float* %tmp21744, i64 1
+  %tmp21746 = getelementptr inbounds float, float* %tmp21745, i64 1
+  %tmp21747 = getelementptr inbounds float, float* %tmp21746, i64 1
+  %tmp21748 = getelementptr inbounds float, float* %tmp21747, i64 1
+  %tmp21749 = getelementptr inbounds float, float* %tmp21748, i64 1
+  %tmp21750 = getelementptr inbounds float, float* %tmp21749, i64 1
+  %tmp21751 = getelementptr inbounds float, float* %tmp21750, i64 1
+  %tmp21752 = getelementptr inbounds float, float* %tmp21751, i64 1
+  %tmp21753 = getelementptr inbounds float, float* %tmp21752, i64 1
+  %tmp21754 = getelementptr inbounds float, float* %tmp21753, i64 1
+  %tmp21755 = getelementptr inbounds float, float* %tmp21754, i64 1
+  %tmp21756 = getelementptr inbounds float, float* %tmp21755, i64 1
+  %tmp21757 = getelementptr inbounds float, float* %tmp21756, i64 1
+  %tmp21758 = getelementptr inbounds float, float* %tmp21757, i64 1
+  %tmp21759 = getelementptr inbounds float, float* %tmp21758, i64 1
+  %tmp21760 = getelementptr inbounds float, float* %tmp21759, i64 1
+  %tmp21761 = getelementptr inbounds float, float* %tmp21760, i64 1
+  %tmp21762 = getelementptr inbounds float, float* %tmp21761, i64 1
+  %tmp21763 = getelementptr inbounds float, float* %tmp21762, i64 1
+  %tmp21764 = getelementptr inbounds float, float* %tmp21763, i64 1
+  %tmp21765 = getelementptr inbounds float, float* %tmp21764, i64 1
+  %tmp21766 = getelementptr inbounds float, float* %tmp21765, i64 1
+  %tmp21767 = getelementptr inbounds float, float* %tmp21766, i64 1
+  %tmp21768 = getelementptr inbounds float, float* %tmp21767, i64 1
+  %tmp21769 = getelementptr inbounds float, float* %tmp21768, i64 1
+  %tmp21770 = getelementptr inbounds float, float* %tmp21769, i64 1
+  %tmp21771 = getelementptr inbounds float, float* %tmp21770, i64 1
+  %tmp21772 = getelementptr inbounds float, float* %tmp21771, i64 1
+  %tmp21773 = getelementptr inbounds float, float* %tmp21772, i64 1
+  %tmp21774 = getelementptr inbounds float, float* %tmp21773, i64 1
+  %tmp21775 = getelementptr inbounds float, float* %tmp21774, i64 1
+  %tmp21776 = getelementptr inbounds float, float* %tmp21775, i64 1
+  %tmp21777 = getelementptr inbounds float, float* %tmp21776, i64 1
+  %tmp21778 = getelementptr inbounds float, float* %tmp21777, i64 1
+  %tmp21779 = getelementptr inbounds float, float* %tmp21778, i64 1
+  %tmp21780 = getelementptr inbounds float, float* %tmp21779, i64 1
+  %tmp21781 = getelementptr inbounds float, float* %tmp21780, i64 1
+  %tmp21782 = getelementptr inbounds float, float* %tmp21781, i64 1
+  %tmp21783 = getelementptr inbounds float, float* %tmp21782, i64 1
+  %tmp21784 = getelementptr inbounds float, float* %tmp21783, i64 1
+  %tmp21785 = getelementptr inbounds float, float* %tmp21784, i64 1
+  %tmp21786 = getelementptr inbounds float, float* %tmp21785, i64 1
+  %tmp21787 = getelementptr inbounds float, float* %tmp21786, i64 1
+  %tmp21788 = getelementptr inbounds float, float* %tmp21787, i64 1
+  %tmp21789 = getelementptr inbounds float, float* %tmp21788, i64 1
+  %tmp21790 = getelementptr inbounds float, float* %tmp21789, i64 1
+  %tmp21791 = getelementptr inbounds float, float* %tmp21790, i64 1
+  %tmp21792 = getelementptr inbounds float, float* %tmp21791, i64 1
+  %tmp21793 = getelementptr inbounds float, float* %tmp21792, i64 1
+  %tmp21794 = getelementptr inbounds float, float* %tmp21793, i64 1
+  %tmp21795 = getelementptr inbounds float, float* %tmp21794, i64 1
+  %tmp21796 = getelementptr inbounds float, float* %tmp21795, i64 1
+  %tmp21797 = getelementptr inbounds float, float* %tmp21796, i64 1
+  %tmp21798 = getelementptr inbounds float, float* %tmp21797, i64 1
+  %tmp21799 = getelementptr inbounds float, float* %tmp21798, i64 1
+  %tmp21800 = getelementptr inbounds float, float* %tmp21799, i64 1
+  %tmp21801 = getelementptr inbounds float, float* %tmp21800, i64 1
+  %tmp21802 = getelementptr inbounds float, float* %tmp21801, i64 1
+  %tmp21803 = getelementptr inbounds float, float* %tmp21802, i64 1
+  %tmp21804 = getelementptr inbounds float, float* %tmp21803, i64 1
+  %tmp21805 = getelementptr inbounds float, float* %tmp21804, i64 1
+  %tmp21806 = getelementptr inbounds float, float* %tmp21805, i64 1
+  %tmp21807 = getelementptr inbounds float, float* %tmp21806, i64 1
+  %tmp21808 = getelementptr inbounds float, float* %tmp21807, i64 1
+  %tmp21809 = getelementptr inbounds float, float* %tmp21808, i64 1
+  %tmp21810 = getelementptr inbounds float, float* %tmp21809, i64 1
+  %tmp21811 = getelementptr inbounds float, float* %tmp21810, i64 1
+  %tmp21812 = getelementptr inbounds float, float* %tmp21811, i64 1
+  %tmp21813 = getelementptr inbounds float, float* %tmp21812, i64 1
+  %tmp21814 = getelementptr inbounds float, float* %tmp21813, i64 1
+  %tmp21815 = getelementptr inbounds float, float* %tmp21814, i64 1
+  %tmp21816 = getelementptr inbounds float, float* %tmp21815, i64 1
+  %tmp21817 = getelementptr inbounds float, float* %tmp21816, i64 1
+  %tmp21818 = getelementptr inbounds float, float* %tmp21817, i64 1
+  %tmp21819 = getelementptr inbounds float, float* %tmp21818, i64 1
+  %tmp21820 = getelementptr inbounds float, float* %tmp21819, i64 1
+  %tmp21821 = getelementptr inbounds float, float* %tmp21820, i64 1
+  %tmp21822 = getelementptr inbounds float, float* %tmp21821, i64 1
+  %tmp21823 = getelementptr inbounds float, float* %tmp21822, i64 1
+  %tmp21824 = getelementptr inbounds float, float* %tmp21823, i64 1
+  %tmp21825 = getelementptr inbounds float, float* %tmp21824, i64 1
+  %tmp21826 = getelementptr inbounds float, float* %tmp21825, i64 1
+  %tmp21827 = getelementptr inbounds float, float* %tmp21826, i64 1
+  %tmp21828 = getelementptr inbounds float, float* %tmp21827, i64 1
+  %tmp21829 = getelementptr inbounds float, float* %tmp21828, i64 1
+  %tmp21830 = getelementptr inbounds float, float* %tmp21829, i64 1
+  %tmp21831 = getelementptr inbounds float, float* %tmp21830, i64 1
+  %tmp21832 = getelementptr inbounds float, float* %tmp21831, i64 1
+  %tmp21833 = getelementptr inbounds float, float* %tmp21832, i64 1
+  %tmp21834 = getelementptr inbounds float, float* %tmp21833, i64 1
+  %tmp21835 = getelementptr inbounds float, float* %tmp21834, i64 1
+  %tmp21836 = getelementptr inbounds float, float* %tmp21835, i64 1
+  %tmp21837 = getelementptr inbounds float, float* %tmp21836, i64 1
+  %tmp21838 = getelementptr inbounds float, float* %tmp21837, i64 1
+  %tmp21839 = getelementptr inbounds float, float* %tmp21838, i64 1
+  %tmp21840 = getelementptr inbounds float, float* %tmp21839, i64 1
+  %tmp21841 = getelementptr inbounds float, float* %tmp21840, i64 1
+  %tmp21842 = getelementptr inbounds float, float* %tmp21841, i64 1
+  %tmp21843 = getelementptr inbounds float, float* %tmp21842, i64 1
+  %tmp21844 = getelementptr inbounds float, float* %tmp21843, i64 1
+  %tmp21845 = getelementptr inbounds float, float* %tmp21844, i64 1
+  %tmp21846 = getelementptr inbounds float, float* %tmp21845, i64 1
+  %tmp21847 = getelementptr inbounds float, float* %tmp21846, i64 1
+  %tmp21848 = getelementptr inbounds float, float* %tmp21847, i64 1
+  %tmp21849 = getelementptr inbounds float, float* %tmp21848, i64 1
+  %tmp21850 = getelementptr inbounds float, float* %tmp21849, i64 1
+  %tmp21851 = getelementptr inbounds float, float* %tmp21850, i64 1
+  %tmp21852 = getelementptr inbounds float, float* %tmp21851, i64 1
+  %tmp21853 = getelementptr inbounds float, float* %tmp21852, i64 1
+  %tmp21854 = getelementptr inbounds float, float* %tmp21853, i64 1
+  %tmp21855 = getelementptr inbounds float, float* %tmp21854, i64 1
+  %tmp21856 = getelementptr inbounds float, float* %tmp21855, i64 1
+  %tmp21857 = getelementptr inbounds float, float* %tmp21856, i64 1
+  %tmp21858 = getelementptr inbounds float, float* %tmp21857, i64 1
+  %tmp21859 = getelementptr inbounds float, float* %tmp21858, i64 1
+  %tmp21860 = getelementptr inbounds float, float* %tmp21859, i64 1
+  %tmp21861 = getelementptr inbounds float, float* %tmp21860, i64 1
+  %tmp21862 = getelementptr inbounds float, float* %tmp21861, i64 1
+  %tmp21863 = getelementptr inbounds float, float* %tmp21862, i64 1
+  %tmp21864 = getelementptr inbounds float, float* %tmp21863, i64 1
+  %tmp21865 = getelementptr inbounds float, float* %tmp21864, i64 1
+  %tmp21866 = getelementptr inbounds float, float* %tmp21865, i64 1
+  %tmp21867 = getelementptr inbounds float, float* %tmp21866, i64 1
+  %tmp21868 = getelementptr inbounds float, float* %tmp21867, i64 1
+  %tmp21869 = getelementptr inbounds float, float* %tmp21868, i64 1
+  %tmp21870 = getelementptr inbounds float, float* %tmp21869, i64 1
+  %tmp21871 = getelementptr inbounds float, float* %tmp21870, i64 1
+  %tmp21872 = getelementptr inbounds float, float* %tmp21871, i64 1
+  %tmp21873 = getelementptr inbounds float, float* %tmp21872, i64 1
+  %tmp21874 = getelementptr inbounds float, float* %tmp21873, i64 1
+  %tmp21875 = getelementptr inbounds float, float* %tmp21874, i64 1
+  %tmp21876 = getelementptr inbounds float, float* %tmp21875, i64 1
+  %tmp21877 = getelementptr inbounds float, float* %tmp21876, i64 1
+  %tmp21878 = getelementptr inbounds float, float* %tmp21877, i64 1
+  %tmp21879 = getelementptr inbounds float, float* %tmp21878, i64 1
+  %tmp21880 = getelementptr inbounds float, float* %tmp21879, i64 1
+  %tmp21881 = getelementptr inbounds float, float* %tmp21880, i64 1
+  %tmp21882 = getelementptr inbounds float, float* %tmp21881, i64 1
+  %tmp21883 = getelementptr inbounds float, float* %tmp21882, i64 1
+  %tmp21884 = getelementptr inbounds float, float* %tmp21883, i64 1
+  %tmp21885 = getelementptr inbounds float, float* %tmp21884, i64 1
+  %tmp21886 = getelementptr inbounds float, float* %tmp21885, i64 1
+  %tmp21887 = getelementptr inbounds float, float* %tmp21886, i64 1
+  %tmp21888 = getelementptr inbounds float, float* %tmp21887, i64 1
+  %tmp21889 = getelementptr inbounds float, float* %tmp21888, i64 1
+  %tmp21890 = getelementptr inbounds float, float* %tmp21889, i64 1
+  %tmp21891 = getelementptr inbounds float, float* %tmp21890, i64 1
+  %tmp21892 = getelementptr inbounds float, float* %tmp21891, i64 1
+  %tmp21893 = getelementptr inbounds float, float* %tmp21892, i64 1
+  %tmp21894 = getelementptr inbounds float, float* %tmp21893, i64 1
+  %tmp21895 = getelementptr inbounds float, float* %tmp21894, i64 1
+  %tmp21896 = getelementptr inbounds float, float* %tmp21895, i64 1
+  %tmp21897 = getelementptr inbounds float, float* %tmp21896, i64 1
+  %tmp21898 = getelementptr inbounds float, float* %tmp21897, i64 1
+  %tmp21899 = getelementptr inbounds float, float* %tmp21898, i64 1
+  %tmp21900 = getelementptr inbounds float, float* %tmp21899, i64 1
+  %tmp21901 = getelementptr inbounds float, float* %tmp21900, i64 1
+  %tmp21902 = getelementptr inbounds float, float* %tmp21901, i64 1
+  %tmp21903 = getelementptr inbounds float, float* %tmp21902, i64 1
+  %tmp21904 = getelementptr inbounds float, float* %tmp21903, i64 1
+  %tmp21905 = getelementptr inbounds float, float* %tmp21904, i64 1
+  %tmp21906 = getelementptr inbounds float, float* %tmp21905, i64 1
+  %tmp21907 = getelementptr inbounds float, float* %tmp21906, i64 1
+  %tmp21908 = getelementptr inbounds float, float* %tmp21907, i64 1
+  %tmp21909 = getelementptr inbounds float, float* %tmp21908, i64 1
+  %tmp21910 = getelementptr inbounds float, float* %tmp21909, i64 1
+  %tmp21911 = getelementptr inbounds float, float* %tmp21910, i64 1
+  %tmp21912 = getelementptr inbounds float, float* %tmp21911, i64 1
+  %tmp21913 = getelementptr inbounds float, float* %tmp21912, i64 1
+  %tmp21914 = getelementptr inbounds float, float* %tmp21913, i64 1
+  %tmp21915 = getelementptr inbounds float, float* %tmp21914, i64 1
+  %tmp21916 = getelementptr inbounds float, float* %tmp21915, i64 1
+  %tmp21917 = getelementptr inbounds float, float* %tmp21916, i64 1
+  %tmp21918 = getelementptr inbounds float, float* %tmp21917, i64 1
+  %tmp21919 = getelementptr inbounds float, float* %tmp21918, i64 1
+  %tmp21920 = getelementptr inbounds float, float* %tmp21919, i64 1
+  %tmp21921 = getelementptr inbounds float, float* %tmp21920, i64 1
+  %tmp21922 = getelementptr inbounds float, float* %tmp21921, i64 1
+  %tmp21923 = getelementptr inbounds float, float* %tmp21922, i64 1
+  %tmp21924 = getelementptr inbounds float, float* %tmp21923, i64 1
+  %tmp21925 = getelementptr inbounds float, float* %tmp21924, i64 1
+  %tmp21926 = getelementptr inbounds float, float* %tmp21925, i64 1
+  %tmp21927 = getelementptr inbounds float, float* %tmp21926, i64 1
+  %tmp21928 = getelementptr inbounds float, float* %tmp21927, i64 1
+  %tmp21929 = getelementptr inbounds float, float* %tmp21928, i64 1
+  %tmp21930 = getelementptr inbounds float, float* %tmp21929, i64 1
+  %tmp21931 = getelementptr inbounds float, float* %tmp21930, i64 1
+  %tmp21932 = getelementptr inbounds float, float* %tmp21931, i64 1
+  %tmp21933 = getelementptr inbounds float, float* %tmp21932, i64 1
+  %tmp21934 = getelementptr inbounds float, float* %tmp21933, i64 1
+  %tmp21935 = getelementptr inbounds float, float* %tmp21934, i64 1
+  %tmp21936 = getelementptr inbounds float, float* %tmp21935, i64 1
+  %tmp21937 = getelementptr inbounds float, float* %tmp21936, i64 1
+  %tmp21938 = getelementptr inbounds float, float* %tmp21937, i64 1
+  %tmp21939 = getelementptr inbounds float, float* %tmp21938, i64 1
+  %tmp21940 = getelementptr inbounds float, float* %tmp21939, i64 1
+  %tmp21941 = getelementptr inbounds float, float* %tmp21940, i64 1
+  %tmp21942 = getelementptr inbounds float, float* %tmp21941, i64 1
+  %tmp21943 = getelementptr inbounds float, float* %tmp21942, i64 1
+  %tmp21944 = getelementptr inbounds float, float* %tmp21943, i64 1
+  %tmp21945 = getelementptr inbounds float, float* %tmp21944, i64 1
+  %tmp21946 = getelementptr inbounds float, float* %tmp21945, i64 1
+  %tmp21947 = getelementptr inbounds float, float* %tmp21946, i64 1
+  %tmp21948 = getelementptr inbounds float, float* %tmp21947, i64 1
+  %tmp21949 = getelementptr inbounds float, float* %tmp21948, i64 1
+  %tmp21950 = getelementptr inbounds float, float* %tmp21949, i64 1
+  %tmp21951 = getelementptr inbounds float, float* %tmp21950, i64 1
+  %tmp21952 = getelementptr inbounds float, float* %tmp21951, i64 1
+  %tmp21953 = getelementptr inbounds float, float* %tmp21952, i64 1
+  %tmp21954 = getelementptr inbounds float, float* %tmp21953, i64 1
+  %tmp21955 = getelementptr inbounds float, float* %tmp21954, i64 1
+  %tmp21956 = getelementptr inbounds float, float* %tmp21955, i64 1
+  %tmp21957 = getelementptr inbounds float, float* %tmp21956, i64 1
+  %tmp21958 = getelementptr inbounds float, float* %tmp21957, i64 1
+  %tmp21959 = getelementptr inbounds float, float* %tmp21958, i64 1
+  %tmp21960 = getelementptr inbounds float, float* %tmp21959, i64 1
+  %tmp21961 = getelementptr inbounds float, float* %tmp21960, i64 1
+  %tmp21962 = getelementptr inbounds float, float* %tmp21961, i64 1
+  %tmp21963 = getelementptr inbounds float, float* %tmp21962, i64 1
+  %tmp21964 = getelementptr inbounds float, float* %tmp21963, i64 1
+  %tmp21965 = getelementptr inbounds float, float* %tmp21964, i64 1
+  %tmp21966 = getelementptr inbounds float, float* %tmp21965, i64 1
+  %tmp21967 = getelementptr inbounds float, float* %tmp21966, i64 1
+  %tmp21968 = getelementptr inbounds float, float* %tmp21967, i64 1
+  %tmp21969 = getelementptr inbounds float, float* %tmp21968, i64 1
+  %tmp21970 = getelementptr inbounds float, float* %tmp21969, i64 1
+  %tmp21971 = getelementptr inbounds float, float* %tmp21970, i64 1
+  %tmp21972 = getelementptr inbounds float, float* %tmp21971, i64 1
+  %tmp21973 = getelementptr inbounds float, float* %tmp21972, i64 1
+  %tmp21974 = getelementptr inbounds float, float* %tmp21973, i64 1
+  %tmp21975 = getelementptr inbounds float, float* %tmp21974, i64 1
+  %tmp21976 = getelementptr inbounds float, float* %tmp21975, i64 1
+  %tmp21977 = getelementptr inbounds float, float* %tmp21976, i64 1
+  %tmp21978 = getelementptr inbounds float, float* %tmp21977, i64 1
+  %tmp21979 = getelementptr inbounds float, float* %tmp21978, i64 1
+  %tmp21980 = getelementptr inbounds float, float* %tmp21979, i64 1
+  %tmp21981 = getelementptr inbounds float, float* %tmp21980, i64 1
+  %tmp21982 = getelementptr inbounds float, float* %tmp21981, i64 1
+  %tmp21983 = getelementptr inbounds float, float* %tmp21982, i64 1
+  %tmp21984 = getelementptr inbounds float, float* %tmp21983, i64 1
+  %tmp21985 = getelementptr inbounds float, float* %tmp21984, i64 1
+  %tmp21986 = getelementptr inbounds float, float* %tmp21985, i64 1
+  %tmp21987 = getelementptr inbounds float, float* %tmp21986, i64 1
+  %tmp21988 = getelementptr inbounds float, float* %tmp21987, i64 1
+  %tmp21989 = getelementptr inbounds float, float* %tmp21988, i64 1
+  %tmp21990 = getelementptr inbounds float, float* %tmp21989, i64 1
+  %tmp21991 = getelementptr inbounds float, float* %tmp21990, i64 1
+  %tmp21992 = getelementptr inbounds float, float* %tmp21991, i64 1
+  %tmp21993 = getelementptr inbounds float, float* %tmp21992, i64 1
+  %tmp21994 = getelementptr inbounds float, float* %tmp21993, i64 1
+  %tmp21995 = getelementptr inbounds float, float* %tmp21994, i64 1
+  %tmp21996 = getelementptr inbounds float, float* %tmp21995, i64 1
+  %tmp21997 = getelementptr inbounds float, float* %tmp21996, i64 1
+  %tmp21998 = getelementptr inbounds float, float* %tmp21997, i64 1
+  %tmp21999 = getelementptr inbounds float, float* %tmp21998, i64 1
+  %tmp22000 = getelementptr inbounds float, float* %tmp21999, i64 1
+  %tmp22001 = getelementptr inbounds float, float* %tmp22000, i64 1
+  %tmp22002 = getelementptr inbounds float, float* %tmp22001, i64 1
+  %tmp22003 = getelementptr inbounds float, float* %tmp22002, i64 1
+  %tmp22004 = getelementptr inbounds float, float* %tmp22003, i64 1
+  %tmp22005 = getelementptr inbounds float, float* %tmp22004, i64 1
+  %tmp22006 = getelementptr inbounds float, float* %tmp22005, i64 1
+  %tmp22007 = getelementptr inbounds float, float* %tmp22006, i64 1
+  %tmp22008 = getelementptr inbounds float, float* %tmp22007, i64 1
+  %tmp22009 = getelementptr inbounds float, float* %tmp22008, i64 1
+  %tmp22010 = getelementptr inbounds float, float* %tmp22009, i64 1
+  %tmp22011 = getelementptr inbounds float, float* %tmp22010, i64 1
+  %tmp22012 = getelementptr inbounds float, float* %tmp22011, i64 1
+  %tmp22013 = getelementptr inbounds float, float* %tmp22012, i64 1
+  %tmp22014 = getelementptr inbounds float, float* %tmp22013, i64 1
+  %tmp22015 = getelementptr inbounds float, float* %tmp22014, i64 1
+  %tmp22016 = getelementptr inbounds float, float* %tmp22015, i64 1
+  %tmp22017 = getelementptr inbounds float, float* %tmp22016, i64 1
+  %tmp22018 = getelementptr inbounds float, float* %tmp22017, i64 1
+  %tmp22019 = getelementptr inbounds float, float* %tmp22018, i64 1
+  %tmp22020 = getelementptr inbounds float, float* %tmp22019, i64 1
+  %tmp22021 = getelementptr inbounds float, float* %tmp22020, i64 1
+  %tmp22022 = getelementptr inbounds float, float* %tmp22021, i64 1
+  %tmp22023 = getelementptr inbounds float, float* %tmp22022, i64 1
+  %tmp22024 = getelementptr inbounds float, float* %tmp22023, i64 1
+  %tmp22025 = getelementptr inbounds float, float* %tmp22024, i64 1
+  %tmp22026 = getelementptr inbounds float, float* %tmp22025, i64 1
+  %tmp22027 = getelementptr inbounds float, float* %tmp22026, i64 1
+  %tmp22028 = getelementptr inbounds float, float* %tmp22027, i64 1
+  %tmp22029 = getelementptr inbounds float, float* %tmp22028, i64 1
+  %tmp22030 = getelementptr inbounds float, float* %tmp22029, i64 1
+  %tmp22031 = getelementptr inbounds float, float* %tmp22030, i64 1
+  %tmp22032 = getelementptr inbounds float, float* %tmp22031, i64 1
+  %tmp22033 = getelementptr inbounds float, float* %tmp22032, i64 1
+  %tmp22034 = getelementptr inbounds float, float* %tmp22033, i64 1
+  %tmp22035 = getelementptr inbounds float, float* %tmp22034, i64 1
+  %tmp22036 = getelementptr inbounds float, float* %tmp22035, i64 1
+  %tmp22037 = getelementptr inbounds float, float* %tmp22036, i64 1
+  %tmp22038 = getelementptr inbounds float, float* %tmp22037, i64 1
+  %tmp22039 = getelementptr inbounds float, float* %tmp22038, i64 1
+  %tmp22040 = getelementptr inbounds float, float* %tmp22039, i64 1
+  %tmp22041 = getelementptr inbounds float, float* %tmp22040, i64 1
+  %tmp22042 = getelementptr inbounds float, float* %tmp22041, i64 1
+  %tmp22043 = getelementptr inbounds float, float* %tmp22042, i64 1
+  %tmp22044 = getelementptr inbounds float, float* %tmp22043, i64 1
+  %tmp22045 = getelementptr inbounds float, float* %tmp22044, i64 1
+  %tmp22046 = getelementptr inbounds float, float* %tmp22045, i64 1
+  %tmp22047 = getelementptr inbounds float, float* %tmp22046, i64 1
+  %tmp22048 = getelementptr inbounds float, float* %tmp22047, i64 1
+  %tmp22049 = getelementptr inbounds float, float* %tmp22048, i64 1
+  %tmp22050 = getelementptr inbounds float, float* %tmp22049, i64 1
+  %tmp22051 = getelementptr inbounds float, float* %tmp22050, i64 1
+  %tmp22052 = getelementptr inbounds float, float* %tmp22051, i64 1
+  %tmp22053 = getelementptr inbounds float, float* %tmp22052, i64 1
+  %tmp22054 = getelementptr inbounds float, float* %tmp22053, i64 1
+  %tmp22055 = getelementptr inbounds float, float* %tmp22054, i64 1
+  %tmp22056 = getelementptr inbounds float, float* %tmp22055, i64 1
+  %tmp22057 = getelementptr inbounds float, float* %tmp22056, i64 1
+  %tmp22058 = getelementptr inbounds float, float* %tmp22057, i64 1
+  %tmp22059 = getelementptr inbounds float, float* %tmp22058, i64 1
+  %tmp22060 = getelementptr inbounds float, float* %tmp22059, i64 1
+  %tmp22061 = getelementptr inbounds float, float* %tmp22060, i64 1
+  %tmp22062 = getelementptr inbounds float, float* %tmp22061, i64 1
+  %tmp22063 = getelementptr inbounds float, float* %tmp22062, i64 1
+  %tmp22064 = getelementptr inbounds float, float* %tmp22063, i64 1
+  %tmp22065 = getelementptr inbounds float, float* %tmp22064, i64 1
+  %tmp22066 = getelementptr inbounds float, float* %tmp22065, i64 1
+  %tmp22067 = getelementptr inbounds float, float* %tmp22066, i64 1
+  %tmp22068 = getelementptr inbounds float, float* %tmp22067, i64 1
+  %tmp22069 = getelementptr inbounds float, float* %tmp22068, i64 1
+  %tmp22070 = getelementptr inbounds float, float* %tmp22069, i64 1
+  %tmp22071 = getelementptr inbounds float, float* %tmp22070, i64 1
+  %tmp22072 = getelementptr inbounds float, float* %tmp22071, i64 1
+  %tmp22073 = getelementptr inbounds float, float* %tmp22072, i64 1
+  %tmp22074 = getelementptr inbounds float, float* %tmp22073, i64 1
+  %tmp22075 = getelementptr inbounds float, float* %tmp22074, i64 1
+  %tmp22076 = getelementptr inbounds float, float* %tmp22075, i64 1
+  %tmp22077 = getelementptr inbounds float, float* %tmp22076, i64 1
+  %tmp22078 = getelementptr inbounds float, float* %tmp22077, i64 1
+  %tmp22079 = getelementptr inbounds float, float* %tmp22078, i64 1
+  %tmp22080 = getelementptr inbounds float, float* %tmp22079, i64 1
+  %tmp22081 = getelementptr inbounds float, float* %tmp22080, i64 1
+  %tmp22082 = getelementptr inbounds float, float* %tmp22081, i64 1
+  %tmp22083 = getelementptr inbounds float, float* %tmp22082, i64 1
+  %tmp22084 = getelementptr inbounds float, float* %tmp22083, i64 1
+  %tmp22085 = getelementptr inbounds float, float* %tmp22084, i64 1
+  %tmp22086 = getelementptr inbounds float, float* %tmp22085, i64 1
+  %tmp22087 = getelementptr inbounds float, float* %tmp22086, i64 1
+  %tmp22088 = getelementptr inbounds float, float* %tmp22087, i64 1
+  %tmp22089 = getelementptr inbounds float, float* %tmp22088, i64 1
+  %tmp22090 = getelementptr inbounds float, float* %tmp22089, i64 1
+  %tmp22091 = getelementptr inbounds float, float* %tmp22090, i64 1
+  %tmp22092 = getelementptr inbounds float, float* %tmp22091, i64 1
+  %tmp22093 = getelementptr inbounds float, float* %tmp22092, i64 1
+  %tmp22094 = getelementptr inbounds float, float* %tmp22093, i64 1
+  %tmp22095 = getelementptr inbounds float, float* %tmp22094, i64 1
+  %tmp22096 = getelementptr inbounds float, float* %tmp22095, i64 1
+  %tmp22097 = getelementptr inbounds float, float* %tmp22096, i64 1
+  %tmp22098 = getelementptr inbounds float, float* %tmp22097, i64 1
+  %tmp22099 = getelementptr inbounds float, float* %tmp22098, i64 1
+  %tmp22100 = getelementptr inbounds float, float* %tmp22099, i64 1
+  %tmp22101 = getelementptr inbounds float, float* %tmp22100, i64 1
+  %tmp22102 = getelementptr inbounds float, float* %tmp22101, i64 1
+  %tmp22103 = getelementptr inbounds float, float* %tmp22102, i64 1
+  %tmp22104 = getelementptr inbounds float, float* %tmp22103, i64 1
+  %tmp22105 = getelementptr inbounds float, float* %tmp22104, i64 1
+  %tmp22106 = getelementptr inbounds float, float* %tmp22105, i64 1
+  %tmp22107 = getelementptr inbounds float, float* %tmp22106, i64 1
+  %tmp22108 = getelementptr inbounds float, float* %tmp22107, i64 1
+  %tmp22109 = getelementptr inbounds float, float* %tmp22108, i64 1
+  %tmp22110 = getelementptr inbounds float, float* %tmp22109, i64 1
+  %tmp22111 = getelementptr inbounds float, float* %tmp22110, i64 1
+  %tmp22112 = getelementptr inbounds float, float* %tmp22111, i64 1
+  %tmp22113 = getelementptr inbounds float, float* %tmp22112, i64 1
+  %tmp22114 = getelementptr inbounds float, float* %tmp22113, i64 1
+  %tmp22115 = getelementptr inbounds float, float* %tmp22114, i64 1
+  %tmp22116 = getelementptr inbounds float, float* %tmp22115, i64 1
+  %tmp22117 = getelementptr inbounds float, float* %tmp22116, i64 1
+  %tmp22118 = getelementptr inbounds float, float* %tmp22117, i64 1
+  %tmp22119 = getelementptr inbounds float, float* %tmp22118, i64 1
+  %tmp22120 = getelementptr inbounds float, float* %tmp22119, i64 1
+  %tmp22121 = getelementptr inbounds float, float* %tmp22120, i64 1
+  %tmp22122 = getelementptr inbounds float, float* %tmp22121, i64 1
+  %tmp22123 = getelementptr inbounds float, float* %tmp22122, i64 1
+  %tmp22124 = getelementptr inbounds float, float* %tmp22123, i64 1
+  %tmp22125 = getelementptr inbounds float, float* %tmp22124, i64 1
+  %tmp22126 = getelementptr inbounds float, float* %tmp22125, i64 1
+  %tmp22127 = getelementptr inbounds float, float* %tmp22126, i64 1
+  %tmp22128 = getelementptr inbounds float, float* %tmp22127, i64 1
+  %tmp22129 = getelementptr inbounds float, float* %tmp22128, i64 1
+  %tmp22130 = getelementptr inbounds float, float* %tmp22129, i64 1
+  %tmp22131 = getelementptr inbounds float, float* %tmp22130, i64 1
+  %tmp22132 = getelementptr inbounds float, float* %tmp22131, i64 1
+  %tmp22133 = getelementptr inbounds float, float* %tmp22132, i64 1
+  %tmp22134 = getelementptr inbounds float, float* %tmp22133, i64 1
+  %tmp22135 = getelementptr inbounds float, float* %tmp22134, i64 1
+  %tmp22136 = getelementptr inbounds float, float* %tmp22135, i64 1
+  %tmp22137 = getelementptr inbounds float, float* %tmp22136, i64 1
+  %tmp22138 = getelementptr inbounds float, float* %tmp22137, i64 1
+  %tmp22139 = getelementptr inbounds float, float* %tmp22138, i64 1
+  %tmp22140 = getelementptr inbounds float, float* %tmp22139, i64 1
+  %tmp22141 = getelementptr inbounds float, float* %tmp22140, i64 1
+  %tmp22142 = getelementptr inbounds float, float* %tmp22141, i64 1
+  %tmp22143 = getelementptr inbounds float, float* %tmp22142, i64 1
+  %tmp22144 = getelementptr inbounds float, float* %tmp22143, i64 1
+  %tmp22145 = getelementptr inbounds float, float* %tmp22144, i64 1
+  %tmp22146 = getelementptr inbounds float, float* %tmp22145, i64 1
+  %tmp22147 = getelementptr inbounds float, float* %tmp22146, i64 1
+  %tmp22148 = getelementptr inbounds float, float* %tmp22147, i64 1
+  %tmp22149 = getelementptr inbounds float, float* %tmp22148, i64 1
+  %tmp22150 = getelementptr inbounds float, float* %tmp22149, i64 1
+  %tmp22151 = getelementptr inbounds float, float* %tmp22150, i64 1
+  %tmp22152 = getelementptr inbounds float, float* %tmp22151, i64 1
+  %tmp22153 = getelementptr inbounds float, float* %tmp22152, i64 1
+  %tmp22154 = getelementptr inbounds float, float* %tmp22153, i64 1
+  %tmp22155 = getelementptr inbounds float, float* %tmp22154, i64 1
+  %tmp22156 = getelementptr inbounds float, float* %tmp22155, i64 1
+  %tmp22157 = getelementptr inbounds float, float* %tmp22156, i64 1
+  %tmp22158 = getelementptr inbounds float, float* %tmp22157, i64 1
+  %tmp22159 = getelementptr inbounds float, float* %tmp22158, i64 1
+  %tmp22160 = getelementptr inbounds float, float* %tmp22159, i64 1
+  %tmp22161 = getelementptr inbounds float, float* %tmp22160, i64 1
+  %tmp22162 = getelementptr inbounds float, float* %tmp22161, i64 1
+  %tmp22163 = getelementptr inbounds float, float* %tmp22162, i64 1
+  %tmp22164 = getelementptr inbounds float, float* %tmp22163, i64 1
+  %tmp22165 = getelementptr inbounds float, float* %tmp22164, i64 1
+  %tmp22166 = getelementptr inbounds float, float* %tmp22165, i64 1
+  %tmp22167 = getelementptr inbounds float, float* %tmp22166, i64 1
+  %tmp22168 = getelementptr inbounds float, float* %tmp22167, i64 1
+  %tmp22169 = getelementptr inbounds float, float* %tmp22168, i64 1
+  %tmp22170 = getelementptr inbounds float, float* %tmp22169, i64 1
+  %tmp22171 = getelementptr inbounds float, float* %tmp22170, i64 1
+  %tmp22172 = getelementptr inbounds float, float* %tmp22171, i64 1
+  %tmp22173 = getelementptr inbounds float, float* %tmp22172, i64 1
+  %tmp22174 = getelementptr inbounds float, float* %tmp22173, i64 1
+  %tmp22175 = getelementptr inbounds float, float* %tmp22174, i64 1
+  %tmp22176 = getelementptr inbounds float, float* %tmp22175, i64 1
+  %tmp22177 = getelementptr inbounds float, float* %tmp22176, i64 1
+  %tmp22178 = getelementptr inbounds float, float* %tmp22177, i64 1
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+  %tmp22490 = getelementptr inbounds float, float* %tmp22489, i64 1
+  %tmp22491 = getelementptr inbounds float, float* %tmp22490, i64 1
+  %tmp22492 = getelementptr inbounds float, float* %tmp22491, i64 1
+  %tmp22493 = getelementptr inbounds float, float* %tmp22492, i64 1
+  %tmp22494 = getelementptr inbounds float, float* %tmp22493, i64 1
+  %tmp22495 = getelementptr inbounds float, float* %tmp22494, i64 1
+  %tmp22496 = getelementptr inbounds float, float* %tmp22495, i64 1
+  %tmp22497 = getelementptr inbounds float, float* %tmp22496, i64 1
+  %tmp22498 = getelementptr inbounds float, float* %tmp22497, i64 1
+  %tmp22499 = getelementptr inbounds float, float* %tmp22498, i64 1
+  %tmp22500 = getelementptr inbounds float, float* %tmp22499, i64 1
+  %tmp22501 = getelementptr inbounds float, float* %tmp22500, i64 1
+  %tmp22502 = getelementptr inbounds float, float* %tmp22501, i64 1
+  %tmp22503 = getelementptr inbounds float, float* %tmp22502, i64 1
+  %tmp22504 = getelementptr inbounds float, float* %tmp22503, i64 1
+  %tmp22505 = getelementptr inbounds float, float* %tmp22504, i64 1
+  %tmp22506 = getelementptr inbounds float, float* %tmp22505, i64 1
+  %tmp22507 = getelementptr inbounds float, float* %tmp22506, i64 1
+  %tmp22508 = getelementptr inbounds float, float* %tmp22507, i64 1
+  %tmp22509 = getelementptr inbounds float, float* %tmp22508, i64 1
+  %tmp22510 = getelementptr inbounds float, float* %tmp22509, i64 1
+  %tmp22511 = getelementptr inbounds float, float* %tmp22510, i64 1
+  %tmp22512 = getelementptr inbounds float, float* %tmp22511, i64 1
+  %tmp22513 = getelementptr inbounds float, float* %tmp22512, i64 1
+  %tmp22514 = getelementptr inbounds float, float* %tmp22513, i64 1
+  %tmp22515 = getelementptr inbounds float, float* %tmp22514, i64 1
+  %tmp22516 = getelementptr inbounds float, float* %tmp22515, i64 1
+  %tmp22517 = getelementptr inbounds float, float* %tmp22516, i64 1
+  %tmp22518 = getelementptr inbounds float, float* %tmp22517, i64 1
+  %tmp22519 = getelementptr inbounds float, float* %tmp22518, i64 1
+  %tmp22520 = getelementptr inbounds float, float* %tmp22519, i64 1
+  %tmp22521 = getelementptr inbounds float, float* %tmp22520, i64 1
+  %tmp22522 = getelementptr inbounds float, float* %tmp22521, i64 1
+  %tmp22523 = getelementptr inbounds float, float* %tmp22522, i64 1
+  %tmp22524 = getelementptr inbounds float, float* %tmp22523, i64 1
+  %tmp22525 = getelementptr inbounds float, float* %tmp22524, i64 1
+  %tmp22526 = getelementptr inbounds float, float* %tmp22525, i64 1
+  %tmp22527 = getelementptr inbounds float, float* %tmp22526, i64 1
+  %tmp22528 = getelementptr inbounds float, float* %tmp22527, i64 1
+  %tmp22529 = getelementptr inbounds float, float* %tmp22528, i64 1
+  %tmp22530 = getelementptr inbounds float, float* %tmp22529, i64 1
+  %tmp22531 = getelementptr inbounds float, float* %tmp22530, i64 1
+  %tmp22532 = getelementptr inbounds float, float* %tmp22531, i64 1
+  %tmp22533 = getelementptr inbounds float, float* %tmp22532, i64 1
+  %tmp22534 = getelementptr inbounds float, float* %tmp22533, i64 1
+  %tmp22535 = getelementptr inbounds float, float* %tmp22534, i64 1
+  %tmp22536 = getelementptr inbounds float, float* %tmp22535, i64 1
+  %tmp22537 = getelementptr inbounds float, float* %tmp22536, i64 1
+  %tmp22538 = getelementptr inbounds float, float* %tmp22537, i64 1
+  %tmp22539 = getelementptr inbounds float, float* %tmp22538, i64 1
+  %tmp22540 = getelementptr inbounds float, float* %tmp22539, i64 1
+  %tmp22541 = getelementptr inbounds float, float* %tmp22540, i64 1
+  %tmp22542 = getelementptr inbounds float, float* %tmp22541, i64 1
+  %tmp22543 = getelementptr inbounds float, float* %tmp22542, i64 1
+  %tmp22544 = getelementptr inbounds float, float* %tmp22543, i64 1
+  %tmp22545 = getelementptr inbounds float, float* %tmp22544, i64 1
+  %tmp22546 = getelementptr inbounds float, float* %tmp22545, i64 1
+  %tmp22547 = getelementptr inbounds float, float* %tmp22546, i64 1
+  %tmp22548 = getelementptr inbounds float, float* %tmp22547, i64 1
+  %tmp22549 = getelementptr inbounds float, float* %tmp22548, i64 1
+  %tmp22550 = getelementptr inbounds float, float* %tmp22549, i64 1
+  %tmp22551 = getelementptr inbounds float, float* %tmp22550, i64 1
+  %tmp22552 = getelementptr inbounds float, float* %tmp22551, i64 1
+  %tmp22553 = getelementptr inbounds float, float* %tmp22552, i64 1
+  %tmp22554 = getelementptr inbounds float, float* %tmp22553, i64 1
+  %tmp22555 = getelementptr inbounds float, float* %tmp22554, i64 1
+  %tmp22556 = getelementptr inbounds float, float* %tmp22555, i64 1
+  %tmp22557 = getelementptr inbounds float, float* %tmp22556, i64 1
+  %tmp22558 = getelementptr inbounds float, float* %tmp22557, i64 1
+  %tmp22559 = getelementptr inbounds float, float* %tmp22558, i64 1
+  %tmp22560 = getelementptr inbounds float, float* %tmp22559, i64 1
+  %tmp22561 = getelementptr inbounds float, float* %tmp22560, i64 1
+  %tmp22562 = getelementptr inbounds float, float* %tmp22561, i64 1
+  %tmp22563 = getelementptr inbounds float, float* %tmp22562, i64 1
+  %tmp22564 = getelementptr inbounds float, float* %tmp22563, i64 1
+  %tmp22565 = getelementptr inbounds float, float* %tmp22564, i64 1
+  %tmp22566 = getelementptr inbounds float, float* %tmp22565, i64 1
+  %tmp22567 = getelementptr inbounds float, float* %tmp22566, i64 1
+  %tmp22568 = getelementptr inbounds float, float* %tmp22567, i64 1
+  %tmp22569 = getelementptr inbounds float, float* %tmp22568, i64 1
+  %tmp22570 = getelementptr inbounds float, float* %tmp22569, i64 1
+  %tmp22571 = getelementptr inbounds float, float* %tmp22570, i64 1
+  %tmp22572 = getelementptr inbounds float, float* %tmp22571, i64 1
+  %tmp22573 = getelementptr inbounds float, float* %tmp22572, i64 1
+  %tmp22574 = getelementptr inbounds float, float* %tmp22573, i64 1
+  %tmp22575 = getelementptr inbounds float, float* %tmp22574, i64 1
+  %tmp22576 = getelementptr inbounds float, float* %tmp22575, i64 1
+  %tmp22577 = getelementptr inbounds float, float* %tmp22576, i64 1
+  %tmp22578 = getelementptr inbounds float, float* %tmp22577, i64 1
+  %tmp22579 = getelementptr inbounds float, float* %tmp22578, i64 1
+  %tmp22580 = getelementptr inbounds float, float* %tmp22579, i64 1
+  %tmp22581 = getelementptr inbounds float, float* %tmp22580, i64 1
+  %tmp22582 = getelementptr inbounds float, float* %tmp22581, i64 1
+  %tmp22583 = getelementptr inbounds float, float* %tmp22582, i64 1
+  %tmp22584 = getelementptr inbounds float, float* %tmp22583, i64 1
+  %tmp22585 = getelementptr inbounds float, float* %tmp22584, i64 1
+  %tmp22586 = getelementptr inbounds float, float* %tmp22585, i64 1
+  %tmp22587 = getelementptr inbounds float, float* %tmp22586, i64 1
+  %tmp22588 = getelementptr inbounds float, float* %tmp22587, i64 1
+  %tmp22589 = getelementptr inbounds float, float* %tmp22588, i64 1
+  %tmp22590 = getelementptr inbounds float, float* %tmp22589, i64 1
+  %tmp22591 = getelementptr inbounds float, float* %tmp22590, i64 1
+  %tmp22592 = getelementptr inbounds float, float* %tmp22591, i64 1
+  %tmp22593 = getelementptr inbounds float, float* %tmp22592, i64 1
+  %tmp22594 = getelementptr inbounds float, float* %tmp22593, i64 1
+  %tmp22595 = getelementptr inbounds float, float* %tmp22594, i64 1
+  %tmp22596 = getelementptr inbounds float, float* %tmp22595, i64 1
+  %tmp22597 = getelementptr inbounds float, float* %tmp22596, i64 1
+  %tmp22598 = getelementptr inbounds float, float* %tmp22597, i64 1
+  %tmp22599 = getelementptr inbounds float, float* %tmp22598, i64 1
+  %tmp22600 = getelementptr inbounds float, float* %tmp22599, i64 1
+  %tmp22601 = getelementptr inbounds float, float* %tmp22600, i64 1
+  %tmp22602 = getelementptr inbounds float, float* %tmp22601, i64 1
+  %tmp22603 = getelementptr inbounds float, float* %tmp22602, i64 1
+  %tmp22604 = getelementptr inbounds float, float* %tmp22603, i64 1
+  %tmp22605 = getelementptr inbounds float, float* %tmp22604, i64 1
+  %tmp22606 = getelementptr inbounds float, float* %tmp22605, i64 1
+  %tmp22607 = getelementptr inbounds float, float* %tmp22606, i64 1
+  %tmp22608 = getelementptr inbounds float, float* %tmp22607, i64 1
+  %tmp22609 = getelementptr inbounds float, float* %tmp22608, i64 1
+  %tmp22610 = getelementptr inbounds float, float* %tmp22609, i64 1
+  %tmp22611 = getelementptr inbounds float, float* %tmp22610, i64 1
+  %tmp22612 = getelementptr inbounds float, float* %tmp22611, i64 1
+  %tmp22613 = getelementptr inbounds float, float* %tmp22612, i64 1
+  %tmp22614 = getelementptr inbounds float, float* %tmp22613, i64 1
+  %tmp22615 = getelementptr inbounds float, float* %tmp22614, i64 1
+  %tmp22616 = getelementptr inbounds float, float* %tmp22615, i64 1
+  %tmp22617 = getelementptr inbounds float, float* %tmp22616, i64 1
+  %tmp22618 = getelementptr inbounds float, float* %tmp22617, i64 1
+  %tmp22619 = getelementptr inbounds float, float* %tmp22618, i64 1
+  %tmp22620 = getelementptr inbounds float, float* %tmp22619, i64 1
+  %tmp22621 = getelementptr inbounds float, float* %tmp22620, i64 1
+  %tmp22622 = getelementptr inbounds float, float* %tmp22621, i64 1
+  %tmp22623 = getelementptr inbounds float, float* %tmp22622, i64 1
+  %tmp22624 = getelementptr inbounds float, float* %tmp22623, i64 1
+  %tmp22625 = getelementptr inbounds float, float* %tmp22624, i64 1
+  %tmp22626 = getelementptr inbounds float, float* %tmp22625, i64 1
+  %tmp22627 = getelementptr inbounds float, float* %tmp22626, i64 1
+  %tmp22628 = getelementptr inbounds float, float* %tmp22627, i64 1
+  %tmp22629 = getelementptr inbounds float, float* %tmp22628, i64 1
+  %tmp22630 = getelementptr inbounds float, float* %tmp22629, i64 1
+  %tmp22631 = getelementptr inbounds float, float* %tmp22630, i64 1
+  %tmp22632 = getelementptr inbounds float, float* %tmp22631, i64 1
+  %tmp22633 = getelementptr inbounds float, float* %tmp22632, i64 1
+  %tmp22634 = getelementptr inbounds float, float* %tmp22633, i64 1
+  %tmp22635 = getelementptr inbounds float, float* %tmp22634, i64 1
+  %tmp22636 = getelementptr inbounds float, float* %tmp22635, i64 1
+  %tmp22637 = getelementptr inbounds float, float* %tmp22636, i64 1
+  %tmp22638 = getelementptr inbounds float, float* %tmp22637, i64 1
+  %tmp22639 = getelementptr inbounds float, float* %tmp22638, i64 1
+  %tmp22640 = getelementptr inbounds float, float* %tmp22639, i64 1
+  %tmp22641 = getelementptr inbounds float, float* %tmp22640, i64 1
+  %tmp22642 = getelementptr inbounds float, float* %tmp22641, i64 1
+  %tmp22643 = getelementptr inbounds float, float* %tmp22642, i64 1
+  %tmp22644 = getelementptr inbounds float, float* %tmp22643, i64 1
+  %tmp22645 = getelementptr inbounds float, float* %tmp22644, i64 1
+  %tmp22646 = getelementptr inbounds float, float* %tmp22645, i64 1
+  %tmp22647 = getelementptr inbounds float, float* %tmp22646, i64 1
+  %tmp22648 = getelementptr inbounds float, float* %tmp22647, i64 1
+  %tmp22649 = getelementptr inbounds float, float* %tmp22648, i64 1
+  %tmp22650 = getelementptr inbounds float, float* %tmp22649, i64 1
+  %tmp22651 = getelementptr inbounds float, float* %tmp22650, i64 1
+  %tmp22652 = getelementptr inbounds float, float* %tmp22651, i64 1
+  %tmp22653 = getelementptr inbounds float, float* %tmp22652, i64 1
+  %tmp22654 = getelementptr inbounds float, float* %tmp22653, i64 1
+  %tmp22655 = getelementptr inbounds float, float* %tmp22654, i64 1
+  %tmp22656 = getelementptr inbounds float, float* %tmp22655, i64 1
+  %tmp22657 = getelementptr inbounds float, float* %tmp22656, i64 1
+  %tmp22658 = getelementptr inbounds float, float* %tmp22657, i64 1
+  %tmp22659 = getelementptr inbounds float, float* %tmp22658, i64 1
+  %tmp22660 = getelementptr inbounds float, float* %tmp22659, i64 1
+  %tmp22661 = getelementptr inbounds float, float* %tmp22660, i64 1
+  %tmp22662 = getelementptr inbounds float, float* %tmp22661, i64 1
+  %tmp22663 = getelementptr inbounds float, float* %tmp22662, i64 1
+  %tmp22664 = getelementptr inbounds float, float* %tmp22663, i64 1
+  %tmp22665 = getelementptr inbounds float, float* %tmp22664, i64 1
+  %tmp22666 = getelementptr inbounds float, float* %tmp22665, i64 1
+  %tmp22667 = getelementptr inbounds float, float* %tmp22666, i64 1
+  %tmp22668 = getelementptr inbounds float, float* %tmp22667, i64 1
+  %tmp22669 = getelementptr inbounds float, float* %tmp22668, i64 1
+  %tmp22670 = getelementptr inbounds float, float* %tmp22669, i64 1
+  %tmp22671 = getelementptr inbounds float, float* %tmp22670, i64 1
+  %tmp22672 = getelementptr inbounds float, float* %tmp22671, i64 1
+  %tmp22673 = getelementptr inbounds float, float* %tmp22672, i64 1
+  %tmp22674 = getelementptr inbounds float, float* %tmp22673, i64 1
+  %tmp22675 = getelementptr inbounds float, float* %tmp22674, i64 1
+  %tmp22676 = getelementptr inbounds float, float* %tmp22675, i64 1
+  %tmp22677 = getelementptr inbounds float, float* %tmp22676, i64 1
+  %tmp22678 = getelementptr inbounds float, float* %tmp22677, i64 1
+  %tmp22679 = getelementptr inbounds float, float* %tmp22678, i64 1
+  %tmp22680 = getelementptr inbounds float, float* %tmp22679, i64 1
+  %tmp22681 = getelementptr inbounds float, float* %tmp22680, i64 1
+  %tmp22682 = getelementptr inbounds float, float* %tmp22681, i64 1
+  %tmp22683 = getelementptr inbounds float, float* %tmp22682, i64 1
+  %tmp22684 = getelementptr inbounds float, float* %tmp22683, i64 1
+  %tmp22685 = getelementptr inbounds float, float* %tmp22684, i64 1
+  %tmp22686 = getelementptr inbounds float, float* %tmp22685, i64 1
+  %tmp22687 = getelementptr inbounds float, float* %tmp22686, i64 1
+  %tmp22688 = getelementptr inbounds float, float* %tmp22687, i64 1
+  %tmp22689 = getelementptr inbounds float, float* %tmp22688, i64 1
+  %tmp22690 = getelementptr inbounds float, float* %tmp22689, i64 1
+  %tmp22691 = getelementptr inbounds float, float* %tmp22690, i64 1
+  %tmp22692 = getelementptr inbounds float, float* %tmp22691, i64 1
+  %tmp22693 = getelementptr inbounds float, float* %tmp22692, i64 1
+  %tmp22694 = getelementptr inbounds float, float* %tmp22693, i64 1
+  %tmp22695 = getelementptr inbounds float, float* %tmp22694, i64 1
+  %tmp22696 = getelementptr inbounds float, float* %tmp22695, i64 1
+  %tmp22697 = getelementptr inbounds float, float* %tmp22696, i64 1
+  %tmp22698 = getelementptr inbounds float, float* %tmp22697, i64 1
+  %tmp22699 = getelementptr inbounds float, float* %tmp22698, i64 1
+  %tmp22700 = getelementptr inbounds float, float* %tmp22699, i64 1
+  %tmp22701 = getelementptr inbounds float, float* %tmp22700, i64 1
+  %tmp22702 = getelementptr inbounds float, float* %tmp22701, i64 1
+  %tmp22703 = getelementptr inbounds float, float* %tmp22702, i64 1
+  %tmp22704 = getelementptr inbounds float, float* %tmp22703, i64 1
+  %tmp22705 = getelementptr inbounds float, float* %tmp22704, i64 1
+  %tmp22706 = getelementptr inbounds float, float* %tmp22705, i64 1
+  %tmp22707 = getelementptr inbounds float, float* %tmp22706, i64 1
+  %tmp22708 = getelementptr inbounds float, float* %tmp22707, i64 1
+  %tmp22709 = getelementptr inbounds float, float* %tmp22708, i64 1
+  %tmp22710 = getelementptr inbounds float, float* %tmp22709, i64 1
+  %tmp22711 = getelementptr inbounds float, float* %tmp22710, i64 1
+  %tmp22712 = getelementptr inbounds float, float* %tmp22711, i64 1
+  %tmp22713 = getelementptr inbounds float, float* %tmp22712, i64 1
+  %tmp22714 = getelementptr inbounds float, float* %tmp22713, i64 1
+  %tmp22715 = getelementptr inbounds float, float* %tmp22714, i64 1
+  %tmp22716 = getelementptr inbounds float, float* %tmp22715, i64 1
+  %tmp22717 = getelementptr inbounds float, float* %tmp22716, i64 1
+  %tmp22718 = getelementptr inbounds float, float* %tmp22717, i64 1
+  %tmp22719 = getelementptr inbounds float, float* %tmp22718, i64 1
+  %tmp22720 = getelementptr inbounds float, float* %tmp22719, i64 1
+  %tmp22721 = getelementptr inbounds float, float* %tmp22720, i64 1
+  %tmp22722 = getelementptr inbounds float, float* %tmp22721, i64 1
+  %tmp22723 = getelementptr inbounds float, float* %tmp22722, i64 1
+  %tmp22724 = getelementptr inbounds float, float* %tmp22723, i64 1
+  %tmp22725 = getelementptr inbounds float, float* %tmp22724, i64 1
+  %tmp22726 = getelementptr inbounds float, float* %tmp22725, i64 1
+  %tmp22727 = getelementptr inbounds float, float* %tmp22726, i64 1
+  %tmp22728 = getelementptr inbounds float, float* %tmp22727, i64 1
+  %tmp22729 = getelementptr inbounds float, float* %tmp22728, i64 1
+  %tmp22730 = getelementptr inbounds float, float* %tmp22729, i64 1
+  %tmp22731 = getelementptr inbounds float, float* %tmp22730, i64 1
+  %tmp22732 = getelementptr inbounds float, float* %tmp22731, i64 1
+  %tmp22733 = getelementptr inbounds float, float* %tmp22732, i64 1
+  %tmp22734 = getelementptr inbounds float, float* %tmp22733, i64 1
+  %tmp22735 = getelementptr inbounds float, float* %tmp22734, i64 1
+  %tmp22736 = getelementptr inbounds float, float* %tmp22735, i64 1
+  %tmp22737 = getelementptr inbounds float, float* %tmp22736, i64 1
+  %tmp22738 = getelementptr inbounds float, float* %tmp22737, i64 1
+  %tmp22739 = getelementptr inbounds float, float* %tmp22738, i64 1
+  %tmp22740 = getelementptr inbounds float, float* %tmp22739, i64 1
+  %tmp22741 = getelementptr inbounds float, float* %tmp22740, i64 1
+  %tmp22742 = getelementptr inbounds float, float* %tmp22741, i64 1
+  %tmp22743 = getelementptr inbounds float, float* %tmp22742, i64 1
+  %tmp22744 = getelementptr inbounds float, float* %tmp22743, i64 1
+  %tmp22745 = getelementptr inbounds float, float* %tmp22744, i64 1
+  %tmp22746 = getelementptr inbounds float, float* %tmp22745, i64 1
+  %tmp22747 = getelementptr inbounds float, float* %tmp22746, i64 1
+  %tmp22748 = getelementptr inbounds float, float* %tmp22747, i64 1
+  %tmp22749 = getelementptr inbounds float, float* %tmp22748, i64 1
+  %tmp22750 = getelementptr inbounds float, float* %tmp22749, i64 1
+  %tmp22751 = getelementptr inbounds float, float* %tmp22750, i64 1
+  %tmp22752 = getelementptr inbounds float, float* %tmp22751, i64 1
+  %tmp22753 = getelementptr inbounds float, float* %tmp22752, i64 1
+  %tmp22754 = getelementptr inbounds float, float* %tmp22753, i64 1
+  %tmp22755 = getelementptr inbounds float, float* %tmp22754, i64 1
+  %tmp22756 = getelementptr inbounds float, float* %tmp22755, i64 1
+  %tmp22757 = getelementptr inbounds float, float* %tmp22756, i64 1
+  %tmp22758 = getelementptr inbounds float, float* %tmp22757, i64 1
+  %tmp22759 = getelementptr inbounds float, float* %tmp22758, i64 1
+  %tmp22760 = getelementptr inbounds float, float* %tmp22759, i64 1
+  %tmp22761 = getelementptr inbounds float, float* %tmp22760, i64 1
+  %tmp22762 = getelementptr inbounds float, float* %tmp22761, i64 1
+  %tmp22763 = getelementptr inbounds float, float* %tmp22762, i64 1
+  %tmp22764 = getelementptr inbounds float, float* %tmp22763, i64 1
+  %tmp22765 = getelementptr inbounds float, float* %tmp22764, i64 1
+  %tmp22766 = getelementptr inbounds float, float* %tmp22765, i64 1
+  %tmp22767 = getelementptr inbounds float, float* %tmp22766, i64 1
+  %tmp22768 = getelementptr inbounds float, float* %tmp22767, i64 1
+  %tmp22769 = getelementptr inbounds float, float* %tmp22768, i64 1
+  %tmp22770 = getelementptr inbounds float, float* %tmp22769, i64 1
+  %tmp22771 = getelementptr inbounds float, float* %tmp22770, i64 1
+  %tmp22772 = getelementptr inbounds float, float* %tmp22771, i64 1
+  %tmp22773 = getelementptr inbounds float, float* %tmp22772, i64 1
+  %tmp22774 = getelementptr inbounds float, float* %tmp22773, i64 1
+  %tmp22775 = getelementptr inbounds float, float* %tmp22774, i64 1
+  %tmp22776 = getelementptr inbounds float, float* %tmp22775, i64 1
+  %tmp22777 = getelementptr inbounds float, float* %tmp22776, i64 1
+  %tmp22778 = getelementptr inbounds float, float* %tmp22777, i64 1
+  %tmp22779 = getelementptr inbounds float, float* %tmp22778, i64 1
+  %tmp22780 = getelementptr inbounds float, float* %tmp22779, i64 1
+  %tmp22781 = getelementptr inbounds float, float* %tmp22780, i64 1
+  %tmp22782 = getelementptr inbounds float, float* %tmp22781, i64 1
+  %tmp22783 = getelementptr inbounds float, float* %tmp22782, i64 1
+  %tmp22784 = getelementptr inbounds float, float* %tmp22783, i64 1
+  %tmp22785 = getelementptr inbounds float, float* %tmp22784, i64 1
+  %tmp22786 = getelementptr inbounds float, float* %tmp22785, i64 1
+  %tmp22787 = getelementptr inbounds float, float* %tmp22786, i64 1
+  %tmp22788 = getelementptr inbounds float, float* %tmp22787, i64 1
+  %tmp22789 = getelementptr inbounds float, float* %tmp22788, i64 1
+  %tmp22790 = getelementptr inbounds float, float* %tmp22789, i64 1
+  %tmp22791 = getelementptr inbounds float, float* %tmp22790, i64 1
+  %tmp22792 = getelementptr inbounds float, float* %tmp22791, i64 1
+  %tmp22793 = getelementptr inbounds float, float* %tmp22792, i64 1
+  %tmp22794 = getelementptr inbounds float, float* %tmp22793, i64 1
+  %tmp22795 = getelementptr inbounds float, float* %tmp22794, i64 1
+  %tmp22796 = getelementptr inbounds float, float* %tmp22795, i64 1
+  %tmp22797 = getelementptr inbounds float, float* %tmp22796, i64 1
+  %tmp22798 = getelementptr inbounds float, float* %tmp22797, i64 1
+  %tmp22799 = getelementptr inbounds float, float* %tmp22798, i64 1
+  %tmp22800 = getelementptr inbounds float, float* %tmp22799, i64 1
+  %tmp22801 = getelementptr inbounds float, float* %tmp22800, i64 1
+  %tmp22802 = getelementptr inbounds float, float* %tmp22801, i64 1
+  %tmp22803 = getelementptr inbounds float, float* %tmp22802, i64 1
+  %tmp22804 = getelementptr inbounds float, float* %tmp22803, i64 1
+  %tmp22805 = getelementptr inbounds float, float* %tmp22804, i64 1
+  %tmp22806 = getelementptr inbounds float, float* %tmp22805, i64 1
+  %tmp22807 = getelementptr inbounds float, float* %tmp22806, i64 1
+  %tmp22808 = getelementptr inbounds float, float* %tmp22807, i64 1
+  %tmp22809 = getelementptr inbounds float, float* %tmp22808, i64 1
+  %tmp22810 = getelementptr inbounds float, float* %tmp22809, i64 1
+  %tmp22811 = getelementptr inbounds float, float* %tmp22810, i64 1
+  %tmp22812 = getelementptr inbounds float, float* %tmp22811, i64 1
+  %tmp22813 = getelementptr inbounds float, float* %tmp22812, i64 1
+  %tmp22814 = getelementptr inbounds float, float* %tmp22813, i64 1
+  %tmp22815 = getelementptr inbounds float, float* %tmp22814, i64 1
+  %tmp22816 = getelementptr inbounds float, float* %tmp22815, i64 1
+  %tmp22817 = getelementptr inbounds float, float* %tmp22816, i64 1
+  %tmp22818 = getelementptr inbounds float, float* %tmp22817, i64 1
+  %tmp22819 = getelementptr inbounds float, float* %tmp22818, i64 1
+  %tmp22820 = getelementptr inbounds float, float* %tmp22819, i64 1
+  %tmp22821 = getelementptr inbounds float, float* %tmp22820, i64 1
+  %tmp22822 = getelementptr inbounds float, float* %tmp22821, i64 1
+  %tmp22823 = getelementptr inbounds float, float* %tmp22822, i64 1
+  %tmp22824 = getelementptr inbounds float, float* %tmp22823, i64 1
+  %tmp22825 = getelementptr inbounds float, float* %tmp22824, i64 1
+  %tmp22826 = getelementptr inbounds float, float* %tmp22825, i64 1
+  %tmp22827 = getelementptr inbounds float, float* %tmp22826, i64 1
+  %tmp22828 = getelementptr inbounds float, float* %tmp22827, i64 1
+  %tmp22829 = getelementptr inbounds float, float* %tmp22828, i64 1
+  %tmp22830 = getelementptr inbounds float, float* %tmp22829, i64 1
+  %tmp22831 = getelementptr inbounds float, float* %tmp22830, i64 1
+  %tmp22832 = getelementptr inbounds float, float* %tmp22831, i64 1
+  %tmp22833 = getelementptr inbounds float, float* %tmp22832, i64 1
+  %tmp22834 = getelementptr inbounds float, float* %tmp22833, i64 1
+  %tmp22835 = getelementptr inbounds float, float* %tmp22834, i64 1
+  %tmp22836 = getelementptr inbounds float, float* %tmp22835, i64 1
+  %tmp22837 = getelementptr inbounds float, float* %tmp22836, i64 1
+  %tmp22838 = getelementptr inbounds float, float* %tmp22837, i64 1
+  %tmp22839 = getelementptr inbounds float, float* %tmp22838, i64 1
+  %tmp22840 = getelementptr inbounds float, float* %tmp22839, i64 1
+  %tmp22841 = getelementptr inbounds float, float* %tmp22840, i64 1
+  %tmp22842 = getelementptr inbounds float, float* %tmp22841, i64 1
+  %tmp22843 = getelementptr inbounds float, float* %tmp22842, i64 1
+  %tmp22844 = getelementptr inbounds float, float* %tmp22843, i64 1
+  %tmp22845 = getelementptr inbounds float, float* %tmp22844, i64 1
+  %tmp22846 = getelementptr inbounds float, float* %tmp22845, i64 1
+  %tmp22847 = getelementptr inbounds float, float* %tmp22846, i64 1
+  %tmp22848 = getelementptr inbounds float, float* %tmp22847, i64 1
+  %tmp22849 = getelementptr inbounds float, float* %tmp22848, i64 1
+  %tmp22850 = getelementptr inbounds float, float* %tmp22849, i64 1
+  %tmp22851 = getelementptr inbounds float, float* %tmp22850, i64 1
+  %tmp22852 = getelementptr inbounds float, float* %tmp22851, i64 1
+  %tmp22853 = getelementptr inbounds float, float* %tmp22852, i64 1
+  %tmp22854 = getelementptr inbounds float, float* %tmp22853, i64 1
+  %tmp22855 = getelementptr inbounds float, float* %tmp22854, i64 1
+  %tmp22856 = getelementptr inbounds float, float* %tmp22855, i64 1
+  %tmp22857 = getelementptr inbounds float, float* %tmp22856, i64 1
+  %tmp22858 = getelementptr inbounds float, float* %tmp22857, i64 1
+  %tmp22859 = getelementptr inbounds float, float* %tmp22858, i64 1
+  %tmp22860 = getelementptr inbounds float, float* %tmp22859, i64 1
+  %tmp22861 = getelementptr inbounds float, float* %tmp22860, i64 1
+  %tmp22862 = getelementptr inbounds float, float* %tmp22861, i64 1
+  %tmp22863 = getelementptr inbounds float, float* %tmp22862, i64 1
+  %tmp22864 = getelementptr inbounds float, float* %tmp22863, i64 1
+  %tmp22865 = getelementptr inbounds float, float* %tmp22864, i64 1
+  %tmp22866 = getelementptr inbounds float, float* %tmp22865, i64 1
+  %tmp22867 = getelementptr inbounds float, float* %tmp22866, i64 1
+  %tmp22868 = getelementptr inbounds float, float* %tmp22867, i64 1
+  %tmp22869 = getelementptr inbounds float, float* %tmp22868, i64 1
+  %tmp22870 = getelementptr inbounds float, float* %tmp22869, i64 1
+  %tmp22871 = getelementptr inbounds float, float* %tmp22870, i64 1
+  %tmp22872 = getelementptr inbounds float, float* %tmp22871, i64 1
+  %tmp22873 = getelementptr inbounds float, float* %tmp22872, i64 1
+  %tmp22874 = getelementptr inbounds float, float* %tmp22873, i64 1
+  %tmp22875 = getelementptr inbounds float, float* %tmp22874, i64 1
+  %tmp22876 = getelementptr inbounds float, float* %tmp22875, i64 1
+  %tmp22877 = getelementptr inbounds float, float* %tmp22876, i64 1
+  %tmp22878 = getelementptr inbounds float, float* %tmp22877, i64 1
+  %tmp22879 = getelementptr inbounds float, float* %tmp22878, i64 1
+  %tmp22880 = getelementptr inbounds float, float* %tmp22879, i64 1
+  %tmp22881 = getelementptr inbounds float, float* %tmp22880, i64 1
+  %tmp22882 = getelementptr inbounds float, float* %tmp22881, i64 1
+  %tmp22883 = getelementptr inbounds float, float* %tmp22882, i64 1
+  %tmp22884 = getelementptr inbounds float, float* %tmp22883, i64 1
+  %tmp22885 = getelementptr inbounds float, float* %tmp22884, i64 1
+  %tmp22886 = getelementptr inbounds float, float* %tmp22885, i64 1
+  %tmp22887 = getelementptr inbounds float, float* %tmp22886, i64 1
+  %tmp22888 = getelementptr inbounds float, float* %tmp22887, i64 1
+  %tmp22889 = getelementptr inbounds float, float* %tmp22888, i64 1
+  %tmp22890 = getelementptr inbounds float, float* %tmp22889, i64 1
+  %tmp22891 = getelementptr inbounds float, float* %tmp22890, i64 1
+  %tmp22892 = getelementptr inbounds float, float* %tmp22891, i64 1
+  %tmp22893 = getelementptr inbounds float, float* %tmp22892, i64 1
+  %tmp22894 = getelementptr inbounds float, float* %tmp22893, i64 1
+  %tmp22895 = getelementptr inbounds float, float* %tmp22894, i64 1
+  %tmp22896 = getelementptr inbounds float, float* %tmp22895, i64 1
+  %tmp22897 = getelementptr inbounds float, float* %tmp22896, i64 1
+  %tmp22898 = getelementptr inbounds float, float* %tmp22897, i64 1
+  %tmp22899 = getelementptr inbounds float, float* %tmp22898, i64 1
+  %tmp22900 = getelementptr inbounds float, float* %tmp22899, i64 1
+  %tmp22901 = getelementptr inbounds float, float* %tmp22900, i64 1
+  %tmp22902 = getelementptr inbounds float, float* %tmp22901, i64 1
+  %tmp22903 = getelementptr inbounds float, float* %tmp22902, i64 1
+  %tmp22904 = getelementptr inbounds float, float* %tmp22903, i64 1
+  %tmp22905 = getelementptr inbounds float, float* %tmp22904, i64 1
+  %tmp22906 = getelementptr inbounds float, float* %tmp22905, i64 1
+  %tmp22907 = getelementptr inbounds float, float* %tmp22906, i64 1
+  %tmp22908 = getelementptr inbounds float, float* %tmp22907, i64 1
+  %tmp22909 = getelementptr inbounds float, float* %tmp22908, i64 1
+  %tmp22910 = getelementptr inbounds float, float* %tmp22909, i64 1
+  %tmp22911 = getelementptr inbounds float, float* %tmp22910, i64 1
+  %tmp22912 = getelementptr inbounds float, float* %tmp22911, i64 1
+  %tmp22913 = getelementptr inbounds float, float* %tmp22912, i64 1
+  %tmp22914 = getelementptr inbounds float, float* %tmp22913, i64 1
+  %tmp22915 = getelementptr inbounds float, float* %tmp22914, i64 1
+  %tmp22916 = getelementptr inbounds float, float* %tmp22915, i64 1
+  %tmp22917 = getelementptr inbounds float, float* %tmp22916, i64 1
+  %tmp22918 = getelementptr inbounds float, float* %tmp22917, i64 1
+  %tmp22919 = getelementptr inbounds float, float* %tmp22918, i64 1
+  %tmp22920 = getelementptr inbounds float, float* %tmp22919, i64 1
+  %tmp22921 = getelementptr inbounds float, float* %tmp22920, i64 1
+  %tmp22922 = getelementptr inbounds float, float* %tmp22921, i64 1
+  %tmp22923 = getelementptr inbounds float, float* %tmp22922, i64 1
+  %tmp22924 = getelementptr inbounds float, float* %tmp22923, i64 1
+  %tmp22925 = getelementptr inbounds float, float* %tmp22924, i64 1
+  %tmp22926 = getelementptr inbounds float, float* %tmp22925, i64 1
+  %tmp22927 = getelementptr inbounds float, float* %tmp22926, i64 1
+  %tmp22928 = getelementptr inbounds float, float* %tmp22927, i64 1
+  %tmp22929 = getelementptr inbounds float, float* %tmp22928, i64 1
+  %tmp22930 = getelementptr inbounds float, float* %tmp22929, i64 1
+  %tmp22931 = getelementptr inbounds float, float* %tmp22930, i64 1
+  %tmp22932 = getelementptr inbounds float, float* %tmp22931, i64 1
+  %tmp22933 = getelementptr inbounds float, float* %tmp22932, i64 1
+  %tmp22934 = getelementptr inbounds float, float* %tmp22933, i64 1
+  %tmp22935 = getelementptr inbounds float, float* %tmp22934, i64 1
+  %tmp22936 = getelementptr inbounds float, float* %tmp22935, i64 1
+  %tmp22937 = getelementptr inbounds float, float* %tmp22936, i64 1
+  %tmp22938 = getelementptr inbounds float, float* %tmp22937, i64 1
+  %tmp22939 = getelementptr inbounds float, float* %tmp22938, i64 1
+  %tmp22940 = getelementptr inbounds float, float* %tmp22939, i64 1
+  %tmp22941 = getelementptr inbounds float, float* %tmp22940, i64 1
+  %tmp22942 = getelementptr inbounds float, float* %tmp22941, i64 1
+  %tmp22943 = getelementptr inbounds float, float* %tmp22942, i64 1
+  %tmp22944 = getelementptr inbounds float, float* %tmp22943, i64 1
+  %tmp22945 = getelementptr inbounds float, float* %tmp22944, i64 1
+  %tmp22946 = getelementptr inbounds float, float* %tmp22945, i64 1
+  %tmp22947 = getelementptr inbounds float, float* %tmp22946, i64 1
+  %tmp22948 = getelementptr inbounds float, float* %tmp22947, i64 1
+  %tmp22949 = getelementptr inbounds float, float* %tmp22948, i64 1
+  %tmp22950 = getelementptr inbounds float, float* %tmp22949, i64 1
+  %tmp22951 = getelementptr inbounds float, float* %tmp22950, i64 1
+  %tmp22952 = getelementptr inbounds float, float* %tmp22951, i64 1
+  %tmp22953 = getelementptr inbounds float, float* %tmp22952, i64 1
+  %tmp22954 = getelementptr inbounds float, float* %tmp22953, i64 1
+  %tmp22955 = getelementptr inbounds float, float* %tmp22954, i64 1
+  %tmp22956 = getelementptr inbounds float, float* %tmp22955, i64 1
+  %tmp22957 = getelementptr inbounds float, float* %tmp22956, i64 1
+  %tmp22958 = getelementptr inbounds float, float* %tmp22957, i64 1
+  %tmp22959 = getelementptr inbounds float, float* %tmp22958, i64 1
+  %tmp22960 = getelementptr inbounds float, float* %tmp22959, i64 1
+  %tmp22961 = getelementptr inbounds float, float* %tmp22960, i64 1
+  %tmp22962 = getelementptr inbounds float, float* %tmp22961, i64 1
+  %tmp22963 = getelementptr inbounds float, float* %tmp22962, i64 1
+  %tmp22964 = getelementptr inbounds float, float* %tmp22963, i64 1
+  %tmp22965 = getelementptr inbounds float, float* %tmp22964, i64 1
+  %tmp22966 = getelementptr inbounds float, float* %tmp22965, i64 1
+  %tmp22967 = getelementptr inbounds float, float* %tmp22966, i64 1
+  %tmp22968 = getelementptr inbounds float, float* %tmp22967, i64 1
+  %tmp22969 = getelementptr inbounds float, float* %tmp22968, i64 1
+  %tmp22970 = getelementptr inbounds float, float* %tmp22969, i64 1
+  %tmp22971 = getelementptr inbounds float, float* %tmp22970, i64 1
+  %tmp22972 = getelementptr inbounds float, float* %tmp22971, i64 1
+  %tmp22973 = getelementptr inbounds float, float* %tmp22972, i64 1
+  %tmp22974 = getelementptr inbounds float, float* %tmp22973, i64 1
+  %tmp22975 = getelementptr inbounds float, float* %tmp22974, i64 1
+  %tmp22976 = getelementptr inbounds float, float* %tmp22975, i64 1
+  %tmp22977 = getelementptr inbounds float, float* %tmp22976, i64 1
+  %tmp22978 = getelementptr inbounds float, float* %tmp22977, i64 1
+  %tmp22979 = getelementptr inbounds float, float* %tmp22978, i64 1
+  %tmp22980 = getelementptr inbounds float, float* %tmp22979, i64 1
+  %tmp22981 = getelementptr inbounds float, float* %tmp22980, i64 1
+  %tmp22982 = getelementptr inbounds float, float* %tmp22981, i64 1
+  %tmp22983 = getelementptr inbounds float, float* %tmp22982, i64 1
+  %tmp22984 = getelementptr inbounds float, float* %tmp22983, i64 1
+  %tmp22985 = getelementptr inbounds float, float* %tmp22984, i64 1
+  %tmp22986 = getelementptr inbounds float, float* %tmp22985, i64 1
+  %tmp22987 = getelementptr inbounds float, float* %tmp22986, i64 1
+  %tmp22988 = getelementptr inbounds float, float* %tmp22987, i64 1
+  %tmp22989 = getelementptr inbounds float, float* %tmp22988, i64 1
+  %tmp22990 = getelementptr inbounds float, float* %tmp22989, i64 1
+  %tmp22991 = getelementptr inbounds float, float* %tmp22990, i64 1
+  %tmp22992 = getelementptr inbounds float, float* %tmp22991, i64 1
+  %tmp22993 = getelementptr inbounds float, float* %tmp22992, i64 1
+  %tmp22994 = getelementptr inbounds float, float* %tmp22993, i64 1
+  %tmp22995 = getelementptr inbounds float, float* %tmp22994, i64 1
+  %tmp22996 = getelementptr inbounds float, float* %tmp22995, i64 1
+  %tmp22997 = getelementptr inbounds float, float* %tmp22996, i64 1
+  %tmp22998 = getelementptr inbounds float, float* %tmp22997, i64 1
+  %tmp22999 = getelementptr inbounds float, float* %tmp22998, i64 1
+  %tmp23000 = getelementptr inbounds float, float* %tmp22999, i64 1
+  %tmp23001 = getelementptr inbounds float, float* %tmp23000, i64 1
+  %tmp23002 = getelementptr inbounds float, float* %tmp23001, i64 1
+  %tmp23003 = getelementptr inbounds float, float* %tmp23002, i64 1
+  %tmp23004 = getelementptr inbounds float, float* %tmp23003, i64 1
+  %tmp23005 = getelementptr inbounds float, float* %tmp23004, i64 1
+  %tmp23006 = getelementptr inbounds float, float* %tmp23005, i64 1
+  %tmp23007 = getelementptr inbounds float, float* %tmp23006, i64 1
+  %tmp23008 = getelementptr inbounds float, float* %tmp23007, i64 1
+  %tmp23009 = getelementptr inbounds float, float* %tmp23008, i64 1
+  %tmp23010 = getelementptr inbounds float, float* %tmp23009, i64 1
+  %tmp23011 = getelementptr inbounds float, float* %tmp23010, i64 1
+  %tmp23012 = getelementptr inbounds float, float* %tmp23011, i64 1
+  %tmp23013 = getelementptr inbounds float, float* %tmp23012, i64 1
+  %tmp23014 = getelementptr inbounds float, float* %tmp23013, i64 1
+  %tmp23015 = getelementptr inbounds float, float* %tmp23014, i64 1
+  %tmp23016 = getelementptr inbounds float, float* %tmp23015, i64 1
+  %tmp23017 = getelementptr inbounds float, float* %tmp23016, i64 1
+  %tmp23018 = getelementptr inbounds float, float* %tmp23017, i64 1
+  %tmp23019 = getelementptr inbounds float, float* %tmp23018, i64 1
+  %tmp23020 = getelementptr inbounds float, float* %tmp23019, i64 1
+  %tmp23021 = getelementptr inbounds float, float* %tmp23020, i64 1
+  %tmp23022 = getelementptr inbounds float, float* %tmp23021, i64 1
+  %tmp23023 = getelementptr inbounds float, float* %tmp23022, i64 1
+  %tmp23024 = getelementptr inbounds float, float* %tmp23023, i64 1
+  %tmp23025 = getelementptr inbounds float, float* %tmp23024, i64 1
+  %tmp23026 = getelementptr inbounds float, float* %tmp23025, i64 1
+  %tmp23027 = getelementptr inbounds float, float* %tmp23026, i64 1
+  %tmp23028 = getelementptr inbounds float, float* %tmp23027, i64 1
+  %tmp23029 = getelementptr inbounds float, float* %tmp23028, i64 1
+  %tmp23030 = getelementptr inbounds float, float* %tmp23029, i64 1
+  %tmp23031 = getelementptr inbounds float, float* %tmp23030, i64 1
+  %tmp23032 = getelementptr inbounds float, float* %tmp23031, i64 1
+  %tmp23033 = getelementptr inbounds float, float* %tmp23032, i64 1
+  %tmp23034 = getelementptr inbounds float, float* %tmp23033, i64 1
+  %tmp23035 = getelementptr inbounds float, float* %tmp23034, i64 1
+  %tmp23036 = getelementptr inbounds float, float* %tmp23035, i64 1
+  %tmp23037 = getelementptr inbounds float, float* %tmp23036, i64 1
+  %tmp23038 = getelementptr inbounds float, float* %tmp23037, i64 1
+  %tmp23039 = getelementptr inbounds float, float* %tmp23038, i64 1
+  %tmp23040 = getelementptr inbounds float, float* %tmp23039, i64 1
+  %tmp23041 = getelementptr inbounds float, float* %tmp23040, i64 1
+  %tmp23042 = getelementptr inbounds float, float* %tmp23041, i64 1
+  %tmp23043 = getelementptr inbounds float, float* %tmp23042, i64 1
+  %tmp23044 = getelementptr inbounds float, float* %tmp23043, i64 1
+  %tmp23045 = getelementptr inbounds float, float* %tmp23044, i64 1
+  %tmp23046 = getelementptr inbounds float, float* %tmp23045, i64 1
+  %tmp23047 = getelementptr inbounds float, float* %tmp23046, i64 1
+  %tmp23048 = getelementptr inbounds float, float* %tmp23047, i64 1
+  %tmp23049 = getelementptr inbounds float, float* %tmp23048, i64 1
+  %tmp23050 = getelementptr inbounds float, float* %tmp23049, i64 1
+  %tmp23051 = getelementptr inbounds float, float* %tmp23050, i64 1
+  %tmp23052 = getelementptr inbounds float, float* %tmp23051, i64 1
+  %tmp23053 = getelementptr inbounds float, float* %tmp23052, i64 1
+  %tmp23054 = getelementptr inbounds float, float* %tmp23053, i64 1
+  %tmp23055 = getelementptr inbounds float, float* %tmp23054, i64 1
+  %tmp23056 = getelementptr inbounds float, float* %tmp23055, i64 1
+  %tmp23057 = getelementptr inbounds float, float* %tmp23056, i64 1
+  %tmp23058 = getelementptr inbounds float, float* %tmp23057, i64 1
+  %tmp23059 = getelementptr inbounds float, float* %tmp23058, i64 1
+  %tmp23060 = getelementptr inbounds float, float* %tmp23059, i64 1
+  %tmp23061 = getelementptr inbounds float, float* %tmp23060, i64 1
+  %tmp23062 = getelementptr inbounds float, float* %tmp23061, i64 1
+  %tmp23063 = getelementptr inbounds float, float* %tmp23062, i64 1
+  %tmp23064 = getelementptr inbounds float, float* %tmp23063, i64 1
+  %tmp23065 = getelementptr inbounds float, float* %tmp23064, i64 1
+  %tmp23066 = getelementptr inbounds float, float* %tmp23065, i64 1
+  %tmp23067 = getelementptr inbounds float, float* %tmp23066, i64 1
+  %tmp23068 = getelementptr inbounds float, float* %tmp23067, i64 1
+  %tmp23069 = getelementptr inbounds float, float* %tmp23068, i64 1
+  %tmp23070 = getelementptr inbounds float, float* %tmp23069, i64 1
+  %tmp23071 = getelementptr inbounds float, float* %tmp23070, i64 1
+  %tmp23072 = getelementptr inbounds float, float* %tmp23071, i64 1
+  %tmp23073 = getelementptr inbounds float, float* %tmp23072, i64 1
+  %tmp23074 = getelementptr inbounds float, float* %tmp23073, i64 1
+  %tmp23075 = getelementptr inbounds float, float* %tmp23074, i64 1
+  %tmp23076 = getelementptr inbounds float, float* %tmp23075, i64 1
+  %tmp23077 = getelementptr inbounds float, float* %tmp23076, i64 1
+  %tmp23078 = getelementptr inbounds float, float* %tmp23077, i64 1
+  %tmp23079 = getelementptr inbounds float, float* %tmp23078, i64 1
+  %tmp23080 = getelementptr inbounds float, float* %tmp23079, i64 1
+  %tmp23081 = getelementptr inbounds float, float* %tmp23080, i64 1
+  %tmp23082 = getelementptr inbounds float, float* %tmp23081, i64 1
+  %tmp23083 = getelementptr inbounds float, float* %tmp23082, i64 1
+  %tmp23084 = getelementptr inbounds float, float* %tmp23083, i64 1
+  %tmp23085 = getelementptr inbounds float, float* %tmp23084, i64 1
+  %tmp23086 = getelementptr inbounds float, float* %tmp23085, i64 1
+  %tmp23087 = getelementptr inbounds float, float* %tmp23086, i64 1
+  %tmp23088 = getelementptr inbounds float, float* %tmp23087, i64 1
+  %tmp23089 = getelementptr inbounds float, float* %tmp23088, i64 1
+  %tmp23090 = getelementptr inbounds float, float* %tmp23089, i64 1
+  %tmp23091 = getelementptr inbounds float, float* %tmp23090, i64 1
+  %tmp23092 = getelementptr inbounds float, float* %tmp23091, i64 1
+  %tmp23093 = getelementptr inbounds float, float* %tmp23092, i64 1
+  %tmp23094 = getelementptr inbounds float, float* %tmp23093, i64 1
+  %tmp23095 = getelementptr inbounds float, float* %tmp23094, i64 1
+  %tmp23096 = getelementptr inbounds float, float* %tmp23095, i64 1
+  %tmp23097 = getelementptr inbounds float, float* %tmp23096, i64 1
+  %tmp23098 = getelementptr inbounds float, float* %tmp23097, i64 1
+  %tmp23099 = getelementptr inbounds float, float* %tmp23098, i64 1
+  %tmp23100 = getelementptr inbounds float, float* %tmp23099, i64 1
+  %tmp23101 = getelementptr inbounds float, float* %tmp23100, i64 1
+  %tmp23102 = getelementptr inbounds float, float* %tmp23101, i64 1
+  %tmp23103 = getelementptr inbounds float, float* %tmp23102, i64 1
+  %tmp23104 = getelementptr inbounds float, float* %tmp23103, i64 1
+  %tmp23105 = getelementptr inbounds float, float* %tmp23104, i64 1
+  %tmp23106 = getelementptr inbounds float, float* %tmp23105, i64 1
+  %tmp23107 = getelementptr inbounds float, float* %tmp23106, i64 1
+  %tmp23108 = getelementptr inbounds float, float* %tmp23107, i64 1
+  %tmp23109 = getelementptr inbounds float, float* %tmp23108, i64 1
+  %tmp23110 = getelementptr inbounds float, float* %tmp23109, i64 1
+  %tmp23111 = getelementptr inbounds float, float* %tmp23110, i64 1
+  %tmp23112 = getelementptr inbounds float, float* %tmp23111, i64 1
+  %tmp23113 = getelementptr inbounds float, float* %tmp23112, i64 1
+  %tmp23114 = getelementptr inbounds float, float* %tmp23113, i64 1
+  %tmp23115 = getelementptr inbounds float, float* %tmp23114, i64 1
+  %tmp23116 = getelementptr inbounds float, float* %tmp23115, i64 1
+  %tmp23117 = getelementptr inbounds float, float* %tmp23116, i64 1
+  %tmp23118 = getelementptr inbounds float, float* %tmp23117, i64 1
+  %tmp23119 = getelementptr inbounds float, float* %tmp23118, i64 1
+  %tmp23120 = getelementptr inbounds float, float* %tmp23119, i64 1
+  %tmp23121 = getelementptr inbounds float, float* %tmp23120, i64 1
+  %tmp23122 = getelementptr inbounds float, float* %tmp23121, i64 1
+  %tmp23123 = getelementptr inbounds float, float* %tmp23122, i64 1
+  %tmp23124 = getelementptr inbounds float, float* %tmp23123, i64 1
+  %tmp23125 = getelementptr inbounds float, float* %tmp23124, i64 1
+  %tmp23126 = getelementptr inbounds float, float* %tmp23125, i64 1
+  %tmp23127 = getelementptr inbounds float, float* %tmp23126, i64 1
+  %tmp23128 = getelementptr inbounds float, float* %tmp23127, i64 1
+  %tmp23129 = getelementptr inbounds float, float* %tmp23128, i64 1
+  %tmp23130 = getelementptr inbounds float, float* %tmp23129, i64 1
+  %tmp23131 = getelementptr inbounds float, float* %tmp23130, i64 1
+  %tmp23132 = getelementptr inbounds float, float* %tmp23131, i64 1
+  %tmp23133 = getelementptr inbounds float, float* %tmp23132, i64 1
+  %tmp23134 = getelementptr inbounds float, float* %tmp23133, i64 1
+  %tmp23135 = getelementptr inbounds float, float* %tmp23134, i64 1
+  %tmp23136 = getelementptr inbounds float, float* %tmp23135, i64 1
+  %tmp23137 = getelementptr inbounds float, float* %tmp23136, i64 1
+  %tmp23138 = getelementptr inbounds float, float* %tmp23137, i64 1
+  %tmp23139 = getelementptr inbounds float, float* %tmp23138, i64 1
+  %tmp23140 = getelementptr inbounds float, float* %tmp23139, i64 1
+  %tmp23141 = getelementptr inbounds float, float* %tmp23140, i64 1
+  %tmp23142 = getelementptr inbounds float, float* %tmp23141, i64 1
+  %tmp23143 = getelementptr inbounds float, float* %tmp23142, i64 1
+  %tmp23144 = getelementptr inbounds float, float* %tmp23143, i64 1
+  %tmp23145 = getelementptr inbounds float, float* %tmp23144, i64 1
+  %tmp23146 = getelementptr inbounds float, float* %tmp23145, i64 1
+  %tmp23147 = getelementptr inbounds float, float* %tmp23146, i64 1
+  %tmp23148 = getelementptr inbounds float, float* %tmp23147, i64 1
+  %tmp23149 = getelementptr inbounds float, float* %tmp23148, i64 1
+  %tmp23150 = getelementptr inbounds float, float* %tmp23149, i64 1
+  %tmp23151 = getelementptr inbounds float, float* %tmp23150, i64 1
+  %tmp23152 = getelementptr inbounds float, float* %tmp23151, i64 1
+  %tmp23153 = getelementptr inbounds float, float* %tmp23152, i64 1
+  %tmp23154 = getelementptr inbounds float, float* %tmp23153, i64 1
+  %tmp23155 = getelementptr inbounds float, float* %tmp23154, i64 1
+  %tmp23156 = getelementptr inbounds float, float* %tmp23155, i64 1
+  %tmp23157 = getelementptr inbounds float, float* %tmp23156, i64 1
+  %tmp23158 = getelementptr inbounds float, float* %tmp23157, i64 1
+  %tmp23159 = getelementptr inbounds float, float* %tmp23158, i64 1
+  %tmp23160 = getelementptr inbounds float, float* %tmp23159, i64 1
+  %tmp23161 = getelementptr inbounds float, float* %tmp23160, i64 1
+  %tmp23162 = getelementptr inbounds float, float* %tmp23161, i64 1
+  %tmp23163 = getelementptr inbounds float, float* %tmp23162, i64 1
+  %tmp23164 = getelementptr inbounds float, float* %tmp23163, i64 1
+  %tmp23165 = getelementptr inbounds float, float* %tmp23164, i64 1
+  %tmp23166 = getelementptr inbounds float, float* %tmp23165, i64 1
+  %tmp23167 = getelementptr inbounds float, float* %tmp23166, i64 1
+  %tmp23168 = getelementptr inbounds float, float* %tmp23167, i64 1
+  %tmp23169 = getelementptr inbounds float, float* %tmp23168, i64 1
+  %tmp23170 = getelementptr inbounds float, float* %tmp23169, i64 1
+  %tmp23171 = getelementptr inbounds float, float* %tmp23170, i64 1
+  %tmp23172 = getelementptr inbounds float, float* %tmp23171, i64 1
+  %tmp23173 = getelementptr inbounds float, float* %tmp23172, i64 1
+  %tmp23174 = getelementptr inbounds float, float* %tmp23173, i64 1
+  %tmp23175 = getelementptr inbounds float, float* %tmp23174, i64 1
+  %tmp23176 = getelementptr inbounds float, float* %tmp23175, i64 1
+  %tmp23177 = getelementptr inbounds float, float* %tmp23176, i64 1
+  %tmp23178 = getelementptr inbounds float, float* %tmp23177, i64 1
+  %tmp23179 = getelementptr inbounds float, float* %tmp23178, i64 1
+  %tmp23180 = getelementptr inbounds float, float* %tmp23179, i64 1
+  %tmp23181 = getelementptr inbounds float, float* %tmp23180, i64 1
+  %tmp23182 = getelementptr inbounds float, float* %tmp23181, i64 1
+  %tmp23183 = getelementptr inbounds float, float* %tmp23182, i64 1
+  %tmp23184 = getelementptr inbounds float, float* %tmp23183, i64 1
+  %tmp23185 = getelementptr inbounds float, float* %tmp23184, i64 1
+  %tmp23186 = getelementptr inbounds float, float* %tmp23185, i64 1
+  %tmp23187 = getelementptr inbounds float, float* %tmp23186, i64 1
+  %tmp23188 = getelementptr inbounds float, float* %tmp23187, i64 1
+  %tmp23189 = getelementptr inbounds float, float* %tmp23188, i64 1
+  %tmp23190 = getelementptr inbounds float, float* %tmp23189, i64 1
+  %tmp23191 = getelementptr inbounds float, float* %tmp23190, i64 1
+  %tmp23192 = getelementptr inbounds float, float* %tmp23191, i64 1
+  %tmp23193 = getelementptr inbounds float, float* %tmp23192, i64 1
+  %tmp23194 = getelementptr inbounds float, float* %tmp23193, i64 1
+  %tmp23195 = getelementptr inbounds float, float* %tmp23194, i64 1
+  %tmp23196 = getelementptr inbounds float, float* %tmp23195, i64 1
+  %tmp23197 = getelementptr inbounds float, float* %tmp23196, i64 1
+  %tmp23198 = getelementptr inbounds float, float* %tmp23197, i64 1
+  %tmp23199 = getelementptr inbounds float, float* %tmp23198, i64 1
+  %tmp23200 = getelementptr inbounds float, float* %tmp23199, i64 1
+  %tmp23201 = getelementptr inbounds float, float* %tmp23200, i64 1
+  %tmp23202 = getelementptr inbounds float, float* %tmp23201, i64 1
+  %tmp23203 = getelementptr inbounds float, float* %tmp23202, i64 1
+  %tmp23204 = getelementptr inbounds float, float* %tmp23203, i64 1
+  %tmp23205 = getelementptr inbounds float, float* %tmp23204, i64 1
+  %tmp23206 = getelementptr inbounds float, float* %tmp23205, i64 1
+  %tmp23207 = getelementptr inbounds float, float* %tmp23206, i64 1
+  %tmp23208 = getelementptr inbounds float, float* %tmp23207, i64 1
+  %tmp23209 = getelementptr inbounds float, float* %tmp23208, i64 1
+  %tmp23210 = getelementptr inbounds float, float* %tmp23209, i64 1
+  %tmp23211 = getelementptr inbounds float, float* %tmp23210, i64 1
+  %tmp23212 = getelementptr inbounds float, float* %tmp23211, i64 1
+  %tmp23213 = getelementptr inbounds float, float* %tmp23212, i64 1
+  %tmp23214 = getelementptr inbounds float, float* %tmp23213, i64 1
+  %tmp23215 = getelementptr inbounds float, float* %tmp23214, i64 1
+  %tmp23216 = getelementptr inbounds float, float* %tmp23215, i64 1
+  %tmp23217 = getelementptr inbounds float, float* %tmp23216, i64 1
+  %tmp23218 = getelementptr inbounds float, float* %tmp23217, i64 1
+  %tmp23219 = getelementptr inbounds float, float* %tmp23218, i64 1
+  %tmp23220 = getelementptr inbounds float, float* %tmp23219, i64 1
+  %tmp23221 = getelementptr inbounds float, float* %tmp23220, i64 1
+  %tmp23222 = getelementptr inbounds float, float* %tmp23221, i64 1
+  %tmp23223 = getelementptr inbounds float, float* %tmp23222, i64 1
+  %tmp23224 = getelementptr inbounds float, float* %tmp23223, i64 1
+  %tmp23225 = getelementptr inbounds float, float* %tmp23224, i64 1
+  %tmp23226 = getelementptr inbounds float, float* %tmp23225, i64 1
+  %tmp23227 = getelementptr inbounds float, float* %tmp23226, i64 1
+  %tmp23228 = getelementptr inbounds float, float* %tmp23227, i64 1
+  %tmp23229 = getelementptr inbounds float, float* %tmp23228, i64 1
+  %tmp23230 = getelementptr inbounds float, float* %tmp23229, i64 1
+  %tmp23231 = getelementptr inbounds float, float* %tmp23230, i64 1
+  %tmp23232 = getelementptr inbounds float, float* %tmp23231, i64 1
+  %tmp23233 = getelementptr inbounds float, float* %tmp23232, i64 1
+  %tmp23234 = getelementptr inbounds float, float* %tmp23233, i64 1
+  %tmp23235 = getelementptr inbounds float, float* %tmp23234, i64 1
+  %tmp23236 = getelementptr inbounds float, float* %tmp23235, i64 1
+  %tmp23237 = getelementptr inbounds float, float* %tmp23236, i64 1
+  %tmp23238 = getelementptr inbounds float, float* %tmp23237, i64 1
+  %tmp23239 = getelementptr inbounds float, float* %tmp23238, i64 1
+  %tmp23240 = getelementptr inbounds float, float* %tmp23239, i64 1
+  %tmp23241 = getelementptr inbounds float, float* %tmp23240, i64 1
+  %tmp23242 = getelementptr inbounds float, float* %tmp23241, i64 1
+  %tmp23243 = getelementptr inbounds float, float* %tmp23242, i64 1
+  %tmp23244 = getelementptr inbounds float, float* %tmp23243, i64 1
+  %tmp23245 = getelementptr inbounds float, float* %tmp23244, i64 1
+  %tmp23246 = getelementptr inbounds float, float* %tmp23245, i64 1
+  %tmp23247 = getelementptr inbounds float, float* %tmp23246, i64 1
+  %tmp23248 = getelementptr inbounds float, float* %tmp23247, i64 1
+  %tmp23249 = getelementptr inbounds float, float* %tmp23248, i64 1
+  %tmp23250 = getelementptr inbounds float, float* %tmp23249, i64 1
+  %tmp23251 = getelementptr inbounds float, float* %tmp23250, i64 1
+  %tmp23252 = getelementptr inbounds float, float* %tmp23251, i64 1
+  %tmp23253 = getelementptr inbounds float, float* %tmp23252, i64 1
+  %tmp23254 = getelementptr inbounds float, float* %tmp23253, i64 1
+  %tmp23255 = getelementptr inbounds float, float* %tmp23254, i64 1
+  %tmp23256 = getelementptr inbounds float, float* %tmp23255, i64 1
+  %tmp23257 = getelementptr inbounds float, float* %tmp23256, i64 1
+  %tmp23258 = getelementptr inbounds float, float* %tmp23257, i64 1
+  %tmp23259 = getelementptr inbounds float, float* %tmp23258, i64 1
+  %tmp23260 = getelementptr inbounds float, float* %tmp23259, i64 1
+  %tmp23261 = getelementptr inbounds float, float* %tmp23260, i64 1
+  %tmp23262 = getelementptr inbounds float, float* %tmp23261, i64 1
+  %tmp23263 = getelementptr inbounds float, float* %tmp23262, i64 1
+  %tmp23264 = getelementptr inbounds float, float* %tmp23263, i64 1
+  %tmp23265 = getelementptr inbounds float, float* %tmp23264, i64 1
+  %tmp23266 = getelementptr inbounds float, float* %tmp23265, i64 1
+  %tmp23267 = getelementptr inbounds float, float* %tmp23266, i64 1
+  %tmp23268 = getelementptr inbounds float, float* %tmp23267, i64 1
+  %tmp23269 = getelementptr inbounds float, float* %tmp23268, i64 1
+  %tmp23270 = getelementptr inbounds float, float* %tmp23269, i64 1
+  %tmp23271 = getelementptr inbounds float, float* %tmp23270, i64 1
+  %tmp23272 = getelementptr inbounds float, float* %tmp23271, i64 1
+  %tmp23273 = getelementptr inbounds float, float* %tmp23272, i64 1
+  %tmp23274 = getelementptr inbounds float, float* %tmp23273, i64 1
+  %tmp23275 = getelementptr inbounds float, float* %tmp23274, i64 1
+  %tmp23276 = getelementptr inbounds float, float* %tmp23275, i64 1
+  %tmp23277 = getelementptr inbounds float, float* %tmp23276, i64 1
+  %tmp23278 = getelementptr inbounds float, float* %tmp23277, i64 1
+  %tmp23279 = getelementptr inbounds float, float* %tmp23278, i64 1
+  %tmp23280 = getelementptr inbounds float, float* %tmp23279, i64 1
+  %tmp23281 = getelementptr inbounds float, float* %tmp23280, i64 1
+  %tmp23282 = getelementptr inbounds float, float* %tmp23281, i64 1
+  %tmp23283 = getelementptr inbounds float, float* %tmp23282, i64 1
+  %tmp23284 = getelementptr inbounds float, float* %tmp23283, i64 1
+  %tmp23285 = getelementptr inbounds float, float* %tmp23284, i64 1
+  %tmp23286 = getelementptr inbounds float, float* %tmp23285, i64 1
+  %tmp23287 = getelementptr inbounds float, float* %tmp23286, i64 1
+  %tmp23288 = getelementptr inbounds float, float* %tmp23287, i64 1
+  %tmp23289 = getelementptr inbounds float, float* %tmp23288, i64 1
+  %tmp23290 = getelementptr inbounds float, float* %tmp23289, i64 1
+  %tmp23291 = getelementptr inbounds float, float* %tmp23290, i64 1
+  %tmp23292 = getelementptr inbounds float, float* %tmp23291, i64 1
+  %tmp23293 = getelementptr inbounds float, float* %tmp23292, i64 1
+  %tmp23294 = getelementptr inbounds float, float* %tmp23293, i64 1
+  %tmp23295 = getelementptr inbounds float, float* %tmp23294, i64 1
+  %tmp23296 = getelementptr inbounds float, float* %tmp23295, i64 1
+  %tmp23297 = getelementptr inbounds float, float* %tmp23296, i64 1
+  %tmp23298 = getelementptr inbounds float, float* %tmp23297, i64 1
+  %tmp23299 = getelementptr inbounds float, float* %tmp23298, i64 1
+  %tmp23300 = getelementptr inbounds float, float* %tmp23299, i64 1
+  %tmp23301 = getelementptr inbounds float, float* %tmp23300, i64 1
+  %tmp23302 = getelementptr inbounds float, float* %tmp23301, i64 1
+  %tmp23303 = getelementptr inbounds float, float* %tmp23302, i64 1
+  %tmp23304 = getelementptr inbounds float, float* %tmp23303, i64 1
+  %tmp23305 = getelementptr inbounds float, float* %tmp23304, i64 1
+  %tmp23306 = getelementptr inbounds float, float* %tmp23305, i64 1
+  %tmp23307 = getelementptr inbounds float, float* %tmp23306, i64 1
+  %tmp23308 = getelementptr inbounds float, float* %tmp23307, i64 1
+  %tmp23309 = getelementptr inbounds float, float* %tmp23308, i64 1
+  %tmp23310 = getelementptr inbounds float, float* %tmp23309, i64 1
+  %tmp23311 = getelementptr inbounds float, float* %tmp23310, i64 1
+  %tmp23312 = getelementptr inbounds float, float* %tmp23311, i64 1
+  %tmp23313 = getelementptr inbounds float, float* %tmp23312, i64 1
+  %tmp23314 = getelementptr inbounds float, float* %tmp23313, i64 1
+  %tmp23315 = getelementptr inbounds float, float* %tmp23314, i64 1
+  %tmp23316 = getelementptr inbounds float, float* %tmp23315, i64 1
+  %tmp23317 = getelementptr inbounds float, float* %tmp23316, i64 1
+  %tmp23318 = getelementptr inbounds float, float* %tmp23317, i64 1
+  %tmp23319 = getelementptr inbounds float, float* %tmp23318, i64 1
+  %tmp23320 = getelementptr inbounds float, float* %tmp23319, i64 1
+  %tmp23321 = getelementptr inbounds float, float* %tmp23320, i64 1
+  %tmp23322 = getelementptr inbounds float, float* %tmp23321, i64 1
+  %tmp23323 = getelementptr inbounds float, float* %tmp23322, i64 1
+  %tmp23324 = getelementptr inbounds float, float* %tmp23323, i64 1
+  %tmp23325 = getelementptr inbounds float, float* %tmp23324, i64 1
+  %tmp23326 = getelementptr inbounds float, float* %tmp23325, i64 1
+  %tmp23327 = getelementptr inbounds float, float* %tmp23326, i64 1
+  %tmp23328 = getelementptr inbounds float, float* %tmp23327, i64 1
+  %tmp23329 = getelementptr inbounds float, float* %tmp23328, i64 1
+  %tmp23330 = getelementptr inbounds float, float* %tmp23329, i64 1
+  %tmp23331 = getelementptr inbounds float, float* %tmp23330, i64 1
+  %tmp23332 = getelementptr inbounds float, float* %tmp23331, i64 1
+  %tmp23333 = getelementptr inbounds float, float* %tmp23332, i64 1
+  %tmp23334 = getelementptr inbounds float, float* %tmp23333, i64 1
+  %tmp23335 = getelementptr inbounds float, float* %tmp23334, i64 1
+  %tmp23336 = getelementptr inbounds float, float* %tmp23335, i64 1
+  %tmp23337 = getelementptr inbounds float, float* %tmp23336, i64 1
+  %tmp23338 = getelementptr inbounds float, float* %tmp23337, i64 1
+  %tmp23339 = getelementptr inbounds float, float* %tmp23338, i64 1
+  %tmp23340 = getelementptr inbounds float, float* %tmp23339, i64 1
+  %tmp23341 = getelementptr inbounds float, float* %tmp23340, i64 1
+  %tmp23342 = getelementptr inbounds float, float* %tmp23341, i64 1
+  %tmp23343 = getelementptr inbounds float, float* %tmp23342, i64 1
+  %tmp23344 = getelementptr inbounds float, float* %tmp23343, i64 1
+  %tmp23345 = getelementptr inbounds float, float* %tmp23344, i64 1
+  %tmp23346 = getelementptr inbounds float, float* %tmp23345, i64 1
+  %tmp23347 = getelementptr inbounds float, float* %tmp23346, i64 1
+  %tmp23348 = getelementptr inbounds float, float* %tmp23347, i64 1
+  %tmp23349 = getelementptr inbounds float, float* %tmp23348, i64 1
+  %tmp23350 = getelementptr inbounds float, float* %tmp23349, i64 1
+  %tmp23351 = getelementptr inbounds float, float* %tmp23350, i64 1
+  %tmp23352 = getelementptr inbounds float, float* %tmp23351, i64 1
+  %tmp23353 = getelementptr inbounds float, float* %tmp23352, i64 1
+  %tmp23354 = getelementptr inbounds float, float* %tmp23353, i64 1
+  %tmp23355 = getelementptr inbounds float, float* %tmp23354, i64 1
+  %tmp23356 = getelementptr inbounds float, float* %tmp23355, i64 1
+  %tmp23357 = getelementptr inbounds float, float* %tmp23356, i64 1
+  %tmp23358 = getelementptr inbounds float, float* %tmp23357, i64 1
+  %tmp23359 = getelementptr inbounds float, float* %tmp23358, i64 1
+  %tmp23360 = getelementptr inbounds float, float* %tmp23359, i64 1
+  %tmp23361 = getelementptr inbounds float, float* %tmp23360, i64 1
+  %tmp23362 = getelementptr inbounds float, float* %tmp23361, i64 1
+  %tmp23363 = getelementptr inbounds float, float* %tmp23362, i64 1
+  %tmp23364 = getelementptr inbounds float, float* %tmp23363, i64 1
+  %tmp23365 = getelementptr inbounds float, float* %tmp23364, i64 1
+  %tmp23366 = getelementptr inbounds float, float* %tmp23365, i64 1
+  %tmp23367 = getelementptr inbounds float, float* %tmp23366, i64 1
+  %tmp23368 = getelementptr inbounds float, float* %tmp23367, i64 1
+  %tmp23369 = getelementptr inbounds float, float* %tmp23368, i64 1
+  %tmp23370 = getelementptr inbounds float, float* %tmp23369, i64 1
+  %tmp23371 = getelementptr inbounds float, float* %tmp23370, i64 1
+  %tmp23372 = getelementptr inbounds float, float* %tmp23371, i64 1
+  %tmp23373 = getelementptr inbounds float, float* %tmp23372, i64 1
+  %tmp23374 = getelementptr inbounds float, float* %tmp23373, i64 1
+  %tmp23375 = getelementptr inbounds float, float* %tmp23374, i64 1
+  %tmp23376 = getelementptr inbounds float, float* %tmp23375, i64 1
+  %tmp23377 = getelementptr inbounds float, float* %tmp23376, i64 1
+  %tmp23378 = getelementptr inbounds float, float* %tmp23377, i64 1
+  %tmp23379 = getelementptr inbounds float, float* %tmp23378, i64 1
+  %tmp23380 = getelementptr inbounds float, float* %tmp23379, i64 1
+  %tmp23381 = getelementptr inbounds float, float* %tmp23380, i64 1
+  %tmp23382 = getelementptr inbounds float, float* %tmp23381, i64 1
+  %tmp23383 = getelementptr inbounds float, float* %tmp23382, i64 1
+  %tmp23384 = getelementptr inbounds float, float* %tmp23383, i64 1
+  %tmp23385 = getelementptr inbounds float, float* %tmp23384, i64 1
+  %tmp23386 = getelementptr inbounds float, float* %tmp23385, i64 1
+  %tmp23387 = getelementptr inbounds float, float* %tmp23386, i64 1
+  %tmp23388 = getelementptr inbounds float, float* %tmp23387, i64 1
+  %tmp23389 = getelementptr inbounds float, float* %tmp23388, i64 1
+  %tmp23390 = getelementptr inbounds float, float* %tmp23389, i64 1
+  %tmp23391 = getelementptr inbounds float, float* %tmp23390, i64 1
+  %tmp23392 = getelementptr inbounds float, float* %tmp23391, i64 1
+  %tmp23393 = getelementptr inbounds float, float* %tmp23392, i64 1
+  %tmp23394 = getelementptr inbounds float, float* %tmp23393, i64 1
+  %tmp23395 = getelementptr inbounds float, float* %tmp23394, i64 1
+  %tmp23396 = getelementptr inbounds float, float* %tmp23395, i64 1
+  %tmp23397 = getelementptr inbounds float, float* %tmp23396, i64 1
+  %tmp23398 = getelementptr inbounds float, float* %tmp23397, i64 1
+  %tmp23399 = getelementptr inbounds float, float* %tmp23398, i64 1
+  %tmp23400 = getelementptr inbounds float, float* %tmp23399, i64 1
+  %tmp23401 = getelementptr inbounds float, float* %tmp23400, i64 1
+  %tmp23402 = getelementptr inbounds float, float* %tmp23401, i64 1
+  %tmp23403 = getelementptr inbounds float, float* %tmp23402, i64 1
+  %tmp23404 = getelementptr inbounds float, float* %tmp23403, i64 1
+  %tmp23405 = getelementptr inbounds float, float* %tmp23404, i64 1
+  %tmp23406 = getelementptr inbounds float, float* %tmp23405, i64 1
+  %tmp23407 = getelementptr inbounds float, float* %tmp23406, i64 1
+  %tmp23408 = getelementptr inbounds float, float* %tmp23407, i64 1
+  %tmp23409 = getelementptr inbounds float, float* %tmp23408, i64 1
+  %tmp23410 = getelementptr inbounds float, float* %tmp23409, i64 1
+  %tmp23411 = getelementptr inbounds float, float* %tmp23410, i64 1
+  %tmp23412 = getelementptr inbounds float, float* %tmp23411, i64 1
+  %tmp23413 = getelementptr inbounds float, float* %tmp23412, i64 1
+  %tmp23414 = getelementptr inbounds float, float* %tmp23413, i64 1
+  %tmp23415 = getelementptr inbounds float, float* %tmp23414, i64 1
+  %tmp23416 = getelementptr inbounds float, float* %tmp23415, i64 1
+  %tmp23417 = getelementptr inbounds float, float* %tmp23416, i64 1
+  %tmp23418 = getelementptr inbounds float, float* %tmp23417, i64 1
+  %tmp23419 = getelementptr inbounds float, float* %tmp23418, i64 1
+  %tmp23420 = getelementptr inbounds float, float* %tmp23419, i64 1
+  %tmp23421 = getelementptr inbounds float, float* %tmp23420, i64 1
+  %tmp23422 = getelementptr inbounds float, float* %tmp23421, i64 1
+  %tmp23423 = getelementptr inbounds float, float* %tmp23422, i64 1
+  %tmp23424 = getelementptr inbounds float, float* %tmp23423, i64 1
+  %tmp23425 = getelementptr inbounds float, float* %tmp23424, i64 1
+  %tmp23426 = getelementptr inbounds float, float* %tmp23425, i64 1
+  %tmp23427 = getelementptr inbounds float, float* %tmp23426, i64 1
+  %tmp23428 = getelementptr inbounds float, float* %tmp23427, i64 1
+  %tmp23429 = getelementptr inbounds float, float* %tmp23428, i64 1
+  %tmp23430 = getelementptr inbounds float, float* %tmp23429, i64 1
+  %tmp23431 = getelementptr inbounds float, float* %tmp23430, i64 1
+  %tmp23432 = getelementptr inbounds float, float* %tmp23431, i64 1
+  %tmp23433 = getelementptr inbounds float, float* %tmp23432, i64 1
+  %tmp23434 = getelementptr inbounds float, float* %tmp23433, i64 1
+  %tmp23435 = getelementptr inbounds float, float* %tmp23434, i64 1
+  %tmp23436 = getelementptr inbounds float, float* %tmp23435, i64 1
+  %tmp23437 = getelementptr inbounds float, float* %tmp23436, i64 1
+  %tmp23438 = getelementptr inbounds float, float* %tmp23437, i64 1
+  %tmp23439 = getelementptr inbounds float, float* %tmp23438, i64 1
+  %tmp23440 = getelementptr inbounds float, float* %tmp23439, i64 1
+  %tmp23441 = getelementptr inbounds float, float* %tmp23440, i64 1
+  %tmp23442 = getelementptr inbounds float, float* %tmp23441, i64 1
+  %tmp23443 = getelementptr inbounds float, float* %tmp23442, i64 1
+  %tmp23444 = getelementptr inbounds float, float* %tmp23443, i64 1
+  %tmp23445 = getelementptr inbounds float, float* %tmp23444, i64 1
+  %tmp23446 = getelementptr inbounds float, float* %tmp23445, i64 1
+  %tmp23447 = getelementptr inbounds float, float* %tmp23446, i64 1
+  %tmp23448 = getelementptr inbounds float, float* %tmp23447, i64 1
+  %tmp23449 = getelementptr inbounds float, float* %tmp23448, i64 1
+  %tmp23450 = getelementptr inbounds float, float* %tmp23449, i64 1
+  %tmp23451 = getelementptr inbounds float, float* %tmp23450, i64 1
+  %tmp23452 = getelementptr inbounds float, float* %tmp23451, i64 1
+  %tmp23453 = getelementptr inbounds float, float* %tmp23452, i64 1
+  %tmp23454 = getelementptr inbounds float, float* %tmp23453, i64 1
+  %tmp23455 = getelementptr inbounds float, float* %tmp23454, i64 1
+  %tmp23456 = getelementptr inbounds float, float* %tmp23455, i64 1
+  %tmp23457 = getelementptr inbounds float, float* %tmp23456, i64 1
+  %tmp23458 = getelementptr inbounds float, float* %tmp23457, i64 1
+  %tmp23459 = getelementptr inbounds float, float* %tmp23458, i64 1
+  %tmp23460 = getelementptr inbounds float, float* %tmp23459, i64 1
+  %tmp23461 = getelementptr inbounds float, float* %tmp23460, i64 1
+  %tmp23462 = getelementptr inbounds float, float* %tmp23461, i64 1
+  %tmp23463 = getelementptr inbounds float, float* %tmp23462, i64 1
+  %tmp23464 = getelementptr inbounds float, float* %tmp23463, i64 1
+  %tmp23465 = getelementptr inbounds float, float* %tmp23464, i64 1
+  %tmp23466 = getelementptr inbounds float, float* %tmp23465, i64 1
+  %tmp23467 = getelementptr inbounds float, float* %tmp23466, i64 1
+  %tmp23468 = getelementptr inbounds float, float* %tmp23467, i64 1
+  %tmp23469 = getelementptr inbounds float, float* %tmp23468, i64 1
+  %tmp23470 = getelementptr inbounds float, float* %tmp23469, i64 1
+  %tmp23471 = getelementptr inbounds float, float* %tmp23470, i64 1
+  %tmp23472 = getelementptr inbounds float, float* %tmp23471, i64 1
+  %tmp23473 = getelementptr inbounds float, float* %tmp23472, i64 1
+  %tmp23474 = getelementptr inbounds float, float* %tmp23473, i64 1
+  %tmp23475 = getelementptr inbounds float, float* %tmp23474, i64 1
+  %tmp23476 = getelementptr inbounds float, float* %tmp23475, i64 1
+  %tmp23477 = getelementptr inbounds float, float* %tmp23476, i64 1
+  %tmp23478 = getelementptr inbounds float, float* %tmp23477, i64 1
+  %tmp23479 = getelementptr inbounds float, float* %tmp23478, i64 1
+  %tmp23480 = getelementptr inbounds float, float* %tmp23479, i64 1
+  %tmp23481 = getelementptr inbounds float, float* %tmp23480, i64 1
+  %tmp23482 = getelementptr inbounds float, float* %tmp23481, i64 1
+  %tmp23483 = getelementptr inbounds float, float* %tmp23482, i64 1
+  %tmp23484 = getelementptr inbounds float, float* %tmp23483, i64 1
+  %tmp23485 = getelementptr inbounds float, float* %tmp23484, i64 1
+  %tmp23486 = getelementptr inbounds float, float* %tmp23485, i64 1
+  %tmp23487 = getelementptr inbounds float, float* %tmp23486, i64 1
+  %tmp23488 = getelementptr inbounds float, float* %tmp23487, i64 1
+  %tmp23489 = getelementptr inbounds float, float* %tmp23488, i64 1
+  %tmp23490 = getelementptr inbounds float, float* %tmp23489, i64 1
+  %tmp23491 = getelementptr inbounds float, float* %tmp23490, i64 1
+  %tmp23492 = getelementptr inbounds float, float* %tmp23491, i64 1
+  %tmp23493 = getelementptr inbounds float, float* %tmp23492, i64 1
+  %tmp23494 = getelementptr inbounds float, float* %tmp23493, i64 1
+  %tmp23495 = getelementptr inbounds float, float* %tmp23494, i64 1
+  %tmp23496 = getelementptr inbounds float, float* %tmp23495, i64 1
+  %tmp23497 = getelementptr inbounds float, float* %tmp23496, i64 1
+  %tmp23498 = getelementptr inbounds float, float* %tmp23497, i64 1
+  %tmp23499 = getelementptr inbounds float, float* %tmp23498, i64 1
+  %tmp23500 = getelementptr inbounds float, float* %tmp23499, i64 1
+  %tmp23501 = getelementptr inbounds float, float* %tmp23500, i64 1
+  %tmp23502 = getelementptr inbounds float, float* %tmp23501, i64 1
+  %tmp23503 = getelementptr inbounds float, float* %tmp23502, i64 1
+  %tmp23504 = getelementptr inbounds float, float* %tmp23503, i64 1
+  %tmp23505 = getelementptr inbounds float, float* %tmp23504, i64 1
+  %tmp23506 = getelementptr inbounds float, float* %tmp23505, i64 1
+  %tmp23507 = getelementptr inbounds float, float* %tmp23506, i64 1
+  %tmp23508 = getelementptr inbounds float, float* %tmp23507, i64 1
+  %tmp23509 = getelementptr inbounds float, float* %tmp23508, i64 1
+  %tmp23510 = getelementptr inbounds float, float* %tmp23509, i64 1
+  %tmp23511 = getelementptr inbounds float, float* %tmp23510, i64 1
+  %tmp23512 = getelementptr inbounds float, float* %tmp23511, i64 1
+  %tmp23513 = getelementptr inbounds float, float* %tmp23512, i64 1
+  %tmp23514 = getelementptr inbounds float, float* %tmp23513, i64 1
+  %tmp23515 = getelementptr inbounds float, float* %tmp23514, i64 1
+  %tmp23516 = getelementptr inbounds float, float* %tmp23515, i64 1
+  %tmp23517 = getelementptr inbounds float, float* %tmp23516, i64 1
+  %tmp23518 = getelementptr inbounds float, float* %tmp23517, i64 1
+  %tmp23519 = getelementptr inbounds float, float* %tmp23518, i64 1
+  %tmp23520 = getelementptr inbounds float, float* %tmp23519, i64 1
+  %tmp23521 = getelementptr inbounds float, float* %tmp23520, i64 1
+  %tmp23522 = getelementptr inbounds float, float* %tmp23521, i64 1
+  %tmp23523 = getelementptr inbounds float, float* %tmp23522, i64 1
+  %tmp23524 = getelementptr inbounds float, float* %tmp23523, i64 1
+  %tmp23525 = getelementptr inbounds float, float* %tmp23524, i64 1
+  %tmp23526 = getelementptr inbounds float, float* %tmp23525, i64 1
+  %tmp23527 = getelementptr inbounds float, float* %tmp23526, i64 1
+  %tmp23528 = getelementptr inbounds float, float* %tmp23527, i64 1
+  %tmp23529 = getelementptr inbounds float, float* %tmp23528, i64 1
+  %tmp23530 = getelementptr inbounds float, float* %tmp23529, i64 1
+  %tmp23531 = getelementptr inbounds float, float* %tmp23530, i64 1
+  %tmp23532 = getelementptr inbounds float, float* %tmp23531, i64 1
+  %tmp23533 = getelementptr inbounds float, float* %tmp23532, i64 1
+  %tmp23534 = getelementptr inbounds float, float* %tmp23533, i64 1
+  %tmp23535 = getelementptr inbounds float, float* %tmp23534, i64 1
+  %tmp23536 = getelementptr inbounds float, float* %tmp23535, i64 1
+  %tmp23537 = getelementptr inbounds float, float* %tmp23536, i64 1
+  %tmp23538 = getelementptr inbounds float, float* %tmp23537, i64 1
+  %tmp23539 = getelementptr inbounds float, float* %tmp23538, i64 1
+  %tmp23540 = getelementptr inbounds float, float* %tmp23539, i64 1
+  %tmp23541 = getelementptr inbounds float, float* %tmp23540, i64 1
+  %tmp23542 = getelementptr inbounds float, float* %tmp23541, i64 1
+  %tmp23543 = getelementptr inbounds float, float* %tmp23542, i64 1
+  %tmp23544 = getelementptr inbounds float, float* %tmp23543, i64 1
+  %tmp23545 = getelementptr inbounds float, float* %tmp23544, i64 1
+  %tmp23546 = getelementptr inbounds float, float* %tmp23545, i64 1
+  %tmp23547 = getelementptr inbounds float, float* %tmp23546, i64 1
+  %tmp23548 = getelementptr inbounds float, float* %tmp23547, i64 1
+  %tmp23549 = getelementptr inbounds float, float* %tmp23548, i64 1
+  %tmp23550 = getelementptr inbounds float, float* %tmp23549, i64 1
+  %tmp23551 = getelementptr inbounds float, float* %tmp23550, i64 1
+  %tmp23552 = getelementptr inbounds float, float* %tmp23551, i64 1
+  %tmp23553 = getelementptr inbounds float, float* %tmp23552, i64 1
+  %tmp23554 = getelementptr inbounds float, float* %tmp23553, i64 1
+  %tmp23555 = getelementptr inbounds float, float* %tmp23554, i64 1
+  %tmp23556 = getelementptr inbounds float, float* %tmp23555, i64 1
+  %tmp23557 = getelementptr inbounds float, float* %tmp23556, i64 1
+  %tmp23558 = getelementptr inbounds float, float* %tmp23557, i64 1
+  %tmp23559 = getelementptr inbounds float, float* %tmp23558, i64 1
+  %tmp23560 = getelementptr inbounds float, float* %tmp23559, i64 1
+  %tmp23561 = getelementptr inbounds float, float* %tmp23560, i64 1
+  %tmp23562 = getelementptr inbounds float, float* %tmp23561, i64 1
+  %tmp23563 = getelementptr inbounds float, float* %tmp23562, i64 1
+  %tmp23564 = getelementptr inbounds float, float* %tmp23563, i64 1
+  %tmp23565 = getelementptr inbounds float, float* %tmp23564, i64 1
+  %tmp23566 = getelementptr inbounds float, float* %tmp23565, i64 1
+  %tmp23567 = getelementptr inbounds float, float* %tmp23566, i64 1
+  %tmp23568 = getelementptr inbounds float, float* %tmp23567, i64 1
+  %tmp23569 = getelementptr inbounds float, float* %tmp23568, i64 1
+  %tmp23570 = getelementptr inbounds float, float* %tmp23569, i64 1
+  %tmp23571 = getelementptr inbounds float, float* %tmp23570, i64 1
+  %tmp23572 = getelementptr inbounds float, float* %tmp23571, i64 1
+  %tmp23573 = getelementptr inbounds float, float* %tmp23572, i64 1
+  %tmp23574 = getelementptr inbounds float, float* %tmp23573, i64 1
+  %tmp23575 = getelementptr inbounds float, float* %tmp23574, i64 1
+  %tmp23576 = getelementptr inbounds float, float* %tmp23575, i64 1
+  %tmp23577 = getelementptr inbounds float, float* %tmp23576, i64 1
+  %tmp23578 = getelementptr inbounds float, float* %tmp23577, i64 1
+  %tmp23579 = getelementptr inbounds float, float* %tmp23578, i64 1
+  %tmp23580 = getelementptr inbounds float, float* %tmp23579, i64 1
+  %tmp23581 = getelementptr inbounds float, float* %tmp23580, i64 1
+  %tmp23582 = getelementptr inbounds float, float* %tmp23581, i64 1
+  %tmp23583 = getelementptr inbounds float, float* %tmp23582, i64 1
+  %tmp23584 = getelementptr inbounds float, float* %tmp23583, i64 1
+  %tmp23585 = getelementptr inbounds float, float* %tmp23584, i64 1
+  %tmp23586 = getelementptr inbounds float, float* %tmp23585, i64 1
+  %tmp23587 = getelementptr inbounds float, float* %tmp23586, i64 1
+  %tmp23588 = getelementptr inbounds float, float* %tmp23587, i64 1
+  %tmp23589 = getelementptr inbounds float, float* %tmp23588, i64 1
+  %tmp23590 = getelementptr inbounds float, float* %tmp23589, i64 1
+  %tmp23591 = getelementptr inbounds float, float* %tmp23590, i64 1
+  %tmp23592 = getelementptr inbounds float, float* %tmp23591, i64 1
+  %tmp23593 = getelementptr inbounds float, float* %tmp23592, i64 1
+  %tmp23594 = getelementptr inbounds float, float* %tmp23593, i64 1
+  %tmp23595 = getelementptr inbounds float, float* %tmp23594, i64 1
+  %tmp23596 = getelementptr inbounds float, float* %tmp23595, i64 1
+  %tmp23597 = getelementptr inbounds float, float* %tmp23596, i64 1
+  %tmp23598 = getelementptr inbounds float, float* %tmp23597, i64 1
+  %tmp23599 = getelementptr inbounds float, float* %tmp23598, i64 1
+  %tmp23600 = getelementptr inbounds float, float* %tmp23599, i64 1
+  %tmp23601 = getelementptr inbounds float, float* %tmp23600, i64 1
+  %tmp23602 = getelementptr inbounds float, float* %tmp23601, i64 1
+  %tmp23603 = getelementptr inbounds float, float* %tmp23602, i64 1
+  %tmp23604 = getelementptr inbounds float, float* %tmp23603, i64 1
+  %tmp23605 = getelementptr inbounds float, float* %tmp23604, i64 1
+  %tmp23606 = getelementptr inbounds float, float* %tmp23605, i64 1
+  %tmp23607 = getelementptr inbounds float, float* %tmp23606, i64 1
+  %tmp23608 = getelementptr inbounds float, float* %tmp23607, i64 1
+  %tmp23609 = getelementptr inbounds float, float* %tmp23608, i64 1
+  %tmp23610 = getelementptr inbounds float, float* %tmp23609, i64 1
+  %tmp23611 = getelementptr inbounds float, float* %tmp23610, i64 1
+  %tmp23612 = getelementptr inbounds float, float* %tmp23611, i64 1
+  %tmp23613 = getelementptr inbounds float, float* %tmp23612, i64 1
+  %tmp23614 = getelementptr inbounds float, float* %tmp23613, i64 1
+  %tmp23615 = getelementptr inbounds float, float* %tmp23614, i64 1
+  %tmp23616 = getelementptr inbounds float, float* %tmp23615, i64 1
+  %tmp23617 = getelementptr inbounds float, float* %tmp23616, i64 1
+  %tmp23618 = getelementptr inbounds float, float* %tmp23617, i64 1
+  %tmp23619 = getelementptr inbounds float, float* %tmp23618, i64 1
+  %tmp23620 = getelementptr inbounds float, float* %tmp23619, i64 1
+  %tmp23621 = getelementptr inbounds float, float* %tmp23620, i64 1
+  %tmp23622 = getelementptr inbounds float, float* %tmp23621, i64 1
+  %tmp23623 = getelementptr inbounds float, float* %tmp23622, i64 1
+  %tmp23624 = getelementptr inbounds float, float* %tmp23623, i64 1
+  %tmp23625 = getelementptr inbounds float, float* %tmp23624, i64 1
+  %tmp23626 = getelementptr inbounds float, float* %tmp23625, i64 1
+  %tmp23627 = getelementptr inbounds float, float* %tmp23626, i64 1
+  %tmp23628 = getelementptr inbounds float, float* %tmp23627, i64 1
+  %tmp23629 = getelementptr inbounds float, float* %tmp23628, i64 1
+  %tmp23630 = getelementptr inbounds float, float* %tmp23629, i64 1
+  %tmp23631 = getelementptr inbounds float, float* %tmp23630, i64 1
+  %tmp23632 = getelementptr inbounds float, float* %tmp23631, i64 1
+  %tmp23633 = getelementptr inbounds float, float* %tmp23632, i64 1
+  %tmp23634 = getelementptr inbounds float, float* %tmp23633, i64 1
+  %tmp23635 = getelementptr inbounds float, float* %tmp23634, i64 1
+  %tmp23636 = getelementptr inbounds float, float* %tmp23635, i64 1
+  %tmp23637 = getelementptr inbounds float, float* %tmp23636, i64 1
+  %tmp23638 = getelementptr inbounds float, float* %tmp23637, i64 1
+  %tmp23639 = getelementptr inbounds float, float* %tmp23638, i64 1
+  %tmp23640 = getelementptr inbounds float, float* %tmp23639, i64 1
+  %tmp23641 = getelementptr inbounds float, float* %tmp23640, i64 1
+  %tmp23642 = getelementptr inbounds float, float* %tmp23641, i64 1
+  %tmp23643 = getelementptr inbounds float, float* %tmp23642, i64 1
+  %tmp23644 = getelementptr inbounds float, float* %tmp23643, i64 1
+  %tmp23645 = getelementptr inbounds float, float* %tmp23644, i64 1
+  %tmp23646 = getelementptr inbounds float, float* %tmp23645, i64 1
+  %tmp23647 = getelementptr inbounds float, float* %tmp23646, i64 1
+  %tmp23648 = getelementptr inbounds float, float* %tmp23647, i64 1
+  %tmp23649 = getelementptr inbounds float, float* %tmp23648, i64 1
+  %tmp23650 = getelementptr inbounds float, float* %tmp23649, i64 1
+  %tmp23651 = getelementptr inbounds float, float* %tmp23650, i64 1
+  %tmp23652 = getelementptr inbounds float, float* %tmp23651, i64 1
+  %tmp23653 = getelementptr inbounds float, float* %tmp23652, i64 1
+  %tmp23654 = getelementptr inbounds float, float* %tmp23653, i64 1
+  %tmp23655 = getelementptr inbounds float, float* %tmp23654, i64 1
+  %tmp23656 = getelementptr inbounds float, float* %tmp23655, i64 1
+  %tmp23657 = getelementptr inbounds float, float* %tmp23656, i64 1
+  %tmp23658 = getelementptr inbounds float, float* %tmp23657, i64 1
+  %tmp23659 = getelementptr inbounds float, float* %tmp23658, i64 1
+  %tmp23660 = getelementptr inbounds float, float* %tmp23659, i64 1
+  %tmp23661 = getelementptr inbounds float, float* %tmp23660, i64 1
+  %tmp23662 = getelementptr inbounds float, float* %tmp23661, i64 1
+  %tmp23663 = getelementptr inbounds float, float* %tmp23662, i64 1
+  %tmp23664 = getelementptr inbounds float, float* %tmp23663, i64 1
+  %tmp23665 = getelementptr inbounds float, float* %tmp23664, i64 1
+  %tmp23666 = getelementptr inbounds float, float* %tmp23665, i64 1
+  %tmp23667 = getelementptr inbounds float, float* %tmp23666, i64 1
+  %tmp23668 = getelementptr inbounds float, float* %tmp23667, i64 1
+  %tmp23669 = getelementptr inbounds float, float* %tmp23668, i64 1
+  %tmp23670 = getelementptr inbounds float, float* %tmp23669, i64 1
+  %tmp23671 = getelementptr inbounds float, float* %tmp23670, i64 1
+  %tmp23672 = getelementptr inbounds float, float* %tmp23671, i64 1
+  %tmp23673 = getelementptr inbounds float, float* %tmp23672, i64 1
+  %tmp23674 = getelementptr inbounds float, float* %tmp23673, i64 1
+  %tmp23675 = getelementptr inbounds float, float* %tmp23674, i64 1
+  %tmp23676 = getelementptr inbounds float, float* %tmp23675, i64 1
+  %tmp23677 = getelementptr inbounds float, float* %tmp23676, i64 1
+  %tmp23678 = getelementptr inbounds float, float* %tmp23677, i64 1
+  %tmp23679 = getelementptr inbounds float, float* %tmp23678, i64 1
+  %tmp23680 = getelementptr inbounds float, float* %tmp23679, i64 1
+  %tmp23681 = getelementptr inbounds float, float* %tmp23680, i64 1
+  %tmp23682 = getelementptr inbounds float, float* %tmp23681, i64 1
+  %tmp23683 = getelementptr inbounds float, float* %tmp23682, i64 1
+  %tmp23684 = getelementptr inbounds float, float* %tmp23683, i64 1
+  %tmp23685 = getelementptr inbounds float, float* %tmp23684, i64 1
+  %tmp23686 = getelementptr inbounds float, float* %tmp23685, i64 1
+  %tmp23687 = getelementptr inbounds float, float* %tmp23686, i64 1
+  %tmp23688 = getelementptr inbounds float, float* %tmp23687, i64 1
+  %tmp23689 = getelementptr inbounds float, float* %tmp23688, i64 1
+  %tmp23690 = getelementptr inbounds float, float* %tmp23689, i64 1
+  %tmp23691 = getelementptr inbounds float, float* %tmp23690, i64 1
+  %tmp23692 = getelementptr inbounds float, float* %tmp23691, i64 1
+  %tmp23693 = getelementptr inbounds float, float* %tmp23692, i64 1
+  %tmp23694 = getelementptr inbounds float, float* %tmp23693, i64 1
+  %tmp23695 = getelementptr inbounds float, float* %tmp23694, i64 1
+  %tmp23696 = getelementptr inbounds float, float* %tmp23695, i64 1
+  %tmp23697 = getelementptr inbounds float, float* %tmp23696, i64 1
+  %tmp23698 = getelementptr inbounds float, float* %tmp23697, i64 1
+  %tmp23699 = getelementptr inbounds float, float* %tmp23698, i64 1
+  %tmp23700 = getelementptr inbounds float, float* %tmp23699, i64 1
+  %tmp23701 = getelementptr inbounds float, float* %tmp23700, i64 1
+  %tmp23702 = getelementptr inbounds float, float* %tmp23701, i64 1
+  %tmp23703 = getelementptr inbounds float, float* %tmp23702, i64 1
+  %tmp23704 = getelementptr inbounds float, float* %tmp23703, i64 1
+  %tmp23705 = getelementptr inbounds float, float* %tmp23704, i64 1
+  %tmp23706 = getelementptr inbounds float, float* %tmp23705, i64 1
+  %tmp23707 = getelementptr inbounds float, float* %tmp23706, i64 1
+  %tmp23708 = getelementptr inbounds float, float* %tmp23707, i64 1
+  %tmp23709 = getelementptr inbounds float, float* %tmp23708, i64 1
+  %tmp23710 = getelementptr inbounds float, float* %tmp23709, i64 1
+  %tmp23711 = getelementptr inbounds float, float* %tmp23710, i64 1
+  %tmp23712 = getelementptr inbounds float, float* %tmp23711, i64 1
+  %tmp23713 = getelementptr inbounds float, float* %tmp23712, i64 1
+  %tmp23714 = getelementptr inbounds float, float* %tmp23713, i64 1
+  %tmp23715 = getelementptr inbounds float, float* %tmp23714, i64 1
+  %tmp23716 = getelementptr inbounds float, float* %tmp23715, i64 1
+  %tmp23717 = getelementptr inbounds float, float* %tmp23716, i64 1
+  %tmp23718 = getelementptr inbounds float, float* %tmp23717, i64 1
+  %tmp23719 = getelementptr inbounds float, float* %tmp23718, i64 1
+  %tmp23720 = getelementptr inbounds float, float* %tmp23719, i64 1
+  %tmp23721 = getelementptr inbounds float, float* %tmp23720, i64 1
+  %tmp23722 = getelementptr inbounds float, float* %tmp23721, i64 1
+  %tmp23723 = getelementptr inbounds float, float* %tmp23722, i64 1
+  %tmp23724 = getelementptr inbounds float, float* %tmp23723, i64 1
+  %tmp23725 = getelementptr inbounds float, float* %tmp23724, i64 1
+  %tmp23726 = getelementptr inbounds float, float* %tmp23725, i64 1
+  %tmp23727 = getelementptr inbounds float, float* %tmp23726, i64 1
+  %tmp23728 = getelementptr inbounds float, float* %tmp23727, i64 1
+  %tmp23729 = getelementptr inbounds float, float* %tmp23728, i64 1
+  %tmp23730 = getelementptr inbounds float, float* %tmp23729, i64 1
+  %tmp23731 = getelementptr inbounds float, float* %tmp23730, i64 1
+  %tmp23732 = getelementptr inbounds float, float* %tmp23731, i64 1
+  %tmp23733 = getelementptr inbounds float, float* %tmp23732, i64 1
+  %tmp23734 = getelementptr inbounds float, float* %tmp23733, i64 1
+  %tmp23735 = getelementptr inbounds float, float* %tmp23734, i64 1
+  %tmp23736 = getelementptr inbounds float, float* %tmp23735, i64 1
+  %tmp23737 = getelementptr inbounds float, float* %tmp23736, i64 1
+  %tmp23738 = getelementptr inbounds float, float* %tmp23737, i64 1
+  %tmp23739 = getelementptr inbounds float, float* %tmp23738, i64 1
+  %tmp23740 = getelementptr inbounds float, float* %tmp23739, i64 1
+  %tmp23741 = getelementptr inbounds float, float* %tmp23740, i64 1
+  %tmp23742 = getelementptr inbounds float, float* %tmp23741, i64 1
+  %tmp23743 = getelementptr inbounds float, float* %tmp23742, i64 1
+  %tmp23744 = getelementptr inbounds float, float* %tmp23743, i64 1
+  %tmp23745 = getelementptr inbounds float, float* %tmp23744, i64 1
+  %tmp23746 = getelementptr inbounds float, float* %tmp23745, i64 1
+  %tmp23747 = getelementptr inbounds float, float* %tmp23746, i64 1
+  %tmp23748 = getelementptr inbounds float, float* %tmp23747, i64 1
+  %tmp23749 = getelementptr inbounds float, float* %tmp23748, i64 1
+  %tmp23750 = getelementptr inbounds float, float* %tmp23749, i64 1
+  %tmp23751 = getelementptr inbounds float, float* %tmp23750, i64 1
+  %tmp23752 = getelementptr inbounds float, float* %tmp23751, i64 1
+  %tmp23753 = getelementptr inbounds float, float* %tmp23752, i64 1
+  %tmp23754 = getelementptr inbounds float, float* %tmp23753, i64 1
+  %tmp23755 = getelementptr inbounds float, float* %tmp23754, i64 1
+  %tmp23756 = getelementptr inbounds float, float* %tmp23755, i64 1
+  %tmp23757 = getelementptr inbounds float, float* %tmp23756, i64 1
+  %tmp23758 = getelementptr inbounds float, float* %tmp23757, i64 1
+  %tmp23759 = getelementptr inbounds float, float* %tmp23758, i64 1
+  %tmp23760 = getelementptr inbounds float, float* %tmp23759, i64 1
+  %tmp23761 = getelementptr inbounds float, float* %tmp23760, i64 1
+  %tmp23762 = getelementptr inbounds float, float* %tmp23761, i64 1
+  %tmp23763 = getelementptr inbounds float, float* %tmp23762, i64 1
+  %tmp23764 = getelementptr inbounds float, float* %tmp23763, i64 1
+  %tmp23765 = getelementptr inbounds float, float* %tmp23764, i64 1
+  %tmp23766 = getelementptr inbounds float, float* %tmp23765, i64 1
+  %tmp23767 = getelementptr inbounds float, float* %tmp23766, i64 1
+  %tmp23768 = getelementptr inbounds float, float* %tmp23767, i64 1
+  %tmp23769 = getelementptr inbounds float, float* %tmp23768, i64 1
+  %tmp23770 = getelementptr inbounds float, float* %tmp23769, i64 1
+  %tmp23771 = getelementptr inbounds float, float* %tmp23770, i64 1
+  %tmp23772 = getelementptr inbounds float, float* %tmp23771, i64 1
+  %tmp23773 = getelementptr inbounds float, float* %tmp23772, i64 1
+  %tmp23774 = getelementptr inbounds float, float* %tmp23773, i64 1
+  %tmp23775 = getelementptr inbounds float, float* %tmp23774, i64 1
+  %tmp23776 = getelementptr inbounds float, float* %tmp23775, i64 1
+  %tmp23777 = getelementptr inbounds float, float* %tmp23776, i64 1
+  %tmp23778 = getelementptr inbounds float, float* %tmp23777, i64 1
+  %tmp23779 = getelementptr inbounds float, float* %tmp23778, i64 1
+  %tmp23780 = getelementptr inbounds float, float* %tmp23779, i64 1
+  %tmp23781 = getelementptr inbounds float, float* %tmp23780, i64 1
+  %tmp23782 = getelementptr inbounds float, float* %tmp23781, i64 1
+  %tmp23783 = getelementptr inbounds float, float* %tmp23782, i64 1
+  %tmp23784 = getelementptr inbounds float, float* %tmp23783, i64 1
+  %tmp23785 = getelementptr inbounds float, float* %tmp23784, i64 1
+  %tmp23786 = getelementptr inbounds float, float* %tmp23785, i64 1
+  %tmp23787 = getelementptr inbounds float, float* %tmp23786, i64 1
+  %tmp23788 = getelementptr inbounds float, float* %tmp23787, i64 1
+  %tmp23789 = getelementptr inbounds float, float* %tmp23788, i64 1
+  %tmp23790 = getelementptr inbounds float, float* %tmp23789, i64 1
+  %tmp23791 = getelementptr inbounds float, float* %tmp23790, i64 1
+  %tmp23792 = getelementptr inbounds float, float* %tmp23791, i64 1
+  %tmp23793 = getelementptr inbounds float, float* %tmp23792, i64 1
+  %tmp23794 = getelementptr inbounds float, float* %tmp23793, i64 1
+  %tmp23795 = getelementptr inbounds float, float* %tmp23794, i64 1
+  %tmp23796 = getelementptr inbounds float, float* %tmp23795, i64 1
+  %tmp23797 = getelementptr inbounds float, float* %tmp23796, i64 1
+  %tmp23798 = getelementptr inbounds float, float* %tmp23797, i64 1
+  %tmp23799 = getelementptr inbounds float, float* %tmp23798, i64 1
+  %tmp23800 = getelementptr inbounds float, float* %tmp23799, i64 1
+  %tmp23801 = getelementptr inbounds float, float* %tmp23800, i64 1
+  %tmp23802 = getelementptr inbounds float, float* %tmp23801, i64 1
+  %tmp23803 = getelementptr inbounds float, float* %tmp23802, i64 1
+  %tmp23804 = getelementptr inbounds float, float* %tmp23803, i64 1
+  %tmp23805 = getelementptr inbounds float, float* %tmp23804, i64 1
+  %tmp23806 = getelementptr inbounds float, float* %tmp23805, i64 1
+  %tmp23807 = getelementptr inbounds float, float* %tmp23806, i64 1
+  %tmp23808 = getelementptr inbounds float, float* %tmp23807, i64 1
+  %tmp23809 = getelementptr inbounds float, float* %tmp23808, i64 1
+  %tmp23810 = getelementptr inbounds float, float* %tmp23809, i64 1
+  %tmp23811 = getelementptr inbounds float, float* %tmp23810, i64 1
+  %tmp23812 = getelementptr inbounds float, float* %tmp23811, i64 1
+  %tmp23813 = getelementptr inbounds float, float* %tmp23812, i64 1
+  %tmp23814 = getelementptr inbounds float, float* %tmp23813, i64 1
+  %tmp23815 = getelementptr inbounds float, float* %tmp23814, i64 1
+  %tmp23816 = getelementptr inbounds float, float* %tmp23815, i64 1
+  %tmp23817 = getelementptr inbounds float, float* %tmp23816, i64 1
+  %tmp23818 = getelementptr inbounds float, float* %tmp23817, i64 1
+  %tmp23819 = getelementptr inbounds float, float* %tmp23818, i64 1
+  %tmp23820 = getelementptr inbounds float, float* %tmp23819, i64 1
+  %tmp23821 = getelementptr inbounds float, float* %tmp23820, i64 1
+  %tmp23822 = getelementptr inbounds float, float* %tmp23821, i64 1
+  %tmp23823 = getelementptr inbounds float, float* %tmp23822, i64 1
+  %tmp23824 = getelementptr inbounds float, float* %tmp23823, i64 1
+  %tmp23825 = getelementptr inbounds float, float* %tmp23824, i64 1
+  %tmp23826 = getelementptr inbounds float, float* %tmp23825, i64 1
+  %tmp23827 = getelementptr inbounds float, float* %tmp23826, i64 1
+  %tmp23828 = getelementptr inbounds float, float* %tmp23827, i64 1
+  %tmp23829 = getelementptr inbounds float, float* %tmp23828, i64 1
+  %tmp23830 = getelementptr inbounds float, float* %tmp23829, i64 1
+  %tmp23831 = getelementptr inbounds float, float* %tmp23830, i64 1
+  %tmp23832 = getelementptr inbounds float, float* %tmp23831, i64 1
+  %tmp23833 = getelementptr inbounds float, float* %tmp23832, i64 1
+  %tmp23834 = getelementptr inbounds float, float* %tmp23833, i64 1
+  %tmp23835 = getelementptr inbounds float, float* %tmp23834, i64 1
+  %tmp23836 = getelementptr inbounds float, float* %tmp23835, i64 1
+  %tmp23837 = getelementptr inbounds float, float* %tmp23836, i64 1
+  %tmp23838 = getelementptr inbounds float, float* %tmp23837, i64 1
+  %tmp23839 = getelementptr inbounds float, float* %tmp23838, i64 1
+  %tmp23840 = getelementptr inbounds float, float* %tmp23839, i64 1
+  %tmp23841 = getelementptr inbounds float, float* %tmp23840, i64 1
+  %tmp23842 = getelementptr inbounds float, float* %tmp23841, i64 1
+  %tmp23843 = getelementptr inbounds float, float* %tmp23842, i64 1
+  %tmp23844 = getelementptr inbounds float, float* %tmp23843, i64 1
+  %tmp23845 = getelementptr inbounds float, float* %tmp23844, i64 1
+  %tmp23846 = getelementptr inbounds float, float* %tmp23845, i64 1
+  %tmp23847 = getelementptr inbounds float, float* %tmp23846, i64 1
+  %tmp23848 = getelementptr inbounds float, float* %tmp23847, i64 1
+  %tmp23849 = getelementptr inbounds float, float* %tmp23848, i64 1
+  %tmp23850 = getelementptr inbounds float, float* %tmp23849, i64 1
+  %tmp23851 = getelementptr inbounds float, float* %tmp23850, i64 1
+  %tmp23852 = getelementptr inbounds float, float* %tmp23851, i64 1
+  %tmp23853 = getelementptr inbounds float, float* %tmp23852, i64 1
+  %tmp23854 = getelementptr inbounds float, float* %tmp23853, i64 1
+  %tmp23855 = getelementptr inbounds float, float* %tmp23854, i64 1
+  %tmp23856 = getelementptr inbounds float, float* %tmp23855, i64 1
+  %tmp23857 = getelementptr inbounds float, float* %tmp23856, i64 1
+  %tmp23858 = getelementptr inbounds float, float* %tmp23857, i64 1
+  %tmp23859 = getelementptr inbounds float, float* %tmp23858, i64 1
+  %tmp23860 = getelementptr inbounds float, float* %tmp23859, i64 1
+  %tmp23861 = getelementptr inbounds float, float* %tmp23860, i64 1
+  %tmp23862 = getelementptr inbounds float, float* %tmp23861, i64 1
+  %tmp23863 = getelementptr inbounds float, float* %tmp23862, i64 1
+  %tmp23864 = getelementptr inbounds float, float* %tmp23863, i64 1
+  %tmp23865 = getelementptr inbounds float, float* %tmp23864, i64 1
+  %tmp23866 = getelementptr inbounds float, float* %tmp23865, i64 1
+  %tmp23867 = getelementptr inbounds float, float* %tmp23866, i64 1
+  %tmp23868 = getelementptr inbounds float, float* %tmp23867, i64 1
+  %tmp23869 = getelementptr inbounds float, float* %tmp23868, i64 1
+  %tmp23870 = getelementptr inbounds float, float* %tmp23869, i64 1
+  %tmp23871 = getelementptr inbounds float, float* %tmp23870, i64 1
+  %tmp23872 = getelementptr inbounds float, float* %tmp23871, i64 1
+  %tmp23873 = getelementptr inbounds float, float* %tmp23872, i64 1
+  %tmp23874 = getelementptr inbounds float, float* %tmp23873, i64 1
+  %tmp23875 = getelementptr inbounds float, float* %tmp23874, i64 1
+  %tmp23876 = getelementptr inbounds float, float* %tmp23875, i64 1
+  %tmp23877 = getelementptr inbounds float, float* %tmp23876, i64 1
+  %tmp23878 = getelementptr inbounds float, float* %tmp23877, i64 1
+  %tmp23879 = getelementptr inbounds float, float* %tmp23878, i64 1
+  %tmp23880 = getelementptr inbounds float, float* %tmp23879, i64 1
+  %tmp23881 = getelementptr inbounds float, float* %tmp23880, i64 1
+  %tmp23882 = getelementptr inbounds float, float* %tmp23881, i64 1
+  %tmp23883 = getelementptr inbounds float, float* %tmp23882, i64 1
+  %tmp23884 = getelementptr inbounds float, float* %tmp23883, i64 1
+  %tmp23885 = getelementptr inbounds float, float* %tmp23884, i64 1
+  %tmp23886 = getelementptr inbounds float, float* %tmp23885, i64 1
+  %tmp23887 = getelementptr inbounds float, float* %tmp23886, i64 1
+  %tmp23888 = getelementptr inbounds float, float* %tmp23887, i64 1
+  %tmp23889 = getelementptr inbounds float, float* %tmp23888, i64 1
+  %tmp23890 = getelementptr inbounds float, float* %tmp23889, i64 1
+  %tmp23891 = getelementptr inbounds float, float* %tmp23890, i64 1
+  %tmp23892 = getelementptr inbounds float, float* %tmp23891, i64 1
+  %tmp23893 = getelementptr inbounds float, float* %tmp23892, i64 1
+  %tmp23894 = getelementptr inbounds float, float* %tmp23893, i64 1
+  %tmp23895 = getelementptr inbounds float, float* %tmp23894, i64 1
+  %tmp23896 = getelementptr inbounds float, float* %tmp23895, i64 1
+  %tmp23897 = getelementptr inbounds float, float* %tmp23896, i64 1
+  %tmp23898 = getelementptr inbounds float, float* %tmp23897, i64 1
+  %tmp23899 = getelementptr inbounds float, float* %tmp23898, i64 1
+  %tmp23900 = getelementptr inbounds float, float* %tmp23899, i64 1
+  %tmp23901 = getelementptr inbounds float, float* %tmp23900, i64 1
+  %tmp23902 = getelementptr inbounds float, float* %tmp23901, i64 1
+  %tmp23903 = getelementptr inbounds float, float* %tmp23902, i64 1
+  %tmp23904 = getelementptr inbounds float, float* %tmp23903, i64 1
+  %tmp23905 = getelementptr inbounds float, float* %tmp23904, i64 1
+  %tmp23906 = getelementptr inbounds float, float* %tmp23905, i64 1
+  %tmp23907 = getelementptr inbounds float, float* %tmp23906, i64 1
+  %tmp23908 = getelementptr inbounds float, float* %tmp23907, i64 1
+  %tmp23909 = getelementptr inbounds float, float* %tmp23908, i64 1
+  %tmp23910 = getelementptr inbounds float, float* %tmp23909, i64 1
+  %tmp23911 = getelementptr inbounds float, float* %tmp23910, i64 1
+  %tmp23912 = getelementptr inbounds float, float* %tmp23911, i64 1
+  %tmp23913 = getelementptr inbounds float, float* %tmp23912, i64 1
+  %tmp23914 = getelementptr inbounds float, float* %tmp23913, i64 1
+  %tmp23915 = getelementptr inbounds float, float* %tmp23914, i64 1
+  %tmp23916 = getelementptr inbounds float, float* %tmp23915, i64 1
+  %tmp23917 = getelementptr inbounds float, float* %tmp23916, i64 1
+  %tmp23918 = getelementptr inbounds float, float* %tmp23917, i64 1
+  %tmp23919 = getelementptr inbounds float, float* %tmp23918, i64 1
+  %tmp23920 = getelementptr inbounds float, float* %tmp23919, i64 1
+  %tmp23921 = getelementptr inbounds float, float* %tmp23920, i64 1
+  %tmp23922 = getelementptr inbounds float, float* %tmp23921, i64 1
+  %tmp23923 = getelementptr inbounds float, float* %tmp23922, i64 1
+  %tmp23924 = getelementptr inbounds float, float* %tmp23923, i64 1
+  %tmp23925 = getelementptr inbounds float, float* %tmp23924, i64 1
+  %tmp23926 = getelementptr inbounds float, float* %tmp23925, i64 1
+  %tmp23927 = getelementptr inbounds float, float* %tmp23926, i64 1
+  %tmp23928 = getelementptr inbounds float, float* %tmp23927, i64 1
+  %tmp23929 = getelementptr inbounds float, float* %tmp23928, i64 1
+  %tmp23930 = getelementptr inbounds float, float* %tmp23929, i64 1
+  %tmp23931 = getelementptr inbounds float, float* %tmp23930, i64 1
+  %tmp23932 = getelementptr inbounds float, float* %tmp23931, i64 1
+  %tmp23933 = getelementptr inbounds float, float* %tmp23932, i64 1
+  %tmp23934 = getelementptr inbounds float, float* %tmp23933, i64 1
+  %tmp23935 = getelementptr inbounds float, float* %tmp23934, i64 1
+  %tmp23936 = getelementptr inbounds float, float* %tmp23935, i64 1
+  %tmp23937 = getelementptr inbounds float, float* %tmp23936, i64 1
+  %tmp23938 = getelementptr inbounds float, float* %tmp23937, i64 1
+  %tmp23939 = getelementptr inbounds float, float* %tmp23938, i64 1
+  %tmp23940 = getelementptr inbounds float, float* %tmp23939, i64 1
+  %tmp23941 = getelementptr inbounds float, float* %tmp23940, i64 1
+  %tmp23942 = getelementptr inbounds float, float* %tmp23941, i64 1
+  %tmp23943 = getelementptr inbounds float, float* %tmp23942, i64 1
+  %tmp23944 = getelementptr inbounds float, float* %tmp23943, i64 1
+  %tmp23945 = getelementptr inbounds float, float* %tmp23944, i64 1
+  %tmp23946 = getelementptr inbounds float, float* %tmp23945, i64 1
+  %tmp23947 = getelementptr inbounds float, float* %tmp23946, i64 1
+  %tmp23948 = getelementptr inbounds float, float* %tmp23947, i64 1
+  %tmp23949 = getelementptr inbounds float, float* %tmp23948, i64 1
+  %tmp23950 = getelementptr inbounds float, float* %tmp23949, i64 1
+  %tmp23951 = getelementptr inbounds float, float* %tmp23950, i64 1
+  %tmp23952 = getelementptr inbounds float, float* %tmp23951, i64 1
+  %tmp23953 = getelementptr inbounds float, float* %tmp23952, i64 1
+  %tmp23954 = getelementptr inbounds float, float* %tmp23953, i64 1
+  %tmp23955 = getelementptr inbounds float, float* %tmp23954, i64 1
+  %tmp23956 = getelementptr inbounds float, float* %tmp23955, i64 1
+  %tmp23957 = getelementptr inbounds float, float* %tmp23956, i64 1
+  %tmp23958 = getelementptr inbounds float, float* %tmp23957, i64 1
+  %tmp23959 = getelementptr inbounds float, float* %tmp23958, i64 1
+  %tmp23960 = getelementptr inbounds float, float* %tmp23959, i64 1
+  %tmp23961 = getelementptr inbounds float, float* %tmp23960, i64 1
+  %tmp23962 = getelementptr inbounds float, float* %tmp23961, i64 1
+  %tmp23963 = getelementptr inbounds float, float* %tmp23962, i64 1
+  %tmp23964 = getelementptr inbounds float, float* %tmp23963, i64 1
+  %tmp23965 = getelementptr inbounds float, float* %tmp23964, i64 1
+  %tmp23966 = getelementptr inbounds float, float* %tmp23965, i64 1
+  %tmp23967 = getelementptr inbounds float, float* %tmp23966, i64 1
+  %tmp23968 = getelementptr inbounds float, float* %tmp23967, i64 1
+  %tmp23969 = getelementptr inbounds float, float* %tmp23968, i64 1
+  %tmp23970 = getelementptr inbounds float, float* %tmp23969, i64 1
+  %tmp23971 = getelementptr inbounds float, float* %tmp23970, i64 1
+  %tmp23972 = getelementptr inbounds float, float* %tmp23971, i64 1
+  %tmp23973 = getelementptr inbounds float, float* %tmp23972, i64 1
+  %tmp23974 = getelementptr inbounds float, float* %tmp23973, i64 1
+  %tmp23975 = getelementptr inbounds float, float* %tmp23974, i64 1
+  %tmp23976 = getelementptr inbounds float, float* %tmp23975, i64 1
+  %tmp23977 = getelementptr inbounds float, float* %tmp23976, i64 1
+  %tmp23978 = getelementptr inbounds float, float* %tmp23977, i64 1
+  %tmp23979 = getelementptr inbounds float, float* %tmp23978, i64 1
+  %tmp23980 = getelementptr inbounds float, float* %tmp23979, i64 1
+  %tmp23981 = getelementptr inbounds float, float* %tmp23980, i64 1
+  %tmp23982 = getelementptr inbounds float, float* %tmp23981, i64 1
+  %tmp23983 = getelementptr inbounds float, float* %tmp23982, i64 1
+  %tmp23984 = getelementptr inbounds float, float* %tmp23983, i64 1
+  %tmp23985 = getelementptr inbounds float, float* %tmp23984, i64 1
+  %tmp23986 = getelementptr inbounds float, float* %tmp23985, i64 1
+  %tmp23987 = getelementptr inbounds float, float* %tmp23986, i64 1
+  %tmp23988 = getelementptr inbounds float, float* %tmp23987, i64 1
+  %tmp23989 = getelementptr inbounds float, float* %tmp23988, i64 1
+  %tmp23990 = getelementptr inbounds float, float* %tmp23989, i64 1
+  %tmp23991 = getelementptr inbounds float, float* %tmp23990, i64 1
+  %tmp23992 = getelementptr inbounds float, float* %tmp23991, i64 1
+  %tmp23993 = getelementptr inbounds float, float* %tmp23992, i64 1
+  %tmp23994 = getelementptr inbounds float, float* %tmp23993, i64 1
+  %tmp23995 = getelementptr inbounds float, float* %tmp23994, i64 1
+  %tmp23996 = getelementptr inbounds float, float* %tmp23995, i64 1
+  %tmp23997 = getelementptr inbounds float, float* %tmp23996, i64 1
+  %tmp23998 = getelementptr inbounds float, float* %tmp23997, i64 1
+  %tmp23999 = getelementptr inbounds float, float* %tmp23998, i64 1
+  %tmp24000 = getelementptr inbounds float, float* %tmp23999, i64 1
+  %tmp24001 = getelementptr inbounds float, float* %tmp24000, i64 1
+  %tmp24002 = getelementptr inbounds float, float* %tmp24001, i64 1
+  %tmp24003 = getelementptr inbounds float, float* %tmp24002, i64 1
+  %tmp24004 = getelementptr inbounds float, float* %tmp24003, i64 1
+  %tmp24005 = getelementptr inbounds float, float* %tmp24004, i64 1
+  %tmp24006 = getelementptr inbounds float, float* %tmp24005, i64 1
+  %tmp24007 = getelementptr inbounds float, float* %tmp24006, i64 1
+  %tmp24008 = getelementptr inbounds float, float* %tmp24007, i64 1
+  %tmp24009 = getelementptr inbounds float, float* %tmp24008, i64 1
+  %tmp24010 = getelementptr inbounds float, float* %tmp24009, i64 1
+  %tmp24011 = getelementptr inbounds float, float* %tmp24010, i64 1
+  %tmp24012 = getelementptr inbounds float, float* %tmp24011, i64 1
+  %tmp24013 = getelementptr inbounds float, float* %tmp24012, i64 1
+  %tmp24014 = getelementptr inbounds float, float* %tmp24013, i64 1
+  %tmp24015 = getelementptr inbounds float, float* %tmp24014, i64 1
+  %tmp24016 = getelementptr inbounds float, float* %tmp24015, i64 1
+  %tmp24017 = getelementptr inbounds float, float* %tmp24016, i64 1
+  %tmp24018 = getelementptr inbounds float, float* %tmp24017, i64 1
+  %tmp24019 = getelementptr inbounds float, float* %tmp24018, i64 1
+  %tmp24020 = getelementptr inbounds float, float* %tmp24019, i64 1
+  %tmp24021 = getelementptr inbounds float, float* %tmp24020, i64 1
+  %tmp24022 = getelementptr inbounds float, float* %tmp24021, i64 1
+  %tmp24023 = getelementptr inbounds float, float* %tmp24022, i64 1
+  %tmp24024 = getelementptr inbounds float, float* %tmp24023, i64 1
+  %tmp24025 = getelementptr inbounds float, float* %tmp24024, i64 1
+  %tmp24026 = getelementptr inbounds float, float* %tmp24025, i64 1
+  %tmp24027 = getelementptr inbounds float, float* %tmp24026, i64 1
+  %tmp24028 = getelementptr inbounds float, float* %tmp24027, i64 1
+  %tmp24029 = getelementptr inbounds float, float* %tmp24028, i64 1
+  %tmp24030 = getelementptr inbounds float, float* %tmp24029, i64 1
+  %tmp24031 = getelementptr inbounds float, float* %tmp24030, i64 1
+  %tmp24032 = getelementptr inbounds float, float* %tmp24031, i64 1
+  %tmp24033 = getelementptr inbounds float, float* %tmp24032, i64 1
+  %tmp24034 = getelementptr inbounds float, float* %tmp24033, i64 1
+  %tmp24035 = getelementptr inbounds float, float* %tmp24034, i64 1
+  %tmp24036 = getelementptr inbounds float, float* %tmp24035, i64 1
+  %tmp24037 = getelementptr inbounds float, float* %tmp24036, i64 1
+  %tmp24038 = getelementptr inbounds float, float* %tmp24037, i64 1
+  %tmp24039 = getelementptr inbounds float, float* %tmp24038, i64 1
+  %tmp24040 = getelementptr inbounds float, float* %tmp24039, i64 1
+  %tmp24041 = getelementptr inbounds float, float* %tmp24040, i64 1
+  %tmp24042 = getelementptr inbounds float, float* %tmp24041, i64 1
+  %tmp24043 = getelementptr inbounds float, float* %tmp24042, i64 1
+  %tmp24044 = getelementptr inbounds float, float* %tmp24043, i64 1
+  %tmp24045 = getelementptr inbounds float, float* %tmp24044, i64 1
+  %tmp24046 = getelementptr inbounds float, float* %tmp24045, i64 1
+  %tmp24047 = getelementptr inbounds float, float* %tmp24046, i64 1
+  %tmp24048 = getelementptr inbounds float, float* %tmp24047, i64 1
+  %tmp24049 = getelementptr inbounds float, float* %tmp24048, i64 1
+  %tmp24050 = getelementptr inbounds float, float* %tmp24049, i64 1
+  %tmp24051 = getelementptr inbounds float, float* %tmp24050, i64 1
+  %tmp24052 = getelementptr inbounds float, float* %tmp24051, i64 1
+  %tmp24053 = getelementptr inbounds float, float* %tmp24052, i64 1
+  %tmp24054 = getelementptr inbounds float, float* %tmp24053, i64 1
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+  %tmp24681 = getelementptr inbounds float, float* %tmp24680, i64 1
+  %tmp24682 = getelementptr inbounds float, float* %tmp24681, i64 1
+  %tmp24683 = getelementptr inbounds float, float* %tmp24682, i64 1
+  %tmp24684 = getelementptr inbounds float, float* %tmp24683, i64 1
+  %tmp24685 = getelementptr inbounds float, float* %tmp24684, i64 1
+  %tmp24686 = getelementptr inbounds float, float* %tmp24685, i64 1
+  %tmp24687 = getelementptr inbounds float, float* %tmp24686, i64 1
+  %tmp24688 = getelementptr inbounds float, float* %tmp24687, i64 1
+  %tmp24689 = getelementptr inbounds float, float* %tmp24688, i64 1
+  %tmp24690 = getelementptr inbounds float, float* %tmp24689, i64 1
+  %tmp24691 = getelementptr inbounds float, float* %tmp24690, i64 1
+  %tmp24692 = getelementptr inbounds float, float* %tmp24691, i64 1
+  %tmp24693 = getelementptr inbounds float, float* %tmp24692, i64 1
+  %tmp24694 = getelementptr inbounds float, float* %tmp24693, i64 1
+  %tmp24695 = getelementptr inbounds float, float* %tmp24694, i64 1
+  %tmp24696 = getelementptr inbounds float, float* %tmp24695, i64 1
+  %tmp24697 = getelementptr inbounds float, float* %tmp24696, i64 1
+  %tmp24698 = getelementptr inbounds float, float* %tmp24697, i64 1
+  %tmp24699 = getelementptr inbounds float, float* %tmp24698, i64 1
+  %tmp24700 = getelementptr inbounds float, float* %tmp24699, i64 1
+  %tmp24701 = getelementptr inbounds float, float* %tmp24700, i64 1
+  %tmp24702 = getelementptr inbounds float, float* %tmp24701, i64 1
+  %tmp24703 = getelementptr inbounds float, float* %tmp24702, i64 1
+  %tmp24704 = getelementptr inbounds float, float* %tmp24703, i64 1
+  %tmp24705 = getelementptr inbounds float, float* %tmp24704, i64 1
+  %tmp24706 = getelementptr inbounds float, float* %tmp24705, i64 1
+  %tmp24707 = getelementptr inbounds float, float* %tmp24706, i64 1
+  %tmp24708 = getelementptr inbounds float, float* %tmp24707, i64 1
+  %tmp24709 = getelementptr inbounds float, float* %tmp24708, i64 1
+  %tmp24710 = getelementptr inbounds float, float* %tmp24709, i64 1
+  %tmp24711 = getelementptr inbounds float, float* %tmp24710, i64 1
+  %tmp24712 = getelementptr inbounds float, float* %tmp24711, i64 1
+  %tmp24713 = getelementptr inbounds float, float* %tmp24712, i64 1
+  %tmp24714 = getelementptr inbounds float, float* %tmp24713, i64 1
+  %tmp24715 = getelementptr inbounds float, float* %tmp24714, i64 1
+  %tmp24716 = getelementptr inbounds float, float* %tmp24715, i64 1
+  %tmp24717 = getelementptr inbounds float, float* %tmp24716, i64 1
+  %tmp24718 = getelementptr inbounds float, float* %tmp24717, i64 1
+  %tmp24719 = getelementptr inbounds float, float* %tmp24718, i64 1
+  %tmp24720 = getelementptr inbounds float, float* %tmp24719, i64 1
+  %tmp24721 = getelementptr inbounds float, float* %tmp24720, i64 1
+  %tmp24722 = getelementptr inbounds float, float* %tmp24721, i64 1
+  %tmp24723 = getelementptr inbounds float, float* %tmp24722, i64 1
+  %tmp24724 = getelementptr inbounds float, float* %tmp24723, i64 1
+  %tmp24725 = getelementptr inbounds float, float* %tmp24724, i64 1
+  %tmp24726 = getelementptr inbounds float, float* %tmp24725, i64 1
+  %tmp24727 = getelementptr inbounds float, float* %tmp24726, i64 1
+  %tmp24728 = getelementptr inbounds float, float* %tmp24727, i64 1
+  %tmp24729 = getelementptr inbounds float, float* %tmp24728, i64 1
+  %tmp24730 = getelementptr inbounds float, float* %tmp24729, i64 1
+  %tmp24731 = getelementptr inbounds float, float* %tmp24730, i64 1
+  %tmp24732 = getelementptr inbounds float, float* %tmp24731, i64 1
+  %tmp24733 = getelementptr inbounds float, float* %tmp24732, i64 1
+  %tmp24734 = getelementptr inbounds float, float* %tmp24733, i64 1
+  %tmp24735 = getelementptr inbounds float, float* %tmp24734, i64 1
+  %tmp24736 = getelementptr inbounds float, float* %tmp24735, i64 1
+  %tmp24737 = getelementptr inbounds float, float* %tmp24736, i64 1
+  %tmp24738 = getelementptr inbounds float, float* %tmp24737, i64 1
+  %tmp24739 = getelementptr inbounds float, float* %tmp24738, i64 1
+  %tmp24740 = getelementptr inbounds float, float* %tmp24739, i64 1
+  %tmp24741 = getelementptr inbounds float, float* %tmp24740, i64 1
+  %tmp24742 = getelementptr inbounds float, float* %tmp24741, i64 1
+  %tmp24743 = getelementptr inbounds float, float* %tmp24742, i64 1
+  %tmp24744 = getelementptr inbounds float, float* %tmp24743, i64 1
+  %tmp24745 = getelementptr inbounds float, float* %tmp24744, i64 1
+  %tmp24746 = getelementptr inbounds float, float* %tmp24745, i64 1
+  %tmp24747 = getelementptr inbounds float, float* %tmp24746, i64 1
+  %tmp24748 = getelementptr inbounds float, float* %tmp24747, i64 1
+  %tmp24749 = getelementptr inbounds float, float* %tmp24748, i64 1
+  %tmp24750 = getelementptr inbounds float, float* %tmp24749, i64 1
+  %tmp24751 = getelementptr inbounds float, float* %tmp24750, i64 1
+  %tmp24752 = getelementptr inbounds float, float* %tmp24751, i64 1
+  %tmp24753 = getelementptr inbounds float, float* %tmp24752, i64 1
+  %tmp24754 = getelementptr inbounds float, float* %tmp24753, i64 1
+  %tmp24755 = getelementptr inbounds float, float* %tmp24754, i64 1
+  %tmp24756 = getelementptr inbounds float, float* %tmp24755, i64 1
+  %tmp24757 = getelementptr inbounds float, float* %tmp24756, i64 1
+  %tmp24758 = getelementptr inbounds float, float* %tmp24757, i64 1
+  %tmp24759 = getelementptr inbounds float, float* %tmp24758, i64 1
+  %tmp24760 = getelementptr inbounds float, float* %tmp24759, i64 1
+  %tmp24761 = getelementptr inbounds float, float* %tmp24760, i64 1
+  %tmp24762 = getelementptr inbounds float, float* %tmp24761, i64 1
+  %tmp24763 = getelementptr inbounds float, float* %tmp24762, i64 1
+  %tmp24764 = getelementptr inbounds float, float* %tmp24763, i64 1
+  %tmp24765 = getelementptr inbounds float, float* %tmp24764, i64 1
+  %tmp24766 = getelementptr inbounds float, float* %tmp24765, i64 1
+  %tmp24767 = getelementptr inbounds float, float* %tmp24766, i64 1
+  %tmp24768 = getelementptr inbounds float, float* %tmp24767, i64 1
+  %tmp24769 = getelementptr inbounds float, float* %tmp24768, i64 1
+  %tmp24770 = getelementptr inbounds float, float* %tmp24769, i64 1
+  %tmp24771 = getelementptr inbounds float, float* %tmp24770, i64 1
+  %tmp24772 = getelementptr inbounds float, float* %tmp24771, i64 1
+  %tmp24773 = getelementptr inbounds float, float* %tmp24772, i64 1
+  %tmp24774 = getelementptr inbounds float, float* %tmp24773, i64 1
+  %tmp24775 = getelementptr inbounds float, float* %tmp24774, i64 1
+  %tmp24776 = getelementptr inbounds float, float* %tmp24775, i64 1
+  %tmp24777 = getelementptr inbounds float, float* %tmp24776, i64 1
+  %tmp24778 = getelementptr inbounds float, float* %tmp24777, i64 1
+  %tmp24779 = getelementptr inbounds float, float* %tmp24778, i64 1
+  %tmp24780 = getelementptr inbounds float, float* %tmp24779, i64 1
+  %tmp24781 = getelementptr inbounds float, float* %tmp24780, i64 1
+  %tmp24782 = getelementptr inbounds float, float* %tmp24781, i64 1
+  %tmp24783 = getelementptr inbounds float, float* %tmp24782, i64 1
+  %tmp24784 = getelementptr inbounds float, float* %tmp24783, i64 1
+  %tmp24785 = getelementptr inbounds float, float* %tmp24784, i64 1
+  %tmp24786 = getelementptr inbounds float, float* %tmp24785, i64 1
+  %tmp24787 = getelementptr inbounds float, float* %tmp24786, i64 1
+  %tmp24788 = getelementptr inbounds float, float* %tmp24787, i64 1
+  %tmp24789 = getelementptr inbounds float, float* %tmp24788, i64 1
+  %tmp24790 = getelementptr inbounds float, float* %tmp24789, i64 1
+  %tmp24791 = getelementptr inbounds float, float* %tmp24790, i64 1
+  %tmp24792 = getelementptr inbounds float, float* %tmp24791, i64 1
+  %tmp24793 = getelementptr inbounds float, float* %tmp24792, i64 1
+  %tmp24794 = getelementptr inbounds float, float* %tmp24793, i64 1
+  %tmp24795 = getelementptr inbounds float, float* %tmp24794, i64 1
+  %tmp24796 = getelementptr inbounds float, float* %tmp24795, i64 1
+  %tmp24797 = getelementptr inbounds float, float* %tmp24796, i64 1
+  %tmp24798 = getelementptr inbounds float, float* %tmp24797, i64 1
+  %tmp24799 = getelementptr inbounds float, float* %tmp24798, i64 1
+  %tmp24800 = getelementptr inbounds float, float* %tmp24799, i64 1
+  %tmp24801 = getelementptr inbounds float, float* %tmp24800, i64 1
+  %tmp24802 = getelementptr inbounds float, float* %tmp24801, i64 1
+  %tmp24803 = getelementptr inbounds float, float* %tmp24802, i64 1
+  %tmp24804 = getelementptr inbounds float, float* %tmp24803, i64 1
+  %tmp24805 = getelementptr inbounds float, float* %tmp24804, i64 1
+  %tmp24806 = getelementptr inbounds float, float* %tmp24805, i64 1
+  %tmp24807 = getelementptr inbounds float, float* %tmp24806, i64 1
+  %tmp24808 = getelementptr inbounds float, float* %tmp24807, i64 1
+  %tmp24809 = getelementptr inbounds float, float* %tmp24808, i64 1
+  %tmp24810 = getelementptr inbounds float, float* %tmp24809, i64 1
+  %tmp24811 = getelementptr inbounds float, float* %tmp24810, i64 1
+  %tmp24812 = getelementptr inbounds float, float* %tmp24811, i64 1
+  %tmp24813 = getelementptr inbounds float, float* %tmp24812, i64 1
+  %tmp24814 = getelementptr inbounds float, float* %tmp24813, i64 1
+  %tmp24815 = getelementptr inbounds float, float* %tmp24814, i64 1
+  %tmp24816 = getelementptr inbounds float, float* %tmp24815, i64 1
+  %tmp24817 = getelementptr inbounds float, float* %tmp24816, i64 1
+  %tmp24818 = getelementptr inbounds float, float* %tmp24817, i64 1
+  %tmp24819 = getelementptr inbounds float, float* %tmp24818, i64 1
+  %tmp24820 = getelementptr inbounds float, float* %tmp24819, i64 1
+  %tmp24821 = getelementptr inbounds float, float* %tmp24820, i64 1
+  %tmp24822 = getelementptr inbounds float, float* %tmp24821, i64 1
+  %tmp24823 = getelementptr inbounds float, float* %tmp24822, i64 1
+  %tmp24824 = getelementptr inbounds float, float* %tmp24823, i64 1
+  %tmp24825 = getelementptr inbounds float, float* %tmp24824, i64 1
+  %tmp24826 = getelementptr inbounds float, float* %tmp24825, i64 1
+  %tmp24827 = getelementptr inbounds float, float* %tmp24826, i64 1
+  %tmp24828 = getelementptr inbounds float, float* %tmp24827, i64 1
+  %tmp24829 = getelementptr inbounds float, float* %tmp24828, i64 1
+  %tmp24830 = getelementptr inbounds float, float* %tmp24829, i64 1
+  %tmp24831 = getelementptr inbounds float, float* %tmp24830, i64 1
+  %tmp24832 = getelementptr inbounds float, float* %tmp24831, i64 1
+  %tmp24833 = getelementptr inbounds float, float* %tmp24832, i64 1
+  %tmp24834 = getelementptr inbounds float, float* %tmp24833, i64 1
+  %tmp24835 = getelementptr inbounds float, float* %tmp24834, i64 1
+  %tmp24836 = getelementptr inbounds float, float* %tmp24835, i64 1
+  %tmp24837 = getelementptr inbounds float, float* %tmp24836, i64 1
+  %tmp24838 = getelementptr inbounds float, float* %tmp24837, i64 1
+  %tmp24839 = getelementptr inbounds float, float* %tmp24838, i64 1
+  %tmp24840 = getelementptr inbounds float, float* %tmp24839, i64 1
+  %tmp24841 = getelementptr inbounds float, float* %tmp24840, i64 1
+  %tmp24842 = getelementptr inbounds float, float* %tmp24841, i64 1
+  %tmp24843 = getelementptr inbounds float, float* %tmp24842, i64 1
+  %tmp24844 = getelementptr inbounds float, float* %tmp24843, i64 1
+  %tmp24845 = getelementptr inbounds float, float* %tmp24844, i64 1
+  %tmp24846 = getelementptr inbounds float, float* %tmp24845, i64 1
+  %tmp24847 = getelementptr inbounds float, float* %tmp24846, i64 1
+  %tmp24848 = getelementptr inbounds float, float* %tmp24847, i64 1
+  %tmp24849 = getelementptr inbounds float, float* %tmp24848, i64 1
+  %tmp24850 = getelementptr inbounds float, float* %tmp24849, i64 1
+  %tmp24851 = getelementptr inbounds float, float* %tmp24850, i64 1
+  %tmp24852 = getelementptr inbounds float, float* %tmp24851, i64 1
+  %tmp24853 = getelementptr inbounds float, float* %tmp24852, i64 1
+  %tmp24854 = getelementptr inbounds float, float* %tmp24853, i64 1
+  %tmp24855 = getelementptr inbounds float, float* %tmp24854, i64 1
+  %tmp24856 = getelementptr inbounds float, float* %tmp24855, i64 1
+  %tmp24857 = getelementptr inbounds float, float* %tmp24856, i64 1
+  %tmp24858 = getelementptr inbounds float, float* %tmp24857, i64 1
+  %tmp24859 = getelementptr inbounds float, float* %tmp24858, i64 1
+  %tmp24860 = getelementptr inbounds float, float* %tmp24859, i64 1
+  %tmp24861 = getelementptr inbounds float, float* %tmp24860, i64 1
+  %tmp24862 = getelementptr inbounds float, float* %tmp24861, i64 1
+  %tmp24863 = getelementptr inbounds float, float* %tmp24862, i64 1
+  %tmp24864 = getelementptr inbounds float, float* %tmp24863, i64 1
+  %tmp24865 = getelementptr inbounds float, float* %tmp24864, i64 1
+  %tmp24866 = getelementptr inbounds float, float* %tmp24865, i64 1
+  %tmp24867 = getelementptr inbounds float, float* %tmp24866, i64 1
+  %tmp24868 = getelementptr inbounds float, float* %tmp24867, i64 1
+  %tmp24869 = getelementptr inbounds float, float* %tmp24868, i64 1
+  %tmp24870 = getelementptr inbounds float, float* %tmp24869, i64 1
+  %tmp24871 = getelementptr inbounds float, float* %tmp24870, i64 1
+  %tmp24872 = getelementptr inbounds float, float* %tmp24871, i64 1
+  %tmp24873 = getelementptr inbounds float, float* %tmp24872, i64 1
+  %tmp24874 = getelementptr inbounds float, float* %tmp24873, i64 1
+  %tmp24875 = getelementptr inbounds float, float* %tmp24874, i64 1
+  %tmp24876 = getelementptr inbounds float, float* %tmp24875, i64 1
+  %tmp24877 = getelementptr inbounds float, float* %tmp24876, i64 1
+  %tmp24878 = getelementptr inbounds float, float* %tmp24877, i64 1
+  %tmp24879 = getelementptr inbounds float, float* %tmp24878, i64 1
+  %tmp24880 = getelementptr inbounds float, float* %tmp24879, i64 1
+  %tmp24881 = getelementptr inbounds float, float* %tmp24880, i64 1
+  %tmp24882 = getelementptr inbounds float, float* %tmp24881, i64 1
+  %tmp24883 = getelementptr inbounds float, float* %tmp24882, i64 1
+  %tmp24884 = getelementptr inbounds float, float* %tmp24883, i64 1
+  %tmp24885 = getelementptr inbounds float, float* %tmp24884, i64 1
+  %tmp24886 = getelementptr inbounds float, float* %tmp24885, i64 1
+  %tmp24887 = getelementptr inbounds float, float* %tmp24886, i64 1
+  %tmp24888 = getelementptr inbounds float, float* %tmp24887, i64 1
+  %tmp24889 = getelementptr inbounds float, float* %tmp24888, i64 1
+  %tmp24890 = getelementptr inbounds float, float* %tmp24889, i64 1
+  %tmp24891 = getelementptr inbounds float, float* %tmp24890, i64 1
+  %tmp24892 = getelementptr inbounds float, float* %tmp24891, i64 1
+  %tmp24893 = getelementptr inbounds float, float* %tmp24892, i64 1
+  %tmp24894 = getelementptr inbounds float, float* %tmp24893, i64 1
+  %tmp24895 = getelementptr inbounds float, float* %tmp24894, i64 1
+  %tmp24896 = getelementptr inbounds float, float* %tmp24895, i64 1
+  %tmp24897 = getelementptr inbounds float, float* %tmp24896, i64 1
+  %tmp24898 = getelementptr inbounds float, float* %tmp24897, i64 1
+  %tmp24899 = getelementptr inbounds float, float* %tmp24898, i64 1
+  %tmp24900 = getelementptr inbounds float, float* %tmp24899, i64 1
+  %tmp24901 = getelementptr inbounds float, float* %tmp24900, i64 1
+  %tmp24902 = getelementptr inbounds float, float* %tmp24901, i64 1
+  %tmp24903 = getelementptr inbounds float, float* %tmp24902, i64 1
+  %tmp24904 = getelementptr inbounds float, float* %tmp24903, i64 1
+  %tmp24905 = getelementptr inbounds float, float* %tmp24904, i64 1
+  %tmp24906 = getelementptr inbounds float, float* %tmp24905, i64 1
+  %tmp24907 = getelementptr inbounds float, float* %tmp24906, i64 1
+  %tmp24908 = getelementptr inbounds float, float* %tmp24907, i64 1
+  %tmp24909 = getelementptr inbounds float, float* %tmp24908, i64 1
+  %tmp24910 = getelementptr inbounds float, float* %tmp24909, i64 1
+  %tmp24911 = getelementptr inbounds float, float* %tmp24910, i64 1
+  %tmp24912 = getelementptr inbounds float, float* %tmp24911, i64 1
+  %tmp24913 = getelementptr inbounds float, float* %tmp24912, i64 1
+  %tmp24914 = getelementptr inbounds float, float* %tmp24913, i64 1
+  %tmp24915 = getelementptr inbounds float, float* %tmp24914, i64 1
+  %tmp24916 = getelementptr inbounds float, float* %tmp24915, i64 1
+  %tmp24917 = getelementptr inbounds float, float* %tmp24916, i64 1
+  %tmp24918 = getelementptr inbounds float, float* %tmp24917, i64 1
+  %tmp24919 = getelementptr inbounds float, float* %tmp24918, i64 1
+  %tmp24920 = getelementptr inbounds float, float* %tmp24919, i64 1
+  %tmp24921 = getelementptr inbounds float, float* %tmp24920, i64 1
+  %tmp24922 = getelementptr inbounds float, float* %tmp24921, i64 1
+  %tmp24923 = getelementptr inbounds float, float* %tmp24922, i64 1
+  %tmp24924 = getelementptr inbounds float, float* %tmp24923, i64 1
+  %tmp24925 = getelementptr inbounds float, float* %tmp24924, i64 1
+  %tmp24926 = getelementptr inbounds float, float* %tmp24925, i64 1
+  %tmp24927 = getelementptr inbounds float, float* %tmp24926, i64 1
+  %tmp24928 = getelementptr inbounds float, float* %tmp24927, i64 1
+  %tmp24929 = getelementptr inbounds float, float* %tmp24928, i64 1
+  %tmp24930 = getelementptr inbounds float, float* %tmp24929, i64 1
+  %tmp24931 = getelementptr inbounds float, float* %tmp24930, i64 1
+  %tmp24932 = getelementptr inbounds float, float* %tmp24931, i64 1
+  %tmp24933 = getelementptr inbounds float, float* %tmp24932, i64 1
+  %tmp24934 = getelementptr inbounds float, float* %tmp24933, i64 1
+  %tmp24935 = getelementptr inbounds float, float* %tmp24934, i64 1
+  %tmp24936 = getelementptr inbounds float, float* %tmp24935, i64 1
+  %tmp24937 = getelementptr inbounds float, float* %tmp24936, i64 1
+  %tmp24938 = getelementptr inbounds float, float* %tmp24937, i64 1
+  %tmp24939 = getelementptr inbounds float, float* %tmp24938, i64 1
+  %tmp24940 = getelementptr inbounds float, float* %tmp24939, i64 1
+  %tmp24941 = getelementptr inbounds float, float* %tmp24940, i64 1
+  %tmp24942 = getelementptr inbounds float, float* %tmp24941, i64 1
+  %tmp24943 = getelementptr inbounds float, float* %tmp24942, i64 1
+  %tmp24944 = getelementptr inbounds float, float* %tmp24943, i64 1
+  %tmp24945 = getelementptr inbounds float, float* %tmp24944, i64 1
+  %tmp24946 = getelementptr inbounds float, float* %tmp24945, i64 1
   store float 0x3F43FD0D00000000, float* %tmp24946
-  %tmp24947 = getelementptr inbounds float* undef, i64 1
-  %tmp24948 = getelementptr inbounds float* undef, i64 1
-  %tmp24949 = getelementptr inbounds float* undef, i64 1
-  %tmp24950 = getelementptr inbounds float* undef, i64 1
-  %tmp24951 = getelementptr inbounds float* %tmp24950, i64 1
-  %tmp24952 = getelementptr inbounds float* undef, i64 1
-  %tmp24953 = getelementptr inbounds float* undef, i64 1
-  %tmp24954 = getelementptr inbounds float* undef, i64 1
-  %tmp24955 = getelementptr inbounds float* undef, i64 1
-  %tmp24956 = getelementptr inbounds float* undef, i64 1
-  %tmp24957 = getelementptr inbounds float* undef, i64 1
-  %tmp24958 = getelementptr inbounds float* %tmp24957, i64 1
-  %tmp24959 = getelementptr inbounds float* undef, i64 1
-  %tmp24960 = getelementptr inbounds float* undef, i64 1
-  %tmp24961 = getelementptr inbounds float* undef, i64 1
-  %tmp24962 = getelementptr inbounds float* undef, i64 1
-  %tmp24963 = getelementptr inbounds float* undef, i64 1
-  %tmp24964 = getelementptr inbounds float* undef, i64 1
-  %tmp24965 = getelementptr inbounds float* undef, i64 1
-  %tmp24966 = getelementptr inbounds float* %tmp24965, i64 1
-  %tmp24967 = getelementptr inbounds float* undef, i64 1
-  %tmp24968 = getelementptr inbounds float* undef, i64 1
-  %tmp24969 = getelementptr inbounds float* undef, i64 1
-  %tmp24970 = getelementptr inbounds float* undef, i64 1
-  %tmp24971 = getelementptr inbounds float* %tmp24970, i64 1
-  %tmp24972 = getelementptr inbounds float* %tmp24971, i64 1
-  %tmp24973 = getelementptr inbounds float* %tmp24972, i64 1
-  %tmp24974 = getelementptr inbounds float* undef, i64 1
-  %tmp24975 = getelementptr inbounds float* undef, i64 1
-  %tmp24976 = getelementptr inbounds float* %tmp24975, i64 1
-  %tmp24977 = getelementptr inbounds float* undef, i64 1
-  %tmp24978 = getelementptr inbounds float* undef, i64 1
-  %tmp24979 = getelementptr inbounds float* undef, i64 1
-  %tmp24980 = getelementptr inbounds float* undef, i64 1
-  %tmp24981 = getelementptr inbounds float* undef, i64 1
-  %tmp24982 = getelementptr inbounds float* undef, i64 1
-  %tmp24983 = getelementptr inbounds float* %tmp24982, i64 1
-  %tmp24984 = getelementptr inbounds float* undef, i64 1
-  %tmp24985 = getelementptr inbounds float* %tmp24984, i64 1
-  %tmp24986 = getelementptr inbounds float* undef, i64 1
-  %tmp24987 = getelementptr inbounds float* %tmp24986, i64 1
-  %tmp24988 = getelementptr inbounds float* %tmp24987, i64 1
-  %tmp24989 = getelementptr inbounds float* undef, i64 1
-  %tmp24990 = getelementptr inbounds float* undef, i64 1
-  %tmp24991 = getelementptr inbounds float* %tmp24990, i64 1
-  %tmp24992 = getelementptr inbounds float* undef, i64 1
-  %tmp24993 = getelementptr inbounds float* %tmp24992, i64 1
-  %tmp24994 = getelementptr inbounds float* %tmp24993, i64 1
-  %tmp24995 = getelementptr inbounds float* undef, i64 1
-  %tmp24996 = getelementptr inbounds float* undef, i64 1
-  %tmp24997 = getelementptr inbounds float* undef, i64 1
-  %tmp24998 = getelementptr inbounds float* undef, i64 1
-  %tmp24999 = getelementptr inbounds float* undef, i64 1
-  %tmp25000 = getelementptr inbounds float* undef, i64 1
-  %tmp25001 = getelementptr inbounds float* undef, i64 1
-  %tmp25002 = getelementptr inbounds float* undef, i64 1
-  %tmp25003 = getelementptr inbounds float* undef, i64 1
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+  %tmp25048 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25049 = getelementptr inbounds float, float* %tmp25048, i64 1
+  %tmp25050 = getelementptr inbounds float, float* %tmp25049, i64 1
+  %tmp25051 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25052 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25053 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25054 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25055 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25056 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25057 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25058 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25059 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25060 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25061 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25062 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25063 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25064 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25065 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25066 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25067 = getelementptr inbounds float, float* %tmp25066, i64 1
+  %tmp25068 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25069 = getelementptr inbounds float, float* %tmp25068, i64 1
+  %tmp25070 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25071 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25072 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25073 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25074 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25075 = getelementptr inbounds float, float* %tmp25074, i64 1
+  %tmp25076 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25077 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25078 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25079 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25080 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25081 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25082 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25083 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25084 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25085 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25086 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25087 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25088 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25089 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25090 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25091 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25092 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25093 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25094 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25095 = getelementptr inbounds float, float* %tmp25094, i64 1
+  %tmp25096 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25097 = getelementptr inbounds float, float* %tmp25096, i64 1
+  %tmp25098 = getelementptr inbounds float, float* %tmp25097, i64 1
+  %tmp25099 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25100 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25101 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25102 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25103 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25104 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25105 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25106 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25107 = getelementptr inbounds float, float* %tmp25106, i64 1
+  %tmp25108 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25109 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25110 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25111 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25112 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25113 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25114 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25115 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25116 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25117 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25118 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25119 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25120 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25121 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25122 = getelementptr inbounds float, float* %tmp25121, i64 1
+  %tmp25123 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25124 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25125 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25126 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25127 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25128 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25129 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25130 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25131 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25132 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25133 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25134 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25135 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25136 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25137 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25138 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25139 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25140 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25141 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25142 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25143 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25144 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25145 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25146 = getelementptr inbounds float, float* %tmp25145, i64 1
+  %tmp25147 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25148 = getelementptr inbounds float, float* %tmp25147, i64 1
+  %tmp25149 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25150 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25151 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25152 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25153 = getelementptr inbounds float, float* %tmp25152, i64 1
+  %tmp25154 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25155 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25156 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25157 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25158 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25159 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25160 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25161 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25162 = getelementptr inbounds float, float* %tmp25161, i64 1
+  %tmp25163 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25164 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25165 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25166 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25167 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25168 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25169 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25170 = getelementptr inbounds float, float* %tmp25169, i64 1
+  %tmp25171 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25172 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25173 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25174 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25175 = getelementptr inbounds float, float* %tmp25174, i64 1
+  %tmp25176 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25177 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25178 = getelementptr inbounds float, float* %tmp25177, i64 1
+  %tmp25179 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25180 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25181 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25182 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25183 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25184 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25185 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25186 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25187 = getelementptr inbounds float, float* %tmp25186, i64 1
+  %tmp25188 = getelementptr inbounds float, float* %tmp25187, i64 1
+  %tmp25189 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25190 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25191 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25192 = getelementptr inbounds float, float* %tmp25191, i64 1
+  %tmp25193 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25194 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25195 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25196 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25197 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25198 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25199 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25200 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25201 = getelementptr inbounds float, float* %tmp25200, i64 1
+  %tmp25202 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25203 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25204 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25205 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25206 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25207 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25208 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25209 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25210 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25211 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25212 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25213 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25214 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25215 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25216 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25217 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25218 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25219 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25220 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25221 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25222 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25223 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25224 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25225 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25226 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25227 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25228 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25229 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25230 = getelementptr inbounds float, float* %tmp25229, i64 1
+  %tmp25231 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25232 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25233 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25234 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25235 = getelementptr inbounds float, float* %tmp25234, i64 1
+  %tmp25236 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25237 = getelementptr inbounds float, float* %tmp25236, i64 1
+  %tmp25238 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25239 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25240 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25241 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25242 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25243 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25244 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25245 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25246 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25247 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25248 = getelementptr inbounds float, float* %tmp25247, i64 1
+  %tmp25249 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25250 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25251 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25252 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25253 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25254 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25255 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25256 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25257 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25258 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25259 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25260 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25261 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25262 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25263 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25264 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25265 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25266 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25267 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25268 = getelementptr inbounds float, float* undef, i64 1
+  %tmp25269 = getelementptr inbounds float, float* undef, i64 1
   br i1 undef, label %bb25270, label %bb25271
 
 bb25270:                                          ; preds = %bb2
@@ -25487,11 +25487,11 @@ bb25332:                                          ; preds = %bb25330, %bb25305
   br i1 undef, label %bb25333, label %bb25357
 
 bb25333:                                          ; preds = %bb25332
-  invoke void (...)* @printf()
+  invoke void (...) @printf()
           to label %bb25334 unwind label %bb25324
 
 bb25334:                                          ; preds = %bb25333
-  invoke void (...)* @printf(i32 undef)
+  invoke void (...) @printf(i32 undef)
           to label %bb25335 unwind label %bb25324
 
 bb25335:                                          ; preds = %bb25334
@@ -25501,7 +25501,7 @@ bb25336:                                          ; preds = %bb25338, %bb25335
   br i1 undef, label %bb25337, label %bb25339
 
 bb25337:                                          ; preds = %bb25336
-  invoke void (...)* @printf(i32 undef, double undef)
+  invoke void (...) @printf(i32 undef, double undef)
           to label %bb25338 unwind label %bb25324
 
 bb25338:                                          ; preds = %bb25337
@@ -25517,11 +25517,11 @@ bb25341:                                          ; preds = %bb25340
   br label %bb25340
 
 bb25342:                                          ; preds = %bb25340
-  invoke void (...)* @printf()
+  invoke void (...) @printf()
           to label %bb25343 unwind label %bb25324
 
 bb25343:                                          ; preds = %bb25342
-  invoke void (...)* @printf(double undef, double undef)
+  invoke void (...) @printf(double undef, double undef)
           to label %bb25344 unwind label %bb25324
 
 bb25344:                                          ; preds = %bb25343
@@ -25547,15 +25547,15 @@ bb25350:                                          ; preds = %bb25349
   br label %bb25349
 
 bb25351:                                          ; preds = %bb25349
-  invoke void (...)* @printf()
+  invoke void (...) @printf()
           to label %bb25352 unwind label %bb25355
 
 bb25352:                                          ; preds = %bb25351
-  invoke void (...)* @printf(double undef)
+  invoke void (...) @printf(double undef)
           to label %bb25353 unwind label %bb25355
 
 bb25353:                                          ; preds = %bb25352
-  invoke void (...)* @printf()
+  invoke void (...) @printf()
           to label %bb25354 unwind label %bb25355
 
 bb25354:                                          ; preds = %bb25353
@@ -25567,7 +25567,7 @@ bb25355:                                          ; preds = %bb25353, %bb25352,
   br label %bb25359
 
 bb25357:                                          ; preds = %bb25332
-  invoke void (...)* @printf()
+  invoke void (...) @printf()
           to label %bb25358 unwind label %bb25324
 
 bb25358:                                          ; preds = %bb25357, %bb25354
diff --git a/test/CodeGen/X86/large-gep-scale.ll b/test/CodeGen/X86/large-gep-scale.ll
index 143294e8b07f..8e6e4d23a818 100644
--- a/test/CodeGen/X86/large-gep-scale.ll
+++ b/test/CodeGen/X86/large-gep-scale.ll
@@ -7,6 +7,6 @@
 ; CHECK: shll $2, %edx
 
 define fastcc i32* @_ada_smkr([2147483647 x i32]* %u, i32 %t) nounwind {
-  %x = getelementptr [2147483647 x i32]* %u, i32 %t, i32 0
+  %x = getelementptr [2147483647 x i32], [2147483647 x i32]* %u, i32 %t, i32 0
   ret i32* %x
 }
diff --git a/test/CodeGen/X86/ldzero.ll b/test/CodeGen/X86/ldzero.ll
index dab04bc353c6..3befa8a99b34 100644
--- a/test/CodeGen/X86/ldzero.ll
+++ b/test/CodeGen/X86/ldzero.ll
@@ -11,15 +11,15 @@ entry:
 	%d = alloca double, align 8		; <double*> [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store double 0.000000e+00, double* %d, align 8
-	%tmp1 = load double* %d, align 8		; <double> [#uses=1]
+	%tmp1 = load double, double* %d, align 8		; <double> [#uses=1]
 	%tmp12 = fpext double %tmp1 to x86_fp80		; <x86_fp80> [#uses=1]
 	store x86_fp80 %tmp12, x86_fp80* %tmp, align 16
-	%tmp3 = load x86_fp80* %tmp, align 16		; <x86_fp80> [#uses=1]
+	%tmp3 = load x86_fp80, x86_fp80* %tmp, align 16		; <x86_fp80> [#uses=1]
 	store x86_fp80 %tmp3, x86_fp80* %retval, align 16
 	br label %return
 
 return:		; preds = %entry
-	%retval4 = load x86_fp80* %retval		; <x86_fp80> [#uses=1]
+	%retval4 = load x86_fp80, x86_fp80* %retval		; <x86_fp80> [#uses=1]
 	ret x86_fp80 %retval4
 }
 
@@ -30,14 +30,14 @@ entry:
 	%ld = alloca x86_fp80, align 16		; <x86_fp80*> [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store x86_fp80 0xK00000000000000000000, x86_fp80* %ld, align 16
-	%tmp1 = load x86_fp80* %ld, align 16		; <x86_fp80> [#uses=1]
+	%tmp1 = load x86_fp80, x86_fp80* %ld, align 16		; <x86_fp80> [#uses=1]
 	%tmp12 = fptrunc x86_fp80 %tmp1 to double		; <double> [#uses=1]
 	store double %tmp12, double* %tmp, align 8
-	%tmp3 = load double* %tmp, align 8		; <double> [#uses=1]
+	%tmp3 = load double, double* %tmp, align 8		; <double> [#uses=1]
 	store double %tmp3, double* %retval, align 8
 	br label %return
 
 return:		; preds = %entry
-	%retval4 = load double* %retval		; <double> [#uses=1]
+	%retval4 = load double, double* %retval		; <double> [#uses=1]
 	ret double %retval4
 }
diff --git a/test/CodeGen/X86/lea-5.ll b/test/CodeGen/X86/lea-5.ll
index 50d3aaf4c594..b89c199e7197 100644
--- a/test/CodeGen/X86/lea-5.ll
+++ b/test/CodeGen/X86/lea-5.ll
@@ -14,11 +14,11 @@ entry:
 
 while.cond:                                       ; preds = %while.cond, %entry
   %d.addr.0 = phi i32 [ %d, %entry ], [ %inc, %while.cond ]
-  %arrayidx = getelementptr inbounds [8 x i32]* %a, i32 0, i32 %d.addr.0
+  %arrayidx = getelementptr inbounds [8 x i32], [8 x i32]* %a, i32 0, i32 %d.addr.0
 
 ; CHECK: leaq	-40(%rsp,%r{{[^,]*}},4), %rax
 ; X32:   leal	-40(%rsp,%r{{[^,]*}},4), %eax
-  %0 = load i32* %arrayidx, align 4
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp eq i32 %0, 0
   %inc = add nsw i32 %d.addr.0, 1
 
@@ -41,11 +41,11 @@ entry:
 
 while.cond:                                       ; preds = %while.cond, %entry
   %d.addr.0 = phi i32 [ %d, %entry ], [ %inc, %while.cond ]
-  %arrayidx = getelementptr inbounds [8 x i32]* %a, i32 0, i32 %d.addr.0
+  %arrayidx = getelementptr inbounds [8 x i32], [8 x i32]* %a, i32 0, i32 %d.addr.0
 
 ; CHECK: leaq	(%rsp,%r{{[^,]*}},4), %rax
 ; X32:   leal	(%rsp,%r{{[^,]*}},4), %eax
-  %0 = load i32* %arrayidx, align 4
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp eq i32 %0, 0
   %inc = add nsw i32 %d.addr.0, 1
 
diff --git a/test/CodeGen/X86/lea-recursion.ll b/test/CodeGen/X86/lea-recursion.ll
index 9480600312ce..55bcd7819c37 100644
--- a/test/CodeGen/X86/lea-recursion.ll
+++ b/test/CodeGen/X86/lea-recursion.ll
@@ -13,34 +13,34 @@
 
 define void @foo() {
 entry:
-	%tmp4 = load i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 0)		; <i32> [#uses=1]
-	%tmp8 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 0)		; <i32> [#uses=1]
+	%tmp4 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g0, i32 0, i32 0)		; <i32> [#uses=1]
+	%tmp8 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 0)		; <i32> [#uses=1]
 	%tmp9 = add i32 %tmp4, 1		; <i32> [#uses=1]
 	%tmp10 = add i32 %tmp9, %tmp8		; <i32> [#uses=2]
-	store i32 %tmp10, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 1)
-	%tmp8.1 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 1)		; <i32> [#uses=1]
+	store i32 %tmp10, i32* getelementptr ([1000 x i32], [1000 x i32]* @g0, i32 0, i32 1)
+	%tmp8.1 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 1)		; <i32> [#uses=1]
 	%tmp9.1 = add i32 %tmp10, 1		; <i32> [#uses=1]
 	%tmp10.1 = add i32 %tmp9.1, %tmp8.1		; <i32> [#uses=2]
-	store i32 %tmp10.1, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 2)
-	%tmp8.2 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 2)		; <i32> [#uses=1]
+	store i32 %tmp10.1, i32* getelementptr ([1000 x i32], [1000 x i32]* @g0, i32 0, i32 2)
+	%tmp8.2 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 2)		; <i32> [#uses=1]
 	%tmp9.2 = add i32 %tmp10.1, 1		; <i32> [#uses=1]
 	%tmp10.2 = add i32 %tmp9.2, %tmp8.2		; <i32> [#uses=2]
-	store i32 %tmp10.2, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 3)
-	%tmp8.3 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 3)		; <i32> [#uses=1]
+	store i32 %tmp10.2, i32* getelementptr ([1000 x i32], [1000 x i32]* @g0, i32 0, i32 3)
+	%tmp8.3 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 3)		; <i32> [#uses=1]
 	%tmp9.3 = add i32 %tmp10.2, 1		; <i32> [#uses=1]
 	%tmp10.3 = add i32 %tmp9.3, %tmp8.3		; <i32> [#uses=2]
-	store i32 %tmp10.3, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 4)
-	%tmp8.4 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 4)		; <i32> [#uses=1]
+	store i32 %tmp10.3, i32* getelementptr ([1000 x i32], [1000 x i32]* @g0, i32 0, i32 4)
+	%tmp8.4 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 4)		; <i32> [#uses=1]
 	%tmp9.4 = add i32 %tmp10.3, 1		; <i32> [#uses=1]
 	%tmp10.4 = add i32 %tmp9.4, %tmp8.4		; <i32> [#uses=2]
-	store i32 %tmp10.4, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 5)
-	%tmp8.5 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 5)		; <i32> [#uses=1]
+	store i32 %tmp10.4, i32* getelementptr ([1000 x i32], [1000 x i32]* @g0, i32 0, i32 5)
+	%tmp8.5 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 5)		; <i32> [#uses=1]
 	%tmp9.5 = add i32 %tmp10.4, 1		; <i32> [#uses=1]
 	%tmp10.5 = add i32 %tmp9.5, %tmp8.5		; <i32> [#uses=2]
-	store i32 %tmp10.5, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 6)
-	%tmp8.6 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 6)		; <i32> [#uses=1]
+	store i32 %tmp10.5, i32* getelementptr ([1000 x i32], [1000 x i32]* @g0, i32 0, i32 6)
+	%tmp8.6 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 6)		; <i32> [#uses=1]
 	%tmp9.6 = add i32 %tmp10.5, 1		; <i32> [#uses=1]
 	%tmp10.6 = add i32 %tmp9.6, %tmp8.6		; <i32> [#uses=1]
-	store i32 %tmp10.6, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 7)
+	store i32 %tmp10.6, i32* getelementptr ([1000 x i32], [1000 x i32]* @g0, i32 0, i32 7)
 	ret void
 }
diff --git a/test/CodeGen/X86/leaf-fp-elim.ll b/test/CodeGen/X86/leaf-fp-elim.ll
index 1bb3c7519146..dfbfbf7d11cb 100644
--- a/test/CodeGen/X86/leaf-fp-elim.ll
+++ b/test/CodeGen/X86/leaf-fp-elim.ll
@@ -19,7 +19,7 @@ entry:
   br i1 %0, label %return, label %bb
 
 bb:                                               ; preds = %entry
-  tail call void asm "mov $1, $0", "=*m,{cx},~{dirflag},~{fpsr},~{flags}"(i8** @msg, i8* getelementptr inbounds ([2 x i8]* @.str, i64 0, i64 0)) nounwind
+  tail call void asm "mov $1, $0", "=*m,{cx},~{dirflag},~{fpsr},~{flags}"(i8** @msg, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i64 0, i64 0)) nounwind
   tail call void @llvm.trap()
   unreachable
 
diff --git a/test/CodeGen/X86/legalize-shift-64.ll b/test/CodeGen/X86/legalize-shift-64.ll
index 64460bb91186..fb8f7b6a6027 100644
--- a/test/CodeGen/X86/legalize-shift-64.ll
+++ b/test/CodeGen/X86/legalize-shift-64.ll
@@ -71,7 +71,7 @@ define i32 @test6() {
   %t = alloca i64, align 8
   store i32 1, i32* %x, align 4
   store i64 1, i64* %t, align 8  ;; DEAD
-  %load = load i32* %x, align 4
+  %load = load i32, i32* %x, align 4
   %shl = shl i32 %load, 8
   %add = add i32 %shl, -224
   %sh_prom = zext i32 %add to i64
diff --git a/test/CodeGen/X86/legalize-sub-zero-2.ll b/test/CodeGen/X86/legalize-sub-zero-2.ll
index f02ca715aeeb..78d0e731fcfd 100644
--- a/test/CodeGen/X86/legalize-sub-zero-2.ll
+++ b/test/CodeGen/X86/legalize-sub-zero-2.ll
@@ -33,7 +33,7 @@ bb80:                                             ; preds = %bb71
   unreachable
 
 bb92:                                             ; preds = %bb71
-  %1 = getelementptr inbounds i8* undef, i32 %.sum745
+  %1 = getelementptr inbounds i8, i8* undef, i32 %.sum745
   unreachable
 
 bb348:                                            ; preds = %bb27
diff --git a/test/CodeGen/X86/licm-nested.ll b/test/CodeGen/X86/licm-nested.ll
index 083ae0875e39..42e6d12ec1e0 100644
--- a/test/CodeGen/X86/licm-nested.ll
+++ b/test/CodeGen/X86/licm-nested.ll
@@ -13,8 +13,8 @@ entry:
   br i1 %cmp, label %while.cond.preheader, label %bb.nph53
 
 while.cond.preheader:                             ; preds = %entry
-  %arrayidx = getelementptr inbounds i8** %argv, i64 1 ; <i8**> [#uses=1]
-  %tmp2 = load i8** %arrayidx                     ; <i8*> [#uses=1]
+  %arrayidx = getelementptr inbounds i8*, i8** %argv, i64 1 ; <i8**> [#uses=1]
+  %tmp2 = load i8*, i8** %arrayidx                     ; <i8*> [#uses=1]
   %call = tail call i32 @atoi(i8* %tmp2) nounwind ; <i32> [#uses=2]
   %tobool51 = icmp eq i32 %call, 0                ; <i1> [#uses=1]
   br i1 %tobool51, label %while.end, label %bb.nph53
@@ -35,7 +35,7 @@ bb.nph:                                           ; preds = %while.cond.loopexit
 for.body:                                         ; preds = %for.body, %bb.nph
   %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %for.body ] ; <i64> [#uses=2]
   %tmp = add i64 %indvar, 2                       ; <i64> [#uses=1]
-  %arrayidx10 = getelementptr [8193 x i8]* @main.flags, i64 0, i64 %tmp ; <i8*> [#uses=1]
+  %arrayidx10 = getelementptr [8193 x i8], [8193 x i8]* @main.flags, i64 0, i64 %tmp ; <i8*> [#uses=1]
   store i8 1, i8* %arrayidx10
   %indvar.next = add i64 %indvar, 1               ; <i64> [#uses=2]
   %exitcond = icmp eq i64 %indvar.next, 8191      ; <i1> [#uses=1]
@@ -49,8 +49,8 @@ for.body15:                                       ; preds = %for.body, %for.inc3
   %tmp71 = add i64 %tmp70, 6                      ; <i64> [#uses=1]
   %tmp73 = shl i64 %indvar57, 1                   ; <i64> [#uses=1]
   %add = add i64 %tmp73, 4                        ; <i64> [#uses=2]
-  %arrayidx17 = getelementptr [8193 x i8]* @main.flags, i64 0, i64 %tmp68 ; <i8*> [#uses=1]
-  %tmp18 = load i8* %arrayidx17                   ; <i8> [#uses=1]
+  %arrayidx17 = getelementptr [8193 x i8], [8193 x i8]* @main.flags, i64 0, i64 %tmp68 ; <i8*> [#uses=1]
+  %tmp18 = load i8, i8* %arrayidx17                   ; <i8> [#uses=1]
   %tobool19 = icmp eq i8 %tmp18, 0                ; <i1> [#uses=1]
   br i1 %tobool19, label %for.inc35, label %if.then
 
@@ -62,7 +62,7 @@ for.body25:                                       ; preds = %if.then, %for.body2
   %indvar55 = phi i64 [ %indvar.next56, %for.body25 ], [ 0, %if.then ] ; <i64> [#uses=2]
   %tmp60 = mul i64 %tmp68, %indvar55              ; <i64> [#uses=2]
   %tmp75 = add i64 %add, %tmp60                   ; <i64> [#uses=1]
-  %arrayidx27 = getelementptr [8193 x i8]* @main.flags, i64 0, i64 %tmp75 ; <i8*> [#uses=1]
+  %arrayidx27 = getelementptr [8193 x i8], [8193 x i8]* @main.flags, i64 0, i64 %tmp75 ; <i8*> [#uses=1]
   store i8 0, i8* %arrayidx27
   %add31 = add i64 %tmp71, %tmp60                 ; <i64> [#uses=1]
   %cmp24 = icmp slt i64 %add31, 8193              ; <i1> [#uses=1]
@@ -81,7 +81,7 @@ for.inc35:                                        ; preds = %for.body15, %for.en
 
 while.end:                                        ; preds = %while.cond.loopexit, %while.cond.preheader
   %count.0.lcssa = phi i32 [ 0, %while.cond.preheader ], [ %count.1, %while.cond.loopexit ] ; <i32> [#uses=1]
-  %call40 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i64 0, i64 0), i32 %count.0.lcssa) nounwind ; <i32> [#uses=0]
+  %call40 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i64 0, i64 0), i32 %count.0.lcssa) nounwind ; <i32> [#uses=0]
   ret i32 0
 }
 
diff --git a/test/CodeGen/X86/licm-regpressure.ll b/test/CodeGen/X86/licm-regpressure.ll
new file mode 100644
index 000000000000..0ab655419c88
--- /dev/null
+++ b/test/CodeGen/X86/licm-regpressure.ll
@@ -0,0 +1,39 @@
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
+; This tests currently fails as MachineLICM does not compute register pressure
+; correctly. More details: llvm.org/PR23143
+; XFAIL: *
+
+; MachineLICM should take register pressure into account.
+; CHECK-NOT: Spill
+
+%struct.A = type { i32, i32, i32, i32, i32, i32, i32 }
+
+define void @test(i1 %b, %struct.A* %a) nounwind {
+entry:
+  br label %loop-header
+
+loop-header:
+  br label %loop-body
+
+loop-body:
+  %0 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 0
+  %1 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 1
+  %2 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 2
+  %3 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 3
+  %4 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 4
+  %5 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 5
+  %6 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 6
+  call void @assign(i32* %0)
+  call void @assign(i32* %1)
+  call void @assign(i32* %2)
+  call void @assign(i32* %3)
+  call void @assign(i32* %4)
+  call void @assign(i32* %5)
+  call void @assign(i32* %6)
+  br i1 %b, label %loop-body, label %loop-exit
+
+loop-exit:
+  ret void
+}
+
+declare void @assign(i32*)
diff --git a/test/CodeGen/X86/licm-symbol.ll b/test/CodeGen/X86/licm-symbol.ll
index c3d1938e9dbd..0f115ddbb6c2 100644
--- a/test/CodeGen/X86/licm-symbol.ll
+++ b/test/CodeGen/X86/licm-symbol.ll
@@ -29,11 +29,11 @@ bb151:                                            ; preds = %bb59, %bb56, %bb14
   br i1 undef, label %bb56, label %bb59
 
 bb56:                                             ; preds = %bb151
-  %t0 = call i32 (%struct.FILE*)* @fprintf(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE]* @__sF, i32 0, i32 2)) nounwind
+  %t0 = call i32 (%struct.FILE*) @fprintf(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE], [0 x %struct.FILE]* @__sF, i32 0, i32 2)) nounwind
   br label %bb151
 
 bb59:                                             ; preds = %bb151
-  %t1 = call i32 (%struct.FILE*)* @fprintf(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE]* @__sF, i32 0, i32 2)) nounwind
+  %t1 = call i32 (%struct.FILE*) @fprintf(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE], [0 x %struct.FILE]* @__sF, i32 0, i32 2)) nounwind
   br label %bb151
 }
 
diff --git a/test/CodeGen/X86/liveness-local-regalloc.ll b/test/CodeGen/X86/liveness-local-regalloc.ll
index 721f545985d7..0954f9d5dd47 100644
--- a/test/CodeGen/X86/liveness-local-regalloc.ll
+++ b/test/CodeGen/X86/liveness-local-regalloc.ll
@@ -49,7 +49,7 @@ bb6:                                              ; preds = %.loopexit
 
 bb8:                                              ; preds = %.loopexit
   %tmp9 = sext i32 %.04 to i64                    ; <i64> [#uses=1]
-  %tmp10 = getelementptr inbounds %0* %arg, i64 0, i32 11, i64 %tmp9 ; <i8*> [#uses=1]
+  %tmp10 = getelementptr inbounds %0, %0* %arg, i64 0, i32 11, i64 %tmp9 ; <i8*> [#uses=1]
   store i8 0, i8* %tmp10, align 1
   ret void
 
@@ -71,7 +71,7 @@ BB:
   %A2 = alloca <2 x i8>
   %A1 = alloca i1
   %A = alloca i32
-  %L = load i8* %0
+  %L = load i8, i8* %0
   store i8 -37, i8* %0
   %E = extractelement <4 x i64> zeroinitializer, i32 2
   %Shuff = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 5, i32 7, i32 1, i32 3>
diff --git a/test/CodeGen/X86/llc-override-mcpu-mattr.ll b/test/CodeGen/X86/llc-override-mcpu-mattr.ll
new file mode 100644
index 000000000000..19a5ed591867
--- /dev/null
+++ b/test/CodeGen/X86/llc-override-mcpu-mattr.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march x86-64 -mcpu=broadwell | FileCheck %s
+; RUN: llc < %s -march x86-64 -mattr=+avx2 | FileCheck %s
+
+; Check that llc can overide function attributes target-cpu and target-features
+; using command line options -mcpu and -mattr.
+
+; CHECK: vpsadbw (%r{{si|dx}}), %ymm{{[0-9]+}}, %ymm{{[0-9]+}}
+
+define <4 x i64> @foo1(<4 x i64>* %s1, <4 x i64>* %s2) #0 {
+entry:
+  %ps1 = load <4 x i64>, <4 x i64>* %s1
+  %ps2 = load <4 x i64>, <4 x i64>* %s2
+  %0 = bitcast <4 x i64> %ps1 to <32 x i8>
+  %1 = bitcast <4 x i64> %ps2 to <32 x i8>
+  %2 = tail call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> %0, <32 x i8> %1)
+  ret <4 x i64> %2
+}
+
+declare <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8>, <32 x i8>)
+
+attributes #0 = { "target-cpu"="core2" "target-features"="+ssse3,+cx16,+sse4.2,+sse4.1,+sse,+sse2,+sse3,+avx,+popcnt" }
diff --git a/test/CodeGen/X86/load-slice.ll b/test/CodeGen/X86/load-slice.ll
index 49eb13160bbc..2f90f819d47e 100644
--- a/test/CodeGen/X86/load-slice.ll
+++ b/test/CodeGen/X86/load-slice.ll
@@ -28,7 +28,7 @@
 ; Swap Imm and Real.
 ; STRESS-NEXT: vinsertps $16, [[RES_Imm]], [[RES_Real]], [[RES_Vec:%xmm[0-9]+]]
 ; Put the results back into out[out_start].
-; STRESS-NEXT: vmovq [[RES_Vec]], ([[BASE]])
+; STRESS-NEXT: vmovlps [[RES_Vec]], ([[BASE]])
 ;
 ; Same for REGULAR, we eliminate register bank copy with each slices.
 ; REGULAR-LABEL: t1:
@@ -43,25 +43,25 @@
 ; Swap Imm and Real.
 ; REGULAR-NEXT: vinsertps $16, [[RES_Imm]], [[RES_Real]], [[RES_Vec:%xmm[0-9]+]]
 ; Put the results back into out[out_start].
-; REGULAR-NEXT: vmovq [[RES_Vec]], ([[BASE]])
+; REGULAR-NEXT: vmovlps [[RES_Vec]], ([[BASE]])
 define void @t1(%class.Complex* nocapture %out, i64 %out_start) {
 entry:
-  %arrayidx = getelementptr inbounds %class.Complex* %out, i64 %out_start
+  %arrayidx = getelementptr inbounds %class.Complex, %class.Complex* %out, i64 %out_start
   %tmp = bitcast %class.Complex* %arrayidx to i64*
-  %tmp1 = load i64* %tmp, align 8
+  %tmp1 = load i64, i64* %tmp, align 8
   %t0.sroa.0.0.extract.trunc = trunc i64 %tmp1 to i32
   %tmp2 = bitcast i32 %t0.sroa.0.0.extract.trunc to float
   %t0.sroa.2.0.extract.shift = lshr i64 %tmp1, 32
   %t0.sroa.2.0.extract.trunc = trunc i64 %t0.sroa.2.0.extract.shift to i32
   %tmp3 = bitcast i32 %t0.sroa.2.0.extract.trunc to float
   %add = add i64 %out_start, 8
-  %arrayidx2 = getelementptr inbounds %class.Complex* %out, i64 %add
-  %i.i = getelementptr inbounds %class.Complex* %arrayidx2, i64 0, i32 0
-  %tmp4 = load float* %i.i, align 4
+  %arrayidx2 = getelementptr inbounds %class.Complex, %class.Complex* %out, i64 %add
+  %i.i = getelementptr inbounds %class.Complex, %class.Complex* %arrayidx2, i64 0, i32 0
+  %tmp4 = load float, float* %i.i, align 4
   %add.i = fadd float %tmp4, %tmp2
   %retval.sroa.0.0.vec.insert.i = insertelement <2 x float> undef, float %add.i, i32 0
-  %r.i = getelementptr inbounds %class.Complex* %arrayidx2, i64 0, i32 1
-  %tmp5 = load float* %r.i, align 4
+  %r.i = getelementptr inbounds %class.Complex, %class.Complex* %arrayidx2, i64 0, i32 1
+  %tmp5 = load float, float* %r.i, align 4
   %add5.i = fadd float %tmp5, %tmp3
   %retval.sroa.0.4.vec.insert.i = insertelement <2 x float> %retval.sroa.0.0.vec.insert.i, float %add5.i, i32 1
   %ref.tmp.sroa.0.0.cast = bitcast %class.Complex* %arrayidx to <2 x float>*
@@ -100,9 +100,9 @@ declare void @llvm.lifetime.end(i64, i8* nocapture)
 ; REGULAR-LABEL: t2:
 ; REGULAR: shrq $48
 define i32 @t2(%class.Complex* nocapture %out, i64 %out_start) {
-  %arrayidx = getelementptr inbounds %class.Complex* %out, i64 %out_start
+  %arrayidx = getelementptr inbounds %class.Complex, %class.Complex* %out, i64 %out_start
   %bitcast = bitcast %class.Complex* %arrayidx to i64*
-  %chunk64 = load i64* %bitcast, align 8
+  %chunk64 = load i64, i64* %bitcast, align 8
   %slice32_low = trunc i64 %chunk64 to i32
   %shift48 = lshr i64 %chunk64, 48
   %slice32_high = trunc i64 %shift48 to i32
@@ -125,9 +125,9 @@ define i32 @t2(%class.Complex* nocapture %out, i64 %out_start) {
 ; REGULAR: shrq $48
 ; REGULAR: shrq $32
 define i32 @t3(%class.Complex* nocapture %out, i64 %out_start) {
-  %arrayidx = getelementptr inbounds %class.Complex* %out, i64 %out_start
+  %arrayidx = getelementptr inbounds %class.Complex, %class.Complex* %out, i64 %out_start
   %bitcast = bitcast %class.Complex* %arrayidx to i64*
-  %chunk64 = load i64* %bitcast, align 8
+  %chunk64 = load i64, i64* %bitcast, align 8
   %slice32_low = trunc i64 %chunk64 to i32
   %shift48 = lshr i64 %chunk64, 48
   %slice32_high = trunc i64 %shift48 to i32
diff --git a/test/CodeGen/X86/logical-load-fold.ll b/test/CodeGen/X86/logical-load-fold.ll
new file mode 100644
index 000000000000..5aac2d7910cd
--- /dev/null
+++ b/test/CodeGen/X86/logical-load-fold.ll
@@ -0,0 +1,53 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2,sse-unaligned-mem | FileCheck %s --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx                    | FileCheck %s --check-prefix=AVX
+
+; Although we have the ability to fold an unaligned load with AVX 
+; and under special conditions with some SSE implementations, we
+; can not fold the load under any circumstances in these test
+; cases because they are not 16-byte loads. The load must be
+; executed as a scalar ('movs*') with a zero extension to
+; 128-bits and then used in the packed logical ('andp*') op. 
+; PR22371 - http://llvm.org/bugs/show_bug.cgi?id=22371
+
+define double @load_double_no_fold(double %x, double %y) {
+; SSE2-LABEL: load_double_no_fold:
+; SSE2:       BB#0:
+; SSE2-NEXT:    cmplesd %xmm0, %xmm1
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; SSE2-NEXT:    andpd %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: load_double_no_fold:
+; AVX:       BB#0:
+; AVX-NEXT:    vcmplesd %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
+; AVX-NEXT:    vandpd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+
+  %cmp = fcmp oge double %x, %y
+  %zext = zext i1 %cmp to i32
+  %conv = sitofp i32 %zext to double
+  ret double %conv
+}
+
+define float @load_float_no_fold(float %x, float %y) {
+; SSE2-LABEL: load_float_no_fold:
+; SSE2:       BB#0:
+; SSE2-NEXT:    cmpless %xmm0, %xmm1
+; SSE2-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT:    andps %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: load_float_no_fold:
+; AVX:       BB#0:
+; AVX-NEXT:    vcmpless %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX-NEXT:    vandps %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+
+  %cmp = fcmp oge float %x, %y
+  %zext = zext i1 %cmp to i32
+  %conv = sitofp i32 %zext to float
+  ret float %conv
+}
+
diff --git a/test/CodeGen/X86/longlong-deadload.ll b/test/CodeGen/X86/longlong-deadload.ll
index 73e10127c065..3adaf49e372b 100644
--- a/test/CodeGen/X86/longlong-deadload.ll
+++ b/test/CodeGen/X86/longlong-deadload.ll
@@ -6,7 +6,7 @@ define void @test(i64* %P) nounwind  {
 ; CHECK: movl 4(%esp), %[[REGISTER:.*]]
 ; CHECK-NOT: 4(%[[REGISTER]])
 ; CHECK: ret
-	%tmp1 = load i64* %P, align 8		; <i64> [#uses=1]
+	%tmp1 = load i64, i64* %P, align 8		; <i64> [#uses=1]
 	%tmp2 = xor i64 %tmp1, 1		; <i64> [#uses=1]
 	store i64 %tmp2, i64* %P, align 8
 	ret void
diff --git a/test/CodeGen/X86/loop-hoist.ll b/test/CodeGen/X86/loop-hoist.ll
index c103e29f3bf3..8de240c0a97f 100644
--- a/test/CodeGen/X86/loop-hoist.ll
+++ b/test/CodeGen/X86/loop-hoist.ll
@@ -16,7 +16,7 @@ entry:
 cond_true:		; preds = %cond_true, %entry
 	%indvar = phi i32 [ %x, %entry ], [ %indvar.next, %cond_true ]		; <i32> [#uses=2]
 	%i.0.0 = bitcast i32 %indvar to i32		; <i32> [#uses=2]
-	%tmp = getelementptr [0 x i32]* @Arr, i32 0, i32 %i.0.0		; <i32*> [#uses=1]
+	%tmp = getelementptr [0 x i32], [0 x i32]* @Arr, i32 0, i32 %i.0.0		; <i32*> [#uses=1]
 	store i32 %i.0.0, i32* %tmp
 	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=2]
 	%exitcond = icmp eq i32 %indvar.next, %N		; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/loop-strength-reduce-2.ll b/test/CodeGen/X86/loop-strength-reduce-2.ll
index b546462b684f..062819021415 100644
--- a/test/CodeGen/X86/loop-strength-reduce-2.ll
+++ b/test/CodeGen/X86/loop-strength-reduce-2.ll
@@ -31,10 +31,10 @@ cond_true:		; preds = %cond_true, %entry
 	%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %cond_true ]		; <i32> [#uses=2]
 	%i.0.0 = bitcast i32 %indvar to i32		; <i32> [#uses=2]
 	%tmp2 = add i32 %i.0.0, 1		; <i32> [#uses=1]
-	%tmp = getelementptr [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp2		; <i32*> [#uses=1]
+	%tmp = getelementptr [16 x [16 x i32]], [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp2		; <i32*> [#uses=1]
 	store i32 4, i32* %tmp
 	%tmp5.upgrd.1 = add i32 %i.0.0, 2		; <i32> [#uses=1]
-	%tmp7 = getelementptr [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp5.upgrd.1		; <i32*> [#uses=1]
+	%tmp7 = getelementptr [16 x [16 x i32]], [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp5.upgrd.1		; <i32*> [#uses=1]
 	store i32 5, i32* %tmp7
 	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=2]
 	%exitcond = icmp eq i32 %indvar.next, %N		; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/loop-strength-reduce-3.ll b/test/CodeGen/X86/loop-strength-reduce-3.ll
index b1c9fb9c0772..9340c5c26713 100644
--- a/test/CodeGen/X86/loop-strength-reduce-3.ll
+++ b/test/CodeGen/X86/loop-strength-reduce-3.ll
@@ -19,10 +19,10 @@ cond_true:		; preds = %cond_true, %entry
 	%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %cond_true ]		; <i32> [#uses=2]
 	%i.0.0 = bitcast i32 %indvar to i32		; <i32> [#uses=2]
 	%tmp2 = add i32 %i.0.0, 1		; <i32> [#uses=1]
-	%tmp = getelementptr [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp2		; <i32*> [#uses=1]
+	%tmp = getelementptr [16 x [16 x i32]], [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp2		; <i32*> [#uses=1]
 	store i32 4, i32* %tmp
 	%tmp5.upgrd.1 = add i32 %i.0.0, 2		; <i32> [#uses=1]
-	%tmp7 = getelementptr [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp5.upgrd.1		; <i32*> [#uses=1]
+	%tmp7 = getelementptr [16 x [16 x i32]], [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp5.upgrd.1		; <i32*> [#uses=1]
 	store i32 5, i32* %tmp7
 	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=2]
 	%exitcond = icmp eq i32 %indvar.next, %N		; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/loop-strength-reduce.ll b/test/CodeGen/X86/loop-strength-reduce.ll
index 42c6ac4983db..2f80e0bb78bd 100644
--- a/test/CodeGen/X86/loop-strength-reduce.ll
+++ b/test/CodeGen/X86/loop-strength-reduce.ll
@@ -19,10 +19,10 @@ cond_true:		; preds = %cond_true, %entry
 	%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %cond_true ]		; <i32> [#uses=2]
 	%i.0.0 = bitcast i32 %indvar to i32		; <i32> [#uses=2]
 	%tmp2 = add i32 %i.0.0, 1		; <i32> [#uses=1]
-	%tmp = getelementptr [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp2		; <i32*> [#uses=1]
+	%tmp = getelementptr [16 x [16 x i32]], [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp2		; <i32*> [#uses=1]
 	store i32 4, i32* %tmp
 	%tmp5.upgrd.1 = add i32 %i.0.0, 2		; <i32> [#uses=1]
-	%tmp7 = getelementptr [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp5.upgrd.1		; <i32*> [#uses=1]
+	%tmp7 = getelementptr [16 x [16 x i32]], [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp5.upgrd.1		; <i32*> [#uses=1]
 	store i32 5, i32* %tmp7
 	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=2]
 	%exitcond = icmp eq i32 %indvar.next, %N		; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/loop-strength-reduce2.ll b/test/CodeGen/X86/loop-strength-reduce2.ll
index 689ee1cf23f4..a83503c7fe7b 100644
--- a/test/CodeGen/X86/loop-strength-reduce2.ll
+++ b/test/CodeGen/X86/loop-strength-reduce2.ll
@@ -18,7 +18,7 @@ bb:		; preds = %bb, %entry
 	%tmp.16 = add i32 %tmp.15, %tmp.		; <i32> [#uses=2]
 	%k_addr.0.0 = bitcast i32 %tmp.16 to i32		; <i32> [#uses=1]
 	%gep.upgrd.1 = zext i32 %tmp.16 to i64		; <i64> [#uses=1]
-	%tmp = getelementptr [8193 x i8]* @flags2, i32 0, i64 %gep.upgrd.1		; <i8*> [#uses=1]
+	%tmp = getelementptr [8193 x i8], [8193 x i8]* @flags2, i32 0, i64 %gep.upgrd.1		; <i8*> [#uses=1]
 	store i8 0, i8* %tmp
 	%k_addr.0 = add i32 %k_addr.0.0, %i		; <i32> [#uses=1]
 	%tmp.upgrd.2 = icmp sgt i32 %k_addr.0, 8192		; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/loop-strength-reduce4.ll b/test/CodeGen/X86/loop-strength-reduce4.ll
index 32e78790abdb..786534b00d39 100644
--- a/test/CodeGen/X86/loop-strength-reduce4.ll
+++ b/test/CodeGen/X86/loop-strength-reduce4.ll
@@ -26,31 +26,31 @@ bb:		; preds = %bb, %entry
 	%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]		; <i32> [#uses=2]
 	%t.063.0 = phi i32 [ 0, %entry ], [ %tmp47, %bb ]		; <i32> [#uses=1]
 	%j.065.0 = shl i32 %indvar, 2		; <i32> [#uses=4]
-	%tmp3 = getelementptr [0 x i32]* @state, i32 0, i32 %j.065.0		; <i32*> [#uses=2]
-	%tmp4 = load i32* %tmp3, align 4		; <i32> [#uses=1]
-	%tmp6 = getelementptr [0 x i32]* @S, i32 0, i32 %t.063.0		; <i32*> [#uses=1]
-	%tmp7 = load i32* %tmp6, align 4		; <i32> [#uses=1]
+	%tmp3 = getelementptr [0 x i32], [0 x i32]* @state, i32 0, i32 %j.065.0		; <i32*> [#uses=2]
+	%tmp4 = load i32, i32* %tmp3, align 4		; <i32> [#uses=1]
+	%tmp6 = getelementptr [0 x i32], [0 x i32]* @S, i32 0, i32 %t.063.0		; <i32*> [#uses=1]
+	%tmp7 = load i32, i32* %tmp6, align 4		; <i32> [#uses=1]
 	%tmp8 = xor i32 %tmp7, %tmp4		; <i32> [#uses=2]
 	store i32 %tmp8, i32* %tmp3, align 4
 	%tmp1378 = or i32 %j.065.0, 1		; <i32> [#uses=1]
-	%tmp16 = getelementptr [0 x i32]* @state, i32 0, i32 %tmp1378		; <i32*> [#uses=2]
-	%tmp17 = load i32* %tmp16, align 4		; <i32> [#uses=1]
-	%tmp19 = getelementptr [0 x i32]* @S, i32 0, i32 %tmp8		; <i32*> [#uses=1]
-	%tmp20 = load i32* %tmp19, align 4		; <i32> [#uses=1]
+	%tmp16 = getelementptr [0 x i32], [0 x i32]* @state, i32 0, i32 %tmp1378		; <i32*> [#uses=2]
+	%tmp17 = load i32, i32* %tmp16, align 4		; <i32> [#uses=1]
+	%tmp19 = getelementptr [0 x i32], [0 x i32]* @S, i32 0, i32 %tmp8		; <i32*> [#uses=1]
+	%tmp20 = load i32, i32* %tmp19, align 4		; <i32> [#uses=1]
 	%tmp21 = xor i32 %tmp20, %tmp17		; <i32> [#uses=2]
 	store i32 %tmp21, i32* %tmp16, align 4
 	%tmp2680 = or i32 %j.065.0, 2		; <i32> [#uses=1]
-	%tmp29 = getelementptr [0 x i32]* @state, i32 0, i32 %tmp2680		; <i32*> [#uses=2]
-	%tmp30 = load i32* %tmp29, align 4		; <i32> [#uses=1]
-	%tmp32 = getelementptr [0 x i32]* @S, i32 0, i32 %tmp21		; <i32*> [#uses=1]
-	%tmp33 = load i32* %tmp32, align 4		; <i32> [#uses=1]
+	%tmp29 = getelementptr [0 x i32], [0 x i32]* @state, i32 0, i32 %tmp2680		; <i32*> [#uses=2]
+	%tmp30 = load i32, i32* %tmp29, align 4		; <i32> [#uses=1]
+	%tmp32 = getelementptr [0 x i32], [0 x i32]* @S, i32 0, i32 %tmp21		; <i32*> [#uses=1]
+	%tmp33 = load i32, i32* %tmp32, align 4		; <i32> [#uses=1]
 	%tmp34 = xor i32 %tmp33, %tmp30		; <i32> [#uses=2]
 	store i32 %tmp34, i32* %tmp29, align 4
 	%tmp3982 = or i32 %j.065.0, 3		; <i32> [#uses=1]
-	%tmp42 = getelementptr [0 x i32]* @state, i32 0, i32 %tmp3982		; <i32*> [#uses=2]
-	%tmp43 = load i32* %tmp42, align 4		; <i32> [#uses=1]
-	%tmp45 = getelementptr [0 x i32]* @S, i32 0, i32 %tmp34		; <i32*> [#uses=1]
-	%tmp46 = load i32* %tmp45, align 4		; <i32> [#uses=1]
+	%tmp42 = getelementptr [0 x i32], [0 x i32]* @state, i32 0, i32 %tmp3982		; <i32*> [#uses=2]
+	%tmp43 = load i32, i32* %tmp42, align 4		; <i32> [#uses=1]
+	%tmp45 = getelementptr [0 x i32], [0 x i32]* @S, i32 0, i32 %tmp34		; <i32*> [#uses=1]
+	%tmp46 = load i32, i32* %tmp45, align 4		; <i32> [#uses=1]
 	%tmp47 = xor i32 %tmp46, %tmp43		; <i32> [#uses=3]
 	store i32 %tmp47, i32* %tmp42, align 4
 	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=2]
diff --git a/test/CodeGen/X86/loop-strength-reduce7.ll b/test/CodeGen/X86/loop-strength-reduce7.ll
index 4b565a67fb2d..92ec485e7752 100644
--- a/test/CodeGen/X86/loop-strength-reduce7.ll
+++ b/test/CodeGen/X86/loop-strength-reduce7.ll
@@ -27,12 +27,12 @@ bb28.i37:		; preds = %bb33.i47, %bb5
 bb29.i38:		; preds = %bb33.i47, %bb28.i37
 	%indvar32.i = phi i32 [ %indvar.next33.i, %bb33.i47 ], [ 0, %bb28.i37 ]		; <i32> [#uses=2]
 	%sfb.314.i = add i32 %indvar32.i, 0		; <i32> [#uses=3]
-	%1 = getelementptr [4 x [21 x double]]* null, i32 0, i32 %0, i32 %sfb.314.i		; <double*> [#uses=1]
-	%2 = load double* %1, align 8		; <double> [#uses=0]
+	%1 = getelementptr [4 x [21 x double]], [4 x [21 x double]]* null, i32 0, i32 %0, i32 %sfb.314.i		; <double*> [#uses=1]
+	%2 = load double, double* %1, align 8		; <double> [#uses=0]
 	br i1 false, label %bb30.i41, label %bb33.i47
 
 bb30.i41:		; preds = %bb29.i38
-	%3 = getelementptr %struct.III_scalefac_t* null, i32 0, i32 1, i32 %sfb.314.i, i32 %i.1.reg2mem.0.i		; <i32*> [#uses=1]
+	%3 = getelementptr %struct.III_scalefac_t, %struct.III_scalefac_t* null, i32 0, i32 1, i32 %sfb.314.i, i32 %i.1.reg2mem.0.i		; <i32*> [#uses=1]
 	store i32 0, i32* %3, align 4
 	br label %bb33.i47
 
diff --git a/test/CodeGen/X86/loop-strength-reduce8.ll b/test/CodeGen/X86/loop-strength-reduce8.ll
index c36047c451ae..716e1478c9ab 100644
--- a/test/CodeGen/X86/loop-strength-reduce8.ll
+++ b/test/CodeGen/X86/loop-strength-reduce8.ll
@@ -53,23 +53,23 @@ entry:
 	%p1 = bitcast i8** %p to i8*		; <i8*> [#uses=2]
 	call void @llvm.va_start(i8* %p1)
 	%0 = call fastcc %struct.tree_node* @make_node(i32 %code) nounwind		; <%struct.tree_node*> [#uses=2]
-	%1 = getelementptr [256 x i32]* @tree_code_length, i32 0, i32 %code		; <i32*> [#uses=1]
-	%2 = load i32* %1, align 4		; <i32> [#uses=2]
-	%3 = load i32* @lineno, align 4		; <i32> [#uses=1]
+	%1 = getelementptr [256 x i32], [256 x i32]* @tree_code_length, i32 0, i32 %code		; <i32*> [#uses=1]
+	%2 = load i32, i32* %1, align 4		; <i32> [#uses=2]
+	%3 = load i32, i32* @lineno, align 4		; <i32> [#uses=1]
 	%4 = bitcast %struct.tree_node* %0 to %struct.tree_exp*		; <%struct.tree_exp*> [#uses=2]
-	%5 = getelementptr %struct.tree_exp* %4, i32 0, i32 1		; <i32*> [#uses=1]
+	%5 = getelementptr %struct.tree_exp, %struct.tree_exp* %4, i32 0, i32 1		; <i32*> [#uses=1]
 	store i32 %3, i32* %5, align 4
 	%6 = icmp sgt i32 %2, 0		; <i1> [#uses=1]
 	br i1 %6, label %bb, label %bb3
 
 bb:		; preds = %bb, %entry
 	%i.01 = phi i32 [ %indvar.next, %bb ], [ 0, %entry ]		; <i32> [#uses=2]
-	%7 = load i8** %p, align 4		; <i8*> [#uses=2]
-	%8 = getelementptr i8* %7, i32 4		; <i8*> [#uses=1]
+	%7 = load i8*, i8** %p, align 4		; <i8*> [#uses=2]
+	%8 = getelementptr i8, i8* %7, i32 4		; <i8*> [#uses=1]
 	store i8* %8, i8** %p, align 4
 	%9 = bitcast i8* %7 to %struct.tree_node**		; <%struct.tree_node**> [#uses=1]
-	%10 = load %struct.tree_node** %9, align 4		; <%struct.tree_node*> [#uses=1]
-	%11 = getelementptr %struct.tree_exp* %4, i32 0, i32 2, i32 %i.01		; <%struct.tree_node**> [#uses=1]
+	%10 = load %struct.tree_node*, %struct.tree_node** %9, align 4		; <%struct.tree_node*> [#uses=1]
+	%11 = getelementptr %struct.tree_exp, %struct.tree_exp* %4, i32 0, i32 2, i32 %i.01		; <%struct.tree_node**> [#uses=1]
 	store %struct.tree_node* %10, %struct.tree_node** %11, align 4
 	%indvar.next = add i32 %i.01, 1		; <i32> [#uses=2]
 	%exitcond = icmp eq i32 %indvar.next, %2		; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/lower-vec-shift-2.ll b/test/CodeGen/X86/lower-vec-shift-2.ll
index 770775d32427..fb8fbba71fca 100644
--- a/test/CodeGen/X86/lower-vec-shift-2.ll
+++ b/test/CodeGen/X86/lower-vec-shift-2.ll
@@ -1,19 +1,20 @@
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s -check-prefix=SSE2
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s -check-prefix=AVX
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE2
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX
 
 define <8 x i16> @test1(<8 x i16> %A, <8 x i16> %B) {
 ; SSE2-LABEL: test1:
-; SSE2:       # BB#0
-; SSE2-NEXT:    movd  %xmm1, %eax
-; SSE2-NEXT:    movzwl  %ax, %eax
-; SSE2-NEXT:    movd  %eax, %xmm1
-; SSE2-NEXT:    psllw  %xmm1, %xmm0
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    movd %xmm1, %eax
+; SSE2-NEXT:    movzwl %ax, %eax
+; SSE2-NEXT:    movd %eax, %xmm1
+; SSE2-NEXT:    psllw %xmm1, %xmm0
 ; SSE2-NEXT:    retq
+;
 ; AVX-LABEL: test1:
-; AVX:       # BB#0
-; AVX-NEXT:    vpxor  %xmm2, %xmm2, %xmm2
-; AVX-NEXT:    vpblendw  {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
-; AVX-NEXT:    vpsllw  %xmm1, %xmm0, %xmm0
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
+; AVX-NEXT:    vpsllw %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 entry:
   %vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
@@ -23,16 +24,17 @@ entry:
 
 define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
 ; SSE2-LABEL: test2:
-; SSE2:       # BB#0
-; SSE2-NEXT:    xorps  %xmm2, %xmm2
-; SSE2-NEXT:    movss  %xmm1, %xmm2
-; SSE2-NEXT:    pslld  %xmm2, %xmm0
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    xorps %xmm2, %xmm2
+; SSE2-NEXT:    movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
+; SSE2-NEXT:    pslld %xmm2, %xmm0
 ; SSE2-NEXT:    retq
+;
 ; AVX-LABEL: test2:
-; AVX:       # BB#0
-; AVX-NEXT:    vpxor  %xmm2, %xmm2
-; AVX-NEXT:    vpblendw  {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
-; AVX-NEXT:    vpslld  %xmm1, %xmm0, %xmm0
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
+; AVX-NEXT:    vpslld %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 entry:
   %vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
@@ -42,12 +44,13 @@ entry:
 
 define <2 x i64> @test3(<2 x i64> %A, <2 x i64> %B) {
 ; SSE2-LABEL: test3:
-; SSE2:       # BB#0
-; SSE2-NEXT:    psllq  %xmm1, %xmm0
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    psllq %xmm1, %xmm0
 ; SSE2-NEXT:    retq
+;
 ; AVX-LABEL: test3:
-; AVX:       # BB#0
-; AVX-NEXT:    vpsllq  %xmm1, %xmm0, %xmm0
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vpsllq %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 entry:
   %vecinit2 = shufflevector <2 x i64> %B, <2 x i64> undef, <2 x i32> zeroinitializer
@@ -57,17 +60,18 @@ entry:
 
 define <8 x i16> @test4(<8 x i16> %A, <8 x i16> %B) {
 ; SSE2-LABEL: test4:
-; SSE2:       # BB#0
-; SSE2-NEXT:    movd  %xmm1, %eax
-; SSE2-NEXT:    movzwl  %ax, %eax
-; SSE2-NEXT:    movd  %eax, %xmm1
-; SSE2-NEXT:    psrlw  %xmm1, %xmm0
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    movd %xmm1, %eax
+; SSE2-NEXT:    movzwl %ax, %eax
+; SSE2-NEXT:    movd %eax, %xmm1
+; SSE2-NEXT:    psrlw %xmm1, %xmm0
 ; SSE2-NEXT:    retq
+;
 ; AVX-LABEL: test4:
-; AVX:       # BB#0
-; AVX-NEXT:    vpxor  %xmm2, %xmm2, %xmm2
-; AVX-NEXT:    vpblendw  {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
-; AVX-NEXT:    vpsrlw  %xmm1, %xmm0, %xmm0
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
+; AVX-NEXT:    vpsrlw %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 entry:
   %vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
@@ -77,16 +81,17 @@ entry:
 
 define <4 x i32> @test5(<4 x i32> %A, <4 x i32> %B) {
 ; SSE2-LABEL: test5:
-; SSE2:       # BB#0
-; SSE2-NEXT:    xorps  %xmm2, %xmm2
-; SSE2-NEXT:    movss  %xmm1, %xmm2
-; SSE2-NEXT:    psrld  %xmm2, %xmm0
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    xorps %xmm2, %xmm2
+; SSE2-NEXT:    movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
+; SSE2-NEXT:    psrld %xmm2, %xmm0
 ; SSE2-NEXT:    retq
+;
 ; AVX-LABEL: test5:
-; AVX:       # BB#0
-; AVX-NEXT:    vpxor  %xmm2, %xmm2
-; AVX-NEXT:    vpblendw  {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
-; AVX-NEXT:    vpsrld  %xmm1, %xmm0, %xmm0
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
+; AVX-NEXT:    vpsrld %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 entry:
   %vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
@@ -96,12 +101,13 @@ entry:
 
 define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) {
 ; SSE2-LABEL: test6:
-; SSE2:       # BB#0
-; SSE2-NEXT:    psrlq  %xmm1, %xmm0
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    psrlq %xmm1, %xmm0
 ; SSE2-NEXT:    retq
+;
 ; AVX-LABEL: test6:
-; AVX:       # BB#0
-; AVX-NEXT:    vpsrlq  %xmm1, %xmm0, %xmm0
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vpsrlq %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 entry:
   %vecinit2 = shufflevector <2 x i64> %B, <2 x i64> undef, <2 x i32> zeroinitializer
@@ -111,17 +117,18 @@ entry:
 
 define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) {
 ; SSE2-LABEL: test7:
-; SSE2:       # BB#0
-; SSE2-NEXT:    movd  %xmm1, %eax
-; SSE2-NEXT:    movzwl  %ax, %eax
-; SSE2-NEXT:    movd  %eax, %xmm1
-; SSE2-NEXT:    psraw  %xmm1, %xmm0
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    movd %xmm1, %eax
+; SSE2-NEXT:    movzwl %ax, %eax
+; SSE2-NEXT:    movd %eax, %xmm1
+; SSE2-NEXT:    psraw %xmm1, %xmm0
 ; SSE2-NEXT:    retq
+;
 ; AVX-LABEL: test7:
-; AVX:       # BB#0
-; AVX-NEXT:    vpxor  %xmm2, %xmm2, %xmm2
-; AVX-NEXT:    vpblendw  {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
-; AVX-NEXT:    vpsraw  %xmm1, %xmm0, %xmm0
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
+; AVX-NEXT:    vpsraw %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 entry:
   %vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
@@ -131,16 +138,17 @@ entry:
 
 define <4 x i32> @test8(<4 x i32> %A, <4 x i32> %B) {
 ; SSE2-LABEL: test8:
-; SSE2:       # BB#0
-; SSE2-NEXT:    xorps  %xmm2, %xmm2
-; SSE2-NEXT:    movss  %xmm1, %xmm2
-; SSE2-NEXT:    psrad  %xmm2, %xmm0
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    xorps %xmm2, %xmm2
+; SSE2-NEXT:    movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
+; SSE2-NEXT:    psrad %xmm2, %xmm0
 ; SSE2-NEXT:    retq
+;
 ; AVX-LABEL: test8:
-; AVX:       # BB#0
-; AVX-NEXT:    vpxor  %xmm2, %xmm2
-; AVX-NEXT:    vpblendw  {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
-; AVX-NEXT:    vpsrad  %xmm1, %xmm0, %xmm0
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
+; AVX-NEXT:    vpsrad %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 entry:
   %vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
diff --git a/test/CodeGen/X86/lsr-delayed-fold.ll b/test/CodeGen/X86/lsr-delayed-fold.ll
index 8ed97e447fee..eaa52dec2835 100644
--- a/test/CodeGen/X86/lsr-delayed-fold.ll
+++ b/test/CodeGen/X86/lsr-delayed-fold.ll
@@ -42,7 +42,7 @@ for.cond:                                         ; preds = %lbl_264, %for.inc,
 
 lbl_264:                                          ; preds = %if.end, %lbl_264.preheader
   %g_263.tmp.0 = phi i8 [ %g_263.tmp.1, %for.cond ] ; <i8> [#uses=1]
-  %tmp7 = load i16* undef                         ; <i16> [#uses=1]
+  %tmp7 = load i16, i16* undef                         ; <i16> [#uses=1]
   %conv8 = trunc i16 %tmp7 to i8                  ; <i8> [#uses=1]
   %mul.i = mul i8 %p_95.addr.0, %p_95.addr.0      ; <i8> [#uses=1]
   %mul.i18 = mul i8 %mul.i, %conv8                ; <i8> [#uses=1]
@@ -98,8 +98,8 @@ lor.lhs.false:                                    ; preds = %for.body
   %add106 = trunc i64 %tmp43 to i32               ; <i32> [#uses=1]
   %add112 = trunc i64 %tmp45 to i32               ; <i32> [#uses=1]
   %add118 = trunc i64 %tmp47 to i32               ; <i32> [#uses=1]
-  %tmp10 = getelementptr %struct.Bu* %bu, i64 %indvar, i32 2 ; <i32*> [#uses=1]
-  %tmp11 = load i32* %tmp10                       ; <i32> [#uses=0]
+  %tmp10 = getelementptr %struct.Bu, %struct.Bu* %bu, i64 %indvar, i32 2 ; <i32*> [#uses=1]
+  %tmp11 = load i32, i32* %tmp10                       ; <i32> [#uses=0]
   tail call void undef(i32 %add22)
   tail call void undef(i32 %add28)
   tail call void undef(i32 %add34)
diff --git a/test/CodeGen/X86/lsr-i386.ll b/test/CodeGen/X86/lsr-i386.ll
index 02baf2072e3b..9338939fafd0 100644
--- a/test/CodeGen/X86/lsr-i386.ll
+++ b/test/CodeGen/X86/lsr-i386.ll
@@ -22,7 +22,7 @@ entry:
 bb1:                                              ; preds = %bb6, %bb
   %indvar11 = phi i32 [ %indvar.next12, %bb6 ], [ 0, %entry ] ; <i32> [#uses=2]
   %tmp21 = add i32 %indvar11, 1                   ; <i32> [#uses=1]
-  %t = load i32* getelementptr inbounds (%struct.anon* @mp2grad_, i32 0, i32 1)
+  %t = load i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @mp2grad_, i32 0, i32 1)
   %tmp15 = mul i32 %n, %t                      ; <i32> [#uses=1]
   %tmp16 = add i32 %tmp21, %tmp15                 ; <i32> [#uses=1]
   %tmp17 = shl i32 %tmp16, 3                      ; <i32> [#uses=1]
@@ -32,7 +32,7 @@ bb1:                                              ; preds = %bb6, %bb
 bb2:                                              ; preds = %bb2, %bb2.preheader
   %indvar = phi i32 [ 0, %bb1 ], [ %indvar.next, %bb2 ] ; <i32> [#uses=2]
   %tmp19 = add i32 %tmp18, %indvar                ; <i32> [#uses=1]
-  %scevgep = getelementptr %struct.anon* @mp2grad_, i32 0, i32 0, i32 %tmp19 ; <i32*> [#uses=1]
+  %scevgep = getelementptr %struct.anon, %struct.anon* @mp2grad_, i32 0, i32 0, i32 %tmp19 ; <i32*> [#uses=1]
   store i32 0, i32* %scevgep
   %indvar.next = add i32 %indvar, 1               ; <i32> [#uses=1]
   %c = icmp ne i32 %indvar.next, %m
diff --git a/test/CodeGen/X86/lsr-interesting-step.ll b/test/CodeGen/X86/lsr-interesting-step.ll
index 8ea3c53de41e..fe8337e2981a 100644
--- a/test/CodeGen/X86/lsr-interesting-step.ll
+++ b/test/CodeGen/X86/lsr-interesting-step.ll
@@ -27,7 +27,7 @@ bb10:                                             ; preds = %bb7
 
 bb11:                                             ; preds = %bb10, %bb11
   %tmp12 = phi i64 [ %tmp14, %bb11 ], [ 2, %bb10 ] ; <i64> [#uses=2]
-  %tmp13 = getelementptr inbounds [8192 x i8]* @flags, i64 0, i64 %tmp12 ; <i8*> [#uses=1]
+  %tmp13 = getelementptr inbounds [8192 x i8], [8192 x i8]* @flags, i64 0, i64 %tmp12 ; <i8*> [#uses=1]
   store i8 0, i8* %tmp13, align 1
   %tmp14 = add nsw i64 %tmp12, %tmp8              ; <i64> [#uses=2]
   %tmp15 = icmp slt i64 %tmp14, 8192              ; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/lsr-loop-exit-cond.ll b/test/CodeGen/X86/lsr-loop-exit-cond.ll
index e7d74a924075..2e3929be31c5 100644
--- a/test/CodeGen/X86/lsr-loop-exit-cond.ll
+++ b/test/CodeGen/X86/lsr-loop-exit-cond.ll
@@ -17,9 +17,9 @@
 
 define void @t(i8* nocapture %in, i8* nocapture %out, i32* nocapture %rk, i32 %r) nounwind {
 entry:
-	%0 = load i32* %rk, align 4		; <i32> [#uses=1]
-	%1 = getelementptr i32* %rk, i64 1		; <i32*> [#uses=1]
-	%2 = load i32* %1, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* %rk, align 4		; <i32> [#uses=1]
+	%1 = getelementptr i32, i32* %rk, i64 1		; <i32*> [#uses=1]
+	%2 = load i32, i32* %1, align 4		; <i32> [#uses=1]
 	%tmp15 = add i32 %r, -1		; <i32> [#uses=1]
 	%tmp.16 = zext i32 %tmp15 to i64		; <i64> [#uses=2]
 	br label %bb
@@ -32,64 +32,64 @@ bb:		; preds = %bb1, %entry
 	%rk26 = bitcast i32* %rk to i8*		; <i8*> [#uses=6]
 	%3 = lshr i32 %s0.0, 24		; <i32> [#uses=1]
 	%4 = zext i32 %3 to i64		; <i64> [#uses=1]
-	%5 = getelementptr [256 x i32]* @Te0, i64 0, i64 %4		; <i32*> [#uses=1]
-	%6 = load i32* %5, align 4		; <i32> [#uses=1]
+	%5 = getelementptr [256 x i32], [256 x i32]* @Te0, i64 0, i64 %4		; <i32*> [#uses=1]
+	%6 = load i32, i32* %5, align 4		; <i32> [#uses=1]
 	%7 = lshr i32 %s1.0, 16		; <i32> [#uses=1]
 	%8 = and i32 %7, 255		; <i32> [#uses=1]
 	%9 = zext i32 %8 to i64		; <i64> [#uses=1]
-	%10 = getelementptr [256 x i32]* @Te1, i64 0, i64 %9		; <i32*> [#uses=1]
-	%11 = load i32* %10, align 4		; <i32> [#uses=1]
+	%10 = getelementptr [256 x i32], [256 x i32]* @Te1, i64 0, i64 %9		; <i32*> [#uses=1]
+	%11 = load i32, i32* %10, align 4		; <i32> [#uses=1]
 	%ctg2.sum2728 = or i64 %tmp18, 8		; <i64> [#uses=1]
-	%12 = getelementptr i8* %rk26, i64 %ctg2.sum2728		; <i8*> [#uses=1]
+	%12 = getelementptr i8, i8* %rk26, i64 %ctg2.sum2728		; <i8*> [#uses=1]
 	%13 = bitcast i8* %12 to i32*		; <i32*> [#uses=1]
-	%14 = load i32* %13, align 4		; <i32> [#uses=1]
+	%14 = load i32, i32* %13, align 4		; <i32> [#uses=1]
 	%15 = xor i32 %11, %6		; <i32> [#uses=1]
 	%16 = xor i32 %15, %14		; <i32> [#uses=3]
 	%17 = lshr i32 %s1.0, 24		; <i32> [#uses=1]
 	%18 = zext i32 %17 to i64		; <i64> [#uses=1]
-	%19 = getelementptr [256 x i32]* @Te0, i64 0, i64 %18		; <i32*> [#uses=1]
-	%20 = load i32* %19, align 4		; <i32> [#uses=1]
+	%19 = getelementptr [256 x i32], [256 x i32]* @Te0, i64 0, i64 %18		; <i32*> [#uses=1]
+	%20 = load i32, i32* %19, align 4		; <i32> [#uses=1]
 	%21 = and i32 %s0.0, 255		; <i32> [#uses=1]
 	%22 = zext i32 %21 to i64		; <i64> [#uses=1]
-	%23 = getelementptr [256 x i32]* @Te3, i64 0, i64 %22		; <i32*> [#uses=1]
-	%24 = load i32* %23, align 4		; <i32> [#uses=1]
+	%23 = getelementptr [256 x i32], [256 x i32]* @Te3, i64 0, i64 %22		; <i32*> [#uses=1]
+	%24 = load i32, i32* %23, align 4		; <i32> [#uses=1]
 	%ctg2.sum2930 = or i64 %tmp18, 12		; <i64> [#uses=1]
-	%25 = getelementptr i8* %rk26, i64 %ctg2.sum2930		; <i8*> [#uses=1]
+	%25 = getelementptr i8, i8* %rk26, i64 %ctg2.sum2930		; <i8*> [#uses=1]
 	%26 = bitcast i8* %25 to i32*		; <i32*> [#uses=1]
-	%27 = load i32* %26, align 4		; <i32> [#uses=1]
+	%27 = load i32, i32* %26, align 4		; <i32> [#uses=1]
 	%28 = xor i32 %24, %20		; <i32> [#uses=1]
 	%29 = xor i32 %28, %27		; <i32> [#uses=4]
 	%30 = lshr i32 %16, 24		; <i32> [#uses=1]
 	%31 = zext i32 %30 to i64		; <i64> [#uses=1]
-	%32 = getelementptr [256 x i32]* @Te0, i64 0, i64 %31		; <i32*> [#uses=1]
-	%33 = load i32* %32, align 4		; <i32> [#uses=2]
+	%32 = getelementptr [256 x i32], [256 x i32]* @Te0, i64 0, i64 %31		; <i32*> [#uses=1]
+	%33 = load i32, i32* %32, align 4		; <i32> [#uses=2]
 	%exitcond = icmp eq i64 %indvar, %tmp.16		; <i1> [#uses=1]
 	br i1 %exitcond, label %bb2, label %bb1
 
 bb1:		; preds = %bb
 	%ctg2.sum31 = add i64 %tmp18, 16		; <i64> [#uses=1]
-	%34 = getelementptr i8* %rk26, i64 %ctg2.sum31		; <i8*> [#uses=1]
+	%34 = getelementptr i8, i8* %rk26, i64 %ctg2.sum31		; <i8*> [#uses=1]
 	%35 = bitcast i8* %34 to i32*		; <i32*> [#uses=1]
 	%36 = lshr i32 %29, 16		; <i32> [#uses=1]
 	%37 = and i32 %36, 255		; <i32> [#uses=1]
 	%38 = zext i32 %37 to i64		; <i64> [#uses=1]
-	%39 = getelementptr [256 x i32]* @Te1, i64 0, i64 %38		; <i32*> [#uses=1]
-	%40 = load i32* %39, align 4		; <i32> [#uses=1]
-	%41 = load i32* %35, align 4		; <i32> [#uses=1]
+	%39 = getelementptr [256 x i32], [256 x i32]* @Te1, i64 0, i64 %38		; <i32*> [#uses=1]
+	%40 = load i32, i32* %39, align 4		; <i32> [#uses=1]
+	%41 = load i32, i32* %35, align 4		; <i32> [#uses=1]
 	%42 = xor i32 %40, %33		; <i32> [#uses=1]
 	%43 = xor i32 %42, %41		; <i32> [#uses=1]
 	%44 = lshr i32 %29, 24		; <i32> [#uses=1]
 	%45 = zext i32 %44 to i64		; <i64> [#uses=1]
-	%46 = getelementptr [256 x i32]* @Te0, i64 0, i64 %45		; <i32*> [#uses=1]
-	%47 = load i32* %46, align 4		; <i32> [#uses=1]
+	%46 = getelementptr [256 x i32], [256 x i32]* @Te0, i64 0, i64 %45		; <i32*> [#uses=1]
+	%47 = load i32, i32* %46, align 4		; <i32> [#uses=1]
 	%48 = and i32 %16, 255		; <i32> [#uses=1]
 	%49 = zext i32 %48 to i64		; <i64> [#uses=1]
-	%50 = getelementptr [256 x i32]* @Te3, i64 0, i64 %49		; <i32*> [#uses=1]
-	%51 = load i32* %50, align 4		; <i32> [#uses=1]
+	%50 = getelementptr [256 x i32], [256 x i32]* @Te3, i64 0, i64 %49		; <i32*> [#uses=1]
+	%51 = load i32, i32* %50, align 4		; <i32> [#uses=1]
 	%ctg2.sum32 = add i64 %tmp18, 20		; <i64> [#uses=1]
-	%52 = getelementptr i8* %rk26, i64 %ctg2.sum32		; <i8*> [#uses=1]
+	%52 = getelementptr i8, i8* %rk26, i64 %ctg2.sum32		; <i8*> [#uses=1]
 	%53 = bitcast i8* %52 to i32*		; <i32*> [#uses=1]
-	%54 = load i32* %53, align 4		; <i32> [#uses=1]
+	%54 = load i32, i32* %53, align 4		; <i32> [#uses=1]
 	%55 = xor i32 %51, %47		; <i32> [#uses=1]
 	%56 = xor i32 %55, %54		; <i32> [#uses=1]
 	%indvar.next = add i64 %indvar, 1		; <i64> [#uses=1]
@@ -98,48 +98,48 @@ bb1:		; preds = %bb
 bb2:		; preds = %bb
 	%tmp10 = shl i64 %tmp.16, 4		; <i64> [#uses=2]
 	%ctg2.sum = add i64 %tmp10, 16		; <i64> [#uses=1]
-	%tmp1213 = getelementptr i8* %rk26, i64 %ctg2.sum		; <i8*> [#uses=1]
+	%tmp1213 = getelementptr i8, i8* %rk26, i64 %ctg2.sum		; <i8*> [#uses=1]
 	%57 = bitcast i8* %tmp1213 to i32*		; <i32*> [#uses=1]
 	%58 = and i32 %33, -16777216		; <i32> [#uses=1]
 	%59 = lshr i32 %29, 16		; <i32> [#uses=1]
 	%60 = and i32 %59, 255		; <i32> [#uses=1]
 	%61 = zext i32 %60 to i64		; <i64> [#uses=1]
-	%62 = getelementptr [256 x i32]* @Te1, i64 0, i64 %61		; <i32*> [#uses=1]
-	%63 = load i32* %62, align 4		; <i32> [#uses=1]
+	%62 = getelementptr [256 x i32], [256 x i32]* @Te1, i64 0, i64 %61		; <i32*> [#uses=1]
+	%63 = load i32, i32* %62, align 4		; <i32> [#uses=1]
 	%64 = and i32 %63, 16711680		; <i32> [#uses=1]
 	%65 = or i32 %64, %58		; <i32> [#uses=1]
-	%66 = load i32* %57, align 4		; <i32> [#uses=1]
+	%66 = load i32, i32* %57, align 4		; <i32> [#uses=1]
 	%67 = xor i32 %65, %66		; <i32> [#uses=2]
 	%68 = lshr i32 %29, 8		; <i32> [#uses=1]
 	%69 = zext i32 %68 to i64		; <i64> [#uses=1]
-	%70 = getelementptr [256 x i32]* @Te0, i64 0, i64 %69		; <i32*> [#uses=1]
-	%71 = load i32* %70, align 4		; <i32> [#uses=1]
+	%70 = getelementptr [256 x i32], [256 x i32]* @Te0, i64 0, i64 %69		; <i32*> [#uses=1]
+	%71 = load i32, i32* %70, align 4		; <i32> [#uses=1]
 	%72 = and i32 %71, -16777216		; <i32> [#uses=1]
 	%73 = and i32 %16, 255		; <i32> [#uses=1]
 	%74 = zext i32 %73 to i64		; <i64> [#uses=1]
-	%75 = getelementptr [256 x i32]* @Te1, i64 0, i64 %74		; <i32*> [#uses=1]
-	%76 = load i32* %75, align 4		; <i32> [#uses=1]
+	%75 = getelementptr [256 x i32], [256 x i32]* @Te1, i64 0, i64 %74		; <i32*> [#uses=1]
+	%76 = load i32, i32* %75, align 4		; <i32> [#uses=1]
 	%77 = and i32 %76, 16711680		; <i32> [#uses=1]
 	%78 = or i32 %77, %72		; <i32> [#uses=1]
 	%ctg2.sum25 = add i64 %tmp10, 20		; <i64> [#uses=1]
-	%79 = getelementptr i8* %rk26, i64 %ctg2.sum25		; <i8*> [#uses=1]
+	%79 = getelementptr i8, i8* %rk26, i64 %ctg2.sum25		; <i8*> [#uses=1]
 	%80 = bitcast i8* %79 to i32*		; <i32*> [#uses=1]
-	%81 = load i32* %80, align 4		; <i32> [#uses=1]
+	%81 = load i32, i32* %80, align 4		; <i32> [#uses=1]
 	%82 = xor i32 %78, %81		; <i32> [#uses=2]
 	%83 = lshr i32 %67, 24		; <i32> [#uses=1]
 	%84 = trunc i32 %83 to i8		; <i8> [#uses=1]
 	store i8 %84, i8* %out, align 1
 	%85 = lshr i32 %67, 16		; <i32> [#uses=1]
 	%86 = trunc i32 %85 to i8		; <i8> [#uses=1]
-	%87 = getelementptr i8* %out, i64 1		; <i8*> [#uses=1]
+	%87 = getelementptr i8, i8* %out, i64 1		; <i8*> [#uses=1]
 	store i8 %86, i8* %87, align 1
-	%88 = getelementptr i8* %out, i64 4		; <i8*> [#uses=1]
+	%88 = getelementptr i8, i8* %out, i64 4		; <i8*> [#uses=1]
 	%89 = lshr i32 %82, 24		; <i32> [#uses=1]
 	%90 = trunc i32 %89 to i8		; <i8> [#uses=1]
 	store i8 %90, i8* %88, align 1
 	%91 = lshr i32 %82, 16		; <i32> [#uses=1]
 	%92 = trunc i32 %91 to i8		; <i8> [#uses=1]
-	%93 = getelementptr i8* %out, i64 5		; <i8*> [#uses=1]
+	%93 = getelementptr i8, i8* %out, i64 5		; <i8*> [#uses=1]
 	store i8 %92, i8* %93, align 1
 	ret void
 }
@@ -175,8 +175,8 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %indvars.iv = phi i64 [ %0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]
   %bi.06 = phi i32 [ 0, %for.body.lr.ph ], [ %i.addr.0.bi.0, %for.body ]
   %b.05 = phi i32 [ 0, %for.body.lr.ph ], [ %.b.0, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %1 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp ugt i32 %1, %b.05
   %.b.0 = select i1 %cmp1, i32 %1, i32 %b.05
   %2 = trunc i64 %indvars.iv to i32
diff --git a/test/CodeGen/X86/lsr-normalization.ll b/test/CodeGen/X86/lsr-normalization.ll
index 2775558b0cfd..09c892c9fc88 100644
--- a/test/CodeGen/X86/lsr-normalization.ll
+++ b/test/CodeGen/X86/lsr-normalization.ll
@@ -22,12 +22,12 @@ bb:
   %tmp = alloca %0, align 8                       ; <%0*> [#uses=11]
   %tmp2 = bitcast %0* %tmp to i8*                 ; <i8*> [#uses=1]
   call void @llvm.memset.p0i8.i64(i8* %tmp2, i8 0, i64 16, i32 8, i1 false) nounwind
-  %tmp3 = getelementptr inbounds %0* %tmp, i64 0, i32 0 ; <%0**> [#uses=3]
+  %tmp3 = getelementptr inbounds %0, %0* %tmp, i64 0, i32 0 ; <%0**> [#uses=3]
   store %0* %tmp, %0** %tmp3
-  %tmp4 = getelementptr inbounds %0* %tmp, i64 0, i32 1 ; <%0**> [#uses=1]
+  %tmp4 = getelementptr inbounds %0, %0* %tmp, i64 0, i32 1 ; <%0**> [#uses=1]
   store %0* %tmp, %0** %tmp4
   %tmp5 = call noalias i8* @_Znwm(i64 24) nounwind ; <i8*> [#uses=2]
-  %tmp6 = getelementptr inbounds i8* %tmp5, i64 16 ; <i8*> [#uses=2]
+  %tmp6 = getelementptr inbounds i8, i8* %tmp5, i64 16 ; <i8*> [#uses=2]
   %tmp7 = icmp eq i8* %tmp6, null                 ; <i1> [#uses=1]
   br i1 %tmp7, label %bb10, label %bb8
 
@@ -39,19 +39,19 @@ bb8:                                              ; preds = %bb
 bb10:                                             ; preds = %bb8, %bb
   %tmp11 = bitcast i8* %tmp5 to %0*               ; <%0*> [#uses=1]
   call void @_ZNSt15_List_node_base4hookEPS_(%0* %tmp11, %0* %tmp) nounwind
-  %tmp12 = load %0** %tmp3                        ; <%0*> [#uses=3]
+  %tmp12 = load %0*, %0** %tmp3                        ; <%0*> [#uses=3]
   %tmp13 = icmp eq %0* %tmp12, %tmp               ; <i1> [#uses=1]
   br i1 %tmp13, label %bb14, label %bb16
 
 bb14:                                             ; preds = %bb10
-  %tmp15 = call i32 @puts(i8* getelementptr inbounds ([5 x i8]* @1, i64 0, i64 0))
+  %tmp15 = call i32 @puts(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @1, i64 0, i64 0))
   br label %bb35
 
 bb16:                                             ; preds = %bb16, %bb10
   %tmp17 = phi i64 [ %tmp22, %bb16 ], [ 0, %bb10 ] ; <i64> [#uses=1]
   %tmp18 = phi %0* [ %tmp20, %bb16 ], [ %tmp12, %bb10 ] ; <%0*> [#uses=1]
-  %tmp19 = getelementptr inbounds %0* %tmp18, i64 0, i32 0 ; <%0**> [#uses=1]
-  %tmp20 = load %0** %tmp19                       ; <%0*> [#uses=2]
+  %tmp19 = getelementptr inbounds %0, %0* %tmp18, i64 0, i32 0 ; <%0**> [#uses=1]
+  %tmp20 = load %0*, %0** %tmp19                       ; <%0*> [#uses=2]
   %tmp21 = icmp eq %0* %tmp20, %tmp               ; <i1> [#uses=1]
   %tmp22 = add i64 %tmp17, 1                      ; <i64> [#uses=2]
   br i1 %tmp21, label %bb23, label %bb16
@@ -63,26 +63,26 @@ bb23:                                             ; preds = %bb16
 bb25:                                             ; preds = %bb25, %bb23
   %tmp26 = phi i64 [ %tmp31, %bb25 ], [ 0, %bb23 ] ; <i64> [#uses=1]
   %tmp27 = phi %0* [ %tmp29, %bb25 ], [ %tmp12, %bb23 ] ; <%0*> [#uses=1]
-  %tmp28 = getelementptr inbounds %0* %tmp27, i64 0, i32 0 ; <%0**> [#uses=1]
-  %tmp29 = load %0** %tmp28                       ; <%0*> [#uses=2]
+  %tmp28 = getelementptr inbounds %0, %0* %tmp27, i64 0, i32 0 ; <%0**> [#uses=1]
+  %tmp29 = load %0*, %0** %tmp28                       ; <%0*> [#uses=2]
   %tmp30 = icmp eq %0* %tmp29, %tmp               ; <i1> [#uses=1]
   %tmp31 = add i64 %tmp26, 1                      ; <i64> [#uses=2]
   br i1 %tmp30, label %bb32, label %bb25
 
 bb32:                                             ; preds = %bb25
   %tmp33 = mul i64 %tmp31, %tmp24                 ; <i64> [#uses=1]
-  %tmp34 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @0, i64 0, i64 0), i64 %tmp33) nounwind
+  %tmp34 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @0, i64 0, i64 0), i64 %tmp33) nounwind
   br label %bb35
 
 bb35:                                             ; preds = %bb32, %bb14
-  %tmp36 = load %0** %tmp3                        ; <%0*> [#uses=2]
+  %tmp36 = load %0*, %0** %tmp3                        ; <%0*> [#uses=2]
   %tmp37 = icmp eq %0* %tmp36, %tmp               ; <i1> [#uses=1]
   br i1 %tmp37, label %bb44, label %bb38
 
 bb38:                                             ; preds = %bb38, %bb35
   %tmp39 = phi %0* [ %tmp41, %bb38 ], [ %tmp36, %bb35 ] ; <%0*> [#uses=2]
-  %tmp40 = getelementptr inbounds %0* %tmp39, i64 0, i32 0 ; <%0**> [#uses=1]
-  %tmp41 = load %0** %tmp40                       ; <%0*> [#uses=2]
+  %tmp40 = getelementptr inbounds %0, %0* %tmp39, i64 0, i32 0 ; <%0**> [#uses=1]
+  %tmp41 = load %0*, %0** %tmp40                       ; <%0*> [#uses=2]
   %tmp42 = bitcast %0* %tmp39 to i8*              ; <i8*> [#uses=1]
   call void @_ZdlPv(i8* %tmp42) nounwind
   %tmp43 = icmp eq %0* %tmp41, %tmp               ; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/lsr-quadratic-expand.ll b/test/CodeGen/X86/lsr-quadratic-expand.ll
index 2bbb47092904..29a8da2ef3aa 100644
--- a/test/CodeGen/X86/lsr-quadratic-expand.ll
+++ b/test/CodeGen/X86/lsr-quadratic-expand.ll
@@ -13,7 +13,7 @@ bb:                                               ; preds = %bb, %entry
   %z5 = add nsw i32 %z4, %z2
   %z6 = trunc i32 %z5 to i16
   call fastcc void @dw210x_op_rw(i16 zeroext %z6)
-  %z7 = getelementptr i8* null, i64 %z
+  %z7 = getelementptr i8, i8* null, i64 %z
   store i8 undef, i8* %z7, align 1
   %z8 = add nsw i32 %z2, 1
   br label %bb
diff --git a/test/CodeGen/X86/lsr-redundant-addressing.ll b/test/CodeGen/X86/lsr-redundant-addressing.ll
index cb0ac8b67a7e..31a1859e3b27 100644
--- a/test/CodeGen/X86/lsr-redundant-addressing.ll
+++ b/test/CodeGen/X86/lsr-redundant-addressing.ll
@@ -22,8 +22,8 @@ bb:
 bb38:                                             ; preds = %bb200, %bb
   %tmp39 = phi i64 [ %tmp201, %bb200 ], [ 0, %bb ]
   %tmp40 = sub i64 0, %tmp39
-  %tmp47 = getelementptr [5 x %0]* @pgm, i64 0, i64 %tmp40, i32 0
-  %tmp34 = load i32* %tmp47, align 16
+  %tmp47 = getelementptr [5 x %0], [5 x %0]* @pgm, i64 0, i64 %tmp40, i32 0
+  %tmp34 = load i32, i32* %tmp47, align 16
   %tmp203 = icmp slt i32 %tmp34, 12
   br i1 %tmp203, label %bb215, label %bb200
 
@@ -32,20 +32,20 @@ bb200:                                            ; preds = %bb38
   br label %bb38
 
 bb215:                                            ; preds = %bb38
-  %tmp50 = getelementptr [5 x %0]* @pgm, i64 0, i64 %tmp40, i32 1, i64 2
-  %tmp49 = getelementptr [5 x %0]* @pgm, i64 0, i64 %tmp40, i32 1, i64 1
-  %tmp48 = getelementptr [5 x %0]* @pgm, i64 0, i64 %tmp40, i32 1, i64 0
+  %tmp50 = getelementptr [5 x %0], [5 x %0]* @pgm, i64 0, i64 %tmp40, i32 1, i64 2
+  %tmp49 = getelementptr [5 x %0], [5 x %0]* @pgm, i64 0, i64 %tmp40, i32 1, i64 1
+  %tmp48 = getelementptr [5 x %0], [5 x %0]* @pgm, i64 0, i64 %tmp40, i32 1, i64 0
   %tmp216 = add nsw i32 %tmp34, 1
   store i32 %tmp216, i32* %tmp47, align 16
   %tmp217 = sext i32 %tmp216 to i64
-  %tmp218 = getelementptr inbounds [13 x %1]* @isa, i64 0, i64 %tmp217, i32 3, i64 0
-  %tmp219 = load i32* %tmp218, align 8
+  %tmp218 = getelementptr inbounds [13 x %1], [13 x %1]* @isa, i64 0, i64 %tmp217, i32 3, i64 0
+  %tmp219 = load i32, i32* %tmp218, align 8
   store i32 %tmp219, i32* %tmp48, align 4
-  %tmp220 = getelementptr inbounds [13 x %1]* @isa, i64 0, i64 %tmp217, i32 3, i64 1
-  %tmp221 = load i32* %tmp220, align 4
+  %tmp220 = getelementptr inbounds [13 x %1], [13 x %1]* @isa, i64 0, i64 %tmp217, i32 3, i64 1
+  %tmp221 = load i32, i32* %tmp220, align 4
   store i32 %tmp221, i32* %tmp49, align 4
-  %tmp222 = getelementptr inbounds [13 x %1]* @isa, i64 0, i64 %tmp217, i32 3, i64 2
-  %tmp223 = load i32* %tmp222, align 8
+  %tmp222 = getelementptr inbounds [13 x %1], [13 x %1]* @isa, i64 0, i64 %tmp217, i32 3, i64 2
+  %tmp223 = load i32, i32* %tmp222, align 8
   store i32 %tmp223, i32* %tmp50, align 4
   ret void
 }
diff --git a/test/CodeGen/X86/lsr-reuse-trunc.ll b/test/CodeGen/X86/lsr-reuse-trunc.ll
index 276dab72f7cc..7f73b6b9d1ee 100644
--- a/test/CodeGen/X86/lsr-reuse-trunc.ll
+++ b/test/CodeGen/X86/lsr-reuse-trunc.ll
@@ -14,18 +14,18 @@
 
 define void @vvfloorf(float* nocapture %y, float* nocapture %x, i32* nocapture %n) nounwind {
 entry:
-  %0 = load i32* %n, align 4
+  %0 = load i32, i32* %n, align 4
   %1 = icmp sgt i32 %0, 0
   br i1 %1, label %bb, label %return
 
 bb:
   %indvar = phi i64 [ %indvar.next, %bb ], [ 0, %entry ]
   %tmp = shl i64 %indvar, 2
-  %scevgep = getelementptr float* %y, i64 %tmp
+  %scevgep = getelementptr float, float* %y, i64 %tmp
   %scevgep9 = bitcast float* %scevgep to <4 x float>*
-  %scevgep10 = getelementptr float* %x, i64 %tmp
+  %scevgep10 = getelementptr float, float* %x, i64 %tmp
   %scevgep1011 = bitcast float* %scevgep10 to <4 x float>*
-  %2 = load <4 x float>* %scevgep1011, align 16
+  %2 = load <4 x float>, <4 x float>* %scevgep1011, align 16
   %3 = bitcast <4 x float> %2 to <4 x i32>
   %4 = and <4 x i32> %3, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
   %5 = bitcast <4 x i32> %4 to <4 x float>
@@ -48,7 +48,7 @@ bb:
   store <4 x float> %19, <4 x float>* %scevgep9, align 16
   %tmp12 = add i64 %tmp, 4
   %tmp13 = trunc i64 %tmp12 to i32
-  %20 = load i32* %n, align 4
+  %20 = load i32, i32* %n, align 4
   %21 = icmp sgt i32 %20, %tmp13
   %indvar.next = add i64 %indvar, 1
   br i1 %21, label %bb, label %return
diff --git a/test/CodeGen/X86/lsr-reuse.ll b/test/CodeGen/X86/lsr-reuse.ll
index 40c041ab6b09..dd1e40f6a1ec 100644
--- a/test/CodeGen/X86/lsr-reuse.ll
+++ b/test/CodeGen/X86/lsr-reuse.ll
@@ -25,11 +25,11 @@ entry:
 
 loop:
   %i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
-  %Ai = getelementptr inbounds double* %A, i64 %i
-  %Bi = getelementptr inbounds double* %B, i64 %i
-  %Ci = getelementptr inbounds double* %C, i64 %i
-  %t1 = load double* %Bi
-  %t2 = load double* %Ci
+  %Ai = getelementptr inbounds double, double* %A, i64 %i
+  %Bi = getelementptr inbounds double, double* %B, i64 %i
+  %Ci = getelementptr inbounds double, double* %C, i64 %i
+  %t1 = load double, double* %Bi
+  %t2 = load double, double* %Ci
   %m = fmul double %t1, %t2
   store double %m, double* %Ai
   %i.next = add nsw i64 %i, 1
@@ -70,19 +70,19 @@ entry:
 
 loop:
   %i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
-  %Ai = getelementptr inbounds double* %A, i64 %i
-  %Bi = getelementptr inbounds double* %B, i64 %i
-  %Ci = getelementptr inbounds double* %C, i64 %i
-  %t1 = load double* %Bi
-  %t2 = load double* %Ci
+  %Ai = getelementptr inbounds double, double* %A, i64 %i
+  %Bi = getelementptr inbounds double, double* %B, i64 %i
+  %Ci = getelementptr inbounds double, double* %C, i64 %i
+  %t1 = load double, double* %Bi
+  %t2 = load double, double* %Ci
   %m = fmul double %t1, %t2
   store double %m, double* %Ai
   %j = add i64 %i, 256
-  %Aj = getelementptr inbounds double* %A, i64 %j
-  %Bj = getelementptr inbounds double* %B, i64 %j
-  %Cj = getelementptr inbounds double* %C, i64 %j
-  %t3 = load double* %Bj
-  %t4 = load double* %Cj
+  %Aj = getelementptr inbounds double, double* %A, i64 %j
+  %Bj = getelementptr inbounds double, double* %B, i64 %j
+  %Cj = getelementptr inbounds double, double* %C, i64 %j
+  %t3 = load double, double* %Bj
+  %t4 = load double, double* %Cj
   %o = fdiv double %t3, %t4
   store double %o, double* %Aj
   %i.next = add nsw i64 %i, 1
@@ -116,19 +116,19 @@ entry:
 
 loop:
   %i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
-  %Ai = getelementptr inbounds double* %A, i64 %i
-  %Bi = getelementptr inbounds double* %B, i64 %i
-  %Ci = getelementptr inbounds double* %C, i64 %i
-  %t1 = load double* %Bi
-  %t2 = load double* %Ci
+  %Ai = getelementptr inbounds double, double* %A, i64 %i
+  %Bi = getelementptr inbounds double, double* %B, i64 %i
+  %Ci = getelementptr inbounds double, double* %C, i64 %i
+  %t1 = load double, double* %Bi
+  %t2 = load double, double* %Ci
   %m = fmul double %t1, %t2
   store double %m, double* %Ai
   %j = sub i64 %i, 256
-  %Aj = getelementptr inbounds double* %A, i64 %j
-  %Bj = getelementptr inbounds double* %B, i64 %j
-  %Cj = getelementptr inbounds double* %C, i64 %j
-  %t3 = load double* %Bj
-  %t4 = load double* %Cj
+  %Aj = getelementptr inbounds double, double* %A, i64 %j
+  %Bj = getelementptr inbounds double, double* %B, i64 %j
+  %Cj = getelementptr inbounds double, double* %C, i64 %j
+  %t3 = load double, double* %Bj
+  %t4 = load double, double* %Cj
   %o = fdiv double %t3, %t4
   store double %o, double* %Aj
   %i.next = add nsw i64 %i, 1
@@ -162,19 +162,19 @@ entry:
 loop:
   %i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
   %k = add i64 %i, 256
-  %Ak = getelementptr inbounds double* %A, i64 %k
-  %Bk = getelementptr inbounds double* %B, i64 %k
-  %Ck = getelementptr inbounds double* %C, i64 %k
-  %t1 = load double* %Bk
-  %t2 = load double* %Ck
+  %Ak = getelementptr inbounds double, double* %A, i64 %k
+  %Bk = getelementptr inbounds double, double* %B, i64 %k
+  %Ck = getelementptr inbounds double, double* %C, i64 %k
+  %t1 = load double, double* %Bk
+  %t2 = load double, double* %Ck
   %m = fmul double %t1, %t2
   store double %m, double* %Ak
   %j = sub i64 %i, 256
-  %Aj = getelementptr inbounds double* %A, i64 %j
-  %Bj = getelementptr inbounds double* %B, i64 %j
-  %Cj = getelementptr inbounds double* %C, i64 %j
-  %t3 = load double* %Bj
-  %t4 = load double* %Cj
+  %Aj = getelementptr inbounds double, double* %A, i64 %j
+  %Bj = getelementptr inbounds double, double* %B, i64 %j
+  %Cj = getelementptr inbounds double, double* %C, i64 %j
+  %t3 = load double, double* %Bj
+  %t4 = load double, double* %Cj
   %o = fdiv double %t3, %t4
   store double %o, double* %Aj
   %i.next = add nsw i64 %i, 1
@@ -205,11 +205,11 @@ entry:
 
 loop:
   %i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
-  %Ai = getelementptr inbounds double* %A, i64 %i
-  %Bi = getelementptr inbounds double* %B, i64 %i
-  %Ci = getelementptr inbounds double* %C, i64 %i
-  %t1 = load double* %Bi
-  %t2 = load double* %Ci
+  %Ai = getelementptr inbounds double, double* %A, i64 %i
+  %Bi = getelementptr inbounds double, double* %B, i64 %i
+  %Ci = getelementptr inbounds double, double* %C, i64 %i
+  %t1 = load double, double* %Bi
+  %t2 = load double, double* %Ci
   %m = fmul double %t1, %t2
   store double %m, double* %Ai
   %i.next = add nsw i64 %i, 1
@@ -240,11 +240,11 @@ entry:
 
 loop:
   %i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
-  %Ai = getelementptr inbounds double* %A, i64 %i
-  %Bi = getelementptr inbounds double* %B, i64 %i
-  %Ci = getelementptr inbounds double* %C, i64 %i
-  %t1 = load double* %Bi
-  %t2 = load double* %Ci
+  %Ai = getelementptr inbounds double, double* %A, i64 %i
+  %Bi = getelementptr inbounds double, double* %B, i64 %i
+  %Ci = getelementptr inbounds double, double* %C, i64 %i
+  %t1 = load double, double* %Bi
+  %t2 = load double, double* %Ci
   %m = fmul double %t1, %t2
   store double %m, double* %Ai
   %i.next = add nsw i64 %i, 1
@@ -280,20 +280,20 @@ entry:
 loop:
   %i = phi i64 [ 0, %entry ], [ %i.next, %loop ]
   %i5 = add i64 %i, 5
-  %Ai = getelementptr double* %A, i64 %i5
-  %t2 = load double* %Ai
-  %Bi = getelementptr double* %B, i64 %i5
-  %t4 = load double* %Bi
+  %Ai = getelementptr double, double* %A, i64 %i5
+  %t2 = load double, double* %Ai
+  %Bi = getelementptr double, double* %B, i64 %i5
+  %t4 = load double, double* %Bi
   %t5 = fadd double %t2, %t4
-  %Ci = getelementptr double* %C, i64 %i5
+  %Ci = getelementptr double, double* %C, i64 %i5
   store double %t5, double* %Ci
   %i10 = add i64 %i, 10
-  %Ai10 = getelementptr double* %A, i64 %i10
-  %t9 = load double* %Ai10
-  %Bi10 = getelementptr double* %B, i64 %i10
-  %t11 = load double* %Bi10
+  %Ai10 = getelementptr double, double* %A, i64 %i10
+  %t9 = load double, double* %Ai10
+  %Bi10 = getelementptr double, double* %B, i64 %i10
+  %t11 = load double, double* %Bi10
   %t12 = fsub double %t9, %t11
-  %Ci10 = getelementptr double* %C, i64 %i10
+  %Ci10 = getelementptr double, double* %C, i64 %i10
   store double %t12, double* %Ci10
   %i.next = add i64 %i, 1
   %exitcond = icmp eq i64 %i.next, 5000
@@ -327,20 +327,20 @@ entry:
 loop:
   %i = phi i64 [ 0, %entry ], [ %i.next, %loop ]
   %i5 = add i64 %i, 5
-  %Ai = getelementptr double* %A, i64 %i5
-  %t2 = load double* %Ai
-  %Bi = getelementptr double* %B, i64 %i5
-  %t4 = load double* %Bi
+  %Ai = getelementptr double, double* %A, i64 %i5
+  %t2 = load double, double* %Ai
+  %Bi = getelementptr double, double* %B, i64 %i5
+  %t4 = load double, double* %Bi
   %t5 = fadd double %t2, %t4
-  %Ci = getelementptr double* %C, i64 %i5
+  %Ci = getelementptr double, double* %C, i64 %i5
   store double %t5, double* %Ci
   %i10 = add i64 %i, 10
-  %Ai10 = getelementptr double* %A, i64 %i10
-  %t9 = load double* %Ai10
-  %Bi10 = getelementptr double* %B, i64 %i10
-  %t11 = load double* %Bi10
+  %Ai10 = getelementptr double, double* %A, i64 %i10
+  %t9 = load double, double* %Ai10
+  %Bi10 = getelementptr double, double* %B, i64 %i10
+  %t11 = load double, double* %Bi10
   %t12 = fsub double %t9, %t11
-  %Ci10 = getelementptr double* %C, i64 %i10
+  %Ci10 = getelementptr double, double* %C, i64 %i10
   store double %t12, double* %Ci10
   %i.next = add i64 %i, 1
   %exitcond = icmp eq i64 %i.next, %n
@@ -372,11 +372,11 @@ entry:
 loop:
   %i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
   call void @use(i64 %i)
-  %Ai = getelementptr inbounds double* %A, i64 %i
-  %Bi = getelementptr inbounds double* %B, i64 %i
-  %Ci = getelementptr inbounds double* %C, i64 %i
-  %t1 = load double* %Bi
-  %t2 = load double* %Ci
+  %Ai = getelementptr inbounds double, double* %A, i64 %i
+  %Bi = getelementptr inbounds double, double* %B, i64 %i
+  %Ci = getelementptr inbounds double, double* %C, i64 %i
+  %t1 = load double, double* %Bi
+  %t2 = load double, double* %Ci
   %m = fmul double %t1, %t2
   store double %m, double* %Ai
   %i.next = add nsw i64 %i, 1
@@ -413,8 +413,8 @@ bb.nph14:                                         ; preds = %entry
 bb:                                               ; preds = %bb3, %bb.nph14
   %indvar16 = phi i64 [ 0, %bb.nph14 ], [ %indvar.next17, %bb3 ] ; <i64> [#uses=3]
   %s.113 = phi i32 [ 0, %bb.nph14 ], [ %s.0.lcssa, %bb3 ] ; <i32> [#uses=2]
-  %scevgep2526 = getelementptr [123123 x %struct.anon]* @bars, i64 0, i64 %indvar16, i32 0 ; <i32*> [#uses=1]
-  %1 = load i32* %scevgep2526, align 4            ; <i32> [#uses=2]
+  %scevgep2526 = getelementptr [123123 x %struct.anon], [123123 x %struct.anon]* @bars, i64 0, i64 %indvar16, i32 0 ; <i32*> [#uses=1]
+  %1 = load i32, i32* %scevgep2526, align 4            ; <i32> [#uses=2]
   %2 = icmp sgt i32 %1, 0                         ; <i1> [#uses=1]
   br i1 %2, label %bb.nph, label %bb3
 
@@ -425,8 +425,8 @@ bb.nph:                                           ; preds = %bb
 bb1:                                              ; preds = %bb.nph, %bb1
   %indvar = phi i64 [ 0, %bb.nph ], [ %tmp19, %bb1 ] ; <i64> [#uses=2]
   %s.07 = phi i32 [ %s.113, %bb.nph ], [ %4, %bb1 ] ; <i32> [#uses=1]
-  %c.08 = getelementptr [123123 x %struct.anon]* @bars, i64 0, i64 %indvar16, i32 1, i64 %indvar ; <i32*> [#uses=1]
-  %3 = load i32* %c.08, align 4                   ; <i32> [#uses=1]
+  %c.08 = getelementptr [123123 x %struct.anon], [123123 x %struct.anon]* @bars, i64 0, i64 %indvar16, i32 1, i64 %indvar ; <i32*> [#uses=1]
+  %3 = load i32, i32* %c.08, align 4                   ; <i32> [#uses=1]
   %4 = add nsw i32 %3, %s.07                      ; <i32> [#uses=2]
   %tmp19 = add i64 %indvar, 1                     ; <i64> [#uses=2]
   %5 = icmp sgt i64 %tmp23, %tmp19                ; <i1> [#uses=1]
@@ -493,7 +493,7 @@ define void @test(float* %arg, i64 %arg1, float* nocapture %arg2, float* nocaptu
 bb:
   %t = alloca float, align 4                      ; <float*> [#uses=3]
   %t7 = alloca float, align 4                     ; <float*> [#uses=2]
-  %t8 = load float* %arg3                         ; <float> [#uses=8]
+  %t8 = load float, float* %arg3                         ; <float> [#uses=8]
   %t9 = ptrtoint float* %arg to i64               ; <i64> [#uses=1]
   %t10 = ptrtoint float* %arg4 to i64             ; <i64> [#uses=1]
   %t11 = xor i64 %t10, %t9                        ; <i64> [#uses=1]
@@ -507,15 +507,15 @@ bb:
   br i1 %t18, label %bb19, label %bb213
 
 bb19:                                             ; preds = %bb
-  %t20 = load float* %arg2                        ; <float> [#uses=1]
+  %t20 = load float, float* %arg2                        ; <float> [#uses=1]
   br label %bb21
 
 bb21:                                             ; preds = %bb32, %bb19
   %t22 = phi i64 [ %t36, %bb32 ], [ 0, %bb19 ]    ; <i64> [#uses=21]
   %t23 = phi float [ %t35, %bb32 ], [ %t20, %bb19 ] ; <float> [#uses=6]
   %t24 = sub i64 %arg6, %t22                      ; <i64> [#uses=4]
-  %t25 = getelementptr float* %arg4, i64 %t22     ; <float*> [#uses=4]
-  %t26 = getelementptr float* %arg, i64 %t22      ; <float*> [#uses=3]
+  %t25 = getelementptr float, float* %arg4, i64 %t22     ; <float*> [#uses=4]
+  %t26 = getelementptr float, float* %arg, i64 %t22      ; <float*> [#uses=3]
   %t27 = icmp sgt i64 %t24, 0                     ; <i1> [#uses=1]
   br i1 %t27, label %bb28, label %bb37
 
@@ -526,7 +526,7 @@ bb28:                                             ; preds = %bb21
   br i1 %t31, label %bb37, label %bb32
 
 bb32:                                             ; preds = %bb28
-  %t33 = load float* %t26                         ; <float> [#uses=1]
+  %t33 = load float, float* %t26                         ; <float> [#uses=1]
   %t34 = fmul float %t23, %t33                    ; <float> [#uses=1]
   store float %t34, float* %t25
   %t35 = fadd float %t23, %t8                     ; <float> [#uses=1]
@@ -561,8 +561,8 @@ bb57:                                             ; preds = %bb37
   br i1 %t56, label %bb61, label %bb112
 
 bb58:                                             ; preds = %bb68
-  %t59 = getelementptr float* %arg, i64 %t78      ; <float*> [#uses=1]
-  %t60 = getelementptr float* %arg4, i64 %t78     ; <float*> [#uses=1]
+  %t59 = getelementptr float, float* %arg, i64 %t78      ; <float*> [#uses=1]
+  %t60 = getelementptr float, float* %arg4, i64 %t78     ; <float*> [#uses=1]
   br label %bb112
 
 bb61:                                             ; preds = %bb57
@@ -582,32 +582,32 @@ bb68:                                             ; preds = %bb68, %bb61
   %t73 = phi <4 x float> [ %t52, %bb61 ], [ %t109, %bb68 ] ; <<4 x float>> [#uses=2]
   %t74 = shl i64 %t69, 4                          ; <i64> [#uses=5]
   %t75 = add i64 %t22, %t74                       ; <i64> [#uses=2]
-  %t76 = getelementptr float* %arg, i64 %t75      ; <float*> [#uses=1]
+  %t76 = getelementptr float, float* %arg, i64 %t75      ; <float*> [#uses=1]
   %t77 = bitcast float* %t76 to <4 x float>*      ; <<4 x float>*> [#uses=1]
   %t78 = add i64 %t62, %t74                       ; <i64> [#uses=2]
   %t79 = add i64 %t63, %t74                       ; <i64> [#uses=2]
-  %t80 = getelementptr float* %arg, i64 %t79      ; <float*> [#uses=1]
+  %t80 = getelementptr float, float* %arg, i64 %t79      ; <float*> [#uses=1]
   %t81 = bitcast float* %t80 to <4 x float>*      ; <<4 x float>*> [#uses=1]
   %t82 = add i64 %t64, %t74                       ; <i64> [#uses=2]
-  %t83 = getelementptr float* %arg, i64 %t82      ; <float*> [#uses=1]
+  %t83 = getelementptr float, float* %arg, i64 %t82      ; <float*> [#uses=1]
   %t84 = bitcast float* %t83 to <4 x float>*      ; <<4 x float>*> [#uses=1]
   %t85 = add i64 %t65, %t74                       ; <i64> [#uses=2]
-  %t86 = getelementptr float* %arg, i64 %t85      ; <float*> [#uses=1]
+  %t86 = getelementptr float, float* %arg, i64 %t85      ; <float*> [#uses=1]
   %t87 = bitcast float* %t86 to <4 x float>*      ; <<4 x float>*> [#uses=1]
-  %t88 = getelementptr float* %arg4, i64 %t75     ; <float*> [#uses=1]
+  %t88 = getelementptr float, float* %arg4, i64 %t75     ; <float*> [#uses=1]
   %t89 = bitcast float* %t88 to <4 x float>*      ; <<4 x float>*> [#uses=1]
-  %t90 = getelementptr float* %arg4, i64 %t79     ; <float*> [#uses=1]
+  %t90 = getelementptr float, float* %arg4, i64 %t79     ; <float*> [#uses=1]
   %t91 = bitcast float* %t90 to <4 x float>*      ; <<4 x float>*> [#uses=1]
-  %t92 = getelementptr float* %arg4, i64 %t82     ; <float*> [#uses=1]
+  %t92 = getelementptr float, float* %arg4, i64 %t82     ; <float*> [#uses=1]
   %t93 = bitcast float* %t92 to <4 x float>*      ; <<4 x float>*> [#uses=1]
-  %t94 = getelementptr float* %arg4, i64 %t85     ; <float*> [#uses=1]
+  %t94 = getelementptr float, float* %arg4, i64 %t85     ; <float*> [#uses=1]
   %t95 = bitcast float* %t94 to <4 x float>*      ; <<4 x float>*> [#uses=1]
   %t96 = mul i64 %t69, -16                        ; <i64> [#uses=1]
   %t97 = add i64 %t67, %t96                       ; <i64> [#uses=2]
-  %t98 = load <4 x float>* %t77                   ; <<4 x float>> [#uses=1]
-  %t99 = load <4 x float>* %t81                   ; <<4 x float>> [#uses=1]
-  %t100 = load <4 x float>* %t84                  ; <<4 x float>> [#uses=1]
-  %t101 = load <4 x float>* %t87                  ; <<4 x float>> [#uses=1]
+  %t98 = load <4 x float>, <4 x float>* %t77                   ; <<4 x float>> [#uses=1]
+  %t99 = load <4 x float>, <4 x float>* %t81                   ; <<4 x float>> [#uses=1]
+  %t100 = load <4 x float>, <4 x float>* %t84                  ; <<4 x float>> [#uses=1]
+  %t101 = load <4 x float>, <4 x float>* %t87                  ; <<4 x float>> [#uses=1]
   %t102 = fmul <4 x float> %t98, %t71             ; <<4 x float>> [#uses=1]
   %t103 = fadd <4 x float> %t71, %t55             ; <<4 x float>> [#uses=2]
   %t104 = fmul <4 x float> %t99, %t73             ; <<4 x float>> [#uses=1]
@@ -636,15 +636,15 @@ bb118:                                            ; preds = %bb37
   br i1 %t56, label %bb122, label %bb194
 
 bb119:                                            ; preds = %bb137
-  %t120 = getelementptr float* %arg, i64 %t145    ; <float*> [#uses=1]
-  %t121 = getelementptr float* %arg4, i64 %t145   ; <float*> [#uses=1]
+  %t120 = getelementptr float, float* %arg, i64 %t145    ; <float*> [#uses=1]
+  %t121 = getelementptr float, float* %arg4, i64 %t145   ; <float*> [#uses=1]
   br label %bb194
 
 bb122:                                            ; preds = %bb118
   %t123 = add i64 %t22, -1                        ; <i64> [#uses=1]
-  %t124 = getelementptr inbounds float* %arg, i64 %t123 ; <float*> [#uses=1]
+  %t124 = getelementptr inbounds float, float* %arg, i64 %t123 ; <float*> [#uses=1]
   %t125 = bitcast float* %t124 to <4 x float>*    ; <<4 x float>*> [#uses=1]
-  %t126 = load <4 x float>* %t125                 ; <<4 x float>> [#uses=1]
+  %t126 = load <4 x float>, <4 x float>* %t125                 ; <<4 x float>> [#uses=1]
   %t127 = add i64 %t22, 16                        ; <i64> [#uses=1]
   %t128 = add i64 %t22, 3                         ; <i64> [#uses=1]
   %t129 = add i64 %t22, 7                         ; <i64> [#uses=1]
@@ -667,35 +667,35 @@ bb137:                                            ; preds = %bb137, %bb122
   %t144 = shl i64 %t138, 4                        ; <i64> [#uses=9]
   %t145 = add i64 %t127, %t144                    ; <i64> [#uses=2]
   %t146 = add i64 %t128, %t144                    ; <i64> [#uses=1]
-  %t147 = getelementptr float* %arg, i64 %t146    ; <float*> [#uses=1]
+  %t147 = getelementptr float, float* %arg, i64 %t146    ; <float*> [#uses=1]
   %t148 = bitcast float* %t147 to <4 x float>*    ; <<4 x float>*> [#uses=1]
   %t149 = add i64 %t129, %t144                    ; <i64> [#uses=1]
-  %t150 = getelementptr float* %arg, i64 %t149    ; <float*> [#uses=1]
+  %t150 = getelementptr float, float* %arg, i64 %t149    ; <float*> [#uses=1]
   %t151 = bitcast float* %t150 to <4 x float>*    ; <<4 x float>*> [#uses=1]
   %t152 = add i64 %t130, %t144                    ; <i64> [#uses=1]
-  %t153 = getelementptr float* %arg, i64 %t152    ; <float*> [#uses=1]
+  %t153 = getelementptr float, float* %arg, i64 %t152    ; <float*> [#uses=1]
   %t154 = bitcast float* %t153 to <4 x float>*    ; <<4 x float>*> [#uses=1]
   %t155 = add i64 %t131, %t144                    ; <i64> [#uses=1]
-  %t156 = getelementptr float* %arg, i64 %t155    ; <float*> [#uses=1]
+  %t156 = getelementptr float, float* %arg, i64 %t155    ; <float*> [#uses=1]
   %t157 = bitcast float* %t156 to <4 x float>*    ; <<4 x float>*> [#uses=1]
   %t158 = add i64 %t22, %t144                     ; <i64> [#uses=1]
-  %t159 = getelementptr float* %arg4, i64 %t158   ; <float*> [#uses=1]
+  %t159 = getelementptr float, float* %arg4, i64 %t158   ; <float*> [#uses=1]
   %t160 = bitcast float* %t159 to <4 x float>*    ; <<4 x float>*> [#uses=1]
   %t161 = add i64 %t132, %t144                    ; <i64> [#uses=1]
-  %t162 = getelementptr float* %arg4, i64 %t161   ; <float*> [#uses=1]
+  %t162 = getelementptr float, float* %arg4, i64 %t161   ; <float*> [#uses=1]
   %t163 = bitcast float* %t162 to <4 x float>*    ; <<4 x float>*> [#uses=1]
   %t164 = add i64 %t133, %t144                    ; <i64> [#uses=1]
-  %t165 = getelementptr float* %arg4, i64 %t164   ; <float*> [#uses=1]
+  %t165 = getelementptr float, float* %arg4, i64 %t164   ; <float*> [#uses=1]
   %t166 = bitcast float* %t165 to <4 x float>*    ; <<4 x float>*> [#uses=1]
   %t167 = add i64 %t134, %t144                    ; <i64> [#uses=1]
-  %t168 = getelementptr float* %arg4, i64 %t167   ; <float*> [#uses=1]
+  %t168 = getelementptr float, float* %arg4, i64 %t167   ; <float*> [#uses=1]
   %t169 = bitcast float* %t168 to <4 x float>*    ; <<4 x float>*> [#uses=1]
   %t170 = mul i64 %t138, -16                      ; <i64> [#uses=1]
   %t171 = add i64 %t136, %t170                    ; <i64> [#uses=2]
-  %t172 = load <4 x float>* %t148                 ; <<4 x float>> [#uses=2]
-  %t173 = load <4 x float>* %t151                 ; <<4 x float>> [#uses=2]
-  %t174 = load <4 x float>* %t154                 ; <<4 x float>> [#uses=2]
-  %t175 = load <4 x float>* %t157                 ; <<4 x float>> [#uses=2]
+  %t172 = load <4 x float>, <4 x float>* %t148                 ; <<4 x float>> [#uses=2]
+  %t173 = load <4 x float>, <4 x float>* %t151                 ; <<4 x float>> [#uses=2]
+  %t174 = load <4 x float>, <4 x float>* %t154                 ; <<4 x float>> [#uses=2]
+  %t175 = load <4 x float>, <4 x float>* %t157                 ; <<4 x float>> [#uses=2]
   %t176 = shufflevector <4 x float> %t143, <4 x float> %t172, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
   %t177 = shufflevector <4 x float> %t176, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1]
   %t178 = shufflevector <4 x float> %t172, <4 x float> %t173, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
@@ -732,9 +732,9 @@ bb194:                                            ; preds = %bb119, %bb118, %bb1
 bb201:                                            ; preds = %bb201, %bb194
   %t202 = phi i64 [ %t209, %bb201 ], [ 0, %bb194 ] ; <i64> [#uses=3]
   %t203 = phi float [ %t208, %bb201 ], [ %t199, %bb194 ] ; <float> [#uses=2]
-  %t204 = getelementptr float* %t198, i64 %t202   ; <float*> [#uses=1]
-  %t205 = getelementptr float* %t197, i64 %t202   ; <float*> [#uses=1]
-  %t206 = load float* %t204                       ; <float> [#uses=1]
+  %t204 = getelementptr float, float* %t198, i64 %t202   ; <float*> [#uses=1]
+  %t205 = getelementptr float, float* %t197, i64 %t202   ; <float*> [#uses=1]
+  %t206 = load float, float* %t204                       ; <float> [#uses=1]
   %t207 = fmul float %t203, %t206                 ; <float> [#uses=1]
   store float %t207, float* %t205
   %t208 = fadd float %t203, %t8                   ; <float> [#uses=2]
diff --git a/test/CodeGen/X86/lsr-static-addr.ll b/test/CodeGen/X86/lsr-static-addr.ll
index 1bac790f57f9..1765ed7871d8 100644
--- a/test/CodeGen/X86/lsr-static-addr.ll
+++ b/test/CodeGen/X86/lsr-static-addr.ll
@@ -29,8 +29,8 @@ entry:
 
 for.body:
   %i.06 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr [0 x double]* @A, i64 0, i64 %i.06
-  %tmp3 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr [0 x double], [0 x double]* @A, i64 0, i64 %i.06
+  %tmp3 = load double, double* %arrayidx, align 8
   %mul = fmul double %tmp3, 2.300000e+00
   store double %mul, double* %arrayidx, align 8
   %inc = add nsw i64 %i.06, 1
diff --git a/test/CodeGen/X86/lsr-wrap.ll b/test/CodeGen/X86/lsr-wrap.ll
index d605e4f14fe4..adf954477791 100644
--- a/test/CodeGen/X86/lsr-wrap.ll
+++ b/test/CodeGen/X86/lsr-wrap.ll
@@ -20,7 +20,7 @@ bb:                                               ; preds = %bb, %entry
   %indvar = phi i16 [ 0, %entry ], [ %indvar.next, %bb ] ; <i16> [#uses=2]
   %tmp = sub i16 0, %indvar                       ; <i16> [#uses=1]
   %tmp27 = trunc i16 %tmp to i8                   ; <i8> [#uses=1]
-  %tmp1 = load i32* @g_19, align 4                ; <i32> [#uses=2]
+  %tmp1 = load i32, i32* @g_19, align 4                ; <i32> [#uses=2]
   %tmp2 = add i32 %tmp1, 1                        ; <i32> [#uses=1]
   store i32 %tmp2, i32* @g_19, align 4
   %tmp3 = trunc i32 %tmp1 to i8                   ; <i8> [#uses=1]
diff --git a/test/CodeGen/X86/lzcnt-tzcnt.ll b/test/CodeGen/X86/lzcnt-tzcnt.ll
index e98764a0d787..aa9ae2b7b100 100644
--- a/test/CodeGen/X86/lzcnt-tzcnt.ll
+++ b/test/CodeGen/X86/lzcnt-tzcnt.ll
@@ -106,7 +106,7 @@ define i64 @test9_ctlz(i64 %v) {
 
 
 define i16 @test10_ctlz(i16* %ptr) {
-  %v = load i16* %ptr
+  %v = load i16, i16* %ptr
   %cnt = tail call i16 @llvm.ctlz.i16(i16 %v, i1 true)
   %tobool = icmp eq i16 %v, 0
   %cond = select i1 %tobool, i16 16, i16 %cnt
@@ -119,7 +119,7 @@ define i16 @test10_ctlz(i16* %ptr) {
 
 
 define i32 @test11_ctlz(i32* %ptr) {
-  %v = load i32* %ptr
+  %v = load i32, i32* %ptr
   %cnt = tail call i32 @llvm.ctlz.i32(i32 %v, i1 true)
   %tobool = icmp eq i32 %v, 0
   %cond = select i1 %tobool, i32 32, i32 %cnt
@@ -132,7 +132,7 @@ define i32 @test11_ctlz(i32* %ptr) {
 
 
 define i64 @test12_ctlz(i64* %ptr) {
-  %v = load i64* %ptr
+  %v = load i64, i64* %ptr
   %cnt = tail call i64 @llvm.ctlz.i64(i64 %v, i1 true)
   %tobool = icmp eq i64 %v, 0
   %cond = select i1 %tobool, i64 64, i64 %cnt
@@ -145,7 +145,7 @@ define i64 @test12_ctlz(i64* %ptr) {
 
 
 define i16 @test13_ctlz(i16* %ptr) {
-  %v = load i16* %ptr
+  %v = load i16, i16* %ptr
   %cnt = tail call i16 @llvm.ctlz.i16(i16 %v, i1 true)
   %tobool = icmp eq i16 0, %v
   %cond = select i1 %tobool, i16 16, i16 %cnt
@@ -158,7 +158,7 @@ define i16 @test13_ctlz(i16* %ptr) {
 
 
 define i32 @test14_ctlz(i32* %ptr) {
-  %v = load i32* %ptr
+  %v = load i32, i32* %ptr
   %cnt = tail call i32 @llvm.ctlz.i32(i32 %v, i1 true)
   %tobool = icmp eq i32 0, %v
   %cond = select i1 %tobool, i32 32, i32 %cnt
@@ -171,7 +171,7 @@ define i32 @test14_ctlz(i32* %ptr) {
 
 
 define i64 @test15_ctlz(i64* %ptr) {
-  %v = load i64* %ptr
+  %v = load i64, i64* %ptr
   %cnt = tail call i64 @llvm.ctlz.i64(i64 %v, i1 true)
   %tobool = icmp eq i64 0, %v
   %cond = select i1 %tobool, i64 64, i64 %cnt
@@ -184,7 +184,7 @@ define i64 @test15_ctlz(i64* %ptr) {
 
 
 define i16 @test16_ctlz(i16* %ptr) {
-  %v = load i16* %ptr
+  %v = load i16, i16* %ptr
   %cnt = tail call i16 @llvm.ctlz.i16(i16 %v, i1 true)
   %tobool = icmp eq i16 0, %v
   %cond = select i1 %tobool, i16 %cnt, i16 16
@@ -197,7 +197,7 @@ define i16 @test16_ctlz(i16* %ptr) {
 
 
 define i32 @test17_ctlz(i32* %ptr) {
-  %v = load i32* %ptr
+  %v = load i32, i32* %ptr
   %cnt = tail call i32 @llvm.ctlz.i32(i32 %v, i1 true)
   %tobool = icmp eq i32 0, %v
   %cond = select i1 %tobool, i32 %cnt, i32 32
@@ -210,7 +210,7 @@ define i32 @test17_ctlz(i32* %ptr) {
 
 
 define i64 @test18_ctlz(i64* %ptr) {
-  %v = load i64* %ptr
+  %v = load i64, i64* %ptr
   %cnt = tail call i64 @llvm.ctlz.i64(i64 %v, i1 true)
   %tobool = icmp eq i64 0, %v
   %cond = select i1 %tobool, i64 %cnt, i64 64
@@ -322,7 +322,7 @@ define i64 @test9_cttz(i64 %v) {
 
 
 define i16 @test10_cttz(i16* %ptr) {
-  %v = load i16* %ptr
+  %v = load i16, i16* %ptr
   %cnt = tail call i16 @llvm.cttz.i16(i16 %v, i1 true)
   %tobool = icmp eq i16 %v, 0
   %cond = select i1 %tobool, i16 16, i16 %cnt
@@ -335,7 +335,7 @@ define i16 @test10_cttz(i16* %ptr) {
 
 
 define i32 @test11_cttz(i32* %ptr) {
-  %v = load i32* %ptr
+  %v = load i32, i32* %ptr
   %cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true)
   %tobool = icmp eq i32 %v, 0
   %cond = select i1 %tobool, i32 32, i32 %cnt
@@ -348,7 +348,7 @@ define i32 @test11_cttz(i32* %ptr) {
 
 
 define i64 @test12_cttz(i64* %ptr) {
-  %v = load i64* %ptr
+  %v = load i64, i64* %ptr
   %cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true)
   %tobool = icmp eq i64 %v, 0
   %cond = select i1 %tobool, i64 64, i64 %cnt
@@ -361,7 +361,7 @@ define i64 @test12_cttz(i64* %ptr) {
 
 
 define i16 @test13_cttz(i16* %ptr) {
-  %v = load i16* %ptr
+  %v = load i16, i16* %ptr
   %cnt = tail call i16 @llvm.cttz.i16(i16 %v, i1 true)
   %tobool = icmp eq i16 0, %v
   %cond = select i1 %tobool, i16 16, i16 %cnt
@@ -374,7 +374,7 @@ define i16 @test13_cttz(i16* %ptr) {
 
 
 define i32 @test14_cttz(i32* %ptr) {
-  %v = load i32* %ptr
+  %v = load i32, i32* %ptr
   %cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true)
   %tobool = icmp eq i32 0, %v
   %cond = select i1 %tobool, i32 32, i32 %cnt
@@ -387,7 +387,7 @@ define i32 @test14_cttz(i32* %ptr) {
 
 
 define i64 @test15_cttz(i64* %ptr) {
-  %v = load i64* %ptr
+  %v = load i64, i64* %ptr
   %cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true)
   %tobool = icmp eq i64 0, %v
   %cond = select i1 %tobool, i64 64, i64 %cnt
@@ -400,7 +400,7 @@ define i64 @test15_cttz(i64* %ptr) {
 
 
 define i16 @test16_cttz(i16* %ptr) {
-  %v = load i16* %ptr
+  %v = load i16, i16* %ptr
   %cnt = tail call i16 @llvm.cttz.i16(i16 %v, i1 true)
   %tobool = icmp eq i16 0, %v
   %cond = select i1 %tobool, i16 %cnt, i16 16
@@ -413,7 +413,7 @@ define i16 @test16_cttz(i16* %ptr) {
 
 
 define i32 @test17_cttz(i32* %ptr) {
-  %v = load i32* %ptr
+  %v = load i32, i32* %ptr
   %cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true)
   %tobool = icmp eq i32 0, %v
   %cond = select i1 %tobool, i32 %cnt, i32 32
@@ -426,7 +426,7 @@ define i32 @test17_cttz(i32* %ptr) {
 
 
 define i64 @test18_cttz(i64* %ptr) {
-  %v = load i64* %ptr
+  %v = load i64, i64* %ptr
   %cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true)
   %tobool = icmp eq i64 0, %v
   %cond = select i1 %tobool, i64 %cnt, i64 64
diff --git a/test/CodeGen/X86/machine-cse.ll b/test/CodeGen/X86/machine-cse.ll
index 409147b1d1f1..c6876d29dfc2 100644
--- a/test/CodeGen/X86/machine-cse.ll
+++ b/test/CodeGen/X86/machine-cse.ll
@@ -11,7 +11,7 @@ entry:
 ; CHECK-LABEL: t:
 ; CHECK: leaq (%rax,%rax,4)
   %0 = zext i32 %base to i64
-  %1 = getelementptr inbounds %struct.s2* null, i64 %0
+  %1 = getelementptr inbounds %struct.s2, %struct.s2* null, i64 %0
   br i1 undef, label %bb1, label %bb2
 
 bb1:
@@ -19,7 +19,7 @@ bb1:
 ; CHECK-NOT: shlq $9
 ; CHECK-NOT: leaq
 ; CHECK: call
-  %2 = getelementptr inbounds %struct.s2* null, i64 %0, i32 0
+  %2 = getelementptr inbounds %struct.s2, %struct.s2* null, i64 %0, i32 0
   call void @bar(i32* %2) nounwind
   unreachable
 
@@ -62,7 +62,7 @@ if.end34:                                         ; preds = %sw.bb
 ; CHECK: %if.end34
 ; CHECK: leal
 ; CHECK-NOT: imull
-  tail call void (...)* @printf(i32 %test_case, i32 %mul20) nounwind
+  tail call void (...) @printf(i32 %test_case, i32 %mul20) nounwind
   %tmp = mul i32 %scale, %test_case
   %tmp752 = mul i32 %tmp, 3
   %tmp753 = zext i32 %tmp752 to i64
@@ -126,7 +126,7 @@ do.body:
   br i1 %cmp3, label %return, label %do.cond
 
 do.cond:
-  %incdec.ptr = getelementptr inbounds i8* %p.0, i64 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %p.0, i64 1
   %dec = add i64 %n.addr.0, -1
   %cmp6 = icmp eq i64 %dec, 0
   br i1 %cmp6, label %return, label %do.body
@@ -147,7 +147,7 @@ define i32 @t2() {
   br i1 %c, label %a, label %b
 
 a:
-  %l = load i32* @t2_global
+  %l = load i32, i32* @t2_global
   ret i32 %l
 
 b:
diff --git a/test/CodeGen/X86/masked-iv-safe.ll b/test/CodeGen/X86/masked-iv-safe.ll
index 9ddc84708d5b..8c0a4d4f1752 100644
--- a/test/CodeGen/X86/masked-iv-safe.ll
+++ b/test/CodeGen/X86/masked-iv-safe.ll
@@ -15,17 +15,17 @@ entry:
 loop:
 	%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
 	%indvar.i8 = and i64 %indvar, 255
-	%t0 = getelementptr double* %d, i64 %indvar.i8
-	%t1 = load double* %t0
+	%t0 = getelementptr double, double* %d, i64 %indvar.i8
+	%t1 = load double, double* %t0
 	%t2 = fmul double %t1, 0.1
 	store double %t2, double* %t0
 	%indvar.i24 = and i64 %indvar, 16777215
-	%t3 = getelementptr double* %d, i64 %indvar.i24
-	%t4 = load double* %t3
+	%t3 = getelementptr double, double* %d, i64 %indvar.i24
+	%t4 = load double, double* %t3
 	%t5 = fmul double %t4, 2.3
 	store double %t5, double* %t3
-	%t6 = getelementptr double* %d, i64 %indvar
-	%t7 = load double* %t6
+	%t6 = getelementptr double, double* %d, i64 %indvar
+	%t7 = load double, double* %t6
 	%t8 = fmul double %t7, 4.5
 	store double %t8, double* %t6
 	%indvar.next = add i64 %indvar, 1
@@ -48,17 +48,17 @@ entry:
 loop:
 	%indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
 	%indvar.i8 = and i64 %indvar, 255
-	%t0 = getelementptr double* %d, i64 %indvar.i8
-	%t1 = load double* %t0
+	%t0 = getelementptr double, double* %d, i64 %indvar.i8
+	%t1 = load double, double* %t0
 	%t2 = fmul double %t1, 0.1
 	store double %t2, double* %t0
 	%indvar.i24 = and i64 %indvar, 16777215
-	%t3 = getelementptr double* %d, i64 %indvar.i24
-	%t4 = load double* %t3
+	%t3 = getelementptr double, double* %d, i64 %indvar.i24
+	%t4 = load double, double* %t3
 	%t5 = fmul double %t4, 2.3
 	store double %t5, double* %t3
-	%t6 = getelementptr double* %d, i64 %indvar
-	%t7 = load double* %t6
+	%t6 = getelementptr double, double* %d, i64 %indvar
+	%t7 = load double, double* %t6
 	%t8 = fmul double %t7, 4.5
 	store double %t8, double* %t6
 	%indvar.next = sub i64 %indvar, 1
@@ -82,18 +82,18 @@ loop:
 	%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
         %s0 = shl i64 %indvar, 8
 	%indvar.i8 = ashr i64 %s0, 8
-	%t0 = getelementptr double* %d, i64 %indvar.i8
-	%t1 = load double* %t0
+	%t0 = getelementptr double, double* %d, i64 %indvar.i8
+	%t1 = load double, double* %t0
 	%t2 = fmul double %t1, 0.1
 	store double %t2, double* %t0
 	%s1 = shl i64 %indvar, 24
 	%indvar.i24 = ashr i64 %s1, 24
-	%t3 = getelementptr double* %d, i64 %indvar.i24
-	%t4 = load double* %t3
+	%t3 = getelementptr double, double* %d, i64 %indvar.i24
+	%t4 = load double, double* %t3
 	%t5 = fmul double %t4, 2.3
 	store double %t5, double* %t3
-	%t6 = getelementptr double* %d, i64 %indvar
-	%t7 = load double* %t6
+	%t6 = getelementptr double, double* %d, i64 %indvar
+	%t7 = load double, double* %t6
 	%t8 = fmul double %t7, 4.5
 	store double %t8, double* %t6
 	%indvar.next = add i64 %indvar, 1
@@ -117,18 +117,18 @@ loop:
 	%indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
         %s0 = shl i64 %indvar, 8
 	%indvar.i8 = ashr i64 %s0, 8
-	%t0 = getelementptr double* %d, i64 %indvar.i8
-	%t1 = load double* %t0
+	%t0 = getelementptr double, double* %d, i64 %indvar.i8
+	%t1 = load double, double* %t0
 	%t2 = fmul double %t1, 0.1
 	store double %t2, double* %t0
 	%s1 = shl i64 %indvar, 24
 	%indvar.i24 = ashr i64 %s1, 24
-	%t3 = getelementptr double* %d, i64 %indvar.i24
-	%t4 = load double* %t3
+	%t3 = getelementptr double, double* %d, i64 %indvar.i24
+	%t4 = load double, double* %t3
 	%t5 = fmul double %t4, 2.3
 	store double %t5, double* %t3
-	%t6 = getelementptr double* %d, i64 %indvar
-	%t7 = load double* %t6
+	%t6 = getelementptr double, double* %d, i64 %indvar
+	%t7 = load double, double* %t6
 	%t8 = fmul double %t7, 4.5
 	store double %t8, double* %t6
 	%indvar.next = sub i64 %indvar, 1
@@ -151,17 +151,17 @@ entry:
 loop:
 	%indvar = phi i64 [ 18446744073709551615, %entry ], [ %indvar.next, %loop ]
 	%indvar.i8 = and i64 %indvar, 255
-	%t0 = getelementptr double* %d, i64 %indvar.i8
-	%t1 = load double* %t0
+	%t0 = getelementptr double, double* %d, i64 %indvar.i8
+	%t1 = load double, double* %t0
 	%t2 = fmul double %t1, 0.1
 	store double %t2, double* %t0
 	%indvar.i24 = and i64 %indvar, 16777215
-	%t3 = getelementptr double* %d, i64 %indvar.i24
-	%t4 = load double* %t3
+	%t3 = getelementptr double, double* %d, i64 %indvar.i24
+	%t4 = load double, double* %t3
 	%t5 = fmul double %t4, 2.3
 	store double %t5, double* %t3
-	%t6 = getelementptr double* %d, i64 %indvar
-	%t7 = load double* %t6
+	%t6 = getelementptr double, double* %d, i64 %indvar
+	%t7 = load double, double* %t6
 	%t8 = fmul double %t7, 4.5
 	store double %t8, double* %t6
 	%indvar.next = add i64 %indvar, 1
@@ -184,17 +184,17 @@ entry:
 loop:
 	%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
 	%indvar.i8 = and i64 %indvar, 255
-	%t0 = getelementptr double* %d, i64 %indvar.i8
-	%t1 = load double* %t0
+	%t0 = getelementptr double, double* %d, i64 %indvar.i8
+	%t1 = load double, double* %t0
 	%t2 = fmul double %t1, 0.1
 	store double %t2, double* %t0
 	%indvar.i24 = and i64 %indvar, 16777215
-	%t3 = getelementptr double* %d, i64 %indvar.i24
-	%t4 = load double* %t3
+	%t3 = getelementptr double, double* %d, i64 %indvar.i24
+	%t4 = load double, double* %t3
 	%t5 = fdiv double %t4, 2.3
 	store double %t5, double* %t3
-	%t6 = getelementptr double* %d, i64 %indvar
-	%t7 = load double* %t6
+	%t6 = getelementptr double, double* %d, i64 %indvar
+	%t7 = load double, double* %t6
 	%t8 = fmul double %t7, 4.5
 	store double %t8, double* %t6
 	%indvar.next = sub i64 %indvar, 1
@@ -218,18 +218,18 @@ loop:
 	%indvar = phi i64 [ 18446744073709551615, %entry ], [ %indvar.next, %loop ]
         %s0 = shl i64 %indvar, 8
 	%indvar.i8 = ashr i64 %s0, 8
-	%t0 = getelementptr double* %d, i64 %indvar.i8
-	%t1 = load double* %t0
+	%t0 = getelementptr double, double* %d, i64 %indvar.i8
+	%t1 = load double, double* %t0
 	%t2 = fmul double %t1, 0.1
 	store double %t2, double* %t0
 	%s1 = shl i64 %indvar, 24
 	%indvar.i24 = ashr i64 %s1, 24
-	%t3 = getelementptr double* %d, i64 %indvar.i24
-	%t4 = load double* %t3
+	%t3 = getelementptr double, double* %d, i64 %indvar.i24
+	%t4 = load double, double* %t3
 	%t5 = fdiv double %t4, 2.3
 	store double %t5, double* %t3
-	%t6 = getelementptr double* %d, i64 %indvar
-	%t7 = load double* %t6
+	%t6 = getelementptr double, double* %d, i64 %indvar
+	%t7 = load double, double* %t6
 	%t8 = fmul double %t7, 4.5
 	store double %t8, double* %t6
 	%indvar.next = add i64 %indvar, 1
@@ -253,18 +253,18 @@ loop:
 	%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
         %s0 = shl i64 %indvar, 8
 	%indvar.i8 = ashr i64 %s0, 8
-	%t0 = getelementptr double* %d, i64 %indvar.i8
-	%t1 = load double* %t0
+	%t0 = getelementptr double, double* %d, i64 %indvar.i8
+	%t1 = load double, double* %t0
 	%t2 = fmul double %t1, 0.1
 	store double %t2, double* %t0
 	%s1 = shl i64 %indvar, 24
 	%indvar.i24 = ashr i64 %s1, 24
-	%t3 = getelementptr double* %d, i64 %indvar.i24
-	%t4 = load double* %t3
+	%t3 = getelementptr double, double* %d, i64 %indvar.i24
+	%t4 = load double, double* %t3
 	%t5 = fdiv double %t4, 2.3
 	store double %t5, double* %t3
-	%t6 = getelementptr double* %d, i64 %indvar
-	%t7 = load double* %t6
+	%t6 = getelementptr double, double* %d, i64 %indvar
+	%t7 = load double, double* %t6
 	%t8 = fmul double %t7, 4.5
 	store double %t8, double* %t6
 	%indvar.next = sub i64 %indvar, 1
diff --git a/test/CodeGen/X86/masked-iv-unsafe.ll b/test/CodeGen/X86/masked-iv-unsafe.ll
index f23c02019548..974a1cfb90d1 100644
--- a/test/CodeGen/X86/masked-iv-unsafe.ll
+++ b/test/CodeGen/X86/masked-iv-unsafe.ll
@@ -13,17 +13,17 @@ entry:
 loop:
 	%indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
 	%indvar.i8 = and i64 %indvar, 255
-	%t0 = getelementptr double* %d, i64 %indvar.i8
-	%t1 = load double* %t0
+	%t0 = getelementptr double, double* %d, i64 %indvar.i8
+	%t1 = load double, double* %t0
 	%t2 = fmul double %t1, 0.1
 	store double %t2, double* %t0
 	%indvar.i24 = and i64 %indvar, 16777215
-	%t3 = getelementptr double* %d, i64 %indvar.i24
-	%t4 = load double* %t3
+	%t3 = getelementptr double, double* %d, i64 %indvar.i24
+	%t4 = load double, double* %t3
 	%t5 = fmul double %t4, 2.3
 	store double %t5, double* %t3
-	%t6 = getelementptr double* %d, i64 %indvar
-	%t7 = load double* %t6
+	%t6 = getelementptr double, double* %d, i64 %indvar
+	%t7 = load double, double* %t6
 	%t8 = fmul double %t7, 4.5
 	store double %t8, double* %t6
 	%indvar.next = add i64 %indvar, 1
@@ -41,17 +41,17 @@ entry:
 loop:
 	%indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
 	%indvar.i8 = and i64 %indvar, 255
-	%t0 = getelementptr double* %d, i64 %indvar.i8
-	%t1 = load double* %t0
+	%t0 = getelementptr double, double* %d, i64 %indvar.i8
+	%t1 = load double, double* %t0
 	%t2 = fmul double %t1, 0.1
 	store double %t2, double* %t0
 	%indvar.i24 = and i64 %indvar, 16777215
-	%t3 = getelementptr double* %d, i64 %indvar.i24
-	%t4 = load double* %t3
+	%t3 = getelementptr double, double* %d, i64 %indvar.i24
+	%t4 = load double, double* %t3
 	%t5 = fmul double %t4, 2.3
 	store double %t5, double* %t3
-	%t6 = getelementptr double* %d, i64 %indvar
-	%t7 = load double* %t6
+	%t6 = getelementptr double, double* %d, i64 %indvar
+	%t7 = load double, double* %t6
 	%t8 = fmul double %t7, 4.5
 	store double %t8, double* %t6
 	%indvar.next = sub i64 %indvar, 1
@@ -70,18 +70,18 @@ loop:
 	%indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
         %s0 = shl i64 %indvar, 8
 	%indvar.i8 = ashr i64 %s0, 8
-	%t0 = getelementptr double* %d, i64 %indvar.i8
-	%t1 = load double* %t0
+	%t0 = getelementptr double, double* %d, i64 %indvar.i8
+	%t1 = load double, double* %t0
 	%t2 = fmul double %t1, 0.1
 	store double %t2, double* %t0
 	%s1 = shl i64 %indvar, 24
 	%indvar.i24 = ashr i64 %s1, 24
-	%t3 = getelementptr double* %d, i64 %indvar.i24
-	%t4 = load double* %t3
+	%t3 = getelementptr double, double* %d, i64 %indvar.i24
+	%t4 = load double, double* %t3
 	%t5 = fmul double %t4, 2.3
 	store double %t5, double* %t3
-	%t6 = getelementptr double* %d, i64 %indvar
-	%t7 = load double* %t6
+	%t6 = getelementptr double, double* %d, i64 %indvar
+	%t7 = load double, double* %t6
 	%t8 = fmul double %t7, 4.5
 	store double %t8, double* %t6
 	%indvar.next = add i64 %indvar, 1
@@ -100,18 +100,18 @@ loop:
 	%indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
         %s0 = shl i64 %indvar, 8
 	%indvar.i8 = ashr i64 %s0, 8
-	%t0 = getelementptr double* %d, i64 %indvar.i8
-	%t1 = load double* %t0
+	%t0 = getelementptr double, double* %d, i64 %indvar.i8
+	%t1 = load double, double* %t0
 	%t2 = fmul double %t1, 0.1
 	store double %t2, double* %t0
 	%s1 = shl i64 %indvar, 24
 	%indvar.i24 = ashr i64 %s1, 24
-	%t3 = getelementptr double* %d, i64 %indvar.i24
-	%t4 = load double* %t3
+	%t3 = getelementptr double, double* %d, i64 %indvar.i24
+	%t4 = load double, double* %t3
 	%t5 = fmul double %t4, 2.3
 	store double %t5, double* %t3
-	%t6 = getelementptr double* %d, i64 %indvar
-	%t7 = load double* %t6
+	%t6 = getelementptr double, double* %d, i64 %indvar
+	%t7 = load double, double* %t6
 	%t8 = fmul double %t7, 4.5
 	store double %t8, double* %t6
 	%indvar.next = sub i64 %indvar, 1
@@ -129,17 +129,17 @@ entry:
 loop:
         %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
         %indvar.i8 = and i64 %indvar, 255
-        %t0 = getelementptr double* %d, i64 %indvar.i8
-        %t1 = load double* %t0
+        %t0 = getelementptr double, double* %d, i64 %indvar.i8
+        %t1 = load double, double* %t0
         %t2 = fmul double %t1, 0.1
         store double %t2, double* %t0
         %indvar.i24 = and i64 %indvar, 16777215
-        %t3 = getelementptr double* %d, i64 %indvar.i24
-        %t4 = load double* %t3
+        %t3 = getelementptr double, double* %d, i64 %indvar.i24
+        %t4 = load double, double* %t3
         %t5 = fmul double %t4, 2.3
         store double %t5, double* %t3
-        %t6 = getelementptr double* %d, i64 %indvar
-        %t7 = load double* %t6
+        %t6 = getelementptr double, double* %d, i64 %indvar
+        %t7 = load double, double* %t6
         %t8 = fmul double %t7, 4.5
         store double %t8, double* %t6
         %indvar.next = add i64 %indvar, 1
@@ -157,17 +157,17 @@ entry:
 loop:
         %indvar = phi i64 [ %n, %entry ], [ %indvar.next, %loop ]
         %indvar.i8 = and i64 %indvar, 255
-        %t0 = getelementptr double* %d, i64 %indvar.i8
-        %t1 = load double* %t0
+        %t0 = getelementptr double, double* %d, i64 %indvar.i8
+        %t1 = load double, double* %t0
         %t2 = fmul double %t1, 0.1
         store double %t2, double* %t0
         %indvar.i24 = and i64 %indvar, 16777215
-        %t3 = getelementptr double* %d, i64 %indvar.i24
-        %t4 = load double* %t3
+        %t3 = getelementptr double, double* %d, i64 %indvar.i24
+        %t4 = load double, double* %t3
         %t5 = fmul double %t4, 2.3
         store double %t5, double* %t3
-        %t6 = getelementptr double* %d, i64 %indvar
-        %t7 = load double* %t6
+        %t6 = getelementptr double, double* %d, i64 %indvar
+        %t7 = load double, double* %t6
         %t8 = fmul double %t7, 4.5
         store double %t8, double* %t6
         %indvar.next = sub i64 %indvar, 1
@@ -186,18 +186,18 @@ loop:
         %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
         %s0 = shl i64 %indvar, 8
         %indvar.i8 = ashr i64 %s0, 8
-        %t0 = getelementptr double* %d, i64 %indvar.i8
-        %t1 = load double* %t0
+        %t0 = getelementptr double, double* %d, i64 %indvar.i8
+        %t1 = load double, double* %t0
         %t2 = fmul double %t1, 0.1
         store double %t2, double* %t0
         %s1 = shl i64 %indvar, 24
         %indvar.i24 = ashr i64 %s1, 24
-        %t3 = getelementptr double* %d, i64 %indvar.i24
-        %t4 = load double* %t3
+        %t3 = getelementptr double, double* %d, i64 %indvar.i24
+        %t4 = load double, double* %t3
         %t5 = fmul double %t4, 2.3
         store double %t5, double* %t3
-        %t6 = getelementptr double* %d, i64 %indvar
-        %t7 = load double* %t6
+        %t6 = getelementptr double, double* %d, i64 %indvar
+        %t7 = load double, double* %t6
         %t8 = fmul double %t7, 4.5
         store double %t8, double* %t6
         %indvar.next = add i64 %indvar, 1
@@ -216,18 +216,18 @@ loop:
         %indvar = phi i64 [ %n, %entry ], [ %indvar.next, %loop ]
         %s0 = shl i64 %indvar, 8
         %indvar.i8 = ashr i64 %s0, 8
-        %t0 = getelementptr double* %d, i64 %indvar.i8
-        %t1 = load double* %t0
+        %t0 = getelementptr double, double* %d, i64 %indvar.i8
+        %t1 = load double, double* %t0
         %t2 = fmul double %t1, 0.1
         store double %t2, double* %t0
         %s1 = shl i64 %indvar, 24
         %indvar.i24 = ashr i64 %s1, 24
-        %t3 = getelementptr double* %d, i64 %indvar.i24
-        %t4 = load double* %t3
+        %t3 = getelementptr double, double* %d, i64 %indvar.i24
+        %t4 = load double, double* %t3
         %t5 = fmul double %t4, 2.3
         store double %t5, double* %t3
-        %t6 = getelementptr double* %d, i64 %indvar
-        %t7 = load double* %t6
+        %t6 = getelementptr double, double* %d, i64 %indvar
+        %t7 = load double, double* %t6
         %t8 = fmul double %t7, 4.5
         store double %t8, double* %t6
         %indvar.next = sub i64 %indvar, 1
@@ -245,17 +245,17 @@ entry:
 loop:
 	%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
 	%indvar.i8 = and i64 %indvar, 255
-	%t0 = getelementptr double* %d, i64 %indvar.i8
-	%t1 = load double* %t0
+	%t0 = getelementptr double, double* %d, i64 %indvar.i8
+	%t1 = load double, double* %t0
 	%t2 = fmul double %t1, 0.1
 	store double %t2, double* %t0
 	%indvar.i24 = and i64 %indvar, 16777215
-	%t3 = getelementptr double* %d, i64 %indvar.i24
-	%t4 = load double* %t3
+	%t3 = getelementptr double, double* %d, i64 %indvar.i24
+	%t4 = load double, double* %t3
 	%t5 = fmul double %t4, 2.3
 	store double %t5, double* %t3
-	%t6 = getelementptr double* %d, i64 %indvar
-	%t7 = load double* %t6
+	%t6 = getelementptr double, double* %d, i64 %indvar
+	%t7 = load double, double* %t6
 	%t8 = fmul double %t7, 4.5
 	store double %t8, double* %t6
 	%indvar.next = sub i64 %indvar, 1
@@ -273,17 +273,17 @@ entry:
 loop:
         %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
         %indvar.i8 = and i64 %indvar, 255
-        %t0 = getelementptr double* %d, i64 %indvar.i8
-        %t1 = load double* %t0
+        %t0 = getelementptr double, double* %d, i64 %indvar.i8
+        %t1 = load double, double* %t0
         %t2 = fmul double %t1, 0.1
         store double %t2, double* %t0
         %indvar.i24 = and i64 %indvar, 16777215
-        %t3 = getelementptr double* %d, i64 %indvar.i24
-        %t4 = load double* %t3
+        %t3 = getelementptr double, double* %d, i64 %indvar.i24
+        %t4 = load double, double* %t3
         %t5 = fmul double %t4, 2.3
         store double %t5, double* %t3
-        %t6 = getelementptr double* %d, i64 %indvar
-        %t7 = load double* %t6
+        %t6 = getelementptr double, double* %d, i64 %indvar
+        %t7 = load double, double* %t6
         %t8 = fmul double %t7, 4.5
         store double %t8, double* %t6
         %indvar.next = add i64 %indvar, 3
@@ -301,17 +301,17 @@ entry:
 loop:
         %indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
         %indvar.i8 = and i64 %indvar, 255
-        %t0 = getelementptr double* %d, i64 %indvar.i8
-        %t1 = load double* %t0
+        %t0 = getelementptr double, double* %d, i64 %indvar.i8
+        %t1 = load double, double* %t0
         %t2 = fmul double %t1, 0.1
         store double %t2, double* %t0
         %indvar.i24 = and i64 %indvar, 16777215
-        %t3 = getelementptr double* %d, i64 %indvar.i24
-        %t4 = load double* %t3
+        %t3 = getelementptr double, double* %d, i64 %indvar.i24
+        %t4 = load double, double* %t3
         %t5 = fmul double %t4, 2.3
         store double %t5, double* %t3
-        %t6 = getelementptr double* %d, i64 %indvar
-        %t7 = load double* %t6
+        %t6 = getelementptr double, double* %d, i64 %indvar
+        %t7 = load double, double* %t6
         %t8 = fmul double %t7, 4.5
         store double %t8, double* %t6
         %indvar.next = sub i64 %indvar, 3
@@ -330,18 +330,18 @@ loop:
         %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
         %s0 = shl i64 %indvar, 8
         %indvar.i8 = ashr i64 %s0, 8
-        %t0 = getelementptr double* %d, i64 %indvar.i8
-        %t1 = load double* %t0
+        %t0 = getelementptr double, double* %d, i64 %indvar.i8
+        %t1 = load double, double* %t0
         %t2 = fmul double %t1, 0.1
         store double %t2, double* %t0
         %s1 = shl i64 %indvar, 24
         %indvar.i24 = ashr i64 %s1, 24
-        %t3 = getelementptr double* %d, i64 %indvar.i24
-        %t4 = load double* %t3
+        %t3 = getelementptr double, double* %d, i64 %indvar.i24
+        %t4 = load double, double* %t3
         %t5 = fmul double %t4, 2.3
         store double %t5, double* %t3
-        %t6 = getelementptr double* %d, i64 %indvar
-        %t7 = load double* %t6
+        %t6 = getelementptr double, double* %d, i64 %indvar
+        %t7 = load double, double* %t6
         %t8 = fmul double %t7, 4.5
         store double %t8, double* %t6
         %indvar.next = add i64 %indvar, 3
@@ -360,18 +360,18 @@ loop:
         %indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
         %s0 = shl i64 %indvar, 8
         %indvar.i8 = ashr i64 %s0, 8
-        %t0 = getelementptr double* %d, i64 %indvar.i8
-        %t1 = load double* %t0
+        %t0 = getelementptr double, double* %d, i64 %indvar.i8
+        %t1 = load double, double* %t0
         %t2 = fmul double %t1, 0.1
         store double %t2, double* %t0
         %s1 = shl i64 %indvar, 24
         %indvar.i24 = ashr i64 %s1, 24
-        %t3 = getelementptr double* %d, i64 %indvar.i24
-        %t4 = load double* %t3
+        %t3 = getelementptr double, double* %d, i64 %indvar.i24
+        %t4 = load double, double* %t3
         %t5 = fmul double %t4, 2.3
         store double %t5, double* %t3
-        %t6 = getelementptr double* %d, i64 %indvar
-        %t7 = load double* %t6
+        %t6 = getelementptr double, double* %d, i64 %indvar
+        %t7 = load double, double* %t6
         %t8 = fmul double %t7, 4.5
         store double %t8, double* %t6
         %indvar.next = sub i64 %indvar, 3
diff --git a/test/CodeGen/X86/masked_gather_scatter.ll b/test/CodeGen/X86/masked_gather_scatter.ll
new file mode 100644
index 000000000000..de16e5ddc06b
--- /dev/null
+++ b/test/CodeGen/X86/masked_gather_scatter.ll
@@ -0,0 +1,142 @@
+; RUN: llc -mtriple=x86_64-apple-darwin  -mcpu=knl < %s | FileCheck %s -check-prefix=KNL
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; KNL-LABEL: test1
+; KNL: kxnorw  %k1, %k1, %k1
+; KNL: vgatherdps      (%rdi,%zmm0,4), %zmm1 {%k1}
+define <16 x float> @test1(float* %base, <16 x i32> %ind) {
+
+  %broadcast.splatinsert = insertelement <16 x float*> undef, float* %base, i32 0
+  %broadcast.splat = shufflevector <16 x float*> %broadcast.splatinsert, <16 x float*> undef, <16 x i32> zeroinitializer
+
+  %sext_ind = sext <16 x i32> %ind to <16 x i64>
+  %gep.random = getelementptr float, <16 x float*> %broadcast.splat, <16 x i64> %sext_ind
+  
+  %res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
+  ret <16 x float>%res
+}
+
+declare <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*>, i32, <16 x i1>, <16 x i32>)
+declare <16 x float> @llvm.masked.gather.v16f32(<16 x float*>, i32, <16 x i1>, <16 x float>)
+declare <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> , i32, <8 x i1> , <8 x i32> )
+  
+; KNL-LABEL: test2
+; KNL: kmovw %esi, %k1
+; KNL: vgatherdps      (%rdi,%zmm0,4), %zmm1 {%k1}
+define <16 x float> @test2(float* %base, <16 x i32> %ind, i16 %mask) {
+
+  %broadcast.splatinsert = insertelement <16 x float*> undef, float* %base, i32 0
+  %broadcast.splat = shufflevector <16 x float*> %broadcast.splatinsert, <16 x float*> undef, <16 x i32> zeroinitializer
+
+  %sext_ind = sext <16 x i32> %ind to <16 x i64>
+  %gep.random = getelementptr float, <16 x float*> %broadcast.splat, <16 x i64> %sext_ind
+  %imask = bitcast i16 %mask to <16 x i1>
+  %res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> %imask, <16 x float>undef)
+  ret <16 x float> %res
+}
+
+; KNL-LABEL: test3
+; KNL: kmovw %esi, %k1
+; KNL: vpgatherdd      (%rdi,%zmm0,4), %zmm1 {%k1}
+define <16 x i32> @test3(i32* %base, <16 x i32> %ind, i16 %mask) {
+
+  %broadcast.splatinsert = insertelement <16 x i32*> undef, i32* %base, i32 0
+  %broadcast.splat = shufflevector <16 x i32*> %broadcast.splatinsert, <16 x i32*> undef, <16 x i32> zeroinitializer
+
+  %sext_ind = sext <16 x i32> %ind to <16 x i64>
+  %gep.random = getelementptr i32, <16 x i32*> %broadcast.splat, <16 x i64> %sext_ind
+  %imask = bitcast i16 %mask to <16 x i1>
+  %res = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask, <16 x i32>undef)
+  ret <16 x i32> %res
+}
+
+; KNL-LABEL: test4
+; KNL: kmovw %esi, %k1
+; KNL: kmovw
+; KNL: vpgatherdd
+; KNL: vpgatherdd
+
+define <16 x i32> @test4(i32* %base, <16 x i32> %ind, i16 %mask) {
+
+  %broadcast.splatinsert = insertelement <16 x i32*> undef, i32* %base, i32 0
+  %broadcast.splat = shufflevector <16 x i32*> %broadcast.splatinsert, <16 x i32*> undef, <16 x i32> zeroinitializer
+
+  %gep.random = getelementptr i32, <16 x i32*> %broadcast.splat, <16 x i32> %ind
+  %imask = bitcast i16 %mask to <16 x i1>
+  %gt1 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask, <16 x i32>undef)
+  %gt2 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask, <16 x i32>%gt1)
+  %res = add <16 x i32> %gt1, %gt2
+  ret <16 x i32> %res
+}
+
+; KNL-LABEL: test5
+; KNL: kmovw %k1, %k2
+; KNL: vpscatterdd {{.*}}%k2
+; KNL: vpscatterdd {{.*}}%k1
+
+define void @test5(i32* %base, <16 x i32> %ind, i16 %mask, <16 x i32>%val) {
+
+  %broadcast.splatinsert = insertelement <16 x i32*> undef, i32* %base, i32 0
+  %broadcast.splat = shufflevector <16 x i32*> %broadcast.splatinsert, <16 x i32*> undef, <16 x i32> zeroinitializer
+
+  %gep.random = getelementptr i32, <16 x i32*> %broadcast.splat, <16 x i32> %ind
+  %imask = bitcast i16 %mask to <16 x i1>
+  call void @llvm.masked.scatter.v16i32(<16 x i32>%val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
+  call void @llvm.masked.scatter.v16i32(<16 x i32>%val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
+  ret void
+}
+
+declare void @llvm.masked.scatter.v8i32(<8 x i32> , <8 x i32*> , i32 , <8 x i1> )
+declare void @llvm.masked.scatter.v16i32(<16 x i32> , <16 x i32*> , i32 , <16 x i1> )
+
+; KNL-LABEL: test6
+; KNL: kxnorw  %k1, %k1, %k1
+; KNL: kxnorw  %k2, %k2, %k2
+; KNL: vpgatherqd      (,%zmm{{.*}}), %ymm{{.*}} {%k2}
+; KNL: vpscatterqd     %ymm{{.*}}, (,%zmm{{.*}}) {%k1}
+define <8 x i32> @test6(<8 x i32>%a1, <8 x i32*> %ptr) {
+
+  %a = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %ptr, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i32> undef)
+
+  call void @llvm.masked.scatter.v8i32(<8 x i32> %a1, <8 x i32*> %ptr, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
+  ret <8 x i32>%a
+}
+
+; In this case the index should be promoted to <8 x i64> for KNL
+; KNL-LABEL: test7
+; KNL: vpmovsxdq %ymm0, %zmm0
+; KNL: kmovw   %k1, %k2
+; KNL: vpgatherqd {{.*}} {%k2}
+; KNL: vpgatherqd {{.*}} {%k1}
+define <8 x i32> @test7(i32* %base, <8 x i32> %ind, i8 %mask) {
+
+  %broadcast.splatinsert = insertelement <8 x i32*> undef, i32* %base, i32 0
+  %broadcast.splat = shufflevector <8 x i32*> %broadcast.splatinsert, <8 x i32*> undef, <8 x i32> zeroinitializer
+
+  %gep.random = getelementptr i32, <8 x i32*> %broadcast.splat, <8 x i32> %ind
+  %imask = bitcast i8 %mask to <8 x i1>
+  %gt1 = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.random, i32 4, <8 x i1> %imask, <8 x i32>undef)
+  %gt2 = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.random, i32 4, <8 x i1> %imask, <8 x i32>%gt1)
+  %res = add <8 x i32> %gt1, %gt2
+  ret <8 x i32> %res
+}
+
+; No uniform base in this case, index <8 x i64> contains addresses,
+; each gather call will be split into two
+; KNL-LABEL: test8
+; KNL: kshiftrw        $8, %k1, %k2
+; KNL: vpgatherqd
+; KNL: vpgatherqd
+; KNL: vinserti64x4
+; KNL: vpgatherqd
+; KNL: vpgatherqd
+; KNL: vinserti64x4
+define <16 x i32> @test8(<16 x i32*> %ptr.random, <16 x i32> %ind, i16 %mask) {
+  %imask = bitcast i16 %mask to <16 x i1>
+  %gt1 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %ptr.random, i32 4, <16 x i1> %imask, <16 x i32>undef)
+  %gt2 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %ptr.random, i32 4, <16 x i1> %imask, <16 x i32>%gt1)
+  %res = add <16 x i32> %gt1, %gt2
+  ret <16 x i32> %res
+}
diff --git a/test/CodeGen/X86/masked_memop.ll b/test/CodeGen/X86/masked_memop.ll
index b5ff630f497a..6c16e634a59f 100644
--- a/test/CodeGen/X86/masked_memop.ll
+++ b/test/CodeGen/X86/masked_memop.ll
@@ -1,13 +1,14 @@
 ; RUN: llc -mtriple=x86_64-apple-darwin  -mcpu=knl < %s | FileCheck %s -check-prefix=AVX512
 ; RUN: llc -mtriple=x86_64-apple-darwin  -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX2
 ; RUN: opt -mtriple=x86_64-apple-darwin -codegenprepare -mcpu=corei7-avx -S < %s | FileCheck %s -check-prefix=AVX_SCALAR
+; RUN: llc -mtriple=x86_64-apple-darwin  -mcpu=skx < %s | FileCheck %s -check-prefix=SKX
 
 ; AVX512-LABEL: test1
 ; AVX512: vmovdqu32       (%rdi), %zmm0 {%k1} {z}
 
 ; AVX2-LABEL: test1
-; AVX2: vpmaskmovd      32(%rdi)
-; AVX2: vpmaskmovd      (%rdi)
+; AVX2: vpmaskmovd      {{.*}}(%rdi)
+; AVX2: vpmaskmovd      {{.*}}(%rdi)
 ; AVX2-NOT: blend
 
 ; AVX_SCALAR-LABEL: test1
@@ -82,6 +83,9 @@ define <8 x double> @test5(<8 x i32> %trigger, <8 x double>* %addr, <8 x double>
 ; AVX2-LABEL: test6
 ; AVX2: vmaskmovpd
 ; AVX2: vblendvpd
+
+; SKX-LABEL: test6
+; SKX: vmovupd {{.*}}{%k1}
 define <2 x double> @test6(<2 x i64> %trigger, <2 x double>* %addr, <2 x double> %dst) {
   %mask = icmp eq <2 x i64> %trigger, zeroinitializer
   %res = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %addr, i32 4, <2 x i1>%mask, <2 x double>%dst)
@@ -91,6 +95,9 @@ define <2 x double> @test6(<2 x i64> %trigger, <2 x double>* %addr, <2 x double>
 ; AVX2-LABEL: test7
 ; AVX2: vmaskmovps      {{.*}}(%rdi)
 ; AVX2: blend
+
+; SKX-LABEL: test7
+; SKX: vmovups (%rdi){{.*}}{%k1}
 define <4 x float> @test7(<4 x i32> %trigger, <4 x float>* %addr, <4 x float> %dst) {
   %mask = icmp eq <4 x i32> %trigger, zeroinitializer
   %res = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %addr, i32 4, <4 x i1>%mask, <4 x float>%dst)
@@ -100,6 +107,9 @@ define <4 x float> @test7(<4 x i32> %trigger, <4 x float>* %addr, <4 x float> %d
 ; AVX2-LABEL: test8
 ; AVX2: vpmaskmovd      {{.*}}(%rdi)
 ; AVX2: blend
+
+; SKX-LABEL: test8
+; SKX: vmovdqu32 (%rdi){{.*}}{%k1}
 define <4 x i32> @test8(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %dst) {
   %mask = icmp eq <4 x i32> %trigger, zeroinitializer
   %res = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %addr, i32 4, <4 x i1>%mask, <4 x i32>%dst)
@@ -108,6 +118,9 @@ define <4 x i32> @test8(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %dst) {
 
 ; AVX2-LABEL: test9
 ; AVX2: vpmaskmovd %xmm
+
+; SKX-LABEL: test9
+; SKX: vmovdqu32 %xmm{{.*}}{%k1}
 define void @test9(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %val) {
   %mask = icmp eq <4 x i32> %trigger, zeroinitializer
   call void @llvm.masked.store.v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1>%mask)
@@ -117,23 +130,32 @@ define void @test9(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %val) {
 ; AVX2-LABEL: test10
 ; AVX2: vmaskmovpd    (%rdi), %ymm
 ; AVX2: blend
+
+; SKX-LABEL: test10
+; SKX: vmovapd {{.*}}{%k1}
 define <4 x double> @test10(<4 x i32> %trigger, <4 x double>* %addr, <4 x double> %dst) {
   %mask = icmp eq <4 x i32> %trigger, zeroinitializer
-  %res = call <4 x double> @llvm.masked.load.v4f64(<4 x double>* %addr, i32 4, <4 x i1>%mask, <4 x double>%dst)
+  %res = call <4 x double> @llvm.masked.load.v4f64(<4 x double>* %addr, i32 32, <4 x i1>%mask, <4 x double>%dst)
   ret <4 x double> %res
 }
 
 ; AVX2-LABEL: test11
 ; AVX2: vmaskmovps
 ; AVX2: vblendvps
+
+; SKX-LABEL: test11
+; SKX: vmovaps {{.*}}{%k1}
 define <8 x float> @test11(<8 x i32> %trigger, <8 x float>* %addr, <8 x float> %dst) {
   %mask = icmp eq <8 x i32> %trigger, zeroinitializer
-  %res = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 4, <8 x i1>%mask, <8 x float>%dst)
+  %res = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 32, <8 x i1>%mask, <8 x float>%dst)
   ret <8 x float> %res
 }
 
 ; AVX2-LABEL: test12
 ; AVX2: vpmaskmovd %ymm
+
+; SKX-LABEL: test12
+; SKX: vmovdqu32 {{.*}}{%k1}
 define void @test12(<8 x i32> %trigger, <8 x i32>* %addr, <8 x i32> %val) {
   %mask = icmp eq <8 x i32> %trigger, zeroinitializer
   call void @llvm.masked.store.v8i32(<8 x i32>%val, <8 x i32>* %addr, i32 4, <8 x i1>%mask)
@@ -150,8 +172,15 @@ define void @test13(<16 x i32> %trigger, <16 x float>* %addr, <16 x float> %val)
 }
 
 ; AVX2-LABEL: test14
-; AVX2: vinsertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
+; AVX2: vpshufd
+; AVX2: vmovq
 ; AVX2: vmaskmovps
+
+; SKX-LABEL: test14
+; SKX: kshiftl
+; SKX: kshiftr
+; SKX: vmovups {{.*}}{%k1}
+
 define void @test14(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %val) {
   %mask = icmp eq <2 x i32> %trigger, zeroinitializer
   call void @llvm.masked.store.v2f32(<2 x float>%val, <2 x float>* %addr, i32 4, <2 x i1>%mask)
@@ -160,6 +189,11 @@ define void @test14(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %val) {
 
 ; AVX2-LABEL: test15
 ; AVX2: vpmaskmovd
+
+; SKX-LABEL: test15
+; SKX: kshiftl
+; SKX: kshiftr
+; SKX: vmovdqu32 {{.*}}{%k1}
 define void @test15(<2 x i32> %trigger, <2 x i32>* %addr, <2 x i32> %val) {
   %mask = icmp eq <2 x i32> %trigger, zeroinitializer
   call void @llvm.masked.store.v2i32(<2 x i32>%val, <2 x i32>* %addr, i32 4, <2 x i1>%mask)
@@ -169,6 +203,11 @@ define void @test15(<2 x i32> %trigger, <2 x i32>* %addr, <2 x i32> %val) {
 ; AVX2-LABEL: test16
 ; AVX2: vmaskmovps
 ; AVX2: vblendvps
+
+; SKX-LABEL: test16
+; SKX: kshiftl
+; SKX: kshiftr
+; SKX: vmovups {{.*}}{%k1}
 define <2 x float> @test16(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %dst) {
   %mask = icmp eq <2 x i32> %trigger, zeroinitializer
   %res = call <2 x float> @llvm.masked.load.v2f32(<2 x float>* %addr, i32 4, <2 x i1>%mask, <2 x float>%dst)
@@ -179,6 +218,11 @@ define <2 x float> @test16(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %
 ; AVX2: vpmaskmovd
 ; AVX2: vblendvps
 ; AVX2: vpmovsxdq
+
+; SKX-LABEL: test17
+; SKX: kshiftl
+; SKX: kshiftr
+; SKX: vmovdqu32 {{.*}}{%k1}
 define <2 x i32> @test17(<2 x i32> %trigger, <2 x i32>* %addr, <2 x i32> %dst) {
   %mask = icmp eq <2 x i32> %trigger, zeroinitializer
   %res = call <2 x i32> @llvm.masked.load.v2i32(<2 x i32>* %addr, i32 4, <2 x i1>%mask, <2 x i32>%dst)
diff --git a/test/CodeGen/X86/mcinst-lowering.ll b/test/CodeGen/X86/mcinst-lowering.ll
index a82cfc431ba4..51b2895f1c78 100644
--- a/test/CodeGen/X86/mcinst-lowering.ll
+++ b/test/CodeGen/X86/mcinst-lowering.ll
@@ -5,7 +5,7 @@ target triple = "x86_64-apple-darwin10.0.0"
 
 define i32 @f0(i32* nocapture %x) nounwind readonly ssp {
 entry:
-  %tmp1 = load i32* %x                            ; <i32> [#uses=2]
+  %tmp1 = load i32, i32* %x                            ; <i32> [#uses=2]
   %tobool = icmp eq i32 %tmp1, 0                  ; <i1> [#uses=1]
   br i1 %tobool, label %if.end, label %return
 
diff --git a/test/CodeGen/X86/mem-intrin-base-reg.ll b/test/CodeGen/X86/mem-intrin-base-reg.ll
index 9a6de3dd1d92..9bace29e185f 100644
--- a/test/CodeGen/X86/mem-intrin-base-reg.ll
+++ b/test/CodeGen/X86/mem-intrin-base-reg.ll
@@ -24,9 +24,9 @@ no_vectors:
   ret i32 0
 
 spill_vectors:
-  %vp1 = getelementptr <4 x i32>* %vp0, i32 1
-  %v0 = load <4 x i32>* %vp0
-  %v1 = load <4 x i32>* %vp1
+  %vp1 = getelementptr <4 x i32>, <4 x i32>* %vp0, i32 1
+  %v0 = load <4 x i32>, <4 x i32>* %vp0
+  %v1 = load <4 x i32>, <4 x i32>* %vp1
   %vicmp = icmp slt <4 x i32> %v0, %v1
   %icmp = extractelement <4 x i1> %vicmp, i32 0
   call void @escape_vla_and_icmp(i8* null, i1 zeroext %icmp)
@@ -49,9 +49,9 @@ no_vectors:
   ret i32 0
 
 spill_vectors:
-  %vp1 = getelementptr <4 x i32>* %vp0, i32 1
-  %v0 = load <4 x i32>* %vp0
-  %v1 = load <4 x i32>* %vp1
+  %vp1 = getelementptr <4 x i32>, <4 x i32>* %vp0, i32 1
+  %v0 = load <4 x i32>, <4 x i32>* %vp0
+  %v1 = load <4 x i32>, <4 x i32>* %vp1
   %vicmp = icmp slt <4 x i32> %v0, %v1
   %icmp = extractelement <4 x i1> %vicmp, i32 0
   %vla = alloca i8, i32 %n
@@ -77,9 +77,9 @@ no_vectors:
   ret i32 0
 
 spill_vectors:
-  %vp1 = getelementptr <4 x i32>* %vp0, i32 1
-  %v0 = load <4 x i32>* %vp0
-  %v1 = load <4 x i32>* %vp1
+  %vp1 = getelementptr <4 x i32>, <4 x i32>* %vp0, i32 1
+  %v0 = load <4 x i32>, <4 x i32>* %vp0
+  %v1 = load <4 x i32>, <4 x i32>* %vp1
   %vicmp = icmp slt <4 x i32> %v0, %v1
   %icmp = extractelement <4 x i1> %vicmp, i32 0
   %vla = alloca i8, i32 %n
diff --git a/test/CodeGen/X86/mem-promote-integers.ll b/test/CodeGen/X86/mem-promote-integers.ll
index ea38b95a864e..3023cf2e900e 100644
--- a/test/CodeGen/X86/mem-promote-integers.ll
+++ b/test/CodeGen/X86/mem-promote-integers.ll
@@ -5,7 +5,7 @@
 ; RUN: llc -march=x86-64 < %s > /dev/null
 
 define <1 x i8> @test_1xi8(<1 x i8> %x, <1 x i8>* %b) {
-  %bb = load <1 x i8>* %b
+  %bb = load <1 x i8>, <1 x i8>* %b
   %tt = xor <1 x i8> %x, %bb
   store <1 x i8> %tt, <1 x i8>* %b
   br label %next
@@ -16,7 +16,7 @@ next:
 
 
 define <1 x i16> @test_1xi16(<1 x i16> %x, <1 x i16>* %b) {
-  %bb = load <1 x i16>* %b
+  %bb = load <1 x i16>, <1 x i16>* %b
   %tt = xor <1 x i16> %x, %bb
   store <1 x i16> %tt, <1 x i16>* %b
   br label %next
@@ -27,7 +27,7 @@ next:
 
 
 define <1 x i32> @test_1xi32(<1 x i32> %x, <1 x i32>* %b) {
-  %bb = load <1 x i32>* %b
+  %bb = load <1 x i32>, <1 x i32>* %b
   %tt = xor <1 x i32> %x, %bb
   store <1 x i32> %tt, <1 x i32>* %b
   br label %next
@@ -38,7 +38,7 @@ next:
 
 
 define <1 x i64> @test_1xi64(<1 x i64> %x, <1 x i64>* %b) {
-  %bb = load <1 x i64>* %b
+  %bb = load <1 x i64>, <1 x i64>* %b
   %tt = xor <1 x i64> %x, %bb
   store <1 x i64> %tt, <1 x i64>* %b
   br label %next
@@ -49,7 +49,7 @@ next:
 
 
 define <1 x i128> @test_1xi128(<1 x i128> %x, <1 x i128>* %b) {
-  %bb = load <1 x i128>* %b
+  %bb = load <1 x i128>, <1 x i128>* %b
   %tt = xor <1 x i128> %x, %bb
   store <1 x i128> %tt, <1 x i128>* %b
   br label %next
@@ -60,7 +60,7 @@ next:
 
 
 define <1 x i256> @test_1xi256(<1 x i256> %x, <1 x i256>* %b) {
-  %bb = load <1 x i256>* %b
+  %bb = load <1 x i256>, <1 x i256>* %b
   %tt = xor <1 x i256> %x, %bb
   store <1 x i256> %tt, <1 x i256>* %b
   br label %next
@@ -71,7 +71,7 @@ next:
 
 
 define <1 x i512> @test_1xi512(<1 x i512> %x, <1 x i512>* %b) {
-  %bb = load <1 x i512>* %b
+  %bb = load <1 x i512>, <1 x i512>* %b
   %tt = xor <1 x i512> %x, %bb
   store <1 x i512> %tt, <1 x i512>* %b
   br label %next
@@ -82,7 +82,7 @@ next:
 
 
 define <2 x i8> @test_2xi8(<2 x i8> %x, <2 x i8>* %b) {
-  %bb = load <2 x i8>* %b
+  %bb = load <2 x i8>, <2 x i8>* %b
   %tt = xor <2 x i8> %x, %bb
   store <2 x i8> %tt, <2 x i8>* %b
   br label %next
@@ -93,7 +93,7 @@ next:
 
 
 define <2 x i16> @test_2xi16(<2 x i16> %x, <2 x i16>* %b) {
-  %bb = load <2 x i16>* %b
+  %bb = load <2 x i16>, <2 x i16>* %b
   %tt = xor <2 x i16> %x, %bb
   store <2 x i16> %tt, <2 x i16>* %b
   br label %next
@@ -104,7 +104,7 @@ next:
 
 
 define <2 x i32> @test_2xi32(<2 x i32> %x, <2 x i32>* %b) {
-  %bb = load <2 x i32>* %b
+  %bb = load <2 x i32>, <2 x i32>* %b
   %tt = xor <2 x i32> %x, %bb
   store <2 x i32> %tt, <2 x i32>* %b
   br label %next
@@ -115,7 +115,7 @@ next:
 
 
 define <2 x i64> @test_2xi64(<2 x i64> %x, <2 x i64>* %b) {
-  %bb = load <2 x i64>* %b
+  %bb = load <2 x i64>, <2 x i64>* %b
   %tt = xor <2 x i64> %x, %bb
   store <2 x i64> %tt, <2 x i64>* %b
   br label %next
@@ -126,7 +126,7 @@ next:
 
 
 define <2 x i128> @test_2xi128(<2 x i128> %x, <2 x i128>* %b) {
-  %bb = load <2 x i128>* %b
+  %bb = load <2 x i128>, <2 x i128>* %b
   %tt = xor <2 x i128> %x, %bb
   store <2 x i128> %tt, <2 x i128>* %b
   br label %next
@@ -137,7 +137,7 @@ next:
 
 
 define <2 x i256> @test_2xi256(<2 x i256> %x, <2 x i256>* %b) {
-  %bb = load <2 x i256>* %b
+  %bb = load <2 x i256>, <2 x i256>* %b
   %tt = xor <2 x i256> %x, %bb
   store <2 x i256> %tt, <2 x i256>* %b
   br label %next
@@ -148,7 +148,7 @@ next:
 
 
 define <2 x i512> @test_2xi512(<2 x i512> %x, <2 x i512>* %b) {
-  %bb = load <2 x i512>* %b
+  %bb = load <2 x i512>, <2 x i512>* %b
   %tt = xor <2 x i512> %x, %bb
   store <2 x i512> %tt, <2 x i512>* %b
   br label %next
@@ -159,7 +159,7 @@ next:
 
 
 define <3 x i8> @test_3xi8(<3 x i8> %x, <3 x i8>* %b) {
-  %bb = load <3 x i8>* %b
+  %bb = load <3 x i8>, <3 x i8>* %b
   %tt = xor <3 x i8> %x, %bb
   store <3 x i8> %tt, <3 x i8>* %b
   br label %next
@@ -170,7 +170,7 @@ next:
 
 
 define <3 x i16> @test_3xi16(<3 x i16> %x, <3 x i16>* %b) {
-  %bb = load <3 x i16>* %b
+  %bb = load <3 x i16>, <3 x i16>* %b
   %tt = xor <3 x i16> %x, %bb
   store <3 x i16> %tt, <3 x i16>* %b
   br label %next
@@ -181,7 +181,7 @@ next:
 
 
 define <3 x i32> @test_3xi32(<3 x i32> %x, <3 x i32>* %b) {
-  %bb = load <3 x i32>* %b
+  %bb = load <3 x i32>, <3 x i32>* %b
   %tt = xor <3 x i32> %x, %bb
   store <3 x i32> %tt, <3 x i32>* %b
   br label %next
@@ -192,7 +192,7 @@ next:
 
 
 define <3 x i64> @test_3xi64(<3 x i64> %x, <3 x i64>* %b) {
-  %bb = load <3 x i64>* %b
+  %bb = load <3 x i64>, <3 x i64>* %b
   %tt = xor <3 x i64> %x, %bb
   store <3 x i64> %tt, <3 x i64>* %b
   br label %next
@@ -203,7 +203,7 @@ next:
 
 
 define <3 x i128> @test_3xi128(<3 x i128> %x, <3 x i128>* %b) {
-  %bb = load <3 x i128>* %b
+  %bb = load <3 x i128>, <3 x i128>* %b
   %tt = xor <3 x i128> %x, %bb
   store <3 x i128> %tt, <3 x i128>* %b
   br label %next
@@ -214,7 +214,7 @@ next:
 
 
 define <3 x i256> @test_3xi256(<3 x i256> %x, <3 x i256>* %b) {
-  %bb = load <3 x i256>* %b
+  %bb = load <3 x i256>, <3 x i256>* %b
   %tt = xor <3 x i256> %x, %bb
   store <3 x i256> %tt, <3 x i256>* %b
   br label %next
@@ -225,7 +225,7 @@ next:
 
 
 define <3 x i512> @test_3xi512(<3 x i512> %x, <3 x i512>* %b) {
-  %bb = load <3 x i512>* %b
+  %bb = load <3 x i512>, <3 x i512>* %b
   %tt = xor <3 x i512> %x, %bb
   store <3 x i512> %tt, <3 x i512>* %b
   br label %next
@@ -236,7 +236,7 @@ next:
 
 
 define <4 x i8> @test_4xi8(<4 x i8> %x, <4 x i8>* %b) {
-  %bb = load <4 x i8>* %b
+  %bb = load <4 x i8>, <4 x i8>* %b
   %tt = xor <4 x i8> %x, %bb
   store <4 x i8> %tt, <4 x i8>* %b
   br label %next
@@ -247,7 +247,7 @@ next:
 
 
 define <4 x i16> @test_4xi16(<4 x i16> %x, <4 x i16>* %b) {
-  %bb = load <4 x i16>* %b
+  %bb = load <4 x i16>, <4 x i16>* %b
   %tt = xor <4 x i16> %x, %bb
   store <4 x i16> %tt, <4 x i16>* %b
   br label %next
@@ -258,7 +258,7 @@ next:
 
 
 define <4 x i32> @test_4xi32(<4 x i32> %x, <4 x i32>* %b) {
-  %bb = load <4 x i32>* %b
+  %bb = load <4 x i32>, <4 x i32>* %b
   %tt = xor <4 x i32> %x, %bb
   store <4 x i32> %tt, <4 x i32>* %b
   br label %next
@@ -269,7 +269,7 @@ next:
 
 
 define <4 x i64> @test_4xi64(<4 x i64> %x, <4 x i64>* %b) {
-  %bb = load <4 x i64>* %b
+  %bb = load <4 x i64>, <4 x i64>* %b
   %tt = xor <4 x i64> %x, %bb
   store <4 x i64> %tt, <4 x i64>* %b
   br label %next
@@ -280,7 +280,7 @@ next:
 
 
 define <4 x i128> @test_4xi128(<4 x i128> %x, <4 x i128>* %b) {
-  %bb = load <4 x i128>* %b
+  %bb = load <4 x i128>, <4 x i128>* %b
   %tt = xor <4 x i128> %x, %bb
   store <4 x i128> %tt, <4 x i128>* %b
   br label %next
@@ -291,7 +291,7 @@ next:
 
 
 define <4 x i256> @test_4xi256(<4 x i256> %x, <4 x i256>* %b) {
-  %bb = load <4 x i256>* %b
+  %bb = load <4 x i256>, <4 x i256>* %b
   %tt = xor <4 x i256> %x, %bb
   store <4 x i256> %tt, <4 x i256>* %b
   br label %next
@@ -302,7 +302,7 @@ next:
 
 
 define <4 x i512> @test_4xi512(<4 x i512> %x, <4 x i512>* %b) {
-  %bb = load <4 x i512>* %b
+  %bb = load <4 x i512>, <4 x i512>* %b
   %tt = xor <4 x i512> %x, %bb
   store <4 x i512> %tt, <4 x i512>* %b
   br label %next
@@ -313,7 +313,7 @@ next:
 
 
 define <5 x i8> @test_5xi8(<5 x i8> %x, <5 x i8>* %b) {
-  %bb = load <5 x i8>* %b
+  %bb = load <5 x i8>, <5 x i8>* %b
   %tt = xor <5 x i8> %x, %bb
   store <5 x i8> %tt, <5 x i8>* %b
   br label %next
@@ -324,7 +324,7 @@ next:
 
 
 define <5 x i16> @test_5xi16(<5 x i16> %x, <5 x i16>* %b) {
-  %bb = load <5 x i16>* %b
+  %bb = load <5 x i16>, <5 x i16>* %b
   %tt = xor <5 x i16> %x, %bb
   store <5 x i16> %tt, <5 x i16>* %b
   br label %next
@@ -335,7 +335,7 @@ next:
 
 
 define <5 x i32> @test_5xi32(<5 x i32> %x, <5 x i32>* %b) {
-  %bb = load <5 x i32>* %b
+  %bb = load <5 x i32>, <5 x i32>* %b
   %tt = xor <5 x i32> %x, %bb
   store <5 x i32> %tt, <5 x i32>* %b
   br label %next
@@ -346,7 +346,7 @@ next:
 
 
 define <5 x i64> @test_5xi64(<5 x i64> %x, <5 x i64>* %b) {
-  %bb = load <5 x i64>* %b
+  %bb = load <5 x i64>, <5 x i64>* %b
   %tt = xor <5 x i64> %x, %bb
   store <5 x i64> %tt, <5 x i64>* %b
   br label %next
@@ -357,7 +357,7 @@ next:
 
 
 define <5 x i128> @test_5xi128(<5 x i128> %x, <5 x i128>* %b) {
-  %bb = load <5 x i128>* %b
+  %bb = load <5 x i128>, <5 x i128>* %b
   %tt = xor <5 x i128> %x, %bb
   store <5 x i128> %tt, <5 x i128>* %b
   br label %next
@@ -368,7 +368,7 @@ next:
 
 
 define <5 x i256> @test_5xi256(<5 x i256> %x, <5 x i256>* %b) {
-  %bb = load <5 x i256>* %b
+  %bb = load <5 x i256>, <5 x i256>* %b
   %tt = xor <5 x i256> %x, %bb
   store <5 x i256> %tt, <5 x i256>* %b
   br label %next
@@ -379,7 +379,7 @@ next:
 
 
 define <5 x i512> @test_5xi512(<5 x i512> %x, <5 x i512>* %b) {
-  %bb = load <5 x i512>* %b
+  %bb = load <5 x i512>, <5 x i512>* %b
   %tt = xor <5 x i512> %x, %bb
   store <5 x i512> %tt, <5 x i512>* %b
   br label %next
diff --git a/test/CodeGen/X86/memcmp.ll b/test/CodeGen/X86/memcmp.ll
index 0a534926c6cd..e5f1f526b467 100644
--- a/test/CodeGen/X86/memcmp.ll
+++ b/test/CodeGen/X86/memcmp.ll
@@ -11,7 +11,7 @@ declare i32 @memcmp(...)
 
 define void @memcmp2(i8* %X, i8* %Y, i32* nocapture %P) nounwind {
 entry:
-  %0 = tail call i32 (...)* @memcmp(i8* %X, i8* %Y, i32 2) nounwind ; <i32> [#uses=1]
+  %0 = tail call i32 (...) @memcmp(i8* %X, i8* %Y, i32 2) nounwind ; <i32> [#uses=1]
   %1 = icmp eq i32 %0, 0                          ; <i1> [#uses=1]
   br i1 %1, label %return, label %bb
 
@@ -31,7 +31,7 @@ return:                                           ; preds = %entry
 
 define void @memcmp2a(i8* %X, i32* nocapture %P) nounwind {
 entry:
-  %0 = tail call i32 (...)* @memcmp(i8* %X, i8* getelementptr inbounds ([23 x i8]* @.str, i32 0, i32 1), i32 2) nounwind ; <i32> [#uses=1]
+  %0 = tail call i32 (...) @memcmp(i8* %X, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @.str, i32 0, i32 1), i32 2) nounwind ; <i32> [#uses=1]
   %1 = icmp eq i32 %0, 0                          ; <i1> [#uses=1]
   br i1 %1, label %return, label %bb
 
@@ -49,7 +49,7 @@ return:                                           ; preds = %entry
 
 define void @memcmp4(i8* %X, i8* %Y, i32* nocapture %P) nounwind {
 entry:
-  %0 = tail call i32 (...)* @memcmp(i8* %X, i8* %Y, i32 4) nounwind ; <i32> [#uses=1]
+  %0 = tail call i32 (...) @memcmp(i8* %X, i8* %Y, i32 4) nounwind ; <i32> [#uses=1]
   %1 = icmp eq i32 %0, 0                          ; <i1> [#uses=1]
   br i1 %1, label %return, label %bb
 
@@ -66,7 +66,7 @@ return:                                           ; preds = %entry
 
 define void @memcmp4a(i8* %X, i32* nocapture %P) nounwind {
 entry:
-  %0 = tail call i32 (...)* @memcmp(i8* %X, i8* getelementptr inbounds ([23 x i8]* @.str, i32 0, i32 1), i32 4) nounwind ; <i32> [#uses=1]
+  %0 = tail call i32 (...) @memcmp(i8* %X, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @.str, i32 0, i32 1), i32 4) nounwind ; <i32> [#uses=1]
   %1 = icmp eq i32 %0, 0                          ; <i1> [#uses=1]
   br i1 %1, label %return, label %bb
 
@@ -82,7 +82,7 @@ return:                                           ; preds = %entry
 
 define void @memcmp8(i8* %X, i8* %Y, i32* nocapture %P) nounwind {
 entry:
-  %0 = tail call i32 (...)* @memcmp(i8* %X, i8* %Y, i32 8) nounwind ; <i32> [#uses=1]
+  %0 = tail call i32 (...) @memcmp(i8* %X, i8* %Y, i32 8) nounwind ; <i32> [#uses=1]
   %1 = icmp eq i32 %0, 0                          ; <i1> [#uses=1]
   br i1 %1, label %return, label %bb
 
@@ -99,7 +99,7 @@ return:                                           ; preds = %entry
 
 define void @memcmp8a(i8* %X, i32* nocapture %P) nounwind {
 entry:
-  %0 = tail call i32 (...)* @memcmp(i8* %X, i8* getelementptr inbounds ([23 x i8]* @.str, i32 0, i32 0), i32 8) nounwind ; <i32> [#uses=1]
+  %0 = tail call i32 (...) @memcmp(i8* %X, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @.str, i32 0, i32 0), i32 8) nounwind ; <i32> [#uses=1]
   %1 = icmp eq i32 %0, 0                          ; <i1> [#uses=1]
   br i1 %1, label %return, label %bb
 
diff --git a/test/CodeGen/X86/memcpy-2.ll b/test/CodeGen/X86/memcpy-2.ll
index 6ae7807810e9..0111c0d433f1 100644
--- a/test/CodeGen/X86/memcpy-2.ll
+++ b/test/CodeGen/X86/memcpy-2.ll
@@ -46,7 +46,7 @@ entry:
 ; X86-64: movq $0
   %tmp1 = alloca [25 x i8]
   %tmp2 = bitcast [25 x i8]* %tmp1 to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp2, i8* getelementptr inbounds ([25 x i8]* @.str, i32 0, i32 0), i32 25, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp2, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i32 25, i32 1, i1 false)
   unreachable
 }
 
@@ -188,7 +188,7 @@ entry:
 ; X86-64: movl $2021161080
   %tmp1 = alloca [30 x i8]
   %tmp2 = bitcast [30 x i8]* %tmp1 to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp2, i8* getelementptr inbounds ([30 x i8]* @.str2, i32 0, i32 0), i32 30, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp2, i8* getelementptr inbounds ([30 x i8], [30 x i8]* @.str2, i32 0, i32 0), i32 30, i32 1, i1 false)
   unreachable
 }
 
diff --git a/test/CodeGen/X86/memcpy.ll b/test/CodeGen/X86/memcpy.ll
index 88b6cfd2295f..f582571252b5 100644
--- a/test/CodeGen/X86/memcpy.ll
+++ b/test/CodeGen/X86/memcpy.ll
@@ -84,7 +84,7 @@ entry:
 
 define void @test5(i8* nocapture %C) nounwind uwtable ssp {
 entry:
-  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([30 x i8]* @.str, i64 0, i64 0), i64 16, i32 1, i1 false)
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([30 x i8], [30 x i8]* @.str, i64 0, i64 0), i64 16, i32 1, i1 false)
   ret void
 
 ; DARWIN-LABEL: test5:
@@ -101,7 +101,7 @@ entry:
 ; DARWIN: test6
 ; DARWIN: movw $0, 8
 ; DARWIN: movq $120, 0
-  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* null, i8* getelementptr inbounds ([2 x i8]* @.str2, i64 0, i64 0), i64 10, i32 1, i1 false)
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* null, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str2, i64 0, i64 0), i64 10, i32 1, i1 false)
   ret void
 }
 
diff --git a/test/CodeGen/X86/memset-3.ll b/test/CodeGen/X86/memset-3.ll
index 29febfab29af..455e6756013f 100644
--- a/test/CodeGen/X86/memset-3.ll
+++ b/test/CodeGen/X86/memset-3.ll
@@ -4,7 +4,7 @@
 define void @t() nounwind ssp {
 entry:
   %buf = alloca [512 x i8], align 1
-  %ptr = getelementptr inbounds [512 x i8]* %buf, i32 0, i32 0
+  %ptr = getelementptr inbounds [512 x i8], [512 x i8]* %buf, i32 0, i32 0
   call void @llvm.memset.p0i8.i32(i8* %ptr, i8 undef, i32 512, i32 1, i1 false)
   unreachable
 }
diff --git a/test/CodeGen/X86/memset.ll b/test/CodeGen/X86/memset.ll
index 0d479f0abe7b..96a22e885675 100644
--- a/test/CodeGen/X86/memset.ll
+++ b/test/CodeGen/X86/memset.ll
@@ -7,7 +7,7 @@
 define void @t() nounwind  {
 entry:
 	%up_mvd = alloca [8 x %struct.x]		; <[8 x %struct.x]*> [#uses=2]
-	%up_mvd116 = getelementptr [8 x %struct.x]* %up_mvd, i32 0, i32 0		; <%struct.x*> [#uses=1]
+	%up_mvd116 = getelementptr [8 x %struct.x], [8 x %struct.x]* %up_mvd, i32 0, i32 0		; <%struct.x*> [#uses=1]
 	%tmp110117 = bitcast [8 x %struct.x]* %up_mvd to i8*		; <i8*> [#uses=1]
 
 	call void @llvm.memset.p0i8.i64(i8* %tmp110117, i8 0, i64 32, i32 8, i1 false)
diff --git a/test/CodeGen/X86/merge-consecutive-stores-i1.ll b/test/CodeGen/X86/merge-consecutive-stores-i1.ll
new file mode 100644
index 000000000000..a7f5c2142271
--- /dev/null
+++ b/test/CodeGen/X86/merge-consecutive-stores-i1.ll
@@ -0,0 +1,15 @@
+; RUN: llc  -march=x86-64 < %s
+
+; Ensure that MergeConsecutiveStores doesn't crash when dealing with
+; i1 operands.
+
+%struct.X = type { i1, i1 }
+
+@b = common global %struct.X zeroinitializer, align 4
+
+define void @foo() {
+entry:
+  store i1 0, i1* getelementptr inbounds (%struct.X, %struct.X* @b, i64 0, i32 0), align 4
+  store i1 0, i1* getelementptr inbounds (%struct.X, %struct.X* @b, i64 0, i32 1), align 1
+  ret void
+}
diff --git a/test/CodeGen/X86/merge_store.ll b/test/CodeGen/X86/merge_store.ll
index f98963d8e90e..2701f369bcde 100644
--- a/test/CodeGen/X86/merge_store.ll
+++ b/test/CodeGen/X86/merge_store.ll
@@ -10,16 +10,16 @@ entry:
 
   for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
   store i32 1, i32* %arrayidx, align 4
   %0 = or i64 %indvars.iv, 1
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %0
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %0
   store i32 1, i32* %arrayidx2, align 4
   %1 = or i64 %indvars.iv, 2
-  %arrayidx5 = getelementptr inbounds i32* %a, i64 %1
+  %arrayidx5 = getelementptr inbounds i32, i32* %a, i64 %1
   store i32 1, i32* %arrayidx5, align 4
   %2 = or i64 %indvars.iv, 3
-  %arrayidx8 = getelementptr inbounds i32* %a, i64 %2
+  %arrayidx8 = getelementptr inbounds i32, i32* %a, i64 %2
   store i32 1, i32* %arrayidx8, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 4
   %3 = trunc i64 %indvars.iv.next to i32
diff --git a/test/CodeGen/X86/mingw-alloca.ll b/test/CodeGen/X86/mingw-alloca.ll
index 72b69400ffa1..cbad4fbfa2ea 100644
--- a/test/CodeGen/X86/mingw-alloca.ll
+++ b/test/CodeGen/X86/mingw-alloca.ll
@@ -29,7 +29,7 @@ entry:
 ; ELF: calll _alloca
 ; ELF: movl	8028(%esp), %eax
 	%A2 = alloca [2000 x i32], align 16		; <[2000 x i32]*> [#uses=1]
-	%A2.sub = getelementptr [2000 x i32]* %A2, i32 0, i32 0		; <i32*> [#uses=1]
+	%A2.sub = getelementptr [2000 x i32], [2000 x i32]* %A2, i32 0, i32 0		; <i32*> [#uses=1]
 	call void @bar2( i32* %A2.sub, i32 %N )
 	ret void
 }
diff --git a/test/CodeGen/X86/misaligned-memset.ll b/test/CodeGen/X86/misaligned-memset.ll
index 21f8bf2bf29e..ef8e0e81ad77 100644
--- a/test/CodeGen/X86/misaligned-memset.ll
+++ b/test/CodeGen/X86/misaligned-memset.ll
@@ -7,8 +7,8 @@ define i32 @main() nounwind ssp {
 entry:
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
-  call void @llvm.memset.p0i8.i64(i8* bitcast (i64* getelementptr inbounds ([3 x i64]* @a, i32 0, i64 1) to i8*), i8 0, i64 16, i32 1, i1 false)
-  %0 = load i32* %retval
+  call void @llvm.memset.p0i8.i64(i8* bitcast (i64* getelementptr inbounds ([3 x i64], [3 x i64]* @a, i32 0, i64 1) to i8*), i8 0, i64 16, i32 1, i1 false)
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
diff --git a/test/CodeGen/X86/misched-aa-colored.ll b/test/CodeGen/X86/misched-aa-colored.ll
index 52a5e5d25d11..ef7b98ac9c69 100644
--- a/test/CodeGen/X86/misched-aa-colored.ll
+++ b/test/CodeGen/X86/misched-aa-colored.ll
@@ -155,13 +155,13 @@ entry:
   %ref.tmp.i = alloca %"struct.std::pair.112.119.719.1079.2039.2159.2399.4199", align 8
   %Op.i = alloca %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083", align 8
   %0 = bitcast %"struct.std::pair.112.119.719.1079.2039.2159.2399.4199"* %ref.tmp.i to i8*
-  %retval.sroa.0.0.idx.i36 = getelementptr inbounds %"struct.std::pair.112.119.719.1079.2039.2159.2399.4199"* %ref.tmp.i, i64 0, i32 1, i32 0, i32 0
-  %retval.sroa.0.0.copyload.i37 = load i32* %retval.sroa.0.0.idx.i36, align 8
+  %retval.sroa.0.0.idx.i36 = getelementptr inbounds %"struct.std::pair.112.119.719.1079.2039.2159.2399.4199", %"struct.std::pair.112.119.719.1079.2039.2159.2399.4199"* %ref.tmp.i, i64 0, i32 1, i32 0, i32 0
+  %retval.sroa.0.0.copyload.i37 = load i32, i32* %retval.sroa.0.0.idx.i36, align 8
   call void @llvm.lifetime.end(i64 24, i8* %0) #1
-  %agg.tmp8.sroa.2.0.copyload = load i32* undef, align 8
+  %agg.tmp8.sroa.2.0.copyload = load i32, i32* undef, align 8
   %1 = bitcast %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* %Op.i to i8*
   call void @llvm.lifetime.start(i64 16, i8* %1) #1
-  %2 = getelementptr %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* %Op.i, i64 0, i32 1
+  %2 = getelementptr %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083", %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* %Op.i, i64 0, i32 1
   store i32 %agg.tmp8.sroa.2.0.copyload, i32* %2, align 8
 
 ; CHECK: movl	(%rax), %eax
diff --git a/test/CodeGen/X86/misched-aa-mmos.ll b/test/CodeGen/X86/misched-aa-mmos.ll
index 343e26f54725..c457a5eb4130 100644
--- a/test/CodeGen/X86/misched-aa-mmos.ll
+++ b/test/CodeGen/X86/misched-aa-mmos.ll
@@ -18,13 +18,13 @@ entry:
   br i1 undef, label %if.else56, label %cond.end.i
 
 cond.end.i:
-  %significand.i18.i = getelementptr inbounds %c1* %temp_rhs, i64 0, i32 1
-  %exponent.i = getelementptr inbounds %c1* %temp_rhs, i64 0, i32 2
-  %0 = load i16* %exponent.i, align 8
+  %significand.i18.i = getelementptr inbounds %c1, %c1* %temp_rhs, i64 0, i32 1
+  %exponent.i = getelementptr inbounds %c1, %c1* %temp_rhs, i64 0, i32 2
+  %0 = load i16, i16* %exponent.i, align 8
   %sub.i = add i16 %0, -1
   store i16 %sub.i, i16* %exponent.i, align 8
   %parts.i.i = bitcast %u1* %significand.i18.i to i64**
-  %1 = load i64** %parts.i.i, align 8
+  %1 = load i64*, i64** %parts.i.i, align 8
   %call5.i = call zeroext i1 @bar(i64* %1, i32 undef) #1
   unreachable
 
diff --git a/test/CodeGen/X86/misched-balance.ll b/test/CodeGen/X86/misched-balance.ll
index 1900802ac9b3..ca3b57992a2e 100644
--- a/test/CodeGen/X86/misched-balance.ll
+++ b/test/CodeGen/X86/misched-balance.ll
@@ -48,65 +48,65 @@ entry:
 ; CHECK-LABEL: %end
 for.body:
   %indvars.iv42.i = phi i64 [ %indvars.iv.next43.i, %for.body ], [ 0, %entry ]
-  %tmp57 = load i32* %tmp56, align 4
-  %arrayidx12.us.i61 = getelementptr inbounds i32* %pre, i64 %indvars.iv42.i
-  %tmp58 = load i32* %arrayidx12.us.i61, align 4
+  %tmp57 = load i32, i32* %tmp56, align 4
+  %arrayidx12.us.i61 = getelementptr inbounds i32, i32* %pre, i64 %indvars.iv42.i
+  %tmp58 = load i32, i32* %arrayidx12.us.i61, align 4
   %mul.us.i = mul nsw i32 %tmp58, %tmp57
-  %arrayidx8.us.i.1 = getelementptr inbounds i32* %tmp56, i64 1
-  %tmp59 = load i32* %arrayidx8.us.i.1, align 4
-  %arrayidx12.us.i61.1 = getelementptr inbounds i32* %pre94, i64 %indvars.iv42.i
-  %tmp60 = load i32* %arrayidx12.us.i61.1, align 4
+  %arrayidx8.us.i.1 = getelementptr inbounds i32, i32* %tmp56, i64 1
+  %tmp59 = load i32, i32* %arrayidx8.us.i.1, align 4
+  %arrayidx12.us.i61.1 = getelementptr inbounds i32, i32* %pre94, i64 %indvars.iv42.i
+  %tmp60 = load i32, i32* %arrayidx12.us.i61.1, align 4
   %mul.us.i.1 = mul nsw i32 %tmp60, %tmp59
   %add.us.i.1 = add nsw i32 %mul.us.i.1, %mul.us.i
-  %arrayidx8.us.i.2 = getelementptr inbounds i32* %tmp56, i64 2
-  %tmp61 = load i32* %arrayidx8.us.i.2, align 4
-  %arrayidx12.us.i61.2 = getelementptr inbounds i32* %pre95, i64 %indvars.iv42.i
-  %tmp62 = load i32* %arrayidx12.us.i61.2, align 4
+  %arrayidx8.us.i.2 = getelementptr inbounds i32, i32* %tmp56, i64 2
+  %tmp61 = load i32, i32* %arrayidx8.us.i.2, align 4
+  %arrayidx12.us.i61.2 = getelementptr inbounds i32, i32* %pre95, i64 %indvars.iv42.i
+  %tmp62 = load i32, i32* %arrayidx12.us.i61.2, align 4
   %mul.us.i.2 = mul nsw i32 %tmp62, %tmp61
   %add.us.i.2 = add nsw i32 %mul.us.i.2, %add.us.i.1
-  %arrayidx8.us.i.3 = getelementptr inbounds i32* %tmp56, i64 3
-  %tmp63 = load i32* %arrayidx8.us.i.3, align 4
-  %arrayidx12.us.i61.3 = getelementptr inbounds i32* %pre96, i64 %indvars.iv42.i
-  %tmp64 = load i32* %arrayidx12.us.i61.3, align 4
+  %arrayidx8.us.i.3 = getelementptr inbounds i32, i32* %tmp56, i64 3
+  %tmp63 = load i32, i32* %arrayidx8.us.i.3, align 4
+  %arrayidx12.us.i61.3 = getelementptr inbounds i32, i32* %pre96, i64 %indvars.iv42.i
+  %tmp64 = load i32, i32* %arrayidx12.us.i61.3, align 4
   %mul.us.i.3 = mul nsw i32 %tmp64, %tmp63
   %add.us.i.3 = add nsw i32 %mul.us.i.3, %add.us.i.2
-  %arrayidx8.us.i.4 = getelementptr inbounds i32* %tmp56, i64 4
-  %tmp65 = load i32* %arrayidx8.us.i.4, align 4
-  %arrayidx12.us.i61.4 = getelementptr inbounds i32* %pre97, i64 %indvars.iv42.i
-  %tmp66 = load i32* %arrayidx12.us.i61.4, align 4
+  %arrayidx8.us.i.4 = getelementptr inbounds i32, i32* %tmp56, i64 4
+  %tmp65 = load i32, i32* %arrayidx8.us.i.4, align 4
+  %arrayidx12.us.i61.4 = getelementptr inbounds i32, i32* %pre97, i64 %indvars.iv42.i
+  %tmp66 = load i32, i32* %arrayidx12.us.i61.4, align 4
   %mul.us.i.4 = mul nsw i32 %tmp66, %tmp65
   %add.us.i.4 = add nsw i32 %mul.us.i.4, %add.us.i.3
-  %arrayidx8.us.i.5 = getelementptr inbounds i32* %tmp56, i64 5
-  %tmp67 = load i32* %arrayidx8.us.i.5, align 4
-  %arrayidx12.us.i61.5 = getelementptr inbounds i32* %pre98, i64 %indvars.iv42.i
-  %tmp68 = load i32* %arrayidx12.us.i61.5, align 4
+  %arrayidx8.us.i.5 = getelementptr inbounds i32, i32* %tmp56, i64 5
+  %tmp67 = load i32, i32* %arrayidx8.us.i.5, align 4
+  %arrayidx12.us.i61.5 = getelementptr inbounds i32, i32* %pre98, i64 %indvars.iv42.i
+  %tmp68 = load i32, i32* %arrayidx12.us.i61.5, align 4
   %mul.us.i.5 = mul nsw i32 %tmp68, %tmp67
   %add.us.i.5 = add nsw i32 %mul.us.i.5, %add.us.i.4
-  %arrayidx8.us.i.6 = getelementptr inbounds i32* %tmp56, i64 6
-  %tmp69 = load i32* %arrayidx8.us.i.6, align 4
-  %arrayidx12.us.i61.6 = getelementptr inbounds i32* %pre99, i64 %indvars.iv42.i
-  %tmp70 = load i32* %arrayidx12.us.i61.6, align 4
+  %arrayidx8.us.i.6 = getelementptr inbounds i32, i32* %tmp56, i64 6
+  %tmp69 = load i32, i32* %arrayidx8.us.i.6, align 4
+  %arrayidx12.us.i61.6 = getelementptr inbounds i32, i32* %pre99, i64 %indvars.iv42.i
+  %tmp70 = load i32, i32* %arrayidx12.us.i61.6, align 4
   %mul.us.i.6 = mul nsw i32 %tmp70, %tmp69
   %add.us.i.6 = add nsw i32 %mul.us.i.6, %add.us.i.5
-  %arrayidx8.us.i.7 = getelementptr inbounds i32* %tmp56, i64 7
-  %tmp71 = load i32* %arrayidx8.us.i.7, align 4
-  %arrayidx12.us.i61.7 = getelementptr inbounds i32* %pre100, i64 %indvars.iv42.i
-  %tmp72 = load i32* %arrayidx12.us.i61.7, align 4
+  %arrayidx8.us.i.7 = getelementptr inbounds i32, i32* %tmp56, i64 7
+  %tmp71 = load i32, i32* %arrayidx8.us.i.7, align 4
+  %arrayidx12.us.i61.7 = getelementptr inbounds i32, i32* %pre100, i64 %indvars.iv42.i
+  %tmp72 = load i32, i32* %arrayidx12.us.i61.7, align 4
   %mul.us.i.7 = mul nsw i32 %tmp72, %tmp71
   %add.us.i.7 = add nsw i32 %mul.us.i.7, %add.us.i.6
-  %arrayidx8.us.i.8 = getelementptr inbounds i32* %tmp56, i64 8
-  %tmp73 = load i32* %arrayidx8.us.i.8, align 4
-  %arrayidx12.us.i61.8 = getelementptr inbounds i32* %pre101, i64 %indvars.iv42.i
-  %tmp74 = load i32* %arrayidx12.us.i61.8, align 4
+  %arrayidx8.us.i.8 = getelementptr inbounds i32, i32* %tmp56, i64 8
+  %tmp73 = load i32, i32* %arrayidx8.us.i.8, align 4
+  %arrayidx12.us.i61.8 = getelementptr inbounds i32, i32* %pre101, i64 %indvars.iv42.i
+  %tmp74 = load i32, i32* %arrayidx12.us.i61.8, align 4
   %mul.us.i.8 = mul nsw i32 %tmp74, %tmp73
   %add.us.i.8 = add nsw i32 %mul.us.i.8, %add.us.i.7
-  %arrayidx8.us.i.9 = getelementptr inbounds i32* %tmp56, i64 9
-  %tmp75 = load i32* %arrayidx8.us.i.9, align 4
-  %arrayidx12.us.i61.9 = getelementptr inbounds i32* %pre102, i64 %indvars.iv42.i
-  %tmp76 = load i32* %arrayidx12.us.i61.9, align 4
+  %arrayidx8.us.i.9 = getelementptr inbounds i32, i32* %tmp56, i64 9
+  %tmp75 = load i32, i32* %arrayidx8.us.i.9, align 4
+  %arrayidx12.us.i61.9 = getelementptr inbounds i32, i32* %pre102, i64 %indvars.iv42.i
+  %tmp76 = load i32, i32* %arrayidx12.us.i61.9, align 4
   %mul.us.i.9 = mul nsw i32 %tmp76, %tmp75
   %add.us.i.9 = add nsw i32 %mul.us.i.9, %add.us.i.8
-  %arrayidx16.us.i = getelementptr inbounds i32* %tmp55, i64 %indvars.iv42.i
+  %arrayidx16.us.i = getelementptr inbounds i32, i32* %tmp55, i64 %indvars.iv42.i
   store i32 %add.us.i.9, i32* %arrayidx16.us.i, align 4
   %indvars.iv.next43.i = add i64 %indvars.iv42.i, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next43.i to i32
@@ -159,46 +159,46 @@ entry:
   br label %for.body
 for.body:
   %indvars.iv42.i = phi i64 [ %indvars.iv.next43.i, %for.body ], [ 0, %entry ]
-  %tmp57 = load i32* %tmp56, align 4
-  %arrayidx12.us.i61 = getelementptr inbounds i32* %pre, i64 %indvars.iv42.i
-  %tmp58 = load i32* %arrayidx12.us.i61, align 4
-  %arrayidx8.us.i.1 = getelementptr inbounds i32* %tmp56, i64 1
-  %tmp59 = load i32* %arrayidx8.us.i.1, align 4
-  %arrayidx12.us.i61.1 = getelementptr inbounds i32* %pre94, i64 %indvars.iv42.i
-  %tmp60 = load i32* %arrayidx12.us.i61.1, align 4
-  %arrayidx8.us.i.2 = getelementptr inbounds i32* %tmp56, i64 2
-  %tmp61 = load i32* %arrayidx8.us.i.2, align 4
-  %arrayidx12.us.i61.2 = getelementptr inbounds i32* %pre95, i64 %indvars.iv42.i
-  %tmp62 = load i32* %arrayidx12.us.i61.2, align 4
-  %arrayidx8.us.i.3 = getelementptr inbounds i32* %tmp56, i64 3
-  %tmp63 = load i32* %arrayidx8.us.i.3, align 4
-  %arrayidx12.us.i61.3 = getelementptr inbounds i32* %pre96, i64 %indvars.iv42.i
-  %tmp64 = load i32* %arrayidx12.us.i61.3, align 4
-  %arrayidx8.us.i.4 = getelementptr inbounds i32* %tmp56, i64 4
-  %tmp65 = load i32* %arrayidx8.us.i.4, align 4
-  %arrayidx12.us.i61.4 = getelementptr inbounds i32* %pre97, i64 %indvars.iv42.i
-  %tmp66 = load i32* %arrayidx12.us.i61.4, align 4
-  %arrayidx8.us.i.5 = getelementptr inbounds i32* %tmp56, i64 5
-  %tmp67 = load i32* %arrayidx8.us.i.5, align 4
-  %arrayidx12.us.i61.5 = getelementptr inbounds i32* %pre98, i64 %indvars.iv42.i
-  %tmp68 = load i32* %arrayidx12.us.i61.5, align 4
-  %arrayidx8.us.i.6 = getelementptr inbounds i32* %tmp56, i64 6
-  %tmp69 = load i32* %arrayidx8.us.i.6, align 4
-  %arrayidx12.us.i61.6 = getelementptr inbounds i32* %pre99, i64 %indvars.iv42.i
-  %tmp70 = load i32* %arrayidx12.us.i61.6, align 4
+  %tmp57 = load i32, i32* %tmp56, align 4
+  %arrayidx12.us.i61 = getelementptr inbounds i32, i32* %pre, i64 %indvars.iv42.i
+  %tmp58 = load i32, i32* %arrayidx12.us.i61, align 4
+  %arrayidx8.us.i.1 = getelementptr inbounds i32, i32* %tmp56, i64 1
+  %tmp59 = load i32, i32* %arrayidx8.us.i.1, align 4
+  %arrayidx12.us.i61.1 = getelementptr inbounds i32, i32* %pre94, i64 %indvars.iv42.i
+  %tmp60 = load i32, i32* %arrayidx12.us.i61.1, align 4
+  %arrayidx8.us.i.2 = getelementptr inbounds i32, i32* %tmp56, i64 2
+  %tmp61 = load i32, i32* %arrayidx8.us.i.2, align 4
+  %arrayidx12.us.i61.2 = getelementptr inbounds i32, i32* %pre95, i64 %indvars.iv42.i
+  %tmp62 = load i32, i32* %arrayidx12.us.i61.2, align 4
+  %arrayidx8.us.i.3 = getelementptr inbounds i32, i32* %tmp56, i64 3
+  %tmp63 = load i32, i32* %arrayidx8.us.i.3, align 4
+  %arrayidx12.us.i61.3 = getelementptr inbounds i32, i32* %pre96, i64 %indvars.iv42.i
+  %tmp64 = load i32, i32* %arrayidx12.us.i61.3, align 4
+  %arrayidx8.us.i.4 = getelementptr inbounds i32, i32* %tmp56, i64 4
+  %tmp65 = load i32, i32* %arrayidx8.us.i.4, align 4
+  %arrayidx12.us.i61.4 = getelementptr inbounds i32, i32* %pre97, i64 %indvars.iv42.i
+  %tmp66 = load i32, i32* %arrayidx12.us.i61.4, align 4
+  %arrayidx8.us.i.5 = getelementptr inbounds i32, i32* %tmp56, i64 5
+  %tmp67 = load i32, i32* %arrayidx8.us.i.5, align 4
+  %arrayidx12.us.i61.5 = getelementptr inbounds i32, i32* %pre98, i64 %indvars.iv42.i
+  %tmp68 = load i32, i32* %arrayidx12.us.i61.5, align 4
+  %arrayidx8.us.i.6 = getelementptr inbounds i32, i32* %tmp56, i64 6
+  %tmp69 = load i32, i32* %arrayidx8.us.i.6, align 4
+  %arrayidx12.us.i61.6 = getelementptr inbounds i32, i32* %pre99, i64 %indvars.iv42.i
+  %tmp70 = load i32, i32* %arrayidx12.us.i61.6, align 4
   %mul.us.i = mul nsw i32 %tmp58, %tmp57
-  %arrayidx8.us.i.7 = getelementptr inbounds i32* %tmp56, i64 7
-  %tmp71 = load i32* %arrayidx8.us.i.7, align 4
-  %arrayidx12.us.i61.7 = getelementptr inbounds i32* %pre100, i64 %indvars.iv42.i
-  %tmp72 = load i32* %arrayidx12.us.i61.7, align 4
-  %arrayidx8.us.i.8 = getelementptr inbounds i32* %tmp56, i64 8
-  %tmp73 = load i32* %arrayidx8.us.i.8, align 4
-  %arrayidx12.us.i61.8 = getelementptr inbounds i32* %pre101, i64 %indvars.iv42.i
-  %tmp74 = load i32* %arrayidx12.us.i61.8, align 4
-  %arrayidx8.us.i.9 = getelementptr inbounds i32* %tmp56, i64 9
-  %tmp75 = load i32* %arrayidx8.us.i.9, align 4
-  %arrayidx12.us.i61.9 = getelementptr inbounds i32* %pre102, i64 %indvars.iv42.i
-  %tmp76 = load i32* %arrayidx12.us.i61.9, align 4
+  %arrayidx8.us.i.7 = getelementptr inbounds i32, i32* %tmp56, i64 7
+  %tmp71 = load i32, i32* %arrayidx8.us.i.7, align 4
+  %arrayidx12.us.i61.7 = getelementptr inbounds i32, i32* %pre100, i64 %indvars.iv42.i
+  %tmp72 = load i32, i32* %arrayidx12.us.i61.7, align 4
+  %arrayidx8.us.i.8 = getelementptr inbounds i32, i32* %tmp56, i64 8
+  %tmp73 = load i32, i32* %arrayidx8.us.i.8, align 4
+  %arrayidx12.us.i61.8 = getelementptr inbounds i32, i32* %pre101, i64 %indvars.iv42.i
+  %tmp74 = load i32, i32* %arrayidx12.us.i61.8, align 4
+  %arrayidx8.us.i.9 = getelementptr inbounds i32, i32* %tmp56, i64 9
+  %tmp75 = load i32, i32* %arrayidx8.us.i.9, align 4
+  %arrayidx12.us.i61.9 = getelementptr inbounds i32, i32* %pre102, i64 %indvars.iv42.i
+  %tmp76 = load i32, i32* %arrayidx12.us.i61.9, align 4
   %mul.us.i.1 = mul nsw i32 %tmp60, %tmp59
   %add.us.i.1 = add nsw i32 %mul.us.i.1, %mul.us.i
   %mul.us.i.2 = mul nsw i32 %tmp62, %tmp61
@@ -217,7 +217,7 @@ for.body:
   %add.us.i.8 = add nsw i32 %mul.us.i.8, %add.us.i.7
   %mul.us.i.9 = mul nsw i32 %tmp76, %tmp75
   %add.us.i.9 = add nsw i32 %mul.us.i.9, %add.us.i.8
-  %arrayidx16.us.i = getelementptr inbounds i32* %tmp55, i64 %indvars.iv42.i
+  %arrayidx16.us.i = getelementptr inbounds i32, i32* %tmp55, i64 %indvars.iv42.i
   store i32 %add.us.i.9, i32* %arrayidx16.us.i, align 4
   %indvars.iv.next43.i = add i64 %indvars.iv42.i, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next43.i to i32
@@ -243,20 +243,20 @@ end:
 @d = external global i32, align 4
 define i32 @encpc1() nounwind {
 entry:
-  %l1 = load i32* @a, align 16
+  %l1 = load i32, i32* @a, align 16
   %conv = shl i32 %l1, 8
   %s5 = lshr i32 %l1, 8
   %add = or i32 %conv, %s5
   store i32 %add, i32* @b
-  %l6 = load i32* @a
-  %l7 = load i32* @c
+  %l6 = load i32, i32* @a
+  %l7 = load i32, i32* @c
   %add.i = add i32 %l7, %l6
   %idxprom.i = zext i32 %l7 to i64
-  %arrayidx.i = getelementptr inbounds i32* @d, i64 %idxprom.i
-  %l8 = load i32* %arrayidx.i
+  %arrayidx.i = getelementptr inbounds i32, i32* @d, i64 %idxprom.i
+  %l8 = load i32, i32* %arrayidx.i
   store i32 346, i32* @c
   store i32 20021, i32* @d
-  %l9 = load i32* @a
+  %l9 = load i32, i32* @a
   store i32 %l8, i32* @a
   store i32 %l9, i32* @b
   store i32 %add.i, i32* @c
diff --git a/test/CodeGen/X86/misched-code-difference-with-debug.ll b/test/CodeGen/X86/misched-code-difference-with-debug.ll
index fb2a986e561b..0f1f382c49a8 100644
--- a/test/CodeGen/X86/misched-code-difference-with-debug.ll
+++ b/test/CodeGen/X86/misched-code-difference-with-debug.ll
@@ -32,11 +32,11 @@ declare i32 @test_function(%class.C*, i8 signext, i8 signext, i8 signext, ...)
 define void @test_without_debug() {
 entry:
   %c = alloca %class.C, align 1
-  %0 = load i8* @argc, align 1
+  %0 = load i8, i8* @argc, align 1
   %conv = sext i8 %0 to i32
-  %call = call i32 (%class.C*, i8, i8, i8, ...)* @test_function(%class.C* %c, i8 signext 0, i8 signext %0, i8 signext 0, i32 %conv)
-  %1 = load i8* @argc, align 1
-  %call2 = call i32 (%class.C*, i8, i8, i8, ...)* @test_function(%class.C* %c, i8 signext 0, i8 signext %1, i8 signext 0, i32 %conv)
+  %call = call i32 (%class.C*, i8, i8, i8, ...) @test_function(%class.C* %c, i8 signext 0, i8 signext %0, i8 signext 0, i32 %conv)
+  %1 = load i8, i8* @argc, align 1
+  %call2 = call i32 (%class.C*, i8, i8, i8, ...) @test_function(%class.C* %c, i8 signext 0, i8 signext %1, i8 signext 0, i32 %conv)
   ret void
 }
 
@@ -46,14 +46,14 @@ entry:
 define void @test_with_debug() {
 entry:
   %c = alloca %class.C, align 1
-  %0 = load i8* @argc, align 1
-  tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !19, metadata !29)
+  %0 = load i8, i8* @argc, align 1
+  tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !19, metadata !29), !dbg !DILocation(scope: !13)
   %conv = sext i8 %0 to i32
-  tail call void @llvm.dbg.value(metadata %class.C* %c, i64 0, metadata !18, metadata !29)
-  %call = call i32 (%class.C*, i8, i8, i8, ...)* @test_function(%class.C* %c, i8 signext 0, i8 signext %0, i8 signext 0, i32 %conv)
-  %1 = load i8* @argc, align 1
-  call void @llvm.dbg.value(metadata %class.C* %c, i64 0, metadata !18, metadata !29)
-  %call2 = call i32 (%class.C*, i8, i8, i8, ...)* @test_function(%class.C* %c, i8 signext 0, i8 signext %1, i8 signext 0, i32 %conv)
+  tail call void @llvm.dbg.value(metadata %class.C* %c, i64 0, metadata !18, metadata !29), !dbg !DILocation(scope: !13)
+  %call = call i32 (%class.C*, i8, i8, i8, ...) @test_function(%class.C* %c, i8 signext 0, i8 signext %0, i8 signext 0, i32 %conv)
+  %1 = load i8, i8* @argc, align 1
+  call void @llvm.dbg.value(metadata %class.C* %c, i64 0, metadata !18, metadata !29), !dbg !DILocation(scope: !13)
+  %call2 = call i32 (%class.C*, i8, i8, i8, ...) @test_function(%class.C* %c, i8 signext 0, i8 signext %1, i8 signext 0, i32 %conv)
   ret void
 }
 
@@ -62,29 +62,29 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!22, !23}
 
-!0 = !{!"", !1, !2, !3, !12, !20, !2} ; [ DW_TAG_compile_unit ] [test.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"test.cpp", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, enums: !2, retainedTypes: !3, subprograms: !12, globals: !20, imports: !2)
+!1 = !DIFile(filename: "test.cpp", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2\00C\002\008\008\000\000\000", !1, null, null, !5, null, null, !"_ZTS1C"} ; [ DW_TAG_class_type ] [C] [line 2, size 8, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_class_type, name: "C", line: 2, size: 8, align: 8, file: !1, elements: !5, identifier: "_ZTS1C")
 !5 = !{!6}
-!6 = !{!"", !1, !"_ZTS1C", !7, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 4] [public] [test]
-!7 = !{!"", null, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DISubprogram(name: "test", file: !1, scope: !"_ZTS1C", type: !7)
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !10, !11, !11, !11, null}
-!9 = !{!"", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"", null, null, !"_ZTS1C"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1C]
-!11 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
+!9 = !DIBasicType(encoding: DW_ATE_signed, size: 32, align: 32, name: "int")
+!10 = !DIDerivedType(baseType: !"_ZTS1C", tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
 !12 = !{!13}
-!13 = !{!"0x2e\00test_with_debug\00test_with_debug\00test_with_debug\006\000\001\000\000\00256\001\006", !1, !14, !15, null, void ()* @test_with_debug, null, null, !17} ; [ DW_TAG_subprogram ] [line 6] [def] [test_with_debug]
-!14 = !{!"0x29", !1}
-!15 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DISubprogram(name: "test_with_debug", linkageName: "test_with_debug", line: 6, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 6, file: !1, scope: !14, type: !15, function: void ()* @test_with_debug, variables: !17)
+!14 = !DIFile(filename: "test.cpp", directory: "")
+!15 = !DISubroutineType(types: !16)
 !16 = !{null}
 !17 = !{!18, !19}
-!18 = !{!"0x100\00c\007\000", !13, !14, !"_ZTS1C"} ; [ DW_TAG_auto_variable ] [c] [line 7]
-!19 = !{!"0x100\00lc\008\000", !13, !14, !11} ; [ DW_TAG_auto_variable ] [lc] [line 8]
+!18 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "c", line: 7, scope: !13, file: !14, type: !"_ZTS1C")
+!19 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "lc", line: 8, scope: !13, file: !14, type: !11)
 !20 = !{!21}
-!21 = !{!"0x34\00argc\00argc\00\001\000\001", null, !14, !11, i8* @argc, null} ; [ DW_TAG_variable ] [argc] [line 1] [def]
+!21 = !DIGlobalVariable(name: "argc", line: 1, isLocal: false, isDefinition: true, scope: null, file: !14, type: !11, variable: i8* @argc)
 !22 = !{i32 2, !"Dwarf Version", i32 4}
-!23 = !{i32 2, !"Debug Info Version", i32 2}
-!25 = !MDLocation(line: 8, column: 3, scope: !13)
-!29 = !{!"0x102"}               ; [ DW_TAG_expression ]
+!23 = !{i32 2, !"Debug Info Version", i32 3}
+!25 = !DILocation(line: 8, column: 3, scope: !13)
+!29 = !DIExpression()
diff --git a/test/CodeGen/X86/misched-crash.ll b/test/CodeGen/X86/misched-crash.ll
index 21c3fa3510d6..fa7de1a843ea 100644
--- a/test/CodeGen/X86/misched-crash.ll
+++ b/test/CodeGen/X86/misched-crash.ll
@@ -9,7 +9,7 @@ entry:
   %cmp = icmp ult i64 %_x1, %_x2
   %cond = select i1 %cmp, i64 %_x1, i64 %_x2
   %cond10 = select i1 %cmp, i64 %_x2, i64 %_x1
-  %0 = load i64* null, align 8
+  %0 = load i64, i64* null, align 8
   %cmp16 = icmp ult i64 %cond, %0
   %cmp23 = icmp ugt i64 %cond10, 0
   br i1 %cmp16, label %land.lhs.true21, label %return
@@ -26,8 +26,8 @@ if.then24:                                        ; preds = %land.lhs.true21
 
 for.body34.i:                                     ; preds = %for.inc39.i, %if.then24
   %index.178.i = phi i64 [ %add21.i, %if.then24 ], [ %inc41.i, %for.inc39.i ]
-  %arrayidx35.i = getelementptr inbounds i8* %plane, i64 %index.178.i
-  %1 = load i8* %arrayidx35.i, align 1
+  %arrayidx35.i = getelementptr inbounds i8, i8* %plane, i64 %index.178.i
+  %1 = load i8, i8* %arrayidx35.i, align 1
   %tobool36.i = icmp eq i8 %1, 0
   br i1 %tobool36.i, label %for.inc39.i, label %return
 
diff --git a/test/CodeGen/X86/misched-fusion.ll b/test/CodeGen/X86/misched-fusion.ll
index 859d92d6978b..0975faacb9ed 100644
--- a/test/CodeGen/X86/misched-fusion.ll
+++ b/test/CodeGen/X86/misched-fusion.ll
@@ -16,11 +16,11 @@ loop:
 
 loop1:
   %cond = icmp eq i32* %var, null
-  %next.load = load i32** %next.ptr
+  %next.load = load i32*, i32** %next.ptr
   br i1 %cond, label %loop, label %loop2
 
 loop2:                                           ; preds = %loop1
-  %gep = getelementptr inbounds i32** %next.ptr, i32 1
+  %gep = getelementptr inbounds i32*, i32** %next.ptr, i32 1
   store i32* %next.load, i32** undef
   br label %loop
 }
@@ -42,12 +42,12 @@ loop:
 loop1:
   %var2 = sub i32 %var, 1
   %cond = icmp eq i32 %var2, 0
-  %next.load = load i32** %next.ptr
-  %next.var = load i32* %next.load
+  %next.load = load i32*, i32** %next.ptr
+  %next.var = load i32, i32* %next.load
   br i1 %cond, label %loop, label %loop2
 
 loop2:
-  %gep = getelementptr inbounds i32** %next.ptr, i32 1
+  %gep = getelementptr inbounds i32*, i32** %next.ptr, i32 1
   store i32* %next.load, i32** undef
   br label %loop
 }
@@ -70,12 +70,12 @@ loop2a:                                           ; preds = %loop1, %body, %entr
 loop1:                                            ; preds = %loop2a, %loop2b
   %var2 = sub i32 %var, 1
   %cond = icmp slt i32 %var2, 0
-  %next.load = load i32** %next.ptr
-  %next.var = load i32* %next.load
+  %next.load = load i32*, i32** %next.ptr
+  %next.var = load i32, i32* %next.load
   br i1 %cond, label %loop2a, label %loop2b
 
 loop2b:                                           ; preds = %loop1
-  %gep = getelementptr inbounds i32** %next.ptr, i32 1
+  %gep = getelementptr inbounds i32*, i32** %next.ptr, i32 1
   store i32* %next.load, i32** undef
   br label %loop2a
 }
@@ -97,12 +97,12 @@ loop2a:                                           ; preds = %loop1, %body, %entr
 loop1:                                            ; preds = %loop2a, %loop2b
   %var2 = sub i32 %var, 1
   %cond = icmp ult i32 %var2, %n
-  %next.load = load i32** %next.ptr
-  %next.var = load i32* %next.load
+  %next.load = load i32*, i32** %next.ptr
+  %next.var = load i32, i32* %next.load
   br i1 %cond, label %loop2a, label %loop2b
 
 loop2b:                                           ; preds = %loop1
-  %gep = getelementptr inbounds i32** %next.ptr, i32 1
+  %gep = getelementptr inbounds i32*, i32** %next.ptr, i32 1
   store i32* %next.load, i32** undef
   br label %loop2a
 }
diff --git a/test/CodeGen/X86/misched-matmul.ll b/test/CodeGen/X86/misched-matmul.ll
index 5454b7cf780a..384344691f9b 100644
--- a/test/CodeGen/X86/misched-matmul.ll
+++ b/test/CodeGen/X86/misched-matmul.ll
@@ -14,87 +14,87 @@
 
 define void @wrap_mul4(double* nocapture %Out, [4 x double]* nocapture %A, [4 x double]* nocapture %B) #0 {
 entry:
-  %arrayidx1.i = getelementptr inbounds [4 x double]* %A, i64 0, i64 0
-  %0 = load double* %arrayidx1.i, align 8
-  %arrayidx3.i = getelementptr inbounds [4 x double]* %B, i64 0, i64 0
-  %1 = load double* %arrayidx3.i, align 8
+  %arrayidx1.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 0, i64 0
+  %0 = load double, double* %arrayidx1.i, align 8
+  %arrayidx3.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 0, i64 0
+  %1 = load double, double* %arrayidx3.i, align 8
   %mul.i = fmul double %0, %1
-  %arrayidx5.i = getelementptr inbounds [4 x double]* %A, i64 0, i64 1
-  %2 = load double* %arrayidx5.i, align 8
-  %arrayidx7.i = getelementptr inbounds [4 x double]* %B, i64 1, i64 0
-  %3 = load double* %arrayidx7.i, align 8
+  %arrayidx5.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 0, i64 1
+  %2 = load double, double* %arrayidx5.i, align 8
+  %arrayidx7.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 1, i64 0
+  %3 = load double, double* %arrayidx7.i, align 8
   %mul8.i = fmul double %2, %3
   %add.i = fadd double %mul.i, %mul8.i
-  %arrayidx10.i = getelementptr inbounds [4 x double]* %A, i64 0, i64 2
-  %4 = load double* %arrayidx10.i, align 8
-  %arrayidx12.i = getelementptr inbounds [4 x double]* %B, i64 2, i64 0
-  %5 = load double* %arrayidx12.i, align 8
+  %arrayidx10.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 0, i64 2
+  %4 = load double, double* %arrayidx10.i, align 8
+  %arrayidx12.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 2, i64 0
+  %5 = load double, double* %arrayidx12.i, align 8
   %mul13.i = fmul double %4, %5
   %add14.i = fadd double %add.i, %mul13.i
-  %arrayidx16.i = getelementptr inbounds [4 x double]* %A, i64 0, i64 3
-  %6 = load double* %arrayidx16.i, align 8
-  %arrayidx18.i = getelementptr inbounds [4 x double]* %B, i64 3, i64 0
-  %7 = load double* %arrayidx18.i, align 8
+  %arrayidx16.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 0, i64 3
+  %6 = load double, double* %arrayidx16.i, align 8
+  %arrayidx18.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 3, i64 0
+  %7 = load double, double* %arrayidx18.i, align 8
   %mul19.i = fmul double %6, %7
   %add20.i = fadd double %add14.i, %mul19.i
-  %arrayidx25.i = getelementptr inbounds [4 x double]* %B, i64 0, i64 1
-  %8 = load double* %arrayidx25.i, align 8
+  %arrayidx25.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 0, i64 1
+  %8 = load double, double* %arrayidx25.i, align 8
   %mul26.i = fmul double %0, %8
-  %arrayidx30.i = getelementptr inbounds [4 x double]* %B, i64 1, i64 1
-  %9 = load double* %arrayidx30.i, align 8
+  %arrayidx30.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 1, i64 1
+  %9 = load double, double* %arrayidx30.i, align 8
   %mul31.i = fmul double %2, %9
   %add32.i = fadd double %mul26.i, %mul31.i
-  %arrayidx36.i = getelementptr inbounds [4 x double]* %B, i64 2, i64 1
-  %10 = load double* %arrayidx36.i, align 8
+  %arrayidx36.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 2, i64 1
+  %10 = load double, double* %arrayidx36.i, align 8
   %mul37.i = fmul double %4, %10
   %add38.i = fadd double %add32.i, %mul37.i
-  %arrayidx42.i = getelementptr inbounds [4 x double]* %B, i64 3, i64 1
-  %11 = load double* %arrayidx42.i, align 8
+  %arrayidx42.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 3, i64 1
+  %11 = load double, double* %arrayidx42.i, align 8
   %mul43.i = fmul double %6, %11
   %add44.i = fadd double %add38.i, %mul43.i
-  %arrayidx49.i = getelementptr inbounds [4 x double]* %B, i64 0, i64 2
-  %12 = load double* %arrayidx49.i, align 8
+  %arrayidx49.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 0, i64 2
+  %12 = load double, double* %arrayidx49.i, align 8
   %mul50.i = fmul double %0, %12
-  %arrayidx54.i = getelementptr inbounds [4 x double]* %B, i64 1, i64 2
-  %13 = load double* %arrayidx54.i, align 8
+  %arrayidx54.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 1, i64 2
+  %13 = load double, double* %arrayidx54.i, align 8
   %mul55.i = fmul double %2, %13
   %add56.i = fadd double %mul50.i, %mul55.i
-  %arrayidx60.i = getelementptr inbounds [4 x double]* %B, i64 2, i64 2
-  %14 = load double* %arrayidx60.i, align 8
+  %arrayidx60.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 2, i64 2
+  %14 = load double, double* %arrayidx60.i, align 8
   %mul61.i = fmul double %4, %14
   %add62.i = fadd double %add56.i, %mul61.i
-  %arrayidx66.i = getelementptr inbounds [4 x double]* %B, i64 3, i64 2
-  %15 = load double* %arrayidx66.i, align 8
+  %arrayidx66.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 3, i64 2
+  %15 = load double, double* %arrayidx66.i, align 8
   %mul67.i = fmul double %6, %15
   %add68.i = fadd double %add62.i, %mul67.i
-  %arrayidx73.i = getelementptr inbounds [4 x double]* %B, i64 0, i64 3
-  %16 = load double* %arrayidx73.i, align 8
+  %arrayidx73.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 0, i64 3
+  %16 = load double, double* %arrayidx73.i, align 8
   %mul74.i = fmul double %0, %16
-  %arrayidx78.i = getelementptr inbounds [4 x double]* %B, i64 1, i64 3
-  %17 = load double* %arrayidx78.i, align 8
+  %arrayidx78.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 1, i64 3
+  %17 = load double, double* %arrayidx78.i, align 8
   %mul79.i = fmul double %2, %17
   %add80.i = fadd double %mul74.i, %mul79.i
-  %arrayidx84.i = getelementptr inbounds [4 x double]* %B, i64 2, i64 3
-  %18 = load double* %arrayidx84.i, align 8
+  %arrayidx84.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 2, i64 3
+  %18 = load double, double* %arrayidx84.i, align 8
   %mul85.i = fmul double %4, %18
   %add86.i = fadd double %add80.i, %mul85.i
-  %arrayidx90.i = getelementptr inbounds [4 x double]* %B, i64 3, i64 3
-  %19 = load double* %arrayidx90.i, align 8
+  %arrayidx90.i = getelementptr inbounds [4 x double], [4 x double]* %B, i64 3, i64 3
+  %19 = load double, double* %arrayidx90.i, align 8
   %mul91.i = fmul double %6, %19
   %add92.i = fadd double %add86.i, %mul91.i
-  %arrayidx95.i = getelementptr inbounds [4 x double]* %A, i64 1, i64 0
-  %20 = load double* %arrayidx95.i, align 8
+  %arrayidx95.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 1, i64 0
+  %20 = load double, double* %arrayidx95.i, align 8
   %mul98.i = fmul double %1, %20
-  %arrayidx100.i = getelementptr inbounds [4 x double]* %A, i64 1, i64 1
-  %21 = load double* %arrayidx100.i, align 8
+  %arrayidx100.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 1, i64 1
+  %21 = load double, double* %arrayidx100.i, align 8
   %mul103.i = fmul double %3, %21
   %add104.i = fadd double %mul98.i, %mul103.i
-  %arrayidx106.i = getelementptr inbounds [4 x double]* %A, i64 1, i64 2
-  %22 = load double* %arrayidx106.i, align 8
+  %arrayidx106.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 1, i64 2
+  %22 = load double, double* %arrayidx106.i, align 8
   %mul109.i = fmul double %5, %22
   %add110.i = fadd double %add104.i, %mul109.i
-  %arrayidx112.i = getelementptr inbounds [4 x double]* %A, i64 1, i64 3
-  %23 = load double* %arrayidx112.i, align 8
+  %arrayidx112.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 1, i64 3
+  %23 = load double, double* %arrayidx112.i, align 8
   %mul115.i = fmul double %7, %23
   %add116.i = fadd double %add110.i, %mul115.i
   %mul122.i = fmul double %8, %20
@@ -118,19 +118,19 @@ entry:
   %add182.i = fadd double %add176.i, %mul181.i
   %mul187.i = fmul double %19, %23
   %add188.i = fadd double %add182.i, %mul187.i
-  %arrayidx191.i = getelementptr inbounds [4 x double]* %A, i64 2, i64 0
-  %24 = load double* %arrayidx191.i, align 8
+  %arrayidx191.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 2, i64 0
+  %24 = load double, double* %arrayidx191.i, align 8
   %mul194.i = fmul double %1, %24
-  %arrayidx196.i = getelementptr inbounds [4 x double]* %A, i64 2, i64 1
-  %25 = load double* %arrayidx196.i, align 8
+  %arrayidx196.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 2, i64 1
+  %25 = load double, double* %arrayidx196.i, align 8
   %mul199.i = fmul double %3, %25
   %add200.i = fadd double %mul194.i, %mul199.i
-  %arrayidx202.i = getelementptr inbounds [4 x double]* %A, i64 2, i64 2
-  %26 = load double* %arrayidx202.i, align 8
+  %arrayidx202.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 2, i64 2
+  %26 = load double, double* %arrayidx202.i, align 8
   %mul205.i = fmul double %5, %26
   %add206.i = fadd double %add200.i, %mul205.i
-  %arrayidx208.i = getelementptr inbounds [4 x double]* %A, i64 2, i64 3
-  %27 = load double* %arrayidx208.i, align 8
+  %arrayidx208.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 2, i64 3
+  %27 = load double, double* %arrayidx208.i, align 8
   %mul211.i = fmul double %7, %27
   %add212.i = fadd double %add206.i, %mul211.i
   %mul218.i = fmul double %8, %24
@@ -154,19 +154,19 @@ entry:
   %add278.i = fadd double %add272.i, %mul277.i
   %mul283.i = fmul double %19, %27
   %add284.i = fadd double %add278.i, %mul283.i
-  %arrayidx287.i = getelementptr inbounds [4 x double]* %A, i64 3, i64 0
-  %28 = load double* %arrayidx287.i, align 8
+  %arrayidx287.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 3, i64 0
+  %28 = load double, double* %arrayidx287.i, align 8
   %mul290.i = fmul double %1, %28
-  %arrayidx292.i = getelementptr inbounds [4 x double]* %A, i64 3, i64 1
-  %29 = load double* %arrayidx292.i, align 8
+  %arrayidx292.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 3, i64 1
+  %29 = load double, double* %arrayidx292.i, align 8
   %mul295.i = fmul double %3, %29
   %add296.i = fadd double %mul290.i, %mul295.i
-  %arrayidx298.i = getelementptr inbounds [4 x double]* %A, i64 3, i64 2
-  %30 = load double* %arrayidx298.i, align 8
+  %arrayidx298.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 3, i64 2
+  %30 = load double, double* %arrayidx298.i, align 8
   %mul301.i = fmul double %5, %30
   %add302.i = fadd double %add296.i, %mul301.i
-  %arrayidx304.i = getelementptr inbounds [4 x double]* %A, i64 3, i64 3
-  %31 = load double* %arrayidx304.i, align 8
+  %arrayidx304.i = getelementptr inbounds [4 x double], [4 x double]* %A, i64 3, i64 3
+  %31 = load double, double* %arrayidx304.i, align 8
   %mul307.i = fmul double %7, %31
   %add308.i = fadd double %add302.i, %mul307.i
   %mul314.i = fmul double %8, %28
@@ -191,35 +191,35 @@ entry:
   %mul379.i = fmul double %19, %31
   %add380.i = fadd double %add374.i, %mul379.i
   store double %add20.i, double* %Out, align 8
-  %Res.i.sroa.1.8.idx2 = getelementptr inbounds double* %Out, i64 1
+  %Res.i.sroa.1.8.idx2 = getelementptr inbounds double, double* %Out, i64 1
   store double %add44.i, double* %Res.i.sroa.1.8.idx2, align 8
-  %Res.i.sroa.2.16.idx4 = getelementptr inbounds double* %Out, i64 2
+  %Res.i.sroa.2.16.idx4 = getelementptr inbounds double, double* %Out, i64 2
   store double %add68.i, double* %Res.i.sroa.2.16.idx4, align 8
-  %Res.i.sroa.3.24.idx6 = getelementptr inbounds double* %Out, i64 3
+  %Res.i.sroa.3.24.idx6 = getelementptr inbounds double, double* %Out, i64 3
   store double %add92.i, double* %Res.i.sroa.3.24.idx6, align 8
-  %Res.i.sroa.4.32.idx8 = getelementptr inbounds double* %Out, i64 4
+  %Res.i.sroa.4.32.idx8 = getelementptr inbounds double, double* %Out, i64 4
   store double %add116.i, double* %Res.i.sroa.4.32.idx8, align 8
-  %Res.i.sroa.5.40.idx10 = getelementptr inbounds double* %Out, i64 5
+  %Res.i.sroa.5.40.idx10 = getelementptr inbounds double, double* %Out, i64 5
   store double %add140.i, double* %Res.i.sroa.5.40.idx10, align 8
-  %Res.i.sroa.6.48.idx12 = getelementptr inbounds double* %Out, i64 6
+  %Res.i.sroa.6.48.idx12 = getelementptr inbounds double, double* %Out, i64 6
   store double %add164.i, double* %Res.i.sroa.6.48.idx12, align 8
-  %Res.i.sroa.7.56.idx14 = getelementptr inbounds double* %Out, i64 7
+  %Res.i.sroa.7.56.idx14 = getelementptr inbounds double, double* %Out, i64 7
   store double %add188.i, double* %Res.i.sroa.7.56.idx14, align 8
-  %Res.i.sroa.8.64.idx16 = getelementptr inbounds double* %Out, i64 8
+  %Res.i.sroa.8.64.idx16 = getelementptr inbounds double, double* %Out, i64 8
   store double %add212.i, double* %Res.i.sroa.8.64.idx16, align 8
-  %Res.i.sroa.9.72.idx18 = getelementptr inbounds double* %Out, i64 9
+  %Res.i.sroa.9.72.idx18 = getelementptr inbounds double, double* %Out, i64 9
   store double %add236.i, double* %Res.i.sroa.9.72.idx18, align 8
-  %Res.i.sroa.10.80.idx20 = getelementptr inbounds double* %Out, i64 10
+  %Res.i.sroa.10.80.idx20 = getelementptr inbounds double, double* %Out, i64 10
   store double %add260.i, double* %Res.i.sroa.10.80.idx20, align 8
-  %Res.i.sroa.11.88.idx22 = getelementptr inbounds double* %Out, i64 11
+  %Res.i.sroa.11.88.idx22 = getelementptr inbounds double, double* %Out, i64 11
   store double %add284.i, double* %Res.i.sroa.11.88.idx22, align 8
-  %Res.i.sroa.12.96.idx24 = getelementptr inbounds double* %Out, i64 12
+  %Res.i.sroa.12.96.idx24 = getelementptr inbounds double, double* %Out, i64 12
   store double %add308.i, double* %Res.i.sroa.12.96.idx24, align 8
-  %Res.i.sroa.13.104.idx26 = getelementptr inbounds double* %Out, i64 13
+  %Res.i.sroa.13.104.idx26 = getelementptr inbounds double, double* %Out, i64 13
   store double %add332.i, double* %Res.i.sroa.13.104.idx26, align 8
-  %Res.i.sroa.14.112.idx28 = getelementptr inbounds double* %Out, i64 14
+  %Res.i.sroa.14.112.idx28 = getelementptr inbounds double, double* %Out, i64 14
   store double %add356.i, double* %Res.i.sroa.14.112.idx28, align 8
-  %Res.i.sroa.15.120.idx30 = getelementptr inbounds double* %Out, i64 15
+  %Res.i.sroa.15.120.idx30 = getelementptr inbounds double, double* %Out, i64 15
   store double %add380.i, double* %Res.i.sroa.15.120.idx30, align 8
   ret void
 }
diff --git a/test/CodeGen/X86/misched-matrix.ll b/test/CodeGen/X86/misched-matrix.ll
index 23b561f6e5db..e62a1d04dad6 100644
--- a/test/CodeGen/X86/misched-matrix.ll
+++ b/test/CodeGen/X86/misched-matrix.ll
@@ -93,58 +93,58 @@ entry:
 
 for.body:                              ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx8 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 0
-  %tmp = load i32* %arrayidx8, align 4
-  %arrayidx12 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 0
-  %tmp1 = load i32* %arrayidx12, align 4
-  %arrayidx8.1 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 1
-  %tmp2 = load i32* %arrayidx8.1, align 4
-  %arrayidx12.1 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 0
-  %tmp3 = load i32* %arrayidx12.1, align 4
-  %arrayidx8.2 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 2
-  %tmp4 = load i32* %arrayidx8.2, align 4
-  %arrayidx12.2 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 0
-  %tmp5 = load i32* %arrayidx12.2, align 4
-  %arrayidx8.3 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 3
-  %tmp6 = load i32* %arrayidx8.3, align 4
-  %arrayidx12.3 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 0
-  %tmp8 = load i32* %arrayidx8, align 4
-  %arrayidx12.137 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 1
-  %tmp9 = load i32* %arrayidx12.137, align 4
-  %tmp10 = load i32* %arrayidx8.1, align 4
-  %arrayidx12.1.1 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 1
-  %tmp11 = load i32* %arrayidx12.1.1, align 4
-  %tmp12 = load i32* %arrayidx8.2, align 4
-  %arrayidx12.2.1 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 1
-  %tmp13 = load i32* %arrayidx12.2.1, align 4
-  %tmp14 = load i32* %arrayidx8.3, align 4
-  %arrayidx12.3.1 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 1
-  %tmp15 = load i32* %arrayidx12.3.1, align 4
-  %tmp16 = load i32* %arrayidx8, align 4
-  %arrayidx12.239 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 2
-  %tmp17 = load i32* %arrayidx12.239, align 4
-  %tmp18 = load i32* %arrayidx8.1, align 4
-  %arrayidx12.1.2 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 2
-  %tmp19 = load i32* %arrayidx12.1.2, align 4
-  %tmp20 = load i32* %arrayidx8.2, align 4
-  %arrayidx12.2.2 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 2
-  %tmp21 = load i32* %arrayidx12.2.2, align 4
-  %tmp22 = load i32* %arrayidx8.3, align 4
-  %arrayidx12.3.2 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 2
-  %tmp23 = load i32* %arrayidx12.3.2, align 4
-  %tmp24 = load i32* %arrayidx8, align 4
-  %arrayidx12.341 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 3
-  %tmp25 = load i32* %arrayidx12.341, align 4
-  %tmp26 = load i32* %arrayidx8.1, align 4
-  %arrayidx12.1.3 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 3
-  %tmp27 = load i32* %arrayidx12.1.3, align 4
-  %tmp28 = load i32* %arrayidx8.2, align 4
-  %arrayidx12.2.3 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 3
-  %tmp29 = load i32* %arrayidx12.2.3, align 4
-  %tmp30 = load i32* %arrayidx8.3, align 4
-  %arrayidx12.3.3 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 3
-  %tmp31 = load i32* %arrayidx12.3.3, align 4
-  %tmp7 = load i32* %arrayidx12.3, align 4
+  %arrayidx8 = getelementptr inbounds [4 x i32], [4 x i32]* %m1, i64 %indvars.iv, i64 0
+  %tmp = load i32, i32* %arrayidx8, align 4
+  %arrayidx12 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 0, i64 0
+  %tmp1 = load i32, i32* %arrayidx12, align 4
+  %arrayidx8.1 = getelementptr inbounds [4 x i32], [4 x i32]* %m1, i64 %indvars.iv, i64 1
+  %tmp2 = load i32, i32* %arrayidx8.1, align 4
+  %arrayidx12.1 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 1, i64 0
+  %tmp3 = load i32, i32* %arrayidx12.1, align 4
+  %arrayidx8.2 = getelementptr inbounds [4 x i32], [4 x i32]* %m1, i64 %indvars.iv, i64 2
+  %tmp4 = load i32, i32* %arrayidx8.2, align 4
+  %arrayidx12.2 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 2, i64 0
+  %tmp5 = load i32, i32* %arrayidx12.2, align 4
+  %arrayidx8.3 = getelementptr inbounds [4 x i32], [4 x i32]* %m1, i64 %indvars.iv, i64 3
+  %tmp6 = load i32, i32* %arrayidx8.3, align 4
+  %arrayidx12.3 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 3, i64 0
+  %tmp8 = load i32, i32* %arrayidx8, align 4
+  %arrayidx12.137 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 0, i64 1
+  %tmp9 = load i32, i32* %arrayidx12.137, align 4
+  %tmp10 = load i32, i32* %arrayidx8.1, align 4
+  %arrayidx12.1.1 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 1, i64 1
+  %tmp11 = load i32, i32* %arrayidx12.1.1, align 4
+  %tmp12 = load i32, i32* %arrayidx8.2, align 4
+  %arrayidx12.2.1 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 2, i64 1
+  %tmp13 = load i32, i32* %arrayidx12.2.1, align 4
+  %tmp14 = load i32, i32* %arrayidx8.3, align 4
+  %arrayidx12.3.1 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 3, i64 1
+  %tmp15 = load i32, i32* %arrayidx12.3.1, align 4
+  %tmp16 = load i32, i32* %arrayidx8, align 4
+  %arrayidx12.239 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 0, i64 2
+  %tmp17 = load i32, i32* %arrayidx12.239, align 4
+  %tmp18 = load i32, i32* %arrayidx8.1, align 4
+  %arrayidx12.1.2 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 1, i64 2
+  %tmp19 = load i32, i32* %arrayidx12.1.2, align 4
+  %tmp20 = load i32, i32* %arrayidx8.2, align 4
+  %arrayidx12.2.2 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 2, i64 2
+  %tmp21 = load i32, i32* %arrayidx12.2.2, align 4
+  %tmp22 = load i32, i32* %arrayidx8.3, align 4
+  %arrayidx12.3.2 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 3, i64 2
+  %tmp23 = load i32, i32* %arrayidx12.3.2, align 4
+  %tmp24 = load i32, i32* %arrayidx8, align 4
+  %arrayidx12.341 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 0, i64 3
+  %tmp25 = load i32, i32* %arrayidx12.341, align 4
+  %tmp26 = load i32, i32* %arrayidx8.1, align 4
+  %arrayidx12.1.3 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 1, i64 3
+  %tmp27 = load i32, i32* %arrayidx12.1.3, align 4
+  %tmp28 = load i32, i32* %arrayidx8.2, align 4
+  %arrayidx12.2.3 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 2, i64 3
+  %tmp29 = load i32, i32* %arrayidx12.2.3, align 4
+  %tmp30 = load i32, i32* %arrayidx8.3, align 4
+  %arrayidx12.3.3 = getelementptr inbounds [4 x i32], [4 x i32]* %m2, i64 3, i64 3
+  %tmp31 = load i32, i32* %arrayidx12.3.3, align 4
+  %tmp7 = load i32, i32* %arrayidx12.3, align 4
   %mul = mul nsw i32 %tmp1, %tmp
   %mul.1 = mul nsw i32 %tmp3, %tmp2
   %mul.2 = mul nsw i32 %tmp5, %tmp4
@@ -173,13 +173,13 @@ for.body:                              ; preds = %for.body, %entry
   %add.1.3 = add nsw i32 %mul.1.3, %mul.342
   %add.2.3 = add nsw i32 %mul.2.3, %add.1.3
   %add.3.3 = add nsw i32 %mul.3.3, %add.2.3
-  %arrayidx16 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 0
+  %arrayidx16 = getelementptr inbounds [4 x i32], [4 x i32]* %m3, i64 %indvars.iv, i64 0
   store i32 %add.3, i32* %arrayidx16, align 4
-  %arrayidx16.1 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 1
+  %arrayidx16.1 = getelementptr inbounds [4 x i32], [4 x i32]* %m3, i64 %indvars.iv, i64 1
   store i32 %add.3.1, i32* %arrayidx16.1, align 4
-  %arrayidx16.2 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 2
+  %arrayidx16.2 = getelementptr inbounds [4 x i32], [4 x i32]* %m3, i64 %indvars.iv, i64 2
   store i32 %add.3.2, i32* %arrayidx16.2, align 4
-  %arrayidx16.3 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 3
+  %arrayidx16.3 = getelementptr inbounds [4 x i32], [4 x i32]* %m3, i64 %indvars.iv, i64 3
   store i32 %add.3.3, i32* %arrayidx16.3, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/CodeGen/X86/misched-new.ll b/test/CodeGen/X86/misched-new.ll
index 89e45b7cfc21..410a7f320643 100644
--- a/test/CodeGen/X86/misched-new.ll
+++ b/test/CodeGen/X86/misched-new.ll
@@ -90,12 +90,12 @@ define void @hasundef() unnamed_addr uwtable ssp align 2 {
 ; TOPDOWN: movzbl %al
 ; TOPDOWN: ret
 define void @testSubregTracking() nounwind uwtable ssp align 2 {
-  %tmp = load i8* undef, align 1
+  %tmp = load i8, i8* undef, align 1
   %tmp6 = sub i8 0, %tmp
-  %tmp7 = load i8* undef, align 1
+  %tmp7 = load i8, i8* undef, align 1
   %tmp8 = udiv i8 %tmp6, %tmp7
   %tmp9 = zext i8 %tmp8 to i64
-  %tmp10 = load i8* undef, align 1
+  %tmp10 = load i8, i8* undef, align 1
   %tmp11 = zext i8 %tmp10 to i64
   %tmp12 = mul i64 %tmp11, %tmp9
   %tmp13 = urem i8 %tmp6, %tmp7
diff --git a/test/CodeGen/X86/mmx-arg-passing-x86-64.ll b/test/CodeGen/X86/mmx-arg-passing-x86-64.ll
new file mode 100644
index 000000000000..2727e3eb0280
--- /dev/null
+++ b/test/CodeGen/X86/mmx-arg-passing-x86-64.ll
@@ -0,0 +1,54 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X86-64
+;
+; On Darwin x86-64, v8i8, v4i16, v2i32 values are passed in XMM[0-7].
+; On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.
+
+@g_v8qi = external global <8 x i8>
+
+define void @t3() nounwind  {
+; X86-64-LABEL: t3:
+; X86-64:       ## BB#0:
+; X86-64-NEXT:    movq _g_v8qi@{{.*}}(%rip), %rax
+; X86-64-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
+; X86-64-NEXT:    movb $1, %al
+; X86-64-NEXT:    jmp _pass_v8qi ## TAILCALL
+  %tmp3 = load <8 x i8>, <8 x i8>* @g_v8qi, align 8
+  %tmp3a = bitcast <8 x i8> %tmp3 to x86_mmx
+  %tmp4 = tail call i32 (...) @pass_v8qi( x86_mmx %tmp3a ) nounwind
+  ret void
+}
+
+define void @t4(x86_mmx %v1, x86_mmx %v2) nounwind  {
+; X86-64-LABEL: t4:
+; X86-64:       ## BB#0:
+; X86-64-NEXT:    movdq2q %xmm1, %mm0
+; X86-64-NEXT:    movq %mm0, -{{[0-9]+}}(%rsp)
+; X86-64-NEXT:    movdq2q %xmm0, %mm0
+; X86-64-NEXT:    movq %mm0, -{{[0-9]+}}(%rsp)
+; X86-64-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero
+; X86-64-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
+; X86-64-NEXT:    paddb %xmm1, %xmm0
+; X86-64-NEXT:    movb $1, %al
+; X86-64-NEXT:    jmp _pass_v8qi ## TAILCALL
+  %v1a = bitcast x86_mmx %v1 to <8 x i8>
+  %v2b = bitcast x86_mmx %v2 to <8 x i8>
+  %tmp3 = add <8 x i8> %v1a, %v2b
+  %tmp3a = bitcast <8 x i8> %tmp3 to x86_mmx
+  %tmp4 = tail call i32 (...) @pass_v8qi( x86_mmx %tmp3a ) nounwind
+  ret void
+}
+
+define void @t5() nounwind  {
+; X86-64-LABEL: t5:
+; X86-64:       ## BB#0:
+; X86-64-NEXT:    pushq %rax
+; X86-64-NEXT:    xorl %edi, %edi
+; X86-64-NEXT:    callq _pass_v1di
+; X86-64-NEXT:    popq %rax
+; X86-64-NEXT:    retq
+  call void @pass_v1di( <1 x i64> zeroinitializer )
+  ret void
+}
+
+declare i32 @pass_v8qi(...)
+declare void @pass_v1di(<1 x i64>)
diff --git a/test/CodeGen/X86/mmx-arg-passing.ll b/test/CodeGen/X86/mmx-arg-passing.ll
index 3a0fb95711e5..4e0031076200 100644
--- a/test/CodeGen/X86/mmx-arg-passing.ll
+++ b/test/CodeGen/X86/mmx-arg-passing.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | FileCheck %s -check-prefix=X86-32
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | FileCheck %s -check-prefix=X86-64
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | FileCheck %s --check-prefix=X86-32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X86-64
 ;
 ; On Darwin x86-32, v8i8, v4i16, v2i32 values are passed in MM[0-2].
 ; On Darwin x86-32, v1i64 values are passed in memory.  In this example, they
@@ -10,29 +10,40 @@
 @u1 = external global x86_mmx
 
 define void @t1(x86_mmx %v1) nounwind  {
-	store x86_mmx %v1, x86_mmx* @u1, align 8
-	ret void
-
 ; X86-32-LABEL: t1:
-; X86-32: movq %mm0
-
+; X86-32:       ## BB#0:
+; X86-32-NEXT:    movl L_u1$non_lazy_ptr, %eax
+; X86-32-NEXT:    movq %mm0, (%eax)
+; X86-32-NEXT:    retl
+;
 ; X86-64-LABEL: t1:
-; X86-64: movdq2q %xmm0
-; X86-64: movq %mm0
+; X86-64:       ## BB#0:
+; X86-64-NEXT:    movdq2q %xmm0, %mm0
+; X86-64-NEXT:    movq _u1@{{.*}}(%rip), %rax
+; X86-64-NEXT:    movq %mm0, (%rax)
+; X86-64-NEXT:    retq
+	store x86_mmx %v1, x86_mmx* @u1, align 8
+	ret void
 }
 
 @u2 = external global x86_mmx
 
 define void @t2(<1 x i64> %v1) nounwind  {
+; X86-32-LABEL: t2:
+; X86-32:       ## BB#0:
+; X86-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-32-NEXT:    movl L_u2$non_lazy_ptr, %edx
+; X86-32-NEXT:    movl %ecx, 4(%edx)
+; X86-32-NEXT:    movl %eax, (%edx)
+; X86-32-NEXT:    retl
+;
+; X86-64-LABEL: t2:
+; X86-64:       ## BB#0:
+; X86-64-NEXT:    movq _u2@{{.*}}(%rip), %rax
+; X86-64-NEXT:    movq %rdi, (%rax)
+; X86-64-NEXT:    retq
         %tmp = bitcast <1 x i64> %v1 to x86_mmx
 	store x86_mmx %tmp, x86_mmx* @u2, align 8
 	ret void
-
-; X86-32-LABEL: t2:
-; X86-32: movl 4(%esp)
-; X86-32: movl 8(%esp)
-
-; X86-64-LABEL: t2:
-; X86-64: movq %rdi
 }
-
diff --git a/test/CodeGen/X86/mmx-arg-passing2.ll b/test/CodeGen/X86/mmx-arg-passing2.ll
deleted file mode 100644
index c132d311b94b..000000000000
--- a/test/CodeGen/X86/mmx-arg-passing2.ll
+++ /dev/null
@@ -1,28 +0,0 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep movdq2q | count 2
-; Since the add is not an MMX add, we don't have a movq2dq any more.
-
-@g_v8qi = external global <8 x i8>
-
-define void @t1() nounwind  {
-	%tmp3 = load <8 x i8>* @g_v8qi, align 8
-        %tmp3a = bitcast <8 x i8> %tmp3 to x86_mmx
-	%tmp4 = tail call i32 (...)* @pass_v8qi( x86_mmx %tmp3a ) nounwind
-	ret void
-}
-
-define void @t2(x86_mmx %v1, x86_mmx %v2) nounwind  {
-       %v1a = bitcast x86_mmx %v1 to <8 x i8>
-       %v2b = bitcast x86_mmx %v2 to <8 x i8>
-       %tmp3 = add <8 x i8> %v1a, %v2b
-       %tmp3a = bitcast <8 x i8> %tmp3 to x86_mmx
-       %tmp4 = tail call i32 (...)* @pass_v8qi( x86_mmx %tmp3a ) nounwind
-       ret void
-}
-
-define void @t3() nounwind  {
-	call void @pass_v1di( <1 x i64> zeroinitializer )
-        ret void
-}
-
-declare i32 @pass_v8qi(...)
-declare void @pass_v1di(<1 x i64>)
diff --git a/test/CodeGen/X86/mmx-arith.ll b/test/CodeGen/X86/mmx-arith.ll
index 681748732401..114d2535d603 100644
--- a/test/CodeGen/X86/mmx-arith.ll
+++ b/test/CodeGen/X86/mmx-arith.ll
@@ -1,309 +1,308 @@
-; RUN: llc < %s -march=x86 -mattr=+mmx
+; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 | FileCheck -check-prefix=X32 %s
+; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | FileCheck -check-prefix=X64 %s
 
 ;; A basic sanity check to make sure that MMX arithmetic actually compiles.
 ;; First is a straight translation of the original with bitcasts as needed.
 
-define void @foo(x86_mmx* %A, x86_mmx* %B) {
+; X32-LABEL: test0
+; X64-LABEL: test0
+define void @test0(x86_mmx* %A, x86_mmx* %B) {
 entry:
-	%tmp1 = load x86_mmx* %A		; <x86_mmx> [#uses=1]
-	%tmp3 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp1a = bitcast x86_mmx %tmp1 to <8 x i8>
-        %tmp3a = bitcast x86_mmx %tmp3 to <8 x i8>
-	%tmp4 = add <8 x i8> %tmp1a, %tmp3a		; <<8 x i8>> [#uses=2]
-        %tmp4a = bitcast <8 x i8> %tmp4 to x86_mmx
-	store x86_mmx %tmp4a, x86_mmx* %A
-	%tmp7 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp12 = tail call x86_mmx @llvm.x86.mmx.padds.b( x86_mmx %tmp4a, x86_mmx %tmp7 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp12, x86_mmx* %A
-	%tmp16 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp21 = tail call x86_mmx @llvm.x86.mmx.paddus.b( x86_mmx %tmp12, x86_mmx %tmp16 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp21, x86_mmx* %A
-	%tmp27 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp21a = bitcast x86_mmx %tmp21 to <8 x i8>
-        %tmp27a = bitcast x86_mmx %tmp27 to <8 x i8>
-	%tmp28 = sub <8 x i8> %tmp21a, %tmp27a		; <<8 x i8>> [#uses=2]
-        %tmp28a = bitcast <8 x i8> %tmp28 to x86_mmx
-	store x86_mmx %tmp28a, x86_mmx* %A
-	%tmp31 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp36 = tail call x86_mmx @llvm.x86.mmx.psubs.b( x86_mmx %tmp28a, x86_mmx %tmp31 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp36, x86_mmx* %A
-	%tmp40 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp45 = tail call x86_mmx @llvm.x86.mmx.psubus.b( x86_mmx %tmp36, x86_mmx %tmp40 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp45, x86_mmx* %A
-	%tmp51 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp45a = bitcast x86_mmx %tmp45 to <8 x i8>
-        %tmp51a = bitcast x86_mmx %tmp51 to <8 x i8>
-	%tmp52 = mul <8 x i8> %tmp45a, %tmp51a		; <<8 x i8>> [#uses=2]
-        %tmp52a = bitcast <8 x i8> %tmp52 to x86_mmx
-	store x86_mmx %tmp52a, x86_mmx* %A
-	%tmp57 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp57a = bitcast x86_mmx %tmp57 to <8 x i8>
-	%tmp58 = and <8 x i8> %tmp52, %tmp57a		; <<8 x i8>> [#uses=2]
-        %tmp58a = bitcast <8 x i8> %tmp58 to x86_mmx
-	store x86_mmx %tmp58a, x86_mmx* %A
-	%tmp63 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp63a = bitcast x86_mmx %tmp63 to <8 x i8>
-	%tmp64 = or <8 x i8> %tmp58, %tmp63a		; <<8 x i8>> [#uses=2]
-        %tmp64a = bitcast <8 x i8> %tmp64 to x86_mmx
-	store x86_mmx %tmp64a, x86_mmx* %A
-	%tmp69 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp69a = bitcast x86_mmx %tmp69 to <8 x i8>
-        %tmp64b = bitcast x86_mmx %tmp64a to <8 x i8>
-	%tmp70 = xor <8 x i8> %tmp64b, %tmp69a		; <<8 x i8>> [#uses=1]
-        %tmp70a = bitcast <8 x i8> %tmp70 to x86_mmx
-	store x86_mmx %tmp70a, x86_mmx* %A
-	tail call void @llvm.x86.mmx.emms( )
-	ret void
+  %tmp1 = load x86_mmx, x86_mmx* %A
+  %tmp3 = load x86_mmx, x86_mmx* %B
+  %tmp1a = bitcast x86_mmx %tmp1 to <8 x i8>
+  %tmp3a = bitcast x86_mmx %tmp3 to <8 x i8>
+  %tmp4 = add <8 x i8> %tmp1a, %tmp3a
+  %tmp4a = bitcast <8 x i8> %tmp4 to x86_mmx
+  store x86_mmx %tmp4a, x86_mmx* %A
+  %tmp7 = load x86_mmx, x86_mmx* %B
+  %tmp12 = tail call x86_mmx @llvm.x86.mmx.padds.b(x86_mmx %tmp4a, x86_mmx %tmp7)
+  store x86_mmx %tmp12, x86_mmx* %A
+  %tmp16 = load x86_mmx, x86_mmx* %B
+  %tmp21 = tail call x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx %tmp12, x86_mmx %tmp16)
+  store x86_mmx %tmp21, x86_mmx* %A
+  %tmp27 = load x86_mmx, x86_mmx* %B
+  %tmp21a = bitcast x86_mmx %tmp21 to <8 x i8>
+  %tmp27a = bitcast x86_mmx %tmp27 to <8 x i8>
+  %tmp28 = sub <8 x i8> %tmp21a, %tmp27a
+  %tmp28a = bitcast <8 x i8> %tmp28 to x86_mmx
+  store x86_mmx %tmp28a, x86_mmx* %A
+  %tmp31 = load x86_mmx, x86_mmx* %B
+  %tmp36 = tail call x86_mmx @llvm.x86.mmx.psubs.b(x86_mmx %tmp28a, x86_mmx %tmp31)
+  store x86_mmx %tmp36, x86_mmx* %A
+  %tmp40 = load x86_mmx, x86_mmx* %B
+  %tmp45 = tail call x86_mmx @llvm.x86.mmx.psubus.b(x86_mmx %tmp36, x86_mmx %tmp40)
+  store x86_mmx %tmp45, x86_mmx* %A
+  %tmp51 = load x86_mmx, x86_mmx* %B
+  %tmp45a = bitcast x86_mmx %tmp45 to <8 x i8>
+  %tmp51a = bitcast x86_mmx %tmp51 to <8 x i8>
+  %tmp52 = mul <8 x i8> %tmp45a, %tmp51a
+  %tmp52a = bitcast <8 x i8> %tmp52 to x86_mmx
+  store x86_mmx %tmp52a, x86_mmx* %A
+  %tmp57 = load x86_mmx, x86_mmx* %B
+  %tmp57a = bitcast x86_mmx %tmp57 to <8 x i8>
+  %tmp58 = and <8 x i8> %tmp52, %tmp57a
+  %tmp58a = bitcast <8 x i8> %tmp58 to x86_mmx
+  store x86_mmx %tmp58a, x86_mmx* %A
+  %tmp63 = load x86_mmx, x86_mmx* %B
+  %tmp63a = bitcast x86_mmx %tmp63 to <8 x i8>
+  %tmp64 = or <8 x i8> %tmp58, %tmp63a
+  %tmp64a = bitcast <8 x i8> %tmp64 to x86_mmx
+  store x86_mmx %tmp64a, x86_mmx* %A
+  %tmp69 = load x86_mmx, x86_mmx* %B
+  %tmp69a = bitcast x86_mmx %tmp69 to <8 x i8>
+  %tmp64b = bitcast x86_mmx %tmp64a to <8 x i8>
+  %tmp70 = xor <8 x i8> %tmp64b, %tmp69a
+  %tmp70a = bitcast <8 x i8> %tmp70 to x86_mmx
+  store x86_mmx %tmp70a, x86_mmx* %A
+  tail call void @llvm.x86.mmx.emms()
+  ret void
 }
 
-define void @baz(x86_mmx* %A, x86_mmx* %B) {
+; X32-LABEL: test1
+; X64-LABEL: test1
+define void @test1(x86_mmx* %A, x86_mmx* %B) {
 entry:
-	%tmp1 = load x86_mmx* %A		; <x86_mmx> [#uses=1]
-	%tmp3 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp1a = bitcast x86_mmx %tmp1 to <2 x i32>
-        %tmp3a = bitcast x86_mmx %tmp3 to <2 x i32>
-	%tmp4 = add <2 x i32> %tmp1a, %tmp3a		; <<2 x i32>> [#uses=2]
-        %tmp4a = bitcast <2 x i32> %tmp4 to x86_mmx
-	store x86_mmx %tmp4a, x86_mmx* %A
-	%tmp9 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp9a = bitcast x86_mmx %tmp9 to <2 x i32>
-	%tmp10 = sub <2 x i32> %tmp4, %tmp9a		; <<2 x i32>> [#uses=2]
-        %tmp10a = bitcast <2 x i32> %tmp4 to x86_mmx
-	store x86_mmx %tmp10a, x86_mmx* %A
-	%tmp15 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp10b = bitcast x86_mmx %tmp10a to <2 x i32>
-        %tmp15a = bitcast x86_mmx %tmp15 to <2 x i32>
-	%tmp16 = mul <2 x i32> %tmp10b, %tmp15a		; <<2 x i32>> [#uses=2]
-        %tmp16a = bitcast <2 x i32> %tmp16 to x86_mmx
-	store x86_mmx %tmp16a, x86_mmx* %A
-	%tmp21 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp16b = bitcast x86_mmx %tmp16a to <2 x i32>
-        %tmp21a = bitcast x86_mmx %tmp21 to <2 x i32>
-	%tmp22 = and <2 x i32> %tmp16b, %tmp21a		; <<2 x i32>> [#uses=2]
-        %tmp22a = bitcast <2 x i32> %tmp22 to x86_mmx
-	store x86_mmx %tmp22a, x86_mmx* %A
-	%tmp27 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp22b = bitcast x86_mmx %tmp22a to <2 x i32>
-        %tmp27a = bitcast x86_mmx %tmp27 to <2 x i32>
-	%tmp28 = or <2 x i32> %tmp22b, %tmp27a		; <<2 x i32>> [#uses=2]
-        %tmp28a = bitcast <2 x i32> %tmp28 to x86_mmx
-	store x86_mmx %tmp28a, x86_mmx* %A
-	%tmp33 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp28b = bitcast x86_mmx %tmp28a to <2 x i32>
-        %tmp33a = bitcast x86_mmx %tmp33 to <2 x i32>
-	%tmp34 = xor <2 x i32> %tmp28b, %tmp33a		; <<2 x i32>> [#uses=1]
-        %tmp34a = bitcast <2 x i32> %tmp34 to x86_mmx
-	store x86_mmx %tmp34a, x86_mmx* %A
-	tail call void @llvm.x86.mmx.emms( )
-	ret void
+  %tmp1 = load x86_mmx, x86_mmx* %A
+  %tmp3 = load x86_mmx, x86_mmx* %B
+  %tmp1a = bitcast x86_mmx %tmp1 to <2 x i32>
+  %tmp3a = bitcast x86_mmx %tmp3 to <2 x i32>
+  %tmp4 = add <2 x i32> %tmp1a, %tmp3a
+  %tmp4a = bitcast <2 x i32> %tmp4 to x86_mmx
+  store x86_mmx %tmp4a, x86_mmx* %A
+  %tmp9 = load x86_mmx, x86_mmx* %B
+  %tmp9a = bitcast x86_mmx %tmp9 to <2 x i32>
+  %tmp10 = sub <2 x i32> %tmp4, %tmp9a
+  %tmp10a = bitcast <2 x i32> %tmp4 to x86_mmx
+  store x86_mmx %tmp10a, x86_mmx* %A
+  %tmp15 = load x86_mmx, x86_mmx* %B
+  %tmp10b = bitcast x86_mmx %tmp10a to <2 x i32>
+  %tmp15a = bitcast x86_mmx %tmp15 to <2 x i32>
+  %tmp16 = mul <2 x i32> %tmp10b, %tmp15a
+  %tmp16a = bitcast <2 x i32> %tmp16 to x86_mmx
+  store x86_mmx %tmp16a, x86_mmx* %A
+  %tmp21 = load x86_mmx, x86_mmx* %B
+  %tmp16b = bitcast x86_mmx %tmp16a to <2 x i32>
+  %tmp21a = bitcast x86_mmx %tmp21 to <2 x i32>
+  %tmp22 = and <2 x i32> %tmp16b, %tmp21a
+  %tmp22a = bitcast <2 x i32> %tmp22 to x86_mmx
+  store x86_mmx %tmp22a, x86_mmx* %A
+  %tmp27 = load x86_mmx, x86_mmx* %B
+  %tmp22b = bitcast x86_mmx %tmp22a to <2 x i32>
+  %tmp27a = bitcast x86_mmx %tmp27 to <2 x i32>
+  %tmp28 = or <2 x i32> %tmp22b, %tmp27a
+  %tmp28a = bitcast <2 x i32> %tmp28 to x86_mmx
+  store x86_mmx %tmp28a, x86_mmx* %A
+  %tmp33 = load x86_mmx, x86_mmx* %B
+  %tmp28b = bitcast x86_mmx %tmp28a to <2 x i32>
+  %tmp33a = bitcast x86_mmx %tmp33 to <2 x i32>
+  %tmp34 = xor <2 x i32> %tmp28b, %tmp33a
+  %tmp34a = bitcast <2 x i32> %tmp34 to x86_mmx
+  store x86_mmx %tmp34a, x86_mmx* %A
+  tail call void @llvm.x86.mmx.emms( )
+  ret void
 }
 
-define void @bar(x86_mmx* %A, x86_mmx* %B) {
+; X32-LABEL: test2
+; X64-LABEL: test2
+define void @test2(x86_mmx* %A, x86_mmx* %B) {
 entry:
-	%tmp1 = load x86_mmx* %A		; <x86_mmx> [#uses=1]
-	%tmp3 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp1a = bitcast x86_mmx %tmp1 to <4 x i16>
-        %tmp3a = bitcast x86_mmx %tmp3 to <4 x i16>
-	%tmp4 = add <4 x i16> %tmp1a, %tmp3a		; <<4 x i16>> [#uses=2]
-        %tmp4a = bitcast <4 x i16> %tmp4 to x86_mmx
-	store x86_mmx %tmp4a, x86_mmx* %A
-	%tmp7 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp12 = tail call x86_mmx @llvm.x86.mmx.padds.w( x86_mmx %tmp4a, x86_mmx %tmp7 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp12, x86_mmx* %A
-	%tmp16 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp21 = tail call x86_mmx @llvm.x86.mmx.paddus.w( x86_mmx %tmp12, x86_mmx %tmp16 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp21, x86_mmx* %A
-	%tmp27 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp21a = bitcast x86_mmx %tmp21 to <4 x i16>
-        %tmp27a = bitcast x86_mmx %tmp27 to <4 x i16>
-	%tmp28 = sub <4 x i16> %tmp21a, %tmp27a		; <<4 x i16>> [#uses=2]
-        %tmp28a = bitcast <4 x i16> %tmp28 to x86_mmx
-	store x86_mmx %tmp28a, x86_mmx* %A
-	%tmp31 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp36 = tail call x86_mmx @llvm.x86.mmx.psubs.w( x86_mmx %tmp28a, x86_mmx %tmp31 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp36, x86_mmx* %A
-	%tmp40 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp45 = tail call x86_mmx @llvm.x86.mmx.psubus.w( x86_mmx %tmp36, x86_mmx %tmp40 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp45, x86_mmx* %A
-	%tmp51 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp45a = bitcast x86_mmx %tmp45 to <4 x i16>
-        %tmp51a = bitcast x86_mmx %tmp51 to <4 x i16>
-	%tmp52 = mul <4 x i16> %tmp45a, %tmp51a		; <<4 x i16>> [#uses=2]
-        %tmp52a = bitcast <4 x i16> %tmp52 to x86_mmx
-	store x86_mmx %tmp52a, x86_mmx* %A
-	%tmp55 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp60 = tail call x86_mmx @llvm.x86.mmx.pmulh.w( x86_mmx %tmp52a, x86_mmx %tmp55 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp60, x86_mmx* %A
-	%tmp64 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp69 = tail call x86_mmx @llvm.x86.mmx.pmadd.wd( x86_mmx %tmp60, x86_mmx %tmp64 )		; <x86_mmx> [#uses=1]
-	%tmp70 = bitcast x86_mmx %tmp69 to x86_mmx		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp70, x86_mmx* %A
-	%tmp75 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp70a = bitcast x86_mmx %tmp70 to <4 x i16>
-        %tmp75a = bitcast x86_mmx %tmp75 to <4 x i16>
-	%tmp76 = and <4 x i16> %tmp70a, %tmp75a		; <<4 x i16>> [#uses=2]
-        %tmp76a = bitcast <4 x i16> %tmp76 to x86_mmx
-	store x86_mmx %tmp76a, x86_mmx* %A
-	%tmp81 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp76b = bitcast x86_mmx %tmp76a to <4 x i16>
-        %tmp81a = bitcast x86_mmx %tmp81 to <4 x i16>
-	%tmp82 = or <4 x i16> %tmp76b, %tmp81a		; <<4 x i16>> [#uses=2]
-        %tmp82a = bitcast <4 x i16> %tmp82 to x86_mmx
-	store x86_mmx %tmp82a, x86_mmx* %A
-	%tmp87 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp82b = bitcast x86_mmx %tmp82a to <4 x i16>
-        %tmp87a = bitcast x86_mmx %tmp87 to <4 x i16>
-	%tmp88 = xor <4 x i16> %tmp82b, %tmp87a		; <<4 x i16>> [#uses=1]
-        %tmp88a = bitcast <4 x i16> %tmp88 to x86_mmx
-	store x86_mmx %tmp88a, x86_mmx* %A
-	tail call void @llvm.x86.mmx.emms( )
-	ret void
+  %tmp1 = load x86_mmx, x86_mmx* %A
+  %tmp3 = load x86_mmx, x86_mmx* %B
+  %tmp1a = bitcast x86_mmx %tmp1 to <4 x i16>
+  %tmp3a = bitcast x86_mmx %tmp3 to <4 x i16>
+  %tmp4 = add <4 x i16> %tmp1a, %tmp3a
+  %tmp4a = bitcast <4 x i16> %tmp4 to x86_mmx
+  store x86_mmx %tmp4a, x86_mmx* %A
+  %tmp7 = load x86_mmx, x86_mmx* %B
+  %tmp12 = tail call x86_mmx @llvm.x86.mmx.padds.w(x86_mmx %tmp4a, x86_mmx %tmp7)
+  store x86_mmx %tmp12, x86_mmx* %A
+  %tmp16 = load x86_mmx, x86_mmx* %B
+  %tmp21 = tail call x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx %tmp12, x86_mmx %tmp16)
+  store x86_mmx %tmp21, x86_mmx* %A
+  %tmp27 = load x86_mmx, x86_mmx* %B
+  %tmp21a = bitcast x86_mmx %tmp21 to <4 x i16>
+  %tmp27a = bitcast x86_mmx %tmp27 to <4 x i16>
+  %tmp28 = sub <4 x i16> %tmp21a, %tmp27a
+  %tmp28a = bitcast <4 x i16> %tmp28 to x86_mmx
+  store x86_mmx %tmp28a, x86_mmx* %A
+  %tmp31 = load x86_mmx, x86_mmx* %B
+  %tmp36 = tail call x86_mmx @llvm.x86.mmx.psubs.w(x86_mmx %tmp28a, x86_mmx %tmp31)
+  store x86_mmx %tmp36, x86_mmx* %A
+  %tmp40 = load x86_mmx, x86_mmx* %B
+  %tmp45 = tail call x86_mmx @llvm.x86.mmx.psubus.w(x86_mmx %tmp36, x86_mmx %tmp40)
+  store x86_mmx %tmp45, x86_mmx* %A
+  %tmp51 = load x86_mmx, x86_mmx* %B
+  %tmp45a = bitcast x86_mmx %tmp45 to <4 x i16>
+  %tmp51a = bitcast x86_mmx %tmp51 to <4 x i16>
+  %tmp52 = mul <4 x i16> %tmp45a, %tmp51a
+  %tmp52a = bitcast <4 x i16> %tmp52 to x86_mmx
+  store x86_mmx %tmp52a, x86_mmx* %A
+  %tmp55 = load x86_mmx, x86_mmx* %B
+  %tmp60 = tail call x86_mmx @llvm.x86.mmx.pmulh.w(x86_mmx %tmp52a, x86_mmx %tmp55)
+  store x86_mmx %tmp60, x86_mmx* %A
+  %tmp64 = load x86_mmx, x86_mmx* %B
+  %tmp69 = tail call x86_mmx @llvm.x86.mmx.pmadd.wd(x86_mmx %tmp60, x86_mmx %tmp64)
+  %tmp70 = bitcast x86_mmx %tmp69 to x86_mmx
+  store x86_mmx %tmp70, x86_mmx* %A
+  %tmp75 = load x86_mmx, x86_mmx* %B
+  %tmp70a = bitcast x86_mmx %tmp70 to <4 x i16>
+  %tmp75a = bitcast x86_mmx %tmp75 to <4 x i16>
+  %tmp76 = and <4 x i16> %tmp70a, %tmp75a
+  %tmp76a = bitcast <4 x i16> %tmp76 to x86_mmx
+  store x86_mmx %tmp76a, x86_mmx* %A
+  %tmp81 = load x86_mmx, x86_mmx* %B
+  %tmp76b = bitcast x86_mmx %tmp76a to <4 x i16>
+  %tmp81a = bitcast x86_mmx %tmp81 to <4 x i16>
+  %tmp82 = or <4 x i16> %tmp76b, %tmp81a
+  %tmp82a = bitcast <4 x i16> %tmp82 to x86_mmx
+  store x86_mmx %tmp82a, x86_mmx* %A
+  %tmp87 = load x86_mmx, x86_mmx* %B
+  %tmp82b = bitcast x86_mmx %tmp82a to <4 x i16>
+  %tmp87a = bitcast x86_mmx %tmp87 to <4 x i16>
+  %tmp88 = xor <4 x i16> %tmp82b, %tmp87a
+  %tmp88a = bitcast <4 x i16> %tmp88 to x86_mmx
+  store x86_mmx %tmp88a, x86_mmx* %A
+  tail call void @llvm.x86.mmx.emms( )
+  ret void
 }
 
-;; The following is modified to use MMX intrinsics everywhere they work.
+; X32-LABEL: test3
+define <1 x i64> @test3(<1 x i64>* %a, <1 x i64>* %b, i32 %count) nounwind {
+entry:
+  %tmp2942 = icmp eq i32 %count, 0
+  br i1 %tmp2942, label %bb31, label %bb26
+
+bb26:
+; X32:  addl
+; X32:  adcl
+  %i.037.0 = phi i32 [ 0, %entry ], [ %tmp25, %bb26 ]
+  %sum.035.0 = phi <1 x i64> [ zeroinitializer, %entry ], [ %tmp22, %bb26 ]
+  %tmp13 = getelementptr <1 x i64>, <1 x i64>* %b, i32 %i.037.0
+  %tmp14 = load <1 x i64>, <1 x i64>* %tmp13
+  %tmp18 = getelementptr <1 x i64>, <1 x i64>* %a, i32 %i.037.0
+  %tmp19 = load <1 x i64>, <1 x i64>* %tmp18
+  %tmp21 = add <1 x i64> %tmp19, %tmp14
+  %tmp22 = add <1 x i64> %tmp21, %sum.035.0
+  %tmp25 = add i32 %i.037.0, 1
+  %tmp29 = icmp ult i32 %tmp25, %count
+  br i1 %tmp29, label %bb26, label %bb31
+
+bb31:
+  %sum.035.1 = phi <1 x i64> [ zeroinitializer, %entry ], [ %tmp22, %bb26 ]
+  ret <1 x i64> %sum.035.1
+}
 
-define void @fooa(x86_mmx* %A, x86_mmx* %B) {
+; There are no MMX operations here, so we use XMM or i64.
+; X64-LABEL: ti8
+define void @ti8(double %a, double %b) nounwind {
 entry:
-	%tmp1 = load x86_mmx* %A		; <x86_mmx> [#uses=1]
-	%tmp3 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp4 = tail call x86_mmx @llvm.x86.mmx.padd.b( x86_mmx %tmp1, x86_mmx %tmp3 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp4, x86_mmx* %A
-	%tmp7 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp12 = tail call x86_mmx @llvm.x86.mmx.padds.b( x86_mmx %tmp4, x86_mmx %tmp7 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp12, x86_mmx* %A
-	%tmp16 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp21 = tail call x86_mmx @llvm.x86.mmx.paddus.b( x86_mmx %tmp12, x86_mmx %tmp16 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp21, x86_mmx* %A
-	%tmp27 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp28 = tail call x86_mmx @llvm.x86.mmx.psub.b( x86_mmx %tmp21, x86_mmx %tmp27 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp28, x86_mmx* %A
-	%tmp31 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp36 = tail call x86_mmx @llvm.x86.mmx.psubs.b( x86_mmx %tmp28, x86_mmx %tmp31 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp36, x86_mmx* %A
-	%tmp40 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp45 = tail call x86_mmx @llvm.x86.mmx.psubus.b( x86_mmx %tmp36, x86_mmx %tmp40 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp45, x86_mmx* %A
-	%tmp51 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp51a = bitcast x86_mmx %tmp51 to i64
-        %tmp51aa = bitcast i64 %tmp51a to <8 x i8>
-        %tmp51b = bitcast x86_mmx %tmp45 to <8 x i8>
-	%tmp52 = mul <8 x i8> %tmp51b, %tmp51aa		; <x86_mmx> [#uses=2]
-        %tmp52a = bitcast <8 x i8> %tmp52 to i64
-        %tmp52aa = bitcast i64 %tmp52a to x86_mmx
-	store x86_mmx %tmp52aa, x86_mmx* %A
-	%tmp57 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp58 = tail call x86_mmx @llvm.x86.mmx.pand( x86_mmx %tmp51, x86_mmx %tmp57 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp58, x86_mmx* %A
-	%tmp63 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp64 = tail call x86_mmx @llvm.x86.mmx.por( x86_mmx %tmp58, x86_mmx %tmp63 )		; <x86_mmx> [#uses=2]	
-	store x86_mmx %tmp64, x86_mmx* %A
-	%tmp69 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp70 = tail call x86_mmx @llvm.x86.mmx.pxor( x86_mmx %tmp64, x86_mmx %tmp69 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp70, x86_mmx* %A
-	tail call void @llvm.x86.mmx.emms( )
-	ret void
+  %tmp1 = bitcast double %a to <8 x i8>
+  %tmp2 = bitcast double %b to <8 x i8>
+  %tmp3 = add <8 x i8> %tmp1, %tmp2
+; X64:  paddb
+  store <8 x i8> %tmp3, <8 x i8>* null
+  ret void
 }
 
-define void @baza(x86_mmx* %A, x86_mmx* %B) {
+; X64-LABEL: ti16
+define void @ti16(double %a, double %b) nounwind {
 entry:
-	%tmp1 = load x86_mmx* %A		; <x86_mmx> [#uses=1]
-	%tmp3 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp4 = tail call x86_mmx @llvm.x86.mmx.padd.d( x86_mmx %tmp1, x86_mmx %tmp3 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp4, x86_mmx* %A
-	%tmp9 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp10 = tail call x86_mmx @llvm.x86.mmx.psub.d( x86_mmx %tmp4, x86_mmx %tmp9 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp10, x86_mmx* %A
-	%tmp15 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-        %tmp10a = bitcast x86_mmx %tmp10 to <2 x i32>
-        %tmp15a = bitcast x86_mmx %tmp15 to <2 x i32>
-	%tmp16 = mul <2 x i32> %tmp10a, %tmp15a		; <x86_mmx> [#uses=2]
-        %tmp16a = bitcast <2 x i32> %tmp16 to x86_mmx
-	store x86_mmx %tmp16a, x86_mmx* %A
-	%tmp21 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp22 = tail call x86_mmx @llvm.x86.mmx.pand( x86_mmx %tmp16a, x86_mmx %tmp21 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp22, x86_mmx* %A
-	%tmp27 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp28 = tail call x86_mmx @llvm.x86.mmx.por( x86_mmx %tmp22, x86_mmx %tmp27 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp28, x86_mmx* %A
-	%tmp33 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp34 = tail call x86_mmx @llvm.x86.mmx.pxor( x86_mmx %tmp28, x86_mmx %tmp33 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp34, x86_mmx* %A
-	tail call void @llvm.x86.mmx.emms( )
-	ret void
+  %tmp1 = bitcast double %a to <4 x i16>
+  %tmp2 = bitcast double %b to <4 x i16>
+  %tmp3 = add <4 x i16> %tmp1, %tmp2
+; X64:  paddw
+  store <4 x i16> %tmp3, <4 x i16>* null
+  ret void
 }
 
-define void @bara(x86_mmx* %A, x86_mmx* %B) {
+; X64-LABEL: ti32
+define void @ti32(double %a, double %b) nounwind {
 entry:
-	%tmp1 = load x86_mmx* %A		; <x86_mmx> [#uses=1]
-	%tmp3 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp4 = tail call x86_mmx @llvm.x86.mmx.padd.w( x86_mmx %tmp1, x86_mmx %tmp3 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp4, x86_mmx* %A
-	%tmp7 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp12 = tail call x86_mmx @llvm.x86.mmx.padds.w( x86_mmx %tmp4, x86_mmx %tmp7 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp12, x86_mmx* %A
-	%tmp16 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp21 = tail call x86_mmx @llvm.x86.mmx.paddus.w( x86_mmx %tmp12, x86_mmx %tmp16 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp21, x86_mmx* %A
-	%tmp27 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp28 = tail call x86_mmx @llvm.x86.mmx.psub.w( x86_mmx %tmp21, x86_mmx %tmp27 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp28, x86_mmx* %A
-	%tmp31 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp36 = tail call x86_mmx @llvm.x86.mmx.psubs.w( x86_mmx %tmp28, x86_mmx %tmp31 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp36, x86_mmx* %A
-	%tmp40 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp45 = tail call x86_mmx @llvm.x86.mmx.psubus.w( x86_mmx %tmp36, x86_mmx %tmp40 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp45, x86_mmx* %A
-	%tmp51 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp52 = tail call x86_mmx @llvm.x86.mmx.pmull.w( x86_mmx %tmp45, x86_mmx %tmp51 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp52, x86_mmx* %A
-	%tmp55 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp60 = tail call x86_mmx @llvm.x86.mmx.pmulh.w( x86_mmx %tmp52, x86_mmx %tmp55 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp60, x86_mmx* %A
-	%tmp64 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp69 = tail call x86_mmx @llvm.x86.mmx.pmadd.wd( x86_mmx %tmp60, x86_mmx %tmp64 )		; <x86_mmx> [#uses=1]
-	%tmp70 = bitcast x86_mmx %tmp69 to x86_mmx		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp70, x86_mmx* %A
-	%tmp75 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp76 = tail call x86_mmx @llvm.x86.mmx.pand( x86_mmx %tmp70, x86_mmx %tmp75 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp76, x86_mmx* %A
-	%tmp81 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp82 = tail call x86_mmx @llvm.x86.mmx.por( x86_mmx %tmp76, x86_mmx %tmp81 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp82, x86_mmx* %A
-	%tmp87 = load x86_mmx* %B		; <x86_mmx> [#uses=1]
-	%tmp88 = tail call x86_mmx @llvm.x86.mmx.pxor( x86_mmx %tmp82, x86_mmx %tmp87 )		; <x86_mmx> [#uses=2]
-	store x86_mmx %tmp88, x86_mmx* %A
-	tail call void @llvm.x86.mmx.emms( )
-	ret void
+  %tmp1 = bitcast double %a to <2 x i32>
+  %tmp2 = bitcast double %b to <2 x i32>
+  %tmp3 = add <2 x i32> %tmp1, %tmp2
+; X64:  paddd
+  store <2 x i32> %tmp3, <2 x i32>* null
+  ret void
 }
 
-declare x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx, x86_mmx)
+; X64-LABEL: ti64
+define void @ti64(double %a, double %b) nounwind {
+entry:
+  %tmp1 = bitcast double %a to <1 x i64>
+  %tmp2 = bitcast double %b to <1 x i64>
+  %tmp3 = add <1 x i64> %tmp1, %tmp2
+; X64:  addq
+  store <1 x i64> %tmp3, <1 x i64>* null
+  ret void
+}
 
-declare x86_mmx @llvm.x86.mmx.psubus.b(x86_mmx, x86_mmx)
+; MMX intrinsics calls get us MMX instructions.
+; X64-LABEL: ti8a
+define void @ti8a(double %a, double %b) nounwind {
+entry:
+  %tmp1 = bitcast double %a to x86_mmx
+; X64: movdq2q
+  %tmp2 = bitcast double %b to x86_mmx
+; X64: movdq2q
+  %tmp3 = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %tmp1, x86_mmx %tmp2)
+  store x86_mmx %tmp3, x86_mmx* null
+  ret void
+}
 
-declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx)
+; X64-LABEL: ti16a
+define void @ti16a(double %a, double %b) nounwind {
+entry:
+  %tmp1 = bitcast double %a to x86_mmx
+; X64: movdq2q
+  %tmp2 = bitcast double %b to x86_mmx
+; X64: movdq2q
+  %tmp3 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %tmp1, x86_mmx %tmp2)
+  store x86_mmx %tmp3, x86_mmx* null
+  ret void
+}
 
-declare x86_mmx @llvm.x86.mmx.psubus.w(x86_mmx, x86_mmx)
+; X64-LABEL: ti32a
+define void @ti32a(double %a, double %b) nounwind {
+entry:
+  %tmp1 = bitcast double %a to x86_mmx
+; X64: movdq2q
+  %tmp2 = bitcast double %b to x86_mmx
+; X64: movdq2q
+  %tmp3 = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %tmp1, x86_mmx %tmp2)
+  store x86_mmx %tmp3, x86_mmx* null
+  ret void
+}
 
-declare x86_mmx @llvm.x86.mmx.pmulh.w(x86_mmx, x86_mmx)
+; X64-LABEL: ti64a
+define void @ti64a(double %a, double %b) nounwind {
+entry:
+  %tmp1 = bitcast double %a to x86_mmx
+; X64: movdq2q
+  %tmp2 = bitcast double %b to x86_mmx
+; X64: movdq2q
+  %tmp3 = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %tmp1, x86_mmx %tmp2)
+  store x86_mmx %tmp3, x86_mmx* null
+  ret void
+}
+
+declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx)
+declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx)
+declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx)
+declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx)
 
+declare x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx, x86_mmx)
+declare x86_mmx @llvm.x86.mmx.psubus.b(x86_mmx, x86_mmx)
+declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx)
+declare x86_mmx @llvm.x86.mmx.psubus.w(x86_mmx, x86_mmx)
+declare x86_mmx @llvm.x86.mmx.pmulh.w(x86_mmx, x86_mmx)
 declare x86_mmx @llvm.x86.mmx.pmadd.wd(x86_mmx, x86_mmx)
 
 declare void @llvm.x86.mmx.emms()
 
-declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx)
 declare x86_mmx @llvm.x86.mmx.padds.b(x86_mmx, x86_mmx)
 declare x86_mmx @llvm.x86.mmx.padds.w(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.padds.d(x86_mmx, x86_mmx)
 declare x86_mmx @llvm.x86.mmx.psubs.b(x86_mmx, x86_mmx)
 declare x86_mmx @llvm.x86.mmx.psubs.w(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.psubs.d(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.psub.b(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.psub.w(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.psub.d(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.pand(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.por(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.pxor(x86_mmx, x86_mmx)
 
diff --git a/test/CodeGen/X86/mmx-bitcast-to-i64.ll b/test/CodeGen/X86/mmx-bitcast-to-i64.ll
deleted file mode 100644
index 8b1840abf615..000000000000
--- a/test/CodeGen/X86/mmx-bitcast-to-i64.ll
+++ /dev/null
@@ -1,31 +0,0 @@
-; RUN: llc < %s -march=x86-64 | grep movd | count 4
-
-define i64 @foo(x86_mmx* %p) {
-  %t = load x86_mmx* %p
-  %u = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %t, x86_mmx %t)
-  %s = bitcast x86_mmx %u to i64
-  ret i64 %s
-}
-define i64 @goo(x86_mmx* %p) {
-  %t = load x86_mmx* %p
-  %u = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %t, x86_mmx %t)
-  %s = bitcast x86_mmx %u to i64
-  ret i64 %s
-}
-define i64 @hoo(x86_mmx* %p) {
-  %t = load x86_mmx* %p
-  %u = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %t, x86_mmx %t)
-  %s = bitcast x86_mmx %u to i64
-  ret i64 %s
-}
-define i64 @ioo(x86_mmx* %p) {
-  %t = load x86_mmx* %p
-  %u = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %t, x86_mmx %t)
-  %s = bitcast x86_mmx %u to i64
-  ret i64 %s
-}
-
-declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx)
-declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx)
diff --git a/test/CodeGen/X86/mmx-bitcast.ll b/test/CodeGen/X86/mmx-bitcast.ll
new file mode 100644
index 000000000000..00c803917f75
--- /dev/null
+++ b/test/CodeGen/X86/mmx-bitcast.ll
@@ -0,0 +1,108 @@
+; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse2 | FileCheck %s
+
+define i64 @t0(x86_mmx* %p) {
+; CHECK-LABEL: t0:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    movq
+; CHECK-NEXT:    paddq %mm0, %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    retq
+  %t = load x86_mmx, x86_mmx* %p
+  %u = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %t, x86_mmx %t)
+  %s = bitcast x86_mmx %u to i64
+  ret i64 %s
+}
+
+define i64 @t1(x86_mmx* %p) {
+; CHECK-LABEL: t1:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    movq
+; CHECK-NEXT:    paddd %mm0, %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    retq
+  %t = load x86_mmx, x86_mmx* %p
+  %u = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %t, x86_mmx %t)
+  %s = bitcast x86_mmx %u to i64
+  ret i64 %s
+}
+
+define i64 @t2(x86_mmx* %p) {
+; CHECK-LABEL: t2:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    movq
+; CHECK-NEXT:    paddw %mm0, %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    retq
+  %t = load x86_mmx, x86_mmx* %p
+  %u = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %t, x86_mmx %t)
+  %s = bitcast x86_mmx %u to i64
+  ret i64 %s
+}
+
+define i64 @t3(x86_mmx* %p) {
+; CHECK-LABEL: t3:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    movq
+; CHECK-NEXT:    paddb %mm0, %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    retq
+  %t = load x86_mmx, x86_mmx* %p
+  %u = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %t, x86_mmx %t)
+  %s = bitcast x86_mmx %u to i64
+  ret i64 %s
+}
+
+@R = external global x86_mmx
+
+define void @t4(<1 x i64> %A, <1 x i64> %B) {
+; CHECK-LABEL: t4:
+; CHECK:       ## BB#0: ## %entry
+; CHECK-NEXT:    movd
+; CHECK-NEXT:    movd
+; CHECK:    retq
+entry:
+  %tmp2 = bitcast <1 x i64> %A to x86_mmx
+  %tmp3 = bitcast <1 x i64> %B to x86_mmx
+  %tmp7 = tail call x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx %tmp2, x86_mmx %tmp3)
+  store x86_mmx %tmp7, x86_mmx* @R
+  tail call void @llvm.x86.mmx.emms()
+  ret void
+}
+
+define i64 @t5(i32 %a, i32 %b) nounwind readnone {
+; CHECK-LABEL: t5:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    movd
+; CHECK-NEXT:    movd
+; CHECK-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; CHECK-NEXT:    movd %xmm1, %rax
+; CHECK-NEXT:    retq
+  %v0 = insertelement <2 x i32> undef, i32 %a, i32 0
+  %v1 = insertelement <2 x i32> %v0, i32 %b, i32 1
+  %conv = bitcast <2 x i32> %v1 to i64
+  ret i64 %conv
+}
+
+declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
+
+define <1 x i64> @t6(i64 %t) {
+; CHECK-LABEL: t6:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    movd
+; CHECK-NEXT:    psllq $48, %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    retq
+  %t1 = insertelement <1 x i64> undef, i64 %t, i32 0
+  %t0 = bitcast <1 x i64> %t1 to x86_mmx
+  %t2 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %t0, i32 48)
+  %t3 = bitcast x86_mmx %t2 to <1 x i64>
+  ret <1 x i64> %t3
+}
+
+declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx)
+declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx)
+declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx)
+declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx)
+declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx)
+declare void @llvm.x86.mmx.emms()
+
diff --git a/test/CodeGen/X86/mmx-builtins.ll b/test/CodeGen/X86/mmx-builtins.ll
deleted file mode 100644
index aabdd53b09d6..000000000000
--- a/test/CodeGen/X86/mmx-builtins.ll
+++ /dev/null
@@ -1,1349 +0,0 @@
-; RUN: llc < %s -march=x86 -mattr=+mmx,+ssse3,-avx | FileCheck %s
-; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s
-; RUN: llc < %s -march=x86-64 -mattr=+mmx,+ssse3,-avx | FileCheck %s
-; RUN: llc < %s -march=x86-64 -mattr=+avx | FileCheck %s
-
-declare x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test1(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: phaddw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %2 = bitcast <4 x i16> %1 to x86_mmx
-  %3 = bitcast <4 x i16> %0 to x86_mmx
-  %4 = tail call x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx %2, x86_mmx %3) nounwind readnone
-  %5 = bitcast x86_mmx %4 to <4 x i16>
-  %6 = bitcast <4 x i16> %5 to <1 x i64>
-  %7 = extractelement <1 x i64> %6, i32 0
-  ret i64 %7
-}
-
-declare x86_mmx @llvm.x86.mmx.pcmpgt.d(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test88(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pcmpgtd
-entry:
-  %0 = bitcast <1 x i64> %b to <2 x i32>
-  %1 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
-  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pcmpgt.d(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <2 x i32>
-  %4 = bitcast <2 x i32> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pcmpgt.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test87(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pcmpgtw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pcmpgt.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pcmpgt.b(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test86(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pcmpgtb
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
-  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pcmpgt.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pcmpeq.d(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test85(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pcmpeqd
-entry:
-  %0 = bitcast <1 x i64> %b to <2 x i32>
-  %1 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
-  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pcmpeq.d(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <2 x i32>
-  %4 = bitcast <2 x i32> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pcmpeq.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test84(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pcmpeqw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pcmpeq.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pcmpeq.b(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test83(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pcmpeqb
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
-  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pcmpeq.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.punpckldq(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test82(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: punpckldq
-entry:
-  %0 = bitcast <1 x i64> %b to <2 x i32>
-  %1 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
-  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.punpckldq(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <2 x i32>
-  %4 = bitcast <2 x i32> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.punpcklwd(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test81(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: punpcklwd
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.punpcklwd(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.punpcklbw(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test80(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: punpcklbw
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
-  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.punpcklbw(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.punpckhdq(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test79(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: punpckhdq
-entry:
-  %0 = bitcast <1 x i64> %b to <2 x i32>
-  %1 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
-  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.punpckhdq(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <2 x i32>
-  %4 = bitcast <2 x i32> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.punpckhwd(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test78(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: punpckhwd
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.punpckhwd(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.punpckhbw(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test77(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: punpckhbw
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
-  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.punpckhbw(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.packuswb(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test76(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: packuswb
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.packuswb(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.packssdw(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test75(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: packssdw
-entry:
-  %0 = bitcast <1 x i64> %b to <2 x i32>
-  %1 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
-  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.packssdw(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.packsswb(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test74(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: packsswb
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.packsswb(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.psrai.d(x86_mmx, i32) nounwind readnone
-
-define i64 @test73(<1 x i64> %a) nounwind readnone optsize ssp {
-; CHECK: psrad
-entry:
-  %0 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx
-  %1 = tail call x86_mmx @llvm.x86.mmx.psrai.d(x86_mmx %mmx_var.i, i32 3) nounwind
-  %2 = bitcast x86_mmx %1 to <2 x i32>
-  %3 = bitcast <2 x i32> %2 to <1 x i64>
-  %4 = extractelement <1 x i64> %3, i32 0
-  ret i64 %4
-}
-
-declare x86_mmx @llvm.x86.mmx.psrai.w(x86_mmx, i32) nounwind readnone
-
-define i64 @test72(<1 x i64> %a) nounwind readnone optsize ssp {
-; CHECK: psraw
-entry:
-  %0 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx
-  %1 = tail call x86_mmx @llvm.x86.mmx.psrai.w(x86_mmx %mmx_var.i, i32 3) nounwind
-  %2 = bitcast x86_mmx %1 to <4 x i16>
-  %3 = bitcast <4 x i16> %2 to <1 x i64>
-  %4 = extractelement <1 x i64> %3, i32 0
-  ret i64 %4
-}
-
-declare x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx, i32) nounwind readnone
-
-define i64 @test71(<1 x i64> %a) nounwind readnone optsize ssp {
-; CHECK: psrlq
-entry:
-  %0 = extractelement <1 x i64> %a, i32 0
-  %mmx_var.i = bitcast i64 %0 to x86_mmx
-  %1 = tail call x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx %mmx_var.i, i32 3) nounwind
-  %2 = bitcast x86_mmx %1 to i64
-  ret i64 %2
-}
-
-declare x86_mmx @llvm.x86.mmx.psrli.d(x86_mmx, i32) nounwind readnone
-
-define i64 @test70(<1 x i64> %a) nounwind readnone optsize ssp {
-; CHECK: psrld
-entry:
-  %0 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx
-  %1 = tail call x86_mmx @llvm.x86.mmx.psrli.d(x86_mmx %mmx_var.i, i32 3) nounwind
-  %2 = bitcast x86_mmx %1 to <2 x i32>
-  %3 = bitcast <2 x i32> %2 to <1 x i64>
-  %4 = extractelement <1 x i64> %3, i32 0
-  ret i64 %4
-}
-
-declare x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx, i32) nounwind readnone
-
-define i64 @test69(<1 x i64> %a) nounwind readnone optsize ssp {
-; CHECK: psrlw
-entry:
-  %0 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx
-  %1 = tail call x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx %mmx_var.i, i32 3) nounwind
-  %2 = bitcast x86_mmx %1 to <4 x i16>
-  %3 = bitcast <4 x i16> %2 to <1 x i64>
-  %4 = extractelement <1 x i64> %3, i32 0
-  ret i64 %4
-}
-
-declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32) nounwind readnone
-
-define i64 @test68(<1 x i64> %a) nounwind readnone optsize ssp {
-; CHECK: psllq
-entry:
-  %0 = extractelement <1 x i64> %a, i32 0
-  %mmx_var.i = bitcast i64 %0 to x86_mmx
-  %1 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %mmx_var.i, i32 3) nounwind
-  %2 = bitcast x86_mmx %1 to i64
-  ret i64 %2
-}
-
-declare x86_mmx @llvm.x86.mmx.pslli.d(x86_mmx, i32) nounwind readnone
-
-define i64 @test67(<1 x i64> %a) nounwind readnone optsize ssp {
-; CHECK: pslld
-entry:
-  %0 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx
-  %1 = tail call x86_mmx @llvm.x86.mmx.pslli.d(x86_mmx %mmx_var.i, i32 3) nounwind
-  %2 = bitcast x86_mmx %1 to <2 x i32>
-  %3 = bitcast <2 x i32> %2 to <1 x i64>
-  %4 = extractelement <1 x i64> %3, i32 0
-  ret i64 %4
-}
-
-declare x86_mmx @llvm.x86.mmx.pslli.w(x86_mmx, i32) nounwind readnone
-
-define i64 @test66(<1 x i64> %a) nounwind readnone optsize ssp {
-; CHECK: psllw
-entry:
-  %0 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx
-  %1 = tail call x86_mmx @llvm.x86.mmx.pslli.w(x86_mmx %mmx_var.i, i32 3) nounwind
-  %2 = bitcast x86_mmx %1 to <4 x i16>
-  %3 = bitcast <4 x i16> %2 to <1 x i64>
-  %4 = extractelement <1 x i64> %3, i32 0
-  ret i64 %4
-}
-
-declare x86_mmx @llvm.x86.mmx.psra.d(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test65(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psrad
-entry:
-  %0 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx
-  %1 = extractelement <1 x i64> %b, i32 0
-  %mmx_var1.i = bitcast i64 %1 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psra.d(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <2 x i32>
-  %4 = bitcast <2 x i32> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.psra.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test64(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psraw
-entry:
-  %0 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx
-  %1 = extractelement <1 x i64> %b, i32 0
-  %mmx_var1.i = bitcast i64 %1 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psra.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test63(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psrlq
-entry:
-  %0 = extractelement <1 x i64> %a, i32 0
-  %mmx_var.i = bitcast i64 %0 to x86_mmx
-  %1 = extractelement <1 x i64> %b, i32 0
-  %mmx_var1.i = bitcast i64 %1 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to i64
-  ret i64 %3
-}
-
-declare x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test62(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psrld
-entry:
-  %0 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx
-  %1 = extractelement <1 x i64> %b, i32 0
-  %mmx_var1.i = bitcast i64 %1 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <2 x i32>
-  %4 = bitcast <2 x i32> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test61(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psrlw
-entry:
-  %0 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx
-  %1 = extractelement <1 x i64> %b, i32 0
-  %mmx_var1.i = bitcast i64 %1 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.psll.q(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test60(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psllq
-entry:
-  %0 = extractelement <1 x i64> %a, i32 0
-  %mmx_var.i = bitcast i64 %0 to x86_mmx
-  %1 = extractelement <1 x i64> %b, i32 0
-  %mmx_var1.i = bitcast i64 %1 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psll.q(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to i64
-  ret i64 %3
-}
-
-declare x86_mmx @llvm.x86.mmx.psll.d(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test59(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pslld
-entry:
-  %0 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx
-  %1 = extractelement <1 x i64> %b, i32 0
-  %mmx_var1.i = bitcast i64 %1 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psll.d(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <2 x i32>
-  %4 = bitcast <2 x i32> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.psll.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test58(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psllw
-entry:
-  %0 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx
-  %1 = extractelement <1 x i64> %b, i32 0
-  %mmx_var1.i = bitcast i64 %1 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psll.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pxor(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test56(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pxor
-entry:
-  %0 = bitcast <1 x i64> %b to <2 x i32>
-  %1 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
-  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pxor(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <2 x i32>
-  %4 = bitcast <2 x i32> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.por(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test55(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: por
-entry:
-  %0 = bitcast <1 x i64> %b to <2 x i32>
-  %1 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
-  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.por(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <2 x i32>
-  %4 = bitcast <2 x i32> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pandn(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test54(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pandn
-entry:
-  %0 = bitcast <1 x i64> %b to <2 x i32>
-  %1 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
-  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pandn(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <2 x i32>
-  %4 = bitcast <2 x i32> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pand(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test53(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pand
-entry:
-  %0 = bitcast <1 x i64> %b to <2 x i32>
-  %1 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
-  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pand(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <2 x i32>
-  %4 = bitcast <2 x i32> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test52(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pmullw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-define i64 @test51(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pmullw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pmulh.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test50(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pmulhw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pmulh.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pmadd.wd(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test49(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pmaddwd
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pmadd.wd(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <2 x i32>
-  %4 = bitcast <2 x i32> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.psubus.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test48(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psubusw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psubus.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.psubus.b(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test47(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psubusb
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
-  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psubus.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.psubs.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test46(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psubsw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psubs.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.psubs.b(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test45(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psubsb
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
-  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psubs.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-define i64 @test44(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psubq
-entry:
-  %0 = extractelement <1 x i64> %a, i32 0
-  %mmx_var = bitcast i64 %0 to x86_mmx
-  %1 = extractelement <1 x i64> %b, i32 0
-  %mmx_var1 = bitcast i64 %1 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psub.q(x86_mmx %mmx_var, x86_mmx %mmx_var1)
-  %3 = bitcast x86_mmx %2 to i64
-  ret i64 %3
-}
-
-declare x86_mmx @llvm.x86.mmx.psub.q(x86_mmx, x86_mmx) nounwind readnone
-
-declare x86_mmx @llvm.x86.mmx.psub.d(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test43(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psubd
-entry:
-  %0 = bitcast <1 x i64> %b to <2 x i32>
-  %1 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
-  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psub.d(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <2 x i32>
-  %4 = bitcast <2 x i32> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.psub.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test42(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psubw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psub.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.psub.b(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test41(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psubb
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
-  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psub.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test40(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: paddusw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test39(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: paddusb
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
-  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.padds.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test38(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: paddsw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.padds.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.padds.b(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test37(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: paddsb
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
-  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.padds.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test36(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: paddq
-entry:
-  %0 = extractelement <1 x i64> %a, i32 0
-  %mmx_var = bitcast i64 %0 to x86_mmx
-  %1 = extractelement <1 x i64> %b, i32 0
-  %mmx_var1 = bitcast i64 %1 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %mmx_var, x86_mmx %mmx_var1)
-  %3 = bitcast x86_mmx %2 to i64
-  ret i64 %3
-}
-
-declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test35(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: paddd
-entry:
-  %0 = bitcast <1 x i64> %b to <2 x i32>
-  %1 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
-  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <2 x i32>
-  %4 = bitcast <2 x i32> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test34(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: paddw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test33(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: paddb
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
-  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.psad.bw(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test32(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psadbw
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
-  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.psad.bw(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to i64
-  ret i64 %3
-}
-
-declare x86_mmx @llvm.x86.mmx.pmins.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test31(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pminsw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pmins.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pminu.b(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test30(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pminub
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
-  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pminu.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pmaxs.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test29(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pmaxsw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pmaxs.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pmaxu.b(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test28(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pmaxub
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
-  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pmaxu.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pavg.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test27(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pavgw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pavg.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pavg.b(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test26(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pavgb
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
-  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pavg.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare void @llvm.x86.mmx.movnt.dq(x86_mmx*, x86_mmx) nounwind
-
-define void @test25(<1 x i64>* %p, <1 x i64> %a) nounwind optsize ssp {
-; CHECK: movntq
-entry:
-  %mmx_ptr_var.i = bitcast <1 x i64>* %p to x86_mmx*
-  %0 = extractelement <1 x i64> %a, i32 0
-  %mmx_var.i = bitcast i64 %0 to x86_mmx
-  tail call void @llvm.x86.mmx.movnt.dq(x86_mmx* %mmx_ptr_var.i, x86_mmx %mmx_var.i) nounwind
-  ret void
-}
-
-declare i32 @llvm.x86.mmx.pmovmskb(x86_mmx) nounwind readnone
-
-define i32 @test24(<1 x i64> %a) nounwind readnone optsize ssp {
-; CHECK: pmovmskb
-entry:
-  %0 = bitcast <1 x i64> %a to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %0 to x86_mmx
-  %1 = tail call i32 @llvm.x86.mmx.pmovmskb(x86_mmx %mmx_var.i) nounwind
-  ret i32 %1
-}
-
-declare void @llvm.x86.mmx.maskmovq(x86_mmx, x86_mmx, i8*) nounwind
-
-define void @test23(<1 x i64> %d, <1 x i64> %n, i8* %p) nounwind optsize ssp {
-; CHECK: maskmovq
-entry:
-  %0 = bitcast <1 x i64> %n to <8 x i8>
-  %1 = bitcast <1 x i64> %d to <8 x i8>
-  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
-  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
-  tail call void @llvm.x86.mmx.maskmovq(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i, i8* %p) nounwind
-  ret void
-}
-
-declare x86_mmx @llvm.x86.mmx.pmulhu.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test22(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pmulhuw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
-  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pmulhu.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8) nounwind readnone
-
-define i64 @test21(<1 x i64> %a) nounwind readnone optsize ssp {
-; CHECK: pshufw
-entry:
-  %0 = bitcast <1 x i64> %a to <4 x i16>
-  %1 = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 3) nounwind readnone
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-define i32 @test21_2(<1 x i64> %a) nounwind readnone optsize ssp {
-; CHECK: test21_2
-; CHECK: pshufw
-; CHECK: movd
-entry:
-  %0 = bitcast <1 x i64> %a to <4 x i16>
-  %1 = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 3) nounwind readnone
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <2 x i32>
-  %5 = extractelement <2 x i32> %4, i32 0
-  ret i32 %5
-}
-
-declare x86_mmx @llvm.x86.mmx.pmulu.dq(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test20(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pmuludq
-entry:
-  %0 = bitcast <1 x i64> %b to <2 x i32>
-  %1 = bitcast <1 x i64> %a to <2 x i32>
-  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
-  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.pmulu.dq(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
-  %3 = bitcast x86_mmx %2 to i64
-  ret i64 %3
-}
-
-declare <2 x double> @llvm.x86.sse.cvtpi2pd(x86_mmx) nounwind readnone
-
-define <2 x double> @test19(<1 x i64> %a) nounwind readnone optsize ssp {
-; CHECK: cvtpi2pd
-entry:
-  %0 = bitcast <1 x i64> %a to <2 x i32>
-  %1 = bitcast <2 x i32> %0 to x86_mmx
-  %2 = tail call <2 x double> @llvm.x86.sse.cvtpi2pd(x86_mmx %1) nounwind readnone
-  ret <2 x double> %2
-}
-
-declare x86_mmx @llvm.x86.sse.cvttpd2pi(<2 x double>) nounwind readnone
-
-define i64 @test18(<2 x double> %a) nounwind readnone optsize ssp {
-; CHECK: cvttpd2pi
-entry:
-  %0 = tail call x86_mmx @llvm.x86.sse.cvttpd2pi(<2 x double> %a) nounwind readnone
-  %1 = bitcast x86_mmx %0 to <2 x i32>
-  %2 = bitcast <2 x i32> %1 to <1 x i64>
-  %3 = extractelement <1 x i64> %2, i32 0
-  ret i64 %3
-}
-
-declare x86_mmx @llvm.x86.sse.cvtpd2pi(<2 x double>) nounwind readnone
-
-define i64 @test17(<2 x double> %a) nounwind readnone optsize ssp {
-; CHECK: cvtpd2pi
-entry:
-  %0 = tail call x86_mmx @llvm.x86.sse.cvtpd2pi(<2 x double> %a) nounwind readnone
-  %1 = bitcast x86_mmx %0 to <2 x i32>
-  %2 = bitcast <2 x i32> %1 to <1 x i64>
-  %3 = extractelement <1 x i64> %2, i32 0
-  ret i64 %3
-}
-
-declare x86_mmx @llvm.x86.mmx.palignr.b(x86_mmx, x86_mmx, i8) nounwind readnone
-
-define i64 @test16(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: palignr
-entry:
-  %0 = extractelement <1 x i64> %a, i32 0
-  %mmx_var = bitcast i64 %0 to x86_mmx
-  %1 = extractelement <1 x i64> %b, i32 0
-  %mmx_var1 = bitcast i64 %1 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.mmx.palignr.b(x86_mmx %mmx_var, x86_mmx %mmx_var1, i8 16)
-  %3 = bitcast x86_mmx %2 to i64
-  ret i64 %3
-}
-
-declare x86_mmx @llvm.x86.ssse3.pabs.d(x86_mmx) nounwind readnone
-
-define i64 @test15(<1 x i64> %a) nounwind readnone optsize ssp {
-; CHECK: pabsd
-entry:
-  %0 = bitcast <1 x i64> %a to <2 x i32>
-  %1 = bitcast <2 x i32> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.ssse3.pabs.d(x86_mmx %1) nounwind readnone
-  %3 = bitcast x86_mmx %2 to <2 x i32>
-  %4 = bitcast <2 x i32> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.ssse3.pabs.w(x86_mmx) nounwind readnone
-
-define i64 @test14(<1 x i64> %a) nounwind readnone optsize ssp {
-; CHECK: pabsw
-entry:
-  %0 = bitcast <1 x i64> %a to <4 x i16>
-  %1 = bitcast <4 x i16> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.ssse3.pabs.w(x86_mmx %1) nounwind readnone
-  %3 = bitcast x86_mmx %2 to <4 x i16>
-  %4 = bitcast <4 x i16> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.ssse3.pabs.b(x86_mmx) nounwind readnone
-
-define i64 @test13(<1 x i64> %a) nounwind readnone optsize ssp {
-; CHECK: pabsb
-entry:
-  %0 = bitcast <1 x i64> %a to <8 x i8>
-  %1 = bitcast <8 x i8> %0 to x86_mmx
-  %2 = tail call x86_mmx @llvm.x86.ssse3.pabs.b(x86_mmx %1) nounwind readnone
-  %3 = bitcast x86_mmx %2 to <8 x i8>
-  %4 = bitcast <8 x i8> %3 to <1 x i64>
-  %5 = extractelement <1 x i64> %4, i32 0
-  ret i64 %5
-}
-
-declare x86_mmx @llvm.x86.ssse3.psign.d(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test12(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psignd
-entry:
-  %0 = bitcast <1 x i64> %b to <2 x i32>
-  %1 = bitcast <1 x i64> %a to <2 x i32>
-  %2 = bitcast <2 x i32> %1 to x86_mmx
-  %3 = bitcast <2 x i32> %0 to x86_mmx
-  %4 = tail call x86_mmx @llvm.x86.ssse3.psign.d(x86_mmx %2, x86_mmx %3) nounwind readnone
-  %5 = bitcast x86_mmx %4 to <2 x i32>
-  %6 = bitcast <2 x i32> %5 to <1 x i64>
-  %7 = extractelement <1 x i64> %6, i32 0
-  ret i64 %7
-}
-
-declare x86_mmx @llvm.x86.ssse3.psign.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test11(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psignw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %2 = bitcast <4 x i16> %1 to x86_mmx
-  %3 = bitcast <4 x i16> %0 to x86_mmx
-  %4 = tail call x86_mmx @llvm.x86.ssse3.psign.w(x86_mmx %2, x86_mmx %3) nounwind readnone
-  %5 = bitcast x86_mmx %4 to <4 x i16>
-  %6 = bitcast <4 x i16> %5 to <1 x i64>
-  %7 = extractelement <1 x i64> %6, i32 0
-  ret i64 %7
-}
-
-declare x86_mmx @llvm.x86.ssse3.psign.b(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test10(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: psignb
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %2 = bitcast <8 x i8> %1 to x86_mmx
-  %3 = bitcast <8 x i8> %0 to x86_mmx
-  %4 = tail call x86_mmx @llvm.x86.ssse3.psign.b(x86_mmx %2, x86_mmx %3) nounwind readnone
-  %5 = bitcast x86_mmx %4 to <8 x i8>
-  %6 = bitcast <8 x i8> %5 to <1 x i64>
-  %7 = extractelement <1 x i64> %6, i32 0
-  ret i64 %7
-}
-
-declare x86_mmx @llvm.x86.ssse3.pshuf.b(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test9(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pshufb
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %2 = bitcast <8 x i8> %1 to x86_mmx
-  %3 = bitcast <8 x i8> %0 to x86_mmx
-  %4 = tail call x86_mmx @llvm.x86.ssse3.pshuf.b(x86_mmx %2, x86_mmx %3) nounwind readnone
-  %5 = bitcast x86_mmx %4 to <8 x i8>
-  %6 = bitcast <8 x i8> %5 to <1 x i64>
-  %7 = extractelement <1 x i64> %6, i32 0
-  ret i64 %7
-}
-
-declare x86_mmx @llvm.x86.ssse3.pmul.hr.sw(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test8(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pmulhrsw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %2 = bitcast <4 x i16> %1 to x86_mmx
-  %3 = bitcast <4 x i16> %0 to x86_mmx
-  %4 = tail call x86_mmx @llvm.x86.ssse3.pmul.hr.sw(x86_mmx %2, x86_mmx %3) nounwind readnone
-  %5 = bitcast x86_mmx %4 to <4 x i16>
-  %6 = bitcast <4 x i16> %5 to <1 x i64>
-  %7 = extractelement <1 x i64> %6, i32 0
-  ret i64 %7
-}
-
-declare x86_mmx @llvm.x86.ssse3.pmadd.ub.sw(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test7(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: pmaddubsw
-entry:
-  %0 = bitcast <1 x i64> %b to <8 x i8>
-  %1 = bitcast <1 x i64> %a to <8 x i8>
-  %2 = bitcast <8 x i8> %1 to x86_mmx
-  %3 = bitcast <8 x i8> %0 to x86_mmx
-  %4 = tail call x86_mmx @llvm.x86.ssse3.pmadd.ub.sw(x86_mmx %2, x86_mmx %3) nounwind readnone
-  %5 = bitcast x86_mmx %4 to <8 x i8>
-  %6 = bitcast <8 x i8> %5 to <1 x i64>
-  %7 = extractelement <1 x i64> %6, i32 0
-  ret i64 %7
-}
-
-declare x86_mmx @llvm.x86.ssse3.phsub.sw(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test6(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: phsubsw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %2 = bitcast <4 x i16> %1 to x86_mmx
-  %3 = bitcast <4 x i16> %0 to x86_mmx
-  %4 = tail call x86_mmx @llvm.x86.ssse3.phsub.sw(x86_mmx %2, x86_mmx %3) nounwind readnone
-  %5 = bitcast x86_mmx %4 to <4 x i16>
-  %6 = bitcast <4 x i16> %5 to <1 x i64>
-  %7 = extractelement <1 x i64> %6, i32 0
-  ret i64 %7
-}
-
-declare x86_mmx @llvm.x86.ssse3.phsub.d(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test5(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: phsubd
-entry:
-  %0 = bitcast <1 x i64> %b to <2 x i32>
-  %1 = bitcast <1 x i64> %a to <2 x i32>
-  %2 = bitcast <2 x i32> %1 to x86_mmx
-  %3 = bitcast <2 x i32> %0 to x86_mmx
-  %4 = tail call x86_mmx @llvm.x86.ssse3.phsub.d(x86_mmx %2, x86_mmx %3) nounwind readnone
-  %5 = bitcast x86_mmx %4 to <2 x i32>
-  %6 = bitcast <2 x i32> %5 to <1 x i64>
-  %7 = extractelement <1 x i64> %6, i32 0
-  ret i64 %7
-}
-
-declare x86_mmx @llvm.x86.ssse3.phsub.w(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test4(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: phsubw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %2 = bitcast <4 x i16> %1 to x86_mmx
-  %3 = bitcast <4 x i16> %0 to x86_mmx
-  %4 = tail call x86_mmx @llvm.x86.ssse3.phsub.w(x86_mmx %2, x86_mmx %3) nounwind readnone
-  %5 = bitcast x86_mmx %4 to <4 x i16>
-  %6 = bitcast <4 x i16> %5 to <1 x i64>
-  %7 = extractelement <1 x i64> %6, i32 0
-  ret i64 %7
-}
-
-declare x86_mmx @llvm.x86.ssse3.phadd.sw(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test3(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: phaddsw
-entry:
-  %0 = bitcast <1 x i64> %b to <4 x i16>
-  %1 = bitcast <1 x i64> %a to <4 x i16>
-  %2 = bitcast <4 x i16> %1 to x86_mmx
-  %3 = bitcast <4 x i16> %0 to x86_mmx
-  %4 = tail call x86_mmx @llvm.x86.ssse3.phadd.sw(x86_mmx %2, x86_mmx %3) nounwind readnone
-  %5 = bitcast x86_mmx %4 to <4 x i16>
-  %6 = bitcast <4 x i16> %5 to <1 x i64>
-  %7 = extractelement <1 x i64> %6, i32 0
-  ret i64 %7
-}
-
-declare x86_mmx @llvm.x86.ssse3.phadd.d(x86_mmx, x86_mmx) nounwind readnone
-
-define i64 @test2(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
-; CHECK: phaddd
-entry:
-  %0 = bitcast <1 x i64> %b to <2 x i32>
-  %1 = bitcast <1 x i64> %a to <2 x i32>
-  %2 = bitcast <2 x i32> %1 to x86_mmx
-  %3 = bitcast <2 x i32> %0 to x86_mmx
-  %4 = tail call x86_mmx @llvm.x86.ssse3.phadd.d(x86_mmx %2, x86_mmx %3) nounwind readnone
-  %5 = bitcast x86_mmx %4 to <2 x i32>
-  %6 = bitcast <2 x i32> %5 to <1 x i64>
-  %7 = extractelement <1 x i64> %6, i32 0
-  ret i64 %7
-}
-
-define <4 x float> @test89(<4 x float> %a, x86_mmx %b) nounwind {
-; CHECK: cvtpi2ps
-  %c = tail call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> %a, x86_mmx %b)
-  ret <4 x float> %c
-}
-
-declare <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float>, x86_mmx) nounwind readnone
diff --git a/test/CodeGen/X86/mmx-copy-gprs.ll b/test/CodeGen/X86/mmx-copy-gprs.ll
index 377875565bf8..6d39713833e8 100644
--- a/test/CodeGen/X86/mmx-copy-gprs.ll
+++ b/test/CodeGen/X86/mmx-copy-gprs.ll
@@ -11,7 +11,7 @@
 
 define void @foo(<1 x i64>* %x, <1 x i64>* %y) nounwind  {
 entry:
-	%tmp1 = load <1 x i64>* %y, align 8		; <<1 x i64>> [#uses=1]
+	%tmp1 = load <1 x i64>, <1 x i64>* %y, align 8		; <<1 x i64>> [#uses=1]
 	store <1 x i64> %tmp1, <1 x i64>* %x, align 8
 	ret void
 }
diff --git a/test/CodeGen/X86/mmx-emms.ll b/test/CodeGen/X86/mmx-emms.ll
deleted file mode 100644
index 5ff2588da699..000000000000
--- a/test/CodeGen/X86/mmx-emms.ll
+++ /dev/null
@@ -1,11 +0,0 @@
-; RUN: llc < %s -march=x86 -mattr=+mmx | grep emms
-define void @foo() {
-entry:
-	call void @llvm.x86.mmx.emms( )
-	br label %return
-
-return:		; preds = %entry
-	ret void
-}
-
-declare void @llvm.x86.mmx.emms()
diff --git a/test/CodeGen/X86/mmx-fold-load.ll b/test/CodeGen/X86/mmx-fold-load.ll
new file mode 100644
index 000000000000..2b9d30f59fd5
--- /dev/null
+++ b/test/CodeGen/X86/mmx-fold-load.ll
@@ -0,0 +1,282 @@
+; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | FileCheck %s
+
+define i64 @t0(<1 x i64>* %a, i32* %b) {
+; CHECK-LABEL: t0:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:         movq (%[[REG1:[a-z]+]]), %mm0
+; CHECK-NEXT:    psllq (%[[REG2:[a-z]+]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = bitcast <1 x i64>* %a to x86_mmx*
+  %1 = load x86_mmx, x86_mmx* %0, align 8
+  %2 = load i32, i32* %b, align 4
+  %3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %1, i32 %2)
+  %4 = bitcast x86_mmx %3 to i64
+  ret i64 %4
+}
+declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
+
+define i64 @t1(<1 x i64>* %a, i32* %b) {
+; CHECK-LABEL: t1:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:         movq (%[[REG1]]), %mm0
+; CHECK-NEXT:    psrlq (%[[REG2]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = bitcast <1 x i64>* %a to x86_mmx*
+  %1 = load x86_mmx, x86_mmx* %0, align 8
+  %2 = load i32, i32* %b, align 4
+  %3 = tail call x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx %1, i32 %2)
+  %4 = bitcast x86_mmx %3 to i64
+  ret i64 %4
+}
+declare x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx, i32)
+
+define i64 @t2(<1 x i64>* %a, i32* %b) {
+; CHECK-LABEL: t2:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:         movq (%[[REG1]]), %mm0
+; CHECK-NEXT:    psllw (%[[REG2]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = bitcast <1 x i64>* %a to x86_mmx*
+  %1 = load x86_mmx, x86_mmx* %0, align 8
+  %2 = load i32, i32* %b, align 4
+  %3 = tail call x86_mmx @llvm.x86.mmx.pslli.w(x86_mmx %1, i32 %2)
+  %4 = bitcast x86_mmx %3 to i64
+  ret i64 %4
+}
+declare x86_mmx @llvm.x86.mmx.pslli.w(x86_mmx, i32)
+
+define i64 @t3(<1 x i64>* %a, i32* %b) {
+; CHECK-LABEL: t3:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:         movq (%[[REG1]]), %mm0
+; CHECK-NEXT:    psrlw (%[[REG2]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = bitcast <1 x i64>* %a to x86_mmx*
+  %1 = load x86_mmx, x86_mmx* %0, align 8
+  %2 = load i32, i32* %b, align 4
+  %3 = tail call x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx %1, i32 %2)
+  %4 = bitcast x86_mmx %3 to i64
+  ret i64 %4
+}
+declare x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx, i32)
+
+define i64 @t4(<1 x i64>* %a, i32* %b) {
+; CHECK-LABEL: t4:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:         movq (%[[REG1]]), %mm0
+; CHECK-NEXT:    pslld (%[[REG2]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = bitcast <1 x i64>* %a to x86_mmx*
+  %1 = load x86_mmx, x86_mmx* %0, align 8
+  %2 = load i32, i32* %b, align 4
+  %3 = tail call x86_mmx @llvm.x86.mmx.pslli.d(x86_mmx %1, i32 %2)
+  %4 = bitcast x86_mmx %3 to i64
+  ret i64 %4
+}
+declare x86_mmx @llvm.x86.mmx.pslli.d(x86_mmx, i32)
+
+define i64 @t5(<1 x i64>* %a, i32* %b) {
+; CHECK-LABEL: t5:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:         movq (%[[REG1]]), %mm0
+; CHECK-NEXT:    psrld (%[[REG2]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = bitcast <1 x i64>* %a to x86_mmx*
+  %1 = load x86_mmx, x86_mmx* %0, align 8
+  %2 = load i32, i32* %b, align 4
+  %3 = tail call x86_mmx @llvm.x86.mmx.psrli.d(x86_mmx %1, i32 %2)
+  %4 = bitcast x86_mmx %3 to i64
+  ret i64 %4
+}
+declare x86_mmx @llvm.x86.mmx.psrli.d(x86_mmx, i32)
+
+define i64 @t6(<1 x i64>* %a, i32* %b) {
+; CHECK-LABEL: t6:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:         movq (%[[REG1]]), %mm0
+; CHECK-NEXT:    psraw (%[[REG2]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = bitcast <1 x i64>* %a to x86_mmx*
+  %1 = load x86_mmx, x86_mmx* %0, align 8
+  %2 = load i32, i32* %b, align 4
+  %3 = tail call x86_mmx @llvm.x86.mmx.psrai.w(x86_mmx %1, i32 %2)
+  %4 = bitcast x86_mmx %3 to i64
+  ret i64 %4
+}
+declare x86_mmx @llvm.x86.mmx.psrai.w(x86_mmx, i32)
+
+define i64 @t7(<1 x i64>* %a, i32* %b) {
+; CHECK-LABEL: t7:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:         movq (%[[REG1]]), %mm0
+; CHECK-NEXT:    psrad (%[[REG2]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = bitcast <1 x i64>* %a to x86_mmx*
+  %1 = load x86_mmx, x86_mmx* %0, align 8
+  %2 = load i32, i32* %b, align 4
+  %3 = tail call x86_mmx @llvm.x86.mmx.psrai.d(x86_mmx %1, i32 %2)
+  %4 = bitcast x86_mmx %3 to i64
+  ret i64 %4
+}
+declare x86_mmx @llvm.x86.mmx.psrai.d(x86_mmx, i32)
+
+define i64 @tt0(x86_mmx %t, x86_mmx* %q) {
+; CHECK-LABEL: tt0:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    paddb (%[[REG3:[a-z]+]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    emms
+; CHECK-NEXT:    retq
+entry:
+  %v = load x86_mmx, x86_mmx* %q
+  %u = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %t, x86_mmx %v)
+  %s = bitcast x86_mmx %u to i64
+  call void @llvm.x86.mmx.emms()
+  ret i64 %s
+}
+declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx)
+declare void @llvm.x86.mmx.emms()
+
+define i64 @tt1(x86_mmx %t, x86_mmx* %q) {
+; CHECK-LABEL: tt1:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    paddw (%[[REG3]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    emms
+; CHECK-NEXT:    retq
+entry:
+  %v = load x86_mmx, x86_mmx* %q
+  %u = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %t, x86_mmx %v)
+  %s = bitcast x86_mmx %u to i64
+  call void @llvm.x86.mmx.emms()
+  ret i64 %s
+}
+declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx)
+
+define i64 @tt2(x86_mmx %t, x86_mmx* %q) {
+; CHECK-LABEL: tt2:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    paddd (%[[REG3]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    emms
+; CHECK-NEXT:    retq
+entry:
+  %v = load x86_mmx, x86_mmx* %q
+  %u = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %t, x86_mmx %v)
+  %s = bitcast x86_mmx %u to i64
+  call void @llvm.x86.mmx.emms()
+  ret i64 %s
+}
+declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx)
+
+define i64 @tt3(x86_mmx %t, x86_mmx* %q) {
+; CHECK-LABEL: tt3:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    paddq (%[[REG3]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    emms
+; CHECK-NEXT:    retq
+entry:
+  %v = load x86_mmx, x86_mmx* %q
+  %u = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %t, x86_mmx %v)
+  %s = bitcast x86_mmx %u to i64
+  call void @llvm.x86.mmx.emms()
+  ret i64 %s
+}
+declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx)
+
+define i64 @tt4(x86_mmx %t, x86_mmx* %q) {
+; CHECK-LABEL: tt4:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    paddusb (%[[REG3]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    emms
+; CHECK-NEXT:    retq
+entry:
+  %v = load x86_mmx, x86_mmx* %q
+  %u = tail call x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx %t, x86_mmx %v)
+  %s = bitcast x86_mmx %u to i64
+  call void @llvm.x86.mmx.emms()
+  ret i64 %s
+}
+declare x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx, x86_mmx)
+
+define i64 @tt5(x86_mmx %t, x86_mmx* %q) {
+; CHECK-LABEL: tt5:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    paddusw (%[[REG3]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    emms
+; CHECK-NEXT:    retq
+entry:
+  %v = load x86_mmx, x86_mmx* %q
+  %u = tail call x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx %t, x86_mmx %v)
+  %s = bitcast x86_mmx %u to i64
+  call void @llvm.x86.mmx.emms()
+  ret i64 %s
+}
+declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx)
+
+define i64 @tt6(x86_mmx %t, x86_mmx* %q) {
+; CHECK-LABEL: tt6:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    psrlw (%[[REG3]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    emms
+; CHECK-NEXT:    retq
+entry:
+  %v = load x86_mmx, x86_mmx* %q
+  %u = tail call x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx %t, x86_mmx %v)
+  %s = bitcast x86_mmx %u to i64
+  call void @llvm.x86.mmx.emms()
+  ret i64 %s
+}
+declare x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx, x86_mmx)
+
+define i64 @tt7(x86_mmx %t, x86_mmx* %q) {
+; CHECK-LABEL: tt7:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    psrld (%[[REG3]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    emms
+; CHECK-NEXT:    retq
+entry:
+  %v = load x86_mmx, x86_mmx* %q
+  %u = tail call x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx %t, x86_mmx %v)
+  %s = bitcast x86_mmx %u to i64
+  call void @llvm.x86.mmx.emms()
+  ret i64 %s
+}
+declare x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx, x86_mmx)
+
+define i64 @tt8(x86_mmx %t, x86_mmx* %q) {
+; CHECK-LABEL: tt8:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    psrlq (%[[REG3]]), %mm0
+; CHECK-NEXT:    movd %mm0, %rax
+; CHECK-NEXT:    emms
+; CHECK-NEXT:    retq
+entry:
+  %v = load x86_mmx, x86_mmx* %q
+  %u = tail call x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx %t, x86_mmx %v)
+  %s = bitcast x86_mmx %u to i64
+  call void @llvm.x86.mmx.emms()
+  ret i64 %s
+}
+declare x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx, x86_mmx)
diff --git a/test/CodeGen/X86/mmx-insert-element.ll b/test/CodeGen/X86/mmx-insert-element.ll
deleted file mode 100644
index 348dac8d4d59..000000000000
--- a/test/CodeGen/X86/mmx-insert-element.ll
+++ /dev/null
@@ -1,9 +0,0 @@
-; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 | grep movq
-; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 | grep pshufd
-; This is not an MMX operation; promoted to XMM.
-
-define x86_mmx @qux(i32 %A) nounwind {
-	%tmp3 = insertelement <2 x i32> < i32 0, i32 undef >, i32 %A, i32 1		; <<2 x i32>> [#uses=1]
-        %tmp4 = bitcast <2 x i32> %tmp3 to x86_mmx
-	ret x86_mmx %tmp4
-}
diff --git a/test/CodeGen/X86/mmx-intrinsics.ll b/test/CodeGen/X86/mmx-intrinsics.ll
new file mode 100644
index 000000000000..39d481b16e7a
--- /dev/null
+++ b/test/CodeGen/X86/mmx-intrinsics.ll
@@ -0,0 +1,1358 @@
+; RUN: llc < %s -march=x86 -mattr=+mmx,+ssse3,-avx | FileCheck %s
+; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mattr=+mmx,+ssse3,-avx | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mattr=+avx | FileCheck %s
+
+declare x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test1(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: phaddw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %2 = bitcast <4 x i16> %1 to x86_mmx
+  %3 = bitcast <4 x i16> %0 to x86_mmx
+  %4 = tail call x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx %2, x86_mmx %3) nounwind readnone
+  %5 = bitcast x86_mmx %4 to <4 x i16>
+  %6 = bitcast <4 x i16> %5 to <1 x i64>
+  %7 = extractelement <1 x i64> %6, i32 0
+  ret i64 %7
+}
+
+declare x86_mmx @llvm.x86.mmx.pcmpgt.d(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test88(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pcmpgtd
+entry:
+  %0 = bitcast <1 x i64> %b to <2 x i32>
+  %1 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
+  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pcmpgt.d(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <2 x i32>
+  %4 = bitcast <2 x i32> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pcmpgt.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test87(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pcmpgtw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pcmpgt.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pcmpgt.b(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test86(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pcmpgtb
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
+  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pcmpgt.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pcmpeq.d(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test85(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pcmpeqd
+entry:
+  %0 = bitcast <1 x i64> %b to <2 x i32>
+  %1 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
+  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pcmpeq.d(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <2 x i32>
+  %4 = bitcast <2 x i32> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pcmpeq.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test84(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pcmpeqw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pcmpeq.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pcmpeq.b(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test83(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pcmpeqb
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
+  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pcmpeq.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.punpckldq(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test82(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: punpckldq
+entry:
+  %0 = bitcast <1 x i64> %b to <2 x i32>
+  %1 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
+  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.punpckldq(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <2 x i32>
+  %4 = bitcast <2 x i32> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.punpcklwd(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test81(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: punpcklwd
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.punpcklwd(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.punpcklbw(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test80(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: punpcklbw
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
+  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.punpcklbw(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.punpckhdq(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test79(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: punpckhdq
+entry:
+  %0 = bitcast <1 x i64> %b to <2 x i32>
+  %1 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
+  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.punpckhdq(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <2 x i32>
+  %4 = bitcast <2 x i32> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.punpckhwd(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test78(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: punpckhwd
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.punpckhwd(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.punpckhbw(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test77(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: punpckhbw
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
+  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.punpckhbw(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.packuswb(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test76(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: packuswb
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.packuswb(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.packssdw(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test75(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: packssdw
+entry:
+  %0 = bitcast <1 x i64> %b to <2 x i32>
+  %1 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
+  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.packssdw(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.packsswb(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test74(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: packsswb
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.packsswb(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.psrai.d(x86_mmx, i32) nounwind readnone
+
+define i64 @test73(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: psrad
+entry:
+  %0 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx
+  %1 = tail call x86_mmx @llvm.x86.mmx.psrai.d(x86_mmx %mmx_var.i, i32 3) nounwind
+  %2 = bitcast x86_mmx %1 to <2 x i32>
+  %3 = bitcast <2 x i32> %2 to <1 x i64>
+  %4 = extractelement <1 x i64> %3, i32 0
+  ret i64 %4
+}
+
+declare x86_mmx @llvm.x86.mmx.psrai.w(x86_mmx, i32) nounwind readnone
+
+define i64 @test72(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: psraw
+entry:
+  %0 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx
+  %1 = tail call x86_mmx @llvm.x86.mmx.psrai.w(x86_mmx %mmx_var.i, i32 3) nounwind
+  %2 = bitcast x86_mmx %1 to <4 x i16>
+  %3 = bitcast <4 x i16> %2 to <1 x i64>
+  %4 = extractelement <1 x i64> %3, i32 0
+  ret i64 %4
+}
+
+declare x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx, i32) nounwind readnone
+
+define i64 @test71(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: psrlq
+entry:
+  %0 = extractelement <1 x i64> %a, i32 0
+  %mmx_var.i = bitcast i64 %0 to x86_mmx
+  %1 = tail call x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx %mmx_var.i, i32 3) nounwind
+  %2 = bitcast x86_mmx %1 to i64
+  ret i64 %2
+}
+
+declare x86_mmx @llvm.x86.mmx.psrli.d(x86_mmx, i32) nounwind readnone
+
+define i64 @test70(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: psrld
+entry:
+  %0 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx
+  %1 = tail call x86_mmx @llvm.x86.mmx.psrli.d(x86_mmx %mmx_var.i, i32 3) nounwind
+  %2 = bitcast x86_mmx %1 to <2 x i32>
+  %3 = bitcast <2 x i32> %2 to <1 x i64>
+  %4 = extractelement <1 x i64> %3, i32 0
+  ret i64 %4
+}
+
+declare x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx, i32) nounwind readnone
+
+define i64 @test69(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: psrlw
+entry:
+  %0 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx
+  %1 = tail call x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx %mmx_var.i, i32 3) nounwind
+  %2 = bitcast x86_mmx %1 to <4 x i16>
+  %3 = bitcast <4 x i16> %2 to <1 x i64>
+  %4 = extractelement <1 x i64> %3, i32 0
+  ret i64 %4
+}
+
+declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32) nounwind readnone
+
+define i64 @test68(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: psllq
+entry:
+  %0 = extractelement <1 x i64> %a, i32 0
+  %mmx_var.i = bitcast i64 %0 to x86_mmx
+  %1 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %mmx_var.i, i32 3) nounwind
+  %2 = bitcast x86_mmx %1 to i64
+  ret i64 %2
+}
+
+declare x86_mmx @llvm.x86.mmx.pslli.d(x86_mmx, i32) nounwind readnone
+
+define i64 @test67(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: pslld
+entry:
+  %0 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx
+  %1 = tail call x86_mmx @llvm.x86.mmx.pslli.d(x86_mmx %mmx_var.i, i32 3) nounwind
+  %2 = bitcast x86_mmx %1 to <2 x i32>
+  %3 = bitcast <2 x i32> %2 to <1 x i64>
+  %4 = extractelement <1 x i64> %3, i32 0
+  ret i64 %4
+}
+
+declare x86_mmx @llvm.x86.mmx.pslli.w(x86_mmx, i32) nounwind readnone
+
+define i64 @test66(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: psllw
+entry:
+  %0 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx
+  %1 = tail call x86_mmx @llvm.x86.mmx.pslli.w(x86_mmx %mmx_var.i, i32 3) nounwind
+  %2 = bitcast x86_mmx %1 to <4 x i16>
+  %3 = bitcast <4 x i16> %2 to <1 x i64>
+  %4 = extractelement <1 x i64> %3, i32 0
+  ret i64 %4
+}
+
+declare x86_mmx @llvm.x86.mmx.psra.d(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test65(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psrad
+entry:
+  %0 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx
+  %1 = extractelement <1 x i64> %b, i32 0
+  %mmx_var1.i = bitcast i64 %1 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psra.d(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <2 x i32>
+  %4 = bitcast <2 x i32> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.psra.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test64(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psraw
+entry:
+  %0 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx
+  %1 = extractelement <1 x i64> %b, i32 0
+  %mmx_var1.i = bitcast i64 %1 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psra.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test63(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psrlq
+entry:
+  %0 = extractelement <1 x i64> %a, i32 0
+  %mmx_var.i = bitcast i64 %0 to x86_mmx
+  %1 = extractelement <1 x i64> %b, i32 0
+  %mmx_var1.i = bitcast i64 %1 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to i64
+  ret i64 %3
+}
+
+declare x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test62(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psrld
+entry:
+  %0 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx
+  %1 = extractelement <1 x i64> %b, i32 0
+  %mmx_var1.i = bitcast i64 %1 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <2 x i32>
+  %4 = bitcast <2 x i32> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test61(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psrlw
+entry:
+  %0 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx
+  %1 = extractelement <1 x i64> %b, i32 0
+  %mmx_var1.i = bitcast i64 %1 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.psll.q(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test60(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psllq
+entry:
+  %0 = extractelement <1 x i64> %a, i32 0
+  %mmx_var.i = bitcast i64 %0 to x86_mmx
+  %1 = extractelement <1 x i64> %b, i32 0
+  %mmx_var1.i = bitcast i64 %1 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psll.q(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to i64
+  ret i64 %3
+}
+
+declare x86_mmx @llvm.x86.mmx.psll.d(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test59(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pslld
+entry:
+  %0 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx
+  %1 = extractelement <1 x i64> %b, i32 0
+  %mmx_var1.i = bitcast i64 %1 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psll.d(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <2 x i32>
+  %4 = bitcast <2 x i32> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.psll.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test58(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psllw
+entry:
+  %0 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx
+  %1 = extractelement <1 x i64> %b, i32 0
+  %mmx_var1.i = bitcast i64 %1 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psll.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pxor(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test56(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pxor
+entry:
+  %0 = bitcast <1 x i64> %b to <2 x i32>
+  %1 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
+  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pxor(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <2 x i32>
+  %4 = bitcast <2 x i32> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.por(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test55(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: por
+entry:
+  %0 = bitcast <1 x i64> %b to <2 x i32>
+  %1 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
+  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.por(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <2 x i32>
+  %4 = bitcast <2 x i32> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pandn(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test54(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pandn
+entry:
+  %0 = bitcast <1 x i64> %b to <2 x i32>
+  %1 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
+  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pandn(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <2 x i32>
+  %4 = bitcast <2 x i32> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pand(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test53(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pand
+entry:
+  %0 = bitcast <1 x i64> %b to <2 x i32>
+  %1 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
+  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pand(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <2 x i32>
+  %4 = bitcast <2 x i32> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test52(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pmullw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+define i64 @test51(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pmullw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pmulh.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test50(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pmulhw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pmulh.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pmadd.wd(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test49(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pmaddwd
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pmadd.wd(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <2 x i32>
+  %4 = bitcast <2 x i32> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.psubus.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test48(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psubusw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psubus.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.psubus.b(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test47(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psubusb
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
+  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psubus.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.psubs.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test46(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psubsw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psubs.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.psubs.b(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test45(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psubsb
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
+  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psubs.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+define i64 @test44(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psubq
+entry:
+  %0 = extractelement <1 x i64> %a, i32 0
+  %mmx_var = bitcast i64 %0 to x86_mmx
+  %1 = extractelement <1 x i64> %b, i32 0
+  %mmx_var1 = bitcast i64 %1 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psub.q(x86_mmx %mmx_var, x86_mmx %mmx_var1)
+  %3 = bitcast x86_mmx %2 to i64
+  ret i64 %3
+}
+
+declare x86_mmx @llvm.x86.mmx.psub.q(x86_mmx, x86_mmx) nounwind readnone
+
+declare x86_mmx @llvm.x86.mmx.psub.d(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test43(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psubd
+entry:
+  %0 = bitcast <1 x i64> %b to <2 x i32>
+  %1 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
+  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psub.d(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <2 x i32>
+  %4 = bitcast <2 x i32> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.psub.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test42(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psubw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psub.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.psub.b(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test41(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psubb
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
+  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psub.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test40(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: paddusw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test39(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: paddusb
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
+  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.padds.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test38(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: paddsw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.padds.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.padds.b(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test37(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: paddsb
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
+  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.padds.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test36(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: paddq
+entry:
+  %0 = extractelement <1 x i64> %a, i32 0
+  %mmx_var = bitcast i64 %0 to x86_mmx
+  %1 = extractelement <1 x i64> %b, i32 0
+  %mmx_var1 = bitcast i64 %1 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %mmx_var, x86_mmx %mmx_var1)
+  %3 = bitcast x86_mmx %2 to i64
+  ret i64 %3
+}
+
+declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test35(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: paddd
+entry:
+  %0 = bitcast <1 x i64> %b to <2 x i32>
+  %1 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
+  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <2 x i32>
+  %4 = bitcast <2 x i32> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test34(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: paddw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test33(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: paddb
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
+  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.psad.bw(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test32(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psadbw
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
+  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.psad.bw(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to i64
+  ret i64 %3
+}
+
+declare x86_mmx @llvm.x86.mmx.pmins.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test31(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pminsw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pmins.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pminu.b(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test30(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pminub
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
+  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pminu.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pmaxs.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test29(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pmaxsw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pmaxs.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pmaxu.b(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test28(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pmaxub
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
+  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pmaxu.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pavg.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test27(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pavgw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pavg.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pavg.b(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test26(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pavgb
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
+  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pavg.b(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare void @llvm.x86.mmx.movnt.dq(x86_mmx*, x86_mmx) nounwind
+
+define void @test25(<1 x i64>* %p, <1 x i64> %a) nounwind optsize ssp {
+; CHECK: movntq
+entry:
+  %mmx_ptr_var.i = bitcast <1 x i64>* %p to x86_mmx*
+  %0 = extractelement <1 x i64> %a, i32 0
+  %mmx_var.i = bitcast i64 %0 to x86_mmx
+  tail call void @llvm.x86.mmx.movnt.dq(x86_mmx* %mmx_ptr_var.i, x86_mmx %mmx_var.i) nounwind
+  ret void
+}
+
+declare i32 @llvm.x86.mmx.pmovmskb(x86_mmx) nounwind readnone
+
+define i32 @test24(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: pmovmskb
+entry:
+  %0 = bitcast <1 x i64> %a to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %0 to x86_mmx
+  %1 = tail call i32 @llvm.x86.mmx.pmovmskb(x86_mmx %mmx_var.i) nounwind
+  ret i32 %1
+}
+
+declare void @llvm.x86.mmx.maskmovq(x86_mmx, x86_mmx, i8*) nounwind
+
+define void @test23(<1 x i64> %d, <1 x i64> %n, i8* %p) nounwind optsize ssp {
+; CHECK: maskmovq
+entry:
+  %0 = bitcast <1 x i64> %n to <8 x i8>
+  %1 = bitcast <1 x i64> %d to <8 x i8>
+  %mmx_var.i = bitcast <8 x i8> %1 to x86_mmx
+  %mmx_var1.i = bitcast <8 x i8> %0 to x86_mmx
+  tail call void @llvm.x86.mmx.maskmovq(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i, i8* %p) nounwind
+  ret void
+}
+
+declare x86_mmx @llvm.x86.mmx.pmulhu.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test22(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pmulhuw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx
+  %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pmulhu.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8) nounwind readnone
+
+define i64 @test21(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: pshufw
+entry:
+  %0 = bitcast <1 x i64> %a to <4 x i16>
+  %1 = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 3) nounwind readnone
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+define i32 @test21_2(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: test21_2
+; CHECK: pshufw
+; CHECK: movd
+entry:
+  %0 = bitcast <1 x i64> %a to <4 x i16>
+  %1 = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 3) nounwind readnone
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <2 x i32>
+  %5 = extractelement <2 x i32> %4, i32 0
+  ret i32 %5
+}
+
+declare x86_mmx @llvm.x86.mmx.pmulu.dq(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test20(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pmuludq
+entry:
+  %0 = bitcast <1 x i64> %b to <2 x i32>
+  %1 = bitcast <1 x i64> %a to <2 x i32>
+  %mmx_var.i = bitcast <2 x i32> %1 to x86_mmx
+  %mmx_var1.i = bitcast <2 x i32> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.pmulu.dq(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
+  %3 = bitcast x86_mmx %2 to i64
+  ret i64 %3
+}
+
+declare <2 x double> @llvm.x86.sse.cvtpi2pd(x86_mmx) nounwind readnone
+
+define <2 x double> @test19(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: cvtpi2pd
+entry:
+  %0 = bitcast <1 x i64> %a to <2 x i32>
+  %1 = bitcast <2 x i32> %0 to x86_mmx
+  %2 = tail call <2 x double> @llvm.x86.sse.cvtpi2pd(x86_mmx %1) nounwind readnone
+  ret <2 x double> %2
+}
+
+declare x86_mmx @llvm.x86.sse.cvttpd2pi(<2 x double>) nounwind readnone
+
+define i64 @test18(<2 x double> %a) nounwind readnone optsize ssp {
+; CHECK: cvttpd2pi
+entry:
+  %0 = tail call x86_mmx @llvm.x86.sse.cvttpd2pi(<2 x double> %a) nounwind readnone
+  %1 = bitcast x86_mmx %0 to <2 x i32>
+  %2 = bitcast <2 x i32> %1 to <1 x i64>
+  %3 = extractelement <1 x i64> %2, i32 0
+  ret i64 %3
+}
+
+declare x86_mmx @llvm.x86.sse.cvtpd2pi(<2 x double>) nounwind readnone
+
+define i64 @test17(<2 x double> %a) nounwind readnone optsize ssp {
+; CHECK: cvtpd2pi
+entry:
+  %0 = tail call x86_mmx @llvm.x86.sse.cvtpd2pi(<2 x double> %a) nounwind readnone
+  %1 = bitcast x86_mmx %0 to <2 x i32>
+  %2 = bitcast <2 x i32> %1 to <1 x i64>
+  %3 = extractelement <1 x i64> %2, i32 0
+  ret i64 %3
+}
+
+declare x86_mmx @llvm.x86.mmx.palignr.b(x86_mmx, x86_mmx, i8) nounwind readnone
+
+define i64 @test16(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: palignr
+entry:
+  %0 = extractelement <1 x i64> %a, i32 0
+  %mmx_var = bitcast i64 %0 to x86_mmx
+  %1 = extractelement <1 x i64> %b, i32 0
+  %mmx_var1 = bitcast i64 %1 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.mmx.palignr.b(x86_mmx %mmx_var, x86_mmx %mmx_var1, i8 16)
+  %3 = bitcast x86_mmx %2 to i64
+  ret i64 %3
+}
+
+declare x86_mmx @llvm.x86.ssse3.pabs.d(x86_mmx) nounwind readnone
+
+define i64 @test15(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: pabsd
+entry:
+  %0 = bitcast <1 x i64> %a to <2 x i32>
+  %1 = bitcast <2 x i32> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.ssse3.pabs.d(x86_mmx %1) nounwind readnone
+  %3 = bitcast x86_mmx %2 to <2 x i32>
+  %4 = bitcast <2 x i32> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.ssse3.pabs.w(x86_mmx) nounwind readnone
+
+define i64 @test14(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: pabsw
+entry:
+  %0 = bitcast <1 x i64> %a to <4 x i16>
+  %1 = bitcast <4 x i16> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.ssse3.pabs.w(x86_mmx %1) nounwind readnone
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.ssse3.pabs.b(x86_mmx) nounwind readnone
+
+define i64 @test13(<1 x i64> %a) nounwind readnone optsize ssp {
+; CHECK: pabsb
+entry:
+  %0 = bitcast <1 x i64> %a to <8 x i8>
+  %1 = bitcast <8 x i8> %0 to x86_mmx
+  %2 = tail call x86_mmx @llvm.x86.ssse3.pabs.b(x86_mmx %1) nounwind readnone
+  %3 = bitcast x86_mmx %2 to <8 x i8>
+  %4 = bitcast <8 x i8> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  ret i64 %5
+}
+
+declare x86_mmx @llvm.x86.ssse3.psign.d(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test12(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psignd
+entry:
+  %0 = bitcast <1 x i64> %b to <2 x i32>
+  %1 = bitcast <1 x i64> %a to <2 x i32>
+  %2 = bitcast <2 x i32> %1 to x86_mmx
+  %3 = bitcast <2 x i32> %0 to x86_mmx
+  %4 = tail call x86_mmx @llvm.x86.ssse3.psign.d(x86_mmx %2, x86_mmx %3) nounwind readnone
+  %5 = bitcast x86_mmx %4 to <2 x i32>
+  %6 = bitcast <2 x i32> %5 to <1 x i64>
+  %7 = extractelement <1 x i64> %6, i32 0
+  ret i64 %7
+}
+
+declare x86_mmx @llvm.x86.ssse3.psign.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test11(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psignw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %2 = bitcast <4 x i16> %1 to x86_mmx
+  %3 = bitcast <4 x i16> %0 to x86_mmx
+  %4 = tail call x86_mmx @llvm.x86.ssse3.psign.w(x86_mmx %2, x86_mmx %3) nounwind readnone
+  %5 = bitcast x86_mmx %4 to <4 x i16>
+  %6 = bitcast <4 x i16> %5 to <1 x i64>
+  %7 = extractelement <1 x i64> %6, i32 0
+  ret i64 %7
+}
+
+declare x86_mmx @llvm.x86.ssse3.psign.b(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test10(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: psignb
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %2 = bitcast <8 x i8> %1 to x86_mmx
+  %3 = bitcast <8 x i8> %0 to x86_mmx
+  %4 = tail call x86_mmx @llvm.x86.ssse3.psign.b(x86_mmx %2, x86_mmx %3) nounwind readnone
+  %5 = bitcast x86_mmx %4 to <8 x i8>
+  %6 = bitcast <8 x i8> %5 to <1 x i64>
+  %7 = extractelement <1 x i64> %6, i32 0
+  ret i64 %7
+}
+
+declare x86_mmx @llvm.x86.ssse3.pshuf.b(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test9(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pshufb
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %2 = bitcast <8 x i8> %1 to x86_mmx
+  %3 = bitcast <8 x i8> %0 to x86_mmx
+  %4 = tail call x86_mmx @llvm.x86.ssse3.pshuf.b(x86_mmx %2, x86_mmx %3) nounwind readnone
+  %5 = bitcast x86_mmx %4 to <8 x i8>
+  %6 = bitcast <8 x i8> %5 to <1 x i64>
+  %7 = extractelement <1 x i64> %6, i32 0
+  ret i64 %7
+}
+
+declare x86_mmx @llvm.x86.ssse3.pmul.hr.sw(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test8(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pmulhrsw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %2 = bitcast <4 x i16> %1 to x86_mmx
+  %3 = bitcast <4 x i16> %0 to x86_mmx
+  %4 = tail call x86_mmx @llvm.x86.ssse3.pmul.hr.sw(x86_mmx %2, x86_mmx %3) nounwind readnone
+  %5 = bitcast x86_mmx %4 to <4 x i16>
+  %6 = bitcast <4 x i16> %5 to <1 x i64>
+  %7 = extractelement <1 x i64> %6, i32 0
+  ret i64 %7
+}
+
+declare x86_mmx @llvm.x86.ssse3.pmadd.ub.sw(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test7(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: pmaddubsw
+entry:
+  %0 = bitcast <1 x i64> %b to <8 x i8>
+  %1 = bitcast <1 x i64> %a to <8 x i8>
+  %2 = bitcast <8 x i8> %1 to x86_mmx
+  %3 = bitcast <8 x i8> %0 to x86_mmx
+  %4 = tail call x86_mmx @llvm.x86.ssse3.pmadd.ub.sw(x86_mmx %2, x86_mmx %3) nounwind readnone
+  %5 = bitcast x86_mmx %4 to <8 x i8>
+  %6 = bitcast <8 x i8> %5 to <1 x i64>
+  %7 = extractelement <1 x i64> %6, i32 0
+  ret i64 %7
+}
+
+declare x86_mmx @llvm.x86.ssse3.phsub.sw(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test6(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: phsubsw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %2 = bitcast <4 x i16> %1 to x86_mmx
+  %3 = bitcast <4 x i16> %0 to x86_mmx
+  %4 = tail call x86_mmx @llvm.x86.ssse3.phsub.sw(x86_mmx %2, x86_mmx %3) nounwind readnone
+  %5 = bitcast x86_mmx %4 to <4 x i16>
+  %6 = bitcast <4 x i16> %5 to <1 x i64>
+  %7 = extractelement <1 x i64> %6, i32 0
+  ret i64 %7
+}
+
+declare x86_mmx @llvm.x86.ssse3.phsub.d(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test5(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: phsubd
+entry:
+  %0 = bitcast <1 x i64> %b to <2 x i32>
+  %1 = bitcast <1 x i64> %a to <2 x i32>
+  %2 = bitcast <2 x i32> %1 to x86_mmx
+  %3 = bitcast <2 x i32> %0 to x86_mmx
+  %4 = tail call x86_mmx @llvm.x86.ssse3.phsub.d(x86_mmx %2, x86_mmx %3) nounwind readnone
+  %5 = bitcast x86_mmx %4 to <2 x i32>
+  %6 = bitcast <2 x i32> %5 to <1 x i64>
+  %7 = extractelement <1 x i64> %6, i32 0
+  ret i64 %7
+}
+
+declare x86_mmx @llvm.x86.ssse3.phsub.w(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test4(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: phsubw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %2 = bitcast <4 x i16> %1 to x86_mmx
+  %3 = bitcast <4 x i16> %0 to x86_mmx
+  %4 = tail call x86_mmx @llvm.x86.ssse3.phsub.w(x86_mmx %2, x86_mmx %3) nounwind readnone
+  %5 = bitcast x86_mmx %4 to <4 x i16>
+  %6 = bitcast <4 x i16> %5 to <1 x i64>
+  %7 = extractelement <1 x i64> %6, i32 0
+  ret i64 %7
+}
+
+declare x86_mmx @llvm.x86.ssse3.phadd.sw(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test3(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: phaddsw
+entry:
+  %0 = bitcast <1 x i64> %b to <4 x i16>
+  %1 = bitcast <1 x i64> %a to <4 x i16>
+  %2 = bitcast <4 x i16> %1 to x86_mmx
+  %3 = bitcast <4 x i16> %0 to x86_mmx
+  %4 = tail call x86_mmx @llvm.x86.ssse3.phadd.sw(x86_mmx %2, x86_mmx %3) nounwind readnone
+  %5 = bitcast x86_mmx %4 to <4 x i16>
+  %6 = bitcast <4 x i16> %5 to <1 x i64>
+  %7 = extractelement <1 x i64> %6, i32 0
+  ret i64 %7
+}
+
+declare x86_mmx @llvm.x86.ssse3.phadd.d(x86_mmx, x86_mmx) nounwind readnone
+
+define i64 @test2(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp {
+; CHECK: phaddd
+entry:
+  %0 = bitcast <1 x i64> %b to <2 x i32>
+  %1 = bitcast <1 x i64> %a to <2 x i32>
+  %2 = bitcast <2 x i32> %1 to x86_mmx
+  %3 = bitcast <2 x i32> %0 to x86_mmx
+  %4 = tail call x86_mmx @llvm.x86.ssse3.phadd.d(x86_mmx %2, x86_mmx %3) nounwind readnone
+  %5 = bitcast x86_mmx %4 to <2 x i32>
+  %6 = bitcast <2 x i32> %5 to <1 x i64>
+  %7 = extractelement <1 x i64> %6, i32 0
+  ret i64 %7
+}
+
+define <4 x float> @test89(<4 x float> %a, x86_mmx %b) nounwind {
+; CHECK: cvtpi2ps
+  %c = tail call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> %a, x86_mmx %b)
+  ret <4 x float> %c
+}
+
+declare <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float>, x86_mmx) nounwind readnone
+
+; CHECK-LABEL: test90
+define void @test90() {
+; CHECK: emms
+  call void @llvm.x86.mmx.emms()
+  ret void
+}
+
+declare void @llvm.x86.mmx.emms()
diff --git a/test/CodeGen/X86/mmx-pinsrw.ll b/test/CodeGen/X86/mmx-pinsrw.ll
deleted file mode 100644
index 33dd2eb81cfa..000000000000
--- a/test/CodeGen/X86/mmx-pinsrw.ll
+++ /dev/null
@@ -1,17 +0,0 @@
-; RUN: llc < %s  -mtriple=x86_64-linux -mcpu=corei7 | FileCheck %s
-; PR2562
-
-; CHECK: pinsr
-
-external global i16		; <i16*>:0 [#uses=1]
-external global <4 x i16>		; <<4 x i16>*>:1 [#uses=2]
-
-declare void @abort()
-
-define void @""() {
-	load i16* @0		; <i16>:1 [#uses=1]
-	load <4 x i16>* @1		; <<4 x i16>>:2 [#uses=1]
-	insertelement <4 x i16> %2, i16 %1, i32 0		; <<4 x i16>>:3 [#uses=1]
-	store <4 x i16> %3, <4 x i16>* @1
-	ret void
-}
diff --git a/test/CodeGen/X86/mmx-punpckhdq.ll b/test/CodeGen/X86/mmx-punpckhdq.ll
deleted file mode 100644
index 9e8f5bf53363..000000000000
--- a/test/CodeGen/X86/mmx-punpckhdq.ll
+++ /dev/null
@@ -1,31 +0,0 @@
-; RUN: llc < %s -march=x86 -mattr=+mmx,+sse4.2 -mtriple=x86_64-apple-darwin10 | FileCheck %s
-; There are no MMX operations in bork; promoted to XMM.
-
-define void @bork(<1 x i64>* %x) {
-; CHECK: bork
-; CHECK: movlpd
-entry:
-	%tmp2 = load <1 x i64>* %x		; <<1 x i64>> [#uses=1]
-	%tmp6 = bitcast <1 x i64> %tmp2 to <2 x i32>		; <<2 x i32>> [#uses=1]
-	%tmp9 = shufflevector <2 x i32> %tmp6, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >		; <<2 x i32>> [#uses=1]
-	%tmp10 = bitcast <2 x i32> %tmp9 to <1 x i64>		; <<1 x i64>> [#uses=1]
-	store <1 x i64> %tmp10, <1 x i64>* %x
-	tail call void @llvm.x86.mmx.emms( )
-	ret void
-}
-
-; pork uses MMX.
-
-define void @pork(x86_mmx* %x) {
-; CHECK: pork
-; CHECK: punpckhdq
-entry:
-	%tmp2 = load x86_mmx* %x		; <x86_mmx> [#uses=1]
-        %tmp9 = tail call x86_mmx @llvm.x86.mmx.punpckhdq (x86_mmx %tmp2, x86_mmx %tmp2)
-	store x86_mmx %tmp9, x86_mmx* %x
-	tail call void @llvm.x86.mmx.emms( )
-	ret void
-}
-
-declare x86_mmx @llvm.x86.mmx.punpckhdq(x86_mmx, x86_mmx)
-declare void @llvm.x86.mmx.emms()
diff --git a/test/CodeGen/X86/mmx-s2v.ll b/test/CodeGen/X86/mmx-s2v.ll
deleted file mode 100644
index c98023c0f417..000000000000
--- a/test/CodeGen/X86/mmx-s2v.ll
+++ /dev/null
@@ -1,15 +0,0 @@
-; RUN: llc < %s -march=x86 -mattr=+mmx
-; PR2574
-
-define void @entry(i32 %m_task_id, i32 %start_x, i32 %end_x) {; <label>:0
-        br i1 true, label %bb.nph, label %._crit_edge
-
-bb.nph:         ; preds = %bb.nph, %0
-        %t2206f2.0 = phi <2 x float> [ %2, %bb.nph ], [ undef, %0 ]             ; <<2 x float>> [#uses=1]
-        insertelement <2 x float> %t2206f2.0, float 0.000000e+00, i32 0         ; <<2 x float>>:1 [#uses=1]
-        insertelement <2 x float> %1, float 0.000000e+00, i32 1         ; <<2 x float>>:2 [#uses=1]
-        br label %bb.nph
-
-._crit_edge:            ; preds = %0
-        ret void
-}
diff --git a/test/CodeGen/X86/mmx-shift.ll b/test/CodeGen/X86/mmx-shift.ll
deleted file mode 100644
index c7c6e75a5071..000000000000
--- a/test/CodeGen/X86/mmx-shift.ll
+++ /dev/null
@@ -1,39 +0,0 @@
-; RUN: llc < %s -march=x86 -mattr=+mmx | FileCheck %s
-; RUN: llc < %s -march=x86-64 -mattr=+mmx | FileCheck %s
-
-define i64 @t1(<1 x i64> %mm1) nounwind  {
-entry:
-        %tmp = bitcast <1 x i64> %mm1 to x86_mmx
-	%tmp6 = tail call x86_mmx @llvm.x86.mmx.pslli.q( x86_mmx %tmp, i32 32 )		; <x86_mmx> [#uses=1]
-        %retval1112 = bitcast x86_mmx %tmp6 to i64
-	ret i64 %retval1112
-
-; CHECK-LABEL: t1:
-; CHECK: psllq $32
-}
-
-declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32) nounwind readnone 
-
-define i64 @t2(x86_mmx %mm1, x86_mmx %mm2) nounwind  {
-entry:
-	%tmp7 = tail call x86_mmx @llvm.x86.mmx.psra.d( x86_mmx %mm1, x86_mmx %mm2 ) nounwind readnone 		; <x86_mmx> [#uses=1]
-        %retval1112 = bitcast x86_mmx %tmp7 to i64
-	ret i64 %retval1112
-
-; CHECK-LABEL: t2:
-; CHECK: psrad
-}
-
-declare x86_mmx @llvm.x86.mmx.psra.d(x86_mmx, x86_mmx) nounwind readnone 
-
-define i64 @t3(x86_mmx %mm1, i32 %bits) nounwind  {
-entry:
-	%tmp8 = tail call x86_mmx @llvm.x86.mmx.psrli.w( x86_mmx %mm1, i32 %bits ) nounwind readnone 		; <x86_mmx> [#uses=1]
-        %retval1314 = bitcast x86_mmx %tmp8 to i64
-	ret i64 %retval1314
-
-; CHECK-LABEL: t3:
-; CHECK: psrlw
-}
-
-declare x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx, i32) nounwind readnone 
diff --git a/test/CodeGen/X86/mmx-shuffle.ll b/test/CodeGen/X86/mmx-shuffle.ll
deleted file mode 100644
index 869f32b89fb7..000000000000
--- a/test/CodeGen/X86/mmx-shuffle.ll
+++ /dev/null
@@ -1,31 +0,0 @@
-; RUN: llc < %s -mcpu=yonah
-; PR1427
-
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
-target triple = "i686-pc-linux-gnu"
-	%struct.DrawHelper = type { void (i32, %struct.QT_FT_Span*, i8*)*, void (i32, %struct.QT_FT_Span*, i8*)*, void (%struct.QRasterBuffer*, i32, i32, i32, i8*, i32, i32, i32)*, void (%struct.QRasterBuffer*, i32, i32, i32, i8*, i32, i32, i32)*, void (%struct.QRasterBuffer*, i32, i32, i32, i32, i32)* }
-	%struct.QBasicAtomic = type { i32 }
-	%struct.QClipData = type { i32, %"struct.QClipData::ClipLine"*, i32, i32, %struct.QT_FT_Span*, i32, i32, i32, i32 }
-	%"struct.QClipData::ClipLine" = type { i32, %struct.QT_FT_Span* }
-	%struct.QRasterBuffer = type { %struct.QRect, %struct.QRegion, %struct.QClipData*, %struct.QClipData*, i8, i32, i32, %struct.DrawHelper*, i32, i32, i32, i8* }
-	%struct.QRect = type { i32, i32, i32, i32 }
-	%struct.QRegion = type { %"struct.QRegion::QRegionData"* }
-	%"struct.QRegion::QRegionData" = type { %struct.QBasicAtomic, %struct._XRegion*, i8*, %struct.QRegionPrivate* }
-	%struct.QRegionPrivate = type opaque
-	%struct.QT_FT_Span = type { i16, i16, i16, i8 }
-	%struct._XRegion = type opaque
-
-define void @_Z19qt_bitmapblit16_sseP13QRasterBufferiijPKhiii(%struct.QRasterBuffer* %rasterBuffer, i32 %x, i32 %y, i32 %color, i8* %src, i32 %width, i32 %height, i32 %stride) {
-entry:
-	%tmp528 = bitcast <8 x i8> zeroinitializer to <2 x i32>		; <<2 x i32>> [#uses=1]
-	%tmp529 = and <2 x i32> %tmp528, bitcast (<4 x i16> < i16 -32640, i16 16448, i16 8224, i16 4112 > to <2 x i32>)		; <<2 x i32>> [#uses=1]
-	%tmp542 = bitcast <2 x i32> %tmp529 to <4 x i16>		; <<4 x i16>> [#uses=1]
-	%tmp543 = add <4 x i16> %tmp542, < i16 0, i16 16448, i16 24672, i16 28784 >		; <<4 x i16>> [#uses=1]
-	%tmp555 = bitcast <4 x i16> %tmp543 to <8 x i8>		; <<8 x i8>> [#uses=1]
-        %tmp556 = bitcast <8 x i8> %tmp555 to x86_mmx
-        %tmp557 = bitcast <8 x i8> zeroinitializer to x86_mmx
-	tail call void @llvm.x86.mmx.maskmovq( x86_mmx %tmp557, x86_mmx %tmp556, i8* null )
-	ret void
-}
-
-declare void @llvm.x86.mmx.maskmovq(x86_mmx, x86_mmx, i8*)
diff --git a/test/CodeGen/X86/movbe.ll b/test/CodeGen/X86/movbe.ll
index e248410b2020..49e765de2e77 100644
--- a/test/CodeGen/X86/movbe.ll
+++ b/test/CodeGen/X86/movbe.ll
@@ -16,7 +16,7 @@ define void @test1(i16* nocapture %x, i16 %y) nounwind {
 }
 
 define i16 @test2(i16* %x) nounwind {
-  %load = load i16* %x, align 2
+  %load = load i16, i16* %x, align 2
   %bswap = call i16 @llvm.bswap.i16(i16 %load)
   ret i16 %bswap
 ; CHECK-LABEL: test2:
@@ -36,7 +36,7 @@ define void @test3(i32* nocapture %x, i32 %y) nounwind {
 }
 
 define i32 @test4(i32* %x) nounwind {
-  %load = load i32* %x, align 4
+  %load = load i32, i32* %x, align 4
   %bswap = call i32 @llvm.bswap.i32(i32 %load)
   ret i32 %bswap
 ; CHECK-LABEL: test4:
@@ -56,7 +56,7 @@ define void @test5(i64* %x, i64 %y) nounwind {
 }
 
 define i64 @test6(i64* %x) nounwind {
-  %load = load i64* %x, align 8
+  %load = load i64, i64* %x, align 8
   %bswap = call i64 @llvm.bswap.i64(i64 %load)
   ret i64 %bswap
 ; CHECK-LABEL: test6:
diff --git a/test/CodeGen/X86/movfs.ll b/test/CodeGen/X86/movfs.ll
index 823e98689e7d..75b2404ec56e 100644
--- a/test/CodeGen/X86/movfs.ll
+++ b/test/CodeGen/X86/movfs.ll
@@ -2,7 +2,7 @@
 
 define i32 @foo() nounwind readonly {
 entry:
-	%tmp = load i32* addrspace(257)* getelementptr (i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31)		; <i32*> [#uses=1]
-	%tmp1 = load i32* %tmp		; <i32> [#uses=1]
+	%tmp = load i32*, i32* addrspace(257)* getelementptr (i32*, i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31)		; <i32*> [#uses=1]
+	%tmp1 = load i32, i32* %tmp		; <i32> [#uses=1]
 	ret i32 %tmp1
 }
diff --git a/test/CodeGen/X86/movgs.ll b/test/CodeGen/X86/movgs.ll
index 96c5dbb8ea98..07d497b9f0a9 100644
--- a/test/CodeGen/X86/movgs.ll
+++ b/test/CodeGen/X86/movgs.ll
@@ -15,8 +15,8 @@ define i32 @test1() nounwind readonly {
 ; X64-NEXT:    movl (%rax), %eax
 ; X64-NEXT:    retq
 entry:
-	%tmp = load i32* addrspace(256)* getelementptr (i32* addrspace(256)* inttoptr (i32 72 to i32* addrspace(256)*), i32 31)		; <i32*> [#uses=1]
-	%tmp1 = load i32* %tmp		; <i32> [#uses=1]
+	%tmp = load i32*, i32* addrspace(256)* getelementptr (i32*, i32* addrspace(256)* inttoptr (i32 72 to i32* addrspace(256)*), i32 31)		; <i32*> [#uses=1]
+	%tmp1 = load i32, i32* %tmp		; <i32> [#uses=1]
 	ret i32 %tmp1
 }
 
@@ -39,7 +39,7 @@ define i64 @test2(void (i8*)* addrspace(256)* %tmp8) nounwind {
 ; X64-NEXT:    {{(addq.*%rsp|popq)}}
 ; X64-NEXT:    retq
 entry:
-  %tmp9 = load void (i8*)* addrspace(256)* %tmp8, align 8
+  %tmp9 = load void (i8*)*, void (i8*)* addrspace(256)* %tmp8, align 8
   tail call void %tmp9(i8* undef) nounwind optsize
   ret i64 0
 }
@@ -56,7 +56,7 @@ define <2 x i64> @pmovsxwd_1(i64 addrspace(256)* %p) nounwind readonly {
 ; X64-NEXT:    pmovsxwd %gs:(%{{(rcx|rdi)}}), %xmm0
 ; X64-NEXT:    retq
 entry:
-  %0 = load i64 addrspace(256)* %p
+  %0 = load i64, i64 addrspace(256)* %p
   %tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0
   %1 = bitcast <2 x i64> %tmp2 to <8 x i16>
   %2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone
@@ -83,10 +83,10 @@ define i32 @test_no_cse() nounwind readonly {
 ; X64-NEXT:    addl (%rcx), %eax
 ; X64-NEXT:    retq
 entry:
-	%tmp = load i32* addrspace(256)* getelementptr (i32* addrspace(256)* inttoptr (i32 72 to i32* addrspace(256)*), i32 31)		; <i32*> [#uses=1]
-	%tmp1 = load i32* %tmp		; <i32> [#uses=1]
-	%tmp2 = load i32* addrspace(257)* getelementptr (i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31)		; <i32*> [#uses=1]
-	%tmp3 = load i32* %tmp2		; <i32> [#uses=1]
+	%tmp = load i32*, i32* addrspace(256)* getelementptr (i32*, i32* addrspace(256)* inttoptr (i32 72 to i32* addrspace(256)*), i32 31)		; <i32*> [#uses=1]
+	%tmp1 = load i32, i32* %tmp		; <i32> [#uses=1]
+	%tmp2 = load i32*, i32* addrspace(257)* getelementptr (i32*, i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31)		; <i32*> [#uses=1]
+	%tmp3 = load i32, i32* %tmp2		; <i32> [#uses=1]
 	%tmp4 = add i32 %tmp1, %tmp3
 	ret i32 %tmp4
 }
diff --git a/test/CodeGen/X86/movmsk.ll b/test/CodeGen/X86/movmsk.ll
index 25206621077b..a7ebebca4b72 100644
--- a/test/CodeGen/X86/movmsk.ll
+++ b/test/CodeGen/X86/movmsk.ll
@@ -13,7 +13,7 @@ entry:
   %0 = bitcast double* %__x.addr.i to i8*
   %1 = bitcast %0* %__u.i to i8*
   store double %d1, double* %__x.addr.i, align 8
-  %__f.i = getelementptr inbounds %0* %__u.i, i64 0, i32 0
+  %__f.i = getelementptr inbounds %0, %0* %__u.i, i64 0, i32 0
   store double %d1, double* %__f.i, align 8
   %tmp = bitcast double %d1 to i64
 ; CHECK-NOT: shr
@@ -32,7 +32,7 @@ entry:
   %0 = bitcast double* %__x.addr.i to i8*
   %1 = bitcast %0* %__u.i to i8*
   store double %add, double* %__x.addr.i, align 8
-  %__f.i = getelementptr inbounds %0* %__u.i, i64 0, i32 0
+  %__f.i = getelementptr inbounds %0, %0* %__u.i, i64 0, i32 0
   store double %add, double* %__f.i, align 8
   %tmp = bitcast double %add to i64
 ; CHECK-NOT: shr
@@ -50,7 +50,7 @@ entry:
   %0 = bitcast float* %__x.addr.i to i8*
   %1 = bitcast %union.anon* %__u.i to i8*
   store float %f1, float* %__x.addr.i, align 4
-  %__f.i = getelementptr inbounds %union.anon* %__u.i, i64 0, i32 0
+  %__f.i = getelementptr inbounds %union.anon, %union.anon* %__u.i, i64 0, i32 0
   store float %f1, float* %__f.i, align 4
   %2 = bitcast float %f1 to i32
 ; CHECK-NOT: shr
@@ -68,7 +68,7 @@ entry:
   %0 = bitcast float* %__x.addr.i to i8*
   %1 = bitcast %union.anon* %__u.i to i8*
   store float %add, float* %__x.addr.i, align 4
-  %__f.i = getelementptr inbounds %union.anon* %__u.i, i64 0, i32 0
+  %__f.i = getelementptr inbounds %union.anon, %union.anon* %__u.i, i64 0, i32 0
   store float %add, float* %__f.i, align 4
   %2 = bitcast float %add to i32
 ; CHECK-NOT: shr
@@ -104,8 +104,8 @@ entry:
 ; CHECK-NOT: movslq
   %0 = tail call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %x) nounwind
   %idxprom = sext i32 %0 to i64
-  %arrayidx = getelementptr inbounds i32* %indexTable, i64 %idxprom
-  %1 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %indexTable, i64 %idxprom
+  %1 = load i32, i32* %arrayidx, align 4
   ret i32 %1
 }
 
@@ -117,8 +117,8 @@ entry:
   %0 = bitcast <4 x float> %x to <2 x double>
   %1 = tail call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %0) nounwind
   %idxprom = sext i32 %1 to i64
-  %arrayidx = getelementptr inbounds i32* %indexTable, i64 %idxprom
-  %2 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %indexTable, i64 %idxprom
+  %2 = load i32, i32* %arrayidx, align 4
   ret i32 %2
 }
 
diff --git a/test/CodeGen/X86/movtopush.ll b/test/CodeGen/X86/movtopush.ll
index cb48ed747be4..f89e52457f35 100644
--- a/test/CodeGen/X86/movtopush.ll
+++ b/test/CodeGen/X86/movtopush.ll
@@ -1,24 +1,68 @@
 ; RUN: llc < %s -mtriple=i686-windows | FileCheck %s -check-prefix=NORMAL
+; RUN: llc < %s -mtriple=x86_64-windows | FileCheck %s -check-prefix=X64
 ; RUN: llc < %s -mtriple=i686-windows -force-align-stack -stack-alignment=32 | FileCheck %s -check-prefix=ALIGNED 
+
 declare void @good(i32 %a, i32 %b, i32 %c, i32 %d)
 declare void @inreg(i32 %a, i32 inreg %b, i32 %c, i32 %d)
+declare void @oneparam(i32 %a)
+declare void @eightparams(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h)
+
 
 ; Here, we should have a reserved frame, so we don't expect pushes
-; NORMAL-LABEL: test1
+; NORMAL-LABEL: test1:
 ; NORMAL: subl    $16, %esp
 ; NORMAL-NEXT: movl    $4, 12(%esp)
 ; NORMAL-NEXT: movl    $3, 8(%esp)
 ; NORMAL-NEXT: movl    $2, 4(%esp)
 ; NORMAL-NEXT: movl    $1, (%esp)
 ; NORMAL-NEXT: call
+; NORMAL-NEXT: addl $16, %esp
 define void @test1() {
 entry:
   call void @good(i32 1, i32 2, i32 3, i32 4)
   ret void
 }
 
-; Here, we expect a sequence of 4 immediate pushes
-; NORMAL-LABEL: test2
+; We're optimizing for code size, so we should get pushes for x86,
+; even though there is a reserved call frame.
+; Make sure we don't touch x86-64
+; NORMAL-LABEL: test1b:
+; NORMAL-NOT: subl {{.*}} %esp
+; NORMAL: pushl   $4
+; NORMAL-NEXT: pushl   $3
+; NORMAL-NEXT: pushl   $2
+; NORMAL-NEXT: pushl   $1
+; NORMAL-NEXT: call
+; NORMAL-NEXT: addl $16, %esp
+; X64-LABEL: test1b:
+; X64: movl    $1, %ecx
+; X64-NEXT: movl    $2, %edx
+; X64-NEXT: movl    $3, %r8d
+; X64-NEXT: movl    $4, %r9d
+; X64-NEXT: callq   good
+define void @test1b() optsize {
+entry:
+  call void @good(i32 1, i32 2, i32 3, i32 4)
+  ret void
+}
+
+; Same as above, but for minsize
+; NORMAL-LABEL: test1c:
+; NORMAL-NOT: subl {{.*}} %esp
+; NORMAL: pushl   $4
+; NORMAL-NEXT: pushl   $3
+; NORMAL-NEXT: pushl   $2
+; NORMAL-NEXT: pushl   $1
+; NORMAL-NEXT: call
+; NORMAL-NEXT: addl $16, %esp
+define void @test1c() minsize {
+entry:
+  call void @good(i32 1, i32 2, i32 3, i32 4)
+  ret void
+}
+
+; If we have a reserved frame, we should have pushes
+; NORMAL-LABEL: test2:
 ; NORMAL-NOT: subl {{.*}} %esp
 ; NORMAL: pushl   $4
 ; NORMAL-NEXT: pushl   $3
@@ -34,53 +78,54 @@ entry:
 
 ; Again, we expect a sequence of 4 immediate pushes
 ; Checks that we generate the right pushes for >8bit immediates
-; NORMAL-LABEL: test2b
+; NORMAL-LABEL: test2b:
 ; NORMAL-NOT: subl {{.*}} %esp
 ; NORMAL: pushl   $4096
 ; NORMAL-NEXT: pushl   $3072
 ; NORMAL-NEXT: pushl   $2048
 ; NORMAL-NEXT: pushl   $1024
 ; NORMAL-NEXT: call
-define void @test2b(i32 %k) {
+; NORMAL-NEXT: addl $16, %esp
+define void @test2b() optsize {
 entry:
-  %a = alloca i32, i32 %k
   call void @good(i32 1024, i32 2048, i32 3072, i32 4096)
   ret void
 }
 
 ; The first push should push a register
-; NORMAL-LABEL: test3
+; NORMAL-LABEL: test3:
 ; NORMAL-NOT: subl {{.*}} %esp
 ; NORMAL: pushl   $4
 ; NORMAL-NEXT: pushl   $3
 ; NORMAL-NEXT: pushl   $2
 ; NORMAL-NEXT: pushl   %e{{..}}
 ; NORMAL-NEXT: call
-define void @test3(i32 %k) {
+; NORMAL-NEXT: addl $16, %esp
+define void @test3(i32 %k) optsize {
 entry:
-  %a = alloca i32, i32 %k
-  call void @good(i32 %k, i32 2, i32 3, i32 4)
+  %f = add i32 %k, 1
+  call void @good(i32 %f, i32 2, i32 3, i32 4)
   ret void
 }
 
 ; We don't support weird calling conventions
-; NORMAL-LABEL: test4
+; NORMAL-LABEL: test4:
 ; NORMAL: subl    $12, %esp
 ; NORMAL-NEXT: movl    $4, 8(%esp)
 ; NORMAL-NEXT: movl    $3, 4(%esp)
 ; NORMAL-NEXT: movl    $1, (%esp)
 ; NORMAL-NEXT: movl    $2, %eax
 ; NORMAL-NEXT: call
-define void @test4(i32 %k) {
+; NORMAL-NEXT: addl $12, %esp
+define void @test4() optsize {
 entry:
-  %a = alloca i32, i32 %k
   call void @inreg(i32 1, i32 2, i32 3, i32 4)
   ret void
 }
 
-; Check that additional alignment is added when the pushes
-; don't add up to the required alignment.
-; ALIGNED-LABEL: test5
+; When there is no reserved call frame, check that additional alignment
+; is added when the pushes don't add up to the required alignment.
+; ALIGNED-LABEL: test5:
 ; ALIGNED: subl    $16, %esp
 ; ALIGNED-NEXT: pushl   $4
 ; ALIGNED-NEXT: pushl   $3
@@ -94,10 +139,38 @@ entry:
   ret void
 }
 
+; When the alignment adds up, do the transformation
+; ALIGNED-LABEL: test5b:
+; ALIGNED: pushl   $8
+; ALIGNED-NEXT: pushl   $7
+; ALIGNED-NEXT: pushl   $6
+; ALIGNED-NEXT: pushl   $5
+; ALIGNED-NEXT: pushl   $4
+; ALIGNED-NEXT: pushl   $3
+; ALIGNED-NEXT: pushl   $2
+; ALIGNED-NEXT: pushl   $1
+; ALIGNED-NEXT: call
+define void @test5b() optsize {
+entry:
+  call void @eightparams(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8)
+  ret void
+}
+
+; When having to compensate for the alignment isn't worth it,
+; don't use pushes.
+; ALIGNED-LABEL: test5c:
+; ALIGNED: movl $1, (%esp)
+; ALIGNED-NEXT: call
+define void @test5c() optsize {
+entry:
+  call void @oneparam(i32 1)
+  ret void
+}
+
 ; Check that pushing the addresses of globals (Or generally, things that 
 ; aren't exactly immediates) isn't broken.
 ; Fixes PR21878.
-; NORMAL-LABEL: test6
+; NORMAL-LABEL: test6:
 ; NORMAL: pushl    $_ext
 ; NORMAL-NEXT: call
 declare void @f(i8*)
@@ -110,3 +183,164 @@ bb:
   alloca i32
   ret void
 }
+
+; Check that we fold simple cases into the push
+; NORMAL-LABEL: test7:
+; NORMAL-NOT: subl {{.*}} %esp
+; NORMAL: movl 4(%esp), [[EAX:%e..]]
+; NORMAL-NEXT: pushl   $4
+; NORMAL-NEXT: pushl   ([[EAX]])
+; NORMAL-NEXT: pushl   $2
+; NORMAL-NEXT: pushl   $1
+; NORMAL-NEXT: call
+; NORMAL-NEXT: addl $16, %esp
+define void @test7(i32* %ptr) optsize {
+entry:
+  %val = load i32, i32* %ptr
+  call void @good(i32 1, i32 2, i32 %val, i32 4)
+  ret void
+}
+
+; Fold stack-relative loads into the push, with correct offset
+; In particular, at the second push, %b was at 12(%esp) and
+; %a wast at 8(%esp), but the second push bumped %esp, so %a
+; is now it at 12(%esp)
+; NORMAL-LABEL: test8:
+; NORMAL: pushl   $4
+; NORMAL-NEXT: pushl   12(%esp)
+; NORMAL-NEXT: pushl   12(%esp)
+; NORMAL-NEXT: pushl   $1
+; NORMAL-NEXT: call
+; NORMAL-NEXT: addl $16, %esp
+define void @test8(i32 %a, i32 %b) optsize {
+entry:
+  call void @good(i32 1, i32 %a, i32 %b, i32 4)
+  ret void
+}
+
+; If one function is using push instructions, and the other isn't
+; (because it has frame-index references), then we must resolve
+; these references correctly.
+; NORMAL-LABEL: test9:
+; NORMAL-NOT: leal (%esp), 
+; NORMAL: pushl $4
+; NORMAL-NEXT: pushl $3
+; NORMAL-NEXT: pushl $2
+; NORMAL-NEXT: pushl $1
+; NORMAL-NEXT: call
+; NORMAL-NEXT: addl $16, %esp
+; NORMAL-NEXT: subl $16, %esp
+; NORMAL-NEXT: leal 16(%esp), [[EAX:%e..]]
+; NORMAL-NEXT: movl    [[EAX]], 12(%esp)
+; NORMAL-NEXT: movl    $7, 8(%esp)
+; NORMAL-NEXT: movl    $6, 4(%esp)
+; NORMAL-NEXT: movl    $5, (%esp)
+; NORMAL-NEXT: call
+; NORMAL-NEXT: addl $16, %esp
+define void @test9() optsize {
+entry:
+  %p = alloca i32, align 4
+  call void @good(i32 1, i32 2, i32 3, i32 4)
+  %0 = ptrtoint i32* %p to i32
+  call void @good(i32 5, i32 6, i32 7, i32 %0)
+  ret void
+}
+
+; We can end up with an indirect call which gets reloaded on the spot.
+; Make sure we reference the correct stack slot - we spill into (%esp)
+; and reload from 16(%esp) due to the pushes.
+; NORMAL-LABEL: test10:
+; NORMAL: movl $_good, [[ALLOC:.*]]
+; NORMAL-NEXT: movl [[ALLOC]], [[EAX:%e..]]
+; NORMAL-NEXT: movl [[EAX]], (%esp) # 4-byte Spill
+; NORMAL: nop
+; NORMAL: pushl $4
+; NORMAL-NEXT: pushl $3
+; NORMAL-NEXT: pushl $2
+; NORMAL-NEXT: pushl $1
+; NORMAL-NEXT: calll *16(%esp)
+; NORMAL-NEXT: addl $16, %esp
+define void @test10() optsize {
+  %stack_fptr = alloca void (i32, i32, i32, i32)*
+  store void (i32, i32, i32, i32)* @good, void (i32, i32, i32, i32)** %stack_fptr
+  %good_ptr = load volatile void (i32, i32, i32, i32)*, void (i32, i32, i32, i32)** %stack_fptr
+  call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di}"()
+  call void (i32, i32, i32, i32) %good_ptr(i32 1, i32 2, i32 3, i32 4)
+  ret void
+}
+
+; We can't fold the load from the global into the push because of 
+; interference from the store
+; NORMAL-LABEL: test11:
+; NORMAL: movl    _the_global, [[EAX:%e..]]
+; NORMAL-NEXT: movl    $42, _the_global
+; NORMAL-NEXT: pushl $4
+; NORMAL-NEXT: pushl $3
+; NORMAL-NEXT: pushl $2
+; NORMAL-NEXT: pushl [[EAX]]
+; NORMAL-NEXT: call
+; NORMAL-NEXT: addl $16, %esp
+@the_global = external global i32
+define void @test11() optsize {
+  %myload = load i32, i32* @the_global
+  store i32 42, i32* @the_global
+  call void @good(i32 %myload, i32 2, i32 3, i32 4)
+  ret void
+}
+
+; Converting one mov into a push isn't worth it when 
+; doing so forces too much overhead for other calls.
+; NORMAL-LABEL: test12:
+; NORMAL: subl    $16, %esp
+; NORMAL-NEXT: movl    $4, 8(%esp)
+; NORMAL-NEXT: movl    $3, 4(%esp)
+; NORMAL-NEXT: movl    $1, (%esp)
+; NORMAL-NEXT: movl    $2, %eax
+; NORMAL-NEXT: calll _inreg
+; NORMAL-NEXT: movl    $8, 12(%esp)
+; NORMAL-NEXT: movl    $7, 8(%esp)
+; NORMAL-NEXT: movl    $6, 4(%esp)
+; NORMAL-NEXT: movl    $5, (%esp)
+; NORMAL-NEXT: calll _good
+; NORMAL-NEXT: movl    $12, 8(%esp)
+; NORMAL-NEXT: movl    $11, 4(%esp)
+; NORMAL-NEXT: movl    $9, (%esp)
+; NORMAL-NEXT: movl    $10, %eax
+; NORMAL-NEXT: calll _inreg
+; NORMAL-NEXT: addl $16, %esp
+define void @test12() optsize {
+entry:
+  call void @inreg(i32 1, i32 2, i32 3, i32 4)
+  call void @good(i32 5, i32 6, i32 7, i32 8)
+  call void @inreg(i32 9, i32 10, i32 11, i32 12)
+  ret void
+}
+
+; But if the gains outweigh the overhead, we should do it
+; NORMAL-LABEL: test12b:
+; NORMAL: pushl    $4
+; NORMAL-NEXT: pushl    $3
+; NORMAL-NEXT: pushl    $2
+; NORMAL-NEXT: pushl    $1
+; NORMAL-NEXT: calll _good
+; NORMAL-NEXT: addl    $16, %esp
+; NORMAL-NEXT: subl    $12, %esp
+; NORMAL-NEXT: movl    $8, 8(%esp)
+; NORMAL-NEXT: movl    $7, 4(%esp)
+; NORMAL-NEXT: movl    $5, (%esp)
+; NORMAL-NEXT: movl    $6, %eax
+; NORMAL-NEXT: calll _inreg
+; NORMAL-NEXT: addl    $12, %esp
+; NORMAL-NEXT: pushl    $12
+; NORMAL-NEXT: pushl    $11
+; NORMAL-NEXT: pushl    $10
+; NORMAL-NEXT: pushl    $9
+; NORMAL-NEXT: calll _good
+; NORMAL-NEXT: addl $16, %esp
+define void @test12b() optsize {
+entry:
+  call void @good(i32 1, i32 2, i32 3, i32 4)
+  call void @inreg(i32 5, i32 6, i32 7, i32 8)
+  call void @good(i32 9, i32 10, i32 11, i32 12)
+  ret void
+}
diff --git a/test/CodeGen/X86/ms-inline-asm.ll b/test/CodeGen/X86/ms-inline-asm.ll
index f0bdbba50ef3..428eb1b7190b 100644
--- a/test/CodeGen/X86/ms-inline-asm.ll
+++ b/test/CodeGen/X86/ms-inline-asm.ll
@@ -44,13 +44,13 @@ entry:
 define i32 @t18() nounwind {
 entry:
   %foo = alloca %struct.t18_type, align 4
-  %a = getelementptr inbounds %struct.t18_type* %foo, i32 0, i32 0
+  %a = getelementptr inbounds %struct.t18_type, %struct.t18_type* %foo, i32 0, i32 0
   store i32 1, i32* %a, align 4
-  %b = getelementptr inbounds %struct.t18_type* %foo, i32 0, i32 1
+  %b = getelementptr inbounds %struct.t18_type, %struct.t18_type* %foo, i32 0, i32 1
   store i32 2, i32* %b, align 4
   call void asm sideeffect inteldialect "lea ebx, foo\0A\09mov eax, [ebx].0\0A\09mov [ebx].4, ecx", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
-  %b1 = getelementptr inbounds %struct.t18_type* %foo, i32 0, i32 1
-  %0 = load i32* %b1, align 4
+  %b1 = getelementptr inbounds %struct.t18_type, %struct.t18_type* %foo, i32 0, i32 1
+  %0 = load i32, i32* %b1, align 4
   ret i32 %0
 ; CHECK: t18
 ; CHECK: {{## InlineAsm Start|#APP}}
@@ -87,7 +87,7 @@ entry:
   %res = alloca i32*, align 4
   call void asm sideeffect inteldialect "lea edi, dword ptr $0", "*m,~{edi},~{dirflag},~{fpsr},~{flags}"([2 x i32]* @results) nounwind
   call void asm sideeffect inteldialect "mov dword ptr $0, edi", "=*m,~{dirflag},~{fpsr},~{flags}"(i32** %res) nounwind
-  %0 = load i32** %res, align 4
+  %0 = load i32*, i32** %res, align 4
   ret i32* %0
 ; CHECK-LABEL: t30:
 ; CHECK: {{## InlineAsm Start|#APP}}
@@ -111,7 +111,7 @@ entry:
   %val = alloca i32, align 64
   store i32 -1, i32* %val, align 64
   call void asm sideeffect inteldialect "mov dword ptr $0, esp", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %val)
-  %sp = load i32* %val, align 64
+  %sp = load i32, i32* %val, align 64
   ret i32 %sp
 ; CHECK-LABEL: t31:
 ; CHECK: pushl %ebp
diff --git a/test/CodeGen/X86/mul128_sext_loop.ll b/test/CodeGen/X86/mul128_sext_loop.ll
index a516f03cbc3e..efb7e02720b4 100644
--- a/test/CodeGen/X86/mul128_sext_loop.ll
+++ b/test/CodeGen/X86/mul128_sext_loop.ll
@@ -14,8 +14,8 @@ define void @test(i64* nocapture %arr, i64 %arrsize, i64 %factor) nounwind uwtab
 ; CHECK-NOT: mul
   %carry.02 = phi i128 [ 0, %.lr.ph ], [ %10, %3 ]
   %i.01 = phi i64 [ 0, %.lr.ph ], [ %11, %3 ]
-  %4 = getelementptr inbounds i64* %arr, i64 %i.01
-  %5 = load i64* %4, align 8
+  %4 = getelementptr inbounds i64, i64* %arr, i64 %i.01
+  %5 = load i64, i64* %4, align 8
   %6 = sext i64 %5 to i128
   %7 = mul nsw i128 %6, %2
   %8 = add nsw i128 %7, %carry.02
diff --git a/test/CodeGen/X86/muloti.ll b/test/CodeGen/X86/muloti.ll
index 2f0986e831e2..6c6198e400fc 100644
--- a/test/CodeGen/X86/muloti.ll
+++ b/test/CodeGen/X86/muloti.ll
@@ -41,21 +41,21 @@ entry:
   %coerce1 = alloca i128, align 16
   %b.addr = alloca i128, align 16
   %0 = bitcast i128* %coerce to %0*
-  %1 = getelementptr %0* %0, i32 0, i32 0
+  %1 = getelementptr %0, %0* %0, i32 0, i32 0
   store i64 %a.coerce0, i64* %1
-  %2 = getelementptr %0* %0, i32 0, i32 1
+  %2 = getelementptr %0, %0* %0, i32 0, i32 1
   store i64 %a.coerce1, i64* %2
-  %a = load i128* %coerce, align 16
+  %a = load i128, i128* %coerce, align 16
   store i128 %a, i128* %a.addr, align 16
   %3 = bitcast i128* %coerce1 to %0*
-  %4 = getelementptr %0* %3, i32 0, i32 0
+  %4 = getelementptr %0, %0* %3, i32 0, i32 0
   store i64 %b.coerce0, i64* %4
-  %5 = getelementptr %0* %3, i32 0, i32 1
+  %5 = getelementptr %0, %0* %3, i32 0, i32 1
   store i64 %b.coerce1, i64* %5
-  %b = load i128* %coerce1, align 16
+  %b = load i128, i128* %coerce1, align 16
   store i128 %b, i128* %b.addr, align 16
-  %tmp = load i128* %a.addr, align 16
-  %tmp2 = load i128* %b.addr, align 16
+  %tmp = load i128, i128* %a.addr, align 16
+  %tmp2 = load i128, i128* %b.addr, align 16
   %6 = call %1 @llvm.umul.with.overflow.i128(i128 %tmp, i128 %tmp2)
 ; CHECK: cmov
 ; CHECK: divti3
@@ -70,7 +70,7 @@ overflow:                                         ; preds = %entry
 nooverflow:                                       ; preds = %entry
   store i128 %7, i128* %retval
   %9 = bitcast i128* %retval to %0*
-  %10 = load %0* %9, align 1
+  %10 = load %0, %0* %9, align 1
   ret %0 %10
 }
 
diff --git a/test/CodeGen/X86/mult-alt-generic-i686.ll b/test/CodeGen/X86/mult-alt-generic-i686.ll
index 54bc3a42f035..9ebdf55d0e03 100644
--- a/test/CodeGen/X86/mult-alt-generic-i686.ll
+++ b/test/CodeGen/X86/mult-alt-generic-i686.ll
@@ -33,10 +33,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,<r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,r<,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -48,10 +48,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,>r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,r>,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -63,7 +63,7 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
@@ -120,10 +120,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r,imr,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind
@@ -137,15 +137,15 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind
   store i32 %2, i32* %out0, align 4
-  %3 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %3 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %3, i32* %out0, align 4
   %4 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+001) nounwind
   store i32 %4, i32* %out0, align 4
@@ -158,14 +158,14 @@ define void @single_p() nounwind {
 entry:
   %out0 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
-  %0 = call i32 asm "foo $1,$0", "=r,im,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %0 = call i32 asm "foo $1,$0", "=r,im,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
 }
 
 define void @multi_m() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*m|r,m|r,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
@@ -190,10 +190,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|<r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|r<,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -205,10 +205,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|>r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|r>,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -220,7 +220,7 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|m,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
@@ -277,10 +277,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r|r,r|imr,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind
@@ -294,15 +294,15 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind
   store i32 %2, i32* %out0, align 4
-  %3 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %3 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %3, i32* %out0, align 4
   %4 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+001) nounwind
   store i32 %4, i32* %out0, align 4
@@ -315,7 +315,7 @@ define void @multi_p() nounwind {
 entry:
   %out0 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
-  %0 = call i32 asm "foo $1,$0", "=r|r,r|im,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %0 = call i32 asm "foo $1,$0", "=r|r,r|im,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
 }
diff --git a/test/CodeGen/X86/mult-alt-generic-x86_64.ll b/test/CodeGen/X86/mult-alt-generic-x86_64.ll
index 84a9c8140943..a87655e5eef3 100644
--- a/test/CodeGen/X86/mult-alt-generic-x86_64.ll
+++ b/test/CodeGen/X86/mult-alt-generic-x86_64.ll
@@ -33,10 +33,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,<r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,r<,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -48,10 +48,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,>r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,r>,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -63,7 +63,7 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
@@ -120,10 +120,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r,imr,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind
@@ -137,15 +137,15 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind
   store i32 %2, i32* %out0, align 4
-  %3 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %3 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %3, i32* %out0, align 4
   %4 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+001) nounwind
   store i32 %4, i32* %out0, align 4
@@ -158,14 +158,14 @@ define void @single_p() nounwind {
 entry:
   %out0 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
-  %0 = call i32 asm "foo $1,$0", "=r,im,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %0 = call i32 asm "foo $1,$0", "=r,im,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
 }
 
 define void @multi_m() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*m|r,m|r,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
@@ -190,10 +190,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|<r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|r<,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -205,10 +205,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|>r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* %in1, align 4
+  %tmp1 = load i32, i32* %in1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|r>,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   ret void
@@ -220,7 +220,7 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|m,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
@@ -277,10 +277,10 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r|r,r|imr,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind
@@ -294,15 +294,15 @@ entry:
   %in1 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
   store i32 1, i32* %in1, align 4
-  %tmp = load i32* %in1, align 4
+  %tmp = load i32, i32* %in1, align 4
   %0 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* %out0, align 4
-  %tmp1 = load i32* @min1, align 4
+  %tmp1 = load i32, i32* @min1, align 4
   %1 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind
   store i32 %1, i32* %out0, align 4
   %2 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind
   store i32 %2, i32* %out0, align 4
-  %3 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %3 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %3, i32* %out0, align 4
   %4 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+001) nounwind
   store i32 %4, i32* %out0, align 4
@@ -315,7 +315,7 @@ define void @multi_p() nounwind {
 entry:
   %out0 = alloca i32, align 4
   store i32 0, i32* %out0, align 4
-  %0 = call i32 asm "foo $1,$0", "=r|r,r|im,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind
+  %0 = call i32 asm "foo $1,$0", "=r|r,r|im,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
   store i32 %0, i32* %out0, align 4
   ret void
 }
diff --git a/test/CodeGen/X86/mult-alt-x86.ll b/test/CodeGen/X86/mult-alt-x86.ll
index cb2219a6ed75..5174f85adb9f 100644
--- a/test/CodeGen/X86/mult-alt-x86.ll
+++ b/test/CodeGen/X86/mult-alt-x86.ll
@@ -11,7 +11,7 @@ target triple = "i686-pc-win32"
 
 define void @single_R() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   %0 = call i32 asm "foo $1,$0", "=R,R,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* @mout0, align 4
   ret void
@@ -19,7 +19,7 @@ entry:
 
 define void @single_q() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   %0 = call i32 asm "foo $1,$0", "=q,q,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* @mout0, align 4
   ret void
@@ -27,7 +27,7 @@ entry:
 
 define void @single_Q() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   %0 = call i32 asm "foo $1,$0", "=Q,Q,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* @mout0, align 4
   ret void
@@ -35,7 +35,7 @@ entry:
 
 define void @single_a() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   %0 = call i32 asm "foo $1,$0", "={ax},{ax},~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* @mout0, align 4
   ret void
@@ -43,7 +43,7 @@ entry:
 
 define void @single_b() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   %0 = call i32 asm "foo $1,$0", "={bx},{bx},~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* @mout0, align 4
   ret void
@@ -51,7 +51,7 @@ entry:
 
 define void @single_c() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   %0 = call i32 asm "foo $1,$0", "={cx},{cx},~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* @mout0, align 4
   ret void
@@ -59,7 +59,7 @@ entry:
 
 define void @single_d() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   %0 = call i32 asm "foo $1,$0", "={dx},{dx},~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* @mout0, align 4
   ret void
@@ -67,7 +67,7 @@ entry:
 
 define void @single_S() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   %0 = call i32 asm "foo $1,$0", "={si},{si},~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* @mout0, align 4
   ret void
@@ -75,7 +75,7 @@ entry:
 
 define void @single_D() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   %0 = call i32 asm "foo $1,$0", "={di},{di},~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* @mout0, align 4
   ret void
@@ -83,7 +83,7 @@ entry:
 
 define void @single_A() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   %0 = call i32 asm "foo $1,$0", "=A,A,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind
   store i32 %0, i32* @mout0, align 4
   ret void
@@ -106,7 +106,7 @@ entry:
 
 define void @single_y() nounwind {
 entry:
-  %tmp = load double* @din1, align 8
+  %tmp = load double, double* @din1, align 8
   %0 = call double asm "foo $1,$0", "=y,y,~{dirflag},~{fpsr},~{flags}"(double %tmp) nounwind
   store double %0, double* @dout0, align 8
   ret void
@@ -114,7 +114,7 @@ entry:
 
 define void @single_x() nounwind {
 entry:
-  %tmp = load double* @din1, align 8
+  %tmp = load double, double* @din1, align 8
   %0 = call double asm "foo $1,$0", "=x,x,~{dirflag},~{fpsr},~{flags}"(double %tmp) nounwind
   store double %0, double* @dout0, align 8
   ret void
@@ -191,70 +191,70 @@ entry:
 
 define void @multi_R() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*r|R|m,r|R|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
 
 define void @multi_q() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*r|q|m,r|q|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
 
 define void @multi_Q() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*r|Q|m,r|Q|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
 
 define void @multi_a() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*r|{ax}|m,r|{ax}|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
 
 define void @multi_b() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*r|{bx}|m,r|{bx}|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
 
 define void @multi_c() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*r|{cx}|m,r|{cx}|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
 
 define void @multi_d() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*r|{dx}|m,r|{dx},~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
 
 define void @multi_S() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*r|{si}|m,r|{si}|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
 
 define void @multi_D() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*r|{di}|m,r|{di}|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
 
 define void @multi_A() nounwind {
 entry:
-  %tmp = load i32* @min1, align 4
+  %tmp = load i32, i32* @min1, align 4
   call void asm "foo $1,$0", "=*r|A|m,r|A|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind
   ret void
 }
@@ -276,14 +276,14 @@ entry:
 
 define void @multi_y() nounwind {
 entry:
-  %tmp = load double* @din1, align 8
+  %tmp = load double, double* @din1, align 8
   call void asm "foo $1,$0", "=*r|y|m,r|y|m,~{dirflag},~{fpsr},~{flags}"(double* @dout0, double %tmp) nounwind
   ret void
 }
 
 define void @multi_x() nounwind {
 entry:
-  %tmp = load double* @din1, align 8
+  %tmp = load double, double* @din1, align 8
   call void asm "foo $1,$0", "=*r|x|m,r|x|m,~{dirflag},~{fpsr},~{flags}"(double* @dout0, double %tmp) nounwind
   ret void
 }
diff --git a/test/CodeGen/X86/multiple-loop-post-inc.ll b/test/CodeGen/X86/multiple-loop-post-inc.ll
index 4edc1ff0b3fa..be778da57332 100644
--- a/test/CodeGen/X86/multiple-loop-post-inc.ll
+++ b/test/CodeGen/X86/multiple-loop-post-inc.ll
@@ -19,7 +19,7 @@ define void @foo(float* %I, i64 %IS, float* nocapture %Start, float* nocapture %
 entry:
   %times4 = alloca float, align 4                 ; <float*> [#uses=3]
   %timesN = alloca float, align 4                 ; <float*> [#uses=2]
-  %0 = load float* %Step, align 4                 ; <float> [#uses=8]
+  %0 = load float, float* %Step, align 4                 ; <float> [#uses=8]
   %1 = ptrtoint float* %I to i64                  ; <i64> [#uses=1]
   %2 = ptrtoint float* %O to i64                  ; <i64> [#uses=1]
   %tmp = xor i64 %2, %1                           ; <i64> [#uses=1]
@@ -34,11 +34,11 @@ entry:
   br i1 %9, label %bb, label %return
 
 bb:                                               ; preds = %entry
-  %10 = load float* %Start, align 4               ; <float> [#uses=1]
+  %10 = load float, float* %Start, align 4               ; <float> [#uses=1]
   br label %bb2
 
 bb1:                                              ; preds = %bb3
-  %11 = load float* %I_addr.0, align 4            ; <float> [#uses=1]
+  %11 = load float, float* %I_addr.0, align 4            ; <float> [#uses=1]
   %12 = fmul float %11, %x.0                      ; <float> [#uses=1]
   store float %12, float* %O_addr.0, align 4
   %13 = fadd float %x.0, %0                       ; <float> [#uses=1]
@@ -49,8 +49,8 @@ bb2:                                              ; preds = %bb1, %bb
   %14 = phi i64 [ %indvar.next53, %bb1 ], [ 0, %bb ] ; <i64> [#uses=21]
   %x.0 = phi float [ %13, %bb1 ], [ %10, %bb ]    ; <float> [#uses=6]
   %N_addr.0 = sub i64 %N, %14                     ; <i64> [#uses=4]
-  %O_addr.0 = getelementptr float* %O, i64 %14    ; <float*> [#uses=4]
-  %I_addr.0 = getelementptr float* %I, i64 %14    ; <float*> [#uses=3]
+  %O_addr.0 = getelementptr float, float* %O, i64 %14    ; <float*> [#uses=4]
+  %I_addr.0 = getelementptr float, float* %I, i64 %14    ; <float*> [#uses=3]
   %15 = icmp slt i64 %N_addr.0, 1                 ; <i1> [#uses=1]
   br i1 %15, label %bb4, label %bb3
 
@@ -105,32 +105,32 @@ bb5:                                              ; preds = %bb.nph43, %bb5
   %vX1.036 = phi <4 x float> [ %32, %bb.nph43 ], [ %47, %bb5 ] ; <<4 x float>> [#uses=2]
   %tmp104 = shl i64 %indvar102, 4                 ; <i64> [#uses=5]
   %tmp105 = add i64 %14, %tmp104                  ; <i64> [#uses=2]
-  %scevgep106 = getelementptr float* %I, i64 %tmp105 ; <float*> [#uses=1]
+  %scevgep106 = getelementptr float, float* %I, i64 %tmp105 ; <float*> [#uses=1]
   %scevgep106107 = bitcast float* %scevgep106 to <4 x float>* ; <<4 x float>*> [#uses=1]
   %tmp109 = add i64 %tmp108, %tmp104              ; <i64> [#uses=2]
   %tmp112 = add i64 %tmp111, %tmp104              ; <i64> [#uses=2]
-  %scevgep113 = getelementptr float* %I, i64 %tmp112 ; <float*> [#uses=1]
+  %scevgep113 = getelementptr float, float* %I, i64 %tmp112 ; <float*> [#uses=1]
   %scevgep113114 = bitcast float* %scevgep113 to <4 x float>* ; <<4 x float>*> [#uses=1]
   %tmp116 = add i64 %tmp115, %tmp104              ; <i64> [#uses=2]
-  %scevgep117 = getelementptr float* %I, i64 %tmp116 ; <float*> [#uses=1]
+  %scevgep117 = getelementptr float, float* %I, i64 %tmp116 ; <float*> [#uses=1]
   %scevgep117118 = bitcast float* %scevgep117 to <4 x float>* ; <<4 x float>*> [#uses=1]
   %tmp120 = add i64 %tmp119, %tmp104              ; <i64> [#uses=2]
-  %scevgep121 = getelementptr float* %I, i64 %tmp120 ; <float*> [#uses=1]
+  %scevgep121 = getelementptr float, float* %I, i64 %tmp120 ; <float*> [#uses=1]
   %scevgep121122 = bitcast float* %scevgep121 to <4 x float>* ; <<4 x float>*> [#uses=1]
-  %scevgep123 = getelementptr float* %O, i64 %tmp105 ; <float*> [#uses=1]
+  %scevgep123 = getelementptr float, float* %O, i64 %tmp105 ; <float*> [#uses=1]
   %scevgep123124 = bitcast float* %scevgep123 to <4 x float>* ; <<4 x float>*> [#uses=1]
-  %scevgep126 = getelementptr float* %O, i64 %tmp112 ; <float*> [#uses=1]
+  %scevgep126 = getelementptr float, float* %O, i64 %tmp112 ; <float*> [#uses=1]
   %scevgep126127 = bitcast float* %scevgep126 to <4 x float>* ; <<4 x float>*> [#uses=1]
-  %scevgep128 = getelementptr float* %O, i64 %tmp116 ; <float*> [#uses=1]
+  %scevgep128 = getelementptr float, float* %O, i64 %tmp116 ; <float*> [#uses=1]
   %scevgep128129 = bitcast float* %scevgep128 to <4 x float>* ; <<4 x float>*> [#uses=1]
-  %scevgep130 = getelementptr float* %O, i64 %tmp120 ; <float*> [#uses=1]
+  %scevgep130 = getelementptr float, float* %O, i64 %tmp120 ; <float*> [#uses=1]
   %scevgep130131 = bitcast float* %scevgep130 to <4 x float>* ; <<4 x float>*> [#uses=1]
   %tmp132 = mul i64 %indvar102, -16               ; <i64> [#uses=1]
   %tmp136 = add i64 %tmp135, %tmp132              ; <i64> [#uses=2]
-  %36 = load <4 x float>* %scevgep106107, align 16 ; <<4 x float>> [#uses=1]
-  %37 = load <4 x float>* %scevgep113114, align 16 ; <<4 x float>> [#uses=1]
-  %38 = load <4 x float>* %scevgep117118, align 16 ; <<4 x float>> [#uses=1]
-  %39 = load <4 x float>* %scevgep121122, align 16 ; <<4 x float>> [#uses=1]
+  %36 = load <4 x float>, <4 x float>* %scevgep106107, align 16 ; <<4 x float>> [#uses=1]
+  %37 = load <4 x float>, <4 x float>* %scevgep113114, align 16 ; <<4 x float>> [#uses=1]
+  %38 = load <4 x float>, <4 x float>* %scevgep117118, align 16 ; <<4 x float>> [#uses=1]
+  %39 = load <4 x float>, <4 x float>* %scevgep121122, align 16 ; <<4 x float>> [#uses=1]
   %40 = fmul <4 x float> %36, %vX0.039            ; <<4 x float>> [#uses=1]
   %41 = fadd <4 x float> %vX0.039, %asmtmp.i18    ; <<4 x float>> [#uses=2]
   %42 = fmul <4 x float> %37, %vX1.036            ; <<4 x float>> [#uses=1]
@@ -149,8 +149,8 @@ bb5:                                              ; preds = %bb.nph43, %bb5
 
 bb6.bb7_crit_edge:                                ; preds = %bb5
   call void asm sideeffect "# Stop.", "~{dirflag},~{fpsr},~{flags}"() nounwind
-  %scevgep110 = getelementptr float* %I, i64 %tmp109 ; <float*> [#uses=1]
-  %scevgep125 = getelementptr float* %O, i64 %tmp109 ; <float*> [#uses=1]
+  %scevgep110 = getelementptr float, float* %I, i64 %tmp109 ; <float*> [#uses=1]
+  %scevgep125 = getelementptr float, float* %O, i64 %tmp109 ; <float*> [#uses=1]
   br label %bb7
 
 bb7:                                              ; preds = %bb6.bb7_crit_edge, %bb6.preheader
@@ -166,9 +166,9 @@ bb8:                                              ; preds = %bb4
 
 bb.nph:                                           ; preds = %bb8
   %I_addr.0.sum = add i64 %14, -1                 ; <i64> [#uses=1]
-  %49 = getelementptr inbounds float* %I, i64 %I_addr.0.sum ; <float*> [#uses=1]
+  %49 = getelementptr inbounds float, float* %I, i64 %I_addr.0.sum ; <float*> [#uses=1]
   %50 = bitcast float* %49 to <4 x float>*        ; <<4 x float>*> [#uses=1]
-  %51 = load <4 x float>* %50, align 16           ; <<4 x float>> [#uses=1]
+  %51 = load <4 x float>, <4 x float>* %50, align 16           ; <<4 x float>> [#uses=1]
   %tmp54 = add i64 %14, 16                        ; <i64> [#uses=1]
   %tmp56 = add i64 %14, 3                         ; <i64> [#uses=1]
   %tmp60 = add i64 %14, 7                         ; <i64> [#uses=1]
@@ -191,35 +191,35 @@ bb9:                                              ; preds = %bb.nph, %bb9
   %tmp51 = shl i64 %indvar, 4                     ; <i64> [#uses=9]
   %tmp55 = add i64 %tmp54, %tmp51                 ; <i64> [#uses=2]
   %tmp57 = add i64 %tmp56, %tmp51                 ; <i64> [#uses=1]
-  %scevgep58 = getelementptr float* %I, i64 %tmp57 ; <float*> [#uses=1]
+  %scevgep58 = getelementptr float, float* %I, i64 %tmp57 ; <float*> [#uses=1]
   %scevgep5859 = bitcast float* %scevgep58 to <4 x float>* ; <<4 x float>*> [#uses=1]
   %tmp61 = add i64 %tmp60, %tmp51                 ; <i64> [#uses=1]
-  %scevgep62 = getelementptr float* %I, i64 %tmp61 ; <float*> [#uses=1]
+  %scevgep62 = getelementptr float, float* %I, i64 %tmp61 ; <float*> [#uses=1]
   %scevgep6263 = bitcast float* %scevgep62 to <4 x float>* ; <<4 x float>*> [#uses=1]
   %tmp65 = add i64 %tmp64, %tmp51                 ; <i64> [#uses=1]
-  %scevgep66 = getelementptr float* %I, i64 %tmp65 ; <float*> [#uses=1]
+  %scevgep66 = getelementptr float, float* %I, i64 %tmp65 ; <float*> [#uses=1]
   %scevgep6667 = bitcast float* %scevgep66 to <4 x float>* ; <<4 x float>*> [#uses=1]
   %tmp69 = add i64 %tmp68, %tmp51                 ; <i64> [#uses=1]
-  %scevgep70 = getelementptr float* %I, i64 %tmp69 ; <float*> [#uses=1]
+  %scevgep70 = getelementptr float, float* %I, i64 %tmp69 ; <float*> [#uses=1]
   %scevgep7071 = bitcast float* %scevgep70 to <4 x float>* ; <<4 x float>*> [#uses=1]
   %tmp72 = add i64 %14, %tmp51                    ; <i64> [#uses=1]
-  %scevgep73 = getelementptr float* %O, i64 %tmp72 ; <float*> [#uses=1]
+  %scevgep73 = getelementptr float, float* %O, i64 %tmp72 ; <float*> [#uses=1]
   %scevgep7374 = bitcast float* %scevgep73 to <4 x float>* ; <<4 x float>*> [#uses=1]
   %tmp77 = add i64 %tmp76, %tmp51                 ; <i64> [#uses=1]
-  %scevgep78 = getelementptr float* %O, i64 %tmp77 ; <float*> [#uses=1]
+  %scevgep78 = getelementptr float, float* %O, i64 %tmp77 ; <float*> [#uses=1]
   %scevgep7879 = bitcast float* %scevgep78 to <4 x float>* ; <<4 x float>*> [#uses=1]
   %tmp81 = add i64 %tmp80, %tmp51                 ; <i64> [#uses=1]
-  %scevgep82 = getelementptr float* %O, i64 %tmp81 ; <float*> [#uses=1]
+  %scevgep82 = getelementptr float, float* %O, i64 %tmp81 ; <float*> [#uses=1]
   %scevgep8283 = bitcast float* %scevgep82 to <4 x float>* ; <<4 x float>*> [#uses=1]
   %tmp85 = add i64 %tmp84, %tmp51                 ; <i64> [#uses=1]
-  %scevgep86 = getelementptr float* %O, i64 %tmp85 ; <float*> [#uses=1]
+  %scevgep86 = getelementptr float, float* %O, i64 %tmp85 ; <float*> [#uses=1]
   %scevgep8687 = bitcast float* %scevgep86 to <4 x float>* ; <<4 x float>*> [#uses=1]
   %tmp88 = mul i64 %indvar, -16                   ; <i64> [#uses=1]
   %tmp92 = add i64 %tmp91, %tmp88                 ; <i64> [#uses=2]
-  %52 = load <4 x float>* %scevgep5859, align 16  ; <<4 x float>> [#uses=2]
-  %53 = load <4 x float>* %scevgep6263, align 16  ; <<4 x float>> [#uses=2]
-  %54 = load <4 x float>* %scevgep6667, align 16  ; <<4 x float>> [#uses=2]
-  %55 = load <4 x float>* %scevgep7071, align 16  ; <<4 x float>> [#uses=2]
+  %52 = load <4 x float>, <4 x float>* %scevgep5859, align 16  ; <<4 x float>> [#uses=2]
+  %53 = load <4 x float>, <4 x float>* %scevgep6263, align 16  ; <<4 x float>> [#uses=2]
+  %54 = load <4 x float>, <4 x float>* %scevgep6667, align 16  ; <<4 x float>> [#uses=2]
+  %55 = load <4 x float>, <4 x float>* %scevgep7071, align 16  ; <<4 x float>> [#uses=2]
   %56 = shufflevector <4 x float> %vI0.019, <4 x float> %52, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
   %57 = shufflevector <4 x float> %56, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1]
   %58 = shufflevector <4 x float> %52, <4 x float> %53, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
@@ -245,8 +245,8 @@ bb9:                                              ; preds = %bb.nph, %bb9
   br i1 %72, label %bb9, label %bb10.bb11.loopexit_crit_edge
 
 bb10.bb11.loopexit_crit_edge:                     ; preds = %bb9
-  %scevgep = getelementptr float* %I, i64 %tmp55  ; <float*> [#uses=1]
-  %scevgep75 = getelementptr float* %O, i64 %tmp55 ; <float*> [#uses=1]
+  %scevgep = getelementptr float, float* %I, i64 %tmp55  ; <float*> [#uses=1]
+  %scevgep75 = getelementptr float, float* %O, i64 %tmp55 ; <float*> [#uses=1]
   br label %bb11
 
 bb11:                                             ; preds = %bb8, %bb10.bb11.loopexit_crit_edge, %bb7
@@ -261,9 +261,9 @@ bb11:                                             ; preds = %bb8, %bb10.bb11.loo
 bb12:                                             ; preds = %bb11, %bb12
   %indvar94 = phi i64 [ %indvar.next95, %bb12 ], [ 0, %bb11 ] ; <i64> [#uses=3]
   %x.130 = phi float [ %77, %bb12 ], [ %73, %bb11 ] ; <float> [#uses=2]
-  %I_addr.433 = getelementptr float* %I_addr.2, i64 %indvar94 ; <float*> [#uses=1]
-  %O_addr.432 = getelementptr float* %O_addr.2, i64 %indvar94 ; <float*> [#uses=1]
-  %75 = load float* %I_addr.433, align 4          ; <float> [#uses=1]
+  %I_addr.433 = getelementptr float, float* %I_addr.2, i64 %indvar94 ; <float*> [#uses=1]
+  %O_addr.432 = getelementptr float, float* %O_addr.2, i64 %indvar94 ; <float*> [#uses=1]
+  %75 = load float, float* %I_addr.433, align 4          ; <float> [#uses=1]
   %76 = fmul float %75, %x.130                    ; <float> [#uses=1]
   store float %76, float* %O_addr.432, align 4
   %77 = fadd float %x.130, %0                     ; <float> [#uses=2]
@@ -293,7 +293,7 @@ outer:                                     ; preds = %bb1, %entry
 
 inner:                                       ; preds = %bb0, %if.end275
   %i8 = phi i32 [ %a, %outer ], [ %indvar.next159, %bb0 ] ; <i32> [#uses=2]
-  %t338 = load i32* undef                     ; <i32> [#uses=1]
+  %t338 = load i32, i32* undef                     ; <i32> [#uses=1]
   %t191 = mul i32 %i8, %t338        ; <i32> [#uses=1]
   %t179 = add i32 %i6, %t191        ; <i32> [#uses=1]
   br label %bb0
diff --git a/test/CodeGen/X86/mulx32.ll b/test/CodeGen/X86/mulx32.ll
index b75ac009e76d..42ef2eb6f647 100644
--- a/test/CodeGen/X86/mulx32.ll
+++ b/test/CodeGen/X86/mulx32.ll
@@ -11,7 +11,7 @@ define i64 @f1(i32 %a, i32 %b) {
 }
 
 define i64 @f2(i32 %a, i32* %p) {
-  %b = load i32* %p
+  %b = load i32, i32* %p
   %x = zext i32 %a to i64
   %y = zext i32 %b to i64
   %r = mul i64 %x, %y
diff --git a/test/CodeGen/X86/mulx64.ll b/test/CodeGen/X86/mulx64.ll
index d5730282a137..808c02290b7c 100644
--- a/test/CodeGen/X86/mulx64.ll
+++ b/test/CodeGen/X86/mulx64.ll
@@ -11,7 +11,7 @@ define i128 @f1(i64 %a, i64 %b) {
 }
 
 define i128 @f2(i64 %a, i64* %p) {
-  %b = load i64* %p
+  %b = load i64, i64* %p
   %x = zext i64 %a to i128
   %y = zext i64 %b to i128
   %r = mul i128 %x, %y
diff --git a/test/CodeGen/X86/musttail-fastcall.ll b/test/CodeGen/X86/musttail-fastcall.ll
index c7e5ffcfa877..a95e0ff12c34 100644
--- a/test/CodeGen/X86/musttail-fastcall.ll
+++ b/test/CodeGen/X86/musttail-fastcall.ll
@@ -9,13 +9,13 @@
 declare void @puts(i8*)
 
 define i32 @call_fast_thunk() {
-  %r = call x86_fastcallcc i32 (...)* @fast_thunk(i32 inreg 1, i32 inreg 2, i32 3)
+  %r = call x86_fastcallcc i32 (...) @fast_thunk(i32 inreg 1, i32 inreg 2, i32 3)
   ret i32 %r
 }
 
 define x86_fastcallcc i32 @fast_thunk(...) {
-  call void @puts(i8* getelementptr ([4 x i8]* @asdf, i32 0, i32 0))
-  %r = musttail call x86_fastcallcc i32 (...)* bitcast (i32 (i32, i32, i32)* @fast_target to i32 (...)*) (...)
+  call void @puts(i8* getelementptr ([4 x i8], [4 x i8]* @asdf, i32 0, i32 0))
+  %r = musttail call x86_fastcallcc i32 (...) bitcast (i32 (i32, i32, i32)* @fast_target to i32 (...)*) (...)
   ret i32 %r
 }
 
@@ -38,13 +38,13 @@ define x86_fastcallcc i32 @fast_target(i32 inreg %a, i32 inreg %b, i32 %c) {
 ; Repeat the test for vectorcall, which has XMM registers.
 
 define i32 @call_vector_thunk() {
-  %r = call x86_vectorcallcc i32 (...)* @vector_thunk(i32 inreg 1, i32 inreg 2, i32 3)
+  %r = call x86_vectorcallcc i32 (...) @vector_thunk(i32 inreg 1, i32 inreg 2, i32 3)
   ret i32 %r
 }
 
 define x86_vectorcallcc i32 @vector_thunk(...) {
-  call void @puts(i8* getelementptr ([4 x i8]* @asdf, i32 0, i32 0))
-  %r = musttail call x86_vectorcallcc i32 (...)* bitcast (i32 (i32, i32, i32)* @vector_target to i32 (...)*) (...)
+  call void @puts(i8* getelementptr ([4 x i8], [4 x i8]* @asdf, i32 0, i32 0))
+  %r = musttail call x86_vectorcallcc i32 (...) bitcast (i32 (i32, i32, i32)* @vector_target to i32 (...)*) (...)
   ret i32 %r
 }
 
diff --git a/test/CodeGen/X86/musttail-indirect.ll b/test/CodeGen/X86/musttail-indirect.ll
index 9d21b5ea5d52..7bb71c3fb038 100644
--- a/test/CodeGen/X86/musttail-indirect.ll
+++ b/test/CodeGen/X86/musttail-indirect.ll
@@ -31,8 +31,8 @@
 define x86_thiscallcc i32 @f_thunk(%struct.B* %this, i32) {
 entry:
   %1 = bitcast %struct.B* %this to i32 (%struct.B*, i32)***
-  %vtable = load i32 (%struct.B*, i32)*** %1
-  %2 = load i32 (%struct.B*, i32)** %vtable
+  %vtable = load i32 (%struct.B*, i32)**, i32 (%struct.B*, i32)*** %1
+  %2 = load i32 (%struct.B*, i32)*, i32 (%struct.B*, i32)** %vtable
   %3 = musttail call x86_thiscallcc i32 %2(%struct.B* %this, i32 %0)
   ret i32 %3
 }
@@ -45,9 +45,9 @@ entry:
 define x86_thiscallcc i32 @g_thunk(%struct.B* %this, <{ %struct.A, i32, %struct.A }>* inalloca) {
 entry:
   %1 = bitcast %struct.B* %this to i32 (%struct.B*, <{ %struct.A, i32, %struct.A }>*)***
-  %vtable = load i32 (%struct.B*, <{ %struct.A, i32, %struct.A }>*)*** %1
-  %vfn = getelementptr inbounds i32 (%struct.B*, <{ %struct.A, i32, %struct.A }>*)** %vtable, i32 1
-  %2 = load i32 (%struct.B*, <{ %struct.A, i32, %struct.A }>*)** %vfn
+  %vtable = load i32 (%struct.B*, <{ %struct.A, i32, %struct.A }>*)**, i32 (%struct.B*, <{ %struct.A, i32, %struct.A }>*)*** %1
+  %vfn = getelementptr inbounds i32 (%struct.B*, <{ %struct.A, i32, %struct.A }>*)*, i32 (%struct.B*, <{ %struct.A, i32, %struct.A }>*)** %vtable, i32 1
+  %2 = load i32 (%struct.B*, <{ %struct.A, i32, %struct.A }>*)*, i32 (%struct.B*, <{ %struct.A, i32, %struct.A }>*)** %vfn
   %3 = musttail call x86_thiscallcc i32 %2(%struct.B* %this, <{ %struct.A, i32, %struct.A }>* inalloca %0)
   ret i32 %3
 }
@@ -59,9 +59,9 @@ entry:
 define x86_thiscallcc void @h_thunk(%struct.B* %this, <{ %struct.A, i32, %struct.A }>* inalloca) {
 entry:
   %1 = bitcast %struct.B* %this to void (%struct.B*, <{ %struct.A, i32, %struct.A }>*)***
-  %vtable = load void (%struct.B*, <{ %struct.A, i32, %struct.A }>*)*** %1
-  %vfn = getelementptr inbounds void (%struct.B*, <{ %struct.A, i32, %struct.A }>*)** %vtable, i32 2
-  %2 = load void (%struct.B*, <{ %struct.A, i32, %struct.A }>*)** %vfn
+  %vtable = load void (%struct.B*, <{ %struct.A, i32, %struct.A }>*)**, void (%struct.B*, <{ %struct.A, i32, %struct.A }>*)*** %1
+  %vfn = getelementptr inbounds void (%struct.B*, <{ %struct.A, i32, %struct.A }>*)*, void (%struct.B*, <{ %struct.A, i32, %struct.A }>*)** %vtable, i32 2
+  %2 = load void (%struct.B*, <{ %struct.A, i32, %struct.A }>*)*, void (%struct.B*, <{ %struct.A, i32, %struct.A }>*)** %vfn
   musttail call x86_thiscallcc void %2(%struct.B* %this, <{ %struct.A, i32, %struct.A }>* inalloca %0)
   ret void
 }
@@ -73,9 +73,9 @@ entry:
 define x86_thiscallcc %struct.A* @i_thunk(%struct.B* %this, <{ %struct.A*, %struct.A, i32, %struct.A }>* inalloca) {
 entry:
   %1 = bitcast %struct.B* %this to %struct.A* (%struct.B*, <{ %struct.A*, %struct.A, i32, %struct.A }>*)***
-  %vtable = load %struct.A* (%struct.B*, <{ %struct.A*, %struct.A, i32, %struct.A }>*)*** %1
-  %vfn = getelementptr inbounds %struct.A* (%struct.B*, <{ %struct.A*, %struct.A, i32, %struct.A }>*)** %vtable, i32 3
-  %2 = load %struct.A* (%struct.B*, <{ %struct.A*, %struct.A, i32, %struct.A }>*)** %vfn
+  %vtable = load %struct.A* (%struct.B*, <{ %struct.A*, %struct.A, i32, %struct.A }>*)**, %struct.A* (%struct.B*, <{ %struct.A*, %struct.A, i32, %struct.A }>*)*** %1
+  %vfn = getelementptr inbounds %struct.A* (%struct.B*, <{ %struct.A*, %struct.A, i32, %struct.A }>*)*, %struct.A* (%struct.B*, <{ %struct.A*, %struct.A, i32, %struct.A }>*)** %vtable, i32 3
+  %2 = load %struct.A* (%struct.B*, <{ %struct.A*, %struct.A, i32, %struct.A }>*)*, %struct.A* (%struct.B*, <{ %struct.A*, %struct.A, i32, %struct.A }>*)** %vfn
   %3 = musttail call x86_thiscallcc %struct.A* %2(%struct.B* %this, <{ %struct.A*, %struct.A, i32, %struct.A }>* inalloca %0)
   ret %struct.A* %3
 }
@@ -86,9 +86,9 @@ entry:
 define x86_thiscallcc void @j_thunk(%struct.A* noalias sret %agg.result, %struct.B* %this, i32) {
 entry:
   %1 = bitcast %struct.B* %this to void (%struct.A*, %struct.B*, i32)***
-  %vtable = load void (%struct.A*, %struct.B*, i32)*** %1
-  %vfn = getelementptr inbounds void (%struct.A*, %struct.B*, i32)** %vtable, i32 4
-  %2 = load void (%struct.A*, %struct.B*, i32)** %vfn
+  %vtable = load void (%struct.A*, %struct.B*, i32)**, void (%struct.A*, %struct.B*, i32)*** %1
+  %vfn = getelementptr inbounds void (%struct.A*, %struct.B*, i32)*, void (%struct.A*, %struct.B*, i32)** %vtable, i32 4
+  %2 = load void (%struct.A*, %struct.B*, i32)*, void (%struct.A*, %struct.B*, i32)** %vfn
   musttail call x86_thiscallcc void %2(%struct.A* sret %agg.result, %struct.B* %this, i32 %0)
   ret void
 }
@@ -99,12 +99,12 @@ entry:
 ; CHECK-NOT: ret
 define x86_stdcallcc i32 @stdcall_thunk(<{ %struct.B*, %struct.A }>* inalloca) {
 entry:
-  %this_ptr = getelementptr inbounds <{ %struct.B*, %struct.A }>* %0, i32 0, i32 0
-  %this = load %struct.B** %this_ptr
+  %this_ptr = getelementptr inbounds <{ %struct.B*, %struct.A }>, <{ %struct.B*, %struct.A }>* %0, i32 0, i32 0
+  %this = load %struct.B*, %struct.B** %this_ptr
   %1 = bitcast %struct.B* %this to i32 (<{ %struct.B*, %struct.A }>*)***
-  %vtable = load i32 (<{ %struct.B*, %struct.A }>*)*** %1
-  %vfn = getelementptr inbounds i32 (<{ %struct.B*, %struct.A }>*)** %vtable, i32 1
-  %2 = load i32 (<{ %struct.B*, %struct.A }>*)** %vfn
+  %vtable = load i32 (<{ %struct.B*, %struct.A }>*)**, i32 (<{ %struct.B*, %struct.A }>*)*** %1
+  %vfn = getelementptr inbounds i32 (<{ %struct.B*, %struct.A }>*)*, i32 (<{ %struct.B*, %struct.A }>*)** %vtable, i32 1
+  %2 = load i32 (<{ %struct.B*, %struct.A }>*)*, i32 (<{ %struct.B*, %struct.A }>*)** %vfn
   %3 = musttail call x86_stdcallcc i32 %2(<{ %struct.B*, %struct.A }>* inalloca %0)
   ret i32 %3
 }
@@ -116,9 +116,9 @@ entry:
 define x86_fastcallcc i32 @fastcall_thunk(%struct.B* inreg %this, <{ %struct.A }>* inalloca) {
 entry:
   %1 = bitcast %struct.B* %this to i32 (%struct.B*, <{ %struct.A }>*)***
-  %vtable = load i32 (%struct.B*, <{ %struct.A }>*)*** %1
-  %vfn = getelementptr inbounds i32 (%struct.B*, <{ %struct.A }>*)** %vtable, i32 1
-  %2 = load i32 (%struct.B*, <{ %struct.A }>*)** %vfn
+  %vtable = load i32 (%struct.B*, <{ %struct.A }>*)**, i32 (%struct.B*, <{ %struct.A }>*)*** %1
+  %vfn = getelementptr inbounds i32 (%struct.B*, <{ %struct.A }>*)*, i32 (%struct.B*, <{ %struct.A }>*)** %vtable, i32 1
+  %2 = load i32 (%struct.B*, <{ %struct.A }>*)*, i32 (%struct.B*, <{ %struct.A }>*)** %vfn
   %3 = musttail call x86_fastcallcc i32 %2(%struct.B* inreg %this, <{ %struct.A }>* inalloca %0)
   ret i32 %3
 }
diff --git a/test/CodeGen/X86/musttail-thiscall.ll b/test/CodeGen/X86/musttail-thiscall.ll
index 8ea12482e504..1402f10b091a 100644
--- a/test/CodeGen/X86/musttail-thiscall.ll
+++ b/test/CodeGen/X86/musttail-thiscall.ll
@@ -4,7 +4,7 @@
 ; CHECK-LABEL: t1:
 ; CHECK: jmp {{_?}}t1_callee
 define x86_thiscallcc void @t1(i8* %this) {
-  %adj = getelementptr i8* %this, i32 4
+  %adj = getelementptr i8, i8* %this, i32 4
   musttail call x86_thiscallcc void @t1_callee(i8* %adj)
   ret void
 }
@@ -13,7 +13,7 @@ declare x86_thiscallcc void @t1_callee(i8* %this)
 ; CHECK-LABEL: t2:
 ; CHECK: jmp {{_?}}t2_callee
 define x86_thiscallcc i32 @t2(i8* %this, i32 %a) {
-  %adj = getelementptr i8* %this, i32 4
+  %adj = getelementptr i8, i8* %this, i32 4
   %rv = musttail call x86_thiscallcc i32 @t2_callee(i8* %adj, i32 %a)
   ret i32 %rv
 }
@@ -22,8 +22,8 @@ declare x86_thiscallcc i32 @t2_callee(i8* %this, i32 %a)
 ; CHECK-LABEL: t3:
 ; CHECK: jmp {{_?}}t3_callee
 define x86_thiscallcc i8* @t3(i8* %this, <{ i8*, i32 }>* inalloca %args) {
-  %adj = getelementptr i8* %this, i32 4
-  %a_ptr = getelementptr <{ i8*, i32 }>* %args, i32 0, i32 1
+  %adj = getelementptr i8, i8* %this, i32 4
+  %a_ptr = getelementptr <{ i8*, i32 }>, <{ i8*, i32 }>* %args, i32 0, i32 1
   store i32 0, i32* %a_ptr
   %rv = musttail call x86_thiscallcc i8* @t3_callee(i8* %adj, <{ i8*, i32 }>* inalloca %args)
   ret i8* %rv
diff --git a/test/CodeGen/X86/musttail-varargs.ll b/test/CodeGen/X86/musttail-varargs.ll
index 7f105a13a6a0..3613f4c08cce 100644
--- a/test/CodeGen/X86/musttail-varargs.ll
+++ b/test/CodeGen/X86/musttail-varargs.ll
@@ -16,8 +16,8 @@ define void @f_thunk(i8* %this, ...) {
   %ap_i8 = bitcast [4 x i8*]* %ap to i8*
   call void @llvm.va_start(i8* %ap_i8)
 
-  %fptr = call void(i8*, ...)*(i8*)* @get_f(i8* %this)
-  musttail call void (i8*, ...)* %fptr(i8* %this, ...)
+  %fptr = call void(i8*, ...)*(i8*) @get_f(i8* %this)
+  musttail call void (i8*, ...) %fptr(i8* %this, ...)
   ret void
 }
 
@@ -84,7 +84,7 @@ define void @f_thunk(i8* %this, ...) {
 
 define void @g_thunk(i8* %fptr_i8, ...) {
   %fptr = bitcast i8* %fptr_i8 to void (i8*, ...)*
-  musttail call void (i8*, ...)* %fptr(i8* %fptr_i8, ...)
+  musttail call void (i8*, ...) %fptr(i8* %fptr_i8, ...)
   ret void
 }
 
@@ -106,23 +106,23 @@ define void @g_thunk(i8* %fptr_i8, ...) {
 @g = external global i32
 
 define void @h_thunk(%struct.Foo* %this, ...) {
-  %cond_p = getelementptr %struct.Foo* %this, i32 0, i32 0
-  %cond = load i1* %cond_p
+  %cond_p = getelementptr %struct.Foo, %struct.Foo* %this, i32 0, i32 0
+  %cond = load i1, i1* %cond_p
   br i1 %cond, label %then, label %else
 
 then:
-  %a_p = getelementptr %struct.Foo* %this, i32 0, i32 1
-  %a_i8 = load i8** %a_p
+  %a_p = getelementptr %struct.Foo, %struct.Foo* %this, i32 0, i32 1
+  %a_i8 = load i8*, i8** %a_p
   %a = bitcast i8* %a_i8 to void (%struct.Foo*, ...)*
-  musttail call void (%struct.Foo*, ...)* %a(%struct.Foo* %this, ...)
+  musttail call void (%struct.Foo*, ...) %a(%struct.Foo* %this, ...)
   ret void
 
 else:
-  %b_p = getelementptr %struct.Foo* %this, i32 0, i32 2
-  %b_i8 = load i8** %b_p
+  %b_p = getelementptr %struct.Foo, %struct.Foo* %this, i32 0, i32 2
+  %b_i8 = load i8*, i8** %b_p
   %b = bitcast i8* %b_i8 to void (%struct.Foo*, ...)*
   store i32 42, i32* @g
-  musttail call void (%struct.Foo*, ...)* %b(%struct.Foo* %this, ...)
+  musttail call void (%struct.Foo*, ...) %b(%struct.Foo* %this, ...)
   ret void
 }
 
diff --git a/test/CodeGen/X86/nancvt.ll b/test/CodeGen/X86/nancvt.ll
index 8a665fa79cff..9222f6b76822 100644
--- a/test/CodeGen/X86/nancvt.ll
+++ b/test/CodeGen/X86/nancvt.ll
@@ -29,38 +29,38 @@ entry:
 	br label %bb23
 
 bb:		; preds = %bb23
-	%tmp = load i32* %i, align 4		; <i32> [#uses=1]
-	%tmp1 = getelementptr [3 x i32]* @fnan, i32 0, i32 %tmp		; <i32*> [#uses=1]
-	%tmp2 = load i32* %tmp1, align 4		; <i32> [#uses=1]
-	%tmp3 = getelementptr %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
+	%tmp = load i32, i32* %i, align 4		; <i32> [#uses=1]
+	%tmp1 = getelementptr [3 x i32], [3 x i32]* @fnan, i32 0, i32 %tmp		; <i32*> [#uses=1]
+	%tmp2 = load i32, i32* %tmp1, align 4		; <i32> [#uses=1]
+	%tmp3 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
 	%tmp34 = bitcast float* %tmp3 to i32*		; <i32*> [#uses=1]
 	store i32 %tmp2, i32* %tmp34, align 4
-	%tmp5 = getelementptr %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
-	%tmp6 = load float* %tmp5, align 4		; <float> [#uses=1]
+	%tmp5 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
+	%tmp6 = load float, float* %tmp5, align 4		; <float> [#uses=1]
 	%tmp67 = fpext float %tmp6 to double		; <double> [#uses=1]
-	%tmp8 = getelementptr %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp8 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
 	store double %tmp67, double* %tmp8, align 8
-	%tmp9 = getelementptr %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp9 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
 	%tmp910 = bitcast double* %tmp9 to i64*		; <i64*> [#uses=1]
-	%tmp11 = load i64* %tmp910, align 8		; <i64> [#uses=1]
+	%tmp11 = load i64, i64* %tmp910, align 8		; <i64> [#uses=1]
 	%tmp1112 = trunc i64 %tmp11 to i32		; <i32> [#uses=1]
 	%tmp13 = and i32 %tmp1112, -1		; <i32> [#uses=1]
-	%tmp14 = getelementptr %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp14 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
 	%tmp1415 = bitcast double* %tmp14 to i64*		; <i64*> [#uses=1]
-	%tmp16 = load i64* %tmp1415, align 8		; <i64> [#uses=1]
+	%tmp16 = load i64, i64* %tmp1415, align 8		; <i64> [#uses=1]
 	%.cast = zext i32 32 to i64		; <i64> [#uses=1]
 	%tmp17 = ashr i64 %tmp16, %.cast		; <i64> [#uses=1]
 	%tmp1718 = trunc i64 %tmp17 to i32		; <i32> [#uses=1]
-	%tmp19 = getelementptr [10 x i8]* @.str, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp19 = getelementptr [10 x i8], [10 x i8]* @.str, i32 0, i32 0		; <i8*> [#uses=1]
 	store volatile i32 %tmp1718, i32* @var
 	store volatile i32 %tmp13, i32* @var
-	%tmp21 = load i32* %i, align 4		; <i32> [#uses=1]
+	%tmp21 = load i32, i32* %i, align 4		; <i32> [#uses=1]
 	%tmp22 = add i32 %tmp21, 1		; <i32> [#uses=1]
 	store i32 %tmp22, i32* %i, align 4
 	br label %bb23
 
 bb23:		; preds = %bb, %entry
-	%tmp24 = load i32* %i, align 4		; <i32> [#uses=1]
+	%tmp24 = load i32, i32* %i, align 4		; <i32> [#uses=1]
 	%tmp25 = icmp sle i32 %tmp24, 2		; <i1> [#uses=1]
 	%tmp2526 = zext i1 %tmp25 to i8		; <i8> [#uses=1]
 	%toBool = icmp ne i8 %tmp2526, 0		; <i1> [#uses=1]
@@ -71,29 +71,29 @@ bb27:		; preds = %bb23
 	br label %bb46
 
 bb28:		; preds = %bb46
-	%tmp29 = load i32* %i, align 4		; <i32> [#uses=1]
-	%tmp30 = getelementptr [3 x i64]* @dnan, i32 0, i32 %tmp29		; <i64*> [#uses=1]
-	%tmp31 = load i64* %tmp30, align 8		; <i64> [#uses=1]
-	%tmp32 = getelementptr %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp29 = load i32, i32* %i, align 4		; <i32> [#uses=1]
+	%tmp30 = getelementptr [3 x i64], [3 x i64]* @dnan, i32 0, i32 %tmp29		; <i64*> [#uses=1]
+	%tmp31 = load i64, i64* %tmp30, align 8		; <i64> [#uses=1]
+	%tmp32 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
 	%tmp3233 = bitcast double* %tmp32 to i64*		; <i64*> [#uses=1]
 	store i64 %tmp31, i64* %tmp3233, align 8
-	%tmp35 = getelementptr %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
-	%tmp36 = load double* %tmp35, align 8		; <double> [#uses=1]
+	%tmp35 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp36 = load double, double* %tmp35, align 8		; <double> [#uses=1]
 	%tmp3637 = fptrunc double %tmp36 to float		; <float> [#uses=1]
-	%tmp38 = getelementptr %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
+	%tmp38 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
 	store float %tmp3637, float* %tmp38, align 4
-	%tmp39 = getelementptr %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
+	%tmp39 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
 	%tmp3940 = bitcast float* %tmp39 to i32*		; <i32*> [#uses=1]
-	%tmp41 = load i32* %tmp3940, align 4		; <i32> [#uses=1]
-	%tmp42 = getelementptr [6 x i8]* @.str1, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp41 = load i32, i32* %tmp3940, align 4		; <i32> [#uses=1]
+	%tmp42 = getelementptr [6 x i8], [6 x i8]* @.str1, i32 0, i32 0		; <i8*> [#uses=1]
 	store volatile i32 %tmp41, i32* @var
-	%tmp44 = load i32* %i, align 4		; <i32> [#uses=1]
+	%tmp44 = load i32, i32* %i, align 4		; <i32> [#uses=1]
 	%tmp45 = add i32 %tmp44, 1		; <i32> [#uses=1]
 	store i32 %tmp45, i32* %i, align 4
 	br label %bb46
 
 bb46:		; preds = %bb28, %bb27
-	%tmp47 = load i32* %i, align 4		; <i32> [#uses=1]
+	%tmp47 = load i32, i32* %i, align 4		; <i32> [#uses=1]
 	%tmp48 = icmp sle i32 %tmp47, 2		; <i1> [#uses=1]
 	%tmp4849 = zext i1 %tmp48 to i8		; <i8> [#uses=1]
 	%toBool50 = icmp ne i8 %tmp4849, 0		; <i1> [#uses=1]
@@ -104,38 +104,38 @@ bb51:		; preds = %bb46
 	br label %bb78
 
 bb52:		; preds = %bb78
-	%tmp53 = load i32* %i, align 4		; <i32> [#uses=1]
-	%tmp54 = getelementptr [3 x i32]* @fsnan, i32 0, i32 %tmp53		; <i32*> [#uses=1]
-	%tmp55 = load i32* %tmp54, align 4		; <i32> [#uses=1]
-	%tmp56 = getelementptr %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
+	%tmp53 = load i32, i32* %i, align 4		; <i32> [#uses=1]
+	%tmp54 = getelementptr [3 x i32], [3 x i32]* @fsnan, i32 0, i32 %tmp53		; <i32*> [#uses=1]
+	%tmp55 = load i32, i32* %tmp54, align 4		; <i32> [#uses=1]
+	%tmp56 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
 	%tmp5657 = bitcast float* %tmp56 to i32*		; <i32*> [#uses=1]
 	store i32 %tmp55, i32* %tmp5657, align 4
-	%tmp58 = getelementptr %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
-	%tmp59 = load float* %tmp58, align 4		; <float> [#uses=1]
+	%tmp58 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
+	%tmp59 = load float, float* %tmp58, align 4		; <float> [#uses=1]
 	%tmp5960 = fpext float %tmp59 to double		; <double> [#uses=1]
-	%tmp61 = getelementptr %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp61 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
 	store double %tmp5960, double* %tmp61, align 8
-	%tmp62 = getelementptr %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp62 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
 	%tmp6263 = bitcast double* %tmp62 to i64*		; <i64*> [#uses=1]
-	%tmp64 = load i64* %tmp6263, align 8		; <i64> [#uses=1]
+	%tmp64 = load i64, i64* %tmp6263, align 8		; <i64> [#uses=1]
 	%tmp6465 = trunc i64 %tmp64 to i32		; <i32> [#uses=1]
 	%tmp66 = and i32 %tmp6465, -1		; <i32> [#uses=1]
-	%tmp68 = getelementptr %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp68 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
 	%tmp6869 = bitcast double* %tmp68 to i64*		; <i64*> [#uses=1]
-	%tmp70 = load i64* %tmp6869, align 8		; <i64> [#uses=1]
+	%tmp70 = load i64, i64* %tmp6869, align 8		; <i64> [#uses=1]
 	%.cast71 = zext i32 32 to i64		; <i64> [#uses=1]
 	%tmp72 = ashr i64 %tmp70, %.cast71		; <i64> [#uses=1]
 	%tmp7273 = trunc i64 %tmp72 to i32		; <i32> [#uses=1]
-	%tmp74 = getelementptr [10 x i8]* @.str, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp74 = getelementptr [10 x i8], [10 x i8]* @.str, i32 0, i32 0		; <i8*> [#uses=1]
 	store volatile i32 %tmp7273, i32* @var
 	store volatile i32 %tmp66, i32* @var
-	%tmp76 = load i32* %i, align 4		; <i32> [#uses=1]
+	%tmp76 = load i32, i32* %i, align 4		; <i32> [#uses=1]
 	%tmp77 = add i32 %tmp76, 1		; <i32> [#uses=1]
 	store i32 %tmp77, i32* %i, align 4
 	br label %bb78
 
 bb78:		; preds = %bb52, %bb51
-	%tmp79 = load i32* %i, align 4		; <i32> [#uses=1]
+	%tmp79 = load i32, i32* %i, align 4		; <i32> [#uses=1]
 	%tmp80 = icmp sle i32 %tmp79, 2		; <i1> [#uses=1]
 	%tmp8081 = zext i1 %tmp80 to i8		; <i8> [#uses=1]
 	%toBool82 = icmp ne i8 %tmp8081, 0		; <i1> [#uses=1]
@@ -146,29 +146,29 @@ bb83:		; preds = %bb78
 	br label %bb101
 
 bb84:		; preds = %bb101
-	%tmp85 = load i32* %i, align 4		; <i32> [#uses=1]
-	%tmp86 = getelementptr [3 x i64]* @dsnan, i32 0, i32 %tmp85		; <i64*> [#uses=1]
-	%tmp87 = load i64* %tmp86, align 8		; <i64> [#uses=1]
-	%tmp88 = getelementptr %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp85 = load i32, i32* %i, align 4		; <i32> [#uses=1]
+	%tmp86 = getelementptr [3 x i64], [3 x i64]* @dsnan, i32 0, i32 %tmp85		; <i64*> [#uses=1]
+	%tmp87 = load i64, i64* %tmp86, align 8		; <i64> [#uses=1]
+	%tmp88 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
 	%tmp8889 = bitcast double* %tmp88 to i64*		; <i64*> [#uses=1]
 	store i64 %tmp87, i64* %tmp8889, align 8
-	%tmp90 = getelementptr %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
-	%tmp91 = load double* %tmp90, align 8		; <double> [#uses=1]
+	%tmp90 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp91 = load double, double* %tmp90, align 8		; <double> [#uses=1]
 	%tmp9192 = fptrunc double %tmp91 to float		; <float> [#uses=1]
-	%tmp93 = getelementptr %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
+	%tmp93 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
 	store float %tmp9192, float* %tmp93, align 4
-	%tmp94 = getelementptr %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
+	%tmp94 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0		; <float*> [#uses=1]
 	%tmp9495 = bitcast float* %tmp94 to i32*		; <i32*> [#uses=1]
-	%tmp96 = load i32* %tmp9495, align 4		; <i32> [#uses=1]
-	%tmp97 = getelementptr [6 x i8]* @.str1, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp96 = load i32, i32* %tmp9495, align 4		; <i32> [#uses=1]
+	%tmp97 = getelementptr [6 x i8], [6 x i8]* @.str1, i32 0, i32 0		; <i8*> [#uses=1]
 	store volatile i32 %tmp96, i32* @var
-	%tmp99 = load i32* %i, align 4		; <i32> [#uses=1]
+	%tmp99 = load i32, i32* %i, align 4		; <i32> [#uses=1]
 	%tmp100 = add i32 %tmp99, 1		; <i32> [#uses=1]
 	store i32 %tmp100, i32* %i, align 4
 	br label %bb101
 
 bb101:		; preds = %bb84, %bb83
-	%tmp102 = load i32* %i, align 4		; <i32> [#uses=1]
+	%tmp102 = load i32, i32* %i, align 4		; <i32> [#uses=1]
 	%tmp103 = icmp sle i32 %tmp102, 2		; <i1> [#uses=1]
 	%tmp103104 = zext i1 %tmp103 to i8		; <i8> [#uses=1]
 	%toBool105 = icmp ne i8 %tmp103104, 0		; <i1> [#uses=1]
@@ -178,6 +178,6 @@ bb106:		; preds = %bb101
 	br label %return
 
 return:		; preds = %bb106
-	%retval107 = load i32* %retval		; <i32> [#uses=1]
+	%retval107 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval107
 }
diff --git a/test/CodeGen/X86/narrow-shl-cst.ll b/test/CodeGen/X86/narrow-shl-cst.ll
index 40b976014a77..c9e9a3d2a976 100644
--- a/test/CodeGen/X86/narrow-shl-cst.ll
+++ b/test/CodeGen/X86/narrow-shl-cst.ll
@@ -99,3 +99,26 @@ define i64 @test11(i64 %x) nounwind {
 ; CHECK: xorq $-65536
 ; CHECK: shlq $33
 }
+
+; PR23098
+define i32 @test12(i32 %x, i32* %y) nounwind {
+  %and = shl i32 %x, 1
+  %shl = and i32 %and, 255
+  store i32 %shl, i32* %y
+  ret i32 %shl
+; CHECK-LABEL: test12:
+; CHECK: andl $127
+; CHECK-NEXT: addl
+; CHECK-NOT: shl
+}
+
+define i64 @test13(i64 %x, i64* %y) nounwind {
+  %and = shl i64 %x, 1
+  %shl = and i64 %and, 255
+  store i64 %shl, i64* %y
+  ret i64 %shl
+; CHECK-LABEL: test13:
+; CHECK: andq $127
+; CHECK-NEXT: addq
+; CHECK-NOT: shl
+}
diff --git a/test/CodeGen/X86/narrow-shl-load.ll b/test/CodeGen/X86/narrow-shl-load.ll
index 5175bfc2bcb1..9dc0d749cb23 100644
--- a/test/CodeGen/X86/narrow-shl-load.ll
+++ b/test/CodeGen/X86/narrow-shl-load.ll
@@ -11,7 +11,7 @@ bb.nph:
   br label %while.cond
 
 while.cond:                                       ; preds = %while.cond, %bb.nph
-  %tmp6 = load i32* undef, align 4
+  %tmp6 = load i32, i32* undef, align 4
   %and = or i64 undef, undef
   %conv11 = zext i32 undef to i64
   %conv14 = zext i32 %tmp6 to i64
@@ -20,7 +20,7 @@ while.cond:                                       ; preds = %while.cond, %bb.nph
   %and17 = or i64 %shl15.masked, %conv11
   %add = add i64 %and17, 1
   %xor = xor i64 %add, %and
-  %tmp20 = load i64* undef, align 8
+  %tmp20 = load i64, i64* undef, align 8
   %add21 = add i64 %xor, %tmp20
   %conv22 = trunc i64 %add21 to i32
   store i32 %conv22, i32* undef, align 4
@@ -34,7 +34,7 @@ while.end:                                        ; preds = %while.cond
 ; PR8757
 define i32 @test3(i32 *%P) nounwind ssp {
   store volatile i32 128, i32* %P
-  %tmp4.pre = load i32* %P
+  %tmp4.pre = load i32, i32* %P
   %phitmp = trunc i32 %tmp4.pre to i16
   %phitmp13 = shl i16 %phitmp, 8
   %phitmp14 = ashr i16 %phitmp13, 8
diff --git a/test/CodeGen/X86/narrow_op-1.ll b/test/CodeGen/X86/narrow_op-1.ll
index 89ae3f1a3353..592ff94c57ba 100644
--- a/test/CodeGen/X86/narrow_op-1.ll
+++ b/test/CodeGen/X86/narrow_op-1.ll
@@ -5,9 +5,9 @@
 
 define void @t1() nounwind optsize ssp {
 entry:
-	%0 = load i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
+	%0 = load i32, i32* bitcast (i16* getelementptr (%struct.bf, %struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
 	%1 = or i32 %0, 65536
-	store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
+	store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf, %struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
 	ret void
 
 ; CHECK-LABEL: t1:
@@ -17,9 +17,9 @@ entry:
 
 define void @t2() nounwind optsize ssp {
 entry:
-	%0 = load i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
+	%0 = load i32, i32* bitcast (i16* getelementptr (%struct.bf, %struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
 	%1 = or i32 %0, 16842752
-	store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
+	store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf, %struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
 	ret void
 
 ; CHECK-LABEL: t2:
diff --git a/test/CodeGen/X86/negate-add-zero.ll b/test/CodeGen/X86/negate-add-zero.ll
index c961bd091b95..06341dc7ba53 100644
--- a/test/CodeGen/X86/negate-add-zero.ll
+++ b/test/CodeGen/X86/negate-add-zero.ll
@@ -486,8 +486,6 @@ declare void @_ZN7CDSListIP9HingeNodeEC1Eii(%"struct.CDSList<HingeNode*>"*, i32,
 
 declare i8* @_Znwm(i32)
 
-declare i32 @llvm.eh.typeid.for.i32(i8*) nounwind
-
 declare void @_ZdlPv(i8*) nounwind
 
 declare i32 @__gxx_personality_v0(...)
@@ -827,39 +825,39 @@ declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi6ELi0ELi0EEEENT_13
 declare void @_ZN21HNodeTranslateRotate311toCartesianEv(%struct.HNodeTranslateRotate3*)
 
 define linkonce void @_ZN21HNodeTranslateRotate36setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate3* %this, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"* %velv) {
-	%1 = getelementptr double* null, i32 -1		; <double*> [#uses=1]
-	%2 = load double* %1, align 8		; <double> [#uses=1]
-	%3 = load double* null, align 8		; <double> [#uses=2]
-	%4 = load double* null, align 8		; <double> [#uses=2]
-	%5 = load double* null, align 8		; <double> [#uses=3]
-	%6 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 0		; <double*> [#uses=0]
-	%7 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 1		; <double*> [#uses=0]
-	%8 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 2		; <double*> [#uses=0]
-	%9 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 3		; <double*> [#uses=0]
-	%10 = load double* null, align 8		; <double> [#uses=2]
+	%1 = getelementptr double, double* null, i32 -1		; <double*> [#uses=1]
+	%2 = load double, double* %1, align 8		; <double> [#uses=1]
+	%3 = load double, double* null, align 8		; <double> [#uses=2]
+	%4 = load double, double* null, align 8		; <double> [#uses=2]
+	%5 = load double, double* null, align 8		; <double> [#uses=3]
+	%6 = getelementptr %struct.HNodeTranslateRotate3, %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 0		; <double*> [#uses=0]
+	%7 = getelementptr %struct.HNodeTranslateRotate3, %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 1		; <double*> [#uses=0]
+	%8 = getelementptr %struct.HNodeTranslateRotate3, %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 2		; <double*> [#uses=0]
+	%9 = getelementptr %struct.HNodeTranslateRotate3, %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 3		; <double*> [#uses=0]
+	%10 = load double, double* null, align 8		; <double> [#uses=2]
 	%11 = fsub double -0.000000e+00, %10		; <double> [#uses=1]
-	%12 = load double* null, align 8		; <double> [#uses=2]
-	%13 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 1, i32 0, i32 0, i32 0, i32 3		; <double*> [#uses=1]
-	%14 = load double* %13, align 8		; <double> [#uses=2]
+	%12 = load double, double* null, align 8		; <double> [#uses=2]
+	%13 = getelementptr %struct.HNodeTranslateRotate3, %struct.HNodeTranslateRotate3* %this, i32 0, i32 1, i32 0, i32 0, i32 0, i32 3		; <double*> [#uses=1]
+	%14 = load double, double* %13, align 8		; <double> [#uses=2]
 	%15 = fsub double -0.000000e+00, %14		; <double> [#uses=1]
-	%16 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 1, i32 0, i32 0, i32 0, i32 2		; <double*> [#uses=1]
-	%17 = load double* %16, align 8		; <double> [#uses=2]
+	%16 = getelementptr %struct.HNodeTranslateRotate3, %struct.HNodeTranslateRotate3* %this, i32 0, i32 1, i32 0, i32 0, i32 0, i32 2		; <double*> [#uses=1]
+	%17 = load double, double* %16, align 8		; <double> [#uses=2]
 	%18 = fsub double -0.000000e+00, %17		; <double> [#uses=1]
-	%19 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 0		; <double*> [#uses=0]
-	%20 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 3		; <double*> [#uses=0]
-	%21 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 6		; <double*> [#uses=0]
-	%22 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 9		; <double*> [#uses=0]
-	%23 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 1		; <double*> [#uses=0]
-	%24 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 4		; <double*> [#uses=0]
-	%25 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 7		; <double*> [#uses=0]
-	%26 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 10		; <double*> [#uses=0]
-	%27 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 2		; <double*> [#uses=0]
-	%28 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 5		; <double*> [#uses=0]
-	%29 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 8		; <double*> [#uses=0]
-	%30 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 11		; <double*> [#uses=0]
-	%31 = getelementptr %"struct.FixedMatrix<double,1,3,0,0>"* null, i32 0, i32 0, i32 0, i32 0		; <double*> [#uses=0]
-	%32 = getelementptr %"struct.FixedMatrix<double,1,3,0,0>"* null, i32 0, i32 0, i32 0, i32 1		; <double*> [#uses=1]
-	%33 = getelementptr %"struct.FixedMatrix<double,1,3,0,0>"* null, i32 0, i32 0, i32 0, i32 2		; <double*> [#uses=1]
+	%19 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>", %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 0		; <double*> [#uses=0]
+	%20 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>", %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 3		; <double*> [#uses=0]
+	%21 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>", %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 6		; <double*> [#uses=0]
+	%22 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>", %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 9		; <double*> [#uses=0]
+	%23 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>", %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 1		; <double*> [#uses=0]
+	%24 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>", %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 4		; <double*> [#uses=0]
+	%25 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>", %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 7		; <double*> [#uses=0]
+	%26 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>", %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 10		; <double*> [#uses=0]
+	%27 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>", %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 2		; <double*> [#uses=0]
+	%28 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>", %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 5		; <double*> [#uses=0]
+	%29 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>", %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 8		; <double*> [#uses=0]
+	%30 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>", %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 11		; <double*> [#uses=0]
+	%31 = getelementptr %"struct.FixedMatrix<double,1,3,0,0>", %"struct.FixedMatrix<double,1,3,0,0>"* null, i32 0, i32 0, i32 0, i32 0		; <double*> [#uses=0]
+	%32 = getelementptr %"struct.FixedMatrix<double,1,3,0,0>", %"struct.FixedMatrix<double,1,3,0,0>"* null, i32 0, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%33 = getelementptr %"struct.FixedMatrix<double,1,3,0,0>", %"struct.FixedMatrix<double,1,3,0,0>"* null, i32 0, i32 0, i32 0, i32 2		; <double*> [#uses=1]
 	%34 = fmul double %17, %5		; <double> [#uses=1]
 	%35 = fadd double 0.000000e+00, %34		; <double> [#uses=1]
 	%36 = fadd double 0.000000e+00, 0.000000e+00		; <double> [#uses=1]
@@ -882,17 +880,17 @@ define linkonce void @_ZN21HNodeTranslateRotate36setVelERK9CDSVectorIdLi1EN3CDS1
 	%51 = fmul double %35, 2.000000e+00		; <double> [#uses=1]
 	%52 = fmul double %42, 2.000000e+00		; <double> [#uses=1]
 	%53 = fmul double %50, 2.000000e+00		; <double> [#uses=1]
-	%54 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 0, i32 10, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%54 = getelementptr %struct.HNodeTranslateRotate3, %struct.HNodeTranslateRotate3* %this, i32 0, i32 0, i32 10, i32 0, i32 0, i32 0		; <double*> [#uses=1]
 	store double %51, double* %54, align 8
-	%55 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 0, i32 10, i32 0, i32 0, i32 1		; <double*> [#uses=1]
+	%55 = getelementptr %struct.HNodeTranslateRotate3, %struct.HNodeTranslateRotate3* %this, i32 0, i32 0, i32 10, i32 0, i32 0, i32 1		; <double*> [#uses=1]
 	store double %52, double* %55, align 8
-	%56 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 0, i32 10, i32 0, i32 0, i32 2		; <double*> [#uses=1]
+	%56 = getelementptr %struct.HNodeTranslateRotate3, %struct.HNodeTranslateRotate3* %this, i32 0, i32 0, i32 10, i32 0, i32 0, i32 2		; <double*> [#uses=1]
 	store double %53, double* %56, align 8
-	%57 = getelementptr %"struct.SubVector<CDSVector<double, 1, CDS::DefaultAlloc> >"* null, i32 0, i32 0		; <%"struct.CDSVector<double,0,CDS::DefaultAlloc>"**> [#uses=1]
+	%57 = getelementptr %"struct.SubVector<CDSVector<double, 1, CDS::DefaultAlloc> >", %"struct.SubVector<CDSVector<double, 1, CDS::DefaultAlloc> >"* null, i32 0, i32 0		; <%"struct.CDSVector<double,0,CDS::DefaultAlloc>"**> [#uses=1]
 	store %"struct.CDSVector<double,0,CDS::DefaultAlloc>"* %velv, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"** %57, align 8
-	%58 = getelementptr %"struct.SubVector<CDSVector<double, 1, CDS::DefaultAlloc> >"* null, i32 0, i32 1		; <i32*> [#uses=1]
+	%58 = getelementptr %"struct.SubVector<CDSVector<double, 1, CDS::DefaultAlloc> >", %"struct.SubVector<CDSVector<double, 1, CDS::DefaultAlloc> >"* null, i32 0, i32 1		; <i32*> [#uses=1]
 	store i32 4, i32* %58, align 4
-	%59 = getelementptr %"struct.SubVector<CDSVector<double, 1, CDS::DefaultAlloc> >"* null, i32 0, i32 2		; <i32*> [#uses=1]
+	%59 = getelementptr %"struct.SubVector<CDSVector<double, 1, CDS::DefaultAlloc> >", %"struct.SubVector<CDSVector<double, 1, CDS::DefaultAlloc> >"* null, i32 0, i32 2		; <i32*> [#uses=1]
 	store i32 3, i32* %59, align 8
 	unreachable
 }
diff --git a/test/CodeGen/X86/negative-subscript.ll b/test/CodeGen/X86/negative-subscript.ll
index 28f7d6b2dbae..f69157551b7a 100644
--- a/test/CodeGen/X86/negative-subscript.ll
+++ b/test/CodeGen/X86/negative-subscript.ll
@@ -5,6 +5,6 @@
 
 define i32 @main() nounwind {
 entry:
-	store i8* bitcast (i8** getelementptr ([255 x i8*]* @a, i32 0, i32 -2147483624) to i8*), i8** getelementptr ([255 x i8*]* @a, i32 0, i32 16), align 32
+	store i8* bitcast (i8** getelementptr ([255 x i8*], [255 x i8*]* @a, i32 0, i32 -2147483624) to i8*), i8** getelementptr ([255 x i8*], [255 x i8*]* @a, i32 0, i32 16), align 32
 	ret i32 0
 }
diff --git a/test/CodeGen/X86/no-cmov.ll b/test/CodeGen/X86/no-cmov.ll
index e13edf26cad7..8fc0f7075c0e 100644
--- a/test/CodeGen/X86/no-cmov.ll
+++ b/test/CodeGen/X86/no-cmov.ll
@@ -2,7 +2,7 @@
 
 define i32 @test1(i32 %g, i32* %j) {
   %tobool = icmp eq i32 %g, 0
-  %cmp = load i32* %j, align 4
+  %cmp = load i32, i32* %j, align 4
   %retval.0 = select i1 %tobool, i32 1, i32 %cmp
   ret i32 %retval.0
 
diff --git a/test/CodeGen/X86/non-unique-sections.ll b/test/CodeGen/X86/non-unique-sections.ll
new file mode 100644
index 000000000000..e588b9dda98d
--- /dev/null
+++ b/test/CodeGen/X86/non-unique-sections.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux -function-sections -unique-section-names=false | FileCheck %s
+
+; CHECK:   .section                      .text,"ax",@progbits,unique
+; CHECK-NOT: section
+; CHECK: f:
+define void @f() {
+  ret void
+}
+
+; CHECK:   .section                      .text,"ax",@progbits,unique
+; CHECK-NOT: section
+; CHECK: g:
+define void @g() {
+  ret void
+}
diff --git a/test/CodeGen/X86/nontemporal-2.ll b/test/CodeGen/X86/nontemporal-2.ll
index f62f3725d7d8..8c08b3c163c0 100644
--- a/test/CodeGen/X86/nontemporal-2.ll
+++ b/test/CodeGen/X86/nontemporal-2.ll
@@ -1,31 +1,303 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7 | FileCheck %s -check-prefix=CHECK -check-prefix=SSE
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx | FileCheck %s -check-prefix=CHECK -check-prefix=AVX
-
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx2 | FileCheck %s -check-prefix=CHECK -check-prefix=AVX2
 
 ; Make sure that we generate non-temporal stores for the test cases below.
+; We use xorps for zeroing, so domain information isn't available anymore.
 
-define void @test1(<4 x float>* %dst) {
-; CHECK-LABEL: test1:
+define void @test_zero_v4f32(<4 x float>* %dst) {
+; CHECK-LABEL: test_zero_v4f32:
 ; SSE: movntps
 ; AVX: vmovntps
   store <4 x float> zeroinitializer, <4 x float>* %dst, align 16, !nontemporal !1
   ret void
 }
 
-define void @test2(<4 x i32>* %dst) {
-; CHECK-LABEL: test2:
+define void @test_zero_v4i32(<4 x i32>* %dst) {
+; CHECK-LABEL: test_zero_v4i32:
 ; SSE: movntps
 ; AVX: vmovntps
   store <4 x i32> zeroinitializer, <4 x i32>* %dst, align 16, !nontemporal !1
   ret void
 }
 
-define void @test3(<2 x double>* %dst) {
-; CHECK-LABEL: test3:
+define void @test_zero_v2f64(<2 x double>* %dst) {
+; CHECK-LABEL: test_zero_v2f64:
 ; SSE: movntps
 ; AVX: vmovntps
   store <2 x double> zeroinitializer, <2 x double>* %dst, align 16, !nontemporal !1
   ret void
 }
 
+define void @test_zero_v2i64(<2 x i64>* %dst) {
+; CHECK-LABEL: test_zero_v2i64:
+; SSE: movntps
+; AVX: vmovntps
+  store <2 x i64> zeroinitializer, <2 x i64>* %dst, align 16, !nontemporal !1
+  ret void
+}
+
+define void @test_zero_v8i16(<8 x i16>* %dst) {
+; CHECK-LABEL: test_zero_v8i16:
+; SSE: movntps
+; AVX: vmovntps
+  store <8 x i16> zeroinitializer, <8 x i16>* %dst, align 16, !nontemporal !1
+  ret void
+}
+
+define void @test_zero_v16i8(<16 x i8>* %dst) {
+; CHECK-LABEL: test_zero_v16i8:
+; SSE: movntps
+; AVX: vmovntps
+  store <16 x i8> zeroinitializer, <16 x i8>* %dst, align 16, !nontemporal !1
+  ret void
+}
+
+; And now YMM versions.
+
+define void @test_zero_v8f32(<8 x float>* %dst) {
+; CHECK-LABEL: test_zero_v8f32:
+; AVX: vmovntps %ymm
+  store <8 x float> zeroinitializer, <8 x float>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+define void @test_zero_v8i32(<8 x i32>* %dst) {
+; CHECK-LABEL: test_zero_v8i32:
+; AVX2: vmovntps %ymm
+  store <8 x i32> zeroinitializer, <8 x i32>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+define void @test_zero_v4f64(<4 x double>* %dst) {
+; CHECK-LABEL: test_zero_v4f64:
+; AVX: vmovntps %ymm
+  store <4 x double> zeroinitializer, <4 x double>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+define void @test_zero_v4i64(<4 x i64>* %dst) {
+; CHECK-LABEL: test_zero_v4i64:
+; AVX2: vmovntps %ymm
+  store <4 x i64> zeroinitializer, <4 x i64>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+define void @test_zero_v16i16(<16 x i16>* %dst) {
+; CHECK-LABEL: test_zero_v16i16:
+; AVX2: vmovntps %ymm
+  store <16 x i16> zeroinitializer, <16 x i16>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+define void @test_zero_v32i8(<32 x i8>* %dst) {
+; CHECK-LABEL: test_zero_v32i8:
+; AVX2: vmovntps %ymm
+  store <32 x i8> zeroinitializer, <32 x i8>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+
+; Check that we also handle arguments.  Here the type survives longer.
+
+define void @test_arg_v4f32(<4 x float> %arg, <4 x float>* %dst) {
+; CHECK-LABEL: test_arg_v4f32:
+; SSE: movntps
+; AVX: vmovntps
+  store <4 x float> %arg, <4 x float>* %dst, align 16, !nontemporal !1
+  ret void
+}
+
+define void @test_arg_v4i32(<4 x i32> %arg, <4 x i32>* %dst) {
+; CHECK-LABEL: test_arg_v4i32:
+; SSE: movntps
+; AVX: vmovntps
+  store <4 x i32> %arg, <4 x i32>* %dst, align 16, !nontemporal !1
+  ret void
+}
+
+define void @test_arg_v2f64(<2 x double> %arg, <2 x double>* %dst) {
+; CHECK-LABEL: test_arg_v2f64:
+; SSE: movntps
+; AVX: vmovntps
+  store <2 x double> %arg, <2 x double>* %dst, align 16, !nontemporal !1
+  ret void
+}
+
+define void @test_arg_v2i64(<2 x i64> %arg, <2 x i64>* %dst) {
+; CHECK-LABEL: test_arg_v2i64:
+; SSE: movntps
+; AVX: vmovntps
+  store <2 x i64> %arg, <2 x i64>* %dst, align 16, !nontemporal !1
+  ret void
+}
+
+define void @test_arg_v8i16(<8 x i16> %arg, <8 x i16>* %dst) {
+; CHECK-LABEL: test_arg_v8i16:
+; SSE: movntps
+; AVX: vmovntps
+  store <8 x i16> %arg, <8 x i16>* %dst, align 16, !nontemporal !1
+  ret void
+}
+
+define void @test_arg_v16i8(<16 x i8> %arg, <16 x i8>* %dst) {
+; CHECK-LABEL: test_arg_v16i8:
+; SSE: movntps
+; AVX: vmovntps
+  store <16 x i8> %arg, <16 x i8>* %dst, align 16, !nontemporal !1
+  ret void
+}
+
+; And now YMM versions.
+
+define void @test_arg_v8f32(<8 x float> %arg, <8 x float>* %dst) {
+; CHECK-LABEL: test_arg_v8f32:
+; AVX: vmovntps %ymm
+  store <8 x float> %arg, <8 x float>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+define void @test_arg_v8i32(<8 x i32> %arg, <8 x i32>* %dst) {
+; CHECK-LABEL: test_arg_v8i32:
+; AVX2: vmovntps %ymm
+  store <8 x i32> %arg, <8 x i32>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+define void @test_arg_v4f64(<4 x double> %arg, <4 x double>* %dst) {
+; CHECK-LABEL: test_arg_v4f64:
+; AVX: vmovntps %ymm
+  store <4 x double> %arg, <4 x double>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+define void @test_arg_v4i64(<4 x i64> %arg, <4 x i64>* %dst) {
+; CHECK-LABEL: test_arg_v4i64:
+; AVX2: vmovntps %ymm
+  store <4 x i64> %arg, <4 x i64>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+define void @test_arg_v16i16(<16 x i16> %arg, <16 x i16>* %dst) {
+; CHECK-LABEL: test_arg_v16i16:
+; AVX2: vmovntps %ymm
+  store <16 x i16> %arg, <16 x i16>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+define void @test_arg_v32i8(<32 x i8> %arg, <32 x i8>* %dst) {
+; CHECK-LABEL: test_arg_v32i8:
+; AVX2: vmovntps %ymm
+  store <32 x i8> %arg, <32 x i8>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+
+; Now check that if the execution domain is trivially visible, we use it.
+; We use an add to make the type survive all the way to the MOVNT.
+
+define void @test_op_v4f32(<4 x float> %a, <4 x float> %b, <4 x float>* %dst) {
+; CHECK-LABEL: test_op_v4f32:
+; SSE: movntps
+; AVX: vmovntps
+  %r = fadd <4 x float> %a, %b
+  store <4 x float> %r, <4 x float>* %dst, align 16, !nontemporal !1
+  ret void
+}
+
+define void @test_op_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32>* %dst) {
+; CHECK-LABEL: test_op_v4i32:
+; SSE: movntdq
+; AVX: vmovntdq
+  %r = add <4 x i32> %a, %b
+  store <4 x i32> %r, <4 x i32>* %dst, align 16, !nontemporal !1
+  ret void
+}
+
+define void @test_op_v2f64(<2 x double> %a, <2 x double> %b, <2 x double>* %dst) {
+; CHECK-LABEL: test_op_v2f64:
+; SSE: movntpd
+; AVX: vmovntpd
+  %r = fadd <2 x double> %a, %b
+  store <2 x double> %r, <2 x double>* %dst, align 16, !nontemporal !1
+  ret void
+}
+
+define void @test_op_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64>* %dst) {
+; CHECK-LABEL: test_op_v2i64:
+; SSE: movntdq
+; AVX: vmovntdq
+  %r = add <2 x i64> %a, %b
+  store <2 x i64> %r, <2 x i64>* %dst, align 16, !nontemporal !1
+  ret void
+}
+
+define void @test_op_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16>* %dst) {
+; CHECK-LABEL: test_op_v8i16:
+; SSE: movntdq
+; AVX: vmovntdq
+  %r = add <8 x i16> %a, %b
+  store <8 x i16> %r, <8 x i16>* %dst, align 16, !nontemporal !1
+  ret void
+}
+
+define void @test_op_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8>* %dst) {
+; CHECK-LABEL: test_op_v16i8:
+; SSE: movntdq
+; AVX: vmovntdq
+  %r = add <16 x i8> %a, %b
+  store <16 x i8> %r, <16 x i8>* %dst, align 16, !nontemporal !1
+  ret void
+}
+
+; And now YMM versions.
+
+define void @test_op_v8f32(<8 x float> %a, <8 x float> %b, <8 x float>* %dst) {
+; CHECK-LABEL: test_op_v8f32:
+; AVX: vmovntps %ymm
+  %r = fadd <8 x float> %a, %b
+  store <8 x float> %r, <8 x float>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+define void @test_op_v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32>* %dst) {
+; CHECK-LABEL: test_op_v8i32:
+; AVX2: vmovntdq %ymm
+  %r = add <8 x i32> %a, %b
+  store <8 x i32> %r, <8 x i32>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+define void @test_op_v4f64(<4 x double> %a, <4 x double> %b, <4 x double>* %dst) {
+; CHECK-LABEL: test_op_v4f64:
+; AVX: vmovntpd %ymm
+  %r = fadd <4 x double> %a, %b
+  store <4 x double> %r, <4 x double>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+define void @test_op_v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64>* %dst) {
+; CHECK-LABEL: test_op_v4i64:
+; AVX2: vmovntdq %ymm
+  %r = add <4 x i64> %a, %b
+  store <4 x i64> %r, <4 x i64>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+define void @test_op_v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16>* %dst) {
+; CHECK-LABEL: test_op_v16i16:
+; AVX2: vmovntdq %ymm
+  %r = add <16 x i16> %a, %b
+  store <16 x i16> %r, <16 x i16>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
+define void @test_op_v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8>* %dst) {
+; CHECK-LABEL: test_op_v32i8:
+; AVX2: vmovntdq %ymm
+  %r = add <32 x i8> %a, %b
+  store <32 x i8> %r, <32 x i8>* %dst, align 32, !nontemporal !1
+  ret void
+}
+
 !1 = !{i32 1}
diff --git a/test/CodeGen/X86/norex-subreg.ll b/test/CodeGen/X86/norex-subreg.ll
index fb41dede287f..dd47af9ae9ab 100644
--- a/test/CodeGen/X86/norex-subreg.ll
+++ b/test/CodeGen/X86/norex-subreg.ll
@@ -15,17 +15,17 @@ target triple = "x86_64-apple-macosx10.7"
 
 define void @f() nounwind uwtable ssp {
 entry:
-  %0 = load i32* undef, align 4
+  %0 = load i32, i32* undef, align 4
   %add = add i32 0, %0
   %conv1 = trunc i32 %add to i16
   %bf.value = and i16 %conv1, 255
   %1 = and i16 %bf.value, 255
   %2 = shl i16 %1, 8
-  %3 = load i16* undef, align 1
+  %3 = load i16, i16* undef, align 1
   %4 = and i16 %3, 255
   %5 = or i16 %4, %2
   store i16 %5, i16* undef, align 1
-  %6 = load i16* undef, align 1
+  %6 = load i16, i16* undef, align 1
   %7 = lshr i16 %6, 8
   %bf.clear2 = and i16 %7, 255
   %conv3 = zext i16 %bf.clear2 to i32
diff --git a/test/CodeGen/X86/nosse-error1.ll b/test/CodeGen/X86/nosse-error1.ll
index 291379eeaec9..7617d59f4a05 100644
--- a/test/CodeGen/X86/nosse-error1.ll
+++ b/test/CodeGen/X86/nosse-error1.ll
@@ -12,16 +12,16 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define void @test() nounwind {
 entry:
-	%0 = load float* @f, align 4		; <float> [#uses=1]
+	%0 = load float, float* @f, align 4		; <float> [#uses=1]
 	%1 = tail call float @foo1(float %0) nounwind		; <float> [#uses=1]
 	store float %1, float* @f, align 4
-	%2 = load double* @d, align 8		; <double> [#uses=1]
+	%2 = load double, double* @d, align 8		; <double> [#uses=1]
 	%3 = tail call double @foo2(double %2) nounwind		; <double> [#uses=1]
 	store double %3, double* @d, align 8
-	%4 = load float* @f, align 4		; <float> [#uses=1]
+	%4 = load float, float* @f, align 4		; <float> [#uses=1]
 	%5 = tail call float @foo3(float %4) nounwind		; <float> [#uses=1]
 	store float %5, float* @f, align 4
-	%6 = load double* @d, align 8		; <double> [#uses=1]
+	%6 = load double, double* @d, align 8		; <double> [#uses=1]
 	%7 = tail call double @foo4(double %6) nounwind		; <double> [#uses=1]
 	store double %7, double* @d, align 8
 	ret void
diff --git a/test/CodeGen/X86/nosse-error2.ll b/test/CodeGen/X86/nosse-error2.ll
index a7cee2dd8211..3da80aae686f 100644
--- a/test/CodeGen/X86/nosse-error2.ll
+++ b/test/CodeGen/X86/nosse-error2.ll
@@ -12,16 +12,16 @@ target triple = "i386-unknown-linux-gnu"
 
 define void @test() nounwind {
 entry:
-	%0 = load float* @f, align 4		; <float> [#uses=1]
+	%0 = load float, float* @f, align 4		; <float> [#uses=1]
 	%1 = tail call inreg float @foo1(float inreg %0) nounwind		; <float> [#uses=1]
 	store float %1, float* @f, align 4
-	%2 = load double* @d, align 8		; <double> [#uses=1]
+	%2 = load double, double* @d, align 8		; <double> [#uses=1]
 	%3 = tail call inreg double @foo2(double inreg %2) nounwind		; <double> [#uses=1]
 	store double %3, double* @d, align 8
-	%4 = load float* @f, align 4		; <float> [#uses=1]
+	%4 = load float, float* @f, align 4		; <float> [#uses=1]
 	%5 = tail call inreg float @foo3(float inreg %4) nounwind		; <float> [#uses=1]
 	store float %5, float* @f, align 4
-	%6 = load double* @d, align 8		; <double> [#uses=1]
+	%6 = load double, double* @d, align 8		; <double> [#uses=1]
 	%7 = tail call inreg double @foo4(double inreg %6) nounwind		; <double> [#uses=1]
 	store double %7, double* @d, align 8
 	ret void
diff --git a/test/CodeGen/X86/nosse-varargs.ll b/test/CodeGen/X86/nosse-varargs.ll
index e6da0ab5e371..8a81d0e71953 100644
--- a/test/CodeGen/X86/nosse-varargs.ll
+++ b/test/CodeGen/X86/nosse-varargs.ll
@@ -1,42 +1,43 @@
-; RUN: llvm-as < %s > %t
-; RUN: llc -march=x86-64 -mattr=-sse < %t | not grep xmm
-; RUN: llc -march=x86-64 < %t | grep xmm
+; RUN: llc < %s -march=x86-64 -mattr=-sse | FileCheck %s -check-prefix=NOSSE
+; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=YESSSE
 ; PR3403
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-unknown-linux-gnu"
 	%struct.__va_list_tag = type { i32, i32, i8*, i8* }
 
+; NOSSE-NOT: xmm
+; YESSSE: xmm
 define i32 @foo(float %a, i8* nocapture %fmt, ...) nounwind {
 entry:
 	%ap = alloca [1 x %struct.__va_list_tag], align 8		; <[1 x %struct.__va_list_tag]*> [#uses=4]
 	%ap12 = bitcast [1 x %struct.__va_list_tag]* %ap to i8*		; <i8*> [#uses=2]
 	call void @llvm.va_start(i8* %ap12)
-	%0 = getelementptr [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0, i32 0		; <i32*> [#uses=2]
-	%1 = load i32* %0, align 8		; <i32> [#uses=3]
+	%0 = getelementptr [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0, i32 0		; <i32*> [#uses=2]
+	%1 = load i32, i32* %0, align 8		; <i32> [#uses=3]
 	%2 = icmp ult i32 %1, 48		; <i1> [#uses=1]
 	br i1 %2, label %bb, label %bb3
 
 bb:		; preds = %entry
-	%3 = getelementptr [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0, i32 3		; <i8**> [#uses=1]
-	%4 = load i8** %3, align 8		; <i8*> [#uses=1]
+	%3 = getelementptr [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0, i32 3		; <i8**> [#uses=1]
+	%4 = load i8*, i8** %3, align 8		; <i8*> [#uses=1]
 	%5 = inttoptr i32 %1 to i8*		; <i8*> [#uses=1]
 	%6 = ptrtoint i8* %5 to i64		; <i64> [#uses=1]
-	%ctg2 = getelementptr i8* %4, i64 %6		; <i8*> [#uses=1]
+	%ctg2 = getelementptr i8, i8* %4, i64 %6		; <i8*> [#uses=1]
 	%7 = add i32 %1, 8		; <i32> [#uses=1]
 	store i32 %7, i32* %0, align 8
 	br label %bb4
 
 bb3:		; preds = %entry
-	%8 = getelementptr [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0, i32 2		; <i8**> [#uses=2]
-	%9 = load i8** %8, align 8		; <i8*> [#uses=2]
-	%10 = getelementptr i8* %9, i64 8		; <i8*> [#uses=1]
+	%8 = getelementptr [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0, i32 2		; <i8**> [#uses=2]
+	%9 = load i8*, i8** %8, align 8		; <i8*> [#uses=2]
+	%10 = getelementptr i8, i8* %9, i64 8		; <i8*> [#uses=1]
 	store i8* %10, i8** %8, align 8
 	br label %bb4
 
 bb4:		; preds = %bb3, %bb
 	%addr.0.0 = phi i8* [ %ctg2, %bb ], [ %9, %bb3 ]		; <i8*> [#uses=1]
 	%11 = bitcast i8* %addr.0.0 to i32*		; <i32*> [#uses=1]
-	%12 = load i32* %11, align 4		; <i32> [#uses=1]
+	%12 = load i32, i32* %11, align 4		; <i32> [#uses=1]
 	call void @llvm.va_end(i8* %ap12)
 	ret i32 %12
 }
diff --git a/test/CodeGen/X86/null-streamer.ll b/test/CodeGen/X86/null-streamer.ll
index f6eb0e15aabb..3f5abfd40f29 100644
--- a/test/CodeGen/X86/null-streamer.ll
+++ b/test/CodeGen/X86/null-streamer.ll
@@ -14,16 +14,15 @@ define void @f1() {
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!11, !13}
 
-!0 = !{!"0x11\004\00 \001\00\000\00\000", !1, !2, !2, !3, !9, !2} ; [ DW_TAG_compile_unit ]
-!1 = !{!"", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: " ", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !9, imports: !2)
+!1 = !DIFile(filename: "file.c", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00\00\00\002\000\001\000\006\00256\001\002", !1, !5, !6, null, i32 ()* null, null, null, !2} ; [ DW_TAG_subprogram ]
-!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ]
+!4 = !DISubprogram(name: "", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2, file: !1, scope: !1, type: !6, function: i32 ()* null, variables: !2)
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
+!8 = !DIBasicType(tag: DW_TAG_base_type, size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{!10}
-!10 = !{!"0x34\00i\00i\00_ZL1i\001\001\001", null, !5, !8, null, null} ; [ DW_TAG_variable ]
+!10 = !DIGlobalVariable(name: "i", linkageName: "_ZL1i", line: 1, isLocal: true, isDefinition: true, scope: null, file: !1, type: !8)
 !11 = !{i32 2, !"Dwarf Version", i32 3}
-!13 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/object-size.ll b/test/CodeGen/X86/object-size.ll
index 0610f0b6de2e..9f42af4aea95 100644
--- a/test/CodeGen/X86/object-size.ll
+++ b/test/CodeGen/X86/object-size.ll
@@ -9,7 +9,7 @@ target triple = "x86_64-apple-darwin10.0"
 
 define void @bar() nounwind ssp {
 entry:
-  %tmp = load i8** @p                             ; <i8*> [#uses=1]
+  %tmp = load i8*, i8** @p                             ; <i8*> [#uses=1]
   %0 = call i64 @llvm.objectsize.i64.p0i8(i8* %tmp, i1 0) ; <i64> [#uses=1]
   %cmp = icmp ne i64 %0, -1                       ; <i1> [#uses=1]
 ; CHECK: movq $-1, [[RAX:%r..]]
@@ -17,15 +17,15 @@ entry:
   br i1 %cmp, label %cond.true, label %cond.false
 
 cond.true:                                        ; preds = %entry
-  %tmp1 = load i8** @p                            ; <i8*> [#uses=1]
-  %tmp2 = load i8** @p                            ; <i8*> [#uses=1]
+  %tmp1 = load i8*, i8** @p                            ; <i8*> [#uses=1]
+  %tmp2 = load i8*, i8** @p                            ; <i8*> [#uses=1]
   %1 = call i64 @llvm.objectsize.i64.p0i8(i8* %tmp2, i1 1) ; <i64> [#uses=1]
-  %call = call i8* @__strcpy_chk(i8* %tmp1, i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i64 %1) ssp ; <i8*> [#uses=1]
+  %call = call i8* @__strcpy_chk(i8* %tmp1, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i64 %1) ssp ; <i8*> [#uses=1]
   br label %cond.end
 
 cond.false:                                       ; preds = %entry
-  %tmp3 = load i8** @p                            ; <i8*> [#uses=1]
-  %call4 = call i8* @__inline_strcpy_chk(i8* %tmp3, i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0)) ssp ; <i8*> [#uses=1]
+  %tmp3 = load i8*, i8** @p                            ; <i8*> [#uses=1]
+  %call4 = call i8* @__inline_strcpy_chk(i8* %tmp3, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0)) ssp ; <i8*> [#uses=1]
   br label %cond.end
 
 cond.end:                                         ; preds = %cond.false, %cond.true
@@ -44,12 +44,12 @@ entry:
   %__src.addr = alloca i8*                        ; <i8**> [#uses=2]
   store i8* %__dest, i8** %__dest.addr
   store i8* %__src, i8** %__src.addr
-  %tmp = load i8** %__dest.addr                   ; <i8*> [#uses=1]
-  %tmp1 = load i8** %__src.addr                   ; <i8*> [#uses=1]
-  %tmp2 = load i8** %__dest.addr                  ; <i8*> [#uses=1]
+  %tmp = load i8*, i8** %__dest.addr                   ; <i8*> [#uses=1]
+  %tmp1 = load i8*, i8** %__src.addr                   ; <i8*> [#uses=1]
+  %tmp2 = load i8*, i8** %__dest.addr                  ; <i8*> [#uses=1]
   %0 = call i64 @llvm.objectsize.i64.p0i8(i8* %tmp2, i1 1) ; <i64> [#uses=1]
   %call = call i8* @__strcpy_chk(i8* %tmp, i8* %tmp1, i64 %0) ssp ; <i8*> [#uses=1]
   store i8* %call, i8** %retval
-  %1 = load i8** %retval                          ; <i8*> [#uses=1]
+  %1 = load i8*, i8** %retval                          ; <i8*> [#uses=1]
   ret i8* %1
 }
diff --git a/test/CodeGen/X86/odr_comdat.ll b/test/CodeGen/X86/odr_comdat.ll
deleted file mode 100644
index 547334c045a3..000000000000
--- a/test/CodeGen/X86/odr_comdat.ll
+++ /dev/null
@@ -1,16 +0,0 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s -check-prefix=X86LINUX
-
-; Checking that a comdat group gets generated correctly for a static member 
-; of instantiated C++ templates.
-; see http://sourcery.mentor.com/public/cxx-abi/abi.html#vague-itemplate
-; section 5.2.6 Instantiated templates
-; "Any static member data object is emitted in a COMDAT identified by its mangled 
-;  name, in any object file with a reference to its name symbol."
-
-; Case 1: variable is not explicitly initialized, and ends up in a .bss section
-; X86LINUX:   .section        .bss._ZN1CIiE1iE,"aGw",@nobits,_ZN1CIiE1iE,comdat
-@_ZN1CIiE1iE = weak_odr global i32 0, align 4
-
-; Case 2: variable is explicitly initialized, and ends up in a .data section
-; X86LINUX:   .section        .data._ZN1CIiE1jE,"aGw",@progbits,_ZN1CIiE1jE,comdat
-@_ZN1CIiE1jE = weak_odr global i32 12, align 4
diff --git a/test/CodeGen/X86/opaque-constant-asm.ll b/test/CodeGen/X86/opaque-constant-asm.ll
index dd1cc8ec4839..f5daed8869b9 100644
--- a/test/CodeGen/X86/opaque-constant-asm.ll
+++ b/test/CodeGen/X86/opaque-constant-asm.ll
@@ -8,6 +8,6 @@
 
 define void @test() {
 ; CHECK: #ASM $16
-  call void asm sideeffect "#ASM $0", "n"(i32 ptrtoint (i32* getelementptr inbounds (%struct2* bitcast (%union.anon* getelementptr inbounds (%struct1* null, i32 0, i32 1) to %struct2*), i32 0, i32 2) to i32))
+  call void asm sideeffect "#ASM $0", "n"(i32 ptrtoint (i32* getelementptr inbounds (%struct2, %struct2* bitcast (%union.anon* getelementptr inbounds (%struct1, %struct1* null, i32 0, i32 1) to %struct2*), i32 0, i32 2) to i32))
   ret void
 }
diff --git a/test/CodeGen/X86/opt-ext-uses.ll b/test/CodeGen/X86/opt-ext-uses.ll
index 72fb38b27dfe..5d05ad9c4544 100644
--- a/test/CodeGen/X86/opt-ext-uses.ll
+++ b/test/CodeGen/X86/opt-ext-uses.ll
@@ -2,7 +2,7 @@
 
 define signext i16 @t()   {
 entry:
-        %tmp180 = load i16* null, align 2               ; <i16> [#uses=3]
+        %tmp180 = load i16, i16* null, align 2               ; <i16> [#uses=3]
         %tmp180181 = sext i16 %tmp180 to i32            ; <i32> [#uses=1]
         %tmp182 = add i16 %tmp180, 10
         %tmp185 = icmp slt i16 %tmp182, 0               ; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/optimize-max-0.ll b/test/CodeGen/X86/optimize-max-0.ll
index 981a16a44971..006592aaade2 100644
--- a/test/CodeGen/X86/optimize-max-0.ll
+++ b/test/CodeGen/X86/optimize-max-0.ll
@@ -32,9 +32,9 @@ bb6:                                              ; preds = %bb7, %bb.nph7
   %7 = add i32 %x.06, %4
   %8 = shl i32 %x.06, 1
   %9 = add i32 %6, %8
-  %10 = getelementptr i8* %r, i32 %9
-  %11 = load i8* %10, align 1
-  %12 = getelementptr i8* %j, i32 %7
+  %10 = getelementptr i8, i8* %r, i32 %9
+  %11 = load i8, i8* %10, align 1
+  %12 = getelementptr i8, i8* %j, i32 %7
   store i8 %11, i8* %12, align 1
   br label %bb7
 
@@ -103,18 +103,18 @@ bb14:                                             ; preds = %bb15, %bb.nph3
   %x.12 = phi i32 [ 0, %bb.nph3 ], [ %indvar.next, %bb15 ]
   %25 = shl i32 %x.12, 2
   %26 = add i32 %25, %21
-  %27 = getelementptr i8* %r, i32 %26
-  %28 = load i8* %27, align 1
+  %27 = getelementptr i8, i8* %r, i32 %26
+  %28 = load i8, i8* %27, align 1
   %.sum = add i32 %22, %x.12
-  %29 = getelementptr i8* %j, i32 %.sum
+  %29 = getelementptr i8, i8* %j, i32 %.sum
   store i8 %28, i8* %29, align 1
   %30 = shl i32 %x.12, 2
   %31 = or i32 %30, 2
   %32 = add i32 %31, %21
-  %33 = getelementptr i8* %r, i32 %32
-  %34 = load i8* %33, align 1
+  %33 = getelementptr i8, i8* %r, i32 %32
+  %34 = load i8, i8* %33, align 1
   %.sum6 = add i32 %23, %x.12
-  %35 = getelementptr i8* %j, i32 %.sum6
+  %35 = getelementptr i8, i8* %j, i32 %.sum6
   store i8 %34, i8* %35, align 1
   br label %bb15
 
@@ -169,10 +169,10 @@ bb23:                                             ; preds = %bb24, %bb.nph
   %y.21 = phi i32 [ 0, %bb.nph ], [ %indvar.next5, %bb24 ]
   %45 = mul i32 %y.21, %42
   %.sum1 = add i32 %45, %43
-  %46 = getelementptr i8* %r, i32 %.sum1
+  %46 = getelementptr i8, i8* %r, i32 %.sum1
   %47 = mul i32 %y.21, %w
   %.sum5 = add i32 %47, %.sum3
-  %48 = getelementptr i8* %j, i32 %.sum5
+  %48 = getelementptr i8, i8* %j, i32 %.sum5
   tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %48, i8* %46, i32 %w, i32 1, i1 false)
   br label %bb24
 
@@ -187,7 +187,7 @@ bb24.bb26_crit_edge:                              ; preds = %bb24
 bb26:                                             ; preds = %bb24.bb26_crit_edge, %bb22
   %49 = mul i32 %x, %w
   %.sum4 = add i32 %.sum3, %49
-  %50 = getelementptr i8* %j, i32 %.sum4
+  %50 = getelementptr i8, i8* %j, i32 %.sum4
   %51 = mul i32 %x, %w
   %52 = sdiv i32 %51, 2
   tail call void @llvm.memset.p0i8.i32(i8* %50, i8 -128, i32 %52, i32 1, i1 false)
@@ -205,9 +205,9 @@ bb.nph11:                                         ; preds = %bb29
 bb30:                                             ; preds = %bb31, %bb.nph11
   %y.310 = phi i32 [ 0, %bb.nph11 ], [ %indvar.next13, %bb31 ]
   %56 = mul i32 %y.310, %54
-  %57 = getelementptr i8* %r, i32 %56
+  %57 = getelementptr i8, i8* %r, i32 %56
   %58 = mul i32 %y.310, %w
-  %59 = getelementptr i8* %j, i32 %58
+  %59 = getelementptr i8, i8* %j, i32 %58
   tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %59, i8* %57, i32 %w, i32 1, i1 false)
   br label %bb31
 
@@ -221,7 +221,7 @@ bb31.bb33_crit_edge:                              ; preds = %bb31
 
 bb33:                                             ; preds = %bb31.bb33_crit_edge, %bb29
   %60 = mul i32 %x, %w
-  %61 = getelementptr i8* %j, i32 %60
+  %61 = getelementptr i8, i8* %j, i32 %60
   %62 = mul i32 %x, %w
   %63 = sdiv i32 %62, 2
   tail call void @llvm.memset.p0i8.i32(i8* %61, i8 -128, i32 %63, i32 1, i1 false)
@@ -257,9 +257,9 @@ bb6:                                              ; preds = %bb7, %bb.nph7
   %7 = add i32 %x.06, %4
   %8 = shl i32 %x.06, 1
   %9 = add i32 %6, %8
-  %10 = getelementptr i8* %r, i32 %9
-  %11 = load i8* %10, align 1
-  %12 = getelementptr i8* %j, i32 %7
+  %10 = getelementptr i8, i8* %r, i32 %9
+  %11 = load i8, i8* %10, align 1
+  %12 = getelementptr i8, i8* %j, i32 %7
   store i8 %11, i8* %12, align 1
   br label %bb7
 
@@ -328,18 +328,18 @@ bb14:                                             ; preds = %bb15, %bb.nph3
   %x.12 = phi i32 [ 0, %bb.nph3 ], [ %indvar.next, %bb15 ]
   %25 = shl i32 %x.12, 2
   %26 = add i32 %25, %21
-  %27 = getelementptr i8* %r, i32 %26
-  %28 = load i8* %27, align 1
+  %27 = getelementptr i8, i8* %r, i32 %26
+  %28 = load i8, i8* %27, align 1
   %.sum = add i32 %22, %x.12
-  %29 = getelementptr i8* %j, i32 %.sum
+  %29 = getelementptr i8, i8* %j, i32 %.sum
   store i8 %28, i8* %29, align 1
   %30 = shl i32 %x.12, 2
   %31 = or i32 %30, 2
   %32 = add i32 %31, %21
-  %33 = getelementptr i8* %r, i32 %32
-  %34 = load i8* %33, align 1
+  %33 = getelementptr i8, i8* %r, i32 %32
+  %34 = load i8, i8* %33, align 1
   %.sum6 = add i32 %23, %x.12
-  %35 = getelementptr i8* %j, i32 %.sum6
+  %35 = getelementptr i8, i8* %j, i32 %.sum6
   store i8 %34, i8* %35, align 1
   br label %bb15
 
@@ -394,10 +394,10 @@ bb23:                                             ; preds = %bb24, %bb.nph
   %y.21 = phi i32 [ 0, %bb.nph ], [ %indvar.next5, %bb24 ]
   %45 = mul i32 %y.21, %42
   %.sum1 = add i32 %45, %43
-  %46 = getelementptr i8* %r, i32 %.sum1
+  %46 = getelementptr i8, i8* %r, i32 %.sum1
   %47 = mul i32 %y.21, %w
   %.sum5 = add i32 %47, %.sum3
-  %48 = getelementptr i8* %j, i32 %.sum5
+  %48 = getelementptr i8, i8* %j, i32 %.sum5
   tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %48, i8* %46, i32 %w, i32 1, i1 false)
   br label %bb24
 
@@ -412,7 +412,7 @@ bb24.bb26_crit_edge:                              ; preds = %bb24
 bb26:                                             ; preds = %bb24.bb26_crit_edge, %bb22
   %49 = mul i32 %x, %w
   %.sum4 = add i32 %.sum3, %49
-  %50 = getelementptr i8* %j, i32 %.sum4
+  %50 = getelementptr i8, i8* %j, i32 %.sum4
   %51 = mul i32 %x, %w
   %52 = udiv i32 %51, 2
   tail call void @llvm.memset.p0i8.i32(i8* %50, i8 -128, i32 %52, i32 1, i1 false)
@@ -430,9 +430,9 @@ bb.nph11:                                         ; preds = %bb29
 bb30:                                             ; preds = %bb31, %bb.nph11
   %y.310 = phi i32 [ 0, %bb.nph11 ], [ %indvar.next13, %bb31 ]
   %56 = mul i32 %y.310, %54
-  %57 = getelementptr i8* %r, i32 %56
+  %57 = getelementptr i8, i8* %r, i32 %56
   %58 = mul i32 %y.310, %w
-  %59 = getelementptr i8* %j, i32 %58
+  %59 = getelementptr i8, i8* %j, i32 %58
   tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %59, i8* %57, i32 %w, i32 1, i1 false)
   br label %bb31
 
@@ -446,7 +446,7 @@ bb31.bb33_crit_edge:                              ; preds = %bb31
 
 bb33:                                             ; preds = %bb31.bb33_crit_edge, %bb29
   %60 = mul i32 %x, %w
-  %61 = getelementptr i8* %j, i32 %60
+  %61 = getelementptr i8, i8* %j, i32 %60
   %62 = mul i32 %x, %w
   %63 = udiv i32 %62, 2
   tail call void @llvm.memset.p0i8.i32(i8* %61, i8 -128, i32 %63, i32 1, i1 false)
diff --git a/test/CodeGen/X86/optimize-max-1.ll b/test/CodeGen/X86/optimize-max-1.ll
index ad6c24dce009..11e2f9a93a57 100644
--- a/test/CodeGen/X86/optimize-max-1.ll
+++ b/test/CodeGen/X86/optimize-max-1.ll
@@ -13,7 +13,7 @@ entry:
 
 bb:		; preds = %bb, %entry
 	%i.0 = phi i64 [ 0, %entry ], [ %0, %bb ]		; <i64> [#uses=2]
-	%scevgep = getelementptr double* %p, i64 %i.0		; <double*> [#uses=1]
+	%scevgep = getelementptr double, double* %p, i64 %i.0		; <double*> [#uses=1]
 	store double 0.000000e+00, double* %scevgep, align 8
 	%0 = add i64 %i.0, 1		; <i64> [#uses=2]
 	%exitcond = icmp eq i64 %0, %smax		; <i1> [#uses=1]
@@ -31,7 +31,7 @@ entry:
 
 bb:		; preds = %bb, %entry
 	%i.0 = phi i64 [ 0, %entry ], [ %0, %bb ]		; <i64> [#uses=2]
-	%scevgep = getelementptr double* %p, i64 %i.0		; <double*> [#uses=1]
+	%scevgep = getelementptr double, double* %p, i64 %i.0		; <double*> [#uses=1]
 	store double 0.000000e+00, double* %scevgep, align 8
 	%0 = add i64 %i.0, 1		; <i64> [#uses=2]
 	%exitcond = icmp eq i64 %0, %smax		; <i1> [#uses=1]
@@ -49,7 +49,7 @@ entry:
 
 bb:		; preds = %bb, %entry
 	%i.0 = phi i64 [ 0, %entry ], [ %0, %bb ]		; <i64> [#uses=2]
-	%scevgep = getelementptr double* %p, i64 %i.0		; <double*> [#uses=1]
+	%scevgep = getelementptr double, double* %p, i64 %i.0		; <double*> [#uses=1]
 	store double 0.000000e+00, double* %scevgep, align 8
 	%0 = add i64 %i.0, 1		; <i64> [#uses=2]
 	%exitcond = icmp eq i64 %0, %umax		; <i1> [#uses=1]
@@ -67,7 +67,7 @@ entry:
 
 bb:		; preds = %bb, %entry
 	%i.0 = phi i64 [ 0, %entry ], [ %0, %bb ]		; <i64> [#uses=2]
-	%scevgep = getelementptr double* %p, i64 %i.0		; <double*> [#uses=1]
+	%scevgep = getelementptr double, double* %p, i64 %i.0		; <double*> [#uses=1]
 	store double 0.000000e+00, double* %scevgep, align 8
 	%0 = add i64 %i.0, 1		; <i64> [#uses=2]
 	%exitcond = icmp eq i64 %0, %umax		; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/optimize-max-2.ll b/test/CodeGen/X86/optimize-max-2.ll
index 10ab831c1e3d..45b542e2267c 100644
--- a/test/CodeGen/X86/optimize-max-2.ll
+++ b/test/CodeGen/X86/optimize-max-2.ll
@@ -19,8 +19,8 @@ entry:
 
 bb4:		; preds = %bb4, %entry
 	%i.07 = phi i64 [ 0, %entry ], [ %2, %bb4 ]		; <i64> [#uses=2]
-	%scevgep = getelementptr double* %p, i64 %i.07		; <double*> [#uses=2]
-	%0 = load double* %scevgep, align 8		; <double> [#uses=1]
+	%scevgep = getelementptr double, double* %p, i64 %i.07		; <double*> [#uses=2]
+	%0 = load double, double* %scevgep, align 8		; <double> [#uses=1]
 	%1 = fmul double %0, 2.000000e+00		; <double> [#uses=1]
 	store double %1, double* %scevgep, align 8
 	%2 = add i64 %i.07, 1		; <i64> [#uses=2]
diff --git a/test/CodeGen/X86/optimize-max-3.ll b/test/CodeGen/X86/optimize-max-3.ll
index 1b653736ad3b..71885efbd31f 100644
--- a/test/CodeGen/X86/optimize-max-3.ll
+++ b/test/CodeGen/X86/optimize-max-3.ll
@@ -20,8 +20,8 @@ for.body.preheader:                               ; preds = %entry
 
 for.body:                                         ; preds = %for.body.preheader, %for.body
   %i = phi i64 [ %i.next, %for.body ], [ 0, %for.body.preheader ] ; <i64> [#uses=2]
-  %arrayidx = getelementptr double* %p, i64 %i    ; <double*> [#uses=2]
-  %t4 = load double* %arrayidx                    ; <double> [#uses=1]
+  %arrayidx = getelementptr double, double* %p, i64 %i    ; <double*> [#uses=2]
+  %t4 = load double, double* %arrayidx                    ; <double> [#uses=1]
   %mul = fmul double %t4, 2.200000e+00            ; <double> [#uses=1]
   store double %mul, double* %arrayidx
   %i.next = add nsw i64 %i, 1                     ; <i64> [#uses=2]
diff --git a/test/CodeGen/X86/or-address.ll b/test/CodeGen/X86/or-address.ll
index 6bea864027bd..16b0aa60b689 100644
--- a/test/CodeGen/X86/or-address.ll
+++ b/test/CodeGen/X86/or-address.ll
@@ -26,16 +26,16 @@ bb:                                               ; preds = %bb, %bb.nph
   %4 = add i8 %3, %iftmp.0.0                      ; <i8> [#uses=1]
   %5 = shl i8 %4, 2                               ; <i8> [#uses=1]
   %6 = zext i8 %5 to i64                          ; <i64> [#uses=4]
-  %7 = getelementptr inbounds i32* %array, i64 %6 ; <i32*> [#uses=1]
+  %7 = getelementptr inbounds i32, i32* %array, i64 %6 ; <i32*> [#uses=1]
   store i32 %r0, i32* %7, align 4
   %8 = or i64 %6, 2                               ; <i64> [#uses=1]
-  %9 = getelementptr inbounds i32* %array, i64 %8 ; <i32*> [#uses=1]
+  %9 = getelementptr inbounds i32, i32* %array, i64 %8 ; <i32*> [#uses=1]
   store i32 %r0, i32* %9, align 4
   %10 = or i64 %6, 1                              ; <i64> [#uses=1]
-  %11 = getelementptr inbounds i32* %array, i64 %10 ; <i32*> [#uses=1]
+  %11 = getelementptr inbounds i32, i32* %array, i64 %10 ; <i32*> [#uses=1]
   store i32 %r0, i32* %11, align 4
   %12 = or i64 %6, 3                              ; <i64> [#uses=1]
-  %13 = getelementptr inbounds i32* %array, i64 %12 ; <i32*> [#uses=1]
+  %13 = getelementptr inbounds i32, i32* %array, i64 %12 ; <i32*> [#uses=1]
   store i32 %r0, i32* %13, align 4
   %14 = add nsw i8 %j.010, 1                      ; <i8> [#uses=2]
   %15 = add i8 %iftmp.0.0, 1                      ; <i8> [#uses=1]
@@ -69,16 +69,16 @@ for.body:                                         ; preds = %for.body, %bb.nph
   %mul22 = shl i8 %inc.k.addr.1, 4                ; <i8> [#uses=1]
   %add23 = add i8 %mul22, %mul                    ; <i8> [#uses=1]
   %idxprom = zext i8 %add23 to i64                ; <i64> [#uses=4]
-  %arrayidx = getelementptr inbounds i32* %array, i64 %idxprom ; <i32*> [#uses=1]
+  %arrayidx = getelementptr inbounds i32, i32* %array, i64 %idxprom ; <i32*> [#uses=1]
   store i32 %r0, i32* %arrayidx
   %add3356 = or i64 %idxprom, 2                   ; <i64> [#uses=1]
-  %arrayidx36 = getelementptr inbounds i32* %array, i64 %add3356 ; <i32*> [#uses=1]
+  %arrayidx36 = getelementptr inbounds i32, i32* %array, i64 %add3356 ; <i32*> [#uses=1]
   store i32 %r0, i32* %arrayidx36
   %add4058 = or i64 %idxprom, 1                   ; <i64> [#uses=1]
-  %arrayidx43 = getelementptr inbounds i32* %array, i64 %add4058 ; <i32*> [#uses=1]
+  %arrayidx43 = getelementptr inbounds i32, i32* %array, i64 %add4058 ; <i32*> [#uses=1]
   store i32 %r0, i32* %arrayidx43
   %add4760 = or i64 %idxprom, 3                   ; <i64> [#uses=1]
-  %arrayidx50 = getelementptr inbounds i32* %array, i64 %add4760 ; <i32*> [#uses=1]
+  %arrayidx50 = getelementptr inbounds i32, i32* %array, i64 %add4760 ; <i32*> [#uses=1]
   store i32 %r0, i32* %arrayidx50
   %inc52 = add nsw i8 %j.065, 1                   ; <i8> [#uses=2]
   %add = add i8 %cond, 1                          ; <i8> [#uses=1]
diff --git a/test/CodeGen/X86/or-branch.ll b/test/CodeGen/X86/or-branch.ll
index 9ebf8901b77c..ae3ed3f8344a 100644
--- a/test/CodeGen/X86/or-branch.ll
+++ b/test/CodeGen/X86/or-branch.ll
@@ -2,14 +2,14 @@
 
 define void @foo(i32 %X, i32 %Y, i32 %Z) nounwind {
 entry:
-	%tmp = tail call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp = tail call i32 (...) @bar( )		; <i32> [#uses=0]
 	%tmp.upgrd.1 = icmp eq i32 %X, 0		; <i1> [#uses=1]
 	%tmp3 = icmp slt i32 %Y, 5		; <i1> [#uses=1]
 	%tmp4 = or i1 %tmp3, %tmp.upgrd.1		; <i1> [#uses=1]
 	br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
 
 cond_true:		; preds = %entry
-	%tmp5 = tail call i32 (...)* @bar( )		; <i32> [#uses=0]
+	%tmp5 = tail call i32 (...) @bar( )		; <i32> [#uses=0]
 	ret void
 
 UnifiedReturnBlock:		; preds = %entry
diff --git a/test/CodeGen/X86/packed_struct.ll b/test/CodeGen/X86/packed_struct.ll
index da6e8f8745fe..c9aeb7deb4f3 100644
--- a/test/CodeGen/X86/packed_struct.ll
+++ b/test/CodeGen/X86/packed_struct.ll
@@ -17,9 +17,9 @@ target triple = "i686-pc-linux-gnu"
 
 define i32 @foo() nounwind {
 entry:
-	%tmp = load i32* getelementptr (%struct.anon* @foos, i32 0, i32 1)		; <i32> [#uses=1]
-	%tmp3 = load i32* getelementptr (%struct.anon* @foos, i32 0, i32 2)		; <i32> [#uses=1]
-	%tmp6 = load i32* getelementptr (%struct.anon* @foos, i32 0, i32 3)		; <i32> [#uses=1]
+	%tmp = load i32, i32* getelementptr (%struct.anon, %struct.anon* @foos, i32 0, i32 1)		; <i32> [#uses=1]
+	%tmp3 = load i32, i32* getelementptr (%struct.anon, %struct.anon* @foos, i32 0, i32 2)		; <i32> [#uses=1]
+	%tmp6 = load i32, i32* getelementptr (%struct.anon, %struct.anon* @foos, i32 0, i32 3)		; <i32> [#uses=1]
 	%tmp4 = add i32 %tmp3, %tmp		; <i32> [#uses=1]
 	%tmp7 = add i32 %tmp4, %tmp6		; <i32> [#uses=1]
 	ret i32 %tmp7
@@ -27,8 +27,8 @@ entry:
 
 define i8 @bar() nounwind {
 entry:
-	%tmp = load i8* getelementptr ([4 x <{ i32, i8 }>]* @bara, i32 0, i32 0, i32 1)		; <i8> [#uses=1]
-	%tmp4 = load i8* getelementptr ([4 x <{ i32, i8 }>]* @bara, i32 0, i32 3, i32 1)		; <i8> [#uses=1]
+	%tmp = load i8, i8* getelementptr ([4 x <{ i32, i8 }>], [4 x <{ i32, i8 }>]* @bara, i32 0, i32 0, i32 1)		; <i8> [#uses=1]
+	%tmp4 = load i8, i8* getelementptr ([4 x <{ i32, i8 }>], [4 x <{ i32, i8 }>]* @bara, i32 0, i32 3, i32 1)		; <i8> [#uses=1]
 	%tmp5 = add i8 %tmp4, %tmp		; <i8> [#uses=1]
 	ret i8 %tmp5
 }
diff --git a/test/CodeGen/X86/palignr-2.ll b/test/CodeGen/X86/palignr-2.ll
deleted file mode 100644
index 4df9a2284cb7..000000000000
--- a/test/CodeGen/X86/palignr-2.ll
+++ /dev/null
@@ -1,28 +0,0 @@
-; RUN: llc < %s -march=x86 -mattr=+ssse3 | FileCheck %s
-; rdar://7341330
-
-@a = global [4 x i32] [i32 4, i32 5, i32 6, i32 7], align 16 ; <[4 x i32]*> [#uses=1]
-@c = common global [4 x i32] zeroinitializer, align 16 ; <[4 x i32]*> [#uses=1]
-@b = global [4 x i32] [i32 0, i32 1, i32 2, i32 3], align 16 ; <[4 x i32]*> [#uses=1]
-
-define void @t1(<2 x i64> %a, <2 x i64> %b) nounwind ssp {
-entry:
-; CHECK-LABEL: t1:
-; palignr $3, %xmm1, %xmm0
-  %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i8 24) nounwind readnone
-  store <2 x i64> %0, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16
-  ret void
-}
-
-declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone
-
-define void @t2() nounwind ssp {
-entry:
-; CHECK-LABEL: t2:
-; palignr $4, _b, %xmm0
-  %0 = load <2 x i64>* bitcast ([4 x i32]* @b to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1]
-  %1 = load <2 x i64>* bitcast ([4 x i32]* @a to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1]
-  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) nounwind readnone
-  store <2 x i64> %2, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16
-  ret void
-}
diff --git a/test/CodeGen/X86/palignr.ll b/test/CodeGen/X86/palignr.ll
index 3efcc2e41215..dfa2cedf45a2 100644
--- a/test/CodeGen/X86/palignr.ll
+++ b/test/CodeGen/X86/palignr.ll
@@ -40,7 +40,9 @@ define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind {
 ;
 ; CHECK-YONAH-LABEL: test3:
 ; CHECK-YONAH:       # BB#0:
-; CHECK-YONAH-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,2],xmm1[2,0]
+; CHECK-YONAH-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
+; CHECK-YONAH-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,2,2,3]
+; CHECK-YONAH-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
 ; CHECK-YONAH-NEXT:    retl
   %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 undef, i32 4 >
 	ret <4 x i32> %C
diff --git a/test/CodeGen/X86/patchpoint-invoke.ll b/test/CodeGen/X86/patchpoint-invoke.ll
index 192cacc908ab..98e9eb3b6a44 100644
--- a/test/CodeGen/X86/patchpoint-invoke.ll
+++ b/test/CodeGen/X86/patchpoint-invoke.ll
@@ -5,8 +5,8 @@
 define i64 @patchpoint_invoke(i64 %p1, i64 %p2) {
 entry:
 ; CHECK-LABEL: patchpoint_invoke:
+; CHECK-NEXT:  [[FUNC_BEGIN:.L.*]]:
 ; CHECK-NEXT: .cfi_startproc
-; CHECK:      [[FUNC_BEGIN:.L.*]]:
 ; CHECK:      .cfi_lsda 3, [[EXCEPTION_LABEL:.L[^ ]*]]
 ; CHECK:      pushq %rbp
 
@@ -18,7 +18,7 @@ entry:
 ; CHECK-NEXT: [[PP_END:.L.*]]:
 ; CHECK:      ret
   %resolveCall = inttoptr i64 -559038736 to i8*
-  %result = invoke i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %resolveCall, i32 1, i64 %p1, i64 %p2)
+  %result = invoke i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %resolveCall, i32 1, i64 %p1, i64 %p2)
             to label %success unwind label %threw
 
 success:
diff --git a/test/CodeGen/X86/patchpoint-webkit_jscc.ll b/test/CodeGen/X86/patchpoint-webkit_jscc.ll
index 5e76bf8d4e60..5c39438b22d6 100644
--- a/test/CodeGen/X86/patchpoint-webkit_jscc.ll
+++ b/test/CodeGen/X86/patchpoint-webkit_jscc.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7                             < %s | FileCheck %s
-; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort < %s | FileCheck %s --check-prefix=FAST
+; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s --check-prefix=FAST
 
 ; Test the webkit_jscc calling convention.
 ; One argument will be passed in register, the other will be pushed on the stack.
@@ -25,9 +25,9 @@ entry:
 ; FAST:       movq %rax, (%rsp)
 ; FAST:       callq
   %resolveCall2 = inttoptr i64 -559038736 to i8*
-  %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2)
+  %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2)
   %resolveCall3 = inttoptr i64 -559038737 to i8*
-  tail call webkit_jscc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 6, i32 15, i8* %resolveCall3, i32 2, i64 %p4, i64 %result)
+  tail call webkit_jscc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 15, i8* %resolveCall3, i32 2, i64 %p4, i64 %result)
   ret void
 }
 
@@ -51,7 +51,7 @@ entry:
 ; FAST-NEXT:  movabsq $-559038736, %r11
 ; FAST-NEXT:  callq *%r11
   %call = inttoptr i64 -559038736 to i8*
-  %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 7, i32 15, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6)
+  %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 15, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6)
   ret i64 %result
 }
 
@@ -79,7 +79,7 @@ entry:
 ; FAST-NEXT:  movabsq $-559038736, %r11
 ; FAST-NEXT:  callq *%r11
   %call = inttoptr i64 -559038736 to i8*
-  %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 7, i32 15, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10)
+  %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 15, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10)
   ret i64 %result
 }
 
diff --git a/test/CodeGen/X86/patchpoint.ll b/test/CodeGen/X86/patchpoint.ll
index 07148f0329a2..82b15c36c2b2 100644
--- a/test/CodeGen/X86/patchpoint.ll
+++ b/test/CodeGen/X86/patchpoint.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7                             < %s | FileCheck %s
-; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
 
 ; Trivial patchpoint codegen
 ;
@@ -15,12 +15,28 @@ entry:
 ; CHECK:      movq %[[REG]], %rax
 ; CHECK:      ret
   %resolveCall2 = inttoptr i64 -559038736 to i8*
-  %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
+  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
   %resolveCall3 = inttoptr i64 -559038737 to i8*
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 3, i32 15, i8* %resolveCall3, i32 2, i64 %p1, i64 %result)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 15, i8* %resolveCall3, i32 2, i64 %p1, i64 %result)
   ret i64 %result
 }
 
+; Trivial symbolic patchpoint codegen.
+;
+
+declare i64 @foo(i64 %p1, i64 %p2)
+define i64 @trivial_symbolic_patchpoint_codegen(i64 %p1, i64 %p2) {
+entry:
+; CHECK-LABEL: trivial_symbolic_patchpoint_codegen:
+; CHECK:       movabsq $_foo, %r11
+; CHECK-NEXT:  callq   *%r11
+; CHECK-NEXT:  xchgw   %ax, %ax
+; CHECK:       retq
+  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 9, i32 15, i8* bitcast (i64 (i64, i64)* @foo to i8*), i32 2, i64 %p1, i64 %p2)
+  ret i64 %result
+}
+
+
 ; Caller frame metadata with stackmaps. This should not be optimized
 ; as a leaf function.
 ;
@@ -35,7 +51,7 @@ entry:
   store i64 11, i64* %metadata
   store i64 12, i64* %metadata
   store i64 13, i64* %metadata
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
   ret void
 }
 
@@ -47,15 +63,15 @@ define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, i64* %tmp33, i64
 entry:
   %tmp80 = add i64 %tmp79, -16
   %tmp81 = inttoptr i64 %tmp80 to i64*
-  %tmp82 = load i64* %tmp81, align 8
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 14, i32 5, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82)
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 15, i32 30, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
-  %tmp83 = load i64* %tmp33, align 8
+  %tmp82 = load i64, i64* %tmp81, align 8
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 5, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 15, i32 30, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
+  %tmp83 = load i64, i64* %tmp33, align 8
   %tmp84 = add i64 %tmp83, -24
   %tmp85 = inttoptr i64 %tmp84 to i64*
-  %tmp86 = load i64* %tmp85, align 8
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 17, i32 5, i64 %arg, i64 %tmp10, i64 %tmp86)
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 18, i32 30, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
+  %tmp86 = load i64, i64* %tmp85, align 8
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 17, i32 5, i64 %arg, i64 %tmp10, i64 %tmp86)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 18, i32 30, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
   ret i64 10
 }
 
@@ -67,7 +83,7 @@ entry:
 ; CHECK:      nopl 8(%rax,%rax)
 ; CHECK-NEXT: popq
 ; CHECK-NEXT: ret
-  %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 5, i8* null, i32 2, i64 %p1, i64 %p2)
+  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 5, i8* null, i32 2, i64 %p1, i64 %p2)
   ret void
 }
 
@@ -78,7 +94,7 @@ entry:
 ; CHECK:      movabsq $6153737369414576827, %r11
 ; CHECK-NEXT: callq *%r11
   %resolveCall2 = inttoptr i64 6153737369414576827 to i8*
-  %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %resolveCall2, i32 0)
+  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %resolveCall2, i32 0)
   ret i64 %result
 }
 
diff --git a/test/CodeGen/X86/peep-test-0.ll b/test/CodeGen/X86/peep-test-0.ll
index e521d8e37854..1772f008b94e 100644
--- a/test/CodeGen/X86/peep-test-0.ll
+++ b/test/CodeGen/X86/peep-test-0.ll
@@ -9,8 +9,8 @@ entry:
 bb:
 	%indvar = phi i64 [ %n, %entry ], [ %indvar.next, %bb ]
 	%i.03 = add i64 %indvar, %n
-	%0 = getelementptr double* %d, i64 %i.03
-	%1 = load double* %0, align 8
+	%0 = getelementptr double, double* %d, i64 %i.03
+	%1 = load double, double* %0, align 8
 	%2 = fmul double %1, 3.000000e+00
 	store double %2, double* %0, align 8
 	%indvar.next = add i64 %indvar, 1
diff --git a/test/CodeGen/X86/peep-test-1.ll b/test/CodeGen/X86/peep-test-1.ll
index f83f0f6aa6ff..7448da3894da 100644
--- a/test/CodeGen/X86/peep-test-1.ll
+++ b/test/CodeGen/X86/peep-test-1.ll
@@ -9,8 +9,8 @@ define void @foo(i32 %n, double* nocapture %p) nounwind {
 bb:
 	%indvar = phi i32 [ 0, %0 ], [ %indvar.next, %bb ]
 	%i.03 = sub i32 %n, %indvar
-	%1 = getelementptr double* %p, i32 %i.03
-	%2 = load double* %1, align 4
+	%1 = getelementptr double, double* %p, i32 %i.03
+	%2 = load double, double* %1, align 4
 	%3 = fmul double %2, 2.930000e+00
 	store double %3, double* %1, align 4
 	%4 = add i32 %i.03, -1
diff --git a/test/CodeGen/X86/peephole-fold-movsd.ll b/test/CodeGen/X86/peephole-fold-movsd.ll
index 09d9328815da..818040a6f02c 100644
--- a/test/CodeGen/X86/peephole-fold-movsd.ll
+++ b/test/CodeGen/X86/peephole-fold-movsd.ll
@@ -17,10 +17,10 @@ define void @foo1(double %a.coerce0, double %a.coerce1, double %b.coerce0, doubl
   %1 = alloca <2 x double>, align 16
   %tmpcast = bitcast <2 x double>* %1 to %struct.S1*
   call void @foo3(%struct.S1* %tmpcast) #2
-  %p2 = getelementptr inbounds %struct.S1* %tmpcast, i64 0, i32 0
-  %2 = load double* %p2, align 16
-  %p3 = getelementptr inbounds %struct.S1* %tmpcast, i64 0, i32 1
-  %3 = load double* %p3, align 8
+  %p2 = getelementptr inbounds %struct.S1, %struct.S1* %tmpcast, i64 0, i32 0
+  %2 = load double, double* %p2, align 16
+  %p3 = getelementptr inbounds %struct.S1, %struct.S1* %tmpcast, i64 0, i32 1
+  %3 = load double, double* %p3, align 8
   %4 = insertelement <2 x double> undef, double %2, i32 0
   %5 = insertelement <2 x double> %4, double 0.000000e+00, i32 1
   %6 = insertelement <2 x double> undef, double %3, i32 1
diff --git a/test/CodeGen/X86/peephole-multiple-folds.ll b/test/CodeGen/X86/peephole-multiple-folds.ll
index a6cec66c73c9..9fcc1a20798b 100644
--- a/test/CodeGen/X86/peephole-multiple-folds.ll
+++ b/test/CodeGen/X86/peephole-multiple-folds.ll
@@ -13,8 +13,8 @@ loopbody:
 ; CHECK: vfmadd231ps ({{%rsi|%rdx}}),
   %vsum1 = phi <8 x float> [ %vsum1.next, %loopbody ], [ zeroinitializer, %entry ]
   %vsum2 = phi <8 x float> [ %vsum2.next, %loopbody ], [ zeroinitializer, %entry ]
-  %m1 = load <8 x float>* %p1, align 1
-  %m2 = load <8 x float>* %p2, align 1
+  %m1 = load <8 x float>, <8 x float>* %p1, align 1
+  %m2 = load <8 x float>, <8 x float>* %p2, align 1
   %vsum1.next = tail call <8 x float> @llvm.x86.fma.vfmadd.ps.256(<8 x float> %m1, <8 x float> zeroinitializer, <8 x float> %vsum1)
   %vsum2.next = tail call <8 x float> @llvm.x86.fma.vfmadd.ps.256(<8 x float> %m2, <8 x float> zeroinitializer, <8 x float> %vsum2)
   %vsum1.next.1 = extractelement <8 x float> %vsum1.next, i32 0
diff --git a/test/CodeGen/X86/phi-bit-propagation.ll b/test/CodeGen/X86/phi-bit-propagation.ll
index 94c97229b092..37f3f096556f 100644
--- a/test/CodeGen/X86/phi-bit-propagation.ll
+++ b/test/CodeGen/X86/phi-bit-propagation.ll
@@ -14,11 +14,11 @@ for.cond:                                         ; preds = %for.inc, %entry
   br i1 %cmp, label %return, label %for.body
 
 for.body:                                         ; preds = %for.cond
-  %arrayidx = getelementptr inbounds i32* %b, i64 %conv
-  %tmp5 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %conv
+  %tmp5 = load i32, i32* %arrayidx, align 4
   %conv6 = zext i32 %tmp5 to i64
   %rem.i.i.i.i = and i64 %conv6, 63
-  %tmp3.i = load i64* %tmp.i.i.i.i, align 8
+  %tmp3.i = load i64, i64* %tmp.i.i.i.i, align 8
   %shl.i.i = shl i64 1, %rem.i.i.i.i
   %and.i = and i64 %shl.i.i, %tmp3.i
   %cmp.i = icmp eq i64 %and.i, 0
diff --git a/test/CodeGen/X86/phielim-split.ll b/test/CodeGen/X86/phielim-split.ll
index aa477359d60e..423ef0486ac7 100644
--- a/test/CodeGen/X86/phielim-split.ll
+++ b/test/CodeGen/X86/phielim-split.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -no-phi-elim-live-out-early-exit | FileCheck %s
 target triple = "x86_64-apple-macosx10.8.0"
 
 ; The critical edge from for.cond to if.end2 should be split to avoid injecting
@@ -18,8 +18,8 @@ entry:
 
 for.cond:                                         ; preds = %entry, %for.cond
   %p.addr.0 = phi i8* [ %incdec.ptr, %for.cond ], [ %p, %entry ]
-  %incdec.ptr = getelementptr inbounds i8* %p.addr.0, i64 1
-  %0 = load i8* %p.addr.0, align 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %p.addr.0, i64 1
+  %0 = load i8, i8* %p.addr.0, align 1
   %tobool = icmp eq i8 %0, 0
   br i1 %tobool, label %for.cond, label %if.end2
 
@@ -28,3 +28,40 @@ if.end2:                                          ; preds = %for.cond, %entry
   %add = add nsw i32 %r.0, %b
   ret i32 %add
 }
+
+; CHECK: split_live_out
+; CHECK: %while.body
+; CHECK: cmp
+; CHECK-NEXT: ja
+define i8* @split_live_out(i32 %value, i8* %target) nounwind uwtable readonly ssp {
+entry:
+  %cmp10 = icmp ugt i32 %value, 127
+  br i1 %cmp10, label %while.body.preheader, label %while.end
+
+while.body.preheader:                             ; preds = %entry
+  br label %while.body
+
+while.body:                                       ; preds = %while.body.preheader, %while.body
+  %target.addr.012 = phi i8* [ %incdec.ptr, %while.body ], [ %target, %while.body.preheader ]
+  %value.addr.011 = phi i32 [ %shr, %while.body ], [ %value, %while.body.preheader ]
+  %or = or i32 %value.addr.011, 128
+  %conv = trunc i32 %or to i8
+  store i8 %conv, i8* %target.addr.012, align 1
+  %shr = lshr i32 %value.addr.011, 7
+  %incdec.ptr = getelementptr inbounds i8, i8* %target.addr.012, i64 1
+  %cmp = icmp ugt i32 %value.addr.011, 16383
+  br i1 %cmp, label %while.body, label %while.end.loopexit
+
+while.end.loopexit:                               ; preds = %while.body
+  %incdec.ptr.lcssa = phi i8* [ %incdec.ptr, %while.body ]
+  %shr.lcssa = phi i32 [ %shr, %while.body ]
+  br label %while.end
+
+while.end:                                        ; preds = %while.end.loopexit, %entry
+  %target.addr.0.lcssa = phi i8* [ %target, %entry ], [ %incdec.ptr.lcssa, %while.end.loopexit ]
+  %value.addr.0.lcssa = phi i32 [ %value, %entry ], [ %shr.lcssa, %while.end.loopexit ]
+  %conv1 = trunc i32 %value.addr.0.lcssa to i8
+  store i8 %conv1, i8* %target.addr.0.lcssa, align 1
+  %incdec.ptr3 = getelementptr inbounds i8, i8* %target.addr.0.lcssa, i64 1
+  ret i8* %incdec.ptr3
+}
diff --git a/test/CodeGen/X86/phys-reg-local-regalloc.ll b/test/CodeGen/X86/phys-reg-local-regalloc.ll
index 37eca1ce0a72..a0adba0f8338 100644
--- a/test/CodeGen/X86/phys-reg-local-regalloc.ll
+++ b/test/CodeGen/X86/phys-reg-local-regalloc.ll
@@ -50,15 +50,15 @@ entry:
   store i32 %asmtmp2, i32* %"%eax"
   %3 = call i32 asm "", "={ax}"() nounwind        ; <i32> [#uses=1]
   call void asm sideeffect alignstack "movl $0, $1", "{eax},*m,~{dirflag},~{fpsr},~{flags},~{memory}"(i32 %3, i32* %result) nounwind
-  %4 = load i32* %result, align 4                 ; <i32> [#uses=1]
-  %5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), i32 %4) nounwind ; <i32> [#uses=0]
+  %4 = load i32, i32* %result, align 4                 ; <i32> [#uses=1]
+  %5 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), i32 %4) nounwind ; <i32> [#uses=0]
   store i32 0, i32* %0, align 4
-  %6 = load i32* %0, align 4                      ; <i32> [#uses=1]
+  %6 = load i32, i32* %0, align 4                      ; <i32> [#uses=1]
   store i32 %6, i32* %retval, align 4
   br label %return
 
 return:                                           ; preds = %entry
-  %retval3 = load i32* %retval                    ; <i32> [#uses=1]
+  %retval3 = load i32, i32* %retval                    ; <i32> [#uses=1]
   ret i32 %retval3
 }
 
diff --git a/test/CodeGen/X86/phys_subreg_coalesce-2.ll b/test/CodeGen/X86/phys_subreg_coalesce-2.ll
index 02c519fb3e47..8ee97ae07e65 100644
--- a/test/CodeGen/X86/phys_subreg_coalesce-2.ll
+++ b/test/CodeGen/X86/phys_subreg_coalesce-2.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -march=x86 | FileCheck %s
+; RUN: llc -no-phi-elim-live-out-early-exit -terminal-rule < %s -march=x86 | FileCheck %s
 ; PR2659
 
 define i32 @binomial(i32 %n, i32 %k) nounwind {
diff --git a/test/CodeGen/X86/phys_subreg_coalesce-3.ll b/test/CodeGen/X86/phys_subreg_coalesce-3.ll
index 12a3adfdfe98..74e3d1291c05 100644
--- a/test/CodeGen/X86/phys_subreg_coalesce-3.ll
+++ b/test/CodeGen/X86/phys_subreg_coalesce-3.ll
@@ -25,11 +25,11 @@ bb:                                               ; preds = %bb, %bb.nph
   %indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
   %j.06 = sub i32 %j.03, %indvar                  ; <i32> [#uses=1]
   %tmp11 = sub i32 %tmp10, %indvar                ; <i32> [#uses=1]
-  %scevgep = getelementptr i32* %ptr, i32 %tmp11  ; <i32*> [#uses=1]
-  %1 = load i32* %scevgep, align 4                ; <i32> [#uses=1]
+  %scevgep = getelementptr i32, i32* %ptr, i32 %tmp11  ; <i32*> [#uses=1]
+  %1 = load i32, i32* %scevgep, align 4                ; <i32> [#uses=1]
   %2 = ashr i32 %j.06, %shifts                    ; <i32> [#uses=1]
   %3 = and i32 %2, 65535                          ; <i32> [#uses=1]
-  %4 = getelementptr inbounds i32* %quadrant, i32 %1 ; <i32*> [#uses=1]
+  %4 = getelementptr inbounds i32, i32* %quadrant, i32 %1 ; <i32*> [#uses=1]
   store i32 %3, i32* %4, align 4
   %indvar.next = add i32 %indvar, 1               ; <i32> [#uses=2]
   %exitcond = icmp eq i32 %indvar.next, %bbSize   ; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/pic.ll b/test/CodeGen/X86/pic.ll
index da1e2248065f..d543deb804d1 100644
--- a/test/CodeGen/X86/pic.ll
+++ b/test/CodeGen/X86/pic.ll
@@ -7,7 +7,7 @@
 define void @test0() nounwind {
 entry:
     store i32* @dst, i32** @ptr
-    %tmp.s = load i32* @src
+    %tmp.s = load i32, i32* @src
     store i32 %tmp.s, i32* @dst
     ret void
     
@@ -29,7 +29,7 @@ entry:
 define void @test1() nounwind {
 entry:
     store i32* @dst2, i32** @ptr2
-    %tmp.s = load i32* @src2
+    %tmp.s = load i32, i32* @src2
     store i32 %tmp.s, i32* @dst2
     ret void
     
@@ -69,10 +69,10 @@ entry:
 
 define void @test3() nounwind {
 entry:
-    %tmp = call void(...)*(...)* @afoo()
+    %tmp = call void(...)*(...) @afoo()
     store void(...)* %tmp, void(...)** @pfoo
-    %tmp1 = load void(...)** @pfoo
-    call void(...)* %tmp1()
+    %tmp1 = load void(...)*, void(...)** @pfoo
+    call void(...) %tmp1()
     ret void
 ; LINUX-LABEL: test3:
 ; LINUX: 	calll	.L3$pb
@@ -88,7 +88,7 @@ declare void(...)* @afoo(...)
 
 define void @test4() nounwind {
 entry:
-    call void(...)* @foo()
+    call void(...) @foo()
     ret void
 ; LINUX-LABEL: test4:
 ; LINUX: calll	.L4$pb
@@ -107,7 +107,7 @@ declare void @foo(...)
 define void @test5() nounwind {
 entry:
     store i32* @dst6, i32** @ptr6
-    %tmp.s = load i32* @src6
+    %tmp.s = load i32, i32* @src6
     store i32 %tmp.s, i32* @dst6
     ret void
     
@@ -146,43 +146,43 @@ define void @test7(i32 %n.u) nounwind {
 entry:
     switch i32 %n.u, label %bb12 [i32 1, label %bb i32 2, label %bb6 i32 4, label %bb7 i32 5, label %bb8 i32 6, label %bb10 i32 7, label %bb1 i32 8, label %bb3 i32 9, label %bb4 i32 10, label %bb9 i32 11, label %bb2 i32 12, label %bb5 i32 13, label %bb11 ]
 bb:
-    tail call void(...)* @foo1()
+    tail call void(...) @foo1()
     ret void
 bb1:
-    tail call void(...)* @foo2()
+    tail call void(...) @foo2()
     ret void
 bb2:
-    tail call void(...)* @foo6()
+    tail call void(...) @foo6()
     ret void
 bb3:
-    tail call void(...)* @foo3()
+    tail call void(...) @foo3()
     ret void
 bb4:
-    tail call void(...)* @foo4()
+    tail call void(...) @foo4()
     ret void
 bb5:
-    tail call void(...)* @foo5()
+    tail call void(...) @foo5()
     ret void
 bb6:
-    tail call void(...)* @foo1()
+    tail call void(...) @foo1()
     ret void
 bb7:
-    tail call void(...)* @foo2()
+    tail call void(...) @foo2()
     ret void
 bb8:
-    tail call void(...)* @foo6()
+    tail call void(...) @foo6()
     ret void
 bb9:
-    tail call void(...)* @foo3()
+    tail call void(...) @foo3()
     ret void
 bb10:
-    tail call void(...)* @foo4()
+    tail call void(...) @foo4()
     ret void
 bb11:
-    tail call void(...)* @foo5()
+    tail call void(...) @foo5()
     ret void
 bb12:
-    tail call void(...)* @foo6()
+    tail call void(...) @foo6()
     ret void
     
 ; LINUX-LABEL: test7:
diff --git a/test/CodeGen/X86/pic_jumptable.ll b/test/CodeGen/X86/pic_jumptable.ll
index bdd885935842..8c1992a24ece 100644
--- a/test/CodeGen/X86/pic_jumptable.ll
+++ b/test/CodeGen/X86/pic_jumptable.ll
@@ -10,7 +10,7 @@
 
 declare void @_Z3bari(i32)
 
-; CHECK-LINUX: .text._Z3fooILi1EEvi,"axG",@progbits,_Z3fooILi1EEvi,comdat
+; CHECK-LINUX: _Z3fooILi1EEvi:
 define linkonce void @_Z3fooILi1EEvi(i32 %Y) nounwind {
 entry:
 ; CHECK:       L0$pb
@@ -31,7 +31,7 @@ entry:
 	%Y_addr = alloca i32		; <i32*> [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store i32 %Y, i32* %Y_addr
-	%tmp = load i32* %Y_addr		; <i32> [#uses=1]
+	%tmp = load i32, i32* %Y_addr		; <i32> [#uses=1]
 	switch i32 %tmp, label %bb10 [
 		 i32 0, label %bb3
 		 i32 1, label %bb
@@ -55,13 +55,15 @@ entry:
 	]
 
 bb:		; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry
+	call void @_Z3bari( i32 0 )
 	br label %bb1
 
 bb1:		; preds = %bb, %entry
+	call void @_Z3bari( i32 1 )
 	br label %bb2
 
 bb2:		; preds = %bb1, %entry
-	call void @_Z3bari( i32 1 )
+	call void @_Z3bari( i32 2 )
 	br label %bb11
 
 bb3:		; preds = %entry
diff --git a/test/CodeGen/X86/pmovext.ll b/test/CodeGen/X86/pmovext.ll
index f0e468f53cb3..6c76949fb78b 100644
--- a/test/CodeGen/X86/pmovext.ll
+++ b/test/CodeGen/X86/pmovext.ll
@@ -8,7 +8,7 @@
 ;CHECK-NEXT: ret
 define void @intrin_pmov(i16* noalias %dest, i8* noalias %src) nounwind uwtable ssp {
   %1 = bitcast i8* %src to <2 x i64>*
-  %2 = load <2 x i64>* %1, align 16
+  %2 = load <2 x i64>, <2 x i64>* %1, align 16
   %3 = bitcast <2 x i64> %2 to <16 x i8>
   %4 = tail call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %3) nounwind
   %5 = bitcast i16* %dest to i8*
diff --git a/test/CodeGen/X86/pmovsx-inreg.ll b/test/CodeGen/X86/pmovsx-inreg.ll
index 07979f61ddd8..2897d6bd814e 100644
--- a/test/CodeGen/X86/pmovsx-inreg.ll
+++ b/test/CodeGen/X86/pmovsx-inreg.ll
@@ -6,7 +6,7 @@
 ; These tests inject a store into the chain to test the inreg versions of pmovsx
 
 define void @test1(<2 x i8>* %in, <2 x i64>* %out) nounwind {
-  %wide.load35 = load <2 x i8>* %in, align 1
+  %wide.load35 = load <2 x i8>, <2 x i8>* %in, align 1
   %sext = sext <2 x i8> %wide.load35 to <2 x i64>
   store <2 x i64> zeroinitializer, <2 x i64>* undef, align 8
   store <2 x i64> %sext, <2 x i64>* %out, align 8
@@ -23,7 +23,7 @@ define void @test1(<2 x i8>* %in, <2 x i64>* %out) nounwind {
 }
 
 define void @test2(<4 x i8>* %in, <4 x i64>* %out) nounwind {
-  %wide.load35 = load <4 x i8>* %in, align 1
+  %wide.load35 = load <4 x i8>, <4 x i8>* %in, align 1
   %sext = sext <4 x i8> %wide.load35 to <4 x i64>
   store <4 x i64> zeroinitializer, <4 x i64>* undef, align 8
   store <4 x i64> %sext, <4 x i64>* %out, align 8
@@ -34,7 +34,7 @@ define void @test2(<4 x i8>* %in, <4 x i64>* %out) nounwind {
 }
 
 define void @test3(<4 x i8>* %in, <4 x i32>* %out) nounwind {
-  %wide.load35 = load <4 x i8>* %in, align 1
+  %wide.load35 = load <4 x i8>, <4 x i8>* %in, align 1
   %sext = sext <4 x i8> %wide.load35 to <4 x i32>
   store <4 x i32> zeroinitializer, <4 x i32>* undef, align 8
   store <4 x i32> %sext, <4 x i32>* %out, align 8
@@ -51,7 +51,7 @@ define void @test3(<4 x i8>* %in, <4 x i32>* %out) nounwind {
 }
 
 define void @test4(<8 x i8>* %in, <8 x i32>* %out) nounwind {
-  %wide.load35 = load <8 x i8>* %in, align 1
+  %wide.load35 = load <8 x i8>, <8 x i8>* %in, align 1
   %sext = sext <8 x i8> %wide.load35 to <8 x i32>
   store <8 x i32> zeroinitializer, <8 x i32>* undef, align 8
   store <8 x i32> %sext, <8 x i32>* %out, align 8
@@ -62,7 +62,7 @@ define void @test4(<8 x i8>* %in, <8 x i32>* %out) nounwind {
 }
 
 define void @test5(<8 x i8>* %in, <8 x i16>* %out) nounwind {
-  %wide.load35 = load <8 x i8>* %in, align 1
+  %wide.load35 = load <8 x i8>, <8 x i8>* %in, align 1
   %sext = sext <8 x i8> %wide.load35 to <8 x i16>
   store <8 x i16> zeroinitializer, <8 x i16>* undef, align 8
   store <8 x i16> %sext, <8 x i16>* %out, align 8
@@ -79,7 +79,7 @@ define void @test5(<8 x i8>* %in, <8 x i16>* %out) nounwind {
 }
 
 define void @test6(<16 x i8>* %in, <16 x i16>* %out) nounwind {
-  %wide.load35 = load <16 x i8>* %in, align 1
+  %wide.load35 = load <16 x i8>, <16 x i8>* %in, align 1
   %sext = sext <16 x i8> %wide.load35 to <16 x i16>
   store <16 x i16> zeroinitializer, <16 x i16>* undef, align 8
   store <16 x i16> %sext, <16 x i16>* %out, align 8
@@ -90,7 +90,7 @@ define void @test6(<16 x i8>* %in, <16 x i16>* %out) nounwind {
 }
 
 define void @test7(<2 x i16>* %in, <2 x i64>* %out) nounwind {
-  %wide.load35 = load <2 x i16>* %in, align 1
+  %wide.load35 = load <2 x i16>, <2 x i16>* %in, align 1
   %sext = sext <2 x i16> %wide.load35 to <2 x i64>
   store <2 x i64> zeroinitializer, <2 x i64>* undef, align 8
   store <2 x i64> %sext, <2 x i64>* %out, align 8
@@ -108,7 +108,7 @@ define void @test7(<2 x i16>* %in, <2 x i64>* %out) nounwind {
 }
 
 define void @test8(<4 x i16>* %in, <4 x i64>* %out) nounwind {
-  %wide.load35 = load <4 x i16>* %in, align 1
+  %wide.load35 = load <4 x i16>, <4 x i16>* %in, align 1
   %sext = sext <4 x i16> %wide.load35 to <4 x i64>
   store <4 x i64> zeroinitializer, <4 x i64>* undef, align 8
   store <4 x i64> %sext, <4 x i64>* %out, align 8
@@ -119,7 +119,7 @@ define void @test8(<4 x i16>* %in, <4 x i64>* %out) nounwind {
 }
 
 define void @test9(<4 x i16>* %in, <4 x i32>* %out) nounwind {
-  %wide.load35 = load <4 x i16>* %in, align 1
+  %wide.load35 = load <4 x i16>, <4 x i16>* %in, align 1
   %sext = sext <4 x i16> %wide.load35 to <4 x i32>
   store <4 x i32> zeroinitializer, <4 x i32>* undef, align 8
   store <4 x i32> %sext, <4 x i32>* %out, align 8
@@ -136,7 +136,7 @@ define void @test9(<4 x i16>* %in, <4 x i32>* %out) nounwind {
 }
 
 define void @test10(<8 x i16>* %in, <8 x i32>* %out) nounwind {
-  %wide.load35 = load <8 x i16>* %in, align 1
+  %wide.load35 = load <8 x i16>, <8 x i16>* %in, align 1
   %sext = sext <8 x i16> %wide.load35 to <8 x i32>
   store <8 x i32> zeroinitializer, <8 x i32>* undef, align 8
   store <8 x i32> %sext, <8 x i32>* %out, align 8
@@ -147,7 +147,7 @@ define void @test10(<8 x i16>* %in, <8 x i32>* %out) nounwind {
 }
 
 define void @test11(<2 x i32>* %in, <2 x i64>* %out) nounwind {
-  %wide.load35 = load <2 x i32>* %in, align 1
+  %wide.load35 = load <2 x i32>, <2 x i32>* %in, align 1
   %sext = sext <2 x i32> %wide.load35 to <2 x i64>
   store <2 x i64> zeroinitializer, <2 x i64>* undef, align 8
   store <2 x i64> %sext, <2 x i64>* %out, align 8
@@ -164,7 +164,7 @@ define void @test11(<2 x i32>* %in, <2 x i64>* %out) nounwind {
 }
 
 define void @test12(<4 x i32>* %in, <4 x i64>* %out) nounwind {
-  %wide.load35 = load <4 x i32>* %in, align 1
+  %wide.load35 = load <4 x i32>, <4 x i32>* %in, align 1
   %sext = sext <4 x i32> %wide.load35 to <4 x i64>
   store <4 x i64> zeroinitializer, <4 x i64>* undef, align 8
   store <4 x i64> %sext, <4 x i64>* %out, align 8
diff --git a/test/CodeGen/X86/pmul.ll b/test/CodeGen/X86/pmul.ll
index 8937d6afa0ae..21463b8539dc 100644
--- a/test/CodeGen/X86/pmul.ll
+++ b/test/CodeGen/X86/pmul.ll
@@ -1,18 +1,68 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE41
 
+define <16 x i8> @mul8c(<16 x i8> %i) nounwind  {
+; SSE2-LABEL: mul8c:
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    movdqa {{.*#+}} xmm1 = [117,117,117,117,117,117,117,117,117,117,117,117,117,117,117,117]
+; SSE2-NEXT:    psraw $8, %xmm1
+; SSE2-NEXT:    movdqa %xmm0, %xmm2
+; SSE2-NEXT:    punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
+; SSE2-NEXT:    psraw $8, %xmm2
+; SSE2-NEXT:    pmullw %xmm1, %xmm2
+; SSE2-NEXT:    movdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
+; SSE2-NEXT:    pand %xmm3, %xmm2
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-NEXT:    psraw $8, %xmm0
+; SSE2-NEXT:    pmullw %xmm1, %xmm0
+; SSE2-NEXT:    pand %xmm3, %xmm0
+; SSE2-NEXT:    packuswb %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE41-LABEL: mul8c:
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    pmovsxbw %xmm0, %xmm1
+; SSE41-NEXT:    pmovsxbw {{.*}}(%rip), %xmm2
+; SSE41-NEXT:    pmullw %xmm2, %xmm1
+; SSE41-NEXT:    movdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
+; SSE41-NEXT:    pand %xmm3, %xmm1
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; SSE41-NEXT:    pmovsxbw %xmm0, %xmm0
+; SSE41-NEXT:    pmullw %xmm2, %xmm0
+; SSE41-NEXT:    pand %xmm3, %xmm0
+; SSE41-NEXT:    packuswb %xmm0, %xmm1
+; SSE41-NEXT:    movdqa %xmm1, %xmm0
+; SSE41-NEXT:    retq
+entry:
+  %A = mul <16 x i8> %i, < i8 117, i8 117, i8 117, i8 117, i8 117, i8 117, i8 117, i8 117, i8 117, i8 117, i8 117, i8 117, i8 117, i8 117, i8 117, i8 117 >
+  ret <16 x i8> %A
+}
+
+define <8 x i16> @mul16c(<8 x i16> %i) nounwind  {
+; ALL-LABEL: mul16c:
+; ALL:       # BB#0: # %entry
+; ALL-NEXT:    pmullw {{.*}}(%rip), %xmm0
+; ALL-NEXT:    retq
+entry:
+  %A = mul <8 x i16> %i, < i16 117, i16 117, i16 117, i16 117, i16 117, i16 117, i16 117, i16 117 >
+  ret <8 x i16> %A
+}
+
 define <4 x i32> @a(<4 x i32> %i) nounwind  {
 ; SSE2-LABEL: a:
-; SSE2:         movdqa {{.*}}, %[[X1:xmm[0-9]+]]
-; SSE2-NEXT:    pshufd {{.*}} # [[X2:xmm[0-9]+]] = xmm0[1,1,3,3]
-; SSE2-NEXT:    pmuludq %[[X1]], %xmm0
-; SSE2-NEXT:    pmuludq %[[X1]], %[[X2]]
-; SSE2-NEXT:    shufps {{.*}} # xmm0 = xmm0[0,2],[[X2]][0,2]
-; SSE2-NEXT:    shufps {{.*}} # xmm0 = xmm0[0,2,1,3]
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    movdqa {{.*#+}} xmm1 = [117,117,117,117]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; SSE2-NEXT:    pmuludq %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    pmuludq %xmm1, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSE41-LABEL: a:
-; SSE41:         pmulld
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    pmulld {{.*}}(%rip), %xmm0
 ; SSE41-NEXT:    retq
 entry:
   %A = mul <4 x i32> %i, < i32 117, i32 117, i32 117, i32 117 >
@@ -21,26 +71,91 @@ entry:
 
 define <2 x i64> @b(<2 x i64> %i) nounwind  {
 ; ALL-LABEL: b:
-; ALL:         pmuludq
-; ALL:         pmuludq
-; ALL:         pmuludq
+; ALL:       # BB#0: # %entry
+; ALL-NEXT:    movdqa {{.*#+}} xmm1 = [117,117]
+; ALL-NEXT:    movdqa %xmm0, %xmm2
+; ALL-NEXT:    pmuludq %xmm1, %xmm2
+; ALL-NEXT:    pxor %xmm3, %xmm3
+; ALL-NEXT:    pmuludq %xmm0, %xmm3
+; ALL-NEXT:    psllq $32, %xmm3
+; ALL-NEXT:    paddq %xmm3, %xmm2
+; ALL-NEXT:    psrlq $32, %xmm0
+; ALL-NEXT:    pmuludq %xmm1, %xmm0
+; ALL-NEXT:    psllq $32, %xmm0
+; ALL-NEXT:    paddq %xmm2, %xmm0
+; ALL-NEXT:    retq
 entry:
   %A = mul <2 x i64> %i, < i64 117, i64 117 >
   ret <2 x i64> %A
 }
 
+define <16 x i8> @mul8(<16 x i8> %i, <16 x i8> %j) nounwind  {
+; SSE2-LABEL: mul8:
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    movdqa %xmm1, %xmm2
+; SSE2-NEXT:    punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
+; SSE2-NEXT:    psraw $8, %xmm2
+; SSE2-NEXT:    movdqa %xmm0, %xmm3
+; SSE2-NEXT:    punpckhbw {{.*#+}} xmm3 = xmm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
+; SSE2-NEXT:    psraw $8, %xmm3
+; SSE2-NEXT:    pmullw %xmm2, %xmm3
+; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
+; SSE2-NEXT:    pand %xmm2, %xmm3
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-NEXT:    psraw $8, %xmm1
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-NEXT:    psraw $8, %xmm0
+; SSE2-NEXT:    pmullw %xmm1, %xmm0
+; SSE2-NEXT:    pand %xmm2, %xmm0
+; SSE2-NEXT:    packuswb %xmm3, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE41-LABEL: mul8:
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    pmovsxbw %xmm1, %xmm3
+; SSE41-NEXT:    pmovsxbw %xmm0, %xmm2
+; SSE41-NEXT:    pmullw %xmm3, %xmm2
+; SSE41-NEXT:    movdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
+; SSE41-NEXT:    pand %xmm3, %xmm2
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; SSE41-NEXT:    pmovsxbw %xmm1, %xmm1
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; SSE41-NEXT:    pmovsxbw %xmm0, %xmm0
+; SSE41-NEXT:    pmullw %xmm1, %xmm0
+; SSE41-NEXT:    pand %xmm3, %xmm0
+; SSE41-NEXT:    packuswb %xmm0, %xmm2
+; SSE41-NEXT:    movdqa %xmm2, %xmm0
+; SSE41-NEXT:    retq
+entry:
+  %A = mul <16 x i8> %i, %j
+  ret <16 x i8> %A
+}
+
+define <8 x i16> @mul16(<8 x i16> %i, <8 x i16> %j) nounwind  {
+; ALL-LABEL: mul16:
+; ALL:       # BB#0: # %entry
+; ALL-NEXT:    pmullw %xmm1, %xmm0
+; ALL-NEXT:    retq
+entry:
+  %A = mul <8 x i16> %i, %j
+  ret <8 x i16> %A
+}
+
 define <4 x i32> @c(<4 x i32> %i, <4 x i32> %j) nounwind  {
 ; SSE2-LABEL: c:
-; SSE2:         pshufd {{.*}} # [[X2:xmm[0-9]+]] = xmm0[1,1,3,3]
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
 ; SSE2-NEXT:    pmuludq %xmm1, %xmm0
-; SSE2-NEXT:    pshufd {{.*}} # xmm1 = xmm1[1,1,3,3]
-; SSE2-NEXT:    pmuludq %[[X2]], %xmm1
-; SSE2-NEXT:    shufps {{.*}} # xmm0 = xmm0[0,2],xmm1[0,2]
-; SSE2-NEXT:    shufps {{.*}} # xmm0 = xmm0[0,2,1,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; SSE2-NEXT:    pmuludq %xmm2, %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSE41-LABEL: c:
-; SSE41:         pmulld
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    pmulld %xmm1, %xmm0
 ; SSE41-NEXT:    retq
 entry:
   %A = mul <4 x i32> %i, %j
@@ -49,9 +164,19 @@ entry:
 
 define <2 x i64> @d(<2 x i64> %i, <2 x i64> %j) nounwind  {
 ; ALL-LABEL: d:
-; ALL:         pmuludq
-; ALL:         pmuludq
-; ALL:         pmuludq
+; ALL:       # BB#0: # %entry
+; ALL-NEXT:    movdqa %xmm0, %xmm2
+; ALL-NEXT:    pmuludq %xmm1, %xmm2
+; ALL-NEXT:    movdqa %xmm1, %xmm3
+; ALL-NEXT:    psrlq $32, %xmm3
+; ALL-NEXT:    pmuludq %xmm0, %xmm3
+; ALL-NEXT:    psllq $32, %xmm3
+; ALL-NEXT:    paddq %xmm3, %xmm2
+; ALL-NEXT:    psrlq $32, %xmm0
+; ALL-NEXT:    pmuludq %xmm1, %xmm0
+; ALL-NEXT:    psllq $32, %xmm0
+; ALL-NEXT:    paddq %xmm2, %xmm0
+; ALL-NEXT:    retq
 entry:
   %A = mul <2 x i64> %i, %j
   ret <2 x i64> %A
@@ -61,20 +186,32 @@ declare void @foo()
 
 define <4 x i32> @e(<4 x i32> %i, <4 x i32> %j) nounwind  {
 ; SSE2-LABEL: e:
-; SSE2:         movdqa {{[0-9]*}}(%rsp), %xmm0
-; SSE2-NEXT:    pshufd {{.*}} # [[X1:xmm[0-9]+]] = xmm0[1,1,3,3]
-; SSE2-NEXT:    movdqa {{[0-9]*}}(%rsp), %[[X2:xmm[0-9]+]]
-; SSE2-NEXT:    pmuludq %[[X2]], %xmm0
-; SSE2-NEXT:    pshufd {{.*}} # [[X2]] = [[X2]][1,1,3,3]
-; SSE2-NEXT:    pmuludq %[[X1]], %[[X2]]
-; SSE2-NEXT:    shufps {{.*}} # xmm0 = xmm0[0,2],[[X2]][0,2]
-; SSE2-NEXT:    shufps {{.*}} # xmm0 = xmm0[0,2,1,3]
-; SSE2-NEXT:    addq ${{[0-9]+}}, %rsp
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    subq $40, %rsp
+; SSE2-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp) # 16-byte Spill
+; SSE2-NEXT:    movaps %xmm0, (%rsp) # 16-byte Spill
+; SSE2-NEXT:    callq foo
+; SSE2-NEXT:    movdqa (%rsp), %xmm0 # 16-byte Reload
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm2 # 16-byte Reload
+; SSE2-NEXT:    pmuludq %xmm2, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; SSE2-NEXT:    pmuludq %xmm1, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT:    addq $40, %rsp
 ; SSE2-NEXT:    retq
 ;
 ; SSE41-LABEL: e:
-; SSE41:         pmulld {{[0-9]+}}(%rsp), %xmm
-; SSE41-NEXT:    addq ${{[0-9]+}}, %rsp
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    subq $40, %rsp
+; SSE41-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp) # 16-byte Spill
+; SSE41-NEXT:    movaps %xmm0, (%rsp) # 16-byte Spill
+; SSE41-NEXT:    callq foo
+; SSE41-NEXT:    movdqa (%rsp), %xmm0 # 16-byte Reload
+; SSE41-NEXT:    pmulld {{[0-9]+}}(%rsp), %xmm0 # 16-byte Folded Reload
+; SSE41-NEXT:    addq $40, %rsp
 ; SSE41-NEXT:    retq
 entry:
   ; Use a call to force spills.
@@ -85,9 +222,26 @@ entry:
 
 define <2 x i64> @f(<2 x i64> %i, <2 x i64> %j) nounwind  {
 ; ALL-LABEL: f:
-; ALL:         pmuludq
-; ALL:         pmuludq
-; ALL:         pmuludq
+; ALL:       # BB#0: # %entry
+; ALL-NEXT:    subq $40, %rsp
+; ALL-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp) # 16-byte Spill
+; ALL-NEXT:    movaps %xmm0, (%rsp) # 16-byte Spill
+; ALL-NEXT:    callq foo
+; ALL-NEXT:    movdqa (%rsp), %xmm0 # 16-byte Reload
+; ALL-NEXT:    movdqa %xmm0, %xmm2
+; ALL-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm3 # 16-byte Reload
+; ALL-NEXT:    pmuludq %xmm3, %xmm2
+; ALL-NEXT:    movdqa %xmm3, %xmm1
+; ALL-NEXT:    psrlq $32, %xmm1
+; ALL-NEXT:    pmuludq %xmm0, %xmm1
+; ALL-NEXT:    psllq $32, %xmm1
+; ALL-NEXT:    paddq %xmm1, %xmm2
+; ALL-NEXT:    psrlq $32, %xmm0
+; ALL-NEXT:    pmuludq %xmm3, %xmm0
+; ALL-NEXT:    psllq $32, %xmm0
+; ALL-NEXT:    paddq %xmm2, %xmm0
+; ALL-NEXT:    addq $40, %rsp
+; ALL-NEXT:    retq
 entry:
   ; Use a call to force spills.
   call void @foo()
diff --git a/test/CodeGen/X86/pmulld.ll b/test/CodeGen/X86/pmulld.ll
index 3db0f73954d7..3fe3ebc9763c 100644
--- a/test/CodeGen/X86/pmulld.ll
+++ b/test/CodeGen/X86/pmulld.ll
@@ -20,7 +20,7 @@ define <4 x i32> @test1a(<4 x i32> %A, <4 x i32> *%Bp) nounwind {
 ; WIN64-NEXT: movdqa  (%rcx), %xmm0
 ; WIN64-NEXT: pmulld  (%rdx), %xmm0
 
-  %B = load <4 x i32>* %Bp
+  %B = load <4 x i32>, <4 x i32>* %Bp
   %C = mul <4 x i32> %A, %B
   ret <4 x i32> %C
 }
diff --git a/test/CodeGen/X86/pointer-vector.ll b/test/CodeGen/X86/pointer-vector.ll
index 0ee99875264f..48c8b2376bd5 100644
--- a/test/CodeGen/X86/pointer-vector.ll
+++ b/test/CodeGen/X86/pointer-vector.ll
@@ -31,7 +31,7 @@ entry:
 ;CHECK: LOAD0
 define <4 x i8*> @LOAD0(<4 x i8*>* %p) nounwind {
 entry:
-  %G = load <4 x i8*>* %p
+  %G = load <4 x i8*>, <4 x i8*>* %p
 ;CHECK: movaps
   ret <4 x i8*> %G
 ;CHECK: ret
@@ -40,7 +40,7 @@ entry:
 ;CHECK: LOAD1
 define <4 x i8*> @LOAD1(<4 x i8*>* %p) nounwind {
 entry:
-  %G = load <4 x i8*>* %p
+  %G = load <4 x i8*>, <4 x i8*>* %p
 ;CHECK: movdqa
 ;CHECK: pshufd
 ;CHECK: movdqa
@@ -55,11 +55,11 @@ define <4 x i8*> @LOAD2(<4 x i8*>* %p) nounwind {
 entry:
   %I = alloca <4 x i8*>
 ;CHECK: sub
-  %G = load <4 x i8*>* %p
+  %G = load <4 x i8*>, <4 x i8*>* %p
 ;CHECK: movaps
   store <4 x i8*> %G, <4 x i8*>* %I
 ;CHECK: movaps
-  %Z = load <4 x i8*>* %I
+  %Z = load <4 x i8*>, <4 x i8*>* %I
   ret <4 x i8*> %Z
 ;CHECK: add
 ;CHECK: ret
@@ -68,7 +68,7 @@ entry:
 ;CHECK: INT2PTR0
 define <4 x i32> @INT2PTR0(<4 x i8*>* %p) nounwind {
 entry:
-  %G = load <4 x i8*>* %p
+  %G = load <4 x i8*>, <4 x i8*>* %p
 ;CHECK: movl
 ;CHECK: movaps
   %K = ptrtoint <4 x i8*> %G to <4 x i32>
@@ -79,10 +79,9 @@ entry:
 ;CHECK: INT2PTR1
 define <4 x i32*> @INT2PTR1(<4 x i8>* %p) nounwind {
 entry:
-  %G = load <4 x i8>* %p
+  %G = load <4 x i8>, <4 x i8>* %p
 ;CHECK: movl
-;CHECK: pmovzxbd
-;CHECK: pand
+;CHECK: pmovzxbd (%
   %K = inttoptr <4 x i8> %G to <4 x i32*>
 ;CHECK: ret
   ret <4 x i32*> %K
@@ -91,7 +90,7 @@ entry:
 ;CHECK: BITCAST0
 define <4 x i32*> @BITCAST0(<4 x i8*>* %p) nounwind {
 entry:
-  %G = load <4 x i8*>* %p
+  %G = load <4 x i8*>, <4 x i8*>* %p
 ;CHECK: movl
   %T = bitcast <4 x i8*> %G to <4 x i32*>
 ;CHECK: movaps
@@ -102,7 +101,7 @@ entry:
 ;CHECK: BITCAST1
 define <2 x i32*> @BITCAST1(<2 x i8*>* %p) nounwind {
 entry:
-  %G = load <2 x i8*>* %p
+  %G = load <2 x i8*>, <2 x i8*>* %p
 ;CHECK: movl
 ;CHECK: pmovzxdq
   %T = bitcast <2 x i8*> %G to <2 x i32*>
@@ -113,8 +112,8 @@ entry:
 ;CHECK: ICMP0
 define <4 x i32> @ICMP0(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
 entry:
-  %g0 = load <4 x i8*>* %p0
-  %g1 = load <4 x i8*>* %p1
+  %g0 = load <4 x i8*>, <4 x i8*>* %p0
+  %g1 = load <4 x i8*>, <4 x i8*>* %p1
   %k = icmp sgt <4 x i8*> %g0, %g1
   ;CHECK: pcmpgtd
   %j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6>
@@ -125,8 +124,8 @@ entry:
 ;CHECK: ICMP1
 define <4 x i32> @ICMP1(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
 entry:
-  %g0 = load <4 x i8*>* %p0
-  %g1 = load <4 x i8*>* %p1
+  %g0 = load <4 x i8*>, <4 x i8*>* %p0
+  %g1 = load <4 x i8*>, <4 x i8*>* %p1
   %k = icmp eq <4 x i8*> %g0, %g1
   ;CHECK: pcmpeqd
   %j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6>
diff --git a/test/CodeGen/X86/postra-licm.ll b/test/CodeGen/X86/postra-licm.ll
index 946b8362122d..5c93160125e7 100644
--- a/test/CodeGen/X86/postra-licm.ll
+++ b/test/CodeGen/X86/postra-licm.ll
@@ -30,7 +30,7 @@ bb.i:                                             ; preds = %bb3
   unreachable
 
 bb.nph41:                                         ; preds = %bb3
-  %0 = call %struct.FILE* @"\01_fopen$UNIX2003"(i8* undef, i8* getelementptr inbounds ([2 x i8]* @.str12, i32 0, i32 0)) nounwind ; <%struct.FILE*> [#uses=3]
+  %0 = call %struct.FILE* @"\01_fopen$UNIX2003"(i8* undef, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str12, i32 0, i32 0)) nounwind ; <%struct.FILE*> [#uses=3]
   br i1 undef, label %bb4, label %bb5.preheader
 
 bb5.preheader:                                    ; preds = %bb.nph41
@@ -85,7 +85,7 @@ bb28:                                             ; preds = %bb28, %bb26.prehead
   br label %bb28
 
 bb30:                                             ; preds = %bb26.preheader
-  %5 = call i32 @strcmp(i8* undef, i8* getelementptr inbounds ([7 x i8]* @.str19, i32 0, i32 0)) nounwind readonly ; <i32> [#uses=0]
+  %5 = call i32 @strcmp(i8* undef, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str19, i32 0, i32 0)) nounwind readonly ; <i32> [#uses=0]
   br i1 undef, label %bb34, label %bb70
 
 bb32.loopexit:                                    ; preds = %bb45
@@ -101,19 +101,19 @@ bb35:                                             ; preds = %bb34
   unreachable
 
 bb39.preheader:                                   ; preds = %bb34
-  %7 = getelementptr inbounds %struct.epoch_t* undef, i32 %indvar54, i32 3 ; <i32*> [#uses=1]
-  %8 = getelementptr inbounds %struct.epoch_t* undef, i32 %indvar54, i32 2 ; <i32*> [#uses=0]
+  %7 = getelementptr inbounds %struct.epoch_t, %struct.epoch_t* undef, i32 %indvar54, i32 3 ; <i32*> [#uses=1]
+  %8 = getelementptr inbounds %struct.epoch_t, %struct.epoch_t* undef, i32 %indvar54, i32 2 ; <i32*> [#uses=0]
   br i1 false, label %bb42, label %bb45
 
 bb42:                                             ; preds = %bb39.preheader
   unreachable
 
 bb45:                                             ; preds = %bb39.preheader
-  %9 = call i32 @strcmp(i8* undef, i8* getelementptr inbounds ([4 x i8]* @.str24, i32 0, i32 0)) nounwind readonly ; <i32> [#uses=0]
+  %9 = call i32 @strcmp(i8* undef, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str24, i32 0, i32 0)) nounwind readonly ; <i32> [#uses=0]
   br i1 false, label %bb47, label %bb32.loopexit
 
 bb47:                                             ; preds = %bb45
-  %10 = load i32* %7, align 4                     ; <i32> [#uses=0]
+  %10 = load i32, i32* %7, align 4                     ; <i32> [#uses=0]
   unreachable
 
 bb70:                                             ; preds = %bb32.loopexit, %bb30
@@ -162,19 +162,19 @@ bb.nph:                                           ; preds = %entry
 bb:                                               ; preds = %bb, %bb.nph
   %tmp9 = mul i64 undef, undef                    ; <i64> [#uses=2]
   %tmp12 = add i64 %tmp11, %tmp9                  ; <i64> [#uses=1]
-  %scevgep13 = getelementptr i8* %bufp, i64 %tmp12 ; <i8*> [#uses=1]
+  %scevgep13 = getelementptr i8, i8* %bufp, i64 %tmp12 ; <i8*> [#uses=1]
   %tmp15 = add i64 %tmp14, %tmp9                  ; <i64> [#uses=1]
-  %scevgep16 = getelementptr i8* %bufp, i64 %tmp15 ; <i8*> [#uses=1]
-  %0 = load i8* undef, align 1                    ; <i8> [#uses=1]
+  %scevgep16 = getelementptr i8, i8* %bufp, i64 %tmp15 ; <i8*> [#uses=1]
+  %0 = load i8, i8* undef, align 1                    ; <i8> [#uses=1]
   %1 = zext i8 %0 to i32                          ; <i32> [#uses=1]
-  %2 = getelementptr inbounds [16 x i16]* @map_4_to_16, i64 0, i64 0 ; <i16*> [#uses=1]
-  %3 = load i16* %2, align 2                      ; <i16> [#uses=1]
+  %2 = getelementptr inbounds [16 x i16], [16 x i16]* @map_4_to_16, i64 0, i64 0 ; <i16*> [#uses=1]
+  %3 = load i16, i16* %2, align 2                      ; <i16> [#uses=1]
   %4 = trunc i16 %3 to i8                         ; <i8> [#uses=1]
   store i8 %4, i8* undef, align 1
   %5 = and i32 %1, 15                             ; <i32> [#uses=1]
   %6 = zext i32 %5 to i64                         ; <i64> [#uses=1]
-  %7 = getelementptr inbounds [16 x i16]* @map_4_to_16, i64 0, i64 %6 ; <i16*> [#uses=1]
-  %8 = load i16* %7, align 2                      ; <i16> [#uses=2]
+  %7 = getelementptr inbounds [16 x i16], [16 x i16]* @map_4_to_16, i64 0, i64 %6 ; <i16*> [#uses=1]
+  %8 = load i16, i16* %7, align 2                      ; <i16> [#uses=2]
   %9 = lshr i16 %8, 8                             ; <i16> [#uses=1]
   %10 = trunc i16 %9 to i8                        ; <i8> [#uses=1]
   store i8 %10, i8* %scevgep13, align 1
diff --git a/test/CodeGen/X86/pr10475.ll b/test/CodeGen/X86/pr10475.ll
index 3efc39ee9f1f..d81fce8bc4f2 100644
--- a/test/CodeGen/X86/pr10475.ll
+++ b/test/CodeGen/X86/pr10475.ll
@@ -10,7 +10,7 @@ CF79:                                             ; preds = %CF79, %BB
   br i1 undef, label %CF79, label %CF84.critedge.critedge
 
 CF84.critedge.critedge:                           ; preds = %CF79
-  %L35 = load <8 x i32>* undef
+  %L35 = load <8 x i32>, <8 x i32>* undef
   br label %CF85
 
 CF85:                                             ; preds = %CF85, %CF84.critedge.critedge
diff --git a/test/CodeGen/X86/pr10525.ll b/test/CodeGen/X86/pr10525.ll
index 30ce2979e8e1..436d89caabe0 100644
--- a/test/CodeGen/X86/pr10525.ll
+++ b/test/CodeGen/X86/pr10525.ll
@@ -4,7 +4,7 @@
 
 define void @autogen_163411_5000() {
 BB:
-  %L = load <2 x i64>* undef
+  %L = load <2 x i64>, <2 x i64>* undef
   %Shuff11 = shufflevector <2 x i64> %L, <2 x i64> %L, <2 x i32> <i32 2, i32 0>
   %I51 = insertelement <2 x i64> undef, i64 undef, i32 0
   %Shuff152 = shufflevector <2 x i64> %I51, <2 x i64> %Shuff11, <2 x i32> <i32 1, i32 3>
diff --git a/test/CodeGen/X86/pr11334.ll b/test/CodeGen/X86/pr11334.ll
index 0bdb0ec7cf44..6da4697c3b21 100644
--- a/test/CodeGen/X86/pr11334.ll
+++ b/test/CodeGen/X86/pr11334.ll
@@ -57,7 +57,7 @@ entry:
 
 define void @test_vector_creation() nounwind {
   %1 = insertelement <4 x double> undef, double 0.000000e+00, i32 2
-  %2 = load double addrspace(1)* null
+  %2 = load double, double addrspace(1)* null
   %3 = insertelement <4 x double> %1, double %2, i32 3
   store <4 x double> %3, <4 x double>* undef
   ret void
diff --git a/test/CodeGen/X86/pr12360.ll b/test/CodeGen/X86/pr12360.ll
index 673403624589..3e762da545d2 100644
--- a/test/CodeGen/X86/pr12360.ll
+++ b/test/CodeGen/X86/pr12360.ll
@@ -6,7 +6,7 @@ define zeroext i1 @f1(i8* %x) {
 ; CHECK-NEXT: ret
 
 entry:
-  %0 = load i8* %x, align 1, !range !0
+  %0 = load i8, i8* %x, align 1, !range !0
   %tobool = trunc i8 %0 to i1
   ret i1 %tobool
 }
@@ -17,7 +17,7 @@ define zeroext i1 @f2(i8* %x) {
 ; CHECK-NEXT: ret
 
 entry:
-  %0 = load i8* %x, align 1, !range !0
+  %0 = load i8, i8* %x, align 1, !range !0
   %tobool = icmp ne i8 %0, 0
   ret i1 %tobool
 }
diff --git a/test/CodeGen/X86/pr12889.ll b/test/CodeGen/X86/pr12889.ll
index 428e9b760b70..8234fcc67e08 100644
--- a/test/CodeGen/X86/pr12889.ll
+++ b/test/CodeGen/X86/pr12889.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define void @func() nounwind uwtable {
 entry:
-  %0 = load i8* @c0, align 1
+  %0 = load i8, i8* @c0, align 1
   %tobool = icmp ne i8 %0, 0
   %conv = zext i1 %tobool to i8
   %storemerge = shl nuw nsw i8 %conv, %conv
diff --git a/test/CodeGen/X86/pr13209.ll b/test/CodeGen/X86/pr13209.ll
index 8e5eca2b2c21..0d5196fc7c8a 100644
--- a/test/CodeGen/X86/pr13209.ll
+++ b/test/CodeGen/X86/pr13209.ll
@@ -11,37 +11,37 @@ indirectgoto.preheader:
   %frombool.i5915.ph = phi i8 [ undef, %if.end51 ], [ %frombool.i5917, %jit_return ]
   br label %indirectgoto
 do.end165:
-  %tmp92 = load i8** %x, align 8
+  %tmp92 = load i8*, i8** %x, align 8
   br label %indirectgoto
 do.end209:
-  %tmp104 = load i8** %x, align 8
+  %tmp104 = load i8*, i8** %x, align 8
   br label %indirectgoto
 do.end220:
-  %tmp107 = load i8** %x, align 8
+  %tmp107 = load i8*, i8** %x, align 8
   br label %indirectgoto
 do.end231:
-  %tmp110 = load i8** %x, align 8
+  %tmp110 = load i8*, i8** %x, align 8
   br label %indirectgoto
 do.end242:
-  %tmp113 = load i8** %x, align 8
+  %tmp113 = load i8*, i8** %x, align 8
   br label %indirectgoto
 do.end253:
-  %tmp116 = load i8** %x, align 8
+  %tmp116 = load i8*, i8** %x, align 8
   br label %indirectgoto
 do.end286:
-  %tmp125 = load i8** %x, align 8
+  %tmp125 = load i8*, i8** %x, align 8
   br label %indirectgoto
 do.end297:
-  %tmp128 = load i8** %x, align 8
+  %tmp128 = load i8*, i8** %x, align 8
   br label %indirectgoto
 do.end308:
-  %tmp131 = load i8** %x, align 8
+  %tmp131 = load i8*, i8** %x, align 8
   br label %indirectgoto
 do.end429:
-  %tmp164 = load i8** %x, align 8
+  %tmp164 = load i8*, i8** %x, align 8
   br label %indirectgoto
 do.end440:
-  %tmp167 = load i8** %x, align 8
+  %tmp167 = load i8*, i8** %x, align 8
   br label %indirectgoto
 do.body482:
   br i1 false, label %indirectgoto, label %do.body495
@@ -55,16 +55,16 @@ inline_return:
 jit_return:
   br label %indirectgoto.preheader
 L_JSOP_UINT24:
-  %tmp864 = load i8** %x, align 8
+  %tmp864 = load i8*, i8** %x, align 8
   br label %indirectgoto
 L_JSOP_THROWING:
-  %tmp1201 = load i8** %x, align 8
+  %tmp1201 = load i8*, i8** %x, align 8
   br label %indirectgoto
 do.body4936:
-  %tmp1240 = load i8** %x, align 8
+  %tmp1240 = load i8*, i8** %x, align 8
   br label %indirectgoto
 do.body5184:
-  %tmp1340 = load i8** %x, align 8
+  %tmp1340 = load i8*, i8** %x, align 8
   br label %indirectgoto
 if.end5571:
   br  label %inline_return
diff --git a/test/CodeGen/X86/pr13458.ll b/test/CodeGen/X86/pr13458.ll
index 55548b3c3b45..426fd67e6b43 100644
--- a/test/CodeGen/X86/pr13458.ll
+++ b/test/CodeGen/X86/pr13458.ll
@@ -9,6 +9,6 @@ target triple = "x86_64-apple-darwin11.4.2"
 
 define void @MergeStats() nounwind {
 allocas:
-  %r.i.i720 = atomicrmw max i64* getelementptr inbounds (%v8_uniform_Stats.0.2.4.10* @globalStats, i64 0, i32 30), i64 0 seq_cst
+  %r.i.i720 = atomicrmw max i64* getelementptr inbounds (%v8_uniform_Stats.0.2.4.10, %v8_uniform_Stats.0.2.4.10* @globalStats, i64 0, i32 30), i64 0 seq_cst
   ret void
 }
diff --git a/test/CodeGen/X86/pr13859.ll b/test/CodeGen/X86/pr13859.ll
index 719721dfd87b..1ebc79647ee1 100644
--- a/test/CodeGen/X86/pr13859.ll
+++ b/test/CodeGen/X86/pr13859.ll
@@ -7,7 +7,7 @@ entry:
   %aMyAlloca = alloca i32, align 32
   %dest = alloca <1 x i64>, align 32
 
-  %a32 = load i32* %aMyAlloca, align 4
+  %a32 = load i32, i32* %aMyAlloca, align 4
   %aconv = trunc i32 %a32 to i16
   %a36 = insertelement <4 x i16> undef, i16 %aconv, i32 0
   %a37 = insertelement <4 x i16> %a36, i16 %aconv, i32 1
diff --git a/test/CodeGen/X86/pr13899.ll b/test/CodeGen/X86/pr13899.ll
index bc81e34d67e3..abfb918ff0f5 100644
--- a/test/CodeGen/X86/pr13899.ll
+++ b/test/CodeGen/X86/pr13899.ll
@@ -26,25 +26,25 @@ declare <8 x float> @bar64(<8 x float> %i0, <8 x float> %i1,
                          <8 x float> %i8, <8 x float> %i9)
 
 define <8 x float> @foo64(<8 x float>* %p) {
-  %1 = load <8 x float>* %p
-  %idx1 = getelementptr inbounds <8 x float>* %p, i64 1
-  %2 = load <8 x float>* %idx1
-  %idx2 = getelementptr inbounds <8 x float>* %p, i64 2
-  %3 = load <8 x float>* %idx2
-  %idx3 = getelementptr inbounds <8 x float>* %p, i64 3
-  %4 = load <8 x float>* %idx3
-  %idx4 = getelementptr inbounds <8 x float>* %p, i64 4
-  %5 = load <8 x float>* %idx4
-  %idx5 = getelementptr inbounds <8 x float>* %p, i64 5
-  %6 = load <8 x float>* %idx5
-  %idx6 = getelementptr inbounds <8 x float>* %p, i64 6
-  %7 = load <8 x float>* %idx6
-  %idx7 = getelementptr inbounds <8 x float>* %p, i64 7
-  %8 = load <8 x float>* %idx7
-  %idx8 = getelementptr inbounds <8 x float>* %p, i64 8
-  %9 = load <8 x float>* %idx8
-  %idx9 = getelementptr inbounds <8 x float>* %p, i64 9
-  %10 = load <8 x float>* %idx9
+  %1 = load <8 x float>, <8 x float>* %p
+  %idx1 = getelementptr inbounds <8 x float>, <8 x float>* %p, i64 1
+  %2 = load <8 x float>, <8 x float>* %idx1
+  %idx2 = getelementptr inbounds <8 x float>, <8 x float>* %p, i64 2
+  %3 = load <8 x float>, <8 x float>* %idx2
+  %idx3 = getelementptr inbounds <8 x float>, <8 x float>* %p, i64 3
+  %4 = load <8 x float>, <8 x float>* %idx3
+  %idx4 = getelementptr inbounds <8 x float>, <8 x float>* %p, i64 4
+  %5 = load <8 x float>, <8 x float>* %idx4
+  %idx5 = getelementptr inbounds <8 x float>, <8 x float>* %p, i64 5
+  %6 = load <8 x float>, <8 x float>* %idx5
+  %idx6 = getelementptr inbounds <8 x float>, <8 x float>* %p, i64 6
+  %7 = load <8 x float>, <8 x float>* %idx6
+  %idx7 = getelementptr inbounds <8 x float>, <8 x float>* %p, i64 7
+  %8 = load <8 x float>, <8 x float>* %idx7
+  %idx8 = getelementptr inbounds <8 x float>, <8 x float>* %p, i64 8
+  %9 = load <8 x float>, <8 x float>* %idx8
+  %idx9 = getelementptr inbounds <8 x float>, <8 x float>* %p, i64 9
+  %10 = load <8 x float>, <8 x float>* %idx9
   %r = tail call <8 x float> @bar64(<8 x float> %1, <8 x float> %2,
                                     <8 x float> %3, <8 x float> %4,
                                     <8 x float> %5, <8 x float> %6,
diff --git a/test/CodeGen/X86/pr14161.ll b/test/CodeGen/X86/pr14161.ll
index c2bb8d3df8f3..95c71405bc9e 100644
--- a/test/CodeGen/X86/pr14161.ll
+++ b/test/CodeGen/X86/pr14161.ll
@@ -10,7 +10,7 @@ define <2 x i16> @good(<4 x i32>*, <4 x i8>*) {
 ; CHECK-NEXT:    pmovzxwq %xmm0, %xmm0
 ; CHECK-NEXT:    retq
 entry:
-  %2 = load <4 x i32>* %0, align 16
+  %2 = load <4 x i32>, <4 x i32>* %0, align 16
   %3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32 127>)
   %4 = extractelement <4 x i32> %3, i32 0
   %5 = extractelement <4 x i32> %3, i32 1
@@ -26,12 +26,11 @@ define <2 x i16> @bad(<4 x i32>*, <4 x i8>*) {
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    movdqa (%rdi), %xmm0
 ; CHECK-NEXT:    pminud {{.*}}(%rip), %xmm0
-; CHECK-NEXT:    pextrd $1, %xmm0, %eax
-; CHECK-NEXT:    movd %eax, %xmm0
-; CHECK-NEXT:    pmovzxwq %xmm0, %xmm0
+; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
+; CHECK-NEXT:    pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
 ; CHECK-NEXT:    retq
 entry:
-  %2 = load <4 x i32>* %0, align 16
+  %2 = load <4 x i32>, <4 x i32>* %0, align 16
   %3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32 127>)
   %4 = extractelement <4 x i32> %3, i32 0
   %5 = extractelement <4 x i32> %3, i32 1
diff --git a/test/CodeGen/X86/pr14333.ll b/test/CodeGen/X86/pr14333.ll
index 86c12ef6b547..89779302d7f2 100644
--- a/test/CodeGen/X86/pr14333.ll
+++ b/test/CodeGen/X86/pr14333.ll
@@ -1,9 +1,9 @@
 ; RUN: llc -mtriple=x86_64-unknown-unknown < %s
 %foo = type { i64, i64 }
 define void @bar(%foo* %zed) {
-  %tmp = getelementptr inbounds %foo* %zed, i64 0, i32 0
+  %tmp = getelementptr inbounds %foo, %foo* %zed, i64 0, i32 0
   store i64 0, i64* %tmp, align 8
-  %tmp2 = getelementptr inbounds %foo* %zed, i64 0, i32 1
+  %tmp2 = getelementptr inbounds %foo, %foo* %zed, i64 0, i32 1
   store i64 0, i64* %tmp2, align 8
   %tmp3 = bitcast %foo* %zed to i8*
   call void @llvm.memset.p0i8.i64(i8* %tmp3, i8 0, i64 16, i32 8, i1 false)
diff --git a/test/CodeGen/X86/pr14562.ll b/test/CodeGen/X86/pr14562.ll
index e66f1752a30f..31674546423e 100644
--- a/test/CodeGen/X86/pr14562.ll
+++ b/test/CodeGen/X86/pr14562.ll
@@ -3,7 +3,7 @@
 @temp1 = global i64 -77129852189294865, align 8
 
 define void @foo() nounwind {
-  %x = load i64* @temp1, align 8
+  %x = load i64, i64* @temp1, align 8
   %s = shl i64 %x, 32
   %t = trunc i64 %s to i32
   %z = zext i32 %t to i64
diff --git a/test/CodeGen/X86/pr1489.ll b/test/CodeGen/X86/pr1489.ll
index c9e24bfb13fa..13ced2a32745 100644
--- a/test/CodeGen/X86/pr1489.ll
+++ b/test/CodeGen/X86/pr1489.ll
@@ -48,7 +48,7 @@ entry:
 	%tmp1 = tail call i32 @bar( )		; <i32> [#uses=1]
 	%tmp2 = tail call i32 @foo( )		; <i32> [#uses=1]
 	%tmp3 = tail call i32 @quux( )		; <i32> [#uses=1]
-	%tmp5 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([13 x i8]* @.str, i32 0, i32 0), i32 %tmp3, i32 %tmp2, i32 %tmp1, i32 %tmp )		; <i32> [#uses=0]
+	%tmp5 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %tmp3, i32 %tmp2, i32 %tmp1, i32 %tmp )		; <i32> [#uses=0]
 	ret i32 undef
 }
 
diff --git a/test/CodeGen/X86/pr1505b.ll b/test/CodeGen/X86/pr1505b.ll
index c348fec54674..c1363457c8c4 100644
--- a/test/CodeGen/X86/pr1505b.ll
+++ b/test/CodeGen/X86/pr1505b.ll
@@ -33,7 +33,7 @@ declare i32 @__cxa_atexit(void (i8*)*, i8*, i8*)
 define i32 @main() {
 entry:
 ; CHECK: flds
-	%tmp6 = load volatile float* @a		; <float> [#uses=1]
+	%tmp6 = load volatile float, float* @a		; <float> [#uses=1]
 ; CHECK: fstps (%esp)
 ; CHECK: tanf
 	%tmp9 = tail call float @tanf( float %tmp6 )		; <float> [#uses=1]
@@ -41,14 +41,14 @@ entry:
 ; CHECK: fstp
 
 ; CHECK: fldl
-	%tmp12 = load volatile double* @b		; <double> [#uses=1]
+	%tmp12 = load volatile double, double* @b		; <double> [#uses=1]
 ; CHECK: fstpl (%esp)
 ; CHECK: tan
 	%tmp13 = tail call double @tan( double %tmp12 )		; <double> [#uses=1]
 ; Spill returned value:
 ; CHECK: fstp
 	%tmp1314 = fptrunc double %tmp13 to float		; <float> [#uses=1]
-	%tmp16 = tail call %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc( %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZSt4cout, i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0) )		; <%"struct.std::basic_ostream<char,std::char_traits<char> >"*> [#uses=1]
+	%tmp16 = tail call %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc( %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZSt4cout, i8* getelementptr ([12 x i8], [12 x i8]* @.str, i32 0, i32 0) )		; <%"struct.std::basic_ostream<char,std::char_traits<char> >"*> [#uses=1]
 	%tmp1920 = fpext float %tmp9 to double		; <double> [#uses=1]
 ; reload:
 ; CHECK: fld
@@ -58,7 +58,7 @@ entry:
 	%tmp30 = tail call %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_( %"struct.std::basic_ostream<char,std::char_traits<char> >"* %tmp22 )		; <%"struct.std::basic_ostream<char,std::char_traits<char> >"*> [#uses=0]
 ; reload:
 ; CHECK: ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
-	%tmp34 = tail call %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc( %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZSt4cout, i8* getelementptr ([13 x i8]* @.str1, i32 0, i32 0) )		; <%"struct.std::basic_ostream<char,std::char_traits<char> >"*> [#uses=1]
+	%tmp34 = tail call %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc( %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZSt4cout, i8* getelementptr ([13 x i8], [13 x i8]* @.str1, i32 0, i32 0) )		; <%"struct.std::basic_ostream<char,std::char_traits<char> >"*> [#uses=1]
 	%tmp3940 = fpext float %tmp1314 to double		; <double> [#uses=1]
 ; CHECK: fld
 ; CHECK: fstpl
diff --git a/test/CodeGen/X86/pr15267.ll b/test/CodeGen/X86/pr15267.ll
index 90df9905fe1a..95d7deb34170 100644
--- a/test/CodeGen/X86/pr15267.ll
+++ b/test/CodeGen/X86/pr15267.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s
 
 define <4 x i3> @test1(<4 x i3>* %in) nounwind {
-  %ret = load <4 x i3>* %in, align 1
+  %ret = load <4 x i3>, <4 x i3>* %in, align 1
   ret <4 x i3> %ret
 }
 ; CHECK-LABEL: test1
@@ -20,7 +20,7 @@ define <4 x i3> @test1(<4 x i3>* %in) nounwind {
 ; CHECK: ret
 
 define <4 x i1> @test2(<4 x i1>* %in) nounwind {
-  %ret = load <4 x i1>* %in, align 1
+  %ret = load <4 x i1>, <4 x i1>* %in, align 1
   ret <4 x i1> %ret
 }
 
@@ -40,7 +40,7 @@ define <4 x i1> @test2(<4 x i1>* %in) nounwind {
 ; CHECK: ret
 
 define <4 x i64> @test3(<4 x i1>* %in) nounwind {
-  %wide.load35 = load <4 x i1>* %in, align 1
+  %wide.load35 = load <4 x i1>, <4 x i1>* %in, align 1
   %sext = sext <4 x i1> %wide.load35 to <4 x i64>
   ret <4 x i64> %sext
 }
@@ -50,25 +50,27 @@ define <4 x i64> @test3(<4 x i1>* %in) nounwind {
 ; CHECK: movq
 ; CHECK: shlq
 ; CHECK: sarq
-; CHECK: vmovq
 ; CHECK: movq
 ; CHECK: shlq
 ; CHECK: sarq
-; CHECK: vmovq
-; CHECK: vpunpcklqdq
+; CHECK: vmovd
+; CHECK: vpinsrd
 ; CHECK: movq
 ; CHECK: shlq
 ; CHECK: sarq
-; CHECK: vmovq
+; CHECK: vpinsrd
 ; CHECK: shlq
 ; CHECK: sarq
-; CHECK: vmovq
-; CHECK: vpunpcklqdq
+; CHECK: vpinsrd
+; CHECK: vpmovsxdq
+; CHECK: vmovd
+; CHECK: vpinsrd
+; CHECK: vpmovsxdq
 ; CHECK: vinsertf128
 ; CHECK: ret
 
 define <16 x i4> @test4(<16 x i4>* %in) nounwind {
-  %ret = load <16 x i4>* %in, align 1
+  %ret = load <16 x i4>, <16 x i4>* %in, align 1
   ret <16 x i4> %ret
 }
 
diff --git a/test/CodeGen/X86/pr15309.ll b/test/CodeGen/X86/pr15309.ll
index 6dbbc72a7b7a..e9d9b9e54c13 100644
--- a/test/CodeGen/X86/pr15309.ll
+++ b/test/CodeGen/X86/pr15309.ll
@@ -2,10 +2,10 @@
 
 define void @test_convert_float2_ulong2(<2 x i64>* nocapture %src, <2 x float>* nocapture %dest) noinline {
 L.entry:
-  %0 = getelementptr <2 x i64>* %src, i32 10
-  %1 = load <2 x i64>* %0, align 16
+  %0 = getelementptr <2 x i64>, <2 x i64>* %src, i32 10
+  %1 = load <2 x i64>, <2 x i64>* %0, align 16
   %2 = uitofp <2 x i64> %1 to <2 x float>
-  %3 = getelementptr <2 x float>* %dest, i32 10
+  %3 = getelementptr <2 x float>, <2 x float>* %dest, i32 10
   store <2 x float> %2, <2 x float>* %3, align 8
   ret void
 }
diff --git a/test/CodeGen/X86/pr18023.ll b/test/CodeGen/X86/pr18023.ll
index 4c6f8cfce732..c7ea20c281ba 100644
--- a/test/CodeGen/X86/pr18023.ll
+++ b/test/CodeGen/X86/pr18023.ll
@@ -13,18 +13,18 @@
 @.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1
 
 define void @func() {
-  store i32 1, i32* getelementptr inbounds ([3 x i32]* @a, i64 0, i64 1), align 4
-  store i32 0, i32* getelementptr inbounds ([3 x i32]* @a, i64 0, i64 0), align 4
-  %1 = load volatile i32* @b, align 4
-  store i32 1, i32* getelementptr inbounds ([3 x i32]* @a, i64 0, i64 1), align 4
-  store i32 0, i32* getelementptr inbounds ([3 x i32]* @a, i64 0, i64 1), align 4
-  %2 = load volatile i32* @b, align 4
-  store i32 1, i32* getelementptr inbounds ([3 x i32]* @a, i64 0, i64 1), align 4
-  store i32 0, i32* getelementptr inbounds ([3 x i32]* @a, i64 0, i64 2), align 4
-  %3 = load volatile i32* @b, align 4
+  store i32 1, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @a, i64 0, i64 1), align 4
+  store i32 0, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @a, i64 0, i64 0), align 4
+  %1 = load volatile i32, i32* @b, align 4
+  store i32 1, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @a, i64 0, i64 1), align 4
+  store i32 0, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @a, i64 0, i64 1), align 4
+  %2 = load volatile i32, i32* @b, align 4
+  store i32 1, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @a, i64 0, i64 1), align 4
+  store i32 0, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @a, i64 0, i64 2), align 4
+  %3 = load volatile i32, i32* @b, align 4
   store i32 3, i32* @c, align 4
-  %4 = load i32* getelementptr inbounds ([3 x i32]* @a, i64 0, i64 1), align 4
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32 %4)
+  %4 = load i32, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @a, i64 0, i64 1), align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %4)
   ret void
 }
 
diff --git a/test/CodeGen/X86/pr18162.ll b/test/CodeGen/X86/pr18162.ll
index 523e47db5eee..7912db863edb 100644
--- a/test/CodeGen/X86/pr18162.ll
+++ b/test/CodeGen/X86/pr18162.ll
@@ -13,15 +13,15 @@ define { i64, <2 x float> } @Foo(%"Iterator"* %this) {
 entry:
   %retval = alloca i32
   %this.addr = alloca %"Iterator"*
-  %this1 = load %"Iterator"** %this.addr
-  %bundle_ = getelementptr inbounds %"Iterator"* %this1, i32 0, i32 0
-  %0 = load i32** %bundle_
+  %this1 = load %"Iterator"*, %"Iterator"** %this.addr
+  %bundle_ = getelementptr inbounds %"Iterator", %"Iterator"* %this1, i32 0, i32 0
+  %0 = load i32*, i32** %bundle_
   %1 = call { i64, <2 x float> } @Call()
   %2 = call { i64, <2 x float> }* @CallPtr()
-  %3 = getelementptr { i64, <2 x float> }* %2, i32 0, i32 1
+  %3 = getelementptr { i64, <2 x float> }, { i64, <2 x float> }* %2, i32 0, i32 1
   %4 = extractvalue { i64, <2 x float> } %1, 1
   store <2 x float> %4, <2 x float>* %3
-  %5 = load { i64, <2 x float> }* %2
+  %5 = load { i64, <2 x float> }, { i64, <2 x float> }* %2
   ret { i64, <2 x float> } %5
 }
 
diff --git a/test/CodeGen/X86/pr18846.ll b/test/CodeGen/X86/pr18846.ll
index c65bc79d6813..02c33fed8d6b 100644
--- a/test/CodeGen/X86/pr18846.ll
+++ b/test/CodeGen/X86/pr18846.ll
@@ -21,31 +21,31 @@ for.body29:                                       ; preds = %for.body29, %entry
   br i1 undef, label %for.body29, label %for.body65
 
 for.body65:                                       ; preds = %for.body29
-  %0 = load float* undef, align 4, !tbaa !1
+  %0 = load float, float* undef, align 4, !tbaa !1
   %vecinit7.i4448 = insertelement <8 x float> undef, float %0, i32 7
-  %1 = load float* null, align 4, !tbaa !1
+  %1 = load float, float* null, align 4, !tbaa !1
   %vecinit7.i4304 = insertelement <8 x float> undef, float %1, i32 7
-  %2 = load float* undef, align 4, !tbaa !1
+  %2 = load float, float* undef, align 4, !tbaa !1
   %vecinit7.i4196 = insertelement <8 x float> undef, float %2, i32 7
   %3 = or i64 0, 16
   %add.ptr111.sum4096 = add i64 %3, 0
-  %4 = load <8 x float>* null, align 16, !tbaa !5
-  %add.ptr162 = getelementptr inbounds [65536 x float]* null, i64 0, i64 %add.ptr111.sum4096
+  %4 = load <8 x float>, <8 x float>* null, align 16, !tbaa !5
+  %add.ptr162 = getelementptr inbounds [65536 x float], [65536 x float]* null, i64 0, i64 %add.ptr111.sum4096
   %__v.i4158 = bitcast float* %add.ptr162 to <8 x float>*
-  %5 = load <8 x float>* %__v.i4158, align 16, !tbaa !5
+  %5 = load <8 x float>, <8 x float>* %__v.i4158, align 16, !tbaa !5
   %add.ptr158.sum40975066 = or i64 %add.ptr111.sum4096, 8
-  %add.ptr183 = getelementptr inbounds [65536 x float]* null, i64 0, i64 %add.ptr158.sum40975066
+  %add.ptr183 = getelementptr inbounds [65536 x float], [65536 x float]* null, i64 0, i64 %add.ptr158.sum40975066
   %__v.i4162 = bitcast float* %add.ptr183 to <8 x float>*
-  %6 = load <8 x float>* %__v.i4162, align 16, !tbaa !5
+  %6 = load <8 x float>, <8 x float>* %__v.i4162, align 16, !tbaa !5
   %add.ptr200.sum40995067 = or i64 undef, 8
-  %add.ptr225 = getelementptr inbounds [65536 x float]* null, i64 0, i64 %add.ptr200.sum40995067
+  %add.ptr225 = getelementptr inbounds [65536 x float], [65536 x float]* null, i64 0, i64 %add.ptr200.sum40995067
   %__v.i4167 = bitcast float* %add.ptr225 to <8 x float>*
-  %7 = load <8 x float>* %__v.i4167, align 4, !tbaa !5
-  %8 = load <8 x float>* undef, align 16, !tbaa !5
+  %7 = load <8 x float>, <8 x float>* %__v.i4167, align 4, !tbaa !5
+  %8 = load <8 x float>, <8 x float>* undef, align 16, !tbaa !5
   %add.ptr242.sum41015068 = or i64 0, 8
-  %add.ptr267 = getelementptr inbounds [65536 x float]* null, i64 0, i64 %add.ptr242.sum41015068
+  %add.ptr267 = getelementptr inbounds [65536 x float], [65536 x float]* null, i64 0, i64 %add.ptr242.sum41015068
   %__v.i4171 = bitcast float* %add.ptr267 to <8 x float>*
-  %9 = load <8 x float>* %__v.i4171, align 4, !tbaa !5
+  %9 = load <8 x float>, <8 x float>* %__v.i4171, align 4, !tbaa !5
   %mul.i4690 = fmul <8 x float> %7, undef
   %add.i4665 = fadd <8 x float> undef, undef
   %mul.i4616 = fmul <8 x float> %8, undef
@@ -56,8 +56,8 @@ for.body65:                                       ; preds = %for.body29
   %mul.i4578 = fmul <8 x float> %9, undef
   %add.i4577 = fadd <8 x float> %add.i4593, %mul.i4578
   call void @llvm.x86.avx.storeu.ps.256(i8* undef, <8 x float> %add.i4577) #1
-  %10 = load <8 x float>* null, align 16, !tbaa !5
-  %11 = load <8 x float>* undef, align 16, !tbaa !5
+  %10 = load <8 x float>, <8 x float>* null, align 16, !tbaa !5
+  %11 = load <8 x float>, <8 x float>* undef, align 16, !tbaa !5
   %mul.i4564 = fmul <8 x float> %4, undef
   %add.i4563 = fadd <8 x float> %10, %mul.i4564
   %mul.i4560 = fmul <8 x float> %5, undef
@@ -107,7 +107,7 @@ for.body65:                                       ; preds = %for.body29
   call void @llvm.x86.avx.storeu.ps.256(i8* undef, <8 x float> %add.i4293) #1
   call void @llvm.x86.avx.storeu.ps.256(i8* undef, <8 x float> %add.i4291) #1
   call void @llvm.x86.avx.storeu.ps.256(i8* undef, <8 x float> %add.i4289) #1
-  %12 = load <8 x float>* undef, align 16, !tbaa !5
+  %12 = load <8 x float>, <8 x float>* undef, align 16, !tbaa !5
   %mul.i4274 = fmul <8 x float> undef, undef
   %add.i4273 = fadd <8 x float> %12, %mul.i4274
   %mul.i4258 = fmul <8 x float> %7, undef
diff --git a/test/CodeGen/X86/pr20020.ll b/test/CodeGen/X86/pr20020.ll
index 83dae369dd75..56c12faaf707 100644
--- a/test/CodeGen/X86/pr20020.ll
+++ b/test/CodeGen/X86/pr20020.ll
@@ -17,7 +17,7 @@ entry:
   br i1 %cmp4, label %for.body.preheader, label %for.end38
 
 for.body.preheader:                               ; preds = %entry
-  %gep = getelementptr %struct.planet* %bodies, i64 1, i32 1
+  %gep = getelementptr %struct.planet, %struct.planet* %bodies, i64 1, i32 1
   %gep13 = bitcast double* %gep to %struct.planet*
   %0 = add i32 %nbodies, -1
   br label %for.body
@@ -32,33 +32,33 @@ for.body:                                         ; preds = %for.body.preheader,
   br i1 %cmp22, label %for.body3.lr.ph, label %for.inc20
 
 for.body3.lr.ph:                                  ; preds = %for.body
-  %x = getelementptr inbounds %struct.planet* %bodies, i64 %iv9, i32 0
-  %y = getelementptr inbounds %struct.planet* %bodies, i64 %iv9, i32 1
-  %vx = getelementptr inbounds %struct.planet* %bodies, i64 %iv9, i32 2
+  %x = getelementptr inbounds %struct.planet, %struct.planet* %bodies, i64 %iv9, i32 0
+  %y = getelementptr inbounds %struct.planet, %struct.planet* %bodies, i64 %iv9, i32 1
+  %vx = getelementptr inbounds %struct.planet, %struct.planet* %bodies, i64 %iv9, i32 2
   br label %for.body3
 
 for.body3:                                        ; preds = %for.body3, %for.body3.lr.ph
   %iv20 = phi i32 [ %iv.next21, %for.body3 ], [ %iv19, %for.body3.lr.ph ]
   %iv15 = phi %struct.planet* [ %gep16, %for.body3 ], [ %iv, %for.body3.lr.ph ]
   %iv1517 = bitcast %struct.planet* %iv15 to double*
-  %2 = load double* %x, align 8
-  %gep18 = getelementptr double* %iv1517, i64 -1
-  %3 = load double* %gep18, align 8
+  %2 = load double, double* %x, align 8
+  %gep18 = getelementptr double, double* %iv1517, i64 -1
+  %3 = load double, double* %gep18, align 8
   %sub = fsub double %2, %3
-  %4 = load double* %y, align 8
-  %5 = load double* %iv1517, align 8
+  %4 = load double, double* %y, align 8
+  %5 = load double, double* %iv1517, align 8
   %sub8 = fsub double %4, %5
   %add10 = fadd double %sub, %sub8
   %call = tail call double @sqrt(double %sub8) #2
   store double %add10, double* %vx, align 8
-  %gep16 = getelementptr %struct.planet* %iv15, i64 1
+  %gep16 = getelementptr %struct.planet, %struct.planet* %iv15, i64 1
   %iv.next21 = add i32 %iv20, -1
   %exitcond = icmp eq i32 %iv.next21, 0
   br i1 %exitcond, label %for.inc20, label %for.body3
 
 for.inc20:                                        ; preds = %for.body3, %for.body
   %lftr.wideiv11 = trunc i64 %iv.next10 to i32
-  %gep14 = getelementptr %struct.planet* %iv, i64 1
+  %gep14 = getelementptr %struct.planet, %struct.planet* %iv, i64 1
   %iv.next = add i32 %iv19, -1
   %exitcond12 = icmp eq i32 %lftr.wideiv11, %nbodies
   br i1 %exitcond12, label %for.end38, label %for.body
diff --git a/test/CodeGen/X86/pr21099.ll b/test/CodeGen/X86/pr21099.ll
index 07292c125eea..cd8205dbc815 100644
--- a/test/CodeGen/X86/pr21099.ll
+++ b/test/CodeGen/X86/pr21099.ll
@@ -2,8 +2,7 @@
 
 define void @pr21099(i64* %p) {
 ; CHECK-LABEL: pr21099
-; CHECK: lock
-; CHECK-NEXT: addq $-2147483648
+; CHECK: lock addq $-2147483648
 ; This number is INT32_MIN: 0x80000000UL
   %1 = atomicrmw add i64* %p, i64 -2147483648 seq_cst
   ret void
diff --git a/test/CodeGen/X86/pr2177.ll b/test/CodeGen/X86/pr2177.ll
index e941bf7fdabe..8260a7f0614d 100644
--- a/test/CodeGen/X86/pr2177.ll
+++ b/test/CodeGen/X86/pr2177.ll
@@ -22,10 +22,10 @@ bb10:		; preds = %bb5
 bb54:		; preds = %bb5
 	ret void
 bb118:		; preds = %bb5, %bb5, %bb5, %bb5
-	%tmp125 = load i8** null, align 8		; <i8*> [#uses=1]
+	%tmp125 = load i8*, i8** null, align 8		; <i8*> [#uses=1]
 	%tmp125126 = bitcast i8* %tmp125 to %struct.S2259*		; <%struct.S2259*> [#uses=1]
-	%tmp128 = getelementptr %struct.S2259* %tmp125126, i32 0, i32 0		; <<4 x i16>*> [#uses=1]
-	%tmp129 = load <4 x i16>* %tmp128, align 8		; <<4 x i16>> [#uses=1]
+	%tmp128 = getelementptr %struct.S2259, %struct.S2259* %tmp125126, i32 0, i32 0		; <<4 x i16>*> [#uses=1]
+	%tmp129 = load <4 x i16>, <4 x i16>* %tmp128, align 8		; <<4 x i16>> [#uses=1]
 	store <4 x i16> %tmp129, <4 x i16>* null, align 8
 	ret void
 bb155:		; preds = %bb5
diff --git a/test/CodeGen/X86/pr21792.ll b/test/CodeGen/X86/pr21792.ll
new file mode 100644
index 000000000000..59866c090543
--- /dev/null
+++ b/test/CodeGen/X86/pr21792.ll
@@ -0,0 +1,41 @@
+; RUN: llc -mtriple=x86_64-linux -mcpu=corei7 < %s | FileCheck %s

+; This fixes a missing cases in the MI scheduler's constrainLocalCopy exposed by

+; PR21792

+

+@stuff = external constant [256 x double], align 16

+

+define void @func(<4 x float> %vx) {

+entry:

+  %tmp2 = bitcast <4 x float> %vx to <2 x i64>

+  %and.i = and <2 x i64> %tmp2, <i64 8727373547504, i64 8727373547504>

+  %tmp3 = bitcast <2 x i64> %and.i to <4 x i32>

+  %index.sroa.0.0.vec.extract = extractelement <4 x i32> %tmp3, i32 0

+  %idx.ext = sext i32 %index.sroa.0.0.vec.extract to i64

+  %add.ptr = getelementptr inbounds i8, i8* bitcast ([256 x double]* @stuff to i8*), i64 %idx.ext

+  %tmp4 = bitcast i8* %add.ptr to double*

+  %index.sroa.0.4.vec.extract = extractelement <4 x i32> %tmp3, i32 1

+  %idx.ext5 = sext i32 %index.sroa.0.4.vec.extract to i64

+  %add.ptr6 = getelementptr inbounds i8, i8* bitcast ([256 x double]* @stuff to i8*), i64 %idx.ext5

+  %tmp5 = bitcast i8* %add.ptr6 to double*

+  %index.sroa.0.8.vec.extract = extractelement <4 x i32> %tmp3, i32 2

+  %idx.ext14 = sext i32 %index.sroa.0.8.vec.extract to i64

+  %add.ptr15 = getelementptr inbounds i8, i8* bitcast ([256 x double]* @stuff to i8*), i64 %idx.ext14

+  %tmp6 = bitcast i8* %add.ptr15 to double*

+  %index.sroa.0.12.vec.extract = extractelement <4 x i32> %tmp3, i32 3

+  %idx.ext19 = sext i32 %index.sroa.0.12.vec.extract to i64

+  %add.ptr20 = getelementptr inbounds i8, i8* bitcast ([256 x double]* @stuff to i8*), i64 %idx.ext19

+  %tmp7 = bitcast i8* %add.ptr20 to double*

+  %add.ptr46 = getelementptr inbounds i8, i8* bitcast (double* getelementptr inbounds ([256 x double], [256 x double]* @stuff, i64 0, i64 1) to i8*), i64 %idx.ext

+  %tmp16 = bitcast i8* %add.ptr46 to double*

+  %add.ptr51 = getelementptr inbounds i8, i8* bitcast (double* getelementptr inbounds ([256 x double], [256 x double]* @stuff, i64 0, i64 1) to i8*), i64 %idx.ext5

+  %tmp17 = bitcast i8* %add.ptr51 to double*

+  call void @toto(double* %tmp4, double* %tmp5, double* %tmp6, double* %tmp7, double* %tmp16, double* %tmp17)

+  ret void

+; CHECK-LABEL: func:

+; CHECK: pextrq  $1, %xmm0,

+; CHECK-NEXT: movd    %xmm0, %r[[AX:..]]

+; CHECK-NEXT: movslq  %e[[AX]],

+; CHECK-NEXT: sarq    $32, %r[[AX]]

+}

+

+declare void @toto(double*, double*, double*, double*, double*, double*)

diff --git a/test/CodeGen/X86/pr2182.ll b/test/CodeGen/X86/pr2182.ll
index 94429b265d97..0cf3acf23b3c 100644
--- a/test/CodeGen/X86/pr2182.ll
+++ b/test/CodeGen/X86/pr2182.ll
@@ -15,16 +15,16 @@ define void @loop_2() nounwind  {
 ; CHECK-NEXT: addl $3, (%{{.*}})
 ; CHECK-NEXT: ret
 
-  %tmp = load volatile i32* @x, align 4           ; <i32> [#uses=1]
+  %tmp = load volatile i32, i32* @x, align 4           ; <i32> [#uses=1]
   %tmp1 = add i32 %tmp, 3         ; <i32> [#uses=1]
   store volatile i32 %tmp1, i32* @x, align 4
-  %tmp.1 = load volatile i32* @x, align 4         ; <i32> [#uses=1]
+  %tmp.1 = load volatile i32, i32* @x, align 4         ; <i32> [#uses=1]
   %tmp1.1 = add i32 %tmp.1, 3             ; <i32> [#uses=1]
   store volatile i32 %tmp1.1, i32* @x, align 4
-  %tmp.2 = load volatile i32* @x, align 4         ; <i32> [#uses=1]
+  %tmp.2 = load volatile i32, i32* @x, align 4         ; <i32> [#uses=1]
   %tmp1.2 = add i32 %tmp.2, 3             ; <i32> [#uses=1]
   store volatile i32 %tmp1.2, i32* @x, align 4
-  %tmp.3 = load volatile i32* @x, align 4         ; <i32> [#uses=1]
+  %tmp.3 = load volatile i32, i32* @x, align 4         ; <i32> [#uses=1]
   %tmp1.3 = add i32 %tmp.3, 3             ; <i32> [#uses=1]
   store volatile i32 %tmp1.3, i32* @x, align 4
   ret void
diff --git a/test/CodeGen/X86/pr22774.ll b/test/CodeGen/X86/pr22774.ll
index 426fcc43e308..8a80e9d6d625 100644
--- a/test/CodeGen/X86/pr22774.ll
+++ b/test/CodeGen/X86/pr22774.ll
@@ -1,17 +1,14 @@
-; RUN: llc -mattr=avx %s -o - | FileCheck %s

+; RUN: llc -mtriple=x86_64-pc-linux-gnu -mattr=+avx < %s | FileCheck %s
 
-target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
-target triple = "x86_64-pc-linux-gnu"
-

 @in = global <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, align 32
 @out = global <2 x i64> zeroinitializer, align 16
 
 define i32 @_Z3foov() {
 entry:
-; CHECK: {{vmovdqa|vmovaps}} in(%rip), %ymm0
+; CHECK: vmovdqa in(%rip), %ymm0
 ; CHECK-NEXT: vmovq %xmm0, %xmm0
-; CHECK-NEXT: {{vmovdqa|vmovaps}} %xmm0, out(%rip)
-  %0 = load <4 x i64>* @in, align 32
+; CHECK-NEXT: vmovdqa %xmm0, out(%rip)
+  %0 = load <4 x i64>, <4 x i64>* @in, align 32
   %vecext = extractelement <4 x i64> %0, i32 0
   %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
   %vecinit1 = insertelement <2 x i64> %vecinit, i64 0, i32 1
diff --git a/test/CodeGen/X86/pr23103.ll b/test/CodeGen/X86/pr23103.ll
new file mode 100644
index 000000000000..e0508effac05
--- /dev/null
+++ b/test/CodeGen/X86/pr23103.ll
@@ -0,0 +1,21 @@
+; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx < %s | FileCheck %s
+
+; When commuting a VADDSDrr instruction, verify that the 'IsUndef' flag is
+; correctly propagated to the operands of the resulting instruction.
+; Test for PR23103;
+
+declare zeroext i1 @foo(<1 x double>)
+
+define <1 x double> @pr23103(<1 x double>* align 8 %Vp) {
+; CHECK-LABEL: pr23103:
+; CHECK:         vmovsd (%rdi), %xmm0
+; CHECK-NEXT:    vmovsd %xmm0, {{.*}}(%rsp) {{.*#+}} 8-byte Spill
+; CHECK-NEXT:    callq foo
+; CHECK-NEXT:    vaddsd {{.*}}(%rsp), %xmm0, %xmm0 {{.*#+}} 8-byte Folded Reload
+; CHECK:         retq
+entry:
+  %V = load <1 x double>, <1 x double>* %Vp, align 8
+  %call = call zeroext i1 @foo(<1 x double> %V)
+  %fadd = fadd <1 x double> %V, undef
+  ret <1 x double> %fadd
+}
diff --git a/test/CodeGen/X86/pr23246.ll b/test/CodeGen/X86/pr23246.ll
new file mode 100644
index 000000000000..6eb24a6b1634
--- /dev/null
+++ b/test/CodeGen/X86/pr23246.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple x86_64-unknown-unknown | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+
+; PR23246
+; We're really only interested in doing something sane with the shuffle.
+
+; CHECK-LABEL: test:
+; CHECK:      movq2dq %mm0, %xmm0
+; CHECK-NEXT: pshufd {{.*}} xmm0 = xmm0[0,1,0,1]
+; CHECK-NEXT: retq
+define <2 x i64> @test(x86_mmx %a) #0 {
+entry:
+  %b = bitcast x86_mmx %a to <1 x i64>
+  %s = shufflevector <1 x i64> %b, <1 x i64> undef, <2 x i32> <i32 undef, i32 0>
+  ret <2 x i64> %s
+}
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/X86/pr2326.ll b/test/CodeGen/X86/pr2326.ll
index f82dcb5d678f..88c7bb586701 100644
--- a/test/CodeGen/X86/pr2326.ll
+++ b/test/CodeGen/X86/pr2326.ll
@@ -4,12 +4,12 @@
 define i32 @func_59(i32 %p_60) nounwind  {
 entry:
 	%l_108 = alloca i32		; <i32*> [#uses=2]
-	%tmp15 = load i32* null, align 4		; <i32> [#uses=1]
-	%tmp16 = load i32* %l_108, align 4		; <i32> [#uses=1]
+	%tmp15 = load i32, i32* null, align 4		; <i32> [#uses=1]
+	%tmp16 = load i32, i32* %l_108, align 4		; <i32> [#uses=1]
 	%tmp17 = icmp eq i32 %tmp15, %tmp16		; <i1> [#uses=1]
 	%tmp1718 = zext i1 %tmp17 to i8		; <i8> [#uses=1]
-	%tmp19 = load i32* null, align 4		; <i32> [#uses=1]
-	%tmp20 = load i32* %l_108, align 4		; <i32> [#uses=1]
+	%tmp19 = load i32, i32* null, align 4		; <i32> [#uses=1]
+	%tmp20 = load i32, i32* %l_108, align 4		; <i32> [#uses=1]
 	%tmp21 = icmp ule i32 %tmp19, %tmp20		; <i1> [#uses=1]
 	%tmp2122 = zext i1 %tmp21 to i8		; <i8> [#uses=1]
 	%toBool23 = icmp ne i8 %tmp1718, 0		; <i1> [#uses=1]
@@ -17,7 +17,7 @@ entry:
 	%tmp25 = and i1 %toBool23, %toBool24		; <i1> [#uses=1]
 	%tmp2526 = zext i1 %tmp25 to i8		; <i8> [#uses=1]
 	%tmp252627 = zext i8 %tmp2526 to i32		; <i32> [#uses=1]
-	%tmp29 = call i32 (...)* @func_15( i32 %tmp252627, i32 0 ) nounwind 		; <i32> [#uses=0]
+	%tmp29 = call i32 (...) @func_15( i32 %tmp252627, i32 0 ) nounwind 		; <i32> [#uses=0]
 	unreachable
 }
 
diff --git a/test/CodeGen/X86/pr23273.ll b/test/CodeGen/X86/pr23273.ll
new file mode 100644
index 000000000000..2702eb820f2f
--- /dev/null
+++ b/test/CodeGen/X86/pr23273.ll
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=i386-unknown-unknown -mcpu=generic -march=x86 -mattr=-sse2 -fast-isel < %s
+
+; Verify that the backend doesn't crash during fast-isel with an assertion
+; failure when selecting a int-to-double conversion. The fast selection routine
+; for SINT_TO_FP wrongly assumed that the target had at least SSE2.
+
+@a = common global i32 0, align 4
+
+define i32 @pr23273() {
+entry:
+  %0 = load i32, i32* @a, align 4
+  %conv = sitofp i32 %0 to double
+  %call = call i32 @fn1(double %conv)
+  ret i32 0
+}
+
+declare i32 @fn1(double) #1
diff --git a/test/CodeGen/X86/pr2656.ll b/test/CodeGen/X86/pr2656.ll
index 1122d2d57114..9a162d77ef48 100644
--- a/test/CodeGen/X86/pr2656.ll
+++ b/test/CodeGen/X86/pr2656.ll
@@ -11,15 +11,15 @@ target triple = "i686-apple-darwin9.4.0"
 
 define void @foo(%struct.anon* byval %p) nounwind {
 entry:
-	%tmp = getelementptr %struct.anon* %p, i32 0, i32 0		; <float*> [#uses=1]
-	%tmp1 = load float* %tmp		; <float> [#uses=1]
-	%tmp2 = getelementptr %struct.anon* %p, i32 0, i32 1		; <float*> [#uses=1]
-	%tmp3 = load float* %tmp2		; <float> [#uses=1]
+	%tmp = getelementptr %struct.anon, %struct.anon* %p, i32 0, i32 0		; <float*> [#uses=1]
+	%tmp1 = load float, float* %tmp		; <float> [#uses=1]
+	%tmp2 = getelementptr %struct.anon, %struct.anon* %p, i32 0, i32 1		; <float*> [#uses=1]
+	%tmp3 = load float, float* %tmp2		; <float> [#uses=1]
 	%neg = fsub float -0.000000e+00, %tmp1		; <float> [#uses=1]
 	%conv = fpext float %neg to double		; <double> [#uses=1]
 	%neg4 = fsub float -0.000000e+00, %tmp3		; <float> [#uses=1]
 	%conv5 = fpext float %neg4 to double		; <double> [#uses=1]
-	%call = call i32 (...)* @printf( i8* getelementptr ([17 x i8]* @.str, i32 0, i32 0), double %conv, double %conv5 )		; <i32> [#uses=0]
+	%call = call i32 (...) @printf( i8* getelementptr ([17 x i8], [17 x i8]* @.str, i32 0, i32 0), double %conv, double %conv5 )		; <i32> [#uses=0]
 	ret void
 }
 
diff --git a/test/CodeGen/X86/pr2849.ll b/test/CodeGen/X86/pr2849.ll
index 0fec4813e109..c3fd101ab6db 100644
--- a/test/CodeGen/X86/pr2849.ll
+++ b/test/CodeGen/X86/pr2849.ll
@@ -13,24 +13,24 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define void @obshow() {
 entry:
-	%tmp = load %struct.HashEntry** @hash_table_begin, align 8
+	%tmp = load %struct.HashEntry*, %struct.HashEntry** @hash_table_begin, align 8
 	br i1 false, label %xlygetvalue.exit, label %xlygetvalue.exit
 
 xlygetvalue.exit:
 	%storemerge.in.i = phi %struct.NODE** [ null, %entry ], [ null, %entry ]
-	%storemerge.i = load %struct.NODE** %storemerge.in.i
+	%storemerge.i = load %struct.NODE*, %struct.NODE** %storemerge.in.i
 	%tmp1 = ptrtoint %struct.NODE** %storemerge.in.i to i64
 	%tmp2 = lshr i64 %tmp1, 3
 	%tmp3 = and i64 %tmp2, 2147483647
-	%tmp4 = getelementptr %struct.HashEntry* %tmp, i64 %tmp3, i32 0, i32 1
-	%tmp7 = load i8** %tmp4, align 8
-	%tmp8 = getelementptr %struct.NODE* %storemerge.i, i64 0, i32 2
+	%tmp4 = getelementptr %struct.HashEntry, %struct.HashEntry* %tmp, i64 %tmp3, i32 0, i32 1
+	%tmp7 = load i8*, i8** %tmp4, align 8
+	%tmp8 = getelementptr %struct.NODE, %struct.NODE* %storemerge.i, i64 0, i32 2
 	%tmp9 = bitcast %struct.anon* %tmp8 to %struct.NODE***
-	%tmp11 = load %struct.NODE*** %tmp9, align 8
+	%tmp11 = load %struct.NODE**, %struct.NODE*** %tmp9, align 8
 	%tmp12 = ptrtoint %struct.NODE** %tmp11 to i64
 	%tmp13 = lshr i64 %tmp12, 3
 	%tmp14 = and i64 %tmp13, 2147483647
-	%tmp15 = getelementptr %struct.HashEntry* %tmp, i64 %tmp14, i32 0, i32 1
+	%tmp15 = getelementptr %struct.HashEntry, %struct.HashEntry* %tmp, i64 %tmp14, i32 0, i32 1
 	call fastcc void @xlprint(i8** %tmp4, i8* %tmp7, i8** %tmp15)
 	ret void
 }
diff --git a/test/CodeGen/X86/pr2924.ll b/test/CodeGen/X86/pr2924.ll
index b9e8dc1740d9..14e9fc49a2aa 100644
--- a/test/CodeGen/X86/pr2924.ll
+++ b/test/CodeGen/X86/pr2924.ll
@@ -7,18 +7,18 @@ target triple = "i686-pc-linux-gnu"
 
 define x86_stdcallcc { i32, i8* } @_D3std6string7toupperFAaZAa({ i32, i8* } %s) {
 entry_std.string.toupper:
-        %tmp58 = load i32* null
+        %tmp58 = load i32, i32* null
         %tmp59 = icmp eq i32 %tmp58, 0
-        %r.val = load { i32, i8* }* null, align 8
+        %r.val = load { i32, i8* }, { i32, i8* }* null, align 8
         %condtmp.0 = select i1 %tmp59, { i32, i8* } undef, { i32, i8* } %r.val 
 
         ret { i32, i8* } %condtmp.0
 }
 define { } @empty({ } %s) {
 entry_std.string.toupper:
-        %tmp58 = load i32* null
+        %tmp58 = load i32, i32* null
         %tmp59 = icmp eq i32 %tmp58, 0
-        %r.val = load { }* null, align 8
+        %r.val = load { }, { }* null, align 8
         %condtmp.0 = select i1 %tmp59, { } undef, { } %r.val
         ret { } %condtmp.0
 }
diff --git a/test/CodeGen/X86/pr2982.ll b/test/CodeGen/X86/pr2982.ll
index 3f9a5953153b..b7902b8cc3a0 100644
--- a/test/CodeGen/X86/pr2982.ll
+++ b/test/CodeGen/X86/pr2982.ll
@@ -12,15 +12,15 @@ declare i32 @rshift_u_u(...)
 
 define void @bar() nounwind {
 entry:
-        %0 = load i32* @g_279, align 4          ; <i32> [#uses=1]
+        %0 = load i32, i32* @g_279, align 4          ; <i32> [#uses=1]
         %1 = shl i32 %0, 1              ; <i32> [#uses=1]
         %2 = and i32 %1, 2              ; <i32> [#uses=1]
-        %3 = load i32* @g_265, align 4          ; <i32> [#uses=1]
-        %4 = load i8* @g_3, align 1             ; <i8> [#uses=1]
+        %3 = load i32, i32* @g_265, align 4          ; <i32> [#uses=1]
+        %4 = load i8, i8* @g_3, align 1             ; <i8> [#uses=1]
         %5 = sext i8 %4 to i32          ; <i32> [#uses=1]
         %6 = add i32 %2, %3             ; <i32> [#uses=1]
         %7 = add i32 %6, %5             ; <i32> [#uses=1]
-        %8 = tail call i32 (...)* @rshift_u_u(i32 %7, i32 0) nounwind          
+        %8 = tail call i32 (...) @rshift_u_u(i32 %7, i32 0) nounwind          
 ; <i32> [#uses=0]
         ret void
 }
diff --git a/test/CodeGen/X86/pr3154.ll b/test/CodeGen/X86/pr3154.ll
index 18df97c72302..5da88403802e 100644
--- a/test/CodeGen/X86/pr3154.ll
+++ b/test/CodeGen/X86/pr3154.ll
@@ -8,7 +8,7 @@ entry:
 	%0 = add i32 %len, 2		; <i32> [#uses=1]
 	%1 = add i32 %0, %lag		; <i32> [#uses=1]
 	%2 = alloca double, i32 %1		; <double*> [#uses=2]
-	%3 = getelementptr double* %2, i32 %lag		; <double*> [#uses=2]
+	%3 = getelementptr double, double* %2, i32 %lag		; <double*> [#uses=2]
 	%4 = ptrtoint double* %3 to i32		; <i32> [#uses=1]
 	%5 = and i32 %4, 8		; <i32> [#uses=1]
 	%6 = icmp eq i32 %5, 0		; <i1> [#uses=1]
@@ -16,7 +16,7 @@ entry:
 
 bb:		; preds = %entry
 	%.sum = add i32 %lag, 1		; <i32> [#uses=1]
-	%7 = getelementptr double* %2, i32 %.sum		; <double*> [#uses=1]
+	%7 = getelementptr double, double* %2, i32 %.sum		; <double*> [#uses=1]
 	br label %bb19
 
 bb19:		; preds = %bb, %entry
@@ -32,8 +32,8 @@ bb19:		; preds = %bb, %entry
 	call void asm sideeffect "movsd   $0,     %xmm7                \0A\09movapd  ff_pd_1, %xmm6     \0A\09movapd  ff_pd_2, %xmm5     \0A\09movlhps %xmm7, %xmm7                \0A\09subpd   %xmm5, %xmm7                \0A\09addsd   %xmm6, %xmm7                \0A\09", "*m,~{dirflag},~{fpsr},~{flags}"(double* %c) nounwind
 	%15 = and i32 %len, 1		; <i32> [#uses=1]
 	%toBool = icmp eq i32 %15, 0		; <i1> [#uses=1]
-	%16 = getelementptr double* %data15.0, i32 %11		; <double*> [#uses=2]
-	%17 = getelementptr i32* %data, i32 %11		; <i32*> [#uses=2]
+	%16 = getelementptr double, double* %data15.0, i32 %11		; <double*> [#uses=2]
+	%17 = getelementptr i32, i32* %data, i32 %11		; <i32*> [#uses=2]
 	br i1 %toBool, label %bb22, label %bb20
 
 bb20:		; preds = %bb19
@@ -51,14 +51,14 @@ bb28.preheader:		; preds = %bb22, %bb20
 bb27:		; preds = %bb27, %bb28.preheader
 	%j4.042 = phi i32 [ 0, %bb28.preheader ], [ %indvar.next45, %bb27 ]		; <i32> [#uses=2]
 	%19 = sub i32 %j4.042, %lag		; <i32> [#uses=1]
-	%20 = getelementptr double* %data15.0, i32 %19		; <double*> [#uses=1]
+	%20 = getelementptr double, double* %data15.0, i32 %19		; <double*> [#uses=1]
 	store double 0.000000e+00, double* %20, align 8
 	%indvar.next45 = add i32 %j4.042, 1		; <i32> [#uses=2]
 	%exitcond = icmp eq i32 %indvar.next45, %lag		; <i1> [#uses=1]
 	br i1 %exitcond, label %bb29, label %bb27
 
 bb29:		; preds = %bb27, %bb28.preheader
-	%21 = getelementptr double* %data15.0, i32 %len		; <double*> [#uses=3]
+	%21 = getelementptr double, double* %data15.0, i32 %len		; <double*> [#uses=3]
 	store double 0.000000e+00, double* %21, align 8
 	br i1 %18, label %bb.nph, label %bb37
 
@@ -77,18 +77,18 @@ bb30:		; preds = %bb35, %bb.nph
 bb31:		; preds = %bb30
 	%26 = add i32 %j4.141, 2		; <i32> [#uses=2]
 	%.sum38 = sub i32 %len, %j4.141		; <i32> [#uses=1]
-	%27 = getelementptr double* %data15.0, i32 %.sum38		; <double*> [#uses=1]
-	%28 = getelementptr double* %autoc, i32 %j4.141		; <double*> [#uses=1]
-	%29 = getelementptr double* %autoc, i32 %25		; <double*> [#uses=1]
-	%30 = getelementptr double* %autoc, i32 %26		; <double*> [#uses=1]
+	%27 = getelementptr double, double* %data15.0, i32 %.sum38		; <double*> [#uses=1]
+	%28 = getelementptr double, double* %autoc, i32 %j4.141		; <double*> [#uses=1]
+	%29 = getelementptr double, double* %autoc, i32 %25		; <double*> [#uses=1]
+	%30 = getelementptr double, double* %autoc, i32 %26		; <double*> [#uses=1]
 	%asmtmp32 = call i32 asm sideeffect "movsd    ff_pd_1, %xmm0 \0A\09movsd    ff_pd_1, %xmm1 \0A\09movsd    ff_pd_1, %xmm2 \0A\091:                                 \0A\09movapd   ($4,$0), %xmm3           \0A\09movupd -8($5,$0), %xmm4           \0A\09movapd   ($5,$0), %xmm5           \0A\09mulpd     %xmm3, %xmm4           \0A\09mulpd     %xmm3, %xmm5           \0A\09mulpd -16($5,$0), %xmm3           \0A\09addpd     %xmm4, %xmm1           \0A\09addpd     %xmm5, %xmm0           \0A\09addpd     %xmm3, %xmm2           \0A\09add       $$16,    $0               \0A\09jl 1b                              \0A\09movhlps   %xmm0, %xmm3           \0A\09movhlps   %xmm1, %xmm4           \0A\09movhlps   %xmm2, %xmm5           \0A\09addsd     %xmm3, %xmm0           \0A\09addsd     %xmm4, %xmm1           \0A\09addsd     %xmm5, %xmm2           \0A\09movsd     %xmm0, $1               \0A\09movsd     %xmm1, $2               \0A\09movsd     %xmm2, $3               \0A\09", "=&r,=*m,=*m,=*m,r,r,0,~{dirflag},~{fpsr},~{flags}"(double* %28, double* %29, double* %30, double* %21, double* %27, i32 %22) nounwind		; <i32> [#uses=0]
 	br label %bb35
 
 bb33:		; preds = %bb30
 	%.sum39 = sub i32 %len, %j4.141		; <i32> [#uses=1]
-	%31 = getelementptr double* %data15.0, i32 %.sum39		; <double*> [#uses=1]
-	%32 = getelementptr double* %autoc, i32 %j4.141		; <double*> [#uses=1]
-	%33 = getelementptr double* %autoc, i32 %25		; <double*> [#uses=1]
+	%31 = getelementptr double, double* %data15.0, i32 %.sum39		; <double*> [#uses=1]
+	%32 = getelementptr double, double* %autoc, i32 %j4.141		; <double*> [#uses=1]
+	%33 = getelementptr double, double* %autoc, i32 %25		; <double*> [#uses=1]
 	%asmtmp34 = call i32 asm sideeffect "movsd    ff_pd_1, %xmm0 \0A\09movsd    ff_pd_1, %xmm1 \0A\091:                                 \0A\09movapd   ($3,$0), %xmm3           \0A\09movupd -8($4,$0), %xmm4           \0A\09mulpd     %xmm3, %xmm4           \0A\09mulpd    ($4,$0), %xmm3           \0A\09addpd     %xmm4, %xmm1           \0A\09addpd     %xmm3, %xmm0           \0A\09add       $$16,    $0               \0A\09jl 1b                              \0A\09movhlps   %xmm0, %xmm3           \0A\09movhlps   %xmm1, %xmm4           \0A\09addsd     %xmm3, %xmm0           \0A\09addsd     %xmm4, %xmm1           \0A\09movsd     %xmm0, $1               \0A\09movsd     %xmm1, $2               \0A\09", "=&r,=*m,=*m,r,r,0,~{dirflag},~{fpsr},~{flags}"(double* %32, double* %33, double* %21, double* %31, i32 %22) nounwind		; <i32> [#uses=0]
 	%.pre = add i32 %j4.141, 2		; <i32> [#uses=1]
 	br label %bb35
diff --git a/test/CodeGen/X86/pr3216.ll b/test/CodeGen/X86/pr3216.ll
index a4a48210d358..23dcf5693cd0 100644
--- a/test/CodeGen/X86/pr3216.ll
+++ b/test/CodeGen/X86/pr3216.ll
@@ -8,7 +8,7 @@ define i32 @main() nounwind {
 ; CHECK: sar{{.}} $5
 ; CHECK: ret
 
-   %tmp = load i8* @foo
+   %tmp = load i8, i8* @foo
    %bf.lo = lshr i8 %tmp, 5
    %bf.lo.cleared = and i8 %bf.lo, 7
    %1 = shl i8 %bf.lo.cleared, 5
diff --git a/test/CodeGen/X86/pr3241.ll b/test/CodeGen/X86/pr3241.ll
index 2f7917b77c39..f89634d5b82a 100644
--- a/test/CodeGen/X86/pr3241.ll
+++ b/test/CodeGen/X86/pr3241.ll
@@ -9,7 +9,7 @@ entry:
 	%t1 = call i32 @safe_add_macro_uint32_t_u_u() nounwind
 	%t2 = icmp sgt i32 %t1, 0
 	%t3 = zext i1 %t2 to i32
-	%t4 = load i32* @g_620, align 4
+	%t4 = load i32, i32* @g_620, align 4
 	%t5 = icmp eq i32 %t3, %t4
 	%t6 = xor i32 %p_21, 1
 	%t7 = call i32 @func_55(i32 %t6) nounwind
diff --git a/test/CodeGen/X86/pr3244.ll b/test/CodeGen/X86/pr3244.ll
index 2598c2f976b2..c6419d8ce768 100644
--- a/test/CodeGen/X86/pr3244.ll
+++ b/test/CodeGen/X86/pr3244.ll
@@ -6,11 +6,11 @@
 
 define i32 @func_42(i32 %p_43, i32 %p_44, i32 %p_45, i32 %p_46) nounwind {
 entry:
-        %0 = load i16* @g_62, align 2           ; <i16> [#uses=1]
-        %1 = load i32* @g_487, align 4          ; <i32> [#uses=1]
+        %0 = load i16, i16* @g_62, align 2           ; <i16> [#uses=1]
+        %1 = load i32, i32* @g_487, align 4          ; <i32> [#uses=1]
         %2 = trunc i16 %0 to i8         ; <i8> [#uses=1]
         %3 = trunc i32 %1 to i8         ; <i8> [#uses=1]
-        %4 = tail call i32 (...)* @func_7(i64 -4455561449541442965, i32 1)
+        %4 = tail call i32 (...) @func_7(i64 -4455561449541442965, i32 1)
 nounwind             ; <i32> [#uses=1]
         %5 = trunc i32 %4 to i8         ; <i8> [#uses=1]
         %6 = mul i8 %3, %2              ; <i8> [#uses=1]
diff --git a/test/CodeGen/X86/pr3250.ll b/test/CodeGen/X86/pr3250.ll
index cccbf54bcc6b..4ab989eaf77f 100644
--- a/test/CodeGen/X86/pr3250.ll
+++ b/test/CodeGen/X86/pr3250.ll
@@ -5,7 +5,7 @@ declare i32 @safe_sub_func_short_u_u(i16 signext, i16 signext) nounwind
 
 define i32 @func_106(i32 %p_107) nounwind {
 entry:
-        %0 = tail call i32 (...)* @safe_div_(i32 %p_107, i32 1) nounwind       
+        %0 = tail call i32 (...) @safe_div_(i32 %p_107, i32 1) nounwind       
         ; <i32> [#uses=1]
         %1 = lshr i32 %0, -9            ; <i32> [#uses=1]
         %2 = trunc i32 %1 to i16                ; <i16> [#uses=1]
diff --git a/test/CodeGen/X86/pr3317.ll b/test/CodeGen/X86/pr3317.ll
index d83daf01d3b0..cab8ae6b73fd 100644
--- a/test/CodeGen/X86/pr3317.ll
+++ b/test/CodeGen/X86/pr3317.ll
@@ -20,8 +20,8 @@ declare void @jnjvmNullPointerException()
 
 define i32 @JnJVM_java_rmi_activation_ActivationGroupID_hashCode__(%JavaObject* nocapture) nounwind {
 start:
-        %1 = getelementptr %JavaObject* %0, i64 1, i32 1                ; <%JavaCommonClass**> [#uses=1]
-        %2 = load %JavaCommonClass** %1         ; <%JavaCommonClass*> [#uses=4]
+        %1 = getelementptr %JavaObject, %JavaObject* %0, i64 1, i32 1                ; <%JavaCommonClass**> [#uses=1]
+        %2 = load %JavaCommonClass*, %JavaCommonClass** %1         ; <%JavaCommonClass*> [#uses=4]
         %3 = icmp eq %JavaCommonClass* %2, null         ; <i1> [#uses=1]
         br i1 %3, label %verifyNullExit1, label %verifyNullCont2
 
@@ -31,14 +31,14 @@ verifyNullExit1:                ; preds = %start
 
 verifyNullCont2:                ; preds = %start
         %4 = bitcast %JavaCommonClass* %2 to { %JavaObject, i16, i32, i64 }*            ; <{ %JavaObject, i16, i32, i64 }*> [#uses=1]
-        %5 = getelementptr { %JavaObject, i16, i32, i64 }* %4, i64 0, i32 2             ; <i32*> [#uses=1]
-        %6 = load i32* %5               ; <i32> [#uses=1]
-        %7 = getelementptr %JavaCommonClass* %2, i64 0, i32 4           ; <%JavaClass***> [#uses=1]
+        %5 = getelementptr { %JavaObject, i16, i32, i64 }, { %JavaObject, i16, i32, i64 }* %4, i64 0, i32 2             ; <i32*> [#uses=1]
+        %6 = load i32, i32* %5               ; <i32> [#uses=1]
+        %7 = getelementptr %JavaCommonClass, %JavaCommonClass* %2, i64 0, i32 4           ; <%JavaClass***> [#uses=1]
         %8 = bitcast %JavaClass*** %7 to i64*           ; <i64*> [#uses=1]
-        %9 = load i64* %8               ; <i64> [#uses=1]
+        %9 = load i64, i64* %8               ; <i64> [#uses=1]
         %10 = trunc i64 %9 to i32               ; <i32> [#uses=1]
-        %11 = getelementptr %JavaCommonClass* %2, i64 0, i32 3          ; <i16*> [#uses=1]
-        %12 = load i16* %11             ; <i16> [#uses=1]
+        %11 = getelementptr %JavaCommonClass, %JavaCommonClass* %2, i64 0, i32 3          ; <i16*> [#uses=1]
+        %12 = load i16, i16* %11             ; <i16> [#uses=1]
         %13 = sext i16 %12 to i32               ; <i32> [#uses=1]
         %14 = xor i32 %10, %6           ; <i32> [#uses=1]
         %15 = xor i32 %14, %13          ; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/pr3366.ll b/test/CodeGen/X86/pr3366.ll
index 1127b6093215..b89a69ab7d41 100644
--- a/test/CodeGen/X86/pr3366.ll
+++ b/test/CodeGen/X86/pr3366.ll
@@ -3,7 +3,7 @@
 
 define void @_ada_c34002a() nounwind {
 entry:
-  %0 = load i8* null, align 1
+  %0 = load i8, i8* null, align 1
   %1 = sdiv i8 90, %0
   %2 = icmp ne i8 %1, 3
   %3 = zext i1 %2 to i8
diff --git a/test/CodeGen/X86/pr3457.ll b/test/CodeGen/X86/pr3457.ll
index 7264bcd12c42..d4c0020cb856 100644
--- a/test/CodeGen/X86/pr3457.ll
+++ b/test/CodeGen/X86/pr3457.ll
@@ -4,8 +4,8 @@
 
 define void @foo(double* nocapture %P) nounwind {
 entry:
-	%0 = tail call double (...)* @test() nounwind		; <double> [#uses=2]
-	%1 = tail call double (...)* @test() nounwind		; <double> [#uses=2]
+	%0 = tail call double (...) @test() nounwind		; <double> [#uses=2]
+	%1 = tail call double (...) @test() nounwind		; <double> [#uses=2]
 	%2 = fmul double %0, %0		; <double> [#uses=1]
 	%3 = fmul double %1, %1		; <double> [#uses=1]
 	%4 = fadd double %2, %3		; <double> [#uses=1]
diff --git a/test/CodeGen/X86/pr3522.ll b/test/CodeGen/X86/pr3522.ll
index 9f8dc0370668..867f2828d4d9 100644
--- a/test/CodeGen/X86/pr3522.ll
+++ b/test/CodeGen/X86/pr3522.ll
@@ -9,7 +9,7 @@ define void @_ada_c34018a() {
 entry:
 	%0 = tail call i32 @report__ident_int(i32 90)		; <i32> [#uses=1]
 	%1 = trunc i32 %0 to i8		; <i8> [#uses=1]
-	invoke void @__gnat_rcheck_12(i8* getelementptr ([13 x i8]* @.str, i32 0, i32 0), i32 32) noreturn
+	invoke void @__gnat_rcheck_12(i8* getelementptr ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 32) noreturn
 			to label %invcont unwind label %lpad
 
 invcont:		; preds = %entry
diff --git a/test/CodeGen/X86/pr5145.ll b/test/CodeGen/X86/pr5145.ll
index 32a797ba138a..4dee5f8d7d2a 100644
--- a/test/CodeGen/X86/pr5145.ll
+++ b/test/CodeGen/X86/pr5145.ll
@@ -7,29 +7,25 @@ define void @atomic_maxmin_i8() {
 ; CHECK: [[LABEL1:\.?LBB[0-9]+_[0-9]+]]:
 ; CHECK: movsbl
 ; CHECK: cmpl
-; CHECK: lock
-; CHECK-NEXT: cmpxchgb
+; CHECK: lock cmpxchgb
 ; CHECK: jne [[LABEL1]]
   %2 = atomicrmw min  i8* @sc8, i8 6 acquire
 ; CHECK: [[LABEL3:\.?LBB[0-9]+_[0-9]+]]:
 ; CHECK: movsbl
 ; CHECK: cmpl
-; CHECK: lock
-; CHECK-NEXT: cmpxchgb
+; CHECK: lock cmpxchgb
 ; CHECK: jne [[LABEL3]]
   %3 = atomicrmw umax i8* @sc8, i8 7 acquire
 ; CHECK: [[LABEL5:\.?LBB[0-9]+_[0-9]+]]:
 ; CHECK: movzbl
 ; CHECK: cmpl
-; CHECK: lock
-; CHECK-NEXT: cmpxchgb
+; CHECK: lock cmpxchgb
 ; CHECK: jne [[LABEL5]]
   %4 = atomicrmw umin i8* @sc8, i8 8 acquire
 ; CHECK: [[LABEL7:\.?LBB[0-9]+_[0-9]+]]:
 ; CHECK: movzbl
 ; CHECK: cmpl
-; CHECK: lock
-; CHECK-NEXT: cmpxchgb
+; CHECK: lock cmpxchgb
 ; CHECK: jne [[LABEL7]]
   ret void
 }
diff --git a/test/CodeGen/X86/pr9127.ll b/test/CodeGen/X86/pr9127.ll
index ba92c77e22bd..33f9ace33ff5 100644
--- a/test/CodeGen/X86/pr9127.ll
+++ b/test/CodeGen/X86/pr9127.ll
@@ -3,7 +3,7 @@
 
 define i8 @foobar(double %d, double* %x) {
 entry:
-  %tmp2 = load double* %x, align 8
+  %tmp2 = load double, double* %x, align 8
   %cmp = fcmp oeq double %tmp2, %d
   %conv3 = zext i1 %cmp to i8
   ret i8 %conv3
diff --git a/test/CodeGen/X86/pre-ra-sched.ll b/test/CodeGen/X86/pre-ra-sched.ll
index bb4c1269b7cf..f8e196ba5808 100644
--- a/test/CodeGen/X86/pre-ra-sched.ll
+++ b/test/CodeGen/X86/pre-ra-sched.ll
@@ -14,33 +14,33 @@
 ; CHECK-NOT: Repushing
 ; CHECK: *** Final schedule
 define i32 @test(i8* %pin) #0 {
-  %g0 = getelementptr inbounds i8* %pin, i64 0
-  %l0 = load i8* %g0, align 1
+  %g0 = getelementptr inbounds i8, i8* %pin, i64 0
+  %l0 = load i8, i8* %g0, align 1
 
-  %g1a = getelementptr inbounds i8* %pin, i64 1
-  %l1a = load i8* %g1a, align 1
+  %g1a = getelementptr inbounds i8, i8* %pin, i64 1
+  %l1a = load i8, i8* %g1a, align 1
   %z1a = zext i8 %l1a to i32
-  %g1b = getelementptr inbounds i8* %pin, i64 2
-  %l1b = load i8* %g1b, align 1
+  %g1b = getelementptr inbounds i8, i8* %pin, i64 2
+  %l1b = load i8, i8* %g1b, align 1
   %z1b = zext i8 %l1b to i32
   %c1 = icmp ne i8 %l0, 0
   %x1 = xor i32 %z1a, %z1b
   %s1 = select i1 %c1, i32 %z1a, i32 %x1
 
-  %g2a = getelementptr inbounds i8* %pin, i64 3
-  %l2a = load i8* %g2a, align 1
+  %g2a = getelementptr inbounds i8, i8* %pin, i64 3
+  %l2a = load i8, i8* %g2a, align 1
   %z2a = zext i8 %l2a to i32
-  %g2b = getelementptr inbounds i8* %pin, i64 4
-  %l2b = load i8* %g2b, align 1
+  %g2b = getelementptr inbounds i8, i8* %pin, i64 4
+  %l2b = load i8, i8* %g2b, align 1
   %z2b = zext i8 %l2b to i32
   %x2 = xor i32 %z2a, %z2b
   %s2 = select i1 %c1, i32 %z2a, i32 %x2
 
-  %g3a = getelementptr inbounds i8* %pin, i64 5
-  %l3a = load i8* %g3a, align 1
+  %g3a = getelementptr inbounds i8, i8* %pin, i64 5
+  %l3a = load i8, i8* %g3a, align 1
   %z3a = zext i8 %l3a to i32
-  %g3b = getelementptr inbounds i8* %pin, i64 6
-  %l3b = load i8* %g3b, align 1
+  %g3b = getelementptr inbounds i8, i8* %pin, i64 6
+  %l3b = load i8, i8* %g3b, align 1
   %z3b = zext i8 %l3b to i32
   %x3 = xor i32 %z3a, %z3b
   %s3 = select i1 %c1, i32 %z3a, i32 %x3
diff --git a/test/CodeGen/X86/private-2.ll b/test/CodeGen/X86/private-2.ll
index cf2d74119374..21b6b3aff2d2 100644
--- a/test/CodeGen/X86/private-2.ll
+++ b/test/CodeGen/X86/private-2.ll
@@ -9,7 +9,7 @@
 
 define internal i32* @"\01-[Example1 whatever]"() nounwind optsize ssp {
 entry:
-	%0 = getelementptr %struct.A* @"_ZZ20-[Example1 whatever]E4C.91", i64 0, i32 0		; <i32**> [#uses=1]
-	%1 = load i32** %0, align 8		; <i32*> [#uses=1]
+	%0 = getelementptr %struct.A, %struct.A* @"_ZZ20-[Example1 whatever]E4C.91", i64 0, i32 0		; <i32**> [#uses=1]
+	%1 = load i32*, i32** %0, align 8		; <i32*> [#uses=1]
 	ret i32* %1
 }
diff --git a/test/CodeGen/X86/private.ll b/test/CodeGen/X86/private.ll
index c02d19319a49..4b936d2323ec 100644
--- a/test/CodeGen/X86/private.ll
+++ b/test/CodeGen/X86/private.ll
@@ -10,7 +10,7 @@ define private void @foo() {
 
 define i32 @bar() {
         call void @foo()
-	%1 = load i32* @baz, align 4
+	%1 = load i32, i32* @baz, align 4
         ret i32 %1
 
 ; CHECK-LABEL: bar:
diff --git a/test/CodeGen/X86/promote-assert-zext.ll b/test/CodeGen/X86/promote-assert-zext.ll
index b582806c96a4..506748312052 100644
--- a/test/CodeGen/X86/promote-assert-zext.ll
+++ b/test/CodeGen/X86/promote-assert-zext.ll
@@ -11,7 +11,7 @@ target triple = "x86_64-apple-darwin11"
 
 define i64 @_ZL5matchPKtPKhiR9MatchData(i8* %tmp13) nounwind {
 entry:
-  %tmp14 = load i8* %tmp13, align 1
+  %tmp14 = load i8, i8* %tmp13, align 1
   %tmp17 = zext i8 %tmp14 to i16
   br label %bb341
 
diff --git a/test/CodeGen/X86/promote-trunc.ll b/test/CodeGen/X86/promote-trunc.ll
index 40a58b073924..a20557a1fef2 100644
--- a/test/CodeGen/X86/promote-trunc.ll
+++ b/test/CodeGen/X86/promote-trunc.ll
@@ -1,9 +1,9 @@
 ; RUN: llc < %s -march=x86-64
 
 define<4 x i8> @func_8_64() {
-  %F = load <4 x i64>* undef
+  %F = load <4 x i64>, <4 x i64>* undef
   %G = trunc <4 x i64> %F to <4 x i8>
-  %H = load <4 x i64>* undef
+  %H = load <4 x i64>, <4 x i64>* undef
   %Y = trunc <4 x i64> %H to <4 x i8>
   %T = add <4 x i8> %Y, %G
   ret <4 x i8> %T
diff --git a/test/CodeGen/X86/promote.ll b/test/CodeGen/X86/promote.ll
index 283f48cd37b4..38cdc14b380f 100644
--- a/test/CodeGen/X86/promote.ll
+++ b/test/CodeGen/X86/promote.ll
@@ -9,7 +9,7 @@ define i32 @mul_f(<4 x i8>* %A) {
 entry:
 ; CHECK: pmul
 ; CHECK-NOT: mulb
-  %0 = load <4 x i8>* %A, align 8
+  %0 = load <4 x i8>, <4 x i8>* %A, align 8
   %mul = mul <4 x i8> %0, %0
   store <4 x i8> %mul, <4 x i8>* undef
   ret i32 0
@@ -23,7 +23,7 @@ entry:
 ; CHECK: pmovzxbd
 ; CHECK: paddd
 ; CHECK: pshufb
-  %0 = load <4 x i8>* %A, align 8
+  %0 = load <4 x i8>, <4 x i8>* %A, align 8
   %add = add <4 x i8> %0, %0
   store <4 x i8> %add, <4 x i8>* undef
   ret i32 0
diff --git a/test/CodeGen/X86/pshufb-mask-comments.ll b/test/CodeGen/X86/pshufb-mask-comments.ll
index ca5a02ce8d3a..105a035be592 100644
--- a/test/CodeGen/X86/pshufb-mask-comments.ll
+++ b/test/CodeGen/X86/pshufb-mask-comments.ll
@@ -41,10 +41,10 @@ define <16 x i8> @test5() {
 ; CHECK-LABEL: test5
 ; CHECK: pshufb {{.*}}
   store <2 x i64> <i64 1, i64 0>, <2 x i64>* undef, align 16
-  %l = load <2 x i64>* undef, align 16
+  %l = load <2 x i64>, <2 x i64>* undef, align 16
   %shuffle = shufflevector <2 x i64> %l, <2 x i64> undef, <2 x i32> zeroinitializer
   store <2 x i64> %shuffle, <2 x i64>* undef, align 16
-  %1 = load <16 x i8>* undef, align 16
+  %1 = load <16 x i8>, <16 x i8>* undef, align 16
   %2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> undef, <16 x i8> %1)
   ret <16 x i8> %2
 }
diff --git a/test/CodeGen/X86/psubus.ll b/test/CodeGen/X86/psubus.ll
index aff4afbd2e35..4b83b55997e2 100644
--- a/test/CodeGen/X86/psubus.ll
+++ b/test/CodeGen/X86/psubus.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=core2 < %s | FileCheck %s -check-prefix=SSE2
+; RUN: llc -mcpu=core2 < %s | FileCheck %s -check-prefix=SSSE3
 ; RUN: llc -mcpu=corei7-avx < %s | FileCheck %s -check-prefix=AVX1
 ; RUN: llc -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX2
 
@@ -7,334 +7,344 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 define void @test1(i16* nocapture %head) nounwind {
 vector.ph:
-  br label %vector.body
-
-vector.body:                                      ; preds = %vector.body, %vector.ph
-  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %0 = getelementptr inbounds i16* %head, i64 %index
+  %0 = getelementptr inbounds i16, i16* %head, i64 0
   %1 = bitcast i16* %0 to <8 x i16>*
-  %2 = load <8 x i16>* %1, align 2
+  %2 = load <8 x i16>, <8 x i16>* %1, align 2
   %3 = icmp slt <8 x i16> %2, zeroinitializer
   %4 = xor <8 x i16> %2, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768>
   %5 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> zeroinitializer
   store <8 x i16> %5, <8 x i16>* %1, align 2
-  %index.next = add i64 %index, 8
-  %6 = icmp eq i64 %index.next, 16384
-  br i1 %6, label %for.end, label %vector.body
-
-for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: @test1
-; SSE2: psubusw LCPI0_0(%rip), %xmm0
+; SSSE3: @test1
+; SSSE3:      # BB#0:
+; SSSE3-NEXT: movdqu (%rdi), %xmm0
+; SSSE3-NEXT: psubusw LCPI0_0(%rip), %xmm0
+; SSSE3-NEXT: movdqu %xmm0, (%rdi)
+; SSSE3-NEXT: retq
 
 ; AVX1: @test1
-; AVX1: vpsubusw LCPI0_0(%rip), %xmm0, %xmm0
+; AVX1:      # BB#0:
+; AVX1-NEXT: vmovdqu (%rdi), %xmm0
+; AVX1-NEXT: vpsubusw LCPI0_0(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vmovdqu %xmm0, (%rdi)
+; AVX1-NEXT: retq
 
 ; AVX2: @test1
-; AVX2: vpsubusw LCPI0_0(%rip), %xmm0, %xmm0
+; AVX2:      # BB#0:
+; AVX2-NEXT: vmovdqu (%rdi), %xmm0
+; AVX2-NEXT: vpsubusw LCPI0_0(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vmovdqu %xmm0, (%rdi)
+; AVX2-NEXT: retq
 }
 
 define void @test2(i16* nocapture %head) nounwind {
 vector.ph:
-  br label %vector.body
-
-vector.body:                                      ; preds = %vector.body, %vector.ph
-  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %0 = getelementptr inbounds i16* %head, i64 %index
+  %0 = getelementptr inbounds i16, i16* %head, i64 0
   %1 = bitcast i16* %0 to <8 x i16>*
-  %2 = load <8 x i16>* %1, align 2
+  %2 = load <8 x i16>, <8 x i16>* %1, align 2
   %3 = icmp ugt <8 x i16> %2, <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>
   %4 = add <8 x i16> %2, <i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767>
   %5 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> zeroinitializer
   store <8 x i16> %5, <8 x i16>* %1, align 2
-  %index.next = add i64 %index, 8
-  %6 = icmp eq i64 %index.next, 16384
-  br i1 %6, label %for.end, label %vector.body
-
-for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: @test2
-; SSE2: psubusw LCPI1_0(%rip), %xmm0
+; SSSE3: @test2
+; SSSE3:      # BB#0:
+; SSSE3-NEXT: movdqu (%rdi), %xmm0
+; SSSE3-NEXT: psubusw LCPI1_0(%rip), %xmm0
+; SSSE3-NEXT: movdqu %xmm0, (%rdi)
+; SSSE3-NEXT: retq
 
 ; AVX1: @test2
-; AVX1: vpsubusw LCPI1_0(%rip), %xmm0, %xmm0
+; AVX1:      # BB#0:
+; AVX1-NEXT: vmovdqu (%rdi), %xmm0
+; AVX1-NEXT: vpsubusw LCPI1_0(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vmovdqu %xmm0, (%rdi)
+; AVX1-NEXT: retq
 
 ; AVX2: @test2
-; AVX2: vpsubusw LCPI1_0(%rip), %xmm0, %xmm0
+; AVX2:      # BB#0:
+; AVX2-NEXT: vmovdqu (%rdi), %xmm0
+; AVX2-NEXT: vpsubusw LCPI1_0(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vmovdqu %xmm0, (%rdi)
+; AVX2-NEXT: retq
 }
 
 define void @test3(i16* nocapture %head, i16 zeroext %w) nounwind {
 vector.ph:
   %0 = insertelement <8 x i16> undef, i16 %w, i32 0
   %broadcast15 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer
-  br label %vector.body
-
-vector.body:                                      ; preds = %vector.body, %vector.ph
-  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %1 = getelementptr inbounds i16* %head, i64 %index
+  %1 = getelementptr inbounds i16, i16* %head, i64 0
   %2 = bitcast i16* %1 to <8 x i16>*
-  %3 = load <8 x i16>* %2, align 2
+  %3 = load <8 x i16>, <8 x i16>* %2, align 2
   %4 = icmp ult <8 x i16> %3, %broadcast15
   %5 = sub <8 x i16> %3, %broadcast15
   %6 = select <8 x i1> %4, <8 x i16> zeroinitializer, <8 x i16> %5
   store <8 x i16> %6, <8 x i16>* %2, align 2
-  %index.next = add i64 %index, 8
-  %7 = icmp eq i64 %index.next, 16384
-  br i1 %7, label %for.end, label %vector.body
-
-for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: @test3
-; SSE2: psubusw %xmm0, %xmm1
+; SSSE3: @test3
+; SSSE3:      # BB#0:
+; SSSE3-NEXT: movd %esi, %xmm0
+; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
+; SSSE3-NEXT: movdqu (%rdi), %xmm1
+; SSSE3-NEXT: psubusw %xmm0, %xmm1
+; SSSE3-NEXT: movdqu %xmm1, (%rdi)
+; SSSE3-NEXT: retq
 
 ; AVX1: @test3
-; AVX1: vpsubusw %xmm0, %xmm1, %xmm1
+; AVX1:      # BB#0:
+; AVX1-NEXT: vmovd %esi, %xmm0
+; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
+; AVX1-NEXT: vmovdqu (%rdi), %xmm1
+; AVX1-NEXT: vpsubusw %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vmovdqu %xmm0, (%rdi)
+; AVX1-NEXT: retq
 
 ; AVX2: @test3
-; AVX2: vpsubusw %xmm0, %xmm1, %xmm1
+; AVX2:      # BB#0:
+; AVX2-NEXT: vmovd %esi, %xmm0
+; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
+; AVX2-NEXT: vmovdqu (%rdi), %xmm1
+; AVX2-NEXT: vpsubusw %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vmovdqu %xmm0, (%rdi)
+; AVX2-NEXT: retq
 }
 
 define void @test4(i8* nocapture %head) nounwind {
 vector.ph:
-  br label %vector.body
-
-vector.body:                                      ; preds = %vector.body, %vector.ph
-  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %0 = getelementptr inbounds i8* %head, i64 %index
+  %0 = getelementptr inbounds i8, i8* %head, i64 0
   %1 = bitcast i8* %0 to <16 x i8>*
-  %2 = load <16 x i8>* %1, align 1
+  %2 = load <16 x i8>, <16 x i8>* %1, align 1
   %3 = icmp slt <16 x i8> %2, zeroinitializer
   %4 = xor <16 x i8> %2, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
   %5 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> zeroinitializer
   store <16 x i8> %5, <16 x i8>* %1, align 1
-  %index.next = add i64 %index, 16
-  %6 = icmp eq i64 %index.next, 16384
-  br i1 %6, label %for.end, label %vector.body
-
-for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: @test4
-; SSE2: psubusb LCPI3_0(%rip), %xmm0
+; SSSE3: @test4
+; SSSE3:      # BB#0:
+; SSSE3-NEXT: movdqu (%rdi), %xmm0
+; SSSE3-NEXT: psubusb LCPI3_0(%rip), %xmm0
+; SSSE3-NEXT: movdqu %xmm0, (%rdi)
+; SSSE3-NEXT: retq
 
 ; AVX1: @test4
-; AVX1: vpsubusb LCPI3_0(%rip), %xmm0, %xmm0
+; AVX1:      # BB#0:
+; AVX1-NEXT: vmovdqu (%rdi), %xmm0
+; AVX1-NEXT: vpsubusb LCPI3_0(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vmovdqu %xmm0, (%rdi)
+; AVX1-NEXT: retq
 
 ; AVX2: @test4
-; AVX2: vpsubusb LCPI3_0(%rip), %xmm0, %xmm0
+; AVX2:      # BB#0:
+; AVX2-NEXT: vmovdqu (%rdi), %xmm0
+; AVX2-NEXT: vpsubusb LCPI3_0(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vmovdqu %xmm0, (%rdi)
+; AVX2-NEXT: retq
 }
 
 define void @test5(i8* nocapture %head) nounwind {
 vector.ph:
-  br label %vector.body
-
-vector.body:                                      ; preds = %vector.body, %vector.ph
-  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %0 = getelementptr inbounds i8* %head, i64 %index
+  %0 = getelementptr inbounds i8, i8* %head, i64 0
   %1 = bitcast i8* %0 to <16 x i8>*
-  %2 = load <16 x i8>* %1, align 1
+  %2 = load <16 x i8>, <16 x i8>* %1, align 1
   %3 = icmp ugt <16 x i8> %2, <i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126>
   %4 = add <16 x i8> %2, <i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127>
   %5 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> zeroinitializer
   store <16 x i8> %5, <16 x i8>* %1, align 1
-  %index.next = add i64 %index, 16
-  %6 = icmp eq i64 %index.next, 16384
-  br i1 %6, label %for.end, label %vector.body
-
-for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: @test5
-; SSE2: psubusb LCPI4_0(%rip), %xmm0
+; SSSE3: @test5
+; SSSE3:      # BB#0:
+; SSSE3-NEXT: movdqu (%rdi), %xmm0
+; SSSE3-NEXT: psubusb LCPI4_0(%rip), %xmm0
+; SSSE3-NEXT: movdqu %xmm0, (%rdi)
+; SSSE3-NEXT: retq
 
 ; AVX1: @test5
-; AVX1: vpsubusb LCPI4_0(%rip), %xmm0, %xmm0
+; AVX1:      # BB#0:
+; AVX1-NEXT: vmovdqu (%rdi), %xmm0
+; AVX1-NEXT: vpsubusb LCPI4_0(%rip), %xmm0
+; AVX1-NEXT: vmovdqu %xmm0, (%rdi)
+; AVX1-NEXT: retq
 
 ; AVX2: @test5
-; AVX2: vpsubusb LCPI4_0(%rip), %xmm0, %xmm0
+; AVX2:      # BB#0:
+; AVX2-NEXT: vmovdqu (%rdi), %xmm0
+; AVX2-NEXT: vpsubusb LCPI4_0(%rip), %xmm0
+; AVX2-NEXT: vmovdqu %xmm0, (%rdi)
+; AVX2-NEXT: retq
 }
 
 define void @test6(i8* nocapture %head, i8 zeroext %w) nounwind {
 vector.ph:
   %0 = insertelement <16 x i8> undef, i8 %w, i32 0
   %broadcast15 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer
-  br label %vector.body
-
-vector.body:                                      ; preds = %vector.body, %vector.ph
-  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %1 = getelementptr inbounds i8* %head, i64 %index
+  %1 = getelementptr inbounds i8, i8* %head, i64 0
   %2 = bitcast i8* %1 to <16 x i8>*
-  %3 = load <16 x i8>* %2, align 1
+  %3 = load <16 x i8>, <16 x i8>* %2, align 1
   %4 = icmp ult <16 x i8> %3, %broadcast15
   %5 = sub <16 x i8> %3, %broadcast15
   %6 = select <16 x i1> %4, <16 x i8> zeroinitializer, <16 x i8> %5
   store <16 x i8> %6, <16 x i8>* %2, align 1
-  %index.next = add i64 %index, 16
-  %7 = icmp eq i64 %index.next, 16384
-  br i1 %7, label %for.end, label %vector.body
-
-for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: @test6
-; SSE2: psubusb %xmm0, %xmm1
+; SSSE3: @test6
+; SSSE3:      # BB#0:
+; SSSE3-NEXT: movd %esi, %xmm0
+; SSSE3-NEXT: pxor %xmm1, %xmm1
+; SSSE3-NEXT: pshufb %xmm1, %xmm0
+; SSSE3-NEXT: movdqu (%rdi), %xmm1
+; SSSE3-NEXT: psubusb %xmm0, %xmm1
+; SSSE3-NEXT: movdqu %xmm1, (%rdi)
+; SSSE3-NEXT: retq
 
 ; AVX1: @test6
-; AVX1: vpsubusb %xmm0, %xmm1, %xmm1
+; AVX1:      # BB#0:
+; AVX1-NEXT: vmovd %esi, %xmm0
+; AVX1-NEXT: vpxor %xmm1, %xmm1
+; AVX1-NEXT: vpshufb %xmm1, %xmm0
+; AVX1-NEXT: vmovdqu (%rdi), %xmm1
+; AVX1-NEXT: vpsubusb %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vmovdqu %xmm0, (%rdi)
+; AVX1-NEXT: retq
 
 ; AVX2: @test6
-; AVX2: vpsubusb %xmm0, %xmm1, %xmm1
+; AVX2:      # BB#0:
+; AVX2-NEXT: vmovd %esi, %xmm0
+; AVX2-NEXT: vpbroadcastb %xmm0, %xmm0
+; AVX2-NEXT: vmovdqu (%rdi), %xmm1
+; AVX2-NEXT: vpsubusb %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vmovdqu %xmm0, (%rdi)
+; AVX2-NEXT: retq
 }
 
 define void @test7(i16* nocapture %head) nounwind {
 vector.ph:
-  br label %vector.body
-
-vector.body:                                      ; preds = %vector.body, %vector.ph
-  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %0 = getelementptr inbounds i16* %head, i64 %index
+  %0 = getelementptr inbounds i16, i16* %head, i64 0
   %1 = bitcast i16* %0 to <16 x i16>*
-  %2 = load <16 x i16>* %1, align 2
+  %2 = load <16 x i16>, <16 x i16>* %1, align 2
   %3 = icmp slt <16 x i16> %2, zeroinitializer
   %4 = xor <16 x i16> %2, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768>
   %5 = select <16 x i1> %3, <16 x i16> %4, <16 x i16> zeroinitializer
   store <16 x i16> %5, <16 x i16>* %1, align 2
-  %index.next = add i64 %index, 8
-  %6 = icmp eq i64 %index.next, 16384
-  br i1 %6, label %for.end, label %vector.body
-
-for.end:                                          ; preds = %vector.body
   ret void
 
 ; AVX2: @test7
-; AVX2: vpsubusw LCPI6_0(%rip), %ymm0, %ymm0
+; AVX2:      # BB#0:
+; AVX2-NEXT: vmovdqu (%rdi), %ymm0
+; AVX2-NEXT: vpsubusw LCPI6_0(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vmovdqu %ymm0, (%rdi)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
 }
 
 define void @test8(i16* nocapture %head) nounwind {
 vector.ph:
-  br label %vector.body
-
-vector.body:                                      ; preds = %vector.body, %vector.ph
-  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %0 = getelementptr inbounds i16* %head, i64 %index
+  %0 = getelementptr inbounds i16, i16* %head, i64 0
   %1 = bitcast i16* %0 to <16 x i16>*
-  %2 = load <16 x i16>* %1, align 2
+  %2 = load <16 x i16>, <16 x i16>* %1, align 2
   %3 = icmp ugt <16 x i16> %2, <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>
   %4 = add <16 x i16> %2, <i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767>
   %5 = select <16 x i1> %3, <16 x i16> %4, <16 x i16> zeroinitializer
   store <16 x i16> %5, <16 x i16>* %1, align 2
-  %index.next = add i64 %index, 8
-  %6 = icmp eq i64 %index.next, 16384
-  br i1 %6, label %for.end, label %vector.body
-
-for.end:                                          ; preds = %vector.body
   ret void
 
 ; AVX2: @test8
-; AVX2: vpsubusw LCPI7_0(%rip), %ymm0, %ymm0
+; AVX2:      # BB#0:
+; AVX2-NEXT: vmovdqu (%rdi), %ymm0
+; AVX2-NEXT: vpsubusw LCPI7_0(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vmovdqu %ymm0, (%rdi)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
 }
 
 define void @test9(i16* nocapture %head, i16 zeroext %w) nounwind {
 vector.ph:
   %0 = insertelement <16 x i16> undef, i16 %w, i32 0
   %broadcast15 = shufflevector <16 x i16> %0, <16 x i16> undef, <16 x i32> zeroinitializer
-  br label %vector.body
-
-vector.body:                                      ; preds = %vector.body, %vector.ph
-  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %1 = getelementptr inbounds i16* %head, i64 %index
+  %1 = getelementptr inbounds i16, i16* %head, i64 0
   %2 = bitcast i16* %1 to <16 x i16>*
-  %3 = load <16 x i16>* %2, align 2
+  %3 = load <16 x i16>, <16 x i16>* %2, align 2
   %4 = icmp ult <16 x i16> %3, %broadcast15
   %5 = sub <16 x i16> %3, %broadcast15
   %6 = select <16 x i1> %4, <16 x i16> zeroinitializer, <16 x i16> %5
   store <16 x i16> %6, <16 x i16>* %2, align 2
-  %index.next = add i64 %index, 8
-  %7 = icmp eq i64 %index.next, 16384
-  br i1 %7, label %for.end, label %vector.body
-
-for.end:                                          ; preds = %vector.body
   ret void
 
-
 ; AVX2: @test9
-; AVX2: vpsubusw %ymm0, %ymm1, %ymm1
+; AVX2:      # BB#0:
+; AVX2-NEXT: vmovd %esi, %xmm0
+; AVX2-NEXT: vpbroadcastw %xmm0, %ymm0
+; AVX2-NEXT: vmovdqu (%rdi), %ymm1
+; AVX2-NEXT: vpsubusw %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vmovdqu %ymm0, (%rdi)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
 }
 
 define void @test10(i8* nocapture %head) nounwind {
 vector.ph:
-  br label %vector.body
-
-vector.body:                                      ; preds = %vector.body, %vector.ph
-  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %0 = getelementptr inbounds i8* %head, i64 %index
+  %0 = getelementptr inbounds i8, i8* %head, i64 0
   %1 = bitcast i8* %0 to <32 x i8>*
-  %2 = load <32 x i8>* %1, align 1
+  %2 = load <32 x i8>, <32 x i8>* %1, align 1
   %3 = icmp slt <32 x i8> %2, zeroinitializer
   %4 = xor <32 x i8> %2, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
   %5 = select <32 x i1> %3, <32 x i8> %4, <32 x i8> zeroinitializer
   store <32 x i8> %5, <32 x i8>* %1, align 1
-  %index.next = add i64 %index, 16
-  %6 = icmp eq i64 %index.next, 16384
-  br i1 %6, label %for.end, label %vector.body
-
-for.end:                                          ; preds = %vector.body
   ret void
 
-
 ; AVX2: @test10
-; AVX2: vpsubusb LCPI9_0(%rip), %ymm0, %ymm0
+; AVX2:      # BB#0:
+; AVX2-NEXT: vmovdqu (%rdi), %ymm0
+; AVX2-NEXT: vpsubusb LCPI9_0(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vmovdqu %ymm0, (%rdi)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
 }
 
 define void @test11(i8* nocapture %head) nounwind {
 vector.ph:
-  br label %vector.body
-
-vector.body:                                      ; preds = %vector.body, %vector.ph
-  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %0 = getelementptr inbounds i8* %head, i64 %index
+  %0 = getelementptr inbounds i8, i8* %head, i64 0
   %1 = bitcast i8* %0 to <32 x i8>*
-  %2 = load <32 x i8>* %1, align 1
+  %2 = load <32 x i8>, <32 x i8>* %1, align 1
   %3 = icmp ugt <32 x i8> %2, <i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126>
   %4 = add <32 x i8> %2, <i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127>
   %5 = select <32 x i1> %3, <32 x i8> %4, <32 x i8> zeroinitializer
   store <32 x i8> %5, <32 x i8>* %1, align 1
-  %index.next = add i64 %index, 16
-  %6 = icmp eq i64 %index.next, 16384
-  br i1 %6, label %for.end, label %vector.body
-
-for.end:                                          ; preds = %vector.body
   ret void
 
 ; AVX2: @test11
-; AVX2: vpsubusb LCPI10_0(%rip), %ymm0, %ymm0
+; AVX2:      # BB#0:
+; AVX2-NEXT: vmovdqu (%rdi), %ymm0
+; AVX2-NEXT: vpsubusb LCPI10_0(%rip), %ymm0, %ymm0
+; AVX2-NEXT: vmovdqu %ymm0, (%rdi)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
 }
 
 define void @test12(i8* nocapture %head, i8 zeroext %w) nounwind {
 vector.ph:
   %0 = insertelement <32 x i8> undef, i8 %w, i32 0
   %broadcast15 = shufflevector <32 x i8> %0, <32 x i8> undef, <32 x i32> zeroinitializer
-  br label %vector.body
-
-vector.body:                                      ; preds = %vector.body, %vector.ph
-  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %1 = getelementptr inbounds i8* %head, i64 %index
+  %1 = getelementptr inbounds i8, i8* %head, i64 0
   %2 = bitcast i8* %1 to <32 x i8>*
-  %3 = load <32 x i8>* %2, align 1
+  %3 = load <32 x i8>, <32 x i8>* %2, align 1
   %4 = icmp ult <32 x i8> %3, %broadcast15
   %5 = sub <32 x i8> %3, %broadcast15
   %6 = select <32 x i1> %4, <32 x i8> zeroinitializer, <32 x i8> %5
   store <32 x i8> %6, <32 x i8>* %2, align 1
-  %index.next = add i64 %index, 16
-  %7 = icmp eq i64 %index.next, 16384
-  br i1 %7, label %for.end, label %vector.body
-
-for.end:                                          ; preds = %vector.body
   ret void
 
 ; AVX2: @test12
-; AVX2: vpsubusb %ymm0, %ymm1, %ymm1
+; AVX2:      # BB#0:
+; AVX2-NEXT: vmovd %esi, %xmm0
+; AVX2-NEXT: vpbroadcastb %xmm0, %ymm0
+; AVX2-NEXT: vmovdqu (%rdi), %ymm1
+; AVX2-NEXT: vpsubusb %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vmovdqu %ymm0, (%rdi)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
 }
diff --git a/test/CodeGen/X86/ptrtoint-constexpr.ll b/test/CodeGen/X86/ptrtoint-constexpr.ll
index d1cb34bec8a0..095201572bf5 100644
--- a/test/CodeGen/X86/ptrtoint-constexpr.ll
+++ b/test/CodeGen/X86/ptrtoint-constexpr.ll
@@ -11,4 +11,4 @@
 ; CHECK: x:
 ; CHECK: .quad	((0+1)&4294967295)*3
 
-@x = global i64 mul (i64 3, i64 ptrtoint (i2* getelementptr (i2* null, i64 1) to i64))
+@x = global i64 mul (i64 3, i64 ptrtoint (i2* getelementptr (i2, i2* null, i64 1) to i64))
diff --git a/test/CodeGen/X86/ragreedy-bug.ll b/test/CodeGen/X86/ragreedy-bug.ll
index 83ac274bba19..e8426317f13d 100644
--- a/test/CodeGen/X86/ragreedy-bug.ll
+++ b/test/CodeGen/X86/ragreedy-bug.ll
@@ -30,31 +30,31 @@ declare i32 @__maskrune(i32, i64) #7
 define fastcc i32 @prune_match(%struct.Connector_struct* nocapture readonly %a, %struct.Connector_struct* nocapture readonly %b) #9 {
 entry:
   %label56 = bitcast %struct.Connector_struct* %a to i16*
-  %0 = load i16* %label56, align 2
+  %0 = load i16, i16* %label56, align 2
   %label157 = bitcast %struct.Connector_struct* %b to i16*
-  %1 = load i16* %label157, align 2
+  %1 = load i16, i16* %label157, align 2
   %cmp = icmp eq i16 %0, %1
   br i1 %cmp, label %if.end, label %return, !prof !988
 if.end:
-  %priority = getelementptr inbounds %struct.Connector_struct* %a, i64 0, i32 2
-  %2 = load i8* %priority, align 1
-  %priority5 = getelementptr inbounds %struct.Connector_struct* %b, i64 0, i32 2
-  %3 = load i8* %priority5, align 1
-  %string = getelementptr inbounds %struct.Connector_struct* %a, i64 0, i32 5
-  %4 = load i8** %string, align 8
-  %string7 = getelementptr inbounds %struct.Connector_struct* %b, i64 0, i32 5
-  %5 = load i8** %string7, align 8
+  %priority = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %a, i64 0, i32 2
+  %2 = load i8, i8* %priority, align 1
+  %priority5 = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %b, i64 0, i32 2
+  %3 = load i8, i8* %priority5, align 1
+  %string = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %a, i64 0, i32 5
+  %4 = load i8*, i8** %string, align 8
+  %string7 = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %b, i64 0, i32 5
+  %5 = load i8*, i8** %string7, align 8
   br label %while.cond
 while.cond:
   %lsr.iv27 = phi i64 [ %lsr.iv.next28, %if.end17 ], [ 0, %if.end ]
-  %scevgep55 = getelementptr i8* %4, i64 %lsr.iv27
-  %6 = load i8* %scevgep55, align 1
+  %scevgep55 = getelementptr i8, i8* %4, i64 %lsr.iv27
+  %6 = load i8, i8* %scevgep55, align 1
   %idxprom.i.i = sext i8 %6 to i64
   %isascii.i.i224 = icmp sgt i8 %6, -1
   br i1 %isascii.i.i224, label %cond.true.i.i, label %cond.false.i.i, !prof !181
 cond.true.i.i:
-  %arrayidx.i.i = getelementptr inbounds %struct._RuneLocale* @_DefaultRuneLocale, i64 0, i32 5, i64 %idxprom.i.i
-  %7 = load i32* %arrayidx.i.i, align 4
+  %arrayidx.i.i = getelementptr inbounds %struct._RuneLocale, %struct._RuneLocale* @_DefaultRuneLocale, i64 0, i32 5, i64 %idxprom.i.i
+  %7 = load i32, i32* %arrayidx.i.i, align 4
   %and.i.i = and i32 %7, 32768
   br label %isupper.exit
 cond.false.i.i:
@@ -70,13 +70,13 @@ lor.rhs:
   %sunkaddr = ptrtoint i8* %5 to i64
   %sunkaddr58 = add i64 %sunkaddr, %lsr.iv27
   %sunkaddr59 = inttoptr i64 %sunkaddr58 to i8*
-  %9 = load i8* %sunkaddr59, align 1
+  %9 = load i8, i8* %sunkaddr59, align 1
   %idxprom.i.i214 = sext i8 %9 to i64
   %isascii.i.i213225 = icmp sgt i8 %9, -1
   br i1 %isascii.i.i213225, label %cond.true.i.i217, label %cond.false.i.i219, !prof !181
 cond.true.i.i217:
-  %arrayidx.i.i215 = getelementptr inbounds %struct._RuneLocale* @_DefaultRuneLocale, i64 0, i32 5, i64 %idxprom.i.i214
-  %10 = load i32* %arrayidx.i.i215, align 4
+  %arrayidx.i.i215 = getelementptr inbounds %struct._RuneLocale, %struct._RuneLocale* @_DefaultRuneLocale, i64 0, i32 5, i64 %idxprom.i.i214
+  %10 = load i32, i32* %arrayidx.i.i215, align 4
   %and.i.i216 = and i32 %10, 32768
   br label %isupper.exit223
 cond.false.i.i219:
@@ -92,11 +92,11 @@ while.body:
   %sunkaddr60 = ptrtoint i8* %4 to i64
   %sunkaddr61 = add i64 %sunkaddr60, %lsr.iv27
   %sunkaddr62 = inttoptr i64 %sunkaddr61 to i8*
-  %12 = load i8* %sunkaddr62, align 1
+  %12 = load i8, i8* %sunkaddr62, align 1
   %sunkaddr63 = ptrtoint i8* %5 to i64
   %sunkaddr64 = add i64 %sunkaddr63, %lsr.iv27
   %sunkaddr65 = inttoptr i64 %sunkaddr64 to i8*
-  %13 = load i8* %sunkaddr65, align 1
+  %13 = load i8, i8* %sunkaddr65, align 1
   %cmp14 = icmp eq i8 %12, %13
   br i1 %cmp14, label %if.end17, label %return, !prof !991
 if.end17:
@@ -110,13 +110,13 @@ if.then23:
   %sunkaddr66 = ptrtoint %struct.Connector_struct* %a to i64
   %sunkaddr67 = add i64 %sunkaddr66, 16
   %sunkaddr68 = inttoptr i64 %sunkaddr67 to i8**
-  %16 = load i8** %sunkaddr68, align 8
-  %17 = load i8* %16, align 1
+  %16 = load i8*, i8** %sunkaddr68, align 8
+  %17 = load i8, i8* %16, align 1
   %cmp26 = icmp eq i8 %17, 83
   %sunkaddr69 = ptrtoint i8* %4 to i64
   %sunkaddr70 = add i64 %sunkaddr69, %lsr.iv27
   %sunkaddr71 = inttoptr i64 %sunkaddr70 to i8*
-  %18 = load i8* %sunkaddr71, align 1
+  %18 = load i8, i8* %sunkaddr71, align 1
   br i1 %cmp26, label %land.lhs.true28, label %while.cond59.preheader, !prof !993
 land.lhs.true28:
   switch i8 %18, label %land.rhs.preheader [
@@ -127,24 +127,24 @@ land.lhs.true35:
   %sunkaddr72 = ptrtoint i8* %5 to i64
   %sunkaddr73 = add i64 %sunkaddr72, %lsr.iv27
   %sunkaddr74 = inttoptr i64 %sunkaddr73 to i8*
-  %19 = load i8* %sunkaddr74, align 1
+  %19 = load i8, i8* %sunkaddr74, align 1
   switch i8 %19, label %land.rhs.preheader [
     i8 112, label %land.lhs.true43
   ], !prof !995
 land.lhs.true43:
   %20 = ptrtoint i8* %16 to i64
   %21 = sub i64 0, %20
-  %scevgep52 = getelementptr i8* %4, i64 %21
-  %scevgep53 = getelementptr i8* %scevgep52, i64 %lsr.iv27
-  %scevgep54 = getelementptr i8* %scevgep53, i64 -1
+  %scevgep52 = getelementptr i8, i8* %4, i64 %21
+  %scevgep53 = getelementptr i8, i8* %scevgep52, i64 %lsr.iv27
+  %scevgep54 = getelementptr i8, i8* %scevgep53, i64 -1
   %cmp45 = icmp eq i8* %scevgep54, null
   br i1 %cmp45, label %return, label %lor.lhs.false47, !prof !996
 lor.lhs.false47:
   %22 = ptrtoint i8* %16 to i64
   %23 = sub i64 0, %22
-  %scevgep47 = getelementptr i8* %4, i64 %23
-  %scevgep48 = getelementptr i8* %scevgep47, i64 %lsr.iv27
-  %scevgep49 = getelementptr i8* %scevgep48, i64 -2
+  %scevgep47 = getelementptr i8, i8* %4, i64 %23
+  %scevgep48 = getelementptr i8, i8* %scevgep47, i64 %lsr.iv27
+  %scevgep49 = getelementptr i8, i8* %scevgep48, i64 -2
   %cmp50 = icmp eq i8* %scevgep49, null
   br i1 %cmp50, label %land.lhs.true52, label %while.cond59.preheader, !prof !997
 land.lhs.true52:
@@ -152,7 +152,7 @@ land.lhs.true52:
   %sunkaddr76 = add i64 %sunkaddr75, %lsr.iv27
   %sunkaddr77 = add i64 %sunkaddr76, -1
   %sunkaddr78 = inttoptr i64 %sunkaddr77 to i8*
-  %24 = load i8* %sunkaddr78, align 1
+  %24 = load i8, i8* %sunkaddr78, align 1
   %cmp55 = icmp eq i8 %24, 73
   %cmp61233 = icmp eq i8 %18, 0
   %or.cond265 = or i1 %cmp55, %cmp61233
@@ -161,14 +161,14 @@ while.cond59.preheader:
   %cmp61233.old = icmp eq i8 %18, 0
   br i1 %cmp61233.old, label %return, label %land.rhs.preheader, !prof !999
 land.rhs.preheader:
-  %scevgep33 = getelementptr i8* %5, i64 %lsr.iv27
-  %scevgep43 = getelementptr i8* %4, i64 %lsr.iv27
+  %scevgep33 = getelementptr i8, i8* %5, i64 %lsr.iv27
+  %scevgep43 = getelementptr i8, i8* %4, i64 %lsr.iv27
   br label %land.rhs
 land.rhs:
   %lsr.iv = phi i64 [ 0, %land.rhs.preheader ], [ %lsr.iv.next, %if.then83 ]
   %25 = phi i8 [ %27, %if.then83 ], [ %18, %land.rhs.preheader ]
-  %scevgep34 = getelementptr i8* %scevgep33, i64 %lsr.iv
-  %26 = load i8* %scevgep34, align 1
+  %scevgep34 = getelementptr i8, i8* %scevgep33, i64 %lsr.iv
+  %26 = load i8, i8* %scevgep34, align 1
   %cmp64 = icmp eq i8 %26, 0
   br i1 %cmp64, label %return, label %while.body66, !prof !1000
 while.body66:
@@ -182,9 +182,9 @@ lor.lhs.false74:
   %or.cond208 = or i1 %cmp77, %cmp81
   br i1 %or.cond208, label %return, label %if.then83, !prof !1002
 if.then83:
-  %scevgep44 = getelementptr i8* %scevgep43, i64 %lsr.iv
-  %scevgep45 = getelementptr i8* %scevgep44, i64 1
-  %27 = load i8* %scevgep45, align 1
+  %scevgep44 = getelementptr i8, i8* %scevgep43, i64 %lsr.iv
+  %scevgep45 = getelementptr i8, i8* %scevgep44, i64 1
+  %27 = load i8, i8* %scevgep45, align 1
   %cmp61 = icmp eq i8 %27, 0
   %lsr.iv.next = add i64 %lsr.iv, 1
   br i1 %cmp61, label %return, label %land.rhs, !prof !999
@@ -197,18 +197,18 @@ while.cond95.preheader:
   %sunkaddr79 = ptrtoint i8* %4 to i64
   %sunkaddr80 = add i64 %sunkaddr79, %lsr.iv27
   %sunkaddr81 = inttoptr i64 %sunkaddr80 to i8*
-  %28 = load i8* %sunkaddr81, align 1
+  %28 = load i8, i8* %sunkaddr81, align 1
   %cmp97238 = icmp eq i8 %28, 0
   br i1 %cmp97238, label %return, label %land.rhs99.preheader, !prof !1004
 land.rhs99.preheader:
-  %scevgep31 = getelementptr i8* %5, i64 %lsr.iv27
-  %scevgep40 = getelementptr i8* %4, i64 %lsr.iv27
+  %scevgep31 = getelementptr i8, i8* %5, i64 %lsr.iv27
+  %scevgep40 = getelementptr i8, i8* %4, i64 %lsr.iv27
   br label %land.rhs99
 land.rhs99:
   %lsr.iv17 = phi i64 [ 0, %land.rhs99.preheader ], [ %lsr.iv.next18, %if.then117 ]
   %29 = phi i8 [ %31, %if.then117 ], [ %28, %land.rhs99.preheader ]
-  %scevgep32 = getelementptr i8* %scevgep31, i64 %lsr.iv17
-  %30 = load i8* %scevgep32, align 1
+  %scevgep32 = getelementptr i8, i8* %scevgep31, i64 %lsr.iv17
+  %30 = load i8, i8* %scevgep32, align 1
   %cmp101 = icmp eq i8 %30, 0
   br i1 %cmp101, label %return, label %while.body104, !prof !1005
 while.body104:
@@ -219,9 +219,9 @@ while.body104:
   %or.cond210 = or i1 %or.cond209, %cmp115
   br i1 %or.cond210, label %if.then117, label %return, !prof !1006
 if.then117:
-  %scevgep41 = getelementptr i8* %scevgep40, i64 %lsr.iv17
-  %scevgep42 = getelementptr i8* %scevgep41, i64 1
-  %31 = load i8* %scevgep42, align 1
+  %scevgep41 = getelementptr i8, i8* %scevgep40, i64 %lsr.iv17
+  %scevgep42 = getelementptr i8, i8* %scevgep41, i64 1
+  %31 = load i8, i8* %scevgep42, align 1
   %cmp97 = icmp eq i8 %31, 0
   %lsr.iv.next18 = add i64 %lsr.iv17, 1
   br i1 %cmp97, label %return, label %land.rhs99, !prof !1004
@@ -234,18 +234,18 @@ while.cond130.preheader:
   %sunkaddr82 = ptrtoint i8* %4 to i64
   %sunkaddr83 = add i64 %sunkaddr82, %lsr.iv27
   %sunkaddr84 = inttoptr i64 %sunkaddr83 to i8*
-  %32 = load i8* %sunkaddr84, align 1
+  %32 = load i8, i8* %sunkaddr84, align 1
   %cmp132244 = icmp eq i8 %32, 0
   br i1 %cmp132244, label %return, label %land.rhs134.preheader, !prof !1008
 land.rhs134.preheader:
-  %scevgep29 = getelementptr i8* %5, i64 %lsr.iv27
-  %scevgep37 = getelementptr i8* %4, i64 %lsr.iv27
+  %scevgep29 = getelementptr i8, i8* %5, i64 %lsr.iv27
+  %scevgep37 = getelementptr i8, i8* %4, i64 %lsr.iv27
   br label %land.rhs134
 land.rhs134:
   %lsr.iv22 = phi i64 [ 0, %land.rhs134.preheader ], [ %lsr.iv.next23, %if.then152 ]
   %33 = phi i8 [ %35, %if.then152 ], [ %32, %land.rhs134.preheader ]
-  %scevgep30 = getelementptr i8* %scevgep29, i64 %lsr.iv22
-  %34 = load i8* %scevgep30, align 1
+  %scevgep30 = getelementptr i8, i8* %scevgep29, i64 %lsr.iv22
+  %34 = load i8, i8* %scevgep30, align 1
   %cmp136 = icmp eq i8 %34, 0
   br i1 %cmp136, label %return, label %while.body139, !prof !1009
 while.body139:
@@ -256,9 +256,9 @@ while.body139:
   %or.cond212 = or i1 %or.cond211, %cmp150
   br i1 %or.cond212, label %if.then152, label %return, !prof !1010
 if.then152:
-  %scevgep38 = getelementptr i8* %scevgep37, i64 %lsr.iv22
-  %scevgep39 = getelementptr i8* %scevgep38, i64 1
-  %35 = load i8* %scevgep39, align 1
+  %scevgep38 = getelementptr i8, i8* %scevgep37, i64 %lsr.iv22
+  %scevgep39 = getelementptr i8, i8* %scevgep38, i64 1
+  %35 = load i8, i8* %scevgep39, align 1
   %cmp132 = icmp eq i8 %35, 0
   %lsr.iv.next23 = add i64 %lsr.iv22, 1
   br i1 %cmp132, label %return, label %land.rhs134, !prof !1008
diff --git a/test/CodeGen/X86/ragreedy-hoist-spill.ll b/test/CodeGen/X86/ragreedy-hoist-spill.ll
index 57afb4152db5..e7dda5349568 100644
--- a/test/CodeGen/X86/ragreedy-hoist-spill.ll
+++ b/test/CodeGen/X86/ragreedy-hoist-spill.ll
@@ -18,7 +18,7 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
 entry:
   %sub.ptr.rhs.cast646 = ptrtoint i8* %line to i64
   %old = alloca [512 x i8], align 16
-  %0 = getelementptr inbounds [512 x i8]* %old, i64 0, i64 0
+  %0 = getelementptr inbounds [512 x i8], [512 x i8]* %old, i64 0, i64 0
   switch i64 %fid, label %if.then [
     i64 2, label %if.end
     i64 0, label %if.end
@@ -30,7 +30,7 @@ if.then:
 if.end:
   switch i64 undef, label %if.end25 [
     i64 0, label %if.then4
-    i64 1, label %land.lhs.true14
+    i64 1, label %if.end25
   ]
 
 if.then4:
@@ -58,7 +58,7 @@ if.then.i2712:
   unreachable
 
 SyTime.exit2720:
-  %add.ptr = getelementptr [512 x i8]* %old, i64 0, i64 512
+  %add.ptr = getelementptr [512 x i8], [512 x i8]* %old, i64 0, i64 512
   %cmp293427 = icmp ult i8* %0, %add.ptr
   br i1 %cmp293427, label %for.body.lr.ph, label %while.body.preheader
 
@@ -67,8 +67,8 @@ for.body.lr.ph:
   br label %while.body.preheader
 
 while.body.preheader:
-  %add.ptr1603 = getelementptr [512 x i8]* null, i64 0, i64 512
-  %echo.i3101 = getelementptr [16 x %struct.TMP.1]* @syBuf, i64 0, i64 %fid, i32 1
+  %add.ptr1603 = getelementptr [512 x i8], [512 x i8]* null, i64 0, i64 512
+  %echo.i3101 = getelementptr [16 x %struct.TMP.1], [16 x %struct.TMP.1]* @syBuf, i64 0, i64 %fid, i32 1
   %1 = xor i64 %sub.ptr.rhs.cast646, -1
   br label %do.body
 
@@ -210,7 +210,7 @@ land.lhs.true504:
   br i1 undef, label %do.body479.backedge, label %if.end517
 
 do.body479.backedge:
-  %incdec.ptr480 = getelementptr i8* %incdec.ptr4803316, i64 1
+  %incdec.ptr480 = getelementptr i8, i8* %incdec.ptr4803316, i64 1
   %cmp483 = icmp eq i8 undef, 0
   br i1 %cmp483, label %if.end517, label %do.body479.backedge.land.rhs485_crit_edge
 
@@ -228,7 +228,7 @@ if.end517:
   ]
 
 if.then532:
-  store i8 0, i8* getelementptr inbounds ([512 x i8]* @SyFgets.yank, i64 0, i64 0), align 16, !tbaa !5
+  store i8 0, i8* getelementptr inbounds ([512 x i8], [512 x i8]* @SyFgets.yank, i64 0, i64 0), align 16, !tbaa !5
   br label %for.cond534
 
 for.cond534:
@@ -245,7 +245,7 @@ for.end552:
   %s.2.lcssa = phi i8* [ undef, %for.cond542.preheader ], [ %q.4, %for.body545 ]
   %sub.ptr.lhs.cast553 = ptrtoint i8* %s.2.lcssa to i64
   %sub.ptr.sub555 = sub i64 %sub.ptr.lhs.cast553, 0
-  %arrayidx556 = getelementptr i8* null, i64 %sub.ptr.sub555
+  %arrayidx556 = getelementptr i8, i8* null, i64 %sub.ptr.sub555
   store i8 0, i8* %arrayidx556, align 1, !tbaa !5
   br label %while.cond197.backedge
 
@@ -340,7 +340,7 @@ while.cond1683.preheader:
 
 while.body1679:
   %oldc.43406 = phi i32 [ %inc, %syEchoch.exit3070 ], [ %oldc.1.lcssa, %for.body1664.lr.ph ]
-  %4 = load %struct.TMP.2** %echo.i3101, align 8, !tbaa !6
+  %4 = load %struct.TMP.2*, %struct.TMP.2** %echo.i3101, align 8, !tbaa !6
   %call.i3062 = call i32 @fileno(%struct.TMP.2* %4)
   br i1 undef, label %if.then.i3069, label %syEchoch.exit3070
 
@@ -360,10 +360,10 @@ while.end1693:
   unreachable
 
 for.body1723:
-  %q.303203 = phi i8* [ getelementptr inbounds ([8192 x i8]* @syHistory, i64 0, i64 8189), %if.then1477 ], [ %incdec.ptr1730, %for.body1723 ]
-  %add.ptr1728 = getelementptr i8* %q.303203, i64 %idx.neg1727
-  %5 = load i8* %add.ptr1728, align 1, !tbaa !5
-  %incdec.ptr1730 = getelementptr i8* %q.303203, i64 -1
+  %q.303203 = phi i8* [ getelementptr inbounds ([8192 x i8], [8192 x i8]* @syHistory, i64 0, i64 8189), %if.then1477 ], [ %incdec.ptr1730, %for.body1723 ]
+  %add.ptr1728 = getelementptr i8, i8* %q.303203, i64 %idx.neg1727
+  %5 = load i8, i8* %add.ptr1728, align 1, !tbaa !5
+  %incdec.ptr1730 = getelementptr i8, i8* %q.303203, i64 -1
   br label %for.body1723
 
 cleanup:
diff --git a/test/CodeGen/X86/ragreedy-last-chance-recoloring.ll b/test/CodeGen/X86/ragreedy-last-chance-recoloring.ll
index 49d58f437c21..f32875581f55 100644
--- a/test/CodeGen/X86/ragreedy-last-chance-recoloring.ll
+++ b/test/CodeGen/X86/ragreedy-last-chance-recoloring.ll
@@ -36,27 +36,27 @@ bb85:                                             ; preds = %bb222, %bb85, %bb
   indirectbr i8* undef, [label %bb439, label %bb85]
 
 bb206:                                            ; preds = %bb
-  %tmp = getelementptr [499 x i32]* @fp_dh_36985b17790d59a27994eaab5dcb00ee, i32 0, i32 undef
-  %tmp207 = load i32* %tmp
+  %tmp = getelementptr [499 x i32], [499 x i32]* @fp_dh_36985b17790d59a27994eaab5dcb00ee, i32 0, i32 undef
+  %tmp207 = load i32, i32* %tmp
   %tmp208 = add i32 %tmp207, 1
   %tmp209 = inttoptr i32 %tmp208 to i8*
   indirectbr i8* %tmp209, [label %bb213]
 
 bb213:                                            ; preds = %bb206
-  %tmp214 = load i32* @fp_dh_18716afa4a5354de0a302c8edb3b0ee1, align 4
-  %tmp215 = load i8** @fp_dh_20a33cdeefab8f4c8887e82766cb9dcb, align 4
+  %tmp214 = load i32, i32* @fp_dh_18716afa4a5354de0a302c8edb3b0ee1, align 4
+  %tmp215 = load i8*, i8** @fp_dh_20a33cdeefab8f4c8887e82766cb9dcb, align 4
   %tmp216 = urem i32 -717428541, %tmp214
-  %tmp217 = getelementptr i8* %tmp215, i32 %tmp216
+  %tmp217 = getelementptr i8, i8* %tmp215, i32 %tmp216
   %tmp218 = bitcast i8* %tmp217 to i32*
-  %tmp219 = load i32* %tmp218, align 4
+  %tmp219 = load i32, i32* %tmp218, align 4
   store i32 %tmp219, i32* undef, align 4
   %tmp220 = select i1 false, i32 359373646, i32 1677237955
   %tmp221 = add i32 %tmp220, 0
   indirectbr i8* undef, [label %bb432, label %bb222]
 
 bb222:                                            ; preds = %bb213
-  %tmp224 = load i32* undef, align 4
-  %tmp225 = load i32* undef, align 4
+  %tmp224 = load i32, i32* undef, align 4
+  %tmp225 = load i32, i32* undef, align 4
   %tmp226 = xor i32 %tmp225, %tmp224
   %tmp227 = shl i32 %tmp226, 1
   %tmp228 = and i32 %tmp227, -2048880334
@@ -65,13 +65,13 @@ bb222:                                            ; preds = %bb213
   %tmp231 = xor i32 %tmp230, 1059356227
   %tmp232 = mul i32 %tmp231, 1603744721
   %tmp233 = urem i32 %tmp232, 259
-  %tmp234 = getelementptr [259 x i8]* bitcast (i8* getelementptr inbounds ([5419648 x i8]* @fp_dh_9d93c897906e39883c58b034c8e786b2, i32 0, i32 2039075) to [259 x i8]*), i32 0, i32 %tmp233
-  %tmp235 = load i8* %tmp234, align 1
+  %tmp234 = getelementptr [259 x i8], [259 x i8]* bitcast (i8* getelementptr inbounds ([5419648 x i8], [5419648 x i8]* @fp_dh_9d93c897906e39883c58b034c8e786b2, i32 0, i32 2039075) to [259 x i8]*), i32 0, i32 %tmp233
+  %tmp235 = load i8, i8* %tmp234, align 1
   %tmp236 = add i32 %tmp233, 2
-  %tmp237 = getelementptr [264 x i8]* bitcast (i8* getelementptr inbounds ([5419648 x i8]* @fp_dh_9d93c897906e39883c58b034c8e786b2, i32 0, i32 3388166) to [264 x i8]*), i32 0, i32 %tmp236
-  %tmp238 = load i8* %tmp237, align 1
-  %tmp239 = getelementptr [265 x i8]* bitcast (i8* getelementptr inbounds ([5419648 x i8]* @fp_dh_9d93c897906e39883c58b034c8e786b2, i32 0, i32 1325165) to [265 x i8]*), i32 0, i32 0
-  %tmp240 = load i8* %tmp239, align 1
+  %tmp237 = getelementptr [264 x i8], [264 x i8]* bitcast (i8* getelementptr inbounds ([5419648 x i8], [5419648 x i8]* @fp_dh_9d93c897906e39883c58b034c8e786b2, i32 0, i32 3388166) to [264 x i8]*), i32 0, i32 %tmp236
+  %tmp238 = load i8, i8* %tmp237, align 1
+  %tmp239 = getelementptr [265 x i8], [265 x i8]* bitcast (i8* getelementptr inbounds ([5419648 x i8], [5419648 x i8]* @fp_dh_9d93c897906e39883c58b034c8e786b2, i32 0, i32 1325165) to [265 x i8]*), i32 0, i32 0
+  %tmp240 = load i8, i8* %tmp239, align 1
   %tmp241 = add i32 %tmp233, 6
   %tmp242 = trunc i32 %tmp241 to i8
   %tmp243 = mul i8 %tmp242, -3
@@ -80,7 +80,7 @@ bb222:                                            ; preds = %bb213
   %tmp246 = and i8 %tmp245, 6
   %tmp247 = sub i8 0, %tmp246
   %tmp248 = add i8 %tmp244, %tmp247
-  %tmp249 = load i8* undef, align 1
+  %tmp249 = load i8, i8* undef, align 1
   %tmp250 = xor i8 %tmp235, 17
   %tmp251 = xor i8 %tmp250, %tmp238
   %tmp252 = xor i8 %tmp251, %tmp240
@@ -88,13 +88,13 @@ bb222:                                            ; preds = %bb213
   %tmp254 = xor i8 %tmp253, %tmp248
   %tmp255 = zext i8 %tmp254 to i16
   %tmp256 = shl nuw i16 %tmp255, 8
-  %tmp257 = load i8* null, align 1
-  %tmp258 = load i32* @fp_dh_18716afa4a5354de0a302c8edb3b0ee1, align 4
-  %tmp259 = load i8** @fp_dh_20a33cdeefab8f4c8887e82766cb9dcb, align 4
+  %tmp257 = load i8, i8* null, align 1
+  %tmp258 = load i32, i32* @fp_dh_18716afa4a5354de0a302c8edb3b0ee1, align 4
+  %tmp259 = load i8*, i8** @fp_dh_20a33cdeefab8f4c8887e82766cb9dcb, align 4
   %tmp260 = urem i32 -717428541, %tmp258
-  %tmp261 = getelementptr i8* %tmp259, i32 %tmp260
+  %tmp261 = getelementptr i8, i8* %tmp259, i32 %tmp260
   %tmp262 = bitcast i8* %tmp261 to i32*
-  %tmp263 = load i32* %tmp262, align 4
+  %tmp263 = load i32, i32* %tmp262, align 4
   %tmp264 = xor i32 %tmp263, 0
   %tmp265 = shl i32 %tmp264, 1
   %tmp266 = and i32 %tmp265, -1312119832
@@ -104,8 +104,8 @@ bb222:                                            ; preds = %bb213
   %tmp270 = mul i32 %tmp269, 1603744721
   %tmp271 = urem i32 %tmp270, 259
   %tmp274 = add i32 %tmp271, 3
-  %tmp275 = getelementptr [265 x i8]* bitcast (i8* getelementptr inbounds ([5419648 x i8]* @fp_dh_9d93c897906e39883c58b034c8e786b2, i32 0, i32 1325165) to [265 x i8]*), i32 0, i32 %tmp274
-  %tmp276 = load i8* %tmp275, align 1
+  %tmp275 = getelementptr [265 x i8], [265 x i8]* bitcast (i8* getelementptr inbounds ([5419648 x i8], [5419648 x i8]* @fp_dh_9d93c897906e39883c58b034c8e786b2, i32 0, i32 1325165) to [265 x i8]*), i32 0, i32 %tmp274
+  %tmp276 = load i8, i8* %tmp275, align 1
   %tmp277 = add i32 %tmp271, 6
   %tmp278 = trunc i32 %tmp277 to i8
   %tmp279 = mul i8 %tmp278, -3
@@ -161,8 +161,8 @@ bb222:                                            ; preds = %bb213
   %tmp334 = add i32 %tmp327, -1456704142
   %tmp335 = zext i1 %tmp333 to i32
   %tmp336 = add i32 %tmp334, %tmp335
-  %tmp337 = getelementptr [499 x i32]* @fp_dh_36985b17790d59a27994eaab5dcb00ee, i32 0, i32 %tmp336
-  %tmp338 = load i32* %tmp337
+  %tmp337 = getelementptr [499 x i32], [499 x i32]* @fp_dh_36985b17790d59a27994eaab5dcb00ee, i32 0, i32 %tmp336
+  %tmp338 = load i32, i32* %tmp337
   %tmp339 = add i32 %tmp338, 1
   %tmp340 = inttoptr i32 %tmp339 to i8*
   indirectbr i8* %tmp340, [label %bb85, label %bb439]
@@ -170,8 +170,8 @@ bb222:                                            ; preds = %bb213
 bb432:                                            ; preds = %bb432, %bb213
   %tmp433 = phi i32 [ %tmp221, %bb213 ], [ %tmp433, %bb432 ]
   %tmp434 = add i32 %tmp433, 1022523279
-  %tmp435 = getelementptr [499 x i32]* @fp_dh_36985b17790d59a27994eaab5dcb00ee, i32 0, i32 %tmp434
-  %tmp436 = load i32* %tmp435
+  %tmp435 = getelementptr [499 x i32], [499 x i32]* @fp_dh_36985b17790d59a27994eaab5dcb00ee, i32 0, i32 %tmp434
+  %tmp436 = load i32, i32* %tmp435
   %tmp437 = add i32 %tmp436, 1
   %tmp438 = inttoptr i32 %tmp437 to i8*
   indirectbr i8* %tmp438, [label %bb432]
diff --git a/test/CodeGen/X86/rd-mod-wr-eflags.ll b/test/CodeGen/X86/rd-mod-wr-eflags.ll
index 5089bd761a80..972372151bcf 100644
--- a/test/CodeGen/X86/rd-mod-wr-eflags.ll
+++ b/test/CodeGen/X86/rd-mod-wr-eflags.ll
@@ -7,8 +7,8 @@ define void @_Z7releaseP3obj(%struct.obj* nocapture %o) nounwind uwtable ssp {
 entry:
 ; CHECK: decq	(%{{rdi|rcx}})
 ; CHECK-NEXT: je
-  %refcnt = getelementptr inbounds %struct.obj* %o, i64 0, i32 0
-  %0 = load i64* %refcnt, align 8
+  %refcnt = getelementptr inbounds %struct.obj, %struct.obj* %o, i64 0, i32 0
+  %0 = load i64, i64* %refcnt, align 8
   %dec = add i64 %0, -1
   store i64 %dec, i64* %refcnt, align 8
   %tobool = icmp eq i64 %dec, 0
@@ -33,13 +33,13 @@ define i32 @test() nounwind uwtable ssp {
 entry:
 ; CHECK: decq
 ; CHECK-NOT: decq
-%0 = load i64* @c, align 8
+%0 = load i64, i64* @c, align 8
 %dec.i = add nsw i64 %0, -1
 store i64 %dec.i, i64* @c, align 8
 %tobool.i = icmp ne i64 %dec.i, 0
 %lor.ext.i = zext i1 %tobool.i to i32
 store i32 %lor.ext.i, i32* @a, align 4
-%call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %dec.i) nounwind
+%call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i64 0, i64 0), i64 %dec.i) nounwind
 ret i32 0
 }
 
@@ -47,13 +47,13 @@ ret i32 0
 define i32 @test2() nounwind uwtable ssp {
 entry:
 ; CHECK-NOT: decq ({{.*}})
-%0 = load i64* @c, align 8
+%0 = load i64, i64* @c, align 8
 %dec.i = add nsw i64 %0, -1
 store i64 %dec.i, i64* @c, align 8
 %tobool.i = icmp ne i64 %0, 0
 %lor.ext.i = zext i1 %tobool.i to i32
 store i32 %lor.ext.i, i32* @a, align 4
-%call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %dec.i) nounwind
+%call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i64 0, i64 0), i64 %dec.i) nounwind
 ret i32 0
 }
 
@@ -69,9 +69,9 @@ declare void @other(%struct.obj2* ) nounwind;
 define void @example_dec(%struct.obj2* %o) nounwind uwtable ssp {
 ; 64 bit dec
 entry:
-  %s64 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 0
+  %s64 = getelementptr inbounds %struct.obj2, %struct.obj2* %o, i64 0, i32 0
 ; CHECK-NOT: load 
-  %0 = load i64* %s64, align 8
+  %0 = load i64, i64* %s64, align 8
 ; CHECK: decq ({{.*}})
   %dec = add i64 %0, -1
   store i64 %dec, i64* %s64, align 8
@@ -80,9 +80,9 @@ entry:
 
 ; 32 bit dec
 if.end:
-  %s32 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 1
+  %s32 = getelementptr inbounds %struct.obj2, %struct.obj2* %o, i64 0, i32 1
 ; CHECK-NOT: load 
-  %1 = load i32* %s32, align 4
+  %1 = load i32, i32* %s32, align 4
 ; CHECK: decl {{[0-9][0-9]*}}({{.*}})
   %dec1 = add i32 %1, -1
   store i32 %dec1, i32* %s32, align 4
@@ -91,9 +91,9 @@ if.end:
 
 ; 16 bit dec
 if.end1:
-  %s16 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 2
+  %s16 = getelementptr inbounds %struct.obj2, %struct.obj2* %o, i64 0, i32 2
 ; CHECK-NOT: load 
-  %2 = load i16* %s16, align 2
+  %2 = load i16, i16* %s16, align 2
 ; CHECK: decw {{[0-9][0-9]*}}({{.*}})
   %dec2 = add i16 %2, -1
   store i16 %dec2, i16* %s16, align 2
@@ -102,9 +102,9 @@ if.end1:
 
 ; 8 bit dec
 if.end2:
-  %s8 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 3
+  %s8 = getelementptr inbounds %struct.obj2, %struct.obj2* %o, i64 0, i32 3
 ; CHECK-NOT: load 
-  %3 = load i8* %s8
+  %3 = load i8, i8* %s8
 ; CHECK: decb {{[0-9][0-9]*}}({{.*}})
   %dec3 = add i8 %3, -1
   store i8 %dec3, i8* %s8
@@ -123,9 +123,9 @@ return:                                           ; preds = %if.end4, %if.end, %
 define void @example_inc(%struct.obj2* %o) nounwind uwtable ssp {
 ; 64 bit inc
 entry:
-  %s64 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 0
+  %s64 = getelementptr inbounds %struct.obj2, %struct.obj2* %o, i64 0, i32 0
 ; CHECK-NOT: load 
-  %0 = load i64* %s64, align 8
+  %0 = load i64, i64* %s64, align 8
 ; CHECK: incq ({{.*}})
   %inc = add i64 %0, 1
   store i64 %inc, i64* %s64, align 8
@@ -134,9 +134,9 @@ entry:
 
 ; 32 bit inc
 if.end:
-  %s32 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 1
+  %s32 = getelementptr inbounds %struct.obj2, %struct.obj2* %o, i64 0, i32 1
 ; CHECK-NOT: load 
-  %1 = load i32* %s32, align 4
+  %1 = load i32, i32* %s32, align 4
 ; CHECK: incl {{[0-9][0-9]*}}({{.*}})
   %inc1 = add i32 %1, 1
   store i32 %inc1, i32* %s32, align 4
@@ -145,9 +145,9 @@ if.end:
 
 ; 16 bit inc
 if.end1:
-  %s16 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 2
+  %s16 = getelementptr inbounds %struct.obj2, %struct.obj2* %o, i64 0, i32 2
 ; CHECK-NOT: load 
-  %2 = load i16* %s16, align 2
+  %2 = load i16, i16* %s16, align 2
 ; CHECK: incw {{[0-9][0-9]*}}({{.*}})
   %inc2 = add i16 %2, 1
   store i16 %inc2, i16* %s16, align 2
@@ -156,9 +156,9 @@ if.end1:
 
 ; 8 bit inc
 if.end2:
-  %s8 = getelementptr inbounds %struct.obj2* %o, i64 0, i32 3
+  %s8 = getelementptr inbounds %struct.obj2, %struct.obj2* %o, i64 0, i32 3
 ; CHECK-NOT: load 
-  %3 = load i8* %s8
+  %3 = load i8, i8* %s8
 ; CHECK: incb {{[0-9][0-9]*}}({{.*}})
   %inc3 = add i8 %3, 1
   store i8 %inc3, i8* %s8
@@ -181,9 +181,9 @@ define void @test3() nounwind ssp {
 entry:
 ; CHECK-LABEL: test3:
 ; CHECK: decq 16(%rax)
-  %0 = load i64** @foo, align 8
-  %arrayidx = getelementptr inbounds i64* %0, i64 2
-  %1 = load i64* %arrayidx, align 8
+  %0 = load i64*, i64** @foo, align 8
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 2
+  %1 = load i64, i64* %arrayidx, align 8
   %dec = add i64 %1, -1
   store i64 %dec, i64* %arrayidx, align 8
   %cmp = icmp eq i64 %dec, 0
@@ -209,8 +209,8 @@ declare void @baz()
 
 define void @test4() nounwind uwtable ssp {
 entry:
-  %0 = load i32* @x, align 4
-  %1 = load i32* @y, align 4
+  %0 = load i32, i32* @x, align 4
+  %1 = load i32, i32* @y, align 4
   %dec = add nsw i32 %1, -1
   store i32 %dec, i32* @y, align 4
   %tobool.i = icmp ne i32 %dec, 0
diff --git a/test/CodeGen/X86/rdrand.ll b/test/CodeGen/X86/rdrand.ll
index 48182d029eb2..107cde05a0e6 100644
--- a/test/CodeGen/X86/rdrand.ll
+++ b/test/CodeGen/X86/rdrand.ll
@@ -69,7 +69,7 @@ while.body:                                       ; preds = %entry, %while.body
   %p.addr.03 = phi i32* [ %incdec.ptr, %while.body ], [ %p, %entry ]
   %n.addr.02 = phi i32 [ %dec, %while.body ], [ %n, %entry ]
   %dec = add nsw i32 %n.addr.02, -1
-  %incdec.ptr = getelementptr inbounds i32* %p.addr.03, i64 1
+  %incdec.ptr = getelementptr inbounds i32, i32* %p.addr.03, i64 1
   %rand = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
   %v1 = extractvalue { i32, i32 } %rand, 0
   store i32 %v1, i32* %p.addr.03, align 4
diff --git a/test/CodeGen/X86/recip-fastmath.ll b/test/CodeGen/X86/recip-fastmath.ll
index 83b86accdb38..fcd077092dab 100644
--- a/test/CodeGen/X86/recip-fastmath.ll
+++ b/test/CodeGen/X86/recip-fastmath.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core2 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 | FileCheck %s --check-prefix=BTVER2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+use-recip-est,+avx -x86-recip-refinement-steps=2 | FileCheck %s --check-prefix=REFINE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx,use-recip-est | FileCheck %s --check-prefix=RECIP
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx,use-recip-est -x86-recip-refinement-steps=2 | FileCheck %s --check-prefix=REFINE
 
 ; If the target's divss/divps instructions are substantially
 ; slower than rcpss/rcpps with a Newton-Raphson refinement,
@@ -20,13 +20,13 @@ define float @reciprocal_estimate(float %x) #0 {
 ; CHECK-NEXT: movaps
 ; CHECK-NEXT: retq
 
-; BTVER2-LABEL: reciprocal_estimate:
-; BTVER2: vrcpss
-; BTVER2: vmulss
-; BTVER2: vsubss
-; BTVER2: vmulss
-; BTVER2: vaddss
-; BTVER2-NEXT: retq
+; RECIP-LABEL: reciprocal_estimate:
+; RECIP: vrcpss
+; RECIP: vmulss
+; RECIP: vsubss
+; RECIP: vmulss
+; RECIP: vaddss
+; RECIP-NEXT: retq
 
 ; REFINE-LABEL: reciprocal_estimate:
 ; REFINE: vrcpss
@@ -51,13 +51,13 @@ define <4 x float> @reciprocal_estimate_v4f32(<4 x float> %x) #0 {
 ; CHECK-NEXT: movaps
 ; CHECK-NEXT: retq
 
-; BTVER2-LABEL: reciprocal_estimate_v4f32:
-; BTVER2: vrcpps
-; BTVER2: vmulps
-; BTVER2: vsubps
-; BTVER2: vmulps
-; BTVER2: vaddps
-; BTVER2-NEXT: retq
+; RECIP-LABEL: reciprocal_estimate_v4f32:
+; RECIP: vrcpps
+; RECIP: vmulps
+; RECIP: vsubps
+; RECIP: vmulps
+; RECIP: vaddps
+; RECIP-NEXT: retq
 
 ; REFINE-LABEL: reciprocal_estimate_v4f32:
 ; REFINE: vrcpps
@@ -85,13 +85,13 @@ define <8 x float> @reciprocal_estimate_v8f32(<8 x float> %x) #0 {
 ; CHECK-NEXT: movaps
 ; CHECK-NEXT: retq
 
-; BTVER2-LABEL: reciprocal_estimate_v8f32:
-; BTVER2: vrcpps
-; BTVER2: vmulps
-; BTVER2: vsubps
-; BTVER2: vmulps
-; BTVER2: vaddps
-; BTVER2-NEXT: retq
+; RECIP-LABEL: reciprocal_estimate_v8f32:
+; RECIP: vrcpps
+; RECIP: vmulps
+; RECIP: vsubps
+; RECIP: vmulps
+; RECIP: vaddps
+; RECIP-NEXT: retq
 
 ; REFINE-LABEL: reciprocal_estimate_v8f32:
 ; REFINE: vrcpps
diff --git a/test/CodeGen/X86/regalloc-reconcile-broken-hints.ll b/test/CodeGen/X86/regalloc-reconcile-broken-hints.ll
index 00679428ca63..016b0d13fc4a 100644
--- a/test/CodeGen/X86/regalloc-reconcile-broken-hints.ll
+++ b/test/CodeGen/X86/regalloc-reconcile-broken-hints.ll
@@ -43,10 +43,10 @@ declare noalias i32* @make_data()
 define %struct._list* @make_list(i32* nocapture readonly %data, i32* nocapture %value, i32* nocapture %all) {
 entry:
   %call = tail call i8* @malloc(i64 16)
-  %next = getelementptr inbounds i8* %call, i64 8
+  %next = getelementptr inbounds i8, i8* %call, i64 8
   %tmp = bitcast i8* %next to %struct._list**
   %tmp2 = bitcast i8* %call to %struct._list*
-  %.pre78 = load i32* @ncol, align 4
+  %.pre78 = load i32, i32* @ncol, align 4
   br label %for.cond1.preheader
 
 for.cond1.preheader:                              ; preds = %for.inc32, %entry
@@ -60,7 +60,7 @@ for.body3:                                        ; preds = %if.end31, %for.cond
   %row.172 = phi i32 [ %row.3, %if.end31 ], [ 0, %for.cond1.preheader ]
   %col.071 = phi i32 [ %inc, %if.end31 ], [ 0, %for.cond1.preheader ]
   %call4 = tail call i32* @make_data()
-  %tmp5 = load i32* @ncol, align 4
+  %tmp5 = load i32, i32* @ncol, align 4
   %tobool14.i = icmp eq i32 %tmp5, 0
   br i1 %tobool14.i, label %while.cond.i, label %while.body.lr.ph.i
 
@@ -83,10 +83,10 @@ while.cond.i:                                     ; preds = %land.rhs.i, %while.
   br i1 %tobool.i66, label %if.else, label %land.rhs.i
 
 land.rhs.i:                                       ; preds = %while.cond.i
-  %arrayidx.i67 = getelementptr inbounds i32* %call4, i64 %indvars.iv.next.i65
-  %tmp11 = load i32* %arrayidx.i67, align 4
-  %arrayidx2.i68 = getelementptr inbounds i32* %data, i64 %indvars.iv.next.i65
-  %tmp12 = load i32* %arrayidx2.i68, align 4
+  %arrayidx.i67 = getelementptr inbounds i32, i32* %call4, i64 %indvars.iv.next.i65
+  %tmp11 = load i32, i32* %arrayidx.i67, align 4
+  %arrayidx2.i68 = getelementptr inbounds i32, i32* %data, i64 %indvars.iv.next.i65
+  %tmp12 = load i32, i32* %arrayidx2.i68, align 4
   %cmp.i69 = icmp eq i32 %tmp11, %tmp12
   br i1 %cmp.i69, label %while.cond.i, label %equal_data.exit
 
@@ -95,15 +95,15 @@ equal_data.exit:                                  ; preds = %land.rhs.i
   br i1 %cmp3.i, label %if.else, label %if.then
 
 if.then:                                          ; preds = %equal_data.exit
-  %next7 = getelementptr inbounds %struct._list* %current.173, i64 0, i32 1
-  %tmp14 = load %struct._list** %next7, align 8
-  %next12 = getelementptr inbounds %struct._list* %tmp14, i64 0, i32 1
+  %next7 = getelementptr inbounds %struct._list, %struct._list* %current.173, i64 0, i32 1
+  %tmp14 = load %struct._list*, %struct._list** %next7, align 8
+  %next12 = getelementptr inbounds %struct._list, %struct._list* %tmp14, i64 0, i32 1
   store %struct._list* null, %struct._list** %next12, align 8
-  %tmp15 = load %struct._list** %next7, align 8
-  %tmp16 = load i32* %value, align 4
+  %tmp15 = load %struct._list*, %struct._list** %next7, align 8
+  %tmp16 = load i32, i32* %value, align 4
   %cmp14 = icmp eq i32 %tmp16, 1
   %.tmp16 = select i1 %cmp14, i32 0, i32 %tmp16
-  %tmp18 = load i32* %all, align 4
+  %tmp18 = load i32, i32* %all, align 4
   %tmp19 = or i32 %tmp18, %.tmp16
   %tmp20 = icmp eq i32 %tmp19, 0
   br i1 %tmp20, label %if.then19, label %if.end31
@@ -123,12 +123,12 @@ if.end31:                                         ; preds = %if.else, %if.then19
   %row.3 = phi i32 [ %.row.172, %if.else ], [ %row.172, %if.then ], [ 0, %if.then19 ]
   %current.2 = phi %struct._list* [ %current.173, %if.else ], [ %tmp15, %if.then ], [ %tmp15, %if.then19 ]
   %inc = add nsw i32 %col.1, 1
-  %tmp25 = load i32* @ncol, align 4
+  %tmp25 = load i32, i32* @ncol, align 4
   %cmp2 = icmp eq i32 %inc, %tmp25
   br i1 %cmp2, label %for.cond1.for.inc32_crit_edge, label %for.body3
 
 for.cond1.for.inc32_crit_edge:                    ; preds = %if.end31
-  %.pre79 = load i32* @nrow, align 4
+  %.pre79 = load i32, i32* @nrow, align 4
   br label %for.inc32
 
 for.inc32:                                        ; preds = %for.cond1.for.inc32_crit_edge, %for.cond1.preheader
@@ -140,6 +140,6 @@ for.inc32:                                        ; preds = %for.cond1.for.inc32
   br i1 %cmp, label %for.end34, label %for.cond1.preheader
 
 for.end34:                                        ; preds = %for.inc32
-  %.pre = load %struct._list** %tmp, align 8
+  %.pre = load %struct._list*, %struct._list** %tmp, align 8
   ret %struct._list* %.pre
 }
diff --git a/test/CodeGen/X86/regpressure.ll b/test/CodeGen/X86/regpressure.ll
index 1f756bee8a9d..8f352b8fbb5a 100644
--- a/test/CodeGen/X86/regpressure.ll
+++ b/test/CodeGen/X86/regpressure.ll
@@ -9,57 +9,57 @@
 ;; folded into the multiplies, 2 registers otherwise.
 
 define i32 @regpressure1(i32* %P) {
-	%A = load i32* %P		; <i32> [#uses=1]
-	%Bp = getelementptr i32* %P, i32 1		; <i32*> [#uses=1]
-	%B = load i32* %Bp		; <i32> [#uses=1]
+	%A = load i32, i32* %P		; <i32> [#uses=1]
+	%Bp = getelementptr i32, i32* %P, i32 1		; <i32*> [#uses=1]
+	%B = load i32, i32* %Bp		; <i32> [#uses=1]
 	%s1 = mul i32 %A, %B		; <i32> [#uses=1]
-	%Cp = getelementptr i32* %P, i32 2		; <i32*> [#uses=1]
-	%C = load i32* %Cp		; <i32> [#uses=1]
+	%Cp = getelementptr i32, i32* %P, i32 2		; <i32*> [#uses=1]
+	%C = load i32, i32* %Cp		; <i32> [#uses=1]
 	%s2 = mul i32 %s1, %C		; <i32> [#uses=1]
-	%Dp = getelementptr i32* %P, i32 3		; <i32*> [#uses=1]
-	%D = load i32* %Dp		; <i32> [#uses=1]
+	%Dp = getelementptr i32, i32* %P, i32 3		; <i32*> [#uses=1]
+	%D = load i32, i32* %Dp		; <i32> [#uses=1]
 	%s3 = mul i32 %s2, %D		; <i32> [#uses=1]
-	%Ep = getelementptr i32* %P, i32 4		; <i32*> [#uses=1]
-	%E = load i32* %Ep		; <i32> [#uses=1]
+	%Ep = getelementptr i32, i32* %P, i32 4		; <i32*> [#uses=1]
+	%E = load i32, i32* %Ep		; <i32> [#uses=1]
 	%s4 = mul i32 %s3, %E		; <i32> [#uses=1]
-	%Fp = getelementptr i32* %P, i32 5		; <i32*> [#uses=1]
-	%F = load i32* %Fp		; <i32> [#uses=1]
+	%Fp = getelementptr i32, i32* %P, i32 5		; <i32*> [#uses=1]
+	%F = load i32, i32* %Fp		; <i32> [#uses=1]
 	%s5 = mul i32 %s4, %F		; <i32> [#uses=1]
-	%Gp = getelementptr i32* %P, i32 6		; <i32*> [#uses=1]
-	%G = load i32* %Gp		; <i32> [#uses=1]
+	%Gp = getelementptr i32, i32* %P, i32 6		; <i32*> [#uses=1]
+	%G = load i32, i32* %Gp		; <i32> [#uses=1]
 	%s6 = mul i32 %s5, %G		; <i32> [#uses=1]
-	%Hp = getelementptr i32* %P, i32 7		; <i32*> [#uses=1]
-	%H = load i32* %Hp		; <i32> [#uses=1]
+	%Hp = getelementptr i32, i32* %P, i32 7		; <i32*> [#uses=1]
+	%H = load i32, i32* %Hp		; <i32> [#uses=1]
 	%s7 = mul i32 %s6, %H		; <i32> [#uses=1]
-	%Ip = getelementptr i32* %P, i32 8		; <i32*> [#uses=1]
-	%I = load i32* %Ip		; <i32> [#uses=1]
+	%Ip = getelementptr i32, i32* %P, i32 8		; <i32*> [#uses=1]
+	%I = load i32, i32* %Ip		; <i32> [#uses=1]
 	%s8 = mul i32 %s7, %I		; <i32> [#uses=1]
-	%Jp = getelementptr i32* %P, i32 9		; <i32*> [#uses=1]
-	%J = load i32* %Jp		; <i32> [#uses=1]
+	%Jp = getelementptr i32, i32* %P, i32 9		; <i32*> [#uses=1]
+	%J = load i32, i32* %Jp		; <i32> [#uses=1]
 	%s9 = mul i32 %s8, %J		; <i32> [#uses=1]
 	ret i32 %s9
 }
 
 define i32 @regpressure2(i32* %P) {
-	%A = load i32* %P		; <i32> [#uses=1]
-	%Bp = getelementptr i32* %P, i32 1		; <i32*> [#uses=1]
-	%B = load i32* %Bp		; <i32> [#uses=1]
-	%Cp = getelementptr i32* %P, i32 2		; <i32*> [#uses=1]
-	%C = load i32* %Cp		; <i32> [#uses=1]
-	%Dp = getelementptr i32* %P, i32 3		; <i32*> [#uses=1]
-	%D = load i32* %Dp		; <i32> [#uses=1]
-	%Ep = getelementptr i32* %P, i32 4		; <i32*> [#uses=1]
-	%E = load i32* %Ep		; <i32> [#uses=1]
-	%Fp = getelementptr i32* %P, i32 5		; <i32*> [#uses=1]
-	%F = load i32* %Fp		; <i32> [#uses=1]
-	%Gp = getelementptr i32* %P, i32 6		; <i32*> [#uses=1]
-	%G = load i32* %Gp		; <i32> [#uses=1]
-	%Hp = getelementptr i32* %P, i32 7		; <i32*> [#uses=1]
-	%H = load i32* %Hp		; <i32> [#uses=1]
-	%Ip = getelementptr i32* %P, i32 8		; <i32*> [#uses=1]
-	%I = load i32* %Ip		; <i32> [#uses=1]
-	%Jp = getelementptr i32* %P, i32 9		; <i32*> [#uses=1]
-	%J = load i32* %Jp		; <i32> [#uses=1]
+	%A = load i32, i32* %P		; <i32> [#uses=1]
+	%Bp = getelementptr i32, i32* %P, i32 1		; <i32*> [#uses=1]
+	%B = load i32, i32* %Bp		; <i32> [#uses=1]
+	%Cp = getelementptr i32, i32* %P, i32 2		; <i32*> [#uses=1]
+	%C = load i32, i32* %Cp		; <i32> [#uses=1]
+	%Dp = getelementptr i32, i32* %P, i32 3		; <i32*> [#uses=1]
+	%D = load i32, i32* %Dp		; <i32> [#uses=1]
+	%Ep = getelementptr i32, i32* %P, i32 4		; <i32*> [#uses=1]
+	%E = load i32, i32* %Ep		; <i32> [#uses=1]
+	%Fp = getelementptr i32, i32* %P, i32 5		; <i32*> [#uses=1]
+	%F = load i32, i32* %Fp		; <i32> [#uses=1]
+	%Gp = getelementptr i32, i32* %P, i32 6		; <i32*> [#uses=1]
+	%G = load i32, i32* %Gp		; <i32> [#uses=1]
+	%Hp = getelementptr i32, i32* %P, i32 7		; <i32*> [#uses=1]
+	%H = load i32, i32* %Hp		; <i32> [#uses=1]
+	%Ip = getelementptr i32, i32* %P, i32 8		; <i32*> [#uses=1]
+	%I = load i32, i32* %Ip		; <i32> [#uses=1]
+	%Jp = getelementptr i32, i32* %P, i32 9		; <i32*> [#uses=1]
+	%J = load i32, i32* %Jp		; <i32> [#uses=1]
 	%s1 = mul i32 %A, %B		; <i32> [#uses=1]
 	%s2 = mul i32 %s1, %C		; <i32> [#uses=1]
 	%s3 = mul i32 %s2, %D		; <i32> [#uses=1]
@@ -73,25 +73,25 @@ define i32 @regpressure2(i32* %P) {
 }
 
 define i32 @regpressure3(i16* %P, i1 %Cond, i32* %Other) {
-	%A = load i16* %P		; <i16> [#uses=1]
-	%Bp = getelementptr i16* %P, i32 1		; <i16*> [#uses=1]
-	%B = load i16* %Bp		; <i16> [#uses=1]
-	%Cp = getelementptr i16* %P, i32 2		; <i16*> [#uses=1]
-	%C = load i16* %Cp		; <i16> [#uses=1]
-	%Dp = getelementptr i16* %P, i32 3		; <i16*> [#uses=1]
-	%D = load i16* %Dp		; <i16> [#uses=1]
-	%Ep = getelementptr i16* %P, i32 4		; <i16*> [#uses=1]
-	%E = load i16* %Ep		; <i16> [#uses=1]
-	%Fp = getelementptr i16* %P, i32 5		; <i16*> [#uses=1]
-	%F = load i16* %Fp		; <i16> [#uses=1]
-	%Gp = getelementptr i16* %P, i32 6		; <i16*> [#uses=1]
-	%G = load i16* %Gp		; <i16> [#uses=1]
-	%Hp = getelementptr i16* %P, i32 7		; <i16*> [#uses=1]
-	%H = load i16* %Hp		; <i16> [#uses=1]
-	%Ip = getelementptr i16* %P, i32 8		; <i16*> [#uses=1]
-	%I = load i16* %Ip		; <i16> [#uses=1]
-	%Jp = getelementptr i16* %P, i32 9		; <i16*> [#uses=1]
-	%J = load i16* %Jp		; <i16> [#uses=1]
+	%A = load i16, i16* %P		; <i16> [#uses=1]
+	%Bp = getelementptr i16, i16* %P, i32 1		; <i16*> [#uses=1]
+	%B = load i16, i16* %Bp		; <i16> [#uses=1]
+	%Cp = getelementptr i16, i16* %P, i32 2		; <i16*> [#uses=1]
+	%C = load i16, i16* %Cp		; <i16> [#uses=1]
+	%Dp = getelementptr i16, i16* %P, i32 3		; <i16*> [#uses=1]
+	%D = load i16, i16* %Dp		; <i16> [#uses=1]
+	%Ep = getelementptr i16, i16* %P, i32 4		; <i16*> [#uses=1]
+	%E = load i16, i16* %Ep		; <i16> [#uses=1]
+	%Fp = getelementptr i16, i16* %P, i32 5		; <i16*> [#uses=1]
+	%F = load i16, i16* %Fp		; <i16> [#uses=1]
+	%Gp = getelementptr i16, i16* %P, i32 6		; <i16*> [#uses=1]
+	%G = load i16, i16* %Gp		; <i16> [#uses=1]
+	%Hp = getelementptr i16, i16* %P, i32 7		; <i16*> [#uses=1]
+	%H = load i16, i16* %Hp		; <i16> [#uses=1]
+	%Ip = getelementptr i16, i16* %P, i32 8		; <i16*> [#uses=1]
+	%I = load i16, i16* %Ip		; <i16> [#uses=1]
+	%Jp = getelementptr i16, i16* %P, i32 9		; <i16*> [#uses=1]
+	%J = load i16, i16* %Jp		; <i16> [#uses=1]
 	%A.upgrd.1 = sext i16 %A to i32		; <i32> [#uses=1]
 	%B.upgrd.2 = sext i16 %B to i32		; <i32> [#uses=1]
 	%D.upgrd.3 = sext i16 %D to i32		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/remat-constant.ll b/test/CodeGen/X86/remat-constant.ll
index 3e813209d410..5a6826f38090 100644
--- a/test/CodeGen/X86/remat-constant.ll
+++ b/test/CodeGen/X86/remat-constant.ll
@@ -7,7 +7,7 @@ declare void @bar() nounwind
 declare void @qux(float %f) nounwind 
 
 define void @foo() nounwind  {
-  %f = load float* @a
+  %f = load float, float* @a
   call void @bar()
   call void @qux(float %f)
   call void @qux(float %f)
diff --git a/test/CodeGen/X86/remat-fold-load.ll b/test/CodeGen/X86/remat-fold-load.ll
index de77ad375672..3478033bfbf1 100644
--- a/test/CodeGen/X86/remat-fold-load.ll
+++ b/test/CodeGen/X86/remat-fold-load.ll
@@ -38,26 +38,26 @@ while.body12:                                     ; preds = %if.end24, %while.bo
 
 if.then.i.i.i.i71:                                ; preds = %while.body12
   %call4.i.i.i.i68 = call noalias i8* @malloc(i32 undef) nounwind
-  %tmp1 = getelementptr inbounds %type_a* %tmp, i32 0, i32 1, i32 0, i32 1
+  %tmp1 = getelementptr inbounds %type_a, %type_a* %tmp, i32 0, i32 1, i32 0, i32 1
   %buf_6.i.i.i.i70 = bitcast %type_d* %tmp1 to i8**
-  %tmp2 = load i8** %buf_6.i.i.i.i70, align 4
+  %tmp2 = load i8*, i8** %buf_6.i.i.i.i70, align 4
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* %tmp2, i32 undef, i32 1, i1 false) nounwind
   unreachable
 
 if.else.i.i.i.i74:                                ; preds = %while.body12
-  %i_.i.i.i.i72 = getelementptr inbounds %type_a* %tmp, i32 0, i32 1, i32 0, i32 1, i32 0
-  %tmp3 = load i64* %i_.i.i.i.i72, align 4
+  %i_.i.i.i.i72 = getelementptr inbounds %type_a, %type_a* %tmp, i32 0, i32 1, i32 0, i32 1, i32 0
+  %tmp3 = load i64, i64* %i_.i.i.i.i72, align 4
   %tmp4 = zext i64 %tmp3 to i128
   %tmp5 = shl nuw nsw i128 %tmp4, 32
   %ins148 = or i128 %tmp5, %ins151
-  %second3.i.i76 = getelementptr inbounds %type_a* %tmp, i32 0, i32 1, i32 1
-  %tmp6 = load i32* %second3.i.i76, align 4
+  %second3.i.i76 = getelementptr inbounds %type_a, %type_a* %tmp, i32 0, i32 1, i32 1
+  %tmp6 = load i32, i32* %second3.i.i76, align 4
   %tmp7 = zext i32 %tmp6 to i128
   %tmp8 = shl nuw i128 %tmp7, 96
   %mask144 = and i128 %ins148, 79228162495817593519834398720
-  %tmp9 = load %type_e** undef, align 4
-  %len_.i.i.i.i86 = getelementptr inbounds %type_e* %tmp9, i32 0, i32 0, i32 0
-  %tmp10 = load i32* %len_.i.i.i.i86, align 4
+  %tmp9 = load %type_e*, %type_e** undef, align 4
+  %len_.i.i.i.i86 = getelementptr inbounds %type_e, %type_e* %tmp9, i32 0, i32 0, i32 0
+  %tmp10 = load i32, i32* %len_.i.i.i.i86, align 4
   %tmp11 = zext i32 %tmp10 to i128
   %ins135 = or i128 %tmp11, %ins135156160
   %cmp.i.i.i.i.i88 = icmp sgt i32 %tmp10, 8
@@ -66,20 +66,20 @@ if.else.i.i.i.i74:                                ; preds = %while.body12
 if.then.i.i.i.i92:                                ; preds = %if.else.i.i.i.i74
   %call4.i.i.i.i89 = call noalias i8* @malloc(i32 %tmp10) nounwind
   %ins126 = or i128 0, %ins135
-  %tmp12 = getelementptr inbounds %type_e* %tmp9, i32 0, i32 0, i32 1
+  %tmp12 = getelementptr inbounds %type_e, %type_e* %tmp9, i32 0, i32 0, i32 1
   %buf_6.i.i.i.i91 = bitcast %type_d* %tmp12 to i8**
-  %tmp13 = load i8** %buf_6.i.i.i.i91, align 4
+  %tmp13 = load i8*, i8** %buf_6.i.i.i.i91, align 4
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %call4.i.i.i.i89, i8* %tmp13, i32 %tmp10, i32 1, i1 false) nounwind
   br label %A
 
 if.else.i.i.i.i95:                                ; preds = %if.else.i.i.i.i74
-  %i_.i.i.i.i93 = getelementptr inbounds %type_e* %tmp9, i32 0, i32 0, i32 1, i32 0
+  %i_.i.i.i.i93 = getelementptr inbounds %type_e, %type_e* %tmp9, i32 0, i32 0, i32 1, i32 0
   br label %A
 
 A:                                                ; preds = %if.else.i.i.i.i95, %if.then.i.i.i.i92
   %ins135157 = phi i128 [ %ins126, %if.then.i.i.i.i92 ], [ undef, %if.else.i.i.i.i95 ]
-  %second3.i.i97 = getelementptr inbounds %type_e* %tmp9, i32 0, i32 1
-  %tmp14 = load i64* %second3.i.i97, align 4
+  %second3.i.i97 = getelementptr inbounds %type_e, %type_e* %tmp9, i32 0, i32 1
+  %tmp14 = load i64, i64* %second3.i.i97, align 4
   %tmp15 = trunc i64 %tmp14 to i32
   %cmp.i99 = icmp sgt i32 %tmp6, %tmp15
   %tmp16 = trunc i128 %ins135157 to i32
@@ -118,13 +118,13 @@ E:                                                ; preds = %D
 if.end24:                                         ; preds = %E, %C
   %phitmp = or i128 %tmp8, %mask144
   %phitmp158 = or i128 undef, undef
-  %tmp18 = load %type_a** undef, align 4
-  %tmp19 = load %type_a** undef, align 4
+  %tmp18 = load %type_a*, %type_a** undef, align 4
+  %tmp19 = load %type_a*, %type_a** undef, align 4
   %cmp.i49 = icmp eq %type_a* %tmp18, %tmp19
   br i1 %cmp.i49, label %while.cond10.while.end26_crit_edge, label %while.body12
 
 while.cond10.while.end26_crit_edge:               ; preds = %if.end24
-  %.pre = load %type_e** undef, align 4
+  %.pre = load %type_e*, %type_e** undef, align 4
   br label %while.end26
 
 while.end26:                                      ; preds = %while.cond10.while.end26_crit_edge, %while.end.while.end26_crit_edge
diff --git a/test/CodeGen/X86/remat-invalid-liveness.ll b/test/CodeGen/X86/remat-invalid-liveness.ll
index d285e83b7981..c6b43b0dd3e4 100644
--- a/test/CodeGen/X86/remat-invalid-liveness.ll
+++ b/test/CodeGen/X86/remat-invalid-liveness.ll
@@ -40,7 +40,7 @@ entry:
 
 sw.bb.i:                                          ; preds = %entry
   %call.i.i.i = tail call i32 undef(%struct.A* %ht, i8 zeroext 22, i32 undef, i32 0, %struct.D* undef)
-  %bf.load.i.i = load i128* undef, align 4
+  %bf.load.i.i = load i128, i128* undef, align 4
   %bf.lshr.i.i = lshr i128 %bf.load.i.i, %const72
   %shl1.i.i = shl nuw nsw i128 %bf.lshr.i.i, 8
   %shl.i.i = trunc i128 %shl1.i.i to i32
@@ -50,22 +50,22 @@ __XXX2.exit.i.i:                    ; preds = %sw.bb.i
   %extract11.i.i.i = lshr i128 %bf.load.i.i, %const3
   %extract.t12.i.i.i = trunc i128 %extract11.i.i.i to i32
   %bf.cast7.i.i.i = and i32 %extract.t12.i.i.i, 3
-  %arrayidx.i.i.i = getelementptr inbounds %struct.A* %ht, i32 0, i32 3, i32 %bf.cast7.i.i.i
+  %arrayidx.i.i.i = getelementptr inbounds %struct.A, %struct.A* %ht, i32 0, i32 3, i32 %bf.cast7.i.i.i
   br label %cond.end12.i.i
 
 cond.false10.i.i:                                 ; preds = %sw.bb.i
-  %arrayidx.i6.i.i = getelementptr inbounds %struct.A* %ht, i32 0, i32 3, i32 0
+  %arrayidx.i6.i.i = getelementptr inbounds %struct.A, %struct.A* %ht, i32 0, i32 3, i32 0
   br label %cond.end12.i.i
 
 cond.end12.i.i:                                   ; preds = %cond.false10.i.i, %__XXX2.exit.i.i
   %.sink.in.i.i = phi i8** [ %arrayidx.i.i.i, %__XXX2.exit.i.i ], [ %arrayidx.i6.i.i, %cond.false10.i.i ]
-  %.sink.i.i = load i8** %.sink.in.i.i, align 4
+  %.sink.i.i = load i8*, i8** %.sink.in.i.i, align 4
   %tmp = bitcast i8* %.sink.i.i to %union.E*
   br i1 undef, label %for.body.i.i, label %if.end196
 
 for.body.i.i:                                     ; preds = %for.body.i.i, %cond.end12.i.i
-  %weak.i.i = getelementptr inbounds %union.E* %tmp, i32 undef, i32 0
-  %tmp1 = load i32* %weak.i.i, align 4
+  %weak.i.i = getelementptr inbounds %union.E, %union.E* %tmp, i32 undef, i32 0
+  %tmp1 = load i32, i32* %weak.i.i, align 4
   %cmp36.i.i = icmp ne i32 %tmp1, %shl.i.i
   %or.cond = and i1 %cmp36.i.i, false
   br i1 %or.cond, label %for.body.i.i, label %if.end196
diff --git a/test/CodeGen/X86/remat-scalar-zero.ll b/test/CodeGen/X86/remat-scalar-zero.ll
index f6095a75561c..0f081937b241 100644
--- a/test/CodeGen/X86/remat-scalar-zero.ll
+++ b/test/CodeGen/X86/remat-scalar-zero.ll
@@ -10,88 +10,88 @@
 
 define void @foo(double* nocapture %x, double* nocapture %y) nounwind {
 entry:
-  %tmp1 = load double* %x                         ; <double> [#uses=1]
-  %arrayidx4 = getelementptr inbounds double* %x, i64 1 ; <double*> [#uses=1]
-  %tmp5 = load double* %arrayidx4                 ; <double> [#uses=1]
-  %arrayidx8 = getelementptr inbounds double* %x, i64 2 ; <double*> [#uses=1]
-  %tmp9 = load double* %arrayidx8                 ; <double> [#uses=1]
-  %arrayidx12 = getelementptr inbounds double* %x, i64 3 ; <double*> [#uses=1]
-  %tmp13 = load double* %arrayidx12               ; <double> [#uses=1]
-  %arrayidx16 = getelementptr inbounds double* %x, i64 4 ; <double*> [#uses=1]
-  %tmp17 = load double* %arrayidx16               ; <double> [#uses=1]
-  %arrayidx20 = getelementptr inbounds double* %x, i64 5 ; <double*> [#uses=1]
-  %tmp21 = load double* %arrayidx20               ; <double> [#uses=1]
-  %arrayidx24 = getelementptr inbounds double* %x, i64 6 ; <double*> [#uses=1]
-  %tmp25 = load double* %arrayidx24               ; <double> [#uses=1]
-  %arrayidx28 = getelementptr inbounds double* %x, i64 7 ; <double*> [#uses=1]
-  %tmp29 = load double* %arrayidx28               ; <double> [#uses=1]
-  %arrayidx32 = getelementptr inbounds double* %x, i64 8 ; <double*> [#uses=1]
-  %tmp33 = load double* %arrayidx32               ; <double> [#uses=1]
-  %arrayidx36 = getelementptr inbounds double* %x, i64 9 ; <double*> [#uses=1]
-  %tmp37 = load double* %arrayidx36               ; <double> [#uses=1]
-  %arrayidx40 = getelementptr inbounds double* %x, i64 10 ; <double*> [#uses=1]
-  %tmp41 = load double* %arrayidx40               ; <double> [#uses=1]
-  %arrayidx44 = getelementptr inbounds double* %x, i64 11 ; <double*> [#uses=1]
-  %tmp45 = load double* %arrayidx44               ; <double> [#uses=1]
-  %arrayidx48 = getelementptr inbounds double* %x, i64 12 ; <double*> [#uses=1]
-  %tmp49 = load double* %arrayidx48               ; <double> [#uses=1]
-  %arrayidx52 = getelementptr inbounds double* %x, i64 13 ; <double*> [#uses=1]
-  %tmp53 = load double* %arrayidx52               ; <double> [#uses=1]
-  %arrayidx56 = getelementptr inbounds double* %x, i64 14 ; <double*> [#uses=1]
-  %tmp57 = load double* %arrayidx56               ; <double> [#uses=1]
-  %arrayidx60 = getelementptr inbounds double* %x, i64 15 ; <double*> [#uses=1]
-  %tmp61 = load double* %arrayidx60               ; <double> [#uses=1]
-  %arrayidx64 = getelementptr inbounds double* %x, i64 16 ; <double*> [#uses=1]
-  %tmp65 = load double* %arrayidx64               ; <double> [#uses=1]
+  %tmp1 = load double, double* %x                         ; <double> [#uses=1]
+  %arrayidx4 = getelementptr inbounds double, double* %x, i64 1 ; <double*> [#uses=1]
+  %tmp5 = load double, double* %arrayidx4                 ; <double> [#uses=1]
+  %arrayidx8 = getelementptr inbounds double, double* %x, i64 2 ; <double*> [#uses=1]
+  %tmp9 = load double, double* %arrayidx8                 ; <double> [#uses=1]
+  %arrayidx12 = getelementptr inbounds double, double* %x, i64 3 ; <double*> [#uses=1]
+  %tmp13 = load double, double* %arrayidx12               ; <double> [#uses=1]
+  %arrayidx16 = getelementptr inbounds double, double* %x, i64 4 ; <double*> [#uses=1]
+  %tmp17 = load double, double* %arrayidx16               ; <double> [#uses=1]
+  %arrayidx20 = getelementptr inbounds double, double* %x, i64 5 ; <double*> [#uses=1]
+  %tmp21 = load double, double* %arrayidx20               ; <double> [#uses=1]
+  %arrayidx24 = getelementptr inbounds double, double* %x, i64 6 ; <double*> [#uses=1]
+  %tmp25 = load double, double* %arrayidx24               ; <double> [#uses=1]
+  %arrayidx28 = getelementptr inbounds double, double* %x, i64 7 ; <double*> [#uses=1]
+  %tmp29 = load double, double* %arrayidx28               ; <double> [#uses=1]
+  %arrayidx32 = getelementptr inbounds double, double* %x, i64 8 ; <double*> [#uses=1]
+  %tmp33 = load double, double* %arrayidx32               ; <double> [#uses=1]
+  %arrayidx36 = getelementptr inbounds double, double* %x, i64 9 ; <double*> [#uses=1]
+  %tmp37 = load double, double* %arrayidx36               ; <double> [#uses=1]
+  %arrayidx40 = getelementptr inbounds double, double* %x, i64 10 ; <double*> [#uses=1]
+  %tmp41 = load double, double* %arrayidx40               ; <double> [#uses=1]
+  %arrayidx44 = getelementptr inbounds double, double* %x, i64 11 ; <double*> [#uses=1]
+  %tmp45 = load double, double* %arrayidx44               ; <double> [#uses=1]
+  %arrayidx48 = getelementptr inbounds double, double* %x, i64 12 ; <double*> [#uses=1]
+  %tmp49 = load double, double* %arrayidx48               ; <double> [#uses=1]
+  %arrayidx52 = getelementptr inbounds double, double* %x, i64 13 ; <double*> [#uses=1]
+  %tmp53 = load double, double* %arrayidx52               ; <double> [#uses=1]
+  %arrayidx56 = getelementptr inbounds double, double* %x, i64 14 ; <double*> [#uses=1]
+  %tmp57 = load double, double* %arrayidx56               ; <double> [#uses=1]
+  %arrayidx60 = getelementptr inbounds double, double* %x, i64 15 ; <double*> [#uses=1]
+  %tmp61 = load double, double* %arrayidx60               ; <double> [#uses=1]
+  %arrayidx64 = getelementptr inbounds double, double* %x, i64 16 ; <double*> [#uses=1]
+  %tmp65 = load double, double* %arrayidx64               ; <double> [#uses=1]
   %div = fdiv double %tmp1, 0.000000e+00          ; <double> [#uses=1]
   store double %div, double* %y
   %div70 = fdiv double %tmp5, 2.000000e-01        ; <double> [#uses=1]
-  %arrayidx72 = getelementptr inbounds double* %y, i64 1 ; <double*> [#uses=1]
+  %arrayidx72 = getelementptr inbounds double, double* %y, i64 1 ; <double*> [#uses=1]
   store double %div70, double* %arrayidx72
   %div74 = fdiv double %tmp9, 2.000000e-01        ; <double> [#uses=1]
-  %arrayidx76 = getelementptr inbounds double* %y, i64 2 ; <double*> [#uses=1]
+  %arrayidx76 = getelementptr inbounds double, double* %y, i64 2 ; <double*> [#uses=1]
   store double %div74, double* %arrayidx76
   %div78 = fdiv double %tmp13, 2.000000e-01       ; <double> [#uses=1]
-  %arrayidx80 = getelementptr inbounds double* %y, i64 3 ; <double*> [#uses=1]
+  %arrayidx80 = getelementptr inbounds double, double* %y, i64 3 ; <double*> [#uses=1]
   store double %div78, double* %arrayidx80
   %div82 = fdiv double %tmp17, 2.000000e-01       ; <double> [#uses=1]
-  %arrayidx84 = getelementptr inbounds double* %y, i64 4 ; <double*> [#uses=1]
+  %arrayidx84 = getelementptr inbounds double, double* %y, i64 4 ; <double*> [#uses=1]
   store double %div82, double* %arrayidx84
   %div86 = fdiv double %tmp21, 2.000000e-01       ; <double> [#uses=1]
-  %arrayidx88 = getelementptr inbounds double* %y, i64 5 ; <double*> [#uses=1]
+  %arrayidx88 = getelementptr inbounds double, double* %y, i64 5 ; <double*> [#uses=1]
   store double %div86, double* %arrayidx88
   %div90 = fdiv double %tmp25, 2.000000e-01       ; <double> [#uses=1]
-  %arrayidx92 = getelementptr inbounds double* %y, i64 6 ; <double*> [#uses=1]
+  %arrayidx92 = getelementptr inbounds double, double* %y, i64 6 ; <double*> [#uses=1]
   store double %div90, double* %arrayidx92
   %div94 = fdiv double %tmp29, 2.000000e-01       ; <double> [#uses=1]
-  %arrayidx96 = getelementptr inbounds double* %y, i64 7 ; <double*> [#uses=1]
+  %arrayidx96 = getelementptr inbounds double, double* %y, i64 7 ; <double*> [#uses=1]
   store double %div94, double* %arrayidx96
   %div98 = fdiv double %tmp33, 2.000000e-01       ; <double> [#uses=1]
-  %arrayidx100 = getelementptr inbounds double* %y, i64 8 ; <double*> [#uses=1]
+  %arrayidx100 = getelementptr inbounds double, double* %y, i64 8 ; <double*> [#uses=1]
   store double %div98, double* %arrayidx100
   %div102 = fdiv double %tmp37, 2.000000e-01      ; <double> [#uses=1]
-  %arrayidx104 = getelementptr inbounds double* %y, i64 9 ; <double*> [#uses=1]
+  %arrayidx104 = getelementptr inbounds double, double* %y, i64 9 ; <double*> [#uses=1]
   store double %div102, double* %arrayidx104
   %div106 = fdiv double %tmp41, 2.000000e-01      ; <double> [#uses=1]
-  %arrayidx108 = getelementptr inbounds double* %y, i64 10 ; <double*> [#uses=1]
+  %arrayidx108 = getelementptr inbounds double, double* %y, i64 10 ; <double*> [#uses=1]
   store double %div106, double* %arrayidx108
   %div110 = fdiv double %tmp45, 2.000000e-01      ; <double> [#uses=1]
-  %arrayidx112 = getelementptr inbounds double* %y, i64 11 ; <double*> [#uses=1]
+  %arrayidx112 = getelementptr inbounds double, double* %y, i64 11 ; <double*> [#uses=1]
   store double %div110, double* %arrayidx112
   %div114 = fdiv double %tmp49, 2.000000e-01      ; <double> [#uses=1]
-  %arrayidx116 = getelementptr inbounds double* %y, i64 12 ; <double*> [#uses=1]
+  %arrayidx116 = getelementptr inbounds double, double* %y, i64 12 ; <double*> [#uses=1]
   store double %div114, double* %arrayidx116
   %div118 = fdiv double %tmp53, 2.000000e-01      ; <double> [#uses=1]
-  %arrayidx120 = getelementptr inbounds double* %y, i64 13 ; <double*> [#uses=1]
+  %arrayidx120 = getelementptr inbounds double, double* %y, i64 13 ; <double*> [#uses=1]
   store double %div118, double* %arrayidx120
   %div122 = fdiv double %tmp57, 2.000000e-01      ; <double> [#uses=1]
-  %arrayidx124 = getelementptr inbounds double* %y, i64 14 ; <double*> [#uses=1]
+  %arrayidx124 = getelementptr inbounds double, double* %y, i64 14 ; <double*> [#uses=1]
   store double %div122, double* %arrayidx124
   %div126 = fdiv double %tmp61, 2.000000e-01      ; <double> [#uses=1]
-  %arrayidx128 = getelementptr inbounds double* %y, i64 15 ; <double*> [#uses=1]
+  %arrayidx128 = getelementptr inbounds double, double* %y, i64 15 ; <double*> [#uses=1]
   store double %div126, double* %arrayidx128
   %div130 = fdiv double %tmp65, 0.000000e+00      ; <double> [#uses=1]
-  %arrayidx132 = getelementptr inbounds double* %y, i64 16 ; <double*> [#uses=1]
+  %arrayidx132 = getelementptr inbounds double, double* %y, i64 16 ; <double*> [#uses=1]
   store double %div130, double* %arrayidx132
   ret void
 }
diff --git a/test/CodeGen/X86/reverse_branches.ll b/test/CodeGen/X86/reverse_branches.ll
index ee6333e61e88..83a172b8de17 100644
--- a/test/CodeGen/X86/reverse_branches.ll
+++ b/test/CodeGen/X86/reverse_branches.ll
@@ -30,15 +30,15 @@ for.cond1:
   br i1 %cmp2, label %for.body3, label %for.inc9
 
 for.body3:
-  %arraydecay = getelementptr inbounds [1000 x [1001 x i8]]* %strs, i64 0, i64 %indvars.iv50, i64 0
+  %arraydecay = getelementptr inbounds [1000 x [1001 x i8]], [1000 x [1001 x i8]]* %strs, i64 0, i64 %indvars.iv50, i64 0
   %call = call i8* @memchr(i8* %arraydecay, i32 120, i64 1000)
-  %add.ptr = getelementptr inbounds [1000 x [1001 x i8]]* %strs, i64 0, i64 %indvars.iv50, i64 %indvars.iv50
+  %add.ptr = getelementptr inbounds [1000 x [1001 x i8]], [1000 x [1001 x i8]]* %strs, i64 0, i64 %indvars.iv50, i64 %indvars.iv50
   %cmp7 = icmp eq i8* %call, %add.ptr
   %indvars.iv.next51 = add i64 %indvars.iv50, 1
   br i1 %cmp7, label %for.cond1, label %if.then
 
 if.then:
-  %puts = call i32 @puts(i8* getelementptr inbounds ([5 x i8]* @str4, i64 0, i64 0))
+  %puts = call i32 @puts(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @str4, i64 0, i64 0))
   call void @exit(i32 1) noreturn
   unreachable
 
@@ -47,7 +47,7 @@ for.inc9:
   br label %for.cond
 
 for.end11:
-  %puts42 = call i32 @puts(i8* getelementptr inbounds ([7 x i8]* @.str2, i64 0, i64 0))
+  %puts42 = call i32 @puts(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str2, i64 0, i64 0))
   br label %for.cond14
 
 for.cond14:
@@ -62,30 +62,30 @@ for.cond18:
   br i1 %cmp19, label %for.body20, label %for.inc38
 
 for.body20:
-  %arraydecay24 = getelementptr inbounds [1000 x [1001 x i8]]* %strs, i64 0, i64 %indvars.iv, i64 0
+  %arraydecay24 = getelementptr inbounds [1000 x [1001 x i8]], [1000 x [1001 x i8]]* %strs, i64 0, i64 %indvars.iv, i64 0
   br label %do.body.i
 
 do.body.i:
   %n.addr.0.i = phi i64 [ %dec.i, %do.cond.i ], [ 1000, %for.body20 ]
   %p.0.i = phi i8* [ %incdec.ptr.i, %do.cond.i ], [ %arraydecay24, %for.body20 ]
-  %2 = load i8* %p.0.i, align 1
+  %2 = load i8, i8* %p.0.i, align 1
   %cmp3.i = icmp eq i8 %2, 120
   br i1 %cmp3.i, label %exit, label %do.cond.i
 
 do.cond.i:
-  %incdec.ptr.i = getelementptr inbounds i8* %p.0.i, i64 1
+  %incdec.ptr.i = getelementptr inbounds i8, i8* %p.0.i, i64 1
   %dec.i = add i64 %n.addr.0.i, -1
   %cmp5.i = icmp eq i64 %dec.i, 0
   br i1 %cmp5.i, label %if.then32, label %do.body.i
 
 exit:
-  %add.ptr30 = getelementptr inbounds [1000 x [1001 x i8]]* %strs, i64 0, i64 %indvars.iv, i64 %indvars.iv
+  %add.ptr30 = getelementptr inbounds [1000 x [1001 x i8]], [1000 x [1001 x i8]]* %strs, i64 0, i64 %indvars.iv, i64 %indvars.iv
   %cmp31 = icmp eq i8* %p.0.i, %add.ptr30
   %indvars.iv.next = add i64 %indvars.iv, 1
   br i1 %cmp31, label %for.cond18, label %if.then32
 
 if.then32:
-  %puts43 = call i32 @puts(i8* getelementptr inbounds ([5 x i8]* @str4, i64 0, i64 0))
+  %puts43 = call i32 @puts(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @str4, i64 0, i64 0))
   call void @exit(i32 1) noreturn
   unreachable
 
@@ -94,7 +94,7 @@ for.inc38:
   br label %for.cond14
 
 for.end40:
-  %puts44 = call i32 @puts(i8* getelementptr inbounds ([11 x i8]* @.str3, i64 0, i64 0))
+  %puts44 = call i32 @puts(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str3, i64 0, i64 0))
   ret i32 0
 }
 
diff --git a/test/CodeGen/X86/rip-rel-address.ll b/test/CodeGen/X86/rip-rel-address.ll
index 24ff07b4b219..b49d597d9f05 100644
--- a/test/CodeGen/X86/rip-rel-address.ll
+++ b/test/CodeGen/X86/rip-rel-address.ll
@@ -6,7 +6,7 @@
 
 @a = internal global double 3.4
 define double @foo() nounwind {
-  %a = load double* @a
+  %a = load double, double* @a
   ret double %a
   
 ; PIC64:    movsd	_a(%rip), %xmm0
diff --git a/test/CodeGen/X86/rip-rel-lea.ll b/test/CodeGen/X86/rip-rel-lea.ll
index 71dacf60caa1..6d78aabb5c2f 100644
--- a/test/CodeGen/X86/rip-rel-lea.ll
+++ b/test/CodeGen/X86/rip-rel-lea.ll
@@ -7,7 +7,7 @@
 
 @a = internal global double 3.4
 define double* @foo() nounwind {
-  %a = getelementptr double* @a, i64 0
+  %a = getelementptr double, double* @a, i64 0
   ret double* %a
   
 ; PIC64:    leaq	a(%rip)
diff --git a/test/CodeGen/X86/rot32.ll b/test/CodeGen/X86/rot32.ll
index 7bdd606e9cbb..5738f70fa47e 100644
--- a/test/CodeGen/X86/rot32.ll
+++ b/test/CodeGen/X86/rot32.ll
@@ -61,7 +61,7 @@ define i32 @xfoop(i32* %p) nounwind readnone {
 entry:
 ; BMI2-LABEL: xfoop:
 ; BMI2: rorxl $25, ({{.+}}), %{{.+}}
-	%x = load i32* %p
+	%x = load i32, i32* %p
 	%a = lshr i32 %x, 25
 	%b = shl i32 %x, 7
 	%c = or i32 %a, %b
@@ -94,7 +94,7 @@ define i32 @xunp(i32* %p) nounwind readnone {
 entry:
 ; BMI2-LABEL: xunp:
 ; BMI2: rorxl $7, ({{.+}}), %{{.+}}
-	%x = load i32* %p
+	%x = load i32, i32* %p
 	%a = lshr i32 %x, 7
 	%b = shl i32 %x, 25
 	%c = or i32 %a, %b
diff --git a/test/CodeGen/X86/rot64.ll b/test/CodeGen/X86/rot64.ll
index e19a35da1cd6..f77bde050c78 100644
--- a/test/CodeGen/X86/rot64.ll
+++ b/test/CodeGen/X86/rot64.ll
@@ -55,7 +55,7 @@ define i64 @xfoop(i64* %p) nounwind readnone {
 entry:
 ; BMI2-LABEL: xfoop:
 ; BMI2: rorxq $57, ({{.+}}), %{{.+}}
-	%x = load i64* %p
+	%x = load i64, i64* %p
 	%a = lshr i64 %x, 57
 	%b = shl i64 %x, 7
 	%c = or i64 %a, %b
@@ -84,7 +84,7 @@ define i64 @xunp(i64* %p) nounwind readnone {
 entry:
 ; BMI2-LABEL: xunp:
 ; BMI2: rorxq $7, ({{.+}}), %{{.+}}
-	%x = load i64* %p
+	%x = load i64, i64* %p
 	%a = lshr i64 %x, 7
 	%b = shl i64 %x, 57
 	%c = or i64 %a, %b
diff --git a/test/CodeGen/X86/rotate4.ll b/test/CodeGen/X86/rotate4.ll
index 5372612aeab8..56a7d3285056 100644
--- a/test/CodeGen/X86/rotate4.ll
+++ b/test/CodeGen/X86/rotate4.ll
@@ -68,7 +68,7 @@ define void @rotate_left_m32(i32 *%pa, i32 %b) {
 ; no store:
 ; CHECK-NOT: mov
 entry:
-  %a = load i32* %pa, align 16
+  %a = load i32, i32* %pa, align 16
   %and = and i32 %b, 31
   %shl = shl i32 %a, %and
   %0 = sub i32 0, %b
@@ -86,7 +86,7 @@ define void @rotate_right_m32(i32 *%pa, i32 %b) {
 ; no store:
 ; CHECK-NOT: mov
 entry:
-  %a = load i32* %pa, align 16
+  %a = load i32, i32* %pa, align 16
   %and = and i32 %b, 31
   %shl = lshr i32 %a, %and
   %0 = sub i32 0, %b
@@ -104,7 +104,7 @@ define void @rotate_left_m64(i64 *%pa, i64 %b) {
 ; no store:
 ; CHECK-NOT: mov
 entry:
-  %a = load i64* %pa, align 16
+  %a = load i64, i64* %pa, align 16
   %and = and i64 %b, 63
   %shl = shl i64 %a, %and
   %0 = sub i64 0, %b
@@ -122,7 +122,7 @@ define void @rotate_right_m64(i64 *%pa, i64 %b) {
 ; no store:
 ; CHECK-NOT: mov
 entry:
-  %a = load i64* %pa, align 16
+  %a = load i64, i64* %pa, align 16
   %and = and i64 %b, 63
   %shl = lshr i64 %a, %and
   %0 = sub i64 0, %b
diff --git a/test/CodeGen/X86/sandybridge-loads.ll b/test/CodeGen/X86/sandybridge-loads.ll
index b8c364e2961c..2e31154068fc 100644
--- a/test/CodeGen/X86/sandybridge-loads.ll
+++ b/test/CodeGen/X86/sandybridge-loads.ll
@@ -8,10 +8,10 @@
 ;CHECK: ret
 
 define void @wideloads(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind uwtable noinline ssp {
-  %v0 = load <8 x float>* %a, align 16  ; <---- unaligned!
-  %v1 = load <8 x float>* %b, align 32  ; <---- aligned!
+  %v0 = load <8 x float>, <8 x float>* %a, align 16  ; <---- unaligned!
+  %v1 = load <8 x float>, <8 x float>* %b, align 32  ; <---- aligned!
   %m0 = fcmp olt <8 x float> %v1, %v0
-  %v2 = load <8 x float>* %c, align 32  ; <---- aligned!
+  %v2 = load <8 x float>, <8 x float>* %c, align 32  ; <---- aligned!
   %m1 = fcmp olt <8 x float> %v2, %v0
   %mand = and <8 x i1> %m1, %m0
   %r = zext <8 x i1> %mand to <8 x i32>
@@ -30,8 +30,8 @@ define void @wideloads(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwi
 ;CHECK: ret
 
 define void @widestores(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind uwtable noinline ssp {
-  %v0 = load <8 x float>* %a, align 32
-  %v1 = load <8 x float>* %b, align 32
+  %v0 = load <8 x float>, <8 x float>* %a, align 32
+  %v1 = load <8 x float>, <8 x float>* %b, align 32
   store <8 x float> %v0, <8 x float>* %b, align 32 ; <--- aligned
   store <8 x float> %v1, <8 x float>* %a, align 16 ; <--- unaligned
   ret void
diff --git a/test/CodeGen/X86/scalar-extract.ll b/test/CodeGen/X86/scalar-extract.ll
index 284583840933..b8ef5e74c436 100644
--- a/test/CodeGen/X86/scalar-extract.ll
+++ b/test/CodeGen/X86/scalar-extract.ll
@@ -6,7 +6,7 @@
 
 define void @foo(<2 x i16>* %A, <2 x i16>* %B) {
 entry:
-	%tmp1 = load <2 x i16>* %A		; <<2 x i16>> [#uses=1]
+	%tmp1 = load <2 x i16>, <2 x i16>* %A		; <<2 x i16>> [#uses=1]
 	store <2 x i16> %tmp1, <2 x i16>* %B
 	ret void
 }
diff --git a/test/CodeGen/X86/scalar_sse_minmax.ll b/test/CodeGen/X86/scalar_sse_minmax.ll
index bc4ab5d836c7..5ca3f85ce029 100644
--- a/test/CodeGen/X86/scalar_sse_minmax.ll
+++ b/test/CodeGen/X86/scalar_sse_minmax.ll
@@ -1,44 +1,53 @@
-; RUN: llc < %s -march=x86 -mattr=+sse,+sse2 | \
-; RUN:   grep mins | count 3
-; RUN: llc < %s -march=x86 -mattr=+sse,+sse2 | \
-; RUN:   grep maxs | count 2
-
-declare i1 @llvm.isunordered.f64(double, double)
-
-declare i1 @llvm.isunordered.f32(float, float)
+; RUN: llc < %s -march=x86 -mattr=+sse,+sse2 | FileCheck %s
 
 define float @min1(float %x, float %y) {
-	%tmp = fcmp olt float %x, %y		; <i1> [#uses=1]
-	%retval = select i1 %tmp, float %x, float %y		; <float> [#uses=1]
+; CHECK-LABEL: min1
+; CHECK: mins
+	%tmp = fcmp olt float %x, %y
+	%retval = select i1 %tmp, float %x, float %y
 	ret float %retval
 }
 
 define double @min2(double %x, double %y) {
-	%tmp = fcmp olt double %x, %y		; <i1> [#uses=1]
-	%retval = select i1 %tmp, double %x, double %y		; <double> [#uses=1]
+; CHECK-LABEL: min2
+; CHECK: mins
+	%tmp = fcmp olt double %x, %y
+	%retval = select i1 %tmp, double %x, double %y
 	ret double %retval
 }
 
+declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>)
+define <4 x float> @min3(float %x, float %y) {
+; CHECK-LABEL: min3
+; CHECK: mins
+	%vec0 = insertelement <4 x float> undef, float %x, i32 0
+	%vec1 = insertelement <4 x float> undef, float %y, i32 0
+	%retval = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %vec0, <4 x float> %vec1)
+	ret <4 x float> %retval
+}
+
 define float @max1(float %x, float %y) {
-	%tmp = fcmp oge float %x, %y		; <i1> [#uses=1]
-	%tmp2 = fcmp uno float %x, %y		; <i1> [#uses=1]
-	%tmp3 = or i1 %tmp2, %tmp		; <i1> [#uses=1]
-	%retval = select i1 %tmp3, float %x, float %y		; <float> [#uses=1]
+; CHECK-LABEL: max1
+; CHECK: maxs
+	%tmp = fcmp uge float %x, %y
+	%retval = select i1 %tmp, float %x, float %y
 	ret float %retval
 }
 
 define double @max2(double %x, double %y) {
-	%tmp = fcmp oge double %x, %y		; <i1> [#uses=1]
-	%tmp2 = fcmp uno double %x, %y		; <i1> [#uses=1]
-	%tmp3 = or i1 %tmp2, %tmp		; <i1> [#uses=1]
-	%retval = select i1 %tmp3, double %x, double %y		; <double> [#uses=1]
+; CHECK-LABEL: max2
+; CHECK: maxs
+	%tmp = fcmp uge double %x, %y
+	%retval = select i1 %tmp, double %x, double %y
 	ret double %retval
 }
 
-define <4 x float> @min3(float %tmp37) {
-	%tmp375 = insertelement <4 x float> undef, float %tmp37, i32 0		; <<4 x float>> [#uses=1]
-	%tmp48 = tail call <4 x float> @llvm.x86.sse.min.ss( <4 x float> %tmp375, <4 x float> < float 6.553500e+04, float undef, float undef, float undef > )		; <<4 x float>> [#uses=1]
-	ret <4 x float> %tmp48
+declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>)
+define <4 x float> @max3(float %x, float %y) {
+; CHECK-LABEL: max3
+; CHECK: maxs
+	%vec0 = insertelement <4 x float> undef, float %x, i32 0
+	%vec1 = insertelement <4 x float> undef, float %y, i32 0
+	%retval = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %vec0, <4 x float> %vec1)
+	ret <4 x float> %retval
 }
-
-declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>)
diff --git a/test/CodeGen/X86/scalar_widen_div.ll b/test/CodeGen/X86/scalar_widen_div.ll
index 5807d5babfff..1671f8f89108 100644
--- a/test/CodeGen/X86/scalar_widen_div.ll
+++ b/test/CodeGen/X86/scalar_widen_div.ll
@@ -17,17 +17,17 @@ entry:
   store <2 x i32> addrspace(1)* %nsource, <2 x i32> addrspace(1)** %nsource.addr
   store <2 x i32> addrspace(1)* %dsource, <2 x i32> addrspace(1)** %dsource.addr
   store <2 x i32> addrspace(1)* %qdest, <2 x i32> addrspace(1)** %qdest.addr
-  %tmp = load <2 x i32> addrspace(1)** %qdest.addr
-  %tmp1 = load i32* %index
-  %arrayidx = getelementptr <2 x i32> addrspace(1)* %tmp, i32 %tmp1
-  %tmp2 = load <2 x i32> addrspace(1)** %nsource.addr
-  %tmp3 = load i32* %index
-  %arrayidx4 = getelementptr <2 x i32> addrspace(1)* %tmp2, i32 %tmp3
-  %tmp5 = load <2 x i32> addrspace(1)* %arrayidx4
-  %tmp6 = load <2 x i32> addrspace(1)** %dsource.addr
-  %tmp7 = load i32* %index
-  %arrayidx8 = getelementptr <2 x i32> addrspace(1)* %tmp6, i32 %tmp7
-  %tmp9 = load <2 x i32> addrspace(1)* %arrayidx8
+  %tmp = load <2 x i32> addrspace(1)*, <2 x i32> addrspace(1)** %qdest.addr
+  %tmp1 = load i32, i32* %index
+  %arrayidx = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %tmp, i32 %tmp1
+  %tmp2 = load <2 x i32> addrspace(1)*, <2 x i32> addrspace(1)** %nsource.addr
+  %tmp3 = load i32, i32* %index
+  %arrayidx4 = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %tmp2, i32 %tmp3
+  %tmp5 = load <2 x i32>, <2 x i32> addrspace(1)* %arrayidx4
+  %tmp6 = load <2 x i32> addrspace(1)*, <2 x i32> addrspace(1)** %dsource.addr
+  %tmp7 = load i32, i32* %index
+  %arrayidx8 = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %tmp6, i32 %tmp7
+  %tmp9 = load <2 x i32>, <2 x i32> addrspace(1)* %arrayidx8
   %tmp10 = sdiv <2 x i32> %tmp5, %tmp9
   store <2 x i32> %tmp10, <2 x i32> addrspace(1)* %arrayidx
   ret void
@@ -180,10 +180,10 @@ bb.nph:
 
 for.body:
   %i.014 = phi i32 [ 0, %bb.nph ], [ %inc, %for.body ] 
-  %arrayidx11 = getelementptr <3 x i32>* %dest, i32 %i.014
-  %tmp4 = load <3 x i32>* %arrayidx11 ; <<3 x i32>> [#uses=1]
-  %arrayidx7 = getelementptr inbounds <3 x i32>* %old, i32 %i.014
-  %tmp8 = load <3 x i32>* %arrayidx7 ; <<3 x i32>> [#uses=1]
+  %arrayidx11 = getelementptr <3 x i32>, <3 x i32>* %dest, i32 %i.014
+  %tmp4 = load <3 x i32>, <3 x i32>* %arrayidx11 ; <<3 x i32>> [#uses=1]
+  %arrayidx7 = getelementptr inbounds <3 x i32>, <3 x i32>* %old, i32 %i.014
+  %tmp8 = load <3 x i32>, <3 x i32>* %arrayidx7 ; <<3 x i32>> [#uses=1]
   %div = sdiv <3 x i32> %tmp4, %tmp8
   store <3 x i32> %div, <3 x i32>* %arrayidx11
   %inc = add nsw i32 %i.014, 1
diff --git a/test/CodeGen/X86/scalarize-bitcast.ll b/test/CodeGen/X86/scalarize-bitcast.ll
index f6b29ecfbb60..60650f46302f 100644
--- a/test/CodeGen/X86/scalarize-bitcast.ll
+++ b/test/CodeGen/X86/scalarize-bitcast.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-pc-linux-gnu"
 
 define void @mmxCombineMaskU(i32* nocapture %src, i32* nocapture %mask) nounwind {
 entry:
-	%tmp1 = load i32* %src		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* %src		; <i32> [#uses=1]
 	%0 = insertelement <2 x i32> undef, i32 %tmp1, i32 0		; <<2 x i32>> [#uses=1]
 	%1 = insertelement <2 x i32> %0, i32 0, i32 1		; <<2 x i32>> [#uses=1]
 	%conv.i.i = bitcast <2 x i32> %1 to <1 x i64>		; <<1 x i64>> [#uses=1]
@@ -21,7 +21,7 @@ entry:
 	%tmp24.i = extractelement <1 x i64> %tmp10.i, i32 0		; <i64> [#uses=1]
 	%tmp10 = bitcast i64 %tmp24.i to <1 x i64>		; <<1 x i64>> [#uses=1]
 	%tmp7 = extractelement <1 x i64> %tmp10, i32 0		; <i64> [#uses=1]
-	%call6 = tail call i32 (...)* @store8888(i64 %tmp7)		; <i32> [#uses=1]
+	%call6 = tail call i32 (...) @store8888(i64 %tmp7)		; <i32> [#uses=1]
 	store i32 %call6, i32* %src
 	ret void
 }
diff --git a/test/CodeGen/X86/scev-interchange.ll b/test/CodeGen/X86/scev-interchange.ll
index 0e7047b4845d..e224c0858aff 100644
--- a/test/CodeGen/X86/scev-interchange.ll
+++ b/test/CodeGen/X86/scev-interchange.ll
@@ -296,7 +296,7 @@ bb9.i216.i:		; preds = %bb29.loopexit.i.i, %bb8.i.i
 
 bb15.i.i:		; preds = %bb16.preheader.i.i, %bb15.i.i
 	%j1.0212.i.i = phi i32 [ %1, %bb15.i.i ], [ 0, %bb16.preheader.i.i ]		; <i32> [#uses=2]
-	%tmp6.i.i195.i.i = load i32* undef, align 4		; <i32> [#uses=1]
+	%tmp6.i.i195.i.i = load i32, i32* undef, align 4		; <i32> [#uses=1]
 	%tmp231.i.i = mul i32 %0, %tmp6.i.i195.i.i		; <i32> [#uses=1]
 	%tmp13.i197.i.i = add i32 %j1.0212.i.i, %tmp231.i.i		; <i32> [#uses=0]
 	%1 = add i32 %j1.0212.i.i, 1		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/segmented-stacks.ll b/test/CodeGen/X86/segmented-stacks.ll
index 3e47121a380e..55eaab91da50 100644
--- a/test/CodeGen/X86/segmented-stacks.ll
+++ b/test/CodeGen/X86/segmented-stacks.ll
@@ -11,16 +11,16 @@
 ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-mingw32 -verify-machineinstrs | FileCheck %s -check-prefix=X64-MinGW
 
 ; We used to crash with filetype=obj
-; RUN: llc < %s -mcpu=generic -mtriple=i686-linux -filetype=obj
-; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux -filetype=obj
-; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux-gnux32 -filetype=obj
-; RUN: llc < %s -mcpu=generic -mtriple=i686-darwin -filetype=obj
-; RUN: llc < %s -mcpu=generic -mtriple=x86_64-darwin -filetype=obj
-; RUN: llc < %s -mcpu=generic -mtriple=i686-mingw32 -filetype=obj
-; RUN: llc < %s -mcpu=generic -mtriple=x86_64-freebsd -filetype=obj
-; RUN: llc < %s -mcpu=generic -mtriple=i686-dragonfly -filetype=obj
-; RUN: llc < %s -mcpu=generic -mtriple=x86_64-dragonfly -filetype=obj
-; RUN: llc < %s -mcpu=generic -mtriple=x86_64-mingw32 -filetype=obj
+; RUN: llc < %s -mcpu=generic -mtriple=i686-linux -filetype=obj -o /dev/null
+; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux -filetype=obj -o /dev/null
+; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux-gnux32 -filetype=obj -o /dev/null
+; RUN: llc < %s -mcpu=generic -mtriple=i686-darwin -filetype=obj -o /dev/null
+; RUN: llc < %s -mcpu=generic -mtriple=x86_64-darwin -filetype=obj -o /dev/null
+; RUN: llc < %s -mcpu=generic -mtriple=i686-mingw32 -filetype=obj -o /dev/null
+; RUN: llc < %s -mcpu=generic -mtriple=x86_64-freebsd -filetype=obj -o /dev/null
+; RUN: llc < %s -mcpu=generic -mtriple=i686-dragonfly -filetype=obj -o /dev/null
+; RUN: llc < %s -mcpu=generic -mtriple=x86_64-dragonfly -filetype=obj -o /dev/null
+; RUN: llc < %s -mcpu=generic -mtriple=x86_64-mingw32 -filetype=obj -o /dev/null
 
 ; RUN: not llc < %s -mcpu=generic -mtriple=x86_64-solaris 2> %t.log
 ; RUN: FileCheck %s -input-file=%t.log -check-prefix=X64-Solaris
@@ -152,7 +152,7 @@ define void @test_basic() #0 {
 }
 
 define i32 @test_nested(i32 * nest %closure, i32 %other) #0 {
-       %addend = load i32 * %closure
+       %addend = load i32 , i32 * %closure
        %result = add i32 %other, %addend
        %mem = alloca i32, i32 10
        call void @dummy_use (i32* %mem, i32 10)
diff --git a/test/CodeGen/X86/seh-catch-all.ll b/test/CodeGen/X86/seh-catch-all.ll
new file mode 100644
index 000000000000..51840134eda3
--- /dev/null
+++ b/test/CodeGen/X86/seh-catch-all.ll
@@ -0,0 +1,44 @@
+; RUN: llc -mtriple=x86_64-windows-msvc < %s | FileCheck %s
+
+@str = linkonce_odr unnamed_addr constant [27 x i8] c"GetExceptionCode(): 0x%lx\0A\00", align 1
+
+declare i32 @__C_specific_handler(...)
+declare void @crash()
+declare i32 @printf(i8* nocapture readonly, ...) nounwind
+
+define i32 @main() {
+entry:
+  invoke void @crash()
+          to label %__try.cont unwind label %lpad
+
+lpad:
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+          catch i8* null
+  %1 = extractvalue { i8*, i32 } %0, 0
+  %2 = ptrtoint i8* %1 to i64
+  %3 = trunc i64 %2 to i32
+  call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([27 x i8], [27 x i8]* @str, i64 0, i64 0), i32 %3)
+  br label %__try.cont
+
+__try.cont:
+  ret i32 0
+
+eh.resume:
+  resume { i8*, i32 } %0
+}
+
+; Check that we can get the exception code from eax to the printf.
+
+; CHECK-LABEL: main:
+; CHECK: retq
+; CHECK: # Block address taken
+; CHECK: leaq str(%rip), %rcx
+; CHECK: movl %eax, %edx
+; CHECK: callq printf
+
+; CHECK: .seh_handlerdata
+; CHECK-NEXT: .long 1
+; CHECK-NEXT: .Ltmp{{[0-9]+}}@IMGREL
+; CHECK-NEXT: .Ltmp{{[0-9]+}}@IMGREL+1
+; CHECK-NEXT: 1
+; CHECK-NEXT: .Ltmp{{[0-9]+}}@IMGREL
diff --git a/test/CodeGen/X86/seh-except-finally.ll b/test/CodeGen/X86/seh-except-finally.ll
new file mode 100644
index 000000000000..c796f1ef2888
--- /dev/null
+++ b/test/CodeGen/X86/seh-except-finally.ll
@@ -0,0 +1,167 @@
+; RUN: llc < %s | FileCheck %s
+
+; Test case based on this source:
+; int puts(const char*);
+; __declspec(noinline) void crash() {
+;   *(volatile int*)0 = 42;
+; }
+; int filt();
+; void use_both() {
+;   __try {
+;     __try {
+;       crash();
+;     } __finally {
+;       puts("__finally");
+;     }
+;   } __except (filt()) {
+;     puts("__except");
+;   }
+; }
+
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+$"\01??_C@_09KJEHOMHG@__finally?$AA@" = comdat any
+
+$"\01??_C@_08MLCMLGHM@__except?$AA@" = comdat any
+
+@"\01??_C@_09KJEHOMHG@__finally?$AA@" = linkonce_odr unnamed_addr constant [10 x i8] c"__finally\00", comdat, align 1
+@"\01??_C@_08MLCMLGHM@__except?$AA@" = linkonce_odr unnamed_addr constant [9 x i8] c"__except\00", comdat, align 1
+
+declare void @crash()
+
+declare i32 @filt()
+
+; Function Attrs: nounwind uwtable
+define void @use_both() #1 {
+entry:
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  invoke void @crash() #5
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %entry
+  %0 = call i8* @llvm.frameaddress(i32 0)
+  invoke void @"\01?fin$0@0@use_both@@"(i1 zeroext false, i8* %0) #5
+          to label %invoke.cont2 unwind label %lpad1
+
+invoke.cont2:                                     ; preds = %invoke.cont
+  br label %__try.cont
+
+lpad:                                             ; preds = %entry
+  %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+          cleanup
+          catch i8* bitcast (i32 (i8*, i8*)* @"\01?filt$0@0@use_both@@" to i8*)
+  %2 = extractvalue { i8*, i32 } %1, 0
+  store i8* %2, i8** %exn.slot
+  %3 = extractvalue { i8*, i32 } %1, 1
+  store i32 %3, i32* %ehselector.slot
+  %4 = call i8* @llvm.frameaddress(i32 0)
+  invoke void @"\01?fin$0@0@use_both@@"(i1 zeroext true, i8* %4) #5
+          to label %invoke.cont3 unwind label %lpad1
+
+lpad1:                                            ; preds = %lpad, %invoke.cont
+  %5 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+          catch i8* bitcast (i32 (i8*, i8*)* @"\01?filt$0@0@use_both@@" to i8*)
+  %6 = extractvalue { i8*, i32 } %5, 0
+  store i8* %6, i8** %exn.slot
+  %7 = extractvalue { i8*, i32 } %5, 1
+  store i32 %7, i32* %ehselector.slot
+  br label %catch.dispatch
+
+invoke.cont3:                                     ; preds = %lpad
+  br label %catch.dispatch
+
+catch.dispatch:                                   ; preds = %invoke.cont3, %lpad1
+  %sel = load i32, i32* %ehselector.slot
+  %8 = call i32 @llvm.eh.typeid.for(i8* bitcast (i32 (i8*, i8*)* @"\01?filt$0@0@use_both@@" to i8*)) #6
+  %matches = icmp eq i32 %sel, %8
+  br i1 %matches, label %__except, label %eh.resume
+
+__except:                                         ; preds = %catch.dispatch
+  %call = call i32 @puts(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @"\01??_C@_08MLCMLGHM@__except?$AA@", i32 0, i32 0))
+  br label %__try.cont
+
+__try.cont:                                       ; preds = %__except, %invoke.cont2
+  ret void
+
+eh.resume:                                        ; preds = %catch.dispatch
+  %exn = load i8*, i8** %exn.slot
+  %sel4 = load i32, i32* %ehselector.slot
+  %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn, 0
+  %lpad.val5 = insertvalue { i8*, i32 } %lpad.val, i32 %sel4, 1
+  resume { i8*, i32 } %lpad.val5
+}
+
+; CHECK-LABEL: use_both:
+; CHECK: .Ltmp0
+; CHECK: callq crash
+; CHECK: .Ltmp1
+; CHECK: .Ltmp3
+; CHECK: callq "?fin$0@0@use_both@@"
+; CHECK: .Ltmp4
+; CHECK: retq
+;
+; CHECK: .seh_handlerdata
+; CHECK-NEXT: .long 3
+; CHECK-NEXT: .long .Ltmp0@IMGREL
+; CHECK-NEXT: .long .Ltmp1@IMGREL+1
+; CHECK-NEXT: .long "?fin$0@0@use_both@@"@IMGREL
+; CHECK-NEXT: .long 0
+; CHECK-NEXT: .long .Ltmp0@IMGREL
+; CHECK-NEXT: .long .Ltmp1@IMGREL+1
+; CHECK-NEXT: .long "?filt$0@0@use_both@@"@IMGREL
+; CHECK-NEXT: .long .Ltmp{{[0-9]+}}@IMGREL
+; CHECK-NEXT: .long .Ltmp3@IMGREL
+; CHECK-NEXT: .long .Ltmp4@IMGREL+1
+; CHECK-NEXT: .long "?filt$0@0@use_both@@"@IMGREL
+; CHECK-NEXT: .long .Ltmp{{[0-9]+}}@IMGREL
+
+; Function Attrs: noinline nounwind
+define internal i32 @"\01?filt$0@0@use_both@@"(i8* %exception_pointers, i8* %frame_pointer) #2 {
+entry:
+  %frame_pointer.addr = alloca i8*, align 8
+  %exception_pointers.addr = alloca i8*, align 8
+  %exn.slot = alloca i8*
+  store i8* %frame_pointer, i8** %frame_pointer.addr, align 8
+  store i8* %exception_pointers, i8** %exception_pointers.addr, align 8
+  %0 = load i8*, i8** %exception_pointers.addr
+  %1 = bitcast i8* %0 to { i32*, i8* }*
+  %2 = getelementptr inbounds { i32*, i8* }, { i32*, i8* }* %1, i32 0, i32 0
+  %3 = load i32*, i32** %2
+  %4 = load i32, i32* %3
+  %5 = zext i32 %4 to i64
+  %6 = inttoptr i64 %5 to i8*
+  store i8* %6, i8** %exn.slot
+  %call = call i32 @filt()
+  ret i32 %call
+}
+
+define internal void @"\01?fin$0@0@use_both@@"(i1 zeroext %abnormal_termination, i8* %frame_pointer) #3 {
+entry:
+  %frame_pointer.addr = alloca i8*, align 8
+  %abnormal_termination.addr = alloca i8, align 1
+  store i8* %frame_pointer, i8** %frame_pointer.addr, align 8
+  %frombool = zext i1 %abnormal_termination to i8
+  store i8 %frombool, i8* %abnormal_termination.addr, align 1
+  %call = call i32 @puts(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @"\01??_C@_09KJEHOMHG@__finally?$AA@", i32 0, i32 0))
+  ret void
+}
+
+declare i32 @puts(i8*) #3
+
+declare i32 @__C_specific_handler(...)
+
+; Function Attrs: nounwind readnone
+declare i8* @llvm.frameaddress(i32) #4
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #4
+
+attributes #0 = { noinline nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { noinline nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #4 = { nounwind readnone }
+attributes #5 = { noinline }
+attributes #6 = { nounwind }
diff --git a/test/CodeGen/X86/seh-filter.ll b/test/CodeGen/X86/seh-filter.ll
new file mode 100644
index 000000000000..6a3a23edb1ae
--- /dev/null
+++ b/test/CodeGen/X86/seh-filter.ll
@@ -0,0 +1,21 @@
+; RUN: llc -O0 -mtriple=x86_64-windows-msvc < %s | FileCheck %s
+
+declare void @g()
+define void @f() {
+  invoke void @g() to label %return unwind label %lpad
+
+return:
+  ret void
+
+lpad:
+  %ehptrs = landingpad {i8*, i32} personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+    filter [0 x i8*] zeroinitializer
+  call void @__cxa_call_unexpected(i8* null)
+  unreachable
+}
+declare i32 @__C_specific_handler(...)
+declare void @__cxa_call_unexpected(i8*)
+
+; We don't emit entries for filters.
+; CHECK: .seh_handlerdata
+; CHECK: .long 0
diff --git a/test/CodeGen/X86/seh-finally.ll b/test/CodeGen/X86/seh-finally.ll
new file mode 100644
index 000000000000..91baed570f25
--- /dev/null
+++ b/test/CodeGen/X86/seh-finally.ll
@@ -0,0 +1,51 @@
+; RUN: llc -mtriple=x86_64-windows-msvc < %s | FileCheck %s
+
+@str_recovered = internal unnamed_addr constant [10 x i8] c"recovered\00", align 1
+
+declare void @crash()
+
+define i32 @main() {
+entry:
+  invoke void @crash()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %entry
+  %call = call i32 @puts(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @str_recovered, i64 0, i64 0))
+  call void @abort()
+  ret i32 0
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+          cleanup
+  %1 = extractvalue { i8*, i32 } %0, 0
+  %2 = extractvalue { i8*, i32 } %0, 1
+  %call2 = invoke i32 @puts(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @str_recovered, i64 0, i64 0))
+          to label %invoke.cont1 unwind label %terminate.lpad
+
+invoke.cont1:                                     ; preds = %lpad
+  resume { i8*, i32 } %0
+
+terminate.lpad:                                   ; preds = %lpad
+  %3 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+          catch i8* null
+  call void @abort()
+  unreachable
+}
+
+; CHECK-LABEL: main:
+; CHECK: .seh_handlerdata
+; CHECK-NEXT: .long 1
+; CHECK-NEXT: .long .Ltmp0@IMGREL
+; CHECK-NEXT: .long .Ltmp1@IMGREL
+; CHECK-NEXT: .long main.cleanup@IMGREL
+; CHECK-NEXT: .long 0
+
+; CHECK-LABEL: main.cleanup:
+; CHECK: callq puts
+; CHECK: retq
+
+declare i32 @__C_specific_handler(...)
+
+declare i32 @puts(i8*)
+
+declare void @abort()
diff --git a/test/CodeGen/X86/seh-safe-div.ll b/test/CodeGen/X86/seh-safe-div.ll
new file mode 100644
index 000000000000..80b15b601020
--- /dev/null
+++ b/test/CodeGen/X86/seh-safe-div.ll
@@ -0,0 +1,180 @@
+; RUN: llc -mtriple x86_64-pc-windows-msvc < %s | FileCheck %s
+
+; This test case is also intended to be run manually as a complete functional
+; test. It should link, print something, and exit zero rather than crashing.
+; It is the hypothetical lowering of a C source program that looks like:
+;
+;   int safe_div(int *n, int *d) {
+;     int r;
+;     __try {
+;       __try {
+;         r = *n / *d;
+;       } __except(GetExceptionCode() == EXCEPTION_ACCESS_VIOLATION) {
+;         puts("EXCEPTION_ACCESS_VIOLATION");
+;         r = -1;
+;       }
+;     } __except(GetExceptionCode() == EXCEPTION_INT_DIVIDE_BY_ZERO) {
+;       puts("EXCEPTION_INT_DIVIDE_BY_ZERO");
+;       r = -2;
+;     }
+;     return r;
+;   }
+
+@str1 = internal constant [27 x i8] c"EXCEPTION_ACCESS_VIOLATION\00"
+@str2 = internal constant [29 x i8] c"EXCEPTION_INT_DIVIDE_BY_ZERO\00"
+
+define i32 @safe_div(i32* %n, i32* %d) {
+entry:
+  %r = alloca i32, align 4
+  invoke void @try_body(i32* %r, i32* %n, i32* %d)
+          to label %__try.cont unwind label %lpad
+
+lpad:
+  %vals = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+          catch i8* bitcast (i32 (i8*, i8*)* @safe_div_filt0 to i8*)
+          catch i8* bitcast (i32 (i8*, i8*)* @safe_div_filt1 to i8*)
+  %ehptr = extractvalue { i8*, i32 } %vals, 0
+  %sel = extractvalue { i8*, i32 } %vals, 1
+  %filt0_val = call i32 @llvm.eh.typeid.for(i8* bitcast (i32 (i8*, i8*)* @safe_div_filt0 to i8*))
+  %is_filt0 = icmp eq i32 %sel, %filt0_val
+  br i1 %is_filt0, label %handler0, label %eh.dispatch1
+
+eh.dispatch1:
+  %filt1_val = call i32 @llvm.eh.typeid.for(i8* bitcast (i32 (i8*, i8*)* @safe_div_filt1 to i8*))
+  %is_filt1 = icmp eq i32 %sel, %filt1_val
+  br i1 %is_filt1, label %handler1, label %eh.resume
+
+handler0:
+  call void @puts(i8* getelementptr ([27 x i8], [27 x i8]* @str1, i32 0, i32 0))
+  store i32 -1, i32* %r, align 4
+  br label %__try.cont
+
+handler1:
+  call void @puts(i8* getelementptr ([29 x i8], [29 x i8]* @str2, i32 0, i32 0))
+  store i32 -2, i32* %r, align 4
+  br label %__try.cont
+
+eh.resume:
+  resume { i8*, i32 } %vals
+
+__try.cont:
+  %safe_ret = load i32, i32* %r, align 4
+  ret i32 %safe_ret
+}
+
+; Normal path code
+
+; CHECK: {{^}}safe_div:
+; CHECK: .seh_proc safe_div
+; CHECK: .seh_handler __C_specific_handler, @unwind, @except
+; CHECK: .Ltmp0:
+; CHECK: leaq [[rloc:.*\(%rsp\)]], %rcx
+; CHECK: callq try_body
+; CHECK-NEXT: .Ltmp1
+; CHECK: [[cont_bb:\.LBB0_[0-9]+]]:
+; CHECK: movl [[rloc]], %eax
+; CHECK: retq
+
+; Landing pad code
+
+; CHECK: [[handler0:\.Ltmp[0-9]+]]: # Block address taken
+; CHECK: # %handler0
+; CHECK: callq puts
+; CHECK: movl $-1, [[rloc]]
+; CHECK: jmp [[cont_bb]]
+
+; CHECK: [[handler1:\.Ltmp[0-9]+]]: # Block address taken
+; CHECK: # %handler1
+; CHECK: callq puts
+; CHECK: movl $-2, [[rloc]]
+; CHECK: jmp [[cont_bb]]
+
+; CHECK: .seh_handlerdata
+; CHECK-NEXT: .long 2
+; CHECK-NEXT: .long .Ltmp0@IMGREL
+; CHECK-NEXT: .long .Ltmp1@IMGREL+1
+; CHECK-NEXT: .long safe_div_filt0@IMGREL
+; CHECK-NEXT: .long [[handler0]]@IMGREL
+; CHECK-NEXT: .long .Ltmp0@IMGREL
+; CHECK-NEXT: .long .Ltmp1@IMGREL+1
+; CHECK-NEXT: .long safe_div_filt1@IMGREL
+; CHECK-NEXT: .long [[handler1]]@IMGREL
+; CHECK: .text
+; CHECK: .seh_endproc
+
+
+define void @try_body(i32* %r, i32* %n, i32* %d) {
+entry:
+  %0 = load i32, i32* %n, align 4
+  %1 = load i32, i32* %d, align 4
+  %div = sdiv i32 %0, %1
+  store i32 %div, i32* %r, align 4
+  ret void
+}
+
+; The prototype of these filter functions is:
+; int filter(EXCEPTION_POINTERS *eh_ptrs, void *rbp);
+
+; The definition of EXCEPTION_POINTERS is:
+;   typedef struct _EXCEPTION_POINTERS {
+;     EXCEPTION_RECORD *ExceptionRecord;
+;     CONTEXT          *ContextRecord;
+;   } EXCEPTION_POINTERS;
+
+; The definition of EXCEPTION_RECORD is:
+;   typedef struct _EXCEPTION_RECORD {
+;     DWORD ExceptionCode;
+;     ...
+;   } EXCEPTION_RECORD;
+
+; The exception code can be retreived with two loads, one for the record
+; pointer and one for the code.  The values of local variables can be
+; accessed via rbp, but that would require additional not yet implemented LLVM
+; support.
+
+define i32 @safe_div_filt0(i8* %eh_ptrs, i8* %rbp) {
+  %eh_ptrs_c = bitcast i8* %eh_ptrs to i32**
+  %eh_rec = load i32*, i32** %eh_ptrs_c
+  %eh_code = load i32, i32* %eh_rec
+  ; EXCEPTION_ACCESS_VIOLATION = 0xC0000005
+  %cmp = icmp eq i32 %eh_code, 3221225477
+  %filt.res = zext i1 %cmp to i32
+  ret i32 %filt.res
+}
+
+define i32 @safe_div_filt1(i8* %eh_ptrs, i8* %rbp) {
+  %eh_ptrs_c = bitcast i8* %eh_ptrs to i32**
+  %eh_rec = load i32*, i32** %eh_ptrs_c
+  %eh_code = load i32, i32* %eh_rec
+  ; EXCEPTION_INT_DIVIDE_BY_ZERO = 0xC0000094
+  %cmp = icmp eq i32 %eh_code, 3221225620
+  %filt.res = zext i1 %cmp to i32
+  ret i32 %filt.res
+}
+
+@str_result = internal constant [21 x i8] c"safe_div result: %d\0A\00"
+
+define i32 @main() {
+  %d.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+
+  store i32 10, i32* %n.addr, align 4
+  store i32 2, i32* %d.addr, align 4
+  %r1 = call i32 @safe_div(i32* %n.addr, i32* %d.addr)
+  call void (i8*, ...) @printf(i8* getelementptr ([21 x i8], [21 x i8]* @str_result, i32 0, i32 0), i32 %r1)
+
+  store i32 10, i32* %n.addr, align 4
+  store i32 0, i32* %d.addr, align 4
+  %r2 = call i32 @safe_div(i32* %n.addr, i32* %d.addr)
+  call void (i8*, ...) @printf(i8* getelementptr ([21 x i8], [21 x i8]* @str_result, i32 0, i32 0), i32 %r2)
+
+  %r3 = call i32 @safe_div(i32* %n.addr, i32* null)
+  call void (i8*, ...) @printf(i8* getelementptr ([21 x i8], [21 x i8]* @str_result, i32 0, i32 0), i32 %r3)
+  ret i32 0
+}
+
+declare i32 @__C_specific_handler(...)
+declare i32 @llvm.eh.typeid.for(i8*) readnone nounwind
+declare void @puts(i8*)
+declare void @printf(i8*, ...)
+declare void @abort()
diff --git a/test/CodeGen/X86/select-with-and-or.ll b/test/CodeGen/X86/select-with-and-or.ll
index 1ccf30bf2083..40af46bc0ff6 100644
--- a/test/CodeGen/X86/select-with-and-or.ll
+++ b/test/CodeGen/X86/select-with-and-or.ll
@@ -62,7 +62,7 @@ define <4 x i32> @test6(<4 x float> %a, <4 x float> %b, <4 x i32> %c) {
 define <4 x i32> @test7(<4 x float> %a, <4 x float> %b, <4 x i32>* %p) {
   %f = fcmp ult <4 x float> %a, %b
   %s = sext <4 x i1> %f to <4 x i32>
-  %l = load <4 x i32>* %p
+  %l = load <4 x i32>, <4 x i32>* %p
   %r = and <4 x i32> %l, %s
   ret <4 x i32> %r
 ; CHECK: test7
diff --git a/test/CodeGen/X86/select.ll b/test/CodeGen/X86/select.ll
index 7e6f15321415..a4e06b398446 100644
--- a/test/CodeGen/X86/select.ll
+++ b/test/CodeGen/X86/select.ll
@@ -5,8 +5,8 @@
 %0 = type { i64, i32 }
 
 define i32 @test1(%0* %p, %0* %q, i1 %r) nounwind {
-  %t0 = load %0* %p
-  %t1 = load %0* %q
+  %t0 = load %0, %0* %p
+  %t1 = load %0, %0* %q
   %t4 = select i1 %r, %0 %t0, %0 %t1
   %t5 = extractvalue %0 %t4, 1
   ret i32 %t5
@@ -62,8 +62,8 @@ define signext i8 @test4(i8* nocapture %P, double %F) nounwind readonly {
 entry:
 	%0 = fcmp olt double %F, 4.200000e+01		; <i1> [#uses=1]
 	%iftmp.0.0 = select i1 %0, i32 4, i32 0		; <i32> [#uses=1]
-	%1 = getelementptr i8* %P, i32 %iftmp.0.0		; <i8*> [#uses=1]
-	%2 = load i8* %1, align 1		; <i8> [#uses=1]
+	%1 = getelementptr i8, i8* %P, i32 %iftmp.0.0		; <i8*> [#uses=1]
+	%2 = load i8, i8* %1, align 1		; <i8> [#uses=1]
 	ret i8 %2
 ; CHECK-LABEL: test4:
 ; CHECK: movsbl	({{.*}},4), %eax
@@ -82,8 +82,8 @@ define void @test5(i1 %c, <2 x i16> %a, <2 x i16> %b, <2 x i16>* %p) nounwind {
 }
 
 define void @test6(i32 %C, <4 x float>* %A, <4 x float>* %B) nounwind {
-        %tmp = load <4 x float>* %A             ; <<4 x float>> [#uses=1]
-        %tmp3 = load <4 x float>* %B            ; <<4 x float>> [#uses=2]
+        %tmp = load <4 x float>, <4 x float>* %A             ; <<4 x float>> [#uses=1]
+        %tmp3 = load <4 x float>, <4 x float>* %B            ; <<4 x float>> [#uses=2]
         %tmp9 = fmul <4 x float> %tmp3, %tmp3            ; <<4 x float>> [#uses=1]
         %tmp.upgrd.1 = icmp eq i32 %C, 0                ; <i1> [#uses=1]
         %iftmp.38.0 = select i1 %tmp.upgrd.1, <4 x float> %tmp9, <4 x float> %tmp               ; <<4 x float>> [#uses=1]
diff --git a/test/CodeGen/X86/selectiondag-crash.ll b/test/CodeGen/X86/selectiondag-crash.ll
new file mode 100644
index 000000000000..99789021a737
--- /dev/null
+++ b/test/CodeGen/X86/selectiondag-crash.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=corei7 < %s
+
+; Check that llc doesn't crash in the attempt to fold a shuffle with
+; a splat mask into a constant build_vector.
+
+define <8 x i8> @autogen_SD26299(i8) {
+BB:
+  %Shuff = shufflevector <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <8 x i32> zeroinitializer, <8 x i32> <i32 2, i32 undef, i32 6, i32 8, i32 undef, i32 12, i32 14, i32 0>
+  %Shuff14 = shufflevector <8 x i32> %Shuff, <8 x i32> %Shuff, <8 x i32> <i32 7, i32 9, i32 11, i32 undef, i32 undef, i32 1, i32 3, i32 5>
+  %Shuff35 = shufflevector <8 x i32> %Shuff14, <8 x i32> %Shuff, <8 x i32> <i32 undef, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13>
+  %I42 = insertelement <8 x i32> %Shuff35, i32 88608, i32 0
+  %Shuff48 = shufflevector <8 x i32> %Shuff35, <8 x i32> %I42, <8 x i32> <i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2>
+  %Tr59 = trunc <8 x i32> %Shuff48 to <8 x i8>
+  ret <8 x i8> %Tr59
+}
diff --git a/test/CodeGen/X86/selectiondag-cse.ll b/test/CodeGen/X86/selectiondag-cse.ll
index a653a1c8ca3b..c9e58015339d 100644
--- a/test/CodeGen/X86/selectiondag-cse.ll
+++ b/test/CodeGen/X86/selectiondag-cse.ll
@@ -39,7 +39,7 @@ bb5:
   %tmp13 = add i32 %tmp12, %tmp10
   %tmp14 = lshr i32 %tmp13, 2
   %tmp15 = trunc i32 %tmp14 to i16
-  store i16 %tmp15, i16* getelementptr inbounds (%0* @images, i64 0, i32 47, i64 3, i64 0, i64 3), align 2
+  store i16 %tmp15, i16* getelementptr inbounds (%0, %0* @images, i64 0, i32 47, i64 3, i64 0, i64 3), align 2
   %tmp16 = lshr i208 %tmp, 96
   %tmp17 = trunc i208 %tmp16 to i32
   %tmp18 = and i32 %tmp17, 65535
@@ -48,12 +48,12 @@ bb5:
   %tmp21 = add i32 %tmp20, 0
   %tmp22 = lshr i32 %tmp21, 2
   %tmp23 = trunc i32 %tmp22 to i16
-  store i16 %tmp23, i16* getelementptr inbounds (%0* @images, i64 0, i32 47, i64 3, i64 2, i64 3), align 2
+  store i16 %tmp23, i16* getelementptr inbounds (%0, %0* @images, i64 0, i32 47, i64 3, i64 2, i64 3), align 2
   %tmp24 = add i32 %tmp6, %tmp9
   %tmp25 = add i32 %tmp24, 0
   %tmp26 = lshr i32 %tmp25, 2
   %tmp27 = trunc i32 %tmp26 to i16
-  store i16 %tmp27, i16* getelementptr inbounds (%0* @images, i64 0, i32 47, i64 7, i64 1, i64 2), align 4
+  store i16 %tmp27, i16* getelementptr inbounds (%0, %0* @images, i64 0, i32 47, i64 7, i64 1, i64 2), align 4
   %tmp28 = lshr i208 %tmp, 80
   %tmp29 = shl nuw nsw i208 %tmp28, 1
   %tmp30 = trunc i208 %tmp29 to i32
@@ -61,7 +61,7 @@ bb5:
   %tmp32 = add i32 %tmp12, %tmp31
   %tmp33 = lshr i32 %tmp32, 2
   %tmp34 = trunc i32 %tmp33 to i16
-  store i16 %tmp34, i16* getelementptr inbounds (%0* @images, i64 0, i32 47, i64 7, i64 1, i64 3), align 2
+  store i16 %tmp34, i16* getelementptr inbounds (%0, %0* @images, i64 0, i32 47, i64 7, i64 1, i64 3), align 2
   br label %bb35
 
 bb35:                                             ; preds = %bb5, %bb4
diff --git a/test/CodeGen/X86/setcc-narrowing.ll b/test/CodeGen/X86/setcc-narrowing.ll
index 25cb2c822c5b..bf5b45031a24 100644
--- a/test/CodeGen/X86/setcc-narrowing.ll
+++ b/test/CodeGen/X86/setcc-narrowing.ll
@@ -10,7 +10,7 @@ entry:
 ; CHECK-NEXT: setne %al
 ; CHECK-NEXT: movzbl %al, %eax
 ; CHECK-NEXT: ret
-  %0 = load i64* @t1.global, align 8
+  %0 = load i64, i64* @t1.global, align 8
   %and = and i64 4294967295, %0
   %cmp = icmp sgt i64 %and, 0
   %conv = zext i1 %cmp to i32
diff --git a/test/CodeGen/X86/setcc.ll b/test/CodeGen/X86/setcc.ll
index 2454af926aae..6f1ddbdc6aca 100644
--- a/test/CodeGen/X86/setcc.ll
+++ b/test/CodeGen/X86/setcc.ll
@@ -29,7 +29,7 @@ define i64 @t3(i64 %x) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: t3:
 ; CHECK: sbbq %rax, %rax
-; CHECK: andq $64, %rax
+; CHECK: andl $64, %eax
   %0 = icmp ult i64 %x, 18                        ; <i1> [#uses=1]
   %iftmp.2.0 = select i1 %0, i64 64, i64 0        ; <i64> [#uses=1]
   ret i64 %iftmp.2.0
diff --git a/test/CodeGen/X86/sext-load.ll b/test/CodeGen/X86/sext-load.ll
index 2753e8766294..2ea6e012192e 100644
--- a/test/CodeGen/X86/sext-load.ll
+++ b/test/CodeGen/X86/sext-load.ll
@@ -21,9 +21,9 @@ entry:
 ; CHECK-NEXT: ret
 define i32 @test2({i16, [6 x i8]}* %this) {
 entry:
-  %b48 = getelementptr inbounds { i16, [6 x i8] }* %this, i32 0, i32 1
+  %b48 = getelementptr inbounds { i16, [6 x i8] }, { i16, [6 x i8] }* %this, i32 0, i32 1
   %cast = bitcast [6 x i8]* %b48 to i48*
-  %bf.load = load i48* %cast, align 2
+  %bf.load = load i48, i48* %cast, align 2
   %bf.ashr = ashr i48 %bf.load, 32
   %bf.cast = trunc i48 %bf.ashr to i32
   ret i32 %bf.cast
diff --git a/test/CodeGen/X86/sha.ll b/test/CodeGen/X86/sha.ll
index bf81e9938ec8..fe42637bc538 100644
--- a/test/CodeGen/X86/sha.ll
+++ b/test/CodeGen/X86/sha.ll
@@ -13,7 +13,7 @@ entry:
 
 define <4 x i32> @test_sha1rnds4rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
 entry:
-  %0 = load <4 x i32>* %b
+  %0 = load <4 x i32>, <4 x i32>* %b
   %1 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %0, i8 3)
   ret <4 x i32> %1
   ; CHECK: test_sha1rnds4rm
@@ -32,7 +32,7 @@ entry:
 
 define <4 x i32> @test_sha1nexterm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
 entry:
-  %0 = load <4 x i32>* %b
+  %0 = load <4 x i32>, <4 x i32>* %b
   %1 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %0)
   ret <4 x i32> %1
   ; CHECK: test_sha1nexterm
@@ -51,7 +51,7 @@ entry:
 
 define <4 x i32> @test_sha1msg1rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
 entry:
-  %0 = load <4 x i32>* %b
+  %0 = load <4 x i32>, <4 x i32>* %b
   %1 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %0)
   ret <4 x i32> %1
   ; CHECK: test_sha1msg1rm
@@ -70,7 +70,7 @@ entry:
 
 define <4 x i32> @test_sha1msg2rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
 entry:
-  %0 = load <4 x i32>* %b
+  %0 = load <4 x i32>, <4 x i32>* %b
   %1 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %0)
   ret <4 x i32> %1
   ; CHECK: test_sha1msg2rm
@@ -91,7 +91,7 @@ entry:
 
 define <4 x i32> @test_sha256rnds2rm(<4 x i32> %a, <4 x i32>* %b, <4 x i32> %c) nounwind uwtable {
 entry:
-  %0 = load <4 x i32>* %b
+  %0 = load <4 x i32>, <4 x i32>* %b
   %1 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %0, <4 x i32> %c)
   ret <4 x i32> %1
   ; CHECK: test_sha256rnds2rm
@@ -112,7 +112,7 @@ entry:
 
 define <4 x i32> @test_sha256msg1rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
 entry:
-  %0 = load <4 x i32>* %b
+  %0 = load <4 x i32>, <4 x i32>* %b
   %1 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %0)
   ret <4 x i32> %1
   ; CHECK: test_sha256msg1rm
@@ -131,7 +131,7 @@ entry:
 
 define <4 x i32> @test_sha256msg2rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
 entry:
-  %0 = load <4 x i32>* %b
+  %0 = load <4 x i32>, <4 x i32>* %b
   %1 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %0)
   ret <4 x i32> %1
   ; CHECK: test_sha256msg2rm
diff --git a/test/CodeGen/X86/shift-and.ll b/test/CodeGen/X86/shift-and.ll
index d487368431b0..edd43a35ce56 100644
--- a/test/CodeGen/X86/shift-and.ll
+++ b/test/CodeGen/X86/shift-and.ll
@@ -38,7 +38,7 @@ define void @t3(i16 %t) nounwind {
 ; X64-NOT: andl
 ; X64: sarw
        %shamt = and i16 %t, 31
-       %tmp = load i16* @X
+       %tmp = load i16, i16* @X
        %tmp1 = ashr i16 %tmp, %shamt
        store i16 %tmp1, i16* @X
        ret void
@@ -71,7 +71,7 @@ entry:
 ; X64: decq
 ; X64: andq
   %shr = lshr i64 %key, 3
-  %0 = load i64* %val, align 8
+  %0 = load i64, i64* %val, align 8
   %sub = add i64 %0, 2305843009213693951
   %and = and i64 %sub, %shr
   ret i64 %and
diff --git a/test/CodeGen/X86/shift-avx2-crash.ll b/test/CodeGen/X86/shift-avx2-crash.ll
new file mode 100755
index 000000000000..b23d6e3359ee
--- /dev/null
+++ b/test/CodeGen/X86/shift-avx2-crash.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s  -mcpu=core-avx2 > /dev/null
+; This test crashed on variable shift creation on AVX2
+
+target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
+target triple = "i386-unknown-linux-gnu"
+
+define void @f_f(float* noalias nocapture %RET, float %aFOO, i32 %div)  {
+allocas:
+  %__idiv_table_u32_offset10_offset_load.i = add i64 0, -2
+  br label %if_then18.i
+
+if_then18.i:
+  %aFOO_load_to_uint32 = fptoui float %aFOO to i32
+  %aFOO_load_to_uint32_broadcast_init = insertelement <8 x i32> undef, i32 %aFOO_load_to_uint32, i32 0
+  %aFOO_load_to_uint32_broadcast = shufflevector <8 x i32> %aFOO_load_to_uint32_broadcast_init, <8 x i32> undef, <8 x i32> zeroinitializer
+
+  %multiplier_load_broadcast_init.i = insertelement <8 x i64> undef, i64 2, i32 0
+  %multiplier_load_broadcast.i = shufflevector <8 x i64> %multiplier_load_broadcast_init.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  %numerator_load_to_uint64.i = zext <8 x i32> %aFOO_load_to_uint32_broadcast to <8 x i64>
+
+  ;if replace '%__idiv_table_u32_offset10_offset_load.i' with '-2' or remove 'if_then18.i' label the error disappears
+  %add__shift_load21.i = add i64 %__idiv_table_u32_offset10_offset_load.i, 32
+  %add__shift_load21_broadcast_init.i = insertelement <8 x i64> undef, i64 %add__shift_load21.i, i32 0
+  %add__shift_load21_broadcast.i = shufflevector <8 x i64> %add__shift_load21_broadcast_init.i, <8 x i64> undef, <8 x i32> zeroinitializer
+
+  %mul_val_load_mult_load.i = mul <8 x i64> %numerator_load_to_uint64.i, %multiplier_load_broadcast.i
+  %bitop22.i = lshr <8 x i64> %mul_val_load_mult_load.i, %add__shift_load21_broadcast.i
+  %bitop22_to_uint32.i = trunc <8 x i64> %bitop22.i to <8 x i32>
+  br label %__fast_idiv___UM_vyuunu.exit
+
+
+__fast_idiv___UM_vyuunu.exit:                   
+  %calltmp_to_float = uitofp <8 x i32> %bitop22_to_uint32.i to <8 x float>
+  %ptrcast = bitcast float* %RET to <8 x float>*
+  store <8 x float> %calltmp_to_float, <8 x float>* %ptrcast, align 4
+  ret void
+}
+
diff --git a/test/CodeGen/X86/shift-bmi2.ll b/test/CodeGen/X86/shift-bmi2.ll
index 7615754a042a..63b6ec55fac8 100644
--- a/test/CodeGen/X86/shift-bmi2.ll
+++ b/test/CodeGen/X86/shift-bmi2.ll
@@ -27,7 +27,7 @@ entry:
 
 define i32 @shl32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
 entry:
-  %x = load i32* %p
+  %x = load i32, i32* %p
   %shl = shl i32 %x, %shamt
 ; BMI2: shl32p
 ; Source order scheduling prevents folding, rdar:14208996.
@@ -41,7 +41,7 @@ entry:
 
 define i32 @shl32pi(i32* %p) nounwind uwtable readnone {
 entry:
-  %x = load i32* %p
+  %x = load i32, i32* %p
   %shl = shl i32 %x, 5
 ; BMI2: shl32pi
 ; BMI2-NOT: shlxl
@@ -72,7 +72,7 @@ entry:
 
 define i64 @shl64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
 entry:
-  %x = load i64* %p
+  %x = load i64, i64* %p
   %shl = shl i64 %x, %shamt
 ; BMI264: shl64p
 ; BMI264: shlxq %{{.+}}, %{{.+}}, %{{.+}}
@@ -82,7 +82,7 @@ entry:
 
 define i64 @shl64pi(i64* %p) nounwind uwtable readnone {
 entry:
-  %x = load i64* %p
+  %x = load i64, i64* %p
   %shl = shl i64 %x, 7
 ; BMI264: shl64pi
 ; BMI264-NOT: shlxq
@@ -104,7 +104,7 @@ entry:
 
 define i32 @lshr32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
 entry:
-  %x = load i32* %p
+  %x = load i32, i32* %p
   %shl = lshr i32 %x, %shamt
 ; BMI2: lshr32p
 ; Source order scheduling prevents folding, rdar:14208996.
@@ -127,7 +127,7 @@ entry:
 
 define i64 @lshr64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
 entry:
-  %x = load i64* %p
+  %x = load i64, i64* %p
   %shl = lshr i64 %x, %shamt
 ; BMI264: lshr64p
 ; BMI264: shrxq %{{.+}}, %{{.+}}, %{{.+}}
@@ -149,7 +149,7 @@ entry:
 
 define i32 @ashr32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
 entry:
-  %x = load i32* %p
+  %x = load i32, i32* %p
   %shl = ashr i32 %x, %shamt
 ; BMI2: ashr32p
 ; Source order scheduling prevents folding, rdar:14208996.
@@ -172,7 +172,7 @@ entry:
 
 define i64 @ashr64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
 entry:
-  %x = load i64* %p
+  %x = load i64, i64* %p
   %shl = ashr i64 %x, %shamt
 ; BMI264: ashr64p
 ; BMI264: sarxq %{{.+}}, %{{.+}}, %{{.+}}
diff --git a/test/CodeGen/X86/shift-coalesce.ll b/test/CodeGen/X86/shift-coalesce.ll
index 5241042d0c55..dee7d373dcee 100644
--- a/test/CodeGen/X86/shift-coalesce.ll
+++ b/test/CodeGen/X86/shift-coalesce.ll
@@ -6,7 +6,7 @@
 ; PR687
 
 define i64 @foo(i64 %x, i64* %X) {
-        %tmp.1 = load i64* %X           ; <i64> [#uses=1]
+        %tmp.1 = load i64, i64* %X           ; <i64> [#uses=1]
         %tmp.3 = trunc i64 %tmp.1 to i8         ; <i8> [#uses=1]
         %shift.upgrd.1 = zext i8 %tmp.3 to i64          ; <i64> [#uses=1]
         %tmp.4 = shl i64 %x, %shift.upgrd.1             ; <i64> [#uses=1]
diff --git a/test/CodeGen/X86/shift-codegen.ll b/test/CodeGen/X86/shift-codegen.ll
index 88b86100794a..7d52bdeb9e3a 100644
--- a/test/CodeGen/X86/shift-codegen.ll
+++ b/test/CodeGen/X86/shift-codegen.ll
@@ -15,9 +15,9 @@ define void @fn1() {
 ; CHECK-NOT: lea
 ; CHECK: ret
 
-  %tmp = load i32* @Y             ; <i32> [#uses=1]
+  %tmp = load i32, i32* @Y             ; <i32> [#uses=1]
   %tmp1 = shl i32 %tmp, 3         ; <i32> [#uses=1]
-  %tmp2 = load i32* @X            ; <i32> [#uses=1]
+  %tmp2 = load i32, i32* @X            ; <i32> [#uses=1]
   %tmp3 = or i32 %tmp1, %tmp2             ; <i32> [#uses=1]
   store i32 %tmp3, i32* @X
   ret void
diff --git a/test/CodeGen/X86/shift-combine.ll b/test/CodeGen/X86/shift-combine.ll
index 113dedb4a00c..ec62bcdcdba1 100644
--- a/test/CodeGen/X86/shift-combine.ll
+++ b/test/CodeGen/X86/shift-combine.ll
@@ -12,8 +12,8 @@ define i32 @test_lshr_and(i32 %x) {
 entry:
   %tmp2 = lshr i32 %x, 2
   %tmp3 = and i32 %tmp2, 3
-  %tmp4 = getelementptr [4 x i32]* @array, i32 0, i32 %tmp3
-  %tmp5 = load i32* %tmp4, align 4
+  %tmp4 = getelementptr [4 x i32], [4 x i32]* @array, i32 0, i32 %tmp3
+  %tmp5 = load i32, i32* %tmp4, align 4
   ret i32 %tmp5
 }
 
diff --git a/test/CodeGen/X86/shift-folding.ll b/test/CodeGen/X86/shift-folding.ll
index ea9002c397b8..698878708977 100644
--- a/test/CodeGen/X86/shift-folding.ll
+++ b/test/CodeGen/X86/shift-folding.ll
@@ -9,7 +9,7 @@ define i32* @test1(i32* %P, i32 %X) {
 entry:
   %Y = lshr i32 %X, 2
   %gep.upgrd.1 = zext i32 %Y to i64
-  %P2 = getelementptr i32* %P, i64 %gep.upgrd.1
+  %P2 = getelementptr i32, i32* %P, i64 %gep.upgrd.1
   ret i32* %P2
 }
 
@@ -22,7 +22,7 @@ define i32* @test2(i32* %P, i32 %X) {
 entry:
   %Y = shl i32 %X, 2
   %gep.upgrd.2 = zext i32 %Y to i64
-  %P2 = getelementptr i32* %P, i64 %gep.upgrd.2
+  %P2 = getelementptr i32, i32* %P, i64 %gep.upgrd.2
   ret i32* %P2
 }
 
@@ -34,7 +34,7 @@ define i32* @test3(i32* %P, i32 %X) {
 
 entry:
   %Y = ashr i32 %X, 2
-  %P2 = getelementptr i32* %P, i32 %Y
+  %P2 = getelementptr i32, i32* %P, i32 %Y
   ret i32* %P2
 }
 
@@ -44,7 +44,7 @@ define fastcc i32 @test4(i32* %d) {
 ; CHECK: ret
 
 entry:
-  %tmp4 = load i32* %d
+  %tmp4 = load i32, i32* %d
   %tmp512 = lshr i32 %tmp4, 24
   ret i32 %tmp512
 }
@@ -62,8 +62,8 @@ entry:
   %i.zext = zext i16 %i to i32
   %index = lshr i32 %i.zext, 11
   %index.zext = zext i32 %index to i64
-  %val.ptr = getelementptr inbounds i32* %arr, i64 %index.zext
-  %val = load i32* %val.ptr
+  %val.ptr = getelementptr inbounds i32, i32* %arr, i64 %index.zext
+  %val = load i32, i32* %val.ptr
   %val.zext = zext i32 %val to i64
   %sum = add i64 %val.zext, %index.zext
   ret i64 %sum
diff --git a/test/CodeGen/X86/shift-i256.ll b/test/CodeGen/X86/shift-i256.ll
index d5f65a6ed18c..866e7e67fb0a 100644
--- a/test/CodeGen/X86/shift-i256.ll
+++ b/test/CodeGen/X86/shift-i256.ll
@@ -1,9 +1,21 @@
-; RUN: llc < %s -march=x86
-; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -march=x86        | FileCheck %s
+; RUN: llc < %s -march=x86-64 -O0 | FileCheck %s -check-prefix=CHECK-X64
+; RUN: llc < %s -march=x86-64 -O2 | FileCheck %s -check-prefix=CHECK-X64
 
-define void @t(i256 %x, i256 %a, i256* nocapture %r) nounwind readnone {
+; CHECK-LABEL: shift1
+define void @shift1(i256 %x, i256 %a, i256* nocapture %r) nounwind readnone {
 entry:
 	%0 = ashr i256 %x, %a
 	store i256 %0, i256* %r
         ret void
 }
+
+; CHECK-LABEL: shift2
+define i256 @shift2(i256 %c) nounwind
+{
+  %b = shl i256 1, %c  ; %c must not be a constant
+  ; Special case when %c is 0:
+  ; CHECK-X64: testb [[REG:%r[0-9]+b]], [[REG]]
+  ; CHECK-X64: cmoveq
+  ret i256 %b
+}
diff --git a/test/CodeGen/X86/shift-one.ll b/test/CodeGen/X86/shift-one.ll
index 0f80f90c773e..1ff02eb53e93 100644
--- a/test/CodeGen/X86/shift-one.ll
+++ b/test/CodeGen/X86/shift-one.ll
@@ -3,7 +3,7 @@
 @x = external global i32                ; <i32*> [#uses=1]
 
 define i32 @test() {
-        %tmp.0 = load i32* @x           ; <i32> [#uses=1]
+        %tmp.0 = load i32, i32* @x           ; <i32> [#uses=1]
         %tmp.1 = shl i32 %tmp.0, 1              ; <i32> [#uses=1]
         ret i32 %tmp.1
 }
diff --git a/test/CodeGen/X86/shift-pair.ll b/test/CodeGen/X86/shift-pair.ll
index 24ba1fc77074..62e51f002f7d 100644
--- a/test/CodeGen/X86/shift-pair.ll
+++ b/test/CodeGen/X86/shift-pair.ll
@@ -3,7 +3,7 @@
 define i64 @test(i64 %A) {
 ; CHECK: @test
 ; CHECK: shrq $54
-; CHECK: andq $1020
+; CHECK: andl $1020
 ; CHECK: ret
     %B = lshr i64 %A, 56
     %C = shl i64 %B, 2
diff --git a/test/CodeGen/X86/shift-parts.ll b/test/CodeGen/X86/shift-parts.ll
index 763da6397101..0b25a7595f2a 100644
--- a/test/CodeGen/X86/shift-parts.ll
+++ b/test/CodeGen/X86/shift-parts.ll
@@ -9,7 +9,7 @@
 
 define i32 @int87(i32 %uint64p_8, i1 %cond) nounwind {
 entry:
-  %srcval4 = load i320* bitcast (%0* @g_144 to i320*), align 8 ; <i320> [#uses=1]
+  %srcval4 = load i320, i320* bitcast (%0* @g_144 to i320*), align 8 ; <i320> [#uses=1]
   br label %for.cond
 
 for.cond:                                         ; preds = %for.cond, %entry
diff --git a/test/CodeGen/X86/shl-i64.ll b/test/CodeGen/X86/shl-i64.ll
index f00058a8a886..849912cc12e9 100644
--- a/test/CodeGen/X86/shl-i64.ll
+++ b/test/CodeGen/X86/shl-i64.ll
@@ -6,10 +6,10 @@
 
 define void @test_cl(<4 x i64>*  %dst, <4 x i64>* %src, i32 %idx) {
 entry:
-  %arrayidx = getelementptr inbounds <4 x i64> * %src, i32 %idx
-  %0 = load <4 x i64> * %arrayidx, align 32
-  %arrayidx1 = getelementptr inbounds <4 x i64> * %dst, i32 %idx
-  %1 = load <4 x i64> * %arrayidx1, align 32
+  %arrayidx = getelementptr inbounds <4 x i64>, <4 x i64> * %src, i32 %idx
+  %0 = load <4 x i64> , <4 x i64> * %arrayidx, align 32
+  %arrayidx1 = getelementptr inbounds <4 x i64>, <4 x i64> * %dst, i32 %idx
+  %1 = load <4 x i64> , <4 x i64> * %arrayidx1, align 32
   %2 = extractelement <4 x i64> %1, i32 0
   %and = and i64 %2, 63
   %3 = insertelement <4 x i64> undef, i64 %and, i32 0    
diff --git a/test/CodeGen/X86/shl_undef.ll b/test/CodeGen/X86/shl_undef.ll
index 705af5b4e332..f59d014a2d85 100644
--- a/test/CodeGen/X86/shl_undef.ll
+++ b/test/CodeGen/X86/shl_undef.ll
@@ -18,7 +18,7 @@ entry:
   %tmp0 = alloca i8
   %tmp1 = alloca i32
   store i8 1, i8* %tmp0
-  %tmp921.i7845 = load i8* %a0, align 1
+  %tmp921.i7845 = load i8, i8* %a0, align 1
   %tmp309 = xor i8 %tmp921.i7845, 104
   %tmp592 = zext i8 %tmp309 to i32
   %tmp862 = xor i32 1293461297, %tmp592
@@ -49,7 +49,7 @@ entry:
 ; shl undef, x -> 0
 define i32 @foo1_undef(i32* %a0) nounwind {
 entry:
-  %tmp1 = load i32* %a0, align 1
+  %tmp1 = load i32, i32* %a0, align 1
   %tmp2 = shl i32 undef, %tmp1;
   ret i32 %tmp2
 }
diff --git a/test/CodeGen/X86/shrink-compare.ll b/test/CodeGen/X86/shrink-compare.ll
index 4ddef4ca5351..0efa073cb191 100644
--- a/test/CodeGen/X86/shrink-compare.ll
+++ b/test/CodeGen/X86/shrink-compare.ll
@@ -4,7 +4,7 @@ declare void @bar()
 
 define void @test1(i32* nocapture %X) nounwind minsize {
 entry:
-  %tmp1 = load i32* %X, align 4
+  %tmp1 = load i32, i32* %X, align 4
   %and = and i32 %tmp1, 255
   %cmp = icmp eq i32 %and, 47
   br i1 %cmp, label %if.then, label %if.end
@@ -72,7 +72,7 @@ lor.end:                                          ; preds = %lor.rhs, %entry
 ; PR16551
 define void @test5(i32 %X) nounwind minsize {
 entry:
-  %bf.load = load i56* bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @x to i56*), align 4
+  %bf.load = load i56, i56* bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @x to i56*), align 4
   %bf.lshr = lshr i56 %bf.load, 32
   %bf.cast = trunc i56 %bf.lshr to i32
   %cmp = icmp ne i32 %bf.cast, 1
diff --git a/test/CodeGen/X86/shuffle-combine-crash.ll b/test/CodeGen/X86/shuffle-combine-crash.ll
index 6ab7b97e6a7b..06fcaa973893 100644
--- a/test/CodeGen/X86/shuffle-combine-crash.ll
+++ b/test/CodeGen/X86/shuffle-combine-crash.ll
@@ -18,7 +18,7 @@ define void @sample_test() {
   br i1 undef, label %5, label %1
 
 ; <label>:1                                       ; preds = %0
-  %2 = load <4 x i8>* undef
+  %2 = load <4 x i8>, <4 x i8>* undef
   %3 = shufflevector <4 x i8> %2, <4 x i8> undef, <4 x i32> <i32 2, i32 2, i32 0, i32 0>
   %4 = shufflevector <4 x i8> %3, <4 x i8> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
   store <4 x i8> %4, <4 x i8>* undef
diff --git a/test/CodeGen/X86/sibcall-4.ll b/test/CodeGen/X86/sibcall-4.ll
index 2c7f51d28025..23b73c031c0b 100644
--- a/test/CodeGen/X86/sibcall-4.ll
+++ b/test/CodeGen/X86/sibcall-4.ll
@@ -5,8 +5,8 @@ define ghccc void @t(i32* %Base_Arg, i32* %Sp_Arg, i32* %Hp_Arg, i32 %R1_Arg) no
 cm1:
 ; CHECK-LABEL: t:
 ; CHECK: jmpl *%eax
-  %nm3 = getelementptr i32* %Sp_Arg, i32 1
-  %nm9 = load i32* %Sp_Arg
+  %nm3 = getelementptr i32, i32* %Sp_Arg, i32 1
+  %nm9 = load i32, i32* %Sp_Arg
   %nma = inttoptr i32 %nm9 to void (i32*, i32*, i32*, i32)*
   tail call ghccc void %nma(i32* %Base_Arg, i32* %nm3, i32* %Hp_Arg, i32 %R1_Arg) nounwind
   ret void
diff --git a/test/CodeGen/X86/sibcall-5.ll b/test/CodeGen/X86/sibcall-5.ll
index b065cce17b24..aab028bd17c8 100644
--- a/test/CodeGen/X86/sibcall-5.ll
+++ b/test/CodeGen/X86/sibcall-5.ll
@@ -46,7 +46,7 @@ define hidden { double, double } @foo2(%0* %self, i8* nocapture %_cmd) uwtable o
 ; X64_BAD: call
 ; X64_BAD: call
 ; X64_BAD: call
-  %1 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_2", align 8, !invariant.load !0
+  %1 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_2", align 8, !invariant.load !0
   %2 = bitcast %0* %self to i8*
   %3 = tail call { double, double } bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to { double, double } (i8*, i8*)*)(i8* %2, i8* %1) optsize
   %4 = extractvalue { double, double } %3, 0
diff --git a/test/CodeGen/X86/sibcall-win64.ll b/test/CodeGen/X86/sibcall-win64.ll
new file mode 100644
index 000000000000..f7038726f9ca
--- /dev/null
+++ b/test/CodeGen/X86/sibcall-win64.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s
+
+declare x86_64_win64cc void @win64_callee(i32)
+declare void @sysv_callee(i32)
+
+define void @sysv_caller(i32 %p1) {
+entry:
+  tail call x86_64_win64cc void @win64_callee(i32 %p1)
+  ret void
+}
+
+; CHECK-LABEL: sysv_caller:
+; CHECK: subq $40, %rsp
+; CHECK: callq win64_callee
+; CHECK: addq $40, %rsp
+; CHECK: retq
+
+define x86_64_win64cc void @win64_caller(i32 %p1) {
+entry:
+  tail call void @sysv_callee(i32 %p1)
+  ret void
+}
+
+; CHECK-LABEL: win64_caller:
+; CHECK: callq sysv_callee
+; CHECK: retq
+
+define void @sysv_matched(i32 %p1) {
+  tail call void @sysv_callee(i32 %p1)
+  ret void
+}
+
+; CHECK-LABEL: sysv_matched:
+; CHECK: jmp sysv_callee # TAILCALL
+
+define x86_64_win64cc void @win64_matched(i32 %p1) {
+  tail call x86_64_win64cc void @win64_callee(i32 %p1)
+  ret void
+}
+
+; CHECK-LABEL: win64_matched:
+; CHECK: jmp win64_callee # TAILCALL
diff --git a/test/CodeGen/X86/sibcall.ll b/test/CodeGen/X86/sibcall.ll
index 28fc626afd9d..b94960af65ab 100644
--- a/test/CodeGen/X86/sibcall.ll
+++ b/test/CodeGen/X86/sibcall.ll
@@ -1,5 +1,6 @@
 ; RUN: llc < %s -mtriple=i686-linux   -mcpu=core2 -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=32
 ; RUN: llc < %s -mtriple=x86_64-linux -mcpu=core2 -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=64
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mcpu=core2 -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=X32ABI
 
 define void @t1(i32 %x) nounwind ssp {
 entry:
@@ -8,6 +9,9 @@ entry:
 
 ; 64-LABEL: t1:
 ; 64: jmp {{_?}}foo
+
+; X32ABI-LABEL: t1:
+; X32ABI: jmp {{_?}}foo
   tail call void @foo() nounwind
   ret void
 }
@@ -21,6 +25,9 @@ entry:
 
 ; 64-LABEL: t2:
 ; 64: jmp {{_?}}foo2
+
+; X32ABI-LABEL: t2:
+; X32ABI: jmp {{_?}}foo2
   %0 = tail call i32 @foo2() nounwind
   ret void
 }
@@ -34,6 +41,9 @@ entry:
 
 ; 64-LABEL: t3:
 ; 64: jmp {{_?}}foo3
+
+; X32ABI-LABEL: t3:
+; X32ABI: jmp {{_?}}foo3
   %0 = tail call i32 @foo3() nounwind
   ret void
 }
@@ -49,6 +59,10 @@ entry:
 ; 64-LABEL: t4:
 ; 64-NOT: call
 ; 64: jmpq *
+
+; X32ABI-LABEL: t4:
+; X32ABI-NOT: call
+; X32ABI: jmpq *
   tail call void %x(i32 0) nounwind
   ret void
 }
@@ -62,6 +76,13 @@ entry:
 ; 64-LABEL: t5:
 ; 64-NOT: call
 ; 64: jmpq *%rdi
+
+; X32ABI-LABEL: t5:
+; X32ABI-NOT: call
+; FIXME: This isn't needed since x32 psABI specifies that callers must
+;        zero-extend pointers passed in registers.
+; X32ABI: movl %edi, %eax
+; X32ABI: jmpq *%rax
   tail call void %x() nounwind
   ret void
 }
@@ -75,6 +96,10 @@ entry:
 ; 64-LABEL: t6:
 ; 64: jmp {{_?}}t6
 ; 64: jmp {{_?}}bar
+
+; X32ABI-LABEL: t6:
+; X32ABI: jmp {{_?}}t6
+; X32ABI: jmp {{_?}}bar
   %0 = icmp slt i32 %x, 10
   br i1 %0, label %bb, label %bb1
 
@@ -97,6 +122,9 @@ entry:
 
 ; 64-LABEL: t7:
 ; 64: jmp {{_?}}bar2
+
+; X32ABI-LABEL: t7:
+; X32ABI: jmp {{_?}}bar2
   %0 = tail call i32 @bar2(i32 %a, i32 %b, i32 %c) nounwind
   ret i32 %0
 }
@@ -110,6 +138,9 @@ entry:
 
 ; 64-LABEL: t8:
 ; 64: jmp {{_?}}bar3
+
+; X32ABI-LABEL: t8:
+; X32ABI: jmp {{_?}}bar3
   %0 = tail call signext i16 @bar3() nounwind      ; <i16> [#uses=1]
   ret i16 %0
 }
@@ -123,6 +154,9 @@ entry:
 
 ; 64-LABEL: t9:
 ; 64: jmpq *
+
+; X32ABI-LABEL: t9:
+; X32ABI: jmpq *
   %0 = bitcast i32 (i32)* %x to i16 (i32)*
   %1 = tail call signext i16 %0(i32 0) nounwind
   ret i16 %1
@@ -135,6 +169,9 @@ entry:
 
 ; 64-LABEL: t10:
 ; 64: callq
+
+; X32ABI-LABEL: t10:
+; X32ABI: callq
   %0 = tail call i32 @foo4() noreturn nounwind
   unreachable
 }
@@ -153,9 +190,14 @@ define i32 @t11(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind ssp {
 ; 32: jmp {{_?}}foo5
 
 ; 64-LABEL: t11:
-; 64-NOT: subq ${{[0-9]+}}, %esp
-; 64-NOT: addq ${{[0-9]+}}, %esp
+; 64-NOT: subq ${{[0-9]+}}, %rsp
+; 64-NOT: addq ${{[0-9]+}}, %rsp
 ; 64: jmp {{_?}}foo5
+
+; X32ABI-LABEL: t11:
+; X32ABI-NOT: subl ${{[0-9]+}}, %esp
+; X32ABI-NOT: addl ${{[0-9]+}}, %esp
+; X32ABI: jmp {{_?}}foo5
 entry:
   %0 = icmp eq i32 %x, 0
   br i1 %0, label %bb6, label %bb
@@ -179,9 +221,14 @@ define i32 @t12(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind ssp {
 ; 32: jmp {{_?}}foo6
 
 ; 64-LABEL: t12:
-; 64-NOT: subq ${{[0-9]+}}, %esp
-; 64-NOT: addq ${{[0-9]+}}, %esp
+; 64-NOT: subq ${{[0-9]+}}, %rsp
+; 64-NOT: addq ${{[0-9]+}}, %rsp
 ; 64: jmp {{_?}}foo6
+
+; X32ABI-LABEL: t12:
+; X32ABI-NOT: subl ${{[0-9]+}}, %esp
+; X32ABI-NOT: addl ${{[0-9]+}}, %esp
+; X32ABI: jmp {{_?}}foo6
 entry:
   %0 = icmp eq i32 %x, 0
   br i1 %0, label %bb2, label %bb
@@ -210,6 +257,11 @@ define %struct.ns* @t13(%struct.cp* %yy) nounwind ssp {
 ; 64-NOT: jmp
 ; 64: callq
 ; 64: ret
+
+; X32ABI-LABEL: t13:
+; X32ABI-NOT: jmp
+; X32ABI: callq
+; X32ABI: ret
 entry:
   %0 = tail call fastcc %struct.ns* @foo7(%struct.cp* byval align 4 %yy, i8 signext 0) nounwind
   ret %struct.ns* %0
@@ -230,11 +282,16 @@ entry:
 ; 64: movq 32(%rdi)
 ; 64-NOT: movq 16(%rdi)
 ; 64: jmpq *16({{%rdi|%rax}})
-  %0 = getelementptr inbounds %struct.__block_literal_2* %.block_descriptor, i64 0, i32 5 ; <void ()**> [#uses=1]
-  %1 = load void ()** %0, align 8                 ; <void ()*> [#uses=2]
+
+; X32ABI-LABEL: t14:
+; X32ABI: movl 20(%edi), %edi
+; X32ABI-NEXT: movl 12(%edi), %eax
+; X32ABI-NEXT: jmpq *%rax
+  %0 = getelementptr inbounds %struct.__block_literal_2, %struct.__block_literal_2* %.block_descriptor, i64 0, i32 5 ; <void ()**> [#uses=1]
+  %1 = load void ()*, void ()** %0, align 8                 ; <void ()*> [#uses=2]
   %2 = bitcast void ()* %1 to %struct.__block_literal_1* ; <%struct.__block_literal_1*> [#uses=1]
-  %3 = getelementptr inbounds %struct.__block_literal_1* %2, i64 0, i32 3 ; <i8**> [#uses=1]
-  %4 = load i8** %3, align 8                      ; <i8*> [#uses=1]
+  %3 = getelementptr inbounds %struct.__block_literal_1, %struct.__block_literal_1* %2, i64 0, i32 3 ; <i8**> [#uses=1]
+  %4 = load i8*, i8** %3, align 8                      ; <i8*> [#uses=1]
   %5 = bitcast i8* %4 to void (i8*)*              ; <void (i8*)*> [#uses=1]
   %6 = bitcast void ()* %1 to i8*                 ; <i8*> [#uses=1]
   tail call void %5(i8* %6) nounwind
@@ -252,6 +309,10 @@ define void @t15(%struct.foo* noalias sret %agg.result) nounwind  {
 ; 64-LABEL: t15:
 ; 64: callq {{_?}}f
 ; 64: retq
+
+; X32ABI-LABEL: t15:
+; X32ABI: callq {{_?}}f
+; X32ABI: retq
   tail call fastcc void @f(%struct.foo* noalias sret %agg.result) nounwind
   ret void
 }
@@ -266,6 +327,9 @@ entry:
 
 ; 64-LABEL: t16:
 ; 64: jmp {{_?}}bar4
+
+; X32ABI-LABEL: t16:
+; X32ABI: jmp {{_?}}bar4
   %0 = tail call double @bar4() nounwind
   ret void
 }
@@ -281,7 +345,11 @@ entry:
 ; 64-LABEL: t17:
 ; 64: xorl %eax, %eax
 ; 64: jmp {{_?}}bar5
-  tail call void (...)* @bar5() nounwind
+
+; X32ABI-LABEL: t17:
+; X32ABI: xorl %eax, %eax
+; X32ABI: jmp {{_?}}bar5
+  tail call void (...) @bar5() nounwind
   ret void
 }
 
@@ -297,7 +365,11 @@ entry:
 ; 64-LABEL: t18:
 ; 64: xorl %eax, %eax
 ; 64: jmp {{_?}}bar6
-  %0 = tail call double (...)* @bar6() nounwind
+
+; X32ABI-LABEL: t18:
+; X32ABI: xorl %eax, %eax
+; X32ABI: jmp {{_?}}bar6
+  %0 = tail call double (...) @bar6() nounwind
   ret void
 }
 
@@ -308,6 +380,10 @@ entry:
 ; CHECK-LABEL: t19:
 ; CHECK: andl $-32
 ; CHECK: calll {{_?}}foo
+
+; X32ABI-LABEL: t19:
+; X32ABI: andl $-32
+; X32ABI: callq {{_?}}foo
   tail call void @foo() nounwind
   ret void
 }
@@ -324,6 +400,9 @@ entry:
 
 ; 64-LABEL: t20:
 ; 64: jmp {{_?}}foo20
+
+; X32ABI-LABEL: t20:
+; X32ABI: jmp {{_?}}foo20
   %0 = tail call fastcc double @foo20(double %x) nounwind
   ret double %0
 }
diff --git a/test/CodeGen/X86/simple-zext.ll b/test/CodeGen/X86/simple-zext.ll
index ccd8292bcdb3..b80c0bc6b10d 100644
--- a/test/CodeGen/X86/simple-zext.ll
+++ b/test/CodeGen/X86/simple-zext.ll
@@ -6,7 +6,7 @@
 
 define void @load_zext(i32* nocapture %p){
 entry:
-  %0 = load i32* %p, align 4
+  %0 = load i32, i32* %p, align 4
   %and = and i32 %0, 255
   tail call void @use(i32 %and)
   ret void
diff --git a/test/CodeGen/X86/sincos-opt.ll b/test/CodeGen/X86/sincos-opt.ll
index 1e34a2be10b3..9d02bcd9a6c7 100644
--- a/test/CodeGen/X86/sincos-opt.ll
+++ b/test/CodeGen/X86/sincos-opt.ll
@@ -15,9 +15,8 @@ entry:
 
 ; OSX_SINCOS-LABEL: test1:
 ; OSX_SINCOS: callq ___sincosf_stret
-; OSX_SINCOS: movaps %xmm0, %xmm1
-; OSX_SINCOS: shufps {{.*}} ## xmm1 = xmm1[1,1,2,3]
-; OSX_SINCOS: addss %xmm0, %xmm1
+; OSX_SINCOS: movshdup {{.*}} xmm1 = xmm0[1,1,3,3]
+; OSX_SINCOS: addss %xmm1, %xmm0
 
 ; OSX_NOOPT: test1
 ; OSX_NOOPT: callq _sinf
diff --git a/test/CodeGen/X86/sink-cheap-instructions.ll b/test/CodeGen/X86/sink-cheap-instructions.ll
new file mode 100644
index 000000000000..9b9a6865af93
--- /dev/null
+++ b/test/CodeGen/X86/sink-cheap-instructions.ll
@@ -0,0 +1,62 @@
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK
+; RUN: llc < %s -mtriple=x86_64-linux -sink-insts-to-avoid-spills | FileCheck %s -check-prefix=SINK
+
+; Ensure that we sink copy-like instructions into loops to avoid register
+; spills.
+
+; CHECK: Spill
+; SINK-NOT: Spill
+
+%struct.A = type { i32, i32, i32, i32, i32, i32 }
+
+define void @_Z1fPhP1A(i8* nocapture readonly %input, %struct.A* %a) {
+  %1 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 0
+  %2 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 1
+  %3 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 2
+  %4 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 3
+  %5 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 4
+  %6 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 5
+  br label %.backedge
+
+.backedge:
+  %.0 = phi i8* [ %input, %0 ], [ %7, %.backedge.backedge ]
+  %7 = getelementptr inbounds i8, i8* %.0, i64 1
+  %8 = load i8, i8* %7, align 1
+  switch i8 %8, label %.backedge.backedge [
+    i8 0, label %9
+    i8 10, label %10
+    i8 20, label %11
+    i8 30, label %12
+    i8 40, label %13
+    i8 50, label %14
+  ]
+
+; <label>:9
+  tail call void @_Z6assignPj(i32* %1)
+  br label %.backedge.backedge
+
+; <label>:10
+  tail call void @_Z6assignPj(i32* %2)
+  br label %.backedge.backedge
+
+.backedge.backedge:
+  br label %.backedge
+
+; <label>:11
+  tail call void @_Z6assignPj(i32* %3)
+  br label %.backedge.backedge
+
+; <label>:12
+  tail call void @_Z6assignPj(i32* %4)
+  br label %.backedge.backedge
+
+; <label>:13
+  tail call void @_Z6assignPj(i32* %5)
+  br label %.backedge.backedge
+
+; <label>:14
+  tail call void @_Z6assignPj(i32* %6)
+  br label %.backedge.backedge
+}
+
+declare void @_Z6assignPj(i32*)
diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll
index 455cf24bce1c..972fbdf48cb5 100644
--- a/test/CodeGen/X86/sink-hoist.ll
+++ b/test/CodeGen/X86/sink-hoist.ll
@@ -9,7 +9,7 @@
 ; CHECK-NEXT: testb $1, %dil
 ; CHECK-NEXT: jne
 ; CHECK-NEXT: divsd
-; CHECK-NEXT: movaps
+; CHECK-NEXT: movapd
 ; CHECK-NEXT: ret
 ; CHECK:      divsd
 
@@ -28,7 +28,7 @@ define double @foo(double %x, double %y, i1 %c) nounwind {
 ; CHECK-NEXT: testb $1, %dil
 ; CHECK-NEXT: je
 ; CHECK:      divsd
-; CHECK:      movaps
+; CHECK:      movapd
 ; CHECK:      ret
 define double @split(double %x, double %y, i1 %c) nounwind {
   %a = fdiv double %x, 3.2
@@ -49,8 +49,8 @@ entry:
 
 bb:
   %i.03 = phi i64 [ 0, %entry ], [ %3, %bb ]
-  %scevgep = getelementptr double* %p, i64 %i.03
-  %1 = load double* %scevgep, align 8
+  %scevgep = getelementptr double, double* %p, i64 %i.03
+  %1 = load double, double* %scevgep, align 8
   %2 = fdiv double 3.200000e+00, %1
   store double %2, double* %scevgep, align 8
   %3 = add nsw i64 %i.03, 1
@@ -104,7 +104,7 @@ entry:
 bb:                                               ; preds = %bb60
   %i.0 = phi i32 [ 0, %bb60 ]                    ; <i32> [#uses=2]
   %0 = bitcast float* %x_addr.0 to <4 x float>*   ; <<4 x float>*> [#uses=1]
-  %1 = load <4 x float>* %0, align 16             ; <<4 x float>> [#uses=4]
+  %1 = load <4 x float>, <4 x float>* %0, align 16             ; <<4 x float>> [#uses=4]
   %tmp20 = bitcast <4 x float> %1 to <4 x i32>    ; <<4 x i32>> [#uses=1]
   %tmp22 = and <4 x i32> %tmp20, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> ; <<4 x i32>> [#uses=1]
   %tmp23 = bitcast <4 x i32> %tmp22 to <4 x float> ; <<4 x float>> [#uses=1]
@@ -127,10 +127,10 @@ bb:                                               ; preds = %bb60
   %tmp58 = bitcast <4 x i32> %tmp57 to <4 x float> ; <<4 x float>> [#uses=1]
   %4 = bitcast float* %y_addr.0 to <4 x float>*   ; <<4 x float>*> [#uses=1]
   store <4 x float> %tmp58, <4 x float>* %4, align 16
-  %5 = getelementptr float* %x_addr.0, i64 4      ; <float*> [#uses=1]
-  %6 = getelementptr float* %y_addr.0, i64 4      ; <float*> [#uses=1]
+  %5 = getelementptr float, float* %x_addr.0, i64 4      ; <float*> [#uses=1]
+  %6 = getelementptr float, float* %y_addr.0, i64 4      ; <float*> [#uses=1]
   %7 = add i32 %i.0, 4                            ; <i32> [#uses=1]
-  %8 = load i32* %n, align 4                      ; <i32> [#uses=1]
+  %8 = load i32, i32* %n, align 4                      ; <i32> [#uses=1]
   %9 = icmp sgt i32 %8, %7                        ; <i1> [#uses=1]
   br i1 %9, label %bb60, label %return
 
@@ -157,14 +157,14 @@ declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone
 
 define void @default_get_pch_validity() nounwind {
 entry:
-  %tmp4 = load i32* @cl_options_count, align 4    ; <i32> [#uses=1]
+  %tmp4 = load i32, i32* @cl_options_count, align 4    ; <i32> [#uses=1]
   %tmp5 = icmp eq i32 %tmp4, 0                    ; <i1> [#uses=1]
   br i1 %tmp5, label %bb6, label %bb2
 
 bb2:                                              ; preds = %bb2, %entry
   %i.019 = phi i64 [ 0, %entry ], [ %tmp25, %bb2 ] ; <i64> [#uses=1]
   %tmp25 = add i64 %i.019, 1                      ; <i64> [#uses=2]
-  %tmp11 = load i32* @cl_options_count, align 4   ; <i32> [#uses=1]
+  %tmp11 = load i32, i32* @cl_options_count, align 4   ; <i32> [#uses=1]
   %tmp12 = zext i32 %tmp11 to i64                 ; <i64> [#uses=1]
   %tmp13 = icmp ugt i64 %tmp12, %tmp25            ; <i1> [#uses=1]
   br i1 %tmp13, label %bb2, label %bb6
diff --git a/test/CodeGen/X86/sink-out-of-loop.ll b/test/CodeGen/X86/sink-out-of-loop.ll
index 6757f315b6da..4bf829a02738 100644
--- a/test/CodeGen/X86/sink-out-of-loop.ll
+++ b/test/CodeGen/X86/sink-out-of-loop.ll
@@ -61,7 +61,7 @@ entry:
 loop:
   %i = phi i32 [ 0, %entry ], [ %i2, %loop ]
   %j = mul i32 %i, %i
-  %addr = getelementptr i32* %output, i32 %i
+  %addr = getelementptr i32, i32* %output, i32 %i
   store i32 %i, i32* %addr
   %i2 = add i32 %i, 1
   %exit_cond = icmp sge i32 %i2, %n
diff --git a/test/CodeGen/X86/sjlj.ll b/test/CodeGen/X86/sjlj.ll
index 681db0094384..3fa3d30ea5cc 100644
--- a/test/CodeGen/X86/sjlj.ll
+++ b/test/CodeGen/X86/sjlj.ll
@@ -15,9 +15,9 @@ declare void @llvm.eh.sjlj.longjmp(i8*) nounwind
 
 define i32 @sj0() nounwind {
   %fp = tail call i8* @llvm.frameaddress(i32 0)
-  store i8* %fp, i8** getelementptr inbounds ([5 x i8*]* @buf, i64 0, i64 0), align 16
+  store i8* %fp, i8** getelementptr inbounds ([5 x i8*], [5 x i8*]* @buf, i64 0, i64 0), align 16
   %sp = tail call i8* @llvm.stacksave()
-  store i8* %sp, i8** getelementptr inbounds ([5 x i8*]* @buf, i64 0, i64 2), align 16
+  store i8* %sp, i8** getelementptr inbounds ([5 x i8*], [5 x i8*]* @buf, i64 0, i64 2), align 16
   %r = tail call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([5 x i8*]* @buf to i8*))
   ret i32 %r
 ; X86: sj0
diff --git a/test/CodeGen/X86/slow-incdec.ll b/test/CodeGen/X86/slow-incdec.ll
index 323e3ae8c472..1857f61e6c29 100644
--- a/test/CodeGen/X86/slow-incdec.ll
+++ b/test/CodeGen/X86/slow-incdec.ll
@@ -28,8 +28,8 @@ for.cond:                                         ; preds = %for.body
 
 for.body:                                         ; preds = %for.body.preheader, %for.cond
   %i.06 = phi i32 [ %dec, %for.cond ], [ %s, %for.body.preheader ]
-  %arrayidx = getelementptr inbounds i32* %a, i32 %i.06
-  %0 = load i32* %arrayidx, align 4, !tbaa !1
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %i.06
+  %0 = load i32, i32* %arrayidx, align 4, !tbaa !1
   %cmp1 = icmp eq i32 %0, 0
 ;
   %dec = add nsw i32 %i.06, -1
@@ -59,8 +59,8 @@ for.cond:                                         ; preds = %for.body
 
 for.body:                                         ; preds = %for.body.preheader, %for.cond
   %i.06 = phi i32 [ %inc, %for.cond ], [ %s, %for.body.preheader ]
-  %arrayidx = getelementptr inbounds i32* %a, i32 %i.06
-  %0 = load i32* %arrayidx, align 4, !tbaa !1
+  %arrayidx = getelementptr inbounds i32, i32* %a, i32 %i.06
+  %0 = load i32, i32* %arrayidx, align 4, !tbaa !1
   %cmp1 = icmp eq i32 %0, 0
   %inc = add nsw i32 %i.06, 1
   br i1 %cmp1, label %for.end.loopexit, label %for.cond
diff --git a/test/CodeGen/X86/smul-with-overflow.ll b/test/CodeGen/X86/smul-with-overflow.ll
index cefbda64751b..2b21f4ff84e9 100644
--- a/test/CodeGen/X86/smul-with-overflow.ll
+++ b/test/CodeGen/X86/smul-with-overflow.ll
@@ -11,11 +11,11 @@ entry:
   br i1 %obit, label %overflow, label %normal
 
 normal:
-  %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
+  %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
   ret i1 true
 
 overflow:
-  %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+  %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
 ; CHECK-LABEL: test1:
 ; CHECK: imull
@@ -30,11 +30,11 @@ entry:
   br i1 %obit, label %overflow, label %normal
 
 overflow:
-  %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+  %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
 
 normal:
-  %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
+  %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
   ret i1 true
 ; CHECK-LABEL: test2:
 ; CHECK: imull
diff --git a/test/CodeGen/X86/soft-fp.ll b/test/CodeGen/X86/soft-fp.ll
index a52135dc9087..fa38d1044a48 100644
--- a/test/CodeGen/X86/soft-fp.ll
+++ b/test/CodeGen/X86/soft-fp.ll
@@ -1,14 +1,16 @@
-; RUN: llc < %s -march=x86    -mattr=+sse2 -soft-float | not grep xmm
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 -soft-float | not grep xmm
+; RUN: llc < %s -march=x86    -mattr=+sse2,+soft-float | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mattr=+sse2,+soft-float | FileCheck %s
 
-	%struct.__va_list_tag = type { i32, i32, i8*, i8* }
+; CHECK-NOT: xmm{[0-9]+}
+
+%struct.__va_list_tag = type { i32, i32, i8*, i8* }
 
 define i32 @t1(i32 %a, ...) nounwind {
 entry:
 	%va = alloca [1 x %struct.__va_list_tag], align 8		; <[1 x %struct.__va_list_tag]*> [#uses=2]
 	%va12 = bitcast [1 x %struct.__va_list_tag]* %va to i8*		; <i8*> [#uses=2]
 	call void @llvm.va_start(i8* %va12)
-	%va3 = getelementptr [1 x %struct.__va_list_tag]* %va, i64 0, i64 0		; <%struct.__va_list_tag*> [#uses=1]
+	%va3 = getelementptr [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %va, i64 0, i64 0		; <%struct.__va_list_tag*> [#uses=1]
 	call void @bar(%struct.__va_list_tag* %va3) nounwind
 	call void @llvm.va_end(i8* %va12)
 	ret i32 undef
diff --git a/test/CodeGen/X86/splat-const.ll b/test/CodeGen/X86/splat-const.ll
new file mode 100644
index 000000000000..19997b03ad5e
--- /dev/null
+++ b/test/CodeGen/X86/splat-const.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -mcpu=penryn | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mcpu=sandybridge | FileCheck %s --check-prefix=AVX
+; RUN: llc < %s -mcpu=haswell | FileCheck %s --check-prefix=AVX2
+; This checks that lowering for creation of constant vectors is sane and
+; doesn't use redundant shuffles. (fixes PR22276)
+target triple = "x86_64-unknown-unknown"
+
+define <4 x i32> @zero_vector() {
+; SSE-LABEL: zero_vector:
+; SSE: xorps %xmm0, %xmm0
+; SSE-NEXT: retq
+; AVX-LABEL: zero_vector:
+; AVX: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: retq
+; AVX2-LABEL: zero_vector:
+; AVX2: vxorps %xmm0, %xmm0, %xmm0
+; AVX2-NEXT: retq
+  %zero = insertelement <4 x i32> undef, i32 0, i32 0
+  %splat = shufflevector <4 x i32> %zero, <4 x i32> undef, <4 x i32> zeroinitializer
+  ret <4 x i32> %splat
+}
+
+; Note that for the "const_vector" versions, lowering that uses a shuffle
+; instead of a load would be legitimate, if it's a single broadcast shuffle.
+; (as opposed to the previous mess)
+; However, this is not the current preferred lowering.
+define <4 x i32> @const_vector() {
+; SSE-LABEL: const_vector:
+; SSE: movaps {{.*}}, %xmm0 # xmm0 = [42,42,42,42]
+; SSE-NEXT: retq
+; AVX-LABEL: const_vector:
+; AVX: vmovaps {{.*}}, %xmm0 # xmm0 = [42,42,42,42]
+; AVX-NEXT: retq
+; AVX2-LABEL: const_vector:
+; AVX2: vbroadcastss {{[^%].*}}, %xmm0
+; AVX2-NEXT: retq
+  %const = insertelement <4 x i32> undef, i32 42, i32 0
+  %splat = shufflevector <4 x i32> %const, <4 x i32> undef, <4 x i32> zeroinitializer
+  ret <4 x i32> %splat
+}
diff --git a/test/CodeGen/X86/splat-for-size.ll b/test/CodeGen/X86/splat-for-size.ll
index c052ad2aa146..635aa821d78a 100644
--- a/test/CodeGen/X86/splat-for-size.ll
+++ b/test/CodeGen/X86/splat-for-size.ll
@@ -138,4 +138,18 @@ define <32 x i8> @splat_v32i8(<32 x i8> %x) #0 {
 ; CHECK: retq
 }
 
+; PR23259: Verify that ISel doesn't crash with a 'fatal error in backend'
+; due to a missing AVX pattern to select a v2i64 X86ISD::BROADCAST of a
+; loadi64 with multiple uses.
+
+@A = common global <3 x i64> zeroinitializer, align 32
+
+define <8 x i64> @pr23259() #0 {
+entry:
+  %0 = load <4 x i64>, <4 x i64>* bitcast (<3 x i64>* @A to <4 x i64>*), align 32
+  %1 = shufflevector <4 x i64> %0, <4 x i64> undef, <3 x i32> <i32 undef, i32 undef, i32 2>
+  %shuffle = shufflevector <3 x i64> <i64 1, i64 undef, i64 undef>, <3 x i64> %1, <8 x i32> <i32 5, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+  ret <8 x i64> %shuffle
+}
+
 attributes #0 = { optsize }
diff --git a/test/CodeGen/X86/split-eh-lpad-edges.ll b/test/CodeGen/X86/split-eh-lpad-edges.ll
index 756a3ddc86bb..852214e7c248 100644
--- a/test/CodeGen/X86/split-eh-lpad-edges.ll
+++ b/test/CodeGen/X86/split-eh-lpad-edges.ll
@@ -16,7 +16,7 @@ entry:
 			to label %invcont unwind label %lpad		; <%struct.NSObject*> [#uses=1]
 
 invcont:		; preds = %entry
-	%1 = invoke %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...)* @objc_msgSend(%struct.NSObject* %0, %struct.objc_selector* null)
+	%1 = invoke %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...) @objc_msgSend(%struct.NSObject* %0, %struct.objc_selector* null)
 			to label %invcont26 unwind label %lpad		; <%struct.NSObject*> [#uses=0]
 
 invcont26:		; preds = %invcont
diff --git a/test/CodeGen/X86/split-vector-bitcast.ll b/test/CodeGen/X86/split-vector-bitcast.ll
index fae15cfaf26e..8d80754b9a35 100644
--- a/test/CodeGen/X86/split-vector-bitcast.ll
+++ b/test/CodeGen/X86/split-vector-bitcast.ll
@@ -3,7 +3,7 @@
 ; PR10497 + another isel issue with sse2 disabled
 ; (This is primarily checking that this construct doesn't crash.)
 define void @a(<2 x float>* %a, <2 x i32>* %b) {
-  %cc = load <2 x float>* %a
+  %cc = load <2 x float>, <2 x float>* %a
   %c = fadd <2 x float> %cc, %cc
   %dd = bitcast <2 x float> %c to <2 x i32>
   %d = add <2 x i32> %dd, %dd
diff --git a/test/CodeGen/X86/sqrt-fastmath.ll b/test/CodeGen/X86/sqrt-fastmath.ll
index 24b175eed7a3..4c6b521156e0 100644
--- a/test/CodeGen/X86/sqrt-fastmath.ll
+++ b/test/CodeGen/X86/sqrt-fastmath.ll
@@ -1,132 +1,141 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core2 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 | FileCheck %s --check-prefix=BTVER2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx,use-sqrt-est | FileCheck %s --check-prefix=ESTIMATE
 
-; generated using "clang -S -O2 -ffast-math -emit-llvm sqrt.c" from
-; #include <math.h>
-; 
-; double fd(double d){
-;   return sqrt(d);
-; }
-; 
-; float ff(float f){
-;   return sqrtf(f);
-; }
-; 
-; long double fld(long double ld){
-;   return sqrtl(ld);
-; }
-;
-; Tests conversion of sqrt function calls into sqrt instructions when
-; -ffast-math is in effect.
+declare double @__sqrt_finite(double) #0
+declare float @__sqrtf_finite(float) #0
+declare x86_fp80 @__sqrtl_finite(x86_fp80) #0
+declare float @llvm.sqrt.f32(float) #0
+declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #0
+declare <8 x float> @llvm.sqrt.v8f32(<8 x float>) #0
 
-; ModuleID = 'sqrt.c'
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
-target triple = "x86_64-unknown-linux-gnu"
 
-; Function Attrs: nounwind readnone uwtable
 define double @fd(double %d) #0 {
-entry:
-; CHECK: sqrtsd
-  %call = tail call double @__sqrt_finite(double %d) #2
+; CHECK-LABEL: fd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    sqrtsd %xmm0, %xmm0
+; CHECK-NEXT:    retq
+;
+; ESTIMATE-LABEL: fd:
+; ESTIMATE:       # BB#0:
+; ESTIMATE-NEXT:    vsqrtsd %xmm0, %xmm0, %xmm0
+; ESTIMATE-NEXT:    retq
+  %call = tail call double @__sqrt_finite(double %d) #1
   ret double %call
 }
 
-; Function Attrs: nounwind readnone
-declare double @__sqrt_finite(double) #1
 
-; Function Attrs: nounwind readnone uwtable
 define float @ff(float %f) #0 {
-entry:
-; CHECK: sqrtss
-  %call = tail call float @__sqrtf_finite(float %f) #2
+; CHECK-LABEL: ff:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    sqrtss %xmm0, %xmm0
+; CHECK-NEXT:    retq
+;
+; ESTIMATE-LABEL: ff:
+; ESTIMATE:       # BB#0:
+; ESTIMATE-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
+; ESTIMATE-NEXT:    vmulss {{.*}}(%rip), %xmm1, %xmm2
+; ESTIMATE-NEXT:    vmulss %xmm1, %xmm1, %xmm1
+; ESTIMATE-NEXT:    vmulss %xmm0, %xmm1, %xmm1
+; ESTIMATE-NEXT:    vaddss {{.*}}(%rip), %xmm1, %xmm1
+; ESTIMATE-NEXT:    vmulss %xmm2, %xmm1, %xmm1
+; ESTIMATE-NEXT:    vmulss %xmm1, %xmm0, %xmm1
+; ESTIMATE-NEXT:    vxorps %xmm2, %xmm2, %xmm2
+; ESTIMATE-NEXT:    vcmpeqss %xmm2, %xmm0, %xmm0
+; ESTIMATE-NEXT:    vandnps %xmm1, %xmm0, %xmm0
+; ESTIMATE-NEXT:    retq
+  %call = tail call float @__sqrtf_finite(float %f) #1
   ret float %call
 }
 
-; Function Attrs: nounwind readnone
-declare float @__sqrtf_finite(float) #1
 
-; Function Attrs: nounwind readnone uwtable
 define x86_fp80 @fld(x86_fp80 %ld) #0 {
-entry:
-; CHECK: fsqrt
-  %call = tail call x86_fp80 @__sqrtl_finite(x86_fp80 %ld) #2
+; CHECK-LABEL: fld:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    fldt {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    fsqrt
+; CHECK-NEXT:    retq
+;
+; ESTIMATE-LABEL: fld:
+; ESTIMATE:       # BB#0:
+; ESTIMATE-NEXT:    fldt {{[0-9]+}}(%rsp)
+; ESTIMATE-NEXT:    fsqrt
+; ESTIMATE-NEXT:    retq
+  %call = tail call x86_fp80 @__sqrtl_finite(x86_fp80 %ld) #1
   ret x86_fp80 %call
 }
 
-declare x86_fp80 @__sqrtl_finite(x86_fp80) #1
-
-declare float @llvm.sqrt.f32(float) #1
-declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1
-declare <8 x float> @llvm.sqrt.v8f32(<8 x float>) #1
 
-; If the target's sqrtss and divss instructions are substantially
-; slower than rsqrtss with a Newton-Raphson refinement, we should
-; generate the estimate sequence.
 
 define float @reciprocal_square_root(float %x) #0 {
+; CHECK-LABEL: reciprocal_square_root:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    sqrtss %xmm0, %xmm1
+; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:    divss %xmm1, %xmm0
+; CHECK-NEXT:    retq
+;
+; ESTIMATE-LABEL: reciprocal_square_root:
+; ESTIMATE:       # BB#0:
+; ESTIMATE-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
+; ESTIMATE-NEXT:    vmulss {{.*}}(%rip), %xmm1, %xmm2
+; ESTIMATE-NEXT:    vmulss %xmm1, %xmm1, %xmm1
+; ESTIMATE-NEXT:    vmulss %xmm0, %xmm1, %xmm0
+; ESTIMATE-NEXT:    vaddss {{.*}}(%rip), %xmm0, %xmm0
+; ESTIMATE-NEXT:    vmulss %xmm2, %xmm0, %xmm0
+; ESTIMATE-NEXT:    retq
   %sqrt = tail call float @llvm.sqrt.f32(float %x)
   %div = fdiv fast float 1.0, %sqrt
   ret float %div
-
-; CHECK-LABEL: reciprocal_square_root:
-; CHECK: sqrtss
-; CHECK-NEXT: movss
-; CHECK-NEXT: divss
-; CHECK-NEXT: retq
-; BTVER2-LABEL: reciprocal_square_root:
-; BTVER2: vrsqrtss
-; BTVER2-NEXT: vmulss
-; BTVER2-NEXT: vmulss
-; BTVER2-NEXT: vmulss
-; BTVER2-NEXT: vaddss
-; BTVER2-NEXT: vmulss
-; BTVER2-NEXT: retq
 }
 
 define <4 x float> @reciprocal_square_root_v4f32(<4 x float> %x) #0 {
+; CHECK-LABEL: reciprocal_square_root_v4f32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    sqrtps %xmm0, %xmm1
+; CHECK-NEXT:    movaps {{.*#+}} xmm0 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
+; CHECK-NEXT:    divps %xmm1, %xmm0
+; CHECK-NEXT:    retq
+;
+; ESTIMATE-LABEL: reciprocal_square_root_v4f32:
+; ESTIMATE:       # BB#0:
+; ESTIMATE-NEXT:    vrsqrtps %xmm0, %xmm1
+; ESTIMATE-NEXT:    vmulps %xmm1, %xmm1, %xmm2
+; ESTIMATE-NEXT:    vmulps %xmm0, %xmm2, %xmm0
+; ESTIMATE-NEXT:    vaddps {{.*}}(%rip), %xmm0, %xmm0
+; ESTIMATE-NEXT:    vmulps {{.*}}(%rip), %xmm1, %xmm1
+; ESTIMATE-NEXT:    vmulps %xmm1, %xmm0, %xmm0
+; ESTIMATE-NEXT:    retq
   %sqrt = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
   %div = fdiv fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
   ret <4 x float> %div
-
-; CHECK-LABEL: reciprocal_square_root_v4f32:
-; CHECK: sqrtps
-; CHECK-NEXT: movaps
-; CHECK-NEXT: divps
-; CHECK-NEXT: retq
-; BTVER2-LABEL: reciprocal_square_root_v4f32:
-; BTVER2: vrsqrtps
-; BTVER2-NEXT: vmulps
-; BTVER2-NEXT: vmulps
-; BTVER2-NEXT: vmulps
-; BTVER2-NEXT: vaddps
-; BTVER2-NEXT: vmulps
-; BTVER2-NEXT: retq
 }
 
 define <8 x float> @reciprocal_square_root_v8f32(<8 x float> %x) #0 {
+; CHECK-LABEL: reciprocal_square_root_v8f32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    sqrtps %xmm1, %xmm2
+; CHECK-NEXT:    sqrtps %xmm0, %xmm3
+; CHECK-NEXT:    movaps {{.*#+}} xmm1 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
+; CHECK-NEXT:    movaps %xmm1, %xmm0
+; CHECK-NEXT:    divps %xmm3, %xmm0
+; CHECK-NEXT:    divps %xmm2, %xmm1
+; CHECK-NEXT:    retq
+;
+; ESTIMATE-LABEL: reciprocal_square_root_v8f32:
+; ESTIMATE:       # BB#0:
+; ESTIMATE-NEXT:    vrsqrtps %ymm0, %ymm1
+; ESTIMATE-NEXT:    vmulps %ymm1, %ymm1, %ymm2
+; ESTIMATE-NEXT:    vmulps %ymm0, %ymm2, %ymm0
+; ESTIMATE-NEXT:    vaddps {{.*}}(%rip), %ymm0, %ymm0
+; ESTIMATE-NEXT:    vmulps {{.*}}(%rip), %ymm1, %ymm1
+; ESTIMATE-NEXT:    vmulps %ymm1, %ymm0, %ymm0
+; ESTIMATE-NEXT:    retq
   %sqrt = tail call <8 x float> @llvm.sqrt.v8f32(<8 x float> %x)
   %div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
   ret <8 x float> %div
-
-; CHECK-LABEL: reciprocal_square_root_v8f32:
-; CHECK: sqrtps
-; CHECK-NEXT: sqrtps
-; CHECK-NEXT: movaps
-; CHECK-NEXT: movaps
-; CHECK-NEXT: divps
-; CHECK-NEXT: divps
-; CHECK-NEXT: retq
-; BTVER2-LABEL: reciprocal_square_root_v8f32:
-; BTVER2: vrsqrtps
-; BTVER2-NEXT: vmulps
-; BTVER2-NEXT: vmulps
-; BTVER2-NEXT: vmulps
-; BTVER2-NEXT: vaddps
-; BTVER2-NEXT: vmulps
-; BTVER2-NEXT: retq
 }
 
 
-attributes #0 = { nounwind readnone uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "unsafe-fp-math"="true" "use-soft-float"="false" }
-attributes #1 = { nounwind readnone "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "unsafe-fp-math"="true" "use-soft-float"="false" }
-attributes #2 = { nounwind readnone }
+attributes #0 = { "unsafe-fp-math"="true" }
+attributes #1 = { nounwind readnone }
+
diff --git a/test/CodeGen/X86/sqrt.ll b/test/CodeGen/X86/sqrt.ll
index be7c6e867399..b22c041250fe 100644
--- a/test/CodeGen/X86/sqrt.ll
+++ b/test/CodeGen/X86/sqrt.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2                             | FileCheck %s --check-prefix=SSE2
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE2
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx                             | FileCheck %s --check-prefix=AVX
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=AVX
 
 define float @test_sqrt_f32(float %a) {
 ; SSE2-LABEL: test_sqrt_f32
diff --git a/test/CodeGen/X86/sret-implicit.ll b/test/CodeGen/X86/sret-implicit.ll
new file mode 100644
index 000000000000..2a998fc6b6c7
--- /dev/null
+++ b/test/CodeGen/X86/sret-implicit.ll
@@ -0,0 +1,34 @@
+; RUN: llc -mtriple=x86_64-apple-darwin8 < %s | FileCheck %s --check-prefix=X64
+; RUN: llc -mtriple=x86_64-pc-linux < %s | FileCheck %s --check-prefix=X64
+; RUN: llc -mtriple=i686-pc-linux < %s | FileCheck %s --check-prefix=X86
+; RUN: llc -mtriple=x86_64-apple-darwin8 -terminal-rule < %s | FileCheck %s --check-prefix=X64
+; RUN: llc -mtriple=x86_64-pc-linux -terminal-rule < %s | FileCheck %s --check-prefix=X64
+
+define void @sret_void(i32* sret %p) {
+  store i32 0, i32* %p
+  ret void
+}
+
+; X64-LABEL: sret_void
+; X64-DAG: movl $0, (%rdi)
+; X64-DAG: movq %rdi, %rax
+; X64: retq
+
+; X86-LABEL: sret_void
+; X86: movl 4(%esp), %eax
+; X86: movl $0, (%eax)
+; X86: retl
+
+define i256 @sret_demoted() {
+  ret i256 0
+}
+
+; X64-LABEL: sret_demoted
+; X64-DAG: movq $0, (%rdi)
+; X64-DAG: movq %rdi, %rax
+; X64: retq
+
+; X86-LABEL: sret_demoted
+; X86: movl 4(%esp), %eax
+; X86: movl $0, (%eax)
+; X86: retl
diff --git a/test/CodeGen/X86/sse-align-0.ll b/test/CodeGen/X86/sse-align-0.ll
index 8ffd31247702..54c89ea411a4 100644
--- a/test/CodeGen/X86/sse-align-0.ll
+++ b/test/CodeGen/X86/sse-align-0.ll
@@ -2,12 +2,12 @@
 ; CHECK-NOT:     mov
 
 define <4 x float> @foo(<4 x float>* %p, <4 x float> %x) nounwind {
-  %t = load <4 x float>* %p
+  %t = load <4 x float>, <4 x float>* %p
   %z = fmul <4 x float> %t, %x
   ret <4 x float> %z
 }
 define <2 x double> @bar(<2 x double>* %p, <2 x double> %x) nounwind {
-  %t = load <2 x double>* %p
+  %t = load <2 x double>, <2 x double>* %p
   %z = fmul <2 x double> %t, %x
   ret <2 x double> %z
 }
diff --git a/test/CodeGen/X86/sse-align-1.ll b/test/CodeGen/X86/sse-align-1.ll
index c7a5cd559120..1a6058c6114c 100644
--- a/test/CodeGen/X86/sse-align-1.ll
+++ b/test/CodeGen/X86/sse-align-1.ll
@@ -1,10 +1,10 @@
 ; RUN: llc < %s -march=x86-64 | grep movap | count 2
 
 define <4 x float> @foo(<4 x float>* %p) nounwind {
-  %t = load <4 x float>* %p
+  %t = load <4 x float>, <4 x float>* %p
   ret <4 x float> %t
 }
 define <2 x double> @bar(<2 x double>* %p) nounwind {
-  %t = load <2 x double>* %p
+  %t = load <2 x double>, <2 x double>* %p
   ret <2 x double> %t
 }
diff --git a/test/CodeGen/X86/sse-align-10.ll b/test/CodeGen/X86/sse-align-10.ll
index 0f9169712556..81bf55354cd2 100644
--- a/test/CodeGen/X86/sse-align-10.ll
+++ b/test/CodeGen/X86/sse-align-10.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86-64 | grep movups | count 1
 
 define <2 x i64> @bar(<2 x i64>* %p) nounwind {
-  %t = load <2 x i64>* %p, align 8
+  %t = load <2 x i64>, <2 x i64>* %p, align 8
   ret <2 x i64> %t
 }
diff --git a/test/CodeGen/X86/sse-align-12.ll b/test/CodeGen/X86/sse-align-12.ll
index 396da0f48956..9441cc0002fb 100644
--- a/test/CodeGen/X86/sse-align-12.ll
+++ b/test/CodeGen/X86/sse-align-12.ll
@@ -6,7 +6,7 @@ define <4 x float> @a(<4 x float>* %y) nounwind {
 ; CHECK-NEXT:    movups (%rdi), %xmm0
 ; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,2,1,0]
 ; CHECK-NEXT:    retq
-  %x = load <4 x float>* %y, align 4
+  %x = load <4 x float>, <4 x float>* %y, align 4
   %a = extractelement <4 x float> %x, i32 0
   %b = extractelement <4 x float> %x, i32 1
   %c = extractelement <4 x float> %x, i32 2
@@ -24,7 +24,7 @@ define <4 x float> @b(<4 x float>* %y, <4 x float> %z) nounwind {
 ; CHECK-NEXT:    movups (%rdi), %xmm1
 ; CHECK-NEXT:    unpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; CHECK-NEXT:    retq
-  %x = load <4 x float>* %y, align 4
+  %x = load <4 x float>, <4 x float>* %y, align 4
   %a = extractelement <4 x float> %x, i32 2
   %b = extractelement <4 x float> %x, i32 3
   %c = extractelement <4 x float> %z, i32 2
@@ -42,7 +42,7 @@ define <2 x double> @c(<2 x double>* %y) nounwind {
 ; CHECK-NEXT:    movupd (%rdi), %xmm0
 ; CHECK-NEXT:    shufpd {{.*#+}} xmm0 = xmm0[1,0]
 ; CHECK-NEXT:    retq
-  %x = load <2 x double>* %y, align 8
+  %x = load <2 x double>, <2 x double>* %y, align 8
   %a = extractelement <2 x double> %x, i32 0
   %c = extractelement <2 x double> %x, i32 1
   %p = insertelement <2 x double> undef, double %c, i32 0
@@ -56,7 +56,7 @@ define <2 x double> @d(<2 x double>* %y, <2 x double> %z) nounwind {
 ; CHECK-NEXT:    movupd (%rdi), %xmm1
 ; CHECK-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
 ; CHECK-NEXT:    retq
-  %x = load <2 x double>* %y, align 8
+  %x = load <2 x double>, <2 x double>* %y, align 8
   %a = extractelement <2 x double> %x, i32 1
   %c = extractelement <2 x double> %z, i32 1
   %p = insertelement <2 x double> undef, double %c, i32 0
diff --git a/test/CodeGen/X86/sse-align-2.ll b/test/CodeGen/X86/sse-align-2.ll
index 98e75b56e891..063cc9d2f563 100644
--- a/test/CodeGen/X86/sse-align-2.ll
+++ b/test/CodeGen/X86/sse-align-2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86-64 -mcpu=penryn | FileCheck %s
 
 define <4 x float> @foo(<4 x float>* %p, <4 x float> %x) nounwind {
-  %t = load <4 x float>* %p, align 4
+  %t = load <4 x float>, <4 x float>* %p, align 4
   %z = fmul <4 x float> %t, %x
   ret <4 x float> %z
 }
@@ -11,7 +11,7 @@ define <4 x float> @foo(<4 x float>* %p, <4 x float> %x) nounwind {
 ; CHECK: ret
 
 define <2 x double> @bar(<2 x double>* %p, <2 x double> %x) nounwind {
-  %t = load <2 x double>* %p, align 8
+  %t = load <2 x double>, <2 x double>* %p, align 8
   %z = fmul <2 x double> %t, %x
   ret <2 x double> %z
 }
diff --git a/test/CodeGen/X86/sse-align-5.ll b/test/CodeGen/X86/sse-align-5.ll
index 21cd2311b916..a64b953220d5 100644
--- a/test/CodeGen/X86/sse-align-5.ll
+++ b/test/CodeGen/X86/sse-align-5.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86-64 | grep movaps | count 1
 
 define <2 x i64> @bar(<2 x i64>* %p) nounwind {
-  %t = load <2 x i64>* %p
+  %t = load <2 x i64>, <2 x i64>* %p
   ret <2 x i64> %t
 }
diff --git a/test/CodeGen/X86/sse-align-6.ll b/test/CodeGen/X86/sse-align-6.ll
index fcea1b102a20..01f225101b96 100644
--- a/test/CodeGen/X86/sse-align-6.ll
+++ b/test/CodeGen/X86/sse-align-6.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86-64 | grep movdqu | count 1
 
 define <2 x i64> @bar(<2 x i64>* %p, <2 x i64> %x) nounwind {
-  %t = load <2 x i64>* %p, align 8
+  %t = load <2 x i64>, <2 x i64>* %p, align 8
   %z = mul <2 x i64> %t, %x
   ret <2 x i64> %z
 }
diff --git a/test/CodeGen/X86/sse-align-9.ll b/test/CodeGen/X86/sse-align-9.ll
index cb26b9535a81..182c91c69d93 100644
--- a/test/CodeGen/X86/sse-align-9.ll
+++ b/test/CodeGen/X86/sse-align-9.ll
@@ -1,10 +1,10 @@
 ; RUN: llc < %s -march=x86-64 | grep movup | count 2
 
 define <4 x float> @foo(<4 x float>* %p) nounwind {
-  %t = load <4 x float>* %p, align 4
+  %t = load <4 x float>, <4 x float>* %p, align 4
   ret <4 x float> %t
 }
 define <2 x double> @bar(<2 x double>* %p) nounwind {
-  %t = load <2 x double>* %p, align 8
+  %t = load <2 x double>, <2 x double>* %p, align 8
   ret <2 x double> %t
 }
diff --git a/test/CodeGen/X86/sse-domains.ll b/test/CodeGen/X86/sse-domains.ll
index 8cf522dd3c15..8016a246fa66 100644
--- a/test/CodeGen/X86/sse-domains.ll
+++ b/test/CodeGen/X86/sse-domains.ll
@@ -33,9 +33,9 @@ while.body:
   %x.02 = phi <4 x i32> [ %add, %while.body ], [ zeroinitializer, %entry ]
   %dec = add nsw i32 %n.addr.03, -1
   %and = and <4 x i32> %x.02, <i32 127, i32 127, i32 127, i32 127>
-  %incdec.ptr = getelementptr inbounds <4 x i32>* %p.addr.04, i64 1
+  %incdec.ptr = getelementptr inbounds <4 x i32>, <4 x i32>* %p.addr.04, i64 1
   store <4 x i32> %and, <4 x i32>* %p.addr.04, align 16
-  %0 = load <4 x i32>* %incdec.ptr, align 16
+  %0 = load <4 x i32>, <4 x i32>* %incdec.ptr, align 16
   %add = shl <4 x i32> %0, <i32 1, i32 1, i32 1, i32 1>
   %tobool = icmp eq i32 %dec, 0
   br i1 %tobool, label %while.end, label %while.body
diff --git a/test/CodeGen/X86/sse-fcopysign.ll b/test/CodeGen/X86/sse-fcopysign.ll
index 0e0e4a9a86cf..25634b5472aa 100644
--- a/test/CodeGen/X86/sse-fcopysign.ll
+++ b/test/CodeGen/X86/sse-fcopysign.ll
@@ -1,16 +1,134 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep test
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=X64
+
+;
+; Library Functions
+;
 
 define float @tst1(float %a, float %b) {
-	%tmp = tail call float @copysignf( float %b, float %a )
-	ret float %tmp
+; X32-LABEL: @tst1
+; X32:       movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X32-NEXT:  movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:  movss %xmm1, 4(%esp)
+; X32-NEXT:  movss %xmm0, (%esp)
+; X32-NEXT:  calll copysignf
+; X32-NEXT:  addl $8, %esp
+; X32-NEXT:  retl
+;
+; X64-LABEL: @tst1
+; X64:       movaps  %xmm0, %xmm2
+; X64-NEXT:  movaps  %xmm1, %xmm0
+; X64-NEXT:  movaps  %xmm2, %xmm1
+; X64-NEXT:  jmp copysignf
+  %tmp = tail call float @copysignf( float %b, float %a )
+  ret float %tmp
 }
 
 define double @tst2(double %a, float %b, float %c) {
-	%tmp1 = fadd float %b, %c
-	%tmp2 = fpext float %tmp1 to double
-	%tmp = tail call double @copysign( double %a, double %tmp2 )
-	ret double %tmp
+; X32-LABEL: @tst2
+; X32:       movsd {{.*#+}} xmm0 = mem[0],zero
+; X32-NEXT:  movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:  addss 32(%esp), %xmm1
+; X32-NEXT:  cvtss2sd %xmm1, %xmm1
+; X32-NEXT:  movsd %xmm0, (%esp)
+; X32-NEXT:  movsd %xmm1, 8(%esp)
+; X32-NEXT:  calll copysign
+; X32-NEXT:  addl $16, %esp
+; X32-NEXT:  retl
+;
+; X64-LABEL: @tst2
+; X64:       addss   %xmm2, %xmm1
+; X64-NEXT:  cvtss2sd        %xmm1, %xmm1
+; X64-NEXT:  jmp copysign
+  %tmp1 = fadd float %b, %c
+  %tmp2 = fpext float %tmp1 to double
+  %tmp = tail call double @copysign( double %a, double %tmp2 )
+  ret double %tmp
 }
 
 declare float @copysignf(float, float)
 declare double @copysign(double, double)
+
+;
+; LLVM Intrinsic
+;
+
+define float @int1(float %a, float %b) {
+; X32-LABEL: @int1
+; X32:       movss 12(%esp), %xmm0 {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X32-NEXT:  movss  8(%esp), %xmm1 {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:  andps .LCPI2_0, %xmm1
+; X32-NEXT:  andps .LCPI2_1, %xmm0
+; X32-NEXT:  orps  %xmm1, %xmm0
+; X32-NEXT:  movss %xmm0, (%esp)
+; X32-NEXT:  flds  (%esp)
+; X32-NEXT:  popl %eax
+; X32-NEXT:  retl
+;
+; X64-LABEL: @int1
+; X64:       andps .LCPI2_0(%rip), %xmm0
+; X64-NEXT:  andps .LCPI2_1(%rip), %xmm1
+; X64-NEXT:  orps  %xmm1, %xmm0
+; X64-NEXT:  retq
+  %tmp = tail call float @llvm.copysign.f32( float %b, float %a )
+  ret float %tmp
+}
+
+define double @int2(double %a, float %b, float %c) {
+; X32-LABEL: @int2
+; X32:       movsd  8(%ebp), %xmm0 {{.*#+}} xmm0 = mem[0],zero
+; X32-NEXT:  movss 16(%ebp), %xmm1 {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:  addss 20(%ebp), %xmm1
+; X32-NEXT:  andpd .LCPI3_0, %xmm0
+; X32-NEXT:  cvtss2sd %xmm1, %xmm1
+; X32-NEXT:  andpd .LCPI3_1, %xmm1
+; X32-NEXT:  orpd  %xmm0, %xmm1
+; X32-NEXT:  movsd %xmm1, (%esp)
+; X32-NEXT:  fldl  (%esp)
+; X32-NEXT:  movl %ebp, %esp
+; X32-NEXT:  popl %ebp
+; X32-NEXT:  retl
+;
+; X64-LABEL: @int2
+; X64:       addss %xmm2, %xmm1
+; X64-NEXT:  andpd .LCPI3_0(%rip), %xmm0
+; X64-NEXT:  cvtss2sd %xmm1, %xmm1
+; X64-NEXT:  andpd .LCPI3_1(%rip), %xmm1
+; X64-NEXT:  orpd %xmm1, %xmm0
+; X64-NEXT:  retq
+  %tmp1 = fadd float %b, %c
+  %tmp2 = fpext float %tmp1 to double
+  %tmp = tail call double @llvm.copysign.f64( double %a, double %tmp2 )
+  ret double %tmp
+}
+
+define float @cst1() {
+; X32-LABEL: @cst1
+; X32:       fld1
+; X32-NEXT:  fchs
+; X32-NEXT:  retl
+;
+; X64-LABEL: @cst1
+; X64:       movss .LCPI4_0(%rip), %xmm0 {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X64-NEXT:  retq
+  %tmp = tail call float @llvm.copysign.f32( float 1.0, float -2.0 )
+  ret float %tmp
+}
+
+define double @cst2() {
+; X32-LABEL: @cst2
+; X32:       fldz
+; X32-NEXT:  fchs
+; X32-NEXT:  retl
+;
+; X64-LABEL: @cst2
+; X64:       movsd .LCPI5_0(%rip), %xmm0 {{.*#+}} xmm0 = mem[0],zero
+; X64-NEXT:  retq
+  %tmp1 = fadd float -1.0, -1.0
+  %tmp2 = fpext float %tmp1 to double
+  %tmp = tail call double @llvm.copysign.f64( double 0.0, double %tmp2 )
+  ret double %tmp
+}
+
+declare float     @llvm.copysign.f32(float  %Mag, float  %Sgn)
+declare double    @llvm.copysign.f64(double %Mag, double %Sgn)
diff --git a/test/CodeGen/X86/sse-intel-ocl.ll b/test/CodeGen/X86/sse-intel-ocl.ll
index 188505072f05..b96ecc575021 100644
--- a/test/CodeGen/X86/sse-intel-ocl.ll
+++ b/test/CodeGen/X86/sse-intel-ocl.ll
@@ -36,7 +36,7 @@ define <16 x float> @testf16_inp(<16 x float> %a, <16 x float> %b) nounwind {
   %y = alloca <16 x float>, align 16
   %x = fadd <16 x float> %a, %b
   %1 = call intel_ocl_bicc <16 x float> @func_float16_ptr(<16 x float> %x, <16 x float>* %y) 
-  %2 = load <16 x float>* %y, align 16
+  %2 = load <16 x float>, <16 x float>* %y, align 16
   %3 = fadd <16 x float> %2, %1
   ret <16 x float> %3
 }
@@ -63,7 +63,7 @@ define <16 x float> @testf16_regs(<16 x float> %a, <16 x float> %b) nounwind {
   %y = alloca <16 x float>, align 16
   %x = fadd <16 x float> %a, %b
   %1 = call intel_ocl_bicc <16 x float> @func_float16_ptr(<16 x float> %x, <16 x float>* %y) 
-  %2 = load <16 x float>* %y, align 16
+  %2 = load <16 x float>, <16 x float>* %y, align 16
   %3 = fadd <16 x float> %1, %b
   %4 = fadd <16 x float> %2, %3
   ret <16 x float> %4
diff --git a/test/CodeGen/X86/sse-intrinsics-x86.ll b/test/CodeGen/X86/sse-intrinsics-x86.ll
index 65d44bfb5ba8..0857189be734 100644
--- a/test/CodeGen/X86/sse-intrinsics-x86.ll
+++ b/test/CodeGen/X86/sse-intrinsics-x86.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+sse | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=knl | FileCheck %s
 
 define <4 x float> @test_x86_sse_add_ss(<4 x float> %a0, <4 x float> %a1) {
   ; CHECK: addss
diff --git a/test/CodeGen/X86/sse-load-ret.ll b/test/CodeGen/X86/sse-load-ret.ll
index 1ebcb1a6fa64..8da45a786e7c 100644
--- a/test/CodeGen/X86/sse-load-ret.ll
+++ b/test/CodeGen/X86/sse-load-ret.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=x86 -mcpu=yonah | not grep xmm
 
 define double @test1(double* %P) {
-        %X = load double* %P            ; <double> [#uses=1]
+        %X = load double, double* %P            ; <double> [#uses=1]
         ret double %X
 }
 
diff --git a/test/CodeGen/X86/sse-minmax.ll b/test/CodeGen/X86/sse-minmax.ll
index 4dcb54ca4b0b..e4d0373299fb 100644
--- a/test/CodeGen/X86/sse-minmax.ll
+++ b/test/CodeGen/X86/sse-minmax.ll
@@ -805,7 +805,7 @@ define double @ule_inverse_y(double %x) nounwind {
 ; CHECK-LABEL: clampTo3k_a:
 ; CHECK-NEXT: movsd {{[^,]*}}, %xmm1
 ; CHECK-NEXT: minsd %xmm0, %xmm1
-; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: movapd %xmm1, %xmm0
 ; CHECK-NEXT: ret
 ; UNSAFE-LABEL: clampTo3k_a:
 ; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
@@ -813,7 +813,7 @@ define double @ule_inverse_y(double %x) nounwind {
 ; FINITE-LABEL: clampTo3k_a:
 ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
 ; FINITE-NEXT: minsd %xmm0, %xmm1
-; FINITE-NEXT: movaps %xmm1, %xmm0
+; FINITE-NEXT: movapd %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @clampTo3k_a(double %x) nounwind readnone {
 entry:
@@ -831,7 +831,7 @@ entry:
 ; FINITE-LABEL: clampTo3k_b:
 ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
 ; FINITE-NEXT: minsd %xmm0, %xmm1
-; FINITE-NEXT: movaps %xmm1, %xmm0
+; FINITE-NEXT: movapd %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @clampTo3k_b(double %x) nounwind readnone {
 entry:
@@ -843,7 +843,7 @@ entry:
 ; CHECK-LABEL: clampTo3k_c:
 ; CHECK-NEXT: movsd {{[^,]*}}, %xmm1
 ; CHECK-NEXT: maxsd %xmm0, %xmm1
-; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: movapd %xmm1, %xmm0
 ; CHECK-NEXT: ret
 ; UNSAFE-LABEL: clampTo3k_c:
 ; UNSAFE-NEXT: maxsd {{[^,]*}}, %xmm0
@@ -851,7 +851,7 @@ entry:
 ; FINITE-LABEL: clampTo3k_c:
 ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
 ; FINITE-NEXT: maxsd %xmm0, %xmm1
-; FINITE-NEXT: movaps %xmm1, %xmm0
+; FINITE-NEXT: movapd %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @clampTo3k_c(double %x) nounwind readnone {
 entry:
@@ -869,7 +869,7 @@ entry:
 ; FINITE-LABEL: clampTo3k_d:
 ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
 ; FINITE-NEXT: maxsd %xmm0, %xmm1
-; FINITE-NEXT: movaps %xmm1, %xmm0
+; FINITE-NEXT: movapd %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @clampTo3k_d(double %x) nounwind readnone {
 entry:
@@ -881,7 +881,7 @@ entry:
 ; CHECK-LABEL: clampTo3k_e:
 ; CHECK-NEXT: movsd {{[^,]*}}, %xmm1
 ; CHECK-NEXT: maxsd %xmm0, %xmm1
-; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: movapd %xmm1, %xmm0
 ; CHECK-NEXT: ret
 ; UNSAFE-LABEL: clampTo3k_e:
 ; UNSAFE-NEXT: maxsd {{[^,]*}}, %xmm0
@@ -889,7 +889,7 @@ entry:
 ; FINITE-LABEL: clampTo3k_e:
 ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
 ; FINITE-NEXT: maxsd %xmm0, %xmm1
-; FINITE-NEXT: movaps %xmm1, %xmm0
+; FINITE-NEXT: movapd %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @clampTo3k_e(double %x) nounwind readnone {
 entry:
@@ -907,7 +907,7 @@ entry:
 ; FINITE-LABEL: clampTo3k_f:
 ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
 ; FINITE-NEXT: maxsd %xmm0, %xmm1
-; FINITE-NEXT: movaps %xmm1, %xmm0
+; FINITE-NEXT: movapd %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @clampTo3k_f(double %x) nounwind readnone {
 entry:
@@ -919,7 +919,7 @@ entry:
 ; CHECK-LABEL: clampTo3k_g:
 ; CHECK-NEXT: movsd {{[^,]*}}, %xmm1
 ; CHECK-NEXT: minsd %xmm0, %xmm1
-; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: movapd %xmm1, %xmm0
 ; CHECK-NEXT: ret
 ; UNSAFE-LABEL: clampTo3k_g:
 ; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
@@ -927,7 +927,7 @@ entry:
 ; FINITE-LABEL: clampTo3k_g:
 ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
 ; FINITE-NEXT: minsd %xmm0, %xmm1
-; FINITE-NEXT: movaps %xmm1, %xmm0
+; FINITE-NEXT: movapd %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @clampTo3k_g(double %x) nounwind readnone {
 entry:
@@ -945,7 +945,7 @@ entry:
 ; FINITE-LABEL: clampTo3k_h:
 ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
 ; FINITE-NEXT: minsd %xmm0, %xmm1
-; FINITE-NEXT: movaps %xmm1, %xmm0
+; FINITE-NEXT: movapd %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @clampTo3k_h(double %x) nounwind readnone {
 entry:
diff --git a/test/CodeGen/X86/sse-scalar-fp-arith-unary.ll b/test/CodeGen/X86/sse-scalar-fp-arith-unary.ll
new file mode 100644
index 000000000000..fab4f90279e8
--- /dev/null
+++ b/test/CodeGen/X86/sse-scalar-fp-arith-unary.ll
@@ -0,0 +1,73 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=sse2 < %s   | FileCheck --check-prefix=SSE %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=sse4.1 < %s | FileCheck --check-prefix=SSE %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx < %s    | FileCheck --check-prefix=AVX %s
+
+; PR21507 - https://llvm.org/bugs/show_bug.cgi?id=21507
+; Each function should be a single math op; no extra moves.
+
+
+define <4 x float> @recip(<4 x float> %x) {
+; SSE-LABEL: recip:
+; SSE:       # BB#0:
+; SSE-NEXT:    rcpss %xmm0, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: recip:
+; AVX:       # BB#0:
+; AVX-NEXT:    vrcpss %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %y = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %x)
+  %shuf = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+  ret <4 x float> %shuf
+}
+
+define <4 x float> @recip_square_root(<4 x float> %x) {
+; SSE-LABEL: recip_square_root:
+; SSE:       # BB#0:
+; SSE-NEXT:    rsqrtss %xmm0, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: recip_square_root:
+; AVX:       # BB#0:
+; AVX-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %y = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %x)
+  %shuf = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+  ret <4 x float> %shuf
+}
+
+define <4 x float> @square_root(<4 x float> %x) {
+; SSE-LABEL: square_root:
+; SSE:       # BB#0:
+; SSE-NEXT:    sqrtss %xmm0, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: square_root:
+; AVX:       # BB#0:
+; AVX-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %y = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %x)
+  %shuf = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+  ret <4 x float> %shuf
+}
+
+define <2 x double> @square_root_double(<2 x double> %x) {
+; SSE-LABEL: square_root_double:
+; SSE:       # BB#0:
+; SSE-NEXT:    sqrtsd %xmm0, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: square_root_double:
+; AVX:       # BB#0:
+; AVX-NEXT:    vsqrtsd %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %y = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %x)
+  %shuf = shufflevector <2 x double> %y, <2 x double> %x, <2 x i32> <i32 0, i32 3>
+  ret <2 x double> %shuf
+}
+
+declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>)
+declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>)
+declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>)
+declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>)
+
diff --git a/test/CodeGen/X86/sse-scalar-fp-arith.ll b/test/CodeGen/X86/sse-scalar-fp-arith.ll
index b122ef67544c..7162d2715bce 100644
--- a/test/CodeGen/X86/sse-scalar-fp-arith.ll
+++ b/test/CodeGen/X86/sse-scalar-fp-arith.ll
@@ -76,6 +76,31 @@ define <4 x float> @test_div_ss(<4 x float> %a, <4 x float> %b) {
   ret <4 x float> %3
 }
 
+define <4 x float> @test_sqrt_ss(<4 x float> %a) {
+; SSE2-LABEL: test_sqrt_ss:
+; SSE2:       # BB#0:
+; SSE2-NEXT:   sqrtss %xmm0, %xmm1
+; SSE2-NEXT:   movss %xmm1, %xmm0
+; SSE2-NEXT:   retq
+;
+; SSE41-LABEL: test_sqrt_ss:
+; SSE41:       # BB#0:
+; SSE41-NEXT:  sqrtss %xmm0, %xmm1
+; SSE41-NEXT:  blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; SSE41-NEXT:  retq
+;
+; AVX-LABEL: test_sqrt_ss:
+; AVX:       # BB#0:
+; AVX-NEXT:    vsqrtss %xmm0, %xmm0, %xmm1
+; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; AVX-NEXT:    retq
+  %1 = extractelement <4 x float> %a, i32 0
+  %2 = call float @llvm.sqrt.f32(float %1)
+  %3 = insertelement <4 x float> %a, float %2, i32 0
+  ret <4 x float> %3
+}
+declare float @llvm.sqrt.f32(float)
+
 define <2 x double> @test_add_sd(<2 x double> %a, <2 x double> %b) {
 ; SSE-LABEL: test_add_sd:
 ; SSE:       # BB#0:
@@ -144,6 +169,25 @@ define <2 x double> @test_div_sd(<2 x double> %a, <2 x double> %b) {
   ret <2 x double> %3
 }
 
+define <2 x double> @test_sqrt_sd(<2 x double> %a) {
+; SSE-LABEL: test_sqrt_sd:
+; SSE:       # BB#0:
+; SSE-NEXT:    sqrtsd %xmm0, %xmm1
+; SSE-NEXT:    movsd %xmm1, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: test_sqrt_sd:
+; AVX:       # BB#0:
+; AVX-NEXT:    vsqrtsd %xmm0, %xmm0, %xmm1
+; AVX-NEXT:    vmovsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %1 = extractelement <2 x double> %a, i32 0
+  %2 = call double @llvm.sqrt.f64(double %1)
+  %3 = insertelement <2 x double> %a, double %2, i32 0
+  ret <2 x double> %3
+}
+declare double @llvm.sqrt.f64(double)
+
 define <4 x float> @test2_add_ss(<4 x float> %a, <4 x float> %b) {
 ; SSE-LABEL: test2_add_ss:
 ; SSE:       # BB#0:
@@ -220,7 +264,7 @@ define <2 x double> @test2_add_sd(<2 x double> %a, <2 x double> %b) {
 ; SSE-LABEL: test2_add_sd:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    addsd %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    movapd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test2_add_sd:
@@ -238,7 +282,7 @@ define <2 x double> @test2_sub_sd(<2 x double> %a, <2 x double> %b) {
 ; SSE-LABEL: test2_sub_sd:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    subsd %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    movapd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test2_sub_sd:
@@ -256,7 +300,7 @@ define <2 x double> @test2_mul_sd(<2 x double> %a, <2 x double> %b) {
 ; SSE-LABEL: test2_mul_sd:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    mulsd %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    movapd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test2_mul_sd:
@@ -274,7 +318,7 @@ define <2 x double> @test2_div_sd(<2 x double> %a, <2 x double> %b) {
 ; SSE-LABEL: test2_div_sd:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    divsd %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    movapd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test2_div_sd:
@@ -370,8 +414,155 @@ define <4 x float> @test_multiple_div_ss(<4 x float> %a, <4 x float> %b) {
   ret <4 x float> %3
 }
 
+; With SSE4.1 or greater, the shuffles in the following tests may
+; be lowered to X86Blendi nodes.
+
+define <4 x float> @blend_add_ss(<4 x float> %a, float %b) {
+; SSE-LABEL: blend_add_ss:
+; SSE:       # BB#0:
+; SSE-NEXT:    addss %xmm1, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: blend_add_ss:
+; AVX:       # BB#0:
+; AVX-NEXT:    vaddss %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+
+  %ext = extractelement <4 x float> %a, i32 0
+  %op = fadd float %b, %ext
+  %ins = insertelement <4 x float> undef, float %op, i32 0
+  %shuf = shufflevector <4 x float> %ins, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+  ret <4 x float> %shuf
+}
+
+define <4 x float> @blend_sub_ss(<4 x float> %a, float %b) {
+; SSE-LABEL: blend_sub_ss:
+; SSE:       # BB#0:
+; SSE-NEXT:    subss %xmm1, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: blend_sub_ss:
+; AVX:       # BB#0:
+; AVX-NEXT:    vsubss %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+
+  %ext = extractelement <4 x float> %a, i32 0
+  %op = fsub float %ext, %b
+  %ins = insertelement <4 x float> undef, float %op, i32 0
+  %shuf = shufflevector <4 x float> %ins, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+  ret <4 x float> %shuf
+}
+
+define <4 x float> @blend_mul_ss(<4 x float> %a, float %b) {
+; SSE-LABEL: blend_mul_ss:
+; SSE:       # BB#0:
+; SSE-NEXT:    mulss %xmm1, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: blend_mul_ss:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmulss %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+
+  %ext = extractelement <4 x float> %a, i32 0
+  %op = fmul float %b, %ext
+  %ins = insertelement <4 x float> undef, float %op, i32 0
+  %shuf = shufflevector <4 x float> %ins, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+  ret <4 x float> %shuf
+}
+
+define <4 x float> @blend_div_ss(<4 x float> %a, float %b) {
+; SSE-LABEL: blend_div_ss:
+; SSE:       # BB#0:
+; SSE-NEXT:    divss %xmm1, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: blend_div_ss:
+; AVX:       # BB#0:
+; AVX-NEXT:    vdivss %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+
+  %ext = extractelement <4 x float> %a, i32 0
+  %op = fdiv float %ext, %b
+  %ins = insertelement <4 x float> undef, float %op, i32 0
+  %shuf = shufflevector <4 x float> %ins, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+  ret <4 x float> %shuf
+}
+
+define <2 x double> @blend_add_sd(<2 x double> %a, double %b) {
+; SSE-LABEL: blend_add_sd:
+; SSE:       # BB#0:
+; SSE-NEXT:    addsd %xmm1, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: blend_add_sd:
+; AVX:       # BB#0:
+; AVX-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+
+  %ext = extractelement <2 x double> %a, i32 0
+  %op = fadd double %b, %ext
+  %ins = insertelement <2 x double> undef, double %op, i32 0
+  %shuf = shufflevector <2 x double> %ins, <2 x double> %a, <2 x i32> <i32 0, i32 3>
+  ret <2 x double> %shuf
+}
+
+define <2 x double> @blend_sub_sd(<2 x double> %a, double %b) {
+; SSE-LABEL: blend_sub_sd:
+; SSE:       # BB#0:
+; SSE-NEXT:    subsd %xmm1, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: blend_sub_sd:
+; AVX:       # BB#0:
+; AVX-NEXT:    vsubsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+
+  %ext = extractelement <2 x double> %a, i32 0
+  %op = fsub double %ext, %b
+  %ins = insertelement <2 x double> undef, double %op, i32 0
+  %shuf = shufflevector <2 x double> %ins, <2 x double> %a, <2 x i32> <i32 0, i32 3>
+  ret <2 x double> %shuf
+}
+
+define <2 x double> @blend_mul_sd(<2 x double> %a, double %b) {
+; SSE-LABEL: blend_mul_sd:
+; SSE:       # BB#0:
+; SSE-NEXT:    mulsd %xmm1, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: blend_mul_sd:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmulsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+
+  %ext = extractelement <2 x double> %a, i32 0
+  %op = fmul double %b, %ext
+  %ins = insertelement <2 x double> undef, double %op, i32 0
+  %shuf = shufflevector <2 x double> %ins, <2 x double> %a, <2 x i32> <i32 0, i32 3>
+  ret <2 x double> %shuf
+}
+
+define <2 x double> @blend_div_sd(<2 x double> %a, double %b) {
+; SSE-LABEL: blend_div_sd:
+; SSE:       # BB#0:
+; SSE-NEXT:    divsd %xmm1, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: blend_div_sd:
+; AVX:       # BB#0:
+; AVX-NEXT:    vdivsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+
+  %ext = extractelement <2 x double> %a, i32 0
+  %op = fdiv double %ext, %b
+  %ins = insertelement <2 x double> undef, double %op, i32 0
+  %shuf = shufflevector <2 x double> %ins, <2 x double> %a, <2 x i32> <i32 0, i32 3>
+  ret <2 x double> %shuf
+}
+
 ; Ensure that the backend selects SSE/AVX scalar fp instructions
-; from a packed fp instrution plus a vector insert.
+; from a packed fp instruction plus a vector insert.
 
 define <4 x float> @insert_test_add_ss(<4 x float> %a, <4 x float> %b) {
 ; SSE-LABEL: insert_test_add_ss:
@@ -561,7 +752,7 @@ define <2 x double> @insert_test2_add_sd(<2 x double> %a, <2 x double> %b) {
 ; SSE-LABEL: insert_test2_add_sd:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    addsd %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    movapd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_test2_add_sd:
@@ -577,7 +768,7 @@ define <2 x double> @insert_test2_sub_sd(<2 x double> %a, <2 x double> %b) {
 ; SSE-LABEL: insert_test2_sub_sd:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    subsd %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    movapd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_test2_sub_sd:
@@ -593,7 +784,7 @@ define <2 x double> @insert_test2_mul_sd(<2 x double> %a, <2 x double> %b) {
 ; SSE-LABEL: insert_test2_mul_sd:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    mulsd %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    movapd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_test2_mul_sd:
@@ -609,7 +800,7 @@ define <2 x double> @insert_test2_div_sd(<2 x double> %a, <2 x double> %b) {
 ; SSE-LABEL: insert_test2_div_sd:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    divsd %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    movapd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_test2_div_sd:
@@ -809,7 +1000,7 @@ define <2 x double> @insert_test4_add_sd(<2 x double> %a, <2 x double> %b) {
 ; SSE-LABEL: insert_test4_add_sd:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    addsd %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    movapd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_test4_add_sd:
@@ -825,7 +1016,7 @@ define <2 x double> @insert_test4_sub_sd(<2 x double> %a, <2 x double> %b) {
 ; SSE-LABEL: insert_test4_sub_sd:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    subsd %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    movapd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_test4_sub_sd:
@@ -841,7 +1032,7 @@ define <2 x double> @insert_test4_mul_sd(<2 x double> %a, <2 x double> %b) {
 ; SSE-LABEL: insert_test4_mul_sd:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    mulsd %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    movapd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_test4_mul_sd:
@@ -857,7 +1048,7 @@ define <2 x double> @insert_test4_div_sd(<2 x double> %a, <2 x double> %b) {
 ; SSE-LABEL: insert_test4_div_sd:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    divsd %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    movapd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_test4_div_sd:
diff --git a/test/CodeGen/X86/sse-unaligned-mem-feature.ll b/test/CodeGen/X86/sse-unaligned-mem-feature.ll
index 15f91ee04eaf..1c61a515f383 100644
--- a/test/CodeGen/X86/sse-unaligned-mem-feature.ll
+++ b/test/CodeGen/X86/sse-unaligned-mem-feature.ll
@@ -4,10 +4,10 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-unknown-linux-gnu"
 
 define <4 x float> @foo(<4 x float>* %P, <4 x float> %In) nounwind {
-	%A = load <4 x float>* %P, align 4
+	%A = load <4 x float>, <4 x float>* %P, align 4
 	%B = fadd <4 x float> %A, %In
 	ret <4 x float> %B
 
 ; CHECK-LABEL: @foo
-; CHECK:       addps (
+; CHECK:       addps (%eax), %xmm0
 }
diff --git a/test/CodeGen/X86/sse-varargs.ll b/test/CodeGen/X86/sse-varargs.ll
index da38f0e148f6..7c3c78113def 100644
--- a/test/CodeGen/X86/sse-varargs.ll
+++ b/test/CodeGen/X86/sse-varargs.ll
@@ -2,7 +2,7 @@
 
 define i32 @t() nounwind  {
 entry:
-	tail call void (i32, ...)* @foo( i32 1, <4 x i32> < i32 10, i32 11, i32 12, i32 13 > ) nounwind 
+	tail call void (i32, ...) @foo( i32 1, <4 x i32> < i32 10, i32 11, i32 12, i32 13 > ) nounwind 
 	ret i32 0
 }
 
diff --git a/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll b/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
new file mode 100644
index 000000000000..b0412b96bdb2
--- /dev/null
+++ b/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=pentium4 -mattr=sse2 | FileCheck %s
+
+define <2 x i64> @test_x86_sse2_psll_dq_bs(<2 x i64> %a0) {
+  ; CHECK: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8]
+  %res = call <2 x i64> @llvm.x86.sse2.psll.dq.bs(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
+  ret <2 x i64> %res
+}
+declare <2 x i64> @llvm.x86.sse2.psll.dq.bs(<2 x i64>, i32) nounwind readnone
+
+
+define <2 x i64> @test_x86_sse2_psrl_dq_bs(<2 x i64> %a0) {
+  ; CHECK: psrldq {{.*#+}} xmm0 = xmm0[7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero
+  %res = call <2 x i64> @llvm.x86.sse2.psrl.dq.bs(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
+  ret <2 x i64> %res
+}
+declare <2 x i64> @llvm.x86.sse2.psrl.dq.bs(<2 x i64>, i32) nounwind readnone
+
+define <2 x i64> @test_x86_sse2_psll_dq(<2 x i64> %a0) {
+  ; CHECK: pslldq {{.*#+}} xmm0 = zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
+  %res = call <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1]
+  ret <2 x i64> %res
+}
+declare <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64>, i32) nounwind readnone
+
+
+define <2 x i64> @test_x86_sse2_psrl_dq(<2 x i64> %a0) {
+  ; CHECK: psrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero
+  %res = call <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1]
+  ret <2 x i64> %res
+}
+declare <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64>, i32) nounwind readnone
diff --git a/test/CodeGen/X86/sse2-intrinsics-x86.ll b/test/CodeGen/X86/sse2-intrinsics-x86.ll
index ddb04211ec7b..53132a167fb8 100644
--- a/test/CodeGen/X86/sse2-intrinsics-x86.ll
+++ b/test/CodeGen/X86/sse2-intrinsics-x86.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+sse2 | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
+; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=knl | FileCheck %s
 
 define <2 x double> @test_x86_sse2_add_sd(<2 x double> %a0, <2 x double> %a1) {
   ; CHECK: addsd
@@ -142,7 +143,7 @@ declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone
 
 define <4 x float> @test_x86_sse2_cvtsd2ss(<4 x float> %a0, <2 x double> %a1) {
   ; CHECK: cvtsd2ss 
-  ; CHECK-NOT: cvtsd2ss %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm{{[0-9]+}} 
+  ; SSE-NOT: cvtsd2ss %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm{{[0-9]+}} 
   %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
@@ -410,22 +411,6 @@ define <4 x i32> @test_x86_sse2_psll_d(<4 x i32> %a0, <4 x i32> %a1) {
 declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone
 
 
-define <2 x i64> @test_x86_sse2_psll_dq(<2 x i64> %a0) {
-  ; CHECK: pslldq {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
-  %res = call <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
-  ret <2 x i64> %res
-}
-declare <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64>, i32) nounwind readnone
-
-
-define <2 x i64> @test_x86_sse2_psll_dq_bs(<2 x i64> %a0) {
-  ; CHECK: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8]
-  %res = call <2 x i64> @llvm.x86.sse2.psll.dq.bs(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
-  ret <2 x i64> %res
-}
-declare <2 x i64> @llvm.x86.sse2.psll.dq.bs(<2 x i64>, i32) nounwind readnone
-
-
 define <2 x i64> @test_x86_sse2_psll_q(<2 x i64> %a0, <2 x i64> %a1) {
   ; CHECK: psllq
   %res = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
@@ -506,22 +491,6 @@ define <4 x i32> @test_x86_sse2_psrl_d(<4 x i32> %a0, <4 x i32> %a1) {
 declare <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32>, <4 x i32>) nounwind readnone
 
 
-define <2 x i64> @test_x86_sse2_psrl_dq(<2 x i64> %a0) {
-  ; CHECK: psrldq {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
-  %res = call <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
-  ret <2 x i64> %res
-}
-declare <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64>, i32) nounwind readnone
-
-
-define <2 x i64> @test_x86_sse2_psrl_dq_bs(<2 x i64> %a0) {
-  ; CHECK: psrldq {{.*#+}} xmm0 = xmm0[7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero
-  %res = call <2 x i64> @llvm.x86.sse2.psrl.dq.bs(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
-  ret <2 x i64> %res
-}
-declare <2 x i64> @llvm.x86.sse2.psrl.dq.bs(<2 x i64>, i32) nounwind readnone
-
-
 define <2 x i64> @test_x86_sse2_psrl_q(<2 x i64> %a0, <2 x i64> %a1) {
   ; CHECK: psrlq
   %res = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
@@ -613,7 +582,7 @@ declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
 define void @test_x86_sse2_storel_dq(i8* %a0, <4 x i32> %a1) {
   ; CHECK: test_x86_sse2_storel_dq
   ; CHECK: movl
-  ; CHECK: movq
+  ; CHECK: movlps
   call void @llvm.x86.sse2.storel.dq(i8* %a0, <4 x i32> %a1)
   ret void
 }
diff --git a/test/CodeGen/X86/sse2.ll b/test/CodeGen/X86/sse2.ll
index b7db6cb56ef2..d3ee3c6f0454 100644
--- a/test/CodeGen/X86/sse2.ll
+++ b/test/CodeGen/X86/sse2.ll
@@ -10,7 +10,7 @@ define void @test1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind  {
 ; CHECK-NEXT:    movlpd {{[0-9]+}}(%esp), %xmm0
 ; CHECK-NEXT:    movapd %xmm0, (%eax)
 ; CHECK-NEXT:    retl
-	%tmp3 = load <2 x double>* %A, align 16
+	%tmp3 = load <2 x double>, <2 x double>* %A, align 16
 	%tmp7 = insertelement <2 x double> undef, double %B, i32 0
 	%tmp9 = shufflevector <2 x double> %tmp3, <2 x double> %tmp7, <2 x i32> < i32 2, i32 1 >
 	store <2 x double> %tmp9, <2 x double>* %r, align 16
@@ -26,7 +26,7 @@ define void @test2(<2 x double>* %r, <2 x double>* %A, double %B) nounwind  {
 ; CHECK-NEXT:    movhpd {{[0-9]+}}(%esp), %xmm0
 ; CHECK-NEXT:    movapd %xmm0, (%eax)
 ; CHECK-NEXT:    retl
-	%tmp3 = load <2 x double>* %A, align 16
+	%tmp3 = load <2 x double>, <2 x double>* %A, align 16
 	%tmp7 = insertelement <2 x double> undef, double %B, i32 0
 	%tmp9 = shufflevector <2 x double> %tmp3, <2 x double> %tmp7, <2 x i32> < i32 0, i32 2 >
 	store <2 x double> %tmp9, <2 x double>* %r, align 16
@@ -44,8 +44,8 @@ define void @test3(<4 x float>* %res, <4 x float>* %A, <4 x float>* %B) nounwind
 ; CHECK-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
 ; CHECK-NEXT:    movaps %xmm0, (%eax)
 ; CHECK-NEXT:    retl
-	%tmp = load <4 x float>* %B		; <<4 x float>> [#uses=2]
-	%tmp3 = load <4 x float>* %A		; <<4 x float>> [#uses=2]
+	%tmp = load <4 x float>, <4 x float>* %B		; <<4 x float>> [#uses=2]
+	%tmp3 = load <4 x float>, <4 x float>* %A		; <<4 x float>> [#uses=2]
 	%tmp.upgrd.1 = extractelement <4 x float> %tmp3, i32 0		; <float> [#uses=1]
 	%tmp7 = extractelement <4 x float> %tmp, i32 0		; <float> [#uses=1]
 	%tmp8 = extractelement <4 x float> %tmp3, i32 1		; <float> [#uses=1]
@@ -75,14 +75,14 @@ define <4 x i32> @test5(i8** %ptr) nounwind {
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl (%eax), %eax
-; CHECK-NEXT:    movss (%eax), %xmm1
+; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    pxor %xmm0, %xmm0
 ; CHECK-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
 ; CHECK-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; CHECK-NEXT:    retl
-	%tmp = load i8** %ptr		; <i8*> [#uses=1]
+	%tmp = load i8*, i8** %ptr		; <i8*> [#uses=1]
 	%tmp.upgrd.1 = bitcast i8* %tmp to float*		; <float*> [#uses=1]
-	%tmp.upgrd.2 = load float* %tmp.upgrd.1		; <float> [#uses=1]
+	%tmp.upgrd.2 = load float, float* %tmp.upgrd.1		; <float> [#uses=1]
 	%tmp.upgrd.3 = insertelement <4 x float> undef, float %tmp.upgrd.2, i32 0		; <<4 x float>> [#uses=1]
 	%tmp9 = insertelement <4 x float> %tmp.upgrd.3, float 0.000000e+00, i32 1		; <<4 x float>> [#uses=1]
 	%tmp10 = insertelement <4 x float> %tmp9, float 0.000000e+00, i32 2		; <<4 x float>> [#uses=1]
@@ -103,7 +103,7 @@ define void @test6(<4 x float>* %res, <4 x float>* %A) nounwind {
 ; CHECK-NEXT:    movaps (%ecx), %xmm0
 ; CHECK-NEXT:    movaps %xmm0, (%eax)
 ; CHECK-NEXT:    retl
-  %tmp1 = load <4 x float>* %A            ; <<4 x float>> [#uses=1]
+  %tmp1 = load <4 x float>, <4 x float>* %A            ; <<4 x float>> [#uses=1]
   %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >          ; <<4 x float>> [#uses=1]
   store <4 x float> %tmp2, <4 x float>* %res
   ret void
@@ -129,10 +129,10 @@ define <2 x i64> @test8() nounwind {
 ; CHECK-NEXT:    movl L_x$non_lazy_ptr, %eax
 ; CHECK-NEXT:    movups (%eax), %xmm0
 ; CHECK-NEXT:    retl
-	%tmp = load i32* getelementptr ([4 x i32]* @x, i32 0, i32 0)		; <i32> [#uses=1]
-	%tmp3 = load i32* getelementptr ([4 x i32]* @x, i32 0, i32 1)		; <i32> [#uses=1]
-	%tmp5 = load i32* getelementptr ([4 x i32]* @x, i32 0, i32 2)		; <i32> [#uses=1]
-	%tmp7 = load i32* getelementptr ([4 x i32]* @x, i32 0, i32 3)		; <i32> [#uses=1]
+	%tmp = load i32, i32* getelementptr ([4 x i32], [4 x i32]* @x, i32 0, i32 0)		; <i32> [#uses=1]
+	%tmp3 = load i32, i32* getelementptr ([4 x i32], [4 x i32]* @x, i32 0, i32 1)		; <i32> [#uses=1]
+	%tmp5 = load i32, i32* getelementptr ([4 x i32], [4 x i32]* @x, i32 0, i32 2)		; <i32> [#uses=1]
+	%tmp7 = load i32, i32* getelementptr ([4 x i32], [4 x i32]* @x, i32 0, i32 3)		; <i32> [#uses=1]
 	%tmp.upgrd.1 = insertelement <4 x i32> undef, i32 %tmp, i32 0		; <<4 x i32>> [#uses=1]
 	%tmp13 = insertelement <4 x i32> %tmp.upgrd.1, i32 %tmp3, i32 1		; <<4 x i32>> [#uses=1]
 	%tmp14 = insertelement <4 x i32> %tmp13, i32 %tmp5, i32 2		; <<4 x i32>> [#uses=1]
@@ -179,14 +179,14 @@ define void @test12() nounwind {
 ; CHECK-LABEL: test12:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    movapd 0, %xmm0
-; CHECK-NEXT:    movaps {{.*#+}} xmm1 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
-; CHECK-NEXT:    movsd %xmm0, %xmm1
+; CHECK-NEXT:    movapd {{.*#+}} xmm1 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
+; CHECK-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
 ; CHECK-NEXT:    xorpd %xmm2, %xmm2
 ; CHECK-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm2[1]
 ; CHECK-NEXT:    addps %xmm1, %xmm0
 ; CHECK-NEXT:    movaps %xmm0, 0
 ; CHECK-NEXT:    retl
-  %tmp1 = load <4 x float>* null          ; <<4 x float>> [#uses=2]
+  %tmp1 = load <4 x float>, <4 x float>* null          ; <<4 x float>> [#uses=2]
   %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> < float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 >, <4 x i32> < i32 0, i32 1, i32 6, i32 7 >             ; <<4 x float>> [#uses=1]
   %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 2, i32 3, i32 6, i32 7 >                ; <<4 x float>> [#uses=1]
   %tmp4 = fadd <4 x float> %tmp2, %tmp3            ; <<4 x float>> [#uses=1]
@@ -205,8 +205,8 @@ define void @test13(<4 x float>* %res, <4 x float>* %A, <4 x float>* %B, <4 x fl
 ; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
 ; CHECK-NEXT:    movaps %xmm0, (%eax)
 ; CHECK-NEXT:    retl
-  %tmp3 = load <4 x float>* %B            ; <<4 x float>> [#uses=1]
-  %tmp5 = load <4 x float>* %C            ; <<4 x float>> [#uses=1]
+  %tmp3 = load <4 x float>, <4 x float>* %B            ; <<4 x float>> [#uses=1]
+  %tmp5 = load <4 x float>, <4 x float>* %C            ; <<4 x float>> [#uses=1]
   %tmp11 = shufflevector <4 x float> %tmp3, <4 x float> %tmp5, <4 x i32> < i32 1, i32 4, i32 1, i32 5 >         ; <<4 x float>> [#uses=1]
   store <4 x float> %tmp11, <4 x float>* %res
   ret void
@@ -224,8 +224,8 @@ define <4 x float> @test14(<4 x float>* %x, <4 x float>* %y) nounwind {
 ; CHECK-NEXT:    subps %xmm1, %xmm2
 ; CHECK-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
 ; CHECK-NEXT:    retl
-  %tmp = load <4 x float>* %y             ; <<4 x float>> [#uses=2]
-  %tmp5 = load <4 x float>* %x            ; <<4 x float>> [#uses=2]
+  %tmp = load <4 x float>, <4 x float>* %y             ; <<4 x float>> [#uses=2]
+  %tmp5 = load <4 x float>, <4 x float>* %x            ; <<4 x float>> [#uses=2]
   %tmp9 = fadd <4 x float> %tmp5, %tmp             ; <<4 x float>> [#uses=1]
   %tmp21 = fsub <4 x float> %tmp5, %tmp            ; <<4 x float>> [#uses=1]
   %tmp27 = shufflevector <4 x float> %tmp9, <4 x float> %tmp21, <4 x i32> < i32 0, i32 1, i32 4, i32 5 >                ; <<4 x float>> [#uses=1]
@@ -241,8 +241,8 @@ define <4 x float> @test15(<4 x float>* %x, <4 x float>* %y) nounwind {
 ; CHECK-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1],mem[1]
 ; CHECK-NEXT:    retl
 entry:
-  %tmp = load <4 x float>* %y             ; <<4 x float>> [#uses=1]
-  %tmp3 = load <4 x float>* %x            ; <<4 x float>> [#uses=1]
+  %tmp = load <4 x float>, <4 x float>* %y             ; <<4 x float>> [#uses=1]
+  %tmp3 = load <4 x float>, <4 x float>* %x            ; <<4 x float>> [#uses=1]
   %tmp4 = shufflevector <4 x float> %tmp3, <4 x float> %tmp, <4 x i32> < i32 2, i32 3, i32 6, i32 7 >           ; <<4 x float>> [#uses=1]
   ret <4 x float> %tmp4
 }
@@ -256,8 +256,8 @@ define  <2 x double> @test16(<4 x double> * nocapture %srcA, <2 x double>* nocap
 ; CHECK-NEXT:    movapd 96(%eax), %xmm0
 ; CHECK-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],mem[0]
 ; CHECK-NEXT:    retl
-  %i5 = getelementptr inbounds <4 x double>* %srcA, i32 3
-  %i6 = load <4 x double>* %i5, align 32
+  %i5 = getelementptr inbounds <4 x double>, <4 x double>* %srcA, i32 3
+  %i6 = load <4 x double>, <4 x double>* %i5, align 32
   %i7 = shufflevector <4 x double> %i6, <4 x double> undef, <2 x i32> <i32 0, i32 2>
   ret <2 x double> %i7
 }
@@ -293,7 +293,7 @@ entry:
 define <2 x i64> @test_insert_64_zext(<2 x i64> %i) {
 ; CHECK-LABEL: test_insert_64_zext:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    movq %xmm0, %xmm0
+; CHECK-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
 ; CHECK-NEXT:    retl
   %1 = shufflevector <2 x i64> %i, <2 x i64> <i64 0, i64 undef>, <2 x i32> <i32 0, i32 2>
   ret <2 x i64> %1
@@ -302,8 +302,7 @@ define <2 x i64> @test_insert_64_zext(<2 x i64> %i) {
 define <4 x i32> @PR19721(<4 x i32> %i) {
 ; CHECK-LABEL: PR19721:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    xorps %xmm1, %xmm1
-; CHECK-NEXT:    movss %xmm1, %xmm0
+; CHECK-NEXT:    andps LCPI19_0, %xmm0
 ; CHECK-NEXT:    retl
   %bc = bitcast <4 x i32> %i to i128
   %insert = and i128 %bc, -4294967296
@@ -316,10 +315,11 @@ define <4 x i32> @test_mul(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
 ; CHECK-NEXT:    pmuludq %xmm1, %xmm0
+; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
 ; CHECK-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
 ; CHECK-NEXT:    pmuludq %xmm2, %xmm1
-; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
-; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; CHECK-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; CHECK-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; CHECK-NEXT:    retl
   %m = mul <4 x i32> %x, %y
   ret <4 x i32> %m
diff --git a/test/CodeGen/X86/sse3-avx-addsub-2.ll b/test/CodeGen/X86/sse3-avx-addsub-2.ll
index 5b2de28c0f5d..71efa3f8f105 100644
--- a/test/CodeGen/X86/sse3-avx-addsub-2.ll
+++ b/test/CodeGen/X86/sse3-avx-addsub-2.ll
@@ -315,4 +315,17 @@ define <4 x float> @test16(<4 x float> %A, <4 x float> %B) {
 ; CHECK-NOT: addsubps
 ; CHECK: ret
 
-
+define <2 x float> @test_v2f32(<2 x float> %v0, <2 x float> %v1) {
+  %v2 = extractelement <2 x float> %v0, i32 0
+  %v3 = extractelement <2 x float> %v1, i32 0
+  %v4 = extractelement <2 x float> %v0, i32 1
+  %v5 = extractelement <2 x float> %v1, i32 1
+  %sub = fsub float %v2, %v3
+  %add = fadd float %v5, %v4
+  %res0 = insertelement <2 x float> undef, float %sub, i32 0
+  %res1 = insertelement <2 x float> %res0, float %add, i32 1
+  ret <2 x float> %res1
+}
+; CHECK-LABEL: test_v2f32
+; CHECK: addsubps %xmm1, %xmm0
+; CHECK-NEXT: retq
diff --git a/test/CodeGen/X86/sse3-avx-addsub.ll b/test/CodeGen/X86/sse3-avx-addsub.ll
index 431588f90ab2..76141fc876ae 100644
--- a/test/CodeGen/X86/sse3-avx-addsub.ll
+++ b/test/CodeGen/X86/sse3-avx-addsub.ll
@@ -87,7 +87,7 @@ define <2 x double> @test4(<2 x double> %A, <2 x double> %B) #0 {
 
 
 define <4 x float> @test1b(<4 x float> %A, <4 x float>* %B) {
-  %1 = load <4 x float>* %B
+  %1 = load <4 x float>, <4 x float>* %B
   %add = fadd <4 x float> %A, %1
   %sub = fsub <4 x float> %A, %1
   %vecinit6 = shufflevector <4 x float> %sub, <4 x float> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
@@ -100,7 +100,7 @@ define <4 x float> @test1b(<4 x float> %A, <4 x float>* %B) {
 
 
 define <8 x float> @test2b(<8 x float> %A, <8 x float>* %B) {
-  %1 = load <8 x float>* %B
+  %1 = load <8 x float>, <8 x float>* %B
   %add = fadd <8 x float> %A, %1
   %sub = fsub <8 x float> %A, %1
   %vecinit14 = shufflevector <8 x float> %sub, <8 x float> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
@@ -115,7 +115,7 @@ define <8 x float> @test2b(<8 x float> %A, <8 x float>* %B) {
 
 
 define <4 x double> @test3b(<4 x double> %A, <4 x double>* %B) {
-  %1 = load <4 x double>* %B
+  %1 = load <4 x double>, <4 x double>* %B
   %add = fadd <4 x double> %A, %1
   %sub = fsub <4 x double> %A, %1
   %vecinit6 = shufflevector <4 x double> %sub, <4 x double> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
@@ -130,7 +130,7 @@ define <4 x double> @test3b(<4 x double> %A, <4 x double>* %B) {
 
 
 define <2 x double> @test4b(<2 x double> %A, <2 x double>* %B) {
-  %1 = load <2 x double>* %B
+  %1 = load <2 x double>, <2 x double>* %B
   %sub = fsub <2 x double> %A, %1
   %add = fadd <2 x double> %A, %1
   %vecinit2 = shufflevector <2 x double> %sub, <2 x double> %add, <2 x i32> <i32 0, i32 3>
diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll
index 0a5b0cab851c..c1cd91beaf53 100644
--- a/test/CodeGen/X86/sse3.ll
+++ b/test/CodeGen/X86/sse3.ll
@@ -14,7 +14,7 @@ define void @t0(<8 x i16>* %dest, <8 x i16>* %old) nounwind {
 ; X64-NEXT:    movdqa %xmm0, (%rdi)
 ; X64-NEXT:    retq
 entry:
-	%tmp3 = load <8 x i16>* %old
+	%tmp3 = load <8 x i16>, <8 x i16>* %old
 	%tmp6 = shufflevector <8 x i16> %tmp3,
                 <8 x i16> < i16 1, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef >,
                 <8 x i32> < i32 8, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef  >
@@ -25,17 +25,14 @@ entry:
 define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ; X64-LABEL: t1:
 ; X64:       ## BB#0:
-; X64-NEXT:    movdqa (%rdi), %xmm0
-; X64-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
-; X64-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
-; X64-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[2,1,2,3,4,5,6,7]
-; X64-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
-; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; X64-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[1,0,2,3,4,5,6,7]
-; X64-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X64-NEXT:    movaps {{.*#+}} xmm0 = [0,65535,65535,65535,65535,65535,65535,65535]
+; X64-NEXT:    movaps %xmm0, %xmm1
+; X64-NEXT:    andnps (%rsi), %xmm1
+; X64-NEXT:    andps (%rdi), %xmm0
+; X64-NEXT:    orps %xmm1, %xmm0
 ; X64-NEXT:    retq
-	%tmp1 = load <8 x i16>* %A
-	%tmp2 = load <8 x i16>* %B
+	%tmp1 = load <8 x i16>, <8 x i16>* %A
+	%tmp2 = load <8 x i16>, <8 x i16>* %B
 	%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
 	ret <8 x i16> %tmp3
 
@@ -44,11 +41,11 @@ define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) nounwind {
 ; X64-LABEL: t2:
 ; X64:       ## BB#0:
-; X64-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
-; X64-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
-; X64-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[3,2,0,3,4,5,6,7]
-; X64-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; X64-NEXT:    movdqa {{.*#+}} xmm2 = [0,65535,65535,0,65535,65535,65535,65535]
+; X64-NEXT:    pand %xmm2, %xmm0
+; X64-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[1,1,2,1,4,5,6,7]
+; X64-NEXT:    pandn %xmm1, %xmm2
+; X64-NEXT:    por %xmm2, %xmm0
 ; X64-NEXT:    retq
 	%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 9, i32 1, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7 >
 	ret <8 x i16> %tmp
@@ -92,7 +89,7 @@ define <8 x i16> @t5(<8 x i16> %A, <8 x i16> %B) nounwind {
 define <8 x i16> @t6(<8 x i16> %A, <8 x i16> %B) nounwind {
 ; X64-LABEL: t6:
 ; X64:       ## BB#0:
-; X64-NEXT:    movss %xmm1, %xmm0
+; X64-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
 ; X64-NEXT:    retq
 	%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
 	ret <8 x i16> %tmp
@@ -115,7 +112,7 @@ define void @t8(<2 x i64>* %res, <2 x i64>* %A) nounwind {
 ; X64-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,5,4,7]
 ; X64-NEXT:    movdqa %xmm0, (%rdi)
 ; X64-NEXT:    retq
-	%tmp = load <2 x i64>* %A
+	%tmp = load <2 x i64>, <2 x i64>* %A
 	%tmp.upgrd.1 = bitcast <2 x i64> %tmp to <8 x i16>
 	%tmp0 = extractelement <8 x i16> %tmp.upgrd.1, i32 0
 	%tmp1 = extractelement <8 x i16> %tmp.upgrd.1, i32 1
@@ -145,9 +142,9 @@ define void @t9(<4 x float>* %r, <2 x i32>* %A) nounwind {
 ; X64-NEXT:    movhpd (%rsi), %xmm0
 ; X64-NEXT:    movapd %xmm0, (%rdi)
 ; X64-NEXT:    retq
-	%tmp = load <4 x float>* %r
+	%tmp = load <4 x float>, <4 x float>* %r
 	%tmp.upgrd.3 = bitcast <2 x i32>* %A to double*
-	%tmp.upgrd.4 = load double* %tmp.upgrd.3
+	%tmp.upgrd.4 = load double, double* %tmp.upgrd.3
 	%tmp.upgrd.5 = insertelement <2 x double> undef, double %tmp.upgrd.4, i32 0
 	%tmp5 = insertelement <2 x double> %tmp.upgrd.5, double undef, i32 1
 	%tmp6 = bitcast <2 x double> %tmp5 to <4 x float>
@@ -181,7 +178,7 @@ define void @t10() nounwind {
 ; X64-NEXT:    movq _g2@{{.*}}(%rip), %rax
 ; X64-NEXT:    movq %xmm0, (%rax)
 ; X64-NEXT:    retq
-  load <4 x i32>* @g1, align 16
+  load <4 x i32>, <4 x i32>* @g1, align 16
   bitcast <4 x i32> %1 to <8 x i16>
   shufflevector <8 x i16> %2, <8 x i16> undef, <8 x i32> < i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef >
   bitcast <8 x i16> %3 to <2 x i64>
@@ -195,8 +192,8 @@ define void @t10() nounwind {
 define <8 x i16> @t11(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 ; X64-LABEL: t11:
 ; X64:       ## BB#0: ## %entry
+; X64-NEXT:    psrld $16, %xmm0
 ; X64-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; X64-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[2,1,2,3,4,5,6,7]
 ; X64-NEXT:    retq
 entry:
 	%tmp7 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 1, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
@@ -232,8 +229,9 @@ entry:
 define <8 x i16> @t14(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 ; X64-LABEL: t14:
 ; X64:       ## BB#0: ## %entry
-; X64-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; X64-NEXT:    pshuflw {{.*#+}} xmm0 = xmm1[0,2,2,3,4,5,6,7]
+; X64-NEXT:    psrlq $16, %xmm0
+; X64-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; X64-NEXT:    movdqa %xmm1, %xmm0
 ; X64-NEXT:    retq
 entry:
 	%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 2, i32 undef , i32 undef >
@@ -245,11 +243,8 @@ define <8 x i16> @t15(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 ; X64-LABEL: t15:
 ; X64:       ## BB#0: ## %entry
 ; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
-; X64-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[1,1,2,3,4,5,6,7]
-; X64-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,0,3]
-; X64-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7]
-; X64-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,6,7]
+; X64-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,1,1,2,4,5,6,7]
+; X64-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
 ; X64-NEXT:    retq
 entry:
   %tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef >
@@ -262,15 +257,7 @@ define <16 x i8> @t16(<16 x i8> %T0) nounwind readnone {
 ; X64:       ## BB#0: ## %entry
 ; X64-NEXT:    movdqa {{.*#+}} xmm1 = [0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0]
 ; X64-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; X64-NEXT:    pxor %xmm2, %xmm2
-; X64-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
-; X64-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
-; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
-; X64-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; X64-NEXT:    pshuflw {{.*#+}} xmm0 = xmm1[0,2,2,3,4,5,6,7]
-; X64-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,7,6,7]
-; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; X64-NEXT:    packuswb %xmm0, %xmm0
+; X64-NEXT:    movdqa %xmm1, %xmm0
 ; X64-NEXT:    retq
 entry:
   %tmp8 = shufflevector <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 0, i8 0, i8 0, i8 0,  i8 0, i8 0, i8 0, i8 0>, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 16, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
@@ -282,13 +269,13 @@ entry:
 define <4 x i32> @t17() nounwind {
 ; X64-LABEL: t17:
 ; X64:       ## BB#0: ## %entry
-; X64-NEXT:    movddup (%rax), %xmm0
+; X64-NEXT:    movddup {{.*#+}} xmm0 = mem[0,0]
 ; X64-NEXT:    andpd {{.*}}(%rip), %xmm0
 ; X64-NEXT:    retq
 entry:
-  %tmp1 = load <4 x float>* undef, align 16
+  %tmp1 = load <4 x float>, <4 x float>* undef, align 16
   %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
-  %tmp3 = load <4 x float>* undef, align 16
+  %tmp3 = load <4 x float>, <4 x float>* undef, align 16
   %tmp4 = shufflevector <4 x float> %tmp2, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
   %tmp5 = bitcast <4 x float> %tmp3 to <4 x i32>
   %tmp6 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
diff --git a/test/CodeGen/X86/sse41-intrinsics-x86.ll b/test/CodeGen/X86/sse41-intrinsics-x86.ll
index 5f25a16380de..771e4024336c 100644
--- a/test/CodeGen/X86/sse41-intrinsics-x86.ll
+++ b/test/CodeGen/X86/sse41-intrinsics-x86.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+sse4.1 | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=knl | FileCheck %s
 
 define <2 x double> @test_x86_sse41_blendpd(<2 x double> %a0, <2 x double> %a1) {
   ; CHECK: blendpd
diff --git a/test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll b/test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll
index 55faf4d32b36..a16e79277143 100644
--- a/test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll
+++ b/test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll
@@ -5,7 +5,7 @@ define <8 x i16> @test_llvm_x86_sse41_pmovsxbw(<16 x i8>* %a) {
 ; CHECK-LABEL: test_llvm_x86_sse41_pmovsxbw
 ; SSE41: pmovsxbw (%rdi), %xmm0
 ; AVX:  vpmovsxbw (%rdi), %xmm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8> %1)
   ret <8 x i16> %2
 }
@@ -14,7 +14,7 @@ define <4 x i32> @test_llvm_x86_sse41_pmovsxbd(<16 x i8>* %a) {
 ; CHECK-LABEL: test_llvm_x86_sse41_pmovsxbd
 ; SSE41: pmovsxbd (%rdi), %xmm0
 ; AVX:  vpmovsxbd (%rdi), %xmm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %1)
   ret <4 x i32> %2
 }
@@ -23,7 +23,7 @@ define <2 x i64> @test_llvm_x86_sse41_pmovsxbq(<16 x i8>* %a) {
 ; CHECK-LABEL: test_llvm_x86_sse41_pmovsxbq
 ; SSE41: pmovsxbq (%rdi), %xmm0
 ; AVX:  vpmovsxbq (%rdi), %xmm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8> %1)
   ret <2 x i64> %2
 }
@@ -32,7 +32,7 @@ define <4 x i32> @test_llvm_x86_sse41_pmovsxwd(<8 x i16>* %a) {
 ; CHECK-LABEL: test_llvm_x86_sse41_pmovsxwd
 ; SSE41: pmovsxwd (%rdi), %xmm0
 ; AVX:  vpmovsxwd (%rdi), %xmm0
-  %1 = load <8 x i16>* %a, align 1
+  %1 = load <8 x i16>, <8 x i16>* %a, align 1
   %2 = call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1)
   ret <4 x i32> %2
 }
@@ -41,7 +41,7 @@ define <2 x i64> @test_llvm_x86_sse41_pmovsxwq(<8 x i16>* %a) {
 ; CHECK-LABEL: test_llvm_x86_sse41_pmovsxwq
 ; SSE41: pmovsxwq (%rdi), %xmm0
 ; AVX:  vpmovsxwq (%rdi), %xmm0
-  %1 = load <8 x i16>* %a, align 1
+  %1 = load <8 x i16>, <8 x i16>* %a, align 1
   %2 = call <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16> %1)
   ret <2 x i64> %2
 }
@@ -50,7 +50,7 @@ define <2 x i64> @test_llvm_x86_sse41_pmovsxdq(<4 x i32>* %a) {
 ; CHECK-LABEL: test_llvm_x86_sse41_pmovsxdq
 ; SSE41: pmovsxdq (%rdi), %xmm0
 ; AVX:  vpmovsxdq (%rdi), %xmm0
-  %1 = load <4 x i32>* %a, align 1
+  %1 = load <4 x i32>, <4 x i32>* %a, align 1
   %2 = call <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32> %1)
   ret <2 x i64> %2
 }
@@ -59,7 +59,7 @@ define <8 x i16> @test_llvm_x86_sse41_pmovzxbw(<16 x i8>* %a) {
 ; CHECK-LABEL: test_llvm_x86_sse41_pmovzxbw
 ; SSE41: pmovzxbw (%rdi), %xmm0
 ; AVX:  vpmovzxbw (%rdi), %xmm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %1)
   ret <8 x i16> %2
 }
@@ -68,7 +68,7 @@ define <4 x i32> @test_llvm_x86_sse41_pmovzxbd(<16 x i8>* %a) {
 ; CHECK-LABEL: test_llvm_x86_sse41_pmovzxbd
 ; SSE41: pmovzxbd (%rdi), %xmm0
 ; AVX:  vpmovzxbd (%rdi), %xmm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8> %1)
   ret <4 x i32> %2
 }
@@ -77,7 +77,7 @@ define <2 x i64> @test_llvm_x86_sse41_pmovzxbq(<16 x i8>* %a) {
 ; CHECK-LABEL: test_llvm_x86_sse41_pmovzxbq
 ; SSE41: pmovzxbq (%rdi), %xmm0
 ; AVX:  vpmovzxbq (%rdi), %xmm0
-  %1 = load <16 x i8>* %a, align 1
+  %1 = load <16 x i8>, <16 x i8>* %a, align 1
   %2 = call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %1)
   ret <2 x i64> %2
 }
@@ -86,7 +86,7 @@ define <4 x i32> @test_llvm_x86_sse41_pmovzxwd(<8 x i16>* %a) {
 ; CHECK-LABEL: test_llvm_x86_sse41_pmovzxwd
 ; SSE41: pmovzxwd (%rdi), %xmm0
 ; AVX:  vpmovzxwd (%rdi), %xmm0
-  %1 = load <8 x i16>* %a, align 1
+  %1 = load <8 x i16>, <8 x i16>* %a, align 1
   %2 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %1)
   ret <4 x i32> %2
 }
@@ -95,7 +95,7 @@ define <2 x i64> @test_llvm_x86_sse41_pmovzxwq(<8 x i16>* %a) {
 ; CHECK-LABEL: test_llvm_x86_sse41_pmovzxwq
 ; SSE41: pmovzxwq (%rdi), %xmm0
 ; AVX:  vpmovzxwq (%rdi), %xmm0
-  %1 = load <8 x i16>* %a, align 1
+  %1 = load <8 x i16>, <8 x i16>* %a, align 1
   %2 = call <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16> %1)
   ret <2 x i64> %2
 }
@@ -104,7 +104,7 @@ define <2 x i64> @test_llvm_x86_sse41_pmovzxdq(<4 x i32>* %a) {
 ; CHECK-LABEL: test_llvm_x86_sse41_pmovzxdq
 ; SSE41: pmovzxdq (%rdi), %xmm0
 ; AVX:  vpmovzxdq (%rdi), %xmm0
-  %1 = load <4 x i32>* %a, align 1
+  %1 = load <4 x i32>, <4 x i32>* %a, align 1
   %2 = call <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32> %1)
   ret <2 x i64> %2
 }
diff --git a/test/CodeGen/X86/sse41.ll b/test/CodeGen/X86/sse41.ll
index 9c0c2221cb7f..8532c012aa9b 100644
--- a/test/CodeGen/X86/sse41.ll
+++ b/test/CodeGen/X86/sse41.ll
@@ -43,7 +43,7 @@ define <2 x i64> @pmovsxbd_1(i32* %p) nounwind {
 ; X64-NEXT:    pmovsxbd (%rdi), %xmm0
 ; X64-NEXT:    retq
 entry:
-	%0 = load i32* %p, align 4
+	%0 = load i32, i32* %p, align 4
 	%1 = insertelement <4 x i32> undef, i32 %0, i32 0
 	%2 = insertelement <4 x i32> %1, i32 0, i32 1
 	%3 = insertelement <4 x i32> %2, i32 0, i32 2
@@ -66,7 +66,7 @@ define <2 x i64> @pmovsxwd_1(i64* %p) nounwind readonly {
 ; X64-NEXT:    pmovsxwd (%rdi), %xmm0
 ; X64-NEXT:    retq
 entry:
-	%0 = load i64* %p		; <i64> [#uses=1]
+	%0 = load i64, i64* %p		; <i64> [#uses=1]
 	%tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0		; <<2 x i64>> [#uses=1]
 	%1 = bitcast <2 x i64> %tmp2 to <8 x i16>		; <<8 x i16>> [#uses=1]
 	%2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone		; <<4 x i32>> [#uses=1]
@@ -78,16 +78,16 @@ define <2 x i64> @pmovzxbq_1() nounwind {
 ; X32-LABEL: pmovzxbq_1:
 ; X32:       ## BB#0: ## %entry
 ; X32-NEXT:    movl L_g16$non_lazy_ptr, %eax
-; X32-NEXT:    pmovzxbq (%eax), %xmm0
+; X32-NEXT:    pmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: pmovzxbq_1:
 ; X64:       ## BB#0: ## %entry
 ; X64-NEXT:    movq _g16@{{.*}}(%rip), %rax
-; X64-NEXT:    pmovzxbq (%rax), %xmm0
+; X64-NEXT:    pmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
 ; X64-NEXT:    retq
 entry:
-	%0 = load i16* @g16, align 2		; <i16> [#uses=1]
+	%0 = load i16, i16* @g16, align 2		; <i16> [#uses=1]
 	%1 = insertelement <8 x i16> undef, i16 %0, i32 0		; <<8 x i16>> [#uses=1]
 	%2 = bitcast <8 x i16> %1 to <16 x i8>		; <<16 x i8>> [#uses=1]
 	%3 = tail call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %2) nounwind readnone		; <<2 x i64>> [#uses=1]
@@ -199,28 +199,51 @@ define <4 x float> @insertps_1(<4 x float> %t1, <4 x float> %t2) nounwind {
 
 declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
 
-define <4 x float> @insertps_2(<4 x float> %t1, float %t2) nounwind {
-; X32-LABEL: insertps_2:
+; When optimizing for speed, prefer blendps over insertps even if it means we have to
+; generate a separate movss to load the scalar operand.
+define <4 x float> @blendps_not_insertps_1(<4 x float> %t1, float %t2) nounwind {
+; X32-LABEL: blendps_not_insertps_1:
 ; X32:       ## BB#0:
-; X32-NEXT:    insertps $0, {{[0-9]+}}(%esp), %xmm0
+; X32-NEXT:    movss   {{.*#+}} xmm1
+; X32-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
 ; X32-NEXT:    retl
 ;
-; X64-LABEL: insertps_2:
+; X64-LABEL: blendps_not_insertps_1:
 ; X64:       ## BB#0:
-; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; X64-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
 ; X64-NEXT:    retq
   %tmp1 = insertelement <4 x float> %t1, float %t2, i32 0
   ret <4 x float> %tmp1
 }
-define <4 x float> @insertps_3(<4 x float> %t1, <4 x float> %t2) nounwind {
-; X32-LABEL: insertps_3:
+
+; When optimizing for size, generate an insertps if there's a load fold opportunity.
+; The difference between i386 and x86-64 ABIs for the float operand means we should
+; generate an insertps for X32 but not for X64!
+define <4 x float> @insertps_or_blendps(<4 x float> %t1, float %t2) minsize nounwind {
+; X32-LABEL: insertps_or_blendps:
 ; X32:       ## BB#0:
-; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; X32-NEXT:    insertps {{.*#+}} xmm0 = mem[0],xmm0[1,2,3]
 ; X32-NEXT:    retl
 ;
-; X64-LABEL: insertps_3:
+; X64-LABEL: insertps_or_blendps:
 ; X64:       ## BB#0:
-; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; X64-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; X64-NEXT:    retq
+  %tmp1 = insertelement <4 x float> %t1, float %t2, i32 0
+  ret <4 x float> %tmp1
+}
+
+; An insert into the low 32-bits of a vector from the low 32-bits of another vector
+; is always just a blendps because blendps is never more expensive than insertps.
+define <4 x float> @blendps_not_insertps_2(<4 x float> %t1, <4 x float> %t2) nounwind {
+; X32-LABEL: blendps_not_insertps_2:
+; X32:       ## BB#0:
+; X32-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; X32-NEXT:    retl
+;
+; X64-LABEL: blendps_not_insertps_2:
+; X64:       ## BB#0:
+; X64-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
 ; X64-NEXT:    retq
   %tmp2 = extractelement <4 x float> %t2, i32 0
   %tmp1 = insertelement <4 x float> %t1, float %tmp2, i32 0
@@ -291,22 +314,20 @@ declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone
 define <2 x float> @buildvector(<2 x float> %A, <2 x float> %B) nounwind  {
 ; X32-LABEL: buildvector:
 ; X32:       ## BB#0: ## %entry
-; X32-NEXT:    movaps %xmm0, %xmm2
-; X32-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,1,2,3]
+; X32-NEXT:    movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; X32-NEXT:    movshdup {{.*#+}} xmm3 = xmm1[1,1,3,3]
 ; X32-NEXT:    addss %xmm1, %xmm0
-; X32-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
-; X32-NEXT:    addss %xmm2, %xmm1
-; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+; X32-NEXT:    addss %xmm2, %xmm3
+; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: buildvector:
 ; X64:       ## BB#0: ## %entry
-; X64-NEXT:    movaps %xmm0, %xmm2
-; X64-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,1,2,3]
+; X64-NEXT:    movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; X64-NEXT:    movshdup {{.*#+}} xmm3 = xmm1[1,1,3,3]
 ; X64-NEXT:    addss %xmm1, %xmm0
-; X64-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
-; X64-NEXT:    addss %xmm2, %xmm1
-; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+; X64-NEXT:    addss %xmm2, %xmm3
+; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3]
 ; X64-NEXT:    retq
 entry:
   %tmp7 = extractelement <2 x float> %A, i32 0
@@ -324,15 +345,15 @@ define <4 x float> @insertps_from_shufflevector_1(<4 x float> %a, <4 x float>* n
 ; X32-LABEL: insertps_from_shufflevector_1:
 ; X32:       ## BB#0: ## %entry
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    insertps $48, (%eax), %xmm0
+; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_from_shufflevector_1:
 ; X64:       ## BB#0: ## %entry
-; X64-NEXT:    insertps $48, (%rdi), %xmm0
+; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
 ; X64-NEXT:    retq
 entry:
-  %0 = load <4 x float>* %pb, align 16
+  %0 = load <4 x float>, <4 x float>* %pb, align 16
   %vecinit6 = shufflevector <4 x float> %a, <4 x float> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
   ret <4 x float> %vecinit6
 }
@@ -358,15 +379,17 @@ define <4 x i32> @pinsrd_from_shufflevector_i32(<4 x i32> %a, <4 x i32>* nocaptu
 ; X32-LABEL: pinsrd_from_shufflevector_i32:
 ; X32:       ## BB#0: ## %entry
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    insertps $48, (%eax), %xmm0
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = mem[0,1,2,0]
+; X32-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: pinsrd_from_shufflevector_i32:
 ; X64:       ## BB#0: ## %entry
-; X64-NEXT:    insertps $48, (%rdi), %xmm0
+; X64-NEXT:    pshufd {{.*#+}} xmm1 = mem[0,1,2,0]
+; X64-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
 ; X64-NEXT:    retq
 entry:
-  %0 = load <4 x i32>* %pb, align 16
+  %0 = load <4 x i32>, <4 x i32>* %pb, align 16
   %vecinit6 = shufflevector <4 x i32> %a, <4 x i32> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
   ret <4 x i32> %vecinit6
 }
@@ -374,12 +397,14 @@ entry:
 define <4 x i32> @insertps_from_shufflevector_i32_2(<4 x i32> %a, <4 x i32> %b) {
 ; X32-LABEL: insertps_from_shufflevector_i32_2:
 ; X32:       ## BB#0: ## %entry
-; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],xmm1[3],xmm0[2,3]
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; X32-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_from_shufflevector_i32_2:
 ; X64:       ## BB#0: ## %entry
-; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],xmm1[3],xmm0[2,3]
+; X64-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; X64-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
 ; X64-NEXT:    retq
 entry:
   %vecinit6 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
@@ -390,14 +415,14 @@ define <4 x float> @insertps_from_load_ins_elt_undef(<4 x float> %a, float* %b)
 ; X32-LABEL: insertps_from_load_ins_elt_undef:
 ; X32:       ## BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    insertps $16, (%eax), %xmm0
+; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_from_load_ins_elt_undef:
 ; X64:       ## BB#0:
-; X64-NEXT:    insertps $16, (%rdi), %xmm0
+; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
 ; X64-NEXT:    retq
-  %1 = load float* %b, align 4
+  %1 = load float, float* %b, align 4
   %2 = insertelement <4 x float> undef, float %1, i32 0
   %result = shufflevector <4 x float> %a, <4 x float> %2, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
   ret <4 x float> %result
@@ -408,16 +433,18 @@ define <4 x i32> @insertps_from_load_ins_elt_undef_i32(<4 x i32> %a, i32* %b) {
 ; X32-LABEL: insertps_from_load_ins_elt_undef_i32:
 ; X32:       ## BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    movd (%eax), %xmm1
-; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
+; X32-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
+; X32-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_from_load_ins_elt_undef_i32:
 ; X64:       ## BB#0:
-; X64-NEXT:    movd (%rdi), %xmm1
-; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
+; X64-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X64-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
+; X64-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
 ; X64-NEXT:    retq
-  %1 = load i32* %b, align 4
+  %1 = load i32, i32* %b, align 4
   %2 = insertelement <4 x i32> undef, i32 %1, i32 0
   %result = shufflevector <4 x i32> %a, <4 x i32> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
   ret <4 x i32> %result
@@ -449,12 +476,12 @@ define <4 x float> @shuf_XYZ0(<4 x float> %x, <4 x float> %a) {
 define <4 x float> @shuf_XY00(<4 x float> %x, <4 x float> %a) {
 ; X32-LABEL: shuf_XY00:
 ; X32:       ## BB#0:
-; X32-NEXT:    movq %xmm0, %xmm0
+; X32-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: shuf_XY00:
 ; X64:       ## BB#0:
-; X64-NEXT:    movq %xmm0, %xmm0
+; X64-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
 ; X64-NEXT:    retq
   %vecext = extractelement <4 x float> %x, i32 0
   %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
@@ -547,18 +574,12 @@ define <4 x float> @shuf_X00A(<4 x float> %x, <4 x float> %a) {
 define <4 x float> @shuf_X00X(<4 x float> %x, <4 x float> %a) {
 ; X32-LABEL: shuf_X00X:
 ; X32:       ## BB#0:
-; X32-NEXT:    xorps %xmm1, %xmm1
-; X32-NEXT:    blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
-; X32-NEXT:    insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
-; X32-NEXT:    movaps %xmm1, %xmm0
+; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm0[0]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: shuf_X00X:
 ; X64:       ## BB#0:
-; X64-NEXT:    xorps %xmm1, %xmm1
-; X64-NEXT:    blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
-; X64-NEXT:    insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
-; X64-NEXT:    movaps %xmm1, %xmm0
+; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm0[0]
 ; X64-NEXT:    retq
   %vecext = extractelement <4 x float> %x, i32 0
   %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
@@ -571,20 +592,14 @@ define <4 x float> @shuf_X00X(<4 x float> %x, <4 x float> %a) {
 define <4 x float> @shuf_X0YC(<4 x float> %x, <4 x float> %a) {
 ; X32-LABEL: shuf_X0YC:
 ; X32:       ## BB#0:
-; X32-NEXT:    xorps %xmm2, %xmm2
-; X32-NEXT:    blendps {{.*#+}} xmm2 = xmm0[0],xmm2[1],xmm0[2,3]
-; X32-NEXT:    insertps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1],zero
-; X32-NEXT:    insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
-; X32-NEXT:    movaps %xmm2, %xmm0
+; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
+; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[2]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: shuf_X0YC:
 ; X64:       ## BB#0:
-; X64-NEXT:    xorps %xmm2, %xmm2
-; X64-NEXT:    blendps {{.*#+}} xmm2 = xmm0[0],xmm2[1],xmm0[2,3]
-; X64-NEXT:    insertps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1],zero
-; X64-NEXT:    insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
-; X64-NEXT:    movaps %xmm2, %xmm0
+; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
+; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[2]
 ; X64-NEXT:    retq
   %vecext = extractelement <4 x float> %x, i32 0
   %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
@@ -619,12 +634,12 @@ define <4 x i32> @i32_shuf_XYZ0(<4 x i32> %x, <4 x i32> %a) {
 define <4 x i32> @i32_shuf_XY00(<4 x i32> %x, <4 x i32> %a) {
 ; X32-LABEL: i32_shuf_XY00:
 ; X32:       ## BB#0:
-; X32-NEXT:    movq %xmm0, %xmm0
+; X32-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: i32_shuf_XY00:
 ; X64:       ## BB#0:
-; X64-NEXT:    movq %xmm0, %xmm0
+; X64-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
 ; X64-NEXT:    retq
   %vecext = extractelement <4 x i32> %x, i32 0
   %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
@@ -638,12 +653,16 @@ define <4 x i32> @i32_shuf_XY00(<4 x i32> %x, <4 x i32> %a) {
 define <4 x i32> @i32_shuf_XYY0(<4 x i32> %x, <4 x i32> %a) {
 ; X32-LABEL: i32_shuf_XYY0:
 ; X32:       ## BB#0:
-; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
+; X32-NEXT:    pxor %xmm0, %xmm0
+; X32-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: i32_shuf_XYY0:
 ; X64:       ## BB#0:
-; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
+; X64-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
+; X64-NEXT:    pxor %xmm0, %xmm0
+; X64-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
 ; X64-NEXT:    retq
   %vecext = extractelement <4 x i32> %x, i32 0
   %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
@@ -657,12 +676,16 @@ define <4 x i32> @i32_shuf_XYY0(<4 x i32> %x, <4 x i32> %a) {
 define <4 x i32> @i32_shuf_XYW0(<4 x i32> %x, <4 x i32> %a) {
 ; X32-LABEL: i32_shuf_XYW0:
 ; X32:       ## BB#0:
-; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[0,1,3,3]
+; X32-NEXT:    pxor %xmm0, %xmm0
+; X32-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: i32_shuf_XYW0:
 ; X64:       ## BB#0:
-; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
+; X64-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[0,1,3,3]
+; X64-NEXT:    pxor %xmm0, %xmm0
+; X64-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
 ; X64-NEXT:    retq
   %vecext = extractelement <4 x i32> %x, i32 0
   %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
@@ -677,12 +700,16 @@ define <4 x i32> @i32_shuf_XYW0(<4 x i32> %x, <4 x i32> %a) {
 define <4 x i32> @i32_shuf_W00W(<4 x i32> %x, <4 x i32> %a) {
 ; X32-LABEL: i32_shuf_W00W:
 ; X32:       ## BB#0:
-; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[3,1,2,3]
+; X32-NEXT:    pxor %xmm0, %xmm0
+; X32-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: i32_shuf_W00W:
 ; X64:       ## BB#0:
-; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
+; X64-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[3,1,2,3]
+; X64-NEXT:    pxor %xmm0, %xmm0
+; X64-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
 ; X64-NEXT:    retq
   %vecext = extractelement <4 x i32> %x, i32 3
   %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
@@ -697,14 +724,16 @@ define <4 x i32> @i32_shuf_X00A(<4 x i32> %x, <4 x i32> %a) {
 ; X32:       ## BB#0:
 ; X32-NEXT:    pxor %xmm2, %xmm2
 ; X32-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7]
-; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,1,2,0]
+; X32-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: i32_shuf_X00A:
 ; X64:       ## BB#0:
 ; X64-NEXT:    pxor %xmm2, %xmm2
 ; X64-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7]
-; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
+; X64-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,1,2,0]
+; X64-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
 ; X64-NEXT:    retq
   %vecext = extractelement <4 x i32> %x, i32 0
   %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
@@ -717,18 +746,16 @@ define <4 x i32> @i32_shuf_X00A(<4 x i32> %x, <4 x i32> %a) {
 define <4 x i32> @i32_shuf_X00X(<4 x i32> %x, <4 x i32> %a) {
 ; X32-LABEL: i32_shuf_X00X:
 ; X32:       ## BB#0:
-; X32-NEXT:    pxor %xmm1, %xmm1
-; X32-NEXT:    pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
-; X32-NEXT:    insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
-; X32-NEXT:    movaps %xmm1, %xmm0
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[0,1,2,0]
+; X32-NEXT:    pxor %xmm0, %xmm0
+; X32-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: i32_shuf_X00X:
 ; X64:       ## BB#0:
-; X64-NEXT:    pxor %xmm1, %xmm1
-; X64-NEXT:    pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
-; X64-NEXT:    insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
-; X64-NEXT:    movaps %xmm1, %xmm0
+; X64-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[0,1,2,0]
+; X64-NEXT:    pxor %xmm0, %xmm0
+; X64-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
 ; X64-NEXT:    retq
   %vecext = extractelement <4 x i32> %x, i32 0
   %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
@@ -741,18 +768,16 @@ define <4 x i32> @i32_shuf_X00X(<4 x i32> %x, <4 x i32> %a) {
 define <4 x i32> @i32_shuf_X0YC(<4 x i32> %x, <4 x i32> %a) {
 ; X32-LABEL: i32_shuf_X0YC:
 ; X32:       ## BB#0:
-; X32-NEXT:    pmovzxdq %xmm0, %xmm2
-; X32-NEXT:    insertps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1],zero
-; X32-NEXT:    insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
-; X32-NEXT:    movaps %xmm2, %xmm0
+; X32-NEXT:    pmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero
+; X32-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[0,1,2,2]
+; X32-NEXT:    pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3,4,5],xmm0[6,7]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: i32_shuf_X0YC:
 ; X64:       ## BB#0:
-; X64-NEXT:    pmovzxdq %xmm0, %xmm2
-; X64-NEXT:    insertps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1],zero
-; X64-NEXT:    insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
-; X64-NEXT:    movaps %xmm2, %xmm0
+; X64-NEXT:    pmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero
+; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[0,1,2,2]
+; X64-NEXT:    pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3,4,5],xmm0[6,7]
 ; X64-NEXT:    retq
   %vecext = extractelement <4 x i32> %x, i32 0
   %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
@@ -814,14 +839,14 @@ define <4 x float> @insertps_from_vector_load(<4 x float> %a, <4 x float>* nocap
 ; X32-LABEL: insertps_from_vector_load:
 ; X32:       ## BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    insertps $48, (%eax), %xmm0
+; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_from_vector_load:
 ; X64:       ## BB#0:
-; X64-NEXT:    insertps $48, (%rdi), %xmm0
+; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
 ; X64-NEXT:    retq
-  %1 = load <4 x float>* %pb, align 16
+  %1 = load <4 x float>, <4 x float>* %pb, align 16
   %2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 48)
   ret <4 x float> %2
 }
@@ -832,14 +857,14 @@ define <4 x float> @insertps_from_vector_load_offset(<4 x float> %a, <4 x float>
 ; X32-LABEL: insertps_from_vector_load_offset:
 ; X32:       ## BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    insertps $96, 4(%eax), %xmm0
+; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1],mem[1],xmm0[3]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_from_vector_load_offset:
 ; X64:       ## BB#0:
-; X64-NEXT:    insertps $96, 4(%rdi), %xmm0
+; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1],mem[1],xmm0[3]
 ; X64-NEXT:    retq
-  %1 = load <4 x float>* %pb, align 16
+  %1 = load <4 x float>, <4 x float>* %pb, align 16
   %2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 96)
   ret <4 x float> %2
 }
@@ -851,16 +876,16 @@ define <4 x float> @insertps_from_vector_load_offset_2(<4 x float> %a, <4 x floa
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    shll $4, %ecx
-; X32-NEXT:    insertps $-64, 12(%eax,%ecx), %xmm0
+; X32-NEXT:    insertps {{.*#+}} xmm0 = mem[3],xmm0[1,2,3]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_from_vector_load_offset_2:
 ; X64:       ## BB#0:
 ; X64-NEXT:    shlq $4, %rsi
-; X64-NEXT:    insertps $-64, 12(%rdi,%rsi), %xmm0
+; X64-NEXT:    insertps {{.*#+}} xmm0 = mem[3],xmm0[1,2,3]
 ; X64-NEXT:    retq
-  %1 = getelementptr inbounds <4 x float>* %pb, i64 %index
-  %2 = load <4 x float>* %1, align 16
+  %1 = getelementptr inbounds <4 x float>, <4 x float>* %pb, i64 %index
+  %2 = load <4 x float>, <4 x float>* %1, align 16
   %3 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %2, i32 192)
   ret <4 x float> %3
 }
@@ -870,19 +895,19 @@ define <4 x float> @insertps_from_broadcast_loadf32(<4 x float> %a, float* nocap
 ; X32:       ## BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    movss (%ecx,%eax,4), %xmm1
+; X32-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; X32-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
 ; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_from_broadcast_loadf32:
 ; X64:       ## BB#0:
-; X64-NEXT:    movss (%rdi,%rsi,4), %xmm1
+; X64-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; X64-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
 ; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
 ; X64-NEXT:    retq
-  %1 = getelementptr inbounds float* %fb, i64 %index
-  %2 = load float* %1, align 4
+  %1 = getelementptr inbounds float, float* %fb, i64 %index
+  %2 = load float, float* %1, align 4
   %3 = insertelement <4 x float> undef, float %2, i32 0
   %4 = insertelement <4 x float> %3, float %2, i32 1
   %5 = insertelement <4 x float> %4, float %2, i32 2
@@ -906,7 +931,7 @@ define <4 x float> @insertps_from_broadcast_loadv4f32(<4 x float> %a, <4 x float
 ; X64-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
 ; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
 ; X64-NEXT:    retq
-  %1 = load <4 x float>* %b, align 4
+  %1 = load <4 x float>, <4 x float>* %b, align 4
   %2 = extractelement <4 x float> %1, i32 0
   %3 = insertelement <4 x float> undef, float %2, i32 0
   %4 = insertelement <4 x float> %3, float %2, i32 1
@@ -922,7 +947,7 @@ define <4 x float> @insertps_from_broadcast_multiple_use(<4 x float> %a, <4 x fl
 ; X32:       ## BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    movss (%ecx,%eax,4), %xmm4
+; X32-NEXT:    movss {{.*#+}} xmm4 = mem[0],zero,zero,zero
 ; X32-NEXT:    shufps {{.*#+}} xmm4 = xmm4[0,0,0,0]
 ; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0]
 ; X32-NEXT:    insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
@@ -935,7 +960,7 @@ define <4 x float> @insertps_from_broadcast_multiple_use(<4 x float> %a, <4 x fl
 ;
 ; X64-LABEL: insertps_from_broadcast_multiple_use:
 ; X64:       ## BB#0:
-; X64-NEXT:    movss (%rdi,%rsi,4), %xmm4
+; X64-NEXT:    movss {{.*#+}} xmm4 = mem[0],zero,zero,zero
 ; X64-NEXT:    shufps {{.*#+}} xmm4 = xmm4[0,0,0,0]
 ; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0]
 ; X64-NEXT:    insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
@@ -945,8 +970,8 @@ define <4 x float> @insertps_from_broadcast_multiple_use(<4 x float> %a, <4 x fl
 ; X64-NEXT:    addps %xmm2, %xmm3
 ; X64-NEXT:    addps %xmm3, %xmm0
 ; X64-NEXT:    retq
-  %1 = getelementptr inbounds float* %fb, i64 %index
-  %2 = load float* %1, align 4
+  %1 = getelementptr inbounds float, float* %fb, i64 %index
+  %2 = load float, float* %1, align 4
   %3 = insertelement <4 x float> undef, float %2, i32 0
   %4 = insertelement <4 x float> %3, float %2, i32 1
   %5 = insertelement <4 x float> %4, float %2, i32 2
@@ -965,18 +990,18 @@ define <4 x float> @insertps_with_undefs(<4 x float> %a, float* %b) {
 ; X32-LABEL: insertps_with_undefs:
 ; X32:       ## BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    movss (%eax), %xmm1
-; X32-NEXT:    insertps {{.*#+}} xmm1 = xmm1[0],zero,xmm0[0],xmm1[3]
-; X32-NEXT:    movaps %xmm1, %xmm0
+; X32-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; X32-NEXT:    movapd %xmm1, %xmm0
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_with_undefs:
 ; X64:       ## BB#0:
-; X64-NEXT:    movss (%rdi), %xmm1
-; X64-NEXT:    insertps {{.*#+}} xmm1 = xmm1[0],zero,xmm0[0],xmm1[3]
-; X64-NEXT:    movaps %xmm1, %xmm0
+; X64-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X64-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; X64-NEXT:    movapd %xmm1, %xmm0
 ; X64-NEXT:    retq
-  %1 = load float* %b, align 4
+  %1 = load float, float* %b, align 4
   %2 = insertelement <4 x float> undef, float %1, i32 0
   %result = shufflevector <4 x float> %a, <4 x float> %2, <4 x i32> <i32 4, i32 undef, i32 0, i32 7>
   ret <4 x float> %result
@@ -988,38 +1013,35 @@ define <4 x float> @pr20087(<4 x float> %a, <4 x float> *%ptr) {
 ; X32-LABEL: pr20087:
 ; X32:       ## BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    insertps $-78, 8(%eax), %xmm0
+; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],mem[2]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: pr20087:
 ; X64:       ## BB#0:
-; X64-NEXT:    insertps $-78, 8(%rdi), %xmm0
+; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],mem[2]
 ; X64-NEXT:    retq
-  %load = load <4 x float> *%ptr
+  %load = load <4 x float> , <4 x float> *%ptr
   %ret = shufflevector <4 x float> %load, <4 x float> %a, <4 x i32> <i32 4, i32 undef, i32 6, i32 2>
   ret <4 x float> %ret
 }
 
 ; Edge case for insertps where we end up with a shuffle with mask=<0, 7, -1, -1>
-define void @insertps_pr20411(i32* noalias nocapture %RET) #1 {
+define void @insertps_pr20411(<4 x i32> %shuffle109, <4 x i32> %shuffle116, i32* noalias nocapture %RET) #1 {
 ; X32-LABEL: insertps_pr20411:
 ; X32:       ## BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    pshufd {{.*#+}} xmm0 = mem[3,1,2,3]
-; X32-NEXT:    insertps $-36, LCPI49_1+12, %xmm0
-; X32-NEXT:    movups %xmm0, (%eax)
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; X32-NEXT:    pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
+; X32-NEXT:    movdqu %xmm1, (%eax)
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_pr20411:
 ; X64:       ## BB#0:
-; X64-NEXT:    pshufd {{.*#+}} xmm0 = mem[3,1,2,3]
-; X64-NEXT:    insertps $-36, LCPI49_1+{{.*}}(%rip), %xmm0
-; X64-NEXT:    movups %xmm0, (%rdi)
+; X64-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; X64-NEXT:    pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
+; X64-NEXT:    movdqu %xmm1, (%rdi)
 ; X64-NEXT:    retq
-  %gather_load = shufflevector <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, <8 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-  %shuffle109 = shufflevector <4 x i32> <i32 4, i32 5, i32 6, i32 7>, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>  ; 4 5 6 7
-  %shuffle116 = shufflevector <8 x i32> %gather_load, <8 x i32> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef> ; 3 x x x
-  %shuffle117 = shufflevector <4 x i32> %shuffle109, <4 x i32> %shuffle116, <4 x i32> <i32 4, i32 3, i32 undef, i32 undef> ; 3 7 x x
+  %shuffle117 = shufflevector <4 x i32> %shuffle109, <4 x i32> %shuffle116, <4 x i32> <i32 0, i32 7, i32 undef, i32 undef>
   %ptrcast = bitcast i32* %RET to <4 x i32>*
   store <4 x i32> %shuffle117, <4 x i32>* %ptrcast, align 4
   ret void
@@ -1027,12 +1049,12 @@ define void @insertps_pr20411(i32* noalias nocapture %RET) #1 {
 
 define <4 x float> @insertps_4(<4 x float> %A, <4 x float> %B) {
 ; X32-LABEL: insertps_4:
-; X32:       ## BB#0:
+; X32:       ## BB#0: ## %entry
 ; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_4:
-; X64:       ## BB#0:
+; X64:       ## BB#0: ## %entry
 ; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
 ; X64-NEXT:    retq
 entry:
@@ -1047,12 +1069,12 @@ entry:
 
 define <4 x float> @insertps_5(<4 x float> %A, <4 x float> %B) {
 ; X32-LABEL: insertps_5:
-; X32:       ## BB#0:
+; X32:       ## BB#0: ## %entry
 ; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],xmm1[1],zero,zero
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_5:
-; X64:       ## BB#0:
+; X64:       ## BB#0: ## %entry
 ; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],xmm1[1],zero,zero
 ; X64-NEXT:    retq
 entry:
@@ -1067,12 +1089,12 @@ entry:
 
 define <4 x float> @insertps_6(<4 x float> %A, <4 x float> %B) {
 ; X32-LABEL: insertps_6:
-; X32:       ## BB#0:
+; X32:       ## BB#0: ## %entry
 ; X32-NEXT:    insertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[2],zero
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_6:
-; X64:       ## BB#0:
+; X64:       ## BB#0: ## %entry
 ; X64-NEXT:    insertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[2],zero
 ; X64-NEXT:    retq
 entry:
@@ -1086,12 +1108,12 @@ entry:
 
 define <4 x float> @insertps_7(<4 x float> %A, <4 x float> %B) {
 ; X32-LABEL: insertps_7:
-; X32:       ## BB#0:
+; X32:       ## BB#0: ## %entry
 ; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[1],zero
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_7:
-; X64:       ## BB#0:
+; X64:       ## BB#0: ## %entry
 ; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[1],zero
 ; X64-NEXT:    retq
 entry:
@@ -1106,12 +1128,12 @@ entry:
 
 define <4 x float> @insertps_8(<4 x float> %A, <4 x float> %B) {
 ; X32-LABEL: insertps_8:
-; X32:       ## BB#0:
+; X32:       ## BB#0: ## %entry
 ; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_8:
-; X64:       ## BB#0:
+; X64:       ## BB#0: ## %entry
 ; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
 ; X64-NEXT:    retq
 entry:
@@ -1126,13 +1148,13 @@ entry:
 
 define <4 x float> @insertps_9(<4 x float> %A, <4 x float> %B) {
 ; X32-LABEL: insertps_9:
-; X32:       ## BB#0:
+; X32:       ## BB#0: ## %entry
 ; X32-NEXT:    insertps {{.*#+}} xmm1 = zero,xmm0[0],xmm1[2],zero
 ; X32-NEXT:    movaps %xmm1, %xmm0
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: insertps_9:
-; X64:       ## BB#0:
+; X64:       ## BB#0: ## %entry
 ; X64-NEXT:    insertps {{.*#+}} xmm1 = zero,xmm0[0],xmm1[2],zero
 ; X64-NEXT:    movaps %xmm1, %xmm0
 ; X64-NEXT:    retq
@@ -1146,7 +1168,6 @@ entry:
 }
 
 define <4 x float> @insertps_10(<4 x float> %A)
-{
 ; X32-LABEL: insertps_10:
 ; X32:       ## BB#0:
 ; X32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[0],zero
@@ -1156,6 +1177,7 @@ define <4 x float> @insertps_10(<4 x float> %A)
 ; X64:       ## BB#0:
 ; X64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[0],zero
 ; X64-NEXT:    retq
+{
   %vecext = extractelement <4 x float> %A, i32 0
   %vecbuild1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %vecext, i32 0
   %vecbuild2 = insertelement <4 x float> %vecbuild1, float %vecext, i32 2
@@ -1164,13 +1186,13 @@ define <4 x float> @insertps_10(<4 x float> %A)
 
 define <4 x float> @build_vector_to_shuffle_1(<4 x float> %A) {
 ; X32-LABEL: build_vector_to_shuffle_1:
-; X32:       ## BB#0:
+; X32:       ## BB#0: ## %entry
 ; X32-NEXT:    xorps %xmm1, %xmm1
 ; X32-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: build_vector_to_shuffle_1:
-; X64:       ## BB#0:
+; X64:       ## BB#0: ## %entry
 ; X64-NEXT:    xorps %xmm1, %xmm1
 ; X64-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
 ; X64-NEXT:    retq
@@ -1184,13 +1206,13 @@ entry:
 
 define <4 x float> @build_vector_to_shuffle_2(<4 x float> %A) {
 ; X32-LABEL: build_vector_to_shuffle_2:
-; X32:       ## BB#0:
+; X32:       ## BB#0: ## %entry
 ; X32-NEXT:    xorps %xmm1, %xmm1
 ; X32-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: build_vector_to_shuffle_2:
-; X64:       ## BB#0:
+; X64:       ## BB#0: ## %entry
 ; X64-NEXT:    xorps %xmm1, %xmm1
 ; X64-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
 ; X64-NEXT:    retq
diff --git a/test/CodeGen/X86/sse42-intrinsics-x86.ll b/test/CodeGen/X86/sse42-intrinsics-x86.ll
index 5ca800982827..706c86b71a4a 100644
--- a/test/CodeGen/X86/sse42-intrinsics-x86.ll
+++ b/test/CodeGen/X86/sse42-intrinsics-x86.ll
@@ -16,8 +16,8 @@ define i32 @test_x86_sse42_pcmpestri128_load(<16 x i8>* %a0, <16 x i8>* %a2) {
   ; CHECK: movl $7
   ; CHECK: pcmpestri $7, (
   ; CHECK: movl
-  %1 = load <16 x i8>* %a0
-  %2 = load <16 x i8>* %a2
+  %1 = load <16 x i8>, <16 x i8>* %a0
+  %2 = load <16 x i8>, <16 x i8>* %a2
   %res = call i32 @llvm.x86.sse42.pcmpestri128(<16 x i8> %1, i32 7, <16 x i8> %2, i32 7, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -94,7 +94,7 @@ define <16 x i8> @test_x86_sse42_pcmpestrm128_load(<16 x i8> %a0, <16 x i8>* %a2
   ; CHECK: movl $7
   ; CHECK: pcmpestrm $7,
   ; CHECK-NOT: vmov
-  %1 = load <16 x i8>* %a2
+  %1 = load <16 x i8>, <16 x i8>* %a2
   %res = call <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8> %a0, i32 7, <16 x i8> %1, i32 7, i8 7) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
@@ -112,8 +112,8 @@ declare i32 @llvm.x86.sse42.pcmpistri128(<16 x i8>, <16 x i8>, i8) nounwind read
 define i32 @test_x86_sse42_pcmpistri128_load(<16 x i8>* %a0, <16 x i8>* %a1) {
   ; CHECK: pcmpistri $7, (
   ; CHECK: movl
-  %1 = load <16 x i8>* %a0
-  %2 = load <16 x i8>* %a1
+  %1 = load <16 x i8>, <16 x i8>* %a0
+  %2 = load <16 x i8>, <16 x i8>* %a1
   %res = call i32 @llvm.x86.sse42.pcmpistri128(<16 x i8> %1, <16 x i8> %2, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
@@ -176,7 +176,7 @@ declare <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8>, <16 x i8>, i8) nounwin
 define <16 x i8> @test_x86_sse42_pcmpistrm128_load(<16 x i8> %a0, <16 x i8>* %a1) {
   ; CHECK: pcmpistrm $7, (
   ; CHECK-NOT: vmov
-  %1 = load <16 x i8>* %a1
+  %1 = load <16 x i8>, <16 x i8>* %a1
   %res = call <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8> %a0, <16 x i8> %1, i8 7) ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %res
 }
diff --git a/test/CodeGen/X86/sse4a.ll b/test/CodeGen/X86/sse4a.ll
index 165d47639d7a..f8fa125f98e7 100644
--- a/test/CodeGen/X86/sse4a.ll
+++ b/test/CodeGen/X86/sse4a.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4a | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-linux -mattr=sse4a | FileCheck %s
 
 define void @test1(i8* %p, <4 x float> %a) nounwind optsize ssp {
 ; CHECK-LABEL: test1:
diff --git a/test/CodeGen/X86/sse_partial_update.ll b/test/CodeGen/X86/sse_partial_update.ll
index a88ab014641b..377c3b7d6ead 100644
--- a/test/CodeGen/X86/sse_partial_update.ll
+++ b/test/CodeGen/X86/sse_partial_update.ll
@@ -12,7 +12,7 @@ entry:
 ; CHECK-LABEL: rsqrtss:
 ; CHECK: rsqrtss %xmm0, %xmm0
 ; CHECK-NEXT: cvtss2sd %xmm0
-; CHECK-NEXT: shufps
+; CHECK-NEXT: movshdup
 ; CHECK-NEXT: cvtss2sd %xmm0
 ; CHECK-NEXT: movap
 ; CHECK-NEXT: jmp
@@ -33,7 +33,7 @@ entry:
 ; CHECK-LABEL: rcpss:
 ; CHECK: rcpss %xmm0, %xmm0
 ; CHECK-NEXT: cvtss2sd %xmm0
-; CHECK-NEXT: shufps
+; CHECK-NEXT: movshdup
 ; CHECK-NEXT: cvtss2sd %xmm0
 ; CHECK-NEXT: movap
 ; CHECK-NEXT: jmp
@@ -53,7 +53,7 @@ entry:
 ; CHECK-LABEL: sqrtss:
 ; CHECK: sqrtss %xmm0, %xmm0
 ; CHECK-NEXT: cvtss2sd %xmm0
-; CHECK-NEXT: shufps
+; CHECK-NEXT: movshdup
 ; CHECK-NEXT: cvtss2sd %xmm0
 ; CHECK-NEXT: movap
 ; CHECK-NEXT: jmp
@@ -67,3 +67,26 @@ entry:
   ret void
 }
 declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
+
+define void @sqrtsd(<2 x double> %a) nounwind uwtable ssp {
+entry:
+; CHECK-LABEL: sqrtsd:
+; CHECK: sqrtsd %xmm0, %xmm0
+; CHECK-NEXT: cvtsd2ss %xmm0
+; CHECK-NEXT: shufpd
+; CHECK-NEXT: cvtsd2ss %xmm0
+; CHECK-NEXT: movap
+; CHECK-NEXT: jmp
+
+ %0 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a) nounwind
+ %a0 = extractelement <2 x double> %0, i32 0
+ %conv = fptrunc double %a0 to float
+ %a1 = extractelement <2 x double> %0, i32 1
+ %conv3 = fptrunc double %a1 to float
+ tail call void @callee2(float %conv, float %conv3) nounwind
+ ret void
+}
+
+declare void @callee2(float, float)
+declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
+
diff --git a/test/CodeGen/X86/ssp-data-layout.ll b/test/CodeGen/X86/ssp-data-layout.ll
index e76ad7b871ba..4a63aceb7ccf 100644
--- a/test/CodeGen/X86/ssp-data-layout.ll
+++ b/test/CodeGen/X86/ssp-data-layout.ll
@@ -114,57 +114,57 @@ entry:
   store i32 %call3, i32* %ptr, align 4
   call void @end_addrof()
   %call4 = call signext i16 @get_small_nonchar()
-  %arrayidx = getelementptr inbounds [2 x i16]* %small2, i32 0, i64 0
+  %arrayidx = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i64 0
   store i16 %call4, i16* %arrayidx, align 2
   call void @end_small_nonchar()
   %call5 = call i32 @get_large_nonchar()
-  %arrayidx6 = getelementptr inbounds [8 x i32]* %large2, i32 0, i64 0
+  %arrayidx6 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i64 0
   store i32 %call5, i32* %arrayidx6, align 4
   call void @end_large_nonchar()
   %call7 = call signext i8 @get_small_char()
-  %arrayidx8 = getelementptr inbounds [2 x i8]* %small, i32 0, i64 0
+  %arrayidx8 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i64 0
   store i8 %call7, i8* %arrayidx8, align 1
   call void @end_small_char()
   %call9 = call signext i8 @get_large_char()
-  %arrayidx10 = getelementptr inbounds [8 x i8]* %large, i32 0, i64 0
+  %arrayidx10 = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i64 0
   store i8 %call9, i8* %arrayidx10, align 1
   call void @end_large_char()
   %call11 = call signext i8 @get_struct_large_char()
-  %foo = getelementptr inbounds %struct.struct_large_char* %a, i32 0, i32 0
-  %arrayidx12 = getelementptr inbounds [8 x i8]* %foo, i32 0, i64 0
+  %foo = getelementptr inbounds %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
+  %arrayidx12 = getelementptr inbounds [8 x i8], [8 x i8]* %foo, i32 0, i64 0
   store i8 %call11, i8* %arrayidx12, align 1
   call void @end_struct_large_char()
   %call13 = call signext i8 @get_struct_small_char()
-  %foo14 = getelementptr inbounds %struct.struct_small_char* %b, i32 0, i32 0
-  %arrayidx15 = getelementptr inbounds [2 x i8]* %foo14, i32 0, i64 0
+  %foo14 = getelementptr inbounds %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
+  %arrayidx15 = getelementptr inbounds [2 x i8], [2 x i8]* %foo14, i32 0, i64 0
   store i8 %call13, i8* %arrayidx15, align 1
   call void @end_struct_small_char()
   %call16 = call i32 @get_struct_large_nonchar()
-  %foo17 = getelementptr inbounds %struct.struct_large_nonchar* %c, i32 0, i32 0
-  %arrayidx18 = getelementptr inbounds [8 x i32]* %foo17, i32 0, i64 0
+  %foo17 = getelementptr inbounds %struct.struct_large_nonchar, %struct.struct_large_nonchar* %c, i32 0, i32 0
+  %arrayidx18 = getelementptr inbounds [8 x i32], [8 x i32]* %foo17, i32 0, i64 0
   store i32 %call16, i32* %arrayidx18, align 4
   call void @end_struct_large_nonchar()
   %call19 = call signext i16 @get_struct_small_nonchar()
-  %foo20 = getelementptr inbounds %struct.struct_small_nonchar* %d, i32 0, i32 0
-  %arrayidx21 = getelementptr inbounds [2 x i16]* %foo20, i32 0, i64 0
+  %foo20 = getelementptr inbounds %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
+  %arrayidx21 = getelementptr inbounds [2 x i16], [2 x i16]* %foo20, i32 0, i64 0
   store i16 %call19, i16* %arrayidx21, align 2
   call void @end_struct_small_nonchar()
-  %arraydecay = getelementptr inbounds [8 x i8]* %large, i32 0, i32 0
-  %arraydecay22 = getelementptr inbounds [2 x i8]* %small, i32 0, i32 0
-  %arraydecay23 = getelementptr inbounds [8 x i32]* %large2, i32 0, i32 0
-  %arraydecay24 = getelementptr inbounds [2 x i16]* %small2, i32 0, i32 0
-  %0 = load i32* %x, align 4
-  %1 = load i32* %y, align 4
-  %2 = load i32* %z, align 4
-  %coerce.dive = getelementptr %struct.struct_large_char* %a, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i32 0
+  %arraydecay22 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i32 0
+  %arraydecay23 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i32 0
+  %arraydecay24 = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i32 0
+  %0 = load i32, i32* %x, align 4
+  %1 = load i32, i32* %y, align 4
+  %2 = load i32, i32* %z, align 4
+  %coerce.dive = getelementptr %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
   %3 = bitcast [8 x i8]* %coerce.dive to i64*
-  %4 = load i64* %3, align 1
-  %coerce.dive25 = getelementptr %struct.struct_small_char* %b, i32 0, i32 0
+  %4 = load i64, i64* %3, align 1
+  %coerce.dive25 = getelementptr %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
   %5 = bitcast [2 x i8]* %coerce.dive25 to i16*
-  %6 = load i16* %5, align 1
-  %coerce.dive26 = getelementptr %struct.struct_small_nonchar* %d, i32 0, i32 0
+  %6 = load i16, i16* %5, align 1
+  %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
   %7 = bitcast [2 x i16]* %coerce.dive26 to i32*
-  %8 = load i32* %7, align 1
+  %8 = load i32, i32* %7, align 1
   call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
   ret void
 }
@@ -258,57 +258,57 @@ entry:
   store i32 %call3, i32* %ptr, align 4
   call void @end_addrof()
   %call4 = call signext i16 @get_small_nonchar()
-  %arrayidx = getelementptr inbounds [2 x i16]* %small2, i32 0, i64 0
+  %arrayidx = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i64 0
   store i16 %call4, i16* %arrayidx, align 2
   call void @end_small_nonchar()
   %call5 = call i32 @get_large_nonchar()
-  %arrayidx6 = getelementptr inbounds [8 x i32]* %large2, i32 0, i64 0
+  %arrayidx6 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i64 0
   store i32 %call5, i32* %arrayidx6, align 4
   call void @end_large_nonchar()
   %call7 = call signext i8 @get_small_char()
-  %arrayidx8 = getelementptr inbounds [2 x i8]* %small, i32 0, i64 0
+  %arrayidx8 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i64 0
   store i8 %call7, i8* %arrayidx8, align 1
   call void @end_small_char()
   %call9 = call signext i8 @get_large_char()
-  %arrayidx10 = getelementptr inbounds [8 x i8]* %large, i32 0, i64 0
+  %arrayidx10 = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i64 0
   store i8 %call9, i8* %arrayidx10, align 1
   call void @end_large_char()
   %call11 = call signext i8 @get_struct_large_char()
-  %foo = getelementptr inbounds %struct.struct_large_char* %a, i32 0, i32 0
-  %arrayidx12 = getelementptr inbounds [8 x i8]* %foo, i32 0, i64 0
+  %foo = getelementptr inbounds %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
+  %arrayidx12 = getelementptr inbounds [8 x i8], [8 x i8]* %foo, i32 0, i64 0
   store i8 %call11, i8* %arrayidx12, align 1
   call void @end_struct_large_char()
   %call13 = call signext i8 @get_struct_small_char()
-  %foo14 = getelementptr inbounds %struct.struct_small_char* %b, i32 0, i32 0
-  %arrayidx15 = getelementptr inbounds [2 x i8]* %foo14, i32 0, i64 0
+  %foo14 = getelementptr inbounds %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
+  %arrayidx15 = getelementptr inbounds [2 x i8], [2 x i8]* %foo14, i32 0, i64 0
   store i8 %call13, i8* %arrayidx15, align 1
   call void @end_struct_small_char()
   %call16 = call i32 @get_struct_large_nonchar()
-  %foo17 = getelementptr inbounds %struct.struct_large_nonchar* %c, i32 0, i32 0
-  %arrayidx18 = getelementptr inbounds [8 x i32]* %foo17, i32 0, i64 0
+  %foo17 = getelementptr inbounds %struct.struct_large_nonchar, %struct.struct_large_nonchar* %c, i32 0, i32 0
+  %arrayidx18 = getelementptr inbounds [8 x i32], [8 x i32]* %foo17, i32 0, i64 0
   store i32 %call16, i32* %arrayidx18, align 4
   call void @end_struct_large_nonchar()
   %call19 = call signext i16 @get_struct_small_nonchar()
-  %foo20 = getelementptr inbounds %struct.struct_small_nonchar* %d, i32 0, i32 0
-  %arrayidx21 = getelementptr inbounds [2 x i16]* %foo20, i32 0, i64 0
+  %foo20 = getelementptr inbounds %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
+  %arrayidx21 = getelementptr inbounds [2 x i16], [2 x i16]* %foo20, i32 0, i64 0
   store i16 %call19, i16* %arrayidx21, align 2
   call void @end_struct_small_nonchar()
-  %arraydecay = getelementptr inbounds [8 x i8]* %large, i32 0, i32 0
-  %arraydecay22 = getelementptr inbounds [2 x i8]* %small, i32 0, i32 0
-  %arraydecay23 = getelementptr inbounds [8 x i32]* %large2, i32 0, i32 0
-  %arraydecay24 = getelementptr inbounds [2 x i16]* %small2, i32 0, i32 0
-  %0 = load i32* %x, align 4
-  %1 = load i32* %y, align 4
-  %2 = load i32* %z, align 4
-  %coerce.dive = getelementptr %struct.struct_large_char* %a, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i32 0
+  %arraydecay22 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i32 0
+  %arraydecay23 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i32 0
+  %arraydecay24 = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i32 0
+  %0 = load i32, i32* %x, align 4
+  %1 = load i32, i32* %y, align 4
+  %2 = load i32, i32* %z, align 4
+  %coerce.dive = getelementptr %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
   %3 = bitcast [8 x i8]* %coerce.dive to i64*
-  %4 = load i64* %3, align 1
-  %coerce.dive25 = getelementptr %struct.struct_small_char* %b, i32 0, i32 0
+  %4 = load i64, i64* %3, align 1
+  %coerce.dive25 = getelementptr %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
   %5 = bitcast [2 x i8]* %coerce.dive25 to i16*
-  %6 = load i16* %5, align 1
-  %coerce.dive26 = getelementptr %struct.struct_small_nonchar* %d, i32 0, i32 0
+  %6 = load i16, i16* %5, align 1
+  %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
   %7 = bitcast [2 x i16]* %coerce.dive26 to i32*
-  %8 = load i32* %7, align 1
+  %8 = load i32, i32* %7, align 1
   call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
   ret void
 }
@@ -390,57 +390,57 @@ entry:
   store i32 %call3, i32* %ptr, align 4
   call void @end_addrof()
   %call4 = call signext i16 @get_small_nonchar()
-  %arrayidx = getelementptr inbounds [2 x i16]* %small2, i32 0, i64 0
+  %arrayidx = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i64 0
   store i16 %call4, i16* %arrayidx, align 2
   call void @end_small_nonchar()
   %call5 = call i32 @get_large_nonchar()
-  %arrayidx6 = getelementptr inbounds [8 x i32]* %large2, i32 0, i64 0
+  %arrayidx6 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i64 0
   store i32 %call5, i32* %arrayidx6, align 4
   call void @end_large_nonchar()
   %call7 = call signext i8 @get_small_char()
-  %arrayidx8 = getelementptr inbounds [2 x i8]* %small, i32 0, i64 0
+  %arrayidx8 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i64 0
   store i8 %call7, i8* %arrayidx8, align 1
   call void @end_small_char()
   %call9 = call signext i8 @get_large_char()
-  %arrayidx10 = getelementptr inbounds [8 x i8]* %large, i32 0, i64 0
+  %arrayidx10 = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i64 0
   store i8 %call9, i8* %arrayidx10, align 1
   call void @end_large_char()
   %call11 = call signext i8 @get_struct_large_char()
-  %foo = getelementptr inbounds %struct.struct_large_char* %a, i32 0, i32 0
-  %arrayidx12 = getelementptr inbounds [8 x i8]* %foo, i32 0, i64 0
+  %foo = getelementptr inbounds %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
+  %arrayidx12 = getelementptr inbounds [8 x i8], [8 x i8]* %foo, i32 0, i64 0
   store i8 %call11, i8* %arrayidx12, align 1
   call void @end_struct_large_char()
   %call13 = call signext i8 @get_struct_small_char()
-  %foo14 = getelementptr inbounds %struct.struct_small_char* %b, i32 0, i32 0
-  %arrayidx15 = getelementptr inbounds [2 x i8]* %foo14, i32 0, i64 0
+  %foo14 = getelementptr inbounds %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
+  %arrayidx15 = getelementptr inbounds [2 x i8], [2 x i8]* %foo14, i32 0, i64 0
   store i8 %call13, i8* %arrayidx15, align 1
   call void @end_struct_small_char()
   %call16 = call i32 @get_struct_large_nonchar()
-  %foo17 = getelementptr inbounds %struct.struct_large_nonchar* %c, i32 0, i32 0
-  %arrayidx18 = getelementptr inbounds [8 x i32]* %foo17, i32 0, i64 0
+  %foo17 = getelementptr inbounds %struct.struct_large_nonchar, %struct.struct_large_nonchar* %c, i32 0, i32 0
+  %arrayidx18 = getelementptr inbounds [8 x i32], [8 x i32]* %foo17, i32 0, i64 0
   store i32 %call16, i32* %arrayidx18, align 4
   call void @end_struct_large_nonchar()
   %call19 = call signext i16 @get_struct_small_nonchar()
-  %foo20 = getelementptr inbounds %struct.struct_small_nonchar* %d, i32 0, i32 0
-  %arrayidx21 = getelementptr inbounds [2 x i16]* %foo20, i32 0, i64 0
+  %foo20 = getelementptr inbounds %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
+  %arrayidx21 = getelementptr inbounds [2 x i16], [2 x i16]* %foo20, i32 0, i64 0
   store i16 %call19, i16* %arrayidx21, align 2
   call void @end_struct_small_nonchar()
-  %arraydecay = getelementptr inbounds [8 x i8]* %large, i32 0, i32 0
-  %arraydecay22 = getelementptr inbounds [2 x i8]* %small, i32 0, i32 0
-  %arraydecay23 = getelementptr inbounds [8 x i32]* %large2, i32 0, i32 0
-  %arraydecay24 = getelementptr inbounds [2 x i16]* %small2, i32 0, i32 0
-  %0 = load i32* %x, align 4
-  %1 = load i32* %y, align 4
-  %2 = load i32* %z, align 4
-  %coerce.dive = getelementptr %struct.struct_large_char* %a, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i32 0
+  %arraydecay22 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i32 0
+  %arraydecay23 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i32 0
+  %arraydecay24 = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i32 0
+  %0 = load i32, i32* %x, align 4
+  %1 = load i32, i32* %y, align 4
+  %2 = load i32, i32* %z, align 4
+  %coerce.dive = getelementptr %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
   %3 = bitcast [8 x i8]* %coerce.dive to i64*
-  %4 = load i64* %3, align 1
-  %coerce.dive25 = getelementptr %struct.struct_small_char* %b, i32 0, i32 0
+  %4 = load i64, i64* %3, align 1
+  %coerce.dive25 = getelementptr %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
   %5 = bitcast [2 x i8]* %coerce.dive25 to i16*
-  %6 = load i16* %5, align 1
-  %coerce.dive26 = getelementptr %struct.struct_small_nonchar* %d, i32 0, i32 0
+  %6 = load i16, i16* %5, align 1
+  %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
   %7 = bitcast [2 x i16]* %coerce.dive26 to i32*
-  %8 = load i32* %7, align 1
+  %8 = load i32, i32* %7, align 1
   call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
   ret void
 }
@@ -461,11 +461,11 @@ entry:
   store i32 %call, i32* %x, align 4
   call void @end_scalar1()
   %call1 = call signext i8 @get_large_char()
-  %arrayidx = getelementptr inbounds [8 x i8]* %large, i32 0, i64 0
+  %arrayidx = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i64 0
   store i8 %call1, i8* %arrayidx, align 1
   call void @end_large_char()
-  %0 = load i32* %x, align 4
-  %arraydecay = getelementptr inbounds [8 x i8]* %large, i32 0, i32 0
+  %0 = load i32, i32* %x, align 4
+  %arraydecay = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i32 0
   call void @takes_two(i32 %0, i8* %arraydecay)
   ret void
 }
diff --git a/test/CodeGen/X86/stack-align.ll b/test/CodeGen/X86/stack-align.ll
index eafb7c29fa0a..0cff95f266a9 100644
--- a/test/CodeGen/X86/stack-align.ll
+++ b/test/CodeGen/X86/stack-align.ll
@@ -1,7 +1,10 @@
 ; RUN: llc < %s -relocation-model=static -mcpu=yonah | FileCheck %s
 
-; The double argument is at 4(esp) which is 16-byte aligned, allowing us to
-; fold the load into the andpd.
+; The double argument is at 4(esp) which is 16-byte aligned, but we
+; are required to read in extra bytes of memory in order to fold the
+; load. Bad Things may happen when reading/processing undefined bytes,
+; so don't fold the load.
+; PR22371 / http://reviews.llvm.org/D7474
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i686-apple-darwin8"
@@ -9,28 +12,37 @@ target triple = "i686-apple-darwin8"
 
 define void @test({ double, double }* byval  %z, double* %P) nounwind {
 entry:
-	%tmp3 = load double* @G, align 16		; <double> [#uses=1]
+	%tmp3 = load double, double* @G, align 16		; <double> [#uses=1]
 	%tmp4 = tail call double @fabs( double %tmp3 ) readnone	; <double> [#uses=1]
         store volatile double %tmp4, double* %P
-	%tmp = getelementptr { double, double }* %z, i32 0, i32 0		; <double*> [#uses=1]
-	%tmp1 = load volatile double* %tmp, align 8		; <double> [#uses=1]
+	%tmp = getelementptr { double, double }, { double, double }* %z, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp1 = load volatile double, double* %tmp, align 8		; <double> [#uses=1]
 	%tmp2 = tail call double @fabs( double %tmp1 ) readnone	; <double> [#uses=1]
-    ; CHECK: andpd{{.*}}4(%esp), %xmm
 	%tmp6 = fadd double %tmp4, %tmp2		; <double> [#uses=1]
 	store volatile double %tmp6, double* %P, align 8
 	ret void
+
+; CHECK-LABEL: test:
+; CHECK:       movsd	{{.*}}G, %xmm{{.*}}
+; CHECK:       andpd	%xmm{{.*}}, %xmm{{.*}}
+; CHECK:       movsd	4(%esp), %xmm{{.*}}
+; CHECK:       andpd	%xmm{{.*}}, %xmm{{.*}}
+
+
 }
 
 define void @test2() alignstack(16) nounwind {
 entry:
-    ; CHECK: andl{{.*}}$-16, %esp
+; CHECK-LABEL: test2:
+; CHECK: andl{{.*}}$-16, %esp
     ret void
 }
 
 ; Use a call to force a spill.
 define <2 x double> @test3(<2 x double> %x, <2 x double> %y) alignstack(32) nounwind {
 entry:
-    ; CHECK: andl{{.*}}$-32, %esp
+; CHECK-LABEL: test3:
+; CHECK: andl{{.*}}$-32, %esp
     call void @test2()
     %A = fmul <2 x double> %x, %y
     ret <2 x double> %A
diff --git a/test/CodeGen/X86/stack-folding-3dnow.ll b/test/CodeGen/X86/stack-folding-3dnow.ll
new file mode 100644
index 000000000000..955bf44999cb
--- /dev/null
+++ b/test/CodeGen/X86/stack-folding-3dnow.ll
@@ -0,0 +1,217 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+3dnow | FileCheck %s
+
+define x86_mmx @stack_fold_pavgusb(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pavgusb
+  ;CHECK:       pavgusb {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pf2id(x86_mmx %a) {
+  ;CHECK-LABEL: stack_fold_pf2id
+  ;CHECK:       pf2id {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm1},~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx %a) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pf2iw(x86_mmx %a) {
+  ;CHECK-LABEL: stack_fold_pf2iw
+  ;CHECK:       pf2iw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm1},~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnowa.pf2iw(x86_mmx %a) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnowa.pf2iw(x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfacc(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pfacc
+  ;CHECK:       pfacc {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pfacc(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pfacc(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfadd(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pfadd
+  ;CHECK:       pfadd {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pfadd(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pfadd(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfcmpeq(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pfcmpeq
+  ;CHECK:       pfcmpeq {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pfcmpeq(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pfcmpeq(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfcmpge(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pfcmpge
+  ;CHECK:       pfcmpge {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pfcmpge(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pfcmpge(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfcmpgt(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pfcmpgt
+  ;CHECK:       pfcmpgt {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pfcmpgt(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pfcmpgt(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfmax(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pfmax
+  ;CHECK:       pfmax {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pfmax(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pfmax(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfmin(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pfmin
+  ;CHECK:       pfmin {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pfmin(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pfmin(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfmul(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pfmul
+  ;CHECK:       pfmul {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pfmul(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pfmul(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfnacc(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pfnacc
+  ;CHECK:       pfnacc {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnowa.pfnacc(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnowa.pfnacc(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfpnacc(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pfpnacc
+  ;CHECK:       pfpnacc {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnowa.pfpnacc(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnowa.pfpnacc(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfrcp(x86_mmx %a) {
+  ;CHECK-LABEL: stack_fold_pfrcp
+  ;CHECK:       pfrcp {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm1},~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pfrcp(x86_mmx %a) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pfrcp(x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfrcpit1(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pfrcpit1
+  ;CHECK:       pfrcpit1 {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pfrcpit1(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pfrcpit1(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfrcpit2(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pfrcpit2
+  ;CHECK:       pfrcpit2 {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pfrcpit2(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pfrcpit2(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfrsqit1(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pfrsqit1
+  ;CHECK:       pfrsqit1 {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pfrsqit1(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pfrsqit1(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfrsqrt(x86_mmx %a) {
+  ;CHECK-LABEL: stack_fold_pfrsqrt
+  ;CHECK:       pfrsqrt {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm1},~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pfrsqrt(x86_mmx %a) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pfrsqrt(x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfsub(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pfsub
+  ;CHECK:       pfsub {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pfsub(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pfsub(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pfsubr(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pfsubr
+  ;CHECK:       pfsubr {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pfsubr(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pfsubr(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pi2fd(x86_mmx %a) {
+  ;CHECK-LABEL: stack_fold_pi2fd
+  ;CHECK:       pi2fd {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm1},~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pi2fd(x86_mmx %a) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pi2fd(x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pi2fw(x86_mmx %a) {
+  ;CHECK-LABEL: stack_fold_pi2fw
+  ;CHECK:       pi2fw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm1},~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnowa.pi2fw(x86_mmx %a) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnowa.pi2fw(x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pmulhrw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pmulhrw
+  ;CHECK:       pmulhrw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnow.pmulhrw(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnow.pmulhrw(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pswapd(x86_mmx %a) {
+  ;CHECK-LABEL: stack_fold_pswapd
+  ;CHECK:       pswapd {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm1},~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.3dnowa.pswapd(x86_mmx %a) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.3dnowa.pswapd(x86_mmx) nounwind readnone
diff --git a/test/CodeGen/X86/stack-folding-fp-avx1.ll b/test/CodeGen/X86/stack-folding-fp-avx1.ll
new file mode 100644
index 000000000000..c7c1fc946386
--- /dev/null
+++ b/test/CodeGen/X86/stack-folding-fp-avx1.ll
@@ -0,0 +1,1827 @@
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx,+f16c < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-unknown"
+
+; Stack reload folding tests.
+;
+; By including a nop call with sideeffects we can force a partial register spill of the
+; relevant registers and check that the reload is correctly folded into the instruction.
+
+define <2 x double> @stack_fold_addpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_addpd
+  ;CHECK:       vaddpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fadd <2 x double> %a0, %a1
+  ret <2 x double> %2
+}
+
+define <4 x double> @stack_fold_addpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_addpd_ymm
+  ;CHECK:       vaddpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fadd <4 x double> %a0, %a1
+  ret <4 x double> %2
+}
+
+define <4 x float> @stack_fold_addps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_addps
+  ;CHECK:       vaddps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fadd <4 x float> %a0, %a1
+  ret <4 x float> %2
+}
+
+define <8 x float> @stack_fold_addps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_addps_ymm
+  ;CHECK:       vaddps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fadd <8 x float> %a0, %a1
+  ret <8 x float> %2
+}
+
+define double @stack_fold_addsd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_addsd
+  ;CHECK:       vaddsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fadd double %a0, %a1
+  ret double %2
+}
+
+define <2 x double> @stack_fold_addsd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_addsd_int
+  ;CHECK:       vaddsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.add.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define float @stack_fold_addss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_addss
+  ;CHECK:       vaddss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fadd float %a0, %a1
+  ret float %2
+}
+
+define <4 x float> @stack_fold_addss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_addss_int
+  ;CHECK:       vaddss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.add.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_addsubpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_addsubpd
+  ;CHECK:       vaddsubpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone
+
+define <4 x double> @stack_fold_addsubpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_addsubpd_ymm
+  ;CHECK:       vaddsubpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %a0, <4 x double> %a1)
+  ret <4 x double> %2
+}
+declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_addsubps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_addsubps
+  ;CHECK:       vaddsubps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone
+
+define <8 x float> @stack_fold_addsubps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_addsubps_ymm
+  ;CHECK:       vaddsubps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %a0, <8 x float> %a1)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_andnpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_andnpd
+  ;CHECK:       vandnpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <2 x double> %a0 to <2 x i64>
+  %3 = bitcast <2 x double> %a1 to <2 x i64>
+  %4 = xor <2 x i64> %2, <i64 -1, i64 -1>
+  %5 = and <2 x i64> %4, %3
+  %6 = bitcast <2 x i64> %5 to <2 x double>
+  ; fadd forces execution domain
+  %7 = fadd <2 x double> %6, <double 0x0, double 0x0>
+  ret <2 x double> %7
+}
+
+define <4 x double> @stack_fold_andnpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_andnpd_ymm
+  ;CHECK:       vandnpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <4 x double> %a0 to <4 x i64>
+  %3 = bitcast <4 x double> %a1 to <4 x i64>
+  %4 = xor <4 x i64> %2, <i64 -1, i64 -1, i64 -1, i64 -1>
+  %5 = and <4 x i64> %4, %3
+  %6 = bitcast <4 x i64> %5 to <4 x double>
+  ; fadd forces execution domain
+  %7 = fadd <4 x double> %6, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %7
+}
+
+define <4 x float> @stack_fold_andnps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_andnps
+  ;CHECK:       vandnps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <4 x float> %a0 to <2 x i64>
+  %3 = bitcast <4 x float> %a1 to <2 x i64>
+  %4 = xor <2 x i64> %2, <i64 -1, i64 -1>
+  %5 = and <2 x i64> %4, %3
+  %6 = bitcast <2 x i64> %5 to <4 x float>
+  ; fadd forces execution domain
+  %7 = fadd <4 x float> %6, <float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <4 x float> %7
+}
+
+define <8 x float> @stack_fold_andnps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_andnps_ymm
+  ;CHECK:       vandnps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <8 x float> %a0 to <4 x i64>
+  %3 = bitcast <8 x float> %a1 to <4 x i64>
+  %4 = xor <4 x i64> %2, <i64 -1, i64 -1, i64 -1, i64 -1>
+  %5 = and <4 x i64> %4, %3
+  %6 = bitcast <4 x i64> %5 to <8 x float>
+  ; fadd forces execution domain
+  %7 = fadd <8 x float> %6, <float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <8 x float> %7
+}
+
+define <2 x double> @stack_fold_andpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_andpd
+  ;CHECK:       vandpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <2 x double> %a0 to <2 x i64>
+  %3 = bitcast <2 x double> %a1 to <2 x i64>
+  %4 = and <2 x i64> %2, %3
+  %5 = bitcast <2 x i64> %4 to <2 x double>
+  ; fadd forces execution domain
+  %6 = fadd <2 x double> %5, <double 0x0, double 0x0>
+  ret <2 x double> %6
+}
+
+define <4 x double> @stack_fold_andpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_andpd_ymm
+  ;CHECK:       vandpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <4 x double> %a0 to <4 x i64>
+  %3 = bitcast <4 x double> %a1 to <4 x i64>
+  %4 = and <4 x i64> %2, %3
+  %5 = bitcast <4 x i64> %4 to <4 x double>
+  ; fadd forces execution domain
+  %6 = fadd <4 x double> %5, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %6
+}
+
+define <4 x float> @stack_fold_andps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_andps
+  ;CHECK:       vandps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <4 x float> %a0 to <2 x i64>
+  %3 = bitcast <4 x float> %a1 to <2 x i64>
+  %4 = and <2 x i64> %2, %3
+  %5 = bitcast <2 x i64> %4 to <4 x float>
+  ; fadd forces execution domain
+  %6 = fadd <4 x float> %5, <float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <4 x float> %6
+}
+
+define <8 x float> @stack_fold_andps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_andps_ymm
+  ;CHECK:       vandps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <8 x float> %a0 to <4 x i64>
+  %3 = bitcast <8 x float> %a1 to <4 x i64>
+  %4 = and <4 x i64> %2, %3
+  %5 = bitcast <4 x i64> %4 to <8 x float>
+  ; fadd forces execution domain
+  %6 = fadd <8 x float> %5, <float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <8 x float> %6
+}
+
+define <2 x double> @stack_fold_blendpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_blendpd
+  ;CHECK:       vblendpd $2, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = select <2 x i1> <i1 1, i1 0>, <2 x double> %a0, <2 x double> %a1
+  ret <2 x double> %2
+}
+
+define <4 x double> @stack_fold_blendpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_blendpd_ymm
+  ;CHECK:       vblendpd $6, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = select <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x double> %a0, <4 x double> %a1
+  ret <4 x double> %2
+}
+
+define <4 x float> @stack_fold_blendps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_blendps
+  ;CHECK:       vblendps $6, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = select <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x float> %a0, <4 x float> %a1
+  ret <4 x float> %2
+}
+
+define <8 x float> @stack_fold_blendps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_blendps_ymm
+  ;CHECK:       vblendps $102, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = select <8 x i1> <i1 1, i1 0, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1>, <8 x float> %a0, <8 x float> %a1
+  ret <8 x float> %2
+}
+
+define <2 x double> @stack_fold_blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %c) {
+  ;CHECK-LABEL: stack_fold_blendvpd
+  ;CHECK:       vblendvpd {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse41.blendvpd(<2 x double> %a1, <2 x double> %c, <2 x double> %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse41.blendvpd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone
+
+define <4 x double> @stack_fold_blendvpd_ymm(<4 x double> %a0, <4 x double> %a1, <4 x double> %c) {
+  ;CHECK-LABEL: stack_fold_blendvpd_ymm
+  ;CHECK:       vblendvpd {{%ymm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %a1, <4 x double> %c, <4 x double> %a0)
+  ret <4 x double> %2
+}
+declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> %c) {
+  ;CHECK-LABEL: stack_fold_blendvps
+  ;CHECK:       vblendvps {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %a1, <4 x float> %c, <4 x float> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
+
+define <8 x float> @stack_fold_blendvps_ymm(<8 x float> %a0, <8 x float> %a1, <8 x float> %c) {
+  ;CHECK-LABEL: stack_fold_blendvps_ymm
+  ;CHECK:       vblendvps {{%ymm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %a1, <8 x float> %c, <8 x float> %a0)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_cmppd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_cmppd
+  ;CHECK:       vcmpeqpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> %a0, <2 x double> %a1, i8 0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double>, <2 x double>, i8) nounwind readnone
+
+define <4 x double> @stack_fold_cmppd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_cmppd_ymm
+  ;CHECK:       vcmpeqpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> %a0, <4 x double> %a1, i8 0)
+  ret <4 x double> %2
+}
+declare <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone
+
+define <4 x float> @stack_fold_cmpps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_cmpps
+  ;CHECK:       vcmpeqps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %a0, <4 x float> %a1, i8 0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone
+
+define <8 x float> @stack_fold_cmpps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_cmpps_ymm
+  ;CHECK:       vcmpeqps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 0)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone
+
+define i32 @stack_fold_cmpsd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_cmpsd
+  ;CHECK:       vcmpeqsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp oeq double %a0, %a1
+  %3 = zext i1 %2 to i32
+  ret i32 %3
+}
+
+define <2 x double> @stack_fold_cmpsd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_cmpsd_int
+  ;CHECK:       vcmpeqsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a0, <2 x double> %a1, i8 0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounwind readnone
+
+define i32 @stack_fold_cmpss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_cmpss
+  ;CHECK:       vcmpeqss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp oeq float %a0, %a1
+  %3 = zext i1 %2 to i32
+  ret i32 %3
+}
+
+define <4 x float> @stack_fold_cmpss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_cmpss_int
+  ;CHECK:       vcmpeqss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %a0, <4 x float> %a1, i8 0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8) nounwind readnone
+
+; TODO stack_fold_comisd
+
+define i32 @stack_fold_comisd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_comisd_int
+  ;CHECK:       vcomisd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readnone
+
+; TODO stack_fold_comiss
+
+define i32 @stack_fold_comiss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_comiss_int
+  ;CHECK:       vcomiss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse.comieq.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_cvtdq2pd(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtdq2pd
+  ;CHECK:   vcvtdq2pd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32> %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32>) nounwind readnone
+
+define <4 x double> @stack_fold_cvtdq2pd_ymm(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtdq2pd_ymm
+  ;CHECK:   vcvtdq2pd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32> %a0)
+  ret <4 x double> %2
+}
+declare <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32>) nounwind readnone
+
+define <4 x float> @stack_fold_cvtdq2ps(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtdq2ps
+  ;CHECK:   vcvtdq2ps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = sitofp <4 x i32> %a0 to <4 x float>
+  ret <4 x float> %2
+}
+
+define <8 x float> @stack_fold_cvtdq2ps_ymm(<8 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtdq2ps_ymm
+  ;CHECK:   vcvtdq2ps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = sitofp <8 x i32> %a0 to <8 x float>
+  ret <8 x float> %2
+}
+
+define <4 x i32> @stack_fold_cvtpd2dq(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtpd2dq
+  ;CHECK:   vcvtpd2dqx {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double>) nounwind readnone
+
+define <4 x i32> @stack_fold_cvtpd2dq_ymm(<4 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtpd2dq_ymm
+  ;CHECK:   vcvtpd2dqy {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double>) nounwind readnone
+
+define <2 x float> @stack_fold_cvtpd2ps(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtpd2ps
+  ;CHECK:   vcvtpd2psx {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fptrunc <2 x double> %a0 to <2 x float>
+  ret <2 x float> %2
+}
+
+define <4 x float> @stack_fold_cvtpd2ps_ymm(<4 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtpd2ps_ymm
+  ;CHECK:   vcvtpd2psy {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fptrunc <4 x double> %a0 to <4 x float>
+  ret <4 x float> %2
+}
+
+define <4 x float> @stack_fold_cvtph2ps(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtph2ps
+  ;CHECK:   vcvtph2ps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16>) nounwind readonly
+
+define <8 x float> @stack_fold_cvtph2ps_ymm(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtph2ps_ymm
+  ;CHECK:   vcvtph2ps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %a0)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>) nounwind readonly
+
+define <4 x i32> @stack_fold_cvtps2dq(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtps2dq
+  ;CHECK:  vcvtps2dq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float>) nounwind readnone
+
+define <8 x i32> @stack_fold_cvtps2dq_ymm(<8 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtps2dq_ymm
+  ;CHECK:  vcvtps2dq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float> %a0)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_cvtps2pd(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtps2pd
+  ;CHECK:   vcvtps2pd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float> %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float>) nounwind readnone
+
+define <4 x double> @stack_fold_cvtps2pd_ymm(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtps2pd_ymm
+  ;CHECK:   vcvtps2pd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.avx.cvt.ps2.pd.256(<4 x float> %a0)
+  ret <4 x double> %2
+}
+declare <4 x double> @llvm.x86.avx.cvt.ps2.pd.256(<4 x float>) nounwind readnone
+
+define <8 x i16> @stack_fold_cvtps2ph(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtps2ph
+  ;CHECK:   vcvtps2ph $0, {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 16-byte Folded Spill
+  %1 = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0)
+  %2 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  ret <8 x i16> %1
+}
+declare <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float>, i32) nounwind readonly
+
+define <8 x i16> @stack_fold_cvtps2ph_ymm(<8 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtps2ph_ymm
+  ;CHECK:   vcvtps2ph $0, {{%ymm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 16-byte Folded Spill
+  %1 = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0)
+  %2 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  ret <8 x i16> %1
+}
+declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32) nounwind readonly
+
+; TODO stack_fold_cvtsd2si
+
+define i32 @stack_fold_cvtsd2si_int(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsd2si_int
+  ;CHECK:  cvtsd2si {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %a0)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone
+
+; TODO stack_fold_cvtsd2si64
+
+define i64 @stack_fold_cvtsd2si64_int(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsd2si64_int
+  ;CHECK:  cvtsd2si {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0)
+  ret i64 %2
+}
+declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
+
+; TODO stack_fold_cvtsd2ss
+
+define <4 x float> @stack_fold_cvtsd2ss_int(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsd2ss_int
+  ;CHECK:  cvtsd2ss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> <float 0x0, float 0x0, float 0x0, float 0x0>, <2 x double> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float>, <2 x double>) nounwind readnone
+
+define double @stack_fold_cvtsi2sd(i32 %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsi2sd
+  ;CHECK:  cvtsi2sdl {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = sitofp i32 %a0 to double
+  ret double %2
+}
+
+define <2 x double> @stack_fold_cvtsi2sd_int(i32 %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsi2sd_int
+  ;CHECK:  cvtsi2sdl {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = call <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double> <double 0x0, double 0x0>, i32 %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double>, i32) nounwind readnone
+
+define double @stack_fold_cvtsi642sd(i64 %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsi642sd
+  ;CHECK:  cvtsi2sdq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = sitofp i64 %a0 to double
+  ret double %2
+}
+
+define <2 x double> @stack_fold_cvtsi642sd_int(i64 %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsi642sd_int
+  ;CHECK:  cvtsi2sdq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> <double 0x0, double 0x0>, i64 %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone
+
+define float @stack_fold_cvtsi2ss(i32 %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsi2ss
+  ;CHECK:  cvtsi2ssl {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = sitofp i32 %a0 to float
+  ret float %2
+}
+
+define <4 x float> @stack_fold_cvtsi2ss_int(i32 %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsi2ss_int
+  ;CHECK:  cvtsi2ssl {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = call <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float> <float 0x0, float 0x0, float 0x0, float 0x0>, i32 %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float>, i32) nounwind readnone
+
+define float @stack_fold_cvtsi642ss(i64 %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsi642ss
+  ;CHECK:  cvtsi2ssq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = sitofp i64 %a0 to float
+  ret float %2
+}
+
+define <4 x float> @stack_fold_cvtsi642ss_int(i64 %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsi642ss_int
+  ;CHECK:  cvtsi2ssq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> <float 0x0, float 0x0, float 0x0, float 0x0>, i64 %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone
+
+; TODO stack_fold_cvtss2sd
+
+define <2 x double> @stack_fold_cvtss2sd_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtss2sd_int
+  ;CHECK:  cvtss2sd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double> <double 0x0, double 0x0>, <4 x float> %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double>, <4 x float>) nounwind readnone
+
+; TODO stack_fold_cvtss2si
+
+define i32 @stack_fold_cvtss2si_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtss2si_int
+  ;CHECK:  vcvtss2si {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse.cvtss2si(<4 x float> %a0)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse.cvtss2si(<4 x float>) nounwind readnone
+
+; TODO stack_fold_cvtss2si64
+
+define i64 @stack_fold_cvtss2si64_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtss2si64_int
+  ;CHECK:  vcvtss2si {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %a0)
+  ret i64 %2
+}
+declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) nounwind readnone
+
+define <4 x i32> @stack_fold_cvttpd2dq(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttpd2dq
+  ;CHECK:  vcvttpd2dqx {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>) nounwind readnone
+
+define <4 x i32> @stack_fold_cvttpd2dq_ymm(<4 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttpd2dq_ymm
+  ;CHECK:  vcvttpd2dqy {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fptosi <4 x double> %a0 to <4 x i32>
+  ret <4 x i32> %2
+}
+
+define <4 x i32> @stack_fold_cvttps2dq(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttps2dq
+  ;CHECK:  vcvttps2dq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fptosi <4 x float> %a0 to <4 x i32>
+  ret <4 x i32> %2
+}
+
+define <8 x i32> @stack_fold_cvttps2dq_ymm(<8 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttps2dq_ymm
+  ;CHECK:  vcvttps2dq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fptosi <8 x float> %a0 to <8 x i32>
+  ret <8 x i32> %2
+}
+
+define i32 @stack_fold_cvttsd2si(double %a0) {
+  ;CHECK-LABEL: stack_fold_cvttsd2si
+  ;CHECK:  vcvttsd2si {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fptosi double %a0 to i32
+  ret i32 %2
+}
+
+define i32 @stack_fold_cvttsd2si_int(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttsd2si_int
+  ;CHECK:  vcvttsd2si {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %a0)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) nounwind readnone
+
+define i64 @stack_fold_cvttsd2si64(double %a0) {
+  ;CHECK-LABEL: stack_fold_cvttsd2si64
+  ;CHECK:  vcvttsd2si {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fptosi double %a0 to i64
+  ret i64 %2
+}
+
+define i64 @stack_fold_cvttsd2si64_int(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttsd2si64_int
+  ;CHECK:  vcvttsd2si {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0)
+  ret i64 %2
+}
+declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
+
+define i32 @stack_fold_cvttss2si(float %a0) {
+  ;CHECK-LABEL: stack_fold_cvttss2si
+  ;CHECK:  vcvttss2si {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fptosi float %a0 to i32
+  ret i32 %2
+}
+
+define i32 @stack_fold_cvttss2si_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttss2si_int
+  ;CHECK:  vcvttss2si {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %a0)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone
+
+define i64 @stack_fold_cvttss2si64(float %a0) {
+  ;CHECK-LABEL: stack_fold_cvttss2si64
+  ;CHECK:  vcvttss2si {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fptosi float %a0 to i64
+  ret i64 %2
+}
+
+define i64 @stack_fold_cvttss2si64_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttss2si64_int
+  ;CHECK:  cvttss2si {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %a0)
+  ret i64 %2
+}
+declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_divpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_divpd
+  ;CHECK:       vdivpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fdiv <2 x double> %a0, %a1
+  ret <2 x double> %2
+}
+
+define <4 x double> @stack_fold_divpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_divpd_ymm
+  ;CHECK:       vdivpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fdiv <4 x double> %a0, %a1
+  ret <4 x double> %2
+}
+
+define <4 x float> @stack_fold_divps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_divps
+  ;CHECK:       vdivps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fdiv <4 x float> %a0, %a1
+  ret <4 x float> %2
+}
+
+define <8 x float> @stack_fold_divps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_divps_ymm
+  ;CHECK:       vdivps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fdiv <8 x float> %a0, %a1
+  ret <8 x float> %2
+}
+
+define double @stack_fold_divsd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_divsd
+  ;CHECK:       vdivsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fdiv double %a0, %a1
+  ret double %2
+}
+
+define <2 x double> @stack_fold_divsd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_divsd_int
+  ;CHECK:       vdivsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.div.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define float @stack_fold_divss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_divss
+  ;CHECK:       vdivss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fdiv float %a0, %a1
+  ret float %2
+}
+
+define <4 x float> @stack_fold_divss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_divss_int
+  ;CHECK:       vdivss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.div.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_dppd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_dppd
+  ;CHECK:       vdppd $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse41.dppd(<2 x double> %a0, <2 x double> %a1, i8 7)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse41.dppd(<2 x double>, <2 x double>, i8) nounwind readnone
+
+define <4 x float> @stack_fold_dpps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_dpps
+  ;CHECK:       vdpps $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse41.dpps(<4 x float> %a0, <4 x float> %a1, i8 7)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse41.dpps(<4 x float>, <4 x float>, i8) nounwind readnone
+
+define <8 x float> @stack_fold_dpps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_dpps_ymm
+  ;CHECK:       vdpps $7, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone
+
+define <4 x float> @stack_fold_extractf128(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_extractf128
+  ;CHECK:       vextractf128 $1, {{%ymm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 16-byte Folded Spill
+  %1 = shufflevector <8 x float> %a0, <8 x float> %a1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+  %2 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  ret <4 x float> %1
+}
+
+define i32 @stack_fold_extractps(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_extractps
+  ;CHECK:       vextractps $1, {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 4-byte Folded Spill
+  ;CHECK:       movl    {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Reload
+  %1 = extractelement <4 x float> %a0, i32 1
+  %2 = bitcast float %1 to i32
+  %3 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  ret i32 %2
+}
+
+define <2 x double> @stack_fold_haddpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_haddpd
+  ;CHECK:       vhaddpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>) nounwind readnone
+
+define <4 x double> @stack_fold_haddpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_haddpd_ymm
+  ;CHECK:       vhaddpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> %a0, <4 x double> %a1)
+  ret <4 x double> %2
+}
+declare <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double>, <4 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_haddps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_haddps
+  ;CHECK:       vhaddps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind readnone
+
+define <8 x float> @stack_fold_haddps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_haddps_ymm
+  ;CHECK:       vhaddps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %a0, <8 x float> %a1)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_hsubpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_hsubpd
+  ;CHECK:       vhsubpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
+
+define <4 x double> @stack_fold_hsubpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_hsubpd_ymm
+  ;CHECK:       vhsubpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1)
+  ret <4 x double> %2
+}
+declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_hsubps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_hsubps
+  ;CHECK:       vhsubps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
+
+define <8 x float> @stack_fold_hsubps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_hsubps_ymm
+  ;CHECK:       vhsubps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
+
+define <8 x float> @stack_fold_insertf128(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_insertf128
+  ;CHECK:       vinsertf128 $1, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  ret <8 x float> %2
+}
+
+; TODO stack_fold_insertps
+
+define <2 x double> @stack_fold_maxpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_maxpd
+  ;CHECK:       vmaxpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone
+
+define <4 x double> @stack_fold_maxpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_maxpd_ymm
+  ;CHECK:       vmaxpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.avx.max.pd.256(<4 x double> %a0, <4 x double> %a1)
+  ret <4 x double> %2
+}
+declare <4 x double> @llvm.x86.avx.max.pd.256(<4 x double>, <4 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_maxps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_maxps
+  ;CHECK:       vmaxps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind readnone
+
+define <8 x float> @stack_fold_maxps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_maxps_ymm
+  ;CHECK:       vmaxps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.avx.max.ps.256(<8 x float> %a0, <8 x float> %a1)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.avx.max.ps.256(<8 x float>, <8 x float>) nounwind readnone
+
+define double @stack_fold_maxsd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_maxsd
+  ;CHECK:       vmaxsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp ogt double %a0, %a1
+  %3 = select i1 %2, double %a0, double %a1
+  ret double %3
+}
+
+define <2 x double> @stack_fold_maxsd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_maxsd_int
+  ;CHECK:       vmaxsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define float @stack_fold_maxss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_maxss
+  ;CHECK:       vmaxss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp ogt float %a0, %a1
+  %3 = select i1 %2, float %a0, float %a1
+  ret float %3
+}
+
+define <4 x float> @stack_fold_maxss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_maxss_int
+  ;CHECK:       vmaxss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_minpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_minpd
+  ;CHECK:       vminpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
+
+define <4 x double> @stack_fold_minpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_minpd_ymm
+  ;CHECK:       vminpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.avx.min.pd.256(<4 x double> %a0, <4 x double> %a1)
+  ret <4 x double> %2
+}
+declare <4 x double> @llvm.x86.avx.min.pd.256(<4 x double>, <4 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_minps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_minps
+  ;CHECK:       vminps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone
+
+define <8 x float> @stack_fold_minps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_minps_ymm
+  ;CHECK:       vminps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> %a0, <8 x float> %a1)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.avx.min.ps.256(<8 x float>, <8 x float>) nounwind readnone
+
+define double @stack_fold_minsd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_minsd
+  ;CHECK:       vminsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp olt double %a0, %a1
+  %3 = select i1 %2, double %a0, double %a1
+  ret double %3
+}
+
+define <2 x double> @stack_fold_minsd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_minsd_int
+  ;CHECK:       vminsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define float @stack_fold_minss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_minss
+  ;CHECK:       vminss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp olt float %a0, %a1
+  %3 = select i1 %2, float %a0, float %a1
+  ret float %3
+}
+
+define <4 x float> @stack_fold_minss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_minss_int
+  ;CHECK:       vminss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_movddup(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_movddup
+  ;CHECK:   vmovddup {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <2 x double> %a0, <2 x double> undef, <2 x i32> <i32 0, i32 0>
+  ret <2 x double> %2
+}
+
+define <4 x double> @stack_fold_movddup_ymm(<4 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_movddup_ymm
+  ;CHECK:   vmovddup {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
+  ret <4 x double> %2
+}
+
+; TODO stack_fold_movhpd (load / store)
+; TODO stack_fold_movhps (load / store)
+
+; TODO stack_fold_movlpd (load / store)
+; TODO stack_fold_movlps (load / store)
+
+define <4 x float> @stack_fold_movshdup(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_movshdup
+  ;CHECK:   vmovshdup {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
+  ret <4 x float> %2
+}
+
+define <8 x float> @stack_fold_movshdup_ymm(<8 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_movshdup_ymm
+  ;CHECK:   vmovshdup {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x float> %a0, <8 x float> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
+  ret <8 x float> %2
+}
+
+define <4 x float> @stack_fold_movsldup(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_movsldup
+  ;CHECK:   vmovsldup {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
+  ret <4 x float> %2
+}
+
+define <8 x float> @stack_fold_movsldup_ymm(<8 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_movsldup_ymm
+  ;CHECK:   vmovsldup {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x float> %a0, <8 x float> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
+  ret <8 x float> %2
+}
+
+define <2 x double> @stack_fold_mulpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_mulpd
+  ;CHECK:       vmulpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fmul <2 x double> %a0, %a1
+  ret <2 x double> %2
+}
+
+define <4 x double> @stack_fold_mulpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_mulpd_ymm
+  ;CHECK:       vmulpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fmul <4 x double> %a0, %a1
+  ret <4 x double> %2
+}
+
+define <4 x float> @stack_fold_mulps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_mulps
+  ;CHECK:       vmulps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fmul <4 x float> %a0, %a1
+  ret <4 x float> %2
+}
+
+define <8 x float> @stack_fold_mulps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_mulps_ymm
+  ;CHECK:       vmulps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fmul <8 x float> %a0, %a1
+  ret <8 x float> %2
+}
+
+define double @stack_fold_mulsd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_mulsd
+  ;CHECK:       vmulsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fmul double %a0, %a1
+  ret double %2
+}
+
+define <2 x double> @stack_fold_mulsd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_mulsd_int
+  ;CHECK:       vmulsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.mul.sd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.mul.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define float @stack_fold_mulss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_mulss
+  ;CHECK:       vmulss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fmul float %a0, %a1
+  ret float %2
+}
+
+define <4 x float> @stack_fold_mulss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_mulss_int
+  ;CHECK:       vmulss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.mul.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_orpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_orpd
+  ;CHECK:       vorpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <2 x double> %a0 to <2 x i64>
+  %3 = bitcast <2 x double> %a1 to <2 x i64>
+  %4 = or <2 x i64> %2, %3
+  %5 = bitcast <2 x i64> %4 to <2 x double>
+  ; fadd forces execution domain
+  %6 = fadd <2 x double> %5, <double 0x0, double 0x0>
+  ret <2 x double> %6
+}
+
+define <4 x double> @stack_fold_orpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_orpd_ymm
+  ;CHECK:       vorpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <4 x double> %a0 to <4 x i64>
+  %3 = bitcast <4 x double> %a1 to <4 x i64>
+  %4 = or <4 x i64> %2, %3
+  %5 = bitcast <4 x i64> %4 to <4 x double>
+  ; fadd forces execution domain
+  %6 = fadd <4 x double> %5, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %6
+}
+
+define <4 x float> @stack_fold_orps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_orps
+  ;CHECK:       vorps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <4 x float> %a0 to <2 x i64>
+  %3 = bitcast <4 x float> %a1 to <2 x i64>
+  %4 = or <2 x i64> %2, %3
+  %5 = bitcast <2 x i64> %4 to <4 x float>
+  ; fadd forces execution domain
+  %6 = fadd <4 x float> %5, <float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <4 x float> %6
+}
+
+define <8 x float> @stack_fold_orps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_orps_ymm
+  ;CHECK:       vorps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <8 x float> %a0 to <4 x i64>
+  %3 = bitcast <8 x float> %a1 to <4 x i64>
+  %4 = or <4 x i64> %2, %3
+  %5 = bitcast <4 x i64> %4 to <8 x float>
+  ; fadd forces execution domain
+  %6 = fadd <8 x float> %5, <float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <8 x float> %6
+}
+
+define <8 x float> @stack_fold_perm2f128(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_perm2f128
+  ;CHECK:   vperm2f128 $33, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x float> %a0, <8 x float> %a1, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
+  ret <8 x float> %2
+}
+
+define <2 x double> @stack_fold_permilpd(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_permilpd
+  ;CHECK:   vpermilpd $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <2 x double> %a0, <2 x double> undef, <2 x i32> <i32 1, i32 0>
+  ret <2 x double> %2
+}
+
+define <4 x double> @stack_fold_permilpd_ymm(<4 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_permilpd_ymm
+  ;CHECK:   vpermilpd $5, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+  ret <4 x double> %2
+}
+
+define <2 x double> @stack_fold_permilpdvar(<2 x double> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_permilpdvar
+  ;CHECK:       vpermilpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i64>) nounwind readnone
+
+define <4 x double> @stack_fold_permilpdvar_ymm(<4 x double> %a0, <4 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_permilpdvar_ymm
+  ;CHECK:       vpermilpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> %a1)
+  ret <4 x double> %2
+}
+declare <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double>, <4 x i64>) nounwind readnone
+
+define <4 x float> @stack_fold_permilps(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_permilps
+  ;CHECK:   vpermilps $27, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  ret <4 x float> %2
+}
+
+define <8 x float> @stack_fold_permilps_ymm(<8 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_permilps_ymm
+  ;CHECK:   vpermilps $27, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x float> %a0, <8 x float> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+  ret <8 x float> %2
+}
+
+define <4 x float> @stack_fold_permilpsvar(<4 x float> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_permilpsvar
+  ;CHECK:       vpermilps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>) nounwind readnone
+
+define <8 x float> @stack_fold_permilpsvar_ymm(<8 x float> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_permilpsvar_ymm
+  ;CHECK:       vpermilps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> %a1)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float>, <8 x i32>) nounwind readnone
+
+; TODO stack_fold_rcpps
+
+define <4 x float> @stack_fold_rcpps_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_rcpps_int
+  ;CHECK:       vrcpps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>) nounwind readnone
+
+; TODO stack_fold_rcpps_ymm
+
+define <8 x float> @stack_fold_rcpps_ymm_int(<8 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_rcpps_ymm_int
+  ;CHECK:       vrcpps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float> %a0)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float>) nounwind readnone
+
+; TODO stack_fold_rcpss
+
+define <4 x float> @stack_fold_rcpss_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_rcpss_int
+  ;CHECK:       vrcpss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_roundpd(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_roundpd
+  ;CHECK:  vroundpd $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse41.round.pd(<2 x double> %a0, i32 7)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse41.round.pd(<2 x double>, i32) nounwind readnone
+
+define <4 x double> @stack_fold_roundpd_ymm(<4 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_roundpd_ymm
+  ;CHECK:  vroundpd $7, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.avx.round.pd.256(<4 x double> %a0, i32 7)
+  ret <4 x double> %2
+}
+declare <4 x double> @llvm.x86.avx.round.pd.256(<4 x double>, i32) nounwind readnone
+
+define <4 x float> @stack_fold_roundps(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_roundps
+  ;CHECK:  vroundps $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %a0, i32 7)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse41.round.ps(<4 x float>, i32) nounwind readnone
+
+define <8 x float> @stack_fold_roundps_ymm(<8 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_roundps_ymm
+  ;CHECK:  vroundps $7, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.avx.round.ps.256(<8 x float> %a0, i32 7)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.avx.round.ps.256(<8 x float>, i32) nounwind readnone
+
+; TODO stack_fold_roundsd
+
+; TODO stack_fold_roundsd_int
+declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) nounwind readnone
+
+; TODO stack_fold_roundss
+
+; TODO stack_fold_roundss_int
+declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) nounwind readnone
+
+; TODO stack_fold_rsqrtps
+
+define <4 x float> @stack_fold_rsqrtps_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_rsqrtps_int
+  ;CHECK:       vrsqrtps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float>) nounwind readnone
+
+; TODO stack_fold_rsqrtps_ymm
+
+define <8 x float> @stack_fold_rsqrtps_ymm_int(<8 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_rsqrtps_ymm_int
+  ;CHECK:       vrsqrtps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float> %a0)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float>) nounwind readnone
+
+; TODO stack_fold_rsqrtss
+
+define <4 x float> @stack_fold_rsqrtss_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_rsqrtss_int
+  ;CHECK:       vrsqrtss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_shufpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_shufpd
+  ;CHECK:       vshufpd $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 1, i32 2>
+  ret <2 x double> %2
+}
+
+define <4 x double> @stack_fold_shufpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_shufpd_ymm
+  ;CHECK:       vshufpd $5, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 1, i32 4, i32 3, i32 6>
+  ret <4 x double> %2
+}
+
+define <4 x float> @stack_fold_shufps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_shufps
+  ;CHECK:       vshufps $200, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 0, i32 2, i32 4, i32 7>
+  ret <4 x float> %2
+}
+
+define <8 x float> @stack_fold_shufps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_shufps_ymm
+  ;CHECK:       vshufps $148, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x float> %a0, <8 x float> %a1, <8 x i32> <i32 0, i32 1, i32 9, i32 10, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <8 x float> %2
+}
+
+define <2 x double> @stack_fold_sqrtpd(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_sqrtpd
+  ;CHECK:       vsqrtpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double> %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>) nounwind readnone
+
+define <4 x double> @stack_fold_sqrtpd_ymm(<4 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_sqrtpd_ymm
+  ;CHECK:       vsqrtpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double> %a0)
+  ret <4 x double> %2
+}
+declare <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_sqrtps(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_sqrtps
+  ;CHECK:       vsqrtps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>) nounwind readnone
+
+define <8 x float> @stack_fold_sqrtps_ymm(<8 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_sqrtps_ymm
+  ;CHECK:       vsqrtps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float> %a0)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float>) nounwind readnone
+
+define double @stack_fold_sqrtsd(double %a0) {
+  ;CHECK-LABEL: stack_fold_sqrtsd
+  ;CHECK:       vsqrtsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call double @llvm.sqrt.f64(double %a0)
+  ret double %2
+}
+declare double @llvm.sqrt.f64(double) nounwind readnone
+
+define <2 x double> @stack_fold_sqrtsd_int(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_sqrtsd_int
+  ;CHECK:       vsqrtsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
+
+define float @stack_fold_sqrtss(float %a0) {
+  ;CHECK-LABEL: stack_fold_sqrtss
+  ;CHECK:       vsqrtss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call float @llvm.sqrt.f32(float %a0)
+  ret float %2
+}
+declare float @llvm.sqrt.f32(float) nounwind readnone
+
+define <4 x float> @stack_fold_sqrtss_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_sqrtss_int
+  ;CHECK:       vsqrtss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_subpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_subpd
+  ;CHECK:       vsubpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fsub <2 x double> %a0, %a1
+  ret <2 x double> %2
+}
+
+define <4 x double> @stack_fold_subpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_subpd_ymm
+  ;CHECK:       vsubpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fsub <4 x double> %a0, %a1
+  ret <4 x double> %2
+}
+
+define <4 x float> @stack_fold_subps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_subps
+  ;CHECK:       vsubps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fsub <4 x float> %a0, %a1
+  ret <4 x float> %2
+}
+
+define <8 x float> @stack_fold_subps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_subps_ymm
+  ;CHECK:       vsubps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fsub <8 x float> %a0, %a1
+  ret <8 x float> %2
+}
+
+define double @stack_fold_subsd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_subsd
+  ;CHECK:       vsubsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fsub double %a0, %a1
+  ret double %2
+}
+
+define <2 x double> @stack_fold_subsd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_subsd_int
+  ;CHECK:       vsubsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.sub.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define float @stack_fold_subss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_subss
+  ;CHECK:       vsubss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fsub float %a0, %a1
+  ret float %2
+}
+
+define <4 x float> @stack_fold_subss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_subss_int
+  ;CHECK:       vsubss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define i32 @stack_fold_testpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_testpd
+  ;CHECK:       vtestpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.avx.vtestc.pd(<2 x double> %a0, <2 x double> %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.avx.vtestc.pd(<2 x double>, <2 x double>) nounwind readnone
+
+define i32 @stack_fold_testpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_testpd_ymm
+  ;CHECK:       vtestpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.avx.vtestc.pd.256(<4 x double> %a0, <4 x double> %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.avx.vtestc.pd.256(<4 x double>, <4 x double>) nounwind readnone
+
+define i32 @stack_fold_testps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_testps
+  ;CHECK:       vtestps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.avx.vtestc.ps(<4 x float> %a0, <4 x float> %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.avx.vtestc.ps(<4 x float>, <4 x float>) nounwind readnone
+
+define i32 @stack_fold_testps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_testps_ymm
+  ;CHECK:       vtestps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.avx.vtestc.ps.256(<8 x float> %a0, <8 x float> %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.avx.vtestc.ps.256(<8 x float>, <8 x float>) nounwind readnone
+
+define i32 @stack_fold_ucomisd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_ucomisd
+  ;CHECK:       vucomisd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp ueq double %a0, %a1
+  %3 = select i1 %2, i32 1, i32 -1
+  ret i32 %3
+}
+
+define i32 @stack_fold_ucomisd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_ucomisd_int
+  ;CHECK:       vucomisd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %a0, <2 x double> %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define i32 @stack_fold_ucomiss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_ucomiss
+  ;CHECK:       vucomiss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp ueq float %a0, %a1
+  %3 = select i1 %2, i32 1, i32 -1
+  ret i32 %3
+}
+
+define i32 @stack_fold_ucomiss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_ucomiss_int
+  ;CHECK:       vucomiss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse.ucomieq.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_unpckhpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_unpckhpd
+  ;CHECK:       vunpckhpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 1, i32 3>
+  ; fadd forces execution domain
+  %3 = fadd <2 x double> %2, <double 0x0, double 0x0>
+  ret <2 x double> %3
+}
+
+define <4 x double> @stack_fold_unpckhpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_unpckhpd_ymm
+  ;CHECK:       vunpckhpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+  ; fadd forces execution domain
+  %3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %3
+}
+
+define <4 x float> @stack_fold_unpckhps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_unpckhps
+  ;CHECK:       vunpckhps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+  ; fadd forces execution domain
+  %3 = fadd <4 x float> %2, <float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <4 x float> %3
+}
+
+define <8 x float> @stack_fold_unpckhps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_unpckhps_ymm
+  ;CHECK:       vunpckhps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x float> %a0, <8 x float> %a1, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15>
+  ; fadd forces execution domain
+  %3 = fadd <8 x float> %2, <float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <8 x float> %3
+}
+
+define <2 x double> @stack_fold_unpcklpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_unpcklpd
+  ;CHECK:       vunpcklpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 0, i32 2>
+  ; fadd forces execution domain
+  %3 = fadd <2 x double> %2, <double 0x0, double 0x0>
+  ret <2 x double> %3
+}
+
+define <4 x double> @stack_fold_unpcklpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_unpcklpd_ymm
+  ;CHECK:       vunpcklpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+  ; fadd forces execution domain
+  %3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %3
+}
+
+define <4 x float> @stack_fold_unpcklps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_unpcklps
+  ;CHECK:       vunpcklps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+  ; fadd forces execution domain
+  %3 = fadd <4 x float> %2, <float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <4 x float> %3
+}
+
+define <8 x float> @stack_fold_unpcklps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_unpcklps_ymm
+  ;CHECK:       vunpcklps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x float> %a0, <8 x float> %a1, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13>
+  ; fadd forces execution domain
+  %3 = fadd <8 x float> %2, <float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <8 x float> %3
+}
+
+define <2 x double> @stack_fold_xorpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_xorpd
+  ;CHECK:       vxorpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <2 x double> %a0 to <2 x i64>
+  %3 = bitcast <2 x double> %a1 to <2 x i64>
+  %4 = xor <2 x i64> %2, %3
+  %5 = bitcast <2 x i64> %4 to <2 x double>
+  ; fadd forces execution domain
+  %6 = fadd <2 x double> %5, <double 0x0, double 0x0>
+  ret <2 x double> %6
+}
+
+define <4 x double> @stack_fold_xorpd_ymm(<4 x double> %a0, <4 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_xorpd_ymm
+  ;CHECK:       vxorpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <4 x double> %a0 to <4 x i64>
+  %3 = bitcast <4 x double> %a1 to <4 x i64>
+  %4 = xor <4 x i64> %2, %3
+  %5 = bitcast <4 x i64> %4 to <4 x double>
+  ; fadd forces execution domain
+  %6 = fadd <4 x double> %5, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %6
+}
+
+define <4 x float> @stack_fold_xorps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_xorps
+  ;CHECK:       vxorps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <4 x float> %a0 to <2 x i64>
+  %3 = bitcast <4 x float> %a1 to <2 x i64>
+  %4 = xor <2 x i64> %2, %3
+  %5 = bitcast <2 x i64> %4 to <4 x float>
+  ; fadd forces execution domain
+  %6 = fadd <4 x float> %5, <float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <4 x float> %6
+}
+
+define <8 x float> @stack_fold_xorps_ymm(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_xorps_ymm
+  ;CHECK:       vxorps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <8 x float> %a0 to <4 x i64>
+  %3 = bitcast <8 x float> %a1 to <4 x i64>
+  %4 = xor <4 x i64> %2, %3
+  %5 = bitcast <4 x i64> %4 to <8 x float>
+  ; fadd forces execution domain
+  %6 = fadd <8 x float> %5, <float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <8 x float> %6
+}
diff --git a/test/CodeGen/X86/stack-folding-fp-sse42.ll b/test/CodeGen/X86/stack-folding-fp-sse42.ll
new file mode 100644
index 000000000000..95f0c3d3a188
--- /dev/null
+++ b/test/CodeGen/X86/stack-folding-fp-sse42.ll
@@ -0,0 +1,1097 @@
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.2 < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-unknown"
+
+; Stack reload folding tests.
+;
+; By including a nop call with sideeffects we can force a partial register spill of the
+; relevant registers and check that the reload is correctly folded into the instruction.
+
+define <2 x double> @stack_fold_addpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_addpd
+  ;CHECK:       addpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fadd <2 x double> %a0, %a1
+  ret <2 x double> %2
+}
+
+define <4 x float> @stack_fold_addps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_addps
+  ;CHECK:       addps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fadd <4 x float> %a0, %a1
+  ret <4 x float> %2
+}
+
+define double @stack_fold_addsd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_addsd
+  ;CHECK:       addsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fadd double %a0, %a1
+  ret double %2
+}
+
+define <2 x double> @stack_fold_addsd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_addsd_int
+  ;CHECK:       addsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.add.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define float @stack_fold_addss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_addss
+  ;CHECK:       addss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fadd float %a0, %a1
+  ret float %2
+}
+
+define <4 x float> @stack_fold_addss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_addss_int
+  ;CHECK:       addss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.add.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_addsubpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_addsubpd
+  ;CHECK:       addsubpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_addsubps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_addsubps
+  ;CHECK:       addsubps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_andnpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_andnpd
+  ;CHECK:       andnpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <2 x double> %a0 to <2 x i64>
+  %3 = bitcast <2 x double> %a1 to <2 x i64>
+  %4 = xor <2 x i64> %2, <i64 -1, i64 -1>
+  %5 = and <2 x i64> %4, %3
+  %6 = bitcast <2 x i64> %5 to <2 x double>
+  ; fadd forces execution domain
+  %7 = fadd <2 x double> %6, <double 0x0, double 0x0>
+  ret <2 x double> %7
+}
+
+define <4 x float> @stack_fold_andnps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_andnps
+  ;CHECK:       andnps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <4 x float> %a0 to <2 x i64>
+  %3 = bitcast <4 x float> %a1 to <2 x i64>
+  %4 = xor <2 x i64> %2, <i64 -1, i64 -1>
+  %5 = and <2 x i64> %4, %3
+  %6 = bitcast <2 x i64> %5 to <4 x float>
+  ; fadd forces execution domain
+  %7 = fadd <4 x float> %6, <float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <4 x float> %7
+}
+
+define <2 x double> @stack_fold_andpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_andpd
+  ;CHECK:       andpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <2 x double> %a0 to <2 x i64>
+  %3 = bitcast <2 x double> %a1 to <2 x i64>
+  %4 = and <2 x i64> %2, %3
+  %5 = bitcast <2 x i64> %4 to <2 x double>
+  ; fadd forces execution domain
+  %6 = fadd <2 x double> %5, <double 0x0, double 0x0>
+  ret <2 x double> %6
+}
+
+define <4 x float> @stack_fold_andps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_andps
+  ;CHECK:       andps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <4 x float> %a0 to <2 x i64>
+  %3 = bitcast <4 x float> %a1 to <2 x i64>
+  %4 = and <2 x i64> %2, %3
+  %5 = bitcast <2 x i64> %4 to <4 x float>
+  ; fadd forces execution domain
+  %6 = fadd <4 x float> %5, <float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <4 x float> %6
+}
+
+define <2 x double> @stack_fold_blendpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_blendpd
+  ;CHECK:       blendpd $2, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = select <2 x i1> <i1 1, i1 0>, <2 x double> %a0, <2 x double> %a1
+  ret <2 x double> %2
+}
+
+define <4 x float> @stack_fold_blendps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_blendps
+  ;CHECK:       blendps $6, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = select <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x float> %a0, <4 x float> %a1
+  ret <4 x float> %2
+}
+
+define <2 x double> @stack_fold_blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %c) {
+  ;CHECK-LABEL: stack_fold_blendvpd
+  ;CHECK:       blendvpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse41.blendvpd(<2 x double> %a1, <2 x double> %c, <2 x double> %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse41.blendvpd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> %c) {
+  ;CHECK-LABEL: stack_fold_blendvps
+  ;CHECK:       blendvps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %a1, <4 x float> %c, <4 x float> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_cmppd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_cmppd
+  ;CHECK:       cmpeqpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> %a0, <2 x double> %a1, i8 0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double>, <2 x double>, i8) nounwind readnone
+
+define <4 x float> @stack_fold_cmpps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_cmpps
+  ;CHECK:       cmpeqps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %a0, <4 x float> %a1, i8 0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone
+
+define i32 @stack_fold_cmpsd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_cmpsd
+  ;CHECK:       cmpeqsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp oeq double %a0, %a1
+  %3 = zext i1 %2 to i32
+  ret i32 %3
+}
+
+define <2 x double> @stack_fold_cmpsd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_cmpsd_int
+  ;CHECK:       cmpeqsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a0, <2 x double> %a1, i8 0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounwind readnone
+
+define i32 @stack_fold_cmpss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_cmpss
+  ;CHECK:       cmpeqss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp oeq float %a0, %a1
+  %3 = zext i1 %2 to i32
+  ret i32 %3
+}
+
+define <4 x float> @stack_fold_cmpss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_cmpss_int
+  ;CHECK:       cmpeqss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %a0, <4 x float> %a1, i8 0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8) nounwind readnone
+
+; TODO stack_fold_comisd
+
+define i32 @stack_fold_comisd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_comisd_int
+  ;CHECK:       comisd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readnone
+
+; TODO stack_fold_comiss
+
+define i32 @stack_fold_comiss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_comiss_int
+  ;CHECK:       comiss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse.comieq.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_cvtdq2pd(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtdq2pd
+  ;CHECK:       cvtdq2pd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32> %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32>) nounwind readnone
+
+define <4 x float> @stack_fold_cvtdq2ps(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtdq2ps
+  ;CHECK:       cvtdq2ps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = sitofp <4 x i32> %a0 to <4 x float>
+  ret <4 x float> %2
+}
+
+define <4 x i32> @stack_fold_cvtpd2dq(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtpd2dq
+  ;CHECK:       cvtpd2dq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double>) nounwind readnone
+
+define <2 x float> @stack_fold_cvtpd2ps(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtpd2ps
+  ;CHECK:       cvtpd2ps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fptrunc <2 x double> %a0 to <2 x float>
+  ret <2 x float> %2
+}
+
+define <4 x i32> @stack_fold_cvtps2dq(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtps2dq
+  ;CHECK:       cvtps2dq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_cvtps2pd(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtps2pd
+  ;CHECK:       cvtps2pd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float> %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float>) nounwind readnone
+
+; TODO stack_fold_cvtsd2si
+
+define i32 @stack_fold_cvtsd2si_int(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsd2si_int
+  ;CHECK:       cvtsd2si {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %a0)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone
+
+; TODO stack_fold_cvtsd2si64
+
+define i64 @stack_fold_cvtsd2si64_int(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsd2si64_int
+  ;CHECK:       cvtsd2siq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0)
+  ret i64 %2
+}
+declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
+
+; TODO stack_fold_cvtsd2ss
+
+define <4 x float> @stack_fold_cvtsd2ss_int(<2 x double> %a0) optsize {
+  ;CHECK-LABEL: stack_fold_cvtsd2ss_int
+  ;CHECK:       cvtsd2ss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> <float 0x0, float 0x0, float 0x0, float 0x0>, <2 x double> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float>, <2 x double>) nounwind readnone
+
+define double @stack_fold_cvtsi2sd(i32 %a0) optsize {
+  ;CHECK-LABEL: stack_fold_cvtsi2sd
+  ;CHECK:       cvtsi2sdl {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = sitofp i32 %a0 to double
+  ret double %2
+}
+
+define <2 x double> @stack_fold_cvtsi2sd_int(i32 %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsi2sd_int
+  ;CHECK:       cvtsi2sdl {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = call <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double> <double 0x0, double 0x0>, i32 %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double>, i32) nounwind readnone
+
+define double @stack_fold_cvtsi642sd(i64 %a0) optsize {
+  ;CHECK-LABEL: stack_fold_cvtsi642sd
+  ;CHECK:       cvtsi2sdq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = sitofp i64 %a0 to double
+  ret double %2
+}
+
+define <2 x double> @stack_fold_cvtsi642sd_int(i64 %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsi642sd_int
+  ;CHECK:       cvtsi2sdq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> <double 0x0, double 0x0>, i64 %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone
+
+define float @stack_fold_cvtsi2ss(i32 %a0) optsize {
+  ;CHECK-LABEL: stack_fold_cvtsi2ss
+  ;CHECK:       cvtsi2ssl {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = sitofp i32 %a0 to float
+  ret float %2
+}
+
+define <4 x float> @stack_fold_cvtsi2ss_int(i32 %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsi2ss_int
+  ;CHECK:  cvtsi2ssl {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = call <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float> <float 0x0, float 0x0, float 0x0, float 0x0>, i32 %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float>, i32) nounwind readnone
+
+define float @stack_fold_cvtsi642ss(i64 %a0) optsize {
+  ;CHECK-LABEL: stack_fold_cvtsi642ss
+  ;CHECK:       cvtsi2ssq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = sitofp i64 %a0 to float
+  ret float %2
+}
+
+define <4 x float> @stack_fold_cvtsi642ss_int(i64 %a0) {
+  ;CHECK-LABEL: stack_fold_cvtsi642ss_int
+  ;CHECK:  cvtsi2ssq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> <float 0x0, float 0x0, float 0x0, float 0x0>, i64 %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone
+
+define double @stack_fold_cvtss2sd(float %a0) optsize {
+  ;CHECK-LABEL: stack_fold_cvtss2sd
+  ;CHECK:       cvtss2sd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fpext float %a0 to double
+  ret double %2
+}
+
+define <2 x double> @stack_fold_cvtss2sd_int(<4 x float> %a0) optsize {
+  ;CHECK-LABEL: stack_fold_cvtss2sd_int
+  ;CHECK:       cvtss2sd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double> <double 0x0, double 0x0>, <4 x float> %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double>, <4 x float>) nounwind readnone
+
+; TODO stack_fold_cvtss2si
+
+define i32 @stack_fold_cvtss2si_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtss2si_int
+  ;CHECK:       cvtss2si {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse.cvtss2si(<4 x float> %a0)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse.cvtss2si(<4 x float>) nounwind readnone
+
+; TODO stack_fold_cvtss2si64
+
+define i64 @stack_fold_cvtss2si64_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtss2si64_int
+  ;CHECK:       cvtss2si {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %a0)
+  ret i64 %2
+}
+declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) nounwind readnone
+
+define <4 x i32> @stack_fold_cvttpd2dq(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttpd2dq
+  ;CHECK:       cvttpd2dq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>) nounwind readnone
+
+define <4 x i32> @stack_fold_cvttps2dq(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttps2dq
+  ;CHECK:       cvttps2dq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fptosi <4 x float> %a0 to <4 x i32>
+  ret <4 x i32> %2
+}
+
+define i32 @stack_fold_cvttsd2si(double %a0) {
+  ;CHECK-LABEL: stack_fold_cvttsd2si
+  ;CHECK:       cvttsd2si {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fptosi double %a0 to i32
+  ret i32 %2
+}
+
+define i32 @stack_fold_cvttsd2si_int(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttsd2si_int
+  ;CHECK:       cvttsd2si {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %a0)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) nounwind readnone
+
+define i64 @stack_fold_cvttsd2si64(double %a0) {
+  ;CHECK-LABEL: stack_fold_cvttsd2si64
+  ;CHECK:       cvttsd2si {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fptosi double %a0 to i64
+  ret i64 %2
+}
+
+define i64 @stack_fold_cvttsd2si64_int(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttsd2si64_int
+  ;CHECK:       cvttsd2si {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0)
+  ret i64 %2
+}
+declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
+
+define i32 @stack_fold_cvttss2si(float %a0) {
+  ;CHECK-LABEL: stack_fold_cvttss2si
+  ;CHECK:       cvttss2si {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fptosi float %a0 to i32
+  ret i32 %2
+}
+
+define i32 @stack_fold_cvttss2si_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttss2si_int
+  ;CHECK:       cvttss2si {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %a0)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone
+
+define i64 @stack_fold_cvttss2si64(float %a0) {
+  ;CHECK-LABEL: stack_fold_cvttss2si64
+  ;CHECK:       cvttss2si {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fptosi float %a0 to i64
+  ret i64 %2
+}
+
+define i64 @stack_fold_cvttss2si64_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttss2si64_int
+  ;CHECK:       cvttss2si {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %a0)
+  ret i64 %2
+}
+declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_divpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_divpd
+  ;CHECK:       divpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fdiv <2 x double> %a0, %a1
+  ret <2 x double> %2
+}
+
+define <4 x float> @stack_fold_divps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_divps
+  ;CHECK:       divps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fdiv <4 x float> %a0, %a1
+  ret <4 x float> %2
+}
+
+define double @stack_fold_divsd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_divsd
+  ;CHECK:       divsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fdiv double %a0, %a1
+  ret double %2
+}
+
+define <2 x double> @stack_fold_divsd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_divsd_int
+  ;CHECK:       divsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.div.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define float @stack_fold_divss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_divss
+  ;CHECK:       divss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fdiv float %a0, %a1
+  ret float %2
+}
+
+define <4 x float> @stack_fold_divss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_divss_int
+  ;CHECK:       divss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.div.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_dppd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_dppd
+  ;CHECK:       dppd $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse41.dppd(<2 x double> %a0, <2 x double> %a1, i8 7)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse41.dppd(<2 x double>, <2 x double>, i8) nounwind readnone
+
+define <4 x float> @stack_fold_dpps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_dpps
+  ;CHECK:       dpps $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse41.dpps(<4 x float> %a0, <4 x float> %a1, i8 7)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse41.dpps(<4 x float>, <4 x float>, i8) nounwind readnone
+
+define i32 @stack_fold_extractps(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_extractps
+  ;CHECK:       extractps $1, {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 4-byte Folded Spill
+  ;CHECK:       movl    {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Reload
+  %1 = extractelement <4 x float> %a0, i32 1
+  %2 = bitcast float %1 to i32
+  %3 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  ret i32 %2
+}
+
+define <2 x double> @stack_fold_haddpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_haddpd
+  ;CHECK:       haddpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_haddps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_haddps
+  ;CHECK:       haddps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_hsubpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_hsubpd
+  ;CHECK:       hsubpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_hsubps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_hsubps
+  ;CHECK:       hsubps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
+
+; TODO stack_fold_insertps
+
+define <2 x double> @stack_fold_maxpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_maxpd
+  ;CHECK:       maxpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_maxps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_maxps
+  ;CHECK:       maxps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind readnone
+
+define double @stack_fold_maxsd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_maxsd
+  ;CHECK:       maxsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp ogt double %a0, %a1
+  %3 = select i1 %2, double %a0, double %a1
+  ret double %3
+}
+
+define <2 x double> @stack_fold_maxsd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_maxsd_int
+  ;CHECK:       maxsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define float @stack_fold_maxss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_maxss
+  ;CHECK:       maxss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp ogt float %a0, %a1
+  %3 = select i1 %2, float %a0, float %a1
+  ret float %3
+}
+
+define <4 x float> @stack_fold_maxss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_maxss_int
+  ;CHECK:       maxss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_minpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_minpd
+  ;CHECK:       minpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_minps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_minps
+  ;CHECK:       minps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone
+
+define double @stack_fold_minsd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_minsd
+  ;CHECK:       minsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp olt double %a0, %a1
+  %3 = select i1 %2, double %a0, double %a1
+  ret double %3
+}
+
+define <2 x double> @stack_fold_minsd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_minsd_int
+  ;CHECK:       minsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define float @stack_fold_minss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_minss
+  ;CHECK:       minss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp olt float %a0, %a1
+  %3 = select i1 %2, float %a0, float %a1
+  ret float %3
+}
+
+define <4 x float> @stack_fold_minss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_minss_int
+  ;CHECK:       minss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_movddup(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_movddup
+  ;CHECK:   movddup {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <2 x double> %a0, <2 x double> undef, <2 x i32> <i32 0, i32 0>
+  ret <2 x double> %2
+}
+; TODO stack_fold_movhpd (load / store)
+; TODO stack_fold_movhps (load / store)
+
+; TODO stack_fold_movlpd (load / store)
+; TODO stack_fold_movlps (load / store)
+
+define <4 x float> @stack_fold_movshdup(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_movshdup
+  ;CHECK:       movshdup {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
+  ret <4 x float> %2
+}
+
+define <4 x float> @stack_fold_movsldup(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_movsldup
+  ;CHECK:       movsldup {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
+  ret <4 x float> %2
+}
+
+define <2 x double> @stack_fold_mulpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_mulpd
+  ;CHECK:       mulpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fmul <2 x double> %a0, %a1
+  ret <2 x double> %2
+}
+
+define <4 x float> @stack_fold_mulps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_mulps
+  ;CHECK:       mulps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fmul <4 x float> %a0, %a1
+  ret <4 x float> %2
+}
+
+define double @stack_fold_mulsd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_mulsd
+  ;CHECK:       mulsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fmul double %a0, %a1
+  ret double %2
+}
+
+define <2 x double> @stack_fold_mulsd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_mulsd_int
+  ;CHECK:       mulsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.mul.sd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.mul.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define float @stack_fold_mulss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_mulss
+  ;CHECK:       mulss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fmul float %a0, %a1
+  ret float %2
+}
+
+define <4 x float> @stack_fold_mulss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_mulss_int
+  ;CHECK:       mulss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.mul.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_orpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_orpd
+  ;CHECK:       orpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <2 x double> %a0 to <2 x i64>
+  %3 = bitcast <2 x double> %a1 to <2 x i64>
+  %4 = or <2 x i64> %2, %3
+  %5 = bitcast <2 x i64> %4 to <2 x double>
+  ; fadd forces execution domain
+  %6 = fadd <2 x double> %5, <double 0x0, double 0x0>
+  ret <2 x double> %6
+}
+
+define <4 x float> @stack_fold_orps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_orps
+  ;CHECK:       orps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <4 x float> %a0 to <2 x i64>
+  %3 = bitcast <4 x float> %a1 to <2 x i64>
+  %4 = or <2 x i64> %2, %3
+  %5 = bitcast <2 x i64> %4 to <4 x float>
+  ; fadd forces execution domain
+  %6 = fadd <4 x float> %5, <float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <4 x float> %6
+}
+
+; TODO stack_fold_rcpps
+
+define <4 x float> @stack_fold_rcpps_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_rcpps_int
+  ;CHECK:       rcpps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>) nounwind readnone
+
+; TODO stack_fold_rcpss
+; TODO stack_fold_rcpss_int
+
+define <2 x double> @stack_fold_roundpd(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_roundpd
+  ;CHECK:       roundpd $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse41.round.pd(<2 x double> %a0, i32 7)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse41.round.pd(<2 x double>, i32) nounwind readnone
+
+define <4 x float> @stack_fold_roundps(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_roundps
+  ;CHECK:       roundps $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %a0, i32 7)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse41.round.ps(<4 x float>, i32) nounwind readnone
+
+; TODO stack_fold_roundsd
+; TODO stack_fold_roundsd_int
+
+; TODO stack_fold_roundss
+; TODO stack_fold_roundss_int
+
+; TODO stack_fold_rsqrtps
+
+define <4 x float> @stack_fold_rsqrtps_int(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_rsqrtps_int
+  ;CHECK:       rsqrtps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float>) nounwind readnone
+
+; TODO stack_fold_rsqrtss
+; TODO stack_fold_rsqrtss_int
+
+define <2 x double> @stack_fold_shufpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_shufpd
+  ;CHECK:       shufpd $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 1, i32 2>
+  ret <2 x double> %2
+}
+
+define <4 x float> @stack_fold_shufps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_shufps
+  ;CHECK:       shufps $200, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 0, i32 2, i32 4, i32 7>
+  ret <4 x float> %2
+}
+
+define <2 x double> @stack_fold_sqrtpd(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_sqrtpd
+  ;CHECK:       sqrtpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double> %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_sqrtps(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_sqrtps
+  ;CHECK:       sqrtps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>) nounwind readnone
+
+; TODO stack_fold_sqrtsd
+declare double @llvm.sqrt.f64(double) nounwind readnone
+
+; TODO stack_fold_sqrtsd_int
+declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
+
+; TODO stack_fold_sqrtss
+declare float @llvm.sqrt.f32(float) nounwind readnone
+
+; TODO stack_fold_sqrtss_int
+declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_subpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_subpd
+  ;CHECK:       subpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fsub <2 x double> %a0, %a1
+  ret <2 x double> %2
+}
+
+define <4 x float> @stack_fold_subps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_subps
+  ;CHECK:       subps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fsub <4 x float> %a0, %a1
+  ret <4 x float> %2
+}
+
+define double @stack_fold_subsd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_subsd
+  ;CHECK:       subsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fsub double %a0, %a1
+  ret double %2
+}
+
+define <2 x double> @stack_fold_subsd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_subsd_int
+  ;CHECK:       subsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %a0, <2 x double> %a1)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse2.sub.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define float @stack_fold_subss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_subss
+  ;CHECK:       subss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fsub float %a0, %a1
+  ret float %2
+}
+
+define <4 x float> @stack_fold_subss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_subss_int
+  ;CHECK:       subss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %a0, <4 x float> %a1)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define i32 @stack_fold_ucomisd(double %a0, double %a1) {
+  ;CHECK-LABEL: stack_fold_ucomisd
+  ;CHECK:       ucomisd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp ueq double %a0, %a1
+  %3 = select i1 %2, i32 1, i32 -1
+  ret i32 %3
+}
+
+define i32 @stack_fold_ucomisd_int(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_ucomisd_int
+  ;CHECK:       ucomisd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %a0, <2 x double> %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define i32 @stack_fold_ucomiss(float %a0, float %a1) {
+  ;CHECK-LABEL: stack_fold_ucomiss
+  ;CHECK:       ucomiss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = fcmp ueq float %a0, %a1
+  %3 = select i1 %2, i32 1, i32 -1
+  ret i32 %3
+}
+
+define i32 @stack_fold_ucomiss_int(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_ucomiss_int
+  ;CHECK:       ucomiss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse.ucomieq.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_unpckhpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_unpckhpd
+  ;CHECK:       unpckhpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 1, i32 3>
+  ; fadd forces execution domain
+  %3 = fadd <2 x double> %2, <double 0x0, double 0x0>
+  ret <2 x double> %3
+}
+
+define <4 x float> @stack_fold_unpckhps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_unpckhps
+  ;CHECK:       unpckhps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+  ; fadd forces execution domain
+  %3 = fadd <4 x float> %2, <float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <4 x float> %3
+}
+
+define <2 x double> @stack_fold_unpcklpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_unpcklpd
+  ;CHECK:       unpcklpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 0, i32 2>
+  ; fadd forces execution domain
+  %3 = fadd <2 x double> %2, <double 0x0, double 0x0>
+  ret <2 x double> %3
+}
+
+define <4 x float> @stack_fold_unpcklps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_unpcklps
+  ;CHECK:       unpcklps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+  ; fadd forces execution domain
+  %3 = fadd <4 x float> %2, <float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <4 x float> %3
+}
+
+define <2 x double> @stack_fold_xorpd(<2 x double> %a0, <2 x double> %a1) {
+  ;CHECK-LABEL: stack_fold_xorpd
+  ;CHECK:       xorpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <2 x double> %a0 to <2 x i64>
+  %3 = bitcast <2 x double> %a1 to <2 x i64>
+  %4 = xor <2 x i64> %2, %3
+  %5 = bitcast <2 x i64> %4 to <2 x double>
+  ; fadd forces execution domain
+  %6 = fadd <2 x double> %5, <double 0x0, double 0x0>
+  ret <2 x double> %6
+}
+
+define <4 x float> @stack_fold_xorps(<4 x float> %a0, <4 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_xorps
+  ;CHECK:       xorps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = bitcast <4 x float> %a0 to <2 x i64>
+  %3 = bitcast <4 x float> %a1 to <2 x i64>
+  %4 = xor <2 x i64> %2, %3
+  %5 = bitcast <2 x i64> %4 to <4 x float>
+  ; fadd forces execution domain
+  %6 = fadd <4 x float> %5, <float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <4 x float> %6
+}
diff --git a/test/CodeGen/X86/stack-folding-int-avx1.ll b/test/CodeGen/X86/stack-folding-int-avx1.ll
new file mode 100644
index 000000000000..fec297d5e9d4
--- /dev/null
+++ b/test/CodeGen/X86/stack-folding-int-avx1.ll
@@ -0,0 +1,1156 @@
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx,+aes,+pclmul < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-unknown"
+
+; Stack reload folding tests.
+;
+; By including a nop call with sideeffects we can force a partial register spill of the
+; relevant registers and check that the reload is correctly folded into the instruction.
+
+define <2 x i64> @stack_fold_aesdec(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_aesdec
+  ;CHECK:       vaesdec {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <2 x i64> @stack_fold_aesdeclast(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_aesdeclast
+  ;CHECK:       vaesdeclast {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <2 x i64> @stack_fold_aesenc(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_aesenc
+  ;CHECK:       vaesenc {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <2 x i64> @stack_fold_aesenclast(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_aesenclast
+  ;CHECK:       vaesenclast {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <2 x i64> @stack_fold_aesimc(<2 x i64> %a0) {
+  ;CHECK-LABEL: stack_fold_aesimc
+  ;CHECK:       vaesimc {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64>) nounwind readnone
+
+define <2 x i64> @stack_fold_aeskeygenassist(<2 x i64> %a0) {
+  ;CHECK-LABEL: stack_fold_aeskeygenassist
+  ;CHECK:       vaeskeygenassist $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64> %a0, i8 7)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8) nounwind readnone
+
+define <4 x i32> @stack_fold_movd_load(i32 %a0) {
+  ;CHECK-LABEL: stack_fold_movd_load
+  ;CHECK:       movd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = insertelement <4 x i32> zeroinitializer, i32 %a0, i32 0
+  ; add forces execution domain
+  %3 = add <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %3
+}
+
+define i32 @stack_fold_movd_store(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_movd_store
+  ;CHECK:       movd {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 4-byte Folded Spill
+  ; add forces execution domain
+  %1 = add <4 x i32> %a0, <i32 1, i32 1, i32 1, i32 1>
+  %2 = extractelement <4 x i32> %1, i32 0
+  %3 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  ret i32 %2
+}
+
+define <2 x i64> @stack_fold_movq_load(<2 x i64> %a0) {
+  ;CHECK-LABEL: stack_fold_movq_load
+  ;CHECK:       movq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <2 x i64> %a0, <2 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>
+  ; add forces execution domain
+  %3 = add <2 x i64> %2, <i64 1, i64 1>
+  ret <2 x i64> %3
+}
+
+define i64 @stack_fold_movq_store(<2 x i64> %a0) {
+  ;CHECK-LABEL: stack_fold_movq_store
+  ;CHECK:       movq {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 8-byte Folded Spill
+  ; add forces execution domain
+  %1 = add <2 x i64> %a0, <i64 1, i64 1>
+  %2 = extractelement <2 x i64> %1, i32 0
+  %3 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  ret i64 %2
+}
+
+define <8 x i16> @stack_fold_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_mpsadbw
+  ;CHECK:       vmpsadbw $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> %a0, <16 x i8> %a1, i8 7)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8>, <16 x i8>, i8) nounwind readnone
+
+define <16 x i8> @stack_fold_pabsb(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pabsb
+  ;CHECK:       vpabsb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %a0)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_pabsd(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pabsd
+  ;CHECK:       vpabsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_pabsw(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pabsw
+  ;CHECK:       vpabsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %a0)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_packssdw(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_packssdw
+  ;CHECK:       vpackssdw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %a0, <4 x i32> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <16 x i8> @stack_fold_packsswb(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_packsswb
+  ;CHECK:       vpacksswb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_packusdw(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_packusdw
+  ;CHECK:       vpackusdw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <16 x i8> @stack_fold_packuswb(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_packuswb
+  ;CHECK:       vpackuswb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_paddb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_paddb
+  ;CHECK:       vpaddb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = add <16 x i8> %a0, %a1
+  ret <16 x i8> %2
+}
+
+define <4 x i32> @stack_fold_paddd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_paddd
+  ;CHECK:       vpaddd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = add <4 x i32> %a0, %a1
+  ret <4 x i32> %2
+}
+
+define <2 x i64> @stack_fold_paddq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_paddq
+  ;CHECK:       vpaddq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = add <2 x i64> %a0, %a1
+  ret <2 x i64> %2
+}
+
+define <16 x i8> @stack_fold_paddsb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_paddsb
+  ;CHECK:       vpaddsb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_paddsw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_paddsw
+  ;CHECK:       vpaddsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_paddusb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_paddusb
+  ;CHECK:       vpaddusb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_paddusw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_paddusw
+  ;CHECK:       vpaddusw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_paddw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_paddw
+  ;CHECK:       vpaddw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = add <8 x i16> %a0, %a1
+  ret <8 x i16> %2
+}
+
+define <16 x i8> @stack_fold_palignr(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_palignr
+  ;CHECK:       vpalignr $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <16 x i8> %a1, <16 x i8> %a0, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
+  ret <16 x i8> %2
+}
+
+define <16 x i8> @stack_fold_pand(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pand
+  ;CHECK:       vpand {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = and <16 x i8> %a0, %a1
+  ; add forces execution domain
+  %3 = add <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %3
+}
+
+define <16 x i8> @stack_fold_pandn(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pandn
+  ;CHECK:       vpandn {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = xor <16 x i8> %a0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %3 = and <16 x i8> %2, %a1
+  ; add forces execution domain
+  %4 = add <16 x i8> %3, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %4
+}
+
+define <16 x i8> @stack_fold_pavgb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pavgb
+  ;CHECK:       vpavgb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_pavgw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pavgw
+  ;CHECK:       vpavgw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_pblendvb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %c) {
+  ;CHECK-LABEL: stack_fold_pblendvb
+  ;CHECK:       vpblendvb {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %a1, <16 x i8> %c, <16 x i8> %a0)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_pblendw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pblendw
+  ;CHECK:       vpblendw $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %a0, <8 x i16> %a1, i8 7)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i8) nounwind readnone
+
+define <2 x i64> @stack_fold_pclmulqdq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_pclmulqdq
+  ;CHECK:       vpclmulqdq $0, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a0, <2 x i64> %a1, i8 0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.pclmulqdq(<2 x i64>, <2 x i64>, i8) nounwind readnone
+
+define <16 x i8> @stack_fold_pcmpeqb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpeqb
+  ;CHECK:       vpcmpeqb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp eq <16 x i8> %a0, %a1
+  %3 = sext <16 x i1> %2 to <16 x i8>
+  ret <16 x i8> %3
+}
+
+define <4 x i32> @stack_fold_pcmpeqd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpeqd
+  ;CHECK:       vpcmpeqd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp eq <4 x i32> %a0, %a1
+  %3 = sext <4 x i1> %2 to <4 x i32>
+  ret <4 x i32> %3
+}
+
+define <2 x i64> @stack_fold_pcmpeqq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpeqq
+  ;CHECK:       vpcmpeqq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp eq <2 x i64> %a0, %a1
+  %3 = sext <2 x i1> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <8 x i16> @stack_fold_pcmpeqw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpeqw
+  ;CHECK:       vpcmpeqw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp eq <8 x i16> %a0, %a1
+  %3 = sext <8 x i1> %2 to <8 x i16>
+  ret <8 x i16> %3
+}
+
+define i32 @stack_fold_pcmpestri(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpestri
+  ;CHECK:       vpcmpestri $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{rax},~{flags}"()
+  %2 = call i32 @llvm.x86.sse42.pcmpestri128(<16 x i8> %a0, i32 7, <16 x i8> %a1, i32 7, i8 7)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse42.pcmpestri128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
+
+define <16 x i8> @stack_fold_pcmpestrm(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpestrm
+  ;CHECK:       vpcmpestrm $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{rax},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8> %a0, i32 7, <16 x i8> %a1, i32 7, i8 7)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
+
+define <16 x i8> @stack_fold_pcmpgtb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpgtb
+  ;CHECK:       vpcmpgtb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp sgt <16 x i8> %a0, %a1
+  %3 = sext <16 x i1> %2 to <16 x i8>
+  ret <16 x i8> %3
+}
+
+define <4 x i32> @stack_fold_pcmpgtd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpgtd
+  ;CHECK:       vpcmpgtd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp sgt <4 x i32> %a0, %a1
+  %3 = sext <4 x i1> %2 to <4 x i32>
+  ret <4 x i32> %3
+}
+
+define <2 x i64> @stack_fold_pcmpgtq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpgtq
+  ;CHECK:       vpcmpgtq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp sgt <2 x i64> %a0, %a1
+  %3 = sext <2 x i1> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <8 x i16> @stack_fold_pcmpgtw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpgtw
+  ;CHECK:       vpcmpgtw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp sgt <8 x i16> %a0, %a1
+  %3 = sext <8 x i1> %2 to <8 x i16>
+  ret <8 x i16> %3
+}
+
+define i32 @stack_fold_pcmpistri(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpistri
+  ;CHECK:       vpcmpistri $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse42.pcmpistri128(<16 x i8> %a0, <16 x i8> %a1, i8 7)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse42.pcmpistri128(<16 x i8>, <16 x i8>, i8) nounwind readnone
+
+define <16 x i8> @stack_fold_pcmpistrm(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpistrm
+  ;CHECK:       vpcmpistrm $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8> %a0, <16 x i8> %a1, i8 7)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8>, <16 x i8>, i8) nounwind readnone
+
+; TODO stack_fold_pextrb
+
+define i32 @stack_fold_pextrd(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pextrd
+  ;CHECK:       pextrd $1, {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 4-byte Folded Spill
+  ;CHECK:       movl    {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Reload
+  %1 = extractelement <4 x i32> %a0, i32 1
+  %2 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  ret i32 %1
+}
+
+define i64 @stack_fold_pextrq(<2 x i64> %a0) {
+  ;CHECK-LABEL: stack_fold_pextrq
+  ;CHECK:       pextrq $1, {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 8-byte Folded Spill
+  ;CHECK:       movq    {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Reload
+  %1 = extractelement <2 x i64> %a0, i32 1
+  %2 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  ret i64 %1
+}
+
+; TODO stack_fold_pextrw
+
+define <4 x i32> @stack_fold_phaddd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_phaddd
+  ;CHECK:       vphaddd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_phaddsw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_phaddsw
+  ;CHECK:       vphaddsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_phaddw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_phaddw
+  ;CHECK:       vphaddw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_phminposuw(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_phminposuw
+  ;CHECK:       vphminposuw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16> %a0)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_phsubd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_phsubd
+  ;CHECK:       vphsubd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_phsubsw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_phsubsw
+  ;CHECK:       vphsubsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_phsubw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_phsubw
+  ;CHECK:       vphsubw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_pinsrb(<16 x i8> %a0, i8 %a1) {
+  ;CHECK-LABEL: stack_fold_pinsrb
+  ;CHECK:       vpinsrb $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = insertelement <16 x i8> %a0, i8 %a1, i32 1
+  ret <16 x i8> %2
+}
+
+define <4 x i32> @stack_fold_pinsrd(<4 x i32> %a0, i32 %a1) {
+  ;CHECK-LABEL: stack_fold_pinsrd
+  ;CHECK:       vpinsrd $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = insertelement <4 x i32> %a0, i32 %a1, i32 1
+  ret <4 x i32> %2
+}
+
+define <2 x i64> @stack_fold_pinsrq(<2 x i64> %a0, i64 %a1) {
+  ;CHECK-LABEL: stack_fold_pinsrq
+  ;CHECK:       vpinsrq $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = insertelement <2 x i64> %a0, i64 %a1, i32 1
+  ret <2 x i64> %2
+}
+
+define <8 x i16> @stack_fold_pinsrw(<8 x i16> %a0, i16 %a1) {
+  ;CHECK-LABEL: stack_fold_pinsrw
+  ;CHECK:       vpinsrw $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = insertelement <8 x i16> %a0, i16 %a1, i32 1
+  ret <8 x i16> %2
+}
+
+define <8 x i16> @stack_fold_pmaddubsw(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaddubsw
+  ;CHECK:       vpmaddubsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8> %a0, <16 x i8> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_pmaddwd(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaddwd
+  ;CHECK:       vpmaddwd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a0, <8 x i16> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_pmaxsb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxsb
+  ;CHECK:       vpmaxsb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_pmaxsd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxsd
+  ;CHECK:       vpmaxsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_pmaxsw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxsw
+  ;CHECK:       vpmaxsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_pmaxub(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxub
+  ;CHECK:       vpmaxub {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_pmaxud(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxud
+  ;CHECK:       vpmaxud {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_pmaxuw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxuw
+  ;CHECK:       vpmaxuw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_pminsb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pminsb
+  ;CHECK:       vpminsb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_pminsd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pminsd
+  ;CHECK:       vpminsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_pminsw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pminsw
+  ;CHECK:       vpminsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_pminub(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pminub
+  ;CHECK:       vpminub {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_pminud(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pminud
+  ;CHECK:       vpminud {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_pminuw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pminuw
+  ;CHECK:       vpminuw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_pmovsxbd(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxbd
+  ;CHECK:       vpmovsxbd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
+
+define <2 x i64> @stack_fold_pmovsxbq(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxbq
+  ;CHECK:       pmovsxbq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_pmovsxbw(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxbw
+  ;CHECK:       vpmovsxbw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8> %a0)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8>) nounwind readnone
+
+define <2 x i64> @stack_fold_pmovsxdq(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxdq
+  ;CHECK:       vpmovsxdq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32>) nounwind readnone
+
+define <4 x i32> @stack_fold_pmovsxwd(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxwd
+  ;CHECK:       vpmovsxwd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
+
+define <2 x i64> @stack_fold_pmovsxwq(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxwq
+  ;CHECK:       vpmovsxwq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_pmovzxbd(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxbd
+  ;CHECK:       vpmovzxbd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <16 x i8> %a0, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 16, i32 17, i32 18, i32 1, i32 19, i32 20, i32 21, i32 2, i32 22, i32 23, i32 24, i32 3, i32 25, i32 26, i32 27>
+  %3 = bitcast <16 x i8> %2 to <4 x i32>
+  ret <4 x i32> %3
+}
+
+define <2 x i64> @stack_fold_pmovzxbq(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxbq
+  ;CHECK:       vpmovzxbq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <16 x i8> %a0, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 1, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28>
+  %3 = bitcast <16 x i8> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <8 x i16> @stack_fold_pmovzxbw(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxbw
+  ;CHECK:       vpmovzxbw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <16 x i8> %a0, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
+  %3 = bitcast <16 x i8> %2 to <8 x i16>
+  ret <8 x i16> %3
+}
+
+define <2 x i64> @stack_fold_pmovzxdq(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxdq
+  ;CHECK:       vpmovzxdq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x i32> %a0, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+  %3 = bitcast <4 x i32> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <4 x i32> @stack_fold_pmovzxwd(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxwd
+  ;CHECK:       vpmovzxwd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i16> %a0, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+  %3 = bitcast <8 x i16> %2 to <4 x i32>
+  ret <4 x i32> %3
+}
+
+define <2 x i64> @stack_fold_pmovzxwq(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxwq
+  ;CHECK:       vpmovzxwq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i16> %a0, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 9, i32 10, i32 1, i32 11, i32 12, i32 13>
+  %3 = bitcast <8 x i16> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <2 x i64> @stack_fold_pmuldq(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pmuldq
+  ;CHECK:       vpmuldq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> %a0, <4 x i32> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_pmulhrsw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmulhrsw
+  ;CHECK:       vpmulhrsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_pmulhuw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmulhuw
+  ;CHECK:       vpmulhuw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_pmulhw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmulhw
+  ;CHECK:       vpmulhw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_pmulld(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pmulld
+  ;CHECK:       vpmulld {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = mul <4 x i32> %a0, %a1
+  ret <4 x i32> %2
+}
+
+define <8 x i16> @stack_fold_pmullw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmullw
+  ;CHECK:       vpmullw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = mul <8 x i16> %a0, %a1
+  ret <8 x i16> %2
+}
+
+define <2 x i64> @stack_fold_pmuludq(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pmuludq
+  ;CHECK:       vpmuludq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %a0, <4 x i32> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <16 x i8> @stack_fold_por(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_por
+  ;CHECK:       vpor {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = or <16 x i8> %a0, %a1
+  ; add forces execution domain
+  %3 = add <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %3
+}
+
+define <2 x i64> @stack_fold_psadbw(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_psadbw
+  ;CHECK:       vpsadbw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %a0, <16 x i8> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <16 x i8> @stack_fold_pshufb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pshufb
+  ;CHECK:       vpshufb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_pshufd(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pshufd
+  ;CHECK:       vpshufd $27, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  ret <4 x i32> %2
+}
+
+define <8 x i16> @stack_fold_pshufhw(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pshufhw
+  ;CHECK:       vpshufhw $11, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 6, i32 4, i32 4>
+  ret <8 x i16> %2
+}
+
+define <8 x i16> @stack_fold_pshuflw(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pshuflw
+  ;CHECK:       vpshuflw $27, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>
+  ret <8 x i16> %2
+}
+
+define <16 x i8> @stack_fold_psignb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_psignb
+  ;CHECK:       vpsignb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_psignd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psignd
+  ;CHECK:       vpsignd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_psignw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psignw
+  ;CHECK:       vpsignw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_pslld(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pslld
+  ;CHECK:       vpslld {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <2 x i64> @stack_fold_psllq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_psllq
+  ;CHECK:       vpsllq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i16> @stack_fold_psllw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psllw
+  ;CHECK:       vpsllw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_psrad(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psrad
+  ;CHECK:       vpsrad {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_psraw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psraw
+  ;CHECK:       vpsraw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_psrld(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psrld
+  ;CHECK:       vpsrld {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <2 x i64> @stack_fold_psrlq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_psrlq
+  ;CHECK:       vpsrlq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i16> @stack_fold_psrlw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psrlw
+  ;CHECK:       vpsrlw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_psubb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_psubb
+  ;CHECK:       vpsubb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = sub <16 x i8> %a0, %a1
+  ret <16 x i8> %2
+}
+
+define <4 x i32> @stack_fold_psubd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psubd
+  ;CHECK:       vpsubd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = sub <4 x i32> %a0, %a1
+  ret <4 x i32> %2
+}
+
+define <2 x i64> @stack_fold_psubq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_psubq
+  ;CHECK:       vpsubq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = sub <2 x i64> %a0, %a1
+  ret <2 x i64> %2
+}
+
+define <16 x i8> @stack_fold_psubsb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_psubsb
+  ;CHECK:       vpsubsb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_psubsw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psubsw
+  ;CHECK:       vpsubsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_psubusb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_psubusb
+  ;CHECK:       vpsubusb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_psubusw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psubusw
+  ;CHECK:       vpsubusw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_psubw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psubw
+  ;CHECK:       vpsubw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = sub <8 x i16> %a0, %a1
+  ret <8 x i16> %2
+}
+
+define i32 @stack_fold_ptest(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_ptest
+  ;CHECK:       vptest {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %a0, <2 x i64> %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone
+
+define i32 @stack_fold_ptest_ymm(<4 x i64> %a0, <4 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_ptest_ymm
+  ;CHECK:       vptest {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a0, <4 x i64> %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.avx.ptestc.256(<4 x i64>, <4 x i64>) nounwind readnone
+
+define <16 x i8> @stack_fold_punpckhbw(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_punpckhbw
+  ;CHECK:       vpunpckhbw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <16 x i8> %a0, <16 x i8> %a1, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
+  ret <16 x i8> %2
+}
+
+define <4 x i32> @stack_fold_punpckhdq(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_punpckhdq
+  ;CHECK:       vpunpckhdq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+  ; add forces execution domain
+  %3 = add <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %3
+}
+
+define <2 x i64> @stack_fold_punpckhqdq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_punpckhqdq
+  ;CHECK:       vpunpckhqdq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <2 x i64> %a0, <2 x i64> %a1, <2 x i32> <i32 1, i32 3>
+  ; add forces execution domain
+  %3 = add <2 x i64> %2, <i64 1, i64 1>
+  ret <2 x i64> %3
+}
+
+define <8 x i16> @stack_fold_punpckhwd(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_punpckhwd
+  ;CHECK:       vpunpckhwd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i16> %a0, <8 x i16> %a1, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+  ret <8 x i16> %2
+}
+
+define <16 x i8> @stack_fold_punpcklbw(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_punpcklbw
+  ;CHECK:       vpunpcklbw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <16 x i8> %a0, <16 x i8> %a1, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
+  ret <16 x i8> %2
+}
+
+define <4 x i32> @stack_fold_punpckldq(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_punpckldq
+  ;CHECK:       vpunpckldq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+  ; add forces execution domain
+  %3 = add <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %3
+}
+
+define <2 x i64> @stack_fold_punpcklqdq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_punpcklqdq
+  ;CHECK:       vpunpcklqdq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <2 x i64> %a0, <2 x i64> %a1, <2 x i32> <i32 0, i32 2>
+  ; add forces execution domain
+  %3 = add <2 x i64> %2, <i64 1, i64 1>
+  ret <2 x i64> %3
+}
+
+define <8 x i16> @stack_fold_punpcklwd(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_punpcklwd
+  ;CHECK:       vpunpcklwd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i16> %a0, <8 x i16> %a1, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+  ret <8 x i16> %2
+}
+
+define <16 x i8> @stack_fold_pxor(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pxor
+  ;CHECK:       vpxor {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = xor <16 x i8> %a0, %a1
+  ; add forces execution domain
+  %3 = add <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %3
+}
diff --git a/test/CodeGen/X86/stack-folding-int-avx2.ll b/test/CodeGen/X86/stack-folding-int-avx2.ll
new file mode 100644
index 000000000000..e930d244638a
--- /dev/null
+++ b/test/CodeGen/X86/stack-folding-int-avx2.ll
@@ -0,0 +1,1211 @@
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-unknown"
+
+; Stack reload folding tests.
+;
+; By including a nop call with sideeffects we can force a partial register spill of the
+; relevant registers and check that the reload is correctly folded into the instruction.
+
+define <4 x double> @stack_fold_broadcastsd_ymm(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_broadcastsd_ymm
+  ;CHECK:       vbroadcastsd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.avx2.vbroadcast.sd.pd.256(<2 x double> %a0)
+  ; fadd forces execution domain
+  %3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %3
+}
+declare <4 x double> @llvm.x86.avx2.vbroadcast.sd.pd.256(<2 x double>) nounwind readonly
+
+define <4 x float> @stack_fold_broadcastss(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_broadcastss
+  ;CHECK:       vbroadcastss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.avx2.vbroadcast.ss.ps(<4 x float> %a0)
+  ; fadd forces execution domain
+  %3 = fadd <4 x float> %2, <float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <4 x float> %3
+}
+declare <4 x float> @llvm.x86.avx2.vbroadcast.ss.ps(<4 x float>) nounwind readonly
+
+define <8 x float> @stack_fold_broadcastss_ymm(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_broadcastss_ymm
+  ;CHECK:       vbroadcastss {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.avx2.vbroadcast.ss.ps.256(<4 x float> %a0)
+  ; fadd forces execution domain
+  %3 = fadd <8 x float> %2, <float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0, float 0x0>
+  ret <8 x float> %3
+}
+declare <8 x float> @llvm.x86.avx2.vbroadcast.ss.ps.256(<4 x float>) nounwind readonly
+
+define <4 x i32> @stack_fold_extracti128(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_extracti128
+  ;CHECK:       vextracti128 $1, {{%ymm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 16-byte Folded Spill
+  ; add forces execution domain
+  %1 = add <8 x i32> %a0, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+  %2 = shufflevector <8 x i32> %1, <8 x i32> %a1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+  %3 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  ret <4 x i32> %2
+}
+
+define <8 x i32> @stack_fold_inserti128(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_inserti128
+  ;CHECK:       vinserti128 $1, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x i32> %a0, <4 x i32> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  ; add forces execution domain
+  %3 = add <8 x i32> %2, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+  ret <8 x i32> %3
+}
+
+define <16 x i16> @stack_fold_mpsadbw(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_mpsadbw
+  ;CHECK:       vmpsadbw $7, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> %a0, <32 x i8> %a1, i8 7)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8>, <32 x i8>, i8) nounwind readnone
+
+define <32 x i8> @stack_fold_pabsb(<32 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pabsb
+  ;CHECK:       vpabsb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8> %a0)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8>) nounwind readnone
+
+define <8 x i32> @stack_fold_pabsd(<8 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pabsd
+  ;CHECK:       vpabsd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32> %a0)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32>) nounwind readnone
+
+define <16 x i16> @stack_fold_pabsw(<16 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pabsw
+  ;CHECK:       vpabsw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.pabs.w(<16 x i16> %a0)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.pabs.w(<16 x i16>) nounwind readnone
+
+define <16 x i16> @stack_fold_packssdw(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_packssdw
+  ;CHECK:       vpackssdw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %a0, <8 x i32> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32>, <8 x i32>) nounwind readnone
+
+define <32 x i8> @stack_fold_packsswb(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_packsswb
+  ;CHECK:       vpacksswb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> %a0, <16 x i16> %a1)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <16 x i16> @stack_fold_packusdw(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_packusdw
+  ;CHECK:       vpackusdw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> %a0, <8 x i32> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32>, <8 x i32>) nounwind readnone
+
+define <32 x i8> @stack_fold_packuswb(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_packuswb
+  ;CHECK:       vpackuswb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %a0, <16 x i16> %a1)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <32 x i8> @stack_fold_paddb(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_paddb
+  ;CHECK:       vpaddb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = add <32 x i8> %a0, %a1
+  ret <32 x i8> %2
+}
+
+define <8 x i32> @stack_fold_paddd(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_paddd
+  ;CHECK:       vpaddd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = add <8 x i32> %a0, %a1
+  ret <8 x i32> %2
+}
+
+define <4 x i64> @stack_fold_paddq(<4 x i64> %a0, <4 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_paddq
+  ;CHECK:       vpaddq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = add <4 x i64> %a0, %a1
+  ret <4 x i64> %2
+}
+
+define <32 x i8> @stack_fold_paddsb(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_paddsb
+  ;CHECK:       vpaddsb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.padds.b(<32 x i8> %a0, <32 x i8> %a1)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.padds.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+define <16 x i16> @stack_fold_paddsw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_paddsw
+  ;CHECK:       vpaddsw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.padds.w(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.padds.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <32 x i8> @stack_fold_paddusb(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_paddusb
+  ;CHECK:       vpaddusb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.paddus.b(<32 x i8> %a0, <32 x i8> %a1)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.paddus.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+define <16 x i16> @stack_fold_paddusw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_paddusw
+  ;CHECK:       vpaddusw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.paddus.w(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.paddus.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <16 x i16> @stack_fold_paddw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_paddw
+  ;CHECK:       vpaddw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = add <16 x i16> %a0, %a1
+  ret <16 x i16> %2
+}
+
+define <32 x i8> @stack_fold_palignr(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_palignr
+  ;CHECK:       vpalignr $1, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <32 x i8> %a1, <32 x i8> %a0, <32 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48>
+  ret <32 x i8> %2
+}
+
+define <32 x i8> @stack_fold_pand(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pand
+  ;CHECK:       vpand {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = and <32 x i8> %a0, %a1
+  ; add forces execution domain
+  %3 = add <32 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <32 x i8> %3
+}
+
+define <32 x i8> @stack_fold_pandn(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pandn
+  ;CHECK:       vpandn {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = xor <32 x i8> %a0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %3 = and <32 x i8> %2, %a1
+  ; add forces execution domain
+  %4 = add <32 x i8> %3, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <32 x i8> %4
+}
+
+define <32 x i8> @stack_fold_pavgb(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pavgb
+  ;CHECK:       vpavgb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.pavg.b(<32 x i8> %a0, <32 x i8> %a1)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.pavg.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+define <16 x i16> @stack_fold_pavgw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pavgw
+  ;CHECK:       vpavgw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.pavg.w(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.pavg.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_pblendd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pblendd
+  ;CHECK:       vpblendd $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 4, i32 5, i32 6, i32 3>
+  ret <4 x i32> %2
+}
+
+define <8 x i32> @stack_fold_pblendd_ymm(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pblendd_ymm
+  ;CHECK:       vpblendd $7, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i32> %a0, <8 x i32> %a1, <8 x i32> <i32 8, i32 9, i32 10, i32 3, i32 4, i32 5, i32 6, i32 7>
+  ret <8 x i32> %2
+}
+
+define <32 x i8> @stack_fold_pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %c) {
+  ;CHECK-LABEL: stack_fold_pblendvb
+  ;CHECK:       vpblendvb {{%ymm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %a1, <32 x i8> %c, <32 x i8> %a0)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8>, <32 x i8>, <32 x i8>) nounwind readnone
+
+define <16 x i16> @stack_fold_pblendw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pblendw
+  ;CHECK:       vpblendw $7, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i8 7)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16>, <16 x i16>, i8) nounwind readnone
+
+define <16 x i8> @stack_fold_pbroadcastb(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pbroadcastb
+  ;CHECK:       vpbroadcastb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.avx2.pbroadcastb.128(<16 x i8> %a0)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.avx2.pbroadcastb.128(<16 x i8>) nounwind readonly
+
+define <32 x i8> @stack_fold_pbroadcastb_ymm(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pbroadcastb_ymm
+  ;CHECK:       vpbroadcastb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.pbroadcastb.256(<16 x i8> %a0)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.pbroadcastb.256(<16 x i8>) nounwind readonly
+
+define <4 x i32> @stack_fold_pbroadcastd(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pbroadcastd
+  ;CHECK:       vpbroadcastd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.avx2.pbroadcastd.128(<4 x i32> %a0)
+  ; add forces execution domain
+  %3 = add <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %3
+}
+declare <4 x i32> @llvm.x86.avx2.pbroadcastd.128(<4 x i32>) nounwind readonly
+
+define <8 x i32> @stack_fold_pbroadcastd_ymm(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pbroadcastd_ymm
+  ;CHECK:       vpbroadcastd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.pbroadcastd.256(<4 x i32> %a0)
+  ; add forces execution domain
+  %3 = add <8 x i32> %2, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+  ret <8 x i32> %3
+}
+declare <8 x i32> @llvm.x86.avx2.pbroadcastd.256(<4 x i32>) nounwind readonly
+
+define <2 x i64> @stack_fold_pbroadcastq(<2 x i64> %a0) {
+  ;CHECK-LABEL: stack_fold_pbroadcastq
+  ;CHECK:       vpbroadcastq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.avx2.pbroadcastq.128(<2 x i64> %a0)
+  ; add forces execution domain
+  %3 = add <2 x i64> %2, <i64 1, i64 1>
+  ret <2 x i64> %3
+}
+declare <2 x i64> @llvm.x86.avx2.pbroadcastq.128(<2 x i64>) nounwind readonly
+
+define <4 x i64> @stack_fold_pbroadcastq_ymm(<2 x i64> %a0) {
+  ;CHECK-LABEL: stack_fold_pbroadcastq_ymm
+  ;CHECK:       vpbroadcastq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.avx2.pbroadcastq.256(<2 x i64> %a0)
+  ; add forces execution domain
+  %3 = add <4 x i64> %2, <i64 1, i64 1, i64 1, i64 1>
+  ret <4 x i64> %3
+}
+declare <4 x i64> @llvm.x86.avx2.pbroadcastq.256(<2 x i64>) nounwind readonly
+
+define <8 x i16> @stack_fold_pbroadcastw(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pbroadcastw
+  ;CHECK:       vpbroadcastw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.avx2.pbroadcastw.128(<8 x i16> %a0)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.avx2.pbroadcastw.128(<8 x i16>) nounwind readonly
+
+define <16 x i16> @stack_fold_pbroadcastw_ymm(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pbroadcastw_ymm
+  ;CHECK:       vpbroadcastw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.pbroadcastw.256(<8 x i16> %a0)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.pbroadcastw.256(<8 x i16>) nounwind readonly
+
+define <32 x i8> @stack_fold_pcmpeqb(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpeqb
+  ;CHECK:       vpcmpeqb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp eq <32 x i8> %a0, %a1
+  %3 = sext <32 x i1> %2 to <32 x i8>
+  ret <32 x i8> %3
+}
+
+define <8 x i32> @stack_fold_pcmpeqd(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpeqd
+  ;CHECK:       vpcmpeqd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp eq <8 x i32> %a0, %a1
+  %3 = sext <8 x i1> %2 to <8 x i32>
+  ret <8 x i32> %3
+}
+
+define <4 x i64> @stack_fold_pcmpeqq(<4 x i64> %a0, <4 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpeqq
+  ;CHECK:       vpcmpeqq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp eq <4 x i64> %a0, %a1
+  %3 = sext <4 x i1> %2 to <4 x i64>
+  ret <4 x i64> %3
+}
+
+define <16 x i16> @stack_fold_pcmpeqw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpeqw
+  ;CHECK:       vpcmpeqw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp eq <16 x i16> %a0, %a1
+  %3 = sext <16 x i1> %2 to <16 x i16>
+  ret <16 x i16> %3
+}
+
+define <32 x i8> @stack_fold_pcmpgtb(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpgtb
+  ;CHECK:       vpcmpgtb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp sgt <32 x i8> %a0, %a1
+  %3 = sext <32 x i1> %2 to <32 x i8>
+  ret <32 x i8> %3
+}
+
+define <8 x i32> @stack_fold_pcmpgtd(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpgtd
+  ;CHECK:       vpcmpgtd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp sgt <8 x i32> %a0, %a1
+  %3 = sext <8 x i1> %2 to <8 x i32>
+  ret <8 x i32> %3
+}
+
+define <4 x i64> @stack_fold_pcmpgtq(<4 x i64> %a0, <4 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpgtq
+  ;CHECK:       vpcmpgtq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp sgt <4 x i64> %a0, %a1
+  %3 = sext <4 x i1> %2 to <4 x i64>
+  ret <4 x i64> %3
+}
+
+define <16 x i16> @stack_fold_pcmpgtw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpgtw
+  ;CHECK:       vpcmpgtw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp sgt <16 x i16> %a0, %a1
+  %3 = sext <16 x i1> %2 to <16 x i16>
+  ret <16 x i16> %3
+}
+
+define <8 x i32> @stack_fold_perm2i128(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_perm2i128
+  ;CHECK:   vperm2i128 $33, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i32> %a0, <8 x i32> %a1, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
+  ; add forces execution domain
+  %3 = add <8 x i32> %2, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+  ret <8 x i32> %3
+}
+
+define <8 x i32> @stack_fold_permd(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_permd
+  ;CHECK:   vpermd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a1, <8 x i32> %a0)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.permd(<8 x i32>, <8 x i32>) nounwind readonly
+
+define <4 x double> @stack_fold_permpd(<4 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_permpd
+  ;CHECK:   vpermpd $255, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+  ; fadd forces execution domain
+  %3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %3
+}
+
+define <8 x float> @stack_fold_permps(<8 x float> %a0, <8 x float> %a1) {
+  ;CHECK-LABEL: stack_fold_permps
+  ;CHECK:       vpermps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a1, <8 x float> %a0)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.avx2.permps(<8 x float>, <8 x float>) nounwind readonly
+
+define <4 x i64> @stack_fold_permq(<4 x i64> %a0) {
+  ;CHECK-LABEL: stack_fold_permq
+  ;CHECK:   vpermq $255, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+  ; add forces execution domain
+  %3 = add <4 x i64> %2, <i64 1, i64 1, i64 1, i64 1>
+  ret <4 x i64> %3
+}
+
+define <8 x i32> @stack_fold_phaddd(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_phaddd
+  ;CHECK:       vphaddd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32> %a0, <8 x i32> %a1)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32>, <8 x i32>) nounwind readnone
+
+define <16 x i16> @stack_fold_phaddsw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_phaddsw
+  ;CHECK:       vphaddsw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <16 x i16> @stack_fold_phaddw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_phaddw
+  ;CHECK:       vphaddw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <8 x i32> @stack_fold_phsubd(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_phsubd
+  ;CHECK:       vphsubd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32> %a0, <8 x i32> %a1)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32>, <8 x i32>) nounwind readnone
+
+define <16 x i16> @stack_fold_phsubsw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_phsubsw
+  ;CHECK:       vphsubsw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <16 x i16> @stack_fold_phsubw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_phsubw
+  ;CHECK:       vphsubw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <16 x i16> @stack_fold_pmaddubsw(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaddubsw
+  ;CHECK:       vpmaddubsw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %a0, <32 x i8> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8>, <32 x i8>) nounwind readnone
+
+define <8 x i32> @stack_fold_pmaddwd(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaddwd
+  ;CHECK:       vpmaddwd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a0, <16 x i16> %a1)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <32 x i8> @stack_fold_pmaxsb(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxsb
+  ;CHECK:       vpmaxsb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.pmaxs.b(<32 x i8> %a0, <32 x i8> %a1)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.pmaxs.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+define <8 x i32> @stack_fold_pmaxsd(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxsd
+  ;CHECK:       vpmaxsd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.pmaxs.d(<8 x i32> %a0, <8 x i32> %a1)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.pmaxs.d(<8 x i32>, <8 x i32>) nounwind readnone
+
+define <16 x i16> @stack_fold_pmaxsw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxsw
+  ;CHECK:       vpmaxsw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.pmaxs.w(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.pmaxs.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <32 x i8> @stack_fold_pmaxub(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxub
+  ;CHECK:       vpmaxub {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.pmaxu.b(<32 x i8> %a0, <32 x i8> %a1)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.pmaxu.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+define <8 x i32> @stack_fold_pmaxud(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxud
+  ;CHECK:       vpmaxud {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.pmaxu.d(<8 x i32> %a0, <8 x i32> %a1)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.pmaxu.d(<8 x i32>, <8 x i32>) nounwind readnone
+
+define <16 x i16> @stack_fold_pmaxuw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxuw
+  ;CHECK:       vpmaxuw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.pmaxu.w(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.pmaxu.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <32 x i8> @stack_fold_pminsb(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pminsb
+  ;CHECK:       vpminsb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.pmins.b(<32 x i8> %a0, <32 x i8> %a1)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.pmins.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+define <8 x i32> @stack_fold_pminsd(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pminsd
+  ;CHECK:       vpminsd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.pmins.d(<8 x i32> %a0, <8 x i32> %a1)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.pmins.d(<8 x i32>, <8 x i32>) nounwind readnone
+
+define <16 x i16> @stack_fold_pminsw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pminsw
+  ;CHECK:       vpminsw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.pmins.w(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.pmins.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <32 x i8> @stack_fold_pminub(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pminub
+  ;CHECK:       vpminub {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.pminu.b(<32 x i8> %a0, <32 x i8> %a1)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.pminu.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+define <8 x i32> @stack_fold_pminud(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pminud
+  ;CHECK:       vpminud {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.pminu.d(<8 x i32> %a0, <8 x i32> %a1)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.pminu.d(<8 x i32>, <8 x i32>) nounwind readnone
+
+define <16 x i16> @stack_fold_pminuw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pminuw
+  ;CHECK:       vpminuw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.pminu.w(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.pminu.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <8 x i32> @stack_fold_pmovsxbd(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxbd
+  ;CHECK:       vpmovsxbd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.pmovsxbd(<16 x i8> %a0)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.pmovsxbd(<16 x i8>) nounwind readnone
+
+define <4 x i64> @stack_fold_pmovsxbq(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxbq
+  ;CHECK:       pmovsxbq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.avx2.pmovsxbq(<16 x i8> %a0)
+  ret <4 x i64> %2
+}
+declare <4 x i64> @llvm.x86.avx2.pmovsxbq(<16 x i8>) nounwind readnone
+
+define <16 x i16> @stack_fold_pmovsxbw(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxbw
+  ;CHECK:       vpmovsxbw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8> %a0)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8>) nounwind readnone
+
+define <4 x i64> @stack_fold_pmovsxdq(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxdq
+  ;CHECK:       vpmovsxdq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.avx2.pmovsxdq(<4 x i32> %a0)
+  ret <4 x i64> %2
+}
+declare <4 x i64> @llvm.x86.avx2.pmovsxdq(<4 x i32>) nounwind readnone
+
+define <8 x i32> @stack_fold_pmovsxwd(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxwd
+  ;CHECK:       vpmovsxwd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.pmovsxwd(<8 x i16> %a0)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.pmovsxwd(<8 x i16>) nounwind readnone
+
+define <4 x i64> @stack_fold_pmovsxwq(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxwq
+  ;CHECK:       vpmovsxwq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16> %a0)
+  ret <4 x i64> %2
+}
+declare <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16>) nounwind readnone
+
+define <8 x i32> @stack_fold_pmovzxbd(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxbd
+  ;CHECK:       vpmovzxbd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8> %a0)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8>) nounwind readnone
+
+define <4 x i64> @stack_fold_pmovzxbq(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxbq
+  ;CHECK:       vpmovzxbq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8> %a0)
+  ret <4 x i64> %2
+}
+declare <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8>) nounwind readnone
+
+define <16 x i16> @stack_fold_pmovzxbw(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxbw
+  ;CHECK:       vpmovzxbw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8> %a0)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8>) nounwind readnone
+
+define <4 x i64> @stack_fold_pmovzxdq(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxdq
+  ;CHECK:       vpmovzxdq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32> %a0)
+  ret <4 x i64> %2
+}
+declare <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32>) nounwind readnone
+
+define <8 x i32> @stack_fold_pmovzxwd(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxwd
+  ;CHECK:       vpmovzxwd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16> %a0)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16>) nounwind readnone
+
+define <4 x i64> @stack_fold_pmovzxwq(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxwq
+  ;CHECK:       vpmovzxwq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16> %a0)
+  ret <4 x i64> %2
+}
+declare <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16>) nounwind readnone
+
+define <4 x i64> @stack_fold_pmuldq(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pmuldq
+  ;CHECK:       vpmuldq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32> %a0, <8 x i32> %a1)
+  ret <4 x i64> %2
+}
+declare <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32>, <8 x i32>) nounwind readnone
+
+define <16 x i16> @stack_fold_pmulhrsw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmulhrsw
+  ;CHECK:       vpmulhrsw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.pmul.hr.sw(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.pmul.hr.sw(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <16 x i16> @stack_fold_pmulhuw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmulhuw
+  ;CHECK:       vpmulhuw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <16 x i16> @stack_fold_pmulhw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmulhw
+  ;CHECK:       vpmulhw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <8 x i32> @stack_fold_pmulld(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pmulld
+  ;CHECK:       vpmulld {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = mul <8 x i32> %a0, %a1
+  ret <8 x i32> %2
+}
+
+define <16 x i16> @stack_fold_pmullw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmullw
+  ;CHECK:       vpmullw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = mul <16 x i16> %a0, %a1
+  ret <16 x i16> %2
+}
+
+define <4 x i64> @stack_fold_pmuludq(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pmuludq
+  ;CHECK:       vpmuludq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32> %a0, <8 x i32> %a1)
+  ret <4 x i64> %2
+}
+declare <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32>, <8 x i32>) nounwind readnone
+
+define <32 x i8> @stack_fold_por(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_por
+  ;CHECK:       vpor {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = or <32 x i8> %a0, %a1
+  ; add forces execution domain
+  %3 = add <32 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <32 x i8> %3
+}
+
+define <4 x i64> @stack_fold_psadbw(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_psadbw
+  ;CHECK:       vpsadbw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> %a0, <32 x i8> %a1)
+  ret <4 x i64> %2
+}
+declare <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8>, <32 x i8>) nounwind readnone
+
+define <32 x i8> @stack_fold_pshufb(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pshufb
+  ;CHECK:       vpshufb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> %a1)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+define <8 x i32> @stack_fold_pshufd(<8 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pshufd
+  ;CHECK:       vpshufd $27, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+  ret <8 x i32> %2
+}
+
+; TODO stack_fold_pshufhw
+
+; TODO stack_fold_pshuflw
+
+define <32 x i8> @stack_fold_psignb(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_psignb
+  ;CHECK:       vpsignb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.psign.b(<32 x i8> %a0, <32 x i8> %a1)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.psign.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+define <8 x i32> @stack_fold_psignd(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psignd
+  ;CHECK:       vpsignd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.psign.d(<8 x i32> %a0, <8 x i32> %a1)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.psign.d(<8 x i32>, <8 x i32>) nounwind readnone
+
+define <16 x i16> @stack_fold_psignw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psignw
+  ;CHECK:       vpsignw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.psign.w(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.psign.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <8 x i32> @stack_fold_pslld(<8 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pslld
+  ;CHECK:       vpslld {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %a0, <4 x i32> %a1)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32>, <4 x i32>) nounwind readnone
+
+define <4 x i64> @stack_fold_psllq(<4 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_psllq
+  ;CHECK:       vpsllq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %a0, <2 x i64> %a1)
+  ret <4 x i64> %2
+}
+declare <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64>, <2 x i64>) nounwind readnone
+
+define <4 x i32> @stack_fold_psllvd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psllvd
+  ;CHECK:       vpsllvd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i32> @stack_fold_psllvd_ymm(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psllvd_ymm
+  ;CHECK:       vpsllvd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %a0, <8 x i32> %a1)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32>, <8 x i32>) nounwind readnone
+
+define <2 x i64> @stack_fold_psllvq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_psllvq
+  ;CHECK:       vpsllvq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <4 x i64> @stack_fold_psllvq_ymm(<4 x i64> %a0, <4 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_psllvq_ymm
+  ;CHECK:       vpsllvq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %a0, <4 x i64> %a1)
+  ret <4 x i64> %2
+}
+declare <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64>, <4 x i64>) nounwind readnone
+
+define <16 x i16> @stack_fold_psllw(<16 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psllw
+  ;CHECK:       vpsllw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %a0, <8 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i32> @stack_fold_psrad(<8 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psrad
+  ;CHECK:       vpsrad {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %a0, <4 x i32> %a1)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32>, <4 x i32>) nounwind readnone
+
+define <4 x i32> @stack_fold_psravd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psravd
+  ;CHECK:       vpsravd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i32> @stack_fold_psravd_ymm(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psravd_ymm
+  ;CHECK:       vpsravd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %a0, <8 x i32> %a1)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32>, <8 x i32>) nounwind readnone
+
+define <16 x i16> @stack_fold_psraw(<16 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psraw
+  ;CHECK:       vpsraw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %a0, <8 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i32> @stack_fold_psrld(<8 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psrld
+  ;CHECK:       vpsrld {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %a0, <4 x i32> %a1)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32>, <4 x i32>) nounwind readnone
+
+define <4 x i64> @stack_fold_psrlq(<4 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_psrlq
+  ;CHECK:       vpsrlq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %a0, <2 x i64> %a1)
+  ret <4 x i64> %2
+}
+declare <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64>, <2 x i64>) nounwind readnone
+
+define <4 x i32> @stack_fold_psrlvd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psrlvd
+  ;CHECK:       vpsrlvd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i32> @stack_fold_psrlvd_ymm(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psrlvd_ymm
+  ;CHECK:       vpsrlvd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %a0, <8 x i32> %a1)
+  ret <8 x i32> %2
+}
+declare <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32>, <8 x i32>) nounwind readnone
+
+define <2 x i64> @stack_fold_psrlvq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_psrlvq
+  ;CHECK:       vpsrlvq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <4 x i64> @stack_fold_psrlvq_ymm(<4 x i64> %a0, <4 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_psrlvq_ymm
+  ;CHECK:       vpsrlvq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %a0, <4 x i64> %a1)
+  ret <4 x i64> %2
+}
+declare <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64>, <4 x i64>) nounwind readnone
+
+define <16 x i16> @stack_fold_psrlw(<16 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psrlw
+  ;CHECK:       vpsrlw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %a0, <8 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16>, <8 x i16>) nounwind readnone
+
+define <32 x i8> @stack_fold_psubb(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_psubb
+  ;CHECK:       vpsubb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = sub <32 x i8> %a0, %a1
+  ret <32 x i8> %2
+}
+
+define <8 x i32> @stack_fold_psubd(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psubd
+  ;CHECK:       vpsubd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = sub <8 x i32> %a0, %a1
+  ret <8 x i32> %2
+}
+
+define <4 x i64> @stack_fold_psubq(<4 x i64> %a0, <4 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_psubq
+  ;CHECK:       vpsubq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = sub <4 x i64> %a0, %a1
+  ret <4 x i64> %2
+}
+
+define <32 x i8> @stack_fold_psubsb(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_psubsb
+  ;CHECK:       vpsubsb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.psubs.b(<32 x i8> %a0, <32 x i8> %a1)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.psubs.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+define <16 x i16> @stack_fold_psubsw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psubsw
+  ;CHECK:       vpsubsw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.psubs.w(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.psubs.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <32 x i8> @stack_fold_psubusb(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_psubusb
+  ;CHECK:       vpsubusb {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <32 x i8> @llvm.x86.avx2.psubus.b(<32 x i8> %a0, <32 x i8> %a1)
+  ret <32 x i8> %2
+}
+declare <32 x i8> @llvm.x86.avx2.psubus.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+define <16 x i16> @stack_fold_psubusw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psubusw
+  ;CHECK:       vpsubusw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i16> @llvm.x86.avx2.psubus.w(<16 x i16> %a0, <16 x i16> %a1)
+  ret <16 x i16> %2
+}
+declare <16 x i16> @llvm.x86.avx2.psubus.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+define <16 x i16> @stack_fold_psubw(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psubw
+  ;CHECK:       vpsubw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = sub <16 x i16> %a0, %a1
+  ret <16 x i16> %2
+}
+
+define <32 x i8> @stack_fold_punpckhbw(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_punpckhbw
+  ;CHECK:       vpunpckhbw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <32 x i8> %a0, <32 x i8> %a1, <32 x i32> <i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63>
+  ret <32 x i8> %2
+}
+
+define <8 x i32> @stack_fold_punpckhdq(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_punpckhdq
+  ;CHECK:       vpunpckhdq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i32> %a0, <8 x i32> %a1, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15>
+  ; add forces execution domain
+  %3 = add <8 x i32> %2, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+  ret <8 x i32> %3
+}
+
+define <4 x i64> @stack_fold_punpckhqdq(<4 x i64> %a0, <4 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_punpckhqdq
+  ;CHECK:       vpunpckhqdq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x i64> %a0, <4 x i64> %a1, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+  ; add forces execution domain
+  %3 = add <4 x i64> %2, <i64 1, i64 1, i64 1, i64 1>
+  ret <4 x i64> %3
+}
+
+define <16 x i16> @stack_fold_punpckhwd(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_punpckhwd
+  ;CHECK:       vpunpckhwd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <16 x i16> %a0, <16 x i16> %a1, <16 x i32> <i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
+  ret <16 x i16> %2
+}
+
+define <32 x i8> @stack_fold_punpcklbw(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_punpcklbw
+  ;CHECK:       vpunpcklbw {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <32 x i8> %a0, <32 x i8> %a1, <32 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55>
+  ret <32 x i8> %2
+}
+
+define <8 x i32> @stack_fold_punpckldq(<8 x i32> %a0, <8 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_punpckldq
+  ;CHECK:       vpunpckldq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i32> %a0, <8 x i32> %a1, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13>
+  ; add forces execution domain
+  %3 = add <8 x i32> %2, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+  ret <8 x i32> %3
+}
+
+define <4 x i64> @stack_fold_punpcklqdq(<4 x i64> %a0, <4 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_punpcklqdq
+  ;CHECK:       vpunpcklqdq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x i64> %a0, <4 x i64> %a1, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+  ; add forces execution domain
+  %3 = add <4 x i64> %2, <i64 1, i64 1, i64 1, i64 1>
+  ret <4 x i64> %3
+}
+
+define <16 x i16> @stack_fold_punpcklwd(<16 x i16> %a0, <16 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_punpcklwd
+  ;CHECK:       vpunpcklwd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <16 x i16> %a0, <16 x i16> %a1, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27>
+  ret <16 x i16> %2
+}
+
+define <32 x i8> @stack_fold_pxor(<32 x i8> %a0, <32 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pxor
+  ;CHECK:       vpxor {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = xor <32 x i8> %a0, %a1
+  ; add forces execution domain
+  %3 = add <32 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <32 x i8> %3
+}
diff --git a/test/CodeGen/X86/stack-folding-int-sse42.ll b/test/CodeGen/X86/stack-folding-int-sse42.ll
new file mode 100644
index 000000000000..e814ae6df501
--- /dev/null
+++ b/test/CodeGen/X86/stack-folding-int-sse42.ll
@@ -0,0 +1,1174 @@
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.2,+aes,+pclmul < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-unknown"
+
+; Stack reload folding tests.
+;
+; By including a nop call with sideeffects we can force a partial register spill of the
+; relevant registers and check that the reload is correctly folded into the instruction.
+
+define <2 x i64> @stack_fold_aesdec(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_aesdec
+  ;CHECK:       aesdec {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <2 x i64> @stack_fold_aesdeclast(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_aesdeclast
+  ;CHECK:       aesdeclast {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <2 x i64> @stack_fold_aesenc(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_aesenc
+  ;CHECK:       aesenc {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <2 x i64> @stack_fold_aesenclast(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_aesenclast
+  ;CHECK:       aesenclast {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <2 x i64> @stack_fold_aesimc(<2 x i64> %a0) {
+  ;CHECK-LABEL: stack_fold_aesimc
+  ;CHECK:       aesimc {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64>) nounwind readnone
+
+define <2 x i64> @stack_fold_aeskeygenassist(<2 x i64> %a0) {
+  ;CHECK-LABEL: stack_fold_aeskeygenassist
+  ;CHECK:       aeskeygenassist $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64> %a0, i8 7)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8) nounwind readnone
+
+;TODO stack_fold_crc32_32_8
+declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind
+
+;TODO stack_fold_crc32_32_16
+declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind
+
+define i32 @stack_fold_crc32_32_32(i32 %a0, i32 %a1) {
+  ;CHECK-LABEL: stack_fold_crc32_32_32
+  ;CHECK:       crc32l {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a0, i32 %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind
+
+;TODO stack_fold_crc32_64_8
+declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind
+
+define i64 @stack_fold_crc32_64_64(i64 %a0, i64 %a1) {
+  ;CHECK-LABEL: stack_fold_crc32_64_64
+  ;CHECK:       crc32q {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = call i64 @llvm.x86.sse42.crc32.64.64(i64 %a0, i64 %a1)
+  ret i64 %2
+}
+declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind
+
+define <4 x i32> @stack_fold_movd_load(i32 %a0) {
+  ;CHECK-LABEL: stack_fold_movd_load
+  ;CHECK:       movd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = insertelement <4 x i32> zeroinitializer, i32 %a0, i32 0
+  ; add forces execution domain
+  %3 = add <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %3
+}
+
+define i32 @stack_fold_movd_store(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_movd_store
+  ;CHECK:       movd {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 4-byte Folded Spill
+  ; add forces execution domain
+  %1 = add <4 x i32> %a0, <i32 1, i32 1, i32 1, i32 1>
+  %2 = extractelement <4 x i32> %1, i32 0
+  %3 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  ret i32 %2
+}
+
+define <2 x i64> @stack_fold_movq_load(<2 x i64> %a0) {
+  ;CHECK-LABEL: stack_fold_movq_load
+  ;CHECK:       movq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <2 x i64> %a0, <2 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>
+  ; add forces execution domain
+  %3 = add <2 x i64> %2, <i64 1, i64 1>
+  ret <2 x i64> %3
+}
+
+define i64 @stack_fold_movq_store(<2 x i64> %a0) {
+  ;CHECK-LABEL: stack_fold_movq_store
+  ;CHECK:       movq {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 8-byte Folded Spill
+  ; add forces execution domain
+  %1 = add <2 x i64> %a0, <i64 1, i64 1>
+  %2 = extractelement <2 x i64> %1, i32 0
+  %3 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  ret i64 %2
+}
+
+define <8 x i16> @stack_fold_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_mpsadbw
+  ;CHECK:       mpsadbw $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> %a0, <16 x i8> %a1, i8 7)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8>, <16 x i8>, i8) nounwind readnone
+
+define <16 x i8> @stack_fold_pabsb(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pabsb
+  ;CHECK:       pabsb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %a0)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_pabsd(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pabsd
+  ;CHECK:       pabsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_pabsw(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pabsw
+  ;CHECK:       pabsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %a0)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_packssdw(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_packssdw
+  ;CHECK:       packssdw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %a0, <4 x i32> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <16 x i8> @stack_fold_packsswb(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_packsswb
+  ;CHECK:       packsswb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_packusdw(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_packusdw
+  ;CHECK:       packusdw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <16 x i8> @stack_fold_packuswb(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_packuswb
+  ;CHECK:       packuswb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_paddb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_paddb
+  ;CHECK:       paddb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = add <16 x i8> %a0, %a1
+  ret <16 x i8> %2
+}
+
+define <4 x i32> @stack_fold_paddd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_paddd
+  ;CHECK:       paddd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = add <4 x i32> %a0, %a1
+  ret <4 x i32> %2
+}
+
+define <2 x i64> @stack_fold_paddq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_paddq
+  ;CHECK:       paddq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = add <2 x i64> %a0, %a1
+  ret <2 x i64> %2
+}
+
+define <16 x i8> @stack_fold_paddsb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_paddsb
+  ;CHECK:       paddsb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_paddsw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_paddsw
+  ;CHECK:       paddsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_paddusb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_paddusb
+  ;CHECK:       paddusb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_paddusw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_paddusw
+  ;CHECK:       paddusw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_paddw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_paddw
+  ;CHECK:       paddw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = add <8 x i16> %a0, %a1
+  ret <8 x i16> %2
+}
+
+define <16 x i8> @stack_fold_palignr(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_palignr
+  ;CHECK:       palignr $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <16 x i8> %a1, <16 x i8> %a0, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
+  ret <16 x i8> %2
+}
+
+define <16 x i8> @stack_fold_pand(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pand
+  ;CHECK:       pand {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = and <16 x i8> %a0, %a1
+  ; add forces execution domain
+  %3 = add <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %3
+}
+
+define <16 x i8> @stack_fold_pandn(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pandn
+  ;CHECK:       pandn {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = xor <16 x i8> %a0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %3 = and <16 x i8> %2, %a1
+  ; add forces execution domain
+  %4 = add <16 x i8> %3, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %4
+}
+
+define <16 x i8> @stack_fold_pavgb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pavgb
+  ;CHECK:       pavgb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_pavgw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pavgw
+  ;CHECK:       pavgw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_pblendvb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %c) {
+  ;CHECK-LABEL: stack_fold_pblendvb
+  ;CHECK:       pblendvb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %a1, <16 x i8> %c, <16 x i8> %a0)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_pblendw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pblendw
+  ;CHECK:       pblendw $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %a0, <8 x i16> %a1, i8 7)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i8) nounwind readnone
+
+define <2 x i64> @stack_fold_pclmulqdq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_pclmulqdq
+  ;CHECK:       pclmulqdq $0, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a0, <2 x i64> %a1, i8 0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.pclmulqdq(<2 x i64>, <2 x i64>, i8) nounwind readnone
+
+define <16 x i8> @stack_fold_pcmpeqb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpeqb
+  ;CHECK:       pcmpeqb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp eq <16 x i8> %a0, %a1
+  %3 = sext <16 x i1> %2 to <16 x i8>
+  ret <16 x i8> %3
+}
+
+define <4 x i32> @stack_fold_pcmpeqd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpeqd
+  ;CHECK:       pcmpeqd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp eq <4 x i32> %a0, %a1
+  %3 = sext <4 x i1> %2 to <4 x i32>
+  ret <4 x i32> %3
+}
+
+define <2 x i64> @stack_fold_pcmpeqq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpeqq
+  ;CHECK:       pcmpeqq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp eq <2 x i64> %a0, %a1
+  %3 = sext <2 x i1> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <8 x i16> @stack_fold_pcmpeqw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpeqw
+  ;CHECK:       pcmpeqw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp eq <8 x i16> %a0, %a1
+  %3 = sext <8 x i1> %2 to <8 x i16>
+  ret <8 x i16> %3
+}
+
+define i32 @stack_fold_pcmpestri(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpestri
+  ;CHECK:       pcmpestri $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{rax},~{flags}"()
+  %2 = call i32 @llvm.x86.sse42.pcmpestri128(<16 x i8> %a0, i32 7, <16 x i8> %a1, i32 7, i8 7)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse42.pcmpestri128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
+
+define <16 x i8> @stack_fold_pcmpestrm(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpestrm
+  ;CHECK:       pcmpestrm $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{rax},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8> %a0, i32 7, <16 x i8> %a1, i32 7, i8 7)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
+
+define <16 x i8> @stack_fold_pcmpgtb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpgtb
+  ;CHECK:       pcmpgtb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp sgt <16 x i8> %a0, %a1
+  %3 = sext <16 x i1> %2 to <16 x i8>
+  ret <16 x i8> %3
+}
+
+define <4 x i32> @stack_fold_pcmpgtd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpgtd
+  ;CHECK:       pcmpgtd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp sgt <4 x i32> %a0, %a1
+  %3 = sext <4 x i1> %2 to <4 x i32>
+  ret <4 x i32> %3
+}
+
+define <2 x i64> @stack_fold_pcmpgtq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpgtq
+  ;CHECK:       pcmpgtq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp sgt <2 x i64> %a0, %a1
+  %3 = sext <2 x i1> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <8 x i16> @stack_fold_pcmpgtw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpgtw
+  ;CHECK:       pcmpgtw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = icmp sgt <8 x i16> %a0, %a1
+  %3 = sext <8 x i1> %2 to <8 x i16>
+  ret <8 x i16> %3
+}
+
+define i32 @stack_fold_pcmpistri(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpistri
+  ;CHECK:       pcmpistri $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse42.pcmpistri128(<16 x i8> %a0, <16 x i8> %a1, i8 7)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse42.pcmpistri128(<16 x i8>, <16 x i8>, i8) nounwind readnone
+
+define <16 x i8> @stack_fold_pcmpistrm(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pcmpistrm
+  ;CHECK:       pcmpistrm $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8> %a0, <16 x i8> %a1, i8 7)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8>, <16 x i8>, i8) nounwind readnone
+
+; TODO stack_fold_pextrb
+
+define i32 @stack_fold_pextrd(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pextrd
+  ;CHECK:       pextrd $1, {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 4-byte Folded Spill
+  ;CHECK:       movl    {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Reload
+  %1 = extractelement <4 x i32> %a0, i32 1
+  %2 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  ret i32 %1
+}
+
+define i64 @stack_fold_pextrq(<2 x i64> %a0) {
+  ;CHECK-LABEL: stack_fold_pextrq
+  ;CHECK:       pextrq $1, {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 8-byte Folded Spill
+  ;CHECK:       movq    {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Reload
+  %1 = extractelement <2 x i64> %a0, i32 1
+  %2 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  ret i64 %1
+}
+
+; TODO stack_fold_pextrw
+
+define <4 x i32> @stack_fold_phaddd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_phaddd
+  ;CHECK:       phaddd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_phaddsw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_phaddsw
+  ;CHECK:       phaddsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_phaddw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_phaddw
+  ;CHECK:       phaddw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_phminposuw(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_phminposuw
+  ;CHECK:       phminposuw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16> %a0)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_phsubd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_phsubd
+  ;CHECK:       phsubd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_phsubsw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_phsubsw
+  ;CHECK:       phsubsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_phsubw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_phsubw
+  ;CHECK:       phsubw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_pinsrb(<16 x i8> %a0, i8 %a1) {
+  ;CHECK-LABEL: stack_fold_pinsrb
+  ;CHECK:       pinsrb $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = insertelement <16 x i8> %a0, i8 %a1, i32 1
+  ret <16 x i8> %2
+}
+
+define <4 x i32> @stack_fold_pinsrd(<4 x i32> %a0, i32 %a1) {
+  ;CHECK-LABEL: stack_fold_pinsrd
+  ;CHECK:       pinsrd $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = insertelement <4 x i32> %a0, i32 %a1, i32 1
+  ret <4 x i32> %2
+}
+
+define <2 x i64> @stack_fold_pinsrq(<2 x i64> %a0, i64 %a1) {
+  ;CHECK-LABEL: stack_fold_pinsrq
+  ;CHECK:       pinsrq $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = insertelement <2 x i64> %a0, i64 %a1, i32 1
+  ret <2 x i64> %2
+}
+
+define <8 x i16> @stack_fold_pinsrw(<8 x i16> %a0, i16 %a1) {
+  ;CHECK-LABEL: stack_fold_pinsrw
+  ;CHECK:       pinsrw $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = insertelement <8 x i16> %a0, i16 %a1, i32 1
+  ret <8 x i16> %2
+}
+
+define <8 x i16> @stack_fold_pmaddubsw(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaddubsw
+  ;CHECK:       pmaddubsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8> %a0, <16 x i8> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_pmaddwd(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaddwd
+  ;CHECK:       pmaddwd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a0, <8 x i16> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_pmaxsb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxsb
+  ;CHECK:       pmaxsb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_pmaxsd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxsd
+  ;CHECK:       pmaxsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_pmaxsw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxsw
+  ;CHECK:       pmaxsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_pmaxub(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxub
+  ;CHECK:       pmaxub {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_pmaxud(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxud
+  ;CHECK:       pmaxud {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_pmaxuw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmaxuw
+  ;CHECK:       pmaxuw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_pminsb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pminsb
+  ;CHECK:       pminsb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_pminsd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pminsd
+  ;CHECK:       pminsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_pminsw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pminsw
+  ;CHECK:       pminsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_pminub(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pminub
+  ;CHECK:       pminub {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_pminud(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pminud
+  ;CHECK:       pminud {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_pminuw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pminuw
+  ;CHECK:       pminuw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_pmovsxbd(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxbd
+  ;CHECK:       pmovsxbd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
+
+define <2 x i64> @stack_fold_pmovsxbq(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxbq
+  ;CHECK:       pmovsxbq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_pmovsxbw(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxbw
+  ;CHECK:       pmovsxbw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8> %a0)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8>) nounwind readnone
+
+define <2 x i64> @stack_fold_pmovsxdq(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxdq
+  ;CHECK:       pmovsxdq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32>) nounwind readnone
+
+define <4 x i32> @stack_fold_pmovsxwd(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxwd
+  ;CHECK:       pmovsxwd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
+
+define <2 x i64> @stack_fold_pmovsxwq(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovsxwq
+  ;CHECK:       pmovsxwq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_pmovzxbd(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxbd
+  ;CHECK:       pmovzxbd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <16 x i8> %a0, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 16, i32 17, i32 18, i32 1, i32 19, i32 20, i32 21, i32 2, i32 22, i32 23, i32 24, i32 3, i32 25, i32 26, i32 27>
+  %3 = bitcast <16 x i8> %2 to <4 x i32>
+  ret <4 x i32> %3
+}
+
+define <2 x i64> @stack_fold_pmovzxbq(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxbq
+  ;CHECK:       pmovzxbq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <16 x i8> %a0, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 1, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28>
+  %3 = bitcast <16 x i8> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <8 x i16> @stack_fold_pmovzxbw(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxbw
+  ;CHECK:       pmovzxbw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <16 x i8> %a0, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
+  %3 = bitcast <16 x i8> %2 to <8 x i16>
+  ret <8 x i16> %3
+}
+
+define <2 x i64> @stack_fold_pmovzxdq(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxdq
+  ;CHECK:       pmovzxdq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x i32> %a0, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+  %3 = bitcast <4 x i32> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <4 x i32> @stack_fold_pmovzxwd(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxwd
+  ;CHECK:       pmovzxwd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i16> %a0, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+  %3 = bitcast <8 x i16> %2 to <4 x i32>
+  ret <4 x i32> %3
+}
+
+define <2 x i64> @stack_fold_pmovzxwq(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pmovzxwq
+  ;CHECK:       pmovzxwq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i16> %a0, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 9, i32 10, i32 1, i32 11, i32 12, i32 13>
+  %3 = bitcast <8 x i16> %2 to <2 x i64>
+  ret <2 x i64> %3
+}
+
+define <2 x i64> @stack_fold_pmuldq(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pmuldq
+  ;CHECK:       pmuldq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> %a0, <4 x i32> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_pmulhrsw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmulhrsw
+  ;CHECK:       pmulhrsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_pmulhuw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmulhuw
+  ;CHECK:       pmulhuw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_pmulhw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmulhw
+  ;CHECK:       pmulhw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_pmulld(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pmulld
+  ;CHECK:       pmulld {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = mul <4 x i32> %a0, %a1
+  ret <4 x i32> %2
+}
+
+define <8 x i16> @stack_fold_pmullw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_pmullw
+  ;CHECK:       pmullw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = mul <8 x i16> %a0, %a1
+  ret <8 x i16> %2
+}
+
+define <2 x i64> @stack_fold_pmuludq(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pmuludq
+  ;CHECK:       pmuludq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %a0, <4 x i32> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <16 x i8> @stack_fold_por(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_por
+  ;CHECK:       por {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = or <16 x i8> %a0, %a1
+  ; add forces execution domain
+  %3 = add <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %3
+}
+
+define <2 x i64> @stack_fold_psadbw(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_psadbw
+  ;CHECK:       psadbw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %a0, <16 x i8> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <16 x i8> @stack_fold_pshufb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pshufb
+  ;CHECK:       pshufb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_pshufd(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_pshufd
+  ;CHECK:       pshufd $27, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  ret <4 x i32> %2
+}
+
+define <8 x i16> @stack_fold_pshufhw(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pshufhw
+  ;CHECK:       pshufhw $11, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 6, i32 4, i32 4>
+  ret <8 x i16> %2
+}
+
+define <8 x i16> @stack_fold_pshuflw(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_pshuflw
+  ;CHECK:       pshuflw $27, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>
+  ret <8 x i16> %2
+}
+
+define <16 x i8> @stack_fold_psignb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_psignb
+  ;CHECK:       psignb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_psignd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psignd
+  ;CHECK:       psignd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_psignw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psignw
+  ;CHECK:       psignw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_pslld(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_pslld
+  ;CHECK:       pslld {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <2 x i64> @stack_fold_psllq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_psllq
+  ;CHECK:       psllq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i16> @stack_fold_psllw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psllw
+  ;CHECK:       psllw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_psrad(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psrad
+  ;CHECK:       psrad {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_psraw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psraw
+  ;CHECK:       psraw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_psrld(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psrld
+  ;CHECK:       psrld {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <2 x i64> @stack_fold_psrlq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_psrlq
+  ;CHECK:       psrlq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i16> @stack_fold_psrlw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psrlw
+  ;CHECK:       psrlw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_psubb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_psubb
+  ;CHECK:       psubb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = sub <16 x i8> %a0, %a1
+  ret <16 x i8> %2
+}
+
+define <4 x i32> @stack_fold_psubd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_psubd
+  ;CHECK:       psubd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = sub <4 x i32> %a0, %a1
+  ret <4 x i32> %2
+}
+
+define <2 x i64> @stack_fold_psubq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_psubq
+  ;CHECK:       psubq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = sub <2 x i64> %a0, %a1
+  ret <2 x i64> %2
+}
+
+define <16 x i8> @stack_fold_psubsb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_psubsb
+  ;CHECK:       psubsb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_psubsw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psubsw
+  ;CHECK:       psubsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_psubusb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_psubusb
+  ;CHECK:       psubusb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_psubusw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psubusw
+  ;CHECK:       psubusw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_psubw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_psubw
+  ;CHECK:       psubw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = sub <8 x i16> %a0, %a1
+  ret <8 x i16> %2
+}
+
+define i32 @stack_fold_ptest(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_ptest
+  ;CHECK:       ptest {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %a0, <2 x i64> %a1)
+  ret i32 %2
+}
+declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <16 x i8> @stack_fold_punpckhbw(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_punpckhbw
+  ;CHECK:       punpckhbw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <16 x i8> %a0, <16 x i8> %a1, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
+  ret <16 x i8> %2
+}
+
+define <4 x i32> @stack_fold_punpckhdq(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_punpckhdq
+  ;CHECK:       punpckhdq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+  ; add forces execution domain
+  %3 = add <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %3
+}
+
+define <2 x i64> @stack_fold_punpckhqdq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_punpckhqdq
+  ;CHECK:       punpckhqdq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <2 x i64> %a0, <2 x i64> %a1, <2 x i32> <i32 1, i32 3>
+  ; add forces execution domain
+  %3 = add <2 x i64> %2, <i64 1, i64 1>
+  ret <2 x i64> %3
+}
+
+define <8 x i16> @stack_fold_punpckhwd(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_punpckhwd
+  ;CHECK:       punpckhwd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i16> %a0, <8 x i16> %a1, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+  ret <8 x i16> %2
+}
+
+define <16 x i8> @stack_fold_punpcklbw(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_punpcklbw
+  ;CHECK:       punpcklbw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <16 x i8> %a0, <16 x i8> %a1, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
+  ret <16 x i8> %2
+}
+
+define <4 x i32> @stack_fold_punpckldq(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_punpckldq
+  ;CHECK:       punpckldq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+  ; add forces execution domain
+  %3 = add <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %3
+}
+
+define <2 x i64> @stack_fold_punpcklqdq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_punpcklqdq
+  ;CHECK:       punpcklqdq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <2 x i64> %a0, <2 x i64> %a1, <2 x i32> <i32 0, i32 2>
+  ; add forces execution domain
+  %3 = add <2 x i64> %2, <i64 1, i64 1>
+  ret <2 x i64> %3
+}
+
+define <8 x i16> @stack_fold_punpcklwd(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_punpcklwd
+  ;CHECK:       punpcklwd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = shufflevector <8 x i16> %a0, <8 x i16> %a1, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+  ret <8 x i16> %2
+}
+
+define <16 x i8> @stack_fold_pxor(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_pxor
+  ;CHECK:       pxor {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = xor <16 x i8> %a0, %a1
+  ; add forces execution domain
+  %3 = add <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %3
+}
diff --git a/test/CodeGen/X86/stack-folding-mmx.ll b/test/CodeGen/X86/stack-folding-mmx.ll
new file mode 100644
index 000000000000..8a5d4e2770dc
--- /dev/null
+++ b/test/CodeGen/X86/stack-folding-mmx.ll
@@ -0,0 +1,566 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s
+
+define x86_mmx @stack_fold_cvtpd2pi(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtpd2pi
+  ;CHECK:       cvtpd2pi {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call x86_mmx @llvm.x86.sse.cvtpd2pi(<2 x double> %a0) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.sse.cvtpd2pi(<2 x double>) nounwind readnone
+
+define <2 x double> @stack_fold_cvtpi2pd(x86_mmx %a0) {
+  ;CHECK-LABEL: stack_fold_cvtpi2pd
+  ;CHECK:       cvtpi2pd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm1},~{mm1},~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call <2 x double> @llvm.x86.sse.cvtpi2pd(x86_mmx %a0) nounwind readnone
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.sse.cvtpi2pd(x86_mmx) nounwind readnone
+
+define <4 x float> @stack_fold_cvtpi2ps(<4 x float> %a0, x86_mmx %a1) {
+  ;CHECK-LABEL: stack_fold_cvtpi2ps
+  ;CHECK:       cvtpi2ps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm1},~{mm1},~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> %a0, x86_mmx %a1) nounwind readnone
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float>, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_cvtps2pi(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvtps2pi
+  ;CHECK:       cvtps2pi {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call x86_mmx @llvm.x86.sse.cvtps2pi(<4 x float> %a0) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.sse.cvtps2pi(<4 x float>) nounwind readnone
+
+define x86_mmx @stack_fold_cvttpd2pi(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttpd2pi
+  ;CHECK:       cvttpd2pi {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call x86_mmx @llvm.x86.sse.cvttpd2pi(<2 x double> %a0) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.sse.cvttpd2pi(<2 x double>) nounwind readnone
+
+define x86_mmx @stack_fold_cvttps2pi(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_cvttps2pi
+  ;CHECK:       cvttps2pi {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call x86_mmx @llvm.x86.sse.cvttps2pi(<4 x float> %a0) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.sse.cvttps2pi(<4 x float>) nounwind readnone
+
+; TODO stack_fold_movd_load
+; TODO stack_fold_movd_store
+; TODO stack_fold_movq_load
+; TODO stack_fold_movq_store
+
+define x86_mmx @stack_fold_packssdw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_packssdw
+  ;CHECK:       packssdw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.packssdw(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.packssdw(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_packsswb(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_packsswb
+  ;CHECK:       packsswb {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.packsswb(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.packsswb(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_packuswb(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_packuswb
+  ;CHECK:       packuswb {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.packuswb(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.packuswb(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_paddb(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_paddb
+  ;CHECK:       paddb {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_paddd(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_paddd
+  ;CHECK:       paddd {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_paddq(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_paddq
+  ;CHECK:       paddq {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_paddsb(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_paddsb
+  ;CHECK:       paddsb {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.padds.b(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.padds.b(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_paddsw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_paddsw
+  ;CHECK:       paddsw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.padds.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.padds.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_paddusb(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_paddusb
+  ;CHECK:       paddusb {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_paddusw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_paddusw
+  ;CHECK:       paddusw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_paddw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_paddw
+  ;CHECK:       paddw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pand(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pand
+  ;CHECK:       pand {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pand(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pand(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pandn(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pandn
+  ;CHECK:       pandn {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pandn(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pandn(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pavgb(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pavgb
+  ;CHECK:       pavgb {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pavg.b(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pavg.b(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pavgw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pavgw
+  ;CHECK:       pavgw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pavg.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pavg.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pcmpeqb(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pcmpeqb
+  ;CHECK:       pcmpeqb {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pcmpeq.b(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pcmpeq.b(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pcmpeqd(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pcmpeqd
+  ;CHECK:       pcmpeqd {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pcmpeq.d(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pcmpeq.d(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pcmpeqw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pcmpeqw
+  ;CHECK:       pcmpeqw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pcmpeq.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pcmpeq.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pcmpgtb(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pcmpgtb
+  ;CHECK:       pcmpgtb {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pcmpgt.b(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pcmpgt.b(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pcmpgtd(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pcmpgtd
+  ;CHECK:       pcmpgtd {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pcmpgt.d(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pcmpgt.d(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pcmpgtw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pcmpgtw
+  ;CHECK:       pcmpgtw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pcmpgt.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pcmpgt.w(x86_mmx, x86_mmx) nounwind readnone
+
+; TODO stack_fold_pinsrw
+
+define x86_mmx @stack_fold_pmaddwd(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pmaddwd
+  ;CHECK:       pmaddwd {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pmadd.wd(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pmadd.wd(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pmaxsw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pmaxsw
+  ;CHECK:       pmaxsw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pmaxs.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pmaxs.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pmaxub(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pmaxub
+  ;CHECK:       pmaxub {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pmaxu.b(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pmaxu.b(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pminsw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pminsw
+  ;CHECK:       pminsw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pmins.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pmins.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pminub(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pminub
+  ;CHECK:       pminub {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pminu.b(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pminu.b(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pmulhuw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pmulhuw
+  ;CHECK:       pmulhuw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pmulhu.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pmulhu.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pmulhw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pmulhw
+  ;CHECK:       pmulhw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pmulh.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pmulh.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pmullw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pmullw
+  ;CHECK:       pmullw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pmuludq(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pmuludq
+  ;CHECK:       pmuludq {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pmulu.dq(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pmulu.dq(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_por(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_por
+  ;CHECK:       por {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.por(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.por(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psadbw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psadbw
+  ;CHECK:       psadbw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psad.bw(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psad.bw(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pshufw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pshufw
+  ;CHECK:       pshufw $1, {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm1},~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %a, i8 1) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8) nounwind readnone
+
+define x86_mmx @stack_fold_pslld(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pslld
+  ;CHECK:       pslld {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psll.d(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psll.d(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psllq(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psllq
+  ;CHECK:       psllq {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psll.q(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psll.q(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psllw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psllw
+  ;CHECK:       psllw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psll.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psll.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psrad(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psrad
+  ;CHECK:       psrad {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psra.d(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psra.d(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psraw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psraw
+  ;CHECK:       psraw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psra.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psra.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psrld(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psrld
+  ;CHECK:       psrld {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psrlq(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psrlq
+  ;CHECK:       psrlq {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psrlw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psrlw
+  ;CHECK:       psrlw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psubb(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psubb
+  ;CHECK:       psubb {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psub.b(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psub.b(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psubd(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psubd
+  ;CHECK:       psubd {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psub.d(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psub.d(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psubq(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psubq
+  ;CHECK:       psubq {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psub.q(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psub.q(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psubsb(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psubsb
+  ;CHECK:       psubsb {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psubs.b(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psubs.b(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psubsw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psubsw
+  ;CHECK:       psubsw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psubs.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psubs.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psubusb(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psubusb
+  ;CHECK:       psubusb {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psubus.b(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psubus.b(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psubusw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psubusw
+  ;CHECK:       psubusw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psubus.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psubus.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_psubw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_psubw
+  ;CHECK:       psubw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.psub.w(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.psub.w(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_punpckhbw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_punpckhbw
+  ;CHECK:       punpckhbw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.punpckhbw(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.punpckhbw(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_punpckhdq(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_punpckhdq
+  ;CHECK:       punpckhdq {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.punpckhdq(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.punpckhdq(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_punpckhwd(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_punpckhwd
+  ;CHECK:       punpckhwd {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.punpckhwd(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.punpckhwd(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_punpcklbw(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_punpcklbw
+  ;CHECK:       punpcklbw {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.punpcklbw(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.punpcklbw(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_punpckldq(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_punpckldq
+  ;CHECK:       punpckldq {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.punpckldq(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.punpckldq(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_punpcklwd(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_punpcklwd
+  ;CHECK:       punpcklwd {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.punpcklwd(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.punpcklwd(x86_mmx, x86_mmx) nounwind readnone
+
+define x86_mmx @stack_fold_pxor(x86_mmx %a, x86_mmx %b) {
+  ;CHECK-LABEL: stack_fold_pxor
+  ;CHECK:       pxor {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
+  %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
+  %2 = call x86_mmx @llvm.x86.mmx.pxor(x86_mmx %a, x86_mmx %b) nounwind readnone
+  ret x86_mmx %2
+}
+declare x86_mmx @llvm.x86.mmx.pxor(x86_mmx, x86_mmx) nounwind readnone
diff --git a/test/CodeGen/X86/stack-folding-xop.ll b/test/CodeGen/X86/stack-folding-xop.ll
new file mode 100644
index 000000000000..44a0d1dc6582
--- /dev/null
+++ b/test/CodeGen/X86/stack-folding-xop.ll
@@ -0,0 +1,718 @@
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx,+xop < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-unknown"
+
+; Stack reload folding tests.
+;
+; By including a nop call with sideeffects we can force a partial register spill of the
+; relevant registers and check that the reload is correctly folded into the instruction.
+
+define <2 x double> @stack_fold_vfrczpd(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_vfrczpd
+  ;CHECK:       vfrczpd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.xop.vfrcz.pd(<2 x double> %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.xop.vfrcz.pd(<2 x double>) nounwind readnone
+
+define <4 x double> @stack_fold_vfrczpd_ymm(<4 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_vfrczpd_ymm
+  ;CHECK:       vfrczpd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.xop.vfrcz.pd.256(<4 x double> %a0)
+  ret <4 x double> %2
+}
+declare <4 x double> @llvm.x86.xop.vfrcz.pd.256(<4 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_vfrczps(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_vfrczps
+  ;CHECK:       vfrczps {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.xop.vfrcz.ps(<4 x float> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.xop.vfrcz.ps(<4 x float>) nounwind readnone
+
+define <8 x float> @stack_fold_vfrczps_ymm(<8 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_vfrczps_ymm
+  ;CHECK:       vfrczps {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.xop.vfrcz.ps.256(<8 x float> %a0)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.xop.vfrcz.ps.256(<8 x float>) nounwind readnone
+
+define <2 x double> @stack_fold_vfrczsd(<2 x double> %a0) {
+  ;CHECK-LABEL: stack_fold_vfrczsd
+  ;CHECK:       vfrczsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %a0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double>) nounwind readnone
+
+define <4 x float> @stack_fold_vfrczss(<4 x float> %a0) {
+  ;CHECK-LABEL: stack_fold_vfrczss
+  ;CHECK:       vfrczss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %a0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float>) nounwind readnone
+
+define <2 x i64> @stack_fold_vpcmov_rm(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) {
+  ;CHECK-LABEL: stack_fold_vpcmov_rm
+  ;CHECK:       vpcmov {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2)
+  ret <2 x i64> %2
+}
+define <2 x i64> @stack_fold_vpcmov_mr(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) {
+  ;CHECK-LABEL: stack_fold_vpcmov_mr
+  ;CHECK:       vpcmov {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64> %a0, <2 x i64> %a2, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
+
+define <4 x i64> @stack_fold_vpcmov_rm_ymm(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) {
+  ;CHECK-LABEL: stack_fold_vpcmov_rm_ymm
+  ;CHECK:       vpcmov {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2)
+  ret <4 x i64> %2
+}
+define <4 x i64> @stack_fold_vpcmov_mr_ymm(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) {
+  ;CHECK-LABEL: stack_fold_vpcmov_mr_ymm
+  ;CHECK:       vpcmov {{%ymm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a2, <4 x i64> %a1)
+  ret <4 x i64> %2
+}
+declare <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64>, <4 x i64>, <4 x i64>) nounwind readnone
+
+define <16 x i8> @stack_fold_vpcomb(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_vpcomb
+  ;CHECK:       vpcomltb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.xop.vpcomb(<16 x i8> %a0, <16 x i8> %a1, i8 0)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.xop.vpcomb(<16 x i8>, <16 x i8>, i8) nounwind readnone
+
+define <4 x i32> @stack_fold_vpcomd(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_vpcomd
+  ;CHECK:       vpcomltd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vpcomd(<4 x i32> %a0, <4 x i32> %a1, i8 0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpcomd(<4 x i32>, <4 x i32>, i8) nounwind readnone
+
+define <2 x i64> @stack_fold_vpcomq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_vpcomq
+  ;CHECK:       vpcomltq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vpcomq(<2 x i64> %a0, <2 x i64> %a1, i8 0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vpcomq(<2 x i64>, <2 x i64>, i8) nounwind readnone
+
+define <16 x i8> @stack_fold_vpcomub(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_vpcomub
+  ;CHECK:       vpcomltub {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.xop.vpcomub(<16 x i8> %a0, <16 x i8> %a1, i8 0)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.xop.vpcomub(<16 x i8>, <16 x i8>, i8) nounwind readnone
+
+define <4 x i32> @stack_fold_vpcomud(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_vpcomud
+  ;CHECK:       vpcomltud {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vpcomud(<4 x i32> %a0, <4 x i32> %a1, i8 0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpcomud(<4 x i32>, <4 x i32>, i8) nounwind readnone
+
+define <2 x i64> @stack_fold_vpcomuq(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_vpcomuq
+  ;CHECK:       vpcomltuq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vpcomuq(<2 x i64> %a0, <2 x i64> %a1, i8 0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vpcomuq(<2 x i64>, <2 x i64>, i8) nounwind readnone
+
+define <8 x i16> @stack_fold_vpcomuw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_vpcomuw
+  ;CHECK:       vpcomltuw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.xop.vpcomuw(<8 x i16> %a0, <8 x i16> %a1, i8 0)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.xop.vpcomuw(<8 x i16>, <8 x i16>, i8) nounwind readnone
+
+define <8 x i16> @stack_fold_vpcomw(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_vpcomw
+  ;CHECK:       vpcomltw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.xop.vpcomw(<8 x i16> %a0, <8 x i16> %a1, i8 0)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.xop.vpcomw(<8 x i16>, <8 x i16>, i8) nounwind readnone
+
+define <2 x double> @stack_fold_vpermil2pd_rm(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) {
+  ;CHECK-LABEL: stack_fold_vpermil2pd_rm
+  ;CHECK:       vpermil2pd $0, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 0)
+  ret <2 x double> %2
+}
+define <2 x double> @stack_fold_vpermil2pd_mr(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) {
+  ;CHECK-LABEL: stack_fold_vpermil2pd_mr
+  ;CHECK:       vpermil2pd $0, {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a2, <2 x double> %a1, i8 0)
+  ret <2 x double> %2
+}
+declare <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double>, <2 x double>, <2 x double>, i8) nounwind readnone
+
+define <4 x double> @stack_fold_vpermil2pd_rm_ymm(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) {
+  ;CHECK-LABEL: stack_fold_vpermil2pd_rm
+  ;CHECK:       vpermil2pd $0, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 0)
+  ret <4 x double> %2
+}
+define <4 x double> @stack_fold_vpermil2pd_mr_ymm(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) {
+  ;CHECK-LABEL: stack_fold_vpermil2pd_mr
+  ;CHECK:       vpermil2pd $0, {{%ymm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a2, <4 x double> %a1, i8 0)
+  ret <4 x double> %2
+}
+declare <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double>, <4 x double>, <4 x double>, i8) nounwind readnone
+
+define <4 x float> @stack_fold_vpermil2ps_rm(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
+  ;CHECK-LABEL: stack_fold_vpermil2ps_rm
+  ;CHECK:       vpermil2ps $0, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 0)
+  ret <4 x float> %2
+}
+define <4 x float> @stack_fold_vpermil2ps_mr(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
+  ;CHECK-LABEL: stack_fold_vpermil2ps_mr
+  ;CHECK:       vpermil2ps $0, {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float> %a0, <4 x float> %a2, <4 x float> %a1, i8 0)
+  ret <4 x float> %2
+}
+declare <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone
+
+define <8 x float> @stack_fold_vpermil2ps_rm_ymm(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) {
+  ;CHECK-LABEL: stack_fold_vpermil2ps_rm
+  ;CHECK:       vpermil2ps $0, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 0)
+  ret <8 x float> %2
+}
+define <8 x float> @stack_fold_vpermil2ps_mr_ymm(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) {
+  ;CHECK-LABEL: stack_fold_vpermil2ps_mr
+  ;CHECK:       vpermil2ps $0, {{%ymm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float> %a0, <8 x float> %a2, <8 x float> %a1, i8 0)
+  ret <8 x float> %2
+}
+declare <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float>, <8 x float>, <8 x float>, i8) nounwind readnone
+
+define <4 x i32> @stack_fold_vphaddbd(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_vphaddbd
+  ;CHECK:       vphaddbd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vphaddbd(<16 x i8> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vphaddbd(<16 x i8>) nounwind readnone
+
+define <2 x i64> @stack_fold_vphaddbq(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_vphaddbq
+  ;CHECK:       vphaddbq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vphaddbq(<16 x i8> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vphaddbq(<16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_vphaddbw(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_vphaddbw
+  ;CHECK:       vphaddbw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.xop.vphaddbw(<16 x i8> %a0)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.xop.vphaddbw(<16 x i8>) nounwind readnone
+
+define <2 x i64> @stack_fold_vphadddq(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_vphadddq
+  ;CHECK:       vphadddq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vphadddq(<4 x i32> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vphadddq(<4 x i32>) nounwind readnone
+
+define <4 x i32> @stack_fold_vphaddubd(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_vphaddubd
+  ;CHECK:       vphaddubd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vphaddubd(<16 x i8> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vphaddubd(<16 x i8>) nounwind readnone
+
+define <2 x i64> @stack_fold_vphaddubq(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_vphaddubq
+  ;CHECK:       vphaddubq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vphaddubq(<16 x i8> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vphaddubq(<16 x i8>) nounwind readnone
+
+define <8 x i16> @stack_fold_vphaddubw(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_vphaddubw
+  ;CHECK:       vphaddubw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.xop.vphaddubw(<16 x i8> %a0)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.xop.vphaddubw(<16 x i8>) nounwind readnone
+
+define <2 x i64> @stack_fold_vphaddudq(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_vphaddudq
+  ;CHECK:       vphaddudq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vphaddudq(<4 x i32> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vphaddudq(<4 x i32>) nounwind readnone
+
+define <4 x i32> @stack_fold_vphadduwd(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_vphadduwd
+  ;CHECK:       vphadduwd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vphadduwd(<8 x i16> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vphadduwd(<8 x i16>) nounwind readnone
+
+define <2 x i64> @stack_fold_vphadduwq(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_vphadduwq
+  ;CHECK:       vphadduwq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vphadduwq(<8 x i16> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vphadduwq(<8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_vphaddwd(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_vphaddwd
+  ;CHECK:       vphaddwd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vphaddwd(<8 x i16> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vphaddwd(<8 x i16>) nounwind readnone
+
+define <2 x i64> @stack_fold_vphaddwq(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_vphaddwq
+  ;CHECK:       vphaddwq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vphaddwq(<8 x i16> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vphaddwq(<8 x i16>) nounwind readnone
+
+define <8 x i16> @stack_fold_vphsubbw(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_vphsubbw
+  ;CHECK:       vphsubbw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.xop.vphsubbw(<16 x i8> %a0)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.xop.vphsubbw(<16 x i8>) nounwind readnone
+
+define <2 x i64> @stack_fold_vphsubdq(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_vphsubdq
+  ;CHECK:       vphsubdq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vphsubdq(<4 x i32> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vphsubdq(<4 x i32>) nounwind readnone
+
+define <4 x i32> @stack_fold_vphsubwd(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_vphsubwd
+  ;CHECK:       vphsubwd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vphsubwd(<8 x i16> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vphsubwd(<8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_vpmacsdd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) {
+  ;CHECK-LABEL: stack_fold_vpmacsdd
+  ;CHECK:       vpmacsdd {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vpmacsdd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpmacsdd(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
+
+define <2 x i64> @stack_fold_vpmacsdqh(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) {
+  ;CHECK-LABEL: stack_fold_vpmacsdqh
+  ;CHECK:       vpmacsdqh {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vpmacsdqh(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vpmacsdqh(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
+
+define <2 x i64> @stack_fold_vpmacsdql(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) {
+  ;CHECK-LABEL: stack_fold_vpmacsdql
+  ;CHECK:       vpmacsdql {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vpmacsdql(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vpmacsdql(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
+
+define <4 x i32> @stack_fold_vpmacssdd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) {
+  ;CHECK-LABEL: stack_fold_vpmacssdd
+  ;CHECK:       vpmacssdd {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vpmacssdd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpmacssdd(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
+
+define <2 x i64> @stack_fold_vpmacssdqh(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) {
+  ;CHECK-LABEL: stack_fold_vpmacssdqh
+  ;CHECK:       vpmacssdqh {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vpmacssdqh(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vpmacssdqh(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
+
+define <2 x i64> @stack_fold_vpmacssdql(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) {
+  ;CHECK-LABEL: stack_fold_vpmacssdql
+  ;CHECK:       vpmacssdql {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vpmacssdql(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vpmacssdql(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
+
+define <4 x i32> @stack_fold_vpmacsswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) {
+  ;CHECK-LABEL: stack_fold_vpmacsswd
+  ;CHECK:       vpmacsswd {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vpmacsswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpmacsswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_vpmacssww(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2) {
+  ;CHECK-LABEL: stack_fold_vpmacssww
+  ;CHECK:       vpmacssww {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.xop.vpmacssww(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.xop.vpmacssww(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_vpmacswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) {
+  ;CHECK-LABEL: stack_fold_vpmacswd
+  ;CHECK:       vpmacswd {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vpmacswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpmacswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @stack_fold_vpmacsww(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2) {
+  ;CHECK-LABEL: stack_fold_vpmacsww
+  ;CHECK:       vpmacsww {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.xop.vpmacsww(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.xop.vpmacsww(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
+
+define <4 x i32> @stack_fold_vpmadcsswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) {
+  ;CHECK-LABEL: stack_fold_vpmadcsswd
+  ;CHECK:       vpmadcsswd {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vpmadcsswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpmadcsswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
+
+define <4 x i32> @stack_fold_vpmadcswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) {
+  ;CHECK-LABEL: stack_fold_vpmadcswd
+  ;CHECK:       vpmadcswd {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vpmadcswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpmadcswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
+
+define <16 x i8> @stack_fold_vpperm_rm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) {
+  ;CHECK-LABEL: stack_fold_vpperm_rm
+  ;CHECK:       vpperm {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2)
+  ret <16 x i8> %2
+}
+define <16 x i8> @stack_fold_vpperm_mr(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) {
+  ;CHECK-LABEL: stack_fold_vpperm_mr
+  ;CHECK:       vpperm {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a2, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.xop.vpperm(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
+
+define <16 x i8> @stack_fold_vprotb(<16 x i8> %a0) {
+  ;CHECK-LABEL: stack_fold_vprotb
+  ;CHECK:       vprotb $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.xop.vprotbi(<16 x i8> %a0, i8 7)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.xop.vprotbi(<16 x i8>, i8) nounwind readnone
+
+define <16 x i8> @stack_fold_vprotb_rm(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_vprotb_rm
+  ;CHECK:       vprotb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.xop.vprotb(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+define <16 x i8> @stack_fold_vprotb_mr(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_vprotb_mr
+  ;CHECK:       vprotb {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.xop.vprotb(<16 x i8> %a1, <16 x i8> %a0)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.xop.vprotb(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_vprotd(<4 x i32> %a0) {
+  ;CHECK-LABEL: stack_fold_vprotd
+  ;CHECK:       vprotd $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vprotdi(<4 x i32> %a0, i8 7)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vprotdi(<4 x i32>, i8) nounwind readnone
+
+define <4 x i32> @stack_fold_vprotd_rm(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_vprotd_rm
+  ;CHECK:       vprotd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vprotd(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+define <4 x i32> @stack_fold_vprotd_mr(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_vprotd_mr
+  ;CHECK:       vprotd {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vprotd(<4 x i32> %a1, <4 x i32> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vprotd(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <2 x i64> @stack_fold_vprotq(<2 x i64> %a0) {
+  ;CHECK-LABEL: stack_fold_vprotq
+  ;CHECK:       vprotq $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vprotqi(<2 x i64> %a0, i8 7)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vprotqi(<2 x i64>, i8) nounwind readnone
+
+define <2 x i64> @stack_fold_vprotq_rm(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_vprotq_rm
+  ;CHECK:       vprotq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vprotq(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+define <2 x i64> @stack_fold_vprotq_mr(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_vprotq_mr
+  ;CHECK:       vprotq {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vprotq(<2 x i64> %a1, <2 x i64> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vprotq(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i16> @stack_fold_vprotw(<8 x i16> %a0) {
+  ;CHECK-LABEL: stack_fold_vprotw
+  ;CHECK:       vprotw $7, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.xop.vprotwi(<8 x i16> %a0, i8 7)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.xop.vprotwi(<8 x i16>, i8) nounwind readnone
+
+define <8 x i16> @stack_fold_vprotw_rm(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_vprotw_rm
+  ;CHECK:       vprotw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.xop.vprotw(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+define <8 x i16> @stack_fold_vprotw_mr(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_vprotw_mr
+  ;CHECK:       vprotw {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.xop.vprotw(<8 x i16> %a1, <8 x i16> %a0)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.xop.vprotw(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_vpshab_rm(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshab_rm
+  ;CHECK:       vpshab {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.xop.vpshab(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+define <16 x i8> @stack_fold_vpshab_mr(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshab_mr
+  ;CHECK:       vpshab {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.xop.vpshab(<16 x i8> %a1, <16 x i8> %a0)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.xop.vpshab(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_vpshad_rm(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshad_rm
+  ;CHECK:       vpshad {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vpshad(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+define <4 x i32> @stack_fold_vpshad_mr(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshad_mr
+  ;CHECK:       vpshad {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vpshad(<4 x i32> %a1, <4 x i32> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpshad(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <2 x i64> @stack_fold_vpshaq_rm(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshaq_rm
+  ;CHECK:       vpshaq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vpshaq(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+define <2 x i64> @stack_fold_vpshaq_mr(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshaq_mr
+  ;CHECK:       vpshaq {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vpshaq(<2 x i64> %a1, <2 x i64> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vpshaq(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i16> @stack_fold_vpshaw_rm(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshaw_rm
+  ;CHECK:       vpshaw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.xop.vpshaw(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+define <8 x i16> @stack_fold_vpshaw_mr(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshaw_mr
+  ;CHECK:       vpshaw {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.xop.vpshaw(<8 x i16> %a1, <8 x i16> %a0)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.xop.vpshaw(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <16 x i8> @stack_fold_vpshlb_rm(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshlb_rm
+  ;CHECK:       vpshlb {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.xop.vpshlb(<16 x i8> %a0, <16 x i8> %a1)
+  ret <16 x i8> %2
+}
+define <16 x i8> @stack_fold_vpshlb_mr(<16 x i8> %a0, <16 x i8> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshlb_mr
+  ;CHECK:       vpshlb {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <16 x i8> @llvm.x86.xop.vpshlb(<16 x i8> %a1, <16 x i8> %a0)
+  ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.x86.xop.vpshlb(<16 x i8>, <16 x i8>) nounwind readnone
+
+define <4 x i32> @stack_fold_vpshld_rm(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshld_rm
+  ;CHECK:       vpshld {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vpshld(<4 x i32> %a0, <4 x i32> %a1)
+  ret <4 x i32> %2
+}
+define <4 x i32> @stack_fold_vpshld_mr(<4 x i32> %a0, <4 x i32> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshld_mr
+  ;CHECK:       vpshld {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <4 x i32> @llvm.x86.xop.vpshld(<4 x i32> %a1, <4 x i32> %a0)
+  ret <4 x i32> %2
+}
+declare <4 x i32> @llvm.x86.xop.vpshld(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <2 x i64> @stack_fold_vpshlq_rm(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshlq_rm
+  ;CHECK:       vpshlq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vpshlq(<2 x i64> %a0, <2 x i64> %a1)
+  ret <2 x i64> %2
+}
+define <2 x i64> @stack_fold_vpshlq_mr(<2 x i64> %a0, <2 x i64> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshlq_mr
+  ;CHECK:       vpshlq {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <2 x i64> @llvm.x86.xop.vpshlq(<2 x i64> %a1, <2 x i64> %a0)
+  ret <2 x i64> %2
+}
+declare <2 x i64> @llvm.x86.xop.vpshlq(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i16> @stack_fold_vpshlw_rm(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshlw_rm
+  ;CHECK:       vpshlw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.xop.vpshlw(<8 x i16> %a0, <8 x i16> %a1)
+  ret <8 x i16> %2
+}
+define <8 x i16> @stack_fold_vpshlw_mr(<8 x i16> %a0, <8 x i16> %a1) {
+  ;CHECK-LABEL: stack_fold_vpshlw_mr
+  ;CHECK:       vpshlw {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
+  %2 = call <8 x i16> @llvm.x86.xop.vpshlw(<8 x i16> %a1, <8 x i16> %a0)
+  ret <8 x i16> %2
+}
+declare <8 x i16> @llvm.x86.xop.vpshlw(<8 x i16>, <8 x i16>) nounwind readnone
diff --git a/test/CodeGen/X86/stack-protector-dbginfo.ll b/test/CodeGen/X86/stack-protector-dbginfo.ll
index a84b77eac5f6..3aba19464b9d 100644
--- a/test/CodeGen/X86/stack-protector-dbginfo.ll
+++ b/test/CodeGen/X86/stack-protector-dbginfo.ll
@@ -10,9 +10,9 @@
 ; Function Attrs: nounwind sspreq
 define i32 @_Z18read_response_sizev() #0 {
 entry:
-  tail call void @llvm.dbg.value(metadata !22, i64 0, metadata !23, metadata !{!"0x102"}), !dbg !39
-  %0 = load i64* getelementptr inbounds ({ i64, [56 x i8] }* @a, i32 0, i32 0), align 8, !dbg !40
-  tail call void @llvm.dbg.value(metadata i32 undef, i64 0, metadata !64, metadata !{!"0x102"}), !dbg !71
+  tail call void @llvm.dbg.value(metadata !22, i64 0, metadata !23, metadata !DIExpression()), !dbg !39
+  %0 = load i64, i64* getelementptr inbounds ({ i64, [56 x i8] }, { i64, [56 x i8] }* @a, i32 0, i32 0), align 8, !dbg !40
+  tail call void @llvm.dbg.value(metadata i32 undef, i64 0, metadata !64, metadata !DIExpression()), !dbg !71
   %1 = trunc i64 %0 to i32
   ret i32 %1
 }
@@ -25,73 +25,72 @@ attributes #0 = { sspreq }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!21, !72}
 
-!0 = !{!"0x11\004\00clang version 3.4 \001\00\000\00\001", !1, !2, !5, !8, !20, !5} ; [ DW_TAG_compile_unit ] [/Users/matt/ryan_bug/<unknown>] [DW_LANG_C_plus_plus]
-!1 = !{!"<unknown>", !"/Users/matt/ryan_bug"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !5, subprograms: !8, globals: !20, imports: !5)
+!1 = !DIFile(filename: "<unknown>", directory: "/Users/matt/ryan_bug")
 !2 = !{!3}
-!3 = !{!"0x4\00\0020\0032\0032\000\000\000", !1, !4, null, !6, null, null, null} ; [ DW_TAG_enumeration_type ] [line 20, size 32, align 32, offset 0] [def] [from ]
-!4 = !{!"0x13\00C\0019\008\008\000\000\000", !1, null, null, !5, null, null, null} ; [ DW_TAG_structure_type ] [C] [line 19, size 8, align 8, offset 0] [def] [from ]
+!3 = !DICompositeType(tag: DW_TAG_enumeration_type, line: 20, size: 32, align: 32, file: !1, scope: !4, elements: !6)
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "C", line: 19, size: 8, align: 8, file: !1, elements: !5)
 !5 = !{}
 !6 = !{!7}
-!7 = !{!"0x28\00max_frame_size\000"} ; [ DW_TAG_enumerator ] [max_frame_size :: 0]
+!7 = !DIEnumerator(name: "max_frame_size", value: 0) ; [ DW_TAG_enumerator ] [max_frame_size :: 0]
 !8 = !{!9, !24, !41, !65}
-!9 = !{!"0x2e\00read_response_size\00read_response_size\00_Z18read_response_sizev\0027\000\001\000\006\00256\001\0027", !1, !10, !11, null, i32 ()* @_Z18read_response_sizev, null, null, !14} ; [ DW_TAG_subprogram ] [line 27] [def] [read_response_size]
-!10 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/Users/matt/ryan_bug/<unknown>]
-!11 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!9 = !DISubprogram(name: "read_response_size", linkageName: "_Z18read_response_sizev", line: 27, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 27, file: !1, scope: !10, type: !11, function: i32 ()* @_Z18read_response_sizev, variables: !14)
+!10 = !DIFile(filename: "<unknown>", directory: "/Users/matt/ryan_bug")
+!11 = !DISubroutineType(types: !12)
 !12 = !{!13}
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !14 = !{!15, !19}
-!15 = !{!"0x100\00b\0028\000", !9, !10, !16} ; [ DW_TAG_auto_variable ] [b] [line 28]
-!16 = !{!"0x13\00B\0016\0032\0032\000\000\000", !1, null, null, !17, null, null} ; [ DW_TAG_structure_type ] [B] [line 16, size 32, align 32, offset 0] [def] [from ]
+!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 28, scope: !9, file: !10, type: !16)
+!16 = !DICompositeType(tag: DW_TAG_structure_type, name: "B", line: 16, size: 32, align: 32, file: !1, elements: !17)
 !17 = !{!18}
-!18 = !{!"0xd\00end_of_file\0017\0032\0032\000\000", !1, !16, !13} ; [ DW_TAG_member ] [end_of_file] [line 17, size 32, align 32, offset 0] [from int]
-!19 = !{!"0x100\00c\0029\000", !9, !10, !13} ; [ DW_TAG_auto_variable ] [c] [line 29]
+!18 = !DIDerivedType(tag: DW_TAG_member, name: "end_of_file", line: 17, size: 32, align: 32, file: !1, scope: !16, baseType: !13)
+!19 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "c", line: 29, scope: !9, file: !10, type: !13)
 !20 = !{}
 !21 = !{i32 2, !"Dwarf Version", i32 2}
-!22 = !{i64* getelementptr inbounds ({ i64, [56 x i8] }* @a, i32 0, i32 0)}
-!23 = !{!"0x101\00p2\0033554444\000", !24, !10, !32, !38} ; [ DW_TAG_arg_variable ] [p2] [line 12]
-!24 = !{!"0x2e\00min<unsigned long long>\00min<unsigned long long>\00_ZN3__13minIyEERKT_S3_RS1_\0012\000\001\000\006\00256\001\0012", !1, !25, !27, null, null, !33, null, !35} ; [ DW_TAG_subprogram ] [line 12] [def] [min<unsigned long long>]
-!25 = !{!"0x39\00__1\001", !26, null} ; [ DW_TAG_namespace ] [__1] [line 1]
-!26 = !{!"main.cpp", !"/Users/matt/ryan_bug"}
-!27 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !28, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!22 = !{i64* getelementptr inbounds ({ i64, [56 x i8] }, { i64, [56 x i8] }* @a, i32 0, i32 0)}
+!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p2", line: 12, arg: 2, scope: !24, file: !10, type: !32)
+!24 = !DISubprogram(name: "min<unsigned long long>", linkageName: "_ZN3__13minIyEERKT_S3_RS1_", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 12, file: !1, scope: !25, type: !27, templateParams: !33, variables: !35)
+!25 = !DINamespace(name: "__1", line: 1, file: !26, scope: null)
+!26 = !DIFile(filename: "main.cpp", directory: "/Users/matt/ryan_bug")
+!27 = !DISubroutineType(types: !28)
 !28 = !{!29, !29, !32}
-!29 = !{!"0x10\00\000\000\000\000\000", null, null, !30} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from ]
-!30 = !{!"0x26\00\000\000\000\000\000", null, null, !31} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from long long unsigned int]
-!31 = !{!"0x24\00long long unsigned int\000\0064\0064\000\000\007", null, null} ; [ DW_TAG_base_type ] [long long unsigned int] [line 0, size 64, align 64, offset 0, enc DW_ATE_unsigned]
-!32 = !{!"0x10\00\000\000\000\000\000", null, null, !31} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from long long unsigned int]
+!29 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !30)
+!30 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !31)
+!31 = !DIBasicType(tag: DW_TAG_base_type, name: "long long unsigned int", size: 64, align: 64, encoding: DW_ATE_unsigned)
+!32 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !31)
 !33 = !{!34}
-!34 = !{!"0x2f\00_Tp\000\000", null, !31, null} ; [ DW_TAG_template_type_parameter ]
+!34 = !DITemplateTypeParameter(name: "_Tp", type: !31)
 !35 = !{!36, !37}
-!36 = !{!"0x101\00p1\0016777228\000", !24, !10, !29} ; [ DW_TAG_arg_variable ] [p1] [line 12]
-!37 = !{!"0x101\00p2\0033554444\000", !24, !10, !32} ; [ DW_TAG_arg_variable ] [p2] [line 12]
-!38 = !MDLocation(line: 33, scope: !9)
-!39 = !MDLocation(line: 12, scope: !24, inlinedAt: !38)
-!40 = !MDLocation(line: 9, scope: !41, inlinedAt: !59)
-!41 = !{!"0x2e\00min<unsigned long long, __1::A>\00min<unsigned long long, __1::A>\00_ZN3__13minIyNS_1AEEERKT_S4_RS2_T0_\007\000\001\000\006\00256\001\008", !1, !25, !42, null, null, !53, null, !55} ; [ DW_TAG_subprogram ] [line 7] [def] [scope 8] [min<unsigned long long, __1::A>]
-!42 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !43, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!36 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p1", line: 12, arg: 1, scope: !24, file: !10, type: !29)
+!37 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p2", line: 12, arg: 2, scope: !24, file: !10, type: !32)
+!38 = !DILocation(line: 33, scope: !9)
+!39 = !DILocation(line: 12, scope: !24, inlinedAt: !38)
+!40 = !DILocation(line: 9, scope: !41, inlinedAt: !59)
+!41 = !DISubprogram(name: "min<unsigned long long, __1::A>", linkageName: "_ZN3__13minIyNS_1AEEERKT_S4_RS2_T0_", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 8, file: !1, scope: !25, type: !42, templateParams: !53, variables: !55)
+!42 = !DISubroutineType(types: !43)
 !43 = !{!29, !29, !32, !44}
-!44 = !{!"0x13\00A\000\008\008\000\000\000", !1, !25, null, !45, null, null, null} ; [ DW_TAG_structure_type ] [A] [line 0, size 8, align 8, offset 0] [def] [from ]
+!44 = !DICompositeType(tag: DW_TAG_structure_type, name: "A", size: 8, align: 8, file: !1, scope: !25, elements: !45)
 !45 = !{!46}
-!46 = !{!"0x2e\00operator()\00operator()\00_ZN3__11AclERKiS2_\001\000\000\000\006\00256\001\001", !1, !44, !47, null, null, null, i32 0, !52} ; [ DW_TAG_subprogram ] [line 1] [operator()]
-!47 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !48, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!46 = !DISubprogram(name: "operator()", linkageName: "_ZN3__11AclERKiS2_", line: 1, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !1, scope: !44, type: !47)
+!47 = !DISubroutineType(types: !48)
 !48 = !{!13, !49, !50, !50}
-!49 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !44} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from A]
-!50 = !{!"0x10\00\000\000\000\000\000", null, null, !51} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from ]
-!51 = !{!"0x26\00\000\000\000\000\000", null, null, !13} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from int]
-!52 = !{i32 786468}
+!49 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !44)
+!50 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !51)
+!51 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !13)
 !53 = !{!34, !54}
-!54 = !{!"0x2f\00_Compare\000\000", null, !44, null} ; [ DW_TAG_template_type_parameter ]
+!54 = !DITemplateTypeParameter(name: "_Compare", type: !44)
 !55 = !{!56, !57, !58}
-!56 = !{!"0x101\00p1\0016777223\000", !41, !10, !29} ; [ DW_TAG_arg_variable ] [p1] [line 7]
-!57 = !{!"0x101\00p2\0033554439\000", !41, !10, !32} ; [ DW_TAG_arg_variable ] [p2] [line 7]
-!58 = !{!"0x101\00p3\0050331656\000", !41, !10, !44} ; [ DW_TAG_arg_variable ] [p3] [line 8]
-!59 = !MDLocation(line: 13, scope: !24, inlinedAt: !38)
+!56 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p1", line: 7, arg: 1, scope: !41, file: !10, type: !29)
+!57 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p2", line: 7, arg: 2, scope: !41, file: !10, type: !32)
+!58 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p3", line: 8, arg: 3, scope: !41, file: !10, type: !44)
+!59 = !DILocation(line: 13, scope: !24, inlinedAt: !38)
 !63 = !{i32 undef}
-!64 = !{!"0x101\00p1\0033554433\000", !65, !10, !50, !40} ; [ DW_TAG_arg_variable ] [p1] [line 1]
-!65 = !{!"0x2e\00operator()\00operator()\00_ZN3__11AclERKiS2_\001\000\001\000\006\00256\001\002", !1, !25, !47, null, null, null, !46, !66} ; [ DW_TAG_subprogram ] [line 1] [def] [scope 2] [operator()]
+!64 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p1", line: 1, arg: 2, scope: !65, file: !10, type: !50)
+!65 = !DISubprogram(name: "operator()", linkageName: "_ZN3__11AclERKiS2_", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2, file: !1, scope: !25, type: !47, declaration: !46, variables: !66)
 !66 = !{!67, !69, !70}
-!67 = !{!"0x101\00this\0016777216\001088", !65, null, !68} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!68 = !{!"0xf\00\000\0064\0064\000\000", null, null, !44} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from A]
-!69 = !{!"0x101\00p1\0033554433\000", !65, !10, !50} ; [ DW_TAG_arg_variable ] [p1] [line 1]
-!70 = !{!"0x101\00\0050331650\000", !65, !10, !50} ; [ DW_TAG_arg_variable ] [line 2]
-!71 = !MDLocation(line: 1, scope: !65, inlinedAt: !40)
-!72 = !{i32 1, !"Debug Info Version", i32 2}
+!67 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !65, type: !68)
+!68 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !44)
+!69 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p1", line: 1, arg: 2, scope: !65, file: !10, type: !50)
+!70 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "", line: 2, arg: 3, scope: !65, file: !10, type: !50)
+!71 = !DILocation(line: 1, scope: !65, inlinedAt: !40)
+!72 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/stack-protector-vreg-to-vreg-copy.ll b/test/CodeGen/X86/stack-protector-vreg-to-vreg-copy.ll
index 7d499f9abd74..f3f9eebb26c4 100644
--- a/test/CodeGen/X86/stack-protector-vreg-to-vreg-copy.ll
+++ b/test/CodeGen/X86/stack-protector-vreg-to-vreg-copy.ll
@@ -28,7 +28,7 @@ declare void @g(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
 define void @do_something(i32 %i) #0 {
 entry:
   %data = alloca [8 x i8], align 1
-  %0 = load i32* @state, align 4
+  %0 = load i32, i32* @state, align 4
   %cmp = icmp eq i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
@@ -38,7 +38,7 @@ if.then:                                          ; preds = %entry
 
 if.else:                                          ; preds = %entry
   tail call fastcc void @send_int(i32 %i)
-  %arrayidx = getelementptr inbounds [8 x i8]* %data, i32 0, i32 0
+  %arrayidx = getelementptr inbounds [8 x i8], [8 x i8]* %data, i32 0, i32 0
   call void @zero_char(i8* %arrayidx)
   br label %if.end
 
diff --git a/test/CodeGen/X86/stack-protector-weight.ll b/test/CodeGen/X86/stack-protector-weight.ll
index c5bf49134e4b..4220a4c46a0a 100644
--- a/test/CodeGen/X86/stack-protector-weight.ll
+++ b/test/CodeGen/X86/stack-protector-weight.ll
@@ -18,11 +18,11 @@ entry:
   %a = alloca [128 x i32], align 16
   %0 = bitcast [128 x i32]* %a to i8*
   call void @llvm.lifetime.start(i64 512, i8* %0)
-  %arraydecay = getelementptr inbounds [128 x i32]* %a, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [128 x i32], [128 x i32]* %a, i64 0, i64 0
   call void @foo2(i32* %arraydecay)
   %idxprom = sext i32 %n to i64
-  %arrayidx = getelementptr inbounds [128 x i32]* %a, i64 0, i64 %idxprom
-  %1 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [128 x i32], [128 x i32]* %a, i64 0, i64 %idxprom
+  %1 = load i32, i32* %arrayidx, align 4
   call void @llvm.lifetime.end(i64 512, i8* %0)
   ret i32 %1
 }
diff --git a/test/CodeGen/X86/stack-protector.ll b/test/CodeGen/X86/stack-protector.ll
index 4db0f9a3426b..acaba6dc17f8 100644
--- a/test/CodeGen/X86/stack-protector.ll
+++ b/test/CodeGen/X86/stack-protector.ll
@@ -43,11 +43,11 @@ entry:
   %a.addr = alloca i8*, align 8
   %buf = alloca [16 x i8], align 16
   store i8* %a, i8** %a.addr, align 8
-  %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %arraydecay = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %arraydecay1 = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
+  %arraydecay1 = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i32 0, i32 0
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
   ret void
 }
 
@@ -79,11 +79,11 @@ entry:
   %a.addr = alloca i8*, align 8
   %buf = alloca [16 x i8], align 16
   store i8* %a, i8** %a.addr, align 8
-  %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %arraydecay = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %arraydecay1 = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
+  %arraydecay1 = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i32 0, i32 0
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
   ret void
 }
 
@@ -111,11 +111,11 @@ entry:
   %a.addr = alloca i8*, align 8
   %buf = alloca [16 x i8], align 16
   store i8* %a, i8** %a.addr, align 8
-  %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %arraydecay = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %arraydecay1 = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
+  %arraydecay1 = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i32 0, i32 0
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
   ret void
 }
 
@@ -143,11 +143,11 @@ entry:
   %a.addr = alloca i8*, align 8
   %buf = alloca [16 x i8], align 16
   store i8* %a, i8** %a.addr, align 8
-  %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %arraydecay = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %arraydecay1 = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
+  %arraydecay1 = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i32 0, i32 0
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
   ret void
 }
 
@@ -174,13 +174,13 @@ entry:
   %a.addr = alloca i8*, align 8
   %b = alloca %struct.foo, align 1
   store i8* %a, i8** %a.addr, align 8
-  %buf = getelementptr inbounds %struct.foo* %b, i32 0, i32 0
-  %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %buf = getelementptr inbounds %struct.foo, %struct.foo* %b, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %buf1 = getelementptr inbounds %struct.foo* %b, i32 0, i32 0
-  %arraydecay2 = getelementptr inbounds [16 x i8]* %buf1, i32 0, i32 0
-  %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
+  %buf1 = getelementptr inbounds %struct.foo, %struct.foo* %b, i32 0, i32 0
+  %arraydecay2 = getelementptr inbounds [16 x i8], [16 x i8]* %buf1, i32 0, i32 0
+  %call3 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
   ret void
 }
 
@@ -208,13 +208,13 @@ entry:
   %a.addr = alloca i8*, align 8
   %b = alloca %struct.foo, align 1
   store i8* %a, i8** %a.addr, align 8
-  %buf = getelementptr inbounds %struct.foo* %b, i32 0, i32 0
-  %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %buf = getelementptr inbounds %struct.foo, %struct.foo* %b, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %buf1 = getelementptr inbounds %struct.foo* %b, i32 0, i32 0
-  %arraydecay2 = getelementptr inbounds [16 x i8]* %buf1, i32 0, i32 0
-  %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
+  %buf1 = getelementptr inbounds %struct.foo, %struct.foo* %b, i32 0, i32 0
+  %arraydecay2 = getelementptr inbounds [16 x i8], [16 x i8]* %buf1, i32 0, i32 0
+  %call3 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
   ret void
 }
 
@@ -242,13 +242,13 @@ entry:
   %a.addr = alloca i8*, align 8
   %b = alloca %struct.foo, align 1
   store i8* %a, i8** %a.addr, align 8
-  %buf = getelementptr inbounds %struct.foo* %b, i32 0, i32 0
-  %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %buf = getelementptr inbounds %struct.foo, %struct.foo* %b, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %buf1 = getelementptr inbounds %struct.foo* %b, i32 0, i32 0
-  %arraydecay2 = getelementptr inbounds [16 x i8]* %buf1, i32 0, i32 0
-  %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
+  %buf1 = getelementptr inbounds %struct.foo, %struct.foo* %b, i32 0, i32 0
+  %arraydecay2 = getelementptr inbounds [16 x i8], [16 x i8]* %buf1, i32 0, i32 0
+  %call3 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
   ret void
 }
 
@@ -276,13 +276,13 @@ entry:
   %a.addr = alloca i8*, align 8
   %b = alloca %struct.foo, align 1
   store i8* %a, i8** %a.addr, align 8
-  %buf = getelementptr inbounds %struct.foo* %b, i32 0, i32 0
-  %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %buf = getelementptr inbounds %struct.foo, %struct.foo* %b, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [16 x i8], [16 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %buf1 = getelementptr inbounds %struct.foo* %b, i32 0, i32 0
-  %arraydecay2 = getelementptr inbounds [16 x i8]* %buf1, i32 0, i32 0
-  %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
+  %buf1 = getelementptr inbounds %struct.foo, %struct.foo* %b, i32 0, i32 0
+  %arraydecay2 = getelementptr inbounds [16 x i8], [16 x i8]* %buf1, i32 0, i32 0
+  %call3 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
   ret void
 }
 
@@ -309,11 +309,11 @@ entry:
   %a.addr = alloca i8*, align 8
   %buf = alloca [4 x i8], align 1
   store i8* %a, i8** %a.addr, align 8
-  %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %arraydecay = getelementptr inbounds [4 x i8], [4 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %arraydecay1 = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
+  %arraydecay1 = getelementptr inbounds [4 x i8], [4 x i8]* %buf, i32 0, i32 0
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
   ret void
 }
 
@@ -341,11 +341,11 @@ entry:
   %a.addr = alloca i8*, align 8
   %buf = alloca [4 x i8], align 1
   store i8* %a, i8** %a.addr, align 8
-  %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %arraydecay = getelementptr inbounds [4 x i8], [4 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %arraydecay1 = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
+  %arraydecay1 = getelementptr inbounds [4 x i8], [4 x i8]* %buf, i32 0, i32 0
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
   ret void
 }
 
@@ -373,11 +373,11 @@ entry:
   %a.addr = alloca i8*, align 8
   %buf = alloca [4 x i8], align 1
   store i8* %a, i8** %a.addr, align 8
-  %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %arraydecay = getelementptr inbounds [4 x i8], [4 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %arraydecay1 = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
+  %arraydecay1 = getelementptr inbounds [4 x i8], [4 x i8]* %buf, i32 0, i32 0
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
   ret void
 }
 
@@ -405,11 +405,11 @@ entry:
   %a.addr = alloca i8*, align 8
   %buf = alloca [4 x i8], align 1
   store i8* %a, i8** %a.addr, align 8
-  %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %arraydecay = getelementptr inbounds [4 x i8], [4 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %arraydecay1 = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
+  %arraydecay1 = getelementptr inbounds [4 x i8], [4 x i8]* %buf, i32 0, i32 0
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1)
   ret void
 }
 
@@ -436,13 +436,13 @@ entry:
   %a.addr = alloca i8*, align 8
   %b = alloca %struct.foo.0, align 1
   store i8* %a, i8** %a.addr, align 8
-  %buf = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0
-  %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %buf = getelementptr inbounds %struct.foo.0, %struct.foo.0* %b, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [4 x i8], [4 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %buf1 = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0
-  %arraydecay2 = getelementptr inbounds [4 x i8]* %buf1, i32 0, i32 0
-  %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
+  %buf1 = getelementptr inbounds %struct.foo.0, %struct.foo.0* %b, i32 0, i32 0
+  %arraydecay2 = getelementptr inbounds [4 x i8], [4 x i8]* %buf1, i32 0, i32 0
+  %call3 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
   ret void
 }
 
@@ -470,13 +470,13 @@ entry:
   %a.addr = alloca i8*, align 8
   %b = alloca %struct.foo.0, align 1
   store i8* %a, i8** %a.addr, align 8
-  %buf = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0
-  %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %buf = getelementptr inbounds %struct.foo.0, %struct.foo.0* %b, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [4 x i8], [4 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %buf1 = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0
-  %arraydecay2 = getelementptr inbounds [4 x i8]* %buf1, i32 0, i32 0
-  %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
+  %buf1 = getelementptr inbounds %struct.foo.0, %struct.foo.0* %b, i32 0, i32 0
+  %arraydecay2 = getelementptr inbounds [4 x i8], [4 x i8]* %buf1, i32 0, i32 0
+  %call3 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
   ret void
 }
 
@@ -504,13 +504,13 @@ entry:
   %a.addr = alloca i8*, align 8
   %b = alloca %struct.foo.0, align 1
   store i8* %a, i8** %a.addr, align 8
-  %buf = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0
-  %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %buf = getelementptr inbounds %struct.foo.0, %struct.foo.0* %b, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [4 x i8], [4 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %buf1 = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0
-  %arraydecay2 = getelementptr inbounds [4 x i8]* %buf1, i32 0, i32 0
-  %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
+  %buf1 = getelementptr inbounds %struct.foo.0, %struct.foo.0* %b, i32 0, i32 0
+  %arraydecay2 = getelementptr inbounds [4 x i8], [4 x i8]* %buf1, i32 0, i32 0
+  %call3 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
   ret void
 }
 
@@ -538,13 +538,13 @@ entry:
   %a.addr = alloca i8*, align 8
   %b = alloca %struct.foo.0, align 1
   store i8* %a, i8** %a.addr, align 8
-  %buf = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0
-  %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0
-  %0 = load i8** %a.addr, align 8
+  %buf = getelementptr inbounds %struct.foo.0, %struct.foo.0* %b, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [4 x i8], [4 x i8]* %buf, i32 0, i32 0
+  %0 = load i8*, i8** %a.addr, align 8
   %call = call i8* @strcpy(i8* %arraydecay, i8* %0)
-  %buf1 = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0
-  %arraydecay2 = getelementptr inbounds [4 x i8]* %buf1, i32 0, i32 0
-  %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
+  %buf1 = getelementptr inbounds %struct.foo.0, %struct.foo.0* %b, i32 0, i32 0
+  %arraydecay2 = getelementptr inbounds [4 x i8], [4 x i8]* %buf1, i32 0, i32 0
+  %call3 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2)
   ret void
 }
 
@@ -570,8 +570,8 @@ entry:
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
   store i8* %a, i8** %a.addr, align 8
-  %0 = load i8** %a.addr, align 8
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %0)
+  %0 = load i8*, i8** %a.addr, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %0)
   ret void
 }
 
@@ -598,8 +598,8 @@ entry:
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
   store i8* %a, i8** %a.addr, align 8
-  %0 = load i8** %a.addr, align 8
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %0)
+  %0 = load i8*, i8** %a.addr, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %0)
   ret void
 }
 
@@ -626,8 +626,8 @@ entry:
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
   store i8* %a, i8** %a.addr, align 8
-  %0 = load i8** %a.addr, align 8
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %0)
+  %0 = load i8*, i8** %a.addr, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %0)
   ret void
 }
 
@@ -654,8 +654,8 @@ entry:
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
   store i8* %a, i8** %a.addr, align 8
-  %0 = load i8** %a.addr, align 8
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %0)
+  %0 = load i8*, i8** %a.addr, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %0)
   ret void
 }
 
@@ -683,7 +683,7 @@ entry:
   %a = alloca i32, align 4
   %j = alloca i32*, align 8
   store i32 0, i32* %retval
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %add = add nsw i32 %0, 1
   store i32 %add, i32* %a, align 4
   store i32* %a, i32** %j, align 8
@@ -715,7 +715,7 @@ entry:
   %a = alloca i32, align 4
   %j = alloca i32*, align 8
   store i32 0, i32* %retval
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %add = add nsw i32 %0, 1
   store i32 %add, i32* %a, align 4
   store i32* %a, i32** %j, align 8
@@ -747,7 +747,7 @@ entry:
   %a = alloca i32, align 4
   %j = alloca i32*, align 8
   store i32 0, i32* %retval
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %add = add nsw i32 %0, 1
   store i32 %add, i32* %a, align 4
   store i32* %a, i32** %j, align 8
@@ -779,7 +779,7 @@ entry:
   %a = alloca i32, align 4
   %j = alloca i32*, align 8
   store i32 0, i32* %retval
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %add = add nsw i32 %0, 1
   store i32 %add, i32* %a, align 4
   store i32* %a, i32** %j, align 8
@@ -808,7 +808,7 @@ entry:
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
   %0 = ptrtoint i32* %a to i64
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i64 %0)
   ret void
 }
 
@@ -835,7 +835,7 @@ entry:
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
   %0 = ptrtoint i32* %a to i64
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i64 %0)
   ret void
 }
 
@@ -862,7 +862,7 @@ entry:
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
   %0 = ptrtoint i32* %a to i64
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i64 %0)
   ret void
 }
 
@@ -889,7 +889,7 @@ entry:
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
   %0 = ptrtoint i32* %a to i64
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i64 %0)
   ret void
 }
 
@@ -1021,7 +1021,7 @@ entry:
   store double %call, double* %x, align 8
   %cmp2 = fcmp ogt double %call, 0.000000e+00
   %y.1 = select i1 %cmp2, double* %x, double* null
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), double* %y.1)
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), double* %y.1)
   ret void
 }
 
@@ -1051,7 +1051,7 @@ entry:
   store double %call, double* %x, align 8
   %cmp2 = fcmp ogt double %call, 0.000000e+00
   %y.1 = select i1 %cmp2, double* %x, double* null
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), double* %y.1)
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), double* %y.1)
   ret void
 }
 
@@ -1081,7 +1081,7 @@ entry:
   store double %call, double* %x, align 8
   %cmp2 = fcmp ogt double %call, 0.000000e+00
   %y.1 = select i1 %cmp2, double* %x, double* null
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), double* %y.1)
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), double* %y.1)
   ret void
 }
 
@@ -1111,7 +1111,7 @@ entry:
   store double %call, double* %x, align 8
   %cmp2 = fcmp ogt double %call, 0.000000e+00
   %y.1 = select i1 %cmp2, double* %x, double* null
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), double* %y.1)
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), double* %y.1)
   ret void
 }
 
@@ -1155,7 +1155,7 @@ if.then3:                                         ; preds = %if.else
 
 if.end4:                                          ; preds = %if.else, %if.then3, %if.then
   %y.0 = phi double* [ null, %if.then ], [ %x, %if.then3 ], [ null, %if.else ]
-  %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), double* %y.0)
+  %call5 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), double* %y.0)
   ret void
 }
 
@@ -1200,7 +1200,7 @@ if.then3:                                         ; preds = %if.else
 
 if.end4:                                          ; preds = %if.else, %if.then3, %if.then
   %y.0 = phi double* [ null, %if.then ], [ %x, %if.then3 ], [ null, %if.else ]
-  %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), double* %y.0)
+  %call5 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), double* %y.0)
   ret void
 }
 
@@ -1245,7 +1245,7 @@ if.then3:                                         ; preds = %if.else
 
 if.end4:                                          ; preds = %if.else, %if.then3, %if.then
   %y.0 = phi double* [ null, %if.then ], [ %x, %if.then3 ], [ null, %if.else ]
-  %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), double* %y.0)
+  %call5 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), double* %y.0)
   ret void
 }
 
@@ -1290,7 +1290,7 @@ if.then3:                                         ; preds = %if.else
 
 if.end4:                                          ; preds = %if.else, %if.then3, %if.then
   %y.0 = phi double* [ null, %if.then ], [ %x, %if.then3 ], [ null, %if.else ]
-  %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), double* %y.0)
+  %call5 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), double* %y.0)
   ret void
 }
 
@@ -1316,10 +1316,10 @@ entry:
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
   %b = alloca i32*, align 8
-  %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1
+  %y = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 1
   store i32* %y, i32** %b, align 8
-  %0 = load i32** %b, align 8
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32* %0)
+  %0 = load i32*, i32** %b, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32* %0)
   ret void
 }
 
@@ -1346,10 +1346,10 @@ entry:
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
   %b = alloca i32*, align 8
-  %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1
+  %y = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 1
   store i32* %y, i32** %b, align 8
-  %0 = load i32** %b, align 8
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32* %0)
+  %0 = load i32*, i32** %b, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32* %0)
   ret void
 }
 
@@ -1376,10 +1376,10 @@ entry:
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
   %b = alloca i32*, align 8
-  %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1
+  %y = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 1
   store i32* %y, i32** %b, align 8
-  %0 = load i32** %b, align 8
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32* %0)
+  %0 = load i32*, i32** %b, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32* %0)
   ret void
 }
 
@@ -1406,10 +1406,10 @@ entry:
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
   %b = alloca i32*, align 8
-  %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1
+  %y = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 1
   store i32* %y, i32** %b, align 8
-  %0 = load i32** %b, align 8
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32* %0)
+  %0 = load i32*, i32** %b, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32* %0)
   ret void
 }
 
@@ -1435,9 +1435,9 @@ entry:
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
   %b = alloca i32*, align 8
-  %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1
+  %y = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 1
   %0 = ptrtoint i32* %y to i64
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i64 %0)
   ret void
 }
 
@@ -1464,9 +1464,9 @@ entry:
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
   %b = alloca i32*, align 8
-  %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1
+  %y = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 1
   %0 = ptrtoint i32* %y to i64
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i64 %0)
   ret void
 }
 
@@ -1492,9 +1492,9 @@ entry:
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
   %b = alloca i32*, align 8
-  %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1
+  %y = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 1
   %0 = ptrtoint i32* %y to i64
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i64 %0)
   ret void
 }
 
@@ -1521,9 +1521,9 @@ entry:
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
   %b = alloca i32*, align 8
-  %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1
+  %y = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 1
   %0 = ptrtoint i32* %y to i64
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i64 %0)
   ret void
 }
 
@@ -1548,8 +1548,8 @@ entry:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
-  %y = getelementptr inbounds %struct.pair* %c, i64 0, i32 1
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %y)
+  %y = getelementptr inbounds %struct.pair, %struct.pair* %c, i64 0, i32 1
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32* %y)
   ret void
 }
 
@@ -1575,8 +1575,8 @@ entry:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
-  %y = getelementptr inbounds %struct.pair* %c, i64 0, i32 1
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %y)
+  %y = getelementptr inbounds %struct.pair, %struct.pair* %c, i64 0, i32 1
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32* %y)
   ret void
 }
 
@@ -1602,8 +1602,8 @@ entry:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
-  %y = getelementptr inbounds %struct.pair* %c, i64 0, i32 1
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %y)
+  %y = getelementptr inbounds %struct.pair, %struct.pair* %c, i64 0, i32 1
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32* %y)
   ret void
 }
 
@@ -1629,8 +1629,8 @@ entry:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
-  %y = getelementptr inbounds %struct.pair* %c, i64 0, i32 1
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %y)
+  %y = getelementptr inbounds %struct.pair, %struct.pair* %c, i64 0, i32 1
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32* %y)
   ret void
 }
 
@@ -1655,8 +1655,8 @@ entry:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
-  %add.ptr5 = getelementptr inbounds i32* %a, i64 -12
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %add.ptr5)
+  %add.ptr5 = getelementptr inbounds i32, i32* %a, i64 -12
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32* %add.ptr5)
   ret void
 }
 
@@ -1682,8 +1682,8 @@ entry:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
-  %add.ptr5 = getelementptr inbounds i32* %a, i64 -12
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %add.ptr5)
+  %add.ptr5 = getelementptr inbounds i32, i32* %a, i64 -12
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32* %add.ptr5)
   ret void
 }
 
@@ -1709,8 +1709,8 @@ entry:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
-  %add.ptr5 = getelementptr inbounds i32* %a, i64 -12
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %add.ptr5)
+  %add.ptr5 = getelementptr inbounds i32, i32* %a, i64 -12
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32* %add.ptr5)
   ret void
 }
 
@@ -1736,8 +1736,8 @@ entry:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
-  %add.ptr5 = getelementptr inbounds i32* %a, i64 -12
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %add.ptr5)
+  %add.ptr5 = getelementptr inbounds i32, i32* %a, i64 -12
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32* %add.ptr5)
   ret void
 }
 
@@ -1767,8 +1767,8 @@ entry:
   store i32 0, i32* %a, align 4
   %0 = bitcast i32* %a to float*
   store float* %0, float** %b, align 8
-  %1 = load float** %b, align 8
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), float* %1)
+  %1 = load float*, float** %b, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), float* %1)
   ret void
 }
 
@@ -1799,8 +1799,8 @@ entry:
   store i32 0, i32* %a, align 4
   %0 = bitcast i32* %a to float*
   store float* %0, float** %b, align 8
-  %1 = load float** %b, align 8
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), float* %1)
+  %1 = load float*, float** %b, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), float* %1)
   ret void
 }
 
@@ -1831,8 +1831,8 @@ entry:
   store i32 0, i32* %a, align 4
   %0 = bitcast i32* %a to float*
   store float* %0, float** %b, align 8
-  %1 = load float** %b, align 8
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), float* %1)
+  %1 = load float*, float** %b, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), float* %1)
   ret void
 }
 
@@ -1863,8 +1863,8 @@ entry:
   store i32 0, i32* %a, align 4
   %0 = bitcast i32* %a to float*
   store float* %0, float** %b, align 8
-  %1 = load float** %b, align 8
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), float* %1)
+  %1 = load float*, float** %b, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), float* %1)
   ret void
 }
 
@@ -2004,9 +2004,9 @@ entry:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.vec, align 16
-  %y = getelementptr inbounds %struct.vec* %c, i64 0, i32 0
-  %add.ptr = getelementptr inbounds <4 x i32>* %y, i64 -12
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), <4 x i32>* %add.ptr)
+  %y = getelementptr inbounds %struct.vec, %struct.vec* %c, i64 0, i32 0
+  %add.ptr = getelementptr inbounds <4 x i32>, <4 x i32>* %y, i64 -12
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), <4 x i32>* %add.ptr)
   ret void
 }
 
@@ -2032,9 +2032,9 @@ entry:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.vec, align 16
-  %y = getelementptr inbounds %struct.vec* %c, i64 0, i32 0
-  %add.ptr = getelementptr inbounds <4 x i32>* %y, i64 -12
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), <4 x i32>* %add.ptr)
+  %y = getelementptr inbounds %struct.vec, %struct.vec* %c, i64 0, i32 0
+  %add.ptr = getelementptr inbounds <4 x i32>, <4 x i32>* %y, i64 -12
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), <4 x i32>* %add.ptr)
   ret void
 }
 
@@ -2060,9 +2060,9 @@ entry:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.vec, align 16
-  %y = getelementptr inbounds %struct.vec* %c, i64 0, i32 0
-  %add.ptr = getelementptr inbounds <4 x i32>* %y, i64 -12
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), <4 x i32>* %add.ptr)
+  %y = getelementptr inbounds %struct.vec, %struct.vec* %c, i64 0, i32 0
+  %add.ptr = getelementptr inbounds <4 x i32>, <4 x i32>* %y, i64 -12
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), <4 x i32>* %add.ptr)
   ret void
 }
 
@@ -2088,9 +2088,9 @@ entry:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.vec, align 16
-  %y = getelementptr inbounds %struct.vec* %c, i64 0, i32 0
-  %add.ptr = getelementptr inbounds <4 x i32>* %y, i64 -12
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), <4 x i32>* %add.ptr)
+  %y = getelementptr inbounds %struct.vec, %struct.vec* %c, i64 0, i32 0
+  %add.ptr = getelementptr inbounds <4 x i32>, <4 x i32>* %y, i64 -12
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), <4 x i32>* %add.ptr)
   ret void
 }
 
@@ -2264,9 +2264,9 @@ entry:
   %c = alloca %struct.pair, align 4
   %exn.slot = alloca i8*
   %ehselector.slot = alloca i32
-  %a = getelementptr inbounds %struct.pair* %c, i32 0, i32 0
+  %a = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 0
   store i32 0, i32* %a, align 4
-  %a1 = getelementptr inbounds %struct.pair* %c, i32 0, i32 0
+  %a1 = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 0
   invoke void @_Z3exceptPi(i32* %a1)
           to label %invoke.cont unwind label %lpad
 
@@ -2304,9 +2304,9 @@ entry:
   %c = alloca %struct.pair, align 4
   %exn.slot = alloca i8*
   %ehselector.slot = alloca i32
-  %a = getelementptr inbounds %struct.pair* %c, i32 0, i32 0
+  %a = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 0
   store i32 0, i32* %a, align 4
-  %a1 = getelementptr inbounds %struct.pair* %c, i32 0, i32 0
+  %a1 = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 0
   invoke void @_Z3exceptPi(i32* %a1)
           to label %invoke.cont unwind label %lpad
 
@@ -2344,9 +2344,9 @@ entry:
   %c = alloca %struct.pair, align 4
   %exn.slot = alloca i8*
   %ehselector.slot = alloca i32
-  %a = getelementptr inbounds %struct.pair* %c, i32 0, i32 0
+  %a = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 0
   store i32 0, i32* %a, align 4
-  %a1 = getelementptr inbounds %struct.pair* %c, i32 0, i32 0
+  %a1 = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 0
   invoke void @_Z3exceptPi(i32* %a1)
           to label %invoke.cont unwind label %lpad
 
@@ -2388,9 +2388,9 @@ entry:
   %c = alloca %struct.pair, align 4
   %exn.slot = alloca i8*
   %ehselector.slot = alloca i32
-  %a = getelementptr inbounds %struct.pair* %c, i32 0, i32 0
+  %a = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 0
   store i32 0, i32* %a, align 4
-  %a1 = getelementptr inbounds %struct.pair* %c, i32 0, i32 0
+  %a1 = getelementptr inbounds %struct.pair, %struct.pair* %c, i32 0, i32 0
   invoke void @_Z3exceptPi(i32* %a1)
           to label %invoke.cont unwind label %lpad
 
@@ -2428,7 +2428,7 @@ entry:
   %call = call i32* @getp()
   store i32* %call, i32** %a, align 8
   store i32** %a, i32*** %b, align 8
-  %0 = load i32*** %b, align 8
+  %0 = load i32**, i32*** %b, align 8
   call void @funcall2(i32** %0)
   ret void
 }
@@ -2459,7 +2459,7 @@ entry:
   %call = call i32* @getp()
   store i32* %call, i32** %a, align 8
   store i32** %a, i32*** %b, align 8
-  %0 = load i32*** %b, align 8
+  %0 = load i32**, i32*** %b, align 8
   call void @funcall2(i32** %0)
   ret void
 }
@@ -2490,7 +2490,7 @@ entry:
   %call = call i32* @getp()
   store i32* %call, i32** %a, align 8
   store i32** %a, i32*** %b, align 8
-  %0 = load i32*** %b, align 8
+  %0 = load i32**, i32*** %b, align 8
   call void @funcall2(i32** %0)
   ret void
 }
@@ -2521,7 +2521,7 @@ entry:
   %call = call i32* @getp()
   store i32* %call, i32** %a, align 8
   store i32** %a, i32*** %b, align 8
-  %0 = load i32*** %b, align 8
+  %0 = load i32**, i32*** %b, align 8
   call void @funcall2(i32** %0)
   ret void
 }
@@ -2552,7 +2552,7 @@ entry:
   store i32* %call, i32** %a, align 8
   %0 = bitcast i32** %a to float**
   store float** %0, float*** %b, align 8
-  %1 = load float*** %b, align 8
+  %1 = load float**, float*** %b, align 8
   call void @funfloat2(float** %1)
   ret void
 }
@@ -2584,7 +2584,7 @@ entry:
   store i32* %call, i32** %a, align 8
   %0 = bitcast i32** %a to float**
   store float** %0, float*** %b, align 8
-  %1 = load float*** %b, align 8
+  %1 = load float**, float*** %b, align 8
   call void @funfloat2(float** %1)
   ret void
 }
@@ -2616,7 +2616,7 @@ entry:
   store i32* %call, i32** %a, align 8
   %0 = bitcast i32** %a to float**
   store float** %0, float*** %b, align 8
-  %1 = load float*** %b, align 8
+  %1 = load float**, float*** %b, align 8
   call void @funfloat2(float** %1)
   ret void
 }
@@ -2648,7 +2648,7 @@ entry:
   store i32* %call, i32** %a, align 8
   %0 = bitcast i32** %a to float**
   store float** %0, float*** %b, align 8
-  %1 = load float*** %b, align 8
+  %1 = load float**, float*** %b, align 8
   call void @funfloat2(float** %1)
   ret void
 }
@@ -2674,9 +2674,9 @@ entry:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca %class.A, align 1
-  %array = getelementptr inbounds %class.A* %a, i32 0, i32 0
-  %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0
-  %0 = load i8* %arrayidx, align 1
+  %array = getelementptr inbounds %class.A, %class.A* %a, i32 0, i32 0
+  %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* %array, i32 0, i64 0
+  %0 = load i8, i8* %arrayidx, align 1
   ret i8 %0
 }
 
@@ -2702,9 +2702,9 @@ entry:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca %class.A, align 1
-  %array = getelementptr inbounds %class.A* %a, i32 0, i32 0
-  %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0
-  %0 = load i8* %arrayidx, align 1
+  %array = getelementptr inbounds %class.A, %class.A* %a, i32 0, i32 0
+  %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* %array, i32 0, i64 0
+  %0 = load i8, i8* %arrayidx, align 1
   ret i8 %0
 }
 
@@ -2730,9 +2730,9 @@ entry:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca %class.A, align 1
-  %array = getelementptr inbounds %class.A* %a, i32 0, i32 0
-  %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0
-  %0 = load i8* %arrayidx, align 1
+  %array = getelementptr inbounds %class.A, %class.A* %a, i32 0, i32 0
+  %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* %array, i32 0, i64 0
+  %0 = load i8, i8* %arrayidx, align 1
   ret i8 %0
 }
 
@@ -2758,9 +2758,9 @@ entry:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca %class.A, align 1
-  %array = getelementptr inbounds %class.A* %a, i32 0, i32 0
-  %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0
-  %0 = load i8* %arrayidx, align 1
+  %array = getelementptr inbounds %class.A, %class.A* %a, i32 0, i32 0
+  %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* %array, i32 0, i64 0
+  %0 = load i8, i8* %arrayidx, align 1
   ret i8 %0
 }
 
@@ -2785,13 +2785,13 @@ entry:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %x = alloca %struct.deep, align 1
-  %b = getelementptr inbounds %struct.deep* %x, i32 0, i32 0
+  %b = getelementptr inbounds %struct.deep, %struct.deep* %x, i32 0, i32 0
   %c = bitcast %union.anon* %b to %struct.anon*
-  %d = getelementptr inbounds %struct.anon* %c, i32 0, i32 0
-  %e = getelementptr inbounds %struct.anon.0* %d, i32 0, i32 0
+  %d = getelementptr inbounds %struct.anon, %struct.anon* %c, i32 0, i32 0
+  %e = getelementptr inbounds %struct.anon.0, %struct.anon.0* %d, i32 0, i32 0
   %array = bitcast %union.anon.1* %e to [2 x i8]*
-  %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* %array, i32 0, i64 0
+  %0 = load i8, i8* %arrayidx, align 1
   ret i8 %0
 }
 
@@ -2817,13 +2817,13 @@ entry:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %x = alloca %struct.deep, align 1
-  %b = getelementptr inbounds %struct.deep* %x, i32 0, i32 0
+  %b = getelementptr inbounds %struct.deep, %struct.deep* %x, i32 0, i32 0
   %c = bitcast %union.anon* %b to %struct.anon*
-  %d = getelementptr inbounds %struct.anon* %c, i32 0, i32 0
-  %e = getelementptr inbounds %struct.anon.0* %d, i32 0, i32 0
+  %d = getelementptr inbounds %struct.anon, %struct.anon* %c, i32 0, i32 0
+  %e = getelementptr inbounds %struct.anon.0, %struct.anon.0* %d, i32 0, i32 0
   %array = bitcast %union.anon.1* %e to [2 x i8]*
-  %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* %array, i32 0, i64 0
+  %0 = load i8, i8* %arrayidx, align 1
   ret i8 %0
 }
 
@@ -2849,13 +2849,13 @@ entry:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %x = alloca %struct.deep, align 1
-  %b = getelementptr inbounds %struct.deep* %x, i32 0, i32 0
+  %b = getelementptr inbounds %struct.deep, %struct.deep* %x, i32 0, i32 0
   %c = bitcast %union.anon* %b to %struct.anon*
-  %d = getelementptr inbounds %struct.anon* %c, i32 0, i32 0
-  %e = getelementptr inbounds %struct.anon.0* %d, i32 0, i32 0
+  %d = getelementptr inbounds %struct.anon, %struct.anon* %c, i32 0, i32 0
+  %e = getelementptr inbounds %struct.anon.0, %struct.anon.0* %d, i32 0, i32 0
   %array = bitcast %union.anon.1* %e to [2 x i8]*
-  %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* %array, i32 0, i64 0
+  %0 = load i8, i8* %arrayidx, align 1
   ret i8 %0
 }
 
@@ -2881,13 +2881,13 @@ entry:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %x = alloca %struct.deep, align 1
-  %b = getelementptr inbounds %struct.deep* %x, i32 0, i32 0
+  %b = getelementptr inbounds %struct.deep, %struct.deep* %x, i32 0, i32 0
   %c = bitcast %union.anon* %b to %struct.anon*
-  %d = getelementptr inbounds %struct.anon* %c, i32 0, i32 0
-  %e = getelementptr inbounds %struct.anon.0* %d, i32 0, i32 0
+  %d = getelementptr inbounds %struct.anon, %struct.anon* %c, i32 0, i32 0
+  %e = getelementptr inbounds %struct.anon.0, %struct.anon.0* %d, i32 0, i32 0
   %array = bitcast %union.anon.1* %e to [2 x i8]*
-  %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* %array, i32 0, i64 0
+  %0 = load i8, i8* %arrayidx, align 1
   ret i8 %0
 }
 
@@ -2914,7 +2914,7 @@ entry:
   %n.addr = alloca i32, align 4
   %a = alloca i32*, align 8
   store i32 %n, i32* %n.addr, align 4
-  %0 = load i32* %n.addr, align 4
+  %0 = load i32, i32* %n.addr, align 4
   %conv = sext i32 %0 to i64
   %1 = alloca i8, i64 %conv
   %2 = bitcast i8* %1 to i32*
@@ -2946,7 +2946,7 @@ entry:
   %n.addr = alloca i32, align 4
   %a = alloca i32*, align 8
   store i32 %n, i32* %n.addr, align 4
-  %0 = load i32* %n.addr, align 4
+  %0 = load i32, i32* %n.addr, align 4
   %conv = sext i32 %0 to i64
   %1 = alloca i8, i64 %conv
   %2 = bitcast i8* %1 to i32*
@@ -2978,7 +2978,7 @@ entry:
   %n.addr = alloca i32, align 4
   %a = alloca i32*, align 8
   store i32 %n, i32* %n.addr, align 4
-  %0 = load i32* %n.addr, align 4
+  %0 = load i32, i32* %n.addr, align 4
   %conv = sext i32 %0 to i64
   %1 = alloca i8, i64 %conv
   %2 = bitcast i8* %1 to i32*
@@ -3010,7 +3010,7 @@ entry:
   %n.addr = alloca i32, align 4
   %a = alloca i32*, align 8
   store i32 %n, i32* %n.addr, align 4
-  %0 = load i32* %n.addr, align 4
+  %0 = load i32, i32* %n.addr, align 4
   %conv = sext i32 %0 to i64
   %1 = alloca i8, i64 %conv
   %2 = bitcast i8* %1 to i32*
@@ -3039,8 +3039,8 @@ entry:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca [4 x i32], align 16
-  %arrayidx = getelementptr inbounds [4 x i32]* %a, i32 0, i64 0
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [4 x i32], [4 x i32]* %a, i32 0, i64 0
+  %0 = load i32, i32* %arrayidx, align 4
   ret i32 %0
 }
 
@@ -3066,8 +3066,8 @@ entry:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca [4 x i32], align 16
-  %arrayidx = getelementptr inbounds [4 x i32]* %a, i32 0, i64 0
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [4 x i32], [4 x i32]* %a, i32 0, i64 0
+  %0 = load i32, i32* %arrayidx, align 4
   ret i32 %0
 }
 
@@ -3093,8 +3093,8 @@ entry:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca [4 x i32], align 16
-  %arrayidx = getelementptr inbounds [4 x i32]* %a, i32 0, i64 0
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [4 x i32], [4 x i32]* %a, i32 0, i64 0
+  %0 = load i32, i32* %arrayidx, align 4
   ret i32 %0
 }
 
@@ -3120,8 +3120,8 @@ entry:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca [4 x i32], align 16
-  %arrayidx = getelementptr inbounds [4 x i32]* %a, i32 0, i64 0
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [4 x i32], [4 x i32]* %a, i32 0, i64 0
+  %0 = load i32, i32* %arrayidx, align 4
   ret i32 %0
 }
 
@@ -3149,10 +3149,10 @@ entry:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.nest, align 4
-  %b = getelementptr inbounds %struct.nest* %c, i32 0, i32 1
-  %_a = getelementptr inbounds %struct.pair* %b, i32 0, i32 0
-  %0 = load i32* %_a, align 4
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 %0)
+  %b = getelementptr inbounds %struct.nest, %struct.nest* %c, i32 0, i32 1
+  %_a = getelementptr inbounds %struct.pair, %struct.pair* %b, i32 0, i32 0
+  %0 = load i32, i32* %_a, align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %0)
   ret void
 }
 
@@ -3181,8 +3181,8 @@ bb:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %tmp = alloca %struct.small*, align 8
-  %tmp1 = call i32 (...)* @dummy(%struct.small** %tmp)
-  %tmp2 = load %struct.small** %tmp, align 8
+  %tmp1 = call i32 (...) @dummy(%struct.small** %tmp)
+  %tmp2 = load %struct.small*, %struct.small** %tmp, align 8
   %tmp3 = ptrtoint %struct.small* %tmp2 to i64
   %tmp4 = trunc i64 %tmp3 to i32
   %tmp5 = icmp sgt i32 %tmp4, 0
@@ -3192,8 +3192,8 @@ bb6:                                              ; preds = %bb17, %bb
   %tmp7 = phi %struct.small* [ %tmp19, %bb17 ], [ %tmp2, %bb ]
   %tmp8 = phi i64 [ %tmp20, %bb17 ], [ 1, %bb ]
   %tmp9 = phi i32 [ %tmp14, %bb17 ], [ %tmp1, %bb ]
-  %tmp10 = getelementptr inbounds %struct.small* %tmp7, i64 0, i32 0
-  %tmp11 = load i8* %tmp10, align 1
+  %tmp10 = getelementptr inbounds %struct.small, %struct.small* %tmp7, i64 0, i32 0
+  %tmp11 = load i8, i8* %tmp10, align 1
   %tmp12 = icmp eq i8 %tmp11, 1
   %tmp13 = add nsw i32 %tmp9, 8
   %tmp14 = select i1 %tmp12, i32 %tmp13, i32 %tmp9
@@ -3202,14 +3202,14 @@ bb6:                                              ; preds = %bb17, %bb
   br i1 %tmp16, label %bb21, label %bb17
 
 bb17:                                             ; preds = %bb6
-  %tmp18 = getelementptr inbounds %struct.small** %tmp, i64 %tmp8
-  %tmp19 = load %struct.small** %tmp18, align 8
+  %tmp18 = getelementptr inbounds %struct.small*, %struct.small** %tmp, i64 %tmp8
+  %tmp19 = load %struct.small*, %struct.small** %tmp18, align 8
   %tmp20 = add i64 %tmp8, 1
   br label %bb6
 
 bb21:                                             ; preds = %bb6, %bb
   %tmp22 = phi i32 [ %tmp1, %bb ], [ %tmp14, %bb6 ]
-  %tmp23 = call i32 (...)* @dummy(i32 %tmp22)
+  %tmp23 = call i32 (...) @dummy(i32 %tmp22)
   ret i32 undef
 }
 
@@ -3234,8 +3234,8 @@ entry:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %test = alloca [32 x i8], align 16
-  %arraydecay = getelementptr inbounds [32 x i8]* %test, i32 0, i32 0
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay)
+  %arraydecay = getelementptr inbounds [32 x i8], [32 x i8]* %test, i32 0, i32 0
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay)
   ret i32 %call
 }
 
@@ -3260,8 +3260,8 @@ entry:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %test = alloca [33 x i8], align 16
-  %arraydecay = getelementptr inbounds [33 x i8]* %test, i32 0, i32 0
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay)
+  %arraydecay = getelementptr inbounds [33 x i8], [33 x i8]* %test, i32 0, i32 0
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay)
   ret i32 %call
 }
 
@@ -3286,8 +3286,8 @@ entry:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %test = alloca [4 x i8], align 1
-  %arraydecay = getelementptr inbounds [4 x i8]* %test, i32 0, i32 0
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay)
+  %arraydecay = getelementptr inbounds [4 x i8], [4 x i8]* %test, i32 0, i32 0
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay)
   ret i32 %call
 }
 
@@ -3312,8 +3312,8 @@ entry:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %test = alloca [5 x i8], align 1
-  %arraydecay = getelementptr inbounds [5 x i8]* %test, i32 0, i32 0
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay)
+  %arraydecay = getelementptr inbounds [5 x i8], [5 x i8]* %test, i32 0, i32 0
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay)
   ret i32 %call
 }
 
@@ -3343,11 +3343,11 @@ entry:
   %0 = bitcast { i64, i8 }* %test.coerce to i8*
   %1 = bitcast %struct.small_char* %test to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 12, i32 0, i1 false)
-  %2 = getelementptr { i64, i8 }* %test.coerce, i32 0, i32 0
-  %3 = load i64* %2, align 1
-  %4 = getelementptr { i64, i8 }* %test.coerce, i32 0, i32 1
-  %5 = load i8* %4, align 1
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %3, i8 %5)
+  %2 = getelementptr { i64, i8 }, { i64, i8 }* %test.coerce, i32 0, i32 0
+  %3 = load i64, i64* %2, align 1
+  %4 = getelementptr { i64, i8 }, { i64, i8 }* %test.coerce, i32 0, i32 1
+  %5 = load i8, i8* %4, align 1
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i64 %3, i8 %5)
   ret i32 %call
 }
 
@@ -3377,11 +3377,11 @@ entry:
   %0 = bitcast { i64, i8 }* %test.coerce to i8*
   %1 = bitcast %struct.small_char* %test to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 12, i32 0, i1 false)
-  %2 = getelementptr { i64, i8 }* %test.coerce, i32 0, i32 0
-  %3 = load i64* %2, align 1
-  %4 = getelementptr { i64, i8 }* %test.coerce, i32 0, i32 1
-  %5 = load i8* %4, align 1
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %3, i8 %5)
+  %2 = getelementptr { i64, i8 }, { i64, i8 }* %test.coerce, i32 0, i32 0
+  %3 = load i64, i64* %2, align 1
+  %4 = getelementptr { i64, i8 }, { i64, i8 }* %test.coerce, i32 0, i32 1
+  %5 = load i8, i8* %4, align 1
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i64 %3, i8 %5)
   ret i32 %call
 }
 
@@ -3409,8 +3409,8 @@ entry:
   %test = alloca i8*, align 8
   %0 = alloca i8, i64 4
   store i8* %0, i8** %test, align 8
-  %1 = load i8** %test, align 8
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %1)
+  %1 = load i8*, i8** %test, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %1)
   ret i32 %call
 }
 
@@ -3437,8 +3437,8 @@ entry:
   %test = alloca i8*, align 8
   %0 = alloca i8, i64 5
   store i8* %0, i8** %test, align 8
-  %1 = load i8** %test, align 8
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %1)
+  %1 = load i8*, i8** %test, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %1)
   ret i32 %call
 }
 
diff --git a/test/CodeGen/X86/stack-update-frame-opcode.ll b/test/CodeGen/X86/stack-update-frame-opcode.ll
index 9a5a2421233d..943e86e10d3a 100644
--- a/test/CodeGen/X86/stack-update-frame-opcode.ll
+++ b/test/CodeGen/X86/stack-update-frame-opcode.ll
@@ -16,7 +16,7 @@ entry:
 ; ATOM_LP64: leaq -1608
 ; ATOM_ILP32: leal -1608
 
-  %arraydecay = getelementptr inbounds [400 x i32]* %arr, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [400 x i32], [400 x i32]* %arr, i64 0, i64 0
   %call = call i32 @foo(i32 %a, i32* %arraydecay) nounwind
   ret i32 %call
 
diff --git a/test/CodeGen/X86/stack_guard_remat.ll b/test/CodeGen/X86/stack_guard_remat.ll
index dd639a7c7b4c..90ac2cc601fa 100644
--- a/test/CodeGen/X86/stack_guard_remat.ll
+++ b/test/CodeGen/X86/stack_guard_remat.ll
@@ -10,7 +10,7 @@ entry:
   %a1 = alloca [256 x i32], align 16
   %0 = bitcast [256 x i32]* %a1 to i8*
   call void @llvm.lifetime.start(i64 1024, i8* %0)
-  %arraydecay = getelementptr inbounds [256 x i32]* %a1, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [256 x i32], [256 x i32]* %a1, i64 0, i64 0
   call void @foo3(i32* %arraydecay)
   call void asm sideeffect "foo2", "~{r12},~{r13},~{r14},~{r15},~{ebx},~{esi},~{edi},~{dirflag},~{fpsr},~{flags}"()
   call void @llvm.lifetime.end(i64 1024, i8* %0)
diff --git a/test/CodeGen/X86/stackmap-fast-isel.ll b/test/CodeGen/X86/stackmap-fast-isel.ll
index dfb16adaa339..1392e5bd87c1 100644
--- a/test/CodeGen/X86/stackmap-fast-isel.ll
+++ b/test/CodeGen/X86/stackmap-fast-isel.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7                             | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; CHECK-LABEL:  .section  __LLVM_STACKMAPS,__llvm_stackmaps
 ; CHECK-NEXT:  __LLVM_StackMaps:
@@ -99,7 +99,7 @@
 
 define void @constantargs() {
 entry:
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 1, i32 15, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 1, i32 15, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1)
   ret void
 }
 
@@ -116,7 +116,7 @@ entry:
 ; CHECK-NEXT:   .long   33
 
 define void @liveConstant() {
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 15, i32 5, i32 33)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 15, i32 5, i32 33)
   ret void
 }
 
@@ -139,7 +139,7 @@ entry:
   store i64 11, i64* %metadata1
   store i64 12, i64* %metadata1
   store i64 13, i64* %metadata1
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 16, i32 0, i64* %metadata1)
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 0, i64* %metadata1)
   ret void
 }
 
@@ -155,10 +155,10 @@ entry:
 ; CHECK-LABEL:  .long L{{.*}}-_longid
 define void @longid() {
 entry:
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 4294967295, i32 0)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 4294967296, i32 0)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 9223372036854775807, i32 0)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 -1, i32 0)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4294967295, i32 0)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4294967296, i32 0)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 9223372036854775807, i32 0)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 -1, i32 0)
   ret void
 }
 
diff --git a/test/CodeGen/X86/stackmap-large-constants.ll b/test/CodeGen/X86/stackmap-large-constants.ll
index 73ee4f3d1569..a38b9209a1cf 100644
--- a/test/CodeGen/X86/stackmap-large-constants.ll
+++ b/test/CodeGen/X86/stackmap-large-constants.ll
@@ -51,7 +51,7 @@
 declare void @llvm.experimental.stackmap(i64, i32, ...)
 
 define void @foo() {
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 0, i32 0, i64 9223372036854775807)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 0, i32 0, i64 9223372036854775807)
   ret void
 }
 
@@ -78,6 +78,6 @@ define void @foo() {
 
 
 define void @bar() {
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 0, i32 0, i64 -9223372036854775808)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 0, i32 0, i64 -9223372036854775808)
   ret void
 }
diff --git a/test/CodeGen/X86/stackmap-liveness.ll b/test/CodeGen/X86/stackmap-liveness.ll
index 31553c0b6842..599b6265abfa 100644
--- a/test/CodeGen/X86/stackmap-liveness.ll
+++ b/test/CodeGen/X86/stackmap-liveness.ll
@@ -50,7 +50,7 @@ entry:
 ; PATCH-NEXT:   .byte 16
 ; Align
 ; PATCH-NEXT:   .align  3
-  call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 1, i32 12, i8* null, i32 0)
+  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 12, i8* null, i32 0)
   %a2 = call i64 asm sideeffect "", "={r8}"() nounwind
   %a3 = call i8 asm sideeffect "", "={ah}"() nounwind
   %a4 = call <4 x double> asm sideeffect "", "={ymm0}"() nounwind
@@ -97,7 +97,7 @@ entry:
 ; PATCH-NEXT:   .byte 16
 ; Align
 ; PATCH-NEXT:   .align  3
-  call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 2, i32 12, i8* null, i32 0)
+  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 2, i32 12, i8* null, i32 0)
   call void asm sideeffect "", "{r8},{ah},{ymm0},{ymm1}"(i64 %a2, i8 %a3, <4 x double> %a4, <4 x double> %a5) nounwind
 
 ; StackMap 3 (no liveness information available)
@@ -129,7 +129,7 @@ entry:
 ; PATCH-NEXT:   .byte 16
 ; Align
 ; PATCH-NEXT:   .align  3
-  call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 3, i32 12, i8* null, i32 0)
+  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 12, i8* null, i32 0)
   call void asm sideeffect "", "{xmm2}"(<2 x double> %a1) nounwind
   ret void
 }
@@ -166,8 +166,8 @@ entry:
 ; PATCH-NEXT:   .byte 16
 ; Align
 ; PATCH-NEXT:   .align  3
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 4, i32 5)
-  call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 5, i32 0, i8* null, i32 0)
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 5)
+  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 5, i32 0, i8* null, i32 0)
   call void asm sideeffect "", "{xmm2}"(<2 x double> %a1) nounwind
   ret void
 }
diff --git a/test/CodeGen/X86/stackmap-nops.ll b/test/CodeGen/X86/stackmap-nops.ll
index 7932c0dfb99d..08fee2ecd3e0 100644
--- a/test/CodeGen/X86/stackmap-nops.ll
+++ b/test/CodeGen/X86/stackmap-nops.ll
@@ -193,41 +193,41 @@ entry:
 ; CHECK-NEXT: .byte 102
 ; CHECK-NEXT: .byte 102
 ; CHECK-NEXT: nopw %cs:512(%rax,%rax)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  0, i32  0)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  1, i32  1)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  2, i32  2)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  3, i32  3)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  4, i32  4)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  5, i32  5)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  6, i32  6)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  7, i32  7)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  8, i32  8)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  9, i32  9)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 10, i32 10)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 11, i32 11)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 12, i32 12)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 13, i32 13)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 14, i32 14)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 15, i32 15)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 16, i32 16)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 17, i32 17)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 18, i32 18)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 19, i32 19)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 20, i32 20)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 21, i32 21)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 22, i32 22)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 23, i32 23)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 24, i32 24)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 25, i32 25)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 26, i32 26)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 27, i32 27)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 28, i32 28)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 29, i32 29)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 30, i32 30)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  0, i32  0)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  1, i32  1)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  2, i32  2)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  3, i32  3)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  4, i32  4)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  5, i32  5)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  6, i32  6)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  7, i32  7)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  8, i32  8)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  9, i32  9)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 10, i32 10)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 11, i32 11)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 12)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 13, i32 13)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 14)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 15, i32 15)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 16)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 17, i32 17)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 18, i32 18)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 19, i32 19)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 20, i32 20)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 21, i32 21)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 22, i32 22)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 23, i32 23)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 24, i32 24)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 25, i32 25)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 26, i32 26)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 27, i32 27)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 28, i32 28)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 29, i32 29)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 30, i32 30)
 ; Add an extra stackmap with a zero-length shadow to thwart the shadow
 ; optimization. This will force all 15 bytes of the previous shadow to be
 ; padded with nops.
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 31, i32 0)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 31, i32 0)
   ret void
 }
 
diff --git a/test/CodeGen/X86/stackmap-shadow-optimization.ll b/test/CodeGen/X86/stackmap-shadow-optimization.ll
index a3725f2c5b72..001d8d9f5434 100644
--- a/test/CodeGen/X86/stackmap-shadow-optimization.ll
+++ b/test/CodeGen/X86/stackmap-shadow-optimization.ll
@@ -18,7 +18,7 @@ entry:
 ; CHECK:        callq   _bar
 ; CHECK-NOT:    nop
   call void @bar()
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 0, i32 8)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 0, i32 8)
   call void @bar()
   call void @bar()
   ret void
diff --git a/test/CodeGen/X86/stackmap.ll b/test/CodeGen/X86/stackmap.ll
index 5e356f3e03d1..0805e8147044 100644
--- a/test/CodeGen/X86/stackmap.ll
+++ b/test/CodeGen/X86/stackmap.ll
@@ -125,7 +125,7 @@
 define void @constantargs() {
 entry:
   %0 = inttoptr i64 12345 to i8*
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 1, i32 15, i8* %0, i32 0, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 15, i8* %0, i32 0, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1)
   ret void
 }
 
@@ -147,7 +147,7 @@ entry:
   ; Runtime void->void call.
   call void inttoptr (i64 -559038737 to void ()*)()
   ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
   ret void
 }
 
@@ -173,7 +173,7 @@ entry:
 cold:
   ; OSR patchpoint with 12-byte nop-slide and 2 live vars.
   %thunk = inttoptr i64 -559038737 to i8*
-  call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 4, i32 15, i8* %thunk, i32 0, i64 %a, i64 %b)
+  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 15, i8* %thunk, i32 0, i64 %a, i64 %b)
   unreachable
 ret:
   ret void
@@ -194,7 +194,7 @@ ret:
 define i64 @propertyRead(i64* %obj) {
 entry:
   %resolveRead = inttoptr i64 -559038737 to i8*
-  %result = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %resolveRead, i32 1, i64* %obj)
+  %result = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %resolveRead, i32 1, i64* %obj)
   %add = add i64 %result, 3
   ret i64 %add
 }
@@ -214,7 +214,7 @@ entry:
 define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
 entry:
   %resolveWrite = inttoptr i64 -559038737 to i8*
-  call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 6, i32 15, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
+  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 15, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
   ret void
 }
 
@@ -236,7 +236,7 @@ entry:
 define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
   %resolveCall = inttoptr i64 -559038737 to i8*
-  call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 7, i32 15, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
+  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 15, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
   ret void
 }
 
@@ -258,7 +258,7 @@ entry:
 define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
   %resolveCall = inttoptr i64 -559038737 to i8*
-  %result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 8, i32 15, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
+  %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 15, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
   %add = add i64 %result, 3
   ret i64 %add
 }
@@ -278,7 +278,7 @@ entry:
 ; CHECK-NEXT:   .short 6
 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) {
 entry:
-  call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 11, i32 15, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
+  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 15, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
   ret void
 }
 
@@ -297,7 +297,7 @@ entry:
 ; CHECK-NEXT:   .short 6
 define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) {
 entry:
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 12, i32 15, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 15, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
   ret void
 }
 
@@ -321,7 +321,7 @@ bb1:
   unreachable
 
 bb2:
-  %tmp = load i64* inttoptr (i64 140685446136880 to i64*)
+  %tmp = load i64, i64* inttoptr (i64 140685446136880 to i64*)
   br i1 undef, label %bb16, label %bb17
 
 bb16:
@@ -333,7 +333,7 @@ bb17:
 
 bb60:
   tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 13, i32 5, i32 %tmp32)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 13, i32 5, i32 %tmp32)
   unreachable
 
 bb61:
@@ -367,7 +367,7 @@ define void @subRegOffset(i16 %arg) {
   %arghi = lshr i16 %v, 8
   %a1 = trunc i16 %arghi to i8
   tail call void asm sideeffect "nop", "~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 14, i32 5, i8 %a0, i8 %a1)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 5, i8 %a0, i8 %a1)
   ret void
 }
 
@@ -384,7 +384,7 @@ define void @subRegOffset(i16 %arg) {
 ; CHECK-NEXT:   .long   33
 
 define void @liveConstant() {
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 15, i32 5, i32 33)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 15, i32 5, i32 33)
   ret void
 }
 
@@ -422,10 +422,10 @@ entry:
   store i64 11, i64* %metadata1
   store i64 12, i64* %metadata1
   store i64 13, i64* %metadata1
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 16, i32 0, i64* %metadata1)
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 0, i64* %metadata1)
   %metadata2 = alloca i8, i32 4, align 8
   %metadata3 = alloca i16, i32 4, align 8
-  call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 17, i32 5, i8* null, i32 0, i8* %metadata2, i16* %metadata3)
+  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 17, i32 5, i8* null, i32 0, i8* %metadata2, i16* %metadata3)
   ret void
 }
 
@@ -441,10 +441,10 @@ entry:
 ; CHECK-LABEL:  .long L{{.*}}-_longid
 define void @longid() {
 entry:
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 4294967295, i32 0, i8* null, i32 0)
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 4294967296, i32 0, i8* null, i32 0)
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 9223372036854775807, i32 0, i8* null, i32 0)
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 -1, i32 0, i8* null, i32 0)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4294967295, i32 0, i8* null, i32 0)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4294967296, i32 0, i8* null, i32 0)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 9223372036854775807, i32 0, i8* null, i32 0)
+  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 -1, i32 0, i8* null, i32 0)
   ret void
 }
 
@@ -462,7 +462,7 @@ entry:
 ; CHECK-NEXT:   .long   -{{[0-9]+}}
 define void @clobberScratch(i32 %a) {
   tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r12},~{r13},~{r14},~{r15}"() nounwind
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 16, i32 8, i32 %a)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 8, i32 %a)
   ret void
 }
 
@@ -474,11 +474,11 @@ define void @clobberScratch(i32 %a) {
 ; CHECK-NEXT:   .short 0
 define void @needsStackRealignment() {
   %val = alloca i64, i32 3, align 128
-  tail call void (...)* @escape_values(i64* %val)
+  tail call void (...) @escape_values(i64* %val)
 ; Note: Adding any non-constant to the stackmap would fail because we
 ; expected to be able to address off the frame pointer.  In a realigned
 ; frame, we must use the stack pointer instead.  This is a separate bug.
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 0, i32 0)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 0, i32 0)
   ret void
 }
 declare void @escape_values(...)
diff --git a/test/CodeGen/X86/statepoint-allocas.ll b/test/CodeGen/X86/statepoint-allocas.ll
new file mode 100644
index 000000000000..4af33e1f5478
--- /dev/null
+++ b/test/CodeGen/X86/statepoint-allocas.ll
@@ -0,0 +1,130 @@
+; RUN: llc < %s | FileCheck %s
+; Check that we can lower a use of an alloca both as a deopt value (where the
+; exact meaning is up to the consumer of the stackmap) and as an explicit spill
+; slot used for GC.  
+
+target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnu"
+
+declare zeroext i1 @return_i1()
+
+; Can we handle an explicit relocation slot (in the form of an alloca) given 
+; to the statepoint?
+define i32 addrspace(1)* @test(i32 addrspace(1)* %ptr) gc "statepoint-example" {
+; CHECK-LABEL: test
+; CHECK: pushq  %rax
+; CHECK: movq   %rdi, (%rsp)
+; CHECK: callq return_i1
+; CHECK: movq   (%rsp), %rax
+; CHECK: popq   %rdx
+; CHECK: retq
+entry:
+  %alloca = alloca i32 addrspace(1)*, align 8
+  store i32 addrspace(1)* %ptr, i32 addrspace(1)** %alloca
+  call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, i32 addrspace(1)** %alloca)
+  %rel = load i32 addrspace(1)*, i32 addrspace(1)** %alloca
+  ret i32 addrspace(1)* %rel
+}
+
+; Can we handle an alloca as a deopt value?  
+define i32 addrspace(1)* @test2(i32 addrspace(1)* %ptr) gc "statepoint-example" {
+; CHECK-LABEL: test2
+; CHECK: pushq  %rax
+; CHECK: movq   %rdi, (%rsp)
+; CHECK: callq return_i1
+; CHECK: xorl   %eax, %eax
+; CHECK: popq   %rdx
+; CHECK: retq
+entry:
+  %alloca = alloca i32 addrspace(1)*, align 8
+  store i32 addrspace(1)* %ptr, i32 addrspace(1)** %alloca
+  call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 1, i32 addrspace(1)** %alloca)
+  ret i32 addrspace(1)* null
+}
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i32, ...)
+
+
+; CHECK-LABEL: .section .llvm_stackmaps
+; CHECK-NEXT:  __LLVM_StackMaps:
+; Header
+; CHECK-NEXT:   .byte 1
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 0
+; Num Functions
+; CHECK-NEXT:   .long 2
+; Num LargeConstants
+; CHECK-NEXT:   .long 0
+; Num Callsites
+; CHECK-NEXT:   .long 2
+
+; Functions and stack size
+; CHECK-NEXT:   .quad test
+; CHECK-NEXT:   .quad 8
+; CHECK-NEXT:   .quad test2
+; CHECK-NEXT:   .quad 8
+
+; Large Constants
+; Statepoint ID only
+; CHECK: .quad	0
+
+; Callsites
+; The GC one
+; CHECK: .long	.Ltmp1-test
+; CHECK: .short	0
+; CHECK: .short	4
+; SmallConstant (0)
+; CHECK: .byte	4
+; CHECK: .byte	8
+; CHECK: .short	0
+; CHECK: .long	0
+; SmallConstant (0)
+; CHECK: .byte	4
+; CHECK: .byte	8
+; CHECK: .short	0
+; CHECK: .long	0
+; SmallConstant (0)
+; CHECK: .byte	4
+; CHECK: .byte	8
+; CHECK: .short	0
+; CHECK: .long	0
+; Direct Spill Slot [RSP+0]
+; CHECK: .byte	2
+; CHECK: .byte	8
+; CHECK: .short	7
+; CHECK: .long	0
+; No Padding or LiveOuts
+; CHECK: .short	0
+; CHECK: .short	0
+; CHECK: .align	8
+
+; The Deopt one
+; CHECK: .long	.Ltmp3-test2
+; CHECK: .short	0
+; CHECK: .short	4
+; SmallConstant (0)
+; CHECK: .byte	4
+; CHECK: .byte	8
+; CHECK: .short	0
+; CHECK: .long	0
+; SmallConstant (0)
+; CHECK: .byte	4
+; CHECK: .byte	8
+; CHECK: .short	0
+; CHECK: .long	0
+; SmallConstant (1)
+; CHECK: .byte	4
+; CHECK: .byte	8
+; CHECK: .short	0
+; CHECK: .long	1
+; Direct Spill Slot [RSP+0]
+; CHECK: .byte	2
+; CHECK: .byte	8
+; CHECK: .short	7
+; CHECK: .long	0
+
+; No Padding or LiveOuts
+; CHECK: .short	0
+; CHECK: .short	0
+; CHECK: .align	8
+
diff --git a/test/CodeGen/X86/statepoint-call-lowering.ll b/test/CodeGen/X86/statepoint-call-lowering.ll
index e7a0dcab9ab7..8f352b7728c3 100644
--- a/test/CodeGen/X86/statepoint-call-lowering.ll
+++ b/test/CodeGen/X86/statepoint-call-lowering.ll
@@ -9,8 +9,9 @@ declare zeroext i1 @return_i1()
 declare zeroext i32 @return_i32()
 declare i32* @return_i32ptr()
 declare float @return_float()
+declare void @varargf(i32, ...)
 
-define i1 @test_i1_return() {
+define i1 @test_i1_return() gc "statepoint-example" {
 ; CHECK-LABEL: test_i1_return
 ; This is just checking that a i1 gets lowered normally when there's no extra
 ; state arguments to the statepoint
@@ -19,72 +20,98 @@ define i1 @test_i1_return() {
 ; CHECK: popq %rdx
 ; CHECK: retq
 entry:
-  %safepoint_token = tail call i32 (i1 ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_i1f(i1 ()* @return_i1, i32 0, i32 0, i32 0)
-  %call1 = call zeroext i1 @llvm.experimental.gc.result.int.i1(i32 %safepoint_token)
+  %safepoint_token = tail call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0)
+  %call1 = call zeroext i1 @llvm.experimental.gc.result.i1(i32 %safepoint_token)
   ret i1 %call1
 }
 
-define i32 @test_i32_return() {
+define i32 @test_i32_return() gc "statepoint-example" {
 ; CHECK-LABEL: test_i32_return
 ; CHECK: pushq %rax
 ; CHECK: callq return_i32
 ; CHECK: popq %rdx
 ; CHECK: retq
 entry:
-  %safepoint_token = tail call i32 (i32 ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_i32f(i32 ()* @return_i32, i32 0, i32 0, i32 0)
-  %call1 = call zeroext i32 @llvm.experimental.gc.result.int.i32(i32 %safepoint_token)
+  %safepoint_token = tail call i32 (i64, i32, i32 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i32f(i64 0, i32 0, i32 ()* @return_i32, i32 0, i32 0, i32 0, i32 0)
+  %call1 = call zeroext i32 @llvm.experimental.gc.result.i32(i32 %safepoint_token)
   ret i32 %call1
 }
 
-define i32* @test_i32ptr_return() {
+define i32* @test_i32ptr_return() gc "statepoint-example" {
 ; CHECK-LABEL: test_i32ptr_return
 ; CHECK: pushq %rax
 ; CHECK: callq return_i32ptr
 ; CHECK: popq %rdx
 ; CHECK: retq
 entry:
-  %safepoint_token = tail call i32 (i32* ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_p0i32f(i32* ()* @return_i32ptr, i32 0, i32 0, i32 0)
-  %call1 = call i32* @llvm.experimental.gc.result.ptr.p0i32(i32 %safepoint_token)
+  %safepoint_token = tail call i32 (i64, i32, i32* ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_p0i32f(i64 0, i32 0, i32* ()* @return_i32ptr, i32 0, i32 0, i32 0, i32 0)
+  %call1 = call i32* @llvm.experimental.gc.result.p0i32(i32 %safepoint_token)
   ret i32* %call1
 }
 
-define float @test_float_return() {
+define float @test_float_return() gc "statepoint-example" {
 ; CHECK-LABEL: test_float_return
 ; CHECK: pushq %rax
 ; CHECK: callq return_float
 ; CHECK: popq %rax
 ; CHECK: retq
 entry:
-  %safepoint_token = tail call i32 (float ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_f32f(float ()* @return_float, i32 0, i32 0, i32 0)
-  %call1 = call float @llvm.experimental.gc.result.float.f32(i32 %safepoint_token)
+  %safepoint_token = tail call i32 (i64, i32, float ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_f32f(i64 0, i32 0, float ()* @return_float, i32 0, i32 0, i32 0, i32 0)
+  %call1 = call float @llvm.experimental.gc.result.f32(i32 %safepoint_token)
   ret float %call1
 }
 
-define i1 @test_relocate(i32* %a) {
+define i1 @test_relocate(i32 addrspace(1)* %a) gc "statepoint-example" {
 ; CHECK-LABEL: test_relocate
 ; Check that an ununsed relocate has no code-generation impact
 ; CHECK: pushq %rax
 ; CHECK: callq return_i1
-; CHECK-NEXT: .Ltmp13:
+; CHECK-NEXT: .Ltmp9:
 ; CHECK-NEXT: popq %rdx
 ; CHECK-NEXT: retq
 entry:
-  %safepoint_token = tail call i32 (i1 ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_i1f(i1 ()* @return_i1, i32 0, i32 0, i32 0, i32* %a)
-  %call1 = call i32* @llvm.experimental.gc.relocate.p0i32(i32 %safepoint_token, i32 4, i32 4)
-  %call2 = call zeroext i1 @llvm.experimental.gc.result.int.i1(i32 %safepoint_token)
+  %safepoint_token = tail call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, i32 addrspace(1)* %a)
+  %call1 = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token,  i32 7, i32 7)
+  %call2 = call zeroext i1 @llvm.experimental.gc.result.i1(i32 %safepoint_token)
   ret i1 %call2
 }
 
-declare i32 @llvm.experimental.gc.statepoint.p0f_i1f(i1 ()*, i32, i32, ...)
-declare i1 @llvm.experimental.gc.result.int.i1(i32)
+define void @test_void_vararg() gc "statepoint-example" {
+; CHECK-LABEL: test_void_vararg
+; Check a statepoint wrapping a *void* returning vararg function works
+; CHECK: callq varargf
+entry:
+  %safepoint_token = tail call i32 (i64, i32, void (i32, ...)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi32varargf(i64 0, i32 0, void (i32, ...)* @varargf, i32 2, i32 0, i32 42, i32 43, i32 0, i32 0)
+  ;; if we try to use the result from a statepoint wrapping a
+  ;; non-void-returning varargf, we will experience a crash.
+  ret void
+}
+
+define i1 @test_i1_return_patchable() gc "statepoint-example" {
+; CHECK-LABEL: test_i1_return_patchable
+; A patchable variant of test_i1_return
+; CHECK: pushq %rax
+; CHECK: nopl
+; CHECK: popq %rdx
+; CHECK: retq
+entry:
+  %safepoint_token = tail call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 3, i1 ()*null, i32 0, i32 0, i32 0, i32 0)
+  %call1 = call zeroext i1 @llvm.experimental.gc.result.i1(i32 %safepoint_token)
+  ret i1 %call1
+}
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i32, ...)
+declare i1 @llvm.experimental.gc.result.i1(i32)
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_i32f(i64, i32, i32 ()*, i32, i32, ...)
+declare i32 @llvm.experimental.gc.result.i32(i32)
 
-declare i32 @llvm.experimental.gc.statepoint.p0f_i32f(i32 ()*, i32, i32, ...)
-declare i32 @llvm.experimental.gc.result.int.i32(i32)
+declare i32 @llvm.experimental.gc.statepoint.p0f_p0i32f(i64, i32, i32* ()*, i32, i32, ...)
+declare i32* @llvm.experimental.gc.result.p0i32(i32)
 
-declare i32 @llvm.experimental.gc.statepoint.p0f_p0i32f(i32* ()*, i32, i32, ...)
-declare i32* @llvm.experimental.gc.result.ptr.p0i32(i32)
+declare i32 @llvm.experimental.gc.statepoint.p0f_f32f(i64, i32, float ()*, i32, i32, ...)
+declare float @llvm.experimental.gc.result.f32(i32)
 
-declare i32 @llvm.experimental.gc.statepoint.p0f_f32f(float ()*, i32, i32, ...)
-declare float @llvm.experimental.gc.result.float.f32(i32)
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidi32varargf(i64, i32, void (i32, ...)*, i32, i32, ...)
 
-declare i32* @llvm.experimental.gc.relocate.p0i32(i32, i32, i32)
+declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32, i32, i32)
diff --git a/test/CodeGen/X86/statepoint-forward.ll b/test/CodeGen/X86/statepoint-forward.ll
index 12a6ac2c72a9..698229e705f4 100644
--- a/test/CodeGen/X86/statepoint-forward.ll
+++ b/test/CodeGen/X86/statepoint-forward.ll
@@ -22,12 +22,12 @@ declare void @func() readonly
 ;; be valid, but is not currently implemented.
 define i1 @test_load_forward(i32 addrspace(1)* addrspace(1)* %p) gc "statepoint-example" {
 entry:
-  %before = load i32 addrspace(1)* addrspace(1)* %p
+  %before = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* %p
   %cmp1 = call i1 @f(i32 addrspace(1)* %before)
   call void @llvm.assume(i1 %cmp1)
-  %safepoint_token = tail call i32 (void ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_isVoidf(void ()* @func, i32 0, i32 0, i32 0, i32 addrspace(1)* addrspace(1)* %p)
-  %pnew = call i32 addrspace(1)* addrspace(1)* @llvm.experimental.gc.relocate.p1p1i32(i32 %safepoint_token, i32 4, i32 4)
-  %after = load i32 addrspace(1)* addrspace(1)* %pnew
+  %safepoint_token = tail call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @func, i32 0, i32 0, i32 0, i32 0, i32 addrspace(1)* addrspace(1)* %p)
+  %pnew = call i32 addrspace(1)* addrspace(1)* @llvm.experimental.gc.relocate.p1p1i32(i32 %safepoint_token,  i32 7, i32 7)
+  %after = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* %pnew
   %cmp2 = call i1 @f(i32 addrspace(1)* %after)
   ret i1 %cmp2
 
@@ -44,9 +44,9 @@ entry:
   %cmp1 = call i1 @f(i32 addrspace(1)* %v)
   call void @llvm.assume(i1 %cmp1)
   store i32 addrspace(1)* %v, i32 addrspace(1)* addrspace(1)* %p
-  %safepoint_token = tail call i32 (void ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_isVoidf(void ()* @func, i32 0, i32 0, i32 0, i32 addrspace(1)* addrspace(1)* %p)
-  %pnew = call i32 addrspace(1)* addrspace(1)* @llvm.experimental.gc.relocate.p1p1i32(i32 %safepoint_token, i32 4, i32 4)
-  %after = load i32 addrspace(1)* addrspace(1)* %pnew
+  %safepoint_token = tail call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @func, i32 0, i32 0, i32 0, i32 0, i32 addrspace(1)* addrspace(1)* %p)
+  %pnew = call i32 addrspace(1)* addrspace(1)* @llvm.experimental.gc.relocate.p1p1i32(i32 %safepoint_token,  i32 7, i32 7)
+  %after = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* %pnew
   %cmp2 = call i1 @f(i32 addrspace(1)* %after)
   ret i1 %cmp2
 
@@ -69,11 +69,11 @@ declare i1 @f(i32 addrspace(1)* %v) readnone
 ; statepoint does not provide the collector with this root.
 define i1 @test_load_forward_nongc_heap(i32 addrspace(1)** %p) gc "statepoint-example" {
 entry:
-  %before = load i32 addrspace(1)** %p
+  %before = load i32 addrspace(1)*, i32 addrspace(1)** %p
   %cmp1 = call i1 @f(i32 addrspace(1)* %before)
   call void @llvm.assume(i1 %cmp1)
-  call i32 (void ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_isVoidf(void ()* @func, i32 0, i32 0, i32 0)
-  %after = load i32 addrspace(1)** %p
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @func, i32 0, i32 0, i32 0, i32 0)
+  %after = load i32 addrspace(1)*, i32 addrspace(1)** %p
   %cmp2 = call i1 @f(i32 addrspace(1)* %after)
   ret i1 %cmp2
 
@@ -90,8 +90,8 @@ entry:
   %cmp1 = call i1 @f(i32 addrspace(1)* %v)
   call void @llvm.assume(i1 %cmp1)
   store i32 addrspace(1)* %v, i32 addrspace(1)** %p
-  call i32 (void ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_isVoidf(void ()* @func, i32 0, i32 0, i32 0)
-  %after = load i32 addrspace(1)** %p
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @func, i32 0, i32 0, i32 0, i32 0)
+  %after = load i32 addrspace(1)*, i32 addrspace(1)** %p
   %cmp2 = call i1 @f(i32 addrspace(1)* %after)
   ret i1 %cmp2
 
@@ -102,6 +102,5 @@ entry:
 }
 
 declare void @llvm.assume(i1)
-declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(void ()*, i32, i32, ...)
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
 declare i32 addrspace(1)* addrspace(1)* @llvm.experimental.gc.relocate.p1p1i32(i32, i32, i32) #3
-
diff --git a/test/CodeGen/X86/statepoint-gctransition-call-lowering.ll b/test/CodeGen/X86/statepoint-gctransition-call-lowering.ll
new file mode 100644
index 000000000000..61b8ded2c472
--- /dev/null
+++ b/test/CodeGen/X86/statepoint-gctransition-call-lowering.ll
@@ -0,0 +1,133 @@
+; RUN: llc < %s | FileCheck %s
+; This file contains a collection of basic tests to ensure we didn't
+; screw up normal call lowering when a statepoint is a GC transition.
+
+target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnu"
+
+declare zeroext i1 @return_i1()
+declare zeroext i32 @return_i32()
+declare zeroext i32 @return_i32_with_args(i32, i8*)
+declare i32* @return_i32ptr()
+declare float @return_float()
+declare void @varargf(i32, ...)
+
+define i1 @test_i1_return() gc "statepoint-example" {
+; CHECK-LABEL: test_i1_return
+; This is just checking that a i1 gets lowered normally when there's no extra
+; state arguments to the statepoint
+; CHECK: pushq %rax
+; CHECK: callq return_i1
+; CHECK: popq %rdx
+; CHECK: retq
+entry:
+  %safepoint_token = tail call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 1, i32 0, i32 0)
+  %call1 = call zeroext i1 @llvm.experimental.gc.result.i1(i32 %safepoint_token)
+  ret i1 %call1
+}
+
+define i32 @test_i32_return() gc "statepoint-example" {
+; CHECK-LABEL: test_i32_return
+; CHECK: pushq %rax
+; CHECK: callq return_i32
+; CHECK: popq %rdx
+; CHECK: retq
+entry:
+  %safepoint_token = tail call i32 (i64, i32, i32 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i32f(i64 0, i32 0, i32 ()* @return_i32, i32 0, i32 1, i32 0, i32 0)
+  %call1 = call zeroext i32 @llvm.experimental.gc.result.i32(i32 %safepoint_token)
+  ret i32 %call1
+}
+
+define i32* @test_i32ptr_return() gc "statepoint-example" {
+; CHECK-LABEL: test_i32ptr_return
+; CHECK: pushq %rax
+; CHECK: callq return_i32ptr
+; CHECK: popq %rdx
+; CHECK: retq
+entry:
+  %safepoint_token = tail call i32 (i64, i32, i32* ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_p0i32f(i64 0, i32 0, i32* ()* @return_i32ptr, i32 0, i32 1, i32 0, i32 0)
+  %call1 = call i32* @llvm.experimental.gc.result.p0i32(i32 %safepoint_token)
+  ret i32* %call1
+}
+
+define float @test_float_return() gc "statepoint-example" {
+; CHECK-LABEL: test_float_return
+; CHECK: pushq %rax
+; CHECK: callq return_float
+; CHECK: popq %rax
+; CHECK: retq
+entry:
+  %safepoint_token = tail call i32 (i64, i32, float ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_f32f(i64 0, i32 0, float ()* @return_float, i32 0, i32 1, i32 0, i32 0)
+  %call1 = call float @llvm.experimental.gc.result.f32(i32 %safepoint_token)
+  ret float %call1
+}
+
+define i1 @test_relocate(i32 addrspace(1)* %a) gc "statepoint-example" {
+; CHECK-LABEL: test_relocate
+; Check that an ununsed relocate has no code-generation impact
+; CHECK: pushq %rax
+; CHECK: callq return_i1
+; CHECK-NEXT: .Ltmp9:
+; CHECK-NEXT: popq %rdx
+; CHECK-NEXT: retq
+entry:
+  %safepoint_token = tail call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 1, i32 0, i32 0, i32 addrspace(1)* %a)
+  %call1 = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 7, i32 7)
+  %call2 = call zeroext i1 @llvm.experimental.gc.result.i1(i32 %safepoint_token)
+  ret i1 %call2
+}
+
+define void @test_void_vararg() gc "statepoint-example" {
+; CHECK-LABEL: test_void_vararg
+; Check a statepoint wrapping a *void* returning vararg function works
+; CHECK: callq varargf
+entry:
+  %safepoint_token = tail call i32 (i64, i32, void (i32, ...)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi32varargf(i64 0, i32 0, void (i32, ...)* @varargf, i32 2, i32 1, i32 42, i32 43, i32 0, i32 0)
+  ;; if we try to use the result from a statepoint wrapping a
+  ;; non-void-returning varargf, we will experience a crash.
+  ret void
+}
+
+define i32 @test_transition_args() gc "statepoint-example" {
+; CHECK-LABEL: test_transition_args
+; CHECK: pushq %rax
+; CHECK: callq return_i32
+; CHECK: popq %rdx
+; CHECK: retq
+entry:
+  %val = alloca i32
+  %safepoint_token = call i32 (i64, i32, i32 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i32f(i64 0, i32 0, i32 ()* @return_i32, i32 0, i32 1, i32 2, i32* %val, i64 42, i32 0)
+  %call1 = call i32 @llvm.experimental.gc.result.i32(i32 %safepoint_token)
+  ret i32 %call1
+}
+
+define i32 @test_transition_args_2() gc "statepoint-example" {
+; CHECK-LABEL: test_transition_args_2
+; CHECK: pushq %rax
+; CHECK: callq return_i32
+; CHECK: popq %rdx
+; CHECK: retq
+entry:
+  %val = alloca i32
+  %arg = alloca i8
+  %safepoint_token = call i32 (i64, i32, i32 (i32, i8*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i32i32p0i8f(i64 0, i32 0, i32 (i32, i8*)* @return_i32_with_args, i32 2, i32 1, i32 0, i8* %arg, i32 2, i32* %val, i64 42, i32 0)
+  %call1 = call i32 @llvm.experimental.gc.result.i32(i32 %safepoint_token)
+  ret i32 %call1
+}
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i32, ...)
+declare i1 @llvm.experimental.gc.result.i1(i32)
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_i32f(i64, i32, i32 ()*, i32, i32, ...)
+declare i32 @llvm.experimental.gc.statepoint.p0f_i32i32p0i8f(i64, i32, i32 (i32, i8*)*, i32, i32, ...)
+declare i32 @llvm.experimental.gc.result.i32(i32)
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_p0i32f(i64, i32, i32* ()*, i32, i32, ...)
+declare i32* @llvm.experimental.gc.result.p0i32(i32)
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_f32f(i64, i32, float ()*, i32, i32, ...)
+declare float @llvm.experimental.gc.result.f32(i32)
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidi32varargf(i64, i32, void (i32, ...)*, i32, i32, ...)
+
+declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32, i32, i32)
\ No newline at end of file
diff --git a/test/CodeGen/X86/statepoint-invoke.ll b/test/CodeGen/X86/statepoint-invoke.ll
new file mode 100644
index 000000000000..df78978c117c
--- /dev/null
+++ b/test/CodeGen/X86/statepoint-invoke.ll
@@ -0,0 +1,198 @@
+; RUN: llc < %s 2>&1 | FileCheck %s
+
+target triple = "x86_64-pc-linux-gnu"
+
+declare void @"some_call"(i64 addrspace(1)*)
+declare i64 addrspace(1)* @"some_other_call"(i64 addrspace(1)*)
+
+declare i32 @"personality_function"()
+
+define i64 addrspace(1)* @test_basic(i64 addrspace(1)* %obj,
+                                     i64 addrspace(1)* %obj1)
+gc "statepoint-example" {
+entry:
+  ; CHECK: Ltmp{{[0-9]+}}:
+  ; CHECK: callq some_call
+  ; CHECK: Ltmp{{[0-9]+}}:
+  %0 = invoke i32 (i64, i32, void (i64 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidp1i64f(i64 0, i32 0, void (i64 addrspace(1)*)* @some_call, i32 1, i32 0, i64 addrspace(1)* %obj, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i64 addrspace(1)* %obj, i64 addrspace(1)* %obj1)
+          to label %invoke_safepoint_normal_dest unwind label %exceptional_return
+
+invoke_safepoint_normal_dest:
+  ; CHECK: movq
+  %obj.relocated = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %0, i32 13, i32 13)
+  %obj1.relocated = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %0, i32 14, i32 14)
+  br label %normal_return
+
+normal_return:
+  ; CHECK: retq
+  ret i64 addrspace(1)* %obj.relocated
+
+exceptional_return:
+  ; CHECK: Ltmp{{[0-9]+}}:
+  ; CHECK: movq
+  ; CHECK: retq
+  %landing_pad = landingpad { i8*, i32 } personality i32 ()* @"personality_function"
+          cleanup
+  %relocate_token = extractvalue { i8*, i32 } %landing_pad, 1
+  %obj.relocated1 = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %relocate_token, i32 13, i32 13)
+  %obj1.relocated1 = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %relocate_token, i32 14, i32 14)
+  ret i64 addrspace(1)* %obj1.relocated1
+}
+; CHECK-LABEL: GCC_except_table{{[0-9]+}}:
+; CHECK: .long  .Ltmp{{[0-9]+}}-.Ltmp{{[0-9]+}}
+; CHECK: .long  .Ltmp{{[0-9]+}}-.Lfunc_begin{{[0-9]+}}
+; CHECK: .byte  0
+; CHECK: .align 4
+
+define i64 addrspace(1)* @test_result(i64 addrspace(1)* %obj,
+                                      i64 addrspace(1)* %obj1)
+  gc "statepoint-example" {
+entry:
+  ; CHECK: .Ltmp{{[0-9]+}}:
+  ; CHECK: callq some_other_call
+  ; CHECK: .Ltmp{{[0-9]+}}:
+  %0 = invoke i32 (i64, i32, i64 addrspace(1)* (i64 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_p1i64p1i64f(i64 0, i32 0, i64 addrspace(1)* (i64 addrspace(1)*)* @some_other_call, i32 1, i32 0, i64 addrspace(1)* %obj, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i64 addrspace(1)* %obj, i64 addrspace(1)* %obj1)
+          to label %normal_return unwind label %exceptional_return
+
+normal_return:
+  ; CHECK: popq 
+  ; CHECK: retq
+  %ret_val = call i64 addrspace(1)* @llvm.experimental.gc.result.p1i64(i32 %0)
+  ret i64 addrspace(1)* %ret_val
+
+exceptional_return:
+  ; CHECK: .Ltmp{{[0-9]+}}:
+  ; CHECK: movq
+  %landing_pad = landingpad { i8*, i32 } personality i32 ()* @personality_function
+          cleanup
+  %relocate_token = extractvalue { i8*, i32 } %landing_pad, 1
+  %obj.relocated = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %relocate_token, i32 13, i32 13)
+  ret i64 addrspace(1)* %obj.relocated
+}
+; CHECK-LABEL: GCC_except_table{{[0-9]+}}:
+; CHECK: .long .Ltmp{{[0-9]+}}-.Ltmp{{[0-9]+}}
+; CHECK: .long .Ltmp{{[0-9]+}}-.Lfunc_begin{{[0-9]+}}
+; CHECK: .byte 0
+; CHECK: .align 4
+
+define i64 addrspace(1)* @test_same_val(i1 %cond, i64 addrspace(1)* %val1, i64 addrspace(1)* %val2, i64 addrspace(1)* %val3)
+  gc "statepoint-example" {
+entry:
+  br i1 %cond, label %left, label %right
+
+left:
+  ; CHECK-LABEL: %left
+  ; CHECK: movq %rdx, 8(%rsp)
+  ; CHECK: movq
+  ; CHECK: callq some_call
+  %sp1 = invoke i32 (i64, i32, void (i64 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidp1i64f(i64 0, i32 0, void (i64 addrspace(1)*)* @some_call, i32 1, i32 0, i64 addrspace(1)* %val1, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i64 addrspace(1)* %val1, i64 addrspace(1)* %val2)
+           to label %left.relocs unwind label %exceptional_return.left
+
+left.relocs:
+  ; CHECK: movq (%rsp),
+  ; CHECK: movq 8(%rsp), [[REGVAL2:%[a-z]+]]
+  %val1.relocated = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %sp1, i32 13, i32 13)
+  %val2.relocated_left = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %sp1, i32 14, i32 14)
+  br label %normal_return
+
+right:
+  ; CHECK-LABEL: %right
+  ; CHECK: movq
+  ; CHECK: movq %rdx, (%rsp)
+  ; CHECK: callq some_call
+  %sp2 = invoke i32 (i64, i32, void (i64 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidp1i64f(i64 0, i32 0, void (i64 addrspace(1)*)* @some_call, i32 1, i32 0, i64 addrspace(1)* %val1, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i64 addrspace(1)* %val2, i64 addrspace(1)* %val3)
+           to label %right.relocs unwind label %exceptional_return.right
+
+right.relocs:
+  ; CHECK: movq (%rsp), [[REGVAL2]]
+  ; CHECK: movq
+  %val2.relocated_right = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %sp2, i32 13, i32 13)
+  %val3.relocated = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %sp2, i32 14, i32 14)
+  br label %normal_return
+
+normal_return:
+  ; CHECK-LABEL: %normal_return
+  ; CHECK: cmoveq {{.*}}[[REGVAL2]]{{.*}}
+  ; CHECK retq
+  %a1 = phi i64 addrspace(1)* [%val1.relocated, %left.relocs], [%val3.relocated, %right.relocs]
+  %a2 = phi i64 addrspace(1)* [%val2.relocated_left, %left.relocs], [%val2.relocated_right, %right.relocs]
+  %ret = select i1 %cond, i64 addrspace(1)* %a1, i64 addrspace(1)* %a2
+  ret i64 addrspace(1)* %ret
+
+exceptional_return.left:
+  %landing_pad = landingpad { i8*, i32 } personality i32 ()* @"personality_function"
+          cleanup
+  %relocate_token = extractvalue { i8*, i32 } %landing_pad, 1
+  %val.relocated2 = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %relocate_token, i32 13, i32 13)
+  ret i64 addrspace(1)* %val.relocated2
+
+exceptional_return.right:
+  %landing_pad1 = landingpad { i8*, i32 } personality i32 ()* @"personality_function"
+          cleanup
+  %relocate_token1 = extractvalue { i8*, i32 } %landing_pad1, 1
+  %val.relocated3 = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %relocate_token1, i32 13, i32 13)
+  ret i64 addrspace(1)* %val.relocated3
+}
+
+define i64 addrspace(1)* @test_null_undef(i64 addrspace(1)* %val1)
+       gc "statepoint-example" {
+; CHECK-LABEL: test_null_undef:
+entry:
+  ; CHECK: callq some_call
+  %sp1 = invoke i32 (i64, i32, void (i64 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidp1i64f(i64 0, i32 0, void (i64 addrspace(1)*)* @some_call, i32 1, i32 0, i64 addrspace(1)* %val1, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i64 addrspace(1)* null, i64 addrspace(1)* undef)
+           to label %normal_return unwind label %exceptional_return
+
+normal_return:
+  ; CHECK-LABEL: %normal_return
+  ; CHECK: xorl %eax, %eax
+  ; CHECK-NEXT: popq
+  ; CHECK-NEXT: retq
+  %null.relocated = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %sp1, i32 13, i32 13)
+  %undef.relocated = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %sp1, i32 14, i32 14)
+  ret i64 addrspace(1)* %null.relocated
+
+exceptional_return:
+  %landing_pad = landingpad { i8*, i32 } personality i32 ()* @"personality_function"
+          cleanup
+  %relocate_token = extractvalue { i8*, i32 } %landing_pad, 1
+  %null.relocated2 = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %relocate_token, i32 13, i32 13)
+  %undef.relocated2 = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %relocate_token, i32 14, i32 14)
+  ret i64 addrspace(1)* %null.relocated2
+}
+
+define i64 addrspace(1)* @test_alloca_and_const(i64 addrspace(1)* %val1)
+       gc "statepoint-example" {
+; CHECK-LABEL: test_alloca_and_const:
+entry:
+  %a = alloca i32
+  %aa = addrspacecast i32* %a to i32 addrspace(1)*
+  %c = inttoptr i64 15 to i64 addrspace(1)*
+  ; CHECK: callq
+  %sp = invoke i32 (i64, i32, void (i64 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidp1i64f(i64 0, i32 0, void (i64 addrspace(1)*)* @some_call, i32 1, i32 0, i64 addrspace(1)* %val1, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i32 addrspace(1)* %aa, i64 addrspace(1)* %c)
+           to label %normal_return unwind label %exceptional_return
+
+normal_return:
+  ; CHECK: leaq
+  ; CHECK-NEXT: popq
+  ; CHECK-NEXT: retq
+  %aa.rel = call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %sp, i32 13, i32 13)
+  %aa.converted = bitcast i32 addrspace(1)* %aa.rel to i64 addrspace(1)*
+  ret i64 addrspace(1)* %aa.converted
+
+exceptional_return:
+  ; CHECK: movl	$15
+  ; CHECK-NEXT: popq
+  ; CHECK-NEXT: retq
+  %landing_pad = landingpad { i8*, i32 } personality i32 ()* @"personality_function"
+          cleanup
+  %relocate_token = extractvalue { i8*, i32 } %landing_pad, 1
+  %aa.rel2 = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %relocate_token, i32 14, i32 14)
+  ret i64 addrspace(1)* %aa.rel2
+}
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidp1i64f(i64, i32, void (i64 addrspace(1)*)*, i32, i32, ...)
+declare i32 @llvm.experimental.gc.statepoint.p0f_p1i64p1i64f(i64, i32, i64 addrspace(1)* (i64 addrspace(1)*)*, i32, i32, ...)
+
+declare i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32, i32, i32)
+declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32, i32, i32)
+declare i64 addrspace(1)* @llvm.experimental.gc.result.p1i64(i32)
diff --git a/test/CodeGen/X86/statepoint-stack-usage.ll b/test/CodeGen/X86/statepoint-stack-usage.ll
index fd24bf841688..02d20c9fcb96 100644
--- a/test/CodeGen/X86/statepoint-stack-usage.ll
+++ b/test/CodeGen/X86/statepoint-stack-usage.ll
@@ -8,53 +8,53 @@ target triple = "x86_64-pc-linux-gnu"
 ; of GC arguments differ, niave lowering code would insert loads and 
 ; stores to rearrange items on the stack.  We need to make sure (for
 ; performance) that this doesn't happen.
-define i32 @back_to_back_calls(i32* %a, i32* %b, i32* %c) #1 {
+define i32 @back_to_back_calls(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i32 addrspace(1)* %c) #1 gc "statepoint-example" {
 ; CHECK-LABEL: back_to_back_calls
 ; The exact stores don't matter, but there need to be three stack slots created
-; CHECK: movq	%rdx, 16(%rsp)
-; CHECK: movq	%rdi, 8(%rsp)
+; CHECK: movq	%rdi, 16(%rsp)
+; CHECK: movq	%rdx, 8(%rsp)
 ; CHECK: movq	%rsi, (%rsp)
-  %safepoint_token = tail call i32 (void ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_isVoidf(void ()* undef, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i32* %a, i32* %b, i32* %c)
-  %a1 = tail call coldcc i32* @llvm.experimental.gc.relocate.p0i32(i32 %safepoint_token, i32 9, i32 9)
-  %b1 = tail call coldcc i32* @llvm.experimental.gc.relocate.p0i32(i32 %safepoint_token, i32 9, i32 10)
-  %c1 = tail call coldcc i32* @llvm.experimental.gc.relocate.p0i32(i32 %safepoint_token, i32 9, i32 11)
+  %safepoint_token = tail call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* undef, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i32 addrspace(1)* %a, i32 addrspace(1)* %b, i32 addrspace(1)* %c)
+  %a1 = tail call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 12, i32 12)
+  %b1 = tail call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 12, i32 13)
+  %c1 = tail call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 12, i32 14)
 ; CHECK: callq
 ; This is the key check.  There should NOT be any memory moves here
 ; CHECK-NOT: movq
-  %safepoint_token2 = tail call i32 (void ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_isVoidf(void ()* undef, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i32* %c1, i32* %b1, i32* %a1)
-  %a2 = tail call coldcc i32* @llvm.experimental.gc.relocate.p0i32(i32 %safepoint_token2, i32 9, i32 11)
-  %b2 = tail call coldcc i32* @llvm.experimental.gc.relocate.p0i32(i32 %safepoint_token2, i32 9, i32 10)
-  %c2 = tail call coldcc i32* @llvm.experimental.gc.relocate.p0i32(i32 %safepoint_token2, i32 9, i32 9)
+  %safepoint_token2 = tail call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* undef, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i32 addrspace(1)* %c1, i32 addrspace(1)* %b1, i32 addrspace(1)* %a1)
+  %a2 = tail call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token2, i32 12, i32 14)
+  %b2 = tail call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token2, i32 12, i32 13)
+  %c2 = tail call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token2, i32 12, i32 12)
 ; CHECK: callq
   ret i32 1
 }
 
 ; This test simply checks that minor changes in vm state don't prevent slots
 ; being reused for gc values.  
-define i32 @reserve_first(i32* %a, i32* %b, i32* %c) #1 {
+define i32 @reserve_first(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i32 addrspace(1)* %c) #1 gc "statepoint-example" {
 ; CHECK-LABEL: reserve_first
 ; The exact stores don't matter, but there need to be three stack slots created
-; CHECK: movq	%rdx, 16(%rsp)
-; CHECK: movq	%rdi, 8(%rsp)
+; CHECK: movq	%rdi, 16(%rsp)
+; CHECK: movq	%rdx, 8(%rsp)
 ; CHECK: movq	%rsi, (%rsp)
-  %safepoint_token = tail call i32 (void ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_isVoidf(void ()* undef, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i32* %a, i32* %b, i32* %c)
-  %a1 = tail call coldcc i32* @llvm.experimental.gc.relocate.p0i32(i32 %safepoint_token, i32 9, i32 9)
-  %b1 = tail call coldcc i32* @llvm.experimental.gc.relocate.p0i32(i32 %safepoint_token, i32 9, i32 10)
-  %c1 = tail call coldcc i32* @llvm.experimental.gc.relocate.p0i32(i32 %safepoint_token, i32 9, i32 11)
+  %safepoint_token = tail call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* undef, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i32 addrspace(1)* %a, i32 addrspace(1)* %b, i32 addrspace(1)* %c)
+  %a1 = tail call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 12, i32 12)
+  %b1 = tail call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 12, i32 13)
+  %c1 = tail call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 12, i32 14)
 ; CHECK: callq
 ; This is the key check.  There should NOT be any memory moves here
 ; CHECK-NOT: movq
-  %safepoint_token2 = tail call i32 (void ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_isVoidf(void ()* undef, i32 0, i32 0, i32 5, i32* %a1, i32 0, i32* %c1, i32 0, i32 0, i32* %c1, i32* %b1, i32* %a1)
-  %a2 = tail call coldcc i32* @llvm.experimental.gc.relocate.p0i32(i32 %safepoint_token2, i32 9, i32 11)
-  %b2 = tail call coldcc i32* @llvm.experimental.gc.relocate.p0i32(i32 %safepoint_token2, i32 9, i32 10)
-  %c2 = tail call coldcc i32* @llvm.experimental.gc.relocate.p0i32(i32 %safepoint_token2, i32 9, i32 9)
+  %safepoint_token2 = tail call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* undef, i32 0, i32 0, i32 0, i32 5, i32 addrspace(1)* %a1, i32 0, i32 addrspace(1)* %c1, i32 0, i32 0, i32 addrspace(1)* %c1, i32 addrspace(1)* %b1, i32 addrspace(1)* %a1)
+  %a2 = tail call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token2, i32 12, i32 14)
+  %b2 = tail call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token2, i32 12, i32 13)
+  %c2 = tail call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token2, i32 12, i32 12)
 ; CHECK: callq
   ret i32 1
 }
 
 ; Function Attrs: nounwind
-declare i32* @llvm.experimental.gc.relocate.p0i32(i32, i32, i32) #3
+declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32, i32, i32) #3
 
-declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(void ()*, i32, i32, ...)
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
 
-attributes #1 = { uwtable }
+attributes #1 = { uwtable }
\ No newline at end of file
diff --git a/test/CodeGen/X86/statepoint-stackmap-format.ll b/test/CodeGen/X86/statepoint-stackmap-format.ll
index 416674839ea8..6bb0d8980e5b 100644
--- a/test/CodeGen/X86/statepoint-stackmap-format.ll
+++ b/test/CodeGen/X86/statepoint-stackmap-format.ll
@@ -8,32 +8,73 @@ target triple = "x86_64-pc-linux-gnu"
 
 declare zeroext i1 @return_i1()
 
-define i1 @test(i32 addrspace(1)* %ptr) {
+define i1 @test(i32 addrspace(1)* %ptr_base, i32 %arg)
+  gc "statepoint-example" {
 ; CHECK-LABEL: test
-; Do we see one spill for the local value and the store to the
+; Do we see two spills for the local values and the store to the
 ; alloca?
-; CHECK: subq	$24, %rsp
-; CHECK: movq	$0, 8(%rsp)
-; CHECK: movq	%rdi, (%rsp)
+; CHECK: subq	$40, %rsp
+; CHECK: movq	$0,   24(%rsp)
+; CHECK: movq	%rdi, 16(%rsp)
+; CHECK: movq	%rax, 8(%rsp)
 ; CHECK: callq return_i1
-; CHECK: addq	$24, %rsp
+; CHECK: addq	$40, %rsp
 ; CHECK: retq
 entry:
   %metadata1 = alloca i32 addrspace(1)*, i32 2, align 8
   store i32 addrspace(1)* null, i32 addrspace(1)** %metadata1
-  %safepoint_token = tail call i32 (i1 ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_i1f(i1 ()* @return_i1, i32 0, i32 0, i32 2, i32 addrspace(1)* %ptr, i32 addrspace(1)* null, i32 addrspace(1)* %ptr, i32 addrspace(1)* null)
-  %call1 = call zeroext i1 @llvm.experimental.gc.result.int.i1(i32 %safepoint_token)
-  %a = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 6, i32 6)
-  %b = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 7, i32 7)
+  %ptr_derived = getelementptr i32, i32 addrspace(1)* %ptr_base, i32 %arg
+  %safepoint_token = tail call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 2, i32 addrspace(1)* %ptr_base, i32 addrspace(1)* null, i32 addrspace(1)* %ptr_base, i32 addrspace(1)* %ptr_derived, i32 addrspace(1)* null)
+  %call1 = call zeroext i1 @llvm.experimental.gc.result.i1(i32 %safepoint_token)
+  %a = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 9, i32 9)
+  %b = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 9, i32 10)
+  %c = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 11, i32 11)
 ; 
   ret i1 %call1
 }
 
-declare i32 @llvm.experimental.gc.statepoint.p0f_i1f(i1 ()*, i32, i32, ...)
-declare i1 @llvm.experimental.gc.result.int.i1(i32)
-declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32, i32, i32) #3
+; This is similar to the previous test except that we have derived pointer as
+; argument to the function. Despite that this can not happen after the
+; RewriteSafepointForGC pass, lowering should be able to handle it anyway.
+define i1 @test_derived_arg(i32 addrspace(1)* %ptr_base,
+                            i32 addrspace(1)* %ptr_derived)
+  gc "statepoint-example" {
+; CHECK-LABEL: test_derived_arg
+; Do we see two spills for the local values and the store to the
+; alloca?
+; CHECK: subq	$40, %rsp
+; CHECK: movq	$0,   24(%rsp)
+; CHECK: movq	%rdi, 16(%rsp)
+; CHECK: movq	%rsi, 8(%rsp)
+; CHECK: callq return_i1
+; CHECK: addq	$40, %rsp
+; CHECK: retq
+entry:
+  %metadata1 = alloca i32 addrspace(1)*, i32 2, align 8
+  store i32 addrspace(1)* null, i32 addrspace(1)** %metadata1
+  %safepoint_token = tail call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 2, i32 addrspace(1)* %ptr_base, i32 addrspace(1)* null, i32 addrspace(1)* %ptr_base, i32 addrspace(1)* %ptr_derived, i32 addrspace(1)* null)
+  %call1 = call zeroext i1 @llvm.experimental.gc.result.i1(i32 %safepoint_token)
+  %a = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 9, i32 9)
+  %b = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 9, i32 10)
+  %c = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 11, i32 11)
+; 
+  ret i1 %call1
+}
+
+; Simple test case to check that we emit the ID field correctly
+define i1 @test_id() gc "statepoint-example" {
+; CHECK-LABEL: test_id
+entry:
+  %safepoint_token = tail call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 237, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0)
+  %call1 = call zeroext i1 @llvm.experimental.gc.result.i1(i32 %safepoint_token)
+  ret i1 %call1
+}
 
 
+declare i32 @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i32, ...)
+declare i1 @llvm.experimental.gc.result.i1(i32)
+declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32, i32, i32) #3
+
 ; CHECK-LABEL: .section .llvm_stackmaps
 ; CHECK-NEXT:  __LLVM_StackMaps:
 ; Header
@@ -41,25 +82,36 @@ declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32, i32, i32) #3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 0
 ; Num Functions
-; CHECK-NEXT:   .long 1
+; CHECK-NEXT:   .long 3
 ; Num LargeConstants
 ; CHECK-NEXT:   .long 0
 ; Num Callsites
-; CHECK-NEXT:   .long 1
+; CHECK-NEXT:   .long 3
 
 ; Functions and stack size
 ; CHECK-NEXT:   .quad test
-; CHECK-NEXT:   .quad 24
+; CHECK-NEXT:   .quad 40
+; CHECK-NEXT:   .quad test_derived_arg
+; CHECK-NEXT:   .quad 40
+
+;
+; test
+;
 
 ; Large Constants
 ; Statepoint ID only
-; CHECK: .quad	2882400000
+; CHECK: .quad	0
 
 ; Callsites
 ; Constant arguments
 ; CHECK: .long	.Ltmp1-test
 ; CHECK: .short	0
-; CHECK: .short	8
+; CHECK: .short	11
+; SmallConstant (0)
+; CHECK: .byte	4
+; CHECK: .byte	8
+; CHECK: .short	0
+; CHECK: .long	0
 ; SmallConstant (0)
 ; CHECK: .byte	4
 ; CHECK: .byte	8
@@ -74,7 +126,7 @@ declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32, i32, i32) #3
 ; CHECK: .byte	2
 ; CHECK: .byte	8
 ; CHECK: .short	7
-; CHECK: .long	0
+; CHECK: .long	16
 ; SmallConstant  (0)
 ; CHECK: .byte	4
 ; CHECK: .byte	8
@@ -90,20 +142,139 @@ declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32, i32, i32) #3
 ; CHECK: .byte	8
 ; CHECK: .short	0
 ; CHECK: .long	0
-; Direct Spill Slot [RSP+0]
+; Direct Spill Slot [RSP+16]
+; CHECK: .byte	2
+; CHECK: .byte	8
+; CHECK: .short	7
+; CHECK: .long	16
+; Direct Spill Slot [RSP+8]
 ; CHECK: .byte	2
 ; CHECK: .byte	8
 ; CHECK: .short	7
+; CHECK: .long	8
+; Direct Spill Slot [RSP+16]
+; CHECK: .byte	2
+; CHECK: .byte	8
+; CHECK: .short	7
+; CHECK: .long	16
+; Direct Spill Slot [RSP+16]
+; CHECK: .byte	2
+; CHECK: .byte	8
+; CHECK: .short	7
+; CHECK: .long	16
+
+; No Padding or LiveOuts
+; CHECK: .short	0
+; CHECK: .short	0
+; CHECK: .align	8
+
+;
+; test_derived_arg
+;
+
+; Large Constants
+; Statepoint ID only
+; CHECK: .quad	0
+
+; Callsites
+; Constant arguments
+; CHECK: .long	.Ltmp3-test_derived_arg
+; CHECK: .short	0
+; CHECK: .short	11
+; SmallConstant (0)
+; CHECK: .byte	4
+; CHECK: .byte	8
+; CHECK: .short	0
 ; CHECK: .long	0
+; SmallConstant (2)
+; CHECK: .byte	4
+; CHECK: .byte	8
+; CHECK: .short	0
+; CHECK: .long	2
 ; Direct Spill Slot [RSP+0]
 ; CHECK: .byte	2
 ; CHECK: .byte	8
 ; CHECK: .short	7
+; CHECK: .long	16
+; SmallConstant  (0)
+; CHECK: .byte	4
+; CHECK: .byte	8
+; CHECK: .short	0
+; CHECK: .long	0
+; SmallConstant  (0)
+; CHECK: .byte	4
+; CHECK: .byte	8
+; CHECK: .short	0
+; CHECK: .long	0
+; SmallConstant  (0)
+; CHECK: .byte	4
+; CHECK: .byte	8
+; CHECK: .short	0
 ; CHECK: .long	0
+; Direct Spill Slot [RSP+16]
+; CHECK: .byte	2
+; CHECK: .byte	8
+; CHECK: .short	7
+; CHECK: .long	16
+; Direct Spill Slot [RSP+8]
+; CHECK: .byte	2
+; CHECK: .byte	8
+; CHECK: .short	7
+; CHECK: .long	8
+; Direct Spill Slot [RSP+16]
+; CHECK: .byte	2
+; CHECK: .byte	8
+; CHECK: .short	7
+; CHECK: .long	16
+; Direct Spill Slot [RSP+16]
+; CHECK: .byte	2
+; CHECK: .byte	8
+; CHECK: .short	7
+; CHECK: .long	16
 
 ; No Padding or LiveOuts
 ; CHECK: .short	0
 ; CHECK: .short	0
 ; CHECK: .align	8
 
+; Records for the test_id function:
+; No large constants
+
+; The Statepoint ID:
+; CHECK: .quad	237
+
+; Instruction Offset
+; CHECK: .long	.Ltmp5-test_id
+
+; Reserved:
+; CHECK: .short	0
+
+; NumLocations:
+; CHECK: .short	3
+
+; StkMapRecord[0]:
+; SmallConstant(0):
+; CHECK: .byte	4
+; CHECK: .byte	8
+; CHECK: .short	0
+; CHECK: .long	0
+
+; StkMapRecord[1]:
+; SmallConstant(0):
+; CHECK: .byte	4
+; CHECK: .byte	8
+; CHECK: .short	0
+; CHECK: .long	0
+
+; StkMapRecord[2]:
+; SmallConstant(0):
+; CHECK: .byte	4
+; CHECK: .byte	8
+; CHECK: .short	0
+; CHECK: .long	0
+
+; No padding or LiveOuts
+; CHECK: .short	0
+; CHECK: .short	0
+; CHECK: .align	8
 
diff --git a/test/CodeGen/X86/stdarg.ll b/test/CodeGen/X86/stdarg.ll
index 5728daf1ee1c..18d502ad5834 100644
--- a/test/CodeGen/X86/stdarg.ll
+++ b/test/CodeGen/X86/stdarg.ll
@@ -8,7 +8,7 @@ entry:
   %ap = alloca [1 x %struct.__va_list_tag], align 8; <[1 x %struct.__va_list_tag]*> [#uses=2]
   %ap12 = bitcast [1 x %struct.__va_list_tag]* %ap to i8*; <i8*> [#uses=2]
   call void @llvm.va_start(i8* %ap12)
-  %ap3 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0; <%struct.__va_list_tag*> [#uses=1]
+  %ap3 = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0; <%struct.__va_list_tag*> [#uses=1]
   call void @bar(%struct.__va_list_tag* %ap3) nounwind
   call void @llvm.va_end(i8* %ap12)
   ret void
diff --git a/test/CodeGen/X86/store-narrow.ll b/test/CodeGen/X86/store-narrow.ll
index e3cc2fa668ef..6c1c56e43a4c 100644
--- a/test/CodeGen/X86/store-narrow.ll
+++ b/test/CodeGen/X86/store-narrow.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-apple-darwin10.2"
 
 define void @test1(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp {
 entry:
-  %A = load i32* %a0, align 4
+  %A = load i32, i32* %a0, align 4
   %B = and i32 %A, -256     ; 0xFFFFFF00
   %C = zext i8 %a1 to i32
   %D = or i32 %C, %B
@@ -23,7 +23,7 @@ entry:
 
 define void @test2(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp {
 entry:
-  %A = load i32* %a0, align 4
+  %A = load i32, i32* %a0, align 4
   %B = and i32 %A, -65281    ; 0xFFFF00FF
   %C = zext i8 %a1 to i32
   %CS = shl i32 %C, 8
@@ -40,7 +40,7 @@ entry:
 
 define void @test3(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp {
 entry:
-  %A = load i32* %a0, align 4
+  %A = load i32, i32* %a0, align 4
   %B = and i32 %A, -65536    ; 0xFFFF0000
   %C = zext i16 %a1 to i32
   %D = or i32 %B, %C
@@ -56,7 +56,7 @@ entry:
 
 define void @test4(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp {
 entry:
-  %A = load i32* %a0, align 4
+  %A = load i32, i32* %a0, align 4
   %B = and i32 %A, 65535    ; 0x0000FFFF
   %C = zext i16 %a1 to i32
   %CS = shl i32 %C, 16
@@ -73,7 +73,7 @@ entry:
 
 define void @test5(i64* nocapture %a0, i16 zeroext %a1) nounwind ssp {
 entry:
-  %A = load i64* %a0, align 4
+  %A = load i64, i64* %a0, align 4
   %B = and i64 %A, -4294901761    ; 0xFFFFFFFF0000FFFF
   %C = zext i16 %a1 to i64
   %CS = shl i64 %C, 16
@@ -90,7 +90,7 @@ entry:
 
 define void @test6(i64* nocapture %a0, i8 zeroext %a1) nounwind ssp {
 entry:
-  %A = load i64* %a0, align 4
+  %A = load i64, i64* %a0, align 4
   %B = and i64 %A, -280375465082881    ; 0xFFFF00FFFFFFFFFF
   %C = zext i8 %a1 to i64
   %CS = shl i64 %C, 40
@@ -108,8 +108,8 @@ entry:
 
 define i32 @test7(i64* nocapture %a0, i8 zeroext %a1, i32* %P2) nounwind {
 entry:
-  %OtherLoad = load i32 *%P2
-  %A = load i64* %a0, align 4
+  %OtherLoad = load i32 , i32 *%P2
+  %A = load i64, i64* %a0, align 4
   %B = and i64 %A, -280375465082881    ; 0xFFFF00FFFFFFFFFF
   %C = zext i8 %a1 to i64
   %CS = shl i64 %C, 40
@@ -136,7 +136,7 @@ entry:
 ; X64-NEXT: movl %eax, _g_16(%rip)
 ; X64-NEXT: ret
 define void @test8() nounwind {
-  %tmp = load i32* @g_16
+  %tmp = load i32, i32* @g_16
   store i32 0, i32* @g_16
   %or = or i32 %tmp, 1
   store i32 %or, i32* @g_16
@@ -147,7 +147,7 @@ define void @test8() nounwind {
 ; X64-NEXT: orb $1, _g_16(%rip)
 ; X64-NEXT: ret
 define void @test9() nounwind {
-  %tmp = load i32* @g_16
+  %tmp = load i32, i32* @g_16
   %or = or i32 %tmp, 1
   store i32 %or, i32* @g_16
   ret void
@@ -160,7 +160,7 @@ define void @test9() nounwind {
 ; X64-NEXT: ret
 define i8 @test10(i8* %P) nounwind ssp {
 entry:
-  %tmp = load i8* %P, align 1
+  %tmp = load i8, i8* %P, align 1
   %conv = sext i8 %tmp to i32
   %shr3 = lshr i32 %conv, 8
   %conv2 = trunc i32 %shr3 to i8
diff --git a/test/CodeGen/X86/store_op_load_fold.ll b/test/CodeGen/X86/store_op_load_fold.ll
index bbeb7443c07f..c4cdc0e9932a 100644
--- a/test/CodeGen/X86/store_op_load_fold.ll
+++ b/test/CodeGen/X86/store_op_load_fold.ll
@@ -9,7 +9,7 @@ define void @foo() nounwind {
 ; CHECK-NOT: mov
 ; CHECK: add
 ; CHECK-NEXT: ret
-        %tmp.0 = load i16* @X           ; <i16> [#uses=1]
+        %tmp.0 = load i16, i16* @X           ; <i16> [#uses=1]
         %tmp.3 = add i16 %tmp.0, 329            ; <i16> [#uses=1]
         store i16 %tmp.3, i16* @X
         ret void
@@ -23,8 +23,8 @@ define void @test2() nounwind uwtable ssp {
 ; CHECK: mov
 ; CHECK-NEXT: and
 ; CHECK-NEXT: ret
-  %bf.load35 = load i56* bitcast ([7 x i8]* getelementptr inbounds (%struct.S2* @s2, i32 0, i32 5) to i56*), align 16
+  %bf.load35 = load i56, i56* bitcast ([7 x i8]* getelementptr inbounds (%struct.S2, %struct.S2* @s2, i32 0, i32 5) to i56*), align 16
   %bf.clear36 = and i56 %bf.load35, -1125895611875329
-  store i56 %bf.clear36, i56* bitcast ([7 x i8]* getelementptr inbounds (%struct.S2* @s2, i32 0, i32 5) to i56*), align 16
+  store i56 %bf.clear36, i56* bitcast ([7 x i8]* getelementptr inbounds (%struct.S2, %struct.S2* @s2, i32 0, i32 5) to i56*), align 16
   ret void
 }
diff --git a/test/CodeGen/X86/store_op_load_fold2.ll b/test/CodeGen/X86/store_op_load_fold2.ll
index 705fdcdc13af..f47d87f4bb89 100644
--- a/test/CodeGen/X86/store_op_load_fold2.ll
+++ b/test/CodeGen/X86/store_op_load_fold2.ll
@@ -6,10 +6,10 @@ target datalayout = "e-p:32:32"
 
 define internal fastcc i32 @dct_chroma(i32 %uv, i32 %cr_cbp) nounwind {
 cond_true2732.preheader:                ; preds = %entry
-        %tmp2666 = getelementptr %struct.Macroblock* null, i32 0, i32 13                ; <i64*> [#uses=2]
+        %tmp2666 = getelementptr %struct.Macroblock, %struct.Macroblock* null, i32 0, i32 13                ; <i64*> [#uses=2]
         %tmp2674 = trunc i32 0 to i8            ; <i8> [#uses=1]
-        %tmp2667.us.us = load i64* %tmp2666             ; <i64> [#uses=1]
-        %tmp2670.us.us = load i64* null         ; <i64> [#uses=1]
+        %tmp2667.us.us = load i64, i64* %tmp2666             ; <i64> [#uses=1]
+        %tmp2670.us.us = load i64, i64* null         ; <i64> [#uses=1]
         %shift.upgrd.1 = zext i8 %tmp2674 to i64                ; <i64> [#uses=1]
         %tmp2675.us.us = shl i64 %tmp2670.us.us, %shift.upgrd.1         ; <i64> [#uses=1]
         %tmp2675not.us.us = xor i64 %tmp2675.us.us, -1          ; <i64> [#uses=1]
diff --git a/test/CodeGen/X86/stores-merging.ll b/test/CodeGen/X86/stores-merging.ll
index 61dea088995b..d6daa573b4ae 100644
--- a/test/CodeGen/X86/stores-merging.ll
+++ b/test/CodeGen/X86/stores-merging.ll
@@ -15,9 +15,9 @@ entry:
 ; CHECK:   movq    %rax, e+4(%rip)
 ; CHECK:   movl    $456, e+8(%rip)
 
-  store i32 1, i32* getelementptr inbounds (%structTy* @e, i64 0, i32 1), align 4
-  store i32 123, i32* getelementptr inbounds (%structTy* @e, i64 0, i32 2), align 4
-  store i32 456, i32* getelementptr inbounds (%structTy* @e, i64 0, i32 2), align 4
+  store i32 1, i32* getelementptr inbounds (%structTy, %structTy* @e, i64 0, i32 1), align 4
+  store i32 123, i32* getelementptr inbounds (%structTy, %structTy* @e, i64 0, i32 2), align 4
+  store i32 456, i32* getelementptr inbounds (%structTy, %structTy* @e, i64 0, i32 2), align 4
   ret void
 }
 
diff --git a/test/CodeGen/X86/stride-nine-with-base-reg.ll b/test/CodeGen/X86/stride-nine-with-base-reg.ll
index ddf059c675df..551bd7c2541e 100644
--- a/test/CodeGen/X86/stride-nine-with-base-reg.ll
+++ b/test/CodeGen/X86/stride-nine-with-base-reg.ll
@@ -17,16 +17,16 @@ entry:
 
 bb:
 	%i.019.0 = phi i32 [ %indvar.next, %bb ], [ 0, %entry ]
-	%tmp2 = getelementptr [1000 x i8]* @B, i32 0, i32 %i.019.0
-	%tmp3 = load i8* %tmp2, align 4
+	%tmp2 = getelementptr [1000 x i8], [1000 x i8]* @B, i32 0, i32 %i.019.0
+	%tmp3 = load i8, i8* %tmp2, align 4
 	%tmp4 = mul i8 %tmp3, 2
-	%tmp5 = getelementptr [1000 x i8]* @A, i32 0, i32 %i.019.0
+	%tmp5 = getelementptr [1000 x i8], [1000 x i8]* @A, i32 0, i32 %i.019.0
 	store i8 %tmp4, i8* %tmp5, align 4
 	%tmp8 = mul i32 %i.019.0, 9
         %tmp0 = add i32 %tmp8, %p
-	%tmp10 = getelementptr [1000 x i8]* @P, i32 0, i32 %tmp0
+	%tmp10 = getelementptr [1000 x i8], [1000 x i8]* @P, i32 0, i32 %tmp0
 	store i8 17, i8* %tmp10, align 4
-	%tmp11 = getelementptr [1000 x i8]* @Q, i32 0, i32 %tmp0
+	%tmp11 = getelementptr [1000 x i8], [1000 x i8]* @Q, i32 0, i32 %tmp0
 	store i8 19, i8* %tmp11, align 4
 	%indvar.next = add i32 %i.019.0, 1
 	%exitcond = icmp eq i32 %indvar.next, %m
diff --git a/test/CodeGen/X86/stride-reuse.ll b/test/CodeGen/X86/stride-reuse.ll
index 81de22ca4e35..af036f3a8f14 100644
--- a/test/CodeGen/X86/stride-reuse.ll
+++ b/test/CodeGen/X86/stride-reuse.ll
@@ -13,14 +13,14 @@ entry:
 
 bb:
 	%i.019.0 = phi i32 [ %indvar.next, %bb ], [ 0, %entry ]
-	%tmp2 = getelementptr [1000 x float]* @B, i32 0, i32 %i.019.0
-	%tmp3 = load float* %tmp2, align 4
+	%tmp2 = getelementptr [1000 x float], [1000 x float]* @B, i32 0, i32 %i.019.0
+	%tmp3 = load float, float* %tmp2, align 4
 	%tmp4 = fmul float %tmp3, 2.000000e+00
-	%tmp5 = getelementptr [1000 x float]* @A, i32 0, i32 %i.019.0
+	%tmp5 = getelementptr [1000 x float], [1000 x float]* @A, i32 0, i32 %i.019.0
 	store float %tmp4, float* %tmp5, align 4
 	%tmp8 = shl i32 %i.019.0, 1
 	%tmp9 = add i32 %tmp8, 64
-	%tmp10 = getelementptr [1000 x i32]* @P, i32 0, i32 %i.019.0
+	%tmp10 = getelementptr [1000 x i32], [1000 x i32]* @P, i32 0, i32 %i.019.0
 	store i32 %tmp9, i32* %tmp10, align 4
 	%indvar.next = add i32 %i.019.0, 1
 	%exitcond = icmp eq i32 %indvar.next, %m
diff --git a/test/CodeGen/X86/sub-with-overflow.ll b/test/CodeGen/X86/sub-with-overflow.ll
index baaee3541108..fa00d6f61c70 100644
--- a/test/CodeGen/X86/sub-with-overflow.ll
+++ b/test/CodeGen/X86/sub-with-overflow.ll
@@ -11,11 +11,11 @@ entry:
   br i1 %obit, label %overflow, label %normal
 
 normal:
-  %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
+  %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
   ret i1 true
 
 overflow:
-  %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+  %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
 
 ; CHECK-LABEL: func1:
@@ -31,11 +31,11 @@ entry:
   br i1 %obit, label %carry, label %normal
 
 normal:
-  %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
+  %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
   ret i1 true
 
 carry:
-  %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+  %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
 
 ; CHECK-LABEL: func2:
diff --git a/test/CodeGen/X86/subreg-to-reg-0.ll b/test/CodeGen/X86/subreg-to-reg-0.ll
index d718c85a1d1f..251a754f4383 100644
--- a/test/CodeGen/X86/subreg-to-reg-0.ll
+++ b/test/CodeGen/X86/subreg-to-reg-0.ll
@@ -4,7 +4,7 @@
 ; x86-64's implicit zero-extension!
 
 define i64 @foo(i32* %p) nounwind {
-  %t = load i32* %p
+  %t = load i32, i32* %p
   %n = add i32 %t, 1
   %z = zext i32 %n to i64
   ret i64 %z
diff --git a/test/CodeGen/X86/subreg-to-reg-2.ll b/test/CodeGen/X86/subreg-to-reg-2.ll
index 49d2e88d2c8d..6766b013a36e 100644
--- a/test/CodeGen/X86/subreg-to-reg-2.ll
+++ b/test/CodeGen/X86/subreg-to-reg-2.ll
@@ -10,8 +10,8 @@
 
 define internal fastcc %XXValue* @t(i64* %out, %"struct.XXC::ArrayStorage"* %tmp9) nounwind {
 prologue:
-	%array = load %XXValue** inttoptr (i64 11111111 to %XXValue**)		; <%XXValue*> [#uses=0]
-	%index = load %XXValue** inttoptr (i64 22222222 to %XXValue**)		; <%XXValue*> [#uses=1]
+	%array = load %XXValue*, %XXValue** inttoptr (i64 11111111 to %XXValue**)		; <%XXValue*> [#uses=0]
+	%index = load %XXValue*, %XXValue** inttoptr (i64 22222222 to %XXValue**)		; <%XXValue*> [#uses=1]
 	%tmp = ptrtoint %XXValue* %index to i64		; <i64> [#uses=2]
 	store i64 %tmp, i64* %out
 	%tmp6 = trunc i64 %tmp to i32		; <i32> [#uses=1]
@@ -19,7 +19,7 @@ prologue:
 
 bb5:		; preds = %prologue
 	%tmp10 = zext i32 %tmp6 to i64		; <i64> [#uses=1]
-	%tmp11 = getelementptr %"struct.XXC::ArrayStorage"* %tmp9, i64 0, i32 5, i64 %tmp10		; <%XXValue**> [#uses=1]
-	%tmp12 = load %XXValue** %tmp11, align 8		; <%XXValue*> [#uses=1]
+	%tmp11 = getelementptr %"struct.XXC::ArrayStorage", %"struct.XXC::ArrayStorage"* %tmp9, i64 0, i32 5, i64 %tmp10		; <%XXValue**> [#uses=1]
+	%tmp12 = load %XXValue*, %XXValue** %tmp11, align 8		; <%XXValue*> [#uses=1]
 	ret %XXValue* %tmp12
 }
diff --git a/test/CodeGen/X86/subreg-to-reg-4.ll b/test/CodeGen/X86/subreg-to-reg-4.ll
index 0693789fe5d5..8340fc536140 100644
--- a/test/CodeGen/X86/subreg-to-reg-4.ll
+++ b/test/CodeGen/X86/subreg-to-reg-4.ll
@@ -28,7 +28,7 @@ entry:
 }
 define void @cola(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
 entry:
-        %p = load i64* %x
+        %p = load i64, i64* %x
 	%t0 = add i64 %p, %y
 	%t1 = and i64 %t0, 4294967295
         %t2 = xor i64 %t1, %u
@@ -37,7 +37,7 @@ entry:
 }
 define void @yaks(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
 entry:
-        %p = load i64* %x
+        %p = load i64, i64* %x
 	%t0 = add i64 %p, %y
         %t1 = xor i64 %t0, %u
 	%t2 = and i64 %t1, 4294967295
@@ -46,8 +46,8 @@ entry:
 }
 define void @foo(i64 *%x, i64 *%y, i64* %z) nounwind readnone {
 entry:
-        %a = load i64* %x
-        %b = load i64* %y
+        %a = load i64, i64* %x
+        %b = load i64, i64* %y
 	%t0 = add i64 %a, %b
 	%t1 = and i64 %t0, 4294967295
         store i64 %t1, i64* %z
@@ -94,7 +94,7 @@ entry:
 }
 define void @scola(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
 entry:
-        %p = load i64* %x
+        %p = load i64, i64* %x
 	%t0 = sub i64 %p, %y
 	%t1 = and i64 %t0, 4294967295
         %t2 = xor i64 %t1, %u
@@ -103,7 +103,7 @@ entry:
 }
 define void @syaks(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
 entry:
-        %p = load i64* %x
+        %p = load i64, i64* %x
 	%t0 = sub i64 %p, %y
         %t1 = xor i64 %t0, %u
 	%t2 = and i64 %t1, 4294967295
@@ -112,8 +112,8 @@ entry:
 }
 define void @sfoo(i64 *%x, i64 *%y, i64* %z) nounwind readnone {
 entry:
-        %a = load i64* %x
-        %b = load i64* %y
+        %a = load i64, i64* %x
+        %b = load i64, i64* %y
 	%t0 = sub i64 %a, %b
 	%t1 = and i64 %t0, 4294967295
         store i64 %t1, i64* %z
diff --git a/test/CodeGen/X86/subreg-to-reg-6.ll b/test/CodeGen/X86/subreg-to-reg-6.ll
index 76430cd783e3..bef09fa944ef 100644
--- a/test/CodeGen/X86/subreg-to-reg-6.ll
+++ b/test/CodeGen/X86/subreg-to-reg-6.ll
@@ -2,7 +2,7 @@
 
 define i64 @foo() nounwind {
 entry:
-	%t0 = load i32* null, align 8
+	%t0 = load i32, i32* null, align 8
 	switch i32 %t0, label %bb65 [
 		i32 16, label %bb
 		i32 12, label %bb56
diff --git a/test/CodeGen/X86/sunkaddr-ext.ll b/test/CodeGen/X86/sunkaddr-ext.ll
index 6d238678ce30..b57981151bdd 100644
--- a/test/CodeGen/X86/sunkaddr-ext.ll
+++ b/test/CodeGen/X86/sunkaddr-ext.ll
@@ -11,11 +11,11 @@ target triple = "x86_64-apple-macosx10.9.0"
 define void @test_sink(i8* %arg1, i32 %arg2, i8 %arg3) #0 {
   %tmp1 = add i32 -2147483648, %arg2
   %tmp2 = add i32 -2147483648, %tmp1
-  %tmp3 = getelementptr i8* %arg1, i32 %arg2
+  %tmp3 = getelementptr i8, i8* %arg1, i32 %arg2
   br label %bb1
 
 bb1:
-  %tmp4 = getelementptr i8* %arg1, i32 %tmp2
+  %tmp4 = getelementptr i8, i8* %arg1, i32 %tmp2
   store i8 %arg3, i8* %tmp4
   ret void;
 }
diff --git a/test/CodeGen/X86/switch-bt.ll b/test/CodeGen/X86/switch-bt.ll
index a80002bc97cc..2cf3aafe5471 100644
--- a/test/CodeGen/X86/switch-bt.ll
+++ b/test/CodeGen/X86/switch-bt.ll
@@ -16,8 +16,8 @@ define void @test(i8* %l) nounwind {
 entry:
   %l.addr = alloca i8*, align 8                   ; <i8**> [#uses=2]
   store i8* %l, i8** %l.addr
-  %tmp = load i8** %l.addr                        ; <i8*> [#uses=1]
-  %tmp1 = load i8* %tmp                           ; <i8> [#uses=1]
+  %tmp = load i8*, i8** %l.addr                        ; <i8*> [#uses=1]
+  %tmp1 = load i8, i8* %tmp                           ; <i8> [#uses=1]
   %conv = sext i8 %tmp1 to i32                    ; <i32> [#uses=1]
   switch i32 %conv, label %sw.default [
     i32 62, label %sw.bb
@@ -99,3 +99,59 @@ if.then:
 if.end:
   ret void
 }
+
+; Ensure that optimizing for jump tables doesn't needlessly deteriorate the
+; created binary tree search. See PR22262.
+define void @test4(i32 %x, i32* %y) {
+; CHECK-LABEL: test4:
+
+entry:
+  switch i32 %x, label %sw.default [
+    i32 10, label %sw.bb
+    i32 20, label %sw.bb1
+    i32 30, label %sw.bb2
+    i32 40, label %sw.bb3
+    i32 50, label %sw.bb4
+    i32 60, label %sw.bb5
+  ]
+sw.bb:
+  store i32 1, i32* %y
+  br label %sw.epilog
+sw.bb1:
+  store i32 2, i32* %y
+  br label %sw.epilog
+sw.bb2:
+  store i32 3, i32* %y
+  br label %sw.epilog
+sw.bb3:
+  store i32 4, i32* %y
+  br label %sw.epilog
+sw.bb4:
+  store i32 5, i32* %y
+  br label %sw.epilog
+sw.bb5:
+  store i32 6, i32* %y
+  br label %sw.epilog
+sw.default:
+  store i32 7, i32* %y
+  br label %sw.epilog
+sw.epilog:
+  ret void
+
+; The balanced binary switch here would start with a comparison against 39, but
+; it is currently starting with 29 because of the density-sum heuristic.
+; CHECK: cmpl $39
+; CHECK: jg
+; CHECK: cmpl $10
+; CHECK: je
+; CHECK: cmpl $20
+; CHECK: jne
+; CHECK: cmpl $40
+; CHECK: je
+; CHECK: cmpl $50
+; CHECK: jne
+; CHECK: cmpl $30
+; CHECK: jne
+; CHECK: cmpl $60
+; CHECK: jne
+}
diff --git a/test/CodeGen/X86/switch-crit-edge-constant.ll b/test/CodeGen/X86/switch-crit-edge-constant.ll
index 18f987e72213..e9a208d709ef 100644
--- a/test/CodeGen/X86/switch-crit-edge-constant.ll
+++ b/test/CodeGen/X86/switch-crit-edge-constant.ll
@@ -34,20 +34,20 @@ cond_true:		; preds = %bb2
 	br label %blahaha
 
 blahaha:		; preds = %cond_true, %bb2, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry
-	%s.0 = phi i8* [ getelementptr ([8 x i8]* @str, i32 0, i64 0), %cond_true ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str2, i32 0, i64 0), %bb2 ]		; <i8*> [#uses=13]
-	%tmp8 = tail call i32 (i8*, ...)* @printf( i8* %s.0 )		; <i32> [#uses=0]
-	%tmp10 = tail call i32 (i8*, ...)* @printf( i8* %s.0 )		; <i32> [#uses=0]
-	%tmp12 = tail call i32 (i8*, ...)* @printf( i8* %s.0 )		; <i32> [#uses=0]
-	%tmp14 = tail call i32 (i8*, ...)* @printf( i8* %s.0 )		; <i32> [#uses=0]
-	%tmp16 = tail call i32 (i8*, ...)* @printf( i8* %s.0 )		; <i32> [#uses=0]
-	%tmp18 = tail call i32 (i8*, ...)* @printf( i8* %s.0 )		; <i32> [#uses=0]
-	%tmp20 = tail call i32 (i8*, ...)* @printf( i8* %s.0 )		; <i32> [#uses=0]
-	%tmp22 = tail call i32 (i8*, ...)* @printf( i8* %s.0 )		; <i32> [#uses=0]
-	%tmp24 = tail call i32 (i8*, ...)* @printf( i8* %s.0 )		; <i32> [#uses=0]
-	%tmp26 = tail call i32 (i8*, ...)* @printf( i8* %s.0 )		; <i32> [#uses=0]
-	%tmp28 = tail call i32 (i8*, ...)* @printf( i8* %s.0 )		; <i32> [#uses=0]
-	%tmp30 = tail call i32 (i8*, ...)* @printf( i8* %s.0 )		; <i32> [#uses=0]
-	%tmp32 = tail call i32 (i8*, ...)* @printf( i8* %s.0 )		; <i32> [#uses=0]
+	%s.0 = phi i8* [ getelementptr ([8 x i8], [8 x i8]* @str, i32 0, i64 0), %cond_true ], [ getelementptr ([5 x i8], [5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8], [5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8], [5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8], [5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8], [5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8], [5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8], [5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8], [5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8], [5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8], [5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8], [5 x i8]* @str2, i32 0, i64 0), %bb2 ]		; <i8*> [#uses=13]
+	%tmp8 = tail call i32 (i8*, ...) @printf( i8* %s.0 )		; <i32> [#uses=0]
+	%tmp10 = tail call i32 (i8*, ...) @printf( i8* %s.0 )		; <i32> [#uses=0]
+	%tmp12 = tail call i32 (i8*, ...) @printf( i8* %s.0 )		; <i32> [#uses=0]
+	%tmp14 = tail call i32 (i8*, ...) @printf( i8* %s.0 )		; <i32> [#uses=0]
+	%tmp16 = tail call i32 (i8*, ...) @printf( i8* %s.0 )		; <i32> [#uses=0]
+	%tmp18 = tail call i32 (i8*, ...) @printf( i8* %s.0 )		; <i32> [#uses=0]
+	%tmp20 = tail call i32 (i8*, ...) @printf( i8* %s.0 )		; <i32> [#uses=0]
+	%tmp22 = tail call i32 (i8*, ...) @printf( i8* %s.0 )		; <i32> [#uses=0]
+	%tmp24 = tail call i32 (i8*, ...) @printf( i8* %s.0 )		; <i32> [#uses=0]
+	%tmp26 = tail call i32 (i8*, ...) @printf( i8* %s.0 )		; <i32> [#uses=0]
+	%tmp28 = tail call i32 (i8*, ...) @printf( i8* %s.0 )		; <i32> [#uses=0]
+	%tmp30 = tail call i32 (i8*, ...) @printf( i8* %s.0 )		; <i32> [#uses=0]
+	%tmp32 = tail call i32 (i8*, ...) @printf( i8* %s.0 )		; <i32> [#uses=0]
 	ret void
 }
 
diff --git a/test/CodeGen/X86/switch-or.ll b/test/CodeGen/X86/switch-or.ll
index 75832c7d304c..6e6b013d9fa8 100644
--- a/test/CodeGen/X86/switch-or.ll
+++ b/test/CodeGen/X86/switch-or.ll
@@ -12,7 +12,7 @@ entry:
   ]
 
 if.then:
-  %call = tail call i32 (...)* @bar() nounwind
+  %call = tail call i32 (...) @bar() nounwind
   ret void
 
 if.end:
diff --git a/test/CodeGen/X86/switch-zextload.ll b/test/CodeGen/X86/switch-zextload.ll
index 55425bc7da5c..2dd3f0e3ae72 100644
--- a/test/CodeGen/X86/switch-zextload.ll
+++ b/test/CodeGen/X86/switch-zextload.ll
@@ -9,7 +9,7 @@ target triple = "i386-apple-darwin9.6"
 
 define fastcc void @set_proof_and_disproof_numbers(%struct.node_t* nocapture %node) nounwind {
 entry:
-	%0 = load i8* null, align 1		; <i8> [#uses=1]
+	%0 = load i8, i8* null, align 1		; <i8> [#uses=1]
 	switch i8 %0, label %return [
 		i8 2, label %bb31
 		i8 0, label %bb80
diff --git a/test/CodeGen/X86/switch.ll b/test/CodeGen/X86/switch.ll
new file mode 100644
index 000000000000..66a739c8470c
--- /dev/null
+++ b/test/CodeGen/X86/switch.ll
@@ -0,0 +1,536 @@
+; RUN: llc -mtriple=x86_64-linux-gnu %s -o - | FileCheck %s
+; RUN: llc -mtriple=x86_64-linux-gnu %s -o - -O0 | FileCheck --check-prefix=NOOPT %s
+
+declare void @g(i32)
+
+define void @basic(i32 %x) {
+entry:
+  switch i32 %x, label %return [
+    i32 3, label %bb0
+    i32 1, label %bb1
+    i32 4, label %bb1
+    i32 5, label %bb2
+  ]
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+bb2: tail call void @g(i32 1) br label %return
+return: ret void
+
+; Should be lowered as straight compares in -O0 mode.
+; NOOPT-LABEL: basic
+; NOOPT: subl $1, %eax
+; NOOPT: je
+; NOOPT: subl $3, %eax
+; NOOPT: je
+; NOOPT: subl $4, %eax
+; NOOPT: je
+; NOOPT: subl $5, %eax
+; NOOPT: je
+
+; Jump table otherwise.
+; CHECK-LABEL: basic
+; CHECK: decl
+; CHECK: cmpl $4
+; CHECK: ja
+; CHECK: jmpq *.LJTI
+}
+
+
+define void @simple_ranges(i32 %x) {
+entry:
+  switch i32 %x, label %return [
+    i32 0, label %bb0
+    i32 1, label %bb0
+    i32 2, label %bb0
+    i32 3, label %bb0
+    i32 100, label %bb1
+    i32 101, label %bb1
+    i32 102, label %bb1
+    i32 103, label %bb1
+  ]
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+return: ret void
+
+; Should be lowered to two range checks.
+; CHECK-LABEL: simple_ranges
+; CHECK: leal -100
+; CHECK: cmpl $4
+; CHECK: jae
+; CHECK: cmpl $3
+; CHECK: ja
+
+; We do this even at -O0, because it's cheap and makes codegen faster.
+; NOOPT-LABEL: simple_ranges
+; NOOPT: subl $4
+; NOOPT: jb
+; NOOPT: addl $-100
+; NOOPT: subl $4
+; NOOPT: jb
+}
+
+
+define void @jt_is_better(i32 %x) {
+entry:
+  switch i32 %x, label %return [
+    i32 0, label %bb0
+    i32 2, label %bb0
+    i32 4, label %bb0
+    i32 1, label %bb1
+    i32 3, label %bb1
+    i32 5, label %bb1
+
+    i32 6, label %bb2
+    i32 7, label %bb3
+    i32 8, label %bb4
+  ]
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+bb2: tail call void @g(i32 2) br label %return
+bb3: tail call void @g(i32 3) br label %return
+bb4: tail call void @g(i32 4) br label %return
+return: ret void
+
+; Cases 0-5 could be lowered with two bit tests,
+; but with 6-8, the whole switch is suitable for a jump table.
+; CHECK-LABEL: jt_is_better
+; CHECK: cmpl $8
+; CHECK: jbe
+; CHECK: jmpq *.LJTI
+}
+
+
+define void @bt_is_better(i32 %x) {
+entry:
+  switch i32 %x, label %return [
+    i32 0, label %bb0
+    i32 3, label %bb0
+    i32 6, label %bb0
+    i32 1, label %bb1
+    i32 4, label %bb1
+    i32 7, label %bb1
+    i32 2, label %bb2
+    i32 5, label %bb2
+    i32 8, label %bb2
+
+  ]
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+bb2: tail call void @g(i32 2) br label %return
+return: ret void
+
+; This could be lowered as a jump table, but bit tests is more efficient.
+; CHECK-LABEL: bt_is_better
+; 73 = 2^0 + 2^3 + 2^6
+; CHECK: movl $73
+; CHECK: btl
+; 146 = 2^1 + 2^4 + 2^7
+; CHECK: movl $146
+; CHECK: btl
+; 292 = 2^2 + 2^5 + 2^8
+; CHECK: movl $292
+; CHECK: btl
+}
+
+
+define void @optimal_pivot1(i32 %x) {
+entry:
+  switch i32 %x, label %return [
+    i32 100, label %bb0
+    i32 200, label %bb1
+    i32 300, label %bb0
+    i32 400, label %bb1
+    i32 500, label %bb0
+    i32 600, label %bb1
+
+  ]
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+return: ret void
+
+; Should pivot around 400 for two subtrees of equal size.
+; CHECK-LABEL: optimal_pivot1
+; CHECK-NOT: cmpl
+; CHECK: cmpl $399
+}
+
+
+define void @optimal_pivot2(i32 %x) {
+entry:
+  switch i32 %x, label %return [
+    i32 100, label %bb0   i32 101, label %bb1   i32 102, label %bb2   i32 103, label %bb3
+    i32 200, label %bb0   i32 201, label %bb1   i32 202, label %bb2   i32 203, label %bb3
+    i32 300, label %bb0   i32 301, label %bb1   i32 302, label %bb2   i32 303, label %bb3
+    i32 400, label %bb0   i32 401, label %bb1   i32 402, label %bb2   i32 403, label %bb3
+
+  ]
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+bb2: tail call void @g(i32 2) br label %return
+bb3: tail call void @g(i32 3) br label %return
+return: ret void
+
+; Should pivot around 300 for two subtrees with two jump tables each.
+; CHECK-LABEL: optimal_pivot2
+; CHECK-NOT: cmpl
+; CHECK: cmpl $299
+; CHECK: jmpq *.LJTI
+; CHECK: jmpq *.LJTI
+; CHECK: jmpq *.LJTI
+; CHECK: jmpq *.LJTI
+}
+
+
+define void @optimal_jump_table1(i32 %x) {
+entry:
+  switch i32 %x, label %return [
+    i32 0,  label %bb0
+    i32 5,  label %bb1
+    i32 6,  label %bb2
+    i32 12, label %bb3
+    i32 13, label %bb4
+    i32 15, label %bb5
+  ]
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+bb2: tail call void @g(i32 2) br label %return
+bb3: tail call void @g(i32 3) br label %return
+bb4: tail call void @g(i32 4) br label %return
+bb5: tail call void @g(i32 5) br label %return
+return: ret void
+
+; Splitting in the largest gap (between 6 and 12) would yield suboptimal result.
+; Expecting a jump table from 5 to 15.
+; CHECK-LABEL: optimal_jump_table1
+; CHECK: leal -5
+; CHECK: cmpl $10
+; CHECK: jmpq *.LJTI
+}
+
+
+define void @optimal_jump_table2(i32 %x) {
+entry:
+  switch i32 %x, label %return [
+    i32 0,  label %bb0
+    i32 1,  label %bb1
+    i32 2,  label %bb2
+    i32 9,  label %bb3
+    i32 14, label %bb4
+    i32 15, label %bb5
+  ]
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+bb2: tail call void @g(i32 2) br label %return
+bb3: tail call void @g(i32 3) br label %return
+bb4: tail call void @g(i32 4) br label %return
+bb5: tail call void @g(i32 5) br label %return
+return: ret void
+
+; Partitioning the cases to the minimum number of dense sets is not good enough.
+; This can be partitioned as {0,1,2,9},{14,15} or {0,1,2},{9,14,15}. The former
+; should be preferred. Expecting a table from 0-9.
+; CHECK-LABEL: optimal_jump_table2
+; CHECK: cmpl $9
+; CHECK: jmpq *.LJTI
+}
+
+
+define void @optimal_jump_table3(i32 %x) {
+entry:
+  switch i32 %x, label %return [
+    i32 1,  label %bb0
+    i32 2,  label %bb1
+    i32 3,  label %bb2
+    i32 10, label %bb3
+    i32 13, label %bb0
+    i32 14, label %bb1
+    i32 15, label %bb2
+    i32 20, label %bb3
+    i32 25, label %bb4
+  ]
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+bb2: tail call void @g(i32 2) br label %return
+bb3: tail call void @g(i32 3) br label %return
+bb4: tail call void @g(i32 4) br label %return
+return: ret void
+
+; Splitting to maximize left-right density sum and gap size would split this
+; between 3 and 10, and then between 20 and 25. It's better to build a table
+; from 1-20.
+; CHECK-LABEL: optimal_jump_table3
+; CHECK: leal -1
+; CHECK: cmpl $19
+; CHECK: jmpq *.LJTI
+}
+
+%struct.S = type { %struct.S*, i32 }
+define void @phi_node_trouble(%struct.S* %s) {
+entry:
+  br label %header
+header:
+  %ptr = phi %struct.S* [ %s, %entry ], [ %next, %loop ]
+  %bool = icmp eq %struct.S* %ptr, null
+  br i1 %bool, label %exit, label %loop
+loop:
+  %nextptr = getelementptr inbounds %struct.S, %struct.S* %ptr, i64 0, i32 0
+  %next = load %struct.S*, %struct.S** %nextptr
+  %xptr = getelementptr inbounds %struct.S, %struct.S* %next, i64 0, i32 1
+  %x = load i32, i32* %xptr
+  switch i32 %x, label %exit [
+    i32 4, label %header
+    i32 36, label %exit2
+    i32 69, label %exit2
+    i32 25, label %exit2
+  ]
+exit:
+  ret void
+exit2:
+  ret void
+
+; This will be lowered to a comparison with 4 and then bit tests. Make sure
+; that the phi node in %header gets a value from the comparison block.
+; CHECK-LABEL: phi_node_trouble
+; CHECK: movq (%[[REG1:[a-z]+]]), %[[REG1]]
+; CHECK: movl 8(%[[REG1]]), %[[REG2:[a-z]+]]
+; CHECK: cmpl $4, %[[REG2]]
+}
+
+
+define void @default_only(i32 %x) {
+entry:
+  br label %sw
+return:
+  ret void
+sw:
+  switch i32 %x, label %return [
+  ]
+
+; Branch directly to the default.
+; (In optimized builds the switch is removed earlier.)
+; NOOPT-LABEL: default_only
+; NOOPT: .[[L:[A-Z0-9_]+]]:
+; NOOPT-NEXT: retq
+; NOOPT: jmp .[[L]]
+}
+
+
+define void @int_max_table_cluster(i8 %x) {
+entry:
+  switch i8 %x, label %return [
+    i8 0, label %bb0 i8 1, label %bb0 i8 2, label %bb0 i8 3, label %bb0
+    i8 4, label %bb0 i8 5, label %bb0 i8 6, label %bb0 i8 7, label %bb0
+    i8 8, label %bb0 i8 9, label %bb0 i8 10, label %bb0 i8 11, label %bb0
+    i8 12, label %bb0 i8 13, label %bb0 i8 14, label %bb0 i8 15, label %bb0
+    i8 16, label %bb0 i8 17, label %bb0 i8 18, label %bb0 i8 19, label %bb0
+    i8 20, label %bb0 i8 21, label %bb0 i8 22, label %bb0 i8 23, label %bb0
+    i8 24, label %bb0 i8 25, label %bb0 i8 26, label %bb0 i8 27, label %bb0
+    i8 28, label %bb0 i8 29, label %bb0 i8 30, label %bb0 i8 31, label %bb0
+    i8 32, label %bb0 i8 33, label %bb0 i8 34, label %bb0 i8 35, label %bb0
+    i8 36, label %bb0 i8 37, label %bb0 i8 38, label %bb0 i8 39, label %bb0
+    i8 40, label %bb0 i8 41, label %bb0 i8 42, label %bb0 i8 43, label %bb0
+    i8 44, label %bb0 i8 45, label %bb0 i8 46, label %bb0 i8 47, label %bb0
+    i8 48, label %bb0 i8 49, label %bb0 i8 50, label %bb0 i8 51, label %bb0
+    i8 52, label %bb0 i8 53, label %bb0 i8 54, label %bb0 i8 55, label %bb0
+    i8 56, label %bb0 i8 57, label %bb0 i8 58, label %bb0 i8 59, label %bb0
+    i8 60, label %bb0 i8 61, label %bb0 i8 62, label %bb0 i8 63, label %bb0
+    i8 64, label %bb0 i8 65, label %bb0 i8 66, label %bb0 i8 67, label %bb0
+    i8 68, label %bb0 i8 69, label %bb0 i8 70, label %bb0 i8 71, label %bb0
+    i8 72, label %bb0 i8 73, label %bb0 i8 74, label %bb0 i8 75, label %bb0
+    i8 76, label %bb0 i8 77, label %bb0 i8 78, label %bb0 i8 79, label %bb0
+    i8 80, label %bb0 i8 81, label %bb0 i8 82, label %bb0 i8 83, label %bb0
+    i8 84, label %bb0 i8 85, label %bb0 i8 86, label %bb0 i8 87, label %bb0
+    i8 88, label %bb0 i8 89, label %bb0 i8 90, label %bb0 i8 91, label %bb0
+    i8 92, label %bb0 i8 93, label %bb0 i8 94, label %bb0 i8 95, label %bb0
+    i8 96, label %bb0 i8 97, label %bb0 i8 98, label %bb0 i8 99, label %bb0
+    i8 100, label %bb0 i8 101, label %bb0 i8 102, label %bb0 i8 103, label %bb0
+    i8 104, label %bb0 i8 105, label %bb0 i8 106, label %bb0 i8 107, label %bb0
+    i8 108, label %bb0 i8 109, label %bb0 i8 110, label %bb0 i8 111, label %bb0
+    i8 112, label %bb0 i8 113, label %bb0 i8 114, label %bb0 i8 115, label %bb0
+    i8 116, label %bb0 i8 117, label %bb0 i8 118, label %bb0 i8 119, label %bb0
+    i8 120, label %bb0 i8 121, label %bb0 i8 122, label %bb0 i8 123, label %bb0
+    i8 124, label %bb0 i8 125, label %bb0 i8 126, label %bb0 i8 127, label %bb0
+    i8 -64, label %bb1 i8 -63, label %bb1 i8 -62, label %bb1 i8 -61, label %bb1
+    i8 -60, label %bb1 i8 -59, label %bb1 i8 -58, label %bb1 i8 -57, label %bb1
+    i8 -56, label %bb1 i8 -55, label %bb1 i8 -54, label %bb1 i8 -53, label %bb1
+    i8 -52, label %bb1 i8 -51, label %bb1 i8 -50, label %bb1 i8 -49, label %bb1
+    i8 -48, label %bb1 i8 -47, label %bb1 i8 -46, label %bb1 i8 -45, label %bb1
+    i8 -44, label %bb1 i8 -43, label %bb1 i8 -42, label %bb1 i8 -41, label %bb1
+    i8 -40, label %bb1 i8 -39, label %bb1 i8 -38, label %bb1 i8 -37, label %bb1
+    i8 -36, label %bb1 i8 -35, label %bb1 i8 -34, label %bb1 i8 -33, label %bb1
+    i8 -32, label %bb2 i8 -31, label %bb2 i8 -30, label %bb2 i8 -29, label %bb2
+    i8 -28, label %bb2 i8 -27, label %bb2 i8 -26, label %bb2 i8 -25, label %bb2
+    i8 -24, label %bb2 i8 -23, label %bb2 i8 -22, label %bb2 i8 -21, label %bb2
+    i8 -20, label %bb2 i8 -19, label %bb2 i8 -18, label %bb2 i8 -17, label %bb2
+    i8 -16, label %bb3 i8 -15, label %bb3 i8 -14, label %bb3 i8 -13, label %bb3
+    i8 -12, label %bb3 i8 -11, label %bb3 i8 -10, label %bb3 i8 -9, label %bb3
+  ]
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+bb2: tail call void @g(i32 1) br label %return
+bb3: tail call void @g(i32 1) br label %return
+return: ret void
+
+; Don't infloop on jump tables where the upper bound is the max value of the
+; input type (in this case 127).
+; CHECK-LABEL: int_max_table_cluster
+; CHECK: jmpq *.LJTI
+}
+
+
+define void @bt_order_by_weight(i32 %x) {
+entry:
+  switch i32 %x, label %return [
+    i32 0, label %bb0
+    i32 3, label %bb0
+    i32 6, label %bb0
+    i32 1, label %bb1
+    i32 4, label %bb1
+    i32 7, label %bb1
+    i32 2, label %bb2
+    i32 5, label %bb2
+    i32 8, label %bb2
+    i32 9, label %bb2
+  ], !prof !1
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+bb2: tail call void @g(i32 2) br label %return
+return: ret void
+
+; Cases 1,4,7 have a very large branch weight (which shouldn't overflow), so
+; their bit test should come first. 0,3,6 and 2,5,8,9 both have a weight of 12,
+; but the latter set has more cases, so should be tested for earlier.
+
+; CHECK-LABEL: bt_order_by_weight
+; 146 = 2^1 + 2^4 + 2^7
+; CHECK: movl $146
+; CHECK: btl
+; 292 = 2^2 + 2^5 + 2^8 + 2^9
+; CHECK: movl $804
+; CHECK: btl
+; 73 = 2^0 + 2^3 + 2^6
+; CHECK: movl $73
+; CHECK: btl
+}
+
+!1 = !{!"branch_weights",
+       ; Default:
+       i32 1,
+       ; Cases 0,3,6:
+       i32 4, i32 4, i32 4,
+       ; Cases 1,4,7:
+       i32 4294967295, i32 2, i32 4294967295,
+       ; Cases 2,5,8,9:
+       i32 3, i32 3, i32 3, i32 3}
+
+define void @order_by_weight_and_fallthrough(i32 %x) {
+entry:
+  switch i32 %x, label %return [
+    i32 100, label %bb1
+    i32 200, label %bb0
+    i32 300, label %bb0
+  ], !prof !2
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+return: ret void
+
+; Case 200 has the highest weight and should come first. 100 and 300 have the
+; same weight, but 300 goes to the 'next' block, so should be last.
+; CHECK-LABEL: order_by_weight_and_fallthrough
+; CHECK: cmpl $200
+; CHECK: cmpl $100
+; CHECK: cmpl $300
+}
+
+!2 = !{!"branch_weights",
+       ; Default:
+       i32 1,
+       ; Case 100:
+       i32 10,
+       ; Case 200:
+       i32 1000,
+       ; Case 300:
+       i32 10}
+
+
+define void @zero_weight_tree(i32 %x) {
+entry:
+  switch i32 %x, label %return [
+    i32 0,  label %bb0
+    i32 10, label %bb1
+    i32 20, label %bb2
+    i32 30, label %bb3
+    i32 40, label %bb4
+    i32 50, label %bb5
+  ], !prof !3
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+bb2: tail call void @g(i32 2) br label %return
+bb3: tail call void @g(i32 3) br label %return
+bb4: tail call void @g(i32 4) br label %return
+bb5: tail call void @g(i32 5) br label %return
+return: ret void
+
+; Make sure to pick a pivot in the middle also with zero-weight cases.
+; CHECK-LABEL: zero_weight_tree
+; CHECK-NOT: cmpl
+; CHECK: cmpl $29
+}
+
+!3 = !{!"branch_weights", i32 1, i32 10, i32 0, i32 0, i32 0, i32 0, i32 10}
+
+
+define void @left_leaning_weight_balanced_tree(i32 %x) {
+entry:
+  switch i32 %x, label %return [
+    i32 0,  label %bb0
+    i32 10, label %bb1
+    i32 20, label %bb2
+    i32 30, label %bb3
+    i32 40, label %bb4
+    i32 50, label %bb5
+  ], !prof !4
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+bb2: tail call void @g(i32 2) br label %return
+bb3: tail call void @g(i32 3) br label %return
+bb4: tail call void @g(i32 4) br label %return
+bb5: tail call void @g(i32 5) br label %return
+return: ret void
+
+; To balance the tree by weight, the pivot is shifted to the right, moving hot
+; cases closer to the root.
+; CHECK-LABEL: left_leaning_weight_balanced_tree
+; CHECK-NOT: cmpl
+; CHECK: cmpl $39
+}
+
+!4 = !{!"branch_weights", i32 1, i32 10, i32 1, i32 1, i32 1, i32 10, i32 10}
+
+
+define void @jump_table_affects_balance(i32 %x) {
+entry:
+  switch i32 %x, label %return [
+    ; Jump table:
+    i32 0,  label %bb0
+    i32 1,  label %bb1
+    i32 2,  label %bb2
+    i32 3,  label %bb3
+
+    i32 100, label %bb0
+    i32 200, label %bb1
+    i32 300, label %bb2
+  ]
+bb0: tail call void @g(i32 0) br label %return
+bb1: tail call void @g(i32 1) br label %return
+bb2: tail call void @g(i32 2) br label %return
+bb3: tail call void @g(i32 3) br label %return
+return: ret void
+
+; CHECK-LABEL: jump_table_affects_balance
+; If the tree were balanced based on number of clusters, {0-3,100} would go on
+; the left and {200,300} on the right. However, the jump table weights as much
+; as its components, so 100 is selected as the pivot.
+; CHECK-NOT: cmpl
+; CHECK: cmpl $99
+}
diff --git a/test/CodeGen/X86/tail-call-win64.ll b/test/CodeGen/X86/tail-call-win64.ll
new file mode 100644
index 000000000000..fb10d5d2a24a
--- /dev/null
+++ b/test/CodeGen/X86/tail-call-win64.ll
@@ -0,0 +1,36 @@
+; RUN: llc -mtriple=x86_64-windows -show-mc-encoding < %s | FileCheck %s
+
+; The Win64 ABI wants tail jmps to use a REX_W prefix so it can distinguish
+; in-function jumps from function exiting jumps.
+
+define void @tail_jmp_reg(i32, i32, void ()* %fptr) {
+  tail call void () %fptr()
+  ret void
+}
+
+; Check that we merge the REX prefixes into 0x49 instead of 0x48, 0x41.
+
+; CHECK-LABEL: tail_jmp_reg:
+; CHECK: rex64 jmpq *%r8
+; CHECK: 	encoding: [0x49,0xff,0xe0]
+
+declare void @tail_tgt()
+
+define void @tail_jmp_imm() {
+  tail call void @tail_tgt()
+  ret void
+}
+
+; CHECK-LABEL: tail_jmp_imm:
+; CHECK: rex64 jmp tail_tgt
+
+@g_fptr = global void ()* @tail_tgt
+
+define void @tail_jmp_mem() {
+  %fptr = load void ()*, void ()** @g_fptr
+  tail call void () %fptr()
+  ret void
+}
+
+; CHECK-LABEL: tail_jmp_mem:
+; CHECK: rex64 jmpq *g_fptr(%rip)
diff --git a/test/CodeGen/X86/tail-dup-addr.ll b/test/CodeGen/X86/tail-dup-addr.ll
index c68a8c6bf845..3e5c8c8dbc3f 100644
--- a/test/CodeGen/X86/tail-dup-addr.ll
+++ b/test/CodeGen/X86/tail-dup-addr.ll
@@ -10,7 +10,7 @@
 
 define void @foo() noreturn nounwind uwtable ssp {
 entry:
-  %tmp = load i32* @a, align 4
+  %tmp = load i32, i32* @a, align 4
   %foo = icmp eq i32 0, %tmp
   br i1 %foo, label %sw.bb, label %sw.default
 
diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll
index 73d93ff993c6..f590176d9815 100644
--- a/test/CodeGen/X86/tail-opts.ll
+++ b/test/CodeGen/X86/tail-opts.ll
@@ -126,12 +126,12 @@ altret:
 
 define i1 @dont_merge_oddly(float* %result) nounwind {
 entry:
-  %tmp4 = getelementptr float* %result, i32 2
-  %tmp5 = load float* %tmp4, align 4
-  %tmp7 = getelementptr float* %result, i32 4
-  %tmp8 = load float* %tmp7, align 4
-  %tmp10 = getelementptr float* %result, i32 6
-  %tmp11 = load float* %tmp10, align 4
+  %tmp4 = getelementptr float, float* %result, i32 2
+  %tmp5 = load float, float* %tmp4, align 4
+  %tmp7 = getelementptr float, float* %result, i32 4
+  %tmp8 = load float, float* %tmp7, align 4
+  %tmp10 = getelementptr float, float* %result, i32 6
+  %tmp11 = load float, float* %tmp10, align 4
   %tmp12 = fcmp olt float %tmp8, %tmp11
   br i1 %tmp12, label %bb, label %bb21
 
@@ -179,7 +179,7 @@ bb30:
 
 define fastcc void @c_expand_expr_stmt(%union.tree_node* %expr) nounwind {
 entry:
-  %tmp4 = load i8* null, align 8                  ; <i8> [#uses=3]
+  %tmp4 = load i8, i8* null, align 8                  ; <i8> [#uses=3]
   switch i8 %tmp4, label %bb3 [
     i8 18, label %bb
   ]
@@ -199,9 +199,9 @@ bb2.i:                                            ; preds = %bb
   br label %bb3
 
 lvalue_p.exit:                                    ; preds = %bb.i
-  %tmp21 = load %union.tree_node** null, align 8  ; <%union.tree_node*> [#uses=3]
-  %tmp22 = getelementptr inbounds %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 0 ; <i8*> [#uses=1]
-  %tmp23 = load i8* %tmp22, align 8               ; <i8> [#uses=1]
+  %tmp21 = load %union.tree_node*, %union.tree_node** null, align 8  ; <%union.tree_node*> [#uses=3]
+  %tmp22 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 0 ; <i8*> [#uses=1]
+  %tmp23 = load i8, i8* %tmp22, align 8               ; <i8> [#uses=1]
   %tmp24 = zext i8 %tmp23 to i32                  ; <i32> [#uses=1]
   switch i32 %tmp24, label %lvalue_p.exit4 [
     i32 0, label %bb2.i3
@@ -209,11 +209,11 @@ lvalue_p.exit:                                    ; preds = %bb.i
   ]
 
 bb.i1:                                            ; preds = %lvalue_p.exit
-  %tmp25 = getelementptr inbounds %union.tree_node* %tmp21, i64 0, i32 0, i32 2 ; <i32*> [#uses=1]
+  %tmp25 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp21, i64 0, i32 0, i32 2 ; <i32*> [#uses=1]
   %tmp26 = bitcast i32* %tmp25 to %union.tree_node** ; <%union.tree_node**> [#uses=1]
-  %tmp27 = load %union.tree_node** %tmp26, align 8 ; <%union.tree_node*> [#uses=2]
-  %tmp28 = getelementptr inbounds %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
-  %tmp29 = load i8* %tmp28, align 8               ; <i8> [#uses=1]
+  %tmp27 = load %union.tree_node*, %union.tree_node** %tmp26, align 8 ; <%union.tree_node*> [#uses=2]
+  %tmp28 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
+  %tmp29 = load i8, i8* %tmp28, align 8               ; <i8> [#uses=1]
   %tmp30 = zext i8 %tmp29 to i32                  ; <i32> [#uses=1]
   switch i32 %tmp30, label %lvalue_p.exit4 [
     i32 0, label %bb2.i.i2
@@ -226,22 +226,22 @@ bb.i.i:                                           ; preds = %bb.i1
   br label %lvalue_p.exit4
 
 bb2.i.i2:                                         ; preds = %bb.i1
-  %tmp35 = getelementptr inbounds %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1]
+  %tmp35 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1]
   %tmp36 = bitcast i8* %tmp35 to %union.tree_node** ; <%union.tree_node**> [#uses=1]
-  %tmp37 = load %union.tree_node** %tmp36, align 8 ; <%union.tree_node*> [#uses=1]
-  %tmp38 = getelementptr inbounds %union.tree_node* %tmp37, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
-  %tmp39 = load i8* %tmp38, align 8               ; <i8> [#uses=1]
+  %tmp37 = load %union.tree_node*, %union.tree_node** %tmp36, align 8 ; <%union.tree_node*> [#uses=1]
+  %tmp38 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp37, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
+  %tmp39 = load i8, i8* %tmp38, align 8               ; <i8> [#uses=1]
   switch i8 %tmp39, label %bb2 [
     i8 16, label %lvalue_p.exit4
     i8 23, label %lvalue_p.exit4
   ]
 
 bb2.i3:                                           ; preds = %lvalue_p.exit
-  %tmp40 = getelementptr inbounds %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1]
+  %tmp40 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1]
   %tmp41 = bitcast i8* %tmp40 to %union.tree_node** ; <%union.tree_node**> [#uses=1]
-  %tmp42 = load %union.tree_node** %tmp41, align 8 ; <%union.tree_node*> [#uses=1]
-  %tmp43 = getelementptr inbounds %union.tree_node* %tmp42, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
-  %tmp44 = load i8* %tmp43, align 8               ; <i8> [#uses=1]
+  %tmp42 = load %union.tree_node*, %union.tree_node** %tmp41, align 8 ; <%union.tree_node*> [#uses=1]
+  %tmp43 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp42, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
+  %tmp44 = load i8, i8* %tmp43, align 8               ; <i8> [#uses=1]
   switch i8 %tmp44, label %bb2 [
     i8 16, label %lvalue_p.exit4
     i8 23, label %lvalue_p.exit4
diff --git a/test/CodeGen/X86/tailcall-64.ll b/test/CodeGen/X86/tailcall-64.ll
index deab1dcc7eb9..9e054fea5b35 100644
--- a/test/CodeGen/X86/tailcall-64.ll
+++ b/test/CodeGen/X86/tailcall-64.ll
@@ -165,7 +165,7 @@ declare %struct.B* @testu()
 define %struct.A* @test_upcast() {
 entry:
   %A = tail call %struct.B* @testu()
-  %x = getelementptr inbounds %struct.B* %A, i32 0, i32 0
+  %x = getelementptr inbounds %struct.B, %struct.B* %A, i32 0, i32 0
   ret %struct.A* %x
 }
 
@@ -182,13 +182,13 @@ define { i64, i64 } @crash(i8* %this) {
 ; Check that we can fold an indexed load into a tail call instruction.
 ; CHECK: fold_indexed_load
 ; CHECK: leaq (%rsi,%rsi,4), %[[RAX:r..]]
-; CHECK: jmpq *16(%{{r..}},%[[RAX]],8)  # TAILCALL
+; CHECK: jmpq *16(%{{r..}},%[[RAX]],8)  ## TAILCALL
 %struct.funcs = type { i32 (i8*, i32*, i32)*, i32 (i8*)*, i32 (i8*)*, i32 (i8*, i32)*, i32 }
 @func_table = external global [0 x %struct.funcs]
 define void @fold_indexed_load(i8* %mbstr, i64 %idxprom) nounwind uwtable ssp {
 entry:
-  %dsplen = getelementptr inbounds [0 x %struct.funcs]* @func_table, i64 0, i64 %idxprom, i32 2
-  %x1 = load i32 (i8*)** %dsplen, align 8
+  %dsplen = getelementptr inbounds [0 x %struct.funcs], [0 x %struct.funcs]* @func_table, i64 0, i64 %idxprom, i32 2
+  %x1 = load i32 (i8*)*, i32 (i8*)** %dsplen, align 8
   %call = tail call i32 %x1(i8* %mbstr) nounwind
   ret void
 }
@@ -207,15 +207,15 @@ entry:
 ; }
 ;
 ; CHECK-LABEL: rdar12282281
-; CHECK: jmpq *%r11 # TAILCALL
+; CHECK: jmpq *%r11 ## TAILCALL
 @funcs = external constant [0 x i32 (i8*, ...)*]
 
 define i32 @rdar12282281(i32 %n) nounwind uwtable ssp {
 entry:
   %idxprom = sext i32 %n to i64
-  %arrayidx = getelementptr inbounds [0 x i32 (i8*, ...)*]* @funcs, i64 0, i64 %idxprom
-  %0 = load i32 (i8*, ...)** %arrayidx, align 8
-  %call = tail call i32 (i8*, ...)* %0(i8* null, i32 0, i32 0, i32 0, i32 0, i32 0) nounwind
+  %arrayidx = getelementptr inbounds [0 x i32 (i8*, ...)*], [0 x i32 (i8*, ...)*]* @funcs, i64 0, i64 %idxprom
+  %0 = load i32 (i8*, ...)*, i32 (i8*, ...)** %arrayidx, align 8
+  %call = tail call i32 (i8*, ...) %0(i8* null, i32 0, i32 0, i32 0, i32 0, i32 0) nounwind
   ret i32 %call
 }
 
diff --git a/test/CodeGen/X86/tailcall-fastisel.ll b/test/CodeGen/X86/tailcall-fastisel.ll
index 842ed25439f8..f69e75ca6c65 100644
--- a/test/CodeGen/X86/tailcall-fastisel.ll
+++ b/test/CodeGen/X86/tailcall-fastisel.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -tailcallopt -fast-isel -fast-isel-abort | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -tailcallopt -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 %0 = type { i64, i32, i8* }
 
@@ -11,7 +11,7 @@ fail:                                             ; preds = %entry
 
 define i32 @foo() nounwind {
 entry:
- %0 = tail call i32 (...)* @bar() nounwind       ; <i32> [#uses=1]
+ %0 = tail call i32 (...) @bar() nounwind       ; <i32> [#uses=1]
  ret i32 %0
 }
 
diff --git a/test/CodeGen/X86/tailcall-mem-intrinsics.ll b/test/CodeGen/X86/tailcall-mem-intrinsics.ll
new file mode 100644
index 000000000000..0e0ab5c478fc
--- /dev/null
+++ b/test/CodeGen/X86/tailcall-mem-intrinsics.ll
@@ -0,0 +1,31 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
+
+; CHECK-LABEL: tail_memcpy
+; CHECK: jmp memcpy
+define void @tail_memcpy(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 {
+entry:
+  tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: tail_memset
+; CHECK; jmp memmove
+define void @tail_memmove(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 {
+entry:
+  tail call void @llvm.memmove.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: tail_memset
+; CHECK: jmp memset
+define void @tail_memset(i8* nocapture %p, i8 %c, i32 %n) #0 {
+entry:
+  tail call void @llvm.memset.p0i8.i32(i8* %p, i8 %c, i32 %n, i32 1, i1 false)
+  ret void
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0
+declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0
+declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) #0
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/X86/tailcall-returndup-void.ll b/test/CodeGen/X86/tailcall-returndup-void.ll
index 2c39cb4468df..62c40164d798 100644
--- a/test/CodeGen/X86/tailcall-returndup-void.ll
+++ b/test/CodeGen/X86/tailcall-returndup-void.ll
@@ -7,7 +7,7 @@ declare ghccc void @sEH_info(i64* noalias nocapture, i64* noalias nocapture, i64
 
 define ghccc void @rBM_info(i64* noalias nocapture %Base_Arg, i64* noalias nocapture %Sp_Arg, i64* noalias nocapture %Hp_Arg, i64 %R1_Arg, i64 %R2_Arg, i64 %R3_Arg) nounwind align 8 {
 c263:
-  %ln265 = getelementptr inbounds i64* %Sp_Arg, i64 -2
+  %ln265 = getelementptr inbounds i64, i64* %Sp_Arg, i64 -2
   %ln266 = ptrtoint i64* %ln265 to i64
   %ln268 = icmp ult i64 %ln266, %R3_Arg
   br i1 %ln268, label %c26a, label %n26p
@@ -16,7 +16,7 @@ n26p:                                             ; preds = %c263
   br i1 icmp ne (i64 and (i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 7), i64 0), label %c1ZP.i, label %n1ZQ.i
 
 n1ZQ.i:                                           ; preds = %n26p
-  %ln1ZT.i = load i64* getelementptr inbounds ([0 x i64]* @sES_closure, i64 0, i64 0), align 8
+  %ln1ZT.i = load i64, i64* getelementptr inbounds ([0 x i64], [0 x i64]* @sES_closure, i64 0, i64 0), align 8
   %ln1ZU.i = inttoptr i64 %ln1ZT.i to void (i64*, i64*, i64*, i64, i64, i64)*
   tail call ghccc void %ln1ZU.i(i64* %Base_Arg, i64* %Sp_Arg, i64* %Hp_Arg, i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 %R3_Arg) nounwind
   br label %rBL_info.exit
@@ -29,8 +29,8 @@ rBL_info.exit:                                    ; preds = %c1ZP.i, %n1ZQ.i
   ret void
 
 c26a:                                             ; preds = %c263
-  %ln27h = getelementptr inbounds i64* %Base_Arg, i64 -2
-  %ln27j = load i64* %ln27h, align 8
+  %ln27h = getelementptr inbounds i64, i64* %Base_Arg, i64 -2
+  %ln27j = load i64, i64* %ln27h, align 8
   %ln27k = inttoptr i64 %ln27j to void (i64*, i64*, i64*, i64, i64, i64)*
   tail call ghccc void %ln27k(i64* %Base_Arg, i64* %Sp_Arg, i64* %Hp_Arg, i64 %R1_Arg, i64 %R2_Arg, i64 %R3_Arg) nounwind
   ret void
diff --git a/test/CodeGen/X86/tailcall-ri64.ll b/test/CodeGen/X86/tailcall-ri64.ll
index 914d8f7b8bc7..443d48868e54 100644
--- a/test/CodeGen/X86/tailcall-ri64.ll
+++ b/test/CodeGen/X86/tailcall-ri64.ll
@@ -16,9 +16,9 @@ define %vt* @_ZN4llvm9UnsetInit20convertInitializerToEPNS_5RecTyE(%class*
 %this, %vt* %Ty) align 2 {
 entry:
   %0 = bitcast %vt* %Ty to %vt* (%vt*, %class*)***
-  %vtable = load %vt* (%vt*, %class*)*** %0, align 8
-  %vfn = getelementptr inbounds %vt* (%vt*, %class*)** %vtable, i64 4
-  %1 = load %vt* (%vt*, %class*)** %vfn, align 8
+  %vtable = load %vt* (%vt*, %class*)**, %vt* (%vt*, %class*)*** %0, align 8
+  %vfn = getelementptr inbounds %vt* (%vt*, %class*)*, %vt* (%vt*, %class*)** %vtable, i64 4
+  %1 = load %vt* (%vt*, %class*)*, %vt* (%vt*, %class*)** %vfn, align 8
   %call = tail call %vt* %1(%vt* %Ty, %class* %this)
   ret %vt* %call
 }
diff --git a/test/CodeGen/X86/tailcallbyval.ll b/test/CodeGen/X86/tailcallbyval.ll
index 9a0b57c138c2..8a0113a645a3 100644
--- a/test/CodeGen/X86/tailcallbyval.ll
+++ b/test/CodeGen/X86/tailcallbyval.ll
@@ -5,8 +5,8 @@
 
 define  fastcc i32 @tailcallee(%struct.s* byval %a) nounwind {
 entry:
-        %tmp2 = getelementptr %struct.s* %a, i32 0, i32 0
-        %tmp3 = load i32* %tmp2
+        %tmp2 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 0
+        %tmp3 = load i32, i32* %tmp2
         ret i32 %tmp3
 ; CHECK: tailcallee
 ; CHECK: movl 4(%esp), %eax
diff --git a/test/CodeGen/X86/tailcallbyval64.ll b/test/CodeGen/X86/tailcallbyval64.ll
index 75a6d874da37..9df1470c67f1 100644
--- a/test/CodeGen/X86/tailcallbyval64.ll
+++ b/test/CodeGen/X86/tailcallbyval64.ll
@@ -35,8 +35,8 @@ declare  fastcc i64 @tailcallee(%struct.s* byval %a, i64 %val, i64 %val2, i64 %v
 
 define  fastcc i64 @tailcaller(i64 %b, %struct.s* byval %a) {
 entry:
-        %tmp2 = getelementptr %struct.s* %a, i32 0, i32 1
-        %tmp3 = load i64* %tmp2, align 8
+        %tmp2 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 1
+        %tmp3 = load i64, i64* %tmp2, align 8
         %tmp4 = tail call fastcc i64 @tailcallee(%struct.s* byval %a , i64 %tmp3, i64 %b, i64 7, i64 13, i64 17)
         ret i64 %tmp4
 }
diff --git a/test/CodeGen/X86/tailcallstack64.ll b/test/CodeGen/X86/tailcallstack64.ll
index bff5f9924f66..158b777fe1fb 100644
--- a/test/CodeGen/X86/tailcallstack64.ll
+++ b/test/CodeGen/X86/tailcallstack64.ll
@@ -12,9 +12,9 @@
 ; Add %in1 %p1 to a different temporary register (%eax).
 ; CHECK: addl {{%edi|%ecx}}, [[R1]]
 ; Move param %in2 to stack.
-; CHECK: movl  [[R2]], [[A1]](%rsp)
+; CHECK-DAG: movl  [[R2]], [[A1]](%rsp)
 ; Move result of addition to stack.
-; CHECK: movl  [[R1]], [[A2]](%rsp)
+; CHECK-DAG: movl  [[R1]], [[A2]](%rsp)
 ; Eventually, do a TAILCALL
 ; CHECK: TAILCALL
 
diff --git a/test/CodeGen/X86/tbm-intrinsics-x86_64.ll b/test/CodeGen/X86/tbm-intrinsics-x86_64.ll
index 1beee72dfd0a..12218cc8ec4a 100644
--- a/test/CodeGen/X86/tbm-intrinsics-x86_64.ll
+++ b/test/CodeGen/X86/tbm-intrinsics-x86_64.ll
@@ -16,7 +16,7 @@ entry:
   ; CHECK-LABEL: test_x86_tbm_bextri_u32_m:
   ; CHECK-NOT: mov
   ; CHECK: bextr $
-  %tmp1 = load i32* %a, align 4
+  %tmp1 = load i32, i32* %a, align 4
   %0 = tail call i32 @llvm.x86.tbm.bextri.u32(i32 %tmp1, i32 2814)
   ret i32 %0
 }
@@ -37,7 +37,7 @@ entry:
   ; CHECK-LABEL: test_x86_tbm_bextri_u64_m:
   ; CHECK-NOT: mov
   ; CHECK: bextr $
-  %tmp1 = load i64* %a, align 8
+  %tmp1 = load i64, i64* %a, align 8
   %0 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %tmp1, i64 2814)
   ret i64 %0
 }
diff --git a/test/CodeGen/X86/tbm_patterns.ll b/test/CodeGen/X86/tbm_patterns.ll
index 79eea10af3ae..80d36d5af4d2 100644
--- a/test/CodeGen/X86/tbm_patterns.ll
+++ b/test/CodeGen/X86/tbm_patterns.ll
@@ -15,7 +15,7 @@ entry:
   ; CHECK-LABEL: test_x86_tbm_bextri_u32_m:
   ; CHECK-NOT: mov
   ; CHECK: bextr $
-  %0 = load i32* %a
+  %0 = load i32, i32* %a
   %1 = lshr i32 %0, 4
   %2 = and i32 %1, 4095
   ret i32 %2
@@ -36,7 +36,7 @@ entry:
   ; CHECK-LABEL: test_x86_tbm_bextri_u64_m:
   ; CHECK-NOT: mov
   ; CHECK: bextr $
-  %0 = load i64* %a
+  %0 = load i64, i64* %a
   %1 = lshr i64 %0, 4
   %2 = and i64 %1, 4095
   ret i64 %2
diff --git a/test/CodeGen/X86/test-shrink-bug.ll b/test/CodeGen/X86/test-shrink-bug.ll
index 64631ea5fc9b..1bb1e6384832 100644
--- a/test/CodeGen/X86/test-shrink-bug.ll
+++ b/test/CodeGen/X86/test-shrink-bug.ll
@@ -14,7 +14,7 @@ declare i32 @func_16(i8 signext %p_19, i32 %p_20) nounwind
 
 define i32 @func_35(i64 %p_38) nounwind ssp {
 entry:
-  %tmp = load i8* @g_14                           ; <i8> [#uses=2]
+  %tmp = load i8, i8* @g_14                           ; <i8> [#uses=2]
   %conv = zext i8 %tmp to i32                     ; <i32> [#uses=1]
   %cmp = icmp sle i32 1, %conv                    ; <i1> [#uses=1]
   %conv2 = zext i1 %cmp to i32                    ; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/testl-commute.ll b/test/CodeGen/X86/testl-commute.ll
index bf6debf17542..a9a9e581d995 100644
--- a/test/CodeGen/X86/testl-commute.ll
+++ b/test/CodeGen/X86/testl-commute.ll
@@ -13,8 +13,8 @@ define i32 @test(i32* %P, i32* %G) nounwind {
 ; CHECK: ret
 
 entry:
-	%0 = load i32* %P, align 4		; <i32> [#uses=3]
-	%1 = load i32* %G, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* %P, align 4		; <i32> [#uses=3]
+	%1 = load i32, i32* %G, align 4		; <i32> [#uses=1]
 	%2 = and i32 %1, %0		; <i32> [#uses=1]
 	%3 = icmp eq i32 %2, 0		; <i1> [#uses=1]
 	br i1 %3, label %bb1, label %bb
@@ -34,8 +34,8 @@ define i32 @test2(i32* %P, i32* %G) nounwind {
 ; CHECK: ret
 
 entry:
-	%0 = load i32* %P, align 4		; <i32> [#uses=3]
-	%1 = load i32* %G, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* %P, align 4		; <i32> [#uses=3]
+	%1 = load i32, i32* %G, align 4		; <i32> [#uses=1]
 	%2 = and i32 %0, %1		; <i32> [#uses=1]
 	%3 = icmp eq i32 %2, 0		; <i1> [#uses=1]
 	br i1 %3, label %bb1, label %bb
@@ -55,8 +55,8 @@ define i32 @test3(i32* %P, i32* %G) nounwind {
 ; CHECK: ret
 
 entry:
-	%0 = load i32* %P, align 4		; <i32> [#uses=3]
-	%1 = load i32* %G, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* %P, align 4		; <i32> [#uses=3]
+	%1 = load i32, i32* %G, align 4		; <i32> [#uses=1]
 	%2 = and i32 %0, %1		; <i32> [#uses=1]
 	%3 = icmp eq i32 %2, 0		; <i1> [#uses=1]
 	br i1 %3, label %bb1, label %bb
diff --git a/test/CodeGen/X86/this-return-64.ll b/test/CodeGen/X86/this-return-64.ll
index 4e6be71238ab..df8f416c4075 100644
--- a/test/CodeGen/X86/this-return-64.ll
+++ b/test/CodeGen/X86/this-return-64.ll
@@ -16,7 +16,7 @@ define %struct.C* @C_ctor(%struct.C* %this, i32 %y) {
 entry:
 ; CHECK-LABEL: C_ctor:
 ; CHECK: jmp     B_ctor                  # TAILCALL
-  %0 = getelementptr inbounds %struct.C* %this, i64 0, i32 0
+  %0 = getelementptr inbounds %struct.C, %struct.C* %this, i64 0, i32 0
   %call = tail call %struct.B* @B_ctor(%struct.B* %0, i32 %y)
   ret %struct.C* %this
 }
@@ -25,7 +25,7 @@ define %struct.C* @C_ctor_nothisret(%struct.C* %this, i32 %y) {
 entry:
 ; CHECK-LABEL: C_ctor_nothisret:
 ; CHECK-NOT: jmp     B_ctor_nothisret
-  %0 = getelementptr inbounds %struct.C* %this, i64 0, i32 0
+  %0 = getelementptr inbounds %struct.C, %struct.C* %this, i64 0, i32 0
   %call = tail call %struct.B* @B_ctor_nothisret(%struct.B* %0, i32 %y)
   ret %struct.C* %this
 }
@@ -39,7 +39,7 @@ entry:
 ; CHECK: jmp     B_ctor                  # TAILCALL
   %0 = bitcast %struct.D* %this to %struct.A*
   %call = tail call %struct.A* @A_ctor(%struct.A* %0)
-  %1 = getelementptr inbounds %struct.D* %this, i64 0, i32 0
+  %1 = getelementptr inbounds %struct.D, %struct.D* %this, i64 0, i32 0
   %call2 = tail call %struct.B* @B_ctor(%struct.B* %1, i32 %y)
 ; (this next line would never be generated by Clang, actually)
   %2 = bitcast %struct.A* %call to %struct.D*
@@ -55,7 +55,7 @@ entry:
 ; CHECK-NOT: jmp     B_ctor_nothisret
   %0 = bitcast %struct.D* %this to %struct.A*
   %call = tail call %struct.A* @A_ctor_nothisret(%struct.A* %0)
-  %1 = getelementptr inbounds %struct.D* %this, i64 0, i32 0
+  %1 = getelementptr inbounds %struct.D, %struct.D* %this, i64 0, i32 0
   %call2 = tail call %struct.B* @B_ctor_nothisret(%struct.B* %1, i32 %y)
 ; (this next line would never be generated by Clang, actually)
   %2 = bitcast %struct.A* %call to %struct.D*
@@ -69,7 +69,7 @@ entry:
 ; CHECK: callq   B_ctor
 ; CHECK: movq    [[SAVETHIS]], %rcx
 ; CHECK: jmp     B_ctor                  # TAILCALL
-  %b = getelementptr inbounds %struct.E* %this, i64 0, i32 0
+  %b = getelementptr inbounds %struct.E, %struct.E* %this, i64 0, i32 0
   %call = tail call %struct.B* @B_ctor(%struct.B* %b, i32 %x)
   %call4 = tail call %struct.B* @B_ctor(%struct.B* %b, i32 %x)
   ret %struct.E* %this
@@ -82,7 +82,7 @@ entry:
 ; CHECK: callq   B_ctor_nothisret
 ; CHECK: movq    [[SAVETHIS]], %rcx
 ; CHECK-NOT: jmp     B_ctor_nothisret
-  %b = getelementptr inbounds %struct.E* %this, i64 0, i32 0
+  %b = getelementptr inbounds %struct.E, %struct.E* %this, i64 0, i32 0
   %call = tail call %struct.B* @B_ctor_nothisret(%struct.B* %b, i32 %x)
   %call4 = tail call %struct.B* @B_ctor_nothisret(%struct.B* %b, i32 %x)
   ret %struct.E* %this
diff --git a/test/CodeGen/X86/tls-addr-non-leaf-function.ll b/test/CodeGen/X86/tls-addr-non-leaf-function.ll
index ec47232059f8..b9cab65465b8 100644
--- a/test/CodeGen/X86/tls-addr-non-leaf-function.ll
+++ b/test/CodeGen/X86/tls-addr-non-leaf-function.ll
@@ -32,6 +32,6 @@ target triple = "x86_64-unknown-linux-gnu"
 
 @x = thread_local global i32 0
 define i32 @foo() "no-frame-pointer-elim-non-leaf" {
-  %a = load i32* @x, align 4
+  %a = load i32, i32* @x, align 4
   ret i32 %a
 }
diff --git a/test/CodeGen/X86/tls-local-dynamic.ll b/test/CodeGen/X86/tls-local-dynamic.ll
index 4841e52c5b0e..1f1b41a8a6d4 100644
--- a/test/CodeGen/X86/tls-local-dynamic.ll
+++ b/test/CodeGen/X86/tls-local-dynamic.ll
@@ -32,7 +32,7 @@ entry:
 
 
 if.else:
-  %0 = load i32* @x, align 4
+  %0 = load i32, i32* @x, align 4
   %cmp1 = icmp eq i32 %i, 2
   br i1 %cmp1, label %if.then2, label %return
 ; Now we call __tls_get_addr.
@@ -43,7 +43,7 @@ if.else:
 
 
 if.then2:
-  %1 = load i32* @y, align 4
+  %1 = load i32, i32* @y, align 4
   %add = add nsw i32 %1, %0
   br label %return
 ; This accesses TLS, but is dominated by the previous block,
diff --git a/test/CodeGen/X86/tls-pic.ll b/test/CodeGen/X86/tls-pic.ll
index 0c79da6667a1..805bc25c17b6 100644
--- a/test/CodeGen/X86/tls-pic.ll
+++ b/test/CodeGen/X86/tls-pic.ll
@@ -7,7 +7,7 @@
 
 define i32 @f1() {
 entry:
-	%tmp1 = load i32* @i
+	%tmp1 = load i32, i32* @i
 	ret i32 %tmp1
 }
 
@@ -39,7 +39,7 @@ entry:
 
 define i32 @f3() {
 entry:
-	%tmp1 = load i32* @i		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* @i		; <i32> [#uses=1]
 	ret i32 %tmp1
 }
 
@@ -68,8 +68,8 @@ entry:
 
 define i32 @f5() nounwind {
 entry:
-	%0 = load i32* @j, align 4
-	%1 = load i32* @k, align 4
+	%0 = load i32, i32* @j, align 4
+	%1 = load i32, i32* @k, align 4
 	%add = add nsw i32 %0, %1
 	ret i32 %add
 }
diff --git a/test/CodeGen/X86/tls-pie.ll b/test/CodeGen/X86/tls-pie.ll
index d1e09c2442f7..10fe1e94bbdc 100644
--- a/test/CodeGen/X86/tls-pie.ll
+++ b/test/CodeGen/X86/tls-pie.ll
@@ -15,7 +15,7 @@ define i32 @f1() {
 ; X64-NEXT: ret
 
 entry:
-	%tmp1 = load i32* @i
+	%tmp1 = load i32, i32* @i
 	ret i32 %tmp1
 }
 
@@ -49,7 +49,7 @@ define i32 @f3() {
 ; X64-NEXT: ret
 
 entry:
-	%tmp1 = load i32* @i2
+	%tmp1 = load i32, i32* @i2
 	ret i32 %tmp1
 }
 
diff --git a/test/CodeGen/X86/tls.ll b/test/CodeGen/X86/tls.ll
index 75e7fc4f6bb3..0f3d3adec4c3 100644
--- a/test/CodeGen/X86/tls.ll
+++ b/test/CodeGen/X86/tls.ll
@@ -12,6 +12,7 @@
 @i5 = external hidden thread_local global i32
 @s1 = thread_local global i16 15
 @b1 = thread_local global i8 0
+@b2 = thread_local(localexec) global i8 0
 
 define i32 @f1() {
 ; X32_LINUX-LABEL: f1:
@@ -40,7 +41,7 @@ define i32 @f1() {
 ; MINGW32-NEXT: retl
 
 entry:
-	%tmp1 = load i32* @i1
+	%tmp1 = load i32, i32* @i1
 	ret i32 %tmp1
 }
 
@@ -105,7 +106,7 @@ define i32 @f3() nounwind {
 ; MINGW32-NEXT: retl
 
 entry:
-	%tmp1 = load i32* @i2
+	%tmp1 = load i32, i32* @i2
 	ret i32 %tmp1
 }
 
@@ -168,7 +169,7 @@ define i32 @f5() nounwind {
 ; MINGW32-NEXT: retl
 
 entry:
-	%tmp1 = load i32* @i3
+	%tmp1 = load i32, i32* @i3
 	ret i32 %tmp1
 }
 
@@ -219,7 +220,7 @@ define i32 @f7() {
 ; MINGW32-NEXT: retl
 
 entry:
-	%tmp1 = load i32* @i4
+	%tmp1 = load i32, i32* @i4
 	ret i32 %tmp1
 }
 
@@ -258,7 +259,7 @@ define i32 @f9() {
 ; MINGW32-NEXT: retl
 
 entry:
-	%tmp1 = load i32* @i5
+	%tmp1 = load i32, i32* @i5
 	ret i32 %tmp1
 }
 
@@ -309,7 +310,7 @@ define i16 @f11() {
 ; MINGW32: retl
 
 entry:
-	%tmp1 = load i16* @s1
+	%tmp1 = load i16, i16* @s1
 	ret i16 %tmp1
 }
 
@@ -341,7 +342,7 @@ define i32 @f12() {
 
 
 entry:
-	%tmp1 = load i16* @s1
+	%tmp1 = load i16, i16* @s1
   %tmp2 = sext i16 %tmp1 to i32
 	ret i32 %tmp2
 }
@@ -373,7 +374,7 @@ define i8 @f13() {
 ; MINGW32-NEXT: retl
 
 entry:
-	%tmp1 = load i8* @b1
+	%tmp1 = load i8, i8* @b1
 	ret i8 %tmp1
 }
 
@@ -404,8 +405,36 @@ define i32 @f14() {
 ; MINGW32-NEXT: retl
 
 entry:
-	%tmp1 = load i8* @b1
+	%tmp1 = load i8, i8* @b1
   %tmp2 = sext i8 %tmp1 to i32
 	ret i32 %tmp2
 }
 
+define i8* @f15() {
+; X32_LINUX-LABEL: f15:
+; X32_LINUX:      movl %gs:0, %eax
+; X32_LINUX-NEXT: leal b2@NTPOFF(%eax), %eax
+; X32_LINUX-NEXT: ret
+; X64_LINUX-LABEL: f15:
+; X64_LINUX:      movq %fs:0, %rax
+; X64_LINUX-NEXT: leaq b2@TPOFF(%rax), %rax
+; X64_LINUX-NEXT: ret
+; X32_WIN-LABEL: f15:
+; X32_WIN:      movl %fs:__tls_array, %eax
+; X32_WIN-NEXT: movl (%eax), %eax
+; X32_WIN-NEXT: leal _b2@SECREL32(%eax), %eax
+; X32_WIN-NEXT: ret
+; X64_WIN-LABEL: f15:
+; X64_WIN:      movq %gs:88, %rax
+; X64_WIN-NEXT: movq (%rax), %rax
+; X64_WIN-NEXT: leaq b2@SECREL32(%rax), %rax
+; X64_WIN-NEXT: ret
+; MINGW32-LABEL: f15:
+; MINGW32:      movl %fs:44, %eax
+; MINGW32-NEXT: movl (%eax), %eax
+; MINGW32-NEXT: leal _b2@SECREL32(%eax), %eax
+; MINGW32-NEXT: ret
+entry:
+	ret i8* @b2
+}
+
diff --git a/test/CodeGen/X86/tlv-1.ll b/test/CodeGen/X86/tlv-1.ll
index 66e2f819ee24..5f017d31dbbf 100644
--- a/test/CodeGen/X86/tlv-1.ll
+++ b/test/CodeGen/X86/tlv-1.ll
@@ -7,7 +7,7 @@
 define void @main() nounwind ssp {
 ; CHECK-LABEL: main:
 entry:
-  call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds (%struct.A* @c, i32 0, i32 0, i32 0), i8 0, i64 60, i32 1, i1 false)
+  call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds (%struct.A, %struct.A* @c, i32 0, i32 0, i32 0), i8 0, i64 60, i32 1, i1 false)
   unreachable  
   ; CHECK: movq    _c@TLVP(%rip), %rdi
   ; CHECK-NEXT: callq   *(%rdi)
@@ -25,8 +25,8 @@ entry:
 ; CHECK: movq _b@TLVP(%rip),
 ; CHECK: callq *
 ; CHECK: subl (%rax), [[REGISTER]]
-  %0 = load i32* @a, align 4
-  %1 = load i32* @b, align 4
+  %0 = load i32, i32* @a, align 4
+  %1 = load i32, i32* @b, align 4
   %sub = sub nsw i32 %0, %1
   ret i32 %sub
 }
diff --git a/test/CodeGen/X86/trap.ll b/test/CodeGen/X86/trap.ll
index 149c667c8cb7..ca33f9e6b4e1 100644
--- a/test/CodeGen/X86/trap.ll
+++ b/test/CodeGen/X86/trap.ll
@@ -1,15 +1,25 @@
-; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
+; RUN: llc < %s -mtriple=i686-apple-darwin8 -mcpu=yonah | FileCheck %s -check-prefix=DARWIN
+; RUN: llc < %s -mtriple=i686-unknown-linux -mcpu=yonah | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=x86_64-scei-ps4 | FileCheck %s -check-prefix=PS4
 
-; CHECK-LABEL: test0:
-; CHECK: ud2
+; DARWIN-LABEL: test0:
+; DARWIN: ud2
+; LINUX-LABEL: test0:
+; LINUX: ud2
+; PS4-LABEL: test0:
+; PS4: ud2
 define i32 @test0() noreturn nounwind  {
 entry:
 	tail call void @llvm.trap( )
 	unreachable
 }
 
-; CHECK-LABEL: test1:
-; CHECK: int3
+; DARWIN-LABEL: test1:
+; DARWIN: int3
+; LINUX-LABEL: test1:
+; LINUX: int3
+; PS4-LABEL: test1:
+; PS4: int     $65
 define i32 @test1() noreturn nounwind  {
 entry:
 	tail call void @llvm.debugtrap( )
diff --git a/test/CodeGen/X86/trunc-ext-ld-st.ll b/test/CodeGen/X86/trunc-ext-ld-st.ll
index 8de6297906c7..8c60697d8032 100644
--- a/test/CodeGen/X86/trunc-ext-ld-st.ll
+++ b/test/CodeGen/X86/trunc-ext-ld-st.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mattr=+sse4.1 | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mattr=+sse4.1 | FileCheck %s
 
 ;CHECK-LABEL: load_2_i8:
 ; A single 16-bit load
@@ -10,7 +10,7 @@
 ;CHECK: ret
 
 define void @load_2_i8(<2 x i8>* %A)  {
-   %T = load <2 x i8>* %A
+   %T = load <2 x i8>, <2 x i8>* %A
    %G = add <2 x i8> %T, <i8 9, i8 7>
    store <2 x i8> %G, <2 x i8>* %A
    ret void
@@ -24,7 +24,7 @@ define void @load_2_i8(<2 x i8>* %A)  {
 ;CHECK: movd
 ;CHECK: ret
 define void @load_2_i16(<2 x i16>* %A)  {
-   %T = load <2 x i16>* %A
+   %T = load <2 x i16>, <2 x i16>* %A
    %G = add <2 x i16> %T, <i16 9, i16 7>
    store <2 x i16> %G, <2 x i16>* %A
    ret void
@@ -36,7 +36,7 @@ define void @load_2_i16(<2 x i16>* %A)  {
 ;CHECK: pshufd
 ;CHECK: ret
 define void @load_2_i32(<2 x i32>* %A)  {
-   %T = load <2 x i32>* %A
+   %T = load <2 x i32>, <2 x i32>* %A
    %G = add <2 x i32> %T, <i32 9, i32 7>
    store <2 x i32> %G, <2 x i32>* %A
    ret void
@@ -48,7 +48,7 @@ define void @load_2_i32(<2 x i32>* %A)  {
 ;CHECK: pshufb
 ;CHECK: ret
 define void @load_4_i8(<4 x i8>* %A)  {
-   %T = load <4 x i8>* %A
+   %T = load <4 x i8>, <4 x i8>* %A
    %G = add <4 x i8> %T, <i8 1, i8 4, i8 9, i8 7>
    store <4 x i8> %G, <4 x i8>* %A
    ret void
@@ -60,7 +60,7 @@ define void @load_4_i8(<4 x i8>* %A)  {
 ;CHECK: pshufb
 ;CHECK: ret
 define void @load_4_i16(<4 x i16>* %A)  {
-   %T = load <4 x i16>* %A
+   %T = load <4 x i16>, <4 x i16>* %A
    %G = add <4 x i16> %T, <i16 1, i16 4, i16 9, i16 7>
    store <4 x i16> %G, <4 x i16>* %A
    ret void
@@ -72,7 +72,7 @@ define void @load_4_i16(<4 x i16>* %A)  {
 ;CHECK: pshufb
 ;CHECK: ret
 define void @load_8_i8(<8 x i8>* %A)  {
-   %T = load <8 x i8>* %A
+   %T = load <8 x i8>, <8 x i8>* %A
    %G = add <8 x i8> %T, %T
    store <8 x i8> %G, <8 x i8>* %A
    ret void
diff --git a/test/CodeGen/X86/trunc-to-bool.ll b/test/CodeGen/X86/trunc-to-bool.ll
index 0ed634774ab3..3dd98eea7fa9 100644
--- a/test/CodeGen/X86/trunc-to-bool.ll
+++ b/test/CodeGen/X86/trunc-to-bool.ll
@@ -25,7 +25,7 @@ ret_false:
 ; CHECK: btl
 
 define i32 @test3(i8* %ptr) nounwind {
-    %val = load i8* %ptr
+    %val = load i8, i8* %ptr
     %tmp = trunc i8 %val to i1
     br i1 %tmp, label %cond_true, label %cond_false
 cond_true:
diff --git a/test/CodeGen/X86/twoaddr-coalesce-3.ll b/test/CodeGen/X86/twoaddr-coalesce-3.ll
new file mode 100644
index 000000000000..33c9d46f13c3
--- /dev/null
+++ b/test/CodeGen/X86/twoaddr-coalesce-3.ll
@@ -0,0 +1,84 @@
+; RUN: llc < %s -march=x86-64 -relocation-model=pic | FileCheck %s
+; This test is to ensure the TwoAddrInstruction pass chooses the proper operands to
+; merge and generates fewer mov insns.
+
+@M = common global i32 0, align 4
+@total = common global i32 0, align 4
+@g = common global i32 0, align 4
+
+; Function Attrs: nounwind uwtable
+define void @foo() {
+entry:
+  %0 = load i32, i32* @M, align 4
+  %cmp3 = icmp sgt i32 %0, 0
+  br i1 %cmp3, label %for.body.lr.ph, label %for.end
+
+for.body.lr.ph:                                   ; preds = %entry
+  %total.promoted = load i32, i32* @total, align 4
+  br label %for.body
+
+; Check that only one mov will be generated in the kernel loop.
+; CHECK-LABEL: foo:
+; CHECK: [[LOOP1:^[a-zA-Z0-9_.]+]]: {{#.*}} %for.body
+; CHECK-NOT: mov
+; CHECK: movl {{.*}}, [[REG1:%[a-z0-9]+]]
+; CHECK-NOT: mov
+; CHECK: shrl $31, [[REG1]]
+; CHECK-NOT: mov
+; CHECK: jl [[LOOP1]]
+for.body:                                         ; preds = %for.body.lr.ph, %for.body
+  %add5 = phi i32 [ %total.promoted, %for.body.lr.ph ], [ %add, %for.body ]
+  %i.04 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
+  %div = sdiv i32 %i.04, 2
+  %add = add nsw i32 %div, %add5
+  %inc = add nuw nsw i32 %i.04, 1
+  %cmp = icmp slt i32 %inc, %0
+  br i1 %cmp, label %for.body, label %for.cond.for.end_crit_edge
+
+for.cond.for.end_crit_edge:                       ; preds = %for.body
+  store i32 %add, i32* @total, align 4
+  br label %for.end
+
+for.end:                                          ; preds = %for.cond.for.end_crit_edge, %entry
+  ret void
+}
+
+; Function Attrs: nounwind uwtable
+define void @goo() {
+entry:
+  %0 = load i32, i32* @M, align 4
+  %cmp3 = icmp sgt i32 %0, 0
+  br i1 %cmp3, label %for.body.lr.ph, label %for.end
+
+for.body.lr.ph:                                   ; preds = %entry
+  %total.promoted = load i32, i32* @total, align 4
+  br label %for.body
+
+; Check that only two mov will be generated in the kernel loop.
+; CHECK-LABEL: goo:
+; CHECK: [[LOOP2:^[a-zA-Z0-9_.]+]]: {{#.*}} %for.body
+; CHECK-NOT: mov
+; CHECK: movl {{.*}}, [[REG2:%[a-z0-9]+]]
+; CHECK-NOT: mov
+; CHECK: shrl $31, [[REG2]]
+; CHECK-NOT: mov
+; CHECK: movl {{.*}}
+; CHECK: jl [[LOOP2]]
+for.body:                                         ; preds = %for.body.lr.ph, %for.body
+  %add5 = phi i32 [ %total.promoted, %for.body.lr.ph ], [ %add, %for.body ]
+  %i.04 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
+  %div = sdiv i32 %i.04, 2
+  %add = add nsw i32 %div, %add5
+  store volatile i32 %add, i32* @g, align 4
+  %inc = add nuw nsw i32 %i.04, 1
+  %cmp = icmp slt i32 %inc, %0
+  br i1 %cmp, label %for.body, label %for.cond.for.end_crit_edge
+
+for.cond.for.end_crit_edge:                       ; preds = %for.body
+  store i32 %add, i32* @total, align 4
+  br label %for.end
+
+for.end:                                          ; preds = %for.cond.for.end_crit_edge, %entry
+  ret void
+}
+
diff --git a/test/CodeGen/X86/twoaddr-coalesce.ll b/test/CodeGen/X86/twoaddr-coalesce.ll
index 6f6d6f2cd967..38685ec27c02 100644
--- a/test/CodeGen/X86/twoaddr-coalesce.ll
+++ b/test/CodeGen/X86/twoaddr-coalesce.ll
@@ -12,7 +12,7 @@ bb1:		; preds = %bb1, %bb1.thread
 	%0 = trunc i32 %i.0.reg2mem.0 to i8		; <i8> [#uses=1]
 	%1 = sdiv i8 %0, 2		; <i8> [#uses=1]
 	%2 = sext i8 %1 to i32		; <i32> [#uses=1]
-	%3 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), i32 %2) nounwind		; <i32> [#uses=0]
+	%3 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), i32 %2) nounwind		; <i32> [#uses=0]
 	%indvar.next = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=2]
 	%exitcond = icmp eq i32 %indvar.next, 258		; <i1> [#uses=1]
 	br i1 %exitcond, label %bb2, label %bb1
diff --git a/test/CodeGen/X86/twoaddr-pass-sink.ll b/test/CodeGen/X86/twoaddr-pass-sink.ll
index 9ca280627afe..9a98e4794f9e 100644
--- a/test/CodeGen/X86/twoaddr-pass-sink.ll
+++ b/test/CodeGen/X86/twoaddr-pass-sink.ll
@@ -8,20 +8,20 @@ entry:
 bb:		; preds = %bb, %entry
 	%skiplist_addr.0.rec = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]		; <i32> [#uses=3]
 	%vYp_addr.0.rec = shl i32 %skiplist_addr.0.rec, 3		; <i32> [#uses=3]
-	%vDct_addr.0 = getelementptr <2 x i64>* %vDct, i32 %vYp_addr.0.rec		; <<2 x i64>*> [#uses=1]
-	%vYp_addr.0 = getelementptr <2 x i64>* %vYp, i32 %vYp_addr.0.rec		; <<2 x i64>*> [#uses=1]
-	%skiplist_addr.0 = getelementptr i8* %skiplist, i32 %skiplist_addr.0.rec		; <i8*> [#uses=1]
+	%vDct_addr.0 = getelementptr <2 x i64>, <2 x i64>* %vDct, i32 %vYp_addr.0.rec		; <<2 x i64>*> [#uses=1]
+	%vYp_addr.0 = getelementptr <2 x i64>, <2 x i64>* %vYp, i32 %vYp_addr.0.rec		; <<2 x i64>*> [#uses=1]
+	%skiplist_addr.0 = getelementptr i8, i8* %skiplist, i32 %skiplist_addr.0.rec		; <i8*> [#uses=1]
 	%vDct_addr.0.sum43 = or i32 %vYp_addr.0.rec, 1		; <i32> [#uses=1]
-	%tmp7 = getelementptr <2 x i64>* %vDct, i32 %vDct_addr.0.sum43		; <<2 x i64>*> [#uses=1]
-	%tmp8 = load <2 x i64>* %tmp7, align 16		; <<2 x i64>> [#uses=1]
-	%tmp11 = load <2 x i64>* %vDct_addr.0, align 16		; <<2 x i64>> [#uses=1]
+	%tmp7 = getelementptr <2 x i64>, <2 x i64>* %vDct, i32 %vDct_addr.0.sum43		; <<2 x i64>*> [#uses=1]
+	%tmp8 = load <2 x i64>, <2 x i64>* %tmp7, align 16		; <<2 x i64>> [#uses=1]
+	%tmp11 = load <2 x i64>, <2 x i64>* %vDct_addr.0, align 16		; <<2 x i64>> [#uses=1]
 	%tmp13 = bitcast <2 x i64> %tmp8 to <8 x i16>		; <<8 x i16>> [#uses=1]
 	%tmp15 = bitcast <2 x i64> %tmp11 to <8 x i16>		; <<8 x i16>> [#uses=1]
 	%tmp16 = shufflevector <8 x i16> %tmp15, <8 x i16> %tmp13, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 >		; <<8 x i16>> [#uses=1]
 	%tmp26 = mul <8 x i16> %tmp25, %tmp16		; <<8 x i16>> [#uses=1]
 	%tmp27 = bitcast <8 x i16> %tmp26 to <2 x i64>		; <<2 x i64>> [#uses=1]
 	store <2 x i64> %tmp27, <2 x i64>* %vYp_addr.0, align 16
-	%tmp37 = load i8* %skiplist_addr.0, align 1		; <i8> [#uses=1]
+	%tmp37 = load i8, i8* %skiplist_addr.0, align 1		; <i8> [#uses=1]
 	%tmp38 = icmp eq i8 %tmp37, 0		; <i1> [#uses=1]
 	%indvar.next = add i32 %skiplist_addr.0.rec, 1		; <i32> [#uses=1]
 	br i1 %tmp38, label %return, label %bb
diff --git a/test/CodeGen/X86/uint64-to-float.ll b/test/CodeGen/X86/uint64-to-float.ll
index ca764e7568f3..a1074a6d6989 100644
--- a/test/CodeGen/X86/uint64-to-float.ll
+++ b/test/CodeGen/X86/uint64-to-float.ll
@@ -6,13 +6,13 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10.0.0"
 
-; CHECK: testq %rdi, %rdi
+; CHECK: andl
+; CHECK-NEXT: testq %rdi, %rdi
 ; CHECK-NEXT: js LBB0_1
 ; CHECK: cvtsi2ss
 ; CHECK-NEXT: ret
 ; CHECK: LBB0_1
 ; CHECK: shrq
-; CHECK-NEXT: andq
 ; CHECK-NEXT: orq
 ; CHECK-NEXT: cvtsi2ss
 define float @test(i64 %a) {
diff --git a/test/CodeGen/X86/uint_to_fp-2.ll b/test/CodeGen/X86/uint_to_fp-2.ll
index e47f15453ed4..4b594f7c62ab 100644
--- a/test/CodeGen/X86/uint_to_fp-2.ll
+++ b/test/CodeGen/X86/uint_to_fp-2.ll
@@ -7,7 +7,7 @@ define float @test1(i32 %x) nounwind readnone {
 ; CHECK-NEXT:    pushl %eax
 ; CHECK-NEXT:    movsd .LCPI0_0, %xmm0
 ; CHECK-NEXT:    movd {{[0-9]+}}(%esp), %xmm1
-; CHECK-NEXT:    orps %xmm0, %xmm1
+; CHECK-NEXT:    orpd %xmm0, %xmm1
 ; CHECK-NEXT:    subsd %xmm0, %xmm1
 ; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    cvtsd2ss %xmm1, %xmm0
diff --git a/test/CodeGen/X86/umul-with-carry.ll b/test/CodeGen/X86/umul-with-carry.ll
index 56fdadbf937b..6435760e88a4 100644
--- a/test/CodeGen/X86/umul-with-carry.ll
+++ b/test/CodeGen/X86/umul-with-carry.ll
@@ -14,11 +14,11 @@ entry:
   br i1 %obit, label %carry, label %normal
 
 normal:
-  %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
+  %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
   ret i1 true
 
 carry:
-  %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+  %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
 }
 
diff --git a/test/CodeGen/X86/unaligned-32-byte-memops.ll b/test/CodeGen/X86/unaligned-32-byte-memops.ll
index 347f330d67ae..b337a80b84b3 100644
--- a/test/CodeGen/X86/unaligned-32-byte-memops.ll
+++ b/test/CodeGen/X86/unaligned-32-byte-memops.ll
@@ -20,7 +20,7 @@ define <8 x float> @load32bytes(<8 x float>* %Ap) {
   ; HASWELL: vmovups
   ; HASWELL: retq
 
-  %A = load <8 x float>* %Ap, align 16
+  %A = load <8 x float>, <8 x float>* %Ap, align 16
   ret <8 x float> %A
 }
 
@@ -48,56 +48,6 @@ define void @store32bytes(<8 x float> %A, <8 x float>* %P) {
 ; Merge two consecutive 16-byte subvector loads into a single 32-byte load
 ; if it's faster.
 
-declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i8)
-
-; Use the vinsertf128 intrinsic to model source code 
-; that explicitly uses AVX intrinsics.
-define <8 x float> @combine_16_byte_loads(<4 x float>* %ptr) {
-  ; CHECK-LABEL: combine_16_byte_loads
-
-  ; SANDYB: vmovups
-  ; SANDYB-NEXT: vinsertf128
-  ; SANDYB-NEXT: retq
-
-  ; BTVER2: vmovups
-  ; BTVER2-NEXT: retq
-
-  ; HASWELL: vmovups
-  ; HASWELL-NEXT: retq
-
-  %ptr2 = getelementptr inbounds <4 x float>* %ptr, i64 1
-  %v1 = load <4 x float>* %ptr, align 1
-  %v2 = load <4 x float>* %ptr2, align 1
-  %shuffle = shufflevector <4 x float> %v1, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
-  %v3 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %shuffle, <4 x float> %v2, i8 1)
-  ret <8 x float> %v3
-}
-
-; Swap the operands of the shufflevector and vinsertf128 to ensure that the
-; pattern still matches.
-define <8 x float> @combine_16_byte_loads_swap(<4 x float>* %ptr) {
-  ; CHECK-LABEL: combine_16_byte_loads_swap
-
-  ; SANDYB: vmovups
-  ; SANDYB-NEXT: vinsertf128
-  ; SANDYB-NEXT: retq
-
-  ; BTVER2: vmovups
-  ; BTVER2-NEXT: retq
-
-  ; HASWELL: vmovups
-  ; HASWELL-NEXT: retq
-
-  %ptr2 = getelementptr inbounds <4 x float>* %ptr, i64 1
-  %v1 = load <4 x float>* %ptr, align 1
-  %v2 = load <4 x float>* %ptr2, align 1
-  %shuffle = shufflevector <4 x float> %v2, <4 x float> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3>
-  %v3 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %shuffle, <4 x float> %v1, i8 0)
-  ret <8 x float> %v3
-}
-
-; Replace the vinsertf128 intrinsic with a shufflevector as might be
-; expected from auto-vectorized code.
 define <8 x float> @combine_16_byte_loads_no_intrinsic(<4 x float>* %ptr) {
   ; CHECK-LABEL: combine_16_byte_loads_no_intrinsic
 
@@ -111,9 +61,10 @@ define <8 x float> @combine_16_byte_loads_no_intrinsic(<4 x float>* %ptr) {
   ; HASWELL: vmovups
   ; HASWELL-NEXT: retq
 
-  %ptr2 = getelementptr inbounds <4 x float>* %ptr, i64 1
-  %v1 = load <4 x float>* %ptr, align 1
-  %v2 = load <4 x float>* %ptr2, align 1
+  %ptr1 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64 3
+  %ptr2 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64 4
+  %v1 = load <4 x float>, <4 x float>* %ptr1, align 1
+  %v2 = load <4 x float>, <4 x float>* %ptr2, align 1
   %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x float> %v3
 }
@@ -133,9 +84,10 @@ define <8 x float> @combine_16_byte_loads_no_intrinsic_swap(<4 x float>* %ptr) {
   ; HASWELL: vmovups
   ; HASWELL-NEXT: retq
 
-  %ptr2 = getelementptr inbounds <4 x float>* %ptr, i64 1
-  %v1 = load <4 x float>* %ptr, align 1
-  %v2 = load <4 x float>* %ptr2, align 1
+  %ptr1 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64 4
+  %ptr2 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64 5
+  %v1 = load <4 x float>, <4 x float>* %ptr1, align 1
+  %v2 = load <4 x float>, <4 x float>* %ptr2, align 1
   %v3 = shufflevector <4 x float> %v2, <4 x float> %v1, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
   ret <8 x float> %v3
 }
@@ -160,13 +112,14 @@ define <4 x i64> @combine_16_byte_loads_i64(<2 x i64>* %ptr, <4 x i64> %x) {
   ; BTVER2-NEXT: vinsertf128
   ; BTVER2-NEXT: retq
 
-  ; HASWELL: vmovdqu
-  ; HASWELL-NEXT: vpaddq
+  ; HASWELL-NOT: vextract
+  ; HASWELL: vpaddq
   ; HASWELL-NEXT: retq
 
-  %ptr2 = getelementptr inbounds <2 x i64>* %ptr, i64 1
-  %v1 = load <2 x i64>* %ptr, align 1
-  %v2 = load <2 x i64>* %ptr2, align 1
+  %ptr1 = getelementptr inbounds <2 x i64>, <2 x i64>* %ptr, i64 5
+  %ptr2 = getelementptr inbounds <2 x i64>, <2 x i64>* %ptr, i64 6
+  %v1 = load <2 x i64>, <2 x i64>* %ptr1, align 1
+  %v2 = load <2 x i64>, <2 x i64>* %ptr2, align 1
   %v3 = shufflevector <2 x i64> %v1, <2 x i64> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %v4 = add <4 x i64> %v3, %x
   ret <4 x i64> %v4
@@ -187,13 +140,14 @@ define <8 x i32> @combine_16_byte_loads_i32(<4 x i32>* %ptr, <8 x i32> %x) {
   ; BTVER2-NEXT: vinsertf128
   ; BTVER2-NEXT: retq
 
-  ; HASWELL: vmovdqu
-  ; HASWELL-NEXT: vpaddd
+  ; HASWELL-NOT: vextract
+  ; HASWELL: vpaddd
   ; HASWELL-NEXT: retq
 
-  %ptr2 = getelementptr inbounds <4 x i32>* %ptr, i64 1
-  %v1 = load <4 x i32>* %ptr, align 1
-  %v2 = load <4 x i32>* %ptr2, align 1
+  %ptr1 = getelementptr inbounds <4 x i32>, <4 x i32>* %ptr, i64 6
+  %ptr2 = getelementptr inbounds <4 x i32>, <4 x i32>* %ptr, i64 7
+  %v1 = load <4 x i32>, <4 x i32>* %ptr1, align 1
+  %v2 = load <4 x i32>, <4 x i32>* %ptr2, align 1
   %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   %v4 = add <8 x i32> %v3, %x
   ret <8 x i32> %v4
@@ -214,13 +168,14 @@ define <16 x i16> @combine_16_byte_loads_i16(<8 x i16>* %ptr, <16 x i16> %x) {
   ; BTVER2-NEXT: vinsertf128
   ; BTVER2-NEXT: retq
 
-  ; HASWELL: vmovdqu
-  ; HASWELL-NEXT: vpaddw
+  ; HASWELL-NOT: vextract
+  ; HASWELL: vpaddw
   ; HASWELL-NEXT: retq
 
-  %ptr2 = getelementptr inbounds <8 x i16>* %ptr, i64 1
-  %v1 = load <8 x i16>* %ptr, align 1
-  %v2 = load <8 x i16>* %ptr2, align 1
+  %ptr1 = getelementptr inbounds <8 x i16>, <8 x i16>* %ptr, i64 7
+  %ptr2 = getelementptr inbounds <8 x i16>, <8 x i16>* %ptr, i64 8
+  %v1 = load <8 x i16>, <8 x i16>* %ptr1, align 1
+  %v2 = load <8 x i16>, <8 x i16>* %ptr2, align 1
   %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %v4 = add <16 x i16> %v3, %x
   ret <16 x i16> %v4
@@ -241,13 +196,14 @@ define <32 x i8> @combine_16_byte_loads_i8(<16 x i8>* %ptr, <32 x i8> %x) {
   ; BTVER2-NEXT: vinsertf128
   ; BTVER2-NEXT: retq
 
-  ; HASWELL: vmovdqu
-  ; HASWELL-NEXT: vpaddb
+  ; HASWELL-NOT: vextract
+  ; HASWELL: vpaddb
   ; HASWELL-NEXT: retq
 
-  %ptr2 = getelementptr inbounds <16 x i8>* %ptr, i64 1
-  %v1 = load <16 x i8>* %ptr, align 1
-  %v2 = load <16 x i8>* %ptr2, align 1
+  %ptr1 = getelementptr inbounds <16 x i8>, <16 x i8>* %ptr, i64 8
+  %ptr2 = getelementptr inbounds <16 x i8>, <16 x i8>* %ptr, i64 9
+  %v1 = load <16 x i8>, <16 x i8>* %ptr1, align 1
+  %v2 = load <16 x i8>, <16 x i8>* %ptr2, align 1
   %v3 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   %v4 = add <32 x i8> %v3, %x
   ret <32 x i8> %v4
@@ -261,17 +217,18 @@ define <4 x double> @combine_16_byte_loads_double(<2 x double>* %ptr, <4 x doubl
   ; SANDYB-NEXT: vaddpd
   ; SANDYB-NEXT: retq
 
-  ; BTVER2: vmovupd
-  ; BTVER2-NEXT: vaddpd
+  ; BTVER2-NOT: vinsertf128
+  ; BTVER2: vaddpd
   ; BTVER2-NEXT: retq
 
-  ; HASWELL: vmovupd
+  ; HASWELL-NOT: vinsertf128
   ; HASWELL: vaddpd
   ; HASWELL-NEXT: retq
 
-  %ptr2 = getelementptr inbounds <2 x double>* %ptr, i64 1
-  %v1 = load <2 x double>* %ptr, align 1
-  %v2 = load <2 x double>* %ptr2, align 1
+  %ptr1 = getelementptr inbounds <2 x double>, <2 x double>* %ptr, i64 9
+  %ptr2 = getelementptr inbounds <2 x double>, <2 x double>* %ptr, i64 10
+  %v1 = load <2 x double>, <2 x double>* %ptr1, align 1
+  %v2 = load <2 x double>, <2 x double>* %ptr2, align 1
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %v4 = fadd <4 x double> %v3, %x
   ret <4 x double> %v4
diff --git a/test/CodeGen/X86/unaligned-load.ll b/test/CodeGen/X86/unaligned-load.ll
index d8fffbec4f0f..ffbbcff2e5d6 100644
--- a/test/CodeGen/X86/unaligned-load.ll
+++ b/test/CodeGen/X86/unaligned-load.ll
@@ -11,8 +11,8 @@ entry:
   br label %bb
 
 bb:                                               ; preds = %bb, %entry
-  %String2Loc9 = getelementptr inbounds [31 x i8]* %String2Loc, i64 0, i64 0
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %String2Loc9, i8* getelementptr inbounds ([31 x i8]* @.str3, i64 0, i64 0), i64 31, i32 1, i1 false)
+  %String2Loc9 = getelementptr inbounds [31 x i8], [31 x i8]* %String2Loc, i64 0, i64 0
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %String2Loc9, i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str3, i64 0, i64 0), i64 31, i32 1, i1 false)
   br label %bb
 
 return:                                           ; No predecessors!
diff --git a/test/CodeGen/X86/unaligned-spill-folding.ll b/test/CodeGen/X86/unaligned-spill-folding.ll
index 154ce9e324d6..33e2daf9dc1b 100644
--- a/test/CodeGen/X86/unaligned-spill-folding.ll
+++ b/test/CodeGen/X86/unaligned-spill-folding.ll
@@ -11,9 +11,9 @@ vector.ph:
 
 vector.body:
   %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %0 = getelementptr inbounds [32 x i32]* @arr, i32 0, i32 %index
+  %0 = getelementptr inbounds [32 x i32], [32 x i32]* @arr, i32 0, i32 %index
   %1 = bitcast i32* %0 to <4 x i32>*
-  %wide.load = load <4 x i32>* %1, align 16
+  %wide.load = load <4 x i32>, <4 x i32>* %1, align 16
   %2 = add nsw <4 x i32> %wide.load, <i32 10, i32 10, i32 10, i32 10>
   %3 = xor <4 x i32> %2, <i32 123345, i32 123345, i32 123345, i32 123345>
   %4 = add nsw <4 x i32> %3, <i32 112, i32 112, i32 112, i32 112>
diff --git a/test/CodeGen/X86/unknown-location.ll b/test/CodeGen/X86/unknown-location.ll
index 140121ba3035..c018a49d135e 100644
--- a/test/CodeGen/X86/unknown-location.ll
+++ b/test/CodeGen/X86/unknown-location.ll
@@ -8,7 +8,7 @@
 ; CHECK-NEXT:         .loc 1 0 0
 ;      CHECK:         cltd
 ; CHECK-NEXT:         idivl
-; CHECK-NEXT:         .loc 2 4 3
+; CHECK-NEXT:         .loc 1 4 3
 
 define i32 @foo(i32 %w, i32 %x, i32 %y, i32 %z) nounwind {
 entry:
@@ -21,16 +21,16 @@ entry:
 !llvm.dbg.cu = !{!3}
 !llvm.module.flags = !{!12}
 
-!0 = !{!"0x101\00x\001\000", !1, !2, !6} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00foo\00foo\00foo\001\000\001\000\006\000\000\001", !10, !2, !4, null, i32 (i32, i32, i32, i32)* @foo, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !10} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\0012\00producer\000\00\000\00\000", !10, !11, !11, !9, null, null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !10, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 1, arg: 0, scope: !1, file: !2, type: !6)
+!1 = !DISubprogram(name: "foo", linkageName: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !10, scope: !2, type: !4, function: i32 (i32, i32, i32, i32)* @foo)
+!2 = !DIFile(filename: "test.c", directory: "/dir")
+!3 = !DICompileUnit(language: DW_LANG_C99, producer: "producer", isOptimized: false, emissionKind: 0, file: !10, enums: !11, retainedTypes: !11, subprograms: !9)
+!4 = !DISubroutineType(types: !5)
 !5 = !{!6}
-!6 = !{!"0x24\00int\000\0032\0032\000\000\005", !10, !2} ; [ DW_TAG_base_type ]
-!7 = !{!"0xb\001\0030\000", !2, !1} ; [ DW_TAG_lexical_block ]
-!8 = !MDLocation(line: 4, column: 3, scope: !7)
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!7 = distinct !DILexicalBlock(line: 1, column: 30, file: !10, scope: !1)
+!8 = !DILocation(line: 4, column: 3, scope: !7)
 !9 = !{!1}
-!10 = !{!"test.c", !"/dir"}
-!11 = !{i32 0}
-!12 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !DIFile(filename: "test.c", directory: "/dir")
+!11 = !{}
+!12 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/CodeGen/X86/unwindraise.ll b/test/CodeGen/X86/unwindraise.ll
index 9bbe98043fd8..fb8319b63c2c 100644
--- a/test/CodeGen/X86/unwindraise.ll
+++ b/test/CodeGen/X86/unwindraise.ll
@@ -35,11 +35,11 @@ entry:
   %2 = bitcast %struct._Unwind_Context* %cur_context to i8*
   %3 = bitcast %struct._Unwind_Context* %this_context to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 240, i32 8, i1 false)
-  %personality = getelementptr inbounds %struct._Unwind_FrameState* %fs, i64 0, i32 6
-  %retaddr_column.i = getelementptr inbounds %struct._Unwind_FrameState* %fs, i64 0, i32 9
-  %flags.i.i.i.i = getelementptr inbounds %struct._Unwind_Context* %cur_context, i64 0, i32 5
-  %ra.i = getelementptr inbounds %struct._Unwind_Context* %cur_context, i64 0, i32 2
-  %exception_class = getelementptr inbounds %struct._Unwind_Exception* %exc, i64 0, i32 0
+  %personality = getelementptr inbounds %struct._Unwind_FrameState, %struct._Unwind_FrameState* %fs, i64 0, i32 6
+  %retaddr_column.i = getelementptr inbounds %struct._Unwind_FrameState, %struct._Unwind_FrameState* %fs, i64 0, i32 9
+  %flags.i.i.i.i = getelementptr inbounds %struct._Unwind_Context, %struct._Unwind_Context* %cur_context, i64 0, i32 5
+  %ra.i = getelementptr inbounds %struct._Unwind_Context, %struct._Unwind_Context* %cur_context, i64 0, i32 2
+  %exception_class = getelementptr inbounds %struct._Unwind_Exception, %struct._Unwind_Exception* %exc, i64 0, i32 0
   br label %while.body
 
 while.body:                                       ; preds = %uw_update_context.exit, %entry
@@ -50,12 +50,12 @@ while.body:                                       ; preds = %uw_update_context.e
   ]
 
 if.end3:                                          ; preds = %while.body
-  %4 = load i32 (i32, i32, i64, %struct._Unwind_Exception*, %struct._Unwind_Context*)** %personality, align 8
+  %4 = load i32 (i32, i32, i64, %struct._Unwind_Exception*, %struct._Unwind_Context*)*, i32 (i32, i32, i64, %struct._Unwind_Exception*, %struct._Unwind_Context*)** %personality, align 8
   %tobool = icmp eq i32 (i32, i32, i64, %struct._Unwind_Exception*, %struct._Unwind_Context*)* %4, null
   br i1 %tobool, label %if.end13, label %if.then4
 
 if.then4:                                         ; preds = %if.end3
-  %5 = load i64* %exception_class, align 8
+  %5 = load i64, i64* %exception_class, align 8
   %call6 = call i32 %4(i32 1, i32 1, i64 %5, %struct._Unwind_Exception* %exc, %struct._Unwind_Context* %cur_context)
   switch i32 %call6, label %do.end21.loopexit46 [
     i32 6, label %while.end
@@ -64,7 +64,7 @@ if.then4:                                         ; preds = %if.end3
 
 if.end13:                                         ; preds = %if.then4, %if.end3
   call fastcc void @uw_update_context_1(%struct._Unwind_Context* %cur_context, %struct._Unwind_FrameState* %fs)
-  %6 = load i64* %retaddr_column.i, align 8
+  %6 = load i64, i64* %retaddr_column.i, align 8
   %conv.i = trunc i64 %6 to i32
   %cmp.i.i.i = icmp slt i32 %conv.i, 18
   br i1 %cmp.i.i.i, label %cond.end.i.i.i, label %cond.true.i.i.i
@@ -76,18 +76,18 @@ cond.true.i.i.i:                                  ; preds = %if.end13
 cond.end.i.i.i:                                   ; preds = %if.end13
   %sext.i = shl i64 %6, 32
   %idxprom.i.i.i = ashr exact i64 %sext.i, 32
-  %arrayidx.i.i.i = getelementptr inbounds [18 x i8]* @dwarf_reg_size_table, i64 0, i64 %idxprom.i.i.i
-  %7 = load i8* %arrayidx.i.i.i, align 1
-  %arrayidx2.i.i.i = getelementptr inbounds %struct._Unwind_Context* %cur_context, i64 0, i32 0, i64 %idxprom.i.i.i
-  %8 = load i8** %arrayidx2.i.i.i, align 8
-  %9 = load i64* %flags.i.i.i.i, align 8
+  %arrayidx.i.i.i = getelementptr inbounds [18 x i8], [18 x i8]* @dwarf_reg_size_table, i64 0, i64 %idxprom.i.i.i
+  %7 = load i8, i8* %arrayidx.i.i.i, align 1
+  %arrayidx2.i.i.i = getelementptr inbounds %struct._Unwind_Context, %struct._Unwind_Context* %cur_context, i64 0, i32 0, i64 %idxprom.i.i.i
+  %8 = load i8*, i8** %arrayidx2.i.i.i, align 8
+  %9 = load i64, i64* %flags.i.i.i.i, align 8
   %and.i.i.i.i = and i64 %9, 4611686018427387904
   %tobool.i.i.i = icmp eq i64 %and.i.i.i.i, 0
   br i1 %tobool.i.i.i, label %if.end.i.i.i, label %land.lhs.true.i.i.i
 
 land.lhs.true.i.i.i:                              ; preds = %cond.end.i.i.i
-  %arrayidx4.i.i.i = getelementptr inbounds %struct._Unwind_Context* %cur_context, i64 0, i32 8, i64 %idxprom.i.i.i
-  %10 = load i8* %arrayidx4.i.i.i, align 1
+  %arrayidx4.i.i.i = getelementptr inbounds %struct._Unwind_Context, %struct._Unwind_Context* %cur_context, i64 0, i32 8, i64 %idxprom.i.i.i
+  %10 = load i8, i8* %arrayidx4.i.i.i, align 1
   %tobool6.i.i.i = icmp eq i8 %10, 0
   br i1 %tobool6.i.i.i, label %if.end.i.i.i, label %if.then.i.i.i
 
@@ -101,7 +101,7 @@ if.end.i.i.i:                                     ; preds = %land.lhs.true.i.i.i
 
 if.then10.i.i.i:                                  ; preds = %if.end.i.i.i
   %12 = bitcast i8* %8 to i64*
-  %13 = load i64* %12, align 8
+  %13 = load i64, i64* %12, align 8
   br label %uw_update_context.exit
 
 cond.true14.i.i.i:                                ; preds = %if.end.i.i.i
@@ -115,36 +115,36 @@ uw_update_context.exit:                           ; preds = %if.then10.i.i.i, %i
   br label %while.body
 
 while.end:                                        ; preds = %if.then4
-  %private_1 = getelementptr inbounds %struct._Unwind_Exception* %exc, i64 0, i32 2
+  %private_1 = getelementptr inbounds %struct._Unwind_Exception, %struct._Unwind_Exception* %exc, i64 0, i32 2
   store i64 0, i64* %private_1, align 8
-  %15 = load i8** %ra.i, align 8
+  %15 = load i8*, i8** %ra.i, align 8
   %16 = ptrtoint i8* %15 to i64
-  %private_2 = getelementptr inbounds %struct._Unwind_Exception* %exc, i64 0, i32 3
+  %private_2 = getelementptr inbounds %struct._Unwind_Exception, %struct._Unwind_Exception* %exc, i64 0, i32 3
   store i64 %16, i64* %private_2, align 8
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 240, i32 8, i1 false)
   %17 = bitcast %struct._Unwind_FrameState* %fs.i to i8*
   call void @llvm.lifetime.start(i64 -1, i8* %17)
-  %personality.i = getelementptr inbounds %struct._Unwind_FrameState* %fs.i, i64 0, i32 6
-  %retaddr_column.i22 = getelementptr inbounds %struct._Unwind_FrameState* %fs.i, i64 0, i32 9
+  %personality.i = getelementptr inbounds %struct._Unwind_FrameState, %struct._Unwind_FrameState* %fs.i, i64 0, i32 6
+  %retaddr_column.i22 = getelementptr inbounds %struct._Unwind_FrameState, %struct._Unwind_FrameState* %fs.i, i64 0, i32 9
   br label %while.body.i
 
 while.body.i:                                     ; preds = %uw_update_context.exit44, %while.end
   %call.i = call fastcc i32 @uw_frame_state_for(%struct._Unwind_Context* %cur_context, %struct._Unwind_FrameState* %fs.i)
-  %18 = load i8** %ra.i, align 8
+  %18 = load i8*, i8** %ra.i, align 8
   %19 = ptrtoint i8* %18 to i64
-  %20 = load i64* %private_2, align 8
+  %20 = load i64, i64* %private_2, align 8
   %cmp.i = icmp eq i64 %19, %20
   %cmp2.i = icmp eq i32 %call.i, 0
   br i1 %cmp2.i, label %if.end.i, label %do.end21
 
 if.end.i:                                         ; preds = %while.body.i
-  %21 = load i32 (i32, i32, i64, %struct._Unwind_Exception*, %struct._Unwind_Context*)** %personality.i, align 8
+  %21 = load i32 (i32, i32, i64, %struct._Unwind_Exception*, %struct._Unwind_Context*)*, i32 (i32, i32, i64, %struct._Unwind_Exception*, %struct._Unwind_Context*)** %personality.i, align 8
   %tobool.i = icmp eq i32 (i32, i32, i64, %struct._Unwind_Exception*, %struct._Unwind_Context*)* %21, null
   br i1 %tobool.i, label %if.end12.i, label %if.then3.i
 
 if.then3.i:                                       ; preds = %if.end.i
   %or.i = select i1 %cmp.i, i32 6, i32 2
-  %22 = load i64* %exception_class, align 8
+  %22 = load i64, i64* %exception_class, align 8
   %call5.i = call i32 %21(i32 1, i32 %or.i, i64 %22, %struct._Unwind_Exception* %exc, %struct._Unwind_Context* %cur_context)
   switch i32 %call5.i, label %do.end21 [
     i32 7, label %do.body19
@@ -160,7 +160,7 @@ cond.true.i:                                      ; preds = %if.end12.i
 
 cond.end.i:                                       ; preds = %if.end12.i
   call fastcc void @uw_update_context_1(%struct._Unwind_Context* %cur_context, %struct._Unwind_FrameState* %fs.i)
-  %23 = load i64* %retaddr_column.i22, align 8
+  %23 = load i64, i64* %retaddr_column.i22, align 8
   %conv.i23 = trunc i64 %23 to i32
   %cmp.i.i.i24 = icmp slt i32 %conv.i23, 18
   br i1 %cmp.i.i.i24, label %cond.end.i.i.i33, label %cond.true.i.i.i25
@@ -172,18 +172,18 @@ cond.true.i.i.i25:                                ; preds = %cond.end.i
 cond.end.i.i.i33:                                 ; preds = %cond.end.i
   %sext.i26 = shl i64 %23, 32
   %idxprom.i.i.i27 = ashr exact i64 %sext.i26, 32
-  %arrayidx.i.i.i28 = getelementptr inbounds [18 x i8]* @dwarf_reg_size_table, i64 0, i64 %idxprom.i.i.i27
-  %24 = load i8* %arrayidx.i.i.i28, align 1
-  %arrayidx2.i.i.i29 = getelementptr inbounds %struct._Unwind_Context* %cur_context, i64 0, i32 0, i64 %idxprom.i.i.i27
-  %25 = load i8** %arrayidx2.i.i.i29, align 8
-  %26 = load i64* %flags.i.i.i.i, align 8
+  %arrayidx.i.i.i28 = getelementptr inbounds [18 x i8], [18 x i8]* @dwarf_reg_size_table, i64 0, i64 %idxprom.i.i.i27
+  %24 = load i8, i8* %arrayidx.i.i.i28, align 1
+  %arrayidx2.i.i.i29 = getelementptr inbounds %struct._Unwind_Context, %struct._Unwind_Context* %cur_context, i64 0, i32 0, i64 %idxprom.i.i.i27
+  %25 = load i8*, i8** %arrayidx2.i.i.i29, align 8
+  %26 = load i64, i64* %flags.i.i.i.i, align 8
   %and.i.i.i.i31 = and i64 %26, 4611686018427387904
   %tobool.i.i.i32 = icmp eq i64 %and.i.i.i.i31, 0
   br i1 %tobool.i.i.i32, label %if.end.i.i.i39, label %land.lhs.true.i.i.i36
 
 land.lhs.true.i.i.i36:                            ; preds = %cond.end.i.i.i33
-  %arrayidx4.i.i.i34 = getelementptr inbounds %struct._Unwind_Context* %cur_context, i64 0, i32 8, i64 %idxprom.i.i.i27
-  %27 = load i8* %arrayidx4.i.i.i34, align 1
+  %arrayidx4.i.i.i34 = getelementptr inbounds %struct._Unwind_Context, %struct._Unwind_Context* %cur_context, i64 0, i32 8, i64 %idxprom.i.i.i27
+  %27 = load i8, i8* %arrayidx4.i.i.i34, align 1
   %tobool6.i.i.i35 = icmp eq i8 %27, 0
   br i1 %tobool6.i.i.i35, label %if.end.i.i.i39, label %if.then.i.i.i37
 
@@ -197,7 +197,7 @@ if.end.i.i.i39:                                   ; preds = %land.lhs.true.i.i.i
 
 if.then10.i.i.i40:                                ; preds = %if.end.i.i.i39
   %29 = bitcast i8* %25 to i64*
-  %30 = load i64* %29, align 8
+  %30 = load i64, i64* %29, align 8
   br label %uw_update_context.exit44
 
 cond.true14.i.i.i41:                              ; preds = %if.end.i.i.i39
@@ -213,7 +213,7 @@ uw_update_context.exit44:                         ; preds = %if.then10.i.i.i40,
 do.body19:                                        ; preds = %if.then3.i
   call void @llvm.lifetime.end(i64 -1, i8* %17)
   %call20 = call fastcc i64 @uw_install_context_1(%struct._Unwind_Context* %this_context, %struct._Unwind_Context* %cur_context)
-  %32 = load i8** %ra.i, align 8
+  %32 = load i8*, i8** %ra.i, align 8
   call void @llvm.eh.return.i64(i64 %call20, i8* %32)
   unreachable
 
diff --git a/test/CodeGen/X86/use-add-flags.ll b/test/CodeGen/X86/use-add-flags.ll
index fd57f5ca8d2d..da0002cc2520 100644
--- a/test/CodeGen/X86/use-add-flags.ll
+++ b/test/CodeGen/X86/use-add-flags.ll
@@ -13,7 +13,7 @@
 ;     CHECK: ret
 
 define i32 @test1(i32* %x, i32 %y, i32 %a, i32 %b) nounwind {
-	%tmp2 = load i32* %x, align 4		; <i32> [#uses=1]
+	%tmp2 = load i32, i32* %x, align 4		; <i32> [#uses=1]
 	%tmp4 = add i32 %tmp2, %y		; <i32> [#uses=1]
 	%tmp5 = icmp slt i32 %tmp4, 0		; <i1> [#uses=1]
 	%tmp.0 = select i1 %tmp5, i32 %a, i32 %b		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/utf16-cfstrings.ll b/test/CodeGen/X86/utf16-cfstrings.ll
index c7ec3eb7abce..5f0e78fccc65 100644
--- a/test/CodeGen/X86/utf16-cfstrings.ll
+++ b/test/CodeGen/X86/utf16-cfstrings.ll
@@ -6,7 +6,7 @@
 
 @__CFConstantStringClassReference = external global [0 x i32]
 @.str = internal unnamed_addr constant [5 x i16] [i16 252, i16 98, i16 101, i16 114, i16 0], align 2
-@_unnamed_cfstring_ = private constant %struct.NSConstantString { i32* getelementptr inbounds ([0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 2000, i8* bitcast ([5 x i16]* @.str to i8*), i64 4 }, section "__DATA,__cfstring"
+@_unnamed_cfstring_ = private constant %struct.NSConstantString { i32* getelementptr inbounds ([0 x i32], [0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 2000, i8* bitcast ([5 x i16]* @.str to i8*), i64 4 }, section "__DATA,__cfstring"
 
 ; CHECK:         .section      __TEXT,__ustring
 ; CHECK-NEXT:    .align        1
@@ -21,7 +21,7 @@ define i32 @main() uwtable ssp {
 entry:
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
-  call void (%0*, ...)* @NSLog(%0* bitcast (%struct.NSConstantString* @_unnamed_cfstring_ to %0*))
+  call void (%0*, ...) @NSLog(%0* bitcast (%struct.NSConstantString* @_unnamed_cfstring_ to %0*))
   ret i32 0
 }
 
diff --git a/test/CodeGen/X86/v2f32.ll b/test/CodeGen/X86/v2f32.ll
index b9bd80f949ec..7beed52295ee 100644
--- a/test/CodeGen/X86/v2f32.ll
+++ b/test/CodeGen/X86/v2f32.ll
@@ -5,8 +5,7 @@
 define void @test1(<2 x float> %Q, float *%P2) nounwind {
 ; X64-LABEL: test1:
 ; X64:       # BB#0:
-; X64-NEXT:    movaps %xmm0, %xmm1
-; X64-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
+; X64-NEXT:    movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
 ; X64-NEXT:    addss %xmm0, %xmm1
 ; X64-NEXT:    movss %xmm1, (%rdi)
 ; X64-NEXT:    retq
@@ -14,8 +13,7 @@ define void @test1(<2 x float> %Q, float *%P2) nounwind {
 ; X32-LABEL: test1:
 ; X32:       # BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    movaps %xmm0, %xmm1
-; X32-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
+; X32-NEXT:    movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
 ; X32-NEXT:    addss %xmm0, %xmm1
 ; X32-NEXT:    movss %xmm1, (%eax)
 ; X32-NEXT:    retl
diff --git a/test/CodeGen/X86/v4i32load-crash.ll b/test/CodeGen/X86/v4i32load-crash.ll
index 3e7f9e63c9a8..8d019bc43d6b 100644
--- a/test/CodeGen/X86/v4i32load-crash.ll
+++ b/test/CodeGen/X86/v4i32load-crash.ll
@@ -13,10 +13,10 @@
 ; Function Attrs: nounwind
 define void @fn3(i32 %el) {
 entry:
-  %0 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i32 0)
-  %1 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i32 1)
-  %2 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i32 2)
-  %3 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i32 3)
+  %0 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i32 0)
+  %1 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i32 1)
+  %2 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i32 2)
+  %3 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i32 3)
   %4 = insertelement <4 x i32> undef, i32 %0, i32 0
   %5 = insertelement <4 x i32> %4, i32 %1, i32 1
   %6 = insertelement <4 x i32> %5, i32 %2, i32 2
diff --git a/test/CodeGen/X86/v8i1-masks.ll b/test/CodeGen/X86/v8i1-masks.ll
index 5da6e9636ebe..21fe96321987 100644
--- a/test/CodeGen/X86/v8i1-masks.ll
+++ b/test/CodeGen/X86/v8i1-masks.ll
@@ -10,10 +10,10 @@
 ;CHECK: ret
 
 define void @and_masks(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind uwtable noinline ssp {
-  %v0 = load <8 x float>* %a, align 16
-  %v1 = load <8 x float>* %b, align 16
+  %v0 = load <8 x float>, <8 x float>* %a, align 16
+  %v1 = load <8 x float>, <8 x float>* %b, align 16
   %m0 = fcmp olt <8 x float> %v1, %v0
-  %v2 = load <8 x float>* %c, align 16
+  %v2 = load <8 x float>, <8 x float>* %c, align 16
   %m1 = fcmp olt <8 x float> %v2, %v0
   %mand = and <8 x i1> %m1, %m0
   %r = zext <8 x i1> %mand to <8 x i32>
@@ -28,8 +28,8 @@ define void @and_masks(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwi
 ;CHECK: vmovaps
 ;CHECK: ret
 define void @neg_masks(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind uwtable noinline ssp {
-  %v0 = load <8 x float>* %a, align 16
-  %v1 = load <8 x float>* %b, align 16
+  %v0 = load <8 x float>, <8 x float>* %a, align 16
+  %v1 = load <8 x float>, <8 x float>* %b, align 16
   %m0 = fcmp olt <8 x float> %v1, %v0
   %mand = xor <8 x i1> %m0, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
   %r = zext <8 x i1> %mand to <8 x i32>
diff --git a/test/CodeGen/X86/vaargs.ll b/test/CodeGen/X86/vaargs.ll
index 43c895eb39ef..3767f41c2aae 100644
--- a/test/CodeGen/X86/vaargs.ll
+++ b/test/CodeGen/X86/vaargs.ll
@@ -28,9 +28,9 @@ define i32 @sum(i32 %count, ...) nounwind optsize ssp uwtable {
   br i1 %2, label %.lr.ph, label %._crit_edge
 
 .lr.ph:                                           ; preds = %0
-  %3 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0, i32 0
-  %4 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0, i32 2
-  %.pre = load i32* %3, align 16
+  %3 = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0, i32 0
+  %4 = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0, i32 2
+  %.pre = load i32, i32* %3, align 16
   br label %5
 
 ; <label>:5                                       ; preds = %.lr.ph, %13
@@ -45,8 +45,8 @@ define i32 @sum(i32 %count, ...) nounwind optsize ssp uwtable {
   br label %13
 
 ; <label>:10                                      ; preds = %5
-  %11 = load i8** %4, align 8
-  %12 = getelementptr i8* %11, i64 8
+  %11 = load i8*, i8** %4, align 8
+  %12 = getelementptr i8, i8* %11, i64 8
   store i8* %12, i8** %4, align 8
   br label %13
 
diff --git a/test/CodeGen/X86/vararg-callee-cleanup.ll b/test/CodeGen/X86/vararg-callee-cleanup.ll
index 2dcf319a2080..bb1104d85d87 100644
--- a/test/CodeGen/X86/vararg-callee-cleanup.ll
+++ b/test/CodeGen/X86/vararg-callee-cleanup.ll
@@ -4,8 +4,8 @@ target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"
 
 declare x86_thiscallcc void @thiscall_thunk(i8* %this, ...)
 define i32 @call_varargs_thiscall_thunk(i8* %a, i32 %b, i32 %c, i32 %d) {
-  call x86_thiscallcc void (i8*, ...)* @thiscall_thunk(i8* %a, i32 1, i32 2)
-  call x86_thiscallcc void (i8*, ...)* @thiscall_thunk(i8* %a, i32 1, i32 2)
+  call x86_thiscallcc void (i8*, ...) @thiscall_thunk(i8* %a, i32 1, i32 2)
+  call x86_thiscallcc void (i8*, ...) @thiscall_thunk(i8* %a, i32 1, i32 2)
   %t1 = add i32 %b, %c
   %r = add i32 %t1, %d
   ret i32 %r
@@ -19,8 +19,8 @@ define i32 @call_varargs_thiscall_thunk(i8* %a, i32 %b, i32 %c, i32 %d) {
 
 declare x86_stdcallcc void @stdcall_thunk(i8* %this, ...)
 define i32 @call_varargs_stdcall_thunk(i8* %a, i32 %b, i32 %c, i32 %d) {
-  call x86_stdcallcc void (i8*, ...)* @stdcall_thunk(i8* %a, i32 1, i32 2)
-  call x86_stdcallcc void (i8*, ...)* @stdcall_thunk(i8* %a, i32 1, i32 2)
+  call x86_stdcallcc void (i8*, ...) @stdcall_thunk(i8* %a, i32 1, i32 2)
+  call x86_stdcallcc void (i8*, ...) @stdcall_thunk(i8* %a, i32 1, i32 2)
   %t1 = add i32 %b, %c
   %r = add i32 %t1, %d
   ret i32 %r
@@ -32,8 +32,8 @@ define i32 @call_varargs_stdcall_thunk(i8* %a, i32 %b, i32 %c, i32 %d) {
 
 declare x86_fastcallcc void @fastcall_thunk(i8* %this, ...)
 define i32 @call_varargs_fastcall_thunk(i8* %a, i32 %b, i32 %c, i32 %d) {
-  call x86_fastcallcc void (i8*, ...)* @fastcall_thunk(i8* inreg %a, i32 inreg 1, i32 2)
-  call x86_fastcallcc void (i8*, ...)* @fastcall_thunk(i8* inreg %a, i32 inreg 1, i32 2)
+  call x86_fastcallcc void (i8*, ...) @fastcall_thunk(i8* inreg %a, i32 inreg 1, i32 2)
+  call x86_fastcallcc void (i8*, ...) @fastcall_thunk(i8* inreg %a, i32 inreg 1, i32 2)
   %t1 = add i32 %b, %c
   %r = add i32 %t1, %d
   ret i32 %r
diff --git a/test/CodeGen/X86/vararg_tailcall.ll b/test/CodeGen/X86/vararg_tailcall.ll
index eeda5e15a168..98aa4a89afc1 100644
--- a/test/CodeGen/X86/vararg_tailcall.ll
+++ b/test/CodeGen/X86/vararg_tailcall.ll
@@ -15,7 +15,7 @@
 ; WIN64: callq
 define void @foo(i64 %arg) nounwind optsize ssp noredzone {
 entry:
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %arg) nounwind optsize noredzone
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i64 0, i64 0), i64 %arg) nounwind optsize noredzone
   ret void
 }
 
@@ -27,7 +27,7 @@ declare i32 @printf(i8*, ...) optsize noredzone
 ; WIN64: jmp
 define void @bar(i64 %arg) nounwind optsize ssp noredzone {
 entry:
-  tail call void @bar2(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %arg) nounwind optsize noredzone
+  tail call void @bar2(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i64 0, i64 0), i64 %arg) nounwind optsize noredzone
   ret void
 }
 
@@ -39,8 +39,8 @@ declare void @bar2(i8*, i64) optsize noredzone
 ; WIN64: callq
 define i8* @foo2(i8* %arg) nounwind optsize ssp noredzone {
 entry:
-  %tmp1 = load i8** @sel, align 8
-  %call = tail call i8* (i8*, i8*, ...)* @x2(i8* %arg, i8* %tmp1) nounwind optsize noredzone
+  %tmp1 = load i8*, i8** @sel, align 8
+  %call = tail call i8* (i8*, i8*, ...) @x2(i8* %arg, i8* %tmp1) nounwind optsize noredzone
   ret i8* %call
 }
 
@@ -52,11 +52,11 @@ declare i8* @x2(i8*, i8*, ...) optsize noredzone
 ; WIN64: callq
 define i8* @foo6(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone {
 entry:
-  %tmp2 = load i8** @sel3, align 8
-  %tmp3 = load i8** @sel4, align 8
-  %tmp4 = load i8** @sel5, align 8
-  %tmp5 = load i8** @sel6, align 8
-  %call = tail call i8* (i8*, i8*, i8*, ...)* @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5) nounwind optsize noredzone
+  %tmp2 = load i8*, i8** @sel3, align 8
+  %tmp3 = load i8*, i8** @sel4, align 8
+  %tmp4 = load i8*, i8** @sel5, align 8
+  %tmp5 = load i8*, i8** @sel6, align 8
+  %call = tail call i8* (i8*, i8*, i8*, ...) @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5) nounwind optsize noredzone
   ret i8* %call
 }
 
@@ -68,12 +68,12 @@ declare i8* @x3(i8*, i8*, i8*, ...) optsize noredzone
 ; WIN64: callq
 define i8* @foo7(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone {
 entry:
-  %tmp2 = load i8** @sel3, align 8
-  %tmp3 = load i8** @sel4, align 8
-  %tmp4 = load i8** @sel5, align 8
-  %tmp5 = load i8** @sel6, align 8
-  %tmp6 = load i8** @sel7, align 8
-  %call = tail call i8* (i8*, i8*, i8*, i8*, i8*, i8*, i8*, ...)* @x7(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i8* %tmp6) nounwind optsize noredzone
+  %tmp2 = load i8*, i8** @sel3, align 8
+  %tmp3 = load i8*, i8** @sel4, align 8
+  %tmp4 = load i8*, i8** @sel5, align 8
+  %tmp5 = load i8*, i8** @sel6, align 8
+  %tmp6 = load i8*, i8** @sel7, align 8
+  %call = tail call i8* (i8*, i8*, i8*, i8*, i8*, i8*, i8*, ...) @x7(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i8* %tmp6) nounwind optsize noredzone
   ret i8* %call
 }
 
@@ -85,10 +85,10 @@ declare i8* @x7(i8*, i8*, i8*, i8*, i8*, i8*, i8*, ...) optsize noredzone
 ; WIN64: callq
 define i8* @foo8(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone {
 entry:
-  %tmp2 = load i8** @sel3, align 8
-  %tmp3 = load i8** @sel4, align 8
-  %tmp4 = load i8** @sel5, align 8
-  %tmp5 = load i8** @sel6, align 8
-  %call = tail call i8* (i8*, i8*, i8*, ...)* @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i32 48879, i32 48879) nounwind optsize noredzone
+  %tmp2 = load i8*, i8** @sel3, align 8
+  %tmp3 = load i8*, i8** @sel4, align 8
+  %tmp4 = load i8*, i8** @sel5, align 8
+  %tmp5 = load i8*, i8** @sel6, align 8
+  %call = tail call i8* (i8*, i8*, i8*, ...) @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i32 48879, i32 48879) nounwind optsize noredzone
   ret i8* %call
 }
diff --git a/test/CodeGen/X86/variadic-node-pic.ll b/test/CodeGen/X86/variadic-node-pic.ll
index 1182a306abd0..704459e67a6d 100644
--- a/test/CodeGen/X86/variadic-node-pic.ll
+++ b/test/CodeGen/X86/variadic-node-pic.ll
@@ -6,6 +6,6 @@ target triple = "x86_64-apple-darwin8"
 declare void @xscanf(i64) nounwind 
 
 define void @foo() nounwind  {
-	call void (i64)* @xscanf( i64 0 ) nounwind
+	call void (i64) @xscanf( i64 0 ) nounwind
 	unreachable
 }
diff --git a/test/CodeGen/X86/vec-loadsingles-alignment.ll b/test/CodeGen/X86/vec-loadsingles-alignment.ll
index 6aa2adb228e1..ee3bfb311adf 100644
--- a/test/CodeGen/X86/vec-loadsingles-alignment.ll
+++ b/test/CodeGen/X86/vec-loadsingles-alignment.ll
@@ -10,14 +10,14 @@ define i32 @subb() nounwind ssp {
 ; CHECK-LABEL: subb:
 ; CHECK:  vmovups e(%rip), %ymm
 entry:
-  %0 = load i32* getelementptr inbounds ([8 x i32]* @e, i64 0, i64 7), align 4
-  %1 = load i32* getelementptr inbounds ([8 x i32]* @e, i64 0, i64 6), align 8
-  %2 = load i32* getelementptr inbounds ([8 x i32]* @e, i64 0, i64 5), align 4
-  %3 = load i32* getelementptr inbounds ([8 x i32]* @e, i64 0, i64 4), align 16
-  %4 = load i32* getelementptr inbounds ([8 x i32]* @e, i64 0, i64 3), align 4
-  %5 = load i32* getelementptr inbounds ([8 x i32]* @e, i64 0, i64 2), align 8
-  %6 = load i32* getelementptr inbounds ([8 x i32]* @e, i64 0, i64 1), align 4
-  %7 = load i32* getelementptr inbounds ([8 x i32]* @e, i64 0, i64 0), align 16
+  %0 = load i32, i32* getelementptr inbounds ([8 x i32], [8 x i32]* @e, i64 0, i64 7), align 4
+  %1 = load i32, i32* getelementptr inbounds ([8 x i32], [8 x i32]* @e, i64 0, i64 6), align 8
+  %2 = load i32, i32* getelementptr inbounds ([8 x i32], [8 x i32]* @e, i64 0, i64 5), align 4
+  %3 = load i32, i32* getelementptr inbounds ([8 x i32], [8 x i32]* @e, i64 0, i64 4), align 16
+  %4 = load i32, i32* getelementptr inbounds ([8 x i32], [8 x i32]* @e, i64 0, i64 3), align 4
+  %5 = load i32, i32* getelementptr inbounds ([8 x i32], [8 x i32]* @e, i64 0, i64 2), align 8
+  %6 = load i32, i32* getelementptr inbounds ([8 x i32], [8 x i32]* @e, i64 0, i64 1), align 4
+  %7 = load i32, i32* getelementptr inbounds ([8 x i32], [8 x i32]* @e, i64 0, i64 0), align 16
   %vecinit.i = insertelement <8 x i32> undef, i32 %7, i32 0
   %vecinit1.i = insertelement <8 x i32> %vecinit.i, i32 %6, i32 1
   %vecinit2.i = insertelement <8 x i32> %vecinit1.i, i32 %5, i32 2
diff --git a/test/CodeGen/X86/vec-trunc-store.ll b/test/CodeGen/X86/vec-trunc-store.ll
index 4d665f1843ef..d7897f8f3fa9 100644
--- a/test/CodeGen/X86/vec-trunc-store.ll
+++ b/test/CodeGen/X86/vec-trunc-store.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=x86-64
 
 define void @foo(<8 x i32>* %p) nounwind {
-  %t = load <8 x i32>* %p
+  %t = load <8 x i32>, <8 x i32>* %p
   %cti69 = trunc <8 x i32> %t to <8 x i16>     ; <<8 x i16>> [#uses=1]
   store <8 x i16> %cti69, <8 x i16>* undef
   ret void
 }
 
 define void @bar(<4 x i32>* %p) nounwind {
-  %t = load <4 x i32>* %p
+  %t = load <4 x i32>, <4 x i32>* %p
   %cti44 = trunc <4 x i32> %t to <4 x i16>     ; <<4 x i16>> [#uses=1]
   store <4 x i16> %cti44, <4 x i16>* undef
   ret void
diff --git a/test/CodeGen/X86/vec_align.ll b/test/CodeGen/X86/vec_align.ll
index e27311561b2c..558d768aced4 100644
--- a/test/CodeGen/X86/vec_align.ll
+++ b/test/CodeGen/X86/vec_align.ll
@@ -16,15 +16,15 @@ define %f4 @test1(float %W, float %X, float %Y, float %Z) nounwind {
 }
 
 define %f4 @test2() nounwind {
-	%Wp = getelementptr { float,float,float,float}* @G, i32 0, i32 0
-	%Xp = getelementptr { float,float,float,float}* @G, i32 0, i32 1
-	%Yp = getelementptr { float,float,float,float}* @G, i32 0, i32 2
-	%Zp = getelementptr { float,float,float,float}* @G, i32 0, i32 3
+	%Wp = getelementptr { float,float,float,float}, { float,float,float,float}* @G, i32 0, i32 0
+	%Xp = getelementptr { float,float,float,float}, { float,float,float,float}* @G, i32 0, i32 1
+	%Yp = getelementptr { float,float,float,float}, { float,float,float,float}* @G, i32 0, i32 2
+	%Zp = getelementptr { float,float,float,float}, { float,float,float,float}* @G, i32 0, i32 3
 	
-	%W = load float* %Wp
-	%X = load float* %Xp
-	%Y = load float* %Yp
-	%Z = load float* %Zp
+	%W = load float, float* %Wp
+	%X = load float, float* %Xp
+	%Y = load float, float* %Yp
+	%Z = load float, float* %Zp
 
         %tmp = insertelement %f4 undef, float %W, i32 0
         %tmp2 = insertelement %f4 %tmp, float %X, i32 1
diff --git a/test/CodeGen/X86/vec_anyext.ll b/test/CodeGen/X86/vec_anyext.ll
index d2a4c7f60dd7..c088d7f57b1a 100644
--- a/test/CodeGen/X86/vec_anyext.ll
+++ b/test/CodeGen/X86/vec_anyext.ll
@@ -2,9 +2,9 @@
 ; PR 9267
 
 define<4 x i16> @func_16_32() {
-  %F = load <4 x i32>* undef
+  %F = load <4 x i32>, <4 x i32>* undef
   %G = trunc <4 x i32> %F to <4 x i16>
-  %H = load <4 x i32>* undef
+  %H = load <4 x i32>, <4 x i32>* undef
   %Y = trunc <4 x i32> %H to <4 x i16>
   %T = add <4 x i16> %Y, %G
   store <4 x i16>%T , <4 x i16>* undef
@@ -12,9 +12,9 @@ define<4 x i16> @func_16_32() {
 }
 
 define<4 x i16> @func_16_64() {
-  %F = load <4 x i64>* undef
+  %F = load <4 x i64>, <4 x i64>* undef
   %G = trunc <4 x i64> %F to <4 x i16>
-  %H = load <4 x i64>* undef
+  %H = load <4 x i64>, <4 x i64>* undef
   %Y = trunc <4 x i64> %H to <4 x i16>
   %T = xor <4 x i16> %Y, %G
   store <4 x i16>%T , <4 x i16>* undef
@@ -22,36 +22,36 @@ define<4 x i16> @func_16_64() {
 }
 
 define<4 x i32> @func_32_64() {
-  %F = load <4 x i64>* undef
+  %F = load <4 x i64>, <4 x i64>* undef
   %G = trunc <4 x i64> %F to <4 x i32>
-  %H = load <4 x i64>* undef
+  %H = load <4 x i64>, <4 x i64>* undef
   %Y = trunc <4 x i64> %H to <4 x i32>
   %T = or <4 x i32> %Y, %G
   ret <4 x i32> %T
 }
 
 define<4 x i8> @func_8_16() {
-  %F = load <4 x i16>* undef
+  %F = load <4 x i16>, <4 x i16>* undef
   %G = trunc <4 x i16> %F to <4 x i8>
-  %H = load <4 x i16>* undef
+  %H = load <4 x i16>, <4 x i16>* undef
   %Y = trunc <4 x i16> %H to <4 x i8>
   %T = add <4 x i8> %Y, %G
   ret <4 x i8> %T
 }
 
 define<4 x i8> @func_8_32() {
-  %F = load <4 x i32>* undef
+  %F = load <4 x i32>, <4 x i32>* undef
   %G = trunc <4 x i32> %F to <4 x i8>
-  %H = load <4 x i32>* undef
+  %H = load <4 x i32>, <4 x i32>* undef
   %Y = trunc <4 x i32> %H to <4 x i8>
   %T = sub <4 x i8> %Y, %G
   ret <4 x i8> %T
 }
 
 define<4 x i8> @func_8_64() {
-  %F = load <4 x i64>* undef
+  %F = load <4 x i64>, <4 x i64>* undef
   %G = trunc <4 x i64> %F to <4 x i8>
-  %H = load <4 x i64>* undef
+  %H = load <4 x i64>, <4 x i64>* undef
   %Y = trunc <4 x i64> %H to <4 x i8>
   %T = add <4 x i8> %Y, %G
   ret <4 x i8> %T
diff --git a/test/CodeGen/X86/vec_cast2.ll b/test/CodeGen/X86/vec_cast2.ll
index 8600c48aaac1..1ba11f51baa2 100644
--- a/test/CodeGen/X86/vec_cast2.ll
+++ b/test/CodeGen/X86/vec_cast2.ll
@@ -5,7 +5,7 @@ define <8 x float> @foo1_8(<8 x i8> %src) {
 ; CHECK-LABEL: foo1_8:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    vpunpckhwd {{.*#+}} xmm1 = xmm0[4,4,5,5,6,6,7,7]
-; CHECK-NEXT:    vpmovzxwd %xmm0, %xmm0
+; CHECK-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
 ; CHECK-NEXT:    vpslld $24, %xmm0, %xmm0
 ; CHECK-NEXT:    vpsrad $24, %xmm0, %xmm0
 ; CHECK-NEXT:    vpslld $24, %xmm1, %xmm1
@@ -16,13 +16,9 @@ define <8 x float> @foo1_8(<8 x i8> %src) {
 ;
 ; CHECK-WIDE-LABEL: foo1_8:
 ; CHECK-WIDE:       ## BB#0:
-; CHECK-WIDE-NEXT:    vpmovzxbd %xmm0, %xmm1
-; CHECK-WIDE-NEXT:    vpslld $24, %xmm1, %xmm1
-; CHECK-WIDE-NEXT:    vpsrad $24, %xmm1, %xmm1
-; CHECK-WIDE-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; CHECK-WIDE-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
-; CHECK-WIDE-NEXT:    vpslld $24, %xmm0, %xmm0
-; CHECK-WIDE-NEXT:    vpsrad $24, %xmm0, %xmm0
+; CHECK-WIDE-NEXT:    vpmovsxbd %xmm0, %xmm1
+; CHECK-WIDE-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
+; CHECK-WIDE-NEXT:    vpmovsxbd %xmm0, %xmm0
 ; CHECK-WIDE-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; CHECK-WIDE-NEXT:    vcvtdq2ps %ymm0, %ymm0
 ; CHECK-WIDE-NEXT:    retl
@@ -40,9 +36,7 @@ define <4 x float> @foo1_4(<4 x i8> %src) {
 ;
 ; CHECK-WIDE-LABEL: foo1_4:
 ; CHECK-WIDE:       ## BB#0:
-; CHECK-WIDE-NEXT:    vpmovzxbd %xmm0, %xmm0
-; CHECK-WIDE-NEXT:    vpslld $24, %xmm0, %xmm0
-; CHECK-WIDE-NEXT:    vpsrad $24, %xmm0, %xmm0
+; CHECK-WIDE-NEXT:    vpmovsxbd %xmm0, %xmm0
 ; CHECK-WIDE-NEXT:    vcvtdq2ps %xmm0, %xmm0
 ; CHECK-WIDE-NEXT:    retl
   %res = sitofp <4 x i8> %src to <4 x float>
@@ -52,7 +46,7 @@ define <4 x float> @foo1_4(<4 x i8> %src) {
 define <8 x float> @foo2_8(<8 x i8> %src) {
 ; CHECK-LABEL: foo2_8:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpmovzxwd %xmm0, %xmm1
+; CHECK-NEXT:    vpmovzxwd {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
 ; CHECK-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
 ; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; CHECK-NEXT:    vandps LCPI2_0, %ymm0, %ymm0
@@ -61,20 +55,9 @@ define <8 x float> @foo2_8(<8 x i8> %src) {
 ;
 ; CHECK-WIDE-LABEL: foo2_8:
 ; CHECK-WIDE:       ## BB#0:
-; CHECK-WIDE-NEXT:    vxorps %xmm1, %xmm1, %xmm1
-; CHECK-WIDE-NEXT:    vextractf128 $1, %ymm1, %xmm2
-; CHECK-WIDE-NEXT:    vmovdqa {{.*#+}} xmm3 = <1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u>
-; CHECK-WIDE-NEXT:    vpshufb %xmm3, %xmm2, %xmm4
-; CHECK-WIDE-NEXT:    vmovdqa {{.*#+}} xmm5 = <2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u>
-; CHECK-WIDE-NEXT:    vpshufb %xmm5, %xmm2, %xmm2
-; CHECK-WIDE-NEXT:    vpshufd {{.*#+}} xmm6 = xmm0[1,1,2,3]
-; CHECK-WIDE-NEXT:    vpunpcklbw {{.*#+}} xmm2 = xmm6[0],xmm2[0],xmm6[1],xmm2[1],xmm6[2],xmm2[2],xmm6[3],xmm2[3],xmm6[4],xmm2[4],xmm6[5],xmm2[5],xmm6[6],xmm2[6],xmm6[7],xmm2[7]
-; CHECK-WIDE-NEXT:    vpunpcklbw {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3],xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
-; CHECK-WIDE-NEXT:    vpshufb %xmm3, %xmm1, %xmm3
-; CHECK-WIDE-NEXT:    vpshufb %xmm5, %xmm1, %xmm1
-; CHECK-WIDE-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
-; CHECK-WIDE-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7]
-; CHECK-WIDE-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; CHECK-WIDE-NEXT:    vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; CHECK-WIDE-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
+; CHECK-WIDE-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; CHECK-WIDE-NEXT:    vcvtdq2ps %ymm0, %ymm0
 ; CHECK-WIDE-NEXT:    retl
   %res = uitofp <8 x i8> %src to <8 x float>
@@ -90,7 +73,7 @@ define <4 x float> @foo2_4(<4 x i8> %src) {
 ;
 ; CHECK-WIDE-LABEL: foo2_4:
 ; CHECK-WIDE:       ## BB#0:
-; CHECK-WIDE-NEXT:    vpmovzxbd %xmm0, %xmm0
+; CHECK-WIDE-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
 ; CHECK-WIDE-NEXT:    vcvtdq2ps %xmm0, %xmm0
 ; CHECK-WIDE-NEXT:    retl
   %res = uitofp <4 x i8> %src to <4 x float>
@@ -111,37 +94,29 @@ define <8 x i8> @foo3_8(<8 x float> %src) {
 ;
 ; CHECK-WIDE-LABEL: foo3_8:
 ; CHECK-WIDE:       ## BB#0:
-; CHECK-WIDE-NEXT:    vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
-; CHECK-WIDE-NEXT:    vcvttss2si %xmm1, %eax
-; CHECK-WIDE-NEXT:    shll $8, %eax
-; CHECK-WIDE-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
-; CHECK-WIDE-NEXT:    vcvttss2si %xmm1, %ecx
-; CHECK-WIDE-NEXT:    movzbl %cl, %ecx
-; CHECK-WIDE-NEXT:    orl %eax, %ecx
-; CHECK-WIDE-NEXT:    vpermilps {{.*#+}} xmm1 = xmm0[1,1,2,3]
-; CHECK-WIDE-NEXT:    vcvttss2si %xmm1, %eax
-; CHECK-WIDE-NEXT:    shll $8, %eax
-; CHECK-WIDE-NEXT:    vcvttss2si %xmm0, %edx
-; CHECK-WIDE-NEXT:    movzbl %dl, %edx
-; CHECK-WIDE-NEXT:    orl %eax, %edx
-; CHECK-WIDE-NEXT:    vpinsrw $0, %edx, %xmm0, %xmm1
-; CHECK-WIDE-NEXT:    vpinsrw $1, %ecx, %xmm1, %xmm1
+; CHECK-WIDE-NEXT:    vcvttss2si %xmm0, %eax
+; CHECK-WIDE-NEXT:    vpinsrb $0, %eax, %xmm0, %xmm1
+; CHECK-WIDE-NEXT:    vmovshdup %xmm0, %xmm2    ## xmm2 = xmm0[1,1,3,3]
+; CHECK-WIDE-NEXT:    vcvttss2si %xmm2, %eax
+; CHECK-WIDE-NEXT:    vpinsrb $1, %eax, %xmm1, %xmm1
+; CHECK-WIDE-NEXT:    vpermilpd $1, %xmm0, %xmm2 ## xmm2 = xmm0[1,0]
+; CHECK-WIDE-NEXT:    vcvttss2si %xmm2, %eax
+; CHECK-WIDE-NEXT:    vpinsrb $2, %eax, %xmm1, %xmm1
+; CHECK-WIDE-NEXT:    vpermilps $231, %xmm0, %xmm2 ## xmm2 = xmm0[3,1,2,3]
+; CHECK-WIDE-NEXT:    vcvttss2si %xmm2, %eax
+; CHECK-WIDE-NEXT:    vpinsrb $3, %eax, %xmm1, %xmm1
 ; CHECK-WIDE-NEXT:    vextractf128 $1, %ymm0, %xmm0
-; CHECK-WIDE-NEXT:    vpermilps {{.*#+}} xmm2 = xmm0[1,1,2,3]
+; CHECK-WIDE-NEXT:    vcvttss2si %xmm0, %eax
+; CHECK-WIDE-NEXT:    vpinsrb $4, %eax, %xmm1, %xmm1
+; CHECK-WIDE-NEXT:    vmovshdup %xmm0, %xmm2    ## xmm2 = xmm0[1,1,3,3]
 ; CHECK-WIDE-NEXT:    vcvttss2si %xmm2, %eax
-; CHECK-WIDE-NEXT:    shll $8, %eax
-; CHECK-WIDE-NEXT:    vcvttss2si %xmm0, %ecx
-; CHECK-WIDE-NEXT:    movzbl %cl, %ecx
-; CHECK-WIDE-NEXT:    orl %eax, %ecx
-; CHECK-WIDE-NEXT:    vpinsrw $2, %ecx, %xmm1, %xmm1
-; CHECK-WIDE-NEXT:    vpermilps {{.*#+}} xmm2 = xmm0[3,1,2,3]
+; CHECK-WIDE-NEXT:    vpinsrb $5, %eax, %xmm1, %xmm1
+; CHECK-WIDE-NEXT:    vpermilpd $1, %xmm0, %xmm2 ## xmm2 = xmm0[1,0]
 ; CHECK-WIDE-NEXT:    vcvttss2si %xmm2, %eax
-; CHECK-WIDE-NEXT:    shll $8, %eax
-; CHECK-WIDE-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
-; CHECK-WIDE-NEXT:    vcvttss2si %xmm0, %ecx
-; CHECK-WIDE-NEXT:    movzbl %cl, %ecx
-; CHECK-WIDE-NEXT:    orl %eax, %ecx
-; CHECK-WIDE-NEXT:    vpinsrw $3, %ecx, %xmm1, %xmm0
+; CHECK-WIDE-NEXT:    vpinsrb $6, %eax, %xmm1, %xmm1
+; CHECK-WIDE-NEXT:    vpermilps $231, %xmm0, %xmm0 ## xmm0 = xmm0[3,1,2,3]
+; CHECK-WIDE-NEXT:    vcvttss2si %xmm0, %eax
+; CHECK-WIDE-NEXT:    vpinsrb $7, %eax, %xmm1, %xmm0
 ; CHECK-WIDE-NEXT:    vzeroupper
 ; CHECK-WIDE-NEXT:    retl
   %res = fptosi <8 x float> %src to <8 x i8>
@@ -156,21 +131,17 @@ define <4 x i8> @foo3_4(<4 x float> %src) {
 ;
 ; CHECK-WIDE-LABEL: foo3_4:
 ; CHECK-WIDE:       ## BB#0:
-; CHECK-WIDE-NEXT:    vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
-; CHECK-WIDE-NEXT:    vcvttss2si %xmm1, %eax
-; CHECK-WIDE-NEXT:    shll $8, %eax
-; CHECK-WIDE-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
-; CHECK-WIDE-NEXT:    vcvttss2si %xmm1, %ecx
-; CHECK-WIDE-NEXT:    movzbl %cl, %ecx
-; CHECK-WIDE-NEXT:    orl %eax, %ecx
-; CHECK-WIDE-NEXT:    vpermilps {{.*#+}} xmm1 = xmm0[1,1,2,3]
-; CHECK-WIDE-NEXT:    vcvttss2si %xmm1, %eax
-; CHECK-WIDE-NEXT:    shll $8, %eax
-; CHECK-WIDE-NEXT:    vcvttss2si %xmm0, %edx
-; CHECK-WIDE-NEXT:    movzbl %dl, %edx
-; CHECK-WIDE-NEXT:    orl %eax, %edx
-; CHECK-WIDE-NEXT:    vpinsrw $0, %edx, %xmm0, %xmm0
-; CHECK-WIDE-NEXT:    vpinsrw $1, %ecx, %xmm0, %xmm0
+; CHECK-WIDE-NEXT:    vcvttss2si %xmm0, %eax
+; CHECK-WIDE-NEXT:    vpinsrb $0, %eax, %xmm0, %xmm1
+; CHECK-WIDE-NEXT:    vmovshdup %xmm0, %xmm2    ## xmm2 = xmm0[1,1,3,3]
+; CHECK-WIDE-NEXT:    vcvttss2si %xmm2, %eax
+; CHECK-WIDE-NEXT:    vpinsrb $1, %eax, %xmm1, %xmm1
+; CHECK-WIDE-NEXT:    vpermilpd $1, %xmm0, %xmm2 ## xmm2 = xmm0[1,0]
+; CHECK-WIDE-NEXT:    vcvttss2si %xmm2, %eax
+; CHECK-WIDE-NEXT:    vpinsrb $2, %eax, %xmm1, %xmm1
+; CHECK-WIDE-NEXT:    vpermilps $231, %xmm0, %xmm0 ## xmm0 = xmm0[3,1,2,3]
+; CHECK-WIDE-NEXT:    vcvttss2si %xmm0, %eax
+; CHECK-WIDE-NEXT:    vpinsrb $3, %eax, %xmm1, %xmm0
 ; CHECK-WIDE-NEXT:    retl
   %res = fptosi <4 x float> %src to <4 x i8>
   ret <4 x i8> %res
diff --git a/test/CodeGen/X86/vec_clear.ll b/test/CodeGen/X86/vec_clear.ll
deleted file mode 100644
index 166d4363ec8d..000000000000
--- a/test/CodeGen/X86/vec_clear.ll
+++ /dev/null
@@ -1,13 +0,0 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -o %t
-; RUN: not grep and %t
-; RUN: not grep psrldq %t
-; RUN: grep xorps %t
-
-define <4 x float> @test(<4 x float>* %v1) nounwind {
-        %tmp = load <4 x float>* %v1            ; <<4 x float>> [#uses=1]
-        %tmp15 = bitcast <4 x float> %tmp to <2 x i64>          ; <<2 x i64>> [#uses=1]
-        %tmp24 = and <2 x i64> %tmp15, bitcast (<4 x i32> < i32 0, i32 0, i32 -1, i32 -1 > to <2 x i64>)              ; <<2 x i64>> [#uses=1]
-        %tmp31 = bitcast <2 x i64> %tmp24 to <4 x float>                ; <<4 x float>> [#uses=1]
-        ret <4 x float> %tmp31
-}
-
diff --git a/test/CodeGen/X86/vec_compare.ll b/test/CodeGen/X86/vec_compare.ll
index 365fe92220b5..df3eae3399f3 100644
--- a/test/CodeGen/X86/vec_compare.ll
+++ b/test/CodeGen/X86/vec_compare.ll
@@ -45,7 +45,7 @@ define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind {
 define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) nounwind {
 ; CHECK-LABEL: test5:
 ; CHECK: pcmpeqd
-; CHECK: pshufd $-79
+; CHECK: pshufd $177
 ; CHECK: pand
 ; CHECK: ret
 	%C = icmp eq <2 x i64> %A, %B
@@ -56,7 +56,7 @@ define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) nounwind {
 define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) nounwind {
 ; CHECK-LABEL: test6:
 ; CHECK: pcmpeqd
-; CHECK: pshufd $-79
+; CHECK: pshufd $177
 ; CHECK: pand
 ; CHECK: pcmpeqd
 ; CHECK: pxor
@@ -77,11 +77,11 @@ define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind {
 ; CHECK: pxor [[CONSTREG]]
 ; CHECK: pxor [[CONSTREG]]
 ; CHECK: pcmpgtd %xmm1
-; CHECK: pshufd $-96
+; CHECK: pshufd $160
 ; CHECK: pcmpeqd
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: pand
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: por
 ; CHECK: ret
 	%C = icmp sgt <2 x i64> %A, %B
@@ -94,11 +94,11 @@ define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind {
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm0
-; CHECK: pshufd $-96
+; CHECK: pshufd $160
 ; CHECK: pcmpeqd
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: pand
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: por
 ; CHECK: ret
 	%C = icmp slt <2 x i64> %A, %B
@@ -111,11 +111,11 @@ define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind {
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm0
-; CHECK: pshufd $-96
+; CHECK: pshufd $160
 ; CHECK: pcmpeqd
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: pand
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: por
 ; CHECK: pcmpeqd
 ; CHECK: pxor
@@ -130,11 +130,11 @@ define <2 x i64> @test10(<2 x i64> %A, <2 x i64> %B) nounwind {
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm1
-; CHECK: pshufd $-96
+; CHECK: pshufd $160
 ; CHECK: pcmpeqd
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: pand
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: por
 ; CHECK: pcmpeqd
 ; CHECK: pxor
@@ -155,11 +155,11 @@ define <2 x i64> @test11(<2 x i64> %A, <2 x i64> %B) nounwind {
 ; CHECK: pxor [[CONSTREG]]
 ; CHECK: pxor [[CONSTREG]]
 ; CHECK: pcmpgtd %xmm1
-; CHECK: pshufd $-96
+; CHECK: pshufd $160
 ; CHECK: pcmpeqd
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: pand
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: por
 ; CHECK: ret
 	%C = icmp ugt <2 x i64> %A, %B
@@ -172,11 +172,11 @@ define <2 x i64> @test12(<2 x i64> %A, <2 x i64> %B) nounwind {
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm0
-; CHECK: pshufd $-96
+; CHECK: pshufd $160
 ; CHECK: pcmpeqd
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: pand
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: por
 ; CHECK: ret
 	%C = icmp ult <2 x i64> %A, %B
@@ -189,11 +189,11 @@ define <2 x i64> @test13(<2 x i64> %A, <2 x i64> %B) nounwind {
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm0
-; CHECK: pshufd $-96
+; CHECK: pshufd $160
 ; CHECK: pcmpeqd
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: pand
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: por
 ; CHECK: pcmpeqd
 ; CHECK: pxor
@@ -208,11 +208,11 @@ define <2 x i64> @test14(<2 x i64> %A, <2 x i64> %B) nounwind {
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm1
-; CHECK: pshufd $-96
+; CHECK: pshufd $160
 ; CHECK: pcmpeqd
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: pand
-; CHECK: pshufd $-11
+; CHECK: pshufd $245
 ; CHECK: por
 ; CHECK: pcmpeqd
 ; CHECK: pxor
diff --git a/test/CodeGen/X86/vec_extract-mmx.ll b/test/CodeGen/X86/vec_extract-mmx.ll
new file mode 100644
index 000000000000..780066d2da15
--- /dev/null
+++ b/test/CodeGen/X86/vec_extract-mmx.ll
@@ -0,0 +1,71 @@
+; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | FileCheck %s
+
+define i32 @test0(<1 x i64>* %v4) {
+; CHECK-LABEL: test0:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    pshufw $238, (%[[REG:[a-z]+]]), %mm0
+; CHECK-NEXT:    movd %mm0, %eax
+; CHECK-NEXT:    addl $32, %eax
+; CHECK-NEXT:    retq
+entry:
+  %v5 = load <1 x i64>, <1 x i64>* %v4, align 8
+  %v12 = bitcast <1 x i64> %v5 to <4 x i16>
+  %v13 = bitcast <4 x i16> %v12 to x86_mmx
+  %v14 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %v13, i8 -18)
+  %v15 = bitcast x86_mmx %v14 to <4 x i16>
+  %v16 = bitcast <4 x i16> %v15 to <1 x i64>
+  %v17 = extractelement <1 x i64> %v16, i32 0
+  %v18 = bitcast i64 %v17 to <2 x i32>
+  %v19 = extractelement <2 x i32> %v18, i32 0
+  %v20 = add i32 %v19, 32
+  ret i32 %v20
+}
+
+define i32 @test1(i32* nocapture readonly %ptr) {
+; CHECK-LABEL: test1:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    movd (%[[REG]]), %mm0
+; CHECK-NEXT:    pshufw $232, %mm0, %mm0
+; CHECK-NEXT:    movd %mm0, %eax
+; CHECK-NEXT:    emms
+; CHECK-NEXT:    retq
+entry:
+  %0 = load i32, i32* %ptr, align 4
+  %1 = insertelement <2 x i32> undef, i32 %0, i32 0
+  %2 = insertelement <2 x i32> %1, i32 0, i32 1
+  %3 = bitcast <2 x i32> %2 to x86_mmx
+  %4 = bitcast x86_mmx %3 to i64
+  %5 = bitcast i64 %4 to <4 x i16>
+  %6 = bitcast <4 x i16> %5 to x86_mmx
+  %7 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %6, i8 -24)
+  %8 = bitcast x86_mmx %7 to <4 x i16>
+  %9 = bitcast <4 x i16> %8 to <1 x i64>
+  %10 = extractelement <1 x i64> %9, i32 0
+  %11 = bitcast i64 %10 to <2 x i32>
+  %12 = extractelement <2 x i32> %11, i32 0
+  tail call void @llvm.x86.mmx.emms()
+  ret i32 %12
+}
+
+define i32 @test2(i32* nocapture readonly %ptr) {
+; CHECK-LABEL: test2:
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    pshufw $232, (%[[REG]]), %mm0
+; CHECK-NEXT:    movd %mm0, %eax
+; CHECK-NEXT:    emms
+; CHECK-NEXT:    retq
+entry:
+  %0 = bitcast i32* %ptr to x86_mmx*
+  %1 = load x86_mmx, x86_mmx* %0, align 8
+  %2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -24)
+  %3 = bitcast x86_mmx %2 to <4 x i16>
+  %4 = bitcast <4 x i16> %3 to <1 x i64>
+  %5 = extractelement <1 x i64> %4, i32 0
+  %6 = bitcast i64 %5 to <2 x i32>
+  %7 = extractelement <2 x i32> %6, i32 0
+  tail call void @llvm.x86.mmx.emms()
+  ret i32 %7
+}
+
+declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)
+declare void @llvm.x86.mmx.emms()
diff --git a/test/CodeGen/X86/vec_extract-sse4.ll b/test/CodeGen/X86/vec_extract-sse4.ll
index 530911add121..9f4210f7847e 100644
--- a/test/CodeGen/X86/vec_extract-sse4.ll
+++ b/test/CodeGen/X86/vec_extract-sse4.ll
@@ -9,7 +9,7 @@ define void @t1(float* %R, <4 x float>* %P1) nounwind {
 ; CHECK-NEXT:    movss %xmm0, (%eax)
 ; CHECK-NEXT:    retl
 
-	%X = load <4 x float>* %P1
+	%X = load <4 x float>, <4 x float>* %P1
 	%tmp = extractelement <4 x float> %X, i32 3
 	store float %tmp, float* %R
 	ret void
@@ -27,7 +27,7 @@ define float @t2(<4 x float>* %P1) nounwind {
 ; CHECK-NEXT:    popl %eax
 ; CHECK-NEXT:    retl
 
-	%X = load <4 x float>* %P1
+	%X = load <4 x float>, <4 x float>* %P1
 	%tmp = extractelement <4 x float> %X, i32 2
 	ret float %tmp
 }
@@ -41,7 +41,7 @@ define void @t3(i32* %R, <4 x i32>* %P1) nounwind {
 ; CHECK-NEXT:    movl %ecx, (%eax)
 ; CHECK-NEXT:    retl
 
-	%X = load <4 x i32>* %P1
+	%X = load <4 x i32>, <4 x i32>* %P1
 	%tmp = extractelement <4 x i32> %X, i32 3
 	store i32 %tmp, i32* %R
 	ret void
@@ -54,7 +54,7 @@ define i32 @t4(<4 x i32>* %P1) nounwind {
 ; CHECK-NEXT:    movl 12(%eax), %eax
 ; CHECK-NEXT:    retl
 
-	%X = load <4 x i32>* %P1
+	%X = load <4 x i32>, <4 x i32>* %P1
 	%tmp = extractelement <4 x i32> %X, i32 3
 	ret i32 %tmp
 }
diff --git a/test/CodeGen/X86/vec_extract.ll b/test/CodeGen/X86/vec_extract.ll
index 6df7be7a087b..3b478880590d 100644
--- a/test/CodeGen/X86/vec_extract.ll
+++ b/test/CodeGen/X86/vec_extract.ll
@@ -12,7 +12,7 @@ define void @test1(<4 x float>* %F, float* %f) nounwind {
 ; CHECK-NEXT:    movss %xmm0, (%eax)
 ; CHECK-NEXT:    retl
 entry:
-	%tmp = load <4 x float>* %F		; <<4 x float>> [#uses=2]
+	%tmp = load <4 x float>, <4 x float>* %F		; <<4 x float>> [#uses=2]
 	%tmp7 = fadd <4 x float> %tmp, %tmp		; <<4 x float>> [#uses=1]
 	%tmp2 = extractelement <4 x float> %tmp7, i32 0		; <float> [#uses=1]
 	store float %tmp2, float* %f
@@ -32,7 +32,7 @@ define float @test2(<4 x float>* %F, float* %f) nounwind {
 ; CHECK-NEXT:    popl %eax
 ; CHECK-NEXT:    retl
 entry:
-	%tmp = load <4 x float>* %F		; <<4 x float>> [#uses=2]
+	%tmp = load <4 x float>, <4 x float>* %F		; <<4 x float>> [#uses=2]
 	%tmp7 = fadd <4 x float> %tmp, %tmp		; <<4 x float>> [#uses=1]
 	%tmp2 = extractelement <4 x float> %tmp7, i32 2		; <float> [#uses=1]
 	ret float %tmp2
@@ -47,7 +47,7 @@ define void @test3(float* %R, <4 x float>* %P1) nounwind {
 ; CHECK-NEXT:    movss %xmm0, (%eax)
 ; CHECK-NEXT:    retl
 entry:
-	%X = load <4 x float>* %P1		; <<4 x float>> [#uses=1]
+	%X = load <4 x float>, <4 x float>* %P1		; <<4 x float>> [#uses=1]
 	%tmp = extractelement <4 x float> %X, i32 3		; <float> [#uses=1]
 	store float %tmp, float* %R
 	ret void
diff --git a/test/CodeGen/X86/vec_fabs.ll b/test/CodeGen/X86/vec_fabs.ll
index ac02acfed342..bfefbcf5ebd3 100644
--- a/test/CodeGen/X86/vec_fabs.ll
+++ b/test/CodeGen/X86/vec_fabs.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s
 
 
 define <2 x double> @fabs_v2f64(<2 x double> %p)
diff --git a/test/CodeGen/X86/vec_floor.ll b/test/CodeGen/X86/vec_floor.ll
index 4db68bd18223..f35c4ab4a76e 100644
--- a/test/CodeGen/X86/vec_floor.ll
+++ b/test/CodeGen/X86/vec_floor.ll
@@ -180,3 +180,49 @@ define <8 x float> @nearbyint_v8f32(<8 x float> %p)
   ret <8 x float> %t
 }
 declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
+
+;
+; Constant Folding
+;
+
+define <2 x double> @const_floor_v2f64() {
+  ; CHECK: const_floor_v2f64
+  ; CHECK: movaps {{.*#+}} xmm0 = [-2.000000e+00,2.000000e+00]
+  %t = call <2 x double> @llvm.floor.v2f64(<2 x double> <double -1.5, double 2.5>)
+  ret <2 x double> %t
+}
+
+define <4 x float> @const_floor_v4f32() {
+  ; CHECK: const_floor_v4f32
+  ; CHECK: movaps {{.*#+}} xmm0 = [-4.000000e+00,6.000000e+00,-9.000000e+00,2.000000e+00]
+  %t = call <4 x float> @llvm.floor.v4f32(<4 x float> <float -3.5, float 6.0, float -9.0, float 2.5>)
+  ret <4 x float> %t
+}
+
+define <2 x double> @const_ceil_v2f64() {
+  ; CHECK: const_ceil_v2f64
+  ; CHECK: movaps {{.*#+}} xmm0 = [-1.000000e+00,3.000000e+00]
+  %t = call <2 x double> @llvm.ceil.v2f64(<2 x double> <double -1.5, double 2.5>)
+  ret <2 x double> %t
+}
+
+define <4 x float> @const_ceil_v4f32() {
+  ; CHECK: const_ceil_v4f32
+  ; CHECK: movaps {{.*#+}} xmm0 = [-3.000000e+00,6.000000e+00,-9.000000e+00,3.000000e+00]
+  %t = call <4 x float> @llvm.ceil.v4f32(<4 x float> <float -3.5, float 6.0, float -9.0, float 2.5>)
+  ret <4 x float> %t
+}
+
+define <2 x double> @const_trunc_v2f64() {
+  ; CHECK: const_trunc_v2f64
+  ; CHECK: movaps {{.*#+}} xmm0 = [-1.000000e+00,2.000000e+00]
+  %t = call <2 x double> @llvm.trunc.v2f64(<2 x double> <double -1.5, double 2.5>)
+  ret <2 x double> %t
+}
+
+define <4 x float> @const_trunc_v4f32() {
+  ; CHECK: const_trunc_v4f32
+  ; CHECK: movaps {{.*#+}} xmm0 = [-3.000000e+00,6.000000e+00,-9.000000e+00,2.000000e+00]
+  %t = call <4 x float> @llvm.trunc.v4f32(<4 x float> <float -3.5, float 6.0, float -9.0, float 2.5>)
+  ret <4 x float> %t
+}
diff --git a/test/CodeGen/X86/vec_fneg.ll b/test/CodeGen/X86/vec_fneg.ll
index 9743f7148c69..a85ae984d8e6 100644
--- a/test/CodeGen/X86/vec_fneg.ll
+++ b/test/CodeGen/X86/vec_fneg.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse | FileCheck %s
 
 ; FNEG is defined as subtraction from -0.0.
 
diff --git a/test/CodeGen/X86/vec_fp_to_int.ll b/test/CodeGen/X86/vec_fp_to_int.ll
new file mode 100644
index 000000000000..9f1c7afa295b
--- /dev/null
+++ b/test/CodeGen/X86/vec_fp_to_int.ll
@@ -0,0 +1,955 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL  --check-prefix=AVX
+
+;
+; Double to Signed Integer
+;
+
+define <2 x i64> @fptosi_2vf64(<2 x double> %a) {
+; SSE2-LABEL: fptosi_2vf64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    cvttsd2si %xmm0, %rax
+; SSE2-NEXT:    movd %rax, %xmm1
+; SSE2-NEXT:    shufpd {{.*#+}} xmm0 = xmm0[1,0]
+; SSE2-NEXT:    cvttsd2si %xmm0, %rax
+; SSE2-NEXT:    movd %rax, %xmm0
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptosi_2vf64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vcvttsd2si %xmm0, %rax
+; AVX-NEXT:    vmovq %rax, %xmm1
+; AVX-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX-NEXT:    vcvttsd2si %xmm0, %rax
+; AVX-NEXT:    vmovq %rax, %xmm0
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX-NEXT:    retq
+  %cvt = fptosi <2 x double> %a to <2 x i64>
+  ret <2 x i64> %cvt
+}
+
+define <4 x i32> @fptosi_2vf64_i32(<2 x double> %a) {
+; SSE2-LABEL: fptosi_2vf64_i32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    cvttsd2si %xmm0, %rax
+; SSE2-NEXT:    movd %rax, %xmm1
+; SSE2-NEXT:    shufpd {{.*#+}} xmm0 = xmm0[1,0]
+; SSE2-NEXT:    cvttsd2si %xmm0, %rax
+; SSE2-NEXT:    movd %rax, %xmm0
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptosi_2vf64_i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vcvttsd2si %xmm0, %rax
+; AVX-NEXT:    vmovq %rax, %xmm1
+; AVX-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX-NEXT:    vcvttsd2si %xmm0, %rax
+; AVX-NEXT:    vmovq %rax, %xmm0
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; AVX-NEXT:    retq
+  %cvt = fptosi <2 x double> %a to <2 x i32>
+  %ext = shufflevector <2 x i32> %cvt, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  ret <4 x i32> %ext
+}
+
+define <4 x i64> @fptosi_4vf64(<4 x double> %a) {
+; SSE2-LABEL: fptosi_4vf64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    cvttsd2si %xmm0, %rax
+; SSE2-NEXT:    movd %rax, %xmm2
+; SSE2-NEXT:    shufpd {{.*#+}} xmm0 = xmm0[1,0]
+; SSE2-NEXT:    cvttsd2si %xmm0, %rax
+; SSE2-NEXT:    movd %rax, %xmm0
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; SSE2-NEXT:    cvttsd2si %xmm1, %rax
+; SSE2-NEXT:    movd %rax, %xmm3
+; SSE2-NEXT:    shufpd {{.*#+}} xmm1 = xmm1[1,0]
+; SSE2-NEXT:    cvttsd2si %xmm1, %rax
+; SSE2-NEXT:    movd %rax, %xmm0
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
+; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    movdqa %xmm3, %xmm1
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptosi_4vf64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX-NEXT:    vcvttsd2si %xmm1, %rax
+; AVX-NEXT:    vmovq %rax, %xmm2
+; AVX-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm1[1,0]
+; AVX-NEXT:    vcvttsd2si %xmm1, %rax
+; AVX-NEXT:    vmovq %rax, %xmm1
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; AVX-NEXT:    vcvttsd2si %xmm0, %rax
+; AVX-NEXT:    vmovq %rax, %xmm2
+; AVX-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX-NEXT:    vcvttsd2si %xmm0, %rax
+; AVX-NEXT:    vmovq %rax, %xmm0
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
+; AVX-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX-NEXT:    retq
+  %cvt = fptosi <4 x double> %a to <4 x i64>
+  ret <4 x i64> %cvt
+}
+
+define <4 x i32> @fptosi_4vf64_i32(<4 x double> %a) {
+; SSE2-LABEL: fptosi_4vf64_i32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    cvttsd2si %xmm1, %rax
+; SSE2-NEXT:    movd %rax, %xmm2
+; SSE2-NEXT:    shufpd {{.*#+}} xmm1 = xmm1[1,0]
+; SSE2-NEXT:    cvttsd2si %xmm1, %rax
+; SSE2-NEXT:    movd %rax, %xmm1
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
+; SSE2-NEXT:    cvttsd2si %xmm0, %rax
+; SSE2-NEXT:    movd %rax, %xmm2
+; SSE2-NEXT:    shufpd {{.*#+}} xmm0 = xmm0[1,0]
+; SSE2-NEXT:    cvttsd2si %xmm0, %rax
+; SSE2-NEXT:    movd %rax, %xmm0
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptosi_4vf64_i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vcvttpd2dqy %ymm0, %xmm0
+; AVX-NEXT:    vzeroupper
+; AVX-NEXT:    retq
+  %cvt = fptosi <4 x double> %a to <4 x i32>
+  ret <4 x i32> %cvt
+}
+
+;
+; Double to Unsigned Integer
+;
+
+define <2 x i64> @fptoui_2vf64(<2 x double> %a) {
+; SSE2-LABEL: fptoui_2vf64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movsd {{.*#+}} xmm2 = mem[0],zero
+; SSE2-NEXT:    movapd %xmm0, %xmm1
+; SSE2-NEXT:    subsd %xmm2, %xmm1
+; SSE2-NEXT:    cvttsd2si %xmm1, %rax
+; SSE2-NEXT:    movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE2-NEXT:    xorq %rcx, %rax
+; SSE2-NEXT:    cvttsd2si %xmm0, %rdx
+; SSE2-NEXT:    ucomisd %xmm2, %xmm0
+; SSE2-NEXT:    cmovaeq %rax, %rdx
+; SSE2-NEXT:    movd %rdx, %xmm1
+; SSE2-NEXT:    shufpd {{.*#+}} xmm0 = xmm0[1,0]
+; SSE2-NEXT:    movapd %xmm0, %xmm3
+; SSE2-NEXT:    subsd %xmm2, %xmm3
+; SSE2-NEXT:    cvttsd2si %xmm3, %rax
+; SSE2-NEXT:    xorq %rcx, %rax
+; SSE2-NEXT:    cvttsd2si %xmm0, %rcx
+; SSE2-NEXT:    ucomisd %xmm2, %xmm0
+; SSE2-NEXT:    cmovaeq %rax, %rcx
+; SSE2-NEXT:    movd %rcx, %xmm0
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptoui_2vf64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
+; AVX-NEXT:    vsubsd %xmm1, %xmm0, %xmm2
+; AVX-NEXT:    vcvttsd2si %xmm2, %rax
+; AVX-NEXT:    movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; AVX-NEXT:    xorq %rcx, %rax
+; AVX-NEXT:    vcvttsd2si %xmm0, %rdx
+; AVX-NEXT:    vucomisd %xmm1, %xmm0
+; AVX-NEXT:    cmovaeq %rax, %rdx
+; AVX-NEXT:    vmovq %rdx, %xmm2
+; AVX-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX-NEXT:    vsubsd %xmm1, %xmm0, %xmm3
+; AVX-NEXT:    vcvttsd2si %xmm3, %rax
+; AVX-NEXT:    xorq %rcx, %rax
+; AVX-NEXT:    vcvttsd2si %xmm0, %rcx
+; AVX-NEXT:    vucomisd %xmm1, %xmm0
+; AVX-NEXT:    cmovaeq %rax, %rcx
+; AVX-NEXT:    vmovq %rcx, %xmm0
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
+; AVX-NEXT:    retq
+  %cvt = fptoui <2 x double> %a to <2 x i64>
+  ret <2 x i64> %cvt
+}
+
+define <4 x i32> @fptoui_2vf64_i32(<2 x double> %a) {
+; SSE2-LABEL: fptoui_2vf64_i32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
+; SSE2-NEXT:    movapd %xmm0, %xmm2
+; SSE2-NEXT:    subsd %xmm1, %xmm2
+; SSE2-NEXT:    cvttsd2si %xmm2, %rax
+; SSE2-NEXT:    movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE2-NEXT:    xorq %rcx, %rax
+; SSE2-NEXT:    cvttsd2si %xmm0, %rdx
+; SSE2-NEXT:    ucomisd %xmm1, %xmm0
+; SSE2-NEXT:    cmovaeq %rax, %rdx
+; SSE2-NEXT:    movd %rdx, %xmm2
+; SSE2-NEXT:    shufpd {{.*#+}} xmm0 = xmm0[1,0]
+; SSE2-NEXT:    movapd %xmm0, %xmm3
+; SSE2-NEXT:    subsd %xmm1, %xmm3
+; SSE2-NEXT:    cvttsd2si %xmm3, %rax
+; SSE2-NEXT:    xorq %rcx, %rax
+; SSE2-NEXT:    cvttsd2si %xmm0, %rcx
+; SSE2-NEXT:    ucomisd %xmm1, %xmm0
+; SSE2-NEXT:    cmovaeq %rax, %rcx
+; SSE2-NEXT:    movd %rcx, %xmm0
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptoui_2vf64_i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
+; AVX-NEXT:    vsubsd %xmm1, %xmm0, %xmm2
+; AVX-NEXT:    vcvttsd2si %xmm2, %rax
+; AVX-NEXT:    movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; AVX-NEXT:    xorq %rcx, %rax
+; AVX-NEXT:    vcvttsd2si %xmm0, %rdx
+; AVX-NEXT:    vucomisd %xmm1, %xmm0
+; AVX-NEXT:    cmovaeq %rax, %rdx
+; AVX-NEXT:    vmovq %rdx, %xmm2
+; AVX-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX-NEXT:    vsubsd %xmm1, %xmm0, %xmm3
+; AVX-NEXT:    vcvttsd2si %xmm3, %rax
+; AVX-NEXT:    xorq %rcx, %rax
+; AVX-NEXT:    vcvttsd2si %xmm0, %rcx
+; AVX-NEXT:    vucomisd %xmm1, %xmm0
+; AVX-NEXT:    cmovaeq %rax, %rcx
+; AVX-NEXT:    vmovq %rcx, %xmm0
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
+; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; AVX-NEXT:    retq
+  %cvt = fptoui <2 x double> %a to <2 x i32>
+  %ext = shufflevector <2 x i32> %cvt, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  ret <4 x i32> %ext
+}
+
+define <4 x i64> @fptoui_4vf64(<4 x double> %a) {
+; SSE2-LABEL: fptoui_4vf64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movapd %xmm0, %xmm2
+; SSE2-NEXT:    movsd {{.*#+}} xmm3 = mem[0],zero
+; SSE2-NEXT:    {{.*#+}} kill: XMM0<def> XMM2<kill>
+; SSE2-NEXT:    subsd %xmm3, %xmm0
+; SSE2-NEXT:    cvttsd2si %xmm0, %rcx
+; SSE2-NEXT:    movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
+; SSE2-NEXT:    xorq %rax, %rcx
+; SSE2-NEXT:    cvttsd2si %xmm2, %rdx
+; SSE2-NEXT:    ucomisd %xmm3, %xmm2
+; SSE2-NEXT:    cmovaeq %rcx, %rdx
+; SSE2-NEXT:    movd %rdx, %xmm0
+; SSE2-NEXT:    shufpd {{.*#+}} xmm2 = xmm2[1,0]
+; SSE2-NEXT:    movapd %xmm2, %xmm4
+; SSE2-NEXT:    subsd %xmm3, %xmm4
+; SSE2-NEXT:    cvttsd2si %xmm4, %rcx
+; SSE2-NEXT:    xorq %rax, %rcx
+; SSE2-NEXT:    cvttsd2si %xmm2, %rdx
+; SSE2-NEXT:    ucomisd %xmm3, %xmm2
+; SSE2-NEXT:    cmovaeq %rcx, %rdx
+; SSE2-NEXT:    movd %rdx, %xmm2
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-NEXT:    movapd %xmm1, %xmm2
+; SSE2-NEXT:    subsd %xmm3, %xmm2
+; SSE2-NEXT:    cvttsd2si %xmm2, %rcx
+; SSE2-NEXT:    xorq %rax, %rcx
+; SSE2-NEXT:    cvttsd2si %xmm1, %rdx
+; SSE2-NEXT:    ucomisd %xmm3, %xmm1
+; SSE2-NEXT:    cmovaeq %rcx, %rdx
+; SSE2-NEXT:    movd %rdx, %xmm2
+; SSE2-NEXT:    shufpd {{.*#+}} xmm1 = xmm1[1,0]
+; SSE2-NEXT:    movapd %xmm1, %xmm4
+; SSE2-NEXT:    subsd %xmm3, %xmm4
+; SSE2-NEXT:    cvttsd2si %xmm4, %rcx
+; SSE2-NEXT:    xorq %rax, %rcx
+; SSE2-NEXT:    cvttsd2si %xmm1, %rax
+; SSE2-NEXT:    ucomisd %xmm3, %xmm1
+; SSE2-NEXT:    cmovaeq %rcx, %rax
+; SSE2-NEXT:    movd %rax, %xmm1
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; SSE2-NEXT:    movdqa %xmm2, %xmm1
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptoui_4vf64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
+; AVX-NEXT:    vsubsd %xmm1, %xmm2, %xmm3
+; AVX-NEXT:    vcvttsd2si %xmm3, %rax
+; AVX-NEXT:    movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; AVX-NEXT:    xorq %rcx, %rax
+; AVX-NEXT:    vcvttsd2si %xmm2, %rdx
+; AVX-NEXT:    vucomisd %xmm1, %xmm2
+; AVX-NEXT:    cmovaeq %rax, %rdx
+; AVX-NEXT:    vmovq %rdx, %xmm3
+; AVX-NEXT:    vpermilpd {{.*#+}} xmm2 = xmm2[1,0]
+; AVX-NEXT:    vsubsd %xmm1, %xmm2, %xmm4
+; AVX-NEXT:    vcvttsd2si %xmm4, %rax
+; AVX-NEXT:    xorq %rcx, %rax
+; AVX-NEXT:    vcvttsd2si %xmm2, %rdx
+; AVX-NEXT:    vucomisd %xmm1, %xmm2
+; AVX-NEXT:    cmovaeq %rax, %rdx
+; AVX-NEXT:    vmovq %rdx, %xmm2
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
+; AVX-NEXT:    vsubsd %xmm1, %xmm0, %xmm3
+; AVX-NEXT:    vcvttsd2si %xmm3, %rax
+; AVX-NEXT:    xorq %rcx, %rax
+; AVX-NEXT:    vcvttsd2si %xmm0, %rdx
+; AVX-NEXT:    vucomisd %xmm1, %xmm0
+; AVX-NEXT:    cmovaeq %rax, %rdx
+; AVX-NEXT:    vmovq %rdx, %xmm3
+; AVX-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX-NEXT:    vsubsd %xmm1, %xmm0, %xmm4
+; AVX-NEXT:    vcvttsd2si %xmm4, %rax
+; AVX-NEXT:    xorq %rcx, %rax
+; AVX-NEXT:    vcvttsd2si %xmm0, %rcx
+; AVX-NEXT:    vucomisd %xmm1, %xmm0
+; AVX-NEXT:    cmovaeq %rax, %rcx
+; AVX-NEXT:    vmovq %rcx, %xmm0
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]
+; AVX-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX-NEXT:    retq
+  %cvt = fptoui <4 x double> %a to <4 x i64>
+  ret <4 x i64> %cvt
+}
+
+define <4 x i32> @fptoui_4vf64_i32(<4 x double> %a) {
+; SSE2-LABEL: fptoui_4vf64_i32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movsd {{.*#+}} xmm2 = mem[0],zero
+; SSE2-NEXT:    movapd %xmm1, %xmm3
+; SSE2-NEXT:    subsd %xmm2, %xmm3
+; SSE2-NEXT:    cvttsd2si %xmm3, %rcx
+; SSE2-NEXT:    movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
+; SSE2-NEXT:    xorq %rax, %rcx
+; SSE2-NEXT:    cvttsd2si %xmm1, %rdx
+; SSE2-NEXT:    ucomisd %xmm2, %xmm1
+; SSE2-NEXT:    cmovaeq %rcx, %rdx
+; SSE2-NEXT:    movd %rdx, %xmm3
+; SSE2-NEXT:    shufpd {{.*#+}} xmm1 = xmm1[1,0]
+; SSE2-NEXT:    movapd %xmm1, %xmm4
+; SSE2-NEXT:    subsd %xmm2, %xmm4
+; SSE2-NEXT:    cvttsd2si %xmm4, %rcx
+; SSE2-NEXT:    xorq %rax, %rcx
+; SSE2-NEXT:    cvttsd2si %xmm1, %rdx
+; SSE2-NEXT:    ucomisd %xmm2, %xmm1
+; SSE2-NEXT:    cmovaeq %rcx, %rdx
+; SSE2-NEXT:    movd %rdx, %xmm1
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm1[0]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3]
+; SSE2-NEXT:    movapd %xmm0, %xmm3
+; SSE2-NEXT:    subsd %xmm2, %xmm3
+; SSE2-NEXT:    cvttsd2si %xmm3, %rcx
+; SSE2-NEXT:    xorq %rax, %rcx
+; SSE2-NEXT:    cvttsd2si %xmm0, %rdx
+; SSE2-NEXT:    ucomisd %xmm2, %xmm0
+; SSE2-NEXT:    cmovaeq %rcx, %rdx
+; SSE2-NEXT:    movd %rdx, %xmm3
+; SSE2-NEXT:    shufpd {{.*#+}} xmm0 = xmm0[1,0]
+; SSE2-NEXT:    movapd %xmm0, %xmm4
+; SSE2-NEXT:    subsd %xmm2, %xmm4
+; SSE2-NEXT:    cvttsd2si %xmm4, %rcx
+; SSE2-NEXT:    xorq %rax, %rcx
+; SSE2-NEXT:    cvttsd2si %xmm0, %rax
+; SSE2-NEXT:    ucomisd %xmm2, %xmm0
+; SSE2-NEXT:    cmovaeq %rcx, %rax
+; SSE2-NEXT:    movd %rax, %xmm0
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptoui_4vf64_i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX-NEXT:    vcvttsd2si %xmm1, %rax
+; AVX-NEXT:    vcvttsd2si %xmm0, %rcx
+; AVX-NEXT:    vmovd %ecx, %xmm1
+; AVX-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
+; AVX-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX-NEXT:    vcvttsd2si %xmm0, %rax
+; AVX-NEXT:    vpinsrd $2, %eax, %xmm1, %xmm1
+; AVX-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX-NEXT:    vcvttsd2si %xmm0, %rax
+; AVX-NEXT:    vpinsrd $3, %eax, %xmm1, %xmm0
+; AVX-NEXT:    vzeroupper
+; AVX-NEXT:    retq
+  %cvt = fptoui <4 x double> %a to <4 x i32>
+  ret <4 x i32> %cvt
+}
+
+;
+; Float to Signed Integer
+;
+
+define <4 x i32> @fptosi_4vf32(<4 x float> %a) {
+; SSE2-LABEL: fptosi_4vf32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    cvttps2dq %xmm0, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptosi_4vf32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vcvttps2dq %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %cvt = fptosi <4 x float> %a to <4 x i32>
+  ret <4 x i32> %cvt
+}
+
+define <2 x i64> @fptosi_4vf32_i64(<4 x float> %a) {
+; SSE2-LABEL: fptosi_4vf32_i64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    cvttss2si %xmm0, %rax
+; SSE2-NEXT:    movd %rax, %xmm1
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
+; SSE2-NEXT:    cvttss2si %xmm0, %rax
+; SSE2-NEXT:    movd %rax, %xmm0
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptosi_4vf32_i64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vcvttss2si %xmm0, %rax
+; AVX-NEXT:    vmovq %rax, %xmm1
+; AVX-NEXT:    vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; AVX-NEXT:    vcvttss2si %xmm0, %rax
+; AVX-NEXT:    vmovq %rax, %xmm0
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX-NEXT:    retq
+  %shuf = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> <i32 0, i32 1>
+  %cvt = fptosi <2 x float> %shuf to <2 x i64>
+  ret <2 x i64> %cvt
+}
+
+define <8 x i32> @fptosi_8vf32(<8 x float> %a) {
+; SSE2-LABEL: fptosi_8vf32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    cvttps2dq %xmm0, %xmm0
+; SSE2-NEXT:    cvttps2dq %xmm1, %xmm1
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptosi_8vf32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX-NEXT:    retq
+  %cvt = fptosi <8 x float> %a to <8 x i32>
+  ret <8 x i32> %cvt
+}
+
+define <4 x i64> @fptosi_8vf32_i64(<8 x float> %a) {
+; SSE2-LABEL: fptosi_8vf32_i64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    cvttss2si %xmm0, %rax
+; SSE2-NEXT:    movd %rax, %xmm2
+; SSE2-NEXT:    movaps %xmm0, %xmm1
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
+; SSE2-NEXT:    cvttss2si %xmm1, %rax
+; SSE2-NEXT:    movd %rax, %xmm1
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; SSE2-NEXT:    movaps %xmm0, %xmm1
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,1,2,3]
+; SSE2-NEXT:    cvttss2si %xmm1, %rax
+; SSE2-NEXT:    movd %rax, %xmm3
+; SSE2-NEXT:    shufpd {{.*#+}} xmm0 = xmm0[1,0]
+; SSE2-NEXT:    cvttss2si %xmm0, %rax
+; SSE2-NEXT:    movd %rax, %xmm1
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
+; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptosi_8vf32_i64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
+; AVX-NEXT:    vcvttss2si %xmm1, %rax
+; AVX-NEXT:    vmovq %rax, %xmm1
+; AVX-NEXT:    vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
+; AVX-NEXT:    vcvttss2si %xmm2, %rax
+; AVX-NEXT:    vmovq %rax, %xmm2
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; AVX-NEXT:    vcvttss2si %xmm0, %rax
+; AVX-NEXT:    vmovq %rax, %xmm2
+; AVX-NEXT:    vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; AVX-NEXT:    vcvttss2si %xmm0, %rax
+; AVX-NEXT:    vmovq %rax, %xmm0
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
+; AVX-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX-NEXT:    retq
+  %shuf = shufflevector <8 x float> %a, <8 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %cvt = fptosi <4 x float> %shuf to <4 x i64>
+  ret <4 x i64> %cvt
+}
+
+;
+; Float to Unsigned Integer
+;
+
+define <4 x i32> @fptoui_4vf32(<4 x float> %a) {
+; SSE2-LABEL: fptoui_4vf32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps %xmm0, %xmm1
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,1,2,3]
+; SSE2-NEXT:    cvttss2si %xmm1, %rax
+; SSE2-NEXT:    movd %eax, %xmm1
+; SSE2-NEXT:    movaps %xmm0, %xmm2
+; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,1,2,3]
+; SSE2-NEXT:    cvttss2si %xmm2, %rax
+; SSE2-NEXT:    movd %eax, %xmm2
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; SSE2-NEXT:    cvttss2si %xmm0, %rax
+; SSE2-NEXT:    movd %eax, %xmm1
+; SSE2-NEXT:    shufpd {{.*#+}} xmm0 = xmm0[1,0]
+; SSE2-NEXT:    cvttss2si %xmm0, %rax
+; SSE2-NEXT:    movd %eax, %xmm0
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptoui_4vf32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; AVX-NEXT:    vcvttss2si %xmm1, %rax
+; AVX-NEXT:    vcvttss2si %xmm0, %rcx
+; AVX-NEXT:    vmovd %ecx, %xmm1
+; AVX-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
+; AVX-NEXT:    vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
+; AVX-NEXT:    vcvttss2si %xmm2, %rax
+; AVX-NEXT:    vpinsrd $2, %eax, %xmm1, %xmm1
+; AVX-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3]
+; AVX-NEXT:    vcvttss2si %xmm0, %rax
+; AVX-NEXT:    vpinsrd $3, %eax, %xmm1, %xmm0
+; AVX-NEXT:    retq
+  %cvt = fptoui <4 x float> %a to <4 x i32>
+  ret <4 x i32> %cvt
+}
+
+define <2 x i64> @fptoui_4vf32_i64(<4 x float> %a) {
+; SSE2-LABEL: fptoui_4vf32_i64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE2-NEXT:    movaps %xmm0, %xmm1
+; SSE2-NEXT:    subss %xmm2, %xmm1
+; SSE2-NEXT:    cvttss2si %xmm1, %rax
+; SSE2-NEXT:    movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE2-NEXT:    xorq %rcx, %rax
+; SSE2-NEXT:    cvttss2si %xmm0, %rdx
+; SSE2-NEXT:    ucomiss %xmm2, %xmm0
+; SSE2-NEXT:    cmovaeq %rax, %rdx
+; SSE2-NEXT:    movd %rdx, %xmm1
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
+; SSE2-NEXT:    movaps %xmm0, %xmm3
+; SSE2-NEXT:    subss %xmm2, %xmm3
+; SSE2-NEXT:    cvttss2si %xmm3, %rax
+; SSE2-NEXT:    xorq %rcx, %rax
+; SSE2-NEXT:    cvttss2si %xmm0, %rcx
+; SSE2-NEXT:    ucomiss %xmm2, %xmm0
+; SSE2-NEXT:    cmovaeq %rax, %rcx
+; SSE2-NEXT:    movd %rcx, %xmm0
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptoui_4vf32_i64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX-NEXT:    vsubss %xmm1, %xmm0, %xmm2
+; AVX-NEXT:    vcvttss2si %xmm2, %rax
+; AVX-NEXT:    movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; AVX-NEXT:    xorq %rcx, %rax
+; AVX-NEXT:    vcvttss2si %xmm0, %rdx
+; AVX-NEXT:    vucomiss %xmm1, %xmm0
+; AVX-NEXT:    cmovaeq %rax, %rdx
+; AVX-NEXT:    vmovq %rdx, %xmm2
+; AVX-NEXT:    vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; AVX-NEXT:    vsubss %xmm1, %xmm0, %xmm3
+; AVX-NEXT:    vcvttss2si %xmm3, %rax
+; AVX-NEXT:    xorq %rcx, %rax
+; AVX-NEXT:    vcvttss2si %xmm0, %rcx
+; AVX-NEXT:    vucomiss %xmm1, %xmm0
+; AVX-NEXT:    cmovaeq %rax, %rcx
+; AVX-NEXT:    vmovq %rcx, %xmm0
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
+; AVX-NEXT:    retq
+  %shuf = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> <i32 0, i32 1>
+  %cvt = fptoui <2 x float> %shuf to <2 x i64>
+  ret <2 x i64> %cvt
+}
+
+define <8 x i32> @fptoui_8vf32(<8 x float> %a) {
+; SSE2-LABEL: fptoui_8vf32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps %xmm0, %xmm2
+; SSE2-NEXT:    {{.*#+}} kill: XMM0<def> XMM2<kill>
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
+; SSE2-NEXT:    cvttss2si %xmm0, %rax
+; SSE2-NEXT:    movd %eax, %xmm0
+; SSE2-NEXT:    movaps %xmm2, %xmm3
+; SSE2-NEXT:    shufps {{.*#+}} xmm3 = xmm3[1,1,2,3]
+; SSE2-NEXT:    cvttss2si %xmm3, %rax
+; SSE2-NEXT:    movd %eax, %xmm3
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
+; SSE2-NEXT:    cvttss2si %xmm2, %rax
+; SSE2-NEXT:    movd %eax, %xmm0
+; SSE2-NEXT:    shufpd {{.*#+}} xmm2 = xmm2[1,0]
+; SSE2-NEXT:    cvttss2si %xmm2, %rax
+; SSE2-NEXT:    movd %eax, %xmm2
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
+; SSE2-NEXT:    movaps %xmm1, %xmm2
+; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[3,1,2,3]
+; SSE2-NEXT:    cvttss2si %xmm2, %rax
+; SSE2-NEXT:    movd %eax, %xmm2
+; SSE2-NEXT:    movaps %xmm1, %xmm3
+; SSE2-NEXT:    shufps {{.*#+}} xmm3 = xmm3[1,1,2,3]
+; SSE2-NEXT:    cvttss2si %xmm3, %rax
+; SSE2-NEXT:    movd %eax, %xmm3
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; SSE2-NEXT:    cvttss2si %xmm1, %rax
+; SSE2-NEXT:    movd %eax, %xmm2
+; SSE2-NEXT:    shufpd {{.*#+}} xmm1 = xmm1[1,0]
+; SSE2-NEXT:    cvttss2si %xmm1, %rax
+; SSE2-NEXT:    movd %eax, %xmm1
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
+; SSE2-NEXT:    movdqa %xmm2, %xmm1
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptoui_8vf32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX-NEXT:    vmovshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
+; AVX-NEXT:    vcvttss2si %xmm2, %rax
+; AVX-NEXT:    vcvttss2si %xmm1, %rcx
+; AVX-NEXT:    vmovd %ecx, %xmm2
+; AVX-NEXT:    vpinsrd $1, %eax, %xmm2, %xmm2
+; AVX-NEXT:    vpermilpd {{.*#+}} xmm3 = xmm1[1,0]
+; AVX-NEXT:    vcvttss2si %xmm3, %rax
+; AVX-NEXT:    vpinsrd $2, %eax, %xmm2, %xmm2
+; AVX-NEXT:    vpermilps {{.*#+}} xmm1 = xmm1[3,1,2,3]
+; AVX-NEXT:    vcvttss2si %xmm1, %rax
+; AVX-NEXT:    vpinsrd $3, %eax, %xmm2, %xmm1
+; AVX-NEXT:    vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; AVX-NEXT:    vcvttss2si %xmm2, %rax
+; AVX-NEXT:    vcvttss2si %xmm0, %rcx
+; AVX-NEXT:    vmovd %ecx, %xmm2
+; AVX-NEXT:    vpinsrd $1, %eax, %xmm2, %xmm2
+; AVX-NEXT:    vpermilpd {{.*#+}} xmm3 = xmm0[1,0]
+; AVX-NEXT:    vcvttss2si %xmm3, %rax
+; AVX-NEXT:    vpinsrd $2, %eax, %xmm2, %xmm2
+; AVX-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3]
+; AVX-NEXT:    vcvttss2si %xmm0, %rax
+; AVX-NEXT:    vpinsrd $3, %eax, %xmm2, %xmm0
+; AVX-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX-NEXT:    retq
+  %cvt = fptoui <8 x float> %a to <8 x i32>
+  ret <8 x i32> %cvt
+}
+
+define <4 x i64> @fptoui_8vf32_i64(<8 x float> %a) {
+; SSE2-LABEL: fptoui_8vf32_i64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-NEXT:    movaps %xmm0, %xmm2
+; SSE2-NEXT:    subss %xmm1, %xmm2
+; SSE2-NEXT:    cvttss2si %xmm2, %rcx
+; SSE2-NEXT:    movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
+; SSE2-NEXT:    xorq %rax, %rcx
+; SSE2-NEXT:    cvttss2si %xmm0, %rdx
+; SSE2-NEXT:    ucomiss %xmm1, %xmm0
+; SSE2-NEXT:    cmovaeq %rcx, %rdx
+; SSE2-NEXT:    movd %rdx, %xmm2
+; SSE2-NEXT:    movaps %xmm0, %xmm3
+; SSE2-NEXT:    shufps {{.*#+}} xmm3 = xmm3[1,1,2,3]
+; SSE2-NEXT:    movaps %xmm3, %xmm4
+; SSE2-NEXT:    subss %xmm1, %xmm4
+; SSE2-NEXT:    cvttss2si %xmm4, %rcx
+; SSE2-NEXT:    xorq %rax, %rcx
+; SSE2-NEXT:    cvttss2si %xmm3, %rdx
+; SSE2-NEXT:    ucomiss %xmm1, %xmm3
+; SSE2-NEXT:    cmovaeq %rcx, %rdx
+; SSE2-NEXT:    movd %rdx, %xmm3
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
+; SSE2-NEXT:    movaps %xmm0, %xmm3
+; SSE2-NEXT:    shufps {{.*#+}} xmm3 = xmm3[3,1,2,3]
+; SSE2-NEXT:    movaps %xmm3, %xmm4
+; SSE2-NEXT:    subss %xmm1, %xmm4
+; SSE2-NEXT:    cvttss2si %xmm4, %rcx
+; SSE2-NEXT:    xorq %rax, %rcx
+; SSE2-NEXT:    cvttss2si %xmm3, %rdx
+; SSE2-NEXT:    ucomiss %xmm1, %xmm3
+; SSE2-NEXT:    cmovaeq %rcx, %rdx
+; SSE2-NEXT:    movd %rdx, %xmm3
+; SSE2-NEXT:    shufpd {{.*#+}} xmm0 = xmm0[1,0]
+; SSE2-NEXT:    movapd %xmm0, %xmm4
+; SSE2-NEXT:    subss %xmm1, %xmm4
+; SSE2-NEXT:    cvttss2si %xmm4, %rcx
+; SSE2-NEXT:    xorq %rax, %rcx
+; SSE2-NEXT:    cvttss2si %xmm0, %rax
+; SSE2-NEXT:    ucomiss %xmm1, %xmm0
+; SSE2-NEXT:    cmovaeq %rcx, %rax
+; SSE2-NEXT:    movd %rax, %xmm1
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
+; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptoui_8vf32_i64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpermilps {{.*#+}} xmm2 = xmm0[3,1,2,3]
+; AVX-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX-NEXT:    vsubss %xmm1, %xmm2, %xmm3
+; AVX-NEXT:    vcvttss2si %xmm3, %rax
+; AVX-NEXT:    movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; AVX-NEXT:    xorq %rcx, %rax
+; AVX-NEXT:    vcvttss2si %xmm2, %rdx
+; AVX-NEXT:    vucomiss %xmm1, %xmm2
+; AVX-NEXT:    cmovaeq %rax, %rdx
+; AVX-NEXT:    vmovq %rdx, %xmm2
+; AVX-NEXT:    vpermilpd {{.*#+}} xmm3 = xmm0[1,0]
+; AVX-NEXT:    vsubss %xmm1, %xmm3, %xmm4
+; AVX-NEXT:    vcvttss2si %xmm4, %rax
+; AVX-NEXT:    xorq %rcx, %rax
+; AVX-NEXT:    vcvttss2si %xmm3, %rdx
+; AVX-NEXT:    vucomiss %xmm1, %xmm3
+; AVX-NEXT:    cmovaeq %rax, %rdx
+; AVX-NEXT:    vmovq %rdx, %xmm3
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
+; AVX-NEXT:    vsubss %xmm1, %xmm0, %xmm3
+; AVX-NEXT:    vcvttss2si %xmm3, %rax
+; AVX-NEXT:    xorq %rcx, %rax
+; AVX-NEXT:    vcvttss2si %xmm0, %rdx
+; AVX-NEXT:    vucomiss %xmm1, %xmm0
+; AVX-NEXT:    cmovaeq %rax, %rdx
+; AVX-NEXT:    vmovq %rdx, %xmm3
+; AVX-NEXT:    vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; AVX-NEXT:    vsubss %xmm1, %xmm0, %xmm4
+; AVX-NEXT:    vcvttss2si %xmm4, %rax
+; AVX-NEXT:    xorq %rcx, %rax
+; AVX-NEXT:    vcvttss2si %xmm0, %rcx
+; AVX-NEXT:    vucomiss %xmm1, %xmm0
+; AVX-NEXT:    cmovaeq %rax, %rcx
+; AVX-NEXT:    vmovq %rcx, %xmm0
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]
+; AVX-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX-NEXT:    retq
+  %shuf = shufflevector <8 x float> %a, <8 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %cvt = fptoui <4 x float> %shuf to <4 x i64>
+  ret <4 x i64> %cvt
+}
+
+;
+; Constant Folding
+;
+
+define <2 x i64> @fptosi_2vf64c() {
+; SSE2-LABEL: fptosi_2vf64c:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm0 = [1,18446744073709551615]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptosi_2vf64c:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [1,18446744073709551615]
+; AVX-NEXT:    retq
+  %cvt = fptosi <2 x double> <double 1.0, double -1.0> to <2 x i64>
+  ret <2 x i64> %cvt
+}
+
+define <4 x i32> @fptosi_2vf64c_i32() {
+; SSE2-LABEL: fptosi_2vf64c_i32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm0 = <4294967295,1,u,u>
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptosi_2vf64c_i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = <4294967295,1,u,u>
+; AVX-NEXT:    retq
+  %cvt = fptosi <2 x double> <double -1.0, double 1.0> to <2 x i32>
+  %ext = shufflevector <2 x i32> %cvt, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  ret <4 x i32> %ext
+}
+
+define <4 x i64> @fptosi_4vf64c() {
+; SSE2-LABEL: fptosi_4vf64c:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm0 = [1,18446744073709551615]
+; SSE2-NEXT:    movaps {{.*#+}} xmm1 = [2,18446744073709551613]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptosi_4vf64c:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [1,18446744073709551615,2,18446744073709551613]
+; AVX-NEXT:    retq
+  %cvt = fptosi <4 x double> <double 1.0, double -1.0, double 2.0, double -3.0> to <4 x i64>
+  ret <4 x i64> %cvt
+}
+
+define <4 x i32> @fptosi_4vf64c_i32() {
+; SSE2-LABEL: fptosi_4vf64c_i32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm0 = [4294967295,1,4294967294,3]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptosi_4vf64c_i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [4294967295,1,4294967294,3]
+; AVX-NEXT:    retq
+  %cvt = fptosi <4 x double> <double -1.0, double 1.0, double -2.0, double 3.0> to <4 x i32>
+  ret <4 x i32> %cvt
+}
+
+define <2 x i64> @fptoui_2vf64c() {
+; SSE2-LABEL: fptoui_2vf64c:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm0 = [2,4]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptoui_2vf64c:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [2,4]
+; AVX-NEXT:    retq
+  %cvt = fptoui <2 x double> <double 2.0, double 4.0> to <2 x i64>
+  ret <2 x i64> %cvt
+}
+
+define <4 x i32> @fptoui_2vf64c_i32(<2 x double> %a) {
+; SSE2-LABEL: fptoui_2vf64c_i32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm0 = <2,4,u,u>
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptoui_2vf64c_i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = <2,4,u,u>
+; AVX-NEXT:    retq
+  %cvt = fptoui <2 x double> <double 2.0, double 4.0> to <2 x i32>
+  %ext = shufflevector <2 x i32> %cvt, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  ret <4 x i32> %ext
+}
+
+define <4 x i64> @fptoui_4vf64c(<4 x double> %a) {
+; SSE2-LABEL: fptoui_4vf64c:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm0 = [2,4]
+; SSE2-NEXT:    movaps {{.*#+}} xmm1 = [6,8]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptoui_4vf64c:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [2,4,6,8]
+; AVX-NEXT:    retq
+  %cvt = fptoui <4 x double> <double 2.0, double 4.0, double 6.0, double 8.0> to <4 x i64>
+  ret <4 x i64> %cvt
+}
+
+define <4 x i32> @fptoui_4vf64c_i32(<4 x double> %a) {
+; SSE2-LABEL: fptoui_4vf64c_i32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm0 = [2,4,6,8]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptoui_4vf64c_i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [2,4,6,8]
+; AVX-NEXT:    retq
+  %cvt = fptoui <4 x double> <double 2.0, double 4.0, double 6.0, double 8.0> to <4 x i32>
+  ret <4 x i32> %cvt
+}
+
+define <4 x i32> @fptosi_4vf32c() {
+; SSE2-LABEL: fptosi_4vf32c:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm0 = [1,4294967295,2,3]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptosi_4vf32c:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [1,4294967295,2,3]
+; AVX-NEXT:    retq
+  %cvt = fptosi <4 x float> <float 1.0, float -1.0, float 2.0, float 3.0> to <4 x i32>
+  ret <4 x i32> %cvt
+}
+
+define <4 x i64> @fptosi_4vf32c_i64() {
+; SSE2-LABEL: fptosi_4vf32c_i64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm0 = [1,18446744073709551615]
+; SSE2-NEXT:    movaps {{.*#+}} xmm1 = [2,3]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptosi_4vf32c_i64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [1,18446744073709551615,2,3]
+; AVX-NEXT:    retq
+  %cvt = fptosi <4 x float> <float 1.0, float -1.0, float 2.0, float 3.0> to <4 x i64>
+  ret <4 x i64> %cvt
+}
+
+define <8 x i32> @fptosi_8vf32c(<8 x float> %a) {
+; SSE2-LABEL: fptosi_8vf32c:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm0 = [1,4294967295,2,3]
+; SSE2-NEXT:    movaps {{.*#+}} xmm1 = [6,4294967288,2,4294967295]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptosi_8vf32c:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [1,4294967295,2,3,6,4294967288,2,4294967295]
+; AVX-NEXT:    retq
+  %cvt = fptosi <8 x float> <float 1.0, float -1.0, float 2.0, float 3.0, float 6.0, float -8.0, float 2.0, float -1.0> to <8 x i32>
+  ret <8 x i32> %cvt
+}
+
+define <4 x i32> @fptoui_4vf32c(<4 x float> %a) {
+; SSE2-LABEL: fptoui_4vf32c:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm0 = [1,2,4,6]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptoui_4vf32c:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [1,2,4,6]
+; AVX-NEXT:    retq
+  %cvt = fptoui <4 x float> <float 1.0, float 2.0, float 4.0, float 6.0> to <4 x i32>
+  ret <4 x i32> %cvt
+}
+
+define <4 x i64> @fptoui_4vf32c_i64() {
+; SSE2-LABEL: fptoui_4vf32c_i64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm0 = [1,2]
+; SSE2-NEXT:    movaps {{.*#+}} xmm1 = [4,8]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptoui_4vf32c_i64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [1,2,4,8]
+; AVX-NEXT:    retq
+  %cvt = fptoui <4 x float> <float 1.0, float 2.0, float 4.0, float 8.0> to <4 x i64>
+  ret <4 x i64> %cvt
+}
+
+define <8 x i32> @fptoui_8vf32c(<8 x float> %a) {
+; SSE2-LABEL: fptoui_8vf32c:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm0 = [1,2,4,6]
+; SSE2-NEXT:    movaps {{.*#+}} xmm1 = [8,6,4,1]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: fptoui_8vf32c:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [1,2,4,6,8,6,4,1]
+; AVX-NEXT:    retq
+  %cvt = fptoui <8 x float> <float 1.0, float 2.0, float 4.0, float 6.0, float 8.0, float 6.0, float 4.0, float 1.0> to <8 x i32>
+  ret <8 x i32> %cvt
+}
diff --git a/test/CodeGen/X86/vec_fpext.ll b/test/CodeGen/X86/vec_fpext.ll
index b882a5e272b5..bb5409b91ee4 100644
--- a/test/CodeGen/X86/vec_fpext.ll
+++ b/test/CodeGen/X86/vec_fpext.ll
@@ -8,7 +8,7 @@ define void @fpext_frommem(<2 x float>* %in, <2 x double>* %out) {
 entry:
 ; CHECK: cvtps2pd (%{{.+}}), %xmm{{[0-9]+}}
 ; AVX: vcvtps2pd (%{{.+}}), %xmm{{[0-9]+}}
-  %0 = load <2 x float>* %in, align 8
+  %0 = load <2 x float>, <2 x float>* %in, align 8
   %1 = fpext <2 x float> %0 to <2 x double>
   store <2 x double> %1, <2 x double>* %out, align 1
   ret void
@@ -21,7 +21,7 @@ entry:
 ; CHECK: cvtps2pd (%{{.+}}), %xmm{{[0-9]+}}
 ; CHECK: cvtps2pd 8(%{{.+}}), %xmm{{[0-9]+}}
 ; AVX: vcvtps2pd (%{{.+}}), %ymm{{[0-9]+}}
-  %0 = load <4 x float>* %in
+  %0 = load <4 x float>, <4 x float>* %in
   %1 = fpext <4 x float> %0 to <4 x double>
   store <4 x double> %1, <4 x double>* %out, align 1
   ret void
@@ -37,8 +37,20 @@ entry:
 ; CHECK: cvtps2pd 24(%{{.+}}), %xmm{{[0-9]+}}
 ; AVX: vcvtps2pd 16(%{{.+}}), %ymm{{[0-9]+}}
 ; AVX: vcvtps2pd (%{{.+}}), %ymm{{[0-9]+}}
-  %0 = load <8 x float>* %in
+  %0 = load <8 x float>, <8 x float>* %in
   %1 = fpext <8 x float> %0 to <8 x double>
   store <8 x double> %1, <8 x double>* %out, align 1
   ret void
 }
+
+define <2 x double> @fpext_fromconst() {
+; CHECK-LABEL: fpext_fromconst:
+; AVX-LABEL: fpext_fromconst:
+entry:
+; CHECK: movaps {{.*#+}} xmm0 = [1.000000e+00,-2.000000e+00]
+; AVX: vmovaps {{.*#+}} xmm0 = [1.000000e+00,-2.000000e+00]
+  %0  = insertelement <2 x float> undef, float 1.0, i32 0
+  %1  = insertelement <2 x float> %0, float -2.0, i32 1
+  %2  = fpext <2 x float> %1 to <2 x double>
+  ret <2 x double> %2
+}
diff --git a/test/CodeGen/X86/vec_i64.ll b/test/CodeGen/X86/vec_i64.ll
index 462e16e13023..48ca1ff021d9 100644
--- a/test/CodeGen/X86/vec_i64.ll
+++ b/test/CodeGen/X86/vec_i64.ll
@@ -5,7 +5,7 @@
 
 define <2 x i64> @foo1(i64* %y) nounwind  {
 entry:
-	%tmp1 = load i64* %y, align 8		; <i64> [#uses=1]
+	%tmp1 = load i64, i64* %y, align 8		; <i64> [#uses=1]
 	%s2v = insertelement <2 x i64> undef, i64 %tmp1, i32 0
 	%loadl = shufflevector <2 x i64> zeroinitializer, <2 x i64> %s2v, <2 x i32> <i32 2, i32 1>
 	ret <2 x i64> %loadl
@@ -14,7 +14,7 @@ entry:
 
 define <4 x float> @foo2(i64* %p) nounwind {
 entry:
-	%load = load i64* %p
+	%load = load i64, i64* %p
 	%s2v = insertelement <2 x i64> undef, i64 %load, i32 0
 	%loadl = shufflevector <2 x i64> zeroinitializer, <2 x i64> %s2v, <2 x i32> <i32 2, i32 1>
 	%0 = bitcast <2 x i64> %loadl to <4 x float>
diff --git a/test/CodeGen/X86/vec_ins_extract.ll b/test/CodeGen/X86/vec_ins_extract.ll
index daf222e395bf..e92f46dbabb5 100644
--- a/test/CodeGen/X86/vec_ins_extract.ll
+++ b/test/CodeGen/X86/vec_ins_extract.ll
@@ -7,7 +7,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 
 define void @test(<4 x float>* %F, float %f) {
 entry:
-	%tmp = load <4 x float>* %F		; <<4 x float>> [#uses=2]
+	%tmp = load <4 x float>, <4 x float>* %F		; <<4 x float>> [#uses=2]
 	%tmp3 = fadd <4 x float> %tmp, %tmp		; <<4 x float>> [#uses=1]
 	%tmp10 = insertelement <4 x float> %tmp3, float %f, i32 0		; <<4 x float>> [#uses=2]
 	%tmp6 = fadd <4 x float> %tmp10, %tmp10		; <<4 x float>> [#uses=1]
@@ -18,12 +18,12 @@ entry:
 define void @test2(<4 x float>* %F, float %f) {
 entry:
 	%G = alloca <4 x float>, align 16		; <<4 x float>*> [#uses=3]
-	%tmp = load <4 x float>* %F		; <<4 x float>> [#uses=2]
+	%tmp = load <4 x float>, <4 x float>* %F		; <<4 x float>> [#uses=2]
 	%tmp3 = fadd <4 x float> %tmp, %tmp		; <<4 x float>> [#uses=1]
 	store <4 x float> %tmp3, <4 x float>* %G
-	%tmp.upgrd.1 = getelementptr <4 x float>* %G, i32 0, i32 2		; <float*> [#uses=1]
+	%tmp.upgrd.1 = getelementptr <4 x float>, <4 x float>* %G, i32 0, i32 2		; <float*> [#uses=1]
 	store float %f, float* %tmp.upgrd.1
-	%tmp4 = load <4 x float>* %G		; <<4 x float>> [#uses=2]
+	%tmp4 = load <4 x float>, <4 x float>* %G		; <<4 x float>> [#uses=2]
 	%tmp6 = fadd <4 x float> %tmp4, %tmp4		; <<4 x float>> [#uses=1]
 	store <4 x float> %tmp6, <4 x float>* %F
 	ret void
@@ -32,18 +32,18 @@ entry:
 define void @test3(<4 x float>* %F, float* %f) {
 entry:
 	%G = alloca <4 x float>, align 16		; <<4 x float>*> [#uses=2]
-	%tmp = load <4 x float>* %F		; <<4 x float>> [#uses=2]
+	%tmp = load <4 x float>, <4 x float>* %F		; <<4 x float>> [#uses=2]
 	%tmp3 = fadd <4 x float> %tmp, %tmp		; <<4 x float>> [#uses=1]
 	store <4 x float> %tmp3, <4 x float>* %G
-	%tmp.upgrd.2 = getelementptr <4 x float>* %G, i32 0, i32 2		; <float*> [#uses=1]
-	%tmp.upgrd.3 = load float* %tmp.upgrd.2		; <float> [#uses=1]
+	%tmp.upgrd.2 = getelementptr <4 x float>, <4 x float>* %G, i32 0, i32 2		; <float*> [#uses=1]
+	%tmp.upgrd.3 = load float, float* %tmp.upgrd.2		; <float> [#uses=1]
 	store float %tmp.upgrd.3, float* %f
 	ret void
 }
 
 define void @test4(<4 x float>* %F, float* %f) {
 entry:
-	%tmp = load <4 x float>* %F		; <<4 x float>> [#uses=2]
+	%tmp = load <4 x float>, <4 x float>* %F		; <<4 x float>> [#uses=2]
 	%tmp5.lhs = extractelement <4 x float> %tmp, i32 0		; <float> [#uses=1]
 	%tmp5.rhs = extractelement <4 x float> %tmp, i32 0		; <float> [#uses=1]
 	%tmp5 = fadd float %tmp5.lhs, %tmp5.rhs		; <float> [#uses=1]
diff --git a/test/CodeGen/X86/vec_insert-3.ll b/test/CodeGen/X86/vec_insert-3.ll
index a8713398e955..75244ae0b71a 100644
--- a/test/CodeGen/X86/vec_insert-3.ll
+++ b/test/CodeGen/X86/vec_insert-3.ll
@@ -1,6 +1,10 @@
-; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse4.1 | grep punpcklqdq | count 1
+; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse4.1 | FileCheck %s
 
 define <2 x i64> @t1(i64 %s, <2 x i64> %tmp) nounwind {
-        %tmp1 = insertelement <2 x i64> %tmp, i64 %s, i32 1
-        ret <2 x i64> %tmp1
+; CHECK-LABEL: t1:
+; CHECK:  punpcklqdq 
+; CHECK-NEXT:  retq 
+
+  %tmp1 = insertelement <2 x i64> %tmp, i64 %s, i32 1
+  ret <2 x i64> %tmp1
 }
diff --git a/test/CodeGen/X86/vec_insert-5.ll b/test/CodeGen/X86/vec_insert-5.ll
index b72044aee30b..4018a21090e7 100644
--- a/test/CodeGen/X86/vec_insert-5.ll
+++ b/test/CodeGen/X86/vec_insert-5.ll
@@ -8,8 +8,8 @@ define void  @t1(i32 %a, x86_mmx* %P) nounwind {
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    shll $12, %ecx
 ; CHECK-NEXT:    movd %ecx, %xmm0
-; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,0,0,1]
-; CHECK-NEXT:    movlpd %xmm0, (%eax)
+; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
+; CHECK-NEXT:    movq %xmm0, (%eax)
 ; CHECK-NEXT:    retl
  %tmp12 = shl i32 %a, 12
  %tmp21 = insertelement <2 x i32> undef, i32 %tmp12, i32 1
@@ -25,10 +25,10 @@ define <4 x float> @t2(<4 x float>* %P) nounwind {
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movaps (%eax), %xmm1
 ; CHECK-NEXT:    xorps %xmm0, %xmm0
-; CHECK-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
-; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0]
+; CHECK-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
+; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
 ; CHECK-NEXT:    retl
-  %tmp1 = load <4 x float>* %P
+  %tmp1 = load <4 x float>, <4 x float>* %P
   %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 4, i32 4, i32 4, i32 0 >
   ret <4 x float> %tmp2
 }
@@ -37,11 +37,11 @@ define <4 x float> @t3(<4 x float>* %P) nounwind {
 ; CHECK-LABEL: t3:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    movaps (%eax), %xmm0
-; CHECK-NEXT:    xorps %xmm1, %xmm1
-; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,3],xmm1[0,0]
+; CHECK-NEXT:    movapd (%eax), %xmm0
+; CHECK-NEXT:    xorpd %xmm1, %xmm1
+; CHECK-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
 ; CHECK-NEXT:    retl
-  %tmp1 = load <4 x float>* %P
+  %tmp1 = load <4 x float>, <4 x float>* %P
   %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 2, i32 3, i32 4, i32 4 >
   ret <4 x float> %tmp2
 }
@@ -52,10 +52,10 @@ define <4 x float> @t4(<4 x float>* %P) nounwind {
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movaps (%eax), %xmm0
 ; CHECK-NEXT:    xorps %xmm1, %xmm1
-; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[0,0]
-; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,0]
+; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[1,0]
+; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
 ; CHECK-NEXT:    retl
-  %tmp1 = load <4 x float>* %P
+  %tmp1 = load <4 x float>, <4 x float>* %P
   %tmp2 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp1, <4 x i32> < i32 7, i32 0, i32 0, i32 0 >
   ret <4 x float> %tmp2
 }
@@ -63,7 +63,7 @@ define <4 x float> @t4(<4 x float>* %P) nounwind {
 define <16 x i8> @t5(<16 x i8> %x) nounwind {
 ; CHECK-LABEL: t5:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    psrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero
+; CHECK-NEXT:    psrlw $8, %xmm0
 ; CHECK-NEXT:    retl
   %s = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 17>
   ret <16 x i8> %s
@@ -72,7 +72,7 @@ define <16 x i8> @t5(<16 x i8> %x) nounwind {
 define <16 x i8> @t6(<16 x i8> %x) nounwind {
 ; CHECK-LABEL: t6:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    psrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero
+; CHECK-NEXT:    psrlw $8, %xmm0
 ; CHECK-NEXT:    retl
   %s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   ret <16 x i8> %s
@@ -86,3 +86,21 @@ define <16 x i8> @t7(<16 x i8> %x) nounwind {
   %s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2>
   ret <16 x i8> %s
 }
+
+define <16 x i8> @t8(<16 x i8> %x) nounwind {
+; CHECK-LABEL: t8:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    psrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero
+; CHECK-NEXT:    retl
+  %s = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 17>
+  ret <16 x i8> %s
+}
+
+define <16 x i8> @t9(<16 x i8> %x) nounwind {
+; CHECK-LABEL: t9:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    psrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero
+; CHECK-NEXT:    retl
+  %s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 7, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 14, i32 undef, i32 undef>
+  ret <16 x i8> %s
+}
diff --git a/test/CodeGen/X86/vec_insert-mmx.ll b/test/CodeGen/X86/vec_insert-mmx.ll
new file mode 100644
index 000000000000..cbd420885ac1
--- /dev/null
+++ b/test/CodeGen/X86/vec_insert-mmx.ll
@@ -0,0 +1,58 @@
+; RUN: llc < %s -mtriple=i686-darwin -mattr=+mmx,+sse2 | FileCheck %s -check-prefix=X86-32
+; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse4.1 | FileCheck %s -check-prefix=X86-64
+
+; This is not an MMX operation; promoted to XMM.
+define x86_mmx @t0(i32 %A) nounwind {
+; X86-32-LABEL: t0:
+; X86-32:       ## BB#0:
+; X86-32:    movd {{[0-9]+}}(%esp), %xmm0
+; X86-32-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
+; X86-32-NEXT:    movq %xmm0, (%esp)
+; X86-32-NEXT:    movq (%esp), %mm0
+; X86-32-NEXT:    addl $12, %esp
+; X86-32-NEXT:    retl
+  %tmp3 = insertelement <2 x i32> < i32 0, i32 undef >, i32 %A, i32 1
+  %tmp4 = bitcast <2 x i32> %tmp3 to x86_mmx
+  ret x86_mmx %tmp4
+}
+
+define <8 x i8> @t1(i8 zeroext %x) nounwind {
+; X86-32-LABEL: t1:
+; X86-32:       ## BB#0:
+; X86-32-NOT:  movl
+; X86-32-NEXT:    movd {{[0-9]+}}(%esp), %xmm0
+; X86-32-NEXT:    retl
+  %r = insertelement <8 x i8> undef, i8 %x, i32 0
+  ret <8 x i8> %r
+}
+
+; PR2574
+define <2 x float> @t2(<2 x float> %a0) {
+; X86-32-LABEL: t2:
+; X86-32:       ## BB#0:
+; X86-32-NEXT:    xorps %xmm0, %xmm0
+; X86-32-NEXT:    retl
+  %v1 = insertelement <2 x float> %a0, float 0.000000e+00, i32 0
+  %v2 = insertelement <2 x float> %v1, float 0.000000e+00, i32 1
+  ret <2 x float> %v2
+}
+
+@g0 = external global i16
+@g1 = external global <4 x i16>
+
+; PR2562
+define void @t3() {
+; X86-64-LABEL: t3:
+; X86-64:       ## BB#0:
+; X86-64:    pmovzxwd (%rcx)
+; X86-64-NEXT:    movzwl
+; X86-64-NEXT:    pinsrd $0
+; X86-64-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; X86-64-NEXT:    movq %xmm0
+; X86-64-NEXT:    retq
+  load i16, i16* @g0
+  load <4 x i16>, <4 x i16>* @g1
+  insertelement <4 x i16> %2, i16 %1, i32 0
+  store <4 x i16> %3, <4 x i16>* @g1
+  ret void
+}
diff --git a/test/CodeGen/X86/vec_int_to_fp.ll b/test/CodeGen/X86/vec_int_to_fp.ll
new file mode 100644
index 000000000000..5052ff51092e
--- /dev/null
+++ b/test/CodeGen/X86/vec_int_to_fp.ll
@@ -0,0 +1,714 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL  --check-prefix=AVX
+
+;
+; Signed Integer to Double
+;
+
+define <2 x double> @sitofp_2vf64(<2 x i64> %a) {
+; SSE2-LABEL: sitofp_2vf64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movd %xmm0, %rax
+; SSE2-NEXT:    cvtsi2sdq %rax, %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; SSE2-NEXT:    movd %xmm0, %rax
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2sdq %rax, %xmm0
+; SSE2-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE2-NEXT:    movapd %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: sitofp_2vf64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpextrq $1, %xmm0, %rax
+; AVX-NEXT:    vcvtsi2sdq %rax, %xmm0, %xmm1
+; AVX-NEXT:    vmovq %xmm0, %rax
+; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vcvtsi2sdq %rax, %xmm0, %xmm0
+; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX-NEXT:    retq
+  %cvt = sitofp <2 x i64> %a to <2 x double>
+  ret <2 x double> %cvt
+}
+
+define <2 x double> @sitofp_2vf64_i32(<4 x i32> %a) {
+; SSE2-LABEL: sitofp_2vf64_i32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
+; SSE2-NEXT:    movd %xmm1, %rax
+; SSE2-NEXT:    cltq
+; SSE2-NEXT:    movd %xmm0, %rcx
+; SSE2-NEXT:    movslq %ecx, %rcx
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2sdq %rcx, %xmm0
+; SSE2-NEXT:    xorps %xmm1, %xmm1
+; SSE2-NEXT:    cvtsi2sdq %rax, %xmm1
+; SSE2-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: sitofp_2vf64_i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
+; AVX-NEXT:    vmovq %xmm0, %rax
+; AVX-NEXT:    cltq
+; AVX-NEXT:    vpextrq $1, %xmm0, %rcx
+; AVX-NEXT:    movslq %ecx, %rcx
+; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vcvtsi2sdq %rcx, %xmm0, %xmm0
+; AVX-NEXT:    vcvtsi2sdq %rax, %xmm0, %xmm1
+; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX-NEXT:    retq
+  %shuf = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
+  %cvt = sitofp <2 x i32> %shuf to <2 x double>
+  ret <2 x double> %cvt
+}
+
+define <4 x double> @sitofp_4vf64(<4 x i64> %a) {
+; SSE2-LABEL: sitofp_4vf64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movd %xmm0, %rax
+; SSE2-NEXT:    cvtsi2sdq %rax, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; SSE2-NEXT:    movd %xmm0, %rax
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2sdq %rax, %xmm0
+; SSE2-NEXT:    unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; SSE2-NEXT:    movd %xmm1, %rax
+; SSE2-NEXT:    cvtsi2sdq %rax, %xmm3
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1]
+; SSE2-NEXT:    movd %xmm0, %rax
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2sdq %rax, %xmm0
+; SSE2-NEXT:    unpcklpd {{.*#+}} xmm3 = xmm3[0],xmm0[0]
+; SSE2-NEXT:    movapd %xmm2, %xmm0
+; SSE2-NEXT:    movapd %xmm3, %xmm1
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: sitofp_4vf64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX-NEXT:    vpextrq $1, %xmm1, %rax
+; AVX-NEXT:    vcvtsi2sdq %rax, %xmm0, %xmm2
+; AVX-NEXT:    vmovq %xmm1, %rax
+; AVX-NEXT:    vcvtsi2sdq %rax, %xmm0, %xmm1
+; AVX-NEXT:    vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX-NEXT:    vpextrq $1, %xmm0, %rax
+; AVX-NEXT:    vcvtsi2sdq %rax, %xmm0, %xmm2
+; AVX-NEXT:    vmovq %xmm0, %rax
+; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vcvtsi2sdq %rax, %xmm0, %xmm0
+; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; AVX-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX-NEXT:    retq
+  %cvt = sitofp <4 x i64> %a to <4 x double>
+  ret <4 x double> %cvt
+}
+
+define <4 x double> @sitofp_4vf64_i32(<4 x i32> %a) {
+; SSE2-LABEL: sitofp_4vf64_i32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
+; SSE2-NEXT:    movd %xmm1, %rax
+; SSE2-NEXT:    cltq
+; SSE2-NEXT:    cvtsi2sdq %rax, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; SSE2-NEXT:    movd %xmm1, %rax
+; SSE2-NEXT:    cltq
+; SSE2-NEXT:    xorps %xmm1, %xmm1
+; SSE2-NEXT:    cvtsi2sdq %rax, %xmm1
+; SSE2-NEXT:    unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
+; SSE2-NEXT:    movd %xmm0, %rax
+; SSE2-NEXT:    cltq
+; SSE2-NEXT:    xorps %xmm1, %xmm1
+; SSE2-NEXT:    cvtsi2sdq %rax, %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; SSE2-NEXT:    movd %xmm0, %rax
+; SSE2-NEXT:    cltq
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2sdq %rax, %xmm0
+; SSE2-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE2-NEXT:    movapd %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: sitofp_4vf64_i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vcvtdq2pd %xmm0, %ymm0
+; AVX-NEXT:    retq
+  %cvt = sitofp <4 x i32> %a to <4 x double>
+  ret <4 x double> %cvt
+}
+
+;
+; Unsigned Integer to Double
+;
+
+define <2 x double> @uitofp_2vf64(<2 x i64> %a) {
+; SSE2-LABEL: uitofp_2vf64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT:    movapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
+; SSE2-NEXT:    subpd %xmm3, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
+; SSE2-NEXT:    addpd %xmm4, %xmm0
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; SSE2-NEXT:    subpd %xmm3, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[2,3,0,1]
+; SSE2-NEXT:    addpd %xmm2, %xmm1
+; SSE2-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: uitofp_2vf64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
+; AVX-NEXT:    vpunpckldq {{.*#+}} xmm2 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; AVX-NEXT:    vmovapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
+; AVX-NEXT:    vsubpd %xmm3, %xmm2, %xmm2
+; AVX-NEXT:    vhaddpd %xmm2, %xmm2, %xmm2
+; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; AVX-NEXT:    vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; AVX-NEXT:    vsubpd %xmm3, %xmm0, %xmm0
+; AVX-NEXT:    vhaddpd %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm2[0],xmm0[0]
+; AVX-NEXT:    retq
+  %cvt = uitofp <2 x i64> %a to <2 x double>
+  ret <2 x double> %cvt
+}
+
+define <2 x double> @uitofp_2vf64_i32(<4 x i32> %a) {
+; SSE2-LABEL: uitofp_2vf64_i32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    pxor %xmm1, %xmm1
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT:    movdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT:    movapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
+; SSE2-NEXT:    subpd %xmm3, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
+; SSE2-NEXT:    addpd %xmm4, %xmm0
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; SSE2-NEXT:    subpd %xmm3, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[2,3,0,1]
+; SSE2-NEXT:    addpd %xmm2, %xmm1
+; SSE2-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: uitofp_2vf64_i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
+; AVX-NEXT:    vmovdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
+; AVX-NEXT:    vpunpckldq {{.*#+}} xmm2 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; AVX-NEXT:    vmovapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
+; AVX-NEXT:    vsubpd %xmm3, %xmm2, %xmm2
+; AVX-NEXT:    vhaddpd %xmm2, %xmm2, %xmm2
+; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; AVX-NEXT:    vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; AVX-NEXT:    vsubpd %xmm3, %xmm0, %xmm0
+; AVX-NEXT:    vhaddpd %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm2[0],xmm0[0]
+; AVX-NEXT:    retq
+  %shuf = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
+  %cvt = uitofp <2 x i32> %shuf to <2 x double>
+  ret <2 x double> %cvt
+}
+
+define <4 x double> @uitofp_4vf64(<4 x i64> %a) {
+; SSE2-LABEL: uitofp_4vf64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [1127219200,1160773632,0,0]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-NEXT:    movapd {{.*#+}} xmm4 = [4.503600e+15,1.934281e+25]
+; SSE2-NEXT:    subpd %xmm4, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm0[2,3,0,1]
+; SSE2-NEXT:    addpd %xmm5, %xmm0
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; SSE2-NEXT:    subpd %xmm4, %xmm3
+; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm3[2,3,0,1]
+; SSE2-NEXT:    addpd %xmm3, %xmm5
+; SSE2-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm5[0]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
+; SSE2-NEXT:    subpd %xmm4, %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm1[2,3,0,1]
+; SSE2-NEXT:    addpd %xmm5, %xmm1
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; SSE2-NEXT:    subpd %xmm4, %xmm3
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm3[2,3,0,1]
+; SSE2-NEXT:    addpd %xmm3, %xmm2
+; SSE2-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: uitofp_4vf64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX-NEXT:    vmovdqa {{.*#+}} xmm2 = [1127219200,1160773632,0,0]
+; AVX-NEXT:    vpunpckldq {{.*#+}} xmm3 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
+; AVX-NEXT:    vmovapd {{.*#+}} xmm4 = [4.503600e+15,1.934281e+25]
+; AVX-NEXT:    vsubpd %xmm4, %xmm3, %xmm3
+; AVX-NEXT:    vhaddpd %xmm3, %xmm3, %xmm3
+; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; AVX-NEXT:    vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
+; AVX-NEXT:    vsubpd %xmm4, %xmm1, %xmm1
+; AVX-NEXT:    vhaddpd %xmm1, %xmm1, %xmm1
+; AVX-NEXT:    vunpcklpd {{.*#+}} xmm1 = xmm3[0],xmm1[0]
+; AVX-NEXT:    vpunpckldq {{.*#+}} xmm3 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; AVX-NEXT:    vsubpd %xmm4, %xmm3, %xmm3
+; AVX-NEXT:    vhaddpd %xmm3, %xmm3, %xmm3
+; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; AVX-NEXT:    vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; AVX-NEXT:    vsubpd %xmm4, %xmm0, %xmm0
+; AVX-NEXT:    vhaddpd %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm3[0],xmm0[0]
+; AVX-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX-NEXT:    retq
+  %cvt = uitofp <4 x i64> %a to <4 x double>
+  ret <4 x double> %cvt
+}
+
+define <4 x double> @uitofp_4vf64_i32(<4 x i32> %a) {
+; SSE2-LABEL: uitofp_4vf64_i32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    pxor %xmm1, %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[2,2,3,3]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT:    movdqa {{.*#+}} xmm3 = [1127219200,1160773632,0,0]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
+; SSE2-NEXT:    movapd {{.*#+}} xmm4 = [4.503600e+15,1.934281e+25]
+; SSE2-NEXT:    subpd %xmm4, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm0[2,3,0,1]
+; SSE2-NEXT:    addpd %xmm5, %xmm0
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
+; SSE2-NEXT:    subpd %xmm4, %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm1[2,3,0,1]
+; SSE2-NEXT:    addpd %xmm1, %xmm5
+; SSE2-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm5[0]
+; SSE2-NEXT:    pand .LCPI7_2(%rip), %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm2[2,3,0,1]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
+; SSE2-NEXT:    subpd %xmm4, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[2,3,0,1]
+; SSE2-NEXT:    addpd %xmm2, %xmm1
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[1]
+; SSE2-NEXT:    subpd %xmm4, %xmm5
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm5[2,3,0,1]
+; SSE2-NEXT:    addpd %xmm5, %xmm2
+; SSE2-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: uitofp_4vf64_i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpand .LCPI7_0(%rip), %xmm0, %xmm1
+; AVX-NEXT:    vcvtdq2pd %xmm1, %ymm1
+; AVX-NEXT:    vpsrld $16, %xmm0, %xmm0
+; AVX-NEXT:    vcvtdq2pd %xmm0, %ymm0
+; AVX-NEXT:    vmulpd .LCPI7_1(%rip), %ymm0, %ymm0
+; AVX-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    retq
+  %cvt = uitofp <4 x i32> %a to <4 x double>
+  ret <4 x double> %cvt
+}
+
+;
+; Signed Integer to Float
+;
+
+define <4 x float> @sitofp_4vf32(<4 x i32> %a) {
+; SSE2-LABEL: sitofp_4vf32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: sitofp_4vf32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vcvtdq2ps %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %cvt = sitofp <4 x i32> %a to <4 x float>
+  ret <4 x float> %cvt
+}
+
+define <4 x float> @sitofp_4vf32_i64(<2 x i64> %a) {
+; SSE2-LABEL: sitofp_4vf32_i64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movd %xmm0, %rax
+; SSE2-NEXT:    cvtsi2ssq %rax, %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; SSE2-NEXT:    movd %xmm0, %rax
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2ssq %rax, %xmm0
+; SSE2-NEXT:    unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: sitofp_4vf32_i64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpextrq $1, %xmm0, %rax
+; AVX-NEXT:    vcvtsi2ssq %rax, %xmm0, %xmm1
+; AVX-NEXT:    vmovq %xmm0, %rax
+; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vcvtsi2ssq %rax, %xmm0, %xmm0
+; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+; AVX-NEXT:    vcvtsi2ssq %rax, %xmm0, %xmm1
+; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
+; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
+; AVX-NEXT:    retq
+  %cvt = sitofp <2 x i64> %a to <2 x float>
+  %ext = shufflevector <2 x float> %cvt, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  ret <4 x float> %ext
+}
+
+define <8 x float> @sitofp_8vf32(<8 x i32> %a) {
+; SSE2-LABEL: sitofp_8vf32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE2-NEXT:    cvtdq2ps %xmm1, %xmm1
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: sitofp_8vf32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX-NEXT:    retq
+  %cvt = sitofp <8 x i32> %a to <8 x float>
+  ret <8 x float> %cvt
+}
+
+define <4 x float> @sitofp_4vf32_4i64(<4 x i64> %a) {
+; SSE2-LABEL: sitofp_4vf32_4i64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movd %xmm1, %rax
+; SSE2-NEXT:    cvtsi2ssq %rax, %xmm3
+; SSE2-NEXT:    movd %xmm0, %rax
+; SSE2-NEXT:    cvtsi2ssq %rax, %xmm2
+; SSE2-NEXT:    unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; SSE2-NEXT:    movd %xmm1, %rax
+; SSE2-NEXT:    xorps %xmm1, %xmm1
+; SSE2-NEXT:    cvtsi2ssq %rax, %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; SSE2-NEXT:    movd %xmm0, %rax
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2ssq %rax, %xmm0
+; SSE2-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT:    unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; SSE2-NEXT:    movaps %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: sitofp_4vf32_4i64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpextrq $1, %xmm0, %rax
+; AVX-NEXT:    vcvtsi2ssq %rax, %xmm0, %xmm1
+; AVX-NEXT:    vmovq %xmm0, %rax
+; AVX-NEXT:    vcvtsi2ssq %rax, %xmm0, %xmm2
+; AVX-NEXT:    vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
+; AVX-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX-NEXT:    vmovq %xmm0, %rax
+; AVX-NEXT:    vcvtsi2ssq %rax, %xmm0, %xmm2
+; AVX-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
+; AVX-NEXT:    vpextrq $1, %xmm0, %rax
+; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vcvtsi2ssq %rax, %xmm0, %xmm0
+; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
+; AVX-NEXT:    vzeroupper
+; AVX-NEXT:    retq
+  %cvt = sitofp <4 x i64> %a to <4 x float>
+  ret <4 x float> %cvt
+}
+
+;
+; Unsigned Integer to Float
+;
+
+define <4 x float> @uitofp_4vf32(<4 x i32> %a) {
+; SSE2-LABEL: uitofp_4vf32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
+; SSE2-NEXT:    pand %xmm0, %xmm1
+; SSE2-NEXT:    por .LCPI12_1(%rip), %xmm1
+; SSE2-NEXT:    psrld $16, %xmm0
+; SSE2-NEXT:    por .LCPI12_2(%rip), %xmm0
+; SSE2-NEXT:    addps .LCPI12_3(%rip), %xmm0
+; SSE2-NEXT:    addps %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: uitofp_4vf32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
+; AVX-NEXT:    vpsrld $16, %xmm0, %xmm0
+; AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
+; AVX-NEXT:    vaddps .LCPI12_2(%rip), %xmm0, %xmm0
+; AVX-NEXT:    vaddps %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    retq
+  %cvt = uitofp <4 x i32> %a to <4 x float>
+  ret <4 x float> %cvt
+}
+
+define <4 x float> @uitofp_4vf32_i64(<2 x i64> %a) {
+; SSE2-LABEL: uitofp_4vf32_i64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movdqa %xmm0, %xmm1
+; SSE2-NEXT:    movd %xmm1, %rax
+; SSE2-NEXT:    movl %eax, %ecx
+; SSE2-NEXT:    andl $1, %ecx
+; SSE2-NEXT:    testq %rax, %rax
+; SSE2-NEXT:    js .LBB13_1
+; SSE2-NEXT:  # BB#2:
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2ssq %rax, %xmm0
+; SSE2-NEXT:    jmp .LBB13_3
+; SSE2-NEXT:  .LBB13_1:
+; SSE2-NEXT:    shrq %rax
+; SSE2-NEXT:    orq %rax, %rcx
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2ssq %rcx, %xmm0
+; SSE2-NEXT:    addss %xmm0, %xmm0
+; SSE2-NEXT:  .LBB13_3:
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; SSE2-NEXT:    movd %xmm1, %rax
+; SSE2-NEXT:    movl %eax, %ecx
+; SSE2-NEXT:    andl $1, %ecx
+; SSE2-NEXT:    testq %rax, %rax
+; SSE2-NEXT:    js .LBB13_4
+; SSE2-NEXT:  # BB#5:
+; SSE2-NEXT:    xorps %xmm1, %xmm1
+; SSE2-NEXT:    cvtsi2ssq %rax, %xmm1
+; SSE2-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT:    retq
+; SSE2-NEXT:  .LBB13_4:
+; SSE2-NEXT:    shrq %rax
+; SSE2-NEXT:    orq %rax, %rcx
+; SSE2-NEXT:    xorps %xmm1, %xmm1
+; SSE2-NEXT:    cvtsi2ssq %rcx, %xmm1
+; SSE2-NEXT:    addss %xmm1, %xmm1
+; SSE2-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: uitofp_4vf32_i64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpextrq $1, %xmm0, %rax
+; AVX-NEXT:    movl %eax, %ecx
+; AVX-NEXT:    andl $1, %ecx
+; AVX-NEXT:    testq %rax, %rax
+; AVX-NEXT:    js .LBB13_1
+; AVX-NEXT:  # BB#2:
+; AVX-NEXT:    vcvtsi2ssq %rax, %xmm0, %xmm1
+; AVX-NEXT:    jmp .LBB13_3
+; AVX-NEXT:  .LBB13_1:
+; AVX-NEXT:    shrq %rax
+; AVX-NEXT:    orq %rax, %rcx
+; AVX-NEXT:    vcvtsi2ssq %rcx, %xmm0, %xmm1
+; AVX-NEXT:    vaddss %xmm1, %xmm1, %xmm1
+; AVX-NEXT:  .LBB13_3:
+; AVX-NEXT:    vmovq %xmm0, %rax
+; AVX-NEXT:    movl %eax, %ecx
+; AVX-NEXT:    andl $1, %ecx
+; AVX-NEXT:    testq %rax, %rax
+; AVX-NEXT:    js .LBB13_4
+; AVX-NEXT:  # BB#5:
+; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vcvtsi2ssq %rax, %xmm0, %xmm0
+; AVX-NEXT:    jmp .LBB13_6
+; AVX-NEXT:  .LBB13_4:
+; AVX-NEXT:    shrq %rax
+; AVX-NEXT:    orq %rax, %rcx
+; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vcvtsi2ssq %rcx, %xmm0, %xmm0
+; AVX-NEXT:    vaddss %xmm0, %xmm0, %xmm0
+; AVX-NEXT:  .LBB13_6:
+; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
+; AVX-NEXT:    testq %rax, %rax
+; AVX-NEXT:    js .LBB13_8
+; AVX-NEXT:  # BB#7:
+; AVX-NEXT:    vcvtsi2ssq %rax, %xmm0, %xmm1
+; AVX-NEXT:  .LBB13_8:
+; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
+; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
+; AVX-NEXT:    retq
+  %cvt = uitofp <2 x i64> %a to <2 x float>
+  %ext = shufflevector <2 x float> %cvt, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  ret <4 x float> %ext
+}
+
+define <8 x float> @uitofp_8vf32(<8 x i32> %a) {
+; SSE2-LABEL: uitofp_8vf32:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [65535,65535,65535,65535]
+; SSE2-NEXT:    movdqa %xmm0, %xmm3
+; SSE2-NEXT:    pand %xmm2, %xmm3
+; SSE2-NEXT:    movdqa {{.*#+}} xmm4 = [1258291200,1258291200,1258291200,1258291200]
+; SSE2-NEXT:    por %xmm4, %xmm3
+; SSE2-NEXT:    psrld $16, %xmm0
+; SSE2-NEXT:    movdqa {{.*#+}} xmm5 = [1392508928,1392508928,1392508928,1392508928]
+; SSE2-NEXT:    por %xmm5, %xmm0
+; SSE2-NEXT:    movaps {{.*#+}} xmm6 = [-5.497642e+11,-5.497642e+11,-5.497642e+11,-5.497642e+11]
+; SSE2-NEXT:    addps %xmm6, %xmm0
+; SSE2-NEXT:    addps %xmm3, %xmm0
+; SSE2-NEXT:    pand %xmm1, %xmm2
+; SSE2-NEXT:    por %xmm4, %xmm2
+; SSE2-NEXT:    psrld $16, %xmm1
+; SSE2-NEXT:    por %xmm5, %xmm1
+; SSE2-NEXT:    addps %xmm6, %xmm1
+; SSE2-NEXT:    addps %xmm2, %xmm1
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: uitofp_8vf32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vandps .LCPI14_0(%rip), %ymm0, %ymm1
+; AVX-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX-NEXT:    vpsrld $16, %xmm0, %xmm2
+; AVX-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX-NEXT:    vpsrld $16, %xmm0, %xmm0
+; AVX-NEXT:    vinsertf128 $1, %xmm0, %ymm2, %ymm0
+; AVX-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX-NEXT:    vmulps .LCPI14_1(%rip), %ymm0, %ymm0
+; AVX-NEXT:    vaddps %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    retq
+  %cvt = uitofp <8 x i32> %a to <8 x float>
+  ret <8 x float> %cvt
+}
+
+define <4 x float> @uitofp_4vf32_4i64(<4 x i64> %a) {
+; SSE2-LABEL: uitofp_4vf32_4i64:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movd %xmm1, %rax
+; SSE2-NEXT:    movl %eax, %ecx
+; SSE2-NEXT:    andl $1, %ecx
+; SSE2-NEXT:    testq %rax, %rax
+; SSE2-NEXT:    js .LBB15_1
+; SSE2-NEXT:  # BB#2:
+; SSE2-NEXT:    cvtsi2ssq %rax, %xmm3
+; SSE2-NEXT:    jmp .LBB15_3
+; SSE2-NEXT:  .LBB15_1:
+; SSE2-NEXT:    shrq %rax
+; SSE2-NEXT:    orq %rax, %rcx
+; SSE2-NEXT:    cvtsi2ssq %rcx, %xmm3
+; SSE2-NEXT:    addss %xmm3, %xmm3
+; SSE2-NEXT:  .LBB15_3:
+; SSE2-NEXT:    movd %xmm0, %rax
+; SSE2-NEXT:    movl %eax, %ecx
+; SSE2-NEXT:    andl $1, %ecx
+; SSE2-NEXT:    testq %rax, %rax
+; SSE2-NEXT:    js .LBB15_4
+; SSE2-NEXT:  # BB#5:
+; SSE2-NEXT:    cvtsi2ssq %rax, %xmm2
+; SSE2-NEXT:    jmp .LBB15_6
+; SSE2-NEXT:  .LBB15_4:
+; SSE2-NEXT:    shrq %rax
+; SSE2-NEXT:    orq %rax, %rcx
+; SSE2-NEXT:    cvtsi2ssq %rcx, %xmm2
+; SSE2-NEXT:    addss %xmm2, %xmm2
+; SSE2-NEXT:  .LBB15_6:
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; SSE2-NEXT:    movd %xmm1, %rax
+; SSE2-NEXT:    movl %eax, %ecx
+; SSE2-NEXT:    andl $1, %ecx
+; SSE2-NEXT:    testq %rax, %rax
+; SSE2-NEXT:    js .LBB15_7
+; SSE2-NEXT:  # BB#8:
+; SSE2-NEXT:    xorps %xmm1, %xmm1
+; SSE2-NEXT:    cvtsi2ssq %rax, %xmm1
+; SSE2-NEXT:    jmp .LBB15_9
+; SSE2-NEXT:  .LBB15_7:
+; SSE2-NEXT:    shrq %rax
+; SSE2-NEXT:    orq %rax, %rcx
+; SSE2-NEXT:    xorps %xmm1, %xmm1
+; SSE2-NEXT:    cvtsi2ssq %rcx, %xmm1
+; SSE2-NEXT:    addss %xmm1, %xmm1
+; SSE2-NEXT:  .LBB15_9:
+; SSE2-NEXT:    unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; SSE2-NEXT:    movd %xmm0, %rax
+; SSE2-NEXT:    movl %eax, %ecx
+; SSE2-NEXT:    andl $1, %ecx
+; SSE2-NEXT:    testq %rax, %rax
+; SSE2-NEXT:    js .LBB15_10
+; SSE2-NEXT:  # BB#11:
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2ssq %rax, %xmm0
+; SSE2-NEXT:    jmp .LBB15_12
+; SSE2-NEXT:  .LBB15_10:
+; SSE2-NEXT:    shrq %rax
+; SSE2-NEXT:    orq %rax, %rcx
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2ssq %rcx, %xmm0
+; SSE2-NEXT:    addss %xmm0, %xmm0
+; SSE2-NEXT:  .LBB15_12:
+; SSE2-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT:    unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; SSE2-NEXT:    movaps %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; AVX-LABEL: uitofp_4vf32_4i64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpextrq $1, %xmm0, %rax
+; AVX-NEXT:    movl %eax, %ecx
+; AVX-NEXT:    andl $1, %ecx
+; AVX-NEXT:    testq %rax, %rax
+; AVX-NEXT:    js .LBB15_1
+; AVX-NEXT:  # BB#2:
+; AVX-NEXT:    vcvtsi2ssq %rax, %xmm0, %xmm1
+; AVX-NEXT:    jmp .LBB15_3
+; AVX-NEXT:  .LBB15_1:
+; AVX-NEXT:    shrq %rax
+; AVX-NEXT:    orq %rax, %rcx
+; AVX-NEXT:    vcvtsi2ssq %rcx, %xmm0, %xmm1
+; AVX-NEXT:    vaddss %xmm1, %xmm1, %xmm1
+; AVX-NEXT:  .LBB15_3:
+; AVX-NEXT:    vmovq %xmm0, %rax
+; AVX-NEXT:    movl %eax, %ecx
+; AVX-NEXT:    andl $1, %ecx
+; AVX-NEXT:    testq %rax, %rax
+; AVX-NEXT:    js .LBB15_4
+; AVX-NEXT:  # BB#5:
+; AVX-NEXT:    vcvtsi2ssq %rax, %xmm0, %xmm2
+; AVX-NEXT:    jmp .LBB15_6
+; AVX-NEXT:  .LBB15_4:
+; AVX-NEXT:    shrq %rax
+; AVX-NEXT:    orq %rax, %rcx
+; AVX-NEXT:    vcvtsi2ssq %rcx, %xmm0, %xmm2
+; AVX-NEXT:    vaddss %xmm2, %xmm2, %xmm2
+; AVX-NEXT:  .LBB15_6:
+; AVX-NEXT:    vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
+; AVX-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX-NEXT:    vmovq %xmm0, %rax
+; AVX-NEXT:    movl %eax, %ecx
+; AVX-NEXT:    andl $1, %ecx
+; AVX-NEXT:    testq %rax, %rax
+; AVX-NEXT:    js .LBB15_7
+; AVX-NEXT:  # BB#8:
+; AVX-NEXT:    vcvtsi2ssq %rax, %xmm0, %xmm2
+; AVX-NEXT:    jmp .LBB15_9
+; AVX-NEXT:  .LBB15_7:
+; AVX-NEXT:    shrq %rax
+; AVX-NEXT:    orq %rax, %rcx
+; AVX-NEXT:    vcvtsi2ssq %rcx, %xmm0, %xmm2
+; AVX-NEXT:    vaddss %xmm2, %xmm2, %xmm2
+; AVX-NEXT:  .LBB15_9:
+; AVX-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
+; AVX-NEXT:    vpextrq $1, %xmm0, %rax
+; AVX-NEXT:    movl %eax, %ecx
+; AVX-NEXT:    andl $1, %ecx
+; AVX-NEXT:    testq %rax, %rax
+; AVX-NEXT:    js .LBB15_10
+; AVX-NEXT:  # BB#11:
+; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vcvtsi2ssq %rax, %xmm0, %xmm0
+; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
+; AVX-NEXT:    vzeroupper
+; AVX-NEXT:    retq
+; AVX-NEXT:  .LBB15_10:
+; AVX-NEXT:    shrq %rax
+; AVX-NEXT:    orq %rax, %rcx
+; AVX-NEXT:    vcvtsi2ssq %rcx, %xmm0, %xmm0
+; AVX-NEXT:    vaddss %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
+; AVX-NEXT:    vzeroupper
+; AVX-NEXT:    retq
+  %cvt = uitofp <4 x i64> %a to <4 x float>
+  ret <4 x float> %cvt
+}
diff --git a/test/CodeGen/X86/vec_loadsingles.ll b/test/CodeGen/X86/vec_loadsingles.ll
index fd132a52b8f1..ecae5d962826 100644
--- a/test/CodeGen/X86/vec_loadsingles.ll
+++ b/test/CodeGen/X86/vec_loadsingles.ll
@@ -2,10 +2,10 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+slow-unaligned-mem-32 | FileCheck %s --check-prefix=ALL --check-prefix=SLOW32
 
 define <4 x float> @merge_2_floats(float* nocapture %p) nounwind readonly {
-  %tmp1 = load float* %p
+  %tmp1 = load float, float* %p
   %vecins = insertelement <4 x float> undef, float %tmp1, i32 0
-  %add.ptr = getelementptr float* %p, i32 1
-  %tmp5 = load float* %add.ptr
+  %add.ptr = getelementptr float, float* %p, i32 1
+  %tmp5 = load float, float* %add.ptr
   %vecins7 = insertelement <4 x float> %vecins, float %tmp5, i32 1
   ret <4 x float> %vecins7
 
@@ -17,13 +17,13 @@ define <4 x float> @merge_2_floats(float* nocapture %p) nounwind readonly {
 ; Test-case generated due to a crash when trying to treat loading the first
 ; two i64s of a <4 x i64> as a load of two i32s.
 define <4 x i64> @merge_2_floats_into_4() {
-  %1 = load i64** undef, align 8
-  %2 = getelementptr inbounds i64* %1, i64 0
-  %3 = load i64* %2
+  %1 = load i64*, i64** undef, align 8
+  %2 = getelementptr inbounds i64, i64* %1, i64 0
+  %3 = load i64, i64* %2
   %4 = insertelement <4 x i64> undef, i64 %3, i32 0
-  %5 = load i64** undef, align 8
-  %6 = getelementptr inbounds i64* %5, i64 1
-  %7 = load i64* %6
+  %5 = load i64*, i64** undef, align 8
+  %6 = getelementptr inbounds i64, i64* %5, i64 1
+  %7 = load i64, i64* %6
   %8 = insertelement <4 x i64> %4, i64 %7, i32 1
   %9 = shufflevector <4 x i64> %8, <4 x i64> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
   ret <4 x i64> %9
@@ -34,16 +34,16 @@ define <4 x i64> @merge_2_floats_into_4() {
 }
 
 define <4 x float> @merge_4_floats(float* %ptr) {
-  %a = load float* %ptr, align 8
+  %a = load float, float* %ptr, align 8
   %vec = insertelement <4 x float> undef, float %a, i32 0
-  %idx1 = getelementptr inbounds float* %ptr, i64 1
-  %b = load float* %idx1, align 8
+  %idx1 = getelementptr inbounds float, float* %ptr, i64 1
+  %b = load float, float* %idx1, align 8
   %vec2 = insertelement <4 x float> %vec, float %b, i32 1
-  %idx3 = getelementptr inbounds float* %ptr, i64 2
-  %c = load float* %idx3, align 8
+  %idx3 = getelementptr inbounds float, float* %ptr, i64 2
+  %c = load float, float* %idx3, align 8
   %vec4 = insertelement <4 x float> %vec2, float %c, i32 2
-  %idx5 = getelementptr inbounds float* %ptr, i64 3
-  %d = load float* %idx5, align 8
+  %idx5 = getelementptr inbounds float, float* %ptr, i64 3
+  %d = load float, float* %idx5, align 8
   %vec6 = insertelement <4 x float> %vec4, float %d, i32 3
   ret <4 x float> %vec6
 
@@ -58,28 +58,28 @@ define <4 x float> @merge_4_floats(float* %ptr) {
 ; 16-byte loads.
 
 define <8 x float> @merge_8_floats(float* %ptr) {
-  %a = load float* %ptr, align 4
+  %a = load float, float* %ptr, align 4
   %vec = insertelement <8 x float> undef, float %a, i32 0
-  %idx1 = getelementptr inbounds float* %ptr, i64 1
-  %b = load float* %idx1, align 4
+  %idx1 = getelementptr inbounds float, float* %ptr, i64 1
+  %b = load float, float* %idx1, align 4
   %vec2 = insertelement <8 x float> %vec, float %b, i32 1
-  %idx3 = getelementptr inbounds float* %ptr, i64 2
-  %c = load float* %idx3, align 4
+  %idx3 = getelementptr inbounds float, float* %ptr, i64 2
+  %c = load float, float* %idx3, align 4
   %vec4 = insertelement <8 x float> %vec2, float %c, i32 2
-  %idx5 = getelementptr inbounds float* %ptr, i64 3
-  %d = load float* %idx5, align 4
+  %idx5 = getelementptr inbounds float, float* %ptr, i64 3
+  %d = load float, float* %idx5, align 4
   %vec6 = insertelement <8 x float> %vec4, float %d, i32 3
-  %idx7 = getelementptr inbounds float* %ptr, i64 4
-  %e = load float* %idx7, align 4
+  %idx7 = getelementptr inbounds float, float* %ptr, i64 4
+  %e = load float, float* %idx7, align 4
   %vec8 = insertelement <8 x float> %vec6, float %e, i32 4
-  %idx9 = getelementptr inbounds float* %ptr, i64 5
-  %f = load float* %idx9, align 4
+  %idx9 = getelementptr inbounds float, float* %ptr, i64 5
+  %f = load float, float* %idx9, align 4
   %vec10 = insertelement <8 x float> %vec8, float %f, i32 5
-  %idx11 = getelementptr inbounds float* %ptr, i64 6
-  %g = load float* %idx11, align 4
+  %idx11 = getelementptr inbounds float, float* %ptr, i64 6
+  %g = load float, float* %idx11, align 4
   %vec12 = insertelement <8 x float> %vec10, float %g, i32 6
-  %idx13 = getelementptr inbounds float* %ptr, i64 7
-  %h = load float* %idx13, align 4
+  %idx13 = getelementptr inbounds float, float* %ptr, i64 7
+  %h = load float, float* %idx13, align 4
   %vec14 = insertelement <8 x float> %vec12, float %h, i32 7
   ret <8 x float> %vec14
 
@@ -94,16 +94,16 @@ define <8 x float> @merge_8_floats(float* %ptr) {
 }
 
 define <4 x double> @merge_4_doubles(double* %ptr) {
-  %a = load double* %ptr, align 8
+  %a = load double, double* %ptr, align 8
   %vec = insertelement <4 x double> undef, double %a, i32 0
-  %idx1 = getelementptr inbounds double* %ptr, i64 1
-  %b = load double* %idx1, align 8
+  %idx1 = getelementptr inbounds double, double* %ptr, i64 1
+  %b = load double, double* %idx1, align 8
   %vec2 = insertelement <4 x double> %vec, double %b, i32 1
-  %idx3 = getelementptr inbounds double* %ptr, i64 2
-  %c = load double* %idx3, align 8
+  %idx3 = getelementptr inbounds double, double* %ptr, i64 2
+  %c = load double, double* %idx3, align 8
   %vec4 = insertelement <4 x double> %vec2, double %c, i32 2
-  %idx5 = getelementptr inbounds double* %ptr, i64 3
-  %d = load double* %idx5, align 8
+  %idx5 = getelementptr inbounds double, double* %ptr, i64 3
+  %d = load double, double* %idx5, align 8
   %vec6 = insertelement <4 x double> %vec4, double %d, i32 3
   ret <4 x double> %vec6
 
@@ -120,14 +120,14 @@ define <4 x double> @merge_4_doubles(double* %ptr) {
 ; Recognize and combine consecutive loads even when the
 ; first of the combined loads is offset from the base address.
 define <4 x double> @merge_4_doubles_offset(double* %ptr) {
-  %arrayidx4 = getelementptr inbounds double* %ptr, i64 4
-  %arrayidx5 = getelementptr inbounds double* %ptr, i64 5
-  %arrayidx6 = getelementptr inbounds double* %ptr, i64 6
-  %arrayidx7 = getelementptr inbounds double* %ptr, i64 7
-  %e = load double* %arrayidx4, align 8
-  %f = load double* %arrayidx5, align 8
-  %g = load double* %arrayidx6, align 8
-  %h = load double* %arrayidx7, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 4
+  %arrayidx5 = getelementptr inbounds double, double* %ptr, i64 5
+  %arrayidx6 = getelementptr inbounds double, double* %ptr, i64 6
+  %arrayidx7 = getelementptr inbounds double, double* %ptr, i64 7
+  %e = load double, double* %arrayidx4, align 8
+  %f = load double, double* %arrayidx5, align 8
+  %g = load double, double* %arrayidx6, align 8
+  %h = load double, double* %arrayidx7, align 8
   %vecinit4 = insertelement <4 x double> undef, double %e, i32 0
   %vecinit5 = insertelement <4 x double> %vecinit4, double %f, i32 1
   %vecinit6 = insertelement <4 x double> %vecinit5, double %g, i32 2
diff --git a/test/CodeGen/X86/vec_logical.ll b/test/CodeGen/X86/vec_logical.ll
index 1dc0b163aeb3..6ab2d8963abd 100644
--- a/test/CodeGen/X86/vec_logical.ll
+++ b/test/CodeGen/X86/vec_logical.ll
@@ -29,7 +29,7 @@ entry:
 
 define void @t3(<4 x float> %a, <4 x float> %b, <4 x float>* %c, <4 x float>* %d) {
 entry:
-	%tmp3 = load <4 x float>* %c		; <<4 x float>> [#uses=1]
+	%tmp3 = load <4 x float>, <4 x float>* %c		; <<4 x float>> [#uses=1]
 	%tmp11 = bitcast <4 x float> %a to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp12 = bitcast <4 x float> %b to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp13 = xor <4 x i32> %tmp11, < i32 -1, i32 -1, i32 -1, i32 -1 >		; <<4 x i32>> [#uses=1]
diff --git a/test/CodeGen/X86/vec_partial.ll b/test/CodeGen/X86/vec_partial.ll
new file mode 100644
index 000000000000..709f326e5027
--- /dev/null
+++ b/test/CodeGen/X86/vec_partial.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s

+

+; PR11580

+define <3 x float> @addf3(<3 x float> %x) {

+; CHECK-LABEL: addf3

+; CHECK:       # BB#0:

+; CHECK-NEXT:  addps .LCPI0_0(%rip), %xmm0

+; CHECK-NEXT:  retq

+entry:

+  %add = fadd <3 x float> %x, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>

+  ret <3 x float> %add

+}

+

+; PR11580

+define <4 x float> @cvtf3_f4(<3 x float> %x) {

+; CHECK-LABEL: cvtf3_f4

+; CHECK:       # BB#0:

+; CHECK-NEXT:  retq

+entry:

+  %extractVec = shufflevector <3 x float> %x, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>

+  ret <4 x float> %extractVec

+}

+

+; PR11580

+define <3 x float> @cvtf4_f3(<4 x float> %x) {

+; CHECK-LABEL: cvtf4_f3

+; CHECK:       # BB#0:

+; CHECK-NEXT:  retq

+entry:

+  %extractVec = shufflevector <4 x float> %x, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>

+  ret <3 x float> %extractVec

+}

diff --git a/test/CodeGen/X86/vec_reassociate.ll b/test/CodeGen/X86/vec_reassociate.ll
new file mode 100644
index 000000000000..bf2053f78424
--- /dev/null
+++ b/test/CodeGen/X86/vec_reassociate.ll
@@ -0,0 +1,119 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s

+

+define <4 x i32> @add_4i32(<4 x i32> %a0, <4 x i32> %a1) {

+  ;CHECK-LABEL:  @add_4i32

+  ;CHECK:        # BB#0:

+  ;CHECK-NEXT:   paddd %xmm1, %xmm0

+  ;CHECK-NEXT:   retq

+  %1 = add <4 x i32> %a0, <i32  1, i32 -2, i32  3, i32 -4>

+  %2 = add <4 x i32> %a1, <i32 -1, i32  2, i32 -3, i32  4>

+  %3 = add <4 x i32> %1, %2

+  ret <4 x i32> %3

+}

+

+define <4 x i32> @add_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {

+  ;CHECK-LABEL:  @add_4i32_commute

+  ;CHECK:        # BB#0:

+  ;CHECK-NEXT:   paddd %xmm1, %xmm0

+  ;CHECK-NEXT:   retq

+  %1 = add <4 x i32> <i32  1, i32 -2, i32  3, i32 -4>, %a0

+  %2 = add <4 x i32> <i32 -1, i32  2, i32 -3, i32  4>, %a1

+  %3 = add <4 x i32> %1, %2

+  ret <4 x i32> %3

+}

+

+define <4 x i32> @mul_4i32(<4 x i32> %a0, <4 x i32> %a1) {

+  ;CHECK-LABEL:  @mul_4i32

+  ;CHECK:        # BB#0:

+  ;CHECK-NEXT:   pmulld %xmm1, %xmm0

+  ;CHECK-NEXT:   pmulld .LCPI2_0(%rip), %xmm0

+  ;CHECK-NEXT:   retq

+  %1 = mul <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 4>

+  %2 = mul <4 x i32> %a1, <i32 4, i32 3, i32 2, i32 1>

+  %3 = mul <4 x i32> %1, %2

+  ret <4 x i32> %3

+}

+

+define <4 x i32> @mul_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {

+  ;CHECK-LABEL:  @mul_4i32_commute

+  ;CHECK:        # BB#0:

+  ;CHECK-NEXT:   pmulld %xmm1, %xmm0

+  ;CHECK-NEXT:   pmulld .LCPI3_0(%rip), %xmm0

+  ;CHECK-NEXT:   retq

+  %1 = mul <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %a0

+  %2 = mul <4 x i32> <i32 4, i32 3, i32 2, i32 1>, %a1

+  %3 = mul <4 x i32> %1, %2

+  ret <4 x i32> %3

+}

+

+define <4 x i32> @and_4i32(<4 x i32> %a0, <4 x i32> %a1) {

+  ;CHECK-LABEL:  @and_4i32

+  ;CHECK:        # BB#0:

+  ;CHECK-NEXT:   andps %xmm1, %xmm0

+  ;CHECK-NEXT:   andps .LCPI4_0(%rip), %xmm0

+  ;CHECK-NEXT:   retq

+  %1 = and <4 x i32> %a0, <i32 -2, i32 -2, i32  3, i32  3>

+  %2 = and <4 x i32> %a1, <i32 -1, i32 -1, i32  1, i32  1>

+  %3 = and <4 x i32> %1, %2

+  ret <4 x i32> %3

+}

+

+define <4 x i32> @and_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {

+  ;CHECK-LABEL:  @and_4i32_commute

+  ;CHECK:        # BB#0:

+  ;CHECK-NEXT:   andps %xmm1, %xmm0

+  ;CHECK-NEXT:   andps .LCPI5_0(%rip), %xmm0

+  ;CHECK-NEXT:   retq

+  %1 = and <4 x i32> <i32 -2, i32 -2, i32  3, i32  3>, %a0

+  %2 = and <4 x i32> <i32 -1, i32 -1, i32  1, i32  1>, %a1

+  %3 = and <4 x i32> %1, %2

+  ret <4 x i32> %3

+}

+

+define <4 x i32> @or_4i32(<4 x i32> %a0, <4 x i32> %a1) {

+  ;CHECK-LABEL:  @or_4i32

+  ;CHECK:        # BB#0:

+  ;CHECK-NEXT:   orps %xmm1, %xmm0

+  ;CHECK-NEXT:   orps .LCPI6_0(%rip), %xmm0

+  ;CHECK-NEXT:   retq

+  %1 = or <4 x i32> %a0, <i32 -2, i32 -2, i32  3, i32  3>

+  %2 = or <4 x i32> %a1, <i32 -1, i32 -1, i32  1, i32  1>

+  %3 = or <4 x i32> %1, %2

+  ret <4 x i32> %3

+}

+

+define <4 x i32> @or_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {

+  ;CHECK-LABEL:  @or_4i32_commute

+  ;CHECK:        # BB#0:

+  ;CHECK-NEXT:   orps %xmm1, %xmm0

+  ;CHECK-NEXT:   orps .LCPI7_0(%rip), %xmm0

+  ;CHECK-NEXT:   retq

+  %1 = or <4 x i32> <i32 -2, i32 -2, i32  3, i32  3>, %a0 

+  %2 = or <4 x i32> <i32 -1, i32 -1, i32  1, i32  1>, %a1

+  %3 = or <4 x i32> %1, %2

+  ret <4 x i32> %3

+}

+

+define <4 x i32> @xor_4i32(<4 x i32> %a0, <4 x i32> %a1) {

+  ;CHECK-LABEL:  @xor_4i32

+  ;CHECK:        # BB#0:

+  ;CHECK-NEXT:   xorps %xmm1, %xmm0

+  ;CHECK-NEXT:   xorps .LCPI8_0(%rip), %xmm0

+  ;CHECK-NEXT:   retq

+  %1 = xor <4 x i32> %a0, <i32 -2, i32 -2, i32  3, i32  3>

+  %2 = xor <4 x i32> %a1, <i32 -1, i32 -1, i32  1, i32  1>

+  %3 = xor <4 x i32> %1, %2

+  ret <4 x i32> %3

+}

+

+define <4 x i32> @xor_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {

+  ;CHECK-LABEL:  @xor_4i32_commute

+  ;CHECK:        # BB#0:

+  ;CHECK-NEXT:   xorps %xmm1, %xmm0

+  ;CHECK-NEXT:   xorps .LCPI9_0(%rip), %xmm0

+  ;CHECK-NEXT:   retq

+  %1 = xor <4 x i32> <i32 -2, i32 -2, i32  3, i32  3>, %a0

+  %2 = xor <4 x i32> <i32 -1, i32 -1, i32  1, i32  1>, %a1

+  %3 = xor <4 x i32> %1, %2

+  ret <4 x i32> %3

+}

diff --git a/test/CodeGen/X86/vec_set-7.ll b/test/CodeGen/X86/vec_set-7.ll
index d993178a9892..1701e491da66 100644
--- a/test/CodeGen/X86/vec_set-7.ll
+++ b/test/CodeGen/X86/vec_set-7.ll
@@ -2,7 +2,7 @@
 
 define <2 x i64> @test(<2 x i64>* %p) nounwind {
 	%tmp = bitcast <2 x i64>* %p to double*		
-	%tmp.upgrd.1 = load double* %tmp	
+	%tmp.upgrd.1 = load double, double* %tmp	
 	%tmp.upgrd.2 = insertelement <2 x double> undef, double %tmp.upgrd.1, i32 0
 	%tmp5 = insertelement <2 x double> %tmp.upgrd.2, double 0.0, i32 1
 	%tmp.upgrd.3 = bitcast <2 x double> %tmp5 to <2 x i64>
diff --git a/test/CodeGen/X86/vec_set-F.ll b/test/CodeGen/X86/vec_set-F.ll
index 6dd3cb0abeb9..aa17f9bfbf5c 100644
--- a/test/CodeGen/X86/vec_set-F.ll
+++ b/test/CodeGen/X86/vec_set-F.ll
@@ -4,7 +4,7 @@
 
 define <2 x i64> @t1(<2 x i64>* %ptr) nounwind  {
 	%tmp45 = bitcast <2 x i64>* %ptr to <2 x i32>*
-	%tmp615 = load <2 x i32>* %tmp45
+	%tmp615 = load <2 x i32>, <2 x i32>* %tmp45
 	%tmp7 = bitcast <2 x i32> %tmp615 to i64
 	%tmp8 = insertelement <2 x i64> zeroinitializer, i64 %tmp7, i32 0
 	ret <2 x i64> %tmp8
diff --git a/test/CodeGen/X86/vec_setcc-2.ll b/test/CodeGen/X86/vec_setcc-2.ll
index ef916dcd709e..e150882642a1 100644
--- a/test/CodeGen/X86/vec_setcc-2.ll
+++ b/test/CodeGen/X86/vec_setcc-2.ll
@@ -25,13 +25,13 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx1 = getelementptr inbounds <2 x i64>* %in, i64 %indvars.iv
-  %arrayidx1.val = load <2 x i64>* %arrayidx1, align 16
+  %arrayidx1 = getelementptr inbounds <2 x i64>, <2 x i64>* %in, i64 %indvars.iv
+  %arrayidx1.val = load <2 x i64>, <2 x i64>* %arrayidx1, align 16
   %0 = bitcast <2 x i64> %arrayidx1.val to <8 x i16>
   %cmp.i.i = icmp ult <8 x i16> %0, <i16 26, i16 26, i16 26, i16 26, i16 26, i16 26, i16 26, i16 26>
   %sext.i.i = sext <8 x i1> %cmp.i.i to <8 x i16>
   %1 = bitcast <8 x i16> %sext.i.i to <2 x i64>
-  %arrayidx5 = getelementptr inbounds <2 x i64>* %out, i64 %indvars.iv
+  %arrayidx5 = getelementptr inbounds <2 x i64>, <2 x i64>* %out, i64 %indvars.iv
   store <2 x i64> %1, <2 x i64>* %arrayidx5, align 16
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -54,13 +54,13 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx1 = getelementptr inbounds <2 x i64>* %in, i64 %indvars.iv
-  %arrayidx1.val = load <2 x i64>* %arrayidx1, align 16
+  %arrayidx1 = getelementptr inbounds <2 x i64>, <2 x i64>* %in, i64 %indvars.iv
+  %arrayidx1.val = load <2 x i64>, <2 x i64>* %arrayidx1, align 16
   %0 = bitcast <2 x i64> %arrayidx1.val to <8 x i16>
   %cmp.i.i = icmp ult <8 x i16> %0, <i16 0, i16 26, i16 26, i16 26, i16 26, i16 26, i16 26, i16 26>
   %sext.i.i = sext <8 x i1> %cmp.i.i to <8 x i16>
   %1 = bitcast <8 x i16> %sext.i.i to <2 x i64>
-  %arrayidx5 = getelementptr inbounds <2 x i64>* %out, i64 %indvars.iv
+  %arrayidx5 = getelementptr inbounds <2 x i64>, <2 x i64>* %out, i64 %indvars.iv
   store <2 x i64> %1, <2 x i64>* %arrayidx5, align 16
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/CodeGen/X86/vec_shift5.ll b/test/CodeGen/X86/vec_shift5.ll
index 2e98003ae1cd..499aa22de52d 100644
--- a/test/CodeGen/X86/vec_shift5.ll
+++ b/test/CodeGen/X86/vec_shift5.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=x86-64 -mcpu=corei7 -mattr=-sse4.1 < %s | FileCheck %s
+; RUN: llc -march=x86-64 -mattr=+sse2 < %s | FileCheck %s
 
 ; Verify that we correctly fold target specific packed vector shifts by
 ; immediate count into a simple build_vector when the elements of the vector
diff --git a/test/CodeGen/X86/vec_shift6.ll b/test/CodeGen/X86/vec_shift6.ll
index df2d9cb04687..b71f9893a9db 100644
--- a/test/CodeGen/X86/vec_shift6.ll
+++ b/test/CodeGen/X86/vec_shift6.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s -check-prefix=CHECK -check-prefix=SSE
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core-avx2 | FileCheck %s -check-prefix=CHECK -check-prefix=AVX2 -check-prefix=AVX2ONLY
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=knl | FileCheck %s -check-prefix=CHECK -check-prefix=AVX2 -check-prefix=AVX512
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=sse4.1 | FileCheck %s -check-prefix=CHECK -check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx2 | FileCheck %s -check-prefix=CHECK -check-prefix=AVX2 -check-prefix=AVX2ONLY
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx512f | FileCheck %s -check-prefix=CHECK -check-prefix=AVX2 -check-prefix=AVX512
 
 
 ; Verify that we don't scalarize a packed vector shift left of 16-bit
diff --git a/test/CodeGen/X86/vec_shift7.ll b/test/CodeGen/X86/vec_shift7.ll
new file mode 100644
index 000000000000..cdf828976be4
--- /dev/null
+++ b/test/CodeGen/X86/vec_shift7.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
+
+
+; Verify that we don't fail when shift by zero is encountered.
+
+define i64 @test1(<2 x i64> %a) {
+entry:
+ %c = shl <2 x i64> %a, <i64 0, i64 2>
+ %d = extractelement <2 x i64> %c, i32 0
+ ret i64 %d
+}
+; CHECK-LABEL: test1
diff --git a/test/CodeGen/X86/vec_split.ll b/test/CodeGen/X86/vec_split.ll
index bc2c6633f20d..1df4cf2b2325 100644
--- a/test/CodeGen/X86/vec_split.ll
+++ b/test/CodeGen/X86/vec_split.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=x86-64 -mcpu=corei7 < %s | FileCheck %s -check-prefix=SSE4
-; RUN: llc -march=x86-64 -mcpu=corei7-avx < %s | FileCheck %s -check-prefix=AVX1
-; RUN: llc -march=x86-64 -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX2
+; RUN: llc -march=x86-64 -mattr=sse4.1 < %s | FileCheck %s -check-prefix=SSE4
+; RUN: llc -march=x86-64 -mattr=avx < %s | FileCheck %s -check-prefix=AVX1
+; RUN: llc -march=x86-64 -mattr=avx2 < %s | FileCheck %s -check-prefix=AVX2
 
 define <16 x i16> @split16(<16 x i16> %a, <16 x i16> %b, <16 x i8> %__mask) {
 ; SSE4-LABEL: split16:
diff --git a/test/CodeGen/X86/vec_ss_load_fold.ll b/test/CodeGen/X86/vec_ss_load_fold.ll
index 80f12a2dec2c..ab5031e267dc 100644
--- a/test/CodeGen/X86/vec_ss_load_fold.ll
+++ b/test/CodeGen/X86/vec_ss_load_fold.ll
@@ -51,7 +51,7 @@ declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32)
 declare <4 x float> @f()
 
 define <4 x float> @test3(<4 x float> %A, float *%b, i32 %C) nounwind {
-  %a = load float *%b
+  %a = load float , float *%b
   %B = insertelement <4 x float> undef, float %a, i32 0
   %X = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %A, <4 x float> %B, i32 4)
   ret <4 x float> %X
@@ -60,7 +60,7 @@ define <4 x float> @test3(<4 x float> %A, float *%b, i32 %C) nounwind {
 }
 
 define <4 x float> @test4(<4 x float> %A, float *%b, i32 %C) nounwind {
-  %a = load float *%b
+  %a = load float , float *%b
   %B = insertelement <4 x float> undef, float %a, i32 0
   %q = call <4 x float> @f()
   %X = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %q, <4 x float> %B, i32 4)
diff --git a/test/CodeGen/X86/vec_trunc_sext.ll b/test/CodeGen/X86/vec_trunc_sext.ll
index 3c446bba4ea8..dcfe423eb748 100644
--- a/test/CodeGen/X86/vec_trunc_sext.ll
+++ b/test/CodeGen/X86/vec_trunc_sext.ll
@@ -9,7 +9,7 @@
 ; but that is beyond our current codegen capabilities.
 
 define <4 x i32> @trunc_sext(<4 x i16>* %in) {
-  %load = load <4 x i16>* %in
+  %load = load <4 x i16>, <4 x i16>* %in
   %trunc = trunc <4 x i16> %load to <4 x i8>
   %sext = sext <4 x i8> %trunc to <4 x i32>
   ret <4 x i32> %sext
diff --git a/test/CodeGen/X86/vec_zero.ll b/test/CodeGen/X86/vec_zero.ll
index c3ea0ad2023f..1d900a0919f2 100644
--- a/test/CodeGen/X86/vec_zero.ll
+++ b/test/CodeGen/X86/vec_zero.ll
@@ -3,7 +3,7 @@
 ; CHECK: foo
 ; CHECK: xorps
 define void @foo(<4 x float>* %P) {
-        %T = load <4 x float>* %P               ; <<4 x float>> [#uses=1]
+        %T = load <4 x float>, <4 x float>* %P               ; <<4 x float>> [#uses=1]
         %S = fadd <4 x float> zeroinitializer, %T                ; <<4 x float>> [#uses=1]
         store <4 x float> %S, <4 x float>* %P
         ret void
@@ -12,7 +12,7 @@ define void @foo(<4 x float>* %P) {
 ; CHECK: bar
 ; CHECK: pxor
 define void @bar(<4 x i32>* %P) {
-        %T = load <4 x i32>* %P         ; <<4 x i32>> [#uses=1]
+        %T = load <4 x i32>, <4 x i32>* %P         ; <<4 x i32>> [#uses=1]
         %S = sub <4 x i32> zeroinitializer, %T          ; <<4 x i32>> [#uses=1]
         store <4 x i32> %S, <4 x i32>* %P
         ret void
diff --git a/test/CodeGen/X86/vec_zero_cse.ll b/test/CodeGen/X86/vec_zero_cse.ll
index bda3feff2b00..8ed8083a284f 100644
--- a/test/CodeGen/X86/vec_zero_cse.ll
+++ b/test/CodeGen/X86/vec_zero_cse.ll
@@ -1,38 +1,39 @@
-; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | FileCheck %s
-; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | FileCheck -check-prefix CHECK2 %s
+; RUN: llc < %s -relocation-model=static -mtriple=i686-unknown -mattr=+mmx,+sse3 | FileCheck %s
 ; 64-bit stores here do not use MMX.
 
-; CHECK: xorps
-; CHECK-NOT: xorps
-
-; CHECK2: pcmpeqd
-; CHECK2-NOT: pcmpeqd
-
 @M1 = external global <1 x i64>
 @M2 = external global <2 x i32>
 
 @S1 = external global <2 x i64>
 @S2 = external global <4 x i32>
 
-define void @test() {
+define void @test1() {
+;CHECK-LABEL: @test1
+;CHECK: xorps
   store <1 x i64> zeroinitializer, <1 x i64>* @M1
   store <2 x i32> zeroinitializer, <2 x i32>* @M2
   ret void
 }
 
 define void @test2() {
+;CHECK-LABEL: @test2
+;CHECK: pcmpeqd
   store <1 x i64> < i64 -1 >, <1 x i64>* @M1
   store <2 x i32> < i32 -1, i32 -1 >, <2 x i32>* @M2
   ret void
 }
 
 define void @test3() {
+;CHECK-LABEL: @test3
+;CHECK: xorps
   store <2 x i64> zeroinitializer, <2 x i64>* @S1
   store <4 x i32> zeroinitializer, <4 x i32>* @S2
   ret void
 }
 
 define void @test4() {
+;CHECK-LABEL: @test4
+;CHECK: pcmpeqd
   store <2 x i64> < i64 -1, i64 -1>, <2 x i64>* @S1
   store <4 x i32> < i32 -1, i32 -1, i32 -1, i32 -1 >, <4 x i32>* @S2
   ret void
diff --git a/test/CodeGen/X86/vector-blend.ll b/test/CodeGen/X86/vector-blend.ll
index f23b82883858..e15daaa54a33 100644
--- a/test/CodeGen/X86/vector-blend.ll
+++ b/test/CodeGen/X86/vector-blend.ll
@@ -9,16 +9,14 @@
 define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
 ; SSE2-LABEL: vsel_float:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    andps {{.*}}(%rip), %xmm1
-; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
-; SSE2-NEXT:    orps %xmm1, %xmm0
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: vsel_float:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm1
-; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
-; SSSE3-NEXT:    orps %xmm1, %xmm0
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: vsel_float:
@@ -38,13 +36,13 @@ entry:
 define <4 x float> @vsel_float2(<4 x float> %v1, <4 x float> %v2) {
 ; SSE2-LABEL: vsel_float2:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movss %xmm0, %xmm1
+; SSE2-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE2-NEXT:    movaps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: vsel_float2:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movss %xmm0, %xmm1
+; SSSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
@@ -55,7 +53,7 @@ define <4 x float> @vsel_float2(<4 x float> %v1, <4 x float> %v2) {
 ;
 ; AVX-LABEL: vsel_float2:
 ; AVX:       # BB#0: # %entry
-; AVX-NEXT:    blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
+; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
 ; AVX-NEXT:    retq
 entry:
   %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
@@ -65,16 +63,14 @@ entry:
 define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
 ; SSE2-LABEL: vsel_4xi8:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    andps {{.*}}(%rip), %xmm1
-; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
-; SSE2-NEXT:    orps %xmm1, %xmm0
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: vsel_4xi8:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm1
-; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
-; SSSE3-NEXT:    orps %xmm1, %xmm0
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: vsel_4xi8:
@@ -99,16 +95,16 @@ entry:
 define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) {
 ; SSE2-LABEL: vsel_4xi16:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    andps {{.*}}(%rip), %xmm1
-; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
-; SSE2-NEXT:    orps %xmm1, %xmm0
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
+; SSE2-NEXT:    movaps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: vsel_4xi16:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm1
-; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
-; SSSE3-NEXT:    orps %xmm1, %xmm0
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
+; SSSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: vsel_4xi16:
@@ -133,16 +129,16 @@ entry:
 define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
 ; SSE2-LABEL: vsel_i32:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    andps {{.*}}(%rip), %xmm1
-; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
-; SSE2-NEXT:    orps %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: vsel_i32:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm1
-; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
-; SSSE3-NEXT:    orps %xmm1, %xmm0
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: vsel_i32:
@@ -167,14 +163,14 @@ entry:
 define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
 ; SSE2-LABEL: vsel_double:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movsd %xmm0, %xmm1
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE2-NEXT:    movapd %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: vsel_double:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movsd %xmm0, %xmm1
-; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSSE3-NEXT:    movapd %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: vsel_double:
@@ -194,14 +190,14 @@ entry:
 define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
 ; SSE2-LABEL: vsel_i64:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movsd %xmm0, %xmm1
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE2-NEXT:    movapd %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: vsel_i64:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movsd %xmm0, %xmm1
-; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSSE3-NEXT:    movapd %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: vsel_i64:
@@ -226,16 +222,20 @@ entry:
 define <8 x i16> @vsel_8xi16(<8 x i16> %v1, <8 x i16> %v2) {
 ; SSE2-LABEL: vsel_8xi16:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    andps {{.*}}(%rip), %xmm1
-; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
-; SSE2-NEXT:    orps %xmm1, %xmm0
+; SSE2-NEXT:    movaps {{.*#+}} xmm2 = [0,65535,65535,65535,0,65535,65535,65535]
+; SSE2-NEXT:    andps %xmm2, %xmm1
+; SSE2-NEXT:    andnps %xmm0, %xmm2
+; SSE2-NEXT:    orps %xmm1, %xmm2
+; SSE2-NEXT:    movaps %xmm2, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: vsel_8xi16:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm1
-; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
-; SSSE3-NEXT:    orps %xmm1, %xmm0
+; SSSE3-NEXT:    movaps {{.*#+}} xmm2 = [0,65535,65535,65535,0,65535,65535,65535]
+; SSSE3-NEXT:    andps %xmm2, %xmm1
+; SSSE3-NEXT:    andnps %xmm0, %xmm2
+; SSSE3-NEXT:    orps %xmm1, %xmm2
+; SSSE3-NEXT:    movaps %xmm2, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: vsel_8xi16:
@@ -255,29 +255,30 @@ entry:
 define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
 ; SSE2-LABEL: vsel_i8:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    andps {{.*}}(%rip), %xmm1
-; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
-; SSE2-NEXT:    orps %xmm1, %xmm0
+; SSE2-NEXT:    movaps {{.*#+}} xmm2 = [255,0,0,0,255,0,0,0,255,255,255,255,255,255,255,255]
+; SSE2-NEXT:    andps %xmm2, %xmm0
+; SSE2-NEXT:    andnps %xmm1, %xmm2
+; SSE2-NEXT:    orps %xmm2, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: vsel_i8:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm1
-; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
-; SSSE3-NEXT:    orps %xmm1, %xmm0
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = zero,xmm1[1,2,3],zero,xmm1[5,6,7],zero,zero,zero,zero,zero,zero,zero,zero
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[8,9,10,11,12,13,14,15]
+; SSSE3-NEXT:    por %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: vsel_i8:
 ; SSE41:       # BB#0: # %entry
 ; SSE41-NEXT:    movdqa %xmm0, %xmm2
-; SSE41-NEXT:    movaps {{.*#+}} xmm0 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
+; SSE41-NEXT:    movaps {{.*#+}} xmm0 = [255,0,0,0,255,0,0,0,255,255,255,255,255,255,255,255]
 ; SSE41-NEXT:    pblendvb %xmm2, %xmm1
 ; SSE41-NEXT:    movdqa %xmm1, %xmm0
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: vsel_i8:
 ; AVX:       # BB#0: # %entry
-; AVX-NEXT:    vmovdqa {{.*#+}} xmm2 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
+; AVX-NEXT:    vmovdqa {{.*#+}} xmm2 = [255,0,0,0,255,0,0,0,255,255,255,255,255,255,255,255]
 ; AVX-NEXT:    vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
 entry:
@@ -291,16 +292,16 @@ entry:
 define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
 ; SSE2-LABEL: vsel_float8:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movss %xmm0, %xmm2
-; SSE2-NEXT:    movss %xmm1, %xmm3
+; SSE2-NEXT:    movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
+; SSE2-NEXT:    movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
 ; SSE2-NEXT:    movaps %xmm2, %xmm0
 ; SSE2-NEXT:    movaps %xmm3, %xmm1
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: vsel_float8:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movss %xmm0, %xmm2
-; SSSE3-NEXT:    movss %xmm1, %xmm3
+; SSSE3-NEXT:    movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
+; SSSE3-NEXT:    movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
 ; SSSE3-NEXT:    movaps %xmm2, %xmm0
 ; SSSE3-NEXT:    movaps %xmm3, %xmm1
 ; SSSE3-NEXT:    retq
@@ -323,16 +324,16 @@ entry:
 define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
 ; SSE2-LABEL: vsel_i328:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movss %xmm0, %xmm2
-; SSE2-NEXT:    movss %xmm1, %xmm3
+; SSE2-NEXT:    movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
+; SSE2-NEXT:    movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
 ; SSE2-NEXT:    movaps %xmm2, %xmm0
 ; SSE2-NEXT:    movaps %xmm3, %xmm1
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: vsel_i328:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movss %xmm0, %xmm2
-; SSSE3-NEXT:    movss %xmm1, %xmm3
+; SSSE3-NEXT:    movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
+; SSSE3-NEXT:    movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
 ; SSSE3-NEXT:    movaps %xmm2, %xmm0
 ; SSSE3-NEXT:    movaps %xmm3, %xmm1
 ; SSSE3-NEXT:    retq
@@ -360,21 +361,21 @@ entry:
 define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
 ; SSE2-LABEL: vsel_double8:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movsd %xmm0, %xmm4
-; SSE2-NEXT:    movsd %xmm2, %xmm6
-; SSE2-NEXT:    movaps %xmm4, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm4 = xmm0[0],xmm4[1]
+; SSE2-NEXT:    movsd {{.*#+}} xmm6 = xmm2[0],xmm6[1]
+; SSE2-NEXT:    movapd %xmm4, %xmm0
 ; SSE2-NEXT:    movaps %xmm5, %xmm1
-; SSE2-NEXT:    movaps %xmm6, %xmm2
+; SSE2-NEXT:    movapd %xmm6, %xmm2
 ; SSE2-NEXT:    movaps %xmm7, %xmm3
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: vsel_double8:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movsd %xmm0, %xmm4
-; SSSE3-NEXT:    movsd %xmm2, %xmm6
-; SSSE3-NEXT:    movaps %xmm4, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm4 = xmm0[0],xmm4[1]
+; SSSE3-NEXT:    movsd {{.*#+}} xmm6 = xmm2[0],xmm6[1]
+; SSSE3-NEXT:    movapd %xmm4, %xmm0
 ; SSSE3-NEXT:    movaps %xmm5, %xmm1
-; SSSE3-NEXT:    movaps %xmm6, %xmm2
+; SSSE3-NEXT:    movapd %xmm6, %xmm2
 ; SSSE3-NEXT:    movaps %xmm7, %xmm3
 ; SSSE3-NEXT:    retq
 ;
@@ -399,21 +400,21 @@ entry:
 define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
 ; SSE2-LABEL: vsel_i648:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movsd %xmm0, %xmm4
-; SSE2-NEXT:    movsd %xmm2, %xmm6
-; SSE2-NEXT:    movaps %xmm4, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm4 = xmm0[0],xmm4[1]
+; SSE2-NEXT:    movsd {{.*#+}} xmm6 = xmm2[0],xmm6[1]
+; SSE2-NEXT:    movapd %xmm4, %xmm0
 ; SSE2-NEXT:    movaps %xmm5, %xmm1
-; SSE2-NEXT:    movaps %xmm6, %xmm2
+; SSE2-NEXT:    movapd %xmm6, %xmm2
 ; SSE2-NEXT:    movaps %xmm7, %xmm3
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: vsel_i648:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movsd %xmm0, %xmm4
-; SSSE3-NEXT:    movsd %xmm2, %xmm6
-; SSSE3-NEXT:    movaps %xmm4, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm4 = xmm0[0],xmm4[1]
+; SSSE3-NEXT:    movsd {{.*#+}} xmm6 = xmm2[0],xmm6[1]
+; SSSE3-NEXT:    movapd %xmm4, %xmm0
 ; SSSE3-NEXT:    movaps %xmm5, %xmm1
-; SSSE3-NEXT:    movaps %xmm6, %xmm2
+; SSSE3-NEXT:    movapd %xmm6, %xmm2
 ; SSSE3-NEXT:    movaps %xmm7, %xmm3
 ; SSSE3-NEXT:    retq
 ;
@@ -444,18 +445,18 @@ entry:
 define <4 x double> @vsel_double4(<4 x double> %v1, <4 x double> %v2) {
 ; SSE2-LABEL: vsel_double4:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movsd %xmm0, %xmm2
-; SSE2-NEXT:    movsd %xmm1, %xmm3
-; SSE2-NEXT:    movaps %xmm2, %xmm0
-; SSE2-NEXT:    movaps %xmm3, %xmm1
+; SSE2-NEXT:    movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
+; SSE2-NEXT:    movsd {{.*#+}} xmm3 = xmm1[0],xmm3[1]
+; SSE2-NEXT:    movapd %xmm2, %xmm0
+; SSE2-NEXT:    movapd %xmm3, %xmm1
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: vsel_double4:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movsd %xmm0, %xmm2
-; SSSE3-NEXT:    movsd %xmm1, %xmm3
-; SSSE3-NEXT:    movaps %xmm2, %xmm0
-; SSSE3-NEXT:    movaps %xmm3, %xmm1
+; SSSE3-NEXT:    movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
+; SSSE3-NEXT:    movsd {{.*#+}} xmm3 = xmm1[0],xmm3[1]
+; SSSE3-NEXT:    movapd %xmm2, %xmm0
+; SSSE3-NEXT:    movapd %xmm3, %xmm1
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: vsel_double4:
@@ -556,16 +557,16 @@ entry:
 define <4 x double> @constant_blendvpd_avx(<4 x double> %xy, <4 x double> %ab) {
 ; SSE2-LABEL: constant_blendvpd_avx:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movsd %xmm1, %xmm3
+; SSE2-NEXT:    movsd {{.*#+}} xmm3 = xmm1[0],xmm3[1]
 ; SSE2-NEXT:    movaps %xmm2, %xmm0
-; SSE2-NEXT:    movaps %xmm3, %xmm1
+; SSE2-NEXT:    movapd %xmm3, %xmm1
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: constant_blendvpd_avx:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movsd %xmm1, %xmm3
+; SSSE3-NEXT:    movsd {{.*#+}} xmm3 = xmm1[0],xmm3[1]
 ; SSSE3-NEXT:    movaps %xmm2, %xmm0
-; SSSE3-NEXT:    movaps %xmm3, %xmm1
+; SSSE3-NEXT:    movapd %xmm3, %xmm1
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: constant_blendvpd_avx:
@@ -586,26 +587,22 @@ entry:
 define <8 x float> @constant_blendvps_avx(<8 x float> %xyzw, <8 x float> %abcd) {
 ; SSE2-LABEL: constant_blendvps_avx:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movaps {{.*#+}} xmm4 = [4294967295,4294967295,4294967295,0]
-; SSE2-NEXT:    andps %xmm4, %xmm2
-; SSE2-NEXT:    movaps {{.*#+}} xmm5 = [0,0,0,4294967295]
-; SSE2-NEXT:    andps %xmm5, %xmm0
-; SSE2-NEXT:    orps %xmm2, %xmm0
-; SSE2-NEXT:    andps %xmm4, %xmm3
-; SSE2-NEXT:    andps %xmm5, %xmm1
-; SSE2-NEXT:    orps %xmm3, %xmm1
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,0],xmm2[2,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,0],xmm3[2,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[2,0]
+; SSE2-NEXT:    movaps %xmm2, %xmm0
+; SSE2-NEXT:    movaps %xmm3, %xmm1
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: constant_blendvps_avx:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movaps {{.*#+}} xmm4 = [4294967295,4294967295,4294967295,0]
-; SSSE3-NEXT:    andps %xmm4, %xmm2
-; SSSE3-NEXT:    movaps {{.*#+}} xmm5 = [0,0,0,4294967295]
-; SSSE3-NEXT:    andps %xmm5, %xmm0
-; SSSE3-NEXT:    orps %xmm2, %xmm0
-; SSSE3-NEXT:    andps %xmm4, %xmm3
-; SSSE3-NEXT:    andps %xmm5, %xmm1
-; SSSE3-NEXT:    orps %xmm3, %xmm1
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,0],xmm2[2,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,0],xmm3[2,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[2,0]
+; SSSE3-NEXT:    movaps %xmm2, %xmm0
+; SSSE3-NEXT:    movaps %xmm3, %xmm1
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: constant_blendvps_avx:
@@ -626,32 +623,32 @@ entry:
 define <32 x i8> @constant_pblendvb_avx2(<32 x i8> %xyzw, <32 x i8> %abcd) {
 ; SSE2-LABEL: constant_pblendvb_avx2:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movaps {{.*#+}} xmm4 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]
-; SSE2-NEXT:    andps %xmm4, %xmm2
-; SSE2-NEXT:    movaps {{.*#+}} xmm5 = [0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0]
-; SSE2-NEXT:    andps %xmm5, %xmm0
-; SSE2-NEXT:    orps %xmm2, %xmm0
-; SSE2-NEXT:    andps %xmm4, %xmm3
-; SSE2-NEXT:    andps %xmm5, %xmm1
-; SSE2-NEXT:    orps %xmm3, %xmm1
+; SSE2-NEXT:    movaps {{.*#+}} xmm4 = [0,0,255,0,255,255,255,0,255,255,255,255,255,255,255,255]
+; SSE2-NEXT:    movaps %xmm4, %xmm5
+; SSE2-NEXT:    andnps %xmm2, %xmm5
+; SSE2-NEXT:    andps %xmm4, %xmm0
+; SSE2-NEXT:    orps %xmm5, %xmm0
+; SSE2-NEXT:    andps %xmm4, %xmm1
+; SSE2-NEXT:    andnps %xmm3, %xmm4
+; SSE2-NEXT:    orps %xmm4, %xmm1
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: constant_pblendvb_avx2:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movaps {{.*#+}} xmm4 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]
-; SSSE3-NEXT:    andps %xmm4, %xmm2
-; SSSE3-NEXT:    movaps {{.*#+}} xmm5 = [0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0]
-; SSSE3-NEXT:    andps %xmm5, %xmm0
-; SSSE3-NEXT:    orps %xmm2, %xmm0
-; SSSE3-NEXT:    andps %xmm4, %xmm3
-; SSSE3-NEXT:    andps %xmm5, %xmm1
-; SSSE3-NEXT:    orps %xmm3, %xmm1
+; SSSE3-NEXT:    movdqa {{.*#+}} xmm4 = [0,1,128,3,128,128,128,7,128,128,128,128,128,128,128,128]
+; SSSE3-NEXT:    pshufb %xmm4, %xmm2
+; SSSE3-NEXT:    movdqa {{.*#+}} xmm5 = [128,128,2,128,4,5,6,128,8,9,10,11,12,13,14,15]
+; SSSE3-NEXT:    pshufb %xmm5, %xmm0
+; SSSE3-NEXT:    por %xmm2, %xmm0
+; SSSE3-NEXT:    pshufb %xmm4, %xmm3
+; SSSE3-NEXT:    pshufb %xmm5, %xmm1
+; SSSE3-NEXT:    por %xmm3, %xmm1
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: constant_pblendvb_avx2:
 ; SSE41:       # BB#0: # %entry
 ; SSE41-NEXT:    movdqa %xmm0, %xmm4
-; SSE41-NEXT:    movaps {{.*#+}} xmm0 = [0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0]
+; SSE41-NEXT:    movaps {{.*#+}} xmm0 = [0,0,255,0,255,255,255,0,255,255,255,255,255,255,255,255]
 ; SSE41-NEXT:    pblendvb %xmm4, %xmm2
 ; SSE41-NEXT:    pblendvb %xmm1, %xmm3
 ; SSE41-NEXT:    movdqa %xmm2, %xmm0
@@ -660,14 +657,15 @@ define <32 x i8> @constant_pblendvb_avx2(<32 x i8> %xyzw, <32 x i8> %abcd) {
 ;
 ; AVX1-LABEL: constant_pblendvb_avx2:
 ; AVX1:       # BB#0: # %entry
-; AVX1-NEXT:    vandps {{.*}}(%rip), %ymm1, %ymm1
-; AVX1-NEXT:    vandps {{.*}}(%rip), %ymm0, %ymm0
-; AVX1-NEXT:    vorps %ymm1, %ymm0, %ymm0
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,0,255,0,255,255,255,0,255,255,255,255,255,255,255,255]
+; AVX1-NEXT:    vpblendvb %xmm2, %xmm0, %xmm1, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: constant_pblendvb_avx2:
 ; AVX2:       # BB#0: # %entry
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0]
+; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,255,0,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
 ; AVX2-NEXT:    vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
 ; AVX2-NEXT:    retq
 entry:
@@ -709,7 +707,7 @@ entry:
 define <8 x float> @blend_shufflevector_8xfloat(<8 x float> %a, <8 x float> %b) {
 ; SSE2-LABEL: blend_shufflevector_8xfloat:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movss %xmm0, %xmm2
+; SSE2-NEXT:    movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm3[3,0]
 ; SSE2-NEXT:    shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[0,2]
 ; SSE2-NEXT:    movaps %xmm2, %xmm0
@@ -718,7 +716,7 @@ define <8 x float> @blend_shufflevector_8xfloat(<8 x float> %a, <8 x float> %b)
 ;
 ; SSSE3-LABEL: blend_shufflevector_8xfloat:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movss %xmm0, %xmm2
+; SSSE3-NEXT:    movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
 ; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm3[3,0]
 ; SSSE3-NEXT:    shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[0,2]
 ; SSSE3-NEXT:    movaps %xmm2, %xmm0
@@ -743,14 +741,14 @@ entry:
 define <4 x double> @blend_shufflevector_4xdouble(<4 x double> %a, <4 x double> %b) {
 ; SSE2-LABEL: blend_shufflevector_4xdouble:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movsd %xmm0, %xmm2
-; SSE2-NEXT:    movaps %xmm2, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
+; SSE2-NEXT:    movapd %xmm2, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: blend_shufflevector_4xdouble:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movsd %xmm0, %xmm2
-; SSSE3-NEXT:    movaps %xmm2, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
+; SSSE3-NEXT:    movapd %xmm2, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: blend_shufflevector_4xdouble:
@@ -770,13 +768,13 @@ entry:
 define <4 x i64> @blend_shufflevector_4xi64(<4 x i64> %a, <4 x i64> %b) {
 ; SSE2-LABEL: blend_shufflevector_4xi64:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movsd %xmm2, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
 ; SSE2-NEXT:    movaps %xmm3, %xmm1
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: blend_shufflevector_4xi64:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movsd %xmm2, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
 ; SSSE3-NEXT:    movaps %xmm3, %xmm1
 ; SSSE3-NEXT:    retq
 ;
diff --git a/test/CodeGen/X86/vector-ctpop.ll b/test/CodeGen/X86/vector-ctpop.ll
index 7091927a9006..59d67928c6fa 100644
--- a/test/CodeGen/X86/vector-ctpop.ll
+++ b/test/CodeGen/X86/vector-ctpop.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 | FileCheck -check-prefix=AVX2 %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=-popcnt | FileCheck -check-prefix=AVX1-NOPOPCNT %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=-popcnt | FileCheck -check-prefix=AVX2-NOPOPCNT %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx2                | FileCheck -check-prefix=AVX2 %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx  -mattr=-popcnt | FileCheck -check-prefix=AVX1-NOPOPCNT %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx2 -mattr=-popcnt | FileCheck -check-prefix=AVX2-NOPOPCNT %s
 
 ; Vector version of:
 ; v = v - ((v >> 1) & 0x55555555)
diff --git a/test/CodeGen/X86/vector-gep.ll b/test/CodeGen/X86/vector-gep.ll
index 3f7ee3aa3e42..ce98e6759b65 100644
--- a/test/CodeGen/X86/vector-gep.ll
+++ b/test/CodeGen/X86/vector-gep.ll
@@ -12,8 +12,8 @@ entry:
   %vecinit2.i = insertelement <4 x i32*> %vecinit.i, i32* %ptr, i32 1
   %vecinit4.i = insertelement <4 x i32*> %vecinit2.i, i32* %ptr, i32 2
   %vecinit6.i = insertelement <4 x i32*> %vecinit4.i, i32* %ptr, i32 3
-  %A2 = getelementptr <4 x i32*> %vecinit6.i, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
-  %A3 = getelementptr <4 x i32*> %A2, <4 x i32> <i32 10, i32 14, i32 19, i32 233>
+  %A2 = getelementptr i32, <4 x i32*> %vecinit6.i, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
+  %A3 = getelementptr i32, <4 x i32*> %A2, <4 x i32> <i32 10, i32 14, i32 19, i32 233>
   ret <4 x i32*> %A3
 }
 
@@ -24,9 +24,9 @@ entry:
 ;CHECK: vpaddd
 ;CHECK-NEXT: vpextrd
 ;CHECK-NEXT: movl
-  %A2 = getelementptr <4 x i32*> %param, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
+  %A2 = getelementptr i32, <4 x i32*> %param, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
   %k = extractelement <4 x i32*> %A2, i32 3
-  %v = load i32* %k
+  %v = load i32, i32* %k
   ret i32 %v
 ;CHECK: ret
 }
@@ -37,9 +37,9 @@ entry:
 ;CHECK-LABEL: AGEP2
 ;CHECK: vpslld $2
 ;CHECK-NEXT: vpadd
-  %A2 = getelementptr <4 x i32*> %param, <4 x i32> %off
+  %A2 = getelementptr i32, <4 x i32*> %param, <4 x i32> %off
   %k = extractelement <4 x i32*> %A2, i32 3
-  %v = load i32* %k
+  %v = load i32, i32* %k
   ret i32 %v
 ;CHECK: ret
 }
@@ -50,7 +50,7 @@ entry:
 ;CHECK-LABEL: AGEP3
 ;CHECK: vpslld $2
 ;CHECK-NEXT: vpadd
-  %A2 = getelementptr <4 x i32*> %param, <4 x i32> %off
+  %A2 = getelementptr i32, <4 x i32*> %param, <4 x i32> %off
   %v = alloca i32
   %k = insertelement <4 x i32*> %A2, i32* %v, i32 3
   ret <4 x i32*> %k
@@ -65,7 +65,7 @@ entry:
 ;CHECK: vpadd
 ; add the base to the offset
 ;CHECK-NEXT: vpadd
-  %A = getelementptr <4 x i16*> %param, <4 x i32> %off
+  %A = getelementptr i16, <4 x i16*> %param, <4 x i32> %off
   ret <4 x i16*> %A
 ;CHECK: ret
 }
@@ -75,7 +75,7 @@ define <4 x i8*> @AGEP5(<4 x i8*> %param, <4 x i8> %off) nounwind {
 entry:
 ;CHECK-LABEL: AGEP5
 ;CHECK: vpaddd
-  %A = getelementptr <4 x i8*> %param, <4 x i8> %off
+  %A = getelementptr i8, <4 x i8*> %param, <4 x i8> %off
   ret <4 x i8*> %A
 ;CHECK: ret
 }
@@ -87,7 +87,7 @@ define <4 x i8*> @AGEP6(<4 x i8*> %param, <4 x i32> %off) nounwind {
 entry:
 ;CHECK-LABEL: AGEP6
 ;CHECK-NOT: pslld
-  %A = getelementptr <4 x i8*> %param, <4 x i32> %off
+  %A = getelementptr i8, <4 x i8*> %param, <4 x i32> %off
   ret <4 x i8*> %A
 ;CHECK: ret
 }
diff --git a/test/CodeGen/X86/vector-idiv.ll b/test/CodeGen/X86/vector-idiv.ll
index 4b269dc923c4..2e482a0f1430 100644
--- a/test/CodeGen/X86/vector-idiv.ll
+++ b/test/CodeGen/X86/vector-idiv.ll
@@ -4,20 +4,19 @@
 
 target triple = "x86_64-unknown-unknown"
 
-define <4 x i32> @test1(<4 x i32> %a) {
+define <4 x i32> @test1(<4 x i32> %a) #0 {
 ; SSE41-LABEL: test1:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    movdqa {{.*#+}} xmm1 = [613566757,613566757,613566757,613566757]
-; SSE41-NEXT:    movdqa %xmm0, %xmm2
-; SSE41-NEXT:    pmuludq %xmm1, %xmm2
-; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
 ; SSE41-NEXT:    pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; SSE41-NEXT:    pmuludq %xmm1, %xmm3
-; SSE41-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,3],xmm3[1,3]
-; SSE41-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
-; SSE41-NEXT:    psubd %xmm2, %xmm0
+; SSE41-NEXT:    pmuludq %xmm2, %xmm3
+; SSE41-NEXT:    pmuludq %xmm0, %xmm1
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
+; SSE41-NEXT:    psubd %xmm1, %xmm0
 ; SSE41-NEXT:    psrld $1, %xmm0
-; SSE41-NEXT:    paddd %xmm2, %xmm0
+; SSE41-NEXT:    paddd %xmm1, %xmm0
 ; SSE41-NEXT:    psrld $2, %xmm0
 ; SSE41-NEXT:    retq
 ;
@@ -26,11 +25,12 @@ define <4 x i32> @test1(<4 x i32> %a) {
 ; SSE-NEXT:    movdqa {{.*#+}} xmm1 = [613566757,613566757,613566757,613566757]
 ; SSE-NEXT:    movdqa %xmm0, %xmm2
 ; SSE-NEXT:    pmuludq %xmm1, %xmm2
+; SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
 ; SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
 ; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
 ; SSE-NEXT:    pmuludq %xmm1, %xmm3
-; SSE-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,3],xmm3[1,3]
-; SSE-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3]
+; SSE-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
 ; SSE-NEXT:    psubd %xmm2, %xmm0
 ; SSE-NEXT:    psrld $1, %xmm0
 ; SSE-NEXT:    paddd %xmm2, %xmm0
@@ -40,12 +40,12 @@ define <4 x i32> @test1(<4 x i32> %a) {
 ; AVX-LABEL: test1:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vpbroadcastd {{.*}}(%rip), %xmm1
-; AVX-NEXT:    vpmuludq %xmm1, %xmm0, %xmm2
-; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; AVX-NEXT:    vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
 ; AVX-NEXT:    vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; AVX-NEXT:    vpmuludq %xmm1, %xmm3, %xmm1
-; AVX-NEXT:    vshufps {{.*#+}} xmm1 = xmm2[1,3],xmm1[1,3]
-; AVX-NEXT:    vshufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
+; AVX-NEXT:    vpmuludq %xmm2, %xmm3, %xmm2
+; AVX-NEXT:    vpmuludq %xmm1, %xmm0, %xmm1
+; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; AVX-NEXT:    vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
 ; AVX-NEXT:    vpsubd %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    vpsrld $1, %xmm0, %xmm0
 ; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
@@ -55,26 +55,26 @@ define <4 x i32> @test1(<4 x i32> %a) {
   ret <4 x i32> %div
 }
 
-define <8 x i32> @test2(<8 x i32> %a) {
+define <8 x i32> @test2(<8 x i32> %a) #0 {
 ; SSE41-LABEL: test2:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    movdqa {{.*#+}} xmm2 = [613566757,613566757,613566757,613566757]
-; SSE41-NEXT:    movdqa %xmm0, %xmm3
-; SSE41-NEXT:    pmuludq %xmm2, %xmm3
-; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3]
-; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm0[1,1,3,3]
-; SSE41-NEXT:    pmuludq %xmm4, %xmm5
-; SSE41-NEXT:    shufps {{.*#+}} xmm3 = xmm3[1,3],xmm5[1,3]
-; SSE41-NEXT:    shufps {{.*#+}} xmm3 = xmm3[0,2,1,3]
-; SSE41-NEXT:    psubd %xmm3, %xmm0
+; SSE41-NEXT:    pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; SSE41-NEXT:    pmuludq %xmm3, %xmm4
+; SSE41-NEXT:    movdqa %xmm0, %xmm5
+; SSE41-NEXT:    pmuludq %xmm2, %xmm5
+; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm5 = xmm5[0,1],xmm4[2,3],xmm5[4,5],xmm4[6,7]
+; SSE41-NEXT:    psubd %xmm5, %xmm0
 ; SSE41-NEXT:    psrld $1, %xmm0
-; SSE41-NEXT:    paddd %xmm3, %xmm0
+; SSE41-NEXT:    paddd %xmm5, %xmm0
 ; SSE41-NEXT:    psrld $2, %xmm0
+; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm1[1,1,3,3]
+; SSE41-NEXT:    pmuludq %xmm3, %xmm4
 ; SSE41-NEXT:    pmuludq %xmm1, %xmm2
-; SSE41-NEXT:    pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
-; SSE41-NEXT:    pmuludq %xmm4, %xmm3
-; SSE41-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,3],xmm3[1,3]
-; SSE41-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm4[2,3],xmm2[4,5],xmm4[6,7]
 ; SSE41-NEXT:    psubd %xmm2, %xmm1
 ; SSE41-NEXT:    psrld $1, %xmm1
 ; SSE41-NEXT:    paddd %xmm2, %xmm1
@@ -86,20 +86,22 @@ define <8 x i32> @test2(<8 x i32> %a) {
 ; SSE-NEXT:    movdqa {{.*#+}} xmm2 = [613566757,613566757,613566757,613566757]
 ; SSE-NEXT:    movdqa %xmm0, %xmm3
 ; SSE-NEXT:    pmuludq %xmm2, %xmm3
+; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[1,3,2,3]
 ; SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3]
 ; SSE-NEXT:    pshufd {{.*#+}} xmm5 = xmm0[1,1,3,3]
 ; SSE-NEXT:    pmuludq %xmm4, %xmm5
-; SSE-NEXT:    shufps {{.*#+}} xmm3 = xmm3[1,3],xmm5[1,3]
-; SSE-NEXT:    shufps {{.*#+}} xmm3 = xmm3[0,2,1,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm5 = xmm5[1,3,2,3]
+; SSE-NEXT:    punpckldq {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[1]
 ; SSE-NEXT:    psubd %xmm3, %xmm0
 ; SSE-NEXT:    psrld $1, %xmm0
 ; SSE-NEXT:    paddd %xmm3, %xmm0
 ; SSE-NEXT:    psrld $2, %xmm0
 ; SSE-NEXT:    pmuludq %xmm1, %xmm2
+; SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
 ; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
 ; SSE-NEXT:    pmuludq %xmm4, %xmm3
-; SSE-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,3],xmm3[1,3]
-; SSE-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[1,3,2,3]
+; SSE-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
 ; SSE-NEXT:    psubd %xmm2, %xmm1
 ; SSE-NEXT:    psrld $1, %xmm1
 ; SSE-NEXT:    paddd %xmm2, %xmm1
@@ -124,7 +126,7 @@ define <8 x i32> @test2(<8 x i32> %a) {
   ret <8 x i32> %div
 }
 
-define <8 x i16> @test3(<8 x i16> %a) {
+define <8 x i16> @test3(<8 x i16> %a) #0 {
 ; SSE41-LABEL: test3:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    movdqa {{.*#+}} xmm1 = [9363,9363,9363,9363,9363,9363,9363,9363]
@@ -157,7 +159,7 @@ define <8 x i16> @test3(<8 x i16> %a) {
   ret <8 x i16> %div
 }
 
-define <16 x i16> @test4(<16 x i16> %a) {
+define <16 x i16> @test4(<16 x i16> %a) #0 {
 ; SSE41-LABEL: test4:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    movdqa {{.*#+}} xmm2 = [9363,9363,9363,9363,9363,9363,9363,9363]
@@ -202,7 +204,7 @@ define <16 x i16> @test4(<16 x i16> %a) {
   ret <16 x i16> %div
 }
 
-define <8 x i16> @test5(<8 x i16> %a) {
+define <8 x i16> @test5(<8 x i16> %a) #0 {
 ; SSE41-LABEL: test5:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    pmulhw {{.*}}(%rip), %xmm0
@@ -232,7 +234,7 @@ define <8 x i16> @test5(<8 x i16> %a) {
   ret <8 x i16> %div
 }
 
-define <16 x i16> @test6(<16 x i16> %a) {
+define <16 x i16> @test6(<16 x i16> %a) #0 {
 ; SSE41-LABEL: test6:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    movdqa {{.*#+}} xmm2 = [18725,18725,18725,18725,18725,18725,18725,18725]
@@ -274,7 +276,7 @@ define <16 x i16> @test6(<16 x i16> %a) {
   ret <16 x i16> %div
 }
 
-define <16 x i8> @test7(<16 x i8> %a) {
+define <16 x i8> @test7(<16 x i8> %a) #0 {
 ; SSE41-LABEL: test7:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    pextrb $1, %xmm0, %eax
@@ -458,6 +460,9 @@ define <16 x i8> @test7(<16 x i8> %a) {
 ;
 ; SSE-LABEL: test7:
 ; SSE:       # BB#0:
+; SSE-NEXT:    pushq %rbp
+; SSE-NEXT:    pushq %r14
+; SSE-NEXT:    pushq %rbx
 ; SSE-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
 ; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
 ; SSE-NEXT:    imull $-109, %eax, %ecx
@@ -469,156 +474,156 @@ define <16 x i8> @test7(<16 x i8> %a) {
 ; SSE-NEXT:    addb %al, %cl
 ; SSE-NEXT:    movzbl %cl, %eax
 ; SSE-NEXT:    movd %eax, %xmm0
+; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %r14d
+; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %edx
+; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %r9d
 ; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
-; SSE-NEXT:    imull $-109, %eax, %ecx
-; SSE-NEXT:    shrl $8, %ecx
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movb %cl, %al
-; SSE-NEXT:    shrb $7, %al
-; SSE-NEXT:    sarb $2, %cl
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
-; SSE-NEXT:    movd %eax, %xmm1
+; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %r11d
+; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %ecx
+; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %r8d
+; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %esi
+; SSE-NEXT:    imull $-109, %esi, %edi
+; SSE-NEXT:    shrl $8, %edi
+; SSE-NEXT:    addb %sil, %dil
+; SSE-NEXT:    movb %dil, %bl
+; SSE-NEXT:    shrb $7, %bl
+; SSE-NEXT:    sarb $2, %dil
+; SSE-NEXT:    addb %bl, %dil
+; SSE-NEXT:    movzbl %dil, %esi
+; SSE-NEXT:    movd %esi, %xmm1
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
-; SSE-NEXT:    imull $-109, %eax, %ecx
-; SSE-NEXT:    shrl $8, %ecx
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movb %cl, %al
+; SSE-NEXT:    imull $-109, %eax, %esi
+; SSE-NEXT:    shrl $8, %esi
+; SSE-NEXT:    addb %al, %sil
+; SSE-NEXT:    movb %sil, %al
 ; SSE-NEXT:    shrb $7, %al
-; SSE-NEXT:    sarb $2, %cl
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
+; SSE-NEXT:    sarb $2, %sil
+; SSE-NEXT:    addb %al, %sil
+; SSE-NEXT:    movzbl %sil, %eax
 ; SSE-NEXT:    movd %eax, %xmm2
-; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
-; SSE-NEXT:    imull $-109, %eax, %ecx
-; SSE-NEXT:    shrl $8, %ecx
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movb %cl, %al
+; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %ebp
+; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %esi
+; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %r10d
+; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %edi
+; SSE-NEXT:    imull $-109, %edi, %ebx
+; SSE-NEXT:    shrl $8, %ebx
+; SSE-NEXT:    addb %dil, %bl
+; SSE-NEXT:    movb %bl, %al
 ; SSE-NEXT:    shrb $7, %al
-; SSE-NEXT:    sarb $2, %cl
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
+; SSE-NEXT:    sarb $2, %bl
+; SSE-NEXT:    addb %al, %bl
+; SSE-NEXT:    movzbl %bl, %eax
 ; SSE-NEXT:    movd %eax, %xmm0
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
-; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
-; SSE-NEXT:    imull $-109, %eax, %ecx
-; SSE-NEXT:    shrl $8, %ecx
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movb %cl, %al
-; SSE-NEXT:    shrb $7, %al
-; SSE-NEXT:    sarb $2, %cl
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
+; SSE-NEXT:    imull $-109, %edx, %eax
+; SSE-NEXT:    shrl $8, %eax
+; SSE-NEXT:    addb %dl, %al
+; SSE-NEXT:    movb %al, %dl
+; SSE-NEXT:    shrb $7, %dl
+; SSE-NEXT:    sarb $2, %al
+; SSE-NEXT:    addb %dl, %al
+; SSE-NEXT:    movzbl %al, %eax
 ; SSE-NEXT:    movd %eax, %xmm1
-; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
-; SSE-NEXT:    imull $-109, %eax, %ecx
-; SSE-NEXT:    shrl $8, %ecx
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movb %cl, %al
-; SSE-NEXT:    shrb $7, %al
-; SSE-NEXT:    sarb $2, %cl
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
+; SSE-NEXT:    imull $-109, %esi, %eax
+; SSE-NEXT:    shrl $8, %eax
+; SSE-NEXT:    addb %sil, %al
+; SSE-NEXT:    movb %al, %dl
+; SSE-NEXT:    shrb $7, %dl
+; SSE-NEXT:    sarb $2, %al
+; SSE-NEXT:    addb %dl, %al
+; SSE-NEXT:    movzbl %al, %eax
 ; SSE-NEXT:    movd %eax, %xmm2
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
-; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
-; SSE-NEXT:    imull $-109, %eax, %ecx
-; SSE-NEXT:    shrl $8, %ecx
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movb %cl, %al
-; SSE-NEXT:    shrb $7, %al
-; SSE-NEXT:    sarb $2, %cl
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
+; SSE-NEXT:    imull $-109, %ecx, %eax
+; SSE-NEXT:    shrl $8, %eax
+; SSE-NEXT:    addb %cl, %al
+; SSE-NEXT:    movb %al, %cl
+; SSE-NEXT:    shrb $7, %cl
+; SSE-NEXT:    sarb $2, %al
+; SSE-NEXT:    addb %cl, %al
+; SSE-NEXT:    movzbl %al, %eax
 ; SSE-NEXT:    movd %eax, %xmm3
+; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %ecx
 ; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
-; SSE-NEXT:    imull $-109, %eax, %ecx
-; SSE-NEXT:    shrl $8, %ecx
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movb %cl, %al
+; SSE-NEXT:    imull $-109, %eax, %edx
+; SSE-NEXT:    shrl $8, %edx
+; SSE-NEXT:    addb %al, %dl
+; SSE-NEXT:    movb %dl, %al
 ; SSE-NEXT:    shrb $7, %al
-; SSE-NEXT:    sarb $2, %cl
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
+; SSE-NEXT:    sarb $2, %dl
+; SSE-NEXT:    addb %al, %dl
+; SSE-NEXT:    movzbl %dl, %eax
 ; SSE-NEXT:    movd %eax, %xmm1
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3],xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7]
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
-; SSE-NEXT:    imull $-109, %eax, %ecx
-; SSE-NEXT:    shrl $8, %ecx
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movb %cl, %al
-; SSE-NEXT:    shrb $7, %al
-; SSE-NEXT:    sarb $2, %cl
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
+; SSE-NEXT:    imull $-109, %r14d, %eax
+; SSE-NEXT:    shrl $8, %eax
+; SSE-NEXT:    addb %r14b, %al
+; SSE-NEXT:    movb %al, %dl
+; SSE-NEXT:    shrb $7, %dl
+; SSE-NEXT:    sarb $2, %al
+; SSE-NEXT:    addb %dl, %al
+; SSE-NEXT:    movzbl %al, %eax
 ; SSE-NEXT:    movd %eax, %xmm2
-; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
-; SSE-NEXT:    imull $-109, %eax, %ecx
-; SSE-NEXT:    shrl $8, %ecx
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movb %cl, %al
-; SSE-NEXT:    shrb $7, %al
-; SSE-NEXT:    sarb $2, %cl
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
+; SSE-NEXT:    imull $-109, %ebp, %eax
+; SSE-NEXT:    shrl $8, %eax
+; SSE-NEXT:    addb %bpl, %al
+; SSE-NEXT:    movb %al, %dl
+; SSE-NEXT:    shrb $7, %dl
+; SSE-NEXT:    sarb $2, %al
+; SSE-NEXT:    addb %dl, %al
+; SSE-NEXT:    movzbl %al, %eax
 ; SSE-NEXT:    movd %eax, %xmm0
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
-; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
-; SSE-NEXT:    imull $-109, %eax, %ecx
-; SSE-NEXT:    shrl $8, %ecx
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movb %cl, %al
-; SSE-NEXT:    shrb $7, %al
-; SSE-NEXT:    sarb $2, %cl
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
+; SSE-NEXT:    imull $-109, %r11d, %eax
+; SSE-NEXT:    shrl $8, %eax
+; SSE-NEXT:    addb %r11b, %al
+; SSE-NEXT:    movb %al, %dl
+; SSE-NEXT:    shrb $7, %dl
+; SSE-NEXT:    sarb $2, %al
+; SSE-NEXT:    addb %dl, %al
+; SSE-NEXT:    movzbl %al, %eax
 ; SSE-NEXT:    movd %eax, %xmm3
-; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
-; SSE-NEXT:    imull $-109, %eax, %ecx
-; SSE-NEXT:    shrl $8, %ecx
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movb %cl, %al
-; SSE-NEXT:    shrb $7, %al
-; SSE-NEXT:    sarb $2, %cl
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
+; SSE-NEXT:    imull $-109, %ecx, %eax
+; SSE-NEXT:    shrl $8, %eax
+; SSE-NEXT:    addb %cl, %al
+; SSE-NEXT:    movb %al, %cl
+; SSE-NEXT:    shrb $7, %cl
+; SSE-NEXT:    sarb $2, %al
+; SSE-NEXT:    addb %cl, %al
+; SSE-NEXT:    movzbl %al, %eax
 ; SSE-NEXT:    movd %eax, %xmm2
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1],xmm2[2],xmm3[2],xmm2[3],xmm3[3],xmm2[4],xmm3[4],xmm2[5],xmm3[5],xmm2[6],xmm3[6],xmm2[7],xmm3[7]
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
-; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
-; SSE-NEXT:    imull $-109, %eax, %ecx
-; SSE-NEXT:    shrl $8, %ecx
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movb %cl, %al
-; SSE-NEXT:    shrb $7, %al
-; SSE-NEXT:    sarb $2, %cl
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
+; SSE-NEXT:    imull $-109, %r9d, %eax
+; SSE-NEXT:    shrl $8, %eax
+; SSE-NEXT:    addb %r9b, %al
+; SSE-NEXT:    movb %al, %cl
+; SSE-NEXT:    shrb $7, %cl
+; SSE-NEXT:    sarb $2, %al
+; SSE-NEXT:    addb %cl, %al
+; SSE-NEXT:    movzbl %al, %eax
 ; SSE-NEXT:    movd %eax, %xmm0
-; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
-; SSE-NEXT:    imull $-109, %eax, %ecx
-; SSE-NEXT:    shrl $8, %ecx
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movb %cl, %al
-; SSE-NEXT:    shrb $7, %al
-; SSE-NEXT:    sarb $2, %cl
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
+; SSE-NEXT:    imull $-109, %r10d, %eax
+; SSE-NEXT:    shrl $8, %eax
+; SSE-NEXT:    addb %r10b, %al
+; SSE-NEXT:    movb %al, %cl
+; SSE-NEXT:    shrb $7, %cl
+; SSE-NEXT:    sarb $2, %al
+; SSE-NEXT:    addb %cl, %al
+; SSE-NEXT:    movzbl %al, %eax
 ; SSE-NEXT:    movd %eax, %xmm3
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
-; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
-; SSE-NEXT:    imull $-109, %eax, %ecx
-; SSE-NEXT:    shrl $8, %ecx
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movb %cl, %al
-; SSE-NEXT:    shrb $7, %al
-; SSE-NEXT:    sarb $2, %cl
-; SSE-NEXT:    addb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
+; SSE-NEXT:    imull $-109, %r8d, %eax
+; SSE-NEXT:    shrl $8, %eax
+; SSE-NEXT:    addb %r8b, %al
+; SSE-NEXT:    movb %al, %cl
+; SSE-NEXT:    shrb $7, %cl
+; SSE-NEXT:    sarb $2, %al
+; SSE-NEXT:    addb %cl, %al
+; SSE-NEXT:    movzbl %al, %eax
 ; SSE-NEXT:    movd %eax, %xmm4
 ; SSE-NEXT:    movsbl -{{[0-9]+}}(%rsp), %eax
 ; SSE-NEXT:    imull $-109, %eax, %ecx
@@ -634,6 +639,9 @@ define <16 x i8> @test7(<16 x i8> %a) {
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7]
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; SSE-NEXT:    popq %rbx
+; SSE-NEXT:    popq %r14
+; SSE-NEXT:    popq %rbp
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test7:
@@ -819,17 +827,16 @@ define <16 x i8> @test7(<16 x i8> %a) {
   ret <16 x i8> %div
 }
 
-define <4 x i32> @test8(<4 x i32> %a) {
+define <4 x i32> @test8(<4 x i32> %a) #0 {
 ; SSE41-LABEL: test8:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    movdqa {{.*#+}} xmm2 = [2454267027,2454267027,2454267027,2454267027]
-; SSE41-NEXT:    movdqa %xmm0, %xmm1
-; SSE41-NEXT:    pmuldq %xmm2, %xmm1
-; SSE41-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; SSE41-NEXT:    movdqa {{.*#+}} xmm1 = [2454267027,2454267027,2454267027,2454267027]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
 ; SSE41-NEXT:    pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
 ; SSE41-NEXT:    pmuldq %xmm2, %xmm3
-; SSE41-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,3],xmm3[1,3]
-; SSE41-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
+; SSE41-NEXT:    pmuldq %xmm0, %xmm1
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
 ; SSE41-NEXT:    paddd %xmm0, %xmm1
 ; SSE41-NEXT:    movdqa %xmm1, %xmm0
 ; SSE41-NEXT:    psrld $31, %xmm0
@@ -840,22 +847,22 @@ define <4 x i32> @test8(<4 x i32> %a) {
 ;
 ; SSE-LABEL: test8:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movdqa {{.*#+}} xmm2 = [2454267027,2454267027,2454267027,2454267027]
-; SSE-NEXT:    movdqa %xmm2, %xmm1
+; SSE-NEXT:    movdqa {{.*#+}} xmm1 = [2454267027,2454267027,2454267027,2454267027]
+; SSE-NEXT:    movdqa %xmm0, %xmm2
+; SSE-NEXT:    psrad $31, %xmm2
+; SSE-NEXT:    pand %xmm1, %xmm2
+; SSE-NEXT:    movdqa %xmm0, %xmm3
+; SSE-NEXT:    pmuludq %xmm1, %xmm3
+; SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm1[1,1,3,3]
 ; SSE-NEXT:    psrad $31, %xmm1
 ; SSE-NEXT:    pand %xmm0, %xmm1
-; SSE-NEXT:    movdqa %xmm0, %xmm3
-; SSE-NEXT:    psrad $31, %xmm3
-; SSE-NEXT:    pand %xmm2, %xmm3
-; SSE-NEXT:    paddd %xmm1, %xmm3
-; SSE-NEXT:    movdqa %xmm0, %xmm1
-; SSE-NEXT:    pmuludq %xmm2, %xmm1
-; SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
-; SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
-; SSE-NEXT:    pmuludq %xmm2, %xmm4
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,3],xmm4[1,3]
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
-; SSE-NEXT:    psubd %xmm3, %xmm1
+; SSE-NEXT:    paddd %xmm1, %xmm2
+; SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
+; SSE-NEXT:    pmuludq %xmm4, %xmm3
+; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[1,3,2,3]
+; SSE-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
+; SSE-NEXT:    psubd %xmm2, %xmm1
 ; SSE-NEXT:    paddd %xmm0, %xmm1
 ; SSE-NEXT:    movdqa %xmm1, %xmm0
 ; SSE-NEXT:    psrld $31, %xmm0
@@ -867,12 +874,12 @@ define <4 x i32> @test8(<4 x i32> %a) {
 ; AVX-LABEL: test8:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vpbroadcastd {{.*}}(%rip), %xmm1
-; AVX-NEXT:    vpmuldq %xmm1, %xmm0, %xmm2
-; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; AVX-NEXT:    vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
 ; AVX-NEXT:    vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; AVX-NEXT:    vpmuldq %xmm1, %xmm3, %xmm1
-; AVX-NEXT:    vshufps {{.*#+}} xmm1 = xmm2[1,3],xmm1[1,3]
-; AVX-NEXT:    vshufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
+; AVX-NEXT:    vpmuldq %xmm2, %xmm3, %xmm2
+; AVX-NEXT:    vpmuldq %xmm1, %xmm0, %xmm1
+; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; AVX-NEXT:    vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
 ; AVX-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    vpsrld $31, %xmm0, %xmm1
 ; AVX-NEXT:    vpsrad $2, %xmm0, %xmm0
@@ -882,78 +889,80 @@ define <4 x i32> @test8(<4 x i32> %a) {
   ret <4 x i32> %div
 }
 
-define <8 x i32> @test9(<8 x i32> %a) {
+define <8 x i32> @test9(<8 x i32> %a) #0 {
 ; SSE41-LABEL: test9:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    movdqa %xmm1, %xmm2
-; SSE41-NEXT:    movdqa %xmm0, %xmm3
-; SSE41-NEXT:    movdqa {{.*#+}} xmm1 = [2454267027,2454267027,2454267027,2454267027]
-; SSE41-NEXT:   # kill: XMM0<def> XMM3<kill>
-; SSE41-NEXT:    pmuldq %xmm1, %xmm0
-; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm1[1,1,3,3]
-; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm3[1,1,3,3]
+; SSE41-NEXT:    movdqa {{.*#+}} xmm3 = [2454267027,2454267027,2454267027,2454267027]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm0[1,1,3,3]
 ; SSE41-NEXT:    pmuldq %xmm4, %xmm5
-; SSE41-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,3],xmm5[1,3]
-; SSE41-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
-; SSE41-NEXT:    paddd %xmm3, %xmm0
-; SSE41-NEXT:    movdqa %xmm0, %xmm3
-; SSE41-NEXT:    psrld $31, %xmm3
-; SSE41-NEXT:    psrad $2, %xmm0
-; SSE41-NEXT:    paddd %xmm3, %xmm0
-; SSE41-NEXT:    pmuldq %xmm2, %xmm1
-; SSE41-NEXT:    pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
-; SSE41-NEXT:    pmuldq %xmm4, %xmm3
-; SSE41-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,3],xmm3[1,3]
-; SSE41-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
-; SSE41-NEXT:    paddd %xmm2, %xmm1
-; SSE41-NEXT:    movdqa %xmm1, %xmm2
-; SSE41-NEXT:    psrld $31, %xmm2
-; SSE41-NEXT:    psrad $2, %xmm1
-; SSE41-NEXT:    paddd %xmm2, %xmm1
+; SSE41-NEXT:    movdqa %xmm0, %xmm2
+; SSE41-NEXT:    pmuldq %xmm3, %xmm2
+; SSE41-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm5[2,3],xmm2[4,5],xmm5[6,7]
+; SSE41-NEXT:    paddd %xmm0, %xmm2
+; SSE41-NEXT:    movdqa %xmm2, %xmm0
+; SSE41-NEXT:    psrld $31, %xmm0
+; SSE41-NEXT:    psrad $2, %xmm2
+; SSE41-NEXT:    paddd %xmm0, %xmm2
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
+; SSE41-NEXT:    pmuldq %xmm4, %xmm0
+; SSE41-NEXT:    pmuldq %xmm1, %xmm3
+; SSE41-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm0[2,3],xmm3[4,5],xmm0[6,7]
+; SSE41-NEXT:    paddd %xmm1, %xmm3
+; SSE41-NEXT:    movdqa %xmm3, %xmm0
+; SSE41-NEXT:    psrld $31, %xmm0
+; SSE41-NEXT:    psrad $2, %xmm3
+; SSE41-NEXT:    paddd %xmm0, %xmm3
+; SSE41-NEXT:    movdqa %xmm2, %xmm0
+; SSE41-NEXT:    movdqa %xmm3, %xmm1
 ; SSE41-NEXT:    retq
 ;
 ; SSE-LABEL: test9:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movdqa %xmm1, %xmm2
-; SSE-NEXT:    movdqa %xmm0, %xmm3
-; SSE-NEXT:    movdqa {{.*#+}} xmm1 = [2454267027,2454267027,2454267027,2454267027]
-; SSE-NEXT:    movdqa %xmm1, %xmm4
+; SSE-NEXT:    movdqa %xmm0, %xmm2
+; SSE-NEXT:    movdqa {{.*#+}} xmm3 = [2454267027,2454267027,2454267027,2454267027]
+; SSE-NEXT:    movdqa %xmm3, %xmm4
 ; SSE-NEXT:    psrad $31, %xmm4
 ; SSE-NEXT:    movdqa %xmm4, %xmm0
-; SSE-NEXT:    pand %xmm3, %xmm0
-; SSE-NEXT:    movdqa %xmm3, %xmm5
+; SSE-NEXT:    pand %xmm2, %xmm0
+; SSE-NEXT:    movdqa %xmm2, %xmm5
 ; SSE-NEXT:    psrad $31, %xmm5
-; SSE-NEXT:    pand %xmm1, %xmm5
+; SSE-NEXT:    pand %xmm3, %xmm5
 ; SSE-NEXT:    paddd %xmm0, %xmm5
-; SSE-NEXT:    movdqa %xmm3, %xmm0
-; SSE-NEXT:    pmuludq %xmm1, %xmm0
-; SSE-NEXT:    pshufd {{.*#+}} xmm6 = xmm1[1,1,3,3]
-; SSE-NEXT:    pshufd {{.*#+}} xmm7 = xmm3[1,1,3,3]
+; SSE-NEXT:    movdqa %xmm2, %xmm0
+; SSE-NEXT:    pmuludq %xmm3, %xmm0
+; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm6 = xmm3[1,1,3,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm7 = xmm2[1,1,3,3]
 ; SSE-NEXT:    pmuludq %xmm6, %xmm7
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,3],xmm7[1,3]
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm7 = xmm7[1,3,2,3]
+; SSE-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[1]
 ; SSE-NEXT:    psubd %xmm5, %xmm0
-; SSE-NEXT:    paddd %xmm3, %xmm0
-; SSE-NEXT:    movdqa %xmm0, %xmm3
-; SSE-NEXT:    psrld $31, %xmm3
-; SSE-NEXT:    psrad $2, %xmm0
-; SSE-NEXT:    paddd %xmm3, %xmm0
-; SSE-NEXT:    pand %xmm2, %xmm4
-; SSE-NEXT:    movdqa %xmm2, %xmm3
-; SSE-NEXT:    psrad $31, %xmm3
-; SSE-NEXT:    pand %xmm1, %xmm3
-; SSE-NEXT:    paddd %xmm4, %xmm3
-; SSE-NEXT:    pmuludq %xmm2, %xmm1
-; SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3]
-; SSE-NEXT:    pmuludq %xmm6, %xmm4
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,3],xmm4[1,3]
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
-; SSE-NEXT:    psubd %xmm3, %xmm1
-; SSE-NEXT:    paddd %xmm2, %xmm1
-; SSE-NEXT:    movdqa %xmm1, %xmm2
+; SSE-NEXT:    paddd %xmm2, %xmm0
+; SSE-NEXT:    movdqa %xmm0, %xmm2
 ; SSE-NEXT:    psrld $31, %xmm2
-; SSE-NEXT:    psrad $2, %xmm1
-; SSE-NEXT:    paddd %xmm2, %xmm1
+; SSE-NEXT:    psrad $2, %xmm0
+; SSE-NEXT:    paddd %xmm2, %xmm0
+; SSE-NEXT:    pand %xmm1, %xmm4
+; SSE-NEXT:    movdqa %xmm1, %xmm5
+; SSE-NEXT:    psrad $31, %xmm5
+; SSE-NEXT:    pand %xmm3, %xmm5
+; SSE-NEXT:    paddd %xmm4, %xmm5
+; SSE-NEXT:    pmuludq %xmm1, %xmm3
+; SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
+; SSE-NEXT:    pmuludq %xmm6, %xmm3
+; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[1,3,2,3]
+; SSE-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
+; SSE-NEXT:    psubd %xmm5, %xmm2
+; SSE-NEXT:    paddd %xmm1, %xmm2
+; SSE-NEXT:    movdqa %xmm2, %xmm1
+; SSE-NEXT:    psrld $31, %xmm1
+; SSE-NEXT:    psrad $2, %xmm2
+; SSE-NEXT:    paddd %xmm1, %xmm2
+; SSE-NEXT:    movdqa %xmm2, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test9:
@@ -974,76 +983,80 @@ define <8 x i32> @test9(<8 x i32> %a) {
   ret <8 x i32> %div
 }
 
-define <8 x i32> @test10(<8 x i32> %a) {
+define <8 x i32> @test10(<8 x i32> %a) #0 {
 ; SSE41-LABEL: test10:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    movdqa {{.*#+}} xmm2 = [613566757,613566757,613566757,613566757]
-; SSE41-NEXT:    movdqa %xmm0, %xmm3
-; SSE41-NEXT:    pmuludq %xmm2, %xmm3
-; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3]
-; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm0[1,1,3,3]
-; SSE41-NEXT:    pmuludq %xmm4, %xmm5
-; SSE41-NEXT:    shufps {{.*#+}} xmm3 = xmm3[1,3],xmm5[1,3]
-; SSE41-NEXT:    shufps {{.*#+}} xmm3 = xmm3[0,2,1,3]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; SSE41-NEXT:    pmuludq %xmm3, %xmm4
 ; SSE41-NEXT:    movdqa %xmm0, %xmm5
-; SSE41-NEXT:    psubd %xmm3, %xmm5
-; SSE41-NEXT:    psrld $1, %xmm5
-; SSE41-NEXT:    paddd %xmm3, %xmm5
-; SSE41-NEXT:    psrld $2, %xmm5
-; SSE41-NEXT:    movdqa {{.*#+}} xmm3 = [7,7,7,7]
-; SSE41-NEXT:    pmulld %xmm3, %xmm5
-; SSE41-NEXT:    psubd %xmm5, %xmm0
-; SSE41-NEXT:    pmuludq %xmm1, %xmm2
-; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm1[1,1,3,3]
-; SSE41-NEXT:    pmuludq %xmm4, %xmm5
-; SSE41-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,3],xmm5[1,3]
-; SSE41-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
-; SSE41-NEXT:    movdqa %xmm1, %xmm4
-; SSE41-NEXT:    psubd %xmm2, %xmm4
+; SSE41-NEXT:    pmuludq %xmm2, %xmm5
+; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm5 = xmm5[0,1],xmm4[2,3],xmm5[4,5],xmm4[6,7]
+; SSE41-NEXT:    movdqa %xmm0, %xmm4
+; SSE41-NEXT:    psubd %xmm5, %xmm4
 ; SSE41-NEXT:    psrld $1, %xmm4
-; SSE41-NEXT:    paddd %xmm2, %xmm4
+; SSE41-NEXT:    paddd %xmm5, %xmm4
 ; SSE41-NEXT:    psrld $2, %xmm4
-; SSE41-NEXT:    pmulld %xmm3, %xmm4
-; SSE41-NEXT:    psubd %xmm4, %xmm1
+; SSE41-NEXT:    movdqa {{.*#+}} xmm5 = [7,7,7,7]
+; SSE41-NEXT:    pmulld %xmm5, %xmm4
+; SSE41-NEXT:    psubd %xmm4, %xmm0
+; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm1[1,1,3,3]
+; SSE41-NEXT:    pmuludq %xmm3, %xmm4
+; SSE41-NEXT:    pmuludq %xmm1, %xmm2
+; SSE41-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm4[2,3],xmm2[4,5],xmm4[6,7]
+; SSE41-NEXT:    movdqa %xmm1, %xmm3
+; SSE41-NEXT:    psubd %xmm2, %xmm3
+; SSE41-NEXT:    psrld $1, %xmm3
+; SSE41-NEXT:    paddd %xmm2, %xmm3
+; SSE41-NEXT:    psrld $2, %xmm3
+; SSE41-NEXT:    pmulld %xmm5, %xmm3
+; SSE41-NEXT:    psubd %xmm3, %xmm1
 ; SSE41-NEXT:    retq
 ;
 ; SSE-LABEL: test10:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movdqa {{.*#+}} xmm2 = [613566757,613566757,613566757,613566757]
-; SSE-NEXT:    movdqa %xmm0, %xmm3
-; SSE-NEXT:    pmuludq %xmm2, %xmm3
-; SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3]
+; SSE-NEXT:    movdqa {{.*#+}} xmm3 = [613566757,613566757,613566757,613566757]
+; SSE-NEXT:    movdqa %xmm0, %xmm2
+; SSE-NEXT:    pmuludq %xmm3, %xmm2
+; SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
 ; SSE-NEXT:    pshufd {{.*#+}} xmm5 = xmm0[1,1,3,3]
 ; SSE-NEXT:    pmuludq %xmm4, %xmm5
-; SSE-NEXT:    shufps {{.*#+}} xmm3 = xmm3[1,3],xmm5[1,3]
-; SSE-NEXT:    shufps {{.*#+}} xmm3 = xmm3[0,2,1,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm5 = xmm5[1,3,2,3]
+; SSE-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1]
 ; SSE-NEXT:    movdqa %xmm0, %xmm5
-; SSE-NEXT:    psubd %xmm3, %xmm5
+; SSE-NEXT:    psubd %xmm2, %xmm5
 ; SSE-NEXT:    psrld $1, %xmm5
-; SSE-NEXT:    paddd %xmm3, %xmm5
+; SSE-NEXT:    paddd %xmm2, %xmm5
 ; SSE-NEXT:    psrld $2, %xmm5
-; SSE-NEXT:    movdqa {{.*#+}} xmm3 = [7,7,7,7]
+; SSE-NEXT:    movdqa {{.*#+}} xmm2 = [7,7,7,7]
 ; SSE-NEXT:    pshufd {{.*#+}} xmm6 = xmm5[1,1,3,3]
-; SSE-NEXT:    pmuludq %xmm3, %xmm5
-; SSE-NEXT:    pmuludq %xmm3, %xmm6
-; SSE-NEXT:    shufps {{.*#+}} xmm5 = xmm5[0,2],xmm6[0,2]
-; SSE-NEXT:    shufps {{.*#+}} xmm5 = xmm5[0,2,1,3]
+; SSE-NEXT:    pmuludq %xmm2, %xmm5
+; SSE-NEXT:    pshufd {{.*#+}} xmm5 = xmm5[0,2,2,3]
+; SSE-NEXT:    pmuludq %xmm2, %xmm6
+; SSE-NEXT:    pshufd {{.*#+}} xmm6 = xmm6[0,2,2,3]
+; SSE-NEXT:    punpckldq {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1]
 ; SSE-NEXT:    psubd %xmm5, %xmm0
-; SSE-NEXT:    pmuludq %xmm1, %xmm2
+; SSE-NEXT:    pmuludq %xmm1, %xmm3
+; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[1,3,2,3]
 ; SSE-NEXT:    pshufd {{.*#+}} xmm5 = xmm1[1,1,3,3]
 ; SSE-NEXT:    pmuludq %xmm4, %xmm5
-; SSE-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,3],xmm5[1,3]
-; SSE-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm5[1,3,2,3]
+; SSE-NEXT:    punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
 ; SSE-NEXT:    movdqa %xmm1, %xmm4
-; SSE-NEXT:    psubd %xmm2, %xmm4
+; SSE-NEXT:    psubd %xmm3, %xmm4
 ; SSE-NEXT:    psrld $1, %xmm4
-; SSE-NEXT:    paddd %xmm2, %xmm4
+; SSE-NEXT:    paddd %xmm3, %xmm4
 ; SSE-NEXT:    psrld $2, %xmm4
-; SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]
-; SSE-NEXT:    pmuludq %xmm3, %xmm4
-; SSE-NEXT:    pmuludq %xmm3, %xmm2
-; SSE-NEXT:    shufps {{.*#+}} xmm4 = xmm4[0,2],xmm2[0,2]
-; SSE-NEXT:    shufps {{.*#+}} xmm4 = xmm4[0,2,1,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
+; SSE-NEXT:    pmuludq %xmm2, %xmm4
+; SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
+; SSE-NEXT:    pmuludq %xmm2, %xmm3
+; SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3]
+; SSE-NEXT:    punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
 ; SSE-NEXT:    psubd %xmm4, %xmm1
 ; SSE-NEXT:    retq
 ;
@@ -1068,36 +1081,36 @@ define <8 x i32> @test10(<8 x i32> %a) {
   ret <8 x i32> %rem
 }
 
-define <8 x i32> @test11(<8 x i32> %a) {
+define <8 x i32> @test11(<8 x i32> %a) #0 {
 ; SSE41-LABEL: test11:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    movdqa {{.*#+}} xmm2 = [2454267027,2454267027,2454267027,2454267027]
-; SSE41-NEXT:    movdqa %xmm0, %xmm3
-; SSE41-NEXT:    pmuldq %xmm2, %xmm3
-; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3]
-; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm0[1,1,3,3]
-; SSE41-NEXT:    pmuldq %xmm4, %xmm5
-; SSE41-NEXT:    shufps {{.*#+}} xmm3 = xmm3[1,3],xmm5[1,3]
-; SSE41-NEXT:    shufps {{.*#+}} xmm3 = xmm3[0,2,1,3]
-; SSE41-NEXT:    paddd %xmm0, %xmm3
-; SSE41-NEXT:    movdqa %xmm3, %xmm5
-; SSE41-NEXT:    psrld $31, %xmm5
-; SSE41-NEXT:    psrad $2, %xmm3
-; SSE41-NEXT:    paddd %xmm5, %xmm3
-; SSE41-NEXT:    movdqa {{.*#+}} xmm5 = [7,7,7,7]
-; SSE41-NEXT:    pmulld %xmm5, %xmm3
-; SSE41-NEXT:    psubd %xmm3, %xmm0
+; SSE41-NEXT:    pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; SSE41-NEXT:    pmuldq %xmm3, %xmm4
+; SSE41-NEXT:    movdqa %xmm0, %xmm5
+; SSE41-NEXT:    pmuldq %xmm2, %xmm5
+; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm5 = xmm5[0,1],xmm4[2,3],xmm5[4,5],xmm4[6,7]
+; SSE41-NEXT:    paddd %xmm0, %xmm5
+; SSE41-NEXT:    movdqa %xmm5, %xmm4
+; SSE41-NEXT:    psrld $31, %xmm4
+; SSE41-NEXT:    psrad $2, %xmm5
+; SSE41-NEXT:    paddd %xmm4, %xmm5
+; SSE41-NEXT:    movdqa {{.*#+}} xmm4 = [7,7,7,7]
+; SSE41-NEXT:    pmulld %xmm4, %xmm5
+; SSE41-NEXT:    psubd %xmm5, %xmm0
+; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm1[1,1,3,3]
+; SSE41-NEXT:    pmuldq %xmm3, %xmm5
 ; SSE41-NEXT:    pmuldq %xmm1, %xmm2
-; SSE41-NEXT:    pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
-; SSE41-NEXT:    pmuldq %xmm4, %xmm3
-; SSE41-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,3],xmm3[1,3]
-; SSE41-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm5[2,3],xmm2[4,5],xmm5[6,7]
 ; SSE41-NEXT:    paddd %xmm1, %xmm2
 ; SSE41-NEXT:    movdqa %xmm2, %xmm3
 ; SSE41-NEXT:    psrld $31, %xmm3
 ; SSE41-NEXT:    psrad $2, %xmm2
 ; SSE41-NEXT:    paddd %xmm3, %xmm2
-; SSE41-NEXT:    pmulld %xmm5, %xmm2
+; SSE41-NEXT:    pmulld %xmm4, %xmm2
 ; SSE41-NEXT:    psubd %xmm2, %xmm1
 ; SSE41-NEXT:    retq
 ;
@@ -1112,13 +1125,14 @@ define <8 x i32> @test11(<8 x i32> %a) {
 ; SSE-NEXT:    psrad $31, %xmm6
 ; SSE-NEXT:    pand %xmm2, %xmm6
 ; SSE-NEXT:    paddd %xmm4, %xmm6
-; SSE-NEXT:    movdqa %xmm0, %xmm7
-; SSE-NEXT:    pmuludq %xmm2, %xmm7
+; SSE-NEXT:    movdqa %xmm0, %xmm4
+; SSE-NEXT:    pmuludq %xmm2, %xmm4
+; SSE-NEXT:    pshufd {{.*#+}} xmm7 = xmm4[1,3,2,3]
 ; SSE-NEXT:    pshufd {{.*#+}} xmm5 = xmm2[1,1,3,3]
 ; SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
 ; SSE-NEXT:    pmuludq %xmm5, %xmm4
-; SSE-NEXT:    shufps {{.*#+}} xmm7 = xmm7[1,3],xmm4[1,3]
-; SSE-NEXT:    shufps {{.*#+}} xmm7 = xmm7[0,2,1,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm4[1,3,2,3]
+; SSE-NEXT:    punpckldq {{.*#+}} xmm7 = xmm7[0],xmm4[0],xmm7[1],xmm4[1]
 ; SSE-NEXT:    psubd %xmm6, %xmm7
 ; SSE-NEXT:    paddd %xmm0, %xmm7
 ; SSE-NEXT:    movdqa %xmm7, %xmm4
@@ -1128,9 +1142,10 @@ define <8 x i32> @test11(<8 x i32> %a) {
 ; SSE-NEXT:    movdqa {{.*#+}} xmm4 = [7,7,7,7]
 ; SSE-NEXT:    pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
 ; SSE-NEXT:    pmuludq %xmm4, %xmm7
+; SSE-NEXT:    pshufd {{.*#+}} xmm7 = xmm7[0,2,2,3]
 ; SSE-NEXT:    pmuludq %xmm4, %xmm6
-; SSE-NEXT:    shufps {{.*#+}} xmm7 = xmm7[0,2],xmm6[0,2]
-; SSE-NEXT:    shufps {{.*#+}} xmm7 = xmm7[0,2,1,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm6 = xmm6[0,2,2,3]
+; SSE-NEXT:    punpckldq {{.*#+}} xmm7 = xmm7[0],xmm6[0],xmm7[1],xmm6[1]
 ; SSE-NEXT:    psubd %xmm7, %xmm0
 ; SSE-NEXT:    pand %xmm1, %xmm3
 ; SSE-NEXT:    movdqa %xmm1, %xmm6
@@ -1138,10 +1153,11 @@ define <8 x i32> @test11(<8 x i32> %a) {
 ; SSE-NEXT:    pand %xmm2, %xmm6
 ; SSE-NEXT:    paddd %xmm3, %xmm6
 ; SSE-NEXT:    pmuludq %xmm1, %xmm2
+; SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
 ; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
 ; SSE-NEXT:    pmuludq %xmm5, %xmm3
-; SSE-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,3],xmm3[1,3]
-; SSE-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[1,3,2,3]
+; SSE-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
 ; SSE-NEXT:    psubd %xmm6, %xmm2
 ; SSE-NEXT:    paddd %xmm1, %xmm2
 ; SSE-NEXT:    movdqa %xmm2, %xmm3
@@ -1150,9 +1166,10 @@ define <8 x i32> @test11(<8 x i32> %a) {
 ; SSE-NEXT:    paddd %xmm3, %xmm2
 ; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
 ; SSE-NEXT:    pmuludq %xmm4, %xmm2
+; SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
 ; SSE-NEXT:    pmuludq %xmm4, %xmm3
-; SSE-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2],xmm3[0,2]
-; SSE-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
+; SSE-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
 ; SSE-NEXT:    psubd %xmm2, %xmm1
 ; SSE-NEXT:    retq
 ;
@@ -1177,7 +1194,7 @@ define <8 x i32> @test11(<8 x i32> %a) {
   ret <8 x i32> %rem
 }
 
-define <2 x i16> @test12() {
+define <2 x i16> @test12() #0 {
 ; SSE41-LABEL: test12:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    xorps %xmm0, %xmm0
@@ -1198,20 +1215,19 @@ define <2 x i16> @test12() {
   ret <2 x i16> %B9
 }
 
-define <4 x i32> @PR20355(<4 x i32> %a) {
+define <4 x i32> @PR20355(<4 x i32> %a) #0 {
 ; SSE41-LABEL: PR20355:
 ; SSE41:       # BB#0: # %entry
 ; SSE41-NEXT:    movdqa {{.*#+}} xmm1 = [1431655766,1431655766,1431655766,1431655766]
-; SSE41-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
+; SSE41-NEXT:    pmuldq %xmm2, %xmm3
 ; SSE41-NEXT:    pmuldq %xmm1, %xmm0
-; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; SSE41-NEXT:    pmuldq %xmm2, %xmm1
-; SSE41-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
-; SSE41-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
-; SSE41-NEXT:    movaps %xmm0, %xmm1
-; SSE41-NEXT:    psrld $31, %xmm1
-; SSE41-NEXT:    paddd %xmm0, %xmm1
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
 ; SSE41-NEXT:    movdqa %xmm1, %xmm0
+; SSE41-NEXT:    psrld $31, %xmm0
+; SSE41-NEXT:    paddd %xmm1, %xmm0
 ; SSE41-NEXT:    retq
 ;
 ; SSE-LABEL: PR20355:
@@ -1226,26 +1242,26 @@ define <4 x i32> @PR20355(<4 x i32> %a) {
 ; SSE-NEXT:    paddd %xmm2, %xmm3
 ; SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
 ; SSE-NEXT:    pmuludq %xmm1, %xmm0
-; SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; SSE-NEXT:    pmuludq %xmm2, %xmm1
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
-; SSE-NEXT:    psubd %xmm3, %xmm0
-; SSE-NEXT:    movdqa %xmm0, %xmm1
-; SSE-NEXT:    psrld $31, %xmm1
-; SSE-NEXT:    paddd %xmm0, %xmm1
-; SSE-NEXT:    movdqa %xmm1, %xmm0
+; SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm0[1,3,2,3]
+; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
+; SSE-NEXT:    pmuludq %xmm2, %xmm0
+; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
+; SSE-NEXT:    punpckldq {{.*#+}} xmm4 = xmm4[0],xmm0[0],xmm4[1],xmm0[1]
+; SSE-NEXT:    psubd %xmm3, %xmm4
+; SSE-NEXT:    movdqa %xmm4, %xmm0
+; SSE-NEXT:    psrld $31, %xmm0
+; SSE-NEXT:    paddd %xmm4, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: PR20355:
 ; AVX:       # BB#0: # %entry
 ; AVX-NEXT:    vpbroadcastd {{.*}}(%rip), %xmm1
-; AVX-NEXT:    vpmuldq %xmm1, %xmm0, %xmm2
-; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; AVX-NEXT:    vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
+; AVX-NEXT:    vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
+; AVX-NEXT:    vpmuldq %xmm2, %xmm3, %xmm2
 ; AVX-NEXT:    vpmuldq %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm2[1,3],xmm0[1,3]
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; AVX-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
 ; AVX-NEXT:    vpsrld $31, %xmm0, %xmm1
 ; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
@@ -1253,3 +1269,5 @@ entry:
   %sdiv = sdiv <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3>
   ret <4 x i32> %sdiv
 }
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/X86/vector-intrinsics.ll b/test/CodeGen/X86/vector-intrinsics.ll
index cabacb572cea..c140468d3006 100644
--- a/test/CodeGen/X86/vector-intrinsics.ll
+++ b/test/CodeGen/X86/vector-intrinsics.ll
@@ -32,20 +32,20 @@ declare <9 x double> @llvm.pow.v9f64(<9 x double> %a, <9 x double> %b)
 declare <9 x double> @llvm.powi.v9f64(<9 x double> %a, i32)
 
 define void @a(<9 x double>* %p) nounwind {
-  %a = load <9 x double>* %p
+  %a = load <9 x double>, <9 x double>* %p
   %r = call <9 x double> @llvm.exp.v9f64(<9 x double> %a)
   store <9 x double> %r, <9 x double>* %p
   ret void
 }
 define void @b(<9 x double>* %p, <9 x double>* %q) nounwind {
-  %a = load <9 x double>* %p
-  %b = load <9 x double>* %q
+  %a = load <9 x double>, <9 x double>* %p
+  %b = load <9 x double>, <9 x double>* %q
   %r = call <9 x double> @llvm.pow.v9f64(<9 x double> %a, <9 x double> %b)
   store <9 x double> %r, <9 x double>* %p
   ret void
 }
 define void @c(<9 x double>* %p, i32 %n) nounwind {
-  %a = load <9 x double>* %p
+  %a = load <9 x double>, <9 x double>* %p
   %r = call <9 x double> @llvm.powi.v9f64(<9 x double> %a, i32 %n)
   store <9 x double> %r, <9 x double>* %p
   ret void
diff --git a/test/CodeGen/X86/vector-sext.ll b/test/CodeGen/X86/vector-sext.ll
index 758833155a96..e6acc7efaf39 100644
--- a/test/CodeGen/X86/vector-sext.ll
+++ b/test/CodeGen/X86/vector-sext.ll
@@ -10,37 +10,30 @@
 define <8 x i32> @sext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
 ; SSE2-LABEL: sext_8i16_to_8i32:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movdqa %xmm0, %xmm1
-; SSE2-NEXT:   # kill: XMM0<def> XMM1<kill>
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
-; SSE2-NEXT:    pslld $16, %xmm0
-; SSE2-NEXT:    psrad $16, %xmm0
-; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
-; SSE2-NEXT:    pslld $16, %xmm1
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
+; SSE2-NEXT:    psrad $16, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
 ; SSE2-NEXT:    psrad $16, %xmm1
+; SSE2-NEXT:    movdqa %xmm2, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: sext_8i16_to_8i32:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movdqa %xmm0, %xmm1
-; SSSE3-NEXT:   # kill: XMM0<def> XMM1<kill>
-; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
-; SSSE3-NEXT:    pslld $16, %xmm0
-; SSSE3-NEXT:    psrad $16, %xmm0
-; SSSE3-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
-; SSSE3-NEXT:    pslld $16, %xmm1
+; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
+; SSSE3-NEXT:    psrad $16, %xmm2
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
 ; SSSE3-NEXT:    psrad $16, %xmm1
+; SSSE3-NEXT:    movdqa %xmm2, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: sext_8i16_to_8i32:
 ; SSE41:       # BB#0: # %entry
-; SSE41-NEXT:    movdqa %xmm0, %xmm1
-; SSE41-NEXT:    pmovzxwd %xmm1, %xmm0
-; SSE41-NEXT:    pslld $16, %xmm0
-; SSE41-NEXT:    psrad $16, %xmm0
-; SSE41-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
-; SSE41-NEXT:    pslld $16, %xmm1
-; SSE41-NEXT:    psrad $16, %xmm1
+; SSE41-NEXT:    pmovsxwd %xmm0, %xmm2
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; SSE41-NEXT:    pmovsxwd %xmm0, %xmm1
+; SSE41-NEXT:    movdqa %xmm2, %xmm0
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: sext_8i16_to_8i32:
@@ -58,13 +51,10 @@ define <8 x i32> @sext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp
 ;
 ; X32-SSE41-LABEL: sext_8i16_to_8i32:
 ; X32-SSE41:       # BB#0: # %entry
-; X32-SSE41-NEXT:    movdqa %xmm0, %xmm1
-; X32-SSE41-NEXT:    pmovzxwd %xmm1, %xmm0
-; X32-SSE41-NEXT:    pslld $16, %xmm0
-; X32-SSE41-NEXT:    psrad $16, %xmm0
-; X32-SSE41-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
-; X32-SSE41-NEXT:    pslld $16, %xmm1
-; X32-SSE41-NEXT:    psrad $16, %xmm1
+; X32-SSE41-NEXT:    pmovsxwd %xmm0, %xmm2
+; X32-SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; X32-SSE41-NEXT:    pmovsxwd %xmm0, %xmm1
+; X32-SSE41-NEXT:    movdqa %xmm2, %xmm0
 ; X32-SSE41-NEXT:    retl
 entry:
   %B = sext <8 x i16> %A to <8 x i32>
@@ -74,68 +64,31 @@ entry:
 define <4 x i64> @sext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
 ; SSE2-LABEL: sext_4i32_to_4i64:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
-; SSE2-NEXT:    movd %xmm1, %rax
-; SSE2-NEXT:    cltq
-; SSE2-NEXT:    movd %rax, %xmm2
-; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; SSE2-NEXT:    movd %xmm1, %rax
-; SSE2-NEXT:    cltq
-; SSE2-NEXT:    movd %rax, %xmm1
-; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
-; SSE2-NEXT:    movd %xmm0, %rax
-; SSE2-NEXT:    cltq
-; SSE2-NEXT:    movd %rax, %xmm1
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
-; SSE2-NEXT:    movd %xmm0, %rax
-; SSE2-NEXT:    cltq
-; SSE2-NEXT:    movd %rax, %xmm0
-; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    movdqa %xmm0, %xmm2
+; SSE2-NEXT:    psrad $31, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-NEXT:    movdqa %xmm1, %xmm2
+; SSE2-NEXT:    psrad $31, %xmm2
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: sext_4i32_to_4i64:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
-; SSSE3-NEXT:    movd %xmm1, %rax
-; SSSE3-NEXT:    cltq
-; SSSE3-NEXT:    movd %rax, %xmm2
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; SSSE3-NEXT:    movd %xmm1, %rax
-; SSSE3-NEXT:    cltq
-; SSSE3-NEXT:    movd %rax, %xmm1
-; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
-; SSSE3-NEXT:    movd %xmm0, %rax
-; SSSE3-NEXT:    cltq
-; SSSE3-NEXT:    movd %rax, %xmm1
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
-; SSSE3-NEXT:    movd %xmm0, %rax
-; SSSE3-NEXT:    cltq
-; SSSE3-NEXT:    movd %rax, %xmm0
-; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; SSSE3-NEXT:    movdqa %xmm2, %xmm0
+; SSSE3-NEXT:    movdqa %xmm0, %xmm2
+; SSSE3-NEXT:    psrad $31, %xmm2
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSSE3-NEXT:    movdqa %xmm1, %xmm2
+; SSSE3-NEXT:    psrad $31, %xmm2
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: sext_4i32_to_4i64:
 ; SSE41:       # BB#0: # %entry
-; SSE41-NEXT:    pmovzxdq %xmm0, %xmm1
-; SSE41-NEXT:    pextrq $1, %xmm1, %rax
-; SSE41-NEXT:    cltq
-; SSE41-NEXT:    movd %rax, %xmm3
-; SSE41-NEXT:    movd %xmm1, %rax
-; SSE41-NEXT:    cltq
-; SSE41-NEXT:    movd %rax, %xmm2
-; SSE41-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
-; SSE41-NEXT:    pextrq $1, %xmm0, %rax
-; SSE41-NEXT:    cltq
-; SSE41-NEXT:    movd %rax, %xmm3
-; SSE41-NEXT:    movd %xmm0, %rax
-; SSE41-NEXT:    cltq
-; SSE41-NEXT:    movd %rax, %xmm1
-; SSE41-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
+; SSE41-NEXT:    pmovsxdq %xmm0, %xmm2
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; SSE41-NEXT:    pmovsxdq %xmm0, %xmm1
 ; SSE41-NEXT:    movdqa %xmm2, %xmm0
 ; SSE41-NEXT:    retq
 ;
@@ -154,20 +107,9 @@ define <4 x i64> @sext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp
 ;
 ; X32-SSE41-LABEL: sext_4i32_to_4i64:
 ; X32-SSE41:       # BB#0: # %entry
-; X32-SSE41-NEXT:    pmovzxdq %xmm0, %xmm2
-; X32-SSE41-NEXT:    movd %xmm2, %eax
-; X32-SSE41-NEXT:    sarl $31, %eax
-; X32-SSE41-NEXT:    pextrd $2, %xmm2, %ecx
-; X32-SSE41-NEXT:    pinsrd $1, %eax, %xmm2
-; X32-SSE41-NEXT:    sarl $31, %ecx
-; X32-SSE41-NEXT:    pinsrd $3, %ecx, %xmm2
-; X32-SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
-; X32-SSE41-NEXT:    movd %xmm1, %eax
-; X32-SSE41-NEXT:    sarl $31, %eax
-; X32-SSE41-NEXT:    pextrd $2, %xmm1, %ecx
-; X32-SSE41-NEXT:    pinsrd $1, %eax, %xmm1
-; X32-SSE41-NEXT:    sarl $31, %ecx
-; X32-SSE41-NEXT:    pinsrd $3, %ecx, %xmm1
+; X32-SSE41-NEXT:    pmovsxdq %xmm0, %xmm2
+; X32-SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; X32-SSE41-NEXT:    pmovsxdq %xmm0, %xmm1
 ; X32-SSE41-NEXT:    movdqa %xmm2, %xmm0
 ; X32-SSE41-NEXT:    retl
 entry:
@@ -206,7 +148,7 @@ define <4 x i32> @load_sext_test1(<4 x i16> *%ptr) {
 ; X32-SSE41-NEXT:    pmovsxwd (%eax), %xmm0
 ; X32-SSE41-NEXT:    retl
 entry:
- %X = load <4 x i16>* %ptr
+ %X = load <4 x i16>, <4 x i16>* %ptr
  %Y = sext <4 x i16> %X to <4 x i32>
  ret <4 x i32>%Y
 }
@@ -244,7 +186,7 @@ define <4 x i32> @load_sext_test2(<4 x i8> *%ptr) {
 ; X32-SSE41-NEXT:    pmovsxbd (%eax), %xmm0
 ; X32-SSE41-NEXT:    retl
 entry:
- %X = load <4 x i8>* %ptr
+ %X = load <4 x i8>, <4 x i8>* %ptr
  %Y = sext <4 x i8> %X to <4 x i32>
  ret <4 x i32>%Y
 }
@@ -252,20 +194,26 @@ entry:
 define <2 x i64> @load_sext_test3(<2 x i8> *%ptr) {
 ; SSE2-LABEL: load_sext_test3:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movsbq 1(%rdi), %rax
-; SSE2-NEXT:    movd %rax, %xmm1
-; SSE2-NEXT:    movsbq (%rdi), %rax
-; SSE2-NEXT:    movd %rax, %xmm0
-; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    movzwl (%rdi), %eax
+; SSE2-NEXT:    movd %eax, %xmm0
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
+; SSE2-NEXT:    movdqa %xmm0, %xmm1
+; SSE2-NEXT:    psrad $31, %xmm1
+; SSE2-NEXT:    psrad $24, %xmm0
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: load_sext_test3:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movsbq 1(%rdi), %rax
-; SSSE3-NEXT:    movd %rax, %xmm1
-; SSSE3-NEXT:    movsbq (%rdi), %rax
-; SSSE3-NEXT:    movd %rax, %xmm0
-; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSSE3-NEXT:    movzwl (%rdi), %eax
+; SSSE3-NEXT:    movd %eax, %xmm0
+; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
+; SSSE3-NEXT:    movdqa %xmm0, %xmm1
+; SSSE3-NEXT:    psrad $31, %xmm1
+; SSSE3-NEXT:    psrad $24, %xmm0
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: load_sext_test3:
@@ -284,7 +232,7 @@ define <2 x i64> @load_sext_test3(<2 x i8> *%ptr) {
 ; X32-SSE41-NEXT:    pmovsxbq (%eax), %xmm0
 ; X32-SSE41-NEXT:    retl
 entry:
- %X = load <2 x i8>* %ptr
+ %X = load <2 x i8>, <2 x i8>* %ptr
  %Y = sext <2 x i8> %X to <2 x i64>
  ret <2 x i64>%Y
 }
@@ -292,20 +240,22 @@ entry:
 define <2 x i64> @load_sext_test4(<2 x i16> *%ptr) {
 ; SSE2-LABEL: load_sext_test4:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movswq 2(%rdi), %rax
-; SSE2-NEXT:    movd %rax, %xmm1
-; SSE2-NEXT:    movswq (%rdi), %rax
-; SSE2-NEXT:    movd %rax, %xmm0
-; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    movd (%rdi), %xmm0
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
+; SSE2-NEXT:    movdqa %xmm0, %xmm1
+; SSE2-NEXT:    psrad $31, %xmm1
+; SSE2-NEXT:    psrad $16, %xmm0
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: load_sext_test4:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movswq 2(%rdi), %rax
-; SSSE3-NEXT:    movd %rax, %xmm1
-; SSSE3-NEXT:    movswq (%rdi), %rax
-; SSSE3-NEXT:    movd %rax, %xmm0
-; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSSE3-NEXT:    movd (%rdi), %xmm0
+; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
+; SSSE3-NEXT:    movdqa %xmm0, %xmm1
+; SSSE3-NEXT:    psrad $31, %xmm1
+; SSSE3-NEXT:    psrad $16, %xmm0
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: load_sext_test4:
@@ -324,7 +274,7 @@ define <2 x i64> @load_sext_test4(<2 x i16> *%ptr) {
 ; X32-SSE41-NEXT:    pmovsxwq (%eax), %xmm0
 ; X32-SSE41-NEXT:    retl
 entry:
- %X = load <2 x i16>* %ptr
+ %X = load <2 x i16>, <2 x i16>* %ptr
  %Y = sext <2 x i16> %X to <2 x i64>
  ret <2 x i64>%Y
 }
@@ -332,20 +282,18 @@ entry:
 define <2 x i64> @load_sext_test5(<2 x i32> *%ptr) {
 ; SSE2-LABEL: load_sext_test5:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movslq 4(%rdi), %rax
-; SSE2-NEXT:    movd %rax, %xmm1
-; SSE2-NEXT:    movslq (%rdi), %rax
-; SSE2-NEXT:    movd %rax, %xmm0
-; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    movq (%rdi), %xmm0
+; SSE2-NEXT:    movdqa %xmm0, %xmm1
+; SSE2-NEXT:    psrad $31, %xmm1
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: load_sext_test5:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movslq 4(%rdi), %rax
-; SSSE3-NEXT:    movd %rax, %xmm1
-; SSSE3-NEXT:    movslq (%rdi), %rax
-; SSSE3-NEXT:    movd %rax, %xmm0
-; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSSE3-NEXT:    movq (%rdi), %xmm0
+; SSSE3-NEXT:    movdqa %xmm0, %xmm1
+; SSSE3-NEXT:    psrad $31, %xmm1
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: load_sext_test5:
@@ -364,7 +312,7 @@ define <2 x i64> @load_sext_test5(<2 x i32> *%ptr) {
 ; X32-SSE41-NEXT:    pmovsxdq (%eax), %xmm0
 ; X32-SSE41-NEXT:    retl
 entry:
- %X = load <2 x i32>* %ptr
+ %X = load <2 x i32>, <2 x i32>* %ptr
  %Y = sext <2 x i32> %X to <2 x i64>
  ret <2 x i64>%Y
 }
@@ -400,7 +348,7 @@ define <8 x i16> @load_sext_test6(<8 x i8> *%ptr) {
 ; X32-SSE41-NEXT:    pmovsxbw (%eax), %xmm0
 ; X32-SSE41-NEXT:    retl
 entry:
- %X = load <8 x i8>* %ptr
+ %X = load <8 x i8>, <8 x i8>* %ptr
  %Y = sext <8 x i8> %X to <8 x i16>
  ret <8 x i16>%Y
 }
@@ -410,72 +358,35 @@ define <4 x i64> @sext_4i1_to_4i64(<4 x i1> %mask) {
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    pslld $31, %xmm0
 ; SSE2-NEXT:    psrad $31, %xmm0
-; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
-; SSE2-NEXT:    movd %xmm1, %rax
-; SSE2-NEXT:    cltq
-; SSE2-NEXT:    movd %rax, %xmm2
-; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; SSE2-NEXT:    movd %xmm1, %rax
-; SSE2-NEXT:    cltq
-; SSE2-NEXT:    movd %rax, %xmm1
-; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
-; SSE2-NEXT:    movd %xmm0, %rax
-; SSE2-NEXT:    cltq
-; SSE2-NEXT:    movd %rax, %xmm1
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
-; SSE2-NEXT:    movd %xmm0, %rax
-; SSE2-NEXT:    cltq
-; SSE2-NEXT:    movd %rax, %xmm0
-; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    movdqa %xmm0, %xmm2
+; SSE2-NEXT:    psrad $31, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-NEXT:    movdqa %xmm1, %xmm2
+; SSE2-NEXT:    psrad $31, %xmm2
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: sext_4i1_to_4i64:
 ; SSSE3:       # BB#0:
 ; SSSE3-NEXT:    pslld $31, %xmm0
 ; SSSE3-NEXT:    psrad $31, %xmm0
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
-; SSSE3-NEXT:    movd %xmm1, %rax
-; SSSE3-NEXT:    cltq
-; SSSE3-NEXT:    movd %rax, %xmm2
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; SSSE3-NEXT:    movd %xmm1, %rax
-; SSSE3-NEXT:    cltq
-; SSSE3-NEXT:    movd %rax, %xmm1
-; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
-; SSSE3-NEXT:    movd %xmm0, %rax
-; SSSE3-NEXT:    cltq
-; SSSE3-NEXT:    movd %rax, %xmm1
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
-; SSSE3-NEXT:    movd %xmm0, %rax
-; SSSE3-NEXT:    cltq
-; SSSE3-NEXT:    movd %rax, %xmm0
-; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; SSSE3-NEXT:    movdqa %xmm2, %xmm0
+; SSSE3-NEXT:    movdqa %xmm0, %xmm2
+; SSSE3-NEXT:    psrad $31, %xmm2
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSSE3-NEXT:    movdqa %xmm1, %xmm2
+; SSSE3-NEXT:    psrad $31, %xmm2
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: sext_4i1_to_4i64:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    pslld $31, %xmm0
 ; SSE41-NEXT:    psrad $31, %xmm0
-; SSE41-NEXT:    pmovzxdq %xmm0, %xmm1
-; SSE41-NEXT:    pextrq $1, %xmm1, %rax
-; SSE41-NEXT:    cltq
-; SSE41-NEXT:    movd %rax, %xmm3
-; SSE41-NEXT:    movd %xmm1, %rax
-; SSE41-NEXT:    cltq
-; SSE41-NEXT:    movd %rax, %xmm2
-; SSE41-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
-; SSE41-NEXT:    pextrq $1, %xmm0, %rax
-; SSE41-NEXT:    cltq
-; SSE41-NEXT:    movd %rax, %xmm3
-; SSE41-NEXT:    movd %xmm0, %rax
-; SSE41-NEXT:    cltq
-; SSE41-NEXT:    movd %rax, %xmm1
-; SSE41-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
+; SSE41-NEXT:    pmovsxdq %xmm0, %xmm2
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; SSE41-NEXT:    pmovsxdq %xmm0, %xmm1
 ; SSE41-NEXT:    movdqa %xmm2, %xmm0
 ; SSE41-NEXT:    retq
 ;
@@ -500,20 +411,9 @@ define <4 x i64> @sext_4i1_to_4i64(<4 x i1> %mask) {
 ; X32-SSE41:       # BB#0:
 ; X32-SSE41-NEXT:    pslld $31, %xmm0
 ; X32-SSE41-NEXT:    psrad $31, %xmm0
-; X32-SSE41-NEXT:    pmovzxdq %xmm0, %xmm2
-; X32-SSE41-NEXT:    movd %xmm2, %eax
-; X32-SSE41-NEXT:    sarl $31, %eax
-; X32-SSE41-NEXT:    pextrd $2, %xmm2, %ecx
-; X32-SSE41-NEXT:    pinsrd $1, %eax, %xmm2
-; X32-SSE41-NEXT:    sarl $31, %ecx
-; X32-SSE41-NEXT:    pinsrd $3, %ecx, %xmm2
-; X32-SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
-; X32-SSE41-NEXT:    movd %xmm1, %eax
-; X32-SSE41-NEXT:    sarl $31, %eax
-; X32-SSE41-NEXT:    pextrd $2, %xmm1, %ecx
-; X32-SSE41-NEXT:    pinsrd $1, %eax, %xmm1
-; X32-SSE41-NEXT:    sarl $31, %ecx
-; X32-SSE41-NEXT:    pinsrd $3, %ecx, %xmm1
+; X32-SSE41-NEXT:    pmovsxdq %xmm0, %xmm2
+; X32-SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; X32-SSE41-NEXT:    pmovsxdq %xmm0, %xmm1
 ; X32-SSE41-NEXT:    movdqa %xmm2, %xmm0
 ; X32-SSE41-NEXT:    retl
   %extmask = sext <4 x i1> %mask to <4 x i64>
@@ -523,46 +423,35 @@ define <4 x i64> @sext_4i1_to_4i64(<4 x i1> %mask) {
 define <16 x i16> @sext_16i8_to_16i16(<16 x i8> *%ptr) {
 ; SSE2-LABEL: sext_16i8_to_16i16:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movdqa (%rdi), %xmm1
-; SSE2-NEXT:    movdqa %xmm1, %xmm0
+; SSE2-NEXT:    movq (%rdi), %xmm0
 ; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; SSE2-NEXT:    psllw $8, %xmm0
 ; SSE2-NEXT:    psraw $8, %xmm0
-; SSE2-NEXT:    punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; SSE2-NEXT:    psllw $8, %xmm1
+; SSE2-NEXT:    movq 8(%rdi), %xmm1
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
 ; SSE2-NEXT:    psraw $8, %xmm1
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: sext_16i8_to_16i16:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movdqa (%rdi), %xmm1
-; SSSE3-NEXT:    movdqa %xmm1, %xmm0
+; SSSE3-NEXT:    movq (%rdi), %xmm0
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; SSSE3-NEXT:    psllw $8, %xmm0
 ; SSSE3-NEXT:    psraw $8, %xmm0
-; SSSE3-NEXT:    punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; SSSE3-NEXT:    psllw $8, %xmm1
+; SSSE3-NEXT:    movq 8(%rdi), %xmm1
+; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
 ; SSSE3-NEXT:    psraw $8, %xmm1
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: sext_16i8_to_16i16:
 ; SSE41:       # BB#0: # %entry
-; SSE41-NEXT:    movdqa (%rdi), %xmm1
-; SSE41-NEXT:    pmovzxbw %xmm1, %xmm0
-; SSE41-NEXT:    psllw $8, %xmm0
-; SSE41-NEXT:    psraw $8, %xmm0
-; SSE41-NEXT:    punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; SSE41-NEXT:    psllw $8, %xmm1
-; SSE41-NEXT:    psraw $8, %xmm1
+; SSE41-NEXT:    pmovsxbw (%rdi), %xmm0
+; SSE41-NEXT:    pmovsxbw 8(%rdi), %xmm1
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: sext_16i8_to_16i16:
 ; AVX1:       # BB#0: # %entry
-; AVX1-NEXT:    vmovdqa (%rdi), %xmm0
-; AVX1-NEXT:    vpmovsxbw %xmm0, %xmm1
-; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
-; AVX1-NEXT:    vpmovsxbw %xmm0, %xmm0
-; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    vpmovsxbw (%rdi), %xmm0
+; AVX1-NEXT:    vpmovsxbw 8(%rdi), %xmm1
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: sext_16i8_to_16i16:
@@ -573,16 +462,11 @@ define <16 x i16> @sext_16i8_to_16i16(<16 x i8> *%ptr) {
 ; X32-SSE41-LABEL: sext_16i8_to_16i16:
 ; X32-SSE41:       # BB#0: # %entry
 ; X32-SSE41-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-SSE41-NEXT:    movdqa (%eax), %xmm1
-; X32-SSE41-NEXT:    pmovzxbw %xmm1, %xmm0
-; X32-SSE41-NEXT:    psllw $8, %xmm0
-; X32-SSE41-NEXT:    psraw $8, %xmm0
-; X32-SSE41-NEXT:    punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; X32-SSE41-NEXT:    psllw $8, %xmm1
-; X32-SSE41-NEXT:    psraw $8, %xmm1
+; X32-SSE41-NEXT:    pmovsxbw (%eax), %xmm0
+; X32-SSE41-NEXT:    pmovsxbw 8(%eax), %xmm1
 ; X32-SSE41-NEXT:    retl
 entry:
- %X = load <16 x i8>* %ptr
+ %X = load <16 x i8>, <16 x i8>* %ptr
  %Y = sext <16 x i8> %X to <16 x i16>
  ret <16 x i16> %Y
 }
@@ -592,72 +476,35 @@ define <4 x i64> @sext_4i8_to_4i64(<4 x i8> %mask) {
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    pslld $24, %xmm0
 ; SSE2-NEXT:    psrad $24, %xmm0
-; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
-; SSE2-NEXT:    movd %xmm1, %rax
-; SSE2-NEXT:    cltq
-; SSE2-NEXT:    movd %rax, %xmm2
-; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; SSE2-NEXT:    movd %xmm1, %rax
-; SSE2-NEXT:    cltq
-; SSE2-NEXT:    movd %rax, %xmm1
-; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
-; SSE2-NEXT:    movd %xmm0, %rax
-; SSE2-NEXT:    cltq
-; SSE2-NEXT:    movd %rax, %xmm1
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
-; SSE2-NEXT:    movd %xmm0, %rax
-; SSE2-NEXT:    cltq
-; SSE2-NEXT:    movd %rax, %xmm0
-; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    movdqa %xmm0, %xmm2
+; SSE2-NEXT:    psrad $31, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-NEXT:    movdqa %xmm1, %xmm2
+; SSE2-NEXT:    psrad $31, %xmm2
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: sext_4i8_to_4i64:
 ; SSSE3:       # BB#0:
 ; SSSE3-NEXT:    pslld $24, %xmm0
 ; SSSE3-NEXT:    psrad $24, %xmm0
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
-; SSSE3-NEXT:    movd %xmm1, %rax
-; SSSE3-NEXT:    cltq
-; SSSE3-NEXT:    movd %rax, %xmm2
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; SSSE3-NEXT:    movd %xmm1, %rax
-; SSSE3-NEXT:    cltq
-; SSSE3-NEXT:    movd %rax, %xmm1
-; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
-; SSSE3-NEXT:    movd %xmm0, %rax
-; SSSE3-NEXT:    cltq
-; SSSE3-NEXT:    movd %rax, %xmm1
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
-; SSSE3-NEXT:    movd %xmm0, %rax
-; SSSE3-NEXT:    cltq
-; SSSE3-NEXT:    movd %rax, %xmm0
-; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; SSSE3-NEXT:    movdqa %xmm2, %xmm0
+; SSSE3-NEXT:    movdqa %xmm0, %xmm2
+; SSSE3-NEXT:    psrad $31, %xmm2
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSSE3-NEXT:    movdqa %xmm1, %xmm2
+; SSSE3-NEXT:    psrad $31, %xmm2
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: sext_4i8_to_4i64:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    pslld $24, %xmm0
 ; SSE41-NEXT:    psrad $24, %xmm0
-; SSE41-NEXT:    pmovzxdq %xmm0, %xmm1
-; SSE41-NEXT:    pextrq $1, %xmm1, %rax
-; SSE41-NEXT:    cltq
-; SSE41-NEXT:    movd %rax, %xmm3
-; SSE41-NEXT:    movd %xmm1, %rax
-; SSE41-NEXT:    cltq
-; SSE41-NEXT:    movd %rax, %xmm2
-; SSE41-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
-; SSE41-NEXT:    pextrq $1, %xmm0, %rax
-; SSE41-NEXT:    cltq
-; SSE41-NEXT:    movd %rax, %xmm3
-; SSE41-NEXT:    movd %xmm0, %rax
-; SSE41-NEXT:    cltq
-; SSE41-NEXT:    movd %rax, %xmm1
-; SSE41-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
+; SSE41-NEXT:    pmovsxdq %xmm0, %xmm2
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; SSE41-NEXT:    pmovsxdq %xmm0, %xmm1
 ; SSE41-NEXT:    movdqa %xmm2, %xmm0
 ; SSE41-NEXT:    retq
 ;
@@ -682,20 +529,9 @@ define <4 x i64> @sext_4i8_to_4i64(<4 x i8> %mask) {
 ; X32-SSE41:       # BB#0:
 ; X32-SSE41-NEXT:    pslld $24, %xmm0
 ; X32-SSE41-NEXT:    psrad $24, %xmm0
-; X32-SSE41-NEXT:    pmovzxdq %xmm0, %xmm2
-; X32-SSE41-NEXT:    movd %xmm2, %eax
-; X32-SSE41-NEXT:    sarl $31, %eax
-; X32-SSE41-NEXT:    pextrd $2, %xmm2, %ecx
-; X32-SSE41-NEXT:    pinsrd $1, %eax, %xmm2
-; X32-SSE41-NEXT:    sarl $31, %ecx
-; X32-SSE41-NEXT:    pinsrd $3, %ecx, %xmm2
-; X32-SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
-; X32-SSE41-NEXT:    movd %xmm1, %eax
-; X32-SSE41-NEXT:    sarl $31, %eax
-; X32-SSE41-NEXT:    pextrd $2, %xmm1, %ecx
-; X32-SSE41-NEXT:    pinsrd $1, %eax, %xmm1
-; X32-SSE41-NEXT:    sarl $31, %ecx
-; X32-SSE41-NEXT:    pinsrd $3, %ecx, %xmm1
+; X32-SSE41-NEXT:    pmovsxdq %xmm0, %xmm2
+; X32-SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; X32-SSE41-NEXT:    pmovsxdq %xmm0, %xmm1
 ; X32-SSE41-NEXT:    movdqa %xmm2, %xmm0
 ; X32-SSE41-NEXT:    retl
   %extmask = sext <4 x i8> %mask to <4 x i64>
@@ -705,73 +541,36 @@ define <4 x i64> @sext_4i8_to_4i64(<4 x i8> %mask) {
 define <4 x i64> @load_sext_4i8_to_4i64(<4 x i8> *%ptr) {
 ; SSE2-LABEL: load_sext_4i8_to_4i64:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movd (%rdi), %xmm1
-; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[0,1,1,3]
-; SSE2-NEXT:    movd %xmm2, %rax
-; SSE2-NEXT:    movsbq %al, %rax
+; SSE2-NEXT:    movsbq 1(%rdi), %rax
+; SSE2-NEXT:    movd %rax, %xmm1
+; SSE2-NEXT:    movsbq (%rdi), %rax
 ; SSE2-NEXT:    movd %rax, %xmm0
-; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
-; SSE2-NEXT:    movd %xmm2, %rax
-; SSE2-NEXT:    movsbq %al, %rax
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    movsbq 3(%rdi), %rax
 ; SSE2-NEXT:    movd %rax, %xmm2
-; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
-; SSE2-NEXT:    movd %xmm2, %rax
-; SSE2-NEXT:    movsbq %al, %rax
+; SSE2-NEXT:    movsbq 2(%rdi), %rax
 ; SSE2-NEXT:    movd %rax, %xmm1
-; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
-; SSE2-NEXT:    movd %xmm2, %rax
-; SSE2-NEXT:    movsbq %al, %rax
-; SSE2-NEXT:    movd %rax, %xmm2
 ; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: load_sext_4i8_to_4i64:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movd (%rdi), %xmm1
-; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[0,1,1,3]
-; SSSE3-NEXT:    movd %xmm2, %rax
-; SSSE3-NEXT:    movsbq %al, %rax
+; SSSE3-NEXT:    movsbq 1(%rdi), %rax
+; SSSE3-NEXT:    movd %rax, %xmm1
+; SSSE3-NEXT:    movsbq (%rdi), %rax
 ; SSSE3-NEXT:    movd %rax, %xmm0
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
-; SSSE3-NEXT:    movd %xmm2, %rax
-; SSSE3-NEXT:    movsbq %al, %rax
+; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSSE3-NEXT:    movsbq 3(%rdi), %rax
 ; SSSE3-NEXT:    movd %rax, %xmm2
-; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
-; SSSE3-NEXT:    movd %xmm2, %rax
-; SSSE3-NEXT:    movsbq %al, %rax
+; SSSE3-NEXT:    movsbq 2(%rdi), %rax
 ; SSSE3-NEXT:    movd %rax, %xmm1
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
-; SSSE3-NEXT:    movd %xmm2, %rax
-; SSSE3-NEXT:    movsbq %al, %rax
-; SSSE3-NEXT:    movd %rax, %xmm2
 ; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: load_sext_4i8_to_4i64:
 ; SSE41:       # BB#0: # %entry
-; SSE41-NEXT:    pmovzxbd (%rdi), %xmm1
-; SSE41-NEXT:    pmovzxdq %xmm1, %xmm0
-; SSE41-NEXT:    pextrq $1, %xmm0, %rax
-; SSE41-NEXT:    movsbq %al, %rax
-; SSE41-NEXT:    movd %rax, %xmm2
-; SSE41-NEXT:    movd %xmm0, %rax
-; SSE41-NEXT:    movsbq %al, %rax
-; SSE41-NEXT:    movd %rax, %xmm0
-; SSE41-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
-; SSE41-NEXT:    pextrq $1, %xmm1, %rax
-; SSE41-NEXT:    movsbq %al, %rax
-; SSE41-NEXT:    movd %rax, %xmm2
-; SSE41-NEXT:    movd %xmm1, %rax
-; SSE41-NEXT:    movsbq %al, %rax
-; SSE41-NEXT:    movd %rax, %xmm1
-; SSE41-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; SSE41-NEXT:    pmovsxbq (%rdi), %xmm0
+; SSE41-NEXT:    pmovsxbq 2(%rdi), %xmm1
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: load_sext_4i8_to_4i64:
@@ -791,33 +590,11 @@ define <4 x i64> @load_sext_4i8_to_4i64(<4 x i8> *%ptr) {
 ; X32-SSE41-LABEL: load_sext_4i8_to_4i64:
 ; X32-SSE41:       # BB#0: # %entry
 ; X32-SSE41-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-SSE41-NEXT:    movd (%eax), %xmm0
-; X32-SSE41-NEXT:    pmovzxbd %xmm0, %xmm1
-; X32-SSE41-NEXT:    pmovzxbq %xmm0, %xmm2
-; X32-SSE41-NEXT:    movd %xmm2, %eax
-; X32-SSE41-NEXT:    movsbl %al, %eax
-; X32-SSE41-NEXT:    movd %eax, %xmm0
-; X32-SSE41-NEXT:    sarl $31, %eax
-; X32-SSE41-NEXT:    pinsrd $1, %eax, %xmm0
-; X32-SSE41-NEXT:    pextrd $2, %xmm2, %eax
-; X32-SSE41-NEXT:    movsbl %al, %eax
-; X32-SSE41-NEXT:    pinsrd $2, %eax, %xmm0
-; X32-SSE41-NEXT:    sarl $31, %eax
-; X32-SSE41-NEXT:    pinsrd $3, %eax, %xmm0
-; X32-SSE41-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
-; X32-SSE41-NEXT:    movd %xmm2, %eax
-; X32-SSE41-NEXT:    movsbl %al, %eax
-; X32-SSE41-NEXT:    movd %eax, %xmm1
-; X32-SSE41-NEXT:    sarl $31, %eax
-; X32-SSE41-NEXT:    pinsrd $1, %eax, %xmm1
-; X32-SSE41-NEXT:    pextrd $2, %xmm2, %eax
-; X32-SSE41-NEXT:    movsbl %al, %eax
-; X32-SSE41-NEXT:    pinsrd $2, %eax, %xmm1
-; X32-SSE41-NEXT:    sarl $31, %eax
-; X32-SSE41-NEXT:    pinsrd $3, %eax, %xmm1
+; X32-SSE41-NEXT:    pmovsxbq (%eax), %xmm0
+; X32-SSE41-NEXT:    pmovsxbq 2(%eax), %xmm1
 ; X32-SSE41-NEXT:    retl
 entry:
- %X = load <4 x i8>* %ptr
+ %X = load <4 x i8>, <4 x i8>* %ptr
  %Y = sext <4 x i8> %X to <4 x i64>
  ret <4 x i64>%Y
 }
@@ -825,72 +602,36 @@ entry:
 define <4 x i64> @load_sext_4i16_to_4i64(<4 x i16> *%ptr) {
 ; SSE2-LABEL: load_sext_4i16_to_4i64:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movq (%rdi), %xmm1
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[0,1,1,3]
-; SSE2-NEXT:    movd %xmm2, %rax
-; SSE2-NEXT:    movswq %ax, %rax
+; SSE2-NEXT:    movswq 2(%rdi), %rax
+; SSE2-NEXT:    movd %rax, %xmm1
+; SSE2-NEXT:    movswq (%rdi), %rax
 ; SSE2-NEXT:    movd %rax, %xmm0
-; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
-; SSE2-NEXT:    movd %xmm2, %rax
-; SSE2-NEXT:    movswq %ax, %rax
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    movswq 6(%rdi), %rax
 ; SSE2-NEXT:    movd %rax, %xmm2
-; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
-; SSE2-NEXT:    movd %xmm2, %rax
-; SSE2-NEXT:    movswq %ax, %rax
+; SSE2-NEXT:    movswq 4(%rdi), %rax
 ; SSE2-NEXT:    movd %rax, %xmm1
-; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
-; SSE2-NEXT:    movd %xmm2, %rax
-; SSE2-NEXT:    movswq %ax, %rax
-; SSE2-NEXT:    movd %rax, %xmm2
 ; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: load_sext_4i16_to_4i64:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movq (%rdi), %xmm1
-; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[0,1,1,3]
-; SSSE3-NEXT:    movd %xmm2, %rax
-; SSSE3-NEXT:    movswq %ax, %rax
+; SSSE3-NEXT:    movswq 2(%rdi), %rax
+; SSSE3-NEXT:    movd %rax, %xmm1
+; SSSE3-NEXT:    movswq (%rdi), %rax
 ; SSSE3-NEXT:    movd %rax, %xmm0
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
-; SSSE3-NEXT:    movd %xmm2, %rax
-; SSSE3-NEXT:    movswq %ax, %rax
+; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSSE3-NEXT:    movswq 6(%rdi), %rax
 ; SSSE3-NEXT:    movd %rax, %xmm2
-; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
-; SSSE3-NEXT:    movd %xmm2, %rax
-; SSSE3-NEXT:    movswq %ax, %rax
+; SSSE3-NEXT:    movswq 4(%rdi), %rax
 ; SSSE3-NEXT:    movd %rax, %xmm1
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
-; SSSE3-NEXT:    movd %xmm2, %rax
-; SSSE3-NEXT:    movswq %ax, %rax
-; SSSE3-NEXT:    movd %rax, %xmm2
 ; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: load_sext_4i16_to_4i64:
 ; SSE41:       # BB#0: # %entry
-; SSE41-NEXT:    movq (%rdi), %xmm0
-; SSE41-NEXT:    pmovzxwd %xmm0, %xmm1
-; SSE41-NEXT:    pmovzxwq %xmm0, %xmm0
-; SSE41-NEXT:    pextrq $1, %xmm0, %rax
-; SSE41-NEXT:    movswq %ax, %rax
-; SSE41-NEXT:    movd %rax, %xmm2
-; SSE41-NEXT:    movd %xmm0, %rax
-; SSE41-NEXT:    movswq %ax, %rax
-; SSE41-NEXT:    movd %rax, %xmm0
-; SSE41-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
-; SSE41-NEXT:    pextrq $1, %xmm1, %rax
-; SSE41-NEXT:    movswq %ax, %rax
-; SSE41-NEXT:    movd %rax, %xmm2
-; SSE41-NEXT:    movd %xmm1, %rax
-; SSE41-NEXT:    movswq %ax, %rax
-; SSE41-NEXT:    movd %rax, %xmm1
-; SSE41-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; SSE41-NEXT:    pmovsxwq (%rdi), %xmm0
+; SSE41-NEXT:    pmovsxwq 4(%rdi), %xmm1
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: load_sext_4i16_to_4i64:
@@ -910,33 +651,11 @@ define <4 x i64> @load_sext_4i16_to_4i64(<4 x i16> *%ptr) {
 ; X32-SSE41-LABEL: load_sext_4i16_to_4i64:
 ; X32-SSE41:       # BB#0: # %entry
 ; X32-SSE41-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-SSE41-NEXT:    movsd (%eax), %xmm0
-; X32-SSE41-NEXT:    pmovzxwd %xmm0, %xmm1
-; X32-SSE41-NEXT:    pmovzxwq %xmm0, %xmm2
-; X32-SSE41-NEXT:    movd %xmm2, %eax
-; X32-SSE41-NEXT:    cwtl
-; X32-SSE41-NEXT:    movd %eax, %xmm0
-; X32-SSE41-NEXT:    sarl $31, %eax
-; X32-SSE41-NEXT:    pinsrd $1, %eax, %xmm0
-; X32-SSE41-NEXT:    pextrd $2, %xmm2, %eax
-; X32-SSE41-NEXT:    cwtl
-; X32-SSE41-NEXT:    pinsrd $2, %eax, %xmm0
-; X32-SSE41-NEXT:    sarl $31, %eax
-; X32-SSE41-NEXT:    pinsrd $3, %eax, %xmm0
-; X32-SSE41-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
-; X32-SSE41-NEXT:    movd %xmm2, %eax
-; X32-SSE41-NEXT:    cwtl
-; X32-SSE41-NEXT:    movd %eax, %xmm1
-; X32-SSE41-NEXT:    sarl $31, %eax
-; X32-SSE41-NEXT:    pinsrd $1, %eax, %xmm1
-; X32-SSE41-NEXT:    pextrd $2, %xmm2, %eax
-; X32-SSE41-NEXT:    cwtl
-; X32-SSE41-NEXT:    pinsrd $2, %eax, %xmm1
-; X32-SSE41-NEXT:    sarl $31, %eax
-; X32-SSE41-NEXT:    pinsrd $3, %eax, %xmm1
+; X32-SSE41-NEXT:    pmovsxwq (%eax), %xmm0
+; X32-SSE41-NEXT:    pmovsxwq 4(%eax), %xmm1
 ; X32-SSE41-NEXT:    retl
 entry:
- %X = load <4 x i16>* %ptr
+ %X = load <4 x i16>, <4 x i16>* %ptr
  %Y = sext <4 x i16> %X to <4 x i64>
  ret <4 x i64>%Y
 }
diff --git a/test/CodeGen/X86/vector-shuffle-128-v16.ll b/test/CodeGen/X86/vector-shuffle-128-v16.ll
index 14058c912861..53d13c86657b 100644
--- a/test/CodeGen/X86/vector-shuffle-128-v16.ll
+++ b/test/CodeGen/X86/vector-shuffle-128-v16.ll
@@ -1,8 +1,8 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-unknown"
@@ -247,13 +247,34 @@ define <16 x i8> @shuffle_v16i8_08_24_09_25_10_26_11_27_12_28_13_29_14_30_15_31(
 }
 
 define <16 x i8> @shuffle_v16i8_16_00_16_01_16_02_16_03_16_04_16_05_16_06_16_07(<16 x i8> %a, <16 x i8> %b) {
-; SSE-LABEL: shuffle_v16i8_16_00_16_01_16_02_16_03_16_04_16_05_16_06_16_07:
-; SSE:       # BB#0:
-; SSE-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; SSE-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
-; SSE-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; SSE-NEXT:    movdqa %xmm1, %xmm0
-; SSE-NEXT:    retq
+; SSE2-LABEL: shuffle_v16i8_16_00_16_01_16_02_16_03_16_04_16_05_16_06_16_07:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,1,0,3]
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
+; SSE2-NEXT:    pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,4,4,4]
+; SSE2-NEXT:    pand %xmm2, %xmm1
+; SSE2-NEXT:    pandn %xmm0, %xmm2
+; SSE2-NEXT:    por %xmm1, %xmm2
+; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v16i8_16_00_16_01_16_02_16_03_16_04_16_05_16_06_16_07:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSSE3-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
+; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
+; SSSE3-NEXT:    movdqa %xmm1, %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v16i8_16_00_16_01_16_02_16_03_16_04_16_05_16_06_16_07:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE41-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
+; SSE41-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
+; SSE41-NEXT:    movdqa %xmm1, %xmm0
+; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: shuffle_v16i8_16_00_16_01_16_02_16_03_16_04_16_05_16_06_16_07:
 ; AVX1:       # BB#0:
@@ -318,23 +339,20 @@ define <16 x i8> @shuffle_v16i8_03_02_01_00_07_06_05_04_19_18_17_16_23_22_21_20(
 ;
 ; SSSE3-LABEL: shuffle_v16i8_03_02_01_00_07_06_05_04_19_18_17_16_23_22_21_20:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[3,2,1,0,7,6,5,4]
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4],zero,zero,zero,zero,zero,zero,zero,zero
-; SSSE3-NEXT:    por %xmm1, %xmm0
+; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[6,4,2,0,14,12,10,8,7,5,3,1,15,13,11,9]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v16i8_03_02_01_00_07_06_05_04_19_18_17_16_23_22_21_20:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[3,2,1,0,7,6,5,4]
-; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4],zero,zero,zero,zero,zero,zero,zero,zero
-; SSE41-NEXT:    por %xmm1, %xmm0
+; SSE41-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[6,4,2,0,14,12,10,8,7,5,3,1,15,13,11,9]
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v16i8_03_02_01_00_07_06_05_04_19_18_17_16_23_22_21_20:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[3,2,1,0,7,6,5,4]
-; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4],zero,zero,zero,zero,zero,zero,zero,zero
-; AVX-NEXT:    vpor %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[6,4,2,0,14,12,10,8,7,5,3,1,15,13,11,9]
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 19, i32 18, i32 17, i32 16, i32 23, i32 22, i32 21, i32 20>
   ret <16 x i8> %shuffle
@@ -343,47 +361,181 @@ define <16 x i8> @shuffle_v16i8_03_02_01_00_07_06_05_04_19_18_17_16_23_22_21_20(
 define <16 x i8> @shuffle_v16i8_03_02_01_00_31_30_29_28_11_10_09_08_23_22_21_20(<16 x i8> %a, <16 x i8> %b) {
 ; SSE2-LABEL: shuffle_v16i8_03_02_01_00_31_30_29_28_11_10_09_08_23_22_21_20:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    pxor %xmm2, %xmm2
-; SSE2-NEXT:    movdqa %xmm1, %xmm3
-; SSE2-NEXT:    punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3],xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,7,6,5,4]
-; SSE2-NEXT:    movdqa %xmm0, %xmm4
-; SSE2-NEXT:    punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm2[8],xmm4[9],xmm2[9],xmm4[10],xmm2[10],xmm4[11],xmm2[11],xmm4[12],xmm2[12],xmm4[13],xmm2[13],xmm4[14],xmm2[14],xmm4[15],xmm2[15]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm4 = xmm4[3,2,1,0,4,5,6,7]
-; SSE2-NEXT:    movsd %xmm4, %xmm3
-; SSE2-NEXT:    punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm2[8],xmm1[9],xmm2[9],xmm1[10],xmm2[10],xmm1[11],xmm2[11],xmm1[12],xmm2[12],xmm1[13],xmm2[13],xmm1[14],xmm2[14],xmm1[15],xmm2[15]
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,6,5,4]
-; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT:    pxor %xmm1, %xmm1
+; SSE2-NEXT:    movdqa %xmm0, %xmm2
+; SSE2-NEXT:    punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm3 = xmm2[3,2,1,0,4,5,6,7]
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[3,2,1,0,4,5,6,7]
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm1[0]
 ; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
-; SSE2-NEXT:    movsd %xmm0, %xmm1
-; SSE2-NEXT:    packuswb %xmm3, %xmm1
-; SSE2-NEXT:    movdqa %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[2,3,2,3]
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[3,2,1,0,4,5,6,7]
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    packuswb %xmm3, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v16i8_03_02_01_00_31_30_29_28_11_10_09_08_23_22_21_20:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,xmm1[15,14,13,12],zero,zero,zero,zero,xmm1[7,6,5,4]
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[3,2,1,0],zero,zero,zero,zero,xmm0[11,10,9,8],zero,zero,zero,zero
-; SSSE3-NEXT:    por %xmm1, %xmm0
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[15,14,13,12,7,6,5,4,u,u,u,u,u,u,u,u]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,11,10,9,8,u,u,u,u,u,u,u,u]
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v16i8_03_02_01_00_31_30_29_28_11_10_09_08_23_22_21_20:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,xmm1[15,14,13,12],zero,zero,zero,zero,xmm1[7,6,5,4]
-; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[3,2,1,0],zero,zero,zero,zero,xmm0[11,10,9,8],zero,zero,zero,zero
-; SSE41-NEXT:    por %xmm1, %xmm0
+; SSE41-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[15,14,13,12,7,6,5,4,u,u,u,u,u,u,u,u]
+; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,11,10,9,8,u,u,u,u,u,u,u,u]
+; SSE41-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v16i8_03_02_01_00_31_30_29_28_11_10_09_08_23_22_21_20:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpshufb {{.*#+}} xmm1 = zero,zero,zero,zero,xmm1[15,14,13,12],zero,zero,zero,zero,xmm1[7,6,5,4]
-; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0],zero,zero,zero,zero,xmm0[11,10,9,8],zero,zero,zero,zero
-; AVX-NEXT:    vpor %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[15,14,13,12,7,6,5,4,u,u,u,u,u,u,u,u]
+; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,11,10,9,8,u,u,u,u,u,u,u,u]
+; AVX-NEXT:    vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 31, i32 30, i32 29, i32 28, i32 11, i32 10, i32 9, i32 8, i32 23, i32 22, i32 21, i32 20>
   ret <16 x i8> %shuffle
 }
 
+define <16 x i8> @shuffle_v16i8_00_17_02_19_04_21_06_23_08_25_10_27_12_29_14_31(<16 x i8> %a, <16 x i8> %b) {
+; SSE2-LABEL: shuffle_v16i8_00_17_02_19_04_21_06_23_08_25_10_27_12_29_14_31:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
+; SSE2-NEXT:    andps %xmm2, %xmm0
+; SSE2-NEXT:    andnps %xmm1, %xmm2
+; SSE2-NEXT:    orps %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v16i8_00_17_02_19_04_21_06_23_08_25_10_27_12_29_14_31:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v16i8_00_17_02_19_04_21_06_23_08_25_10_27_12_29_14_31:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    movdqa %xmm0, %xmm2
+; SSE41-NEXT:    movaps {{.*#+}} xmm0 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
+; SSE41-NEXT:    pblendvb %xmm2, %xmm1
+; SSE41-NEXT:    movdqa %xmm1, %xmm0
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v16i8_00_17_02_19_04_21_06_23_08_25_10_27_12_29_14_31:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovdqa {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
+; AVX-NEXT:    vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
+  ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_v16i8_00_01_02_19_04_05_06_23_08_09_10_27_12_13_14_31(<16 x i8> %a, <16 x i8> %b) {
+; SSE2-LABEL: shuffle_v16i8_00_01_02_19_04_05_06_23_08_09_10_27_12_13_14_31:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm2 = [255,255,255,0,255,255,255,0,255,255,255,0,255,255,255,0]
+; SSE2-NEXT:    andps %xmm2, %xmm0
+; SSE2-NEXT:    andnps %xmm1, %xmm2
+; SSE2-NEXT:    orps %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v16i8_00_01_02_19_04_05_06_23_08_09_10_27_12_13_14_31:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[15]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,2],zero,xmm0[4,5,6],zero,xmm0[8,9,10],zero,xmm0[12,13,14],zero
+; SSSE3-NEXT:    por %xmm1, %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v16i8_00_01_02_19_04_05_06_23_08_09_10_27_12_13_14_31:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    movdqa %xmm0, %xmm2
+; SSE41-NEXT:    movaps {{.*#+}} xmm0 = [255,255,255,0,255,255,255,0,255,255,255,0,255,255,255,0]
+; SSE41-NEXT:    pblendvb %xmm2, %xmm1
+; SSE41-NEXT:    movdqa %xmm1, %xmm0
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v16i8_00_01_02_19_04_05_06_23_08_09_10_27_12_13_14_31:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovdqa {{.*#+}} xmm2 = [255,255,255,0,255,255,255,0,255,255,255,0,255,255,255,0]
+; AVX-NEXT:    vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 4, i32 5, i32 6, i32 23, i32 8, i32 9, i32 10, i32 27, i32 12, i32 13, i32 14, i32 31>
+  ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_v16i8_00_01_02_03_20_05_06_23_08_09_10_11_28_13_14_31(<16 x i8> %a, <16 x i8> %b) {
+; SSE2-LABEL: shuffle_v16i8_00_01_02_03_20_05_06_23_08_09_10_11_28_13_14_31:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm2 = [255,255,255,255,0,255,255,0,255,255,255,255,0,255,255,0]
+; SSE2-NEXT:    andps %xmm2, %xmm0
+; SSE2-NEXT:    andnps %xmm1, %xmm2
+; SSE2-NEXT:    orps %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v16i8_00_01_02_03_20_05_06_23_08_09_10_11_28_13_14_31:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,xmm1[4],zero,zero,xmm1[7],zero,zero,zero,zero,xmm1[12],zero,zero,xmm1[15]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3],zero,xmm0[5,6],zero,xmm0[8,9,10,11],zero,xmm0[13,14],zero
+; SSSE3-NEXT:    por %xmm1, %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v16i8_00_01_02_03_20_05_06_23_08_09_10_11_28_13_14_31:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    movdqa %xmm0, %xmm2
+; SSE41-NEXT:    movaps {{.*#+}} xmm0 = [255,255,255,255,0,255,255,0,255,255,255,255,0,255,255,0]
+; SSE41-NEXT:    pblendvb %xmm2, %xmm1
+; SSE41-NEXT:    movdqa %xmm1, %xmm0
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v16i8_00_01_02_03_20_05_06_23_08_09_10_11_28_13_14_31:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovdqa {{.*#+}} xmm2 = [255,255,255,255,0,255,255,0,255,255,255,255,0,255,255,0]
+; AVX-NEXT:    vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 23, i32 8, i32 9, i32 10, i32 11, i32 28, i32 13, i32 14, i32 31>
+  ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_v16i8_16_17_18_19_04_05_06_07_24_25_10_11_28_13_30_15(<16 x i8> %a, <16 x i8> %b) {
+; SSE2-LABEL: shuffle_v16i8_16_17_18_19_04_05_06_07_24_25_10_11_28_13_30_15:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm2 = [255,255,255,255,0,0,0,0,255,255,0,0,255,0,255,0]
+; SSE2-NEXT:    andps %xmm2, %xmm1
+; SSE2-NEXT:    andnps %xmm0, %xmm2
+; SSE2-NEXT:    orps %xmm1, %xmm2
+; SSE2-NEXT:    movaps %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v16i8_16_17_18_19_04_05_06_07_24_25_10_11_28_13_30_15:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[4,5,6,7],zero,zero,xmm0[10,11],zero,xmm0[13],zero,xmm0[15]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[0,1,2,3],zero,zero,zero,zero,xmm1[8,9],zero,zero,xmm1[12],zero,xmm1[14],zero
+; SSSE3-NEXT:    por %xmm1, %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v16i8_16_17_18_19_04_05_06_07_24_25_10_11_28_13_30_15:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    movdqa %xmm0, %xmm2
+; SSE41-NEXT:    movaps {{.*#+}} xmm0 = [255,255,255,255,0,0,0,0,255,255,0,0,255,0,255,0]
+; SSE41-NEXT:    pblendvb %xmm1, %xmm2
+; SSE41-NEXT:    movdqa %xmm2, %xmm0
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v16i8_16_17_18_19_04_05_06_07_24_25_10_11_28_13_30_15:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovdqa {{.*#+}} xmm2 = [255,255,255,255,0,0,0,0,255,255,0,0,255,0,255,0]
+; AVX-NEXT:    vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 10, i32 11, i32 28, i32 13, i32 30, i32 15>
+  ret <16 x i8> %shuffle
+}
+
 define <16 x i8> @trunc_v4i32_shuffle(<16 x i8> %a) {
 ; SSE2-LABEL: trunc_v4i32_shuffle:
 ; SSE2:       # BB#0:
@@ -429,12 +581,12 @@ entry:
   ret <16 x i8> %s.16.0
 }
 
-define <16 x i8> @stress_test1(<16 x i8> %s.0.5, <16 x i8> %s.0.8, <16 x i8> %s.0.9) noinline nounwind {
+define <16 x i8> @undef_test1(<16 x i8> %s.0.5, <16 x i8> %s.0.8, <16 x i8> %s.0.9) noinline nounwind {
 ; There is nothing interesting to check about these instructions other than
 ; that they survive codegen. However, we actually do better and delete all of
 ; them because the result is 'undef'.
 ;
-; ALL-LABEL: stress_test1:
+; ALL-LABEL: undef_test1:
 ; ALL:       # BB#0: # %entry
 ; ALL-NEXT:    retq
 entry:
@@ -460,12 +612,7 @@ define <16 x i8> @PR20540(<8 x i8> %a) {
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    pand {{.*}}(%rip), %xmm0
 ; SSE2-NEXT:    packuswb %xmm0, %xmm0
-; SSE2-NEXT:    pxor %xmm1, %xmm1
-; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,1,0,3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,4,4,4]
-; SSE2-NEXT:    packuswb %xmm1, %xmm0
+; SSE2-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: PR20540:
@@ -487,28 +634,16 @@ define <16 x i8> @PR20540(<8 x i8> %a) {
 }
 
 define <16 x i8> @shuffle_v16i8_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(i8 %i) {
-; SSE2-LABEL: shuffle_v16i8_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
-; SSE2:       # BB#0:
-; SSE2-NEXT:    movzbl %dil, %eax
-; SSE2-NEXT:    movd %eax, %xmm0
-; SSE2-NEXT:    retq
-;
-; SSSE3-LABEL: shuffle_v16i8_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
-; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movd %edi, %xmm0
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; SSSE3-NEXT:    retq
-;
-; SSE41-LABEL: shuffle_v16i8_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
-; SSE41:       # BB#0:
-; SSE41-NEXT:    movd %edi, %xmm0
-; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; SSE41-NEXT:    retq
+; SSE-LABEL: shuffle_v16i8_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
+; SSE:       # BB#0:
+; SSE-NEXT:    movzbl %dil, %eax
+; SSE-NEXT:    movd %eax, %xmm0
+; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v16i8_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovd %edi, %xmm0
-; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; AVX-NEXT:    movzbl %dil, %eax
+; AVX-NEXT:    vmovd %eax, %xmm0
 ; AVX-NEXT:    retq
   %a = insertelement <16 x i8> undef, i8 %i, i32 0
   %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -518,27 +653,28 @@ define <16 x i8> @shuffle_v16i8_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(
 define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(i8 %i) {
 ; SSE2-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movzbl %dil, %eax
-; SSE2-NEXT:    movd %eax, %xmm0
-; SSE2-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10]
+; SSE2-NEXT:    shll   $8, %edi
+; SSE2-NEXT:    pxor   %xmm0, %xmm0
+; SSE2-NEXT:    pinsrw $2, %edi, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movd %edi, %xmm0
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,xmm0[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; SSSE3-NEXT:    shll   $8, %edi
+; SSSE3-NEXT:    pxor   %xmm0, %xmm0
+; SSSE3-NEXT:    pinsrw $2, %edi, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    movd %edi, %xmm0
-; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,xmm0[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; SSE41-NEXT:    pxor   %xmm0, %xmm0
+; SSE41-NEXT:    pinsrb $5, %edi, %xmm0
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovd %edi, %xmm0
-; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,xmm0[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; AVX-NEXT:    vpxor   %xmm0, %xmm0
+; AVX-NEXT:    vpinsrb $5, %edi, %xmm0
 ; AVX-NEXT:    retq
   %a = insertelement <16 x i8> undef, i8 %i, i32 0
   %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
@@ -546,16 +682,30 @@ define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(
 }
 
 define <16 x i8> @shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16(i8 %i) {
-; SSE-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16:
-; SSE:       # BB#0:
-; SSE-NEXT:    movd %edi, %xmm0
-; SSE-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0]
-; SSE-NEXT:    retq
+; SSE2-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    shll   $8, %edi
+; SSE2-NEXT:    pxor   %xmm0, %xmm0
+; SSE2-NEXT:    pinsrw $7, %edi, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    shll   $8, %edi
+; SSSE3-NEXT:    pxor   %xmm0, %xmm0
+; SSSE3-NEXT:    pinsrw $7, %edi, %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pxor   %xmm0, %xmm0
+; SSE41-NEXT:    pinsrb $15, %edi, %xmm0
+; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovd %edi, %xmm0
-; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0]
+; AVX-NEXT:    vpxor   %xmm0, %xmm0
+; AVX-NEXT:    vpinsrb $15, %edi, %xmm0
 ; AVX-NEXT:    retq
   %a = insertelement <16 x i8> undef, i8 %i, i32 0
   %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 16>
@@ -566,29 +716,27 @@ define <16 x i8> @shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(
 ; SSE2-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    movzbl %dil, %eax
-; SSE2-NEXT:    movd %eax, %xmm0
-; SSE2-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
+; SSE2-NEXT:    pxor   %xmm0, %xmm0
+; SSE2-NEXT:    pinsrw $1, %eax, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movd %edi, %xmm0
-; SSSE3-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12]
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; SSSE3-NEXT:    movzbl %dil, %eax
+; SSSE3-NEXT:    pxor   %xmm0, %xmm0
+; SSSE3-NEXT:    pinsrw $1, %eax, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    movd %edi, %xmm0
-; SSE41-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12]
-; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; SSE41-NEXT:    pxor   %xmm0, %xmm0
+; SSE41-NEXT:    pinsrb $2, %edi, %xmm0
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovd %edi, %xmm0
-; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12]
-; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; AVX-NEXT:    vpxor   %xmm0, %xmm0
+; AVX-NEXT:    vpinsrb $2, %edi, %xmm0
 ; AVX-NEXT:    retq
   %a = insertelement <16 x i8> undef, i8 %i, i32 3
   %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 19, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -605,7 +753,7 @@ define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_16_uu_18_uu(
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3]
 ; AVX-NEXT:    retq
-  %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 09, i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 undef, i32 18, i32 undef>
+  %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 undef, i32 18, i32 undef>
   ret <16 x i8> %shuffle
 }
 
@@ -800,12 +948,12 @@ define <16 x i8> @shuffle_v16i8_00_uu_uu_uu_uu_uu_uu_uu_01_uu_uu_uu_uu_uu_uu_uu(
 ;
 ; SSE41-LABEL: shuffle_v16i8_00_uu_uu_uu_uu_uu_uu_uu_01_uu_uu_uu_uu_uu_uu_uu:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxbq %xmm0, %xmm0
+; SSE41-NEXT:    pmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v16i8_00_uu_uu_uu_uu_uu_uu_uu_01_uu_uu_uu_uu_uu_uu_uu:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpmovzxbq %xmm0, %xmm0
+; AVX-NEXT:    vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   ret <16 x i8> %shuffle
@@ -827,12 +975,12 @@ define <16 x i8> @shuffle_v16i8_00_zz_zz_zz_zz_zz_zz_zz_01_zz_zz_zz_zz_zz_zz_zz(
 ;
 ; SSE41-LABEL: shuffle_v16i8_00_zz_zz_zz_zz_zz_zz_zz_01_zz_zz_zz_zz_zz_zz_zz:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxbq %xmm0, %xmm0
+; SSE41-NEXT:    pmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v16i8_00_zz_zz_zz_zz_zz_zz_zz_01_zz_zz_zz_zz_zz_zz_zz:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpmovzxbq %xmm0, %xmm0
+; AVX-NEXT:    vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 1, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %shuffle
@@ -853,12 +1001,12 @@ define <16 x i8> @shuffle_v16i8_00_uu_uu_uu_01_uu_uu_uu_02_uu_uu_uu_03_uu_uu_uu(
 ;
 ; SSE41-LABEL: shuffle_v16i8_00_uu_uu_uu_01_uu_uu_uu_02_uu_uu_uu_03_uu_uu_uu:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxbd %xmm0, %xmm0
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v16i8_00_uu_uu_uu_01_uu_uu_uu_02_uu_uu_uu_03_uu_uu_uu:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpmovzxbd %xmm0, %xmm0
+; AVX-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 undef, i32 undef, i32 2, i32 undef, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 undef>
   ret <16 x i8> %shuffle
@@ -881,12 +1029,12 @@ define <16 x i8> @shuffle_v16i8_00_zz_zz_zz_01_zz_zz_zz_02_zz_zz_zz_03_zz_zz_zz(
 ;
 ; SSE41-LABEL: shuffle_v16i8_00_zz_zz_zz_01_zz_zz_zz_02_zz_zz_zz_03_zz_zz_zz:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxbd %xmm0, %xmm0
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v16i8_00_zz_zz_zz_01_zz_zz_zz_02_zz_zz_zz_03_zz_zz_zz:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpmovzxbd %xmm0, %xmm0
+; AVX-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 17, i32 18, i32 19, i32 1, i32 21, i32 22, i32 23, i32 2, i32 25, i32 26, i32 27, i32 3, i32 29, i32 30, i32 31>
   ret <16 x i8> %shuffle
@@ -905,12 +1053,12 @@ define <16 x i8> @shuffle_v16i8_00_uu_01_uu_02_uu_03_uu_04_uu_05_uu_06_uu_07_uu(
 ;
 ; SSE41-LABEL: shuffle_v16i8_00_uu_01_uu_02_uu_03_uu_04_uu_05_uu_06_uu_07_uu:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxbw %xmm0, %xmm0
+; SSE41-NEXT:    pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v16i8_00_uu_01_uu_02_uu_03_uu_04_uu_05_uu_06_uu_07_uu:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpmovzxbw %xmm0, %xmm0
+; AVX-NEXT:    vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3, i32 undef, i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7, i32 undef>
   ret <16 x i8> %shuffle
@@ -931,12 +1079,12 @@ define <16 x i8> @shuffle_v16i8_00_zz_01_zz_02_zz_03_zz_04_zz_05_zz_06_zz_07_zz(
 ;
 ; SSE41-LABEL: shuffle_v16i8_00_zz_01_zz_02_zz_03_zz_04_zz_05_zz_06_zz_07_zz:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxbw %xmm0, %xmm0
+; SSE41-NEXT:    pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v16i8_00_zz_01_zz_02_zz_03_zz_04_zz_05_zz_06_zz_07_zz:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpmovzxbw %xmm0, %xmm0
+; AVX-NEXT:    vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 17, i32 1, i32 19, i32 2, i32 21, i32 3, i32 23, i32 4, i32 25, i32 5, i32 27, i32 6, i32 29, i32 7, i32 31>
   ret <16 x i8> %shuffle
@@ -948,69 +1096,53 @@ define <16 x i8> @shuffle_v16i8_uu_10_02_07_22_14_07_02_18_03_01_14_18_09_11_00(
 ; SSE2-NEXT:    pxor %xmm2, %xmm2
 ; SSE2-NEXT:    movdqa %xmm0, %xmm3
 ; SSE2-NEXT:    punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm3[2,3,0,1]
-; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm2 = xmm0[0,2,2,3,4,5,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[0,3,2,3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,3,4,5,6,7]
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm2 = xmm2[2,0,3,1,4,5,6,7]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm4 = xmm3[2,1,2,3,4,5,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm4[0,3,2,3]
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm0[0],xmm4[1],xmm0[1],xmm4[2],xmm0[2],xmm4[3],xmm0[3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm4 = xmm4[0,2,2,3,4,5,6,7]
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,4,7,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm4 = xmm4[0,2,3,1,4,5,6,7]
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3]
-; SSE2-NEXT:    packuswb %xmm0, %xmm4
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[2,1,2,3,4,5,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,3,2,3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,1,3,3,4,5,6,7]
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,7,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm2 = xmm0[0,2,1,3,4,5,6,7]
-; SSE2-NEXT:    packuswb %xmm0, %xmm2
-; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[3,1,2,3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm3[0,3,0,1]
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm4 = xmm4[0,1,2,2,4,5,6,7]
+; SSE2-NEXT:    pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,4,5,7,7]
+; SSE2-NEXT:    movdqa {{.*#+}} xmm5 = [65535,65535,65535,0,65535,0,0,65535]
 ; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
-; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[0,1,0,3]
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm2 = xmm2[0,3,1,3,4,5,6,7]
+; SSE2-NEXT:    pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,5,6,4]
+; SSE2-NEXT:    pand %xmm5, %xmm2
+; SSE2-NEXT:    pandn %xmm4, %xmm5
+; SSE2-NEXT:    por %xmm2, %xmm5
+; SSE2-NEXT:    psrlq $16, %xmm3
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,1,1,3]
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,1,2,1,4,5,6,7]
+; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,7,4]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; SSE2-NEXT:    packuswb %xmm5, %xmm2
+; SSE2-NEXT:    movdqa {{.*#+}} xmm0 = [255,255,255,255,0,255,255,255,0,255,255,255,0,255,255,255]
+; SSE2-NEXT:    pand %xmm0, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,1,0,3]
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[0,1,3,3,4,5,6,7]
+; SSE2-NEXT:    pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,5,5,5,7]
+; SSE2-NEXT:    pandn %xmm1, %xmm0
+; SSE2-NEXT:    por %xmm2, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v16i8_uu_10_02_07_22_14_07_02_18_03_01_14_18_09_11_00:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movdqa %xmm0, %xmm2
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm2 = xmm2[2,7,1,11,u,u,u,u,u,u,u,u,u,u,u,u]
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[6,6,2,2,2,2,3,3,4,4,5,5,6,6,7,7]
-; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[10,7,14,2,3,14,9,0,u,u,u,u,u,u,u,u]
-; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; SSSE3-NEXT:    movdqa %xmm1, %xmm0
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[u],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[2],zero,zero,zero
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[u,10,2,7],zero,xmm0[14,7,2],zero,xmm0[3,1,14],zero,xmm0[9,11,0]
+; SSSE3-NEXT:    por %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v16i8_uu_10_02_07_22_14_07_02_18_03_01_14_18_09_11_00:
 ; SSE41:       # BB#0: # %entry
-; SSE41-NEXT:    movdqa %xmm0, %xmm2
-; SSE41-NEXT:    pshufb {{.*#+}} xmm2 = xmm2[2,7,1,11,u,u,u,u,u,u,u,u,u,u,u,u]
-; SSE41-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[6,6,2,2,2,2,3,3,4,4,5,5,6,6,7,7]
-; SSE41-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
-; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[10,7,14,2,3,14,9,0,u,u,u,u,u,u,u,u]
-; SSE41-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; SSE41-NEXT:    movdqa %xmm1, %xmm0
+; SSE41-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[u],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[2],zero,zero,zero
+; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[u,10,2,7],zero,xmm0[14,7,2],zero,xmm0[3,1,14],zero,xmm0[9,11,0]
+; SSE41-NEXT:    por %xmm1, %xmm0
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v16i8_uu_10_02_07_22_14_07_02_18_03_01_14_18_09_11_00:
 ; AVX:       # BB#0: # %entry
-; AVX-NEXT:    vpshufb {{.*#+}} xmm2 = xmm0[2,7,1,11,u,u,u,u,u,u,u,u,u,u,u,u]
-; AVX-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[6,6,2,2,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX-NEXT:    vpunpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
-; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[10,7,14,2,3,14,9,0,u,u,u,u,u,u,u,u]
-; AVX-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
+; AVX-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[u],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[2],zero,zero,zero
+; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[u,10,2,7],zero,xmm0[14,7,2],zero,xmm0[3,1,14],zero,xmm0[9,11,0]
+; AVX-NEXT:    vpor %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 entry:
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 undef, i32 10, i32 2, i32 7, i32 22, i32 14, i32 7, i32 2, i32 18, i32 3, i32 1, i32 14, i32 18, i32 9, i32 11, i32 0>
@@ -1053,6 +1185,108 @@ entry:
   ret void
 }
 
+;
+; Shuffle to logical bit shifts
+;
+
+define <16 x i8> @shuffle_v16i8_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_14(<16 x i8> %a, <16 x i8> %b) {
+; SSE-LABEL: shuffle_v16i8_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_14:
+; SSE:       # BB#0:
+; SSE-NEXT:    psllw $8, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v16i8_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_14:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsllw $8, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 16, i32 2, i32 16, i32 4, i32 16, i32 6, i32 16, i32 8, i32 16, i32 10, i32 16, i32 12, i32 16, i32 14>
+  ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_v16i8_zz_zz_zz_00_zz_zz_zz_04_zz_zz_zz_08_zz_zz_zz_12(<16 x i8> %a, <16 x i8> %b) {
+; SSE-LABEL: shuffle_v16i8_zz_zz_zz_00_zz_zz_zz_04_zz_zz_zz_08_zz_zz_zz_12:
+; SSE:       # BB#0:
+; SSE-NEXT:    pslld $24, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v16i8_zz_zz_zz_00_zz_zz_zz_04_zz_zz_zz_08_zz_zz_zz_12:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpslld $24, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 4, i32 16, i32 16, i32 16, i32 8, i32 16, i32 16, i32 16, i32 12>
+  ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_00_zz_zz_zz_zz_zz_zz_zz_08(<16 x i8> %a, <16 x i8> %b) {
+; SSE-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_00_zz_zz_zz_zz_zz_zz_zz_08:
+; SSE:       # BB#0:
+; SSE-NEXT:    psllq $56, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_00_zz_zz_zz_zz_zz_zz_zz_08:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsllq $56, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 8>
+  ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_v16i8_zz_00_uu_02_03_uu_05_06_zz_08_09_uu_11_12_13_14(<16 x i8> %a, <16 x i8> %b) {
+; SSE-LABEL: shuffle_v16i8_zz_00_uu_02_03_uu_05_06_zz_08_09_uu_11_12_13_14:
+; SSE:       # BB#0:
+; SSE-NEXT:    psllq $8, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v16i8_zz_00_uu_02_03_uu_05_06_zz_08_09_uu_11_12_13_14:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsllq $8, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 undef, i32 2, i32 3, i32 undef, i32 5, i32 6, i32 16, i32 8, i32 9, i32 undef, i32 11, i32 12, i32 13, i32 14>
+  ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_v16i8_01_uu_uu_uu_uu_zz_uu_zz_uu_zz_11_zz_13_zz_15_zz(<16 x i8> %a, <16 x i8> %b) {
+; SSE-LABEL: shuffle_v16i8_01_uu_uu_uu_uu_zz_uu_zz_uu_zz_11_zz_13_zz_15_zz:
+; SSE:       # BB#0:
+; SSE-NEXT:    psrlw $8, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v16i8_01_uu_uu_uu_uu_zz_uu_zz_uu_zz_11_zz_13_zz_15_zz:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsrlw $8, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 undef, i32 16, i32 undef, i32 16, i32 11, i32 16, i32 13, i32 16, i32 15, i32 16>
+  ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_v16i8_02_03_zz_zz_06_07_uu_uu_uu_uu_uu_uu_14_15_zz_zz(<16 x i8> %a, <16 x i8> %b) {
+; SSE-LABEL: shuffle_v16i8_02_03_zz_zz_06_07_uu_uu_uu_uu_uu_uu_14_15_zz_zz:
+; SSE:       # BB#0:
+; SSE-NEXT:    psrld $16, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v16i8_02_03_zz_zz_06_07_uu_uu_uu_uu_uu_uu_14_15_zz_zz:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsrld $16, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 2, i32 3, i32 16, i32 16, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 14, i32 15, i32 16, i32 16>
+  ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_v16i8_07_zz_zz_zz_zz_zz_uu_uu_15_uu_uu_uu_uu_uu_zz_zz(<16 x i8> %a, <16 x i8> %b) {
+; SSE-LABEL: shuffle_v16i8_07_zz_zz_zz_zz_zz_uu_uu_15_uu_uu_uu_uu_uu_zz_zz:
+; SSE:       # BB#0:
+; SSE-NEXT:    psrlq $56, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v16i8_07_zz_zz_zz_zz_zz_uu_uu_15_uu_uu_uu_uu_uu_zz_zz:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsrlq $56, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 7, i32 16, i32 16, i32 16, i32 16, i32 16, i32 undef, i32 undef, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 16>
+  ret <16 x i8> %shuffle
+}
+
 define <16 x i8> @PR12412(<16 x i8> %inval1, <16 x i8> %inval2) {
 ; SSE2-LABEL: PR12412:
 ; SSE2:       # BB#0: # %entry
@@ -1063,26 +1297,62 @@ define <16 x i8> @PR12412(<16 x i8> %inval1, <16 x i8> %inval2) {
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: PR12412:
-; SSSE3:      # BB#0: # %entry
-; SSSE3-NEXT:   pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,2,4,6,8,10,12,14]
-; SSSE3-NEXT:   pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
-; SSSE3-NEXT:   por %xmm1, %xmm0
-; SSSE3-NEXT:   retq
+; SSSE3:       # BB#0: # %entry
+; SSSE3-NEXT:    movdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
+; SSSE3-NEXT:    pshufb %xmm2, %xmm1
+; SSSE3-NEXT:    pshufb %xmm2, %xmm0
+; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: PR12412:
-; SSE41:      # BB#0: # %entry
-; SSE41-NEXT:   pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,2,4,6,8,10,12,14]
-; SSE41-NEXT:   pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
-; SSE41-NEXT:   por %xmm1, %xmm0
-; SSE41-NEXT:   retq
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    movdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
+; SSE41-NEXT:    pshufb %xmm2, %xmm1
+; SSE41-NEXT:    pshufb %xmm2, %xmm0
+; SSE41-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: PR12412:
-; AVX:        # BB#0: # %entry
-; AVX-NEXT:     vpshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,2,4,6,8,10,12,14]
-; AVX-NEXT:     vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
-; AVX-NEXT:     vpor %xmm1, %xmm0, %xmm0
-; AVX-NEXT:     retq
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
+; AVX-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
+; AVX-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX-NEXT:    retq
 entry:
   %0 = shufflevector <16 x i8> %inval1, <16 x i8> %inval2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
   ret <16 x i8> %0
 }
+
+define <16 x i8> @shuffle_v16i8_uu_02_03_zz_uu_06_07_zz_uu_10_11_zz_uu_14_15_zz(<16 x i8> %a) {
+; SSE-LABEL: shuffle_v16i8_uu_02_03_zz_uu_06_07_zz_uu_10_11_zz_uu_14_15_zz:
+; SSE:       # BB#0:
+; SSE-NEXT:    psrld $8, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v16i8_uu_02_03_zz_uu_06_07_zz_uu_10_11_zz_uu_14_15_zz:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsrld $8, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 undef, i32 2, i32 3, i32 16, i32 undef, i32 6, i32 7, i32 16, i32 undef, i32 10, i32 11, i32 16, i32 undef, i32 14, i32 15, i32 16>
+  ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_v16i8_bitcast_unpack(<16 x i8> %a, <16 x i8> %b) {
+; SSE-LABEL: shuffle_v16i8_bitcast_unpack:
+; SSE:       # BB#0:
+; SSE-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v16i8_bitcast_unpack:
+; AVX:       # BB#0:
+; AVX-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; AVX-NEXT:    retq
+  %shuffle8  = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 7, i32 23, i32 6, i32 22, i32 5, i32 21, i32 4, i32 20, i32 3, i32 19, i32 2, i32 18, i32 1, i32 17, i32 0, i32 16>
+  %bitcast32 = bitcast <16 x i8> %shuffle8 to <4 x float>
+  %shuffle32 = shufflevector <4 x float> %bitcast32, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %bitcast16 = bitcast <4 x float> %shuffle32 to <8 x i16>
+  %shuffle16 = shufflevector <8 x i16> %bitcast16, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+  %bitcast8  = bitcast <8 x i16> %shuffle16 to <16 x i8>
+  ret <16 x i8> %bitcast8
+}
diff --git a/test/CodeGen/X86/vector-shuffle-128-v2.ll b/test/CodeGen/X86/vector-shuffle-128-v2.ll
index 57fa0e859813..ee68df581bfd 100644
--- a/test/CodeGen/X86/vector-shuffle-128-v2.ll
+++ b/test/CodeGen/X86/vector-shuffle-128-v2.ll
@@ -1,9 +1,9 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse3 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-unknown"
@@ -105,22 +105,22 @@ define <2 x double> @shuffle_v2f64_00(<2 x double> %a, <2 x double> %b) {
 ;
 ; SSE3-LABEL: shuffle_v2f64_00:
 ; SSE3:       # BB#0:
-; SSE3-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; SSE3-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v2f64_00:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; SSSE3-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v2f64_00:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; SSE41-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v2f64_00:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 0>
   ret <2 x double> %shuffle
@@ -160,25 +160,22 @@ define <2 x double> @shuffle_v2f64_22(<2 x double> %a, <2 x double> %b) {
 ;
 ; SSE3-LABEL: shuffle_v2f64_22:
 ; SSE3:       # BB#0:
-; SSE3-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0,0]
-; SSE3-NEXT:    movapd %xmm1, %xmm0
+; SSE3-NEXT:    movddup {{.*#+}} xmm0 = xmm1[0,0]
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v2f64_22:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0,0]
-; SSSE3-NEXT:    movapd %xmm1, %xmm0
+; SSSE3-NEXT:    movddup {{.*#+}} xmm0 = xmm1[0,0]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v2f64_22:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0,0]
-; SSE41-NEXT:    movapd %xmm1, %xmm0
+; SSE41-NEXT:    movddup {{.*#+}} xmm0 = xmm1[0,0]
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v2f64_22:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm1[0,0]
+; AVX-NEXT:    vmovddup {{.*#+}} xmm0 = xmm1[0,0]
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 2, i32 2>
   ret <2 x double> %shuffle
@@ -214,20 +211,20 @@ define <2 x double> @shuffle_v2f64_33(<2 x double> %a, <2 x double> %b) {
 define <2 x double> @shuffle_v2f64_03(<2 x double> %a, <2 x double> %b) {
 ; SSE2-LABEL: shuffle_v2f64_03:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movsd %xmm0, %xmm1
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE2-NEXT:    movapd %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: shuffle_v2f64_03:
 ; SSE3:       # BB#0:
-; SSE3-NEXT:    movsd %xmm0, %xmm1
-; SSE3-NEXT:    movaps %xmm1, %xmm0
+; SSE3-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE3-NEXT:    movapd %xmm1, %xmm0
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v2f64_03:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movsd %xmm0, %xmm1
-; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSSE3-NEXT:    movapd %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v2f64_03:
@@ -245,17 +242,17 @@ define <2 x double> @shuffle_v2f64_03(<2 x double> %a, <2 x double> %b) {
 define <2 x double> @shuffle_v2f64_21(<2 x double> %a, <2 x double> %b) {
 ; SSE2-LABEL: shuffle_v2f64_21:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movsd %xmm1, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: shuffle_v2f64_21:
 ; SSE3:       # BB#0:
-; SSE3-NEXT:    movsd %xmm1, %xmm0
+; SSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v2f64_21:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movsd %xmm1, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v2f64_21:
@@ -302,20 +299,20 @@ define <2 x i64> @shuffle_v2i64_02_copy(<2 x i64> %nonce, <2 x i64> %a, <2 x i64
 define <2 x i64> @shuffle_v2i64_03(<2 x i64> %a, <2 x i64> %b) {
 ; SSE2-LABEL: shuffle_v2i64_03:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movsd %xmm0, %xmm1
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE2-NEXT:    movapd %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: shuffle_v2i64_03:
 ; SSE3:       # BB#0:
-; SSE3-NEXT:    movsd %xmm0, %xmm1
-; SSE3-NEXT:    movaps %xmm1, %xmm0
+; SSE3-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE3-NEXT:    movapd %xmm1, %xmm0
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v2i64_03:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movsd %xmm0, %xmm1
-; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSSE3-NEXT:    movapd %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v2i64_03:
@@ -338,20 +335,20 @@ define <2 x i64> @shuffle_v2i64_03(<2 x i64> %a, <2 x i64> %b) {
 define <2 x i64> @shuffle_v2i64_03_copy(<2 x i64> %nonce, <2 x i64> %a, <2 x i64> %b) {
 ; SSE2-LABEL: shuffle_v2i64_03_copy:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movsd %xmm1, %xmm2
-; SSE2-NEXT:    movaps %xmm2, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
+; SSE2-NEXT:    movapd %xmm2, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: shuffle_v2i64_03_copy:
 ; SSE3:       # BB#0:
-; SSE3-NEXT:    movsd %xmm1, %xmm2
-; SSE3-NEXT:    movaps %xmm2, %xmm0
+; SSE3-NEXT:    movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
+; SSE3-NEXT:    movapd %xmm2, %xmm0
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v2i64_03_copy:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movsd %xmm1, %xmm2
-; SSSE3-NEXT:    movaps %xmm2, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
+; SSSE3-NEXT:    movapd %xmm2, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v2i64_03_copy:
@@ -492,17 +489,17 @@ define <2 x i64> @shuffle_v2i64_20_copy(<2 x i64> %nonce, <2 x i64> %a, <2 x i64
 define <2 x i64> @shuffle_v2i64_21(<2 x i64> %a, <2 x i64> %b) {
 ; SSE2-LABEL: shuffle_v2i64_21:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movsd %xmm1, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: shuffle_v2i64_21:
 ; SSE3:       # BB#0:
-; SSE3-NEXT:    movsd %xmm1, %xmm0
+; SSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v2i64_21:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movsd %xmm1, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v2i64_21:
@@ -525,20 +522,20 @@ define <2 x i64> @shuffle_v2i64_21(<2 x i64> %a, <2 x i64> %b) {
 define <2 x i64> @shuffle_v2i64_21_copy(<2 x i64> %nonce, <2 x i64> %a, <2 x i64> %b) {
 ; SSE2-LABEL: shuffle_v2i64_21_copy:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movsd %xmm2, %xmm1
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
+; SSE2-NEXT:    movapd %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: shuffle_v2i64_21_copy:
 ; SSE3:       # BB#0:
-; SSE3-NEXT:    movsd %xmm2, %xmm1
-; SSE3-NEXT:    movaps %xmm1, %xmm0
+; SSE3-NEXT:    movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
+; SSE3-NEXT:    movapd %xmm1, %xmm0
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v2i64_21_copy:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movsd %xmm2, %xmm1
-; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
+; SSSE3-NEXT:    movapd %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v2i64_21_copy:
@@ -653,12 +650,12 @@ define <2 x i64> @shuffle_v2i64_31_copy(<2 x i64> %nonce, <2 x i64> %a, <2 x i64
 define <2 x i64> @shuffle_v2i64_0z(<2 x i64> %a) {
 ; SSE-LABEL: shuffle_v2i64_0z:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movq %xmm0, %xmm0
+; SSE-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v2i64_0z:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovq %xmm0, %xmm0
+; AVX-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> <i32 0, i32 3>
   ret <2 x i64> %shuffle
@@ -695,20 +692,20 @@ define <2 x i64> @shuffle_v2i64_z0(<2 x i64> %a) {
 define <2 x i64> @shuffle_v2i64_z1(<2 x i64> %a) {
 ; SSE2-LABEL: shuffle_v2i64_z1:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    xorps %xmm1, %xmm1
-; SSE2-NEXT:    movsd %xmm1, %xmm0
+; SSE2-NEXT:    xorpd %xmm1, %xmm1
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: shuffle_v2i64_z1:
 ; SSE3:       # BB#0:
-; SSE3-NEXT:    xorps %xmm1, %xmm1
-; SSE3-NEXT:    movsd %xmm1, %xmm0
+; SSE3-NEXT:    xorpd %xmm1, %xmm1
+; SSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v2i64_z1:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    xorps %xmm1, %xmm1
-; SSSE3-NEXT:    movsd %xmm1, %xmm0
+; SSSE3-NEXT:    xorpd %xmm1, %xmm1
+; SSSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v2i64_z1:
@@ -735,12 +732,12 @@ define <2 x i64> @shuffle_v2i64_z1(<2 x i64> %a) {
 define <2 x double> @shuffle_v2f64_0z(<2 x double> %a) {
 ; SSE-LABEL: shuffle_v2f64_0z:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movq %xmm0, %xmm0
+; SSE-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v2f64_0z:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovq %xmm0, %xmm0
+; AVX-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <2 x double> %a, <2 x double> zeroinitializer, <2 x i32> <i32 0, i32 3>
   ret <2 x double> %shuffle
@@ -782,20 +779,20 @@ define <2 x double> @shuffle_v2f64_z0(<2 x double> %a) {
 define <2 x double> @shuffle_v2f64_z1(<2 x double> %a) {
 ; SSE2-LABEL: shuffle_v2f64_z1:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    xorps %xmm1, %xmm1
-; SSE2-NEXT:    movsd %xmm1, %xmm0
+; SSE2-NEXT:    xorpd %xmm1, %xmm1
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: shuffle_v2f64_z1:
 ; SSE3:       # BB#0:
-; SSE3-NEXT:    xorps %xmm1, %xmm1
-; SSE3-NEXT:    movsd %xmm1, %xmm0
+; SSE3-NEXT:    xorpd %xmm1, %xmm1
+; SSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v2f64_z1:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    xorps %xmm1, %xmm1
-; SSSE3-NEXT:    movsd %xmm1, %xmm0
+; SSSE3-NEXT:    xorpd %xmm1, %xmm1
+; SSSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v2f64_z1:
@@ -813,6 +810,25 @@ define <2 x double> @shuffle_v2f64_z1(<2 x double> %a) {
   ret <2 x double> %shuffle
 }
 
+define <2 x double> @shuffle_v2f64_bitcast_1z(<2 x double> %a) {
+; SSE-LABEL: shuffle_v2f64_bitcast_1z:
+; SSE:       # BB#0:
+; SSE-NEXT:    xorpd %xmm1, %xmm1
+; SSE-NEXT:    shufpd {{.*#+}} xmm0 = xmm0[1],xmm1[0]
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v2f64_bitcast_1z:
+; AVX:       # BB#0:
+; AVX-NEXT:    vxorpd %xmm1, %xmm1, %xmm1
+; AVX-NEXT:    vshufpd {{.*#+}} xmm0 = xmm0[1],xmm1[0]
+; AVX-NEXT:    retq
+  %shuffle64 = shufflevector <2 x double> %a, <2 x double> zeroinitializer, <2 x i32> <i32 2, i32 1>
+  %bitcast32 = bitcast <2 x double> %shuffle64 to <4 x float>
+  %shuffle32 = shufflevector <4 x float> %bitcast32, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
+  %bitcast64 = bitcast <4 x float> %shuffle32 to <2 x double>
+  ret <2 x double> %bitcast64
+}
+
 define <2 x i64> @insert_reg_and_zero_v2i64(i64 %a) {
 ; SSE-LABEL: insert_reg_and_zero_v2i64:
 ; SSE:       # BB#0:
@@ -831,14 +847,14 @@ define <2 x i64> @insert_reg_and_zero_v2i64(i64 %a) {
 define <2 x i64> @insert_mem_and_zero_v2i64(i64* %ptr) {
 ; SSE-LABEL: insert_mem_and_zero_v2i64:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movq (%rdi), %xmm0
+; SSE-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_mem_and_zero_v2i64:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovq (%rdi), %xmm0
+; AVX-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero
 ; AVX-NEXT:    retq
-  %a = load i64* %ptr
+  %a = load i64, i64* %ptr
   %v = insertelement <2 x i64> undef, i64 %a, i32 0
   %shuffle = shufflevector <2 x i64> %v, <2 x i64> zeroinitializer, <2 x i32> <i32 0, i32 3>
   ret <2 x i64> %shuffle
@@ -847,12 +863,12 @@ define <2 x i64> @insert_mem_and_zero_v2i64(i64* %ptr) {
 define <2 x double> @insert_reg_and_zero_v2f64(double %a) {
 ; SSE-LABEL: insert_reg_and_zero_v2f64:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movq %xmm0, %xmm0
+; SSE-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_reg_and_zero_v2f64:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovq %xmm0, %xmm0
+; AVX-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero
 ; AVX-NEXT:    retq
   %v = insertelement <2 x double> undef, double %a, i32 0
   %shuffle = shufflevector <2 x double> %v, <2 x double> zeroinitializer, <2 x i32> <i32 0, i32 3>
@@ -862,14 +878,14 @@ define <2 x double> @insert_reg_and_zero_v2f64(double %a) {
 define <2 x double> @insert_mem_and_zero_v2f64(double* %ptr) {
 ; SSE-LABEL: insert_mem_and_zero_v2f64:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movsd (%rdi), %xmm0
+; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_mem_and_zero_v2f64:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovsd (%rdi), %xmm0
+; AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-NEXT:    retq
-  %a = load double* %ptr
+  %a = load double, double* %ptr
   %v = insertelement <2 x double> undef, double %a, i32 0
   %shuffle = shufflevector <2 x double> %v, <2 x double> zeroinitializer, <2 x i32> <i32 0, i32 3>
   ret <2 x double> %shuffle
@@ -879,19 +895,19 @@ define <2 x i64> @insert_reg_lo_v2i64(i64 %a, <2 x i64> %b) {
 ; SSE2-LABEL: insert_reg_lo_v2i64:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    movd %rdi, %xmm1
-; SSE2-NEXT:    movsd %xmm1, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: insert_reg_lo_v2i64:
 ; SSE3:       # BB#0:
 ; SSE3-NEXT:    movd %rdi, %xmm1
-; SSE3-NEXT:    movsd %xmm1, %xmm0
+; SSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: insert_reg_lo_v2i64:
 ; SSSE3:       # BB#0:
 ; SSSE3-NEXT:    movd %rdi, %xmm1
-; SSSE3-NEXT:    movsd %xmm1, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: insert_reg_lo_v2i64:
@@ -934,22 +950,22 @@ define <2 x i64> @insert_mem_lo_v2i64(i64* %ptr, <2 x i64> %b) {
 ;
 ; SSE41-LABEL: insert_mem_lo_v2i64:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    movq (%rdi), %xmm1
+; SSE41-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero
 ; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: insert_mem_lo_v2i64:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vmovq (%rdi), %xmm1
+; AVX1-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero
 ; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: insert_mem_lo_v2i64:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vmovq (%rdi), %xmm1
+; AVX2-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero
 ; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
 ; AVX2-NEXT:    retq
-  %a = load i64* %ptr
+  %a = load i64, i64* %ptr
   %v = insertelement <2 x i64> undef, i64 %a, i32 0
   %shuffle = shufflevector <2 x i64> %v, <2 x i64> %b, <2 x i32> <i32 0, i32 3>
   ret <2 x i64> %shuffle
@@ -975,16 +991,16 @@ define <2 x i64> @insert_reg_hi_v2i64(i64 %a, <2 x i64> %b) {
 define <2 x i64> @insert_mem_hi_v2i64(i64* %ptr, <2 x i64> %b) {
 ; SSE-LABEL: insert_mem_hi_v2i64:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movq (%rdi), %xmm1
+; SSE-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero
 ; SSE-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_mem_hi_v2i64:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovq (%rdi), %xmm1
+; AVX-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero
 ; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
 ; AVX-NEXT:    retq
-  %a = load i64* %ptr
+  %a = load i64, i64* %ptr
   %v = insertelement <2 x i64> undef, i64 %a, i32 0
   %shuffle = shufflevector <2 x i64> %v, <2 x i64> %b, <2 x i32> <i32 2, i32 0>
   ret <2 x i64> %shuffle
@@ -993,13 +1009,13 @@ define <2 x i64> @insert_mem_hi_v2i64(i64* %ptr, <2 x i64> %b) {
 define <2 x double> @insert_reg_lo_v2f64(double %a, <2 x double> %b) {
 ; SSE-LABEL: insert_reg_lo_v2f64:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movsd %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE-NEXT:    movapd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_reg_lo_v2f64:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovsd %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
 ; AVX-NEXT:    retq
   %v = insertelement <2 x double> undef, double %a, i32 0
   %shuffle = shufflevector <2 x double> %v, <2 x double> %b, <2 x i32> <i32 0, i32 3>
@@ -1016,7 +1032,7 @@ define <2 x double> @insert_mem_lo_v2f64(double* %ptr, <2 x double> %b) {
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vmovlpd (%rdi), %xmm0, %xmm0
 ; AVX-NEXT:    retq
-  %a = load double* %ptr
+  %a = load double, double* %ptr
   %v = insertelement <2 x double> undef, double %a, i32 0
   %shuffle = shufflevector <2 x double> %v, <2 x double> %b, <2 x i32> <i32 0, i32 3>
   ret <2 x double> %shuffle
@@ -1048,7 +1064,7 @@ define <2 x double> @insert_mem_hi_v2f64(double* %ptr, <2 x double> %b) {
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vmovhpd (%rdi), %xmm0, %xmm0
 ; AVX-NEXT:    retq
-  %a = load double* %ptr
+  %a = load double, double* %ptr
   %v = insertelement <2 x double> undef, double %a, i32 0
   %shuffle = shufflevector <2 x double> %v, <2 x double> %b, <2 x i32> <i32 2, i32 0>
   ret <2 x double> %shuffle
@@ -1064,22 +1080,22 @@ define <2 x double> @insert_dup_reg_v2f64(double %a) {
 ;
 ; SSE3-LABEL: insert_dup_reg_v2f64:
 ; SSE3:       # BB#0:
-; SSE3-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; SSE3-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: insert_dup_reg_v2f64:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; SSSE3-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: insert_dup_reg_v2f64:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; SSE41-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: insert_dup_reg_v2f64:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX-NEXT:    retq
   %v = insertelement <2 x double> undef, double %a, i32 0
   %shuffle = shufflevector <2 x double> %v, <2 x double> undef, <2 x i32> <i32 0, i32 0>
@@ -1088,30 +1104,30 @@ define <2 x double> @insert_dup_reg_v2f64(double %a) {
 define <2 x double> @insert_dup_mem_v2f64(double* %ptr) {
 ; SSE2-LABEL: insert_dup_mem_v2f64:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movsd (%rdi), %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE2-NEXT:    movlhps {{.*#+}} xmm0 = xmm0[0,0]
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: insert_dup_mem_v2f64:
 ; SSE3:       # BB#0:
-; SSE3-NEXT:    movddup (%rdi), %xmm0
+; SSE3-NEXT:    movddup {{.*#+}} xmm0 = mem[0,0]
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: insert_dup_mem_v2f64:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movddup (%rdi), %xmm0
+; SSSE3-NEXT:    movddup {{.*#+}} xmm0 = mem[0,0]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: insert_dup_mem_v2f64:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    movddup (%rdi), %xmm0
+; SSE41-NEXT:    movddup {{.*#+}} xmm0 = mem[0,0]
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: insert_dup_mem_v2f64:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovddup (%rdi), %xmm0
+; AVX-NEXT:    vmovddup {{.*#+}} xmm0 = mem[0,0]
 ; AVX-NEXT:    retq
-  %a = load double* %ptr
+  %a = load double, double* %ptr
   %v = insertelement <2 x double> undef, double %a, i32 0
   %shuffle = shufflevector <2 x double> %v, <2 x double> undef, <2 x i32> <i32 0, i32 0>
   ret <2 x double> %shuffle
@@ -1128,7 +1144,7 @@ define <2 x double> @shuffle_mem_v2f64_10(<2 x double>* %ptr) {
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vpermilpd {{.*#+}} xmm0 = mem[1,0]
 ; AVX-NEXT:    retq
-  %a = load <2 x double>* %ptr
+  %a = load <2 x double>, <2 x double>* %ptr
   %shuffle = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 1, i32 0>
   ret <2 x double> %shuffle
 }
diff --git a/test/CodeGen/X86/vector-shuffle-128-v4.ll b/test/CodeGen/X86/vector-shuffle-128-v4.ll
index 53fb09e32428..8612a5afa3d2 100644
--- a/test/CodeGen/X86/vector-shuffle-128-v4.ll
+++ b/test/CodeGen/X86/vector-shuffle-128-v4.ll
@@ -1,9 +1,9 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse3 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-unknown"
@@ -322,60 +322,150 @@ define <4 x i32> @shuffle_v4i32_0124(<4 x i32> %a, <4 x i32> %b) {
 ;
 ; SSE41-LABEL: shuffle_v4i32_0124:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,1,2,0]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
 ; SSE41-NEXT:    retq
 ;
-; AVX-LABEL: shuffle_v4i32_0124:
-; AVX:       # BB#0:
-; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
-; AVX-NEXT:    retq
+; AVX1-LABEL: shuffle_v4i32_0124:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,1,2,0]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v4i32_0124:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpbroadcastd %xmm1, %xmm1
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
+; AVX2-NEXT:    retq
   %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
   ret <4 x i32> %shuffle
 }
 define <4 x i32> @shuffle_v4i32_0142(<4 x i32> %a, <4 x i32> %b) {
-; SSE-LABEL: shuffle_v4i32_0142:
-; SSE:       # BB#0:
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
-; SSE-NEXT:    retq
+; SSE2-LABEL: shuffle_v4i32_0142:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
+; SSE2-NEXT:    retq
 ;
-; AVX-LABEL: shuffle_v4i32_0142:
-; AVX:       # BB#0:
-; AVX-NEXT:    vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
-; AVX-NEXT:    retq
+; SSE3-LABEL: shuffle_v4i32_0142:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
+; SSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
+; SSE3-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v4i32_0142:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v4i32_0142:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,2,2]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: shuffle_v4i32_0142:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,2,2]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v4i32_0142:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpbroadcastq %xmm1, %xmm1
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,2,2]
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
+; AVX2-NEXT:    retq
   %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
   ret <4 x i32> %shuffle
 }
 define <4 x i32> @shuffle_v4i32_0412(<4 x i32> %a, <4 x i32> %b) {
-; SSE-LABEL: shuffle_v4i32_0412:
-; SSE:       # BB#0:
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,2]
-; SSE-NEXT:    movaps %xmm1, %xmm0
-; SSE-NEXT:    retq
+; SSE2-LABEL: shuffle_v4i32_0412:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,2]
+; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    retq
 ;
-; AVX-LABEL: shuffle_v4i32_0412:
-; AVX:       # BB#0:
-; AVX-NEXT:    vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[1,2]
-; AVX-NEXT:    retq
+; SSE3-LABEL: shuffle_v4i32_0412:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
+; SSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,2]
+; SSE3-NEXT:    movaps %xmm1, %xmm0
+; SSE3-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v4i32_0412:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,2]
+; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v4i32_0412:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,1,2]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: shuffle_v4i32_0412:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,2]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v4i32_0412:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpbroadcastd %xmm1, %xmm1
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,2]
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
+; AVX2-NEXT:    retq
   %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 2>
   ret <4 x i32> %shuffle
 }
 define <4 x i32> @shuffle_v4i32_4012(<4 x i32> %a, <4 x i32> %b) {
-; SSE-LABEL: shuffle_v4i32_4012:
-; SSE:       # BB#0:
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,2]
-; SSE-NEXT:    movaps %xmm1, %xmm0
-; SSE-NEXT:    retq
+; SSE2-LABEL: shuffle_v4i32_4012:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,2]
+; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    retq
 ;
-; AVX-LABEL: shuffle_v4i32_4012:
-; AVX:       # BB#0:
-; AVX-NEXT:    vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[1,2]
-; AVX-NEXT:    retq
+; SSE3-LABEL: shuffle_v4i32_4012:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
+; SSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,2]
+; SSE3-NEXT:    movaps %xmm1, %xmm0
+; SSE3-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v4i32_4012:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,2]
+; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v4i32_4012:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,0,1,2]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: shuffle_v4i32_4012:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,2]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v4i32_4012:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,2]
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; AVX2-NEXT:    retq
   %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 0, i32 1, i32 2>
   ret <4 x i32> %shuffle
 }
@@ -393,17 +483,44 @@ define <4 x i32> @shuffle_v4i32_0145(<4 x i32> %a, <4 x i32> %b) {
   ret <4 x i32> %shuffle
 }
 define <4 x i32> @shuffle_v4i32_0451(<4 x i32> %a, <4 x i32> %b) {
-; SSE-LABEL: shuffle_v4i32_0451:
-; SSE:       # BB#0:
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,1]
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
-; SSE-NEXT:    retq
+; SSE2-LABEL: shuffle_v4i32_0451:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,3,2]
+; SSE2-NEXT:    retq
 ;
-; AVX-LABEL: shuffle_v4i32_0451:
-; AVX:       # BB#0:
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,1]
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
-; AVX-NEXT:    retq
+; SSE3-LABEL: shuffle_v4i32_0451:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,3,2]
+; SSE3-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v4i32_0451:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,3,2]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v4i32_0451:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5],xmm0[6,7]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: shuffle_v4i32_0451:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5],xmm0[6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v4i32_0451:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
+; AVX2-NEXT:    vpbroadcastq %xmm0, %xmm0
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]
+; AVX2-NEXT:    retq
   %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 1>
   ret <4 x i32> %shuffle
 }
@@ -422,17 +539,44 @@ define <4 x i32> @shuffle_v4i32_4501(<4 x i32> %a, <4 x i32> %b) {
   ret <4 x i32> %shuffle
 }
 define <4 x i32> @shuffle_v4i32_4015(<4 x i32> %a, <4 x i32> %b) {
-; SSE-LABEL: shuffle_v4i32_4015:
-; SSE:       # BB#0:
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,1]
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0,1,3]
-; SSE-NEXT:    retq
+; SSE2-LABEL: shuffle_v4i32_4015:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,0,2,3]
+; SSE2-NEXT:    retq
 ;
-; AVX-LABEL: shuffle_v4i32_4015:
-; AVX:       # BB#0:
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,1]
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[2,0,1,3]
-; AVX-NEXT:    retq
+; SSE3-LABEL: shuffle_v4i32_4015:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,0,2,3]
+; SSE3-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v4i32_4015:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,0,2,3]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v4i32_4015:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: shuffle_v4i32_4015:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v4i32_4015:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpbroadcastq %xmm1, %xmm1
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3]
+; AVX2-NEXT:    retq
   %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 0, i32 1, i32 5>
   ret <4 x i32> %shuffle
 }
@@ -441,21 +585,21 @@ define <4 x float> @shuffle_v4f32_4zzz(<4 x float> %a) {
 ; SSE2-LABEL: shuffle_v4f32_4zzz:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    xorps %xmm1, %xmm1
-; SSE2-NEXT:    movss %xmm0, %xmm1
+; SSE2-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE2-NEXT:    movaps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: shuffle_v4f32_4zzz:
 ; SSE3:       # BB#0:
 ; SSE3-NEXT:    xorps %xmm1, %xmm1
-; SSE3-NEXT:    movss %xmm0, %xmm1
+; SSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v4f32_4zzz:
 ; SSSE3:       # BB#0:
 ; SSSE3-NEXT:    xorps %xmm1, %xmm1
-; SSSE3-NEXT:    movss %xmm0, %xmm1
+; SSSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
@@ -478,22 +622,22 @@ define <4 x float> @shuffle_v4f32_z4zz(<4 x float> %a) {
 ; SSE2-LABEL: shuffle_v4f32_z4zz:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    xorps %xmm1, %xmm1
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0]
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: shuffle_v4f32_z4zz:
 ; SSE3:       # BB#0:
 ; SSE3-NEXT:    xorps %xmm1, %xmm1
-; SSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0]
-; SSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]
+; SSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
+; SSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v4f32_z4zz:
 ; SSSE3:       # BB#0:
 ; SSSE3-NEXT:    xorps %xmm1, %xmm1
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v4f32_z4zz:
@@ -513,24 +657,24 @@ define <4 x float> @shuffle_v4f32_zz4z(<4 x float> %a) {
 ; SSE2-LABEL: shuffle_v4f32_zz4z:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    xorps %xmm1, %xmm1
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
-; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,2]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2]
 ; SSE2-NEXT:    movaps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: shuffle_v4f32_zz4z:
 ; SSE3:       # BB#0:
 ; SSE3-NEXT:    xorps %xmm1, %xmm1
-; SSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
-; SSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,2]
+; SSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
+; SSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2]
 ; SSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v4f32_zz4z:
 ; SSSE3:       # BB#0:
 ; SSSE3-NEXT:    xorps %xmm1, %xmm1
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,2]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2]
 ; SSSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
@@ -657,25 +801,191 @@ define <4 x float> @shuffle_v4f32_z6zz(<4 x float> %a) {
   ret <4 x float> %shuffle
 }
 
+define <4 x float> @shuffle_v4f32_0z23(<4 x float> %a) {
+; SSE2-LABEL: shuffle_v4f32_0z23:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    xorps %xmm1, %xmm1
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
+; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE3-LABEL: shuffle_v4f32_0z23:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    xorps %xmm1, %xmm1
+; SSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
+; SSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
+; SSE3-NEXT:    movaps %xmm1, %xmm0
+; SSE3-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v4f32_0z23:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    xorps %xmm1, %xmm1
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
+; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v4f32_0z23:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    xorps %xmm1, %xmm1
+; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v4f32_0z23:
+; AVX:       # BB#0:
+; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
+; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
+  ret <4 x float> %shuffle
+}
+
+define <4 x float> @shuffle_v4f32_01z3(<4 x float> %a) {
+; SSE2-LABEL: shuffle_v4f32_01z3:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    xorps %xmm1, %xmm1
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
+; SSE2-NEXT:    retq
+;
+; SSE3-LABEL: shuffle_v4f32_01z3:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    xorps %xmm1, %xmm1
+; SSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
+; SSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
+; SSE3-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v4f32_01z3:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    xorps %xmm1, %xmm1
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v4f32_01z3:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    xorps %xmm1, %xmm1
+; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v4f32_01z3:
+; AVX:       # BB#0:
+; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
+; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
+  ret <4 x float> %shuffle
+}
+
+define <4 x float> @shuffle_v4f32_012z(<4 x float> %a) {
+; SSE2-LABEL: shuffle_v4f32_012z:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    xorps %xmm1, %xmm1
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
+; SSE2-NEXT:    retq
+;
+; SSE3-LABEL: shuffle_v4f32_012z:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    xorps %xmm1, %xmm1
+; SSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
+; SSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
+; SSE3-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v4f32_012z:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    xorps %xmm1, %xmm1
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v4f32_012z:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    xorps %xmm1, %xmm1
+; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v4f32_012z:
+; AVX:       # BB#0:
+; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
+; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+  ret <4 x float> %shuffle
+}
+
+define <4 x float> @shuffle_v4f32_0zz3(<4 x float> %a) {
+; SSE2-LABEL: shuffle_v4f32_0zz3:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    xorps %xmm1, %xmm1
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[1,2]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
+; SSE2-NEXT:    retq
+;
+; SSE3-LABEL: shuffle_v4f32_0zz3:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    xorps %xmm1, %xmm1
+; SSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[1,2]
+; SSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
+; SSE3-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v4f32_0zz3:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    xorps %xmm1, %xmm1
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[1,2]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v4f32_0zz3:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    xorps %xmm1, %xmm1
+; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v4f32_0zz3:
+; AVX:       # BB#0:
+; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
+; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 3>
+  ret <4 x float> %shuffle
+}
+
+define <4 x float> @shuffle_v4f32_u051(<4 x float> %a, <4 x float> %b) {
+; SSE-LABEL: shuffle_v4f32_u051:
+; SSE:       # BB#0:
+; SSE-NEXT:    unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v4f32_u051:
+; AVX:       # BB#0:
+; AVX-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 undef, i32 0, i32 5, i32 1>
+  ret <4 x float> %shuffle
+}
+
 define <4 x i32> @shuffle_v4i32_4zzz(<4 x i32> %a) {
 ; SSE2-LABEL: shuffle_v4i32_4zzz:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    xorps %xmm1, %xmm1
-; SSE2-NEXT:    movss %xmm0, %xmm1
+; SSE2-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE2-NEXT:    movaps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: shuffle_v4i32_4zzz:
 ; SSE3:       # BB#0:
 ; SSE3-NEXT:    xorps %xmm1, %xmm1
-; SSE3-NEXT:    movss %xmm0, %xmm1
+; SSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v4i32_4zzz:
 ; SSSE3:       # BB#0:
 ; SSSE3-NEXT:    xorps %xmm1, %xmm1
-; SSSE3-NEXT:    movss %xmm0, %xmm1
+; SSSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
@@ -698,21 +1008,21 @@ define <4 x i32> @shuffle_v4i32_z4zz(<4 x i32> %a) {
 ; SSE2-LABEL: shuffle_v4i32_z4zz:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    xorps %xmm1, %xmm1
-; SSE2-NEXT:    movss %xmm0, %xmm1
+; SSE2-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,0,1,1]
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: shuffle_v4i32_z4zz:
 ; SSE3:       # BB#0:
 ; SSE3-NEXT:    xorps %xmm1, %xmm1
-; SSE3-NEXT:    movss %xmm0, %xmm1
+; SSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,0,1,1]
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v4i32_z4zz:
 ; SSSE3:       # BB#0:
 ; SSSE3-NEXT:    xorps %xmm1, %xmm1
-; SSSE3-NEXT:    movss %xmm0, %xmm1
+; SSSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,0,1,1]
 ; SSSE3-NEXT:    retq
 ;
@@ -737,21 +1047,21 @@ define <4 x i32> @shuffle_v4i32_zz4z(<4 x i32> %a) {
 ; SSE2-LABEL: shuffle_v4i32_zz4z:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    xorps %xmm1, %xmm1
-; SSE2-NEXT:    movss %xmm0, %xmm1
+; SSE2-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,0,1]
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: shuffle_v4i32_zz4z:
 ; SSE3:       # BB#0:
 ; SSE3-NEXT:    xorps %xmm1, %xmm1
-; SSE3-NEXT:    movss %xmm0, %xmm1
+; SSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,0,1]
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v4i32_zz4z:
 ; SSSE3:       # BB#0:
 ; SSSE3-NEXT:    xorps %xmm1, %xmm1
-; SSSE3-NEXT:    movss %xmm0, %xmm1
+; SSSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,0,1]
 ; SSSE3-NEXT:    retq
 ;
@@ -810,13 +1120,24 @@ define <4 x i32> @shuffle_v4i32_z6zz(<4 x i32> %a) {
 ;
 ; SSE41-LABEL: shuffle_v4i32_z6zz:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    insertps {{.*#+}} xmm0 = zero,xmm0[2],zero,zero
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
+; SSE41-NEXT:    pxor %xmm0, %xmm0
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
 ; SSE41-NEXT:    retq
 ;
-; AVX-LABEL: shuffle_v4i32_z6zz:
-; AVX:       # BB#0:
-; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = zero,xmm0[2],zero,zero
-; AVX-NEXT:    retq
+; AVX1-LABEL: shuffle_v4i32_z6zz:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
+; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v4i32_z6zz:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
+; AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
+; AVX2-NEXT:    retq
   %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
   ret <4 x i32> %shuffle
 }
@@ -982,6 +1303,21 @@ define <4 x i32> @shuffle_v4i32_2345(<4 x i32> %a, <4 x i32> %b) {
   ret <4 x i32> %shuffle
 }
 
+define <4 x i32> @shuffle_v4i32_40u1(<4 x i32> %a, <4 x i32> %b) {
+; SSE-LABEL: shuffle_v4i32_40u1:
+; SSE:       # BB#0:
+; SSE-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE-NEXT:    movdqa %xmm1, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v4i32_40u1:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 0, i32 undef, i32 1>
+  ret <4 x i32> %shuffle
+}
+
 define <4 x i32> @shuffle_v4i32_3456(<4 x i32> %a, <4 x i32> %b) {
 ; SSE2-LABEL: shuffle_v4i32_3456:
 ; SSE2:       # BB#0:
@@ -1033,12 +1369,12 @@ define <4 x i32> @shuffle_v4i32_0u1u(<4 x i32> %a, <4 x i32> %b) {
 ;
 ; SSE41-LABEL: shuffle_v4i32_0u1u:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxdq %xmm0, %xmm0
+; SSE41-NEXT:    pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v4i32_0u1u:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpmovzxdq %xmm0, %xmm0
+; AVX-NEXT:    vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 undef, i32 1, i32 undef>
   ret <4 x i32> %shuffle
@@ -1065,17 +1401,196 @@ define <4 x i32> @shuffle_v4i32_0z1z(<4 x i32> %a) {
 ;
 ; SSE41-LABEL: shuffle_v4i32_0z1z:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxdq %xmm0, %xmm0
+; SSE41-NEXT:    pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v4i32_0z1z:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpmovzxdq %xmm0, %xmm0
+; AVX-NEXT:    vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
   ret <4 x i32> %shuffle
 }
 
+define <4 x i32> @shuffle_v4i32_01zu(<4 x i32> %a) {
+; SSE-LABEL: shuffle_v4i32_01zu:
+; SSE:       # BB#0:
+; SSE-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v4i32_01zu:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 7, i32 undef>
+  ret <4 x i32> %shuffle
+}
+
+define <4 x i32> @shuffle_v4i32_0z23(<4 x i32> %a) {
+; SSE2-LABEL: shuffle_v4i32_0z23:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE3-LABEL: shuffle_v4i32_0z23:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSE3-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v4i32_0z23:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v4i32_0z23:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pxor %xmm1, %xmm1
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: shuffle_v4i32_0z23:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v4i32_0z23:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
+  ret <4 x i32> %shuffle
+}
+
+define <4 x i32> @shuffle_v4i32_01z3(<4 x i32> %a) {
+; SSE2-LABEL: shuffle_v4i32_01z3:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE3-LABEL: shuffle_v4i32_01z3:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSE3-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v4i32_01z3:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v4i32_01z3:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pxor %xmm1, %xmm1
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: shuffle_v4i32_01z3:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v4i32_01z3:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
+  ret <4 x i32> %shuffle
+}
+
+define <4 x i32> @shuffle_v4i32_012z(<4 x i32> %a) {
+; SSE2-LABEL: shuffle_v4i32_012z:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE3-LABEL: shuffle_v4i32_012z:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSE3-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v4i32_012z:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v4i32_012z:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pxor %xmm1, %xmm1
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: shuffle_v4i32_012z:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v4i32_012z:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+  ret <4 x i32> %shuffle
+}
+
+define <4 x i32> @shuffle_v4i32_0zz3(<4 x i32> %a) {
+; SSE2-LABEL: shuffle_v4i32_0zz3:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE3-LABEL: shuffle_v4i32_0zz3:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSE3-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v4i32_0zz3:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v4i32_0zz3:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pxor %xmm1, %xmm1
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5],xmm0[6,7]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: shuffle_v4i32_0zz3:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5],xmm0[6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v4i32_0zz3:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 3>
+  ret <4 x i32> %shuffle
+}
+
+define <4 x i32> @shuffle_v4i32_bitcast_0415(<4 x i32> %a, <4 x i32> %b) {
+; SSE-LABEL: shuffle_v4i32_bitcast_0415:
+; SSE:       # BB#0:
+; SSE-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v4i32_bitcast_0415:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; AVX-NEXT:    retq
+  %shuffle32 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 0, i32 4>
+  %bitcast64 = bitcast <4 x i32> %shuffle32 to <2 x double>
+  %shuffle64 = shufflevector <2 x double> %bitcast64, <2 x double> undef, <2 x i32> <i32 1, i32 0>
+  %bitcast32 = bitcast <2 x double> %shuffle64 to <4 x i32>
+  ret <4 x i32> %bitcast32
+}
+
 define <4 x i32> @insert_reg_and_zero_v4i32(i32 %a) {
 ; SSE-LABEL: insert_reg_and_zero_v4i32:
 ; SSE:       # BB#0:
@@ -1094,14 +1609,14 @@ define <4 x i32> @insert_reg_and_zero_v4i32(i32 %a) {
 define <4 x i32> @insert_mem_and_zero_v4i32(i32* %ptr) {
 ; SSE-LABEL: insert_mem_and_zero_v4i32:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movd (%rdi), %xmm0
+; SSE-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_mem_and_zero_v4i32:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovd (%rdi), %xmm0
+; AVX-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-NEXT:    retq
-  %a = load i32* %ptr
+  %a = load i32, i32* %ptr
   %v = insertelement <4 x i32> undef, i32 %a, i32 0
   %shuffle = shufflevector <4 x i32> %v, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
   ret <4 x i32> %shuffle
@@ -1111,21 +1626,21 @@ define <4 x float> @insert_reg_and_zero_v4f32(float %a) {
 ; SSE2-LABEL: insert_reg_and_zero_v4f32:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    xorps %xmm1, %xmm1
-; SSE2-NEXT:    movss %xmm0, %xmm1
+; SSE2-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE2-NEXT:    movaps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: insert_reg_and_zero_v4f32:
 ; SSE3:       # BB#0:
 ; SSE3-NEXT:    xorps %xmm1, %xmm1
-; SSE3-NEXT:    movss %xmm0, %xmm1
+; SSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: insert_reg_and_zero_v4f32:
 ; SSSE3:       # BB#0:
 ; SSSE3-NEXT:    xorps %xmm1, %xmm1
-; SSSE3-NEXT:    movss %xmm0, %xmm1
+; SSSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
@@ -1138,7 +1653,7 @@ define <4 x float> @insert_reg_and_zero_v4f32(float %a) {
 ; AVX-LABEL: insert_reg_and_zero_v4f32:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
-; AVX-NEXT:    vmovss %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
 ; AVX-NEXT:    retq
   %v = insertelement <4 x float> undef, float %a, i32 0
   %shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
@@ -1148,14 +1663,14 @@ define <4 x float> @insert_reg_and_zero_v4f32(float %a) {
 define <4 x float> @insert_mem_and_zero_v4f32(float* %ptr) {
 ; SSE-LABEL: insert_mem_and_zero_v4f32:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movss (%rdi), %xmm0
+; SSE-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_mem_and_zero_v4f32:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovss (%rdi), %xmm0
+; AVX-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-NEXT:    retq
-  %a = load float* %ptr
+  %a = load float, float* %ptr
   %v = insertelement <4 x float> undef, float %a, i32 0
   %shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
   ret <4 x float> %shuffle
@@ -1165,19 +1680,19 @@ define <4 x i32> @insert_reg_lo_v4i32(i64 %a, <4 x i32> %b) {
 ; SSE2-LABEL: insert_reg_lo_v4i32:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    movd %rdi, %xmm1
-; SSE2-NEXT:    movsd %xmm1, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSE3-LABEL: insert_reg_lo_v4i32:
 ; SSE3:       # BB#0:
 ; SSE3-NEXT:    movd %rdi, %xmm1
-; SSE3-NEXT:    movsd %xmm1, %xmm0
+; SSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: insert_reg_lo_v4i32:
 ; SSSE3:       # BB#0:
 ; SSSE3-NEXT:    movd %rdi, %xmm1
-; SSSE3-NEXT:    movsd %xmm1, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: insert_reg_lo_v4i32:
@@ -1221,22 +1736,22 @@ define <4 x i32> @insert_mem_lo_v4i32(<2 x i32>* %ptr, <4 x i32> %b) {
 ;
 ; SSE41-LABEL: insert_mem_lo_v4i32:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    movq (%rdi), %xmm1
+; SSE41-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero
 ; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: insert_mem_lo_v4i32:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vmovq (%rdi), %xmm1
+; AVX1-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero
 ; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: insert_mem_lo_v4i32:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vmovq (%rdi), %xmm1
+; AVX2-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero
 ; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
 ; AVX2-NEXT:    retq
-  %a = load <2 x i32>* %ptr
+  %a = load <2 x i32>, <2 x i32>* %ptr
   %v = shufflevector <2 x i32> %a, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   %shuffle = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
   ret <4 x i32> %shuffle
@@ -1263,16 +1778,16 @@ define <4 x i32> @insert_reg_hi_v4i32(i64 %a, <4 x i32> %b) {
 define <4 x i32> @insert_mem_hi_v4i32(<2 x i32>* %ptr, <4 x i32> %b) {
 ; SSE-LABEL: insert_mem_hi_v4i32:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movq (%rdi), %xmm1
+; SSE-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero
 ; SSE-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_mem_hi_v4i32:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovq (%rdi), %xmm1
+; AVX-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero
 ; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
 ; AVX-NEXT:    retq
-  %a = load <2 x i32>* %ptr
+  %a = load <2 x i32>, <2 x i32>* %ptr
   %v = shufflevector <2 x i32> %a, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   %shuffle = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
   ret <4 x i32> %shuffle
@@ -1281,13 +1796,13 @@ define <4 x i32> @insert_mem_hi_v4i32(<2 x i32>* %ptr, <4 x i32> %b) {
 define <4 x float> @insert_reg_lo_v4f32(double %a, <4 x float> %b) {
 ; SSE-LABEL: insert_reg_lo_v4f32:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movsd %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE-NEXT:    movapd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: insert_reg_lo_v4f32:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovsd %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
 ; AVX-NEXT:    retq
   %a.cast = bitcast double %a to <2 x float>
   %v = shufflevector <2 x float> %a.cast, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
@@ -1305,7 +1820,7 @@ define <4 x float> @insert_mem_lo_v4f32(<2 x float>* %ptr, <4 x float> %b) {
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vmovlpd (%rdi), %xmm0, %xmm0
 ; AVX-NEXT:    retq
-  %a = load <2 x float>* %ptr
+  %a = load <2 x float>, <2 x float>* %ptr
   %v = shufflevector <2 x float> %a, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   %shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
   ret <4 x float> %shuffle
@@ -1338,7 +1853,7 @@ define <4 x float> @insert_mem_hi_v4f32(<2 x float>* %ptr, <4 x float> %b) {
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vmovhpd (%rdi), %xmm0, %xmm0
 ; AVX-NEXT:    retq
-  %a = load <2 x float>* %ptr
+  %a = load <2 x float>, <2 x float>* %ptr
   %v = shufflevector <2 x float> %a, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   %shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
   ret <4 x float> %shuffle
@@ -1355,7 +1870,39 @@ define <4 x float> @shuffle_mem_v4f32_3210(<4 x float>* %ptr) {
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vpermilps {{.*#+}} xmm0 = mem[3,2,1,0]
 ; AVX-NEXT:    retq
-  %a = load <4 x float>* %ptr
+  %a = load <4 x float>, <4 x float>* %ptr
   %shuffle = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   ret <4 x float> %shuffle
 }
+
+;
+; Shuffle to logical bit shifts
+;
+
+define <4 x i32> @shuffle_v4i32_z0zX(<4 x i32> %a) {
+; SSE-LABEL: shuffle_v4i32_z0zX:
+; SSE:       # BB#0:
+; SSE-NEXT:    psllq $32, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v4i32_z0zX:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsllq $32, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 0, i32 4, i32 undef>
+  ret <4 x i32> %shuffle
+}
+
+define <4 x i32> @shuffle_v4i32_1z3z(<4 x i32> %a) {
+; SSE-LABEL: shuffle_v4i32_1z3z:
+; SSE:       # BB#0:
+; SSE-NEXT:    psrlq $32, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v4i32_1z3z:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsrlq $32, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
+  ret <4 x i32> %shuffle
+}
diff --git a/test/CodeGen/X86/vector-shuffle-128-v8.ll b/test/CodeGen/X86/vector-shuffle-128-v8.ll
index de25a16a2e00..4007f0b2b13b 100644
--- a/test/CodeGen/X86/vector-shuffle-128-v8.ll
+++ b/test/CodeGen/X86/vector-shuffle-128-v8.ll
@@ -1,8 +1,8 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-unknown"
@@ -952,20 +952,15 @@ define <8 x i16> @shuffle_v8i16_109832ba(<8 x i16> %a, <8 x i16> %b) {
 ; SSE-LABEL: shuffle_v8i16_109832ba:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSE-NEXT:    pshuflw {{.*#+}} xmm1 = xmm0[2,0,3,1,4,5,6,7]
-; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
 ; SSE-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[2,0,3,1,4,5,6,7]
-; SSE-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; SSE-NEXT:    movdqa %xmm1, %xmm0
+; SSE-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,4,7,5]
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v8i16_109832ba:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm0[2,0,3,1,4,5,6,7]
-; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
 ; AVX-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[2,0,3,1,4,5,6,7]
-; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,4,7,5]
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 0, i32 9, i32 8, i32 3, i32 2, i32 11, i32 10>
   ret <8 x i16> %shuffle
@@ -1023,36 +1018,33 @@ define <8 x i16> @shuffle_v8i16_0213cedf(<8 x i16> %a, <8 x i16> %b) {
 define <8 x i16> @shuffle_v8i16_443aXXXX(<8 x i16> %a, <8 x i16> %b) {
 ; SSE2-LABEL: shuffle_v8i16_443aXXXX:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,3,4,5,6,7]
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,5,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [65535,65535,0,65535,65535,65535,65535,65535]
+; SSE2-NEXT:    pand %xmm2, %xmm0
+; SSE2-NEXT:    pandn %xmm1, %xmm2
+; SSE2-NEXT:    por %xmm0, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[2,1,2,3]
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,0,3,2,4,5,6,7]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v8i16_443aXXXX:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
-; SSSE3-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,3,4,5,6,7]
-; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,12,13,10,11,12,13,10,11,12,13,14,15]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,xmm1[4,5,u,u,u,u,u,u,u,u]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[8,9,8,9,6,7],zero,zero,xmm0[u,u,u,u,u,u,u,u]
+; SSSE3-NEXT:    por %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v8i16_443aXXXX:
 ; SSE41:       # BB#0:
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3,4,5,6,7]
 ; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
-; SSE41-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,3,4,5,6,7]
-; SSE41-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,12,13,10,11,12,13,10,11,12,13,14,15]
+; SSE41-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,0,3,2,4,5,6,7]
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v8i16_443aXXXX:
 ; AVX:       # BB#0:
+; AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3,4,5,6,7]
 ; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
-; AVX-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,2,3,4,5,6,7]
-; AVX-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,12,13,10,11,12,13,10,11,12,13,14,15]
+; AVX-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,3,2,4,5,6,7]
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 4, i32 3, i32 10, i32 undef, i32 undef, i32 undef, i32 undef>
   ret <8 x i16> %shuffle
@@ -1061,34 +1053,37 @@ define <8 x i16> @shuffle_v8i16_443aXXXX(<8 x i16> %a, <8 x i16> %b) {
 define <8 x i16> @shuffle_v8i16_032dXXXX(<8 x i16> %a, <8 x i16> %b) {
 ; SSE2-LABEL: shuffle_v8i16_032dXXXX:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,3,2,3,4,5,6,7]
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[3,1,2,0]
+; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,5,6,7]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
 ; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,3,2,1,4,5,6,7]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v8i16_032dXXXX:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,12,13,8,9,6,7,8,9,12,13,12,13,14,15]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,xmm1[10,11,u,u,u,u,u,u,u,u]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,6,7,4,5],zero,zero,xmm0[u,u,u,u,u,u,u,u]
+; SSSE3-NEXT:    por %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v8i16_032dXXXX:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; SSE41-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,12,13,8,9,6,7,8,9,12,13,12,13,14,15]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,6,7,4,5,10,11,0,1,10,11,0,1,2,3]
 ; SSE41-NEXT:    retq
 ;
-; AVX-LABEL: shuffle_v8i16_032dXXXX:
-; AVX:       # BB#0:
-; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; AVX-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,12,13,8,9,6,7,8,9,12,13,12,13,14,15]
-; AVX-NEXT:    retq
+; AVX1-LABEL: shuffle_v8i16_032dXXXX:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,6,7,4,5,10,11,0,1,10,11,0,1,2,3]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v8i16_032dXXXX:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,6,7,4,5,10,11,0,1,10,11,0,1,2,3]
+; AVX2-NEXT:    retq
   %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 3, i32 2, i32 13, i32 undef, i32 undef, i32 undef, i32 undef>
   ret <8 x i16> %shuffle
 }
@@ -1109,33 +1104,30 @@ define <8 x i16> @shuffle_v8i16_XXXdXXXX(<8 x i16> %a, <8 x i16> %b) {
 define <8 x i16> @shuffle_v8i16_012dXXXX(<8 x i16> %a, <8 x i16> %b) {
 ; SSE2-LABEL: shuffle_v8i16_012dXXXX:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[1,2,0,3,4,5,6,7]
+; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [65535,65535,65535,0,65535,65535,65535,65535]
+; SSE2-NEXT:    pand %xmm2, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
+; SSE2-NEXT:    pandn %xmm1, %xmm2
+; SSE2-NEXT:    por %xmm2, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v8i16_012dXXXX:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,6,7,8,9,0,1,0,1,2,3]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,xmm1[10,11,u,u,u,u,u,u,u,u]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],zero,zero,xmm0[u,u,u,u,u,u,u,u]
+; SSSE3-NEXT:    por %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v8i16_012dXXXX:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; SSE41-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,6,7,8,9,0,1,0,1,2,3]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v8i16_012dXXXX:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; AVX-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,6,7,8,9,0,1,0,1,2,3]
+; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
+; AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 undef, i32 undef, i32 undef, i32 undef>
   ret <8 x i16> %shuffle
@@ -1144,41 +1136,37 @@ define <8 x i16> @shuffle_v8i16_012dXXXX(<8 x i16> %a, <8 x i16> %b) {
 define <8 x i16> @shuffle_v8i16_XXXXcde3(<8 x i16> %a, <8 x i16> %b) {
 ; SSE2-LABEL: shuffle_v8i16_XXXXcde3:
 ; SSE2:       # BB#0:
+; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [65535,65535,65535,65535,65535,65535,65535,0]
+; SSE2-NEXT:    pand %xmm2, %xmm1
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
-; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm1[0,2,2,3,4,5,6,7]
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,7,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,2]
+; SSE2-NEXT:    pandn %xmm0, %xmm2
+; SSE2-NEXT:    por %xmm1, %xmm2
+; SSE2-NEXT:    movdqa %xmm2, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v8i16_XXXXcde3:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
-; SSSE3-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,4,5,6,7,0,1,4,5,8,9,14,15]
-; SSSE3-NEXT:    movdqa %xmm1, %xmm0
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[u,u,u,u,u,u,u,u],zero,zero,zero,zero,zero,zero,xmm0[6,7]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[u,u,u,u,u,u,u,u,8,9,10,11,12,13],zero,zero
+; SSSE3-NEXT:    por %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v8i16_XXXXcde3:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
-; SSE41-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; SSE41-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,4,5,6,7,0,1,4,5,8,9,14,15]
-; SSE41-NEXT:    movdqa %xmm1, %xmm0
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5,6],xmm0[7]
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: shuffle_v8i16_XXXXcde3:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
-; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,4,5,6,7,0,1,4,5,8,9,14,15]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5,6],xmm0[7]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v8i16_XXXXcde3:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vpbroadcastq %xmm0, %xmm0
-; AVX2-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,4,5,6,7,0,1,4,5,8,9,14,15]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5,6],xmm0[7]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 3>
   ret <8 x i16> %shuffle
@@ -1187,42 +1175,32 @@ define <8 x i16> @shuffle_v8i16_XXXXcde3(<8 x i16> %a, <8 x i16> %b) {
 define <8 x i16> @shuffle_v8i16_cde3XXXX(<8 x i16> %a, <8 x i16> %b) {
 ; SSE2-LABEL: shuffle_v8i16_cde3XXXX:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
-; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm1[0,2,2,3,4,5,6,7]
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,7,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [65535,65535,65535,0,65535,65535,65535,65535]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; SSE2-NEXT:    pand %xmm2, %xmm1
+; SSE2-NEXT:    pandn %xmm0, %xmm2
+; SSE2-NEXT:    por %xmm1, %xmm2
+; SSE2-NEXT:    movdqa %xmm2, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v8i16_cde3XXXX:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
-; SSSE3-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,14,15,8,9,14,15,12,13,14,15]
-; SSSE3-NEXT:    movdqa %xmm1, %xmm0
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,xmm0[6,7,u,u,u,u,u,u,u,u]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[8,9,10,11,12,13],zero,zero,xmm1[u,u,u,u,u,u,u,u]
+; SSSE3-NEXT:    por %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v8i16_cde3XXXX:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
-; SSE41-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; SSE41-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,14,15,8,9,14,15,12,13,14,15]
-; SSE41-NEXT:    movdqa %xmm1, %xmm0
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3],xmm1[4,5,6,7]
 ; SSE41-NEXT:    retq
 ;
-; AVX1-LABEL: shuffle_v8i16_cde3XXXX:
-; AVX1:       # BB#0:
-; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
-; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,14,15,8,9,14,15,12,13,14,15]
-; AVX1-NEXT:    retq
-;
-; AVX2-LABEL: shuffle_v8i16_cde3XXXX:
-; AVX2:       # BB#0:
-; AVX2-NEXT:    vpbroadcastq %xmm0, %xmm0
-; AVX2-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,14,15,8,9,14,15,12,13,14,15]
-; AVX2-NEXT:    retq
+; AVX-LABEL: shuffle_v8i16_cde3XXXX:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3],xmm1[4,5,6,7]
+; AVX-NEXT:    retq
   %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 12, i32 13, i32 14, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
   ret <8 x i16> %shuffle
 }
@@ -1230,100 +1208,117 @@ define <8 x i16> @shuffle_v8i16_cde3XXXX(<8 x i16> %a, <8 x i16> %b) {
 define <8 x i16> @shuffle_v8i16_012dcde3(<8 x i16> %a, <8 x i16> %b) {
 ; SSE2-LABEL: shuffle_v8i16_012dcde3:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[0,1,0,1]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
-; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,7,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
+; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[0,3,2,1]
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[3,1,2,0,4,5,6,7]
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[1,2,0,3,4,5,6,7]
-; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,3,2,1,4,5,6,7]
+; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,5,7]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,3,2,1]
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[1,3,0,2,4,5,6,7]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v8i16_012dcde3:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[0,1,0,1]
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
-; SSSE3-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,14,15,8,9,14,15,12,13,14,15]
-; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,6,7,8,9,0,1,0,1,2,3]
-; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,xmm1[10,11,8,9,10,11,12,13],zero,zero
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],zero,zero,zero,zero,zero,zero,zero,zero,xmm0[6,7]
+; SSSE3-NEXT:    por %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v8i16_012dcde3:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[0,1,0,1]
-; SSE41-NEXT:    pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
-; SSE41-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
-; SSE41-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,14,15,8,9,14,15,12,13,14,15]
-; SSE41-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
-; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,6,7,8,9,0,1,0,1,2,3]
-; SSE41-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,10,11,8,9,10,11,12,13,6,7]
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: shuffle_v8i16_012dcde3:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vpshufd {{.*#+}} xmm2 = xmm0[0,1,0,1]
-; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm2 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm2 = xmm2[0,1,4,5,8,9,14,15,8,9,14,15,12,13,14,15]
-; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,6,7,8,9,0,1,0,1,2,3]
-; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,10,11,8,9,10,11,12,13,6,7]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v8i16_012dcde3:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpbroadcastq %xmm0, %xmm2
-; AVX2-NEXT:    vpunpckhwd {{.*#+}} xmm2 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
-; AVX2-NEXT:    vpshufb {{.*#+}} xmm2 = xmm2[0,1,4,5,8,9,14,15,8,9,14,15,12,13,14,15]
-; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; AVX2-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,6,7,8,9,0,1,0,1,2,3]
-; AVX2-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,10,11,8,9,10,11,12,13,6,7]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 12, i32 13, i32 14, i32 3>
   ret <8 x i16> %shuffle
 }
 
+define <8 x i16> @shuffle_v8i16_0923cde7(<8 x i16> %a, <8 x i16> %b) {
+; SSE2-LABEL: shuffle_v8i16_0923cde7:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movaps {{.*#+}} xmm2 = [65535,0,65535,65535,0,0,0,65535]
+; SSE2-NEXT:    andps %xmm2, %xmm0
+; SSE2-NEXT:    andnps %xmm1, %xmm2
+; SSE2-NEXT:    orps %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v8i16_0923cde7:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    movaps {{.*#+}} xmm2 = [65535,0,65535,65535,0,0,0,65535]
+; SSSE3-NEXT:    andps %xmm2, %xmm0
+; SSSE3-NEXT:    andnps %xmm1, %xmm2
+; SSSE3-NEXT:    orps %xmm2, %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v8i16_0923cde7:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3],xmm1[4,5,6],xmm0[7]
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v8i16_0923cde7:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3],xmm1[4,5,6],xmm0[7]
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 9, i32 2, i32 3, i32 12, i32 13, i32 14, i32 7>
+  ret <8 x i16> %shuffle
+}
+
 define <8 x i16> @shuffle_v8i16_XXX1X579(<8 x i16> %a, <8 x i16> %b) {
 ; SSE2-LABEL: shuffle_v8i16_XXX1X579:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,5,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,1,3,2,4,5,6,7]
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,2,1]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,1,2,2,4,5,6,7]
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,4,5,7]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[0,1,2,0]
+; SSE2-NEXT:    movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535,65535,65535,65535,0]
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,1,2,1,4,5,6,7]
+; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,7,7]
+; SSE2-NEXT:    pand %xmm1, %xmm0
+; SSE2-NEXT:    pandn %xmm2, %xmm1
+; SSE2-NEXT:    por %xmm0, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v8i16_XXX1X579:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,10,11,14,15,14,15,10,11,12,13,14,15]
-; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,4,5,8,9,8,9,12,13,6,7]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[u,u,u,u,u,u],zero,zero,xmm1[u,u],zero,zero,zero,zero,xmm1[2,3]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[u,u,u,u,u,u,2,3,u,u,10,11,14,15],zero,zero
+; SSSE3-NEXT:    por %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v8i16_XXX1X579:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,10,11,14,15,14,15,10,11,12,13,14,15]
-; SSE41-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,4,5,8,9,8,9,12,13,6,7]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,1,2,0]
+; SSE41-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,1,2,1,4,5,6,7]
+; SSE41-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,7,7]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
 ; SSE41-NEXT:    retq
 ;
-; AVX-LABEL: shuffle_v8i16_XXX1X579:
-; AVX:       # BB#0:
-; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,10,11,14,15,14,15,10,11,12,13,14,15]
-; AVX-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,4,5,8,9,8,9,12,13,6,7]
-; AVX-NEXT:    retq
+; AVX1-LABEL: shuffle_v8i16_XXX1X579:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,1,2,0]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,1,2,1,4,5,6,7]
+; AVX1-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,7,7]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v8i16_XXX1X579:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpbroadcastd %xmm1, %xmm1
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,1,2,1,4,5,6,7]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,7,7]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
+; AVX2-NEXT:    retq
   %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 5, i32 7, i32 9>
   ret <8 x i16> %shuffle
 }
@@ -1331,42 +1326,40 @@ define <8 x i16> @shuffle_v8i16_XXX1X579(<8 x i16> %a, <8 x i16> %b) {
 define <8 x i16> @shuffle_v8i16_XX4X8acX(<8 x i16> %a, <8 x i16> %b) {
 ; SSE2-LABEL: shuffle_v8i16_XX4X8acX:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm1[0,1,2,0,4,5,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,2,1]
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,1,1,3,4,5,6,7]
-; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,4,7]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[2,2,3,3]
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm1[0,2,2,3,4,5,6,7]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,2,0]
+; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,7,4,7]
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: shuffle_v8i16_XX4X8acX:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
-; SSSE3-NEXT:    pshuflw {{.*#+}} xmm0 = xmm1[0,2,2,3,4,5,6,7]
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
-; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,2,3,0,1,0,1,4,5,8,9,0,1]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[u,u,u,u,8,9,u,u],zero,zero,zero,zero,zero,zero,xmm0[u,u]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[u,u,u,u],zero,zero,xmm1[u,u,0,1,4,5,8,9,u,u]
+; SSSE3-NEXT:    por %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: shuffle_v8i16_XX4X8acX:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
-; SSE41-NEXT:    pshuflw {{.*#+}} xmm0 = xmm1[0,2,2,3,4,5,6,7]
-; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; SSE41-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
-; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,2,3,0,1,0,1,4,5,8,9,0,1]
+; SSE41-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,4,5,6,7,0,1,4,5,8,9,4,5]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
 ; SSE41-NEXT:    retq
 ;
-; AVX-LABEL: shuffle_v8i16_XX4X8acX:
-; AVX:       # BB#0:
-; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
-; AVX-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
-; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
-; AVX-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,2,3,0,1,0,1,4,5,8,9,0,1]
-; AVX-NEXT:    retq
+; AVX1-LABEL: shuffle_v8i16_XX4X8acX:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,4,5,6,7,0,1,4,5,8,9,4,5]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v8i16_XX4X8acX:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,4,5,6,7,0,1,4,5,8,9,4,5]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
+; AVX2-NEXT:    retq
   %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 undef, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 undef>
   ret <8 x i16> %shuffle
 }
@@ -1391,16 +1384,14 @@ define <8 x i16> @shuffle_v8i16_8zzzzzzz(i16 %i) {
 define <8 x i16> @shuffle_v8i16_z8zzzzzz(i16 %i) {
 ; SSE-LABEL: shuffle_v8i16_z8zzzzzz:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movzwl %di, %eax
-; SSE-NEXT:    movd %eax, %xmm0
-; SSE-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
+; SSE-NEXT:    pxor   %xmm0, %xmm0
+; SSE-NEXT:    pinsrw $1, %edi, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v8i16_z8zzzzzz:
 ; AVX:       # BB#0:
-; AVX-NEXT:    movzwl %di, %eax
-; AVX-NEXT:    vmovd %eax, %xmm0
-; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
+; AVX-NEXT:    vpxor   %xmm0, %xmm0
+; AVX-NEXT:    vpinsrw $1, %edi, %xmm0
 ; AVX-NEXT:    retq
   %a = insertelement <8 x i16> undef, i16 %i, i32 0
   %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 2, i32 8, i32 3, i32 7, i32 6, i32 5, i32 4, i32 3>
@@ -1410,16 +1401,14 @@ define <8 x i16> @shuffle_v8i16_z8zzzzzz(i16 %i) {
 define <8 x i16> @shuffle_v8i16_zzzzz8zz(i16 %i) {
 ; SSE-LABEL: shuffle_v8i16_zzzzz8zz:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movzwl %di, %eax
-; SSE-NEXT:    movd %eax, %xmm0
-; SSE-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5]
+; SSE-NEXT:    pxor   %xmm0, %xmm0
+; SSE-NEXT:    pinsrw $5, %edi, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v8i16_zzzzz8zz:
 ; AVX:       # BB#0:
-; AVX-NEXT:    movzwl %di, %eax
-; AVX-NEXT:    vmovd %eax, %xmm0
-; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5]
+; AVX-NEXT:    vpxor   %xmm0, %xmm0
+; AVX-NEXT:    vpinsrw $5, %edi, %xmm0
 ; AVX-NEXT:    retq
   %a = insertelement <8 x i16> undef, i16 %i, i32 0
   %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 8, i32 0, i32 0>
@@ -1429,14 +1418,14 @@ define <8 x i16> @shuffle_v8i16_zzzzz8zz(i16 %i) {
 define <8 x i16> @shuffle_v8i16_zuuzuuz8(i16 %i) {
 ; SSE-LABEL: shuffle_v8i16_zuuzuuz8:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movd %edi, %xmm0
-; SSE-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1]
+; SSE-NEXT:    pxor   %xmm0, %xmm0
+; SSE-NEXT:    pinsrw $7, %edi, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v8i16_zuuzuuz8:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vmovd %edi, %xmm0
-; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1]
+; AVX-NEXT:    vpxor   %xmm0, %xmm0
+; AVX-NEXT:    vpinsrw $7, %edi, %xmm0
 ; AVX-NEXT:    retq
   %a = insertelement <8 x i16> undef, i16 %i, i32 0
   %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 0, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 6, i32 8>
@@ -1446,16 +1435,14 @@ define <8 x i16> @shuffle_v8i16_zuuzuuz8(i16 %i) {
 define <8 x i16> @shuffle_v8i16_zzBzzzzz(i16 %i) {
 ; SSE-LABEL: shuffle_v8i16_zzBzzzzz:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movzwl %di, %eax
-; SSE-NEXT:    movd %eax, %xmm0
-; SSE-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11]
+; SSE-NEXT:    pxor   %xmm0, %xmm0
+; SSE-NEXT:    pinsrw $2, %edi, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v8i16_zzBzzzzz:
 ; AVX:       # BB#0:
-; AVX-NEXT:    movzwl %di, %eax
-; AVX-NEXT:    vmovd %eax, %xmm0
-; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11]
+; AVX-NEXT:    vpxor   %xmm0, %xmm0
+; AVX-NEXT:    vpinsrw $2, %edi, %xmm0
 ; AVX-NEXT:    retq
   %a = insertelement <8 x i16> undef, i16 %i, i32 3
   %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 11, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -1829,12 +1816,12 @@ define <8 x i16> @shuffle_v8i16_0uuu1uuu(<8 x i16> %a) {
 ;
 ; SSE41-LABEL: shuffle_v8i16_0uuu1uuu:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxwq %xmm0, %xmm0
+; SSE41-NEXT:    pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v8i16_0uuu1uuu:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpmovzxwq %xmm0, %xmm0
+; AVX-NEXT:    vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 undef, i32 undef>
   ret <8 x i16> %shuffle
@@ -1857,12 +1844,12 @@ define <8 x i16> @shuffle_v8i16_0zzz1zzz(<8 x i16> %a) {
 ;
 ; SSE41-LABEL: shuffle_v8i16_0zzz1zzz:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxwq %xmm0, %xmm0
+; SSE41-NEXT:    pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v8i16_0zzz1zzz:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpmovzxwq %xmm0, %xmm0
+; AVX-NEXT:    vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 1, i32 13, i32 14, i32 15>
   ret <8 x i16> %shuffle
@@ -1881,12 +1868,12 @@ define <8 x i16> @shuffle_v8i16_0u1u2u3u(<8 x i16> %a) {
 ;
 ; SSE41-LABEL: shuffle_v8i16_0u1u2u3u:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxwd %xmm0, %xmm0
+; SSE41-NEXT:    pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v8i16_0u1u2u3u:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpmovzxwd %xmm0, %xmm0
+; AVX-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3, i32 undef>
   ret <8 x i16> %shuffle
@@ -1907,13 +1894,254 @@ define <8 x i16> @shuffle_v8i16_0z1z2z3z(<8 x i16> %a) {
 ;
 ; SSE41-LABEL: shuffle_v8i16_0z1z2z3z:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxwd %xmm0, %xmm0
+; SSE41-NEXT:    pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: shuffle_v8i16_0z1z2z3z:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpmovzxwd %xmm0, %xmm0
+; AVX-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
 ; AVX-NEXT:    retq
   %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 9, i32 1, i32 11, i32 2, i32 13, i32 3, i32 15>
   ret <8 x i16> %shuffle
 }
+
+;
+; Shuffle to logical bit shifts
+;
+define <8 x i16> @shuffle_v8i16_z0z2z4z6(<8 x i16> %a) {
+; SSE-LABEL: shuffle_v8i16_z0z2z4z6:
+; SSE:       # BB#0:
+; SSE-NEXT:    pslld $16, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v8i16_z0z2z4z6:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpslld $16, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 0, i32 8, i32 2, i32 8, i32 4, i32 8, i32 6>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_zzz0zzz4(<8 x i16> %a) {
+; SSE-LABEL: shuffle_v8i16_zzz0zzz4:
+; SSE:       # BB#0:
+; SSE-NEXT:    psllq $48, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v8i16_zzz0zzz4:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsllq $48, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 8, i32 8, i32 0, i32 8, i32 8, i32 8, i32 4>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_zz01zX4X(<8 x i16> %a) {
+; SSE-LABEL: shuffle_v8i16_zz01zX4X:
+; SSE:       # BB#0:
+; SSE-NEXT:    psllq $32, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v8i16_zz01zX4X:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsllq $32, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 8, i32 0, i32 1, i32 8, i32 undef, i32 4, i32 undef>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_z0X2z456(<8 x i16> %a) {
+; SSE-LABEL: shuffle_v8i16_z0X2z456:
+; SSE:       # BB#0:
+; SSE-NEXT:    psllq $16, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v8i16_z0X2z456:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsllq $16, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 0, i32 undef, i32 2, i32 8, i32 4, i32 5, i32 6>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_1z3zXz7z(<8 x i16> %a) {
+; SSE-LABEL: shuffle_v8i16_1z3zXz7z:
+; SSE:       # BB#0:
+; SSE-NEXT:    psrld $16, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v8i16_1z3zXz7z:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsrld $16, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 1, i32 8, i32 3, i32 8, i32 undef, i32 8, i32 7, i32 8>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_1X3z567z(<8 x i16> %a) {
+; SSE-LABEL: shuffle_v8i16_1X3z567z:
+; SSE:       # BB#0:
+; SSE-NEXT:    psrlq $16, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v8i16_1X3z567z:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsrlq $16, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 1, i32 undef, i32 3, i32 8, i32 5, i32 6, i32 7, i32 8>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_23zz67zz(<8 x i16> %a) {
+; SSE-LABEL: shuffle_v8i16_23zz67zz:
+; SSE:       # BB#0:
+; SSE-NEXT:    psrlq $32, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v8i16_23zz67zz:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsrlq $32, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 2, i32 3, i32 8, i32 8, i32 6, i32 7, i32 8, i32 8>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_3zXXXzzz(<8 x i16> %a) {
+; SSE-LABEL: shuffle_v8i16_3zXXXzzz:
+; SSE:       # BB#0:
+; SSE-NEXT:    psrlq $48, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v8i16_3zXXXzzz:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpsrlq $48, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 3, i32 8, i32 undef, i32 undef, i32 undef, i32 8, i32 8, i32 8>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_01u3zzuz(<8 x i16> %a) {
+; SSE-LABEL: shuffle_v8i16_01u3zzuz:
+; SSE:       # BB#0:
+; SSE-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v8i16_01u3zzuz:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 undef, i32 3, i32 8, i32 8, i32 undef, i32 8>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_0z234567(<8 x i16> %a) {
+; SSE2-LABEL: shuffle_v8i16_0z234567:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v8i16_0z234567:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v8i16_0z234567:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pxor %xmm1, %xmm1
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6,7]
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v8i16_0z234567:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6,7]
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_0zzzz5z7(<8 x i16> %a) {
+; SSE2-LABEL: shuffle_v8i16_0zzzz5z7:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v8i16_0zzzz5z7:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v8i16_0zzzz5z7:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pxor %xmm1, %xmm1
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4],xmm0[5],xmm1[6],xmm0[7]
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v8i16_0zzzz5z7:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4],xmm0[5],xmm1[6],xmm0[7]
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 8, i32 8, i32 8, i32 5, i32 8, i32 7>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_0123456z(<8 x i16> %a) {
+; SSE2-LABEL: shuffle_v8i16_0123456z:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: shuffle_v8i16_0123456z:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuffle_v8i16_0123456z:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pxor %xmm1, %xmm1
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6],xmm1[7]
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v8i16_0123456z:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6],xmm1[7]
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_fu3ucc5u(<8 x i16> %a, <8 x i16> %b) {
+; SSE-LABEL: shuffle_v8i16_fu3ucc5u:
+; SSE:       # BB#0:
+; SSE-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
+; SSE-NEXT:    pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,5,4,4]
+; SSE-NEXT:    punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; SSE-NEXT:    movdqa %xmm1, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v8i16_fu3ucc5u:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
+; AVX-NEXT:    vpshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,5,4,4]
+; AVX-NEXT:    vpunpckhdq {{.*#+}} xmm0 = xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 15, i32 undef, i32 3, i32 undef, i32 12, i32 12, i32 5, i32 undef>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_8012345u(<8 x i16> %a) {
+; SSE-LABEL: shuffle_v8i16_8012345u:
+; SSE:       # BB#0:
+; SSE-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: shuffle_v8i16_8012345u:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
+; AVX-NEXT:    retq
+  %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 8, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 undef>
+
+  ret <8 x i16> %shuffle
+}
diff --git a/test/CodeGen/X86/vector-shuffle-256-v16.ll b/test/CodeGen/X86/vector-shuffle-256-v16.ll
index 7c38149a700c..df4994da6932 100644
--- a/test/CodeGen/X86/vector-shuffle-256-v16.ll
+++ b/test/CodeGen/X86/vector-shuffle-256-v16.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mcpu=x86-64 -mattr=+avx -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX1
-; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX2
+; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX1
+; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX2
 
 target triple = "x86_64-unknown-unknown"
 
@@ -151,9 +151,7 @@ define <16 x i16> @shuffle_v16i16_00_00_00_00_00_00_00_08_00_00_00_00_00_00_00_0
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,1,4,5,6,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,0,1,0,1,0,1,0,1,0,1,0,1,2,3]
 ; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
@@ -161,7 +159,7 @@ define <16 x i16> @shuffle_v16i16_00_00_00_00_00_00_00_08_00_00_00_00_00_00_00_0
 ; AVX2-LABEL: shuffle_v16i16_00_00_00_00_00_00_00_08_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,0,1,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
 ; AVX2-NEXT:    vpbroadcastw %xmm0, %ymm0
 ; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
 ; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
@@ -175,9 +173,7 @@ define <16 x i16> @shuffle_v16i16_00_00_00_00_00_00_09_00_00_00_00_00_00_00_00_0
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,0,3,0,4,5,6,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,0,1,0,1,0,1,0,1,0,1,6,7,0,1]
 ; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
@@ -185,10 +181,9 @@ define <16 x i16> @shuffle_v16i16_00_00_00_00_00_00_09_00_00_00_00_00_00_00_00_0
 ; AVX2-LABEL: shuffle_v16i16_00_00_00_00_00_00_09_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,2,3,u,u,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
-; AVX2-NEXT:    vpbroadcastw %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
+; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = <0,0,255,255,u,u,u,u,u,u,u,u,u,u,u,u,255,255,u,u,u,u,u,u,u,u,u,u,u,u,u,u>
 ; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,0,1,0,1,0,1,0,1,0,1,2,3,0,1,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 9, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <16 x i16> %shuffle
@@ -199,10 +194,7 @@ define <16 x i16> @shuffle_v16i16_00_00_00_00_00_10_00_00_00_00_00_00_00_00_00_0
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,3,0,0,4,5,6,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,0,1,0,1,0,1,0,1,10,11,0,1,0,1]
 ; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
@@ -210,10 +202,8 @@ define <16 x i16> @shuffle_v16i16_00_00_00_00_00_10_00_00_00_00_00_00_00_00_00_0
 ; AVX2-LABEL: shuffle_v16i16_00_00_00_00_00_10_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,4,5,u,u,u,u,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
-; AVX2-NEXT:    vpbroadcastw %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,0,1,0,1,0,1,0,1,4,5,0,1,0,1,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <16 x i16> %shuffle
@@ -224,10 +214,7 @@ define <16 x i16> @shuffle_v16i16_00_00_00_00_11_00_00_00_00_00_00_00_00_00_00_0
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,3,2,3]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[3,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,0,1,0,1,0,1,14,15,0,1,0,1,0,1]
 ; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
@@ -235,10 +222,8 @@ define <16 x i16> @shuffle_v16i16_00_00_00_00_11_00_00_00_00_00_00_00_00_00_00_0
 ; AVX2-LABEL: shuffle_v16i16_00_00_00_00_11_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,6,7,u,u,u,u,u,u,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
-; AVX2-NEXT:    vpbroadcastw %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,0,1,0,1,0,1,6,7,0,1,0,1,0,1,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 11, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <16 x i16> %shuffle
@@ -248,11 +233,8 @@ define <16 x i16> @shuffle_v16i16_00_00_00_12_00_00_00_00_00_00_00_00_00_00_00_0
 ; AVX1-LABEL: shuffle_v16i16_00_00_00_12_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,1,4,5,6,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,0,1,0,1,8,9,0,1,0,1,0,1,0,1]
 ; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
@@ -260,10 +242,8 @@ define <16 x i16> @shuffle_v16i16_00_00_00_12_00_00_00_00_00_00_00_00_00_00_00_0
 ; AVX2-LABEL: shuffle_v16i16_00_00_00_12_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,8,9,u,u,u,u,u,u,u,u,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
-; AVX2-NEXT:    vpbroadcastw %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,0,1,0,1,8,9,0,1,0,1,0,1,0,1,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 0, i32 0, i32 12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <16 x i16> %shuffle
@@ -273,11 +253,8 @@ define <16 x i16> @shuffle_v16i16_00_00_13_00_00_00_00_00_00_00_00_00_00_00_00_0
 ; AVX1-LABEL: shuffle_v16i16_00_00_13_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,0,3,0,4,5,6,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,0,1,10,11,0,1,0,1,0,1,0,1,0,1]
 ; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
@@ -285,10 +262,8 @@ define <16 x i16> @shuffle_v16i16_00_00_13_00_00_00_00_00_00_00_00_00_00_00_00_0
 ; AVX2-LABEL: shuffle_v16i16_00_00_13_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,10,11,u,u,u,u,u,u,u,u,u,u,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
-; AVX2-NEXT:    vpbroadcastw %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,0,1,10,11,0,1,0,1,0,1,0,1,0,1,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 0, i32 13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <16 x i16> %shuffle
@@ -298,12 +273,8 @@ define <16 x i16> @shuffle_v16i16_00_14_00_00_00_00_00_00_00_00_00_00_00_00_00_0
 ; AVX1-LABEL: shuffle_v16i16_00_14_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,3,0,0,4,5,6,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,12,13,0,1,0,1,0,1,0,1,0,1,0,1]
 ; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
@@ -311,10 +282,8 @@ define <16 x i16> @shuffle_v16i16_00_14_00_00_00_00_00_00_00_00_00_00_00_00_00_0
 ; AVX2-LABEL: shuffle_v16i16_00_14_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,12,13,u,u,u,u,u,u,u,u,u,u,u,u,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
-; AVX2-NEXT:    vpbroadcastw %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,12,13,0,1,0,1,0,1,0,1,0,1,0,1,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 14, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <16 x i16> %shuffle
@@ -324,12 +293,8 @@ define <16 x i16> @shuffle_v16i16_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_0
 ; AVX1-LABEL: shuffle_v16i16_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,3,2,3]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[3,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[14,15,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
 ; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
@@ -337,10 +302,8 @@ define <16 x i16> @shuffle_v16i16_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_0
 ; AVX2-LABEL: shuffle_v16i16_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[14,15,u,u,u,u,u,u,u,u,u,u,u,u,u,u,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
-; AVX2-NEXT:    vpbroadcastw %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[14,15,0,1,0,1,0,1,0,1,0,1,0,1,0,1,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <16 x i16> %shuffle
@@ -395,7 +358,8 @@ define <16 x i16> @shuffle_v16i16_00_00_00_00_04_04_04_04_08_08_08_08_12_12_12_1
 ;
 ; AVX2-LABEL: shuffle_v16i16_00_00_00_00_04_04_04_04_08_08_08_08_12_12_12_12:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,0,1,0,1,0,1,8,9,8,9,8,9,8,9,16,17,16,17,16,17,16,17,24,25,24,25,24,25,24,25]
+; AVX2-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[0,0,0,0,4,5,6,7,8,8,8,8,12,13,14,15]
+; AVX2-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,4,4,4,8,9,10,11,12,12,12,12]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4, i32 8, i32 8, i32 8, i32 8, i32 12, i32 12, i32 12, i32 12>
   ret <16 x i16> %shuffle
@@ -414,7 +378,8 @@ define <16 x i16> @shuffle_v16i16_03_03_03_03_07_07_07_07_11_11_11_11_15_15_15_1
 ;
 ; AVX2-LABEL: shuffle_v16i16_03_03_03_03_07_07_07_07_11_11_11_11_15_15_15_15:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[6,7,6,7,6,7,6,7,14,15,14,15,14,15,14,15,22,23,22,23,22,23,22,23,30,31,30,31,30,31,30,31]
+; AVX2-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[3,3,3,3,4,5,6,7,11,11,11,11,12,13,14,15]
+; AVX2-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,7,7,7,8,9,10,11,15,15,15,15]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 3, i32 3, i32 3, i32 3, i32 7, i32 7, i32 7, i32 7, i32 11, i32 11, i32 11, i32 11, i32 15, i32 15, i32 15, i32 15>
   ret <16 x i16> %shuffle
@@ -433,7 +398,8 @@ define <16 x i16> @shuffle_v16i16_00_00_02_02_04_04_06_06_08_08_10_10_12_12_14_1
 ;
 ; AVX2-LABEL: shuffle_v16i16_00_00_02_02_04_04_06_06_08_08_10_10_12_12_14_14:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,0,1,4,5,4,5,8,9,8,9,12,13,12,13,16,17,16,17,20,21,20,21,24,25,24,25,28,29,28,29]
+; AVX2-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[0,0,2,2,4,5,6,7,8,8,10,10,12,13,14,15]
+; AVX2-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,4,6,6,8,9,10,11,12,12,14,14]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
   ret <16 x i16> %shuffle
@@ -452,7 +418,8 @@ define <16 x i16> @shuffle_v16i16_01_01_03_03_05_05_07_07_09_09_11_11_13_13_15_1
 ;
 ; AVX2-LABEL: shuffle_v16i16_01_01_03_03_05_05_07_07_09_09_11_11_13_13_15_15:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15,18,19,18,19,22,23,22,23,26,27,26,27,30,31,30,31]
+; AVX2-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[1,1,3,3,4,5,6,7,9,9,11,11,12,13,14,15]
+; AVX2-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,5,5,7,7,8,9,10,11,13,13,15,15]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
   ret <16 x i16> %shuffle
@@ -724,9 +691,8 @@ define <16 x i16> @shuffle_v16i16_00_01_18_19_20_21_06_07_08_09_26_27_12_13_30_3
 define <16 x i16> @shuffle_v16i16_00_16_00_16_00_16_00_16_00_16_00_16_00_16_00_16(<16 x i16> %a, <16 x i16> %b) {
 ; AVX1-LABEL: shuffle_v16i16_00_16_00_16_00_16_00_16_00_16_00_16_00_16_00_16:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
 ; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -743,20 +709,18 @@ define <16 x i16> @shuffle_v16i16_00_16_00_16_00_16_00_16_00_16_00_16_00_16_00_1
 define <16 x i16> @shuffle_v16i16_00_16_00_16_00_16_00_16_08_24_08_24_08_24_08_24(<16 x i16> %a, <16 x i16> %b) {
 ; AVX1-LABEL: shuffle_v16i16_00_16_00_16_00_16_00_16_08_24_08_24_08_24_08_24:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm2 = xmm2[0,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm3 = xmm3[0,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm2 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm2 = xmm2[0,0,0,0]
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
 ; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm2, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v16i16_00_16_00_16_00_16_00_16_08_24_08_24_08_24_08_24:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,0,1,u,u,0,1,u,u,0,1,u,u,0,1,u,u,16,17,u,u,16,17,u,u,16,17,u,u,16,17]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[0,1,0,1,4,5,0,1,0,1,0,1,12,13,0,1,16,17,16,17,20,21,16,17,16,17,16,17,28,29,16,17]
 ; AVX2-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[0,0,0,0,4,4,4,4]
 ; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
 ; AVX2-NEXT:    retq
@@ -780,7 +744,7 @@ define <16 x i16> @shuffle_v16i16_16_16_16_16_04_05_06_07_24_24_24_24_12_13_14_1
 ;
 ; AVX2-LABEL: shuffle_v16i16_16_16_16_16_04_05_06_07_24_24_24_24_12_13_14_15:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[0,1,0,1,0,1,0,1,u,u,u,u,u,u,u,u,16,17,16,17,16,17,16,17,u,u,u,u,u,u,u,u]
+; AVX2-NEXT:    vpshuflw {{.*#+}} ymm1 = ymm1[0,0,0,0,4,5,6,7,8,8,8,8,12,13,14,15]
 ; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 4, i32 5, i32 6, i32 7, i32 24, i32 24, i32 24, i32 24, i32 12, i32 13, i32 14, i32 15>
@@ -805,9 +769,9 @@ define <16 x i16> @shuffle_v16i16_19_18_17_16_07_06_05_04_27_26_25_24_15_14_13_1
 ;
 ; AVX2-LABEL: shuffle_v16i16_19_18_17_16_07_06_05_04_27_26_25_24_15_14_13_12:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[u,u,u,u,u,u,u,u,14,15,12,13,10,11,8,9,u,u,u,u,u,u,u,u,30,31,28,29,26,27,24,25]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[6,7,4,5,2,3,0,1,u,u,u,u,u,u,u,u,22,23,20,21,18,19,16,17,u,u,u,u,u,u,u,u]
 ; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
+; AVX2-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[3,2,1,0,4,5,6,7,11,10,9,8,12,13,14,15]
+; AVX2-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,6,5,4,8,9,10,11,15,14,13,12]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 19, i32 18, i32 17, i32 16, i32 7, i32 6, i32 5, i32 4, i32 27, i32 26, i32 25, i32 24, i32 15, i32 14, i32 13, i32 12>
   ret <16 x i16> %shuffle
@@ -817,20 +781,20 @@ define <16 x i16> @shuffle_v16i16_19_18_17_16_03_02_01_00_27_26_25_24_11_10_09_0
 ; AVX1-LABEL: shuffle_v16i16_19_18_17_16_03_02_01_00_27_26_25_24_11_10_09_08:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7]
 ; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm3 = xmm3[3,2,1,0,4,5,6,7]
-; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[3,2,1,0,4,5,6,7]
-; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3]
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm3 = [12,13,8,9,4,5,0,1,14,15,10,11,6,7,2,3]
+; AVX1-NEXT:    vpshufb %xmm3, %xmm2, %xmm2
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; AVX1-NEXT:    vpshufb %xmm3, %xmm0, %xmm0
 ; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v16i16_19_18_17_16_03_02_01_00_27_26_25_24_11_10_09_08:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[u,u,u,u,u,u,u,u,6,7,4,5,2,3,0,1,u,u,u,u,u,u,u,u,22,23,20,21,18,19,16,17]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[6,7,4,5,2,3,0,1,u,u,u,u,u,u,u,u,22,23,20,21,18,19,16,17,u,u,u,u,u,u,u,u]
+; AVX2-NEXT:    vpshuflw {{.*#+}} ymm1 = ymm1[3,2,1,0,4,5,6,7,11,10,9,8,12,13,14,15]
+; AVX2-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[0,1,0,1,4,5,4,5]
+; AVX2-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,6,5,4,8,9,10,11,15,14,13,12]
 ; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 19, i32 18, i32 17, i32 16, i32 3, i32 2, i32 1, i32 0, i32 27, i32 26, i32 25, i32 24, i32 11, i32 10, i32 9, i32 8>
@@ -1278,7 +1242,8 @@ define <16 x i16> @shuffle_v16i16_00_00_00_00_04_04_04_04_16_16_16_16_20_20_20_2
 ; AVX2-LABEL: shuffle_v16i16_00_00_00_00_04_04_04_04_16_16_16_16_20_20_20_20:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,0,1,0,1,0,1,8,9,8,9,8,9,8,9,16,17,16,17,16,17,16,17,24,25,24,25,24,25,24,25]
+; AVX2-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[0,0,0,0,4,5,6,7,8,8,8,8,12,13,14,15]
+; AVX2-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,4,4,4,8,9,10,11,12,12,12,12]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4, i32 16, i32 16, i32 16, i32 16, i32 20, i32 20, i32 20, i32 20>
   ret <16 x i16> %shuffle
@@ -1298,7 +1263,8 @@ define <16 x i16> @shuffle_v16i16_08_08_08_08_12_12_12_12_16_16_16_16_20_20_20_2
 ; AVX2-LABEL: shuffle_v16i16_08_08_08_08_12_12_12_12_16_16_16_16_20_20_20_20:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,0,1,0,1,0,1,8,9,8,9,8,9,8,9,16,17,16,17,16,17,16,17,24,25,24,25,24,25,24,25]
+; AVX2-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[0,0,0,0,4,5,6,7,8,8,8,8,12,13,14,15]
+; AVX2-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,4,4,4,8,9,10,11,12,12,12,12]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 8, i32 8, i32 8, i32 8, i32 12, i32 12, i32 12, i32 12, i32 16, i32 16, i32 16, i32 16, i32 20, i32 20, i32 20, i32 20>
   ret <16 x i16> %shuffle
@@ -1319,7 +1285,8 @@ define <16 x i16> @shuffle_v16i16_08_08_08_08_12_12_12_12_24_24_24_24_28_28_28_2
 ; AVX2-LABEL: shuffle_v16i16_08_08_08_08_12_12_12_12_24_24_24_24_28_28_28_28:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,0,1,0,1,0,1,8,9,8,9,8,9,8,9,16,17,16,17,16,17,16,17,24,25,24,25,24,25,24,25]
+; AVX2-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[0,0,0,0,4,5,6,7,8,8,8,8,12,13,14,15]
+; AVX2-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,4,4,4,8,9,10,11,12,12,12,12]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 8, i32 8, i32 8, i32 8, i32 12, i32 12, i32 12, i32 12, i32 24, i32 24, i32 24, i32 24, i32 28, i32 28, i32 28, i32 28>
   ret <16 x i16> %shuffle
@@ -1339,7 +1306,8 @@ define <16 x i16> @shuffle_v16i16_00_00_00_00_04_04_04_04_24_24_24_24_28_28_28_2
 ; AVX2-LABEL: shuffle_v16i16_00_00_00_00_04_04_04_04_24_24_24_24_28_28_28_28:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,0,1,0,1,0,1,8,9,8,9,8,9,8,9,16,17,16,17,16,17,16,17,24,25,24,25,24,25,24,25]
+; AVX2-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[0,0,0,0,4,5,6,7,8,8,8,8,12,13,14,15]
+; AVX2-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,4,4,4,8,9,10,11,12,12,12,12]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4, i32 24, i32 24, i32 24, i32 24, i32 28, i32 28, i32 28, i32 28>
   ret <16 x i16> %shuffle
@@ -1362,3 +1330,1934 @@ define <16 x i16> @shuffle_v16i16_00_16_01_17_02_18_03_19_04_20_05_21_06_22_07_2
   %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
   ret <16 x i16> %shuffle
 }
+
+define <16 x i16> @shuffle_v16i16_zz_zz_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_24(<16 x i16> %a) {
+; AVX1-LABEL: shuffle_v16i16_zz_zz_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_24:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1]
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_zz_zz_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_24:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[0,1],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> zeroinitializer, <16 x i16> %a, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 24>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_17_18_19_20_21_22_23_zz_25_26_27_28_29_30_31_zz(<16 x i16> %a) {
+; AVX1-LABEL: shuffle_v16i16_17_18_19_20_21_22_23_zz_25_26_27_28_29_30_31_zz:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpsrldq {{.*#+}} xmm1 = xmm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpsrldq {{.*#+}} xmm0 = xmm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_17_18_19_20_21_22_23_zz_25_26_27_28_29_30_31_zz:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpsrldq {{.*#+}} ymm0 = ymm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,ymm0[18,19,20,21,22,23,24,25,26,27,28,29,30,31],zero,zero
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> zeroinitializer, <16 x i16> %a, <16 x i32> <i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 0, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0>
+  ret <16 x i16> %shuffle
+}
+
+;
+; Shuffle to logical bit shifts
+;
+
+define <16 x i16> @shuffle_v16i16_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_14(<16 x i16> %a) {
+; AVX1-LABEL: shuffle_v16i16_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_14:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpslld $16, %xmm0, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpslld $16, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_14:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpslld $16, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 16, i32 0, i32 16, i32 2, i32 16, i32 4, i32 16, i32 6, i32 16, i32 8, i32 16, i32 10, i32 16, i32 12, i32 16, i32 14>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_zz_zz_zz_00_zz_zz_zz_04_zz_zz_zz_08_zz_zz_zz_12(<16 x i16> %a) {
+; AVX1-LABEL: shuffle_v16i16_zz_zz_zz_00_zz_zz_zz_04_zz_zz_zz_08_zz_zz_zz_12:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpsllq $48, %xmm0, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpsllq $48, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_zz_zz_zz_00_zz_zz_zz_04_zz_zz_zz_08_zz_zz_zz_12:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpsllq $48, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 4, i32 16, i32 16, i32 16, i32 8, i32 16, i32 16, i32 16, i32 12>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_01_zz_03_zz_05_zz_07_zz_09_zz_11_zz_13_zz_15_zz(<16 x i16> %a) {
+; AVX1-LABEL: shuffle_v16i16_01_zz_03_zz_05_zz_07_zz_09_zz_11_zz_13_zz_15_zz:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpsrld $16, %xmm0, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpsrld $16, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_01_zz_03_zz_05_zz_07_zz_09_zz_11_zz_13_zz_15_zz:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpsrld $16, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 1, i32 16, i32 3, i32 16, i32 5, i32 16, i32 7, i32 16, i32 9, i32 16, i32 11, i32 16, i32 13, i32 16, i32 15, i32 16>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_zz(<16 x i16> %a) {
+; AVX1-LABEL: shuffle_v16i16_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_zz:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vxorps %ymm1, %ymm1, %ymm1
+; AVX1-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7]
+; AVX1-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[0,2,1,3,4,6,5,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_zz:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpsrlq $32, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 2, i32 3, i32 16, i32 16, i32 6, i32 7, i32 16, i32 16, i32 10, i32 11, i32 16, i32 16, i32 14, i32 15, i32 16, i32 16>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_16_zz_zz_zz_17_zz_zz_zz_18_zz_zz_zz_19_zz_zz_zz(<16 x i16> %a) {
+; AVX1-LABEL: shuffle_v16i16_16_zz_zz_zz_17_zz_zz_zz_18_zz_zz_zz_19_zz_zz_zz:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm0[4,5,2,3,4,5,6,7,6,7,10,11,4,5,6,7]
+; AVX1-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3],xmm1[4],xmm2[5,6,7]
+; AVX1-NEXT:    vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_16_zz_zz_zz_17_zz_zz_zz_18_zz_zz_zz_19_zz_zz_zz:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> zeroinitializer, <16 x i16> %a, <16 x i32> <i32 16, i32 0, i32 0, i32 0, i32 17, i32 0, i32 0, i32 0, i32 18, i32 0, i32 0, i32 0, i32 19, i32 0, i32 0, i32 0>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_16_zz_17_zz_18_zz_19_zz_20_zz_21_zz_22_zz_22_zz(<16 x i16> %a) {
+; AVX1-LABEL: shuffle_v16i16_16_zz_17_zz_18_zz_19_zz_20_zz_21_zz_22_zz_22_zz:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; AVX1-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_16_zz_17_zz_18_zz_19_zz_20_zz_21_zz_22_zz_22_zz:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> zeroinitializer, <16 x i16> %a, <16 x i32> <i32 16, i32 0, i32 17, i32 0, i32 18, i32 0, i32 19, i32 0, i32 20, i32 0, i32 21, i32 0, i32 22, i32 0, i32 23, i32 0>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_23_00_01_02_03_04_05_06_31_08_09_10_11_12_13_14(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_23_00_01_02_03_04_05_06_31_08_09_10_11_12_13_14:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[14,15],xmm3[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm1[14,15],xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_23_00_01_02_03_04_05_06_31_08_09_10_11_12_13_14:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm1[14,15],ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13],ymm1[30,31],ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28,29]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 23, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_01_02_03_04_05_06_07_16_09_10_11_12_13_14_15_24(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_01_02_03_04_05_06_07_16_09_10_11_12_13_14_15_24:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[2,3,4,5,6,7,8,9,10,11,12,13,14,15],xmm3[0,1]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],xmm1[0,1]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_01_02_03_04_05_06_07_16_09_10_11_12_13_14_15_24:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0,1],ymm0[18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16,17]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 24>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_17_18_19_20_21_22_23_00_25_26_27_28_29_30_31_8(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_17_18_19_20_21_22_23_00_25_26_27_28_29_30_31_8:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[2,3,4,5,6,7,8,9,10,11,12,13,14,15],xmm3[0,1]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm1[2,3,4,5,6,7,8,9,10,11,12,13,14,15],xmm0[0,1]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_17_18_19_20_21_22_23_00_25_26_27_28_29_30_31_8:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm1[2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm0[0,1],ymm1[18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm0[16,17]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 00, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 8>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_07_16_17_18_19_20_21_22_15_24_25_26_27_28_29_30(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_07_16_17_18_19_20_21_22_15_24_25_26_27_28_29_30:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[14,15],xmm3[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[14,15],xmm1[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_07_16_17_18_19_20_21_22_15_24_25_26_27_28_29_30:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[14,15],ymm1[0,1,2,3,4,5,6,7,8,9,10,11,12,13],ymm0[30,31],ymm1[16,17,18,19,20,21,22,23,24,25,26,27,28,29]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 15, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_01_02_03_04_05_06_07_00_17_18_19_20_21_22_23_16(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_01_02_03_04_05_06_07_00_17_18_19_20_21_22_23_16:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,1]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,1]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_01_02_03_04_05_06_07_00_17_18_19_20_21_22_23_16:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,1,18,19,20,21,22,23,24,25,26,27,28,29,30,31,16,17]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 16>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_07_00_01_02_03_04_05_06_23_16_17_18_19_20_21_22(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_07_00_01_02_03_04_05_06_23_16_17_18_19_20_21_22:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[14,15,0,1,2,3,4,5,6,7,8,9,10,11,12,13]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[14,15,0,1,2,3,4,5,6,7,8,9,10,11,12,13]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_07_00_01_02_03_04_05_06_23_16_17_18_19_20_21_22:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[14,15,0,1,2,3,4,5,6,7,8,9,10,11,12,13,30,31,16,17,18,19,20,21,22,23,24,25,26,27,28,29]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 23, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_01_00_01_02_03_02_11_08_09_08_09_10_11_10_11(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_01_00_01_02_03_02_11_08_09_08_09_10_11_10_11:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,2,0,2,4,5,6,7]
+; AVX1-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,4,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_01_00_01_02_03_02_11_08_09_08_09_10_11_10_11:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,2,0,2,4,5,6,7]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,4,7]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 3, i32 2, i32 11, i32 8, i32 9, i32 8, i32 9, i32 10, i32 11, i32 10, i32 11>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_06_07_04_05_02_03_00_09_14_15_12_13_10_11_08_09(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_06_07_04_05_02_03_00_09_14_15_12_13_10_11_08_09:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_06_07_04_05_02_03_00_09_14_15_12_13_10_11_08_09:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 6, i32 7, i32 4, i32 5, i32 2, i32 3, i32 0, i32 9, i32 14, i32 15, i32 12, i32 13, i32 10, i32 11, i32 8, i32 9>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_04_05_06_07_16_17_18_27_12_13_14_15_24_25_26_27(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_04_05_06_07_16_17_18_27_12_13_14_15_24_25_26_27:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[8,9,10,11,12,13,14,15],xmm3[0,1,2,3,4,5,6,7]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,4,5,6,7,0,1,4,5,8,9,14,15]
+; AVX1-NEXT:    vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_04_05_06_07_16_17_18_27_12_13_14_15_24_25_26_27:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 27, i32 12, i32 13, i32 14, i32 15, i32 24, i32 25, i32 26, i32 27>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_00_00_00_00_00_00_08_08_08_08_08_08_08_08_08(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_00_00_00_00_00_00_08_08_08_08_08_08_08_08_08:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,2,3]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_00_00_00_00_00_00_08_08_08_08_08_08_08_08_08:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,2,3]
+; AVX2-NEXT:    vpbroadcastw %xmm1, %xmm1
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_00_00_00_04_04_04_12_08_08_08_08_12_12_12_12(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_00_00_00_04_04_04_12_08_08_08_08_12_12_12_12:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
+; AVX1-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,4,4,7]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
+; AVX1-NEXT:    vpshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,4,4,4]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_00_00_00_04_04_04_12_08_08_08_08_12_12_12_12:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,4,4,7]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,4,4,4]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 12, i32 8, i32 8, i32 8, i32 8, i32 12, i32 12, i32 12, i32 12>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_00_uu_01_uu_02_uu_11_uu_08_uu_09_uu_10_uu_11(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_00_uu_01_uu_02_uu_11_uu_08_uu_09_uu_10_uu_11:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,2,2,4,5,6,7]
+; AVX1-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,4,6,7]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_00_uu_01_uu_02_uu_11_uu_08_uu_09_uu_10_uu_11:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,2,2,4,5,6,7]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,4,6,7]
+; AVX2-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 11, i32 undef, i32 8, i32 undef, i32 9, i32 undef, i32 10, i32 undef, i32 11>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_04_uu_05_uu_06_uu_15_uu_12_uu_13_uu_14_uu_15(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_04_uu_05_uu_06_uu_15_uu_12_uu_13_uu_14_uu_15:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,2,2,4,5,6,7]
+; AVX1-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,4,6,7]
+; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_04_uu_05_uu_06_uu_15_uu_12_uu_13_uu_14_uu_15:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,2,2,4,5,6,7]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,4,6,7]
+; AVX2-NEXT:    vpunpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 15, i32 undef, i32 12, i32 undef, i32 13, i32 undef, i32 14, i32 undef, i32 15>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_03_01_02_00_06_07_04_13_11_09_10_08_14_15_12_13(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_03_01_02_00_06_07_04_13_11_09_10_08_14_15_12_13:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4],xmm1[5],xmm0[6,7]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[3,1,2,0,4,5,6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,3,2]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[3,1,2,0,4,5,6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,1,3,2]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_03_01_02_00_06_07_04_13_11_09_10_08_14_15_12_13:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4],xmm1[5],xmm0[6,7]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[3,1,2,0,4,5,6,7]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,3,2]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[3,1,2,0,4,5,6,7]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,1,3,2]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 3, i32 1, i32 2, i32 0, i32 6, i32 7, i32 4, i32 13, i32 11, i32 9, i32 10, i32 8, i32 14, i32 15, i32 12, i32 13>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_04_04_04_04_00_00_00_08_12_12_12_12_08_08_08_08(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_04_04_04_04_00_00_00_08_12_12_12_12_08_08_08_08:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[8,9,8,9,8,9,8,9,0,1,0,1,0,1,14,15]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[8,9,8,9,8,9,8,9,0,1,0,1,0,1,0,1]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_04_04_04_04_00_00_00_08_12_12_12_12_08_08_08_08:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpbroadcastw %xmm1, %xmm2
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[8,9,8,9,8,9,8,9,0,1,0,1,0,1,14,15]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[8,9,8,9,8,9,8,9,0,1,0,1,0,1,0,1]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 4, i32 4, i32 4, i32 4, i32 0, i32 0, i32 0, i32 8, i32 12, i32 12, i32 12, i32 12, i32 8, i32 8, i32 8, i32 8>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_02_03_00_01_06_07_04_13_10_11_08_09_14_15_12_13(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_02_03_00_01_06_07_04_13_10_11_08_09_14_15_12_13:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4],xmm1[5],xmm0[6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,2]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[1,0,3,2]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_02_03_00_01_06_07_04_13_10_11_08_09_14_15_12_13:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4],xmm1[5],xmm0[6,7]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,2]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[1,0,3,2]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 2, i32 3, i32 0, i32 1, i32 6, i32 7, i32 4, i32 13, i32 10, i32 11, i32 8, i32 9, i32 14, i32 15, i32 12, i32 13>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_02_03_00_02_06_07_04_13_10_11_08_10_14_15_12_13(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_02_03_00_02_06_07_04_13_10_11_08_10_14_15_12_13:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4],xmm1[5],xmm0[6,7]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[2,3,0,2,4,5,6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,3,2]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[2,3,0,2,4,5,6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,1,3,2]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_02_03_00_02_06_07_04_13_10_11_08_10_14_15_12_13:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4],xmm1[5],xmm0[6,7]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[2,3,0,2,4,5,6,7]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,3,2]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[2,3,0,2,4,5,6,7]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,1,3,2]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 2, i32 3, i32 0, i32 2, i32 6, i32 7, i32 4, i32 13, i32 10, i32 11, i32 8, i32 10, i32 14, i32 15, i32 12, i32 13>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_02_03_00_01_06_07_04_15_10_11_08_09_14_15_12_15(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_02_03_00_01_06_07_04_15_10_11_08_09_14_15_12_15:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,2]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[1,0,2,3]
+; AVX1-NEXT:    vpshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,6,7,4,7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_02_03_00_01_06_07_04_15_10_11_08_09_14_15_12_15:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,2]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[1,0,2,3]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,6,7,4,7]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 2, i32 3, i32 0, i32 1, i32 6, i32 7, i32 4, i32 15, i32 10, i32 11, i32 8, i32 9, i32 14, i32 15, i32 12, i32 15>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_07_05_06_04_03_01_02_08_15_13_14_12_11_09_10_08(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_07_05_06_04_03_01_02_08_15_13_14_12_11_09_10_08:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [14,15,10,11,12,13,8,9,6,7,2,3,4,5,0,1]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm1, %xmm3
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5,6,7]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_07_05_06_04_03_01_02_08_15_13_14_12_11_09_10_08:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vmovdqa {{.*#+}} xmm2 = [14,15,10,11,12,13,8,9,6,7,2,3,4,5,0,1]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm1, %xmm3
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX2-NEXT:    vinserti128 $1, %xmm3, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 7, i32 5, i32 6, i32 4, i32 3, i32 1, i32 2, i32 8, i32 15, i32 13, i32 14, i32 12, i32 11, i32 9, i32 10, i32 8>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_01_00_05_04_05_04_01_08_09_08_13_12_13_12_09_08(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_01_00_05_04_05_04_01_08_09_08_13_12_13_12_09_08:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[2,3,0,1,10,11,8,9,10,11,8,9,2,3,2,3]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[2,3,0,1,10,11,8,9,10,11,8,9,2,3,0,1]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_01_00_05_04_05_04_01_08_09_08_13_12_13_12_09_08:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpbroadcastw %xmm1, %xmm2
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[2,3,0,1,10,11,8,9,10,11,8,9,2,3,2,3]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[2,3,0,1,10,11,8,9,10,11,8,9,2,3,0,1]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 1, i32 0, i32 5, i32 4, i32 5, i32 4, i32 1, i32 8, i32 9, i32 8, i32 13, i32 12, i32 13, i32 12, i32 9, i32 8>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_05_04_01_00_05_04_01_08_13_12_09_08_13_12_09_08(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_05_04_01_00_05_04_01_08_13_12_09_08_13_12_09_08:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[10,11,8,9,2,3,0,1,10,11,8,9,2,3,2,3]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[10,11,8,9,2,3,0,1,10,11,8,9,2,3,0,1]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_05_04_01_00_05_04_01_08_13_12_09_08_13_12_09_08:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpbroadcastw %xmm1, %xmm2
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[10,11,8,9,2,3,0,1,10,11,8,9,2,3,2,3]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[10,11,8,9,2,3,0,1,10,11,8,9,2,3,0,1]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 5, i32 4, i32 1, i32 0, i32 5, i32 4, i32 1, i32 8, i32 13, i32 12, i32 9, i32 8, i32 13, i32 12, i32 9, i32 8>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_05_04_01_00_01_00_05_12_13_12_09_08_09_08_13_12(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_05_04_01_00_01_00_05_12_13_12_09_08_09_08_13_12:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[10,11,8,9,2,3,0,1,2,3,0,1,10,11,2,3]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[10,11,8,9,2,3,0,1,2,3,0,1,10,11,8,9]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_05_04_01_00_01_00_05_12_13_12_09_08_09_08_13_12:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[10,11,8,9,2,3,0,1,2,3,0,1,10,11,2,3]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[10,11,8,9,2,3,0,1,2,3,0,1,10,11,8,9]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 5, i32 4, i32 1, i32 0, i32 1, i32 0, i32 5, i32 12, i32 13, i32 12, i32 9, i32 8, i32 9, i32 8, i32 13, i32 12>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_04_04_00_00_04_04_08_08_12_12_08_08_12_12_08(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_04_04_00_00_04_04_08_08_12_12_08_08_12_12_08:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,8,9,8,9,0,1,0,1,8,9,8,9,2,3]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,8,9,8,9,0,1,0,1,8,9,8,9,0,1]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_04_04_00_00_04_04_08_08_12_12_08_08_12_12_08:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpbroadcastw %xmm1, %xmm2
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,8,9,8,9,0,1,0,1,8,9,8,9,2,3]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,8,9,8,9,0,1,0,1,8,9,8,9,0,1]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 4, i32 4, i32 0, i32 0, i32 4, i32 4, i32 8, i32 8, i32 12, i32 12, i32 8, i32 8, i32 12, i32 12, i32 8>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_04_00_00_04_04_00_00_12_12_08_08_12_12_08_08_12(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_04_00_00_04_04_00_00_12_12_08_08_12_12_08_08_12:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[8,9,0,1,0,1,8,9,8,9,0,1,0,1,2,3]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[8,9,0,1,0,1,8,9,8,9,0,1,0,1,8,9]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_04_00_00_04_04_00_00_12_12_08_08_12_12_08_08_12:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[8,9,0,1,0,1,8,9,8,9,0,1,0,1,2,3]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[8,9,0,1,0,1,8,9,8,9,0,1,0,1,8,9]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 4, i32 0, i32 0, i32 4, i32 4, i32 0, i32 0, i32 12, i32 12, i32 8, i32 8, i32 12, i32 12, i32 8, i32 8, i32 12>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_02_06_04_00_05_01_07_11_10_14_12_08_13_09_15_11(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_02_06_04_00_05_01_07_11_10_14_12_08_13_09_15_11:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [4,5,12,13,8,9,0,1,10,11,2,3,14,15,6,7]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm1, %xmm3
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_02_06_04_00_05_01_07_11_10_14_12_08_13_09_15_11:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vmovdqa {{.*#+}} xmm2 = [4,5,12,13,8,9,0,1,10,11,2,3,14,15,6,7]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm1, %xmm3
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX2-NEXT:    vinserti128 $1, %xmm3, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 2, i32 6, i32 4, i32 0, i32 5, i32 1, i32 7, i32 11, i32 10, i32 14, i32 12, i32 8, i32 13, i32 9, i32 15, i32 11>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_02_00_06_04_05_01_07_11_10_08_14_12_13_09_15_11(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_02_00_06_04_05_01_07_11_10_08_14_12_13_09_15_11:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [4,5,0,1,12,13,8,9,10,11,2,3,14,15,6,7]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm1, %xmm3
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_02_00_06_04_05_01_07_11_10_08_14_12_13_09_15_11:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vmovdqa {{.*#+}} xmm2 = [4,5,0,1,12,13,8,9,10,11,2,3,14,15,6,7]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm1, %xmm3
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX2-NEXT:    vinserti128 $1, %xmm3, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 2, i32 0, i32 6, i32 4, i32 5, i32 1, i32 7, i32 11, i32 10, i32 8, i32 14, i32 12, i32 13, i32 9, i32 15, i32 11>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_02_06_04_00_01_03_07_13_10_14_12_08_09_11_15_13(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_02_06_04_00_01_03_07_13_10_14_12_08_09_11_15_13:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [4,5,12,13,8,9,0,1,2,3,6,7,14,15,10,11]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm1, %xmm3
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4],xmm1[5],xmm0[6,7]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_02_06_04_00_01_03_07_13_10_14_12_08_09_11_15_13:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vmovdqa {{.*#+}} xmm2 = [4,5,12,13,8,9,0,1,2,3,6,7,14,15,10,11]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm1, %xmm3
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4],xmm1[5],xmm0[6,7]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX2-NEXT:    vinserti128 $1, %xmm3, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 2, i32 6, i32 4, i32 0, i32 1, i32 3, i32 7, i32 13, i32 10, i32 14, i32 12, i32 8, i32 9, i32 11, i32 15, i32 13>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_06_06_07_05_01_06_04_11_14_14_15_13_09_14_12_11(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_06_06_07_05_01_06_04_11_14_14_15_13_09_14_12_11:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [12,13,12,13,14,15,10,11,2,3,12,13,8,9,6,7]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm1, %xmm3
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_06_06_07_05_01_06_04_11_14_14_15_13_09_14_12_11:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vmovdqa {{.*#+}} xmm2 = [12,13,12,13,14,15,10,11,2,3,12,13,8,9,6,7]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm1, %xmm3
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX2-NEXT:    vinserti128 $1, %xmm3, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 6, i32 6, i32 7, i32 5, i32 1, i32 6, i32 4, i32 11, i32 14, i32 14, i32 15, i32 13, i32 9, i32 14, i32 12, i32 11>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_00_04_04_04_04_04_12_08_08_12_12_12_12_12_12(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_00_04_04_04_04_04_12_08_08_12_12_12_12_12_12:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,0,1,8,9,8,9,8,9,8,9,8,9,14,15]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,0,1,8,9,8,9,8,9,8,9,8,9,8,9]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_00_04_04_04_04_04_12_08_08_12_12_12_12_12_12:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,0,1,8,9,8,9,8,9,8,9,8,9,14,15]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,0,1,8,9,8,9,8,9,8,9,8,9,8,9]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 0, i32 4, i32 4, i32 4, i32 4, i32 4, i32 12, i32 8, i32 8, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_04_04_00_00_04_04_04_12_12_12_08_08_12_12_12_12(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_04_04_00_00_04_04_04_12_12_12_08_08_12_12_12_12:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[8,9,8,9,0,1,0,1,8,9,8,9,8,9,14,15]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[8,9,8,9,0,1,0,1,8,9,8,9,8,9,8,9]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_04_04_00_00_04_04_04_12_12_12_08_08_12_12_12_12:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[8,9,8,9,0,1,0,1,8,9,8,9,8,9,14,15]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[8,9,8,9,0,1,0,1,8,9,8,9,8,9,8,9]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 4, i32 4, i32 0, i32 0, i32 4, i32 4, i32 4, i32 12, i32 12, i32 12, i32 8, i32 8, i32 12, i32 12, i32 12, i32 12>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_04_04_00_04_04_04_12_08_12_12_08_12_12_12_12(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_04_04_00_04_04_04_12_08_12_12_08_12_12_12_12:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,8,9,8,9,0,1,8,9,8,9,8,9,14,15]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,8,9,8,9,0,1,8,9,8,9,8,9,8,9]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_04_04_00_04_04_04_12_08_12_12_08_12_12_12_12:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,8,9,8,9,0,1,8,9,8,9,8,9,14,15]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,8,9,8,9,0,1,8,9,8,9,8,9,8,9]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 4, i32 4, i32 0, i32 4, i32 4, i32 4, i32 12, i32 8, i32 12, i32 12, i32 8, i32 12, i32 12, i32 12, i32 12>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_04_04_00_00_00_00_08_08_12_12_08_08_08_08_08(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_04_04_00_00_00_00_08_08_12_12_08_08_08_08_08:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,8,9,8,9,0,1,0,1,0,1,0,1,14,15]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,8,9,8,9,0,1,0,1,0,1,0,1,0,1]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_04_04_00_00_00_00_08_08_12_12_08_08_08_08_08:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpbroadcastw %xmm1, %xmm2
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,8,9,8,9,0,1,0,1,0,1,0,1,14,15]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,8,9,8,9,0,1,0,1,0,1,0,1,0,1]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 4, i32 4, i32 0, i32 0, i32 0, i32 0, i32 8, i32 8, i32 12, i32 12, i32 8, i32 8, i32 8, i32 8, i32 8>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_04_04_00_04_05_06_15_08_12_12_08_12_13_14_15(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_04_04_00_04_05_06_15_08_12_12_08_12_13_14_15:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,0,4,5,6,7]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,2,2,0,4,5,6,7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_04_04_00_04_05_06_15_08_12_12_08_12_13_14_15:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,0,4,5,6,7]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,2,2,0,4,5,6,7]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 4, i32 4, i32 0, i32 4, i32 5, i32 6, i32 15, i32 8, i32 12, i32 12, i32 8, i32 12, i32 13, i32 14, i32 15>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_uu_04_04_04_04_04_12_08_uu_12_12_12_12_12_12(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_uu_04_04_04_04_04_12_08_uu_12_12_12_12_12_12:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,8,9,8,9,8,9,8,9,8,9,14,15]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,2,3,8,9,8,9,8,9,8,9,8,9,8,9]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_uu_04_04_04_04_04_12_08_uu_12_12_12_12_12_12:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,8,9,8,9,8,9,8,9,8,9,14,15]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,2,3,8,9,8,9,8,9,8,9,8,9,8,9]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 undef, i32 4, i32 4, i32 4, i32 4, i32 4, i32 12, i32 8, i32 undef, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_04_04_uu_00_04_04_04_12_12_12_uu_08_12_12_12_12(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_04_04_uu_00_04_04_04_12_12_12_uu_08_12_12_12_12:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[8,9,8,9,8,9,0,1,8,9,8,9,8,9,14,15]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[8,9,8,9,8,9,0,1,8,9,8,9,8,9,8,9]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_04_04_uu_00_04_04_04_12_12_12_uu_08_12_12_12_12:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[8,9,8,9,8,9,0,1,8,9,8,9,8,9,14,15]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[8,9,8,9,8,9,0,1,8,9,8,9,8,9,8,9]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 4, i32 4, i32 undef, i32 0, i32 4, i32 4, i32 4, i32 12, i32 12, i32 12, i32 undef, i32 8, i32 12, i32 12, i32 12, i32 12>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_04_04_00_04_04_04_12_uu_12_12_08_12_12_12_12(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_04_04_00_04_04_04_12_uu_12_12_08_12_12_12_12:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,8,9,8,9,0,1,8,9,8,9,8,9,14,15]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,8,9,8,9,0,1,8,9,8,9,8,9,8,9]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_04_04_00_04_04_04_12_uu_12_12_08_12_12_12_12:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpsllq $48, %xmm1, %xmm2
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,8,9,8,9,0,1,8,9,8,9,8,9,14,15]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,8,9,8,9,0,1,8,9,8,9,8,9,8,9]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 4, i32 4, i32 0, i32 4, i32 4, i32 4, i32 12, i32 undef, i32 12, i32 12, i32 8, i32 12, i32 12, i32 12, i32 12>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_01_02_07_uu_uu_uu_uu_08_09_10_15_uu_uu_uu_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_01_02_07_uu_uu_uu_uu_08_09_10_15_uu_uu_uu_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,14,15,4,5,14,15,12,13,14,15]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
+; AVX1-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_01_02_07_uu_uu_uu_uu_08_09_10_15_uu_uu_uu_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,14,15,4,5,14,15,12,13,14,15,16,17,18,19,20,21,30,31,20,21,30,31,28,29,30,31]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 10, i32 15, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_uu_uu_uu_04_05_06_11_uu_uu_uu_uu_12_13_14_11(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_uu_uu_uu_04_05_06_11_uu_uu_uu_uu_12_13_14_11:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm2 = xmm1[0,1,0,1]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[12,13,6,7,4,5,6,7,8,9,10,11,12,13,6,7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_uu_uu_uu_04_05_06_11_uu_uu_uu_uu_12_13_14_11:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpbroadcastq %xmm1, %xmm2
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[12,13,6,7,4,5,6,7,8,9,10,11,12,13,6,7]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 4, i32 5, i32 6, i32 11, i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 11>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_04_05_06_03_uu_uu_uu_uu_12_13_14_11_uu_uu_uu_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_04_05_06_03_uu_uu_uu_uu_12_13_14_11_uu_uu_uu_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [8,9,10,11,12,13,6,7,8,9,10,11,0,1,2,3]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
+; AVX1-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_04_05_06_03_uu_uu_uu_uu_12_13_14_11_uu_uu_uu_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[8,9,10,11,12,13,6,7,8,9,10,11,0,1,2,3,24,25,26,27,28,29,22,23,24,25,26,27,16,17,18,19]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 4, i32 5, i32 6, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 11, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_01_02_07_04_05_06_11_08_09_10_15_12_13_14_11(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_01_02_07_04_05_06_11_08_09_10_15_12_13_14_11:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,14,15,8,9,10,11,12,13,6,7]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm1, %xmm3
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_01_02_07_04_05_06_11_08_09_10_15_12_13_14_11:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,14,15,8,9,10,11,12,13,6,7]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm1, %xmm3
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX2-NEXT:    vinserti128 $1, %xmm3, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 11, i32 8, i32 9, i32 10, i32 15, i32 12, i32 13, i32 14, i32 11>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_04_05_06_03_00_01_02_15_12_13_14_11_08_09_10_15(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_04_05_06_03_00_01_02_15_12_13_14_11_08_09_10_15:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,6,7,0,1,2,3,4,5,2,3]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[8,9,10,11,12,13,6,7,0,1,2,3,4,5,14,15]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_04_05_06_03_00_01_02_15_12_13_14_11_08_09_10_15:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,6,7,0,1,2,3,4,5,2,3]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[8,9,10,11,12,13,6,7,0,1,2,3,4,5,14,15]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 4, i32 5, i32 6, i32 3, i32 0, i32 1, i32 2, i32 15, i32 12, i32 13, i32 14, i32 11, i32 8, i32 9, i32 10, i32 15>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_03_07_01_00_02_07_03_13_11_15_09_08_10_15_11_13(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_03_07_01_00_02_07_03_13_11_15_09_08_10_15_11_13:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [6,7,14,15,2,3,0,1,4,5,14,15,6,7,10,11]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm1, %xmm3
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
+; AVX1-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_03_07_01_00_02_07_03_13_11_15_09_08_10_15_11_13:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vmovdqa {{.*#+}} xmm2 = [6,7,14,15,2,3,0,1,4,5,14,15,6,7,10,11]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm1, %xmm3
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX2-NEXT:    vinserti128 $1, %xmm3, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 3, i32 7, i32 1, i32 0, i32 2, i32 7, i32 3, i32 13, i32 11, i32 15, i32 9, i32 8, i32 10, i32 15, i32 11, i32 13>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_16_01_17_02_18_03_27_08_24_09_25_10_26_11_27(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_16_01_17_02_18_03_27_08_24_09_25_10_26_11_27:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,14,15,14,15,8,9,12,13,14,15]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_16_01_17_02_18_03_27_08_24_09_25_10_26_11_27:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpunpcklwd {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11]
+; AVX2-NEXT:    vextracti128 $1, %ymm1, %xmm2
+; AVX2-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,0,2,2,4,5,6,7]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,4,6,7]
+; AVX2-NEXT:    vpunpcklwd {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3]
+; AVX2-NEXT:    vinserti128 $1, %xmm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 27, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_20_01_21_02_22_03_31_08_28_09_29_10_30_11_31(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_20_01_21_02_22_03_31_08_28_09_29_10_30_11_31:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm3[2,3,0,1]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3]
+; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,14,15,14,15,8,9,12,13,14,15]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_20_01_21_02_22_03_31_08_28_09_29_10_30_11_31:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
+; AVX2-NEXT:    vmovdqa {{.*#+}} xmm1 = [0,1,8,9,2,3,10,11,4,5,12,13,6,7,14,15]
+; AVX2-NEXT:    vpshufb %xmm1, %xmm0, %xmm2
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm0
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,5,6],xmm0[7]
+; AVX2-NEXT:    vpshufb %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vinserti128 $1, %xmm0, %ymm2, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 20, i32 1, i32 21, i32 2, i32 22, i32 3, i32 31, i32 8, i32 28, i32 9, i32 29, i32 10, i32 30, i32 11, i32 31>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_04_20_05_21_06_22_07_31_12_28_13_29_14_30_15_31(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_04_20_05_21_06_22_07_31_12_28_13_29_14_30_15_31:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm3 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
+; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[4,5,0,1,4,5,4,5,0,1,4,5,8,9,14,15]
+; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_04_20_05_21_06_22_07_31_12_28_13_29_14_30_15_31:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpunpckhwd {{.*#+}} ymm0 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15]
+; AVX2-NEXT:    vextracti128 $1, %ymm1, %xmm2
+; AVX2-NEXT:    vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,0,2,2,4,5,6,7]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,4,6,7]
+; AVX2-NEXT:    vpunpckhwd {{.*#+}} xmm2 = xmm2[4,4,5,5,6,6,7,7]
+; AVX2-NEXT:    vinserti128 $1, %xmm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 31, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_04_16_05_17_06_18_07_27_12_24_13_25_14_26_15_27(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_04_16_05_17_06_18_07_27_12_24_13_25_14_26_15_27:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm3 = xmm3[2,3,0,1]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[4,5,0,1,4,5,4,5,0,1,4,5,8,9,14,15]
+; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_04_16_05_17_06_18_07_27_12_24_13_25_14_26_15_27:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
+; AVX2-NEXT:    vmovdqa {{.*#+}} xmm2 = [8,9,0,1,10,11,2,3,12,13,4,5,14,15,6,7]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX2-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 4, i32 16, i32 5, i32 17, i32 6, i32 18, i32 7, i32 27, i32 12, i32 24, i32 13, i32 25, i32 14, i32 26, i32 15, i32 27>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_16_01_17_06_22_07_31_08_24_09_25_14_30_15_31(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_16_01_17_06_22_07_31_08_24_09_25_14_30_15_31:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm3 = xmm2[0,3,2,3]
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm4
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm4[0,3,2,3]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,0,2,1,4,5,6,7]
+; AVX1-NEXT:    vpshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5],xmm2[6,7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[2,3,6,7,10,11,14,15,14,15,10,11,12,13,14,15]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,3,2,3]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_16_01_17_06_22_07_31_08_24_09_25_14_30_15_31:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm1, %xmm2
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,0,2,1,4,5,6,7]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7]
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm2 = xmm2[0,0,2,1,4,5,6,7]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7]
+; AVX2-NEXT:    vinserti128 $1, %xmm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[0,1,1,3,4,5,6,7,8,9,9,11,12,13,14,15]
+; AVX2-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,6,5,7,7,8,9,10,11,14,13,15,15]
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 6, i32 22, i32 7, i32 31, i32 8, i32 24, i32 9, i32 25, i32 14, i32 30, i32 15, i32 31>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_20_01_21_06_16_07_25_08_28_09_29_14_24_15_25(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_20_01_21_06_16_07_25_08_28_09_29_14_24_15_25:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm3 = xmm2[2,0,2,3]
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm4
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm4[0,3,2,3]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2,3,4,5,6,7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[8,9,10,11,0,1,2,3,2,3,0,1,12,13,2,3]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,3,2,3]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_20_01_21_06_16_07_25_08_28_09_29_14_24_15_25:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm1, %xmm2
+; AVX2-NEXT:    vmovdqa {{.*#+}} xmm3 = [8,9,8,9,4,5,10,11,0,1,0,1,12,13,2,3]
+; AVX2-NEXT:    vpshufb %xmm3, %xmm2, %xmm4
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb %xmm3, %xmm1, %xmm1
+; AVX2-NEXT:    vinserti128 $1, %xmm4, %ymm1, %ymm1
+; AVX2-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[0,1,1,3,4,5,6,7,8,9,9,11,12,13,14,15]
+; AVX2-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,6,5,7,7,8,9,10,11,14,13,15,15]
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 20, i32 1, i32 21, i32 6, i32 16, i32 7, i32 25, i32 8, i32 28, i32 9, i32 29, i32 14, i32 24, i32 15, i32 25>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_01_00_17_16_03_02_19_26_09_08_25_24_11_10_27_26(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_01_00_17_16_03_02_19_26_09_08_25_24_11_10_27_26:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[4,5,0,1,12,13,10,11,8,9,10,11,12,13,10,11]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm3 = xmm0[1,0,3,2,4,5,6,7]
+; AVX1-NEXT:    vpunpckldq {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[2,0,3,1,4,5,6,7]
+; AVX1-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,4,7,5]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_01_00_17_16_03_02_19_26_09_08_25_24_11_10_27_26:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm1, %xmm2
+; AVX2-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,1,2,0,4,5,6,7]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5,6,5]
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm2 = xmm2[0,1,2,3,2,3,0,1,8,9,10,11,6,7,4,5]
+; AVX2-NEXT:    vinserti128 $1, %xmm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[2,3,0,1,4,5,6,7,6,7,4,5,4,5,6,7,18,19,16,17,20,21,22,23,22,23,20,21,20,21,22,23]
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 1, i32 0, i32 17, i32 16, i32 3, i32 2, i32 19, i32 26, i32 9, i32 8, i32 25, i32 24, i32 11, i32 10, i32 27, i32 26>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_16_00_17_01_18_02_19_11_24_08_25_09_26_10_27_11(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_16_00_17_01_18_02_19_11_24_08_25_09_26_10_27_11:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,14,15,14,15,8,9,12,13,14,15]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_16_00_17_01_18_02_19_11_24_08_25_09_26_10_27_11:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11]
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm2
+; AVX2-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,2,2,4,5,6,7]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,4,6,7]
+; AVX2-NEXT:    vpunpcklwd {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3]
+; AVX2-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7],ymm1[8],ymm0[9],ymm1[10],ymm0[11],ymm1[12],ymm0[13],ymm1[14],ymm0[15]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 16, i32 0, i32 17, i32 1, i32 18, i32 2, i32 19, i32 11, i32 24, i32 8, i32 25, i32 9, i32 26, i32 10, i32 27, i32 11>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_20_04_21_05_22_06_23_15_28_12_29_13_30_14_31_15(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_20_04_21_05_22_06_23_15_28_12_29_13_30_14_31_15:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm3 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
+; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[4,5,0,1,4,5,4,5,0,1,4,5,8,9,14,15]
+; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_20_04_21_05_22_06_23_15_28_12_29_13_30_14_31_15:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpunpckhwd {{.*#+}} ymm1 = ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15]
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm2
+; AVX2-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,2,2,4,5,6,7]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,4,6,7]
+; AVX2-NEXT:    vpunpckhwd {{.*#+}} xmm2 = xmm2[4,4,5,5,6,6,7,7]
+; AVX2-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7],ymm1[8],ymm0[9],ymm1[10],ymm0[11],ymm1[12],ymm0[13],ymm1[14],ymm0[15]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 20, i32 4, i32 21, i32 5, i32 22, i32 6, i32 23, i32 15, i32 28, i32 12, i32 29, i32 13, i32 30, i32 14, i32 31, i32 15>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_02_01_03_20_22_21_31_08_10_09_11_28_30_29_31(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_02_01_03_20_22_21_31_08_10_09_11_28_30_29_31:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm2 = xmm2[0,2,1,3,4,5,6,7]
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm3[2,3,2,3]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm4 = xmm4[0,2,1,3,4,5,6,7]
+; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
+; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,8,9,4,5,14,15,0,1,4,5,4,5,6,7]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,2,1,3,4,5,6,7]
+; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_02_01_03_20_22_21_31_08_10_09_11_28_30_29_31:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,2,1,3,4,5,6,7]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,5,7]
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
+; AVX2-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,2,1,3,4,5,6,7]
+; AVX2-NEXT:    vpshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,5,7]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 2, i32 1, i32 3, i32 20, i32 22, i32 21, i32 31, i32 8, i32 10, i32 9, i32 11, i32 28, i32 30, i32 29, i32 31>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_04_04_03_18_uu_uu_uu_uu_12_12_11_26_uu_uu_uu_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_04_04_03_18_uu_uu_uu_uu_12_12_11_26_uu_uu_uu_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm2 = xmm0[0,1],xmm1[2],xmm0[3,4,5,6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm2 = xmm2[2,1,2,3]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm2 = xmm2[0,0,3,2,4,5,6,7]
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3,4,5,6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,3,2,4,5,6,7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm2, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_04_04_03_18_uu_uu_uu_uu_12_12_11_26_uu_uu_uu_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4,5,6,7,8,9],ymm1[10],ymm0[11,12,13,14,15]
+; AVX2-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[2,1,2,3,6,5,6,7]
+; AVX2-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[0,0,3,2,4,5,6,7,8,8,11,10,12,13,14,15]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 4, i32 4, i32 3, i32 18, i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 12, i32 11, i32 26, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_03_02_21_uu_uu_uu_uu_08_11_10_29_uu_uu_uu_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_03_02_21_uu_uu_uu_uu_08_11_10_29_uu_uu_uu_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm3 = [0,1,6,7,4,5,10,11,0,1,10,11,0,1,2,3]
+; AVX1-NEXT:    vpshufb %xmm3, %xmm2, %xmm2
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; AVX1-NEXT:    vpshufb %xmm3, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_03_02_21_uu_uu_uu_uu_08_11_10_29_uu_uu_uu_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,6,7,4,5,10,11,0,1,10,11,0,1,2,3,16,17,22,23,20,21,26,27,16,17,26,27,16,17,18,19]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 3, i32 2, i32 21, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 11, i32 10, i32 29, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_uu_uu_21_uu_uu_uu_uu_uu_uu_uu_29_uu_uu_uu_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_uu_uu_21_uu_uu_uu_uu_uu_uu_uu_29_uu_uu_uu_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm1[0,2,2,3,4,6,6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_uu_uu_21_uu_uu_uu_uu_uu_uu_uu_29_uu_uu_uu_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpshufd {{.*#+}} ymm0 = ymm1[0,2,2,3,4,6,6,7]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 21, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 29, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_01_02_21_uu_uu_uu_uu_08_09_10_29_uu_uu_uu_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_01_02_21_uu_uu_uu_uu_08_09_10_29_uu_uu_uu_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm3 = xmm3[2,2,3,3]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[3],xmm2[4,5,6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_01_02_21_uu_uu_uu_uu_08_09_10_29_uu_uu_uu_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5,6,7,8,9,10],ymm1[11],ymm0[12,13,14,15]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 21, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 10, i32 29, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_uu_uu_uu_20_21_22_11_uu_uu_uu_uu_28_29_30_11(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_uu_uu_uu_20_21_22_11_uu_uu_uu_uu_28_29_30_11:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,5,6],xmm0[7]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5,6],xmm0[7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_uu_uu_uu_20_21_22_11_uu_uu_uu_uu_28_29_30_11:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,2,2,2]
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3,4,5,6],ymm0[7],ymm1[8,9,10,11,12,13,14],ymm0[15]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 20, i32 21, i32 22, i32 11, i32 undef, i32 undef, i32 undef, i32 undef, i32 28, i32 29, i32 30, i32 11>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_20_21_22_03_uu_uu_uu_uu_28_29_30_11_uu_uu_uu_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_20_21_22_03_uu_uu_uu_uu_28_29_30_11_uu_uu_uu_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm3 = xmm3[2,3,0,1]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm2 = xmm3[0,1,2],xmm2[3],xmm3[4,5,6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3],xmm1[4,5,6,7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_20_21_22_03_uu_uu_uu_uu_28_29_30_11_uu_uu_uu_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpshufd {{.*#+}} ymm1 = ymm1[2,3,2,3,6,7,6,7]
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5,6,7,8,9,10],ymm0[11],ymm1[12,13,14,15]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 20, i32 21, i32 22, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 28, i32 29, i32 30, i32 11, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_01_02_21_20_21_22_11_08_09_10_29_28_29_30_11(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_01_02_21_20_21_22_11_08_09_10_29_28_29_30_11:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm3 = xmm1[0,2,2,3]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[3,4,5,6],xmm0[7]
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5,10,11,8,9,10,11,12,13,6,7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_01_02_21_20_21_22_11_08_09_10_29_28_29_30_11:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
+; AVX2-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,10,11,8,9,10,11,12,13,6,7]
+; AVX2-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX2-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 21, i32 20, i32 21, i32 22, i32 11, i32 8, i32 9, i32 10, i32 29, i32 28, i32 29, i32 30, i32 11>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_00_17_02_03_20_21_22_15_08_25_10_11_28_29_30_15(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_00_17_02_03_20_21_22_15_08_25_10_11_28_29_30_15:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm2 = xmm3[0],xmm2[1],xmm3[2,3],xmm2[4,5,6],xmm3[7]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3],xmm1[4,5,6],xmm0[7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_00_17_02_03_20_21_22_15_08_25_10_11_28_29_30_15:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,3,2,3]
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3],ymm1[4,5,6],ymm0[7,8],ymm1[9],ymm0[10,11],ymm1[12,13,14],ymm0[15]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 17, i32 2, i32 3, i32 20, i32 21, i32 22, i32 15, i32 8, i32 25, i32 10, i32 11, i32 28, i32 29, i32 30, i32 15>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_uu_uu_01_uu_05_07_25_uu_uu_uu_09_uu_13_15_25(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_uu_uu_01_uu_05_07_25_uu_uu_uu_09_uu_13_15_25:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,1,2,0]
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm2 = xmm2[0,1,2,1,4,5,6,7]
+; AVX1-NEXT:    vpshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,5,7,7]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,5,6],xmm1[7]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,1,2,1,4,5,6,7]
+; AVX1-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,7,7]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_uu_uu_01_uu_05_07_25_uu_uu_uu_09_uu_13_15_25:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpbroadcastd {{.*}}(%rip), %ymm2
+; AVX2-NEXT:    vpermd %ymm1, %ymm2, %ymm1
+; AVX2-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[0,1,2,1,4,5,6,7,8,9,10,9,12,13,14,15]
+; AVX2-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,7,7,8,9,10,11,12,13,15,15]
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm1[7],ymm0[8,9,10,11,12,13,14],ymm1[15]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 5, i32 7, i32 25, i32 undef, i32 undef, i32 undef, i32 9, i32 undef, i32 13, i32 15, i32 25>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_uu_04_uu_16_18_20_uu_uu_uu_12_uu_24_26_28_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_uu_04_uu_16_18_20_uu_uu_uu_12_uu_24_26_28_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm3 = [0,1,4,5,4,5,6,7,0,1,4,5,8,9,4,5]
+; AVX1-NEXT:    vpshufb %xmm3, %xmm2, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm4
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm4[2,2,3,3]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm2 = xmm4[0,1,2,3],xmm2[4,5,6,7]
+; AVX1-NEXT:    vpshufb %xmm3, %xmm1, %xmm1
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_uu_04_uu_16_18_20_uu_uu_uu_12_uu_24_26_28_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[0,1,4,5,4,5,6,7,0,1,4,5,8,9,4,5,16,17,20,21,20,21,22,23,16,17,20,21,24,25,20,21]
+; AVX2-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 undef, i32 4, i32 undef, i32 16, i32 18, i32 20, i32 undef, i32 undef, i32 undef, i32 12, i32 undef, i32 24, i32 26, i32 28, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_21_22_23_00_01_02_03_12_29_30_31_08_09_10_11_12(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_21_22_23_00_01_02_03_12_29_30_31_08_09_10_11_12:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[10,11,12,13,14,15],xmm3[0,1,2,3,4,5,6,7,8,9]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9]
+; AVX1-NEXT:    vpsrldq {{.*#+}} xmm1 = xmm1[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4,5,6,7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_21_22_23_00_01_02_03_12_29_30_31_08_09_10_11_12:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3,4],ymm1[5,6,7],ymm0[8,9,10,11,12],ymm1[13,14,15]
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4],xmm0[5,6,7]
+; AVX2-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9]
+; AVX2-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 21, i32 22, i32 23, i32 0, i32 1, i32 2, i32 3, i32 12, i32 29, i32 30, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_22_uu_uu_01_02_03_uu_uu_30_uu_uu_09_10_11_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_22_uu_uu_01_02_03_uu_uu_30_uu_uu_09_10_11_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[10,11,12,13,14,15],xmm3[0,1,2,3,4,5,6,7,8,9]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm1[10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7,8,9]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_22_uu_uu_01_02_03_uu_uu_30_uu_uu_09_10_11_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm1[10,11,12,13,14,15],ymm0[0,1,2,3,4,5,6,7,8,9],ymm1[26,27,28,29,30,31],ymm0[16,17,18,19,20,21,22,23,24,25]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 22, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 30, i32 undef, i32 undef, i32 9, i32 10, i32 11, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_05_06_07_00_01_02_03_12_13_14_15_08_09_10_11_12(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_05_06_07_00_01_02_03_12_13_14_15_08_09_10_11_12:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4],xmm0[5,6,7]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_05_06_07_00_01_02_03_12_13_14_15_08_09_10_11_12:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4],xmm0[5,6,7]
+; AVX2-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9]
+; AVX2-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_06_uu_uu_01_02_03_uu_uu_14_uu_uu_09_10_11_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_06_uu_uu_01_02_03_uu_uu_14_uu_uu_09_10_11_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm1 = xmm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9]
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_06_uu_uu_01_02_03_uu_uu_14_uu_uu_09_10_11_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,26,27,28,29,30,31,16,17,18,19,20,21,22,23,24,25]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 6, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 14, i32 undef, i32 undef, i32 9, i32 10, i32 11, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_uu_uu_uu_01_02_03_uu_uu_uu_uu_uu_09_10_11_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_uu_uu_uu_01_02_03_uu_uu_uu_uu_uu_09_10_11_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9]
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_uu_uu_uu_01_02_03_uu_uu_uu_uu_uu_09_10_11_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8,9],zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24,25]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 9, i32 10, i32 11, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_19_20_21_22_23_00_01_10_27_28_29_30_31_08_09_10(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_19_20_21_22_23_00_01_10_27_28_29_30_31_08_09_10:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[6,7,8,9,10,11,12,13,14,15],xmm3[0,1,2,3,4,5]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,4,5,6,7,8,9,0,1,4,5,10,11]
+; AVX1-NEXT:    vpsrldq {{.*#+}} xmm1 = xmm1[6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4],xmm0[5,6,7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_19_20_21_22_23_00_01_10_27_28_29_30_31_08_09_10:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3,4,5,6,7],ymm0[8,9,10],ymm1[11,12,13,14,15]
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3,4,5,6,7]
+; AVX2-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5]
+; AVX2-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 19, i32 20, i32 21, i32 22, i32 23, i32 0, i32 1, i32 10, i32 27, i32 28, i32 29, i32 30, i32 31, i32 8, i32 9, i32 10>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_20_21_22_uu_uu_01_uu_uu_28_29_30_uu_uu_09_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_20_21_22_uu_uu_01_uu_uu_28_29_30_uu_uu_09_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[6,7,8,9,10,11,12,13,14,15],xmm3[0,1,2,3,4,5]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm1[6,7,8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_20_21_22_uu_uu_01_uu_uu_28_29_30_uu_uu_09_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm1[6,7,8,9,10,11,12,13,14,15],ymm0[0,1,2,3,4,5],ymm1[22,23,24,25,26,27,28,29,30,31],ymm0[16,17,18,19,20,21]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 20, i32 21, i32 22, i32 undef, i32 undef, i32 1, i32 undef, i32 undef, i32 28, i32 29, i32 30, i32 undef, i32 undef, i32 9, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_03_04_05_06_07_00_01_10_11_12_13_14_15_08_09_10(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_03_04_05_06_07_00_01_10_11_12_13_14_15_08_09_10:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3,4,5,6,7]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_03_04_05_06_07_00_01_10_11_12_13_14_15_08_09_10:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3,4,5,6,7]
+; AVX2-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5]
+; AVX2-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_04_05_06_uu_uu_01_uu_uu_12_13_14_uu_uu_09_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_04_05_06_uu_uu_01_uu_uu_12_13_14_uu_uu_09_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm1 = xmm0[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5]
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_04_05_06_uu_uu_01_uu_uu_12_13_14_uu_uu_09_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5,22,23,24,25,26,27,28,29,30,31,16,17,18,19,20,21]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 4, i32 5, i32 6, i32 undef, i32 undef, i32 1, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 undef, i32 undef, i32 9, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_04_05_06_uu_uu_uu_uu_uu_12_13_14_uu_uu_uu_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_04_05_06_uu_uu_uu_uu_uu_12_13_14_uu_uu_uu_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpsrldq {{.*#+}} xmm1 = xmm0[6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpsrldq {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_04_05_06_uu_uu_uu_uu_uu_12_13_14_uu_uu_uu_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpsrldq {{.*#+}} ymm0 = ymm0[6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,ymm0[22,23,24,25,26,27,28,29,30,31],zero,zero,zero,zero,zero,zero
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 4, i32 5, i32 6, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_03_04_05_06_07_16_17_26_11_12_13_14_15_24_25_26(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_03_04_05_06_07_16_17_26_11_12_13_14_15_24_25_26:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[6,7,8,9,10,11,12,13,14,15],xmm3[0,1,2,3,4,5]
+; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,4,5,6,7,8,9,0,1,4,5,10,11]
+; AVX1-NEXT:    vpsrldq {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4],xmm1[5,6,7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_03_04_05_06_07_16_17_26_11_12_13_14_15_24_25_26:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7],ymm1[8,9,10],ymm0[11,12,13,14,15]
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3,4,5,6,7]
+; AVX2-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5]
+; AVX2-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 26, i32 11, i32 12, i32 13, i32 14, i32 15, i32 24, i32 25, i32 26>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_04_05_06_uu_uu_17_uu_uu_12_13_14_uu_uu_25_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_04_05_06_uu_uu_17_uu_uu_12_13_14_uu_uu_25_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[6,7,8,9,10,11,12,13,14,15],xmm3[0,1,2,3,4,5]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_04_05_06_uu_uu_17_uu_uu_12_13_14_uu_uu_25_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[6,7,8,9,10,11,12,13,14,15],ymm1[0,1,2,3,4,5],ymm0[22,23,24,25,26,27,28,29,30,31],ymm1[16,17,18,19,20,21]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 4, i32 5, i32 6, i32 undef, i32 undef, i32 17, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 undef, i32 undef, i32 25, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_05_06_07_16_17_18_19_28_13_14_15_24_25_26_27_28(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_05_06_07_16_17_18_19_28_13_14_15_24_25_26_27_28:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[10,11,12,13,14,15],xmm3[0,1,2,3,4,5,6,7,8,9]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm3[4,5,6,7]
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7,8,9]
+; AVX1-NEXT:    vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3,4,5,6,7]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_05_06_07_16_17_18_19_28_13_14_15_24_25_26_27_28:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3,4],ymm0[5,6,7],ymm1[8,9,10,11,12],ymm0[13,14,15]
+; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4],xmm0[5,6,7]
+; AVX2-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9]
+; AVX2-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9]
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 28, i32 13, i32 14, i32 15, i32 24, i32 25, i32 26, i32 27, i32 28>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_uu_06_uu_uu_17_18_19_uu_uu_14_uu_uu_25_26_27_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_uu_06_uu_uu_17_18_19_uu_uu_14_uu_uu_25_26_27_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[10,11,12,13,14,15],xmm3[0,1,2,3,4,5,6,7,8,9]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7,8,9]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_uu_06_uu_uu_17_18_19_uu_uu_14_uu_uu_25_26_27_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[10,11,12,13,14,15],ymm1[0,1,2,3,4,5,6,7,8,9],ymm0[26,27,28,29,30,31],ymm1[16,17,18,19,20,21,22,23,24,25]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 6, i32 undef, i32 undef, i32 17, i32 18, i32 19, i32 undef, i32 undef, i32 14, i32 undef, i32 undef, i32 25, i32 26, i32 27, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @shuffle_v16i16_23_uu_03_uu_20_20_05_uu_31_uu_11_uu_28_28_13_uu(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: shuffle_v16i16_23_uu_03_uu_20_20_05_uu_31_uu_11_uu_28_28_13_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm2 = zero,zero,xmm2[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,7,5,4,4]
+; AVX1-NEXT:    vpunpckhdq {{.*#+}} xmm2 = xmm3[2],xmm2[2],xmm3[3],xmm2[3]
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
+; AVX1-NEXT:    vpshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,5,4,4]
+; AVX1-NEXT:    vpunpckhdq {{.*#+}} xmm0 = xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v16i16_23_uu_03_uu_20_20_05_uu_31_uu_11_uu_28_28_13_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4],ymm0[5,6],ymm1[7],ymm0[8,9,10,11],ymm1[12],ymm0[13,14],ymm1[15]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[14,15,14,15,6,7,6,7,8,9,8,9,10,11,14,15,30,31,30,31,22,23,22,23,24,25,24,25,26,27,30,31]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 23, i32 undef, i32 3, i32 undef, i32 20, i32 20, i32 5, i32 undef, i32 31, i32 undef, i32 11, i32 undef, i32 28, i32 28, i32 13, i32 undef>
+  ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @insert_v16i16_0elt_into_zero_vector(i16* %ptr) {
+; ALL-LABEL: insert_v16i16_0elt_into_zero_vector:
+; ALL:       # BB#0:
+; ALL-NEXT:    movzwl (%rdi), %eax
+; ALL-NEXT:    vmovd %eax, %xmm0
+; ALL-NEXT:    retq
+  %val = load i16, i16* %ptr
+  %i0 = insertelement <16 x i16> zeroinitializer, i16 %val, i32 0
+  ret <16 x i16> %i0
+}
+
diff --git a/test/CodeGen/X86/vector-shuffle-256-v32.ll b/test/CodeGen/X86/vector-shuffle-256-v32.ll
index c7f4c3512fba..a0f43de75630 100644
--- a/test/CodeGen/X86/vector-shuffle-256-v32.ll
+++ b/test/CodeGen/X86/vector-shuffle-256-v32.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mcpu=x86-64 -mattr=+avx -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
+; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
+; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
 
 target triple = "x86_64-unknown-unknown"
 
@@ -314,9 +314,8 @@ define <32 x i8> @shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_16_
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpshufb %xmm1, %xmm0, %xmm1
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0]
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],zero
-; AVX1-NEXT:    vpor %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -339,19 +338,17 @@ define <32 x i8> @shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_17_00_
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpshufb %xmm1, %xmm0, %xmm1
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[1],zero
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0,0,0],zero,xmm0[0]
-; AVX1-NEXT:    vpor %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_17_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,1,u,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
-; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
+; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = <0,255,u,u,u,u,u,u,u,u,u,u,u,u,u,u,255,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u>
 ; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 17, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <32 x i8> %shuffle
@@ -363,19 +360,17 @@ define <32 x i8> @shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_18_00_00_
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpshufb %xmm1, %xmm0, %xmm1
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[2],zero,zero
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0,0],zero,xmm0[0,0]
-; AVX1-NEXT:    vpor %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0,0,5,0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_18_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,2,u,u,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
-; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,0,0,0,0,0,0,0,255,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
+; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = <0,0,255,255,u,u,u,u,u,u,u,u,u,u,u,u,255,255,u,u,u,u,u,u,u,u,u,u,u,u,u,u>
 ; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 18, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <32 x i8> %shuffle
@@ -387,19 +382,17 @@ define <32 x i8> @shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_19_00_00_00_
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpshufb %xmm1, %xmm0, %xmm1
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[3],zero,zero,zero
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0],zero,xmm0[0,0,0]
-; AVX1-NEXT:    vpor %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0,7,0,0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_19_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,3,u,u,u,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
-; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,0,0,0,0,0,0,255,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
+; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = <0,0,255,255,u,u,u,u,u,u,u,u,u,u,u,u,255,255,u,u,u,u,u,u,u,u,u,u,u,u,u,u>
 ; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 19, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <32 x i8> %shuffle
@@ -411,19 +404,16 @@ define <32 x i8> @shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_20_00_00_00_00_
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpshufb %xmm1, %xmm0, %xmm1
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[4],zero,zero,zero,zero
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0],zero,xmm0[0,0,0,0]
-; AVX1-NEXT:    vpor %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,9,0,0,0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_20_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,4,u,u,u,u,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
-; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,0,0,0,0,0,255,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,0,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 20, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <32 x i8> %shuffle
@@ -435,19 +425,16 @@ define <32 x i8> @shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_21_00_00_00_00_00_
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpshufb %xmm1, %xmm0, %xmm1
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[5],zero,zero,zero,zero,zero
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0],zero,xmm0[0,0,0,0,0]
-; AVX1-NEXT:    vpor %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,11,0,0,0,0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_21_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,5,u,u,u,u,u,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
-; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,0,0,0,0,255,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,0,0,0,0,0,0,0,0,0,5,0,0,0,0,0,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 21, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <32 x i8> %shuffle
@@ -459,19 +446,16 @@ define <32 x i8> @shuffle_v32i8_00_00_00_00_00_00_00_00_00_22_00_00_00_00_00_00_
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpshufb %xmm1, %xmm0, %xmm1
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[6],zero,zero,zero,zero,zero,zero
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0],zero,xmm0[0,0,0,0,0,0]
-; AVX1-NEXT:    vpor %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,13,0,0,0,0,0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_22_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,6,u,u,u,u,u,u,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
-; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,0,0,0,255,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,0,0,0,0,0,0,0,0,6,0,0,0,0,0,0,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 22, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <32 x i8> %shuffle
@@ -483,19 +467,16 @@ define <32 x i8> @shuffle_v32i8_00_00_00_00_00_00_00_00_23_00_00_00_00_00_00_00_
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpshufb %xmm1, %xmm0, %xmm1
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[7],zero,zero,zero,zero,zero,zero,zero
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0],zero,xmm0[0,0,0,0,0,0,0]
-; AVX1-NEXT:    vpor %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,15,0,0,0,0,0,0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_23_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,7,u,u,u,u,u,u,u,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
-; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,0,0,0,0,0,0,0,7,0,0,0,0,0,0,0,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 23, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <32 x i8> %shuffle
@@ -516,10 +497,8 @@ define <32 x i8> @shuffle_v32i8_00_00_00_00_00_00_00_24_00_00_00_00_00_00_00_00_
 ; AVX2-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_24_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,8,u,u,u,u,u,u,u,u,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
-; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,0,255,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,0,0,0,0,0,0,8,0,0,0,0,0,0,0,0,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 24, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <32 x i8> %shuffle
@@ -540,10 +519,8 @@ define <32 x i8> @shuffle_v32i8_00_00_00_00_00_00_25_00_00_00_00_00_00_00_00_00_
 ; AVX2-LABEL: shuffle_v32i8_00_00_00_00_00_00_25_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,9,u,u,u,u,u,u,u,u,u,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
-; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,0,255,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,0,0,0,0,0,9,0,0,0,0,0,0,0,0,0,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 25, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <32 x i8> %shuffle
@@ -564,10 +541,8 @@ define <32 x i8> @shuffle_v32i8_00_00_00_00_00_26_00_00_00_00_00_00_00_00_00_00_
 ; AVX2-LABEL: shuffle_v32i8_00_00_00_00_00_26_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,10,u,u,u,u,u,u,u,u,u,u,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
-; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,0,255,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,0,0,0,0,10,0,0,0,0,0,0,0,0,0,0,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 26, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <32 x i8> %shuffle
@@ -588,10 +563,8 @@ define <32 x i8> @shuffle_v32i8_00_00_00_00_27_00_00_00_00_00_00_00_00_00_00_00_
 ; AVX2-LABEL: shuffle_v32i8_00_00_00_00_27_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,11,u,u,u,u,u,u,u,u,u,u,u,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
-; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,0,255,0,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,0,0,0,11,0,0,0,0,0,0,0,0,0,0,0,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 27, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <32 x i8> %shuffle
@@ -612,10 +585,8 @@ define <32 x i8> @shuffle_v32i8_00_00_00_28_00_00_00_00_00_00_00_00_00_00_00_00_
 ; AVX2-LABEL: shuffle_v32i8_00_00_00_28_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,12,u,u,u,u,u,u,u,u,u,u,u,u,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
-; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,0,255,0,0,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,0,0,12,0,0,0,0,0,0,0,0,0,0,0,0,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 0, i32 0, i32 28, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <32 x i8> %shuffle
@@ -636,10 +607,8 @@ define <32 x i8> @shuffle_v32i8_00_00_29_00_00_00_00_00_00_00_00_00_00_00_00_00_
 ; AVX2-LABEL: shuffle_v32i8_00_00_29_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,13,u,u,u,u,u,u,u,u,u,u,u,u,u,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
-; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,255,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,0,13,0,0,0,0,0,0,0,0,0,0,0,0,0,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 0, i32 29, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <32 x i8> %shuffle
@@ -660,10 +629,8 @@ define <32 x i8> @shuffle_v32i8_00_30_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
 ; AVX2-LABEL: shuffle_v32i8_00_30_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,14,u,u,u,u,u,u,u,u,u,u,u,u,u,u,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
-; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,14,0,0,0,0,0,0,0,0,0,0,0,0,0,0,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 30, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <32 x i8> %shuffle
@@ -686,14 +653,10 @@ define <32 x i8> @shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
 ; AVX2-LABEL: shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vperm2i128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
 ; AVX2-NEXT:    movl $15, %eax
-; AVX2-NEXT:    vmovd %eax, %xmm2
-; AVX2-NEXT:    vpxor %ymm3, %ymm3, %ymm3
-; AVX2-NEXT:    vinserti128 $0, %xmm2, %ymm3, %ymm2
-; AVX2-NEXT:    vpshufb %ymm2, %ymm1, %ymm1
-; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vmovd %eax, %xmm1
+; AVX2-NEXT:    vpshufb %ymm1, %ymm0, %ymm0
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 31, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <32 x i8> %shuffle
@@ -947,16 +910,11 @@ define <32 x i8> @shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
 define <32 x i8> @shuffle_v32i8_00_33_02_35_04_37_06_39_08_41_10_43_12_45_14_47_16_49_18_51_20_53_22_55_24_57_26_59_28_61_30_63(<32 x i8> %a, <32 x i8> %b) {
 ; AVX1-LABEL: shuffle_v32i8_00_33_02_35_04_37_06_39_08_41_10_43_12_45_14_47_16_49_18_51_20_53_22_55_24_57_26_59_28_61_30_63:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
-; AVX1-NEXT:    vmovdqa {{.*#+}} xmm3 = <1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u>
-; AVX1-NEXT:    vpshufb %xmm3, %xmm2, %xmm2
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm4
-; AVX1-NEXT:    vmovdqa {{.*#+}} xmm5 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
-; AVX1-NEXT:    vpshufb %xmm5, %xmm4, %xmm4
-; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm2 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3],xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7]
-; AVX1-NEXT:    vpshufb %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpshufb %xmm5, %xmm0, %xmm0
-; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm4 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
+; AVX1-NEXT:    vpblendvb %xmm4, %xmm2, %xmm3, %xmm2
+; AVX1-NEXT:    vpblendvb %xmm4, %xmm0, %xmm1, %xmm0
 ; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -972,16 +930,11 @@ define <32 x i8> @shuffle_v32i8_00_33_02_35_04_37_06_39_08_41_10_43_12_45_14_47_
 define <32 x i8> @shuffle_v32i8_32_01_34_03_36_05_38_07_40_09_42_11_44_13_46_15_48_17_50_19_52_21_54_23_56_25_58_27_60_29_62_31(<32 x i8> %a, <32 x i8> %b) {
 ; AVX1-LABEL: shuffle_v32i8_32_01_34_03_36_05_38_07_40_09_42_11_44_13_46_15_48_17_50_19_52_21_54_23_56_25_58_27_60_29_62_31:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT:    vmovdqa {{.*#+}} xmm3 = <1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u>
-; AVX1-NEXT:    vpshufb %xmm3, %xmm2, %xmm2
-; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm4
-; AVX1-NEXT:    vmovdqa {{.*#+}} xmm5 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
-; AVX1-NEXT:    vpshufb %xmm5, %xmm4, %xmm4
-; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm2 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3],xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7]
-; AVX1-NEXT:    vpshufb %xmm3, %xmm0, %xmm0
-; AVX1-NEXT:    vpshufb %xmm5, %xmm1, %xmm1
-; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm4 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
+; AVX1-NEXT:    vpblendvb %xmm4, %xmm2, %xmm3, %xmm2
+; AVX1-NEXT:    vpblendvb %xmm4, %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -997,11 +950,8 @@ define <32 x i8> @shuffle_v32i8_32_01_34_03_36_05_38_07_40_09_42_11_44_13_46_15_
 define <32 x i8> @shuffle_v32i8_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32(<32 x i8> %a, <32 x i8> %b) {
 ; AVX1-LABEL: shuffle_v32i8_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
 ; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -1020,17 +970,12 @@ define <32 x i8> @shuffle_v32i8_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_
 ; AVX1-LABEL: shuffle_v32i8_00_32_00_32_00_32_00_32_00_32_00_32_00_32_00_32_16_48_16_48_16_48_16_48_16_48_16_48_16_48_16_48:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
-; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm2 = xmm2[0,0,0,0,4,5,6,7]
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
-; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm3 = xmm3[0,0,0,0,4,5,6,7]
 ; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3],xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
-; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
-; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm3 = [0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
+; AVX1-NEXT:    vpshufb %xmm3, %xmm2, %xmm2
 ; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; AVX1-NEXT:    vpshufb %xmm3, %xmm0, %xmm0
 ; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -1050,15 +995,15 @@ define <32 x i8> @shuffle_v32i8_32_32_32_32_32_32_32_32_08_09_10_11_12_13_14_15_
 ; AVX1-LABEL: shuffle_v32i8_32_32_32_32_32_32_32_32_08_09_10_11_12_13_14_15_48_48_48_48_48_48_48_48_24_25_26_27_28_29_30_31:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT:    vmovdqa {{.*#+}} xmm3 = [128,128,128,128,128,128,128,128,8,9,10,11,12,13,14,15]
-; AVX1-NEXT:    vpshufb %xmm3, %xmm2, %xmm2
-; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm4
-; AVX1-NEXT:    vmovdqa {{.*#+}} xmm5 = [0,0,0,0,0,0,0,0,128,128,128,128,128,128,128,128]
-; AVX1-NEXT:    vpshufb %xmm5, %xmm4, %xmm4
-; AVX1-NEXT:    vpor %xmm2, %xmm4, %xmm2
-; AVX1-NEXT:    vpshufb %xmm3, %xmm0, %xmm0
-; AVX1-NEXT:    vpshufb %xmm5, %xmm1, %xmm1
-; AVX1-NEXT:    vpor %xmm0, %xmm1, %xmm0
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm3 = xmm3[0,0,0,0,4,5,6,7]
+; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; AVX1-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
+; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -1076,23 +1021,22 @@ define <32 x i8> @shuffle_v32i8_39_38_37_36_35_34_33_32_15_14_13_12_11_10_09_08_
 ; AVX1-LABEL: shuffle_v32i8_39_38_37_36_35_34_33_32_15_14_13_12_11_10_09_08_55_54_53_52_51_50_49_48_31_30_29_28_27_26_25_24:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT:    vmovdqa {{.*#+}} xmm3 = [128,128,128,128,128,128,128,128,15,14,13,12,11,10,9,8]
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm3 = <15,14,13,12,11,10,9,8,u,u,u,u,u,u,u,u>
 ; AVX1-NEXT:    vpshufb %xmm3, %xmm2, %xmm2
 ; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm4
-; AVX1-NEXT:    vmovdqa {{.*#+}} xmm5 = [7,6,5,4,3,2,1,0,128,128,128,128,128,128,128,128]
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm5 = <7,6,5,4,3,2,1,0,u,u,u,u,u,u,u,u>
 ; AVX1-NEXT:    vpshufb %xmm5, %xmm4, %xmm4
-; AVX1-NEXT:    vpor %xmm2, %xmm4, %xmm2
+; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm4[0],xmm2[0]
 ; AVX1-NEXT:    vpshufb %xmm3, %xmm0, %xmm0
 ; AVX1-NEXT:    vpshufb %xmm5, %xmm1, %xmm1
-; AVX1-NEXT:    vpor %xmm0, %xmm1, %xmm0
+; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v32i8_39_38_37_36_35_34_33_32_15_14_13_12_11_10_09_08_55_54_53_52_51_50_49_48_31_30_29_28_27_26_25_24:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[u,u,u,u,u,u,u,u,15,14,13,12,11,10,9,8,u,u,u,u,u,u,u,u,31,30,29,28,27,26,25,24]
-; AVX2-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[7,6,5,4,3,2,1,0,u,u,u,u,u,u,u,u,23,22,21,20,19,18,17,16,u,u,u,u,u,u,u,u]
 ; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8,23,22,21,20,19,18,17,16,31,30,29,28,27,26,25,24]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24>
   ret <32 x i8> %shuffle
@@ -1102,15 +1046,12 @@ define <32 x i8> @shuffle_v32i8_39_38_37_36_35_34_33_32_07_06_05_04_03_02_01_00_
 ; AVX1-LABEL: shuffle_v32i8_39_38_37_36_35_34_33_32_07_06_05_04_03_02_01_00_55_54_53_52_51_50_49_48_23_22_21_20_19_18_17_16:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT:    vmovdqa {{.*#+}} xmm3 = [128,128,128,128,128,128,128,128,7,6,5,4,3,2,1,0]
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3],xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm3 = [14,12,10,8,6,4,2,0,15,13,11,9,7,5,3,1]
 ; AVX1-NEXT:    vpshufb %xmm3, %xmm2, %xmm2
-; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm4
-; AVX1-NEXT:    vmovdqa {{.*#+}} xmm5 = [7,6,5,4,3,2,1,0,128,128,128,128,128,128,128,128]
-; AVX1-NEXT:    vpshufb %xmm5, %xmm4, %xmm4
-; AVX1-NEXT:    vpor %xmm2, %xmm4, %xmm2
+; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
 ; AVX1-NEXT:    vpshufb %xmm3, %xmm0, %xmm0
-; AVX1-NEXT:    vpshufb %xmm5, %xmm1, %xmm1
-; AVX1-NEXT:    vpor %xmm0, %xmm1, %xmm0
 ; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -1520,27 +1461,24 @@ define <32 x i8> @shuffle_v32i8_08_08_08_08_08_08_08_08_uu_uu_uu_uu_uu_uu_uu_uu_
 define <32 x i8> @shuffle_v32i8_42_45_12_13_35_35_60_40_17_22_29_44_33_12_48_51_20_19_52_19_49_54_37_32_48_42_59_07_36_34_36_39(<32 x i8> %a, <32 x i8> %b) {
 ; AVX1-LABEL: shuffle_v32i8_42_45_12_13_35_35_60_40_17_22_29_44_33_12_48_51_20_19_52_19_49_54_37_32_48_42_59_07_36_34_36_39:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm2 = zero,zero,xmm0[u],zero,xmm0[u,u,u,u,u,u,u,7,u,u,u,u]
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm4 = xmm3[4,3,u,3,u,u,u,u,u,u,u],zero,xmm3[u,u,u,u]
-; AVX1-NEXT:    vpor %xmm2, %xmm4, %xmm2
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm2 = xmm2[0,1],zero,xmm2[3],zero,zero,zero,zero,zero,zero,zero,xmm2[11],zero,zero,zero,zero
-; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm4
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm5 = xmm4[u,u,4,u,1,6],zero,zero,xmm4[0],zero,xmm4[11,u],zero,zero,zero,zero
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm6 = xmm1[u,u],zero,xmm1[u],zero,zero,xmm1[5,0],zero,xmm1[10],zero,xmm1[u,4,2,4,7]
-; AVX1-NEXT:    vpor %xmm5, %xmm6, %xmm5
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm5 = zero,zero,xmm5[2],zero,xmm5[4,5,6,7,8,9,10],zero,xmm5[12,13,14,15]
-; AVX1-NEXT:    vpor %xmm2, %xmm5, %xmm2
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm3 = xmm3[u,u],zero,zero,xmm3[u,u,u,u,1,6,13,u,u],zero,xmm3[u,u]
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[u,u,12,13,u,u,u,u],zero,zero,zero,xmm0[u,u,12,u,u]
-; AVX1-NEXT:    vpor %xmm3, %xmm0, %xmm0
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = zero,zero,xmm0[2,3],zero,zero,zero,zero,xmm0[8,9,10],zero,zero,xmm0[13],zero,zero
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm3 = zero,zero,xmm4[u,u],zero,zero,xmm4[12],zero,xmm4[u,u,u],zero,zero,xmm4[u,0,3]
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm3 = xmm2[u,u,4,u,1,6],zero,zero,xmm2[0],zero,xmm2[11,u],zero,zero,zero,zero
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm4 = xmm1[u,u],zero,xmm1[u],zero,zero,xmm1[5,0],zero,xmm1[10],zero,xmm1[u,4,2,4,7]
+; AVX1-NEXT:    vpor %xmm3, %xmm4, %xmm3
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm4
+; AVX1-NEXT:    vpunpcklbw {{.*#+}} xmm5 = xmm4[0],xmm0[0],xmm4[1],xmm0[1],xmm4[2],xmm0[2],xmm4[3],xmm0[3],xmm4[4],xmm0[4],xmm4[5],xmm0[5],xmm4[6],xmm0[6],xmm4[7],xmm0[7]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm5 = xmm5[8,6,u,6,u,u,u,u,u,u,u,15,u,u,u,u]
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm6 = [0,0,255,0,255,255,255,255,255,255,255,0,255,255,255,255]
+; AVX1-NEXT:    vpblendvb %xmm6, %xmm3, %xmm5, %xmm3
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm2 = zero,zero,xmm2[u,u],zero,zero,xmm2[12],zero,xmm2[u,u,u],zero,zero,xmm2[u,0,3]
 ; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[10,13,u,u,3,3],zero,xmm1[8,u,u,u,12,1,u],zero,zero
-; AVX1-NEXT:    vpor %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1],zero,zero,xmm1[4,5,6,7],zero,zero,zero,xmm1[11,12],zero,xmm1[14,15]
-; AVX1-NEXT:    vpor %xmm0, %xmm1, %xmm0
-; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    vpor %xmm2, %xmm1, %xmm1
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm2 = xmm4[u,u],zero,zero,xmm4[u,u,u,u,1,6,13,u,u],zero,xmm4[u,u]
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[u,u,12,13,u,u,u,u],zero,zero,zero,xmm0[u,u,12,u,u]
+; AVX1-NEXT:    vpor %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [255,255,0,0,255,255,255,255,0,0,0,255,255,0,255,255]
+; AVX1-NEXT:    vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v32i8_42_45_12_13_35_35_60_40_17_22_29_44_33_12_48_51_20_19_52_19_49_54_37_32_48_42_59_07_36_34_36_39:
@@ -1654,3 +1592,367 @@ define <32 x i8> @shuffle_v32i8_00_32_01_33_02_34_03_35_04_36_05_37_06_38_07_39_
   %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47>
   ret <32 x i8> %shuffle
 }
+
+define <32 x i8> @shuffle_v32i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_32_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_48(<32 x i8> %a) {
+; AVX1-LABEL: shuffle_v32i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_32_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_48:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0]
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_32_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_48:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> zeroinitializer, <32 x i8> %a, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 32, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 48>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_47_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_63_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(<32 x i8> %a) {
+; AVX1-LABEL: shuffle_v32i8_47_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_63_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpsrldq {{.*#+}} xmm1 = xmm0[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpsrldq {{.*#+}} xmm0 = xmm0[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_47_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_63_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpsrldq {{.*#+}} ymm0 = ymm0[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[31],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> zeroinitializer, <32 x i8> %a, <32 x i32> <i32 47, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 63, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+  ret <32 x i8> %shuffle
+}
+
+;
+; Shuffle to logical bit shifts
+;
+
+define <32 x i8> @shuffle_v32i8_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_14_zz_16_zz_18_zz_20_zz_22_zz_24_zz_26_zz_28_zz_30(<32 x i8> %a) {
+; AVX1-LABEL: shuffle_v32i8_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_14_zz_16_zz_18_zz_20_zz_22_zz_24_zz_26_zz_28_zz_30:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpsllw $8, %xmm0, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpsllw $8, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_14_zz_16_zz_18_zz_20_zz_22_zz_24_zz_26_zz_28_zz_30:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpsllw $8, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 0, i32 32, i32 2, i32 32, i32 4, i32 32, i32 6, i32 32, i32 8, i32 32, i32 10, i32 32, i32 12, i32 32, i32 14, i32 32, i32 16, i32 32, i32 18, i32 32, i32 20, i32 32, i32 22, i32 32, i32 24, i32 32, i32 26, i32 32, i32 28, i32 32, i32 30>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_zz_zz_00_01_zz_zz_04_05_zz_zz_08_09_zz_zz_12_13_zz_zz_16_17_zz_zz_20_21_zz_zz_24_25_zz_zz_28_29(<32 x i8> %a) {
+; AVX1-LABEL: shuffle_v32i8_zz_zz_00_01_zz_zz_04_05_zz_zz_08_09_zz_zz_12_13_zz_zz_16_17_zz_zz_20_21_zz_zz_24_25_zz_zz_28_29:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpslld $16, %xmm0, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpslld $16, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_zz_zz_00_01_zz_zz_04_05_zz_zz_08_09_zz_zz_12_13_zz_zz_16_17_zz_zz_20_21_zz_zz_24_25_zz_zz_28_29:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpslld $16, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 32, i32 0, i32 1, i32 32, i32 32, i32 4, i32 5, i32 32, i32 32, i32 8, i32 9, i32 32, i32 32, i32 12, i32 13, i32 32, i32 32, i32 16, i32 17, i32 32, i32 32, i32 20, i32 21, i32 32, i32 32, i32 24, i32 25, i32 32, i32 32, i32 28, i32 29>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_zz_zz_zz_zz_zz_zz_00_01_zz_zz_zz_zz_zz_zz_08_09_zz_zz_zz_zz_zz_zz_16_17_zz_zz_zz_zz_zz_zz_24_25(<32 x i8> %a) {
+; AVX1-LABEL: shuffle_v32i8_zz_zz_zz_zz_zz_zz_00_01_zz_zz_zz_zz_zz_zz_08_09_zz_zz_zz_zz_zz_zz_16_17_zz_zz_zz_zz_zz_zz_24_25:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpsllq $48, %xmm0, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpsllq $48, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_zz_zz_zz_zz_zz_zz_00_01_zz_zz_zz_zz_zz_zz_08_09_zz_zz_zz_zz_zz_zz_16_17_zz_zz_zz_zz_zz_zz_24_25:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpsllq $48, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 0, i32 1, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 8, i32 9, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 16, i32 17, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 24, i32 25>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_01_zz_03_zz_05_zz_07_zz_09_zz_11_zz_13_zz_15_zz_17_zz_19_zz_21_zz_23_zz_25_zz_27_zz_29_zz_31_zz(<32 x i8> %a) {
+; AVX1-LABEL: shuffle_v32i8_01_zz_03_zz_05_zz_07_zz_09_zz_11_zz_13_zz_15_zz_17_zz_19_zz_21_zz_23_zz_25_zz_27_zz_29_zz_31_zz:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpsrlw $8, %xmm0, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpsrlw $8, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_01_zz_03_zz_05_zz_07_zz_09_zz_11_zz_13_zz_15_zz_17_zz_19_zz_21_zz_23_zz_25_zz_27_zz_29_zz_31_zz:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpsrlw $8, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 1, i32 32, i32 3, i32 32, i32 5, i32 32, i32 7, i32 32, i32 9, i32 32, i32 11, i32 32, i32 13, i32 32, i32 15, i32 32, i32 17, i32 32, i32 19, i32 32, i32 21, i32 32, i32 23, i32 32, i32 25, i32 32, i32 27, i32 32, i32 29, i32 32, i32 31, i32 32>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_zz_18_19_zz_zz_22_23_zz_zz_26_27_zz_zz_30_31_zz_zz(<32 x i8> %a) {
+; AVX1-LABEL: shuffle_v32i8_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_zz_18_19_zz_zz_22_23_zz_zz_26_27_zz_zz_30_31_zz_zz:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpsrld $16, %xmm0, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpsrld $16, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_zz_18_19_zz_zz_22_23_zz_zz_26_27_zz_zz_30_31_zz_zz:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpsrld $16, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 2, i32 3, i32 32, i32 32, i32 6, i32 7, i32 32, i32 32, i32 10, i32 11, i32 32, i32 32, i32 14, i32 15, i32 32, i32 32, i32 18, i32 19, i32 32, i32 32, i32 22, i32 23, i32 32, i32 32, i32 26, i32 27, i32 32, i32 32, i32 30, i32 31, i32 32, i32 32>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_07_zz_zz_zz_zz_zz_zz_zz_15_zz_zz_zz_zz_z_zz_zz_23_zz_zz_zz_zz_zz_zz_zz_31_zz_zz_zz_zz_zz_zz_zz(<32 x i8> %a) {
+; AVX1-LABEL: shuffle_v32i8_07_zz_zz_zz_zz_zz_zz_zz_15_zz_zz_zz_zz_z_zz_zz_23_zz_zz_zz_zz_zz_zz_zz_31_zz_zz_zz_zz_zz_zz_zz:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpsrlq $56, %xmm0, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpsrlq $56, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_07_zz_zz_zz_zz_zz_zz_zz_15_zz_zz_zz_zz_z_zz_zz_23_zz_zz_zz_zz_zz_zz_zz_31_zz_zz_zz_zz_zz_zz_zz:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpsrlq $56, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 7, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 15, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 23, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 31, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_32_zz_zz_zz_zz_zz_zz_zz_33_zz_zz_zz_zz_zz_zz_zz_34_zz_zz_zz_zz_zz_zz_zz_35_zz_zz_zz_zz_zz_zz_zz(<32 x i8> %a) {
+; AVX1-LABEL: shuffle_v32i8_32_zz_zz_zz_zz_zz_zz_zz_33_zz_zz_zz_zz_zz_zz_zz_34_zz_zz_zz_zz_zz_zz_zz_35_zz_zz_zz_zz_zz_zz_zz:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpmovzxbq {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_32_zz_zz_zz_zz_zz_zz_zz_33_zz_zz_zz_zz_zz_zz_zz_34_zz_zz_zz_zz_zz_zz_zz_35_zz_zz_zz_zz_zz_zz_zz:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
+; AVX2-NEXT:    retq
+
+  %shuffle = shufflevector <32 x i8> zeroinitializer, <32 x i8> %a, <32 x i32> <i32 32, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 33, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 34, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 35, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_32_zz_zz_zz_33_zz_zz_zz_34_zz_zz_zz_35_zz_zz_zz_36_zz_zz_zz_37_zz_zz_zz_38_zz_zz_zz_39_zz_zz_zz(<32 x i8> %a) {
+; AVX1-LABEL: shuffle_v32i8_32_zz_zz_zz_33_zz_zz_zz_34_zz_zz_zz_35_zz_zz_zz_36_zz_zz_zz_37_zz_zz_zz_38_zz_zz_zz_39_zz_zz_zz:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_32_zz_zz_zz_33_zz_zz_zz_34_zz_zz_zz_35_zz_zz_zz_36_zz_zz_zz_37_zz_zz_zz_38_zz_zz_zz_39_zz_zz_zz:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> zeroinitializer, <32 x i8> %a, <32 x i32> <i32 32, i32 0, i32 0, i32 0, i32 33, i32 0, i32 0, i32 0, i32 34, i32 0, i32 0, i32 0, i32 35, i32 0, i32 0, i32 0, i32 36, i32 0, i32 0, i32 0, i32 37, i32 0, i32 0, i32 0, i32 38, i32 0, i32 0, i32 0, i32 39, i32 0, i32 0, i32 0>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_32_zz_33_zz_34_zz_35_zz_36_zz_37_zz_38_zz_39_zz_40_zz_41_zz_42_zz_43_zz_44_zz_45_zz_46_zz_47_zz(<32 x i8> %a) {
+; AVX1-LABEL: shuffle_v32i8_32_zz_33_zz_34_zz_35_zz_36_zz_37_zz_38_zz_39_zz_40_zz_41_zz_42_zz_43_zz_44_zz_45_zz_46_zz_47_zz:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_32_zz_33_zz_34_zz_35_zz_36_zz_37_zz_38_zz_39_zz_40_zz_41_zz_42_zz_43_zz_44_zz_45_zz_46_zz_47_zz:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> zeroinitializer, <32 x i8> %a, <32 x i32> <i32 32, i32 0, i32 33, i32 0, i32 34, i32 0, i32 35, i32 0, i32 36, i32 0, i32 37, i32 0, i32 38, i32 0, i32 39, i32 0, i32 40, i32 0, i32 41, i32 0, i32 42, i32 0, i32 43, i32 0, i32 44, i32 0, i32 45, i32 0, i32 46, i32 0, i32 47, i32 0>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_47_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_63_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30(<32 x i8> %a, <32 x i8> %b) {
+; AVX1-LABEL: shuffle_v32i8_47_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_63_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[15],xmm3[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm1[15],xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_47_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_63_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm1[15],ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14],ymm1[31],ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 47, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 63, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_uu_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_63_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30(<32 x i8> %a, <32 x i8> %b) {
+; AVX1-LABEL: shuffle_v32i8_uu_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_63_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[15],xmm2[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm0 = zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_uu_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_63_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm1[15],ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14],ymm1[31],ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 63, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_47_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_uu_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30(<32 x i8> %a, <32 x i8> %b) {
+; AVX1-LABEL: shuffle_v32i8_47_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_uu_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[15],xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm0 = zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_47_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_uu_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm1[15],ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14],ymm1[31],ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 47, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 undef, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_uu_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_63_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu(<32 x i8> %a, <32 x i8> %b) {
+; AVX1-LABEL: shuffle_v32i8_uu_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_63_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpslldq {{.*#+}} xmm0 = zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT:    vpsrldq {{.*#+}} xmm1 = xmm1[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_uu_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_63_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm1[15],ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14],ymm1[31],ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 63, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_63_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30(<32 x i8> %a, <32 x i8> %b) {
+; AVX1-LABEL: shuffle_v32i8_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_63_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm1[15],xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_63_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm1[15],ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14],ymm1[31],ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 63, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_01_02_03_04_05_06_07_08_09_10_11_12_13_14_15_32_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_48(<32 x i8> %a, <32 x i8> %b) {
+; AVX1-LABEL: shuffle_v32i8_01_02_03_04_05_06_07_08_09_10_11_12_13_14_15_32_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_48:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],xmm3[0]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],xmm1[0]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_01_02_03_04_05_06_07_08_09_10_11_12_13_14_15_32_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_48:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0],ymm0[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_33_34_35_36_37_38_39_40_41_42_43_44_45_46_47_00_49_50_51_52_53_54_55_56_57_58_59_60_61_62_63_16(<32 x i8> %a, <32 x i8> %b) {
+; AVX1-LABEL: shuffle_v32i8_33_34_35_36_37_38_39_40_41_42_43_44_45_46_47_00_49_50_51_52_53_54_55_56_57_58_59_60_61_62_63_16:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],xmm3[0]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm1[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],xmm0[0]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_33_34_35_36_37_38_39_40_41_42_43_44_45_46_47_00_49_50_51_52_53_54_55_56_57_58_59_60_61_62_63_16:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm1[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm0[0],ymm1[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm0[16]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 00, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 16>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_15_32_33_34_35_36_37_38_39_40_41_42_43_44_45_46_31_48_49_50_51_52_53_54_55_56_57_58_59_60_61_62(<32 x i8> %a, <32 x i8> %b) {
+; AVX1-LABEL: shuffle_v32i8_15_32_33_34_35_36_37_38_39_40_41_42_43_44_45_46_31_48_49_50_51_52_53_54_55_56_57_58_59_60_61_62:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm2 = xmm2[15],xmm3[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[15],xmm1[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_15_32_33_34_35_36_37_38_39_40_41_42_43_44_45_46_31_48_49_50_51_52_53_54_55_56_57_58_59_60_61_62:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[15],ymm1[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14],ymm0[31],ymm1[16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_01_02_03_04_05_06_07_08_09_10_11_12_13_14_15_00_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_16(<32 x i8> %a, <32 x i8> %b) {
+; AVX1-LABEL: shuffle_v32i8_01_02_03_04_05_06_07_08_09_10_11_12_13_14_15_00_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_16:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm1 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0]
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_01_02_03_04_05_06_07_08_09_10_11_12_13_14_15_00_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_16:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,16]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 16>
+  ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @shuffle_v32i8_15_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_31_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30(<32 x i8> %a, <32 x i8> %b) {
+; AVX1-LABEL: shuffle_v32i8_15_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_31_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm1 = xmm0[15,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[15,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v32i8_15_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_31_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[15,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,31,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 31, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>
+  ret <32 x i8> %shuffle
+}
diff --git a/test/CodeGen/X86/vector-shuffle-256-v4.ll b/test/CodeGen/X86/vector-shuffle-256-v4.ll
index bca7fb7a276d..1b42a637907c 100644
--- a/test/CodeGen/X86/vector-shuffle-256-v4.ll
+++ b/test/CodeGen/X86/vector-shuffle-256-v4.ll
@@ -1,12 +1,12 @@
-; RUN: llc < %s -mcpu=x86-64 -mattr=+avx -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
+; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
+; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
 
 target triple = "x86_64-unknown-unknown"
 
 define <4 x double> @shuffle_v4f64_0000(<4 x double> %a, <4 x double> %b) {
 ; AVX1-LABEL: shuffle_v4f64_0000:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -21,7 +21,7 @@ define <4 x double> @shuffle_v4f64_0000(<4 x double> %a, <4 x double> %b) {
 define <4 x double> @shuffle_v4f64_0001(<4 x double> %a, <4 x double> %b) {
 ; AVX1-LABEL: shuffle_v4f64_0001:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vunpcklpd {{.*#+}} xmm1 = xmm0[0,0]
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm1 = xmm0[0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -38,7 +38,7 @@ define <4 x double> @shuffle_v4f64_0020(<4 x double> %a, <4 x double> %b) {
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; AVX1-NEXT:    vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; AVX1-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -70,7 +70,7 @@ define <4 x double> @shuffle_v4f64_1000(<4 x double> %a, <4 x double> %b) {
 ; AVX1-LABEL: shuffle_v4f64_1000:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
-; AVX1-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -86,7 +86,7 @@ define <4 x double> @shuffle_v4f64_2200(<4 x double> %a, <4 x double> %b) {
 ; AVX1-LABEL: shuffle_v4f64_2200:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
-; AVX1-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[0,0,2,2]
+; AVX1-NEXT:    vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v4f64_2200:
@@ -101,9 +101,8 @@ define <4 x double> @shuffle_v4f64_3330(<4 x double> %a, <4 x double> %b) {
 ; AVX1-LABEL: shuffle_v4f64_3330:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX1-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm1[1,1,2,2]
-; AVX1-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[0,0,3,2]
-; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3]
+; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3]
+; AVX1-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[1,1,3,2]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v4f64_3330:
@@ -141,7 +140,7 @@ define <4 x double> @shuffle_v4f64_0023(<4 x double> %a, <4 x double> %b) {
 define <4 x double> @shuffle_v4f64_0022(<4 x double> %a, <4 x double> %b) {
 ; ALL-LABEL: shuffle_v4f64_0022:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[0,0,2,2]
+; ALL-NEXT:    vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
   ret <4 x double> %shuffle
@@ -186,7 +185,7 @@ define <4 x double> @shuffle_v4f64_1022(<4 x double> %a, <4 x double> %b) {
 define <4 x double> @shuffle_v4f64_0423(<4 x double> %a, <4 x double> %b) {
 ; AVX1-LABEL: shuffle_v4f64_0423:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm1[0,0,2,2]
+; AVX1-NEXT:    vmovddup {{.*#+}} ymm1 = ymm1[0,0,2,2]
 ; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3]
 ; AVX1-NEXT:    retq
 ;
@@ -202,8 +201,8 @@ define <4 x double> @shuffle_v4f64_0423(<4 x double> %a, <4 x double> %b) {
 define <4 x double> @shuffle_v4f64_0462(<4 x double> %a, <4 x double> %b) {
 ; ALL-LABEL: shuffle_v4f64_0462:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm1[0,0,2,2]
-; ALL-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[0,0,2,2]
+; ALL-NEXT:    vmovddup {{.*#+}} ymm1 = ymm1[0,0,2,2]
+; ALL-NEXT:    vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
 ; ALL-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3]
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 4, i32 6, i32 2>
@@ -358,10 +357,19 @@ define <4 x double> @shuffle_v4f64_0415(<4 x double> %a, <4 x double> %b) {
   ret <4 x double> %shuffle
 }
 
+define <4 x double> @shuffle_v4f64_u062(<4 x double> %a, <4 x double> %b) {
+; ALL-LABEL: shuffle_v4f64_u062:
+; ALL:       # BB#0:
+; ALL-NEXT:    vunpcklpd {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[2],ymm0[2]
+; ALL-NEXT:    retq
+  %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 undef, i32 0, i32 6, i32 2>
+  ret <4 x double> %shuffle
+}
+
 define <4 x i64> @shuffle_v4i64_0000(<4 x i64> %a, <4 x i64> %b) {
 ; AVX1-LABEL: shuffle_v4i64_0000:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -376,7 +384,7 @@ define <4 x i64> @shuffle_v4i64_0000(<4 x i64> %a, <4 x i64> %b) {
 define <4 x i64> @shuffle_v4i64_0001(<4 x i64> %a, <4 x i64> %b) {
 ; AVX1-LABEL: shuffle_v4i64_0001:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vunpcklpd {{.*#+}} xmm1 = xmm0[0,0]
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm1 = xmm0[0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -393,7 +401,7 @@ define <4 x i64> @shuffle_v4i64_0020(<4 x i64> %a, <4 x i64> %b) {
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; AVX1-NEXT:    vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; AVX1-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -441,7 +449,7 @@ define <4 x i64> @shuffle_v4i64_1000(<4 x i64> %a, <4 x i64> %b) {
 ; AVX1-LABEL: shuffle_v4i64_1000:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
-; AVX1-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -457,7 +465,7 @@ define <4 x i64> @shuffle_v4i64_2200(<4 x i64> %a, <4 x i64> %b) {
 ; AVX1-LABEL: shuffle_v4i64_2200:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
-; AVX1-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[0,0,2,2]
+; AVX1-NEXT:    vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v4i64_2200:
@@ -472,9 +480,8 @@ define <4 x i64> @shuffle_v4i64_3330(<4 x i64> %a, <4 x i64> %b) {
 ; AVX1-LABEL: shuffle_v4i64_3330:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX1-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm1[1,1,2,2]
-; AVX1-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[0,0,3,2]
-; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3]
+; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3]
+; AVX1-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[1,1,3,2]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v4i64_3330:
@@ -503,7 +510,7 @@ define <4 x i64> @shuffle_v4i64_3210(<4 x i64> %a, <4 x i64> %b) {
 define <4 x i64> @shuffle_v4i64_0124(<4 x i64> %a, <4 x i64> %b) {
 ; AVX1-LABEL: shuffle_v4i64_0124:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vunpcklpd {{.*#+}} xmm1 = xmm1[0,0]
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm1 = xmm1[0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm1
 ; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3]
 ; AVX1-NEXT:    retq
@@ -541,7 +548,7 @@ define <4 x i64> @shuffle_v4i64_0412(<4 x i64> %a, <4 x i64> %b) {
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
 ; AVX1-NEXT:    vshufpd {{.*#+}} xmm2 = xmm0[1],xmm2[0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
-; AVX1-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm1[0,0,2,2]
+; AVX1-NEXT:    vmovddup {{.*#+}} ymm1 = ymm1[0,0,2,2]
 ; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3]
 ; AVX1-NEXT:    retq
 ;
@@ -560,7 +567,7 @@ define <4 x i64> @shuffle_v4i64_4012(<4 x i64> %a, <4 x i64> %b) {
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
 ; AVX1-NEXT:    vshufpd {{.*#+}} xmm2 = xmm0[1],xmm2[0]
-; AVX1-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
 ; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3]
 ; AVX1-NEXT:    retq
@@ -638,9 +645,8 @@ define <4 x i64> @shuffle_v4i64_2u35(<4 x i64> %a, <4 x i64> %b) {
 ;
 ; AVX2-LABEL: shuffle_v4i64_2u35:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm1, %ymm1
-; AVX2-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[2,1,3,3]
-; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6,7]
+; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5,6,7]
+; AVX2-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[2,1,3,1]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 2, i32 undef, i32 3, i32 5>
   ret <4 x i64> %shuffle
@@ -748,22 +754,53 @@ define <4 x i64> @shuffle_v4i64_0415(<4 x i64> %a, <4 x i64> %b) {
   ret <4 x i64> %shuffle
 }
 
-define <4 x i64> @stress_test1(<4 x i64> %a, <4 x i64> %b) {
-; AVX1-LABEL: stress_test1:
+define <4 x i64> @shuffle_v4i64_z4z6(<4 x i64> %a) {
+; AVX1-LABEL: shuffle_v4i64_z4z6:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm1[2,3,0,1]
-; AVX1-NEXT:    vpermilpd {{.*#+}} ymm2 = ymm0[1,0,3,2]
-; AVX1-NEXT:    vblendpd {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3]
-; AVX1-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[1,1,3,2]
+; AVX1-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
+; AVX1-NEXT:    vunpcklpd {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[2],ymm0[2]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v4i64_z4z6:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5,6,7],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21,22,23]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <4 x i64> zeroinitializer, <4 x i64> %a, <4 x i32> <i32 0, i32 4, i32 0, i32 6>
+  ret <4 x i64> %shuffle
+}
+
+define <4 x i64> @shuffle_v4i64_5zuz(<4 x i64> %a) {
+; AVX1-LABEL: shuffle_v4i64_5zuz:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
 ; AVX1-NEXT:    vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
 ; AVX1-NEXT:    retq
 ;
-; AVX2-LABEL: stress_test1:
+; AVX2-LABEL: shuffle_v4i64_5zuz:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpermq {{.*#+}} ymm0 = ymm1[3,1,1,0]
-; AVX2-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[3,3,1,3]
-; AVX2-NEXT:    vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3]
+; AVX2-NEXT:    vpsrldq {{.*#+}} ymm0 = ymm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[24,25,26,27,28,29,30,31],zero,zero,zero,zero,zero,zero,zero,zero
 ; AVX2-NEXT:    retq
+  %shuffle = shufflevector <4 x i64> zeroinitializer, <4 x i64> %a, <4 x i32> <i32 5, i32 0, i32 undef, i32 0>
+  ret <4 x i64> %shuffle
+}
+
+define <4 x i64> @shuffle_v4i64_40u2(<4 x i64> %a, <4 x i64> %b) {
+; AVX1-LABEL: shuffle_v4i64_40u2:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vunpcklpd {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[2],ymm0[2]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v4i64_40u2:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpunpcklqdq {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[2],ymm0[2]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 0, i32 undef, i32 2>
+  ret <4 x i64> %shuffle
+}
+
+define <4 x i64> @stress_test1(<4 x i64> %a, <4 x i64> %b) {
+; ALL-LABEL: stress_test1:
+; ALL:         retq
   %c = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> <i32 3, i32 1, i32 1, i32 0>
   %d = shufflevector <4 x i64> %c, <4 x i64> undef, <4 x i32> <i32 3, i32 undef, i32 2, i32 undef>
   %e = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> <i32 3, i32 3, i32 1, i32 undef>
@@ -776,15 +813,11 @@ define <4 x i64> @insert_reg_and_zero_v4i64(i64 %a) {
 ; AVX1-LABEL: insert_reg_and_zero_v4i64:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vmovq %rdi, %xmm0
-; AVX1-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
-; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: insert_reg_and_zero_v4i64:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vmovq %rdi, %xmm0
-; AVX2-NEXT:    vpxor %ymm1, %ymm1, %ymm1
-; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
 ; AVX2-NEXT:    retq
   %v = insertelement <4 x i64> undef, i64 %a, i64 0
   %shuffle = shufflevector <4 x i64> %v, <4 x i64> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
@@ -794,18 +827,14 @@ define <4 x i64> @insert_reg_and_zero_v4i64(i64 %a) {
 define <4 x i64> @insert_mem_and_zero_v4i64(i64* %ptr) {
 ; AVX1-LABEL: insert_mem_and_zero_v4i64:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vmovq (%rdi), %xmm0
-; AVX1-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
-; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
+; AVX1-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: insert_mem_and_zero_v4i64:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vmovq (%rdi), %xmm0
-; AVX2-NEXT:    vpxor %ymm1, %ymm1, %ymm1
-; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX2-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero
 ; AVX2-NEXT:    retq
-  %a = load i64* %ptr
+  %a = load i64, i64* %ptr
   %v = insertelement <4 x i64> undef, i64 %a, i64 0
   %shuffle = shufflevector <4 x i64> %v, <4 x i64> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
   ret <4 x i64> %shuffle
@@ -814,8 +843,9 @@ define <4 x i64> @insert_mem_and_zero_v4i64(i64* %ptr) {
 define <4 x double> @insert_reg_and_zero_v4f64(double %a) {
 ; ALL-LABEL: insert_reg_and_zero_v4f64:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vxorps %xmm1, %xmm1, %xmm1
-; ALL-NEXT:    vmovsd %xmm0, %xmm1, %xmm0
+; ALL-NEXT:    # kill: XMM0<def> XMM0<kill> YMM0<def>
+; ALL-NEXT:    vxorpd %ymm1, %ymm1, %ymm1
+; ALL-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
 ; ALL-NEXT:    retq
   %v = insertelement <4 x double> undef, double %a, i32 0
   %shuffle = shufflevector <4 x double> %v, <4 x double> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
@@ -825,9 +855,9 @@ define <4 x double> @insert_reg_and_zero_v4f64(double %a) {
 define <4 x double> @insert_mem_and_zero_v4f64(double* %ptr) {
 ; ALL-LABEL: insert_mem_and_zero_v4f64:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vmovsd (%rdi), %xmm0
+; ALL-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; ALL-NEXT:    retq
-  %a = load double* %ptr
+  %a = load double, double* %ptr
   %v = insertelement <4 x double> undef, double %a, i32 0
   %shuffle = shufflevector <4 x double> %v, <4 x double> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
   ret <4 x double> %shuffle
@@ -838,7 +868,7 @@ define <4 x double> @splat_mem_v4f64(double* %ptr) {
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vbroadcastsd (%rdi), %ymm0
 ; ALL-NEXT:    retq
-  %a = load double* %ptr
+  %a = load double, double* %ptr
   %v = insertelement <4 x double> undef, double %a, i32 0
   %shuffle = shufflevector <4 x double> %v, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
   ret <4 x double> %shuffle
@@ -847,15 +877,14 @@ define <4 x double> @splat_mem_v4f64(double* %ptr) {
 define <4 x i64> @splat_mem_v4i64(i64* %ptr) {
 ; AVX1-LABEL: splat_mem_v4i64:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vmovddup (%rdi), %xmm0
-; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; AVX1-NEXT:    vbroadcastsd (%rdi), %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: splat_mem_v4i64:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vbroadcastsd (%rdi), %ymm0
 ; AVX2-NEXT:    retq
-  %a = load i64* %ptr
+  %a = load i64, i64* %ptr
   %v = insertelement <4 x i64> undef, i64 %a, i64 0
   %shuffle = shufflevector <4 x i64> %v, <4 x i64> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
   ret <4 x i64> %shuffle
@@ -866,7 +895,7 @@ define <4 x double> @splat_mem_v4f64_2(double* %p) {
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vbroadcastsd (%rdi), %ymm0
 ; ALL-NEXT:    retq
-  %1 = load double* %p
+  %1 = load double, double* %p
   %2 = insertelement <2 x double> undef, double %1, i32 0
   %3 = shufflevector <2 x double> %2, <2 x double> undef, <4 x i32> zeroinitializer
   ret <4 x double> %3
@@ -875,7 +904,7 @@ define <4 x double> @splat_mem_v4f64_2(double* %p) {
 define <4 x double> @splat_v4f64(<2 x double> %r) {
 ; AVX1-LABEL: splat_v4f64:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -886,3 +915,22 @@ define <4 x double> @splat_v4f64(<2 x double> %r) {
   %1 = shufflevector <2 x double> %r, <2 x double> undef, <4 x i32> zeroinitializer
   ret <4 x double> %1
 }
+
+define <4 x double> @bitcast_v4f64_0426(<4 x double> %a, <4 x double> %b) {
+; AVX1-LABEL: bitcast_v4f64_0426:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: bitcast_v4f64_0426:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpunpcklqdq  {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
+; AVX2-NEXT:    retq
+  %shuffle64 = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 4, i32 0, i32 6, i32 2>
+  %bitcast32 = bitcast <4 x double> %shuffle64 to <8 x float>
+  %shuffle32 = shufflevector <8 x float> %bitcast32, <8 x float> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+  %bitcast16 = bitcast <8 x float> %shuffle32 to <16 x i16>
+  %shuffle16 = shufflevector <16 x i16> %bitcast16, <16 x i16> undef, <16 x i32> <i32 2, i32 3, i32 0, i32 1, i32 6, i32 7, i32 4, i32 5, i32 10, i32 11, i32 8, i32 9, i32 14, i32 15, i32 12, i32 13>
+  %bitcast64 = bitcast <16 x i16> %shuffle16 to <4 x double>
+  ret <4 x double> %bitcast64
+}
diff --git a/test/CodeGen/X86/vector-shuffle-256-v8.ll b/test/CodeGen/X86/vector-shuffle-256-v8.ll
index 77903da35583..bb07077b5559 100644
--- a/test/CodeGen/X86/vector-shuffle-256-v8.ll
+++ b/test/CodeGen/X86/vector-shuffle-256-v8.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mcpu=x86-64 -mattr=+avx -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX1
-; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX2
+; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX1
+; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX2
 
 target triple = "x86_64-unknown-unknown"
 
@@ -91,9 +91,8 @@ define <8 x float> @shuffle_v8f32_00500000(<8 x float> %a, <8 x float> %b) {
 ; AVX1-LABEL: shuffle_v8f32_00500000:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX1-NEXT:    vpermilps {{.*#+}} ymm1 = ymm1[u,u,1,u,4,4,4,4]
-; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,0,4,4,6,4]
-; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3],ymm1[4,5,6,7]
+; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
+; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[0,0,1,0,4,4,4,4]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v8f32_00500000:
@@ -109,9 +108,8 @@ define <8 x float> @shuffle_v8f32_06000000(<8 x float> %a, <8 x float> %b) {
 ; AVX1-LABEL: shuffle_v8f32_06000000:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX1-NEXT:    vpermilps {{.*#+}} ymm1 = ymm1[u,2,u,u,4,4,4,4]
-; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[0,1,0,0,4,5,4,4]
-; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3],ymm1[4,5,6,7]
+; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
+; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[0,2,0,0,4,4,4,4]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v8f32_06000000:
@@ -127,18 +125,14 @@ define <8 x float> @shuffle_v8f32_70000000(<8 x float> %a, <8 x float> %b) {
 ; AVX1-LABEL: shuffle_v8f32_70000000:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX1-NEXT:    vpermilps {{.*#+}} ymm1 = ymm1[3,u,u,u,4,4,4,4]
-; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[0,0,0,0,4,4,4,4]
-; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3],ymm1[4,5,6,7]
+; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
+; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[3,0,0,0,4,4,4,4]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v8f32_70000000:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX2-NEXT:    movl $7, %eax
-; AVX2-NEXT:    vpinsrd $0, %eax, %xmm1, %xmm1
-; AVX2-NEXT:    vpxor %ymm2, %ymm2, %ymm2
-; AVX2-NEXT:    vinserti128 $0, %xmm1, %ymm2, %ymm1
+; AVX2-NEXT:    vmovd %eax, %xmm1
 ; AVX2-NEXT:    vpermps %ymm0, %ymm1, %ymm0
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
@@ -148,7 +142,7 @@ define <8 x float> @shuffle_v8f32_70000000(<8 x float> %a, <8 x float> %b) {
 define <8 x float> @shuffle_v8f32_01014545(<8 x float> %a, <8 x float> %b) {
 ; ALL-LABEL: shuffle_v8f32_01014545:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[0,0,2,2]
+; ALL-NEXT:    vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5>
   ret <8 x float> %shuffle
@@ -202,7 +196,7 @@ define <8 x float> @shuffle_v8f32_08080808(<8 x float> %a, <8 x float> %b) {
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vpermilps {{.*#+}} xmm1 = xmm1[0,0,2,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm1, %ymm1
-; AVX1-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
 ; AVX1-NEXT:    retq
@@ -295,11 +289,11 @@ define <8 x float> @shuffle_v8f32_08192a3b(<8 x float> %a, <8 x float> %b) {
 define <8 x float> @shuffle_v8f32_08991abb(<8 x float> %a, <8 x float> %b) {
 ; AVX1-LABEL: shuffle_v8f32_08991abb:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vshufps {{.*#+}} xmm2 = xmm0[1,0],xmm1[2,0]
-; AVX1-NEXT:    vshufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[3,3]
-; AVX1-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
-; AVX1-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,1]
-; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    vshufps {{.*#+}} xmm2 = xmm0[0,0],xmm1[0,0]
+; AVX1-NEXT:    vshufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,1]
+; AVX1-NEXT:    vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
+; AVX1-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[1,2,3,3]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm2, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v8f32_08991abb:
@@ -336,7 +330,7 @@ define <8 x float> @shuffle_v8f32_091b2d3f(<8 x float> %a, <8 x float> %b) {
 define <8 x float> @shuffle_v8f32_09ab1def(<8 x float> %a, <8 x float> %b) {
 ; AVX1-LABEL: shuffle_v8f32_09ab1def:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vpermilps {{.*#+}} xmm2 = xmm0[1,1,2,3]
+; AVX1-NEXT:    vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
 ; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]
 ; AVX1-NEXT:    retq
@@ -426,7 +420,7 @@ define <8 x float> @shuffle_v8f32_00234467(<8 x float> %a, <8 x float> %b) {
 define <8 x float> @shuffle_v8f32_00224466(<8 x float> %a, <8 x float> %b) {
 ; ALL-LABEL: shuffle_v8f32_00224466:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
+; ALL-NEXT:    vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
   ret <8 x float> %shuffle
@@ -444,7 +438,7 @@ define <8 x float> @shuffle_v8f32_10325476(<8 x float> %a, <8 x float> %b) {
 define <8 x float> @shuffle_v8f32_11335577(<8 x float> %a, <8 x float> %b) {
 ; ALL-LABEL: shuffle_v8f32_11335577:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
+; ALL-NEXT:    vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
   ret <8 x float> %shuffle
@@ -775,6 +769,29 @@ define <8 x float> @shuffle_v8f32_fedc7654(<8 x float> %a, <8 x float> %b) {
   ret <8 x float> %shuffle
 }
 
+define <8 x float> @PR21138(<8 x float> %truc, <8 x float> %tchose) {
+; AVX1-LABEL: PR21138:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vshufps {{.*#+}} xmm1 = xmm1[1,3],xmm2[1,3]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm1
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm2[1,3]
+; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: PR21138:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vmovaps {{.*#+}} ymm2 = <u,u,u,u,1,3,5,7>
+; AVX2-NEXT:    vpermps %ymm1, %ymm2, %ymm1
+; AVX2-NEXT:    vmovaps {{.*#+}} ymm2 = <1,3,5,7,u,u,u,u>
+; AVX2-NEXT:    vpermps %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <8 x float> %truc, <8 x float> %tchose, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+  ret <8 x float> %shuffle
+}
+
 define <8 x float> @shuffle_v8f32_ba987654(<8 x float> %a, <8 x float> %b) {
 ; ALL-LABEL: shuffle_v8f32_ba987654:
 ; ALL:       # BB#0:
@@ -795,6 +812,24 @@ define <8 x float> @shuffle_v8f32_ba983210(<8 x float> %a, <8 x float> %b) {
   ret <8 x float> %shuffle
 }
 
+define <8 x float> @shuffle_v8f32_80u1c4u5(<8 x float> %a, <8 x float> %b) {
+; ALL-LABEL: shuffle_v8f32_80u1c4u5:
+; ALL:       # BB#0:
+; ALL-NEXT:    vunpcklps {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[4],ymm0[4],ymm1[5],ymm0[5]
+; ALL-NEXT:    retq
+  %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 8, i32 0, i32 undef, i32 1, i32 12, i32 4, i32 undef, i32 5>
+  ret <8 x float> %shuffle
+}
+
+define <8 x float> @shuffle_v8f32_a2u3e6f7(<8 x float> %a, <8 x float> %b) {
+; ALL-LABEL: shuffle_v8f32_a2u3e6f7:
+; ALL:       # BB#0:
+; ALL-NEXT:    vunpckhps {{.*#+}} ymm0 = ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[6],ymm0[6],ymm1[7],ymm0[7]
+; ALL-NEXT:    retq
+  %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 10, i32 2, i32 undef, i32 3, i32 14, i32 6, i32 15, i32 7>
+  ret <8 x float> %shuffle
+}
+
 define <8 x i32> @shuffle_v8i32_00000000(<8 x i32> %a, <8 x i32> %b) {
 ; AVX1-LABEL: shuffle_v8i32_00000000:
 ; AVX1:       # BB#0:
@@ -883,9 +918,8 @@ define <8 x i32> @shuffle_v8i32_00500000(<8 x i32> %a, <8 x i32> %b) {
 ; AVX1-LABEL: shuffle_v8i32_00500000:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX1-NEXT:    vpermilps {{.*#+}} ymm1 = ymm1[u,u,1,u,4,4,4,4]
-; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,0,4,4,6,4]
-; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3],ymm1[4,5,6,7]
+; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
+; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[0,0,1,0,4,4,4,4]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v8i32_00500000:
@@ -901,9 +935,8 @@ define <8 x i32> @shuffle_v8i32_06000000(<8 x i32> %a, <8 x i32> %b) {
 ; AVX1-LABEL: shuffle_v8i32_06000000:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX1-NEXT:    vpermilps {{.*#+}} ymm1 = ymm1[u,2,u,u,4,4,4,4]
-; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[0,1,0,0,4,5,4,4]
-; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3],ymm1[4,5,6,7]
+; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
+; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[0,2,0,0,4,4,4,4]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v8i32_06000000:
@@ -919,18 +952,14 @@ define <8 x i32> @shuffle_v8i32_70000000(<8 x i32> %a, <8 x i32> %b) {
 ; AVX1-LABEL: shuffle_v8i32_70000000:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
-; AVX1-NEXT:    vpermilps {{.*#+}} ymm1 = ymm1[3,u,u,u,4,4,4,4]
-; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[0,0,0,0,4,4,4,4]
-; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3],ymm1[4,5,6,7]
+; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
+; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[3,0,0,0,4,4,4,4]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v8i32_70000000:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX2-NEXT:    movl $7, %eax
-; AVX2-NEXT:    vpinsrd $0, %eax, %xmm1, %xmm1
-; AVX2-NEXT:    vpxor %ymm2, %ymm2, %ymm2
-; AVX2-NEXT:    vinserti128 $0, %xmm1, %ymm2, %ymm1
+; AVX2-NEXT:    vmovd %eax, %xmm1
 ; AVX2-NEXT:    vpermd %ymm0, %ymm1, %ymm0
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
@@ -940,7 +969,7 @@ define <8 x i32> @shuffle_v8i32_70000000(<8 x i32> %a, <8 x i32> %b) {
 define <8 x i32> @shuffle_v8i32_01014545(<8 x i32> %a, <8 x i32> %b) {
 ; AVX1-LABEL: shuffle_v8i32_01014545:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[0,0,2,2]
+; AVX1-NEXT:    vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v8i32_01014545:
@@ -954,8 +983,8 @@ define <8 x i32> @shuffle_v8i32_01014545(<8 x i32> %a, <8 x i32> %b) {
 define <8 x i32> @shuffle_v8i32_00112233(<8 x i32> %a, <8 x i32> %b) {
 ; AVX1-LABEL: shuffle_v8i32_00112233:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vunpcklps {{.*#+}} xmm1 = xmm0[0,0,1,1]
-; AVX1-NEXT:    vunpckhps {{.*#+}} xmm0 = xmm0[2,2,3,3]
+; AVX1-NEXT:    vpermilps {{.*#+}} xmm1 = xmm0[0,0,1,1]
+; AVX1-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
 ;
@@ -1004,7 +1033,7 @@ define <8 x i32> @shuffle_v8i32_08080808(<8 x i32> %a, <8 x i32> %b) {
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vpermilps {{.*#+}} xmm1 = xmm1[0,0,2,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm1, %ymm1
-; AVX1-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
 ; AVX1-NEXT:    retq
@@ -1059,9 +1088,8 @@ define <8 x i32> @shuffle_v8i32_9832dc76(<8 x i32> %a, <8 x i32> %b) {
 ;
 ; AVX2-LABEL: shuffle_v8i32_9832dc76:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[0,1,3,2,4,5,7,6]
-; AVX2-NEXT:    vpshufd {{.*#+}} ymm1 = ymm1[1,0,2,3,5,4,6,7]
 ; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
+; AVX2-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[1,0,3,2,5,4,7,6]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 9, i32 8, i32 3, i32 2, i32 13, i32 12, i32 7, i32 6>
   ret <8 x i32> %shuffle
@@ -1123,8 +1151,7 @@ define <8 x i32> @shuffle_v8i32_08192a3b(<8 x i32> %a, <8 x i32> %b) {
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = <u,0,u,1,u,2,u,3>
 ; AVX2-NEXT:    vpermd %ymm1, %ymm2, %ymm1
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = <0,u,1,u,2,u,3,u>
-; AVX2-NEXT:    vpermd %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
 ; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
@@ -1134,11 +1161,11 @@ define <8 x i32> @shuffle_v8i32_08192a3b(<8 x i32> %a, <8 x i32> %b) {
 define <8 x i32> @shuffle_v8i32_08991abb(<8 x i32> %a, <8 x i32> %b) {
 ; AVX1-LABEL: shuffle_v8i32_08991abb:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vshufps {{.*#+}} xmm2 = xmm0[1,0],xmm1[2,0]
-; AVX1-NEXT:    vshufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[3,3]
-; AVX1-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
-; AVX1-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,1]
-; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    vshufps {{.*#+}} xmm2 = xmm0[0,0],xmm1[0,0]
+; AVX1-NEXT:    vshufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,1]
+; AVX1-NEXT:    vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
+; AVX1-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[1,2,3,3]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm2, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v8i32_08991abb:
@@ -1164,8 +1191,7 @@ define <8 x i32> @shuffle_v8i32_091b2d3f(<8 x i32> %a, <8 x i32> %b) {
 ;
 ; AVX2-LABEL: shuffle_v8i32_091b2d3f:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = <0,u,1,u,2,u,3,u>
-; AVX2-NEXT:    vpermd %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
 ; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
 ; AVX2-NEXT:    retq
   %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 9, i32 1, i32 11, i32 2, i32 13, i32 3, i32 15>
@@ -1175,7 +1201,7 @@ define <8 x i32> @shuffle_v8i32_091b2d3f(<8 x i32> %a, <8 x i32> %b) {
 define <8 x i32> @shuffle_v8i32_09ab1def(<8 x i32> %a, <8 x i32> %b) {
 ; AVX1-LABEL: shuffle_v8i32_09ab1def:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vpermilps {{.*#+}} xmm2 = xmm0[1,1,2,3]
+; AVX1-NEXT:    vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
 ; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]
 ; AVX1-NEXT:    retq
@@ -1305,7 +1331,7 @@ define <8 x i32> @shuffle_v8i32_00234467(<8 x i32> %a, <8 x i32> %b) {
 define <8 x i32> @shuffle_v8i32_00224466(<8 x i32> %a, <8 x i32> %b) {
 ; AVX1-LABEL: shuffle_v8i32_00224466:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
+; AVX1-NEXT:    vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v8i32_00224466:
@@ -1333,7 +1359,7 @@ define <8 x i32> @shuffle_v8i32_10325476(<8 x i32> %a, <8 x i32> %b) {
 define <8 x i32> @shuffle_v8i32_11335577(<8 x i32> %a, <8 x i32> %b) {
 ; AVX1-LABEL: shuffle_v8i32_11335577:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
+; AVX1-NEXT:    vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: shuffle_v8i32_11335577:
@@ -1824,12 +1850,57 @@ define <8 x i32> @shuffle_v8i32_ba983210(<8 x i32> %a, <8 x i32> %b) {
   ret <8 x i32> %shuffle
 }
 
+define <8 x i32> @shuffle_v8i32_zuu8zuuc(<8 x i32> %a) {
+; AVX1-LABEL: shuffle_v8i32_zuu8zuuc:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vxorps %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vshufps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,0],ymm1[4,5],ymm0[6,4]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v8i32_zuu8zuuc:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <8 x i32> zeroinitializer, <8 x i32> %a, <8 x i32> <i32 0, i32 undef, i32 undef, i32 8, i32 0, i32 undef, i32 undef, i32 12>
+  ret <8 x i32> %shuffle
+}
+
+define <8 x i32> @shuffle_v8i32_9ubzdefz(<8 x i32> %a) {
+; AVX1-LABEL: shuffle_v8i32_9ubzdefz:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vxorps %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vshufps {{.*#+}} ymm1 = ymm1[3,0],ymm0[3,0],ymm1[7,4],ymm0[7,4]
+; AVX1-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[1,2],ymm1[2,0],ymm0[5,6],ymm1[6,4]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v8i32_9ubzdefz:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpsrldq {{.*#+}} ymm0 = ymm0[4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,ymm0[20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero,zero
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <8 x i32> zeroinitializer, <8 x i32> %a, <8 x i32> <i32 9, i32 undef, i32 11, i32 0, i32 13, i32 14, i32 15, i32 0>
+  ret <8 x i32> %shuffle
+}
+
+define <8 x i32> @shuffle_v8i32_80u1b4uu(<8 x i32> %a, <8 x i32> %b) {
+; AVX1-LABEL: shuffle_v8i32_80u1b4uu:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vunpcklps {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[4],ymm0[4],ymm1[5],ymm0[5]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v8i32_80u1b4uu:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpunpckldq {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[4],ymm0[4],ymm1[5],ymm0[5]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 8, i32 0, i32 undef, i32 1, i32 12, i32 4, i32 undef, i32 undef>
+  ret <8 x i32> %shuffle
+}
+
 define <8 x float> @splat_mem_v8f32_2(float* %p) {
 ; ALL-LABEL: splat_mem_v8f32_2:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vbroadcastss (%rdi), %ymm0
 ; ALL-NEXT:    retq
-  %1 = load float* %p
+  %1 = load float, float* %p
   %2 = insertelement <4 x float> undef, float %1, i32 0
   %3 = shufflevector <4 x float> %2, <4 x float> undef, <8 x i32> zeroinitializer
   ret <8 x float> %3
@@ -1849,3 +1920,186 @@ define <8 x float> @splat_v8f32(<4 x float> %r) {
   %1 = shufflevector <4 x float> %r, <4 x float> undef, <8 x i32> zeroinitializer
   ret <8 x float> %1
 }
+
+;
+; Shuffle to logical bit shifts
+;
+
+define <8 x i32> @shuffle_v8i32_z0U2zUz6(<8 x i32> %a) {
+; AVX1-LABEL: shuffle_v8i32_z0U2zUz6:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vxorps %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6]
+; AVX1-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v8i32_z0U2zUz6:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpsllq $32, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <8 x i32> %a, <8 x i32> zeroinitializer, <8 x i32> <i32 8, i32 0, i32 undef, i32 2, i32 8, i32 undef, i32 8, i32 6>
+  ret <8 x i32> %shuffle
+}
+
+define <8 x i32> @shuffle_v8i32_1U3z5zUU(<8 x i32> %a) {
+; AVX1-LABEL: shuffle_v8i32_1U3z5zUU:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vxorps %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7]
+; AVX1-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[0,2,1,3,4,6,5,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v8i32_1U3z5zUU:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpsrlq $32, %ymm0, %ymm0
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <8 x i32> %a, <8 x i32> zeroinitializer, <8 x i32> <i32 1, i32 undef, i32 3, i32 8, i32 5, i32 8, i32 undef, i32 undef>
+  ret <8 x i32> %shuffle
+}
+
+define <8 x i32> @shuffle_v8i32_B012F456(<8 x i32> %a, <8 x i32> %b) {
+; AVX1-LABEL: shuffle_v8i32_B012F456:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vshufps {{.*#+}} ymm1 = ymm1[3,0],ymm0[0,0],ymm1[7,4],ymm0[4,4]
+; AVX1-NEXT:    vshufps {{.*#+}} ymm0 = ymm1[0,2],ymm0[1,2],ymm1[4,6],ymm0[5,6]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v8i32_B012F456:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm1[12,13,14,15],ymm0[0,1,2,3,4,5,6,7,8,9,10,11],ymm1[28,29,30,31],ymm0[16,17,18,19,20,21,22,23,24,25,26,27]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 11, i32 0, i32 1, i32 2, i32 15, i32 4, i32 5, i32 6>
+  ret <8 x i32> %shuffle
+}
+
+define <8 x i32> @shuffle_v8i32_1238567C(<8 x i32> %a, <8 x i32> %b) {
+; AVX1-LABEL: shuffle_v8i32_1238567C:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vshufps {{.*#+}} ymm1 = ymm1[0,0],ymm0[3,0],ymm1[4,4],ymm0[7,4]
+; AVX1-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[1,2],ymm1[2,0],ymm0[5,6],ymm1[6,4]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v8i32_1238567C:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0,1,2,3],ymm0[20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16,17,18,19]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 7, i32 12>
+  ret <8 x i32> %shuffle
+}
+
+define <8 x i32> @shuffle_v8i32_9AB0DEF4(<8 x i32> %a, <8 x i32> %b) {
+; AVX1-LABEL: shuffle_v8i32_9AB0DEF4:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[0,0],ymm1[3,0],ymm0[4,4],ymm1[7,4]
+; AVX1-NEXT:    vshufps {{.*#+}} ymm0 = ymm1[1,2],ymm0[2,0],ymm1[5,6],ymm0[6,4]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v8i32_9AB0DEF4:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm1[4,5,6,7,8,9,10,11,12,13,14,15],ymm0[0,1,2,3],ymm1[20,21,22,23,24,25,26,27,28,29,30,31],ymm0[16,17,18,19]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 9, i32 10, i32 11, i32 0, i32 13, i32 14, i32 15, i32 4>
+  ret <8 x i32> %shuffle
+}
+
+define <8 x i32> @shuffle_v8i32_389A7CDE(<8 x i32> %a, <8 x i32> %b) {
+; AVX1-LABEL: shuffle_v8i32_389A7CDE:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[3,0],ymm1[0,0],ymm0[7,4],ymm1[4,4]
+; AVX1-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm1[1,2],ymm0[4,6],ymm1[5,6]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v8i32_389A7CDE:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[12,13,14,15],ymm1[0,1,2,3,4,5,6,7,8,9,10,11],ymm0[28,29,30,31],ymm1[16,17,18,19,20,21,22,23,24,25,26,27]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 8, i32 9, i32 10, i32 7, i32 12, i32 13, i32 14>
+  ret <8 x i32> %shuffle
+}
+
+define <8 x i32> @shuffle_v8i32_30127456(<8 x i32> %a, <8 x i32> %b) {
+; AVX1-LABEL: shuffle_v8i32_30127456:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[3,0,1,2,7,4,5,6]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v8i32_30127456:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[3,0,1,2,7,4,5,6]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6>
+  ret <8 x i32> %shuffle
+}
+
+define <8 x i32> @shuffle_v8i32_12305674(<8 x i32> %a, <8 x i32> %b) {
+; AVX1-LABEL: shuffle_v8i32_12305674:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[1,2,3,0,5,6,7,4]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuffle_v8i32_12305674:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[1,2,3,0,5,6,7,4]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 2, i32 3, i32 0, i32 5, i32 6, i32 7, i32 4>
+  ret <8 x i32> %shuffle
+}
+
+define <8x float> @concat_v2f32_1(<2 x float>* %tmp64, <2 x float>* %tmp65) {
+; ALL-LABEL: concat_v2f32_1:
+; ALL:       # BB#0: # %entry
+; ALL-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero
+; ALL-NEXT:    vmovhpd (%rsi), %xmm0, %xmm0
+; ALL-NEXT:    retq
+entry:
+  %tmp74 = load <2 x float>, <2 x float>* %tmp65, align 8
+  %tmp72 = load <2 x float>, <2 x float>* %tmp64, align 8
+  %tmp73 = shufflevector <2 x float> %tmp72, <2 x float> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %tmp75 = shufflevector <2 x float> %tmp74, <2 x float> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %tmp76 = shufflevector <8 x float> %tmp73, <8 x float> %tmp75, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <8 x float> %tmp76
+}
+
+define <8x float> @concat_v2f32_2(<2 x float>* %tmp64, <2 x float>* %tmp65) {
+; ALL-LABEL: concat_v2f32_2:
+; ALL:       # BB#0: # %entry
+; ALL-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero
+; ALL-NEXT:    vmovhpd (%rsi), %xmm0, %xmm0
+; ALL-NEXT:    retq
+entry:
+  %tmp74 = load <2 x float>, <2 x float>* %tmp65, align 8
+  %tmp72 = load <2 x float>, <2 x float>* %tmp64, align 8
+  %tmp76 = shufflevector <2 x float> %tmp72, <2 x float> %tmp74, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <8 x float> %tmp76
+}
+
+define <8x float> @concat_v2f32_3(<2 x float>* %tmp64, <2 x float>* %tmp65) {
+; ALL-LABEL: concat_v2f32_3:
+; ALL:       # BB#0: # %entry
+; ALL-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero
+; ALL-NEXT:    vmovhpd (%rsi), %xmm0, %xmm0
+; ALL-NEXT:    retq
+entry:
+  %tmp74 = load <2 x float>, <2 x float>* %tmp65, align 8
+  %tmp72 = load <2 x float>, <2 x float>* %tmp64, align 8
+  %tmp76 = shufflevector <2 x float> %tmp72, <2 x float> %tmp74, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %res = shufflevector <4 x float> %tmp76, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <8 x float> %res
+}
+
+define <8 x i32> @insert_mem_and_zero_v8i32(i32* %ptr) {
+; AVX1-LABEL: insert_mem_and_zero_v8i32:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: insert_mem_and_zero_v8i32:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX2-NEXT:    retq
+  %a = load i32, i32* %ptr
+  %v = insertelement <8 x i32> undef, i32 %a, i32 0
+  %shuffle = shufflevector <8 x i32> %v, <8 x i32> zeroinitializer, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  ret <8 x i32> %shuffle
+}
+
diff --git a/test/CodeGen/X86/vector-shuffle-512-v16.ll b/test/CodeGen/X86/vector-shuffle-512-v16.ll
index 713ef7835cde..406d52406d95 100644
--- a/test/CodeGen/X86/vector-shuffle-512-v16.ll
+++ b/test/CodeGen/X86/vector-shuffle-512-v16.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512f -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512F
-; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512bw -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512BW
+; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512F
+; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512BW
 
 target triple = "x86_64-unknown-unknown"
 
diff --git a/test/CodeGen/X86/vector-shuffle-512-v8.ll b/test/CodeGen/X86/vector-shuffle-512-v8.ll
index 9edd62d7d92a..62d4af7809b6 100644
--- a/test/CodeGen/X86/vector-shuffle-512-v8.ll
+++ b/test/CodeGen/X86/vector-shuffle-512-v8.ll
@@ -1,12 +1,12 @@
-; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512f -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512F
-; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512bw -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512BW
+; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512F
+; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512BW
 
 target triple = "x86_64-unknown-unknown"
 
 define <8 x double> @shuffle_v8f64_00000000(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_00000000:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vbroadcastsd %xmm0, %zmm0 
+; ALL-NEXT:    vbroadcastsd %xmm0, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <8 x double> %shuffle
@@ -48,7 +48,7 @@ define <8 x double> @shuffle_v8f64_00003000(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_00040000(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_00040000:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
 ; ALL-NEXT:    vbroadcastsd %xmm1, %ymm1
 ; ALL-NEXT:    vbroadcastsd %xmm0, %ymm0
 ; ALL-NEXT:    vblendpd {{.*#+}} ymm1 = ymm0[0,1,2],ymm1[3]
@@ -61,10 +61,10 @@ define <8 x double> @shuffle_v8f64_00040000(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_00500000(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_00500000:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1 
-; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm1[0,1,1,3]
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
+; ALL-NEXT:    vblendpd {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2,3]
+; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm1[0,0,1,0]
 ; ALL-NEXT:    vbroadcastsd %xmm0, %ymm0
-; ALL-NEXT:    vblendpd {{.*#+}} ymm1 = ymm0[0,1],ymm1[2],ymm0[3]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 0, i32 0>
@@ -74,10 +74,10 @@ define <8 x double> @shuffle_v8f64_00500000(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_06000000(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_06000000:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1 
-; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm1[0,2,2,3]
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
+; ALL-NEXT:    vblendpd {{.*#+}} ymm1 = ymm0[0,1],ymm1[2],ymm0[3]
+; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm1[0,2,0,0]
 ; ALL-NEXT:    vbroadcastsd %xmm0, %ymm0
-; ALL-NEXT:    vblendpd {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2,3]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
@@ -87,10 +87,10 @@ define <8 x double> @shuffle_v8f64_06000000(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_70000000(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_70000000:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1 
-; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm1[3,1,2,3]
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
+; ALL-NEXT:    vblendpd {{.*#+}} ymm1 = ymm0[0,1,2],ymm1[3]
+; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm1[3,0,0,0]
 ; ALL-NEXT:    vbroadcastsd %xmm0, %ymm0
-; ALL-NEXT:    vblendpd {{.*#+}} ymm1 = ymm1[0],ymm0[1,2,3]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
@@ -100,7 +100,7 @@ define <8 x double> @shuffle_v8f64_70000000(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_01014545(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_01014545:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
 ; ALL-NEXT:    vinsertf128 $1, %xmm1, %ymm1, %ymm1
 ; ALL-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
@@ -134,8 +134,8 @@ define <8 x double> @shuffle_v8f64_00001111(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_81a3c5e7(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_81a3c5e7:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm2 
-; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm3 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm2
+; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm3
 ; ALL-NEXT:    vblendpd {{.*#+}} ymm2 = ymm3[0],ymm2[1],ymm3[2],ymm2[3]
 ; ALL-NEXT:    vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
@@ -159,9 +159,9 @@ define <8 x double> @shuffle_v8f64_08080808(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_08084c4c(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_08084c4c:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm2 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm2
 ; ALL-NEXT:    vinsertf128 $1, %xmm2, %ymm2, %ymm2
-; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm3 
+; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm3
 ; ALL-NEXT:    vbroadcastsd %xmm3, %ymm3
 ; ALL-NEXT:    vblendpd {{.*#+}} ymm2 = ymm2[0],ymm3[1],ymm2[2],ymm3[3]
 ; ALL-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
@@ -176,8 +176,8 @@ define <8 x double> @shuffle_v8f64_08084c4c(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_8823cc67(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_8823cc67:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm2 
-; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm3 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm2
+; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm3
 ; ALL-NEXT:    vbroadcastsd %xmm3, %ymm3
 ; ALL-NEXT:    vblendpd {{.*#+}} ymm2 = ymm3[0,1],ymm2[2,3]
 ; ALL-NEXT:    vbroadcastsd %xmm1, %ymm1
@@ -221,9 +221,9 @@ define <8 x double> @shuffle_v8f64_9810dc54(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_08194c5d(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_08194c5d:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm2 
+; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm2
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm2 = ymm2[0,0,2,1]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm3 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm3
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm3 = ymm3[0,1,1,3]
 ; ALL-NEXT:    vblendpd {{.*#+}} ymm2 = ymm3[0],ymm2[1],ymm3[2],ymm2[3]
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm1[0,0,2,1]
@@ -238,9 +238,9 @@ define <8 x double> @shuffle_v8f64_08194c5d(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_2a3b6e7f(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_2a3b6e7f:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm2 
+; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm2
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm2 = ymm2[0,2,2,3]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm3 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm3
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm3 = ymm3[2,1,3,3]
 ; ALL-NEXT:    vblendpd {{.*#+}} ymm2 = ymm3[0],ymm2[1],ymm3[2],ymm2[3]
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm1[0,2,2,3]
@@ -270,12 +270,11 @@ define <8 x double> @shuffle_v8f64_08192a3b(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_08991abb(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_08991abb:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vpermilpd {{.*#+}} ymm2 = ymm0[1,0,2,2]
-; ALL-NEXT:    vpermpd {{.*#+}} ymm3 = ymm1[0,2,3,3]
-; ALL-NEXT:    vblendpd {{.*#+}} ymm2 = ymm2[0],ymm3[1,2,3]
-; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm1[0,0,1,1]
-; ALL-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
-; ALL-NEXT:    vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
+; ALL-NEXT:    vpermpd {{.*#+}} ymm2 = ymm1[0,0,1,1]
+; ALL-NEXT:    vblendpd {{.*#+}} ymm2 = ymm0[0],ymm2[1,2,3]
+; ALL-NEXT:    vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3]
+; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[1,2,3,3]
+; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm2, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 8, i32 9, i32 9, i32 1, i32 10, i32 11, i32 11>
   ret <8 x double> %shuffle
@@ -284,7 +283,7 @@ define <8 x double> @shuffle_v8f64_08991abb(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_091b2d3f(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_091b2d3f:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm2 
+; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm2
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm3 = ymm0[2,1,3,3]
 ; ALL-NEXT:    vblendpd {{.*#+}} ymm2 = ymm3[0],ymm2[1],ymm3[2],ymm2[3]
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[0,1,1,3]
@@ -298,7 +297,7 @@ define <8 x double> @shuffle_v8f64_091b2d3f(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_09ab1def(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_09ab1def:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm2 
+; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm2
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm3 = ymm0[1,0,2,2]
 ; ALL-NEXT:    vblendpd {{.*#+}} ymm2 = ymm3[0],ymm2[1,2,3]
 ; ALL-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
@@ -312,7 +311,7 @@ define <8 x double> @shuffle_v8f64_00014445(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_00014445:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm0[0,0,0,1]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[0,0,0,1]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -324,7 +323,7 @@ define <8 x double> @shuffle_v8f64_00204464(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_00204464:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm0[0,0,2,0]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[0,0,2,0]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -336,7 +335,7 @@ define <8 x double> @shuffle_v8f64_03004744(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_03004744:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm0[0,3,0,0]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[0,3,0,0]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -348,7 +347,7 @@ define <8 x double> @shuffle_v8f64_10005444(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_10005444:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm0[1,0,0,0]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[1,0,0,0]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -360,7 +359,7 @@ define <8 x double> @shuffle_v8f64_22006644(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_22006644:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm0[2,2,0,0]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[2,2,0,0]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -372,7 +371,7 @@ define <8 x double> @shuffle_v8f64_33307774(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_33307774:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm0[3,3,3,0]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[3,3,3,0]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -384,7 +383,7 @@ define <8 x double> @shuffle_v8f64_32107654(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_32107654:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm0[3,2,1,0]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[3,2,1,0]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -396,7 +395,7 @@ define <8 x double> @shuffle_v8f64_00234467(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_00234467:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm0[0,0,2,3]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[0,0,2,3]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -407,9 +406,9 @@ define <8 x double> @shuffle_v8f64_00234467(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_00224466(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_00224466:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm0[0,0,2,2]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
-; ALL-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[0,0,2,2]
+; ALL-NEXT:    vmovddup {{.*#+}} ymm1 = ymm0[0,0,2,2]
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
+; ALL-NEXT:    vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
@@ -420,7 +419,7 @@ define <8 x double> @shuffle_v8f64_10325476(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_10325476:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm0[1,0,3,2]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[1,0,3,2]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -432,7 +431,7 @@ define <8 x double> @shuffle_v8f64_11335577(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_11335577:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm0[1,1,3,3]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[1,1,3,3]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -444,7 +443,7 @@ define <8 x double> @shuffle_v8f64_10235467(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_10235467:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm0[1,0,2,3]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[1,0,2,3]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -456,7 +455,7 @@ define <8 x double> @shuffle_v8f64_10225466(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_10225466:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm0[1,0,2,2]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[1,0,2,2]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -468,7 +467,7 @@ define <8 x double> @shuffle_v8f64_00015444(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_00015444:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm0[0,0,0,1]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[1,0,0,0]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -480,7 +479,7 @@ define <8 x double> @shuffle_v8f64_00204644(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_00204644:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm0[0,0,2,0]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[0,2,0,0]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -492,7 +491,7 @@ define <8 x double> @shuffle_v8f64_03004474(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_03004474:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm0[0,3,0,0]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[0,0,3,0]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -504,7 +503,7 @@ define <8 x double> @shuffle_v8f64_10004444(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_10004444:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm0[1,0,0,0]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vbroadcastsd %xmm0, %ymm0
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -516,7 +515,7 @@ define <8 x double> @shuffle_v8f64_22006446(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_22006446:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm0[2,2,0,0]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[2,0,0,2]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -528,7 +527,7 @@ define <8 x double> @shuffle_v8f64_33307474(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_33307474:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm0[3,3,3,0]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[3,0,3,0]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -540,7 +539,7 @@ define <8 x double> @shuffle_v8f64_32104567(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_32104567:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm0[3,2,1,0]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>
@@ -551,7 +550,7 @@ define <8 x double> @shuffle_v8f64_00236744(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_00236744:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm0[0,0,2,3]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[2,3,0,0]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -562,8 +561,8 @@ define <8 x double> @shuffle_v8f64_00236744(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_00226644(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_00226644:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm0[0,0,2,2]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vmovddup {{.*#+}} ymm1 = ymm0[0,0,2,2]
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[2,2,0,0]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -575,7 +574,7 @@ define <8 x double> @shuffle_v8f64_10324567(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_10324567:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm0[1,0,3,2]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 6, i32 7>
@@ -586,7 +585,7 @@ define <8 x double> @shuffle_v8f64_11334567(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_11334567:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm0[1,1,3,3]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -596,7 +595,7 @@ define <8 x double> @shuffle_v8f64_11334567(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_01235467(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_01235467:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm1[1,0,2,3]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
 ; ALL-NEXT:    retq
@@ -607,7 +606,7 @@ define <8 x double> @shuffle_v8f64_01235467(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_01235466(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_01235466:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm1[1,0,2,2]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
 ; ALL-NEXT:    retq
@@ -618,8 +617,8 @@ define <8 x double> @shuffle_v8f64_01235466(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_002u6u44(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_002u6u44:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm0[0,0,2,2]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vmovddup {{.*#+}} ymm1 = ymm0[0,0,2,2]
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[2,1,0,0]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -631,7 +630,7 @@ define <8 x double> @shuffle_v8f64_00uu66uu(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_00uu66uu:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vbroadcastsd %xmm0, %ymm1
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[2,2,2,3]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -643,7 +642,7 @@ define <8 x double> @shuffle_v8f64_103245uu(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_103245uu:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm0[1,0,3,2]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 undef, i32 undef>
@@ -654,7 +653,7 @@ define <8 x double> @shuffle_v8f64_1133uu67(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_1133uu67:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm0[1,1,3,3]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 undef, i32 undef, i32 6, i32 7>
@@ -664,7 +663,7 @@ define <8 x double> @shuffle_v8f64_1133uu67(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_0uu354uu(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_0uu354uu:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
 ; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm1[1,0,2,2]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
 ; ALL-NEXT:    retq
@@ -675,8 +674,8 @@ define <8 x double> @shuffle_v8f64_0uu354uu(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_uuu3uu66(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_uuu3uu66:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1 
-; ALL-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm1[0,0,2,2]
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
+; ALL-NEXT:    vmovddup {{.*#+}} ymm1 = ymm1[0,0,2,2]
 ; ALL-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 6, i32 6>
@@ -686,9 +685,9 @@ define <8 x double> @shuffle_v8f64_uuu3uu66(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_c348cda0(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_c348cda0:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm2 
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm2
 ; ALL-NEXT:    vperm2f128 {{.*#+}} ymm2 = ymm0[2,3],ymm2[0,1]
-; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm3 
+; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm3
 ; ALL-NEXT:    vbroadcastsd %xmm1, %ymm4
 ; ALL-NEXT:    vblendpd {{.*#+}} ymm4 = ymm3[0,1,2],ymm4[3]
 ; ALL-NEXT:    vblendpd {{.*#+}} ymm2 = ymm4[0],ymm2[1,2],ymm4[3]
@@ -704,18 +703,17 @@ define <8 x double> @shuffle_v8f64_c348cda0(<8 x double> %a, <8 x double> %b) {
 define <8 x double> @shuffle_v8f64_f511235a(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_f511235a:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vperm2f128 {{.*#+}} ymm2 = ymm0[2,3,0,1]
-; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm3 
-; ALL-NEXT:    vpermpd {{.*#+}} ymm4 = ymm3[0,1,1,3]
-; ALL-NEXT:    vblendpd {{.*#+}} ymm2 = ymm2[0,1],ymm4[2],ymm2[3]
-; ALL-NEXT:    vpermilpd {{.*#+}} ymm4 = ymm1[0,0,2,2]
-; ALL-NEXT:    vblendpd {{.*#+}} ymm2 = ymm2[0,1,2],ymm4[3]
+; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm2
+; ALL-NEXT:    vblendpd {{.*#+}} ymm3 = ymm0[0],ymm2[1],ymm0[2,3]
+; ALL-NEXT:    vpermpd {{.*#+}} ymm3 = ymm3[2,3,1,3]
+; ALL-NEXT:    vmovddup {{.*#+}} ymm4 = ymm1[0,0,2,2]
+; ALL-NEXT:    vblendpd {{.*#+}} ymm3 = ymm3[0,1,2],ymm4[3]
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[0,1,1,1]
-; ALL-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm3[1],ymm0[2,3]
-; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm1 
+; ALL-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2,3]
+; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm1
 ; ALL-NEXT:    vpermpd {{.*#+}} ymm1 = ymm1[3,1,2,3]
 ; ALL-NEXT:    vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3]
-; ALL-NEXT:    vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
+; ALL-NEXT:    vinsertf64x4 $1, %ymm3, %zmm0, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 15, i32 5, i32 1, i32 1, i32 2, i32 3, i32 5, i32 10>
   ret <8 x double> %shuffle
@@ -766,7 +764,7 @@ define <8 x i64> @shuffle_v8i64_00003000(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_00040000(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_00040000:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
 ; ALL-NEXT:    vpbroadcastq %xmm1, %ymm1
 ; ALL-NEXT:    vpbroadcastq %xmm0, %ymm0
 ; ALL-NEXT:    vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3,4,5],ymm1[6,7]
@@ -779,10 +777,10 @@ define <8 x i64> @shuffle_v8i64_00040000(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_00500000(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_00500000:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1 
-; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[0,1,1,3]
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
+; ALL-NEXT:    vpblendd {{.*#+}} ymm1 = ymm0[0,1],ymm1[2,3],ymm0[4,5,6,7]
+; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[0,0,1,0]
 ; ALL-NEXT:    vpbroadcastq %xmm0, %ymm0
-; ALL-NEXT:    vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5],ymm0[6,7]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 0, i32 0>
@@ -792,10 +790,10 @@ define <8 x i64> @shuffle_v8i64_00500000(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_06000000(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_06000000:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1 
-; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
+; ALL-NEXT:    vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5],ymm0[6,7]
+; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[0,2,0,0]
 ; ALL-NEXT:    vpbroadcastq %xmm0, %ymm0
-; ALL-NEXT:    vpblendd {{.*#+}} ymm1 = ymm0[0,1],ymm1[2,3],ymm0[4,5,6,7]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
@@ -805,10 +803,10 @@ define <8 x i64> @shuffle_v8i64_06000000(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_70000000(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_70000000:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1 
-; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[3,1,2,3]
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
+; ALL-NEXT:    vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3,4,5],ymm1[6,7]
+; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[3,0,0,0]
 ; ALL-NEXT:    vpbroadcastq %xmm0, %ymm0
-; ALL-NEXT:    vpblendd {{.*#+}} ymm1 = ymm1[0,1],ymm0[2,3,4,5,6,7]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
@@ -818,7 +816,7 @@ define <8 x i64> @shuffle_v8i64_70000000(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_01014545(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_01014545:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
 ; ALL-NEXT:    vinserti128 $1, %xmm1, %ymm1, %ymm1
 ; ALL-NEXT:    vinserti128 $1, %xmm0, %ymm0, %ymm0
 ; ALL-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
@@ -852,8 +850,8 @@ define <8 x i64> @shuffle_v8i64_00001111(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_81a3c5e7(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_81a3c5e7:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm2 
-; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm3 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm2
+; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm3
 ; ALL-NEXT:    vpblendd {{.*#+}} ymm2 = ymm3[0,1],ymm2[2,3],ymm3[4,5],ymm2[6,7]
 ; ALL-NEXT:    vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm2, %zmm0, %zmm0
@@ -877,9 +875,9 @@ define <8 x i64> @shuffle_v8i64_08080808(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_08084c4c(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_08084c4c:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm2 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm2
 ; ALL-NEXT:    vinserti128 $1, %xmm2, %ymm2, %ymm2
-; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm3 
+; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm3
 ; ALL-NEXT:    vpbroadcastq %xmm3, %ymm3
 ; ALL-NEXT:    vpblendd {{.*#+}} ymm2 = ymm2[0,1],ymm3[2,3],ymm2[4,5],ymm3[6,7]
 ; ALL-NEXT:    vinserti128 $1, %xmm0, %ymm0, %ymm0
@@ -894,8 +892,8 @@ define <8 x i64> @shuffle_v8i64_08084c4c(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_8823cc67(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_8823cc67:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm2 
-; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm3 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm2
+; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm3
 ; ALL-NEXT:    vpbroadcastq %xmm3, %ymm3
 ; ALL-NEXT:    vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7]
 ; ALL-NEXT:    vpbroadcastq %xmm1, %ymm1
@@ -939,9 +937,9 @@ define <8 x i64> @shuffle_v8i64_9810dc54(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_08194c5d(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_08194c5d:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm2 
+; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm2
 ; ALL-NEXT:    vpermq {{.*#+}} ymm2 = ymm2[0,0,2,1]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm3 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
 ; ALL-NEXT:    vpermq {{.*#+}} ymm3 = ymm3[0,1,1,3]
 ; ALL-NEXT:    vpblendd {{.*#+}} ymm2 = ymm3[0,1],ymm2[2,3],ymm3[4,5],ymm2[6,7]
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[0,0,2,1]
@@ -956,9 +954,9 @@ define <8 x i64> @shuffle_v8i64_08194c5d(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_2a3b6e7f(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_2a3b6e7f:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm2 
+; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm2
 ; ALL-NEXT:    vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm3 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
 ; ALL-NEXT:    vpermq {{.*#+}} ymm3 = ymm3[2,1,3,3]
 ; ALL-NEXT:    vpblendd {{.*#+}} ymm2 = ymm3[0,1],ymm2[2,3],ymm3[4,5],ymm2[6,7]
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
@@ -988,12 +986,11 @@ define <8 x i64> @shuffle_v8i64_08192a3b(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_08991abb(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_08991abb:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vpshufd {{.*#+}} ymm2 = ymm0[2,3,2,3,6,7,6,7]
-; ALL-NEXT:    vpermq {{.*#+}} ymm3 = ymm1[0,2,3,3]
-; ALL-NEXT:    vpblendd {{.*#+}} ymm2 = ymm2[0,1],ymm3[2,3,4,5,6,7]
-; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[0,0,1,1]
-; ALL-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
-; ALL-NEXT:    vinserti64x4 $1, %ymm2, %zmm0, %zmm0
+; ALL-NEXT:    vpermq {{.*#+}} ymm2 = ymm1[0,0,1,1]
+; ALL-NEXT:    vpblendd {{.*#+}} ymm2 = ymm0[0,1],ymm2[2,3,4,5,6,7]
+; ALL-NEXT:    vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5,6,7]
+; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[1,2,3,3]
+; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm2, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 8, i32 9, i32 9, i32 1, i32 10, i32 11, i32 11>
   ret <8 x i64> %shuffle
@@ -1002,7 +999,7 @@ define <8 x i64> @shuffle_v8i64_08991abb(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_091b2d3f(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_091b2d3f:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm2 
+; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm2
 ; ALL-NEXT:    vpermq {{.*#+}} ymm3 = ymm0[2,1,3,3]
 ; ALL-NEXT:    vpblendd {{.*#+}} ymm2 = ymm3[0,1],ymm2[2,3],ymm3[4,5],ymm2[6,7]
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,1,1,3]
@@ -1016,7 +1013,7 @@ define <8 x i64> @shuffle_v8i64_091b2d3f(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_09ab1def(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_09ab1def:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm2 
+; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm2
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm3 = ymm0[2,3,2,3,6,7,6,7]
 ; ALL-NEXT:    vpblendd {{.*#+}} ymm2 = ymm3[0,1],ymm2[2,3,4,5,6,7]
 ; ALL-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
@@ -1030,7 +1027,7 @@ define <8 x i64> @shuffle_v8i64_00014445(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_00014445:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[0,0,0,1]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,0,0,1]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1042,7 +1039,7 @@ define <8 x i64> @shuffle_v8i64_00204464(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_00204464:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[0,0,2,0]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,0,2,0]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1054,7 +1051,7 @@ define <8 x i64> @shuffle_v8i64_03004744(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_03004744:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[0,3,0,0]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,3,0,0]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1066,7 +1063,7 @@ define <8 x i64> @shuffle_v8i64_10005444(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_10005444:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[1,0,0,0]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[1,0,0,0]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1078,7 +1075,7 @@ define <8 x i64> @shuffle_v8i64_22006644(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_22006644:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[2,2,0,0]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[2,2,0,0]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1090,7 +1087,7 @@ define <8 x i64> @shuffle_v8i64_33307774(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_33307774:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[3,3,3,0]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[3,3,3,0]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1102,7 +1099,7 @@ define <8 x i64> @shuffle_v8i64_32107654(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_32107654:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[3,2,1,0]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1114,7 +1111,7 @@ define <8 x i64> @shuffle_v8i64_00234467(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_00234467:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[0,0,2,3]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,0,2,3]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1126,7 +1123,7 @@ define <8 x i64> @shuffle_v8i64_00224466(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_00224466:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm1 = ymm0[0,1,0,1,4,5,4,5]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[0,1,0,1,4,5,4,5]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1138,7 +1135,7 @@ define <8 x i64> @shuffle_v8i64_10325476(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_10325476:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm1 = ymm0[2,3,0,1,6,7,4,5]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[2,3,0,1,6,7,4,5]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1150,7 +1147,7 @@ define <8 x i64> @shuffle_v8i64_11335577(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_11335577:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm1 = ymm0[2,3,2,3,6,7,6,7]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[2,3,2,3,6,7,6,7]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1162,7 +1159,7 @@ define <8 x i64> @shuffle_v8i64_10235467(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_10235467:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[1,0,2,3]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[1,0,2,3]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1174,7 +1171,7 @@ define <8 x i64> @shuffle_v8i64_10225466(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_10225466:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[1,0,2,2]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[1,0,2,2]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1186,7 +1183,7 @@ define <8 x i64> @shuffle_v8i64_00015444(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_00015444:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[0,0,0,1]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[1,0,0,0]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1198,7 +1195,7 @@ define <8 x i64> @shuffle_v8i64_00204644(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_00204644:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[0,0,2,0]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,2,0,0]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1210,7 +1207,7 @@ define <8 x i64> @shuffle_v8i64_03004474(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_03004474:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[0,3,0,0]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,0,3,0]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1222,7 +1219,7 @@ define <8 x i64> @shuffle_v8i64_10004444(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_10004444:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[1,0,0,0]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpbroadcastq %xmm0, %ymm0
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1234,7 +1231,7 @@ define <8 x i64> @shuffle_v8i64_22006446(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_22006446:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[2,2,0,0]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[2,0,0,2]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1246,7 +1243,7 @@ define <8 x i64> @shuffle_v8i64_33307474(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_33307474:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[3,3,3,0]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[3,0,3,0]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1258,7 +1255,7 @@ define <8 x i64> @shuffle_v8i64_32104567(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_32104567:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[3,2,1,0]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>
@@ -1269,7 +1266,7 @@ define <8 x i64> @shuffle_v8i64_00236744(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_00236744:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm0[0,0,2,3]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[2,3,0,0]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1281,7 +1278,7 @@ define <8 x i64> @shuffle_v8i64_00226644(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_00226644:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm1 = ymm0[0,1,0,1,4,5,4,5]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[2,2,0,0]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1293,7 +1290,7 @@ define <8 x i64> @shuffle_v8i64_10324567(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_10324567:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm1 = ymm0[2,3,0,1,6,7,4,5]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 6, i32 7>
@@ -1304,7 +1301,7 @@ define <8 x i64> @shuffle_v8i64_11334567(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_11334567:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm1 = ymm0[2,3,2,3,6,7,6,7]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -1314,7 +1311,7 @@ define <8 x i64> @shuffle_v8i64_11334567(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_01235467(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_01235467:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[1,0,2,3]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
 ; ALL-NEXT:    retq
@@ -1325,7 +1322,7 @@ define <8 x i64> @shuffle_v8i64_01235467(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_01235466(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_01235466:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
 ; ALL-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[1,0,2,2]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
 ; ALL-NEXT:    retq
@@ -1337,7 +1334,7 @@ define <8 x i64> @shuffle_v8i64_002u6u44(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_002u6u44:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm1 = ymm0[0,1,0,1,4,5,4,5]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[2,1,0,0]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1349,7 +1346,7 @@ define <8 x i64> @shuffle_v8i64_00uu66uu(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_00uu66uu:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpbroadcastq %xmm0, %ymm1
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[2,2,2,3]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
@@ -1361,7 +1358,7 @@ define <8 x i64> @shuffle_v8i64_103245uu(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_103245uu:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm1 = ymm0[2,3,0,1,6,7,4,5]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 undef, i32 undef>
@@ -1372,7 +1369,7 @@ define <8 x i64> @shuffle_v8i64_1133uu67(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_1133uu67:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm1 = ymm0[2,3,2,3,6,7,6,7]
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 undef, i32 undef, i32 6, i32 7>
@@ -1382,7 +1379,7 @@ define <8 x i64> @shuffle_v8i64_1133uu67(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_0uu354uu(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_0uu354uu:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm1 = ymm1[2,3,0,1,6,7,4,5]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
 ; ALL-NEXT:    retq
@@ -1393,7 +1390,7 @@ define <8 x i64> @shuffle_v8i64_0uu354uu(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_uuu3uu66(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_uuu3uu66:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm1 = ymm1[0,1,0,1,4,5,4,5]
 ; ALL-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
 ; ALL-NEXT:    retq
@@ -1404,7 +1401,7 @@ define <8 x i64> @shuffle_v8i64_uuu3uu66(<8 x i64> %a, <8 x i64> %b) {
 define <8 x i64> @shuffle_v8i64_6caa87e5(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_6caa87e5:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
+; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; ALL-NEXT:    vperm2i128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
 ; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm2
 ; ALL-NEXT:    vpblendd {{.*#+}} ymm3 = ymm1[0,1,2,3],ymm2[4,5],ymm1[6,7]
diff --git a/test/CodeGen/X86/vector-shuffle-combining.ll b/test/CodeGen/X86/vector-shuffle-combining.ll
index 4e2bf87fdf64..92c59e2fca08 100644
--- a/test/CodeGen/X86/vector-shuffle-combining.ll
+++ b/test/CodeGen/X86/vector-shuffle-combining.ll
@@ -275,16 +275,18 @@ define <4 x i32> @combine_bitwise_ops_test6(<4 x i32> %a, <4 x i32> %b, <4 x i32
 define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
 ; SSE2-LABEL: combine_bitwise_ops_test1b:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    andps %xmm1, %xmm0
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; SSE2-NEXT:    pand %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_bitwise_ops_test1b:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    andps %xmm1, %xmm0
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; SSSE3-NEXT:    pand %xmm1, %xmm0
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_bitwise_ops_test1b:
@@ -313,16 +315,18 @@ define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i3
 define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
 ; SSE2-LABEL: combine_bitwise_ops_test2b:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    orps %xmm1, %xmm0
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; SSE2-NEXT:    por %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_bitwise_ops_test2b:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    orps %xmm1, %xmm0
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; SSSE3-NEXT:    por %xmm1, %xmm0
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_bitwise_ops_test2b:
@@ -352,17 +356,13 @@ define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i3
 ; SSE2-LABEL: combine_bitwise_ops_test3b:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    xorps %xmm1, %xmm0
-; SSE2-NEXT:    xorps %xmm1, %xmm1
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_bitwise_ops_test3b:
 ; SSSE3:       # BB#0:
 ; SSSE3-NEXT:    xorps %xmm1, %xmm0
-; SSSE3-NEXT:    xorps %xmm1, %xmm1
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_bitwise_ops_test3b:
@@ -394,18 +394,18 @@ define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i3
 define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
 ; SSE2-LABEL: combine_bitwise_ops_test4b:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    andps %xmm1, %xmm0
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
-; SSE2-NEXT:    movaps %xmm2, %xmm0
+; SSE2-NEXT:    pand %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_bitwise_ops_test4b:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    andps %xmm1, %xmm0
-; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
-; SSSE3-NEXT:    movaps %xmm2, %xmm0
+; SSSE3-NEXT:    pand %xmm1, %xmm0
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_bitwise_ops_test4b:
@@ -434,18 +434,18 @@ define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i3
 define <4 x i32> @combine_bitwise_ops_test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
 ; SSE2-LABEL: combine_bitwise_ops_test5b:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    orps %xmm1, %xmm0
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
-; SSE2-NEXT:    movaps %xmm2, %xmm0
+; SSE2-NEXT:    por %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_bitwise_ops_test5b:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    orps %xmm1, %xmm0
-; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
-; SSSE3-NEXT:    movaps %xmm2, %xmm0
+; SSSE3-NEXT:    por %xmm1, %xmm0
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_bitwise_ops_test5b:
@@ -475,19 +475,13 @@ define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i3
 ; SSE2-LABEL: combine_bitwise_ops_test6b:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    xorps %xmm1, %xmm0
-; SSE2-NEXT:    xorps %xmm1, %xmm1
-; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_bitwise_ops_test6b:
 ; SSSE3:       # BB#0:
 ; SSSE3-NEXT:    xorps %xmm1, %xmm0
-; SSSE3-NEXT:    xorps %xmm1, %xmm1
-; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
-; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_bitwise_ops_test6b:
@@ -517,17 +511,42 @@ define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i3
 }
 
 define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
-; SSE-LABEL: combine_bitwise_ops_test1c:
-; SSE:       # BB#0:
-; SSE-NEXT:    andps %xmm1, %xmm0
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
-; SSE-NEXT:    retq
+; SSE2-LABEL: combine_bitwise_ops_test1c:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    pand %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    retq
 ;
-; AVX-LABEL: combine_bitwise_ops_test1c:
-; AVX:       # BB#0:
-; AVX-NEXT:    vandps %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
-; AVX-NEXT:    retq
+; SSSE3-LABEL: combine_bitwise_ops_test1c:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    pand %xmm1, %xmm0
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
+; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: combine_bitwise_ops_test1c:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pand %xmm1, %xmm0
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: combine_bitwise_ops_test1c:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: combine_bitwise_ops_test1c:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; AVX2-NEXT:    retq
   %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
   %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
   %and = and <4 x i32> %shuf1, %shuf2
@@ -535,17 +554,42 @@ define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i3
 }
 
 define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
-; SSE-LABEL: combine_bitwise_ops_test2c:
-; SSE:       # BB#0:
-; SSE-NEXT:    orps %xmm1, %xmm0
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
-; SSE-NEXT:    retq
+; SSE2-LABEL: combine_bitwise_ops_test2c:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    por %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    retq
 ;
-; AVX-LABEL: combine_bitwise_ops_test2c:
-; AVX:       # BB#0:
-; AVX-NEXT:    vorps %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
-; AVX-NEXT:    retq
+; SSSE3-LABEL: combine_bitwise_ops_test2c:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    por %xmm1, %xmm0
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
+; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: combine_bitwise_ops_test2c:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    por %xmm1, %xmm0
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: combine_bitwise_ops_test2c:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: combine_bitwise_ops_test2c:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpor %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; AVX2-NEXT:    retq
   %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
   %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
   %or = or <4 x i32> %shuf1, %shuf2
@@ -554,29 +598,33 @@ define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i3
 
 define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
 ; SSE2-LABEL: combine_bitwise_ops_test3c:
-; SSE2:      # BB#0:
-; SSE2-NEXT:   xorps %xmm1, %xmm0
-; SSE2-NEXT:   xorps %xmm1, %xmm1
-; SSE2-NEXT:   shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
-; SSE2-NEXT:   retq
+; SSE2:       # BB#0:
+; SSE2-NEXT:    pxor %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,2]
+; SSE2-NEXT:    pxor %xmm1, %xmm1
+; SSE2-NEXT:    punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
+; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_bitwise_ops_test3c:
-; SSSE3:      # BB#0:
-; SSSE3-NEXT:   xorps %xmm1, %xmm0
-; SSSE3-NEXT:   xorps %xmm1, %xmm1
-; SSSE3-NEXT:   shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
-; SSSE3-NEXT:   retq
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    pxor %xmm1, %xmm0
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,2]
+; SSSE3-NEXT:    pxor %xmm1, %xmm1
+; SSSE3-NEXT:    punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
+; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_bitwise_ops_test3c:
-; SSE41:      # BB#0:
-; SSE41-NEXT:   xorps %xmm1, %xmm0
-; SSE41-NEXT:   insertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
-; SSE41-NEXT:   retq
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pxor %xmm1, %xmm0
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE41-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
+; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: combine_bitwise_ops_test3c:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vxorps %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
+; AVX-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; AVX-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero
 ; AVX-NEXT:    retq
   %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
   %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
@@ -585,18 +633,42 @@ define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i3
 }
 
 define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
-; SSE-LABEL: combine_bitwise_ops_test4c:
-; SSE:       # BB#0:
-; SSE-NEXT:    andps %xmm1, %xmm0
-; SSE-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
-; SSE-NEXT:    movaps %xmm2, %xmm0
-; SSE-NEXT:    retq
+; SSE2-LABEL: combine_bitwise_ops_test4c:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    pand %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    retq
 ;
-; AVX-LABEL: combine_bitwise_ops_test4c:
-; AVX:       # BB#0:
-; AVX-NEXT:    vandps %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
-; AVX-NEXT:    retq
+; SSSE3-LABEL: combine_bitwise_ops_test4c:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    pand %xmm1, %xmm0
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
+; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: combine_bitwise_ops_test4c:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pand %xmm1, %xmm0
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: combine_bitwise_ops_test4c:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: combine_bitwise_ops_test4c:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; AVX2-NEXT:    retq
   %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
   %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
   %and = and <4 x i32> %shuf1, %shuf2
@@ -604,18 +676,42 @@ define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i3
 }
 
 define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
-; SSE-LABEL: combine_bitwise_ops_test5c:
-; SSE:       # BB#0:
-; SSE-NEXT:    orps %xmm1, %xmm0
-; SSE-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
-; SSE-NEXT:    movaps %xmm2, %xmm0
-; SSE-NEXT:    retq
+; SSE2-LABEL: combine_bitwise_ops_test5c:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    por %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    retq
 ;
-; AVX-LABEL: combine_bitwise_ops_test5c:
-; AVX:       # BB#0:
-; AVX-NEXT:    vorps %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
-; AVX-NEXT:    retq
+; SSSE3-LABEL: combine_bitwise_ops_test5c:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    por %xmm1, %xmm0
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
+; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: combine_bitwise_ops_test5c:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    por %xmm1, %xmm0
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: combine_bitwise_ops_test5c:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: combine_bitwise_ops_test5c:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpor %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; AVX2-NEXT:    retq
   %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
   %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
   %or = or <4 x i32> %shuf1, %shuf2
@@ -623,20 +719,45 @@ define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i3
 }
 
 define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
-; SSE-LABEL: combine_bitwise_ops_test6c:
-; SSE:       # BB#0:
-; SSE-NEXT:    xorps %xmm1, %xmm0
-; SSE-NEXT:    xorps %xmm1, %xmm1
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
-; SSE-NEXT:    movaps %xmm1, %xmm0
-; SSE-NEXT:    retq
+; SSE2-LABEL: combine_bitwise_ops_test6c:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    pxor %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; SSE2-NEXT:    pxor %xmm0, %xmm0
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    retq
 ;
-; AVX-LABEL: combine_bitwise_ops_test6c:
-; AVX:       # BB#0:
-; AVX-NEXT:    vxorps %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[1,3]
-; AVX-NEXT:    retq
+; SSSE3-LABEL: combine_bitwise_ops_test6c:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    pxor %xmm1, %xmm0
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; SSSE3-NEXT:    pxor %xmm0, %xmm0
+; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: combine_bitwise_ops_test6c:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pxor %xmm1, %xmm0
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
+; SSE41-NEXT:    pxor %xmm0, %xmm0
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: combine_bitwise_ops_test6c:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
+; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: combine_bitwise_ops_test6c:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
+; AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
+; AVX2-NEXT:    retq
   %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
   %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
   %xor = xor <4 x i32> %shuf1, %shuf2
@@ -867,19 +988,40 @@ define <4 x i32> @combine_nested_undef_test14(<4 x i32> %A, <4 x i32> %B) {
 ; it.
 
 define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
-; SSE-LABEL: combine_nested_undef_test15:
-; SSE:       # BB#0:
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,1]
-; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
-; SSE-NEXT:    retq
+; SSE2-LABEL: combine_nested_undef_test15:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,1]
+; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    retq
 ;
-; AVX-LABEL: combine_nested_undef_test15:
-; AVX:       # BB#0:
-; AVX-NEXT:    vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[3,1]
-; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
-; AVX-NEXT:    retq
+; SSSE3-LABEL: combine_nested_undef_test15:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,1]
+; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: combine_nested_undef_test15:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: combine_nested_undef_test15:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: combine_nested_undef_test15:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpbroadcastd %xmm1, %xmm1
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
+; AVX2-NEXT:    retq
   %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
   %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
   ret <4 x i32> %2
@@ -888,34 +1030,34 @@ define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
 define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
 ; SSE2-LABEL: combine_nested_undef_test16:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,0,2,3]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_nested_undef_test16:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,0,2,3]
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_nested_undef_test16:
 ; SSE41:       # BB#0:
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
-; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: combine_nested_undef_test16:
 ; AVX1:       # BB#0:
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
-; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: combine_nested_undef_test16:
 ; AVX2:       # BB#0:
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
-; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
 ; AVX2-NEXT:    retq
   %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
   %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
@@ -923,19 +1065,35 @@ define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
 }
 
 define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
-; SSE-LABEL: combine_nested_undef_test17:
-; SSE:       # BB#0:
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
-; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
-; SSE-NEXT:    retq
+; SSE2-LABEL: combine_nested_undef_test17:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
+; SSE2-NEXT:    retq
 ;
-; AVX-LABEL: combine_nested_undef_test17:
-; AVX:       # BB#0:
-; AVX-NEXT:    vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
-; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
-; AVX-NEXT:    retq
+; SSSE3-LABEL: combine_nested_undef_test17:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: combine_nested_undef_test17:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: combine_nested_undef_test17:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: combine_nested_undef_test17:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
+; AVX2-NEXT:    retq
   %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
   %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
   ret <4 x i32> %2
@@ -957,55 +1115,107 @@ define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
 }
 
 define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
-; SSE-LABEL: combine_nested_undef_test19:
-; SSE:       # BB#0:
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
-; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
-; SSE-NEXT:    retq
+; SSE2-LABEL: combine_nested_undef_test19:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,0,0,0]
+; SSE2-NEXT:    retq
 ;
-; AVX-LABEL: combine_nested_undef_test19:
-; AVX:       # BB#0:
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
-; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
-; AVX-NEXT:    retq
+; SSSE3-LABEL: combine_nested_undef_test19:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,0,0,0]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: combine_nested_undef_test19:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,0,0,0]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: combine_nested_undef_test19:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,0,0,0]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: combine_nested_undef_test19:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,0,0,0]
+; AVX2-NEXT:    retq
   %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
   %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
   ret <4 x i32> %2
 }
 
 define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
-; SSE-LABEL: combine_nested_undef_test20:
-; SSE:       # BB#0:
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
-; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
-; SSE-NEXT:    retq
+; SSE2-LABEL: combine_nested_undef_test20:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,3]
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
+; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    retq
 ;
-; AVX-LABEL: combine_nested_undef_test20:
-; AVX:       # BB#0:
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
-; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
-; AVX-NEXT:    retq
+; SSSE3-LABEL: combine_nested_undef_test20:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,3]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
+; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: combine_nested_undef_test20:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,3,0]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: combine_nested_undef_test20:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,3,0]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: combine_nested_undef_test20:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,3,0]
+; AVX2-NEXT:    retq
   %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
   %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
   ret <4 x i32> %2
 }
 
 define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
-; SSE-LABEL: combine_nested_undef_test21:
-; SSE:       # BB#0:
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
-; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
-; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
-; SSE-NEXT:    retq
+; SSE2-LABEL: combine_nested_undef_test21:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[0,3,0,3]
+; SSE2-NEXT:    retq
 ;
-; AVX-LABEL: combine_nested_undef_test21:
-; AVX:       # BB#0:
-; AVX-NEXT:    vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
-; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
-; AVX-NEXT:    retq
+; SSSE3-LABEL: combine_nested_undef_test21:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[0,3,0,3]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: combine_nested_undef_test21:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: combine_nested_undef_test21:
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: combine_nested_undef_test21:
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
+; AVX2-NEXT:    vpbroadcastq %xmm0, %xmm0
+; AVX2-NEXT:    retq
   %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
   %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
   ret <4 x i32> %2
@@ -1148,13 +1358,13 @@ define <4 x float> @combine_test1(<4 x float> %a, <4 x float> %b) {
 define <4 x float> @combine_test2(<4 x float> %a, <4 x float> %b) {
 ; SSE2-LABEL: combine_test2:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movss %xmm0, %xmm1
+; SSE2-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE2-NEXT:    movaps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_test2:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movss %xmm0, %xmm1
+; SSSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
@@ -1206,22 +1416,14 @@ define <4 x float> @combine_test4(<4 x float> %a, <4 x float> %b) {
 define <4 x float> @combine_test5(<4 x float> %a, <4 x float> %b) {
 ; SSE2-LABEL: combine_test5:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movaps %xmm1, %xmm2
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
-; SSE2-NEXT:    movaps %xmm2, %xmm0
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_test5:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movaps %xmm1, %xmm2
-; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
-; SSSE3-NEXT:    movaps %xmm2, %xmm0
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_test5:
@@ -1256,13 +1458,13 @@ define <4 x i32> @combine_test6(<4 x i32> %a, <4 x i32> %b) {
 define <4 x i32> @combine_test7(<4 x i32> %a, <4 x i32> %b) {
 ; SSE2-LABEL: combine_test7:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movss %xmm0, %xmm1
+; SSE2-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE2-NEXT:    movaps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_test7:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movss %xmm0, %xmm1
+; SSSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
@@ -1319,22 +1521,14 @@ define <4 x i32> @combine_test9(<4 x i32> %a, <4 x i32> %b) {
 define <4 x i32> @combine_test10(<4 x i32> %a, <4 x i32> %b) {
 ; SSE2-LABEL: combine_test10:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movaps %xmm1, %xmm2
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
-; SSE2-NEXT:    movaps %xmm2, %xmm0
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_test10:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movaps %xmm1, %xmm2
-; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[2,0]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0]
-; SSSE3-NEXT:    movaps %xmm2, %xmm0
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_test10:
@@ -1368,13 +1562,13 @@ define <4 x float> @combine_test11(<4 x float> %a, <4 x float> %b) {
 define <4 x float> @combine_test12(<4 x float> %a, <4 x float> %b) {
 ; SSE2-LABEL: combine_test12:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movss %xmm0, %xmm1
+; SSE2-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE2-NEXT:    movaps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_test12:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movss %xmm0, %xmm1
+; SSSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
@@ -1425,20 +1619,14 @@ define <4 x float> @combine_test14(<4 x float> %a, <4 x float> %b) {
 define <4 x float> @combine_test15(<4 x float> %a, <4 x float> %b) {
 ; SSE2-LABEL: combine_test15:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movaps %xmm0, %xmm2
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_test15:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movaps %xmm0, %xmm2
-; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_test15:
@@ -1467,13 +1655,13 @@ define <4 x i32> @combine_test16(<4 x i32> %a, <4 x i32> %b) {
 define <4 x i32> @combine_test17(<4 x i32> %a, <4 x i32> %b) {
 ; SSE2-LABEL: combine_test17:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movss %xmm0, %xmm1
+; SSE2-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE2-NEXT:    movaps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_test17:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movss %xmm0, %xmm1
+; SSSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
@@ -1529,20 +1717,14 @@ define <4 x i32> @combine_test19(<4 x i32> %a, <4 x i32> %b) {
 define <4 x i32> @combine_test20(<4 x i32> %a, <4 x i32> %b) {
 ; SSE2-LABEL: combine_test20:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movaps %xmm0, %xmm2
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_test20:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movaps %xmm0, %xmm2
-; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_test20:
@@ -1568,26 +1750,26 @@ define <4 x i32> @combine_test21(<8 x i32> %a, <4 x i32>* %ptr) {
 ; SSE-LABEL: combine_test21:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    movdqa %xmm0, %xmm2
-; SSE-NEXT:    punpcklqdq  {{.*#+}} xmm2 = xmm2[0],xmm1[0]
-; SSE-NEXT:    punpckhqdq  {{.*#+}} xmm0 = xmm0[1],xmm1[1]
-; SSE-NEXT:    movdqa %xmm2,
+; SSE-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; SSE-NEXT:    punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
+; SSE-NEXT:    movdqa %xmm2, (%rdi)
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: combine_test21:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpunpcklqdq  {{.*#+}} xmm2 = xmm0[0],xmm1[0]
-; AVX1-NEXT:    vpunpckhqdq  {{.*#+}} xmm0 = xmm0[1],xmm1[1]
-; AVX1-NEXT:    movdqa %xmm2,
+; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
+; AVX1-NEXT:    vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
+; AVX1-NEXT:    vmovdqa %xmm2, (%rdi)
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: combine_test21:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT:    vpunpcklqdq  {{.*#+}} xmm2 = xmm0[0],xmm1[0]
-; AVX2-NEXT:    vpunpckhqdq  {{.*#+}} xmm0 = xmm0[1],xmm1[1]
-; AVX2-NEXT:    movdqa %xmm2,
+; AVX2-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
+; AVX2-NEXT:    vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
+; AVX2-NEXT:    vmovdqa %xmm2, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
   %1 = shufflevector <8 x i32> %a, <8 x i32> %a, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
@@ -1599,19 +1781,18 @@ define <4 x i32> @combine_test21(<8 x i32> %a, <4 x i32>* %ptr) {
 define <8 x float> @combine_test22(<2 x float>* %a, <2 x float>* %b) {
 ; SSE-LABEL: combine_test22:
 ; SSE:       # BB#0:
-; SSE-NEXT:    movq    (%rdi), %xmm0
-; SSE-NEXT:    movhpd  (%rsi), %xmm0
+; SSE-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
+; SSE-NEXT:    movhpd (%rsi), %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX1-LABEL: combine_test22:
-; AVX1:       # BB#0:
-; AVX1-NEXT:    vmovq    (%rdi), %xmm0
-; AVX1-NEXT:    vmovhpd  (%rsi), %xmm0, %xmm0
-; AVX1-NEXT:    retq
-;
+; AVX-LABEL: combine_test22:
+; AVX:       # BB#0:
+; AVX-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero
+; AVX-NEXT:    vmovhpd (%rsi), %xmm0, %xmm0
+; AVX-NEXT:    retq
 ; Current AVX2 lowering of this is still awful, not adding a test case.
-  %1 = load <2 x float>* %a, align 8
-  %2 = load <2 x float>* %b, align 8
+  %1 = load <2 x float>, <2 x float>* %a, align 8
+  %2 = load <2 x float>, <2 x float>* %b, align 8
   %3 = shufflevector <2 x float> %1, <2 x float> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
   ret <8 x float> %3
 }
@@ -1644,19 +1825,17 @@ define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
 ;
 ; SSSE3-LABEL: combine_test2b:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0,0]
-; SSSE3-NEXT:    movapd %xmm1, %xmm0
+; SSSE3-NEXT:    movddup {{.*#+}} xmm0 = xmm1[0,0]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_test2b:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0,0]
-; SSE41-NEXT:    movapd %xmm1, %xmm0
+; SSE41-NEXT:    movddup {{.*#+}} xmm0 = xmm1[0,0]
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: combine_test2b:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm1[0,0]
+; AVX-NEXT:    vmovddup {{.*#+}} xmm0 = xmm1[0,0]
 ; AVX-NEXT:    retq
   %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
   %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 0, i32 5>
@@ -1664,21 +1843,28 @@ define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
 }
 
 define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
-; SSE-LABEL: combine_test3b:
-; SSE:       # BB#0:
-; SSE-NEXT:    movaps %xmm1, %xmm2
-; SSE-NEXT:    shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[3,0]
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
-; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
-; SSE-NEXT:    retq
+; SSE2-LABEL: combine_test3b:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: combine_test3b:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: combine_test3b:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
+; SSE41-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,3,2,3]
+; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: combine_test3b:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vshufps {{.*#+}} xmm2 = xmm1[2,0],xmm0[3,0]
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
-; AVX-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; AVX-NEXT:    vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
+; AVX-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[0,3,2,3]
 ; AVX-NEXT:    retq
   %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 3>
   %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 7>
@@ -1707,48 +1893,48 @@ define <4 x float> @combine_test4b(<4 x float> %a, <4 x float> %b) {
 define <4 x i8> @combine_test1c(<4 x i8>* %a, <4 x i8>* %b) {
 ; SSE2-LABEL: combine_test1c:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movd (%rdi), %xmm1
+; SSE2-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
 ; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; SSE2-NEXT:    movd (%rsi), %xmm0
+; SSE2-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
 ; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
-; SSE2-NEXT:    movss %xmm1, %xmm0
+; SSE2-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_test1c:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movd (%rdi), %xmm1
+; SSSE3-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
 ; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; SSSE3-NEXT:    movd (%rsi), %xmm0
+; SSSE3-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
 ; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
-; SSSE3-NEXT:    movss %xmm1, %xmm0
+; SSSE3-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_test1c:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxbd (%rdi), %xmm1
-; SSE41-NEXT:    pmovzxbd (%rsi), %xmm0
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
 ; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: combine_test1c:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vpmovzxbd (%rdi), %xmm0
-; AVX1-NEXT:    vpmovzxbd (%rsi), %xmm1
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
 ; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: combine_test1c:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpmovzxbd (%rdi), %xmm0
-; AVX2-NEXT:    vpmovzxbd (%rsi), %xmm1
+; AVX2-NEXT:    vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX2-NEXT:    vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
 ; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
 ; AVX2-NEXT:    retq
-  %A = load <4 x i8>* %a
-  %B = load <4 x i8>* %b
+  %A = load <4 x i8>, <4 x i8>* %a
+  %B = load <4 x i8>, <4 x i8>* %b
   %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
   %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
   ret <4 x i8> %2
@@ -1757,10 +1943,10 @@ define <4 x i8> @combine_test1c(<4 x i8>* %a, <4 x i8>* %b) {
 define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
 ; SSE2-LABEL: combine_test2c:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movd (%rdi), %xmm0
+; SSE2-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
 ; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
-; SSE2-NEXT:    movd (%rsi), %xmm1
+; SSE2-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
 ; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
 ; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
@@ -1768,10 +1954,10 @@ define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
 ;
 ; SSSE3-LABEL: combine_test2c:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movd (%rdi), %xmm0
+; SSSE3-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
 ; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
-; SSSE3-NEXT:    movd (%rsi), %xmm1
+; SSSE3-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
 ; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
 ; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
@@ -1779,19 +1965,19 @@ define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
 ;
 ; SSE41-LABEL: combine_test2c:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxbd (%rdi), %xmm0
-; SSE41-NEXT:    pmovzxbd (%rsi), %xmm1
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
 ; SSE41-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: combine_test2c:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpmovzxbd (%rdi), %xmm0
-; AVX-NEXT:    vpmovzxbd (%rsi), %xmm1
+; AVX-NEXT:    vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX-NEXT:    vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
 ; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
 ; AVX-NEXT:    retq
-  %A = load <4 x i8>* %a
-  %B = load <4 x i8>* %b
+  %A = load <4 x i8>, <4 x i8>* %a
+  %B = load <4 x i8>, <4 x i8>* %b
   %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 1, i32 5>
   %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
   ret <4 x i8> %2
@@ -1800,10 +1986,10 @@ define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
 define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
 ; SSE2-LABEL: combine_test3c:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movd (%rdi), %xmm1
+; SSE2-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
 ; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; SSE2-NEXT:    movd (%rsi), %xmm0
+; SSE2-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
 ; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
 ; SSE2-NEXT:    punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
@@ -1811,10 +1997,10 @@ define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
 ;
 ; SSSE3-LABEL: combine_test3c:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movd (%rdi), %xmm1
+; SSSE3-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
 ; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; SSSE3-NEXT:    movd (%rsi), %xmm0
+; SSSE3-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
 ; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
 ; SSSE3-NEXT:    punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
@@ -1822,19 +2008,19 @@ define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
 ;
 ; SSE41-LABEL: combine_test3c:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxbd (%rdi), %xmm1
-; SSE41-NEXT:    pmovzxbd (%rsi), %xmm0
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
 ; SSE41-NEXT:    punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: combine_test3c:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpmovzxbd (%rdi), %xmm0
-; AVX-NEXT:    vpmovzxbd (%rsi), %xmm1
+; AVX-NEXT:    vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX-NEXT:    vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
 ; AVX-NEXT:    vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
 ; AVX-NEXT:    retq
-  %A = load <4 x i8>* %a
-  %B = load <4 x i8>* %b
+  %A = load <4 x i8>, <4 x i8>* %a
+  %B = load <4 x i8>, <4 x i8>* %b
   %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
   %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
   ret <4 x i8> %2
@@ -1843,56 +2029,50 @@ define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
 define <4 x i8> @combine_test4c(<4 x i8>* %a, <4 x i8>* %b) {
 ; SSE2-LABEL: combine_test4c:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movd (%rdi), %xmm1
+; SSE2-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
+; SSE2-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
 ; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; SSE2-NEXT:    movd (%rsi), %xmm2
-; SSE2-NEXT:    punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
-; SSE2-NEXT:    movdqa %xmm2, %xmm0
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_test4c:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movd (%rdi), %xmm1
+; SSSE3-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
+; SSSE3-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
 ; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; SSSE3-NEXT:    movd (%rsi), %xmm2
-; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
-; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
-; SSSE3-NEXT:    movdqa %xmm2, %xmm0
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_test4c:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pmovzxbd (%rdi), %xmm1
-; SSE41-NEXT:    pmovzxbd (%rsi), %xmm0
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
 ; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: combine_test4c:
 ; AVX1:       # BB#0:
-; AVX1-NEXT:    vpmovzxbd (%rdi), %xmm0
-; AVX1-NEXT:    vpmovzxbd (%rsi), %xmm1
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
 ; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: combine_test4c:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpmovzxbd (%rdi), %xmm0
-; AVX2-NEXT:    vpmovzxbd (%rsi), %xmm1
+; AVX2-NEXT:    vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX2-NEXT:    vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
 ; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
 ; AVX2-NEXT:    retq
-  %A = load <4 x i8>* %a
-  %B = load <4 x i8>* %b
+  %A = load <4 x i8>, <4 x i8>* %a
+  %B = load <4 x i8>, <4 x i8>* %b
   %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
   %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
   ret <4 x i8> %2
@@ -1931,12 +2111,12 @@ define <4 x i8> @combine_test4c(<4 x i8>* %a, <4 x i8>* %b) {
 define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
 ; SSE2-LABEL: combine_blend_01:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movsd %xmm1, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_blend_01:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movsd %xmm1, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_blend_01:
@@ -1956,16 +2136,16 @@ define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
 define <4 x float> @combine_blend_02(<4 x float> %a, <4 x float> %b) {
 ; SSE2-LABEL: combine_blend_02:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movss %xmm1, %xmm0
-; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
+; SSE2-NEXT:    movaps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_blend_02:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movss %xmm1, %xmm0
-; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
-; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
+; SSSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_blend_02:
@@ -1985,13 +2165,13 @@ define <4 x float> @combine_blend_02(<4 x float> %a, <4 x float> %b) {
 define <4 x float> @combine_blend_123(<4 x float> %a, <4 x float> %b) {
 ; SSE2-LABEL: combine_blend_123:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movss %xmm0, %xmm1
+; SSE2-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE2-NEXT:    movaps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_blend_123:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movss %xmm0, %xmm1
+; SSSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSSE3-NEXT:    movaps %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
@@ -2065,12 +2245,12 @@ define <4 x i32> @combine_test_movhl_3(<4 x i32> %a, <4 x i32> %b) {
 define <4 x float> @combine_undef_input_test1(<4 x float> %a, <4 x float> %b) {
 ; SSE2-LABEL: combine_undef_input_test1:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movsd %xmm1, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_undef_input_test1:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movsd %xmm1, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_undef_input_test1:
@@ -2136,14 +2316,14 @@ define <4 x float> @combine_undef_input_test4(<4 x float> %a, <4 x float> %b) {
 define <4 x float> @combine_undef_input_test5(<4 x float> %a, <4 x float> %b) {
 ; SSE2-LABEL: combine_undef_input_test5:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movsd %xmm0, %xmm1
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE2-NEXT:    movapd %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_undef_input_test5:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movsd %xmm0, %xmm1
-; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSSE3-NEXT:    movapd %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_undef_input_test5:
@@ -2181,17 +2361,17 @@ define <4 x float> @combine_undef_input_test7(<4 x float> %a) {
 ;
 ; SSSE3-LABEL: combine_undef_input_test7:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; SSSE3-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_undef_input_test7:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; SSE41-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: combine_undef_input_test7:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX-NEXT:    retq
   %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
   %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
@@ -2206,17 +2386,17 @@ define <4 x float> @combine_undef_input_test8(<4 x float> %a) {
 ;
 ; SSSE3-LABEL: combine_undef_input_test8:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; SSSE3-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_undef_input_test8:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; SSE41-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: combine_undef_input_test8:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX-NEXT:    retq
   %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
   %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
@@ -2250,12 +2430,12 @@ define <4 x float> @combine_undef_input_test10(<4 x float> %a) {
 define <4 x float> @combine_undef_input_test11(<4 x float> %a, <4 x float> %b) {
 ; SSE2-LABEL: combine_undef_input_test11:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movsd %xmm1, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_undef_input_test11:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movsd %xmm1, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_undef_input_test11:
@@ -2321,14 +2501,14 @@ define <4 x float> @combine_undef_input_test14(<4 x float> %a, <4 x float> %b) {
 define <4 x float> @combine_undef_input_test15(<4 x float> %a, <4 x float> %b) {
 ; SSE2-LABEL: combine_undef_input_test15:
 ; SSE2:       # BB#0:
-; SSE2-NEXT:    movsd %xmm0, %xmm1
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE2-NEXT:    movapd %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: combine_undef_input_test15:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    movsd %xmm0, %xmm1
-; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSSE3-NEXT:    movapd %xmm1, %xmm0
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_undef_input_test15:
@@ -2372,17 +2552,17 @@ define <4 x float> @combine_undef_input_test17(<4 x float> %a) {
 ;
 ; SSSE3-LABEL: combine_undef_input_test17:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; SSSE3-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_undef_input_test17:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; SSE41-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: combine_undef_input_test17:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX-NEXT:    retq
   %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
   %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
@@ -2397,17 +2577,17 @@ define <4 x float> @combine_undef_input_test18(<4 x float> %a) {
 ;
 ; SSSE3-LABEL: combine_undef_input_test18:
 ; SSSE3:       # BB#0:
-; SSSE3-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; SSSE3-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: combine_undef_input_test18:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; SSE41-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: combine_undef_input_test18:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0,0]
+; AVX-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX-NEXT:    retq
   %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
   %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 0, i32 5>
@@ -2499,6 +2679,20 @@ define <8 x i32> @combine_unneeded_subvector2(<8 x i32> %a, <8 x i32> %b) {
 }
 
 define <4 x float> @combine_insertps1(<4 x float> %a, <4 x float> %b) {
+; SSE2-LABEL: combine_insertps1:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3]
+; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: combine_insertps1:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3]
+; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    retq
+;
 ; SSE41-LABEL: combine_insertps1:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    insertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
@@ -2515,6 +2709,20 @@ define <4 x float> @combine_insertps1(<4 x float> %a, <4 x float> %b) {
 }
 
 define <4 x float> @combine_insertps2(<4 x float> %a, <4 x float> %b) {
+; SSE2-LABEL: combine_insertps2:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
+; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: combine_insertps2:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
+; SSSE3-NEXT:    movaps %xmm1, %xmm0
+; SSSE3-NEXT:    retq
+;
 ; SSE41-LABEL: combine_insertps2:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
@@ -2531,6 +2739,18 @@ define <4 x float> @combine_insertps2(<4 x float> %a, <4 x float> %b) {
 }
 
 define <4 x float> @combine_insertps3(<4 x float> %a, <4 x float> %b) {
+; SSE2-LABEL: combine_insertps3:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: combine_insertps3:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
+; SSSE3-NEXT:    retq
+;
 ; SSE41-LABEL: combine_insertps3:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
@@ -2547,6 +2767,18 @@ define <4 x float> @combine_insertps3(<4 x float> %a, <4 x float> %b) {
 }
 
 define <4 x float> @combine_insertps4(<4 x float> %a, <4 x float> %b) {
+; SSE2-LABEL: combine_insertps4:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: combine_insertps4:
+; SSSE3:       # BB#0:
+; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
+; SSSE3-NEXT:    retq
+;
 ; SSE41-LABEL: combine_insertps4:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
@@ -2561,3 +2793,115 @@ define <4 x float> @combine_insertps4(<4 x float> %a, <4 x float> %b) {
   %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 6, i32 5>
   ret <4 x float> %d
 }
+
+define <4 x float> @PR22377(<4 x float> %a, <4 x float> %b) {
+; SSE-LABEL: PR22377:
+; SSE:       # BB#0: # %entry
+; SSE-NEXT:    movaps %xmm0, %xmm1
+; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,3,1,3]
+; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,0,2]
+; SSE-NEXT:    addps %xmm0, %xmm1
+; SSE-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: PR22377:
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vpermilps {{.*#+}} xmm1 = xmm0[1,3,1,3]
+; AVX-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[0,2,0,2]
+; AVX-NEXT:    vaddps %xmm0, %xmm1, %xmm1
+; AVX-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; AVX-NEXT:    retq
+entry:
+  %s1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 1, i32 3>
+  %s2 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
+  %r2 = fadd <4 x float> %s1, %s2
+  %s3 = shufflevector <4 x float> %s2, <4 x float> %r2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+  ret <4 x float> %s3
+}
+
+define <4 x float> @PR22390(<4 x float> %a, <4 x float> %b) {
+; SSE2-LABEL: PR22390:
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
+; SSE2-NEXT:    movaps %xmm0, %xmm2
+; SSE2-NEXT:    movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
+; SSE2-NEXT:    addps %xmm0, %xmm2
+; SSE2-NEXT:    movaps %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: PR22390:
+; SSSE3:       # BB#0: # %entry
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
+; SSSE3-NEXT:    movaps %xmm0, %xmm2
+; SSSE3-NEXT:    movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
+; SSSE3-NEXT:    addps %xmm0, %xmm2
+; SSSE3-NEXT:    movaps %xmm2, %xmm0
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: PR22390:
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
+; SSE41-NEXT:    blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1,2,3]
+; SSE41-NEXT:    addps %xmm1, %xmm0
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: PR22390:
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[3,0,1,2]
+; AVX-NEXT:    vblendps {{.*#+}} xmm1 = xmm1[0],xmm0[1,2,3]
+; AVX-NEXT:    vaddps %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+entry:
+  %s1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
+  %s2 = shufflevector <4 x float> %s1, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
+  %r2 = fadd <4 x float> %s1, %s2
+  ret <4 x float> %r2
+}
+
+define <8 x float> @PR22412(<8 x float> %a, <8 x float> %b) {
+; SSE2-LABEL: PR22412:
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
+; SSE2-NEXT:    movapd %xmm2, %xmm0
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm3[3,2]
+; SSE2-NEXT:    shufps {{.*#+}} xmm3 = xmm3[1,0],xmm2[3,2]
+; SSE2-NEXT:    movaps %xmm3, %xmm1
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: PR22412:
+; SSSE3:       # BB#0: # %entry
+; SSSE3-NEXT:    movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
+; SSSE3-NEXT:    movapd %xmm2, %xmm0
+; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm3[3,2]
+; SSSE3-NEXT:    shufps {{.*#+}} xmm3 = xmm3[1,0],xmm2[3,2]
+; SSSE3-NEXT:    movaps %xmm3, %xmm1
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: PR22412:
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm0[0],xmm2[1]
+; SSE41-NEXT:    movapd %xmm0, %xmm1
+; SSE41-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,0],xmm3[3,2]
+; SSE41-NEXT:    shufps {{.*#+}} xmm3 = xmm3[1,0],xmm0[3,2]
+; SSE41-NEXT:    movaps %xmm1, %xmm0
+; SSE41-NEXT:    movaps %xmm3, %xmm1
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: PR22412:
+; AVX1:       # BB#0: # %entry
+; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
+; AVX1-NEXT:    vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
+; AVX1-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[1,0],ymm1[3,2],ymm0[5,4],ymm1[7,6]
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: PR22412:
+; AVX2:       # BB#0: # %entry
+; AVX2-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
+; AVX2-NEXT:    vmovaps {{.*#+}} ymm1 = [1,0,7,6,5,4,3,2]
+; AVX2-NEXT:    vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT:    retq
+entry:
+  %s1 = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %s2 = shufflevector <8 x float> %s1, <8 x float> undef, <8 x i32> <i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2>
+  ret <8 x float> %s2
+}
diff --git a/test/CodeGen/X86/vector-shuffle-mmx.ll b/test/CodeGen/X86/vector-shuffle-mmx.ll
new file mode 100644
index 000000000000..dbccd2694b07
--- /dev/null
+++ b/test/CodeGen/X86/vector-shuffle-mmx.ll
@@ -0,0 +1,105 @@
+; RUN: llc < %s -mtriple=i686-darwin -mattr=+mmx,+sse2 | FileCheck --check-prefix=X32 %s
+; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse2 | FileCheck --check-prefix=X64 %s
+
+; If there is no explicit MMX type usage, always promote to XMM.
+
+define void @test0(<1 x i64>* %x) {
+; X32-LABEL: test0:
+; X32:       ## BB#0: ## %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; X32-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
+; X32-NEXT:    movq %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: test0:
+; X64:       ## BB#0: ## %entry
+; X64-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
+; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
+; X64-NEXT:    movq %xmm0, (%rdi)
+; X64-NEXT:    retq
+entry:
+  %tmp2 = load <1 x i64>, <1 x i64>* %x
+  %tmp6 = bitcast <1 x i64> %tmp2 to <2 x i32>
+  %tmp9 = shufflevector <2 x i32> %tmp6, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
+  %tmp10 = bitcast <2 x i32> %tmp9 to <1 x i64>
+  store <1 x i64> %tmp10, <1 x i64>* %x
+  ret void
+}
+
+define void @test1() {
+; X32-LABEL: test1:
+; X32:       ## BB#0: ## %entry
+; X32-NEXT:    pushl %edi
+; X32-NEXT:  Ltmp0:
+; X32-NEXT:    .cfi_def_cfa_offset 8
+; X32-NEXT:    subl $16, %esp
+; X32-NEXT:  Ltmp1:
+; X32-NEXT:    .cfi_def_cfa_offset 24
+; X32-NEXT:  Ltmp2:
+; X32-NEXT:    .cfi_offset %edi, -8
+; X32-NEXT:    xorps %xmm0, %xmm0
+; X32-NEXT:    movlps %xmm0, (%esp)
+; X32-NEXT:    movq (%esp), %mm0
+; X32-NEXT:    pshuflw {{.*#+}} xmm0 = mem[0,2,2,3,4,5,6,7]
+; X32-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
+; X32-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; X32-NEXT:    movq %xmm0, {{[0-9]+}}(%esp)
+; X32-NEXT:    movq {{[0-9]+}}(%esp), %mm1
+; X32-NEXT:    xorl %edi, %edi
+; X32-NEXT:    maskmovq %mm1, %mm0
+; X32-NEXT:    addl $16, %esp
+; X32-NEXT:    popl %edi
+; X32-NEXT:    retl
+;
+; X64-LABEL: test1:
+; X64:       ## BB#0: ## %entry
+; X64-NEXT:    xorps %xmm0, %xmm0
+; X64-NEXT:    movlps %xmm0, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movq -{{[0-9]+}}(%rsp), %mm0
+; X64-NEXT:    pshuflw {{.*#+}} xmm0 = mem[0,2,2,3,4,5,6,7]
+; X64-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
+; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; X64-NEXT:    movq %xmm0, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movq -{{[0-9]+}}(%rsp), %mm1
+; X64-NEXT:    xorl %edi, %edi
+; X64-NEXT:    maskmovq %mm1, %mm0
+; X64-NEXT:    retq
+entry:
+  %tmp528 = bitcast <8 x i8> zeroinitializer to <2 x i32>
+  %tmp529 = and <2 x i32> %tmp528, bitcast (<4 x i16> < i16 -32640, i16 16448, i16 8224, i16 4112 > to <2 x i32>)
+  %tmp542 = bitcast <2 x i32> %tmp529 to <4 x i16>
+  %tmp543 = add <4 x i16> %tmp542, < i16 0, i16 16448, i16 24672, i16 28784 >
+  %tmp555 = bitcast <4 x i16> %tmp543 to <8 x i8>
+  %tmp556 = bitcast <8 x i8> %tmp555 to x86_mmx
+  %tmp557 = bitcast <8 x i8> zeroinitializer to x86_mmx
+  tail call void @llvm.x86.mmx.maskmovq( x86_mmx %tmp557, x86_mmx %tmp556, i8* null)
+  ret void
+}
+
+@tmp_V2i = common global <2 x i32> zeroinitializer
+
+define void @test2() nounwind {
+; X32-LABEL: test2:
+; X32:       ## BB#0: ## %entry
+; X32-NEXT:    movl L_tmp_V2i$non_lazy_ptr, %eax
+; X32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; X32-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0,0,1,1]
+; X32-NEXT:    movlps %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: test2:
+; X64:       ## BB#0: ## %entry
+; X64-NEXT:    movq _tmp_V2i@{{.*}}(%rip), %rax
+; X64-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
+; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
+; X64-NEXT:    movq %xmm0, (%rax)
+; X64-NEXT:    retq
+entry:
+  %0 = load <2 x i32>, <2 x i32>* @tmp_V2i, align 8
+  %1 = shufflevector <2 x i32> %0, <2 x i32> undef, <2 x i32> zeroinitializer
+  store <2 x i32> %1, <2 x i32>* @tmp_V2i, align 8
+  ret void
+}
+
+declare void @llvm.x86.mmx.maskmovq(x86_mmx, x86_mmx, i8*)
diff --git a/test/CodeGen/X86/vector-shuffle-sse1.ll b/test/CodeGen/X86/vector-shuffle-sse1.ll
index ef60272b6c35..66e53bbb7502 100644
--- a/test/CodeGen/X86/vector-shuffle-sse1.ll
+++ b/test/CodeGen/X86/vector-shuffle-sse1.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mcpu=x86-64 -mattr=-sse2 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=SSE1
+; RUN: llc < %s -mcpu=x86-64 -mattr=-sse2 | FileCheck %s --check-prefix=SSE1
 
 target triple = "x86_64-unknown-unknown"
 
@@ -95,7 +95,7 @@ define <4 x float> @shuffle_v4f32_4zzz(<4 x float> %a) {
 ; SSE1-LABEL: shuffle_v4f32_4zzz:
 ; SSE1:       # BB#0:
 ; SSE1-NEXT:    xorps %xmm1, %xmm1
-; SSE1-NEXT:    movss %xmm0, %xmm1
+; SSE1-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE1-NEXT:    movaps %xmm1, %xmm0
 ; SSE1-NEXT:    retq
   %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
@@ -106,8 +106,8 @@ define <4 x float> @shuffle_v4f32_z4zz(<4 x float> %a) {
 ; SSE1-LABEL: shuffle_v4f32_z4zz:
 ; SSE1:       # BB#0:
 ; SSE1-NEXT:    xorps %xmm1, %xmm1
-; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0]
-; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]
+; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
+; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
 ; SSE1-NEXT:    retq
   %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 4, i32 3, i32 0>
   ret <4 x float> %shuffle
@@ -117,8 +117,8 @@ define <4 x float> @shuffle_v4f32_zz4z(<4 x float> %a) {
 ; SSE1-LABEL: shuffle_v4f32_zz4z:
 ; SSE1:       # BB#0:
 ; SSE1-NEXT:    xorps %xmm1, %xmm1
-; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
-; SSE1-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,2]
+; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
+; SSE1-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2]
 ; SSE1-NEXT:    movaps %xmm1, %xmm0
 ; SSE1-NEXT:    retq
   %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 0, i32 4, i32 0>
@@ -163,7 +163,7 @@ define <4 x float> @insert_reg_and_zero_v4f32(float %a) {
 ; SSE1-LABEL: insert_reg_and_zero_v4f32:
 ; SSE1:       # BB#0:
 ; SSE1-NEXT:    xorps %xmm1, %xmm1
-; SSE1-NEXT:    movss %xmm0, %xmm1
+; SSE1-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; SSE1-NEXT:    movaps %xmm1, %xmm0
 ; SSE1-NEXT:    retq
   %v = insertelement <4 x float> undef, float %a, i32 0
@@ -174,9 +174,9 @@ define <4 x float> @insert_reg_and_zero_v4f32(float %a) {
 define <4 x float> @insert_mem_and_zero_v4f32(float* %ptr) {
 ; SSE1-LABEL: insert_mem_and_zero_v4f32:
 ; SSE1:       # BB#0:
-; SSE1-NEXT:    movss (%rdi), %xmm0
+; SSE1-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE1-NEXT:    retq
-  %a = load float* %ptr
+  %a = load float, float* %ptr
   %v = insertelement <4 x float> undef, float %a, i32 0
   %shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
   ret <4 x float> %shuffle
@@ -189,15 +189,15 @@ define <4 x float> @insert_mem_lo_v4f32(<2 x float>* %ptr, <4 x float> %b) {
 ; SSE1-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
 ; SSE1-NEXT:    shrq $32, %rax
 ; SSE1-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; SSE1-NEXT:    movss -{{[0-9]+}}(%rsp), %xmm1
-; SSE1-NEXT:    movss -{{[0-9]+}}(%rsp), %xmm2
+; SSE1-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE1-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
 ; SSE1-NEXT:    unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
 ; SSE1-NEXT:    xorps %xmm2, %xmm2
-; SSE1-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,1]
+; SSE1-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3]
 ; SSE1-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
 ; SSE1-NEXT:    movaps %xmm1, %xmm0
 ; SSE1-NEXT:    retq
-  %a = load <2 x float>* %ptr
+  %a = load <2 x float>, <2 x float>* %ptr
   %v = shufflevector <2 x float> %a, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   %shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
   ret <4 x float> %shuffle
@@ -210,14 +210,14 @@ define <4 x float> @insert_mem_hi_v4f32(<2 x float>* %ptr, <4 x float> %b) {
 ; SSE1-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
 ; SSE1-NEXT:    shrq $32, %rax
 ; SSE1-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; SSE1-NEXT:    movss -{{[0-9]+}}(%rsp), %xmm1
-; SSE1-NEXT:    movss -{{[0-9]+}}(%rsp), %xmm2
+; SSE1-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE1-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
 ; SSE1-NEXT:    unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
 ; SSE1-NEXT:    xorps %xmm2, %xmm2
-; SSE1-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,1]
+; SSE1-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3]
 ; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,1]
 ; SSE1-NEXT:    retq
-  %a = load <2 x float>* %ptr
+  %a = load <2 x float>, <2 x float>* %ptr
   %v = shufflevector <2 x float> %a, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   %shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
   ret <4 x float> %shuffle
@@ -229,7 +229,7 @@ define <4 x float> @shuffle_mem_v4f32_3210(<4 x float>* %ptr) {
 ; SSE1-NEXT:    movaps (%rdi), %xmm0
 ; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,2,1,0]
 ; SSE1-NEXT:    retq
-  %a = load <4 x float>* %ptr
+  %a = load <4 x float>, <4 x float>* %ptr
   %shuffle = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   ret <4 x float> %shuffle
 }
diff --git a/test/CodeGen/X86/vector-trunc.ll b/test/CodeGen/X86/vector-trunc.ll
index 8a5b7488f664..d2eef9af2a25 100644
--- a/test/CodeGen/X86/vector-trunc.ll
+++ b/test/CodeGen/X86/vector-trunc.ll
@@ -3,18 +3,56 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
 
+define <4 x i32> @trunc2x2i64(<2 x i64> %a, <2 x i64> %b) {
+; SSE2-LABEL: trunc2x2i64:
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: trunc2x2i64:
+; SSSE3:       # BB#0: # %entry
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: trunc2x2i64:
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,1,0,2]
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: trunc2x2i64:
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,2]
+; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; AVX-NEXT:    retq
+
+
+entry:
+  %0 = trunc <2 x i64> %a to <2 x i32>
+  %1 = trunc <2 x i64> %b to <2 x i32>
+  %2 = shufflevector <2 x i32> %0, <2 x i32> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  ret <4 x i32> %2
+}
+
 define i64 @trunc2i64(<2 x i64> %inval) {
-; SSE-LABEL:  trunc2i64:
-; SSE:        # BB#0: # %entry
-; SSE-NEXT:   pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; SSE-NEXT:   movd %xmm0, %rax
-; SSE-NEXT:   retq
+; SSE-LABEL: trunc2i64:
+; SSE:       # BB#0: # %entry
+; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE-NEXT:    movd %xmm0, %rax
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: trunc2i64:
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; AVX-NEXT:    vmovq %xmm0, %rax
+; AVX-NEXT:    retq
 
-; AVX-LABEL:  trunc2i64:
-; AVX:        # BB#0: # %entry
-; AVX-NEXT:   vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; AVX-NEXT:   vmovq %xmm0, %rax
-; AVX-NEXT:   retq
 
 entry:
   %0 = trunc <2 x i64> %inval to <2 x i32>
@@ -22,33 +60,82 @@ entry:
   ret i64 %1
 }
 
+define <8 x i16> @trunc2x4i32(<4 x i32> %a, <4 x i32> %b) {
+; SSE2-LABEL: trunc2x4i32:
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
+; SSE2-NEXT:    pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
+; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: trunc2x4i32:
+; SSSE3:       # BB#0: # %entry
+; SSSE3-NEXT:    movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; SSSE3-NEXT:    pshufb %xmm2, %xmm1
+; SSSE3-NEXT:    pshufb %xmm2, %xmm0
+; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: trunc2x4i32:
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; SSE41-NEXT:    pshufb %xmm2, %xmm1
+; SSE41-NEXT:    pshufb %xmm2, %xmm0
+; SSE41-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: trunc2x4i32:
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; AVX-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
+; AVX-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX-NEXT:    retq
+
+
+
+
+entry:
+  %0 = trunc <4 x i32> %a to <4 x i16>
+  %1 = trunc <4 x i32> %b to <4 x i16>
+  %2 = shufflevector <4 x i16> %0, <4 x i16> %1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  ret <8 x i16> %2
+}
+
 ; PR15524 http://llvm.org/bugs/show_bug.cgi?id=15524
 define i64 @trunc4i32(<4 x i32> %inval) {
-; SSE2-LABEL:  trunc4i32:
-; SSE2:        # BB#0: # %entry
-; SSE2-NEXT:   pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
-; SSE2-NEXT:   pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
-; SSE2-NEXT:   pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; SSE2-NEXT:   movd %xmm0, %rax
-; SSE2-NEXT:   retq
-
+; SSE2-LABEL: trunc4i32:
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
+; SSE2-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    movd %xmm0, %rax
+; SSE2-NEXT:    retq
+;
 ; SSSE3-LABEL: trunc4i32:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:  pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; SSSE3-NEXT:  movd %xmm0, %rax
-; SSSE3-NEXT:  retq
-
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; SSSE3-NEXT:    movd %xmm0, %rax
+; SSSE3-NEXT:    retq
+;
 ; SSE41-LABEL: trunc4i32:
 ; SSE41:       # BB#0: # %entry
-; SSE41-NEXT:  pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; SSE41-NEXT:  movd %xmm0, %rax
-; SSE41-NEXT:  retq
+; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; SSE41-NEXT:    movd %xmm0, %rax
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: trunc4i32:
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; AVX-NEXT:    vmovq %xmm0, %rax
+; AVX-NEXT:    retq
+
+
 
-; AVX-LABEL:  trunc4i32:
-; AVX:        # BB#0: # %entry
-; AVX-NEXT:   vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; AVX-NEXT:   vmovq %xmm0, %rax
-; AVX-NEXT:   retq
 
 entry:
   %0 = trunc <4 x i32> %inval to <4 x i16>
@@ -56,35 +143,98 @@ entry:
   ret i64 %1
 }
 
+define <16 x i8> @trunc2x8i16(<8 x i16> %a, <8 x i16> %b) {
+; SSE2-LABEL: trunc2x8i16:
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
+; SSE2-NEXT:    pand %xmm2, %xmm1
+; SSE2-NEXT:    pand %xmm2, %xmm0
+; SSE2-NEXT:    packuswb %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: trunc2x8i16:
+; SSSE3:       # BB#0: # %entry
+; SSSE3-NEXT:    movdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
+; SSSE3-NEXT:    pshufb %xmm2, %xmm1
+; SSSE3-NEXT:    pshufb %xmm2, %xmm0
+; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: trunc2x8i16:
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    movdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
+; SSE41-NEXT:    pshufb %xmm2, %xmm1
+; SSE41-NEXT:    pshufb %xmm2, %xmm0
+; SSE41-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: trunc2x8i16:
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
+; AVX-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
+; AVX-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX-NEXT:    retq
+
+
+
+
+entry:
+  %0 = trunc <8 x i16> %a to <8 x i8>
+  %1 = trunc <8 x i16> %b to <8 x i8>
+  %2 = shufflevector <8 x i8> %0, <8 x i8> %1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  ret <16 x i8> %2
+}
+
 ; PR15524 http://llvm.org/bugs/show_bug.cgi?id=15524
 define i64 @trunc8i16(<8 x i16> %inval) {
-; SSE2-LABEL:  trunc8i16:
-; SSE2:        # BB#0: # %entry
-; SSE2-NEXT:   pand .LCP{{.*}}(%rip), %xmm0
-; SSE2-NEXT:   packuswb %xmm0, %xmm0
-; SSE2-NEXT:   movd %xmm0, %rax
-; SSE2-NEXT:   retq
-
+; SSE2-LABEL: trunc8i16:
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT:    packuswb %xmm0, %xmm0
+; SSE2-NEXT:    movd %xmm0, %rax
+; SSE2-NEXT:    retq
+;
 ; SSSE3-LABEL: trunc8i16:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:  pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
-; SSSE3-NEXT:  movd %xmm0, %rax
-; SSSE3-NEXT:  retq
-
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; SSSE3-NEXT:    movd %xmm0, %rax
+; SSSE3-NEXT:    retq
+;
 ; SSE41-LABEL: trunc8i16:
 ; SSE41:       # BB#0: # %entry
-; SSE41-NEXT:  pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
-; SSE41-NEXT:  movd %xmm0, %rax
-; SSE41-NEXT:  retq
+; SSE41-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; SSE41-NEXT:    movd %xmm0, %rax
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: trunc8i16:
+; AVX:       # BB#0: # %entry
+; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; AVX-NEXT:    vmovq %xmm0, %rax
+; AVX-NEXT:    retq
+
+
 
-; AVX-LABEL:  trunc8i16:
-; AVX:        # BB#0: # %entry
-; AVX-NEXT:   vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
-; AVX-NEXT:   vmovq %xmm0, %rax
-; AVX-NEXT:   retq
 
 entry:
   %0 = trunc <8 x i16> %inval to <8 x i8>
   %1 = bitcast <8 x i8> %0 to i64
   ret i64 %1
 }
+
+define <16 x i8> @trunc16i64_const() {
+; SSE-LABEL:  trunc16i64_const
+; SSE:        # BB#0: # %entry
+; SSE-NEXT:   xorps %xmm0, %xmm0
+; SSE-NEXT:   retq
+;
+; AVX-LABEL:  trunc16i64_const
+; AVX:        # BB#0: # %entry
+; AVX-NEXT:   vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT:   retq
+
+entry:
+  %0 = trunc <16 x i64> zeroinitializer to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> %0, <16 x i32> <i32 28, i32 30, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 undef, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26>
+  ret <16 x i8> %1
+}
diff --git a/test/CodeGen/X86/vector-variable-idx2.ll b/test/CodeGen/X86/vector-variable-idx2.ll
index 6e8ae2e42c94..df65257bac7e 100644
--- a/test/CodeGen/X86/vector-variable-idx2.ll
+++ b/test/CodeGen/X86/vector-variable-idx2.ll
@@ -8,8 +8,8 @@ define i64 @__builtin_ia32_vec_ext_v2di(<2 x i64> %a, i32 %i) nounwind {
   %2 = alloca i32, align 4
   store <2 x i64> %a, <2 x i64>* %1, align 16
   store i32 %i, i32* %2, align 4
-  %3 = load <2 x i64>* %1, align 16
-  %4 = load i32* %2, align 4
+  %3 = load <2 x i64>, <2 x i64>* %1, align 16
+  %4 = load i32, i32* %2, align 4
   %5 = extractelement <2 x i64> %3, i32 %4
   ret i64 %5
 }
@@ -19,8 +19,8 @@ define <2 x i64> @__builtin_ia32_vec_int_v2di(<2 x i64> %a, i32 %i) nounwind {
   %2 = alloca i32, align 4
   store <2 x i64> %a, <2 x i64>* %1, align 16
   store i32 %i, i32* %2, align 4
-  %3 = load <2 x i64>* %1, align 16
-  %4 = load i32* %2, align 4
+  %3 = load <2 x i64>, <2 x i64>* %1, align 16
+  %4 = load i32, i32* %2, align 4
   %5 = insertelement <2 x i64> %3, i64 1, i32 %4
   ret <2 x i64> %5
 }
diff --git a/test/CodeGen/X86/vector-zext.ll b/test/CodeGen/X86/vector-zext.ll
index cd09deee4550..42781830ff2f 100644
--- a/test/CodeGen/X86/vector-zext.ll
+++ b/test/CodeGen/X86/vector-zext.ll
@@ -7,47 +7,43 @@
 define <8 x i32> @zext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
 ; SSE2-LABEL: zext_8i16_to_8i32:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movdqa %xmm0, %xmm2
-; SSE2-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
-; SSE2-NEXT:    movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
-; SSE2-NEXT:    pand %xmm1, %xmm2
-; SSE2-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
-; SSE2-NEXT:    pand %xmm0, %xmm1
-; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    movdqa %xmm0, %xmm1
+; SSE2-NEXT:    pxor %xmm2, %xmm2
+; SSE2-NEXT:    # kill
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
+; SSE2-NEXT:    pand .LCPI0_0(%rip), %xmm1
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: zext_8i16_to_8i32:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movdqa %xmm0, %xmm2
-; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
-; SSSE3-NEXT:    movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
-; SSSE3-NEXT:    pand %xmm1, %xmm2
-; SSSE3-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
-; SSSE3-NEXT:    pand %xmm0, %xmm1
-; SSSE3-NEXT:    movdqa %xmm2, %xmm0
+; SSSE3-NEXT:    movdqa %xmm0, %xmm1
+; SSSE3-NEXT:    pxor %xmm2, %xmm2
+; SSSE3-NEXT:    # kill
+; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; SSSE3-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
+; SSSE3-NEXT:    pand .LCPI0_0(%rip), %xmm1
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: zext_8i16_to_8i32:
 ; SSE41:       # BB#0: # %entry
-; SSE41-NEXT:    pmovzxwd %xmm0, %xmm2
-; SSE41-NEXT:    movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
-; SSE41-NEXT:    pand %xmm1, %xmm2
-; SSE41-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
-; SSE41-NEXT:    pand %xmm0, %xmm1
-; SSE41-NEXT:    movdqa %xmm2, %xmm0
+; SSE41-NEXT:    movdqa %xmm0, %xmm1
+; SSE41-NEXT:    pmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
+; SSE41-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
+; SSE41-NEXT:    pand .LCPI0_0(%rip), %xmm1
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: zext_8i16_to_8i32:
 ; AVX1:       # BB#0: # %entry
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
-; AVX1-NEXT:    vpmovzxwd %xmm0, %xmm0
+; AVX1-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: zext_8i16_to_8i32:
 ; AVX2:       # BB#0: # %entry
-; AVX2-NEXT:    vpmovzxwd %xmm0, %ymm0
+; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
 ; AVX2-NEXT:    retq
 entry:
   %B = zext <8 x i16> %A to <8 x i32>
@@ -77,7 +73,7 @@ define <4 x i64> @zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp
 ;
 ; SSE41-LABEL: zext_4i32_to_4i64:
 ; SSE41:       # BB#0: # %entry
-; SSE41-NEXT:    pmovzxdq %xmm0, %xmm2
+; SSE41-NEXT:    pmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero
 ; SSE41-NEXT:    movdqa {{.*#+}} xmm3 = [4294967295,4294967295]
 ; SSE41-NEXT:    pand %xmm3, %xmm2
 ; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
@@ -89,13 +85,13 @@ define <4 x i64> @zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp
 ; AVX1:       # BB#0: # %entry
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpunpckhdq {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX1-NEXT:    vpmovzxdq %xmm0, %xmm0
+; AVX1-NEXT:    vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: zext_4i32_to_4i64:
 ; AVX2:       # BB#0: # %entry
-; AVX2-NEXT:    vpmovzxdq %xmm0, %ymm0
+; AVX2-NEXT:    vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
 ; AVX2-NEXT:    retq
 entry:
   %B = zext <4 x i32> %A to <4 x i64>
@@ -127,7 +123,7 @@ define <8 x i32> @zext_8i8_to_8i32(<8 x i8> %z) {
 ;
 ; SSE41-LABEL: zext_8i8_to_8i32:
 ; SSE41:       # BB#0: # %entry
-; SSE41-NEXT:    pmovzxwd %xmm0, %xmm2
+; SSE41-NEXT:    pmovzxwd {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
 ; SSE41-NEXT:    movdqa {{.*#+}} xmm1 = [255,255,255,255]
 ; SSE41-NEXT:    pand %xmm1, %xmm2
 ; SSE41-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
@@ -137,7 +133,7 @@ define <8 x i32> @zext_8i8_to_8i32(<8 x i8> %z) {
 ;
 ; AVX1-LABEL: zext_8i8_to_8i32:
 ; AVX1:       # BB#0: # %entry
-; AVX1-NEXT:    vpmovzxwd %xmm0, %xmm1
+; AVX1-NEXT:    vpmovzxwd {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
 ; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    vandps {{.*}}(%rip), %ymm0, %ymm0
@@ -145,7 +141,7 @@ define <8 x i32> @zext_8i8_to_8i32(<8 x i8> %z) {
 ;
 ; AVX2-LABEL: zext_8i8_to_8i32:
 ; AVX2:       # BB#0: # %entry
-; AVX2-NEXT:    vpmovzxwd %xmm0, %ymm0
+; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
 ; AVX2-NEXT:    vpbroadcastd {{.*}}(%rip), %ymm1
 ; AVX2-NEXT:    vpand %ymm1, %ymm0, %ymm0
 ; AVX2-NEXT:    retq
@@ -158,47 +154,43 @@ entry:
 define <16 x i16> @zext_16i8_to_16i16(<16 x i8> %z) {
 ; SSE2-LABEL: zext_16i8_to_16i16:
 ; SSE2:       # BB#0: # %entry
-; SSE2-NEXT:    movdqa %xmm0, %xmm2
-; SSE2-NEXT:    punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
-; SSE2-NEXT:    movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255]
-; SSE2-NEXT:    pand %xmm1, %xmm2
-; SSE2-NEXT:    punpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; SSE2-NEXT:    pand %xmm0, %xmm1
-; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    movdqa %xmm0, %xmm1
+; SSE2-NEXT:    pxor %xmm2, %xmm2
+; SSE2-NEXT:    # kill
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; SSE2-NEXT:    punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
+; SSE2-NEXT:    pand .LCPI3_0(%rip), %xmm1
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: zext_16i8_to_16i16:
 ; SSSE3:       # BB#0: # %entry
-; SSSE3-NEXT:    movdqa %xmm0, %xmm2
-; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
-; SSSE3-NEXT:    movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255]
-; SSSE3-NEXT:    pand %xmm1, %xmm2
-; SSSE3-NEXT:    punpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; SSSE3-NEXT:    pand %xmm0, %xmm1
-; SSSE3-NEXT:    movdqa %xmm2, %xmm0
+; SSSE3-NEXT:    movdqa %xmm0, %xmm1
+; SSSE3-NEXT:    pxor %xmm2, %xmm2
+; SSSE3-NEXT:    # kill
+; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; SSSE3-NEXT:    punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
+; SSSE3-NEXT:    pand .LCPI3_0(%rip), %xmm1
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: zext_16i8_to_16i16:
 ; SSE41:       # BB#0: # %entry
-; SSE41-NEXT:    pmovzxbw %xmm0, %xmm2
-; SSE41-NEXT:    movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255]
-; SSE41-NEXT:    pand %xmm1, %xmm2
-; SSE41-NEXT:    punpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; SSE41-NEXT:    pand %xmm0, %xmm1
-; SSE41-NEXT:    movdqa %xmm2, %xmm0
+; SSE41-NEXT:    movdqa %xmm0, %xmm1
+; SSE41-NEXT:    pmovzxbw %xmm1, %xmm0 {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
+; SSE41-NEXT:    punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
+; SSE41-NEXT:    pand .LCPI3_0(%rip), %xmm1
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: zext_16i8_to_16i16:
 ; AVX1:       # BB#0: # %entry
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpunpckhbw {{.*#+}} xmm1 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
-; AVX1-NEXT:    vpmovzxbw %xmm0, %xmm0
+; AVX1-NEXT:    vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: zext_16i8_to_16i16:
 ; AVX2:       # BB#0: # %entry
-; AVX2-NEXT:    vpmovzxbw %xmm0, %ymm0
+; AVX2-NEXT:    vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
 ; AVX2-NEXT:    retq
 entry:
   %t = zext <16 x i8> %z to <16 x i16>
@@ -208,51 +200,43 @@ entry:
 define <16 x i16> @load_zext_16i8_to_16i16(<16 x i8> *%ptr) {
 ; SSE2-LABEL: load_zext_16i8_to_16i16:
 ; SSE2:        # BB#0: # %entry
-; SSE2-NEXT:   movdqa        (%rdi), %xmm1
-; SSE2-NEXT:   movdqa        %xmm1, %xmm0
-; SSE2-NEXT:   punpcklbw     %xmm0, %xmm0    # xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; SSE2-NEXT:   movdqa        {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
-; SSE2-NEXT:   pand  %xmm2, %xmm0
-; SSE2-NEXT:   punpckhbw     %xmm1, %xmm1    # xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; SSE2-NEXT:   pand  %xmm2, %xmm1
+; SSE2-NEXT:   movdqa (%rdi), %xmm1
+; SSE2-NEXT:   pxor %xmm2, %xmm2
+; SSE2-NEXT:   movdqa %xmm1, %xmm0
+; SSE2-NEXT:   punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; SSE2-NEXT:   punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
+; SSE2-NEXT:   pand .LCPI4_0(%rip), %xmm1
 ; SSE2-NEXT:   retq
-
+;
 ; SSSE3-LABEL: load_zext_16i8_to_16i16:
 ; SSSE3:        # BB#0: # %entry
-; SSSE3-NEXT:   movdqa        (%rdi), %xmm1
-; SSSE3-NEXT:   movdqa        %xmm1, %xmm0
-; SSSE3-NEXT:   punpcklbw     %xmm0, %xmm0    # xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; SSSE3-NEXT:   movdqa        {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
-; SSSE3-NEXT:   pand  %xmm2, %xmm0
-; SSSE3-NEXT:   punpckhbw     %xmm1, %xmm1    # xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; SSSE3-NEXT:   pand  %xmm2, %xmm1
+; SSSE3-NEXT:   movdqa (%rdi), %xmm1
+; SSSE3-NEXT:   pxor %xmm2, %xmm2
+; SSSE3-NEXT:   movdqa %xmm1, %xmm0
+; SSSE3-NEXT:   punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; SSSE3-NEXT:   punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
+; SSSE3-NEXT:   pand .LCPI4_0(%rip), %xmm1
 ; SSSE3-NEXT:   retq
-
+;
 ; SSE41-LABEL: load_zext_16i8_to_16i16:
-; SSE41:        # BB#0: # %entry
-; SSE41-NEXT: 	movdqa	(%rdi), %xmm1
-; SSE41-NEXT: 	pmovzxbw	%xmm1, %xmm0
-; SSE41-NEXT: 	movdqa	{{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
-; SSE41-NEXT: 	pand	%xmm2, %xmm0
-; SSE41-NEXT: 	punpckhbw	%xmm1, %xmm1    # xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; SSE41-NEXT: 	pand	%xmm2, %xmm1
-; SSE41-NEXT: 	retq
-
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    pmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
+; SSE41-NEXT:    pmovzxbw {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
+; SSE41-NEXT:    retq
+;
 ; AVX1-LABEL: load_zext_16i8_to_16i16:
-; AVX1:        # BB#0: # %entry
-; AVX1-NEXT: 	vmovdqa	(%rdi), %xmm0
-; AVX1-NEXT: 	vpxor	%xmm1, %xmm1, %xmm1
-; AVX1-NEXT: 	vpunpckhbw	%xmm1, %xmm0, %xmm1 # xmm1 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
-; AVX1-NEXT: 	vpmovzxbw	%xmm0, %xmm0
-; AVX1-NEXT: 	vinsertf128	$1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: 	retq
-
+; AVX1:       # BB#0: # %entry
+; AVX1-NEXT:    vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
+; AVX1-NEXT:    vpmovzxbw {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
 ; AVX2-LABEL: load_zext_16i8_to_16i16:
-; AVX2:        # BB#0: # %entry
-; AVX2-NEXT: 	vpmovzxbw	(%rdi), %ymm0
-; AVX2-NEXT: 	retq
+; AVX2:       # BB#0: # %entry
+; AVX2-NEXT:    vpmovzxbw {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero
+; AVX2-NEXT:    retq
 entry:
- %X = load <16 x i8>* %ptr
+ %X = load <16 x i8>, <16 x i8>* %ptr
  %Y = zext <16 x i8> %X to <16 x i16>
  ret <16 x i16> %Y
 }
@@ -260,101 +244,234 @@ entry:
 define <8 x i32> @load_zext_8i16_to_8i32(<8 x i16> *%ptr) {
 ; SSE2-LABEL: load_zext_8i16_to_8i32:
 ; SSE2:          # BB#0: # %entry
-; SSE2-NEXT:   movdqa        (%rdi), %xmm1
-; SSE2-NEXT:   movdqa        %xmm1, %xmm0
-; SSE2-NEXT:   punpcklwd     %xmm0, %xmm0    # xmm0 = xmm0[0,0,1,1,2,2,3,3]
-; SSE2-NEXT:   movdqa        {{.*#+}} xmm2 = [65535,65535,65535,65535]
-; SSE2-NEXT:   pand  %xmm2, %xmm0
-; SSE2-NEXT:   punpckhwd     %xmm1, %xmm1    # xmm1 = xmm1[4,4,5,5,6,6,7,7]
-; SSE2-NEXT:   pand  %xmm2, %xmm1
+; SSE2-NEXT:   movdqa (%rdi), %xmm1
+; SSE2-NEXT:   pxor %xmm2, %xmm2
+; SSE2-NEXT:   movdqa %xmm1, %xmm0
+; SSE2-NEXT:   punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; SSE2-NEXT:   punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
+; SSE2-NEXT:   pand .LCPI5_0(%rip), %xmm1
 ; SSE2-NEXT:   retq
-
+;
 ; SSSE3-LABEL: load_zext_8i16_to_8i32:
 ; SSSE3:        # BB#0: # %entry
-; SSSE3-NEXT:   movdqa        (%rdi), %xmm1
-; SSSE3-NEXT:   movdqa        %xmm1, %xmm0
-; SSSE3-NEXT:   punpcklwd     %xmm0, %xmm0    # xmm0 = xmm0[0,0,1,1,2,2,3,3]
-; SSSE3-NEXT:   movdqa        {{.*#+}} xmm2 = [65535,65535,65535,65535]
-; SSSE3-NEXT:   pand  %xmm2, %xmm0
-; SSSE3-NEXT:   punpckhwd     %xmm1, %xmm1    # xmm1 = xmm1[4,4,5,5,6,6,7,7]
-; SSSE3-NEXT:   pand  %xmm2, %xmm1
+; SSSE3-NEXT:   movdqa (%rdi), %xmm1
+; SSSE3-NEXT:   pxor %xmm2, %xmm2
+; SSSE3-NEXT:   movdqa %xmm1, %xmm0
+; SSSE3-NEXT:   punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; SSSE3-NEXT:   punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
+; SSSE3-NEXT:   pand .LCPI5_0(%rip), %xmm1
 ; SSSE3-NEXT:   retq
-
+;
 ; SSE41-LABEL: load_zext_8i16_to_8i32:
-; SSE41:        # BB#0: # %entry
-; SSE41-NEXT: 	movdqa	(%rdi), %xmm1
-; SSE41-NEXT: 	pmovzxwd	%xmm1, %xmm0
-; SSE41-NEXT: 	movdqa	{{.*#+}} xmm2 = [65535,65535,65535,65535]
-; SSE41-NEXT: 	pand	%xmm2, %xmm0
-; SSE41-NEXT: 	punpckhwd	%xmm1, %xmm1    # xmm1 = xmm1[4,4,5,5,6,6,7,7]
-; SSE41-NEXT: 	pand	%xmm2, %xmm1
-; SSE41-NEXT: 	retq
-
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; SSE41-NEXT:    pmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; SSE41-NEXT:    retq
+;
 ; AVX1-LABEL: load_zext_8i16_to_8i32:
-; AVX1:        # BB#0: # %entry
-; AVX1-NEXT:    vmovdqa       (%rdi), %xmm0
-; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
-; AVX1-NEXT:    vpunpckhwd    %xmm1, %xmm0, %xmm1 # xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
-; AVX1-NEXT:    vpmovzxwd     %xmm0, %xmm0
-; AVX1-NEXT:    vinsertf128   $1, %xmm1, %ymm0, %ymm0
+; AVX1:       # BB#0: # %entry
+; AVX1-NEXT:    vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; AVX1-NEXT:    vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
-
+;
 ; AVX2-LABEL: load_zext_8i16_to_8i32:
-; AVX2:        # BB#0: # %entry
-; AVX2-NEXT: 	vpmovzxwd	(%rdi), %ymm0
-; AVX2-NEXT: 	retq
+; AVX2:       # BB#0: # %entry
+; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
+; AVX2-NEXT:    retq
 entry:
- %X = load <8 x i16>* %ptr
+ %X = load <8 x i16>, <8 x i16>* %ptr
  %Y = zext <8 x i16> %X to <8 x i32>
  ret <8 x i32>%Y
 }
 
 define <4 x i64> @load_zext_4i32_to_4i64(<4 x i32> *%ptr) {
 ; SSE2-LABEL: load_zext_4i32_to_4i64:
-; SSE2:          # BB#0: # %entry
-; SSE2-NEXT:   movdqa        (%rdi), %xmm1
-; SSE2-NEXT:   pshufd        $-44, %xmm1, %xmm0      # xmm0 = xmm1[0,1,1,3]
-; SSE2-NEXT:   movdqa        {{.*#+}} xmm2 = [4294967295,4294967295]
-; SSE2-NEXT:   pand  %xmm2, %xmm0
-; SSE2-NEXT:   pshufd        $-6, %xmm1, %xmm1       # xmm1 = xmm1[2,2,3,3]
-; SSE2-NEXT:   pand  %xmm2, %xmm1
-; SSE2-NEXT:   retq
-
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    movdqa (%rdi), %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[0,1,1,3]
+; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [4294967295,4294967295]
+; SSE2-NEXT:    pand %xmm2, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
+; SSE2-NEXT:    pand %xmm2, %xmm1
+; SSE2-NEXT:    retq
+;
 ; SSSE3-LABEL: load_zext_4i32_to_4i64:
-; SSSE3:        # BB#0: # %entry
-; SSSE3-NEXT:   movdqa        (%rdi), %xmm1
-; SSSE3-NEXT:   pshufd        $-44, %xmm1, %xmm0      # xmm0 = xmm1[0,1,1,3]
-; SSSE3-NEXT:   movdqa        {{.*#+}} xmm2 = [4294967295,4294967295]
-; SSSE3-NEXT:   pand  %xmm2, %xmm0
-; SSSE3-NEXT:   pshufd        $-6, %xmm1, %xmm1       # xmm1 = xmm1[2,2,3,3]
-; SSSE3-NEXT:   pand  %xmm2, %xmm1
-; SSSE3-NEXT:   retq
-
+; SSSE3:       # BB#0: # %entry
+; SSSE3-NEXT:    movdqa (%rdi), %xmm1
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[0,1,1,3]
+; SSSE3-NEXT:    movdqa {{.*#+}} xmm2 = [4294967295,4294967295]
+; SSSE3-NEXT:    pand %xmm2, %xmm0
+; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
+; SSSE3-NEXT:    pand %xmm2, %xmm1
+; SSSE3-NEXT:    retq
+;
 ; SSE41-LABEL: load_zext_4i32_to_4i64:
-; SSE41:        # BB#0: # %entry
-; SSE41-NEXT: 	movdqa	(%rdi), %xmm1
-; SSE41-NEXT: 	pmovzxdq	%xmm1, %xmm0
-; SSE41-NEXT: 	movdqa	{{.*#+}} xmm2 = [4294967295,4294967295]
-; SSE41-NEXT: 	pand	%xmm2, %xmm0
-; SSE41-NEXT: 	pshufd	$-6, %xmm1, %xmm1       # xmm1 = xmm1[2,2,3,3]
-; SSE41-NEXT: 	pand	%xmm2, %xmm1
-; SSE41-NEXT: 	retq
-
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
+; SSE41-NEXT:    pmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero
+; SSE41-NEXT:    retq
+;
 ; AVX1-LABEL: load_zext_4i32_to_4i64:
-; AVX1:        # BB#0: # %entry
-; AVX1-NEXT: 	vmovdqa	(%rdi), %xmm0
-; AVX1-NEXT: 	vpxor	%xmm1, %xmm1, %xmm1
-; AVX1-NEXT: 	vpunpckhdq	%xmm1, %xmm0, %xmm1 # xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX1-NEXT: 	vpmovzxdq	%xmm0, %xmm0
-; AVX1-NEXT: 	vinsertf128	$1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: 	retq
-
+; AVX1:       # BB#0: # %entry
+; AVX1-NEXT:    vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
+; AVX1-NEXT:    vpmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
 ; AVX2-LABEL: load_zext_4i32_to_4i64:
-; AVX2:        # BB#0: # %entry
-; AVX2-NEXT: 	vpmovzxdq	(%rdi), %ymm0
-; AVX2-NEXT: 	retq
+; AVX2:       # BB#0: # %entry
+; AVX2-NEXT:    vpmovzxdq {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; AVX2-NEXT:    retq
 entry:
- %X = load <4 x i32>* %ptr
+ %X = load <4 x i32>, <4 x i32>* %ptr
  %Y = zext <4 x i32> %X to <4 x i64>
  ret <4 x i64>%Y
 }
+
+define <8 x i32> @shuf_zext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
+; SSE2-LABEL: shuf_zext_8i16_to_8i32:
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    movdqa %xmm0, %xmm1
+; SSE2-NEXT:    pxor %xmm2, %xmm2
+; SSE2-NEXT:    # kill
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: shuf_zext_8i16_to_8i32:
+; SSSE3:       # BB#0: # %entry
+; SSSE3-NEXT:    movdqa %xmm0, %xmm1
+; SSSE3-NEXT:    pxor %xmm2, %xmm2
+; SSSE3-NEXT:    # kill
+; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; SSSE3-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuf_zext_8i16_to_8i32:
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    movdqa %xmm0, %xmm1
+; SSE41-NEXT:    pxor %xmm2, %xmm2
+; SSE41-NEXT:    pmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
+; SSE41-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: shuf_zext_8i16_to_8i32:
+; AVX1:       # BB#0: # %entry
+; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; AVX1-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuf_zext_8i16_to_8i32:
+; AVX2:       # BB#0: # %entry
+; AVX2-NEXT:    # kill
+; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX2-NEXT:    retq
+entry:
+  %B = shufflevector <8 x i16> %A, <8 x i16> zeroinitializer, <16 x i32> <i32 0, i32 8, i32 1, i32 8, i32 2, i32 8, i32 3, i32 8, i32 4, i32 8, i32 5, i32 8, i32 6, i32 8, i32 7, i32 8>
+  %Z = bitcast <16 x i16> %B to <8 x i32>
+  ret <8 x i32> %Z
+}
+
+define <4 x i64> @shuf_zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
+; SSE2-LABEL: shuf_zext_4i32_to_4i64:
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    movdqa %xmm0, %xmm1
+; SSE2-NEXT:    pxor %xmm2, %xmm2
+; SSE2-NEXT:    # kill
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-NEXT:    punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: shuf_zext_4i32_to_4i64:
+; SSSE3:       # BB#0: # %entry
+; SSSE3-NEXT:    movdqa %xmm0, %xmm1
+; SSSE3-NEXT:    pxor %xmm2, %xmm2
+; SSSE3-NEXT:    # kill
+; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSSE3-NEXT:    punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuf_zext_4i32_to_4i64:
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    movdqa %xmm0, %xmm1
+; SSE41-NEXT:    pxor %xmm2, %xmm2
+; SSE41-NEXT:    pmovzxdq {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero
+; SSE41-NEXT:    punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: shuf_zext_4i32_to_4i64:
+; AVX1:       # BB#0: # %entry
+; AVX1-NEXT:    vinsertps {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero
+; AVX1-NEXT:    vxorpd %xmm2, %xmm2, %xmm2
+; AVX1-NEXT:    vblendpd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
+; AVX1-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,0]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuf_zext_4i32_to_4i64:
+; AVX2:       # BB#0: # %entry
+; AVX2-NEXT:    # kill
+; AVX2-NEXT:    vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; AVX2-NEXT:    retq
+entry:
+  %B = shufflevector <4 x i32> %A, <4 x i32> zeroinitializer, <8 x i32> <i32 0, i32 4, i32 1, i32 4, i32 2, i32 4, i32 3, i32 4>
+  %Z = bitcast <8 x i32> %B to <4 x i64>
+  ret <4 x i64> %Z
+}
+
+define <8 x i32> @shuf_zext_8i8_to_8i32(<8 x i8> %A) {
+; SSE2-LABEL: shuf_zext_8i8_to_8i32:
+; SSE2:       # BB#0: # %entry
+; SSE2-NEXT:    pand .LCPI9_0(%rip), %xmm0
+; SSE2-NEXT:    packuswb %xmm0, %xmm0
+; SSE2-NEXT:    pxor %xmm1, %xmm1
+; SSE2-NEXT:    movdqa %xmm0, %xmm2
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
+; SSE2-NEXT:    movdqa {{.*#+}} xmm1 = [0,255,255,255,0,255,255,255,0,255,255,255,0,255,255,255]
+; SSE2-NEXT:    pandn %xmm0, %xmm1
+; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: shuf_zext_8i8_to_8i32:
+; SSSE3:       # BB#0: # %entry
+; SSSE3-NEXT:    movdqa %xmm0, %xmm1
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; SSSE3-NEXT:    pxor %xmm2, %xmm2
+; SSSE3-NEXT:    movdqa %xmm1, %xmm0
+; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero
+; SSSE3-NEXT:    retq
+;
+; SSE41-LABEL: shuf_zext_8i8_to_8i32:
+; SSE41:       # BB#0: # %entry
+; SSE41-NEXT:    movdqa %xmm0, %xmm1
+; SSE41-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm0 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
+; SSE41-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: shuf_zext_8i8_to_8i32:
+; AVX1:       # BB#0: # %entry
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; AVX1-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: shuf_zext_8i8_to_8i32:
+; AVX2:       # BB#0: # %entry
+; AVX2-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; AVX2-NEXT:    vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
+; AVX2-NEXT:    retq
+entry:
+  %B = shufflevector <8 x i8> %A, <8 x i8> zeroinitializer, <32 x i32> <i32 0, i32 8, i32 8, i32 8, i32 1, i32 8, i32 8, i32 8, i32 2, i32 8, i32 8, i32 8, i32 3, i32 8, i32 8, i32 8, i32 4, i32 8, i32 8, i32 8, i32 5, i32 8, i32 8, i32 8, i32 6, i32 8, i32 8, i32 8, i32 7, i32 8, i32 8, i32 8>
+  %Z = bitcast <32 x i8> %B to <8 x i32>
+  ret <8 x i32> %Z
+}
diff --git a/test/CodeGen/X86/vector-zmov.ll b/test/CodeGen/X86/vector-zmov.ll
index 4de2543a1d6b..cf592b1e9f42 100644
--- a/test/CodeGen/X86/vector-zmov.ll
+++ b/test/CodeGen/X86/vector-zmov.ll
@@ -15,7 +15,7 @@ define <4 x i32> @load_zmov_4i32_to_0zzz(<4 x i32> *%ptr) {
 ; AVX-NEXT:   vmovd (%rdi), %xmm0
 ; AVX-NEXT:   retq
 entry:
-  %X = load <4 x i32>* %ptr
+  %X = load <4 x i32>, <4 x i32>* %ptr
   %Y = shufflevector <4 x i32> %X, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 4>
   ret <4 x i32>%Y
 }
@@ -31,7 +31,7 @@ define <2 x i64> @load_zmov_2i64_to_0z(<2 x i64> *%ptr) {
 ; AVX-NEXT:   vmovq (%rdi), %xmm0
 ; AVX-NEXT:   retq
 entry:
-  %X = load <2 x i64>* %ptr
+  %X = load <2 x i64>, <2 x i64>* %ptr
   %Y = shufflevector <2 x i64> %X, <2 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>
   ret <2 x i64>%Y
 }
diff --git a/test/CodeGen/X86/vector.ll b/test/CodeGen/X86/vector.ll
index 82d20a23f357..39e7f0e0b066 100644
--- a/test/CodeGen/X86/vector.ll
+++ b/test/CodeGen/X86/vector.ll
@@ -13,48 +13,48 @@
 ;;; TEST HANDLING OF VARIOUS VECTOR SIZES
 
 define void @test_f1(%f1* %P, %f1* %Q, %f1* %S) {
-        %p = load %f1* %P               ; <%f1> [#uses=1]
-        %q = load %f1* %Q               ; <%f1> [#uses=1]
+        %p = load %f1, %f1* %P               ; <%f1> [#uses=1]
+        %q = load %f1, %f1* %Q               ; <%f1> [#uses=1]
         %R = fadd %f1 %p, %q             ; <%f1> [#uses=1]
         store %f1 %R, %f1* %S
         ret void
 }
 
 define void @test_f2(%f2* %P, %f2* %Q, %f2* %S) {
-        %p = load %f2* %P               ; <%f2> [#uses=1]
-        %q = load %f2* %Q               ; <%f2> [#uses=1]
+        %p = load %f2, %f2* %P               ; <%f2> [#uses=1]
+        %q = load %f2, %f2* %Q               ; <%f2> [#uses=1]
         %R = fadd %f2 %p, %q             ; <%f2> [#uses=1]
         store %f2 %R, %f2* %S
         ret void
 }
 
 define void @test_f4(%f4* %P, %f4* %Q, %f4* %S) {
-        %p = load %f4* %P               ; <%f4> [#uses=1]
-        %q = load %f4* %Q               ; <%f4> [#uses=1]
+        %p = load %f4, %f4* %P               ; <%f4> [#uses=1]
+        %q = load %f4, %f4* %Q               ; <%f4> [#uses=1]
         %R = fadd %f4 %p, %q             ; <%f4> [#uses=1]
         store %f4 %R, %f4* %S
         ret void
 }
 
 define void @test_f8(%f8* %P, %f8* %Q, %f8* %S) {
-        %p = load %f8* %P               ; <%f8> [#uses=1]
-        %q = load %f8* %Q               ; <%f8> [#uses=1]
+        %p = load %f8, %f8* %P               ; <%f8> [#uses=1]
+        %q = load %f8, %f8* %Q               ; <%f8> [#uses=1]
         %R = fadd %f8 %p, %q             ; <%f8> [#uses=1]
         store %f8 %R, %f8* %S
         ret void
 }
 
 define void @test_fmul(%f8* %P, %f8* %Q, %f8* %S) {
-        %p = load %f8* %P               ; <%f8> [#uses=1]
-        %q = load %f8* %Q               ; <%f8> [#uses=1]
+        %p = load %f8, %f8* %P               ; <%f8> [#uses=1]
+        %q = load %f8, %f8* %Q               ; <%f8> [#uses=1]
         %R = fmul %f8 %p, %q             ; <%f8> [#uses=1]
         store %f8 %R, %f8* %S
         ret void
 }
 
 define void @test_div(%f8* %P, %f8* %Q, %f8* %S) {
-        %p = load %f8* %P               ; <%f8> [#uses=1]
-        %q = load %f8* %Q               ; <%f8> [#uses=1]
+        %p = load %f8, %f8* %P               ; <%f8> [#uses=1]
+        %q = load %f8, %f8* %Q               ; <%f8> [#uses=1]
         %R = fdiv %f8 %p, %q            ; <%f8> [#uses=1]
         store %f8 %R, %f8* %S
         ret void
@@ -63,21 +63,21 @@ define void @test_div(%f8* %P, %f8* %Q, %f8* %S) {
 ;;; TEST VECTOR CONSTRUCTS
 
 define void @test_cst(%f4* %P, %f4* %S) {
-        %p = load %f4* %P               ; <%f4> [#uses=1]
+        %p = load %f4, %f4* %P               ; <%f4> [#uses=1]
         %R = fadd %f4 %p, < float 0x3FB99999A0000000, float 1.000000e+00, float 2.000000e+00, float 4.500000e+00 >             ; <%f4> [#uses=1]
         store %f4 %R, %f4* %S
         ret void
 }
 
 define void @test_zero(%f4* %P, %f4* %S) {
-        %p = load %f4* %P               ; <%f4> [#uses=1]
+        %p = load %f4, %f4* %P               ; <%f4> [#uses=1]
         %R = fadd %f4 %p, zeroinitializer                ; <%f4> [#uses=1]
         store %f4 %R, %f4* %S
         ret void
 }
 
 define void @test_undef(%f4* %P, %f4* %S) {
-        %p = load %f4* %P               ; <%f4> [#uses=1]
+        %p = load %f4, %f4* %P               ; <%f4> [#uses=1]
         %R = fadd %f4 %p, undef          ; <%f4> [#uses=1]
         store %f4 %R, %f4* %S
         ret void
@@ -102,19 +102,19 @@ define void @test_scalar_to_vector(float %F, %f4* %S) {
 }
 
 define float @test_extract_elt(%f8* %P) {
-        %p = load %f8* %P               ; <%f8> [#uses=1]
+        %p = load %f8, %f8* %P               ; <%f8> [#uses=1]
         %R = extractelement %f8 %p, i32 3               ; <float> [#uses=1]
         ret float %R
 }
 
 define double @test_extract_elt2(%d8* %P) {
-        %p = load %d8* %P               ; <%d8> [#uses=1]
+        %p = load %d8, %d8* %P               ; <%d8> [#uses=1]
         %R = extractelement %d8 %p, i32 3               ; <double> [#uses=1]
         ret double %R
 }
 
 define void @test_cast_1(%f4* %b, %i4* %a) {
-        %tmp = load %f4* %b             ; <%f4> [#uses=1]
+        %tmp = load %f4, %f4* %b             ; <%f4> [#uses=1]
         %tmp2 = fadd %f4 %tmp, < float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00 >              ; <%f4> [#uses=1]
         %tmp3 = bitcast %f4 %tmp2 to %i4                ; <%i4> [#uses=1]
         %tmp4 = add %i4 %tmp3, < i32 1, i32 2, i32 3, i32 4 >           ; <%i4> [#uses=1]
@@ -123,7 +123,7 @@ define void @test_cast_1(%f4* %b, %i4* %a) {
 }
 
 define void @test_cast_2(%f8* %a, <8 x i32>* %b) {
-        %T = load %f8* %a               ; <%f8> [#uses=1]
+        %T = load %f8, %f8* %a               ; <%f8> [#uses=1]
         %T2 = bitcast %f8 %T to <8 x i32>               ; <<8 x i32>> [#uses=1]
         store <8 x i32> %T2, <8 x i32>* %b
         ret void
@@ -137,7 +137,7 @@ define void @splat(%f4* %P, %f4* %Q, float %X) {
         %tmp2 = insertelement %f4 %tmp, float %X, i32 1         ; <%f4> [#uses=1]
         %tmp4 = insertelement %f4 %tmp2, float %X, i32 2                ; <%f4> [#uses=1]
         %tmp6 = insertelement %f4 %tmp4, float %X, i32 3                ; <%f4> [#uses=1]
-        %q = load %f4* %Q               ; <%f4> [#uses=1]
+        %q = load %f4, %f4* %Q               ; <%f4> [#uses=1]
         %R = fadd %f4 %q, %tmp6          ; <%f4> [#uses=1]
         store %f4 %R, %f4* %P
         ret void
@@ -148,7 +148,7 @@ define void @splat_i4(%i4* %P, %i4* %Q, i32 %X) {
         %tmp2 = insertelement %i4 %tmp, i32 %X, i32 1           ; <%i4> [#uses=1]
         %tmp4 = insertelement %i4 %tmp2, i32 %X, i32 2          ; <%i4> [#uses=1]
         %tmp6 = insertelement %i4 %tmp4, i32 %X, i32 3          ; <%i4> [#uses=1]
-        %q = load %i4* %Q               ; <%i4> [#uses=1]
+        %q = load %i4, %i4* %Q               ; <%i4> [#uses=1]
         %R = add %i4 %q, %tmp6          ; <%i4> [#uses=1]
         store %i4 %R, %i4* %P
         ret void
diff --git a/test/CodeGen/X86/viabs.ll b/test/CodeGen/X86/viabs.ll
index d9f2cb074759..fe528fd4ea24 100644
--- a/test/CodeGen/X86/viabs.ll
+++ b/test/CodeGen/X86/viabs.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=x86-64 -mcpu=x86-64 | FileCheck %s -check-prefix=SSE2
-; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s -check-prefix=SSSE3
-; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s -check-prefix=AVX2
-; RUN: llc < %s -march=x86-64 -mcpu=knl | FileCheck %s -check-prefix=AVX512
+; RUN: llc < %s -march=x86-64 -mattr=sse2    | FileCheck %s -check-prefix=SSE2
+; RUN: llc < %s -march=x86-64 -mattr=ssse3   | FileCheck %s -check-prefix=SSSE3
+; RUN: llc < %s -march=x86-64 -mattr=avx2    | FileCheck %s -check-prefix=AVX2
+; RUN: llc < %s -march=x86-64 -mattr=avx512f | FileCheck %s -check-prefix=AVX512
 
 define <4 x i32> @test1(<4 x i32> %a) nounwind {
 ; SSE2-LABEL: test1:
@@ -262,7 +262,7 @@ define <8 x i64> @test13(<8 x i64>* %a.ptr) nounwind {
 ; AVX512-LABEL: test13:
 ; AVX512: vpabsq (%
 ; AVX512-NEXT: ret
-        %a = load <8 x i64>* %a.ptr, align 8
+        %a = load <8 x i64>, <8 x i64>* %a.ptr, align 8
         %tmp1neg = sub <8 x i64> zeroinitializer, %a
         %b = icmp sle <8 x i64> %a, zeroinitializer
         %abs = select <8 x i1> %b, <8 x i64> %tmp1neg, <8 x i64> %a
diff --git a/test/CodeGen/X86/visibility2.ll b/test/CodeGen/X86/visibility2.ll
index 72ea7338de61..48a0ac692198 100644
--- a/test/CodeGen/X86/visibility2.ll
+++ b/test/CodeGen/X86/visibility2.ll
@@ -8,7 +8,7 @@
 
 define void @foo1() nounwind ssp {
 entry:
-  %tmp = load i8** @foo_private_extern_str, align 8
+  %tmp = load i8*, i8** @foo_private_extern_str, align 8
   call void @foo3(i8* %tmp)
   ret void
 }
diff --git a/test/CodeGen/X86/volatile.ll b/test/CodeGen/X86/volatile.ll
index 1a82014536e7..8d521b46f7c9 100644
--- a/test/CodeGen/X86/volatile.ll
+++ b/test/CodeGen/X86/volatile.ll
@@ -4,14 +4,14 @@
 @x = external global double
 
 define void @foo() nounwind  {
-  %a = load volatile double* @x
+  %a = load volatile double, double* @x
   store volatile double 0.0, double* @x
   store volatile double 0.0, double* @x
-  %b = load volatile double* @x
+  %b = load volatile double, double* @x
   ret void
 }
 
 define void @bar() nounwind  {
-  %c = load volatile double* @x
+  %c = load volatile double, double* @x
   ret void
 }
diff --git a/test/CodeGen/X86/vortex-bug.ll b/test/CodeGen/X86/vortex-bug.ll
index 40f11175b20a..b1f42681a508 100644
--- a/test/CodeGen/X86/vortex-bug.ll
+++ b/test/CodeGen/X86/vortex-bug.ll
@@ -16,6 +16,6 @@ bb137.i:		; preds = %bb137.i, %entry
 	br i1 false, label %bb137.i, label %bb149.i.loopexit
 
 bb149.i.loopexit:		; preds = %bb137.i
-	%tmp139.i = getelementptr i8* %FieldName, i64 %tmp139.rec.i		; <i8*> [#uses=0]
+	%tmp139.i = getelementptr i8, i8* %FieldName, i64 %tmp139.rec.i		; <i8*> [#uses=0]
 	unreachable
 }
diff --git a/test/CodeGen/X86/vselect-2.ll b/test/CodeGen/X86/vselect-2.ll
index 0991bdacd9c5..fe4cfba08b8a 100644
--- a/test/CodeGen/X86/vselect-2.ll
+++ b/test/CodeGen/X86/vselect-2.ll
@@ -2,13 +2,13 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
 
 define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) {
-; SSE2-LABEL: test1
-; SSE2:        # BB#0:
-; SSE2-NEXT:     movsd %xmm0, %xmm1
-; SSE2-NEXT:     movaps %xmm1, %xmm0
-; SSE2-NEXT:     retq
+; SSE2-LABEL: test1:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE2-NEXT:    movapd %xmm1, %xmm0
+; SSE2-NEXT:    retq
 ;
-; SSE41-LABEL: test1
+; SSE41-LABEL: test1:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
 ; SSE41-NEXT:    retq
@@ -17,12 +17,12 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) {
 }
 
 define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
-; SSE2-LABEL: test2
-; SSE2:        # BB#0:
-; SSE2-NEXT:     movsd %xmm1, %xmm0
-; SSE2-NEXT:     retq
+; SSE2-LABEL: test2:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
+; SSE2-NEXT:    retq
 ;
-; SSE41-LABEL: test2
+; SSE41-LABEL: test2:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
 ; SSE41-NEXT:    retq
@@ -31,13 +31,13 @@ define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
 }
 
 define <4 x float> @test3(<4 x float> %A, <4 x float> %B) {
-; SSE2-LABEL: test3
-; SSE2:        # BB#0:
-; SSE2-NEXT:     movsd %xmm0, %xmm1
-; SSE2-NEXT:     movaps %xmm1, %xmm0
-; SSE2-NEXT:     retq
+; SSE2-LABEL: test3:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE2-NEXT:    movapd %xmm1, %xmm0
+; SSE2-NEXT:    retq
 ;
-; SSE41-LABEL: test3
+; SSE41-LABEL: test3:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
 ; SSE41-NEXT:    retq
@@ -46,12 +46,12 @@ define <4 x float> @test3(<4 x float> %A, <4 x float> %B) {
 }
 
 define <4 x float> @test4(<4 x float> %A, <4 x float> %B) {
-; SSE2-LABEL: test4
-; SSE2:        # BB#0:
-; SSE2-NEXT:     movsd %xmm1, %xmm0
-; SSE2-NEXT:     retq
+; SSE2-LABEL: test4:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
+; SSE2-NEXT:    retq
 ;
-; SSE41-LABEL: test4
+; SSE41-LABEL: test4:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE41-NEXT:    retq
diff --git a/test/CodeGen/X86/vselect-avx.ll b/test/CodeGen/X86/vselect-avx.ll
index 0c0f4bbf992a..de04a097de02 100644
--- a/test/CodeGen/X86/vselect-avx.ll
+++ b/test/CodeGen/X86/vselect-avx.ll
@@ -14,8 +14,8 @@ target triple = "x86_64-apple-macosx"
 ; <rdar://problem/18675020>
 
 ; CHECK-LABEL: test:
-; CHECK: vmovdqa {{.*#+}} xmm0 = [65535,0,0,65535]
-; CHECK: vmovdqa {{.*#+}} xmm2 = [65533,124,125,14807]
+; CHECK: vmovdqa {{.*#+}} xmm1 = [65533,124,125,14807]
+; CHECK: vmovdqa {{.*#+}} xmm1 = [65535,0,0,65535]
 ; CHECK: ret
 define void @test(<4 x i16>* %a, <4 x i16>* %b) {
 body:
@@ -33,17 +33,18 @@ body:
 ; of the condition.
 ;
 ; CHECK-LABEL: test2:
-; CHECK:	vpslld	$31, %xmm0, %xmm0
-; CHECK-NEXT:	vpmovsxdq	%xmm0, %xmm1
-; CHECK-NEXT:	vpshufd	$78, %xmm0, %xmm0       ## xmm0 = xmm0[2,3,0,1]
-; CHECK-NEXT:	vpmovsxdq	%xmm0, %xmm0
-; CHECK-NEXT:	vinsertf128	$1, %xmm0, %ymm1, [[MASK:%ymm[0-9]+]]
-; CHECK: vblendvpd	[[MASK]]
-; CHECK: retq
+; CHECK:       vpslld $31, %xmm0, %xmm0
+; CHECK-NEXT:  vpsrad $31, %xmm0, %xmm0
+; CHECK-NEXT:  vpmovsxdq %xmm0, %xmm1
+; CHECK-NEXT:  vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; CHECK-NEXT:  vpmovsxdq %xmm0, %xmm0
+; CHECK-NEXT:  vinsertf128 $1, %xmm0, %ymm1, [[MASK:%ymm[0-9]+]]
+; CHECK:       vblendvpd [[MASK]]
+; CHECK:       retq
 define void @test2(double** %call1559, i64 %indvars.iv4198, <4 x i1> %tmp1895) {
 bb:
-  %arrayidx1928 = getelementptr inbounds double** %call1559, i64 %indvars.iv4198
-  %tmp1888 = load double** %arrayidx1928, align 8
+  %arrayidx1928 = getelementptr inbounds double*, double** %call1559, i64 %indvars.iv4198
+  %tmp1888 = load double*, double** %arrayidx1928, align 8
   %predphi.v.v = select <4 x i1> %tmp1895, <4 x double> <double -5.000000e-01, double -5.000000e-01, double -5.000000e-01, double -5.000000e-01>, <4 x double> <double 5.000000e-01, double 5.000000e-01, double 5.000000e-01, double 5.000000e-01>
   %tmp1900 = bitcast double* %tmp1888 to <4 x double>*
   store <4 x double> %predphi.v.v, <4 x double>* %tmp1900, align 8
@@ -59,19 +60,15 @@ bb:
 ; 
 ; <rdar://problem/18819506>
 
-; Note: For now, hard code ORIG_MASK and SHRUNK_MASK registers, because we
-; cannot express that ORIG_MASK must not be equal to ORIG_MASK. Otherwise,
-; even a faulty pattern would pass!
-;  
 ; CHECK-LABEL: test3:
-; Compute the original mask.
-;	CHECK: vpcmpeqd {{%xmm[0-9]+}}, {{%xmm[0-9]+}}, [[ORIG_MASK:%xmm0]]
-; Shrink the bit of the mask.
-; CHECK-NEXT: vpslld	$31, [[ORIG_MASK]], [[SHRUNK_MASK:%xmm3]]
-; Use the shrunk mask in the blend.
-; CHECK-NEXT:	vblendvps	[[SHRUNK_MASK]], %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
-; Use the original mask in the and.
-; CHECK-NEXT: vpand LCPI2_2(%rip), [[ORIG_MASK]], {{%xmm[0-9]+}} 
+; Compute the mask.
+;	CHECK: vpcmpeqd {{%xmm[0-9]+}}, {{%xmm[0-9]+}}, [[MASK:%xmm[0-9]+]]
+; Do not shrink the bit of the mask.
+; CHECK-NOT: vpslld	$31, [[MASK]], {{%xmm[0-9]+}}
+; Use the mask in the blend.
+; CHECK-NEXT:	vblendvps	[[MASK]], %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
+; Use the mask in the and.
+; CHECK-NEXT: vpand LCPI2_2(%rip), [[MASK]], {{%xmm[0-9]+}} 
 ; CHECK: retq
 define void @test3(<4 x i32> %induction30, <4 x i16>* %tmp16, <4 x i16>* %tmp17,  <4 x i16> %tmp3, <4 x i16> %tmp12) {
   %tmp6 = srem <4 x i32> %induction30, <i32 3, i32 3, i32 3, i32 3>
@@ -83,3 +80,14 @@ define void @test3(<4 x i32> %induction30, <4 x i16>* %tmp16, <4 x i16>* %tmp17,
   store <4 x i16> %predphi, <4 x i16>* %tmp17, align 8
  ret void
 }
+
+; We shouldn't try to lower this directly using VSELECT because we don't have
+; vpblendvb in AVX1, only in AVX2. Instead, it should be expanded.
+;
+; CHECK-LABEL: PR22706:
+; CHECK: vpcmpgtb
+; CHECK: vpcmpgtb
+define <32 x i8> @PR22706(<32 x i1> %x) {
+  %tmp = select <32 x i1> %x, <32 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <32 x i8> <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
+  ret <32 x i8> %tmp
+}
diff --git a/test/CodeGen/X86/vselect-minmax.ll b/test/CodeGen/X86/vselect-minmax.ll
index 3efe5684c15b..5ed687f50576 100644
--- a/test/CodeGen/X86/vselect-minmax.ll
+++ b/test/CodeGen/X86/vselect-minmax.ll
@@ -11,12 +11,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp slt <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -46,12 +46,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp sle <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -81,12 +81,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp sgt <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -116,12 +116,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp sge <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -151,12 +151,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp ult <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -186,12 +186,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp ule <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -221,12 +221,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp ugt <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -256,12 +256,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp uge <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -291,12 +291,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp slt <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -326,12 +326,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp sle <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -361,12 +361,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp sgt <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -396,12 +396,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp sge <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -431,12 +431,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp ult <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -466,12 +466,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp ule <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -501,12 +501,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp ugt <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -536,12 +536,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp uge <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -571,12 +571,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp slt <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -606,12 +606,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp sle <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -641,12 +641,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp sgt <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -676,12 +676,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp sge <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -711,12 +711,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp ult <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -746,12 +746,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp ule <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -781,12 +781,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp ugt <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -816,12 +816,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp uge <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -851,12 +851,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp slt <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -880,12 +880,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp sle <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -909,12 +909,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp sgt <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -938,12 +938,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp sge <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -967,12 +967,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp ult <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -996,12 +996,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp ule <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -1025,12 +1025,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp ugt <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -1054,12 +1054,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp uge <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -1083,12 +1083,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp slt <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -1112,12 +1112,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp sle <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -1141,12 +1141,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp sgt <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -1170,12 +1170,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp sge <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -1199,12 +1199,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp ult <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -1228,12 +1228,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp ule <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -1257,12 +1257,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp ugt <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -1286,12 +1286,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp uge <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -1315,12 +1315,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp slt <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -1344,12 +1344,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp sle <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -1373,12 +1373,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp sgt <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -1402,12 +1402,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp sge <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -1431,12 +1431,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp ult <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -1460,12 +1460,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp ule <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -1489,12 +1489,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp ugt <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -1518,12 +1518,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp uge <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -1547,12 +1547,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp slt <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -1582,12 +1582,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp sle <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -1617,12 +1617,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp sgt <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -1652,12 +1652,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp sge <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -1687,12 +1687,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp ult <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -1722,12 +1722,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp ule <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -1757,12 +1757,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp ugt <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -1792,12 +1792,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <16 x i8>*
   %ptr.b = bitcast i8* %gep.b to <16 x i8>*
-  %load.a = load <16 x i8>* %ptr.a, align 2
-  %load.b = load <16 x i8>* %ptr.b, align 2
+  %load.a = load <16 x i8>, <16 x i8>* %ptr.a, align 2
+  %load.b = load <16 x i8>, <16 x i8>* %ptr.b, align 2
   %cmp = icmp uge <16 x i8> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a
   store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2
@@ -1827,12 +1827,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp slt <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -1862,12 +1862,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp sle <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -1897,12 +1897,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp sgt <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -1932,12 +1932,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp sge <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -1967,12 +1967,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp ult <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -2002,12 +2002,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp ule <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -2037,12 +2037,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp ugt <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -2072,12 +2072,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <8 x i16>*
   %ptr.b = bitcast i16* %gep.b to <8 x i16>*
-  %load.a = load <8 x i16>* %ptr.a, align 2
-  %load.b = load <8 x i16>* %ptr.b, align 2
+  %load.a = load <8 x i16>, <8 x i16>* %ptr.a, align 2
+  %load.b = load <8 x i16>, <8 x i16>* %ptr.b, align 2
   %cmp = icmp uge <8 x i16> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a
   store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2
@@ -2107,12 +2107,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp slt <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -2142,12 +2142,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp sle <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -2177,12 +2177,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp sgt <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -2212,12 +2212,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp sge <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -2247,12 +2247,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp ult <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -2282,12 +2282,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp ule <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -2317,12 +2317,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp ugt <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -2352,12 +2352,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i32>*
   %ptr.b = bitcast i32* %gep.b to <4 x i32>*
-  %load.a = load <4 x i32>* %ptr.a, align 2
-  %load.b = load <4 x i32>* %ptr.b, align 2
+  %load.a = load <4 x i32>, <4 x i32>* %ptr.a, align 2
+  %load.b = load <4 x i32>, <4 x i32>* %ptr.b, align 2
   %cmp = icmp uge <4 x i32> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a
   store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2
@@ -2387,12 +2387,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp slt <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -2416,12 +2416,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp sle <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -2445,12 +2445,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp sgt <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -2474,12 +2474,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp sge <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -2503,12 +2503,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp ult <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -2532,12 +2532,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp ule <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -2561,12 +2561,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp ugt <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -2590,12 +2590,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <32 x i8>*
   %ptr.b = bitcast i8* %gep.b to <32 x i8>*
-  %load.a = load <32 x i8>* %ptr.a, align 2
-  %load.b = load <32 x i8>* %ptr.b, align 2
+  %load.a = load <32 x i8>, <32 x i8>* %ptr.a, align 2
+  %load.b = load <32 x i8>, <32 x i8>* %ptr.b, align 2
   %cmp = icmp uge <32 x i8> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a
   store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2
@@ -2619,12 +2619,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp slt <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -2648,12 +2648,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp sle <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -2677,12 +2677,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp sgt <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -2706,12 +2706,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp sge <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -2735,12 +2735,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp ult <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -2764,12 +2764,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp ule <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -2793,12 +2793,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp ugt <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -2822,12 +2822,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <16 x i16>*
   %ptr.b = bitcast i16* %gep.b to <16 x i16>*
-  %load.a = load <16 x i16>* %ptr.a, align 2
-  %load.b = load <16 x i16>* %ptr.b, align 2
+  %load.a = load <16 x i16>, <16 x i16>* %ptr.a, align 2
+  %load.b = load <16 x i16>, <16 x i16>* %ptr.b, align 2
   %cmp = icmp uge <16 x i16> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a
   store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2
@@ -2851,12 +2851,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp slt <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -2880,12 +2880,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp sle <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -2909,12 +2909,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp sgt <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -2938,12 +2938,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp sge <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -2967,12 +2967,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp ult <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -2996,12 +2996,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp ule <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -3025,12 +3025,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp ugt <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -3054,12 +3054,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i32>*
   %ptr.b = bitcast i32* %gep.b to <8 x i32>*
-  %load.a = load <8 x i32>* %ptr.a, align 2
-  %load.b = load <8 x i32>* %ptr.b, align 2
+  %load.a = load <8 x i32>, <8 x i32>* %ptr.a, align 2
+  %load.b = load <8 x i32>, <8 x i32>* %ptr.b, align 2
   %cmp = icmp uge <8 x i32> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a
   store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2
@@ -3085,12 +3085,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp slt <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.a, <64 x i8> %load.b
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -3111,12 +3111,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp sle <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.a, <64 x i8> %load.b
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -3137,12 +3137,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp sgt <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.a, <64 x i8> %load.b
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -3163,12 +3163,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp sge <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.a, <64 x i8> %load.b
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -3189,12 +3189,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp ult <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.a, <64 x i8> %load.b
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -3215,12 +3215,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp ule <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.a, <64 x i8> %load.b
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -3241,12 +3241,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp ugt <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.a, <64 x i8> %load.b
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -3267,12 +3267,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp uge <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.a, <64 x i8> %load.b
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -3293,12 +3293,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp slt <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.a, <32 x i16> %load.b
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -3319,12 +3319,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp sle <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.a, <32 x i16> %load.b
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -3345,12 +3345,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp sgt <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.a, <32 x i16> %load.b
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -3371,12 +3371,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp sge <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.a, <32 x i16> %load.b
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -3397,12 +3397,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp ult <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.a, <32 x i16> %load.b
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -3423,12 +3423,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp ule <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.a, <32 x i16> %load.b
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -3449,12 +3449,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp ugt <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.a, <32 x i16> %load.b
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -3475,12 +3475,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp uge <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.a, <32 x i16> %load.b
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -3501,12 +3501,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp slt <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.a, <16 x i32> %load.b
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -3527,12 +3527,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp sle <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.a, <16 x i32> %load.b
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -3553,12 +3553,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp sgt <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.a, <16 x i32> %load.b
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -3579,12 +3579,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp sge <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.a, <16 x i32> %load.b
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -3605,12 +3605,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp ult <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.a, <16 x i32> %load.b
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -3631,12 +3631,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp ule <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.a, <16 x i32> %load.b
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -3657,12 +3657,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp ugt <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.a, <16 x i32> %load.b
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -3683,12 +3683,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp uge <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.a, <16 x i32> %load.b
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -3709,12 +3709,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp slt <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.a, <8 x i64> %load.b
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -3735,12 +3735,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp sle <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.a, <8 x i64> %load.b
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -3761,12 +3761,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp sgt <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.a, <8 x i64> %load.b
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -3787,12 +3787,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp sge <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.a, <8 x i64> %load.b
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -3813,12 +3813,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp ult <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.a, <8 x i64> %load.b
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -3839,12 +3839,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp ule <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.a, <8 x i64> %load.b
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -3865,12 +3865,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp ugt <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.a, <8 x i64> %load.b
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -3891,12 +3891,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp uge <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.a, <8 x i64> %load.b
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -3917,12 +3917,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp slt <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.b, <64 x i8> %load.a
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -3943,12 +3943,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp sle <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.b, <64 x i8> %load.a
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -3969,12 +3969,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp sgt <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.b, <64 x i8> %load.a
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -3995,12 +3995,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp sge <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.b, <64 x i8> %load.a
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -4021,12 +4021,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp ult <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.b, <64 x i8> %load.a
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -4047,12 +4047,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp ule <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.b, <64 x i8> %load.a
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -4073,12 +4073,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp ugt <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.b, <64 x i8> %load.a
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -4099,12 +4099,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i8* %a, i64 %index
-  %gep.b = getelementptr inbounds i8* %b, i64 %index
+  %gep.a = getelementptr inbounds i8, i8* %a, i64 %index
+  %gep.b = getelementptr inbounds i8, i8* %b, i64 %index
   %ptr.a = bitcast i8* %gep.a to <64 x i8>*
   %ptr.b = bitcast i8* %gep.b to <64 x i8>*
-  %load.a = load <64 x i8>* %ptr.a, align 2
-  %load.b = load <64 x i8>* %ptr.b, align 2
+  %load.a = load <64 x i8>, <64 x i8>* %ptr.a, align 2
+  %load.b = load <64 x i8>, <64 x i8>* %ptr.b, align 2
   %cmp = icmp uge <64 x i8> %load.a, %load.b
   %sel = select <64 x i1> %cmp, <64 x i8> %load.b, <64 x i8> %load.a
   store <64 x i8> %sel, <64 x i8>* %ptr.a, align 2
@@ -4125,12 +4125,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp slt <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.b, <32 x i16> %load.a
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -4151,12 +4151,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp sle <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.b, <32 x i16> %load.a
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -4177,12 +4177,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp sgt <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.b, <32 x i16> %load.a
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -4203,12 +4203,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp sge <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.b, <32 x i16> %load.a
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -4229,12 +4229,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp ult <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.b, <32 x i16> %load.a
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -4255,12 +4255,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp ule <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.b, <32 x i16> %load.a
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -4281,12 +4281,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp ugt <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.b, <32 x i16> %load.a
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -4307,12 +4307,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i16* %a, i64 %index
-  %gep.b = getelementptr inbounds i16* %b, i64 %index
+  %gep.a = getelementptr inbounds i16, i16* %a, i64 %index
+  %gep.b = getelementptr inbounds i16, i16* %b, i64 %index
   %ptr.a = bitcast i16* %gep.a to <32 x i16>*
   %ptr.b = bitcast i16* %gep.b to <32 x i16>*
-  %load.a = load <32 x i16>* %ptr.a, align 2
-  %load.b = load <32 x i16>* %ptr.b, align 2
+  %load.a = load <32 x i16>, <32 x i16>* %ptr.a, align 2
+  %load.b = load <32 x i16>, <32 x i16>* %ptr.b, align 2
   %cmp = icmp uge <32 x i16> %load.a, %load.b
   %sel = select <32 x i1> %cmp, <32 x i16> %load.b, <32 x i16> %load.a
   store <32 x i16> %sel, <32 x i16>* %ptr.a, align 2
@@ -4333,12 +4333,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp slt <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.b, <16 x i32> %load.a
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -4359,12 +4359,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp sle <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.b, <16 x i32> %load.a
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -4385,12 +4385,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp sgt <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.b, <16 x i32> %load.a
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -4411,12 +4411,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp sge <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.b, <16 x i32> %load.a
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -4437,12 +4437,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp ult <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.b, <16 x i32> %load.a
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -4463,12 +4463,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp ule <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.b, <16 x i32> %load.a
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -4489,12 +4489,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp ugt <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.b, <16 x i32> %load.a
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -4515,12 +4515,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <16 x i32>*
   %ptr.b = bitcast i32* %gep.b to <16 x i32>*
-  %load.a = load <16 x i32>* %ptr.a, align 2
-  %load.b = load <16 x i32>* %ptr.b, align 2
+  %load.a = load <16 x i32>, <16 x i32>* %ptr.a, align 2
+  %load.b = load <16 x i32>, <16 x i32>* %ptr.b, align 2
   %cmp = icmp uge <16 x i32> %load.a, %load.b
   %sel = select <16 x i1> %cmp, <16 x i32> %load.b, <16 x i32> %load.a
   store <16 x i32> %sel, <16 x i32>* %ptr.a, align 2
@@ -4543,12 +4543,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp slt <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.b, <8 x i64> %load.a
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -4569,12 +4569,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp sle <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.b, <8 x i64> %load.a
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -4595,12 +4595,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp sgt <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.b, <8 x i64> %load.a
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -4621,12 +4621,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp sge <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.b, <8 x i64> %load.a
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -4647,12 +4647,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp ult <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.b, <8 x i64> %load.a
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -4673,12 +4673,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp ule <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.b, <8 x i64> %load.a
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -4699,12 +4699,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp ugt <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.b, <8 x i64> %load.a
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -4725,12 +4725,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <8 x i64>*
   %ptr.b = bitcast i32* %gep.b to <8 x i64>*
-  %load.a = load <8 x i64>* %ptr.a, align 2
-  %load.b = load <8 x i64>* %ptr.b, align 2
+  %load.a = load <8 x i64>, <8 x i64>* %ptr.a, align 2
+  %load.b = load <8 x i64>, <8 x i64>* %ptr.b, align 2
   %cmp = icmp uge <8 x i64> %load.a, %load.b
   %sel = select <8 x i1> %cmp, <8 x i64> %load.b, <8 x i64> %load.a
   store <8 x i64> %sel, <8 x i64>* %ptr.a, align 2
@@ -4751,12 +4751,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp slt <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.a, <4 x i64> %load.b
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -4777,12 +4777,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp sle <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.a, <4 x i64> %load.b
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -4803,12 +4803,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp sgt <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.a, <4 x i64> %load.b
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -4829,12 +4829,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp sge <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.a, <4 x i64> %load.b
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -4855,12 +4855,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp ult <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.a, <4 x i64> %load.b
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -4881,12 +4881,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp ule <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.a, <4 x i64> %load.b
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -4907,12 +4907,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp ugt <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.a, <4 x i64> %load.b
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -4933,12 +4933,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp uge <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.a, <4 x i64> %load.b
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -4959,12 +4959,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp slt <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.b, <4 x i64> %load.a
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -4985,12 +4985,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp sle <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.b, <4 x i64> %load.a
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -5011,12 +5011,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp sgt <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.b, <4 x i64> %load.a
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -5037,12 +5037,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp sge <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.b, <4 x i64> %load.a
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -5063,12 +5063,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp ult <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.b, <4 x i64> %load.a
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -5089,12 +5089,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp ule <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.b, <4 x i64> %load.a
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -5115,12 +5115,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp ugt <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.b, <4 x i64> %load.a
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -5141,12 +5141,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <4 x i64>*
   %ptr.b = bitcast i32* %gep.b to <4 x i64>*
-  %load.a = load <4 x i64>* %ptr.a, align 2
-  %load.b = load <4 x i64>* %ptr.b, align 2
+  %load.a = load <4 x i64>, <4 x i64>* %ptr.a, align 2
+  %load.b = load <4 x i64>, <4 x i64>* %ptr.b, align 2
   %cmp = icmp uge <4 x i64> %load.a, %load.b
   %sel = select <4 x i1> %cmp, <4 x i64> %load.b, <4 x i64> %load.a
   store <4 x i64> %sel, <4 x i64>* %ptr.a, align 2
@@ -5167,12 +5167,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp slt <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.a, <2 x i64> %load.b
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
@@ -5193,12 +5193,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp sle <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.a, <2 x i64> %load.b
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
@@ -5219,12 +5219,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp sgt <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.a, <2 x i64> %load.b
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
@@ -5245,12 +5245,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp sge <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.a, <2 x i64> %load.b
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
@@ -5271,12 +5271,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp ult <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.a, <2 x i64> %load.b
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
@@ -5297,12 +5297,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp ule <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.a, <2 x i64> %load.b
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
@@ -5323,12 +5323,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp ugt <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.a, <2 x i64> %load.b
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
@@ -5349,12 +5349,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp uge <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.a, <2 x i64> %load.b
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
@@ -5375,12 +5375,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp slt <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.b, <2 x i64> %load.a
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
@@ -5401,12 +5401,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp sle <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.b, <2 x i64> %load.a
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
@@ -5427,12 +5427,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp sgt <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.b, <2 x i64> %load.a
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
@@ -5453,12 +5453,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp sge <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.b, <2 x i64> %load.a
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
@@ -5479,12 +5479,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp ult <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.b, <2 x i64> %load.a
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
@@ -5505,12 +5505,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp ule <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.b, <2 x i64> %load.a
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
@@ -5531,12 +5531,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp ugt <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.b, <2 x i64> %load.a
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
@@ -5557,12 +5557,12 @@ vector.ph:
 
 vector.body:                                      ; preds = %vector.body, %vector.ph
   %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
-  %gep.a = getelementptr inbounds i32* %a, i64 %index
-  %gep.b = getelementptr inbounds i32* %b, i64 %index
+  %gep.a = getelementptr inbounds i32, i32* %a, i64 %index
+  %gep.b = getelementptr inbounds i32, i32* %b, i64 %index
   %ptr.a = bitcast i32* %gep.a to <2 x i64>*
   %ptr.b = bitcast i32* %gep.b to <2 x i64>*
-  %load.a = load <2 x i64>* %ptr.a, align 2
-  %load.b = load <2 x i64>* %ptr.b, align 2
+  %load.a = load <2 x i64>, <2 x i64>* %ptr.a, align 2
+  %load.b = load <2 x i64>, <2 x i64>* %ptr.b, align 2
   %cmp = icmp uge <2 x i64> %load.a, %load.b
   %sel = select <2 x i1> %cmp, <2 x i64> %load.b, <2 x i64> %load.a
   store <2 x i64> %sel, <2 x i64>* %ptr.a, align 2
diff --git a/test/CodeGen/X86/vselect.ll b/test/CodeGen/X86/vselect.ll
index 3bd1dc4cb972..8c8092888834 100644
--- a/test/CodeGen/X86/vselect.ll
+++ b/test/CodeGen/X86/vselect.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=corei7 -mattr=-sse4.1 < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2,-sse4.1 < %s | FileCheck %s
 
 ; Verify that we don't emit packed vector shifts instructions if the
 ; condition used by the vector select is a vector of constants.
@@ -6,9 +6,8 @@
 define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: test1:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    andps {{.*}}(%rip), %xmm1
-; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
-; CHECK-NEXT:    orps %xmm1, %xmm0
+; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
+; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
 ; CHECK-NEXT:    retq
   %1 = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %a, <4 x float> %b
   ret <4 x float> %1
@@ -17,8 +16,8 @@ define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
 define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: test2:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movsd %xmm0, %xmm1
-; CHECK-NEXT:    movaps %xmm1, %xmm0
+; CHECK-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; CHECK-NEXT:    movapd %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %1 = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
   ret <4 x float> %1
@@ -27,7 +26,7 @@ define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
 define <4 x float> @test3(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: test3:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movsd %xmm1, %xmm0
+; CHECK-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; CHECK-NEXT:    retq
   %1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
   ret <4 x float> %1
@@ -53,10 +52,6 @@ define <4 x float> @test5(<4 x float> %a, <4 x float> %b) {
 define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test6:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movaps {{.*#+}} xmm1 = [0,65535,0,65535,0,65535,0,65535]
-; CHECK-NEXT:    andps %xmm0, %xmm1
-; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
-; CHECK-NEXT:    orps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %1 = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <8 x i16> %a, <8 x i16> %a
   ret <8 x i16> %1
@@ -65,9 +60,8 @@ define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
 define <8 x i16> @test7(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test7:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    andps {{.*}}(%rip), %xmm1
-; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
-; CHECK-NEXT:    orps %xmm1, %xmm0
+; CHECK-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; CHECK-NEXT:    movapd %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
   ret <8 x i16> %1
@@ -76,9 +70,7 @@ define <8 x i16> @test7(<8 x i16> %a, <8 x i16> %b) {
 define <8 x i16> @test8(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test8:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    andps {{.*}}(%rip), %xmm1
-; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
-; CHECK-NEXT:    orps %xmm1, %xmm0
+; CHECK-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; CHECK-NEXT:    retq
   %1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
   ret <8 x i16> %1
@@ -104,7 +96,7 @@ define <8 x i16> @test10(<8 x i16> %a, <8 x i16> %b) {
 define <8 x i16> @test11(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test11:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movaps {{.*#+}} xmm2 = <0,65535,65535,0,u,65535,65535,u>
+; CHECK-NEXT:    movaps {{.*#+}} xmm2 = [0,65535,65535,0,65535,65535,65535,65535]
 ; CHECK-NEXT:    andps %xmm2, %xmm0
 ; CHECK-NEXT:    andnps %xmm1, %xmm2
 ; CHECK-NEXT:    orps %xmm2, %xmm0
@@ -170,7 +162,7 @@ define <8 x i16> @test17(<8 x i16> %a, <8 x i16> %b) {
 define <4 x float> @test18(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: test18:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movss %xmm1, %xmm0
+; CHECK-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
 ; CHECK-NEXT:    retq
   %1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
   ret <4 x float> %1
@@ -179,7 +171,7 @@ define <4 x float> @test18(<4 x float> %a, <4 x float> %b) {
 define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test19:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movss %xmm1, %xmm0
+; CHECK-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
 ; CHECK-NEXT:    retq
   %1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x i32> %a, <4 x i32> %b
   ret <4 x i32> %1
@@ -188,7 +180,7 @@ define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
 define <2 x double> @test20(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: test20:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movsd %xmm1, %xmm0
+; CHECK-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; CHECK-NEXT:    retq
   %1 = select <2 x i1> <i1 false, i1 true>, <2 x double> %a, <2 x double> %b
   ret <2 x double> %1
@@ -197,7 +189,7 @@ define <2 x double> @test20(<2 x double> %a, <2 x double> %b) {
 define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test21:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movsd %xmm1, %xmm0
+; CHECK-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; CHECK-NEXT:    retq
   %1 = select <2 x i1> <i1 false, i1 true>, <2 x i64> %a, <2 x i64> %b
   ret <2 x i64> %1
@@ -206,7 +198,7 @@ define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
 define <4 x float> @test22(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: test22:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movss %xmm0, %xmm1
+; CHECK-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; CHECK-NEXT:    movaps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
@@ -216,7 +208,7 @@ define <4 x float> @test22(<4 x float> %a, <4 x float> %b) {
 define <4 x i32> @test23(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test23:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movss %xmm0, %xmm1
+; CHECK-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
 ; CHECK-NEXT:    movaps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %a, <4 x i32> %b
@@ -226,8 +218,8 @@ define <4 x i32> @test23(<4 x i32> %a, <4 x i32> %b) {
 define <2 x double> @test24(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: test24:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movsd %xmm0, %xmm1
-; CHECK-NEXT:    movaps %xmm1, %xmm0
+; CHECK-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; CHECK-NEXT:    movapd %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %1 = select <2 x i1> <i1 true, i1 false>, <2 x double> %a, <2 x double> %b
   ret <2 x double> %1
@@ -236,8 +228,8 @@ define <2 x double> @test24(<2 x double> %a, <2 x double> %b) {
 define <2 x i64> @test25(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test25:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movsd %xmm0, %xmm1
-; CHECK-NEXT:    movaps %xmm1, %xmm0
+; CHECK-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; CHECK-NEXT:    movapd %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %1 = select <2 x i1> <i1 true, i1 false>, <2 x i64> %a, <2 x i64> %b
   ret <2 x i64> %1
@@ -276,6 +268,7 @@ define <16 x double> @select_illegal(<16 x double> %a, <16 x double> %b) {
 ; CHECK-NEXT:    movaps %xmm2, 32(%rdi)
 ; CHECK-NEXT:    movaps %xmm1, 16(%rdi)
 ; CHECK-NEXT:    movaps %xmm0, (%rdi)
+; CHECK-NEXT:    movq %rdi, %rax
 ; CHECK-NEXT:    retq
   %sel = select <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x double> %a, <16 x double> %b
   ret <16 x double> %sel
diff --git a/test/CodeGen/X86/vshift-4.ll b/test/CodeGen/X86/vshift-4.ll
index cda9bc893a2d..4ab5db889820 100644
--- a/test/CodeGen/X86/vshift-4.ll
+++ b/test/CodeGen/X86/vshift-4.ll
@@ -13,11 +13,16 @@ entry:
   ret void
 }
 
-; shift1b can't use a packed shift
+; shift1b can't use a packed shift but can shift lanes separately and shuffle back together
 define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
 entry:
 ; CHECK-LABEL: shift1b:
-; CHECK: shll
+; CHECK:       pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
+; CHECK-NEXT:  movdqa %xmm0, %xmm3
+; CHECK-NEXT:  psllq  %xmm2, %xmm3
+; CHECK-NEXT:  movq   {{.*#+}} xmm1 = xmm1[0],zero
+; CHECK-NEXT:  psllq  %xmm1, %xmm0
+; CHECK-NEXT:  movsd  {{.*#+}} xmm3 = xmm0[0],xmm3[1]
   %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1>
   %shl = shl <2 x i64> %val, %shamt
   store <2 x i64> %shl, <2 x i64>* %dst
diff --git a/test/CodeGen/X86/vshift-5.ll b/test/CodeGen/X86/vshift-5.ll
index 562e520c5528..a6ae8d54bef1 100644
--- a/test/CodeGen/X86/vshift-5.ll
+++ b/test/CodeGen/X86/vshift-5.ll
@@ -7,7 +7,7 @@ entry:
 ; CHECK-LABEL: shift5a:
 ; CHECK: movd
 ; CHECK: pslld
-  %amt = load i32* %pamt 
+  %amt = load i32, i32* %pamt 
   %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
   %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer 
   %shl = shl <4 x i32> %val, %shamt
@@ -21,7 +21,7 @@ entry:
 ; CHECK-LABEL: shift5b:
 ; CHECK: movd
 ; CHECK: psrad
-  %amt = load i32* %pamt 
+  %amt = load i32, i32* %pamt 
   %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
   %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer 
   %shr = ashr <4 x i32> %val, %shamt
diff --git a/test/CodeGen/X86/vshift-6.ll b/test/CodeGen/X86/vshift-6.ll
index f50d9a6bb124..551a13850039 100644
--- a/test/CodeGen/X86/vshift-6.ll
+++ b/test/CodeGen/X86/vshift-6.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mcpu=corei7 -march=x86-64 -mattr=+sse2  | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mattr=+sse2  | FileCheck %s
 
 ; This test makes sure that the compiler does not crash with an
 ; assertion failure when trying to fold a vector shift left
@@ -25,7 +25,7 @@
 define <16 x i8> @do_not_crash(i8*, i32*, i64*, i32, i64, i8) {
 entry:
   store i8 %5, i8* %0
-  %L5 = load i8* %0
+  %L5 = load i8, i8* %0
   %I8 = insertelement <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, i8 %L5, i32 7
   %B51 = shl <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, %I8
   ret <16 x i8> %B51
diff --git a/test/CodeGen/X86/warn-stack.ll b/test/CodeGen/X86/warn-stack.ll
index a76fd2801a1f..aa09ad8066fe 100644
--- a/test/CodeGen/X86/warn-stack.ll
+++ b/test/CodeGen/X86/warn-stack.ll
@@ -7,7 +7,7 @@
 define void @nowarn() nounwind ssp {
 entry:
   %buffer = alloca [12 x i8], align 1
-  %arraydecay = getelementptr inbounds [12 x i8]* %buffer, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [12 x i8], [12 x i8]* %buffer, i64 0, i64 0
   call void @doit(i8* %arraydecay) nounwind
   ret void
 }
@@ -16,7 +16,7 @@ entry:
 define void @warn() nounwind ssp {
 entry:
   %buffer = alloca [80 x i8], align 1
-  %arraydecay = getelementptr inbounds [80 x i8]* %buffer, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [80 x i8], [80 x i8]* %buffer, i64 0, i64 0
   call void @doit(i8* %arraydecay) nounwind
   ret void
 }
diff --git a/test/CodeGen/X86/weak_def_can_be_hidden.ll b/test/CodeGen/X86/weak_def_can_be_hidden.ll
index b17f372afed8..8e6d34c89d88 100644
--- a/test/CodeGen/X86/weak_def_can_be_hidden.ll
+++ b/test/CodeGen/X86/weak_def_can_be_hidden.ll
@@ -12,7 +12,7 @@
 ; CHECK-D89: .weak_definition _v1
 
 define i32 @f1() {
-  %x = load i32 * @v1
+  %x = load i32 , i32 * @v1
   ret i32 %x
 }
 
@@ -46,6 +46,6 @@ define i32* @f3() {
 ; CHECK-D89: .weak_definition _v4
 
 define i32 @f4() {
-  %x = load i32 * @v4
+  %x = load i32 , i32 * @v4
   ret i32 %x
 }
diff --git a/test/CodeGen/X86/widen_arith-1.ll b/test/CodeGen/X86/widen_arith-1.ll
index 6041356e6ac7..5663b8b40946 100644
--- a/test/CodeGen/X86/widen_arith-1.ll
+++ b/test/CodeGen/X86/widen_arith-1.ll
@@ -16,25 +16,25 @@ entry:
 	br label %forcond
 
 forcond:		; preds = %forinc, %entry
-	%tmp = load i32* %i		; <i32> [#uses=1]
-	%tmp1 = load i32* %n.addr		; <i32> [#uses=1]
+	%tmp = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* %n.addr		; <i32> [#uses=1]
 	%cmp = icmp slt i32 %tmp, %tmp1		; <i1> [#uses=1]
 	br i1 %cmp, label %forbody, label %afterfor
 
 forbody:		; preds = %forcond
-	%tmp2 = load i32* %i		; <i32> [#uses=1]
-	%tmp3 = load <3 x i8>** %dst.addr		; <<3 x i8>*> [#uses=1]
-	%arrayidx = getelementptr <3 x i8>* %tmp3, i32 %tmp2		; <<3 x i8>*> [#uses=1]
-	%tmp4 = load i32* %i		; <i32> [#uses=1]
-	%tmp5 = load <3 x i8>** %src.addr		; <<3 x i8>*> [#uses=1]
-	%arrayidx6 = getelementptr <3 x i8>* %tmp5, i32 %tmp4		; <<3 x i8>*> [#uses=1]
-	%tmp7 = load <3 x i8>* %arrayidx6		; <<3 x i8>> [#uses=1]
+	%tmp2 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp3 = load <3 x i8>*, <3 x i8>** %dst.addr		; <<3 x i8>*> [#uses=1]
+	%arrayidx = getelementptr <3 x i8>, <3 x i8>* %tmp3, i32 %tmp2		; <<3 x i8>*> [#uses=1]
+	%tmp4 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp5 = load <3 x i8>*, <3 x i8>** %src.addr		; <<3 x i8>*> [#uses=1]
+	%arrayidx6 = getelementptr <3 x i8>, <3 x i8>* %tmp5, i32 %tmp4		; <<3 x i8>*> [#uses=1]
+	%tmp7 = load <3 x i8>, <3 x i8>* %arrayidx6		; <<3 x i8>> [#uses=1]
 	%add = add <3 x i8> %tmp7, < i8 1, i8 1, i8 1 >		; <<3 x i8>> [#uses=1]
 	store <3 x i8> %add, <3 x i8>* %arrayidx
 	br label %forinc
 
 forinc:		; preds = %forbody
-	%tmp8 = load i32* %i		; <i32> [#uses=1]
+	%tmp8 = load i32, i32* %i		; <i32> [#uses=1]
 	%inc = add i32 %tmp8, 1		; <i32> [#uses=1]
 	store i32 %inc, i32* %i
 	br label %forcond
diff --git a/test/CodeGen/X86/widen_arith-2.ll b/test/CodeGen/X86/widen_arith-2.ll
index 1b81e9f889aa..6c219c1720ef 100644
--- a/test/CodeGen/X86/widen_arith-2.ll
+++ b/test/CodeGen/X86/widen_arith-2.ll
@@ -19,36 +19,36 @@ entry:
 	br label %forcond
 
 forcond:		; preds = %forinc, %entry
-	%tmp = load i32* %i		; <i32> [#uses=1]
-	%tmp1 = load i32* %n.addr		; <i32> [#uses=1]
+	%tmp = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* %n.addr		; <i32> [#uses=1]
 	%cmp = icmp slt i32 %tmp, %tmp1		; <i1> [#uses=1]
 	br i1 %cmp, label %forbody, label %afterfor
 
 forbody:		; preds = %forcond
-	%tmp2 = load i32* %i		; <i32> [#uses=1]
-	%tmp3 = load i64** %dst_i.addr		; <i64*> [#uses=1]
-	%arrayidx = getelementptr i64* %tmp3, i32 %tmp2		; <i64*> [#uses=1]
+	%tmp2 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp3 = load i64*, i64** %dst_i.addr		; <i64*> [#uses=1]
+	%arrayidx = getelementptr i64, i64* %tmp3, i32 %tmp2		; <i64*> [#uses=1]
 	%conv = bitcast i64* %arrayidx to <8 x i8>*		; <<8 x i8>*> [#uses=1]
 	store <8 x i8>* %conv, <8 x i8>** %dst
-	%tmp4 = load i32* %i		; <i32> [#uses=1]
-	%tmp5 = load i64** %src_i.addr		; <i64*> [#uses=1]
-	%arrayidx6 = getelementptr i64* %tmp5, i32 %tmp4		; <i64*> [#uses=1]
+	%tmp4 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp5 = load i64*, i64** %src_i.addr		; <i64*> [#uses=1]
+	%arrayidx6 = getelementptr i64, i64* %tmp5, i32 %tmp4		; <i64*> [#uses=1]
 	%conv7 = bitcast i64* %arrayidx6 to <8 x i8>*		; <<8 x i8>*> [#uses=1]
 	store <8 x i8>* %conv7, <8 x i8>** %src
-	%tmp8 = load i32* %i		; <i32> [#uses=1]
-	%tmp9 = load <8 x i8>** %dst		; <<8 x i8>*> [#uses=1]
-	%arrayidx10 = getelementptr <8 x i8>* %tmp9, i32 %tmp8		; <<8 x i8>*> [#uses=1]
-	%tmp11 = load i32* %i		; <i32> [#uses=1]
-	%tmp12 = load <8 x i8>** %src		; <<8 x i8>*> [#uses=1]
-	%arrayidx13 = getelementptr <8 x i8>* %tmp12, i32 %tmp11		; <<8 x i8>*> [#uses=1]
-	%tmp14 = load <8 x i8>* %arrayidx13		; <<8 x i8>> [#uses=1]
+	%tmp8 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp9 = load <8 x i8>*, <8 x i8>** %dst		; <<8 x i8>*> [#uses=1]
+	%arrayidx10 = getelementptr <8 x i8>, <8 x i8>* %tmp9, i32 %tmp8		; <<8 x i8>*> [#uses=1]
+	%tmp11 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp12 = load <8 x i8>*, <8 x i8>** %src		; <<8 x i8>*> [#uses=1]
+	%arrayidx13 = getelementptr <8 x i8>, <8 x i8>* %tmp12, i32 %tmp11		; <<8 x i8>*> [#uses=1]
+	%tmp14 = load <8 x i8>, <8 x i8>* %arrayidx13		; <<8 x i8>> [#uses=1]
 	%add = add <8 x i8> %tmp14, < i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1 >		; <<8 x i8>> [#uses=1]
 	%and = and <8 x i8> %add, < i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4 >		; <<8 x i8>> [#uses=1]
 	store <8 x i8> %and, <8 x i8>* %arrayidx10
 	br label %forinc
 
 forinc:		; preds = %forbody
-	%tmp15 = load i32* %i		; <i32> [#uses=1]
+	%tmp15 = load i32, i32* %i		; <i32> [#uses=1]
 	%inc = add i32 %tmp15, 1		; <i32> [#uses=1]
 	store i32 %inc, i32* %i
 	br label %forcond
diff --git a/test/CodeGen/X86/widen_arith-3.ll b/test/CodeGen/X86/widen_arith-3.ll
index d2b8e6ee9a75..aea7975a045c 100644
--- a/test/CodeGen/X86/widen_arith-3.ll
+++ b/test/CodeGen/X86/widen_arith-3.ll
@@ -21,25 +21,25 @@ entry:
 	br label %forcond
 
 forcond:		; preds = %forinc, %entry
-	%tmp = load i32* %i		; <i32> [#uses=1]
-	%tmp1 = load i32* %n.addr		; <i32> [#uses=1]
+	%tmp = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* %n.addr		; <i32> [#uses=1]
 	%cmp = icmp slt i32 %tmp, %tmp1		; <i1> [#uses=1]
 	br i1 %cmp, label %forbody, label %afterfor
 
 forbody:		; preds = %forcond
-	%tmp2 = load i32* %i		; <i32> [#uses=1]
-	%tmp3 = load <3 x i16>** %dst.addr		; <<3 x i16>*> [#uses=1]
-	%arrayidx = getelementptr <3 x i16>* %tmp3, i32 %tmp2		; <<3 x i16>*> [#uses=1]
-	%tmp4 = load i32* %i		; <i32> [#uses=1]
-	%tmp5 = load <3 x i16>** %src.addr		; <<3 x i16>*> [#uses=1]
-	%arrayidx6 = getelementptr <3 x i16>* %tmp5, i32 %tmp4		; <<3 x i16>*> [#uses=1]
-	%tmp7 = load <3 x i16>* %arrayidx6		; <<3 x i16>> [#uses=1]
+	%tmp2 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp3 = load <3 x i16>*, <3 x i16>** %dst.addr		; <<3 x i16>*> [#uses=1]
+	%arrayidx = getelementptr <3 x i16>, <3 x i16>* %tmp3, i32 %tmp2		; <<3 x i16>*> [#uses=1]
+	%tmp4 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp5 = load <3 x i16>*, <3 x i16>** %src.addr		; <<3 x i16>*> [#uses=1]
+	%arrayidx6 = getelementptr <3 x i16>, <3 x i16>* %tmp5, i32 %tmp4		; <<3 x i16>*> [#uses=1]
+	%tmp7 = load <3 x i16>, <3 x i16>* %arrayidx6		; <<3 x i16>> [#uses=1]
 	%add = add <3 x i16> %tmp7, < i16 1, i16 1, i16 1 >		; <<3 x i16>> [#uses=1]
 	store <3 x i16> %add, <3 x i16>* %arrayidx
 	br label %forinc
 
 forinc:		; preds = %forbody
-	%tmp8 = load i32* %i		; <i32> [#uses=1]
+	%tmp8 = load i32, i32* %i		; <i32> [#uses=1]
 	%inc = add i32 %tmp8, 1		; <i32> [#uses=1]
 	store i32 %inc, i32* %i
 	br label %forcond
diff --git a/test/CodeGen/X86/widen_arith-4.ll b/test/CodeGen/X86/widen_arith-4.ll
index 5207e1fa9d7b..5dba063d8af4 100644
--- a/test/CodeGen/X86/widen_arith-4.ll
+++ b/test/CodeGen/X86/widen_arith-4.ll
@@ -19,26 +19,26 @@ entry:
 	br label %forcond
 
 forcond:		; preds = %forinc, %entry
-	%tmp = load i32* %i		; <i32> [#uses=1]
-	%tmp1 = load i32* %n.addr		; <i32> [#uses=1]
+	%tmp = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* %n.addr		; <i32> [#uses=1]
 	%cmp = icmp slt i32 %tmp, %tmp1		; <i1> [#uses=1]
 	br i1 %cmp, label %forbody, label %afterfor
 
 forbody:		; preds = %forcond
-	%tmp2 = load i32* %i		; <i32> [#uses=1]
-	%tmp3 = load <5 x i16>** %dst.addr		; <<5 x i16>*> [#uses=1]
-	%arrayidx = getelementptr <5 x i16>* %tmp3, i32 %tmp2		; <<5 x i16>*> [#uses=1]
-	%tmp4 = load i32* %i		; <i32> [#uses=1]
-	%tmp5 = load <5 x i16>** %src.addr		; <<5 x i16>*> [#uses=1]
-	%arrayidx6 = getelementptr <5 x i16>* %tmp5, i32 %tmp4		; <<5 x i16>*> [#uses=1]
-	%tmp7 = load <5 x i16>* %arrayidx6		; <<5 x i16>> [#uses=1]
+	%tmp2 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp3 = load <5 x i16>*, <5 x i16>** %dst.addr		; <<5 x i16>*> [#uses=1]
+	%arrayidx = getelementptr <5 x i16>, <5 x i16>* %tmp3, i32 %tmp2		; <<5 x i16>*> [#uses=1]
+	%tmp4 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp5 = load <5 x i16>*, <5 x i16>** %src.addr		; <<5 x i16>*> [#uses=1]
+	%arrayidx6 = getelementptr <5 x i16>, <5 x i16>* %tmp5, i32 %tmp4		; <<5 x i16>*> [#uses=1]
+	%tmp7 = load <5 x i16>, <5 x i16>* %arrayidx6		; <<5 x i16>> [#uses=1]
 	%sub = sub <5 x i16> %tmp7, < i16 271, i16 271, i16 271, i16 271, i16 271 >		; <<5 x i16>> [#uses=1]
 	%mul = mul <5 x i16> %sub, < i16 2, i16 4, i16 2, i16 2, i16 2 >		; <<5 x i16>> [#uses=1]
 	store <5 x i16> %mul, <5 x i16>* %arrayidx
 	br label %forinc
 
 forinc:		; preds = %forbody
-	%tmp8 = load i32* %i		; <i32> [#uses=1]
+	%tmp8 = load i32, i32* %i		; <i32> [#uses=1]
 	%inc = add i32 %tmp8, 1		; <i32> [#uses=1]
 	store i32 %inc, i32* %i
 	br label %forcond
diff --git a/test/CodeGen/X86/widen_arith-5.ll b/test/CodeGen/X86/widen_arith-5.ll
index 70b6a8a239ab..04c9ec2def2a 100644
--- a/test/CodeGen/X86/widen_arith-5.ll
+++ b/test/CodeGen/X86/widen_arith-5.ll
@@ -20,26 +20,26 @@ entry:
 	br label %forcond
 
 forcond:		; preds = %forinc, %entry
-	%tmp = load i32* %i		; <i32> [#uses=1]
-	%tmp1 = load i32* %n.addr		; <i32> [#uses=1]
+	%tmp = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* %n.addr		; <i32> [#uses=1]
 	%cmp = icmp slt i32 %tmp, %tmp1		; <i1> [#uses=1]
 	br i1 %cmp, label %forbody, label %afterfor
 
 forbody:		; preds = %forcond
-	%tmp2 = load i32* %i		; <i32> [#uses=1]
-	%tmp3 = load <3 x i32>** %dst.addr		; <<3 x i32>*> [#uses=1]
-	%arrayidx = getelementptr <3 x i32>* %tmp3, i32 %tmp2		; <<3 x i32>*> [#uses=1]
-	%tmp4 = load i32* %i		; <i32> [#uses=1]
-	%tmp5 = load <3 x i32>** %src.addr		; <<3 x i32>*> [#uses=1]
-	%arrayidx6 = getelementptr <3 x i32>* %tmp5, i32 %tmp4		; <<3 x i32>*> [#uses=1]
-	%tmp7 = load <3 x i32>* %arrayidx6		; <<3 x i32>> [#uses=1]
+	%tmp2 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp3 = load <3 x i32>*, <3 x i32>** %dst.addr		; <<3 x i32>*> [#uses=1]
+	%arrayidx = getelementptr <3 x i32>, <3 x i32>* %tmp3, i32 %tmp2		; <<3 x i32>*> [#uses=1]
+	%tmp4 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp5 = load <3 x i32>*, <3 x i32>** %src.addr		; <<3 x i32>*> [#uses=1]
+	%arrayidx6 = getelementptr <3 x i32>, <3 x i32>* %tmp5, i32 %tmp4		; <<3 x i32>*> [#uses=1]
+	%tmp7 = load <3 x i32>, <3 x i32>* %arrayidx6		; <<3 x i32>> [#uses=1]
 	%mul = mul <3 x i32> %tmp7, < i32 4, i32 4, i32 4 >		; <<3 x i32>> [#uses=1]
 	%sub = sub <3 x i32> %mul, < i32 3, i32 3, i32 3 >		; <<3 x i32>> [#uses=1]
 	store <3 x i32> %sub, <3 x i32>* %arrayidx
 	br label %forinc
 
 forinc:		; preds = %forbody
-	%tmp8 = load i32* %i		; <i32> [#uses=1]
+	%tmp8 = load i32, i32* %i		; <i32> [#uses=1]
 	%inc = add i32 %tmp8, 1		; <i32> [#uses=1]
 	store i32 %inc, i32* %i
 	br label %forcond
diff --git a/test/CodeGen/X86/widen_arith-6.ll b/test/CodeGen/X86/widen_arith-6.ll
index 329048ad77b7..09998a027d25 100644
--- a/test/CodeGen/X86/widen_arith-6.ll
+++ b/test/CodeGen/X86/widen_arith-6.ll
@@ -19,27 +19,27 @@ entry:
 	br label %forcond
 
 forcond:		; preds = %forinc, %entry
-	%tmp = load i32* %i		; <i32> [#uses=1]
-	%tmp1 = load i32* %n.addr		; <i32> [#uses=1]
+	%tmp = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* %n.addr		; <i32> [#uses=1]
 	%cmp = icmp slt i32 %tmp, %tmp1		; <i1> [#uses=1]
 	br i1 %cmp, label %forbody, label %afterfor
 
 forbody:		; preds = %forcond
-	%tmp2 = load i32* %i		; <i32> [#uses=1]
-	%tmp3 = load <3 x float>** %dst.addr		; <<3 x float>*> [#uses=1]
-	%arrayidx = getelementptr <3 x float>* %tmp3, i32 %tmp2		; <<3 x float>*> [#uses=1]
-	%tmp4 = load i32* %i		; <i32> [#uses=1]
-	%tmp5 = load <3 x float>** %src.addr		; <<3 x float>*> [#uses=1]
-	%arrayidx6 = getelementptr <3 x float>* %tmp5, i32 %tmp4		; <<3 x float>*> [#uses=1]
-	%tmp7 = load <3 x float>* %arrayidx6		; <<3 x float>> [#uses=1]
-	%tmp8 = load <3 x float>* %v		; <<3 x float>> [#uses=1]
+	%tmp2 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp3 = load <3 x float>*, <3 x float>** %dst.addr		; <<3 x float>*> [#uses=1]
+	%arrayidx = getelementptr <3 x float>, <3 x float>* %tmp3, i32 %tmp2		; <<3 x float>*> [#uses=1]
+	%tmp4 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp5 = load <3 x float>*, <3 x float>** %src.addr		; <<3 x float>*> [#uses=1]
+	%arrayidx6 = getelementptr <3 x float>, <3 x float>* %tmp5, i32 %tmp4		; <<3 x float>*> [#uses=1]
+	%tmp7 = load <3 x float>, <3 x float>* %arrayidx6		; <<3 x float>> [#uses=1]
+	%tmp8 = load <3 x float>, <3 x float>* %v		; <<3 x float>> [#uses=1]
 	%mul = fmul <3 x float> %tmp7, %tmp8		; <<3 x float>> [#uses=1]
 	%add = fadd <3 x float> %mul, < float 0x409EE02900000000, float 0x409EE02900000000, float 0x409EE02900000000 >		; <<3 x float>> [#uses=1]
 	store <3 x float> %add, <3 x float>* %arrayidx
 	br label %forinc
 
 forinc:		; preds = %forbody
-	%tmp9 = load i32* %i		; <i32> [#uses=1]
+	%tmp9 = load i32, i32* %i		; <i32> [#uses=1]
 	%inc = add i32 %tmp9, 1		; <i32> [#uses=1]
 	store i32 %inc, i32* %i
 	br label %forcond
diff --git a/test/CodeGen/X86/widen_cast-1.ll b/test/CodeGen/X86/widen_cast-1.ll
index e0b861f29de8..b0240ddb0433 100644
--- a/test/CodeGen/X86/widen_cast-1.ll
+++ b/test/CodeGen/X86/widen_cast-1.ll
@@ -3,12 +3,14 @@
 
 ; CHECK: movl
 ; CHECK: paddw
-; CHECK: movlpd
+; CHECK: movq
+
+; FIXME - if this test cares about scheduling, why isn't it being checked?
 
 ; Scheduler causes produce a different instruction order
 ; ATOM: movl
 ; ATOM: paddw
-; ATOM: movlpd
+; ATOM: movq
 
 ; bitcast a v4i16 to v2i32
 
@@ -23,25 +25,25 @@ entry:
 	br label %forcond
 
 forcond:		; preds = %forinc, %entry
-	%tmp = load i32* %i		; <i32> [#uses=1]
+	%tmp = load i32, i32* %i		; <i32> [#uses=1]
 	%cmp = icmp slt i32 %tmp, 4		; <i1> [#uses=1]
 	br i1 %cmp, label %forbody, label %afterfor
 
 forbody:		; preds = %forcond
-	%tmp1 = load i32* %i		; <i32> [#uses=1]
-	%tmp2 = load <2 x i32>** %dst.addr		; <<2 x i32>*> [#uses=1]
-	%arrayidx = getelementptr <2 x i32>* %tmp2, i32 %tmp1		; <<2 x i32>*> [#uses=1]
-	%tmp3 = load i32* %i		; <i32> [#uses=1]
-	%tmp4 = load <4 x i16>** %src.addr		; <<4 x i16>*> [#uses=1]
-	%arrayidx5 = getelementptr <4 x i16>* %tmp4, i32 %tmp3		; <<4 x i16>*> [#uses=1]
-	%tmp6 = load <4 x i16>* %arrayidx5		; <<4 x i16>> [#uses=1]
+	%tmp1 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp2 = load <2 x i32>*, <2 x i32>** %dst.addr		; <<2 x i32>*> [#uses=1]
+	%arrayidx = getelementptr <2 x i32>, <2 x i32>* %tmp2, i32 %tmp1		; <<2 x i32>*> [#uses=1]
+	%tmp3 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp4 = load <4 x i16>*, <4 x i16>** %src.addr		; <<4 x i16>*> [#uses=1]
+	%arrayidx5 = getelementptr <4 x i16>, <4 x i16>* %tmp4, i32 %tmp3		; <<4 x i16>*> [#uses=1]
+	%tmp6 = load <4 x i16>, <4 x i16>* %arrayidx5		; <<4 x i16>> [#uses=1]
 	%add = add <4 x i16> %tmp6, < i16 1, i16 1, i16 1, i16 1 >		; <<4 x i16>> [#uses=1]
 	%conv = bitcast <4 x i16> %add to <2 x i32>		; <<2 x i32>> [#uses=1]
 	store <2 x i32> %conv, <2 x i32>* %arrayidx
 	br label %forinc
 
 forinc:		; preds = %forbody
-	%tmp7 = load i32* %i		; <i32> [#uses=1]
+	%tmp7 = load i32, i32* %i		; <i32> [#uses=1]
 	%inc = add i32 %tmp7, 1		; <i32> [#uses=1]
 	store i32 %inc, i32* %i
 	br label %forcond
diff --git a/test/CodeGen/X86/widen_cast-2.ll b/test/CodeGen/X86/widen_cast-2.ll
index 40b42fbf1460..5a9acbd52f20 100644
--- a/test/CodeGen/X86/widen_cast-2.ll
+++ b/test/CodeGen/X86/widen_cast-2.ll
@@ -18,25 +18,25 @@ entry:
 	br label %forcond
 
 forcond:		; preds = %forinc, %entry
-	%tmp = load i32* %i		; <i32> [#uses=1]
+	%tmp = load i32, i32* %i		; <i32> [#uses=1]
 	%cmp = icmp slt i32 %tmp, 4		; <i1> [#uses=1]
 	br i1 %cmp, label %forbody, label %afterfor
 
 forbody:		; preds = %forcond
-	%tmp1 = load i32* %i		; <i32> [#uses=1]
-	%tmp2 = load <7 x i32>** %dst.addr		; <<2 x i32>*> [#uses=1]
-	%arrayidx = getelementptr <7 x i32>* %tmp2, i32 %tmp1		; <<7 x i32>*> [#uses=1]
-	%tmp3 = load i32* %i		; <i32> [#uses=1]
-	%tmp4 = load <14 x i16>** %src.addr		; <<4 x i16>*> [#uses=1]
-	%arrayidx5 = getelementptr <14 x i16>* %tmp4, i32 %tmp3		; <<4 x i16>*> [#uses=1]
-	%tmp6 = load <14 x i16>* %arrayidx5		; <<4 x i16>> [#uses=1]
+	%tmp1 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp2 = load <7 x i32>*, <7 x i32>** %dst.addr		; <<2 x i32>*> [#uses=1]
+	%arrayidx = getelementptr <7 x i32>, <7 x i32>* %tmp2, i32 %tmp1		; <<7 x i32>*> [#uses=1]
+	%tmp3 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp4 = load <14 x i16>*, <14 x i16>** %src.addr		; <<4 x i16>*> [#uses=1]
+	%arrayidx5 = getelementptr <14 x i16>, <14 x i16>* %tmp4, i32 %tmp3		; <<4 x i16>*> [#uses=1]
+	%tmp6 = load <14 x i16>, <14 x i16>* %arrayidx5		; <<4 x i16>> [#uses=1]
 	%add = add <14 x i16> %tmp6, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1 >		; <<4 x i16>> [#uses=1]
 	%conv = bitcast <14 x i16> %add to <7 x i32>		; <<7 x i32>> [#uses=1]
 	store <7 x i32> %conv, <7 x i32>* %arrayidx
 	br label %forinc
 
 forinc:		; preds = %forbody
-	%tmp7 = load i32* %i		; <i32> [#uses=1]
+	%tmp7 = load i32, i32* %i		; <i32> [#uses=1]
 	%inc = add i32 %tmp7, 1		; <i32> [#uses=1]
 	store i32 %inc, i32* %i
 	br label %forcond
diff --git a/test/CodeGen/X86/widen_cast-4.ll b/test/CodeGen/X86/widen_cast-4.ll
index 19b84f19a4ff..8ed2785ae73a 100644
--- a/test/CodeGen/X86/widen_cast-4.ll
+++ b/test/CodeGen/X86/widen_cast-4.ll
@@ -18,29 +18,29 @@ entry:
 	br label %forcond
 
 forcond:		; preds = %forinc, %entry
-	%tmp = load i32* %i		; <i32> [#uses=1]
-	%tmp1 = load i32* %n.addr		; <i32> [#uses=1]
+	%tmp = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* %n.addr		; <i32> [#uses=1]
 	%cmp = icmp slt i32 %tmp, %tmp1		; <i1> [#uses=1]
 	br i1 %cmp, label %forbody, label %afterfor
 
 forbody:		; preds = %forcond
-	%tmp2 = load i32* %i		; <i32> [#uses=1]
-	%tmp3 = load i64** %dst_i.addr		; <i64*> [#uses=1]
-	%arrayidx = getelementptr i64* %tmp3, i32 %tmp2		; <i64*> [#uses=1]
+	%tmp2 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp3 = load i64*, i64** %dst_i.addr		; <i64*> [#uses=1]
+	%arrayidx = getelementptr i64, i64* %tmp3, i32 %tmp2		; <i64*> [#uses=1]
 	%conv = bitcast i64* %arrayidx to <8 x i8>*		; <<8 x i8>*> [#uses=1]
 	store <8 x i8>* %conv, <8 x i8>** %dst
-	%tmp4 = load i32* %i		; <i32> [#uses=1]
-	%tmp5 = load i64** %src_i.addr		; <i64*> [#uses=1]
-	%arrayidx6 = getelementptr i64* %tmp5, i32 %tmp4		; <i64*> [#uses=1]
+	%tmp4 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp5 = load i64*, i64** %src_i.addr		; <i64*> [#uses=1]
+	%arrayidx6 = getelementptr i64, i64* %tmp5, i32 %tmp4		; <i64*> [#uses=1]
 	%conv7 = bitcast i64* %arrayidx6 to <8 x i8>*		; <<8 x i8>*> [#uses=1]
 	store <8 x i8>* %conv7, <8 x i8>** %src
-	%tmp8 = load i32* %i		; <i32> [#uses=1]
-	%tmp9 = load <8 x i8>** %dst		; <<8 x i8>*> [#uses=1]
-	%arrayidx10 = getelementptr <8 x i8>* %tmp9, i32 %tmp8		; <<8 x i8>*> [#uses=1]
-	%tmp11 = load i32* %i		; <i32> [#uses=1]
-	%tmp12 = load <8 x i8>** %src		; <<8 x i8>*> [#uses=1]
-	%arrayidx13 = getelementptr <8 x i8>* %tmp12, i32 %tmp11		; <<8 x i8>*> [#uses=1]
-	%tmp14 = load <8 x i8>* %arrayidx13		; <<8 x i8>> [#uses=1]
+	%tmp8 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp9 = load <8 x i8>*, <8 x i8>** %dst		; <<8 x i8>*> [#uses=1]
+	%arrayidx10 = getelementptr <8 x i8>, <8 x i8>* %tmp9, i32 %tmp8		; <<8 x i8>*> [#uses=1]
+	%tmp11 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp12 = load <8 x i8>*, <8 x i8>** %src		; <<8 x i8>*> [#uses=1]
+	%arrayidx13 = getelementptr <8 x i8>, <8 x i8>* %tmp12, i32 %tmp11		; <<8 x i8>*> [#uses=1]
+	%tmp14 = load <8 x i8>, <8 x i8>* %arrayidx13		; <<8 x i8>> [#uses=1]
 	%add = add <8 x i8> %tmp14, < i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1 >		; <<8 x i8>> [#uses=1]
 	%shr = ashr <8 x i8> %add, < i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2 >		; <<8 x i8>> [#uses=1]
 	store <8 x i8> %shr, <8 x i8>* %arrayidx10
@@ -52,7 +52,7 @@ forbody:		; preds = %forcond
 ; CHECK-NEXT: psraw $8
 ; CHECK-NEXT: psraw $2
 ; CHECK-NEXT: pshufb
-; CHECK-NEXT: movlpd
+; CHECK-NEXT: movq
 ;
 ; FIXME: We shouldn't require both a movd and an insert.
 ; CHECK-WIDE: %forbody
@@ -67,7 +67,7 @@ forbody:		; preds = %forcond
 ; CHECK-WIDE-NEXT: movd
 
 forinc:		; preds = %forbody
-	%tmp15 = load i32* %i		; <i32> [#uses=1]
+	%tmp15 = load i32, i32* %i		; <i32> [#uses=1]
 	%inc = add i32 %tmp15, 1		; <i32> [#uses=1]
 	store i32 %inc, i32* %i
 	br label %forcond
diff --git a/test/CodeGen/X86/widen_cast-5.ll b/test/CodeGen/X86/widen_cast-5.ll
index ccf0bd1d0b62..4e9d2dfdb5de 100644
--- a/test/CodeGen/X86/widen_cast-5.ll
+++ b/test/CodeGen/X86/widen_cast-5.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
 ; CHECK: movl
-; CHECK: movlpd
+; CHECK: movq
 
 ; bitcast a i64 to v2i32
 define void @convert(<2 x i32>* %dst.addr, i64 %src) nounwind {
diff --git a/test/CodeGen/X86/widen_conversions.ll b/test/CodeGen/X86/widen_conversions.ll
index 8e5174fbe76e..dd75097a2515 100644
--- a/test/CodeGen/X86/widen_conversions.ll
+++ b/test/CodeGen/X86/widen_conversions.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mcpu=x86-64 -x86-experimental-vector-widening-legalization -x86-experimental-vector-shuffle-lowering | FileCheck %s
+; RUN: llc < %s -mcpu=x86-64 -x86-experimental-vector-widening-legalization | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-unknown"
@@ -12,7 +12,7 @@ define <4 x i32> @zext_v4i8_to_v4i32(<4 x i8>* %ptr) {
 ; CHECK-NEXT: punpcklwd %[[Z]], %[[X]]
 ; CHECK-NEXT: ret
 
-  %val = load <4 x i8>* %ptr
+  %val = load <4 x i8>, <4 x i8>* %ptr
   %ext = zext <4 x i8> %val to <4 x i32>
   ret <4 x i32> %ext
 }
diff --git a/test/CodeGen/X86/widen_load-0.ll b/test/CodeGen/X86/widen_load-0.ll
index d5437281b274..edaaa77c1456 100644
--- a/test/CodeGen/X86/widen_load-0.ll
+++ b/test/CodeGen/X86/widen_load-0.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -o - -mtriple=x86_64-linux -mcpu=corei7 | FileCheck %s
+; RUN: llc < %s -o - -mtriple=x86_64-linux | FileCheck %s
 ; PR4891
 
 ; Both loads should happen before either store.
@@ -10,8 +10,8 @@
 
 define void @short2_int_swap(<2 x i16>* nocapture %b, i32* nocapture %c) nounwind {
 entry:
-  %0 = load <2 x i16>* %b, align 2                ; <<2 x i16>> [#uses=1]
-  %1 = load i32* %c, align 4                      ; <i32> [#uses=1]
+  %0 = load <2 x i16>, <2 x i16>* %b, align 2                ; <<2 x i16>> [#uses=1]
+  %1 = load i32, i32* %c, align 4                      ; <i32> [#uses=1]
   %tmp1 = bitcast i32 %1 to <2 x i16>             ; <<2 x i16>> [#uses=1]
   store <2 x i16> %tmp1, <2 x i16>* %b, align 2
   %tmp5 = bitcast <2 x i16> %0 to <1 x i32>       ; <<1 x i32>> [#uses=1]
diff --git a/test/CodeGen/X86/widen_load-1.ll b/test/CodeGen/X86/widen_load-1.ll
index c59cc58f40fd..c670b45df747 100644
--- a/test/CodeGen/X86/widen_load-1.ll
+++ b/test/CodeGen/X86/widen_load-1.ll
@@ -24,14 +24,14 @@ define void @reset(<2 x float>* noalias %garbage1) {
 
 "file complex.c, line 27, bb13":                  ; preds = %"file complex.c, line 27, bb1"
   store i32 0, i32* %changed, align 4
-  %r2 = getelementptr float* bitcast ([20 x i64]* @compl to float*), i64 32 ; <float*> [#uses=1]
+  %r2 = getelementptr float, float* bitcast ([20 x i64]* @compl to float*), i64 32 ; <float*> [#uses=1]
   %r3 = bitcast float* %r2 to <2 x float>*        ; <<2 x float>*> [#uses=1]
-  %r4 = load <2 x float>* %r3, align 4            ; <<2 x float>> [#uses=1]
+  %r4 = load <2 x float>, <2 x float>* %r3, align 4            ; <<2 x float>> [#uses=1]
   call void @killcommon(i32* %changed)
   br label %"file complex.c, line 34, bb4"
 
 "file complex.c, line 34, bb4":                   ; preds = %"file complex.c, line 27, bb13"
-  %r5 = load i32* %changed, align 4               ; <i32> [#uses=1]
+  %r5 = load i32, i32* %changed, align 4               ; <i32> [#uses=1]
   %r6 = icmp eq i32 %r5, 0                        ; <i1> [#uses=1]
   %r7 = zext i1 %r6 to i32                        ; <i32> [#uses=1]
   %r8 = icmp ne i32 %r7, 0                        ; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/widen_load-2.ll b/test/CodeGen/X86/widen_load-2.ll
index 0ec3574d69eb..f5ddc0eacc61 100644
--- a/test/CodeGen/X86/widen_load-2.ll
+++ b/test/CodeGen/X86/widen_load-2.ll
@@ -10,8 +10,8 @@ define void @add3i32(%i32vec3*  sret %ret, %i32vec3* %ap, %i32vec3* %bp)  {
 ; CHECK-NEXT:    paddd   (%{{.*}}), %[[R0]]
 ; CHECK-NEXT:    pextrd  $2, %[[R0]], 8(%{{.*}})
 ; CHECK-NEXT:    movq    %[[R0]], (%{{.*}})
-	%a = load %i32vec3* %ap, align 16
-	%b = load %i32vec3* %bp, align 16
+	%a = load %i32vec3, %i32vec3* %ap, align 16
+	%b = load %i32vec3, %i32vec3* %bp, align 16
 	%x = add %i32vec3 %a, %b
 	store %i32vec3 %x, %i32vec3* %ret, align 16
 	ret void
@@ -26,8 +26,8 @@ define void @add3i32_2(%i32vec3*  sret %ret, %i32vec3* %ap, %i32vec3* %bp)  {
 ; CHECK-NEXT:    paddd   %[[R0]], %[[R1]]
 ; CHECK-NEXT:    pextrd  $2, %[[R1]], 8(%{{.*}})
 ; CHECK-NEXT:    movq    %[[R1]], (%{{.*}})
-	%a = load %i32vec3* %ap, align 8
-	%b = load %i32vec3* %bp, align 8
+	%a = load %i32vec3, %i32vec3* %ap, align 8
+	%b = load %i32vec3, %i32vec3* %bp, align 8
 	%x = add %i32vec3 %a, %b
 	store %i32vec3 %x, %i32vec3* %ret, align 8
 	ret void
@@ -43,8 +43,8 @@ define void @add7i32(%i32vec7*  sret %ret, %i32vec7* %ap, %i32vec7* %bp)  {
 ; CHECK-NEXT:    pextrd  $2, %[[R1]], 24(%{{.*}})
 ; CHECK-NEXT:    movq    %[[R1]], 16(%{{.*}})
 ; CHECK-NEXT:    movdqa  %[[R0]], (%{{.*}})
-	%a = load %i32vec7* %ap, align 16
-	%b = load %i32vec7* %bp, align 16
+	%a = load %i32vec7, %i32vec7* %ap, align 16
+	%b = load %i32vec7, %i32vec7* %bp, align 16
 	%x = add %i32vec7 %a, %b
 	store %i32vec7 %x, %i32vec7* %ret, align 16
 	ret void
@@ -62,8 +62,8 @@ define void @add12i32(%i32vec12*  sret %ret, %i32vec12* %ap, %i32vec12* %bp)  {
 ; CHECK-NEXT:    movdqa  %[[R2]], 32(%{{.*}})
 ; CHECK-NEXT:    movdqa  %[[R1]], 16(%{{.*}})
 ; CHECK-NEXT:    movdqa  %[[R0]], (%{{.*}})
-	%a = load %i32vec12* %ap, align 16
-	%b = load %i32vec12* %bp, align 16
+	%a = load %i32vec12, %i32vec12* %ap, align 16
+	%b = load %i32vec12, %i32vec12* %bp, align 16
 	%x = add %i32vec12 %a, %b
 	store %i32vec12 %x, %i32vec12* %ret, align 16
 	ret void
@@ -76,13 +76,12 @@ define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp
 ; CHECK:         pmovzxwd (%{{.*}}), %[[R0:xmm[0-9]+]]
 ; CHECK-NEXT:    pmovzxwd (%{{.*}}), %[[R1:xmm[0-9]+]]
 ; CHECK-NEXT:    paddd    %[[R0]], %[[R1]]
-; CHECK-NEXT:    movdqa   %[[R1]], %[[R0]]
-; CHECK-NEXT:    pshufb   {{.*}}, %[[R0]]
-; CHECK-NEXT:    pmovzxdq %[[R0]], %[[R0]]
 ; CHECK-NEXT:    pextrw   $4, %[[R1]], 4(%{{.*}})
+; CHECK-NEXT:    pshufb   {{.*}}, %[[R1]]
+; CHECK-NEXT:    pmovzxdq %[[R1]], %[[R0]]
 ; CHECK-NEXT:    movd     %[[R0]], (%{{.*}})
-	%a = load %i16vec3* %ap, align 16
-	%b = load %i16vec3* %bp, align 16
+	%a = load %i16vec3, %i16vec3* %ap, align 16
+	%b = load %i16vec3, %i16vec3* %bp, align 16
 	%x = add %i16vec3 %a, %b
 	store %i16vec3 %x, %i16vec3* %ret, align 16
 	ret void
@@ -95,8 +94,8 @@ define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp
 ; CHECK-NEXT:    movq    (%{{.*}}), %[[R1:xmm[0-9]+]]
 ; CHECK-NEXT:    paddw   %[[R0]], %[[R1]]
 ; CHECK-NEXT:    movq    %[[R1]], (%{{.*}})
-	%a = load %i16vec4* %ap, align 16
-	%b = load %i16vec4* %bp, align 16
+	%a = load %i16vec4, %i16vec4* %ap, align 16
+	%b = load %i16vec4, %i16vec4* %bp, align 16
 	%x = add %i16vec4 %a, %b
 	store %i16vec4 %x, %i16vec4* %ret, align 16
 	ret void
@@ -111,8 +110,8 @@ define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12*
 ; CHECK-NEXT:    paddw   16(%{{.*}}), %[[R1]]
 ; CHECK-NEXT:    movq    %[[R1]], 16(%{{.*}})
 ; CHECK-NEXT:    movdqa  %[[R0]], (%{{.*}})
-	%a = load %i16vec12* %ap, align 16
-	%b = load %i16vec12* %bp, align 16
+	%a = load %i16vec12, %i16vec12* %ap, align 16
+	%b = load %i16vec12, %i16vec12* %bp, align 16
 	%x = add %i16vec12 %a, %b
 	store %i16vec12 %x, %i16vec12* %ret, align 16
 	ret void
@@ -130,8 +129,8 @@ define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18*
 ; CHECK-NEXT:    movd    %[[R2]], 32(%{{.*}})
 ; CHECK-NEXT:    movdqa  %[[R1]], 16(%{{.*}})
 ; CHECK-NEXT:    movdqa  %[[R0]], (%{{.*}})
-	%a = load %i16vec18* %ap, align 16
-	%b = load %i16vec18* %bp, align 16
+	%a = load %i16vec18, %i16vec18* %ap, align 16
+	%b = load %i16vec18, %i16vec18* %bp, align 16
 	%x = add %i16vec18 %a, %b
 	store %i16vec18 %x, %i16vec18* %ret, align 16
 	ret void
@@ -144,14 +143,13 @@ define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) no
 ; CHECK:         pmovzxbd (%{{.*}}), %[[R0:xmm[0-9]+]]
 ; CHECK-NEXT:    pmovzxbd (%{{.*}}), %[[R1:xmm[0-9]+]]
 ; CHECK-NEXT:    paddd    %[[R0]], %[[R1]]
-; CHECK-NEXT:    movdqa   %[[R1]], %[[R0]]
-; CHECK-NEXT:    pshufb   {{.*}}, %[[R0]]
-; CHECK-NEXT:    pmovzxwq %[[R0]], %[[R0]]
 ; CHECK-NEXT:    pextrb   $8, %[[R1]], 2(%{{.*}})
+; CHECK-NEXT:    pshufb   {{.*}}, %[[R1]]
+; CHECK-NEXT:    pmovzxwq %[[R1]], %[[R0]]
 ; CHECK-NEXT:    movd     %[[R0]], %e[[R2:[abcd]]]x
 ; CHECK-NEXT:    movw     %[[R2]]x, (%{{.*}})
-	%a = load %i8vec3* %ap, align 16
-	%b = load %i8vec3* %bp, align 16
+	%a = load %i8vec3, %i8vec3* %ap, align 16
+	%b = load %i8vec3, %i8vec3* %bp, align 16
 	%x = add %i8vec3 %a, %b
 	store %i8vec3 %x, %i8vec3* %ret, align 16
 	ret void
@@ -169,8 +167,8 @@ define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp
 ; CHECK-NEXT:    pextrd  $2, %[[R1]], 24(%{{.*}})
 ; CHECK-NEXT:    movq    %[[R1]], 16(%{{.*}})
 ; CHECK-NEXT:    movdqa  %[[R0]], (%{{.*}})
-	%a = load %i8vec31* %ap, align 16
-	%b = load %i8vec31* %bp, align 16
+	%a = load %i8vec31, %i8vec31* %ap, align 16
+	%b = load %i8vec31, %i8vec31* %bp, align 16
 	%x = add %i8vec31 %a, %b
 	store %i8vec31 %x, %i8vec31* %ret, align 16
 	ret void
@@ -193,8 +191,9 @@ define void @rot(%i8vec3pack* nocapture sret %result, %i8vec3pack* %X, %i8vec3pa
 ; CHECK-NEXT:    movd    %[[CONSTANT1]], %e[[R1:[abcd]]]x
 ; CHECK-NEXT:    movw    %[[R1]]x, (%[[PTR1:.*]])
 ; CHECK-NEXT:    movb    $1, 2(%[[PTR1]])
-; CHECK-NEXT:    pmovzxbd (%[[PTR0]]), %[[X0:xmm[0-9]+]]
-; CHECK-NEXT:    pand    {{.*}}, %[[X0]]
+; CHECK-NEXT:    movl    (%[[PTR0]]), [[TMP1:%e[abcd]+x]]
+; CHECK-NEXT:    movl    [[TMP1]], [[TMP2:.*]]
+; CHECK-NEXT:    pmovzxbd [[TMP2]], %[[X0:xmm[0-9]+]]
 ; CHECK-NEXT:    pextrd  $1, %[[X0]], %e[[R0:[abcd]]]x
 ; CHECK-NEXT:    shrl    %e[[R0]]x
 ; CHECK-NEXT:    movd    %[[X0]], %e[[R1:[abcd]]]x
@@ -206,10 +205,9 @@ define void @rot(%i8vec3pack* nocapture sret %result, %i8vec3pack* %X, %i8vec3pa
 ; CHECK-NEXT:    pinsrd  $2, %e[[R0]]x, %[[X1]]
 ; CHECK-NEXT:    pextrd  $3, %[[X0]], %e[[R0:[abcd]]]x
 ; CHECK-NEXT:    pinsrd  $3, %e[[R0]]x, %[[X1]]
-; CHECK-NEXT:    movdqa  %[[X1]], %[[X2:xmm[0-9]+]]
-; CHECK-NEXT:    pshufb  %[[SHUFFLE_MASK]], %[[X2]]
-; CHECK-NEXT:    pmovzxwq %[[X2]], %[[X3:xmm[0-9]+]]
 ; CHECK-NEXT:    pextrb  $8, %[[X1]], 2(%{{.*}})
+; CHECK-NEXT:    pshufb  %[[SHUFFLE_MASK]], %[[X1]]
+; CHECK-NEXT:    pmovzxwq %[[X1]], %[[X3:xmm[0-9]+]]
 ; CHECK-NEXT:    movd    %[[X3]], %e[[R0:[abcd]]]x
 ; CHECK-NEXT:    movw    %[[R0]]x, (%{{.*}})
 
@@ -218,9 +216,9 @@ entry:
   store <3 x i8> <i8 -98, i8 -98, i8 -98>, <3 x i8>* %storetmp
   %storetmp1 = bitcast %i8vec3pack* %rot to <3 x i8>*
   store <3 x i8> <i8 1, i8 1, i8 1>, <3 x i8>* %storetmp1
-  %tmp = load %i8vec3pack* %X
+  %tmp = load %i8vec3pack, %i8vec3pack* %X
   %extractVec = extractvalue %i8vec3pack %tmp, 0
-  %tmp2 = load %i8vec3pack* %rot
+  %tmp2 = load %i8vec3pack, %i8vec3pack* %rot
   %extractVec3 = extractvalue %i8vec3pack %tmp2, 0
   %shr = lshr <3 x i8> %extractVec, %extractVec3
   %storetmp4 = bitcast %i8vec3pack* %result to <3 x i8>*
diff --git a/test/CodeGen/X86/widen_shuffle-1.ll b/test/CodeGen/X86/widen_shuffle-1.ll
index 70fdbb7c9c82..302805213d06 100644
--- a/test/CodeGen/X86/widen_shuffle-1.ll
+++ b/test/CodeGen/X86/widen_shuffle-1.ll
@@ -82,9 +82,9 @@ define void @shuf5(<8 x i8>* %p) nounwind {
 ; CHECK-LABEL: shuf5:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    movdqa {{.*#+}} xmm0 = <4,33,u,u,u,u,u,u>
-; CHECK-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[2,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
-; CHECK-NEXT:    movlpd %xmm0, (%eax)
+; CHECK-NEXT:    movdqa {{.*#+}} xmm0 = [33,33,33,33,33,33,33,33]
+; CHECK-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; CHECK-NEXT:    movq %xmm0, (%eax)
 ; CHECK-NEXT:    retl
   %v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   store <8 x i8> %v, <8 x i8>* %p, align 8
diff --git a/test/CodeGen/X86/win32-eh.ll b/test/CodeGen/X86/win32-eh.ll
new file mode 100644
index 000000000000..4d3c34ed6c17
--- /dev/null
+++ b/test/CodeGen/X86/win32-eh.ll
@@ -0,0 +1,91 @@
+; RUN: llc -mtriple=i686-pc-windows-msvc < %s | FileCheck %s
+
+declare void @may_throw_or_crash()
+declare i32 @_except_handler3(...)
+declare i32 @_except_handler4(...)
+declare i32 @__CxxFrameHandler3(...)
+declare void @llvm.eh.begincatch(i8*, i8*)
+declare void @llvm.eh.endcatch()
+
+define void @use_except_handler3() {
+  invoke void @may_throw_or_crash()
+      to label %cont unwind label %catchall
+cont:
+  ret void
+catchall:
+  landingpad { i8*, i32 } personality i32 (...)* @_except_handler3
+      catch i8* null
+  br label %cont
+}
+
+; CHECK-LABEL: _use_except_handler3:
+; CHECK: subl ${{[0-9]+}}, %esp
+; CHECK: movl $-1, 12(%esp)
+; CHECK: movl $L__ehtable$use_except_handler3, 8(%esp)
+; CHECK: movl $__except_handler3, 4(%esp)
+; CHECK: movl %fs:0, %[[next:[^ ,]*]]
+; CHECK: movl %[[next]], (%esp)
+; CHECK: leal (%esp), %[[node:[^ ,]*]]
+; CHECK: movl %[[node]], %fs:0
+; CHECK: calll _may_throw_or_crash
+; CHECK: movl (%esp), %[[next:[^ ,]*]]
+; CHECK: movl %[[next]], %fs:0
+; CHECK: retl
+
+define void @use_except_handler4() {
+  invoke void @may_throw_or_crash()
+      to label %cont unwind label %catchall
+cont:
+  ret void
+catchall:
+  landingpad { i8*, i32 } personality i32 (...)* @_except_handler4
+      catch i8* null
+  br label %cont
+}
+
+; CHECK-LABEL: _use_except_handler4:
+; CHECK: subl ${{[0-9]+}}, %esp
+; CHECK: movl %esp, (%esp)
+; CHECK: movl $-2, 20(%esp)
+; CHECK: movl $L__ehtable$use_except_handler4, 4(%esp)
+; CHECK: leal 8(%esp), %[[node:[^ ,]*]]
+; CHECK: movl $__except_handler4, 12(%esp)
+; CHECK: movl %fs:0, %[[next:[^ ,]*]]
+; CHECK: movl %[[next]], 8(%esp)
+; CHECK: movl %[[node]], %fs:0
+; CHECK: calll _may_throw_or_crash
+; CHECK: movl 8(%esp), %[[next:[^ ,]*]]
+; CHECK: movl %[[next]], %fs:0
+; CHECK: retl
+
+define void @use_CxxFrameHandler3() {
+  invoke void @may_throw_or_crash()
+      to label %cont unwind label %catchall
+cont:
+  ret void
+catchall:
+  %ehvals = landingpad { i8*, i32 } personality i32 (...)* @__CxxFrameHandler3
+      catch i8* null
+  %ehptr = extractvalue { i8*, i32 } %ehvals, 0
+  call void @llvm.eh.begincatch(i8* %ehptr, i8* null)
+  call void @llvm.eh.endcatch()
+  br label %cont
+}
+
+; CHECK-LABEL: _use_CxxFrameHandler3:
+; CHECK: subl ${{[0-9]+}}, %esp
+; CHECK: movl %esp, (%esp)
+; CHECK: movl $-1, 12(%esp)
+; CHECK: leal 4(%esp), %[[node:[^ ,]*]]
+; CHECK: movl $___ehhandler$use_CxxFrameHandler3, 8(%esp)
+; CHECK: movl %fs:0, %[[next:[^ ,]*]]
+; CHECK: movl %[[next]], 4(%esp)
+; CHECK: movl %[[node]], %fs:0
+; CHECK: calll _may_throw_or_crash
+; CHECK: movl 4(%esp), %[[next:[^ ,]*]]
+; CHECK: movl %[[next]], %fs:0
+; CHECK: retl
+
+; CHECK-LABEL: ___ehhandler$use_CxxFrameHandler3:
+; CHECK: movl $L__ehtable$use_CxxFrameHandler3, %eax
+; CHECK: jmp  ___CxxFrameHandler3 # TAILCALL
diff --git a/test/CodeGen/X86/win32_sret.ll b/test/CodeGen/X86/win32_sret.ll
index 8728712cece4..b38273ad9594 100644
--- a/test/CodeGen/X86/win32_sret.ll
+++ b/test/CodeGen/X86/win32_sret.ll
@@ -94,7 +94,7 @@ entry:
 ; LINUX-LABEL:     sret4:
 ; LINUX:     retl $4
 
-  %x = getelementptr inbounds %struct.S4* %agg.result, i32 0, i32 0
+  %x = getelementptr inbounds %struct.S4, %struct.S4* %agg.result, i32 0, i32 0
   store i32 42, i32* %x, align 4
   ret void
 }
@@ -106,8 +106,8 @@ define x86_thiscallcc void @"\01?foo@C5@@QAE?AUS5@@XZ"(%struct.S5* noalias sret
 entry:
   %this.addr = alloca %class.C5*, align 4
   store %class.C5* %this, %class.C5** %this.addr, align 4
-  %this1 = load %class.C5** %this.addr
-  %x = getelementptr inbounds %struct.S5* %agg.result, i32 0, i32 0
+  %this1 = load %class.C5*, %class.C5** %this.addr
+  %x = getelementptr inbounds %struct.S5, %struct.S5* %agg.result, i32 0, i32 0
   store i32 42, i32* %x, align 4
   ret void
 ; WIN32-LABEL:     {{^}}"?foo@C5@@QAE?AUS5@@XZ":
@@ -155,25 +155,25 @@ define void @test6_f(%struct.test6* %x) nounwind {
 ; LINUX-LABEL: test6_f:
 
 ; The %x argument is moved to %ecx. It will be the this pointer.
-; WIN32: movl    8(%ebp), %ecx
+; WIN32: movl    20(%esp), %ecx
 
 ; The %x argument is moved to (%esp). It will be the this pointer. With -O0
 ; we copy esp to ecx and use (ecx) instead of (esp).
-; MINGW_X86: movl    8(%ebp), %eax
+; MINGW_X86: movl    20(%esp), %eax
 ; MINGW_X86: movl    %eax, (%e{{([a-d]x)|(sp)}})
 
-; CYGWIN: movl    8(%ebp), %eax
+; CYGWIN: movl    20(%esp), %eax
 ; CYGWIN: movl    %eax, (%e{{([a-d]x)|(sp)}})
 
 ; The sret pointer is (%esp)
-; WIN32:          leal    8(%esp), %[[REG:e[a-d]x]]
+; WIN32:          leal    4(%esp), %[[REG:e[a-d]x]]
 ; WIN32-NEXT:     movl    %[[REG]], (%e{{([a-d]x)|(sp)}})
 
 ; The sret pointer is %ecx
-; MINGW_X86-NEXT: leal    8(%esp), %ecx
+; MINGW_X86-NEXT: leal    4(%esp), %ecx
 ; MINGW_X86-NEXT: calll   _test6_g
 
-; CYGWIN-NEXT: leal    8(%esp), %ecx
+; CYGWIN-NEXT: leal    4(%esp), %ecx
 ; CYGWIN-NEXT: calll   _test6_g
 
   %tmp = alloca %struct.test6, align 4
@@ -191,16 +191,16 @@ define void @test7_f(%struct.test7* %x) nounwind {
 ; LINUX-LABEL: test7_f:
 
 ; The %x argument is moved to %ecx on all OSs. It will be the this pointer.
-; WIN32:      movl    8(%ebp), %ecx
-; MINGW_X86:  movl    8(%ebp), %ecx
-; CYGWIN:     movl    8(%ebp), %ecx
+; WIN32:      movl    20(%esp), %ecx
+; MINGW_X86:  movl    20(%esp), %ecx
+; CYGWIN:     movl    20(%esp), %ecx
 
 ; The sret pointer is (%esp)
-; WIN32:          leal    8(%esp), %[[REG:e[a-d]x]]
+; WIN32:          leal    4(%esp), %[[REG:e[a-d]x]]
 ; WIN32-NEXT:     movl    %[[REG]], (%e{{([a-d]x)|(sp)}})
-; MINGW_X86:      leal    8(%esp), %[[REG:e[a-d]x]]
+; MINGW_X86:      leal    4(%esp), %[[REG:e[a-d]x]]
 ; MINGW_X86-NEXT: movl    %[[REG]], (%e{{([a-d]x)|(sp)}})
-; CYGWIN:         leal    8(%esp), %[[REG:e[a-d]x]]
+; CYGWIN:         leal    4(%esp), %[[REG:e[a-d]x]]
 ; CYGWIN-NEXT:    movl    %[[REG]], (%e{{([a-d]x)|(sp)}})
 
   %tmp = alloca %struct.test7, align 4
@@ -209,9 +209,9 @@ define void @test7_f(%struct.test7* %x) nounwind {
 }
 
 define x86_thiscallcc void @test7_g(%struct.test7* %in, %struct.test7* sret %out) {
-  %s = getelementptr %struct.test7* %in, i32 0, i32 0
-  %d = getelementptr %struct.test7* %out, i32 0, i32 0
-  %v = load i32* %s
+  %s = getelementptr %struct.test7, %struct.test7* %in, i32 0, i32 0
+  %d = getelementptr %struct.test7, %struct.test7* %out, i32 0, i32 0
+  %v = load i32, i32* %s
   store i32 %v, i32* %d
   call void @clobber_eax()
   ret void
diff --git a/test/CodeGen/X86/win64_alloca_dynalloca.ll b/test/CodeGen/X86/win64_alloca_dynalloca.ll
index aab2eea7ce44..abda2272c662 100644
--- a/test/CodeGen/X86/win64_alloca_dynalloca.ll
+++ b/test/CodeGen/X86/win64_alloca_dynalloca.ll
@@ -14,26 +14,24 @@ entry:
   %buf0 = alloca i8, i64 4096, align 1
 
 ; ___chkstk_ms does not adjust %rsp.
-; M64: movq  %rsp, %rbp
-; M64:       $4096, %rax
+; M64:       $4096, %eax
 ; M64: callq ___chkstk_ms
 ; M64: subq  %rax, %rsp
+; M64: leaq 128(%rsp), %rbp
 
 ; __chkstk does not adjust %rsp.
-; W64: movq  %rsp, %rbp
-; W64:       $4096, %rax
+; W64:       $4096, %eax
 ; W64: callq __chkstk
 ; W64: subq  %rax, %rsp
+; W64: leaq 128(%rsp), %rbp
 
 ; Use %r11 for the large model.
-; L64: movq  %rsp, %rbp
-; L64:       $4096, %rax
+; L64:       $4096, %eax
 ; L64: movabsq $__chkstk, %r11
 ; L64: callq *%r11
 ; L64: subq  %rax, %rsp
 
 ; Freestanding
-; EFI: movq  %rsp, %rbp
 ; EFI:       $[[B0OFS:4096|4104]], %rsp
 ; EFI-NOT:   call
 
@@ -68,12 +66,12 @@ entry:
 
 ; M64: subq  $48, %rsp
 ; M64: movq  %rax, 32(%rsp)
-; M64: leaq  -4096(%rbp), %r9
+; M64: leaq  -128(%rbp), %r9
 ; M64: callq bar
 
 ; W64: subq  $48, %rsp
 ; W64: movq  %rax, 32(%rsp)
-; W64: leaq  -4096(%rbp), %r9
+; W64: leaq  -128(%rbp), %r9
 ; W64: callq bar
 
 ; EFI: subq  $48, %rsp
@@ -83,9 +81,9 @@ entry:
 
   ret i64 %r
 
-; M64: movq    %rbp, %rsp
+; M64: leaq    3968(%rbp), %rsp
 
-; W64: movq    %rbp, %rsp
+; W64: leaq    3968(%rbp), %rsp
 
 }
 
diff --git a/test/CodeGen/X86/win64_eh.ll b/test/CodeGen/X86/win64_eh.ll
index 4670087b9b4d..d668f43c895e 100644
--- a/test/CodeGen/X86/win64_eh.ll
+++ b/test/CodeGen/X86/win64_eh.ll
@@ -1,5 +1,6 @@
-; RUN: llc < %s -O0 -mcpu=corei7 -mtriple=x86_64-pc-windows-itanium | FileCheck %s -check-prefix=WIN64
-; RUN: llc < %s -O0 -mcpu=corei7 -mtriple=x86_64-pc-mingw32 | FileCheck %s -check-prefix=WIN64
+; RUN: llc < %s -O0 -mattr=sse2 -mtriple=x86_64-pc-windows-itanium | FileCheck %s -check-prefix=WIN64 -check-prefix=NORM
+; RUN: llc < %s -O0 -mattr=sse2 -mtriple=x86_64-pc-mingw32 | FileCheck %s -check-prefix=WIN64 -check-prefix=NORM
+; RUN: llc < %s -O0 -mattr=sse2 -mtriple=x86_64-pc-mingw32 -mcpu=atom | FileCheck %s -check-prefix=WIN64 -check-prefix=ATOM
 
 ; Check function without prolog
 define void @foo0() uwtable {
@@ -20,7 +21,8 @@ entry:
 }
 ; WIN64-LABEL: foo1:
 ; WIN64: .seh_proc foo1
-; WIN64: subq $4000, %rsp
+; NORM:  subq $4000, %rsp
+; ATOM:  leaq -4000(%rsp), %rsp
 ; WIN64: .seh_stackalloc 4000
 ; WIN64: .seh_endprologue
 ; WIN64: addq $4000, %rsp
@@ -35,7 +37,7 @@ entry:
 }
 ; WIN64-LABEL: foo2:
 ; WIN64: .seh_proc foo2
-; WIN64: movabsq $8000, %rax
+; WIN64: movl $8000, %eax
 ; WIN64: callq {{__chkstk|___chkstk_ms}}
 ; WIN64: subq %rax, %rsp
 ; WIN64: .seh_stackalloc 8000
@@ -60,21 +62,21 @@ entry:
   store i32 %d_arg, i32* %d
   store i32 %e_arg, i32* %e
   store i32 %f_arg, i32* %f
-  %tmp = load i32* %a
+  %tmp = load i32, i32* %a
   %tmp1 = mul i32 %tmp, 2
-  %tmp2 = load i32* %b
+  %tmp2 = load i32, i32* %b
   %tmp3 = mul i32 %tmp2, 3
   %tmp4 = add i32 %tmp1, %tmp3
-  %tmp5 = load i32* %c
+  %tmp5 = load i32, i32* %c
   %tmp6 = mul i32 %tmp5, 5
   %tmp7 = add i32 %tmp4, %tmp6
-  %tmp8 = load i32* %d
+  %tmp8 = load i32, i32* %d
   %tmp9 = mul i32 %tmp8, 7
   %tmp10 = add i32 %tmp7, %tmp9
-  %tmp11 = load i32* %e
+  %tmp11 = load i32, i32* %e
   %tmp12 = mul i32 %tmp11, 11
   %tmp13 = add i32 %tmp10, %tmp12
-  %tmp14 = load i32* %f
+  %tmp14 = load i32, i32* %f
   %tmp15 = mul i32 %tmp14, 13
   %tmp16 = add i32 %tmp13, %tmp15
   ret i32 %tmp16
@@ -83,7 +85,8 @@ entry:
 ; WIN64: .seh_proc foo3
 ; WIN64: pushq %rsi
 ; WIN64: .seh_pushreg 6
-; WIN64: subq $24, %rsp
+; NORM:  subq $24, %rsp
+; ATOM:  leaq -24(%rsp), %rsp
 ; WIN64: .seh_stackalloc 24
 ; WIN64: .seh_endprologue
 ; WIN64: addq $24, %rsp
@@ -102,7 +105,7 @@ define i32 @foo4() #0 {
 entry:
   %step = alloca i32, align 4
   store i32 0, i32* %step
-  %tmp = load i32* %step
+  %tmp = load i32, i32* %step
 
   %tmp1 = invoke i32 @bar()
           to label %finally unwind label %landingpad
@@ -120,13 +123,14 @@ landingpad:
   unreachable
 
 endtryfinally:
-  %tmp10 = load i32* %step
+  %tmp10 = load i32, i32* %step
   ret i32 %tmp10
 }
 ; WIN64-LABEL: foo4:
 ; WIN64: .seh_proc foo4
 ; WIN64: .seh_handler _d_eh_personality, @unwind, @except
-; WIN64: subq $56, %rsp
+; NORM:  subq $56, %rsp
+; ATOM:  leaq -56(%rsp), %rsp
 ; WIN64: .seh_stackalloc 56
 ; WIN64: .seh_endprologue
 ; WIN64: addq $56, %rsp
@@ -146,23 +150,24 @@ entry:
 ; WIN64: .seh_proc foo5
 ; WIN64: pushq %rbp
 ; WIN64: .seh_pushreg 5
-; WIN64: movq  %rsp, %rbp
 ; WIN64: pushq %rdi
 ; WIN64: .seh_pushreg 7
 ; WIN64: pushq %rbx
 ; WIN64: .seh_pushreg 3
-; WIN64: andq  $-64, %rsp
-; WIN64: subq  $128, %rsp
-; WIN64: .seh_stackalloc 48
-; WIN64: .seh_setframe 5, 64
-; WIN64: movaps  %xmm7, -32(%rbp)        # 16-byte Spill
-; WIN64: movaps  %xmm6, -48(%rbp)        # 16-byte Spill
-; WIN64: .seh_savexmm 6, 16
-; WIN64: .seh_savexmm 7, 32
+; NORM:  subq  $96, %rsp
+; ATOM:  leaq -96(%rsp), %rsp
+; WIN64: .seh_stackalloc 96
+; WIN64: leaq  96(%rsp), %rbp
+; WIN64: .seh_setframe 5, 96
+; WIN64: movaps  %xmm7, -16(%rbp)        # 16-byte Spill
+; WIN64: .seh_savexmm 7, 80
+; WIN64: movaps  %xmm6, -32(%rbp)        # 16-byte Spill
+; WIN64: .seh_savexmm 6, 64
 ; WIN64: .seh_endprologue
-; WIN64: movaps  -48(%rbp), %xmm6        # 16-byte Reload
-; WIN64: movaps  -32(%rbp), %xmm7        # 16-byte Reload
-; WIN64: leaq  -16(%rbp), %rsp
+; WIN64: andq  $-64, %rsp
+; WIN64: movaps  -32(%rbp), %xmm6        # 16-byte Reload
+; WIN64: movaps  -16(%rbp), %xmm7        # 16-byte Reload
+; WIN64: movq  %rbp, %rsp
 ; WIN64: popq  %rbx
 ; WIN64: popq  %rdi
 ; WIN64: popq  %rbp
diff --git a/test/CodeGen/X86/win64_frame.ll b/test/CodeGen/X86/win64_frame.ll
new file mode 100644
index 000000000000..2c62f4918a7f
--- /dev/null
+++ b/test/CodeGen/X86/win64_frame.ll
@@ -0,0 +1,122 @@
+; RUN: llc < %s -mtriple=x86_64-pc-win32 | FileCheck %s
+
+define i32 @f1(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) "no-frame-pointer-elim"="true" {
+  ; CHECK-LABEL: f1:
+  ; CHECK:       movl    48(%rbp), %eax
+  ret i32 %p5
+}
+
+define void @f2(i32 %p, ...) "no-frame-pointer-elim"="true" {
+  ; CHECK-LABEL: f2:
+  ; CHECK:      .seh_stackalloc 8
+  ; CHECK:      movq    %rsp, %rbp
+  ; CHECK:      .seh_setframe 5, 0
+  ; CHECK:      movq    %rdx, 32(%rbp)
+  ; CHECK:      leaq    32(%rbp), %rax
+  %ap = alloca i8, align 8
+  call void @llvm.va_start(i8* %ap)
+  ret void
+}
+
+define i8* @f3() "no-frame-pointer-elim"="true" {
+  ; CHECK-LABEL: f3:
+  ; CHECK:      movq    %rsp, %rbp
+  ; CHECK:      .seh_setframe 5, 0
+  ; CHECK:      movq    8(%rbp), %rax
+  %ra = call i8* @llvm.returnaddress(i32 0)
+  ret i8* %ra
+}
+
+define i8* @f4() "no-frame-pointer-elim"="true" {
+  ; CHECK-LABEL: f4:
+  ; CHECK:      pushq   %rbp
+  ; CHECK:      .seh_pushreg 5
+  ; CHECK:      subq    $304, %rsp
+  ; CHECK:      .seh_stackalloc 304
+  ; CHECK:      leaq    128(%rsp), %rbp
+  ; CHECK:      .seh_setframe 5, 128
+  ; CHECK:      .seh_endprologue
+  ; CHECK:      movq    184(%rbp), %rax
+  alloca [300 x i8]
+  %ra = call i8* @llvm.returnaddress(i32 0)
+  ret i8* %ra
+}
+
+declare void @external(i8*)
+
+define void @f5() "no-frame-pointer-elim"="true" {
+  ; CHECK-LABEL: f5:
+  ; CHECK:      subq    $336, %rsp
+  ; CHECK:      .seh_stackalloc 336
+  ; CHECK:      leaq    128(%rsp), %rbp
+  ; CHECK:      .seh_setframe 5, 128
+  ; CHECK:      leaq    -92(%rbp), %rcx
+  ; CHECK:      callq   external
+  %a = alloca [300 x i8]
+  %gep = getelementptr [300 x i8], [300 x i8]* %a, i32 0, i32 0
+  call void @external(i8* %gep)
+  ret void
+}
+
+define void @f6(i32 %p, ...) "no-frame-pointer-elim"="true" {
+  ; CHECK-LABEL: f6:
+  ; CHECK:      subq    $336, %rsp
+  ; CHECK:      .seh_stackalloc 336
+  ; CHECK:      leaq    128(%rsp), %rbp
+  ; CHECK:      .seh_setframe 5, 128
+  ; CHECK:      leaq    -92(%rbp), %rcx
+  ; CHECK:      callq   external
+  %a = alloca [300 x i8]
+  %gep = getelementptr [300 x i8], [300 x i8]* %a, i32 0, i32 0
+  call void @external(i8* %gep)
+  ret void
+}
+
+define i32 @f7(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) "no-frame-pointer-elim"="true" {
+  ; CHECK-LABEL: f7:
+  ; CHECK:      pushq   %rbp
+  ; CHECK:      .seh_pushreg 5
+  ; CHECK:      subq    $304, %rsp
+  ; CHECK:      .seh_stackalloc 304
+  ; CHECK:      leaq    128(%rsp), %rbp
+  ; CHECK:      .seh_setframe 5, 128
+  ; CHECK:      andq    $-64, %rsp
+  ; CHECK:      movl    224(%rbp), %eax
+  ; CHECK:      leaq    176(%rbp), %rsp
+  alloca [300 x i8], align 64
+  ret i32 %e
+}
+
+define i32 @f8(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) "no-frame-pointer-elim"="true" {
+  ; CHECK-LABEL: f8:
+  ; CHECK:        subq    $352, %rsp
+  ; CHECK:        .seh_stackalloc 352
+  ; CHECK:        leaq    128(%rsp), %rbp
+  ; CHECK:        .seh_setframe 5, 128
+
+  %alloca = alloca [300 x i8], align 64
+  ; CHECK:        andq    $-64, %rsp
+  ; CHECK:        movq    %rsp, %rbx
+
+  alloca i32, i32 %a
+  ; CHECK:        movl    %ecx, %eax
+  ; CHECK:        leaq    15(,%rax,4), %rax
+  ; CHECK:        andq    $-16, %rax
+  ; CHECK:        callq   __chkstk
+  ; CHECK:        subq    %rax, %rsp
+
+  %gep = getelementptr [300 x i8], [300 x i8]* %alloca, i32 0, i32 0
+  call void @external(i8* %gep)
+  ; CHECK:        subq    $32, %rsp
+  ; CHECK:        leaq    (%rbx), %rcx
+  ; CHECK:        callq   external
+  ; CHECK:        addq    $32, %rsp
+
+  ret i32 %e
+  ; CHECK:        movl    %esi, %eax
+  ; CHECK:        leaq    224(%rbp), %rsp
+}
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
+
+declare void @llvm.va_start(i8*) nounwind
diff --git a/test/CodeGen/X86/win64_nonvol.ll b/test/CodeGen/X86/win64_nonvol.ll
new file mode 100644
index 000000000000..8e5f6cec1ab7
--- /dev/null
+++ b/test/CodeGen/X86/win64_nonvol.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -mtriple=x86_64-pc-win32 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s
+
+; Check that, if a Win64 ABI function calls a SysV ABI function, all the
+; Win64 nonvolatile registers get saved.
+
+; CHECK-LABEL: bar:
+define x86_64_win64cc void @bar(i32 %a, i32 %b) {
+; CHECK-DAG: pushq %rdi
+; CHECK-DAG: pushq %rsi
+; CHECK-DAG: movaps %xmm6,
+; CHECK-DAG: movaps %xmm7,
+; CHECK-DAG: movaps %xmm8,
+; CHECK-DAG: movaps %xmm9,
+; CHECK-DAG: movaps %xmm10,
+; CHECK-DAG: movaps %xmm11,
+; CHECK-DAG: movaps %xmm12,
+; CHECK-DAG: movaps %xmm13,
+; CHECK-DAG: movaps %xmm14,
+; CHECK-DAG: movaps %xmm15,
+; CHECK: callq foo
+; CHECK: ret
+  call x86_64_sysvcc void @foo(i32 %a, i32 %b)
+  ret void
+}
+
+declare x86_64_sysvcc void @foo(i32 %a, i32 %b)
+
diff --git a/test/CodeGen/X86/win_cst_pool.ll b/test/CodeGen/X86/win_cst_pool.ll
index d534b126b192..199557dac206 100644
--- a/test/CodeGen/X86/win_cst_pool.ll
+++ b/test/CodeGen/X86/win_cst_pool.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=corei7 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-win32 -mattr=sse2 | FileCheck %s
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-pc-windows-msvc"
 
diff --git a/test/CodeGen/X86/win_eh_prepare.ll b/test/CodeGen/X86/win_eh_prepare.ll
new file mode 100644
index 000000000000..a33dd92ad72a
--- /dev/null
+++ b/test/CodeGen/X86/win_eh_prepare.ll
@@ -0,0 +1,82 @@
+; RUN: opt -S -winehprepare -dwarfehprepare -mtriple x86_64-pc-windows-msvc < %s | FileCheck %s
+
+; FIXME: Add and test outlining here.
+
+declare void @maybe_throw()
+
+@_ZTIi = external constant i8*
+@g = external global i32
+
+declare i32 @__C_specific_handler(...)
+declare i32 @__gxx_personality_seh0(...)
+declare i32 @llvm.eh.typeid.for(i8*) readnone nounwind
+
+define i32 @use_seh() {
+entry:
+  invoke void @maybe_throw()
+      to label %cont unwind label %lpad
+
+cont:
+  ret i32 0
+
+lpad:
+  %ehvals = landingpad { i8*, i32 } personality i32 (...)* @__C_specific_handler
+      cleanup
+      catch i8* bitcast (i32 (i8*, i8*)* @filt_g to i8*)
+  %ehsel = extractvalue { i8*, i32 } %ehvals, 1
+  %filt_g_sel = call i32 @llvm.eh.typeid.for(i8* bitcast (i32 (i8*, i8*)* @filt_g to i8*))
+  %matches = icmp eq i32 %ehsel, %filt_g_sel
+  br i1 %matches, label %ret1, label %eh.resume
+
+ret1:
+  ret i32 1
+
+eh.resume:
+  resume { i8*, i32 } %ehvals
+}
+
+define internal i32 @filt_g(i8*, i8*) {
+  %g = load i32, i32* @g
+  ret i32 %g
+}
+
+; CHECK-LABEL: define i32 @use_seh()
+; CHECK: invoke void @maybe_throw()
+; CHECK-NEXT: to label %cont unwind label %lpad
+; CHECK: landingpad
+; CHECK-NEXT: cleanup
+; CHECK-NEXT: catch
+; CHECK-NEXT: call i8* (...) @llvm.eh.actions({{.*}})
+
+
+; A MinGW64-ish EH style. It could happen if a binary uses both MSVC CRT and
+; mingw CRT and is linked with LTO.
+define i32 @use_gcc() {
+entry:
+  invoke void @maybe_throw()
+      to label %cont unwind label %lpad
+
+cont:
+  ret i32 0
+
+lpad:
+  %ehvals = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_seh0
+      cleanup
+      catch i8* bitcast (i8** @_ZTIi to i8*)
+  %ehsel = extractvalue { i8*, i32 } %ehvals, 1
+  %filt_g_sel = call i32 @llvm.eh.typeid.for(i8* bitcast (i32 (i8*, i8*)* @filt_g to i8*))
+  %matches = icmp eq i32 %ehsel, %filt_g_sel
+  br i1 %matches, label %ret1, label %eh.resume
+
+ret1:
+  ret i32 1
+
+eh.resume:
+  resume { i8*, i32 } %ehvals
+}
+
+; CHECK-LABEL: define i32 @use_gcc()
+; CHECK: invoke void @maybe_throw()
+; CHECK-NEXT: to label %cont unwind label %lpad
+; CHECK: eh.resume:
+; CHECK: call void @_Unwind_Resume(i8* %exn.obj)
diff --git a/test/CodeGen/X86/x32-function_pointer-1.ll b/test/CodeGen/X86/x32-function_pointer-1.ll
index 2baf92a99790..952add91d52b 100644
--- a/test/CodeGen/X86/x32-function_pointer-1.ll
+++ b/test/CodeGen/X86/x32-function_pointer-1.ll
@@ -8,11 +8,11 @@
 
 define void @bar(i8* %h) nounwind uwtable {
 entry:
-  %0 = load void (i8*)** @foo1, align 4
+  %0 = load void (i8*)*, void (i8*)** @foo1, align 4
 ; CHECK: movl	foo1(%rip), %e{{[^,]*}}
   tail call void %0(i8* %h) nounwind
 ; CHECK: callq	*%r{{[^,]*}}
-  %1 = load void (i8*)** @foo2, align 4
+  %1 = load void (i8*)*, void (i8*)** @foo2, align 4
 ; CHECK: movl	foo2(%rip), %e{{[^,]*}}
   tail call void %1(i8* %h) nounwind
 ; CHECK: jmpq	*%r{{[^,]*}}
diff --git a/test/CodeGen/X86/x32-lea-1.ll b/test/CodeGen/X86/x32-lea-1.ll
new file mode 100644
index 000000000000..2f7d71e2baf1
--- /dev/null
+++ b/test/CodeGen/X86/x32-lea-1.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -O0 | FileCheck %s
+; CHECK: leal {{[-0-9]*}}(%r{{s|b}}p),
+; CHECK-NOT: leal {{[-0-9]*}}(%e{{s|b}}p),
+
+define void @foo(i32** %p) {
+  %a = alloca i32, i32 10
+  %addr = getelementptr i32, i32* %a, i32 4
+  store i32* %addr, i32** %p
+  ret void
+}
diff --git a/test/CodeGen/X86/x86-32-vector-calling-conv.ll b/test/CodeGen/X86/x86-32-vector-calling-conv.ll
new file mode 100644
index 000000000000..b2bda7ab8d01
--- /dev/null
+++ b/test/CodeGen/X86/x86-32-vector-calling-conv.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx512f | FileCheck %s --check-prefix=DARWIN
+; RUN: llc < %s -mtriple=i686-pc-linux -mattr=+avx512f | FileCheck %s --check-prefix=LINUX
+
+; CHECK-LABEL: test_sse:
+; DARWIN-DAG: vpaddd  %xmm1, %xmm0, %xmm0
+; DARWIN-DAG: vpaddd  %xmm3, %xmm2, %xmm1
+; DARWIN: vpaddd  %xmm1, %xmm0, %xmm0
+; LINUX-DAG:  vpaddd  %xmm1, %xmm0, %xmm0
+; LINUX-DAG:  vpaddd  {{[0-9]+}}(%e{{s|b}}p), %xmm2, %xmm1
+; LINUX:  vpaddd  %xmm1, %xmm0, %xmm0
+define <4 x i32> @test_sse(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) nounwind {
+  %r0 = add <4 x i32> %a, %b
+  %r1 = add <4 x i32> %c, %d
+  %ret = add <4 x i32> %r0, %r1
+  ret <4 x i32> %ret
+}
+
+; CHECK-LABEL: test_avx:
+; DARWIN-DAG: vpaddd  %ymm1, %ymm0, %ymm0
+; DARWIN-DAG: vpaddd  %ymm3, %ymm2, %ymm1
+; DARWIN: vpaddd  %ymm1, %ymm0, %ymm0
+; LINUX-DAG:  vpaddd  %ymm1, %ymm0, %ymm0
+; LINUX-DAG:  vpaddd  {{[0-9]+}}(%e{{s|b}}p), %ymm2, %ymm1
+; LINUX:  vpaddd  %ymm1, %ymm0, %ymm0
+define <8 x i32> @test_avx(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) nounwind {
+  %r0 = add <8 x i32> %a, %b
+  %r1 = add <8 x i32> %c, %d
+  %ret = add <8 x i32> %r0, %r1
+  ret <8 x i32> %ret
+}
+
+; CHECK-LABEL: test_avx512:
+; DARWIN-DAG: vpaddd  %zmm1, %zmm0, %zmm0
+; DARWIN-DAG: vpaddd  %zmm3, %zmm2, %zmm1
+; DARWIN: vpaddd  %zmm1, %zmm0, %zmm0
+; LINUX-DAG:  vpaddd  %zmm1, %zmm0, %zmm0
+; LINUX-DAG:  vpaddd  {{[0-9]+}}(%e{{s|b}}p), %zmm2, %zmm1
+; LINUX:  vpaddd  %zmm1, %zmm0, %zmm0
+define <16 x i32> @test_avx512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16 x i32> %d) nounwind {
+  %r0 = add <16 x i32> %a, %b
+  %r1 = add <16 x i32> %c, %d
+  %ret = add <16 x i32> %r0, %r1
+  ret <16 x i32> %ret
+}
diff --git a/test/CodeGen/X86/x86-64-and-mask.ll b/test/CodeGen/X86/x86-64-and-mask.ll
index bc6c612482b0..c8a832a6d3a2 100644
--- a/test/CodeGen/X86/x86-64-and-mask.ll
+++ b/test/CodeGen/X86/x86-64-and-mask.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=corei7 < %s | FileCheck %s
+; RUN: llc < %s | FileCheck %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-apple-darwin8"
diff --git a/test/CodeGen/X86/x86-64-asm.ll b/test/CodeGen/X86/x86-64-asm.ll
index 2640e593ec18..f103ab75af99 100644
--- a/test/CodeGen/X86/x86-64-asm.ll
+++ b/test/CodeGen/X86/x86-64-asm.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define void @frame_dummy() {
 entry:
-        %tmp1 = tail call void (i8*)* (void (i8*)*)* asm "", "=r,0,~{dirflag},~{fpsr},~{flags}"( void (i8*)* null )           ; <void (i8*)*> [#uses=0]
+        %tmp1 = tail call void (i8*)* (void (i8*)*) asm "", "=r,0,~{dirflag},~{fpsr},~{flags}"( void (i8*)* null )           ; <void (i8*)*> [#uses=0]
         ret void
 }
 
diff --git a/test/CodeGen/X86/x86-64-baseptr.ll b/test/CodeGen/X86/x86-64-baseptr.ll
new file mode 100644
index 000000000000..7fd94fa10f6c
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-baseptr.ll
@@ -0,0 +1,26 @@
+; RUN: llc -mtriple=x86_64-pc-linux -force-align-stack -stack-alignment=32 < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-pc-linux-gnux32 -force-align-stack -stack-alignment=32 < %s | FileCheck -check-prefix=X32ABI %s
+; This should run with NaCl as well ( -mtriple=x86_64-pc-nacl ) but currently doesn't due to PR22655
+
+; Make sure the correct register gets set up as the base pointer
+; This should be rbx for x64 and 64-bit NaCl and ebx for x32
+; CHECK-LABEL: base
+; CHECK: subq $32, %rsp
+; CHECK: movq %rsp, %rbx
+; X32ABI-LABEL: base
+; X32ABI: subl $32, %esp
+; X32ABI: movl %esp, %ebx
+; NACL-LABEL: base
+; NACL: subq $32, %rsp
+; NACL: movq %rsp, %rbx
+
+declare i32 @helper() nounwind
+define void @base() #0 {
+entry:
+  %k = call i32 @helper()
+  %a = alloca i32, i32 %k, align 4
+  store i32 0, i32* %a, align 4
+  ret void
+}
+
+attributes #0 = { nounwind uwtable "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"}
diff --git a/test/CodeGen/X86/x86-64-disp.ll b/test/CodeGen/X86/x86-64-disp.ll
index d8059ebb1c19..790634c1e4a5 100644
--- a/test/CodeGen/X86/x86-64-disp.ll
+++ b/test/CodeGen/X86/x86-64-disp.ll
@@ -8,7 +8,7 @@ target triple = "x86_64-unknown-linux-gnu"
 @call_used_regs = external global [53 x i8], align 32
 
 define fastcc void @foo() nounwind {
-	%t = getelementptr [53 x i8]* @call_used_regs, i64 0, i64 4294967295
+	%t = getelementptr [53 x i8], [53 x i8]* @call_used_regs, i64 0, i64 4294967295
 	store i8 1, i8* %t, align 1
 	ret void
 }
diff --git a/test/CodeGen/X86/x86-64-gv-offset.ll b/test/CodeGen/X86/x86-64-gv-offset.ll
index 365e4af63fc1..f60d2cff3951 100644
--- a/test/CodeGen/X86/x86-64-gv-offset.ll
+++ b/test/CodeGen/X86/x86-64-gv-offset.ll
@@ -5,8 +5,8 @@
 
 define i32 @main() nounwind  {
 entry:
-	%tmp2 = load float* getelementptr (%struct.x* @X, i32 0, i32 0), align 16		; <float> [#uses=1]
-	%tmp4 = load double* getelementptr (%struct.x* @X, i32 0, i32 1), align 8		; <double> [#uses=1]
+	%tmp2 = load float, float* getelementptr (%struct.x, %struct.x* @X, i32 0, i32 0), align 16		; <float> [#uses=1]
+	%tmp4 = load double, double* getelementptr (%struct.x, %struct.x* @X, i32 0, i32 1), align 8		; <double> [#uses=1]
 	tail call void @t( float %tmp2, double %tmp4 ) nounwind 
 	ret i32 0
 }
diff --git a/test/CodeGen/X86/x86-64-jumps.ll b/test/CodeGen/X86/x86-64-jumps.ll
index 11b40c897618..fcb6d9ed592a 100644
--- a/test/CodeGen/X86/x86-64-jumps.ll
+++ b/test/CodeGen/X86/x86-64-jumps.ll
@@ -22,12 +22,12 @@ define void @test2(i32 %i) nounwind ssp {
 entry:
   %i.addr = alloca i32                            ; <i32*> [#uses=2]
   store i32 %i, i32* %i.addr
-  %tmp = load i32* %i.addr                        ; <i32> [#uses=1]
+  %tmp = load i32, i32* %i.addr                        ; <i32> [#uses=1]
   %idxprom = sext i32 %tmp to i64                 ; <i64> [#uses=1]
-  %arrayidx = getelementptr inbounds i32* getelementptr inbounds ([3 x i32]* @test.array, i32 0, i32 0), i64 %idxprom ; <i32*> [#uses=1]
-  %tmp1 = load i32* %arrayidx                     ; <i32> [#uses=1]
+  %arrayidx = getelementptr inbounds i32, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @test.array, i32 0, i32 0), i64 %idxprom ; <i32*> [#uses=1]
+  %tmp1 = load i32, i32* %arrayidx                     ; <i32> [#uses=1]
   %idx.ext = sext i32 %tmp1 to i64                ; <i64> [#uses=1]
-  %add.ptr = getelementptr i8* blockaddress(@test2, %foo), i64 %idx.ext ; <i8*> [#uses=1]
+  %add.ptr = getelementptr i8, i8* blockaddress(@test2, %foo), i64 %idx.ext ; <i8*> [#uses=1]
   br label %indirectgoto
 
 foo:                                              ; preds = %indirectgoto, %indirectgoto, %indirectgoto, %indirectgoto, %indirectgoto
diff --git a/test/CodeGen/X86/x86-64-mem.ll b/test/CodeGen/X86/x86-64-mem.ll
index d15f516cddee..557f9486ad6a 100644
--- a/test/CodeGen/X86/x86-64-mem.ll
+++ b/test/CodeGen/X86/x86-64-mem.ll
@@ -17,18 +17,18 @@
 @bdst = internal global [500000 x i32] zeroinitializer, align 32		; <[500000 x i32]*> [#uses=0]
 
 define void @test1() nounwind {
-	%tmp = load i32* getelementptr ([0 x i32]* @src, i32 0, i32 0)		; <i32> [#uses=1]
-	store i32 %tmp, i32* getelementptr ([0 x i32]* @dst, i32 0, i32 0)
+	%tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @src, i32 0, i32 0)		; <i32> [#uses=1]
+	store i32 %tmp, i32* getelementptr ([0 x i32], [0 x i32]* @dst, i32 0, i32 0)
 	ret void
 }
 
 define void @test2() nounwind {
-	store i32* getelementptr ([0 x i32]* @dst, i32 0, i32 0), i32** @ptr
+	store i32* getelementptr ([0 x i32], [0 x i32]* @dst, i32 0, i32 0), i32** @ptr
 	ret void
 }
 
 define void @test3() nounwind {
-	store i32* getelementptr ([500 x i32]* @ldst, i32 0, i32 0), i32** @lptr
+	store i32* getelementptr ([500 x i32], [500 x i32]* @ldst, i32 0, i32 0), i32** @lptr
 	br label %return
 
 return:		; preds = %0
diff --git a/test/CodeGen/X86/x86-64-pic-4.ll b/test/CodeGen/X86/x86-64-pic-4.ll
index 33b08c4b4b04..42d08cc2057d 100644
--- a/test/CodeGen/X86/x86-64-pic-4.ll
+++ b/test/CodeGen/X86/x86-64-pic-4.ll
@@ -5,6 +5,6 @@
 
 define i32 @get_a() {
 entry:
-	%tmp1 = load i32* @a, align 4
+	%tmp1 = load i32, i32* @a, align 4
 	ret i32 %tmp1
 }
diff --git a/test/CodeGen/X86/x86-64-pic-5.ll b/test/CodeGen/X86/x86-64-pic-5.ll
index 234bc0d2f4f1..d217a5c47dfb 100644
--- a/test/CodeGen/X86/x86-64-pic-5.ll
+++ b/test/CodeGen/X86/x86-64-pic-5.ll
@@ -6,6 +6,6 @@
 
 define i32 @get_a() {
 entry:
-	%tmp1 = load i32* @a, align 4
+	%tmp1 = load i32, i32* @a, align 4
 	ret i32 %tmp1
 }
diff --git a/test/CodeGen/X86/x86-64-pic-6.ll b/test/CodeGen/X86/x86-64-pic-6.ll
index ae5b5835928d..8671023daa8a 100644
--- a/test/CodeGen/X86/x86-64-pic-6.ll
+++ b/test/CodeGen/X86/x86-64-pic-6.ll
@@ -6,6 +6,6 @@
 
 define i32 @get_a() nounwind {
 entry:
-	%tmp1 = load i32* @a, align 4
+	%tmp1 = load i32, i32* @a, align 4
 	ret i32 %tmp1
 }
diff --git a/test/CodeGen/X86/x86-64-psub.ll b/test/CodeGen/X86/x86-64-psub.ll
index 183ddf446f3d..2e39c145919f 100644
--- a/test/CodeGen/X86/x86-64-psub.ll
+++ b/test/CodeGen/X86/x86-64-psub.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=x86_64-pc-linux -mcpu=corei7 < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-pc-linux -mattr=mmx < %s | FileCheck %s
 
 ; MMX packed sub opcodes were wrongly marked as commutative.
 ; This test checks that the operands of packed sub instructions are
diff --git a/test/CodeGen/X86/x86-64-ptr-arg-simple.ll b/test/CodeGen/X86/x86-64-ptr-arg-simple.ll
index 6d466639890b..11dfc802d513 100644
--- a/test/CodeGen/X86/x86-64-ptr-arg-simple.ll
+++ b/test/CodeGen/X86/x86-64-ptr-arg-simple.ll
@@ -22,7 +22,7 @@ entry:
 
 define void @bar(i32* nocapture %pOut, i32* nocapture %pIn) nounwind {
 entry:
-  %0 = load i32* %pIn, align 4
+  %0 = load i32, i32* %pIn, align 4
   store i32 %0, i32* %pOut, align 4
   ret void
 }
diff --git a/test/CodeGen/X86/x86-64-sret-return.ll b/test/CodeGen/X86/x86-64-sret-return.ll
index 2d001142d7a1..a0c43488db1e 100644
--- a/test/CodeGen/X86/x86-64-sret-return.ll
+++ b/test/CodeGen/X86/x86-64-sret-return.ll
@@ -17,42 +17,42 @@ entry:
 	%memtmp = alloca %struct.foo, align 8		; <%struct.foo*> [#uses=1]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store %struct.foo* %d, %struct.foo** %d_addr
-	%tmp = load %struct.foo** %d_addr, align 8		; <%struct.foo*> [#uses=1]
-	%tmp1 = getelementptr %struct.foo* %agg.result, i32 0, i32 0		; <[4 x i64]*> [#uses=4]
-	%tmp2 = getelementptr %struct.foo* %tmp, i32 0, i32 0		; <[4 x i64]*> [#uses=4]
-	%tmp3 = getelementptr [4 x i64]* %tmp1, i32 0, i32 0		; <i64*> [#uses=1]
-	%tmp4 = getelementptr [4 x i64]* %tmp2, i32 0, i32 0		; <i64*> [#uses=1]
-	%tmp5 = load i64* %tmp4, align 8		; <i64> [#uses=1]
+	%tmp = load %struct.foo*, %struct.foo** %d_addr, align 8		; <%struct.foo*> [#uses=1]
+	%tmp1 = getelementptr %struct.foo, %struct.foo* %agg.result, i32 0, i32 0		; <[4 x i64]*> [#uses=4]
+	%tmp2 = getelementptr %struct.foo, %struct.foo* %tmp, i32 0, i32 0		; <[4 x i64]*> [#uses=4]
+	%tmp3 = getelementptr [4 x i64], [4 x i64]* %tmp1, i32 0, i32 0		; <i64*> [#uses=1]
+	%tmp4 = getelementptr [4 x i64], [4 x i64]* %tmp2, i32 0, i32 0		; <i64*> [#uses=1]
+	%tmp5 = load i64, i64* %tmp4, align 8		; <i64> [#uses=1]
 	store i64 %tmp5, i64* %tmp3, align 8
-	%tmp6 = getelementptr [4 x i64]* %tmp1, i32 0, i32 1		; <i64*> [#uses=1]
-	%tmp7 = getelementptr [4 x i64]* %tmp2, i32 0, i32 1		; <i64*> [#uses=1]
-	%tmp8 = load i64* %tmp7, align 8		; <i64> [#uses=1]
+	%tmp6 = getelementptr [4 x i64], [4 x i64]* %tmp1, i32 0, i32 1		; <i64*> [#uses=1]
+	%tmp7 = getelementptr [4 x i64], [4 x i64]* %tmp2, i32 0, i32 1		; <i64*> [#uses=1]
+	%tmp8 = load i64, i64* %tmp7, align 8		; <i64> [#uses=1]
 	store i64 %tmp8, i64* %tmp6, align 8
-	%tmp9 = getelementptr [4 x i64]* %tmp1, i32 0, i32 2		; <i64*> [#uses=1]
-	%tmp10 = getelementptr [4 x i64]* %tmp2, i32 0, i32 2		; <i64*> [#uses=1]
-	%tmp11 = load i64* %tmp10, align 8		; <i64> [#uses=1]
+	%tmp9 = getelementptr [4 x i64], [4 x i64]* %tmp1, i32 0, i32 2		; <i64*> [#uses=1]
+	%tmp10 = getelementptr [4 x i64], [4 x i64]* %tmp2, i32 0, i32 2		; <i64*> [#uses=1]
+	%tmp11 = load i64, i64* %tmp10, align 8		; <i64> [#uses=1]
 	store i64 %tmp11, i64* %tmp9, align 8
-	%tmp12 = getelementptr [4 x i64]* %tmp1, i32 0, i32 3		; <i64*> [#uses=1]
-	%tmp13 = getelementptr [4 x i64]* %tmp2, i32 0, i32 3		; <i64*> [#uses=1]
-	%tmp14 = load i64* %tmp13, align 8		; <i64> [#uses=1]
+	%tmp12 = getelementptr [4 x i64], [4 x i64]* %tmp1, i32 0, i32 3		; <i64*> [#uses=1]
+	%tmp13 = getelementptr [4 x i64], [4 x i64]* %tmp2, i32 0, i32 3		; <i64*> [#uses=1]
+	%tmp14 = load i64, i64* %tmp13, align 8		; <i64> [#uses=1]
 	store i64 %tmp14, i64* %tmp12, align 8
-	%tmp15 = getelementptr %struct.foo* %memtmp, i32 0, i32 0		; <[4 x i64]*> [#uses=4]
-	%tmp16 = getelementptr %struct.foo* %agg.result, i32 0, i32 0		; <[4 x i64]*> [#uses=4]
-	%tmp17 = getelementptr [4 x i64]* %tmp15, i32 0, i32 0		; <i64*> [#uses=1]
-	%tmp18 = getelementptr [4 x i64]* %tmp16, i32 0, i32 0		; <i64*> [#uses=1]
-	%tmp19 = load i64* %tmp18, align 8		; <i64> [#uses=1]
+	%tmp15 = getelementptr %struct.foo, %struct.foo* %memtmp, i32 0, i32 0		; <[4 x i64]*> [#uses=4]
+	%tmp16 = getelementptr %struct.foo, %struct.foo* %agg.result, i32 0, i32 0		; <[4 x i64]*> [#uses=4]
+	%tmp17 = getelementptr [4 x i64], [4 x i64]* %tmp15, i32 0, i32 0		; <i64*> [#uses=1]
+	%tmp18 = getelementptr [4 x i64], [4 x i64]* %tmp16, i32 0, i32 0		; <i64*> [#uses=1]
+	%tmp19 = load i64, i64* %tmp18, align 8		; <i64> [#uses=1]
 	store i64 %tmp19, i64* %tmp17, align 8
-	%tmp20 = getelementptr [4 x i64]* %tmp15, i32 0, i32 1		; <i64*> [#uses=1]
-	%tmp21 = getelementptr [4 x i64]* %tmp16, i32 0, i32 1		; <i64*> [#uses=1]
-	%tmp22 = load i64* %tmp21, align 8		; <i64> [#uses=1]
+	%tmp20 = getelementptr [4 x i64], [4 x i64]* %tmp15, i32 0, i32 1		; <i64*> [#uses=1]
+	%tmp21 = getelementptr [4 x i64], [4 x i64]* %tmp16, i32 0, i32 1		; <i64*> [#uses=1]
+	%tmp22 = load i64, i64* %tmp21, align 8		; <i64> [#uses=1]
 	store i64 %tmp22, i64* %tmp20, align 8
-	%tmp23 = getelementptr [4 x i64]* %tmp15, i32 0, i32 2		; <i64*> [#uses=1]
-	%tmp24 = getelementptr [4 x i64]* %tmp16, i32 0, i32 2		; <i64*> [#uses=1]
-	%tmp25 = load i64* %tmp24, align 8		; <i64> [#uses=1]
+	%tmp23 = getelementptr [4 x i64], [4 x i64]* %tmp15, i32 0, i32 2		; <i64*> [#uses=1]
+	%tmp24 = getelementptr [4 x i64], [4 x i64]* %tmp16, i32 0, i32 2		; <i64*> [#uses=1]
+	%tmp25 = load i64, i64* %tmp24, align 8		; <i64> [#uses=1]
 	store i64 %tmp25, i64* %tmp23, align 8
-	%tmp26 = getelementptr [4 x i64]* %tmp15, i32 0, i32 3		; <i64*> [#uses=1]
-	%tmp27 = getelementptr [4 x i64]* %tmp16, i32 0, i32 3		; <i64*> [#uses=1]
-	%tmp28 = load i64* %tmp27, align 8		; <i64> [#uses=1]
+	%tmp26 = getelementptr [4 x i64], [4 x i64]* %tmp15, i32 0, i32 3		; <i64*> [#uses=1]
+	%tmp27 = getelementptr [4 x i64], [4 x i64]* %tmp16, i32 0, i32 3		; <i64*> [#uses=1]
+	%tmp28 = load i64, i64* %tmp27, align 8		; <i64> [#uses=1]
 	store i64 %tmp28, i64* %tmp26, align 8
 	br label %return
 
diff --git a/test/CodeGen/X86/x86-64-static-relo-movl.ll b/test/CodeGen/X86/x86-64-static-relo-movl.ll
index 71e52bb99191..5da3a4705039 100644
--- a/test/CodeGen/X86/x86-64-static-relo-movl.ll
+++ b/test/CodeGen/X86/x86-64-static-relo-movl.ll
@@ -11,8 +11,8 @@ define void @setup() {
   %pending = alloca %struct.MatchInfo, align 8
   %t = bitcast %struct.MatchInfo* %pending to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %t, i8* bitcast (%struct.MatchInfo* @NO_MATCH to i8*), i64 512, i32 8, i1 false)
-  %u = getelementptr inbounds %struct.MatchInfo* %pending, i32 0, i32 2
-  %v = load i64* %u, align 8
+  %u = getelementptr inbounds %struct.MatchInfo, %struct.MatchInfo* %pending, i32 0, i32 2
+  %v = load i64, i64* %u, align 8
   br label %done
 done:
   ret void
diff --git a/test/CodeGen/X86/x86-64-tls-1.ll b/test/CodeGen/X86/x86-64-tls-1.ll
index 2879fb4e1e74..2c954dbc9c97 100644
--- a/test/CodeGen/X86/x86-64-tls-1.ll
+++ b/test/CodeGen/X86/x86-64-tls-1.ll
@@ -3,7 +3,7 @@
 define i64 @z() nounwind {
 ; CHECK:      movq    $tm_nest_level@TPOFF, %r[[R0:[abcd]]]x
 ; CHECK-NEXT: addl    %fs:0, %e[[R0]]x
-; CHECK-NEXT: andq    $100, %r[[R0]]x
+; CHECK-NEXT: andl    $100, %e[[R0]]x
 
   ret i64 and (i64 ptrtoint (i32* @tm_nest_level to i64), i64 100)
 }
diff --git a/test/CodeGen/X86/x86-64-varargs.ll b/test/CodeGen/X86/x86-64-varargs.ll
index 428f4493b069..ed07bde631dc 100644
--- a/test/CodeGen/X86/x86-64-varargs.ll
+++ b/test/CodeGen/X86/x86-64-varargs.ll
@@ -6,6 +6,6 @@ declare i32 @printf(i8*, ...) nounwind
 
 define i32 @main() nounwind  {
 entry:
-	%tmp10.i = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([26 x i8]* @.str, i32 0, i64 0), i32 12, double 0x3FF3EB8520000000, i32 120, i64 123456677890, i32 -10, double 4.500000e+15 ) nounwind 		; <i32> [#uses=0]
+	%tmp10.i = tail call i32 (i8*, ...) @printf( i8* getelementptr ([26 x i8], [26 x i8]* @.str, i32 0, i64 0), i32 12, double 0x3FF3EB8520000000, i32 120, i64 123456677890, i32 -10, double 4.500000e+15 ) nounwind 		; <i32> [#uses=0]
 	ret i32 0
 }
diff --git a/test/CodeGen/X86/x86-fold-pshufb.ll b/test/CodeGen/X86/x86-fold-pshufb.ll
new file mode 100644
index 000000000000..c29e592bfe83
--- /dev/null
+++ b/test/CodeGen/X86/x86-fold-pshufb.ll
@@ -0,0 +1,17 @@
+; RUN: llc -relocation-model=pic -march=x86-64 -mtriple=x86_64-unknown-unknown -mattr=+ssse3 < %s | FileCheck %s
+
+; Verify that the backend correctly folds the shuffle in function 'fold_pshufb'
+; into a simple load from constant pool.
+
+define <2 x i64> @fold_pshufb() {
+; CHECK-LABEL: fold_pshufb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movaps {{.*#+}} xmm0 = [0,0,0,0,1,0,0,0,2,0,0,0,3,0,0,0]
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 2, i8 0, i8 0, i8 0, i8 3, i8 0, i8 0, i8 0>, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
+  %1 = bitcast <16 x i8> %0 to <2 x i64>
+  ret <2 x i64> %1
+}
+
+declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>)
diff --git a/test/CodeGen/X86/x86-framelowering-trap.ll b/test/CodeGen/X86/x86-framelowering-trap.ll
new file mode 100644
index 000000000000..58a1da23a294
--- /dev/null
+++ b/test/CodeGen/X86/x86-framelowering-trap.ll
@@ -0,0 +1,15 @@
+; RUN: llc %s -o - | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; CHECK-LABEL: bar:
+; CHECK: ud2
+; CHECK-NEXT: retq
+define void @bar() {
+entry:
+  call void @llvm.trap()
+  ret void
+}
+
+; Function Attrs: noreturn nounwind
+declare void @llvm.trap()
diff --git a/test/CodeGen/X86/x86-mixed-alignment-dagcombine.ll b/test/CodeGen/X86/x86-mixed-alignment-dagcombine.ll
index fcf7eaec0544..8892a69abf08 100644
--- a/test/CodeGen/X86/x86-mixed-alignment-dagcombine.ll
+++ b/test/CodeGen/X86/x86-mixed-alignment-dagcombine.ll
@@ -10,8 +10,8 @@ define void @test1(i1 %cmp) align 2 {
   %1 = alloca  <2 x double>, align 16
   %2 = alloca  <2 x double>, align 8
 
-  %val = load <2 x double>* %1, align 16
-  %val2 = load <2 x double>* %2, align 8
+  %val = load <2 x double>, <2 x double>* %1, align 16
+  %val2 = load <2 x double>, <2 x double>* %2, align 8
   %val3 = select i1 %cmp, <2 x double> %val, <2 x double> %val2
   call void @sink(<2 x double> %val3)
   ret void
@@ -24,8 +24,8 @@ define void @test2(i1 %cmp) align 2 {
   %1 = alloca  <2 x double>, align 16
   %2 = alloca  <2 x double>, align 8
 
-  %val = load <2 x double>* %1, align 16
-  %val2 = load <2 x double>* %2, align 16
+  %val = load <2 x double>, <2 x double>* %1, align 16
+  %val2 = load <2 x double>, <2 x double>* %2, align 16
   %val3 = select i1 %cmp, <2 x double> %val, <2 x double> %val2
   call void @sink(<2 x double> %val3)
   ret void
diff --git a/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll b/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll
index 4317d8ab6a26..a2c5b3a6eedf 100644
--- a/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll
+++ b/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll
@@ -72,3 +72,18 @@ define <4 x float> @foo3(<4 x float> %val, <4 x float> %test) nounwind {
   %result = sitofp <4 x i32> %and to <4 x float>
   ret <4 x float> %result
 }
+
+; Test the general purpose constant folding of uint->fp.
+define void @foo4(<4 x float>* noalias %result) nounwind {
+; CHECK-LABEL: LCPI4_0:
+; CHECK-NEXT: .long 1065353216              ## float 1.000000e+00
+; CHECK-NEXT: .long 1123942400              ## float 1.270000e+02
+; CHECK-NEXT: .long 1124073472              ## float 1.280000e+02
+; CHECK-NEXT: .long 1132396544              ## float 2.550000e+02
+; CHECK-LABEL: foo4:
+; CHECK:  movaps LCPI4_0(%rip), %xmm0
+
+  %val = uitofp <4 x i8> <i8 1, i8 127, i8 -128, i8 -1> to <4 x float>
+  store <4 x float> %val, <4 x float>* %result
+  ret void
+}
diff --git a/test/CodeGen/X86/x86-shifts.ll b/test/CodeGen/X86/x86-shifts.ll
index ec479330ed6b..0cbfab148bb5 100644
--- a/test/CodeGen/X86/x86-shifts.ll
+++ b/test/CodeGen/X86/x86-shifts.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse2 | FileCheck %s
 
 ; Splat patterns below
 
@@ -118,10 +118,16 @@ entry:
 
 define <2 x i64> @shr2_nosplat(<2 x i64> %A) nounwind {
 entry:
-; CHECK: shr2_nosplat
-; CHECK-NOT:  psrlq
-; CHECK-NOT:  psrlq
-; CHECK:      ret
+; CHECK-LABEL: shr2_nosplat
+; CHECK:       movdqa %xmm0, %xmm1
+; CHECK-NEXT:  psrlq  $1, %xmm1
+; CHECK-NEXT:  movdqa %xmm0, %xmm2
+; CHECK-NEXT:  psrlq  $8, %xmm2
+; CHECK-NEXT:  movsd  {{.*#+}} xmm0 = xmm1[0],xmm0[1]
+; CHECK-NEXT:  movsd  {{.*#+}} xmm1 = xmm2[0],xmm1[1]
+; CHECK-NEXT:  xorpd  %xmm0, %xmm1
+; CHECK-NEXT:  movapd %xmm1, %xmm0
+; CHECK-NEXT:  ret
   %B = lshr <2 x i64> %A,  < i64 8, i64 1>
   %C = lshr <2 x i64> %A,  < i64 1, i64 0>
   %K = xor <2 x i64> %B, %C
diff --git a/test/CodeGen/X86/x86-shrink-wrapping.ll b/test/CodeGen/X86/x86-shrink-wrapping.ll
new file mode 100644
index 000000000000..5848eddf4375
--- /dev/null
+++ b/test/CodeGen/X86/x86-shrink-wrapping.ll
@@ -0,0 +1,600 @@
+; RUN: llc %s -o - -enable-shrink-wrap=true | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
+; RUN: llc %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
+;
+; Note: Lots of tests use inline asm instead of regular calls.
+; This allows to have a better control on what the allocation will do.
+; Otherwise, we may have spill right in the entry block, defeating
+; shrink-wrapping. Moreover, some of the inline asm statement (nop)
+; are here to ensure that the related paths do not end up as critical
+; edges.
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "x86_64-apple-macosx"
+
+
+; Initial motivating example: Simple diamond with a call just on one side.
+; CHECK-LABEL: foo:
+;
+; Compare the arguments and jump to exit.
+; No prologue needed.
+; ENABLE: movl %edi, [[ARG0CPY:%e[a-z]+]]
+; ENABLE-NEXT: cmpl %esi, [[ARG0CPY]]
+; ENABLE-NEXT: jge [[EXIT_LABEL:LBB[0-9_]+]]
+;
+; Prologue code.
+; (What we push does not matter. It should be some random sratch register.)
+; CHECK: pushq
+;
+; Compare the arguments and jump to exit.
+; After the prologue is set.
+; DISABLE: movl %edi, [[ARG0CPY:%e[a-z]+]]
+; DISABLE-NEXT: cmpl %esi, [[ARG0CPY]]
+; DISABLE-NEXT: jge [[EXIT_LABEL:LBB[0-9_]+]]
+;
+; Store %a in the alloca.
+; CHECK: movl [[ARG0CPY]], 4(%rsp)
+; Set the alloca address in the second argument.
+; CHECK-NEXT: leaq 4(%rsp), %rsi
+; Set the first argument to zero.
+; CHECK-NEXT: xorl %edi, %edi
+; CHECK-NEXT: callq _doSomething
+;
+; With shrink-wrapping, epilogue is just after the call.
+; ENABLE-NEXT: addq $8, %rsp
+;
+; CHECK: [[EXIT_LABEL]]:
+;
+; Without shrink-wrapping, epilogue is in the exit block.
+; Epilogue code. (What we pop does not matter.)
+; DISABLE-NEXT: popq
+;
+; CHECK-NEXT: retq
+define i32 @foo(i32 %a, i32 %b) {
+  %tmp = alloca i32, align 4
+  %tmp2 = icmp slt i32 %a, %b
+  br i1 %tmp2, label %true, label %false
+
+true:
+  store i32 %a, i32* %tmp, align 4
+  %tmp4 = call i32 @doSomething(i32 0, i32* %tmp)
+  br label %false
+
+false:
+  %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
+  ret i32 %tmp.0
+}
+
+; Function Attrs: optsize
+declare i32 @doSomething(i32, i32*)
+
+
+; Check that we do not perform the restore inside the loop whereas the save
+; is outside.
+; CHECK-LABEL: freqSaveAndRestoreOutsideLoop:
+;
+; Shrink-wrapping allows to skip the prologue in the else case.
+; ENABLE: testl %edi, %edi  
+; ENABLE: je [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; Prologue code.
+; Make sure we save the CSR used in the inline asm: rbx.
+; CHECK: pushq %rbx
+;
+; DISABLE: testl %edi, %edi
+; DISABLE: je [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; SUM is in %esi because it is coalesced with the second
+; argument on the else path.
+; CHECK: xorl [[SUM:%esi]], [[SUM]]
+; CHECK-NEXT: movl $10, [[IV:%e[a-z]+]]
+;
+; Next BB.
+; CHECK: [[LOOP:LBB[0-9_]+]]: ## %for.body
+; CHECK: movl $1, [[TMP:%e[a-z]+]]
+; CHECK: addl [[TMP]], [[SUM]]
+; CHECK-NEXT: decl [[IV]]
+; CHECK-NEXT: jne [[LOOP]]
+;
+; Next BB.
+; SUM << 3.
+; CHECK: shll $3, [[SUM]]
+;
+; Jump to epilogue.
+; DISABLE: jmp [[EPILOG_BB:LBB[0-9_]+]]
+;
+; DISABLE: [[ELSE_LABEL]]: ## %if.else
+; Shift second argument by one and store into returned register.
+; DISABLE: addl %esi, %esi
+; DISABLE: [[EPILOG_BB]]: ## %if.end
+;
+; Epilogue code.
+; CHECK-DAG: popq %rbx
+; CHECK-DAG: movl %esi, %eax
+; CHECK: retq
+;
+; ENABLE: [[ELSE_LABEL]]: ## %if.else
+; Shift second argument by one and store into returned register.
+; ENABLE: addl %esi, %esi
+; ENABLE-NEXT: movl %esi, %eax
+; ENABLE-NEXT: retq
+define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) {
+entry:
+  %tobool = icmp eq i32 %cond, 0
+  br i1 %tobool, label %if.else, label %for.preheader
+
+for.preheader:
+  tail call void asm "nop", ""()
+  br label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
+  %sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ]
+  %call = tail call i32 asm "movl $$1, $0", "=r,~{ebx}"()
+  %add = add nsw i32 %call, %sum.04
+  %inc = add nuw nsw i32 %i.05, 1
+  %exitcond = icmp eq i32 %inc, 10
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  %shl = shl i32 %add, 3
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  %mul = shl nsw i32 %N, 1
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %for.end
+  %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
+  ret i32 %sum.1
+}
+
+declare i32 @something(...)
+
+; Check that we do not perform the shrink-wrapping inside the loop even
+; though that would be legal. The cost model must prevent that.
+; CHECK-LABEL: freqSaveAndRestoreOutsideLoop2:
+; Prologue code.
+; Make sure we save the CSR used in the inline asm: rbx.
+; CHECK: pushq %rbx
+; CHECK: nop
+; CHECK: xorl [[SUM:%e[a-z]+]], [[SUM]]
+; CHECK-NEXT: movl $10, [[IV:%e[a-z]+]]
+; Next BB.
+; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ## %for.body
+; CHECK: movl $1, [[TMP:%e[a-z]+]]
+; CHECK: addl [[TMP]], [[SUM]]
+; CHECK-NEXT: decl [[IV]]
+; CHECK-NEXT: jne [[LOOP_LABEL]]
+; Next BB.
+; CHECK: ## %for.exit
+; CHECK: nop
+; CHECK: popq %rbx
+; CHECK-NEXT: retq
+define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {
+entry:
+  br label %for.preheader
+
+for.preheader:
+  tail call void asm "nop", ""()
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.04 = phi i32 [ 0, %for.preheader ], [ %inc, %for.body ]
+  %sum.03 = phi i32 [ 0, %for.preheader ], [ %add, %for.body ]
+  %call = tail call i32 asm "movl $$1, $0", "=r,~{ebx}"()
+  %add = add nsw i32 %call, %sum.03
+  %inc = add nuw nsw i32 %i.04, 1
+  %exitcond = icmp eq i32 %inc, 10
+  br i1 %exitcond, label %for.exit, label %for.body
+
+for.exit:
+  tail call void asm "nop", ""()
+  br label %for.end
+
+for.end:                                          ; preds = %for.body
+  ret i32 %add
+}
+
+; Check with a more complex case that we do not have save within the loop and
+; restore outside.
+; CHECK-LABEL: loopInfoSaveOutsideLoop:
+;
+; ENABLE: testl %edi, %edi
+; ENABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; Prologue code.
+; Make sure we save the CSR used in the inline asm: rbx.
+; CHECK: pushq %rbx
+;
+; DISABLE: testl %edi, %edi
+; DISABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; CHECK: nop
+; CHECK: xorl [[SUM:%esi]], [[SUM]]
+; CHECK-NEXT: movl $10, [[IV:%e[a-z]+]]
+;
+; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ## %for.body
+; CHECK: movl $1, [[TMP:%e[a-z]+]]
+; CHECK: addl [[TMP]], [[SUM]]
+; CHECK-NEXT: decl [[IV]]
+; CHECK-NEXT: jne [[LOOP_LABEL]]
+; Next BB.
+; CHECK: nop
+; CHECK: shll $3, [[SUM]]
+;
+; DISABLE: jmp [[EPILOG_BB:LBB[0-9_]+]]
+;
+; DISABLE: [[ELSE_LABEL]]: ## %if.else
+; Shift second argument by one and store into returned register.
+; DISABLE: addl %esi, %esi
+; DISABLE: [[EPILOG_BB]]: ## %if.end
+;
+; Epilogue code.
+; CHECK-DAG: popq %rbx
+; CHECK-DAG: movl %esi, %eax
+; CHECK: retq
+;
+; ENABLE: [[ELSE_LABEL]]: ## %if.else
+; Shift second argument by one and store into returned register.
+; ENABLE: addl %esi, %esi
+; ENABLE-NEXT: movl %esi, %eax
+; ENABLE-NEXT: retq
+define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) {
+entry:
+  %tobool = icmp eq i32 %cond, 0
+  br i1 %tobool, label %if.else, label %for.preheader
+
+for.preheader:
+  tail call void asm "nop", ""()
+  br label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
+  %sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ]
+  %call = tail call i32 asm "movl $$1, $0", "=r,~{ebx}"()
+  %add = add nsw i32 %call, %sum.04
+  %inc = add nuw nsw i32 %i.05, 1
+  %exitcond = icmp eq i32 %inc, 10
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  tail call void asm "nop", "~{ebx}"()
+  %shl = shl i32 %add, 3
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  %mul = shl nsw i32 %N, 1
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %for.end
+  %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
+  ret i32 %sum.1
+}
+
+declare void @somethingElse(...)
+
+; Check with a more complex case that we do not have restore within the loop and
+; save outside.
+; CHECK-LABEL: loopInfoRestoreOutsideLoop:
+;
+; ENABLE: testl %edi, %edi
+; ENABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; Prologue code.
+; Make sure we save the CSR used in the inline asm: rbx.
+; CHECK: pushq %rbx
+;
+; DISABLE: testl %edi, %edi
+; DISABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; CHECK: nop
+; CHECK: xorl [[SUM:%esi]], [[SUM]]
+; CHECK-NEXT: movl $10, [[IV:%e[a-z]+]]
+;
+; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ## %for.body
+; CHECK: movl $1, [[TMP:%e[a-z]+]]
+; CHECK: addl [[TMP]], [[SUM]]
+; CHECK-NEXT: decl [[IV]]
+; CHECK-NEXT: jne [[LOOP_LABEL]]
+; Next BB.
+; CHECK: shll $3, [[SUM]]
+;
+; DISABLE: jmp [[EPILOG_BB:LBB[0-9_]+]]
+;
+; DISABLE: [[ELSE_LABEL]]: ## %if.else
+
+; Shift second argument by one and store into returned register.
+; DISABLE: addl %esi, %esi
+; DISABLE: [[EPILOG_BB]]: ## %if.end
+;
+; Epilogue code.
+; CHECK-DAG: popq %rbx
+; CHECK-DAG: movl %esi, %eax
+; CHECK: retq
+;
+; ENABLE: [[ELSE_LABEL]]: ## %if.else
+; Shift second argument by one and store into returned register.
+; ENABLE: addl %esi, %esi
+; ENABLE-NEXT: movl %esi, %eax
+; ENABLE-NEXT: retq
+define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) #0 {
+entry:
+  %tobool = icmp eq i32 %cond, 0
+  br i1 %tobool, label %if.else, label %if.then
+
+if.then:                                          ; preds = %entry
+  tail call void asm "nop", "~{ebx}"()
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %if.then
+  %i.05 = phi i32 [ 0, %if.then ], [ %inc, %for.body ]
+  %sum.04 = phi i32 [ 0, %if.then ], [ %add, %for.body ]
+  %call = tail call i32 asm "movl $$1, $0", "=r,~{ebx}"()
+  %add = add nsw i32 %call, %sum.04
+  %inc = add nuw nsw i32 %i.05, 1
+  %exitcond = icmp eq i32 %inc, 10
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  %shl = shl i32 %add, 3
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  %mul = shl nsw i32 %N, 1
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %for.end
+  %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
+  ret i32 %sum.1
+}
+
+; Check that we handle function with no frame information correctly.
+; CHECK-LABEL: emptyFrame:
+; CHECK: ## %entry
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retq
+define i32 @emptyFrame() {
+entry:
+  ret i32 0
+}
+
+; Check that we handle inline asm correctly.
+; CHECK-LABEL: inlineAsm:
+;
+; ENABLE: testl %edi, %edi
+; ENABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; Prologue code.
+; Make sure we save the CSR used in the inline asm: rbx.
+; CHECK: pushq %rbx
+;
+; DISABLE: testl %edi, %edi
+; DISABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; CHECK: nop
+; CHECK: movl $10, [[IV:%e[a-z]+]]
+;
+; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ## %for.body
+; Inline asm statement.
+; CHECK: addl $1, %ebx
+; CHECK: decl [[IV]]
+; CHECK-NEXT: jne [[LOOP_LABEL]]
+; Next BB.
+; CHECK: nop
+; CHECK: xorl %esi, %esi
+;
+; DISABLE: jmp [[EPILOG_BB:LBB[0-9_]+]]
+;
+; DISABLE: [[ELSE_LABEL]]: ## %if.else
+; Shift second argument by one and store into returned register.
+; DISABLE: addl %esi, %esi
+; DISABLE: [[EPILOG_BB]]: ## %if.end
+;
+; Epilogue code.
+; CHECK-DAG: popq %rbx
+; CHECK-DAG: movl %esi, %eax
+; CHECK: retq
+;
+; ENABLE: [[ELSE_LABEL]]: ## %if.else
+; Shift second argument by one and store into returned register.
+; ENABLE: addl %esi, %esi
+; ENABLE-NEXT: movl %esi, %eax
+; ENABLE-NEXT: retq
+define i32 @inlineAsm(i32 %cond, i32 %N) {
+entry:
+  %tobool = icmp eq i32 %cond, 0
+  br i1 %tobool, label %if.else, label %for.preheader
+
+for.preheader:
+  tail call void asm "nop", ""()
+  br label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %i.03 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
+  tail call void asm "addl $$1, %ebx", "~{ebx}"()
+  %inc = add nuw nsw i32 %i.03, 1
+  %exitcond = icmp eq i32 %inc, 10
+  br i1 %exitcond, label %for.exit, label %for.body
+
+for.exit:
+  tail call void asm "nop", ""()
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  %mul = shl nsw i32 %N, 1
+  br label %if.end
+
+if.end:                                           ; preds = %for.body, %if.else
+  %sum.0 = phi i32 [ %mul, %if.else ], [ 0, %for.exit ]
+  ret i32 %sum.0
+}
+
+; Check that we handle calls to variadic functions correctly.
+; CHECK-LABEL: callVariadicFunc:
+;
+; ENABLE: testl %edi, %edi
+; ENABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; Prologue code.
+; CHECK: pushq
+;
+; DISABLE: testl %edi, %edi
+; DISABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
+;
+; Setup of the varags.
+; CHECK: movl %esi, (%rsp)
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: %esi, %edi
+; CHECK-NEXT: %esi, %edx
+; CHECK-NEXT: %esi, %r8d
+; CHECK-NEXT: %esi, %r9d
+; CHECK-NEXT: %esi, %ecx
+; CHECK-NEXT: callq _someVariadicFunc
+; CHECK-NEXT: movl %eax, %esi
+; CHECK-NEXT: shll $3, %esi
+;
+; ENABLE-NEXT: addq $8, %rsp
+; ENABLE-NEXT: movl %esi, %eax
+; ENABLE-NEXT: retq
+;
+; DISABLE: jmp [[IFEND_LABEL:LBB[0-9_]+]]
+;
+; CHECK: [[ELSE_LABEL]]: ## %if.else
+; Shift second argument by one and store into returned register.
+; CHECK: addl %esi, %esi
+;
+; DISABLE: [[IFEND_LABEL]]: ## %if.end
+;
+; Epilogue code.
+; CHECK-NEXT: movl %esi, %eax
+; DISABLE-NEXT: popq
+; CHECK-NEXT: retq
+define i32 @callVariadicFunc(i32 %cond, i32 %N) {
+entry:
+  %tobool = icmp eq i32 %cond, 0
+  br i1 %tobool, label %if.else, label %if.then
+
+if.then:                                          ; preds = %entry
+  %call = tail call i32 (i32, ...) @someVariadicFunc(i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N)
+  %shl = shl i32 %call, 3
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  %mul = shl nsw i32 %N, 1
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  %sum.0 = phi i32 [ %shl, %if.then ], [ %mul, %if.else ]
+  ret i32 %sum.0
+}
+
+declare i32 @someVariadicFunc(i32, ...)
+
+; Check that we use LEA not to clobber EFLAGS.
+%struct.temp_slot = type { %struct.temp_slot*, %struct.rtx_def*, %struct.rtx_def*, i32, i64, %union.tree_node*, %union.tree_node*, i8, i8, i32, i32, i64, i64 }
+%union.tree_node = type { %struct.tree_decl }
+%struct.tree_decl = type { %struct.tree_common, i8*, i32, i32, %union.tree_node*, i48, %union.anon, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %struct.rtx_def*, %struct.rtx_def*, %union.anon.1, %union.tree_node*, %union.tree_node*, %union.tree_node*, i64, %struct.lang_decl* }
+%struct.tree_common = type { %union.tree_node*, %union.tree_node*, i32 }
+%union.anon = type { i64 }
+%union.anon.1 = type { %struct.function* }
+%struct.function = type { %struct.eh_status*, %struct.stmt_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, i8*, %union.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.ix86_args, %struct.rtx_def*, %struct.rtx_def*, i8*, %struct.initial_value_struct*, i32, %union.tree_node*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %union.tree_node*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i64, %union.tree_node*, %union.tree_node*, %struct.rtx_def*, %struct.rtx_def*, i32, %struct.rtx_def**, %struct.temp_slot*, i32, i32, i32, %struct.var_refs_queue*, i32, i32, i8*, %union.tree_node*, %struct.rtx_def*, i32, i32, %struct.machine_function*, i32, i32, %struct.language_function*, %struct.rtx_def*, i24 }
+%struct.eh_status = type opaque
+%struct.stmt_status = type opaque
+%struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
+%struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %union.tree_node*, %struct.sequence_stack*, i32, i32, i8*, i32, i8*, %union.tree_node**, %struct.rtx_def** }
+%struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %union.tree_node*, %struct.sequence_stack* }
+%struct.varasm_status = type opaque
+%struct.ix86_args = type { i32, i32, i32, i32, i32, i32, i32 }
+%struct.initial_value_struct = type opaque
+%struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
+%struct.machine_function = type opaque
+%struct.language_function = type opaque
+%struct.lang_decl = type opaque
+%struct.rtx_def = type { i32, [1 x %union.rtunion_def] }
+%union.rtunion_def = type { i64 }
+
+declare hidden fastcc %struct.temp_slot* @find_temp_slot_from_address(%struct.rtx_def* readonly)
+
+; CHECK-LABEL: useLEA:
+; DISABLE: pushq 
+;
+; CHECK: testq   %rdi, %rdi
+; CHECK-NEXT: je      [[CLEANUP:LBB[0-9_]+]]
+;
+; CHECK: movzwl  (%rdi), [[BF_LOAD:%e[a-z]+]]
+; CHECK-NEXT: cmpl $66, [[BF_LOAD]]
+; CHECK-NEXT: jne [[CLEANUP]]
+;
+; CHECK: movq 8(%rdi), %rdi
+; CHECK-NEXT: movzwl (%rdi), %e[[BF_LOAD2:[a-z]+]]
+; CHECK-NEXT: leal -54(%r[[BF_LOAD2]]), [[TMP:%e[a-z]+]]
+; CHECK-NEXT: cmpl $14, [[TMP]]
+; CHECK-NEXT: ja [[LOR_LHS_FALSE:LBB[0-9_]+]]
+;
+; CHECK: movl $24599, [[TMP2:%e[a-z]+]]
+; CHECK-NEXT: btl [[TMP]], [[TMP2]]
+; CHECK-NEXT: jb [[CLEANUP]]
+;
+; CHECK: [[LOR_LHS_FALSE]]: ## %lor.lhs.false
+; CHECK: cmpl $134, %e[[BF_LOAD2]]
+; CHECK-NEXT: je [[CLEANUP]]
+;
+; CHECK: cmpl $140, %e[[BF_LOAD2]]
+; CHECK-NEXT: je [[CLEANUP]]
+;
+; ENABLE: pushq
+; CHECK: callq _find_temp_slot_from_address
+; CHECK-NEXT: testq   %rax, %rax
+;
+; The adjustment must use LEA here (or be moved above the test).
+; ENABLE-NEXT: leaq 8(%rsp), %rsp
+;
+; CHECK-NEXT: je [[CLEANUP]]
+;
+; CHECK: movb $1, 57(%rax)
+;
+; CHECK: [[CLEANUP]]: ## %cleanup
+; DISABLE: popq
+; CHECK-NEXT: retq
+define void @useLEA(%struct.rtx_def* readonly %x) {
+entry:
+  %cmp = icmp eq %struct.rtx_def* %x, null
+  br i1 %cmp, label %cleanup, label %if.end
+
+if.end:                                           ; preds = %entry
+  %tmp = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %x, i64 0, i32 0
+  %bf.load = load i32, i32* %tmp, align 8
+  %bf.clear = and i32 %bf.load, 65535
+  %cmp1 = icmp eq i32 %bf.clear, 66
+  br i1 %cmp1, label %lor.lhs.false, label %cleanup
+
+lor.lhs.false:                                    ; preds = %if.end
+  %arrayidx = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %x, i64 0, i32 1, i64 0
+  %rtx = bitcast %union.rtunion_def* %arrayidx to %struct.rtx_def**
+  %tmp1 = load %struct.rtx_def*, %struct.rtx_def** %rtx, align 8
+  %tmp2 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %tmp1, i64 0, i32 0
+  %bf.load2 = load i32, i32* %tmp2, align 8
+  %bf.clear3 = and i32 %bf.load2, 65535
+  switch i32 %bf.clear3, label %if.end.55 [
+    i32 67, label %cleanup
+    i32 68, label %cleanup
+    i32 54, label %cleanup
+    i32 55, label %cleanup
+    i32 58, label %cleanup
+    i32 134, label %cleanup
+    i32 56, label %cleanup
+    i32 140, label %cleanup
+  ]
+
+if.end.55:                                        ; preds = %lor.lhs.false
+  %call = tail call fastcc %struct.temp_slot* @find_temp_slot_from_address(%struct.rtx_def* %tmp1) #2
+  %cmp59 = icmp eq %struct.temp_slot* %call, null
+  br i1 %cmp59, label %cleanup, label %if.then.60
+
+if.then.60:                                       ; preds = %if.end.55
+  %addr_taken = getelementptr inbounds %struct.temp_slot, %struct.temp_slot* %call, i64 0, i32 8
+  store i8 1, i8* %addr_taken, align 1
+  br label %cleanup
+
+cleanup:                                          ; preds = %if.then.60, %if.end.55, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %if.end, %entry
+  ret void
+}
diff --git a/test/CodeGen/X86/x86-upgrade-avx2-vbroadcast.ll b/test/CodeGen/X86/x86-upgrade-avx2-vbroadcast.ll
new file mode 100644
index 000000000000..d4813ea47a3d
--- /dev/null
+++ b/test/CodeGen/X86/x86-upgrade-avx2-vbroadcast.ll
@@ -0,0 +1,18 @@
+; RUN: llc -mattr=+avx2 < %s | FileCheck %s
+
+; Check that we properly upgrade the AVX2 vbroadcast intrinsic to IR.
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+define <4 x i64> @broadcast128(<2 x i64> %src) {
+  ; CHECK-LABEL: broadcast128
+  ; CHECK:       vinsertf128 $1, %xmm0, %ymm0, %ymm0
+  %1 = alloca <2 x i64>, align 16
+  %2 = bitcast <2 x i64>* %1 to i8*
+  store <2 x i64> %src, <2 x i64>* %1, align 16
+  %3 = call <4 x i64> @llvm.x86.avx2.vbroadcasti128(i8* %2)
+  ret <4 x i64> %3
+}
+
+declare <4 x i64> @llvm.x86.avx2.vbroadcasti128(i8*) #1
diff --git a/test/CodeGen/X86/xaluo.ll b/test/CodeGen/X86/xaluo.ll
index 668628c69ede..7c4b60d264c9 100644
--- a/test/CodeGen/X86/xaluo.ll
+++ b/test/CodeGen/X86/xaluo.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=x86_64-darwin-unknown                             < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
-; RUN: llc -mtriple=x86_64-darwin-unknown -fast-isel -fast-isel-abort < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
+; RUN: llc -mtriple=x86_64-darwin-unknown -fast-isel -fast-isel-abort=1 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
 
 ;
 ; Get the actual value of the overflow bit.
diff --git a/test/CodeGen/X86/xmulo.ll b/test/CodeGen/X86/xmulo.ll
index 71efac4e99a1..825efa6361b5 100644
--- a/test/CodeGen/X86/xmulo.ll
+++ b/test/CodeGen/X86/xmulo.ll
@@ -17,7 +17,7 @@ define i32 @t1() nounwind {
     %2 = extractvalue {i64, i1} %1, 0
     %3 = extractvalue {i64, i1} %1, 1
     %4 = zext i1 %3 to i32
-    %5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i32 0, i32 0), i64 %2, i32 %4)
+    %5 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str, i32 0, i32 0), i64 %2, i32 %4)
     ret i32 0
 }
 
@@ -31,7 +31,7 @@ define i32 @t2() nounwind {
     %2 = extractvalue {i64, i1} %1, 0
     %3 = extractvalue {i64, i1} %1, 1
     %4 = zext i1 %3 to i32
-    %5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i32 0, i32 0), i64 %2, i32 %4)
+    %5 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str, i32 0, i32 0), i64 %2, i32 %4)
     ret i32 0
 }
 
@@ -45,6 +45,6 @@ define i32 @t3() nounwind {
     %2 = extractvalue {i64, i1} %1, 0
     %3 = extractvalue {i64, i1} %1, 1
     %4 = zext i1 %3 to i32
-    %5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i32 0, i32 0), i64 %2, i32 %4)
+    %5 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str, i32 0, i32 0), i64 %2, i32 %4)
     ret i32 0
 }
diff --git a/test/CodeGen/X86/xop-intrinsics-x86_64.ll b/test/CodeGen/X86/xop-intrinsics-x86_64.ll
index 8af782cd2f19..2516116f7697 100644
--- a/test/CodeGen/X86/xop-intrinsics-x86_64.ll
+++ b/test/CodeGen/X86/xop-intrinsics-x86_64.ll
@@ -8,14 +8,14 @@ define <2 x double> @test_int_x86_xop_vpermil2pd(<2 x double> %a0, <2 x double>
 define <2 x double> @test_int_x86_xop_vpermil2pd_mr(<2 x double> %a0, <2 x double>* %a1, <2 x double> %a2) {
   ; CHECK-NOT: vmovaps
   ; CHECK: vpermil2pd
-  %vec = load <2 x double>* %a1
+  %vec = load <2 x double>, <2 x double>* %a1
   %res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %vec, <2 x double> %a2, i8 1) ;  [#uses=1]
   ret <2 x double> %res
 }
 define <2 x double> @test_int_x86_xop_vpermil2pd_rm(<2 x double> %a0, <2 x double> %a1, <2 x double>* %a2) {
   ; CHECK-NOT: vmovaps
   ; CHECK: vpermil2pd
-  %vec = load <2 x double>* %a2
+  %vec = load <2 x double>, <2 x double>* %a2
   %res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %vec, i8 1) ;  [#uses=1]
   ret <2 x double> %res
 }
@@ -31,7 +31,7 @@ define <4 x double> @test_int_x86_xop_vpermil2pd_256_mr(<4 x double> %a0, <4 x d
   ; CHECK-NOT: vmovaps
   ; CHECK: vpermil2pd
   ; CHECK: ymm
-  %vec = load <4 x double>* %a1
+  %vec = load <4 x double>, <4 x double>* %a1
   %res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %vec, <4 x double> %a2, i8 2) ;
   ret <4 x double> %res
 }
@@ -39,7 +39,7 @@ define <4 x double> @test_int_x86_xop_vpermil2pd_256_rm(<4 x double> %a0, <4 x d
   ; CHECK-NOT: vmovaps
   ; CHECK: vpermil2pd
   ; CHECK: ymm
-  %vec = load <4 x double>* %a2
+  %vec = load <4 x double>, <4 x double>* %a2
   %res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %vec, i8 2) ;
   ret <4 x double> %res
 }
@@ -77,7 +77,7 @@ define <4 x i64> @test_int_x86_xop_vpcmov_256_mr(<4 x i64> %a0, <4 x i64>* %a1,
   ; CHECK-NOT: vmovaps
   ; CHECK: vpcmov
   ; CHECK: ymm
-  %vec = load <4 x i64>* %a1
+  %vec = load <4 x i64>, <4 x i64>* %a1
   %res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %vec, <4 x i64> %a2) ;
   ret <4 x i64> %res
 }
@@ -85,462 +85,462 @@ define <4 x i64> @test_int_x86_xop_vpcmov_256_rm(<4 x i64> %a0, <4 x i64> %a1, <
   ; CHECK-NOT: vmovaps
   ; CHECK: vpcmov
   ; CHECK: ymm
- %vec = load <4 x i64>* %a2
+ %vec = load <4 x i64>, <4 x i64>* %a2
  %res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %vec) ;
   ret <4 x i64> %res
 }
 declare <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64>, <4 x i64>, <4 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomeqb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK:vpcomb
+  ; CHECK:vpcomeqb
   %res = call <16 x i8> @llvm.x86.xop.vpcomeqb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 define <16 x i8> @test_int_x86_xop_vpcomeqb_mem(<16 x i8> %a0, <16 x i8>* %a1) {
   ; CHECK-NOT: vmovaps
-  ; CHECK:vpcomb
-  %vec = load <16 x i8>* %a1
+  ; CHECK:vpcomeqb
+  %vec = load <16 x i8>, <16 x i8>* %a1
   %res = call <16 x i8> @llvm.x86.xop.vpcomeqb(<16 x i8> %a0, <16 x i8> %vec) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomeqb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomeqw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomw
+  ; CHECK: vpcomeqw
   %res = call <8 x i16> @llvm.x86.xop.vpcomeqw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomeqw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomeqd(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomd
+  ; CHECK: vpcomeqd
   %res = call <4 x i32> @llvm.x86.xop.vpcomeqd(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomeqd(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomeqq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomq
+  ; CHECK: vpcomeqq
   %res = call <2 x i64> @llvm.x86.xop.vpcomeqq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomeqq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomequb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomub
+  ; CHECK: vpcomequb
   %res = call <16 x i8> @llvm.x86.xop.vpcomequb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomequb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomequd(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomud
+  ; CHECK: vpcomequd
   %res = call <4 x i32> @llvm.x86.xop.vpcomequd(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomequd(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomequq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomuq
+  ; CHECK: vpcomequq
   %res = call <2 x i64> @llvm.x86.xop.vpcomequq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomequq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomequw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomuw
+  ; CHECK: vpcomequw
   %res = call <8 x i16> @llvm.x86.xop.vpcomequw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomequw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomfalseb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomb
+  ; CHECK: vpcomfalseb
   %res = call <16 x i8> @llvm.x86.xop.vpcomfalseb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomfalseb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomfalsed(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomd
+  ; CHECK: vpcomfalsed
   %res = call <4 x i32> @llvm.x86.xop.vpcomfalsed(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomfalsed(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomfalseq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomq
+  ; CHECK: vpcomfalseq
   %res = call <2 x i64> @llvm.x86.xop.vpcomfalseq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomfalseq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomfalseub(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomub
+  ; CHECK: vpcomfalseub
   %res = call <16 x i8> @llvm.x86.xop.vpcomfalseub(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomfalseub(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomfalseud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomud
+  ; CHECK: vpcomfalseud
   %res = call <4 x i32> @llvm.x86.xop.vpcomfalseud(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomfalseud(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomfalseuq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomuq
+  ; CHECK: vpcomfalseuq
   %res = call <2 x i64> @llvm.x86.xop.vpcomfalseuq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomfalseuq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomfalseuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomuw
+  ; CHECK: vpcomfalseuw
   %res = call <8 x i16> @llvm.x86.xop.vpcomfalseuw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomfalseuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomfalsew(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomw
+  ; CHECK: vpcomfalsew
   %res = call <8 x i16> @llvm.x86.xop.vpcomfalsew(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomfalsew(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomgeb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomb
+  ; CHECK: vpcomgeb
   %res = call <16 x i8> @llvm.x86.xop.vpcomgeb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomgeb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomged(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomd
+  ; CHECK: vpcomged
   %res = call <4 x i32> @llvm.x86.xop.vpcomged(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomged(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomgeq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomq
+  ; CHECK: vpcomgeq
   %res = call <2 x i64> @llvm.x86.xop.vpcomgeq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomgeq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomgeub(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomub
+  ; CHECK: vpcomgeub
   %res = call <16 x i8> @llvm.x86.xop.vpcomgeub(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomgeub(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomgeud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomud
+  ; CHECK: vpcomgeud
   %res = call <4 x i32> @llvm.x86.xop.vpcomgeud(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomgeud(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomgeuq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomuq
+  ; CHECK: vpcomgeuq
   %res = call <2 x i64> @llvm.x86.xop.vpcomgeuq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomgeuq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomgeuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomuw
+  ; CHECK: vpcomgeuw
   %res = call <8 x i16> @llvm.x86.xop.vpcomgeuw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomgeuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomgew(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomw
+  ; CHECK: vpcomgew
   %res = call <8 x i16> @llvm.x86.xop.vpcomgew(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomgew(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomgtb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomb
+  ; CHECK: vpcomgtb
   %res = call <16 x i8> @llvm.x86.xop.vpcomgtb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomgtb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomgtd(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomd
+  ; CHECK: vpcomgtd
   %res = call <4 x i32> @llvm.x86.xop.vpcomgtd(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomgtd(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomgtq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomq
+  ; CHECK: vpcomgtq
   %res = call <2 x i64> @llvm.x86.xop.vpcomgtq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomgtq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomgtub(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomub
+  ; CHECK: vpcomgtub
   %res = call <16 x i8> @llvm.x86.xop.vpcomgtub(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomgtub(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomgtud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomud
+  ; CHECK: vpcomgtud
   %res = call <4 x i32> @llvm.x86.xop.vpcomgtud(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomgtud(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomgtuq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomuq
+  ; CHECK: vpcomgtuq
   %res = call <2 x i64> @llvm.x86.xop.vpcomgtuq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomgtuq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomgtuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomuw
+  ; CHECK: vpcomgtuw
   %res = call <8 x i16> @llvm.x86.xop.vpcomgtuw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomgtuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomgtw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomw
+  ; CHECK: vpcomgtw
   %res = call <8 x i16> @llvm.x86.xop.vpcomgtw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomgtw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomleb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomb
+  ; CHECK: vpcomleb
   %res = call <16 x i8> @llvm.x86.xop.vpcomleb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomleb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomled(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomd
+  ; CHECK: vpcomled
   %res = call <4 x i32> @llvm.x86.xop.vpcomled(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomled(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomleq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomq
+  ; CHECK: vpcomleq
   %res = call <2 x i64> @llvm.x86.xop.vpcomleq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomleq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomleub(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomub
+  ; CHECK: vpcomleub
   %res = call <16 x i8> @llvm.x86.xop.vpcomleub(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomleub(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomleud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomud
+  ; CHECK: vpcomleud
   %res = call <4 x i32> @llvm.x86.xop.vpcomleud(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomleud(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomleuq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomuq
+  ; CHECK: vpcomleuq
   %res = call <2 x i64> @llvm.x86.xop.vpcomleuq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomleuq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomleuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomuw
+  ; CHECK: vpcomleuw
   %res = call <8 x i16> @llvm.x86.xop.vpcomleuw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomleuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomlew(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomw
+  ; CHECK: vpcomlew
   %res = call <8 x i16> @llvm.x86.xop.vpcomlew(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomlew(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomltb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomb
+  ; CHECK: vpcomltb
   %res = call <16 x i8> @llvm.x86.xop.vpcomltb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomltb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomltd(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomd
+  ; CHECK: vpcomltd
   %res = call <4 x i32> @llvm.x86.xop.vpcomltd(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomltd(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomltq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomq
+  ; CHECK: vpcomltq
   %res = call <2 x i64> @llvm.x86.xop.vpcomltq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomltq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomltub(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomub
+  ; CHECK: vpcomltub
   %res = call <16 x i8> @llvm.x86.xop.vpcomltub(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomltub(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomltud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomud
+  ; CHECK: vpcomltud
   %res = call <4 x i32> @llvm.x86.xop.vpcomltud(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomltud(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomltuq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomuq
+  ; CHECK: vpcomltuq
   %res = call <2 x i64> @llvm.x86.xop.vpcomltuq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomltuq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomltuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomuw
+  ; CHECK: vpcomltuw
   %res = call <8 x i16> @llvm.x86.xop.vpcomltuw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomltuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomltw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomw
+  ; CHECK: vpcomltw
   %res = call <8 x i16> @llvm.x86.xop.vpcomltw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomltw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomneb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomb
+  ; CHECK: vpcomneqb
   %res = call <16 x i8> @llvm.x86.xop.vpcomneb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomneb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomned(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomd
+  ; CHECK: vpcomneqd
   %res = call <4 x i32> @llvm.x86.xop.vpcomned(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomned(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomneq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomq
+  ; CHECK: vpcomneqq
   %res = call <2 x i64> @llvm.x86.xop.vpcomneq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomneq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomneub(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomub
+  ; CHECK: vpcomnequb
   %res = call <16 x i8> @llvm.x86.xop.vpcomneub(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomneub(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomneud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomud
+  ; CHECK: vpcomnequd
   %res = call <4 x i32> @llvm.x86.xop.vpcomneud(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomneud(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomneuq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomuq
+  ; CHECK: vpcomnequq
   %res = call <2 x i64> @llvm.x86.xop.vpcomneuq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomneuq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomneuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomuw
+  ; CHECK: vpcomnequw
   %res = call <8 x i16> @llvm.x86.xop.vpcomneuw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomneuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomnew(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomw
+  ; CHECK: vpcomneqw
   %res = call <8 x i16> @llvm.x86.xop.vpcomnew(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomnew(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomtrueb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomb
+  ; CHECK: vpcomtrueb
   %res = call <16 x i8> @llvm.x86.xop.vpcomtrueb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomtrueb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomtrued(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomd
+  ; CHECK: vpcomtrued
   %res = call <4 x i32> @llvm.x86.xop.vpcomtrued(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomtrued(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomtrueq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomq
+  ; CHECK: vpcomtrueq
   %res = call <2 x i64> @llvm.x86.xop.vpcomtrueq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomtrueq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomtrueub(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomub
+  ; CHECK: vpcomtrueub
   %res = call <16 x i8> @llvm.x86.xop.vpcomtrueub(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomtrueub(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomtrueud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomud
+  ; CHECK: vpcomtrueud
   %res = call <4 x i32> @llvm.x86.xop.vpcomtrueud(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomtrueud(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomtrueuq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomuq
+  ; CHECK: vpcomtrueuq
   %res = call <2 x i64> @llvm.x86.xop.vpcomtrueuq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomtrueuq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomtrueuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomuw
+  ; CHECK: vpcomtrueuw
   %res = call <8 x i16> @llvm.x86.xop.vpcomtrueuw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomtrueuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomtruew(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomw
+  ; CHECK: vpcomtruew
   %res = call <8 x i16> @llvm.x86.xop.vpcomtruew(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
@@ -645,7 +645,7 @@ define <2 x i64> @test_int_x86_xop_vphsubdq(<4 x i32> %a0) {
 define <2 x i64> @test_int_x86_xop_vphsubdq_mem(<4 x i32>* %a0) {
   ; CHECK-NOT: vmovaps
   ; CHECK: vphsubdq
-  %vec = load <4 x i32>* %a0
+  %vec = load <4 x i32>, <4 x i32>* %a0
   %res = call <2 x i64> @llvm.x86.xop.vphsubdq(<4 x i32> %vec) ;
   ret <2 x i64> %res
 }
@@ -659,7 +659,7 @@ define <4 x i32> @test_int_x86_xop_vphsubwd(<8 x i16> %a0) {
 define <4 x i32> @test_int_x86_xop_vphsubwd_mem(<8 x i16>* %a0) {
   ; CHECK-NOT: vmovaps
   ; CHECK: vphsubwd
-  %vec = load <8 x i16>* %a0
+  %vec = load <8 x i16>, <8 x i16>* %a0
   %res = call <4 x i32> @llvm.x86.xop.vphsubwd(<8 x i16> %vec) ;
   ret <4 x i32> %res
 }
@@ -750,7 +750,7 @@ define <4 x i32> @test_int_x86_xop_vpmadcswd(<8 x i16> %a0, <8 x i16> %a1, <4 x
 define <4 x i32> @test_int_x86_xop_vpmadcswd_mem(<8 x i16> %a0, <8 x i16>* %a1, <4 x i32> %a2) {
   ; CHECK-NOT: vmovaps
   ; CHECK: vpmadcswd
-  %vec = load <8 x i16>* %a1
+  %vec = load <8 x i16>, <8 x i16>* %a1
   %res = call <4 x i32> @llvm.x86.xop.vpmadcswd(<8 x i16> %a0, <8 x i16> %vec, <4 x i32> %a2) ;
   ret <4 x i32> %res
 }
@@ -764,14 +764,14 @@ define <16 x i8> @test_int_x86_xop_vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8
 define <16 x i8> @test_int_x86_xop_vpperm_rm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8>* %a2) {
   ; CHECK-NOT: vmovaps
   ; CHECK: vpperm
-  %vec = load <16 x i8>* %a2
+  %vec = load <16 x i8>, <16 x i8>* %a2
   %res = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %vec) ;
   ret <16 x i8> %res
 }
 define <16 x i8> @test_int_x86_xop_vpperm_mr(<16 x i8> %a0, <16 x i8>* %a1, <16 x i8> %a2) {
   ; CHECK-NOT: vmovaps
   ; CHECK: vpperm
-  %vec = load <16 x i8>* %a1
+  %vec = load <16 x i8>, <16 x i8>* %a1
   %res = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %vec, <16 x i8> %a2) ;
   ret <16 x i8> %res
 }
@@ -862,14 +862,14 @@ define <8 x i16> @test_int_x86_xop_vpshlw(<8 x i16> %a0, <8 x i16> %a1) {
 define <8 x i16> @test_int_x86_xop_vpshlw_rm(<8 x i16> %a0, <8 x i16>* %a1) {
   ; CHECK-NOT: vmovaps
   ; CHECK: vpshlw
-  %vec = load <8 x i16>* %a1
+  %vec = load <8 x i16>, <8 x i16>* %a1
   %res = call <8 x i16> @llvm.x86.xop.vpshlw(<8 x i16> %a0, <8 x i16> %vec) ;
   ret <8 x i16> %res
 }
 define <8 x i16> @test_int_x86_xop_vpshlw_mr(<8 x i16>* %a0, <8 x i16> %a1) {
   ; CHECK-NOT: vmovaps
   ; CHECK: vpshlw
-  %vec = load <8 x i16>* %a0
+  %vec = load <8 x i16>, <8 x i16>* %a0
   %res = call <8 x i16> @llvm.x86.xop.vpshlw(<8 x i16> %vec, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
@@ -884,7 +884,7 @@ define <4 x float> @test_int_x86_xop_vfrcz_ss(<4 x float> %a0) {
 define <4 x float> @test_int_x86_xop_vfrcz_ss_mem(float* %a0) {
   ; CHECK-NOT: mov
   ; CHECK: vfrczss
-  %elem = load float* %a0
+  %elem = load float, float* %a0
   %vec = insertelement <4 x float> undef, float %elem, i32 0
   %res = call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %vec) ;
   ret <4 x float> %res
@@ -900,7 +900,7 @@ define <2 x double> @test_int_x86_xop_vfrcz_sd(<2 x double> %a0) {
 define <2 x double> @test_int_x86_xop_vfrcz_sd_mem(double* %a0) {
   ; CHECK-NOT: mov
   ; CHECK: vfrczsd
-  %elem = load double* %a0
+  %elem = load double, double* %a0
   %vec = insertelement <2 x double> undef, double %elem, i32 0
   %res = call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %vec) ;
   ret <2 x double> %res
@@ -915,7 +915,7 @@ define <2 x double> @test_int_x86_xop_vfrcz_pd(<2 x double> %a0) {
 define <2 x double> @test_int_x86_xop_vfrcz_pd_mem(<2 x double>* %a0) {
   ; CHECK-NOT: vmovaps
   ; CHECK: vfrczpd
-  %vec = load <2 x double>* %a0
+  %vec = load <2 x double>, <2 x double>* %a0
   %res = call <2 x double> @llvm.x86.xop.vfrcz.pd(<2 x double> %vec) ;
   ret <2 x double> %res
 }
@@ -931,7 +931,7 @@ define <4 x double> @test_int_x86_xop_vfrcz_pd_256_mem(<4 x double>* %a0) {
   ; CHECK-NOT: vmovaps
   ; CHECK: vfrczpd
   ; CHECK: ymm
-  %vec = load <4 x double>* %a0
+  %vec = load <4 x double>, <4 x double>* %a0
   %res = call <4 x double> @llvm.x86.xop.vfrcz.pd.256(<4 x double> %vec) ;
   ret <4 x double> %res
 }
@@ -945,7 +945,7 @@ define <4 x float> @test_int_x86_xop_vfrcz_ps(<4 x float> %a0) {
 define <4 x float> @test_int_x86_xop_vfrcz_ps_mem(<4 x float>* %a0) {
   ; CHECK-NOT: vmovaps
   ; CHECK: vfrczps
-  %vec = load <4 x float>* %a0
+  %vec = load <4 x float>, <4 x float>* %a0
   %res = call <4 x float> @llvm.x86.xop.vfrcz.ps(<4 x float> %vec) ;
   ret <4 x float> %res
 }
@@ -961,7 +961,7 @@ define <8 x float> @test_int_x86_xop_vfrcz_ps_256_mem(<8 x float>* %a0) {
   ; CHECK-NOT: vmovaps
   ; CHECK: vfrczps
   ; CHECK: ymm
-  %vec = load <8 x float>* %a0
+  %vec = load <8 x float>, <8 x float>* %a0
   %res = call <8 x float> @llvm.x86.xop.vfrcz.ps.256(<8 x float> %vec) ;
   ret <8 x float> %res
 }
diff --git a/test/CodeGen/X86/xor-icmp.ll b/test/CodeGen/X86/xor-icmp.ll
index dd1fcca48f61..397e5bc10f5b 100644
--- a/test/CodeGen/X86/xor-icmp.ll
+++ b/test/CodeGen/X86/xor-icmp.ll
@@ -24,11 +24,11 @@ entry:
   br i1 %4, label %bb1, label %bb
 
 bb:                                               ; preds = %entry
-  %5 = tail call i32 (...)* @foo() nounwind       ; <i32> [#uses=1]
+  %5 = tail call i32 (...) @foo() nounwind       ; <i32> [#uses=1]
   ret i32 %5
 
 bb1:                                              ; preds = %entry
-  %6 = tail call i32 (...)* @bar() nounwind       ; <i32> [#uses=1]
+  %6 = tail call i32 (...) @bar() nounwind       ; <i32> [#uses=1]
   ret i32 %6
 }
 
@@ -59,7 +59,7 @@ entry:
   br i1 %2, label %bb, label %return
 
 bb:                                               ; preds = %entry
-  %3 = tail call i32 (...)* @foo() nounwind       ; <i32> [#uses=0]
+  %3 = tail call i32 (...) @foo() nounwind       ; <i32> [#uses=0]
   ret i32 undef
 
 return:                                           ; preds = %entry
diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll
index fd8e1b4cebaa..829be41e5127 100644
--- a/test/CodeGen/X86/xor.ll
+++ b/test/CodeGen/X86/xor.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -mcpu=corei7 -march=x86 -mattr=+sse2  | FileCheck %s -check-prefix=X32
-; RUN: llc < %s -mcpu=corei7 -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64
-; RUN: llc < %s -mcpu=corei7 -mtriple=x86_64-win32 | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -march=x86            -mattr=+sse2 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2 | FileCheck %s -check-prefix=X64
 
 ; Though it is undefined, we want xor undef,undef to produce zero.
 define <4 x i32> @test1() nounwind {
@@ -181,3 +181,15 @@ define i32 @PR17487(i1 %tobool) {
 ; X32-LABEL: PR17487:
 ; X32: andn
 }
+
+define i32 @test11(i32 %b) {
+  %shl = shl i32 1, %b
+  %neg = xor i32 %shl, -1
+  ret i32 %neg
+; X64-LABEL: test11:
+; X64: movl    $-2, %[[REG:.*]]
+; X64: roll    %{{.*}}, %[[REG]]
+; X32-LABEL: test11:
+; X32: movl    $-2, %[[REG:.*]]
+; X32: roll    %{{.*}}, %[[REG]]
+}
diff --git a/test/CodeGen/X86/zext-extract_subreg.ll b/test/CodeGen/X86/zext-extract_subreg.ll
index 43e79c77acc2..9e34abb69b39 100644
--- a/test/CodeGen/X86/zext-extract_subreg.ll
+++ b/test/CodeGen/X86/zext-extract_subreg.ll
@@ -6,7 +6,7 @@ entry:
   br i1 undef, label %return, label %if.end.i
 
 if.end.i:                                         ; preds = %entry
-  %tmp7.i = load i32* undef, align 4
+  %tmp7.i = load i32, i32* undef, align 4
   br i1 undef, label %return, label %if.end
 
 if.end:                                           ; preds = %if.end.i
diff --git a/test/CodeGen/X86/zext-sext.ll b/test/CodeGen/X86/zext-sext.ll
index 5b2713dc6fc1..01f871159d3b 100644
--- a/test/CodeGen/X86/zext-sext.ll
+++ b/test/CodeGen/X86/zext-sext.ll
@@ -8,15 +8,15 @@
 
 define void @func([40 x i16]* %a, i32* %b, i16** %c, i64* %d) nounwind {
 entry:
-  %tmp103 = getelementptr inbounds [40 x i16]* %a, i64 0, i64 4
-  %tmp104 = load i16* %tmp103, align 2
+  %tmp103 = getelementptr inbounds [40 x i16], [40 x i16]* %a, i64 0, i64 4
+  %tmp104 = load i16, i16* %tmp103, align 2
   %tmp105 = sext i16 %tmp104 to i32
-  %tmp106 = load i32* %b, align 4
+  %tmp106 = load i32, i32* %b, align 4
   %tmp107 = sub nsw i32 4, %tmp106
-  %tmp108 = load i16** %c, align 8
+  %tmp108 = load i16*, i16** %c, align 8
   %tmp109 = sext i32 %tmp107 to i64
-  %tmp110 = getelementptr inbounds i16* %tmp108, i64 %tmp109
-  %tmp111 = load i16* %tmp110, align 1
+  %tmp110 = getelementptr inbounds i16, i16* %tmp108, i64 %tmp109
+  %tmp111 = load i16, i16* %tmp110, align 1
   %tmp112 = sext i16 %tmp111 to i32
   %tmp = mul i32 355244649, %tmp112
   %tmp1 = mul i32 %tmp, %tmp105
@@ -34,11 +34,12 @@ entry:
   %tmp12 = add i64 %tmp11, 5089792279245435153
 
 ; CHECK:      addl	$2138875574, %e[[REGISTER_zext:[a-z0-9]+]]
-; CHECK:      movslq	%e[[REGISTER_zext]], [[REGISTER_sext:%r[a-z0-9]+]]
 ; CHECK:      cmpl	$-8608074, %e[[REGISTER_zext]]
+; CHECK:      movslq	%e[[REGISTER_zext]], [[REGISTER_sext:%r[a-z0-9]+]]
 ; CHECK-NOT:  [[REGISTER_zext]]
-; CHECK-DAG:  testl     %e[[REGISTER_zext]]
-; CHECK:      subq	%r[[REGISTER_zext]], [[REGISTER_sext]]
+; CHECK-DAG:  cmpl	$2138875573, %e[[REGISTER_zext]]
+; CHECK:      movq  [[REGISTER_sext]], [[REGISTER_sext2:%[a-z0-9]+]]
+; CHECK:      subq	%r[[REGISTER_zext]], [[REGISTER_sext2]]
 
   %tmp13 = sub i64 %tmp12, 2138875574
   %tmp14 = zext i32 %tmp4 to i64
@@ -49,7 +50,7 @@ entry:
   %tmp19 = sub i64 %tmp18, 5386586244038704851
   %tmp20 = add i64 %tmp19, -1368057358110947217
   %tmp21 = mul i64 %tmp20, -422037402840850817
-  %tmp115 = load i64* %d, align 8
+  %tmp115 = load i64, i64* %d, align 8
   %alphaX = mul i64 468858157810230901, %tmp21
   %alphaXbetaY = add i64 %alphaX, %tmp115
   %transformed = add i64 %alphaXbetaY, 9040145182981852475
diff --git a/test/CodeGen/X86/zlib-longest-match.ll b/test/CodeGen/X86/zlib-longest-match.ll
index d1598dce02d7..7be03f662dae 100644
--- a/test/CodeGen/X86/zlib-longest-match.ll
+++ b/test/CodeGen/X86/zlib-longest-match.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=x86-64 < %s -block-placement-exit-block-bias=20 | FileCheck %s
+; RUN: llc -march=x86-64 < %s -block-placement-exit-block-bias=20 -no-phi-elim-live-out-early-exit | FileCheck %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.9.0"
 
@@ -25,56 +25,55 @@ target triple = "x86_64-apple-macosx10.9.0"
 ; the two hot blocks are laid out close to each other.
 ; CHECK-NEXT: %land.rhs131
 ; CHECK: jne
-; CHECK: jmp
 define i32 @longest_match(%struct.internal_state* nocapture %s, i32 %cur_match) nounwind {
 entry:
-  %max_chain_length = getelementptr inbounds %struct.internal_state* %s, i64 0, i32 31
-  %0 = load i32* %max_chain_length, align 4
-  %window = getelementptr inbounds %struct.internal_state* %s, i64 0, i32 14
-  %1 = load i8** %window, align 8
-  %strstart = getelementptr inbounds %struct.internal_state* %s, i64 0, i32 27
-  %2 = load i32* %strstart, align 4
+  %max_chain_length = getelementptr inbounds %struct.internal_state, %struct.internal_state* %s, i64 0, i32 31
+  %0 = load i32, i32* %max_chain_length, align 4
+  %window = getelementptr inbounds %struct.internal_state, %struct.internal_state* %s, i64 0, i32 14
+  %1 = load i8*, i8** %window, align 8
+  %strstart = getelementptr inbounds %struct.internal_state, %struct.internal_state* %s, i64 0, i32 27
+  %2 = load i32, i32* %strstart, align 4
   %idx.ext = zext i32 %2 to i64
-  %add.ptr = getelementptr inbounds i8* %1, i64 %idx.ext
-  %prev_length = getelementptr inbounds %struct.internal_state* %s, i64 0, i32 30
-  %3 = load i32* %prev_length, align 4
-  %nice_match1 = getelementptr inbounds %struct.internal_state* %s, i64 0, i32 36
-  %4 = load i32* %nice_match1, align 4
-  %w_size = getelementptr inbounds %struct.internal_state* %s, i64 0, i32 11
-  %5 = load i32* %w_size, align 4
+  %add.ptr = getelementptr inbounds i8, i8* %1, i64 %idx.ext
+  %prev_length = getelementptr inbounds %struct.internal_state, %struct.internal_state* %s, i64 0, i32 30
+  %3 = load i32, i32* %prev_length, align 4
+  %nice_match1 = getelementptr inbounds %struct.internal_state, %struct.internal_state* %s, i64 0, i32 36
+  %4 = load i32, i32* %nice_match1, align 4
+  %w_size = getelementptr inbounds %struct.internal_state, %struct.internal_state* %s, i64 0, i32 11
+  %5 = load i32, i32* %w_size, align 4
   %sub = add i32 %5, -262
   %cmp = icmp ugt i32 %2, %sub
   %sub6 = sub i32 %2, %sub
   %sub6. = select i1 %cmp, i32 %sub6, i32 0
-  %prev7 = getelementptr inbounds %struct.internal_state* %s, i64 0, i32 16
-  %6 = load i16** %prev7, align 8
-  %w_mask = getelementptr inbounds %struct.internal_state* %s, i64 0, i32 13
-  %7 = load i32* %w_mask, align 4
+  %prev7 = getelementptr inbounds %struct.internal_state, %struct.internal_state* %s, i64 0, i32 16
+  %6 = load i16*, i16** %prev7, align 8
+  %w_mask = getelementptr inbounds %struct.internal_state, %struct.internal_state* %s, i64 0, i32 13
+  %7 = load i32, i32* %w_mask, align 4
   %add.ptr11.sum = add i64 %idx.ext, 258
-  %add.ptr12 = getelementptr inbounds i8* %1, i64 %add.ptr11.sum
+  %add.ptr12 = getelementptr inbounds i8, i8* %1, i64 %add.ptr11.sum
   %sub13 = add nsw i32 %3, -1
   %idxprom = sext i32 %sub13 to i64
   %add.ptr.sum = add i64 %idxprom, %idx.ext
-  %arrayidx = getelementptr inbounds i8* %1, i64 %add.ptr.sum
-  %8 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %1, i64 %add.ptr.sum
+  %8 = load i8, i8* %arrayidx, align 1
   %idxprom14 = sext i32 %3 to i64
   %add.ptr.sum213 = add i64 %idxprom14, %idx.ext
-  %arrayidx15 = getelementptr inbounds i8* %1, i64 %add.ptr.sum213
-  %9 = load i8* %arrayidx15, align 1
-  %good_match = getelementptr inbounds %struct.internal_state* %s, i64 0, i32 35
-  %10 = load i32* %good_match, align 4
+  %arrayidx15 = getelementptr inbounds i8, i8* %1, i64 %add.ptr.sum213
+  %9 = load i8, i8* %arrayidx15, align 1
+  %good_match = getelementptr inbounds %struct.internal_state, %struct.internal_state* %s, i64 0, i32 35
+  %10 = load i32, i32* %good_match, align 4
   %cmp17 = icmp ult i32 %3, %10
   %shr = lshr i32 %0, 2
   %chain_length.0 = select i1 %cmp17, i32 %0, i32 %shr
-  %lookahead = getelementptr inbounds %struct.internal_state* %s, i64 0, i32 29
-  %11 = load i32* %lookahead, align 4
+  %lookahead = getelementptr inbounds %struct.internal_state, %struct.internal_state* %s, i64 0, i32 29
+  %11 = load i32, i32* %lookahead, align 4
   %cmp18 = icmp ugt i32 %4, %11
   %. = select i1 %cmp18, i32 %11, i32 %4
-  %match_start = getelementptr inbounds %struct.internal_state* %s, i64 0, i32 28
+  %match_start = getelementptr inbounds %struct.internal_state, %struct.internal_state* %s, i64 0, i32 28
   %add.ptr.sum217 = add i64 %idx.ext, 1
-  %arrayidx44 = getelementptr inbounds i8* %1, i64 %add.ptr.sum217
+  %arrayidx44 = getelementptr inbounds i8, i8* %1, i64 %add.ptr.sum217
   %add.ptr.sum218 = add i64 %idx.ext, 2
-  %add.ptr50 = getelementptr inbounds i8* %1, i64 %add.ptr.sum218
+  %add.ptr50 = getelementptr inbounds i8, i8* %1, i64 %add.ptr.sum218
   %sub.ptr.lhs.cast = ptrtoint i8* %add.ptr12 to i64
   br label %do.body
 
@@ -85,11 +84,11 @@ do.body:                                          ; preds = %land.rhs131, %entry
   %scan_end1.0 = phi i8 [ %scan_end1.1, %land.rhs131 ], [ %8, %entry ]
   %scan_end.0 = phi i8 [ %scan_end.1, %land.rhs131 ], [ %9, %entry ]
   %idx.ext23 = zext i32 %cur_match.addr.0 to i64
-  %add.ptr24 = getelementptr inbounds i8* %1, i64 %idx.ext23
+  %add.ptr24 = getelementptr inbounds i8, i8* %1, i64 %idx.ext23
   %idxprom25 = sext i32 %best_len.0 to i64
   %add.ptr24.sum = add i64 %idx.ext23, %idxprom25
-  %arrayidx26 = getelementptr inbounds i8* %1, i64 %add.ptr24.sum
-  %12 = load i8* %arrayidx26, align 1
+  %arrayidx26 = getelementptr inbounds i8, i8* %1, i64 %add.ptr24.sum
+  %12 = load i8, i8* %arrayidx26, align 1
   %cmp28 = icmp eq i8 %12, %scan_end.0
   br i1 %cmp28, label %lor.lhs.false, label %do.cond125
 
@@ -97,93 +96,93 @@ lor.lhs.false:                                    ; preds = %do.body
   %sub30 = add nsw i32 %best_len.0, -1
   %idxprom31 = sext i32 %sub30 to i64
   %add.ptr24.sum214 = add i64 %idx.ext23, %idxprom31
-  %arrayidx32 = getelementptr inbounds i8* %1, i64 %add.ptr24.sum214
-  %13 = load i8* %arrayidx32, align 1
+  %arrayidx32 = getelementptr inbounds i8, i8* %1, i64 %add.ptr24.sum214
+  %13 = load i8, i8* %arrayidx32, align 1
   %cmp35 = icmp eq i8 %13, %scan_end1.0
   br i1 %cmp35, label %lor.lhs.false37, label %do.cond125
 
 lor.lhs.false37:                                  ; preds = %lor.lhs.false
-  %14 = load i8* %add.ptr24, align 1
-  %15 = load i8* %add.ptr, align 1
+  %14 = load i8, i8* %add.ptr24, align 1
+  %15 = load i8, i8* %add.ptr, align 1
   %cmp40 = icmp eq i8 %14, %15
   br i1 %cmp40, label %lor.lhs.false42, label %do.cond125
 
 lor.lhs.false42:                                  ; preds = %lor.lhs.false37
   %add.ptr24.sum215 = add i64 %idx.ext23, 1
-  %incdec.ptr = getelementptr inbounds i8* %1, i64 %add.ptr24.sum215
-  %16 = load i8* %incdec.ptr, align 1
-  %17 = load i8* %arrayidx44, align 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %1, i64 %add.ptr24.sum215
+  %16 = load i8, i8* %incdec.ptr, align 1
+  %17 = load i8, i8* %arrayidx44, align 1
   %cmp46 = icmp eq i8 %16, %17
   br i1 %cmp46, label %if.end49, label %do.cond125
 
 if.end49:                                         ; preds = %lor.lhs.false42
   %incdec.ptr.sum = add i64 %idx.ext23, 2
-  %incdec.ptr51 = getelementptr inbounds i8* %1, i64 %incdec.ptr.sum
+  %incdec.ptr51 = getelementptr inbounds i8, i8* %1, i64 %incdec.ptr.sum
   br label %do.cond
 
 do.cond:                                          ; preds = %land.lhs.true100, %if.end49
   %match.0 = phi i8* [ %incdec.ptr51, %if.end49 ], [ %incdec.ptr103, %land.lhs.true100 ]
   %scan.1 = phi i8* [ %add.ptr50, %if.end49 ], [ %incdec.ptr101, %land.lhs.true100 ]
-  %incdec.ptr53 = getelementptr inbounds i8* %scan.1, i64 1
-  %18 = load i8* %incdec.ptr53, align 1
-  %incdec.ptr55 = getelementptr inbounds i8* %match.0, i64 1
-  %19 = load i8* %incdec.ptr55, align 1
+  %incdec.ptr53 = getelementptr inbounds i8, i8* %scan.1, i64 1
+  %18 = load i8, i8* %incdec.ptr53, align 1
+  %incdec.ptr55 = getelementptr inbounds i8, i8* %match.0, i64 1
+  %19 = load i8, i8* %incdec.ptr55, align 1
   %cmp57 = icmp eq i8 %18, %19
   br i1 %cmp57, label %land.lhs.true, label %do.end
 
 land.lhs.true:                                    ; preds = %do.cond
-  %incdec.ptr59 = getelementptr inbounds i8* %scan.1, i64 2
-  %20 = load i8* %incdec.ptr59, align 1
-  %incdec.ptr61 = getelementptr inbounds i8* %match.0, i64 2
-  %21 = load i8* %incdec.ptr61, align 1
+  %incdec.ptr59 = getelementptr inbounds i8, i8* %scan.1, i64 2
+  %20 = load i8, i8* %incdec.ptr59, align 1
+  %incdec.ptr61 = getelementptr inbounds i8, i8* %match.0, i64 2
+  %21 = load i8, i8* %incdec.ptr61, align 1
   %cmp63 = icmp eq i8 %20, %21
   br i1 %cmp63, label %land.lhs.true65, label %do.end
 
 land.lhs.true65:                                  ; preds = %land.lhs.true
-  %incdec.ptr66 = getelementptr inbounds i8* %scan.1, i64 3
-  %22 = load i8* %incdec.ptr66, align 1
-  %incdec.ptr68 = getelementptr inbounds i8* %match.0, i64 3
-  %23 = load i8* %incdec.ptr68, align 1
+  %incdec.ptr66 = getelementptr inbounds i8, i8* %scan.1, i64 3
+  %22 = load i8, i8* %incdec.ptr66, align 1
+  %incdec.ptr68 = getelementptr inbounds i8, i8* %match.0, i64 3
+  %23 = load i8, i8* %incdec.ptr68, align 1
   %cmp70 = icmp eq i8 %22, %23
   br i1 %cmp70, label %land.lhs.true72, label %do.end
 
 land.lhs.true72:                                  ; preds = %land.lhs.true65
-  %incdec.ptr73 = getelementptr inbounds i8* %scan.1, i64 4
-  %24 = load i8* %incdec.ptr73, align 1
-  %incdec.ptr75 = getelementptr inbounds i8* %match.0, i64 4
-  %25 = load i8* %incdec.ptr75, align 1
+  %incdec.ptr73 = getelementptr inbounds i8, i8* %scan.1, i64 4
+  %24 = load i8, i8* %incdec.ptr73, align 1
+  %incdec.ptr75 = getelementptr inbounds i8, i8* %match.0, i64 4
+  %25 = load i8, i8* %incdec.ptr75, align 1
   %cmp77 = icmp eq i8 %24, %25
   br i1 %cmp77, label %land.lhs.true79, label %do.end
 
 land.lhs.true79:                                  ; preds = %land.lhs.true72
-  %incdec.ptr80 = getelementptr inbounds i8* %scan.1, i64 5
-  %26 = load i8* %incdec.ptr80, align 1
-  %incdec.ptr82 = getelementptr inbounds i8* %match.0, i64 5
-  %27 = load i8* %incdec.ptr82, align 1
+  %incdec.ptr80 = getelementptr inbounds i8, i8* %scan.1, i64 5
+  %26 = load i8, i8* %incdec.ptr80, align 1
+  %incdec.ptr82 = getelementptr inbounds i8, i8* %match.0, i64 5
+  %27 = load i8, i8* %incdec.ptr82, align 1
   %cmp84 = icmp eq i8 %26, %27
   br i1 %cmp84, label %land.lhs.true86, label %do.end
 
 land.lhs.true86:                                  ; preds = %land.lhs.true79
-  %incdec.ptr87 = getelementptr inbounds i8* %scan.1, i64 6
-  %28 = load i8* %incdec.ptr87, align 1
-  %incdec.ptr89 = getelementptr inbounds i8* %match.0, i64 6
-  %29 = load i8* %incdec.ptr89, align 1
+  %incdec.ptr87 = getelementptr inbounds i8, i8* %scan.1, i64 6
+  %28 = load i8, i8* %incdec.ptr87, align 1
+  %incdec.ptr89 = getelementptr inbounds i8, i8* %match.0, i64 6
+  %29 = load i8, i8* %incdec.ptr89, align 1
   %cmp91 = icmp eq i8 %28, %29
   br i1 %cmp91, label %land.lhs.true93, label %do.end
 
 land.lhs.true93:                                  ; preds = %land.lhs.true86
-  %incdec.ptr94 = getelementptr inbounds i8* %scan.1, i64 7
-  %30 = load i8* %incdec.ptr94, align 1
-  %incdec.ptr96 = getelementptr inbounds i8* %match.0, i64 7
-  %31 = load i8* %incdec.ptr96, align 1
+  %incdec.ptr94 = getelementptr inbounds i8, i8* %scan.1, i64 7
+  %30 = load i8, i8* %incdec.ptr94, align 1
+  %incdec.ptr96 = getelementptr inbounds i8, i8* %match.0, i64 7
+  %31 = load i8, i8* %incdec.ptr96, align 1
   %cmp98 = icmp eq i8 %30, %31
   br i1 %cmp98, label %land.lhs.true100, label %do.end
 
 land.lhs.true100:                                 ; preds = %land.lhs.true93
-  %incdec.ptr101 = getelementptr inbounds i8* %scan.1, i64 8
-  %32 = load i8* %incdec.ptr101, align 1
-  %incdec.ptr103 = getelementptr inbounds i8* %match.0, i64 8
-  %33 = load i8* %incdec.ptr103, align 1
+  %incdec.ptr101 = getelementptr inbounds i8, i8* %scan.1, i64 8
+  %32 = load i8, i8* %incdec.ptr101, align 1
+  %incdec.ptr103 = getelementptr inbounds i8, i8* %match.0, i64 8
+  %33 = load i8, i8* %incdec.ptr103, align 1
   %cmp105 = icmp eq i8 %32, %33
   %cmp107 = icmp ult i8* %incdec.ptr101, %add.ptr12
   %or.cond = and i1 %cmp105, %cmp107
@@ -207,12 +206,12 @@ if.end118:                                        ; preds = %if.then114
   %sub119 = add nsw i32 %sub110, -1
   %idxprom120 = sext i32 %sub119 to i64
   %add.ptr111.sum = add i64 %idxprom120, %idx.ext
-  %arrayidx121 = getelementptr inbounds i8* %1, i64 %add.ptr111.sum
-  %34 = load i8* %arrayidx121, align 1
+  %arrayidx121 = getelementptr inbounds i8, i8* %1, i64 %add.ptr111.sum
+  %34 = load i8, i8* %arrayidx121, align 1
   %idxprom122 = sext i32 %sub110 to i64
   %add.ptr111.sum216 = add i64 %idxprom122, %idx.ext
-  %arrayidx123 = getelementptr inbounds i8* %1, i64 %add.ptr111.sum216
-  %35 = load i8* %arrayidx123, align 1
+  %arrayidx123 = getelementptr inbounds i8, i8* %1, i64 %add.ptr111.sum216
+  %35 = load i8, i8* %arrayidx123, align 1
   br label %do.cond125
 
 do.cond125:                                       ; preds = %if.end118, %do.end, %lor.lhs.false42, %lor.lhs.false37, %lor.lhs.false, %do.body
@@ -221,8 +220,8 @@ do.cond125:                                       ; preds = %if.end118, %do.end,
   %scan_end.1 = phi i8 [ %scan_end.0, %do.body ], [ %scan_end.0, %lor.lhs.false ], [ %scan_end.0, %lor.lhs.false37 ], [ %scan_end.0, %lor.lhs.false42 ], [ %35, %if.end118 ], [ %scan_end.0, %do.end ]
   %and = and i32 %cur_match.addr.0, %7
   %idxprom126 = zext i32 %and to i64
-  %arrayidx127 = getelementptr inbounds i16* %6, i64 %idxprom126
-  %36 = load i16* %arrayidx127, align 2
+  %arrayidx127 = getelementptr inbounds i16, i16* %6, i64 %idxprom126
+  %36 = load i16, i16* %arrayidx127, align 2
   %conv128 = zext i16 %36 to i32
   %cmp129 = icmp ugt i32 %conv128, %sub6.
   br i1 %cmp129, label %land.rhs131, label %do.end135
diff --git a/test/CodeGen/XCore/2009-01-08-Crash.ll b/test/CodeGen/XCore/2009-01-08-Crash.ll
index a31ea1e2e9be..5eddbc33761c 100644
--- a/test/CodeGen/XCore/2009-01-08-Crash.ll
+++ b/test/CodeGen/XCore/2009-01-08-Crash.ll
@@ -6,7 +6,7 @@
 define i32 @test(i32 %bar) nounwind readnone {
 entry:
         %bar_addr = alloca i32
-        %0 = getelementptr i32* %bar_addr, i32 -1
-        %1 = load i32* %0, align 4
+        %0 = getelementptr i32, i32* %bar_addr, i32 -1
+        %1 = load i32, i32* %0, align 4
         ret i32 %1
 }
diff --git a/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll b/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll
index 6ad9a73899d1..693e6f0f136b 100644
--- a/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll
+++ b/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll
@@ -14,9 +14,9 @@ entry:
 bb3.i15.i.i:                                      ; preds = %bb3.i15.i.i, %entry
   %indvar.i.i.i = phi i32 [ %indvar.next.i.i.i, %bb3.i15.i.i ], [ 0, %entry ] ; <i32> [#uses=2]
   %tmp137 = sub i32 0, %indvar.i.i.i              ; <i32> [#uses=1]
-  %scevgep13.i.i.i = getelementptr i32* undef, i32 %tmp137 ; <i32*> [#uses=2]
+  %scevgep13.i.i.i = getelementptr i32, i32* undef, i32 %tmp137 ; <i32*> [#uses=2]
   %scevgep1314.i.i.i = bitcast i32* %scevgep13.i.i.i to %struct.dwarf_fde** ; <%struct.dwarf_fde**> [#uses=1]
-  %0 = load %struct.dwarf_fde** %scevgep1314.i.i.i, align 4 ; <%struct.dwarf_fde*> [#uses=0]
+  %0 = load %struct.dwarf_fde*, %struct.dwarf_fde** %scevgep1314.i.i.i, align 4 ; <%struct.dwarf_fde*> [#uses=0]
   store i32 undef, i32* %scevgep13.i.i.i
   %indvar.next.i.i.i = add i32 %indvar.i.i.i, 1   ; <i32> [#uses=1]
   br label %bb3.i15.i.i
diff --git a/test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll b/test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll
index f8fe0d2136ff..40c9654371fd 100644
--- a/test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll
+++ b/test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll
@@ -5,6 +5,6 @@
 
 define i32 @test_entry() nounwind {
 entry:
-  %0 = load i32* getelementptr inbounds (%struct.st* @x, i32 0, i32 3), align 2
+  %0 = load i32, i32* getelementptr inbounds (%struct.st, %struct.st* @x, i32 0, i32 3), align 2
   ret i32 %0
 }
diff --git a/test/CodeGen/XCore/atomic.ll b/test/CodeGen/XCore/atomic.ll
index 6ca80cf5d9e7..13579dbd8197 100644
--- a/test/CodeGen/XCore/atomic.ll
+++ b/test/CodeGen/XCore/atomic.ll
@@ -25,27 +25,27 @@ entry:
 ; CHECK-NEXT: ldaw r[[R1:[0-9]+]], dp[pool]
 ; CHECK-NEXT: #MEMBARRIER
 ; CHECK-NEXT: ldc r[[R2:[0-9]+]], 0
-  %0 = load atomic i32* bitcast (i64* @pool to i32*) acquire, align 4
+  %0 = load atomic i32, i32* bitcast (i64* @pool to i32*) acquire, align 4
 
 ; CHECK-NEXT: ld16s r3, r[[R1]][r[[R2]]]
 ; CHECK-NEXT: #MEMBARRIER
-  %1 = load atomic i16* bitcast (i64* @pool to i16*) acquire, align 2
+  %1 = load atomic i16, i16* bitcast (i64* @pool to i16*) acquire, align 2
 
 ; CHECK-NEXT: ld8u r11, r[[R1]][r[[R2]]]
 ; CHECK-NEXT: #MEMBARRIER
-  %2 = load atomic i8* bitcast (i64* @pool to i8*) acquire, align 1
+  %2 = load atomic i8, i8* bitcast (i64* @pool to i8*) acquire, align 1
 
 ; CHECK-NEXT: ldw r4, dp[pool]
 ; CHECK-NEXT: #MEMBARRIER
-  %3 = load atomic i32* bitcast (i64* @pool to i32*) seq_cst, align 4
+  %3 = load atomic i32, i32* bitcast (i64* @pool to i32*) seq_cst, align 4
 
 ; CHECK-NEXT: ld16s r5, r[[R1]][r[[R2]]]
 ; CHECK-NEXT: #MEMBARRIER
-  %4 = load atomic i16* bitcast (i64* @pool to i16*) seq_cst, align 2
+  %4 = load atomic i16, i16* bitcast (i64* @pool to i16*) seq_cst, align 2
 
 ; CHECK-NEXT: ld8u r6, r[[R1]][r[[R2]]]
 ; CHECK-NEXT: #MEMBARRIER
-  %5 = load atomic i8* bitcast (i64* @pool to i8*) seq_cst, align 1
+  %5 = load atomic i8, i8* bitcast (i64* @pool to i8*) seq_cst, align 1
 
 ; CHECK-NEXT: #MEMBARRIER
 ; CHECK-NEXT: stw r[[R0]], dp[pool]
@@ -80,11 +80,11 @@ entry:
 ; CHECK-NEXT: st16 r[[R0]], r[[R1]][r[[R2]]]
 ; CHECK-NEXT: ld8u r[[R0]], r[[R1]][r[[R2]]]
 ; CHECK-NEXT: st8 r[[R0]], r[[R1]][r[[R2]]]
-  %6 = load atomic i32* bitcast (i64* @pool to i32*) monotonic, align 4
+  %6 = load atomic i32, i32* bitcast (i64* @pool to i32*) monotonic, align 4
   store atomic i32 %6, i32* bitcast (i64* @pool to i32*) monotonic, align 4
-  %7 = load atomic i16* bitcast (i64* @pool to i16*) monotonic, align 2
+  %7 = load atomic i16, i16* bitcast (i64* @pool to i16*) monotonic, align 2
   store atomic i16 %7, i16* bitcast (i64* @pool to i16*) monotonic, align 2
-  %8 = load atomic i8* bitcast (i64* @pool to i8*) monotonic, align 1
+  %8 = load atomic i8, i8* bitcast (i64* @pool to i8*) monotonic, align 1
   store atomic i8 %8, i8* bitcast (i64* @pool to i8*) monotonic, align 1
 
   ret void
diff --git a/test/CodeGen/XCore/codemodel.ll b/test/CodeGen/XCore/codemodel.ll
index 0245893c478d..4e637995c5a8 100644
--- a/test/CodeGen/XCore/codemodel.ll
+++ b/test/CodeGen/XCore/codemodel.ll
@@ -96,22 +96,22 @@ entry:
 ; LARGE: retsp 0
 define i32 @f(i32* %i) {
 entry:
-  %0 = getelementptr inbounds i32* %i, i32 16383
-  %1 = load i32* %0
-  %2 = getelementptr inbounds i32* %i, i32 16384
-  %3 = load i32* %2
+  %0 = getelementptr inbounds i32, i32* %i, i32 16383
+  %1 = load i32, i32* %0
+  %2 = getelementptr inbounds i32, i32* %i, i32 16384
+  %3 = load i32, i32* %2
   %4 = add nsw i32 %1, %3
-  %5 = load i32* getelementptr inbounds ([100 x i32]* @l, i32 0, i32 0)
+  %5 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @l, i32 0, i32 0)
   %6 = add nsw i32 %4, %5
-  %7 = load i32* getelementptr inbounds ([100 x i32]* @l, i32 0, i32 1)
+  %7 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @l, i32 0, i32 1)
   %8 = add nsw i32 %6, %7
-  %9 = load i32* getelementptr inbounds ([100 x i32]* @l, i32 0, i32 98)
+  %9 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @l, i32 0, i32 98)
   %10 = add nsw i32 %8, %9
-  %11 = load i32* getelementptr inbounds ([100 x i32]* @l, i32 0, i32 99)
+  %11 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @l, i32 0, i32 99)
   %12 = add nsw i32 %10, %11
-  %13 = load i32* getelementptr inbounds ([10 x i32]* @s, i32 0, i32 0)
+  %13 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @s, i32 0, i32 0)
   %14 = add nsw i32 %12, %13
-  %15 = load i32* getelementptr inbounds ([10 x i32]* @s, i32 0, i32 9)
+  %15 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @s, i32 0, i32 9)
   %16 = add nsw i32 %14, %15
   ret i32 %16
 }
@@ -132,7 +132,7 @@ entry:
 @NoSize = external global [0 x i32]
 define i32 @UnknownSize() nounwind {
 entry:
-  %0 = load i32* getelementptr inbounds ([0 x i32]* @NoSize, i32 0, i32 10)
+  %0 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @NoSize, i32 0, i32 10)
   ret i32 %0
 }
 
diff --git a/test/CodeGen/XCore/dwarf_debug.ll b/test/CodeGen/XCore/dwarf_debug.ll
index 8c9c47de6497..ba71dc798a04 100644
--- a/test/CodeGen/XCore/dwarf_debug.ll
+++ b/test/CodeGen/XCore/dwarf_debug.ll
@@ -6,15 +6,15 @@
 ; CHECK-LABEL: f
 ; CHECK: entsp 2
 ; ...the prologue...
-; CHECK: .loc 1 2 0 prologue_end      # :2:0
+; CHECK: .loc 1 2 0 prologue_end      # test.c:2:0
 ; CHECK: add r0, r0, 1
 ; CHECK: retsp 2
 define i32 @f(i32 %a) {
 entry:
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !11, metadata !{!"0x102"}), !dbg !12
-  %0 = load i32* %a.addr, align 4, !dbg !12
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !11, metadata !DIExpression()), !dbg !12
+  %0 = load i32, i32* %a.addr, align 4, !dbg !12
   %add = add nsw i32 %0, 1, !dbg !12
   ret i32 %add, !dbg !12
 }
@@ -23,17 +23,16 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata)
 
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!9, !10}
-!0 = !{!"0x11\0012\00\000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ]
-!1 = !{!"", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.c", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00f\00f\00\002\000\001\000\006\00256\000\002", !1, !5, !6, null, i32 (i32)* @f, null, null, !2} ; [ DW_TAG_subprogram ]
-!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ]
+!4 = !DISubprogram(name: "f", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !1, type: !6, function: i32 (i32)* @f, variables: !2)
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 4}
-!10 = !{i32 2, !"Debug Info Version", i32 2}
-!11 = !{!"0x101\00a\0016777218\000", !4, !5, !8} ; [ DW_TAG_arg_variable ]
-!12 = !MDLocation(line: 2, scope: !4)
+!10 = !{i32 2, !"Debug Info Version", i32 3}
+!11 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 2, arg: 1, scope: !4, file: !1, type: !8)
+!12 = !DILocation(line: 2, scope: !4)
 
diff --git a/test/CodeGen/XCore/epilogue_prologue.ll b/test/CodeGen/XCore/epilogue_prologue.ll
index 99978145ed36..923cc4a09e05 100644
--- a/test/CodeGen/XCore/epilogue_prologue.ll
+++ b/test/CodeGen/XCore/epilogue_prologue.ll
@@ -199,9 +199,9 @@ declare void @f5(i32*)
 define i32 @f6(i32 %i) {
 entry:
   %0 = alloca [200000 x i32]
-  %1 = getelementptr inbounds [200000 x i32]* %0, i32 0, i32 0
+  %1 = getelementptr inbounds [200000 x i32], [200000 x i32]* %0, i32 0, i32 0
   call void @f5(i32* %1)
-  %2 = getelementptr inbounds [200000 x i32]* %0, i32 0, i32 199999
+  %2 = getelementptr inbounds [200000 x i32], [200000 x i32]* %0, i32 0, i32 199999
   call void @f5(i32* %2)
   ret i32 %i
 }
@@ -229,7 +229,7 @@ entry:
 define void @f8() nounwind {
 entry:
   %0 = alloca [256 x i32]
-  %1 = getelementptr inbounds [256 x i32]* %0, i32 0, i32 253
+  %1 = getelementptr inbounds [256 x i32], [256 x i32]* %0, i32 0, i32 253
   call void @f5(i32* %1)
   ret void
 }
@@ -257,7 +257,7 @@ entry:
 define void @f9() nounwind {
 entry:
   %0 = alloca [32768 x i32]
-  %1 = getelementptr inbounds [32768 x i32]* %0, i32 0, i32 32765
+  %1 = getelementptr inbounds [32768 x i32], [32768 x i32]* %0, i32 0, i32 32765
   call void @f5(i32* %1)
   ret void
 }
diff --git a/test/CodeGen/XCore/exception.ll b/test/CodeGen/XCore/exception.ll
index fec83eb15ea5..705c6b42ade7 100644
--- a/test/CodeGen/XCore/exception.ll
+++ b/test/CodeGen/XCore/exception.ll
@@ -39,10 +39,10 @@ entry:
   unreachable
 }
 
-; CHECK-LABEL: fn_catch
+; CHECK-LABEL: fn_catch:
+; CHECK-NEXT: [[START:.L[a-zA-Z0-9_]+]]
 ; CHECK: .cfi_startproc
 ; CHECK: .cfi_personality 0, __gxx_personality_v0
-; CHECK: [[START:.L[a-zA-Z0-9_]+]]
 ; CHECK: .cfi_lsda 0, [[LSDA:.L[a-zA-Z0-9_]+]]
 ; CHECK: entsp 4
 ; CHECK: .cfi_def_cfa_offset 16
@@ -78,21 +78,22 @@ cont:
 ; CHECK: bl __cxa_end_catch
 lpad:
   %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
           catch i8* bitcast (i8** @_ZTIi to i8*)
           catch i8* bitcast (i8** @_ZTId to i8*)
   %1 = extractvalue { i8*, i32 } %0, 0
   %2 = extractvalue { i8*, i32 } %0, 1
   %3 = call i8* @__cxa_begin_catch(i8* %1) nounwind
   %4 = bitcast i8* %3 to i32*
-  %5 = load i32* %4
+  %5 = load i32, i32* %4
   call void @__cxa_end_catch() nounwind
 
 ; CHECK: eq r0, r6, r5
 ; CHECK: bf r0, [[RETURN]]
 ; CHECK: mov r0, r4
 ; CHECK: bl _Unwind_Resume
-; CHECK: .cfi_endproc
 ; CHECK: [[END:.L[a-zA-Z0-9_]+]]
+; CHECK: .cfi_endproc
   %6 = icmp eq i32 %5, %2
   br i1 %6, label %Resume, label %Exit
 Resume:
@@ -110,13 +111,14 @@ Exit:
 ; CHECK: .long [[PRE_G]]-[[START]]
 ; CHECK: .long [[POST_G]]-[[PRE_G]]
 ; CHECK: .long [[LANDING]]-[[START]]
-; CHECK: .byte 3
+; CHECK: .byte 5
 ; CHECK: .long [[POST_G]]-[[START]]
 ; CHECK: .long [[END]]-[[POST_G]]
 ; CHECK: .long 0
 ; CHECK: .byte 0
-; CHECK: .byte 1
 ; CHECK: .byte 0
+; CHECK: .byte 1
+; CHECK: .byte 125
 ; CHECK: .byte 2
 ; CHECK: .byte 125
 ; CHECK: .long _ZTIi
diff --git a/test/CodeGen/XCore/indirectbr.ll b/test/CodeGen/XCore/indirectbr.ll
index d7758ea1d57c..9723cdcbdf14 100644
--- a/test/CodeGen/XCore/indirectbr.ll
+++ b/test/CodeGen/XCore/indirectbr.ll
@@ -6,7 +6,7 @@
 define internal i32 @foo(i32 %i) nounwind {
 ; CHECK-LABEL: foo:
 entry:
-  %0 = load i8** @nextaddr, align 4               ; <i8*> [#uses=2]
+  %0 = load i8*, i8** @nextaddr, align 4               ; <i8*> [#uses=2]
   %1 = icmp eq i8* %0, null                       ; <i1> [#uses=1]
   br i1 %1, label %bb3, label %bb2
 
@@ -16,8 +16,8 @@ bb2:                                              ; preds = %entry, %bb3
   indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
 
 bb3:                                              ; preds = %entry
-  %2 = getelementptr inbounds [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1]
-  %gotovar.4.0.pre = load i8** %2, align 4        ; <i8*> [#uses=1]
+  %2 = getelementptr inbounds [5 x i8*], [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1]
+  %gotovar.4.0.pre = load i8*, i8** %2, align 4        ; <i8*> [#uses=1]
   br label %bb2
 
 L5:                                               ; preds = %bb2
diff --git a/test/CodeGen/XCore/llvm-intrinsics.ll b/test/CodeGen/XCore/llvm-intrinsics.ll
index b436282615c2..b7868d350b4a 100644
--- a/test/CodeGen/XCore/llvm-intrinsics.ll
+++ b/test/CodeGen/XCore/llvm-intrinsics.ll
@@ -122,7 +122,7 @@ entry:
 ; CHECK-NEXT: ldw r0, sp[2]
 ; CHECK-NEXT: set sp, r2
 ; CHECK-NEXT: bau r3
-  call void (...)* @foo()
+  call void (...) @foo()
   call void @llvm.eh.return.i32(i32 %offset, i8* %handler)
   unreachable
 }
@@ -144,8 +144,8 @@ entry:
 ; CHECK-NEXT: ldw r0, sp[2]
 ; CHECK-NEXT: set sp, r2
 ; CHECK-NEXT: bau r3
-  call void (...)* @foo()
-  %0 = load i32* @offset
+  call void (...) @foo()
+  %0 = load i32, i32* @offset
   call void @llvm.eh.return.i32(i32 %0, i8* @handler)
   unreachable
 }
@@ -244,7 +244,7 @@ define void @Unwind0() {
 ; CHECK: ldw r4, sp[9]
 ; CHECK: retsp 10
 define void @Unwind1() {
-  call void (...)* @foo()
+  call void (...) @foo()
   call void @llvm.eh.unwind.init()
   ret void
 }
diff --git a/test/CodeGen/XCore/load.ll b/test/CodeGen/XCore/load.ll
index c7fc2a33db1a..bba7f72301f9 100644
--- a/test/CodeGen/XCore/load.ll
+++ b/test/CodeGen/XCore/load.ll
@@ -4,8 +4,8 @@ define i32 @load32(i32* %p, i32 %offset) nounwind {
 entry:
 ; CHECK-LABEL: load32:
 ; CHECK: ldw r0, r0[r1]
-	%0 = getelementptr i32* %p, i32 %offset
-	%1 = load i32* %0, align 4
+	%0 = getelementptr i32, i32* %p, i32 %offset
+	%1 = load i32, i32* %0, align 4
 	ret i32 %1
 }
 
@@ -13,8 +13,8 @@ define i32 @load32_imm(i32* %p) nounwind {
 entry:
 ; CHECK-LABEL: load32_imm:
 ; CHECK: ldw r0, r0[11]
-	%0 = getelementptr i32* %p, i32 11
-	%1 = load i32* %0, align 4
+	%0 = getelementptr i32, i32* %p, i32 11
+	%1 = load i32, i32* %0, align 4
 	ret i32 %1
 }
 
@@ -23,8 +23,8 @@ entry:
 ; CHECK-LABEL: load16:
 ; CHECK: ld16s r0, r0[r1]
 ; CHECK-NOT: sext
-	%0 = getelementptr i16* %p, i32 %offset
-	%1 = load i16* %0, align 2
+	%0 = getelementptr i16, i16* %p, i32 %offset
+	%1 = load i16, i16* %0, align 2
 	%2 = sext i16 %1 to i32
 	ret i32 %2
 }
@@ -34,8 +34,8 @@ entry:
 ; CHECK-LABEL: load8:
 ; CHECK: ld8u r0, r0[r1]
 ; CHECK-NOT: zext
-	%0 = getelementptr i8* %p, i32 %offset
-	%1 = load i8* %0, align 1
+	%0 = getelementptr i8, i8* %p, i32 %offset
+	%1 = load i8, i8* %0, align 1
 	%2 = zext i8 %1 to i32
 	ret i32 %2
 }
@@ -45,6 +45,6 @@ define i32 @load_cp() nounwind {
 entry:
 ; CHECK-LABEL: load_cp:
 ; CHECK: ldw r0, cp[GConst]
-  %0 = load i32* @GConst
+  %0 = load i32, i32* @GConst
   ret i32 %0
 }
diff --git a/test/CodeGen/XCore/offset_folding.ll b/test/CodeGen/XCore/offset_folding.ll
index 8085a0fd28a7..ab29ad587a50 100644
--- a/test/CodeGen/XCore/offset_folding.ll
+++ b/test/CodeGen/XCore/offset_folding.ll
@@ -8,7 +8,7 @@ entry:
 ; CHECK-LABEL: f1:
 ; CHECK: ldaw r11, cp[a+4]
 ; CHECK: mov r0, r11
-	%0 = getelementptr [0 x i32]* @a, i32 0, i32 1
+	%0 = getelementptr [0 x i32], [0 x i32]* @a, i32 0, i32 1
 	ret i32* %0
 }
 
@@ -16,7 +16,7 @@ define i32 *@f2() nounwind {
 entry:
 ; CHECK-LABEL: f2:
 ; CHECK: ldaw r0, dp[b+4]
-	%0 = getelementptr [0 x i32]* @b, i32 0, i32 1
+	%0 = getelementptr [0 x i32], [0 x i32]* @b, i32 0, i32 1
 	ret i32* %0
 }
 
@@ -28,7 +28,7 @@ entry:
 ; CHECK-LABEL: f3:
 ; CHECK: ldaw r11, cp[a]
 ; CHECK: sub r0, r11, 4
-	%0 = getelementptr [0 x i32]* @a, i32 0, i32 -1
+	%0 = getelementptr [0 x i32], [0 x i32]* @a, i32 0, i32 -1
 	ret i32* %0
 }
 
@@ -37,6 +37,6 @@ entry:
 ; CHECK-LABEL: f4:
 ; CHECK: ldaw [[REG:r[0-9]+]], dp[b]
 ; CHECK: sub r0, [[REG]], 4
-	%0 = getelementptr [0 x i32]* @b, i32 0, i32 -1
+	%0 = getelementptr [0 x i32], [0 x i32]* @b, i32 0, i32 -1
 	ret i32* %0
 }
diff --git a/test/CodeGen/XCore/private.ll b/test/CodeGen/XCore/private.ll
index 474448a50888..a188864a866c 100644
--- a/test/CodeGen/XCore/private.ll
+++ b/test/CodeGen/XCore/private.ll
@@ -14,7 +14,7 @@ define i32 @bar() {
 ; CHECK: bl .Lfoo
 ; CHECK: ldw r0, dp[.Lbaz]
         call void @foo()
-	%1 = load i32* @baz, align 4
+	%1 = load i32, i32* @baz, align 4
         ret i32 %1
 }
 
diff --git a/test/CodeGen/XCore/scavenging.ll b/test/CodeGen/XCore/scavenging.ll
index a0c8a2e09379..7b6f54ebec24 100644
--- a/test/CodeGen/XCore/scavenging.ll
+++ b/test/CodeGen/XCore/scavenging.ll
@@ -17,21 +17,21 @@
 define void @f() nounwind {
 entry:
 	%x = alloca [100 x i32], align 4		; <[100 x i32]*> [#uses=2]
-	%0 = load i32* @size, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* @size, align 4		; <i32> [#uses=1]
 	%1 = alloca i32, i32 %0, align 4		; <i32*> [#uses=1]
-	%2 = load volatile i32* @g0, align 4		; <i32> [#uses=1]
-	%3 = load volatile i32* @g1, align 4		; <i32> [#uses=1]
-	%4 = load volatile i32* @g2, align 4		; <i32> [#uses=1]
-	%5 = load volatile i32* @g3, align 4		; <i32> [#uses=1]
-	%6 = load volatile i32* @g4, align 4		; <i32> [#uses=1]
-	%7 = load volatile i32* @g5, align 4		; <i32> [#uses=1]
-	%8 = load volatile i32* @g6, align 4		; <i32> [#uses=1]
-	%9 = load volatile i32* @g7, align 4		; <i32> [#uses=1]
-	%10 = load volatile i32* @g8, align 4		; <i32> [#uses=1]
-	%11 = load volatile i32* @g9, align 4		; <i32> [#uses=1]
-	%12 = load volatile i32* @g10, align 4		; <i32> [#uses=1]
-	%13 = load volatile i32* @g11, align 4		; <i32> [#uses=2]
-	%14 = getelementptr [100 x i32]* %x, i32 0, i32 50		; <i32*> [#uses=1]
+	%2 = load volatile i32, i32* @g0, align 4		; <i32> [#uses=1]
+	%3 = load volatile i32, i32* @g1, align 4		; <i32> [#uses=1]
+	%4 = load volatile i32, i32* @g2, align 4		; <i32> [#uses=1]
+	%5 = load volatile i32, i32* @g3, align 4		; <i32> [#uses=1]
+	%6 = load volatile i32, i32* @g4, align 4		; <i32> [#uses=1]
+	%7 = load volatile i32, i32* @g5, align 4		; <i32> [#uses=1]
+	%8 = load volatile i32, i32* @g6, align 4		; <i32> [#uses=1]
+	%9 = load volatile i32, i32* @g7, align 4		; <i32> [#uses=1]
+	%10 = load volatile i32, i32* @g8, align 4		; <i32> [#uses=1]
+	%11 = load volatile i32, i32* @g9, align 4		; <i32> [#uses=1]
+	%12 = load volatile i32, i32* @g10, align 4		; <i32> [#uses=1]
+	%13 = load volatile i32, i32* @g11, align 4		; <i32> [#uses=2]
+	%14 = getelementptr [100 x i32], [100 x i32]* %x, i32 0, i32 50		; <i32*> [#uses=1]
 	store i32 %13, i32* %14, align 4
 	store volatile i32 %13, i32* @g11, align 4
 	store volatile i32 %12, i32* @g10, align 4
@@ -45,7 +45,7 @@ entry:
 	store volatile i32 %4, i32* @g2, align 4
 	store volatile i32 %3, i32* @g1, align 4
 	store volatile i32 %2, i32* @g0, align 4
-	%x1 = getelementptr [100 x i32]* %x, i32 0, i32 0		; <i32*> [#uses=1]
+	%x1 = getelementptr [100 x i32], [100 x i32]* %x, i32 0, i32 0		; <i32*> [#uses=1]
 	call void @g(i32* %x1, i32* %1) nounwind
 	ret void
 }
@@ -103,15 +103,15 @@ declare void @g(i32*, i32*)
 define void @ScavengeSlots(i32 %r0, i32 %r1, i32 %r2, i32 %r3, i32 %r4) nounwind {
 entry:
   %Data = alloca [100000 x i32]
-  %i0 = getelementptr inbounds [100000 x i32]* %Data, i32 0, i32 80000
+  %i0 = getelementptr inbounds [100000 x i32], [100000 x i32]* %Data, i32 0, i32 80000
   store volatile i32 %r0, i32* %i0
-  %i1 = getelementptr inbounds [100000 x i32]* %Data, i32 0, i32 81000
+  %i1 = getelementptr inbounds [100000 x i32], [100000 x i32]* %Data, i32 0, i32 81000
   store volatile i32 %r1, i32* %i1
-  %i2 = getelementptr inbounds [100000 x i32]* %Data, i32 0, i32 82000
+  %i2 = getelementptr inbounds [100000 x i32], [100000 x i32]* %Data, i32 0, i32 82000
   store volatile i32 %r2, i32* %i2
-  %i3 = getelementptr inbounds [100000 x i32]* %Data, i32 0, i32 83000
+  %i3 = getelementptr inbounds [100000 x i32], [100000 x i32]* %Data, i32 0, i32 83000
   store volatile i32 %r3, i32* %i3
-  %i4 = getelementptr inbounds [100000 x i32]* %Data, i32 0, i32 84000
+  %i4 = getelementptr inbounds [100000 x i32], [100000 x i32]* %Data, i32 0, i32 84000
   store volatile i32 %r4, i32* %i4
   ret void
 }
diff --git a/test/CodeGen/XCore/store.ll b/test/CodeGen/XCore/store.ll
index 87553d8da18a..a42b444bdff4 100644
--- a/test/CodeGen/XCore/store.ll
+++ b/test/CodeGen/XCore/store.ll
@@ -4,7 +4,7 @@ define void @store32(i32* %p, i32 %offset, i32 %val) nounwind {
 entry:
 ; CHECK-LABEL: store32:
 ; CHECK: stw r2, r0[r1]
-	%0 = getelementptr i32* %p, i32 %offset
+	%0 = getelementptr i32, i32* %p, i32 %offset
 	store i32 %val, i32* %0, align 4
 	ret void
 }
@@ -13,7 +13,7 @@ define void @store32_imm(i32* %p, i32 %val) nounwind {
 entry:
 ; CHECK-LABEL: store32_imm:
 ; CHECK: stw r1, r0[11]
-	%0 = getelementptr i32* %p, i32 11
+	%0 = getelementptr i32, i32* %p, i32 11
 	store i32 %val, i32* %0, align 4
 	ret void
 }
@@ -22,7 +22,7 @@ define void @store16(i16* %p, i32 %offset, i16 %val) nounwind {
 entry:
 ; CHECK-LABEL: store16:
 ; CHECK: st16 r2, r0[r1]
-	%0 = getelementptr i16* %p, i32 %offset
+	%0 = getelementptr i16, i16* %p, i32 %offset
 	store i16 %val, i16* %0, align 2
 	ret void
 }
@@ -31,7 +31,7 @@ define void @store8(i8* %p, i32 %offset, i8 %val) nounwind {
 entry:
 ; CHECK-LABEL: store8:
 ; CHECK: st8 r2, r0[r1]
-	%0 = getelementptr i8* %p, i32 %offset
+	%0 = getelementptr i8, i8* %p, i32 %offset
 	store i8 %val, i8* %0, align 1
 	ret void
 }
diff --git a/test/CodeGen/XCore/threads.ll b/test/CodeGen/XCore/threads.ll
index c50da1d5934e..0c25314295d7 100644
--- a/test/CodeGen/XCore/threads.ll
+++ b/test/CodeGen/XCore/threads.ll
@@ -78,7 +78,7 @@ define i32* @f_tl() {
 ; CHECK: ldc [[R2:r[0-9]]], 12
 ; r0 = id*12 + 8 + &tl
 ; CHECK: lmul {{r[0-9]}}, r0, r11, [[R2]], [[R0]], [[R1]]
-  ret i32* getelementptr inbounds ([3 x i32]* @tl, i32 0, i32 2)
+  ret i32* getelementptr inbounds ([3 x i32], [3 x i32]* @tl, i32 0, i32 2)
 }
 
 define i32* @f_tle() {
@@ -88,7 +88,7 @@ define i32* @f_tle() {
 ; CHECK: ldaw [[R1:r[0-9]]], dp[tle]
 ; r0 = &tl + id*8
 ; CHECK: add r0, [[R1]], [[R0]]
-  ret i32* getelementptr inbounds ([2 x i32]* @tle, i32 0, i32 0)
+  ret i32* getelementptr inbounds ([2 x i32], [2 x i32]* @tle, i32 0, i32 0)
 }
 
 define i32 @f_tlExpr () {
@@ -99,8 +99,8 @@ define i32 @f_tlExpr () {
 ; CHECK: add [[R2:r[0-9]]], [[R1]], [[R0]]
 ; CHECK: add r0, [[R2]], [[R2]]
   ret i32 add(
-      i32 ptrtoint( i32* getelementptr inbounds ([2 x i32]* @tle, i32 0, i32 0) to i32),
-      i32 ptrtoint( i32* getelementptr inbounds ([2 x i32]* @tle, i32 0, i32 0) to i32))
+      i32 ptrtoint( i32* getelementptr inbounds ([2 x i32], [2 x i32]* @tle, i32 0, i32 0) to i32),
+      i32 ptrtoint( i32* getelementptr inbounds ([2 x i32], [2 x i32]* @tle, i32 0, i32 0) to i32))
 }
 
 define void @phiNode1() {
@@ -113,8 +113,8 @@ define void @phiNode1() {
 entry:
   br label %ConstantExpPhiNode
 ConstantExpPhiNode:
-  %ptr = phi i32* [ getelementptr inbounds ([3 x i32]* @tl, i32 0, i32 0), %entry ],
-                  [ getelementptr inbounds ([3 x i32]* @tl, i32 0, i32 0), %ConstantExpPhiNode ]
+  %ptr = phi i32* [ getelementptr inbounds ([3 x i32], [3 x i32]* @tl, i32 0, i32 0), %entry ],
+                  [ getelementptr inbounds ([3 x i32], [3 x i32]* @tl, i32 0, i32 0), %ConstantExpPhiNode ]
   br label %ConstantExpPhiNode
 exit:
   ret void
@@ -134,8 +134,8 @@ define void @phiNode2( i1 %bool) {
 entry:
   br i1 %bool, label %ConstantExpPhiNode, label %exit
 ConstantExpPhiNode:
-  %ptr = phi i32* [ getelementptr inbounds ([3 x i32]* @tl, i32 0, i32 0), %entry ],
-                  [ getelementptr inbounds ([3 x i32]* @tl, i32 0, i32 0), %ConstantExpPhiNode ]
+  %ptr = phi i32* [ getelementptr inbounds ([3 x i32], [3 x i32]* @tl, i32 0, i32 0), %entry ],
+                  [ getelementptr inbounds ([3 x i32], [3 x i32]* @tl, i32 0, i32 0), %ConstantExpPhiNode ]
   br label %ConstantExpPhiNode
 exit:
   ret void
diff --git a/test/CodeGen/XCore/trampoline.ll b/test/CodeGen/XCore/trampoline.ll
index 7ca331a60673..a7280000500f 100644
--- a/test/CodeGen/XCore/trampoline.ll
+++ b/test/CodeGen/XCore/trampoline.ll
@@ -9,14 +9,14 @@ entry:
 ; CHECK: stw r11, sp[7]
   %TRAMP.23 = alloca [20 x i8], align 2
   %FRAME.0 = alloca %struct.FRAME.f, align 4
-  %TRAMP.23.sub = getelementptr inbounds [20 x i8]* %TRAMP.23, i32 0, i32 0
+  %TRAMP.23.sub = getelementptr inbounds [20 x i8], [20 x i8]* %TRAMP.23, i32 0, i32 0
   %FRAME.02 = bitcast %struct.FRAME.f* %FRAME.0 to i8*
   call void @llvm.init.trampoline(i8* %TRAMP.23.sub, i8* bitcast (i32 (%struct.FRAME.f*)* @g.1101 to i8*), i8* %FRAME.02)
   %tramp = call i8* @llvm.adjust.trampoline(i8* %TRAMP.23.sub)
-  %0 = getelementptr inbounds %struct.FRAME.f* %FRAME.0, i32 0, i32 1
+  %0 = getelementptr inbounds %struct.FRAME.f, %struct.FRAME.f* %FRAME.0, i32 0, i32 1
   %1 = bitcast i8* %tramp to i32 ()*
   store i32 ()* %1, i32 ()** %0, align 4
-  %2 = getelementptr inbounds %struct.FRAME.f* %FRAME.0, i32 0, i32 0
+  %2 = getelementptr inbounds %struct.FRAME.f, %struct.FRAME.f* %FRAME.0, i32 0, i32 0
   store i32 1, i32* %2, align 4
   call void @h(i32 ()* %1) nounwind
   ret void
@@ -28,8 +28,8 @@ entry:
 ; CHECK: ldw r11, sp[0]
 ; CHECK-NEXT: ldw r0, r11[0]
 ; CHECK-NEXT: retsp 0
-  %0 = getelementptr inbounds %struct.FRAME.f* %CHAIN.1, i32 0, i32 0
-  %1 = load i32* %0, align 4
+  %0 = getelementptr inbounds %struct.FRAME.f, %struct.FRAME.f* %CHAIN.1, i32 0, i32 0
+  %1 = load i32, i32* %0, align 4
   ret i32 %1
 }
 
diff --git a/test/CodeGen/XCore/unaligned_load.ll b/test/CodeGen/XCore/unaligned_load.ll
index b8b88275538c..325da8f4432d 100644
--- a/test/CodeGen/XCore/unaligned_load.ll
+++ b/test/CodeGen/XCore/unaligned_load.ll
@@ -5,7 +5,7 @@
 ; CHECK: bl __misaligned_load
 define i32 @align1(i32* %p) nounwind {
 entry:
-	%0 = load i32* %p, align 1		; <i32> [#uses=1]
+	%0 = load i32, i32* %p, align 1		; <i32> [#uses=1]
 	ret i32 %0
 }
 
@@ -16,7 +16,7 @@ entry:
 ; CHECK: or
 define i32 @align2(i32* %p) nounwind {
 entry:
-	%0 = load i32* %p, align 2		; <i32> [#uses=1]
+	%0 = load i32, i32* %p, align 2		; <i32> [#uses=1]
 	ret i32 %0
 }
 
@@ -29,6 +29,6 @@ entry:
 ; CHECK: or
 define i32 @align3() nounwind {
 entry:
-	%0 = load i32* bitcast (i8* getelementptr ([5 x i8]* @a, i32 0, i32 1) to i32*), align 1
+	%0 = load i32, i32* bitcast (i8* getelementptr ([5 x i8], [5 x i8]* @a, i32 0, i32 1) to i32*), align 1
 	ret i32 %0
 }
diff --git a/test/CodeGen/XCore/unaligned_store_combine.ll b/test/CodeGen/XCore/unaligned_store_combine.ll
index d1f4e6c15cd5..4b29a05984a1 100644
--- a/test/CodeGen/XCore/unaligned_store_combine.ll
+++ b/test/CodeGen/XCore/unaligned_store_combine.ll
@@ -7,7 +7,7 @@ entry:
 ; CHECK-LABEL: f:
 ; CHECK: ldc r2, 8
 ; CHECK: bl memmove
-	%0 = load i64* %src, align 1
+	%0 = load i64, i64* %src, align 1
 	store i64 %0, i64* %dst, align 1
 	ret void
 }
diff --git a/test/CodeGen/XCore/zextfree.ll b/test/CodeGen/XCore/zextfree.ll
index 48dce8865328..d1e2b7f85784 100644
--- a/test/CodeGen/XCore/zextfree.ll
+++ b/test/CodeGen/XCore/zextfree.ll
@@ -4,7 +4,7 @@
 ; CHECK-NOT: zext
 define void @test(i8* %s1) {
 entry:
-  %u8 = load i8* %s1, align 1
+  %u8 = load i8, i8* %s1, align 1
   %bool = icmp eq i8 %u8, 0
   br label %BB1
 BB1:
diff --git a/test/DebugInfo/2009-11-03-InsertExtractValue.ll b/test/DebugInfo/2009-11-03-InsertExtractValue.ll
index 0b9f1b5ad948..f8382af3abc7 100644
--- a/test/DebugInfo/2009-11-03-InsertExtractValue.ll
+++ b/test/DebugInfo/2009-11-03-InsertExtractValue.ll
@@ -4,12 +4,12 @@
 !llvm.dbg.cu = !{!5}
 !llvm.module.flags = !{!6}
 
-!0 = !{!"0x2e\00bar\00bar\00_ZN3foo3barEv\003\000\000\000\006\00258\000\003", !4, !1, !2, null, null, null, i32 0, !1} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !4} ; [ DW_TAG_file_type ]
-!2 = !{!"0x15\00\000\000\000\000\000\000", !4, !1, null, !3, null} ; [ DW_TAG_subroutine_type ]
+!0 = !DISubprogram(name: "bar", linkageName: "_ZN3foo3barEv", line: 3, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagProtected | DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !4, scope: !1, type: !2)
+!1 = !DIFile(filename: "/foo", directory: "bar.cpp")
+!2 = !DISubroutineType(types: !3)
 !3 = !{null}
-!4 = !{!"/foo", !"bar.cpp"}
-!5 = !{!"0x11\0012\00\001\00\000\00\000", !4, !3, !3, null, null, null}; [DW_TAG_compile_unit ]
+!4 = !DIFile(filename: "/foo", directory: "bar.cpp")
+!5 = !DICompileUnit(language: DW_LANG_C99, isOptimized: true, emissionKind: 0, file: !4, enums: !{}, retainedTypes: !{})
 
 define <{i32, i32}> @f1() {
 ; CHECK: !dbgx ![[NUMBER:[0-9]+]]
@@ -19,5 +19,5 @@ define <{i32, i32}> @f1() {
   ret <{ i32, i32 }> %r
 }
 
-; CHECK: [protected]
-!6 = !{i32 1, !"Debug Info Version", i32 2}
+; CHECK: DIFlagProtected
+!6 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/2009-11-05-DeadGlobalVariable.ll b/test/DebugInfo/2009-11-05-DeadGlobalVariable.ll
index c73b945a7dbd..32d4c0ac6c39 100644
--- a/test/DebugInfo/2009-11-05-DeadGlobalVariable.ll
+++ b/test/DebugInfo/2009-11-05-DeadGlobalVariable.ll
@@ -10,17 +10,17 @@ entry:
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!18}
 
-!0 = !{!"0x11\0012\00clang version 3.0 (trunk 139632)\001\00\000\00\000", !17, !1, !1, !3, !12, null} ; [ DW_TAG_compile_unit ]
-!1 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 139632)", isOptimized: true, emissionKind: 0, file: !17, enums: !1, retainedTypes: !1, subprograms: !3, globals: !12)
+!1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\000\001\000", !17, !6, !7, null, i32 ()* @foo, null, null, null} ; [ DW_TAG_subprogram ] [line 1] [def] [scope 0] [foo]
-!6 = !{!"0x29", !17} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, file: !17, scope: !6, type: !7, function: i32 ()* @foo)
+!6 = !DIFile(filename: "fb.c", directory: "/private/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !12 = !{!14}
-!14 = !{!"0x34\00bar\00bar\00\002\001\001", !5, !6, !9, null, null} ; [ DW_TAG_variable ]
-!15 = !MDLocation(line: 3, column: 3, scope: !16)
-!16 = !{!"0xb\001\0011\000", !17, !5} ; [ DW_TAG_lexical_block ]
-!17 = !{!"fb.c", !"/private/tmp"}
-!18 = !{i32 1, !"Debug Info Version", i32 2}
+!14 = !DIGlobalVariable(name: "bar", line: 2, isLocal: true, isDefinition: true, scope: !5, file: !6, type: !9)
+!15 = !DILocation(line: 3, column: 3, scope: !16)
+!16 = distinct !DILexicalBlock(line: 1, column: 11, file: !17, scope: !5)
+!17 = !DIFile(filename: "fb.c", directory: "/private/tmp")
+!18 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/2009-11-06-NamelessGlobalVariable.ll b/test/DebugInfo/2009-11-06-NamelessGlobalVariable.ll
index 1b7c80f1f091..79f949b438f8 100644
--- a/test/DebugInfo/2009-11-06-NamelessGlobalVariable.ll
+++ b/test/DebugInfo/2009-11-06-NamelessGlobalVariable.ll
@@ -4,11 +4,11 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!9}
 
-!0 = !{!"0x11\0012\00clang version 3.0 (trunk 139632)\001\00\000\00\000", !8, !2, !2, !2, !3, null} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 139632)", isOptimized: true, emissionKind: 0, file: !8, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3)
 !2 = !{}
 !3 = !{!5}
-!5 = !{!"0x34\00a\00a\00\002\000\001", null, !6, !7, i32* @0, null} ; [ DW_TAG_variable ]
-!6 = !{!"0x29", !8} ; [ DW_TAG_file_type ]
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!8 = !{!"g.c", !"/private/tmp"}
-!9 = !{i32 1, !"Debug Info Version", i32 2}
+!5 = !DIGlobalVariable(name: "a", line: 2, isLocal: false, isDefinition: true, scope: null, file: !6, type: !7, variable: i32* @0)
+!6 = !DIFile(filename: "g.c", directory: "/private/tmp")
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DIFile(filename: "g.c", directory: "/private/tmp")
+!9 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/2009-11-10-CurrentFn.ll b/test/DebugInfo/2009-11-10-CurrentFn.ll
index bf237eee23fb..228edec93c42 100644
--- a/test/DebugInfo/2009-11-10-CurrentFn.ll
+++ b/test/DebugInfo/2009-11-10-CurrentFn.ll
@@ -2,7 +2,7 @@
 
 define void @bar(i32 %i) nounwind uwtable ssp {
 entry:
-  tail call void (...)* @foo() nounwind, !dbg !14
+  tail call void (...) @foo() nounwind, !dbg !14
   ret void, !dbg !16
 }
 
@@ -13,19 +13,19 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!18}
 
-!0 = !{!"0x11\0012\00clang version 3.0 (trunk 139632)\001\00\000\00\000", !17, !1, !1, !3, !1, null} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 139632)", isOptimized: true, emissionKind: 0, file: !17, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00bar\00bar\00\003\000\001\000\006\00256\001\000", !17, !6, !7, null, void (i32)* @bar, null, null, !9} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 0] [bar]
-!6 = !{!"0x29", !17} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "bar", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !17, scope: !6, type: !7, function: void (i32)* @bar, variables: !9)
+!6 = !DIFile(filename: "cf.c", directory: "/private/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null}
 !9 = !{!11}
-!11 = !{!"0x101\00i\0016777219\000", !17, !5, !12} ; [ DW_TAG_arg_variable ]
-!12 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!13 = !MDLocation(line: 3, column: 14, scope: !5)
-!14 = !MDLocation(line: 4, column: 3, scope: !15)
-!15 = !{!"0xb\003\0017\000", !17, !5} ; [ DW_TAG_lexical_block ]
-!16 = !MDLocation(line: 5, column: 1, scope: !15)
-!17 = !{!"cf.c", !"/private/tmp"}
-!18 = !{i32 1, !"Debug Info Version", i32 2}
+!11 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 3, arg: 1, scope: !5, file: !17, type: !12)
+!12 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!13 = !DILocation(line: 3, column: 14, scope: !5)
+!14 = !DILocation(line: 4, column: 3, scope: !15)
+!15 = distinct !DILexicalBlock(line: 3, column: 17, file: !17, scope: !5)
+!16 = !DILocation(line: 5, column: 1, scope: !15)
+!17 = !DIFile(filename: "cf.c", directory: "/private/tmp")
+!18 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/2010-01-05-DbgScope.ll b/test/DebugInfo/2010-01-05-DbgScope.ll
index d55972024dda..d5baa1984227 100644
--- a/test/DebugInfo/2010-01-05-DbgScope.ll
+++ b/test/DebugInfo/2010-01-05-DbgScope.ll
@@ -2,7 +2,7 @@
 ; PR 5942
 define i8* @foo() nounwind {
 entry:
-  %0 = load i32* undef, align 4, !dbg !0          ; <i32> [#uses=1]
+  %0 = load i32, i32* undef, align 4, !dbg !0          ; <i32> [#uses=1]
   %1 = inttoptr i32 %0 to i8*, !dbg !0            ; <i8*> [#uses=1]
   ret i8* %1, !dbg !10
 
@@ -11,15 +11,15 @@ entry:
 !llvm.dbg.cu = !{!3}
 !llvm.module.flags = !{!14}
 
-!0 = !MDLocation(line: 571, column: 3, scope: !1)
-!1 = !{!"0xb\001\001\000", !11, !2}; [DW_TAG_lexical_block ]
-!2 = !{!"0x2e\00foo\00foo\00foo\00561\000\001\000\006\000\000\000", i32 0, !3, !4, null, null, null, null, null}; [DW_TAG_subprogram ]
-!3 = !{!"0x11\0012\00clang 1.1\001\00\000\00\000", !11, !12, !12, !13, null, null}; [DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", null, !3, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocation(line: 571, column: 3, scope: !1)
+!1 = distinct !DILexicalBlock(line: 1, column: 1, file: !11, scope: !2)
+!2 = !DISubprogram(name: "foo", linkageName: "foo", line: 561, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !3, type: !4)
+!3 = !DICompileUnit(language: DW_LANG_C99, producer: "clang 1.1", isOptimized: true, emissionKind: 0, file: !11, enums: !12, retainedTypes: !12, subprograms: !13)
+!4 = !DISubroutineType(types: !5)
 !5 = !{!6}
-!6 = !{!"0x24\00char\000\008\008\000\000\006", null, !3} ; [ DW_TAG_base_type ]
-!10 = !MDLocation(line: 588, column: 1, scope: !2)
-!11 = !{!"hashtab.c", !"/usr/src/gnu/usr.bin/cc/cc_tools/../../../../contrib/gcclibs/libiberty"}
-!12 = !{i32 0}
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!10 = !DILocation(line: 588, column: 1, scope: !2)
+!11 = !DIFile(filename: "hashtab.c", directory: "/usr/src/gnu/usr.bin/cc/cc_tools/../../../../contrib/gcclibs/libiberty")
+!12 = !{}
 !13 = !{!2}
-!14 = !{i32 1, !"Debug Info Version", i32 2}
+!14 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/2010-03-12-llc-crash.ll b/test/DebugInfo/2010-03-12-llc-crash.ll
index 1b0d794ab78b..60e657ce5ce6 100644
--- a/test/DebugInfo/2010-03-12-llc-crash.ll
+++ b/test/DebugInfo/2010-03-12-llc-crash.ll
@@ -5,18 +5,18 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 
 define void @foo() {
 entry:
-  call void @llvm.dbg.declare(metadata i32* undef, metadata !0, metadata !{!"0x102"})
+  call void @llvm.dbg.declare(metadata i32* undef, metadata !0, metadata !DIExpression()), !dbg !DILocation(scope: !1)
   ret void
 }
 
-!0 = !{!"0x101\00sy\00890\000", !1, !2, !7} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00foo\00foo\00foo\00892\000\001\000\006\000\000\000", !8, !3, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !8} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\004\00clang 1.1\001\00\000\00\000", !9, !10, !10, null, null, null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !9, !5, null, !6, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!5 = !{!"0x29", !9} ; [ DW_TAG_file_type ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "sy", line: 890, arg: 0, scope: !1, file: !2, type: !7)
+!1 = !DISubprogram(name: "foo", linkageName: "foo", line: 892, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !8, scope: !3, type: !4)
+!2 = !DIFile(filename: "qpainter.h", directory: "QtGui")
+!3 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang 1.1", isOptimized: true, emissionKind: 0, file: !9, enums: !10, retainedTypes: !10)
+!4 = !DISubroutineType(types: !6)
+!5 = !DIFile(filename: "splineeditor.cpp", directory: "src")
 !6 = !{null}
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", !9, !5} ; [ DW_TAG_base_type ]
-!8 = !{!"qpainter.h", !"QtGui"}
-!9 = !{!"splineeditor.cpp", !"src"}
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DIFile(filename: "qpainter.h", directory: "QtGui")
+!9 = !DIFile(filename: "splineeditor.cpp", directory: "src")
 !10 = !{i32 0}
diff --git a/test/DebugInfo/2010-03-19-DbgDeclare.ll b/test/DebugInfo/2010-03-19-DbgDeclare.ll
index 831680160987..40d96e1d443e 100644
--- a/test/DebugInfo/2010-03-19-DbgDeclare.ll
+++ b/test/DebugInfo/2010-03-19-DbgDeclare.ll
@@ -1,19 +1,20 @@
 ; RUN: opt < %s -verify -S | FileCheck %s
 
-; CHECK: [DW_LANG_Mips_Assembler]
+; CHECK: DW_LANG_Mips_Assembler
 
 define void @Foo(i32 %a, i32 %b) {
 entry:
-  call void @llvm.dbg.declare(metadata i32* null, metadata !1, metadata !{!"0x102"})
+  call void @llvm.dbg.declare(metadata i32* null, metadata !1, metadata !DIExpression()), !dbg !DILocation(scope: !6)
   ret void
 }
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!5}
-!2 = !{!"0x11\0032769\00clang version 3.3 \000\00\000\00\001", !4, !3, !3, !3, !3,  !3} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/blaikie/dev/scratch/scratch.cpp] [lang 0x8001]
+!2 = !DICompileUnit(language: DW_LANG_Mips_Assembler, producer: "clang version 3.3 ", isOptimized: false, emissionKind: 1, file: !4, enums: !3, retainedTypes: !3, subprograms: !3, globals: !3, imports:  !3)
 !3 = !{}
-!0 = !MDLocation(line: 662302, column: 26, scope: !1)
-!1 = !{i32 4, !"foo"}
-!4 = !{!"scratch.cpp", !"/usr/local/google/home/blaikie/dev/scratch"}
+!0 = !DILocation(line: 662302, column: 26, scope: !1)
+!1 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "foo", scope: !6)
+!4 = !DIFile(filename: "scratch.cpp", directory: "/usr/local/google/home/blaikie/dev/scratch")
+!6 = !DISubprogram()
 
 declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
-!5 = !{i32 1, !"Debug Info Version", i32 2}
+!5 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/2010-03-24-MemberFn.ll b/test/DebugInfo/2010-03-24-MemberFn.ll
index 7b091095048d..627364ea4f00 100644
--- a/test/DebugInfo/2010-03-24-MemberFn.ll
+++ b/test/DebugInfo/2010-03-24-MemberFn.ll
@@ -8,15 +8,15 @@ entry:
   %0 = alloca i32                                 ; <i32*> [#uses=2]
   %s1 = alloca %struct.S                          ; <%struct.S*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.declare(metadata %struct.S* %s1, metadata !0, metadata !{!"0x102"}), !dbg !16
+  call void @llvm.dbg.declare(metadata %struct.S* %s1, metadata !0, metadata !DIExpression()), !dbg !16
   %1 = call i32 @_ZN1S3fooEv(%struct.S* %s1) nounwind, !dbg !17 ; <i32> [#uses=1]
   store i32 %1, i32* %0, align 4, !dbg !17
-  %2 = load i32* %0, align 4, !dbg !17            ; <i32> [#uses=1]
+  %2 = load i32, i32* %0, align 4, !dbg !17            ; <i32> [#uses=1]
   store i32 %2, i32* %retval, align 4, !dbg !17
   br label %return, !dbg !17
 
 return:                                           ; preds = %entry
-  %retval1 = load i32* %retval, !dbg !17          ; <i32> [#uses=1]
+  %retval1 = load i32, i32* %retval, !dbg !17          ; <i32> [#uses=1]
   ret i32 %retval1, !dbg !16
 }
 
@@ -25,12 +25,12 @@ entry:
   %this_addr = alloca %struct.S*                  ; <%struct.S**> [#uses=1]
   %retval = alloca i32                            ; <i32*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.declare(metadata %struct.S** %this_addr, metadata !18, metadata !{!"0x102"}), !dbg !21
+  call void @llvm.dbg.declare(metadata %struct.S** %this_addr, metadata !18, metadata !DIExpression()), !dbg !21
   store %struct.S* %this, %struct.S** %this_addr
   br label %return, !dbg !21
 
 return:                                           ; preds = %entry
-  %retval1 = load i32* %retval, !dbg !21          ; <i32> [#uses=1]
+  %retval1 = load i32, i32* %retval, !dbg !21          ; <i32> [#uses=1]
   ret i32 %retval1, !dbg !22
 }
 
@@ -39,32 +39,32 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!5}
 !llvm.module.flags = !{!28}
 
-!0 = !{!"0x100\00s1\003\000", !1, !4, !9} ; [ DW_TAG_auto_variable ]
-!1 = !{!"0xb\003\000\000", !25, !2} ; [ DW_TAG_lexical_block ]
-!2 = !{!"0xb\003\000\000", !25, !3} ; [ DW_TAG_lexical_block ]
-!3 = !{!"0x2e\00bar\00bar\00_Z3barv\003\000\001\000\006\000\000\003", !25, !4, !6, null, i32 ()* @_Z3barv, null, null, null} ; [ DW_TAG_subprogram ]
-!4 = !{!"0x29", !25} ; [ DW_TAG_file_type ]
-!5 = !{!"0x11\004\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\000\00\000\00\000", !25, !27, !27, !24, null,  null} ; [ DW_TAG_compile_unit ]
-!6 = !{!"0x15\00\000\000\000\000\000\000", !25, !4, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "s1", line: 3, scope: !1, file: !4, type: !9)
+!1 = distinct !DILexicalBlock(line: 3, column: 0, file: !25, scope: !2)
+!2 = distinct !DILexicalBlock(line: 3, column: 0, file: !25, scope: !3)
+!3 = !DISubprogram(name: "bar", linkageName: "_Z3barv", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 3, file: !25, scope: !4, type: !6, function: i32 ()* @_Z3barv)
+!4 = !DIFile(filename: "one.cc", directory: "/tmp/")
+!5 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: false, emissionKind: 0, file: !25, enums: !27, retainedTypes: !27, subprograms: !24, imports:  null)
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", !25, !4} ; [ DW_TAG_base_type ]
-!9 = !{!"0x13\00S\002\008\008\000\000\000", !26, !4, null, !11, null, null, null} ; [ DW_TAG_structure_type ] [S] [line 2, size 8, align 8, offset 0] [def] [from ]
-!10 = !{!"0x29", !26} ; [ DW_TAG_file_type ]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DICompositeType(tag: DW_TAG_structure_type, name: "S", line: 2, size: 8, align: 8, file: !26, scope: !4, elements: !11)
+!10 = !DIFile(filename: "one.h", directory: "/tmp/")
 !11 = !{!12}
-!12 = !{!"0x2e\00foo\00foo\00_ZN1S3fooEv\003\000\001\000\006\000\000\003", !26, !9, !13, null, i32 (%struct.S*)* @_ZN1S3fooEv, null, null, null} ; [ DW_TAG_subprogram ]
-!13 = !{!"0x15\00\000\000\000\000\000\000", !25, null, null, !14, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = !DISubprogram(name: "foo", linkageName: "_ZN1S3fooEv", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 3, file: !26, scope: !9, type: !13, function: i32 (%struct.S*)* @_ZN1S3fooEv)
+!13 = !DISubroutineType(types: !14)
 !14 = !{!8, !15}
-!15 = !{!"0xf\00\000\0064\0064\000\0064", !25, !4, !9} ; [ DW_TAG_pointer_type ]
-!16 = !MDLocation(line: 3, scope: !1)
-!17 = !MDLocation(line: 3, scope: !3)
-!18 = !{!"0x101\00this\003\000", !12, !10, !19} ; [ DW_TAG_arg_variable ]
-!19 = !{!"0x26\00\000\0064\0064\000\0064", !25, !4, !20} ; [ DW_TAG_const_type ]
-!20 = !{!"0xf\00\000\0064\0064\000\000", !25, !4, !9} ; [ DW_TAG_pointer_type ]
-!21 = !MDLocation(line: 3, scope: !12)
-!22 = !MDLocation(line: 3, scope: !23)
-!23 = !{!"0xb\003\000\000", !26, !12} ; [ DW_TAG_lexical_block ]
+!15 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, file: !25, scope: !4, baseType: !9)
+!16 = !DILocation(line: 3, scope: !1)
+!17 = !DILocation(line: 3, scope: !3)
+!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 3, arg: 0, scope: !12, file: !10, type: !19)
+!19 = !DIDerivedType(tag: DW_TAG_const_type, size: 64, align: 64, flags: DIFlagArtificial, file: !25, scope: !4, baseType: !20)
+!20 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !25, scope: !4, baseType: !9)
+!21 = !DILocation(line: 3, scope: !12)
+!22 = !DILocation(line: 3, scope: !23)
+!23 = distinct !DILexicalBlock(line: 3, column: 0, file: !26, scope: !12)
 !24 = !{!3, !12}
-!25 = !{!"one.cc", !"/tmp/"}
-!26 = !{!"one.h", !"/tmp/"}
-!27 = !{i32 0}
-!28 = !{i32 1, !"Debug Info Version", i32 2}
+!25 = !DIFile(filename: "one.cc", directory: "/tmp/")
+!26 = !DIFile(filename: "one.h", directory: "/tmp/")
+!27 = !{}
+!28 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/2010-03-30-InvalidDbgInfoCrash.ll b/test/DebugInfo/2010-03-30-InvalidDbgInfoCrash.ll
deleted file mode 100644
index c967f73550fb..000000000000
--- a/test/DebugInfo/2010-03-30-InvalidDbgInfoCrash.ll
+++ /dev/null
@@ -1,36 +0,0 @@
-; RUN: llc < %s -o /dev/null
-
-define void @baz(i32 %i) nounwind ssp {
-entry:
-  call void @llvm.dbg.declare(metadata !0, metadata !1, metadata !{!"0x102"}), !dbg !0
-  ret void, !dbg !0
-}
-
-declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
-
-!llvm.dbg.cu = !{!5}
-!llvm.module.flags = !{!22}
-
-!0 = !{{ [0 x i8] }** undef}
-!1 = !{!"0x100\00x\0011\000", !2, !4, !9} ; [ DW_TAG_auto_variable ]
-!2 = !{!"0xb\008\000\000", !20, !3} ; [ DW_TAG_lexical_block ]
-!3 = !{!"0x2e\00baz\00baz\00baz\008\001\001\000\006\000\000\000", !20, null, !6, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!4 = !{!"0x29", !20} ; [ DW_TAG_file_type ]
-!5 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\001\00\000\00\000", !20, !21, !21, null, null, null} ; [ DW_TAG_compile_unit ]
-!6 = !{!"0x15\00\000\000\000\000\000\000", !20, !4, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!7 = !{null, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", !20, !4} ; [ DW_TAG_base_type ]
-!9 = !{!"0xf\00\000\0064\0064\000\000", !20, !4, !10} ; [ DW_TAG_pointer_type ]
-!10 = !{!"0x13\00\0011\008\008\000\000\000", !20, !3, null, !11, null, null, null} ; [ DW_TAG_structure_type ] [line 11, size 8, align 8, offset 0] [def] [from ]
-!11 = !{!12}
-!12 = !{!"0xd\00b\0011\008\008\000\000", !20, !10, !13} ; [ DW_TAG_member ]
-!13 = !{!"0x16\00A\0011\000\000\000\000", !20, !3, !14} ; [ DW_TAG_typedef ]
-!14 = !{!"0x1\00\000\008\008\000\000", !20, !4, !15, !16, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 8, align 8, offset 0] [from char]
-!15 = !{!"0x24\00char\000\008\008\000\000\006", !20, !4} ; [ DW_TAG_base_type ]
-!16 = !{!17}
-!17 = !{!"0x21\000\001"}        ; [ DW_TAG_subrange_type ]
-!18 = !{!"llvm.mdnode.fwdref.19"}
-!19 = !{!"llvm.mdnode.fwdref.23"}
-!20 = !{!"2007-12-VarArrayDebug.c", !"/Users/sabre/llvm/test/FrontendC/"}
-!21 = !{i32 0}
-!22 = !{i32 1, !"Debug Info Version", i32 2}
diff --git a/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll b/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll
index ce52d24aa7f6..45ed4962f7b4 100644
--- a/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll
+++ b/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll
@@ -13,7 +13,7 @@
 ; CHECK-NOT: DW_TAG
 ; CHECK: DW_AT_low_pc
 ; CHECK-NOT: DW_TAG
-; CHECK: DW_AT_MIPS_linkage_name {{.*}} "_ZZN1B2fnEvEN1A3fooEv"
+; CHECK: DW_AT_linkage_name {{.*}} "_ZZN1B2fnEvEN1A3fooEv"
 ; And just double check that there's no out of line definition that references
 ; this subprogram.
 ; CHECK-NOT: DW_AT_specification {{.*}} {[[FOO_INL]]}
@@ -26,10 +26,10 @@ entry:
   %retval = alloca i32, align 4                   ; <i32*> [#uses=3]
   %b = alloca %class.A, align 1                   ; <%class.A*> [#uses=1]
   store i32 0, i32* %retval
-  call void @llvm.dbg.declare(metadata %class.A* %b, metadata !0, metadata !{!"0x102"}), !dbg !14
+  call void @llvm.dbg.declare(metadata %class.A* %b, metadata !0, metadata !DIExpression()), !dbg !14
   %call = call i32 @_ZN1B2fnEv(%class.A* %b), !dbg !15 ; <i32> [#uses=1]
   store i32 %call, i32* %retval, !dbg !15
-  %0 = load i32* %retval, !dbg !16                ; <i32> [#uses=1]
+  %0 = load i32, i32* %retval, !dbg !16                ; <i32> [#uses=1]
   ret i32 %0, !dbg !16
 }
 
@@ -42,15 +42,15 @@ entry:
   %a = alloca %class.A, align 1                   ; <%class.A*> [#uses=1]
   %i = alloca i32, align 4                        ; <i32*> [#uses=2]
   store %class.A* %this, %class.A** %this.addr
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !17, metadata !{!"0x102"}), !dbg !18
-  %this1 = load %class.A** %this.addr             ; <%class.A*> [#uses=0]
-  call void @llvm.dbg.declare(metadata %class.A* %a, metadata !19, metadata !{!"0x102"}), !dbg !27
-  call void @llvm.dbg.declare(metadata i32* %i, metadata !28, metadata !{!"0x102"}), !dbg !29
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !17, metadata !DIExpression()), !dbg !18
+  %this1 = load %class.A*, %class.A** %this.addr             ; <%class.A*> [#uses=0]
+  call void @llvm.dbg.declare(metadata %class.A* %a, metadata !19, metadata !DIExpression()), !dbg !27
+  call void @llvm.dbg.declare(metadata i32* %i, metadata !28, metadata !DIExpression()), !dbg !29
   %call = call i32 @_ZZN1B2fnEvEN1A3fooEv(%class.A* %a), !dbg !30 ; <i32> [#uses=1]
   store i32 %call, i32* %i, !dbg !30
-  %tmp = load i32* %i, !dbg !31                   ; <i32> [#uses=1]
+  %tmp = load i32, i32* %i, !dbg !31                   ; <i32> [#uses=1]
   store i32 %tmp, i32* %retval, !dbg !31
-  %0 = load i32* %retval, !dbg !32                ; <i32> [#uses=1]
+  %0 = load i32, i32* %retval, !dbg !32                ; <i32> [#uses=1]
   ret i32 %0, !dbg !32
 }
 
@@ -59,10 +59,10 @@ entry:
   %retval = alloca i32, align 4                   ; <i32*> [#uses=2]
   %this.addr = alloca %class.A*, align 8          ; <%class.A**> [#uses=2]
   store %class.A* %this, %class.A** %this.addr
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !33, metadata !{!"0x102"}), !dbg !34
-  %this1 = load %class.A** %this.addr             ; <%class.A*> [#uses=0]
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !33, metadata !DIExpression()), !dbg !34
+  %this1 = load %class.A*, %class.A** %this.addr             ; <%class.A*> [#uses=0]
   store i32 42, i32* %retval, !dbg !35
-  %0 = load i32* %retval, !dbg !35                ; <i32> [#uses=1]
+  %0 = load i32, i32* %retval, !dbg !35                ; <i32> [#uses=1]
   ret i32 %0, !dbg !35
 }
 
@@ -70,43 +70,43 @@ entry:
 !llvm.module.flags = !{!40}
 !37 = !{!2, !10, !23}
 
-!0 = !{!"0x100\00b\0016\000", !1, !3, !8} ; [ DW_TAG_auto_variable ]
-!1 = !{!"0xb\0015\0012\000", !38, !2} ; [ DW_TAG_lexical_block ]
-!2 = !{!"0x2e\00main\00main\00main\0015\000\001\000\006\000\000\0015", !38, !3, !5, null, i32 ()* @main, null, null, null} ; [ DW_TAG_subprogram ]
-!3 = !{!"0x29", !38} ; [ DW_TAG_file_type ]
-!4 = !{!"0x11\004\00clang 1.5\000\00\000\00\000", !38, !39, !39, !37, null,  null} ; [ DW_TAG_compile_unit ]
-!5 = !{!"0x15\00\000\000\000\000\000\000", !38, !3, null, !6, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 16, scope: !1, file: !3, type: !8)
+!1 = distinct !DILexicalBlock(line: 15, column: 12, file: !38, scope: !2)
+!2 = !DISubprogram(name: "main", linkageName: "main", line: 15, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 15, file: !38, scope: !3, type: !5, function: i32 ()* @main)
+!3 = !DIFile(filename: "one.cc", directory: "/tmp")
+!4 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang 1.5", isOptimized: false, emissionKind: 0, file: !38, enums: !39, retainedTypes: !39, subprograms: !37, imports:  null)
+!5 = !DISubroutineType(types: !6)
 !6 = !{!7}
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", !38, !3} ; [ DW_TAG_base_type ]
-!8 = !{!"0x2\00B\002\008\008\000\000\000", !38, !3, null, !9, null, null, null} ; [ DW_TAG_class_type ] [B] [line 2, size 8, align 8, offset 0] [def] [from ]
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DICompositeType(tag: DW_TAG_class_type, name: "B", line: 2, size: 8, align: 8, file: !38, scope: !3, elements: !9)
 !9 = !{!10}
-!10 = !{!"0x2e\00fn\00fn\00_ZN1B2fnEv\004\000\001\000\006\000\000\004", !38, !8, !11, null, i32 (%class.A*)* @_ZN1B2fnEv, null, null, null} ; [ DW_TAG_subprogram ]
-!11 = !{!"0x15\00\000\000\000\000\000\000", !38, !3, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!10 = !DISubprogram(name: "fn", linkageName: "_ZN1B2fnEv", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 4, file: !38, scope: !8, type: !11, function: i32 (%class.A*)* @_ZN1B2fnEv)
+!11 = !DISubroutineType(types: !12)
 !12 = !{!7, !13}
-!13 = !{!"0xf\00\000\0064\0064\000\0064", !38, !3, !8} ; [ DW_TAG_pointer_type ]
-!14 = !MDLocation(line: 16, column: 5, scope: !1)
-!15 = !MDLocation(line: 17, column: 3, scope: !1)
-!16 = !MDLocation(line: 18, column: 1, scope: !2)
-!17 = !{!"0x101\00this\004\000", !10, !3, !13} ; [ DW_TAG_arg_variable ]
-!18 = !MDLocation(line: 4, column: 7, scope: !10)
-!19 = !{!"0x100\00a\009\000", !20, !3, !21} ; [ DW_TAG_auto_variable ]
-!20 = !{!"0xb\004\0012\000", !38, !10} ; [ DW_TAG_lexical_block ]
-!21 = !{!"0x2\00A\005\008\008\000\000\000", !38, !10, null, !22, null, null, null} ; [ DW_TAG_class_type ] [A] [line 5, size 8, align 8, offset 0] [def] [from ]
+!13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, file: !38, scope: !3, baseType: !8)
+!14 = !DILocation(line: 16, column: 5, scope: !1)
+!15 = !DILocation(line: 17, column: 3, scope: !1)
+!16 = !DILocation(line: 18, column: 1, scope: !2)
+!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 4, arg: 0, scope: !10, file: !3, type: !13)
+!18 = !DILocation(line: 4, column: 7, scope: !10)
+!19 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 9, scope: !20, file: !3, type: !21)
+!20 = distinct !DILexicalBlock(line: 4, column: 12, file: !38, scope: !10)
+!21 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 5, size: 8, align: 8, file: !38, scope: !10, elements: !22)
 !22 = !{!23}
-!23 = !{!"0x2e\00foo\00foo\00_ZZN1B2fnEvEN1A3fooEv\007\000\001\000\006\000\000\007", !38, !21, !24, null, i32 (%class.A*)* @_ZZN1B2fnEvEN1A3fooEv, null, null, null} ; [ DW_TAG_subprogram ]
-!24 = !{!"0x15\00\000\000\000\000\000\000", !38, !3, null, !25, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!23 = !DISubprogram(name: "foo", linkageName: "_ZZN1B2fnEvEN1A3fooEv", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 7, file: !38, scope: !21, type: !24, function: i32 (%class.A*)* @_ZZN1B2fnEvEN1A3fooEv)
+!24 = !DISubroutineType(types: !25)
 !25 = !{!7, !26}
-!26 = !{!"0xf\00\000\0064\0064\000\0064", !38, !3, !21} ; [ DW_TAG_pointer_type ]
-!27 = !MDLocation(line: 9, column: 7, scope: !20)
-!28 = !{!"0x100\00i\0010\000", !20, !3, !7} ; [ DW_TAG_auto_variable ]
-!29 = !MDLocation(line: 10, column: 9, scope: !20)
-!30 = !MDLocation(line: 10, column: 5, scope: !20)
-!31 = !MDLocation(line: 11, column: 5, scope: !20)
-!32 = !MDLocation(line: 12, column: 3, scope: !10)
-!33 = !{!"0x101\00this\007\000", !23, !3, !26} ; [ DW_TAG_arg_variable ]
-!34 = !MDLocation(line: 7, column: 11, scope: !23)
-!35 = !MDLocation(line: 7, column: 19, scope: !36)
-!36 = !{!"0xb\007\0017\000", !38, !23} ; [ DW_TAG_lexical_block ]
-!38 = !{!"one.cc", !"/tmp" }
-!39 = !{i32 0}
-!40 = !{i32 1, !"Debug Info Version", i32 2}
+!26 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, file: !38, scope: !3, baseType: !21)
+!27 = !DILocation(line: 9, column: 7, scope: !20)
+!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 10, scope: !20, file: !3, type: !7)
+!29 = !DILocation(line: 10, column: 9, scope: !20)
+!30 = !DILocation(line: 10, column: 5, scope: !20)
+!31 = !DILocation(line: 11, column: 5, scope: !20)
+!32 = !DILocation(line: 12, column: 3, scope: !10)
+!33 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 7, arg: 0, scope: !23, file: !3, type: !26)
+!34 = !DILocation(line: 7, column: 11, scope: !23)
+!35 = !DILocation(line: 7, column: 19, scope: !36)
+!36 = distinct !DILexicalBlock(line: 7, column: 17, file: !38, scope: !23)
+!38 = !DIFile(filename: "one.cc", directory: "/tmp")
+!39 = !{}
+!40 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/2010-04-19-FramePtr.ll b/test/DebugInfo/2010-04-19-FramePtr.ll
index fe5a1f448551..ed6a4fdb54e1 100644
--- a/test/DebugInfo/2010-04-19-FramePtr.ll
+++ b/test/DebugInfo/2010-04-19-FramePtr.ll
@@ -10,12 +10,12 @@ entry:
   %0 = alloca i32                                 ; <i32*> [#uses=2]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   store i32 42, i32* %0, align 4, !dbg !0
-  %1 = load i32* %0, align 4, !dbg !0             ; <i32> [#uses=1]
+  %1 = load i32, i32* %0, align 4, !dbg !0             ; <i32> [#uses=1]
   store i32 %1, i32* %retval, align 4, !dbg !0
   br label %return, !dbg !0
 
 return:                                           ; preds = %entry
-  %retval1 = load i32* %retval, !dbg !0           ; <i32> [#uses=1]
+  %retval1 = load i32, i32* %retval, !dbg !0           ; <i32> [#uses=1]
   ret i32 %retval1, !dbg !7
 }
 
@@ -23,15 +23,15 @@ return:                                           ; preds = %entry
 !llvm.module.flags = !{!12}
 !9 = !{!1}
 
-!0 = !MDLocation(line: 2, scope: !1)
-!1 = !{!"0x2e\00foo\00foo\00foo\002\000\001\000\006\000\000\002", !10, null, !4, null, i32 ()* @foo, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !10} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\000\00\000\00\000", !10, !11, !11, !9, null,  null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !10, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocation(line: 2, scope: !1)
+!1 = !DISubprogram(name: "foo", linkageName: "foo", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 2, file: !10, scope: null, type: !4, function: i32 ()* @foo)
+!2 = !DIFile(filename: "a.c", directory: "/tmp")
+!3 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: false, emissionKind: 0, file: !10, enums: !11, retainedTypes: !11, subprograms: !9, imports:  null)
+!4 = !DISubroutineType(types: !5)
 !5 = !{!6}
-!6 = !{!"0x24\00int\000\0032\0032\000\000\005", !10, !2} ; [ DW_TAG_base_type ]
-!7 = !MDLocation(line: 2, scope: !8)
-!8 = !{!"0xb\002\000\000", !10, !1} ; [ DW_TAG_lexical_block ]
-!10 = !{!"a.c", !"/tmp"}
-!11 = !{i32 0}
-!12 = !{i32 1, !"Debug Info Version", i32 2}
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!7 = !DILocation(line: 2, scope: !8)
+!8 = distinct !DILexicalBlock(line: 2, column: 0, file: !10, scope: !1)
+!10 = !DIFile(filename: "a.c", directory: "/tmp")
+!11 = !{}
+!12 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/2010-05-03-DisableFramePtr.ll b/test/DebugInfo/2010-05-03-DisableFramePtr.ll
index d767871a2764..660e9dba498b 100644
--- a/test/DebugInfo/2010-05-03-DisableFramePtr.ll
+++ b/test/DebugInfo/2010-05-03-DisableFramePtr.ll
@@ -6,7 +6,7 @@ define void @DisposeDMNotificationUPP(void (%struct.AppleEvent*)* %userUPP) "no-
 entry:
   %userUPP_addr = alloca void (%struct.AppleEvent*)* ; <void (%struct.AppleEvent*)**> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.declare(metadata void (%struct.AppleEvent*)** %userUPP_addr, metadata !0, metadata !{!"0x102"}), !dbg !13
+  call void @llvm.dbg.declare(metadata void (%struct.AppleEvent*)** %userUPP_addr, metadata !0, metadata !DIExpression()), !dbg !13
   store void (%struct.AppleEvent*)* %userUPP, void (%struct.AppleEvent*)** %userUPP_addr
   br label %return, !dbg !14
 
@@ -18,23 +18,23 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!3}
 !llvm.module.flags = !{!19}
-!0 = !{!"0x101\00userUPP\007\000", !1, !2, !6} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00DisposeDMNotificationUPP\00DisposeDMNotificationUPP\00DisposeDMNotificationUPP\007\000\001\000\006\000\000\000", !16, null, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !16} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)\001\00\000\00\000", !16, !17, !17, !18, null, null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !16, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "userUPP", line: 7, arg: 0, scope: !1, file: !2, type: !6)
+!1 = !DISubprogram(name: "DisposeDMNotificationUPP", linkageName: "DisposeDMNotificationUPP", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !16, scope: null, type: !4)
+!2 = !DIFile(filename: "t.c", directory: "/Users/echeng/LLVM/radars/r7937664/")
+!3 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)", isOptimized: true, emissionKind: 0, file: !16, enums: !17, retainedTypes: !17, subprograms: !18)
+!4 = !DISubroutineType(types: !5)
 !5 = !{null, !6}
-!6 = !{!"0x16\00DMNotificationUPP\006\000\000\000\000", !16, !2, !7} ; [ DW_TAG_typedef ]
-!7 = !{!"0xf\00\000\0064\0064\000\000", !16, !2, !8} ; [ DW_TAG_pointer_type ]
-!8 = !{!"0x15\00\000\000\000\000\000\000", !16, !2, null, !9, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DIDerivedType(tag: DW_TAG_typedef, name: "DMNotificationUPP", line: 6, file: !16, scope: !2, baseType: !7)
+!7 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !16, scope: !2, baseType: !8)
+!8 = !DISubroutineType(types: !9)
 !9 = !{null, !10}
-!10 = !{!"0xf\00\000\0064\0064\000\000", !16, !2, !11} ; [ DW_TAG_pointer_type ]
-!11 = !{!"0x16\00AppleEvent\004\000\000\000\000", !16, !2, !12} ; [ DW_TAG_typedef ]
-!12 = !{!"0x13\00AEDesc\001\000\000\000\004\000", !16, !2, null, null, null, null, null} ; [ DW_TAG_structure_type ] [AEDesc] [line 1, size 0, align 0, offset 0] [decl] [from ]
-!13 = !MDLocation(line: 7, scope: !1)
-!14 = !MDLocation(line: 8, scope: !15)
-!15 = !{!"0xb\007\000\000", !16, !1} ; [ DW_TAG_lexical_block ]
-!16 = !{!"t.c", !"/Users/echeng/LLVM/radars/r7937664/"}
-!17 = !{i32 0}
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !16, scope: !2, baseType: !11)
+!11 = !DIDerivedType(tag: DW_TAG_typedef, name: "AppleEvent", line: 4, file: !16, scope: !2, baseType: !12)
+!12 = !DICompositeType(tag: DW_TAG_structure_type, name: "AEDesc", line: 1, flags: DIFlagFwdDecl, file: !16, scope: !2)
+!13 = !DILocation(line: 7, scope: !1)
+!14 = !DILocation(line: 8, scope: !15)
+!15 = distinct !DILexicalBlock(line: 7, column: 0, file: !16, scope: !1)
+!16 = !DIFile(filename: "t.c", directory: "/Users/echeng/LLVM/radars/r7937664/")
+!17 = !{}
 !18 = !{!1}
-!19 = !{i32 1, !"Debug Info Version", i32 2}
+!19 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/2010-05-03-OriginDIE.ll b/test/DebugInfo/2010-05-03-OriginDIE.ll
index 1caae64967bd..da1e57caba14 100644
--- a/test/DebugInfo/2010-05-03-OriginDIE.ll
+++ b/test/DebugInfo/2010-05-03-OriginDIE.ll
@@ -16,24 +16,24 @@ entry:
   %data_addr.i16 = alloca i64, align 8            ; <i64*> [#uses=0]
   %data_addr.i15 = alloca i32, align 4            ; <i32*> [#uses=0]
   %data_addr.i = alloca i64, align 8              ; <i64*> [#uses=0]
-  %0 = getelementptr inbounds %struct.gpm_t* %gpm, i32 0, i32 2, i32 0 ; <i8*> [#uses=1]
-  %1 = getelementptr inbounds %struct.gpt_t* %gpt, i32 0, i32 9, i32 0 ; <i8*> [#uses=1]
+  %0 = getelementptr inbounds %struct.gpm_t, %struct.gpm_t* %gpm, i32 0, i32 2, i32 0 ; <i8*> [#uses=1]
+  %1 = getelementptr inbounds %struct.gpt_t, %struct.gpt_t* %gpt, i32 0, i32 9, i32 0 ; <i8*> [#uses=1]
   call void @uuid_LtoB(i8* %0, i8* %1) nounwind, !dbg !0
-  %a9 = load volatile i64* %data_addr.i18, align 8 ; <i64> [#uses=1]
+  %a9 = load volatile i64, i64* %data_addr.i18, align 8 ; <i64> [#uses=1]
   %a10 = call i64 @llvm.bswap.i64(i64 %a9) nounwind ; <i64> [#uses=1]
-  %a11 = getelementptr inbounds %struct.gpt_t* %gpt, i32 0, i32 8, !dbg !7 ; <i64*> [#uses=1]
-  %a12 = load i64* %a11, align 4, !dbg !7         ; <i64> [#uses=1]
-  call void @llvm.dbg.declare(metadata i64* %data_addr.i17, metadata !8, metadata !{!"0x102"}) nounwind, !dbg !14
+  %a11 = getelementptr inbounds %struct.gpt_t, %struct.gpt_t* %gpt, i32 0, i32 8, !dbg !7 ; <i64*> [#uses=1]
+  %a12 = load i64, i64* %a11, align 4, !dbg !7         ; <i64> [#uses=1]
+  call void @llvm.dbg.declare(metadata i64* %data_addr.i17, metadata !8, metadata !DIExpression()) nounwind, !dbg !14
   store i64 %a12, i64* %data_addr.i17, align 8
-  call void @llvm.dbg.value(metadata !6, i64 0, metadata !15, metadata !{!"0x102"}) nounwind
-  call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !19, metadata !{!"0x102"}) nounwind
-  call void @llvm.dbg.declare(metadata !6, metadata !23, metadata !{!"0x102"}) nounwind
-  call void @llvm.dbg.value(metadata i64* %data_addr.i17, i64 0, metadata !34, metadata !{!"0x102"}) nounwind
-  %a13 = load volatile i64* %data_addr.i17, align 8 ; <i64> [#uses=1]
+  call void @llvm.dbg.value(metadata !6, i64 0, metadata !15, metadata !DIExpression()) nounwind, !dbg !DILocation(scope: !16)
+  call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !19, metadata !DIExpression()) nounwind, !dbg !DILocation(scope: !16)
+  call void @llvm.dbg.declare(metadata !6, metadata !23, metadata !DIExpression()) nounwind, !dbg !DILocation(scope: !24)
+  call void @llvm.dbg.value(metadata i64* %data_addr.i17, i64 0, metadata !34, metadata !DIExpression()) nounwind, !dbg !DILocation(scope: !24)
+  %a13 = load volatile i64, i64* %data_addr.i17, align 8 ; <i64> [#uses=1]
   %a14 = call i64 @llvm.bswap.i64(i64 %a13) nounwind ; <i64> [#uses=2]
   %a15 = add i64 %a10, %a14, !dbg !7              ; <i64> [#uses=1]
   %a16 = sub i64 %a15, %a14                       ; <i64> [#uses=1]
-  %a17 = getelementptr inbounds %struct.gpm_t* %gpm, i32 0, i32 5, !dbg !7 ; <i64*> [#uses=1]
+  %a17 = getelementptr inbounds %struct.gpm_t, %struct.gpm_t* %gpm, i32 0, i32 5, !dbg !7 ; <i64*> [#uses=1]
   store i64 %a16, i64* %a17, align 4, !dbg !7
   ret void, !dbg !7
 }
@@ -50,45 +50,45 @@ declare void @uuid_LtoB(i8*, i8*)
 
 !llvm.dbg.cu = !{!4}
 !llvm.module.flags = !{!41}
-!0 = !MDLocation(line: 808, scope: !1)
-!1 = !{!"0xb\00807\000\000", !39, !2} ; [ DW_TAG_lexical_block ]
-!2 = !{!"0x2e\00gpt2gpm\00gpt2gpm\00gpt2gpm\00807\001\001\000\006\000\000\000", !39, null, !5, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!3 = !{!"0x29", !39} ; [ DW_TAG_file_type ]
-!4 = !{!"0x11\001\00llvm-gcc\001\00\000\00\000", !39, !18, !18, !40, null, null} ; [ DW_TAG_compile_unit ]
-!5 = !{!"0x15\00\000\000\000\000\000\000", !39, !3, null, !6, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocation(line: 808, scope: !1)
+!1 = distinct !DILexicalBlock(line: 807, column: 0, file: !39, scope: !2)
+!2 = !DISubprogram(name: "gpt2gpm", linkageName: "gpt2gpm", line: 807, isLocal: true, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !39, scope: null, type: !5)
+!3 = !DIFile(filename: "G.c", directory: "/tmp")
+!4 = !DICompileUnit(language: DW_LANG_C89, producer: "llvm-gcc", isOptimized: true, emissionKind: 0, file: !39, enums: !18, retainedTypes: !18, subprograms: !40)
+!5 = !DISubroutineType(types: !6)
 !6 = !{null}
-!7 = !MDLocation(line: 810, scope: !1)
-!8 = !{!"0x101\00data\00201\000", !9, !10, !11} ; [ DW_TAG_arg_variable ]
-!9 = !{!"0x2e\00_OSSwapInt64\00_OSSwapInt64\00_OSSwapInt64\00202\001\001\000\006\000\000\000", !10, null, !5, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!10 = !{!"0x29", !"OSByteOrder.h", !"/usr/include/libkern/ppc", !4} ; [ DW_TAG_file_type ]
-!11 = !{!"0x16\00uint64_t\0059\000\000\000\000", !36, !3, !13} ; [ DW_TAG_typedef ]
-!12 = !{!"0x29", !"stdint.h", !"/usr/4.2.1/include", !4} ; [ DW_TAG_file_type ]
-!13 = !{!"0x24\00long long unsigned int\000\0064\0064\000\000\007", !39, !3} ; [ DW_TAG_base_type ]
-!14 = !MDLocation(line: 202, scope: !9, inlinedAt: !7)
-!15 = !{!"0x101\00base\0092\000", !16, !10, !17} ; [ DW_TAG_arg_variable ]
-!16 = !{!"0x2e\00OSReadSwapInt64\00OSReadSwapInt64\00OSReadSwapInt64\0095\001\001\000\006\000\000\000", !38, null, !5, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!17 = !{!"0xf\00\000\0032\0032\000\000", !39, !3, null} ; [ DW_TAG_pointer_type ]
-!18 = !{i32 0}
-!19 = !{!"0x101\00byteOffset\0094\000", !16, !10, !20} ; [ DW_TAG_arg_variable ]
-!20 = !{!"0x16\00uintptr_t\00114\000\000\000\000", !37, !3, !22} ; [ DW_TAG_typedef ]
-!21 = !{!"0x29", !"types.h", !"/usr/include/ppc", !4} ; [ DW_TAG_file_type ]
-!22 = !{!"0x24\00long unsigned int\000\0032\0032\000\000\007", !39, !3} ; [ DW_TAG_base_type ]
-!23 = !{!"0x100\00u\00100\000", !24, !10, !25} ; [ DW_TAG_auto_variable ]
-!24 = !{!"0xb\0095\000\000", !38, !16} ; [ DW_TAG_lexical_block ]
-!25 = !{!"0x17\00\0097\0064\0064\000\000\000", !38, !16, null, !26, null, null, null} ; [ DW_TAG_union_type ] [line 97, size 64, align 64, offset 0] [def] [from ]
+!7 = !DILocation(line: 810, scope: !1)
+!8 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "data", line: 201, arg: 0, scope: !9, file: !10, type: !11)
+!9 = !DISubprogram(name: "_OSSwapInt64", linkageName: "_OSSwapInt64", line: 202, isLocal: true, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !10, scope: null, type: !5)
+!10 = !DIFile(filename: "OSByteOrder.h", directory: "/usr/include/libkern/ppc")
+!11 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint64_t", line: 59, file: !36, scope: !3, baseType: !13)
+!12 = !DIFile(filename: "stdint.h", directory: "/usr/4.2.1/include")
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "long long unsigned int", size: 64, align: 64, encoding: DW_ATE_unsigned)
+!14 = !DILocation(line: 202, scope: !9, inlinedAt: !7)
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "base", line: 92, arg: 0, scope: !16, file: !10, type: !17)
+!16 = !DISubprogram(name: "OSReadSwapInt64", linkageName: "OSReadSwapInt64", line: 95, isLocal: true, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !38, scope: null, type: !5)
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !39, scope: !3, baseType: null)
+!18 = !{}
+!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "byteOffset", line: 94, arg: 0, scope: !16, file: !10, type: !20)
+!20 = !DIDerivedType(tag: DW_TAG_typedef, name: "uintptr_t", line: 114, file: !37, scope: !3, baseType: !22)
+!21 = !DIFile(filename: "types.h", directory: "/usr/include/ppc")
+!22 = !DIBasicType(tag: DW_TAG_base_type, name: "long unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!23 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "u", line: 100, scope: !24, file: !10, type: !25)
+!24 = distinct !DILexicalBlock(line: 95, column: 0, file: !38, scope: !16)
+!25 = !DICompositeType(tag: DW_TAG_union_type, line: 97, size: 64, align: 64, file: !38, scope: !16, elements: !26)
 !26 = !{!27, !28}
-!27 = !{!"0xd\00u64\0098\0064\0064\000\000", !38, !25, !11} ; [ DW_TAG_member ]
-!28 = !{!"0xd\00u32\0099\0064\0032\000\000", !38, !25, !29} ; [ DW_TAG_member ]
-!29 = !{!"0x1\00\000\0064\0032\000\000", !39, !3, !30, !32, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 64, align 32, offset 0] [from uint32_t]
-!30 = !{!"0x16\00uint32_t\0055\000\000\000\000", !36, !3, !31} ; [ DW_TAG_typedef ]
-!31 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", !39, !3} ; [ DW_TAG_base_type ]
+!27 = !DIDerivedType(tag: DW_TAG_member, name: "u64", line: 98, size: 64, align: 64, file: !38, scope: !25, baseType: !11)
+!28 = !DIDerivedType(tag: DW_TAG_member, name: "u32", line: 99, size: 64, align: 32, file: !38, scope: !25, baseType: !29)
+!29 = !DICompositeType(tag: DW_TAG_array_type, size: 64, align: 32, file: !39, scope: !3, baseType: !30, elements: !32)
+!30 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint32_t", line: 55, file: !36, scope: !3, baseType: !31)
+!31 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
 !32 = !{!33}
-!33 = !{!"0x21\000\002"}        ; [ DW_TAG_subrange_type ]
-!34 = !{!"0x100\00addr\0096\000", !24, !10, !35} ; [ DW_TAG_auto_variable ]
-!35 = !{!"0xf\00\000\0032\0032\000\000", !39, !3, !11} ; [ DW_TAG_pointer_type ]
-!36 = !{!"stdint.h", !"/usr/4.2.1/include"}
-!37 = !{!"types.h", !"/usr/include/ppc"}
-!38 = !{!"OSByteOrder.h", !"/usr/include/libkern/ppc"}
-!39 = !{!"G.c", !"/tmp"}
+!33 = !DISubrange(count: 2)
+!34 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "addr", line: 96, scope: !24, file: !10, type: !35)
+!35 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !39, scope: !3, baseType: !11)
+!36 = !DIFile(filename: "stdint.h", directory: "/usr/4.2.1/include")
+!37 = !DIFile(filename: "types.h", directory: "/usr/include/ppc")
+!38 = !DIFile(filename: "OSByteOrder.h", directory: "/usr/include/libkern/ppc")
+!39 = !DIFile(filename: "G.c", directory: "/tmp")
 !40 = !{!2, !9, !16}
-!41 = !{i32 1, !"Debug Info Version", i32 2}
+!41 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/2010-05-10-MultipleCU.ll b/test/DebugInfo/2010-05-10-MultipleCU.ll
index 502007c80934..6513165ac248 100644
--- a/test/DebugInfo/2010-05-10-MultipleCU.ll
+++ b/test/DebugInfo/2010-05-10-MultipleCU.ll
@@ -22,23 +22,23 @@ return:
 !16 = !{!2}
 !17 = !{!10}
 
-!0 = !MDLocation(line: 3, scope: !1)
-!1 = !{!"0xb\002\000\000", !18, !2} ; [ DW_TAG_lexical_block ]
-!2 = !{!"0x2e\00foo\00foo\00foo\002\000\001\000\006\000\000\000", !18, !3, !5, null, i32 ()* @foo, null, null, null} ; [ DW_TAG_subprogram ]
-!3 = !{!"0x29", !18} ; [ DW_TAG_file_type ]
-!4 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\000\00\000\00\000", !18, !19, !19, !16, null, null} ; [ DW_TAG_compile_unit ]
-!5 = !{!"0x15\00\000\000\000\000\000\000", !18, !3, null, !6, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocation(line: 3, scope: !1)
+!1 = distinct !DILexicalBlock(line: 2, column: 0, file: !18, scope: !2)
+!2 = !DISubprogram(name: "foo", linkageName: "foo", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !18, scope: !3, type: !5, function: i32 ()* @foo)
+!3 = !DIFile(filename: "a.c", directory: "/tmp/")
+!4 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: false, emissionKind: 0, file: !18, enums: !19, retainedTypes: !19, subprograms: !16)
+!5 = !DISubroutineType(types: !6)
 !6 = !{!7}
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", !18, !3} ; [ DW_TAG_base_type ]
-!8 = !MDLocation(line: 3, scope: !9)
-!9 = !{!"0xb\002\000\000", !20, !10} ; [ DW_TAG_lexical_block ]
-!10 = !{!"0x2e\00bar\00bar\00bar\002\000\001\000\006\000\000\000", !20, !11, !13, null, i32 ()* @bar, null, null, null} ; [ DW_TAG_subprogram ]
-!11 = !{!"0x29", !20} ; [ DW_TAG_file_type ]
-!12 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\000\00\000\00\000", !20, !19, !19, !17, null, null} ; [ DW_TAG_compile_unit ]
-!13 = !{!"0x15\00\000\000\000\000\000\000", !20, !11, null, !14, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DILocation(line: 3, scope: !9)
+!9 = distinct !DILexicalBlock(line: 2, column: 0, file: !20, scope: !10)
+!10 = !DISubprogram(name: "bar", linkageName: "bar", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !20, scope: !11, type: !13, function: i32 ()* @bar)
+!11 = !DIFile(filename: "b.c", directory: "/tmp/")
+!12 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: false, emissionKind: 0, file: !20, enums: !19, retainedTypes: !19, subprograms: !17)
+!13 = !DISubroutineType(types: !14)
 !14 = !{!15}
-!15 = !{!"0x24\00int\000\0032\0032\000\000\005", !20, !11} ; [ DW_TAG_base_type ]
-!18 = !{!"a.c", !"/tmp/"}
-!19 = !{i32 0}
-!20 = !{!"b.c", !"/tmp/"}
-!21 = !{i32 1, !"Debug Info Version", i32 2}
+!15 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!18 = !DIFile(filename: "a.c", directory: "/tmp/")
+!19 = !{}
+!20 = !DIFile(filename: "b.c", directory: "/tmp/")
+!21 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll b/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll
index 9f0f7c37fcc0..27a0535bc8c3 100644
--- a/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll
+++ b/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll
@@ -1,9 +1,10 @@
 ; RUN: %llc_dwarf -O2 %s -o - | FileCheck %s
 ; Check struct X for dead variable xyz from inlined function foo.
 
+; CHECK: section_info
 ; CHECK:	DW_TAG_structure_type
-; CHECK-NEXT:	info_string
- 
+; CHECK-NEXT:	DW_AT_name
+
 
 @i = common global i32 0                          ; <i32*> [#uses=2]
 
@@ -13,9 +14,9 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 
 define i32 @bar() nounwind ssp {
 entry:
-  %0 = load i32* @i, align 4, !dbg !17            ; <i32> [#uses=2]
-  tail call void @llvm.dbg.value(metadata i32 %0, i64 0, metadata !9, metadata !{!"0x102"}), !dbg !19
-  tail call void @llvm.dbg.declare(metadata !29, metadata !10, metadata !{!"0x102"}), !dbg !21
+  %0 = load i32, i32* @i, align 4, !dbg !17            ; <i32> [#uses=2]
+  tail call void @llvm.dbg.value(metadata i32 %0, i64 0, metadata !59, metadata !DIExpression()), !dbg !19
+  tail call void @llvm.dbg.declare(metadata !29, metadata !60, metadata !DIExpression()), !dbg !21
   %1 = mul nsw i32 %0, %0, !dbg !22               ; <i32> [#uses=2]
   store i32 %1, i32* @i, align 4, !dbg !17
   ret i32 %1, !dbg !23
@@ -24,33 +25,37 @@ entry:
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!28}
 
-!0 = !{!"0x2e\00foo\00foo\00\009\001\001\000\006\000\001\009", !27, !1, !3, null, null, null, null, !24} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !27} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\001\00\000\00\000", !27, !20, !20, !25, !26,  !20} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !27, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "foo", line: 9, isLocal: true, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 9, file: !27, scope: !1, type: !3, variables: !24)
+!1 = !DIFile(filename: "bar.c", directory: "/tmp/")
+!2 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 0, file: !27, enums: !20, retainedTypes: !20, subprograms: !25, globals: !26, imports:  !20)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5, !5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", !27, !1} ; [ DW_TAG_base_type ]
-!6 = !{!"0x2e\00bar\00bar\00bar\0014\000\001\000\006\000\001\000", !27, !1, !7, null, i32 ()* @bar, null, null, null} ; [ DW_TAG_subprogram ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", !27, !1, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DISubprogram(name: "bar", linkageName: "bar", line: 14, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, file: !27, scope: !1, type: !7, function: i32 ()* @bar)
+!7 = !DISubroutineType(types: !8)
 !8 = !{!5}
-!9 = !{!"0x101\00j\009\000", !0, !1, !5} ; [ DW_TAG_arg_variable ]
-!10 = !{!"0x100\00xyz\0010\000", !11, !1, !12} ; [ DW_TAG_auto_variable ]
-!11 = !{!"0xb\009\000\000", !1, !0} ; [ DW_TAG_lexical_block ]
-!12 = !{!"0x13\00X\0010\0064\0032\000\000\000", !27, !0, null, !13, null, null, null} ; [ DW_TAG_structure_type ] [X] [line 10, size 64, align 32, offset 0] [def] [from ]
+!9 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "j", line: 9, arg: 0, scope: !0, file: !1, type: !5)
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xyz", line: 10, scope: !11, file: !1, type: !12)
+
+!59 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "j", line: 9, arg: 0, scope: !0, file: !1, type: !5)
+!60 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xyz", line: 10, scope: !11, file: !1, type: !12)
+
+!11 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !0)
+!12 = !DICompositeType(tag: DW_TAG_structure_type, name: "X", line: 10, size: 64, align: 32, file: !27, scope: !0, elements: !13)
 !13 = !{!14, !15}
-!14 = !{!"0xd\00a\0010\0032\0032\000\000", !27, !12, !5} ; [ DW_TAG_member ]
-!15 = !{!"0xd\00b\0010\0032\0032\0032\000", !27, !12, !5} ; [ DW_TAG_member ]
-!16 = !{!"0x34\00i\00i\00\005\000\001", !1, !1, !5, i32* @i, null} ; [ DW_TAG_variable ]
-!17 = !MDLocation(line: 15, scope: !18)
-!18 = !{!"0xb\0014\000\001", !1, !6} ; [ DW_TAG_lexical_block ]
-!19 = !MDLocation(line: 9, scope: !0, inlinedAt: !17)
+!14 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 10, size: 32, align: 32, file: !27, scope: !12, baseType: !5)
+!15 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 10, size: 32, align: 32, offset: 32, file: !27, scope: !12, baseType: !5)
+!16 = !DIGlobalVariable(name: "i", line: 5, isLocal: false, isDefinition: true, scope: !1, file: !1, type: !5, variable: i32* @i)
+!17 = !DILocation(line: 15, scope: !18)
+!18 = distinct !DILexicalBlock(line: 14, column: 0, file: !1, scope: !6)
+!19 = !DILocation(line: 9, scope: !0, inlinedAt: !17)
 !20 = !{}
-!21 = !MDLocation(line: 9, scope: !11, inlinedAt: !17)
-!22 = !MDLocation(line: 11, scope: !11, inlinedAt: !17)
-!23 = !MDLocation(line: 16, scope: !18)
+!21 = !DILocation(line: 9, scope: !11, inlinedAt: !17)
+!22 = !DILocation(line: 11, scope: !11, inlinedAt: !17)
+!23 = !DILocation(line: 16, scope: !18)
 !24 = !{!9, !10}
 !25 = !{!0, !6}
 !26 = !{!16}
-!27 = !{!"bar.c", !"/tmp/"}
-!28 = !{i32 1, !"Debug Info Version", i32 2}
+!27 = !DIFile(filename: "bar.c", directory: "/tmp/")
+!28 = !{i32 1, !"Debug Info Version", i32 3}
 !29 = !{null}
diff --git a/test/DebugInfo/2010-07-19-Crash.ll b/test/DebugInfo/2010-07-19-Crash.ll
index 8bbe48c33e90..fbfe9f80189d 100644
--- a/test/DebugInfo/2010-07-19-Crash.ll
+++ b/test/DebugInfo/2010-07-19-Crash.ll
@@ -12,19 +12,19 @@ entry:
 !llvm.dbg.sp = !{!0, !6, !11}
 !llvm.dbg.lv.foo = !{!7}
 
-!0 = !{!"0x2e\00bar\00bar\00bar\003\000\001\000\006\000\001\000", !12, !1, !3, null, i32 ()* @bar, null, null, null} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !12} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang 2.8\001\00\000\00\000", !12, !14, !14, !13, null, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !12, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "bar", linkageName: "bar", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, file: !12, scope: !1, type: !3, function: i32 ()* @bar)
+!1 = !DIFile(filename: "one.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang 2.8", isOptimized: true, emissionKind: 0, file: !12, enums: !14, retainedTypes: !14, subprograms: !13)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", !12, !1} ; [ DW_TAG_base_type ]
-!6 = !{!"0x2e\00foo\00foo\00foo\007\001\001\000\006\000\001\000", !12, !1, !3, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!7 = !{!"0x100\00one\008\000", !8, !1, !5} ; [ DW_TAG_auto_variable ]
-!8 = !{!"0xb\007\0018\000", !12, !6} ; [ DW_TAG_lexical_block ]
-!9 = !MDLocation(line: 4, column: 3, scope: !10)
-!10 = !{!"0xb\003\0011\000", !12, !0} ; [ DW_TAG_lexical_block ]
-!11 = !{!"0x2e\00foo\00foo\00foo\007\001\000\000\006\000\001\000", !12, !1, !3, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!12 = !{!"one.c", !"/private/tmp"}
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DISubprogram(name: "foo", linkageName: "foo", line: 7, isLocal: true, isDefinition: true, virtualIndex: 6, isOptimized: true, file: !12, scope: !1, type: !3)
+!7 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "one", line: 8, scope: !8, file: !1, type: !5)
+!8 = distinct !DILexicalBlock(line: 7, column: 18, file: !12, scope: !6)
+!9 = !DILocation(line: 4, column: 3, scope: !10)
+!10 = distinct !DILexicalBlock(line: 3, column: 11, file: !12, scope: !0)
+!11 = !DISubprogram(name: "foo", linkageName: "foo", line: 7, isLocal: true, isDefinition: false, virtualIndex: 6, isOptimized: true, file: !12, scope: !1, type: !3)
+!12 = !DIFile(filename: "one.c", directory: "/private/tmp")
 !13 = !{!0}
-!14 = !{i32 0}
-!15 = !{i32 1, !"Debug Info Version", i32 2}
+!14 = !{}
+!15 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/2010-10-01-crash.ll b/test/DebugInfo/2010-10-01-crash.ll
index 5c822e94bece..5c736ba85552 100644
--- a/test/DebugInfo/2010-10-01-crash.ll
+++ b/test/DebugInfo/2010-10-01-crash.ll
@@ -1,10 +1,8 @@
 ; RUN: llc -O0 %s -o /dev/null
-; XFAIL: hexagon
-; PR 8235
 
 define void @CGRectStandardize(i32* sret %agg.result, i32* byval %rect) nounwind ssp {
 entry:
-  call void @llvm.dbg.declare(metadata i32* %rect, metadata !23, metadata !{!"0x102"}), !dbg !24
+  call void @llvm.dbg.declare(metadata i32* %rect, metadata !23, metadata !DIExpression()), !dbg !24
   ret void
 }
 
@@ -15,12 +13,12 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32,
 
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!27}
-!0 = !{!"0x2e\00CGRectStandardize\00CGRectStandardize\00CGRectStandardize\0054\000\001\000\006\000\000\000", !1, null, null, null, void (i32*, i32*)* @CGRectStandardize, null, null, null} ; [ DW_TAG_subprogram ] [line 54] [def] [scope 0] [CGRectStandardize]
-!1 = !{!"0x29", !25} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0016\00clang version 2.9 (trunk 115292)\001\00\001\00\000", !25, !26, !26, null, null, null} ; [ DW_TAG_compile_unit ]
-!5 = !{!"0x16\00CGRect\0049\000\000\000\000", !25, null, null} ; [ DW_TAG_typedef ]
-!23 = !{!"0x101\00rect\0053\000", !0, !1, !5} ; [ DW_TAG_arg_variable ]
-!24 = !MDLocation(line: 53, column: 33, scope: !0)
-!25 = !{!"GSFusedSilica.m", !"/Volumes/Data/Users/sabre/Desktop"}
-!26 = !{i32 0}
-!27 = !{i32 1, !"Debug Info Version", i32 2}
+!0 = !DISubprogram(name: "CGRectStandardize", linkageName: "CGRectStandardize", line: 54, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !1, scope: null, function: void (i32*, i32*)* @CGRectStandardize)
+!1 = !DIFile(filename: "GSFusedSilica.m", directory: "/Volumes/Data/Users/sabre/Desktop")
+!2 = !DICompileUnit(language: DW_LANG_ObjC, producer: "clang version 2.9 (trunk 115292)", isOptimized: true, runtimeVersion: 1, emissionKind: 0, file: !25, enums: !26, retainedTypes: !26)
+!5 = !DIDerivedType(tag: DW_TAG_typedef, name: "CGRect", line: 49, file: !25, baseType: null)
+!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "rect", line: 53, arg: 0, scope: !0, file: !1, type: !5)
+!24 = !DILocation(line: 53, column: 33, scope: !0)
+!25 = !DIFile(filename: "GSFusedSilica.m", directory: "/Volumes/Data/Users/sabre/Desktop")
+!26 = !{}
+!27 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/AArch64/big-endian.ll b/test/DebugInfo/AArch64/big-endian.ll
index 79e38c455996..45f49da63077 100644
--- a/test/DebugInfo/AArch64/big-endian.ll
+++ b/test/DebugInfo/AArch64/big-endian.ll
@@ -9,14 +9,14 @@ target triple = "aarch64_be--none-eabi"
 !llvm.module.flags = !{!8, !9}
 !llvm.ident = !{!10}
 
-!0 = !{!"0x11\0012\00clang version 3.6.0 \001\00\000\00\001", !1, !2, !2, !2, !3, !2} ; [ DW_TAG_compile_unit ] [/work/validation/-] [DW_LANG_C99]
-!1 = !{!"-", !"/work/validation"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.6.0 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3, imports: !2)
+!1 = !DIFile(filename: "-", directory: "/work/validation")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x34\00a\00a\00\001\000\001", null, !5, !7, i32* @a, null} ; [ DW_TAG_variable ] [a] [line 1] [def]
-!5 = !{!"0x29", !6}          ; [ DW_TAG_file_type ] [/work/validation/<stdin>]
+!4 = !DIGlobalVariable(name: "a", line: 1, isLocal: false, isDefinition: true, scope: null, file: !5, type: !7, variable: i32* @a)
+!5 = !DIFile(filename: "<stdin>", directory: "/work/validation")
 !6 = !{!"<stdin>", !"/work/validation"}
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !8 = !{i32 2, !"Dwarf Version", i32 4}
-!9 = !{i32 2, !"Debug Info Version", i32 2}
+!9 = !{i32 2, !"Debug Info Version", i32 3}
 !10 = !{!"clang version 3.6.0 "}
diff --git a/test/DebugInfo/AArch64/cfi-eof-prologue.ll b/test/DebugInfo/AArch64/cfi-eof-prologue.ll
index 2d68af629e32..756443a951dd 100644
--- a/test/DebugInfo/AArch64/cfi-eof-prologue.ll
+++ b/test/DebugInfo/AArch64/cfi-eof-prologue.ll
@@ -29,10 +29,10 @@ target triple = "aarch64-apple-ios"
 define %struct.B* @_ZN1BC2Ev(%struct.B* %this) unnamed_addr #0 align 2 {
 entry:
   tail call void @llvm.dbg.value(metadata %struct.B* %this, i64 0, metadata !30, metadata !38), !dbg !39
-  %0 = getelementptr inbounds %struct.B* %this, i64 0, i32 0, !dbg !40
+  %0 = getelementptr inbounds %struct.B, %struct.B* %this, i64 0, i32 0, !dbg !40
   %call = tail call %struct.A* @_ZN1AC2Ev(%struct.A* %0) #3, !dbg !40
-  %1 = getelementptr inbounds %struct.B* %this, i64 0, i32 0, i32 0, !dbg !40
-  store i32 (...)** bitcast (i8** getelementptr inbounds ([4 x i8*]* @_ZTV1B, i64 0, i64 2) to i32 (...)**), i32 (...)*** %1, align 8, !dbg !40, !tbaa !41
+  %1 = getelementptr inbounds %struct.B, %struct.B* %this, i64 0, i32 0, i32 0, !dbg !40
+  store i32 (...)** bitcast (i8** getelementptr inbounds ([4 x i8*], [4 x i8*]* @_ZTV1B, i64 0, i64 2) to i32 (...)**), i32 (...)*** %1, align 8, !dbg !40, !tbaa !41
   ret %struct.B* %this, !dbg !40
 }
 
@@ -43,10 +43,10 @@ define %struct.B* @_ZN1BC1Ev(%struct.B* %this) unnamed_addr #0 align 2 {
 entry:
   tail call void @llvm.dbg.value(metadata %struct.B* %this, i64 0, metadata !34, metadata !38), !dbg !44
   tail call void @llvm.dbg.value(metadata %struct.B* %this, i64 0, metadata !45, metadata !38) #3, !dbg !47
-  %0 = getelementptr inbounds %struct.B* %this, i64 0, i32 0, !dbg !48
+  %0 = getelementptr inbounds %struct.B, %struct.B* %this, i64 0, i32 0, !dbg !48
   %call.i = tail call %struct.A* @_ZN1AC2Ev(%struct.A* %0) #3, !dbg !48
-  %1 = getelementptr inbounds %struct.B* %this, i64 0, i32 0, i32 0, !dbg !48
-  store i32 (...)** bitcast (i8** getelementptr inbounds ([4 x i8*]* @_ZTV1B, i64 0, i64 2) to i32 (...)**), i32 (...)*** %1, align 8, !dbg !48, !tbaa !41
+  %1 = getelementptr inbounds %struct.B, %struct.B* %this, i64 0, i32 0, i32 0, !dbg !48
+  store i32 (...)** bitcast (i8** getelementptr inbounds ([4 x i8*], [4 x i8*]* @_ZTV1B, i64 0, i64 2) to i32 (...)**), i32 (...)*** %1, align 8, !dbg !48, !tbaa !41
   ret %struct.B* %this, !dbg !46
 }
 
@@ -61,52 +61,52 @@ attributes #3 = { nounwind }
 !llvm.module.flags = !{!35, !36}
 !llvm.ident = !{!37}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 (trunk 224279) (llvm/trunk 224283)\001\00\000\00\001", !1, !2, !3, !27, !2, !2} ; [ DW_TAG_compile_unit ] [<stdin>] [DW_LANG_C_plus_plus]
-!1 = !{!"<stdin>", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 (trunk 224279) (llvm/trunk 224283)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !27, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<stdin>", directory: "")
 !2 = !{}
 !3 = !{!4, !13}
-!4 = !{!"0x13\00B\005\0064\0064\000\000\000", !5, null, null, !6, !"_ZTS1A", null, !"_ZTS1B"} ; [ DW_TAG_structure_type ] [B] [line 5, size 64, align 64, offset 0] [def] [from ]
-!5 = !{!"test1.cpp", !""}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "B", line: 5, size: 64, align: 64, file: !5, elements: !6, vtableHolder: !"_ZTS1A", identifier: "_ZTS1B")
+!5 = !DIFile(filename: "test1.cpp", directory: "")
 !6 = !{!7, !8, !12}
-!7 = !{!"0x1c\00\000\000\000\000\000", null, !"_ZTS1B", !"_ZTS1A"} ; [ DW_TAG_inheritance ] [line 0, size 0, align 0, offset 0] [from _ZTS1A]
-!8 = !{!"0x2e\00B\00B\00\006\000\000\000\000\00256\001\006", !5, !"_ZTS1B", !9, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 6] [B]
-!9 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = !DIDerivedType(tag: DW_TAG_inheritance, scope: !"_ZTS1B", baseType: !"_ZTS1A")
+!8 = !DISubprogram(name: "B", line: 6, isLocal: false, isDefinition: false, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 6, file: !5, scope: !"_ZTS1B", type: !9)
+!9 = !DISubroutineType(types: !10)
 !10 = !{null, !11}
-!11 = !{!"0xf\00\000\0064\0064\000\001088\00", null, null, !"_ZTS1B"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1B]
-!12 = !{!"0x2e\00~B\00~B\00\007\000\000\001\000\00256\001\007", !5, !"_ZTS1B", !9, !"_ZTS1B", null, null, null, null} ; [ DW_TAG_subprogram ] [line 7] [~B]
-!13 = !{!"0x13\00A\001\0064\0064\000\000\000", !5, null, null, !14, !"_ZTS1A", null, !"_ZTS1A"} ; [ DW_TAG_structure_type ] [A] [line 1, size 64, align 64, offset 0] [def] [from ]
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1B")
+!12 = !DISubprogram(name: "~B", line: 7, isLocal: false, isDefinition: false, virtuality: DW_VIRTUALITY_virtual, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 7, file: !5, scope: !"_ZTS1B", type: !9, containingType: !"_ZTS1B")
+!13 = !DICompositeType(tag: DW_TAG_structure_type, name: "A", line: 1, size: 64, align: 64, file: !5, elements: !14, vtableHolder: !"_ZTS1A", identifier: "_ZTS1A")
 !14 = !{!15, !22, !26}
-!15 = !{!"0xd\00_vptr$A\000\0064\000\000\0064", !5, !16, !17} ; [ DW_TAG_member ] [_vptr$A] [line 0, size 64, align 0, offset 0] [artificial] [from ]
-!16 = !{!"0x29", !5}                              ; [ DW_TAG_file_type ] [test1.cpp]
-!17 = !{!"0xf\00\000\0064\000\000\000", null, null, !18} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from __vtbl_ptr_type]
-!18 = !{!"0xf\00__vtbl_ptr_type\000\0064\000\000\000", null, null, !19} ; [ DW_TAG_pointer_type ] [__vtbl_ptr_type] [line 0, size 64, align 0, offset 0] [from ]
-!19 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !20, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!15 = !DIDerivedType(tag: DW_TAG_member, name: "_vptr$A", size: 64, flags: DIFlagArtificial, file: !5, scope: !16, baseType: !17)
+!16 = !DIFile(filename: "test1.cpp", directory: "")
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, baseType: !18)
+!18 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "__vtbl_ptr_type", size: 64, baseType: !19)
+!19 = !DISubroutineType(types: !20)
 !20 = !{!21}
-!21 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!22 = !{!"0x2e\00A\00A\00\002\000\000\000\000\00256\001\002", !5, !"_ZTS1A", !23, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 2] [A]
-!23 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !24, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!21 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!22 = !DISubprogram(name: "A", line: 2, isLocal: false, isDefinition: false, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2, file: !5, scope: !"_ZTS1A", type: !23)
+!23 = !DISubroutineType(types: !24)
 !24 = !{null, !25}
-!25 = !{!"0xf\00\000\0064\0064\000\001088\00", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1A]
-!26 = !{!"0x2e\00~A\00~A\00\003\000\000\001\000\00256\001\003", !5, !"_ZTS1A", !23, !"_ZTS1A", null, null, null, null} ; [ DW_TAG_subprogram ] [line 3] [~A]
+!25 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1A")
+!26 = !DISubprogram(name: "~A", line: 3, isLocal: false, isDefinition: false, virtuality: DW_VIRTUALITY_virtual, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !5, scope: !"_ZTS1A", type: !23, containingType: !"_ZTS1A")
 !27 = !{!28, !32}
-!28 = !{!"0x2e\00B\00B\00_ZN1BC2Ev\009\000\001\000\000\00256\001\009", !5, !"_ZTS1B", !9, null, %struct.B* (%struct.B*)* @_ZN1BC2Ev, null, !8, !29} ; [ DW_TAG_subprogram ] [line 9] [def] [B]
+!28 = !DISubprogram(name: "B", linkageName: "_ZN1BC2Ev", line: 9, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 9, file: !5, scope: !"_ZTS1B", type: !9, function: %struct.B* (%struct.B*)* @_ZN1BC2Ev, declaration: !8, variables: !29)
 !29 = !{!30}
-!30 = !{!"0x101\00this\0016777216\001088", !28, null, !31} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!31 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1B"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1B]
-!32 = !{!"0x2e\00B\00B\00_ZN1BC1Ev\009\000\001\000\000\00256\001\009", !5, !"_ZTS1B", !9, null, %struct.B* (%struct.B*)* @_ZN1BC1Ev, null, !8, !33} ; [ DW_TAG_subprogram ] [line 9] [def] [B]
+!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !28, type: !31)
+!31 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1B")
+!32 = !DISubprogram(name: "B", linkageName: "_ZN1BC1Ev", line: 9, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 9, file: !5, scope: !"_ZTS1B", type: !9, function: %struct.B* (%struct.B*)* @_ZN1BC1Ev, declaration: !8, variables: !33)
 !33 = !{!34}
-!34 = !{!"0x101\00this\0016777216\001088", !32, null, !31} ; [ DW_TAG_arg_variable ] [this] [line 0]
+!34 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !32, type: !31)
 !35 = !{i32 2, !"Dwarf Version", i32 4}
-!36 = !{i32 2, !"Debug Info Version", i32 2}
+!36 = !{i32 2, !"Debug Info Version", i32 3}
 !37 = !{!"clang version 3.6.0 (trunk 224279) (llvm/trunk 224283)"}
-!38 = !{!"0x102"}                                 ; [ DW_TAG_expression ]
-!39 = !MDLocation(line: 0, scope: !28)
-!40 = !MDLocation(line: 9, scope: !28)
+!38 = !DIExpression()
+!39 = !DILocation(line: 0, scope: !28)
+!40 = !DILocation(line: 9, scope: !28)
 !41 = !{!42, !42, i64 0}
 !42 = !{!"vtable pointer", !43, i64 0}
 !43 = !{!"Simple C/C++ TBAA"}
-!44 = !MDLocation(line: 0, scope: !32)
-!45 = !{!"0x101\00this\0016777216\001088", !28, null, !31, !46} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!46 = !MDLocation(line: 9, scope: !32)
-!47 = !MDLocation(line: 0, scope: !28, inlinedAt: !46)
-!48 = !MDLocation(line: 9, scope: !28, inlinedAt: !46)
+!44 = !DILocation(line: 0, scope: !32)
+!45 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !28, type: !31)
+!46 = !DILocation(line: 9, scope: !32)
+!47 = !DILocation(line: 0, scope: !28, inlinedAt: !46)
+!48 = !DILocation(line: 9, scope: !28, inlinedAt: !46)
diff --git a/test/DebugInfo/AArch64/coalescing.ll b/test/DebugInfo/AArch64/coalescing.ll
index 35bb04138c13..b1d566197126 100644
--- a/test/DebugInfo/AArch64/coalescing.ll
+++ b/test/DebugInfo/AArch64/coalescing.ll
@@ -44,22 +44,22 @@ attributes #3 = { nounwind optsize }
 !llvm.module.flags = !{!12, !13}
 !llvm.ident = !{!14}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 (trunk 223149) (llvm/trunk 223115)\001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [<stdin>] [DW_LANG_C_plus_plus]
-!1 = !{!"<stdin>", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 (trunk 223149) (llvm/trunk 223115)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<stdin>", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00start\00start\00_Z5startv\002\000\001\000\000\00256\001\003", !5, !6, !7, null, void ()* @_Z5startv, null, null, !9} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 3] [start]
-!5 = !{!"test1.c", !""}
-!6 = !{!"0x29", !5}    ; [ DW_TAG_file_type ] [/test1.c]
-!7 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "start", linkageName: "_Z5startv", line: 2, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !5, scope: !6, type: !7, function: void ()* @_Z5startv, variables: !9)
+!5 = !DIFile(filename: "test1.c", directory: "")
+!6 = !DIFile(filename: "test1.c", directory: "")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null}
 !9 = !{!10}
-!10 = !{!"0x100\00size\004\000", !4, !6, !11} ; [ DW_TAG_auto_variable ] [size] [line 4]
-!11 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, null} ; [ DW_TAG_base_type ] [unsigned int] [line 0, size 32, align 32, offset 0, enc DW_ATE_unsigned]
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "size", line: 4, scope: !4, file: !6, type: !11)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
 !12 = !{i32 2, !"Dwarf Version", i32 2}
-!13 = !{i32 2, !"Debug Info Version", i32 2}
+!13 = !{i32 2, !"Debug Info Version", i32 3}
 !14 = !{!"clang version 3.6.0 (trunk 223149) (llvm/trunk 223115)"}
-!15 = !MDLocation(line: 5, column: 3, scope: !4)
-!16 = !{!"0x102"}               ; [ DW_TAG_expression ]
-!17 = !MDLocation(line: 4, column: 12, scope: !4)
-!18 = !MDLocation(line: 8, column: 1, scope: !4)
+!15 = !DILocation(line: 5, column: 3, scope: !4)
+!16 = !DIExpression()
+!17 = !DILocation(line: 4, column: 12, scope: !4)
+!18 = !DILocation(line: 8, column: 1, scope: !4)
diff --git a/test/DebugInfo/AArch64/constant-dbgloc.ll b/test/DebugInfo/AArch64/constant-dbgloc.ll
new file mode 100644
index 000000000000..a71b869f5366
--- /dev/null
+++ b/test/DebugInfo/AArch64/constant-dbgloc.ll
@@ -0,0 +1,37 @@
+; RUN: llc -filetype=asm %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "aarch64--linux-gnueabihf"
+
+; int
+; main(void)
+; {
+;     return -1;
+; }
+
+; CHECK: test.c:4:5
+; CHECK: movn
+
+; Function Attrs: nounwind
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  ret i32 -1, !dbg !11
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!8, !9}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, subprograms: !3)
+!1 = !DIFile(filename: "test.c", directory: "/home/user/clang/build")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "main", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: false, function: i32 ()* @main, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{!7}
+!7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !{i32 2, !"Dwarf Version", i32 4}
+!9 = !{i32 2, !"Debug Info Version", i32 3}
+!10 = !{i32 1, !"wchar_size", i32 4}
+!11 = !DILocation(line: 4, column: 5, scope: !4)
diff --git a/test/DebugInfo/AArch64/dwarfdump.ll b/test/DebugInfo/AArch64/dwarfdump.ll
index cba18b2b23b1..3e95a6fe314f 100644
--- a/test/DebugInfo/AArch64/dwarfdump.ll
+++ b/test/DebugInfo/AArch64/dwarfdump.ll
@@ -27,14 +27,14 @@ attributes #0 = { nounwind }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!10}
 
-!0 = !{!"0x11\0012\00clang version 3.3 \000\00\000\00\000", !9, !1, !1, !2, !1,  !1} ; [ DW_TAG_compile_unit ] [/home/timnor01/llvm/build/tmp.c] [DW_LANG_C99]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.3 ", isOptimized: false, emissionKind: 0, file: !9, enums: !1, retainedTypes: !1, subprograms: !2, globals: !1, imports:  !1)
 !1 = !{}
 !2 = !{!3}
-!3 = !{!"0x2e\00main\00main\00\001\000\001\000\006\000\000\001", !9, !4, !5, null, i32 ()* @main, null, null, !1} ; [ DW_TAG_subprogram ] [line 1] [def] [main]
-!4 = !{!"0x29", !9} ; [ DW_TAG_file_type ]
-!5 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !6, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!3 = !DISubprogram(name: "main", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !9, scope: !4, type: !5, function: i32 ()* @main, variables: !1)
+!4 = !DIFile(filename: "tmp.c", directory: "/home/tim/llvm/build")
+!5 = !DISubroutineType(types: !6)
 !6 = !{!7}
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!8 = !MDLocation(line: 2, scope: !3)
-!9 = !{!"tmp.c", !"/home/tim/llvm/build"}
-!10 = !{i32 1, !"Debug Info Version", i32 2}
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DILocation(line: 2, scope: !3)
+!9 = !DIFile(filename: "tmp.c", directory: "/home/tim/llvm/build")
+!10 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/AArch64/eh_frame.s b/test/DebugInfo/AArch64/eh_frame.s
index 12a58961d717..65367751223e 100644
--- a/test/DebugInfo/AArch64/eh_frame.s
+++ b/test/DebugInfo/AArch64/eh_frame.s
@@ -17,7 +17,7 @@ foo:
 // Output is:
 
 // CHECK: Contents of section .eh_frame:
-// CHECK-NEXT: 0000 10000000 00000000 037a5200 017c1e01  .........zR..|..
+// CHECK-NEXT: 0000 10000000 00000000 017a5200 017c1e01  .........zR..|..
 // CHECK-NEXT: 0010 1b0c1f00 10000000 18000000 00000000  ................
 
 
diff --git a/test/DebugInfo/AArch64/eh_frame_personality.ll b/test/DebugInfo/AArch64/eh_frame_personality.ll
index 51d6bf80b950..e2832a8c62ca 100644
--- a/test/DebugInfo/AArch64/eh_frame_personality.ll
+++ b/test/DebugInfo/AArch64/eh_frame_personality.ll
@@ -16,7 +16,7 @@ clean:
 }
 
 ; CHECK: Contents of section .eh_frame:
-; CHECK: 0000 1c000000 00000000 037a504c 5200017c  .........zPLR..|
+; CHECK: 0000 1c000000 00000000 017a504c 5200017c  .........zPLR..|
 ; CHECK: 0010 1e0b0000 00000000 00000000 1b0c1f00  ................
 
 ; Don't really care about the rest:
diff --git a/test/DebugInfo/AArch64/frameindices.ll b/test/DebugInfo/AArch64/frameindices.ll
new file mode 100644
index 000000000000..0891cfbbdea8
--- /dev/null
+++ b/test/DebugInfo/AArch64/frameindices.ll
@@ -0,0 +1,257 @@
+; RUN: llc -O0 -filetype=obj < %s | llvm-dwarfdump - | FileCheck %s
+; Test that a variable with multiple entries in the MMI table makes it into the
+; debug info.
+;
+; CHECK: DW_TAG_inlined_subroutine
+; CHECK:    "_Z3f111A"
+; CHECK: DW_TAG_formal_parameter
+; CHECK: DW_AT_location [DW_FORM_block1]    (<0x0b> 91 51 9d 78 08 91 4a 9d 38 88 01 )
+;  -- fbreg -47, bit-piece 120 8 , fbreg -54, bit-piece 56 136 ------^
+; CHECK: DW_AT_abstract_origin {{.*}} "p1"
+;
+; long a;
+; struct A {
+;   bool x4;
+;   void *x5;
+;   bool x6;
+; };
+; int *b;
+; struct B {
+;   B(long);
+;   ~B();
+; };
+; void f9(A);
+; void f13(A p1) {
+;   b = (int *)__builtin_operator_new(a);
+;   f9(p1);
+; }
+; void f11(A p1) { f13(p1); }
+; void f16() {
+;   A c;
+;   B d(a);
+;   c.x6 = c.x4 = true;
+;   f11(c);
+; }
+; ModuleID = 'test.cpp'
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-apple-ios"
+
+%struct.A = type { i8, i8*, i8 }
+%struct.B = type { i8 }
+
+@a = global i64 0, align 8
+@b = global i32* null, align 8
+
+define void @_Z3f131A(%struct.A* nocapture readonly %p1) #0 {
+entry:
+  %agg.tmp = alloca %struct.A, align 8
+  tail call void @llvm.dbg.declare(metadata %struct.A* %p1, metadata !30, metadata !46), !dbg !47
+  %0 = load i64, i64* @a, align 8, !dbg !48, !tbaa !49
+  %call = tail call noalias i8* @_Znwm(i64 %0) #5, !dbg !53
+  store i8* %call, i8** bitcast (i32** @b to i8**), align 8, !dbg !54, !tbaa !55
+  %1 = getelementptr inbounds %struct.A, %struct.A* %agg.tmp, i64 0, i32 0, !dbg !57
+  %2 = getelementptr inbounds %struct.A, %struct.A* %p1, i64 0, i32 0, !dbg !57
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 24, i32 8, i1 false), !dbg !57, !tbaa.struct !58
+  call void @_Z2f91A(%struct.A* %agg.tmp), !dbg !61
+  ret void, !dbg !62
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+; Function Attrs: nobuiltin
+declare noalias i8* @_Znwm(i64) #2
+
+declare void @_Z2f91A(%struct.A*) #0
+
+; Function Attrs: nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #3
+
+define void @_Z3f111A(%struct.A* nocapture readonly %p1) #0 {
+entry:
+  %agg.tmp.i = alloca %struct.A, align 8
+  tail call void @llvm.dbg.declare(metadata %struct.A* %p1, metadata !33, metadata !46), !dbg !63
+  %0 = getelementptr inbounds %struct.A, %struct.A* %p1, i64 0, i32 0, !dbg !64
+  %1 = getelementptr inbounds %struct.A, %struct.A* %agg.tmp.i, i64 0, i32 0, !dbg !65
+  call void @llvm.lifetime.start(i64 24, i8* %1), !dbg !65
+  %2 = load i64, i64* @a, align 8, !dbg !67, !tbaa !49
+  %call.i = tail call noalias i8* @_Znwm(i64 %2) #5, !dbg !68
+  store i8* %call.i, i8** bitcast (i32** @b to i8**), align 8, !dbg !69, !tbaa !55
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %0, i64 24, i32 8, i1 false), !dbg !70
+  call void @_Z2f91A(%struct.A* %agg.tmp.i), !dbg !71
+  call void @llvm.lifetime.end(i64 24, i8* %1), !dbg !72
+  ret void, !dbg !73
+}
+
+define void @_Z3f16v() #0 {
+entry:
+  %agg.tmp.i.i = alloca %struct.A, align 8
+  %d = alloca %struct.B, align 1
+  %agg.tmp.sroa.2 = alloca [15 x i8], align 1
+  %agg.tmp.sroa.4 = alloca [7 x i8], align 1
+  tail call void @llvm.dbg.declare(metadata [15 x i8]* %agg.tmp.sroa.2, metadata !74, metadata !76), !dbg !77
+  tail call void @llvm.dbg.declare(metadata [7 x i8]* %agg.tmp.sroa.4, metadata !74, metadata !78), !dbg !77
+  tail call void @llvm.dbg.declare(metadata %struct.A* undef, metadata !38, metadata !79), !dbg !80
+  %0 = load i64, i64* @a, align 8, !dbg !81, !tbaa !49
+  tail call void @llvm.dbg.value(metadata %struct.B* %d, i64 0, metadata !39, metadata !79), !dbg !82
+  %call = call %struct.B* @_ZN1BC1El(%struct.B* %d, i64 %0), !dbg !82
+  call void @llvm.dbg.value(metadata i8 1, i64 0, metadata !38, metadata !83), !dbg !80
+  call void @llvm.dbg.value(metadata i8 1, i64 0, metadata !38, metadata !84), !dbg !80
+  call void @llvm.dbg.value(metadata i8 1, i64 0, metadata !74, metadata !83), !dbg !77
+  call void @llvm.dbg.value(metadata i8 1, i64 0, metadata !74, metadata !84), !dbg !77
+  call void @llvm.dbg.declare(metadata %struct.A* undef, metadata !74, metadata !46), !dbg !77
+  %1 = getelementptr inbounds %struct.A, %struct.A* %agg.tmp.i.i, i64 0, i32 0, !dbg !85
+  call void @llvm.lifetime.start(i64 24, i8* %1), !dbg !85
+  %2 = load i64, i64* @a, align 8, !dbg !87, !tbaa !49
+  %call.i.i5 = invoke noalias i8* @_Znwm(i64 %2) #5
+          to label %call.i.i.noexc unwind label %lpad, !dbg !88
+
+call.i.i.noexc:                                   ; preds = %entry
+  %agg.tmp.sroa.4.17..sroa_idx = getelementptr inbounds [7 x i8], [7 x i8]* %agg.tmp.sroa.4, i64 0, i64 0, !dbg !89
+  %agg.tmp.sroa.2.1..sroa_idx = getelementptr inbounds [15 x i8], [15 x i8]* %agg.tmp.sroa.2, i64 0, i64 0, !dbg !89
+  store i8* %call.i.i5, i8** bitcast (i32** @b to i8**), align 8, !dbg !90, !tbaa !55
+  store i8 1, i8* %1, align 8, !dbg !91
+  %agg.tmp.sroa.2.0..sroa_raw_idx = getelementptr inbounds i8, i8* %1, i64 1, !dbg !91
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %agg.tmp.sroa.2.0..sroa_raw_idx, i8* %agg.tmp.sroa.2.1..sroa_idx, i64 15, i32 1, i1 false), !dbg !91
+  %agg.tmp.sroa.3.0..sroa_idx = getelementptr inbounds %struct.A, %struct.A* %agg.tmp.i.i, i64 0, i32 2, !dbg !91
+  store i8 1, i8* %agg.tmp.sroa.3.0..sroa_idx, align 8, !dbg !91
+  %agg.tmp.sroa.4.0..sroa_raw_idx = getelementptr inbounds i8, i8* %1, i64 17, !dbg !91
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %agg.tmp.sroa.4.0..sroa_raw_idx, i8* %agg.tmp.sroa.4.17..sroa_idx, i64 7, i32 1, i1 false), !dbg !91
+  invoke void @_Z2f91A(%struct.A* %agg.tmp.i.i)
+          to label %invoke.cont unwind label %lpad, !dbg !92
+
+invoke.cont:                                      ; preds = %call.i.i.noexc
+  call void @llvm.lifetime.end(i64 24, i8* %1), !dbg !93
+  call void @llvm.dbg.value(metadata %struct.B* %d, i64 0, metadata !39, metadata !79), !dbg !82
+  %call1 = call %struct.B* @_ZN1BD1Ev(%struct.B* %d) #3, !dbg !94
+  ret void, !dbg !94
+
+lpad:                                             ; preds = %call.i.i.noexc, %entry
+  %3 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup, !dbg !94
+  call void @llvm.dbg.value(metadata %struct.B* %d, i64 0, metadata !39, metadata !79), !dbg !82
+  %call2 = call %struct.B* @_ZN1BD1Ev(%struct.B* %d) #3, !dbg !94
+  resume { i8*, i32 } %3, !dbg !94
+}
+
+declare %struct.B* @_ZN1BC1El(%struct.B*, i64)
+
+declare i32 @__gxx_personality_v0(...)
+
+; Function Attrs: nounwind
+declare %struct.B* @_ZN1BD1Ev(%struct.B*) #4
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
+
+; Function Attrs: nounwind
+declare void @llvm.lifetime.start(i64, i8* nocapture) #3
+
+; Function Attrs: nounwind
+declare void @llvm.lifetime.end(i64, i8* nocapture) #3
+
+attributes #1 = { nounwind readnone }
+attributes #2 = { nobuiltin }
+attributes #3 = { nounwind }
+attributes #4 = { nounwind  }
+attributes #5 = { builtin }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!43, !44}
+!llvm.ident = !{!45}
+
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.7.0 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !24, globals: !40, imports: !2)
+!1 = !DIFile(filename: "<stdin>", directory: "")
+!2 = !{}
+!3 = !{!4, !12, !14}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "A", line: 2, size: 192, align: 64, file: !5, elements: !6, identifier: "_ZTS1A")
+!5 = !DIFile(filename: "test.cpp", directory: "")
+!6 = !{!7, !9, !11}
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "x4", line: 3, size: 8, align: 8, file: !5, scope: !"_ZTS1A", baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "bool", size: 8, align: 8, encoding: DW_ATE_boolean)
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "x5", line: 4, size: 64, align: 64, offset: 64, file: !5, scope: !"_ZTS1A", baseType: !10)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: null)
+!11 = !DIDerivedType(tag: DW_TAG_member, name: "x6", line: 5, size: 8, align: 8, offset: 128, file: !5, scope: !"_ZTS1A", baseType: !8)
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !13)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!14 = !DICompositeType(tag: DW_TAG_structure_type, name: "B", line: 8, size: 8, align: 8, file: !5, elements: !15, identifier: "_ZTS1B")
+!15 = !{!16, !21}
+!16 = !DISubprogram(name: "B", line: 9, isLocal: false, isDefinition: false, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 9, file: !5, scope: !"_ZTS1B", type: !17)
+!17 = !DISubroutineType(types: !18)
+!18 = !{null, !19, !20}
+!19 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1B")
+!20 = !DIBasicType(tag: DW_TAG_base_type, name: "long int", size: 64, align: 64, encoding: DW_ATE_signed)
+!21 = !DISubprogram(name: "~B", line: 10, isLocal: false, isDefinition: false, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 10, file: !5, scope: !"_ZTS1B", type: !22)
+!22 = !DISubroutineType(types: !23)
+!23 = !{null, !19}
+!24 = !{!25, !31, !34}
+!25 = !DISubprogram(name: "f13", linkageName: "_Z3f131A", line: 13, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 13, file: !5, scope: !26, type: !27, function: void (%struct.A*)* @_Z3f131A, variables: !29)
+!26 = !DIFile(filename: "test.cpp", directory: "")
+!27 = !DISubroutineType(types: !28)
+!28 = !{null, !"_ZTS1A"}
+!29 = !{!30}
+!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p1", line: 13, arg: 1, scope: !25, file: !26, type: !"_ZTS1A")
+!31 = !DISubprogram(name: "f11", linkageName: "_Z3f111A", line: 17, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 17, file: !5, scope: !26, type: !27, function: void (%struct.A*)* @_Z3f111A, variables: !32)
+!32 = !{!33}
+!33 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p1", line: 17, arg: 1, scope: !31, file: !26, type: !"_ZTS1A")
+!34 = !DISubprogram(name: "f16", linkageName: "_Z3f16v", line: 18, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 18, file: !5, scope: !26, type: !35, function: void ()* @_Z3f16v, variables: !37)
+!35 = !DISubroutineType(types: !36)
+!36 = !{null}
+!37 = !{!38, !39}
+!38 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "c", line: 19, scope: !34, file: !26, type: !"_ZTS1A")
+!39 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "d", line: 20, scope: !34, file: !26, type: !"_ZTS1B")
+!40 = !{!41, !42}
+!41 = !DIGlobalVariable(name: "a", line: 1, isLocal: false, isDefinition: true, scope: null, file: !26, type: !20, variable: i64* @a)
+!42 = !DIGlobalVariable(name: "b", line: 7, isLocal: false, isDefinition: true, scope: null, file: !26, type: !12, variable: i32** @b)
+!43 = !{i32 2, !"Dwarf Version", i32 2}
+!44 = !{i32 2, !"Debug Info Version", i32 3}
+!45 = !{!"clang version 3.7.0 "}
+!46 = !DIExpression(DW_OP_deref)
+!47 = !DILocation(line: 13, column: 12, scope: !25)
+!48 = !DILocation(line: 14, column: 37, scope: !25)
+!49 = !{!50, !50, i64 0}
+!50 = !{!"long", !51, i64 0}
+!51 = !{!"omnipotent char", !52, i64 0}
+!52 = !{!"Simple C/C++ TBAA"}
+!53 = !DILocation(line: 14, column: 14, scope: !25)
+!54 = !DILocation(line: 14, column: 5, scope: !25)
+!55 = !{!56, !56, i64 0}
+!56 = !{!"any pointer", !51, i64 0}
+!57 = !DILocation(line: 15, column: 6, scope: !25)
+!58 = !{i64 0, i64 1, !59, i64 8, i64 8, !55, i64 16, i64 1, !59}
+!59 = !{!60, !60, i64 0}
+!60 = !{!"bool", !51, i64 0}
+!61 = !DILocation(line: 15, column: 3, scope: !25)
+!62 = !DILocation(line: 16, column: 1, scope: !25)
+!63 = !DILocation(line: 17, column: 12, scope: !31)
+!64 = !DILocation(line: 17, column: 22, scope: !31)
+!65 = !DILocation(line: 13, column: 12, scope: !25, inlinedAt: !66)
+!66 = distinct !DILocation(line: 17, column: 18, scope: !31)
+!67 = !DILocation(line: 14, column: 37, scope: !25, inlinedAt: !66)
+!68 = !DILocation(line: 14, column: 14, scope: !25, inlinedAt: !66)
+!69 = !DILocation(line: 14, column: 5, scope: !25, inlinedAt: !66)
+!70 = !DILocation(line: 15, column: 6, scope: !25, inlinedAt: !66)
+!71 = !DILocation(line: 15, column: 3, scope: !25, inlinedAt: !66)
+!72 = !DILocation(line: 16, column: 1, scope: !25, inlinedAt: !66)
+!73 = !DILocation(line: 17, column: 27, scope: !31)
+!74 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p1", line: 17, arg: 1, scope: !31, file: !26, type: !"_ZTS1A")
+!75 = distinct !DILocation(line: 22, column: 3, scope: !34)
+!76 = !DIExpression(DW_OP_bit_piece, 8, 120)
+!77 = !DILocation(line: 17, column: 12, scope: !31, inlinedAt: !75)
+!78 = !DIExpression(DW_OP_bit_piece, 136, 56)
+!79 = !DIExpression()
+!80 = !DILocation(line: 19, column: 5, scope: !34)
+!81 = !DILocation(line: 20, column: 7, scope: !34)
+!82 = !DILocation(line: 20, column: 5, scope: !34)
+!83 = !DIExpression(DW_OP_bit_piece, 0, 8)
+!84 = !DIExpression(DW_OP_bit_piece, 128, 8)
+!85 = !DILocation(line: 13, column: 12, scope: !25, inlinedAt: !86)
+!86 = distinct !DILocation(line: 17, column: 18, scope: !31, inlinedAt: !75)
+!87 = !DILocation(line: 14, column: 37, scope: !25, inlinedAt: !86)
+!88 = !DILocation(line: 14, column: 14, scope: !25, inlinedAt: !86)
+!89 = !DILocation(line: 22, column: 7, scope: !34)
+!90 = !DILocation(line: 14, column: 5, scope: !25, inlinedAt: !86)
+!91 = !DILocation(line: 15, column: 6, scope: !25, inlinedAt: !86)
+!92 = !DILocation(line: 15, column: 3, scope: !25, inlinedAt: !86)
+!93 = !DILocation(line: 16, column: 1, scope: !25, inlinedAt: !86)
+!94 = !DILocation(line: 23, column: 1, scope: !34)
diff --git a/test/DebugInfo/AArch64/struct_by_value.ll b/test/DebugInfo/AArch64/struct_by_value.ll
index f66f56cef5bc..dc9ac42e8a0f 100644
--- a/test/DebugInfo/AArch64/struct_by_value.ll
+++ b/test/DebugInfo/AArch64/struct_by_value.ll
@@ -1,6 +1,7 @@
 ; A by-value struct is a register-indirect value (breg).
 ; RUN: llc %s -filetype=asm -o - | FileCheck %s
 
+; CHECK: Lsection_info:
 ; CHECK: DW_AT_location
 ; CHECK-NEXT: .byte 112
 ; 112 = 0x70 = DW_OP_breg0
@@ -32,9 +33,9 @@ target triple = "arm64-apple-ios3.0.0"
 ; Function Attrs: nounwind ssp
 define i32 @return_five_int(%struct.five* %f) #0 {
 entry:
-  call void @llvm.dbg.declare(metadata %struct.five* %f, metadata !17, metadata !{!"0x102"}), !dbg !18
-  %a = getelementptr inbounds %struct.five* %f, i32 0, i32 0, !dbg !19
-  %0 = load i32* %a, align 4, !dbg !19
+  call void @llvm.dbg.declare(metadata %struct.five* %f, metadata !17, metadata !DIExpression(DW_OP_deref)), !dbg !18
+  %a = getelementptr inbounds %struct.five, %struct.five* %f, i32 0, i32 0, !dbg !19
+  %0 = load i32, i32* %a, align 4, !dbg !19
   ret i32 %0, !dbg !19
 }
 
@@ -47,24 +48,24 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!16, !20}
 
-!0 = !{!"0x11\0012\00LLVM version 3.4 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [struct_by_value.c] [DW_LANG_C99]
-!1 = !{!"struct_by_value.c", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "LLVM version 3.4 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "struct_by_value.c", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00return_five_int\00return_five_int\00\0013\000\001\000\006\00256\000\0014", !1, !5, !6, null, i32 (%struct.five*)* @return_five_int, null, null, !2} ; [ DW_TAG_subprogram ] [line 13] [def] [scope 14] [return_five_int]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [struct_by_value.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "return_five_int", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 14, file: !1, scope: !5, type: !6, function: i32 (%struct.five*)* @return_five_int, variables: !2)
+!5 = !DIFile(filename: "struct_by_value.c", directory: "")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !9}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x13\00five\001\00160\0032\000\000\000", !1, null, null, !10, null, null, null} ; [ DW_TAG_structure_type ] [five] [line 1, size 160, align 32, offset 0] [def] [from ]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DICompositeType(tag: DW_TAG_structure_type, name: "five", line: 1, size: 160, align: 32, file: !1, elements: !10)
 !10 = !{!11, !12, !13, !14, !15}
-!11 = !{!"0xd\00a\003\0032\0032\000\000", !1, !9, !8} ; [ DW_TAG_member ] [a] [line 3, size 32, align 32, offset 0] [from int]
-!12 = !{!"0xd\00b\004\0032\0032\0032\000", !1, !9, !8} ; [ DW_TAG_member ] [b] [line 4, size 32, align 32, offset 32] [from int]
-!13 = !{!"0xd\00c\005\0032\0032\0064\000", !1, !9, !8} ; [ DW_TAG_member ] [c] [line 5, size 32, align 32, offset 64] [from int]
-!14 = !{!"0xd\00d\006\0032\0032\0096\000", !1, !9, !8} ; [ DW_TAG_member ] [d] [line 6, size 32, align 32, offset 96] [from int]
-!15 = !{!"0xd\00e\007\0032\0032\00128\000", !1, !9, !8} ; [ DW_TAG_member ] [e] [line 7, size 32, align 32, offset 128] [from int]
+!11 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 3, size: 32, align: 32, file: !1, scope: !9, baseType: !8)
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 4, size: 32, align: 32, offset: 32, file: !1, scope: !9, baseType: !8)
+!13 = !DIDerivedType(tag: DW_TAG_member, name: "c", line: 5, size: 32, align: 32, offset: 64, file: !1, scope: !9, baseType: !8)
+!14 = !DIDerivedType(tag: DW_TAG_member, name: "d", line: 6, size: 32, align: 32, offset: 96, file: !1, scope: !9, baseType: !8)
+!15 = !DIDerivedType(tag: DW_TAG_member, name: "e", line: 7, size: 32, align: 32, offset: 128, file: !1, scope: !9, baseType: !8)
 !16 = !{i32 2, !"Dwarf Version", i32 2}
-!17 = !{!"0x101\00f\0016777229\008192", !4, !5, !9} ; [ DW_TAG_arg_variable ] [f] [line 13]
-!18 = !MDLocation(line: 13, scope: !4)
-!19 = !MDLocation(line: 16, scope: !4)
-!20 = !{i32 1, !"Debug Info Version", i32 2}
+!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "f", line: 13, arg: 1, scope: !4, file: !5, type: !9)
+!18 = !DILocation(line: 13, scope: !4)
+!19 = !DILocation(line: 16, scope: !4)
+!20 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/ARM/PR16736.ll b/test/DebugInfo/ARM/PR16736.ll
index 7c99ae20dc64..9d4992210a24 100644
--- a/test/DebugInfo/ARM/PR16736.ll
+++ b/test/DebugInfo/ARM/PR16736.ll
@@ -15,14 +15,14 @@ target triple = "thumbv7-apple-ios"
 ; Function Attrs: nounwind
 define arm_aapcscc void @_Z1hiiiif(i32, i32, i32, i32, float %x) #0 {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 %0, i64 0, metadata !12, metadata !{!"0x102"}), !dbg !18
-  tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !18
-  tail call void @llvm.dbg.value(metadata i32 %2, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !18
-  tail call void @llvm.dbg.value(metadata i32 %3, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !18
-  tail call void @llvm.dbg.value(metadata float %x, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !18
+  tail call void @llvm.dbg.value(metadata i32 %0, i64 0, metadata !12, metadata !DIExpression()), !dbg !18
+  tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !13, metadata !DIExpression()), !dbg !18
+  tail call void @llvm.dbg.value(metadata i32 %2, i64 0, metadata !14, metadata !DIExpression()), !dbg !18
+  tail call void @llvm.dbg.value(metadata i32 %3, i64 0, metadata !15, metadata !DIExpression()), !dbg !18
+  tail call void @llvm.dbg.value(metadata float %x, i64 0, metadata !16, metadata !DIExpression()), !dbg !18
   %call = tail call arm_aapcscc i32 @_Z1fv() #3, !dbg !19
   %conv = sitofp i32 %call to float, !dbg !19
-  tail call void @llvm.dbg.value(metadata float %conv, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !19
+  tail call void @llvm.dbg.value(metadata float %conv, i64 0, metadata !16, metadata !DIExpression()), !dbg !19
   tail call arm_aapcscc void @_Z1gf(float %conv) #3, !dbg !19
   ret void, !dbg !20
 }
@@ -41,25 +41,25 @@ attributes #3 = { nounwind }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!17, !21}
 
-!0 = !{!"0x11\004\00clang version 3.4 (trunk 190804) (llvm/trunk 190797)\001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [//<unknown>] [DW_LANG_C_plus_plus]
-!1 = !{!"/<unknown>", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 (trunk 190804) (llvm/trunk 190797)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "/<unknown>", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00h\00h\00_Z1hiiiif\003\000\001\000\006\00256\001\003", !5, !6, !7, null, void (i32, i32, i32, i32, float)* @_Z1hiiiif, null, null, !11} ; [ DW_TAG_subprogram ] [line 3] [def] [h]
-!5 = !{!"/arm.cpp", !""}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [//arm.cpp]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "h", linkageName: "_Z1hiiiif", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !5, scope: !6, type: !7, function: void (i32, i32, i32, i32, float)* @_Z1hiiiif, variables: !11)
+!5 = !DIFile(filename: "/arm.cpp", directory: "")
+!6 = !DIFile(filename: "/arm.cpp", directory: "")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9, !9, !9, !9, !10}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"0x24\00float\000\0032\0032\000\000\004", null, null} ; [ DW_TAG_base_type ] [float] [line 0, size 32, align 32, offset 0, enc DW_ATE_float]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float)
 !11 = !{!12, !13, !14, !15, !16}
-!12 = !{!"0x101\00\0016777219\000", !4, !6, !9} ; [ DW_TAG_arg_variable ] [line 3]
-!13 = !{!"0x101\00\0033554435\000", !4, !6, !9} ; [ DW_TAG_arg_variable ] [line 3]
-!14 = !{!"0x101\00\0050331651\000", !4, !6, !9} ; [ DW_TAG_arg_variable ] [line 3]
-!15 = !{!"0x101\00\0067108867\000", !4, !6, !9} ; [ DW_TAG_arg_variable ] [line 3]
-!16 = !{!"0x101\00x\0083886083\000", !4, !6, !10} ; [ DW_TAG_arg_variable ] [x] [line 3]
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "", line: 3, arg: 1, scope: !4, file: !6, type: !9)
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "", line: 3, arg: 2, scope: !4, file: !6, type: !9)
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "", line: 3, arg: 3, scope: !4, file: !6, type: !9)
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "", line: 3, arg: 4, scope: !4, file: !6, type: !9)
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 3, arg: 5, scope: !4, file: !6, type: !10)
 !17 = !{i32 2, !"Dwarf Version", i32 4}
-!18 = !MDLocation(line: 3, scope: !4)
-!19 = !MDLocation(line: 4, scope: !4)
-!20 = !MDLocation(line: 5, scope: !4)
-!21 = !{i32 1, !"Debug Info Version", i32 2}
+!18 = !DILocation(line: 3, scope: !4)
+!19 = !DILocation(line: 4, scope: !4)
+!20 = !DILocation(line: 5, scope: !4)
+!21 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/ARM/cfi-eof-prologue.ll b/test/DebugInfo/ARM/cfi-eof-prologue.ll
index 599806bf7073..07e4d8a717b6 100644
--- a/test/DebugInfo/ARM/cfi-eof-prologue.ll
+++ b/test/DebugInfo/ARM/cfi-eof-prologue.ll
@@ -30,10 +30,10 @@ target triple = "thumbv7-apple-ios"
 define %struct.B* @_ZN1BC2Ev(%struct.B* %this) unnamed_addr #0 align 2 {
 entry:
   tail call void @llvm.dbg.value(metadata %struct.B* %this, i64 0, metadata !30, metadata !40), !dbg !41
-  %0 = getelementptr inbounds %struct.B* %this, i32 0, i32 0, !dbg !42
+  %0 = getelementptr inbounds %struct.B, %struct.B* %this, i32 0, i32 0, !dbg !42
   %call = tail call %struct.A* @_ZN1AC2Ev(%struct.A* %0) #3, !dbg !42
-  %1 = getelementptr inbounds %struct.B* %this, i32 0, i32 0, i32 0, !dbg !42
-  store i32 (...)** bitcast (i8** getelementptr inbounds ([4 x i8*]* @_ZTV1B, i32 0, i32 2) to i32 (...)**), i32 (...)*** %1, align 4, !dbg !42, !tbaa !43
+  %1 = getelementptr inbounds %struct.B, %struct.B* %this, i32 0, i32 0, i32 0, !dbg !42
+  store i32 (...)** bitcast (i8** getelementptr inbounds ([4 x i8*], [4 x i8*]* @_ZTV1B, i32 0, i32 2) to i32 (...)**), i32 (...)*** %1, align 4, !dbg !42, !tbaa !43
   ret %struct.B* %this, !dbg !42
 }
 
@@ -44,10 +44,10 @@ define %struct.B* @_ZN1BC1Ev(%struct.B* %this) unnamed_addr #0 align 2 {
 entry:
   tail call void @llvm.dbg.value(metadata %struct.B* %this, i64 0, metadata !34, metadata !40), !dbg !46
   tail call void @llvm.dbg.value(metadata %struct.B* %this, i64 0, metadata !47, metadata !40) #3, !dbg !49
-  %0 = getelementptr inbounds %struct.B* %this, i32 0, i32 0, !dbg !50
+  %0 = getelementptr inbounds %struct.B, %struct.B* %this, i32 0, i32 0, !dbg !50
   %call.i = tail call %struct.A* @_ZN1AC2Ev(%struct.A* %0) #3, !dbg !50
-  %1 = getelementptr inbounds %struct.B* %this, i32 0, i32 0, i32 0, !dbg !50
-  store i32 (...)** bitcast (i8** getelementptr inbounds ([4 x i8*]* @_ZTV1B, i32 0, i32 2) to i32 (...)**), i32 (...)*** %1, align 4, !dbg !50, !tbaa !43
+  %1 = getelementptr inbounds %struct.B, %struct.B* %this, i32 0, i32 0, i32 0, !dbg !50
+  store i32 (...)** bitcast (i8** getelementptr inbounds ([4 x i8*], [4 x i8*]* @_ZTV1B, i32 0, i32 2) to i32 (...)**), i32 (...)*** %1, align 4, !dbg !50, !tbaa !43
   ret %struct.B* %this, !dbg !48
 }
 
@@ -62,54 +62,54 @@ attributes #3 = { nounwind }
 !llvm.module.flags = !{!35, !36, !37, !38}
 !llvm.ident = !{!39}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 (trunk 224279) (llvm/trunk 224283)\001\00\000\00\001", !1, !2, !3, !27, !2, !2} ; [ DW_TAG_compile_unit ] [<stdin>] [DW_LANG_C_plus_plus]
-!1 = !{!"<stdin>", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 (trunk 224279) (llvm/trunk 224283)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !27, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<stdin>", directory: "")
 !2 = !{}
 !3 = !{!4, !13}
-!4 = !{!"0x13\00B\005\0032\0032\000\000\000", !5, null, null, !6, !"_ZTS1A", null, !"_ZTS1B"} ; [ DW_TAG_structure_type ] [B] [line 5, size 32, align 32, offset 0] [def] [from ]
-!5 = !{!"test1.cpp", !""}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "B", line: 5, size: 32, align: 32, file: !5, elements: !6, vtableHolder: !"_ZTS1A", identifier: "_ZTS1B")
+!5 = !DIFile(filename: "test1.cpp", directory: "")
 !6 = !{!7, !8, !12}
-!7 = !{!"0x1c\00\000\000\000\000\000", null, !"_ZTS1B", !"_ZTS1A"} ; [ DW_TAG_inheritance ] [line 0, size 0, align 0, offset 0] [from _ZTS1A]
-!8 = !{!"0x2e\00B\00B\00\006\000\000\000\000\00256\001\006", !5, !"_ZTS1B", !9, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 6] [B]
-!9 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = !DIDerivedType(tag: DW_TAG_inheritance, scope: !"_ZTS1B", baseType: !"_ZTS1A")
+!8 = !DISubprogram(name: "B", line: 6, isLocal: false, isDefinition: false, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 6, file: !5, scope: !"_ZTS1B", type: !9)
+!9 = !DISubroutineType(types: !10)
 !10 = !{null, !11}
-!11 = !{!"0xf\00\000\0032\0032\000\001088\00", null, null, !"_ZTS1B"} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [artificial] [from _ZTS1B]
-!12 = !{!"0x2e\00~B\00~B\00\007\000\000\001\000\00256\001\007", !5, !"_ZTS1B", !9, !"_ZTS1B", null, null, null, null} ; [ DW_TAG_subprogram ] [line 7] [~B]
-!13 = !{!"0x13\00A\001\0032\0032\000\000\000", !5, null, null, !14, !"_ZTS1A", null, !"_ZTS1A"} ; [ DW_TAG_structure_type ] [A] [line 1, size 32, align 32, offset 0] [def] [from ]
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1B")
+!12 = !DISubprogram(name: "~B", line: 7, isLocal: false, isDefinition: false, virtuality: DW_VIRTUALITY_virtual, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 7, file: !5, scope: !"_ZTS1B", type: !9, containingType: !"_ZTS1B")
+!13 = !DICompositeType(tag: DW_TAG_structure_type, name: "A", line: 1, size: 32, align: 32, file: !5, elements: !14, vtableHolder: !"_ZTS1A", identifier: "_ZTS1A")
 !14 = !{!15, !22, !26}
-!15 = !{!"0xd\00_vptr$A\000\0032\000\000\0064", !5, !16, !17} ; [ DW_TAG_member ] [_vptr$A] [line 0, size 32, align 0, offset 0] [artificial] [from ]
-!16 = !{!"0x29", !5}                              ; [ DW_TAG_file_type ] [test1.cpp]
-!17 = !{!"0xf\00\000\0032\000\000\000", null, null, !18} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 0, offset 0] [from __vtbl_ptr_type]
-!18 = !{!"0xf\00__vtbl_ptr_type\000\0032\000\000\000", null, null, !19} ; [ DW_TAG_pointer_type ] [__vtbl_ptr_type] [line 0, size 32, align 0, offset 0] [from ]
-!19 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !20, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!15 = !DIDerivedType(tag: DW_TAG_member, name: "_vptr$A", size: 32, flags: DIFlagArtificial, file: !5, scope: !16, baseType: !17)
+!16 = !DIFile(filename: "test1.cpp", directory: "")
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, baseType: !18)
+!18 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "__vtbl_ptr_type", size: 32, baseType: !19)
+!19 = !DISubroutineType(types: !20)
 !20 = !{!21}
-!21 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!22 = !{!"0x2e\00A\00A\00\002\000\000\000\000\00256\001\002", !5, !"_ZTS1A", !23, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 2] [A]
-!23 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !24, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!21 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!22 = !DISubprogram(name: "A", line: 2, isLocal: false, isDefinition: false, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2, file: !5, scope: !"_ZTS1A", type: !23)
+!23 = !DISubroutineType(types: !24)
 !24 = !{null, !25}
-!25 = !{!"0xf\00\000\0032\0032\000\001088\00", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [artificial] [from _ZTS1A]
-!26 = !{!"0x2e\00~A\00~A\00\003\000\000\001\000\00256\001\003", !5, !"_ZTS1A", !23, !"_ZTS1A", null, null, null, null} ; [ DW_TAG_subprogram ] [line 3] [~A]
+!25 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1A")
+!26 = !DISubprogram(name: "~A", line: 3, isLocal: false, isDefinition: false, virtuality: DW_VIRTUALITY_virtual, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !5, scope: !"_ZTS1A", type: !23, containingType: !"_ZTS1A")
 !27 = !{!28, !32}
-!28 = !{!"0x2e\00B\00B\00_ZN1BC2Ev\009\000\001\000\000\00256\001\009", !5, !"_ZTS1B", !9, null, %struct.B* (%struct.B*)* @_ZN1BC2Ev, null, !8, !29} ; [ DW_TAG_subprogram ] [line 9] [def] [B]
+!28 = !DISubprogram(name: "B", linkageName: "_ZN1BC2Ev", line: 9, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 9, file: !5, scope: !"_ZTS1B", type: !9, function: %struct.B* (%struct.B*)* @_ZN1BC2Ev, declaration: !8, variables: !29)
 !29 = !{!30}
-!30 = !{!"0x101\00this\0016777216\001088", !28, null, !31} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!31 = !{!"0xf\00\000\0032\0032\000\000", null, null, !"_ZTS1B"} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from _ZTS1B]
-!32 = !{!"0x2e\00B\00B\00_ZN1BC1Ev\009\000\001\000\000\00256\001\009", !5, !"_ZTS1B", !9, null, %struct.B* (%struct.B*)* @_ZN1BC1Ev, null, !8, !33} ; [ DW_TAG_subprogram ] [line 9] [def] [B]
+!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !28, type: !31)
+!31 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !"_ZTS1B")
+!32 = !DISubprogram(name: "B", linkageName: "_ZN1BC1Ev", line: 9, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 9, file: !5, scope: !"_ZTS1B", type: !9, function: %struct.B* (%struct.B*)* @_ZN1BC1Ev, declaration: !8, variables: !33)
 !33 = !{!34}
-!34 = !{!"0x101\00this\0016777216\001088", !32, null, !31} ; [ DW_TAG_arg_variable ] [this] [line 0]
+!34 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !32, type: !31)
 !35 = !{i32 2, !"Dwarf Version", i32 4}
-!36 = !{i32 2, !"Debug Info Version", i32 2}
+!36 = !{i32 2, !"Debug Info Version", i32 3}
 !37 = !{i32 1, !"wchar_size", i32 4}
 !38 = !{i32 1, !"min_enum_size", i32 4}
 !39 = !{!"clang version 3.6.0 (trunk 224279) (llvm/trunk 224283)"}
-!40 = !{!"0x102"}                                 ; [ DW_TAG_expression ]
-!41 = !MDLocation(line: 0, scope: !28)
-!42 = !MDLocation(line: 9, scope: !28)
+!40 = !DIExpression()
+!41 = !DILocation(line: 0, scope: !28)
+!42 = !DILocation(line: 9, scope: !28)
 !43 = !{!44, !44, i64 0}
 !44 = !{!"vtable pointer", !45, i64 0}
 !45 = !{!"Simple C/C++ TBAA"}
-!46 = !MDLocation(line: 0, scope: !32)
-!47 = !{!"0x101\00this\0016777216\001088", !28, null, !31, !48} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!48 = !MDLocation(line: 9, scope: !32)
-!49 = !MDLocation(line: 0, scope: !28, inlinedAt: !48)
-!50 = !MDLocation(line: 9, scope: !28, inlinedAt: !48)
+!46 = !DILocation(line: 0, scope: !32)
+!47 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !28, type: !31)
+!48 = !DILocation(line: 9, scope: !32)
+!49 = !DILocation(line: 0, scope: !28, inlinedAt: !48)
+!50 = !DILocation(line: 9, scope: !28, inlinedAt: !48)
diff --git a/test/DebugInfo/ARM/constant-dbgloc.ll b/test/DebugInfo/ARM/constant-dbgloc.ll
new file mode 100644
index 000000000000..c4a5703f3e8b
--- /dev/null
+++ b/test/DebugInfo/ARM/constant-dbgloc.ll
@@ -0,0 +1,37 @@
+; RUN: llc -filetype=asm %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv7--linux-gnueabihf"
+
+; int
+; main(void)
+; {
+;     return -1;
+; }
+
+; CHECK: test.c:4:5
+; CHECK: mvn
+
+; Function Attrs: nounwind
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  ret i32 -1, !dbg !11
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!8, !9}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, subprograms: !3)
+!1 = !DIFile(filename: "test.c", directory: "/home/user/clang/build")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "main", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: false, function: i32 ()* @main, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{!7}
+!7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !{i32 2, !"Dwarf Version", i32 4}
+!9 = !{i32 2, !"Debug Info Version", i32 3}
+!10 = !{i32 1, !"wchar_size", i32 4}
+!11 = !DILocation(line: 4, column: 5, scope: !4)
diff --git a/test/DebugInfo/ARM/header.ll b/test/DebugInfo/ARM/header.ll
new file mode 100644
index 000000000000..6723f093a59b
--- /dev/null
+++ b/test/DebugInfo/ARM/header.ll
@@ -0,0 +1,30 @@
+; RUN: llc -mtriple armv7-apple-darwin < %s  | FileCheck %s
+
+; Test that we don't pollute the start of the file with debug sections.
+; This is particularly important on ARM MachO as a change in section order can
+; cause a change the relaxation of the instructions used.
+
+; CHECK:      .section        __TEXT,__text,regular,pure_instructions
+; CHECK-NEXT: .syntax unified
+; CHECK-NEXT: .globl  _f
+; CHECK-NEXT: .align  2
+; CHECK-NEXT: _f:                    @ @f
+
+; CHECK:  .section        __DWARF,__debug_str,regular,debug
+
+define void @f() {
+  ret void, !dbg !9
+}
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7, !8}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "foo", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "/foo/test.c", directory: "/foo")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "f", scope: !1, file: !1, line: 1, type: !5, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: true, function: void ()* @f, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{null}
+!7 = !{i32 2, !"Dwarf Version", i32 4}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
+!9 = !DILocation(line: 1, column: 15, scope: !4)
diff --git a/test/DebugInfo/ARM/line.test b/test/DebugInfo/ARM/line.test
new file mode 100644
index 000000000000..47feb4697ce5
--- /dev/null
+++ b/test/DebugInfo/ARM/line.test
@@ -0,0 +1,7 @@
+; RUN: llc -mtriple=arm-none-linux -O0 -filetype=asm < %S/../Inputs/line.ll | FileCheck %S/../Inputs/line.ll
+
+; This is more complex than it looked. It's mixed up somewhere in SelectionDAG
+; (legalized as br_cc, losing the separation between the comparison and the
+; branch, then further lowered to CMPri + brcc but without the fidelity that
+; those two instructions are on separate lines)
+; XFAIL: *
diff --git a/test/DebugInfo/ARM/lowerbdgdeclare_vla.ll b/test/DebugInfo/ARM/lowerbdgdeclare_vla.ll
index 2e137678e0e6..daf26507a036 100644
--- a/test/DebugInfo/ARM/lowerbdgdeclare_vla.ll
+++ b/test/DebugInfo/ARM/lowerbdgdeclare_vla.ll
@@ -19,35 +19,35 @@ target triple = "thumbv7-apple-ios8.0.0"
 ; Function Attrs: nounwind optsize readnone
 define void @run(float %r) #0 {
 entry:
-  tail call void @llvm.dbg.declare(metadata float %r, metadata !11, metadata !{!"0x102"}), !dbg !22
+  tail call void @llvm.dbg.declare(metadata float %r, metadata !11, metadata !DIExpression()), !dbg !22
   %conv = fptosi float %r to i32, !dbg !23
-  tail call void @llvm.dbg.declare(metadata i32 %conv, metadata !12, metadata !{!"0x102"}), !dbg !23
+  tail call void @llvm.dbg.declare(metadata i32 %conv, metadata !12, metadata !DIExpression()), !dbg !23
   %vla = alloca float, i32 %conv, align 4, !dbg !24
-  tail call void @llvm.dbg.declare(metadata float* %vla, metadata !14, metadata !{!"0x102"}), !dbg !24
+  tail call void @llvm.dbg.declare(metadata float* %vla, metadata !14, metadata !DIExpression(DW_OP_deref)), !dbg !24
 ; The VLA alloca should be described by a dbg.declare:
 ; CHECK: call void @llvm.dbg.declare(metadata float* %vla, metadata ![[VLA:.*]], metadata {{.*}})
 ; The VLA alloca and following store into the array should not be lowered to like this:
 ; CHECK-NOT:  call void @llvm.dbg.value(metadata float %r, i64 0, metadata ![[VLA]])
 ; the backend interprets this as "vla has the location of %r".
   store float %r, float* %vla, align 4, !dbg !25, !tbaa !26
-  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !30
+  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !18, metadata !DIExpression()), !dbg !30
   %cmp8 = icmp sgt i32 %conv, 0, !dbg !30
   br i1 %cmp8, label %for.body, label %for.end, !dbg !30
 
 for.body:                                         ; preds = %entry, %for.body.for.body_crit_edge
   %0 = phi float [ %.pre, %for.body.for.body_crit_edge ], [ %r, %entry ]
   %i.09 = phi i32 [ %inc, %for.body.for.body_crit_edge ], [ 0, %entry ]
-  %arrayidx2 = getelementptr inbounds float* %vla, i32 %i.09, !dbg !31
+  %arrayidx2 = getelementptr inbounds float, float* %vla, i32 %i.09, !dbg !31
   %div = fdiv float %0, %r, !dbg !31
   store float %div, float* %arrayidx2, align 4, !dbg !31, !tbaa !26
   %inc = add nsw i32 %i.09, 1, !dbg !30
-  tail call void @llvm.dbg.value(metadata i32 %inc, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !30
+  tail call void @llvm.dbg.value(metadata i32 %inc, i64 0, metadata !18, metadata !DIExpression()), !dbg !30
   %exitcond = icmp eq i32 %inc, %conv, !dbg !30
   br i1 %exitcond, label %for.end, label %for.body.for.body_crit_edge, !dbg !30
 
 for.body.for.body_crit_edge:                      ; preds = %for.body
-  %arrayidx2.phi.trans.insert = getelementptr inbounds float* %vla, i32 %inc
-  %.pre = load float* %arrayidx2.phi.trans.insert, align 4, !dbg !31, !tbaa !26
+  %arrayidx2.phi.trans.insert = getelementptr inbounds float, float* %vla, i32 %inc
+  %.pre = load float, float* %arrayidx2.phi.trans.insert, align 4, !dbg !31, !tbaa !26
   br label %for.body, !dbg !30
 
 for.end:                                          ; preds = %for.body, %entry
@@ -67,37 +67,37 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!20, !33}
 !llvm.ident = !{!21}
 
-!0 = !{!"0x11\0012\00clang version 3.4 \001\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/Volumes/Data/radar/15464571/<unknown>] [DW_LANG_C99]
-!1 = !{!"<unknown>", !"/Volumes/Data/radar/15464571"}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 ", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<unknown>", directory: "/Volumes/Data/radar/15464571")
+!2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00run\00run\00\001\000\001\000\006\00256\001\002", !5, !6, !7, null, void (float)* @run, null, null, !10} ; [ DW_TAG_subprogram ] [line 1] [def] [scope 2] [run]
-!5 = !{!"test.c", !"/Volumes/Data/radar/15464571"}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [/Volumes/Data/radar/15464571/test.c]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "run", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2, file: !5, scope: !6, type: !7, function: void (float)* @run, variables: !10)
+!5 = !DIFile(filename: "test.c", directory: "/Volumes/Data/radar/15464571")
+!6 = !DIFile(filename: "test.c", directory: "/Volumes/Data/radar/15464571")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9}
-!9 = !{!"0x24\00float\000\0032\0032\000\000\004", null, null} ; [ DW_TAG_base_type ] [float] [line 0, size 32, align 32, offset 0, enc DW_ATE_float]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float)
 !10 = !{!11, !12, !14, !18}
-!11 = !{!"0x101\00r\0016777217\000", !4, !6, !9} ; [ DW_TAG_arg_variable ] [r] [line 1]
-!12 = !{!"0x100\00count\003\000", !4, !6, !13} ; [ DW_TAG_auto_variable ] [count] [line 3]
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!14 = !{!"0x100\00vla\004\008192", !4, !6, !15} ; [ DW_TAG_auto_variable ] [vla] [line 4]
-!15 = !{!"0x1\00\000\000\0032\000\000", null, null, !9, !16, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 0, align 32, offset 0] [from float]
+!11 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "r", line: 1, arg: 1, scope: !4, file: !6, type: !9)
+!12 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "count", line: 3, scope: !4, file: !6, type: !13)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vla", line: 4, scope: !4, file: !6, type: !15)
+!15 = !DICompositeType(tag: DW_TAG_array_type, align: 32, baseType: !9, elements: !16)
 !16 = !{!17}
-!17 = !{!"0x21\000\00-1"}       ; [ DW_TAG_subrange_type ] [unbounded]
-!18 = !{!"0x100\00i\006\000", !19, !6, !13} ; [ DW_TAG_auto_variable ] [i] [line 6]
-!19 = !{!"0xb\006\000\000", !5, !4} ; [ DW_TAG_lexical_block ] [/Volumes/Data/radar/15464571/test.c]
+!17 = !DISubrange(count: -1)
+!18 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 6, scope: !19, file: !6, type: !13)
+!19 = distinct !DILexicalBlock(line: 6, column: 0, file: !5, scope: !4)
 !20 = !{i32 2, !"Dwarf Version", i32 2}
 !21 = !{!"clang version 3.4 "}
-!22 = !MDLocation(line: 1, scope: !4)
-!23 = !MDLocation(line: 3, scope: !4)
-!24 = !MDLocation(line: 4, scope: !4)
-!25 = !MDLocation(line: 5, scope: !4)
+!22 = !DILocation(line: 1, scope: !4)
+!23 = !DILocation(line: 3, scope: !4)
+!24 = !DILocation(line: 4, scope: !4)
+!25 = !DILocation(line: 5, scope: !4)
 !26 = !{!27, !27, i64 0}
 !27 = !{!"float", !28, i64 0}
 !28 = !{!"omnipotent char", !29, i64 0}
 !29 = !{!"Simple C/C++ TBAA"}
-!30 = !MDLocation(line: 6, scope: !19)
-!31 = !MDLocation(line: 7, scope: !19)
-!32 = !MDLocation(line: 8, scope: !4)
-!33 = !{i32 1, !"Debug Info Version", i32 2}
+!30 = !DILocation(line: 6, scope: !19)
+!31 = !DILocation(line: 7, scope: !19)
+!32 = !DILocation(line: 8, scope: !4)
+!33 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/ARM/multiple-constant-uses-drops-dbgloc.ll b/test/DebugInfo/ARM/multiple-constant-uses-drops-dbgloc.ll
new file mode 100644
index 000000000000..e68c5b824163
--- /dev/null
+++ b/test/DebugInfo/ARM/multiple-constant-uses-drops-dbgloc.ll
@@ -0,0 +1,54 @@
+; RUN: llc -filetype=asm -asm-verbose=0 < %s | FileCheck %s
+
+; char ch;
+; int b;
+;
+; void proc (void)
+; {
+;     ch = 'A';
+;     b = 0; // <== this should have correct location
+; }
+
+; CHECK: .loc 1 7 7
+; CHECK: mov  r{{[0-9]}}, #0
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv7--linux-gnueabihf"
+
+@ch = common global i8 0, align 1
+@b = common global i32 0, align 4
+
+; Function Attrs: nounwind
+define void @proc() #0 {
+entry:
+  store i8 65, i8* @ch, align 1, !dbg !17
+  store i32 0, i32* @b, align 4, !dbg !18
+  ret void, !dbg !19
+}
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a8" "target-features"="+neon,+vfp3" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!12, !13, !14, !15}
+!llvm.ident = !{!16}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, subprograms: !3)
+!1 = !DIFile(filename: "test.c", directory: "/home/user/clang/build")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "proc", scope: !1, file: !1, line: 4, type: !5, isLocal: false, isDefinition: true, scopeLine: 5, flags: DIFlagPrototyped, isOptimized: false, function: void ()* @proc, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{null}
+!7 = !{!8, !10}
+!8 = !DIGlobalVariable(name: "ch", scope: !0, file: !1, line: 1, type: !9, isLocal: false, isDefinition: true, variable: i8* @ch)
+!9 = !DIBasicType(name: "char", size: 8, align: 8, encoding: DW_ATE_unsigned_char)
+!10 = !DIGlobalVariable(name: "b", scope: !0, file: !1, line: 2, type: !11, isLocal: false, isDefinition: true, variable: i32* @b)
+!11 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!12 = !{i32 2, !"Dwarf Version", i32 4}
+!13 = !{i32 2, !"Debug Info Version", i32 3}
+!14 = !{i32 1, !"wchar_size", i32 4}
+!15 = !{i32 1, !"min_enum_size", i32 4}
+!16 = !{!"clang version 3.7.0 (http://llvm.org/git/clang.git 9b0abb9df531ef7928c8182120e1869affca17d5) (http://llvm.org/git/llvm.git b1e759524dd94f7ce1e24935daed8383927e96c1)"}
+!17 = !DILocation(line: 6, column: 8, scope: !4)
+!18 = !DILocation(line: 7, column: 7, scope: !4)
+!19 = !DILocation(line: 8, column: 1, scope: !4)
diff --git a/test/DebugInfo/ARM/s-super-register.ll b/test/DebugInfo/ARM/s-super-register.ll
index 62a315e508a1..def87695ccce 100644
--- a/test/DebugInfo/ARM/s-super-register.ll
+++ b/test/DebugInfo/ARM/s-super-register.ll
@@ -12,7 +12,7 @@ target triple = "thumbv7-apple-macosx10.6.7"
 define void @_Z3foov() optsize ssp {
 entry:
   %call = tail call float @_Z3barv() optsize, !dbg !11
-  tail call void @llvm.dbg.value(metadata float %call, i64 0, metadata !5, metadata !{!"0x102"}), !dbg !11
+  tail call void @llvm.dbg.value(metadata float %call, i64 0, metadata !5, metadata !DIExpression()), !dbg !11
   %call16 = tail call float @_Z2f2v() optsize, !dbg !12
   %cmp7 = fcmp olt float %call, %call16, !dbg !12
   br i1 %cmp7, label %for.body, label %for.end, !dbg !12
@@ -40,24 +40,24 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!20}
 
-!0 = !{!"0x11\004\00clang version 3.0 (trunk 130845)\001\00\000\00\001", !18, !19, !19, !16, null,  null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"0x2e\00foo\00foo\00_Z3foov\005\000\001\000\006\00256\001\005", !18, !2, !3, null, void ()* @_Z3foov, null, null, !17} ; [ DW_TAG_subprogram ] [line 5] [def] [foo]
-!2 = !{!"0x29", !18} ; [ DW_TAG_file_type ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !18, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.0 (trunk 130845)", isOptimized: true, emissionKind: 1, file: !18, enums: !19, retainedTypes: !19, subprograms: !16, imports:  null)
+!1 = !DISubprogram(name: "foo", linkageName: "_Z3foov", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !18, scope: !2, type: !3, function: void ()* @_Z3foov, variables: !17)
+!2 = !DIFile(filename: "k.cc", directory: "/private/tmp")
+!3 = !DISubroutineType(types: !4)
 !4 = !{null}
-!5 = !{!"0x100\00k\006\000", !6, !2, !7} ; [ DW_TAG_auto_variable ]
-!6 = !{!"0xb\005\0012\000", !18, !1} ; [ DW_TAG_lexical_block ]
-!7 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !0} ; [ DW_TAG_base_type ]
-!8 = !{!"0x100\00y\008\000", !9, !2, !7} ; [ DW_TAG_auto_variable ]
-!9 = !{!"0xb\007\0025\002", !18, !10} ; [ DW_TAG_lexical_block ]
-!10 = !{!"0xb\007\003\001", !18, !6} ; [ DW_TAG_lexical_block ]
-!11 = !MDLocation(line: 6, column: 18, scope: !6)
-!12 = !MDLocation(line: 7, column: 3, scope: !6)
-!13 = !MDLocation(line: 8, column: 20, scope: !9)
-!14 = !MDLocation(line: 7, column: 20, scope: !10)
-!15 = !MDLocation(line: 10, column: 1, scope: !6)
+!5 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 6, scope: !6, file: !2, type: !7)
+!6 = distinct !DILexicalBlock(line: 5, column: 12, file: !18, scope: !1)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float)
+!8 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y", line: 8, scope: !9, file: !2, type: !7)
+!9 = distinct !DILexicalBlock(line: 7, column: 25, file: !18, scope: !10)
+!10 = distinct !DILexicalBlock(line: 7, column: 3, file: !18, scope: !6)
+!11 = !DILocation(line: 6, column: 18, scope: !6)
+!12 = !DILocation(line: 7, column: 3, scope: !6)
+!13 = !DILocation(line: 8, column: 20, scope: !9)
+!14 = !DILocation(line: 7, column: 20, scope: !10)
+!15 = !DILocation(line: 10, column: 1, scope: !6)
 !16 = !{!1}
 !17 = !{!5, !8}
-!18 = !{!"k.cc", !"/private/tmp"}
-!19 = !{i32 0}
-!20 = !{i32 1, !"Debug Info Version", i32 2}
+!18 = !DIFile(filename: "k.cc", directory: "/private/tmp")
+!19 = !{}
+!20 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/ARM/sectionorder.ll b/test/DebugInfo/ARM/sectionorder.ll
deleted file mode 100644
index 41677c7dc05d..000000000000
--- a/test/DebugInfo/ARM/sectionorder.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: llc  -filetype=asm %s -o - | FileCheck %s
-
-; Verifies that the DWARF* sections come _after_ the __TEXT sections.
-; rdar://problem/15623193
-
-; CHECK: .section	__TEXT,__text,
-; CHECK-NOT: __DWARF,__debug
-; CHECK: .section	__TEXT,__cstring,cstring_literals
-target triple = "thumbv7-apple-ios"
-
-!llvm.module.flags = !{!3, !4}
-!llvm.dbg.cu = !{!0}
-
-!0 = !{!"0x11\0012\00LLVM\001\00\00\00\00", !5, !1, !1, !1, !1, null} ; [ DW_TAG_compile_unit ] [/Volumes/Data/radar/15623193/test.c] [DW_LANG_C99]
-!1 = !{}
-!3 = !{i32 2, !"Dwarf Version", i32 2}
-!4 = !{i32 1, !"Debug Info Version", i32 2}
-!5 = !{!"test.c", !"/Volumes/Data/radar/15623193"}
diff --git a/test/DebugInfo/ARM/selectiondag-deadcode.ll b/test/DebugInfo/ARM/selectiondag-deadcode.ll
index 0626d2f1f666..1b6528269f7a 100644
--- a/test/DebugInfo/ARM/selectiondag-deadcode.ll
+++ b/test/DebugInfo/ARM/selectiondag-deadcode.ll
@@ -13,15 +13,15 @@ _ZN7Vector39NormalizeEv.exit:                     ; preds = %1, %0
   ; and SelectionDAGISel crashes.  It should definitely not
   ; crash. Drop the dbg_value instead.
   ; CHECK-NOT: "matrix"
-  tail call void @llvm.dbg.declare(metadata %class.Matrix3.0.6.10* %agg.result, metadata !45, metadata !{!"0x102"})
-  %2 = getelementptr inbounds %class.Matrix3.0.6.10* %agg.result, i32 0, i32 0, i32 8
+  tail call void @llvm.dbg.declare(metadata %class.Matrix3.0.6.10* %agg.result, metadata !45, metadata !DIExpression(DW_OP_deref))
+  %2 = getelementptr inbounds %class.Matrix3.0.6.10, %class.Matrix3.0.6.10* %agg.result, i32 0, i32 0, i32 8
   ret void
 }
 declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
 declare arm_aapcscc void @_ZL4Sqrtd() #2
-!4 = !{!"0x2\00Matrix3\0020\00288\0032\000\000\000", !5, null, null, null, null, null, !"_ZTS7Matrix3"} ; [ DW_TAG_class_type ] [Matrix3] [line 20, size 288, align 32, offset 0] [def] [from ]
-!5 = !{!"test.ii", !"/Volumes/Data/radar/15094721"}
-!39 = !{!"0x2e\00GetMatrix\00GetMatrix\00_Z9GetMatrixv\0032\000\001\000\006\00256\001\0032", !5, !40, !41, null, void (%class.Matrix3.0.6.10*)* @_Z9GetMatrixv, null, null, null} ; [ DW_TAG_subprogram ] [line 32] [def] [GetMatrix]
-!40 = !{!"0x29", !5}         ; [ DW_TAG_file_type ] [/Volumes/Data/radar/15094721/test.ii]
-!41 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, null, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!45 = !{!"0x100\00matrix\0035\008192", !39, !40, !4} ; [ DW_TAG_auto_variable ] [matrix] [line 35]
+!4 = !DICompositeType(tag: DW_TAG_class_type, name: "Matrix3", line: 20, size: 288, align: 32, file: !5, identifier: "_ZTS7Matrix3")
+!5 = !DIFile(filename: "test.ii", directory: "/Volumes/Data/radar/15094721")
+!39 = !DISubprogram(name: "GetMatrix", linkageName: "_Z9GetMatrixv", line: 32, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 32, file: !5, scope: !40, type: !41, function: void (%class.Matrix3.0.6.10*)* @_Z9GetMatrixv)
+!40 = !DIFile(filename: "test.ii", directory: "/Volumes/Data/radar/15094721")
+!41 = !DISubroutineType(types: null)
+!45 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "matrix", line: 35, scope: !39, file: !40, type: !4)
diff --git a/test/DebugInfo/ARM/single-constant-use-preserves-dbgloc.ll b/test/DebugInfo/ARM/single-constant-use-preserves-dbgloc.ll
new file mode 100644
index 000000000000..396eb4fe1946
--- /dev/null
+++ b/test/DebugInfo/ARM/single-constant-use-preserves-dbgloc.ll
@@ -0,0 +1,72 @@
+; RUN: llc -filetype=asm -asm-verbose=0 < %s | FileCheck %s
+
+; int main()
+; {
+;     int x = 0;
+;     if (x > 0)
+;         return x;
+;     x = -1; // <== this line should have correct debug location
+;     return -1;
+; }
+
+; CHECK: .loc 1 6 7
+; CHECK: mvn
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv7--linux-gnueabihf"
+
+; Function Attrs: nounwind
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %x = alloca i32, align 4
+  store i32 0, i32* %retval
+  call void @llvm.dbg.declare(metadata i32* %x, metadata !10, metadata !11), !dbg !12
+  store i32 0, i32* %x, align 4, !dbg !12
+  %0 = load i32, i32* %x, align 4, !dbg !13
+  %cmp = icmp sgt i32 %0, 0, !dbg !15
+  br i1 %cmp, label %if.then, label %if.end, !dbg !16
+
+if.then:                                          ; preds = %entry
+  %1 = load i32, i32* %x, align 4, !dbg !17
+  store i32 %1, i32* %retval, !dbg !18
+  br label %return, !dbg !18
+
+if.end:                                           ; preds = %entry
+  store i32 -1, i32* %x, align 4, !dbg !19
+  store i32 -1, i32* %retval, !dbg !20
+  br label %return, !dbg !20
+
+return:                                           ; preds = %if.end, %if.then
+  %2 = load i32, i32* %retval, !dbg !21
+  ret i32 %2, !dbg !21
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata)
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!8, !9}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, subprograms: !3)
+!1 = !DIFile(filename: "test.c", directory: "/home/user/clang/build")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "main", scope: !1, file: !1, line: 1, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, function: i32 ()* @main, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{!7}
+!7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !{i32 2, !"Dwarf Version", i32 4}
+!9 = !{i32 2, !"Debug Info Version", i32 3}
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", scope: !4, file: !1, line: 3, type: !7)
+!11 = !DIExpression()
+!12 = !DILocation(line: 3, column: 9, scope: !4)
+!13 = !DILocation(line: 4, column: 9, scope: !14)
+!14 = distinct !DILexicalBlock(scope: !4, file: !1, line: 4, column: 9)
+!15 = !DILocation(line: 4, column: 11, scope: !14)
+!16 = !DILocation(line: 4, column: 9, scope: !4)
+!17 = !DILocation(line: 5, column: 13, scope: !14)
+!18 = !DILocation(line: 5, column: 9, scope: !14)
+!19 = !DILocation(line: 6, column: 7, scope: !4)
+!20 = !DILocation(line: 7, column: 5, scope: !4)
+!21 = !DILocation(line: 8, column: 1, scope: !4)
diff --git a/test/DebugInfo/ARM/tls.ll b/test/DebugInfo/ARM/tls.ll
index 39436fe63ca6..e349120b6075 100644
--- a/test/DebugInfo/ARM/tls.ll
+++ b/test/DebugInfo/ARM/tls.ll
@@ -16,13 +16,13 @@
 ; The debug relocation of the address of the tls variable
 ; CHECK: .long x(tlsldo)
 
-!0 = !{!"0x11\0012\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !2, !3, !2} ; [ DW_TAG_compile_unit ] [/tmp/tls.c] [DW_LANG_C99]
-!1 = !{!"tls.c", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3, imports: !2)
+!1 = !DIFile(filename: "tls.c", directory: "/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x34\00x\00x\00\001\000\001", null, !5, !6, i32* @x, null} ; [ DW_TAG_variable ] [x] [line 1] [def]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/tls.c]
-!6 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!4 = !DIGlobalVariable(name: "x", line: 1, isLocal: false, isDefinition: true, scope: null, file: !5, type: !6, variable: i32* @x)
+!5 = !DIFile(filename: "tls.c", directory: "/tmp")
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !7 = !{i32 2, !"Dwarf Version", i32 4}
-!8 = !{i32 1, !"Debug Info Version", i32 2}
+!8 = !{i32 1, !"Debug Info Version", i32 3}
 !9 = !{!"clang version 3.5 "}
diff --git a/test/DebugInfo/COFF/asan-module-ctor.ll b/test/DebugInfo/COFF/asan-module-ctor.ll
index e2c7aef750af..3f8b129ca9b6 100644
--- a/test/DebugInfo/COFF/asan-module-ctor.ll
+++ b/test/DebugInfo/COFF/asan-module-ctor.ll
@@ -9,6 +9,7 @@
 
 ; The module ctor has no debug info.  All we have to do is don't crash.
 ; X86: _asan.module_ctor:
+; X86-NEXT: L{{.*}}:
 ; X86-NEXT: # BB
 ; X86-NEXT: calll   ___asan_init_v3
 ; X86-NEXT: retl
@@ -81,14 +82,14 @@ attributes #0 = { nounwind sanitize_address "less-precise-fpmad"="false" "no-fra
 !llvm.module.flags = !{!7, !8}
 !llvm.ident = !{!9}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 \000\00\000\00\002", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [D:\/asan.c] [DW_LANG_C99]
-!1 = !{!"asan.c", !"D:\5C"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "asan.c", directory: "D:\5C")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, i32 ()* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [D:\/asan.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 ()* @foo, variables: !2)
+!5 = !DIFile(filename: "asan.c", directory: "D:C")
+!6 = !DISubroutineType(types: !2)
 !7 = !{i32 2, !"Dwarf Version", i32 4}
-!8 = !{i32 1, !"Debug Info Version", i32 2}
+!8 = !{i32 1, !"Debug Info Version", i32 3}
 !9 = !{!"clang version 3.5.0 "}
-!10 = !MDLocation(line: 2, scope: !4)
+!10 = !DILocation(line: 2, scope: !4)
diff --git a/test/DebugInfo/COFF/asan-module-without-functions.ll b/test/DebugInfo/COFF/asan-module-without-functions.ll
index 5bd4c9164523..88eec67a4bdb 100644
--- a/test/DebugInfo/COFF/asan-module-without-functions.ll
+++ b/test/DebugInfo/COFF/asan-module-without-functions.ll
@@ -45,9 +45,9 @@ define internal void @asan.module_dtor() {
 !llvm.module.flags = !{!3, !4}
 !llvm.ident = !{!5}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 \000\00\000\00\002", !1, !2, !2, !2, !2, !2} ; [ DW_TAG_compile_unit ] [D:\/asan.c] [DW_LANG_C99]
-!1 = !{!"asan.c", !"D:\5C"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !2, imports: !2)
+!1 = !DIFile(filename: "asan.c", directory: "D:\5C")
 !2 = !{}
 !3 = !{i32 2, !"Dwarf Version", i32 4}
-!4 = !{i32 1, !"Debug Info Version", i32 2}
+!4 = !{i32 1, !"Debug Info Version", i32 3}
 !5 = !{!"clang version 3.5.0 "}
diff --git a/test/DebugInfo/COFF/asm.ll b/test/DebugInfo/COFF/asm.ll
index 4d5cdda5659a..55a50002b8b9 100644
--- a/test/DebugInfo/COFF/asm.ll
+++ b/test/DebugInfo/COFF/asm.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -O0 < %s | FileCheck --check-prefix=X86 %s
-; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -o - -O0 < %s | llvm-mc -triple=i686-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview-linetables | FileCheck --check-prefix=OBJ32 %s
+; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -o - -O0 < %s | llvm-mc -triple=i686-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview -section-symbols | FileCheck --check-prefix=OBJ32 %s
 ; RUN: llc -mcpu=core2 -mtriple=x86_64-pc-win32 -O0 < %s | FileCheck --check-prefix=X64 %s
-; RUN: llc -mcpu=core2 -mtriple=x86_64-pc-win32 -o - -O0 < %s | llvm-mc -triple=x86_64-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview-linetables | FileCheck --check-prefix=OBJ64 %s
+; RUN: llc -mcpu=core2 -mtriple=x86_64-pc-win32 -o - -O0 < %s | llvm-mc -triple=x86_64-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview -section-symbols | FileCheck --check-prefix=OBJ64 %s
 
 ; This LL file was generated by running clang on the following code:
 ; D:\asm.c:
@@ -115,6 +115,7 @@
 ; OBJ32:    }
 
 ; X64-LABEL: f:
+; X64-NEXT: .L{{.*}}:{{$}}
 ; X64-NEXT: [[START:.*]]:{{$}}
 ; X64:      # BB
 ; X64:      subq    $40, %rsp
@@ -239,18 +240,18 @@ attributes #2 = { nounwind }
 !llvm.module.flags = !{!9, !10}
 !llvm.ident = !{!11}
 
-!0 = !{!"0x11\0012\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [D:\/<unknown>] [DW_LANG_C99]
-!1 = !{!"<unknown>", !"D:\5C"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<unknown>", directory: "D:\5C")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00f\00f\00\003\000\001\000\006\00256\000\003", !5, !6, !7, null, void ()* @f, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [f]
-!5 = !{!"asm.c", !"D:\5C"}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [D:\/asm.c]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "f", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !5, scope: !6, type: !7, function: void ()* @f, variables: !2)
+!5 = !DIFile(filename: "asm.c", directory: "D:\5C")
+!6 = !DIFile(filename: "asm.c", directory: "D:C")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null}
 !9 = !{i32 2, !"Dwarf Version", i32 4}
-!10 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !{i32 1, !"Debug Info Version", i32 3}
 !11 = !{!"clang version 3.5 "}
-!12 = !MDLocation(line: 4, scope: !4)
-!13 = !MDLocation(line: 5, scope: !4)
-!14 = !MDLocation(line: 6, scope: !4)
+!12 = !DILocation(line: 4, scope: !4)
+!13 = !DILocation(line: 5, scope: !4)
+!14 = !DILocation(line: 6, scope: !4)
diff --git a/test/DebugInfo/COFF/cpp-mangling.ll b/test/DebugInfo/COFF/cpp-mangling.ll
index 73c8e1594e60..137377847aae 100644
--- a/test/DebugInfo/COFF/cpp-mangling.ll
+++ b/test/DebugInfo/COFF/cpp-mangling.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -o - -O0 < %s | llvm-mc -triple=i686-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview-linetables | FileCheck %s
+; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -o - -O0 < %s | llvm-mc -triple=i686-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview -section-symbols | FileCheck %s
 
 ; This LL file was generated by running clang on the following code:
 ; D:\src.cpp:
@@ -18,7 +18,7 @@ define i32 @"\01?bar@foo@@YAHH@Z"(i32 %x) #0 {
 entry:
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %0 = load i32* %x.addr, align 4, !dbg !11
+  %0 = load i32, i32* %x.addr, align 4, !dbg !11
   %mul = mul nsw i32 %0, 2, !dbg !11
   ret i32 %mul, !dbg !11
 }
@@ -29,15 +29,15 @@ attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"=
 !llvm.module.flags = !{!8, !9}
 !llvm.ident = !{!10}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 \000\00\000\00\002", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [D:\/<stdin>] [DW_LANG_C_plus_plus]
-!1 = !{!"<stdin>", !"D:\5C"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 ", isOptimized: false, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<stdin>", directory: "D:\5C")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00bar\00bar\00\002\000\001\000\000\00256\000\002", !5, !6, !7, null, i32 (i32)* @"\01?bar@foo@@YAHH@Z", null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [bar]
-!5 = !{!"src.cpp", !"D:\5C"}
-!6 = !{!"0x29", !5}    ; [ DW_TAG_file_type ] [D:\/src.cpp]
-!7 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "bar", line: 2, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !5, scope: !6, type: !7, function: i32 (i32)* @"\01?bar@foo@@YAHH@Z", variables: !2)
+!5 = !DIFile(filename: "src.cpp", directory: "D:\5C")
+!6 = !DIFile(filename: "src.cpp", directory: "D:C")
+!7 = !DISubroutineType(types: !2)
 !8 = !{i32 2, !"Dwarf Version", i32 4}
-!9 = !{i32 2, !"Debug Info Version", i32 2}
+!9 = !{i32 2, !"Debug Info Version", i32 3}
 !10 = !{!"clang version 3.6.0 "}
-!11 = !MDLocation(line: 3, scope: !4)
+!11 = !DILocation(line: 3, scope: !4)
diff --git a/test/DebugInfo/COFF/multifile.ll b/test/DebugInfo/COFF/multifile.ll
index 52a62d1c3ca9..0c9782aceec2 100644
--- a/test/DebugInfo/COFF/multifile.ll
+++ b/test/DebugInfo/COFF/multifile.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -O0 < %s | FileCheck --check-prefix=X86 %s
-; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -o - -O0 < %s | llvm-mc -triple=i686-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview-linetables | FileCheck --check-prefix=OBJ32 %s
+; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -o - -O0 < %s | llvm-mc -triple=i686-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview -section-symbols | FileCheck --check-prefix=OBJ32 %s
 ; RUN: llc -mcpu=core2 -mtriple=x86_64-pc-win32 -O0 < %s | FileCheck --check-prefix=X64 %s
-; RUN: llc -mcpu=core2 -mtriple=x86_64-pc-win32 -o - -O0 < %s | llvm-mc -triple=x86_64-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview-linetables | FileCheck --check-prefix=OBJ64 %s
+; RUN: llc -mcpu=core2 -mtriple=x86_64-pc-win32 -o - -O0 < %s | llvm-mc -triple=x86_64-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview -section-symbols | FileCheck --check-prefix=OBJ64 %s
 
 ; This LL file was generated by running clang on the following code:
 ; D:\input.c:
@@ -144,6 +144,7 @@
 ; OBJ32:    }
 
 ; X64-LABEL: f:
+; X64-NEXT: .L{{.*}}:{{$}}
 ; X64-NEXT: [[START:.*]]:{{$}}
 ; X64:      # BB
 ; X64:      subq    $40, %rsp
@@ -307,23 +308,23 @@ attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "
 !llvm.module.flags = !{!9, !10}
 !llvm.ident = !{!11}
 
-!0 = !{!"0x11\0012\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [D:\/<unknown>] [DW_LANG_C99]
-!1 = !{!"<unknown>", !"D:\5C"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<unknown>", directory: "D:\5C")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00f\00f\00\003\000\001\000\006\00256\000\003", !5, !6, !7, null, void ()* @f, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [f]
-!5 = !{!"input.c", !"D:\5C"}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [D:\/input.c]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "f", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !5, scope: !6, type: !7, function: void ()* @f, variables: !2)
+!5 = !DIFile(filename: "input.c", directory: "D:\5C")
+!6 = !DIFile(filename: "input.c", directory: "D:C")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null}
 !9 = !{i32 2, !"Dwarf Version", i32 4}
-!10 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !{i32 1, !"Debug Info Version", i32 3}
 !11 = !{!"clang version 3.5 "}
-!12 = !MDLocation(line: 1, scope: !13)
-!13 = !{!"0xb\000", !14, !4} ; [ DW_TAG_lexical_block ] [D:\/one.c]
-!14 = !{!"one.c", !"D:\5C"}
-!15 = !MDLocation(line: 2, scope: !16)
-!16 = !{!"0xb\000", !17, !4} ; [ DW_TAG_lexical_block ] [D:\/two.c]
-!17 = !{!"two.c", !"D:\5C"}
-!18 = !MDLocation(line: 7, scope: !13)
-!19 = !MDLocation(line: 8, scope: !13)
+!12 = !DILocation(line: 1, scope: !13)
+!13 = !DILexicalBlockFile(discriminator: 0, file: !14, scope: !4)
+!14 = !DIFile(filename: "one.c", directory: "D:\5C")
+!15 = !DILocation(line: 2, scope: !16)
+!16 = !DILexicalBlockFile(discriminator: 0, file: !17, scope: !4)
+!17 = !DIFile(filename: "two.c", directory: "D:\5C")
+!18 = !DILocation(line: 7, scope: !13)
+!19 = !DILocation(line: 8, scope: !13)
diff --git a/test/DebugInfo/COFF/multifunction.ll b/test/DebugInfo/COFF/multifunction.ll
index 01ba617dc1d7..53a8115252d0 100644
--- a/test/DebugInfo/COFF/multifunction.ll
+++ b/test/DebugInfo/COFF/multifunction.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -O0 < %s | FileCheck --check-prefix=X86 %s
-; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -o - -O0 < %s | llvm-mc -triple=i686-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview-linetables | FileCheck --check-prefix=OBJ32 %s
+; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -o - -O0 < %s | llvm-mc -triple=i686-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview -section-symbols | FileCheck --check-prefix=OBJ32 %s
 ; RUN: llc -mcpu=core2 -mtriple=x86_64-pc-win32 -O0 < %s | FileCheck --check-prefix=X64 %s
-; RUN: llc -mcpu=core2 -mtriple=x86_64-pc-win32 -o - -O0 < %s | llvm-mc -triple=x86_64-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview-linetables | FileCheck --check-prefix=OBJ64 %s
+; RUN: llc -mcpu=core2 -mtriple=x86_64-pc-win32 -o - -O0 < %s | llvm-mc -triple=x86_64-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview -section-symbols | FileCheck --check-prefix=OBJ64 %s
 
 ; This LL file was generated by running clang on the following code:
 ; D:\source.c:
@@ -278,6 +278,7 @@
 ; OBJ32:    }
 
 ; X64-LABEL: x:
+; X64-NEXT: .L{{.*}}:
 ; X64-NEXT: [[X_START:.*]]:{{$}}
 ; X64:      # BB
 ; X64:      subq    $40, %rsp
@@ -290,6 +291,7 @@
 ; X64-NEXT: [[END_OF_X:.*]]:
 ;
 ; X64-LABEL: y:
+; X64-NEXT: .L{{.*}}:
 ; X64-NEXT: [[Y_START:.*]]:{{$}}
 ; X64:      # BB
 ; X64:      subq    $40, %rsp
@@ -302,6 +304,7 @@
 ; X64-NEXT: [[END_OF_Y:.*]]:
 ;
 ; X64-LABEL: f:
+; X64-NEXT: .L{{.*}}:
 ; X64-NEXT: [[F_START:.*]]:{{$}}
 ; X64:      # BB
 ; X64:      subq    $40, %rsp
@@ -582,25 +585,25 @@ attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "
 !llvm.module.flags = !{!11, !12}
 !llvm.ident = !{!13}
 
-!0 = !{!"0x11\0012\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [D:\/<unknown>] [DW_LANG_C99]
-!1 = !{!"<unknown>", !"D:\5C"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<unknown>", directory: "D:\5C")
 !2 = !{}
 !3 = !{!4, !9, !10}
-!4 = !{!"0x2e\00x\00x\00\003\000\001\000\006\00256\000\003", !5, !6, !7, null, void ()* @x, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [x]
-!5 = !{!"source.c", !"D:\5C"}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [D:\/source.c]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "x", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !5, scope: !6, type: !7, function: void ()* @x, variables: !2)
+!5 = !DIFile(filename: "source.c", directory: "D:\5C")
+!6 = !DIFile(filename: "source.c", directory: "D:C")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null}
-!9 = !{!"0x2e\00y\00y\00\007\000\001\000\006\00256\000\007", !5, !6, !7, null, void ()* @y, null, null, !2} ; [ DW_TAG_subprogram ] [line 7] [def] [y]
-!10 = !{!"0x2e\00f\00f\00\0011\000\001\000\006\00256\000\0011", !5, !6, !7, null, void ()* @f, null, null, !2} ; [ DW_TAG_subprogram ] [line 11] [def] [f]
+!9 = !DISubprogram(name: "y", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !5, scope: !6, type: !7, function: void ()* @y, variables: !2)
+!10 = !DISubprogram(name: "f", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 11, file: !5, scope: !6, type: !7, function: void ()* @f, variables: !2)
 !11 = !{i32 2, !"Dwarf Version", i32 4}
-!12 = !{i32 1, !"Debug Info Version", i32 2}
+!12 = !{i32 1, !"Debug Info Version", i32 3}
 !13 = !{!"clang version 3.5 "}
-!14 = !MDLocation(line: 4, scope: !4)
-!15 = !MDLocation(line: 5, scope: !4)
-!16 = !MDLocation(line: 8, scope: !9)
-!17 = !MDLocation(line: 9, scope: !9)
-!18 = !MDLocation(line: 12, scope: !10)
-!19 = !MDLocation(line: 13, scope: !10)
-!20 = !MDLocation(line: 14, scope: !10)
-!21 = !MDLocation(line: 15, scope: !10)
+!14 = !DILocation(line: 4, scope: !4)
+!15 = !DILocation(line: 5, scope: !4)
+!16 = !DILocation(line: 8, scope: !9)
+!17 = !DILocation(line: 9, scope: !9)
+!18 = !DILocation(line: 12, scope: !10)
+!19 = !DILocation(line: 13, scope: !10)
+!20 = !DILocation(line: 14, scope: !10)
+!21 = !DILocation(line: 15, scope: !10)
diff --git a/test/DebugInfo/COFF/simple.ll b/test/DebugInfo/COFF/simple.ll
index 196deefe8c4e..9cb1d1e1d904 100644
--- a/test/DebugInfo/COFF/simple.ll
+++ b/test/DebugInfo/COFF/simple.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -O0 < %s | FileCheck --check-prefix=X86 %s
-; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -o - -O0 < %s | llvm-mc -triple=i686-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview-linetables | FileCheck --check-prefix=OBJ32 %s
+; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -o - -O0 < %s | llvm-mc -triple=i686-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview -section-symbols | FileCheck --check-prefix=OBJ32 %s
 ; RUN: llc -mcpu=core2 -mtriple=x86_64-pc-win32 -O0 < %s | FileCheck --check-prefix=X64 %s
-; RUN: llc -mcpu=core2 -mtriple=x86_64-pc-win32 -o - -O0 < %s | llvm-mc -triple=x86_64-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview-linetables | FileCheck --check-prefix=OBJ64 %s
+; RUN: llc -mcpu=core2 -mtriple=x86_64-pc-win32 -o - -O0 < %s | llvm-mc -triple=x86_64-pc-win32 -filetype=obj | llvm-readobj -s -sr -codeview -section-symbols | FileCheck --check-prefix=OBJ64 %s
 
 ; This LL file was generated by running clang on the following code:
 ; D:\test.c:
@@ -107,6 +107,7 @@
 ; OBJ32:    }
 
 ; X64-LABEL: f:
+; X64-NEXT: .L{{.*}}:{{$}}
 ; X64-NEXT: [[START:.*]]:{{$}}
 ; X64:      # BB
 ; X64:      subq    $40, %rsp
@@ -223,17 +224,17 @@ attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "
 !llvm.module.flags = !{!9, !10}
 !llvm.ident = !{!11}
 
-!0 = !{!"0x11\0012\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [D:\/<unknown>] [DW_LANG_C99]
-!1 = !{!"<unknown>", !"D:\5C"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<unknown>", directory: "D:\5C")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00f\00f\00\003\000\001\000\006\00256\000\003", !5, !6, !7, null, void ()* @f, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [f]
-!5 = !{!"test.c", !"D:\5C"}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [D:\/test.c]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "f", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !5, scope: !6, type: !7, function: void ()* @f, variables: !2)
+!5 = !DIFile(filename: "test.c", directory: "D:\5C")
+!6 = !DIFile(filename: "test.c", directory: "D:C")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null}
 !9 = !{i32 2, !"Dwarf Version", i32 4}
-!10 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !{i32 1, !"Debug Info Version", i32 3}
 !11 = !{!"clang version 3.5 "}
-!12 = !MDLocation(line: 4, scope: !4)
-!13 = !MDLocation(line: 5, scope: !4)
+!12 = !DILocation(line: 4, scope: !4)
+!13 = !DILocation(line: 5, scope: !4)
diff --git a/test/DebugInfo/COFF/tail-call-without-lexical-scopes.ll b/test/DebugInfo/COFF/tail-call-without-lexical-scopes.ll
index 83d976d24056..054a2e89a8fb 100644
--- a/test/DebugInfo/COFF/tail-call-without-lexical-scopes.ll
+++ b/test/DebugInfo/COFF/tail-call-without-lexical-scopes.ll
@@ -16,6 +16,7 @@
 ; with debug information available.  This used to be PR19239.
 
 ; X86-LABEL: {{^}}"?bar@@YAXHZZ":
+; X86-NEXT: L{{.*}}:
 ; X86-NEXT: # BB
 ; X86-NEXT: [[JMP_LINE:^L.*]]:{{$}}
 ; X86:      jmp "?foo@@YAXXZ"
@@ -61,18 +62,18 @@ attributes #2 = { nounwind }
 !llvm.module.flags = !{!8, !9}
 !llvm.ident = !{!10}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \001\00\000\00\002", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [D:\/test.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"test.cpp", !"D:\5C"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: true, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.cpp", directory: "D:\5C")
 !2 = !{}
 !3 = !{!4, !7}
-!4 = !{!"0x2e\00spam\00spam\00\007\000\001\000\006\00256\001\007", !1, !5, !6, null, void ()* @"\01?spam@@YAXXZ", null, null, !2} ; [ DW_TAG_subprogram ] [line 7] [def] [spam]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [D:\/test.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!7 = !{!"0x2e\00bar\00bar\00\003\001\001\000\006\00256\001\003", !1, !5, !6, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [local] [def] [bar]
+!4 = !DISubprogram(name: "spam", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 7, file: !1, scope: !5, type: !6, function: void ()* @"\01?spam@@YAXXZ", variables: !2)
+!5 = !DIFile(filename: "test.cpp", directory: "D:C")
+!6 = !DISubroutineType(types: !2)
+!7 = !DISubprogram(name: "bar", line: 3, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !1, scope: !5, type: !6, variables: !2)
 !8 = !{i32 2, !"Dwarf Version", i32 4}
-!9 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !{i32 1, !"Debug Info Version", i32 3}
 !10 = !{!"clang version 3.5.0 "}
-!11 = !MDLocation(line: 8, scope: !4)
-!12 = !MDLocation(line: 9, scope: !4)
-!13 = !MDLocation(line: 4, scope: !7)
-!14 = !MDLocation(line: 5, scope: !7)
+!11 = !DILocation(line: 8, scope: !4)
+!12 = !DILocation(line: 9, scope: !4)
+!13 = !DILocation(line: 4, scope: !7)
+!14 = !DILocation(line: 5, scope: !7)
diff --git a/test/DebugInfo/Inputs/dwarfdump-test.cc b/test/DebugInfo/Inputs/dwarfdump-test.cc
index 408999864907..14295d3cffa0 100644
--- a/test/DebugInfo/Inputs/dwarfdump-test.cc
+++ b/test/DebugInfo/Inputs/dwarfdump-test.cc
@@ -21,3 +21,9 @@ int main() {
 // $ cp dwarfdump-test.cc /tmp/dbginfo
 // $ cd /tmp/dbginfo
 // $ clang++ -g dwarfdump-test.cc -o <output>
+
+// The result is also used as an input to .dwz tool:
+// $ cp <output> output1.dwz
+// $ cp <output> output2.dwz
+// $ dwz -m output.dwz -r output1.dwz output2.dwz
+// $ rm output2.dwz
diff --git a/test/DebugInfo/Inputs/gmlt.ll b/test/DebugInfo/Inputs/gmlt.ll
index e43264010bf9..1436abedfab4 100644
--- a/test/DebugInfo/Inputs/gmlt.ll
+++ b/test/DebugInfo/Inputs/gmlt.ll
@@ -131,23 +131,23 @@ attributes #2 = { nounwind }
 !llvm.module.flags = !{!10, !11}
 !llvm.ident = !{!12}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 \000\00\000\00\002", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/gmlt.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"gmlt.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 ", isOptimized: false, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "gmlt.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4, !7, !8, !9}
-!4 = !{!"0x2e\00f1\00f1\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, void ()* @_Z2f1v, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [f1]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/gmlt.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!7 = !{!"0x2e\00f2\00f2\00\002\000\001\000\006\00256\000\002", !1, !5, !6, null, void ()* @_Z2f2v, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [f2]
-!8 = !{!"0x2e\00f3\00f3\00\003\000\001\000\006\00256\000\003", !1, !5, !6, null, void ()* @_Z2f3v, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [f3]
-!9 = !{!"0x2e\00f4\00f4\00\004\000\001\000\006\00256\000\004", !1, !5, !6, null, void ()* @_Z2f4v, null, null, !2} ; [ DW_TAG_subprogram ] [line 4] [def] [f4]
+!4 = !DISubprogram(name: "f1", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void ()* @_Z2f1v, variables: !2)
+!5 = !DIFile(filename: "gmlt.cpp", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !2)
+!7 = !DISubprogram(name: "f2", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !6, function: void ()* @_Z2f2v, variables: !2)
+!8 = !DISubprogram(name: "f3", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !5, type: !6, function: void ()* @_Z2f3v, variables: !2)
+!9 = !DISubprogram(name: "f4", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !1, scope: !5, type: !6, function: void ()* @_Z2f4v, variables: !2)
 !10 = !{i32 2, !"Dwarf Version", i32 4}
-!11 = !{i32 2, !"Debug Info Version", i32 2}
+!11 = !{i32 2, !"Debug Info Version", i32 3}
 !12 = !{!"clang version 3.6.0 "}
-!13 = !MDLocation(line: 1, column: 12, scope: !4)
-!14 = !MDLocation(line: 2, column: 53, scope: !7)
-!15 = !MDLocation(line: 3, column: 44, scope: !8)
-!16 = !MDLocation(line: 3, column: 50, scope: !8)
-!17 = !MDLocation(line: 3, column: 44, scope: !8, inlinedAt: !18)
-!18 = !MDLocation(line: 4, column: 13, scope: !9)
-!19 = !MDLocation(line: 4, column: 19, scope: !9)
+!13 = !DILocation(line: 1, column: 12, scope: !4)
+!14 = !DILocation(line: 2, column: 53, scope: !7)
+!15 = !DILocation(line: 3, column: 44, scope: !8)
+!16 = !DILocation(line: 3, column: 50, scope: !8)
+!17 = !DILocation(line: 3, column: 44, scope: !8, inlinedAt: !18)
+!18 = !DILocation(line: 4, column: 13, scope: !9)
+!19 = !DILocation(line: 4, column: 19, scope: !9)
diff --git a/test/DebugInfo/Inputs/line.ll b/test/DebugInfo/Inputs/line.ll
new file mode 100644
index 000000000000..d56c7e01a17f
--- /dev/null
+++ b/test/DebugInfo/Inputs/line.ll
@@ -0,0 +1,55 @@
+; From source:
+; int f(int a, int b) {
+;   return a   //
+;          &&  //
+;          b;
+; }
+
+; Check that the comparison of 'a' is attributed to line 2, not 3.
+
+; CHECK: .loc{{ +}}1{{ +}}2
+; CHECK-NOT: .loc{{ }}
+; CHECK: cmp
+
+; Function Attrs: nounwind uwtable
+define i32 @_Z1fii(i32 %a, i32 %b) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  store i32 %b, i32* %b.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4, !dbg !10
+  %tobool = icmp ne i32 %0, 0, !dbg !10
+  br i1 %tobool, label %land.rhs, label %land.end, !dbg !11
+
+land.rhs:                                         ; preds = %entry
+  %1 = load i32, i32* %b.addr, align 4, !dbg !12
+  %tobool1 = icmp ne i32 %1, 0, !dbg !12
+  br label %land.end
+
+land.end:                                         ; preds = %land.rhs, %entry
+  %2 = phi i1 [ false, %entry ], [ %tobool1, %land.rhs ]
+  %conv = zext i1 %2 to i32, !dbg !10
+  ret i32 %conv, !dbg !13
+}
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7, !8}
+!llvm.ident = !{!9}
+
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.7.0 (trunk 227472) (llvm/trunk 227476)", isOptimized: false, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "line.cpp", directory: "/tmp/dbginfo")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "f", line: 1, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 (i32, i32)* @_Z1fii, variables: !2)
+!5 = !DIFile(filename: "line.cpp", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !2)
+!7 = !{i32 2, !"Dwarf Version", i32 4}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
+!9 = !{!"clang version 3.7.0 (trunk 227472) (llvm/trunk 227476)"}
+!10 = !DILocation(line: 2, scope: !4)
+!11 = !DILocation(line: 3, scope: !4)
+!12 = !DILocation(line: 4, scope: !4)
+!13 = !DILocation(line: 2, scope: !4)
diff --git a/test/DebugInfo/Mips/InlinedFnLocalVar.ll b/test/DebugInfo/Mips/InlinedFnLocalVar.ll
new file mode 100644
index 000000000000..2badeba2f579
--- /dev/null
+++ b/test/DebugInfo/Mips/InlinedFnLocalVar.ll
@@ -0,0 +1,61 @@
+; RUN: llc -mtriple mips-linux-gnu -O2 %s -o - | FileCheck %s
+; Check struct X for dead variable xyz from inlined function foo.
+
+; CHECK: section_info
+; CHECK:	DW_TAG_structure_type
+; CHECK-NEXT:	info_string
+
+
+@i = common global i32 0                          ; <i32*> [#uses=2]
+
+declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
+
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone
+
+define i32 @bar() nounwind ssp {
+entry:
+  %0 = load i32, i32* @i, align 4, !dbg !17            ; <i32> [#uses=2]
+  tail call void @llvm.dbg.value(metadata i32 %0, i64 0, metadata !59, metadata !DIExpression()), !dbg !19
+  tail call void @llvm.dbg.declare(metadata !29, metadata !60, metadata !DIExpression()), !dbg !21
+  %1 = mul nsw i32 %0, %0, !dbg !22               ; <i32> [#uses=2]
+  store i32 %1, i32* @i, align 4, !dbg !17
+  ret i32 %1, !dbg !23
+}
+
+!llvm.dbg.cu = !{!2}
+!llvm.module.flags = !{!28}
+
+!0 = !DISubprogram(name: "foo", line: 9, isLocal: true, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 9, file: !27, scope: !1, type: !3, variables: !24)
+!1 = !DIFile(filename: "bar.c", directory: "/tmp/")
+!2 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 0, file: !27, enums: !20, retainedTypes: !20, subprograms: !25, globals: !26, imports:  !20)
+!3 = !DISubroutineType(types: !4)
+!4 = !{!5, !5}
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DISubprogram(name: "bar", linkageName: "bar", line: 14, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, file: !27, scope: !1, type: !7, function: i32 ()* @bar)
+!7 = !DISubroutineType(types: !8)
+!8 = !{!5}
+!9 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "j", line: 9, arg: 0, scope: !0, file: !1, type: !5)
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xyz", line: 10, scope: !11, file: !1, type: !12)
+
+!59 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "j", line: 9, arg: 0, scope: !0, file: !1, type: !5)
+!60 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xyz", line: 10, scope: !11, file: !1, type: !12)
+
+!11 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !0)
+!12 = !DICompositeType(tag: DW_TAG_structure_type, name: "X", line: 10, size: 64, align: 32, file: !27, scope: !0, elements: !13)
+!13 = !{!14, !15}
+!14 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 10, size: 32, align: 32, file: !27, scope: !12, baseType: !5)
+!15 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 10, size: 32, align: 32, offset: 32, file: !27, scope: !12, baseType: !5)
+!16 = !DIGlobalVariable(name: "i", line: 5, isLocal: false, isDefinition: true, scope: !1, file: !1, type: !5, variable: i32* @i)
+!17 = !DILocation(line: 15, scope: !18)
+!18 = distinct !DILexicalBlock(line: 14, column: 0, file: !1, scope: !6)
+!19 = !DILocation(line: 9, scope: !0, inlinedAt: !17)
+!20 = !{}
+!21 = !DILocation(line: 9, scope: !11, inlinedAt: !17)
+!22 = !DILocation(line: 11, scope: !11, inlinedAt: !17)
+!23 = !DILocation(line: 16, scope: !18)
+!24 = !{!9, !10}
+!25 = !{!0, !6}
+!26 = !{!16}
+!27 = !DIFile(filename: "bar.c", directory: "/tmp/")
+!28 = !{i32 1, !"Debug Info Version", i32 3}
+!29 = !{null}
diff --git a/test/DebugInfo/Mips/delay-slot.ll b/test/DebugInfo/Mips/delay-slot.ll
index d860cea32100..bbf749c82ab9 100644
--- a/test/DebugInfo/Mips/delay-slot.ll
+++ b/test/DebugInfo/Mips/delay-slot.ll
@@ -26,7 +26,7 @@ target triple = "mips--linux-gnu"
 ; Function Attrs: nounwind
 define i32 @foo(i32 %x) #0 {
 entry:
-  call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !12, metadata !{!"0x102"}), !dbg !13
+  call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !12, metadata !DIExpression()), !dbg !13
   %tobool = icmp ne i32 %x, 0, !dbg !14
   br i1 %tobool, label %if.then, label %if.end, !dbg !14
 
@@ -54,22 +54,22 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!9, !10}
 !llvm.ident = !{!11}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/test.c] [DW_LANG_C99]
-!1 = !{!"test.c", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.c", directory: "/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, i32 (i32)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/test.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 (i32)* @foo, variables: !2)
+!5 = !DIFile(filename: "test.c", directory: "/tmp")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 4}
-!10 = !{i32 2, !"Debug Info Version", i32 2}
+!10 = !{i32 2, !"Debug Info Version", i32 3}
 !11 = !{!"clang version 3.5.0"}
-!12 = !{!"0x101\00x\0016777217\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [x] [line 1]
-!13 = !MDLocation(line: 1, scope: !4)
-!14 = !MDLocation(line: 2, scope: !15)
-!15 = !{!"0xb\002\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/tmp/test.c]
-!16 = !MDLocation(line: 3, scope: !15)
-!17 = !MDLocation(line: 4, scope: !4)
-!18 = !MDLocation(line: 5, scope: !4)
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 1, arg: 1, scope: !4, file: !5, type: !8)
+!13 = !DILocation(line: 1, scope: !4)
+!14 = !DILocation(line: 2, scope: !15)
+!15 = distinct !DILexicalBlock(line: 2, column: 0, file: !1, scope: !4)
+!16 = !DILocation(line: 3, scope: !15)
+!17 = !DILocation(line: 4, scope: !4)
+!18 = !DILocation(line: 5, scope: !4)
diff --git a/test/DebugInfo/Mips/fn-call-line.ll b/test/DebugInfo/Mips/fn-call-line.ll
index 14cd8c9d987f..18ed3dfa43ad 100644
--- a/test/DebugInfo/Mips/fn-call-line.ll
+++ b/test/DebugInfo/Mips/fn-call-line.ll
@@ -54,8 +54,8 @@
 ; Function Attrs: nounwind uwtable
 define void @f2() #0 {
 entry:
-  call void (...)* @f1(), !dbg !11
-  call void (...)* @f1(), !dbg !12
+  call void (...) @f1(), !dbg !11
+  call void (...) @f1(), !dbg !12
   ret void, !dbg !13
 }
 
@@ -68,17 +68,17 @@ attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n
 !llvm.module.flags = !{!8, !9}
 !llvm.ident = !{!10}
 
-!0 = !{!"0x11\0012\00clang version 3.7.0 (trunk 226641)\000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/fn-call-line.c] [DW_LANG_C99]
-!1 = !{!"fn-call-line.c", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.7.0 (trunk 226641)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "fn-call-line.c", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00f2\00f2\00\002\000\001\000\000\000\000\002", !1, !5, !6, null, void ()* @f2, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [f2]
-!5 = !{!"0x29", !1}                               ; [ DW_TAG_file_type ] [/tmp/dbginfo/fn-call-line.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "f2", line: 2, isLocal: false, isDefinition: true, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !6, function: void ()* @f2, variables: !2)
+!5 = !DIFile(filename: "fn-call-line.c", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
 !8 = !{i32 2, !"Dwarf Version", i32 4}
-!9 = !{i32 2, !"Debug Info Version", i32 2}
+!9 = !{i32 2, !"Debug Info Version", i32 3}
 !10 = !{!"clang version 3.7.0 (trunk 226641)"}
-!11 = !MDLocation(line: 3, column: 3, scope: !4)
-!12 = !MDLocation(line: 4, column: 3, scope: !4)
-!13 = !MDLocation(line: 5, column: 1, scope: !4)
+!11 = !DILocation(line: 3, column: 3, scope: !4)
+!12 = !DILocation(line: 4, column: 3, scope: !4)
+!13 = !DILocation(line: 5, column: 1, scope: !4)
diff --git a/test/DebugInfo/PDB/Inputs/empty.cpp b/test/DebugInfo/PDB/Inputs/empty.cpp
new file mode 100644
index 000000000000..6021aca7bfc1
--- /dev/null
+++ b/test/DebugInfo/PDB/Inputs/empty.cpp
@@ -0,0 +1,7 @@
+// Build with "cl.exe /Zi empty.cpp /link /debug /nodefaultlib /entry:main"
+
+void *__purecall = 0;
+
+int main() {
+  return 42;
+}
diff --git a/test/DebugInfo/PDB/Inputs/empty.pdb b/test/DebugInfo/PDB/Inputs/empty.pdb
new file mode 100644
index 000000000000..ae65c3a885ce
--- /dev/null
+++ b/test/DebugInfo/PDB/Inputs/empty.pdb
diff --git a/test/DebugInfo/PDB/Inputs/symbolformat-fpo.cpp b/test/DebugInfo/PDB/Inputs/symbolformat-fpo.cpp
new file mode 100644
index 000000000000..56a5b26f2ca5
--- /dev/null
+++ b/test/DebugInfo/PDB/Inputs/symbolformat-fpo.cpp
@@ -0,0 +1,6 @@
+// Compile with "cl /GR- /Zi /c /Ox /Oy symbolformat-fpo.cpp"
+// Refer to symbolformat.cpp for linking instructions.
+
+unsigned fpo_func(unsigned n) {
+  return n * 2;
+}
diff --git a/test/DebugInfo/PDB/Inputs/symbolformat.cpp b/test/DebugInfo/PDB/Inputs/symbolformat.cpp
new file mode 100644
index 000000000000..5479b717cd9d
--- /dev/null
+++ b/test/DebugInfo/PDB/Inputs/symbolformat.cpp
@@ -0,0 +1,73 @@
+// Compile with "cl /c /Zi /GR- symbolformat.cpp"
+// Compile symbolformat-fpo.cpp (see file for instructions)
+// Link with "link symbolformat.obj symbolformat-fpo.obj /debug /nodefaultlib
+//    /entry:main /out:symbolformat.exe"
+
+int __cdecl _purecall(void) { return 0; }
+
+enum TestEnum {
+  Value,
+  Value10 = 10
+};
+
+enum class TestEnumClass {
+  Value,
+  Value10 = 10
+};
+
+struct A {
+  virtual void PureFunc() = 0 {}
+  virtual void VirtualFunc() {}
+  void RegularFunc() {}
+};
+
+struct VirtualBase {
+};
+
+struct B : public A, protected virtual VirtualBase {
+  void PureFunc() override {}
+};
+
+struct MemberTest {
+  enum NestedEnum {
+    FirstVal,
+    SecondVal
+  };
+
+  typedef int NestedTypedef;
+
+  NestedEnum m_nested_enum;
+  NestedTypedef m_typedef;
+  bool m_bool;
+  char m_char;
+  wchar_t m_wchar_t;
+  int m_int;
+  unsigned m_unsigned;
+  long m_long;
+  unsigned long m_unsigned_long;
+  __int64 m_int64;
+  unsigned __int64 m_unsigned_int64;
+  float m_float;
+  double m_double;
+  void (*m_pfn_2_args)(int, double);
+};
+
+typedef int IntType;
+typedef A ClassAType;
+
+int g_global_int;
+void *g_global_pointer = nullptr;
+
+int main(int argc, char **argv) {
+  // Force symbol references so the linker generates debug info
+  B b;
+  MemberTest members;
+  auto PureAddr = &B::PureFunc;
+  auto VirtualAddr = &A::PureFunc;
+  auto RegularAddr = &A::RegularFunc;
+  TestEnum Enum = Value;
+  TestEnumClass EnumClass = TestEnumClass::Value10;
+  IntType Int = 12;
+  ClassAType *ClassA = &b;
+  return 0;
+}
diff --git a/test/DebugInfo/PDB/Inputs/symbolformat.pdb b/test/DebugInfo/PDB/Inputs/symbolformat.pdb
new file mode 100644
index 000000000000..53d8a1b31a39
--- /dev/null
+++ b/test/DebugInfo/PDB/Inputs/symbolformat.pdb
diff --git a/test/DebugInfo/PDB/lit.local.cfg b/test/DebugInfo/PDB/lit.local.cfg
new file mode 100644
index 000000000000..28a895f51148
--- /dev/null
+++ b/test/DebugInfo/PDB/lit.local.cfg
@@ -0,0 +1 @@
+config.unsupported = not config.have_dia_sdk
diff --git a/test/DebugInfo/PDB/pdbdump-flags.test b/test/DebugInfo/PDB/pdbdump-flags.test
new file mode 100644
index 000000000000..badbf0784b5e
--- /dev/null
+++ b/test/DebugInfo/PDB/pdbdump-flags.test
@@ -0,0 +1,40 @@
+; RUN: llvm-pdbdump %p/Inputs/empty.pdb | FileCheck %s -check-prefix=NO_ARGS
+; RUN: llvm-pdbdump -types %p/Inputs/empty.pdb | FileCheck %s -check-prefix=TYPES
+; RUN: llvm-pdbdump -compilands %p/Inputs/empty.pdb | FileCheck %s -check-prefix=COMPILANDS
+; RUN: llvm-pdbdump -types -compilands %p/Inputs/empty.pdb | FileCheck %s -check-prefix=MULTIPLE
+
+; Check that neither symbols nor compilands are dumped when neither argument specified.
+; NO_ARGS: empty.pdb
+; NO_ARGS: Guid: {0B355641-86A0-A249-896F-9988FAE52FF0}
+; NO_ARGS: Attributes: HasPrivateSymbols
+; NO_ARGS-NOT: ---TYPES---
+; NO_ARGS-NOT: ---COMPILANDS---
+; NO_ARGS-NOT: ---GLOBALS---
+; NO_ARGS-NOT: ---SYMBOLS---
+
+; Check that only types are dumped when only -types is specified.
+; TYPES: empty.pdb
+; TYPES: Guid: {0B355641-86A0-A249-896F-9988FAE52FF0}
+; TYPES: Attributes: HasPrivateSymbols
+; TYPES: ---TYPES---
+; TYPES-NOT: ---COMPILANDS---
+; TYPES-NOT: ---GLOBALS---
+; TYPES-NOT: ---SYMBOLS---
+
+; Check that only compilands are dumped when only -compilands is specified.
+; COMPILANDS: empty.pdb
+; COMPILANDS: Guid: {0B355641-86A0-A249-896F-9988FAE52FF0}
+; COMPILANDS: Attributes: HasPrivateSymbols
+; COMPILANDS: ---COMPILANDS---
+; COMPILANDS-NOT: ---TYPES---
+; COMPILANDS-NOT: ---GLOBALS---
+; COMPILANDS-NOT: ---SYMBOLS---
+
+; Check that types and compilands are dumped when both arguments are specified.
+; MULTIPLE: empty.pdb
+; MULTIPLE: Guid: {0B355641-86A0-A249-896F-9988FAE52FF0}
+; MULTIPLE: Attributes: HasPrivateSymbols
+; MULTIPLE: ---COMPILANDS---
+; MULTIPLE: ---TYPES---
+; MULTIPLE-NOT: ---GLOBALS---
+; MULTIPLE-NOT: ---SYMBOLS---
diff --git a/test/DebugInfo/PDB/pdbdump-symbol-format.test b/test/DebugInfo/PDB/pdbdump-symbol-format.test
new file mode 100644
index 000000000000..6dd15fee4c59
--- /dev/null
+++ b/test/DebugInfo/PDB/pdbdump-symbol-format.test
@@ -0,0 +1,53 @@
+; RUN: llvm-pdbdump -symbols %p/Inputs/symbolformat.pdb | FileCheck --check-prefix=SYM_FORMAT %s
+; RUN: llvm-pdbdump -types %p/Inputs/symbolformat.pdb | FileCheck --check-prefix=TYPES_FORMAT %s
+; RUN: llvm-pdbdump -globals %p/Inputs/symbolformat.pdb | FileCheck --check-prefix=GLOBALS %s
+
+; The format is func [0x<rva_start>+<prologue_length> - 0x<rva_end>-<epilogue_length>]
+; SYM_FORMAT: ---SYMBOLS---
+; SYM_FORMAT: symbolformat-fpo.obj
+; SYM_FORMAT-DAG: func [{{.*}}] (FPO) unsigned __cdecl fpo_func(unsigned n)
+; SYM_FORMAT: symbolformat.obj
+; SYM_FORMAT-DAG: func [{{.*}}] (EBP) int __cdecl _purecall()
+; SYM_FORMAT-DAG: func [{{.*}}] (EBP) int __cdecl main(int argc, char** argv)
+; SYM_FORMAT-DAG: func [{{.*}}] (EBP) void A::A()
+; SYM_FORMAT-DAG: func [{{.*}}] (EBP) void B::B()
+; SYM_FORMAT-DAG: thunk [{{.*}}] (Pcode) B::`vcall'{0}'
+; SYM_FORMAT-DAG: func [{{.*}}] (EBP) virtual void B::PureFunc()
+; SYM_FORMAT-DAG: func [{{.*}}] (EBP) void A::RegularFunc()
+; SYM_FORMAT-DAG: func [{{.*}}] (EBP) virtual void A::VirtualFunc()
+
+; TYPES_FORMAT: ---TYPES---
+; TYPES_FORMAT: Enums
+; TYPES_FORMAT-DAG: enum TestEnum
+; TYPES_FORMAT-DAG: enum TestEnumClass
+; TYPES_FORMAT: Typedefs
+; TYPES_FORMAT-DAG: typedef int IntType
+; TYPES_FORMAT-DAG: typedef class A ClassAType
+; TYPES_FORMAT: Classes
+; TYPES_FORMAT: struct A {
+; TYPES_FORMAT: public:
+; TYPES_FORMAT: virtual void PureFunc() = 0
+; TYPES_FORMAT: virtual void VirtualFunc()
+; TYPES_FORMAT: void RegularFunc()
+; TYPES_FORMAT: }
+; TYPES_FORMAT-DAG: struct MemberTest {
+; TYPES_FORMAT: data +0x00 MemberTest::NestedEnum m_nested_enum
+; TYPES_FORMAT: data +0x04 int m_typedef
+; TYPES_FORMAT: data +0x08 bool m_bool
+; TYPES_FORMAT: data +0x09 char m_char
+; TYPES_FORMAT: data +0x0a wchar_t m_wchar_t
+; TYPES_FORMAT: data +0x0c int m_int
+; TYPES_FORMAT: data +0x10 unsigned m_unsigned
+; TYPES_FORMAT: data +0x14 long m_long
+; TYPES_FORMAT: data +0x18 unsigned long m_unsigned_long
+; TYPES_FORMAT: data +0x20 __int64 m_int64
+; TYPES_FORMAT: data +0x28 unsigned __int64 m_unsigned_int64
+; TYPES_FORMAT: data +0x30 float m_float
+; TYPES_FORMAT: data +0x38 double m_double
+; TYPES_FORMAT: data +0x40 void (__cdecl *m_pfn_2_args)(int, double)
+; TYPES_FORMAT: }
+
+; GLOBALS: ---GLOBALS---
+; GLOBALS-DAG: func [{{.*}}] (FPO) unsigned __cdecl fpo_func(unsigned n)
+; GLOBALS-DAG: data [{{.*}}] static void* g_global_pointer
+; GLOBALS-DAG: data [{{.*}}] static int g_global_int
diff --git a/test/DebugInfo/PR20038.ll b/test/DebugInfo/PR20038.ll
index bfee8d2b4389..8691895f41ac 100644
--- a/test/DebugInfo/PR20038.ll
+++ b/test/DebugInfo/PR20038.ll
@@ -20,7 +20,7 @@
 
 ; CHECK:  DW_TAG_subprogram
 ; CHECK-NOT: DW_TAG
-; CHECK:   DW_AT_MIPS_linkage_name {{.*}} "_ZN1CD1Ev"
+; CHECK:   DW_AT_linkage_name {{.*}} "_ZN1CD1Ev"
 ; CHECK-NOT: {{DW_TAG|NULL}}
 ; CHECK:  DW_TAG_formal_parameter
 ; CHECK-NOT: DW_TAG
@@ -58,7 +58,7 @@ entry:
   %this.addr.i = alloca %struct.C*, align 8, !dbg !22
   %agg.tmp.ensured = alloca %struct.C, align 1
   %cleanup.cond = alloca i1
-  %0 = load i8* @b, align 1, !dbg !24
+  %0 = load i8, i8* @b, align 1, !dbg !24
   %tobool = trunc i8 %0 to i1, !dbg !24
   store i1 false, i1* %cleanup.cond
   br i1 %tobool, label %land.rhs, label %land.end, !dbg !24
@@ -69,16 +69,16 @@ land.rhs:                                         ; preds = %entry
 
 land.end:                                         ; preds = %land.rhs, %entry
   %1 = phi i1 [ false, %entry ], [ true, %land.rhs ]
-  %cleanup.is_active = load i1* %cleanup.cond, !dbg !27
+  %cleanup.is_active = load i1, i1* %cleanup.cond, !dbg !27
   br i1 %cleanup.is_active, label %cleanup.action, label %cleanup.done, !dbg !27
 
 cleanup.action:                                   ; preds = %land.end
   store %struct.C* %agg.tmp.ensured, %struct.C** %this.addr.i, align 8, !dbg !22
-  call void @llvm.dbg.declare(metadata %struct.C** %this.addr.i, metadata !29, metadata !{!"0x102"}), !dbg !31
-  %this1.i = load %struct.C** %this.addr.i, !dbg !22
+  call void @llvm.dbg.declare(metadata %struct.C** %this.addr.i, metadata !129, metadata !DIExpression()), !dbg !31
+  %this1.i = load %struct.C*, %struct.C** %this.addr.i, !dbg !22
   store %struct.C* %this1.i, %struct.C** %this.addr.i.i, align 8, !dbg !21
-  call void @llvm.dbg.declare(metadata %struct.C** %this.addr.i.i, metadata !32, metadata !{!"0x102"}), !dbg !33
-  %this1.i.i = load %struct.C** %this.addr.i.i, !dbg !21
+  call void @llvm.dbg.declare(metadata %struct.C** %this.addr.i.i, metadata !132, metadata !DIExpression()), !dbg !33
+  %this1.i.i = load %struct.C*, %struct.C** %this.addr.i.i, !dbg !21
   br label %cleanup.done, !dbg !22
 
 cleanup.done:                                     ; preds = %cleanup.action, %land.end
@@ -91,11 +91,11 @@ entry:
   %this.addr.i = alloca %struct.C*, align 8, !dbg !37
   %this.addr = alloca %struct.C*, align 8
   store %struct.C* %this, %struct.C** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.C** %this.addr, metadata !29, metadata !{!"0x102"}), !dbg !38
-  %this1 = load %struct.C** %this.addr
+  call void @llvm.dbg.declare(metadata %struct.C** %this.addr, metadata !29, metadata !DIExpression()), !dbg !38
+  %this1 = load %struct.C*, %struct.C** %this.addr
   store %struct.C* %this1, %struct.C** %this.addr.i, align 8, !dbg !37
-  call void @llvm.dbg.declare(metadata %struct.C** %this.addr.i, metadata !32, metadata !{!"0x102"}), !dbg !39
-  %this1.i = load %struct.C** %this.addr.i, !dbg !37
+  call void @llvm.dbg.declare(metadata %struct.C** %this.addr.i, metadata !232, metadata !DIExpression()), !dbg !39
+  %this1.i = load %struct.C*, %struct.C** %this.addr.i, !dbg !37
   ret void, !dbg !37
 }
 
@@ -104,8 +104,8 @@ define void @_ZN1CD2Ev(%struct.C* %this) unnamed_addr #1 align 2 {
 entry:
   %this.addr = alloca %struct.C*, align 8
   store %struct.C* %this, %struct.C** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.C** %this.addr, metadata !32, metadata !{!"0x102"}), !dbg !40
-  %this1 = load %struct.C** %this.addr
+  call void @llvm.dbg.declare(metadata %struct.C** %this.addr, metadata !32, metadata !DIExpression()), !dbg !40
+  %this1 = load %struct.C*, %struct.C** %this.addr
   ret void, !dbg !41
 }
 
@@ -120,45 +120,50 @@ attributes #2 = { nounwind readnone }
 !llvm.module.flags = !{!18, !19}
 !llvm.ident = !{!20}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !3, !11, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/<stdin>] [DW_LANG_C_plus_plus]
-!1 = !{!"<stdin>", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !11, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<stdin>", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00C\001\008\008\000\000\000", !5, null, null, !6, null, null, !"_ZTS1C"} ; [ DW_TAG_structure_type ] [C] [line 1, size 8, align 8, offset 0] [def] [from ]
-!5 = !{!"PR20038.cpp", !"/tmp/dbginfo"}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "C", line: 1, size: 8, align: 8, file: !5, elements: !6, identifier: "_ZTS1C")
+!5 = !DIFile(filename: "PR20038.cpp", directory: "/tmp/dbginfo")
 !6 = !{!7}
-!7 = !{!"0x2e\00~C\00~C\00\002\000\000\000\006\00256\000\002", !5, !"_ZTS1C", !8, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 2] [~C]
-!8 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !9, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = !DISubprogram(name: "~C", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !5, scope: !"_ZTS1C", type: !8)
+!8 = !DISubroutineType(types: !9)
 !9 = !{null, !10}
-!10 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1C"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1C]
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1C")
 !11 = !{!12, !16, !17}
-!12 = !{!"0x2e\00fun4\00fun4\00_Z4fun4v\005\000\001\000\006\00256\000\005", !5, !13, !14, null, void ()* @_Z4fun4v, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [fun4]
-!13 = !{!"0x29", !5}         ; [ DW_TAG_file_type ] [/tmp/dbginfo/PR20038.cpp]
-!14 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !15, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = !DISubprogram(name: "fun4", linkageName: "_Z4fun4v", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !5, scope: !13, type: !14, function: void ()* @_Z4fun4v, variables: !2)
+!13 = !DIFile(filename: "PR20038.cpp", directory: "/tmp/dbginfo")
+!14 = !DISubroutineType(types: !15)
 !15 = !{null}
-!16 = !{!"0x2e\00~C\00~C\00_ZN1CD2Ev\006\000\001\000\006\00256\000\006", !5, !"_ZTS1C", !8, null, void (%struct.C*)* @_ZN1CD2Ev, null, !7, !2} ; [ DW_TAG_subprogram ] [line 6] [def] [~C]
-!17 = !{!"0x2e\00~C\00~C\00_ZN1CD1Ev\006\000\001\000\006\00256\000\006", !5, !"_ZTS1C", !8, null, void (%struct.C*)* @_ZN1CD1Ev, null, !7, !2} ; [ DW_TAG_subprogram ] [line 6] [def] [~C]
+!16 = !DISubprogram(name: "~C", linkageName: "_ZN1CD2Ev", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 6, file: !5, scope: !"_ZTS1C", type: !8, function: void (%struct.C*)* @_ZN1CD2Ev, declaration: !7, variables: !2)
+!17 = !DISubprogram(name: "~C", linkageName: "_ZN1CD1Ev", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 6, file: !5, scope: !"_ZTS1C", type: !8, function: void (%struct.C*)* @_ZN1CD1Ev, declaration: !7, variables: !2)
 !18 = !{i32 2, !"Dwarf Version", i32 4}
-!19 = !{i32 2, !"Debug Info Version", i32 2}
+!19 = !{i32 2, !"Debug Info Version", i32 3}
 !20 = !{!"clang version 3.5.0 "}
-!21 = !MDLocation(line: 6, scope: !17, inlinedAt: !22)
-!22 = !MDLocation(line: 5, scope: !23)
-!23 = !{!"0xb\005\000\003", !5, !12} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/PR20038.cpp]
-!24 = !MDLocation(line: 5, scope: !12)
-!25 = !MDLocation(line: 5, scope: !26)
-!26 = !{!"0xb\005\000\001", !5, !12} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/PR20038.cpp]
-!27 = !MDLocation(line: 5, scope: !28)
-!28 = !{!"0xb\005\000\002", !5, !12} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/PR20038.cpp]
-!29 = !{!"0x101\00this\0016777216\001088", !17, null, !30} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!30 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1C"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1C]
-!31 = !MDLocation(line: 0, scope: !17, inlinedAt: !22)
-!32 = !{!"0x101\00this\0016777216\001088", !16, null, !30} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!33 = !MDLocation(line: 0, scope: !16, inlinedAt: !21)
-!34 = !MDLocation(line: 5, scope: !35)
-!35 = !{!"0xb\005\000\005", !5, !36} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/PR20038.cpp]
-!36 = !{!"0xb\005\000\004", !5, !12} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/PR20038.cpp]
-!37 = !MDLocation(line: 6, scope: !17)
-!38 = !MDLocation(line: 0, scope: !17)
-!39 = !MDLocation(line: 0, scope: !16, inlinedAt: !37)
-!40 = !MDLocation(line: 0, scope: !16)
-!41 = !MDLocation(line: 6, scope: !16)
+!21 = !DILocation(line: 6, scope: !17, inlinedAt: !22)
+!22 = !DILocation(line: 5, scope: !23)
+!23 = distinct !DILexicalBlock(line: 5, column: 0, file: !5, scope: !12)
+!24 = !DILocation(line: 5, scope: !12)
+!25 = !DILocation(line: 5, scope: !26)
+!26 = distinct !DILexicalBlock(line: 5, column: 0, file: !5, scope: !12)
+!27 = !DILocation(line: 5, scope: !28)
+!28 = distinct !DILexicalBlock(line: 5, column: 0, file: !5, scope: !12)
+!29 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !17, type: !30)
+!30 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1C")
+!31 = !DILocation(line: 0, scope: !17, inlinedAt: !22)
+!32 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !16, type: !30)
+!33 = !DILocation(line: 0, scope: !16, inlinedAt: !21)
+
+!129 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !17, type: !30)
+!132 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !16, type: !30)
+!232 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !16, type: !30)
+
+!34 = !DILocation(line: 5, scope: !35)
+!35 = distinct !DILexicalBlock(line: 5, column: 0, file: !5, scope: !36)
+!36 = distinct !DILexicalBlock(line: 5, column: 0, file: !5, scope: !12)
+!37 = !DILocation(line: 6, scope: !17)
+!38 = !DILocation(line: 0, scope: !17)
+!39 = !DILocation(line: 0, scope: !16, inlinedAt: !37)
+!40 = !DILocation(line: 0, scope: !16)
+!41 = !DILocation(line: 6, scope: !16)
diff --git a/test/DebugInfo/PowerPC/line.test b/test/DebugInfo/PowerPC/line.test
new file mode 100644
index 000000000000..c1970ff811b9
--- /dev/null
+++ b/test/DebugInfo/PowerPC/line.test
@@ -0,0 +1,7 @@
+; RUN: llc -mtriple=powerpc-unknown-linux -O0 -filetype=asm < %S/../Inputs/line.ll | FileCheck %S/../Inputs/line.ll
+
+; This is more complex than it looked. It's mixed up somewhere in SelectionDAG
+; (legalized as br_cc, losing the separation between the comparison and the
+; branch, then further lowered to cmplwi + brcc but without the fidelity that
+; those two instructions are on separate lines)
+; XFAIL: *
diff --git a/test/DebugInfo/PowerPC/tls-fission.ll b/test/DebugInfo/PowerPC/tls-fission.ll
index 7bb1626aa1ec..25bc9959e4d1 100644
--- a/test/DebugInfo/PowerPC/tls-fission.ll
+++ b/test/DebugInfo/PowerPC/tls-fission.ll
@@ -14,6 +14,7 @@
 ; CHECK-NEXT: .byte 224
 ; check that the expected TLS address description is the first thing in the debug_addr section
 ; CHECK: debug_addr
+; CHECK-NEXT: .Laddr_sec:
 ; CHECK-NEXT: .quad tls@dtprel+32768
 
 @tls = thread_local global i32 0, align 4
@@ -21,12 +22,12 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!7, !8}
 
-!0 = !{!"0x11\004\00clang version 3.4 \000\00\000\00tls.dwo\000", !1, !2, !2, !2, !3, !2} ; [ DW_TAG_compile_unit ] [/tmp/tls.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"tls.cpp", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 ", isOptimized: false, splitDebugFilename: "tls.dwo", emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3, imports: !2)
+!1 = !DIFile(filename: "tls.cpp", directory: "/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x34\00tls\00tls\00\001\000\001", null, !5, !6, i32* @tls, null} ; [ DW_TAG_variable ] [tls] [line 1] [def]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/tls.cpp]
-!6 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!4 = !DIGlobalVariable(name: "tls", line: 1, isLocal: false, isDefinition: true, scope: null, file: !5, type: !6, variable: i32* @tls)
+!5 = !DIFile(filename: "tls.cpp", directory: "/tmp")
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !7 = !{i32 2, !"Dwarf Version", i32 3}
-!8 = !{i32 1, !"Debug Info Version", i32 2}
+!8 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/PowerPC/tls.ll b/test/DebugInfo/PowerPC/tls.ll
index be6313633916..8ba350ac60d3 100644
--- a/test/DebugInfo/PowerPC/tls.ll
+++ b/test/DebugInfo/PowerPC/tls.ll
@@ -17,13 +17,13 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!7, !8}
 
-!0 = !{!"0x11\004\00clang version 3.4 \000\00\000\00\000", !1, !2, !2, !2, !3, !2} ; [ DW_TAG_compile_unit ] [/tmp/tls.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"tls.cpp", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3, imports: !2)
+!1 = !DIFile(filename: "tls.cpp", directory: "/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x34\00tls\00tls\00\001\000\001", null, !5, !6, i32* @tls, null} ; [ DW_TAG_variable ] [tls] [line 1] [def]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/tls.cpp]
-!6 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!4 = !DIGlobalVariable(name: "tls", line: 1, isLocal: false, isDefinition: true, scope: null, file: !5, type: !6, variable: i32* @tls)
+!5 = !DIFile(filename: "tls.cpp", directory: "/tmp")
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !7 = !{i32 2, !"Dwarf Version", i32 3}
 
-!8 = !{i32 1, !"Debug Info Version", i32 2}
+!8 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/Sparc/gnu-window-save.ll b/test/DebugInfo/Sparc/gnu-window-save.ll
index 5bf3f02538d5..c2e0364307fa 100644
--- a/test/DebugInfo/Sparc/gnu-window-save.ll
+++ b/test/DebugInfo/Sparc/gnu-window-save.ll
@@ -42,7 +42,7 @@ define signext i32 @main() #0 {
 entry:
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
-  %call = call signext i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str, i32 0, i32 0)), !dbg !12
+  %call = call signext i32 (i8*, ...) @printf(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str, i32 0, i32 0)), !dbg !12
   ret i32 0, !dbg !13
 }
 
@@ -55,17 +55,17 @@ attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n
 !llvm.module.flags = !{!9, !10}
 !llvm.ident = !{!11}
 
-!0 = !{!"0x11\0012\00clang version 3.5 (http://llvm.org/git/clang.git 6a0714fee07fb7c4e32d3972b4fe2ce2f5678cf4) (llvm/ 672e88e934757f76d5c5e5258be41e7615094844)\000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/home/venkatra/work/benchmarks/test/hello/hello.c] [DW_LANG_C99]
-!1 = !{!"hello.c", !"/home/venkatra/work/benchmarks/test/hello"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 (http://llvm.org/git/clang.git 6a0714fee07fb7c4e32d3972b4fe2ce2f5678cf4) (llvm/ 672e88e934757f76d5c5e5258be41e7615094844)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "hello.c", directory: "/home/venkatra/work/benchmarks/test/hello")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00main\00main\00\003\000\001\000\006\00256\000\004", !1, !5, !6, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 4] [main]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/home/venkatra/work/benchmarks/test/hello/hello.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "main", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !1, scope: !5, type: !6, function: i32 ()* @main, variables: !2)
+!5 = !DIFile(filename: "hello.c", directory: "/home/venkatra/work/benchmarks/test/hello")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 4}
-!10 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !{i32 1, !"Debug Info Version", i32 3}
 !11 = !{!"clang version 3.5 (http://llvm.org/git/clang.git 6a0714fee07fb7c4e32d3972b4fe2ce2f5678cf4) (llvm/ 672e88e934757f76d5c5e5258be41e7615094844)"}
-!12 = !MDLocation(line: 5, scope: !4)
-!13 = !MDLocation(line: 6, scope: !4)
+!12 = !DILocation(line: 5, scope: !4)
+!13 = !DILocation(line: 6, scope: !4)
diff --git a/test/DebugInfo/SystemZ/eh_frame.s b/test/DebugInfo/SystemZ/eh_frame.s
index 6189b9019673..ad7862f97481 100644
--- a/test/DebugInfo/SystemZ/eh_frame.s
+++ b/test/DebugInfo/SystemZ/eh_frame.s
@@ -72,7 +72,7 @@ check_largest_class:
 #   DW_CFA_nop
 #
 # CHECK: Contents of section .eh_frame:
-# CHECK-NEXT: 0000 00000014 00000000 037a5200 01780e01  {{.*}}
+# CHECK-NEXT: 0000 00000014 00000000 017a5200 01780e01  {{.*}}
 # CHECK-NEXT: 0010 1b0c0fa0 01000000 0000002c 0000001c  {{.*}}
 # CHECK-NEXT: 0020 00000000 00000032 00468d07 8e068f05  {{.*}}
 # CHECK-NEXT: 0030 440e8003 60981c9c 1b991a9d 199a189e  {{.*}}
diff --git a/test/DebugInfo/SystemZ/eh_frame_personality.s b/test/DebugInfo/SystemZ/eh_frame_personality.s
index 456e0a6e6bdd..c452951941a1 100644
--- a/test/DebugInfo/SystemZ/eh_frame_personality.s
+++ b/test/DebugInfo/SystemZ/eh_frame_personality.s
@@ -61,7 +61,7 @@ DW.ref.__gxx_personality_v0:
 #   DW_CFA_nop
 #
 # CHECK: Contents of section .eh_frame:
-# CHECK-NEXT: 0000 0000001c 00000000 037a504c 52000178  .........zPLR..x
+# CHECK-NEXT: 0000 0000001c 00000000 017a504c 52000178  .........zPLR..x
 # CHECK-NEXT: 0010 0e079b00 0000001b 1b0c0fa0 01000000  ................
 # CHECK-NEXT: 0020 0000001c 00000024 00000000 00000012  .......$........
 # CHECK-NEXT: 0030 04000000 00468e06 8f05440e c0020000  .....F....D.....
diff --git a/test/DebugInfo/SystemZ/variable-loc.ll b/test/DebugInfo/SystemZ/variable-loc.ll
index 9e5c6a9e7e67..5f4fe258b976 100644
--- a/test/DebugInfo/SystemZ/variable-loc.ll
+++ b/test/DebugInfo/SystemZ/variable-loc.ll
@@ -35,15 +35,15 @@ entry:
   %main_arr = alloca [100 x i32], align 4
   %val = alloca i32, align 4
   store volatile i32 0, i32* %retval
-  call void @llvm.dbg.declare(metadata [100 x i32]* %main_arr, metadata !17, metadata !{!"0x102"}), !dbg !22
-  call void @llvm.dbg.declare(metadata i32* %val, metadata !23, metadata !{!"0x102"}), !dbg !24
-  %arraydecay = getelementptr inbounds [100 x i32]* %main_arr, i32 0, i32 0, !dbg !25
+  call void @llvm.dbg.declare(metadata [100 x i32]* %main_arr, metadata !17, metadata !DIExpression()), !dbg !22
+  call void @llvm.dbg.declare(metadata i32* %val, metadata !23, metadata !DIExpression()), !dbg !24
+  %arraydecay = getelementptr inbounds [100 x i32], [100 x i32]* %main_arr, i32 0, i32 0, !dbg !25
   call void @populate_array(i32* %arraydecay, i32 100), !dbg !25
-  %arraydecay1 = getelementptr inbounds [100 x i32]* %main_arr, i32 0, i32 0, !dbg !26
+  %arraydecay1 = getelementptr inbounds [100 x i32], [100 x i32]* %main_arr, i32 0, i32 0, !dbg !26
   %call = call i32 @sum_array(i32* %arraydecay1, i32 100), !dbg !26
   store i32 %call, i32* %val, align 4, !dbg !26
-  %0 = load i32* %val, align 4, !dbg !27
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), i32 %0), !dbg !27
+  %0 = load i32, i32* %val, align 4, !dbg !27
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %0), !dbg !27
   ret i32 0, !dbg !28
 }
 
@@ -52,31 +52,31 @@ declare i32 @printf(i8*, ...)
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!30}
 
-!0 = !{!"0x11\0012\00clang version 3.2 \000\00\000\00\000", !29, !1, !1, !3, !1,  !1} ; [ DW_TAG_compile_unit ] [/home/timnor01/a64-trunk/build/simple.c] [DW_LANG_C99]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.2 ", isOptimized: false, emissionKind: 0, file: !29, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports:  !1)
 !1 = !{}
 !3 = !{!5, !11, !14}
-!5 = !{!"0x2e\00populate_array\00populate_array\00\004\000\001\000\006\00256\000\004", !29, !6, !7, null, void (i32*, i32)* @populate_array, null, null, !1} ; [ DW_TAG_subprogram ] [line 4] [def] [populate_array]
-!6 = !{!"0x29", !29} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "populate_array", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !29, scope: !6, type: !7, function: void (i32*, i32)* @populate_array, variables: !1)
+!6 = !DIFile(filename: "simple.c", directory: "/home/timnor01/a64-trunk/build")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9, !10}
-!9 = !{!"0xf\00\000\0064\0064\000\000", null, null, !10} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
-!10 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!11 = !{!"0x2e\00sum_array\00sum_array\00\009\000\001\000\006\00256\000\009", !29, !6, !12, null, i32 (i32*, i32)* @sum_array, null, null, !1} ; [ DW_TAG_subprogram ] [line 9] [def] [sum_array]
-!12 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !13, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !10)
+!10 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!11 = !DISubprogram(name: "sum_array", line: 9, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 9, file: !29, scope: !6, type: !12, function: i32 (i32*, i32)* @sum_array, variables: !1)
+!12 = !DISubroutineType(types: !13)
 !13 = !{!10, !9, !10}
-!14 = !{!"0x2e\00main\00main\00\0018\000\001\000\006\00256\000\0018", !29, !6, !15, null, i32 ()* @main, null, null, !1} ; [ DW_TAG_subprogram ] [line 18] [def] [main]
-!15 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!14 = !DISubprogram(name: "main", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 18, file: !29, scope: !6, type: !15, function: i32 ()* @main, variables: !1)
+!15 = !DISubroutineType(types: !16)
 !16 = !{!10}
-!17 = !{!"0x100\00main_arr\0019\000", !18, !6, !19} ; [ DW_TAG_auto_variable ] [main_arr] [line 19]
-!18 = !{!"0xb\0018\0016\004", !29, !14} ; [ DW_TAG_lexical_block ] [/home/timnor01/a64-trunk/build/simple.c]
-!19 = !{!"0x1\00\000\003200\0032\000\000", null, null, !10, !20, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 3200, align 32, offset 0] [from int]
-!20 = !{!"0x21\000\0099"}       ; [ DW_TAG_subrange_type ] [0, 99]
-!22 = !MDLocation(line: 19, column: 7, scope: !18)
-!23 = !{!"0x100\00val\0020\000", !18, !6, !10} ; [ DW_TAG_auto_variable ] [val] [line 20]
-!24 = !MDLocation(line: 20, column: 7, scope: !18)
-!25 = !MDLocation(line: 22, column: 3, scope: !18)
-!26 = !MDLocation(line: 23, column: 9, scope: !18)
-!27 = !MDLocation(line: 24, column: 3, scope: !18)
-!28 = !MDLocation(line: 26, column: 3, scope: !18)
-!29 = !{!"simple.c", !"/home/timnor01/a64-trunk/build"}
-!30 = !{i32 1, !"Debug Info Version", i32 2}
+!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "main_arr", line: 19, scope: !18, file: !6, type: !19)
+!18 = distinct !DILexicalBlock(line: 18, column: 16, file: !29, scope: !14)
+!19 = !DICompositeType(tag: DW_TAG_array_type, size: 3200, align: 32, baseType: !10, elements: !{!20})
+!20 = !DISubrange(count: 99)
+!22 = !DILocation(line: 19, column: 7, scope: !18)
+!23 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "val", line: 20, scope: !18, file: !6, type: !10)
+!24 = !DILocation(line: 20, column: 7, scope: !18)
+!25 = !DILocation(line: 22, column: 3, scope: !18)
+!26 = !DILocation(line: 23, column: 9, scope: !18)
+!27 = !DILocation(line: 24, column: 3, scope: !18)
+!28 = !DILocation(line: 26, column: 3, scope: !18)
+!29 = !DIFile(filename: "simple.c", directory: "/home/timnor01/a64-trunk/build")
+!30 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/2010-04-13-PubType.ll b/test/DebugInfo/X86/2010-04-13-PubType.ll
index 0aec0361b885..85c499d59630 100644
--- a/test/DebugInfo/X86/2010-04-13-PubType.ll
+++ b/test/DebugInfo/X86/2010-04-13-PubType.ll
@@ -12,17 +12,17 @@ entry:
   %retval = alloca i32                            ; <i32*> [#uses=2]
   %0 = alloca i32                                 ; <i32*> [#uses=2]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.declare(metadata %struct.X** %x_addr, metadata !0, metadata !{!"0x102"}), !dbg !13
+  call void @llvm.dbg.declare(metadata %struct.X** %x_addr, metadata !0, metadata !DIExpression()), !dbg !13
   store %struct.X* %x, %struct.X** %x_addr
-  call void @llvm.dbg.declare(metadata %struct.Y** %y_addr, metadata !14, metadata !{!"0x102"}), !dbg !13
+  call void @llvm.dbg.declare(metadata %struct.Y** %y_addr, metadata !14, metadata !DIExpression()), !dbg !13
   store %struct.Y* %y, %struct.Y** %y_addr
   store i32 0, i32* %0, align 4, !dbg !13
-  %1 = load i32* %0, align 4, !dbg !13            ; <i32> [#uses=1]
+  %1 = load i32, i32* %0, align 4, !dbg !13            ; <i32> [#uses=1]
   store i32 %1, i32* %retval, align 4, !dbg !13
   br label %return, !dbg !13
 
 return:                                           ; preds = %entry
-  %retval1 = load i32* %retval, !dbg !13          ; <i32> [#uses=1]
+  %retval1 = load i32, i32* %retval, !dbg !13          ; <i32> [#uses=1]
   ret i32 %retval1, !dbg !15
 }
 
@@ -31,24 +31,24 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!3}
 !llvm.module.flags = !{!20}
 
-!0 = !{!"0x101\00x\007\000", !1, !2, !7} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00foo\00foo\00foo\007\000\001\000\006\000\000\007", !18, !2, !4, null, i32 (%struct.X*, %struct.Y*)* @foo, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !18} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\000\00\000\00\000", !18, !19, !19, !17, null,  null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !18, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 7, arg: 0, scope: !1, file: !2, type: !7)
+!1 = !DISubprogram(name: "foo", linkageName: "foo", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 7, file: !18, scope: !2, type: !4, function: i32 (%struct.X*, %struct.Y*)* @foo)
+!2 = !DIFile(filename: "a.c", directory: "/tmp/")
+!3 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: false, emissionKind: 0, file: !18, enums: !19, retainedTypes: !19, subprograms: !17, imports:  null)
+!4 = !DISubroutineType(types: !5)
 !5 = !{!6, !7, !9}
-!6 = !{!"0x24\00int\000\0032\0032\000\000\005", !18, !2} ; [ DW_TAG_base_type ]
-!7 = !{!"0xf\00\000\0064\0064\000\000", !18, !2, !8} ; [ DW_TAG_pointer_type ]
-!8 = !{!"0x13\00X\003\000\000\000\004\000", !18, !2, null, null, null, null, null} ; [ DW_TAG_structure_type ] [X] [line 3, size 0, align 0, offset 0] [decl] [from ]
-!9 = !{!"0xf\00\000\0064\0064\000\000", !18, !2, !10} ; [ DW_TAG_pointer_type ]
-!10 = !{!"0x13\00Y\004\0032\0032\000\000\000", !18, !2, null, !11, null, null, null} ; [ DW_TAG_structure_type ] [Y] [line 4, size 32, align 32, offset 0] [def] [from ]
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!7 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !18, scope: !2, baseType: !8)
+!8 = !DICompositeType(tag: DW_TAG_structure_type, name: "X", line: 3, flags: DIFlagFwdDecl, file: !18, scope: !2)
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !18, scope: !2, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_structure_type, name: "Y", line: 4, size: 32, align: 32, file: !18, scope: !2, elements: !11)
 !11 = !{!12}
-!12 = !{!"0xd\00x\005\0032\0032\000\000", !18, !10, !6} ; [ DW_TAG_member ]
-!13 = !MDLocation(line: 7, scope: !1)
-!14 = !{!"0x101\00y\007\000", !1, !2, !9} ; [ DW_TAG_arg_variable ]
-!15 = !MDLocation(line: 7, scope: !16)
-!16 = !{!"0xb\007\000\000", !18, !1} ; [ DW_TAG_lexical_block ]
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 5, size: 32, align: 32, file: !18, scope: !10, baseType: !6)
+!13 = !DILocation(line: 7, scope: !1)
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "y", line: 7, arg: 0, scope: !1, file: !2, type: !9)
+!15 = !DILocation(line: 7, scope: !16)
+!16 = distinct !DILexicalBlock(line: 7, column: 0, file: !18, scope: !1)
 !17 = !{!1}
-!18 = !{!"a.c", !"/tmp/"}
-!19 = !{i32 0}
-!20 = !{i32 1, !"Debug Info Version", i32 2}
+!18 = !DIFile(filename: "a.c", directory: "/tmp/")
+!19 = !{}
+!20 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/2010-08-10-DbgConstant.ll b/test/DebugInfo/X86/2010-08-10-DbgConstant.ll
deleted file mode 100644
index bcaac896f1af..000000000000
--- a/test/DebugInfo/X86/2010-08-10-DbgConstant.ll
+++ /dev/null
@@ -1,31 +0,0 @@
-; RUN: llc  -mtriple=i686-linux -O0 -filetype=obj -o %t %s
-; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s
-; CHECK: DW_TAG_constant
-; CHECK-NEXT: DW_AT_name [DW_FORM_strp] ( .debug_str[0x{{[0-9a-f]*}}] = "ro")
-
-define void @foo() nounwind ssp {
-entry:
-  call void @bar(i32 201), !dbg !8
-  ret void, !dbg !8
-}
-
-declare void @bar(i32)
-
-!llvm.dbg.cu = !{!2}
-!llvm.module.flags = !{!13}
-
-!0 = !{!"0x2e\00foo\00foo\00foo\003\000\001\000\006\000\000\003", !12, !1, !3, null, void ()* @foo, null, null, null} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !12} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang 2.8\000\00\000\00\000", !12, !4, !4, !10, !11,  !14} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !12, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!4 = !{null}
-!5 = !{!"0x27\00ro\00ro\00ro\001\001\001", !1, !1, !6, i32 201, null} ; [ DW_TAG_constant ]
-!6 = !{!"0x26\00\000\000\000\000\000", !12, !1, !7} ; [ DW_TAG_const_type ]
-!7 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", !12, !1} ; [ DW_TAG_base_type ]
-!8 = !MDLocation(line: 3, column: 14, scope: !9)
-!9 = !{!"0xb\003\0012\000", !12, !0} ; [ DW_TAG_lexical_block ]
-!10 = !{!0}
-!11 = !{!5}
-!12 = !{!"/tmp/l.c", !"/Volumes/Lalgate/clean/D"}
-!13 = !{i32 1, !"Debug Info Version", i32 2}
-!14 = !{}
diff --git a/test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll b/test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll
index d1beadcbb0a2..1252f2cb32e3 100644
--- a/test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll
+++ b/test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll
@@ -7,10 +7,10 @@
 
 define i32 @f() nounwind {
   %LOC = alloca i32, align 4
-  call void @llvm.dbg.declare(metadata i32* %LOC, metadata !15, metadata !{!"0x102"}), !dbg !17
-  %1 = load i32* @GLB, align 4, !dbg !18
+  call void @llvm.dbg.declare(metadata i32* %LOC, metadata !15, metadata !DIExpression()), !dbg !17
+  %1 = load i32, i32* @GLB, align 4, !dbg !18
   store i32 %1, i32* %LOC, align 4, !dbg !18
-  %2 = load i32* @GLB, align 4, !dbg !19
+  %2 = load i32, i32* @GLB, align 4, !dbg !19
   ret i32 %2, !dbg !19
 }
 
@@ -19,22 +19,22 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!21}
 
-!0 = !{!"0x11\0012\00clang version 3.0 (trunk)\000\00\000\00\000", !20, !1, !1, !3, !12,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk)", isOptimized: false, emissionKind: 0, file: !20, enums: !1, retainedTypes: !1, subprograms: !3, globals: !12, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00f\00f\00\003\000\001\000\006\000\000\000", !6, !6, !7, null, i32 ()* @f, null, null, null} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 0] [f]
-!6 = !{!"0x29", !20} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "f", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !6, scope: !6, type: !7, function: i32 ()* @f)
+!6 = !DIFile(filename: "test.c", directory: "/work/llvm/vanilla/test/DebugInfo")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !12 = !{!14}
-!14 = !{!"0x34\00GLB\00GLB\00\001\000\001", null, !6, !9, i32* @GLB, null} ; [ DW_TAG_variable ]
-!15 = !{!"0x100\00LOC\004\000", !16, !6, !9} ; [ DW_TAG_auto_variable ]
-!16 = !{!"0xb\003\009\000", !20, !5} ; [ DW_TAG_lexical_block ]
-!17 = !MDLocation(line: 4, column: 9, scope: !16)
-!18 = !MDLocation(line: 4, column: 23, scope: !16)
-!19 = !MDLocation(line: 5, column: 5, scope: !16)
-!20 = !{!"test.c", !"/work/llvm/vanilla/test/DebugInfo"}
+!14 = !DIGlobalVariable(name: "GLB", line: 1, isLocal: false, isDefinition: true, scope: null, file: !6, type: !9, variable: i32* @GLB)
+!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "LOC", line: 4, scope: !16, file: !6, type: !9)
+!16 = distinct !DILexicalBlock(line: 3, column: 9, file: !20, scope: !5)
+!17 = !DILocation(line: 4, column: 9, scope: !16)
+!18 = !DILocation(line: 4, column: 23, scope: !16)
+!19 = !DILocation(line: 5, column: 5, scope: !16)
+!20 = !DIFile(filename: "test.c", directory: "/work/llvm/vanilla/test/DebugInfo")
 
 ; CHECK: DW_TAG_variable
 ; CHECK-NOT: DW_TAG
@@ -52,4 +52,4 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 ; CHECK-NOT: DW_TAG
 ; CHECK: DW_AT_decl_line [DW_FORM_data1]     (4)
 
-!21 = !{i32 1, !"Debug Info Version", i32 2}
+!21 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/2011-12-16-BadStructRef.ll b/test/DebugInfo/X86/2011-12-16-BadStructRef.ll
index 4880fa49fc5e..fc3f69b3584c 100644
--- a/test/DebugInfo/X86/2011-12-16-BadStructRef.ll
+++ b/test/DebugInfo/X86/2011-12-16-BadStructRef.ll
@@ -15,10 +15,10 @@ entry:
   %myBar = alloca %struct.bar, align 8
   store i32 0, i32* %retval
   store i32 %argc, i32* %argc.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %argc.addr, metadata !49, metadata !{!"0x102"}), !dbg !50
+  call void @llvm.dbg.declare(metadata i32* %argc.addr, metadata !49, metadata !DIExpression()), !dbg !50
   store i8** %argv, i8*** %argv.addr, align 8
-  call void @llvm.dbg.declare(metadata i8*** %argv.addr, metadata !51, metadata !{!"0x102"}), !dbg !52
-  call void @llvm.dbg.declare(metadata %struct.bar* %myBar, metadata !53, metadata !{!"0x102"}), !dbg !55
+  call void @llvm.dbg.declare(metadata i8*** %argv.addr, metadata !51, metadata !DIExpression()), !dbg !52
+  call void @llvm.dbg.declare(metadata %struct.bar* %myBar, metadata !53, metadata !DIExpression()), !dbg !55
   call void @_ZN3barC1Ei(%struct.bar* %myBar, i32 1), !dbg !56
   ret i32 0, !dbg !57
 }
@@ -30,11 +30,11 @@ entry:
   %this.addr = alloca %struct.bar*, align 8
   %x.addr = alloca i32, align 4
   store %struct.bar* %this, %struct.bar** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.bar** %this.addr, metadata !58, metadata !{!"0x102"}), !dbg !59
+  call void @llvm.dbg.declare(metadata %struct.bar** %this.addr, metadata !58, metadata !DIExpression()), !dbg !59
   store i32 %x, i32* %x.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !60, metadata !{!"0x102"}), !dbg !61
-  %this1 = load %struct.bar** %this.addr
-  %0 = load i32* %x.addr, align 4, !dbg !62
+  call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !60, metadata !DIExpression()), !dbg !61
+  %this1 = load %struct.bar*, %struct.bar** %this.addr
+  %0 = load i32, i32* %x.addr, align 4, !dbg !62
   call void @_ZN3barC2Ei(%struct.bar* %this1, i32 %0), !dbg !62
   ret void, !dbg !62
 }
@@ -44,15 +44,15 @@ entry:
   %this.addr = alloca %struct.bar*, align 8
   %x.addr = alloca i32, align 4
   store %struct.bar* %this, %struct.bar** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.bar** %this.addr, metadata !63, metadata !{!"0x102"}), !dbg !64
+  call void @llvm.dbg.declare(metadata %struct.bar** %this.addr, metadata !63, metadata !DIExpression()), !dbg !64
   store i32 %x, i32* %x.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !65, metadata !{!"0x102"}), !dbg !66
-  %this1 = load %struct.bar** %this.addr
-  %b = getelementptr inbounds %struct.bar* %this1, i32 0, i32 0, !dbg !67
-  %0 = load i32* %x.addr, align 4, !dbg !67
+  call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !65, metadata !DIExpression()), !dbg !66
+  %this1 = load %struct.bar*, %struct.bar** %this.addr
+  %b = getelementptr inbounds %struct.bar, %struct.bar* %this1, i32 0, i32 0, !dbg !67
+  %0 = load i32, i32* %x.addr, align 4, !dbg !67
   call void @_ZN3bazC1Ei(%struct.baz* %b, i32 %0), !dbg !67
-  %1 = getelementptr inbounds %struct.bar* %this1, i32 0, i32 1, !dbg !67
-  %b2 = getelementptr inbounds %struct.bar* %this1, i32 0, i32 0, !dbg !67
+  %1 = getelementptr inbounds %struct.bar, %struct.bar* %this1, i32 0, i32 1, !dbg !67
+  %b2 = getelementptr inbounds %struct.bar, %struct.bar* %this1, i32 0, i32 0, !dbg !67
   store %struct.baz* %b2, %struct.baz** %1, align 8, !dbg !67
   ret void, !dbg !68
 }
@@ -62,11 +62,11 @@ entry:
   %this.addr = alloca %struct.baz*, align 8
   %a.addr = alloca i32, align 4
   store %struct.baz* %this, %struct.baz** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.baz** %this.addr, metadata !70, metadata !{!"0x102"}), !dbg !71
+  call void @llvm.dbg.declare(metadata %struct.baz** %this.addr, metadata !70, metadata !DIExpression()), !dbg !71
   store i32 %a, i32* %a.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !72, metadata !{!"0x102"}), !dbg !73
-  %this1 = load %struct.baz** %this.addr
-  %0 = load i32* %a.addr, align 4, !dbg !74
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !72, metadata !DIExpression()), !dbg !73
+  %this1 = load %struct.baz*, %struct.baz** %this.addr
+  %0 = load i32, i32* %a.addr, align 4, !dbg !74
   call void @_ZN3bazC2Ei(%struct.baz* %this1, i32 %0), !dbg !74
   ret void, !dbg !74
 }
@@ -76,12 +76,12 @@ entry:
   %this.addr = alloca %struct.baz*, align 8
   %a.addr = alloca i32, align 4
   store %struct.baz* %this, %struct.baz** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.baz** %this.addr, metadata !75, metadata !{!"0x102"}), !dbg !76
+  call void @llvm.dbg.declare(metadata %struct.baz** %this.addr, metadata !75, metadata !DIExpression()), !dbg !76
   store i32 %a, i32* %a.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !77, metadata !{!"0x102"}), !dbg !78
-  %this1 = load %struct.baz** %this.addr
-  %h = getelementptr inbounds %struct.baz* %this1, i32 0, i32 0, !dbg !79
-  %0 = load i32* %a.addr, align 4, !dbg !79
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !77, metadata !DIExpression()), !dbg !78
+  %this1 = load %struct.baz*, %struct.baz** %this.addr
+  %h = getelementptr inbounds %struct.baz, %struct.baz* %this1, i32 0, i32 0, !dbg !79
+  %0 = load i32, i32* %a.addr, align 4, !dbg !79
   store i32 %0, i32* %h, align 4, !dbg !79
   ret void, !dbg !80
 }
@@ -89,78 +89,78 @@ entry:
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!83}
 
-!0 = !{!"0x11\004\00clang version 3.1 (trunk 146596)\000\00\000\00\000", !82, !1, !3, !27, !1,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.1 (trunk 146596)", isOptimized: false, emissionKind: 0, file: !82, enums: !1, retainedTypes: !3, subprograms: !27, globals: !1, imports:  !1)
 !1 = !{}
 !3 = !{!5, !9}
-!5 = !{!"0x2\00bar\009\00128\0064\000\000\000", !82, null, null, !7, null, null, null} ; [ DW_TAG_class_type ] [bar] [line 9, size 128, align 64, offset 0] [def] [from ]
-!6 = !{!"0x29", !82} ; [ DW_TAG_file_type ]
+!5 = !DICompositeType(tag: DW_TAG_class_type, name: "bar", line: 9, size: 128, align: 64, file: !82, elements: !7)
+!6 = !DIFile(filename: "main.cpp", directory: "/Users/echristo/tmp/bad-struct-ref")
 !7 = !{!8, !19, !21}
-!8 = !{!"0xd\00b\0011\0032\0032\000\000", !82, !5, !9} ; [ DW_TAG_member ]
-!9 = !{!"0x2\00baz\003\0032\0032\000\000\000", !82, null, null, !10, null, null, null} ; [ DW_TAG_class_type ] [baz] [line 3, size 32, align 32, offset 0] [def] [from ]
+!8 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 11, size: 32, align: 32, file: !82, scope: !5, baseType: !9)
+!9 = !DICompositeType(tag: DW_TAG_class_type, name: "baz", line: 3, size: 32, align: 32, file: !82, elements: !10)
 !10 = !{!11, !13}
-!11 = !{!"0xd\00h\005\0032\0032\000\000", !82, !9, !12} ; [ DW_TAG_member ]
-!12 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!13 = !{!"0x2e\00baz\00baz\00\006\000\000\000\006\00256\000\000", !82, !9, !14, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ]
-!14 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !15, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!11 = !DIDerivedType(tag: DW_TAG_member, name: "h", line: 5, size: 32, align: 32, file: !82, scope: !9, baseType: !12)
+!12 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!13 = !DISubprogram(name: "baz", line: 6, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !82, scope: !9, type: !14)
+!14 = !DISubroutineType(types: !15)
 !15 = !{null, !16, !12}
-!16 = !{!"0xf\00\000\0064\0064\000\0064", i32 0, null, !9} ; [ DW_TAG_pointer_type ]
-!19 = !{!"0xd\00b_ref\0012\0064\0064\0064\000", !82, !5, !20} ; [ DW_TAG_member ]
-!20 = !{!"0x10\00\000\000\000\000\000", null, null, !9} ; [ DW_TAG_reference_type ]
-!21 = !{!"0x2e\00bar\00bar\00\0013\000\000\000\006\00256\000\000", !82, !5, !22, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ]
-!22 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !23, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!16 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, baseType: !9)
+!19 = !DIDerivedType(tag: DW_TAG_member, name: "b_ref", line: 12, size: 64, align: 64, offset: 64, file: !82, scope: !5, baseType: !20)
+!20 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !9)
+!21 = !DISubprogram(name: "bar", line: 13, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !82, scope: !5, type: !22)
+!22 = !DISubroutineType(types: !23)
 !23 = !{null, !24, !12}
-!24 = !{!"0xf\00\000\0064\0064\000\0064", i32 0, null, !5} ; [ DW_TAG_pointer_type ]
+!24 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, baseType: !5)
 !27 = !{!29, !37, !40, !43, !46}
-!29 = !{!"0x2e\00main\00main\00\0017\000\001\000\006\00256\000\000", !82, !6, !30, null, i32 (i32, i8**)* @main, null, null, null} ; [ DW_TAG_subprogram ] [line 17] [def] [scope 0] [main]
-!30 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !31, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!29 = !DISubprogram(name: "main", line: 17, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !82, scope: !6, type: !30, function: i32 (i32, i8**)* @main)
+!30 = !DISubroutineType(types: !31)
 !31 = !{!12, !12, !32}
-!32 = !{!"0xf\00\000\0064\0064\000\000", null, null, !33} ; [ DW_TAG_pointer_type ]
-!33 = !{!"0xf\00\000\0064\0064\000\000", null, null, !34} ; [ DW_TAG_pointer_type ]
-!34 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ]
+!32 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !33)
+!33 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !34)
+!34 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
 !35 = !{!36}
-!36 = !{!"0x24"}                      ; [ DW_TAG_base_type ]
-!37 = !{!"0x2e\00bar\00bar\00_ZN3barC1Ei\0013\000\001\000\006\00256\000\000", !82, null, !22, null, void (%struct.bar*, i32)* @_ZN3barC1Ei, null, !21, null} ; [ DW_TAG_subprogram ] [line 13] [def] [scope 0] [bar]
+!36 = !{} ; previously: invalid DW_TAG_base_type
+!37 = !DISubprogram(name: "bar", linkageName: "_ZN3barC1Ei", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !82, scope: null, type: !22, function: void (%struct.bar*, i32)* @_ZN3barC1Ei, declaration: !21)
 !38 = !{!39}
-!39 = !{!"0x24"}                      ; [ DW_TAG_base_type ]
-!40 = !{!"0x2e\00bar\00bar\00_ZN3barC2Ei\0013\000\001\000\006\00256\000\000", !82, null, !22, null, void (%struct.bar*, i32)* @_ZN3barC2Ei, null, !21, null} ; [ DW_TAG_subprogram ] [line 13] [def] [scope 0] [bar]
+!39 = !{} ; previously: invalid DW_TAG_base_type
+!40 = !DISubprogram(name: "bar", linkageName: "_ZN3barC2Ei", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !82, scope: null, type: !22, function: void (%struct.bar*, i32)* @_ZN3barC2Ei, declaration: !21)
 !41 = !{!42}
-!42 = !{!"0x24"}                      ; [ DW_TAG_base_type ]
-!43 = !{!"0x2e\00baz\00baz\00_ZN3bazC1Ei\006\000\001\000\006\00256\000\000", !82, null, !14, null, void (%struct.baz*, i32)* @_ZN3bazC1Ei, null, !13, null} ; [ DW_TAG_subprogram ] [line 6] [def] [scope 0] [baz]
+!42 = !{} ; previously: invalid DW_TAG_base_type
+!43 = !DISubprogram(name: "baz", linkageName: "_ZN3bazC1Ei", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !82, scope: null, type: !14, function: void (%struct.baz*, i32)* @_ZN3bazC1Ei, declaration: !13)
 !44 = !{!45}
-!45 = !{!"0x24"}                      ; [ DW_TAG_base_type ]
-!46 = !{!"0x2e\00baz\00baz\00_ZN3bazC2Ei\006\000\001\000\006\00256\000\000", !82, null, !14, null, void (%struct.baz*, i32)* @_ZN3bazC2Ei, null, !13, null} ; [ DW_TAG_subprogram ] [line 6] [def] [scope 0] [baz]
-!49 = !{!"0x101\00argc\0016777232\000", !29, !6, !12} ; [ DW_TAG_arg_variable ]
-!50 = !MDLocation(line: 16, column: 14, scope: !29)
-!51 = !{!"0x101\00argv\0033554448\000", !29, !6, !32} ; [ DW_TAG_arg_variable ]
-!52 = !MDLocation(line: 16, column: 27, scope: !29)
-!53 = !{!"0x100\00myBar\0018\000", !54, !6, !5} ; [ DW_TAG_auto_variable ]
-!54 = !{!"0xb\0017\001\000", !82, !29} ; [ DW_TAG_lexical_block ]
-!55 = !MDLocation(line: 18, column: 9, scope: !54)
-!56 = !MDLocation(line: 18, column: 17, scope: !54)
-!57 = !MDLocation(line: 19, column: 5, scope: !54)
-!58 = !{!"0x101\00this\0016777229\0064", !37, !6, !24} ; [ DW_TAG_arg_variable ]
-!59 = !MDLocation(line: 13, column: 5, scope: !37)
-!60 = !{!"0x101\00x\0033554445\000", !37, !6, !12} ; [ DW_TAG_arg_variable ]
-!61 = !MDLocation(line: 13, column: 13, scope: !37)
-!62 = !MDLocation(line: 13, column: 34, scope: !37)
-!63 = !{!"0x101\00this\0016777229\0064", !40, !6, !24} ; [ DW_TAG_arg_variable ]
-!64 = !MDLocation(line: 13, column: 5, scope: !40)
-!65 = !{!"0x101\00x\0033554445\000", !40, !6, !12} ; [ DW_TAG_arg_variable ]
-!66 = !MDLocation(line: 13, column: 13, scope: !40)
-!67 = !MDLocation(line: 13, column: 33, scope: !40)
-!68 = !MDLocation(line: 13, column: 34, scope: !69)
-!69 = !{!"0xb\0013\0033\001", !82, !40} ; [ DW_TAG_lexical_block ]
-!70 = !{!"0x101\00this\0016777222\0064", !43, !6, !16} ; [ DW_TAG_arg_variable ]
-!71 = !MDLocation(line: 6, column: 5, scope: !43)
-!72 = !{!"0x101\00a\0033554438\000", !43, !6, !12} ; [ DW_TAG_arg_variable ]
-!73 = !MDLocation(line: 6, column: 13, scope: !43)
-!74 = !MDLocation(line: 6, column: 24, scope: !43)
-!75 = !{!"0x101\00this\0016777222\0064", !46, !6, !16} ; [ DW_TAG_arg_variable ]
-!76 = !MDLocation(line: 6, column: 5, scope: !46)
-!77 = !{!"0x101\00a\0033554438\000", !46, !6, !12} ; [ DW_TAG_arg_variable ]
-!78 = !MDLocation(line: 6, column: 13, scope: !46)
-!79 = !MDLocation(line: 6, column: 23, scope: !46)
-!80 = !MDLocation(line: 6, column: 24, scope: !81)
-!81 = !{!"0xb\006\0023\002", !82, !46} ; [ DW_TAG_lexical_block ]
-!82 = !{!"main.cpp", !"/Users/echristo/tmp/bad-struct-ref"}
-!83 = !{i32 1, !"Debug Info Version", i32 2}
+!45 = !{} ; previously: invalid DW_TAG_base_type
+!46 = !DISubprogram(name: "baz", linkageName: "_ZN3bazC2Ei", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !82, scope: null, type: !14, function: void (%struct.baz*, i32)* @_ZN3bazC2Ei, declaration: !13)
+!49 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 16, arg: 1, scope: !29, file: !6, type: !12)
+!50 = !DILocation(line: 16, column: 14, scope: !29)
+!51 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 16, arg: 2, scope: !29, file: !6, type: !32)
+!52 = !DILocation(line: 16, column: 27, scope: !29)
+!53 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "myBar", line: 18, scope: !54, file: !6, type: !5)
+!54 = distinct !DILexicalBlock(line: 17, column: 1, file: !82, scope: !29)
+!55 = !DILocation(line: 18, column: 9, scope: !54)
+!56 = !DILocation(line: 18, column: 17, scope: !54)
+!57 = !DILocation(line: 19, column: 5, scope: !54)
+!58 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 13, arg: 1, flags: DIFlagArtificial, scope: !37, file: !6, type: !24)
+!59 = !DILocation(line: 13, column: 5, scope: !37)
+!60 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 13, arg: 2, scope: !37, file: !6, type: !12)
+!61 = !DILocation(line: 13, column: 13, scope: !37)
+!62 = !DILocation(line: 13, column: 34, scope: !37)
+!63 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 13, arg: 1, flags: DIFlagArtificial, scope: !40, file: !6, type: !24)
+!64 = !DILocation(line: 13, column: 5, scope: !40)
+!65 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 13, arg: 2, scope: !40, file: !6, type: !12)
+!66 = !DILocation(line: 13, column: 13, scope: !40)
+!67 = !DILocation(line: 13, column: 33, scope: !40)
+!68 = !DILocation(line: 13, column: 34, scope: !69)
+!69 = distinct !DILexicalBlock(line: 13, column: 33, file: !82, scope: !40)
+!70 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 6, arg: 1, flags: DIFlagArtificial, scope: !43, file: !6, type: !16)
+!71 = !DILocation(line: 6, column: 5, scope: !43)
+!72 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 6, arg: 2, scope: !43, file: !6, type: !12)
+!73 = !DILocation(line: 6, column: 13, scope: !43)
+!74 = !DILocation(line: 6, column: 24, scope: !43)
+!75 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 6, arg: 1, flags: DIFlagArtificial, scope: !46, file: !6, type: !16)
+!76 = !DILocation(line: 6, column: 5, scope: !46)
+!77 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 6, arg: 2, scope: !46, file: !6, type: !12)
+!78 = !DILocation(line: 6, column: 13, scope: !46)
+!79 = !DILocation(line: 6, column: 23, scope: !46)
+!80 = !DILocation(line: 6, column: 24, scope: !81)
+!81 = distinct !DILexicalBlock(line: 6, column: 23, file: !82, scope: !46)
+!82 = !DIFile(filename: "main.cpp", directory: "/Users/echristo/tmp/bad-struct-ref")
+!83 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/DW_AT_byte_size.ll b/test/DebugInfo/X86/DW_AT_byte_size.ll
index 8b4f5611c170..bfad4fe261db 100644
--- a/test/DebugInfo/X86/DW_AT_byte_size.ll
+++ b/test/DebugInfo/X86/DW_AT_byte_size.ll
@@ -14,10 +14,10 @@ define i32 @_Z3fooP1A(%struct.A* %a) nounwind uwtable ssp {
 entry:
   %a.addr = alloca %struct.A*, align 8
   store %struct.A* %a, %struct.A** %a.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.A** %a.addr, metadata !16, metadata !{!"0x102"}), !dbg !17
-  %0 = load %struct.A** %a.addr, align 8, !dbg !18
-  %b = getelementptr inbounds %struct.A* %0, i32 0, i32 0, !dbg !18
-  %1 = load i32* %b, align 4, !dbg !18
+  call void @llvm.dbg.declare(metadata %struct.A** %a.addr, metadata !16, metadata !DIExpression()), !dbg !17
+  %0 = load %struct.A*, %struct.A** %a.addr, align 8, !dbg !18
+  %b = getelementptr inbounds %struct.A, %struct.A* %0, i32 0, i32 0, !dbg !18
+  %1 = load i32, i32* %b, align 4, !dbg !18
   ret i32 %1, !dbg !18
 }
 
@@ -26,21 +26,21 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!21}
 
-!0 = !{!"0x11\004\00clang version 3.1 (trunk 150996)\000\00\000\00\000", !20, !1, !1, !3, !1,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.1 (trunk 150996)", isOptimized: false, emissionKind: 0, file: !20, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00foo\00foo\00_Z3fooP1A\003\000\001\000\006\00256\000\003", !20, !6, !7, null, i32 (%struct.A*)* @_Z3fooP1A, null, null, null} ; [ DW_TAG_subprogram ]
-!6 = !{!"0x29", !20} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "foo", linkageName: "_Z3fooP1A", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !20, scope: !6, type: !7, function: i32 (%struct.A*)* @_Z3fooP1A)
+!6 = !DIFile(filename: "foo.cpp", directory: "/Users/echristo")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !10}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!10 = !{!"0xf\00\000\0064\0064\000\000", null, null, !11} ; [ DW_TAG_pointer_type ]
-!11 = !{!"0x2\00A\001\0032\0032\000\000\000", !20, null, null, !12, null, null, null} ; [ DW_TAG_class_type ] [A] [line 1, size 32, align 32, offset 0] [def] [from ]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !11)
+!11 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 1, size: 32, align: 32, file: !20, elements: !12)
 !12 = !{!13}
-!13 = !{!"0xd\00b\001\0032\0032\000\000", !20, !11, !9} ; [ DW_TAG_member ]
-!16 = !{!"0x101\00a\0016777219\000", !5, !6, !10} ; [ DW_TAG_arg_variable ]
-!17 = !MDLocation(line: 3, column: 13, scope: !5)
-!18 = !MDLocation(line: 4, column: 3, scope: !19)
-!19 = !{!"0xb\003\0016\000", !20, !5} ; [ DW_TAG_lexical_block ]
-!20 = !{!"foo.cpp", !"/Users/echristo"}
-!21 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 1, size: 32, align: 32, file: !20, scope: !11, baseType: !9)
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 3, arg: 1, scope: !5, file: !6, type: !10)
+!17 = !DILocation(line: 3, column: 13, scope: !5)
+!18 = !DILocation(line: 4, column: 3, scope: !19)
+!19 = distinct !DILexicalBlock(line: 3, column: 16, file: !20, scope: !5)
+!20 = !DIFile(filename: "foo.cpp", directory: "/Users/echristo")
+!21 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/DW_AT_linkage_name.ll b/test/DebugInfo/X86/DW_AT_linkage_name.ll
index e395e0619736..7f18b5037d5a 100644
--- a/test/DebugInfo/X86/DW_AT_linkage_name.ll
+++ b/test/DebugInfo/X86/DW_AT_linkage_name.ll
@@ -38,8 +38,8 @@ define void @_ZN1AD2Ev(%struct.A* %this) unnamed_addr #0 align 2 {
 entry:
   %this.addr = alloca %struct.A*, align 8
   store %struct.A* %this, %struct.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.A** %this.addr, metadata !26, metadata !{!"0x102"}), !dbg !28
-  %this1 = load %struct.A** %this.addr
+  call void @llvm.dbg.declare(metadata %struct.A** %this.addr, metadata !26, metadata !DIExpression()), !dbg !28
+  %this1 = load %struct.A*, %struct.A** %this.addr
   ret void, !dbg !29
 }
 
@@ -51,8 +51,8 @@ define void @_ZN1AD1Ev(%struct.A* %this) unnamed_addr #0 align 2 {
 entry:
   %this.addr = alloca %struct.A*, align 8
   store %struct.A* %this, %struct.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.A** %this.addr, metadata !30, metadata !{!"0x102"}), !dbg !31
-  %this1 = load %struct.A** %this.addr
+  call void @llvm.dbg.declare(metadata %struct.A** %this.addr, metadata !30, metadata !DIExpression()), !dbg !31
+  %this1 = load %struct.A*, %struct.A** %this.addr
   call void @_ZN1AD2Ev(%struct.A* %this1), !dbg !32
   ret void, !dbg !33
 }
@@ -61,7 +61,7 @@ entry:
 define void @_Z3foov() #2 {
 entry:
   %a = alloca %struct.A, align 1
-  call void @llvm.dbg.declare(metadata %struct.A* %a, metadata !34, metadata !{!"0x102"}), !dbg !35
+  call void @llvm.dbg.declare(metadata %struct.A* %a, metadata !34, metadata !DIExpression()), !dbg !35
   call void @_ZN1AC1Ei(%struct.A* %a, i32 1), !dbg !35
   call void @_ZN1AD1Ev(%struct.A* %a), !dbg !36
   ret void, !dbg !36
@@ -77,40 +77,38 @@ attributes #2 = { ssp uwtable }
 !llvm.module.flags = !{!23, !24}
 !llvm.ident = !{!25}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !3, !16, !2, !2} ; [ DW_TAG_compile_unit ] [linkage-name.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"linkage-name.cpp", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !16, globals: !2, imports: !2)
+!1 = !DIFile(filename: "linkage-name.cpp", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00A\001\008\008\000\000\000", !1, null, null, !5, null, null, !"_ZTS1A"} ; [ DW_TAG_structure_type ] [A] [line 1, size 8, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "A", line: 1, size: 8, align: 8, file: !1, elements: !5, identifier: "_ZTS1A")
 !5 = !{!6, !12}
-!6 = !{!"0x2e\00A\00A\00\002\000\000\000\006\00256\000\002", !1, !"_ZTS1A", !7, null, null, null, i32 0, !11} ; [ DW_TAG_subprogram ] [line 2] [A]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DISubprogram(name: "A", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !"_ZTS1A", type: !7)
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9, !10}
-!9 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1A]
-!10 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!11 = !{i32 786468}
-!12 = !{!"0x2e\00~A\00~A\00\003\000\000\000\006\00256\000\003", !1, !"_ZTS1A", !13, null, null, null, i32 0, !15} ; [ DW_TAG_subprogram ] [line 3] [~A]
-!13 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !14, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1A")
+!10 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!12 = !DISubprogram(name: "~A", line: 3, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !"_ZTS1A", type: !13)
+!13 = !DISubroutineType(types: !14)
 !14 = !{null, !9}
-!15 = !{i32 786468}
 !16 = !{!17, !18, !19}
-!17 = !{!"0x2e\00~A\00~A\00_ZN1AD2Ev\006\000\001\000\006\00256\000\006", !1, !"_ZTS1A", !13, null, void (%struct.A*)* @_ZN1AD2Ev, null, !12, !2} ; [ DW_TAG_subprogram ] [line 6] [def] [~A]
-!18 = !{!"0x2e\00~A\00~A\00_ZN1AD1Ev\006\000\001\000\006\00256\000\006", !1, !"_ZTS1A", !13, null, void (%struct.A*)* @_ZN1AD1Ev, null, !12, !2} ; [ DW_TAG_subprogram ] [line 6] [def] [~A]
-!19 = !{!"0x2e\00foo\00foo\00_Z3foov\0010\000\001\000\006\00256\000\0010", !1, !20, !21, null, void ()* @_Z3foov, null, null, !2} ; [ DW_TAG_subprogram ] [line 10] [def] [foo]
-!20 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [linkage-name.cpp]
-!21 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !22, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!17 = !DISubprogram(name: "~A", linkageName: "_ZN1AD2Ev", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 6, file: !1, scope: !"_ZTS1A", type: !13, function: void (%struct.A*)* @_ZN1AD2Ev, declaration: !12, variables: !2)
+!18 = !DISubprogram(name: "~A", linkageName: "_ZN1AD1Ev", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 6, file: !1, scope: !"_ZTS1A", type: !13, function: void (%struct.A*)* @_ZN1AD1Ev, declaration: !12, variables: !2)
+!19 = !DISubprogram(name: "foo", linkageName: "_Z3foov", line: 10, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 10, file: !1, scope: !20, type: !21, function: void ()* @_Z3foov, variables: !2)
+!20 = !DIFile(filename: "linkage-name.cpp", directory: "")
+!21 = !DISubroutineType(types: !22)
 !22 = !{null}
 !23 = !{i32 2, !"Dwarf Version", i32 2}
-!24 = !{i32 1, !"Debug Info Version", i32 2}
+!24 = !{i32 1, !"Debug Info Version", i32 3}
 !25 = !{!"clang version 3.5.0 "}
-!26 = !{!"0x101\00this\0016777216\001088", !17, null, !27} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!27 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1A]
-!28 = !MDLocation(line: 0, scope: !17)
-!29 = !MDLocation(line: 8, scope: !17)
-!30 = !{!"0x101\00this\0016777216\001088", !18, null, !27} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!31 = !MDLocation(line: 0, scope: !18)
-!32 = !MDLocation(line: 6, scope: !18)
-!33 = !MDLocation(line: 8, scope: !18)
-!34 = !{!"0x100\00a\0011\000", !19, !20, !"_ZTS1A"} ; [ DW_TAG_auto_variable ] [a] [line 11]
-!35 = !MDLocation(line: 11, scope: !19)
-!36 = !MDLocation(line: 12, scope: !19)
+!26 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !17, type: !27)
+!27 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1A")
+!28 = !DILocation(line: 0, scope: !17)
+!29 = !DILocation(line: 8, scope: !17)
+!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !18, type: !27)
+!31 = !DILocation(line: 0, scope: !18)
+!32 = !DILocation(line: 6, scope: !18)
+!33 = !DILocation(line: 8, scope: !18)
+!34 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 11, scope: !19, file: !20, type: !"_ZTS1A")
+!35 = !DILocation(line: 11, scope: !19)
+!36 = !DILocation(line: 12, scope: !19)
diff --git a/test/DebugInfo/X86/DW_AT_location-reference.ll b/test/DebugInfo/X86/DW_AT_location-reference.ll
index a5b5700ca700..96d1e5099574 100644
--- a/test/DebugInfo/X86/DW_AT_location-reference.ll
+++ b/test/DebugInfo/X86/DW_AT_location-reference.ll
@@ -64,7 +64,7 @@ define void @f() nounwind {
 entry:
   %call = tail call i32 @g(i32 0, i32 0) nounwind, !dbg !8
   store i32 %call, i32* @a, align 4, !dbg !8
-  tail call void @llvm.dbg.value(metadata i32 1, i64 0, metadata !5, metadata !{!"0x102"}), !dbg !13
+  tail call void @llvm.dbg.value(metadata i32 1, i64 0, metadata !5, metadata !DIExpression()), !dbg !13
   br label %while.body
 
 while.body:                                       ; preds = %entry, %while.body
@@ -75,10 +75,10 @@ while.body:                                       ; preds = %entry, %while.body
   br i1 %tobool, label %while.end, label %while.body, !dbg !14
 
 while.end:                                        ; preds = %while.body
-  tail call void @llvm.dbg.value(metadata i32 %mul, i64 0, metadata !5, metadata !{!"0x102"}), !dbg !14
+  tail call void @llvm.dbg.value(metadata i32 %mul, i64 0, metadata !5, metadata !DIExpression()), !dbg !14
   %call4 = tail call i32 @g(i32 %mul, i32 0) nounwind, !dbg !15
   store i32 %call4, i32* @a, align 4, !dbg !15
-  tail call void @llvm.dbg.value(metadata i32 2, i64 0, metadata !5, metadata !{!"0x102"}), !dbg !17
+  tail call void @llvm.dbg.value(metadata i32 2, i64 0, metadata !5, metadata !DIExpression()), !dbg !17
   br label %while.body9
 
 while.body9:                                      ; preds = %while.end, %while.body9
@@ -89,7 +89,7 @@ while.body9:                                      ; preds = %while.end, %while.b
   br i1 %tobool8, label %while.end13, label %while.body9, !dbg !18
 
 while.end13:                                      ; preds = %while.body9
-  tail call void @llvm.dbg.value(metadata i32 %mul12, i64 0, metadata !5, metadata !{!"0x102"}), !dbg !18
+  tail call void @llvm.dbg.value(metadata i32 %mul12, i64 0, metadata !5, metadata !DIExpression()), !dbg !18
   %call15 = tail call i32 @g(i32 0, i32 %mul12) nounwind, !dbg !19
   store i32 %call15, i32* @a, align 4, !dbg !19
   ret void, !dbg !20
@@ -102,25 +102,25 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!24}
 
-!0 = !{!"0x2e\00f\00f\00\004\000\001\000\006\00256\001\004", !23, !1, !3, null, void ()* @f, null, null, !22} ; [ DW_TAG_subprogram ] [line 4] [def] [f]
-!1 = !{!"0x29", !23} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 3.0 (trunk)\001\00\000\00\001", !23, !4, !4, !21, null,  null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !23, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "f", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 4, file: !23, scope: !1, type: !3, function: void ()* @f, variables: !22)
+!1 = !DIFile(filename: "simple.c", directory: "/home/rengol01/temp/tests/dwarf/relocation")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk)", isOptimized: true, emissionKind: 1, file: !23, enums: !{}, retainedTypes: !{}, subprograms: !21, imports:  null)
+!3 = !DISubroutineType(types: !4)
 !4 = !{null}
-!5 = !{!"0x100\00x\005\000", !6, !1, !7} ; [ DW_TAG_auto_variable ]
-!6 = !{!"0xb\004\0014\000", !23, !0} ; [ DW_TAG_lexical_block ]
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ]
-!8 = !MDLocation(line: 6, column: 3, scope: !6)
+!5 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 5, scope: !6, file: !1, type: !7)
+!6 = distinct !DILexicalBlock(line: 4, column: 14, file: !23, scope: !0)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DILocation(line: 6, column: 3, scope: !6)
 !12 = !{i32 1}
-!13 = !MDLocation(line: 7, column: 3, scope: !6)
-!14 = !MDLocation(line: 8, column: 3, scope: !6)
-!15 = !MDLocation(line: 9, column: 3, scope: !6)
+!13 = !DILocation(line: 7, column: 3, scope: !6)
+!14 = !DILocation(line: 8, column: 3, scope: !6)
+!15 = !DILocation(line: 9, column: 3, scope: !6)
 !16 = !{i32 2}
-!17 = !MDLocation(line: 10, column: 3, scope: !6)
-!18 = !MDLocation(line: 11, column: 3, scope: !6)
-!19 = !MDLocation(line: 12, column: 3, scope: !6)
-!20 = !MDLocation(line: 13, column: 1, scope: !6)
+!17 = !DILocation(line: 10, column: 3, scope: !6)
+!18 = !DILocation(line: 11, column: 3, scope: !6)
+!19 = !DILocation(line: 12, column: 3, scope: !6)
+!20 = !DILocation(line: 13, column: 1, scope: !6)
 !21 = !{!0}
 !22 = !{!5}
-!23 = !{!"simple.c", !"/home/rengol01/temp/tests/dwarf/relocation"}
-!24 = !{i32 1, !"Debug Info Version", i32 2}
+!23 = !DIFile(filename: "simple.c", directory: "/home/rengol01/temp/tests/dwarf/relocation")
+!24 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/DW_AT_object_pointer.ll b/test/DebugInfo/X86/DW_AT_object_pointer.ll
index 8cff0b87dceb..86d67cae6b0d 100644
--- a/test/DebugInfo/X86/DW_AT_object_pointer.ll
+++ b/test/DebugInfo/X86/DW_AT_object_pointer.ll
@@ -17,11 +17,11 @@ entry:
   %.addr = alloca i32, align 4
   %a = alloca %class.A, align 4
   store i32 %0, i32* %.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %.addr, metadata !36, metadata !{!"0x102"}), !dbg !35
-  call void @llvm.dbg.declare(metadata %class.A* %a, metadata !21, metadata !{!"0x102"}), !dbg !23
+  call void @llvm.dbg.declare(metadata i32* %.addr, metadata !36, metadata !DIExpression()), !dbg !35
+  call void @llvm.dbg.declare(metadata %class.A* %a, metadata !21, metadata !DIExpression()), !dbg !23
   call void @_ZN1AC1Ev(%class.A* %a), !dbg !24
-  %m_a = getelementptr inbounds %class.A* %a, i32 0, i32 0, !dbg !25
-  %1 = load i32* %m_a, align 4, !dbg !25
+  %m_a = getelementptr inbounds %class.A, %class.A* %a, i32 0, i32 0, !dbg !25
+  %1 = load i32, i32* %m_a, align 4, !dbg !25
   ret i32 %1, !dbg !25
 }
 
@@ -31,8 +31,8 @@ define linkonce_odr void @_ZN1AC1Ev(%class.A* %this) unnamed_addr nounwind uwtab
 entry:
   %this.addr = alloca %class.A*, align 8
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !26, metadata !{!"0x102"}), !dbg !28
-  %this1 = load %class.A** %this.addr
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !26, metadata !DIExpression()), !dbg !28
+  %this1 = load %class.A*, %class.A** %this.addr
   call void @_ZN1AC2Ev(%class.A* %this1), !dbg !29
   ret void, !dbg !29
 }
@@ -41,9 +41,9 @@ define linkonce_odr void @_ZN1AC2Ev(%class.A* %this) unnamed_addr nounwind uwtab
 entry:
   %this.addr = alloca %class.A*, align 8
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !30, metadata !{!"0x102"}), !dbg !31
-  %this1 = load %class.A** %this.addr
-  %m_a = getelementptr inbounds %class.A* %this1, i32 0, i32 0, !dbg !32
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !30, metadata !DIExpression()), !dbg !31
+  %this1 = load %class.A*, %class.A** %this.addr
+  %m_a = getelementptr inbounds %class.A, %class.A* %this1, i32 0, i32 0, !dbg !32
   store i32 0, i32* %m_a, align 4, !dbg !32
   ret void, !dbg !34
 }
@@ -51,40 +51,38 @@ entry:
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!38}
 
-!0 = !{!"0x11\004\00clang version 3.2 (trunk 163586) (llvm/trunk 163570)\000\00\000\00\000", !37, !1, !1, !3, !1,  !1} ; [ DW_TAG_compile_unit ] [/Users/echristo/debug-tests/bar.cpp] [DW_LANG_C_plus_plus]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.2 (trunk 163586) (llvm/trunk 163570)", isOptimized: false, emissionKind: 0, file: !37, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports:  !1)
 !1 = !{}
 !3 = !{!5, !10, !20}
-!5 = !{!"0x2e\00foo\00foo\00_Z3fooi\007\000\001\000\006\00256\000\007", !6, !6, !7, null, i32 (i32)* @_Z3fooi, null, null, !1} ; [ DW_TAG_subprogram ] [line 7] [def] [foo]
-!6 = !{!"0x29", !37} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "foo", linkageName: "_Z3fooi", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !6, scope: !6, type: !7, function: i32 (i32)* @_Z3fooi, variables: !1)
+!6 = !DIFile(filename: "bar.cpp", directory: "/Users/echristo/debug-tests")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"0x2e\00A\00A\00_ZN1AC1Ev\003\000\001\000\006\00256\000\003", !6, null, !11, null, void (%class.A*)* @_ZN1AC1Ev, null, !17, !1} ; [ DW_TAG_subprogram ] [line 3] [def] [A]
-!11 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DISubprogram(name: "A", linkageName: "_ZN1AC1Ev", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !6, scope: null, type: !11, function: void (%class.A*)* @_ZN1AC1Ev, declaration: !17, variables: !1)
+!11 = !DISubroutineType(types: !12)
 !12 = !{null, !13}
-!13 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !14} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from A]
-!14 = !{!"0x2\00A\001\0032\0032\000\000\000", !37, null, null, !15, null, null, null} ; [ DW_TAG_class_type ] [A] [line 1, size 32, align 32, offset 0] [def] [from ]
+!13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !14)
+!14 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 1, size: 32, align: 32, file: !37, elements: !15)
 !15 = !{!16, !17}
-!16 = !{!"0xd\00m_a\004\0032\0032\000\000", !37, !14, !9} ; [ DW_TAG_member ] [m_a] [line 4, size 32, align 32, offset 0] [from int]
-!17 = !{!"0x2e\00A\00A\00\003\000\000\000\006\00256\000\003", !6, !14, !11, null, null, null, i32 0, !18} ; [ DW_TAG_subprogram ] [line 3] [A]
-!18 = !{!19}
-!19 = !{!"0x24"}                      ; [ DW_TAG_base_type ] [line 0, size 0, align 0, offset 0]
-!20 = !{!"0x2e\00A\00A\00_ZN1AC2Ev\003\000\001\000\006\00256\000\003", !6, null, !11, null, void (%class.A*)* @_ZN1AC2Ev, null, !17, !1} ; [ DW_TAG_subprogram ] [line 3] [def] [A]
-!21 = !{!"0x100\00a\008\000", !22, !6, !14} ; [ DW_TAG_auto_variable ] [a] [line 8]
-!22 = !{!"0xb\007\0011\000", !6, !5} ; [ DW_TAG_lexical_block ] [/Users/echristo/debug-tests/bar.cpp]
-!23 = !MDLocation(line: 8, column: 5, scope: !22)
-!24 = !MDLocation(line: 8, column: 6, scope: !22)
-!25 = !MDLocation(line: 9, column: 3, scope: !22)
-!26 = !{!"0x101\00this\0016777219\001088", !10, !6, !27} ; [ DW_TAG_arg_variable ] [this] [line 3]
-!27 = !{!"0xf\00\000\0064\0064\000\000", null, null, !14} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from A]
-!28 = !MDLocation(line: 3, column: 3, scope: !10)
-!29 = !MDLocation(line: 3, column: 18, scope: !10)
-!30 = !{!"0x101\00this\0016777219\001088", !20, !6, !27} ; [ DW_TAG_arg_variable ] [this] [line 3]
-!31 = !MDLocation(line: 3, column: 3, scope: !20)
-!32 = !MDLocation(line: 3, column: 9, scope: !33)
-!33 = !{!"0xb\003\007\001", !6, !20} ; [ DW_TAG_lexical_block ] [/Users/echristo/debug-tests/bar.cpp]
-!34 = !MDLocation(line: 3, column: 18, scope: !33)
-!35 = !MDLocation(line: 7, scope: !5)
-!36 = !{!"0x101\00\0016777223\000", !5, !6, !9} ; [ DW_TAG_arg_variable ] [line 7]
-!37 = !{!"bar.cpp", !"/Users/echristo/debug-tests"}
-!38 = !{i32 1, !"Debug Info Version", i32 2}
+!16 = !DIDerivedType(tag: DW_TAG_member, name: "m_a", line: 4, size: 32, align: 32, file: !37, scope: !14, baseType: !9)
+!17 = !DISubprogram(name: "A", line: 3, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !6, scope: !14, type: !11)
+!20 = !DISubprogram(name: "A", linkageName: "_ZN1AC2Ev", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !6, scope: null, type: !11, function: void (%class.A*)* @_ZN1AC2Ev, declaration: !17, variables: !1)
+!21 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 8, scope: !22, file: !6, type: !14)
+!22 = distinct !DILexicalBlock(line: 7, column: 11, file: !6, scope: !5)
+!23 = !DILocation(line: 8, column: 5, scope: !22)
+!24 = !DILocation(line: 8, column: 6, scope: !22)
+!25 = !DILocation(line: 9, column: 3, scope: !22)
+!26 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 3, arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !10, file: !6, type: !27)
+!27 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !14)
+!28 = !DILocation(line: 3, column: 3, scope: !10)
+!29 = !DILocation(line: 3, column: 18, scope: !10)
+!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 3, arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !20, file: !6, type: !27)
+!31 = !DILocation(line: 3, column: 3, scope: !20)
+!32 = !DILocation(line: 3, column: 9, scope: !33)
+!33 = distinct !DILexicalBlock(line: 3, column: 7, file: !6, scope: !20)
+!34 = !DILocation(line: 3, column: 18, scope: !33)
+!35 = !DILocation(line: 7, scope: !5)
+!36 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "", line: 7, arg: 1, scope: !5, file: !6, type: !9)
+!37 = !DIFile(filename: "bar.cpp", directory: "/Users/echristo/debug-tests")
+!38 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/DW_AT_specification.ll b/test/DebugInfo/X86/DW_AT_specification.ll
index ab2075a879d3..993e623c7511 100644
--- a/test/DebugInfo/X86/DW_AT_specification.ll
+++ b/test/DebugInfo/X86/DW_AT_specification.ll
@@ -4,7 +4,7 @@
 ; test that the DW_AT_specification is a back edge in the file.
 
 ; CHECK: DW_TAG_subprogram
-; CHECK-NEXT: DW_AT_MIPS_linkage_name {{.*}} "_ZN3foo3barEv"
+; CHECK-NEXT: DW_AT_linkage_name {{.*}} "_ZN3foo3barEv"
 ; CHECK: DW_TAG_subprogram
 ; CHECK-NOT: DW_TAG
 ; CHECK: DW_AT_specification {{.*}} "_ZN3foo3barEv"
@@ -20,23 +20,23 @@ entry:
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!28}
 
-!0 = !{!"0x11\004\00clang version 3.0 ()\000\00\000\00\000", !27, !1, !1, !3, !18,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.0 ()", isOptimized: false, emissionKind: 0, file: !27, enums: !1, retainedTypes: !1, subprograms: !3, globals: !18, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00bar\00bar\00_ZN3foo3barEv\004\000\001\000\006\00256\000\004", !6, null, !7, null, void ()* @_ZN3foo3barEv, null, !11, null} ; [ DW_TAG_subprogram ] [line 4] [def] [bar]
-!6 = !{!"0x29", !27} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "bar", linkageName: "_ZN3foo3barEv", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !6, scope: null, type: !7, function: void ()* @_ZN3foo3barEv, declaration: !11)
+!6 = !DIFile(filename: "nsNativeAppSupportBase.ii", directory: "/Users/espindola/mozilla-central/obj-x86_64-apple-darwin11.2.0/toolkit/library")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9}
-!9 = !{!"0xf\00\000\0064\0064\000\0064", i32 0, null, !10} ; [ DW_TAG_pointer_type ]
-!10 = !{!"0x13\00foo\001\000\000\000\004\000", !27, null, null, null, null, null, null} ; [ DW_TAG_structure_type ] [foo] [line 1, size 0, align 0, offset 0] [decl] [from ]
-!11 = !{!"0x2e\00bar\00bar\00_ZN3foo3barEv\002\000\000\000\006\00256\000\002", !6, !12, !7, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ]
-!12 = !{!"0x2\00foo\001\008\008\000\000\000", !27, null, null, !13, null, null} ; [ DW_TAG_class_type ]
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo", line: 1, flags: DIFlagFwdDecl, file: !27)
+!11 = !DISubprogram(name: "bar", linkageName: "_ZN3foo3barEv", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !6, scope: !12, type: !7)
+!12 = !DICompositeType(tag: DW_TAG_class_type, name: "foo", line: 1, size: 8, align: 8, file: !27, elements: !13)
 !13 = !{!11}
 !18 = !{!20}
-!20 = !{!"0x34\00x\00x\00\005\001\001", !5, !6, !21, i32* @_ZZN3foo3barEvE1x, null} ; [ DW_TAG_variable ]
-!21 = !{!"0x26\00\000\000\000\000\000", null, null, !22} ; [ DW_TAG_const_type ]
-!22 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!25 = !MDLocation(line: 6, column: 1, scope: !26)
-!26 = !{!"0xb\004\0017\000", !6, !5} ; [ DW_TAG_lexical_block ]
-!27 = !{!"nsNativeAppSupportBase.ii", !"/Users/espindola/mozilla-central/obj-x86_64-apple-darwin11.2.0/toolkit/library"}
-!28 = !{i32 1, !"Debug Info Version", i32 2}
+!20 = !DIGlobalVariable(name: "x", line: 5, isLocal: true, isDefinition: true, scope: !5, file: !6, type: !21, variable: i32* @_ZZN3foo3barEvE1x)
+!21 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !22)
+!22 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!25 = !DILocation(line: 6, column: 1, scope: !26)
+!26 = distinct !DILexicalBlock(line: 4, column: 17, file: !6, scope: !5)
+!27 = !DIFile(filename: "nsNativeAppSupportBase.ii", directory: "/Users/espindola/mozilla-central/obj-x86_64-apple-darwin11.2.0/toolkit/library")
+!28 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/DW_AT_stmt_list_sec_offset.ll b/test/DebugInfo/X86/DW_AT_stmt_list_sec_offset.ll
index 39c334054762..c8e71a26b8fe 100644
--- a/test/DebugInfo/X86/DW_AT_stmt_list_sec_offset.ll
+++ b/test/DebugInfo/X86/DW_AT_stmt_list_sec_offset.ll
@@ -30,15 +30,15 @@ attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"=
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!9, !11}
 
-!0 = !{!"0x11\0012\00clang version 3.4 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [C:\Projects/test.c] [DW_LANG_C99]
-!1 = !{!"test.c", !"C:\5CProjects"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.c", directory: "C:\5CProjects")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00main\00main\00\001\000\001\000\006\000\000\002", !1, !5, !6, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [scope 2] [main]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [C:\Projects/test.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "main", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !6, function: i32 ()* @main, variables: !2)
+!5 = !DIFile(filename: "test.c", directory: "C:CProjects")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 4}
-!10 = !MDLocation(line: 3, scope: !4)
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !DILocation(line: 3, scope: !4)
+!11 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/DW_TAG_friend.ll b/test/DebugInfo/X86/DW_TAG_friend.ll
index ffa032f7cbde..8237c4086d31 100644
--- a/test/DebugInfo/X86/DW_TAG_friend.ll
+++ b/test/DebugInfo/X86/DW_TAG_friend.ll
@@ -18,31 +18,27 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!29}
 
-!0 = !{!"0x11\004\00clang version 3.1 (trunk 153413) (llvm/trunk 153428)\000\00\000\00\000", !28, !1, !1, !1, !3,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.1 (trunk 153413) (llvm/trunk 153428)", isOptimized: false, emissionKind: 0, file: !28, enums: !1, retainedTypes: !1, subprograms: !1, globals: !3, imports:  !1)
 !1 = !{}
 !3 = !{!5, !17}
-!5 = !{!"0x34\00a\00a\00\0010\000\001", null, !6, !7, %class.A* @a, null} ; [ DW_TAG_variable ]
-!6 = !{!"0x29", !28} ; [ DW_TAG_file_type ]
-!7 = !{!"0x2\00A\001\0032\0032\000\000\000", !28, null, null, !8, null, null, null} ; [ DW_TAG_class_type ] [A] [line 1, size 32, align 32, offset 0] [def] [from ]
+!5 = !DIGlobalVariable(name: "a", line: 10, isLocal: false, isDefinition: true, scope: null, file: !6, type: !7, variable: %class.A* @a)
+!6 = !DIFile(filename: "foo.cpp", directory: "/Users/echristo/tmp")
+!7 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 1, size: 32, align: 32, file: !28, elements: !8)
 !8 = !{!9, !11}
-!9 = !{!"0xd\00a\002\0032\0032\000\001", !28, !7, !10} ; [ DW_TAG_member ]
-!10 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!11 = !{!"0x2e\00A\00A\00\001\000\000\000\006\00320\000\001", !6, !7, !12, null, null, null, i32 0, !15} ; [ DW_TAG_subprogram ]
-!12 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !13, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 2, size: 32, align: 32, flags: DIFlagPrivate, file: !28, scope: !7, baseType: !10)
+!10 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!11 = !DISubprogram(name: "A", line: 1, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !6, scope: !7, type: !12)
+!12 = !DISubroutineType(types: !13)
 !13 = !{null, !14}
-!14 = !{!"0xf\00\000\0064\0064\000\0064", i32 0, null, !7} ; [ DW_TAG_pointer_type ]
-!15 = !{!16}
-!16 = !{!"0x24"}                      ; [ DW_TAG_base_type ]
-!17 = !{!"0x34\00b\00b\00\0011\000\001", null, !6, !18, %class.B* @b, null} ; [ DW_TAG_variable ]
-!18 = !{!"0x2\00B\005\0032\0032\000\000\000", !28, null, null, !19, null, null, null} ; [ DW_TAG_class_type ] [B] [line 5, size 32, align 32, offset 0] [def] [from ]
+!14 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, baseType: !7)
+!17 = !DIGlobalVariable(name: "b", line: 11, isLocal: false, isDefinition: true, scope: null, file: !6, type: !18, variable: %class.B* @b)
+!18 = !DICompositeType(tag: DW_TAG_class_type, name: "B", line: 5, size: 32, align: 32, file: !28, elements: !19)
 !19 = !{!20, !21, !27}
-!20 = !{!"0xd\00b\007\0032\0032\000\001", !28, !18, !10} ; [ DW_TAG_member ]
-!21 = !{!"0x2e\00B\00B\00\005\000\000\000\006\00320\000\005", !6, !18, !22, null, null, null, i32 0, !25} ; [ DW_TAG_subprogram ]
-!22 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !23, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!20 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 7, size: 32, align: 32, flags: DIFlagPrivate, file: !28, scope: !18, baseType: !10)
+!21 = !DISubprogram(name: "B", line: 5, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !6, scope: !18, type: !22)
+!22 = !DISubroutineType(types: !23)
 !23 = !{null, !24}
-!24 = !{!"0xf\00\000\0064\0064\000\0064", i32 0, null, !18} ; [ DW_TAG_pointer_type ]
-!25 = !{!26}
-!26 = !{!"0x24"}                      ; [ DW_TAG_base_type ]
-!27 = !{!"0x2a\00\000\000\000\000\000", !18, null, !7} ; [ DW_TAG_friend ]
-!28 = !{!"foo.cpp", !"/Users/echristo/tmp"}
-!29 = !{i32 1, !"Debug Info Version", i32 2}
+!24 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, baseType: !18)
+!27 = !DIDerivedType(tag: DW_TAG_friend, file: !28, baseType: !7)
+!28 = !DIFile(filename: "foo.cpp", directory: "/Users/echristo/tmp")
+!29 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/InlinedFnLocalVar.ll b/test/DebugInfo/X86/InlinedFnLocalVar.ll
new file mode 100644
index 000000000000..74de8b6e6a92
--- /dev/null
+++ b/test/DebugInfo/X86/InlinedFnLocalVar.ll
@@ -0,0 +1,61 @@
+; RUN: llc -mtriple i686-pc-cygwin -O2 %s -o - | FileCheck %s
+; Check struct X for dead variable xyz from inlined function foo.
+
+; CHECK: Lsection_info
+; CHECK:	DW_TAG_structure_type
+; CHECK-NEXT:	info_string
+ 
+
+@i = common global i32 0                          ; <i32*> [#uses=2]
+
+declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
+
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone
+
+define i32 @bar() nounwind ssp {
+entry:
+  %0 = load i32, i32* @i, align 4, !dbg !17            ; <i32> [#uses=2]
+  tail call void @llvm.dbg.value(metadata i32 %0, i64 0, metadata !109, metadata !DIExpression()), !dbg !19
+  tail call void @llvm.dbg.declare(metadata !29, metadata !110, metadata !DIExpression()), !dbg !21
+  %1 = mul nsw i32 %0, %0, !dbg !22               ; <i32> [#uses=2]
+  store i32 %1, i32* @i, align 4, !dbg !17
+  ret i32 %1, !dbg !23
+}
+
+!llvm.dbg.cu = !{!2}
+!llvm.module.flags = !{!28}
+
+!0 = !DISubprogram(name: "foo", line: 9, isLocal: true, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 9, file: !27, scope: !1, type: !3, variables: !24)
+!1 = !DIFile(filename: "bar.c", directory: "/tmp/")
+!2 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 0, file: !27, enums: !20, retainedTypes: !20, subprograms: !25, globals: !26, imports:  !20)
+!3 = !DISubroutineType(types: !4)
+!4 = !{!5, !5}
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DISubprogram(name: "bar", linkageName: "bar", line: 14, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, file: !27, scope: !1, type: !7, function: i32 ()* @bar)
+!7 = !DISubroutineType(types: !8)
+!8 = !{!5}
+!9 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "j", line: 9, arg: 0, scope: !0, file: !1, type: !5)
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xyz", line: 10, scope: !11, file: !1, type: !12)
+
+!109 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "j", line: 9, arg: 0, scope: !0, file: !1, type: !5)
+!110 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xyz", line: 10, scope: !11, file: !1, type: !12)
+
+!11 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !0)
+!12 = !DICompositeType(tag: DW_TAG_structure_type, name: "X", line: 10, size: 64, align: 32, file: !27, scope: !0, elements: !13)
+!13 = !{!14, !15}
+!14 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 10, size: 32, align: 32, file: !27, scope: !12, baseType: !5)
+!15 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 10, size: 32, align: 32, offset: 32, file: !27, scope: !12, baseType: !5)
+!16 = !DIGlobalVariable(name: "i", line: 5, isLocal: false, isDefinition: true, scope: !1, file: !1, type: !5, variable: i32* @i)
+!17 = !DILocation(line: 15, scope: !18)
+!18 = distinct !DILexicalBlock(line: 14, column: 0, file: !1, scope: !6)
+!19 = !DILocation(line: 9, scope: !0, inlinedAt: !17)
+!20 = !{}
+!21 = !DILocation(line: 9, scope: !11, inlinedAt: !17)
+!22 = !DILocation(line: 11, scope: !11, inlinedAt: !17)
+!23 = !DILocation(line: 16, scope: !18)
+!24 = !{!9, !10}
+!25 = !{!0, !6}
+!26 = !{!16}
+!27 = !DIFile(filename: "bar.c", directory: "/tmp/")
+!28 = !{i32 1, !"Debug Info Version", i32 3}
+!29 = !{null}
diff --git a/test/DebugInfo/X86/aligned_stack_var.ll b/test/DebugInfo/X86/aligned_stack_var.ll
index 32c6f2449aa0..560125d6f40d 100644
--- a/test/DebugInfo/X86/aligned_stack_var.ll
+++ b/test/DebugInfo/X86/aligned_stack_var.ll
@@ -18,7 +18,7 @@
 define void @_Z3runv() nounwind uwtable {
 entry:
   %x = alloca i32, align 32
-  call void @llvm.dbg.declare(metadata i32* %x, metadata !9, metadata !{!"0x102"}), !dbg !12
+  call void @llvm.dbg.declare(metadata i32* %x, metadata !9, metadata !DIExpression()), !dbg !12
   ret void, !dbg !13
 }
 
@@ -27,17 +27,17 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!15}
 
-!0 = !{!"0x11\004\00clang version 3.2 (trunk 155696:155697) (llvm/trunk 155696)\000\00\000\00\000", !14, !1, !1, !3, !1,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.2 (trunk 155696:155697) (llvm/trunk 155696)", isOptimized: false, emissionKind: 0, file: !14, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00run\00run\00_Z3runv\001\000\001\000\006\00256\000\001", !14, !6, !7, null, void ()* @_Z3runv, null, null, !1} ; [ DW_TAG_subprogram ]
-!6 = !{!"0x29", !14} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "run", linkageName: "_Z3runv", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !14, scope: !6, type: !7, function: void ()* @_Z3runv, variables: !1)
+!6 = !DIFile(filename: "test.cc", directory: "/home/samsonov/debuginfo")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null}
-!9 = !{!"0x100\00x\002\000", !10, !6, !11} ; [ DW_TAG_auto_variable ]
-!10 = !{!"0xb\001\0012\000", !14, !5} ; [ DW_TAG_lexical_block ]
-!11 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!12 = !MDLocation(line: 2, column: 7, scope: !10)
-!13 = !MDLocation(line: 3, column: 1, scope: !10)
-!14 = !{!"test.cc", !"/home/samsonov/debuginfo"}
-!15 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 2, scope: !10, file: !6, type: !11)
+!10 = distinct !DILexicalBlock(line: 1, column: 12, file: !14, scope: !5)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!12 = !DILocation(line: 2, column: 7, scope: !10)
+!13 = !DILocation(line: 3, column: 1, scope: !10)
+!14 = !DIFile(filename: "test.cc", directory: "/home/samsonov/debuginfo")
+!15 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/arange-and-stub.ll b/test/DebugInfo/X86/arange-and-stub.ll
new file mode 100644
index 000000000000..b1ab6b9fc899
--- /dev/null
+++ b/test/DebugInfo/X86/arange-and-stub.ll
@@ -0,0 +1,53 @@
+; RUN: llc -generate-arange-section -relocation-model=pic < %s | FileCheck %s
+
+; CHECK:   .section        .data.rel,"aw",@progbits
+; CHECK-NOT: .section
+; CHECK: .L_ZTId.DW.stub:
+
+; CHECK:  .section        .data.rel,"aw",@progbits
+; CHECK-NEXT: .Lsec_end0:
+
+target triple = "x86_64-linux-gnu"
+
+@_ZTId = external constant i8*
+@zed = global [1 x void ()*] [void ()* @bar]
+
+define void @foo() {
+  ret void
+}
+
+define void @bar() {
+  invoke void @foo()
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %0
+  ret void
+
+lpad:                                             ; preds = %0
+  %tmp1 = landingpad { i8*, i32 } personality i8* bitcast (void ()* @foo to i8*)
+          filter [1 x i8*] [i8* bitcast (i8** @_ZTId to i8*)]
+  ret void
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!17, !18}
+
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 3.7.0 (trunk 234308) (llvm/trunk 234310)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !10, imports: !2)
+!1 = !DIFile(filename: "/Users/espindola/llvm/<stdin>", directory: "/Users/espindola/llvm/build")
+!2 = !{}
+!3 = !{!4, !9}
+!4 = !DISubprogram(name: "foo", linkageName: "foo", scope: !5, file: !5, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, function: void ()* @foo, variables: !2)
+!5 = !DIFile(filename: "/Users/espindola/llvm/test.cpp", directory: "/Users/espindola/llvm/build")
+!6 = !DISubroutineType(types: !7)
+!7 = !{null, !8}
+!8 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DISubprogram(name: "bar_d", linkageName: "bar", scope: !5, file: !5, line: 3, type: !6, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: false, function: void ()* @bar, variables: !2)
+!10 = !{!11}
+!11 = !DIGlobalVariable(name: "zed", scope: !0, file: !5, line: 6, type: !12, isLocal: false, isDefinition: true, variable: [1 x void ()*]* @zed)
+!12 = !DICompositeType(tag: DW_TAG_array_type, baseType: !13, size: 64, align: 64, elements: !15)
+!13 = !DIDerivedType(tag: DW_TAG_typedef, name: "vifunc", file: !5, line: 5, baseType: !14)
+!14 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !6, size: 64, align: 64)
+!15 = !{!16}
+!16 = !DISubrange(count: 1)
+!17 = !{i32 2, !"Dwarf Version", i32 4}
+!18 = !{i32 2, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/arange.ll b/test/DebugInfo/X86/arange.ll
index 97ab3c59e559..0b0c2a0b3ee7 100644
--- a/test/DebugInfo/X86/arange.ll
+++ b/test/DebugInfo/X86/arange.ll
@@ -29,18 +29,18 @@
 !llvm.module.flags = !{!12, !13}
 !llvm.ident = !{!14}
 
-!0 = !{!"0x11\004\00clang version 3.5 \000\00\000\00\000", !1, !2, !3, !2, !9, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/simple.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"simple.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !2, globals: !9, imports: !2)
+!1 = !DIFile(filename: "simple.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00foo<&i>\003\008\008\000\000\000", !1, null, null, !2, null, !5, !"_ZTS3fooIXadL_Z1iEEE"} ; [ DW_TAG_structure_type ] [foo<&i>] [line 3, size 8, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo<&i>", line: 3, size: 8, align: 8, file: !1, elements: !2, templateParams: !5, identifier: "_ZTS3fooIXadL_Z1iEEE")
 !5 = !{!6}
-!6 = !{!"0x30\00x\000\000", null, !7, i32* @i, null} ; [ DW_TAG_template_value_parameter ]
-!7 = !{!"0xf\00\000\0064\0064\000\000", null, null, !8} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!6 = !DITemplateValueParameter(tag: DW_TAG_template_value_parameter, name: "x", type: !7, value: i32* @i)
+!7 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{!10}
-!10 = !{!"0x34\00f\00f\00\006\000\001", null, !11, !4, %struct.foo* @f, null} ; [ DW_TAG_variable ] [f] [line 6] [def]
-!11 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/tmp/dbginfo/simple.cpp]
+!10 = !DIGlobalVariable(name: "f", line: 6, isLocal: false, isDefinition: true, scope: null, file: !11, type: !4, variable: %struct.foo* @f)
+!11 = !DIFile(filename: "simple.cpp", directory: "/tmp/dbginfo")
 !12 = !{i32 2, !"Dwarf Version", i32 4}
-!13 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = !{i32 1, !"Debug Info Version", i32 3}
 !14 = !{!"clang version 3.5 "}
diff --git a/test/DebugInfo/X86/arguments.ll b/test/DebugInfo/X86/arguments.ll
index 2bc56b4e4dae..0af119b241fc 100644
--- a/test/DebugInfo/X86/arguments.ll
+++ b/test/DebugInfo/X86/arguments.ll
@@ -16,7 +16,7 @@
 ; CHECK: debug_info contents
 ; CHECK: DW_TAG_subprogram
 ; CHECK-NOT: DW_TAG
-; CHECK: DW_AT_MIPS_linkage_name{{.*}}"_Z4func3fooS_"
+; CHECK: DW_AT_linkage_name{{.*}}"_Z4func3fooS_"
 ; CHECK-NOT: NULL
 ; CHECK: DW_TAG_formal_parameter
 ; CHECK-NOT: DW_TAG
@@ -31,10 +31,10 @@
 ; Function Attrs: nounwind uwtable
 define void @_Z4func3fooS_(%struct.foo* %f, %struct.foo* %g) #0 {
 entry:
-  call void @llvm.dbg.declare(metadata %struct.foo* %f, metadata !19, metadata !{!"0x102"}), !dbg !20
-  call void @llvm.dbg.declare(metadata %struct.foo* %g, metadata !21, metadata !{!"0x102"}), !dbg !20
-  %i = getelementptr inbounds %struct.foo* %f, i32 0, i32 0, !dbg !22
-  %0 = load i32* %i, align 4, !dbg !22
+  call void @llvm.dbg.declare(metadata %struct.foo* %f, metadata !19, metadata !DIExpression()), !dbg !20
+  call void @llvm.dbg.declare(metadata %struct.foo* %g, metadata !21, metadata !DIExpression()), !dbg !20
+  %i = getelementptr inbounds %struct.foo, %struct.foo* %f, i32 0, i32 0, !dbg !22
+  %0 = load i32, i32* %i, align 4, !dbg !22
   %inc = add nsw i32 %0, 1, !dbg !22
   store i32 %inc, i32* %i, align 4, !dbg !22
   ret void, !dbg !23
@@ -49,28 +49,27 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!24}
 
-!0 = !{!"0x11\004\00clang version 3.4 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/blaikie/dev/scratch/scratch.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"scratch.cpp", !"/usr/local/google/home/blaikie/dev/scratch"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "scratch.cpp", directory: "/usr/local/google/home/blaikie/dev/scratch")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00func\00func\00_Z4func3fooS_\006\000\001\000\006\00256\000\006", !1, !5, !6, null, void (%struct.foo*, %struct.foo*)* @_Z4func3fooS_, null, null, !2} ; [ DW_TAG_subprogram ] [line 6] [def] [func]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/usr/local/google/home/blaikie/dev/scratch/scratch.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "func", linkageName: "_Z4func3fooS_", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 6, file: !1, scope: !5, type: !6, function: void (%struct.foo*, %struct.foo*)* @_Z4func3fooS_, variables: !2)
+!5 = !DIFile(filename: "scratch.cpp", directory: "/usr/local/google/home/blaikie/dev/scratch")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null, !8, !8}
-!8 = !{!"0x13\00foo\001\0032\0032\000\000\000", !1, null, null, !9, null, null, null} ; [ DW_TAG_structure_type ] [foo] [line 1, size 32, align 32, offset 0] [def] [from ]
+!8 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo", line: 1, size: 32, align: 32, file: !1, elements: !9)
 !9 = !{!10, !12}
-!10 = !{!"0xd\00i\003\0032\0032\000\000", !1, !8, !11} ; [ DW_TAG_member ] [i] [line 3, size 32, align 32, offset 0] [from int]
-!11 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!12 = !{!"0x2e\00foo\00foo\00\002\000\000\000\006\00256\000\002", !1, !8, !13, null, null, null, i32 0, !18} ; [ DW_TAG_subprogram ] [line 2] [foo]
-!13 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !14, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!10 = !DIDerivedType(tag: DW_TAG_member, name: "i", line: 3, size: 32, align: 32, file: !1, scope: !8, baseType: !11)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!12 = !DISubprogram(name: "foo", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !8, type: !13)
+!13 = !DISubroutineType(types: !14)
 !14 = !{null, !15, !16}
-!15 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !8} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from foo]
-!16 = !{!"0x10\00\000\000\000\000\000", null, null, !17} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from ]
-!17 = !{!"0x26\00\000\000\000\000\000", null, null, !8} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from foo]
-!18 = !{i32 786468}
-!19 = !{!"0x101\00f\0016777222\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [f] [line 6]
-!20 = !MDLocation(line: 6, scope: !4)
-!21 = !{!"0x101\00g\0033554438\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [g] [line 6]
-!22 = !MDLocation(line: 7, scope: !4)
-!23 = !MDLocation(line: 8, scope: !4)
-!24 = !{i32 1, !"Debug Info Version", i32 2}
+!15 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !8)
+!16 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !17)
+!17 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !8)
+!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "f", line: 6, arg: 1, scope: !4, file: !5, type: !8)
+!20 = !DILocation(line: 6, scope: !4)
+!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "g", line: 6, arg: 2, scope: !4, file: !5, type: !8)
+!22 = !DILocation(line: 7, scope: !4)
+!23 = !DILocation(line: 8, scope: !4)
+!24 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/array.ll b/test/DebugInfo/X86/array.ll
index e39be5ae0ff0..8da2079a0530 100644
--- a/test/DebugInfo/X86/array.ll
+++ b/test/DebugInfo/X86/array.ll
@@ -25,7 +25,7 @@ target triple = "x86_64-apple-macosx10.9.0"
 
 ; Function Attrs: nounwind ssp uwtable
 define void @f(i32* nocapture %p) #0 {
-  tail call void @llvm.dbg.value(metadata i32* %p, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !28
+  tail call void @llvm.dbg.value(metadata i32* %p, i64 0, metadata !11, metadata !DIExpression()), !dbg !28
   store i32 42, i32* %p, align 4, !dbg !29, !tbaa !30
   ret void, !dbg !34
 }
@@ -33,16 +33,16 @@ define void @f(i32* nocapture %p) #0 {
 ; Function Attrs: nounwind ssp uwtable
 define i32 @main(i32 %argc, i8** nocapture readnone %argv) #0 {
   %array = alloca [4 x i32], align 16
-  tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !35
-  tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !20, metadata !{!"0x102"}), !dbg !35
-  tail call void @llvm.dbg.value(metadata [4 x i32]* %array, i64 0, metadata !21, metadata !{!"0x102"}), !dbg !36
+  tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !19, metadata !DIExpression()), !dbg !35
+  tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !20, metadata !DIExpression()), !dbg !35
+  tail call void @llvm.dbg.value(metadata [4 x i32]* %array, i64 0, metadata !21, metadata !DIExpression()), !dbg !36
   %1 = bitcast [4 x i32]* %array to i8*, !dbg !36
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast ([4 x i32]* @main.array to i8*), i64 16, i32 16, i1 false), !dbg !36
-  tail call void @llvm.dbg.value(metadata [4 x i32]* %array, i64 0, metadata !21, metadata !{!"0x102"}), !dbg !36
-  %2 = getelementptr inbounds [4 x i32]* %array, i64 0, i64 0, !dbg !37
+  tail call void @llvm.dbg.value(metadata [4 x i32]* %array, i64 0, metadata !21, metadata !DIExpression()), !dbg !36
+  %2 = getelementptr inbounds [4 x i32], [4 x i32]* %array, i64 0, i64 0, !dbg !37
   call void @f(i32* %2), !dbg !37
-  tail call void @llvm.dbg.value(metadata [4 x i32]* %array, i64 0, metadata !21, metadata !{!"0x102"}), !dbg !36
-  %3 = load i32* %2, align 16, !dbg !38, !tbaa !30
+  tail call void @llvm.dbg.value(metadata [4 x i32]* %array, i64 0, metadata !21, metadata !DIExpression()), !dbg !36
+  %3 = load i32, i32* %2, align 16, !dbg !38, !tbaa !30
   ret i32 %3, !dbg !38
 }
 
@@ -60,42 +60,42 @@ attributes #2 = { nounwind readnone }
 !llvm.module.flags = !{!25, !26}
 !llvm.ident = !{!27}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 \001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/array.c] [DW_LANG_C99]
-!1 = !{!"array.c", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "array.c", directory: "")
 !2 = !{}
 !3 = !{!4, !12}
-!4 = !{!"0x2e\00f\00f\00\001\000\001\000\006\00256\001\001", !1, !5, !6, null, void (i32*)* @f, null, null, !10} ; [ DW_TAG_subprogram ] [line 1] [def] [f]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/array.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "f", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !1, scope: !5, type: !6, function: void (i32*)* @f, variables: !10)
+!5 = !DIFile(filename: "array.c", directory: "")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null, !8}
-!8 = !{!"0xf\00\000\0064\0064\000\000", null, null, !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !9)
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !10 = !{!11}
-!11 = !{!"0x101\00p\0016777217\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [p] [line 1]
-!12 = !{!"0x2e\00main\00main\00\005\000\001\000\006\00256\001\005", !1, !5, !13, null, i32 (i32, i8**)* @main, null, null, !18} ; [ DW_TAG_subprogram ] [line 5] [def] [main]
-!13 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !14, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!11 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p", line: 1, arg: 1, scope: !4, file: !5, type: !8)
+!12 = !DISubprogram(name: "main", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !1, scope: !5, type: !13, function: i32 (i32, i8**)* @main, variables: !18)
+!13 = !DISubroutineType(types: !14)
 !14 = !{!9, !9, !15}
-!15 = !{!"0xf\00\000\0064\0064\000\000", null, null, !16} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!16 = !{!"0xf\00\000\0064\0064\000\000", null, null, !17} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char]
-!17 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
+!15 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !16)
+!16 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !17)
+!17 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
 !18 = !{!19, !20, !21}
-!19 = !{!"0x101\00argc\0016777221\000", !12, !5, !9} ; [ DW_TAG_arg_variable ] [argc] [line 5]
-!20 = !{!"0x101\00argv\0033554437\000", !12, !5, !15} ; [ DW_TAG_arg_variable ] [argv] [line 5]
-!21 = !{!"0x100\00array\006\000", !12, !5, !22} ; [ DW_TAG_auto_variable ] [array] [line 6]
-!22 = !{!"0x1\00\000\00128\0032\000\000", null, null, !9, !23, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 32, offset 0] [from int]
+!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 5, arg: 1, scope: !12, file: !5, type: !9)
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 5, arg: 2, scope: !12, file: !5, type: !15)
+!21 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "array", line: 6, scope: !12, file: !5, type: !22)
+!22 = !DICompositeType(tag: DW_TAG_array_type, size: 128, align: 32, baseType: !9, elements: !23)
 !23 = !{!24}
-!24 = !{!"0x21\000\004"}        ; [ DW_TAG_subrange_type ] [0, 3]
+!24 = !DISubrange(count: 4)
 !25 = !{i32 2, !"Dwarf Version", i32 2}
-!26 = !{i32 1, !"Debug Info Version", i32 2}
+!26 = !{i32 1, !"Debug Info Version", i32 3}
 !27 = !{!"clang version 3.5.0 "}
-!28 = !MDLocation(line: 1, scope: !4)
-!29 = !MDLocation(line: 2, scope: !4)
+!28 = !DILocation(line: 1, scope: !4)
+!29 = !DILocation(line: 2, scope: !4)
 !30 = !{!31, !31, i64 0}
 !31 = !{!"int", !32, i64 0}
 !32 = !{!"omnipotent char", !33, i64 0}
 !33 = !{!"Simple C/C++ TBAA"}
-!34 = !MDLocation(line: 3, scope: !4)
-!35 = !MDLocation(line: 5, scope: !12)
-!36 = !MDLocation(line: 6, scope: !12)
-!37 = !MDLocation(line: 7, scope: !12)
-!38 = !MDLocation(line: 8, scope: !12)
+!34 = !DILocation(line: 3, scope: !4)
+!35 = !DILocation(line: 5, scope: !12)
+!36 = !DILocation(line: 6, scope: !12)
+!37 = !DILocation(line: 7, scope: !12)
+!38 = !DILocation(line: 8, scope: !12)
diff --git a/test/DebugInfo/X86/array2.ll b/test/DebugInfo/X86/array2.ll
index 5b21188c1cfe..e08c52640b3f 100644
--- a/test/DebugInfo/X86/array2.ll
+++ b/test/DebugInfo/X86/array2.ll
@@ -13,12 +13,12 @@
 ; }
 ;
 ; RUN: opt %s -O2 -S -o - | FileCheck %s
-; Test that we do not lower dbg.declares for arrays.
+; Test that we correctly lower dbg.declares for arrays.
 ;
 ; CHECK: define i32 @main
-; CHECK: call void @llvm.dbg.value
-; CHECK: call void @llvm.dbg.value
-; CHECK: call void @llvm.dbg.declare
+; CHECK: call void @llvm.dbg.value(metadata i32 42, i64 0, metadata ![[ARRAY:[0-9]+]], metadata ![[EXPR:[0-9]+]])
+; CHECK: ![[ARRAY]] = !DILocalVariable(tag: DW_TAG_auto_variable, name: "array",{{.*}} line: 6
+; CHECK: ![[EXPR]] = !DIExpression(DW_OP_bit_piece, 0, 32)
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.9.0"
 
@@ -29,9 +29,9 @@ define void @f(i32* %p) #0 {
 entry:
   %p.addr = alloca i32*, align 8
   store i32* %p, i32** %p.addr, align 8
-  call void @llvm.dbg.declare(metadata i32** %p.addr, metadata !19, metadata !{!"0x102"}), !dbg !20
-  %0 = load i32** %p.addr, align 8, !dbg !21
-  %arrayidx = getelementptr inbounds i32* %0, i64 0, !dbg !21
+  call void @llvm.dbg.declare(metadata i32** %p.addr, metadata !19, metadata !DIExpression()), !dbg !20
+  %0 = load i32*, i32** %p.addr, align 8, !dbg !21
+  %arrayidx = getelementptr inbounds i32, i32* %0, i64 0, !dbg !21
   store i32 42, i32* %arrayidx, align 4, !dbg !21
   ret void, !dbg !22
 }
@@ -48,16 +48,16 @@ entry:
   %array = alloca [4 x i32], align 16
   store i32 0, i32* %retval
   store i32 %argc, i32* %argc.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %argc.addr, metadata !23, metadata !{!"0x102"}), !dbg !24
+  call void @llvm.dbg.declare(metadata i32* %argc.addr, metadata !23, metadata !DIExpression()), !dbg !24
   store i8** %argv, i8*** %argv.addr, align 8
-  call void @llvm.dbg.declare(metadata i8*** %argv.addr, metadata !25, metadata !{!"0x102"}), !dbg !24
-  call void @llvm.dbg.declare(metadata [4 x i32]* %array, metadata !26, metadata !{!"0x102"}), !dbg !30
+  call void @llvm.dbg.declare(metadata i8*** %argv.addr, metadata !25, metadata !DIExpression()), !dbg !24
+  call void @llvm.dbg.declare(metadata [4 x i32]* %array, metadata !26, metadata !DIExpression()), !dbg !30
   %0 = bitcast [4 x i32]* %array to i8*, !dbg !30
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast ([4 x i32]* @main.array to i8*), i64 16, i32 16, i1 false), !dbg !30
-  %arraydecay = getelementptr inbounds [4 x i32]* %array, i32 0, i32 0, !dbg !31
+  %arraydecay = getelementptr inbounds [4 x i32], [4 x i32]* %array, i32 0, i32 0, !dbg !31
   call void @f(i32* %arraydecay), !dbg !31
-  %arrayidx = getelementptr inbounds [4 x i32]* %array, i32 0, i64 0, !dbg !32
-  %1 = load i32* %arrayidx, align 4, !dbg !32
+  %arrayidx = getelementptr inbounds [4 x i32], [4 x i32]* %array, i32 0, i64 0, !dbg !32
+  %1 = load i32, i32* %arrayidx, align 4, !dbg !32
   ret i32 %1, !dbg !32
 }
 
@@ -72,36 +72,36 @@ attributes #2 = { nounwind }
 !llvm.module.flags = !{!16, !17}
 !llvm.ident = !{!18}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [array.c] [DW_LANG_C99]
-!1 = !{!"array.c", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "array.c", directory: "")
 !2 = !{}
 !3 = !{!4, !10}
-!4 = !{!"0x2e\00f\00f\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, void (i32*)* @f, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [f]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [array.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "f", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void (i32*)* @f, variables: !2)
+!5 = !DIFile(filename: "array.c", directory: "")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null, !8}
-!8 = !{!"0xf\00\000\0064\0064\000\000", null, null, !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"0x2e\00main\00main\00\005\000\001\000\006\00256\000\005", !1, !5, !11, null, i32 (i32, i8**)* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [main]
-!11 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !9)
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DISubprogram(name: "main", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !11, function: i32 (i32, i8**)* @main, variables: !2)
+!11 = !DISubroutineType(types: !12)
 !12 = !{!9, !9, !13}
-!13 = !{!"0xf\00\000\0064\0064\000\000", null, null, !14} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!14 = !{!"0xf\00\000\0064\0064\000\000", null, null, !15} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char]
-!15 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
+!13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !14)
+!14 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !15)
+!15 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
 !16 = !{i32 2, !"Dwarf Version", i32 2}
-!17 = !{i32 1, !"Debug Info Version", i32 2}
+!17 = !{i32 1, !"Debug Info Version", i32 3}
 !18 = !{!"clang version 3.5.0 "}
-!19 = !{!"0x101\00p\0016777217\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [p] [line 1]
-!20 = !MDLocation(line: 1, scope: !4)
-!21 = !MDLocation(line: 2, scope: !4)
-!22 = !MDLocation(line: 3, scope: !4)
-!23 = !{!"0x101\00argc\0016777221\000", !10, !5, !9} ; [ DW_TAG_arg_variable ] [argc] [line 5]
-!24 = !MDLocation(line: 5, scope: !10)
-!25 = !{!"0x101\00argv\0033554437\000", !10, !5, !13} ; [ DW_TAG_arg_variable ] [argv] [line 5]
-!26 = !{!"0x100\00array\006\000", !10, !5, !27} ; [ DW_TAG_auto_variable ] [array] [line 6]
-!27 = !{!"0x1\00\000\00128\0032\000\000", null, null, !9, !28, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 32, offset 0] [from int]
+!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p", line: 1, arg: 1, scope: !4, file: !5, type: !8)
+!20 = !DILocation(line: 1, scope: !4)
+!21 = !DILocation(line: 2, scope: !4)
+!22 = !DILocation(line: 3, scope: !4)
+!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 5, arg: 1, scope: !10, file: !5, type: !9)
+!24 = !DILocation(line: 5, scope: !10)
+!25 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 5, arg: 2, scope: !10, file: !5, type: !13)
+!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "array", line: 6, scope: !10, file: !5, type: !27)
+!27 = !DICompositeType(tag: DW_TAG_array_type, size: 128, align: 32, baseType: !9, elements: !28)
 !28 = !{!29}
-!29 = !{!"0x21\000\004"}        ; [ DW_TAG_subrange_type ] [0, 3]
-!30 = !MDLocation(line: 6, scope: !10)
-!31 = !MDLocation(line: 7, scope: !10)
-!32 = !MDLocation(line: 8, scope: !10)
+!29 = !DISubrange(count: 4)
+!30 = !DILocation(line: 6, scope: !10)
+!31 = !DILocation(line: 7, scope: !10)
+!32 = !DILocation(line: 8, scope: !10)
diff --git a/test/DebugInfo/X86/block-capture.ll b/test/DebugInfo/X86/block-capture.ll
index 51d575fdfe42..fe026d656bb6 100644
--- a/test/DebugInfo/X86/block-capture.ll
+++ b/test/DebugInfo/X86/block-capture.ll
@@ -32,20 +32,20 @@ entry:
   %.block_descriptor.addr = alloca i8*, align 8
   %block.addr = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, void (...)* }>*, align 8
   store i8* %.block_descriptor, i8** %.block_descriptor.addr, align 8
-  %0 = load i8** %.block_descriptor.addr
+  %0 = load i8*, i8** %.block_descriptor.addr
   call void @llvm.dbg.value(metadata i8* %0, i64 0, metadata !47, metadata !43), !dbg !66
   call void @llvm.dbg.declare(metadata i8* %.block_descriptor, metadata !47, metadata !43), !dbg !66
   %block = bitcast i8* %.block_descriptor to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, void (...)* }>*, !dbg !67
   store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, void (...)* }>* %block, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, void (...)* }>** %block.addr, align 8
   call void @llvm.dbg.declare(metadata <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, void (...)* }>** %block.addr, metadata !68, metadata !69), !dbg !70
-  %block.capture.addr = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, void (...)* }>* %block, i32 0, i32 5, !dbg !71
-  %1 = load void (...)** %block.capture.addr, align 8, !dbg !71
+  %block.capture.addr = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, void (...)* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, void (...)* }>* %block, i32 0, i32 5, !dbg !71
+  %1 = load void (...)*, void (...)** %block.capture.addr, align 8, !dbg !71
   %block.literal = bitcast void (...)* %1 to %struct.__block_literal_generic*, !dbg !71
-  %2 = getelementptr inbounds %struct.__block_literal_generic* %block.literal, i32 0, i32 3, !dbg !71
+  %2 = getelementptr inbounds %struct.__block_literal_generic, %struct.__block_literal_generic* %block.literal, i32 0, i32 3, !dbg !71
   %3 = bitcast %struct.__block_literal_generic* %block.literal to i8*, !dbg !71
-  %4 = load i8** %2, !dbg !71
+  %4 = load i8*, i8** %2, !dbg !71
   %5 = bitcast i8* %4 to void (i8*, ...)*, !dbg !71
-  call void (i8*, ...)* %5(i8* %3), !dbg !71
+  call void (i8*, ...) %5(i8* %3), !dbg !71
   ret void, !dbg !73
 }
 
@@ -62,70 +62,70 @@ attributes #3 = { nounwind }
 !llvm.module.flags = !{!16, !17, !18, !19, !20, !21, !22}
 !llvm.ident = !{!23}
 
-!0 = !{!"0x11\0016\00clang version 3.6.0 (trunk 223471)\000\00\002\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/foo.m] [DW_LANG_ObjC]
-!1 = !{!"foo.m", !""}
+!0 = !DICompileUnit(language: DW_LANG_ObjC, producer: "clang version 3.6.0 (trunk 223471)", isOptimized: false, runtimeVersion: 2, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "foo.m", directory: "")
 !2 = !{}
 !3 = !{!8}
-!5 = !{!"0x29", !1}    ; [ DW_TAG_file_type ] [/foo.m]
-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DIFile(filename: "foo.m", directory: "")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
-!8 = !{!"0x2e\00__foo_block_invoke\00__foo_block_invoke\00\002\001\001\000\000\00256\000\002", !1, !5, !9, null, void (i8*)* @__foo_block_invoke, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [local] [def] [__foo_block_invoke]
-!9 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = !DISubprogram(name: "__foo_block_invoke", line: 2, isLocal: true, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !9, function: void (i8*)* @__foo_block_invoke, variables: !2)
+!9 = !DISubroutineType(types: !10)
 !10 = !{null, !11}
-!11 = !{!"0xf\00\000\0064\0064\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!13 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !14, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: null)
+!13 = !DISubroutineType(types: !14)
 !14 = !{null, !11, !11}
 !16 = !{i32 1, !"Objective-C Version", i32 2}
 !17 = !{i32 1, !"Objective-C Image Info Version", i32 0}
 !18 = !{i32 1, !"Objective-C Image Info Section", !"__DATA, __objc_imageinfo, regular, no_dead_strip"}
 !19 = !{i32 4, !"Objective-C Garbage Collection", i32 0}
 !20 = !{i32 2, !"Dwarf Version", i32 2}
-!21 = !{i32 2, !"Debug Info Version", i32 2}
+!21 = !{i32 2, !"Debug Info Version", i32 3}
 !22 = !{i32 1, !"PIC Level", i32 2}
 !23 = !{!"clang version 3.6.0 (trunk 223471)"}
-!25 = !{!"0xf\00\000\0064\000\000\000", null, null, !26} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from __block_literal_generic]
-!26 = !{!"0x13\00__block_literal_generic\002\00256\000\000\008\000", !1, !5, null, !27, null, null, null} ; [ DW_TAG_structure_type ] [__block_literal_generic] [line 2, size 256, align 0, offset 0] [def] [from ]
+!25 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, baseType: !26)
+!26 = !DICompositeType(tag: DW_TAG_structure_type, name: "__block_literal_generic", line: 2, size: 256, flags: DIFlagAppleBlock, file: !1, scope: !5, elements: !27)
 !27 = !{!28, !29, !31, !32, !36}
-!28 = !{!"0xd\00__isa\000\0064\0064\000\000", !1, !5, !11} ; [ DW_TAG_member ] [__isa] [line 0, size 64, align 64, offset 0] [from ]
-!29 = !{!"0xd\00__flags\000\0032\0032\0064\000", !1, !5, !30} ; [ DW_TAG_member ] [__flags] [line 0, size 32, align 32, offset 64] [from int]
-!30 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!31 = !{!"0xd\00__reserved\000\0032\0032\0096\000", !1, !5, !30} ; [ DW_TAG_member ] [__reserved] [line 0, size 32, align 32, offset 96] [from int]
-!32 = !{!"0xd\00__FuncPtr\000\0064\0064\00128\000", !1, !5, !33} ; [ DW_TAG_member ] [__FuncPtr] [line 0, size 64, align 64, offset 128] [from ]
-!33 = !{!"0xf\00\000\0064\0064\000\000", null, null, !34} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!34 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !35, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!28 = !DIDerivedType(tag: DW_TAG_member, name: "__isa", size: 64, align: 64, file: !1, scope: !5, baseType: !11)
+!29 = !DIDerivedType(tag: DW_TAG_member, name: "__flags", size: 32, align: 32, offset: 64, file: !1, scope: !5, baseType: !30)
+!30 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!31 = !DIDerivedType(tag: DW_TAG_member, name: "__reserved", size: 32, align: 32, offset: 96, file: !1, scope: !5, baseType: !30)
+!32 = !DIDerivedType(tag: DW_TAG_member, name: "__FuncPtr", size: 64, align: 64, offset: 128, file: !1, scope: !5, baseType: !33)
+!33 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !34)
+!34 = !DISubroutineType(types: !35)
 !35 = !{null, null}
-!36 = !{!"0xd\00__descriptor\002\0064\0064\00192\000", !1, !5, !37} ; [ DW_TAG_member ] [__descriptor] [line 2, size 64, align 64, offset 192] [from ]
-!37 = !{!"0xf\00\000\0064\000\000\000", null, null, !38} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from __block_descriptor]
-!38 = !{!"0x13\00__block_descriptor\002\00128\000\000\008\000", !1, !5, null, !39, null, null, null} ; [ DW_TAG_structure_type ] [__block_descriptor] [line 2, size 128, align 0, offset 0] [def] [from ]
+!36 = !DIDerivedType(tag: DW_TAG_member, name: "__descriptor", line: 2, size: 64, align: 64, offset: 192, file: !1, scope: !5, baseType: !37)
+!37 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, baseType: !38)
+!38 = !DICompositeType(tag: DW_TAG_structure_type, name: "__block_descriptor", line: 2, size: 128, flags: DIFlagAppleBlock, file: !1, scope: !5, elements: !39)
 !39 = !{!40, !42}
-!40 = !{!"0xd\00reserved\000\0064\0064\000\000", !1, !5, !41} ; [ DW_TAG_member ] [reserved] [line 0, size 64, align 64, offset 0] [from long unsigned int]
-!41 = !{!"0x24\00long unsigned int\000\0064\0064\000\000\007", null, null} ; [ DW_TAG_base_type ] [long unsigned int] [line 0, size 64, align 64, offset 0, enc DW_ATE_unsigned]
-!42 = !{!"0xd\00Size\000\0064\0064\0064\000", !1, !5, !41} ; [ DW_TAG_member ] [Size] [line 0, size 64, align 64, offset 64] [from long unsigned int]
-!43 = !{!"0x102"}               ; [ DW_TAG_expression ]
-!47 = !{!"0x101\00.block_descriptor\0016777218\0064", !8, !5, !48} ; [ DW_TAG_arg_variable ] [.block_descriptor] [line 2]
-!48 = !{!"0xf\00\000\0064\000\000\000", null, null, !49} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from __block_literal_1]
-!49 = !{!"0x13\00__block_literal_1\002\00320\0064\000\000\000", !1, !5, null, !50, null, null, null} ; [ DW_TAG_structure_type ] [__block_literal_1] [line 2, size 320, align 64, offset 0] [def] [from ]
+!40 = !DIDerivedType(tag: DW_TAG_member, name: "reserved", size: 64, align: 64, file: !1, scope: !5, baseType: !41)
+!41 = !DIBasicType(tag: DW_TAG_base_type, name: "long unsigned int", size: 64, align: 64, encoding: DW_ATE_unsigned)
+!42 = !DIDerivedType(tag: DW_TAG_member, name: "Size", size: 64, align: 64, offset: 64, file: !1, scope: !5, baseType: !41)
+!43 = !DIExpression()
+!47 = !DILocalVariable(tag: DW_TAG_arg_variable, name: ".block_descriptor", line: 2, arg: 1, flags: DIFlagArtificial, scope: !8, file: !5, type: !48)
+!48 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, baseType: !49)
+!49 = !DICompositeType(tag: DW_TAG_structure_type, name: "__block_literal_1", line: 2, size: 320, align: 64, file: !1, scope: !5, elements: !50)
 !50 = !{!51, !52, !53, !54, !56, !65}
-!51 = !{!"0xd\00__isa\002\0064\0064\000\003", !1, !5, !11} ; [ DW_TAG_member ] [__isa] [line 2, size 64, align 64, offset 0] [public] [from ]
-!52 = !{!"0xd\00__flags\002\0032\0032\0064\003", !1, !5, !30} ; [ DW_TAG_member ] [__flags] [line 2, size 32, align 32, offset 64] [public] [from int]
-!53 = !{!"0xd\00__reserved\002\0032\0032\0096\003", !1, !5, !30} ; [ DW_TAG_member ] [__reserved] [line 2, size 32, align 32, offset 96] [public] [from int]
-!54 = !{!"0xd\00__FuncPtr\002\0064\0064\00128\003", !1, !5, !55} ; [ DW_TAG_member ] [__FuncPtr] [line 2, size 64, align 64, offset 128] [public] [from ]
-!55 = !{!"0xf\00\000\0064\0064\000\000", null, null, !6} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!56 = !{!"0xd\00__descriptor\002\0064\0064\00192\003", !1, !5, !57} ; [ DW_TAG_member ] [__descriptor] [line 2, size 64, align 64, offset 192] [public] [from ]
-!57 = !{!"0xf\00\000\0064\0064\000\000", null, null, !58} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from __block_descriptor_withcopydispose]
-!58 = !{!"0x13\00__block_descriptor_withcopydispose\002\00256\0064\000\000\000", !1, null, null, !59, null, null, null} ; [ DW_TAG_structure_type ] [__block_descriptor_withcopydispose] [line 2, size 256, align 64, offset 0] [def] [from ]
+!51 = !DIDerivedType(tag: DW_TAG_member, name: "__isa", line: 2, size: 64, align: 64, flags: DIFlagPublic, file: !1, scope: !5, baseType: !11)
+!52 = !DIDerivedType(tag: DW_TAG_member, name: "__flags", line: 2, size: 32, align: 32, offset: 64, flags: DIFlagPublic, file: !1, scope: !5, baseType: !30)
+!53 = !DIDerivedType(tag: DW_TAG_member, name: "__reserved", line: 2, size: 32, align: 32, offset: 96, flags: DIFlagPublic, file: !1, scope: !5, baseType: !30)
+!54 = !DIDerivedType(tag: DW_TAG_member, name: "__FuncPtr", line: 2, size: 64, align: 64, offset: 128, flags: DIFlagPublic, file: !1, scope: !5, baseType: !55)
+!55 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !6)
+!56 = !DIDerivedType(tag: DW_TAG_member, name: "__descriptor", line: 2, size: 64, align: 64, offset: 192, flags: DIFlagPublic, file: !1, scope: !5, baseType: !57)
+!57 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !58)
+!58 = !DICompositeType(tag: DW_TAG_structure_type, name: "__block_descriptor_withcopydispose", line: 2, size: 256, align: 64, file: !1, elements: !59)
 !59 = !{!60, !61, !62, !64}
-!60 = !{!"0xd\00reserved\002\0064\0064\000\000", !1, !58, !41} ; [ DW_TAG_member ] [reserved] [line 2, size 64, align 64, offset 0] [from long unsigned int]
-!61 = !{!"0xd\00Size\002\0064\0064\0064\000", !1, !58, !41} ; [ DW_TAG_member ] [Size] [line 2, size 64, align 64, offset 64] [from long unsigned int]
-!62 = !{!"0xd\00CopyFuncPtr\002\0064\0064\00128\000", !1, !58, !63} ; [ DW_TAG_member ] [CopyFuncPtr] [line 2, size 64, align 64, offset 128] [from ]
-!63 = !{!"0xf\00\000\0064\0064\000\000", null, null, !11} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!64 = !{!"0xd\00DestroyFuncPtr\002\0064\0064\00192\000", !1, !58, !63} ; [ DW_TAG_member ] [DestroyFuncPtr] [line 2, size 64, align 64, offset 192] [from ]
-!65 = !{!"0xd\00block\002\0064\0064\00256\003", !1, !5, !25} ; [ DW_TAG_member ] [block] [line 2, size 64, align 64, offset 256] [public] [from ]
-!66 = !MDLocation(line: 2, column: 20, scope: !8)
-!67 = !MDLocation(line: 2, column: 21, scope: !8)
-!68 = !{!"0x100\00block\002\000", !8, !5, !25} ; [ DW_TAG_auto_variable ] [block] [line 2]
-!69 = !{!"0x102\006\0034\0032"} ; [ DW_TAG_expression ] [DW_OP_deref]
-!70 = !MDLocation(line: 2, column: 9, scope: !8)
-!71 = !MDLocation(line: 2, column: 23, scope: !72)
-!72 = !{!"0xb\002\0021\000", !1, !8} ; [ DW_TAG_lexical_block ] [/foo.m]
-!73 = !MDLocation(line: 2, column: 32, scope: !8)
+!60 = !DIDerivedType(tag: DW_TAG_member, name: "reserved", line: 2, size: 64, align: 64, file: !1, scope: !58, baseType: !41)
+!61 = !DIDerivedType(tag: DW_TAG_member, name: "Size", line: 2, size: 64, align: 64, offset: 64, file: !1, scope: !58, baseType: !41)
+!62 = !DIDerivedType(tag: DW_TAG_member, name: "CopyFuncPtr", line: 2, size: 64, align: 64, offset: 128, file: !1, scope: !58, baseType: !63)
+!63 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !11)
+!64 = !DIDerivedType(tag: DW_TAG_member, name: "DestroyFuncPtr", line: 2, size: 64, align: 64, offset: 192, file: !1, scope: !58, baseType: !63)
+!65 = !DIDerivedType(tag: DW_TAG_member, name: "block", line: 2, size: 64, align: 64, offset: 256, flags: DIFlagPublic, file: !1, scope: !5, baseType: !25)
+!66 = !DILocation(line: 2, column: 20, scope: !8)
+!67 = !DILocation(line: 2, column: 21, scope: !8)
+!68 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "block", line: 2, scope: !8, file: !5, type: !25)
+!69 = !DIExpression(DW_OP_deref, DW_OP_plus, 32)
+!70 = !DILocation(line: 2, column: 9, scope: !8)
+!71 = !DILocation(line: 2, column: 23, scope: !72)
+!72 = distinct !DILexicalBlock(line: 2, column: 21, file: !1, scope: !8)
+!73 = !DILocation(line: 2, column: 32, scope: !8)
diff --git a/test/DebugInfo/X86/byvalstruct.ll b/test/DebugInfo/X86/byvalstruct.ll
index d89ba3596c53..dedbfb0200b7 100644
--- a/test/DebugInfo/X86/byvalstruct.ll
+++ b/test/DebugInfo/X86/byvalstruct.ll
@@ -49,13 +49,13 @@ target triple = "x86_64-apple-macosx10.8.0"
 @"OBJC_CLASS_$_Bitmap" = global %struct._class_t { %struct._class_t* @"OBJC_METACLASS_$_Bitmap", %struct._class_t* null, %struct._objc_cache* @_objc_empty_cache, i8* (i8*, i8*)** @_objc_empty_vtable, %struct._class_ro_t* @"\01l_OBJC_CLASS_RO_$_Bitmap" }, section "__DATA, __objc_data", align 8
 @"OBJC_METACLASS_$_Bitmap" = global %struct._class_t { %struct._class_t* @"OBJC_METACLASS_$_Bitmap", %struct._class_t* @"OBJC_CLASS_$_Bitmap", %struct._objc_cache* @_objc_empty_cache, i8* (i8*, i8*)** @_objc_empty_vtable, %struct._class_ro_t* @"\01l_OBJC_METACLASS_RO_$_Bitmap" }, section "__DATA, __objc_data", align 8
 @"\01L_OBJC_CLASS_NAME_" = internal global [7 x i8] c"Bitmap\00", section "__TEXT,__objc_classname,cstring_literals", align 1
-@"\01l_OBJC_METACLASS_RO_$_Bitmap" = internal global %struct._class_ro_t { i32 3, i32 40, i32 40, i8* null, i8* getelementptr inbounds ([7 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), %struct.__method_list_t* null, %struct._objc_protocol_list* null, %struct._ivar_list_t* null, i8* null, %struct._prop_list_t* null }, section "__DATA, __objc_const", align 8
+@"\01l_OBJC_METACLASS_RO_$_Bitmap" = internal global %struct._class_ro_t { i32 3, i32 40, i32 40, i8* null, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), %struct.__method_list_t* null, %struct._objc_protocol_list* null, %struct._ivar_list_t* null, i8* null, %struct._prop_list_t* null }, section "__DATA, __objc_const", align 8
 @"\01L_OBJC_METH_VAR_NAME_" = internal global [32 x i8] c"initWithCopy:andInfo:andLength:\00", section "__TEXT,__objc_methname,cstring_literals", align 1
 @"\01L_OBJC_METH_VAR_TYPE_" = internal global [23 x i8] c"@56@0:8@16{?=QQd}24Q48\00", section "__TEXT,__objc_methtype,cstring_literals", align 1
-@"\01l_OBJC_$_INSTANCE_METHODS_Bitmap" = internal global { i32, i32, [1 x %struct._objc_method] } { i32 24, i32 1, [1 x %struct._objc_method] [%struct._objc_method { i8* getelementptr inbounds ([32 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([23 x i8]* @"\01L_OBJC_METH_VAR_TYPE_", i32 0, i32 0), i8* bitcast (i8* (%0*, i8*, %0*, %struct.ImageInfo*, i64)* @"\01-[Bitmap initWithCopy:andInfo:andLength:]" to i8*) }] }, section "__DATA, __objc_const", align 8
-@"\01l_OBJC_CLASS_RO_$_Bitmap" = internal global %struct._class_ro_t { i32 2, i32 0, i32 0, i8* null, i8* getelementptr inbounds ([7 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), %struct.__method_list_t* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_INSTANCE_METHODS_Bitmap" to %struct.__method_list_t*), %struct._objc_protocol_list* null, %struct._ivar_list_t* null, i8* null, %struct._prop_list_t* null }, section "__DATA, __objc_const", align 8
+@"\01l_OBJC_$_INSTANCE_METHODS_Bitmap" = internal global { i32, i32, [1 x %struct._objc_method] } { i32 24, i32 1, [1 x %struct._objc_method] [%struct._objc_method { i8* getelementptr inbounds ([32 x i8], [32 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([23 x i8], [23 x i8]* @"\01L_OBJC_METH_VAR_TYPE_", i32 0, i32 0), i8* bitcast (i8* (%0*, i8*, %0*, %struct.ImageInfo*, i64)* @"\01-[Bitmap initWithCopy:andInfo:andLength:]" to i8*) }] }, section "__DATA, __objc_const", align 8
+@"\01l_OBJC_CLASS_RO_$_Bitmap" = internal global %struct._class_ro_t { i32 2, i32 0, i32 0, i8* null, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), %struct.__method_list_t* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_INSTANCE_METHODS_Bitmap" to %struct.__method_list_t*), %struct._objc_protocol_list* null, %struct._ivar_list_t* null, i8* null, %struct._prop_list_t* null }, section "__DATA, __objc_const", align 8
 @"\01L_OBJC_LABEL_CLASS_$" = internal global [1 x i8*] [i8* bitcast (%struct._class_t* @"OBJC_CLASS_$_Bitmap" to i8*)], section "__DATA, __objc_classlist, regular, no_dead_strip", align 8
-@llvm.used = appending global [5 x i8*] [i8* getelementptr inbounds ([7 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([32 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([23 x i8]* @"\01L_OBJC_METH_VAR_TYPE_", i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_INSTANCE_METHODS_Bitmap" to i8*), i8* bitcast ([1 x i8*]* @"\01L_OBJC_LABEL_CLASS_$" to i8*)], section "llvm.metadata"
+@llvm.used = appending global [5 x i8*] [i8* getelementptr inbounds ([7 x i8], [7 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([23 x i8], [23 x i8]* @"\01L_OBJC_METH_VAR_TYPE_", i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_INSTANCE_METHODS_Bitmap" to i8*), i8* bitcast ([1 x i8*]* @"\01L_OBJC_LABEL_CLASS_$" to i8*)], section "llvm.metadata"
 
 ; Function Attrs: ssp uwtable
 define internal i8* @"\01-[Bitmap initWithCopy:andInfo:andLength:]"(%0* %self, i8* %_cmd, %0* %otherBitmap, %struct.ImageInfo* byval align 8 %info, i64 %length) #0 {
@@ -66,15 +66,15 @@ entry:
   %otherBitmap.addr = alloca %0*, align 8
   %length.addr = alloca i64, align 8
   store %0* %self, %0** %self.addr, align 8
-  call void @llvm.dbg.declare(metadata %0** %self.addr, metadata !28, metadata !{!"0x102"}), !dbg !29
+  call void @llvm.dbg.declare(metadata %0** %self.addr, metadata !28, metadata !DIExpression()), !dbg !29
   store i8* %_cmd, i8** %_cmd.addr, align 8
-  call void @llvm.dbg.declare(metadata i8** %_cmd.addr, metadata !30, metadata !{!"0x102"}), !dbg !29
+  call void @llvm.dbg.declare(metadata i8** %_cmd.addr, metadata !30, metadata !DIExpression()), !dbg !29
   store %0* %otherBitmap, %0** %otherBitmap.addr, align 8
-  call void @llvm.dbg.declare(metadata %0** %otherBitmap.addr, metadata !32, metadata !{!"0x102"}), !dbg !29
-  call void @llvm.dbg.declare(metadata %struct.ImageInfo* %info, metadata !33, metadata !{!"0x102"}), !dbg !34
+  call void @llvm.dbg.declare(metadata %0** %otherBitmap.addr, metadata !32, metadata !DIExpression()), !dbg !29
+  call void @llvm.dbg.declare(metadata %struct.ImageInfo* %info, metadata !33, metadata !DIExpression()), !dbg !34
   store i64 %length, i64* %length.addr, align 8
-  call void @llvm.dbg.declare(metadata i64* %length.addr, metadata !35, metadata !{!"0x102"}), !dbg !36
-  %0 = load i8** %retval, !dbg !37
+  call void @llvm.dbg.declare(metadata i64* %length.addr, metadata !35, metadata !DIExpression()), !dbg !36
+  %0 = load i8*, i8** %retval, !dbg !37
   ret i8* %0, !dbg !37
 }
 
@@ -87,42 +87,42 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!24, !25, !26, !27, !38}
 
-!0 = !{!"0x11\0017\00clang version 3.4 \000\00\002\00\000", !1, !2, !3, !6, !2, !2} ; [ DW_TAG_compile_unit ] [/t.mm] [DW_LANG_ObjC_plus_plus]
-!1 = !{!"t.mm", !""}
+!0 = !DICompileUnit(language: DW_LANG_ObjC_plus_plus, producer: "clang version 3.4 ", isOptimized: false, runtimeVersion: 2, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !6, globals: !2, imports: !2)
+!1 = !DIFile(filename: "t.mm", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00Bitmap\008\008\008\000\00512\0017", !1, !5, null, !2, null, null, null} ; [ DW_TAG_structure_type ] [Bitmap] [line 8, size 8, align 8, offset 0] [def] [from ]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/t.mm]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "Bitmap", line: 8, size: 8, align: 8, flags: DIFlagObjcClassComplete, runtimeLang: DW_LANG_ObjC_plus_plus, file: !1, scope: !5, elements: !2)
+!5 = !DIFile(filename: "t.mm", directory: "")
 !6 = !{!7}
-!7 = !{!"0x2e\00-[Bitmap initWithCopy:andInfo:andLength:]\00-[Bitmap initWithCopy:andInfo:andLength:]\00\009\001\001\000\006\00256\000\009", !1, !5, !8, null, i8* (%0*, i8*, %0*, %struct.ImageInfo*, i64)* @"\01-[Bitmap initWithCopy:andInfo:andLength:]", null, null, !2} ; [ DW_TAG_subprogram ] [line 9] [local] [def] [-[Bitmap initWithCopy:andInfo:andLength:]]
-!8 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !9, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = !DISubprogram(name: "-[Bitmap initWithCopy:andInfo:andLength:]", line: 9, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 9, file: !1, scope: !5, type: !8, function: i8* (%0*, i8*, %0*, %struct.ImageInfo*, i64)* @"\01-[Bitmap initWithCopy:andInfo:andLength:]", variables: !2)
+!8 = !DISubroutineType(types: !9)
 !9 = !{!4, !10, !11, !14, !15, !19}
-!10 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !4} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from Bitmap]
-!11 = !{!"0x16\00SEL\009\000\000\000\0064", !1, null, !12} ; [ DW_TAG_typedef ] [SEL] [line 9, size 0, align 0, offset 0] [artificial] [from ]
-!12 = !{!"0xf\00\000\0064\0064\000\000", null, null, !13} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from objc_selector]
-!13 = !{!"0x13\00objc_selector\000\000\000\000\004\000", !1, null, null, null, null, null, null} ; [ DW_TAG_structure_type ] [objc_selector] [line 0, size 0, align 0, offset 0] [decl] [from ]
-!14 = !{!"0xf\00\000\0064\0064\000\000", null, null, !4} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from Bitmap]
-!15 = !{!"0x16\00ImageInfo\007\000\000\000\000", !1, null, !16} ; [ DW_TAG_typedef ] [ImageInfo] [line 7, size 0, align 0, offset 0] [from ]
-!16 = !{!"0x13\00\002\00192\0064\000\000\000", !1, null, null, !17, null, null, null} ; [ DW_TAG_structure_type ] [line 2, size 192, align 64, offset 0] [def] [from ]
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !4)
+!11 = !DIDerivedType(tag: DW_TAG_typedef, name: "SEL", line: 9, flags: DIFlagArtificial, file: !1, baseType: !12)
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !13)
+!13 = !DICompositeType(tag: DW_TAG_structure_type, name: "objc_selector", flags: DIFlagFwdDecl, file: !1)
+!14 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !4)
+!15 = !DIDerivedType(tag: DW_TAG_typedef, name: "ImageInfo", line: 7, file: !1, baseType: !16)
+!16 = !DICompositeType(tag: DW_TAG_structure_type, line: 2, size: 192, align: 64, file: !1, elements: !17)
 !17 = !{!18, !21, !22}
-!18 = !{!"0xd\00width\004\0064\0064\000\000", !1, !16, !19} ; [ DW_TAG_member ] [width] [line 4, size 64, align 64, offset 0] [from NSUInteger]
-!19 = !{!"0x16\00NSUInteger\001\000\000\000\000", !1, null, !20} ; [ DW_TAG_typedef ] [NSUInteger] [line 1, size 0, align 0, offset 0] [from long unsigned int]
-!20 = !{!"0x24\00long unsigned int\000\0064\0064\000\000\007", null, null} ; [ DW_TAG_base_type ] [long unsigned int] [line 0, size 64, align 64, offset 0, enc DW_ATE_unsigned]
-!21 = !{!"0xd\00height\005\0064\0064\0064\000", !1, !16, !19} ; [ DW_TAG_member ] [height] [line 5, size 64, align 64, offset 64] [from NSUInteger]
-!22 = !{!"0xd\00pixelAspect\006\0064\0064\00128\000", !1, !16, !23} ; [ DW_TAG_member ] [pixelAspect] [line 6, size 64, align 64, offset 128] [from double]
-!23 = !{!"0x24\00double\000\0064\0064\000\000\004", null, null} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float]
+!18 = !DIDerivedType(tag: DW_TAG_member, name: "width", line: 4, size: 64, align: 64, file: !1, scope: !16, baseType: !19)
+!19 = !DIDerivedType(tag: DW_TAG_typedef, name: "NSUInteger", line: 1, file: !1, baseType: !20)
+!20 = !DIBasicType(tag: DW_TAG_base_type, name: "long unsigned int", size: 64, align: 64, encoding: DW_ATE_unsigned)
+!21 = !DIDerivedType(tag: DW_TAG_member, name: "height", line: 5, size: 64, align: 64, offset: 64, file: !1, scope: !16, baseType: !19)
+!22 = !DIDerivedType(tag: DW_TAG_member, name: "pixelAspect", line: 6, size: 64, align: 64, offset: 128, file: !1, scope: !16, baseType: !23)
+!23 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 64, encoding: DW_ATE_float)
 !24 = !{i32 1, !"Objective-C Version", i32 2}
 !25 = !{i32 1, !"Objective-C Image Info Version", i32 0}
 !26 = !{i32 1, !"Objective-C Image Info Section", !"__DATA, __objc_imageinfo, regular, no_dead_strip"}
 !27 = !{i32 4, !"Objective-C Garbage Collection", i32 0}
-!28 = !{!"0x101\00self\0016777225\001088", !7, !5, !14} ; [ DW_TAG_arg_variable ] [self] [line 9]
-!29 = !MDLocation(line: 9, scope: !7)
-!30 = !{!"0x101\00_cmd\0033554441\0064", !7, !5, !31} ; [ DW_TAG_arg_variable ] [_cmd] [line 9]
-!31 = !{!"0x16\00SEL\009\000\000\000\000", !1, null, !12} ; [ DW_TAG_typedef ] [SEL] [line 9, size 0, align 0, offset 0] [from ]
-!32 = !{!"0x101\00otherBitmap\0050331657\000", !7, !5, !14} ; [ DW_TAG_arg_variable ] [otherBitmap] [line 9]
-!33 = !{!"0x101\00info\0067108874\000", !7, !5, !15} ; [ DW_TAG_arg_variable ] [info] [line 10]
-!34 = !MDLocation(line: 10, scope: !7)
-!35 = !{!"0x101\00length\0083886091\000", !7, !5, !19} ; [ DW_TAG_arg_variable ] [length] [line 11]
-!36 = !MDLocation(line: 11, scope: !7)
-!37 = !MDLocation(line: 13, scope: !7)
-!38 = !{i32 1, !"Debug Info Version", i32 2}
+!28 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "self", line: 9, arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !7, file: !5, type: !14)
+!29 = !DILocation(line: 9, scope: !7)
+!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "_cmd", line: 9, arg: 2, flags: DIFlagArtificial, scope: !7, file: !5, type: !31)
+!31 = !DIDerivedType(tag: DW_TAG_typedef, name: "SEL", line: 9, file: !1, baseType: !12)
+!32 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "otherBitmap", line: 9, arg: 3, scope: !7, file: !5, type: !14)
+!33 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "info", line: 10, arg: 4, scope: !7, file: !5, type: !15)
+!34 = !DILocation(line: 10, scope: !7)
+!35 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "length", line: 11, arg: 5, scope: !7, file: !5, type: !19)
+!36 = !DILocation(line: 11, scope: !7)
+!37 = !DILocation(line: 13, scope: !7)
+!38 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/c-type-units.ll b/test/DebugInfo/X86/c-type-units.ll
index b9bc36eac8d1..6756bd45f88c 100644
--- a/test/DebugInfo/X86/c-type-units.ll
+++ b/test/DebugInfo/X86/c-type-units.ll
@@ -17,13 +17,13 @@
 !llvm.module.flags = !{!7, !8}
 !llvm.ident = !{!9}
 
-!0 = !{!"0x11\0012\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !2, !3, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/simple.c] [DW_LANG_C99]
-!1 = !{!"simple.c", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3, imports: !2)
+!1 = !DIFile(filename: "simple.c", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x34\00f\00f\00\002\000\001", null, !5, !6, %struct.foo* @f, null} ; [ DW_TAG_variable ] [f] [line 2] [def]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/simple.c]
-!6 = !{!"0x13\00foo\001\000\008\000\000\000", !1, null, null, !2, null, null, null} ; [ DW_TAG_structure_type ] [foo] [line 1, size 0, align 8, offset 0] [def] [from ]
+!4 = !DIGlobalVariable(name: "f", line: 2, isLocal: false, isDefinition: true, scope: null, file: !5, type: !6, variable: %struct.foo* @f)
+!5 = !DIFile(filename: "simple.c", directory: "/tmp/dbginfo")
+!6 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo", line: 1, align: 8, file: !1, elements: !2)
 !7 = !{i32 2, !"Dwarf Version", i32 4}
-!8 = !{i32 1, !"Debug Info Version", i32 2}
+!8 = !{i32 1, !"Debug Info Version", i32 3}
 !9 = !{!"clang version 3.5 "}
diff --git a/test/DebugInfo/X86/coff_debug_info_type.ll b/test/DebugInfo/X86/coff_debug_info_type.ll
index 89859d246af8..fd86c88baa15 100644
--- a/test/DebugInfo/X86/coff_debug_info_type.ll
+++ b/test/DebugInfo/X86/coff_debug_info_type.ll
@@ -29,15 +29,15 @@ attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"=
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!9, !11}
 
-!0 = !{!"0x11\0012\00clang version 3.4 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [C:\Projects/test.c] [DW_LANG_C99]
-!1 = !{!"test.c", !"C:\5CProjects"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.c", directory: "C:\5CProjects")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00main\00main\00\001\000\001\000\006\000\000\002", !1, !5, !6, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [scope 2] [main]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [C:\Projects/test.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "main", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !6, function: i32 ()* @main, variables: !2)
+!5 = !DIFile(filename: "test.c", directory: "C:CProjects")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 3}
-!10 = !MDLocation(line: 3, scope: !4)
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !DILocation(line: 3, scope: !4)
+!11 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/coff_relative_names.ll b/test/DebugInfo/X86/coff_relative_names.ll
index 96e70b1e3881..6b7864ab3979 100644
--- a/test/DebugInfo/X86/coff_relative_names.ll
+++ b/test/DebugInfo/X86/coff_relative_names.ll
@@ -23,15 +23,15 @@ attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"=
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!9, !11}
 
-!0 = !{!"0x11\0012\00clang version 3.4 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [C:\Projects/test.c] [DW_LANG_C99]
-!1 = !{!"test.c", !"C:\5CProjects"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.c", directory: "C:\5CProjects")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00main\00main\00\001\000\001\000\006\000\000\002", !1, !5, !6, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [scope 2] [main]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [C:\Projects/test.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "main", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !6, function: i32 ()* @main, variables: !2)
+!5 = !DIFile(filename: "test.c", directory: "C:CProjects")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 3}
-!10 = !MDLocation(line: 3, scope: !4)
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !DILocation(line: 3, scope: !4)
+!11 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/concrete_out_of_line.ll b/test/DebugInfo/X86/concrete_out_of_line.ll
index b5da28ae3289..c1e1f750e2cc 100644
--- a/test/DebugInfo/X86/concrete_out_of_line.ll
+++ b/test/DebugInfo/X86/concrete_out_of_line.ll
@@ -9,11 +9,11 @@
 ; CHECK: DW_TAG_class_type
 ; CHECK:   DW_TAG_subprogram
 ; CHECK:   DW_TAG_subprogram
-; CHECK:     DW_AT_MIPS_linkage_name {{.*}} "_ZN12nsAutoRefCntaSEi"
+; CHECK:     DW_AT_linkage_name {{.*}} "_ZN12nsAutoRefCntaSEi"
 
 ; CHECK: DW_TAG_class_type
 ; CHECK:   DW_TAG_subprogram
-; CHECK:     DW_AT_MIPS_linkage_name {{.*}} "_ZN17nsAutoRefCnt7ReleaseEv"
+; CHECK:     DW_AT_linkage_name {{.*}} "_ZN17nsAutoRefCnt7ReleaseEv"
 ; CHECK:   DW_TAG_subprogram
 ; CHECK:     DW_AT_name {{.*}} "~nsAutoRefCnt"
 
@@ -76,56 +76,56 @@ declare void @_Z8moz_freePv(i8*)
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!60}
 
-!0 = !{!"0x11\004\00clang version 3.1 ()\001\00\000\00\000", !59, !1, !1, !3, !47,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.1 ()", isOptimized: true, emissionKind: 0, file: !59, enums: !1, retainedTypes: !1, subprograms: !3, globals: !47, imports:  !1)
 !1 = !{}
 !3 = !{!5, !23, !27, !31}
-!5 = !{!"0x2e\00Release\00Release\00_ZN17nsAutoRefCnt7ReleaseEv\0014\000\001\000\006\00256\001\0014", !6, null, !7, null, i32 ()* @_ZN17nsAutoRefCnt7ReleaseEv , null, !12, !20} ; [ DW_TAG_subprogram ] [line 14] [def] [Release]
-!6 = !{!"0x29", !59} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "Release", linkageName: "_ZN17nsAutoRefCnt7ReleaseEv", line: 14, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 14, file: !6, scope: null, type: !7, function: i32 ()* @_ZN17nsAutoRefCnt7ReleaseEv , declaration: !12, variables: !20)
+!6 = !DIFile(filename: "nsAutoRefCnt.ii", directory: "/Users/espindola/mozilla-central/obj-x86_64-apple-darwin11.2.0/netwerk/base/src")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !10}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!10 = !{!"0xf\00\000\0064\0064\000\0064", i32 0, null, !11} ; [ DW_TAG_pointer_type ]
-!11 = !{!"0x13\00nsAutoRefCnt\0010\000\000\000\004\000", !59, null, null, null, null, null, null} ; [ DW_TAG_structure_type ] [nsAutoRefCnt] [line 10, size 0, align 0, offset 0] [decl] [from ]
-!12 = !{!"0x2e\00Release\00Release\00_ZN17nsAutoRefCnt7ReleaseEv\0011\000\000\000\006\00256\001\0011", !6, !13, !7, null, null, null, i32 0, !18} ; [ DW_TAG_subprogram ]
-!13 = !{!"0x2\00nsAutoRefCnt\0010\008\008\000\000\000", !59, null, null, !14, null, null} ; [ DW_TAG_class_type ]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, baseType: !11)
+!11 = !DICompositeType(tag: DW_TAG_structure_type, name: "nsAutoRefCnt", line: 10, flags: DIFlagFwdDecl, file: !59)
+!12 = !DISubprogram(name: "Release", linkageName: "_ZN17nsAutoRefCnt7ReleaseEv", line: 11, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !6, scope: !13, type: !7, variables: !18)
+!13 = !DICompositeType(tag: DW_TAG_class_type, name: "nsAutoRefCnt", line: 10, size: 8, align: 8, file: !59, elements: !14)
 !14 = !{!12, !15}
-!15 = !{!"0x2e\00~nsAutoRefCnt\00~nsAutoRefCnt\00\0012\000\000\000\006\00256\001\0012", !6, !13, !16, null, null, null, i32 0, !18} ; [ DW_TAG_subprogram ]
-!16 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !17, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!15 = !DISubprogram(name: "~nsAutoRefCnt", line: 12, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 12, file: !6, scope: !13, type: !16, variables: !18)
+!16 = !DISubroutineType(types: !17)
 !17 = !{null, !10}
 !18 = !{}
 !20 = !{!22}
-!22 = !{!"0x101\00this\0016777230\0064", !5, !6, !10} ; [ DW_TAG_arg_variable ]
-!23 = !{!"0x2e\00~nsAutoRefCnt\00~nsAutoRefCnt\00_ZN17nsAutoRefCntD1Ev\0018\000\001\000\006\00256\001\0018", !6, null, !16, null, void ()* @_ZN17nsAutoRefCntD1Ev, null, !15, !24} ; [ DW_TAG_subprogram ] [line 18] [def] [~nsAutoRefCnt]
+!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 14, arg: 1, flags: DIFlagArtificial, scope: !5, file: !6, type: !10)
+!23 = !DISubprogram(name: "~nsAutoRefCnt", linkageName: "_ZN17nsAutoRefCntD1Ev", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 18, file: !6, scope: null, type: !16, function: void ()* @_ZN17nsAutoRefCntD1Ev, declaration: !15, variables: !24)
 !24 = !{!26}
-!26 = !{!"0x101\00this\0016777234\0064", !23, !6, !10} ; [ DW_TAG_arg_variable ]
-!27 = !{!"0x2e\00~nsAutoRefCnt\00~nsAutoRefCnt\00_ZN17nsAutoRefCntD2Ev\0018\000\001\000\006\00256\001\0018", !6, null, !16, null, i32* null, null, !15, !28} ; [ DW_TAG_subprogram ] [line 18] [def] [~nsAutoRefCnt]
+!26 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 18, arg: 1, flags: DIFlagArtificial, scope: !23, file: !6, type: !10)
+!27 = !DISubprogram(name: "~nsAutoRefCnt", linkageName: "_ZN17nsAutoRefCntD2Ev", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 18, file: !6, scope: null, type: !16, function: i32 ()* null, declaration: !15, variables: !28)
 !28 = !{!30}
-!30 = !{!"0x101\00this\0016777234\0064", !27, !6, !10} ; [ DW_TAG_arg_variable ]
-!31 = !{!"0x2e\00operator=\00operator=\00_ZN12nsAutoRefCntaSEi\004\000\001\000\006\00256\001\004", !6, null, !32, null, null, null, !36, !43} ; [ DW_TAG_subprogram ] [line 4] [def] [operator=]
-!32 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !33, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 18, arg: 1, flags: DIFlagArtificial, scope: !27, file: !6, type: !10)
+!31 = !DISubprogram(name: "operator=", linkageName: "_ZN12nsAutoRefCntaSEi", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 4, file: !6, scope: null, type: !32, declaration: !36, variables: !43)
+!32 = !DISubroutineType(types: !33)
 !33 = !{!9, !34, !9}
-!34 = !{!"0xf\00\000\0064\0064\000\0064", i32 0, null, !35} ; [ DW_TAG_pointer_type ]
-!35 = !{!"0x13\00nsAutoRefCnt\002\000\000\000\004\000", !59, null, null, null, null, null, null} ; [ DW_TAG_structure_type ] [nsAutoRefCnt] [line 2, size 0, align 0, offset 0] [decl] [from ]
-!36 = !{!"0x2e\00operator=\00operator=\00_ZN12nsAutoRefCntaSEi\004\000\000\000\006\00256\001\004", !6, !37, !32, null, null, null, i32 0, !18} ; [ DW_TAG_subprogram ]
-!37 = !{!"0x2\00nsAutoRefCnt\002\0032\0032\000\000\000", !59, null, null, !38, null, null, null} ; [ DW_TAG_class_type ] [nsAutoRefCnt] [line 2, size 32, align 32, offset 0] [def] [from ]
+!34 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, baseType: !35)
+!35 = !DICompositeType(tag: DW_TAG_structure_type, name: "nsAutoRefCnt", line: 2, flags: DIFlagFwdDecl, file: !59)
+!36 = !DISubprogram(name: "operator=", linkageName: "_ZN12nsAutoRefCntaSEi", line: 4, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 4, file: !6, scope: !37, type: !32, variables: !18)
+!37 = !DICompositeType(tag: DW_TAG_class_type, name: "nsAutoRefCnt", line: 2, size: 32, align: 32, file: !59, elements: !38)
 !38 = !{!39, !40, !36}
-!39 = !{!"0xd\00mValue\007\0032\0032\000\000", !59, !37, !9} ; [ DW_TAG_member ]
-!40 = !{!"0x2e\00nsAutoRefCnt\00nsAutoRefCnt\00\003\000\000\000\006\00256\001\003", !6, !37, !41, null, null, null, i32 0, !18} ; [ DW_TAG_subprogram ]
-!41 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !42, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!39 = !DIDerivedType(tag: DW_TAG_member, name: "mValue", line: 7, size: 32, align: 32, file: !59, scope: !37, baseType: !9)
+!40 = !DISubprogram(name: "nsAutoRefCnt", line: 3, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !6, scope: !37, type: !41, variables: !18)
+!41 = !DISubroutineType(types: !42)
 !42 = !{null, !34}
 !43 = !{!45, !46}
-!45 = !{!"0x101\00this\0016777220\0064", !31, !6, !34} ; [ DW_TAG_arg_variable ]
-!46 = !{!"0x101\00aValue\0033554436\000", !31, !6, !9} ; [ DW_TAG_arg_variable ]
+!45 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 4, arg: 1, flags: DIFlagArtificial, scope: !31, file: !6, type: !34)
+!46 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "aValue", line: 4, arg: 2, scope: !31, file: !6, type: !9)
 !47 = !{!49}
-!49 = !{!"0x34\00mRefCnt\00mRefCnt\00\009\000\001", null, !6, !37, i32* null, null} ; [ DW_TAG_variable ]
-!50 = !MDLocation(line: 5, column: 5, scope: !51, inlinedAt: !52)
-!51 = !{!"0xb\004\0029\002", !6, !31} ; [ DW_TAG_lexical_block ]
-!52 = !MDLocation(line: 15, scope: !53)
-!53 = !{!"0xb\0014\0034\000", !6, !5} ; [ DW_TAG_lexical_block ]
-!54 = !MDLocation(line: 19, column: 3, scope: !55, inlinedAt: !56)
-!55 = !{!"0xb\0018\0041\001", !6, !27} ; [ DW_TAG_lexical_block ]
-!56 = !MDLocation(line: 18, column: 41, scope: !23, inlinedAt: !52)
-!57 = !MDLocation(line: 19, column: 3, scope: !55, inlinedAt: !58)
-!58 = !MDLocation(line: 18, column: 41, scope: !23)
-!59 = !{!"nsAutoRefCnt.ii", !"/Users/espindola/mozilla-central/obj-x86_64-apple-darwin11.2.0/netwerk/base/src"}
-!60 = !{i32 1, !"Debug Info Version", i32 2}
+!49 = !DIGlobalVariable(name: "mRefCnt", line: 9, isLocal: false, isDefinition: true, scope: null, file: !6, type: !37, variable: i32* null)
+!50 = !DILocation(line: 5, column: 5, scope: !51, inlinedAt: !52)
+!51 = distinct !DILexicalBlock(line: 4, column: 29, file: !6, scope: !31)
+!52 = !DILocation(line: 15, scope: !53)
+!53 = distinct !DILexicalBlock(line: 14, column: 34, file: !6, scope: !5)
+!54 = !DILocation(line: 19, column: 3, scope: !55, inlinedAt: !56)
+!55 = distinct !DILexicalBlock(line: 18, column: 41, file: !6, scope: !27)
+!56 = !DILocation(line: 18, column: 41, scope: !23, inlinedAt: !52)
+!57 = !DILocation(line: 19, column: 3, scope: !55, inlinedAt: !58)
+!58 = !DILocation(line: 18, column: 41, scope: !23)
+!59 = !DIFile(filename: "nsAutoRefCnt.ii", directory: "/Users/espindola/mozilla-central/obj-x86_64-apple-darwin11.2.0/netwerk/base/src")
+!60 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/constant-aggregate.ll b/test/DebugInfo/X86/constant-aggregate.ll
index 324c83177746..daec3b4e7d66 100644
--- a/test/DebugInfo/X86/constant-aggregate.ll
+++ b/test/DebugInfo/X86/constant-aggregate.ll
@@ -72,47 +72,47 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!33, !34, !35}
 !llvm.ident = !{!36}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 (trunk 225364) (llvm/trunk 225366)\001\00\000\00\001", !1, !2, !3, !11, !2, !2} ; [ DW_TAG_compile_unit ] [/sroasplit-4.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"sroasplit-4.cpp", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 (trunk 225364) (llvm/trunk 225366)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !11, globals: !2, imports: !2)
+!1 = !DIFile(filename: "sroasplit-4.cpp", directory: "")
 !2 = !{}
 !3 = !{!4, !8}
-!4 = !{!"0x13\00\001\0032\0032\000\000\000", !1, null, null, !5, null, null, !"_ZTS1S"} ; [ DW_TAG_structure_type ] [line 1, size 32, align 32, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, line: 1, size: 32, align: 32, file: !1, elements: !5, identifier: "_ZTS1S")
 !5 = !{!6}
-!6 = !{!"0xd\00i\001\0032\0032\000\000", !1, !"_ZTS1S", !7} ; [ DW_TAG_member ] [i] [line 1, size 32, align 32, offset 0] [from unsigned int]
-!7 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, null} ; [ DW_TAG_base_type ] [unsigned int] [line 0, size 32, align 32, offset 0, enc DW_ATE_unsigned]
-!8 = !{!"0x2\00C\008\0032\0032\000\000\000", !1, null, null, !9, null, null, !"_ZTS1C"} ; [ DW_TAG_class_type ] [C] [line 8, size 32, align 32, offset 0] [def] [from ]
+!6 = !DIDerivedType(tag: DW_TAG_member, name: "i", line: 1, size: 32, align: 32, file: !1, scope: !"_ZTS1S", baseType: !7)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!8 = !DICompositeType(tag: DW_TAG_class_type, name: "C", line: 8, size: 32, align: 32, file: !1, elements: !9, identifier: "_ZTS1C")
 !9 = !{!10}
-!10 = !{!"0xd\00i\008\0032\0032\000\003", !1, !"_ZTS1C", !7} ; [ DW_TAG_member ] [i] [line 8, size 32, align 32, offset 0] [public] [from unsigned int]
+!10 = !DIDerivedType(tag: DW_TAG_member, name: "i", line: 8, size: 32, align: 32, flags: DIFlagPublic, file: !1, scope: !"_ZTS1C", baseType: !7)
 !11 = !{!12, !19, !24}
-!12 = !{!"0x2e\00foo\00foo\00_Z3foo1S\003\000\001\000\000\00256\001\003", !1, !13, !14, null, i32 (i32)* @_Z3foo1S, null, null, !17} ; [ DW_TAG_subprogram ] [line 3] [def] [foo]
-!13 = !{!"0x29", !1}                              ; [ DW_TAG_file_type ] [/sroasplit-4.cpp]
-!14 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !15, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = !DISubprogram(name: "foo", linkageName: "_Z3foo1S", line: 3, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !1, scope: !13, type: !14, function: i32 (i32)* @_Z3foo1S, variables: !17)
+!13 = !DIFile(filename: "sroasplit-4.cpp", directory: "")
+!14 = !DISubroutineType(types: !15)
 !15 = !{!7, !16}
-!16 = !{!"0x16\00S\001\000\000\000\000", !1, null, !"_ZTS1S"} ; [ DW_TAG_typedef ] [S] [line 1, size 0, align 0, offset 0] [from _ZTS1S]
+!16 = !DIDerivedType(tag: DW_TAG_typedef, name: "S", line: 1, file: !1, baseType: !"_ZTS1S")
 !17 = !{!18}
-!18 = !{!"0x101\00s\0016777219\000", !12, !13, !16} ; [ DW_TAG_arg_variable ] [s] [line 3]
-!19 = !{!"0x2e\00foo\00foo\00_Z3foo1C\0010\000\001\000\000\00256\001\0010", !1, !13, !20, null, i32 (i32)* @_Z3foo1C, null, null, !22} ; [ DW_TAG_subprogram ] [line 10] [def] [foo]
-!20 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !21, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "s", line: 3, arg: 1, scope: !12, file: !13, type: !16)
+!19 = !DISubprogram(name: "foo", linkageName: "_Z3foo1C", line: 10, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 10, file: !1, scope: !13, type: !20, function: i32 (i32)* @_Z3foo1C, variables: !22)
+!20 = !DISubroutineType(types: !21)
 !21 = !{!7, !"_ZTS1C"}
 !22 = !{!23}
-!23 = !{!"0x101\00c\0016777226\000", !19, !13, !"_ZTS1C"} ; [ DW_TAG_arg_variable ] [c] [line 10]
-!24 = !{!"0x2e\00bar\00bar\00_Z3barv\0015\000\001\000\000\00256\001\0015", !1, !13, !25, null, i32 ()* @_Z3barv, null, null, !27} ; [ DW_TAG_subprogram ] [line 15] [def] [bar]
-!25 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !26, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 10, arg: 1, scope: !19, file: !13, type: !"_ZTS1C")
+!24 = !DISubprogram(name: "bar", linkageName: "_Z3barv", line: 15, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 15, file: !1, scope: !13, type: !25, function: i32 ()* @_Z3barv, variables: !27)
+!25 = !DISubroutineType(types: !26)
 !26 = !{!7}
 !27 = !{!28}
-!28 = !{!"0x100\00a\0016\000", !24, !13, !29}     ; [ DW_TAG_auto_variable ] [a] [line 16]
-!29 = !{!"0x1\00\000\0032\0032\000\000\000", null, null, !30, !31, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 32, align 32, offset 0] [from int]
-!30 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 16, scope: !24, file: !13, type: !29)
+!29 = !DICompositeType(tag: DW_TAG_array_type, size: 32, align: 32, baseType: !30, elements: !31)
+!30 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !31 = !{!32}
-!32 = !{!"0x21\000\001"}                          ; [ DW_TAG_subrange_type ] [0, 0]
+!32 = !DISubrange(count: 1)
 !33 = !{i32 2, !"Dwarf Version", i32 2}
-!34 = !{i32 2, !"Debug Info Version", i32 2}
+!34 = !{i32 2, !"Debug Info Version", i32 3}
 !35 = !{i32 1, !"PIC Level", i32 2}
 !36 = !{!"clang version 3.6.0 (trunk 225364) (llvm/trunk 225366)"}
-!37 = !{!"0x102"}                                 ; [ DW_TAG_expression ]
-!38 = !MDLocation(line: 3, column: 16, scope: !12)
-!39 = !MDLocation(line: 5, column: 3, scope: !12)
-!40 = !MDLocation(line: 10, column: 16, scope: !19)
-!41 = !MDLocation(line: 12, column: 3, scope: !19)
-!42 = !MDLocation(line: 16, column: 6, scope: !24)
-!43 = !MDLocation(line: 17, column: 3, scope: !24)
+!37 = !DIExpression()
+!38 = !DILocation(line: 3, column: 16, scope: !12)
+!39 = !DILocation(line: 5, column: 3, scope: !12)
+!40 = !DILocation(line: 10, column: 16, scope: !19)
+!41 = !DILocation(line: 12, column: 3, scope: !19)
+!42 = !DILocation(line: 16, column: 6, scope: !24)
+!43 = !DILocation(line: 17, column: 3, scope: !24)
diff --git a/test/DebugInfo/X86/cu-ranges-odr.ll b/test/DebugInfo/X86/cu-ranges-odr.ll
index c1f58d7eed73..623e2fdd47a5 100644
--- a/test/DebugInfo/X86/cu-ranges-odr.ll
+++ b/test/DebugInfo/X86/cu-ranges-odr.ll
@@ -35,12 +35,12 @@ entry:
   %this.addr = alloca %class.A*, align 8
   %i.addr = alloca i32, align 4
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !27, metadata !{!"0x102"}), !dbg !29
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !27, metadata !DIExpression()), !dbg !29
   store i32 %i, i32* %i.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %i.addr, metadata !30, metadata !{!"0x102"}), !dbg !31
-  %this1 = load %class.A** %this.addr
-  %a = getelementptr inbounds %class.A* %this1, i32 0, i32 0, !dbg !31
-  %0 = load i32* %i.addr, align 4, !dbg !31
+  call void @llvm.dbg.declare(metadata i32* %i.addr, metadata !30, metadata !DIExpression()), !dbg !31
+  %this1 = load %class.A*, %class.A** %this.addr
+  %a = getelementptr inbounds %class.A, %class.A* %this1, i32 0, i32 0, !dbg !31
+  %0 = load i32, i32* %i.addr, align 4, !dbg !31
   store i32 %0, i32* %a, align 4, !dbg !31
   ret void, !dbg !31
 }
@@ -61,36 +61,35 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!23, !24}
 !llvm.ident = !{!25}
 
-!0 = !{!"0x11\004\00clang version 3.5 (trunk 199923) (llvm/trunk 199940)\000\00\000\00\001", !1, !2, !3, !13, !21, !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/baz.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"baz.cpp", !"/usr/local/google/home/echristo/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 (trunk 199923) (llvm/trunk 199940)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !13, globals: !21, imports: !2)
+!1 = !DIFile(filename: "baz.cpp", directory: "/usr/local/google/home/echristo/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2\00A\001\0032\0032\000\000\000", !1, null, null, !5, null, null, !"_ZTS1A"} ; [ DW_TAG_class_type ] [A] [line 1, size 32, align 32, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 1, size: 32, align: 32, file: !1, elements: !5, identifier: "_ZTS1A")
 !5 = !{!6, !8}
-!6 = !{!"0xd\00a\005\0032\0032\000\001", !1, !"_ZTS1A", !7} ; [ DW_TAG_member ] [a] [line 5, size 32, align 32, offset 0] [private] [from int]
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!8 = !{!"0x2e\00A\00A\00\003\000\000\000\006\00256\000\003", !1, !"_ZTS1A", !9, null, null, null, i32 0, !12} ; [ DW_TAG_subprogram ] [line 3] [A]
-!9 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 5, size: 32, align: 32, flags: DIFlagPrivate, file: !1, scope: !"_ZTS1A", baseType: !7)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DISubprogram(name: "A", line: 3, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !"_ZTS1A", type: !9)
+!9 = !DISubroutineType(types: !10)
 !10 = !{null, !11, !7}
-!11 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1A]
-!12 = !{i32 786468}
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1A")
 !13 = !{!14, !18, !19}
-!14 = !{!"0x2e\00__cxx_global_var_init\00__cxx_global_var_init\00\008\001\001\000\006\00256\000\008", !1, !15, !16, null, void ()* @__cxx_global_var_init, null, null, !2} ; [ DW_TAG_subprogram ] [line 8] [local] [def] [__cxx_global_var_init]
-!15 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/usr/local/google/home/echristo/tmp/baz.cpp]
-!16 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !17, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!14 = !DISubprogram(name: "__cxx_global_var_init", line: 8, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 8, file: !1, scope: !15, type: !16, function: void ()* @__cxx_global_var_init, variables: !2)
+!15 = !DIFile(filename: "baz.cpp", directory: "/usr/local/google/home/echristo/tmp")
+!16 = !DISubroutineType(types: !17)
 !17 = !{null}
-!18 = !{!"0x2e\00A\00A\00_ZN1AC2Ei\003\000\001\000\006\00256\000\003", !1, !"_ZTS1A", !9, null, void (%class.A*, i32)* @_ZN1AC2Ei, null, !8, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [A]
-!19 = !{!"0x2e\00\00\00_GLOBAL__I_a\003\001\001\000\006\0064\000\003", !1, !15, !20, null, void ()* @_GLOBAL__I_a, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [local] [def]
-!20 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!18 = !DISubprogram(name: "A", linkageName: "_ZN1AC2Ei", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !"_ZTS1A", type: !9, function: void (%class.A*, i32)* @_ZN1AC2Ei, declaration: !8, variables: !2)
+!19 = !DISubprogram(name: "", linkageName: "_GLOBAL__I_a", line: 3, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagArtificial, isOptimized: false, scopeLine: 3, file: !1, scope: !15, type: !20, function: void ()* @_GLOBAL__I_a, variables: !2)
+!20 = !DISubroutineType(types: !2)
 !21 = !{!22}
-!22 = !{!"0x34\00a\00a\00\008\000\001", null, !15, !4, %class.A* @a, null} ; [ DW_TAG_variable ] [a] [line 8] [def]
+!22 = !DIGlobalVariable(name: "a", line: 8, isLocal: false, isDefinition: true, scope: null, file: !15, type: !4, variable: %class.A* @a)
 !23 = !{i32 2, !"Dwarf Version", i32 4}
-!24 = !{i32 1, !"Debug Info Version", i32 2}
+!24 = !{i32 1, !"Debug Info Version", i32 3}
 !25 = !{!"clang version 3.5 (trunk 199923) (llvm/trunk 199940)"}
-!26 = !MDLocation(line: 8, scope: !14)
-!27 = !{!"0x101\00this\0016777216\001088", !18, null, !28} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!28 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1A]
-!29 = !MDLocation(line: 0, scope: !18)
-!30 = !{!"0x101\00i\0033554435\000", !18, !15, !7} ; [ DW_TAG_arg_variable ] [i] [line 3]
-!31 = !MDLocation(line: 3, scope: !18)
-!32 = !MDLocation(line: 3, scope: !19)
+!26 = !DILocation(line: 8, scope: !14)
+!27 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !18, type: !28)
+!28 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1A")
+!29 = !DILocation(line: 0, scope: !18)
+!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 3, arg: 2, scope: !18, file: !15, type: !7)
+!31 = !DILocation(line: 3, scope: !18)
+!32 = !DILocation(line: 3, scope: !19)
diff --git a/test/DebugInfo/X86/cu-ranges.ll b/test/DebugInfo/X86/cu-ranges.ll
index 0d872d872f9b..5611a31cd5fb 100644
--- a/test/DebugInfo/X86/cu-ranges.ll
+++ b/test/DebugInfo/X86/cu-ranges.ll
@@ -29,8 +29,8 @@ define i32 @foo(i32 %a) #0 {
 entry:
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !13, metadata !{!"0x102"}), !dbg !14
-  %0 = load i32* %a.addr, align 4, !dbg !14
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !13, metadata !DIExpression()), !dbg !14
+  %0 = load i32, i32* %a.addr, align 4, !dbg !14
   %add = add nsw i32 %0, 1, !dbg !14
   ret i32 %add, !dbg !14
 }
@@ -43,8 +43,8 @@ define i32 @bar(i32 %b) #0 {
 entry:
   %b.addr = alloca i32, align 4
   store i32 %b, i32* %b.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %b.addr, metadata !15, metadata !{!"0x102"}), !dbg !16
-  %0 = load i32* %b.addr, align 4, !dbg !16
+  call void @llvm.dbg.declare(metadata i32* %b.addr, metadata !15, metadata !DIExpression()), !dbg !16
+  %0 = load i32, i32* %b.addr, align 4, !dbg !16
   %add = add nsw i32 %0, 2, !dbg !16
   ret i32 %add, !dbg !16
 }
@@ -56,20 +56,20 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!10, !11}
 !llvm.ident = !{!12}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 (trunk 204164) (llvm/trunk 204183)\000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/z.c] [DW_LANG_C99]
-!1 = !{!"z.c", !"/usr/local/google/home/echristo"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 (trunk 204164) (llvm/trunk 204183)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "z.c", directory: "/usr/local/google/home/echristo")
 !2 = !{}
 !3 = !{!4, !9}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, i32 (i32)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/usr/local/google/home/echristo/z.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 (i32)* @foo, variables: !2)
+!5 = !DIFile(filename: "z.c", directory: "/usr/local/google/home/echristo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x2e\00bar\00bar\00\002\000\001\000\006\00256\000\002", !1, !5, !6, null, i32 (i32)* @bar, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [bar]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DISubprogram(name: "bar", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !6, function: i32 (i32)* @bar, variables: !2)
 !10 = !{i32 2, !"Dwarf Version", i32 4}
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!11 = !{i32 1, !"Debug Info Version", i32 3}
 !12 = !{!"clang version 3.5.0 (trunk 204164) (llvm/trunk 204183)"}
-!13 = !{!"0x101\00a\0016777217\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [a] [line 1]
-!14 = !MDLocation(line: 1, scope: !4)
-!15 = !{!"0x101\00b\0016777218\000", !9, !5, !8} ; [ DW_TAG_arg_variable ] [b] [line 2]
-!16 = !MDLocation(line: 2, scope: !9)
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 1, arg: 1, scope: !4, file: !5, type: !8)
+!14 = !DILocation(line: 1, scope: !4)
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 2, arg: 1, scope: !9, file: !5, type: !8)
+!16 = !DILocation(line: 2, scope: !9)
diff --git a/test/DebugInfo/X86/data_member_location.ll b/test/DebugInfo/X86/data_member_location.ll
index 4fdcc5ddcb92..c17c45bcc696 100644
--- a/test/DebugInfo/X86/data_member_location.ll
+++ b/test/DebugInfo/X86/data_member_location.ll
@@ -34,20 +34,20 @@
 !llvm.module.flags = !{!13, !15}
 !llvm.ident = !{!14}
 
-!0 = !{!"0x11\004\00clang version 3.4 \000\00\000\00\000", !1, !2, !3, !2, !10, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/data_member_location.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"data_member_location.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !2, globals: !10, imports: !2)
+!1 = !DIFile(filename: "data_member_location.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00foo\001\0064\0032\000\000\000", !1, null, null, !5, null, null, !"_ZTS3foo"} ; [ DW_TAG_structure_type ] [foo] [line 1, size 64, align 32, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo", line: 1, size: 64, align: 32, file: !1, elements: !5, identifier: "_ZTS3foo")
 !5 = !{!6, !8}
-!6 = !{!"0xd\00c\002\008\008\000\000", !1, !"_ZTS3foo", !7} ; [ DW_TAG_member ] [c] [line 2, size 8, align 8, offset 0] [from char]
-!7 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
-!8 = !{!"0xd\00i\003\0032\0032\0032\000", !1, !"_ZTS3foo", !9} ; [ DW_TAG_member ] [i] [line 3, size 32, align 32, offset 32] [from int]
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!6 = !DIDerivedType(tag: DW_TAG_member, name: "c", line: 2, size: 8, align: 8, file: !1, scope: !"_ZTS3foo", baseType: !7)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!8 = !DIDerivedType(tag: DW_TAG_member, name: "i", line: 3, size: 32, align: 32, offset: 32, file: !1, scope: !"_ZTS3foo", baseType: !9)
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !10 = !{!11}
-!11 = !{!"0x34\00f\00f\00\006\000\001", null, !12, !4, %struct.foo* @f, null} ; [ DW_TAG_variable ] [f] [line 6] [def]
-!12 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/tmp/dbginfo/data_member_location.cpp]
+!11 = !DIGlobalVariable(name: "f", line: 6, isLocal: false, isDefinition: true, scope: null, file: !12, type: !4, variable: %struct.foo* @f)
+!12 = !DIFile(filename: "data_member_location.cpp", directory: "/tmp/dbginfo")
 !13 = !{i32 2, !"Dwarf Version", i32 4}
 !14 = !{!"clang version 3.4 "}
 
-!15 = !{i32 1, !"Debug Info Version", i32 2}
+!15 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-at-specficiation.ll b/test/DebugInfo/X86/dbg-at-specficiation.ll
index 82696992729b..ccb5ab142cda 100644
--- a/test/DebugInfo/X86/dbg-at-specficiation.ll
+++ b/test/DebugInfo/X86/dbg-at-specficiation.ll
@@ -8,14 +8,14 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!12}
 
-!0 = !{!"0x11\0012\00clang version 3.0 (trunk 140253)\001\00\000\00\000", !11, !2, !2, !2, !3, null} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 140253)", isOptimized: true, emissionKind: 0, file: !11, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3)
 !2 = !{}
 !3 = !{!5}
-!5 = !{!"0x34\00a\00a\00\001\000\001", null, !6, !7, [10 x i32]* @a, null} ; [ DW_TAG_variable ]
-!6 = !{!"0x29", !11} ; [ DW_TAG_file_type ]
-!7 = !{!"0x1\00\000\00320\0032\000\000", null, null, !8, !9, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 320, align 32, offset 0] [from int]
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
+!5 = !DIGlobalVariable(name: "a", line: 1, isLocal: false, isDefinition: true, scope: null, file: !6, type: !7, variable: [10 x i32]* @a)
+!6 = !DIFile(filename: "x.c", directory: "/private/tmp")
+!7 = !DICompositeType(tag: DW_TAG_array_type, size: 320, align: 32, baseType: !8, elements: !9)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{!10}
-!10 = !{!"0x21\000\0010"}        ; [ DW_TAG_subrange_type ]
-!11 = !{!"x.c", !"/private/tmp"}
-!12 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !DISubrange(count: 10)
+!11 = !DIFile(filename: "x.c", directory: "/private/tmp")
+!12 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-byval-parameter.ll b/test/DebugInfo/X86/dbg-byval-parameter.ll
index 713781f38fb7..e07109e08f93 100644
--- a/test/DebugInfo/X86/dbg-byval-parameter.ll
+++ b/test/DebugInfo/X86/dbg-byval-parameter.ll
@@ -9,17 +9,17 @@ entry:
   %retval = alloca double                         ; <double*> [#uses=2]
   %0 = alloca double                              ; <double*> [#uses=2]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.declare(metadata %struct.Rect* %my_r0, metadata !0, metadata !{!"0x102"}), !dbg !15
-  %1 = getelementptr inbounds %struct.Rect* %my_r0, i32 0, i32 0, !dbg !16 ; <%struct.Pt*> [#uses=1]
-  %2 = getelementptr inbounds %struct.Pt* %1, i32 0, i32 0, !dbg !16 ; <double*> [#uses=1]
-  %3 = load double* %2, align 8, !dbg !16         ; <double> [#uses=1]
+  call void @llvm.dbg.declare(metadata %struct.Rect* %my_r0, metadata !0, metadata !DIExpression()), !dbg !15
+  %1 = getelementptr inbounds %struct.Rect, %struct.Rect* %my_r0, i32 0, i32 0, !dbg !16 ; <%struct.Pt*> [#uses=1]
+  %2 = getelementptr inbounds %struct.Pt, %struct.Pt* %1, i32 0, i32 0, !dbg !16 ; <double*> [#uses=1]
+  %3 = load double, double* %2, align 8, !dbg !16         ; <double> [#uses=1]
   store double %3, double* %0, align 8, !dbg !16
-  %4 = load double* %0, align 8, !dbg !16         ; <double> [#uses=1]
+  %4 = load double, double* %0, align 8, !dbg !16         ; <double> [#uses=1]
   store double %4, double* %retval, align 8, !dbg !16
   br label %return, !dbg !16
 
 return:                                           ; preds = %entry
-  %retval1 = load double* %retval, !dbg !16       ; <double> [#uses=1]
+  %retval1 = load double, double* %retval, !dbg !16       ; <double> [#uses=1]
   ret double %retval1, !dbg !16
 }
 
@@ -28,25 +28,25 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!3}
 !llvm.module.flags = !{!21}
 
-!0 = !{!"0x101\00my_r0\0011\000", !1, !2, !7} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00foo\00foo\00foo\0011\000\001\000\006\000\000\000", !19, !2, !4, null, double (%struct.Rect*)* @foo, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !19} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\000\00\000\00\000", !19, !20, !20, !18, null,  null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !19, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "my_r0", line: 11, arg: 0, scope: !1, file: !2, type: !7)
+!1 = !DISubprogram(name: "foo", linkageName: "foo", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !19, scope: !2, type: !4, function: double (%struct.Rect*)* @foo)
+!2 = !DIFile(filename: "b2.c", directory: "/tmp/")
+!3 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: false, emissionKind: 0, file: !19, enums: !20, retainedTypes: !20, subprograms: !18, imports:  null)
+!4 = !DISubroutineType(types: !5)
 !5 = !{!6, !7}
-!6 = !{!"0x24\00double\000\0064\0064\000\000\004", !19, !2} ; [ DW_TAG_base_type ]
-!7 = !{!"0x13\00Rect\006\00256\0064\000\000\000", !19, !2, null, !8, null, null, null} ; [ DW_TAG_structure_type ] [Rect] [line 6, size 256, align 64, offset 0] [def] [from ]
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 64, encoding: DW_ATE_float)
+!7 = !DICompositeType(tag: DW_TAG_structure_type, name: "Rect", line: 6, size: 256, align: 64, file: !19, scope: !2, elements: !8)
 !8 = !{!9, !14}
-!9 = !{!"0xd\00P1\007\00128\0064\000\000", !19, !7, !10} ; [ DW_TAG_member ]
-!10 = !{!"0x13\00Pt\001\00128\0064\000\000\000", !19, !2, null, !11, null, null, null} ; [ DW_TAG_structure_type ] [Pt] [line 1, size 128, align 64, offset 0] [def] [from ]
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "P1", line: 7, size: 128, align: 64, file: !19, scope: !7, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_structure_type, name: "Pt", line: 1, size: 128, align: 64, file: !19, scope: !2, elements: !11)
 !11 = !{!12, !13}
-!12 = !{!"0xd\00x\002\0064\0064\000\000", !19, !10, !6} ; [ DW_TAG_member ]
-!13 = !{!"0xd\00y\003\0064\0064\0064\000", !19, !10, !6} ; [ DW_TAG_member ]
-!14 = !{!"0xd\00P2\008\00128\0064\00128\000", !19, !7, !10} ; [ DW_TAG_member ]
-!15 = !MDLocation(line: 11, scope: !1)
-!16 = !MDLocation(line: 12, scope: !17)
-!17 = !{!"0xb\0011\000\000", !19, !1} ; [ DW_TAG_lexical_block ]
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 2, size: 64, align: 64, file: !19, scope: !10, baseType: !6)
+!13 = !DIDerivedType(tag: DW_TAG_member, name: "y", line: 3, size: 64, align: 64, offset: 64, file: !19, scope: !10, baseType: !6)
+!14 = !DIDerivedType(tag: DW_TAG_member, name: "P2", line: 8, size: 128, align: 64, offset: 128, file: !19, scope: !7, baseType: !10)
+!15 = !DILocation(line: 11, scope: !1)
+!16 = !DILocation(line: 12, scope: !17)
+!17 = distinct !DILexicalBlock(line: 11, column: 0, file: !19, scope: !1)
 !18 = !{!1}
-!19 = !{!"b2.c", !"/tmp/"}
-!20 = !{i32 0}
-!21 = !{i32 1, !"Debug Info Version", i32 2}
+!19 = !DIFile(filename: "b2.c", directory: "/tmp/")
+!20 = !{}
+!21 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-const-int.ll b/test/DebugInfo/X86/dbg-const-int.ll
index 18abbdd5c21d..8482abf373eb 100644
--- a/test/DebugInfo/X86/dbg-const-int.ll
+++ b/test/DebugInfo/X86/dbg-const-int.ll
@@ -12,7 +12,7 @@ target triple = "x86_64-apple-macosx10.6.7"
 
 define i32 @foo() nounwind uwtable readnone optsize ssp {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 42, i64 0, metadata !6, metadata !{!"0x102"}), !dbg !9
+  tail call void @llvm.dbg.value(metadata i32 42, i64 0, metadata !6, metadata !DIExpression()), !dbg !9
   ret i32 42, !dbg !10
 }
 
@@ -21,19 +21,19 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!15}
 
-!0 = !{!"0x11\0012\00clang version 3.0 (trunk 132191)\001\00\000\00\000", !13, !14, !14, !11, null,  null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\000\001\000", !13, !2, !3, null, i32 ()* @foo, null, null, !12} ; [ DW_TAG_subprogram ] [line 1] [def] [scope 0] [foo]
-!2 = !{!"0x29", !13} ; [ DW_TAG_file_type ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !13, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 132191)", isOptimized: true, emissionKind: 0, file: !13, enums: !14, retainedTypes: !14, subprograms: !11, imports:  null)
+!1 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, file: !13, scope: !2, type: !3, function: i32 ()* @foo, variables: !12)
+!2 = !DIFile(filename: "a.c", directory: "/private/tmp")
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ]
-!6 = !{!"0x100\00i\002\000", !7, !2, !5} ; [ DW_TAG_auto_variable ]
-!7 = !{!"0xb\001\0011\000", !13, !1} ; [ DW_TAG_lexical_block ]
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 2, scope: !7, file: !2, type: !5)
+!7 = distinct !DILexicalBlock(line: 1, column: 11, file: !13, scope: !1)
 !8 = !{i32 42}
-!9 = !MDLocation(line: 2, column: 12, scope: !7)
-!10 = !MDLocation(line: 3, column: 2, scope: !7)
+!9 = !DILocation(line: 2, column: 12, scope: !7)
+!10 = !DILocation(line: 3, column: 2, scope: !7)
 !11 = !{!1}
 !12 = !{!6}
-!13 = !{!"a.c", !"/private/tmp"}
-!14 = !{i32 0}
-!15 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = !DIFile(filename: "a.c", directory: "/private/tmp")
+!14 = !{}
+!15 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-const.ll b/test/DebugInfo/X86/dbg-const.ll
index 755565dbf954..27a0eabfe493 100644
--- a/test/DebugInfo/X86/dbg-const.ll
+++ b/test/DebugInfo/X86/dbg-const.ll
@@ -17,9 +17,9 @@ target triple = "x86_64-apple-darwin10.0.0"
 ;CHECK-NEXT:  .byte	42
 define i32 @foobar() nounwind readonly noinline ssp {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 42, i64 0, metadata !6, metadata !{!"0x102"}), !dbg !9
+  tail call void @llvm.dbg.value(metadata i32 42, i64 0, metadata !6, metadata !DIExpression()), !dbg !9
   %call = tail call i32 @bar(), !dbg !11
-  tail call void @llvm.dbg.value(metadata i32 %call, i64 0, metadata !6, metadata !{!"0x102"}), !dbg !11
+  tail call void @llvm.dbg.value(metadata i32 %call, i64 0, metadata !6, metadata !DIExpression()), !dbg !11
   %call2 = tail call i32 @bar(), !dbg !11
   %add = add nsw i32 %call2, %call, !dbg !12
   ret i32 %add, !dbg !10
@@ -31,21 +31,21 @@ declare i32 @bar() nounwind readnone
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!17}
 
-!0 = !{!"0x2e\00foobar\00foobar\00foobar\0012\000\001\000\006\000\001\000", !15, !1, !3, null, i32 ()* @foobar, null, null, !14} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !15} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 2.9 (trunk 114183)\001\00\000\00\001", !15, !16, !16, !13, null,  null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !15, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "foobar", linkageName: "foobar", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, file: !15, scope: !1, type: !3, function: i32 ()* @foobar, variables: !14)
+!1 = !DIFile(filename: "mu.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 2.9 (trunk 114183)", isOptimized: true, emissionKind: 1, file: !15, enums: !16, retainedTypes: !16, subprograms: !13, imports:  null)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", !15, !1} ; [ DW_TAG_base_type ]
-!6 = !{!"0x100\00j\0015\000", !7, !1, !5} ; [ DW_TAG_auto_variable ]
-!7 = !{!"0xb\0012\0052\000", !15, !0} ; [ DW_TAG_lexical_block ]
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 15, scope: !7, file: !1, type: !5)
+!7 = distinct !DILexicalBlock(line: 12, column: 52, file: !15, scope: !0)
 !8 = !{i32 42}
-!9 = !MDLocation(line: 15, column: 12, scope: !7)
-!10 = !MDLocation(line: 23, column: 3, scope: !7)
-!11 = !MDLocation(line: 17, column: 3, scope: !7)
-!12 = !MDLocation(line: 18, column: 3, scope: !7)
+!9 = !DILocation(line: 15, column: 12, scope: !7)
+!10 = !DILocation(line: 23, column: 3, scope: !7)
+!11 = !DILocation(line: 17, column: 3, scope: !7)
+!12 = !DILocation(line: 18, column: 3, scope: !7)
 !13 = !{!0}
 !14 = !{!6}
-!15 = !{!"mu.c", !"/private/tmp"}
-!16 = !{i32 0}
-!17 = !{i32 1, !"Debug Info Version", i32 2}
+!15 = !DIFile(filename: "mu.c", directory: "/private/tmp")
+!16 = !{}
+!17 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-declare-arg.ll b/test/DebugInfo/X86/dbg-declare-arg.ll
index ef975dd9db8d..85ff4b920ad1 100644
--- a/test/DebugInfo/X86/dbg-declare-arg.ll
+++ b/test/DebugInfo/X86/dbg-declare-arg.ll
@@ -14,28 +14,28 @@ entry:
   %nrvo = alloca i1
   %cleanup.dest.slot = alloca i32
   store i32 %i, i32* %i.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %i.addr, metadata !26, metadata !{!"0x102"}), !dbg !27
-  call void @llvm.dbg.declare(metadata i32* %j, metadata !28, metadata !{!"0x102"}), !dbg !30
+  call void @llvm.dbg.declare(metadata i32* %i.addr, metadata !26, metadata !DIExpression()), !dbg !27
+  call void @llvm.dbg.declare(metadata i32* %j, metadata !28, metadata !DIExpression()), !dbg !30
   store i32 0, i32* %j, align 4, !dbg !31
-  %tmp = load i32* %i.addr, align 4, !dbg !32
+  %tmp = load i32, i32* %i.addr, align 4, !dbg !32
   %cmp = icmp eq i32 %tmp, 42, !dbg !32
   br i1 %cmp, label %if.then, label %if.end, !dbg !32
 
 if.then:                                          ; preds = %entry
-  %tmp1 = load i32* %i.addr, align 4, !dbg !33
+  %tmp1 = load i32, i32* %i.addr, align 4, !dbg !33
   %add = add nsw i32 %tmp1, 1, !dbg !33
   store i32 %add, i32* %j, align 4, !dbg !33
   br label %if.end, !dbg !35
 
 if.end:                                           ; preds = %if.then, %entry
   store i1 false, i1* %nrvo, !dbg !36
-  call void @llvm.dbg.declare(metadata %class.A* %agg.result, metadata !37, metadata !{!"0x102"}), !dbg !39
-  %tmp2 = load i32* %j, align 4, !dbg !40
-  %x = getelementptr inbounds %class.A* %agg.result, i32 0, i32 0, !dbg !40
+  call void @llvm.dbg.declare(metadata %class.A* %agg.result, metadata !37, metadata !DIExpression()), !dbg !39
+  %tmp2 = load i32, i32* %j, align 4, !dbg !40
+  %x = getelementptr inbounds %class.A, %class.A* %agg.result, i32 0, i32 0, !dbg !40
   store i32 %tmp2, i32* %x, align 4, !dbg !40
   store i1 true, i1* %nrvo, !dbg !41
   store i32 1, i32* %cleanup.dest.slot
-  %nrvo.val = load i1* %nrvo, !dbg !42
+  %nrvo.val = load i1, i1* %nrvo, !dbg !42
   br i1 %nrvo.val, label %nrvo.skipdtor, label %nrvo.unused, !dbg !42
 
 nrvo.unused:                                      ; preds = %if.end
@@ -52,8 +52,8 @@ define linkonce_odr void @_ZN1AD1Ev(%class.A* %this) unnamed_addr ssp align 2 {
 entry:
   %this.addr = alloca %class.A*, align 8
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !43, metadata !{!"0x102"}), !dbg !44
-  %this1 = load %class.A** %this.addr
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !43, metadata !DIExpression()), !dbg !44
+  %this1 = load %class.A*, %class.A** %this.addr
   call void @_ZN1AD2Ev(%class.A* %this1)
   ret void, !dbg !45
 }
@@ -62,9 +62,9 @@ define linkonce_odr void @_ZN1AD2Ev(%class.A* %this) unnamed_addr nounwind ssp a
 entry:
   %this.addr = alloca %class.A*, align 8
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !46, metadata !{!"0x102"}), !dbg !47
-  %this1 = load %class.A** %this.addr
-  %x = getelementptr inbounds %class.A* %this1, i32 0, i32 0, !dbg !48
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !46, metadata !DIExpression()), !dbg !47
+  %this1 = load %class.A*, %class.A** %this.addr
+  %x = getelementptr inbounds %class.A, %class.A* %this1, i32 0, i32 0, !dbg !48
   store i32 1, i32* %x, align 4, !dbg !48
   ret void, !dbg !48
 }
@@ -72,56 +72,56 @@ entry:
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!52}
 
-!0 = !{!"0x2e\00~A\00~A\00\002\000\000\000\006\00256\000\000", !51, !1, !11, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x2\00A\002\00128\0032\000\000\000", !51, !2, null, !4, null, null, null} ; [ DW_TAG_class_type ] [A] [line 2, size 128, align 32, offset 0] [def] [from ]
-!2 = !{!"0x11\004\00clang version 3.0 (trunk 130127)\000\00\000\00\001", !51, !24, !24, !50, null, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x29", !51} ; [ DW_TAG_file_type ]
+!0 = !DISubprogram(name: "~A", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !51, scope: !1, type: !11)
+!1 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 2, size: 128, align: 32, file: !51, scope: !2, elements: !4)
+!2 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.0 (trunk 130127)", isOptimized: false, emissionKind: 1, file: !51, enums: !{}, retainedTypes: !{}, subprograms: !50)
+!3 = !DIFile(filename: "a.cc", directory: "/private/tmp")
 !4 = !{!5, !7, !8, !9, !0, !10, !14}
-!5 = !{!"0xd\00x\002\0032\0032\000\000", !51, !3, !6} ; [ DW_TAG_member ]
-!6 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ]
-!7 = !{!"0xd\00y\002\0032\0032\0032\000", !51, !3, !6} ; [ DW_TAG_member ]
-!8 = !{!"0xd\00z\002\0032\0032\0064\000", !51, !3, !6} ; [ DW_TAG_member ]
-!9 = !{!"0xd\00o\002\0032\0032\0096\000", !51, !3, !6} ; [ DW_TAG_member ]
-!10 = !{!"0x2e\00A\00A\00\002\000\000\000\006\00320\000\000", !51, !1, !11, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!11 = !{!"0x15\00\000\000\000\000\000\000", !51, !3, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 2, size: 32, align: 32, file: !51, scope: !3, baseType: !6)
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "y", line: 2, size: 32, align: 32, offset: 32, file: !51, scope: !3, baseType: !6)
+!8 = !DIDerivedType(tag: DW_TAG_member, name: "z", line: 2, size: 32, align: 32, offset: 64, file: !51, scope: !3, baseType: !6)
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "o", line: 2, size: 32, align: 32, offset: 96, file: !51, scope: !3, baseType: !6)
+!10 = !DISubprogram(name: "A", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, file: !51, scope: !1, type: !11)
+!11 = !DISubroutineType(types: !12)
 !12 = !{null, !13}
-!13 = !{!"0xf\00\000\0064\0064\000\0064", !2, null, !1} ; [ DW_TAG_pointer_type ]
-!14 = !{!"0x2e\00A\00A\00\002\000\000\000\006\00320\000\000", !51, !1, !15, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!15 = !{!"0x15\00\000\000\000\000\000\000", !51, !3, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, file: !3, baseType: !1)
+!14 = !DISubprogram(name: "A", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, file: !51, scope: !1, type: !15)
+!15 = !DISubroutineType(types: !16)
 !16 = !{null, !13, !17}
-!17 = !{!"0x10\00\000\000\000\000\000", null, !2, !18} ; [ DW_TAG_reference_type ]
-!18 = !{!"0x26\00\000\000\000\000\000", !2, null, !1} ; [ DW_TAG_const_type ]
-!19 = !{!"0x2e\00foo\00foo\00_Z3fooi\004\000\001\000\006\00256\000\000", !51, !3, !20, null, void (%class.A*, i32)* @_Z3fooi, null, null, null} ; [ DW_TAG_subprogram ] [line 4] [def] [scope 0] [foo]
-!20 = !{!"0x15\00\000\000\000\000\000\000", !51, !3, null, !21, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!17 = !DIDerivedType(tag: DW_TAG_reference_type, scope: !2, baseType: !18)
+!18 = !DIDerivedType(tag: DW_TAG_const_type, file: !3, baseType: !1)
+!19 = !DISubprogram(name: "foo", linkageName: "_Z3fooi", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !51, scope: !3, type: !20, function: void (%class.A*, i32)* @_Z3fooi)
+!20 = !DISubroutineType(types: !21)
 !21 = !{!1}
-!22 = !{!"0x2e\00~A\00~A\00_ZN1AD1Ev\002\000\001\000\006\00256\000\000", !51, !3, !23, null, void (%class.A*)* @_ZN1AD1Ev, null, null, null} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 0] [~A]
-!23 = !{!"0x15\00\000\000\000\000\000\000", !51, !3, null, !24, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!22 = !DISubprogram(name: "~A", linkageName: "_ZN1AD1Ev", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !51, scope: !3, type: !23, function: void (%class.A*)* @_ZN1AD1Ev)
+!23 = !DISubroutineType(types: !24)
 !24 = !{null}
-!25 = !{!"0x2e\00~A\00~A\00_ZN1AD2Ev\002\000\001\000\006\00256\000\000", !51, !3, !23, null, void (%class.A*)* @_ZN1AD2Ev, null, null, null} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 0] [~A]
-!26 = !{!"0x101\00i\0016777220\000", !19, !3, !6} ; [ DW_TAG_arg_variable ]
-!27 = !MDLocation(line: 4, column: 11, scope: !19)
-!28 = !{!"0x100\00j\005\000", !29, !3, !6} ; [ DW_TAG_auto_variable ]
-!29 = !{!"0xb\004\0014\000", !51, !19} ; [ DW_TAG_lexical_block ]
-!30 = !MDLocation(line: 5, column: 7, scope: !29)
-!31 = !MDLocation(line: 5, column: 12, scope: !29)
-!32 = !MDLocation(line: 6, column: 3, scope: !29)
-!33 = !MDLocation(line: 7, column: 5, scope: !34)
-!34 = !{!"0xb\006\0016\001", !51, !29} ; [ DW_TAG_lexical_block ]
-!35 = !MDLocation(line: 8, column: 3, scope: !34)
-!36 = !MDLocation(line: 9, column: 9, scope: !29)
-!37 = !{!"0x100\00my_a\009\000", !29, !3, !38} ; [ DW_TAG_auto_variable ]
-!38 = !{!"0x10\00\000\000\000\000\000", !2, null, !1} ; [ DW_TAG_reference_type ]
-!39 = !MDLocation(line: 9, column: 5, scope: !29)
-!40 = !MDLocation(line: 10, column: 3, scope: !29)
-!41 = !MDLocation(line: 11, column: 3, scope: !29)
-!42 = !MDLocation(line: 12, column: 1, scope: !29)
-!43 = !{!"0x101\00this\0016777218\0064", !22, !3, !13} ; [ DW_TAG_arg_variable ]
-!44 = !MDLocation(line: 2, column: 47, scope: !22)
-!45 = !MDLocation(line: 2, column: 61, scope: !22)
-!46 = !{!"0x101\00this\0016777218\0064", !25, !3, !13} ; [ DW_TAG_arg_variable ]
-!47 = !MDLocation(line: 2, column: 47, scope: !25)
-!48 = !MDLocation(line: 2, column: 54, scope: !49)
-!49 = !{!"0xb\002\0052\002", !51, !25} ; [ DW_TAG_lexical_block ]
+!25 = !DISubprogram(name: "~A", linkageName: "_ZN1AD2Ev", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !51, scope: !3, type: !23, function: void (%class.A*)* @_ZN1AD2Ev)
+!26 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 4, arg: 1, scope: !19, file: !3, type: !6)
+!27 = !DILocation(line: 4, column: 11, scope: !19)
+!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 5, scope: !29, file: !3, type: !6)
+!29 = distinct !DILexicalBlock(line: 4, column: 14, file: !51, scope: !19)
+!30 = !DILocation(line: 5, column: 7, scope: !29)
+!31 = !DILocation(line: 5, column: 12, scope: !29)
+!32 = !DILocation(line: 6, column: 3, scope: !29)
+!33 = !DILocation(line: 7, column: 5, scope: !34)
+!34 = distinct !DILexicalBlock(line: 6, column: 16, file: !51, scope: !29)
+!35 = !DILocation(line: 8, column: 3, scope: !34)
+!36 = !DILocation(line: 9, column: 9, scope: !29)
+!37 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "my_a", line: 9, scope: !29, file: !3, type: !38)
+!38 = !DIDerivedType(tag: DW_TAG_reference_type, file: !3, baseType: !1)
+!39 = !DILocation(line: 9, column: 5, scope: !29)
+!40 = !DILocation(line: 10, column: 3, scope: !29)
+!41 = !DILocation(line: 11, column: 3, scope: !29)
+!42 = !DILocation(line: 12, column: 1, scope: !29)
+!43 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 2, arg: 1, flags: DIFlagArtificial, scope: !22, file: !3, type: !13)
+!44 = !DILocation(line: 2, column: 47, scope: !22)
+!45 = !DILocation(line: 2, column: 61, scope: !22)
+!46 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 2, arg: 1, flags: DIFlagArtificial, scope: !25, file: !3, type: !13)
+!47 = !DILocation(line: 2, column: 47, scope: !25)
+!48 = !DILocation(line: 2, column: 54, scope: !49)
+!49 = distinct !DILexicalBlock(line: 2, column: 52, file: !51, scope: !25)
 !50 = !{!19, !22, !25}
-!51 = !{!"a.cc", !"/private/tmp"}
-!52 = !{i32 1, !"Debug Info Version", i32 2}
+!51 = !DIFile(filename: "a.cc", directory: "/private/tmp")
+!52 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-declare.ll b/test/DebugInfo/X86/dbg-declare.ll
index 2ede97b22023..a1420a0ba2ef 100644
--- a/test/DebugInfo/X86/dbg-declare.ll
+++ b/test/DebugInfo/X86/dbg-declare.ll
@@ -7,16 +7,16 @@ entry:
   %saved_stack = alloca i8*
   %cleanup.dest.slot = alloca i32
   store i32* %x, i32** %x.addr, align 8
-  call void @llvm.dbg.declare(metadata i32** %x.addr, metadata !14, metadata !{!"0x102"}), !dbg !15
-  %0 = load i32** %x.addr, align 8, !dbg !16
-  %1 = load i32* %0, align 4, !dbg !16
+  call void @llvm.dbg.declare(metadata i32** %x.addr, metadata !14, metadata !DIExpression()), !dbg !15
+  %0 = load i32*, i32** %x.addr, align 8, !dbg !16
+  %1 = load i32, i32* %0, align 4, !dbg !16
   %2 = zext i32 %1 to i64, !dbg !16
   %3 = call i8* @llvm.stacksave(), !dbg !16
   store i8* %3, i8** %saved_stack, !dbg !16
   %vla = alloca i8, i64 %2, align 16, !dbg !16
-  call void @llvm.dbg.declare(metadata i8* %vla, metadata !18, metadata !{!"0x102"}), !dbg !23
+  call void @llvm.dbg.declare(metadata i8* %vla, metadata !18, metadata !DIExpression()), !dbg !23
   store i32 1, i32* %cleanup.dest.slot
-  %4 = load i8** %saved_stack, !dbg !24
+  %4 = load i8*, i8** %saved_stack, !dbg !24
   call void @llvm.stackrestore(i8* %4), !dbg !24
   ret i32 0, !dbg !25
 }
@@ -30,27 +30,27 @@ declare void @llvm.stackrestore(i8*) nounwind
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!27}
 
-!0 = !{!"0x11\0012\00clang version 3.1 (trunk 153698)\000\00\000\00\000", !26, !1, !1, !3, !1, null} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.1 (trunk 153698)", isOptimized: false, emissionKind: 0, file: !26, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00foo\00foo\00\006\000\001\000\006\00256\000\000", !26, !0, !7, null, i32 (i32*)* @foo, null, null, null} ; [ DW_TAG_subprogram ]
-!6 = !{!"0x29", !26} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "foo", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !26, scope: !0, type: !7, function: i32 (i32*)* @foo)
+!6 = !DIFile(filename: "20020104-2.c", directory: "/Volumes/Sandbox/llvm")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !10}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!10 = !{!"0xf\00\000\0064\0064\000\000", null, null, !11} ; [ DW_TAG_pointer_type ]
-!11 = !{!"0x26\00\000\000\000\000\000", null, null, !9} ; [ DW_TAG_const_type ]
-!14 = !{!"0x101\00x\0016777221\000", !5, !6, !10} ; [ DW_TAG_arg_variable ]
-!15 = !MDLocation(line: 5, column: 21, scope: !5)
-!16 = !MDLocation(line: 7, column: 13, scope: !17)
-!17 = !{!"0xb\006\001\000", !26, !5} ; [ DW_TAG_lexical_block ]
-!18 = !{!"0x100\00a\007\000", !17, !6, !19} ; [ DW_TAG_auto_variable ]
-!19 = !{!"0x1\00\000\000\008\000\000", null, null, !20, !21, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 0, align 8, offset 0] [from char]
-!20 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !11)
+!11 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !9)
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 5, arg: 1, scope: !5, file: !6, type: !10)
+!15 = !DILocation(line: 5, column: 21, scope: !5)
+!16 = !DILocation(line: 7, column: 13, scope: !17)
+!17 = distinct !DILexicalBlock(line: 6, column: 1, file: !26, scope: !5)
+!18 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 7, scope: !17, file: !6, type: !19)
+!19 = !DICompositeType(tag: DW_TAG_array_type, align: 8, baseType: !20, elements: !21)
+!20 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
 !21 = !{!22}
-!22 = !{!"0x21\000\00-1"}        ; [ DW_TAG_subrange_type ]
-!23 = !MDLocation(line: 7, column: 8, scope: !17)
-!24 = !MDLocation(line: 9, column: 1, scope: !17)
-!25 = !MDLocation(line: 8, column: 3, scope: !17)
-!26 = !{!"20020104-2.c", !"/Volumes/Sandbox/llvm"}
-!27 = !{i32 1, !"Debug Info Version", i32 2}
+!22 = !DISubrange(count: -1)
+!23 = !DILocation(line: 7, column: 8, scope: !17)
+!24 = !DILocation(line: 9, column: 1, scope: !17)
+!25 = !DILocation(line: 8, column: 3, scope: !17)
+!26 = !DIFile(filename: "20020104-2.c", directory: "/Volumes/Sandbox/llvm")
+!27 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-file-name.ll b/test/DebugInfo/X86/dbg-file-name.ll
index 94fdb3730ded..cc18c0804db4 100644
--- a/test/DebugInfo/X86/dbg-file-name.ll
+++ b/test/DebugInfo/X86/dbg-file-name.ll
@@ -12,13 +12,13 @@ define i32 @main() nounwind {
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!12}
 
-!1 = !{!"0x29", !10} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\001\00LLVM build 00\001\00\000\00\000", !10, !11, !11, !9, null, null} ; [ DW_TAG_compile_unit ]
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", !10, !1} ; [ DW_TAG_base_type ]
-!6 = !{!"0x2e\00main\00main\00main\009\000\001\000\006\00256\000\000", !10, !1, !7, null, i32 ()* @main, null, null, null} ; [ DW_TAG_subprogram ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", !10, !1, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!1 = !DIFile(filename: "simple.c", directory: "/Users/manav/one/two")
+!2 = !DICompileUnit(language: DW_LANG_C89, producer: "LLVM build 00", isOptimized: true, emissionKind: 0, file: !10, enums: !11, retainedTypes: !11, subprograms: !9)
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DISubprogram(name: "main", linkageName: "main", line: 9, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !10, scope: !1, type: !7, function: i32 ()* @main)
+!7 = !DISubroutineType(types: !8)
 !8 = !{!5}
 !9 = !{!6}
-!10 = !{!"simple.c", !"/Users/manav/one/two"}
-!11 = !{i32 0}
-!12 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !DIFile(filename: "simple.c", directory: "/Users/manav/one/two")
+!11 = !{}
+!12 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-i128-const.ll b/test/DebugInfo/X86/dbg-i128-const.ll
index 71654cb56ce9..de804faabf4a 100644
--- a/test/DebugInfo/X86/dbg-i128-const.ll
+++ b/test/DebugInfo/X86/dbg-i128-const.ll
@@ -1,11 +1,12 @@
 ; RUN: llc -mtriple=x86_64-linux < %s | FileCheck %s
 
+; CHECK: .section        .debug_info
 ; CHECK: DW_AT_const_value
 ; CHECK-NEXT: 42
 
 define i128 @__foo(i128 %a, i128 %b) nounwind {
 entry:
-  tail call void @llvm.dbg.value(metadata i128 42 , i64 0, metadata !1, metadata !{!"0x102"}), !dbg !11
+  tail call void @llvm.dbg.value(metadata i128 42 , i64 0, metadata !1, metadata !DIExpression()), !dbg !11
   %add = add i128 %a, %b, !dbg !11
   ret i128 %add, !dbg !11
 }
@@ -16,19 +17,19 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.module.flags = !{!16}
 
 !0 = !{i128 42 }
-!1 = !{!"0x100\00MAX\0029\000", !2, !4, !8} ; [ DW_TAG_auto_variable ]
-!2 = !{!"0xb\0026\000\000", !13, !3} ; [ DW_TAG_lexical_block ]
-!3 = !{!"0x2e\00__foo\00__foo\00__foo\0026\000\001\000\006\000\000\0026", !13, !4, !6, null, i128 (i128, i128)* @__foo, null, null, null} ; [ DW_TAG_subprogram ]
-!4 = !{!"0x29", !13} ; [ DW_TAG_file_type ]
-!5 = !{!"0x11\001\00clang\001\00\000\00\000", !13, !15, !15, !12, null,  null} ; [ DW_TAG_compile_unit ]
-!6 = !{!"0x15\00\000\000\000\000\000\000", !13, !4, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!1 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "MAX", line: 29, scope: !2, file: !4, type: !8)
+!2 = distinct !DILexicalBlock(line: 26, column: 0, file: !13, scope: !3)
+!3 = !DISubprogram(name: "__foo", linkageName: "__foo", line: 26, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 26, file: !13, scope: !4, type: !6, function: i128 (i128, i128)* @__foo)
+!4 = !DIFile(filename: "foo.c", directory: "/tmp")
+!5 = !DICompileUnit(language: DW_LANG_C89, producer: "clang", isOptimized: true, emissionKind: 0, file: !13, enums: !15, retainedTypes: !15, subprograms: !12, imports:  null)
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8, !8}
-!8 = !{!"0x16\00ti_int\0078\000\000\000\000", !14, !4, !10} ; [ DW_TAG_typedef ]
-!9 = !{!"0x29", !14} ; [ DW_TAG_file_type ]
-!10 = !{!"0x24\00\000\00128\00128\000\000\005", !13, !4} ; [ DW_TAG_base_type ]
-!11 = !MDLocation(line: 29, scope: !2)
+!8 = !DIDerivedType(tag: DW_TAG_typedef, name: "ti_int", line: 78, file: !14, scope: !4, baseType: !10)
+!9 = !DIFile(filename: "myint.h", directory: "/tmp")
+!10 = !DIBasicType(tag: DW_TAG_base_type, size: 128, align: 128, encoding: DW_ATE_signed)
+!11 = !DILocation(line: 29, scope: !2)
 !12 = !{!3}
-!13 = !{!"foo.c", !"/tmp"}
-!14 = !{!"myint.h", !"/tmp"}
-!15 = !{i32 0}
-!16 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = !DIFile(filename: "foo.c", directory: "/tmp")
+!14 = !DIFile(filename: "myint.h", directory: "/tmp")
+!15 = !{}
+!16 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-merge-loc-entry.ll b/test/DebugInfo/X86/dbg-merge-loc-entry.ll
index 0d562223b8c3..14265139b0fd 100644
--- a/test/DebugInfo/X86/dbg-merge-loc-entry.ll
+++ b/test/DebugInfo/X86/dbg-merge-loc-entry.ll
@@ -14,8 +14,8 @@ target triple = "x86_64-apple-darwin8"
 
 define hidden i128 @__divti3(i128 %u, i128 %v) nounwind readnone {
 entry:
-  tail call void @llvm.dbg.value(metadata i128 %u, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !15
-  tail call void @llvm.dbg.value(metadata i64 0, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !21
+  tail call void @llvm.dbg.value(metadata i128 %u, i64 0, metadata !14, metadata !DIExpression()), !dbg !15
+  tail call void @llvm.dbg.value(metadata i64 0, i64 0, metadata !17, metadata !DIExpression()), !dbg !21
   br i1 undef, label %bb2, label %bb4, !dbg !22
 
 bb2:                                              ; preds = %entry
@@ -40,36 +40,36 @@ declare %0 @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!32}
 
-!0 = !{!"0x2e\00__udivmodti4\00__udivmodti4\00\00879\001\001\000\006\00256\001\00879", !29, !1, !3, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !29} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\001\00\000\00\000", !29, !31, !31, !28, null,  null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !29, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "__udivmodti4", line: 879, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 879, file: !29, scope: !1, type: !3)
+!1 = !DIFile(filename: "foobar.c", directory: "/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 0, file: !29, enums: !31, retainedTypes: !31, subprograms: !28, imports:  null)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5, !5, !5, !8}
-!5 = !{!"0x16\00UTItype\00166\000\000\000\000", !30, !6, !7} ; [ DW_TAG_typedef ]
-!6 = !{!"0x29", !30} ; [ DW_TAG_file_type ]
-!7 = !{!"0x24\00\000\00128\00128\000\000\007", !29, !1} ; [ DW_TAG_base_type ]
-!8 = !{!"0xf\00\000\0064\0064\000\000", !29, !1, !5} ; [ DW_TAG_pointer_type ]
-!9 = !{!"0x2e\00__divti3\00__divti3\00__divti3\001094\000\001\000\006\00256\001\001094", !29, !1, !10, null, i128 (i128, i128)* @__divti3, null, null, null} ; [ DW_TAG_subprogram ]
-!10 = !{!"0x15\00\000\000\000\000\000\000", !29, !1, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DIDerivedType(tag: DW_TAG_typedef, name: "UTItype", line: 166, file: !30, scope: !6, baseType: !7)
+!6 = !DIFile(filename: "foobar.h", directory: "/tmp")
+!7 = !DIBasicType(tag: DW_TAG_base_type, size: 128, align: 128, encoding: DW_ATE_unsigned)
+!8 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !29, scope: !1, baseType: !5)
+!9 = !DISubprogram(name: "__divti3", linkageName: "__divti3", line: 1094, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1094, file: !29, scope: !1, type: !10, function: i128 (i128, i128)* @__divti3)
+!10 = !DISubroutineType(types: !11)
 !11 = !{!12, !12, !12}
-!12 = !{!"0x16\00TItype\00160\000\000\000\000", !30, !6, !13} ; [ DW_TAG_typedef ]
-!13 = !{!"0x24\00\000\00128\00128\000\000\005", !29, !1} ; [ DW_TAG_base_type ]
-!14 = !{!"0x101\00u\001093\000", !9, !1, !12} ; [ DW_TAG_arg_variable ]
-!15 = !MDLocation(line: 1093, scope: !9)
+!12 = !DIDerivedType(tag: DW_TAG_typedef, name: "TItype", line: 160, file: !30, scope: !6, baseType: !13)
+!13 = !DIBasicType(tag: DW_TAG_base_type, size: 128, align: 128, encoding: DW_ATE_signed)
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "u", line: 1093, arg: 0, scope: !9, file: !1, type: !12)
+!15 = !DILocation(line: 1093, scope: !9)
 !16 = !{i64 0}
-!17 = !{!"0x100\00c\001095\000", !18, !1, !19} ; [ DW_TAG_auto_variable ]
-!18 = !{!"0xb\001094\000\0013", !29, !9} ; [ DW_TAG_lexical_block ]
-!19 = !{!"0x16\00word_type\00424\000\000\000\000", !30, !6, !20} ; [ DW_TAG_typedef ]
-!20 = !{!"0x24\00long int\000\0064\0064\000\000\005", !29, !1} ; [ DW_TAG_base_type ]
-!21 = !MDLocation(line: 1095, scope: !18)
-!22 = !MDLocation(line: 1103, scope: !18)
-!23 = !MDLocation(line: 1104, scope: !18)
-!24 = !MDLocation(line: 1003, scope: !25, inlinedAt: !26)
-!25 = !{!"0xb\00879\000\000", !29, !0} ; [ DW_TAG_lexical_block ]
-!26 = !MDLocation(line: 1107, scope: !18)
-!27 = !MDLocation(line: 1111, scope: !18)
+!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "c", line: 1095, scope: !18, file: !1, type: !19)
+!18 = distinct !DILexicalBlock(line: 1094, column: 0, file: !29, scope: !9)
+!19 = !DIDerivedType(tag: DW_TAG_typedef, name: "word_type", line: 424, file: !30, scope: !6, baseType: !20)
+!20 = !DIBasicType(tag: DW_TAG_base_type, name: "long int", size: 64, align: 64, encoding: DW_ATE_signed)
+!21 = !DILocation(line: 1095, scope: !18)
+!22 = !DILocation(line: 1103, scope: !18)
+!23 = !DILocation(line: 1104, scope: !18)
+!24 = !DILocation(line: 1003, scope: !25, inlinedAt: !26)
+!25 = distinct !DILexicalBlock(line: 879, column: 0, file: !29, scope: !0)
+!26 = !DILocation(line: 1107, scope: !18)
+!27 = !DILocation(line: 1111, scope: !18)
 !28 = !{!0, !9}
-!29 = !{!"foobar.c", !"/tmp"}
-!30 = !{!"foobar.h", !"/tmp"}
-!31 = !{i32 0}
-!32 = !{i32 1, !"Debug Info Version", i32 2}
+!29 = !DIFile(filename: "foobar.c", directory: "/tmp")
+!30 = !DIFile(filename: "foobar.h", directory: "/tmp")
+!31 = !{}
+!32 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-prolog-end.ll b/test/DebugInfo/X86/dbg-prolog-end.ll
index 4aaaf4a9b2a2..870b09120bcf 100644
--- a/test/DebugInfo/X86/dbg-prolog-end.ll
+++ b/test/DebugInfo/X86/dbg-prolog-end.ll
@@ -8,17 +8,17 @@ entry:
   %i.addr = alloca i32, align 4
   %j = alloca i32, align 4
   store i32 %i, i32* %i.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %i.addr, metadata !7, metadata !{!"0x102"}), !dbg !8
-  call void @llvm.dbg.declare(metadata i32* %j, metadata !9, metadata !{!"0x102"}), !dbg !11
+  call void @llvm.dbg.declare(metadata i32* %i.addr, metadata !7, metadata !DIExpression()), !dbg !8
+  call void @llvm.dbg.declare(metadata i32* %j, metadata !9, metadata !DIExpression()), !dbg !11
   store i32 2, i32* %j, align 4, !dbg !12
-  %tmp = load i32* %j, align 4, !dbg !13
+  %tmp = load i32, i32* %j, align 4, !dbg !13
   %inc = add nsw i32 %tmp, 1, !dbg !13
   store i32 %inc, i32* %j, align 4, !dbg !13
-  %tmp1 = load i32* %j, align 4, !dbg !14
-  %tmp2 = load i32* %i.addr, align 4, !dbg !14
+  %tmp1 = load i32, i32* %j, align 4, !dbg !14
+  %tmp2 = load i32, i32* %i.addr, align 4, !dbg !14
   %add = add nsw i32 %tmp1, %tmp2, !dbg !14
   store i32 %add, i32* %j, align 4, !dbg !14
-  %tmp3 = load i32* %j, align 4, !dbg !15
+  %tmp3 = load i32, i32* %j, align 4, !dbg !15
   ret i32 %tmp3, !dbg !15
 }
 
@@ -36,24 +36,24 @@ entry:
 !llvm.module.flags = !{!21}
 !18 = !{!1, !6}
 
-!0 = !{!"0x11\0012\00clang version 3.0 (trunk 131100)\000\00\000\00\000", !19, !20, !20, !18, null,  null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\000\001", !19, !2, !3, null, i32 (i32)* @foo, null, null, null} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!2 = !{!"0x29", !19} ; [ DW_TAG_file_type ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !19, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 131100)", isOptimized: false, emissionKind: 0, file: !19, enums: !20, retainedTypes: !20, subprograms: !18, imports:  null)
+!1 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !19, scope: !2, type: !3, function: i32 (i32)* @foo)
+!2 = !DIFile(filename: "/tmp/a.c", directory: "/private/tmp")
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ]
-!6 = !{!"0x2e\00main\00main\00\007\000\001\000\006\000\000\007", !19, !2, !3, null, i32 ()* @main, null, null, null} ; [ DW_TAG_subprogram ] [line 7] [def] [main]
-!7 = !{!"0x101\00i\0016777217\000", !1, !2, !5} ; [ DW_TAG_arg_variable ]
-!8 = !MDLocation(line: 1, column: 13, scope: !1)
-!9 = !{!"0x100\00j\002\000", !10, !2, !5} ; [ DW_TAG_auto_variable ]
-!10 = !{!"0xb\001\0016\000", !19, !1} ; [ DW_TAG_lexical_block ]
-!11 = !MDLocation(line: 2, column: 6, scope: !10)
-!12 = !MDLocation(line: 2, column: 11, scope: !10)
-!13 = !MDLocation(line: 3, column: 2, scope: !10)
-!14 = !MDLocation(line: 4, column: 2, scope: !10)
-!15 = !MDLocation(line: 5, column: 2, scope: !10)
-!16 = !MDLocation(line: 8, column: 2, scope: !17)
-!17 = !{!"0xb\007\0012\001", !19, !6} ; [ DW_TAG_lexical_block ]
-!19 = !{!"/tmp/a.c", !"/private/tmp"}
-!20 = !{i32 0}
-!21 = !{i32 1, !"Debug Info Version", i32 2}
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DISubprogram(name: "main", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 7, file: !19, scope: !2, type: !3, function: i32 ()* @main)
+!7 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 1, arg: 1, scope: !1, file: !2, type: !5)
+!8 = !DILocation(line: 1, column: 13, scope: !1)
+!9 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 2, scope: !10, file: !2, type: !5)
+!10 = distinct !DILexicalBlock(line: 1, column: 16, file: !19, scope: !1)
+!11 = !DILocation(line: 2, column: 6, scope: !10)
+!12 = !DILocation(line: 2, column: 11, scope: !10)
+!13 = !DILocation(line: 3, column: 2, scope: !10)
+!14 = !DILocation(line: 4, column: 2, scope: !10)
+!15 = !DILocation(line: 5, column: 2, scope: !10)
+!16 = !DILocation(line: 8, column: 2, scope: !17)
+!17 = distinct !DILexicalBlock(line: 7, column: 12, file: !19, scope: !6)
+!19 = !DIFile(filename: "/tmp/a.c", directory: "/private/tmp")
+!20 = !{}
+!21 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-subrange.ll b/test/DebugInfo/X86/dbg-subrange.ll
index 89754b9b3280..e3bd07355cc3 100644
--- a/test/DebugInfo/X86/dbg-subrange.ll
+++ b/test/DebugInfo/X86/dbg-subrange.ll
@@ -8,28 +8,28 @@ target triple = "x86_64-apple-macosx10.7.2"
 
 define void @bar() nounwind uwtable ssp {
 entry:
-  store i8 97, i8* getelementptr inbounds ([4294967296 x i8]* @s, i32 0, i64 0), align 1, !dbg !18
+  store i8 97, i8* getelementptr inbounds ([4294967296 x i8], [4294967296 x i8]* @s, i32 0, i64 0), align 1, !dbg !18
   ret void, !dbg !20
 }
 
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!22}
 
-!0 = !{!"0x11\0012\00clang version 3.1 (trunk 144833)\000\00\000\00\000", !21, !1, !1, !3, !11,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.1 (trunk 144833)", isOptimized: false, emissionKind: 0, file: !21, enums: !1, retainedTypes: !1, subprograms: !3, globals: !11, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00bar\00bar\00\004\000\001\000\006\00256\000\000", !21, !6, !7, null, void ()* @bar, null, null, null} ; [ DW_TAG_subprogram ] [line 4] [def] [scope 0] [bar]
-!6 = !{!"0x29", !21} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "bar", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !21, scope: !6, type: !7, function: void ()* @bar)
+!6 = !DIFile(filename: "small.c", directory: "/private/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null}
 !11 = !{!13}
-!13 = !{!"0x34\00s\00s\00\002\000\001", null, !6, !14, [4294967296 x i8]* @s, null} ; [ DW_TAG_variable ]
-!14 = !{!"0x1\00\000\0034359738368\008\000\000", null, null, !15, !16, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 34359738368, align 8, offset 0] [from char]
-!15 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ]
+!13 = !DIGlobalVariable(name: "s", line: 2, isLocal: false, isDefinition: true, scope: null, file: !6, type: !14, variable: [4294967296 x i8]* @s)
+!14 = !DICompositeType(tag: DW_TAG_array_type, size: 34359738368, align: 8, baseType: !15, elements: !16)
+!15 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
 !16 = !{!17}
-!17 = !{!"0x21\000\004294967296"} ; [ DW_TAG_subrange_type ]
-!18 = !MDLocation(line: 5, column: 3, scope: !19)
-!19 = !{!"0xb\004\001\000", !21, !5} ; [ DW_TAG_lexical_block ]
-!20 = !MDLocation(line: 6, column: 1, scope: !19)
-!21 = !{!"small.c", !"/private/tmp"}
-!22 = !{i32 1, !"Debug Info Version", i32 2}
+!17 = !DISubrange(count: 4294967296)
+!18 = !DILocation(line: 5, column: 3, scope: !19)
+!19 = distinct !DILexicalBlock(line: 4, column: 1, file: !21, scope: !5)
+!20 = !DILocation(line: 6, column: 1, scope: !19)
+!21 = !DIFile(filename: "small.c", directory: "/private/tmp")
+!22 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-value-const-byref.ll b/test/DebugInfo/X86/dbg-value-const-byref.ll
index c8ffba871356..a54ef0590e41 100644
--- a/test/DebugInfo/X86/dbg-value-const-byref.ll
+++ b/test/DebugInfo/X86/dbg-value-const-byref.ll
@@ -50,13 +50,13 @@ target triple = "x86_64-apple-macosx10.9.0"
 define i32 @foo() #0 {
 entry:
   %i = alloca i32, align 4
-  call void @llvm.dbg.value(metadata i32 3, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !15
+  call void @llvm.dbg.value(metadata i32 3, i64 0, metadata !10, metadata !DIExpression()), !dbg !15
   %call = call i32 @f3(i32 3) #3, !dbg !16
-  call void @llvm.dbg.value(metadata i32 7, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !18
-  %call1 = call i32 (...)* @f1() #3, !dbg !19
-  call void @llvm.dbg.value(metadata i32 %call1, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !19
+  call void @llvm.dbg.value(metadata i32 7, i64 0, metadata !10, metadata !DIExpression()), !dbg !18
+  %call1 = call i32 (...) @f1() #3, !dbg !19
+  call void @llvm.dbg.value(metadata i32 %call1, i64 0, metadata !10, metadata !DIExpression()), !dbg !19
   store i32 %call1, i32* %i, align 4, !dbg !19, !tbaa !20
-  call void @llvm.dbg.value(metadata i32* %i, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !24
+  call void @llvm.dbg.value(metadata i32* %i, i64 0, metadata !10, metadata !DIExpression()), !dbg !24
   call void @f2(i32* %i) #3, !dbg !24
   ret i32 0, !dbg !25
 }
@@ -78,29 +78,29 @@ attributes #3 = { nounwind }
 !llvm.module.flags = !{!11, !12}
 !llvm.ident = !{!13}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 \001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [dbg-value-const-byref.c] [DW_LANG_C99]
-!1 = !{!"dbg-value-const-byref.c", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "dbg-value-const-byref.c", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\005\000\001\000\006\000\001\005", !1, !5, !6, null, i32 ()* @foo, null, null, !9} ; [ DW_TAG_subprogram ] [line 5] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [dbg-value-const-byref.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 5, file: !1, scope: !5, type: !6, function: i32 ()* @foo, variables: !9)
+!5 = !DIFile(filename: "dbg-value-const-byref.c", directory: "")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{!10}
-!10 = !{!"0x100\00i\006\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 6]
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 6, scope: !4, file: !5, type: !8)
 !11 = !{i32 2, !"Dwarf Version", i32 2}
-!12 = !{i32 1, !"Debug Info Version", i32 2}
+!12 = !{i32 1, !"Debug Info Version", i32 3}
 !13 = !{!"clang version 3.5.0 "}
 !14 = !{i32 3}
-!15 = !MDLocation(line: 6, scope: !4)
-!16 = !MDLocation(line: 7, scope: !4)
+!15 = !DILocation(line: 6, scope: !4)
+!16 = !DILocation(line: 7, scope: !4)
 !17 = !{i32 7}
-!18 = !MDLocation(line: 8, scope: !4)
-!19 = !MDLocation(line: 9, scope: !4)
+!18 = !DILocation(line: 8, scope: !4)
+!19 = !DILocation(line: 9, scope: !4)
 !20 = !{!21, !21, i64 0}
 !21 = !{!"int", !22, i64 0}
 !22 = !{!"omnipotent char", !23, i64 0}
 !23 = !{!"Simple C/C++ TBAA"}
-!24 = !MDLocation(line: 10, scope: !4)
-!25 = !MDLocation(line: 11, scope: !4)
+!24 = !DILocation(line: 10, scope: !4)
+!25 = !DILocation(line: 11, scope: !4)
diff --git a/test/DebugInfo/X86/dbg-value-dag-combine.ll b/test/DebugInfo/X86/dbg-value-dag-combine.ll
index 9392da952f98..4331c6591369 100644
--- a/test/DebugInfo/X86/dbg-value-dag-combine.ll
+++ b/test/DebugInfo/X86/dbg-value-dag-combine.ll
@@ -8,40 +8,40 @@ declare <4 x i32> @__amdil_get_global_id_int()
 declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
 define void @__OpenCL_test_kernel(i32 addrspace(1)* %ip) nounwind {
 entry:
-  call void @llvm.dbg.value(metadata i32 addrspace(1)* %ip, i64 0, metadata !7, metadata !{!"0x102"}), !dbg !8
+  call void @llvm.dbg.value(metadata i32 addrspace(1)* %ip, i64 0, metadata !7, metadata !DIExpression()), !dbg !8
   %0 = call <4 x i32> @__amdil_get_global_id_int() nounwind
   %1 = extractelement <4 x i32> %0, i32 0
-  call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !9, metadata !{!"0x102"}), !dbg !11
-  call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !14
-  %tmp2 = load i32 addrspace(1)* %ip, align 4, !dbg !15
+  call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !9, metadata !DIExpression()), !dbg !11
+  call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !13, metadata !DIExpression()), !dbg !14
+  %tmp2 = load i32, i32 addrspace(1)* %ip, align 4, !dbg !15
   %tmp3 = add i32 0, %tmp2, !dbg !15
 ; CHECK:  ##DEBUG_VALUE: idx <- E{{..$}}
-  call void @llvm.dbg.value(metadata i32 %tmp3, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !15
-  %arrayidx = getelementptr i32 addrspace(1)* %ip, i32 %1, !dbg !16
+  call void @llvm.dbg.value(metadata i32 %tmp3, i64 0, metadata !13, metadata !DIExpression()), !dbg !15
+  %arrayidx = getelementptr i32, i32 addrspace(1)* %ip, i32 %1, !dbg !16
   store i32 %tmp3, i32 addrspace(1)* %arrayidx, align 4, !dbg !16
   ret void, !dbg !17
 }
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!20}
 
-!0 = !{!"0x2e\00__OpenCL_test_kernel\00__OpenCL_test_kernel\00__OpenCL_test_kernel\002\000\001\000\006\000\000\000", !19, !1, !3, null, void (i32 addrspace(1)*)* @__OpenCL_test_kernel, null, null, null} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 0] [__OpenCL_test_kernel]
-!1 = !{!"0x29", !19} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\001\00clc\000\00\000\00\001", !19, !12, !12, !18, null,  null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !19, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "__OpenCL_test_kernel", linkageName: "__OpenCL_test_kernel", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !19, scope: !1, type: !3, function: void (i32 addrspace(1)*)* @__OpenCL_test_kernel)
+!1 = !DIFile(filename: "OCL6368.tmp.cl", directory: "E:CUsersCmvillmow.AMDCAppDataCLocalCTemp")
+!2 = !DICompileUnit(language: DW_LANG_C89, producer: "clc", isOptimized: false, emissionKind: 1, file: !19, enums: !12, retainedTypes: !12, subprograms: !18, imports:  null)
+!3 = !DISubroutineType(types: !4)
 !4 = !{null, !5}
-!5 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !6} ; [ DW_TAG_pointer_type ]
-!6 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, !2} ; [ DW_TAG_base_type ]
-!7 = !{!"0x101\00ip\001\000", !0, !1, !5} ; [ DW_TAG_arg_variable ]
-!8 = !MDLocation(line: 1, column: 42, scope: !0)
-!9 = !{!"0x100\00gid\003\000", !10, !1, !6} ; [ DW_TAG_auto_variable ]
-!10 = !{!"0xb\002\001\000", !19, !0} ; [ DW_TAG_lexical_block ]
-!11 = !MDLocation(line: 3, column: 41, scope: !10)
-!12 = !{i32 0}
-!13 = !{!"0x100\00idx\004\000", !10, !1, !6} ; [ DW_TAG_auto_variable ]
-!14 = !MDLocation(line: 4, column: 20, scope: !10)
-!15 = !MDLocation(line: 5, column: 15, scope: !10)
-!16 = !MDLocation(line: 6, column: 18, scope: !10)
-!17 = !MDLocation(line: 7, column: 1, scope: !0)
+!5 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !6)
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!7 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ip", line: 1, arg: 0, scope: !0, file: !1, type: !5)
+!8 = !DILocation(line: 1, column: 42, scope: !0)
+!9 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "gid", line: 3, scope: !10, file: !1, type: !6)
+!10 = distinct !DILexicalBlock(line: 2, column: 1, file: !19, scope: !0)
+!11 = !DILocation(line: 3, column: 41, scope: !10)
+!12 = !{}
+!13 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "idx", line: 4, scope: !10, file: !1, type: !6)
+!14 = !DILocation(line: 4, column: 20, scope: !10)
+!15 = !DILocation(line: 5, column: 15, scope: !10)
+!16 = !DILocation(line: 6, column: 18, scope: !10)
+!17 = !DILocation(line: 7, column: 1, scope: !0)
 !18 = !{!0}
-!19 = !{!"OCL6368.tmp.cl", !"E:\5CUsers\5Cmvillmow.AMD\5CAppData\5CLocal\5CTemp"}
-!20 = !{i32 1, !"Debug Info Version", i32 2}
+!19 = !DIFile(filename: "OCL6368.tmp.cl", directory: "E:\5CUsers\5Cmvillmow.AMD\5CAppData\5CLocal\5CTemp")
+!20 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-value-inlined-parameter.ll b/test/DebugInfo/X86/dbg-value-inlined-parameter.ll
index 31833a8edf57..3fa5cc5a98ab 100644
--- a/test/DebugInfo/X86/dbg-value-inlined-parameter.ll
+++ b/test/DebugInfo/X86/dbg-value-inlined-parameter.ll
@@ -45,12 +45,12 @@
 
 define i32 @foo(%struct.S1* nocapture %sp, i32 %nums) nounwind optsize ssp {
 entry:
-  tail call void @llvm.dbg.value(metadata %struct.S1* %sp, i64 0, metadata !9, metadata !{!"0x102"}), !dbg !20
-  tail call void @llvm.dbg.value(metadata i32 %nums, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !21
-  %tmp2 = getelementptr inbounds %struct.S1* %sp, i64 0, i32 1, !dbg !22
+  tail call void @llvm.dbg.value(metadata %struct.S1* %sp, i64 0, metadata !9, metadata !DIExpression()), !dbg !20
+  tail call void @llvm.dbg.value(metadata i32 %nums, i64 0, metadata !18, metadata !DIExpression()), !dbg !21
+  %tmp2 = getelementptr inbounds %struct.S1, %struct.S1* %sp, i64 0, i32 1, !dbg !22
   store i32 %nums, i32* %tmp2, align 4, !dbg !22
   %call = tail call float* @bar(i32 %nums) nounwind optsize, !dbg !27
-  %tmp5 = getelementptr inbounds %struct.S1* %sp, i64 0, i32 0, !dbg !27
+  %tmp5 = getelementptr inbounds %struct.S1, %struct.S1* %sp, i64 0, i32 0, !dbg !27
   store float* %call, float** %tmp5, align 8, !dbg !27
   %cmp = icmp ne float* %call, null, !dbg !29
   %cond = zext i1 %cmp to i32, !dbg !29
@@ -61,11 +61,11 @@ declare float* @bar(i32) optsize
 
 define void @foobar() nounwind optsize ssp {
 entry:
-  tail call void @llvm.dbg.value(metadata %struct.S1* @p, i64 0, metadata !9, metadata !{!"0x102"}) nounwind, !dbg !31
-  tail call void @llvm.dbg.value(metadata i32 1, i64 0, metadata !18, metadata !{!"0x102"}) nounwind, !dbg !35
-  store i32 1, i32* getelementptr inbounds (%struct.S1* @p, i64 0, i32 1), align 8, !dbg !36
+  tail call void @llvm.dbg.value(metadata %struct.S1* @p, i64 0, metadata !9, metadata !DIExpression()) nounwind, !dbg !31
+  tail call void @llvm.dbg.value(metadata i32 1, i64 0, metadata !18, metadata !DIExpression()) nounwind, !dbg !35
+  store i32 1, i32* getelementptr inbounds (%struct.S1, %struct.S1* @p, i64 0, i32 1), align 8, !dbg !36
   %call.i = tail call float* @bar(i32 1) nounwind optsize, !dbg !37
-  store float* %call.i, float** getelementptr inbounds (%struct.S1* @p, i64 0, i32 0), align 8, !dbg !37
+  store float* %call.i, float** getelementptr inbounds (%struct.S1, %struct.S1* @p, i64 0, i32 0), align 8, !dbg !37
   ret void, !dbg !38
 }
 
@@ -74,44 +74,44 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!43}
 
-!0 = !{!"0x2e\00foo\00foo\00\008\000\001\000\006\00256\001\008", !1, !1, !3, null, i32 (%struct.S1*, i32)* @foo, null, null, !41} ; [ DW_TAG_subprogram ] [line 8] [def] [foo]
-!1 = !{!"0x29", !42} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 2.9 (trunk 125693)\001\00\000\00\001", !42, !8, !8, !39, !40,  !44} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !42, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "foo", line: 8, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 8, file: !1, scope: !1, type: !3, function: i32 (%struct.S1*, i32)* @foo, variables: !41)
+!1 = !DIFile(filename: "nm2.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 2.9 (trunk 125693)", isOptimized: true, emissionKind: 1, file: !42, enums: !{}, retainedTypes: !{}, subprograms: !39, globals: !40, imports:  !44)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ]
-!6 = !{!"0x2e\00foobar\00foobar\00\0015\000\001\000\006\000\001\000", !1, !1, !7, null, void ()* @foobar, null, null, null} ; [ DW_TAG_subprogram ] [line 15] [def] [scope 0] [foobar]
-!7 = !{!"0x15\00\000\000\000\000\000\000", !42, !1, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DISubprogram(name: "foobar", line: 15, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, file: !1, scope: !1, type: !7, function: void ()* @foobar)
+!7 = !DISubroutineType(types: !8)
 !8 = !{null}
-!9 = !{!"0x101\00sp\0016777223\000", !0, !1, !10, !32} ; [ DW_TAG_arg_variable ]
-!10 = !{!"0xf\00\000\0064\0064\000\000", null, !2, !11} ; [ DW_TAG_pointer_type ]
-!11 = !{!"0x16\00S1\004\000\000\000\000", !42, !2, !12} ; [ DW_TAG_typedef ]
-!12 = !{!"0x13\00S1\001\00128\0064\000\000\000", !42, !2, null, !13, null, null, null} ; [ DW_TAG_structure_type ] [S1] [line 1, size 128, align 64, offset 0] [def] [from ]
+!9 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "sp", line: 7, arg: 1, scope: !0, file: !1, type: !10)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, scope: !2, baseType: !11)
+!11 = !DIDerivedType(tag: DW_TAG_typedef, name: "S1", line: 4, file: !42, scope: !2, baseType: !12)
+!12 = !DICompositeType(tag: DW_TAG_structure_type, name: "S1", line: 1, size: 128, align: 64, file: !42, scope: !2, elements: !13)
 !13 = !{!14, !17}
-!14 = !{!"0xd\00m\002\0064\0064\000\000", !42, !1, !15} ; [ DW_TAG_member ]
-!15 = !{!"0xf\00\000\0064\0064\000\000", null, !2, !16} ; [ DW_TAG_pointer_type ]
-!16 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !2} ; [ DW_TAG_base_type ]
-!17 = !{!"0xd\00nums\003\0032\0032\0064\000", !42, !1, !5} ; [ DW_TAG_member ]
-!18 = !{!"0x101\00nums\0033554439\000", !0, !1, !5, !32} ; [ DW_TAG_arg_variable ]
-!19 = !{!"0x34\00p\00p\00\0014\000\001", !2, !1, !11, %struct.S1* @p, null} ; [ DW_TAG_variable ]
-!20 = !MDLocation(line: 7, column: 13, scope: !0)
-!21 = !MDLocation(line: 7, column: 21, scope: !0)
-!22 = !MDLocation(line: 9, column: 3, scope: !23)
-!23 = !{!"0xb\008\001\000", !1, !0} ; [ DW_TAG_lexical_block ]
-!27 = !MDLocation(line: 10, column: 3, scope: !23)
-!29 = !MDLocation(line: 11, column: 3, scope: !23)
+!14 = !DIDerivedType(tag: DW_TAG_member, name: "m", line: 2, size: 64, align: 64, file: !42, scope: !1, baseType: !15)
+!15 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, scope: !2, baseType: !16)
+!16 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float)
+!17 = !DIDerivedType(tag: DW_TAG_member, name: "nums", line: 3, size: 32, align: 32, offset: 64, file: !42, scope: !1, baseType: !5)
+!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "nums", line: 7, arg: 2, scope: !0, file: !1, type: !5)
+!19 = !DIGlobalVariable(name: "p", line: 14, isLocal: false, isDefinition: true, scope: !2, file: !1, type: !11, variable: %struct.S1* @p)
+!20 = !DILocation(line: 7, column: 13, scope: !0)
+!21 = !DILocation(line: 7, column: 21, scope: !0)
+!22 = !DILocation(line: 9, column: 3, scope: !23)
+!23 = distinct !DILexicalBlock(line: 8, column: 1, file: !1, scope: !0)
+!27 = !DILocation(line: 10, column: 3, scope: !23)
+!29 = !DILocation(line: 11, column: 3, scope: !23)
 !30 = !{%struct.S1* @p}
-!31 = !MDLocation(line: 7, column: 13, scope: !0, inlinedAt: !32)
-!32 = !MDLocation(line: 16, column: 3, scope: !33)
-!33 = !{!"0xb\0015\0015\001", !1, !6} ; [ DW_TAG_lexical_block ]
+!31 = !DILocation(line: 7, column: 13, scope: !0, inlinedAt: !32)
+!32 = !DILocation(line: 16, column: 3, scope: !33)
+!33 = distinct !DILexicalBlock(line: 15, column: 15, file: !1, scope: !6)
 !34 = !{i32 1}
-!35 = !MDLocation(line: 7, column: 21, scope: !0, inlinedAt: !32)
-!36 = !MDLocation(line: 9, column: 3, scope: !23, inlinedAt: !32)
-!37 = !MDLocation(line: 10, column: 3, scope: !23, inlinedAt: !32)
-!38 = !MDLocation(line: 17, column: 1, scope: !33)
+!35 = !DILocation(line: 7, column: 21, scope: !0, inlinedAt: !32)
+!36 = !DILocation(line: 9, column: 3, scope: !23, inlinedAt: !32)
+!37 = !DILocation(line: 10, column: 3, scope: !23, inlinedAt: !32)
+!38 = !DILocation(line: 17, column: 1, scope: !33)
 !39 = !{!0, !6}
 !40 = !{!19}
 !41 = !{!9, !18}
-!42 = !{!"nm2.c", !"/private/tmp"}
-!43 = !{i32 1, !"Debug Info Version", i32 2}
+!42 = !DIFile(filename: "nm2.c", directory: "/private/tmp")
+!43 = !{i32 1, !"Debug Info Version", i32 3}
 !44 = !{}
diff --git a/test/DebugInfo/X86/dbg-value-isel.ll b/test/DebugInfo/X86/dbg-value-isel.ll
index a908b322d76e..04e4531d1d72 100644
--- a/test/DebugInfo/X86/dbg-value-isel.ll
+++ b/test/DebugInfo/X86/dbg-value-isel.ll
@@ -13,7 +13,7 @@ target triple = "x86_64-apple-darwin10.0.0"
 
 define void @__OpenCL_nbt02_kernel(i32 addrspace(1)* %ip) nounwind {
 entry:
-  call void @llvm.dbg.value(metadata i32 addrspace(1)* %ip, i64 0, metadata !8, metadata !{!"0x102"}), !dbg !9
+  call void @llvm.dbg.value(metadata i32 addrspace(1)* %ip, i64 0, metadata !8, metadata !DIExpression()), !dbg !9
   %0 = call <4 x i32> @__amdil_get_local_id_int() nounwind
   %1 = extractelement <4 x i32> %0, i32 0
   br label %2
@@ -28,7 +28,7 @@ entry:
 
 get_local_id.exit:                                ; preds = %4
   %6 = phi i32 [ %5, %4 ]
-  call void @llvm.dbg.value(metadata i32 %6, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !12
+  call void @llvm.dbg.value(metadata i32 %6, i64 0, metadata !10, metadata !DIExpression()), !dbg !12
   %7 = call <4 x i32> @__amdil_get_global_id_int() nounwind, !dbg !12
   %8 = extractelement <4 x i32> %7, i32 0, !dbg !12
   br label %9
@@ -43,7 +43,7 @@ get_local_id.exit:                                ; preds = %4
 
 get_global_id.exit:                               ; preds = %11
   %13 = phi i32 [ %12, %11 ]
-  call void @llvm.dbg.value(metadata i32 %13, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !14
+  call void @llvm.dbg.value(metadata i32 %13, i64 0, metadata !13, metadata !DIExpression()), !dbg !14
   %14 = call <4 x i32> @__amdil_get_local_size_int() nounwind
   %15 = extractelement <4 x i32> %14, i32 0
   br label %16
@@ -58,7 +58,7 @@ get_global_id.exit:                               ; preds = %11
 
 get_local_size.exit:                              ; preds = %18
   %20 = phi i32 [ %19, %18 ]
-  call void @llvm.dbg.value(metadata i32 %20, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !16
+  call void @llvm.dbg.value(metadata i32 %20, i64 0, metadata !15, metadata !DIExpression()), !dbg !16
   %tmp5 = add i32 %6, %13, !dbg !17
   %tmp7 = add i32 %tmp5, %20, !dbg !17
   store i32 %tmp7, i32 addrspace(1)* %ip, align 4, !dbg !17
@@ -81,26 +81,26 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!22}
 
-!0 = !{!"0x2e\00__OpenCL_nbt02_kernel\00__OpenCL_nbt02_kernel\00__OpenCL_nbt02_kernel\002\000\001\000\006\000\000\000", !20, !1, !3, null, void (i32 addrspace(1)*)* @__OpenCL_nbt02_kernel, null, null, null} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 0] [__OpenCL_nbt02_kernel]
-!1 = !{!"0x29", !20} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\001\00clc\000\00\000\00\001", !20, !21, !21, !19, null,  null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !20, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "__OpenCL_nbt02_kernel", linkageName: "__OpenCL_nbt02_kernel", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !20, scope: !1, type: !3, function: void (i32 addrspace(1)*)* @__OpenCL_nbt02_kernel)
+!1 = !DIFile(filename: "OCLlLwTXZ.cl", directory: "/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C89, producer: "clc", isOptimized: false, emissionKind: 1, file: !20, enums: !21, retainedTypes: !21, subprograms: !19, imports:  null)
+!3 = !DISubroutineType(types: !4)
 !4 = !{null, !5}
-!5 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !6} ; [ DW_TAG_pointer_type ]
-!6 = !{!"0x16\00uint\000\000\000\000\000", !20, !2, !7} ; [ DW_TAG_typedef ]
-!7 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, !2} ; [ DW_TAG_base_type ]
-!8 = !{!"0x101\00ip\001\000", !0, !1, !5} ; [ DW_TAG_arg_variable ]
-!9 = !MDLocation(line: 1, column: 32, scope: !0)
-!10 = !{!"0x100\00tid\003\000", !11, !1, !6} ; [ DW_TAG_auto_variable ]
-!11 = !{!"0xb\002\001\001", !1, !0} ; [ DW_TAG_lexical_block ]
-!12 = !MDLocation(line: 5, column: 24, scope: !11)
-!13 = !{!"0x100\00gid\003\000", !11, !1, !6} ; [ DW_TAG_auto_variable ]
-!14 = !MDLocation(line: 6, column: 25, scope: !11)
-!15 = !{!"0x100\00lsz\003\000", !11, !1, !6} ; [ DW_TAG_auto_variable ]
-!16 = !MDLocation(line: 7, column: 26, scope: !11)
-!17 = !MDLocation(line: 9, column: 24, scope: !11)
-!18 = !MDLocation(line: 10, column: 1, scope: !0)
+!5 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !6)
+!6 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint", file: !20, scope: !2, baseType: !7)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!8 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ip", line: 1, arg: 0, scope: !0, file: !1, type: !5)
+!9 = !DILocation(line: 1, column: 32, scope: !0)
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "tid", line: 3, scope: !11, file: !1, type: !6)
+!11 = distinct !DILexicalBlock(line: 2, column: 1, file: !1, scope: !0)
+!12 = !DILocation(line: 5, column: 24, scope: !11)
+!13 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "gid", line: 3, scope: !11, file: !1, type: !6)
+!14 = !DILocation(line: 6, column: 25, scope: !11)
+!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "lsz", line: 3, scope: !11, file: !1, type: !6)
+!16 = !DILocation(line: 7, column: 26, scope: !11)
+!17 = !DILocation(line: 9, column: 24, scope: !11)
+!18 = !DILocation(line: 10, column: 1, scope: !0)
 !19 = !{!0}
-!20 = !{!"OCLlLwTXZ.cl", !"/tmp"}
-!21 = !{i32 0}
-!22 = !{i32 1, !"Debug Info Version", i32 2}
+!20 = !DIFile(filename: "OCLlLwTXZ.cl", directory: "/tmp")
+!21 = !{}
+!22 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-value-location.ll b/test/DebugInfo/X86/dbg-value-location.ll
index 015ec89ec4ca..219fa7a5ff34 100644
--- a/test/DebugInfo/X86/dbg-value-location.ll
+++ b/test/DebugInfo/X86/dbg-value-location.ll
@@ -18,8 +18,8 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 
 define i32 @foo(i32 %dev, i64 %cmd, i8* %data, i32 %data2) nounwind optsize ssp {
 entry:
-  call void @llvm.dbg.value(metadata i32 %dev, i64 0, metadata !12, metadata !{!"0x102"}), !dbg !13
-  %tmp.i = load i32* @dfm, align 4, !dbg !14
+  call void @llvm.dbg.value(metadata i32 %dev, i64 0, metadata !12, metadata !DIExpression()), !dbg !13
+  %tmp.i = load i32, i32* @dfm, align 4, !dbg !14
   %cmp.i = icmp eq i32 %tmp.i, 0, !dbg !14
   br i1 %cmp.i, label %if.else, label %if.end.i, !dbg !14
 
@@ -50,30 +50,30 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!29}
 
-!0 = !{!"0x2e\00foo\00foo\00\0019510\000\001\000\006\00256\001\0019510", !26, !1, !3, null, i32 (i32, i64, i8*, i32)* @foo, null, null, null} ; [ DW_TAG_subprogram ] [line 19510] [def] [foo]
-!1 = !{!"0x29", !26} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 2.9 (trunk 124753)\001\00\000\00\000", !27, !28, !28, !24, null,  null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !26, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "foo", line: 19510, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 19510, file: !26, scope: !1, type: !3, function: i32 (i32, i64, i8*, i32)* @foo)
+!1 = !DIFile(filename: "/tmp/f.c", directory: "/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 2.9 (trunk 124753)", isOptimized: true, emissionKind: 0, file: !27, enums: !28, retainedTypes: !28, subprograms: !24, imports:  null)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ]
-!6 = !{!"0x2e\00bar3\00bar3\00\0014827\001\001\000\006\00256\001\000", !26, !1, !3, null, i32 (i32)* @bar3, null, null, null} ; [ DW_TAG_subprogram ] [line 14827] [local] [def] [scope 0] [bar3]
-!7 = !{!"0x2e\00bar2\00bar2\00\0015397\001\001\000\006\00256\001\000", !26, !1, !3, null, i32 (i32)* @bar2, null, null, null} ; [ DW_TAG_subprogram ] [line 15397] [local] [def] [scope 0] [bar2]
-!8 = !{!"0x2e\00bar\00bar\00\0012382\001\001\000\006\00256\001\000", !26, !1, !9, null, i32 (i32, i32*)* @bar, null, null, null} ; [ DW_TAG_subprogram ] [line 12382] [local] [def] [scope 0] [bar]
-!9 = !{!"0x15\00\000\000\000\000\000\000", !26, !1, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DISubprogram(name: "bar3", line: 14827, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !26, scope: !1, type: !3, function: i32 (i32)* @bar3)
+!7 = !DISubprogram(name: "bar2", line: 15397, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !26, scope: !1, type: !3, function: i32 (i32)* @bar2)
+!8 = !DISubprogram(name: "bar", line: 12382, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !26, scope: !1, type: !9, function: i32 (i32, i32*)* @bar)
+!9 = !DISubroutineType(types: !10)
 !10 = !{!11}
-!11 = !{!"0x24\00unsigned char\000\008\008\000\000\008", null, !2} ; [ DW_TAG_base_type ]
-!12 = !{!"0x101\00var\0019509\000", !0, !1, !5} ; [ DW_TAG_arg_variable ]
-!13 = !MDLocation(line: 19509, column: 20, scope: !0)
-!14 = !MDLocation(line: 18091, column: 2, scope: !15, inlinedAt: !17)
-!15 = !{!"0xb\0018086\001\00748", !26, !16} ; [ DW_TAG_lexical_block ]
-!16 = !{!"0x2e\00foo_bar\00foo_bar\00\0018086\001\001\000\006\00256\001\000", !26, !1, !3, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 18086] [local] [def] [scope 0] [foo_bar]
-!17 = !MDLocation(line: 19514, column: 2, scope: !18)
-!18 = !{!"0xb\0019510\001\0099", !26, !0} ; [ DW_TAG_lexical_block ]
-!22 = !MDLocation(line: 18094, column: 2, scope: !15, inlinedAt: !17)
-!23 = !MDLocation(line: 19524, column: 1, scope: !18)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char)
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "var", line: 19509, arg: 0, scope: !0, file: !1, type: !5)
+!13 = !DILocation(line: 19509, column: 20, scope: !0)
+!14 = !DILocation(line: 18091, column: 2, scope: !15, inlinedAt: !17)
+!15 = distinct !DILexicalBlock(line: 18086, column: 1, file: !26, scope: !16)
+!16 = !DISubprogram(name: "foo_bar", line: 18086, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !26, scope: !1, type: !3)
+!17 = !DILocation(line: 19514, column: 2, scope: !18)
+!18 = distinct !DILexicalBlock(line: 19510, column: 1, file: !26, scope: !0)
+!22 = !DILocation(line: 18094, column: 2, scope: !15, inlinedAt: !17)
+!23 = !DILocation(line: 19524, column: 1, scope: !18)
 !24 = !{!0, !6, !7, !8, !16}
-!25 = !{!"0x29", !27} ; [ DW_TAG_file_type ]
-!26 = !{!"/tmp/f.c", !"/tmp"}
-!27 = !{!"f.i", !"/tmp"}
-!28 = !{i32 0}
-!29 = !{i32 1, !"Debug Info Version", i32 2}
+!25 = !DIFile(filename: "f.i", directory: "/tmp")
+!26 = !DIFile(filename: "/tmp/f.c", directory: "/tmp")
+!27 = !DIFile(filename: "f.i", directory: "/tmp")
+!28 = !{}
+!29 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-value-range.ll b/test/DebugInfo/X86/dbg-value-range.ll
index 727f906e1a27..a8fa9073fa77 100644
--- a/test/DebugInfo/X86/dbg-value-range.ll
+++ b/test/DebugInfo/X86/dbg-value-range.ll
@@ -4,11 +4,11 @@
 
 define i32 @bar(%struct.a* nocapture %b) nounwind ssp {
 entry:
-  tail call void @llvm.dbg.value(metadata %struct.a* %b, i64 0, metadata !6, metadata !{!"0x102"}), !dbg !13
-  %tmp1 = getelementptr inbounds %struct.a* %b, i64 0, i32 0, !dbg !14
-  %tmp2 = load i32* %tmp1, align 4, !dbg !14
-  tail call void @llvm.dbg.value(metadata i32 %tmp2, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !14
-  %call = tail call i32 (...)* @foo(i32 %tmp2) nounwind , !dbg !18
+  tail call void @llvm.dbg.value(metadata %struct.a* %b, i64 0, metadata !6, metadata !DIExpression()), !dbg !13
+  %tmp1 = getelementptr inbounds %struct.a, %struct.a* %b, i64 0, i32 0, !dbg !14
+  %tmp2 = load i32, i32* %tmp1, align 4, !dbg !14
+  tail call void @llvm.dbg.value(metadata i32 %tmp2, i64 0, metadata !11, metadata !DIExpression()), !dbg !14
+  %call = tail call i32 (...) @foo(i32 %tmp2) nounwind , !dbg !18
   %add = add nsw i32 %tmp2, 1, !dbg !19
   ret i32 %add, !dbg !19
 }
@@ -20,27 +20,27 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!24}
 
-!0 = !{!"0x2e\00bar\00bar\00\005\000\001\000\006\00256\001\000", !22, !1, !3, null, i32 (%struct.a*)* @bar, null, null, !21} ; [ DW_TAG_subprogram ] [line 5] [def] [scope 0] [bar]
-!1 = !{!"0x29", !22} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 2.9 (trunk 122997)\001\00\000\00\001", !22, !23, !23, !20, null,  null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !22, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "bar", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !22, scope: !1, type: !3, function: i32 (%struct.a*)* @bar, variables: !21)
+!1 = !DIFile(filename: "bar.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 2.9 (trunk 122997)", isOptimized: true, emissionKind: 1, file: !22, enums: !23, retainedTypes: !23, subprograms: !20, imports:  null)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ]
-!6 = !{!"0x101\00b\005\000", !0, !1, !7} ; [ DW_TAG_arg_variable ]
-!7 = !{!"0xf\00\000\0064\0064\000\000", null, !2, !8} ; [ DW_TAG_pointer_type ]
-!8 = !{!"0x13\00a\001\0032\0032\000\000\000", !22, !2, null, !9, null, null, null} ; [ DW_TAG_structure_type ] [a] [line 1, size 32, align 32, offset 0] [def] [from ]
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 5, arg: 0, scope: !0, file: !1, type: !7)
+!7 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, scope: !2, baseType: !8)
+!8 = !DICompositeType(tag: DW_TAG_structure_type, name: "a", line: 1, size: 32, align: 32, file: !22, scope: !2, elements: !9)
 !9 = !{!10}
-!10 = !{!"0xd\00c\002\0032\0032\000\000", !22, !1, !5} ; [ DW_TAG_member ]
-!11 = !{!"0x100\00x\006\000", !12, !1, !5} ; [ DW_TAG_auto_variable ]
-!12 = !{!"0xb\005\0022\000", !22, !0} ; [ DW_TAG_lexical_block ]
-!13 = !MDLocation(line: 5, column: 19, scope: !0)
-!14 = !MDLocation(line: 6, column: 14, scope: !12)
-!18 = !MDLocation(line: 7, column: 2, scope: !12)
-!19 = !MDLocation(line: 8, column: 2, scope: !12)
+!10 = !DIDerivedType(tag: DW_TAG_member, name: "c", line: 2, size: 32, align: 32, file: !22, scope: !1, baseType: !5)
+!11 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 6, scope: !12, file: !1, type: !5)
+!12 = distinct !DILexicalBlock(line: 5, column: 22, file: !22, scope: !0)
+!13 = !DILocation(line: 5, column: 19, scope: !0)
+!14 = !DILocation(line: 6, column: 14, scope: !12)
+!18 = !DILocation(line: 7, column: 2, scope: !12)
+!19 = !DILocation(line: 8, column: 2, scope: !12)
 !20 = !{!0}
 !21 = !{!6, !11}
-!22 = !{!"bar.c", !"/private/tmp"}
-!23 = !{i32 0}
+!22 = !DIFile(filename: "bar.c", directory: "/private/tmp")
+!23 = !{}
 
 ; Check that variable bar:b value range is appropriately truncated in debug info.
 ; The variable is in %rdi which is clobbered by 'movl %ebx, %edi'
@@ -55,11 +55,8 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 ;CHECK-NEXT:	.quad
 ;CHECK-NEXT: [[CLOBBER_OFF:Lset.*]] = [[CLOBBER]]-{{.*}}
 ;CHECK-NEXT:	.quad	[[CLOBBER_OFF]]
-;CHECK-NEXT: Lset{{.*}} = Ltmp{{.*}}-Ltmp{{.*}}
-;CHECK-NEXT:    .short  Lset
-;CHECK-NEXT: Ltmp
+;CHECK-NEXT:  .short 1 ## Loc expr size
 ;CHECK-NEXT:	.byte	85 ## DW_OP_reg
-;CHECK-NEXT: Ltmp
 ;CHECK-NEXT:	.quad	0
 ;CHECK-NEXT:	.quad	0
-!24 = !{i32 1, !"Debug Info Version", i32 2}
+!24 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg-value-terminator.ll b/test/DebugInfo/X86/dbg-value-terminator.ll
index 0653bde62e90..5f50b13aa024 100644
--- a/test/DebugInfo/X86/dbg-value-terminator.ll
+++ b/test/DebugInfo/X86/dbg-value-terminator.ll
@@ -6,7 +6,7 @@
 ; terminator.
 ;
 ; CHECK-LABEL: test:
-; CHECK: ##DEBUG_VALUE: i
+; CHECK: ##DEBUG_VALUE: foo:i
 %a = type { i32, i32 }
 
 define hidden fastcc %a* @test() #1 {
@@ -85,9 +85,9 @@ VEC_edge_base_index.exit7.i:                      ; preds = %"3.i5.i"
   br i1 undef, label %may_unswitch_on.exit, label %"44.i", !dbg !12
 
 "44.i":                                           ; preds = %"42.i"
-  %2 = load %a** undef, align 8, !dbg !12
+  %2 = load %a*, %a** undef, align 8, !dbg !12
   %3 = bitcast %a* %2 to %a*, !dbg !12
-  call void @llvm.dbg.value(metadata %a* %3, i64 0, metadata !6, metadata !{!"0x102"}), !dbg !12
+  call void @llvm.dbg.value(metadata %a* %3, i64 0, metadata !6, metadata !DIExpression()), !dbg !12
   br label %may_unswitch_on.exit, !dbg !12
 
 "45.i":                                           ; preds = %"38.i"
@@ -113,21 +113,21 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!22}
 
-!0 = !{!"0x11\0012\00Apple clang version\001\00\000\00\001", !20, !21, !21, !18, null,  null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"0x2e\00foo\00\00\002\000\001\000\006\00256\001\000", !20, !2, !3, null, %a* ()* @test, null, null, !19} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 0] [foo]
-!2 = !{!"0x29", !20} ; [ DW_TAG_file_type ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !20, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "Apple clang version", isOptimized: true, emissionKind: 1, file: !20, enums: !21, retainedTypes: !21, subprograms: !18, imports:  null)
+!1 = !DISubprogram(name: "foo", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !20, scope: !2, type: !3, function: %a* ()* @test, variables: !19)
+!2 = !DIFile(filename: "a.c", directory: "/private/tmp")
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ]
-!6 = !{!"0x101\00i\0016777218\000", !1, !2, !5} ; [ DW_TAG_arg_variable ]
-!7 = !{!"0x101\00c\0033554434\000", !1, !2, !8} ; [ DW_TAG_arg_variable ]
-!8 = !{!"0xf\00\000\0064\0064\000\000", null, !0, !9} ; [ DW_TAG_pointer_type ]
-!9 = !{!"0x24\00char\000\008\008\000\000\006", null, !0} ; [ DW_TAG_base_type ]
-!10 = !{!"0x100\00a\003\000", !11, !2, !9} ; [ DW_TAG_auto_variable ]
-!11 = !{!"0xb\002\0025\000", !20, !1} ; [ DW_TAG_lexical_block ]
-!12 = !MDLocation(line: 2, column: 13, scope: !1)
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 2, arg: 1, scope: !1, file: !2, type: !5)
+!7 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 2, arg: 2, scope: !1, file: !2, type: !8)
+!8 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, scope: !0, baseType: !9)
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 3, scope: !11, file: !2, type: !9)
+!11 = distinct !DILexicalBlock(line: 2, column: 25, file: !20, scope: !1)
+!12 = !DILocation(line: 2, column: 13, scope: !1)
 !18 = !{!1}
 !19 = !{!6, !7, !10}
-!20 = !{!"a.c", !"/private/tmp"}
-!21 = !{i32 0}
-!22 = !{i32 1, !"Debug Info Version", i32 2}
+!20 = !DIFile(filename: "a.c", directory: "/private/tmp")
+!21 = !{}
+!22 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dbg_value_direct.ll b/test/DebugInfo/X86/dbg_value_direct.ll
index 69c9e99519bb..6446dfe491a6 100644
--- a/test/DebugInfo/X86/dbg_value_direct.ll
+++ b/test/DebugInfo/X86/dbg_value_direct.ll
@@ -51,9 +51,9 @@ entry:
   %17 = lshr i64 %16, 3
   %18 = add i64 %17, 2147450880
   %19 = inttoptr i64 %18 to i8*
-  %20 = load i8* %19
+  %20 = load i8, i8* %19
   %21 = icmp ne i8 %20, 0
-  call void @llvm.dbg.declare(metadata i32* %3, metadata !23, metadata !28)
+  call void @llvm.dbg.declare(metadata i32* %3, metadata !23, metadata !28), !dbg !DILocation(scope: !4)
   br i1 %21, label %22, label %28
 
 ; <label>:22                                      ; preds = %entry
@@ -70,7 +70,7 @@ entry:
 
 ; <label>:28                                      ; preds = %22, %entry
   store i32 %0, i32* %3, align 4
-  call void @llvm.dbg.declare(metadata %struct.A* %agg.result, metadata !24, metadata !{!"0x102"}), !dbg !25
+  call void @llvm.dbg.declare(metadata %struct.A* %agg.result, metadata !24, metadata !DIExpression(DW_OP_deref)), !dbg !25
   call void @_ZN1AC1Ev(%struct.A* %agg.result), !dbg !25
   store i64 1172321806, i64* %4, !dbg !26
   %29 = inttoptr i64 %10 to i32*, !dbg !26
@@ -91,8 +91,8 @@ declare void @_ZN1AC1Ev(%struct.A*) #2
 
 define internal void @asan.module_ctor()  "stack-protector-buffer-size"="1" {
   call void @__asan_init_v3()
-  %1 = load volatile i64* @__asan_mapping_offset
-  %2 = load volatile i64* @__asan_mapping_scale
+  %1 = load volatile i64, i64* @__asan_mapping_offset
+  %2 = load volatile i64, i64* @__asan_mapping_scale
   ret void
 }
 
@@ -147,32 +147,30 @@ attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!22, !27}
 
-!0 = !{!"0x11\004\00clang version 3.4 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/crash.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"crash.cpp", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "crash.cpp", directory: "/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00func\00func\00_Z4funci\006\000\001\000\006\00256\000\006", !1, !5, !6, null, void (%struct.A*, i32)* @_Z4funci, null, null, !2} ; [ DW_TAG_subprogram ] [line 6] [def] [func]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/crash.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "func", linkageName: "_Z4funci", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 6, file: !1, scope: !5, type: !6, function: void (%struct.A*, i32)* @_Z4funci, variables: !2)
+!5 = !DIFile(filename: "crash.cpp", directory: "/tmp")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !21}
-!8 = !{!"0x13\00A\001\008\008\000\000\000", !1, null, null, !9, null, null, null} ; [ DW_TAG_structure_type ] [A] [line 1, size 8, align 8, offset 0] [def] [from ]
+!8 = !DICompositeType(tag: DW_TAG_structure_type, name: "A", line: 1, size: 8, align: 8, file: !1, elements: !9)
 !9 = !{!10, !15}
-!10 = !{!"0x2e\00A\00A\00\002\000\000\000\006\00256\000\002", !1, !8, !11, null, null, null, i32 0, !14} ; [ DW_TAG_subprogram ] [line 2] [A]
-!11 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!10 = !DISubprogram(name: "A", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !8, type: !11)
+!11 = !DISubroutineType(types: !12)
 !12 = !{null, !13}
-!13 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !8} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from A]
-!14 = !{i32 786468}
-!15 = !{!"0x2e\00A\00A\00\003\000\000\000\006\00256\000\003", !1, !8, !16, null, null, null, i32 0, !20} ; [ DW_TAG_subprogram ] [line 3] [A]
-!16 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !17, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !8)
+!15 = !DISubprogram(name: "A", line: 3, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !8, type: !16)
+!16 = !DISubroutineType(types: !17)
 !17 = !{null, !13, !18}
-!18 = !{!"0x10\00\000\000\000\000\000", null, null, !19} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from ]
-!19 = !{!"0x26\00\000\000\000\000\000", null, null, !8} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from A]
-!20 = !{i32 786468}
-!21 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!18 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !19)
+!19 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !8)
+!21 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !22 = !{i32 2, !"Dwarf Version", i32 3}
-!23 = !{!"0x101\00\0016777222\000", !4, !5, !21} ; [ DW_TAG_arg_variable ] [line 6]
-!24 = !{!"0x100\00a\007\008192", !4, !5, !8} ; [ DW_TAG_auto_variable ] [a] [line 7]
-!25 = !MDLocation(line: 7, scope: !4)
-!26 = !MDLocation(line: 8, scope: !4)
-!27 = !{i32 1, !"Debug Info Version", i32 2}
-!28 = !{!"0x102\006"} ; [ DW_TAG_expression ] [DW_OP_deref]
+!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "", line: 6, arg: 1, scope: !4, file: !5, type: !21)
+!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 7, scope: !4, file: !5, type: !8)
+!25 = !DILocation(line: 7, scope: !4)
+!26 = !DILocation(line: 8, scope: !4)
+!27 = !{i32 1, !"Debug Info Version", i32 3}
+!28 = !DIExpression(DW_OP_deref)
diff --git a/test/DebugInfo/X86/debug-dead-local-var.ll b/test/DebugInfo/X86/debug-dead-local-var.ll
index 6733dd866690..d56d17d06e61 100644
--- a/test/DebugInfo/X86/debug-dead-local-var.ll
+++ b/test/DebugInfo/X86/debug-dead-local-var.ll
@@ -27,25 +27,25 @@ attributes #0 = { nounwind readnone uwtable "less-precise-fpmad"="false" "no-fra
 !llvm.module.flags = !{!18, !19}
 !llvm.ident = !{!20}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 (trunk 209255) (llvm/trunk 209253)\001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/debug-dead-local-var.c] [DW_LANG_C99]
-!1 = !{!"debug-dead-local-var.c", !"/usr/local/google/home/echristo"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 (trunk 209255) (llvm/trunk 209253)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "debug-dead-local-var.c", directory: "/usr/local/google/home/echristo")
 !2 = !{}
 !3 = !{!4, !9}
-!4 = !{!"0x2e\00bar\00bar\00\0011\000\001\000\006\000\001\0011", !1, !5, !6, null, i32 ()* @bar, null, null, !2} ; [ DW_TAG_subprogram ] [line 11] [def] [bar]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/usr/local/google/home/echristo/debug-dead-local-var.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "bar", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 11, file: !1, scope: !5, type: !6, function: i32 ()* @bar, variables: !2)
+!5 = !DIFile(filename: "debug-dead-local-var.c", directory: "/usr/local/google/home/echristo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x2e\00foo\00foo\00\006\001\001\000\006\000\001\006", !1, !5, !10, null, null, null, null, !12} ; [ DW_TAG_subprogram ] [line 6] [local] [def] [foo]
-!10 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DISubprogram(name: "foo", line: 6, isLocal: true, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 6, file: !1, scope: !5, type: !10, variables: !12)
+!10 = !DISubroutineType(types: !11)
 !11 = !{null}
 !12 = !{!13}
-!13 = !{!"0x100\00xyz\008\000", !9, !5, !14} ; [ DW_TAG_auto_variable ] [xyz] [line 8]
-!14 = !{!"0x13\00X\008\0064\0032\000\000\000", !1, !9, null, !15, null, null, null} ; [ DW_TAG_structure_type ] [X] [line 8, size 64, align 32, offset 0] [def] [from ]
+!13 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xyz", line: 8, scope: !9, file: !5, type: !14)
+!14 = !DICompositeType(tag: DW_TAG_structure_type, name: "X", line: 8, size: 64, align: 32, file: !1, scope: !9, elements: !15)
 !15 = !{!16, !17}
-!16 = !{!"0xd\00a\008\0032\0032\000\000", !1, !14, !8} ; [ DW_TAG_member ] [a] [line 8, size 32, align 32, offset 0] [from int]
-!17 = !{!"0xd\00b\008\0032\0032\0032\000", !1, !14, !8} ; [ DW_TAG_member ] [b] [line 8, size 32, align 32, offset 32] [from int]
+!16 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 8, size: 32, align: 32, file: !1, scope: !14, baseType: !8)
+!17 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 8, size: 32, align: 32, offset: 32, file: !1, scope: !14, baseType: !8)
 !18 = !{i32 2, !"Dwarf Version", i32 4}
-!19 = !{i32 2, !"Debug Info Version", i32 2}
+!19 = !{i32 2, !"Debug Info Version", i32 3}
 !20 = !{!"clang version 3.5.0 (trunk 209255) (llvm/trunk 209253)"}
-!21 = !MDLocation(line: 13, scope: !4)
+!21 = !DILocation(line: 13, scope: !4)
diff --git a/test/DebugInfo/X86/debug-info-access.ll b/test/DebugInfo/X86/debug-info-access.ll
index 7727384d6f70..21da7b2db1bb 100644
--- a/test/DebugInfo/X86/debug-info-access.ll
+++ b/test/DebugInfo/X86/debug-info-access.ll
@@ -106,45 +106,45 @@ attributes #0 = { nounwind ssp uwtable }
 !llvm.module.flags = !{!38, !39}
 !llvm.ident = !{!40}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 \000\00\000\00\001", !1, !2, !3, !29, !34, !2} ; [ DW_TAG_compile_unit ] [/llvm/tools/clang/test/CodeGenCXX/debug-info-access.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"/llvm/tools/clang/test/CodeGenCXX/debug-info-access.cpp", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !29, globals: !34, imports: !2)
+!1 = !DIFile(filename: "/llvm/tools/clang/test/CodeGenCXX/debug-info-access.cpp", directory: "")
 !2 = !{}
 !3 = !{!4, !12, !22}
-!4 = !{!"0x13\00A\003\008\008\000\000\000", !1, null, null, !5, null, null, !"_ZTS1A"} ; [ DW_TAG_structure_type ] [A] [line 3, size 8, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "A", line: 3, size: 8, align: 8, file: !1, elements: !5, identifier: "_ZTS1A")
 !5 = !{!6, !8}
-!6 = !{!"0xd\00pub_default_static\007\000\000\000\004096", !1, !"_ZTS1A", !7, null} ; [ DW_TAG_member ] [pub_default_static] [line 7, size 0, align 0, offset 0] [static] [from int]
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!8 = !{!"0x2e\00pub_default\00pub_default\00_ZN1A11pub_defaultEv\005\000\000\000\006\00256\000\005", !1, !"_ZTS1A", !9, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 5] [pub_default]
-!9 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DIDerivedType(tag: DW_TAG_member, name: "pub_default_static", line: 7, flags: DIFlagStaticMember, file: !1, scope: !"_ZTS1A", baseType: !7)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DISubprogram(name: "pub_default", linkageName: "_ZN1A11pub_defaultEv", line: 5, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !"_ZTS1A", type: !9)
+!9 = !DISubroutineType(types: !10)
 !10 = !{null, !11}
-!11 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1A]
-!12 = !{!"0x2\00B\0011\008\008\000\000\000", !1, null, null, !13, null, null, !"_ZTS1B"} ; [ DW_TAG_class_type ] [B] [line 11, size 8, align 8, offset 0] [def] [from ]
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1A")
+!12 = !DICompositeType(tag: DW_TAG_class_type, name: "B", line: 11, size: 8, align: 8, file: !1, elements: !13, identifier: "_ZTS1B")
 !13 = !{!14, !15, !16, !20, !21}
-!14 = !{!"0x1c\00\000\000\000\000\003", null, !"_ZTS1B", !"_ZTS1A"} ; [ DW_TAG_inheritance ] [line 0, size 0, align 0, offset 0] [public] [from _ZTS1A]
-!15 = !{!"0xd\00public_static\0016\000\000\000\004099", !1, !"_ZTS1B", !7, null} ; [ DW_TAG_member ] [public_static] [line 16, size 0, align 0, offset 0] [public] [static] [from int]
-!16 = !{!"0x2e\00pub\00pub\00_ZN1B3pubEv\0014\000\000\000\006\00259\000\0014", !1, !"_ZTS1B", !17, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 14] [public] [pub]
-!17 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !18, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!14 = !DIDerivedType(tag: DW_TAG_inheritance, flags: DIFlagPublic, scope: !"_ZTS1B", baseType: !"_ZTS1A")
+!15 = !DIDerivedType(tag: DW_TAG_member, name: "public_static", line: 16, flags: DIFlagPublic | DIFlagStaticMember, file: !1, scope: !"_ZTS1B", baseType: !7)
+!16 = !DISubprogram(name: "pub", linkageName: "_ZN1B3pubEv", line: 14, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPublic | DIFlagPrototyped, isOptimized: false, scopeLine: 14, file: !1, scope: !"_ZTS1B", type: !17)
+!17 = !DISubroutineType(types: !18)
 !18 = !{null, !19}
-!19 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1B"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1B]
-!20 = !{!"0x2e\00prot\00prot\00_ZN1B4protEv\0019\000\000\000\006\00258\000\0019", !1, !"_ZTS1B", !17, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 19] [protected] [prot]
-!21 = !{!"0x2e\00priv_default\00priv_default\00_ZN1B12priv_defaultEv\0022\000\000\000\006\00256\000\0022", !1, !"_ZTS1B", !17, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 22] [priv_default]
-!22 = !{!"0x17\00U\0025\0032\0032\000\000\000", !1, null, null, !23, null, null, !"_ZTS1U"} ; [ DW_TAG_union_type ] [U] [line 25, size 32, align 32, offset 0] [def] [from ]
+!19 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1B")
+!20 = !DISubprogram(name: "prot", linkageName: "_ZN1B4protEv", line: 19, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagProtected | DIFlagPrototyped, isOptimized: false, scopeLine: 19, file: !1, scope: !"_ZTS1B", type: !17)
+!21 = !DISubprogram(name: "priv_default", linkageName: "_ZN1B12priv_defaultEv", line: 22, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 22, file: !1, scope: !"_ZTS1B", type: !17)
+!22 = !DICompositeType(tag: DW_TAG_union_type, name: "U", line: 25, size: 32, align: 32, file: !1, elements: !23, identifier: "_ZTS1U")
 !23 = !{!24, !25}
-!24 = !{!"0xd\00union_priv\0030\0032\0032\000\001", !1, !"_ZTS1U", !7} ; [ DW_TAG_member ] [union_priv] [line 30, size 32, align 32, offset 0] [private] [from int]
-!25 = !{!"0x2e\00union_pub_default\00union_pub_default\00_ZN1U17union_pub_defaultEv\0027\000\000\000\006\00256\000\0027", !1, !"_ZTS1U", !26, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 27] [union_pub_default]
-!26 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !27, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!24 = !DIDerivedType(tag: DW_TAG_member, name: "union_priv", line: 30, size: 32, align: 32, flags: DIFlagPrivate, file: !1, scope: !"_ZTS1U", baseType: !7)
+!25 = !DISubprogram(name: "union_pub_default", linkageName: "_ZN1U17union_pub_defaultEv", line: 27, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 27, file: !1, scope: !"_ZTS1U", type: !26)
+!26 = !DISubroutineType(types: !27)
 !27 = !{null, !28}
-!28 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1U"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1U]
+!28 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1U")
 !29 = !{!30}
-!30 = !{!"0x2e\00free\00free\00_Z4freev\0035\000\001\000\006\00256\000\0035", !1, !31, !32, null, void ()* @_Z4freev, null, null, !2} ; [ DW_TAG_subprogram ] [line 35] [def] [free]
-!31 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/llvm/tools/clang/test/CodeGenCXX/debug-info-access.cpp]
-!32 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !33, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!30 = !DISubprogram(name: "free", linkageName: "_Z4freev", line: 35, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 35, file: !1, scope: !31, type: !32, function: void ()* @_Z4freev, variables: !2)
+!31 = !DIFile(filename: "/llvm/tools/clang/test/CodeGenCXX/debug-info-access.cpp", directory: "")
+!32 = !DISubroutineType(types: !33)
 !33 = !{null}
 !34 = !{!35, !36, !37}
-!35 = !{!"0x34\00a\00a\00\0037\000\001", null, !31, !"_ZTS1A", %struct.A* @a, null} ; [ DW_TAG_variable ] [a] [line 37] [def]
-!36 = !{!"0x34\00b\00b\00\0038\000\001", null, !31, !"_ZTS1B", %class.B* @b, null} ; [ DW_TAG_variable ] [b] [line 38] [def]
-!37 = !{!"0x34\00u\00u\00\0039\000\001", null, !31, !"_ZTS1U", %union.U* @u, null} ; [ DW_TAG_variable ] [u] [line 39] [def]
+!35 = !DIGlobalVariable(name: "a", line: 37, isLocal: false, isDefinition: true, scope: null, file: !31, type: !"_ZTS1A", variable: %struct.A* @a)
+!36 = !DIGlobalVariable(name: "b", line: 38, isLocal: false, isDefinition: true, scope: null, file: !31, type: !"_ZTS1B", variable: %class.B* @b)
+!37 = !DIGlobalVariable(name: "u", line: 39, isLocal: false, isDefinition: true, scope: null, file: !31, type: !"_ZTS1U", variable: %union.U* @u)
 !38 = !{i32 2, !"Dwarf Version", i32 2}
-!39 = !{i32 2, !"Debug Info Version", i32 2}
+!39 = !{i32 2, !"Debug Info Version", i32 3}
 !40 = !{!"clang version 3.6.0 "}
-!41 = !MDLocation(line: 35, column: 14, scope: !30)
+!41 = !DILocation(line: 35, column: 14, scope: !30)
diff --git a/test/DebugInfo/X86/debug-info-block-captured-self.ll b/test/DebugInfo/X86/debug-info-block-captured-self.ll
index b7d6dd486bce..e79b093d031a 100644
--- a/test/DebugInfo/X86/debug-info-block-captured-self.ll
+++ b/test/DebugInfo/X86/debug-info-block-captured-self.ll
@@ -66,47 +66,47 @@
 declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
 define internal void @"__24-[Main initWithContext:]_block_invoke"(i8* %.block_descriptor, i8* %obj) #0 {
   %block = bitcast i8* %.block_descriptor to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>*, !dbg !84
-  %block.captured-self = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %block, i32 0, i32 5, !dbg !84
+  %block.captured-self = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %block, i32 0, i32 5, !dbg !84
   call void @llvm.dbg.declare(metadata <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %block, metadata !86, metadata !110), !dbg !87
   ret void, !dbg !87
 }
 
 define internal void @"__24-[Main initWithContext:]_block_invoke_2"(i8* %.block_descriptor, i8* %object) #0 {
   %block = bitcast i8* %.block_descriptor to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>*, !dbg !103
-  %block.captured-self = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %block, i32 0, i32 5, !dbg !103
+  %block.captured-self = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %block, i32 0, i32 5, !dbg !103
   call void @llvm.dbg.declare(metadata <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %block, metadata !105, metadata !109), !dbg !106
   ret void, !dbg !106
 }
 
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!108}
-!0 = !{!"0x11\0016\00clang version 3.3 \000\00\002\00\000", !107, !2, !4, !23, !15,  !15} ; [ DW_TAG_compile_unit ] [llvm/tools/clang/test/CodeGenObjC/debug-info-block-captured-self.m] [DW_LANG_ObjC]
-!1 = !{!"0x29", !107} ; [ DW_TAG_file_type ]
+!0 = !DICompileUnit(language: DW_LANG_ObjC, producer: "clang version 3.3 ", isOptimized: false, runtimeVersion: 2, emissionKind: 0, file: !107, enums: !2, retainedTypes: !4, subprograms: !23, globals: !15, imports:  !15)
+!1 = !DIFile(filename: "llvm/tools/clang/test/CodeGenObjC/debug-info-block-captured-self.m", directory: "")
 !2 = !{!3}
-!3 = !{!"0x4\00\0020\0032\0032\000\000\000", !107, null, null, !4, null, null, null} ; [ DW_TAG_enumeration_type ] [line 20, size 32, align 32, offset 0] [def] [from ]
+!3 = !DICompositeType(tag: DW_TAG_enumeration_type, line: 20, size: 32, align: 32, file: !107, elements: !4)
 !4 = !{}
 !15 = !{}
 !23 = !{!38, !42}
-!27 = !{!"0x16\00id\0031\000\000\000\000", !107, null, !28} ; [ DW_TAG_typedef ] [id] [line 31, size 0, align 0, offset 0] [from ]
-!28 = !{!"0xf\00\000\0064\0064\000\000", null, null, !29} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from objc_object]
-!29 = !{!"0x13\00objc_object\000\000\000\000\000\000", !107, null, null, !30, null, null, null} ; [ DW_TAG_structure_type ] [objc_object] [line 0, size 0, align 0, offset 0] [def] [from ]
+!27 = !DIDerivedType(tag: DW_TAG_typedef, name: "id", line: 31, file: !107, baseType: !28)
+!28 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !29)
+!29 = !DICompositeType(tag: DW_TAG_structure_type, name: "objc_object", file: !107, elements: !30)
 !30 = !{!31}
-!31 = !{!"0xd\00isa\000\0064\000\000\000", !107, !29, !32} ; [ DW_TAG_member ] [isa] [line 0, size 64, align 0, offset 0] [from ]
-!32 = !{!"0xf\00\000\0064\000\000\000", null, null, !33} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from objc_class]
-!33 = !{!"0x13\00objc_class\000\000\000\000\004\000", !107, null, null, null, null, null, null} ; [ DW_TAG_structure_type ] [objc_class] [line 0, size 0, align 0, offset 0] [decl] [from ]
-!34 = !{!"0x13\00Main\0023\000\000\000\001092\0016", !107, null, null, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [Main] [line 23, size 0, align 0, offset 0] [artificial] [decl] [from ]
-!38 = !{!"0x2e\00__24-[Main initWithContext:]_block_invoke\00__24-[Main initWithContext:]_block_invoke\00\0033\001\001\000\006\00256\000\0033", !1, !1, !39, null, void (i8*, i8*)* @"__24-[Main initWithContext:]_block_invoke", null, null, !15} ; [ DW_TAG_subprogram ] [line 33] [local] [def] [__24-[Main initWithContext:]_block_invoke]
-!39 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !40, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!31 = !DIDerivedType(tag: DW_TAG_member, name: "isa", size: 64, file: !107, scope: !29, baseType: !32)
+!32 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, baseType: !33)
+!33 = !DICompositeType(tag: DW_TAG_structure_type, name: "objc_class", flags: DIFlagFwdDecl, file: !107)
+!34 = !DICompositeType(tag: DW_TAG_structure_type, name: "Main", line: 23, flags: DIFlagArtificial | DIFlagObjectPointer, runtimeLang: DW_LANG_ObjC, file: !107)
+!38 = !DISubprogram(name: "__24-[Main initWithContext:]_block_invoke", line: 33, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 33, file: !1, scope: !1, type: !39, function: void (i8*, i8*)* @"__24-[Main initWithContext:]_block_invoke", variables: !15)
+!39 = !DISubroutineType(types: !40)
 !40 = !{null, !41, !27}
-!41 = !{!"0xf\00\000\0064\0064\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!42 = !{!"0x2e\00__24-[Main initWithContext:]_block_invoke_2\00__24-[Main initWithContext:]_block_invoke_2\00\0035\001\001\000\006\00256\000\0035", !1, !1, !39, null, void (i8*, i8*)* @"__24-[Main initWithContext:]_block_invoke_2", null, null, !15} ; [ DW_TAG_subprogram ] [line 35] [local] [def] [__24-[Main initWithContext:]_block_invoke_2]
-!84 = !MDLocation(line: 33, scope: !38)
-!86 = !{!"0x100\00self\0041\000", !38, !1, !34} ; [ DW_TAG_auto_variable ] [self] [line 41]
-!87 = !MDLocation(line: 41, scope: !38)
-!103 = !MDLocation(line: 35, scope: !42)
-!105 = !{!"0x100\00self\0040\000", !42, !1, !34} ; [ DW_TAG_auto_variable ] [self] [line 40]
-!106 = !MDLocation(line: 40, scope: !42)
-!107 = !{!"llvm/tools/clang/test/CodeGenObjC/debug-info-block-captured-self.m", !""}
-!108 = !{i32 1, !"Debug Info Version", i32 2}
-!109 = !{!"0x102\0034\0032"} ; [ DW_TAG_expression ] [DW_OP_plus 32]
-!110 = !{!"0x102\0034\0032"} ; [ DW_TAG_expression ] [DW_OP_plus 32]
+!41 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: null)
+!42 = !DISubprogram(name: "__24-[Main initWithContext:]_block_invoke_2", line: 35, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 35, file: !1, scope: !1, type: !39, function: void (i8*, i8*)* @"__24-[Main initWithContext:]_block_invoke_2", variables: !15)
+!84 = !DILocation(line: 33, scope: !38)
+!86 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "self", line: 41, scope: !38, file: !1, type: !34)
+!87 = !DILocation(line: 41, scope: !38)
+!103 = !DILocation(line: 35, scope: !42)
+!105 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "self", line: 40, scope: !42, file: !1, type: !34)
+!106 = !DILocation(line: 40, scope: !42)
+!107 = !DIFile(filename: "llvm/tools/clang/test/CodeGenObjC/debug-info-block-captured-self.m", directory: "")
+!108 = !{i32 1, !"Debug Info Version", i32 3}
+!109 = !DIExpression(DW_OP_deref, DW_OP_plus, 32)
+!110 = !DIExpression(DW_OP_deref, DW_OP_plus, 32)
diff --git a/test/DebugInfo/X86/debug-info-blocks.ll b/test/DebugInfo/X86/debug-info-blocks.ll
index 7cba57f69911..a9aadfdb7313 100644
--- a/test/DebugInfo/X86/debug-info-blocks.ll
+++ b/test/DebugInfo/X86/debug-info-blocks.ll
@@ -67,33 +67,33 @@ target triple = "x86_64-apple-darwin"
 @"OBJC_CLASS_$_A" = global %struct._class_t { %struct._class_t* @"OBJC_METACLASS_$_A", %struct._class_t* @"OBJC_CLASS_$_NSObject", %struct._objc_cache* @_objc_empty_cache, i8* (i8*, i8*)** @_objc_empty_vtable, %struct._class_ro_t* @"\01l_OBJC_CLASS_RO_$_A" }, section "__DATA, __objc_data", align 8
 @"\01L_OBJC_CLASSLIST_SUP_REFS_$_" = internal global %struct._class_t* @"OBJC_CLASS_$_A", section "__DATA, __objc_superrefs, regular, no_dead_strip", align 8
 @"\01L_OBJC_METH_VAR_NAME_" = internal global [5 x i8] c"init\00", section "__TEXT,__objc_methname,cstring_literals", align 1
-@"\01L_OBJC_SELECTOR_REFERENCES_" = internal externally_initialized global i8* getelementptr inbounds ([5 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
+@"\01L_OBJC_SELECTOR_REFERENCES_" = internal externally_initialized global i8* getelementptr inbounds ([5 x i8], [5 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
 @"OBJC_CLASS_$_NSMutableDictionary" = external global %struct._class_t
 @"\01L_OBJC_CLASSLIST_REFERENCES_$_" = internal global %struct._class_t* @"OBJC_CLASS_$_NSMutableDictionary", section "__DATA, __objc_classrefs, regular, no_dead_strip", align 8
 @"\01L_OBJC_METH_VAR_NAME_1" = internal global [6 x i8] c"alloc\00", section "__TEXT,__objc_methname,cstring_literals", align 1
-@"\01l_objc_msgSend_fixup_alloc" = weak hidden global { i8* (i8*, %struct._message_ref_t*, ...)*, i8* } { i8* (i8*, %struct._message_ref_t*, ...)* @objc_msgSend_fixup, i8* getelementptr inbounds ([6 x i8]* @"\01L_OBJC_METH_VAR_NAME_1", i32 0, i32 0) }, section "__DATA, __objc_msgrefs, coalesced", align 16
+@"\01l_objc_msgSend_fixup_alloc" = weak hidden global { i8* (i8*, %struct._message_ref_t*, ...)*, i8* } { i8* (i8*, %struct._message_ref_t*, ...)* @objc_msgSend_fixup, i8* getelementptr inbounds ([6 x i8], [6 x i8]* @"\01L_OBJC_METH_VAR_NAME_1", i32 0, i32 0) }, section "__DATA, __objc_msgrefs, coalesced", align 16
 @"\01L_OBJC_METH_VAR_NAME_2" = internal global [6 x i8] c"count\00", section "__TEXT,__objc_methname,cstring_literals", align 1
-@"\01l_objc_msgSend_fixup_count" = weak hidden global { i8* (i8*, %struct._message_ref_t*, ...)*, i8* } { i8* (i8*, %struct._message_ref_t*, ...)* @objc_msgSend_fixup, i8* getelementptr inbounds ([6 x i8]* @"\01L_OBJC_METH_VAR_NAME_2", i32 0, i32 0) }, section "__DATA, __objc_msgrefs, coalesced", align 16
+@"\01l_objc_msgSend_fixup_count" = weak hidden global { i8* (i8*, %struct._message_ref_t*, ...)*, i8* } { i8* (i8*, %struct._message_ref_t*, ...)* @objc_msgSend_fixup, i8* getelementptr inbounds ([6 x i8], [6 x i8]* @"\01L_OBJC_METH_VAR_NAME_2", i32 0, i32 0) }, section "__DATA, __objc_msgrefs, coalesced", align 16
 @"OBJC_IVAR_$_A.ivar" = global i64 0, section "__DATA, __objc_ivar", align 8
 @_NSConcreteStackBlock = external global i8*
 @.str = private unnamed_addr constant [6 x i8] c"v8@?0\00", align 1
-@__block_descriptor_tmp = internal constant { i64, i64, i8*, i8*, i8*, i64 } { i64 0, i64 40, i8* bitcast (void (i8*, i8*)* @__copy_helper_block_ to i8*), i8* bitcast (void (i8*)* @__destroy_helper_block_ to i8*), i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), i64 256 }
+@__block_descriptor_tmp = internal constant { i64, i64, i8*, i8*, i8*, i64 } { i64 0, i64 40, i8* bitcast (void (i8*, i8*)* @__copy_helper_block_ to i8*), i8* bitcast (void (i8*)* @__destroy_helper_block_ to i8*), i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), i64 256 }
 @_objc_empty_cache = external global %struct._objc_cache
 @_objc_empty_vtable = external global i8* (i8*, i8*)*
 @"OBJC_METACLASS_$_NSObject" = external global %struct._class_t
 @"\01L_OBJC_CLASS_NAME_" = internal global [2 x i8] c"A\00", section "__TEXT,__objc_classname,cstring_literals", align 1
-@"\01l_OBJC_METACLASS_RO_$_A" = internal global %struct._class_ro_t { i32 1, i32 40, i32 40, i8* null, i8* getelementptr inbounds ([2 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), %struct.__method_list_t* null, %struct._objc_protocol_list* null, %struct._ivar_list_t* null, i8* null, %struct._prop_list_t* null }, section "__DATA, __objc_const", align 8
+@"\01l_OBJC_METACLASS_RO_$_A" = internal global %struct._class_ro_t { i32 1, i32 40, i32 40, i8* null, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), %struct.__method_list_t* null, %struct._objc_protocol_list* null, %struct._ivar_list_t* null, i8* null, %struct._prop_list_t* null }, section "__DATA, __objc_const", align 8
 @"OBJC_METACLASS_$_A" = global %struct._class_t { %struct._class_t* @"OBJC_METACLASS_$_NSObject", %struct._class_t* @"OBJC_METACLASS_$_NSObject", %struct._objc_cache* @_objc_empty_cache, i8* (i8*, i8*)** @_objc_empty_vtable, %struct._class_ro_t* @"\01l_OBJC_METACLASS_RO_$_A" }, section "__DATA, __objc_data", align 8
 @"OBJC_CLASS_$_NSObject" = external global %struct._class_t
 @"\01L_OBJC_METH_VAR_TYPE_" = internal global [8 x i8] c"@16@0:8\00", section "__TEXT,__objc_methtype,cstring_literals", align 1
-@"\01l_OBJC_$_INSTANCE_METHODS_A" = internal global { i32, i32, [1 x %struct._objc_method] } { i32 24, i32 1, [1 x %struct._objc_method] [%struct._objc_method { i8* getelementptr inbounds ([5 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @"\01L_OBJC_METH_VAR_TYPE_", i32 0, i32 0), i8* bitcast (i8* (%0*, i8*)* @"\01-[A init]" to i8*) }] }, section "__DATA, __objc_const", align 8
+@"\01l_OBJC_$_INSTANCE_METHODS_A" = internal global { i32, i32, [1 x %struct._objc_method] } { i32 24, i32 1, [1 x %struct._objc_method] [%struct._objc_method { i8* getelementptr inbounds ([5 x i8], [5 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([8 x i8], [8 x i8]* @"\01L_OBJC_METH_VAR_TYPE_", i32 0, i32 0), i8* bitcast (i8* (%0*, i8*)* @"\01-[A init]" to i8*) }] }, section "__DATA, __objc_const", align 8
 @"\01L_OBJC_METH_VAR_NAME_3" = internal global [5 x i8] c"ivar\00", section "__TEXT,__objc_methname,cstring_literals", align 1
 @"\01L_OBJC_METH_VAR_TYPE_4" = internal global [2 x i8] c"i\00", section "__TEXT,__objc_methtype,cstring_literals", align 1
-@"\01l_OBJC_$_INSTANCE_VARIABLES_A" = internal global { i32, i32, [1 x %struct._ivar_t] } { i32 32, i32 1, [1 x %struct._ivar_t] [%struct._ivar_t { i64* @"OBJC_IVAR_$_A.ivar", i8* getelementptr inbounds ([5 x i8]* @"\01L_OBJC_METH_VAR_NAME_3", i32 0, i32 0), i8* getelementptr inbounds ([2 x i8]* @"\01L_OBJC_METH_VAR_TYPE_4", i32 0, i32 0), i32 2, i32 4 }] }, section "__DATA, __objc_const", align 8
-@"\01l_OBJC_CLASS_RO_$_A" = internal global %struct._class_ro_t { i32 0, i32 0, i32 4, i8* null, i8* getelementptr inbounds ([2 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), %struct.__method_list_t* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_INSTANCE_METHODS_A" to %struct.__method_list_t*), %struct._objc_protocol_list* null, %struct._ivar_list_t* bitcast ({ i32, i32, [1 x %struct._ivar_t] }* @"\01l_OBJC_$_INSTANCE_VARIABLES_A" to %struct._ivar_list_t*), i8* null, %struct._prop_list_t* null }, section "__DATA, __objc_const", align 8
+@"\01l_OBJC_$_INSTANCE_VARIABLES_A" = internal global { i32, i32, [1 x %struct._ivar_t] } { i32 32, i32 1, [1 x %struct._ivar_t] [%struct._ivar_t { i64* @"OBJC_IVAR_$_A.ivar", i8* getelementptr inbounds ([5 x i8], [5 x i8]* @"\01L_OBJC_METH_VAR_NAME_3", i32 0, i32 0), i8* getelementptr inbounds ([2 x i8], [2 x i8]* @"\01L_OBJC_METH_VAR_TYPE_4", i32 0, i32 0), i32 2, i32 4 }] }, section "__DATA, __objc_const", align 8
+@"\01l_OBJC_CLASS_RO_$_A" = internal global %struct._class_ro_t { i32 0, i32 0, i32 4, i8* null, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), %struct.__method_list_t* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_INSTANCE_METHODS_A" to %struct.__method_list_t*), %struct._objc_protocol_list* null, %struct._ivar_list_t* bitcast ({ i32, i32, [1 x %struct._ivar_t] }* @"\01l_OBJC_$_INSTANCE_VARIABLES_A" to %struct._ivar_list_t*), i8* null, %struct._prop_list_t* null }, section "__DATA, __objc_const", align 8
 @"\01L_OBJC_CLASSLIST_REFERENCES_$_5" = internal global %struct._class_t* @"OBJC_CLASS_$_A", section "__DATA, __objc_classrefs, regular, no_dead_strip", align 8
 @"\01L_OBJC_LABEL_CLASS_$" = internal global [1 x i8*] [i8* bitcast (%struct._class_t* @"OBJC_CLASS_$_A" to i8*)], section "__DATA, __objc_classlist, regular, no_dead_strip", align 8
-@llvm.used = appending global [14 x i8*] [i8* bitcast (%struct._class_t** @"\01L_OBJC_CLASSLIST_SUP_REFS_$_" to i8*), i8* getelementptr inbounds ([5 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* bitcast (%struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_" to i8*), i8* getelementptr inbounds ([6 x i8]* @"\01L_OBJC_METH_VAR_NAME_1", i32 0, i32 0), i8* getelementptr inbounds ([6 x i8]* @"\01L_OBJC_METH_VAR_NAME_2", i32 0, i32 0), i8* getelementptr inbounds ([2 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @"\01L_OBJC_METH_VAR_TYPE_", i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_INSTANCE_METHODS_A" to i8*), i8* getelementptr inbounds ([5 x i8]* @"\01L_OBJC_METH_VAR_NAME_3", i32 0, i32 0), i8* getelementptr inbounds ([2 x i8]* @"\01L_OBJC_METH_VAR_TYPE_4", i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._ivar_t] }* @"\01l_OBJC_$_INSTANCE_VARIABLES_A" to i8*), i8* bitcast (%struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_5" to i8*), i8* bitcast ([1 x i8*]* @"\01L_OBJC_LABEL_CLASS_$" to i8*)], section "llvm.metadata"
+@llvm.used = appending global [14 x i8*] [i8* bitcast (%struct._class_t** @"\01L_OBJC_CLASSLIST_SUP_REFS_$_" to i8*), i8* getelementptr inbounds ([5 x i8], [5 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* bitcast (%struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_" to i8*), i8* getelementptr inbounds ([6 x i8], [6 x i8]* @"\01L_OBJC_METH_VAR_NAME_1", i32 0, i32 0), i8* getelementptr inbounds ([6 x i8], [6 x i8]* @"\01L_OBJC_METH_VAR_NAME_2", i32 0, i32 0), i8* getelementptr inbounds ([2 x i8], [2 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([8 x i8], [8 x i8]* @"\01L_OBJC_METH_VAR_TYPE_", i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_INSTANCE_METHODS_A" to i8*), i8* getelementptr inbounds ([5 x i8], [5 x i8]* @"\01L_OBJC_METH_VAR_NAME_3", i32 0, i32 0), i8* getelementptr inbounds ([2 x i8], [2 x i8]* @"\01L_OBJC_METH_VAR_TYPE_4", i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._ivar_t] }* @"\01l_OBJC_$_INSTANCE_VARIABLES_A" to i8*), i8* bitcast (%struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_5" to i8*), i8* bitcast ([1 x i8*]* @"\01L_OBJC_LABEL_CLASS_$" to i8*)], section "llvm.metadata"
 
 define internal i8* @"\01-[A init]"(%0* %self, i8* %_cmd) #0 {
   %1 = alloca %0*, align 8
@@ -101,18 +101,18 @@ define internal i8* @"\01-[A init]"(%0* %self, i8* %_cmd) #0 {
   %3 = alloca %struct._objc_super
   %4 = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>, align 8
   store %0* %self, %0** %1, align 8
-  call void @llvm.dbg.declare(metadata %0** %1, metadata !60, metadata !{!"0x102"}), !dbg !62
+  call void @llvm.dbg.declare(metadata %0** %1, metadata !60, metadata !DIExpression()), !dbg !62
   store i8* %_cmd, i8** %2, align 8
-  call void @llvm.dbg.declare(metadata i8** %2, metadata !63, metadata !{!"0x102"}), !dbg !62
-  %5 = load %0** %1, !dbg !65
+  call void @llvm.dbg.declare(metadata i8** %2, metadata !63, metadata !DIExpression()), !dbg !62
+  %5 = load %0*, %0** %1, !dbg !65
   %6 = bitcast %0* %5 to i8*, !dbg !65
-  %7 = getelementptr inbounds %struct._objc_super* %3, i32 0, i32 0, !dbg !65
+  %7 = getelementptr inbounds %struct._objc_super, %struct._objc_super* %3, i32 0, i32 0, !dbg !65
   store i8* %6, i8** %7, !dbg !65
-  %8 = load %struct._class_t** @"\01L_OBJC_CLASSLIST_SUP_REFS_$_", !dbg !65
+  %8 = load %struct._class_t*, %struct._class_t** @"\01L_OBJC_CLASSLIST_SUP_REFS_$_", !dbg !65
   %9 = bitcast %struct._class_t* %8 to i8*, !dbg !65
-  %10 = getelementptr inbounds %struct._objc_super* %3, i32 0, i32 1, !dbg !65
+  %10 = getelementptr inbounds %struct._objc_super, %struct._objc_super* %3, i32 0, i32 1, !dbg !65
   store i8* %9, i8** %10, !dbg !65
-  %11 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", !dbg !65, !invariant.load !67
+  %11 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", !dbg !65, !invariant.load !67
   %12 = call i8* bitcast (i8* (%struct._objc_super*, i8*, ...)* @objc_msgSendSuper2 to i8* (%struct._objc_super*, i8*)*)(%struct._objc_super* %3, i8* %11), !dbg !65
   %13 = bitcast i8* %12 to %0*, !dbg !65
   store %0* %13, %0** %1, align 8, !dbg !65
@@ -120,25 +120,25 @@ define internal i8* @"\01-[A init]"(%0* %self, i8* %_cmd) #0 {
   br i1 %14, label %15, label %24, !dbg !65
 
 ; <label>:15                                      ; preds = %0
-  %16 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 0, !dbg !68
+  %16 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 0, !dbg !68
   store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** %16, !dbg !68
-  %17 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 1, !dbg !68
+  %17 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 1, !dbg !68
   store i32 -1040187392, i32* %17, !dbg !68
-  %18 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 2, !dbg !68
+  %18 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 2, !dbg !68
   store i32 0, i32* %18, !dbg !68
-  %19 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 3, !dbg !68
+  %19 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 3, !dbg !68
   store i8* bitcast (void (i8*)* @"__9-[A init]_block_invoke" to i8*), i8** %19, !dbg !68
-  %20 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 4, !dbg !68
+  %20 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 4, !dbg !68
   store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8*, i8*, i64 }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** %20, !dbg !68
-  %21 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 5, !dbg !68
-  %22 = load %0** %1, align 8, !dbg !68
+  %21 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 5, !dbg !68
+  %22 = load %0*, %0** %1, align 8, !dbg !68
   store %0* %22, %0** %21, align 8, !dbg !68
   %23 = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4 to void ()*, !dbg !68
   call void @run(void ()* %23), !dbg !68
   br label %24, !dbg !70
 
 ; <label>:24                                      ; preds = %15, %0
-  %25 = load %0** %1, align 8, !dbg !71
+  %25 = load %0*, %0** %1, align 8, !dbg !71
   %26 = bitcast %0* %25 to i8*, !dbg !71
   ret i8* %26, !dbg !71
 }
@@ -150,12 +150,12 @@ declare i8* @objc_msgSendSuper2(%struct._objc_super*, i8*, ...)
 define internal void @run(void ()* %block) #0 {
   %1 = alloca void ()*, align 8
   store void ()* %block, void ()** %1, align 8
-  call void @llvm.dbg.declare(metadata void ()** %1, metadata !72, metadata !{!"0x102"}), !dbg !73
-  %2 = load void ()** %1, align 8, !dbg !74
+  call void @llvm.dbg.declare(metadata void ()** %1, metadata !72, metadata !DIExpression()), !dbg !73
+  %2 = load void ()*, void ()** %1, align 8, !dbg !74
   %3 = bitcast void ()* %2 to %struct.__block_literal_generic*, !dbg !74
-  %4 = getelementptr inbounds %struct.__block_literal_generic* %3, i32 0, i32 3, !dbg !74
+  %4 = getelementptr inbounds %struct.__block_literal_generic, %struct.__block_literal_generic* %3, i32 0, i32 3, !dbg !74
   %5 = bitcast %struct.__block_literal_generic* %3 to i8*, !dbg !74
-  %6 = load i8** %4, !dbg !74
+  %6 = load i8*, i8** %4, !dbg !74
   %7 = bitcast i8* %6 to void (i8*)*, !dbg !74
   call void %7(i8* %5), !dbg !74
   ret void, !dbg !75
@@ -166,35 +166,35 @@ define internal void @"__9-[A init]_block_invoke"(i8* %.block_descriptor) #0 {
   %2 = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>*, align 8
   %d = alloca %1*, align 8
   store i8* %.block_descriptor, i8** %1, align 8
-  %3 = load i8** %1
-  call void @llvm.dbg.value(metadata i8* %3, i64 0, metadata !76, metadata !{!"0x102"}), !dbg !88
-  call void @llvm.dbg.declare(metadata i8* %.block_descriptor, metadata !76, metadata !{!"0x102"}), !dbg !88
+  %3 = load i8*, i8** %1
+  call void @llvm.dbg.value(metadata i8* %3, i64 0, metadata !76, metadata !DIExpression()), !dbg !88
+  call void @llvm.dbg.declare(metadata i8* %.block_descriptor, metadata !76, metadata !DIExpression()), !dbg !88
   %4 = bitcast i8* %.block_descriptor to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>*, !dbg !88
   store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>** %2, align 8, !dbg !88
-  %5 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 5, !dbg !88
+  %5 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 5, !dbg !88
   call void @llvm.dbg.declare(metadata <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>** %2, metadata !89, metadata !111), !dbg !90
-  call void @llvm.dbg.declare(metadata %1** %d, metadata !91, metadata !{!"0x102"}), !dbg !100
-  %6 = load %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_", !dbg !100
+  call void @llvm.dbg.declare(metadata %1** %d, metadata !91, metadata !DIExpression()), !dbg !100
+  %6 = load %struct._class_t*, %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_", !dbg !100
   %7 = bitcast %struct._class_t* %6 to i8*, !dbg !100
-  %8 = load i8** getelementptr inbounds (%struct._message_ref_t* bitcast ({ i8* (i8*, %struct._message_ref_t*, ...)*, i8* }* @"\01l_objc_msgSend_fixup_alloc" to %struct._message_ref_t*), i32 0, i32 0), !dbg !100
+  %8 = load i8*, i8** getelementptr inbounds (%struct._message_ref_t, %struct._message_ref_t* bitcast ({ i8* (i8*, %struct._message_ref_t*, ...)*, i8* }* @"\01l_objc_msgSend_fixup_alloc" to %struct._message_ref_t*), i32 0, i32 0), !dbg !100
   %9 = bitcast i8* %8 to i8* (i8*, i8*)*, !dbg !100
   %10 = call i8* %9(i8* %7, i8* bitcast ({ i8* (i8*, %struct._message_ref_t*, ...)*, i8* }* @"\01l_objc_msgSend_fixup_alloc" to i8*)), !dbg !100
   %11 = bitcast i8* %10 to %1*, !dbg !100
-  %12 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", !dbg !100, !invariant.load !67
+  %12 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", !dbg !100, !invariant.load !67
   %13 = bitcast %1* %11 to i8*, !dbg !100
   %14 = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %13, i8* %12), !dbg !100
   %15 = bitcast i8* %14 to %1*, !dbg !100
   store %1* %15, %1** %d, align 8, !dbg !100
-  %16 = load %1** %d, align 8, !dbg !101
+  %16 = load %1*, %1** %d, align 8, !dbg !101
   %17 = bitcast %1* %16 to i8*, !dbg !101
-  %18 = load i8** getelementptr inbounds (%struct._message_ref_t* bitcast ({ i8* (i8*, %struct._message_ref_t*, ...)*, i8* }* @"\01l_objc_msgSend_fixup_count" to %struct._message_ref_t*), i32 0, i32 0), !dbg !101
+  %18 = load i8*, i8** getelementptr inbounds (%struct._message_ref_t, %struct._message_ref_t* bitcast ({ i8* (i8*, %struct._message_ref_t*, ...)*, i8* }* @"\01l_objc_msgSend_fixup_count" to %struct._message_ref_t*), i32 0, i32 0), !dbg !101
   %19 = bitcast i8* %18 to i32 (i8*, i8*)*, !dbg !101
   %20 = call i32 %19(i8* %17, i8* bitcast ({ i8* (i8*, %struct._message_ref_t*, ...)*, i8* }* @"\01l_objc_msgSend_fixup_count" to i8*)), !dbg !101
   %21 = add nsw i32 42, %20, !dbg !101
-  %22 = load %0** %5, align 8, !dbg !101
-  %23 = load i64* @"OBJC_IVAR_$_A.ivar", !dbg !101, !invariant.load !67
+  %22 = load %0*, %0** %5, align 8, !dbg !101
+  %23 = load i64, i64* @"OBJC_IVAR_$_A.ivar", !dbg !101, !invariant.load !67
   %24 = bitcast %0* %22 to i8*, !dbg !101
-  %25 = getelementptr inbounds i8* %24, i64 %23, !dbg !101
+  %25 = getelementptr inbounds i8, i8* %24, i64 %23, !dbg !101
   %26 = bitcast i8* %25 to i32*, !dbg !101
   store i32 %21, i32* %26, align 4, !dbg !101
   ret void, !dbg !90
@@ -210,16 +210,16 @@ define internal void @__copy_helper_block_(i8*, i8*) {
   %3 = alloca i8*, align 8
   %4 = alloca i8*, align 8
   store i8* %0, i8** %3, align 8
-  call void @llvm.dbg.declare(metadata i8** %3, metadata !102, metadata !{!"0x102"}), !dbg !103
+  call void @llvm.dbg.declare(metadata i8** %3, metadata !102, metadata !DIExpression()), !dbg !103
   store i8* %1, i8** %4, align 8
-  call void @llvm.dbg.declare(metadata i8** %4, metadata !104, metadata !{!"0x102"}), !dbg !103
-  %5 = load i8** %4, !dbg !103
+  call void @llvm.dbg.declare(metadata i8** %4, metadata !104, metadata !DIExpression()), !dbg !103
+  %5 = load i8*, i8** %4, !dbg !103
   %6 = bitcast i8* %5 to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>*, !dbg !103
-  %7 = load i8** %3, !dbg !103
+  %7 = load i8*, i8** %3, !dbg !103
   %8 = bitcast i8* %7 to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>*, !dbg !103
-  %9 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %6, i32 0, i32 5, !dbg !103
-  %10 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %8, i32 0, i32 5, !dbg !103
-  %11 = load %0** %9, !dbg !103
+  %9 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %6, i32 0, i32 5, !dbg !103
+  %10 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %8, i32 0, i32 5, !dbg !103
+  %11 = load %0*, %0** %9, !dbg !103
   %12 = bitcast %0* %11 to i8*, !dbg !103
   %13 = bitcast %0** %10 to i8*, !dbg !103
   call void @_Block_object_assign(i8* %13, i8* %12, i32 3) #3, !dbg !103
@@ -231,11 +231,11 @@ declare void @_Block_object_assign(i8*, i8*, i32)
 define internal void @__destroy_helper_block_(i8*) {
   %2 = alloca i8*, align 8
   store i8* %0, i8** %2, align 8
-  call void @llvm.dbg.declare(metadata i8** %2, metadata !105, metadata !{!"0x102"}), !dbg !106
-  %3 = load i8** %2, !dbg !106
+  call void @llvm.dbg.declare(metadata i8** %2, metadata !105, metadata !DIExpression()), !dbg !106
+  %3 = load i8*, i8** %2, !dbg !106
   %4 = bitcast i8* %3 to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>*, !dbg !106
-  %5 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 5, !dbg !106
-  %6 = load %0** %5, !dbg !106
+  %5 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %4, i32 0, i32 5, !dbg !106
+  %6 = load %0*, %0** %5, !dbg !106
   %7 = bitcast %0* %6 to i8*, !dbg !106
   call void @_Block_object_dispose(i8* %7, i32 3) #3, !dbg !106
   ret void, !dbg !106
@@ -247,14 +247,14 @@ define i32 @main() #0 {
   %1 = alloca i32, align 4
   %a = alloca %0*, align 8
   store i32 0, i32* %1
-  call void @llvm.dbg.declare(metadata %0** %a, metadata !107, metadata !{!"0x102"}), !dbg !108
-  %2 = load %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_5", !dbg !108
+  call void @llvm.dbg.declare(metadata %0** %a, metadata !107, metadata !DIExpression()), !dbg !108
+  %2 = load %struct._class_t*, %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_5", !dbg !108
   %3 = bitcast %struct._class_t* %2 to i8*, !dbg !108
-  %4 = load i8** getelementptr inbounds (%struct._message_ref_t* bitcast ({ i8* (i8*, %struct._message_ref_t*, ...)*, i8* }* @"\01l_objc_msgSend_fixup_alloc" to %struct._message_ref_t*), i32 0, i32 0), !dbg !108
+  %4 = load i8*, i8** getelementptr inbounds (%struct._message_ref_t, %struct._message_ref_t* bitcast ({ i8* (i8*, %struct._message_ref_t*, ...)*, i8* }* @"\01l_objc_msgSend_fixup_alloc" to %struct._message_ref_t*), i32 0, i32 0), !dbg !108
   %5 = bitcast i8* %4 to i8* (i8*, i8*)*, !dbg !108
   %6 = call i8* %5(i8* %3, i8* bitcast ({ i8* (i8*, %struct._message_ref_t*, ...)*, i8* }* @"\01l_objc_msgSend_fixup_alloc" to i8*)), !dbg !108
   %7 = bitcast i8* %6 to %0*, !dbg !108
-  %8 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", !dbg !108, !invariant.load !67
+  %8 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", !dbg !108, !invariant.load !67
   %9 = bitcast %0* %7 to i8*, !dbg !108
   %10 = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %9, i8* %8), !dbg !108
   %11 = bitcast i8* %10 to %0*, !dbg !108
@@ -270,115 +270,115 @@ attributes #3 = { nounwind }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!56, !57, !58, !59, !110}
 
-!0 = !{!"0x11\0016\00clang version 3.3 \000\00\002\00\001", !1, !2, !3, !12, !2,  !2} ; [ DW_TAG_compile_unit ] [llvm/tools/clang/test/CodeGenObjC/<unknown>] [DW_LANG_ObjC]
-!1 = !{!"llvm/tools/clang/test/CodeGenObjC/<unknown>", !"llvm/_build.ninja.Debug"}
+!0 = !DICompileUnit(language: DW_LANG_ObjC, producer: "clang version 3.3 ", isOptimized: false, runtimeVersion: 2, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !12, globals: !2, imports:  !2)
+!1 = !DIFile(filename: "llvm/tools/clang/test/CodeGenObjC/<unknown>", directory: "llvm/_build.ninja.Debug")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00A\0033\0032\0032\000\00512\0016", !5, !6, null, !7, null, null, null} ; [ DW_TAG_structure_type ] [A] [line 33, size 32, align 32, offset 0] [def] [from ]
-!5 = !{!"llvm/tools/clang/test/CodeGenObjC/debug-info-blocks.m", !"llvm/_build.ninja.Debug"}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [llvm/tools/clang/test/CodeGenObjC/debug-info-blocks.m]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "A", line: 33, size: 32, align: 32, flags: DIFlagObjcClassComplete, runtimeLang: DW_LANG_ObjC, file: !5, scope: !6, elements: !7)
+!5 = !DIFile(filename: "llvm/tools/clang/test/CodeGenObjC/debug-info-blocks.m", directory: "llvm/_build.ninja.Debug")
+!6 = !DIFile(filename: "llvm/tools/clang/test/CodeGenObjC/debug-info-blocks.m", directory: "llvm/_build.ninja.Debug")
 !7 = !{!8, !10}
-!8 = !{!"0x1c\00\000\000\000\000\000", null, !4, !9} ; [ DW_TAG_inheritance ] [line 0, size 0, align 0, offset 0] [from NSObject]
-!9 = !{!"0x13\00NSObject\0021\000\008\000\000\0016", !5, !6, null, !2, null, null, null} ; [ DW_TAG_structure_type ] [NSObject] [line 21, size 0, align 8, offset 0] [def] [from ]
-!10 = !{!"0xd\00ivar\0035\0032\0032\000\000", !5, !6, !11, null} ; [ DW_TAG_member ] [ivar] [line 35, size 32, align 32, offset 0] [from int]
-!11 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIDerivedType(tag: DW_TAG_inheritance, scope: !4, baseType: !9)
+!9 = !DICompositeType(tag: DW_TAG_structure_type, name: "NSObject", line: 21, align: 8, runtimeLang: DW_LANG_ObjC, file: !5, scope: !6, elements: !2)
+!10 = !DIDerivedType(tag: DW_TAG_member, name: "ivar", line: 35, size: 32, align: 32, file: !5, scope: !6, baseType: !11)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !12 = !{!13, !27, !31, !35, !36, !39}
-!13 = !{!"0x2e\00-[A init]\00-[A init]\00\0046\001\001\000\006\00256\000\0046", !5, !6, !14, null, i8* (%0*, i8*)* @"\01-[A init]", null, null, !2} ; [ DW_TAG_subprogram ] [line 46] [local] [def] [-[A init]]
-!14 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !15, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DISubprogram(name: "-[A init]", line: 46, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 46, file: !5, scope: !6, type: !14, function: i8* (%0*, i8*)* @"\01-[A init]", variables: !2)
+!14 = !DISubroutineType(types: !15)
 !15 = !{!16, !23, !24}
-!16 = !{!"0x16\00id\0046\000\000\000\000", !5, null, !17} ; [ DW_TAG_typedef ] [id] [line 46, size 0, align 0, offset 0] [from ]
-!17 = !{!"0xf\00\000\0064\0064\000\000", null, null, !18} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from objc_object]
-!18 = !{!"0x13\00objc_object\000\000\000\000\000\000", !1, null, null, !19, null, null, null} ; [ DW_TAG_structure_type ] [objc_object] [line 0, size 0, align 0, offset 0] [def] [from ]
+!16 = !DIDerivedType(tag: DW_TAG_typedef, name: "id", line: 46, file: !5, baseType: !17)
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !18)
+!18 = !DICompositeType(tag: DW_TAG_structure_type, name: "objc_object", file: !1, elements: !19)
 !19 = !{!20}
-!20 = !{!"0xd\00isa\000\0064\000\000\000", !1, !18, !21} ; [ DW_TAG_member ] [isa] [line 0, size 64, align 0, offset 0] [from ]
-!21 = !{!"0xf\00\000\0064\000\000\000", null, null, !22} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from objc_class]
-!22 = !{!"0x13\00objc_class\000\000\000\000\004\000", !1, null, null, null, null, null, null} ; [ DW_TAG_structure_type ] [objc_class] [line 0, size 0, align 0, offset 0] [decl] [from ]
-!23 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !4} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from A]
-!24 = !{!"0x16\00SEL\0046\000\000\000\0064", !5, null, !25} ; [ DW_TAG_typedef ] [SEL] [line 46, size 0, align 0, offset 0] [artificial] [from ]
-!25 = !{!"0xf\00\000\0064\0064\000\000", null, null, !26} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from objc_selector]
-!26 = !{!"0x13\00objc_selector\000\000\000\000\004\000", !1, null, null, null, null, null, null} ; [ DW_TAG_structure_type ] [objc_selector] [line 0, size 0, align 0, offset 0] [decl] [from ]
-!27 = !{!"0x2e\00__9-[A init]_block_invoke\00__9-[A init]_block_invoke\00\0049\001\001\000\006\00256\000\0049", !5, !6, !28, null, void (i8*)* @"__9-[A init]_block_invoke", null, null, !2} ; [ DW_TAG_subprogram ] [line 49] [local] [def] [__9-[A init]_block_invoke]
-!28 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !29, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!20 = !DIDerivedType(tag: DW_TAG_member, name: "isa", size: 64, file: !1, scope: !18, baseType: !21)
+!21 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, baseType: !22)
+!22 = !DICompositeType(tag: DW_TAG_structure_type, name: "objc_class", flags: DIFlagFwdDecl, file: !1)
+!23 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !4)
+!24 = !DIDerivedType(tag: DW_TAG_typedef, name: "SEL", line: 46, flags: DIFlagArtificial, file: !5, baseType: !25)
+!25 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !26)
+!26 = !DICompositeType(tag: DW_TAG_structure_type, name: "objc_selector", flags: DIFlagFwdDecl, file: !1)
+!27 = !DISubprogram(name: "__9-[A init]_block_invoke", line: 49, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 49, file: !5, scope: !6, type: !28, function: void (i8*)* @"__9-[A init]_block_invoke", variables: !2)
+!28 = !DISubroutineType(types: !29)
 !29 = !{null, !30}
-!30 = !{!"0xf\00\000\0064\0064\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!31 = !{!"0x2e\00__copy_helper_block_\00__copy_helper_block_\00\0052\001\001\000\006\000\000\0052", !1, !32, !33, null, void (i8*, i8*)* @__copy_helper_block_, null, null, !2} ; [ DW_TAG_subprogram ] [line 52] [local] [def] [__copy_helper_block_]
-!32 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [llvm/tools/clang/test/CodeGenObjC/<unknown>]
-!33 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !34, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!30 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: null)
+!31 = !DISubprogram(name: "__copy_helper_block_", line: 52, isLocal: true, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 52, file: !1, scope: !32, type: !33, function: void (i8*, i8*)* @__copy_helper_block_, variables: !2)
+!32 = !DIFile(filename: "llvm/tools/clang/test/CodeGenObjC/<unknown>", directory: "llvm/_build.ninja.Debug")
+!33 = !DISubroutineType(types: !34)
 !34 = !{null, !30, !30}
-!35 = !{!"0x2e\00__destroy_helper_block_\00__destroy_helper_block_\00\0052\001\001\000\006\000\000\0052", !1, !32, !28, null, void (i8*)* @__destroy_helper_block_, null, null, !2} ; [ DW_TAG_subprogram ] [line 52] [local] [def] [__destroy_helper_block_]
-!36 = !{!"0x2e\00main\00main\00\0059\000\001\000\006\000\000\0060", !5, !6, !37, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 59] [def] [scope 60] [main]
-!37 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !38, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!35 = !DISubprogram(name: "__destroy_helper_block_", line: 52, isLocal: true, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 52, file: !1, scope: !32, type: !28, function: void (i8*)* @__destroy_helper_block_, variables: !2)
+!36 = !DISubprogram(name: "main", line: 59, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 60, file: !5, scope: !6, type: !37, function: i32 ()* @main, variables: !2)
+!37 = !DISubroutineType(types: !38)
 !38 = !{!11}
-!39 = !{!"0x2e\00run\00run\00\0039\001\001\000\006\00256\000\0040", !5, !6, !40, null, void (void ()*)* @run, null, null, !2} ; [ DW_TAG_subprogram ] [line 39] [local] [def] [scope 40] [run]
-!40 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !41, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!39 = !DISubprogram(name: "run", line: 39, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 40, file: !5, scope: !6, type: !40, function: void (void ()*)* @run, variables: !2)
+!40 = !DISubroutineType(types: !41)
 !41 = !{null, !42}
-!42 = !{!"0xf\00\000\0064\000\000\000", null, null, !43} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from __block_literal_generic]
-!43 = !{!"0x13\00__block_literal_generic\0040\00256\000\000\008\000", !5, !6, null, !44, null, null, null} ; [ DW_TAG_structure_type ] [__block_literal_generic] [line 40, size 256, align 0, offset 0] [def] [from ]
+!42 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, baseType: !43)
+!43 = !DICompositeType(tag: DW_TAG_structure_type, name: "__block_literal_generic", line: 40, size: 256, flags: DIFlagAppleBlock, file: !5, scope: !6, elements: !44)
 !44 = !{!45, !46, !47, !48, !49}
-!45 = !{!"0xd\00__isa\000\0064\0064\000\000", !5, !6, !30} ; [ DW_TAG_member ] [__isa] [line 0, size 64, align 64, offset 0] [from ]
-!46 = !{!"0xd\00__flags\000\0032\0032\0064\000", !5, !6, !11} ; [ DW_TAG_member ] [__flags] [line 0, size 32, align 32, offset 64] [from int]
-!47 = !{!"0xd\00__reserved\000\0032\0032\0096\000", !5, !6, !11} ; [ DW_TAG_member ] [__reserved] [line 0, size 32, align 32, offset 96] [from int]
-!48 = !{!"0xd\00__FuncPtr\000\0064\0064\00128\000", !5, !6, !30} ; [ DW_TAG_member ] [__FuncPtr] [line 0, size 64, align 64, offset 128] [from ]
-!49 = !{!"0xd\00__descriptor\0040\0064\0064\00192\000", !5, !6, !50} ; [ DW_TAG_member ] [__descriptor] [line 40, size 64, align 64, offset 192] [from ]
-!50 = !{!"0xf\00\000\0064\000\000\000", null, null, !51} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from __block_descriptor]
-!51 = !{!"0x13\00__block_descriptor\0040\00128\000\000\008\000", !5, !6, null, !52, null, null, null} ; [ DW_TAG_structure_type ] [__block_descriptor] [line 40, size 128, align 0, offset 0] [def] [from ]
+!45 = !DIDerivedType(tag: DW_TAG_member, name: "__isa", size: 64, align: 64, file: !5, scope: !6, baseType: !30)
+!46 = !DIDerivedType(tag: DW_TAG_member, name: "__flags", size: 32, align: 32, offset: 64, file: !5, scope: !6, baseType: !11)
+!47 = !DIDerivedType(tag: DW_TAG_member, name: "__reserved", size: 32, align: 32, offset: 96, file: !5, scope: !6, baseType: !11)
+!48 = !DIDerivedType(tag: DW_TAG_member, name: "__FuncPtr", size: 64, align: 64, offset: 128, file: !5, scope: !6, baseType: !30)
+!49 = !DIDerivedType(tag: DW_TAG_member, name: "__descriptor", line: 40, size: 64, align: 64, offset: 192, file: !5, scope: !6, baseType: !50)
+!50 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, baseType: !51)
+!51 = !DICompositeType(tag: DW_TAG_structure_type, name: "__block_descriptor", line: 40, size: 128, flags: DIFlagAppleBlock, file: !5, scope: !6, elements: !52)
 !52 = !{!53, !55}
-!53 = !{!"0xd\00reserved\000\0064\0064\000\000", !5, !6, !54} ; [ DW_TAG_member ] [reserved] [line 0, size 64, align 64, offset 0] [from long unsigned int]
-!54 = !{!"0x24\00long unsigned int\000\0064\0064\000\000\007", null, null} ; [ DW_TAG_base_type ] [long unsigned int] [line 0, size 64, align 64, offset 0, enc DW_ATE_unsigned]
-!55 = !{!"0xd\00Size\000\0064\0064\0064\000", !5, !6, !54} ; [ DW_TAG_member ] [Size] [line 0, size 64, align 64, offset 64] [from long unsigned int]
+!53 = !DIDerivedType(tag: DW_TAG_member, name: "reserved", size: 64, align: 64, file: !5, scope: !6, baseType: !54)
+!54 = !DIBasicType(tag: DW_TAG_base_type, name: "long unsigned int", size: 64, align: 64, encoding: DW_ATE_unsigned)
+!55 = !DIDerivedType(tag: DW_TAG_member, name: "Size", size: 64, align: 64, offset: 64, file: !5, scope: !6, baseType: !54)
 !56 = !{i32 1, !"Objective-C Version", i32 2}
 !57 = !{i32 1, !"Objective-C Image Info Version", i32 0}
 !58 = !{i32 1, !"Objective-C Image Info Section", !"__DATA, __objc_imageinfo, regular, no_dead_strip"}
 !59 = !{i32 4, !"Objective-C Garbage Collection", i32 0}
-!60 = !{!"0x101\00self\0016777262\001088", !13, !32, !61} ; [ DW_TAG_arg_variable ] [self] [line 46]
-!61 = !{!"0xf\00\000\0064\0064\000\000", null, null, !4} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from A]
-!62 = !MDLocation(line: 46, scope: !13)
-!63 = !{!"0x101\00_cmd\0033554478\0064", !13, !32, !64} ; [ DW_TAG_arg_variable ] [_cmd] [line 46]
-!64 = !{!"0x16\00SEL\0046\000\000\000\000", !5, null, !25} ; [ DW_TAG_typedef ] [SEL] [line 46, size 0, align 0, offset 0] [from ]
-!65 = !MDLocation(line: 48, scope: !66)
-!66 = !{!"0xb\0047\000\000", !5, !13} ; [ DW_TAG_lexical_block ] [llvm/tools/clang/test/CodeGenObjC/debug-info-blocks.m]
+!60 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "self", line: 46, arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !13, file: !32, type: !61)
+!61 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !4)
+!62 = !DILocation(line: 46, scope: !13)
+!63 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "_cmd", line: 46, arg: 2, flags: DIFlagArtificial, scope: !13, file: !32, type: !64)
+!64 = !DIDerivedType(tag: DW_TAG_typedef, name: "SEL", line: 46, file: !5, baseType: !25)
+!65 = !DILocation(line: 48, scope: !66)
+!66 = distinct !DILexicalBlock(line: 47, column: 0, file: !5, scope: !13)
 !67 = !{}
-!68 = !MDLocation(line: 49, scope: !69)
-!69 = !{!"0xb\0048\000\001", !5, !66} ; [ DW_TAG_lexical_block ] [llvm/tools/clang/test/CodeGenObjC/debug-info-blocks.m]
-!70 = !MDLocation(line: 53, scope: !69)
-!71 = !MDLocation(line: 54, scope: !66)
-!72 = !{!"0x101\00block\0016777255\000", !39, !6, !42} ; [ DW_TAG_arg_variable ] [block] [line 39]
-!73 = !MDLocation(line: 39, scope: !39)
-!74 = !MDLocation(line: 41, scope: !39)
-!75 = !MDLocation(line: 42, scope: !39)
-!76 = !{!"0x101\00.block_descriptor\0016777265\0064", !27, !6, !77} ; [ DW_TAG_arg_variable ] [.block_descriptor] [line 49]
-!77 = !{!"0xf\00\000\0064\000\000\000", null, null, !78} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from __block_literal_1]
-!78 = !{!"0x13\00__block_literal_1\0049\00320\0064\000\000\000", !5, !6, null, !79, null, null, null} ; [ DW_TAG_structure_type ] [__block_literal_1] [line 49, size 320, align 64, offset 0] [def] [from ]
+!68 = !DILocation(line: 49, scope: !69)
+!69 = distinct !DILexicalBlock(line: 48, column: 0, file: !5, scope: !66)
+!70 = !DILocation(line: 53, scope: !69)
+!71 = !DILocation(line: 54, scope: !66)
+!72 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "block", line: 39, arg: 1, scope: !39, file: !6, type: !42)
+!73 = !DILocation(line: 39, scope: !39)
+!74 = !DILocation(line: 41, scope: !39)
+!75 = !DILocation(line: 42, scope: !39)
+!76 = !DILocalVariable(tag: DW_TAG_arg_variable, name: ".block_descriptor", line: 49, arg: 1, flags: DIFlagArtificial, scope: !27, file: !6, type: !77)
+!77 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, baseType: !78)
+!78 = !DICompositeType(tag: DW_TAG_structure_type, name: "__block_literal_1", line: 49, size: 320, align: 64, file: !5, scope: !6, elements: !79)
 !79 = !{!80, !81, !82, !83, !84, !87}
-!80 = !{!"0xd\00__isa\0049\0064\0064\000\000", !5, !6, !30} ; [ DW_TAG_member ] [__isa] [line 49, size 64, align 64, offset 0] [from ]
-!81 = !{!"0xd\00__flags\0049\0032\0032\0064\000", !5, !6, !11} ; [ DW_TAG_member ] [__flags] [line 49, size 32, align 32, offset 64] [from int]
-!82 = !{!"0xd\00__reserved\0049\0032\0032\0096\000", !5, !6, !11} ; [ DW_TAG_member ] [__reserved] [line 49, size 32, align 32, offset 96] [from int]
-!83 = !{!"0xd\00__FuncPtr\0049\0064\0064\00128\000", !5, !6, !30} ; [ DW_TAG_member ] [__FuncPtr] [line 49, size 64, align 64, offset 128] [from ]
-!84 = !{!"0xd\00__descriptor\0049\0064\0064\00192\000", !5, !6, !85} ; [ DW_TAG_member ] [__descriptor] [line 49, size 64, align 64, offset 192] [from ]
-!85 = !{!"0xf\00\000\0064\0064\000\000", null, null, !86} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from __block_descriptor_withcopydispose]
-!86 = !{!"0x13\00__block_descriptor_withcopydispose\0049\000\000\000\004\000", !1, null, null, null, null, null, null} ; [ DW_TAG_structure_type ] [__block_descriptor_withcopydispose] [line 49, size 0, align 0, offset 0] [decl] [from ]
-!87 = !{!"0xd\00self\0049\0064\0064\00256\000", !5, !6, !61} ; [ DW_TAG_member ] [self] [line 49, size 64, align 64, offset 256] [from ]
-!88 = !MDLocation(line: 49, scope: !27)
-!89 = !{!"0x100\00self\0052\000", !27, !32, !23} ; [ DW_TAG_auto_variable ] [self] [line 52]
-!90 = !MDLocation(line: 52, scope: !27)
-!91 = !{!"0x100\00d\0050\000", !92, !6, !93} ; [ DW_TAG_auto_variable ] [d] [line 50]
-!92 = !{!"0xb\0049\000\002", !5, !27} ; [ DW_TAG_lexical_block ] [llvm/tools/clang/test/CodeGenObjC/debug-info-blocks.m]
-!93 = !{!"0xf\00\000\0064\0064\000\000", null, null, !94} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from NSMutableDictionary]
-!94 = !{!"0x13\00NSMutableDictionary\0030\000\008\000\000\0016", !5, !6, null, !95, null, null, null} ; [ DW_TAG_structure_type ] [NSMutableDictionary] [line 30, size 0, align 8, offset 0] [def] [from ]
+!80 = !DIDerivedType(tag: DW_TAG_member, name: "__isa", line: 49, size: 64, align: 64, file: !5, scope: !6, baseType: !30)
+!81 = !DIDerivedType(tag: DW_TAG_member, name: "__flags", line: 49, size: 32, align: 32, offset: 64, file: !5, scope: !6, baseType: !11)
+!82 = !DIDerivedType(tag: DW_TAG_member, name: "__reserved", line: 49, size: 32, align: 32, offset: 96, file: !5, scope: !6, baseType: !11)
+!83 = !DIDerivedType(tag: DW_TAG_member, name: "__FuncPtr", line: 49, size: 64, align: 64, offset: 128, file: !5, scope: !6, baseType: !30)
+!84 = !DIDerivedType(tag: DW_TAG_member, name: "__descriptor", line: 49, size: 64, align: 64, offset: 192, file: !5, scope: !6, baseType: !85)
+!85 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !86)
+!86 = !DICompositeType(tag: DW_TAG_structure_type, name: "__block_descriptor_withcopydispose", line: 49, flags: DIFlagFwdDecl, file: !1)
+!87 = !DIDerivedType(tag: DW_TAG_member, name: "self", line: 49, size: 64, align: 64, offset: 256, file: !5, scope: !6, baseType: !61)
+!88 = !DILocation(line: 49, scope: !27)
+!89 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "self", line: 52, scope: !27, file: !32, type: !23)
+!90 = !DILocation(line: 52, scope: !27)
+!91 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "d", line: 50, scope: !92, file: !6, type: !93)
+!92 = distinct !DILexicalBlock(line: 49, column: 0, file: !5, scope: !27)
+!93 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !94)
+!94 = !DICompositeType(tag: DW_TAG_structure_type, name: "NSMutableDictionary", line: 30, align: 8, runtimeLang: DW_LANG_ObjC, file: !5, scope: !6, elements: !95)
 !95 = !{!96}
-!96 = !{!"0x1c\00\000\000\000\000\000", null, !94, !97} ; [ DW_TAG_inheritance ] [line 0, size 0, align 0, offset 0] [from NSDictionary]
-!97 = !{!"0x13\00NSDictionary\0026\000\008\000\000\0016", !5, !6, null, !98, null, null, null} ; [ DW_TAG_structure_type ] [NSDictionary] [line 26, size 0, align 8, offset 0] [def] [from ]
+!96 = !DIDerivedType(tag: DW_TAG_inheritance, scope: !94, baseType: !97)
+!97 = !DICompositeType(tag: DW_TAG_structure_type, name: "NSDictionary", line: 26, align: 8, runtimeLang: DW_LANG_ObjC, file: !5, scope: !6, elements: !98)
 !98 = !{!99}
-!99 = !{!"0x1c\00\000\000\000\000\000", null, !97, !9} ; [ DW_TAG_inheritance ] [line 0, size 0, align 0, offset 0] [from NSObject]
-!100 = !MDLocation(line: 50, scope: !92)
-!101 = !MDLocation(line: 51, scope: !92)
-!102 = !{!"0x101\00\0016777268\001088", !31, !32, !30} ; [ DW_TAG_arg_variable ] [line 52]
-!103 = !MDLocation(line: 52, scope: !31)
-!104 = !{!"0x101\00\0033554484\0064", !31, !32, !30} ; [ DW_TAG_arg_variable ] [line 52]
-!105 = !{!"0x101\00\0016777268\001088", !35, !32, !30} ; [ DW_TAG_arg_variable ] [line 52]
-!106 = !MDLocation(line: 52, scope: !35)
-!107 = !{!"0x100\00a\0061\000", !36, !6, !61} ; [ DW_TAG_auto_variable ] [a] [line 61]
-!108 = !MDLocation(line: 61, scope: !36)
-!109 = !MDLocation(line: 62, scope: !36)
-!110 = !{i32 1, !"Debug Info Version", i32 2}
-!111 = !{!"0x102\006\0034\0032"} ; [ DW_TAG_expression ] [DW_OP_deref DW_OP_plus 32]
+!99 = !DIDerivedType(tag: DW_TAG_inheritance, scope: !97, baseType: !9)
+!100 = !DILocation(line: 50, scope: !92)
+!101 = !DILocation(line: 51, scope: !92)
+!102 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "", line: 52, arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !31, file: !32, type: !30)
+!103 = !DILocation(line: 52, scope: !31)
+!104 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "", line: 52, arg: 2, flags: DIFlagArtificial, scope: !31, file: !32, type: !30)
+!105 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "", line: 52, arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !35, file: !32, type: !30)
+!106 = !DILocation(line: 52, scope: !35)
+!107 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 61, scope: !36, file: !6, type: !61)
+!108 = !DILocation(line: 61, scope: !36)
+!109 = !DILocation(line: 62, scope: !36)
+!110 = !{i32 1, !"Debug Info Version", i32 3}
+!111 = !DIExpression(DW_OP_deref, DW_OP_plus, 32)
diff --git a/test/DebugInfo/X86/debug-info-static-member.ll b/test/DebugInfo/X86/debug-info-static-member.ll
index 8a14b6ad19c1..1dc85b954876 100644
--- a/test/DebugInfo/X86/debug-info-static-member.ll
+++ b/test/DebugInfo/X86/debug-info-static-member.ll
@@ -47,10 +47,10 @@ entry:
   %retval = alloca i32, align 4
   %instance_C = alloca %class.C, align 4
   store i32 0, i32* %retval
-  call void @llvm.dbg.declare(metadata %class.C* %instance_C, metadata !29, metadata !{!"0x102"}), !dbg !30
-  %d = getelementptr inbounds %class.C* %instance_C, i32 0, i32 0, !dbg !31
+  call void @llvm.dbg.declare(metadata %class.C* %instance_C, metadata !29, metadata !DIExpression()), !dbg !30
+  %d = getelementptr inbounds %class.C, %class.C* %instance_C, i32 0, i32 0, !dbg !31
   store i32 8, i32* %d, align 4, !dbg !31
-  %0 = load i32* @_ZN1C1cE, align 4, !dbg !32
+  %0 = load i32, i32* @_ZN1C1cE, align 4, !dbg !32
   ret i32 %0, !dbg !32
 }
 
@@ -59,39 +59,39 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!34}
 
-!0 = !{!"0x11\004\00clang version 3.3 (trunk 171914)\000\00\000\00\000", !33, !1, !1, !3, !10,  !1} ; [ DW_TAG_compile_unit ] [/home/probinson/projects/upstream/static-member/test/debug-info-static-member.cpp] [DW_LANG_C_plus_plus]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 (trunk 171914)", isOptimized: false, emissionKind: 0, file: !33, enums: !1, retainedTypes: !1, subprograms: !3, globals: !10, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00main\00main\00\0018\000\001\000\006\00256\000\0023", !33, !6, !7, null, i32 ()* @main, null, null, !1} ; [ DW_TAG_subprogram ] [line 18] [def] [scope 23] [main]
-!6 = !{!"0x29", !33} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "main", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 23, file: !33, scope: !6, type: !7, function: i32 ()* @main, variables: !1)
+!6 = !DIFile(filename: "/usr/local/google/home/blaikie/Development/llvm/src/tools/clang/test/CodeGenCXX/debug-info-static-member.cpp", directory: "/home/blaikie/local/Development/llvm/build/clang/x86-64/Debug/llvm")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !10 = !{!12, !27, !28}
-!12 = !{!"0x34\00a\00a\00_ZN1C1aE\0014\000\001", null, !6, !9, i32* @_ZN1C1aE, !15} ; [ DW_TAG_variable ] [a] [line 14] [def]
-!13 = !{!"0x2\00C\001\0032\0032\000\000\000", !33, null, null, !14, null, null, null} ; [ DW_TAG_class_type ] [C] [line 1, size 32, align 32, offset 0] [def] [from ]
+!12 = !DIGlobalVariable(name: "a", linkageName: "_ZN1C1aE", line: 14, isLocal: false, isDefinition: true, scope: null, file: !6, type: !9, variable: i32* @_ZN1C1aE, declaration: !15)
+!13 = !DICompositeType(tag: DW_TAG_class_type, name: "C", line: 1, size: 32, align: 32, file: !33, elements: !14)
 !14 = !{!15, !16, !19, !20, !23, !24, !26}
-!15 = !{!"0xd\00a\003\000\000\000\004097", !33, !13, !9, null} ; [ DW_TAG_member ] [a] [line 3, size 0, align 0, offset 0] [private] [static] [from int]
-!16 = !{!"0xd\00const_a\004\000\000\000\004097", !33, !13, !17, i1 true} ; [ DW_TAG_member ] [const_a] [line 4, size 0, align 0, offset 0] [private] [static] [from ]
-!17 = !{!"0x26\00\000\000\000\000\000", null, null, !18} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from bool]
-!18 = !{!"0x24\00bool\000\008\008\000\000\002", null, null} ; [ DW_TAG_base_type ] [bool] [line 0, size 8, align 8, offset 0, enc DW_ATE_boolean]
-!19 = !{!"0xd\00b\006\000\000\000\004098", !33, !13, !9, null} ; [ DW_TAG_member ] [b] [line 6, size 0, align 0, offset 0] [protected] [static] [from int]
-!20 = !{!"0xd\00const_b\007\000\000\000\004098", !33, !13, !21, float 0x40091EB860000000} ; [ DW_TAG_member ] [const_b] [line 7, size 0, align 0, offset 0] [protected] [static] [from ]
-!21 = !{!"0x26\00\000\000\000\000\000", null, null, !22} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from float]
-!22 = !{!"0x24\00float\000\0032\0032\000\000\004", null, null} ; [ DW_TAG_base_type ] [float] [line 0, size 32, align 32, offset 0, enc DW_ATE_float]
-!23 = !{!"0xd\00c\009\000\000\000\004099", !33, !13, !9, null} ; [ DW_TAG_member ] [c] [line 9, size 0, align 0, offset 0] [static] [from int]
-!24 = !{!"0xd\00const_c\0010\000\000\000\004099", !33, !13, !25, i32 18} ; [ DW_TAG_member ] [const_c] [line 10, size 0, align 0, offset 0] [static] [from ]
-!25 = !{!"0x26\00\000\000\000\000\000", null, null, !9} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from int]
-!26 = !{!"0xd\00d\0011\0032\0032\000\003", !33, !13, !9} ; [ DW_TAG_member ] [d] [line 11, size 32, align 32, offset 0] [from int]
-!27 = !{!"0x34\00b\00b\00_ZN1C1bE\0015\000\001", null, !6, !9, i32* @_ZN1C1bE, !19} ; [ DW_TAG_variable ] [b] [line 15] [def]
-!28 = !{!"0x34\00c\00c\00_ZN1C1cE\0016\000\001", null, !6, !9, i32* @_ZN1C1cE, !23} ; [ DW_TAG_variable ] [c] [line 16] [def]
-!29 = !{!"0x100\00instance_C\0020\000", !5, !6, !13} ; [ DW_TAG_auto_variable ] [instance_C] [line 20]
-!30 = !MDLocation(line: 20, scope: !5)
-!31 = !MDLocation(line: 21, scope: !5)
-!32 = !MDLocation(line: 22, scope: !5)
-!33 = !{!"/usr/local/google/home/blaikie/Development/llvm/src/tools/clang/test/CodeGenCXX/debug-info-static-member.cpp", !"/home/blaikie/local/Development/llvm/build/clang/x86-64/Debug/llvm"}
+!15 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 3, flags: DIFlagPrivate | DIFlagStaticMember, file: !33, scope: !13, baseType: !9)
+!16 = !DIDerivedType(tag: DW_TAG_member, name: "const_a", line: 4, flags: DIFlagPrivate | DIFlagStaticMember, file: !33, scope: !13, baseType: !17, extraData: i1 true)
+!17 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !18)
+!18 = !DIBasicType(tag: DW_TAG_base_type, name: "bool", size: 8, align: 8, encoding: DW_ATE_boolean)
+!19 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 6, flags: DIFlagProtected | DIFlagStaticMember, file: !33, scope: !13, baseType: !9)
+!20 = !DIDerivedType(tag: DW_TAG_member, name: "const_b", line: 7, flags: DIFlagProtected | DIFlagStaticMember, file: !33, scope: !13, baseType: !21, extraData: float 0x40091EB860000000)
+!21 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !22)
+!22 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float)
+!23 = !DIDerivedType(tag: DW_TAG_member, name: "c", line: 9, flags: DIFlagPublic | DIFlagStaticMember, file: !33, scope: !13, baseType: !9)
+!24 = !DIDerivedType(tag: DW_TAG_member, name: "const_c", line: 10, flags: DIFlagPublic | DIFlagStaticMember, file: !33, scope: !13, baseType: !25, extraData: i32 18)
+!25 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !9)
+!26 = !DIDerivedType(tag: DW_TAG_member, name: "d", line: 11, size: 32, align: 32, flags: DIFlagPublic, file: !33, scope: !13, baseType: !9)
+!27 = !DIGlobalVariable(name: "b", linkageName: "_ZN1C1bE", line: 15, isLocal: false, isDefinition: true, scope: null, file: !6, type: !9, variable: i32* @_ZN1C1bE, declaration: !19)
+!28 = !DIGlobalVariable(name: "c", linkageName: "_ZN1C1cE", line: 16, isLocal: false, isDefinition: true, scope: null, file: !6, type: !9, variable: i32* @_ZN1C1cE, declaration: !23)
+!29 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "instance_C", line: 20, scope: !5, file: !6, type: !13)
+!30 = !DILocation(line: 20, scope: !5)
+!31 = !DILocation(line: 21, scope: !5)
+!32 = !DILocation(line: 22, scope: !5)
+!33 = !DIFile(filename: "/usr/local/google/home/blaikie/Development/llvm/src/tools/clang/test/CodeGenCXX/debug-info-static-member.cpp", directory: "/home/blaikie/local/Development/llvm/build/clang/x86-64/Debug/llvm")
 ; PRESENT verifies that static member declarations have these attributes:
-; external, declaration, accessibility, and either DW_AT_MIPS_linkage_name
+; external, declaration, accessibility, and either DW_AT_linkage_name
 ; (for variables) or DW_AT_const_value (for constants).
 ;
 ; PRESENT:      .debug_info contents:
@@ -253,4 +253,4 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 ; DARWINA-NOT:  DW_AT_const_value
 ; DARWINA-NOT:  DW_AT_location
 ; DARWINA:      NULL
-!34 = !{i32 1, !"Debug Info Version", i32 2}
+!34 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/debug-loc-asan.ll b/test/DebugInfo/X86/debug-loc-asan.ll
index 13e193bdf116..68bef4904800 100644
--- a/test/DebugInfo/X86/debug-loc-asan.ll
+++ b/test/DebugInfo/X86/debug-loc-asan.ll
@@ -46,7 +46,7 @@ define i32 @_Z3bari(i32 %y) #0 {
 entry:
   %MyAlloca = alloca [64 x i8], align 32
   %0 = ptrtoint [64 x i8]* %MyAlloca to i64
-  %1 = load i32* @__asan_option_detect_stack_use_after_return
+  %1 = load i32, i32* @__asan_option_detect_stack_use_after_return
   %2 = icmp ne i32 %1, 0
   br i1 %2, label %3, label %5
 
@@ -75,9 +75,9 @@ entry:
   %19 = lshr i64 %18, 3
   %20 = add i64 %19, 2147450880
   %21 = inttoptr i64 %20 to i8*
-  %22 = load i8* %21
+  %22 = load i8, i8* %21
   %23 = icmp ne i8 %22, 0
-  call void @llvm.dbg.declare(metadata i32* %8, metadata !12, metadata !14)
+  call void @llvm.dbg.declare(metadata i32* %8, metadata !12, metadata !14), !dbg !DILocation(scope: !4)
   br i1 %23, label %24, label %30
 
 ; <label>:24                                      ; preds = %5
@@ -98,7 +98,7 @@ entry:
   %32 = lshr i64 %31, 3, !dbg !13
   %33 = add i64 %32, 2147450880, !dbg !13
   %34 = inttoptr i64 %33 to i8*, !dbg !13
-  %35 = load i8* %34, !dbg !13
+  %35 = load i8, i8* %34, !dbg !13
   %36 = icmp ne i8 %35, 0, !dbg !13
   br i1 %36, label %37, label %43, !dbg !13
 
@@ -115,7 +115,7 @@ entry:
   unreachable
 
 ; <label>:43                                      ; preds = %37, %30
-  %44 = load i32* %8, align 4, !dbg !13
+  %44 = load i32, i32* %8, align 4, !dbg !13
   %add = add nsw i32 %44, 2, !dbg !13
   store i64 1172321806, i64* %9, !dbg !13
   %45 = icmp ne i64 %6, %0, !dbg !13
@@ -127,7 +127,7 @@ entry:
   store i64 -723401728380766731, i64* %48, !dbg !13
   %49 = add i64 %6, 56, !dbg !13
   %50 = inttoptr i64 %49 to i64*, !dbg !13
-  %51 = load i64* %50, !dbg !13
+  %51 = load i64, i64* %50, !dbg !13
   %52 = inttoptr i64 %51 to i8*, !dbg !13
   store i8 0, i8* %52, !dbg !13
   br label %56, !dbg !13
@@ -165,18 +165,18 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!9, !10}
 !llvm.ident = !{!11}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 (209308)\000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/llvm_cmake_gcc/test.cc] [DW_LANG_C_plus_plus]
-!1 = !{!"test.cc", !"/llvm_cmake_gcc"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 (209308)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.cc", directory: "/llvm_cmake_gcc")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00bar\00bar\00_Z3bari\001\000\001\000\006\00256\000\001", !1, !5, !6, null, i32 (i32)* @_Z3bari, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [bar]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/llvm_cmake_gcc/test.cc]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "bar", linkageName: "_Z3bari", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 (i32)* @_Z3bari, variables: !2)
+!5 = !DIFile(filename: "test.cc", directory: "/llvm_cmake_gcc")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 4}
-!10 = !{i32 2, !"Debug Info Version", i32 2}
+!10 = !{i32 2, !"Debug Info Version", i32 3}
 !11 = !{!"clang version 3.5.0 (209308)"}
-!12 = !{!"0x101\00y\0016777217\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [y] [line 1]
-!13 = !MDLocation(line: 2, scope: !4)
-!14 = !{!"0x102\006"} ; [ DW_TAG_expression ] [DW_OP_deref]
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "y", line: 1, arg: 1, scope: !4, file: !5, type: !8)
+!13 = !DILocation(line: 2, scope: !4)
+!14 = !DIExpression(DW_OP_deref)
diff --git a/test/DebugInfo/X86/debug-loc-offset.ll b/test/DebugInfo/X86/debug-loc-offset.ll
index 9022891e06f3..cf2fcc8e2229 100644
--- a/test/DebugInfo/X86/debug-loc-offset.ll
+++ b/test/DebugInfo/X86/debug-loc-offset.ll
@@ -41,7 +41,7 @@
 
 ; CHECK: DW_TAG_subprogram
 ; CHECK-NOT: DW_TAG
-; CHECK: DW_AT_MIPS_linkage_name [DW_FORM_strp]{{.*}}"_Z3baz1A"
+; CHECK: DW_AT_linkage_name [DW_FORM_strp]{{.*}}"_Z3baz1A"
 ; CHECK-NOT: {{DW_TAG|NULL}}
 ; CHECK: DW_TAG_formal_parameter
 ; CHECK-NOT: DW_TAG
@@ -55,7 +55,7 @@
 
 ; CHECK: .debug_loc contents:
 ; CHECK: 0x00000000: Beginning address offset: 0x0000000000000000
-; CHECK:                Ending address offset: 0x000000000000001a
+; CHECK:                Ending address offset: 0x0000000000000017
 
 %struct.A = type { i32 (...)**, i32 }
 
@@ -64,8 +64,8 @@ define i32 @_Z3bari(i32 %b) #0 {
 entry:
   %b.addr = alloca i32, align 4
   store i32 %b, i32* %b.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %b.addr, metadata !21, metadata !{!"0x102"}), !dbg !22
-  %0 = load i32* %b.addr, align 4, !dbg !23
+  call void @llvm.dbg.declare(metadata i32* %b.addr, metadata !21, metadata !DIExpression()), !dbg !22
+  %0 = load i32, i32* %b.addr, align 4, !dbg !23
   %add = add nsw i32 %0, 4, !dbg !23
   ret i32 %add, !dbg !23
 }
@@ -76,16 +76,16 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
 define void @_Z3baz1A(%struct.A* %a) #2 {
 entry:
   %z = alloca i32, align 4
-  call void @llvm.dbg.declare(metadata %struct.A* %a, metadata !24, metadata !{!"0x102"}), !dbg !25
-  call void @llvm.dbg.declare(metadata i32* %z, metadata !26, metadata !{!"0x102"}), !dbg !27
+  call void @llvm.dbg.declare(metadata %struct.A* %a, metadata !24, metadata !DIExpression(DW_OP_deref)), !dbg !25
+  call void @llvm.dbg.declare(metadata i32* %z, metadata !26, metadata !DIExpression()), !dbg !27
   store i32 2, i32* %z, align 4, !dbg !27
-  %var = getelementptr inbounds %struct.A* %a, i32 0, i32 1, !dbg !28
-  %0 = load i32* %var, align 4, !dbg !28
+  %var = getelementptr inbounds %struct.A, %struct.A* %a, i32 0, i32 1, !dbg !28
+  %0 = load i32, i32* %var, align 4, !dbg !28
   %cmp = icmp sgt i32 %0, 2, !dbg !28
   br i1 %cmp, label %if.then, label %if.end, !dbg !28
 
 if.then:                                          ; preds = %entry
-  %1 = load i32* %z, align 4, !dbg !30
+  %1 = load i32, i32* %z, align 4, !dbg !30
   %inc = add nsw i32 %1, 1, !dbg !30
   store i32 %inc, i32* %z, align 4, !dbg !30
   br label %if.end, !dbg !30
@@ -97,7 +97,7 @@ if.end:                                           ; preds = %if.then, %entry
   br i1 %cmp1, label %if.then2, label %if.end4, !dbg !31
 
 if.then2:                                         ; preds = %if.end
-  %2 = load i32* %z, align 4, !dbg !33
+  %2 = load i32, i32* %z, align 4, !dbg !33
   %inc3 = add nsw i32 %2, 1, !dbg !33
   store i32 %inc3, i32* %z, align 4, !dbg !33
   br label %if.end4, !dbg !33
@@ -116,38 +116,38 @@ attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n
 !llvm.module.flags = !{!18, !19}
 !llvm.ident = !{!20, !20}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 (210479)\000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/llvm_cmake_gcc/debug-loc-offset1.cc] [DW_LANG_C_plus_plus]
-!1 = !{!"debug-loc-offset1.cc", !"/llvm_cmake_gcc"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 (210479)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "debug-loc-offset1.cc", directory: "/llvm_cmake_gcc")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00bar\00bar\00_Z3bari\001\000\001\000\006\00256\000\001", !1, !5, !6, null, i32 (i32)* @_Z3bari, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [bar]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/llvm_cmake_gcc/debug-loc-offset1.cc]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "bar", linkageName: "_Z3bari", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 (i32)* @_Z3bari, variables: !2)
+!5 = !DIFile(filename: "debug-loc-offset1.cc", directory: "/llvm_cmake_gcc")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x11\004\00clang version 3.5.0 (210479)\000\00\000\00\001", !10, !2, !11, !13, !2, !2} ; [ DW_TAG_compile_unit ] [/llvm_cmake_gcc/debug-loc-offset2.cc] [DW_LANG_C_plus_plus]
-!10 = !{!"debug-loc-offset2.cc", !"/llvm_cmake_gcc"}
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 (210479)", isOptimized: false, emissionKind: 1, file: !10, enums: !2, retainedTypes: !11, subprograms: !13, globals: !2, imports: !2)
+!10 = !DIFile(filename: "debug-loc-offset2.cc", directory: "/llvm_cmake_gcc")
 !11 = !{!12}
-!12 = !{!"0x13\00A\001\000\000\000\004\000", !10, null, null, null, null, null, !"_ZTS1A"} ; [ DW_TAG_structure_type ] [A] [line 1, size 0, align 0, offset 0] [decl] [from ]
+!12 = !DICompositeType(tag: DW_TAG_structure_type, name: "A", line: 1, flags: DIFlagFwdDecl, file: !10, identifier: "_ZTS1A")
 !13 = !{!14}
-!14 = !{!"0x2e\00baz\00baz\00_Z3baz1A\006\000\001\000\006\00256\000\006", !10, !15, !16, null, void (%struct.A*)* @_Z3baz1A, null, null, !2} ; [ DW_TAG_subprogram ] [line 6] [def] [baz]
-!15 = !{!"0x29", !10}        ; [ DW_TAG_file_type ] [/llvm_cmake_gcc/debug-loc-offset2.cc]
-!16 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !17, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!14 = !DISubprogram(name: "baz", linkageName: "_Z3baz1A", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 6, file: !10, scope: !15, type: !16, function: void (%struct.A*)* @_Z3baz1A, variables: !2)
+!15 = !DIFile(filename: "debug-loc-offset2.cc", directory: "/llvm_cmake_gcc")
+!16 = !DISubroutineType(types: !17)
 !17 = !{null, !12}
 !18 = !{i32 2, !"Dwarf Version", i32 4}
-!19 = !{i32 2, !"Debug Info Version", i32 2}
+!19 = !{i32 2, !"Debug Info Version", i32 3}
 !20 = !{!"clang version 3.5.0 (210479)"}
-!21 = !{!"0x101\00b\0016777217\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [b] [line 1]
-!22 = !MDLocation(line: 1, scope: !4)
-!23 = !MDLocation(line: 2, scope: !4)
-!24 = !{!"0x101\00a\0016777222\008192", !14, !15, !"_ZTS1A"} ; [ DW_TAG_arg_variable ] [a] [line 6]
-!25 = !MDLocation(line: 6, scope: !14)
-!26 = !{!"0x100\00z\007\000", !14, !15, !8} ; [ DW_TAG_auto_variable ] [z] [line 7]
-!27 = !MDLocation(line: 7, scope: !14)
-!28 = !MDLocation(line: 8, scope: !29)
-!29 = !{!"0xb\008\000\000", !10, !14} ; [ DW_TAG_lexical_block ] [/llvm_cmake_gcc/debug-loc-offset2.cc]
-!30 = !MDLocation(line: 9, scope: !29)
-!31 = !MDLocation(line: 10, scope: !32)
-!32 = !{!"0xb\0010\000\000", !10, !14} ; [ DW_TAG_lexical_block ] [/llvm_cmake_gcc/debug-loc-offset2.cc]
-!33 = !MDLocation(line: 11, scope: !32)
-!34 = !MDLocation(line: 12, scope: !14)
+!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 1, arg: 1, scope: !4, file: !5, type: !8)
+!22 = !DILocation(line: 1, scope: !4)
+!23 = !DILocation(line: 2, scope: !4)
+!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 6, arg: 1, scope: !14, file: !15, type: !"_ZTS1A")
+!25 = !DILocation(line: 6, scope: !14)
+!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "z", line: 7, scope: !14, file: !15, type: !8)
+!27 = !DILocation(line: 7, scope: !14)
+!28 = !DILocation(line: 8, scope: !29)
+!29 = distinct !DILexicalBlock(line: 8, column: 0, file: !10, scope: !14)
+!30 = !DILocation(line: 9, scope: !29)
+!31 = !DILocation(line: 10, scope: !32)
+!32 = distinct !DILexicalBlock(line: 10, column: 0, file: !10, scope: !14)
+!33 = !DILocation(line: 11, scope: !32)
+!34 = !DILocation(line: 12, scope: !14)
diff --git a/test/DebugInfo/X86/debug-ranges-offset.ll b/test/DebugInfo/X86/debug-ranges-offset.ll
index fd8fe0e11f35..19c3bcf37483 100644
--- a/test/DebugInfo/X86/debug-ranges-offset.ll
+++ b/test/DebugInfo/X86/debug-ranges-offset.ll
@@ -26,18 +26,18 @@ entry:
   %1 = and i64 %0, -70368744177672, !dbg !19
   %2 = inttoptr i64 %1 to i64*, !dbg !19
   store i64 -1, i64* %2, align 8, !dbg !19
-  store i64 0, i64* getelementptr inbounds ([1000 x i64]* @__msan_param_tls, i64 0, i64 0), align 8, !dbg !19
-  store i64 0, i64* getelementptr inbounds ([8 x i64]* @__msan_retval_tls, i64 0, i64 0), align 8, !dbg !19
+  store i64 0, i64* getelementptr inbounds ([1000 x i64], [1000 x i64]* @__msan_param_tls, i64 0, i64 0), align 8, !dbg !19
+  store i64 0, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @__msan_retval_tls, i64 0, i64 0), align 8, !dbg !19
   %call = call i8* @_Znwm(i64 4) #4, !dbg !19
-  %_msret = load i64* getelementptr inbounds ([8 x i64]* @__msan_retval_tls, i64 0, i64 0), align 8, !dbg !19
+  %_msret = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @__msan_retval_tls, i64 0, i64 0), align 8, !dbg !19
   %3 = bitcast i8* %call to i32*, !dbg !19
-  tail call void @llvm.dbg.value(metadata i32* %3, i64 0, metadata !9, metadata !{!"0x102"}), !dbg !19
+  tail call void @llvm.dbg.value(metadata i32* %3, i64 0, metadata !9, metadata !DIExpression()), !dbg !19
   %4 = inttoptr i64 %1 to i64*, !dbg !19
   store i64 %_msret, i64* %4, align 8, !dbg !19
   store volatile i32* %3, i32** %p, align 8, !dbg !19
-  tail call void @llvm.dbg.value(metadata i32** %p, i64 0, metadata !9, metadata !{!"0x102"}), !dbg !19
-  %p.0.p.0. = load volatile i32** %p, align 8, !dbg !20
-  %_msld = load i64* %4, align 8, !dbg !20
+  tail call void @llvm.dbg.value(metadata i32** %p, i64 0, metadata !9, metadata !DIExpression()), !dbg !19
+  %p.0.p.0. = load volatile i32*, i32** %p, align 8, !dbg !20
+  %_msld = load i64, i64* %4, align 8, !dbg !20
   %_mscmp = icmp eq i64 %_msld, 0, !dbg !20
   br i1 %_mscmp, label %6, label %5, !dbg !20, !prof !22
 
@@ -47,11 +47,11 @@ entry:
   unreachable, !dbg !20
 
 ; <label>:6                                       ; preds = %entry
-  %7 = load i32* %p.0.p.0., align 4, !dbg !20, !tbaa !23
+  %7 = load i32, i32* %p.0.p.0., align 4, !dbg !20, !tbaa !23
   %8 = ptrtoint i32* %p.0.p.0. to i64, !dbg !20
   %9 = and i64 %8, -70368744177665, !dbg !20
   %10 = inttoptr i64 %9 to i32*, !dbg !20
-  %_msld2 = load i32* %10, align 4, !dbg !20
+  %_msld2 = load i32, i32* %10, align 4, !dbg !20
   %11 = icmp ne i32 %_msld2, 0, !dbg !20
   %12 = xor i32 %_msld2, -1, !dbg !20
   %13 = and i32 %7, %12, !dbg !20
@@ -69,9 +69,9 @@ entry:
   br i1 %tobool, label %if.end, label %if.then, !dbg !20
 
 if.then:                                          ; preds = %16
-  store i64 0, i64* getelementptr inbounds ([1000 x i64]* @__msan_param_tls, i64 0, i64 0), align 8, !dbg !28
+  store i64 0, i64* getelementptr inbounds ([1000 x i64], [1000 x i64]* @__msan_param_tls, i64 0, i64 0), align 8, !dbg !28
   store i32 0, i32* bitcast ([8 x i64]* @__msan_retval_tls to i32*), align 8, !dbg !28
-  %puts = call i32 @puts(i8* getelementptr inbounds ([4 x i8]* @str, i64 0, i64 0)), !dbg !28
+  %puts = call i32 @puts(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @str, i64 0, i64 0)), !dbg !28
   br label %if.end, !dbg !28
 
 if.end:                                           ; preds = %16, %if.then
@@ -91,18 +91,18 @@ entry:
   store i64 -1, i64* %2, align 8, !dbg !30
   %p.i.0..sroa_cast = bitcast i32** %p.i to i8*, !dbg !30
   call void @llvm.lifetime.start(i64 8, i8* %p.i.0..sroa_cast), !dbg !30
-  store i64 0, i64* getelementptr inbounds ([1000 x i64]* @__msan_param_tls, i64 0, i64 0), align 8, !dbg !30
-  store i64 0, i64* getelementptr inbounds ([8 x i64]* @__msan_retval_tls, i64 0, i64 0), align 8, !dbg !30
+  store i64 0, i64* getelementptr inbounds ([1000 x i64], [1000 x i64]* @__msan_param_tls, i64 0, i64 0), align 8, !dbg !30
+  store i64 0, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @__msan_retval_tls, i64 0, i64 0), align 8, !dbg !30
   %call.i = call i8* @_Znwm(i64 4) #4, !dbg !30
-  %_msret = load i64* getelementptr inbounds ([8 x i64]* @__msan_retval_tls, i64 0, i64 0), align 8, !dbg !30
+  %_msret = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @__msan_retval_tls, i64 0, i64 0), align 8, !dbg !30
   %3 = bitcast i8* %call.i to i32*, !dbg !30
-  tail call void @llvm.dbg.value(metadata i32* %3, i64 0, metadata !32, metadata !{!"0x102"}), !dbg !30
+  tail call void @llvm.dbg.value(metadata i32* %3, i64 0, metadata !32, metadata !DIExpression()), !dbg !30
   %4 = inttoptr i64 %1 to i64*, !dbg !30
   store i64 %_msret, i64* %4, align 8, !dbg !30
   store volatile i32* %3, i32** %p.i, align 8, !dbg !30
-  tail call void @llvm.dbg.value(metadata i32** %p.i, i64 0, metadata !32, metadata !{!"0x102"}), !dbg !30
-  %p.i.0.p.0.p.0..i = load volatile i32** %p.i, align 8, !dbg !33
-  %_msld = load i64* %4, align 8, !dbg !33
+  tail call void @llvm.dbg.value(metadata i32** %p.i, i64 0, metadata !32, metadata !DIExpression()), !dbg !30
+  %p.i.0.p.0.p.0..i = load volatile i32*, i32** %p.i, align 8, !dbg !33
+  %_msld = load i64, i64* %4, align 8, !dbg !33
   %_mscmp = icmp eq i64 %_msld, 0, !dbg !33
   br i1 %_mscmp, label %6, label %5, !dbg !33, !prof !22
 
@@ -112,11 +112,11 @@ entry:
   unreachable, !dbg !33
 
 ; <label>:6                                       ; preds = %entry
-  %7 = load i32* %p.i.0.p.0.p.0..i, align 4, !dbg !33, !tbaa !23
+  %7 = load i32, i32* %p.i.0.p.0.p.0..i, align 4, !dbg !33, !tbaa !23
   %8 = ptrtoint i32* %p.i.0.p.0.p.0..i to i64, !dbg !33
   %9 = and i64 %8, -70368744177665, !dbg !33
   %10 = inttoptr i64 %9 to i32*, !dbg !33
-  %_msld2 = load i32* %10, align 4, !dbg !33
+  %_msld2 = load i32, i32* %10, align 4, !dbg !33
   %11 = icmp ne i32 %_msld2, 0, !dbg !33
   %12 = xor i32 %_msld2, -1, !dbg !33
   %13 = and i32 %7, %12, !dbg !33
@@ -134,9 +134,9 @@ entry:
   br i1 %tobool.i, label %_Z1fv.exit, label %if.then.i, !dbg !33
 
 if.then.i:                                        ; preds = %16
-  store i64 0, i64* getelementptr inbounds ([1000 x i64]* @__msan_param_tls, i64 0, i64 0), align 8, !dbg !34
+  store i64 0, i64* getelementptr inbounds ([1000 x i64], [1000 x i64]* @__msan_param_tls, i64 0, i64 0), align 8, !dbg !34
   store i32 0, i32* bitcast ([8 x i64]* @__msan_retval_tls to i32*), align 8, !dbg !34
-  %puts.i = call i32 @puts(i8* getelementptr inbounds ([4 x i8]* @str, i64 0, i64 0)), !dbg !34
+  %puts.i = call i32 @puts(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @str, i64 0, i64 0)), !dbg !34
   br label %_Z1fv.exit, !dbg !34
 
 _Z1fv.exit:                                       ; preds = %16, %if.then.i
@@ -202,40 +202,40 @@ attributes #4 = { builtin }
 !llvm.module.flags = !{!16, !17}
 !llvm.ident = !{!18}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 (trunk 207243) (llvm/trunk 207259)\001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/foo.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"foo.cpp", !"/usr/local/google/home/echristo/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 (trunk 207243) (llvm/trunk 207259)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "foo.cpp", directory: "/usr/local/google/home/echristo/tmp")
 !2 = !{}
 !3 = !{!4, !13}
-!4 = !{!"0x2e\00f\00f\00_Z1fv\003\000\001\000\006\00256\001\003", !1, !5, !6, null, void ()* @_Z1fv, null, null, !8} ; [ DW_TAG_subprogram ] [line 3] [def] [f]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/usr/local/google/home/echristo/tmp/foo.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "f", linkageName: "_Z1fv", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !1, scope: !5, type: !6, function: void ()* @_Z1fv, variables: !8)
+!5 = !DIFile(filename: "foo.cpp", directory: "/usr/local/google/home/echristo/tmp")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
 !8 = !{!9}
-!9 = !{!"0x100\00p\004\000", !4, !5, !10} ; [ DW_TAG_auto_variable ] [p] [line 4]
-!10 = !{!"0x35\00\000\000\000\000\000", null, null, !11} ; [ DW_TAG_volatile_type ] [line 0, size 0, align 0, offset 0] [from ]
-!11 = !{!"0xf\00\000\0064\0064\000\000", null, null, !12} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
-!12 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!13 = !{!"0x2e\00main\00main\00\009\000\001\000\006\00256\001\009", !1, !5, !14, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 9] [def] [main]
-!14 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !15, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!9 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "p", line: 4, scope: !4, file: !5, type: !10)
+!10 = !DIDerivedType(tag: DW_TAG_volatile_type, baseType: !11)
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !12)
+!12 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!13 = !DISubprogram(name: "main", line: 9, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 9, file: !1, scope: !5, type: !14, function: i32 ()* @main, variables: !2)
+!14 = !DISubroutineType(types: !15)
 !15 = !{!12}
 !16 = !{i32 2, !"Dwarf Version", i32 4}
-!17 = !{i32 1, !"Debug Info Version", i32 2}
+!17 = !{i32 1, !"Debug Info Version", i32 3}
 !18 = !{!"clang version 3.5.0 (trunk 207243) (llvm/trunk 207259)"}
-!19 = !MDLocation(line: 4, scope: !4)
-!20 = !MDLocation(line: 5, scope: !21)
-!21 = !{!"0xb\005\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/foo.cpp]
+!19 = !DILocation(line: 4, scope: !4)
+!20 = !DILocation(line: 5, scope: !21)
+!21 = distinct !DILexicalBlock(line: 5, column: 0, file: !1, scope: !4)
 !22 = !{!"branch_weights", i32 1000, i32 1}
 !23 = !{!24, !24, i64 0}
 !24 = !{!"int", !25, i64 0}
 !25 = !{!"omnipotent char", !26, i64 0}
 !26 = !{!"Simple C/C++ TBAA"}
 !27 = !{!"branch_weights", i32 1, i32 1000}
-!28 = !MDLocation(line: 6, scope: !21)
-!29 = !MDLocation(line: 7, scope: !4)
-!30 = !MDLocation(line: 4, scope: !4, inlinedAt: !31)
-!31 = !MDLocation(line: 10, scope: !13)
-!32 = !{!"0x100\00p\004\000", !4, !5, !10, !31} ; [ DW_TAG_auto_variable ] [p] [line 4]
-!33 = !MDLocation(line: 5, scope: !21, inlinedAt: !31)
-!34 = !MDLocation(line: 6, scope: !21, inlinedAt: !31)
-!35 = !MDLocation(line: 7, scope: !4, inlinedAt: !31)
-!36 = !MDLocation(line: 11, scope: !13)
+!28 = !DILocation(line: 6, scope: !21)
+!29 = !DILocation(line: 7, scope: !4)
+!30 = !DILocation(line: 4, scope: !4, inlinedAt: !31)
+!31 = !DILocation(line: 10, scope: !13)
+!32 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "p", line: 4, scope: !4, file: !5, type: !10)
+!33 = !DILocation(line: 5, scope: !21, inlinedAt: !31)
+!34 = !DILocation(line: 6, scope: !21, inlinedAt: !31)
+!35 = !DILocation(line: 7, scope: !4, inlinedAt: !31)
+!36 = !DILocation(line: 11, scope: !13)
diff --git a/test/DebugInfo/X86/debug_frame.ll b/test/DebugInfo/X86/debug_frame.ll
index 56122e3c5306..48ce554f0119 100644
--- a/test/DebugInfo/X86/debug_frame.ll
+++ b/test/DebugInfo/X86/debug_frame.ll
@@ -13,10 +13,10 @@ entry:
 !llvm.module.flags = !{!7}
 !5 = !{!0}
 
-!0 = !{!"0x2e\00f\00f\00\001\000\001\000\006\00256\001\001", !6, !1, !3, null, void ()* @f, null, null, null} ; [ DW_TAG_subprogram ] [line 1] [def] [f]
-!1 = !{!"0x29", !6} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 3.0 ()\001\00\000\00\000", !6, !4, !4, !5, null, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !6, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "f", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !6, scope: !1, type: !3, function: void ()* @f)
+!1 = !DIFile(filename: "/home/espindola/llvm/test.c", directory: "/home/espindola/llvm/build")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 ()", isOptimized: true, emissionKind: 0, file: !6, enums: !{}, retainedTypes: !{}, subprograms: !5)
+!3 = !DISubroutineType(types: !4)
 !4 = !{null}
-!6 = !{!"/home/espindola/llvm/test.c", !"/home/espindola/llvm/build"}
-!7 = !{i32 1, !"Debug Info Version", i32 2}
+!6 = !DIFile(filename: "/home/espindola/llvm/test.c", directory: "/home/espindola/llvm/build")
+!7 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/decl-derived-member.ll b/test/DebugInfo/X86/decl-derived-member.ll
index c4f3dd90ffd5..3b833580e9ca 100644
--- a/test/DebugInfo/X86/decl-derived-member.ll
+++ b/test/DebugInfo/X86/decl-derived-member.ll
@@ -46,8 +46,8 @@ entry:
   %this.addr = alloca %struct.foo*, align 8
   store %struct.foo* %this, %struct.foo** %this.addr, align 8
   call void @llvm.dbg.declare(metadata %struct.foo** %this.addr, metadata !34, metadata !36), !dbg !37
-  %this1 = load %struct.foo** %this.addr
-  %b = getelementptr inbounds %struct.foo* %this1, i32 0, i32 0, !dbg !38
+  %this1 = load %struct.foo*, %struct.foo** %this.addr
+  %b = getelementptr inbounds %struct.foo, %struct.foo* %this1, i32 0, i32 0, !dbg !38
   call void @_ZN4baseC2Ev(%struct.base* %b) #2, !dbg !38
   ret void, !dbg !38
 }
@@ -58,8 +58,8 @@ entry:
   %this.addr = alloca %struct.foo*, align 8
   store %struct.foo* %this, %struct.foo** %this.addr, align 8
   call void @llvm.dbg.declare(metadata %struct.foo** %this.addr, metadata !39, metadata !36), !dbg !40
-  %this1 = load %struct.foo** %this.addr
-  %b = getelementptr inbounds %struct.foo* %this1, i32 0, i32 0, !dbg !41
+  %this1 = load %struct.foo*, %struct.foo** %this.addr
+  %b = getelementptr inbounds %struct.foo, %struct.foo* %this1, i32 0, i32 0, !dbg !41
   call void @_ZN4baseD1Ev(%struct.base* %b), !dbg !41
   ret void, !dbg !43
 }
@@ -76,9 +76,9 @@ entry:
   %this.addr = alloca %struct.base*, align 8
   store %struct.base* %this, %struct.base** %this.addr, align 8
   call void @llvm.dbg.declare(metadata %struct.base** %this.addr, metadata !44, metadata !36), !dbg !46
-  %this1 = load %struct.base** %this.addr
+  %this1 = load %struct.base*, %struct.base** %this.addr
   %0 = bitcast %struct.base* %this1 to i32 (...)***, !dbg !47
-  store i32 (...)** bitcast (i8** getelementptr inbounds ([4 x i8*]* @_ZTV4base, i64 0, i64 2) to i32 (...)**), i32 (...)*** %0, !dbg !47
+  store i32 (...)** bitcast (i8** getelementptr inbounds ([4 x i8*], [4 x i8*]* @_ZTV4base, i64 0, i64 2) to i32 (...)**), i32 (...)*** %0, !dbg !47
   ret void, !dbg !47
 }
 
@@ -100,52 +100,52 @@ attributes #4 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n
 !llvm.module.flags = !{!30, !31}
 !llvm.ident = !{!32}
 
-!0 = !{!"0x11\004\00clang version 3.7.0 (trunk 227104) (llvm/trunk 227103)\000\00\000\00\001", !1, !2, !3, !9, !28, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/decl-derived-member.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"decl-derived-member.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.7.0 (trunk 227104) (llvm/trunk 227103)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !9, globals: !28, imports: !2)
+!1 = !DIFile(filename: "decl-derived-member.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4, !8}
-!4 = !{!"0x13\00foo\005\0064\0064\000\000\000", !1, null, null, !5, null, null, !"_ZTS3foo"} ; [ DW_TAG_structure_type ] [foo] [line 5, size 64, align 64, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo", line: 5, size: 64, align: 64, file: !1, elements: !5, identifier: "_ZTS3foo")
 !5 = !{!6}
-!6 = !{!"0xd\00b\006\0064\0064\000\000", !1, !"_ZTS3foo", !7} ; [ DW_TAG_member ] [b] [line 6, size 64, align 64, offset 0] [from base_type]
-!7 = !{!"0x16\00base_type\004\000\000\000\000", !1, null, !"_ZTS4base"} ; [ DW_TAG_typedef ] [base_type] [line 4, size 0, align 0, offset 0] [from _ZTS4base]
-!8 = !{!"0x13\00base\001\000\000\000\004\000", !1, null, null, null, null, null, !"_ZTS4base"} ; [ DW_TAG_structure_type ] [base] [line 1, size 0, align 0, offset 0] [decl] [from ]
+!6 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 6, size: 64, align: 64, file: !1, scope: !"_ZTS3foo", baseType: !7)
+!7 = !DIDerivedType(tag: DW_TAG_typedef, name: "base_type", line: 4, file: !1, baseType: !"_ZTS4base")
+!8 = !DICompositeType(tag: DW_TAG_structure_type, name: "base", line: 1, flags: DIFlagFwdDecl, file: !1, identifier: "_ZTS4base")
 !9 = !{!10, !14, !19, !24, !26}
-!10 = !{!"0x2e\00__cxx_global_var_init\00__cxx_global_var_init\00\008\001\001\000\000\00256\000\008", !1, !11, !12, null, void ()* @__cxx_global_var_init, null, null, !2} ; [ DW_TAG_subprogram ] [line 8] [local] [def] [__cxx_global_var_init]
-!11 = !{!"0x29", !1}                              ; [ DW_TAG_file_type ] [/tmp/dbginfo/decl-derived-member.cpp]
-!12 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !13, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!10 = !DISubprogram(name: "__cxx_global_var_init", line: 8, isLocal: true, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 8, file: !1, scope: !11, type: !12, function: void ()* @__cxx_global_var_init, variables: !2)
+!11 = !DIFile(filename: "decl-derived-member.cpp", directory: "/tmp/dbginfo")
+!12 = !DISubroutineType(types: !13)
 !13 = !{null}
-!14 = !{!"0x2e\00foo\00foo\00_ZN3fooC2Ev\005\000\001\000\000\00320\000\005", !1, !"_ZTS3foo", !15, null, void (%struct.foo*)* @_ZN3fooC2Ev, null, !18, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [foo]
-!15 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!14 = !DISubprogram(name: "foo", linkageName: "_ZN3fooC2Ev", line: 5, isLocal: false, isDefinition: true, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !"_ZTS3foo", type: !15, function: void (%struct.foo*)* @_ZN3fooC2Ev, declaration: !18, variables: !2)
+!15 = !DISubroutineType(types: !16)
 !16 = !{null, !17}
-!17 = !{!"0xf\00\000\0064\0064\000\001088\00", null, null, !"_ZTS3foo"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS3foo]
-!18 = !{!"0x2e\00foo\00foo\00\000\000\000\000\000\00320\000\000", null, !"_ZTS3foo", !15, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 0] [foo]
-!19 = !{!"0x2e\00base\00base\00_ZN4baseC2Ev\001\000\001\000\000\00320\000\001", !1, !"_ZTS4base", !20, null, void (%struct.base*)* @_ZN4baseC2Ev, null, !23, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [base]
-!20 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !21, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS3foo")
+!18 = !DISubprogram(name: "foo", isLocal: false, isDefinition: false, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scope: !"_ZTS3foo", type: !15)
+!19 = !DISubprogram(name: "base", linkageName: "_ZN4baseC2Ev", line: 1, isLocal: false, isDefinition: true, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !"_ZTS4base", type: !20, function: void (%struct.base*)* @_ZN4baseC2Ev, declaration: !23, variables: !2)
+!20 = !DISubroutineType(types: !21)
 !21 = !{null, !22}
-!22 = !{!"0xf\00\000\0064\0064\000\001088\00", null, null, !"_ZTS4base"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS4base]
-!23 = !{!"0x2e\00base\00base\00\000\000\000\000\000\00320\000\000", null, !"_ZTS4base", !20, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 0] [base]
-!24 = !{!"0x2e\00~foo\00~foo\00_ZN3fooD2Ev\005\000\001\000\000\00320\000\005", !1, !"_ZTS3foo", !15, null, void (%struct.foo*)* @_ZN3fooD2Ev, null, !25, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [~foo]
-!25 = !{!"0x2e\00~foo\00~foo\00\000\000\000\000\000\00320\000\000", null, !"_ZTS3foo", !15, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 0] [~foo]
-!26 = !{!"0x2e\00\00\00_GLOBAL__sub_I_decl_derived_member.cpp\000\001\001\000\000\0064\000\000", !1, !11, !27, null, void ()* @_GLOBAL__sub_I_decl_derived_member.cpp, null, null, !2} ; [ DW_TAG_subprogram ] [line 0] [local] [def]
-!27 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!22 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS4base")
+!23 = !DISubprogram(name: "base", isLocal: false, isDefinition: false, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scope: !"_ZTS4base", type: !20)
+!24 = !DISubprogram(name: "~foo", linkageName: "_ZN3fooD2Ev", line: 5, isLocal: false, isDefinition: true, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !"_ZTS3foo", type: !15, function: void (%struct.foo*)* @_ZN3fooD2Ev, declaration: !25, variables: !2)
+!25 = !DISubprogram(name: "~foo", isLocal: false, isDefinition: false, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scope: !"_ZTS3foo", type: !15)
+!26 = !DISubprogram(name: "", linkageName: "_GLOBAL__sub_I_decl_derived_member.cpp", isLocal: true, isDefinition: true, flags: DIFlagArtificial, isOptimized: false, file: !1, scope: !11, type: !27, function: void ()* @_GLOBAL__sub_I_decl_derived_member.cpp, variables: !2)
+!27 = !DISubroutineType(types: !2)
 !28 = !{!29}
-!29 = !{!"0x34\00f\00f\00\008\000\001", null, !11, !"_ZTS3foo", %struct.foo* @f, null} ; [ DW_TAG_variable ] [f] [line 8] [def]
+!29 = !DIGlobalVariable(name: "f", line: 8, isLocal: false, isDefinition: true, scope: null, file: !11, type: !"_ZTS3foo", variable: %struct.foo* @f)
 !30 = !{i32 2, !"Dwarf Version", i32 4}
-!31 = !{i32 2, !"Debug Info Version", i32 2}
+!31 = !{i32 2, !"Debug Info Version", i32 3}
 !32 = !{!"clang version 3.7.0 (trunk 227104) (llvm/trunk 227103)"}
-!33 = !MDLocation(line: 8, column: 5, scope: !10)
-!34 = !{!"0x101\00this\0016777216\001088", !14, null, !35} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!35 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS3foo"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS3foo]
-!36 = !{!"0x102"}                                 ; [ DW_TAG_expression ]
-!37 = !MDLocation(line: 0, scope: !14)
-!38 = !MDLocation(line: 5, column: 8, scope: !14)
-!39 = !{!"0x101\00this\0016777216\001088", !24, null, !35} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!40 = !MDLocation(line: 0, scope: !24)
-!41 = !MDLocation(line: 5, column: 8, scope: !42)
-!42 = !{!"0xb\005\008\002", !1, !24}              ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/decl-derived-member.cpp]
-!43 = !MDLocation(line: 5, column: 8, scope: !24)
-!44 = !{!"0x101\00this\0016777216\001088", !19, null, !45} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!45 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS4base"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS4base]
-!46 = !MDLocation(line: 0, scope: !19)
-!47 = !MDLocation(line: 1, column: 8, scope: !19)
-!48 = !MDLocation(line: 0, scope: !26)
+!33 = !DILocation(line: 8, column: 5, scope: !10)
+!34 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !14, type: !35)
+!35 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS3foo")
+!36 = !DIExpression()
+!37 = !DILocation(line: 0, scope: !14)
+!38 = !DILocation(line: 5, column: 8, scope: !14)
+!39 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !24, type: !35)
+!40 = !DILocation(line: 0, scope: !24)
+!41 = !DILocation(line: 5, column: 8, scope: !42)
+!42 = distinct !DILexicalBlock(line: 5, column: 8, file: !1, scope: !24)
+!43 = !DILocation(line: 5, column: 8, scope: !24)
+!44 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !19, type: !45)
+!45 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS4base")
+!46 = !DILocation(line: 0, scope: !19)
+!47 = !DILocation(line: 1, column: 8, scope: !19)
+!48 = !DILocation(line: 0, scope: !26)
diff --git a/test/DebugInfo/X86/deleted-bit-piece.ll b/test/DebugInfo/X86/deleted-bit-piece.ll
new file mode 100644
index 000000000000..63f3be5ea41e
--- /dev/null
+++ b/test/DebugInfo/X86/deleted-bit-piece.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s | FileCheck %s
+; This is mainly a crasher for the revert in r234717.  A debug info intrinsic
+; that gets deleted can't have its bit piece expression verified after it's
+; deleted.
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+; CHECK: __Z3foov:
+; CHECK: retq
+
+define void @_Z3foov() {
+entry:
+  br i1 undef, label %exit, label %bb
+
+bb:                                               ; preds = %entry
+  call void @llvm.dbg.value(metadata i8* undef, i64 0, metadata !15, metadata !16), !dbg !17
+  br label %exit
+
+exit:                                             ; preds = %bb, %entry
+  ret void
+}
+
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+
+!0 = !{i32 2, !"Dwarf Version", i32 2}
+!1 = !{i32 2, !"Debug Info Version", i32 3}
+!2 = !DICompileUnit(language: DW_LANG_C_plus_plus, file: !3, isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !4, retainedTypes: !5, subprograms: !11, globals: !4, imports: !4)
+!3 = !DIFile(filename: "foo.cpp", directory: "/path/to/dir")
+!4 = !{}
+!5 = !{!6}
+!6 = !DICompositeType(tag: DW_TAG_structure_type, name: "Class", size: 64, align: 64, elements: !7, identifier: "_ZT5Class")
+!7 = !{!8, !10}
+!8 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !"_ZT5Class", baseType: !9, size: 32, align: 32)
+!9 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !"_ZT5Class", baseType: !9, size: 32, align: 32)
+!11 = !{!12}
+!12 = !DISubprogram(name: "foo", scope: null, file: !3, type: !13, isLocal: false, isDefinition: true, isOptimized: false, function: void ()* @_Z3foov)
+!13 = !DISubroutineType(types: !14)
+!14 = !{null}
+!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "v", scope: !12, type: !"_ZT5Class")
+!16 = !DIExpression(DW_OP_bit_piece, 32, 32)
+!17 = !DILocation(line: 2755, column: 9, scope: !12)
diff --git a/test/DebugInfo/X86/discriminator.ll b/test/DebugInfo/X86/discriminator.ll
index 185f7cd24164..da5acc753c48 100644
--- a/test/DebugInfo/X86/discriminator.ll
+++ b/test/DebugInfo/X86/discriminator.ll
@@ -16,12 +16,12 @@ entry:
   %retval = alloca i32, align 4
   %i.addr = alloca i32, align 4
   store i32 %i, i32* %i.addr, align 4
-  %0 = load i32* %i.addr, align 4, !dbg !10
+  %0 = load i32, i32* %i.addr, align 4, !dbg !10
   %cmp = icmp slt i32 %0, 10, !dbg !10
   br i1 %cmp, label %if.then, label %if.end, !dbg !10
 
 if.then:                                          ; preds = %entry
-  %1 = load i32* %i.addr, align 4, !dbg !14
+  %1 = load i32, i32* %i.addr, align 4, !dbg !14
   %sub = sub nsw i32 %1, 1, !dbg !14
   store i32 %sub, i32* %retval, !dbg !14
   br label %return, !dbg !14
@@ -31,7 +31,7 @@ if.end:                                           ; preds = %entry
   br label %return, !dbg !12
 
 return:                                           ; preds = %if.end, %if.then
-  %2 = load i32* %retval, !dbg !13
+  %2 = load i32, i32* %retval, !dbg !13
   ret i32 %2, !dbg !13
 }
 
@@ -41,22 +41,22 @@ attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointe
 !llvm.module.flags = !{!7, !8}
 !llvm.ident = !{!9}
 
-!0 = !{!"0x11\0012\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [./discriminator.c] [DW_LANG_C99]
-!1 = !{!"discriminator.c", !"."}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "discriminator.c", directory: ".")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, i32 (i32)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [./discriminator.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 (i32)* @foo, variables: !2)
+!5 = !DIFile(filename: "discriminator.c", directory: ".")
+!6 = !DISubroutineType(types: !2)
 !7 = !{i32 2, !"Dwarf Version", i32 4}
-!8 = !{i32 1, !"Debug Info Version", i32 2}
+!8 = !{i32 1, !"Debug Info Version", i32 3}
 !9 = !{!"clang version 3.5 "}
-!10 = !MDLocation(line: 2, scope: !11)
-!11 = !{!"0xb\002\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [./discriminator.c]
-!12 = !MDLocation(line: 3, scope: !4)
-!13 = !MDLocation(line: 4, scope: !4)
-!14 = !MDLocation(line: 2, scope: !15)
-!15 = !{!"0xb\0042", !1, !4} ; [ DW_TAG_lexical_block ] [./discriminator.c]
+!10 = !DILocation(line: 2, scope: !11)
+!11 = distinct !DILexicalBlock(line: 2, column: 0, file: !1, scope: !4)
+!12 = !DILocation(line: 3, scope: !4)
+!13 = !DILocation(line: 4, scope: !4)
+!14 = !DILocation(line: 2, scope: !15)
+!15 = !DILexicalBlockFile(discriminator: 42, file: !1, scope: !4)
 
 ; CHECK: Address            Line   Column File   ISA Discriminator Flags
 ; CHECK: ------------------ ------ ------ ------ --- ------------- -------------
diff --git a/test/DebugInfo/X86/dwarf-aranges-no-dwarf-labels.ll b/test/DebugInfo/X86/dwarf-aranges-no-dwarf-labels.ll
index 1bda8ec79844..aae155414bd8 100644
--- a/test/DebugInfo/X86/dwarf-aranges-no-dwarf-labels.ll
+++ b/test/DebugInfo/X86/dwarf-aranges-no-dwarf-labels.ll
@@ -28,14 +28,14 @@ target triple = "x86_64-unknown-linux-gnu"
 ; Function Attrs: nounwind readnone uwtable
 define i32 @_Z3fooi(i32 %bar) #0 {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 %bar, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !20
+  tail call void @llvm.dbg.value(metadata i32 %bar, i64 0, metadata !10, metadata !DIExpression()), !dbg !20
   ret i32 %bar, !dbg !20
 }
 
 ; Function Attrs: nounwind readnone uwtable
 define i32 @_Z4foo2i(i32 %bar2) #0 {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 %bar2, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !21
+  tail call void @llvm.dbg.value(metadata i32 %bar2, i64 0, metadata !13, metadata !DIExpression()), !dbg !21
   ret i32 %bar2, !dbg !21
 }
 
@@ -45,7 +45,7 @@ entry:
   %call = tail call i32 @_Z3fooi(i32 2), !dbg !22
   %call1 = tail call i32 @_Z4foo2i(i32 1), !dbg !22
   %add = add nsw i32 %call1, %call, !dbg !22
-  %0 = load i32* @global, align 4, !dbg !22, !tbaa !23
+  %0 = load i32, i32* @global, align 4, !dbg !22, !tbaa !23
   %add2 = add nsw i32 %add, %0, !dbg !22
   ret i32 %add2, !dbg !22
 }
@@ -60,30 +60,30 @@ attributes #2 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!19, !26}
 
-!0 = !{!"0x11\004\00clang version 3.4 (191881)\001\00\000\00\001", !1, !2, !2, !3, !17, !2} ; [ DW_TAG_compile_unit ] [/tmp/debug_ranges/a.cc] [DW_LANG_C_plus_plus]
-!1 = !{!"tmp/debug_ranges/a.cc", !"/"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 (191881)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !17, imports: !2)
+!1 = !DIFile(filename: "tmp/debug_ranges/a.cc", directory: "/")
 !2 = !{}
 !3 = !{!4, !11, !14}
-!4 = !{!"0x2e\00foo\00foo\00_Z3fooi\002\000\001\000\006\00256\001\002", !1, !5, !6, null, i32 (i32)* @_Z3fooi, null, null, !9} ; [ DW_TAG_subprogram ] [line 2] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/debug_ranges/a.cc]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", linkageName: "_Z3fooi", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2, file: !1, scope: !5, type: !6, function: i32 (i32)* @_Z3fooi, variables: !9)
+!5 = !DIFile(filename: "tmp/debug_ranges/a.cc", directory: "/")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{!10}
-!10 = !{!"0x101\00bar\0016777218\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [bar] [line 2]
-!11 = !{!"0x2e\00foo2\00foo2\00_Z4foo2i\003\000\001\000\006\00256\001\003", !1, !5, !6, null, i32 (i32)* @_Z4foo2i, null, null, !12} ; [ DW_TAG_subprogram ] [line 3] [def] [foo2]
+!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "bar", line: 2, arg: 1, scope: !4, file: !5, type: !8)
+!11 = !DISubprogram(name: "foo2", linkageName: "_Z4foo2i", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !1, scope: !5, type: !6, function: i32 (i32)* @_Z4foo2i, variables: !12)
 !12 = !{!13}
-!13 = !{!"0x101\00bar2\0016777219\000", !11, !5, !8} ; [ DW_TAG_arg_variable ] [bar2] [line 3]
-!14 = !{!"0x2e\00main\00main\00\005\000\001\000\006\00256\001\005", !1, !5, !15, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [main]
-!15 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "bar2", line: 3, arg: 1, scope: !11, file: !5, type: !8)
+!14 = !DISubprogram(name: "main", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !1, scope: !5, type: !15, function: i32 ()* @main, variables: !2)
+!15 = !DISubroutineType(types: !16)
 !16 = !{!8}
 !17 = !{!18}
-!18 = !{!"0x34\00global\00global\00\001\000\001", null, !5, !8, i32* @global, null} ; [ DW_TAG_variable ] [global] [line 1] [def]
+!18 = !DIGlobalVariable(name: "global", line: 1, isLocal: false, isDefinition: true, scope: null, file: !5, type: !8, variable: i32* @global)
 !19 = !{i32 2, !"Dwarf Version", i32 4}
-!20 = !MDLocation(line: 2, scope: !4)
-!21 = !MDLocation(line: 3, scope: !11)
-!22 = !MDLocation(line: 6, scope: !14)
+!20 = !DILocation(line: 2, scope: !4)
+!21 = !DILocation(line: 3, scope: !11)
+!22 = !DILocation(line: 6, scope: !14)
 !23 = !{!"int", !24}
 !24 = !{!"omnipotent char", !25}
 !25 = !{!"Simple C/C++ TBAA"}
-!26 = !{i32 1, !"Debug Info Version", i32 2}
+!26 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dwarf-aranges.ll b/test/DebugInfo/X86/dwarf-aranges.ll
index 6873e58eab5b..9924697247b3 100644
--- a/test/DebugInfo/X86/dwarf-aranges.ll
+++ b/test/DebugInfo/X86/dwarf-aranges.ll
@@ -3,27 +3,27 @@
 
 ; -- header --
 ; CHECK: .short 2 # DWARF Arange version number
-; CHECK-NEXT: .long .L.debug_info_begin0
+; CHECK-NEXT: .long .Lcu_begin0
 ; CHECK-NEXT: .byte 8 # Address Size (in bytes)
 ; CHECK-NEXT: .byte 0 # Segment Size (in bytes)
 ; -- alignment --
 ; CHECK-NEXT: .zero 4,255
 
+; <data section> - it should have made one span covering all vars in this CU.
+; CHECK-NEXT: .quad some_data
+; CHECK-NEXT: .quad .Lsec_end0-some_data
+
+; <other sections> - it should have made one span covering all vars in this CU.
+; CHECK-NEXT: .quad some_other
+; CHECK-NEXT: .quad .Lsec_end1-some_other
+
 ; <common symbols> - it should have made one span for each symbol.
 ; CHECK-NEXT: .quad some_bss
 ; CHECK-NEXT: .quad 4
 
-; <data section> - it should have made one span covering all vars in this CU.
-; CHECK-NEXT: .quad some_data
-; CHECK-NEXT: .quad .Ldebug_end1-some_data
-
 ; <text section> - it should have made one span covering all functions in this CU.
 ; CHECK-NEXT: .quad .Lfunc_begin0
-; CHECK-NEXT: .quad .Ldebug_end2-.Lfunc_begin0
-
-; <other sections> - it should have made one span covering all vars in this CU.
-; CHECK-NEXT: .quad some_other
-; CHECK-NEXT: .quad .Ldebug_end3-some_other
+; CHECK-NEXT: .quad .Lsec_end2-.Lfunc_begin0
 
 ; -- finish --
 ; CHECK-NEXT: # ARange terminator
@@ -50,10 +50,10 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define void @some_code() {
 entry:
-  %0 = load i32* @some_data, align 4, !dbg !14
-  %1 = load i32* @some_other, align 4, !dbg !14
+  %0 = load i32, i32* @some_data, align 4, !dbg !14
+  %1 = load i32, i32* @some_other, align 4, !dbg !14
   %add = add nsw i32 %0, %1, !dbg !14
-  %2 = load i32* @some_bss, align 4, !dbg !14
+  %2 = load i32, i32* @some_bss, align 4, !dbg !14
   %add1 = add nsw i32 %2, %add, !dbg !14
   store i32 %add1, i32* @some_bss, align 4, !dbg !14
   ret void, !dbg !15
@@ -62,20 +62,20 @@ entry:
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!13, !16}
 
-!0 = !{!"0x11\0012\00clang version 3.4 \000\00\000\00\000", !1, !2, !2, !3, !8, !2} ; [ DW_TAG_compile_unit ] [/home/kayamon/test.c] [DW_LANG_C99]
-!1 = !{!"test.c", !"/home/kayamon"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !8, imports: !2)
+!1 = !DIFile(filename: "test.c", directory: "/home/kayamon")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00some_code\00some_code\00\005\000\001\000\006\000\000\006", !1, !5, !6, null, void ()* @some_code, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [scope 6] [some_code]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/home/kayamon/test.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "some_code", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 6, file: !1, scope: !5, type: !6, function: void ()* @some_code, variables: !2)
+!5 = !DIFile(filename: "test.c", directory: "/home/kayamon")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
 !8 = !{!9, !11, !12}
-!9 = !{!"0x34\00some_data\00some_data\00\001\000\001", null, !5, !10, i32* @some_data, null} ; [ DW_TAG_variable ] [some_data] [line 1] [def]
-!10 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!11 = !{!"0x34\00some_other\00some_other\00\003\000\001", null, !5, !10, i32* @some_other, null} ; [ DW_TAG_variable ] [some_other] [line 3] [def]
-!12 = !{!"0x34\00some_bss\00some_bss\00\002\000\001", null, !5, !10, i32* @some_bss, null} ; [ DW_TAG_variable ] [some_bss] [line 2] [def]
+!9 = !DIGlobalVariable(name: "some_data", line: 1, isLocal: false, isDefinition: true, scope: null, file: !5, type: !10, variable: i32* @some_data)
+!10 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!11 = !DIGlobalVariable(name: "some_other", line: 3, isLocal: false, isDefinition: true, scope: null, file: !5, type: !10, variable: i32* @some_other)
+!12 = !DIGlobalVariable(name: "some_bss", line: 2, isLocal: false, isDefinition: true, scope: null, file: !5, type: !10, variable: i32* @some_bss)
 !13 = !{i32 2, !"Dwarf Version", i32 4}
-!14 = !MDLocation(line: 7, scope: !4)
-!15 = !MDLocation(line: 8, scope: !4)
-!16 = !{i32 1, !"Debug Info Version", i32 2}
+!14 = !DILocation(line: 7, scope: !4)
+!15 = !DILocation(line: 8, scope: !4)
+!16 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dwarf-public-names.ll b/test/DebugInfo/X86/dwarf-public-names.ll
index 778738ccb5f0..48f13fd1e07b 100644
--- a/test/DebugInfo/X86/dwarf-public-names.ll
+++ b/test/DebugInfo/X86/dwarf-public-names.ll
@@ -1,7 +1,9 @@
 ; RUN: llc -mtriple=x86_64-pc-linux-gnu -filetype=obj -o %t.o < %s
 ; RUN: llvm-dwarfdump -debug-dump=pubnames %t.o | FileCheck --check-prefix=LINUX %s
 ; RUN: llc -mtriple=x86_64-apple-darwin12 -filetype=obj -o %t.o < %s
-; RUN: llvm-dwarfdump -debug-dump=pubnames %t.o | FileCheck --check-prefix=DARWIN %s
+; RUN: llvm-dwarfdump -debug-dump=pubnames %t.o | FileCheck --check-prefix=NOPUB %s
+; RUN: llc -mtriple=x86_64-scei-ps4 -filetype=obj -o %t.o < %s
+; RUN: llvm-dwarfdump -debug-dump=pubnames %t.o | FileCheck --check-prefix=NOPUB %s
 ; ModuleID = 'dwarf-public-names.cpp'
 ;
 ; Generated from:
@@ -35,9 +37,9 @@
 ;   int global_namespace_variable = 1;
 ; }
 
-; Darwin shouldn't be generating the section by default
-; DARWIN: debug_pubnames
-; DARWIN: {{^$}}
+; Darwin and PS4 shouldn't be generating the section by default
+; NOPUB: debug_pubnames
+; NOPUB: {{^$}}
 
 ; Skip the output to the header of the pubnames section.
 ; LINUX: debug_pubnames
@@ -63,8 +65,8 @@ define void @_ZN1C15member_functionEv(%struct.C* %this) nounwind uwtable align 2
 entry:
   %this.addr = alloca %struct.C*, align 8
   store %struct.C* %this, %struct.C** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.C** %this.addr, metadata !28, metadata !{!"0x102"}), !dbg !30
-  %this1 = load %struct.C** %this.addr
+  call void @llvm.dbg.declare(metadata %struct.C** %this.addr, metadata !28, metadata !DIExpression()), !dbg !30
+  %this1 = load %struct.C*, %struct.C** %this.addr
   store i32 0, i32* @_ZN1C22static_member_variableE, align 4, !dbg !31
   ret void, !dbg !32
 }
@@ -73,7 +75,7 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 
 define i32 @_ZN1C22static_member_functionEv() nounwind uwtable align 2 {
 entry:
-  %0 = load i32* @_ZN1C22static_member_variableE, align 4, !dbg !33
+  %0 = load i32, i32* @_ZN1C22static_member_variableE, align 4, !dbg !33
   ret i32 %0, !dbg !33
 }
 
@@ -94,42 +96,42 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!38}
 
-!0 = !{!"0x11\004\00clang version 3.3 (http://llvm.org/git/clang.git a09cd8103a6a719cb2628cdf0c91682250a17bd2) (http://llvm.org/git/llvm.git 47d03cec0afca0c01ae42b82916d1d731716cd20)\000\00\000\00\000", !37, !1, !1, !2, !24,  !1} ; [ DW_TAG_compile_unit ] [/usr2/kparzysz/s.hex/t/dwarf-public-names.cpp] [DW_LANG_C_plus_plus]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 (http://llvm.org/git/clang.git a09cd8103a6a719cb2628cdf0c91682250a17bd2) (http://llvm.org/git/llvm.git 47d03cec0afca0c01ae42b82916d1d731716cd20)", isOptimized: false, emissionKind: 0, file: !37, enums: !1, retainedTypes: !1, subprograms: !2, globals: !24, imports:  !1)
 !1 = !{}
 !2 = !{!3, !18, !19, !20}
-!3 = !{!"0x2e\00member_function\00member_function\00_ZN1C15member_functionEv\009\000\001\000\006\00256\000\009", !4, null, !5, null, void (%struct.C*)* @_ZN1C15member_functionEv, null, !12, !1} ; [ DW_TAG_subprogram ] [line 9] [def] [member_function]
-!4 = !{!"0x29", !37} ; [ DW_TAG_file_type ]
-!5 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !6, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!3 = !DISubprogram(name: "member_function", linkageName: "_ZN1C15member_functionEv", line: 9, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 9, file: !4, scope: null, type: !5, function: void (%struct.C*)* @_ZN1C15member_functionEv, declaration: !12, variables: !1)
+!4 = !DIFile(filename: "dwarf-public-names.cpp", directory: "/usr2/kparzysz/s.hex/t")
+!5 = !DISubroutineType(types: !6)
 !6 = !{null, !7}
-!7 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !8} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from C]
-!8 = !{!"0x13\00C\001\008\008\000\000\000", !37, null, null, !9, null, null, null} ; [ DW_TAG_structure_type ] [C] [line 1, size 8, align 8, offset 0] [def] [from ]
+!7 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !8)
+!8 = !DICompositeType(tag: DW_TAG_structure_type, name: "C", line: 1, size: 8, align: 8, file: !37, elements: !9)
 !9 = !{!10, !12, !14}
-!10 = !{!"0xd\00static_member_variable\004\000\000\000\004096", !37, !8, !11, null} ; [ DW_TAG_member ] [static_member_variable] [line 4, size 0, align 0, offset 0] [static] [from int]
-!11 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!12 = !{!"0x2e\00member_function\00member_function\00_ZN1C15member_functionEv\002\000\000\000\006\00256\000\002", !4, !8, !5, null, null, null, i32 0, !13} ; [ DW_TAG_subprogram ] [line 2] [member_function]
-!13 = !{!"0x24"}                      ; [ DW_TAG_base_type ] [line 0, size 0, align 0, offset 0]
-!14 = !{!"0x2e\00static_member_function\00static_member_function\00_ZN1C22static_member_functionEv\003\000\000\000\006\00256\000\003", !4, !8, !15, null, null, null, i32 0, !17} ; [ DW_TAG_subprogram ] [line 3] [static_member_function]
-!15 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!10 = !DIDerivedType(tag: DW_TAG_member, name: "static_member_variable", line: 4, flags: DIFlagStaticMember, file: !37, scope: !8, baseType: !11)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!12 = !DISubprogram(name: "member_function", linkageName: "_ZN1C15member_functionEv", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !4, scope: !8, type: !5, variables: !13)
+!13 = !{} ; previously: invalid DW_TAG_base_type
+!14 = !DISubprogram(name: "static_member_function", linkageName: "_ZN1C22static_member_functionEv", line: 3, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !4, scope: !8, type: !15, variables: !17)
+!15 = !DISubroutineType(types: !16)
 !16 = !{!11}
-!17 = !{!"0x24"}                      ; [ DW_TAG_base_type ] [line 0, size 0, align 0, offset 0]
-!18 = !{!"0x2e\00static_member_function\00static_member_function\00_ZN1C22static_member_functionEv\0013\000\001\000\006\00256\000\0013", !4, null, !15, null, i32 ()* @_ZN1C22static_member_functionEv, null, !14, !1} ; [ DW_TAG_subprogram ] [line 13] [def] [static_member_function]
-!19 = !{!"0x2e\00global_function\00global_function\00_Z15global_functionv\0019\000\001\000\006\00256\000\0019", !4, !4, !15, null, i32 ()* @_Z15global_functionv, null, null, !1} ; [ DW_TAG_subprogram ] [line 19] [def] [global_function]
-!20 = !{!"0x2e\00global_namespace_function\00global_namespace_function\00_ZN2ns25global_namespace_functionEv\0024\000\001\000\006\00256\000\0024", !4, !21, !22, null, void ()* @_ZN2ns25global_namespace_functionEv, null, null, !1} ; [ DW_TAG_subprogram ] [line 24] [def] [global_namespace_function]
-!21 = !{!"0x39\00ns\0023", !4, null} ; [ DW_TAG_namespace ] [/usr2/kparzysz/s.hex/t/dwarf-public-names.cpp]
-!22 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !23, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!17 = !{} ; previously: invalid DW_TAG_base_type
+!18 = !DISubprogram(name: "static_member_function", linkageName: "_ZN1C22static_member_functionEv", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 13, file: !4, scope: null, type: !15, function: i32 ()* @_ZN1C22static_member_functionEv, declaration: !14, variables: !1)
+!19 = !DISubprogram(name: "global_function", linkageName: "_Z15global_functionv", line: 19, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 19, file: !4, scope: !4, type: !15, function: i32 ()* @_Z15global_functionv, variables: !1)
+!20 = !DISubprogram(name: "global_namespace_function", linkageName: "_ZN2ns25global_namespace_functionEv", line: 24, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 24, file: !4, scope: !21, type: !22, function: void ()* @_ZN2ns25global_namespace_functionEv, variables: !1)
+!21 = !DINamespace(name: "ns", line: 23, file: !4, scope: null)
+!22 = !DISubroutineType(types: !23)
 !23 = !{null}
 !24 = !{!25, !26, !27}
-!25 = !{!"0x34\00static_member_variable\00static_member_variable\00_ZN1C22static_member_variableE\007\000\001", !8, !4, !11, i32* @_ZN1C22static_member_variableE, !10} ; [ DW_TAG_variable ] [static_member_variable] [line 7] [def]
-!26 = !{!"0x34\00global_variable\00global_variable\00\0017\000\001", null, !4, !8, %struct.C* @global_variable, null} ; [ DW_TAG_variable ] [global_variable] [line 17] [def]
-!27 = !{!"0x34\00global_namespace_variable\00global_namespace_variable\00_ZN2ns25global_namespace_variableE\0027\000\001", !21, !4, !11, i32* @_ZN2ns25global_namespace_variableE, null} ; [ DW_TAG_variable ] [global_namespace_variable] [line 27] [def]
-!28 = !{!"0x101\00this\0016777225\001088", !3, !4, !29} ; [ DW_TAG_arg_variable ] [this] [line 9]
-!29 = !{!"0xf\00\000\0064\0064\000\000", null, null, !8} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from C]
-!30 = !MDLocation(line: 9, scope: !3)
-!31 = !MDLocation(line: 10, scope: !3)
-!32 = !MDLocation(line: 11, scope: !3)
-!33 = !MDLocation(line: 14, scope: !18)
-!34 = !MDLocation(line: 20, scope: !19)
-!35 = !MDLocation(line: 25, scope: !20)
-!36 = !MDLocation(line: 26, scope: !20)
-!37 = !{!"dwarf-public-names.cpp", !"/usr2/kparzysz/s.hex/t"}
-!38 = !{i32 1, !"Debug Info Version", i32 2}
+!25 = !DIGlobalVariable(name: "static_member_variable", linkageName: "_ZN1C22static_member_variableE", line: 7, isLocal: false, isDefinition: true, scope: !8, file: !4, type: !11, variable: i32* @_ZN1C22static_member_variableE, declaration: !10)
+!26 = !DIGlobalVariable(name: "global_variable", line: 17, isLocal: false, isDefinition: true, scope: null, file: !4, type: !8, variable: %struct.C* @global_variable)
+!27 = !DIGlobalVariable(name: "global_namespace_variable", linkageName: "_ZN2ns25global_namespace_variableE", line: 27, isLocal: false, isDefinition: true, scope: !21, file: !4, type: !11, variable: i32* @_ZN2ns25global_namespace_variableE)
+!28 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 9, arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !3, file: !4, type: !29)
+!29 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !8)
+!30 = !DILocation(line: 9, scope: !3)
+!31 = !DILocation(line: 10, scope: !3)
+!32 = !DILocation(line: 11, scope: !3)
+!33 = !DILocation(line: 14, scope: !18)
+!34 = !DILocation(line: 20, scope: !19)
+!35 = !DILocation(line: 25, scope: !20)
+!36 = !DILocation(line: 26, scope: !20)
+!37 = !DIFile(filename: "dwarf-public-names.cpp", directory: "/usr2/kparzysz/s.hex/t")
+!38 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/dwarf-pubnames-split.ll b/test/DebugInfo/X86/dwarf-pubnames-split.ll
index fc99474badd9..f17f7848f046 100644
--- a/test/DebugInfo/X86/dwarf-pubnames-split.ll
+++ b/test/DebugInfo/X86/dwarf-pubnames-split.ll
@@ -9,7 +9,7 @@
 
 ; CHECK: .LpubTypes_begin0:
 ; CHECK-NEXT: .short    2                       # DWARF Version
-; CHECK-NEXT: .long     .L.debug_info_begin0    # Offset of Compilation Unit Info
+; CHECK-NEXT: .long     .Lcu_begin0             # Offset of Compilation Unit Info
 
 ; Function Attrs: nounwind uwtable
 define i32 @main() #0 {
@@ -24,15 +24,15 @@ attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointe
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!9, !11}
 
-!0 = !{!"0x11\0012\00clang version 3.4 (trunk 189287) (llvm/trunk 189296)\000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/foo.c] [DW_LANG_C99]
-!1 = !{!"foo.c", !"/usr/local/google/home/echristo/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 189287) (llvm/trunk 189296)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "foo.c", directory: "/usr/local/google/home/echristo/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00main\00main\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [main]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/usr/local/google/home/echristo/tmp/foo.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "main", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 ()* @main, variables: !2)
+!5 = !DIFile(filename: "foo.c", directory: "/usr/local/google/home/echristo/tmp")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 3}
-!10 = !MDLocation(line: 2, scope: !4)
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !DILocation(line: 2, scope: !4)
+!11 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/earlydup-crash.ll b/test/DebugInfo/X86/earlydup-crash.ll
index fb85ada9d04f..738b7194488f 100644
--- a/test/DebugInfo/X86/earlydup-crash.ll
+++ b/test/DebugInfo/X86/earlydup-crash.ll
@@ -13,11 +13,11 @@ entry:
 bb:                                               ; preds = %entry
   %tmp = icmp eq i32 undef, 0
   %tmp1 = add i32 0, 11
-  call void @llvm.dbg.value(metadata i32 %tmp1, i64 0, metadata !0, metadata !{!"0x102"})
+  call void @llvm.dbg.value(metadata i32 %tmp1, i64 0, metadata !0, metadata !DIExpression()), !dbg !DILocation(scope: !1)
   br i1 undef, label %bb18, label %bb31.preheader
 
 bb31.preheader:                                   ; preds = %bb19, %bb
-  %tmp2 = getelementptr inbounds i8* %fname, i32 0
+  %tmp2 = getelementptr inbounds i8, i8* %fname, i32 0
   br label %bb31
 
 bb18:                                             ; preds = %bb
@@ -44,51 +44,51 @@ declare void @foobar(i32)
 
 !llvm.dbg.cu = !{!4}
 !llvm.module.flags = !{!47}
-!0 = !{!"0x100\00frname_len\00517\000", !1, !3, !38} ; [ DW_TAG_auto_variable ]
-!1 = !{!"0xb\00515\000\0019", !44, !2} ; [ DW_TAG_lexical_block ]
-!2 = !{!"0x2e\00framework_construct_pathname\00framework_construct_pathname\00\00515\001\001\000\006\00256\001\000", !44, null, !5, null, i8* (i8*, %struct.cpp_dir*)* @framework_construct_pathname, null, null, null} ; [ DW_TAG_subprogram ]
-!3 = !{!"0x29", !44}  ; [ DW_TAG_file_type ]
-!4 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\001\00\000\00\000", !44, !46, !46, !45, null, null} ; [ DW_TAG_compile_unit ]
-!5 = !{!"0x15\00\000\000\000\000\000\000", !44, !3, null, !6, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "frname_len", line: 517, scope: !1, file: !3, type: !38)
+!1 = distinct !DILexicalBlock(line: 515, column: 0, file: !44, scope: !2)
+!2 = !DISubprogram(name: "framework_construct_pathname", line: 515, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !44, scope: null, type: !5, function: i8* (i8*, %struct.cpp_dir*)* @framework_construct_pathname)
+!3 = !DIFile(filename: "darwin-c.c", directory: "/Users/espindola/llvm/build-llvm-gcc/gcc/../../llvm-gcc-4.2/gcc/config")
+!4 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 0, file: !44, enums: !46, retainedTypes: !46, subprograms: !45)
+!5 = !DISubroutineType(types: !6)
 !6 = !{!7, !9, !11}
-!7 = !{!"0xf\00\000\0032\0032\000\000", !44, !3, !8} ; [ DW_TAG_pointer_type ]
-!8 = !{!"0x24\00char\000\008\008\000\000\006", !44, !3} ; [ DW_TAG_base_type ]
-!9 = !{!"0xf\00\000\0032\0032\000\000", !44, !3, !10} ; [ DW_TAG_pointer_type ]
-!10 = !{!"0x26\00\000\008\008\000\000", !44, !3, !8} ; [ DW_TAG_const_type ]
-!11 = !{!"0xf\00\000\0032\0032\000\000", !44, !3, !12} ; [ DW_TAG_pointer_type ]
-!12 = !{!"0x16\00cpp_dir\0045\000\000\000\000", !41, !13, !14} ; [ DW_TAG_typedef ]
-!13 = !{!"0x29", !41} ; [ DW_TAG_file_type ]
-!14 = !{!"0x13\00cpp_dir\0043\00352\0032\000\000\000", !41, !3, null, !15, null, null, null} ; [ DW_TAG_structure_type ] [cpp_dir] [line 43, size 352, align 32, offset 0] [def] [from ]
+!7 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !44, scope: !3, baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !44, scope: !3, baseType: !10)
+!10 = !DIDerivedType(tag: DW_TAG_const_type, size: 8, align: 8, file: !44, scope: !3, baseType: !8)
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !44, scope: !3, baseType: !12)
+!12 = !DIDerivedType(tag: DW_TAG_typedef, name: "cpp_dir", line: 45, file: !41, scope: !13, baseType: !14)
+!13 = !DIFile(filename: "cpplib.h", directory: "/Users/espindola/llvm/build-llvm-gcc/gcc/../../llvm-gcc-4.2/gcc/../libcpp/include")
+!14 = !DICompositeType(tag: DW_TAG_structure_type, name: "cpp_dir", line: 43, size: 352, align: 32, file: !41, scope: !3, elements: !15)
 !15 = !{!16, !18, !19, !21, !23, !25, !27, !29, !33, !36}
-!16 = !{!"0xd\00next\00572\0032\0032\000\000", !41, !14, !17} ; [ DW_TAG_member ]
-!17 = !{!"0xf\00\000\0032\0032\000\000", !44, !3, !14} ; [ DW_TAG_pointer_type ]
-!18 = !{!"0xd\00name\00575\0032\0032\0032\000", !41, !14, !7} ; [ DW_TAG_member ]
-!19 = !{!"0xd\00len\00576\0032\0032\0064\000", !41, !14, !20} ; [ DW_TAG_member ]
-!20 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", !44, !3} ; [ DW_TAG_base_type ]
-!21 = !{!"0xd\00sysp\00580\008\008\0096\000", !41, !14, !22} ; [ DW_TAG_member ]
-!22 = !{!"0x24\00unsigned char\000\008\008\000\000\008", !44, !3} ; [ DW_TAG_base_type ]
-!23 = !{!"0xd\00name_map\00584\0032\0032\00128\000", !41, !14, !24} ; [ DW_TAG_member ]
-!24 = !{!"0xf\00\000\0032\0032\000\000", !44, !3, !9} ; [ DW_TAG_pointer_type ]
-!25 = !{!"0xd\00header_map\00590\0032\0032\00160\000", !41, !14, !26} ; [ DW_TAG_member ]
-!26 = !{!"0xf\00\000\0032\0032\000\000", !44, !3, null} ; [ DW_TAG_pointer_type ]
-!27 = !{!"0xd\00construct\00597\0032\0032\00192\000", !41, !14, !28} ; [ DW_TAG_member ]
-!28 = !{!"0xf\00\000\0032\0032\000\000", !44, !3, !5} ; [ DW_TAG_pointer_type ]
-!29 = !{!"0xd\00ino\00601\0064\0064\00224\000", !41, !14, !30} ; [ DW_TAG_member ]
-!30 = !{!"0x16\00ino_t\00141\000\000\000\000", !42, !31, !32} ; [ DW_TAG_typedef ]
-!31 = !{!"0x29", !42} ; [ DW_TAG_file_type ]
-!32 = !{!"0x24\00long long unsigned int\000\0064\0064\000\000\007", !44, !3} ; [ DW_TAG_base_type ]
-!33 = !{!"0xd\00dev\00602\0032\0032\00288\000", !41, !14, !34} ; [ DW_TAG_member ]
-!34 = !{!"0x16\00dev_t\00107\000\000\000\000", !42, !31, !35} ; [ DW_TAG_typedef ]
-!35 = !{!"0x24\00int\000\0032\0032\000\000\005", !44, !3} ; [ DW_TAG_base_type ]
-!36 = !{!"0xd\00user_supplied_p\00605\008\008\00320\000", !41, !14, !37} ; [ DW_TAG_member ]
-!37 = !{!"0x24\00_Bool\000\008\008\000\000\002", !44, !3} ; [ DW_TAG_base_type ]
-!38 = !{!"0x16\00size_t\00326\000\000\000\000", !43, !39, !40} ; [ DW_TAG_typedef ]
-!39 = !{!"0x29", !43} ; [ DW_TAG_file_type ]
-!40 = !{!"0x24\00long unsigned int\000\0032\0032\000\000\007", !44, !3} ; [ DW_TAG_base_type ]
-!41 = !{!"cpplib.h", !"/Users/espindola/llvm/build-llvm-gcc/gcc/../../llvm-gcc-4.2/gcc/../libcpp/include"}
-!42 = !{!"types.h", !"/usr/include/sys"}
-!43 = !{!"stddef.h", !"/Users/espindola/llvm/build-llvm-gcc/./prev-gcc/include"}
-!44 = !{!"darwin-c.c", !"/Users/espindola/llvm/build-llvm-gcc/gcc/../../llvm-gcc-4.2/gcc/config"}
+!16 = !DIDerivedType(tag: DW_TAG_member, name: "next", line: 572, size: 32, align: 32, file: !41, scope: !14, baseType: !17)
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !44, scope: !3, baseType: !14)
+!18 = !DIDerivedType(tag: DW_TAG_member, name: "name", line: 575, size: 32, align: 32, offset: 32, file: !41, scope: !14, baseType: !7)
+!19 = !DIDerivedType(tag: DW_TAG_member, name: "len", line: 576, size: 32, align: 32, offset: 64, file: !41, scope: !14, baseType: !20)
+!20 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!21 = !DIDerivedType(tag: DW_TAG_member, name: "sysp", line: 580, size: 8, align: 8, offset: 96, file: !41, scope: !14, baseType: !22)
+!22 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char)
+!23 = !DIDerivedType(tag: DW_TAG_member, name: "name_map", line: 584, size: 32, align: 32, offset: 128, file: !41, scope: !14, baseType: !24)
+!24 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !44, scope: !3, baseType: !9)
+!25 = !DIDerivedType(tag: DW_TAG_member, name: "header_map", line: 590, size: 32, align: 32, offset: 160, file: !41, scope: !14, baseType: !26)
+!26 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !44, scope: !3, baseType: null)
+!27 = !DIDerivedType(tag: DW_TAG_member, name: "construct", line: 597, size: 32, align: 32, offset: 192, file: !41, scope: !14, baseType: !28)
+!28 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !44, scope: !3, baseType: !5)
+!29 = !DIDerivedType(tag: DW_TAG_member, name: "ino", line: 601, size: 64, align: 64, offset: 224, file: !41, scope: !14, baseType: !30)
+!30 = !DIDerivedType(tag: DW_TAG_typedef, name: "ino_t", line: 141, file: !42, scope: !31, baseType: !32)
+!31 = !DIFile(filename: "types.h", directory: "/usr/include/sys")
+!32 = !DIBasicType(tag: DW_TAG_base_type, name: "long long unsigned int", size: 64, align: 64, encoding: DW_ATE_unsigned)
+!33 = !DIDerivedType(tag: DW_TAG_member, name: "dev", line: 602, size: 32, align: 32, offset: 288, file: !41, scope: !14, baseType: !34)
+!34 = !DIDerivedType(tag: DW_TAG_typedef, name: "dev_t", line: 107, file: !42, scope: !31, baseType: !35)
+!35 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!36 = !DIDerivedType(tag: DW_TAG_member, name: "user_supplied_p", line: 605, size: 8, align: 8, offset: 320, file: !41, scope: !14, baseType: !37)
+!37 = !DIBasicType(tag: DW_TAG_base_type, name: "_Bool", size: 8, align: 8, encoding: DW_ATE_boolean)
+!38 = !DIDerivedType(tag: DW_TAG_typedef, name: "size_t", line: 326, file: !43, scope: !39, baseType: !40)
+!39 = !DIFile(filename: "stddef.h", directory: "/Users/espindola/llvm/build-llvm-gcc/./prev-gcc/include")
+!40 = !DIBasicType(tag: DW_TAG_base_type, name: "long unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!41 = !DIFile(filename: "cpplib.h", directory: "/Users/espindola/llvm/build-llvm-gcc/gcc/../../llvm-gcc-4.2/gcc/../libcpp/include")
+!42 = !DIFile(filename: "types.h", directory: "/usr/include/sys")
+!43 = !DIFile(filename: "stddef.h", directory: "/Users/espindola/llvm/build-llvm-gcc/./prev-gcc/include")
+!44 = !DIFile(filename: "darwin-c.c", directory: "/Users/espindola/llvm/build-llvm-gcc/gcc/../../llvm-gcc-4.2/gcc/config")
 !45 = !{!2}
-!46 = !{i32 0}
-!47 = !{i32 1, !"Debug Info Version", i32 2}
+!46 = !{}
+!47 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/elf-names.ll b/test/DebugInfo/X86/elf-names.ll
index 910a67447770..e4565c27cf72 100644
--- a/test/DebugInfo/X86/elf-names.ll
+++ b/test/DebugInfo/X86/elf-names.ll
@@ -13,7 +13,7 @@
 ; CHECK: DW_TAG_formal_parameter
 ; CHECK: DW_AT_artificial [DW_FORM_flag_present]       (true)
 
-; CHECK-DIS: [artificial]
+; CHECK-DIS: DIFlagArtificial
 
 %class.D = type { i32, i32, i32, i32 }
 
@@ -22,37 +22,37 @@
 
 define void @_ZN1DC2Ev(%class.D* nocapture %this) unnamed_addr nounwind uwtable align 2 {
 entry:
-  tail call void @llvm.dbg.value(metadata %class.D* %this, i64 0, metadata !29, metadata !{!"0x102"}), !dbg !36
-  %c1 = getelementptr inbounds %class.D* %this, i64 0, i32 0, !dbg !37
+  tail call void @llvm.dbg.value(metadata %class.D* %this, i64 0, metadata !29, metadata !DIExpression()), !dbg !36
+  %c1 = getelementptr inbounds %class.D, %class.D* %this, i64 0, i32 0, !dbg !37
   store i32 1, i32* %c1, align 4, !dbg !37
-  %c2 = getelementptr inbounds %class.D* %this, i64 0, i32 1, !dbg !42
+  %c2 = getelementptr inbounds %class.D, %class.D* %this, i64 0, i32 1, !dbg !42
   store i32 2, i32* %c2, align 4, !dbg !42
-  %c3 = getelementptr inbounds %class.D* %this, i64 0, i32 2, !dbg !43
+  %c3 = getelementptr inbounds %class.D, %class.D* %this, i64 0, i32 2, !dbg !43
   store i32 3, i32* %c3, align 4, !dbg !43
-  %c4 = getelementptr inbounds %class.D* %this, i64 0, i32 3, !dbg !44
+  %c4 = getelementptr inbounds %class.D, %class.D* %this, i64 0, i32 3, !dbg !44
   store i32 4, i32* %c4, align 4, !dbg !44
   ret void, !dbg !45
 }
 
 define void @_ZN1DC2ERKS_(%class.D* nocapture %this, %class.D* nocapture %d) unnamed_addr nounwind uwtable align 2 {
 entry:
-  tail call void @llvm.dbg.value(metadata %class.D* %this, i64 0, metadata !34, metadata !{!"0x102"}), !dbg !46
-  tail call void @llvm.dbg.value(metadata %class.D* %d, i64 0, metadata !35, metadata !{!"0x102"}), !dbg !46
-  %c1 = getelementptr inbounds %class.D* %d, i64 0, i32 0, !dbg !47
-  %0 = load i32* %c1, align 4, !dbg !47
-  %c12 = getelementptr inbounds %class.D* %this, i64 0, i32 0, !dbg !47
+  tail call void @llvm.dbg.value(metadata %class.D* %this, i64 0, metadata !34, metadata !DIExpression()), !dbg !46
+  tail call void @llvm.dbg.value(metadata %class.D* %d, i64 0, metadata !35, metadata !DIExpression()), !dbg !46
+  %c1 = getelementptr inbounds %class.D, %class.D* %d, i64 0, i32 0, !dbg !47
+  %0 = load i32, i32* %c1, align 4, !dbg !47
+  %c12 = getelementptr inbounds %class.D, %class.D* %this, i64 0, i32 0, !dbg !47
   store i32 %0, i32* %c12, align 4, !dbg !47
-  %c2 = getelementptr inbounds %class.D* %d, i64 0, i32 1, !dbg !49
-  %1 = load i32* %c2, align 4, !dbg !49
-  %c23 = getelementptr inbounds %class.D* %this, i64 0, i32 1, !dbg !49
+  %c2 = getelementptr inbounds %class.D, %class.D* %d, i64 0, i32 1, !dbg !49
+  %1 = load i32, i32* %c2, align 4, !dbg !49
+  %c23 = getelementptr inbounds %class.D, %class.D* %this, i64 0, i32 1, !dbg !49
   store i32 %1, i32* %c23, align 4, !dbg !49
-  %c3 = getelementptr inbounds %class.D* %d, i64 0, i32 2, !dbg !50
-  %2 = load i32* %c3, align 4, !dbg !50
-  %c34 = getelementptr inbounds %class.D* %this, i64 0, i32 2, !dbg !50
+  %c3 = getelementptr inbounds %class.D, %class.D* %d, i64 0, i32 2, !dbg !50
+  %2 = load i32, i32* %c3, align 4, !dbg !50
+  %c34 = getelementptr inbounds %class.D, %class.D* %this, i64 0, i32 2, !dbg !50
   store i32 %2, i32* %c34, align 4, !dbg !50
-  %c4 = getelementptr inbounds %class.D* %d, i64 0, i32 3, !dbg !51
-  %3 = load i32* %c4, align 4, !dbg !51
-  %c45 = getelementptr inbounds %class.D* %this, i64 0, i32 3, !dbg !51
+  %c4 = getelementptr inbounds %class.D, %class.D* %d, i64 0, i32 3, !dbg !51
+  %3 = load i32, i32* %c4, align 4, !dbg !51
+  %c45 = getelementptr inbounds %class.D, %class.D* %this, i64 0, i32 3, !dbg !51
   store i32 %3, i32* %c45, align 4, !dbg !51
   ret void, !dbg !52
 }
@@ -62,51 +62,47 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!54}
 
-!0 = !{!"0x11\004\00clang version 3.2 (trunk 167506) (llvm/trunk 167505)\001\00\000\00\000", !53, !1, !1, !3, !1,  !1} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/foo.cpp] [DW_LANG_C_plus_plus]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.2 (trunk 167506) (llvm/trunk 167505)", isOptimized: true, emissionKind: 0, file: !53, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports:  !1)
 !1 = !{}
 !3 = !{!5, !31}
-!5 = !{!"0x2e\00D\00D\00_ZN1DC2Ev\0012\000\001\000\006\00256\001\0012", !6, null, !7, null, void (%class.D*)* @_ZN1DC2Ev, null, !17, !27} ; [ DW_TAG_subprogram ] [line 12] [def] [D]
-!6 = !{!"0x29", !53} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "D", linkageName: "_ZN1DC2Ev", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 12, file: !6, scope: null, type: !7, function: void (%class.D*)* @_ZN1DC2Ev, declaration: !17, variables: !27)
+!6 = !DIFile(filename: "foo.cpp", directory: "/usr/local/google/home/echristo")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9}
-!9 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !10} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from D]
-!10 = !{!"0x2\00D\001\00128\0032\000\000\000", !53, null, null, !11, null, null, null} ; [ DW_TAG_class_type ] [D] [line 1, size 128, align 32, offset 0] [def] [from ]
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_class_type, name: "D", line: 1, size: 128, align: 32, file: !53, elements: !11)
 !11 = !{!12, !14, !15, !16, !17, !20}
-!12 = !{!"0xd\00c1\006\0032\0032\000\001", !53, !10, !13} ; [ DW_TAG_member ] [c1] [line 6, size 32, align 32, offset 0] [private] [from int]
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!14 = !{!"0xd\00c2\007\0032\0032\0032\001", !53, !10, !13} ; [ DW_TAG_member ] [c2] [line 7, size 32, align 32, offset 32] [private] [from int]
-!15 = !{!"0xd\00c3\008\0032\0032\0064\001", !53, !10, !13} ; [ DW_TAG_member ] [c3] [line 8, size 32, align 32, offset 64] [private] [from int]
-!16 = !{!"0xd\00c4\009\0032\0032\0096\001", !53, !10, !13} ; [ DW_TAG_member ] [c4] [line 9, size 32, align 32, offset 96] [private] [from int]
-!17 = !{!"0x2e\00D\00D\00\003\000\000\000\006\00256\001\003", !6, !10, !7, null, null, null, i32 0, !18} ; [ DW_TAG_subprogram ] [line 3] [D]
-!18 = !{!19}
-!19 = !{!"0x24"}                      ; [ DW_TAG_base_type ] [line 0, size 0, align 0, offset 0]
-!20 = !{!"0x2e\00D\00D\00\004\000\000\000\006\00256\001\004", !6, !10, !21, null, null, null, i32 0, !25} ; [ DW_TAG_subprogram ] [line 4] [D]
-!21 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !22, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "c1", line: 6, size: 32, align: 32, flags: DIFlagPrivate, file: !53, scope: !10, baseType: !13)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!14 = !DIDerivedType(tag: DW_TAG_member, name: "c2", line: 7, size: 32, align: 32, offset: 32, flags: DIFlagPrivate, file: !53, scope: !10, baseType: !13)
+!15 = !DIDerivedType(tag: DW_TAG_member, name: "c3", line: 8, size: 32, align: 32, offset: 64, flags: DIFlagPrivate, file: !53, scope: !10, baseType: !13)
+!16 = !DIDerivedType(tag: DW_TAG_member, name: "c4", line: 9, size: 32, align: 32, offset: 96, flags: DIFlagPrivate, file: !53, scope: !10, baseType: !13)
+!17 = !DISubprogram(name: "D", line: 3, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !6, scope: !10, type: !7)
+!20 = !DISubprogram(name: "D", line: 4, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 4, file: !6, scope: !10, type: !21)
+!21 = !DISubroutineType(types: !22)
 !22 = !{null, !9, !23}
-!23 = !{!"0x10\00\000\000\000\000\000", null, null, !24} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from ]
-!24 = !{!"0x26\00\000\000\000\000\000", null, null, !10} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from D]
-!25 = !{!26}
-!26 = !{!"0x24"}                      ; [ DW_TAG_base_type ] [line 0, size 0, align 0, offset 0]
+!23 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !24)
+!24 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !10)
 !27 = !{!29}
-!29 = !{!"0x101\00this\0016777228\001088", !5, !6, !30} ; [ DW_TAG_arg_variable ] [this] [line 12]
-!30 = !{!"0xf\00\000\0064\0064\000\000", null, null, !10} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from D]
-!31 = !{!"0x2e\00D\00D\00_ZN1DC2ERKS_\0019\000\001\000\006\00256\001\0019", !6, null, !21, null, void (%class.D*, %class.D*)* @_ZN1DC2ERKS_, null, !20, !32} ; [ DW_TAG_subprogram ] [line 19] [def] [D]
+!29 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 12, arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !5, file: !6, type: !30)
+!30 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !10)
+!31 = !DISubprogram(name: "D", linkageName: "_ZN1DC2ERKS_", line: 19, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 19, file: !6, scope: null, type: !21, function: void (%class.D*, %class.D*)* @_ZN1DC2ERKS_, declaration: !20, variables: !32)
 !32 = !{!34, !35}
-!34 = !{!"0x101\00this\0016777235\001088", !31, !6, !30} ; [ DW_TAG_arg_variable ] [this] [line 19]
-!35 = !{!"0x101\00d\0033554451\000", !31, !6, !23} ; [ DW_TAG_arg_variable ] [d] [line 19]
-!36 = !MDLocation(line: 12, scope: !5)
-!37 = !MDLocation(line: 13, scope: !38)
-!38 = !{!"0xb\0012\000\000", !6, !5} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/foo.cpp]
-!42 = !MDLocation(line: 14, scope: !38)
-!43 = !MDLocation(line: 15, scope: !38)
-!44 = !MDLocation(line: 16, scope: !38)
-!45 = !MDLocation(line: 17, scope: !38)
-!46 = !MDLocation(line: 19, scope: !31)
-!47 = !MDLocation(line: 20, scope: !48)
-!48 = !{!"0xb\0019\000\001", !6, !31} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/foo.cpp]
-!49 = !MDLocation(line: 21, scope: !48)
-!50 = !MDLocation(line: 22, scope: !48)
-!51 = !MDLocation(line: 23, scope: !48)
-!52 = !MDLocation(line: 24, scope: !48)
-!53 = !{!"foo.cpp", !"/usr/local/google/home/echristo"}
-!54 = !{i32 1, !"Debug Info Version", i32 2}
+!34 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 19, arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !31, file: !6, type: !30)
+!35 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "d", line: 19, arg: 2, scope: !31, file: !6, type: !23)
+!36 = !DILocation(line: 12, scope: !5)
+!37 = !DILocation(line: 13, scope: !38)
+!38 = distinct !DILexicalBlock(line: 12, column: 0, file: !6, scope: !5)
+!42 = !DILocation(line: 14, scope: !38)
+!43 = !DILocation(line: 15, scope: !38)
+!44 = !DILocation(line: 16, scope: !38)
+!45 = !DILocation(line: 17, scope: !38)
+!46 = !DILocation(line: 19, scope: !31)
+!47 = !DILocation(line: 20, scope: !48)
+!48 = distinct !DILexicalBlock(line: 19, column: 0, file: !6, scope: !31)
+!49 = !DILocation(line: 21, scope: !48)
+!50 = !DILocation(line: 22, scope: !48)
+!51 = !DILocation(line: 23, scope: !48)
+!52 = !DILocation(line: 24, scope: !48)
+!53 = !DIFile(filename: "foo.cpp", directory: "/usr/local/google/home/echristo")
+!54 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/empty-and-one-elem-array.ll b/test/DebugInfo/X86/empty-and-one-elem-array.ll
index 94e75e4d8bfa..1250b9c64412 100644
--- a/test/DebugInfo/X86/empty-and-one-elem-array.ll
+++ b/test/DebugInfo/X86/empty-and-one-elem-array.ll
@@ -9,16 +9,16 @@ define i32 @func() nounwind uwtable ssp {
 entry:
   %my_foo = alloca %struct.foo, align 4
   %my_bar = alloca %struct.bar, align 4
-  call void @llvm.dbg.declare(metadata %struct.foo* %my_foo, metadata !10, metadata !{!"0x102"}), !dbg !19
-  call void @llvm.dbg.declare(metadata %struct.bar* %my_bar, metadata !20, metadata !{!"0x102"}), !dbg !28
-  %a = getelementptr inbounds %struct.foo* %my_foo, i32 0, i32 0, !dbg !29
+  call void @llvm.dbg.declare(metadata %struct.foo* %my_foo, metadata !10, metadata !DIExpression()), !dbg !19
+  call void @llvm.dbg.declare(metadata %struct.bar* %my_bar, metadata !20, metadata !DIExpression()), !dbg !28
+  %a = getelementptr inbounds %struct.foo, %struct.foo* %my_foo, i32 0, i32 0, !dbg !29
   store i32 3, i32* %a, align 4, !dbg !29
-  %a1 = getelementptr inbounds %struct.bar* %my_bar, i32 0, i32 0, !dbg !30
+  %a1 = getelementptr inbounds %struct.bar, %struct.bar* %my_bar, i32 0, i32 0, !dbg !30
   store i32 5, i32* %a1, align 4, !dbg !30
-  %a2 = getelementptr inbounds %struct.foo* %my_foo, i32 0, i32 0, !dbg !31
-  %0 = load i32* %a2, align 4, !dbg !31
-  %a3 = getelementptr inbounds %struct.bar* %my_bar, i32 0, i32 0, !dbg !31
-  %1 = load i32* %a3, align 4, !dbg !31
+  %a2 = getelementptr inbounds %struct.foo, %struct.foo* %my_foo, i32 0, i32 0, !dbg !31
+  %0 = load i32, i32* %a2, align 4, !dbg !31
+  %a3 = getelementptr inbounds %struct.bar, %struct.bar* %my_bar, i32 0, i32 0, !dbg !31
+  %1 = load i32, i32* %a3, align 4, !dbg !31
   %add = add nsw i32 %0, %1, !dbg !31
   ret i32 %add, !dbg !31
 }
@@ -63,35 +63,35 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!33}
 
-!0 = !{!"0x11\0012\00clang version 3.3 (trunk 169136)\000\00\000\00\000", !32, !1, !1, !3, !1,  !1} ; [ DW_TAG_compile_unit ] [/Volumes/Sandbox/llvm/test.c] [DW_LANG_C99]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.3 (trunk 169136)", isOptimized: false, emissionKind: 0, file: !32, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00func\00func\00\0011\000\001\000\006\000\000\0011", !6, !6, !7, null, i32 ()* @func, null, null, !1} ; [ DW_TAG_subprogram ] [line 11] [def] [func]
-!6 = !{!"0x29", !32} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "func", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 11, file: !6, scope: !6, type: !7, function: i32 ()* @func, variables: !1)
+!6 = !DIFile(filename: "test.c", directory: "/Volumes/Sandbox/llvm")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"0x100\00my_foo\0012\000", !11, !6, !12} ; [ DW_TAG_auto_variable ] [my_foo] [line 12]
-!11 = !{!"0xb\0011\000\000", !6, !5} ; [ DW_TAG_lexical_block ] [/Volumes/Sandbox/llvm/test.c]
-!12 = !{!"0x13\00foo\001\0064\0032\000\000\000", !32, null, null, !13, null, i32 0, null} ; [ DW_TAG_structure_type ] [foo] [line 1, size 64, align 32, offset 0] [def] [from ]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "my_foo", line: 12, scope: !11, file: !6, type: !12)
+!11 = distinct !DILexicalBlock(line: 11, column: 0, file: !6, scope: !5)
+!12 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo", line: 1, size: 64, align: 32, file: !32, elements: !13)
 !13 = !{!14, !15}
-!14 = !{!"0xd\00a\002\0032\0032\000\000", !32, !12, !9} ; [ DW_TAG_member ] [a] [line 2, size 32, align 32, offset 0] [from int]
-!15 = !{!"0xd\00b\003\0032\0032\0032\000", !32, !12, !16} ; [ DW_TAG_member ] [b] [line 3, size 32, align 32, offset 32] [from ]
-!16 = !{!"0x1\00\000\0032\0032\000\000", null, null, !9, !17, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 32, align 32, offset 0] [from int]
+!14 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 2, size: 32, align: 32, file: !32, scope: !12, baseType: !9)
+!15 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 3, size: 32, align: 32, offset: 32, file: !32, scope: !12, baseType: !16)
+!16 = !DICompositeType(tag: DW_TAG_array_type, size: 32, align: 32, baseType: !9, elements: !17)
 !17 = !{!18}
-!18 = !{!"0x21\000\001"} ; [ DW_TAG_subrange_type ] [0, 1]
-!19 = !MDLocation(line: 12, scope: !11)
-!20 = !{!"0x100\00my_bar\0013\000", !11, !6, !21} ; [ DW_TAG_auto_variable ] [my_bar] [line 13]
-!21 = !{!"0x13\00bar\006\0032\0032\000\000\000", !32, null, null, !22, null, i32 0, null} ; [ DW_TAG_structure_type ] [bar] [line 6, size 32, align 32, offset 0] [def] [from ]
+!18 = !DISubrange(count: 1)
+!19 = !DILocation(line: 12, scope: !11)
+!20 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "my_bar", line: 13, scope: !11, file: !6, type: !21)
+!21 = !DICompositeType(tag: DW_TAG_structure_type, name: "bar", line: 6, size: 32, align: 32, file: !32, elements: !22)
 !22 = !{!23, !24}
-!23 = !{!"0xd\00a\007\0032\0032\000\000", !32, !21, !9} ; [ DW_TAG_member ] [a] [line 7, size 32, align 32, offset 0] [from int]
-!24 = !{!"0xd\00b\008\000\0032\0032\000", !32, !21, !25} ; [ DW_TAG_member ] [b] [line 8, size 0, align 32, offset 32] [from ]
-!25 = !{!"0x1\00\000\000\0032\000\000", null, null, !9, !26, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 0, align 32, offset 0] [from int]
+!23 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 7, size: 32, align: 32, file: !32, scope: !21, baseType: !9)
+!24 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 8, align: 32, offset: 32, file: !32, scope: !21, baseType: !25)
+!25 = !DICompositeType(tag: DW_TAG_array_type, align: 32, baseType: !9, elements: !26)
 !26 = !{!27}
-!27 = !{!"0x21\000\000"} ; [ DW_TAG_subrange_type ] [0, 0]
-!28 = !MDLocation(line: 13, scope: !11)
-!29 = !MDLocation(line: 15, scope: !11)
-!30 = !MDLocation(line: 16, scope: !11)
-!31 = !MDLocation(line: 17, scope: !11)
-!32 = !{!"test.c", !"/Volumes/Sandbox/llvm"}
-!33 = !{i32 1, !"Debug Info Version", i32 2}
+!27 = !DISubrange(count: 0)
+!28 = !DILocation(line: 13, scope: !11)
+!29 = !DILocation(line: 15, scope: !11)
+!30 = !DILocation(line: 16, scope: !11)
+!31 = !DILocation(line: 17, scope: !11)
+!32 = !DIFile(filename: "test.c", directory: "/Volumes/Sandbox/llvm")
+!33 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/empty-array.ll b/test/DebugInfo/X86/empty-array.ll
index d5a521acd3bb..ce460a783c05 100644
--- a/test/DebugInfo/X86/empty-array.ll
+++ b/test/DebugInfo/X86/empty-array.ll
@@ -27,23 +27,21 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!21}
 
-!0 = !{!"0x11\004\00clang version 3.3 (trunk 169136)\000\00\000\00\000", !20, !1, !1, !1, !3,  !1} ; [ DW_TAG_compile_unit ] [/Volumes/Sandbox/llvm/t.cpp] [DW_LANG_C_plus_plus]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 (trunk 169136)", isOptimized: false, emissionKind: 0, file: !20, enums: !1, retainedTypes: !1, subprograms: !1, globals: !3, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x34\00a\00a\00\001\000\001", null, !6, !7, %class.A* @a, null} ; [ DW_TAG_variable ] [a] [line 1] [def]
-!6 = !{!"0x29", !20} ; [ DW_TAG_file_type ]
-!7 = !{!"0x2\00A\001\000\0032\000\000\000", !20, null, null, !8, null, null, null} ; [ DW_TAG_class_type ] [A] [line 1, size 0, align 32, offset 0] [def] [from ]
+!5 = !DIGlobalVariable(name: "a", line: 1, isLocal: false, isDefinition: true, scope: null, file: !6, type: !7, variable: %class.A* @a)
+!6 = !DIFile(filename: "t.cpp", directory: "/Volumes/Sandbox/llvm")
+!7 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 1, align: 32, file: !20, elements: !8)
 !8 = !{!9, !14}
-!9 = !{!"0xd\00x\001\000\000\000\001", !20, !7, !10} ; [ DW_TAG_member ] [x] [line 1, size 0, align 0, offset 0] [private] [from ]
-!10 = !{!"0x1\00\000\000\0032\000\000", null, null, !11, !12, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 0, align 32, offset 0] [from int]
-!11 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 1, flags: DIFlagPrivate, file: !20, scope: !7, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_array_type, align: 32, baseType: !11, elements: !12)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !12 = !{!13}
-!13 = !{!"0x21\000\00-1"} ; [ DW_TAG_subrange_type ] [unbound]
-!14 = !{!"0x2e\00A\00A\00\001\000\000\000\006\00320\000\001", !6, !7, !15, null, null, null, i32 0, !18} ; [ DW_TAG_subprogram ] [line 1] [A]
-!15 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DISubrange(count: -1)
+!14 = !DISubprogram(name: "A", line: 1, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !6, scope: !7, type: !15)
+!15 = !DISubroutineType(types: !16)
 !16 = !{null, !17}
-!17 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !7} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from A]
-!18 = !{!19}
-!19 = !{!"0x24"}                      ; [ DW_TAG_base_type ] [line 0, size 0, align 0, offset 0]
-!20 = !{!"t.cpp", !"/Volumes/Sandbox/llvm"}
-!21 = !{i32 1, !"Debug Info Version", i32 2}
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !7)
+!20 = !DIFile(filename: "t.cpp", directory: "/Volumes/Sandbox/llvm")
+!21 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/empty.ll b/test/DebugInfo/X86/empty.ll
new file mode 100644
index 000000000000..1f48a2f21246
--- /dev/null
+++ b/test/DebugInfo/X86/empty.ll
@@ -0,0 +1,26 @@
+; RUN: llc -mtriple i686-pc-cygwin < %s -filetype=obj | llvm-dwarfdump - | FileCheck %s
+; RUN: llc -mtriple i686-pc-cygwin -split-dwarf=Enable < %s -filetype=obj | llvm-dwarfdump - | FileCheck --check-prefix=FISSION %s
+
+; Expect no line table entry since there are no functions and file references in this compile unit
+; CHECK: .debug_line contents:
+; CHECK: Line table prologue:
+; CHECK: total_length: 0x00000019
+; CHECK-NOT: file_names[
+
+; CHECK: .debug_pubnames contents:
+; CHECK-NOT: Offset
+
+; CHECK: .debug_pubtypes contents:
+; CHECK-NOT: Offset
+
+; Don't emit DW_AT_addr_base when there are no addresses.
+; FISSION-NOT: DW_AT_GNU_addr_base [DW_FORM_sec_offset]
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!5}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.1 (trunk 143523)", isOptimized: true, emissionKind: 0, file: !4, enums: !2, retainedTypes: !2, subprograms: !2, globals: !2)
+!2 = !{}
+!3 = !DIFile(filename: "empty.c", directory: "/home/nlewycky")
+!4 = !DIFile(filename: "empty.c", directory: "/home/nlewycky")
+!5 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/ending-run.ll b/test/DebugInfo/X86/ending-run.ll
index 0b5c77fea6ec..9e3584615df2 100644
--- a/test/DebugInfo/X86/ending-run.ll
+++ b/test/DebugInfo/X86/ending-run.ll
@@ -13,13 +13,13 @@ entry:
   %x.addr = alloca i32, align 4
   %y = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !12, metadata !{!"0x102"}), !dbg !13
-  call void @llvm.dbg.declare(metadata i32* %y, metadata !14, metadata !{!"0x102"}), !dbg !16
-  %0 = load i32* %x.addr, align 4, !dbg !17
-  %1 = load i32* %x.addr, align 4, !dbg !17
+  call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !12, metadata !DIExpression()), !dbg !13
+  call void @llvm.dbg.declare(metadata i32* %y, metadata !14, metadata !DIExpression()), !dbg !16
+  %0 = load i32, i32* %x.addr, align 4, !dbg !17
+  %1 = load i32, i32* %x.addr, align 4, !dbg !17
   %mul = mul nsw i32 %0, %1, !dbg !17
   store i32 %mul, i32* %y, align 4, !dbg !17
-  %2 = load i32* %y, align 4, !dbg !18
+  %2 = load i32, i32* %y, align 4, !dbg !18
   %sub = sub nsw i32 %2, 2, !dbg !18
   ret i32 %sub, !dbg !18
 }
@@ -29,20 +29,20 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!20}
 
-!0 = !{!"0x11\0012\00clang version 3.1 (trunk 153921) (llvm/trunk 153916)\000\00\000\00\000", !19, !1, !1, !3, !1,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.1 (trunk 153921) (llvm/trunk 153916)", isOptimized: false, emissionKind: 0, file: !19, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00callee\00callee\00\004\000\001\000\006\000\000\007", !19, !6, !7, null, i32 (i32)* @callee, null, null, null} ; [ DW_TAG_subprogram ]
-!6 = !{!"0x29", !19} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "callee", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 7, file: !19, scope: !6, type: !7, function: i32 (i32)* @callee)
+!6 = !DIFile(filename: "ending-run.c", directory: "/Users/echristo/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!12 = !{!"0x101\00x\0016777221\000", !5, !6, !9} ; [ DW_TAG_arg_variable ]
-!13 = !MDLocation(line: 5, column: 5, scope: !5)
-!14 = !{!"0x100\00y\008\000", !15, !6, !9} ; [ DW_TAG_auto_variable ]
-!15 = !{!"0xb\007\001\000", !19, !5} ; [ DW_TAG_lexical_block ]
-!16 = !MDLocation(line: 8, column: 9, scope: !15)
-!17 = !MDLocation(line: 8, column: 18, scope: !15)
-!18 = !MDLocation(line: 9, column: 5, scope: !15)
-!19 = !{!"ending-run.c", !"/Users/echristo/tmp"}
-!20 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 5, arg: 1, scope: !5, file: !6, type: !9)
+!13 = !DILocation(line: 5, column: 5, scope: !5)
+!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y", line: 8, scope: !15, file: !6, type: !9)
+!15 = distinct !DILexicalBlock(line: 7, column: 1, file: !19, scope: !5)
+!16 = !DILocation(line: 8, column: 9, scope: !15)
+!17 = !DILocation(line: 8, column: 18, scope: !15)
+!18 = !DILocation(line: 9, column: 5, scope: !15)
+!19 = !DIFile(filename: "ending-run.c", directory: "/Users/echristo/tmp")
+!20 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/enum-class.ll b/test/DebugInfo/X86/enum-class.ll
index c2975a9d521e..57b2aa404cbb 100644
--- a/test/DebugInfo/X86/enum-class.ll
+++ b/test/DebugInfo/X86/enum-class.ll
@@ -8,26 +8,26 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!23}
 
-!0 = !{!"0x11\004\00clang version 3.2 (trunk 157269) (llvm/trunk 157264)\000\00\000\00\000", !22, !1, !15, !15, !17,  !15} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.2 (trunk 157269) (llvm/trunk 157264)", isOptimized: false, emissionKind: 0, file: !22, enums: !1, retainedTypes: !15, subprograms: !15, globals: !17, imports:  !15)
 !1 = !{!3, !8, !12}
-!3 = !{!"0x4\00A\001\0032\0032\000\000\000", !4, null, !5, !6, null, null, null} ; [ DW_TAG_enumeration_type ] [A] [line 1, size 32, align 32, offset 0] [def] [from int]
-!4 = !{!"0x29", !22} ; [ DW_TAG_file_type ]
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
+!3 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "A", line: 1, size: 32, align: 32, file: !4, baseType: !5, elements: !6)
+!4 = !DIFile(filename: "foo.cpp", directory: "/Users/echristo/tmp")
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !6 = !{!7}
-!7 = !{!"0x28\00A1\001"} ; [ DW_TAG_enumerator ]
-!8 = !{!"0x4\00B\002\0064\0064\000\000\000", !4, null, !9, !10, null, null, null} ; [ DW_TAG_enumeration_type ] [B] [line 2, size 64, align 64, offset 0] [def] [from long unsigned int]
-!9 = !{!"0x24\00long unsigned int\000\0064\0064\000\000\007", null, null} ; [ DW_TAG_base_type ]
+!7 = !DIEnumerator(name: "A1", value: 1) ; [ DW_TAG_enumerator ]
+!8 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "B", line: 2, size: 64, align: 64, file: !4, baseType: !9, elements: !10)
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "long unsigned int", size: 64, align: 64, encoding: DW_ATE_unsigned)
 !10 = !{!11}
-!11 = !{!"0x28\00B1\001"} ; [ DW_TAG_enumerator ]
-!12 = !{!"0x4\00C\003\0032\0032\000\000\000", !4, null, null, !13, null, null, null} ; [ DW_TAG_enumeration_type ] [C] [line 3, size 32, align 32, offset 0] [def] [from ]
+!11 = !DIEnumerator(name: "B1", value: 1) ; [ DW_TAG_enumerator ]
+!12 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "C", line: 3, size: 32, align: 32, file: !4, elements: !13)
 !13 = !{!14}
-!14 = !{!"0x28\00C1\001"} ; [ DW_TAG_enumerator ]
+!14 = !DIEnumerator(name: "C1", value: 1) ; [ DW_TAG_enumerator ]
 !15 = !{}
 !17 = !{!19, !20, !21}
-!19 = !{!"0x34\00a\00a\00\004\000\001", null, !4, !3, i32* @a, null} ; [ DW_TAG_variable ]
-!20 = !{!"0x34\00b\00b\00\005\000\001", null, !4, !8, i64* @b, null} ; [ DW_TAG_variable ]
-!21 = !{!"0x34\00c\00c\00\006\000\001", null, !4, !12, i32* @c, null} ; [ DW_TAG_variable ]
-!22 = !{!"foo.cpp", !"/Users/echristo/tmp"}
+!19 = !DIGlobalVariable(name: "a", line: 4, isLocal: false, isDefinition: true, scope: null, file: !4, type: !3, variable: i32* @a)
+!20 = !DIGlobalVariable(name: "b", line: 5, isLocal: false, isDefinition: true, scope: null, file: !4, type: !8, variable: i64* @b)
+!21 = !DIGlobalVariable(name: "c", line: 6, isLocal: false, isDefinition: true, scope: null, file: !4, type: !12, variable: i32* @c)
+!22 = !DIFile(filename: "foo.cpp", directory: "/Users/echristo/tmp")
 
 ; CHECK: DW_TAG_enumeration_type [{{.*}}]
 ; CHECK: DW_AT_type [DW_FORM_ref4]
@@ -42,4 +42,4 @@
 ; CHECK: DW_TAG_enumeration_type [6]
 ; CHECK-NOT: DW_AT_enum_class
 ; CHECK: DW_AT_name [DW_FORM_strp]      ( .debug_str[{{.*}}] = "C")
-!23 = !{i32 1, !"Debug Info Version", i32 2}
+!23 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/enum-fwd-decl.ll b/test/DebugInfo/X86/enum-fwd-decl.ll
index 832fdb0673fd..f5deeb7d6712 100644
--- a/test/DebugInfo/X86/enum-fwd-decl.ll
+++ b/test/DebugInfo/X86/enum-fwd-decl.ll
@@ -6,16 +6,16 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!9}
 
-!0 = !{!"0x11\004\00clang version 3.2 (trunk 165274) (llvm/trunk 165272)\000\00\000\00\000", !8, !1, !1, !1, !3,  !1} ; [ DW_TAG_compile_unit ] [/tmp/foo.cpp] [DW_LANG_C_plus_plus]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.2 (trunk 165274) (llvm/trunk 165272)", isOptimized: false, emissionKind: 0, file: !8, enums: !1, retainedTypes: !1, subprograms: !1, globals: !3, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x34\00e\00e\00\002\000\001", null, !6, !7, i16* @e, null} ; [ DW_TAG_variable ] [e] [line 2] [def]
-!6 = !{!"0x29", !8} ; [ DW_TAG_file_type ]
-!7 = !{!"0x4\00E\001\0016\0016\000\004\000", !8, null, null, null, null, null, null} ; [ DW_TAG_enumeration_type ] [E] [line 1, size 16, align 16, offset 0] [decl] [from ]
-!8 = !{!"foo.cpp", !"/tmp"}
+!5 = !DIGlobalVariable(name: "e", line: 2, isLocal: false, isDefinition: true, scope: null, file: !6, type: !7, variable: i16* @e)
+!6 = !DIFile(filename: "foo.cpp", directory: "/tmp")
+!7 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "E", line: 1, size: 16, align: 16, flags: DIFlagFwdDecl, file: !8)
+!8 = !DIFile(filename: "foo.cpp", directory: "/tmp")
 
 ; CHECK: DW_TAG_enumeration_type
 ; CHECK-NEXT: DW_AT_name
 ; CHECK-NEXT: DW_AT_byte_size
 ; CHECK-NEXT: DW_AT_declaration
-!9 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/fission-cu.ll b/test/DebugInfo/X86/fission-cu.ll
index f1ee0fe33afa..493f84283e2e 100644
--- a/test/DebugInfo/X86/fission-cu.ll
+++ b/test/DebugInfo/X86/fission-cu.ll
@@ -8,13 +8,13 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!9}
 
-!0 = !{!"0x11\0012\00clang version 3.3 (trunk 169021) (llvm/trunk 169020)\000\00\000\00baz.dwo\000", !8, !1, !1, !1, !3,  !1} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/baz.c] [DW_LANG_C99]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.3 (trunk 169021) (llvm/trunk 169020)", isOptimized: false, splitDebugFilename: "baz.dwo", emissionKind: 0, file: !8, enums: !1, retainedTypes: !1, subprograms: !1, globals: !3, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x34\00a\00a\00\001\000\001", null, !6, !7, i32* @a, null} ; [ DW_TAG_variable ] [a] [line 1] [def]
-!6 = !{!"0x29", !8} ; [ DW_TAG_file_type ]
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!8 = !{!"baz.c", !"/usr/local/google/home/echristo/tmp"}
+!5 = !DIGlobalVariable(name: "a", line: 1, isLocal: false, isDefinition: true, scope: null, file: !6, type: !7, variable: i32* @a)
+!6 = !DIFile(filename: "baz.c", directory: "/usr/local/google/home/echristo/tmp")
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DIFile(filename: "baz.c", directory: "/usr/local/google/home/echristo/tmp")
 
 ; Check that the skeleton compile unit contains the proper attributes:
 ; This DIE has the following attributes: DW_AT_comp_dir, DW_AT_stmt_list,
@@ -111,4 +111,4 @@
 ; HDR-NOT: .debug_aranges
 ; HDR-NOT: .rela.{{.*}}.dwo
 
-!9 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/fission-hash.ll b/test/DebugInfo/X86/fission-hash.ll
index 5002ac63485e..74764416d748 100644
--- a/test/DebugInfo/X86/fission-hash.ll
+++ b/test/DebugInfo/X86/fission-hash.ll
@@ -9,8 +9,8 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!3, !4}
 
-!0 = !{!"0x11\0012\00clang version 3.4 (trunk 188230) (llvm/trunk 188234)\000\00\000\00foo.dwo\000", !1, !2, !2, !2, !2, !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/foo.c] [DW_LANG_C99]
-!1 = !{!"foo.c", !"/usr/local/google/home/echristo/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 188230) (llvm/trunk 188234)", isOptimized: false, splitDebugFilename: "foo.dwo", emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !2, imports: !2)
+!1 = !DIFile(filename: "foo.c", directory: "/usr/local/google/home/echristo/tmp")
 !2 = !{}
 !3 = !{i32 2, !"Dwarf Version", i32 3}
-!4 = !{i32 1, !"Debug Info Version", i32 2}
+!4 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/fission-inline.ll b/test/DebugInfo/X86/fission-inline.ll
index 64999669c5be..53e782756ca8 100644
--- a/test/DebugInfo/X86/fission-inline.ll
+++ b/test/DebugInfo/X86/fission-inline.ll
@@ -1,4 +1,6 @@
-; RUN: llc -split-dwarf=Enable -O0 < %s -mtriple=x86_64-unknown-linux-gnu -filetype=obj | llvm-dwarfdump -debug-dump=info - | FileCheck %s
+; RUN: llc -split-dwarf=Enable -O0 < %s -mtriple=x86_64-unknown-linux-gnu -filetype=obj > %t
+; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s
+; RUN: llvm-objdump -r %t | FileCheck --check-prefix=RELOCS %s
 
 ; Test the emission of gmlt-like inlining information into the skeleton unit.
 ; This allows inline-aware symbolication/backtracing given only the linked
@@ -65,10 +67,13 @@
 ; CHECK:        DW_TAG_inlined_subroutine
 ; CHECK-NEXT:     DW_AT_abstract_origin {{.*}} "f2<int>"
 ; CHECK-NEXT:     DW_AT_ranges
-; CHECK-NEXT:     DW_AT_call_file
+; CHECK-NOT: {{DW_AT|DW_TAG|NULL}}
+; CHECK:     DW_AT_call_file
 ; CHECK-NEXT:     DW_AT_call_line {{.*}} (18)
 ; CHECK-NOT: DW_
 
+; RELOCS-NOT: RELOCATION RECORDS FOR [.rela.debug_ranges]
+
 ; Function Attrs: uwtable
 define void @_ZN3foo2f3Ez(...) #0 align 2 {
 entry:
@@ -87,33 +92,33 @@ attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n
 !llvm.module.flags = !{!22, !23}
 !llvm.ident = !{!24}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 \000\00\000\00fission-inline.dwo\001", !1, !2, !3, !9, !2, !18} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/fission-inline.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"fission-inline.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 ", isOptimized: false, splitDebugFilename: "fission-inline.dwo", emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !9, globals: !2, imports: !18)
+!1 = !DIFile(filename: "fission-inline.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00foo\001\008\008\000\000\000", !1, null, null, !5, null, null, !"_ZTS3foo"} ; [ DW_TAG_structure_type ] [foo] [line 1, size 8, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo", line: 1, size: 8, align: 8, file: !1, elements: !5, identifier: "_ZTS3foo")
 !5 = !{!6}
-!6 = !{!"0x2e\00f3\00f3\00_ZN3foo2f3Ez\004\000\000\000\000\00256\000\004", !1, !"_ZTS3foo", !7, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 4] [f3]
-!7 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DISubprogram(name: "f3", linkageName: "_ZN3foo2f3Ez", line: 4, isLocal: false, isDefinition: false, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !1, scope: !"_ZTS3foo", type: !7)
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, null}
 !9 = !{!10, !11}
-!10 = !{!"0x2e\00f3\00f3\00_ZN3foo2f3Ez\0015\000\001\000\000\00256\000\0015", !1, !"_ZTS3foo", !7, null, void (...)* @_ZN3foo2f3Ez, null, !6, !2} ; [ DW_TAG_subprogram ] [line 15] [def] [f3]
-!11 = !{!"0x2e\00f2<int>\00f2<int>\00_ZN3foo2f2IiEEvv\0010\000\001\000\000\00256\000\0010", !1, !"_ZTS3foo", !12, null, null, !14, !17, !2} ; [ DW_TAG_subprogram ] [line 10] [def] [f2<int>]
-!12 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !13, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!10 = !DISubprogram(name: "f3", linkageName: "_ZN3foo2f3Ez", line: 15, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 15, file: !1, scope: !"_ZTS3foo", type: !7, function: void (...)* @_ZN3foo2f3Ez, declaration: !6, variables: !2)
+!11 = !DISubprogram(name: "f2<int>", linkageName: "_ZN3foo2f2IiEEvv", line: 10, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 10, file: !1, scope: !"_ZTS3foo", type: !12, templateParams: !14, declaration: !17, variables: !2)
+!12 = !DISubroutineType(types: !13)
 !13 = !{null}
 !14 = !{!15}
-!15 = !{!"0x2f\00T\000\000", null, !16, null} ; [ DW_TAG_template_type_parameter ]
-!16 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!17 = !{!"0x2e\00f2<int>\00f2<int>\00_ZN3foo2f2IiEEvv\0010\000\000\000\000\00256\000\0010", !1, !"_ZTS3foo", !12, null, null, !14, null, null} ; [ DW_TAG_subprogram ] [line 10] [f2<int>]
+!15 = !DITemplateTypeParameter(name: "T", type: !16)
+!16 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!17 = !DISubprogram(name: "f2<int>", linkageName: "_ZN3foo2f2IiEEvv", line: 10, isLocal: false, isDefinition: false, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 10, file: !1, scope: !"_ZTS3foo", type: !12, templateParams: !14)
 !18 = !{!19}
-!19 = !{!"0x8\0019\00", !20, !"_ZTS3foo"} ; [ DW_TAG_imported_declaration ]
-!20 = !{!"0xb\0016\0013\001", !1, !21} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/fission-inline.cpp]
-!21 = !{!"0xb\0016\007\000", !1, !10} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/fission-inline.cpp]
+!19 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 19, scope: !20, entity: !"_ZTS3foo")
+!20 = distinct !DILexicalBlock(line: 16, column: 13, file: !1, scope: !21)
+!21 = distinct !DILexicalBlock(line: 16, column: 7, file: !1, scope: !10)
 !22 = !{i32 2, !"Dwarf Version", i32 4}
-!23 = !{i32 2, !"Debug Info Version", i32 2}
+!23 = !{i32 2, !"Debug Info Version", i32 3}
 !24 = !{!"clang version 3.6.0 "}
-!25 = !MDLocation(line: 17, column: 5, scope: !20)
-!26 = !MDLocation(line: 11, column: 3, scope: !11, inlinedAt: !27)
-!27 = !MDLocation(line: 18, column: 5, scope: !20)
-!28 = !MDLocation(line: 12, column: 3, scope: !11, inlinedAt: !27)
-!29 = !MDLocation(line: 21, column: 1, scope: !10)
+!25 = !DILocation(line: 17, column: 5, scope: !20)
+!26 = !DILocation(line: 11, column: 3, scope: !11, inlinedAt: !27)
+!27 = !DILocation(line: 18, column: 5, scope: !20)
+!28 = !DILocation(line: 12, column: 3, scope: !11, inlinedAt: !27)
+!29 = !DILocation(line: 21, column: 1, scope: !10)
diff --git a/test/DebugInfo/X86/fission-ranges.ll b/test/DebugInfo/X86/fission-ranges.ll
index 400998e9126c..e5eb25ce90c7 100644
--- a/test/DebugInfo/X86/fission-ranges.ll
+++ b/test/DebugInfo/X86/fission-ranges.ll
@@ -25,20 +25,20 @@
 ; if they've changed due to a bugfix, change in register allocation, etc.
 
 ; CHECK: [[A]]: Beginning address index: 2
-; CHECK-NEXT:                    Length: 190
+; CHECK-NEXT:                    Length: 169
 ; CHECK-NEXT:      Location description: 11 00
 ; CHECK-NEXT: {{^$}}
 ; CHECK-NEXT:   Beginning address index: 3
-; CHECK-NEXT:                    Length: 23
+; CHECK-NEXT:                    Length: 21
 ; CHECK-NEXT:      Location description: 50 93 04
 ; CHECK: [[E]]: Beginning address index: 4
-; CHECK-NEXT:                    Length: 21
+; CHECK-NEXT:                    Length: 19
 ; CHECK-NEXT:      Location description: 50 93 04
 ; CHECK: [[B]]: Beginning address index: 5
-; CHECK-NEXT:                    Length: 19
+; CHECK-NEXT:                    Length: 17
 ; CHECK-NEXT:      Location description: 50 93 04
 ; CHECK: [[D]]: Beginning address index: 6
-; CHECK-NEXT:                    Length: 23
+; CHECK-NEXT:                    Length: 17
 ; CHECK-NEXT:      Location description: 50 93 04
 
 ; Make sure we don't produce any relocations in any .dwo section (though in particular, debug_info.dwo)
@@ -91,9 +91,9 @@ entry:
 ; Function Attrs: nounwind uwtable
 define internal fastcc void @foo() #0 {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 1, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !30
-  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !31
-  %c.promoted9 = load i32* @c, align 4, !dbg !32, !tbaa !33
+  tail call void @llvm.dbg.value(metadata i32 1, i64 0, metadata !13, metadata !DIExpression()), !dbg !30
+  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !14, metadata !DIExpression()), !dbg !31
+  %c.promoted9 = load i32, i32* @c, align 4, !dbg !32, !tbaa !33
   br label %for.cond1.preheader, !dbg !31
 
 for.cond1.preheader:                              ; preds = %for.inc16, %entry
@@ -114,28 +114,28 @@ for.cond7.preheader:                              ; preds = %for.inc10, %for.con
 for.body9:                                        ; preds = %for.body9, %for.cond7.preheader
   %and2 = phi i32 [ %and.lcssa5, %for.cond7.preheader ], [ %and, %for.body9 ], !dbg !40
   %e.01 = phi i32 [ 0, %for.cond7.preheader ], [ %inc, %for.body9 ]
-  tail call void @llvm.dbg.value(metadata i32* @c, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !40
+  tail call void @llvm.dbg.value(metadata i32* @c, i64 0, metadata !19, metadata !DIExpression()), !dbg !40
   %and = and i32 %and2, 1, !dbg !32
   %inc = add i32 %e.01, 1, !dbg !39
-  tail call void @llvm.dbg.value(metadata i32 %inc, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !39
+  tail call void @llvm.dbg.value(metadata i32 %inc, i64 0, metadata !18, metadata !DIExpression()), !dbg !39
   %exitcond = icmp eq i32 %inc, 30, !dbg !39
   br i1 %exitcond, label %for.inc10, label %for.body9, !dbg !39
 
 for.inc10:                                        ; preds = %for.body9
   %inc11 = add nsw i32 %b.03, 1, !dbg !38
-  tail call void @llvm.dbg.value(metadata i32 %inc11, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !38
+  tail call void @llvm.dbg.value(metadata i32 %inc11, i64 0, metadata !15, metadata !DIExpression()), !dbg !38
   %exitcond11 = icmp eq i32 %inc11, 30, !dbg !38
   br i1 %exitcond11, label %for.inc13, label %for.cond7.preheader, !dbg !38
 
 for.inc13:                                        ; preds = %for.inc10
   %inc14 = add i32 %d.06, 1, !dbg !37
-  tail call void @llvm.dbg.value(metadata i32 %inc14, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !37
+  tail call void @llvm.dbg.value(metadata i32 %inc14, i64 0, metadata !16, metadata !DIExpression()), !dbg !37
   %exitcond12 = icmp eq i32 %inc14, 30, !dbg !37
   br i1 %exitcond12, label %for.inc16, label %for.cond4.preheader, !dbg !37
 
 for.inc16:                                        ; preds = %for.inc13
   %inc17 = add nsw i32 %a.08, 1, !dbg !31
-  tail call void @llvm.dbg.value(metadata i32 %inc17, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !31
+  tail call void @llvm.dbg.value(metadata i32 %inc17, i64 0, metadata !14, metadata !DIExpression()), !dbg !31
   %exitcond13 = icmp eq i32 %inc17, 30, !dbg !31
   br i1 %exitcond13, label %for.end18, label %for.cond1.preheader, !dbg !31
 
@@ -153,48 +153,48 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!26, !43}
 
-!0 = !{!"0x11\0012\00clang version 3.4 (trunk 191700) (llvm/trunk 191710)\001\00\000\00small.dwo\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/small.c] [DW_LANG_C99]
-!1 = !{!"small.c", !"/usr/local/google/home/echristo/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 191700) (llvm/trunk 191710)", isOptimized: true, splitDebugFilename: "small.dwo", emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "small.c", directory: "/usr/local/google/home/echristo/tmp")
 !2 = !{}
 !3 = !{!4, !8}
-!4 = !{!"0x2e\00bar\00bar\00\0018\000\001\000\006\000\001\0019", !1, !5, !6, null, void ()* @bar, null, null, !2} ; [ DW_TAG_subprogram ] [line 18] [def] [scope 19] [bar]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/usr/local/google/home/echristo/tmp/small.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "bar", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 19, file: !1, scope: !5, type: !6, function: void ()* @bar, variables: !2)
+!5 = !DIFile(filename: "small.c", directory: "/usr/local/google/home/echristo/tmp")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
-!8 = !{!"0x2e\00foo\00foo\00\002\001\001\000\006\00256\001\003", !1, !5, !9, null, void ()* @foo, null, null, !12} ; [ DW_TAG_subprogram ] [line 2] [local] [def] [scope 3] [foo]
-!9 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = !DISubprogram(name: "foo", line: 2, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !1, scope: !5, type: !9, function: void ()* @foo, variables: !12)
+!9 = !DISubroutineType(types: !10)
 !10 = !{null, !11}
-!11 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !12 = !{!13, !14, !15, !16, !18, !19}
-!13 = !{!"0x101\00p\0016777218\000", !8, !5, !11} ; [ DW_TAG_arg_variable ] [p] [line 2]
-!14 = !{!"0x100\00a\004\000", !8, !5, !11} ; [ DW_TAG_auto_variable ] [a] [line 4]
-!15 = !{!"0x100\00b\004\000", !8, !5, !11} ; [ DW_TAG_auto_variable ] [b] [line 4]
-!16 = !{!"0x100\00d\005\000", !8, !5, !17} ; [ DW_TAG_auto_variable ] [d] [line 5]
-!17 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, null} ; [ DW_TAG_base_type ] [unsigned int] [line 0, size 32, align 32, offset 0, enc DW_ATE_unsigned]
-!18 = !{!"0x100\00e\005\000", !8, !5, !17} ; [ DW_TAG_auto_variable ] [e] [line 5]
-!19 = !{!"0x100\00w\0012\000", !20, !5, !25} ; [ DW_TAG_auto_variable ] [w] [line 12]
-!20 = !{!"0xb\0011\000\004", !1, !21} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/small.c]
-!21 = !{!"0xb\0010\000\003", !1, !22} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/small.c]
-!22 = !{!"0xb\009\000\002", !1, !23} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/small.c]
-!23 = !{!"0xb\008\000\001", !1, !24} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/small.c]
-!24 = !{!"0xb\007\000\000", !1, !8} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/small.c]
-!25 = !{!"0xf\00\000\0064\0064\000\000", null, null, !11} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p", line: 2, arg: 1, scope: !8, file: !5, type: !11)
+!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 4, scope: !8, file: !5, type: !11)
+!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 4, scope: !8, file: !5, type: !11)
+!16 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "d", line: 5, scope: !8, file: !5, type: !17)
+!17 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!18 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "e", line: 5, scope: !8, file: !5, type: !17)
+!19 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "w", line: 12, scope: !20, file: !5, type: !25)
+!20 = distinct !DILexicalBlock(line: 11, column: 0, file: !1, scope: !21)
+!21 = distinct !DILexicalBlock(line: 10, column: 0, file: !1, scope: !22)
+!22 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !23)
+!23 = distinct !DILexicalBlock(line: 8, column: 0, file: !1, scope: !24)
+!24 = distinct !DILexicalBlock(line: 7, column: 0, file: !1, scope: !8)
+!25 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !11)
 !26 = !{i32 2, !"Dwarf Version", i32 4}
-!27 = !MDLocation(line: 20, scope: !4)
-!28 = !MDLocation(line: 21, scope: !4)
+!27 = !DILocation(line: 20, scope: !4)
+!28 = !DILocation(line: 21, scope: !4)
 !29 = !{i32 1}
-!30 = !MDLocation(line: 2, scope: !8)
-!31 = !MDLocation(line: 7, scope: !24)
-!32 = !MDLocation(line: 13, scope: !20)
+!30 = !DILocation(line: 2, scope: !8)
+!31 = !DILocation(line: 7, scope: !24)
+!32 = !DILocation(line: 13, scope: !20)
 !33 = !{!34, !34, i64 0}
 !34 = !{!"int", !35, i64 0}
 !35 = !{!"omnipotent char", !36, i64 0}
 !36 = !{!"Simple C/C++ TBAA"}
-!37 = !MDLocation(line: 8, scope: !23)
-!38 = !MDLocation(line: 9, scope: !22)
-!39 = !MDLocation(line: 10, scope: !21)
-!40 = !MDLocation(line: 12, scope: !20)
+!37 = !DILocation(line: 8, scope: !23)
+!38 = !DILocation(line: 9, scope: !22)
+!39 = !DILocation(line: 10, scope: !21)
+!40 = !DILocation(line: 12, scope: !20)
 !41 = !{i32* @c}
-!42 = !MDLocation(line: 15, scope: !8)
-!43 = !{i32 1, !"Debug Info Version", i32 2}
+!42 = !DILocation(line: 15, scope: !8)
+!43 = !{i32 1, !"Debug Info Version", i32 3}
 !44 = !{i32 0}
diff --git a/test/DebugInfo/X86/float_const.ll b/test/DebugInfo/X86/float_const.ll
new file mode 100644
index 000000000000..6e99ffcc1f21
--- /dev/null
+++ b/test/DebugInfo/X86/float_const.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -filetype=obj | llvm-dwarfdump -debug-dump=info - | FileCheck %s
+; from (at -Os):
+; void foo() {
+;   float a = 3.14;
+;   *(int *)&a = 0;
+; }
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+; Function Attrs: nounwind optsize readnone uwtable
+define void @foo() #0 {
+entry:
+  tail call void @llvm.dbg.declare(metadata float* undef, metadata !13, metadata !19), !dbg !20
+  tail call void @llvm.dbg.value(metadata i32 1078523331, i64 0, metadata !13, metadata !19), !dbg !20
+  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !13, metadata !19), !dbg !20
+; CHECK:  DW_AT_const_value [DW_FORM_sdata]    (0)
+; CHECK-NEXT: DW_AT_name {{.*}}"a"
+  ret void, !dbg !21
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
+
+attributes #0 = { nounwind optsize readnone uwtable }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!15, !16, !17}
+!llvm.ident = !{!18}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.7.0 (trunk 227686)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !6, globals: !2, imports: !2)
+!1 = !DIFile(filename: "foo.c", directory: "")
+!2 = !{}
+!3 = !{!4}
+!4 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !5)
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !{!7}
+!7 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, isOptimized: true, scopeLine: 1, file: !8, scope: !9, type: !10, function: void ()* @foo, variables: !12)
+!8 = !DIFile(filename: "foo.c", directory: "")
+!9 = !DIFile(filename: "foo.c", directory: "")
+!10 = !DISubroutineType(types: !11)
+!11 = !{null}
+!12 = !{!13}
+!13 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 2, scope: !7, file: !9, type: !14)
+!14 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float)
+!15 = !{i32 2, !"Dwarf Version", i32 2}
+!16 = !{i32 2, !"Debug Info Version", i32 3}
+!17 = !{i32 1, !"PIC Level", i32 2}
+!18 = !{!"clang version 3.7.0 (trunk 227686)"}
+!19 = !DIExpression()
+!20 = !DILocation(line: 2, column: 9, scope: !7)
+!21 = !DILocation(line: 4, column: 1, scope: !7)
diff --git a/test/DebugInfo/X86/formal_parameter.ll b/test/DebugInfo/X86/formal_parameter.ll
index 9077c74b29fd..e8a8b5f1803b 100644
--- a/test/DebugInfo/X86/formal_parameter.ll
+++ b/test/DebugInfo/X86/formal_parameter.ll
@@ -28,16 +28,16 @@ define void @foo(i32 %map) #0 {
 entry:
   %map.addr = alloca i32, align 4
   store i32 %map, i32* %map.addr, align 4, !tbaa !15
-  call void @llvm.dbg.declare(metadata i32* %map.addr, metadata !10, metadata !{!"0x102"}), !dbg !14
-  %call = call i32 (i32*, ...)* bitcast (i32 (...)* @lookup to i32 (i32*, ...)*)(i32* %map.addr) #3, !dbg !19
+  call void @llvm.dbg.declare(metadata i32* %map.addr, metadata !10, metadata !DIExpression()), !dbg !14
+  %call = call i32 (i32*, ...) bitcast (i32 (...)* @lookup to i32 (i32*, ...)*)(i32* %map.addr) #3, !dbg !19
   ; Ensure that all dbg intrinsics have the same scope after
   ; LowerDbgDeclare is finished with them.
   ;
   ; LOWERING: call void @llvm.dbg.value{{.*}}, !dbg ![[LOC:.*]]
   ; LOWERING: call void @llvm.dbg.value{{.*}}, !dbg ![[LOC]]
   ; LOWERING: call void @llvm.dbg.value{{.*}}, !dbg ![[LOC]]
-%0 = load i32* %map.addr, align 4, !dbg !20, !tbaa !15
-  %call1 = call i32 (i32, ...)* bitcast (i32 (...)* @verify to i32 (i32, ...)*)(i32 %0) #3, !dbg !20
+%0 = load i32, i32* %map.addr, align 4, !dbg !20, !tbaa !15
+  %call1 = call i32 (i32, ...) bitcast (i32 (...)* @verify to i32 (i32, ...)*)(i32 %0) #3, !dbg !20
   ret void, !dbg !22
 }
 
@@ -59,26 +59,26 @@ attributes #3 = { nounwind }
 !llvm.module.flags = !{!11, !12}
 !llvm.ident = !{!13}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 \001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [formal_parameter.c] [DW_LANG_C99]
-!1 = !{!"formal_parameter.c", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "formal_parameter.c", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\001\002", !1, !5, !6, null, void (i32)* @foo, null, null, !9} ; [ DW_TAG_subprogram ] [line 1] [def] [scope 2] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [formal_parameter.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2, file: !1, scope: !5, type: !6, function: void (i32)* @foo, variables: !9)
+!5 = !DIFile(filename: "formal_parameter.c", directory: "")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{!10}
-!10 = !{!"0x101\00map\0016777217\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [map] [line 1]
+!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "map", line: 1, arg: 1, scope: !4, file: !5, type: !8)
 !11 = !{i32 2, !"Dwarf Version", i32 2}
-!12 = !{i32 1, !"Debug Info Version", i32 2}
+!12 = !{i32 1, !"Debug Info Version", i32 3}
 !13 = !{!"clang version 3.5.0 "}
-!14 = !MDLocation(line: 1, scope: !4)
+!14 = !DILocation(line: 1, scope: !4)
 !15 = !{!16, !16, i64 0}
 !16 = !{!"int", !17, i64 0}
 !17 = !{!"omnipotent char", !18, i64 0}
 !18 = !{!"Simple C/C++ TBAA"}
-!19 = !MDLocation(line: 3, scope: !4)
-!20 = !MDLocation(line: 4, scope: !21)
-!21 = !{!"0xb\004\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [formal_parameter.c]
-!22 = !MDLocation(line: 5, scope: !4)
+!19 = !DILocation(line: 3, scope: !4)
+!20 = !DILocation(line: 4, scope: !21)
+!21 = distinct !DILexicalBlock(line: 4, column: 0, file: !1, scope: !4)
+!22 = !DILocation(line: 5, scope: !4)
diff --git a/test/DebugInfo/X86/frame-register.ll b/test/DebugInfo/X86/frame-register.ll
new file mode 100644
index 000000000000..bcf65a1a3853
--- /dev/null
+++ b/test/DebugInfo/X86/frame-register.ll
@@ -0,0 +1,60 @@
+; RUN: llc %s -filetype=obj -o - | llvm-dwarfdump --debug-dump=info - | FileCheck %s
+; CHECK: DW_TAG_variable
+;                                                      DW_OP_fbreg
+; CHECK-NEXT: DW_AT_location [DW_FORM_exprloc]      (<0x2> 91 00 )
+; CHECK-NEXT: DW_AT_name {{.*}}"i"
+
+target datalayout = "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-darwin"
+
+; Function Attrs: nounwind uwtable
+declare i32 @foo(i32 %i) #0
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+; Function Attrs: nounwind uwtable
+define i32 @main() #0 {
+entry:
+  %retval = alloca i32, align 4
+  %i = alloca i32, align 4
+  store i32 0, i32* %retval
+  call void @llvm.dbg.declare(metadata i32* %i, metadata !20, metadata !16), !dbg !21
+  store i32 20, i32* %i, align 4, !dbg !21
+  %0 = load i32, i32* %i, align 4, !dbg !22
+  %call = call i32 @foo(i32 %0), !dbg !23
+  ret i32 %call, !dbg !24
+}
+
+attributes #0 = { nounwind uwtable  }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!12, !13}
+!llvm.ident = !{!14}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.7.0", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "x.c", directory: "")
+!2 = !{}
+!3 = !{!4, !9}
+!4 = !DISubprogram(name: "foo", line: 2, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !5, type: !6, function: i32 (i32)* @foo, variables: !2)
+!5 = !DIFile(filename: "x.c", directory: "")
+!6 = !DISubroutineType(types: !7)
+!7 = !{!8, !8}
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DISubprogram(name: "main", line: 8, isLocal: false, isDefinition: true, isOptimized: false, scopeLine: 9, file: !1, scope: !5, type: !10, function: i32 ()* @main, variables: !2)
+!10 = !DISubroutineType(types: !11)
+!11 = !{!8}
+!12 = !{i32 2, !"Dwarf Version", i32 4}
+!13 = !{i32 2, !"Debug Info Version", i32 3}
+!14 = !{!"clang version 3.7.0"}
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 2, arg: 1, scope: !4, file: !5, type: !8)
+!16 = !DIExpression()
+!17 = !DILocation(line: 2, column: 10, scope: !4)
+!18 = !DILocation(line: 4, column: 10, scope: !4)
+!19 = !DILocation(line: 4, column: 3, scope: !4)
+!20 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 10, scope: !9, file: !5, type: !8)
+!21 = !DILocation(line: 10, column: 7, scope: !9)
+!22 = !DILocation(line: 11, column: 15, scope: !9)
+!23 = !DILocation(line: 11, column: 10, scope: !9)
+!24 = !DILocation(line: 11, column: 3, scope: !9)
diff --git a/test/DebugInfo/X86/generate-odr-hash.ll b/test/DebugInfo/X86/generate-odr-hash.ll
index 6d4fa86697c7..7ac9a69181f3 100644
--- a/test/DebugInfo/X86/generate-odr-hash.ll
+++ b/test/DebugInfo/X86/generate-odr-hash.ll
@@ -183,7 +183,7 @@
 define void @_Z3foov() #0 {
 entry:
   %b = alloca %struct.baz, align 1
-  call void @llvm.dbg.declare(metadata %struct.baz* %b, metadata !46, metadata !{!"0x102"}), !dbg !48
+  call void @llvm.dbg.declare(metadata %struct.baz* %b, metadata !46, metadata !DIExpression()), !dbg !48
   ret void, !dbg !49
 }
 
@@ -201,8 +201,8 @@ define internal void @_ZN12_GLOBAL__N_16walrusC2Ev(%"struct.<anonymous namespace
 entry:
   %this.addr = alloca %"struct.<anonymous namespace>::walrus"*, align 8
   store %"struct.<anonymous namespace>::walrus"* %this, %"struct.<anonymous namespace>::walrus"** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %"struct.<anonymous namespace>::walrus"** %this.addr, metadata !51, metadata !{!"0x102"}), !dbg !53
-  %this1 = load %"struct.<anonymous namespace>::walrus"** %this.addr
+  call void @llvm.dbg.declare(metadata %"struct.<anonymous namespace>::walrus"** %this.addr, metadata !51, metadata !DIExpression()), !dbg !53
+  %this1 = load %"struct.<anonymous namespace>::walrus"*, %"struct.<anonymous namespace>::walrus"** %this.addr
   ret void, !dbg !54
 }
 
@@ -219,59 +219,58 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!43, !44}
 !llvm.ident = !{!45}
 
-!0 = !{!"0x11\004\00clang version 3.5 \000\00\000\00bar.dwo\000", !1, !2, !3, !21, !38, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/bar.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"bar.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, splitDebugFilename: "bar.dwo", emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !21, globals: !38, imports: !2)
+!1 = !DIFile(filename: "bar.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4, !6, !14, !17}
-!4 = !{!"0x13\00bar\001\008\008\000\000\000", !5, null, null, !2, null, null, !"_ZTS3bar"} ; [ DW_TAG_structure_type ] [bar] [line 1, size 8, align 8, offset 0] [def] [from ]
-!5 = !{!"bar.h", !"/tmp/dbginfo"}
-!6 = !{!"0x2\00fluffy\0013\0064\0032\000\000\000", !1, !7, null, !10, null, null, !"_ZTSN7echidna8capybara8mongoose6fluffyE"} ; [ DW_TAG_class_type ] [fluffy] [line 13, size 64, align 32, offset 0] [def] [from ]
-!7 = !{!"0x39\00mongoose\0012", !1, !8} ; [ DW_TAG_namespace ] [mongoose] [line 12]
-!8 = !{!"0x39\00capybara\0011", !1, !9} ; [ DW_TAG_namespace ] [capybara] [line 11]
-!9 = !{!"0x39\00echidna\0010", !1, null} ; [ DW_TAG_namespace ] [echidna] [line 10]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "bar", line: 1, size: 8, align: 8, file: !5, elements: !2, identifier: "_ZTS3bar")
+!5 = !DIFile(filename: "bar.h", directory: "/tmp/dbginfo")
+!6 = !DICompositeType(tag: DW_TAG_class_type, name: "fluffy", line: 13, size: 64, align: 32, file: !1, scope: !7, elements: !10, identifier: "_ZTSN7echidna8capybara8mongoose6fluffyE")
+!7 = !DINamespace(name: "mongoose", line: 12, file: !1, scope: !8)
+!8 = !DINamespace(name: "capybara", line: 11, file: !1, scope: !9)
+!9 = !DINamespace(name: "echidna", line: 10, file: !1, scope: null)
 !10 = !{!11, !13}
-!11 = !{!"0xd\00a\0014\0032\0032\000\001", !1, !"_ZTSN7echidna8capybara8mongoose6fluffyE", !12} ; [ DW_TAG_member ] [a] [line 14, size 32, align 32, offset 0] [private] [from int]
-!12 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!13 = !{!"0xd\00b\0015\0032\0032\0032\001", !1, !"_ZTSN7echidna8capybara8mongoose6fluffyE", !12} ; [ DW_TAG_member ] [b] [line 15, size 32, align 32, offset 32] [private] [from int]
-!14 = !{!"0x13\00wombat\0031\0064\0032\000\000\000", !1, null, null, !15, null, null, !"_ZTS6wombat"} ; [ DW_TAG_structure_type ] [wombat] [line 31, size 64, align 32, offset 0] [def] [from ]
+!11 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 14, size: 32, align: 32, flags: DIFlagPrivate, file: !1, scope: !"_ZTSN7echidna8capybara8mongoose6fluffyE", baseType: !12)
+!12 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!13 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 15, size: 32, align: 32, offset: 32, flags: DIFlagPrivate, file: !1, scope: !"_ZTSN7echidna8capybara8mongoose6fluffyE", baseType: !12)
+!14 = !DICompositeType(tag: DW_TAG_structure_type, name: "wombat", line: 31, size: 64, align: 32, file: !1, elements: !15, identifier: "_ZTS6wombat")
 !15 = !{!16}
-!16 = !{!"0xd\00a_b\0035\0064\0032\000\000", !1, !"_ZTS6wombat", !"_ZTSN6wombatUt_E"} ; [ DW_TAG_member ] [a_b] [line 35, size 64, align 32, offset 0] [from _ZTSN6wombatUt_E]
-!17 = !{!"0x13\00\0032\0064\0032\000\000\000", !1, !"_ZTS6wombat", null, !18, null, null, !"_ZTSN6wombatUt_E"} ; [ DW_TAG_structure_type ] [line 32, size 64, align 32, offset 0] [def] [from ]
+!16 = !DIDerivedType(tag: DW_TAG_member, name: "a_b", line: 35, size: 64, align: 32, file: !1, scope: !"_ZTS6wombat", baseType: !"_ZTSN6wombatUt_E")
+!17 = !DICompositeType(tag: DW_TAG_structure_type, line: 32, size: 64, align: 32, file: !1, scope: !"_ZTS6wombat", elements: !18, identifier: "_ZTSN6wombatUt_E")
 !18 = !{!19, !20}
-!19 = !{!"0xd\00a\0033\0032\0032\000\000", !1, !"_ZTSN6wombatUt_E", !12} ; [ DW_TAG_member ] [a] [line 33, size 32, align 32, offset 0] [from int]
-!20 = !{!"0xd\00b\0034\0032\0032\0032\000", !1, !"_ZTSN6wombatUt_E", !12} ; [ DW_TAG_member ] [b] [line 34, size 32, align 32, offset 32] [from int]
+!19 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 33, size: 32, align: 32, file: !1, scope: !"_ZTSN6wombatUt_E", baseType: !12)
+!20 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 34, size: 32, align: 32, offset: 32, file: !1, scope: !"_ZTSN6wombatUt_E", baseType: !12)
 !21 = !{!22, !26, !27, !36}
-!22 = !{!"0x2e\00foo\00foo\00_Z3foov\005\000\001\000\006\00256\000\005", !1, !23, !24, null, void ()* @_Z3foov, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [foo]
-!23 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/tmp/dbginfo/bar.cpp]
-!24 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !25, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!22 = !DISubprogram(name: "foo", linkageName: "_Z3foov", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !23, type: !24, function: void ()* @_Z3foov, variables: !2)
+!23 = !DIFile(filename: "bar.cpp", directory: "/tmp/dbginfo")
+!24 = !DISubroutineType(types: !25)
 !25 = !{null}
-!26 = !{!"0x2e\00__cxx_global_var_init\00__cxx_global_var_init\00\0029\001\001\000\006\00256\000\0029", !1, !23, !24, null, void ()* @__cxx_global_var_init, null, null, !2} ; [ DW_TAG_subprogram ] [line 29] [local] [def] [__cxx_global_var_init]
-!27 = !{!"0x2e\00walrus\00walrus\00_ZN12_GLOBAL__N_16walrusC2Ev\0025\001\001\000\006\00256\000\0025", !1, !28, !32, null, void (%"struct.<anonymous namespace>::walrus"*)* @_ZN12_GLOBAL__N_16walrusC2Ev, null, !31, !2} ; [ DW_TAG_subprogram ] [line 25] [local] [def] [walrus]
-!28 = !{!"0x13\00walrus\0024\008\008\000\000\000", !1, !29, null, !30, null, null, null} ; [ DW_TAG_structure_type ] [walrus] [line 24, size 8, align 8, offset 0] [def] [from ]
-!29 = !{!"0x39\00\0023", !1, null} ; [ DW_TAG_namespace ] [line 23]
+!26 = !DISubprogram(name: "__cxx_global_var_init", line: 29, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 29, file: !1, scope: !23, type: !24, function: void ()* @__cxx_global_var_init, variables: !2)
+!27 = !DISubprogram(name: "walrus", linkageName: "_ZN12_GLOBAL__N_16walrusC2Ev", line: 25, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 25, file: !1, scope: !28, type: !32, function: void (%"struct.<anonymous namespace>::walrus"*)* @_ZN12_GLOBAL__N_16walrusC2Ev, declaration: !31, variables: !2)
+!28 = !DICompositeType(tag: DW_TAG_structure_type, name: "walrus", line: 24, size: 8, align: 8, file: !1, scope: !29, elements: !30)
+!29 = !DINamespace(line: 23, file: !1, scope: null)
 !30 = !{!31}
-!31 = !{!"0x2e\00walrus\00walrus\00\0025\000\000\000\006\00256\000\0025", !1, !28, !32, null, null, null, i32 0, !35} ; [ DW_TAG_subprogram ] [line 25] [walrus]
-!32 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !33, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!31 = !DISubprogram(name: "walrus", line: 25, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 25, file: !1, scope: !28, type: !32)
+!32 = !DISubroutineType(types: !33)
 !33 = !{null, !34}
-!34 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !28} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from walrus]
-!35 = !{i32 786468}
-!36 = !{!"0x2e\00\00\00_GLOBAL__I_a\0025\001\001\000\006\0064\000\0025", !1, !23, !37, null, void ()* @_GLOBAL__I_a, null, null, !2} ; [ DW_TAG_subprogram ] [line 25] [local] [def]
-!37 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!34 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !28)
+!36 = !DISubprogram(name: "", linkageName: "_GLOBAL__I_a", line: 25, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagArtificial, isOptimized: false, scopeLine: 25, file: !1, scope: !23, type: !37, function: void ()* @_GLOBAL__I_a, variables: !2)
+!37 = !DISubroutineType(types: !2)
 !38 = !{!39, !40, !41, !42}
-!39 = !{!"0x34\00b\00b\00\003\000\001", null, !23, !4, %struct.bar* @b, null} ; [ DW_TAG_variable ] [b] [line 3] [def]
-!40 = !{!"0x34\00animal\00animal\00_ZN7echidna8capybara8mongoose6animalE\0018\000\001", !7, !23, !6, %"class.echidna::capybara::mongoose::fluffy"* @_ZN7echidna8capybara8mongoose6animalE, null} ; [ DW_TAG_variable ] [animal] [line 18] [def]
-!41 = !{!"0x34\00w\00w\00\0029\001\001", null, !23, !28, %"struct.<anonymous namespace>::walrus"* @w, null} ; [ DW_TAG_variable ] [w] [line 29] [local] [def]
-!42 = !{!"0x34\00wom\00wom\00\0038\000\001", null, !23, !14, %struct.wombat* @wom, null} ; [ DW_TAG_variable ] [wom] [line 38] [def]
+!39 = !DIGlobalVariable(name: "b", line: 3, isLocal: false, isDefinition: true, scope: null, file: !23, type: !4, variable: %struct.bar* @b)
+!40 = !DIGlobalVariable(name: "animal", linkageName: "_ZN7echidna8capybara8mongoose6animalE", line: 18, isLocal: false, isDefinition: true, scope: !7, file: !23, type: !6, variable: %"class.echidna::capybara::mongoose::fluffy"* @_ZN7echidna8capybara8mongoose6animalE)
+!41 = !DIGlobalVariable(name: "w", line: 29, isLocal: true, isDefinition: true, scope: null, file: !23, type: !28, variable: %"struct.<anonymous namespace>::walrus"* @w)
+!42 = !DIGlobalVariable(name: "wom", line: 38, isLocal: false, isDefinition: true, scope: null, file: !23, type: !14, variable: %struct.wombat* @wom)
 !43 = !{i32 2, !"Dwarf Version", i32 4}
-!44 = !{i32 1, !"Debug Info Version", i32 2}
+!44 = !{i32 1, !"Debug Info Version", i32 3}
 !45 = !{!"clang version 3.5 "}
-!46 = !{!"0x100\00b\007\000", !22, !23, !47} ; [ DW_TAG_auto_variable ] [b] [line 7]
-!47 = !{!"0x13\00baz\006\008\008\000\000\000", !1, !22, null, !2, null, null, null} ; [ DW_TAG_structure_type ] [baz] [line 6, size 8, align 8, offset 0] [def] [from ]
-!48 = !MDLocation(line: 7, scope: !22)
-!49 = !MDLocation(line: 8, scope: !22)
-!50 = !MDLocation(line: 29, scope: !26)
-!51 = !{!"0x101\00this\0016777216\001088", !27, null, !52} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!52 = !{!"0xf\00\000\0064\0064\000\000", null, null, !28} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from walrus]
-!53 = !MDLocation(line: 0, scope: !27)
-!54 = !MDLocation(line: 25, scope: !27)
-!55 = !MDLocation(line: 25, scope: !36)
+!46 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 7, scope: !22, file: !23, type: !47)
+!47 = !DICompositeType(tag: DW_TAG_structure_type, name: "baz", line: 6, size: 8, align: 8, file: !1, scope: !22, elements: !2)
+!48 = !DILocation(line: 7, scope: !22)
+!49 = !DILocation(line: 8, scope: !22)
+!50 = !DILocation(line: 29, scope: !26)
+!51 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !27, type: !52)
+!52 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !28)
+!53 = !DILocation(line: 0, scope: !27)
+!54 = !DILocation(line: 25, scope: !27)
+!55 = !DILocation(line: 25, scope: !36)
diff --git a/test/DebugInfo/X86/ghost-sdnode-dbgvalues.ll b/test/DebugInfo/X86/ghost-sdnode-dbgvalues.ll
index 9391da6da4f1..ef249e8fab9c 100644
--- a/test/DebugInfo/X86/ghost-sdnode-dbgvalues.ll
+++ b/test/DebugInfo/X86/ghost-sdnode-dbgvalues.ll
@@ -68,38 +68,38 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!13, !14}
 !llvm.ident = !{!15}
 
-!0 = !{!"0x11\0012\00clang version 3.6.0 \000\00\000\00\001", !1, !2, !3, !7, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/ghost-sdnode-dbgvalues.c] [DW_LANG_C99]
-!1 = !{!"ghost-sdnode-dbgvalues.c", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.6.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !7, globals: !2, imports: !2)
+!1 = !DIFile(filename: "ghost-sdnode-dbgvalues.c", directory: "/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x16\00int16_t\0030\000\000\000\000", !5, null, !6} ; [ DW_TAG_typedef ] [int16_t] [line 30, size 0, align 0, offset 0] [from short]
-!5 = !{!"/usr/include/sys/_types/_int16_t.h", !"/tmp"}
-!6 = !{!"0x24\00short\000\0016\0016\000\000\005", null, null} ; [ DW_TAG_base_type ] [short] [line 0, size 16, align 16, offset 0, enc DW_ATE_signed]
+!4 = !DIDerivedType(tag: DW_TAG_typedef, name: "int16_t", line: 30, file: !5, baseType: !6)
+!5 = !DIFile(filename: "/usr/include/sys/_types/_int16_t.h", directory: "/tmp")
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "short", size: 16, align: 16, encoding: DW_ATE_signed)
 !7 = !{!8}
-!8 = !{!"0x2e\00foo\00foo\00\003\000\001\000\000\00256\000\003", !1, !9, !10, null, i32 (i32)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [foo]
-!9 = !{!"0x29", !1}    ; [ DW_TAG_file_type ] [/tmp/ghost-sdnode-dbgvalues.c]
-!10 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = !DISubprogram(name: "foo", line: 3, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !9, type: !10, function: i32 (i32)* @foo, variables: !2)
+!9 = !DIFile(filename: "ghost-sdnode-dbgvalues.c", directory: "/tmp")
+!10 = !DISubroutineType(types: !11)
 !11 = !{!12, !12}
-!12 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!12 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !13 = !{i32 2, !"Dwarf Version", i32 2}
-!14 = !{i32 2, !"Debug Info Version", i32 2}
+!14 = !{i32 2, !"Debug Info Version", i32 3}
 !15 = !{!"clang version 3.6.0 "}
-!16 = !{!"0x101\00a\0016777219\000", !8, !9, !12} ; [ DW_TAG_arg_variable ] [a] [line 3]
-!17 = !{!"0x102"}               ; [ DW_TAG_expression ]
-!18 = !MDLocation(line: 3, column: 13, scope: !8)
-!19 = !MDLocation(line: 4, column: 5, scope: !8)
-!20 = !{!"0x100\00b\004\000", !8, !9, !12} ; [ DW_TAG_auto_variable ] [b] [line 4]
-!21 = !MDLocation(line: 4, column: 9, scope: !8)
-!22 = !MDLocation(line: 5, column: 5, scope: !8)
-!23 = !{!"0x100\00c\005\000", !8, !9, !12} ; [ DW_TAG_auto_variable ] [c] [line 5]
-!24 = !MDLocation(line: 5, column: 9, scope: !8)
-!25 = !MDLocation(line: 6, column: 5, scope: !8)
-!26 = !{!"0x100\00d\006\000", !8, !9, !12} ; [ DW_TAG_auto_variable ] [d] [line 6]
-!27 = !MDLocation(line: 6, column: 9, scope: !8)
-!28 = !MDLocation(line: 7, column: 5, scope: !8)
-!29 = !{!"0x100\00e\007\000", !8, !9, !12} ; [ DW_TAG_auto_variable ] [e] [line 7]
-!30 = !MDLocation(line: 7, column: 9, scope: !8)
-!31 = !MDLocation(line: 8, column: 5, scope: !8)
-!32 = !{!"0x100\00f\008\000", !8, !9, !12} ; [ DW_TAG_auto_variable ] [f] [line 8]
-!33 = !MDLocation(line: 8, column: 9, scope: !8)
-!34 = !MDLocation(line: 9, column: 5, scope: !8)
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 3, arg: 1, scope: !8, file: !9, type: !12)
+!17 = !DIExpression()
+!18 = !DILocation(line: 3, column: 13, scope: !8)
+!19 = !DILocation(line: 4, column: 5, scope: !8)
+!20 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 4, scope: !8, file: !9, type: !12)
+!21 = !DILocation(line: 4, column: 9, scope: !8)
+!22 = !DILocation(line: 5, column: 5, scope: !8)
+!23 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "c", line: 5, scope: !8, file: !9, type: !12)
+!24 = !DILocation(line: 5, column: 9, scope: !8)
+!25 = !DILocation(line: 6, column: 5, scope: !8)
+!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "d", line: 6, scope: !8, file: !9, type: !12)
+!27 = !DILocation(line: 6, column: 9, scope: !8)
+!28 = !DILocation(line: 7, column: 5, scope: !8)
+!29 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "e", line: 7, scope: !8, file: !9, type: !12)
+!30 = !DILocation(line: 7, column: 9, scope: !8)
+!31 = !DILocation(line: 8, column: 5, scope: !8)
+!32 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "f", line: 8, scope: !8, file: !9, type: !12)
+!33 = !DILocation(line: 8, column: 9, scope: !8)
+!34 = !DILocation(line: 9, column: 5, scope: !8)
diff --git a/test/DebugInfo/X86/gnu-public-names-empty.ll b/test/DebugInfo/X86/gnu-public-names-empty.ll
index f9a06175d2cd..d87d8ef19008 100644
--- a/test/DebugInfo/X86/gnu-public-names-empty.ll
+++ b/test/DebugInfo/X86/gnu-public-names-empty.ll
@@ -12,8 +12,8 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!3, !4}
 
-!0 = !{!"0x11\0012\00clang version 3.4 (trunk 191846) (llvm/trunk 191866)\000\00\000\00\000", !1, !2, !2, !2, !2, !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/foo.c] [DW_LANG_C99]
-!1 = !{!"foo.c", !"/usr/local/google/home/echristo/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 191846) (llvm/trunk 191866)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !2, imports: !2)
+!1 = !DIFile(filename: "foo.c", directory: "/usr/local/google/home/echristo/tmp")
 !2 = !{}
 !3 = !{i32 2, !"Dwarf Version", i32 4}
-!4 = !{i32 1, !"Debug Info Version", i32 2}
+!4 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/gnu-public-names.ll b/test/DebugInfo/X86/gnu-public-names.ll
index 7e92b537c894..2022dfaa687c 100644
--- a/test/DebugInfo/X86/gnu-public-names.ll
+++ b/test/DebugInfo/X86/gnu-public-names.ll
@@ -31,10 +31,38 @@
 ;     global_variable.member_function();
 ;   }
 ;   int global_namespace_variable = 1;
+;   extern int global_namespace_variable_decl;
 ;   struct D {
 ;     int A;
 ;   } d;
 ; }
+;
+; using ns::global_namespace_variable_decl;
+;
+; namespace {
+; int i;
+; }
+;
+; int *f3() {
+;   static int z;
+;   return &z;
+; }
+;
+; namespace {
+; namespace inner {
+; int b;
+; }
+; }
+;
+; namespace outer {
+; namespace {
+; int c;
+; }
+; }
+;
+; int f7() {
+;   return i + *f3() + inner::b + outer::c;
+; }
 
 ; ASM: .section        .debug_gnu_pubnames
 ; ASM: .byte   32                      # Kind: VARIABLE, EXTERNAL
@@ -59,11 +87,11 @@
 ; CHECK-NEXT: DW_AT_name {{.*}} "static_member_variable"
 
 ; CHECK: DW_TAG_subprogram
-; CHECK-NEXT: DW_AT_MIPS_linkage_name
+; CHECK-NEXT: DW_AT_linkage_name
 ; CHECK-NEXT: DW_AT_name {{.*}} "member_function"
 
 ; CHECK: DW_TAG_subprogram
-; CHECK-NEXT: DW_AT_MIPS_linkage_name
+; CHECK-NEXT: DW_AT_linkage_name
 ; CHECK-NEXT: DW_AT_name {{.*}} "static_member_function"
 
 ; CHECK: [[INT:0x[0-9a-f]+]]: DW_TAG_base_type
@@ -92,7 +120,7 @@
 
 ; CHECK: [[GLOB_NS_FUNC:0x[0-9a-f]+]]: DW_TAG_subprogram
 ; CHECK-NOT: DW_TAG
-; CHECK: DW_AT_MIPS_linkage_name
+; CHECK: DW_AT_linkage_name
 ; CHECK-NOT: DW_TAG
 ; CHECK: DW_AT_name {{.*}} "global_namespace_function"
 
@@ -109,6 +137,25 @@
 ; CHECK:   NULL
 ; CHECK-NOT: {{DW_TAG|NULL}}
 
+; CHECK: [[ANON:.*]]: DW_TAG_namespace
+; CHECK-NOT:   DW_AT_name
+; CHECK: [[ANON_I:.*]]: DW_TAG_variable
+; CHECK-NOT: DW_TAG
+; CHECK:     DW_AT_name {{.*}} "i"
+; CHECK-NOT: {{DW_TAG|NULL}}
+; CHECK: [[ANON_INNER:.*]]:  DW_TAG_namespace
+; CHECK-NOT: DW_TAG
+; CHECK:     DW_AT_name {{.*}} "inner"
+; CHECK-NOT: {{DW_TAG|NULL}}
+; CHECK: [[ANON_INNER_B:.*]]: DW_TAG_variable
+; CHECK-NOT: DW_TAG
+; CHECK:       DW_AT_name {{.*}} "b"
+; CHECK-NOT: {{DW_TAG|NULL}}
+; CHECK:     NULL
+; CHECK-NOT: {{DW_TAG|NULL}}
+; CHECK:   NULL
+; CHECK-NOT: {{DW_TAG|NULL}}
+
 ; CHECK: [[OUTER:.*]]: DW_TAG_namespace
 ; CHECK-NOT: DW_TAG
 ; CHECK:   DW_AT_name {{.*}} "outer"
@@ -130,23 +177,7 @@
 ; CHECK:   NULL
 ; CHECK-NOT: {{DW_TAG|NULL}}
 
-; CHECK: [[ANON:.*]]: DW_TAG_namespace
-; CHECK-NOT:   DW_AT_name
-; CHECK: [[ANON_INNER:.*]]:  DW_TAG_namespace
-; CHECK-NOT: DW_TAG
-; CHECK:     DW_AT_name {{.*}} "inner"
-; CHECK-NOT: {{DW_TAG|NULL}}
-; CHECK: [[ANON_INNER_B:.*]]: DW_TAG_variable
-; CHECK-NOT: DW_TAG
-; CHECK:       DW_AT_name {{.*}} "b"
-; CHECK-NOT: {{DW_TAG|NULL}}
-; CHECK:     NULL
-; CHECK-NOT: {{DW_TAG|NULL}}
-; CHECK: [[ANON_I:.*]]: DW_TAG_variable
-; CHECK-NOT: DW_TAG
-; CHECK:     DW_AT_name {{.*}} "i"
-; CHECK-NOT: {{DW_TAG|NULL}}
-; CHECK:   NULL
+; CHECK: DW_TAG_imported_declaration
 ; CHECK-NOT: {{DW_TAG|NULL}}
 
 ; CHECK: [[MEM_FUNC:0x[0-9a-f]+]]: DW_TAG_subprogram
@@ -159,36 +190,35 @@
 
 ; CHECK: [[GLOBAL_FUNC:0x[0-9a-f]+]]: DW_TAG_subprogram
 ; CHECK-NOT: DW_TAG
-; CHECK: DW_AT_MIPS_linkage_name
+; CHECK: DW_AT_linkage_name
 ; CHECK-NOT: DW_TAG
 ; CHECK: DW_AT_name {{.*}} "global_function"
 
 ; CHECK-LABEL: .debug_gnu_pubnames contents:
 ; CHECK-NEXT: length = {{.*}} version = 0x0002 unit_offset = 0x00000000 unit_size = {{.*}}
 ; CHECK-NEXT: Offset     Linkage  Kind     Name
-; CHECK-DAG:  [[GLOBAL_FUNC]] EXTERNAL FUNCTION "global_function"
-; CHECK-DAG:  [[NS]] EXTERNAL TYPE     "ns"
-; CHECK-DAG:  [[MEM_FUNC]] EXTERNAL FUNCTION "C::member_function"
-; CHECK-DAG:  [[GLOB_VAR]] EXTERNAL VARIABLE "global_variable"
-; CHECK-DAG:  [[GLOB_NS_VAR]] EXTERNAL VARIABLE "ns::global_namespace_variable"
-; CHECK-DAG:  [[GLOB_NS_FUNC]] EXTERNAL FUNCTION "ns::global_namespace_function"
-; CHECK-DAG:  [[D_VAR]] EXTERNAL VARIABLE "ns::d"
-; CHECK-DAG:  [[STATIC_MEM_VAR]] EXTERNAL VARIABLE "C::static_member_variable"
-; CHECK-DAG:  [[STATIC_MEM_FUNC]] EXTERNAL FUNCTION "C::static_member_function"
-; CHECK-DAG:  [[ANON]] EXTERNAL TYPE "(anonymous namespace)"
-; CHECK-DAG:  [[ANON_INNER]] EXTERNAL TYPE "(anonymous namespace)::inner"
-; CHECK-DAG:  [[OUTER]] EXTERNAL TYPE "outer"
-; CHECK-DAG:  [[OUTER_ANON]] EXTERNAL TYPE "outer::(anonymous namespace)"
-; CHECK-DAG:  [[ANON_I]] STATIC VARIABLE "(anonymous namespace)::i"
-; CHECK-DAG:  [[ANON_INNER_B]] STATIC VARIABLE "(anonymous namespace)::inner::b"
-; CHECK-DAG:  [[OUTER_ANON_C]] STATIC VARIABLE "outer::(anonymous namespace)::c"
-
+; CHECK-NEXT:  [[GLOBAL_FUNC]] EXTERNAL FUNCTION "global_function"
+; CHECK-NEXT:  [[NS]] EXTERNAL TYPE     "ns"
+; CHECK-NEXT:  [[OUTER_ANON_C]] STATIC VARIABLE "outer::(anonymous namespace)::c"
+; CHECK-NEXT:  [[ANON_I]] STATIC VARIABLE "(anonymous namespace)::i"
 ; GCC Doesn't put local statics in pubnames, but it seems not unreasonable and
 ; comes out naturally from LLVM's implementation, so I'm OK with it for now. If
 ; it's demonstrated that this is a major size concern or degrades debug info
 ; consumer behavior, feel free to change it.
+; CHECK-NEXT:  [[F3_Z]] STATIC VARIABLE "f3::z"
+; CHECK-NEXT:  [[ANON]] EXTERNAL TYPE "(anonymous namespace)"
+; CHECK-NEXT:  [[OUTER_ANON]] EXTERNAL TYPE "outer::(anonymous namespace)"
+; CHECK-NEXT:  [[ANON_INNER_B]] STATIC VARIABLE "(anonymous namespace)::inner::b"
+; CHECK-NEXT:  [[OUTER]] EXTERNAL TYPE "outer"
+; CHECK-NEXT:  [[MEM_FUNC]] EXTERNAL FUNCTION "C::member_function"
+; CHECK-NEXT:  [[GLOB_VAR]] EXTERNAL VARIABLE "global_variable"
+; CHECK-NEXT:  [[GLOB_NS_VAR]] EXTERNAL VARIABLE "ns::global_namespace_variable"
+; CHECK-NEXT:  [[ANON_INNER]] EXTERNAL TYPE "(anonymous namespace)::inner"
+; CHECK-NEXT:  [[D_VAR]] EXTERNAL VARIABLE "ns::d"
+; CHECK-NEXT:  [[GLOB_NS_FUNC]] EXTERNAL FUNCTION "ns::global_namespace_function"
+; CHECK-NEXT:  [[STATIC_MEM_VAR]] EXTERNAL VARIABLE "C::static_member_variable"
+; CHECK-NEXT:  [[STATIC_MEM_FUNC]] EXTERNAL FUNCTION "C::static_member_function"
 
-; CHECK-DAG:  [[F3_Z]] STATIC VARIABLE "f3::z"
 
 
 ; CHECK-LABEL: debug_gnu_pubtypes contents:
@@ -214,10 +244,10 @@ define void @_ZN1C15member_functionEv(%struct.C* %this) #0 align 2 {
 entry:
   %this.addr = alloca %struct.C*, align 8
   store %struct.C* %this, %struct.C** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.C** %this.addr, metadata !50, metadata !{!"0x102"}), !dbg !52
-  %this1 = load %struct.C** %this.addr
-  store i32 0, i32* @_ZN1C22static_member_variableE, align 4, !dbg !53
-  ret void, !dbg !54
+  call void @llvm.dbg.declare(metadata %struct.C** %this.addr, metadata !51, metadata !53), !dbg !54
+  %this1 = load %struct.C*, %struct.C** %this.addr
+  store i32 0, i32* @_ZN1C22static_member_variableE, align 4, !dbg !55
+  ret void, !dbg !56
 }
 
 ; Function Attrs: nounwind readnone
@@ -226,108 +256,110 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
 ; Function Attrs: nounwind uwtable
 define i32 @_ZN1C22static_member_functionEv() #0 align 2 {
 entry:
-  %0 = load i32* @_ZN1C22static_member_variableE, align 4, !dbg !55
-  ret i32 %0, !dbg !55
+  %0 = load i32, i32* @_ZN1C22static_member_variableE, align 4, !dbg !57
+  ret i32 %0, !dbg !57
 }
 
 ; Function Attrs: nounwind uwtable
 define i32 @_Z15global_functionv() #0 {
 entry:
-  ret i32 -1, !dbg !56
+  ret i32 -1, !dbg !58
 }
 
 ; Function Attrs: nounwind uwtable
 define void @_ZN2ns25global_namespace_functionEv() #0 {
 entry:
-  call void @_ZN1C15member_functionEv(%struct.C* @global_variable), !dbg !57
-  ret void, !dbg !58
+  call void @_ZN1C15member_functionEv(%struct.C* @global_variable), !dbg !59
+  ret void, !dbg !60
 }
 
 ; Function Attrs: nounwind uwtable
 define i32* @_Z2f3v() #0 {
 entry:
-  ret i32* @_ZZ2f3vE1z, !dbg !59
+  ret i32* @_ZZ2f3vE1z, !dbg !61
 }
 
 ; Function Attrs: nounwind uwtable
 define i32 @_Z2f7v() #0 {
 entry:
-  %0 = load i32* @_ZN12_GLOBAL__N_11iE, align 4, !dbg !60
-  %call = call i32* @_Z2f3v(), !dbg !60
-  %1 = load i32* %call, align 4, !dbg !60
-  %add = add nsw i32 %0, %1, !dbg !60
-  %2 = load i32* @_ZN12_GLOBAL__N_15inner1bE, align 4, !dbg !60
-  %add1 = add nsw i32 %add, %2, !dbg !60
-  %3 = load i32* @_ZN5outer12_GLOBAL__N_11cE, align 4, !dbg !60
-  %add2 = add nsw i32 %add1, %3, !dbg !60
-  ret i32 %add2, !dbg !60
+  %0 = load i32, i32* @_ZN12_GLOBAL__N_11iE, align 4, !dbg !62
+  %call = call i32* @_Z2f3v(), !dbg !62
+  %1 = load i32, i32* %call, align 4, !dbg !62
+  %add = add nsw i32 %0, %1, !dbg !62
+  %2 = load i32, i32* @_ZN12_GLOBAL__N_15inner1bE, align 4, !dbg !62
+  %add1 = add nsw i32 %add, %2, !dbg !62
+  %3 = load i32, i32* @_ZN5outer12_GLOBAL__N_11cE, align 4, !dbg !62
+  %add2 = add nsw i32 %add1, %3, !dbg !62
+  ret i32 %add2, !dbg !62
 }
 
-attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { nounwind readnone }
 
 !llvm.dbg.cu = !{!0}
-!llvm.module.flags = !{!47, !48}
-!llvm.ident = !{!49}
+!llvm.module.flags = !{!48, !49}
+!llvm.ident = !{!50}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !3, !19, !32, !45} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/pubnames.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"pubnames.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 3.7.0 (trunk 234897) (llvm/trunk 234911)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !3, subprograms: !19, globals: !31, imports: !44)
+!1 = !DIFile(filename: "gnu-public-names.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4, !15}
-!4 = !{!"0x13\00C\001\008\008\000\000\000", !1, null, null, !5, null, null, !"_ZTS1C"} ; [ DW_TAG_structure_type ] [C] [line 1, size 8, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "C", file: !1, line: 1, size: 8, align: 8, elements: !5, identifier: "_ZTS1C")
 !5 = !{!6, !8, !12}
-!6 = !{!"0xd\00static_member_variable\004\000\000\000\004096", !1, !"_ZTS1C", !7, null} ; [ DW_TAG_member ] [static_member_variable] [line 4, size 0, align 0, offset 0] [static] [from int]
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!8 = !{!"0x2e\00member_function\00member_function\00_ZN1C15member_functionEv\002\000\000\000\006\00256\000\002", !1, !"_ZTS1C", !9, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 2] [member_function]
-!9 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DIDerivedType(tag: DW_TAG_member, name: "static_member_variable", scope: !"_ZTS1C", file: !1, line: 4, baseType: !7, flags: DIFlagStaticMember)
+!7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DISubprogram(name: "member_function", linkageName: "_ZN1C15member_functionEv", scope: !"_ZTS1C", file: !1, line: 2, type: !9, isLocal: false, isDefinition: false, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: false)
+!9 = !DISubroutineType(types: !10)
 !10 = !{null, !11}
-!11 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1C"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1C]
-!12 = !{!"0x2e\00static_member_function\00static_member_function\00_ZN1C22static_member_functionEv\003\000\000\000\006\00256\000\003", !1, !"_ZTS1C", !13, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 3] [static_member_function]
-!13 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !14, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !"_ZTS1C", size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer)
+!12 = !DISubprogram(name: "static_member_function", linkageName: "_ZN1C22static_member_functionEv", scope: !"_ZTS1C", file: !1, line: 3, type: !13, isLocal: false, isDefinition: false, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: false)
+!13 = !DISubroutineType(types: !14)
 !14 = !{!7}
-!15 = !{!"0x13\00D\0028\0032\0032\000\000\000", !1, !16, null, !17, null, null, !"_ZTSN2ns1DE"} ; [ DW_TAG_structure_type ] [D] [line 28, size 32, align 32, offset 0] [def] [from ]
-!16 = !{!"0x39\00ns\0023", !1, null} ; [ DW_TAG_namespace ] [ns] [line 23]
+!15 = !DICompositeType(tag: DW_TAG_structure_type, name: "D", scope: !16, file: !1, line: 29, size: 32, align: 32, elements: !17, identifier: "_ZTSN2ns1DE")
+!16 = !DINamespace(name: "ns", scope: null, file: !1, line: 23)
 !17 = !{!18}
-!18 = !{!"0xd\00A\0029\0032\0032\000\000", !1, !"_ZTSN2ns1DE", !7} ; [ DW_TAG_member ] [A] [line 29, size 32, align 32, offset 0] [from int]
-!19 = !{!20, !21, !22, !24, !27, !31}
-!20 = !{!"0x2e\00member_function\00member_function\00_ZN1C15member_functionEv\009\000\001\000\006\00256\000\009", !1, !"_ZTS1C", !9, null, void (%struct.C*)* @_ZN1C15member_functionEv, null, !8, !2} ; [ DW_TAG_subprogram ] [line 9] [def] [member_function]
-!21 = !{!"0x2e\00static_member_function\00static_member_function\00_ZN1C22static_member_functionEv\0013\000\001\000\006\00256\000\0013", !1, !"_ZTS1C", !13, null, i32 ()* @_ZN1C22static_member_functionEv, null, !12, !2} ; [ DW_TAG_subprogram ] [line 13] [def] [static_member_function]
-!22 = !{!"0x2e\00global_function\00global_function\00_Z15global_functionv\0019\000\001\000\006\00256\000\0019", !1, !23, !13, null, i32 ()* @_Z15global_functionv, null, null, !2} ; [ DW_TAG_subprogram ] [line 19] [def] [global_function]
-!23 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/tmp/dbginfo/pubnames.cpp]
-!24 = !{!"0x2e\00global_namespace_function\00global_namespace_function\00_ZN2ns25global_namespace_functionEv\0024\000\001\000\006\00256\000\0024", !1, !16, !25, null, void ()* @_ZN2ns25global_namespace_functionEv, null, null, !2} ; [ DW_TAG_subprogram ] [line 24] [def] [global_namespace_function]
-!25 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !26, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!26 = !{null}
-!27 = !{!"0x2e\00f3\00f3\00_Z2f3v\0037\000\001\000\006\00256\000\0037", !1, !23, !28, null, i32* ()* @_Z2f3v, null, null, !2} ; [ DW_TAG_subprogram ] [line 37] [def] [f3]
-!28 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !29, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!29 = !{!30}
-!30 = !{!"0xf\00\000\0064\0064\000\000", null, null, !7} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
-!31 = !{!"0x2e\00f7\00f7\00_Z2f7v\0054\000\001\000\006\00256\000\0054", !1, !23, !13, null, i32 ()* @_Z2f7v, null, null, !2} ; [ DW_TAG_subprogram ] [line 54] [def] [f7]
-!32 = !{!33, !34, !35, !36, !37, !38, !41, !44}
-!33 = !{!"0x34\00static_member_variable\00static_member_variable\00_ZN1C22static_member_variableE\007\000\001", null, !23, !7, i32* @_ZN1C22static_member_variableE, !6} ; [ DW_TAG_variable ] [static_member_variable] [line 7] [def]
-!34 = !{!"0x34\00global_variable\00global_variable\00\0017\000\001", null, !23, !"_ZTS1C", %struct.C* @global_variable, null} ; [ DW_TAG_variable ] [global_variable] [line 17] [def]
-!35 = !{!"0x34\00global_namespace_variable\00global_namespace_variable\00_ZN2ns25global_namespace_variableE\0027\000\001", !16, !23, !7, i32* @_ZN2ns25global_namespace_variableE, null} ; [ DW_TAG_variable ] [global_namespace_variable] [line 27] [def]
-!36 = !{!"0x34\00d\00d\00_ZN2ns1dE\0030\000\001", !16, !23, !"_ZTSN2ns1DE", %"struct.ns::D"* @_ZN2ns1dE, null} ; [ DW_TAG_variable ] [d] [line 30] [def]
-!37 = !{!"0x34\00z\00z\00\0038\001\001", !27, !23, !7, i32* @_ZZ2f3vE1z, null} ; [ DW_TAG_variable ] [z] [line 38] [local] [def]
-!38 = !{!"0x34\00c\00c\00_ZN5outer12_GLOBAL__N_11cE\0050\001\001", !39, !23, !7, i32* @_ZN5outer12_GLOBAL__N_11cE, null} ; [ DW_TAG_variable ] [c] [line 50] [local] [def]
-!39 = !{!"0x39\00\0049", !1, !40} ; [ DW_TAG_namespace ] [line 49]
-!40 = !{!"0x39\00outer\0048", !1, null} ; [ DW_TAG_namespace ] [outer] [line 48]
-!41 = !{!"0x34\00b\00b\00_ZN12_GLOBAL__N_15inner1bE\0044\001\001", !42, !23, !7, i32* @_ZN12_GLOBAL__N_15inner1bE, null} ; [ DW_TAG_variable ] [b] [line 44] [local] [def]
-!42 = !{!"0x39\00inner\0043", !1, !43} ; [ DW_TAG_namespace ] [inner] [line 43]
-!43 = !{!"0x39\00\0033", !1, null} ; [ DW_TAG_namespace ] [line 33]
-!44 = !{!"0x34\00i\00i\00_ZN12_GLOBAL__N_11iE\0034\001\001", !43, !23, !7, i32* @_ZN12_GLOBAL__N_11iE, null} ; [ DW_TAG_variable ] [i] [line 34] [local] [def]
-!45 = !{!46}
-!46 = !{!"0x3a\0040\00", !40, !39} ; [ DW_TAG_imported_module ]
-!47 = !{i32 2, !"Dwarf Version", i32 4}
-!48 = !{i32 2, !"Debug Info Version", i32 2}
-!49 = !{!"clang version 3.5.0 "}
-!50 = !{!"0x101\00this\0016777216\001088", !20, null, !51} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!51 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1C"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1C]
-!52 = !MDLocation(line: 0, scope: !20)
-!53 = !MDLocation(line: 10, scope: !20)
-!54 = !MDLocation(line: 11, scope: !20)
-!55 = !MDLocation(line: 14, scope: !21)
-!56 = !MDLocation(line: 20, scope: !22)
-!57 = !MDLocation(line: 25, scope: !24)
-!58 = !MDLocation(line: 26, scope: !24)
-!59 = !MDLocation(line: 39, scope: !27)
-!60 = !MDLocation(line: 55, scope: !31)
+!18 = !DIDerivedType(tag: DW_TAG_member, name: "A", scope: !"_ZTSN2ns1DE", file: !1, line: 30, baseType: !7, size: 32, align: 32)
+!19 = !{!20, !21, !22, !23, !26, !30}
+!20 = !DISubprogram(name: "member_function", linkageName: "_ZN1C15member_functionEv", scope: !"_ZTS1C", file: !1, line: 9, type: !9, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: false, function: void (%struct.C*)* @_ZN1C15member_functionEv, declaration: !8, variables: !2)
+!21 = !DISubprogram(name: "static_member_function", linkageName: "_ZN1C22static_member_functionEv", scope: !"_ZTS1C", file: !1, line: 13, type: !13, isLocal: false, isDefinition: true, scopeLine: 13, flags: DIFlagPrototyped, isOptimized: false, function: i32 ()* @_ZN1C22static_member_functionEv, declaration: !12, variables: !2)
+!22 = !DISubprogram(name: "global_function", linkageName: "_Z15global_functionv", scope: !1, file: !1, line: 19, type: !13, isLocal: false, isDefinition: true, scopeLine: 19, flags: DIFlagPrototyped, isOptimized: false, function: i32 ()* @_Z15global_functionv, variables: !2)
+!23 = !DISubprogram(name: "global_namespace_function", linkageName: "_ZN2ns25global_namespace_functionEv", scope: !16, file: !1, line: 24, type: !24, isLocal: false, isDefinition: true, scopeLine: 24, flags: DIFlagPrototyped, isOptimized: false, function: void ()* @_ZN2ns25global_namespace_functionEv, variables: !2)
+!24 = !DISubroutineType(types: !25)
+!25 = !{null}
+!26 = !DISubprogram(name: "f3", linkageName: "_Z2f3v", scope: !1, file: !1, line: 40, type: !27, isLocal: false, isDefinition: true, scopeLine: 40, flags: DIFlagPrototyped, isOptimized: false, function: i32* ()* @_Z2f3v, variables: !2)
+!27 = !DISubroutineType(types: !28)
+!28 = !{!29}
+!29 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !7, size: 64, align: 64)
+!30 = !DISubprogram(name: "f7", linkageName: "_Z2f7v", scope: !1, file: !1, line: 57, type: !13, isLocal: false, isDefinition: true, scopeLine: 57, flags: DIFlagPrototyped, isOptimized: false, function: i32 ()* @_Z2f7v, variables: !2)
+!31 = !{!32, !33, !34, !35, !36, !37, !39, !41}
+!32 = !DIGlobalVariable(name: "static_member_variable", linkageName: "_ZN1C22static_member_variableE", scope: !0, file: !1, line: 7, type: !7, isLocal: false, isDefinition: true, variable: i32* @_ZN1C22static_member_variableE, declaration: !6)
+!33 = !DIGlobalVariable(name: "global_variable", scope: !0, file: !1, line: 17, type: !"_ZTS1C", isLocal: false, isDefinition: true, variable: %struct.C* @global_variable)
+!34 = !DIGlobalVariable(name: "global_namespace_variable", linkageName: "_ZN2ns25global_namespace_variableE", scope: !16, file: !1, line: 27, type: !7, isLocal: false, isDefinition: true, variable: i32* @_ZN2ns25global_namespace_variableE)
+!35 = !DIGlobalVariable(name: "d", linkageName: "_ZN2ns1dE", scope: !16, file: !1, line: 31, type: !"_ZTSN2ns1DE", isLocal: false, isDefinition: true, variable: %"struct.ns::D"* @_ZN2ns1dE)
+!36 = !DIGlobalVariable(name: "z", scope: !26, file: !1, line: 41, type: !7, isLocal: true, isDefinition: true, variable: i32* @_ZZ2f3vE1z)
+!37 = !DIGlobalVariable(name: "i", linkageName: "_ZN12_GLOBAL__N_11iE", scope: !38, file: !1, line: 37, type: !7, isLocal: true, isDefinition: true, variable: i32* @_ZN12_GLOBAL__N_11iE)
+!38 = !DINamespace(scope: null, file: !1, line: 36)
+!39 = !DIGlobalVariable(name: "b", linkageName: "_ZN12_GLOBAL__N_15inner1bE", scope: !40, file: !1, line: 47, type: !7, isLocal: true, isDefinition: true, variable: i32* @_ZN12_GLOBAL__N_15inner1bE)
+!40 = !DINamespace(name: "inner", scope: !38, file: !1, line: 46)
+!41 = !DIGlobalVariable(name: "c", linkageName: "_ZN5outer12_GLOBAL__N_11cE", scope: !42, file: !1, line: 53, type: !7, isLocal: true, isDefinition: true, variable: i32* @_ZN5outer12_GLOBAL__N_11cE)
+!42 = !DINamespace(scope: !43, file: !1, line: 52)
+!43 = !DINamespace(name: "outer", scope: null, file: !1, line: 51)
+!44 = !{!45, !47}
+!45 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !0, entity: !46, line: 34)
+!46 = !DIGlobalVariable(name: "global_namespace_variable_decl", linkageName: "_ZN2ns30global_namespace_variable_declE", scope: !16, file: !1, line: 28, type: !7, isLocal: false, isDefinition: false)
+!47 = !DIImportedEntity(tag: DW_TAG_imported_module, scope: !43, entity: !42, line: 43)
+!48 = !{i32 2, !"Dwarf Version", i32 4}
+!49 = !{i32 2, !"Debug Info Version", i32 3}
+!50 = !{!"clang version 3.7.0 (trunk 234897) (llvm/trunk 234911)"}
+!51 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, scope: !20, type: !52, flags: DIFlagArtificial | DIFlagObjectPointer)
+!52 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !"_ZTS1C", size: 64, align: 64)
+!53 = !DIExpression()
+!54 = !DILocation(line: 0, scope: !20)
+!55 = !DILocation(line: 10, scope: !20)
+!56 = !DILocation(line: 11, scope: !20)
+!57 = !DILocation(line: 14, scope: !21)
+!58 = !DILocation(line: 20, scope: !22)
+!59 = !DILocation(line: 25, scope: !23)
+!60 = !DILocation(line: 26, scope: !23)
+!61 = !DILocation(line: 42, scope: !26)
+!62 = !DILocation(line: 58, scope: !30)
diff --git a/test/DebugInfo/X86/header.ll b/test/DebugInfo/X86/header.ll
new file mode 100644
index 000000000000..8575c4a672a2
--- /dev/null
+++ b/test/DebugInfo/X86/header.ll
@@ -0,0 +1,29 @@
+; RUN: llc -mtriple x86_64-pc-linux < %s  | FileCheck %s
+
+; Test that we don't pollute the start of the file with debug sections
+
+; CHECK:       .text
+; CHECK-NEXT: .file	"<stdin>"
+; CHECK-NEXT: .globl	f
+; CHECK-NEXT: .align	16, 0x90
+; CHECK-NEXT: .type	f,@function
+; CHECK-NEXT: f:                                      # @f
+
+; CHECK: .section .debug_str
+
+define void @f() {
+  ret void, !dbg !9
+}
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7, !8}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "foo", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "/foo/test.c", directory: "/foo")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "f", scope: !1, file: !1, line: 1, type: !5, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: true, function: void ()* @f, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{null}
+!7 = !{i32 2, !"Dwarf Version", i32 4}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
+!9 = !DILocation(line: 1, column: 15, scope: !4)
diff --git a/test/DebugInfo/X86/inline-member-function.ll b/test/DebugInfo/X86/inline-member-function.ll
index 68a211fcecc3..73cd1947f4f4 100644
--- a/test/DebugInfo/X86/inline-member-function.ll
+++ b/test/DebugInfo/X86/inline-member-function.ll
@@ -44,13 +44,13 @@ entry:
   %retval = alloca i32, align 4
   %tmp = alloca %struct.foo, align 1
   store i32 0, i32* %retval
-  %0 = load i32* @i, align 4, !dbg !23
+  %0 = load i32, i32* @i, align 4, !dbg !23
   store %struct.foo* %tmp, %struct.foo** %this.addr.i, align 8
-  call void @llvm.dbg.declare(metadata %struct.foo** %this.addr.i, metadata !24, metadata !{!"0x102"}), !dbg !26
+  call void @llvm.dbg.declare(metadata %struct.foo** %this.addr.i, metadata !24, metadata !DIExpression()), !dbg !26
   store i32 %0, i32* %x.addr.i, align 4
-  call void @llvm.dbg.declare(metadata i32* %x.addr.i, metadata !27, metadata !{!"0x102"}), !dbg !28
-  %this1.i = load %struct.foo** %this.addr.i
-  %1 = load i32* %x.addr.i, align 4, !dbg !28
+  call void @llvm.dbg.declare(metadata i32* %x.addr.i, metadata !27, metadata !DIExpression()), !dbg !28
+  %this1.i = load %struct.foo*, %struct.foo** %this.addr.i
+  %1 = load i32, i32* %x.addr.i, align 4, !dbg !28
   %add.i = add nsw i32 %1, 2, !dbg !28
   ret i32 %add.i, !dbg !23
 }
@@ -65,32 +65,31 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!20, !21}
 !llvm.ident = !{!22}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !3, !12, !18, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/inline.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"inline.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !12, globals: !18, imports: !2)
+!1 = !DIFile(filename: "inline.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00foo\001\008\008\000\000\000", !1, null, null, !5, null, null, !"_ZTS3foo"} ; [ DW_TAG_structure_type ] [foo] [line 1, size 8, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo", line: 1, size: 8, align: 8, file: !1, elements: !5, identifier: "_ZTS3foo")
 !5 = !{!6}
-!6 = !{!"0x2e\00func\00func\00_ZN3foo4funcEi\002\000\000\000\006\00256\000\002", !1, !"_ZTS3foo", !7, null, null, null, i32 0, !11} ; [ DW_TAG_subprogram ] [line 2] [func]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DISubprogram(name: "func", linkageName: "_ZN3foo4funcEi", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !"_ZTS3foo", type: !7)
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !10, !9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS3foo"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS3foo]
-!11 = !{i32 786468}
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS3foo")
 !12 = !{!13, !17}
-!13 = !{!"0x2e\00main\00main\00\007\000\001\000\006\00256\000\007", !1, !14, !15, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 7] [def] [main]
-!14 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/tmp/dbginfo/inline.cpp]
-!15 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DISubprogram(name: "main", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !1, scope: !14, type: !15, function: i32 ()* @main, variables: !2)
+!14 = !DIFile(filename: "inline.cpp", directory: "/tmp/dbginfo")
+!15 = !DISubroutineType(types: !16)
 !16 = !{!9}
-!17 = !{!"0x2e\00func\00func\00_ZN3foo4funcEi\002\000\001\000\006\00256\000\002", !1, !"_ZTS3foo", !7, null, null, null, !6, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [func]
+!17 = !DISubprogram(name: "func", linkageName: "_ZN3foo4funcEi", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !"_ZTS3foo", type: !7, declaration: !6, variables: !2)
 !18 = !{!19}
-!19 = !{!"0x34\00i\00i\00\005\000\001", null, !14, !9, i32* @i, null} ; [ DW_TAG_variable ] [i] [line 5] [def]
+!19 = !DIGlobalVariable(name: "i", line: 5, isLocal: false, isDefinition: true, scope: null, file: !14, type: !9, variable: i32* @i)
 !20 = !{i32 2, !"Dwarf Version", i32 4}
-!21 = !{i32 1, !"Debug Info Version", i32 2}
+!21 = !{i32 1, !"Debug Info Version", i32 3}
 !22 = !{!"clang version 3.5.0 "}
-!23 = !MDLocation(line: 8, scope: !13)
-!24 = !{!"0x101\00this\0016777216\001088", !17, null, !25} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!25 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS3foo"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS3foo]
-!26 = !MDLocation(line: 0, scope: !17, inlinedAt: !23)
-!27 = !{!"0x101\00x\0033554434\000", !17, !14, !9} ; [ DW_TAG_arg_variable ] [x] [line 2]
-!28 = !MDLocation(line: 2, scope: !17, inlinedAt: !23)
+!23 = !DILocation(line: 8, scope: !13)
+!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !17, type: !25)
+!25 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS3foo")
+!26 = !DILocation(line: 0, scope: !17, inlinedAt: !23)
+!27 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 2, arg: 2, scope: !17, file: !14, type: !9)
+!28 = !DILocation(line: 2, scope: !17, inlinedAt: !23)
diff --git a/test/DebugInfo/X86/inline-seldag-test.ll b/test/DebugInfo/X86/inline-seldag-test.ll
index 8c10e3a859d9..c8e75cf3fcb3 100644
--- a/test/DebugInfo/X86/inline-seldag-test.ll
+++ b/test/DebugInfo/X86/inline-seldag-test.ll
@@ -27,11 +27,11 @@ define void @func() #0 {
 entry:
   %y.addr.i = alloca i32, align 4
   %x = alloca i32, align 4
-  call void @llvm.dbg.declare(metadata i32* %x, metadata !15, metadata !{!"0x102"}), !dbg !17
-  %0 = load volatile i32* %x, align 4, !dbg !18
+  call void @llvm.dbg.declare(metadata i32* %x, metadata !15, metadata !DIExpression()), !dbg !17
+  %0 = load volatile i32, i32* %x, align 4, !dbg !18
   store i32 %0, i32* %y.addr.i, align 4
-  call void @llvm.dbg.declare(metadata i32* %y.addr.i, metadata !19, metadata !{!"0x102"}), !dbg !20
-  %1 = load i32* %y.addr.i, align 4, !dbg !21
+  call void @llvm.dbg.declare(metadata i32* %y.addr.i, metadata !19, metadata !DIExpression()), !dbg !20
+  %1 = load i32, i32* %y.addr.i, align 4, !dbg !21
   %tobool.i = icmp ne i32 %1, 0, !dbg !21
   %cond.i = select i1 %tobool.i, i32 4, i32 7, !dbg !21
   store volatile i32 %cond.i, i32* %x, align 4, !dbg !18
@@ -48,26 +48,26 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!12, !13}
 !llvm.ident = !{!14}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/inline-seldag-test.c] [DW_LANG_C99]
-!1 = !{!"inline-seldag-test.c", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "inline-seldag-test.c", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4, !8}
-!4 = !{!"0x2e\00func\00func\00\004\000\001\000\006\000\000\004", !1, !5, !6, null, void ()* @func, null, null, !2} ; [ DW_TAG_subprogram ] [line 4] [def] [func]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/inline-seldag-test.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "func", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 4, file: !1, scope: !5, type: !6, function: void ()* @func, variables: !2)
+!5 = !DIFile(filename: "inline-seldag-test.c", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
-!8 = !{!"0x2e\00f\00f\00\001\000\001\000\006\00256\000\001", !1, !5, !9, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [f]
-!9 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = !DISubprogram(name: "f", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !9, variables: !2)
+!9 = !DISubroutineType(types: !10)
 !10 = !{!11, !11}
-!11 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !12 = !{i32 2, !"Dwarf Version", i32 4}
-!13 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = !{i32 1, !"Debug Info Version", i32 3}
 !14 = !{!"clang version 3.5.0 "}
-!15 = !{!"0x100\00x\005\000", !4, !5, !16} ; [ DW_TAG_auto_variable ] [x] [line 5]
-!16 = !{!"0x35\00\000\000\000\000\000", null, null, !11} ; [ DW_TAG_volatile_type ] [line 0, size 0, align 0, offset 0] [from int]
-!17 = !MDLocation(line: 5, scope: !4)
-!18 = !MDLocation(line: 6, column: 7, scope: !4)
-!19 = !{!"0x101\00y\0016777217\000", !8, !5, !11} ; [ DW_TAG_arg_variable ] [y] [line 1]
-!20 = !MDLocation(line: 1, scope: !8, inlinedAt: !18)
-!21 = !MDLocation(line: 2, scope: !8, inlinedAt: !18)
-!22 = !MDLocation(line: 7, scope: !4)
+!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 5, scope: !4, file: !5, type: !16)
+!16 = !DIDerivedType(tag: DW_TAG_volatile_type, baseType: !11)
+!17 = !DILocation(line: 5, scope: !4)
+!18 = !DILocation(line: 6, column: 7, scope: !4)
+!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "y", line: 1, arg: 1, scope: !8, file: !5, type: !11)
+!20 = !DILocation(line: 1, scope: !8, inlinedAt: !18)
+!21 = !DILocation(line: 2, scope: !8, inlinedAt: !18)
+!22 = !DILocation(line: 7, scope: !4)
diff --git a/test/DebugInfo/X86/inlined-formal-parameter.ll b/test/DebugInfo/X86/inlined-formal-parameter.ll
new file mode 100644
index 000000000000..3cc4e5a65a66
--- /dev/null
+++ b/test/DebugInfo/X86/inlined-formal-parameter.ll
@@ -0,0 +1,75 @@
+; RUN: llc -filetype=obj -o %t.o %s
+; RUN: llvm-dwarfdump -debug-dump=info %t.o | FileCheck %s
+
+; Testcase generated using 'clang -g -O2 -S -emit-llvm' from the following:
+;; void sink(void);
+;; static __attribute__((always_inline)) void bar(int a) { sink(); }
+;; void foo(void) {
+;;   bar(0);
+;;   bar(0);
+;; }
+
+; Check that we have formal parameters for 'a' in both inlined subroutines.
+; CHECK:       DW_TAG_inlined_subroutine
+; CHECK-NEXT:    DW_AT_abstract_origin {{.*}} "bar"
+; CHECK:         DW_TAG_formal_parameter
+; CHECK-NEXT:      DW_AT_const_value
+; CHECK-NEXT:      DW_AT_abstract_origin {{.*}} "a"
+; CHECK:       DW_TAG_inlined_subroutine
+; CHECK-NEXT:    DW_AT_abstract_origin {{.*}} "bar"
+; CHECK:         DW_TAG_formal_parameter
+; CHECK-NEXT:      DW_AT_const_value
+; CHECK-NEXT:      DW_AT_abstract_origin {{.*}} "a"
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-darwin"
+
+; Function Attrs: nounwind ssp uwtable
+define void @foo() #0 {
+entry:
+  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !12, metadata !17) #3, !dbg !18
+  tail call void @sink() #3, !dbg !20
+  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !12, metadata !17) #3, !dbg !21
+  tail call void @sink() #3, !dbg !23
+  ret void, !dbg !24
+}
+
+declare void @sink() #1
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2
+
+attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="core2" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="core2" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!13, !14, !15}
+!llvm.ident = !{!16}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 235110) (llvm/trunk 235108)", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "t.c", directory: "/path/to/dir")
+!2 = !{}
+!3 = !{!4, !7}
+!4 = !DISubprogram(name: "foo", scope: !1, file: !1, line: 3, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: true, function: void ()* @foo, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{null}
+!7 = !DISubprogram(name: "bar", scope: !1, file: !1, line: 2, type: !8, isLocal: true, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, variables: !11)
+!8 = !DISubroutineType(types: !9)
+!9 = !{null, !10}
+!10 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!11 = !{!12}
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", arg: 1, scope: !7, file: !1, line: 2, type: !10)
+!13 = !{i32 2, !"Dwarf Version", i32 2}
+!14 = !{i32 2, !"Debug Info Version", i32 3}
+!15 = !{i32 1, !"PIC Level", i32 2}
+!16 = !{!"clang version 3.7.0 (trunk 235110) (llvm/trunk 235108)"}
+!17 = !DIExpression()
+!18 = !DILocation(line: 2, column: 52, scope: !7, inlinedAt: !19)
+!19 = distinct !DILocation(line: 4, column: 3, scope: !4)
+!20 = !DILocation(line: 2, column: 57, scope: !7, inlinedAt: !19)
+!21 = !DILocation(line: 2, column: 52, scope: !7, inlinedAt: !22)
+!22 = distinct !DILocation(line: 5, column: 3, scope: !4)
+!23 = !DILocation(line: 2, column: 57, scope: !7, inlinedAt: !22)
+!24 = !DILocation(line: 6, column: 1, scope: !4)
diff --git a/test/DebugInfo/X86/instcombine-instrinsics.ll b/test/DebugInfo/X86/instcombine-instrinsics.ll
index 12b99a359496..8241e6498f96 100644
--- a/test/DebugInfo/X86/instcombine-instrinsics.ll
+++ b/test/DebugInfo/X86/instcombine-instrinsics.ll
@@ -30,12 +30,12 @@ target triple = "x86_64-apple-macosx10.9.0"
 ; Function Attrs: nounwind ssp uwtable
 define void @init() #0 {
   %p = alloca %struct.i14*, align 8
-  call void @llvm.dbg.declare(metadata %struct.i14** %p, metadata !11, metadata !{!"0x102"}), !dbg !18
+  call void @llvm.dbg.declare(metadata %struct.i14** %p, metadata !11, metadata !DIExpression()), !dbg !18
   store %struct.i14* null, %struct.i14** %p, align 8, !dbg !18
   %1 = call i32 @foo(%struct.i14** %p), !dbg !19
-  %2 = load %struct.i14** %p, align 8, !dbg !20
-  %3 = getelementptr inbounds %struct.i14* %2, i32 0, i32 0, !dbg !20
-  %4 = load i64* %3, align 8, !dbg !20
+  %2 = load %struct.i14*, %struct.i14** %p, align 8, !dbg !20
+  %3 = getelementptr inbounds %struct.i14, %struct.i14* %2, i32 0, i32 0, !dbg !20
+  %4 = load i64, i64* %3, align 8, !dbg !20
   %5 = or i64 %4, 4, !dbg !20
   store i64 %5, i64* %3, align 8, !dbg !20
   %6 = call i32 @foo(%struct.i14** %p), !dbg !21
@@ -54,26 +54,26 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!8, !9}
 !llvm.ident = !{!10}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [instcombine_intrinsics.c] [DW_LANG_C99]
-!1 = !{!"instcombine_intrinsics.c", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "instcombine_intrinsics.c", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00init\00init\00\007\000\001\000\006\000\000\007", !1, !5, !6, null, void ()* @init, null, null, !2} ; [ DW_TAG_subprogram ] [line 7] [def] [init]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [instcombine_intrinsics.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "init", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 7, file: !1, scope: !5, type: !6, function: void ()* @init, variables: !2)
+!5 = !DIFile(filename: "instcombine_intrinsics.c", directory: "")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
 !8 = !{i32 2, !"Dwarf Version", i32 2}
-!9 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !{i32 1, !"Debug Info Version", i32 3}
 !10 = !{!"clang version 3.5.0 "}
-!11 = !{!"0x100\00p\008\000", !4, !5, !12} ; [ DW_TAG_auto_variable ] [p] [line 8]
-!12 = !{!"0xf\00\000\0064\0064\000\000", null, null, !13} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from i14]
-!13 = !{!"0x16\00i14\003\000\000\000\000", !1, null, !14} ; [ DW_TAG_typedef ] [i14] [line 3, size 0, align 0, offset 0] [from ]
-!14 = !{!"0x13\00\001\0064\0064\000\000\000", !1, null, null, !15, null, null, null} ; [ DW_TAG_structure_type ] [line 1, size 64, align 64, offset 0] [def] [from ]
+!11 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "p", line: 8, scope: !4, file: !5, type: !12)
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !13)
+!13 = !DIDerivedType(tag: DW_TAG_typedef, name: "i14", line: 3, file: !1, baseType: !14)
+!14 = !DICompositeType(tag: DW_TAG_structure_type, line: 1, size: 64, align: 64, file: !1, elements: !15)
 !15 = !{!16}
-!16 = !{!"0xd\00i\002\0064\0064\000\000", !1, !14, !17} ; [ DW_TAG_member ] [i] [line 2, size 64, align 64, offset 0] [from long int]
-!17 = !{!"0x24\00long int\000\0064\0064\000\000\005", null, null} ; [ DW_TAG_base_type ] [long int] [line 0, size 64, align 64, offset 0, enc DW_ATE_signed]
-!18 = !MDLocation(line: 8, scope: !4)
-!19 = !MDLocation(line: 9, scope: !4)
-!20 = !MDLocation(line: 10, scope: !4)
-!21 = !MDLocation(line: 11, scope: !4)
-!22 = !MDLocation(line: 12, scope: !4)
+!16 = !DIDerivedType(tag: DW_TAG_member, name: "i", line: 2, size: 64, align: 64, file: !1, scope: !14, baseType: !17)
+!17 = !DIBasicType(tag: DW_TAG_base_type, name: "long int", size: 64, align: 64, encoding: DW_ATE_signed)
+!18 = !DILocation(line: 8, scope: !4)
+!19 = !DILocation(line: 9, scope: !4)
+!20 = !DILocation(line: 10, scope: !4)
+!21 = !DILocation(line: 11, scope: !4)
+!22 = !DILocation(line: 12, scope: !4)
diff --git a/test/DebugInfo/X86/lexical_block.ll b/test/DebugInfo/X86/lexical_block.ll
index a9e377a01810..2619f12f69ed 100644
--- a/test/DebugInfo/X86/lexical_block.ll
+++ b/test/DebugInfo/X86/lexical_block.ll
@@ -25,9 +25,9 @@
 define void @_Z1bv() #0 {
 entry:
   %i = alloca i32, align 4
-  call void @llvm.dbg.declare(metadata i32* %i, metadata !11, metadata !{!"0x102"}), !dbg !14
+  call void @llvm.dbg.declare(metadata i32* %i, metadata !11, metadata !DIExpression()), !dbg !14
   store i32 3, i32* %i, align 4, !dbg !14
-  %0 = load i32* %i, align 4, !dbg !14
+  %0 = load i32, i32* %i, align 4, !dbg !14
   %tobool = icmp ne i32 %0, 0, !dbg !14
   br i1 %tobool, label %if.then, label %if.end, !dbg !14
 
@@ -48,20 +48,20 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!8, !9}
 !llvm.ident = !{!10}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/lexical_block.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"lexical_block.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "lexical_block.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00b\00b\00_Z1bv\001\000\001\000\006\00256\000\001", !1, !5, !6, null, void ()* @_Z1bv, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [b]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/lexical_block.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "b", linkageName: "_Z1bv", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void ()* @_Z1bv, variables: !2)
+!5 = !DIFile(filename: "lexical_block.cpp", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
 !8 = !{i32 2, !"Dwarf Version", i32 4}
-!9 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !{i32 1, !"Debug Info Version", i32 3}
 !10 = !{!"clang version 3.5.0 "}
-!11 = !{!"0x100\00i\002\000", !12, !5, !13} ; [ DW_TAG_auto_variable ] [i] [line 2]
-!12 = !{!"0xb\002\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/lexical_block.cpp]
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!14 = !MDLocation(line: 2, scope: !12)
-!15 = !MDLocation(line: 3, scope: !12)
-!16 = !MDLocation(line: 4, scope: !4)
+!11 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 2, scope: !12, file: !5, type: !13)
+!12 = distinct !DILexicalBlock(line: 2, column: 0, file: !1, scope: !4)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!14 = !DILocation(line: 2, scope: !12)
+!15 = !DILocation(line: 3, scope: !12)
+!16 = !DILocation(line: 4, scope: !4)
diff --git a/test/DebugInfo/X86/line-info.ll b/test/DebugInfo/X86/line-info.ll
index e4364268021b..a3d957f8bc48 100644
--- a/test/DebugInfo/X86/line-info.ll
+++ b/test/DebugInfo/X86/line-info.ll
@@ -18,8 +18,8 @@ define i32 @foo(i32 %x) #0 {
 entry:
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !14, metadata !{!"0x102"}), !dbg !15
-  %0 = load i32* %x.addr, align 4, !dbg !16
+  call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !14, metadata !DIExpression()), !dbg !15
+  %0 = load i32, i32* %x.addr, align 4, !dbg !16
   %inc = add nsw i32 %0, 1, !dbg !16
   store i32 %inc, i32* %x.addr, align 4, !dbg !16
   ret i32 %inc, !dbg !16
@@ -38,23 +38,23 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!19}
 
-!0 = !{!"0x11\0012\00clang version 3.3 \000\00\000\00\000", !1, !2, !2, !3, !2,  !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/blaikie/dev/scratch/list0.c] [DW_LANG_C99]
-!1 = !{!"list0.c", !"/usr/local/google/home/blaikie/dev/scratch"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.3 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports:  !2)
+!1 = !DIFile(filename: "list0.c", directory: "/usr/local/google/home/blaikie/dev/scratch")
 !2 = !{}
 !3 = !{!4, !10}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\000\001", !5, !6, !7, null, i32 (i32)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"./list0.h", !"/usr/local/google/home/blaikie/dev/scratch"}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [/usr/local/google/home/blaikie/dev/scratch/./list0.h]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !5, scope: !6, type: !7, function: i32 (i32)* @foo, variables: !2)
+!5 = !DIFile(filename: "./list0.h", directory: "/usr/local/google/home/blaikie/dev/scratch")
+!6 = !DIFile(filename: "./list0.h", directory: "/usr/local/google/home/blaikie/dev/scratch")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"0x2e\00main\00main\00\002\000\001\000\006\000\000\002", !1, !11, !12, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [main]
-!11 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/usr/local/google/home/blaikie/dev/scratch/list0.c]
-!12 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !13, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DISubprogram(name: "main", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 2, file: !1, scope: !11, type: !12, function: i32 ()* @main, variables: !2)
+!11 = !DIFile(filename: "list0.c", directory: "/usr/local/google/home/blaikie/dev/scratch")
+!12 = !DISubroutineType(types: !13)
 !13 = !{!9}
-!14 = !{!"0x101\00x\0016777217\000", !4, !6, !9} ; [ DW_TAG_arg_variable ] [x] [line 1]
-!15 = !MDLocation(line: 1, scope: !4)
-!16 = !MDLocation(line: 2, scope: !4)
-!17 = !MDLocation(line: 3, scope: !18)
-!18 = !{!"0xb\000", !11, !10} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/blaikie/dev/scratch/list0.c]
-!19 = !{i32 1, !"Debug Info Version", i32 2}
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 1, arg: 1, scope: !4, file: !6, type: !9)
+!15 = !DILocation(line: 1, scope: !4)
+!16 = !DILocation(line: 2, scope: !4)
+!17 = !DILocation(line: 3, scope: !18)
+!18 = !DILexicalBlockFile(discriminator: 0, file: !11, scope: !10)
+!19 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/line.test b/test/DebugInfo/X86/line.test
new file mode 100644
index 000000000000..24d9c5cbce0d
--- /dev/null
+++ b/test/DebugInfo/X86/line.test
@@ -0,0 +1 @@
+; RUN: llc -mtriple=x86_64-linux -O0 -filetype=asm < %S/../Inputs/line.ll | FileCheck %S/../Inputs/line.ll
diff --git a/test/DebugInfo/X86/linkage-name.ll b/test/DebugInfo/X86/linkage-name.ll
index 187ff8bce3af..330a7f9e53a1 100644
--- a/test/DebugInfo/X86/linkage-name.ll
+++ b/test/DebugInfo/X86/linkage-name.ll
@@ -2,7 +2,7 @@
 ; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s
 
 ; CHECK: DW_TAG_subprogram [9] *
-; CHECK-NOT: DW_AT_MIPS_linkage_name
+; CHECK-NOT: DW_AT_{{(MIPS_)?}}linkage_name
 ; CHECK: DW_AT_specification
 
 %class.A = type { i8 }
@@ -14,11 +14,11 @@ entry:
   %this.addr = alloca %class.A*, align 8
   %b.addr = alloca i32, align 4
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !21, metadata !{!"0x102"}), !dbg !23
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !21, metadata !DIExpression()), !dbg !23
   store i32 %b, i32* %b.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %b.addr, metadata !24, metadata !{!"0x102"}), !dbg !25
-  %this1 = load %class.A** %this.addr
-  %0 = load i32* %b.addr, align 4, !dbg !26
+  call void @llvm.dbg.declare(metadata i32* %b.addr, metadata !24, metadata !DIExpression()), !dbg !25
+  %this1 = load %class.A*, %class.A** %this.addr
+  %0 = load i32, i32* %b.addr, align 4, !dbg !26
   ret i32 %0, !dbg !26
 }
 
@@ -27,26 +27,26 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!29}
 
-!0 = !{!"0x11\004\00clang version 3.1 (trunk 152691) (llvm/trunk 152692)\000\00\000\00\000", !28, !1, !1, !3, !18,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.1 (trunk 152691) (llvm/trunk 152692)", isOptimized: false, emissionKind: 0, file: !28, enums: !1, retainedTypes: !1, subprograms: !3, globals: !18, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00a\00a\00_ZN1A1aEi\005\000\001\000\006\00256\000\005", !6, null, !7, null, i32 (%class.A*, i32)* @_ZN1A1aEi, null, !13, null} ; [ DW_TAG_subprogram ]
-!6 = !{!"0x29", !28} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "a", linkageName: "_ZN1A1aEi", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !6, scope: null, type: !7, function: i32 (%class.A*, i32)* @_ZN1A1aEi, declaration: !13)
+!6 = !DIFile(filename: "foo.cpp", directory: "/Users/echristo")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !10, !9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!10 = !{!"0xf\00\000\0064\0064\000\0064", i32 0, null, !11} ; [ DW_TAG_pointer_type ]
-!11 = !{!"0x2\00A\001\008\008\000\000\000", !28, null, null, !12, null, null, null} ; [ DW_TAG_class_type ] [A] [line 1, size 8, align 8, offset 0] [def] [from ]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, baseType: !11)
+!11 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 1, size: 8, align: 8, file: !28, elements: !12)
 !12 = !{!13}
-!13 = !{!"0x2e\00a\00a\00_ZN1A1aEi\002\000\000\000\006\00257\000\000", !6, !11, !7, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ]
+!13 = !DISubprogram(name: "a", linkageName: "_ZN1A1aEi", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrivate | DIFlagPrototyped, isOptimized: false, file: !6, scope: !11, type: !7)
 !18 = !{!20}
-!20 = !{!"0x34\00a\00a\00\009\000\001", null, !6, !11, %class.A* @a, null} ; [ DW_TAG_variable ]
-!21 = !{!"0x101\00this\0016777221\0064", !5, !6, !22} ; [ DW_TAG_arg_variable ]
-!22 = !{!"0xf\00\000\0064\0064\000\000", null, null, !11} ; [ DW_TAG_pointer_type ]
-!23 = !MDLocation(line: 5, column: 8, scope: !5)
-!24 = !{!"0x101\00b\0033554437\000", !5, !6, !9} ; [ DW_TAG_arg_variable ]
-!25 = !MDLocation(line: 5, column: 14, scope: !5)
-!26 = !MDLocation(line: 6, column: 4, scope: !27)
-!27 = !{!"0xb\005\0017\000", !6, !5} ; [ DW_TAG_lexical_block ]
-!28 = !{!"foo.cpp", !"/Users/echristo"}
-!29 = !{i32 1, !"Debug Info Version", i32 2}
+!20 = !DIGlobalVariable(name: "a", line: 9, isLocal: false, isDefinition: true, scope: null, file: !6, type: !11, variable: %class.A* @a)
+!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 5, arg: 1, flags: DIFlagArtificial, scope: !5, file: !6, type: !22)
+!22 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !11)
+!23 = !DILocation(line: 5, column: 8, scope: !5)
+!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 5, arg: 2, scope: !5, file: !6, type: !9)
+!25 = !DILocation(line: 5, column: 14, scope: !5)
+!26 = !DILocation(line: 6, column: 4, scope: !27)
+!27 = distinct !DILexicalBlock(line: 5, column: 17, file: !6, scope: !5)
+!28 = !DIFile(filename: "foo.cpp", directory: "/Users/echristo")
+!29 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/low-pc-cu.ll b/test/DebugInfo/X86/low-pc-cu.ll
index cac572e1b2c8..727a7bb3dec1 100644
--- a/test/DebugInfo/X86/low-pc-cu.ll
+++ b/test/DebugInfo/X86/low-pc-cu.ll
@@ -32,15 +32,15 @@ attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointe
 !llvm.module.flags = !{!8, !9}
 !llvm.ident = !{!10}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 (trunk 204164) (llvm/trunk 204183)\000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/z.c] [DW_LANG_C99]
-!1 = !{!"z.c", !"/usr/local/google/home/echristo"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 (trunk 204164) (llvm/trunk 204183)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "z.c", directory: "/usr/local/google/home/echristo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00z\00z\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, void ()* @z, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [z]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/usr/local/google/home/echristo/z.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "z", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void ()* @z, variables: !2)
+!5 = !DIFile(filename: "z.c", directory: "/usr/local/google/home/echristo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
 !8 = !{i32 2, !"Dwarf Version", i32 4}
-!9 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !{i32 1, !"Debug Info Version", i32 3}
 !10 = !{!"clang version 3.5.0 (trunk 204164) (llvm/trunk 204183)"}
-!11 = !MDLocation(line: 1, scope: !4)
+!11 = !DILocation(line: 1, scope: !4)
diff --git a/test/DebugInfo/X86/memberfnptr.ll b/test/DebugInfo/X86/memberfnptr.ll
index 6d346011a68e..a53264d2c856 100644
--- a/test/DebugInfo/X86/memberfnptr.ll
+++ b/test/DebugInfo/X86/memberfnptr.ll
@@ -24,21 +24,21 @@ declare void @_ZN1A3fooEv(%struct.A*)
 !llvm.module.flags = !{!14, !15, !16}
 !llvm.ident = !{!17}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 \000\00\000\00\001", !1, !2, !3, !2, !10, !2} ; [ DW_TAG_compile_unit ] [/memberfnptr.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"memberfnptr.cpp", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !2, globals: !10, imports: !2)
+!1 = !DIFile(filename: "memberfnptr.cpp", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00A\001\008\008\000\000\000", !1, null, null, !5, null, null, !"_ZTS1A"} ; [ DW_TAG_structure_type ] [A] [line 1, size 8, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "A", line: 1, size: 8, align: 8, file: !1, elements: !5, identifier: "_ZTS1A")
 !5 = !{!6}
-!6 = !{!"0x2e\00foo\00foo\00_ZN1A3fooEv\002\000\000\000\000\00256\000\002", !1, !"_ZTS1A", !7, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 2] [foo]
-!7 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DISubprogram(name: "foo", linkageName: "_ZN1A3fooEv", line: 2, isLocal: false, isDefinition: false, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !"_ZTS1A", type: !7)
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9}
-!9 = !{!"0xf\00\000\0064\0064\000\001088\00", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1A]
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1A")
 !10 = !{!11}
-!11 = !{!"0x34\00p\00p\00\005\000\001", null, !12, !13, { i64, i64 }* @p, null} ; [ DW_TAG_variable ] [p] [line 5] [def]
-!12 = !{!"0x29", !1}                              ; [ DW_TAG_file_type ] [/memberfnptr.cpp]
-!13 = !{!"0x1f\00\000\0064\000\000\000", null, null, !7, !"_ZTS1A"} ; [ DW_TAG_ptr_to_member_type ] [line 0, size 64, align 0, offset 0] [from ]
+!11 = !DIGlobalVariable(name: "p", line: 5, isLocal: false, isDefinition: true, scope: null, file: !12, type: !13, variable: { i64, i64 }* @p)
+!12 = !DIFile(filename: "memberfnptr.cpp", directory: "")
+!13 = !DIDerivedType(tag: DW_TAG_ptr_to_member_type, size: 64, baseType: !7, extraData: !"_ZTS1A")
 !14 = !{i32 2, !"Dwarf Version", i32 2}
-!15 = !{i32 2, !"Debug Info Version", i32 2}
+!15 = !{i32 2, !"Debug Info Version", i32 3}
 !16 = !{i32 1, !"PIC Level", i32 2}
 !17 = !{!"clang version 3.6.0 "}
diff --git a/test/DebugInfo/X86/mi-print.ll b/test/DebugInfo/X86/mi-print.ll
new file mode 100644
index 000000000000..b5d7b0ef067f
--- /dev/null
+++ b/test/DebugInfo/X86/mi-print.ll
@@ -0,0 +1,56 @@
+; RUN: llc -debug -mtriple x86_64-apple-darwin < %s -o /dev/null 2>&1 | FileCheck %s
+; REQUIRES: asserts
+; Check that llc -debug actually prints variables and locations, rather than
+; crashing.
+
+; CHECK: DBG_VALUE
+
+; Generated using `clang -g -O2 -S -emit-llvm -g` on the following source:
+;
+; static int foo(int x) { return x; }
+; int bar(int x) { return foo(x); }
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+; Function Attrs: nounwind readnone ssp uwtable
+define i32 @bar(i32 %x) #0 {
+entry:
+  tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !9, metadata !17), !dbg !18
+  tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !19, metadata !17), !dbg !21
+  ret i32 %x, !dbg !22
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
+
+attributes #0 = { nounwind readnone ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="core2" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!13, !14, !15}
+!llvm.ident = !{!16}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 233919) (llvm/trunk 233920)", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "t.c", directory: "/Users/dexonsmith/data/llvm/debug-info/test/DebugInfo/X86")
+!2 = !{}
+!3 = !{!4, !10}
+!4 = !DISubprogram(name: "bar", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, function: i32 (i32)* @bar, variables: !8)
+!5 = !DISubroutineType(types: !6)
+!6 = !{!7, !7}
+!7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !{!9}
+!9 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", arg: 1, scope: !4, file: !1, line: 2, type: !7)
+!10 = !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !5, isLocal: true, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: true, variables: !11)
+!11 = !{!12}
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", arg: 1, scope: !10, file: !1, line: 1, type: !7)
+!13 = !{i32 2, !"Dwarf Version", i32 2}
+!14 = !{i32 2, !"Debug Info Version", i32 3}
+!15 = !{i32 1, !"PIC Level", i32 2}
+!16 = !{!"clang version 3.7.0 (trunk 233919) (llvm/trunk 233920)"}
+!17 = !DIExpression()
+!18 = !DILocation(line: 2, column: 13, scope: !4)
+!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", arg: 1, scope: !10, file: !1, line: 1, type: !7)
+!20 = distinct !DILocation(line: 2, column: 25, scope: !4)
+!21 = !DILocation(line: 1, column: 20, scope: !10, inlinedAt: !20)
+!22 = !DILocation(line: 2, column: 18, scope: !4)
diff --git a/test/DebugInfo/X86/misched-dbg-value.ll b/test/DebugInfo/X86/misched-dbg-value.ll
index 709b6b2194e3..c660e1f72a9f 100644
--- a/test/DebugInfo/X86/misched-dbg-value.ll
+++ b/test/DebugInfo/X86/misched-dbg-value.ll
@@ -48,33 +48,33 @@
 
 define void @Proc8(i32* nocapture %Array1Par, [51 x i32]* nocapture %Array2Par, i32 %IntParI1, i32 %IntParI2) nounwind optsize {
 entry:
-  tail call void @llvm.dbg.value(metadata i32* %Array1Par, i64 0, metadata !23, metadata !{!"0x102"}), !dbg !64
-  tail call void @llvm.dbg.value(metadata [51 x i32]* %Array2Par, i64 0, metadata !24, metadata !{!"0x102"}), !dbg !65
-  tail call void @llvm.dbg.value(metadata i32 %IntParI1, i64 0, metadata !25, metadata !{!"0x102"}), !dbg !66
-  tail call void @llvm.dbg.value(metadata i32 %IntParI2, i64 0, metadata !26, metadata !{!"0x102"}), !dbg !67
+  tail call void @llvm.dbg.value(metadata i32* %Array1Par, i64 0, metadata !23, metadata !DIExpression()), !dbg !64
+  tail call void @llvm.dbg.value(metadata [51 x i32]* %Array2Par, i64 0, metadata !24, metadata !DIExpression()), !dbg !65
+  tail call void @llvm.dbg.value(metadata i32 %IntParI1, i64 0, metadata !25, metadata !DIExpression()), !dbg !66
+  tail call void @llvm.dbg.value(metadata i32 %IntParI2, i64 0, metadata !26, metadata !DIExpression()), !dbg !67
   %add = add i32 %IntParI1, 5, !dbg !68
-  tail call void @llvm.dbg.value(metadata i32 %add, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !68
+  tail call void @llvm.dbg.value(metadata i32 %add, i64 0, metadata !27, metadata !DIExpression()), !dbg !68
   %idxprom = sext i32 %add to i64, !dbg !69
-  %arrayidx = getelementptr inbounds i32* %Array1Par, i64 %idxprom, !dbg !69
+  %arrayidx = getelementptr inbounds i32, i32* %Array1Par, i64 %idxprom, !dbg !69
   store i32 %IntParI2, i32* %arrayidx, align 4, !dbg !69
   %add3 = add nsw i32 %IntParI1, 6, !dbg !73
   %idxprom4 = sext i32 %add3 to i64, !dbg !73
-  %arrayidx5 = getelementptr inbounds i32* %Array1Par, i64 %idxprom4, !dbg !73
+  %arrayidx5 = getelementptr inbounds i32, i32* %Array1Par, i64 %idxprom4, !dbg !73
   store i32 %IntParI2, i32* %arrayidx5, align 4, !dbg !73
   %add6 = add nsw i32 %IntParI1, 35, !dbg !74
   %idxprom7 = sext i32 %add6 to i64, !dbg !74
-  %arrayidx8 = getelementptr inbounds i32* %Array1Par, i64 %idxprom7, !dbg !74
+  %arrayidx8 = getelementptr inbounds i32, i32* %Array1Par, i64 %idxprom7, !dbg !74
   store i32 %add, i32* %arrayidx8, align 4, !dbg !74
-  tail call void @llvm.dbg.value(metadata i32 %add, i64 0, metadata !28, metadata !{!"0x102"}), !dbg !75
+  tail call void @llvm.dbg.value(metadata i32 %add, i64 0, metadata !28, metadata !DIExpression()), !dbg !75
   br label %for.body, !dbg !75
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %idxprom, %entry ], [ %indvars.iv.next, %for.body ]
   %IntIndex.046 = phi i32 [ %add, %entry ], [ %inc, %for.body ]
-  %arrayidx13 = getelementptr inbounds [51 x i32]* %Array2Par, i64 %idxprom, i64 %indvars.iv, !dbg !77
+  %arrayidx13 = getelementptr inbounds [51 x i32], [51 x i32]* %Array2Par, i64 %idxprom, i64 %indvars.iv, !dbg !77
   store i32 %add, i32* %arrayidx13, align 4, !dbg !77
   %inc = add nsw i32 %IntIndex.046, 1, !dbg !75
-  tail call void @llvm.dbg.value(metadata i32 %inc, i64 0, metadata !28, metadata !{!"0x102"}), !dbg !75
+  tail call void @llvm.dbg.value(metadata i32 %inc, i64 0, metadata !28, metadata !DIExpression()), !dbg !75
   %cmp = icmp sgt i32 %inc, %add3, !dbg !75
   %indvars.iv.next = add i64 %indvars.iv, 1, !dbg !75
   br i1 %cmp, label %for.end, label %for.body, !dbg !75
@@ -82,14 +82,14 @@ for.body:                                         ; preds = %entry, %for.body
 for.end:                                          ; preds = %for.body
   %sub = add nsw i32 %IntParI1, 4, !dbg !78
   %idxprom14 = sext i32 %sub to i64, !dbg !78
-  %arrayidx17 = getelementptr inbounds [51 x i32]* %Array2Par, i64 %idxprom, i64 %idxprom14, !dbg !78
-  %0 = load i32* %arrayidx17, align 4, !dbg !78
+  %arrayidx17 = getelementptr inbounds [51 x i32], [51 x i32]* %Array2Par, i64 %idxprom, i64 %idxprom14, !dbg !78
+  %0 = load i32, i32* %arrayidx17, align 4, !dbg !78
   %inc18 = add nsw i32 %0, 1, !dbg !78
   store i32 %inc18, i32* %arrayidx17, align 4, !dbg !78
-  %1 = load i32* %arrayidx, align 4, !dbg !79
+  %1 = load i32, i32* %arrayidx, align 4, !dbg !79
   %add22 = add nsw i32 %IntParI1, 25, !dbg !79
   %idxprom23 = sext i32 %add22 to i64, !dbg !79
-  %arrayidx25 = getelementptr inbounds [51 x i32]* %Array2Par, i64 %idxprom23, i64 %idxprom, !dbg !79
+  %arrayidx25 = getelementptr inbounds [51 x i32], [51 x i32]* %Array2Par, i64 %idxprom23, i64 %idxprom, !dbg !79
   store i32 %1, i32* %arrayidx25, align 4, !dbg !79
   store i32 5, i32* @IntGlob, align 4, !dbg !80
   ret void, !dbg !81
@@ -103,84 +103,84 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!83}
 
-!0 = !{!"0x11\0012\00clang version 3.3 (trunk 175015)\001\00\000\00\001", !82, !1, !10, !11, !29,  !10} ; [ DW_TAG_compile_unit ] [/Users/manmanren/test-Nov/rdar_13183203/test2/dry.c] [DW_LANG_C99]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.3 (trunk 175015)", isOptimized: true, emissionKind: 1, file: !82, enums: !1, retainedTypes: !10, subprograms: !11, globals: !29, imports:  !10)
 !1 = !{!2}
-!2 = !{!"0x4\00\00128\0032\0032\000\000\000", !82, null, null, !4, null, null, null} ; [ DW_TAG_enumeration_type ] [line 128, size 32, align 32, offset 0] [def] [from ]
-!3 = !{!"0x29", !82} ; [ DW_TAG_file_type ]
+!2 = !DICompositeType(tag: DW_TAG_enumeration_type, line: 128, size: 32, align: 32, file: !82, elements: !4)
+!3 = !DIFile(filename: "dry.c", directory: "/Users/manmanren/test-Nov/rdar_13183203/test2")
 !4 = !{!5, !6, !7, !8, !9}
-!5 = !{!"0x28\00Ident1\000"} ; [ DW_TAG_enumerator ] [Ident1 :: 0]
-!6 = !{!"0x28\00Ident2\0010000"} ; [ DW_TAG_enumerator ] [Ident2 :: 10000]
-!7 = !{!"0x28\00Ident3\0010001"} ; [ DW_TAG_enumerator ] [Ident3 :: 10001]
-!8 = !{!"0x28\00Ident4\0010002"} ; [ DW_TAG_enumerator ] [Ident4 :: 10002]
-!9 = !{!"0x28\00Ident5\0010003"} ; [ DW_TAG_enumerator ] [Ident5 :: 10003]
+!5 = !DIEnumerator(name: "Ident1", value: 0) ; [ DW_TAG_enumerator ] [Ident1 :: 0]
+!6 = !DIEnumerator(name: "Ident2", value: 10000) ; [ DW_TAG_enumerator ] [Ident2 :: 10000]
+!7 = !DIEnumerator(name: "Ident3", value: 10001) ; [ DW_TAG_enumerator ] [Ident3 :: 10001]
+!8 = !DIEnumerator(name: "Ident4", value: 10002) ; [ DW_TAG_enumerator ] [Ident4 :: 10002]
+!9 = !DIEnumerator(name: "Ident5", value: 10003) ; [ DW_TAG_enumerator ] [Ident5 :: 10003]
 !10 = !{}
 !11 = !{!12}
-!12 = !{!"0x2e\00Proc8\00Proc8\00\00180\000\001\000\006\000\001\00185", !82, !3, !13, null, void (i32*, [51 x i32]*, i32, i32)* @Proc8, null, null, !22} ; [ DW_TAG_subprogram ] [line 180] [def] [scope 185] [Proc8]
-!13 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !14, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = !DISubprogram(name: "Proc8", line: 180, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 185, file: !82, scope: !3, type: !13, function: void (i32*, [51 x i32]*, i32, i32)* @Proc8, variables: !22)
+!13 = !DISubroutineType(types: !14)
 !14 = !{null, !15, !17, !21, !21}
-!15 = !{!"0xf\00\000\0064\0064\000\000", null, null, !16} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
-!16 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!17 = !{!"0xf\00\000\0064\0064\000\000", null, null, !18} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!18 = !{!"0x1\00\000\001632\0032\000\000", null, null, !16, !19, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 1632, align 32, offset 0] [from int]
+!15 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !16)
+!16 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !18)
+!18 = !DICompositeType(tag: DW_TAG_array_type, size: 1632, align: 32, baseType: !16, elements: !19)
 !19 = !{!20}
-!20 = !{!"0x21\000\0051"}       ; [ DW_TAG_subrange_type ] [0, 50]
-!21 = !{!"0x16\00OneToFifty\00132\000\000\000\000", !82, null, !16} ; [ DW_TAG_typedef ] [OneToFifty] [line 132, size 0, align 0, offset 0] [from int]
+!20 = !DISubrange(count: 51)
+!21 = !DIDerivedType(tag: DW_TAG_typedef, name: "OneToFifty", line: 132, file: !82, baseType: !16)
 !22 = !{!23, !24, !25, !26, !27, !28}
-!23 = !{!"0x101\00Array1Par\0016777397\000", !12, !3, !15} ; [ DW_TAG_arg_variable ] [Array1Par] [line 181]
-!24 = !{!"0x101\00Array2Par\0033554614\000", !12, !3, !17} ; [ DW_TAG_arg_variable ] [Array2Par] [line 182]
-!25 = !{!"0x101\00IntParI1\0050331831\000", !12, !3, !21} ; [ DW_TAG_arg_variable ] [IntParI1] [line 183]
-!26 = !{!"0x101\00IntParI2\0067109048\000", !12, !3, !21} ; [ DW_TAG_arg_variable ] [IntParI2] [line 184]
-!27 = !{!"0x100\00IntLoc\00186\000", !12, !3, !21} ; [ DW_TAG_auto_variable ] [IntLoc] [line 186]
-!28 = !{!"0x100\00IntIndex\00187\000", !12, !3, !21} ; [ DW_TAG_auto_variable ] [IntIndex] [line 187]
+!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "Array1Par", line: 181, arg: 1, scope: !12, file: !3, type: !15)
+!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "Array2Par", line: 182, arg: 2, scope: !12, file: !3, type: !17)
+!25 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "IntParI1", line: 183, arg: 3, scope: !12, file: !3, type: !21)
+!26 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "IntParI2", line: 184, arg: 4, scope: !12, file: !3, type: !21)
+!27 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "IntLoc", line: 186, scope: !12, file: !3, type: !21)
+!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "IntIndex", line: 187, scope: !12, file: !3, type: !21)
 !29 = !{!30, !35, !36, !38, !39, !40, !42, !46, !63}
-!30 = !{!"0x34\00Version\00Version\00\00111\000\001", null, !3, !31, [4 x i8]* @Version, null} ; [ DW_TAG_variable ] [Version] [line 111] [def]
-!31 = !{!"0x1\00\000\0032\008\000\000", null, null, !32, !33, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 32, align 8, offset 0] [from char]
-!32 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
+!30 = !DIGlobalVariable(name: "Version", line: 111, isLocal: false, isDefinition: true, scope: null, file: !3, type: !31, variable: [4 x i8]* @Version)
+!31 = !DICompositeType(tag: DW_TAG_array_type, size: 32, align: 8, baseType: !32, elements: !33)
+!32 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
 !33 = !{!34}
-!34 = !{!"0x21\000\004"}        ; [ DW_TAG_subrange_type ] [0, 3]
-!35 = !{!"0x34\00IntGlob\00IntGlob\00\00171\000\001", null, !3, !16, i32* @IntGlob, null} ; [ DW_TAG_variable ] [IntGlob] [line 171] [def]
-!36 = !{!"0x34\00BoolGlob\00BoolGlob\00\00172\000\001", null, !3, !37, i32* @BoolGlob, null} ; [ DW_TAG_variable ] [BoolGlob] [line 172] [def]
-!37 = !{!"0x16\00boolean\00149\000\000\000\000", !82, null, !16} ; [ DW_TAG_typedef ] [boolean] [line 149, size 0, align 0, offset 0] [from int]
-!38 = !{!"0x34\00Char1Glob\00Char1Glob\00\00173\000\001", null, !3, !32, i8* @Char1Glob, null} ; [ DW_TAG_variable ] [Char1Glob] [line 173] [def]
-!39 = !{!"0x34\00Char2Glob\00Char2Glob\00\00174\000\001", null, !3, !32, i8* @Char2Glob, null} ; [ DW_TAG_variable ] [Char2Glob] [line 174] [def]
-!40 = !{!"0x34\00Array1Glob\00Array1Glob\00\00175\000\001", null, !3, !41, [51 x i32]* @Array1Glob, null} ; [ DW_TAG_variable ] [Array1Glob] [line 175] [def]
-!41 = !{!"0x16\00Array1Dim\00135\000\000\000\000", !82, null, !18} ; [ DW_TAG_typedef ] [Array1Dim] [line 135, size 0, align 0, offset 0] [from ]
-!42 = !{!"0x34\00Array2Glob\00Array2Glob\00\00176\000\001", null, !3, !43, [51 x [51 x i32]]* @Array2Glob, null} ; [ DW_TAG_variable ] [Array2Glob] [line 176] [def]
-!43 = !{!"0x16\00Array2Dim\00136\000\000\000\000", !82, null, !44} ; [ DW_TAG_typedef ] [Array2Dim] [line 136, size 0, align 0, offset 0] [from ]
-!44 = !{!"0x1\00\000\0083232\0032\000\000", null, null, !16, !45, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 83232, align 32, offset 0] [from int]
+!34 = !DISubrange(count: 4)
+!35 = !DIGlobalVariable(name: "IntGlob", line: 171, isLocal: false, isDefinition: true, scope: null, file: !3, type: !16, variable: i32* @IntGlob)
+!36 = !DIGlobalVariable(name: "BoolGlob", line: 172, isLocal: false, isDefinition: true, scope: null, file: !3, type: !37, variable: i32* @BoolGlob)
+!37 = !DIDerivedType(tag: DW_TAG_typedef, name: "boolean", line: 149, file: !82, baseType: !16)
+!38 = !DIGlobalVariable(name: "Char1Glob", line: 173, isLocal: false, isDefinition: true, scope: null, file: !3, type: !32, variable: i8* @Char1Glob)
+!39 = !DIGlobalVariable(name: "Char2Glob", line: 174, isLocal: false, isDefinition: true, scope: null, file: !3, type: !32, variable: i8* @Char2Glob)
+!40 = !DIGlobalVariable(name: "Array1Glob", line: 175, isLocal: false, isDefinition: true, scope: null, file: !3, type: !41, variable: [51 x i32]* @Array1Glob)
+!41 = !DIDerivedType(tag: DW_TAG_typedef, name: "Array1Dim", line: 135, file: !82, baseType: !18)
+!42 = !DIGlobalVariable(name: "Array2Glob", line: 176, isLocal: false, isDefinition: true, scope: null, file: !3, type: !43, variable: [51 x [51 x i32]]* @Array2Glob)
+!43 = !DIDerivedType(tag: DW_TAG_typedef, name: "Array2Dim", line: 136, file: !82, baseType: !44)
+!44 = !DICompositeType(tag: DW_TAG_array_type, size: 83232, align: 32, baseType: !16, elements: !45)
 !45 = !{!20, !20}
-!46 = !{!"0x34\00PtrGlb\00PtrGlb\00\00177\000\001", null, !3, !47, %struct.Record** @PtrGlb, null} ; [ DW_TAG_variable ] [PtrGlb] [line 177] [def]
-!47 = !{!"0x16\00RecordPtr\00148\000\000\000\000", !82, null, !48} ; [ DW_TAG_typedef ] [RecordPtr] [line 148, size 0, align 0, offset 0] [from ]
-!48 = !{!"0xf\00\000\0064\0064\000\000", null, null, !49} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from RecordType]
-!49 = !{!"0x16\00RecordType\00147\000\000\000\000", !82, null, !50} ; [ DW_TAG_typedef ] [RecordType] [line 147, size 0, align 0, offset 0] [from Record]
-!50 = !{!"0x13\00Record\00138\00448\0064\000\000\000", !82, null, null, !51, null, i32 0, null} ; [ DW_TAG_structure_type ] [Record] [line 138, size 448, align 64, offset 0] [def] [from ]
+!46 = !DIGlobalVariable(name: "PtrGlb", line: 177, isLocal: false, isDefinition: true, scope: null, file: !3, type: !47, variable: %struct.Record** @PtrGlb)
+!47 = !DIDerivedType(tag: DW_TAG_typedef, name: "RecordPtr", line: 148, file: !82, baseType: !48)
+!48 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !49)
+!49 = !DIDerivedType(tag: DW_TAG_typedef, name: "RecordType", line: 147, file: !82, baseType: !50)
+!50 = !DICompositeType(tag: DW_TAG_structure_type, name: "Record", line: 138, size: 448, align: 64, file: !82, elements: !51)
 !51 = !{!52, !54, !56, !57, !58}
-!52 = !{!"0xd\00PtrComp\00140\0064\0064\000\000", !82, !50, !53} ; [ DW_TAG_member ] [PtrComp] [line 140, size 64, align 64, offset 0] [from ]
-!53 = !{!"0xf\00\000\0064\0064\000\000", null, null, !50} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from Record]
-!54 = !{!"0xd\00Discr\00141\0032\0032\0064\000", !82, !50, !55} ; [ DW_TAG_member ] [Discr] [line 141, size 32, align 32, offset 64] [from Enumeration]
-!55 = !{!"0x16\00Enumeration\00128\000\000\000\000", !82, null, !2} ; [ DW_TAG_typedef ] [Enumeration] [line 128, size 0, align 0, offset 0] [from ]
-!56 = !{!"0xd\00EnumComp\00142\0032\0032\0096\000", !82, !50, !55} ; [ DW_TAG_member ] [EnumComp] [line 142, size 32, align 32, offset 96] [from Enumeration]
-!57 = !{!"0xd\00IntComp\00143\0032\0032\00128\000", !82, !50, !21} ; [ DW_TAG_member ] [IntComp] [line 143, size 32, align 32, offset 128] [from OneToFifty]
-!58 = !{!"0xd\00StringComp\00144\00248\008\00160\000", !82, !50, !59} ; [ DW_TAG_member ] [StringComp] [line 144, size 248, align 8, offset 160] [from String30]
-!59 = !{!"0x16\00String30\00134\000\000\000\000", !82, null, !60} ; [ DW_TAG_typedef ] [String30] [line 134, size 0, align 0, offset 0] [from ]
-!60 = !{!"0x1\00\000\00248\008\000\000", null, null, !32, !61, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 248, align 8, offset 0] [from char]
+!52 = !DIDerivedType(tag: DW_TAG_member, name: "PtrComp", line: 140, size: 64, align: 64, file: !82, scope: !50, baseType: !53)
+!53 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !50)
+!54 = !DIDerivedType(tag: DW_TAG_member, name: "Discr", line: 141, size: 32, align: 32, offset: 64, file: !82, scope: !50, baseType: !55)
+!55 = !DIDerivedType(tag: DW_TAG_typedef, name: "Enumeration", line: 128, file: !82, baseType: !2)
+!56 = !DIDerivedType(tag: DW_TAG_member, name: "EnumComp", line: 142, size: 32, align: 32, offset: 96, file: !82, scope: !50, baseType: !55)
+!57 = !DIDerivedType(tag: DW_TAG_member, name: "IntComp", line: 143, size: 32, align: 32, offset: 128, file: !82, scope: !50, baseType: !21)
+!58 = !DIDerivedType(tag: DW_TAG_member, name: "StringComp", line: 144, size: 248, align: 8, offset: 160, file: !82, scope: !50, baseType: !59)
+!59 = !DIDerivedType(tag: DW_TAG_typedef, name: "String30", line: 134, file: !82, baseType: !60)
+!60 = !DICompositeType(tag: DW_TAG_array_type, size: 248, align: 8, baseType: !32, elements: !61)
 !61 = !{!62}
-!62 = !{!"0x21\000\0031"}       ; [ DW_TAG_subrange_type ] [0, 30]
-!63 = !{!"0x34\00PtrGlbNext\00PtrGlbNext\00\00178\000\001", null, !3, !47, %struct.Record** @PtrGlbNext, null} ; [ DW_TAG_variable ] [PtrGlbNext] [line 178] [def]
-!64 = !MDLocation(line: 181, scope: !12)
-!65 = !MDLocation(line: 182, scope: !12)
-!66 = !MDLocation(line: 183, scope: !12)
-!67 = !MDLocation(line: 184, scope: !12)
-!68 = !MDLocation(line: 189, scope: !12)
-!69 = !MDLocation(line: 190, scope: !12)
-!73 = !MDLocation(line: 191, scope: !12)
-!74 = !MDLocation(line: 192, scope: !12)
-!75 = !MDLocation(line: 193, scope: !76)
-!76 = !{!"0xb\00193\000\000", !82, !12} ; [ DW_TAG_lexical_block ] [/Users/manmanren/test-Nov/rdar_13183203/test2/dry.c]
-!77 = !MDLocation(line: 194, scope: !76)
-!78 = !MDLocation(line: 195, scope: !12)
-!79 = !MDLocation(line: 196, scope: !12)
-!80 = !MDLocation(line: 197, scope: !12)
-!81 = !MDLocation(line: 198, scope: !12)
-!82 = !{!"dry.c", !"/Users/manmanren/test-Nov/rdar_13183203/test2"}
-!83 = !{i32 1, !"Debug Info Version", i32 2}
+!62 = !DISubrange(count: 31)
+!63 = !DIGlobalVariable(name: "PtrGlbNext", line: 178, isLocal: false, isDefinition: true, scope: null, file: !3, type: !47, variable: %struct.Record** @PtrGlbNext)
+!64 = !DILocation(line: 181, scope: !12)
+!65 = !DILocation(line: 182, scope: !12)
+!66 = !DILocation(line: 183, scope: !12)
+!67 = !DILocation(line: 184, scope: !12)
+!68 = !DILocation(line: 189, scope: !12)
+!69 = !DILocation(line: 190, scope: !12)
+!73 = !DILocation(line: 191, scope: !12)
+!74 = !DILocation(line: 192, scope: !12)
+!75 = !DILocation(line: 193, scope: !76)
+!76 = distinct !DILexicalBlock(line: 193, column: 0, file: !82, scope: !12)
+!77 = !DILocation(line: 194, scope: !76)
+!78 = !DILocation(line: 195, scope: !12)
+!79 = !DILocation(line: 196, scope: !12)
+!80 = !DILocation(line: 197, scope: !12)
+!81 = !DILocation(line: 198, scope: !12)
+!82 = !DIFile(filename: "dry.c", directory: "/Users/manmanren/test-Nov/rdar_13183203/test2")
+!83 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/missing-file-line.ll b/test/DebugInfo/X86/missing-file-line.ll
new file mode 100644
index 000000000000..455868cb1736
--- /dev/null
+++ b/test/DebugInfo/X86/missing-file-line.ll
@@ -0,0 +1,57 @@
+; REQUIRES: object-emission
+
+; RUN: llc -mtriple=x86_64-linux-gnu -filetype=obj %s -o - | llvm-dwarfdump -debug-dump=all - | FileCheck %s
+
+; Test that we accept and generate DWARF entities for DW_TAG_structure_type,
+; DW_TAG_member and DW_TAG_typedef with no source location. These can come up
+; in some languages with predefined types.
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.S = type { %struct.S* }
+
+define void @f() {
+  %x = alloca %struct.S, align 8
+  ; CHECK: DW_TAG_typedef
+  ; CHECK-NOT: DW_AT_decl_file
+  ; CHECK-NOT: DW_AT_decl_line
+
+  ; CHECK: DW_TAG_structure_type
+  ; CHECK-NOT: DW_AT_decl_file
+  ; CHECK-NOT: DW_AT_decl_line
+
+  ; CHECK: DW_TAG_member
+  ; CHECK-NOT: DW_AT_decl_file
+  ; CHECK-NOT: DW_AT_decl_line
+
+  ; CHECK: {{DW_TAG|NULL}}
+  call void @llvm.dbg.declare(metadata %struct.S* %x, metadata !10, metadata !16), !dbg !17
+  ret void, !dbg !18
+}
+
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7, !8}
+!llvm.ident = !{!9}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "file.c", directory: "/dir")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "f", scope: !1, file: !1, line: 7, type: !5, isLocal: false, isDefinition: true, scopeLine: 7, isOptimized: false, function: void ()* @f, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{null}
+!7 = !{i32 2, !"Dwarf Version", i32 4}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
+!9 = !{!"clang"}
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", scope: !4, file: !1, line: 8, type: !11)
+!11 = !DIDerivedType(tag: DW_TAG_typedef, name: "SS", baseType: !12)
+!12 = !DICompositeType(tag: DW_TAG_structure_type, name: "S", size: 64, align: 64, elements: !13)
+!13 = !{!14}
+!14 = !DIDerivedType(tag: DW_TAG_member, name: "s", scope: !12, baseType: !15, size: 64, align: 64)
+!15 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 64, align: 64)
+!16 = !DIExpression()
+!17 = !DILocation(line: 8, column: 6, scope: !4)
+!18 = !DILocation(line: 9, column: 1, scope: !4)
diff --git a/test/DebugInfo/X86/multiple-aranges.ll b/test/DebugInfo/X86/multiple-aranges.ll
index 88b8bc97ecfa..571454bd8d02 100644
--- a/test/DebugInfo/X86/multiple-aranges.ll
+++ b/test/DebugInfo/X86/multiple-aranges.ll
@@ -1,9 +1,11 @@
 ; RUN: llc -generate-arange-section < %s | FileCheck %s
 
+; CHECK: .section .debug_aranges,"",@progbits
+
 ; First CU
-; CHECK:      .long   44                      # Length of ARange Set
+; CHECK-NEXT: .long   44                      # Length of ARange Set
 ; CHECK-NEXT: .short  2                       # DWARF Arange version number
-; CHECK-NEXT: .long   .L.debug_info_begin0    # Offset Into Debug Info Section
+; CHECK-NEXT: .long   .Lcu_begin0             # Offset Into Debug Info Section
 ; CHECK-NEXT: .byte   8                       # Address Size (in bytes)
 ; CHECK-NEXT: .byte   0                       # Segment Size (in bytes)
 ; CHECK-NEXT: .zero   4,255
@@ -15,12 +17,12 @@
 ; Second CU
 ; CHECK-NEXT: .long   44                      # Length of ARange Set
 ; CHECK-NEXT: .short  2                       # DWARF Arange version number
-; CHECK-NEXT: .long   .L.debug_info_begin1    # Offset Into Debug Info Section
+; CHECK-NEXT: .long   .Lcu_begin1             # Offset Into Debug Info Section
 ; CHECK-NEXT: .byte   8                       # Address Size (in bytes)
 ; CHECK-NEXT: .byte   0                       # Segment Size (in bytes)
 ; CHECK-NEXT: .zero   4,255
 ; CHECK-NEXT: .quad   rainbows
-; CHECK-NEXT: .quad   .Ldebug_end0-rainbows
+; CHECK-NEXT: .quad   .Lsec_end0-rainbows
 ; CHECK-NEXT: .quad   0                       # ARange terminator
 ; CHECK-NEXT: .quad   0
 
@@ -42,17 +44,17 @@ target triple = "x86_64-unknown-linux-gnu"
 !llvm.dbg.cu = !{!0, !7}
 !llvm.module.flags = !{!12, !13}
 
-!0 = !{!"0x11\0012\00clang version 3.4 \000\00\000\00\000", !1, !2, !2, !2, !3, !2} ; [ DW_TAG_compile_unit ] [/home/kayamon/test1.c] [DW_LANG_C99]
-!1 = !{!"test1.c", !"/home/kayamon"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3, imports: !2)
+!1 = !DIFile(filename: "test1.c", directory: "/home/kayamon")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x34\00kittens\00kittens\00\001\000\001", null, !5, !6, i32* @kittens, null} ; [ DW_TAG_variable ] [kittens] [line 1] [def]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/home/kayamon/test1.c]
-!6 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!7 = !{!"0x11\0012\00clang version 3.4 \000\00\000\00\000", !8, !2, !2, !2, !9, !2} ; [ DW_TAG_compile_unit ] [/home/kayamon/test2.c] [DW_LANG_C99]
-!8 = !{!"test2.c", !"/home/kayamon"}
+!4 = !DIGlobalVariable(name: "kittens", line: 1, isLocal: false, isDefinition: true, scope: null, file: !5, type: !6, variable: i32* @kittens)
+!5 = !DIFile(filename: "test1.c", directory: "/home/kayamon")
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!7 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 ", isOptimized: false, emissionKind: 0, file: !8, enums: !2, retainedTypes: !2, subprograms: !2, globals: !9, imports: !2)
+!8 = !DIFile(filename: "test2.c", directory: "/home/kayamon")
 !9 = !{!10}
-!10 = !{!"0x34\00rainbows\00rainbows\00\001\000\001", null, !11, !6, i32* @rainbows, null} ; [ DW_TAG_variable ] [rainbows] [line 1] [def]
-!11 = !{!"0x29", !8}         ; [ DW_TAG_file_type ] [/home/kayamon/test2.c]
+!10 = !DIGlobalVariable(name: "rainbows", line: 1, isLocal: false, isDefinition: true, scope: null, file: !11, type: !6, variable: i32* @rainbows)
+!11 = !DIFile(filename: "test2.c", directory: "/home/kayamon")
 !12 = !{i32 2, !"Dwarf Version", i32 4}
-!13 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/multiple-at-const-val.ll b/test/DebugInfo/X86/multiple-at-const-val.ll
index 17dc2c49619b..01e3af20d2d4 100644
--- a/test/DebugInfo/X86/multiple-at-const-val.ll
+++ b/test/DebugInfo/X86/multiple-at-const-val.ll
@@ -21,7 +21,7 @@
 
 define i32 @main() {
 entry:
-  %call1.i = tail call %"class.std::basic_ostream"* @test(%"class.std::basic_ostream"* @_ZSt4cout, i8* getelementptr inbounds ([6 x i8]* @.str, i64 0, i64 0), i64 5)
+  %call1.i = tail call %"class.std::basic_ostream"* @test(%"class.std::basic_ostream"* @_ZSt4cout, i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0), i64 5)
   ret i32 0
 }
 
@@ -32,32 +32,32 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!1803}
 
-!0 = !{!"0x11\004\00clang version 3.3 (trunk 174207)\001\00\000\00\000", !1802, !1, !955, !956, !1786,  !955} ; [ DW_TAG_compile_unit ] [/privite/tmp/student2.cpp] [DW_LANG_C_plus_plus]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 (trunk 174207)", isOptimized: true, emissionKind: 0, file: !1802, enums: !1, retainedTypes: !955, subprograms: !956, globals: !1786, imports:  !955)
 !1 = !{!26}
-!4 = !{!"0x39\00std\0048", null, !5} ; [ DW_TAG_namespace ]
-!5 = !{!"0x29", !1801} ; [ DW_TAG_file_type ]
-!25 = !{!"0x28\00_S_os_fmtflags_end\0065536"} ; [ DW_TAG_enumerator ]
-!26 = !{!"0x4\00_Ios_Iostate\00146\0032\0032\000\000\000", !1801, !4, null, !27, null, null, null} ; [ DW_TAG_enumeration_type ] [_Ios_Iostate] [line 146, size 32, align 32, offset 0] [def] [from ]
+!4 = !DINamespace(name: "std", line: 48, scope: !5)
+!5 = !DIFile(filename: "os_base.h", directory: "/privite/tmp")
+!25 = !DIEnumerator(name: "_S_os_fmtflags_end", value: 65536) ; [ DW_TAG_enumerator ]
+!26 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "_Ios_Iostate", line: 146, size: 32, align: 32, file: !1801, scope: !4, elements: !27)
 !27 = !{!28, !29, !30, !31, !32}
-!28 = !{!"0x28\00_S_goodbit\000"} ; [ DW_TAG_enumerator ] [_S_goodbit :: 0]
-!29 = !{!"0x28\00_S_badbit\001"} ; [ DW_TAG_enumerator ] [_S_badbit :: 1]
-!30 = !{!"0x28\00_S_eofbit\002"} ; [ DW_TAG_enumerator ] [_S_eofbit :: 2]
-!31 = !{!"0x28\00_S_failbit\004"} ; [ DW_TAG_enumerator ] [_S_failbit :: 4]
-!32 = !{!"0x28\00_S_os_ostate_end\0065536"} ; [ DW_TAG_enumerator ] [_S_os_ostate_end :: 65536]
-!49 = !{!"0x2\00os_base\00200\001728\0064\000\000\000", !1801, !4, null, !50, !49, null, null} ; [ DW_TAG_class_type ] [os_base] [line 200, size 1728, align 64, offset 0] [def] [from ]
+!28 = !DIEnumerator(name: "_S_goodbit", value: 0) ; [ DW_TAG_enumerator ] [_S_goodbit :: 0]
+!29 = !DIEnumerator(name: "_S_badbit", value: 1) ; [ DW_TAG_enumerator ] [_S_badbit :: 1]
+!30 = !DIEnumerator(name: "_S_eofbit", value: 2) ; [ DW_TAG_enumerator ] [_S_eofbit :: 2]
+!31 = !DIEnumerator(name: "_S_failbit", value: 4) ; [ DW_TAG_enumerator ] [_S_failbit :: 4]
+!32 = !DIEnumerator(name: "_S_os_ostate_end", value: 65536) ; [ DW_TAG_enumerator ] [_S_os_ostate_end :: 65536]
+!49 = !DICompositeType(tag: DW_TAG_class_type, name: "os_base", line: 200, size: 1728, align: 64, file: !1801, scope: !4, elements: !50, vtableHolder: !49)
 !50 = !{!77}
-!54 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !55, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!54 = !DISubroutineType(types: !55)
 !55 = !{!56}
-!56 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!77 = !{!"0xd\00badbit\00331\000\000\000\004096", !1801, !49, !78, i32 1} ; [ DW_TAG_member ]
-!78 = !{!"0x26\00\000\000\000\000\000", null, null, !79} ; [ DW_TAG_const_type ]
-!79 = !{!"0x16\00ostate\00327\000\000\000\000", !1801, !49, !26} ; [ DW_TAG_typedef ]
+!56 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!77 = !DIDerivedType(tag: DW_TAG_member, name: "badbit", line: 331, flags: DIFlagStaticMember, file: !1801, scope: !49, baseType: !78, extraData: i32 1)
+!78 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !79)
+!79 = !DIDerivedType(tag: DW_TAG_typedef, name: "ostate", line: 327, file: !1801, scope: !49, baseType: !26)
 !955 = !{}
 !956 = !{!960}
-!960 = !{!"0x2e\00main\00main\00\0073\000\001\000\006\00256\001\0073", !1802, null, !54, null, i32 ()* @main, null, null, !955} ; [ DW_TAG_subprogram ]
-!961 = !{!"0x29", !1802} ; [ DW_TAG_file_type ]
+!960 = !DISubprogram(name: "main", line: 73, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 73, file: !1802, scope: null, type: !54, function: i32 ()* @main, variables: !955)
+!961 = !DIFile(filename: "student2.cpp", directory: "/privite/tmp")
 !1786 = !{!1800}
-!1800 = !{!"0x34\00badbit\00badbit\00badbit\00331\001\001", !5, !5, !78, i32 1, !77} ; [ DW_TAG_variable ]
-!1801 = !{!"os_base.h", !"/privite/tmp"}
-!1802 = !{!"student2.cpp", !"/privite/tmp"}
-!1803 = !{i32 1, !"Debug Info Version", i32 2}
+!1800 = !DIGlobalVariable(name: "badbit", linkageName: "badbit", line: 331, isLocal: true, isDefinition: true, scope: !5, file: !5, type: !78, variable: i32 1, declaration: !77)
+!1801 = !DIFile(filename: "os_base.h", directory: "/privite/tmp")
+!1802 = !DIFile(filename: "student2.cpp", directory: "/privite/tmp")
+!1803 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/nodebug_with_debug_loc.ll b/test/DebugInfo/X86/nodebug_with_debug_loc.ll
index cc9a87472808..8153b3352d4e 100644
--- a/test/DebugInfo/X86/nodebug_with_debug_loc.ll
+++ b/test/DebugInfo/X86/nodebug_with_debug_loc.ll
@@ -51,22 +51,22 @@ define void @_Z2f1v() #0 {
 entry:
   %str2.i = alloca %struct.string, align 4
   %0 = bitcast %struct.string* %str2.i to i8*, !dbg !26
-  %1 = load %struct.string** @str, align 4
-  %mem = getelementptr inbounds %struct.string* %1, i32 0, i32 0
+  %1 = load %struct.string*, %struct.string** @str, align 4
+  %mem = getelementptr inbounds %struct.string, %struct.string* %1, i32 0, i32 0
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
   %iter.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   call void @llvm.lifetime.start(i64 4, i8* %0), !dbg !26
-  call void @llvm.dbg.value(metadata %struct.string* %str2.i, i64 0, metadata !16, metadata !{!"0x102"}) #3, !dbg !26
-  call void @llvm.dbg.value(metadata %struct.string* %str2.i, i64 0, metadata !27, metadata !{!"0x102"}) #3, !dbg !29
+  call void @llvm.dbg.value(metadata %struct.string* %str2.i, i64 0, metadata !16, metadata !DIExpression()) #3, !dbg !26
+  call void @llvm.dbg.value(metadata %struct.string* %str2.i, i64 0, metadata !27, metadata !DIExpression()) #3, !dbg !29
   call void @_Z4sinkPKv(i8* undef) #3, !dbg !29
   call void @_Z4sinkPKv(i8* %0) #3, !dbg !30
   call void @llvm.lifetime.end(i64 4, i8* %0), !dbg !31
-  %2 = load i32** %mem, align 4, !tbaa !32
+  %2 = load i32*, i32** %mem, align 4, !tbaa !32
   %3 = bitcast i32* %2 to i8*
   call void @_Z4sinkPKv(i8* %3) #3
-  %4 = load i8* @b, align 1, !tbaa !37, !range !39
+  %4 = load i8, i8* @b, align 1, !tbaa !37, !range !39
   %tobool = icmp ne i8 %4, 0
   %inc = add nsw i32 %iter.02, 1
   %cmp = icmp eq i32 %inc, 2
@@ -97,38 +97,38 @@ attributes #3 = { nounwind }
 !llvm.module.flags = !{!23, !24}
 !llvm.ident = !{!25}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \001\00\000\00\001", !1, !2, !3, !10, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/<stdin>] [DW_LANG_C_plus_plus]
-!1 = !{!"<stdin>", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !10, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<stdin>", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00string\007\0032\0032\000\000\000", !5, null, null, !6, null, null, !"_ZTS6string"} ; [ DW_TAG_structure_type ] [string] [line 7, size 32, align 32, offset 0] [def] [from ]
-!5 = !{!"repro.cpp", !"/tmp/dbginfo"}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "string", line: 7, size: 32, align: 32, file: !5, elements: !6, identifier: "_ZTS6string")
+!5 = !DIFile(filename: "repro.cpp", directory: "/tmp/dbginfo")
 !6 = !{!7}
-!7 = !{!"0xd\00mem\008\0032\0032\000\000", !5, !"_ZTS6string", !8} ; [ DW_TAG_member ] [mem] [line 8, size 32, align 32, offset 0] [from ]
-!8 = !{!"0xf\00\000\0032\0032\000\000", null, null, !9} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from unsigned int]
-!9 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, null} ; [ DW_TAG_base_type ] [unsigned int] [line 0, size 32, align 32, offset 0, enc DW_ATE_unsigned]
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "mem", line: 8, size: 32, align: 32, file: !5, scope: !"_ZTS6string", baseType: !8)
+!8 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !9)
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
 !10 = !{!11, !17}
-!11 = !{!"0x2e\00f\00f\00_Z1fv\0014\000\001\000\006\00256\001\0014", !5, !12, !13, null, null, null, null, !15} ; [ DW_TAG_subprogram ] [line 14] [def] [f]
-!12 = !{!"0x29", !5}         ; [ DW_TAG_file_type ] [/tmp/dbginfo/repro.cpp]
-!13 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !14, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!11 = !DISubprogram(name: "f", linkageName: "_Z1fv", line: 14, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 14, file: !5, scope: !12, type: !13, variables: !15)
+!12 = !DIFile(filename: "repro.cpp", directory: "/tmp/dbginfo")
+!13 = !DISubroutineType(types: !14)
 !14 = !{null}
 !15 = !{!16}
-!16 = !{!"0x100\00str2\0015\000", !11, !12, !"_ZTS6string"} ; [ DW_TAG_auto_variable ] [str2] [line 15]
-!17 = !{!"0x2e\00s2\00s2\00_Z2s2P6string\0013\000\001\000\006\00256\001\0013", !5, !12, !18, null, null, null, null, !21} ; [ DW_TAG_subprogram ] [line 13] [def] [s2]
-!18 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !19, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!16 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "str2", line: 15, scope: !11, file: !12, type: !"_ZTS6string")
+!17 = !DISubprogram(name: "s2", linkageName: "_Z2s2P6string", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 13, file: !5, scope: !12, type: !18, variables: !21)
+!18 = !DISubroutineType(types: !19)
 !19 = !{null, !20}
-!20 = !{!"0xf\00\000\0032\0032\000\000", null, null, !"_ZTS6string"} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from _ZTS6string]
+!20 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !"_ZTS6string")
 !21 = !{!22}
-!22 = !{!"0x101\00lhs\0016777229\000", !17, !12, !20} ; [ DW_TAG_arg_variable ] [lhs] [line 13]
+!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "lhs", line: 13, arg: 1, scope: !17, file: !12, type: !20)
 !23 = !{i32 2, !"Dwarf Version", i32 4}
-!24 = !{i32 2, !"Debug Info Version", i32 2}
+!24 = !{i32 2, !"Debug Info Version", i32 3}
 !25 = !{!"clang version 3.5.0 "}
-!26 = !MDLocation(line: 15, scope: !11)
-!27 = !{!"0x101\00lhs\0016777229\000", !17, !12, !20, !28} ; [ DW_TAG_arg_variable ] [lhs] [line 13]
-!28 = !MDLocation(line: 16, scope: !11)
-!29 = !MDLocation(line: 13, scope: !17, inlinedAt: !28)
-!30 = !MDLocation(line: 17, scope: !11)
-!31 = !MDLocation(line: 18, scope: !11)
+!26 = !DILocation(line: 15, scope: !11)
+!27 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "lhs", line: 13, arg: 1, scope: !17, file: !12, type: !20)
+!28 = !DILocation(line: 16, scope: !11)
+!29 = !DILocation(line: 13, scope: !17, inlinedAt: !28)
+!30 = !DILocation(line: 17, scope: !11)
+!31 = !DILocation(line: 18, scope: !11)
 !32 = !{!33, !34, i64 0}
 !33 = !{!"_ZTS6string", !34, i64 0}
 !34 = !{!"any pointer", !35, i64 0}
diff --git a/test/DebugInfo/X86/nondefault-subrange-array.ll b/test/DebugInfo/X86/nondefault-subrange-array.ll
index 3167d9f1e6ba..20406cfa0f16 100644
--- a/test/DebugInfo/X86/nondefault-subrange-array.ll
+++ b/test/DebugInfo/X86/nondefault-subrange-array.ll
@@ -30,23 +30,21 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!21}
 
-!0 = !{!"0x11\004\00clang version 3.3 (trunk 169136)\000\00\000\00\000", !20, !1, !1, !1, !3,  !1} ; [ DW_TAG_compile_unit ] [/Volumes/Sandbox/llvm/t.cpp] [DW_LANG_C_plus_plus]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 (trunk 169136)", isOptimized: false, emissionKind: 0, file: !20, enums: !1, retainedTypes: !1, subprograms: !1, globals: !3, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x34\00a\00a\00\001\000\001", null, !6, !7, %class.A* @a, null} ; [ DW_TAG_variable ] [a] [line 1] [def]
-!6 = !{!"0x29", !20} ; [ DW_TAG_file_type ]
-!7 = !{!"0x2\00A\001\000\0032\000\000\000", !20, null, null, !8, null, null, null} ; [ DW_TAG_class_type ] [A] [line 1, size 0, align 32, offset 0] [def] [from ]
+!5 = !DIGlobalVariable(name: "a", line: 1, isLocal: false, isDefinition: true, scope: null, file: !6, type: !7, variable: %class.A* @a)
+!6 = !DIFile(filename: "t.cpp", directory: "/Volumes/Sandbox/llvm")
+!7 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 1, align: 32, file: !20, elements: !8)
 !8 = !{!9, !14}
-!9 = !{!"0xd\00x\001\000\000\000\001", !20, !7, !10} ; [ DW_TAG_member ] [x] [line 1, size 0, align 0, offset 0] [private] [from ]
-!10 = !{!"0x1\00\000\000\0032\000\000", null, null, !11, !12, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 0, align 32, offset 0] [from int]
-!11 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 1, flags: DIFlagPrivate, file: !20, scope: !7, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_array_type, align: 32, baseType: !11, elements: !12)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !12 = !{!13}
-!13 = !{!"0x21\00-3\0042"} ; [ DW_TAG_subrange_type ] [-3, 39]
-!14 = !{!"0x2e\00A\00A\00\001\000\000\000\006\00320\000\001", !6, !7, !15, null, null, null, i32 0, !18} ; [ DW_TAG_subprogram ] [line 1] [A]
-!15 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DISubrange(count: 42, lowerBound: -3)
+!14 = !DISubprogram(name: "A", line: 1, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !6, scope: !7, type: !15)
+!15 = !DISubroutineType(types: !16)
 !16 = !{null, !17}
-!17 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !7} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from A]
-!18 = !{!19}
-!19 = !{!"0x24"}                      ; [ DW_TAG_base_type ] [line 0, size 0, align 0, offset 0]
-!20 = !{!"t.cpp", !"/Volumes/Sandbox/llvm"}
-!21 = !{i32 1, !"Debug Info Version", i32 2}
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !7)
+!20 = !DIFile(filename: "t.cpp", directory: "/Volumes/Sandbox/llvm")
+!21 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/nophysreg.ll b/test/DebugInfo/X86/nophysreg.ll
new file mode 100644
index 000000000000..f4478efb67f8
--- /dev/null
+++ b/test/DebugInfo/X86/nophysreg.ll
@@ -0,0 +1,203 @@
+; RUN: llc -filetype=obj < %s | llvm-dwarfdump -debug-dump=info - | FileCheck %s
+;
+; PR22296: In this testcase the DBG_VALUE describing "p5" becomes unavailable
+; because the register its address is in is clobbered and we (currently) aren't
+; smart enough to realize that the value is rematerialized immediately after the
+; DBG_VALUE and/or is actually a stack slot.
+;
+; Test that we handle this situation gracefully by omitting the DW_AT_location
+; and not asserting.
+; Note that this check may XPASS in the future if DbgValueHistoryCalculator
+; becoms smarter. That would be fine, too.
+;
+; CHECK: DW_TAG_subprogram
+; CHECK: linkage_name{{.*}}_Z2f21A
+; CHECK: DW_TAG_formal_parameter
+; CHECK-NOT: DW_AT_location
+; CHECK-NEXT: DW_AT_name {{.*}}"p5"
+;
+; // Compile at -O1
+; struct A {
+;   int *m1;
+;   int m2;
+; };
+;
+; void f1(int *p1, int p2);
+; void __attribute__((always_inline)) f2(A p5) { f1(p5.m1, p5.m2); }
+;
+; void func(void*);
+; void func(const int &, const int&);
+; int cond();
+; void f() {
+;   while (cond()) {
+;     int x;
+;     func(x, 0);
+;     while (cond()) {
+;       char y;
+;       func(&y);
+;       char j;
+;       func(&j);
+;       char I;
+;       func(&I);
+;       func(0, 0);
+;       A g;
+;       g.m1 = &x;
+;       f2(g);
+;     }
+;   }
+; }
+; ModuleID = 'test.cpp'
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+%struct.A = type { i32*, i32 }
+
+; Function Attrs: alwaysinline ssp uwtable
+define void @_Z2f21A(i32* %p5.coerce0, i32 %p5.coerce1) #0 {
+entry:
+  tail call void @llvm.dbg.value(metadata i32* %p5.coerce0, i64 0, metadata !16, metadata !33), !dbg !34
+  tail call void @llvm.dbg.value(metadata i32 %p5.coerce1, i64 0, metadata !16, metadata !35), !dbg !34
+  tail call void @llvm.dbg.declare(metadata %struct.A* undef, metadata !16, metadata !36), !dbg !34
+  tail call void @_Z2f1Pii(i32* %p5.coerce0, i32 %p5.coerce1), !dbg !37
+  ret void, !dbg !38
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+declare void @_Z2f1Pii(i32*, i32) #2
+
+; Function Attrs: ssp uwtable
+define void @_Z1fv() #3 {
+entry:
+  %x = alloca i32, align 4
+  %ref.tmp = alloca i32, align 4
+  %y = alloca i8, align 1
+  %j = alloca i8, align 1
+  %I = alloca i8, align 1
+  %ref.tmp5 = alloca i32, align 4
+  %ref.tmp6 = alloca i32, align 4
+  %call11 = call i32 @_Z4condv(), !dbg !39
+  %tobool12 = icmp eq i32 %call11, 0, !dbg !39
+  br i1 %tobool12, label %while.end7, label %while.body, !dbg !40
+
+while.cond.loopexit:                              ; preds = %while.body4, %while.body
+  %call = call i32 @_Z4condv(), !dbg !39
+  %tobool = icmp eq i32 %call, 0, !dbg !39
+  br i1 %tobool, label %while.end7, label %while.body, !dbg !40
+
+while.body:                                       ; preds = %entry, %while.cond.loopexit
+  store i32 0, i32* %ref.tmp, align 4, !dbg !41, !tbaa !42
+  call void @llvm.dbg.value(metadata i32* %x, i64 0, metadata !21, metadata !36), !dbg !46
+  call void @_Z4funcRKiS0_(i32* dereferenceable(4) %x, i32* dereferenceable(4) %ref.tmp), !dbg !47
+  %call29 = call i32 @_Z4condv(), !dbg !48
+  %tobool310 = icmp eq i32 %call29, 0, !dbg !48
+  br i1 %tobool310, label %while.cond.loopexit, label %while.body4, !dbg !49
+
+while.body4:                                      ; preds = %while.body, %while.body4
+  call void @llvm.dbg.value(metadata i8* %y, i64 0, metadata !23, metadata !36), !dbg !50
+  call void @_Z4funcPv(i8* %y), !dbg !51
+  call void @llvm.dbg.value(metadata i8* %j, i64 0, metadata !26, metadata !36), !dbg !52
+  call void @_Z4funcPv(i8* %j), !dbg !53
+  call void @llvm.dbg.value(metadata i8* %I, i64 0, metadata !27, metadata !36), !dbg !54
+  call void @_Z4funcPv(i8* %I), !dbg !55
+  store i32 0, i32* %ref.tmp5, align 4, !dbg !56, !tbaa !42
+  store i32 0, i32* %ref.tmp6, align 4, !dbg !57, !tbaa !42
+  call void @_Z4funcRKiS0_(i32* dereferenceable(4) %ref.tmp5, i32* dereferenceable(4) %ref.tmp6), !dbg !58
+  call void @llvm.dbg.declare(metadata %struct.A* undef, metadata !28, metadata !36), !dbg !59
+  call void @llvm.dbg.value(metadata i32* %x, i64 0, metadata !28, metadata !33), !dbg !59
+  call void @llvm.dbg.value(metadata i32* %x, i64 0, metadata !21, metadata !36), !dbg !46
+  call void @llvm.dbg.value(metadata i32* %x, i64 0, metadata !60, metadata !33), !dbg !62
+  call void @llvm.dbg.value(metadata i32 undef, i64 0, metadata !60, metadata !35), !dbg !62
+  call void @llvm.dbg.declare(metadata %struct.A* undef, metadata !60, metadata !36), !dbg !62
+  call void @_Z2f1Pii(i32* %x, i32 undef), !dbg !63
+  %call2 = call i32 @_Z4condv(), !dbg !48
+  %tobool3 = icmp eq i32 %call2, 0, !dbg !48
+  br i1 %tobool3, label %while.cond.loopexit, label %while.body4, !dbg !49
+
+while.end7:                                       ; preds = %while.cond.loopexit, %entry
+  ret void, !dbg !64
+}
+
+declare i32 @_Z4condv()
+
+declare void @_Z4funcRKiS0_(i32* dereferenceable(4), i32* dereferenceable(4))
+
+declare void @_Z4funcPv(i8*)
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
+
+attributes #0 = { alwaysinline ssp uwtable }
+attributes #1 = { nounwind readnone }
+attributes #3 = { ssp uwtable }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!29, !30, !31}
+!llvm.ident = !{!32}
+
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.7.0 (trunk 227088) (llvm/trunk 227091)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !10, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.cpp", directory: "")
+!2 = !{}
+!3 = !{!4}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "A", line: 1, size: 128, align: 64, file: !1, elements: !5, identifier: "_ZTS1A")
+!5 = !{!6, !9}
+!6 = !DIDerivedType(tag: DW_TAG_member, name: "m1", line: 2, size: 64, align: 64, file: !1, scope: !"_ZTS1A", baseType: !7)
+!7 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "m2", line: 3, size: 32, align: 32, offset: 64, file: !1, scope: !"_ZTS1A", baseType: !8)
+!10 = !{!11, !17}
+!11 = !DISubprogram(name: "f2", linkageName: "_Z2f21A", line: 7, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 7, file: !1, scope: !12, type: !13, function: void (i32*, i32)* @_Z2f21A, variables: !15)
+!12 = !DIFile(filename: "test.cpp", directory: "")
+!13 = !DISubroutineType(types: !14)
+!14 = !{null, !"_ZTS1A"}
+!15 = !{!16}
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p5", line: 7, arg: 1, scope: !11, file: !12, type: !"_ZTS1A")
+!17 = !DISubprogram(name: "f", linkageName: "_Z1fv", line: 12, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 12, file: !1, scope: !12, type: !18, function: void ()* @_Z1fv, variables: !20)
+!18 = !DISubroutineType(types: !19)
+!19 = !{null}
+!20 = !{!21, !23, !26, !27, !28}
+!21 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 14, scope: !22, file: !12, type: !8)
+!22 = distinct !DILexicalBlock(line: 13, column: 18, file: !1, scope: !17)
+!23 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y", line: 17, scope: !24, file: !12, type: !25)
+!24 = distinct !DILexicalBlock(line: 16, column: 20, file: !1, scope: !22)
+!25 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 19, scope: !24, file: !12, type: !25)
+!27 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "I", line: 21, scope: !24, file: !12, type: !25)
+!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "g", line: 24, scope: !24, file: !12, type: !"_ZTS1A")
+!29 = !{i32 2, !"Dwarf Version", i32 2}
+!30 = !{i32 2, !"Debug Info Version", i32 3}
+!31 = !{i32 1, !"PIC Level", i32 2}
+!32 = !{!"clang version 3.7.0 (trunk 227088) (llvm/trunk 227091)"}
+!33 = !DIExpression(DW_OP_bit_piece, 0, 8)
+!34 = !DILocation(line: 7, column: 42, scope: !11)
+!35 = !DIExpression(DW_OP_bit_piece, 8, 4)
+!36 = !DIExpression()
+!37 = !DILocation(line: 7, column: 48, scope: !11)
+!38 = !DILocation(line: 7, column: 66, scope: !11)
+!39 = !DILocation(line: 13, column: 10, scope: !17)
+!40 = !DILocation(line: 13, column: 3, scope: !17)
+!41 = !DILocation(line: 15, column: 13, scope: !22)
+!42 = !{!43, !43, i64 0}
+!43 = !{!"int", !44, i64 0}
+!44 = !{!"omnipotent char", !45, i64 0}
+!45 = !{!"Simple C/C++ TBAA"}
+!46 = !DILocation(line: 14, column: 9, scope: !22)
+!47 = !DILocation(line: 15, column: 5, scope: !22)
+!48 = !DILocation(line: 16, column: 12, scope: !22)
+!49 = !DILocation(line: 16, column: 5, scope: !22)
+!50 = !DILocation(line: 17, column: 12, scope: !24)
+!51 = !DILocation(line: 18, column: 7, scope: !24)
+!52 = !DILocation(line: 19, column: 12, scope: !24)
+!53 = !DILocation(line: 20, column: 7, scope: !24)
+!54 = !DILocation(line: 21, column: 12, scope: !24)
+!55 = !DILocation(line: 22, column: 7, scope: !24)
+!56 = !DILocation(line: 23, column: 12, scope: !24)
+!57 = !DILocation(line: 23, column: 15, scope: !24)
+!58 = !DILocation(line: 23, column: 7, scope: !24)
+!59 = !DILocation(line: 24, column: 9, scope: !24)
+!60 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p5", line: 7, arg: 1, scope: !11, file: !12, type: !"_ZTS1A")
+!61 = distinct !DILocation(line: 26, column: 7, scope: !24)
+!62 = !DILocation(line: 7, column: 42, scope: !11, inlinedAt: !61)
+!63 = !DILocation(line: 7, column: 48, scope: !11, inlinedAt: !61)
+!64 = !DILocation(line: 29, column: 1, scope: !17)
diff --git a/test/DebugInfo/X86/objc-fwd-decl.ll b/test/DebugInfo/X86/objc-fwd-decl.ll
index cd71396661c5..5b0aca5f92f5 100644
--- a/test/DebugInfo/X86/objc-fwd-decl.ll
+++ b/test/DebugInfo/X86/objc-fwd-decl.ll
@@ -12,16 +12,16 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!9, !10, !11, !12, !14}
 
-!0 = !{!"0x11\0016\00clang version 3.1 (trunk 152054 trunk 152094)\000\00\002\00\000", !13, !1, !1, !1, !3,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_ObjC, producer: "clang version 3.1 (trunk 152054 trunk 152094)", isOptimized: false, runtimeVersion: 2, emissionKind: 0, file: !13, enums: !1, retainedTypes: !1, subprograms: !1, globals: !3, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x34\00a\00a\00\003\000\001", null, !6, !7, %0** @a, null} ; [ DW_TAG_variable ]
-!6 = !{!"0x29", !13} ; [ DW_TAG_file_type ]
-!7 = !{!"0xf\00\000\0064\0064\000\000", null, null, !8} ; [ DW_TAG_pointer_type ]
-!8 = !{!"0x13\00FooBarBaz\001\000\000\000\004\0016", !13, null, null, null, null, null, null} ; [ DW_TAG_structure_type ] [FooBarBaz] [line 1, size 0, align 0, offset 0] [decl] [from ]
+!5 = !DIGlobalVariable(name: "a", line: 3, isLocal: false, isDefinition: true, scope: null, file: !6, type: !7, variable: %0** @a)
+!6 = !DIFile(filename: "foo.m", directory: "/Users/echristo")
+!7 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !8)
+!8 = !DICompositeType(tag: DW_TAG_structure_type, name: "FooBarBaz", line: 1, flags: DIFlagFwdDecl, runtimeLang: DW_LANG_ObjC, file: !13)
 !9 = !{i32 1, !"Objective-C Version", i32 2}
 !10 = !{i32 1, !"Objective-C Image Info Version", i32 0}
 !11 = !{i32 1, !"Objective-C Image Info Section", !"__DATA, __objc_imageinfo, regular, no_dead_strip"}
 !12 = !{i32 4, !"Objective-C Garbage Collection", i32 0}
-!13 = !{!"foo.m", !"/Users/echristo"}
-!14 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = !DIFile(filename: "foo.m", directory: "/Users/echristo")
+!14 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/objc-property-void.ll b/test/DebugInfo/X86/objc-property-void.ll
index 0ae9e1a337ed..0737fe2d2cb4 100644
--- a/test/DebugInfo/X86/objc-property-void.ll
+++ b/test/DebugInfo/X86/objc-property-void.ll
@@ -39,16 +39,16 @@ target triple = "x86_64-apple-macosx10.9.0"
 @"OBJC_CLASS_$_Foo" = global %struct._class_t { %struct._class_t* @"OBJC_METACLASS_$_Foo", %struct._class_t* null, %struct._objc_cache* @_objc_empty_cache, i8* (i8*, i8*)** null, %struct._class_ro_t* @"\01l_OBJC_CLASS_RO_$_Foo" }, section "__DATA, __objc_data", align 8
 @"OBJC_METACLASS_$_Foo" = global %struct._class_t { %struct._class_t* @"OBJC_METACLASS_$_Foo", %struct._class_t* @"OBJC_CLASS_$_Foo", %struct._objc_cache* @_objc_empty_cache, i8* (i8*, i8*)** null, %struct._class_ro_t* @"\01l_OBJC_METACLASS_RO_$_Foo" }, section "__DATA, __objc_data", align 8
 @"\01L_OBJC_CLASS_NAME_" = internal global [4 x i8] c"Foo\00", section "__TEXT,__objc_classname,cstring_literals", align 1
-@"\01l_OBJC_METACLASS_RO_$_Foo" = internal global %struct._class_ro_t { i32 3, i32 40, i32 40, i8* null, i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), %struct.__method_list_t* null, %struct._objc_protocol_list* null, %struct._ivar_list_t* null, i8* null, %struct._prop_list_t* null }, section "__DATA, __objc_const", align 8
+@"\01l_OBJC_METACLASS_RO_$_Foo" = internal global %struct._class_ro_t { i32 3, i32 40, i32 40, i8* null, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), %struct.__method_list_t* null, %struct._objc_protocol_list* null, %struct._ivar_list_t* null, i8* null, %struct._prop_list_t* null }, section "__DATA, __objc_const", align 8
 @"\01L_OBJC_METH_VAR_NAME_" = internal global [4 x i8] c"foo\00", section "__TEXT,__objc_methname,cstring_literals", align 1
 @"\01L_OBJC_METH_VAR_TYPE_" = internal global [8 x i8] c"v16@0:8\00", section "__TEXT,__objc_methtype,cstring_literals", align 1
-@"\01l_OBJC_$_INSTANCE_METHODS_Foo" = internal global { i32, i32, [1 x %struct._objc_method] } { i32 24, i32 1, [1 x %struct._objc_method] [%struct._objc_method { i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @"\01L_OBJC_METH_VAR_TYPE_", i32 0, i32 0), i8* bitcast (void (%0*, i8*)* @"\01-[Foo foo]" to i8*) }] }, section "__DATA, __objc_const", align 8
+@"\01l_OBJC_$_INSTANCE_METHODS_Foo" = internal global { i32, i32, [1 x %struct._objc_method] } { i32 24, i32 1, [1 x %struct._objc_method] [%struct._objc_method { i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([8 x i8], [8 x i8]* @"\01L_OBJC_METH_VAR_TYPE_", i32 0, i32 0), i8* bitcast (void (%0*, i8*)* @"\01-[Foo foo]" to i8*) }] }, section "__DATA, __objc_const", align 8
 @"\01L_OBJC_PROP_NAME_ATTR_" = internal global [4 x i8] c"foo\00", section "__TEXT,__cstring,cstring_literals", align 1
 @"\01L_OBJC_PROP_NAME_ATTR_1" = internal global [7 x i8] c"Tv,R,N\00", section "__TEXT,__cstring,cstring_literals", align 1
-@"\01l_OBJC_$_PROP_LIST_Foo" = internal global { i32, i32, [1 x %struct._prop_t] } { i32 16, i32 1, [1 x %struct._prop_t] [%struct._prop_t { i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_PROP_NAME_ATTR_", i32 0, i32 0), i8* getelementptr inbounds ([7 x i8]* @"\01L_OBJC_PROP_NAME_ATTR_1", i32 0, i32 0) }] }, section "__DATA, __objc_const", align 8
-@"\01l_OBJC_CLASS_RO_$_Foo" = internal global %struct._class_ro_t { i32 2, i32 0, i32 0, i8* null, i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), %struct.__method_list_t* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_INSTANCE_METHODS_Foo" to %struct.__method_list_t*), %struct._objc_protocol_list* null, %struct._ivar_list_t* null, i8* null, %struct._prop_list_t* bitcast ({ i32, i32, [1 x %struct._prop_t] }* @"\01l_OBJC_$_PROP_LIST_Foo" to %struct._prop_list_t*) }, section "__DATA, __objc_const", align 8
+@"\01l_OBJC_$_PROP_LIST_Foo" = internal global { i32, i32, [1 x %struct._prop_t] } { i32 16, i32 1, [1 x %struct._prop_t] [%struct._prop_t { i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01L_OBJC_PROP_NAME_ATTR_", i32 0, i32 0), i8* getelementptr inbounds ([7 x i8], [7 x i8]* @"\01L_OBJC_PROP_NAME_ATTR_1", i32 0, i32 0) }] }, section "__DATA, __objc_const", align 8
+@"\01l_OBJC_CLASS_RO_$_Foo" = internal global %struct._class_ro_t { i32 2, i32 0, i32 0, i8* null, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), %struct.__method_list_t* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_INSTANCE_METHODS_Foo" to %struct.__method_list_t*), %struct._objc_protocol_list* null, %struct._ivar_list_t* null, i8* null, %struct._prop_list_t* bitcast ({ i32, i32, [1 x %struct._prop_t] }* @"\01l_OBJC_$_PROP_LIST_Foo" to %struct._prop_list_t*) }, section "__DATA, __objc_const", align 8
 @"\01L_OBJC_LABEL_CLASS_$" = internal global [1 x i8*] [i8* bitcast (%struct._class_t* @"OBJC_CLASS_$_Foo" to i8*)], section "__DATA, __objc_classlist, regular, no_dead_strip", align 8
-@llvm.used = appending global [8 x i8*] [i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @"\01L_OBJC_METH_VAR_TYPE_", i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_INSTANCE_METHODS_Foo" to i8*), i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_PROP_NAME_ATTR_", i32 0, i32 0), i8* getelementptr inbounds ([7 x i8]* @"\01L_OBJC_PROP_NAME_ATTR_1", i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._prop_t] }* @"\01l_OBJC_$_PROP_LIST_Foo" to i8*), i8* bitcast ([1 x i8*]* @"\01L_OBJC_LABEL_CLASS_$" to i8*)], section "llvm.metadata"
+@llvm.used = appending global [8 x i8*] [i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([8 x i8], [8 x i8]* @"\01L_OBJC_METH_VAR_TYPE_", i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_INSTANCE_METHODS_Foo" to i8*), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01L_OBJC_PROP_NAME_ATTR_", i32 0, i32 0), i8* getelementptr inbounds ([7 x i8], [7 x i8]* @"\01L_OBJC_PROP_NAME_ATTR_1", i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._prop_t] }* @"\01l_OBJC_$_PROP_LIST_Foo" to i8*), i8* bitcast ([1 x i8*]* @"\01L_OBJC_LABEL_CLASS_$" to i8*)], section "llvm.metadata"
 
 ; Function Attrs: ssp uwtable
 define internal void @"\01-[Foo foo]"(%0* %self, i8* %_cmd) #0 {
@@ -56,9 +56,9 @@ entry:
   %self.addr = alloca %0*, align 8
   %_cmd.addr = alloca i8*, align 8
   store %0* %self, %0** %self.addr, align 8
-  call void @llvm.dbg.declare(metadata %0** %self.addr, metadata !24, metadata !{!"0x102"}), !dbg !26
+  call void @llvm.dbg.declare(metadata %0** %self.addr, metadata !24, metadata !DIExpression()), !dbg !26
   store i8* %_cmd, i8** %_cmd.addr, align 8
-  call void @llvm.dbg.declare(metadata i8** %_cmd.addr, metadata !27, metadata !{!"0x102"}), !dbg !26
+  call void @llvm.dbg.declare(metadata i8** %_cmd.addr, metadata !27, metadata !DIExpression()), !dbg !26
   ret void, !dbg !29
 }
 
@@ -72,33 +72,33 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!17, !18, !19, !20, !21, !22}
 !llvm.ident = !{!23}
 
-!0 = !{!"0x11\0016\00\000\00\002\00\000", !1, !2, !3, !9, !2, !2} ; [ DW_TAG_compile_unit ] [] [DW_LANG_ObjC]
-!1 = !{!"-", !""}
+!0 = !DICompileUnit(language: DW_LANG_ObjC, isOptimized: false, runtimeVersion: 2, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !9, globals: !2, imports: !2)
+!1 = !DIFile(filename: "-", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00Foo\001\000\008\000\00512\0016", !5, !6, null, !7, null, null, null} ; [ DW_TAG_structure_type ] [Foo] [line 1, size 0, align 8, offset 0] [def] [from ]
-!5 = !{!"<stdin>", !""}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] []
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "Foo", line: 1, align: 8, flags: DIFlagObjcClassComplete, runtimeLang: DW_LANG_ObjC, file: !5, scope: !6, elements: !7)
+!5 = !DIFile(filename: "<stdin>", directory: "")
+!6 = !DIFile(filename: "<stdin>", directory: "")
 !7 = !{!8}
-!8 = !{!"0x4200\00foo\002\00\00\002117", !6, null} ; [ DW_TAG_APPLE_property ] [foo] [line 2, properties 2117]
+!8 = !DIObjCProperty(name: "foo", line: 2, attributes: 2117, file: !6)
 !9 = !{!10}
-!10 = !{!"0x2e\00-[Foo foo]\00-[Foo foo]\00\005\001\001\000\006\00256\000\005", !5, !6, !11, null, void (%0*, i8*)* @"\01-[Foo foo]", null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [local] [def] [-[Foo foo]]
-!11 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!10 = !DISubprogram(name: "-[Foo foo]", line: 5, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !5, scope: !6, type: !11, function: void (%0*, i8*)* @"\01-[Foo foo]", variables: !2)
+!11 = !DISubroutineType(types: !12)
 !12 = !{null, !13, !14}
-!13 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !4} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from Foo]
-!14 = !{!"0x16\00SEL\005\000\000\000\0064", !5, null, !15} ; [ DW_TAG_typedef ] [SEL] [line 5, size 0, align 0, offset 0] [artificial] [from ]
-!15 = !{!"0xf\00\000\0064\0064\000\000", null, null, !16} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from objc_selector]
-!16 = !{!"0x13\00objc_selector\000\000\000\000\004\000", !1, null, null, null, null, null, null} ; [ DW_TAG_structure_type ] [objc_selector] [line 0, size 0, align 0, offset 0] [decl] [from ]
+!13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !4)
+!14 = !DIDerivedType(tag: DW_TAG_typedef, name: "SEL", line: 5, flags: DIFlagArtificial, file: !5, baseType: !15)
+!15 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !16)
+!16 = !DICompositeType(tag: DW_TAG_structure_type, name: "objc_selector", flags: DIFlagFwdDecl, file: !1)
 !17 = !{i32 1, !"Objective-C Version", i32 2}
 !18 = !{i32 1, !"Objective-C Image Info Version", i32 0}
 !19 = !{i32 1, !"Objective-C Image Info Section", !"__DATA, __objc_imageinfo, regular, no_dead_strip"}
 !20 = !{i32 4, !"Objective-C Garbage Collection", i32 0}
 !21 = !{i32 2, !"Dwarf Version", i32 2}
-!22 = !{i32 1, !"Debug Info Version", i32 2}
+!22 = !{i32 1, !"Debug Info Version", i32 3}
 !23 = !{!""}
-!24 = !{!"0x101\00self\0016777216\001088", !10, null, !25} ; [ DW_TAG_arg_variable ] [self] [line 0]
-!25 = !{!"0xf\00\000\0064\0064\000\000", null, null, !4} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from Foo]
-!26 = !MDLocation(line: 0, scope: !10)
-!27 = !{!"0x101\00_cmd\0033554432\0064", !10, null, !28} ; [ DW_TAG_arg_variable ] [_cmd] [line 0]
-!28 = !{!"0x16\00SEL\005\000\000\000\000", !5, null, !15} ; [ DW_TAG_typedef ] [SEL] [line 5, size 0, align 0, offset 0] [from ]
-!29 = !MDLocation(line: 5, scope: !10)
+!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "self", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !10, type: !25)
+!25 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !4)
+!26 = !DILocation(line: 0, scope: !10)
+!27 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "_cmd", arg: 2, flags: DIFlagArtificial, scope: !10, type: !28)
+!28 = !DIDerivedType(tag: DW_TAG_typedef, name: "SEL", line: 5, file: !5, baseType: !15)
+!29 = !DILocation(line: 5, scope: !10)
diff --git a/test/DebugInfo/X86/op_deref.ll b/test/DebugInfo/X86/op_deref.ll
index 2aff5c2e8e0f..86f629e9c152 100644
--- a/test/DebugInfo/X86/op_deref.ll
+++ b/test/DebugInfo/X86/op_deref.ll
@@ -24,7 +24,7 @@
 ; ASM-CHECK: DW_OP_breg2
 
 ; RUN: llvm-as %s -o - | llvm-dis - | FileCheck %s --check-prefix=PRETTY-PRINT
-; PRETTY-PRINT: [ DW_TAG_expression ] [DW_OP_deref]
+; PRETTY-PRINT: DIExpression(DW_OP_deref, DW_OP_deref)
 
 define void @testVLAwithSize(i32 %s) nounwind uwtable ssp {
 entry:
@@ -32,41 +32,41 @@ entry:
   %saved_stack = alloca i8*
   %i = alloca i32, align 4
   store i32 %s, i32* %s.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %s.addr, metadata !10, metadata !{!"0x102"}), !dbg !11
-  %0 = load i32* %s.addr, align 4, !dbg !12
+  call void @llvm.dbg.declare(metadata i32* %s.addr, metadata !10, metadata !DIExpression()), !dbg !11
+  %0 = load i32, i32* %s.addr, align 4, !dbg !12
   %1 = zext i32 %0 to i64, !dbg !12
   %2 = call i8* @llvm.stacksave(), !dbg !12
   store i8* %2, i8** %saved_stack, !dbg !12
   %vla = alloca i32, i64 %1, align 16, !dbg !12
   call void @llvm.dbg.declare(metadata i32* %vla, metadata !14, metadata !30), !dbg !18
-  call void @llvm.dbg.declare(metadata i32* %i, metadata !19, metadata !{!"0x102"}), !dbg !20
+  call void @llvm.dbg.declare(metadata i32* %i, metadata !19, metadata !DIExpression()), !dbg !20
   store i32 0, i32* %i, align 4, !dbg !21
   br label %for.cond, !dbg !21
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %3 = load i32* %i, align 4, !dbg !21
-  %4 = load i32* %s.addr, align 4, !dbg !21
+  %3 = load i32, i32* %i, align 4, !dbg !21
+  %4 = load i32, i32* %s.addr, align 4, !dbg !21
   %cmp = icmp slt i32 %3, %4, !dbg !21
   br i1 %cmp, label %for.body, label %for.end, !dbg !21
 
 for.body:                                         ; preds = %for.cond
-  %5 = load i32* %i, align 4, !dbg !23
-  %6 = load i32* %i, align 4, !dbg !23
+  %5 = load i32, i32* %i, align 4, !dbg !23
+  %6 = load i32, i32* %i, align 4, !dbg !23
   %mul = mul nsw i32 %5, %6, !dbg !23
-  %7 = load i32* %i, align 4, !dbg !23
+  %7 = load i32, i32* %i, align 4, !dbg !23
   %idxprom = sext i32 %7 to i64, !dbg !23
-  %arrayidx = getelementptr inbounds i32* %vla, i64 %idxprom, !dbg !23
+  %arrayidx = getelementptr inbounds i32, i32* %vla, i64 %idxprom, !dbg !23
   store i32 %mul, i32* %arrayidx, align 4, !dbg !23
   br label %for.inc, !dbg !25
 
 for.inc:                                          ; preds = %for.body
-  %8 = load i32* %i, align 4, !dbg !26
+  %8 = load i32, i32* %i, align 4, !dbg !26
   %inc = add nsw i32 %8, 1, !dbg !26
   store i32 %inc, i32* %i, align 4, !dbg !26
   br label %for.cond, !dbg !26
 
 for.end:                                          ; preds = %for.cond
-  %9 = load i8** %saved_stack, !dbg !27
+  %9 = load i8*, i8** %saved_stack, !dbg !27
   call void @llvm.stackrestore(i8* %9), !dbg !27
   ret void, !dbg !27
 }
@@ -80,32 +80,32 @@ declare void @llvm.stackrestore(i8*) nounwind
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!29}
 
-!0 = !{!"0x11\0012\00clang version 3.2 (trunk 156005) (llvm/trunk 156000)\000\00\000\00\001", !28, !1, !1, !3, !1,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.2 (trunk 156005) (llvm/trunk 156000)", isOptimized: false, emissionKind: 1, file: !28, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00testVLAwithSize\00testVLAwithSize\00\001\000\001\000\006\00256\000\002", !28, !6, !7, null, void (i32)* @testVLAwithSize, null, null, !1} ; [ DW_TAG_subprogram ]
-!6 = !{!"0x29", !28} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "testVLAwithSize", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !28, scope: !6, type: !7, function: void (i32)* @testVLAwithSize, variables: !1)
+!6 = !DIFile(filename: "bar.c", directory: "/Users/echristo/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!10 = !{!"0x101\00s\0016777217\000", !5, !6, !9} ; [ DW_TAG_arg_variable ]
-!11 = !MDLocation(line: 1, column: 26, scope: !5)
-!12 = !MDLocation(line: 3, column: 13, scope: !13)
-!13 = !{!"0xb\002\001\000", !28, !5} ; [ DW_TAG_lexical_block ]
-!14 = !{!"0x100\00vla\003\008192", !13, !6, !15} ; [ DW_TAG_auto_variable ]
-!15 = !{!"0x1\00\000\000\0032\000\000", null, null, !9, !16, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 0, align 32, offset 0] [from int]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "s", line: 1, arg: 1, scope: !5, file: !6, type: !9)
+!11 = !DILocation(line: 1, column: 26, scope: !5)
+!12 = !DILocation(line: 3, column: 13, scope: !13)
+!13 = distinct !DILexicalBlock(line: 2, column: 1, file: !28, scope: !5)
+!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vla", line: 3, scope: !13, file: !6, type: !15)
+!15 = !DICompositeType(tag: DW_TAG_array_type, align: 32, baseType: !9, elements: !16)
 !16 = !{!17}
-!17 = !{!"0x21\000\00-1"}        ; [ DW_TAG_subrange_type ]
-!18 = !MDLocation(line: 3, column: 7, scope: !13)
-!19 = !{!"0x100\00i\004\000", !13, !6, !9} ; [ DW_TAG_auto_variable ]
-!20 = !MDLocation(line: 4, column: 7, scope: !13)
-!21 = !MDLocation(line: 5, column: 8, scope: !22)
-!22 = !{!"0xb\005\003\001", !28, !13} ; [ DW_TAG_lexical_block ]
-!23 = !MDLocation(line: 6, column: 5, scope: !24)
-!24 = !{!"0xb\005\0027\002", !28, !22} ; [ DW_TAG_lexical_block ]
-!25 = !MDLocation(line: 7, column: 3, scope: !24)
-!26 = !MDLocation(line: 5, column: 22, scope: !22)
-!27 = !MDLocation(line: 8, column: 1, scope: !13)
-!28 = !{!"bar.c", !"/Users/echristo/tmp"}
-!29 = !{i32 1, !"Debug Info Version", i32 2}
-!30 = !{!"0x102\006"} ; [ DW_TAG_expression ] [DW_OP_deref]
+!17 = !DISubrange(count: -1)
+!18 = !DILocation(line: 3, column: 7, scope: !13)
+!19 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 4, scope: !13, file: !6, type: !9)
+!20 = !DILocation(line: 4, column: 7, scope: !13)
+!21 = !DILocation(line: 5, column: 8, scope: !22)
+!22 = distinct !DILexicalBlock(line: 5, column: 3, file: !28, scope: !13)
+!23 = !DILocation(line: 6, column: 5, scope: !24)
+!24 = distinct !DILexicalBlock(line: 5, column: 27, file: !28, scope: !22)
+!25 = !DILocation(line: 7, column: 3, scope: !24)
+!26 = !DILocation(line: 5, column: 22, scope: !22)
+!27 = !DILocation(line: 8, column: 1, scope: !13)
+!28 = !DIFile(filename: "bar.c", directory: "/Users/echristo/tmp")
+!29 = !{i32 1, !"Debug Info Version", i32 3}
+!30 = !DIExpression(DW_OP_deref, DW_OP_deref)
diff --git a/test/DebugInfo/X86/parameters.ll b/test/DebugInfo/X86/parameters.ll
index 1655f09790eb..044f51e6e6b9 100644
--- a/test/DebugInfo/X86/parameters.ll
+++ b/test/DebugInfo/X86/parameters.ll
@@ -42,7 +42,7 @@
 ; Function Attrs: uwtable
 define void @_ZN7pr147634funcENS_3fooE(%"struct.pr14763::foo"* noalias sret %agg.result, %"struct.pr14763::foo"* %f) #0 {
 entry:
-  call void @llvm.dbg.declare(metadata %"struct.pr14763::foo"* %f, metadata !22, metadata !{!"0x102"}), !dbg !24
+  call void @llvm.dbg.declare(metadata %"struct.pr14763::foo"* %f, metadata !22, metadata !DIExpression(DW_OP_deref)), !dbg !24
   call void @_ZN7pr147633fooC1ERKS0_(%"struct.pr14763::foo"* %agg.result, %"struct.pr14763::foo"* %f), !dbg !25
   ret void, !dbg !25
 }
@@ -58,9 +58,9 @@ entry:
   %b.addr = alloca i8, align 1
   %frombool = zext i1 %b to i8
   store i8 %frombool, i8* %b.addr, align 1
-  call void @llvm.dbg.declare(metadata i8* %b.addr, metadata !26, metadata !{!"0x102"}), !dbg !27
-  call void @llvm.dbg.declare(metadata %"struct.pr14763::foo"* %g, metadata !28, metadata !{!"0x102"}), !dbg !27
-  %0 = load i8* %b.addr, align 1, !dbg !29
+  call void @llvm.dbg.declare(metadata i8* %b.addr, metadata !26, metadata !DIExpression()), !dbg !27
+  call void @llvm.dbg.declare(metadata %"struct.pr14763::foo"* %g, metadata !28, metadata !DIExpression(DW_OP_deref)), !dbg !27
+  %0 = load i8, i8* %b.addr, align 1, !dbg !29
   %tobool = trunc i8 %0 to i1, !dbg !29
   br i1 %tobool, label %if.then, label %if.end, !dbg !29
 
@@ -82,37 +82,36 @@ attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!21, !33}
 
-!0 = !{!"0x11\004\00clang version 3.4 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/pass.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"pass.cpp", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "pass.cpp", directory: "/tmp")
 !2 = !{}
 !3 = !{!4, !17}
-!4 = !{!"0x2e\00func\00func\00_ZN7pr147634funcENS_3fooE\006\000\001\000\006\00256\000\006", !1, !5, !6, null, void (%"struct.pr14763::foo"*, %"struct.pr14763::foo"*)* @_ZN7pr147634funcENS_3fooE, null, null, !2} ; [ DW_TAG_subprogram ] [line 6] [def] [func]
-!5 = !{!"0x39\00pr14763\001", !1, null} ; [ DW_TAG_namespace ] [pr14763] [line 1]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "func", linkageName: "_ZN7pr147634funcENS_3fooE", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 6, file: !1, scope: !5, type: !6, function: void (%"struct.pr14763::foo"*, %"struct.pr14763::foo"*)* @_ZN7pr147634funcENS_3fooE, variables: !2)
+!5 = !DINamespace(name: "pr14763", line: 1, file: !1, scope: null)
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8}
-!8 = !{!"0x13\00foo\002\008\008\000\000\000", !1, !5, null, !9, null, null, null} ; [ DW_TAG_structure_type ] [foo] [line 2, size 8, align 8, offset 0] [def] [from ]
+!8 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo", line: 2, size: 8, align: 8, file: !1, scope: !5, elements: !9)
 !9 = !{!10}
-!10 = !{!"0x2e\00foo\00foo\00\003\000\000\000\006\00256\000\003", !1, !8, !11, null, null, null, i32 0, !16} ; [ DW_TAG_subprogram ] [line 3] [foo]
-!11 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!10 = !DISubprogram(name: "foo", line: 3, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !8, type: !11)
+!11 = !DISubroutineType(types: !12)
 !12 = !{null, !13, !14}
-!13 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !8} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from foo]
-!14 = !{!"0x10\00\000\000\000\000\000", null, null, !15} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from ]
-!15 = !{!"0x26\00\000\000\000\000\000", null, null, !8} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from foo]
-!16 = !{i32 786468}
-!17 = !{!"0x2e\00func2\00func2\00_ZN7pr147635func2EbNS_3fooE\0012\000\001\000\006\00256\000\0012", !1, !5, !18, null, void (i1, %"struct.pr14763::foo"*)* @_ZN7pr147635func2EbNS_3fooE, null, null, !2} ; [ DW_TAG_subprogram ] [line 12] [def] [func2]
-!18 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !19, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !8)
+!14 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !15)
+!15 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !8)
+!17 = !DISubprogram(name: "func2", linkageName: "_ZN7pr147635func2EbNS_3fooE", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 12, file: !1, scope: !5, type: !18, function: void (i1, %"struct.pr14763::foo"*)* @_ZN7pr147635func2EbNS_3fooE, variables: !2)
+!18 = !DISubroutineType(types: !19)
 !19 = !{null, !20, !8}
-!20 = !{!"0x24\00bool\000\008\008\000\000\002", null, null} ; [ DW_TAG_base_type ] [bool] [line 0, size 8, align 8, offset 0, enc DW_ATE_boolean]
+!20 = !DIBasicType(tag: DW_TAG_base_type, name: "bool", size: 8, align: 8, encoding: DW_ATE_boolean)
 !21 = !{i32 2, !"Dwarf Version", i32 3}
-!22 = !{!"0x101\00f\0016777222\008192", !4, !23, !8} ; [ DW_TAG_arg_variable ] [f] [line 6]
-!23 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/tmp/pass.cpp]
-!24 = !MDLocation(line: 6, scope: !4)
-!25 = !MDLocation(line: 7, scope: !4)
-!26 = !{!"0x101\00b\0016777228\000", !17, !23, !20} ; [ DW_TAG_arg_variable ] [b] [line 12]
-!27 = !MDLocation(line: 12, scope: !17)
-!28 = !{!"0x101\00g\0033554444\008192", !17, !23, !8} ; [ DW_TAG_arg_variable ] [g] [line 12]
-!29 = !MDLocation(line: 13, scope: !30)
-!30 = !{!"0xb\0013\000\000", !1, !17} ; [ DW_TAG_lexical_block ] [/tmp/pass.cpp]
-!31 = !MDLocation(line: 14, scope: !30)
-!32 = !MDLocation(line: 15, scope: !17)
-!33 = !{i32 1, !"Debug Info Version", i32 2}
+!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "f", line: 6, arg: 1, scope: !4, file: !23, type: !8)
+!23 = !DIFile(filename: "pass.cpp", directory: "/tmp")
+!24 = !DILocation(line: 6, scope: !4)
+!25 = !DILocation(line: 7, scope: !4)
+!26 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 12, arg: 1, scope: !17, file: !23, type: !20)
+!27 = !DILocation(line: 12, scope: !17)
+!28 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "g", line: 12, arg: 2, scope: !17, file: !23, type: !8)
+!29 = !DILocation(line: 13, scope: !30)
+!30 = distinct !DILexicalBlock(line: 13, column: 0, file: !1, scope: !17)
+!31 = !DILocation(line: 14, scope: !30)
+!32 = !DILocation(line: 15, scope: !17)
+!33 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/pieces-1.ll b/test/DebugInfo/X86/pieces-1.ll
index 4c11a8b969cd..f96e045f8285 100644
--- a/test/DebugInfo/X86/pieces-1.ll
+++ b/test/DebugInfo/X86/pieces-1.ll
@@ -50,30 +50,30 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!17, !18}
 !llvm.ident = !{!19}
 
-!0 = !{!"0x11\0012\00clang version 3.5 \001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ]
-!1 = !{!"pieces.c", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "pieces.c", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\003\000\001\000\006\00256\001\003", !1, !5, !6, null, i32 (i64, i32)* @foo, null, null, !15} ; [ DW_TAG_subprogram ] [line 3] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/pieces.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !1, scope: !5, type: !6, function: i32 (i64, i32)* @foo, variables: !15)
+!5 = !DIFile(filename: "pieces.c", directory: "")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !9}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x16\00S\001\000\000\000\000", !1, null, !10} ; [ DW_TAG_typedef ] [S] [line 1, size 0, align 0, offset 0] [from ]
-!10 = !{!"0x13\00\001\00128\0064\000\000\000", !1, null, null, !11, null, null, null} ; [ DW_TAG_structure_type ] [line 1, size 128, align 64, offset 0] [def] [from ]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_typedef, name: "S", line: 1, file: !1, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_structure_type, line: 1, size: 128, align: 64, file: !1, elements: !11)
 !11 = !{!12, !14}
-!12 = !{!"0xd\00a\001\0064\0064\000\000", !1, !10, !13} ; [ DW_TAG_member ] [a] [line 1, size 64, align 64, offset 0] [from long int]
-!13 = !{!"0x24\00long int\000\0064\0064\000\000\005", null, null} ; [ DW_TAG_base_type ] [long int] [line 0, size 64, align 64, offset 0, enc DW_ATE_signed]
-!14 = !{!"0xd\00b\001\0032\0032\0064\000", !1, !10, !8} ; [ DW_TAG_member ] [b] [line 1, size 32, align 32, offset 64] [from int]
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 1, size: 64, align: 64, file: !1, scope: !10, baseType: !13)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "long int", size: 64, align: 64, encoding: DW_ATE_signed)
+!14 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 1, size: 32, align: 32, offset: 64, file: !1, scope: !10, baseType: !8)
 !15 = !{!16}
-!16 = !{!"0x101\00s\0016777219\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [s] [line 3]
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "s", line: 3, arg: 1, scope: !4, file: !5, type: !9)
 !17 = !{i32 2, !"Dwarf Version", i32 4}
-!18 = !{i32 1, !"Debug Info Version", i32 2}
+!18 = !{i32 1, !"Debug Info Version", i32 3}
 !19 = !{!"clang version 3.5 "}
-!20 = !{!"0x101\00s\0016777219\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [s] [line 3]
-!21 = !MDLocation(line: 3, scope: !4)
-!22 = !{!"0x101\00s\0016777219\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [s] [line 3]
-!23 = !MDLocation(line: 4, scope: !4)
-!24 = !{!"0x102\00147\000\008"} ; [ DW_TAG_expression ] [DW_OP_piece 0 8] [piece, size 8, offset 0]
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "s", line: 3, arg: 1, scope: !4, file: !5, type: !9)
+!21 = !DILocation(line: 3, scope: !4)
+!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "s", line: 3, arg: 1, scope: !4, file: !5, type: !9)
+!23 = !DILocation(line: 4, scope: !4)
+!24 = !DIExpression(DW_OP_bit_piece, 0, 64)
 !25 = !{}
-!27 = !{!"0x102\00147\008\004"} ; [ DW_TAG_expression ] [DW_OP_piece 8 4] [piece, size 4, offset 8]
+!27 = !DIExpression(DW_OP_bit_piece, 64, 32)
diff --git a/test/DebugInfo/X86/pieces-2.ll b/test/DebugInfo/X86/pieces-2.ll
index 184840956fd3..7c39d323c3e3 100644
--- a/test/DebugInfo/X86/pieces-2.ll
+++ b/test/DebugInfo/X86/pieces-2.ll
@@ -31,12 +31,12 @@ target triple = "x86_64-apple-macosx10.9.0"
 ; Function Attrs: nounwind ssp uwtable
 define i32 @foo(%struct.Outer* byval align 8 %outer) #0 {
 entry:
-  call void @llvm.dbg.declare(metadata %struct.Outer* %outer, metadata !25, metadata !{!"0x102"}), !dbg !26
-  %i1.sroa.0.0..sroa_idx = getelementptr inbounds %struct.Outer* %outer, i64 0, i32 0, i64 1, i32 0, !dbg !27
-  %i1.sroa.0.0.copyload = load i32* %i1.sroa.0.0..sroa_idx, align 8, !dbg !27
+  call void @llvm.dbg.declare(metadata %struct.Outer* %outer, metadata !25, metadata !DIExpression()), !dbg !26
+  %i1.sroa.0.0..sroa_idx = getelementptr inbounds %struct.Outer, %struct.Outer* %outer, i64 0, i32 0, i64 1, i32 0, !dbg !27
+  %i1.sroa.0.0.copyload = load i32, i32* %i1.sroa.0.0..sroa_idx, align 8, !dbg !27
   call void @llvm.dbg.value(metadata i32 %i1.sroa.0.0.copyload, i64 0, metadata !28, metadata !29), !dbg !27
   %i1.sroa.2.0..sroa_raw_cast = bitcast %struct.Outer* %outer to i8*, !dbg !27
-  %i1.sroa.2.0..sroa_raw_idx = getelementptr inbounds i8* %i1.sroa.2.0..sroa_raw_cast, i64 20, !dbg !27
+  %i1.sroa.2.0..sroa_raw_idx = getelementptr inbounds i8, i8* %i1.sroa.2.0..sroa_raw_cast, i64 20, !dbg !27
   ret i32 %i1.sroa.0.0.copyload, !dbg !32
 }
 
@@ -57,35 +57,35 @@ attributes #2 = { nounwind }
 !llvm.module.flags = !{!22, !23}
 !llvm.ident = !{!24}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/sroasplit-1.c] [DW_LANG_C99]
-!1 = !{!"sroasplit-1.c", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "sroasplit-1.c", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\0010\000\001\000\006\00256\000\0010", !1, !5, !6, null, i32 (%struct.Outer*)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 10] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/sroasplit-1.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 10, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 10, file: !1, scope: !5, type: !6, function: i32 (%struct.Outer*)* @foo, variables: !2)
+!5 = !DIFile(filename: "sroasplit-1.c", directory: "")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !9}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x16\00Outer\008\000\000\000\000", !1, null, !10} ; [ DW_TAG_typedef ] [Outer] [line 8, size 0, align 0, offset 0] [from ]
-!10 = !{!"0x13\00\006\00256\0064\000\000\000", !1, null, null, !11, null, null, null} ; [ DW_TAG_structure_type ] [line 6, size 256, align 64, offset 0] [def] [from ]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_typedef, name: "Outer", line: 8, file: !1, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_structure_type, line: 6, size: 256, align: 64, file: !1, elements: !11)
 !11 = !{!12}
-!12 = !{!"0xd\00inner\007\00256\0064\000\000", !1, !10, !13} ; [ DW_TAG_member ] [inner] [line 7, size 256, align 64, offset 0] [from ]
-!13 = !{!"0x1\00\000\00256\0064\000\000", null, null, !14, !20, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 256, align 64, offset 0] [from Inner]
-!14 = !{!"0x16\00Inner\004\000\000\000\000", !1, null, !15} ; [ DW_TAG_typedef ] [Inner] [line 4, size 0, align 0, offset 0] [from ]
-!15 = !{!"0x13\00\001\00128\0064\000\000\000", !1, null, null, !16, null, null, null} ; [ DW_TAG_structure_type ] [line 1, size 128, align 64, offset 0] [def] [from ]
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "inner", line: 7, size: 256, align: 64, file: !1, scope: !10, baseType: !13)
+!13 = !DICompositeType(tag: DW_TAG_array_type, size: 256, align: 64, baseType: !14, elements: !20)
+!14 = !DIDerivedType(tag: DW_TAG_typedef, name: "Inner", line: 4, file: !1, baseType: !15)
+!15 = !DICompositeType(tag: DW_TAG_structure_type, line: 1, size: 128, align: 64, file: !1, elements: !16)
 !16 = !{!17, !18}
-!17 = !{!"0xd\00a\002\0032\0032\000\000", !1, !15, !8} ; [ DW_TAG_member ] [a] [line 2, size 32, align 32, offset 0] [from int]
-!18 = !{!"0xd\00b\003\0064\0064\0064\000", !1, !15, !19} ; [ DW_TAG_member ] [b] [line 3, size 64, align 64, offset 64] [from long int]
-!19 = !{!"0x24\00long int\000\0064\0064\000\000\005", null, null} ; [ DW_TAG_base_type ] [long int] [line 0, size 64, align 64, offset 0, enc DW_ATE_signed]
+!17 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 2, size: 32, align: 32, file: !1, scope: !15, baseType: !8)
+!18 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 3, size: 64, align: 64, offset: 64, file: !1, scope: !15, baseType: !19)
+!19 = !DIBasicType(tag: DW_TAG_base_type, name: "long int", size: 64, align: 64, encoding: DW_ATE_signed)
 !20 = !{!21}
-!21 = !{!"0x21\000\002"}        ; [ DW_TAG_subrange_type ] [0, 1]
+!21 = !DISubrange(count: 2)
 !22 = !{i32 2, !"Dwarf Version", i32 2}
-!23 = !{i32 1, !"Debug Info Version", i32 2}
+!23 = !{i32 1, !"Debug Info Version", i32 3}
 !24 = !{!"clang version 3.5.0 "}
-!25 = !{!"0x101\00outer\0016777226\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [outer] [line 10]
-!26 = !MDLocation(line: 10, scope: !4)
-!27 = !MDLocation(line: 11, scope: !4)
-!28 = !{!"0x100\00i1\0011\000", !4, !5, !14} ; [ DW_TAG_auto_variable ] [i1] [line 11]
-!29 = !{!"0x102\00147\000\004"} ; [ DW_TAG_expression ] [DW_OP_piece 0 4] [piece, size 4, offset 0]
+!25 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "outer", line: 10, arg: 1, scope: !4, file: !5, type: !9)
+!26 = !DILocation(line: 10, scope: !4)
+!27 = !DILocation(line: 11, scope: !4)
+!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i1", line: 11, scope: !4, file: !5, type: !14)
+!29 = !DIExpression(DW_OP_bit_piece, 0, 32)
 !31 = !{i32 3, i32 0, i32 12}
-!32 = !MDLocation(line: 12, scope: !4)
+!32 = !DILocation(line: 12, scope: !4)
diff --git a/test/DebugInfo/X86/pieces-3.ll b/test/DebugInfo/X86/pieces-3.ll
index 3e4965fcf81a..97ff9aadfcfc 100644
--- a/test/DebugInfo/X86/pieces-3.ll
+++ b/test/DebugInfo/X86/pieces-3.ll
@@ -67,40 +67,40 @@ attributes #2 = { nounwind }
 !llvm.module.flags = !{!21, !22}
 !llvm.ident = !{!23}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/sroasplit-2.c] [DW_LANG_C99]
-!1 = !{!"sroasplit-2.c", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "sroasplit-2.c", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\0010\000\001\000\006\00256\000\0010", !1, !5, !6, null, i32 (i64, i64)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 10] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/sroasplit-2.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 10, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 10, file: !1, scope: !5, type: !6, function: i32 (i64, i64)* @foo, variables: !2)
+!5 = !DIFile(filename: "sroasplit-2.c", directory: "")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !9}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x16\00Outer\008\000\000\000\000", !1, null, !10} ; [ DW_TAG_typedef ] [Outer] [line 8, size 0, align 0, offset 0] [from ]
-!10 = !{!"0x13\00\006\00128\0032\000\000\000", !1, null, null, !11, null, null, null} ; [ DW_TAG_structure_type ] [line 6, size 128, align 32, offset 0] [def] [from ]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_typedef, name: "Outer", line: 8, file: !1, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_structure_type, line: 6, size: 128, align: 32, file: !1, elements: !11)
 !11 = !{!12}
-!12 = !{!"0xd\00inner\007\00128\0032\000\000", !1, !10, !13} ; [ DW_TAG_member ] [inner] [line 7, size 128, align 32, offset 0] [from ]
-!13 = !{!"0x1\00\000\00128\0032\000\000", null, null, !14, !19, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 32, offset 0] [from Inner]
-!14 = !{!"0x16\00Inner\004\000\000\000\000", !1, null, !15} ; [ DW_TAG_typedef ] [Inner] [line 4, size 0, align 0, offset 0] [from ]
-!15 = !{!"0x13\00\001\0064\0032\000\000\000", !1, null, null, !16, null, null, null} ; [ DW_TAG_structure_type ] [line 1, size 64, align 32, offset 0] [def] [from ]
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "inner", line: 7, size: 128, align: 32, file: !1, scope: !10, baseType: !13)
+!13 = !DICompositeType(tag: DW_TAG_array_type, size: 128, align: 32, baseType: !14, elements: !19)
+!14 = !DIDerivedType(tag: DW_TAG_typedef, name: "Inner", line: 4, file: !1, baseType: !15)
+!15 = !DICompositeType(tag: DW_TAG_structure_type, line: 1, size: 64, align: 32, file: !1, elements: !16)
 !16 = !{!17, !18}
-!17 = !{!"0xd\00a\002\0032\0032\000\000", !1, !15, !8} ; [ DW_TAG_member ] [a] [line 2, size 32, align 32, offset 0] [from int]
-!18 = !{!"0xd\00b\003\0032\0032\0032\000", !1, !15, !8} ; [ DW_TAG_member ] [b] [line 3, size 32, align 32, offset 32] [from int]
+!17 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 2, size: 32, align: 32, file: !1, scope: !15, baseType: !8)
+!18 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 3, size: 32, align: 32, offset: 32, file: !1, scope: !15, baseType: !8)
 !19 = !{!20}
-!20 = !{!"0x21\000\002"}        ; [ DW_TAG_subrange_type ] [0, 1]
+!20 = !DISubrange(count: 2)
 !21 = !{i32 2, !"Dwarf Version", i32 2}
-!22 = !{i32 1, !"Debug Info Version", i32 2}
+!22 = !{i32 1, !"Debug Info Version", i32 3}
 !23 = !{!"clang version 3.5.0 "}
-!24 = !{!"0x101\00outer\0016777226\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [outer] [line 10]
-!25 = !{!"0x102\00147\000\008"} ; [ DW_TAG_expression ] [DW_OP_piece 0 8] [piece, size 8, offset 0]
-!26 = !MDLocation(line: 10, scope: !4)
-!27 = !{!"0x101\00outer\0016777226\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [outer] [line 10]
-!28 = !{!"0x102\00147\008\008"} ; [ DW_TAG_expression ] [DW_OP_piece 8 8] [piece, size 8, offset 8]
-!29 = !{!"0x101\00outer\0016777226\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [outer] [line 10]
-!30 = !{!"0x102\00147\0012\004"} ; [ DW_TAG_expression ] [DW_OP_piece 12 4] [piece, size 4, offset 12]
-!31 = !{!"0x101\00outer\0016777226\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [outer] [line 10]
-!32 = !{!"0x102\00147\008\004"} ; [ DW_TAG_expression ] [DW_OP_piece 8 4] [piece, size 4, offset 8]
-!33 = !MDLocation(line: 11, scope: !4)
-!34 = !{!"0x100\00i1\0011\000", !4, !5, !14} ; [ DW_TAG_auto_variable ] [i1] [line 11]
-!35 = !{!"0x102\00147\000\004"} ; [ DW_TAG_expression ] [DW_OP_piece 0 4] [piece, size 4, offset 0]
-!36 = !MDLocation(line: 12, scope: !4)
+!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "outer", line: 10, arg: 1, scope: !4, file: !5, type: !9)
+!25 = !DIExpression(DW_OP_bit_piece, 0, 64)
+!26 = !DILocation(line: 10, scope: !4)
+!27 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "outer", line: 10, arg: 1, scope: !4, file: !5, type: !9)
+!28 = !DIExpression(DW_OP_bit_piece, 64, 64)
+!29 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "outer", line: 10, arg: 1, scope: !4, file: !5, type: !9)
+!30 = !DIExpression(DW_OP_bit_piece, 96, 32)
+!31 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "outer", line: 10, arg: 1, scope: !4, file: !5, type: !9)
+!32 = !DIExpression(DW_OP_bit_piece, 64, 32)
+!33 = !DILocation(line: 11, scope: !4)
+!34 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i1", line: 11, scope: !4, file: !5, type: !14)
+!35 = !DIExpression(DW_OP_bit_piece, 0, 32)
+!36 = !DILocation(line: 12, scope: !4)
diff --git a/test/DebugInfo/X86/pointer-type-size.ll b/test/DebugInfo/X86/pointer-type-size.ll
index a7f569df827e..f5abdfe89251 100644
--- a/test/DebugInfo/X86/pointer-type-size.ll
+++ b/test/DebugInfo/X86/pointer-type-size.ll
@@ -11,16 +11,16 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!14}
 
-!0 = !{!"0x11\0012\00clang version 3.1 (trunk 147882)\000\00\000\00\000", !13, !1, !1, !1, !3,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.1 (trunk 147882)", isOptimized: false, emissionKind: 0, file: !13, enums: !1, retainedTypes: !1, subprograms: !1, globals: !3, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x34\00crass\00crass\00\001\000\001", null, !6, !7, %struct.crass* @crass, null} ; [ DW_TAG_variable ]
-!6 = !{!"0x29", !13} ; [ DW_TAG_file_type ]
-!7 = !{!"0x13\00crass\001\0064\0064\000\000\000", !13, null, null, !8, null, null, null} ; [ DW_TAG_structure_type ] [crass] [line 1, size 64, align 64, offset 0] [def] [from ]
+!5 = !DIGlobalVariable(name: "crass", line: 1, isLocal: false, isDefinition: true, scope: null, file: !6, type: !7, variable: %struct.crass* @crass)
+!6 = !DIFile(filename: "foo.c", directory: "/Users/echristo/tmp")
+!7 = !DICompositeType(tag: DW_TAG_structure_type, name: "crass", line: 1, size: 64, align: 64, file: !13, elements: !8)
 !8 = !{!9}
-!9 = !{!"0xd\00ptr\001\0064\0064\000\000", !13, !7, !10} ; [ DW_TAG_member ]
-!10 = !{!"0x26\00\000\000\000\000\000", null, null, !11} ; [ DW_TAG_const_type ]
-!11 = !{!"0xf\00\000\0064\0064\000\000", null, null, !12} ; [ DW_TAG_pointer_type ]
-!12 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ]
-!13 = !{!"foo.c", !"/Users/echristo/tmp"}
-!14 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "ptr", line: 1, size: 64, align: 64, file: !13, scope: !7, baseType: !10)
+!10 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !11)
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !12)
+!12 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!13 = !DIFile(filename: "foo.c", directory: "/Users/echristo/tmp")
+!14 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/pr11300.ll b/test/DebugInfo/X86/pr11300.ll
index 53e85acf82cc..b68609dd7184 100644
--- a/test/DebugInfo/X86/pr11300.ll
+++ b/test/DebugInfo/X86/pr11300.ll
@@ -7,7 +7,7 @@
 ; CHECK: DW_TAG_subprogram
 ; CHECK: DW_TAG_class_type
 ; CHECK:   DW_TAG_subprogram
-; CHECK:     DW_AT_MIPS_linkage_name {{.*}} "_ZN3foo3barEv"
+; CHECK:     DW_AT_linkage_name {{.*}} "_ZN3foo3barEv"
 ; CHECK: DW_TAG_subprogram
 ; CHECK-NOT: DW_TAG
 ; CHECK:   DW_AT_specification {{.*}} "_ZN3foo3barEv"
@@ -18,8 +18,8 @@ define void @_Z3zedP3foo(%struct.foo* %x) uwtable {
 entry:
   %x.addr = alloca %struct.foo*, align 8
   store %struct.foo* %x, %struct.foo** %x.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.foo** %x.addr, metadata !23, metadata !{!"0x102"}), !dbg !24
-  %0 = load %struct.foo** %x.addr, align 8, !dbg !25
+  call void @llvm.dbg.declare(metadata %struct.foo** %x.addr, metadata !23, metadata !DIExpression()), !dbg !24
+  %0 = load %struct.foo*, %struct.foo** %x.addr, align 8, !dbg !25
   call void @_ZN3foo3barEv(%struct.foo* %0), !dbg !25
   ret void, !dbg !27
 }
@@ -30,41 +30,37 @@ define linkonce_odr void @_ZN3foo3barEv(%struct.foo* %this) nounwind uwtable ali
 entry:
   %this.addr = alloca %struct.foo*, align 8
   store %struct.foo* %this, %struct.foo** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.foo** %this.addr, metadata !28, metadata !{!"0x102"}), !dbg !29
-  %this1 = load %struct.foo** %this.addr
+  call void @llvm.dbg.declare(metadata %struct.foo** %this.addr, metadata !28, metadata !DIExpression()), !dbg !29
+  %this1 = load %struct.foo*, %struct.foo** %this.addr
   ret void, !dbg !30
 }
 
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!33}
 
-!0 = !{!"0x11\004\00clang version 3.0 ()\000\00\000\00\000", !32, !1, !1, !3, !1,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.0 ()", isOptimized: false, emissionKind: 0, file: !32, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports:  !1)
 !1 = !{}
 !3 = !{!5, !20}
-!5 = !{!"0x2e\00zed\00zed\00_Z3zedP3foo\004\000\001\000\006\00256\000\004", !6, !6, !7, null, void (%struct.foo*)* @_Z3zedP3foo, null, null, null} ; [ DW_TAG_subprogram ] [line 4] [def] [zed]
-!6 = !{!"0x29", !32} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "zed", linkageName: "_Z3zedP3foo", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !6, scope: !6, type: !7, function: void (%struct.foo*)* @_Z3zedP3foo)
+!6 = !DIFile(filename: "/home/espindola/llvm/test.cc", directory: "/home/espindola/tmpfs/build")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9}
-!9 = !{!"0xf\00\000\0064\0064\000\000", null, null, !10} ; [ DW_TAG_pointer_type ]
-!10 = !{!"0x2\00foo\001\008\008\000\000\000", !32, null, null, !11, null, null, null} ; [ DW_TAG_class_type ] [foo] [line 1, size 8, align 8, offset 0] [def] [from ]
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_class_type, name: "foo", line: 1, size: 8, align: 8, file: !32, elements: !11)
 !11 = !{!12}
-!12 = !{!"0x2e\00bar\00bar\00_ZN3foo3barEv\002\000\000\000\006\00256\000\002", !6, !10, !13, null, null, null, i32 0, !16} ; [ DW_TAG_subprogram ]
-!13 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !14, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = !DISubprogram(name: "bar", linkageName: "_ZN3foo3barEv", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !6, scope: !10, type: !13)
+!13 = !DISubroutineType(types: !14)
 !14 = !{null, !15}
-!15 = !{!"0xf\00\000\0064\0064\000\0064", i32 0, null, !10} ; [ DW_TAG_pointer_type ]
-!16 = !{!17}
-!17 = !{!"0x24"}                      ; [ DW_TAG_base_type ]
-!18 = !{!19}
-!19 = !{!"0x24"}                      ; [ DW_TAG_base_type ]
-!20 = !{!"0x2e\00bar\00bar\00_ZN3foo3barEv\002\000\001\000\006\00256\000\002", !6, null, !13, null, void (%struct.foo*)* @_ZN3foo3barEv, null, !12, null} ; [ DW_TAG_subprogram ] [line 2] [def] [bar]
-!23 = !{!"0x101\00x\0016777220\000", !5, !6, !9} ; [ DW_TAG_arg_variable ]
-!24 = !MDLocation(line: 4, column: 15, scope: !5)
-!25 = !MDLocation(line: 4, column: 20, scope: !26)
-!26 = !{!"0xb\004\0018\000", !6, !5} ; [ DW_TAG_lexical_block ]
-!27 = !MDLocation(line: 4, column: 30, scope: !26)
-!28 = !{!"0x101\00this\0016777218\0064", !20, !6, !15} ; [ DW_TAG_arg_variable ]
-!29 = !MDLocation(line: 2, column: 8, scope: !20)
-!30 = !MDLocation(line: 2, column: 15, scope: !31)
-!31 = !{!"0xb\002\0014\001", !6, !20} ; [ DW_TAG_lexical_block ]
-!32 = !{!"/home/espindola/llvm/test.cc", !"/home/espindola/tmpfs/build"}
-!33 = !{i32 1, !"Debug Info Version", i32 2}
+!15 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, baseType: !10)
+!20 = !DISubprogram(name: "bar", linkageName: "_ZN3foo3barEv", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !6, scope: null, type: !13, function: void (%struct.foo*)* @_ZN3foo3barEv, declaration: !12)
+!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 4, arg: 1, scope: !5, file: !6, type: !9)
+!24 = !DILocation(line: 4, column: 15, scope: !5)
+!25 = !DILocation(line: 4, column: 20, scope: !26)
+!26 = distinct !DILexicalBlock(line: 4, column: 18, file: !6, scope: !5)
+!27 = !DILocation(line: 4, column: 30, scope: !26)
+!28 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 2, arg: 1, flags: DIFlagArtificial, scope: !20, file: !6, type: !15)
+!29 = !DILocation(line: 2, column: 8, scope: !20)
+!30 = !DILocation(line: 2, column: 15, scope: !31)
+!31 = distinct !DILexicalBlock(line: 2, column: 14, file: !6, scope: !20)
+!32 = !DIFile(filename: "/home/espindola/llvm/test.cc", directory: "/home/espindola/tmpfs/build")
+!33 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/pr12831.ll b/test/DebugInfo/X86/pr12831.ll
index 5adaeaf7d31a..98b9ce488603 100644
--- a/test/DebugInfo/X86/pr12831.ll
+++ b/test/DebugInfo/X86/pr12831.ll
@@ -20,14 +20,14 @@ entry:
   %agg.tmp4 = alloca %class.function, align 1
   %agg.tmp5 = alloca %class.anon.0, align 1
   store %class.BPLFunctionWriter* %this, %class.BPLFunctionWriter** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.BPLFunctionWriter** %this.addr, metadata !133, metadata !{!"0x102"}), !dbg !135
-  %this1 = load %class.BPLFunctionWriter** %this.addr
-  %MW = getelementptr inbounds %class.BPLFunctionWriter* %this1, i32 0, i32 0, !dbg !136
-  %0 = load %struct.BPLModuleWriter** %MW, align 8, !dbg !136
+  call void @llvm.dbg.declare(metadata %class.BPLFunctionWriter** %this.addr, metadata !133, metadata !DIExpression()), !dbg !135
+  %this1 = load %class.BPLFunctionWriter*, %class.BPLFunctionWriter** %this.addr
+  %MW = getelementptr inbounds %class.BPLFunctionWriter, %class.BPLFunctionWriter* %this1, i32 0, i32 0, !dbg !136
+  %0 = load %struct.BPLModuleWriter*, %struct.BPLModuleWriter** %MW, align 8, !dbg !136
   call void @"_ZN8functionIFvvEEC1IZN17BPLFunctionWriter9writeExprEvE3$_0EET_"(%class.function* %agg.tmp), !dbg !136
   call void @_ZN15BPLModuleWriter14writeIntrinsicE8functionIFvvEE(%struct.BPLModuleWriter* %0), !dbg !136
-  %MW3 = getelementptr inbounds %class.BPLFunctionWriter* %this1, i32 0, i32 0, !dbg !138
-  %1 = load %struct.BPLModuleWriter** %MW3, align 8, !dbg !138
+  %MW3 = getelementptr inbounds %class.BPLFunctionWriter, %class.BPLFunctionWriter* %this1, i32 0, i32 0, !dbg !138
+  %1 = load %struct.BPLModuleWriter*, %struct.BPLModuleWriter** %MW3, align 8, !dbg !138
   call void @"_ZN8functionIFvvEEC1IZN17BPLFunctionWriter9writeExprEvE3$_1_0EET_"(%class.function* %agg.tmp4), !dbg !138
   call void @_ZN15BPLModuleWriter14writeIntrinsicE8functionIFvvEE(%struct.BPLModuleWriter* %1), !dbg !138
   ret void, !dbg !139
@@ -42,9 +42,9 @@ entry:
   %this.addr = alloca %class.function*, align 8
   %__f = alloca %class.anon.0, align 1
   store %class.function* %this, %class.function** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.function** %this.addr, metadata !140, metadata !{!"0x102"}), !dbg !142
-  call void @llvm.dbg.declare(metadata %class.anon.0* %__f, metadata !143, metadata !{!"0x102"}), !dbg !144
-  %this1 = load %class.function** %this.addr
+  call void @llvm.dbg.declare(metadata %class.function** %this.addr, metadata !140, metadata !DIExpression()), !dbg !142
+  call void @llvm.dbg.declare(metadata %class.anon.0* %__f, metadata !143, metadata !DIExpression()), !dbg !144
+  %this1 = load %class.function*, %class.function** %this.addr
   call void @"_ZN13_Base_manager21_M_not_empty_functionIZN17BPLFunctionWriter9writeExprEvE3$_1_0EEvRKT_"(%class.anon.0* %__f), !dbg !145
   ret void, !dbg !147
 }
@@ -61,9 +61,9 @@ entry:
   %this.addr = alloca %class.function*, align 8
   %__f = alloca %class.anon, align 1
   store %class.function* %this, %class.function** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.function** %this.addr, metadata !150, metadata !{!"0x102"}), !dbg !151
-  call void @llvm.dbg.declare(metadata %class.anon* %__f, metadata !152, metadata !{!"0x102"}), !dbg !153
-  %this1 = load %class.function** %this.addr
+  call void @llvm.dbg.declare(metadata %class.function** %this.addr, metadata !150, metadata !DIExpression()), !dbg !151
+  call void @llvm.dbg.declare(metadata %class.anon* %__f, metadata !152, metadata !DIExpression()), !dbg !153
+  %this1 = load %class.function*, %class.function** %this.addr
   call void @"_ZN13_Base_manager21_M_not_empty_functionIZN17BPLFunctionWriter9writeExprEvE3$_0EEvRKT_"(%class.anon* %__f), !dbg !154
   ret void, !dbg !156
 }
@@ -78,163 +78,133 @@ entry:
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!162}
 
-!0 = !{!"0x11\004\00clang version 3.2 \000\00\000\00\000", !161, !1, !1, !3, !128, null} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.2 ", isOptimized: false, emissionKind: 0, file: !161, enums: !1, retainedTypes: !1, subprograms: !3, globals: !128)
 !1 = !{}
 !3 = !{!5, !106, !107, !126, !127}
-!5 = !{!"0x2e\00writeExpr\00writeExpr\00_ZN17BPLFunctionWriter9writeExprEv\0019\000\001\000\006\00256\000\0019", !6, null, !7, null, void (%class.BPLFunctionWriter*)* @_ZN17BPLFunctionWriter9writeExprEv, null, !103, !1} ; [ DW_TAG_subprogram ]
-!6 = !{!"0x29", !160} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "writeExpr", linkageName: "_ZN17BPLFunctionWriter9writeExprEv", line: 19, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 19, file: !6, scope: null, type: !7, function: void (%class.BPLFunctionWriter*)* @_ZN17BPLFunctionWriter9writeExprEv, declaration: !103, variables: !1)
+!6 = !DIFile(filename: "BPLFunctionWriter2.ii", directory: "/home/peter/crashdelta")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9}
-!9 = !{!"0xf\00\000\0064\0064\000\0064", i32 0, null, !10} ; [ DW_TAG_pointer_type ]
-!10 = !{!"0x2\00BPLFunctionWriter\0015\0064\0064\000\000\000", !160, null, null, !11, null, null, null} ; [ DW_TAG_class_type ] [BPLFunctionWriter] [line 15, size 64, align 64, offset 0] [def] [from ]
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_class_type, name: "BPLFunctionWriter", line: 15, size: 64, align: 64, file: !160, elements: !11)
 !11 = !{!12, !103}
-!12 = !{!"0xd\00MW\0016\0064\0064\000\001", !160, !10, !13} ; [ DW_TAG_member ]
-!13 = !{!"0xf\00\000\0064\0064\000\000", null, null, !14} ; [ DW_TAG_pointer_type ]
-!14 = !{!"0x2\00BPLModuleWriter\0012\008\008\000\000\000", !160, null, null, !15, null, null, null} ; [ DW_TAG_class_type ] [BPLModuleWriter] [line 12, size 8, align 8, offset 0] [def] [from ]
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "MW", line: 16, size: 64, align: 64, flags: DIFlagPrivate, file: !160, scope: !10, baseType: !13)
+!13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !14)
+!14 = !DICompositeType(tag: DW_TAG_class_type, name: "BPLModuleWriter", line: 12, size: 8, align: 8, file: !160, elements: !15)
 !15 = !{!16}
-!16 = !{!"0x2e\00writeIntrinsic\00writeIntrinsic\00_ZN15BPLModuleWriter14writeIntrinsicE8functionIFvvEE\0013\000\000\000\006\00256\000\0013", !6, !14, !17, null, null, null, i32 0, !101} ; [ DW_TAG_subprogram ]
-!17 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !18, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!16 = !DISubprogram(name: "writeIntrinsic", linkageName: "_ZN15BPLModuleWriter14writeIntrinsicE8functionIFvvEE", line: 13, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 13, file: !6, scope: !14, type: !17)
+!17 = !DISubroutineType(types: !18)
 !18 = !{null, !19, !20}
-!19 = !{!"0xf\00\000\0064\0064\000\0064", i32 0, null, !14} ; [ DW_TAG_pointer_type ]
-!20 = !{!"0x2\00function<void ()>\006\008\008\000\000\000", !160, null, null, !21, null, !97, null} ; [ DW_TAG_class_type ] [function<void ()>] [line 6, size 8, align 8, offset 0] [def] [from ]
+!19 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, baseType: !14)
+!20 = !DICompositeType(tag: DW_TAG_class_type, name: "function<void ()>", line: 6, size: 8, align: 8, file: !160, elements: !21, templateParams: !97)
 !21 = !{!22, !51, !58, !86, !92}
-!22 = !{!"0x2e\00function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >\00function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >\00\008\000\000\000\006\00256\000\008", !6, !20, !23, null, null, !47, i32 0, !49} ; [ DW_TAG_subprogram ]
-!23 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !24, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!22 = !DISubprogram(name: "function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", line: 8, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 8, file: !6, scope: !20, type: !23, templateParams: !47)
+!23 = !DISubroutineType(types: !24)
 !24 = !{null, !25, !26}
-!25 = !{!"0xf\00\000\0064\0064\000\0064", i32 0, null, !20} ; [ DW_TAG_pointer_type ]
-!26 = !{!"0x2\00\0020\008\008\000\000\000", !160, !5, null, !27, null, null, null} ; [ DW_TAG_class_type ] [line 20, size 8, align 8, offset 0] [def] [from ]
+!25 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, baseType: !20)
+!26 = !DICompositeType(tag: DW_TAG_class_type, line: 20, size: 8, align: 8, file: !160, scope: !5, elements: !27)
 !27 = !{!28, !35, !41}
-!28 = !{!"0x2e\00operator()\00operator()\00\0020\000\000\000\006\00256\000\0020", !6, !26, !29, null, null, null, i32 0, !33} ; [ DW_TAG_subprogram ]
-!29 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !30, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!28 = !DISubprogram(name: "operator()", line: 20, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 20, file: !6, scope: !26, type: !29)
+!29 = !DISubroutineType(types: !30)
 !30 = !{null, !31}
-!31 = !{!"0xf\00\000\0064\0064\000\0064", i32 0, null, !32} ; [ DW_TAG_pointer_type ]
-!32 = !{!"0x26\00\000\000\000\000\000", null, null, !26} ; [ DW_TAG_const_type ]
-!33 = !{!34}
-!34 = !{!"0x24"}                      ; [ DW_TAG_base_type ]
-!35 = !{!"0x2e\00~\00~\00\0020\000\000\000\006\00320\000\0020", !6, !26, !36, null, null, null, i32 0, !39} ; [ DW_TAG_subprogram ]
-!36 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !37, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
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+!131 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !132)
+!132 = !DIBasicType(tag: DW_TAG_base_type, name: "bool", size: 8, align: 8, encoding: DW_ATE_boolean)
+!133 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 19, arg: 1, flags: DIFlagArtificial, scope: !5, file: !6, type: !134)
+!134 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !10)
+!135 = !DILocation(line: 19, column: 39, scope: !5)
+!136 = !DILocation(line: 20, column: 17, scope: !137)
+!137 = distinct !DILexicalBlock(line: 19, column: 51, file: !6, scope: !5)
+!138 = !DILocation(line: 23, column: 17, scope: !137)
+!139 = !DILocation(line: 26, column: 15, scope: !137)
+!140 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 8, arg: 1, flags: DIFlagArtificial, scope: !106, file: !6, type: !141)
+!141 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !20)
+!142 = !DILocation(line: 8, column: 45, scope: !106)
+!143 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "__f", line: 8, arg: 2, scope: !106, file: !6, type: !61)
+!144 = !DILocation(line: 8, column: 63, scope: !106)
+!145 = !DILocation(line: 9, column: 9, scope: !146)
+!146 = distinct !DILexicalBlock(line: 8, column: 81, file: !6, scope: !106)
+!147 = !DILocation(line: 10, column: 13, scope: !146)
+!148 = !DILocation(line: 4, column: 5, scope: !149)
+!149 = distinct !DILexicalBlock(line: 3, column: 105, file: !6, scope: !107)
+!150 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 8, arg: 1, flags: DIFlagArtificial, scope: !126, file: !6, type: !141)
+!151 = !DILocation(line: 8, column: 45, scope: !126)
+!152 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "__f", line: 8, arg: 2, scope: !126, file: !6, type: !26)
+!153 = !DILocation(line: 8, column: 63, scope: !126)
+!154 = !DILocation(line: 9, column: 9, scope: !155)
+!155 = distinct !DILexicalBlock(line: 8, column: 81, file: !6, scope: !126)
+!156 = !DILocation(line: 10, column: 13, scope: !155)
+!157 = !DILocation(line: 4, column: 5, scope: !158)
+!158 = distinct !DILexicalBlock(line: 3, column: 105, file: !6, scope: !127)
+!159 = !DIFile(filename: "BPLFunctionWriter.cpp", directory: "/home/peter/crashdelta")
+!160 = !DIFile(filename: "BPLFunctionWriter2.ii", directory: "/home/peter/crashdelta")
+!161 = !DIFile(filename: "BPLFunctionWriter.cpp", directory: "/home/peter/crashdelta")
+!162 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/pr13303.ll b/test/DebugInfo/X86/pr13303.ll
index 2ca697a3e45d..df31a7994469 100644
--- a/test/DebugInfo/X86/pr13303.ll
+++ b/test/DebugInfo/X86/pr13303.ll
@@ -15,15 +15,15 @@ entry:
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!13}
 
-!0 = !{!"0x11\0012\00clang version 3.2 (trunk 160143)\000\00\000\00\000", !12, !1, !1, !3, !1,  !1} ; [ DW_TAG_compile_unit ] [/home/probinson/PR13303.c] [DW_LANG_C99]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.2 (trunk 160143)", isOptimized: false, emissionKind: 0, file: !12, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00main\00main\00\001\000\001\000\006\000\000\001", !12, !6, !7, null, i32 ()* @main, null, null, !1} ; [ DW_TAG_subprogram ] [line 1] [def] [main]
-!6 = !{!"0x29", !12} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "main", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !12, scope: !6, type: !7, function: i32 ()* @main, variables: !1)
+!6 = !DIFile(filename: "PR13303.c", directory: "/home/probinson")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !MDLocation(line: 1, column: 14, scope: !11)
-!11 = !{!"0xb\001\0012\000", !12, !5} ; [ DW_TAG_lexical_block ] [/home/probinson/PR13303.c]
-!12 = !{!"PR13303.c", !"/home/probinson"}
-!13 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DILocation(line: 1, column: 14, scope: !11)
+!11 = distinct !DILexicalBlock(line: 1, column: 12, file: !12, scope: !5)
+!12 = !DIFile(filename: "PR13303.c", directory: "/home/probinson")
+!13 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/pr19307.ll b/test/DebugInfo/X86/pr19307.ll
index c05dc475d63b..e04131fe322c 100644
--- a/test/DebugInfo/X86/pr19307.ll
+++ b/test/DebugInfo/X86/pr19307.ll
@@ -40,29 +40,29 @@ entry:
   %offset.addr = alloca i64*, align 8
   %limit.addr = alloca i64*, align 8
   store i64* %offset, i64** %offset.addr, align 8
-  call void @llvm.dbg.declare(metadata i64** %offset.addr, metadata !45, metadata !{!"0x102"}), !dbg !46
+  call void @llvm.dbg.declare(metadata i64** %offset.addr, metadata !45, metadata !DIExpression()), !dbg !46
   store i64* %limit, i64** %limit.addr, align 8
-  call void @llvm.dbg.declare(metadata i64** %limit.addr, metadata !47, metadata !{!"0x102"}), !dbg !46
-  call void @llvm.dbg.declare(metadata %"class.std::basic_string"* %range, metadata !48, metadata !{!"0x102"}), !dbg !49
-  %call = call i32 @_ZNKSs7compareEmmPKc(%"class.std::basic_string"* %range, i64 0, i64 6, i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0)), !dbg !50
+  call void @llvm.dbg.declare(metadata i64** %limit.addr, metadata !47, metadata !DIExpression()), !dbg !46
+  call void @llvm.dbg.declare(metadata %"class.std::basic_string"* %range, metadata !48, metadata !DIExpression(DW_OP_deref)), !dbg !49
+  %call = call i32 @_ZNKSs7compareEmmPKc(%"class.std::basic_string"* %range, i64 0, i64 6, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0)), !dbg !50
   %cmp = icmp ne i32 %call, 0, !dbg !50
   br i1 %cmp, label %if.then, label %lor.lhs.false, !dbg !50
 
 lor.lhs.false:                                    ; preds = %entry
   %call1 = call i8* @_ZNSsixEm(%"class.std::basic_string"* %range, i64 6), !dbg !52
-  %0 = load i8* %call1, !dbg !52
+  %0 = load i8, i8* %call1, !dbg !52
   %conv = sext i8 %0 to i32, !dbg !52
   %cmp2 = icmp eq i32 %conv, 45, !dbg !52
   br i1 %cmp2, label %if.then, label %if.end, !dbg !52
 
 if.then:                                          ; preds = %lor.lhs.false, %entry
-  %1 = load i64** %offset.addr, align 8, !dbg !54
+  %1 = load i64*, i64** %offset.addr, align 8, !dbg !54
   store i64 1, i64* %1, align 8, !dbg !54
   br label %if.end, !dbg !54
 
 if.end:                                           ; preds = %if.then, %lor.lhs.false
   %call3 = call %"class.std::basic_string"* @_ZNSs5eraseEmm(%"class.std::basic_string"* %range, i64 0, i64 6), !dbg !55
-  %2 = load i64** %limit.addr, align 8, !dbg !56
+  %2 = load i64*, i64** %limit.addr, align 8, !dbg !56
   store i64 2, i64* %2, align 8, !dbg !56
   ret void, !dbg !57
 }
@@ -84,62 +84,62 @@ attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n
 !llvm.module.flags = !{!42, !43}
 !llvm.ident = !{!44}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 (209308)\000\00\000\00\001", !1, !2, !3, !12, !2, !21} ; [ DW_TAG_compile_unit ] [/llvm_cmake_gcc/pr19307.cc] [DW_LANG_C_plus_plus]
-!1 = !{!"pr19307.cc", !"/llvm_cmake_gcc"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 (209308)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !12, globals: !2, imports: !21)
+!1 = !DIFile(filename: "pr19307.cc", directory: "/llvm_cmake_gcc")
 !2 = !{}
 !3 = !{!4, !6, !8}
-!4 = !{!"0x13\00\0083\000\000\000\004\000", !5, null, null, null, null, null, !"_ZTS11__mbstate_t"} ; [ DW_TAG_structure_type ] [line 83, size 0, align 0, offset 0] [decl] [from ]
-!5 = !{!"/usr/include/wchar.h", !"/llvm_cmake_gcc"}
-!6 = !{!"0x13\00lconv\0054\000\000\000\004\000", !7, null, null, null, null, null, !"_ZTS5lconv"} ; [ DW_TAG_structure_type ] [lconv] [line 54, size 0, align 0, offset 0] [decl] [from ]
-!7 = !{!"/usr/include/locale.h", !"/llvm_cmake_gcc"}
-!8 = !{!"0x2\00basic_string<char, std::char_traits<char>, std::allocator<char> >\001134\000\000\000\004\000", !9, !10, null, null, null, null, !"_ZTSSs"} ; [ DW_TAG_class_type ] [basic_string<char, std::char_traits<char>, std::allocator<char> >] [line 1134, size 0, align 0, offset 0] [decl] [from ]
-!9 = !{!"/usr/lib/gcc/x86_64-linux-gnu/4.6/../../../../include/c++/4.6/bits/basic_string.tcc", !"/llvm_cmake_gcc"}
-!10 = !{!"0x39\00std\00153", !11, null} ; [ DW_TAG_namespace ] [std] [line 153]
-!11 = !{!"/usr/lib/gcc/x86_64-linux-gnu/4.6/../../../../include/c++/4.6/x86_64-linux-gnu/bits/c++config.h", !"/llvm_cmake_gcc"}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, line: 83, flags: DIFlagFwdDecl, file: !5, identifier: "_ZTS11__mbstate_t")
+!5 = !DIFile(filename: "/usr/include/wchar.h", directory: "/llvm_cmake_gcc")
+!6 = !DICompositeType(tag: DW_TAG_structure_type, name: "lconv", line: 54, flags: DIFlagFwdDecl, file: !7, identifier: "_ZTS5lconv")
+!7 = !DIFile(filename: "/usr/include/locale.h", directory: "/llvm_cmake_gcc")
+!8 = !DICompositeType(tag: DW_TAG_class_type, name: "basic_string<char, std::char_traits<char>, std::allocator<char> >", line: 1134, flags: DIFlagFwdDecl, file: !9, scope: !10, identifier: "_ZTSSs")
+!9 = !DIFile(filename: "/usr/lib/gcc/x86_64-linux-gnu/4.6/../../../../include/c++/4.6/bits/basic_string.tcc", directory: "/llvm_cmake_gcc")
+!10 = !DINamespace(name: "std", line: 153, file: !11, scope: null)
+!11 = !DIFile(filename: "/usr/lib/gcc/x86_64-linux-gnu/4.6/../../../../include/c++/4.6/x86_64-linux-gnu/bits/c++config.h", directory: "/llvm_cmake_gcc")
 !12 = !{!13}
-!13 = !{!"0x2e\00parse_range\00parse_range\00_Z11parse_rangeRyS_Ss\003\000\001\000\006\00256\000\004", !1, !14, !15, null, void (i64*, i64*, %"class.std::basic_string"*)* @_Z11parse_rangeRyS_Ss, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 4] [parse_range]
-!14 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/llvm_cmake_gcc/pr19307.cc]
-!15 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DISubprogram(name: "parse_range", linkageName: "_Z11parse_rangeRyS_Ss", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !1, scope: !14, type: !15, function: void (i64*, i64*, %"class.std::basic_string"*)* @_Z11parse_rangeRyS_Ss, variables: !2)
+!14 = !DIFile(filename: "pr19307.cc", directory: "/llvm_cmake_gcc")
+!15 = !DISubroutineType(types: !16)
 !16 = !{null, !17, !17, !19}
-!17 = !{!"0x10\00\000\000\000\000\000", null, null, !18} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from long long unsigned int]
-!18 = !{!"0x24\00long long unsigned int\000\0064\0064\000\000\007", null, null} ; [ DW_TAG_base_type ] [long long unsigned int] [line 0, size 64, align 64, offset 0, enc DW_ATE_unsigned]
-!19 = !{!"0x16\00string\0065\000\000\000\000", !20, !10, !"_ZTSSs"} ; [ DW_TAG_typedef ] [string] [line 65, size 0, align 0, offset 0] [from _ZTSSs]
-!20 = !{!"/usr/lib/gcc/x86_64-linux-gnu/4.6/../../../../include/c++/4.6/bits/stringfwd.h", !"/llvm_cmake_gcc"}
+!17 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !18)
+!18 = !DIBasicType(tag: DW_TAG_base_type, name: "long long unsigned int", size: 64, align: 64, encoding: DW_ATE_unsigned)
+!19 = !DIDerivedType(tag: DW_TAG_typedef, name: "string", line: 65, file: !20, scope: !10, baseType: !"_ZTSSs")
+!20 = !DIFile(filename: "/usr/lib/gcc/x86_64-linux-gnu/4.6/../../../../include/c++/4.6/bits/stringfwd.h", directory: "/llvm_cmake_gcc")
 !21 = !{!22, !26, !29, !33, !38, !41}
-!22 = !{!"0x3a\0057\00", !23, !25} ; [ DW_TAG_imported_module ]
-!23 = !{!"0x39\00__gnu_debug\0055", !24, null} ; [ DW_TAG_namespace ] [__gnu_debug] [line 55]
-!24 = !{!"/usr/lib/gcc/x86_64-linux-gnu/4.6/../../../../include/c++/4.6/debug/debug.h", !"/llvm_cmake_gcc"}
-!25 = !{!"0x39\00__debug\0049", !24, !10} ; [ DW_TAG_namespace ] [__debug] [line 49]
-!26 = !{!"0x8\0066\00", !10, !27} ; [ DW_TAG_imported_declaration ]
-!27 = !{!"0x16\00mbstate_t\00106\000\000\000\000", !5, null, !28} ; [ DW_TAG_typedef ] [mbstate_t] [line 106, size 0, align 0, offset 0] [from __mbstate_t]
-!28 = !{!"0x16\00__mbstate_t\0095\000\000\000\000", !5, null, !"_ZTS11__mbstate_t"} ; [ DW_TAG_typedef ] [__mbstate_t] [line 95, size 0, align 0, offset 0] [from _ZTS11__mbstate_t]
-!29 = !{!"0x8\00141\00", !10, !30} ; [ DW_TAG_imported_declaration ]
-!30 = !{!"0x16\00wint_t\00141\000\000\000\000", !31, null, !32} ; [ DW_TAG_typedef ] [wint_t] [line 141, size 0, align 0, offset 0] [from unsigned int]
-!31 = !{!"/llvm_cmake_gcc/bin/../lib/clang/3.5.0/include/stddef.h", !"/llvm_cmake_gcc"}
-!32 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, null} ; [ DW_TAG_base_type ] [unsigned int] [line 0, size 32, align 32, offset 0, enc DW_ATE_unsigned]
-!33 = !{!"0x8\0042\00", !34, !36} ; [ DW_TAG_imported_declaration ]
-!34 = !{!"0x39\00__gnu_cxx\0069", !35, null} ; [ DW_TAG_namespace ] [__gnu_cxx] [line 69]
-!35 = !{!"/usr/lib/gcc/x86_64-linux-gnu/4.6/../../../../include/c++/4.6/bits/cpp_type_traits.h", !"/llvm_cmake_gcc"}
-!36 = !{!"0x16\00size_t\00155\000\000\000\000", !11, !10, !37} ; [ DW_TAG_typedef ] [size_t] [line 155, size 0, align 0, offset 0] [from long unsigned int]
-!37 = !{!"0x24\00long unsigned int\000\0064\0064\000\000\007", null, null} ; [ DW_TAG_base_type ] [long unsigned int] [line 0, size 64, align 64, offset 0, enc DW_ATE_unsigned]
-!38 = !{!"0x8\0043\00", !34, !39} ; [ DW_TAG_imported_declaration ]
-!39 = !{!"0x16\00ptrdiff_t\00156\000\000\000\000", !11, !10, !40} ; [ DW_TAG_typedef ] [ptrdiff_t] [line 156, size 0, align 0, offset 0] [from long int]
-!40 = !{!"0x24\00long int\000\0064\0064\000\000\005", null, null} ; [ DW_TAG_base_type ] [long int] [line 0, size 64, align 64, offset 0, enc DW_ATE_signed]
-!41 = !{!"0x8\0055\00", !10, !"_ZTS5lconv"} ; [ DW_TAG_imported_declaration ]
+!22 = !DIImportedEntity(tag: DW_TAG_imported_module, line: 57, scope: !23, entity: !25)
+!23 = !DINamespace(name: "__gnu_debug", line: 55, file: !24, scope: null)
+!24 = !DIFile(filename: "/usr/lib/gcc/x86_64-linux-gnu/4.6/../../../../include/c++/4.6/debug/debug.h", directory: "/llvm_cmake_gcc")
+!25 = !DINamespace(name: "__debug", line: 49, file: !24, scope: !10)
+!26 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 66, scope: !10, entity: !27)
+!27 = !DIDerivedType(tag: DW_TAG_typedef, name: "mbstate_t", line: 106, file: !5, baseType: !28)
+!28 = !DIDerivedType(tag: DW_TAG_typedef, name: "__mbstate_t", line: 95, file: !5, baseType: !"_ZTS11__mbstate_t")
+!29 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 141, scope: !10, entity: !30)
+!30 = !DIDerivedType(tag: DW_TAG_typedef, name: "wint_t", line: 141, file: !31, baseType: !32)
+!31 = !DIFile(filename: "/llvm_cmake_gcc/bin/../lib/clang/3.5.0/include/stddef.h", directory: "/llvm_cmake_gcc")
+!32 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!33 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 42, scope: !34, entity: !36)
+!34 = !DINamespace(name: "__gnu_cxx", line: 69, file: !35, scope: null)
+!35 = !DIFile(filename: "/usr/lib/gcc/x86_64-linux-gnu/4.6/../../../../include/c++/4.6/bits/cpp_type_traits.h", directory: "/llvm_cmake_gcc")
+!36 = !DIDerivedType(tag: DW_TAG_typedef, name: "size_t", line: 155, file: !11, scope: !10, baseType: !37)
+!37 = !DIBasicType(tag: DW_TAG_base_type, name: "long unsigned int", size: 64, align: 64, encoding: DW_ATE_unsigned)
+!38 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 43, scope: !34, entity: !39)
+!39 = !DIDerivedType(tag: DW_TAG_typedef, name: "ptrdiff_t", line: 156, file: !11, scope: !10, baseType: !40)
+!40 = !DIBasicType(tag: DW_TAG_base_type, name: "long int", size: 64, align: 64, encoding: DW_ATE_signed)
+!41 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 55, scope: !10, entity: !"_ZTS5lconv")
 !42 = !{i32 2, !"Dwarf Version", i32 4}
-!43 = !{i32 2, !"Debug Info Version", i32 2}
+!43 = !{i32 2, !"Debug Info Version", i32 3}
 !44 = !{!"clang version 3.5.0 (209308)"}
-!45 = !{!"0x101\00offset\0016777219\000", !13, !14, !17} ; [ DW_TAG_arg_variable ] [offset] [line 3]
-!46 = !MDLocation(line: 3, scope: !13)
-!47 = !{!"0x101\00limit\0033554435\000", !13, !14, !17} ; [ DW_TAG_arg_variable ] [limit] [line 3]
-!48 = !{!"0x101\00range\0050331652\008192", !13, !14, !19} ; [ DW_TAG_arg_variable ] [range] [line 4]
-!49 = !MDLocation(line: 4, scope: !13)
-!50 = !MDLocation(line: 5, scope: !51)
-!51 = !{!"0xb\005\000\000", !1, !13} ; [ DW_TAG_lexical_block ] [/llvm_cmake_gcc/pr19307.cc]
-!52 = !MDLocation(line: 5, scope: !53)
-!53 = !{!"0xb\005\000\001", !1, !51} ; [ DW_TAG_lexical_block ] [/llvm_cmake_gcc/pr19307.cc]
-!54 = !MDLocation(line: 6, scope: !51)
-!55 = !MDLocation(line: 7, scope: !13)
-!56 = !MDLocation(line: 8, scope: !13)
-!57 = !MDLocation(line: 9, scope: !13)
+!45 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "offset", line: 3, arg: 1, scope: !13, file: !14, type: !17)
+!46 = !DILocation(line: 3, scope: !13)
+!47 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "limit", line: 3, arg: 2, scope: !13, file: !14, type: !17)
+!48 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "range", line: 4, arg: 3, scope: !13, file: !14, type: !19)
+!49 = !DILocation(line: 4, scope: !13)
+!50 = !DILocation(line: 5, scope: !51)
+!51 = distinct !DILexicalBlock(line: 5, column: 0, file: !1, scope: !13)
+!52 = !DILocation(line: 5, scope: !53)
+!53 = distinct !DILexicalBlock(line: 5, column: 0, file: !1, scope: !51)
+!54 = !DILocation(line: 6, scope: !51)
+!55 = !DILocation(line: 7, scope: !13)
+!56 = !DILocation(line: 8, scope: !13)
+!57 = !DILocation(line: 9, scope: !13)
 
diff --git a/test/DebugInfo/X86/processes-relocations.ll b/test/DebugInfo/X86/processes-relocations.ll
index b60ffdfbe213..bb49e6bef784 100644
--- a/test/DebugInfo/X86/processes-relocations.ll
+++ b/test/DebugInfo/X86/processes-relocations.ll
@@ -13,9 +13,9 @@
 !llvm.module.flags = !{!3, !4}
 !llvm.ident = !{!5}
 
-!0 = !{i32 786449, !1, i32 12, !"clang version 3.6.0 ", i1 false, !"", i32 0, !2, !2, !2, !2, !2, !"", i32 1} ; [ DW_TAG_compile_unit ] [/a/empty.c] [DW_LANG_C99]
-!1 = !{!"empty.c", !"/a"}
+!0 = !DICompileUnit(file: !1, language: DW_LANG_C99, producer: "clang version 3.6.0 ", isOptimized: false, enums: !2, retainedTypes: !2, subprograms: !2, globals: !2, imports: !2, emissionKind: 1)
+!1 = !DIFile(filename: "empty.c", directory: "/a")
 !2 = !{}
 !3 = !{i32 2, !"Dwarf Version", i32 4}
-!4 = !{i32 2, !"Debug Info Version", i32 2}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
 !5 = !{!"clang version 3.6.0 "}
diff --git a/test/DebugInfo/X86/prologue-stack.ll b/test/DebugInfo/X86/prologue-stack.ll
index 1cc872ab4184..cd362e380951 100644
--- a/test/DebugInfo/X86/prologue-stack.ll
+++ b/test/DebugInfo/X86/prologue-stack.ll
@@ -21,16 +21,16 @@ declare i32 @callme(i32)
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!14}
 
-!0 = !{!"0x11\0012\00clang version 3.2 (trunk 164980) (llvm/trunk 164979)\000\00\000\00\000", !13, !1, !1, !3, !1,  !1} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/bar.c] [DW_LANG_C99]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.2 (trunk 164980) (llvm/trunk 164979)", isOptimized: false, emissionKind: 0, file: !13, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00isel_line_test2\00isel_line_test2\00\003\000\001\000\006\000\000\004", !13, !6, !7, null, i32 ()* @isel_line_test2, null, null, !1} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 4] [isel_line_test2]
-!6 = !{!"0x29", !13} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "isel_line_test2", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 4, file: !13, scope: !6, type: !7, function: i32 ()* @isel_line_test2, variables: !1)
+!6 = !DIFile(filename: "bar.c", directory: "/usr/local/google/home/echristo/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !MDLocation(line: 5, column: 3, scope: !11)
-!11 = !{!"0xb\004\001\000", !13, !5} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/bar.c]
-!12 = !MDLocation(line: 6, column: 3, scope: !11)
-!13 = !{!"bar.c", !"/usr/local/google/home/echristo/tmp"}
-!14 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DILocation(line: 5, column: 3, scope: !11)
+!11 = distinct !DILexicalBlock(line: 4, column: 1, file: !13, scope: !5)
+!12 = !DILocation(line: 6, column: 3, scope: !11)
+!13 = !DIFile(filename: "bar.c", directory: "/usr/local/google/home/echristo/tmp")
+!14 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/recursive_inlining.ll b/test/DebugInfo/X86/recursive_inlining.ll
index 6cd935ce061a..7825646c7c8d 100644
--- a/test/DebugInfo/X86/recursive_inlining.ll
+++ b/test/DebugInfo/X86/recursive_inlining.ll
@@ -94,11 +94,11 @@
 define void @_Z3fn6v() #0 {
 entry:
   tail call void @_Z3fn8v() #3, !dbg !31
-  %0 = load %struct.C** @x, align 8, !dbg !32, !tbaa !33
-  tail call void @llvm.dbg.value(metadata %struct.C* %0, i64 0, metadata !37, metadata !{!"0x102"}) #3, !dbg !38
+  %0 = load %struct.C*, %struct.C** @x, align 8, !dbg !32, !tbaa !33
+  tail call void @llvm.dbg.value(metadata %struct.C* %0, i64 0, metadata !37, metadata !DIExpression()) #3, !dbg !38
   tail call void @_Z3fn8v() #3, !dbg !39
-  %b.i = getelementptr inbounds %struct.C* %0, i64 0, i32 0, !dbg !40
-  %1 = load i32* %b.i, align 4, !dbg !40, !tbaa !42
+  %b.i = getelementptr inbounds %struct.C, %struct.C* %0, i64 0, i32 0, !dbg !40
+  %1 = load i32, i32* %b.i, align 4, !dbg !40, !tbaa !42
   %tobool.i = icmp eq i32 %1, 0, !dbg !40
   br i1 %tobool.i, label %_ZN1C5m_fn2Ev.exit, label %if.then.i, !dbg !40
 
@@ -116,10 +116,10 @@ declare void @_Z3fn8v() #1
 ; Function Attrs: nounwind
 define linkonce_odr void @_ZN1C5m_fn2Ev(%struct.C* nocapture readonly %this) #0 align 2 {
 entry:
-  tail call void @llvm.dbg.value(metadata %struct.C* %this, i64 0, metadata !24, metadata !{!"0x102"}), !dbg !49
+  tail call void @llvm.dbg.value(metadata %struct.C* %this, i64 0, metadata !24, metadata !DIExpression()), !dbg !49
   tail call void @_Z3fn8v() #3, !dbg !50
-  %b = getelementptr inbounds %struct.C* %this, i64 0, i32 0, !dbg !51
-  %0 = load i32* %b, align 4, !dbg !51, !tbaa !42
+  %b = getelementptr inbounds %struct.C, %struct.C* %this, i64 0, i32 0, !dbg !51
+  %0 = load i32, i32* %b, align 4, !dbg !51, !tbaa !42
   %tobool = icmp eq i32 %0, 0, !dbg !51
   br i1 %tobool, label %if.end, label %if.then, !dbg !51
 
@@ -129,11 +129,11 @@ if.then:                                          ; preds = %entry
 
 if.end:                                           ; preds = %entry, %if.then
   tail call void @_Z3fn8v() #3, !dbg !53
-  %1 = load %struct.C** @x, align 8, !dbg !56, !tbaa !33
-  tail call void @llvm.dbg.value(metadata %struct.C* %1, i64 0, metadata !57, metadata !{!"0x102"}) #3, !dbg !58
+  %1 = load %struct.C*, %struct.C** @x, align 8, !dbg !56, !tbaa !33
+  tail call void @llvm.dbg.value(metadata %struct.C* %1, i64 0, metadata !57, metadata !DIExpression()) #3, !dbg !58
   tail call void @_Z3fn8v() #3, !dbg !59
-  %b.i.i = getelementptr inbounds %struct.C* %1, i64 0, i32 0, !dbg !60
-  %2 = load i32* %b.i.i, align 4, !dbg !60, !tbaa !42
+  %b.i.i = getelementptr inbounds %struct.C, %struct.C* %1, i64 0, i32 0, !dbg !60
+  %2 = load i32, i32* %b.i.i, align 4, !dbg !60, !tbaa !42
   %tobool.i.i = icmp eq i32 %2, 0, !dbg !60
   br i1 %tobool.i.i, label %_Z3fn6v.exit, label %if.then.i.i, !dbg !60
 
@@ -153,11 +153,11 @@ entry:
 
 tailrecurse:                                      ; preds = %tailrecurse.backedge, %entry
   tail call void @_Z3fn8v() #3, !dbg !64
-  %0 = load %struct.C** @x, align 8, !dbg !66, !tbaa !33
-  tail call void @llvm.dbg.value(metadata %struct.C* %0, i64 0, metadata !67, metadata !{!"0x102"}) #3, !dbg !68
+  %0 = load %struct.C*, %struct.C** @x, align 8, !dbg !66, !tbaa !33
+  tail call void @llvm.dbg.value(metadata %struct.C* %0, i64 0, metadata !67, metadata !DIExpression()) #3, !dbg !68
   tail call void @_Z3fn8v() #3, !dbg !69
-  %b.i.i = getelementptr inbounds %struct.C* %0, i64 0, i32 0, !dbg !70
-  %1 = load i32* %b.i.i, align 4, !dbg !70, !tbaa !42
+  %b.i.i = getelementptr inbounds %struct.C, %struct.C* %0, i64 0, i32 0, !dbg !70
+  %1 = load i32, i32* %b.i.i, align 4, !dbg !70, !tbaa !42
   %tobool.i.i = icmp eq i32 %1, 0, !dbg !70
   br i1 %tobool.i.i, label %tailrecurse.backedge, label %if.then.i.i, !dbg !70
 
@@ -172,7 +172,7 @@ if.then.i.i:                                      ; preds = %tailrecurse
 ; Function Attrs: nounwind
 define void @_Z3fn4v() #0 {
 entry:
-  %0 = load %struct.C** @x, align 8, !dbg !72, !tbaa !33
+  %0 = load %struct.C*, %struct.C** @x, align 8, !dbg !72, !tbaa !33
   tail call void @_ZN1C5m_fn2Ev(%struct.C* %0), !dbg !72
   ret void, !dbg !72
 }
@@ -180,7 +180,7 @@ entry:
 ; Function Attrs: nounwind
 define void @_Z3fn5v() #0 {
 entry:
-  %0 = load %struct.C** @x, align 8, !dbg !73, !tbaa !33
+  %0 = load %struct.C*, %struct.C** @x, align 8, !dbg !73, !tbaa !33
   tail call void @_ZN1C5m_fn2Ev(%struct.C* %0), !dbg !73
   ret void, !dbg !73
 }
@@ -199,77 +199,77 @@ attributes #3 = { nounwind }
 !llvm.module.flags = !{!28, !29}
 !llvm.ident = !{!30}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 \001\00\000\00\001", !1, !2, !3, !13, !26, !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/blaikie/dev/scratch/missing_concrete_variable_on_darwin/reduce/<stdin>] [DW_LANG_C_plus_plus]
-!1 = !{!"<stdin>", !"/usr/local/google/home/blaikie/dev/scratch/missing_concrete_variable_on_darwin/reduce"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !13, globals: !26, imports: !2)
+!1 = !DIFile(filename: "<stdin>", directory: "/usr/local/google/home/blaikie/dev/scratch/missing_concrete_variable_on_darwin/reduce")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00C\005\0032\0032\000\000\000", !5, null, null, !6, null, null, !"_ZTS1C"} ; [ DW_TAG_structure_type ] [C] [line 5, size 32, align 32, offset 0] [def] [from ]
-!5 = !{!"recursive_inlining.cpp", !"/usr/local/google/home/blaikie/dev/scratch/missing_concrete_variable_on_darwin/reduce"}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "C", line: 5, size: 32, align: 32, file: !5, elements: !6, identifier: "_ZTS1C")
+!5 = !DIFile(filename: "recursive_inlining.cpp", directory: "/usr/local/google/home/blaikie/dev/scratch/missing_concrete_variable_on_darwin/reduce")
 !6 = !{!7, !9}
-!7 = !{!"0xd\00b\006\0032\0032\000\000", !5, !"_ZTS1C", !8} ; [ DW_TAG_member ] [b] [line 6, size 32, align 32, offset 0] [from int]
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x2e\00m_fn2\00m_fn2\00_ZN1C5m_fn2Ev\007\000\000\000\006\00256\001\007", !5, !"_ZTS1C", !10, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 7] [m_fn2]
-!10 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 6, size: 32, align: 32, file: !5, scope: !"_ZTS1C", baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DISubprogram(name: "m_fn2", linkageName: "_ZN1C5m_fn2Ev", line: 7, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 7, file: !5, scope: !"_ZTS1C", type: !10)
+!10 = !DISubroutineType(types: !11)
 !11 = !{null, !12}
-!12 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1C"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1C]
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1C")
 !13 = !{!14, !18, !19, !20, !21, !22}
-!14 = !{!"0x2e\00fn6\00fn6\00_Z3fn6v\0015\000\001\000\006\00256\001\0015", !5, !15, !16, null, void ()* @_Z3fn6v, null, null, !2} ; [ DW_TAG_subprogram ] [line 15] [def] [fn6]
-!15 = !{!"0x29", !5}         ; [ DW_TAG_file_type ] [/usr/local/google/home/blaikie/dev/scratch/missing_concrete_variable_on_darwin/reduce/recursive_inlining.cpp]
-!16 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !17, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!14 = !DISubprogram(name: "fn6", linkageName: "_Z3fn6v", line: 15, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 15, file: !5, scope: !15, type: !16, function: void ()* @_Z3fn6v, variables: !2)
+!15 = !DIFile(filename: "recursive_inlining.cpp", directory: "/usr/local/google/home/blaikie/dev/scratch/missing_concrete_variable_on_darwin/reduce")
+!16 = !DISubroutineType(types: !17)
 !17 = !{null}
-!18 = !{!"0x2e\00fn3\00fn3\00_Z3fn3v\0020\000\001\000\006\00256\001\0020", !5, !15, !16, null, void ()* @_Z3fn3v, null, null, !2} ; [ DW_TAG_subprogram ] [line 20] [def] [fn3]
-!19 = !{!"0x2e\00fn4\00fn4\00_Z3fn4v\0021\000\001\000\006\00256\001\0021", !5, !15, !16, null, void ()* @_Z3fn4v, null, null, !2} ; [ DW_TAG_subprogram ] [line 21] [def] [fn4]
-!20 = !{!"0x2e\00fn5\00fn5\00_Z3fn5v\0022\000\001\000\006\00256\001\0022", !5, !15, !16, null, void ()* @_Z3fn5v, null, null, !2} ; [ DW_TAG_subprogram ] [line 22] [def] [fn5]
-!21 = !{!"0x2e\00fn7\00fn7\00_Z3fn7v\0014\000\001\000\006\00256\001\0014", !5, !15, !16, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 14] [def] [fn7]
-!22 = !{!"0x2e\00m_fn2\00m_fn2\00_ZN1C5m_fn2Ev\007\000\001\000\006\00256\001\007", !5, !"_ZTS1C", !10, null, void (%struct.C*)* @_ZN1C5m_fn2Ev, null, !9, !23} ; [ DW_TAG_subprogram ] [line 7] [def] [m_fn2]
+!18 = !DISubprogram(name: "fn3", linkageName: "_Z3fn3v", line: 20, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 20, file: !5, scope: !15, type: !16, function: void ()* @_Z3fn3v, variables: !2)
+!19 = !DISubprogram(name: "fn4", linkageName: "_Z3fn4v", line: 21, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 21, file: !5, scope: !15, type: !16, function: void ()* @_Z3fn4v, variables: !2)
+!20 = !DISubprogram(name: "fn5", linkageName: "_Z3fn5v", line: 22, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 22, file: !5, scope: !15, type: !16, function: void ()* @_Z3fn5v, variables: !2)
+!21 = !DISubprogram(name: "fn7", linkageName: "_Z3fn7v", line: 14, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 14, file: !5, scope: !15, type: !16, variables: !2)
+!22 = !DISubprogram(name: "m_fn2", linkageName: "_ZN1C5m_fn2Ev", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 7, file: !5, scope: !"_ZTS1C", type: !10, function: void (%struct.C*)* @_ZN1C5m_fn2Ev, declaration: !9, variables: !23)
 !23 = !{!24}
-!24 = !{!"0x101\00this\0016777216\001088", !22, null, !25} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!25 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1C"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1C]
+!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !22, type: !25)
+!25 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1C")
 !26 = !{!27}
-!27 = !{!"0x34\00x\00x\00\0013\000\001", null, !15, !25, %struct.C** @x, null} ; [ DW_TAG_variable ] [x] [line 13] [def]
+!27 = !DIGlobalVariable(name: "x", line: 13, isLocal: false, isDefinition: true, scope: null, file: !15, type: !25, variable: %struct.C** @x)
 !28 = !{i32 2, !"Dwarf Version", i32 4}
-!29 = !{i32 2, !"Debug Info Version", i32 2}
+!29 = !{i32 2, !"Debug Info Version", i32 3}
 !30 = !{!"clang version 3.6.0 "}
-!31 = !MDLocation(line: 16, scope: !14)
-!32 = !MDLocation(line: 17, scope: !14)
+!31 = !DILocation(line: 16, scope: !14)
+!32 = !DILocation(line: 17, scope: !14)
 !33 = !{!34, !34, i64 0}
 !34 = !{!"any pointer", !35, i64 0}
 !35 = !{!"omnipotent char", !36, i64 0}
 !36 = !{!"Simple C/C++ TBAA"}
-!37 = !{!"0x101\00this\0016777216\001088", !22, null, !25, !32} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!38 = !MDLocation(line: 0, scope: !22, inlinedAt: !32)
-!39 = !MDLocation(line: 8, scope: !22, inlinedAt: !32)
-!40 = !MDLocation(line: 9, scope: !41, inlinedAt: !32)
-!41 = !{!"0xb\009\000\000", !5, !22} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/blaikie/dev/scratch/missing_concrete_variable_on_darwin/reduce/recursive_inlining.cpp]
+!37 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !22, type: !25)
+!38 = !DILocation(line: 0, scope: !22, inlinedAt: !32)
+!39 = !DILocation(line: 8, scope: !22, inlinedAt: !32)
+!40 = !DILocation(line: 9, scope: !41, inlinedAt: !32)
+!41 = distinct !DILexicalBlock(line: 9, column: 0, file: !5, scope: !22)
 !42 = !{!43, !44, i64 0}
 !43 = !{!"_ZTS1C", !44, i64 0}
 !44 = !{!"int", !35, i64 0}
-!45 = !MDLocation(line: 9, scope: !46, inlinedAt: !32)
-!46 = !{!"0xb\009\000\001", !5, !41} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/blaikie/dev/scratch/missing_concrete_variable_on_darwin/reduce/recursive_inlining.cpp]
-!47 = !MDLocation(line: 10, scope: !22, inlinedAt: !32)
-!48 = !MDLocation(line: 19, scope: !14)
-!49 = !MDLocation(line: 0, scope: !22)
-!50 = !MDLocation(line: 8, scope: !22)
-!51 = !MDLocation(line: 9, scope: !41)
-!52 = !MDLocation(line: 9, scope: !46)
-!53 = !MDLocation(line: 16, scope: !14, inlinedAt: !54)
-!54 = !MDLocation(line: 20, scope: !18, inlinedAt: !55)
-!55 = !MDLocation(line: 10, scope: !22)
-!56 = !MDLocation(line: 17, scope: !14, inlinedAt: !54)
-!57 = !{!"0x101\00this\0016777216\001088", !22, null, !25, !56} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!58 = !MDLocation(line: 0, scope: !22, inlinedAt: !56)
-!59 = !MDLocation(line: 8, scope: !22, inlinedAt: !56)
-!60 = !MDLocation(line: 9, scope: !41, inlinedAt: !56)
-!61 = !MDLocation(line: 9, scope: !46, inlinedAt: !56)
-!62 = !MDLocation(line: 10, scope: !22, inlinedAt: !56)
-!63 = !MDLocation(line: 11, scope: !22)
-!64 = !MDLocation(line: 16, scope: !14, inlinedAt: !65)
-!65 = !MDLocation(line: 20, scope: !18)
-!66 = !MDLocation(line: 17, scope: !14, inlinedAt: !65)
-!67 = !{!"0x101\00this\0016777216\001088", !22, null, !25, !66} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!68 = !MDLocation(line: 0, scope: !22, inlinedAt: !66)
-!69 = !MDLocation(line: 8, scope: !22, inlinedAt: !66)
-!70 = !MDLocation(line: 9, scope: !41, inlinedAt: !66)
-!71 = !MDLocation(line: 9, scope: !46, inlinedAt: !66)
-!72 = !MDLocation(line: 21, scope: !19)
-!73 = !MDLocation(line: 22, scope: !20)
+!45 = !DILocation(line: 9, scope: !46, inlinedAt: !32)
+!46 = distinct !DILexicalBlock(line: 9, column: 0, file: !5, scope: !41)
+!47 = !DILocation(line: 10, scope: !22, inlinedAt: !32)
+!48 = !DILocation(line: 19, scope: !14)
+!49 = !DILocation(line: 0, scope: !22)
+!50 = !DILocation(line: 8, scope: !22)
+!51 = !DILocation(line: 9, scope: !41)
+!52 = !DILocation(line: 9, scope: !46)
+!53 = !DILocation(line: 16, scope: !14, inlinedAt: !54)
+!54 = !DILocation(line: 20, scope: !18, inlinedAt: !55)
+!55 = !DILocation(line: 10, scope: !22)
+!56 = !DILocation(line: 17, scope: !14, inlinedAt: !54)
+!57 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !22, type: !25)
+!58 = !DILocation(line: 0, scope: !22, inlinedAt: !56)
+!59 = !DILocation(line: 8, scope: !22, inlinedAt: !56)
+!60 = !DILocation(line: 9, scope: !41, inlinedAt: !56)
+!61 = !DILocation(line: 9, scope: !46, inlinedAt: !56)
+!62 = !DILocation(line: 10, scope: !22, inlinedAt: !56)
+!63 = !DILocation(line: 11, scope: !22)
+!64 = !DILocation(line: 16, scope: !14, inlinedAt: !65)
+!65 = !DILocation(line: 20, scope: !18)
+!66 = !DILocation(line: 17, scope: !14, inlinedAt: !65)
+!67 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !22, type: !25)
+!68 = !DILocation(line: 0, scope: !22, inlinedAt: !66)
+!69 = !DILocation(line: 8, scope: !22, inlinedAt: !66)
+!70 = !DILocation(line: 9, scope: !41, inlinedAt: !66)
+!71 = !DILocation(line: 9, scope: !46, inlinedAt: !66)
+!72 = !DILocation(line: 21, scope: !19)
+!73 = !DILocation(line: 22, scope: !20)
diff --git a/test/DebugInfo/X86/ref_addr_relocation.ll b/test/DebugInfo/X86/ref_addr_relocation.ll
index 7e39b8ee2a92..488f98ef8e1f 100644
--- a/test/DebugInfo/X86/ref_addr_relocation.ll
+++ b/test/DebugInfo/X86/ref_addr_relocation.ll
@@ -2,6 +2,7 @@
 ; RUN: llc -filetype=obj -O0 %s -mtriple=x86_64-linux-gnu -o %t
 ; RUN: llvm-dwarfdump %t | FileCheck %s -check-prefix=CHECK-DWARF
 
+; RUN: llc -filetype=asm -O0 -mtriple=x86_64-apple-darwin < %s | FileCheck --check-prefix=DARWIN-ASM %s
 ; RUN: llc -filetype=obj %s -mtriple=x86_64-apple-darwin -o %t2
 ; RUN: llvm-dwarfdump %t2 | FileCheck %s -check-prefix=DARWIN-DWARF
 
@@ -23,7 +24,7 @@
 ; CHECK: DW_TAG_variable
 ; CHECK: .long [[TYPE:.*]] # DW_AT_type
 ; CHECK: DW_TAG_structure_type
-; CHECK: debug_info_begin1
+; CHECK: cu_begin1
 ; CHECK: DW_TAG_compile_unit
 ; CHECK-NOT: DW_TAG_structure_type
 ; This variable's type is in the 1st CU.
@@ -33,6 +34,10 @@
 ; CHECK-NOT: DW_TAG_structure_type
 ; CHECK: .section
 
+; test that we don't create useless labels
+; DARWIN-ASM: .long [[TYPE:.*]] ## DW_AT_type
+; DARWIN-ASM: .quad [[TYPE]] ## DW_AT_type
+
 ; CHECK-DWARF: DW_TAG_compile_unit
 ; CHECK-DWARF: 0x[[ADDR:.*]]: DW_TAG_structure_type
 ; CHECK-DWARF: DW_TAG_compile_unit
@@ -53,19 +58,19 @@
 !llvm.dbg.cu = !{!0, !9}
 !llvm.module.flags = !{!14, !15}
 
-!0 = !{!"0x11\004\00clang version 3.4 (trunk 191799)\000\00\000\00\000", !1, !2, !3, !2, !6, !2} ; [ DW_TAG_compile_unit ] [/Users/manmanren/test-Nov/type_unique_air/ref_addr/tu1.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"tu1.cpp", !"/Users/manmanren/test-Nov/type_unique_air/ref_addr"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 (trunk 191799)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !2, globals: !6, imports: !2)
+!1 = !DIFile(filename: "tu1.cpp", directory: "/Users/manmanren/test-Nov/type_unique_air/ref_addr")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00foo\001\008\008\000\000\000", !5, null, null, !2, null, null, !"_ZTS3foo"} ; [ DW_TAG_structure_type ] [foo] [line 1, size 8, align 8, offset 0] [def] [from ]
-!5 = !{!"./hdr.h", !"/Users/manmanren/test-Nov/type_unique_air/ref_addr"}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo", line: 1, size: 8, align: 8, file: !5, elements: !2, identifier: "_ZTS3foo")
+!5 = !DIFile(filename: "./hdr.h", directory: "/Users/manmanren/test-Nov/type_unique_air/ref_addr")
 !6 = !{!7}
-!7 = !{!"0x34\00f\00f\00\002\000\001", null, !8, !4, %struct.foo* @f, null} ; [ DW_TAG_variable ] [f] [line 2] [def]
-!8 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/Users/manmanren/test-Nov/type_unique_air/ref_addr/tu1.cpp]
-!9 = !{!"0x11\004\00clang version 3.4 (trunk 191799)\000\00\000\00\000", !10, !2, !3, !2, !11, !2} ; [ DW_TAG_compile_unit ] [/Users/manmanren/test-Nov/type_unique_air/ref_addr/tu2.cpp] [DW_LANG_C_plus_plus]
-!10 = !{!"tu2.cpp", !"/Users/manmanren/test-Nov/type_unique_air/ref_addr"}
+!7 = !DIGlobalVariable(name: "f", line: 2, isLocal: false, isDefinition: true, scope: null, file: !8, type: !4, variable: %struct.foo* @f)
+!8 = !DIFile(filename: "tu1.cpp", directory: "/Users/manmanren/test-Nov/type_unique_air/ref_addr")
+!9 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 (trunk 191799)", isOptimized: false, emissionKind: 0, file: !10, enums: !2, retainedTypes: !3, subprograms: !2, globals: !11, imports: !2)
+!10 = !DIFile(filename: "tu2.cpp", directory: "/Users/manmanren/test-Nov/type_unique_air/ref_addr")
 !11 = !{!12}
-!12 = !{!"0x34\00g\00g\00\002\000\001", null, !13, !4, %struct.foo* @g, null} ; [ DW_TAG_variable ] [g] [line 2] [def]
-!13 = !{!"0x29", !10}        ; [ DW_TAG_file_type ] [/Users/manmanren/test-Nov/type_unique_air/ref_addr/tu2.cpp]
+!12 = !DIGlobalVariable(name: "g", line: 2, isLocal: false, isDefinition: true, scope: null, file: !13, type: !4, variable: %struct.foo* @g)
+!13 = !DIFile(filename: "tu2.cpp", directory: "/Users/manmanren/test-Nov/type_unique_air/ref_addr")
 !14 = !{i32 2, !"Dwarf Version", i32 2}
-!15 = !{i32 1, !"Debug Info Version", i32 2}
+!15 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/reference-argument.ll b/test/DebugInfo/X86/reference-argument.ll
index 68ff200be400..401553ec9711 100644
--- a/test/DebugInfo/X86/reference-argument.ll
+++ b/test/DebugInfo/X86/reference-argument.ll
@@ -20,9 +20,9 @@ define linkonce_odr void @_ZN1A3fooE4SVal(%class.A* %this, %class.SVal* %v) noun
 entry:
   %this.addr = alloca %class.A*, align 8
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !59, metadata !{!"0x102"}), !dbg !61
-  call void @llvm.dbg.declare(metadata %class.SVal* %v, metadata !62, metadata !{!"0x102"}), !dbg !61
-  %this1 = load %class.A** %this.addr
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !59, metadata !DIExpression()), !dbg !61
+  call void @llvm.dbg.declare(metadata %class.SVal* %v, metadata !62, metadata !DIExpression(DW_OP_deref)), !dbg !61
+  %this1 = load %class.A*, %class.A** %this.addr
   call void @_Z3barR4SVal(%class.SVal* %v), !dbg !61
   ret void, !dbg !61
 }
@@ -32,72 +32,67 @@ declare void @_ZN4SValD2Ev(%class.SVal* %this)
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!47, !68}
 
-!0 = !{!"0x11\004\00clang version 3.4 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [aggregate-indirect-arg.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"aggregate-indirect-arg.cpp", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "aggregate-indirect-arg.cpp", directory: "")
 !2 = !{}
 !3 = !{!4, !29, !33, !34, !35}
-!4 = !{!"0x2e\00bar\00bar\00_Z3barR4SVal\0019\000\001\000\006\00256\000\0019", !1, !5, !6, null, void (%class.SVal*)* @_Z3barR4SVal, null, null, !2} ; [ DW_TAG_subprogram ] [line 19] [def] [bar]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [aggregate-indirect-arg.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "bar", linkageName: "_Z3barR4SVal", line: 19, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 19, file: !1, scope: !5, type: !6, function: void (%class.SVal*)* @_Z3barR4SVal, variables: !2)
+!5 = !DIFile(filename: "aggregate-indirect-arg.cpp", directory: "")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null, !8}
-!8 = !{!"0x10\00\000\000\000\000\000", null, null, !9} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from SVal]
-!9 = !{!"0x2\00SVal\0012\00128\0064\000\000\000", !1, null, null, !10, null, null, null} ; [ DW_TAG_class_type ] [SVal] [line 12, size 128, align 64, offset 0] [def] [from ]
+!8 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !9)
+!9 = !DICompositeType(tag: DW_TAG_class_type, name: "SVal", line: 12, size: 128, align: 64, file: !1, elements: !10)
 !10 = !{!11, !14, !16, !21, !23}
-!11 = !{!"0xd\00Data\0015\0064\0064\000\000", !1, !9, !12} ; [ DW_TAG_member ] [Data] [line 15, size 64, align 64, offset 0] [from ]
-!12 = !{!"0xf\00\000\0064\0064\000\000", null, null, !13} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!13 = !{!"0x26\00\000\000\000\000\000", null, null, null} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from ]
-!14 = !{!"0xd\00Kind\0016\0032\0032\0064\000", !1, !9, !15} ; [ DW_TAG_member ] [Kind] [line 16, size 32, align 32, offset 64] [from unsigned int]
-!15 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, null} ; [ DW_TAG_base_type ] [unsigned int] [line 0, size 32, align 32, offset 0, enc DW_ATE_unsigned]
-!16 = !{!"0x2e\00~SVal\00~SVal\00\0014\000\000\000\006\00256\000\0014", !1, !9, !17, null, null, null, i32 0, !20} ; [ DW_TAG_subprogram ] [line 14] [~SVal]
-!17 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !18, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!11 = !DIDerivedType(tag: DW_TAG_member, name: "Data", line: 15, size: 64, align: 64, file: !1, scope: !9, baseType: !12)
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !13)
+!13 = !DIDerivedType(tag: DW_TAG_const_type, baseType: null)
+!14 = !DIDerivedType(tag: DW_TAG_member, name: "Kind", line: 16, size: 32, align: 32, offset: 64, file: !1, scope: !9, baseType: !15)
+!15 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!16 = !DISubprogram(name: "~SVal", line: 14, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 14, file: !1, scope: !9, type: !17)
+!17 = !DISubroutineType(types: !18)
 !18 = !{null, !19}
-!19 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from SVal]
-!20 = !{i32 786468}
-!21 = !{!"0x2e\00SVal\00SVal\00\0012\000\000\000\006\00320\000\0012", !1, !9, !17, null, null, null, i32 0, !22} ; [ DW_TAG_subprogram ] [line 12] [SVal]
-!22 = !{i32 786468}
-!23 = !{!"0x2e\00SVal\00SVal\00\0012\000\000\000\006\00320\000\0012", !1, !9, !24, null, null, null, i32 0, !28} ; [ DW_TAG_subprogram ] [line 12] [SVal]
-!24 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !25, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!19 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !9)
+!21 = !DISubprogram(name: "SVal", line: 12, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 12, file: !1, scope: !9, type: !17)
+!23 = !DISubprogram(name: "SVal", line: 12, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 12, file: !1, scope: !9, type: !24)
+!24 = !DISubroutineType(types: !25)
 !25 = !{null, !19, !26}
-!26 = !{!"0x10\00\000\000\000\000\000", null, null, !27} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from ]
-!27 = !{!"0x26\00\000\000\000\000\000", null, null, !9} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from SVal]
-!28 = !{i32 786468}
-!29 = !{!"0x2e\00main\00main\00\0025\000\001\000\006\00256\000\0025", !1, !5, !30, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 25] [def] [main]
-!30 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !31, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!26 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !27)
+!27 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !9)
+!29 = !DISubprogram(name: "main", line: 25, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 25, file: !1, scope: !5, type: !30, function: i32 ()* @main, variables: !2)
+!30 = !DISubroutineType(types: !31)
 !31 = !{!32}
-!32 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!33 = !{!"0x2e\00~SVal\00~SVal\00_ZN4SValD1Ev\0014\000\001\000\006\00256\000\0014", !1, null, !17, null, void (%class.SVal*)* @_ZN4SValD1Ev, null, !16, !2} ; [ DW_TAG_subprogram ] [line 14] [def] [~SVal]
-!34 = !{!"0x2e\00~SVal\00~SVal\00_ZN4SValD2Ev\0014\000\001\000\006\00256\000\0014", !1, null, !17, null, void (%class.SVal*)* @_ZN4SValD2Ev, null, !16, !2} ; [ DW_TAG_subprogram ] [line 14] [def] [~SVal]
-!35 = !{!"0x2e\00foo\00foo\00_ZN1A3fooE4SVal\0022\000\001\000\006\00256\000\0022", !1, null, !36, null, void (%class.A*, %class.SVal*)* @_ZN1A3fooE4SVal, null, !41, !2} ; [ DW_TAG_subprogram ] [line 22] [def] [foo]
-!36 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !37, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!32 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!33 = !DISubprogram(name: "~SVal", linkageName: "_ZN4SValD1Ev", line: 14, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 14, file: !1, scope: null, type: !17, function: void (%class.SVal*)* @_ZN4SValD1Ev, declaration: !16, variables: !2)
+!34 = !DISubprogram(name: "~SVal", linkageName: "_ZN4SValD2Ev", line: 14, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 14, file: !1, scope: null, type: !17, function: void (%class.SVal*)* @_ZN4SValD2Ev, declaration: !16, variables: !2)
+!35 = !DISubprogram(name: "foo", linkageName: "_ZN1A3fooE4SVal", line: 22, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 22, file: !1, scope: null, type: !36, function: void (%class.A*, %class.SVal*)* @_ZN1A3fooE4SVal, declaration: !41, variables: !2)
+!36 = !DISubroutineType(types: !37)
 !37 = !{null, !38, !9}
-!38 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !39} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from A]
-!39 = !{!"0x2\00A\0020\008\008\000\000\000", !1, null, null, !40, null, null, null} ; [ DW_TAG_class_type ] [A] [line 20, size 8, align 8, offset 0] [def] [from ]
+!38 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !39)
+!39 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 20, size: 8, align: 8, file: !1, elements: !40)
 !40 = !{!41, !43}
-!41 = !{!"0x2e\00foo\00foo\00_ZN1A3fooE4SVal\0022\000\000\000\006\00256\000\0022", !1, !39, !36, null, null, null, i32 0, !42} ; [ DW_TAG_subprogram ] [line 22] [foo]
-!42 = !{i32 786468}
-!43 = !{!"0x2e\00A\00A\00\0020\000\000\000\006\00320\000\0020", !1, !39, !44, null, null, null, i32 0, !46} ; [ DW_TAG_subprogram ] [line 20] [A]
-!44 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !45, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!41 = !DISubprogram(name: "foo", linkageName: "_ZN1A3fooE4SVal", line: 22, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 22, file: !1, scope: !39, type: !36)
+!43 = !DISubprogram(name: "A", line: 20, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 20, file: !1, scope: !39, type: !44)
+!44 = !DISubroutineType(types: !45)
 !45 = !{null, !38}
-!46 = !{i32 786468}
 !47 = !{i32 2, !"Dwarf Version", i32 3}
-!48 = !{!"0x101\00v\0016777235\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [v] [line 19]
-!49 = !MDLocation(line: 19, scope: !4)
-!50 = !{!"0x100\00v\0026\000", !29, !5, !9} ; [ DW_TAG_auto_variable ] [v] [line 26]
-!51 = !MDLocation(line: 26, scope: !29)
-!52 = !MDLocation(line: 27, scope: !29)
-!53 = !MDLocation(line: 28, scope: !29)
-!54 = !{!"0x100\00a\0029\000", !29, !5, !39} ; [ DW_TAG_auto_variable ] [a] [line 29]
-!55 = !MDLocation(line: 29, scope: !29)
-!56 = !MDLocation(line: 30, scope: !29)
-!57 = !MDLocation(line: 31, scope: !29)
-!58 = !MDLocation(line: 32, scope: !29)
-!59 = !{!"0x101\00this\0016777238\001088", !35, !5, !60} ; [ DW_TAG_arg_variable ] [this] [line 22]
-!60 = !{!"0xf\00\000\0064\0064\000\000", null, null, !39} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from A]
-!61 = !MDLocation(line: 22, scope: !35)
-!62 = !{!"0x101\00v\0033554454\008192", !35, !5, !9} ; [ DW_TAG_arg_variable ] [v] [line 22]
-!63 = !{!"0x101\00this\0016777230\001088", !33, !5, !64} ; [ DW_TAG_arg_variable ] [this] [line 14]
-!64 = !{!"0xf\00\000\0064\0064\000\000", null, null, !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from SVal]
-!65 = !MDLocation(line: 14, scope: !33)
-!66 = !{!"0x101\00this\0016777230\001088", !34, !5, !64} ; [ DW_TAG_arg_variable ] [this] [line 14]
-!67 = !MDLocation(line: 14, scope: !34)
-!68 = !{i32 1, !"Debug Info Version", i32 2}
+!48 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "v", line: 19, arg: 1, scope: !4, file: !5, type: !8)
+!49 = !DILocation(line: 19, scope: !4)
+!50 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "v", line: 26, scope: !29, file: !5, type: !9)
+!51 = !DILocation(line: 26, scope: !29)
+!52 = !DILocation(line: 27, scope: !29)
+!53 = !DILocation(line: 28, scope: !29)
+!54 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 29, scope: !29, file: !5, type: !39)
+!55 = !DILocation(line: 29, scope: !29)
+!56 = !DILocation(line: 30, scope: !29)
+!57 = !DILocation(line: 31, scope: !29)
+!58 = !DILocation(line: 32, scope: !29)
+!59 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 22, arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !35, file: !5, type: !60)
+!60 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !39)
+!61 = !DILocation(line: 22, scope: !35)
+!62 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "v", line: 22, arg: 2, scope: !35, file: !5, type: !9)
+!63 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 14, arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !33, file: !5, type: !64)
+!64 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !9)
+!65 = !DILocation(line: 14, scope: !33)
+!66 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 14, arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !34, file: !5, type: !64)
+!67 = !DILocation(line: 14, scope: !34)
+!68 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/rvalue-ref.ll b/test/DebugInfo/X86/rvalue-ref.ll
index 3829966482fe..4e4da67beb08 100644
--- a/test/DebugInfo/X86/rvalue-ref.ll
+++ b/test/DebugInfo/X86/rvalue-ref.ll
@@ -9,10 +9,10 @@ define void @_Z3fooOi(i32* %i) uwtable ssp {
 entry:
   %i.addr = alloca i32*, align 8
   store i32* %i, i32** %i.addr, align 8
-  call void @llvm.dbg.declare(metadata i32** %i.addr, metadata !11, metadata !{!"0x102"}), !dbg !12
-  %0 = load i32** %i.addr, align 8, !dbg !13
-  %1 = load i32* %0, align 4, !dbg !13
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 %1), !dbg !13
+  call void @llvm.dbg.declare(metadata i32** %i.addr, metadata !11, metadata !DIExpression()), !dbg !12
+  %0 = load i32*, i32** %i.addr, align 8, !dbg !13
+  %1 = load i32, i32* %0, align 4, !dbg !13
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %1), !dbg !13
   ret void, !dbg !15
 }
 
@@ -23,19 +23,19 @@ declare i32 @printf(i8*, ...)
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!17}
 
-!0 = !{!"0x11\004\00clang version 3.2 (trunk 157054) (llvm/trunk 157060)\000\00\000\00\000", !16, !1, !1, !3, !1,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.2 (trunk 157054) (llvm/trunk 157060)", isOptimized: false, emissionKind: 0, file: !16, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00foo\00foo\00_Z3fooOi\004\000\001\000\006\00256\000\005", !16, !6, !7, null, void (i32*)* @_Z3fooOi, null, null, !1} ; [ DW_TAG_subprogram ]
-!6 = !{!"0x29", !16} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "foo", linkageName: "_Z3fooOi", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !16, scope: !6, type: !7, function: void (i32*)* @_Z3fooOi, variables: !1)
+!6 = !DIFile(filename: "foo.cpp", directory: "/Users/echristo/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9}
-!9 = !{!"0x42\00\000\000\000\000\000", null, null, !10} ; [ DW_TAG_rvalue_reference_type ]
-!10 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!11 = !{!"0x101\00i\0016777220\000", !5, !6, !9} ; [ DW_TAG_arg_variable ]
-!12 = !MDLocation(line: 4, column: 17, scope: !5)
-!13 = !MDLocation(line: 6, column: 3, scope: !14)
-!14 = !{!"0xb\005\001\000", !16, !5} ; [ DW_TAG_lexical_block ]
-!15 = !MDLocation(line: 7, column: 1, scope: !14)
-!16 = !{!"foo.cpp", !"/Users/echristo/tmp"}
-!17 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DIDerivedType(tag: DW_TAG_rvalue_reference_type, baseType: !10)
+!10 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!11 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 4, arg: 1, scope: !5, file: !6, type: !9)
+!12 = !DILocation(line: 4, column: 17, scope: !5)
+!13 = !DILocation(line: 6, column: 3, scope: !14)
+!14 = distinct !DILexicalBlock(line: 5, column: 1, file: !16, scope: !5)
+!15 = !DILocation(line: 7, column: 1, scope: !14)
+!16 = !DIFile(filename: "foo.cpp", directory: "/Users/echristo/tmp")
+!17 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/sret.ll b/test/DebugInfo/X86/sret.ll
index 42d65695f63c..54d93d571bea 100644
--- a/test/DebugInfo/X86/sret.ll
+++ b/test/DebugInfo/X86/sret.ll
@@ -12,7 +12,7 @@
 @_ZTV1A = linkonce_odr unnamed_addr constant [4 x i8*] [i8* null, i8* bitcast ({ i8*, i8* }* @_ZTI1A to i8*), i8* bitcast (void (%class.A*)* @_ZN1AD2Ev to i8*), i8* bitcast (void (%class.A*)* @_ZN1AD0Ev to i8*)]
 @_ZTVN10__cxxabiv117__class_type_infoE = external global i8*
 @_ZTS1A = linkonce_odr constant [3 x i8] c"1A\00"
-@_ZTI1A = linkonce_odr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8]* @_ZTS1A, i32 0, i32 0) }
+@_ZTI1A = linkonce_odr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @_ZTS1A, i32 0, i32 0) }
 
 @_ZN1AC1Ei = alias void (%class.A*, i32)* @_ZN1AC2Ei
 @_ZN1AC1ERKS_ = alias void (%class.A*, %class.A*)* @_ZN1AC2ERKS_
@@ -23,14 +23,14 @@ entry:
   %this.addr = alloca %class.A*, align 8
   %i.addr = alloca i32, align 4
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !67, metadata !{!"0x102"}), !dbg !69
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !67, metadata !DIExpression()), !dbg !69
   store i32 %i, i32* %i.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %i.addr, metadata !70, metadata !{!"0x102"}), !dbg !71
-  %this1 = load %class.A** %this.addr
+  call void @llvm.dbg.declare(metadata i32* %i.addr, metadata !70, metadata !DIExpression()), !dbg !71
+  %this1 = load %class.A*, %class.A** %this.addr
   %0 = bitcast %class.A* %this1 to i8***, !dbg !72
-  store i8** getelementptr inbounds ([4 x i8*]* @_ZTV1A, i64 0, i64 2), i8*** %0, !dbg !72
-  %m_int = getelementptr inbounds %class.A* %this1, i32 0, i32 1, !dbg !72
-  %1 = load i32* %i.addr, align 4, !dbg !72
+  store i8** getelementptr inbounds ([4 x i8*], [4 x i8*]* @_ZTV1A, i64 0, i64 2), i8*** %0, !dbg !72
+  %m_int = getelementptr inbounds %class.A, %class.A* %this1, i32 0, i32 1, !dbg !72
+  %1 = load i32, i32* %i.addr, align 4, !dbg !72
   store i32 %1, i32* %m_int, align 4, !dbg !72
   ret void, !dbg !73
 }
@@ -44,16 +44,16 @@ entry:
   %this.addr = alloca %class.A*, align 8
   %rhs.addr = alloca %class.A*, align 8
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !74, metadata !{!"0x102"}), !dbg !75
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !74, metadata !DIExpression()), !dbg !75
   store %class.A* %rhs, %class.A** %rhs.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %rhs.addr, metadata !76, metadata !{!"0x102"}), !dbg !77
-  %this1 = load %class.A** %this.addr
+  call void @llvm.dbg.declare(metadata %class.A** %rhs.addr, metadata !76, metadata !DIExpression()), !dbg !77
+  %this1 = load %class.A*, %class.A** %this.addr
   %0 = bitcast %class.A* %this1 to i8***, !dbg !78
-  store i8** getelementptr inbounds ([4 x i8*]* @_ZTV1A, i64 0, i64 2), i8*** %0, !dbg !78
-  %m_int = getelementptr inbounds %class.A* %this1, i32 0, i32 1, !dbg !78
-  %1 = load %class.A** %rhs.addr, align 8, !dbg !78
-  %m_int2 = getelementptr inbounds %class.A* %1, i32 0, i32 1, !dbg !78
-  %2 = load i32* %m_int2, align 4, !dbg !78
+  store i8** getelementptr inbounds ([4 x i8*], [4 x i8*]* @_ZTV1A, i64 0, i64 2), i8*** %0, !dbg !78
+  %m_int = getelementptr inbounds %class.A, %class.A* %this1, i32 0, i32 1, !dbg !78
+  %1 = load %class.A*, %class.A** %rhs.addr, align 8, !dbg !78
+  %m_int2 = getelementptr inbounds %class.A, %class.A* %1, i32 0, i32 1, !dbg !78
+  %2 = load i32, i32* %m_int2, align 4, !dbg !78
   store i32 %2, i32* %m_int, align 4, !dbg !78
   ret void, !dbg !79
 }
@@ -64,14 +64,14 @@ entry:
   %this.addr = alloca %class.A*, align 8
   %rhs.addr = alloca %class.A*, align 8
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !80, metadata !{!"0x102"}), !dbg !81
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !80, metadata !DIExpression()), !dbg !81
   store %class.A* %rhs, %class.A** %rhs.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %rhs.addr, metadata !82, metadata !{!"0x102"}), !dbg !83
-  %this1 = load %class.A** %this.addr
-  %0 = load %class.A** %rhs.addr, align 8, !dbg !84
-  %m_int = getelementptr inbounds %class.A* %0, i32 0, i32 1, !dbg !84
-  %1 = load i32* %m_int, align 4, !dbg !84
-  %m_int2 = getelementptr inbounds %class.A* %this1, i32 0, i32 1, !dbg !84
+  call void @llvm.dbg.declare(metadata %class.A** %rhs.addr, metadata !82, metadata !DIExpression()), !dbg !83
+  %this1 = load %class.A*, %class.A** %this.addr
+  %0 = load %class.A*, %class.A** %rhs.addr, align 8, !dbg !84
+  %m_int = getelementptr inbounds %class.A, %class.A* %0, i32 0, i32 1, !dbg !84
+  %1 = load i32, i32* %m_int, align 4, !dbg !84
+  %m_int2 = getelementptr inbounds %class.A, %class.A* %this1, i32 0, i32 1, !dbg !84
   store i32 %1, i32* %m_int2, align 4, !dbg !84
   ret %class.A* %this1, !dbg !85
 }
@@ -81,10 +81,10 @@ define i32 @_ZN1A7get_intEv(%class.A* %this) #0 align 2 {
 entry:
   %this.addr = alloca %class.A*, align 8
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !86, metadata !{!"0x102"}), !dbg !87
-  %this1 = load %class.A** %this.addr
-  %m_int = getelementptr inbounds %class.A* %this1, i32 0, i32 1, !dbg !88
-  %0 = load i32* %m_int, align 4, !dbg !88
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !86, metadata !DIExpression()), !dbg !87
+  %this1 = load %class.A*, %class.A** %this.addr
+  %m_int = getelementptr inbounds %class.A, %class.A* %this1, i32 0, i32 1, !dbg !88
+  %0 = load i32, i32* %m_int, align 4, !dbg !88
   ret i32 %0, !dbg !88
 }
 
@@ -95,14 +95,14 @@ entry:
   %nrvo = alloca i1
   %cleanup.dest.slot = alloca i32
   store %class.B* %this, %class.B** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.B** %this.addr, metadata !89, metadata !{!"0x102"}), !dbg !91
-  %this1 = load %class.B** %this.addr
+  call void @llvm.dbg.declare(metadata %class.B** %this.addr, metadata !89, metadata !DIExpression()), !dbg !91
+  %this1 = load %class.B*, %class.B** %this.addr
   store i1 false, i1* %nrvo, !dbg !92
-  call void @llvm.dbg.declare(metadata %class.A* %agg.result, metadata !93, metadata !{!"0x102"}), !dbg !92
+  call void @llvm.dbg.declare(metadata %class.A* %agg.result, metadata !93, metadata !DIExpression(DW_OP_deref)), !dbg !92
   call void @_ZN1AC1Ei(%class.A* %agg.result, i32 12), !dbg !92
   store i1 true, i1* %nrvo, !dbg !94
   store i32 1, i32* %cleanup.dest.slot
-  %nrvo.val = load i1* %nrvo, !dbg !95
+  %nrvo.val = load i1, i1* %nrvo, !dbg !95
   br i1 %nrvo.val, label %nrvo.skipdtor, label %nrvo.unused, !dbg !95
 
 nrvo.unused:                                      ; preds = %entry
@@ -118,8 +118,8 @@ define linkonce_odr void @_ZN1AD2Ev(%class.A* %this) unnamed_addr #0 align 2 {
 entry:
   %this.addr = alloca %class.A*, align 8
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !101, metadata !{!"0x102"}), !dbg !102
-  %this1 = load %class.A** %this.addr
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !101, metadata !DIExpression()), !dbg !102
+  %this1 = load %class.A*, %class.A** %this.addr
   ret void, !dbg !103
 }
 
@@ -138,12 +138,12 @@ entry:
   %cleanup.dest.slot = alloca i32
   store i32 0, i32* %retval
   store i32 %argc, i32* %argc.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %argc.addr, metadata !104, metadata !{!"0x102"}), !dbg !105
+  call void @llvm.dbg.declare(metadata i32* %argc.addr, metadata !104, metadata !DIExpression()), !dbg !105
   store i8** %argv, i8*** %argv.addr, align 8
-  call void @llvm.dbg.declare(metadata i8*** %argv.addr, metadata !106, metadata !{!"0x102"}), !dbg !105
-  call void @llvm.dbg.declare(metadata %class.B* %b, metadata !107, metadata !{!"0x102"}), !dbg !108
+  call void @llvm.dbg.declare(metadata i8*** %argv.addr, metadata !106, metadata !DIExpression()), !dbg !105
+  call void @llvm.dbg.declare(metadata %class.B* %b, metadata !107, metadata !DIExpression()), !dbg !108
   call void @_ZN1BC2Ev(%class.B* %b), !dbg !108
-  call void @llvm.dbg.declare(metadata i32* %return_val, metadata !109, metadata !{!"0x102"}), !dbg !110
+  call void @llvm.dbg.declare(metadata i32* %return_val, metadata !109, metadata !DIExpression()), !dbg !110
   call void @_ZN1B9AInstanceEv(%class.A* sret %temp.lvalue, %class.B* %b), !dbg !110
   %call = invoke i32 @_ZN1A7get_intEv(%class.A* %temp.lvalue)
           to label %invoke.cont unwind label %lpad, !dbg !110
@@ -151,13 +151,13 @@ entry:
 invoke.cont:                                      ; preds = %entry
   call void @_ZN1AD2Ev(%class.A* %temp.lvalue), !dbg !111
   store i32 %call, i32* %return_val, align 4, !dbg !111
-  call void @llvm.dbg.declare(metadata %class.A* %a, metadata !113, metadata !{!"0x102"}), !dbg !114
+  call void @llvm.dbg.declare(metadata %class.A* %a, metadata !113, metadata !DIExpression()), !dbg !114
   call void @_ZN1B9AInstanceEv(%class.A* sret %a, %class.B* %b), !dbg !114
-  %0 = load i32* %return_val, align 4, !dbg !115
+  %0 = load i32, i32* %return_val, align 4, !dbg !115
   store i32 %0, i32* %retval, !dbg !115
   store i32 1, i32* %cleanup.dest.slot
   call void @_ZN1AD2Ev(%class.A* %a), !dbg !116
-  %1 = load i32* %retval, !dbg !116
+  %1 = load i32, i32* %retval, !dbg !116
   ret i32 %1, !dbg !116
 
 lpad:                                             ; preds = %entry
@@ -174,8 +174,8 @@ invoke.cont1:                                     ; preds = %lpad
   br label %eh.resume, !dbg !117
 
 eh.resume:                                        ; preds = %invoke.cont1
-  %exn = load i8** %exn.slot, !dbg !119
-  %sel = load i32* %ehselector.slot, !dbg !119
+  %exn = load i8*, i8** %exn.slot, !dbg !119
+  %sel = load i32, i32* %ehselector.slot, !dbg !119
   %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn, 0, !dbg !119
   %lpad.val2 = insertvalue { i8*, i32 } %lpad.val, i32 %sel, 1, !dbg !119
   resume { i8*, i32 } %lpad.val2, !dbg !119
@@ -193,8 +193,8 @@ define linkonce_odr void @_ZN1BC2Ev(%class.B* %this) unnamed_addr #0 align 2 {
 entry:
   %this.addr = alloca %class.B*, align 8
   store %class.B* %this, %class.B** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.B** %this.addr, metadata !123, metadata !{!"0x102"}), !dbg !124
-  %this1 = load %class.B** %this.addr
+  call void @llvm.dbg.declare(metadata %class.B** %this.addr, metadata !123, metadata !DIExpression()), !dbg !124
+  %this1 = load %class.B*, %class.B** %this.addr
   ret void, !dbg !125
 }
 
@@ -218,8 +218,8 @@ entry:
   %exn.slot = alloca i8*
   %ehselector.slot = alloca i32
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !126, metadata !{!"0x102"}), !dbg !127
-  %this1 = load %class.A** %this.addr
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !126, metadata !DIExpression()), !dbg !127
+  %this1 = load %class.A*, %class.A** %this.addr
   invoke void @_ZN1AD2Ev(%class.A* %this1)
           to label %invoke.cont unwind label %lpad, !dbg !128
 
@@ -240,8 +240,8 @@ lpad:                                             ; preds = %entry
   br label %eh.resume, !dbg !131
 
 eh.resume:                                        ; preds = %lpad
-  %exn = load i8** %exn.slot, !dbg !133
-  %sel = load i32* %ehselector.slot, !dbg !133
+  %exn = load i8*, i8** %exn.slot, !dbg !133
+  %sel = load i32, i32* %ehselector.slot, !dbg !133
   %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn, 0, !dbg !133
   %lpad.val2 = insertvalue { i8*, i32 } %lpad.val, i32 %sel, 1, !dbg !133
   resume { i8*, i32 } %lpad.val2, !dbg !133
@@ -263,131 +263,131 @@ attributes #7 = { builtin nounwind }
 !llvm.module.flags = !{!64, !65}
 !llvm.ident = !{!66}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 (trunk 203283) (llvm/trunk 203307)\000\00\000\00sret.dwo\001", !1, !2, !3, !48, !2, !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/sret.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"sret.cpp", !"/usr/local/google/home/echristo/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 (trunk 203283) (llvm/trunk 203307)", isOptimized: false, splitDebugFilename: "sret.dwo", emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !48, globals: !2, imports: !2)
+!1 = !DIFile(filename: "sret.cpp", directory: "/usr/local/google/home/echristo/tmp")
 !2 = !{}
 !3 = !{!4, !37}
-!4 = !{!"0x2\00A\001\00128\0064\000\000\000", !1, null, null, !5, !"_ZTS1A", null, !"_ZTS1A"} ; [ DW_TAG_class_type ] [A] [line 1, size 128, align 64, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 1, size: 128, align: 64, file: !1, elements: !5, vtableHolder: !"_ZTS1A", identifier: "_ZTS1A")
 !5 = !{!6, !13, !14, !19, !25, !29, !33}
-!6 = !{!"0xd\00_vptr$A\000\0064\000\000\0064", !1, !7, !8} ; [ DW_TAG_member ] [_vptr$A] [line 0, size 64, align 0, offset 0] [artificial] [from ]
-!7 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/usr/local/google/home/echristo/tmp/sret.cpp]
-!8 = !{!"0xf\00\000\0064\000\000\000", null, null, !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from __vtbl_ptr_type]
-!9 = !{!"0xf\00__vtbl_ptr_type\000\0064\000\000\000", null, null, !10} ; [ DW_TAG_pointer_type ] [__vtbl_ptr_type] [line 0, size 64, align 0, offset 0] [from ]
-!10 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DIDerivedType(tag: DW_TAG_member, name: "_vptr$A", size: 64, flags: DIFlagArtificial, file: !1, scope: !7, baseType: !8)
+!7 = !DIFile(filename: "sret.cpp", directory: "/usr/local/google/home/echristo/tmp")
+!8 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, baseType: !9)
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "__vtbl_ptr_type", size: 64, baseType: !10)
+!10 = !DISubroutineType(types: !11)
 !11 = !{!12}
-!12 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!13 = !{!"0xd\00m_int\0013\0032\0032\0064\002", !1, !"_ZTS1A", !12} ; [ DW_TAG_member ] [m_int] [line 13, size 32, align 32, offset 64] [protected] [from int]
-!14 = !{!"0x2e\00A\00A\00\004\000\000\000\006\00256\000\004", !1, !"_ZTS1A", !15, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 4] [A]
-!15 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!13 = !DIDerivedType(tag: DW_TAG_member, name: "m_int", line: 13, size: 32, align: 32, offset: 64, flags: DIFlagProtected, file: !1, scope: !"_ZTS1A", baseType: !12)
+!14 = !DISubprogram(name: "A", line: 4, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !1, scope: !"_ZTS1A", type: !15)
+!15 = !DISubroutineType(types: !16)
 !16 = !{null, !17, !12}
-!17 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1A]
-!19 = !{!"0x2e\00A\00A\00\005\000\000\000\006\00256\000\005", !1, !"_ZTS1A", !20, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 5] [A]
-!20 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !21, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1A")
+!19 = !DISubprogram(name: "A", line: 5, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !"_ZTS1A", type: !20)
+!20 = !DISubroutineType(types: !21)
 !21 = !{null, !17, !22}
-!22 = !{!"0x10\00\000\000\000\000\000", null, null, !23} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from ]
-!23 = !{!"0x26\00\000\000\000\000\000", null, null, !"_ZTS1A"} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from _ZTS1A]
-!25 = !{!"0x2e\00operator=\00operator=\00_ZN1AaSERKS_\007\000\000\000\006\00256\000\007", !1, !"_ZTS1A", !26, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 7] [operator=]
-!26 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !27, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!22 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !23)
+!23 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !"_ZTS1A")
+!25 = !DISubprogram(name: "operator=", linkageName: "_ZN1AaSERKS_", line: 7, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !1, scope: !"_ZTS1A", type: !26)
+!26 = !DISubroutineType(types: !27)
 !27 = !{!22, !17, !22}
-!29 = !{!"0x2e\00~A\00~A\00\008\000\000\001\006\00256\000\008", !1, !"_ZTS1A", !30, !"_ZTS1A", null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 8] [~A]
-!30 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !31, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!29 = !DISubprogram(name: "~A", line: 8, isLocal: false, isDefinition: false, virtuality: DW_VIRTUALITY_virtual, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 8, file: !1, scope: !"_ZTS1A", type: !30, containingType: !"_ZTS1A")
+!30 = !DISubroutineType(types: !31)
 !31 = !{null, !17}
-!33 = !{!"0x2e\00get_int\00get_int\00_ZN1A7get_intEv\0010\000\000\000\006\00256\000\0010", !1, !"_ZTS1A", !34, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 10] [get_int]
-!34 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !35, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!33 = !DISubprogram(name: "get_int", linkageName: "_ZN1A7get_intEv", line: 10, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 10, file: !1, scope: !"_ZTS1A", type: !34)
+!34 = !DISubroutineType(types: !35)
 !35 = !{!12, !17}
-!37 = !{!"0x2\00B\0038\008\008\000\000\000", !1, null, null, !38, null, null, !"_ZTS1B"} ; [ DW_TAG_class_type ] [B] [line 38, size 8, align 8, offset 0] [def] [from ]
+!37 = !DICompositeType(tag: DW_TAG_class_type, name: "B", line: 38, size: 8, align: 8, file: !1, elements: !38, identifier: "_ZTS1B")
 !38 = !{!39, !44}
-!39 = !{!"0x2e\00B\00B\00\0041\000\000\000\006\00256\000\0041", !1, !"_ZTS1B", !40, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 41] [B]
-!40 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !41, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!39 = !DISubprogram(name: "B", line: 41, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 41, file: !1, scope: !"_ZTS1B", type: !40)
+!40 = !DISubroutineType(types: !41)
 !41 = !{null, !42}
-!42 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1B"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1B]
-!44 = !{!"0x2e\00AInstance\00AInstance\00_ZN1B9AInstanceEv\0043\000\000\000\006\00256\000\0043", !1, !"_ZTS1B", !45, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 43] [AInstance]
-!45 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !46, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!42 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1B")
+!44 = !DISubprogram(name: "AInstance", linkageName: "_ZN1B9AInstanceEv", line: 43, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 43, file: !1, scope: !"_ZTS1B", type: !45)
+!45 = !DISubroutineType(types: !46)
 !46 = !{!4, !42}
 !48 = !{!49, !50, !51, !52, !53, !54, !61, !62, !63}
-!49 = !{!"0x2e\00A\00A\00_ZN1AC2Ei\0016\000\001\000\006\00256\000\0018", !1, !"_ZTS1A", !15, null, void (%class.A*, i32)* @_ZN1AC2Ei, null, !14, !2} ; [ DW_TAG_subprogram ] [line 16] [def] [scope 18] [A]
-!50 = !{!"0x2e\00A\00A\00_ZN1AC2ERKS_\0021\000\001\000\006\00256\000\0023", !1, !"_ZTS1A", !20, null, void (%class.A*, %class.A*)* @_ZN1AC2ERKS_, null, !19, !2} ; [ DW_TAG_subprogram ] [line 21] [def] [scope 23] [A]
-!51 = !{!"0x2e\00operator=\00operator=\00_ZN1AaSERKS_\0027\000\001\000\006\00256\000\0028", !1, !"_ZTS1A", !26, null, %class.A* (%class.A*, %class.A*)* @_ZN1AaSERKS_, null, !25, !2} ; [ DW_TAG_subprogram ] [line 27] [def] [scope 28] [operator=]
-!52 = !{!"0x2e\00get_int\00get_int\00_ZN1A7get_intEv\0033\000\001\000\006\00256\000\0034", !1, !"_ZTS1A", !34, null, i32 (%class.A*)* @_ZN1A7get_intEv, null, !33, !2} ; [ DW_TAG_subprogram ] [line 33] [def] [scope 34] [get_int]
-!53 = !{!"0x2e\00AInstance\00AInstance\00_ZN1B9AInstanceEv\0047\000\001\000\006\00256\000\0048", !1, !"_ZTS1B", !45, null, void (%class.A*, %class.B*)* @_ZN1B9AInstanceEv, null, !44, !2} ; [ DW_TAG_subprogram ] [line 47] [def] [scope 48] [AInstance]
-!54 = !{!"0x2e\00main\00main\00\0053\000\001\000\006\00256\000\0054", !1, !7, !55, null, i32 (i32, i8**)* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 53] [def] [scope 54] [main]
-!55 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !56, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!49 = !DISubprogram(name: "A", linkageName: "_ZN1AC2Ei", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 18, file: !1, scope: !"_ZTS1A", type: !15, function: void (%class.A*, i32)* @_ZN1AC2Ei, declaration: !14, variables: !2)
+!50 = !DISubprogram(name: "A", linkageName: "_ZN1AC2ERKS_", line: 21, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 23, file: !1, scope: !"_ZTS1A", type: !20, function: void (%class.A*, %class.A*)* @_ZN1AC2ERKS_, declaration: !19, variables: !2)
+!51 = !DISubprogram(name: "operator=", linkageName: "_ZN1AaSERKS_", line: 27, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 28, file: !1, scope: !"_ZTS1A", type: !26, function: %class.A* (%class.A*, %class.A*)* @_ZN1AaSERKS_, declaration: !25, variables: !2)
+!52 = !DISubprogram(name: "get_int", linkageName: "_ZN1A7get_intEv", line: 33, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 34, file: !1, scope: !"_ZTS1A", type: !34, function: i32 (%class.A*)* @_ZN1A7get_intEv, declaration: !33, variables: !2)
+!53 = !DISubprogram(name: "AInstance", linkageName: "_ZN1B9AInstanceEv", line: 47, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 48, file: !1, scope: !"_ZTS1B", type: !45, function: void (%class.A*, %class.B*)* @_ZN1B9AInstanceEv, declaration: !44, variables: !2)
+!54 = !DISubprogram(name: "main", line: 53, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 54, file: !1, scope: !7, type: !55, function: i32 (i32, i8**)* @main, variables: !2)
+!55 = !DISubroutineType(types: !56)
 !56 = !{!12, !12, !57}
-!57 = !{!"0xf\00\000\0064\0064\000\000", null, null, !58} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!58 = !{!"0xf\00\000\0064\0064\000\000", null, null, !59} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!59 = !{!"0x26\00\000\000\000\000\000", null, null, !60} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from char]
-!60 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
-!61 = !{!"0x2e\00~A\00~A\00_ZN1AD0Ev\008\000\001\000\006\00256\000\008", !1, !"_ZTS1A", !30, null, void (%class.A*)* @_ZN1AD0Ev, null, !29, !2} ; [ DW_TAG_subprogram ] [line 8] [def] [~A]
-!62 = !{!"0x2e\00B\00B\00_ZN1BC2Ev\0041\000\001\000\006\00256\000\0041", !1, !"_ZTS1B", !40, null, void (%class.B*)* @_ZN1BC2Ev, null, !39, !2} ; [ DW_TAG_subprogram ] [line 41] [def] [B]
-!63 = !{!"0x2e\00~A\00~A\00_ZN1AD2Ev\008\000\001\000\006\00256\000\008", !1, !"_ZTS1A", !30, null, void (%class.A*)* @_ZN1AD2Ev, null, !29, !2} ; [ DW_TAG_subprogram ] [line 8] [def] [~A]
+!57 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !58)
+!58 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !59)
+!59 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !60)
+!60 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!61 = !DISubprogram(name: "~A", linkageName: "_ZN1AD0Ev", line: 8, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 8, file: !1, scope: !"_ZTS1A", type: !30, function: void (%class.A*)* @_ZN1AD0Ev, declaration: !29, variables: !2)
+!62 = !DISubprogram(name: "B", linkageName: "_ZN1BC2Ev", line: 41, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 41, file: !1, scope: !"_ZTS1B", type: !40, function: void (%class.B*)* @_ZN1BC2Ev, declaration: !39, variables: !2)
+!63 = !DISubprogram(name: "~A", linkageName: "_ZN1AD2Ev", line: 8, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 8, file: !1, scope: !"_ZTS1A", type: !30, function: void (%class.A*)* @_ZN1AD2Ev, declaration: !29, variables: !2)
 !64 = !{i32 2, !"Dwarf Version", i32 4}
-!65 = !{i32 1, !"Debug Info Version", i32 2}
+!65 = !{i32 1, !"Debug Info Version", i32 3}
 !66 = !{!"clang version 3.5.0 (trunk 203283) (llvm/trunk 203307)"}
-!67 = !{!"0x101\00this\0016777216\001088", !49, null, !68} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!68 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1A]
-!69 = !MDLocation(line: 0, scope: !49)
-!70 = !{!"0x101\00i\0033554448\000", !49, !7, !12} ; [ DW_TAG_arg_variable ] [i] [line 16]
-!71 = !MDLocation(line: 16, scope: !49)
-!72 = !MDLocation(line: 18, scope: !49)
-!73 = !MDLocation(line: 19, scope: !49)
-!74 = !{!"0x101\00this\0016777216\001088", !50, null, !68} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!75 = !MDLocation(line: 0, scope: !50)
-!76 = !{!"0x101\00rhs\0033554453\000", !50, !7, !22} ; [ DW_TAG_arg_variable ] [rhs] [line 21]
-!77 = !MDLocation(line: 21, scope: !50)
-!78 = !MDLocation(line: 23, scope: !50)
-!79 = !MDLocation(line: 24, scope: !50)
-!80 = !{!"0x101\00this\0016777216\001088", !51, null, !68} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!81 = !MDLocation(line: 0, scope: !51)
-!82 = !{!"0x101\00rhs\0033554459\000", !51, !7, !22} ; [ DW_TAG_arg_variable ] [rhs] [line 27]
-!83 = !MDLocation(line: 27, scope: !51)
-!84 = !MDLocation(line: 29, scope: !51)
-!85 = !MDLocation(line: 30, scope: !51)
-!86 = !{!"0x101\00this\0016777216\001088", !52, null, !68} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!87 = !MDLocation(line: 0, scope: !52)
-!88 = !MDLocation(line: 35, scope: !52)
-!89 = !{!"0x101\00this\0016777216\001088", !53, null, !90} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!90 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1B"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1B]
-!91 = !MDLocation(line: 0, scope: !53)
-!92 = !MDLocation(line: 49, scope: !53)
-!93 = !{!"0x100\00a\0049\008192", !53, !7, !4} ; [ DW_TAG_auto_variable ] [a] [line 49]
-!94 = !MDLocation(line: 50, scope: !53)
-!95 = !MDLocation(line: 51, scope: !53)
-!96 = !MDLocation(line: 51, scope: !97)
-!97 = !{!"0xb\0051\000\002", !1, !53} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/sret.cpp]
-!98 = !MDLocation(line: 51, scope: !99)
-!99 = !{!"0xb\0051\000\003", !1, !100} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/sret.cpp]
-!100 = !{!"0xb\0051\000\001", !1, !53} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/sret.cpp]
-!101 = !{!"0x101\00this\0016777216\001088", !63, null, !68} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!102 = !MDLocation(line: 0, scope: !63)
-!103 = !MDLocation(line: 8, scope: !63)
-!104 = !{!"0x101\00argc\0016777269\000", !54, !7, !12} ; [ DW_TAG_arg_variable ] [argc] [line 53]
-!105 = !MDLocation(line: 53, scope: !54)
-!106 = !{!"0x101\00argv\0033554485\000", !54, !7, !57} ; [ DW_TAG_arg_variable ] [argv] [line 53]
-!107 = !{!"0x100\00b\0055\000", !54, !7, !37} ; [ DW_TAG_auto_variable ] [b] [line 55]
-!108 = !MDLocation(line: 55, scope: !54)
-!109 = !{!"0x100\00return_val\0056\000", !54, !7, !12} ; [ DW_TAG_auto_variable ] [return_val] [line 56]
-!110 = !MDLocation(line: 56, scope: !54)
-!111 = !MDLocation(line: 56, scope: !112)
-!112 = !{!"0xb\0056\000\001", !1, !54} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/sret.cpp]
-!113 = !{!"0x100\00a\0058\000", !54, !7, !4} ; [ DW_TAG_auto_variable ] [a] [line 58]
-!114 = !MDLocation(line: 58, scope: !54)
-!115 = !MDLocation(line: 59, scope: !54)
-!116 = !MDLocation(line: 60, scope: !54)
-!117 = !MDLocation(line: 60, scope: !118)
-!118 = !{!"0xb\0060\000\001", !1, !54} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/sret.cpp]
-!119 = !MDLocation(line: 60, scope: !120)
-!120 = !{!"0xb\0060\000\003", !1, !54} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/sret.cpp]
-!121 = !MDLocation(line: 60, scope: !122)
-!122 = !{!"0xb\0060\000\002", !1, !54} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/sret.cpp]
-!123 = !{!"0x101\00this\0016777216\001088", !62, null, !90} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!124 = !MDLocation(line: 0, scope: !62)
-!125 = !MDLocation(line: 41, scope: !62)
-!126 = !{!"0x101\00this\0016777216\001088", !61, null, !68} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!127 = !MDLocation(line: 0, scope: !61)
-!128 = !MDLocation(line: 8, scope: !61)
-!129 = !MDLocation(line: 8, scope: !130)
-!130 = !{!"0xb\008\000\001", !1, !61} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/sret.cpp]
-!131 = !MDLocation(line: 8, scope: !132)
-!132 = !{!"0xb\008\000\002", !1, !61} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/sret.cpp]
-!133 = !MDLocation(line: 8, scope: !134)
-!134 = !{!"0xb\008\000\003", !1, !61} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/sret.cpp]
+!67 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !49, type: !68)
+!68 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1A")
+!69 = !DILocation(line: 0, scope: !49)
+!70 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 16, arg: 2, scope: !49, file: !7, type: !12)
+!71 = !DILocation(line: 16, scope: !49)
+!72 = !DILocation(line: 18, scope: !49)
+!73 = !DILocation(line: 19, scope: !49)
+!74 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !50, type: !68)
+!75 = !DILocation(line: 0, scope: !50)
+!76 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "rhs", line: 21, arg: 2, scope: !50, file: !7, type: !22)
+!77 = !DILocation(line: 21, scope: !50)
+!78 = !DILocation(line: 23, scope: !50)
+!79 = !DILocation(line: 24, scope: !50)
+!80 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !51, type: !68)
+!81 = !DILocation(line: 0, scope: !51)
+!82 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "rhs", line: 27, arg: 2, scope: !51, file: !7, type: !22)
+!83 = !DILocation(line: 27, scope: !51)
+!84 = !DILocation(line: 29, scope: !51)
+!85 = !DILocation(line: 30, scope: !51)
+!86 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !52, type: !68)
+!87 = !DILocation(line: 0, scope: !52)
+!88 = !DILocation(line: 35, scope: !52)
+!89 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !53, type: !90)
+!90 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1B")
+!91 = !DILocation(line: 0, scope: !53)
+!92 = !DILocation(line: 49, scope: !53)
+!93 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 49, scope: !53, file: !7, type: !4)
+!94 = !DILocation(line: 50, scope: !53)
+!95 = !DILocation(line: 51, scope: !53)
+!96 = !DILocation(line: 51, scope: !97)
+!97 = distinct !DILexicalBlock(line: 51, column: 0, file: !1, scope: !53)
+!98 = !DILocation(line: 51, scope: !99)
+!99 = distinct !DILexicalBlock(line: 51, column: 0, file: !1, scope: !100)
+!100 = distinct !DILexicalBlock(line: 51, column: 0, file: !1, scope: !53)
+!101 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !63, type: !68)
+!102 = !DILocation(line: 0, scope: !63)
+!103 = !DILocation(line: 8, scope: !63)
+!104 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 53, arg: 1, scope: !54, file: !7, type: !12)
+!105 = !DILocation(line: 53, scope: !54)
+!106 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 53, arg: 2, scope: !54, file: !7, type: !57)
+!107 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 55, scope: !54, file: !7, type: !37)
+!108 = !DILocation(line: 55, scope: !54)
+!109 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "return_val", line: 56, scope: !54, file: !7, type: !12)
+!110 = !DILocation(line: 56, scope: !54)
+!111 = !DILocation(line: 56, scope: !112)
+!112 = distinct !DILexicalBlock(line: 56, column: 0, file: !1, scope: !54)
+!113 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 58, scope: !54, file: !7, type: !4)
+!114 = !DILocation(line: 58, scope: !54)
+!115 = !DILocation(line: 59, scope: !54)
+!116 = !DILocation(line: 60, scope: !54)
+!117 = !DILocation(line: 60, scope: !118)
+!118 = distinct !DILexicalBlock(line: 60, column: 0, file: !1, scope: !54)
+!119 = !DILocation(line: 60, scope: !120)
+!120 = distinct !DILexicalBlock(line: 60, column: 0, file: !1, scope: !54)
+!121 = !DILocation(line: 60, scope: !122)
+!122 = distinct !DILexicalBlock(line: 60, column: 0, file: !1, scope: !54)
+!123 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !62, type: !90)
+!124 = !DILocation(line: 0, scope: !62)
+!125 = !DILocation(line: 41, scope: !62)
+!126 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !61, type: !68)
+!127 = !DILocation(line: 0, scope: !61)
+!128 = !DILocation(line: 8, scope: !61)
+!129 = !DILocation(line: 8, scope: !130)
+!130 = distinct !DILexicalBlock(line: 8, column: 0, file: !1, scope: !61)
+!131 = !DILocation(line: 8, scope: !132)
+!132 = distinct !DILexicalBlock(line: 8, column: 0, file: !1, scope: !61)
+!133 = !DILocation(line: 8, scope: !134)
+!134 = distinct !DILexicalBlock(line: 8, column: 0, file: !1, scope: !61)
diff --git a/test/DebugInfo/X86/sroasplit-1.ll b/test/DebugInfo/X86/sroasplit-1.ll
new file mode 100644
index 000000000000..2179aa380953
--- /dev/null
+++ b/test/DebugInfo/X86/sroasplit-1.ll
@@ -0,0 +1,97 @@
+; RUN: opt %s -sroa -verify -S -o - | FileCheck %s
+;
+; Test that we can partial emit debug info for aggregates repeatedly
+; split up by SROA.
+;
+;    // Compile with -O1
+;    typedef struct {
+;      int a;
+;      long int b;
+;    } Inner;
+;
+;    typedef struct {
+;      Inner inner[2];
+;    } Outer;
+;
+;    int foo(Outer outer) {
+;      Inner i1 = outer.inner[1];
+;      return i1.a;
+;    }
+;
+
+; Verify that SROA creates a variable piece when splitting i1.
+; CHECK: %[[I1:.*]] = alloca [12 x i8], align 4
+; CHECK: call void @llvm.dbg.declare(metadata [12 x i8]* %[[I1]], metadata ![[VAR:[0-9]+]], metadata ![[PIECE1:[0-9]+]])
+; CHECK: call void @llvm.dbg.value(metadata i32 %[[A:.*]], i64 0, metadata ![[VAR]], metadata ![[PIECE2:[0-9]+]])
+; CHECK: ret i32 %[[A]]
+; Read Var and Piece:
+; CHECK: ![[VAR]] = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i1",{{.*}} line: 11,
+; CHECK: ![[PIECE1]] = !DIExpression(DW_OP_bit_piece, 32, 96)
+; CHECK: ![[PIECE2]] = !DIExpression(DW_OP_bit_piece, 0, 32)
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.9.0"
+
+%struct.Outer = type { [2 x %struct.Inner] }
+%struct.Inner = type { i32, i64 }
+
+; Function Attrs: nounwind ssp uwtable
+define i32 @foo(%struct.Outer* byval align 8 %outer) #0 {
+entry:
+  %i1 = alloca %struct.Inner, align 8
+  call void @llvm.dbg.declare(metadata %struct.Outer* %outer, metadata !25, metadata !2), !dbg !26
+  call void @llvm.dbg.declare(metadata %struct.Inner* %i1, metadata !27, metadata !2), !dbg !28
+  %inner = getelementptr inbounds %struct.Outer, %struct.Outer* %outer, i32 0, i32 0, !dbg !28
+  %arrayidx = getelementptr inbounds [2 x %struct.Inner], [2 x %struct.Inner]* %inner, i32 0, i64 1, !dbg !28
+  %0 = bitcast %struct.Inner* %i1 to i8*, !dbg !28
+  %1 = bitcast %struct.Inner* %arrayidx to i8*, !dbg !28
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 16, i32 8, i1 false), !dbg !28
+  %a = getelementptr inbounds %struct.Inner, %struct.Inner* %i1, i32 0, i32 0, !dbg !29
+  %2 = load i32, i32* %a, align 4, !dbg !29
+  ret i32 %2, !dbg !29
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+; Function Attrs: nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #2
+
+attributes #0 = { nounwind ssp uwtable }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!22, !23}
+!llvm.ident = !{!24}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !{}, retainedTypes: !{}, subprograms: !3, globals: !{}, imports: !{})
+!1 = !DIFile(filename: "sroasplit-1.c", directory: "")
+!2 = !DIExpression()
+!3 = !{!4}
+!4 = !DISubprogram(name: "foo", line: 10, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 10, file: !1, scope: !5, type: !6, function: i32 (%struct.Outer*)* @foo, variables: !{})
+!5 = !DIFile(filename: "sroasplit-1.c", directory: "")
+!6 = !DISubroutineType(types: !7)
+!7 = !{!8, !9}
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_typedef, name: "Outer", line: 8, file: !1, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_structure_type, line: 6, size: 256, align: 64, file: !1, elements: !11)
+!11 = !{!12}
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "inner", line: 7, size: 256, align: 64, file: !1, scope: !10, baseType: !13)
+!13 = !DICompositeType(tag: DW_TAG_array_type, size: 256, align: 64, baseType: !14, elements: !20)
+!14 = !DIDerivedType(tag: DW_TAG_typedef, name: "Inner", line: 4, file: !1, baseType: !15)
+!15 = !DICompositeType(tag: DW_TAG_structure_type, line: 1, size: 128, align: 64, file: !1, elements: !16)
+!16 = !{!17, !18}
+!17 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 2, size: 32, align: 32, file: !1, scope: !15, baseType: !8)
+!18 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 3, size: 64, align: 64, offset: 64, file: !1, scope: !15, baseType: !19)
+!19 = !DIBasicType(tag: DW_TAG_base_type, name: "long int", size: 64, align: 64, encoding: DW_ATE_signed)
+!20 = !{!21}
+!21 = !DISubrange(count: 2)
+!22 = !{i32 2, !"Dwarf Version", i32 2}
+!23 = !{i32 1, !"Debug Info Version", i32 3}
+!24 = !{!"clang version 3.5.0 "}
+!25 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "outer", line: 10, arg: 1, scope: !4, file: !5, type: !9)
+!26 = !DILocation(line: 10, scope: !4)
+!27 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i1", line: 11, scope: !4, file: !5, type: !14)
+!28 = !DILocation(line: 11, scope: !4)
+!29 = !DILocation(line: 12, scope: !4)
diff --git a/test/DebugInfo/X86/sroasplit-2.ll b/test/DebugInfo/X86/sroasplit-2.ll
new file mode 100644
index 000000000000..b209fafd4df1
--- /dev/null
+++ b/test/DebugInfo/X86/sroasplit-2.ll
@@ -0,0 +1,102 @@
+; RUN: opt %s -sroa -verify -S -o - | FileCheck %s
+;
+; Test that we can partial emit debug info for aggregates repeatedly
+; split up by SROA.
+;
+;    // Compile with -O1
+;    typedef struct {
+;      int a;
+;      int b;
+;    } Inner;
+;
+;    typedef struct {
+;      Inner inner[2];
+;    } Outer;
+;
+;    int foo(Outer outer) {
+;      Inner i1 = outer.inner[1];
+;      return i1.a;
+;    }
+;
+
+; Verify that SROA creates a variable piece when splitting i1.
+; CHECK:  call void @llvm.dbg.value(metadata i64 %outer.coerce0, i64 0, metadata ![[O:[0-9]+]], metadata ![[PIECE1:[0-9]+]]),
+; CHECK:  call void @llvm.dbg.value(metadata i64 %outer.coerce1, i64 0, metadata ![[O]], metadata ![[PIECE2:[0-9]+]]),
+; CHECK:  call void @llvm.dbg.value({{.*}}, i64 0, metadata ![[I1:[0-9]+]], metadata ![[PIECE3:[0-9]+]]),
+; CHECK-DAG: ![[O]] = !DILocalVariable(tag: DW_TAG_arg_variable, name: "outer",{{.*}} line: 10
+; CHECK-DAG: ![[PIECE1]] = !DIExpression(DW_OP_bit_piece, 0, 64)
+; CHECK-DAG: ![[PIECE2]] = !DIExpression(DW_OP_bit_piece, 64, 64)
+; CHECK-DAG: ![[I1]] = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i1",{{.*}} line: 11
+; CHECK-DAG: ![[PIECE3]] = !DIExpression(DW_OP_bit_piece, 0, 32)
+
+; ModuleID = 'sroasplit-2.c'
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.9.0"
+
+%struct.Outer = type { [2 x %struct.Inner] }
+%struct.Inner = type { i32, i32 }
+
+; Function Attrs: nounwind ssp uwtable
+define i32 @foo(i64 %outer.coerce0, i64 %outer.coerce1) #0 {
+  %outer = alloca %struct.Outer, align 8
+  %i1 = alloca %struct.Inner, align 4
+  %1 = bitcast %struct.Outer* %outer to { i64, i64 }*
+  %2 = getelementptr { i64, i64 }, { i64, i64 }* %1, i32 0, i32 0
+  store i64 %outer.coerce0, i64* %2
+  %3 = getelementptr { i64, i64 }, { i64, i64 }* %1, i32 0, i32 1
+  store i64 %outer.coerce1, i64* %3
+  call void @llvm.dbg.declare(metadata %struct.Outer* %outer, metadata !24, metadata !2), !dbg !25
+  call void @llvm.dbg.declare(metadata %struct.Inner* %i1, metadata !26, metadata !2), !dbg !27
+  %4 = getelementptr inbounds %struct.Outer, %struct.Outer* %outer, i32 0, i32 0, !dbg !27
+  %5 = getelementptr inbounds [2 x %struct.Inner], [2 x %struct.Inner]* %4, i32 0, i64 1, !dbg !27
+  %6 = bitcast %struct.Inner* %i1 to i8*, !dbg !27
+  %7 = bitcast %struct.Inner* %5 to i8*, !dbg !27
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %6, i8* %7, i64 8, i32 4, i1 false), !dbg !27
+  %8 = getelementptr inbounds %struct.Inner, %struct.Inner* %i1, i32 0, i32 0, !dbg !28
+  %9 = load i32, i32* %8, align 4, !dbg !28
+  ret i32 %9, !dbg !28
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+; Function Attrs: nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #2
+
+attributes #0 = { nounwind ssp uwtable "no-frame-pointer-elim"="true" }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!21, !22}
+!llvm.ident = !{!23}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !{}, retainedTypes: !{}, subprograms: !3, globals: !{}, imports: !{})
+!1 = !DIFile(filename: "sroasplit-2.c", directory: "")
+!2 = !DIExpression()
+!3 = !{!4}
+!4 = !DISubprogram(name: "foo", line: 10, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 10, file: !1, scope: !5, type: !6, function: i32 (i64, i64)* @foo, variables: !{})
+!5 = !DIFile(filename: "sroasplit-2.c", directory: "")
+!6 = !DISubroutineType(types: !7)
+!7 = !{!8, !9}
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_typedef, name: "Outer", line: 8, file: !1, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_structure_type, line: 6, size: 128, align: 32, file: !1, elements: !11)
+!11 = !{!12}
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "inner", line: 7, size: 128, align: 32, file: !1, scope: !10, baseType: !13)
+!13 = !DICompositeType(tag: DW_TAG_array_type, size: 128, align: 32, baseType: !14, elements: !19)
+!14 = !DIDerivedType(tag: DW_TAG_typedef, name: "Inner", line: 4, file: !1, baseType: !15)
+!15 = !DICompositeType(tag: DW_TAG_structure_type, line: 1, size: 64, align: 32, file: !1, elements: !16)
+!16 = !{!17, !18}
+!17 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 2, size: 32, align: 32, file: !1, scope: !15, baseType: !8)
+!18 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 3, size: 32, align: 32, offset: 32, file: !1, scope: !15, baseType: !8)
+!19 = !{!20}
+!20 = !DISubrange(count: 2)
+!21 = !{i32 2, !"Dwarf Version", i32 2}
+!22 = !{i32 1, !"Debug Info Version", i32 3}
+!23 = !{!"clang version 3.5.0 "}
+!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "outer", line: 10, arg: 1, scope: !4, file: !5, type: !9)
+!25 = !DILocation(line: 10, scope: !4)
+!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i1", line: 11, scope: !4, file: !5, type: !14)
+!27 = !DILocation(line: 11, scope: !4)
+!28 = !DILocation(line: 12, scope: !4)
diff --git a/test/DebugInfo/X86/sroasplit-3.ll b/test/DebugInfo/X86/sroasplit-3.ll
new file mode 100644
index 000000000000..50b701f781d8
--- /dev/null
+++ b/test/DebugInfo/X86/sroasplit-3.ll
@@ -0,0 +1,63 @@
+; RUN: opt %s -sroa -verify -S -o - | FileCheck %s
+; ModuleID = 'test.c'
+; Test that SROA updates the debug info correctly if an alloca was rewritten but
+; not partitioned into multiple allocas.
+;
+; CHECK: call void @llvm.dbg.value(metadata float %s.coerce, i64 0, metadata ![[VAR:[0-9]+]], metadata ![[EXPR:[0-9]+]])
+; CHECK: ![[VAR]] = !DILocalVariable(tag: DW_TAG_arg_variable, name: "s",{{.*}} line: 3,
+; CHECK: ![[EXPR]] = !DIExpression(
+; CHECK-NOT:                       DW_OP_bit_piece
+
+;
+; struct S { float f; };
+;  
+; float foo(struct S s) {
+;   return s.f;
+; }
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+%struct.S = type { float }
+
+; Function Attrs: nounwind ssp uwtable
+define float @foo(float %s.coerce) #0 {
+entry:
+  %s = alloca %struct.S, align 4
+  %coerce.dive = getelementptr %struct.S, %struct.S* %s, i32 0, i32 0
+  store float %s.coerce, float* %coerce.dive, align 1
+  call void @llvm.dbg.declare(metadata %struct.S* %s, metadata !16, metadata !17), !dbg !18
+  %f = getelementptr inbounds %struct.S, %struct.S* %s, i32 0, i32 0, !dbg !19
+  %0 = load float, float* %f, align 4, !dbg !19
+  ret float %0, !dbg !19
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+attributes #0 = { nounwind ssp uwtable }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!12, !13, !14}
+!llvm.ident = !{!15}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.6.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.c", directory: "/Volumes/Data/llvm/_build.ninja.debug")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "foo", line: 3, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !5, type: !6, function: float (float)* @foo, variables: !2)
+!5 = !DIFile(filename: "test.c", directory: "/Volumes/Data/llvm/_build.ninja.debug")
+!6 = !DISubroutineType(types: !7)
+!7 = !{!8, !9}
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float)
+!9 = !DICompositeType(tag: DW_TAG_structure_type, name: "S", line: 1, size: 32, align: 32, file: !1, elements: !10)
+!10 = !{!11}
+!11 = !DIDerivedType(tag: DW_TAG_member, name: "f", line: 1, size: 32, align: 32, file: !1, scope: !9, baseType: !8)
+!12 = !{i32 2, !"Dwarf Version", i32 2}
+!13 = !{i32 2, !"Debug Info Version", i32 3}
+!14 = !{i32 1, !"PIC Level", i32 2}
+!15 = !{!"clang version 3.6.0 "}
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "s", line: 3, arg: 1, scope: !4, file: !5, type: !9)
+!17 = !DIExpression()
+!18 = !DILocation(line: 3, column: 20, scope: !4)
+!19 = !DILocation(line: 4, column: 2, scope: !4)
diff --git a/test/DebugInfo/X86/sroasplit-4.ll b/test/DebugInfo/X86/sroasplit-4.ll
new file mode 100644
index 000000000000..e9fcdf8eac92
--- /dev/null
+++ b/test/DebugInfo/X86/sroasplit-4.ll
@@ -0,0 +1,146 @@
+; RUN: opt -sroa < %s -S -o - | FileCheck %s
+;
+; Test that recursively splitting an alloca updates the debug info correctly.
+; CHECK: %[[T:.*]] = load i64, i64* @t, align 8
+; CHECK: call void @llvm.dbg.value(metadata i64 %[[T]], i64 0, metadata ![[Y:.*]], metadata ![[P1:.*]])
+; CHECK: %[[T1:.*]] = load i64, i64* @t, align 8
+; CHECK: call void @llvm.dbg.value(metadata i64 %[[T1]], i64 0, metadata ![[Y]], metadata ![[P2:.*]])
+; CHECK: call void @llvm.dbg.value(metadata i64 %[[T]], i64 0, metadata ![[R:.*]], metadata ![[P3:.*]])
+; CHECK: call void @llvm.dbg.value(metadata i64 %[[T1]], i64 0, metadata ![[R]], metadata ![[P4:.*]])
+; CHECK: ![[P1]] = !DIExpression(DW_OP_bit_piece, 0, 64)
+; CHECK: ![[P2]] = !DIExpression(DW_OP_bit_piece, 64, 64)
+; CHECK: ![[P3]] = !DIExpression(DW_OP_bit_piece, 192, 64)
+; CHECK: ![[P4]] = !DIExpression(DW_OP_bit_piece, 256, 64)
+; 
+; struct p {
+;   __SIZE_TYPE__ s;
+;   __SIZE_TYPE__ t;
+; };
+;  
+; struct r {
+;   int i;
+;   struct p x;
+;   struct p y;
+; };
+;  
+; extern int call_me(struct r);
+; extern int maybe();
+; extern __SIZE_TYPE__ t;
+;  
+; int test() {
+;   if (maybe())
+;     return 0;
+;   struct p y = {t, t};
+;   struct r r = {.y = y};
+;   return call_me(r);
+; }
+
+; ModuleID = 'pr22393.cc'
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-darwin"
+
+%struct.p = type { i64, i64 }
+%struct.r = type { i32, %struct.p, %struct.p }
+
+@t = external global i64
+
+; Function Attrs: nounwind
+define i32 @_Z4testv() #0 {
+entry:
+  %retval = alloca i32, align 4
+  %y = alloca %struct.p, align 8
+  %r = alloca %struct.r, align 8
+  %agg.tmp = alloca %struct.r, align 8
+  %call = call i32 @_Z5maybev(), !dbg !24
+  %tobool = icmp ne i32 %call, 0, !dbg !24
+  br i1 %tobool, label %if.then, label %if.end, !dbg !26
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %retval, !dbg !27
+  br label %return, !dbg !27
+
+if.end:                                           ; preds = %entry
+  call void @llvm.dbg.declare(metadata %struct.p* %y, metadata !28, metadata !29), !dbg !30
+  %s = getelementptr inbounds %struct.p, %struct.p* %y, i32 0, i32 0, !dbg !30
+  %0 = load i64, i64* @t, align 8, !dbg !30
+  store i64 %0, i64* %s, align 8, !dbg !30
+  %t = getelementptr inbounds %struct.p, %struct.p* %y, i32 0, i32 1, !dbg !30
+  %1 = load i64, i64* @t, align 8, !dbg !30
+  store i64 %1, i64* %t, align 8, !dbg !30
+  call void @llvm.dbg.declare(metadata %struct.r* %r, metadata !31, metadata !29), !dbg !32
+  %i = getelementptr inbounds %struct.r, %struct.r* %r, i32 0, i32 0, !dbg !32
+  store i32 0, i32* %i, align 4, !dbg !32
+  %x = getelementptr inbounds %struct.r, %struct.r* %r, i32 0, i32 1, !dbg !32
+  %s1 = getelementptr inbounds %struct.p, %struct.p* %x, i32 0, i32 0, !dbg !32
+  store i64 0, i64* %s1, align 8, !dbg !32
+  %t2 = getelementptr inbounds %struct.p, %struct.p* %x, i32 0, i32 1, !dbg !32
+  store i64 0, i64* %t2, align 8, !dbg !32
+  %y3 = getelementptr inbounds %struct.r, %struct.r* %r, i32 0, i32 2, !dbg !32
+  %2 = bitcast %struct.p* %y3 to i8*, !dbg !32
+  %3 = bitcast %struct.p* %y to i8*, !dbg !32
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 16, i32 8, i1 false), !dbg !32
+  %4 = bitcast %struct.r* %agg.tmp to i8*, !dbg !33
+  %5 = bitcast %struct.r* %r to i8*, !dbg !33
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %4, i8* %5, i64 40, i32 8, i1 false), !dbg !33
+  %call4 = call i32 @_Z7call_me1r(%struct.r* byval align 8 %agg.tmp), !dbg !33
+  store i32 %call4, i32* %retval, !dbg !33
+  br label %return, !dbg !33
+
+return:                                           ; preds = %if.end, %if.then
+  %6 = load i32, i32* %retval, !dbg !34
+  ret i32 %6, !dbg !34
+}
+
+declare i32 @_Z5maybev()
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #2
+
+; Function Attrs: nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #3
+
+declare i32 @_Z7call_me1r(%struct.r* byval align 8)
+
+attributes #0 = { nounwind }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!21, !22}
+!llvm.ident = !{!23}
+
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.7.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !16, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<stdin>", directory: "")
+!2 = !{}
+!3 = !{!4, !10}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "p", line: 3, size: 128, align: 64, file: !5, elements: !6, identifier: "_ZTS1p")
+!5 = !DIFile(filename: "pr22393.cc", directory: "")
+!6 = !{!7, !9}
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "s", line: 4, size: 64, align: 64, file: !5, scope: !"_ZTS1p", baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "long unsigned int", size: 64, align: 64, encoding: DW_ATE_unsigned)
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "t", line: 5, size: 64, align: 64, offset: 64, file: !5, scope: !"_ZTS1p", baseType: !8)
+!10 = !DICompositeType(tag: DW_TAG_structure_type, name: "r", line: 8, size: 320, align: 64, file: !5, elements: !11, identifier: "_ZTS1r")
+!11 = !{!12, !14, !15}
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "i", line: 9, size: 32, align: 32, file: !5, scope: !"_ZTS1r", baseType: !13)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!14 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 10, size: 128, align: 64, offset: 64, file: !5, scope: !"_ZTS1r", baseType: !"_ZTS1p")
+!15 = !DIDerivedType(tag: DW_TAG_member, name: "y", line: 11, size: 128, align: 64, offset: 192, file: !5, scope: !"_ZTS1r", baseType: !"_ZTS1p")
+!16 = !{!17}
+!17 = !DISubprogram(name: "test", linkageName: "_Z4testv", line: 18, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 18, file: !5, scope: !18, type: !19, function: i32 ()* @_Z4testv, variables: !2)
+!18 = !DIFile(filename: "pr22393.cc", directory: "")
+!19 = !DISubroutineType(types: !20)
+!20 = !{!13}
+!21 = !{i32 2, !"Dwarf Version", i32 4}
+!22 = !{i32 2, !"Debug Info Version", i32 3}
+!23 = !{!"clang version 3.7.0 "}
+!24 = !DILocation(line: 19, scope: !25)
+!25 = distinct !DILexicalBlock(line: 19, column: 0, file: !5, scope: !17)
+!26 = !DILocation(line: 19, scope: !17)
+!27 = !DILocation(line: 20, scope: !25)
+!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y", line: 21, scope: !17, file: !18, type: !"_ZTS1p")
+!29 = !DIExpression()
+!30 = !DILocation(line: 21, scope: !17)
+!31 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "r", line: 22, scope: !17, file: !18, type: !"_ZTS1r")
+!32 = !DILocation(line: 22, scope: !17)
+!33 = !DILocation(line: 23, scope: !17)
+!34 = !DILocation(line: 24, scope: !17)
diff --git a/test/DebugInfo/X86/sroasplit-5.ll b/test/DebugInfo/X86/sroasplit-5.ll
new file mode 100644
index 000000000000..ce6b4544c56b
--- /dev/null
+++ b/test/DebugInfo/X86/sroasplit-5.ll
@@ -0,0 +1,91 @@
+; RUN: opt %s -sroa -verify -S -o - | FileCheck %s
+; From:
+; struct prog_src_register {
+;   unsigned : 4;       
+;   int Index : 12 + 1; 
+;   unsigned : 12;      
+;   unsigned : 4;       
+;   int : 12 + 1        
+; } src_reg_for_float() {
+;   struct prog_src_register a;
+;   memset(&a, 0, sizeof(a));
+;   int local = a.Index;
+;   return a;
+; }
+; ModuleID = 'pr22495.c'
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; When SROA is creating new smaller allocas, it may add padding.
+;
+; There should be no debug info for the padding.
+; CHECK-NOT: DW_OP_bit_piece, 56
+; CHECK: DIExpression(DW_OP_bit_piece, 32, 24)
+; CHECK-NOT: DW_OP_bit_piece, 56
+; CHECK: DIExpression(DW_OP_bit_piece, 0, 32)
+; CHECK-NOT: DW_OP_bit_piece, 56
+%struct.prog_src_register = type { i32, i24 }
+
+; Function Attrs: nounwind
+define i64 @src_reg_for_float() #0 {
+entry:
+  %retval = alloca %struct.prog_src_register, align 4
+  %a = alloca %struct.prog_src_register, align 4
+  %local = alloca i32, align 4
+  call void @llvm.dbg.declare(metadata %struct.prog_src_register* %a, metadata !16, metadata !17), !dbg !18
+  %0 = bitcast %struct.prog_src_register* %a to i8*, !dbg !19
+  call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 8, i32 4, i1 false), !dbg !19
+  call void @llvm.dbg.declare(metadata i32* %local, metadata !20, metadata !17), !dbg !21
+  %1 = bitcast %struct.prog_src_register* %a to i32*, !dbg !21
+  %bf.load = load i32, i32* %1, align 4, !dbg !21
+  %bf.shl = shl i32 %bf.load, 15, !dbg !21
+  %bf.ashr = ashr i32 %bf.shl, 19, !dbg !21
+  store i32 %bf.ashr, i32* %local, align 4, !dbg !21
+  %2 = bitcast %struct.prog_src_register* %retval to i8*, !dbg !22
+  %3 = bitcast %struct.prog_src_register* %a to i8*, !dbg !22
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 8, i32 4, i1 false), !dbg !22
+  %4 = bitcast %struct.prog_src_register* %retval to i64*, !dbg !22
+  %5 = load i64, i64* %4, align 1, !dbg !22
+  ret i64 %5, !dbg !22
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+; Function Attrs: nounwind
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #2
+
+; Function Attrs: nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #2
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!13, !14}
+!llvm.ident = !{!15}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.7.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<stdin>", directory: "")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "src_reg_for_float", line: 7, isLocal: false, isDefinition: true, isOptimized: false, scopeLine: 7, file: !5, scope: !6, type: !7, function: i64 ()* @src_reg_for_float, variables: !2)
+!5 = !DIFile(filename: "pr22495.c", directory: "")
+!6 = !DIFile(filename: "pr22495.c", directory: "")
+!7 = !DISubroutineType(types: !8)
+!8 = !{!9}
+!9 = !DICompositeType(tag: DW_TAG_structure_type, name: "prog_src_register", line: 1, size: 64, align: 32, file: !5, elements: !10)
+!10 = !{!11}
+!11 = !DIDerivedType(tag: DW_TAG_member, name: "Index", line: 3, size: 13, align: 32, offset: 4, file: !5, scope: !9, baseType: !12)
+!12 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!13 = !{i32 2, !"Dwarf Version", i32 4}
+!14 = !{i32 2, !"Debug Info Version", i32 3}
+!15 = !{!"clang version 3.7.0 "}
+!16 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 8, scope: !4, file: !6, type: !9)
+!17 = !DIExpression()
+!18 = !DILocation(line: 8, scope: !4)
+!19 = !DILocation(line: 9, scope: !4)
+!20 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "local", line: 10, scope: !4, file: !6, type: !12)
+!21 = !DILocation(line: 10, scope: !4)
+!22 = !DILocation(line: 11, scope: !4)
diff --git a/test/DebugInfo/X86/stmt-list-multiple-compile-units.ll b/test/DebugInfo/X86/stmt-list-multiple-compile-units.ll
index 0b2c50ec766d..86a1647d6fa4 100644
--- a/test/DebugInfo/X86/stmt-list-multiple-compile-units.ll
+++ b/test/DebugInfo/X86/stmt-list-multiple-compile-units.ll
@@ -50,18 +50,20 @@
 ; DWARF3-NOT: file_names
 
 ; PR15408
-; ASM: L__DWARF__debug_info_begin0:
-; ASM: Lset3 = Lline_table_start0-Lsection_line ## DW_AT_stmt_list
-; ASM-NEXT: .long   Lset3
-; ASM: L__DWARF__debug_info_begin1:
-; ASM: Lset13 = Lline_table_start0-Lsection_line ## DW_AT_stmt_list
-; ASM-NEXT: .long   Lset13
+; ASM: Lcu_begin0:
+; ASM-NOT: Lcu_begin
+; ASM: Lset[[LT:[0-9]+]] = Lline_table_start0-Lsection_line ## DW_AT_stmt_list
+; ASM-NEXT: .long   Lset[[LT]]
+; ASM: Lcu_begin1:
+; ASM-NOT: Lcu_begin
+; ASM: Lset[[LT:[0-9]+]] = Lline_table_start0-Lsection_line ## DW_AT_stmt_list
+; ASM-NEXT: .long   Lset[[LT]]
 define i32 @test(i32 %a) nounwind uwtable ssp {
 entry:
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !15, metadata !{!"0x102"}), !dbg !16
-  %0 = load i32* %a.addr, align 4, !dbg !17
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !15, metadata !DIExpression()), !dbg !16
+  %0 = load i32, i32* %a.addr, align 4, !dbg !17
   %call = call i32 @fn(i32 %0), !dbg !17
   ret i32 %call, !dbg !17
 }
@@ -72,33 +74,33 @@ define i32 @fn(i32 %a) nounwind uwtable ssp {
 entry:
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !19, metadata !{!"0x102"}), !dbg !20
-  %0 = load i32* %a.addr, align 4, !dbg !21
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !19, metadata !DIExpression()), !dbg !20
+  %0 = load i32, i32* %a.addr, align 4, !dbg !21
   ret i32 %0, !dbg !21
 }
 
 !llvm.dbg.cu = !{!0, !10}
 !llvm.module.flags = !{!25}
-!0 = !{!"0x11\0012\00clang version 3.3\000\00\000\00\001", !23, !1, !1, !3, !1,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.3", isOptimized: false, emissionKind: 1, file: !23, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00test\00test\00\002\000\001\000\006\00256\000\003", !23, !6, !7, null, i32 (i32)* @test, null, null, !1} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 3] [test]
-!6 = !{!"0x29", !23} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "test", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !23, scope: !6, type: !7, function: i32 (i32)* @test, variables: !1)
+!6 = !DIFile(filename: "simple.c", directory: "/private/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"0x11\0012\00clang version 3.3 (trunk 172862)\000\00\000\00\001", !24, !1, !1, !11, !1,  !1} ; [ DW_TAG_compile_unit ]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.3 (trunk 172862)", isOptimized: false, emissionKind: 1, file: !24, enums: !1, retainedTypes: !1, subprograms: !11, globals: !1, imports:  !1)
 !11 = !{!13}
-!13 = !{!"0x2e\00fn\00fn\00\001\000\001\000\006\00256\000\001", !24, !14, !7, null, i32 (i32)* @fn, null, null, !1} ; [ DW_TAG_subprogram ] [line 1] [def] [fn]
-!14 = !{!"0x29", !24} ; [ DW_TAG_file_type ]
-!15 = !{!"0x101\00a\0016777218\000", !5, !6, !9} ; [ DW_TAG_arg_variable ] [a] [line 2]
-!16 = !MDLocation(line: 2, scope: !5)
-!17 = !MDLocation(line: 4, scope: !18)
-!18 = !{!"0xb\003\000\000", !23, !5} ; [ DW_TAG_lexical_block ]
-!19 = !{!"0x101\00a\0016777217\000", !13, !14, !9} ; [ DW_TAG_arg_variable ] [a] [line 1]
-!20 = !MDLocation(line: 1, scope: !13)
-!21 = !MDLocation(line: 2, scope: !22)
-!22 = !{!"0xb\001\000\000", !24, !13} ; [ DW_TAG_lexical_block ]
-!23 = !{!"simple.c", !"/private/tmp"}
-!24 = !{!"simple2.c", !"/private/tmp"}
-!25 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = !DISubprogram(name: "fn", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !24, scope: !14, type: !7, function: i32 (i32)* @fn, variables: !1)
+!14 = !DIFile(filename: "simple2.c", directory: "/private/tmp")
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 2, arg: 1, scope: !5, file: !6, type: !9)
+!16 = !DILocation(line: 2, scope: !5)
+!17 = !DILocation(line: 4, scope: !18)
+!18 = distinct !DILexicalBlock(line: 3, column: 0, file: !23, scope: !5)
+!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 1, arg: 1, scope: !13, file: !14, type: !9)
+!20 = !DILocation(line: 1, scope: !13)
+!21 = !DILocation(line: 2, scope: !22)
+!22 = distinct !DILexicalBlock(line: 1, column: 0, file: !24, scope: !13)
+!23 = !DIFile(filename: "simple.c", directory: "/private/tmp")
+!24 = !DIFile(filename: "simple2.c", directory: "/private/tmp")
+!25 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/stmt-list.ll b/test/DebugInfo/X86/stmt-list.ll
index abd9006ac6c6..1f5189e362a4 100644
--- a/test/DebugInfo/X86/stmt-list.ll
+++ b/test/DebugInfo/X86/stmt-list.ll
@@ -1,10 +1,10 @@
 ; RUN: llc -mtriple x86_64-pc-linux-gnu < %s | FileCheck %s
 
-; CHECK:      .section        .debug_line,"",@progbits
-; CHECK-NEXT: .Lsection_line:
-
 ; CHECK:      .long   .Lline_table_start0          # DW_AT_stmt_list
 
+; CHECK:      .section        .debug_line,"",@progbits
+; CHECK-NEXT: .Lline_table_start0:
+
 define void @f() {
 entry:
   ret void
@@ -14,10 +14,10 @@ entry:
 !llvm.module.flags = !{!7}
 !5 = !{!0}
 
-!0 = !{!"0x2e\00f\00f\00\001\000\001\000\006\00256\001\001", !6, !1, !3, null, void ()* @f, null, null, null} ; [ DW_TAG_subprogram ] [line 1] [def] [f]
-!1 = !{!"0x29", !6} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 3.0 ()\001\00\000\00\000", !6, !4, !4, !5, null, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !6, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "f", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !6, scope: !1, type: !3, function: void ()* @f)
+!1 = !DIFile(filename: "test2.c", directory: "/home/espindola/llvm")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 ()", isOptimized: true, emissionKind: 0, file: !6, enums: !{}, retainedTypes: !{}, subprograms: !5)
+!3 = !DISubroutineType(types: !4)
 !4 = !{null}
-!6 = !{!"test2.c", !"/home/espindola/llvm"}
-!7 = !{i32 1, !"Debug Info Version", i32 2}
+!6 = !DIFile(filename: "test2.c", directory: "/home/espindola/llvm")
+!7 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/stringpool.ll b/test/DebugInfo/X86/stringpool.ll
index 3d5da318ccc8..62b2b1bb55c0 100644
--- a/test/DebugInfo/X86/stringpool.ll
+++ b/test/DebugInfo/X86/stringpool.ll
@@ -6,19 +6,19 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!9}
 
-!0 = !{!"0x11\0012\00clang version 3.1 (trunk 143009)\001\00\000\00\000", !8, !1, !1, !1, !3,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.1 (trunk 143009)", isOptimized: true, emissionKind: 0, file: !8, enums: !1, retainedTypes: !1, subprograms: !1, globals: !3, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x34\00yyyy\00yyyy\00\001\000\001", null, !6, !7, i32* @yyyy, null} ; [ DW_TAG_variable ]
-!6 = !{!"0x29", !8} ; [ DW_TAG_file_type ]
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!8 = !{!"z.c", !"/home/nicholas"}
+!5 = !DIGlobalVariable(name: "yyyy", line: 1, isLocal: false, isDefinition: true, scope: null, file: !6, type: !7, variable: i32* @yyyy)
+!6 = !DIFile(filename: "z.c", directory: "/home/nicholas")
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DIFile(filename: "z.c", directory: "/home/nicholas")
 
 ; Verify that "yyyy" ended up in the stringpool.
 ; LINUX: .section .debug_str,"MS",@progbits,1
 ; LINUX: yyyy
 ; DARWIN: .section __DWARF,__debug_str,regular,debug
-; DARWIN: yyyy
+; DARWIN: .asciz "yyyy" ## string offset=[[YYYY:[0-9]+]]
 
 ; Verify that we refer to 'yyyy' with a relocation.
 ; LINUX:      .long   .Linfo_string3          # DW_AT_name
@@ -30,9 +30,8 @@
 ; LINUX-NEXT: .byte   3
 ; LINUX-NEXT: .quad   yyyy
 
-; Verify that we refer to 'yyyy' without a relocation.
-; DARWIN: Lset[[ID:[0-9]+]] = Linfo_string3-Linfo_string ## DW_AT_name
-; DARWIN-NEXT:        .long   Lset[[ID]]
+; Verify that we refer to 'yyyy' with a direct offset.
+; DARWIN:             .long   [[YYYY]]
 ; DARWIN-NEXT:        .long   {{[0-9]+}}              ## DW_AT_type
 ; DARWIN-NEXT:                                        ## DW_AT_external
 ; DARWIN-NEXT:        .byte   1                       ## DW_AT_decl_file
@@ -40,4 +39,4 @@
 ; DARWIN-NEXT:        .byte   9                       ## DW_AT_location
 ; DARWIN-NEXT:        .byte   3
 ; DARWIN-NEXT:        .quad   _yyyy
-!9 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/struct-loc.ll b/test/DebugInfo/X86/struct-loc.ll
index b2b7e644eae3..2c133b9b66ee 100644
--- a/test/DebugInfo/X86/struct-loc.ll
+++ b/test/DebugInfo/X86/struct-loc.ll
@@ -14,14 +14,14 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!12}
 
-!0 = !{!"0x11\0012\00clang version 3.1 (trunk 152837) (llvm/trunk 152845)\000\00\000\00\000", !11, !1, !1, !1, !3,  !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.1 (trunk 152837) (llvm/trunk 152845)", isOptimized: false, emissionKind: 0, file: !11, enums: !1, retainedTypes: !1, subprograms: !1, globals: !3, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x34\00f\00f\00\005\000\001", null, !6, !7, %struct.foo* @f, null} ; [ DW_TAG_variable ]
-!6 = !{!"0x29", !11} ; [ DW_TAG_file_type ]
-!7 = !{!"0x13\00foo\001\0032\0032\000\000\000", !11, null, null, !8, null, null, null} ; [ DW_TAG_structure_type ] [foo] [line 1, size 32, align 32, offset 0] [def] [from ]
+!5 = !DIGlobalVariable(name: "f", line: 5, isLocal: false, isDefinition: true, scope: null, file: !6, type: !7, variable: %struct.foo* @f)
+!6 = !DIFile(filename: "struct_bug.c", directory: "/Users/echristo/tmp")
+!7 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo", line: 1, size: 32, align: 32, file: !11, elements: !8)
 !8 = !{!9}
-!9 = !{!"0xd\00a\002\0032\0032\000\000", !11, !7, !10} ; [ DW_TAG_member ]
-!10 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!11 = !{!"struct_bug.c", !"/Users/echristo/tmp"}
-!12 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 2, size: 32, align: 32, file: !11, scope: !7, baseType: !10)
+!10 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!11 = !DIFile(filename: "struct_bug.c", directory: "/Users/echristo/tmp")
+!12 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/subrange-type.ll b/test/DebugInfo/X86/subrange-type.ll
index 65d19f2bd442..d83cca6c8776 100644
--- a/test/DebugInfo/X86/subrange-type.ll
+++ b/test/DebugInfo/X86/subrange-type.ll
@@ -12,7 +12,7 @@ entry:
   %retval = alloca i32, align 4
   %i = alloca [2 x i32], align 4
   store i32 0, i32* %retval
-  call void @llvm.dbg.declare(metadata [2 x i32]* %i, metadata !10, metadata !{!"0x102"}), !dbg !15
+  call void @llvm.dbg.declare(metadata [2 x i32]* %i, metadata !10, metadata !DIExpression()), !dbg !15
   ret i32 0, !dbg !16
 }
 
@@ -21,20 +21,20 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!18}
 
-!0 = !{!"0x11\0012\00clang version 3.3 (trunk 171472) (llvm/trunk 171487)\000\00\000\00\000", !17, !1, !1, !3, !1,  !1} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/foo.c] [DW_LANG_C99]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.3 (trunk 171472) (llvm/trunk 171487)", isOptimized: false, emissionKind: 0, file: !17, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00main\00main\00\002\000\001\000\006\00256\000\003", !6, !6, !7, null, i32 ()* @main, null, null, !1} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 3] [main]
-!6 = !{!"0x29", !17} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "main", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !6, scope: !6, type: !7, function: i32 ()* @main, variables: !1)
+!6 = !DIFile(filename: "foo.c", directory: "/usr/local/google/home/echristo/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"0x100\00i\004\000", !11, !6, !12} ; [ DW_TAG_auto_variable ] [i] [line 4]
-!11 = !{!"0xb\003\000\000", !6, !5} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/foo.c]
-!12 = !{!"0x1\00\000\0064\0032\000\000", null, null, !9, !13, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 64, align 32, offset 0] [from int]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 4, scope: !11, file: !6, type: !12)
+!11 = distinct !DILexicalBlock(line: 3, column: 0, file: !6, scope: !5)
+!12 = !DICompositeType(tag: DW_TAG_array_type, size: 64, align: 32, baseType: !9, elements: !13)
 !13 = !{!14}
-!14 = !{!"0x21\000\002"}        ; [ DW_TAG_subrange_type ] [0, 1]
-!15 = !MDLocation(line: 4, scope: !11)
-!16 = !MDLocation(line: 6, scope: !11)
-!17 = !{!"foo.c", !"/usr/local/google/home/echristo/tmp"}
-!18 = !{i32 1, !"Debug Info Version", i32 2}
+!14 = !DISubrange(count: 2)
+!15 = !DILocation(line: 4, scope: !11)
+!16 = !DILocation(line: 6, scope: !11)
+!17 = !DIFile(filename: "foo.c", directory: "/usr/local/google/home/echristo/tmp")
+!18 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/subreg.ll b/test/DebugInfo/X86/subreg.ll
index 2a1de49368ff..b850ce800e37 100644
--- a/test/DebugInfo/X86/subreg.ll
+++ b/test/DebugInfo/X86/subreg.ll
@@ -9,7 +9,7 @@
 
 define i16 @f(i16 signext %zzz) nounwind {
 entry:
-  call void @llvm.dbg.value(metadata i16 %zzz, i64 0, metadata !0, metadata !{!"0x102"})
+  call void @llvm.dbg.value(metadata i16 %zzz, i64 0, metadata !0, metadata !DIExpression()), !dbg !DILocation(scope: !1)
   %conv = sext i16 %zzz to i32, !dbg !7
   %conv1 = trunc i32 %conv to i16
   ret i16 %conv1
@@ -21,14 +21,14 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.module.flags = !{!11}
 !9 = !{!1}
 
-!0 = !{!"0x101\00zzz\0016777219\000", !1, !2, !6} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00f\00f\00\003\000\001\000\006\00256\000\003", !10, !2, !4, null, i16 (i16)* @f, null, null, null} ; [ DW_TAG_subprogram ] [line 3] [def] [f]
-!2 = !{!"0x29", !10} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\0012\00clang version 3.0 ()\000\00\000\00\001", !10, !5, !5, !9, null,  null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !10, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "zzz", line: 3, arg: 1, scope: !1, file: !2, type: !6)
+!1 = !DISubprogram(name: "f", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !10, scope: !2, type: !4, function: i16 (i16)* @f)
+!2 = !DIFile(filename: "/home/espindola/llvm/test.c", directory: "/home/espindola/tmpfs/build")
+!3 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 ()", isOptimized: false, emissionKind: 1, file: !10, enums: !{}, retainedTypes: !{}, subprograms: !9, imports:  null)
+!4 = !DISubroutineType(types: !5)
 !5 = !{null}
-!6 = !{!"0x24\00short\000\0016\0016\000\000\005", null, !3} ; [ DW_TAG_base_type ]
-!7 = !MDLocation(line: 4, column: 22, scope: !8)
-!8 = !{!"0xb\003\0019\000", !10, !1} ; [ DW_TAG_lexical_block ]
-!10 = !{!"/home/espindola/llvm/test.c", !"/home/espindola/tmpfs/build"}
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "short", size: 16, align: 16, encoding: DW_ATE_signed)
+!7 = !DILocation(line: 4, column: 22, scope: !8)
+!8 = distinct !DILexicalBlock(line: 3, column: 19, file: !10, scope: !1)
+!10 = !DIFile(filename: "/home/espindola/llvm/test.c", directory: "/home/espindola/tmpfs/build")
+!11 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/subregisters.ll b/test/DebugInfo/X86/subregisters.ll
index 8e912adbed1c..a4722aa8cd58 100644
--- a/test/DebugInfo/X86/subregisters.ll
+++ b/test/DebugInfo/X86/subregisters.ll
@@ -40,11 +40,11 @@ target triple = "x86_64-apple-macosx10.9.0"
 ; Function Attrs: noinline nounwind ssp uwtable
 define void @doSomething(%struct.bar* nocapture readonly %b) #0 {
 entry:
-  tail call void @llvm.dbg.value(metadata %struct.bar* %b, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !25
-  %a1 = getelementptr inbounds %struct.bar* %b, i64 0, i32 0, !dbg !26
-  %0 = load i32* %a1, align 4, !dbg !26, !tbaa !27
-  tail call void @llvm.dbg.value(metadata i32 %0, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !26
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32 %0) #4, !dbg !32
+  tail call void @llvm.dbg.value(metadata %struct.bar* %b, i64 0, metadata !15, metadata !DIExpression()), !dbg !25
+  %a1 = getelementptr inbounds %struct.bar, %struct.bar* %b, i64 0, i32 0, !dbg !26
+  %0 = load i32, i32* %a1, align 4, !dbg !26, !tbaa !27
+  tail call void @llvm.dbg.value(metadata i32 %0, i64 0, metadata !16, metadata !DIExpression()), !dbg !26
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %0) #4, !dbg !32
   ret void, !dbg !33
 }
 
@@ -59,7 +59,7 @@ define i32 @main() #3 {
 entry:
   %myBar = alloca i64, align 8, !dbg !34
   %tmpcast = bitcast i64* %myBar to %struct.bar*, !dbg !34
-  tail call void @llvm.dbg.declare(metadata %struct.bar* %tmpcast, metadata !21, metadata !{!"0x102"}), !dbg !34
+  tail call void @llvm.dbg.declare(metadata %struct.bar* %tmpcast, metadata !21, metadata !DIExpression()), !dbg !34
   store i64 17179869187, i64* %myBar, align 8, !dbg !34
   call void @doSomething(%struct.bar* %tmpcast), !dbg !35
   ret i32 0, !dbg !36
@@ -78,40 +78,40 @@ attributes #4 = { nounwind }
 !llvm.module.flags = !{!22, !23}
 !llvm.ident = !{!24}
 
-!0 = !{!"0x11\0012\00clang version 3.5 \001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [subregisters.c] [DW_LANG_C99]
-!1 = !{!"subregisters.c", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "subregisters.c", directory: "")
 !2 = !{}
 !3 = !{!4, !17}
-!4 = !{!"0x2e\00doSomething\00doSomething\00\0010\000\001\000\006\00256\001\0011", !1, !5, !6, null, void (%struct.bar*)* @doSomething, null, null, !14} ; [ DW_TAG_subprogram ] [line 10] [def] [scope 11] [doSomething]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [subregisters.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "doSomething", line: 10, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !1, scope: !5, type: !6, function: void (%struct.bar*)* @doSomething, variables: !14)
+!5 = !DIFile(filename: "subregisters.c", directory: "")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null, !8}
-!8 = !{!"0xf\00\000\0064\0064\000\000", null, null, !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from bar]
-!9 = !{!"0x13\00bar\003\0064\0032\000\000\000", !1, null, null, !10, null, null, null} ; [ DW_TAG_structure_type ] [bar] [line 3, size 64, align 32, offset 0] [def] [from ]
+!8 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !9)
+!9 = !DICompositeType(tag: DW_TAG_structure_type, name: "bar", line: 3, size: 64, align: 32, file: !1, elements: !10)
 !10 = !{!11, !13}
-!11 = !{!"0xd\00a\004\0032\0032\000\000", !1, !9, !12} ; [ DW_TAG_member ] [a] [line 4, size 32, align 32, offset 0] [from int]
-!12 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!13 = !{!"0xd\00b\005\0032\0032\0032\000", !1, !9, !12} ; [ DW_TAG_member ] [b] [line 5, size 32, align 32, offset 32] [from int]
+!11 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 4, size: 32, align: 32, file: !1, scope: !9, baseType: !12)
+!12 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!13 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 5, size: 32, align: 32, offset: 32, file: !1, scope: !9, baseType: !12)
 !14 = !{!15, !16}
-!15 = !{!"0x101\00b\0016777226\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [b] [line 10]
-!16 = !{!"0x100\00a\0012\000", !4, !5, !12} ; [ DW_TAG_auto_variable ] [a] [line 12]
-!17 = !{!"0x2e\00main\00main\00\0016\000\001\000\006\000\001\0017", !1, !5, !18, null, i32 ()* @main, null, null, !20} ; [ DW_TAG_subprogram ] [line 16] [def] [scope 17] [main]
-!18 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !19, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 10, arg: 1, scope: !4, file: !5, type: !8)
+!16 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 12, scope: !4, file: !5, type: !12)
+!17 = !DISubprogram(name: "main", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 17, file: !1, scope: !5, type: !18, function: i32 ()* @main, variables: !20)
+!18 = !DISubroutineType(types: !19)
 !19 = !{!12}
 !20 = !{!21}
-!21 = !{!"0x100\00myBar\0018\000", !17, !5, !9} ; [ DW_TAG_auto_variable ] [myBar] [line 18]
+!21 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "myBar", line: 18, scope: !17, file: !5, type: !9)
 !22 = !{i32 2, !"Dwarf Version", i32 2}
-!23 = !{i32 1, !"Debug Info Version", i32 2}
+!23 = !{i32 1, !"Debug Info Version", i32 3}
 !24 = !{!"clang version 3.5 "}
-!25 = !MDLocation(line: 10, scope: !4)
-!26 = !MDLocation(line: 12, scope: !4)
+!25 = !DILocation(line: 10, scope: !4)
+!26 = !DILocation(line: 12, scope: !4)
 !27 = !{!28, !29, i64 0}
 !28 = !{!"bar", !29, i64 0, !29, i64 4}
 !29 = !{!"int", !30, i64 0}
 !30 = !{!"omnipotent char", !31, i64 0}
 !31 = !{!"Simple C/C++ TBAA"}
-!32 = !MDLocation(line: 13, scope: !4)
-!33 = !MDLocation(line: 14, scope: !4)
-!34 = !MDLocation(line: 18, scope: !17)
-!35 = !MDLocation(line: 19, scope: !17)
-!36 = !MDLocation(line: 20, scope: !17)
+!32 = !DILocation(line: 13, scope: !4)
+!33 = !DILocation(line: 14, scope: !4)
+!34 = !DILocation(line: 18, scope: !17)
+!35 = !DILocation(line: 19, scope: !17)
+!36 = !DILocation(line: 20, scope: !17)
diff --git a/test/DebugInfo/X86/template.ll b/test/DebugInfo/X86/template.ll
index 5125b09f91e8..f846b29f5768 100644
--- a/test/DebugInfo/X86/template.ll
+++ b/test/DebugInfo/X86/template.ll
@@ -89,42 +89,42 @@ attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointe
 !llvm.module.flags = !{!33, !34}
 !llvm.ident = !{!35}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 (trunk 224394) (llvm/trunk 224384)\000\00\000\00\001", !1, !2, !3, !9, !30, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/template.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"template.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 (trunk 224394) (llvm/trunk 224384)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !9, globals: !30, imports: !2)
+!1 = !DIFile(filename: "template.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4, !8}
-!4 = !{!"0x13\00y_impl<int>\002\008\008\000\000\000", !1, null, null, !2, null, !5, !"_ZTS6y_implIiE"} ; [ DW_TAG_structure_type ] [y_impl<int>] [line 2, size 8, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "y_impl<int>", line: 2, size: 8, align: 8, file: !1, elements: !2, templateParams: !5, identifier: "_ZTS6y_implIiE")
 !5 = !{!6}
-!6 = !{!"0x2f\00\000\000", null, !7, null}        ; [ DW_TAG_template_type_parameter ]
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!8 = !{!"0x13\00nested\002\008\008\000\000\000", !1, !"_ZTS6y_implIiE", null, !2, null, null, !"_ZTSN6y_implIiE6nestedE"} ; [ DW_TAG_structure_type ] [nested] [line 2, size 8, align 8, offset 0] [def] [from ]
+!6 = !DITemplateTypeParameter(type: !7)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DICompositeType(tag: DW_TAG_structure_type, name: "nested", line: 2, size: 8, align: 8, file: !1, scope: !"_ZTS6y_implIiE", elements: !2, identifier: "_ZTSN6y_implIiE6nestedE")
 !9 = !{!10, !14, !28}
-!10 = !{!"0x2e\00__cxx_global_var_init\00__cxx_global_var_init\00\003\001\001\000\000\00256\000\003", !1, !11, !12, null, void ()* @__cxx_global_var_init, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [local] [def] [__cxx_global_var_init]
-!11 = !{!"0x29", !1}                              ; [ DW_TAG_file_type ] [/tmp/dbginfo/template.cpp]
-!12 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !13, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!10 = !DISubprogram(name: "__cxx_global_var_init", line: 3, isLocal: true, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !11, type: !12, function: void ()* @__cxx_global_var_init, variables: !2)
+!11 = !DIFile(filename: "template.cpp", directory: "/tmp/dbginfo")
+!12 = !DISubroutineType(types: !13)
 !13 = !{null}
-!14 = !{!"0x2e\00func<3, &glbl, y_impl, nullptr, 1, 2>\00func<3, &glbl, y_impl, nullptr, 1, 2>\00_Z4funcILi3EXadL_Z4glblEE6y_implLDn0EJLi1ELi2EEEiv\001\000\001\000\000\00256\000\001", !1, !11, !15, null, i32 ()* @_Z4funcILi3EXadL_Z4glblEE6y_implLDn0EJLi1ELi2EEEiv, !17, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [func<3, &glbl, y_impl, nullptr, 1, 2>]
-!15 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!14 = !DISubprogram(name: "func<3, &glbl, y_impl, nullptr, 1, 2>", linkageName: "_Z4funcILi3EXadL_Z4glblEE6y_implLDn0EJLi1ELi2EEEiv", line: 1, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !11, type: !15, function: i32 ()* @_Z4funcILi3EXadL_Z4glblEE6y_implLDn0EJLi1ELi2EEEiv, templateParams: !17, variables: !2)
+!15 = !DISubroutineType(types: !16)
 !16 = !{!7}
 !17 = !{!18, !19, !21, !22, !24}
-!18 = !{!"0x30\00x\000\000", null, !7, i32 3, null} ; [ DW_TAG_template_value_parameter ]
-!19 = !{!"0x30\00\000\000", null, !20, i32* @glbl, null} ; [ DW_TAG_template_value_parameter ]
-!20 = !{!"0xf\00\000\0064\0064\000\000", null, null, !7} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
-!21 = !{!"0x4106\00y\000\000", null, null, !"y_impl", null} ; [ DW_TAG_GNU_template_template_param ]
-!22 = !{!"0x30\00n\000\000", null, !23, i8 0, null} ; [ DW_TAG_template_value_parameter ]
-!23 = !{!"0x3b\00decltype(nullptr)\000\000\000\000\000\000", null, null} ; [ DW_TAG_unspecified_type ] [decltype(nullptr)] [line 0, size 0, align 0, offset 0]
-!24 = !{!"0x4107\00z\000\000", null, null, !25, null} ; [ DW_TAG_GNU_template_parameter_pack ]
+!18 = !DITemplateValueParameter(tag: DW_TAG_template_value_parameter, name: "x", type: !7, value: i32 3)
+!19 = !DITemplateValueParameter(tag: DW_TAG_template_value_parameter, type: !20, value: i32* @glbl)
+!20 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !7)
+!21 = !DITemplateValueParameter(tag: DW_TAG_GNU_template_template_param, name: "y", type: null, value: !"y_impl")
+!22 = !DITemplateValueParameter(tag: DW_TAG_template_value_parameter, name: "n", type: !23, value: i8 0)
+!23 = !DIBasicType(tag: DW_TAG_unspecified_type, name: "decltype(nullptr)")
+!24 = !DITemplateValueParameter(tag: DW_TAG_GNU_template_parameter_pack, name: "z", type: null, value: !25)
 !25 = !{!26, !27}
-!26 = !{!"0x30\00\000\000", null, !7, i32 1, null} ; [ DW_TAG_template_value_parameter ]
-!27 = !{!"0x30\00\000\000", null, !7, i32 2, null} ; [ DW_TAG_template_value_parameter ]
-!28 = !{!"0x2e\00\00\00_GLOBAL__sub_I_template.cpp\000\001\001\000\000\0064\000\000", !1, !11, !29, null, void ()* @_GLOBAL__sub_I_template.cpp, null, null, !2} ; [ DW_TAG_subprogram ] [line 0] [local] [def]
-!29 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!26 = !DITemplateValueParameter(tag: DW_TAG_template_value_parameter, type: !7, value: i32 1)
+!27 = !DITemplateValueParameter(tag: DW_TAG_template_value_parameter, type: !7, value: i32 2)
+!28 = !DISubprogram(name: "", linkageName: "_GLOBAL__sub_I_template.cpp", isLocal: true, isDefinition: true, flags: DIFlagArtificial, isOptimized: false, file: !1, scope: !11, type: !29, function: void ()* @_GLOBAL__sub_I_template.cpp, variables: !2)
+!29 = !DISubroutineType(types: !2)
 !30 = !{!31, !32}
-!31 = !{!"0x34\00glbl\00glbl\00\003\000\001", null, !11, !7, i32* @glbl, null} ; [ DW_TAG_variable ] [glbl] [line 3] [def]
-!32 = !{!"0x34\00n\00n\00\004\000\001", null, !11, !"_ZTSN6y_implIiE6nestedE", %"struct.y_impl<int>::nested"* @n, null} ; [ DW_TAG_variable ] [n] [line 4] [def]
+!31 = !DIGlobalVariable(name: "glbl", line: 3, isLocal: false, isDefinition: true, scope: null, file: !11, type: !7, variable: i32* @glbl)
+!32 = !DIGlobalVariable(name: "n", line: 4, isLocal: false, isDefinition: true, scope: null, file: !11, type: !"_ZTSN6y_implIiE6nestedE", variable: %"struct.y_impl<int>::nested"* @n)
 !33 = !{i32 2, !"Dwarf Version", i32 4}
-!34 = !{i32 2, !"Debug Info Version", i32 2}
+!34 = !{i32 2, !"Debug Info Version", i32 3}
 !35 = !{!"clang version 3.6.0 (trunk 224394) (llvm/trunk 224384)"}
-!36 = !MDLocation(line: 3, column: 12, scope: !10)
-!37 = !MDLocation(line: 1, column: 96, scope: !14)
-!38 = !MDLocation(line: 0, scope: !28)
+!36 = !DILocation(line: 3, column: 12, scope: !10)
+!37 = !DILocation(line: 1, column: 96, scope: !14)
+!38 = !DILocation(line: 0, scope: !28)
diff --git a/test/DebugInfo/X86/tls.ll b/test/DebugInfo/X86/tls.ll
index 6f673dd378bd..55930f0bacf2 100644
--- a/test/DebugInfo/X86/tls.ll
+++ b/test/DebugInfo/X86/tls.ll
@@ -1,11 +1,20 @@
 ; RUN: llc %s -o - -filetype=asm -O0 -mtriple=x86_64-unknown-linux-gnu \
-; RUN:   | FileCheck --check-prefix=CHECK --check-prefix=SINGLE --check-prefix=SINGLE-64 %s
+; RUN:   | FileCheck --check-prefix=SINGLE --check-prefix=SINGLE-64 --check-prefix=GNUOP %s
 
 ; RUN: llc %s -o - -filetype=asm -O0 -mtriple=i386-linux-gnu \
-; RUN:   | FileCheck --check-prefix=CHECK --check-prefix=SINGLE --check-prefix=SINGLE-32 %s
+; RUN:   | FileCheck --check-prefix=SINGLE --check-prefix=SINGLE-32 --check-prefix=GNUOP %s
 
 ; RUN: llc %s -o - -filetype=asm -O0 -mtriple=x86_64-unknown-linux-gnu -split-dwarf=Enable \
-; RUN:   | FileCheck --check-prefix=CHECK --check-prefix=FISSION %s
+; RUN:   | FileCheck --check-prefix=FISSION --check-prefix=GNUOP %s
+
+; RUN: llc %s -o - -filetype=asm -O0 -mtriple=x86_64-scei-ps4 \
+; RUN:   | FileCheck --check-prefix=SINGLE --check-prefix=SINGLE-64 --check-prefix=STDOP %s
+
+; RUN: llc %s -o - -filetype=asm -O0 -mtriple=x86_64-apple-darwin \
+; RUN:   | FileCheck --check-prefix=DARWIN --check-prefix=STDOP %s
+
+; RUN: llc %s -o - -filetype=asm -O0 -mtriple=x86_64-unknown-freebsd \
+; RUN:   | FileCheck --check-prefix=SINGLE --check-prefix=SINGLE-64 --check-prefix=GNUOP %s
 
 ; FIXME: add relocation and DWARF expression support to llvm-dwarfdump & use
 ; that here instead of raw assembly printing
@@ -19,19 +28,29 @@
 ; FISSION-NEXT: .byte 0
 
 ; SINGLE: .section     .debug_info,
+; DARWIN: .section     {{.*}}debug_info,
+
 ; 10 bytes of data in this DW_FORM_block1 representation of the location of 'tls'
 ; SINGLE-64: .byte     10 # DW_AT_location
 ; DW_OP_const8u (0x0e == 14) of address
 ; SINGLE-64-NEXT: .byte        14
 ; SINGLE-64-NEXT: .quad tls@DTPOFF
 
+; DARWIN: .byte     10 ## DW_AT_location
+; DW_OP_const8u (0x0e == 14) of address
+; DARWIN-NEXT: .byte        14
+; DARWIN-NEXT: .quad _tls
+
+; 6 bytes of data in 32-bit mode
 ; SINGLE-32: .byte     6 # DW_AT_location
 ; DW_OP_const4u (0x0e == 12) of address
 ; SINGLE-32-NEXT: .byte        12
 ; SINGLE-32-NEXT: .long tls@DTPOFF
 
 ; DW_OP_GNU_push_tls_address
-; CHECK-NEXT: .byte 224
+; GNUOP-NEXT: .byte 224
+; DW_OP_form_tls_address
+; STDOP-NEXT: .byte 155
 
 ; FISSION: DW_TAG_variable
 ; FISSION: .byte 2 # DW_AT_location
@@ -49,6 +68,7 @@
 
 ; check that the expected TLS address description is the first thing in the debug_addr section
 ; FISSION: .section    .debug_addr
+; FISSION: addr_sec:
 ; FISSION-NEXT: .quad  tls@DTPOFF
 ; FISSION-NEXT: .quad  glbl
 ; FISSION-NOT: .quad  glbl
@@ -81,22 +101,22 @@ attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointe
 !llvm.module.flags = !{!15, !16}
 !llvm.ident = !{!17}
 
-!0 = !{!"0x11\004\00clang version 3.5 \000\00\000\00-.dwo\000", !1, !2, !2, !3, !12, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/tls.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"tls.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, splitDebugFilename: "-.dwo", emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !12, imports: !2)
+!1 = !DIFile(filename: "tls.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00func<&glbl>\00func<&glbl>\00_Z4funcIXadL_Z4glblEEEiv\005\000\001\000\006\00256\000\005", !1, !5, !6, null, i32 ()* @_Z4funcIXadL_Z4glblEEEiv, !9, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [func<&glbl>]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/tls.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "func<&glbl>", linkageName: "_Z4funcIXadL_Z4glblEEEiv", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, function: i32 ()* @_Z4funcIXadL_Z4glblEEEiv, templateParams: !9, variables: !2)
+!5 = !DIFile(filename: "tls.cpp", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{!10}
-!10 = !{!"0x30\00I\000\000", null, !11, i32* @glbl, null} ; [ DW_TAG_template_value_parameter ]
-!11 = !{!"0xf\00\000\0064\0064\000\000", null, null, !8} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
+!10 = !DITemplateValueParameter(tag: DW_TAG_template_value_parameter, name: "I", type: !11, value: i32* @glbl)
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !8)
 !12 = !{!13, !14}
-!13 = !{!"0x34\00tls\00tls\00\001\000\001", null, !5, !8, i32* @tls, null} ; [ DW_TAG_variable ] [tls] [line 1] [def]
-!14 = !{!"0x34\00glbl\00glbl\00\002\000\001", null, !5, !8, i32* @glbl, null} ; [ DW_TAG_variable ] [glbl] [line 2] [def]
+!13 = !DIGlobalVariable(name: "tls", line: 1, isLocal: false, isDefinition: true, scope: null, file: !5, type: !8, variable: i32* @tls)
+!14 = !DIGlobalVariable(name: "glbl", line: 2, isLocal: false, isDefinition: true, scope: null, file: !5, type: !8, variable: i32* @glbl)
 !15 = !{i32 2, !"Dwarf Version", i32 4}
-!16 = !{i32 1, !"Debug Info Version", i32 2}
+!16 = !{i32 1, !"Debug Info Version", i32 3}
 !17 = !{!"clang version 3.5 "}
-!18 = !MDLocation(line: 6, scope: !4)
+!18 = !DILocation(line: 6, scope: !4)
diff --git a/test/DebugInfo/X86/type_units_with_addresses.ll b/test/DebugInfo/X86/type_units_with_addresses.ll
index 0cd5439042cd..2a8d664e89b8 100644
--- a/test/DebugInfo/X86/type_units_with_addresses.ll
+++ b/test/DebugInfo/X86/type_units_with_addresses.ll
@@ -112,40 +112,40 @@
 !llvm.module.flags = !{!34, !35}
 !llvm.ident = !{!36}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00tu.dwo\001", !1, !2, !3, !2, !27, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/tu.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"tu.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, splitDebugFilename: "tu.dwo", emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !2, globals: !27, imports: !2)
+!1 = !DIFile(filename: "tu.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4, !9, !12, !13, !17, !18, !19, !23, !24}
-!4 = !{!"0x13\00S1<&i>\004\008\008\000\000\000", !1, null, null, !2, null, !5, !"_ZTS2S1IXadL_Z1iEEE"} ; [ DW_TAG_structure_type ] [S1<&i>] [line 4, size 8, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "S1<&i>", line: 4, size: 8, align: 8, file: !1, elements: !2, templateParams: !5, identifier: "_ZTS2S1IXadL_Z1iEEE")
 !5 = !{!6}
-!6 = !{!"0x30\00I\000\000", null, !7, i32* @i, null} ; [ DW_TAG_template_value_parameter ]
-!7 = !{!"0xf\00\000\0064\0064\000\000", null, null, !8} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x13\00S2\0011\008\008\000\000\000", !1, null, null, !10, null, null, !"_ZTS2S2"} ; [ DW_TAG_structure_type ] [S2] [line 11, size 8, align 8, offset 0] [def] [from ]
+!6 = !DITemplateValueParameter(tag: DW_TAG_template_value_parameter, name: "I", type: !7, value: i32* @i)
+!7 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DICompositeType(tag: DW_TAG_structure_type, name: "S2", line: 11, size: 8, align: 8, file: !1, elements: !10, identifier: "_ZTS2S2")
 !10 = !{!11}
-!11 = !{!"0xd\00s2_1\0012\008\008\000\000", !1, !"_ZTS2S2", !"_ZTS4S2_1IXadL_Z1iEEE"} ; [ DW_TAG_member ] [s2_1] [line 12, size 8, align 8, offset 0] [from _ZTS4S2_1IXadL_Z1iEEE]
-!12 = !{!"0x13\00S2_1<&i>\009\008\008\000\000\000", !1, null, null, !2, null, !5, !"_ZTS4S2_1IXadL_Z1iEEE"} ; [ DW_TAG_structure_type ] [S2_1<&i>] [line 9, size 8, align 8, offset 0] [def] [from ]
-!13 = !{!"0x13\00S3\0022\0016\008\000\000\000", !1, null, null, !14, null, null, !"_ZTS2S3"} ; [ DW_TAG_structure_type ] [S3] [line 22, size 16, align 8, offset 0] [def] [from ]
+!11 = !DIDerivedType(tag: DW_TAG_member, name: "s2_1", line: 12, size: 8, align: 8, file: !1, scope: !"_ZTS2S2", baseType: !"_ZTS4S2_1IXadL_Z1iEEE")
+!12 = !DICompositeType(tag: DW_TAG_structure_type, name: "S2_1<&i>", line: 9, size: 8, align: 8, file: !1, elements: !2, templateParams: !5, identifier: "_ZTS4S2_1IXadL_Z1iEEE")
+!13 = !DICompositeType(tag: DW_TAG_structure_type, name: "S3", line: 22, size: 16, align: 8, file: !1, elements: !14, identifier: "_ZTS2S3")
 !14 = !{!15, !16}
-!15 = !{!"0xd\00s3_1\0023\008\008\000\000", !1, !"_ZTS2S3", !"_ZTS4S3_1IXadL_Z1iEEE"} ; [ DW_TAG_member ] [s3_1] [line 23, size 8, align 8, offset 0] [from _ZTS4S3_1IXadL_Z1iEEE]
-!16 = !{!"0xd\00s3_2\0024\008\008\008\000", !1, !"_ZTS2S3", !"_ZTS4S3_2"} ; [ DW_TAG_member ] [s3_2] [line 24, size 8, align 8, offset 8] [from _ZTS4S3_2]
-!17 = !{!"0x13\00S3_1<&i>\0018\008\008\000\000\000", !1, null, null, !2, null, !5, !"_ZTS4S3_1IXadL_Z1iEEE"} ; [ DW_TAG_structure_type ] [S3_1<&i>] [line 18, size 8, align 8, offset 0] [def] [from ]
-!18 = !{!"0x13\00S3_2\0020\008\008\000\000\000", !1, null, null, !2, null, null, !"_ZTS4S3_2"} ; [ DW_TAG_structure_type ] [S3_2] [line 20, size 8, align 8, offset 0] [def] [from ]
-!19 = !{!"0x13\00S4\0034\0016\008\000\000\000", !1, null, null, !20, null, null, !"_ZTS2S4"} ; [ DW_TAG_structure_type ] [S4] [line 34, size 16, align 8, offset 0] [def] [from ]
+!15 = !DIDerivedType(tag: DW_TAG_member, name: "s3_1", line: 23, size: 8, align: 8, file: !1, scope: !"_ZTS2S3", baseType: !"_ZTS4S3_1IXadL_Z1iEEE")
+!16 = !DIDerivedType(tag: DW_TAG_member, name: "s3_2", line: 24, size: 8, align: 8, offset: 8, file: !1, scope: !"_ZTS2S3", baseType: !"_ZTS4S3_2")
+!17 = !DICompositeType(tag: DW_TAG_structure_type, name: "S3_1<&i>", line: 18, size: 8, align: 8, file: !1, elements: !2, templateParams: !5, identifier: "_ZTS4S3_1IXadL_Z1iEEE")
+!18 = !DICompositeType(tag: DW_TAG_structure_type, name: "S3_2", line: 20, size: 8, align: 8, file: !1, elements: !2, identifier: "_ZTS4S3_2")
+!19 = !DICompositeType(tag: DW_TAG_structure_type, name: "S4", line: 34, size: 16, align: 8, file: !1, elements: !20, identifier: "_ZTS2S4")
 !20 = !{!21, !22}
-!21 = !{!"0xd\00s4_1\0035\008\008\000\000", !1, !"_ZTS2S4", !"_ZTS4S4_1"} ; [ DW_TAG_member ] [s4_1] [line 35, size 8, align 8, offset 0] [from _ZTS4S4_1]
-!22 = !{!"0xd\00s4_2\0036\008\008\008\000", !1, !"_ZTS2S4", !"_ZTS4S4_2IXadL_Z1iEEE"} ; [ DW_TAG_member ] [s4_2] [line 36, size 8, align 8, offset 8] [from _ZTS4S4_2IXadL_Z1iEEE]
-!23 = !{!"0x13\00S4_1\0029\008\008\000\000\000", !1, null, null, !2, null, null, !"_ZTS4S4_1"} ; [ DW_TAG_structure_type ] [S4_1] [line 29, size 8, align 8, offset 0] [def] [from ]
-!24 = !{!"0x13\00S4_2<&i>\0032\008\008\000\000\000", !1, null, null, !2, null, !25, !"_ZTS4S4_2IXadL_Z1iEEE"} ; [ DW_TAG_structure_type ] [S4_2<&i>] [line 32, size 8, align 8, offset 0] [def] [from ]
+!21 = !DIDerivedType(tag: DW_TAG_member, name: "s4_1", line: 35, size: 8, align: 8, file: !1, scope: !"_ZTS2S4", baseType: !"_ZTS4S4_1")
+!22 = !DIDerivedType(tag: DW_TAG_member, name: "s4_2", line: 36, size: 8, align: 8, offset: 8, file: !1, scope: !"_ZTS2S4", baseType: !"_ZTS4S4_2IXadL_Z1iEEE")
+!23 = !DICompositeType(tag: DW_TAG_structure_type, name: "S4_1", line: 29, size: 8, align: 8, file: !1, elements: !2, identifier: "_ZTS4S4_1")
+!24 = !DICompositeType(tag: DW_TAG_structure_type, name: "S4_2<&i>", line: 32, size: 8, align: 8, file: !1, elements: !2, templateParams: !25, identifier: "_ZTS4S4_2IXadL_Z1iEEE")
 !25 = !{!26}
-!26 = !{!"0x30\00T\000\000", null, !7, i32* @i, null} ; [ DW_TAG_template_value_parameter ]
+!26 = !DITemplateValueParameter(tag: DW_TAG_template_value_parameter, name: "T", type: !7, value: i32* @i)
 !27 = !{!28, !30, !31, !32, !33}
-!28 = !{!"0x34\00i\00i\00\001\000\001", null, !29, !8, i32* @i, null} ; [ DW_TAG_variable ] [i] [line 1] [def]
-!29 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/tmp/dbginfo/tu.cpp]
-!30 = !{!"0x34\00a\00a\00\006\000\001", null, !29, !"_ZTS2S1IXadL_Z1iEEE", %struct.S1* @a, null} ; [ DW_TAG_variable ] [a] [line 6] [def]
-!31 = !{!"0x34\00s2\00s2\00\0015\000\001", null, !29, !"_ZTS2S2", %struct.S2* @s2, null} ; [ DW_TAG_variable ] [s2] [line 15] [def]
-!32 = !{!"0x34\00s3\00s3\00\0027\000\001", null, !29, !"_ZTS2S3", %struct.S3* @s3, null} ; [ DW_TAG_variable ] [s3] [line 27] [def]
-!33 = !{!"0x34\00s4\00s4\00\0039\000\001", null, !29, !"_ZTS2S4", %struct.S4* @s4, null} ; [ DW_TAG_variable ] [s4] [line 39] [def]
+!28 = !DIGlobalVariable(name: "i", line: 1, isLocal: false, isDefinition: true, scope: null, file: !29, type: !8, variable: i32* @i)
+!29 = !DIFile(filename: "tu.cpp", directory: "/tmp/dbginfo")
+!30 = !DIGlobalVariable(name: "a", line: 6, isLocal: false, isDefinition: true, scope: null, file: !29, type: !"_ZTS2S1IXadL_Z1iEEE", variable: %struct.S1* @a)
+!31 = !DIGlobalVariable(name: "s2", line: 15, isLocal: false, isDefinition: true, scope: null, file: !29, type: !"_ZTS2S2", variable: %struct.S2* @s2)
+!32 = !DIGlobalVariable(name: "s3", line: 27, isLocal: false, isDefinition: true, scope: null, file: !29, type: !"_ZTS2S3", variable: %struct.S3* @s3)
+!33 = !DIGlobalVariable(name: "s4", line: 39, isLocal: false, isDefinition: true, scope: null, file: !29, type: !"_ZTS2S4", variable: %struct.S4* @s4)
 !34 = !{i32 2, !"Dwarf Version", i32 4}
-!35 = !{i32 1, !"Debug Info Version", i32 2}
+!35 = !{i32 1, !"Debug Info Version", i32 3}
 !36 = !{!"clang version 3.5.0 "}
diff --git a/test/DebugInfo/X86/union-const.ll b/test/DebugInfo/X86/union-const.ll
new file mode 100644
index 000000000000..e051c6297b70
--- /dev/null
+++ b/test/DebugInfo/X86/union-const.ll
@@ -0,0 +1,66 @@
+; RUN: llc -filetype=obj < %s | llvm-dwarfdump -debug-dump=info - | FileCheck %s
+; CHECK: DW_TAG_variable
+; CHECK-NEXT: DW_AT_const_value [DW_FORM_udata]	(0)
+; CHECK-NEXT: DW_AT_name {{.*}}"a"
+;
+; ModuleID = 'union.c'
+; generated at -O1 from:
+; union mfi_evt {
+;   struct {
+;     int reserved;
+;   } members;
+; } mfi_aen_setup() {
+;   union mfi_evt a;
+;   a.members.reserved = 0;
+; }
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+%union.mfi_evt = type { %struct.anon }
+%struct.anon = type { i32 }
+
+; Function Attrs: nounwind readnone ssp uwtable
+define i32 @mfi_aen_setup() #0 {
+entry:
+  tail call void @llvm.dbg.declare(metadata %union.mfi_evt* undef, metadata !16, metadata !21), !dbg !22
+  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !16, metadata !21), !dbg !22
+  ret i32 undef, !dbg !23
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
+
+attributes #0 = { nounwind readnone ssp uwtable }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!17, !18, !19}
+!llvm.ident = !{!20}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.7.0 (trunk 226915) (llvm/trunk 226905)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "union.c", directory: "")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "mfi_aen_setup", line: 5, isLocal: false, isDefinition: true, isOptimized: true, scopeLine: 5, file: !1, scope: !5, type: !6, function: i32 ()* @mfi_aen_setup, variables: !15)
+!5 = !DIFile(filename: "union.c", directory: "")
+!6 = !DISubroutineType(types: !7)
+!7 = !{!8}
+!8 = !DICompositeType(tag: DW_TAG_union_type, name: "mfi_evt", line: 1, size: 32, align: 32, file: !1, elements: !9)
+!9 = !{!10}
+!10 = !DIDerivedType(tag: DW_TAG_member, name: "members", line: 4, size: 32, align: 32, file: !1, scope: !8, baseType: !11)
+!11 = !DICompositeType(tag: DW_TAG_structure_type, line: 2, size: 32, align: 32, file: !1, scope: !8, elements: !12)
+!12 = !{!13}
+!13 = !DIDerivedType(tag: DW_TAG_member, name: "reserved", line: 3, size: 32, align: 32, file: !1, scope: !11, baseType: !14)
+!14 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!15 = !{!16}
+!16 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 6, scope: !4, file: !5, type: !8)
+!17 = !{i32 2, !"Dwarf Version", i32 2}
+!18 = !{i32 2, !"Debug Info Version", i32 3}
+!19 = !{i32 1, !"PIC Level", i32 2}
+!20 = !{!"clang version 3.7.0 (trunk 226915) (llvm/trunk 226905)"}
+!21 = !DIExpression()
+!22 = !DILocation(line: 6, column: 17, scope: !4)
+!23 = !DILocation(line: 8, column: 1, scope: !4)
diff --git a/test/DebugInfo/X86/union-template.ll b/test/DebugInfo/X86/union-template.ll
index df070542687b..172dcdcbb9db 100644
--- a/test/DebugInfo/X86/union-template.ll
+++ b/test/DebugInfo/X86/union-template.ll
@@ -16,8 +16,8 @@ entry:
   %value.addr = alloca float, align 4
   %tempValue = alloca %"union.PR15637::Value", align 4
   store float %value, float* %value.addr, align 4
-  call void @llvm.dbg.declare(metadata float* %value.addr, metadata !23, metadata !{!"0x102"}), !dbg !24
-  call void @llvm.dbg.declare(metadata %"union.PR15637::Value"* %tempValue, metadata !25, metadata !{!"0x102"}), !dbg !26
+  call void @llvm.dbg.declare(metadata float* %value.addr, metadata !23, metadata !DIExpression()), !dbg !24
+  call void @llvm.dbg.declare(metadata %"union.PR15637::Value"* %tempValue, metadata !25, metadata !DIExpression()), !dbg !26
   ret void, !dbg !27
 }
 
@@ -29,32 +29,31 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!28}
 
-!0 = !{!"0x11\004\00clang version 3.3 (trunk 178499) (llvm/trunk 178472)\000\00\000\00\000", !1, !2, !2, !3, !9,  !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/foo.cc] [DW_LANG_C_plus_plus]
-!1 = !{!"foo.cc", !"/usr/local/google/home/echristo/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 (trunk 178499) (llvm/trunk 178472)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !9, imports:  !2)
+!1 = !DIFile(filename: "foo.cc", directory: "/usr/local/google/home/echristo/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00g\00g\00_ZN7PR156371gEf\003\000\001\000\006\00256\000\003", !1, !5, !6, null, void (float)* @_ZN7PR156371gEf, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [g]
-!5 = !{!"0x39\00PR15637\001", !1, null} ; [ DW_TAG_namespace ] [PR15637] [line 1]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "g", linkageName: "_ZN7PR156371gEf", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !5, type: !6, function: void (float)* @_ZN7PR156371gEf, variables: !2)
+!5 = !DINamespace(name: "PR15637", line: 1, file: !1, scope: null)
+!6 = !DISubroutineType(types: !7)
 !7 = !{null, !8}
-!8 = !{!"0x24\00float\000\0032\0032\000\000\004", null, null} ; [ DW_TAG_base_type ] [float] [line 0, size 32, align 32, offset 0, enc DW_ATE_float]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float)
 !9 = !{!10}
-!10 = !{!"0x34\00f\00f\00_ZN7PR156371fE\006\000\001", !5, !11, !12, %"union.PR15637::Value"* @_ZN7PR156371fE, null} ; [ DW_TAG_variable ] [f] [line 6] [def]
-!11 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/usr/local/google/home/echristo/tmp/foo.cc]
-!12 = !{!"0x17\00Value<float>\002\0032\0032\000\000\000", !1, !5, null, !13, null, !21, null} ; [ DW_TAG_union_type ] [Value<float>] [line 2, size 32, align 32, offset 0] [def] [from ]
+!10 = !DIGlobalVariable(name: "f", linkageName: "_ZN7PR156371fE", line: 6, isLocal: false, isDefinition: true, scope: !5, file: !11, type: !12, variable: %"union.PR15637::Value"* @_ZN7PR156371fE)
+!11 = !DIFile(filename: "foo.cc", directory: "/usr/local/google/home/echristo/tmp")
+!12 = !DICompositeType(tag: DW_TAG_union_type, name: "Value<float>", line: 2, size: 32, align: 32, file: !1, scope: !5, elements: !13, templateParams: !21)
 !13 = !{!14, !16}
-!14 = !{!"0xd\00a\002\0032\0032\000\000", !1, !12, !15} ; [ DW_TAG_member ] [a] [line 2, size 32, align 32, offset 0] [from int]
-!15 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!16 = !{!"0x2e\00Value\00Value\00\002\000\000\000\006\00320\000\002", !1, !12, !17, null, null, null, i32 0, !20} ; [ DW_TAG_subprogram ] [line 2] [Value]
-!17 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !18, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!14 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 2, size: 32, align: 32, file: !1, scope: !12, baseType: !15)
+!15 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!16 = !DISubprogram(name: "Value", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !12, type: !17)
+!17 = !DISubroutineType(types: !18)
 !18 = !{null, !19}
-!19 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !12} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from Value<float>]
-!20 = !{i32 786468}
+!19 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !12)
 !21 = !{!22}
-!22 = !{!"0x2f\00T\000\000", null, !8, null} ; [ DW_TAG_template_type_parameter ]
-!23 = !{!"0x101\00value\0016777219\000", !4, !11, !8} ; [ DW_TAG_arg_variable ] [value] [line 3]
-!24 = !MDLocation(line: 3, scope: !4)
-!25 = !{!"0x100\00tempValue\004\000", !4, !11, !12} ; [ DW_TAG_auto_variable ] [tempValue] [line 4]
-!26 = !MDLocation(line: 4, scope: !4)
-!27 = !MDLocation(line: 5, scope: !4)
-!28 = !{i32 1, !"Debug Info Version", i32 2}
+!22 = !DITemplateTypeParameter(name: "T", type: !8)
+!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "value", line: 3, arg: 1, scope: !4, file: !11, type: !8)
+!24 = !DILocation(line: 3, scope: !4)
+!25 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "tempValue", line: 4, scope: !4, file: !11, type: !12)
+!26 = !DILocation(line: 4, scope: !4)
+!27 = !DILocation(line: 5, scope: !4)
+!28 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/vector.ll b/test/DebugInfo/X86/vector.ll
index fc17c068caf3..f95ad956dea6 100644
--- a/test/DebugInfo/X86/vector.ll
+++ b/test/DebugInfo/X86/vector.ll
@@ -12,19 +12,19 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!13}
 
-!0 = !{!"0x11\0012\00clang version 3.3 (trunk 171825) (llvm/trunk 171822)\000\00\000\00\000", !12, !1, !1, !1, !3,  !1} ; [ DW_TAG_compile_unit ] [/Users/echristo/foo.c] [DW_LANG_C99]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.3 (trunk 171825) (llvm/trunk 171822)", isOptimized: false, emissionKind: 0, file: !12, enums: !1, retainedTypes: !1, subprograms: !1, globals: !3, imports:  !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x34\00a\00a\00\003\000\001", null, !6, !7, <4 x i32>* @a, null} ; [ DW_TAG_variable ] [a] [line 3] [def]
-!6 = !{!"0x29", !12} ; [ DW_TAG_file_type ]
-!7 = !{!"0x16\00v4si\001\000\000\000\000", !12, null, !8} ; [ DW_TAG_typedef ] [v4si] [line 1, size 0, align 0, offset 0] [from ]
-!8 = !{!"0x1\00\000\00128\00128\000\002048", null, null, !9, !10, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 128, offset 0] [vector] [from int]
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!5 = !DIGlobalVariable(name: "a", line: 3, isLocal: false, isDefinition: true, scope: null, file: !6, type: !7, variable: <4 x i32>* @a)
+!6 = !DIFile(filename: "foo.c", directory: "/Users/echristo")
+!7 = !DIDerivedType(tag: DW_TAG_typedef, name: "v4si", line: 1, file: !12, baseType: !8)
+!8 = !DICompositeType(tag: DW_TAG_array_type, size: 128, align: 128, flags: DIFlagVector, baseType: !9, elements: !10)
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !10 = !{!11}
-!11 = !{!"0x21\000\004"}        ; [ DW_TAG_subrange_type ] [0, 3]
-!12 = !{!"foo.c", !"/Users/echristo"}
+!11 = !DISubrange(count: 4)
+!12 = !DIFile(filename: "foo.c", directory: "/Users/echristo")
 
 ; Check that we get an array type with a vector attribute.
 ; CHECK: DW_TAG_array_type
 ; CHECK-NEXT: DW_AT_GNU_vector
-!13 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/X86/vla.ll b/test/DebugInfo/X86/vla.ll
index b2f2f3d922d0..dfcc5f1cce2a 100644
--- a/test/DebugInfo/X86/vla.ll
+++ b/test/DebugInfo/X86/vla.ll
@@ -27,22 +27,22 @@ entry:
   %saved_stack = alloca i8*
   %cleanup.dest.slot = alloca i32
   store i32 %n, i32* %n.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %n.addr, metadata !15, metadata !{!"0x102"}), !dbg !16
-  %0 = load i32* %n.addr, align 4, !dbg !17
+  call void @llvm.dbg.declare(metadata i32* %n.addr, metadata !15, metadata !DIExpression()), !dbg !16
+  %0 = load i32, i32* %n.addr, align 4, !dbg !17
   %1 = zext i32 %0 to i64, !dbg !17
   %2 = call i8* @llvm.stacksave(), !dbg !17
   store i8* %2, i8** %saved_stack, !dbg !17
   %vla = alloca i32, i64 %1, align 16, !dbg !17
-  call void @llvm.dbg.declare(metadata i32* %vla, metadata !18, metadata !{!"0x102"}), !dbg !17
-  %arrayidx = getelementptr inbounds i32* %vla, i64 0, !dbg !22
+  call void @llvm.dbg.declare(metadata i32* %vla, metadata !18, metadata !DIExpression(DW_OP_deref)), !dbg !17
+  %arrayidx = getelementptr inbounds i32, i32* %vla, i64 0, !dbg !22
   store i32 42, i32* %arrayidx, align 4, !dbg !22
-  %3 = load i32* %n.addr, align 4, !dbg !23
+  %3 = load i32, i32* %n.addr, align 4, !dbg !23
   %sub = sub nsw i32 %3, 1, !dbg !23
   %idxprom = sext i32 %sub to i64, !dbg !23
-  %arrayidx1 = getelementptr inbounds i32* %vla, i64 %idxprom, !dbg !23
-  %4 = load i32* %arrayidx1, align 4, !dbg !23
+  %arrayidx1 = getelementptr inbounds i32, i32* %vla, i64 %idxprom, !dbg !23
+  %4 = load i32, i32* %arrayidx1, align 4, !dbg !23
   store i32 1, i32* %cleanup.dest.slot
-  %5 = load i8** %saved_stack, !dbg !24
+  %5 = load i8*, i8** %saved_stack, !dbg !24
   call void @llvm.stackrestore(i8* %5), !dbg !24
   ret i32 %4, !dbg !23
 }
@@ -64,10 +64,10 @@ entry:
   %argv.addr = alloca i8**, align 8
   store i32 0, i32* %retval
   store i32 %argc, i32* %argc.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %argc.addr, metadata !25, metadata !{!"0x102"}), !dbg !26
+  call void @llvm.dbg.declare(metadata i32* %argc.addr, metadata !25, metadata !DIExpression()), !dbg !26
   store i8** %argv, i8*** %argv.addr, align 8
-  call void @llvm.dbg.declare(metadata i8*** %argv.addr, metadata !27, metadata !{!"0x102"}), !dbg !26
-  %0 = load i32* %argc.addr, align 4, !dbg !28
+  call void @llvm.dbg.declare(metadata i8*** %argv.addr, metadata !27, metadata !DIExpression()), !dbg !26
+  %0 = load i32, i32* %argc.addr, align 4, !dbg !28
   %call = call i32 @vla(i32 %0), !dbg !28
   ret i32 %call, !dbg !28
 }
@@ -75,33 +75,33 @@ entry:
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!29}
 
-!0 = !{!"0x11\0012\00clang version 3.3 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/vla.c] [DW_LANG_C99]
-!1 = !{!"vla.c", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.3 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "vla.c", directory: "")
 !2 = !{}
 !3 = !{!4, !9}
-!4 = !{!"0x2e\00vla\00vla\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, i32 (i32)* @vla, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [vla]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/vla.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "vla", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 (i32)* @vla, variables: !2)
+!5 = !DIFile(filename: "vla.c", directory: "")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x2e\00main\00main\00\007\000\001\000\006\00256\000\007", !1, !5, !10, null, i32 (i32, i8**)* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 7] [def] [main]
-!10 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DISubprogram(name: "main", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !1, scope: !5, type: !10, function: i32 (i32, i8**)* @main, variables: !2)
+!10 = !DISubroutineType(types: !11)
 !11 = !{!8, !8, !12}
-!12 = !{!"0xf\00\000\0064\0064\000\000", null, null, !13} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!13 = !{!"0xf\00\000\0064\0064\000\000", null, null, !14} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char]
-!14 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
-!15 = !{!"0x101\00n\0016777217\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [n] [line 1]
-!16 = !MDLocation(line: 1, scope: !4)
-!17 = !MDLocation(line: 2, scope: !4)
-!18 = !{!"0x100\00a\002\008192", !4, !5, !19} ; [ DW_TAG_auto_variable ] [a] [line 2]
-!19 = !{!"0x1\00\000\000\0032\000\000", null, null, !8, !20, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 0, align 32, offset 0] [from int]
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !13)
+!13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !14)
+!14 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "n", line: 1, arg: 1, scope: !4, file: !5, type: !8)
+!16 = !DILocation(line: 1, scope: !4)
+!17 = !DILocation(line: 2, scope: !4)
+!18 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 2, scope: !4, file: !5, type: !19)
+!19 = !DICompositeType(tag: DW_TAG_array_type, align: 32, baseType: !8, elements: !20)
 !20 = !{!21}
-!21 = !{!"0x21\000\00-1"}       ; [ DW_TAG_subrange_type ] [unbounded]
-!22 = !MDLocation(line: 3, scope: !4)
-!23 = !MDLocation(line: 4, scope: !4)
-!24 = !MDLocation(line: 5, scope: !4)
-!25 = !{!"0x101\00argc\0016777223\000", !9, !5, !8} ; [ DW_TAG_arg_variable ] [argc] [line 7]
-!26 = !MDLocation(line: 7, scope: !9)
-!27 = !{!"0x101\00argv\0033554439\000", !9, !5, !12} ; [ DW_TAG_arg_variable ] [argv] [line 7]
-!28 = !MDLocation(line: 8, scope: !9)
-!29 = !{i32 1, !"Debug Info Version", i32 2}
+!21 = !DISubrange(count: -1)
+!22 = !DILocation(line: 3, scope: !4)
+!23 = !DILocation(line: 4, scope: !4)
+!24 = !DILocation(line: 5, scope: !4)
+!25 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 7, arg: 1, scope: !9, file: !5, type: !8)
+!26 = !DILocation(line: 7, scope: !9)
+!27 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 7, arg: 2, scope: !9, file: !5, type: !12)
+!28 = !DILocation(line: 8, scope: !9)
+!29 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/accel-table-hash-collisions.ll b/test/DebugInfo/accel-table-hash-collisions.ll
new file mode 100644
index 000000000000..5e109a7de5ed
--- /dev/null
+++ b/test/DebugInfo/accel-table-hash-collisions.ll
@@ -0,0 +1,92 @@
+; REQUIRES: object-emission
+; RUN: %llc_dwarf -dwarf-accel-tables=Enable -filetype=obj -o - < %s | llvm-dwarfdump -debug-dump=apple_names - | FileCheck %s
+
+; Generated from the following C code using
+; clang -S -emit-llvm hash-collision.c
+;
+; The names of the variables have been chosen so that they produce hash collisions.
+; There are 12 names here that are hashed to only 6 hashes (each pair of lines
+; hashes to the same value, see the CHECK lines below).
+;
+; int ForceTopDown;
+; int _ZNSt3__116allocator_traitsINS_9allocatorINS_11__tree_nodeINS_12__value_typeIPN4llvm10BasicBlockEPNS4_10RegionNodeEEEPvEEEEE11__constructIS9_JNS_4pairIS6_S8_EEEEEvNS_17integral_constantIbLb1EEERSC_PT_DpOT0_;
+; int _ZN5clang23DataRecursiveASTVisitorIN12_GLOBAL__N_124UnusedBackingIvarCheckerEE26TraverseCUDAKernelCallExprEPNS_18CUDAKernelCallExprE; 
+; int _ZN4llvm16DenseMapIteratorIPNS_10MDLocationENS_6detail13DenseSetEmptyENS_10MDNodeInfoIS1_EENS3_12DenseSetPairIS2_EELb0EE23AdvancePastEmptyBucketsEv;
+; int _ZNK4llvm12LivePhysRegs5printERNS_11raw_ostreamE;
+; int _ZN4llvm15ScalarEvolution14getSignedRangeEPKNS_4SCEVE;
+; int k1;
+; int is;
+; int setStmt;
+; int _ZN4llvm5TwineC1Ei;
+; int _ZNK5clang12OverrideAttr5cloneERNS_10ASTContextE;
+; int _ZN4llvm22MachineModuleInfoMachOD2Ev;
+
+; Check that we have the right amount of hashes.
+; CHECK: Bucket count = 6
+; CHECK: Hashes count = 6
+
+; Check that all the names are present in the output
+; CHECK:  Hash = 0x00597841
+; CHECK:    Name: {{[0-9a-f]*}} "is"
+; CHECK:    Name: {{[0-9a-f]*}} "k1"
+
+; CHECK: Hash = 0xa4b42a1e
+; CHECK:    Name: {{[0-9a-f]*}} "_ZN5clang23DataRecursiveASTVisitorIN12_GLOBAL__N_124UnusedBackingIvarCheckerEE26TraverseCUDAKernelCallExprEPNS_18CUDAKernelCallExprE"
+; CHECK:    Name: {{[0-9a-f]*}} "_ZN4llvm16DenseMapIteratorIPNS_10MDLocationENS_6detail13DenseSetEmptyENS_10MDNodeInfoIS1_EENS3_12DenseSetPairIS2_EELb0EE23AdvancePastEmptyBucketsEv"
+
+; CHECK: Hash = 0xeee7c0b2
+; CHECK:    Name: {{[0-9a-f]*}} "_ZNK4llvm12LivePhysRegs5printERNS_11raw_ostreamE"
+; CHECK:    Name: {{[0-9a-f]*}} "_ZN4llvm15ScalarEvolution14getSignedRangeEPKNS_4SCEVE"
+
+; CHECK: Hash = 0xea48ac5f
+; CHECK:    Name: {{[0-9a-f]*}} "ForceTopDown"
+; CHECK:    Name: {{[0-9a-f]*}} "_ZNSt3__116allocator_traitsINS_9allocatorINS_11__tree_nodeINS_12__value_typeIPN4llvm10BasicBlockEPNS4_10RegionNodeEEEPvEEEEE11__constructIS9_JNS_4pairIS6_S8_EEEEEvNS_17integral_constantIbLb1EEERSC_PT_DpOT0_"
+
+; CHECK:  Hash = 0x6b22f71f
+; CHECK:    Name: {{[0-9a-f]*}} "_ZNK5clang12OverrideAttr5cloneERNS_10ASTContextE"
+; CHECK:    Name: {{[0-9a-f]*}} "_ZN4llvm22MachineModuleInfoMachOD2Ev"
+
+; CHECK:  Hash = 0x8c248979
+; CHECK:    Name: {{[0-9a-f]*}} "setStmt"
+; CHECK:    Name: {{[0-9a-f]*}} "_ZN4llvm5TwineC1Ei"
+
+
+
+@ForceTopDown = common global i32 0, align 4
+@_ZNSt3__116allocator_traitsINS_9allocatorINS_11__tree_nodeINS_12__value_typeIPN4llvm10BasicBlockEPNS4_10RegionNodeEEEPvEEEEE11__constructIS9_JNS_4pairIS6_S8_EEEEEvNS_17integral_constantIbLb1EEERSC_PT_DpOT0_ = common global i32 0, align 4
+@_ZN5clang23DataRecursiveASTVisitorIN12_GLOBAL__N_124UnusedBackingIvarCheckerEE26TraverseCUDAKernelCallExprEPNS_18CUDAKernelCallExprE = common global i32 0, align 4
+@_ZN4llvm16DenseMapIteratorIPNS_10MDLocationENS_6detail13DenseSetEmptyENS_10MDNodeInfoIS1_EENS3_12DenseSetPairIS2_EELb0EE23AdvancePastEmptyBucketsEv = common global i32 0, align 4
+@_ZNK4llvm12LivePhysRegs5printERNS_11raw_ostreamE = common global i32 0, align 4
+@_ZN4llvm15ScalarEvolution14getSignedRangeEPKNS_4SCEVE = common global i32 0, align 4
+@k1 = common global i32 0, align 4
+@is = common global i32 0, align 4
+@setStmt = common global i32 0, align 4
+@_ZN4llvm5TwineC1Ei = common global i32 0, align 4
+@_ZNK5clang12OverrideAttr5cloneERNS_10ASTContextE = common global i32 0, align 4
+@_ZN4llvm22MachineModuleInfoMachOD2Ev = common global i32 0, align 4
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!17, !18, !19}
+!llvm.ident = !{!20}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 231548) (llvm/trunk 231547)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3, imports: !2)
+!1 = !DIFile(filename: "hash-collisions.c", directory: "/tmp")
+!2 = !{}
+!3 = !{!4, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15, !16}
+!4 = !DIGlobalVariable(name: "ForceTopDown", scope: !0, file: !1, line: 1, type: !5, isLocal: false, isDefinition: true, variable: i32* @ForceTopDown)
+!5 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DIGlobalVariable(name: "_ZNSt3__116allocator_traitsINS_9allocatorINS_11__tree_nodeINS_12__value_typeIPN4llvm10BasicBlockEPNS4_10RegionNodeEEEPvEEEEE11__constructIS9_JNS_4pairIS6_S8_EEEEEvNS_17integral_constantIbLb1EEERSC_PT_DpOT0_", scope: !0, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, variable: i32* @_ZNSt3__116allocator_traitsINS_9allocatorINS_11__tree_nodeINS_12__value_typeIPN4llvm10BasicBlockEPNS4_10RegionNodeEEEPvEEEEE11__constructIS9_JNS_4pairIS6_S8_EEEEEvNS_17integral_constantIbLb1EEERSC_PT_DpOT0_)
+!7 = !DIGlobalVariable(name: "_ZN5clang23DataRecursiveASTVisitorIN12_GLOBAL__N_124UnusedBackingIvarCheckerEE26TraverseCUDAKernelCallExprEPNS_18CUDAKernelCallExprE", scope: !0, file: !1, line: 3, type: !5, isLocal: false, isDefinition: true, variable: i32* @_ZN5clang23DataRecursiveASTVisitorIN12_GLOBAL__N_124UnusedBackingIvarCheckerEE26TraverseCUDAKernelCallExprEPNS_18CUDAKernelCallExprE)
+!8 = !DIGlobalVariable(name: "_ZN4llvm16DenseMapIteratorIPNS_10MDLocationENS_6detail13DenseSetEmptyENS_10MDNodeInfoIS1_EENS3_12DenseSetPairIS2_EELb0EE23AdvancePastEmptyBucketsEv", scope: !0, file: !1, line: 4, type: !5, isLocal: false, isDefinition: true, variable: i32* @_ZN4llvm16DenseMapIteratorIPNS_10MDLocationENS_6detail13DenseSetEmptyENS_10MDNodeInfoIS1_EENS3_12DenseSetPairIS2_EELb0EE23AdvancePastEmptyBucketsEv)
+!9 = !DIGlobalVariable(name: "_ZNK4llvm12LivePhysRegs5printERNS_11raw_ostreamE", scope: !0, file: !1, line: 5, type: !5, isLocal: false, isDefinition: true, variable: i32* @_ZNK4llvm12LivePhysRegs5printERNS_11raw_ostreamE)
+!10 = !DIGlobalVariable(name: "_ZN4llvm15ScalarEvolution14getSignedRangeEPKNS_4SCEVE", scope: !0, file: !1, line: 6, type: !5, isLocal: false, isDefinition: true, variable: i32* @_ZN4llvm15ScalarEvolution14getSignedRangeEPKNS_4SCEVE)
+!11 = !DIGlobalVariable(name: "k1", scope: !0, file: !1, line: 7, type: !5, isLocal: false, isDefinition: true, variable: i32* @k1)
+!12 = !DIGlobalVariable(name: "is", scope: !0, file: !1, line: 8, type: !5, isLocal: false, isDefinition: true, variable: i32* @is)
+!13 = !DIGlobalVariable(name: "setStmt", scope: !0, file: !1, line: 9, type: !5, isLocal: false, isDefinition: true, variable: i32* @setStmt)
+!14 = !DIGlobalVariable(name: "_ZN4llvm5TwineC1Ei", scope: !0, file: !1, line: 10, type: !5, isLocal: false, isDefinition: true, variable: i32* @_ZN4llvm5TwineC1Ei)
+!15 = !DIGlobalVariable(name: "_ZNK5clang12OverrideAttr5cloneERNS_10ASTContextE", scope: !0, file: !1, line: 11, type: !5, isLocal: false, isDefinition: true, variable: i32* @_ZNK5clang12OverrideAttr5cloneERNS_10ASTContextE)
+!16 = !DIGlobalVariable(name: "_ZN4llvm22MachineModuleInfoMachOD2Ev", scope: !0, file: !1, line: 12, type: !5, isLocal: false, isDefinition: true, variable: i32* @_ZN4llvm22MachineModuleInfoMachOD2Ev)
+!17 = !{i32 2, !"Dwarf Version", i32 2}
+!18 = !{i32 2, !"Debug Info Version", i32 3}
+!19 = !{i32 1, !"PIC Level", i32 2}
+!20 = !{!"clang version 3.7.0 (trunk 231548) (llvm/trunk 231547)"}
diff --git a/test/DebugInfo/array.ll b/test/DebugInfo/array.ll
index 4439571e7074..f6c79f77c6f2 100644
--- a/test/DebugInfo/array.ll
+++ b/test/DebugInfo/array.ll
@@ -6,7 +6,7 @@ entry:
   %retval = alloca i32, align 4
   %a = alloca [0 x i32], align 4
   store i32 0, i32* %retval
-  call void @llvm.dbg.declare(metadata [0 x i32]* %a, metadata !6, metadata !{!"0x102"}), !dbg !11
+  call void @llvm.dbg.declare(metadata [0 x i32]* %a, metadata !6, metadata !DIExpression()), !dbg !11
   ret i32 0, !dbg !12
 }
 
@@ -15,25 +15,26 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!16}
 
-!0 = !{!"0x2e\00main\00main\00\003\000\001\000\006\000\000\003", !14, !1, !3, null, i32 ()* @main, null, null, null} ; [ DW_TAG_subprogram ] [line 3] [def] [main]
-!1 = !{!"0x29", !14} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 3.0 (trunk 129138)\000\00\000\00\000", !14, !15, !15, !13, null,  null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !14, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "main", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 3, file: !14, scope: !1, type: !3, function: i32 ()* @main)
+!1 = !DIFile(filename: "array.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129138)", isOptimized: false, emissionKind: 0, file: !14, enums: !15, retainedTypes: !15, subprograms: !13, imports:  null)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ]
-!6 = !{!"0x100\00a\004\000", !7, !1, !8} ; [ DW_TAG_auto_variable ]
-!7 = !{!"0xb\003\0012\000", !14, !0} ; [ DW_TAG_lexical_block ]
-!8 = !{!"0x1\00\000\000\0032\000\000", !14, !2, !5, !9, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 0, align 32, offset 0] [from int]
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 4, scope: !7, file: !1, type: !8)
+!7 = distinct !DILexicalBlock(line: 3, column: 12, file: !14, scope: !0)
+!8 = !DICompositeType(tag: DW_TAG_array_type, align: 32, file: !14, scope: !2, baseType: !5, elements: !9)
 !9 = !{!10}
+;CHECK: section_info:
 ;CHECK: DW_TAG_subrange_type
 ;CHECK-NEXT: DW_AT_type
 ;CHECK-NOT: DW_AT_lower_bound
 ;CHECK-NOT: DW_AT_upper_bound
 ;CHECK-NEXT: End Of Children Mark
-!10 = !{!"0x21\000\00-1"}        ; [ DW_TAG_subrange_type ]
-!11 = !MDLocation(line: 4, column: 7, scope: !7)
-!12 = !MDLocation(line: 5, column: 3, scope: !7)
+!10 = !DISubrange(count: -1)
+!11 = !DILocation(line: 4, column: 7, scope: !7)
+!12 = !DILocation(line: 5, column: 3, scope: !7)
 !13 = !{!0}
-!14 = !{!"array.c", !"/private/tmp"}
-!15 = !{i32 0}
-!16 = !{i32 1, !"Debug Info Version", i32 2}
+!14 = !DIFile(filename: "array.c", directory: "/private/tmp")
+!15 = !{}
+!16 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/block-asan.ll b/test/DebugInfo/block-asan.ll
index b25aee1b5ce4..393816b34857 100644
--- a/test/DebugInfo/block-asan.ll
+++ b/test/DebugInfo/block-asan.ll
@@ -13,7 +13,7 @@
 
 ; Check that the location of the ASAN instrumented __block variable is
 ; correct.
-; CHECK: [ DW_TAG_expression ] [DW_OP_deref] [DW_OP_plus 8] [DW_OP_deref] [DW_OP_plus 24]
+; CHECK: !DIExpression(DW_OP_deref, DW_OP_plus, 8, DW_OP_deref, DW_OP_plus, 24)
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 
@@ -24,18 +24,18 @@ define void @foo() #0 {
 entry:
   %x = alloca %struct.__block_byref_x, align 8
   call void @llvm.dbg.declare(metadata %struct.__block_byref_x* %x, metadata !12, metadata !22), !dbg !23
-  %byref.isa = getelementptr inbounds %struct.__block_byref_x* %x, i32 0, i32 0, !dbg !24
+  %byref.isa = getelementptr inbounds %struct.__block_byref_x, %struct.__block_byref_x* %x, i32 0, i32 0, !dbg !24
   store i8* null, i8** %byref.isa, !dbg !24
-  %byref.forwarding = getelementptr inbounds %struct.__block_byref_x* %x, i32 0, i32 1, !dbg !24
+  %byref.forwarding = getelementptr inbounds %struct.__block_byref_x, %struct.__block_byref_x* %x, i32 0, i32 1, !dbg !24
   store %struct.__block_byref_x* %x, %struct.__block_byref_x** %byref.forwarding, !dbg !24
-  %byref.flags = getelementptr inbounds %struct.__block_byref_x* %x, i32 0, i32 2, !dbg !24
+  %byref.flags = getelementptr inbounds %struct.__block_byref_x, %struct.__block_byref_x* %x, i32 0, i32 2, !dbg !24
   store i32 0, i32* %byref.flags, !dbg !24
-  %byref.size = getelementptr inbounds %struct.__block_byref_x* %x, i32 0, i32 3, !dbg !24
+  %byref.size = getelementptr inbounds %struct.__block_byref_x, %struct.__block_byref_x* %x, i32 0, i32 3, !dbg !24
   store i32 32, i32* %byref.size, !dbg !24
-  %forwarding = getelementptr inbounds %struct.__block_byref_x* %x, i32 0, i32 1, !dbg !25
-  %0 = load %struct.__block_byref_x** %forwarding, !dbg !25
-  %x1 = getelementptr inbounds %struct.__block_byref_x* %0, i32 0, i32 4, !dbg !25
-  %1 = load i32* %x1, align 4, !dbg !25
+  %forwarding = getelementptr inbounds %struct.__block_byref_x, %struct.__block_byref_x* %x, i32 0, i32 1, !dbg !25
+  %0 = load %struct.__block_byref_x*, %struct.__block_byref_x** %forwarding, !dbg !25
+  %x1 = getelementptr inbounds %struct.__block_byref_x, %struct.__block_byref_x* %0, i32 0, i32 4, !dbg !25
+  %1 = load i32, i32* %x1, align 4, !dbg !25
   call void @bar(i32 %1), !dbg !25
   %2 = bitcast %struct.__block_byref_x* %x to i8*, !dbg !26
   call void @_Block_object_dispose(i8* %2, i32 8) #3, !dbg !26
@@ -58,30 +58,30 @@ attributes #3 = { nounwind }
 !llvm.module.flags = !{!8, !9, !10}
 !llvm.ident = !{!11}
 
-!0 = !{!"0x11\0012\00clang version 3.6.0 (trunk 223120) (llvm/trunk 223119)\000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/block.c] [DW_LANG_C99]
-!1 = !{!"block.c", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.6.0 (trunk 223120) (llvm/trunk 223119)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "block.c", directory: "/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\003\000\001\000\000\000\000\003", !1, !5, !6, null, void ()* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [foo]
-!5 = !{!"0x29", !1}    ; [ DW_TAG_file_type ] [/tmp/block.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 3, isLocal: false, isDefinition: true, isOptimized: false, scopeLine: 3, file: !1, scope: !5, type: !6, function: void ()* @foo, variables: !2)
+!5 = !DIFile(filename: "block.c", directory: "/tmp")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
 !8 = !{i32 2, !"Dwarf Version", i32 2}
-!9 = !{i32 2, !"Debug Info Version", i32 2}
+!9 = !{i32 2, !"Debug Info Version", i32 3}
 !10 = !{i32 1, !"PIC Level", i32 2}
 !11 = !{!"clang version 3.6.0 (trunk 223120) (llvm/trunk 223119)"}
-!12 = !{!"0x100\00x\004\000", !4, !5, !13} ; [ DW_TAG_auto_variable ] [x] [line 4]
-!13 = !{!"0x13\00\000\00224\000\000\0016\000", !1, !5, null, !14, null, null, null} ; [ DW_TAG_structure_type ] [line 0, size 224, align 0, offset 0] [def] [from ]
+!12 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 4, scope: !4, file: !5, type: !13)
+!13 = !DICompositeType(tag: DW_TAG_structure_type, size: 224, flags: DIFlagBlockByrefStruct, file: !1, scope: !5, elements: !14)
 !14 = !{!15, !17, !18, !20, !21}
-!15 = !{!"0xd\00__isa\000\0064\0064\000\000", !1, !5, !16} ; [ DW_TAG_member ] [__isa] [line 0, size 64, align 64, offset 0] [from ]
-!16 = !{!"0xf\00\000\0064\0064\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!17 = !{!"0xd\00__forwarding\000\0064\0064\0064\000", !1, !5, !16} ; [ DW_TAG_member ] [__forwarding] [line 0, size 64, align 64, offset 64] [from ]
-!18 = !{!"0xd\00__flags\000\0032\0032\00128\000", !1, !5, !19} ; [ DW_TAG_member ] [__flags] [line 0, size 32, align 32, offset 128] [from int]
-!19 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!20 = !{!"0xd\00__size\000\0032\0032\00160\000", !1, !5, !19} ; [ DW_TAG_member ] [__size] [line 0, size 32, align 32, offset 160] [from int]
-!21 = !{!"0xd\00x\000\0032\0032\00192\000", !1, !5, !19} ; [ DW_TAG_member ] [x] [line 0, size 32, align 32, offset 192] [from int]
-!22 = !{!"0x102\0034\008\006\0034\0024"} ; [ DW_TAG_expression ] [DW_OP_plus 8] [DW_OP_deref] [DW_OP_plus 24]
-!23 = !MDLocation(line: 4, column: 15, scope: !4)
-!24 = !MDLocation(line: 4, column: 3, scope: !4)
-!25 = !MDLocation(line: 5, column: 3, scope: !4)
-!26 = !MDLocation(line: 6, column: 1, scope: !4)
+!15 = !DIDerivedType(tag: DW_TAG_member, name: "__isa", size: 64, align: 64, file: !1, scope: !5, baseType: !16)
+!16 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: null)
+!17 = !DIDerivedType(tag: DW_TAG_member, name: "__forwarding", size: 64, align: 64, offset: 64, file: !1, scope: !5, baseType: !16)
+!18 = !DIDerivedType(tag: DW_TAG_member, name: "__flags", size: 32, align: 32, offset: 128, file: !1, scope: !5, baseType: !19)
+!19 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!20 = !DIDerivedType(tag: DW_TAG_member, name: "__size", size: 32, align: 32, offset: 160, file: !1, scope: !5, baseType: !19)
+!21 = !DIDerivedType(tag: DW_TAG_member, name: "x", size: 32, align: 32, offset: 192, file: !1, scope: !5, baseType: !19)
+!22 = !DIExpression(DW_OP_plus, 8, DW_OP_deref, DW_OP_plus, 24)
+!23 = !DILocation(line: 4, column: 15, scope: !4)
+!24 = !DILocation(line: 4, column: 3, scope: !4)
+!25 = !DILocation(line: 5, column: 3, scope: !4)
+!26 = !DILocation(line: 6, column: 1, scope: !4)
diff --git a/test/DebugInfo/bug_null_debuginfo.ll b/test/DebugInfo/bug_null_debuginfo.ll
index 784f17ef61f2..5aaa3834a5f1 100644
--- a/test/DebugInfo/bug_null_debuginfo.ll
+++ b/test/DebugInfo/bug_null_debuginfo.ll
@@ -3,6 +3,6 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!2}
 
-!0 = !{!"0x11\0012\00\000\00\000\00\000", !1, null, null, null,  null, null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"t", !""}
-!2 = !{i32 1, !"Debug Info Version", i32 2}
+!0 = !DICompileUnit(language: DW_LANG_C99, isOptimized: false, emissionKind: 0, file: !1, globals:  null)
+!1 = !DIFile(filename: "t", directory: "")
+!2 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/constant-pointers.ll b/test/DebugInfo/constant-pointers.ll
index add97801b6f6..8e0a242f1bad 100644
--- a/test/DebugInfo/constant-pointers.ll
+++ b/test/DebugInfo/constant-pointers.ll
@@ -30,22 +30,22 @@ attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointe
 !llvm.module.flags = !{!15, !16}
 !llvm.ident = !{!17}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/constant-pointers.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"constant-pointers.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "constant-pointers.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00func<nullptr, nullptr, 42>\00func<nullptr, nullptr, 42>\00_Z4funcILPv0ELPFvvE0ELi42EEvv\002\000\001\000\006\00256\000\002", !1, !5, !6, null, void ()* @_Z4funcILPv0ELPFvvE0ELi42EEvv, !8, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [func<nullptr, nullptr, 42>]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/constant-pointers.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "func<nullptr, nullptr, 42>", linkageName: "_Z4funcILPv0ELPFvvE0ELi42EEvv", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !6, function: void ()* @_Z4funcILPv0ELPFvvE0ELi42EEvv, templateParams: !8, variables: !2)
+!5 = !DIFile(filename: "constant-pointers.cpp", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
 !8 = !{!9, !11, !13}
-!9 = !{!"0x30\00V\000\000", null, !10, i8 0, null} ; [ DW_TAG_template_value_parameter ]
-!10 = !{!"0xf\00\000\0064\0064\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!11 = !{!"0x30\00F\000\000", null, !12, i8 0, null} ; [ DW_TAG_template_value_parameter ]
-!12 = !{!"0xf\00\000\0064\0064\000\000", null, null, !6} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!13 = !{!"0x30\00i\000\000", null, !14, i32 42, null} ; [ DW_TAG_template_value_parameter ]
-!14 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = !DITemplateValueParameter(tag: DW_TAG_template_value_parameter, name: "V", type: !10, value: i8 0)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: null)
+!11 = !DITemplateValueParameter(tag: DW_TAG_template_value_parameter, name: "F", type: !12, value: i8 0)
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !6)
+!13 = !DITemplateValueParameter(tag: DW_TAG_template_value_parameter, name: "i", type: !14, value: i32 42)
+!14 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !15 = !{i32 2, !"Dwarf Version", i32 4}
-!16 = !{i32 2, !"Debug Info Version", i32 2}
+!16 = !{i32 2, !"Debug Info Version", i32 3}
 !17 = !{!"clang version 3.5.0 "}
-!18 = !MDLocation(line: 3, scope: !4)
+!18 = !DILocation(line: 3, scope: !4)
diff --git a/test/DebugInfo/constant-sdnodes-have-dbg-location.ll b/test/DebugInfo/constant-sdnodes-have-dbg-location.ll
new file mode 100644
index 000000000000..1f502a2a262a
--- /dev/null
+++ b/test/DebugInfo/constant-sdnodes-have-dbg-location.ll
@@ -0,0 +1,26 @@
+; RUN: llc -debug < %s 2>&1 | FileCheck %s
+; REQUIRES: asserts
+
+; CHECK: 0x{{[0-9,a-f]+}}: i32 = Constant<-1>test.c:4:5
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  ret i32 -1, !dbg !10
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!8, !9}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, subprograms: !3)
+!1 = !DIFile(filename: "test.c", directory: "/home/user/clang-llvm/build")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "main", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: false, function: i32 ()* @main, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{!7}
+!7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !{i32 2, !"Dwarf Version", i32 4}
+!9 = !{i32 2, !"Debug Info Version", i32 3}
+!10 = !DILocation(line: 4, column: 5, scope: !4)
diff --git a/test/DebugInfo/constantfp-sdnodes-have-dbg-location.ll b/test/DebugInfo/constantfp-sdnodes-have-dbg-location.ll
new file mode 100644
index 000000000000..2f7ecd8b061e
--- /dev/null
+++ b/test/DebugInfo/constantfp-sdnodes-have-dbg-location.ll
@@ -0,0 +1,24 @@
+; RUN: llc -debug < %s 2>&1 | FileCheck %s
+; REQUIRES: asserts
+
+; CHECK: 0x{{[0-9,a-f]+}}: f64 = ConstantFP<1.500000e+00>test.c:3:5
+
+define double @f() {
+entry:
+  ret double 1.500000e+00, !dbg !10
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!8, !9}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, subprograms: !3)
+!1 = !DIFile(filename: "test.c", directory: "/home/user/clang-llvm/build")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "f", scope: !1, file: !1, line: 1, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: false, function: double ()* @f, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{!7}
+!7 = !DIBasicType(name: "double", size: 64, align: 64, encoding: DW_ATE_float)
+!8 = !{i32 2, !"Dwarf Version", i32 4}
+!9 = !{i32 2, !"Debug Info Version", i32 3}
+!10 = !DILocation(line: 3, column: 5, scope: !4)
diff --git a/test/DebugInfo/cross-cu-inlining.ll b/test/DebugInfo/cross-cu-inlining.ll
index fafa3fa4e8f6..436bdda6473b 100644
--- a/test/DebugInfo/cross-cu-inlining.ll
+++ b/test/DebugInfo/cross-cu-inlining.ll
@@ -71,12 +71,12 @@ entry:
   %x.addr.i = alloca i32, align 4
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
-  %0 = load i32* @i, align 4, !dbg !19
+  %0 = load i32, i32* @i, align 4, !dbg !19
   %1 = bitcast i32* %x.addr.i to i8*
   call void @llvm.lifetime.start(i64 4, i8* %1)
   store i32 %0, i32* %x.addr.i, align 4
-  call void @llvm.dbg.declare(metadata i32* %x.addr.i, metadata !20, metadata !{!"0x102"}), !dbg !21
-  %2 = load i32* %x.addr.i, align 4, !dbg !22
+  call void @llvm.dbg.declare(metadata i32* %x.addr.i, metadata !120, metadata !DIExpression()), !dbg !21
+  %2 = load i32, i32* %x.addr.i, align 4, !dbg !22
   %mul.i = mul nsw i32 %2, 2, !dbg !22
   %3 = bitcast i32* %x.addr.i to i8*, !dbg !22
   call void @llvm.lifetime.end(i64 4, i8* %3), !dbg !22
@@ -88,8 +88,8 @@ define i32 @_Z4funci(i32 %x) #1 {
 entry:
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !20, metadata !{!"0x102"}), !dbg !23
-  %0 = load i32* %x.addr, align 4, !dbg !24
+  call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !20, metadata !DIExpression()), !dbg !23
+  %0 = load i32, i32* %x.addr, align 4, !dbg !24
   %mul = mul nsw i32 %0, 2, !dbg !24
   ret i32 %mul, !dbg !24
 }
@@ -112,29 +112,32 @@ attributes #3 = { nounwind }
 !llvm.module.flags = !{!16, !17}
 !llvm.ident = !{!18, !18}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/a.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"a.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "a.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00main\00main\00\003\000\001\000\006\00256\000\003", !1, !5, !6, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [main]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/a.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "main", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !5, type: !6, function: i32 ()* @main, variables: !2)
+!5 = !DIFile(filename: "a.cpp", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !10, !2, !2, !11, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/b.cpp] [DW_LANG_C_plus_plus]
-!10 = !{!"b.cpp", !"/tmp/dbginfo"}
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !10, enums: !2, retainedTypes: !2, subprograms: !11, globals: !2, imports: !2)
+!10 = !DIFile(filename: "b.cpp", directory: "/tmp/dbginfo")
 !11 = !{!12}
-!12 = !{!"0x2e\00func\00func\00_Z4funci\001\000\001\000\006\00256\000\001", !10, !13, !14, null, i32 (i32)* @_Z4funci, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [func]
-!13 = !{!"0x29", !10}        ; [ DW_TAG_file_type ] [/tmp/dbginfo/b.cpp]
-!14 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !15, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = !DISubprogram(name: "func", linkageName: "_Z4funci", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !10, scope: !13, type: !14, function: i32 (i32)* @_Z4funci, variables: !2)
+!13 = !DIFile(filename: "b.cpp", directory: "/tmp/dbginfo")
+!14 = !DISubroutineType(types: !15)
 !15 = !{!8, !8}
 !16 = !{i32 2, !"Dwarf Version", i32 4}
-!17 = !{i32 2, !"Debug Info Version", i32 2}
+!17 = !{i32 2, !"Debug Info Version", i32 3}
 !18 = !{!"clang version 3.5.0 "}
-!19 = !MDLocation(line: 4, scope: !4)
-!20 = !{!"0x101\00x\0016777217\000", !12, !13, !8} ; [ DW_TAG_arg_variable ] [x] [line 1]
-!21 = !MDLocation(line: 1, scope: !12, inlinedAt: !19)
-!22 = !MDLocation(line: 2, scope: !12, inlinedAt: !19)
-!23 = !MDLocation(line: 1, scope: !12)
-!24 = !MDLocation(line: 2, scope: !12)
+!19 = !DILocation(line: 4, scope: !4)
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 1, arg: 1, scope: !12, file: !13, type: !8)
+
+!120 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 1, arg: 1, scope: !12, file: !13, type: !8)
+
+!21 = !DILocation(line: 1, scope: !12, inlinedAt: !19)
+!22 = !DILocation(line: 2, scope: !12, inlinedAt: !19)
+!23 = !DILocation(line: 1, scope: !12)
+!24 = !DILocation(line: 2, scope: !12)
 
diff --git a/test/DebugInfo/cross-cu-linkonce-distinct.ll b/test/DebugInfo/cross-cu-linkonce-distinct.ll
index 2bd7c4718351..b8ce57e70352 100644
--- a/test/DebugInfo/cross-cu-linkonce-distinct.ll
+++ b/test/DebugInfo/cross-cu-linkonce-distinct.ll
@@ -52,8 +52,8 @@
 define linkonce_odr i32 @_Z4funci(i32 %i) #0 {
   %1 = alloca i32, align 4
   store i32 %i, i32* %1, align 4
-  call void @llvm.dbg.declare(metadata i32* %1, metadata !22, metadata !{!"0x102"}), !dbg !23
-  %2 = load i32* %1, align 4, !dbg !24
+  call void @llvm.dbg.declare(metadata i32* %1, metadata !22, metadata !DIExpression()), !dbg !23
+  %2 = load i32, i32* %1, align 4, !dbg !24
   %3 = mul nsw i32 %2, 2, !dbg !24
   ret i32 %3, !dbg !24
 }
@@ -68,28 +68,28 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!19, !20}
 !llvm.ident = !{!21, !21}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !9, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/a.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"a.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !9, imports: !2)
+!1 = !DIFile(filename: "a.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00func\00func\00_Z4funci\001\000\001\000\006\00256\000\001", !1, !5, !6, null, i32 (i32)* @_Z4funci, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [func]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/a.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "func", linkageName: "_Z4funci", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 (i32)* @_Z4funci, variables: !2)
+!5 = !DIFile(filename: "a.cpp", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{!10}
-!10 = !{!"0x34\00x\00x\00\004\000\001", null, !5, !11, i32 (i32)** @x, null} ; [ DW_TAG_variable ] [x] [line 4] [def]
-!11 = !{!"0xf\00\000\0064\0064\000\000", null, null, !6} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!12 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !13, !2, !2, !14, !17, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/b.cpp] [DW_LANG_C_plus_plus]
-!13 = !{!"b.cpp", !"/tmp/dbginfo"}
+!10 = !DIGlobalVariable(name: "x", line: 4, isLocal: false, isDefinition: true, scope: null, file: !5, type: !11, variable: i32 (i32)** @x)
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !6)
+!12 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !13, enums: !2, retainedTypes: !2, subprograms: !14, globals: !17, imports: !2)
+!13 = !DIFile(filename: "b.cpp", directory: "/tmp/dbginfo")
 !14 = !{!15}
-!15 = !{!"0x2e\00func\00func\00_Z4funci\001\000\001\000\006\00256\000\001", !13, !16, !6, null, i32 (i32)* @_Z4funci, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [func]
-!16 = !{!"0x29", !13}        ; [ DW_TAG_file_type ] [/tmp/dbginfo/b.cpp]
+!15 = !DISubprogram(name: "func", linkageName: "_Z4funci", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !13, scope: !16, type: !6, function: i32 (i32)* @_Z4funci, variables: !2)
+!16 = !DIFile(filename: "b.cpp", directory: "/tmp/dbginfo")
 !17 = !{!18}
-!18 = !{!"0x34\00y\00y\00\004\000\001", null, !16, !11, i32 (i32)** @y, null} ; [ DW_TAG_variable ] [y] [line 4] [def]
+!18 = !DIGlobalVariable(name: "y", line: 4, isLocal: false, isDefinition: true, scope: null, file: !16, type: !11, variable: i32 (i32)** @y)
 !19 = !{i32 2, !"Dwarf Version", i32 4}
-!20 = !{i32 1, !"Debug Info Version", i32 2}
+!20 = !{i32 1, !"Debug Info Version", i32 3}
 !21 = !{!"clang version 3.5.0 "}
-!22 = !{!"0x101\00i\0016777217\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [i] [line 1]
-!23 = !MDLocation(line: 1, scope: !4)
-!24 = !MDLocation(line: 2, scope: !4)
+!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 1, arg: 1, scope: !4, file: !5, type: !8)
+!23 = !DILocation(line: 1, scope: !4)
+!24 = !DILocation(line: 2, scope: !4)
diff --git a/test/DebugInfo/cross-cu-linkonce.ll b/test/DebugInfo/cross-cu-linkonce.ll
index aaae4c169d42..3638825fc9c7 100644
--- a/test/DebugInfo/cross-cu-linkonce.ll
+++ b/test/DebugInfo/cross-cu-linkonce.ll
@@ -32,8 +32,8 @@
 define linkonce_odr i32 @_Z4funci(i32 %i) #0 {
   %1 = alloca i32, align 4
   store i32 %i, i32* %1, align 4
-  call void @llvm.dbg.declare(metadata i32* %1, metadata !20, metadata !{!"0x102"}), !dbg !21
-  %2 = load i32* %1, align 4, !dbg !22
+  call void @llvm.dbg.declare(metadata i32* %1, metadata !20, metadata !DIExpression()), !dbg !21
+  %2 = load i32, i32* %1, align 4, !dbg !22
   %3 = mul nsw i32 %2, 2, !dbg !22
   ret i32 %3, !dbg !22
 }
@@ -48,26 +48,26 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!17, !18}
 !llvm.ident = !{!19, !19}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !10, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/a.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"a.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !10, imports: !2)
+!1 = !DIFile(filename: "a.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00func\00func\00_Z4funci\001\000\001\000\006\00256\000\001", !5, !6, !7, null, i32 (i32)* @_Z4funci, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [func]
-!5 = !{!"func.h", !"/tmp/dbginfo"}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/func.h]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "func", linkageName: "_Z4funci", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !5, scope: !6, type: !7, function: i32 (i32)* @_Z4funci, variables: !2)
+!5 = !DIFile(filename: "func.h", directory: "/tmp/dbginfo")
+!6 = !DIFile(filename: "func.h", directory: "/tmp/dbginfo")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !10 = !{!11}
-!11 = !{!"0x34\00x\00x\00\004\000\001", null, !6, !12, i32 (i32)** @x, null} ; [ DW_TAG_variable ] [x] [line 4] [def]
-!12 = !{!"0xf\00\000\0064\0064\000\000", null, null, !7} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!13 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !14, !2, !2, !3, !15, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/b.cpp] [DW_LANG_C_plus_plus]
-!14 = !{!"b.cpp", !"/tmp/dbginfo"}
+!11 = !DIGlobalVariable(name: "x", line: 4, isLocal: false, isDefinition: true, scope: null, file: !6, type: !12, variable: i32 (i32)** @x)
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !7)
+!13 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !14, enums: !2, retainedTypes: !2, subprograms: !3, globals: !15, imports: !2)
+!14 = !DIFile(filename: "b.cpp", directory: "/tmp/dbginfo")
 !15 = !{!16}
-!16 = !{!"0x34\00y\00y\00\004\000\001", null, !6, !12, i32 (i32)** @y, null} ; [ DW_TAG_variable ] [y] [line 4] [def]
+!16 = !DIGlobalVariable(name: "y", line: 4, isLocal: false, isDefinition: true, scope: null, file: !6, type: !12, variable: i32 (i32)** @y)
 !17 = !{i32 2, !"Dwarf Version", i32 4}
-!18 = !{i32 1, !"Debug Info Version", i32 2}
+!18 = !{i32 1, !"Debug Info Version", i32 3}
 !19 = !{!"clang version 3.5.0 "}
-!20 = !{!"0x101\00i\0016777217\000", !4, !6, !9} ; [ DW_TAG_arg_variable ] [i] [line 1]
-!21 = !MDLocation(line: 1, scope: !4)
-!22 = !MDLocation(line: 2, scope: !4)
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 1, arg: 1, scope: !4, file: !6, type: !9)
+!21 = !DILocation(line: 1, scope: !4)
+!22 = !DILocation(line: 2, scope: !4)
diff --git a/test/DebugInfo/cu-range-hole.ll b/test/DebugInfo/cu-range-hole.ll
index aa489b60d8cc..19a305483fb5 100644
--- a/test/DebugInfo/cu-range-hole.ll
+++ b/test/DebugInfo/cu-range-hole.ll
@@ -18,8 +18,8 @@ define i32 @b(i32 %c) #0 {
 entry:
   %c.addr = alloca i32, align 4
   store i32 %c, i32* %c.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %c.addr, metadata !13, metadata !{!"0x102"}), !dbg !14
-  %0 = load i32* %c.addr, align 4, !dbg !14
+  call void @llvm.dbg.declare(metadata i32* %c.addr, metadata !13, metadata !DIExpression()), !dbg !14
+  %0 = load i32, i32* %c.addr, align 4, !dbg !14
   %add = add nsw i32 %0, 1, !dbg !14
   ret i32 %add, !dbg !14
 }
@@ -29,7 +29,7 @@ define i32 @a(i32 %b) #0 {
 entry:
   %b.addr = alloca i32, align 4
   store i32 %b, i32* %b.addr, align 4
-  %0 = load i32* %b.addr, align 4
+  %0 = load i32, i32* %b.addr, align 4
   %add = add nsw i32 %0, 1
   ret i32 %add
 }
@@ -42,8 +42,8 @@ define i32 @d(i32 %e) #0 {
 entry:
   %e.addr = alloca i32, align 4
   store i32 %e, i32* %e.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %e.addr, metadata !15, metadata !{!"0x102"}), !dbg !16
-  %0 = load i32* %e.addr, align 4, !dbg !16
+  call void @llvm.dbg.declare(metadata i32* %e.addr, metadata !15, metadata !DIExpression()), !dbg !16
+  %0 = load i32, i32* %e.addr, align 4, !dbg !16
   %add = add nsw i32 %0, 1, !dbg !16
   ret i32 %add, !dbg !16
 }
@@ -56,19 +56,19 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!11, !12}
 
 !0 = !{!"clang version 3.5.0 (trunk 204164) (llvm/trunk 204183)"}
-!1 = !{!"0x11\0012\00clang version 3.5.0 (trunk 204164) (llvm/trunk 204183)\000\00\000\00\001", !2, !3, !3, !4, !3, !3} ; [ DW_TAG_compile_unit ]
-!2 = !{!"b.c", !"/usr/local/google/home/echristo"}
+!1 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 (trunk 204164) (llvm/trunk 204183)", isOptimized: false, emissionKind: 1, file: !2, enums: !3, retainedTypes: !3, subprograms: !4, globals: !3, imports: !3)
+!2 = !DIFile(filename: "b.c", directory: "/usr/local/google/home/echristo")
 !3 = !{}
 !4 = !{!5, !10}
-!5 = !{!"0x2e\00b\00b\00\001\000\001\000\006\00256\000\001", !2, !6, !7, null, i32 (i32)* @b, null, null, !3} ; [ DW_TAG_subprogram ] [line 1] [def] [b]
-!6 = !{!"0x29", !2}          ; [ DW_TAG_file_type ] [/usr/local/google/home/echristo/b.c]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "b", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !2, scope: !6, type: !7, function: i32 (i32)* @b, variables: !3)
+!6 = !DIFile(filename: "b.c", directory: "/usr/local/google/home/echristo")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"0x2e\00d\00d\00\003\000\001\000\006\00256\000\003", !2, !6, !7, null, i32 (i32)* @d, null, null, !3} ; [ DW_TAG_subprogram ] [line 3] [def] [d]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DISubprogram(name: "d", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !2, scope: !6, type: !7, function: i32 (i32)* @d, variables: !3)
 !11 = !{i32 2, !"Dwarf Version", i32 4}
-!12 = !{i32 1, !"Debug Info Version", i32 2}
-!13 = !{!"0x101\00c\0016777217\000", !5, !6, !9} ; [ DW_TAG_arg_variable ] [c] [line 1]
-!14 = !MDLocation(line: 1, scope: !5)
-!15 = !{!"0x101\00e\0016777219\000", !10, !6, !9} ; [ DW_TAG_arg_variable ] [e] [line 3]
-!16 = !MDLocation(line: 3, scope: !10)
+!12 = !{i32 1, !"Debug Info Version", i32 3}
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 1, arg: 1, scope: !5, file: !6, type: !9)
+!14 = !DILocation(line: 1, scope: !5)
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "e", line: 3, arg: 1, scope: !10, file: !6, type: !9)
+!16 = !DILocation(line: 3, scope: !10)
diff --git a/test/DebugInfo/cu-ranges.ll b/test/DebugInfo/cu-ranges.ll
index 6296b93792c2..3cec5c88f385 100644
--- a/test/DebugInfo/cu-ranges.ll
+++ b/test/DebugInfo/cu-ranges.ll
@@ -22,8 +22,8 @@ define i32 @foo(i32 %a) #0 section "__TEXT,__foo" {
 entry:
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !13, metadata !{!"0x102"}), !dbg !14
-  %0 = load i32* %a.addr, align 4, !dbg !15
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !13, metadata !DIExpression()), !dbg !14
+  %0 = load i32, i32* %a.addr, align 4, !dbg !15
   %add = add nsw i32 %0, 5, !dbg !15
   ret i32 %add, !dbg !15
 }
@@ -36,8 +36,8 @@ define i32 @bar(i32 %a) #0 {
 entry:
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !16, metadata !{!"0x102"}), !dbg !17
-  %0 = load i32* %a.addr, align 4, !dbg !18
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !16, metadata !DIExpression()), !dbg !17
+  %0 = load i32, i32* %a.addr, align 4, !dbg !18
   %add = add nsw i32 %0, 5, !dbg !18
   ret i32 %add, !dbg !18
 }
@@ -49,23 +49,23 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!10, !11}
 !llvm.ident = !{!12}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 (trunk 204164) (llvm/trunk 204183)\000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/foo.c] [DW_LANG_C99]
-!1 = !{!"foo.c", !"/usr/local/google/home/echristo"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 (trunk 204164) (llvm/trunk 204183)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "foo.c", directory: "/usr/local/google/home/echristo")
 !2 = !{}
 !3 = !{!4, !9}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, i32 (i32)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/usr/local/google/home/echristo/foo.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 (i32)* @foo, variables: !2)
+!5 = !DIFile(filename: "foo.c", directory: "/usr/local/google/home/echristo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x2e\00bar\00bar\00\005\000\001\000\006\00256\000\005", !1, !5, !6, null, i32 (i32)* @bar, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [bar]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DISubprogram(name: "bar", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, function: i32 (i32)* @bar, variables: !2)
 !10 = !{i32 2, !"Dwarf Version", i32 4}
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!11 = !{i32 1, !"Debug Info Version", i32 3}
 !12 = !{!"clang version 3.5.0 (trunk 204164) (llvm/trunk 204183)"}
-!13 = !{!"0x101\00a\0016777217\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [a] [line 1]
-!14 = !MDLocation(line: 1, scope: !4)
-!15 = !MDLocation(line: 2, scope: !4)
-!16 = !{!"0x101\00a\0016777221\000", !9, !5, !8} ; [ DW_TAG_arg_variable ] [a] [line 5]
-!17 = !MDLocation(line: 5, scope: !9)
-!18 = !MDLocation(line: 6, scope: !9)
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 1, arg: 1, scope: !4, file: !5, type: !8)
+!14 = !DILocation(line: 1, scope: !4)
+!15 = !DILocation(line: 2, scope: !4)
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 5, arg: 1, scope: !9, file: !5, type: !8)
+!17 = !DILocation(line: 5, scope: !9)
+!18 = !DILocation(line: 6, scope: !9)
 
diff --git a/test/DebugInfo/dead-argument-order.ll b/test/DebugInfo/dead-argument-order.ll
index d375412141a6..2dd556d096d6 100644
--- a/test/DebugInfo/dead-argument-order.ll
+++ b/test/DebugInfo/dead-argument-order.ll
@@ -38,8 +38,8 @@
 ; Function Attrs: nounwind readnone uwtable
 define i32 @_Z8function1Si(i32 %s.coerce, i32 %i) #0 {
 entry:
-  tail call void @llvm.dbg.declare(metadata %struct.S* undef, metadata !14, metadata !{!"0x102"}), !dbg !20
-  tail call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !20
+  tail call void @llvm.dbg.declare(metadata %struct.S* undef, metadata !14, metadata !DIExpression()), !dbg !20
+  tail call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !15, metadata !DIExpression()), !dbg !20
   %add = add nsw i32 %i, %s.coerce, !dbg !20
   ret i32 %add, !dbg !20
 }
@@ -57,25 +57,25 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!16, !17}
 !llvm.ident = !{!18}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \001\00\000\00\001", !1, !2, !3, !8, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/dead-argument-order.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"dead-argument-order.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !8, globals: !2, imports: !2)
+!1 = !DIFile(filename: "dead-argument-order.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00S\001\0032\0032\000\000\000", !1, null, null, !5, null, null, !"_ZTS1S"} ; [ DW_TAG_structure_type ] [S] [line 1, size 32, align 32, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "S", line: 1, size: 32, align: 32, file: !1, elements: !5, identifier: "_ZTS1S")
 !5 = !{!6}
-!6 = !{!"0xd\00i\001\0032\0032\000\000", !1, !"_ZTS1S", !7} ; [ DW_TAG_member ] [i] [line 1, size 32, align 32, offset 0] [from int]
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!6 = !DIDerivedType(tag: DW_TAG_member, name: "i", line: 1, size: 32, align: 32, file: !1, scope: !"_ZTS1S", baseType: !7)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !8 = !{!9}
-!9 = !{!"0x2e\00function\00function\00_Z8function1Si\002\000\001\000\006\00256\001\002", !1, !10, !11, null, i32 (i32, i32)* @_Z8function1Si, null, null, !13} ; [ DW_TAG_subprogram ] [line 2] [def] [function]
-!10 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/tmp/dbginfo/dead-argument-order.cpp]
-!11 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!9 = !DISubprogram(name: "function", linkageName: "_Z8function1Si", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2, file: !1, scope: !10, type: !11, function: i32 (i32, i32)* @_Z8function1Si, variables: !13)
+!10 = !DIFile(filename: "dead-argument-order.cpp", directory: "/tmp/dbginfo")
+!11 = !DISubroutineType(types: !12)
 !12 = !{!7, !4, !7}
 !13 = !{!14, !15}
-!14 = !{!"0x101\00s\0016777218\000", !9, !10, !"_ZTS1S"} ; [ DW_TAG_arg_variable ] [s] [line 2]
-!15 = !{!"0x101\00i\0033554434\000", !9, !10, !7} ; [ DW_TAG_arg_variable ] [i] [line 2]
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "s", line: 2, arg: 1, scope: !9, file: !10, type: !"_ZTS1S")
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 2, arg: 2, scope: !9, file: !10, type: !7)
 !16 = !{i32 2, !"Dwarf Version", i32 4}
-!17 = !{i32 2, !"Debug Info Version", i32 2}
+!17 = !{i32 2, !"Debug Info Version", i32 3}
 !18 = !{!"clang version 3.5.0 "}
 !19 = !{%struct.S* undef}
-!20 = !MDLocation(line: 2, scope: !9)
+!20 = !DILocation(line: 2, scope: !9)
 
diff --git a/test/DebugInfo/debug-info-always-inline.ll b/test/DebugInfo/debug-info-always-inline.ll
index 88ac4cb39d5a..5eaa67522181 100644
--- a/test/DebugInfo/debug-info-always-inline.ll
+++ b/test/DebugInfo/debug-info-always-inline.ll
@@ -78,11 +78,11 @@ entry:
   %arr = alloca [10 x i32], align 16
   %sum = alloca i32, align 4
   call void @llvm.dbg.declare(metadata [10 x i32]* %arr, metadata !14), !dbg !18
-  %arrayidx = getelementptr inbounds [10 x i32]* %arr, i32 0, i64 0, !dbg !19
+  %arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* %arr, i32 0, i64 0, !dbg !19
   store i32 5, i32* %arrayidx, align 4, !dbg !19
   call void @llvm.dbg.declare(metadata i32* %sum, metadata !20), !dbg !21
   store i32 4, i32* %sum, align 4, !dbg !21
-  %0 = load i32* %sum, align 4, !dbg !22
+  %0 = load i32, i32* %sum, align 4, !dbg !22
   ret i32 %0, !dbg !22
 }
 
@@ -99,7 +99,7 @@ entry:
   call void @llvm.dbg.declare(metadata i32* %i, metadata !24), !dbg !25
   %call = call i32 @_Z3foov(), !dbg !25
   store i32 %call, i32* %i, align 4, !dbg !25
-  %0 = load i32* %i, align 4, !dbg !26
+  %0 = load i32, i32* %i, align 4, !dbg !26
   ret i32 %0, !dbg !26
 }
 
@@ -132,12 +132,12 @@ attributes #3 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "
 !15 = !{i32 786433, null, null, !"", i32 0, i64 320, i64 32, i32 0, i32 0, !9, !16, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 320, align 32, offset 0] [from int]
 !16 = !{!17}
 !17 = !{i32 786465, i64 0, i64 10}       ; [ DW_TAG_subrange_type ] [0, 9]
-!18 = !MDLocation(line: 3, scope: !4)
-!19 = !MDLocation(line: 4, scope: !4)
+!18 = !DILocation(line: 3, scope: !4)
+!19 = !DILocation(line: 4, scope: !4)
 !20 = !{i32 786688, !4, !"sum", !6, i32 5, !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [sum] [line 5]
-!21 = !MDLocation(line: 5, scope: !4)
-!22 = !MDLocation(line: 6, scope: !4)
-!23 = !MDLocation(line: 13, scope: !10)
+!21 = !DILocation(line: 5, scope: !4)
+!22 = !DILocation(line: 6, scope: !4)
+!23 = !DILocation(line: 13, scope: !10)
 !24 = !{i32 786688, !10, !"i", !6, i32 14, !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 14]
-!25 = !MDLocation(line: 14, scope: !10)
-!26 = !MDLocation(line: 15, scope: !10)
+!25 = !DILocation(line: 14, scope: !10)
+!26 = !DILocation(line: 15, scope: !10)
diff --git a/test/DebugInfo/debug-info-qualifiers.ll b/test/DebugInfo/debug-info-qualifiers.ll
index b0f9cd4c83b8..1f8f6c419932 100644
--- a/test/DebugInfo/debug-info-qualifiers.ll
+++ b/test/DebugInfo/debug-info-qualifiers.ll
@@ -39,10 +39,10 @@ define void @_Z1gv() #0 {
   %a = alloca %class.A, align 1
   %pl = alloca { i64, i64 }, align 8
   %pr = alloca { i64, i64 }, align 8
-  call void @llvm.dbg.declare(metadata %class.A* %a, metadata !24, metadata !{!"0x102"}), !dbg !25
-  call void @llvm.dbg.declare(metadata { i64, i64 }* %pl, metadata !26, metadata !{!"0x102"}), !dbg !31
+  call void @llvm.dbg.declare(metadata %class.A* %a, metadata !24, metadata !DIExpression()), !dbg !25
+  call void @llvm.dbg.declare(metadata { i64, i64 }* %pl, metadata !26, metadata !DIExpression()), !dbg !31
   store { i64, i64 } { i64 ptrtoint (void (%class.A*)* @_ZNKR1A1lEv to i64), i64 0 }, { i64, i64 }* %pl, align 8, !dbg !31
-  call void @llvm.dbg.declare(metadata { i64, i64 }* %pr, metadata !32, metadata !{!"0x102"}), !dbg !35
+  call void @llvm.dbg.declare(metadata { i64, i64 }* %pr, metadata !32, metadata !DIExpression()), !dbg !35
   store { i64, i64 } { i64 ptrtoint (void (%class.A*)* @_ZNKO1A1rEv to i64), i64 0 }, { i64, i64 }* %pr, align 8, !dbg !35
   ret void, !dbg !36
 }
@@ -61,40 +61,38 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!21, !22}
 !llvm.ident = !{!23}
 
-!0 = !{!"0x11\004\00clang version 3.5 \000\00\000\00\000", !1, !2, !3, !16, !2, !2} ; [ DW_TAG_compile_unit ] [] [DW_LANG_C_plus_plus]
-!1 = !{!"", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !16, globals: !2, imports: !2)
+!1 = !DIFile(filename: "debug-info-qualifiers.cpp", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2\00A\002\008\008\000\000\000", !5, null, null, !6, null, null, !"_ZTS1A"} ; [ DW_TAG_class_type ] [A] [line 2, size 8, align 8, offset 0] [def] [from ]
-!5 = !{!"debug-info-qualifiers.cpp", !""}
+!4 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 2, size: 8, align: 8, file: !5, elements: !6, identifier: "_ZTS1A")
+!5 = !DIFile(filename: "debug-info-qualifiers.cpp", directory: "")
 !6 = !{!7, !13}
-!7 = !{!"0x2e\00l\00l\00_ZNKR1A1lEv\005\000\000\000\006\0016640\000\005", !5, !"_ZTS1A", !8, null, null, null, i32 0, !12} ; [ DW_TAG_subprogram ] [line 5] [reference] [l]
-!8 = !{!"0x15\00\000\000\000\000\0016384\000", i32 0, null, null, !9, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [reference] [from ]
+!7 = !DISubprogram(name: "l", linkageName: "_ZNKR1A1lEv", line: 5, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped | DIFlagLValueReference, isOptimized: false, scopeLine: 5, file: !5, scope: !"_ZTS1A", type: !8)
+!8 = !DISubroutineType(flags: DIFlagLValueReference, types: !9)
 !9 = !{null, !10}
-!10 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !11} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from ]
-!11 = !{!"0x26\00\000\000\000\000\000", null, null, !"_ZTS1A"} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from _ZTS1A]
-!12 = !{i32 786468}
-!13 = !{!"0x2e\00r\00r\00_ZNKO1A1rEv\007\000\000\000\006\0033024\000\007", !5, !"_ZTS1A", !14, null, null, null, i32 0, !15} ; [ DW_TAG_subprogram ] [line 7] [rvalue reference] [r]
-!14 = !{!"0x15\00\000\000\000\000\0032768\000", i32 0, null, null, !9, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [rvalue reference] [from ]
-!15 = !{i32 786468}
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !11)
+!11 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !"_ZTS1A")
+!13 = !DISubprogram(name: "r", linkageName: "_ZNKO1A1rEv", line: 7, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagObjectPointer | DIFlagRValueReference, isOptimized: false, scopeLine: 7, file: !5, scope: !"_ZTS1A", type: !14)
+!14 = !DISubroutineType(flags: DIFlagRValueReference, types: !9)
 !16 = !{!17}
-!17 = !{!"0x2e\00g\00g\00_Z1gv\0010\000\001\000\006\00256\000\0010", !5, !18, !19, null, void ()* @_Z1gv, null, null, !2} ; [ DW_TAG_subprogram ] [line 10] [def] [g]
-!18 = !{!"0x29", !5}         ; [ DW_TAG_file_type ]
-!19 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !20, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!17 = !DISubprogram(name: "g", linkageName: "_Z1gv", line: 10, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 10, file: !5, scope: !18, type: !19, function: void ()* @_Z1gv, variables: !2)
+!18 = !DIFile(filename: "debug-info-qualifiers.cpp", directory: "")
+!19 = !DISubroutineType(types: !20)
 !20 = !{null}
 !21 = !{i32 2, !"Dwarf Version", i32 4}
-!22 = !{i32 1, !"Debug Info Version", i32 2}
+!22 = !{i32 1, !"Debug Info Version", i32 3}
 !23 = !{!"clang version 3.5 "}
-!24 = !{!"0x100\00a\0011\000", !17, !18, !4} ; [ DW_TAG_auto_variable ] [a] [line 11]
-!25 = !MDLocation(line: 11, scope: !17)
-!26 = !{!"0x100\00pl\0016\000", !17, !18, !27} ; [ DW_TAG_auto_variable ] [pl] [line 16]
-!27 = !{!"0x1f\00\000\000\000\000\000", null, null, !28, !"_ZTS1A"} ; [ DW_TAG_ptr_to_member_type ] [line 0, size 0, align 0, offset 0] [from ]
-!28 = !{!"0x15\00\000\000\000\000\0016384\000", i32 0, null, null, !29, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [reference] [from ]
+!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 11, scope: !17, file: !18, type: !4)
+!25 = !DILocation(line: 11, scope: !17)
+!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "pl", line: 16, scope: !17, file: !18, type: !27)
+!27 = !DIDerivedType(tag: DW_TAG_ptr_to_member_type, baseType: !28, extraData: !"_ZTS1A")
+!28 = !DISubroutineType(flags: DIFlagLValueReference, types: !29)
 !29 = !{null, !30}
-!30 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1A]
-!31 = !MDLocation(line: 16, scope: !17)
-!32 = !{!"0x100\00pr\0021\000", !17, !18, !33} ; [ DW_TAG_auto_variable ] [pr] [line 21]
-!33 = !{!"0x1f\00\000\000\000\000\000", null, null, !34, !"_ZTS1A"} ; [ DW_TAG_ptr_to_member_type ] [line 0, size 0, align 0, offset 0] [from ]
-!34 = !{!"0x15\00\000\000\000\000\0032768\000", i32 0, null, null, !29, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [rvalue reference] [from ]
-!35 = !MDLocation(line: 21, scope: !17)
-!36 = !MDLocation(line: 22, scope: !17)
+!30 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1A")
+!31 = !DILocation(line: 16, scope: !17)
+!32 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "pr", line: 21, scope: !17, file: !18, type: !33)
+!33 = !DIDerivedType(tag: DW_TAG_ptr_to_member_type, baseType: !34, extraData: !"_ZTS1A")
+!34 = !DISubroutineType(flags: DIFlagRValueReference, types: !29)
+!35 = !DILocation(line: 21, scope: !17)
+!36 = !DILocation(line: 22, scope: !17)
diff --git a/test/DebugInfo/debuginfofinder-forward-declaration.ll b/test/DebugInfo/debuginfofinder-forward-declaration.ll
new file mode 100644
index 000000000000..db143260e02b
--- /dev/null
+++ b/test/DebugInfo/debuginfofinder-forward-declaration.ll
@@ -0,0 +1,42 @@
+; RUN: opt -analyze -module-debuginfo < %s | FileCheck %s
+
+
+; This module is generated from the following c-code:
+;
+; > union X;
+; >
+; > struct Y {
+; >     union X *x;
+; > };
+; >
+; > struct Y y;
+
+
+; CHECK: Type: Y from /tmp/minimal.c:3 DW_TAG_structure_type
+; CHECK: Type: x from /tmp/minimal.c:4 DW_TAG_member
+; CHECK: Type: DW_TAG_pointer_type
+; CHECK: Type: X from /tmp/minimal.c:1 DW_TAG_structure_type
+
+
+%struct.Y = type { %struct.X* }
+%struct.X = type opaque
+
+@y = common global %struct.Y zeroinitializer, align 8
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!10, !11}
+!llvm.ident = !{!12}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (http://llvm.org/git/clang.git 247b30a043eb8f39ea3708e7e995089da0a6b00f) (http://llvm.org/git/llvm.git 6ecc7365a89c771fd229bdd9ffcc178684ea1aa5)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3, imports: !2)
+!1 = !DIFile(filename: "minimal.c", directory: "/tmp")
+!2 = !{}
+!3 = !{!4}
+!4 = !DIGlobalVariable(name: "y", scope: !0, file: !1, line: 7, type: !5, isLocal: false, isDefinition: true, variable: %struct.Y* @y)
+!5 = !DICompositeType(tag: DW_TAG_structure_type, name: "Y", file: !1, line: 3, size: 64, align: 64, elements: !6)
+!6 = !{!7}
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: !5, file: !1, line: 4, baseType: !8, size: 64, align: 64)
+!8 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 64, align: 64)
+!9 = !DICompositeType(tag: DW_TAG_structure_type, name: "X", file: !1, line: 1, flags: DIFlagFwdDecl)
+!10 = !{i32 2, !"Dwarf Version", i32 4}
+!11 = !{i32 2, !"Debug Info Version", i32 3}
+!12 = !{!"clang version 3.7.0 (http://llvm.org/git/clang.git 247b30a043eb8f39ea3708e7e995089da0a6b00f) (http://llvm.org/git/llvm.git 6ecc7365a89c771fd229bdd9ffcc178684ea1aa5)"}
diff --git a/test/DebugInfo/debuginfofinder-multiple-cu.ll b/test/DebugInfo/debuginfofinder-multiple-cu.ll
index 0eba64d2ea63..4088dd54f53f 100644
--- a/test/DebugInfo/debuginfofinder-multiple-cu.ll
+++ b/test/DebugInfo/debuginfofinder-multiple-cu.ll
@@ -6,10 +6,10 @@
 
 ; Verify that both compile units and both their contained functions are
 ; listed by DebugInfoFinder:
-;CHECK: Compile Unit: [ DW_TAG_compile_unit ] [/tmp/test1.c] [DW_LANG_C99]
-;CHECK: Compile Unit: [ DW_TAG_compile_unit ] [/tmp/test2.c] [DW_LANG_C99]
-;CHECK: Subprogram: [ DW_TAG_subprogram ] [line 1] [def] [f]
-;CHECK: Subprogram: [ DW_TAG_subprogram ] [line 1] [def] [g]
+;CHECK: Compile unit: DW_LANG_C99 from /tmp/test1.c
+;CHECK: Compile unit: DW_LANG_C99 from /tmp/test2.c
+;CHECK: Subprogram: f from /tmp/test1.c:1
+;CHECK: Subprogram: g from /tmp/test2.c:1
 
 define void @f() {
   ret void, !dbg !14
@@ -22,20 +22,20 @@ define void @g() {
 !llvm.dbg.cu = !{!0, !8}
 !llvm.module.flags = !{!13, !16}
 
-!0 = !{!"0x11\0012\00clang version 3.4 (192092)\000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/test1.c] [DW_LANG_C99]
-!1 = !{!"test1.c", !"/tmp"}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (192092)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test1.c", directory: "/tmp")
+!2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00f\00f\00\001\000\001\000\006\000\000\001", !1, !5, !6, null, void ()* @f, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [f]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/test1.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "f", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void ()* @f, variables: !2)
+!5 = !DIFile(filename: "test1.c", directory: "/tmp")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
-!8 = !{!"0x11\0012\00clang version 3.4 (192092)\000\00\000\00\000", !9, !2, !2, !10, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/test2.c] [DW_LANG_C99]
-!9 = !{!"test2.c", !"/tmp"}
+!8 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (192092)", isOptimized: false, emissionKind: 0, file: !9, enums: !2, retainedTypes: !2, subprograms: !10, globals: !2, imports: !2)
+!9 = !DIFile(filename: "test2.c", directory: "/tmp")
 !10 = !{!11}
-!11 = !{!"0x2e\00g\00g\00\001\000\001\000\006\000\000\001", !9, !12, !6, null, void ()* @g, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [g]
-!12 = !{!"0x29", !9}         ; [ DW_TAG_file_type ] [/tmp/test2.c]
+!11 = !DISubprogram(name: "g", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !9, scope: !12, type: !6, function: void ()* @g, variables: !2)
+!12 = !DIFile(filename: "test2.c", directory: "/tmp")
 !13 = !{i32 2, !"Dwarf Version", i32 4}
-!14 = !MDLocation(line: 1, scope: !4)
-!15 = !MDLocation(line: 1, scope: !11)
-!16 = !{i32 1, !"Debug Info Version", i32 2}
+!14 = !DILocation(line: 1, scope: !4)
+!15 = !DILocation(line: 1, scope: !11)
+!16 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/debuglineinfo.test b/test/DebugInfo/debuglineinfo.test
index 14d2f82b04ac..96a32285be46 100644
--- a/test/DebugInfo/debuglineinfo.test
+++ b/test/DebugInfo/debuglineinfo.test
@@ -1,7 +1,11 @@
 RUN: llvm-rtdyld -printline %p/Inputs/test-inline.o \
 RUN:   | FileCheck %s -check-prefix TEST_INLINE
+RUN: llvm-rtdyld -printdebugline %p/Inputs/test-inline.o \
+RUN:   | FileCheck %s -check-prefix TEST_INLINE
 RUN: llvm-rtdyld -printline %p/Inputs/test-parameters.o \
 RUN:   | FileCheck %s -check-prefix TEST_PARAMETERS
+RUN: llvm-rtdyld -printdebugline %p/Inputs/test-parameters.o \
+RUN:   | FileCheck %s -check-prefix TEST_PARAMETERS
 
 ; This test verifies that relocations are correctly applied to the
 ; .debug_line section and exercises DIContext::getLineInfoForAddressRange().
diff --git a/test/DebugInfo/duplicate_inline.ll b/test/DebugInfo/duplicate_inline.ll
deleted file mode 100644
index 2a9c485632b3..000000000000
--- a/test/DebugInfo/duplicate_inline.ll
+++ /dev/null
@@ -1,117 +0,0 @@
-; REQUIRES: object-emission
-
-; RUN: %llc_dwarf < %s -filetype=obj | llvm-dwarfdump -debug-dump=info - | FileCheck %s
-
-; Built with clang from the following source:
-; void f1(int);
-; __attribute__((always_inline)) inline void f2(int i) { f1(i); }
-;
-; #define MULTICALL \
-;   f2(x);          \
-;   f2(y);
-;
-; void f3(int x, int y) { MULTICALL; }
-
-; FIXME: This produces only one inlined_subroutine, with two formal_parameters
-; (both named "this"), one for each of the actual inlined subroutines.  ;
-; Inlined scopes are differentiated by the combination of 'inlined at' (call)
-; location and the location within the function. If two calls to the same
-; function occur at the same location the scopes end up conflated and there
-; appears to be only one inlined function.
-; To fix this, we'd need to add some kind of unique metadata per call site, possibly something like:
-;
-; !42 = !MDLocation(line: 1, scope: !43, inlinedAt: !44)
-; !44 = !MDLocation(line: 2, scope: !45)
-;
-; ->
-;
-; !42 = !MDLocation(line: 1, scope: !43, inlinedAt: !44)
-; !44 = !{!45, !44}
-; !45 = !MDLocation(line: 2, scope: !45)
-;
-; since cycles in metadata are not uniqued, the !44 node would not be shared
-; between calls to the same function from the same location, ensuring separate
-; inlined subroutines would be generated.
-;
-; Once this is done, the (insufficient) hack in clang that adds column
-; information to call sites to differentiate inlined callers can be removed as it
-; will no longer be necessary.
-;
-; While it might be nice to omit the duplicate parameter in this case (while
-; we wait/work on the real fix), it's actually better to leave it in because it
-; allows us to hold the invariant that every DbgVariable has a DIE, every time.
-; This has proved valuable in finding other bugs, so I want to avoid removing the
-; invariant/assertion. Besides, we don't know which one's the right one anyway...
-
-; CHECK: DW_TAG_subprogram
-; CHECK:   DW_TAG_inlined_subroutine
-; CHECK:     DW_TAG_formal_parameter
-; CHECK-NOT: DW_TAG
-; CHECK:     DW_TAG_formal_parameter
-; CHECK-NOT: DW_TAG
-; CHECK:     NULL
-; CHECK-NOT: DW_TAG
-; CHECK:   NULL
-
-; Function Attrs: uwtable
-define void @_Z2f3ii(i32 %x, i32 %y) #0 {
-entry:
-  %i.addr.i1 = alloca i32, align 4
-  %i.addr.i = alloca i32, align 4
-  %x.addr = alloca i32, align 4
-  %y.addr = alloca i32, align 4
-  store i32 %x, i32* %x.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !15, metadata !16), !dbg !17
-  store i32 %y, i32* %y.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %y.addr, metadata !18, metadata !16), !dbg !19
-  %0 = load i32* %x.addr, align 4, !dbg !20
-  store i32 %0, i32* %i.addr.i, align 4, !dbg !20
-  call void @llvm.dbg.declare(metadata i32* %i.addr.i, metadata !21, metadata !16), !dbg !22
-  %1 = load i32* %i.addr.i, align 4, !dbg !23
-  call void @_Z2f1i(i32 %1), !dbg !23
-  %2 = load i32* %y.addr, align 4, !dbg !20
-  store i32 %2, i32* %i.addr.i1, align 4, !dbg !20
-  call void @llvm.dbg.declare(metadata i32* %i.addr.i1, metadata !21, metadata !16), !dbg !22
-  %3 = load i32* %i.addr.i1, align 4, !dbg !23
-  call void @_Z2f1i(i32 %3), !dbg !23
-  ret void, !dbg !24
-}
-
-; Function Attrs: nounwind readnone
-declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
-
-declare void @_Z2f1i(i32) #2
-
-attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
-attributes #1 = { nounwind readnone }
-attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
-
-!llvm.dbg.cu = !{!0}
-!llvm.module.flags = !{!12, !13}
-!llvm.ident = !{!14}
-
-!0 = !{!"0x11\004\00clang version 3.6.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/duplicate_inline.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"duplicate_inline.cpp", !"/tmp/dbginfo"}
-!2 = !{}
-!3 = !{!4, !9}
-!4 = !{!"0x2e\00f3\00f3\00_Z2f3ii\008\000\001\000\000\00256\000\008", !1, !5, !6, null, void (i32, i32)* @_Z2f3ii, null, null, !2} ; [ DW_TAG_subprogram ] [line 8] [def] [f3]
-!5 = !{!"0x29", !1}    ; [ DW_TAG_file_type ] [/tmp/dbginfo/duplicate_inline.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!7 = !{null, !8, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x2e\00f2\00f2\00_Z2f2i\002\000\001\000\000\00256\000\002", !1, !5, !10, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [f2]
-!10 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!11 = !{null, !8}
-!12 = !{i32 2, !"Dwarf Version", i32 4}
-!13 = !{i32 2, !"Debug Info Version", i32 2}
-!14 = !{!"clang version 3.6.0 "}
-!15 = !{!"0x101\00x\0016777224\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [x] [line 8]
-!16 = !{!"0x102"}               ; [ DW_TAG_expression ]
-!17 = !MDLocation(line: 8, column: 13, scope: !4)
-!18 = !{!"0x101\00y\0033554440\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [y] [line 8]
-!19 = !MDLocation(line: 8, column: 20, scope: !4)
-!20 = !MDLocation(line: 8, column: 25, scope: !4)
-!21 = !{!"0x101\00i\0016777218\000", !9, !5, !8} ; [ DW_TAG_arg_variable ] [i] [line 2]
-!22 = !MDLocation(line: 2, column: 51, scope: !9, inlinedAt: !20)
-!23 = !MDLocation(line: 2, column: 56, scope: !9, inlinedAt: !20)
-!24 = !MDLocation(line: 8, column: 36, scope: !4)
diff --git a/test/DebugInfo/dwarf-public-names.ll b/test/DebugInfo/dwarf-public-names.ll
index d2b866420436..bd340578bfb0 100644
--- a/test/DebugInfo/dwarf-public-names.ll
+++ b/test/DebugInfo/dwarf-public-names.ll
@@ -59,8 +59,8 @@ define void @_ZN1C15member_functionEv(%struct.C* %this) nounwind uwtable align 2
 entry:
   %this.addr = alloca %struct.C*, align 8
   store %struct.C* %this, %struct.C** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.C** %this.addr, metadata !28, metadata !{!"0x102"}), !dbg !30
-  %this1 = load %struct.C** %this.addr
+  call void @llvm.dbg.declare(metadata %struct.C** %this.addr, metadata !28, metadata !DIExpression()), !dbg !30
+  %this1 = load %struct.C*, %struct.C** %this.addr
   store i32 0, i32* @_ZN1C22static_member_variableE, align 4, !dbg !31
   ret void, !dbg !32
 }
@@ -69,7 +69,7 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 
 define i32 @_ZN1C22static_member_functionEv() nounwind uwtable align 2 {
 entry:
-  %0 = load i32* @_ZN1C22static_member_variableE, align 4, !dbg !33
+  %0 = load i32, i32* @_ZN1C22static_member_variableE, align 4, !dbg !33
   ret i32 %0, !dbg !33
 }
 
@@ -90,42 +90,42 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!38}
 
-!0 = !{!"0x11\004\00clang version 3.3 (http://llvm.org/git/clang.git a09cd8103a6a719cb2628cdf0c91682250a17bd2) (http://llvm.org/git/llvm.git 47d03cec0afca0c01ae42b82916d1d731716cd20)\000\00\000\00\000", !37, !1, !1, !2, !24,  !1} ; [ DW_TAG_compile_unit ] [/usr2/kparzysz/s.hex/t/dwarf-public-names.cpp] [DW_LANG_C_plus_plus]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 (http://llvm.org/git/clang.git a09cd8103a6a719cb2628cdf0c91682250a17bd2) (http://llvm.org/git/llvm.git 47d03cec0afca0c01ae42b82916d1d731716cd20)", isOptimized: false, emissionKind: 0, file: !37, enums: !1, retainedTypes: !1, subprograms: !2, globals: !24, imports:  !1)
 !1 = !{}
 !2 = !{!3, !18, !19, !20}
-!3 = !{!"0x2e\00member_function\00member_function\00_ZN1C15member_functionEv\009\000\001\000\006\00256\000\009", !4, null, !5, null, void (%struct.C*)* @_ZN1C15member_functionEv, null, !12, !1} ; [ DW_TAG_subprogram ] [line 9] [def] [member_function]
-!4 = !{!"0x29", !37} ; [ DW_TAG_file_type ]
-!5 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !6, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!3 = !DISubprogram(name: "member_function", linkageName: "_ZN1C15member_functionEv", line: 9, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 9, file: !4, scope: null, type: !5, function: void (%struct.C*)* @_ZN1C15member_functionEv, declaration: !12, variables: !1)
+!4 = !DIFile(filename: "dwarf-public-names.cpp", directory: "/usr2/kparzysz/s.hex/t")
+!5 = !DISubroutineType(types: !6)
 !6 = !{null, !7}
-!7 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !8} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from C]
-!8 = !{!"0x13\00C\001\008\008\000\000\000", !37, null, null, !9, null, null, null} ; [ DW_TAG_structure_type ] [C] [line 1, size 8, align 8, offset 0] [def] [from ]
+!7 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !8)
+!8 = !DICompositeType(tag: DW_TAG_structure_type, name: "C", line: 1, size: 8, align: 8, file: !37, elements: !9)
 !9 = !{!10, !12, !14}
-!10 = !{!"0xd\00static_member_variable\004\000\000\000\004096", !37, !8, !11, null} ; [ DW_TAG_member ] [static_member_variable] [line 4, size 0, align 0, offset 0] [static] [from int]
-!11 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!12 = !{!"0x2e\00member_function\00member_function\00_ZN1C15member_functionEv\002\000\000\000\006\00256\000\002", !4, !8, !5, null, null, null, i32 0, !13} ; [ DW_TAG_subprogram ] [line 2] [member_function]
-!13 = !{!"0x24"}                      ; [ DW_TAG_base_type ] [line 0, size 0, align 0, offset 0]
-!14 = !{!"0x2e\00static_member_function\00static_member_function\00_ZN1C22static_member_functionEv\003\000\000\000\006\00256\000\003", !4, !8, !15, null, null, null, i32 0, !17} ; [ DW_TAG_subprogram ] [line 3] [static_member_function]
-!15 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!10 = !DIDerivedType(tag: DW_TAG_member, name: "static_member_variable", line: 4, flags: DIFlagStaticMember, file: !37, scope: !8, baseType: !11)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!12 = !DISubprogram(name: "member_function", linkageName: "_ZN1C15member_functionEv", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !4, scope: !8, type: !5, variables: !13)
+!13 = !{} ; previously: invalid DW_TAG_base_type
+!14 = !DISubprogram(name: "static_member_function", linkageName: "_ZN1C22static_member_functionEv", line: 3, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !4, scope: !8, type: !15, variables: !17)
+!15 = !DISubroutineType(types: !16)
 !16 = !{!11}
-!17 = !{!"0x24"}                      ; [ DW_TAG_base_type ] [line 0, size 0, align 0, offset 0]
-!18 = !{!"0x2e\00static_member_function\00static_member_function\00_ZN1C22static_member_functionEv\0013\000\001\000\006\00256\000\0013", !4, null, !15, null, i32 ()* @_ZN1C22static_member_functionEv, null, !14, !1} ; [ DW_TAG_subprogram ] [line 13] [def] [static_member_function]
-!19 = !{!"0x2e\00global_function\00global_function\00_Z15global_functionv\0019\000\001\000\006\00256\000\0019", !4, !4, !15, null, i32 ()* @_Z15global_functionv, null, null, !1} ; [ DW_TAG_subprogram ] [line 19] [def] [global_function]
-!20 = !{!"0x2e\00global_namespace_function\00global_namespace_function\00_ZN2ns25global_namespace_functionEv\0024\000\001\000\006\00256\000\0024", !4, !21, !22, null, void ()* @_ZN2ns25global_namespace_functionEv, null, null, !1} ; [ DW_TAG_subprogram ] [line 24] [def] [global_namespace_function]
-!21 = !{!"0x39\00ns\0023", !4, null} ; [ DW_TAG_namespace ] [/usr2/kparzysz/s.hex/t/dwarf-public-names.cpp]
-!22 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !23, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!17 = !{} ; previously: invalid DW_TAG_base_type
+!18 = !DISubprogram(name: "static_member_function", linkageName: "_ZN1C22static_member_functionEv", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 13, file: !4, scope: null, type: !15, function: i32 ()* @_ZN1C22static_member_functionEv, declaration: !14, variables: !1)
+!19 = !DISubprogram(name: "global_function", linkageName: "_Z15global_functionv", line: 19, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 19, file: !4, scope: !4, type: !15, function: i32 ()* @_Z15global_functionv, variables: !1)
+!20 = !DISubprogram(name: "global_namespace_function", linkageName: "_ZN2ns25global_namespace_functionEv", line: 24, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 24, file: !4, scope: !21, type: !22, function: void ()* @_ZN2ns25global_namespace_functionEv, variables: !1)
+!21 = !DINamespace(name: "ns", line: 23, file: !4, scope: null)
+!22 = !DISubroutineType(types: !23)
 !23 = !{null}
 !24 = !{!25, !26, !27}
-!25 = !{!"0x34\00static_member_variable\00static_member_variable\00_ZN1C22static_member_variableE\007\000\001", !8, !4, !11, i32* @_ZN1C22static_member_variableE, !10} ; [ DW_TAG_variable ] [static_member_variable] [line 7] [def]
-!26 = !{!"0x34\00global_variable\00global_variable\00\0017\000\001", null, !4, !8, %struct.C* @global_variable, null} ; [ DW_TAG_variable ] [global_variable] [line 17] [def]
-!27 = !{!"0x34\00global_namespace_variable\00global_namespace_variable\00_ZN2ns25global_namespace_variableE\0027\000\001", !21, !4, !11, i32* @_ZN2ns25global_namespace_variableE, null} ; [ DW_TAG_variable ] [global_namespace_variable] [line 27] [def]
-!28 = !{!"0x101\00this\0016777225\001088", !3, !4, !29} ; [ DW_TAG_arg_variable ] [this] [line 9]
-!29 = !{!"0xf\00\000\0064\0064\000\000", null, null, !8} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from C]
-!30 = !MDLocation(line: 9, scope: !3)
-!31 = !MDLocation(line: 10, scope: !3)
-!32 = !MDLocation(line: 11, scope: !3)
-!33 = !MDLocation(line: 14, scope: !18)
-!34 = !MDLocation(line: 20, scope: !19)
-!35 = !MDLocation(line: 25, scope: !20)
-!36 = !MDLocation(line: 26, scope: !20)
-!37 = !{!"dwarf-public-names.cpp", !"/usr2/kparzysz/s.hex/t"}
-!38 = !{i32 1, !"Debug Info Version", i32 2}
+!25 = !DIGlobalVariable(name: "static_member_variable", linkageName: "_ZN1C22static_member_variableE", line: 7, isLocal: false, isDefinition: true, scope: !8, file: !4, type: !11, variable: i32* @_ZN1C22static_member_variableE, declaration: !10)
+!26 = !DIGlobalVariable(name: "global_variable", line: 17, isLocal: false, isDefinition: true, scope: null, file: !4, type: !8, variable: %struct.C* @global_variable)
+!27 = !DIGlobalVariable(name: "global_namespace_variable", linkageName: "_ZN2ns25global_namespace_variableE", line: 27, isLocal: false, isDefinition: true, scope: !21, file: !4, type: !11, variable: i32* @_ZN2ns25global_namespace_variableE)
+!28 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 9, arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !3, file: !4, type: !29)
+!29 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !8)
+!30 = !DILocation(line: 9, scope: !3)
+!31 = !DILocation(line: 10, scope: !3)
+!32 = !DILocation(line: 11, scope: !3)
+!33 = !DILocation(line: 14, scope: !18)
+!34 = !DILocation(line: 20, scope: !19)
+!35 = !DILocation(line: 25, scope: !20)
+!36 = !DILocation(line: 26, scope: !20)
+!37 = !DIFile(filename: "dwarf-public-names.cpp", directory: "/usr2/kparzysz/s.hex/t")
+!38 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/dwarfdump-debug-frame-simple.test b/test/DebugInfo/dwarfdump-debug-frame-simple.test
index c2427d840e45..b1a58e6ec2a4 100644
--- a/test/DebugInfo/dwarfdump-debug-frame-simple.test
+++ b/test/DebugInfo/dwarfdump-debug-frame-simple.test
@@ -6,22 +6,22 @@
 
 ; FRAMES: 00000000 00000010 ffffffff CIE
 ; FRAMES: Version: 1
-; FRAMES:      DW_CFA_def_cfa
-; FRAMES-NEXT: DW_CFA_offset
-; FRAMES-NEXT: DW_CFA_nop
-; FRAMES-NEXT: DW_CFA_nop
+; FRAMES:      DW_CFA_def_cfa: reg4 +4
+; FRAMES-NEXT: DW_CFA_offset: reg8 -4
+; FRAMES-NEXT: DW_CFA_nop:
+; FRAMES-NEXT: DW_CFA_nop:
 
 ; FRAMES: 00000014 00000010 00000000 FDE cie=00000000 pc=00000000...00000022
-; FRAMES:      DW_CFA_advance_loc
-; FRAMES-NEXT: DW_CFA_def_cfa_offset
-; FRAMES-NEXT: DW_CFA_nop
+; FRAMES:      DW_CFA_advance_loc: 3
+; FRAMES-NEXT: DW_CFA_def_cfa_offset: +12
+; FRAMES-NEXT: DW_CFA_nop:
 
 ; FRAMES: 00000028 00000014 00000000 FDE cie=00000000 pc=00000030...00000080
-; FRAMES:      DW_CFA_advance_loc
-; FRAMES-NEXT: DW_CFA_def_cfa_offset
-; FRAMES-NEXT: DW_CFA_offset
-; FRAMES-NEXT: DW_CFA_advance_loc
-; FRAMES-NEXT: DW_CFA_def_cfa_register
+; FRAMES:      DW_CFA_advance_loc: 1
+; FRAMES-NEXT: DW_CFA_def_cfa_offset: +8
+; FRAMES-NEXT: DW_CFA_offset: reg5 -8
+; FRAMES-NEXT: DW_CFA_advance_loc: 2
+; FRAMES-NEXT: DW_CFA_def_cfa_register: reg5
 
 ; FRAMES-NOT: CIE
 ; FRAMES-NOT: FDE
diff --git a/test/DebugInfo/empty.ll b/test/DebugInfo/empty.ll
index 3f7f5463478c..ad26b500b354 100644
--- a/test/DebugInfo/empty.ll
+++ b/test/DebugInfo/empty.ll
@@ -24,8 +24,8 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!5}
 
-!0 = !{!"0x11\0012\00clang version 3.1 (trunk 143523)\001\00\000\00\000", !4, !2, !2, !2, !2, null} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.1 (trunk 143523)", isOptimized: true, emissionKind: 0, file: !4, enums: !2, retainedTypes: !2, subprograms: !2, globals: !2)
 !2 = !{}
-!3 = !{!"0x29", !4} ; [ DW_TAG_file_type ]
-!4 = !{!"empty.c", !"/home/nlewycky"}
-!5 = !{i32 1, !"Debug Info Version", i32 2}
+!3 = !DIFile(filename: "empty.c", directory: "/home/nlewycky")
+!4 = !DIFile(filename: "empty.c", directory: "/home/nlewycky")
+!5 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/enum-types.ll b/test/DebugInfo/enum-types.ll
index 3932535b4c46..7b50f5e9087c 100644
--- a/test/DebugInfo/enum-types.ll
+++ b/test/DebugInfo/enum-types.ll
@@ -25,7 +25,7 @@ define void @_Z4topA2EA(i32 %sa) #0 {
 entry:
   %sa.addr = alloca i32, align 4
   store i32 %sa, i32* %sa.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %sa.addr, metadata !22, metadata !{!"0x102"}), !dbg !23
+  call void @llvm.dbg.declare(metadata i32* %sa.addr, metadata !22, metadata !DIExpression()), !dbg !23
   ret void, !dbg !24
 }
 
@@ -37,7 +37,7 @@ define void @_Z4topB2EA(i32 %sa) #0 {
 entry:
   %sa.addr = alloca i32, align 4
   store i32 %sa, i32* %sa.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %sa.addr, metadata !25, metadata !{!"0x102"}), !dbg !26
+  call void @llvm.dbg.declare(metadata i32* %sa.addr, metadata !25, metadata !DIExpression()), !dbg !26
   ret void, !dbg !27
 }
 
@@ -48,31 +48,31 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!19, !20}
 !llvm.ident = !{!21, !21}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 (trunk 214102:214133) (llvm/trunk 214102:214132)\000\00\000\00\001", !1, !2, !2, !6, !11, !11} ; [ DW_TAG_compile_unit ] [<unknown>] [DW_LANG_C_plus_plus]
-!1 = !{!"a.cpp", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 (trunk 214102:214133) (llvm/trunk 214102:214132)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !6, globals: !11, imports: !11)
+!1 = !DIFile(filename: "a.cpp", directory: "")
 !2 = !{!3}
-!3 = !{!"0x4\00EA\001\0032\0032\000\000\000", !1, null, null, !4, null, null, !"_ZTS2EA"} ; [ DW_TAG_enumeration_type ] [EA] [line 1, size 32, align 32, offset 0] [def] [from ]
+!3 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "EA", line: 1, size: 32, align: 32, file: !1, elements: !4, identifier: "_ZTS2EA")
 !4 = !{!5}
-!5 = !{!"0x28\00EA_0\000"} ; [ DW_TAG_enumerator ] [EA_0 :: 0]
+!5 = !DIEnumerator(name: "EA_0", value: 0) ; [ DW_TAG_enumerator ] [EA_0 :: 0]
 !6 = !{!7}
-!7 = !{!"0x2e\00topA\00topA\00_Z4topA2EA\005\000\001\000\006\00256\000\005", !1, !8, !9, null, void (i32)* @_Z4topA2EA, null, null, !11} ; [ DW_TAG_subprogram ] [line 5] [def] [topA]
-!8 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [a.cpp]
-!9 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = !DISubprogram(name: "topA", linkageName: "_Z4topA2EA", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !8, type: !9, function: void (i32)* @_Z4topA2EA, variables: !11)
+!8 = !DIFile(filename: "a.cpp", directory: "")
+!9 = !DISubroutineType(types: !10)
 !10 = !{null, !"_ZTS2EA"}
 !11 = !{}
-!12 = !{!"0x11\004\00clang version 3.5.0 (trunk 214102:214133) (llvm/trunk 214102:214132)\000\00\000\00\001", !13, !14, !14, !16, !11, !11} ; [ DW_TAG_compile_unit ] [b.cpp] [DW_LANG_C_plus_plus]
-!13 = !{!"b.cpp", !""}
+!12 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 (trunk 214102:214133) (llvm/trunk 214102:214132)", isOptimized: false, emissionKind: 1, file: !13, enums: !14, retainedTypes: !14, subprograms: !16, globals: !11, imports: !11)
+!13 = !DIFile(filename: "b.cpp", directory: "")
 !14 = !{!15}
-!15 = !{!"0x4\00EA\001\0032\0032\000\000\000", !13, null, null, !4, null, null, !"_ZTS2EA"} ; [ DW_TAG_enumeration_type ] [EA] [line 1, size 32, align 32, offset 0] [def] [from ]
+!15 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "EA", line: 1, size: 32, align: 32, file: !13, elements: !4, identifier: "_ZTS2EA")
 !16 = !{!17}
-!17 = !{!"0x2e\00topB\00topB\00_Z4topB2EA\005\000\001\000\006\00256\000\005", !13, !18, !9, null, void (i32)* @_Z4topB2EA, null, null, !11} ; [ DW_TAG_subprogram ] [line 5] [def] [topB]
-!18 = !{!"0x29", !13}        ; [ DW_TAG_file_type ] [b.cpp]
+!17 = !DISubprogram(name: "topB", linkageName: "_Z4topB2EA", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !13, scope: !18, type: !9, function: void (i32)* @_Z4topB2EA, variables: !11)
+!18 = !DIFile(filename: "b.cpp", directory: "")
 !19 = !{i32 2, !"Dwarf Version", i32 2}
-!20 = !{i32 2, !"Debug Info Version", i32 2}
+!20 = !{i32 2, !"Debug Info Version", i32 3}
 !21 = !{!"clang version 3.5.0 (trunk 214102:214133) (llvm/trunk 214102:214132)"}
-!22 = !{!"0x101\00sa\0016777221\000", !7, !8, !"_ZTS2EA"} ; [ DW_TAG_arg_variable ] [sa] [line 5]
-!23 = !MDLocation(line: 5, column: 14, scope: !7)
-!24 = !MDLocation(line: 6, column: 1, scope: !7)
-!25 = !{!"0x101\00sa\0016777221\000", !17, !18, !"_ZTS2EA"} ; [ DW_TAG_arg_variable ] [sa] [line 5]
-!26 = !MDLocation(line: 5, column: 14, scope: !17)
-!27 = !MDLocation(line: 6, column: 1, scope: !17)
+!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "sa", line: 5, arg: 1, scope: !7, file: !8, type: !"_ZTS2EA")
+!23 = !DILocation(line: 5, column: 14, scope: !7)
+!24 = !DILocation(line: 6, column: 1, scope: !7)
+!25 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "sa", line: 5, arg: 1, scope: !17, file: !18, type: !"_ZTS2EA")
+!26 = !DILocation(line: 5, column: 14, scope: !17)
+!27 = !DILocation(line: 6, column: 1, scope: !17)
diff --git a/test/DebugInfo/enum.ll b/test/DebugInfo/enum.ll
index 4dd4c688ad67..fd07a92ae41b 100644
--- a/test/DebugInfo/enum.ll
+++ b/test/DebugInfo/enum.ll
@@ -39,7 +39,7 @@
 define void @_Z4funcv() #0 {
 entry:
   %b = alloca i32, align 4
-  call void @llvm.dbg.declare(metadata i32* %b, metadata !20, metadata !{!"0x102"}), !dbg !22
+  call void @llvm.dbg.declare(metadata i32* %b, metadata !20, metadata !DIExpression()), !dbg !22
   store i32 0, i32* %b, align 4, !dbg !22
   ret void, !dbg !23
 }
@@ -53,28 +53,28 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!19, !24}
 
-!0 = !{!"0x11\004\00clang version 3.4 \000\00\000\00\000", !1, !2, !11, !12, !17, !11} ; [ DW_TAG_compile_unit ] [/tmp/enum.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"enum.cpp", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !11, subprograms: !12, globals: !17, imports: !11)
+!1 = !DIFile(filename: "enum.cpp", directory: "/tmp")
 !2 = !{!3, !8}
-!3 = !{!"0x4\00e1\001\0064\0064\000\000\000", !1, null, null, !4, null, null, null} ; [ DW_TAG_enumeration_type ] [e1] [line 1, size 64, align 64, offset 0] [def] [from ]
+!3 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "e1", line: 1, size: 64, align: 64, file: !1, elements: !4)
 !4 = !{!5, !6, !7}
-!5 = !{!"0x28\00I\000"} ; [ DW_TAG_enumerator ] [I :: 0]
-!6 = !{!"0x28\00J\004294967295"} ; [ DW_TAG_enumerator ] [J :: 4294967295]
-!7 = !{!"0x28\00K\00-1152921504606846976"} ; [ DW_TAG_enumerator ] [K :: 17293822569102704640]
-!8 = !{!"0x4\00e2\002\0032\0032\000\000\000", !1, null, null, !9, null, null, null} ; [ DW_TAG_enumeration_type ] [e2] [line 2, size 32, align 32, offset 0] [def] [from ]
+!5 = !DIEnumerator(name: "I", value: 0) ; [ DW_TAG_enumerator ] [I :: 0]
+!6 = !DIEnumerator(name: "J", value: 4294967295) ; [ DW_TAG_enumerator ] [J :: 4294967295]
+!7 = !DIEnumerator(name: "K", value: -1152921504606846976) ; [ DW_TAG_enumerator ] [K :: 17293822569102704640]
+!8 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "e2", line: 2, size: 32, align: 32, file: !1, elements: !9)
 !9 = !{!10}
-!10 = !{!"0x28\00X\000"} ; [ DW_TAG_enumerator ] [X :: 0]
+!10 = !DIEnumerator(name: "X", value: 0) ; [ DW_TAG_enumerator ] [X :: 0]
 !11 = !{}
 !12 = !{!13}
-!13 = !{!"0x2e\00func\00func\00_Z4funcv\003\000\001\000\006\00256\000\003", !1, !14, !15, null, void ()* @_Z4funcv, null, null, !11} ; [ DW_TAG_subprogram ] [line 3] [def] [func]
-!14 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/tmp/enum.cpp]
-!15 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DISubprogram(name: "func", linkageName: "_Z4funcv", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !14, type: !15, function: void ()* @_Z4funcv, variables: !11)
+!14 = !DIFile(filename: "enum.cpp", directory: "/tmp")
+!15 = !DISubroutineType(types: !16)
 !16 = !{null}
 !17 = !{!18}
-!18 = !{!"0x34\00a\00a\00\001\000\001", null, !14, !3, i64* @a, null} ; [ DW_TAG_variable ] [a] [line 1] [def]
+!18 = !DIGlobalVariable(name: "a", line: 1, isLocal: false, isDefinition: true, scope: null, file: !14, type: !3, variable: i64* @a)
 !19 = !{i32 2, !"Dwarf Version", i32 3}
-!20 = !{!"0x100\00b\004\000", !13, !14, !21} ; [ DW_TAG_auto_variable ] [b] [line 4]
-!21 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!22 = !MDLocation(line: 4, scope: !13)
-!23 = !MDLocation(line: 5, scope: !13)
-!24 = !{i32 1, !"Debug Info Version", i32 2}
+!20 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 4, scope: !13, file: !14, type: !21)
+!21 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!22 = !DILocation(line: 4, scope: !13)
+!23 = !DILocation(line: 5, scope: !13)
+!24 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/global.ll b/test/DebugInfo/global.ll
index 1715ca8388af..cf2d26b36acd 100644
--- a/test/DebugInfo/global.ll
+++ b/test/DebugInfo/global.ll
@@ -26,17 +26,17 @@ attributes #0 = { nounwind readnone uwtable "less-precise-fpmad"="false" "no-fra
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!11, !13}
 
-!0 = !{!"0x11\004\00clang version 3.4 \001\00\000\00\000", !1, !2, !2, !3, !9, !2} ; [ DW_TAG_compile_unit ] [/tmp/global.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"global.cpp", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 ", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !9, imports: !2)
+!1 = !DIFile(filename: "global.cpp", directory: "/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00main\00main\00\002\000\001\000\006\00256\001\002", !1, !5, !6, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [main]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/global.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "main", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2, file: !1, scope: !5, type: !6, function: i32 ()* @main, variables: !2)
+!5 = !DIFile(filename: "global.cpp", directory: "/tmp")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{!10}
-!10 = !{!"0x34\00i\00i\00_ZL1i\001\001\001", null, !5, !8, null, null} ; [ DW_TAG_variable ]
+!10 = !DIGlobalVariable(name: "i", linkageName: "_ZL1i", line: 1, isLocal: true, isDefinition: true, scope: null, file: !5, type: !8)
 !11 = !{i32 2, !"Dwarf Version", i32 3}
-!12 = !MDLocation(line: 4, scope: !4)
-!13 = !{i32 1, !"Debug Info Version", i32 2}
+!12 = !DILocation(line: 4, scope: !4)
+!13 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/incorrect-variable-debugloc.ll b/test/DebugInfo/incorrect-variable-debugloc.ll
index afccd672f90c..930f8c92cf65 100644
--- a/test/DebugInfo/incorrect-variable-debugloc.ll
+++ b/test/DebugInfo/incorrect-variable-debugloc.ll
@@ -62,7 +62,7 @@ define i32 @_Z3fn1v() #0 {
 entry:
   %MyAlloca = alloca [64 x i8], align 32, !dbg !39
   %0 = ptrtoint [64 x i8]* %MyAlloca to i64, !dbg !39
-  %1 = load i32* @__asan_option_detect_stack_use_after_return, !dbg !39
+  %1 = load i32, i32* @__asan_option_detect_stack_use_after_return, !dbg !39
   %2 = icmp ne i32 %1, 0, !dbg !39
   br i1 %2, label %3, label %5
 
@@ -87,12 +87,12 @@ entry:
   %16 = add i64 %15, 0, !dbg !39
   %17 = inttoptr i64 %16 to i64*, !dbg !39
   store i64 -868083117767659023, i64* %17, !dbg !39
-  %i.i = getelementptr inbounds %struct.C* %8, i64 0, i32 1, i32 0, !dbg !39
+  %i.i = getelementptr inbounds %struct.C, %struct.C* %8, i64 0, i32 1, i32 0, !dbg !39
   %18 = ptrtoint i32* %i.i to i64, !dbg !39
   %19 = lshr i64 %18, 3, !dbg !39
   %20 = add i64 %19, 2147450880, !dbg !39
   %21 = inttoptr i64 %20 to i8*, !dbg !39
-  %22 = load i8* %21, !dbg !39
+  %22 = load i8, i8* %21, !dbg !39
   %23 = icmp ne i8 %22, 0, !dbg !39
   br i1 %23, label %24, label %30, !dbg !39
 
@@ -110,7 +110,7 @@ entry:
 
 ; <label>:30                                      ; preds = %24, %5
   store i32 0, i32* %i.i, align 4, !dbg !39, !tbaa !41
-  tail call void @llvm.dbg.value(metadata %struct.C* %8, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !46
+  tail call void @llvm.dbg.value(metadata %struct.C* %8, i64 0, metadata !27, metadata !DIExpression()), !dbg !46
   call void @_ZN1C5m_fn3Ev(%struct.C* %8), !dbg !47
   unreachable, !dbg !47
 }
@@ -120,7 +120,7 @@ define void @_ZN1C5m_fn3Ev(%struct.C* nocapture %this) #1 align 2 {
 entry:
   %MyAlloca = alloca [64 x i8], align 32, !dbg !48
   %0 = ptrtoint [64 x i8]* %MyAlloca to i64, !dbg !48
-  %1 = load i32* @__asan_option_detect_stack_use_after_return, !dbg !48
+  %1 = load i32, i32* @__asan_option_detect_stack_use_after_return, !dbg !48
   %2 = icmp ne i32 %1, 0, !dbg !48
   br i1 %2, label %3, label %5
 
@@ -145,14 +145,14 @@ entry:
   %16 = add i64 %15, 0, !dbg !48
   %17 = inttoptr i64 %16 to i64*, !dbg !48
   store i64 -868083113472691727, i64* %17, !dbg !48
-  tail call void @llvm.dbg.value(metadata %struct.C* %this, i64 0, metadata !30, metadata !{!"0x102"}), !dbg !48
+  tail call void @llvm.dbg.value(metadata %struct.C* %this, i64 0, metadata !30, metadata !DIExpression()), !dbg !48
   %call = call i32 @_ZN1A5m_fn1Ev(%struct.A* %8), !dbg !49
-  %i.i = getelementptr inbounds %struct.C* %this, i64 0, i32 1, i32 0, !dbg !50
+  %i.i = getelementptr inbounds %struct.C, %struct.C* %this, i64 0, i32 1, i32 0, !dbg !50
   %18 = ptrtoint i32* %i.i to i64, !dbg !50
   %19 = lshr i64 %18, 3, !dbg !50
   %20 = add i64 %19, 2147450880, !dbg !50
   %21 = inttoptr i64 %20 to i8*, !dbg !50
-  %22 = load i8* %21, !dbg !50
+  %22 = load i8, i8* %21, !dbg !50
   %23 = icmp ne i8 %22, 0, !dbg !50
   br i1 %23, label %24, label %30, !dbg !50
 
@@ -180,7 +180,7 @@ entry:
   store i64 -723401728380766731, i64* %34, !dbg !52
   %35 = add i64 %6, 56, !dbg !52
   %36 = inttoptr i64 %35 to i64*, !dbg !52
-  %37 = load i64* %36, !dbg !52
+  %37 = load i64, i64* %36, !dbg !52
   %38 = inttoptr i64 %37 to i8*, !dbg !52
   store i8 0, i8* %38, !dbg !52
   br label %42, !dbg !52
@@ -336,56 +336,56 @@ attributes #3 = { nounwind readnone }
 !llvm.module.flags = !{!36, !37}
 !llvm.ident = !{!38}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \001\00\000\00\001", !1, !2, !3, !21, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/<stdin>] [DW_LANG_C_plus_plus]
-!1 = !{!"<stdin>", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !21, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<stdin>", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4, !14}
-!4 = !{!"0x13\00C\0010\0064\0032\000\000\000", !5, null, null, !6, null, null, !"_ZTS1C"} ; [ DW_TAG_structure_type ] [C] [line 10, size 64, align 32, offset 0] [def] [from ]
-!5 = !{!"incorrect-variable-debug-loc.cpp", !"/tmp/dbginfo"}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "C", line: 10, size: 64, align: 32, file: !5, elements: !6, identifier: "_ZTS1C")
+!5 = !DIFile(filename: "incorrect-variable-debug-loc.cpp", directory: "/tmp/dbginfo")
 !6 = !{!7, !9, !10}
-!7 = !{!"0xd\00j\0012\0032\0032\000\000", !5, !"_ZTS1C", !8} ; [ DW_TAG_member ] [j] [line 12, size 32, align 32, offset 0] [from int]
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0xd\00b\0013\0032\0032\0032\000", !5, !"_ZTS1C", !"_ZTS1B"} ; [ DW_TAG_member ] [b] [line 13, size 32, align 32, offset 32] [from _ZTS1B]
-!10 = !{!"0x2e\00m_fn3\00m_fn3\00_ZN1C5m_fn3Ev\0011\000\000\000\006\00256\001\0011", !5, !"_ZTS1C", !11, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 11] [m_fn3]
-!11 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "j", line: 12, size: 32, align: 32, file: !5, scope: !"_ZTS1C", baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 13, size: 32, align: 32, offset: 32, file: !5, scope: !"_ZTS1C", baseType: !"_ZTS1B")
+!10 = !DISubprogram(name: "m_fn3", linkageName: "_ZN1C5m_fn3Ev", line: 11, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !5, scope: !"_ZTS1C", type: !11)
+!11 = !DISubroutineType(types: !12)
 !12 = !{null, !13}
-!13 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1C"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1C]
-!14 = !{!"0x13\00B\005\0032\0032\000\000\000", !5, null, null, !15, null, null, !"_ZTS1B"} ; [ DW_TAG_structure_type ] [B] [line 5, size 32, align 32, offset 0] [def] [from ]
+!13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1C")
+!14 = !DICompositeType(tag: DW_TAG_structure_type, name: "B", line: 5, size: 32, align: 32, file: !5, elements: !15, identifier: "_ZTS1B")
 !15 = !{!16, !17}
-!16 = !{!"0xd\00i\007\0032\0032\000\000", !5, !"_ZTS1B", !8} ; [ DW_TAG_member ] [i] [line 7, size 32, align 32, offset 0] [from int]
-!17 = !{!"0x2e\00m_fn2\00m_fn2\00_ZN1B5m_fn2Ev\006\000\000\000\006\00256\001\006", !5, !"_ZTS1B", !18, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 6] [m_fn2]
-!18 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !19, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!16 = !DIDerivedType(tag: DW_TAG_member, name: "i", line: 7, size: 32, align: 32, file: !5, scope: !"_ZTS1B", baseType: !8)
+!17 = !DISubprogram(name: "m_fn2", linkageName: "_ZN1B5m_fn2Ev", line: 6, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 6, file: !5, scope: !"_ZTS1B", type: !18)
+!18 = !DISubroutineType(types: !19)
 !19 = !{null, !20}
-!20 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1B"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1B]
+!20 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1B")
 !21 = !{!22, !28, !32}
-!22 = !{!"0x2e\00fn1\00fn1\00_Z3fn1v\0016\000\001\000\006\00256\001\0016", !5, !23, !24, null, i32 ()* @_Z3fn1v, null, null, !26} ; [ DW_TAG_subprogram ] [line 16] [def] [fn1]
-!23 = !{!"0x29", !5}         ; [ DW_TAG_file_type ] [/tmp/dbginfo/incorrect-variable-debug-loc.cpp]
-!24 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !25, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!22 = !DISubprogram(name: "fn1", linkageName: "_Z3fn1v", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 16, file: !5, scope: !23, type: !24, function: i32 ()* @_Z3fn1v, variables: !26)
+!23 = !DIFile(filename: "incorrect-variable-debug-loc.cpp", directory: "/tmp/dbginfo")
+!24 = !DISubroutineType(types: !25)
 !25 = !{!8}
 !26 = !{!27}
-!27 = !{!"0x100\00A\0017\000", !22, !23, !"_ZTS1C"} ; [ DW_TAG_auto_variable ] [A] [line 17]
-!28 = !{!"0x2e\00m_fn3\00m_fn3\00_ZN1C5m_fn3Ev\0021\000\001\000\006\00256\001\0021", !5, !"_ZTS1C", !11, null, void (%struct.C*)* @_ZN1C5m_fn3Ev, null, !10, !29} ; [ DW_TAG_subprogram ] [line 21] [def] [m_fn3]
+!27 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "A", line: 17, scope: !22, file: !23, type: !"_ZTS1C")
+!28 = !DISubprogram(name: "m_fn3", linkageName: "_ZN1C5m_fn3Ev", line: 21, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 21, file: !5, scope: !"_ZTS1C", type: !11, function: void (%struct.C*)* @_ZN1C5m_fn3Ev, declaration: !10, variables: !29)
 !29 = !{!30}
-!30 = !{!"0x101\00this\0016777216\001088", !28, null, !31} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!31 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1C"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1C]
-!32 = !{!"0x2e\00m_fn2\00m_fn2\00_ZN1B5m_fn2Ev\006\000\001\000\006\00256\001\006", !5, !"_ZTS1B", !18, null, null, null, !17, !33} ; [ DW_TAG_subprogram ] [line 6] [def] [m_fn2]
+!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !28, type: !31)
+!31 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1C")
+!32 = !DISubprogram(name: "m_fn2", linkageName: "_ZN1B5m_fn2Ev", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 6, file: !5, scope: !"_ZTS1B", type: !18, declaration: !17, variables: !33)
 !33 = !{!34}
-!34 = !{!"0x101\00this\0016777216\001088", !32, null, !35} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!35 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1B"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1B]
+!34 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !32, type: !35)
+!35 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1B")
 !36 = !{i32 2, !"Dwarf Version", i32 4}
-!37 = !{i32 2, !"Debug Info Version", i32 2}
+!37 = !{i32 2, !"Debug Info Version", i32 3}
 !38 = !{!"clang version 3.5.0 "}
-!39 = !MDLocation(line: 6, scope: !32, inlinedAt: !40)
-!40 = !MDLocation(line: 18, scope: !22)
+!39 = !DILocation(line: 6, scope: !32, inlinedAt: !40)
+!40 = !DILocation(line: 18, scope: !22)
 !41 = !{!42, !43, i64 0}
 !42 = !{!"_ZTS1B", !43, i64 0}
 !43 = !{!"int", !44, i64 0}
 !44 = !{!"omnipotent char", !45, i64 0}
 !45 = !{!"Simple C/C++ TBAA"}
-!46 = !MDLocation(line: 17, scope: !22)
-!47 = !MDLocation(line: 19, scope: !22)
-!48 = !MDLocation(line: 0, scope: !28)
-!49 = !MDLocation(line: 22, scope: !28)
-!50 = !MDLocation(line: 6, scope: !32, inlinedAt: !51)
-!51 = !MDLocation(line: 23, scope: !28)
-!52 = !MDLocation(line: 24, scope: !28)
+!46 = !DILocation(line: 17, scope: !22)
+!47 = !DILocation(line: 19, scope: !22)
+!48 = !DILocation(line: 0, scope: !28)
+!49 = !DILocation(line: 22, scope: !28)
+!50 = !DILocation(line: 6, scope: !32, inlinedAt: !51)
+!51 = !DILocation(line: 23, scope: !28)
+!52 = !DILocation(line: 24, scope: !28)
diff --git a/test/DebugInfo/incorrect-variable-debugloc1.ll b/test/DebugInfo/incorrect-variable-debugloc1.ll
index 18f2dc78e3e8..3ece94ac8884 100644
--- a/test/DebugInfo/incorrect-variable-debugloc1.ll
+++ b/test/DebugInfo/incorrect-variable-debugloc1.ll
@@ -36,7 +36,7 @@ entry:
   tail call void @llvm.dbg.value(metadata i32 %call, i64 0, metadata !10, metadata !16), !dbg !17
   store volatile i32 %call, i32* %c, align 4, !dbg !19
   tail call void @llvm.dbg.value(metadata i32* %c, i64 0, metadata !10, metadata !16), !dbg !17
-  %c.0.c.0. = load volatile i32* %c, align 4, !dbg !20
+  %c.0.c.0. = load volatile i32, i32* %c, align 4, !dbg !20
   ret i32 %c.0.c.0., !dbg !20
 }
 
@@ -53,25 +53,25 @@ attributes #2 = { nounwind readnone }
 !llvm.module.flags = !{!12, !13}
 !llvm.ident = !{!14}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 (trunk 223522)\001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/home/kromanova/ngh/ToT_latest/llvm/test/DebugInfo/test.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"test.cpp", !"/home/kromanova/ngh/ToT_latest/llvm/test/DebugInfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 (trunk 223522)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.cpp", directory: "/home/kromanova/ngh/ToT_latest/llvm/test/DebugInfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00main\00main\00\003\000\001\000\000\00256\001\004", !1, !5, !6, null, i32 ()* @main, null, null, !9} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 4] [main]
-!5 = !{!"0x29", !1}    ; [ DW_TAG_file_type ] [/home/kromanova/ngh/ToT_latest/llvm/test/DebugInfo/test.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "main", line: 3, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 4, file: !1, scope: !5, type: !6, function: i32 ()* @main, variables: !9)
+!5 = !DIFile(filename: "test.cpp", directory: "/home/kromanova/ngh/ToT_latest/llvm/test/DebugInfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{!10}
-!10 = !{!"0x100\00c\005\000", !4, !5, !11} ; [ DW_TAG_auto_variable ] [c] [line 5]
-!11 = !{!"0x35\00\000\000\000\000\000", null, null, !8} ; [ DW_TAG_volatile_type ] [line 0, size 0, align 0, offset 0] [from int]
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "c", line: 5, scope: !4, file: !5, type: !11)
+!11 = !DIDerivedType(tag: DW_TAG_volatile_type, baseType: !8)
 !12 = !{i32 2, !"Dwarf Version", i32 2}
-!13 = !{i32 2, !"Debug Info Version", i32 2}
+!13 = !{i32 2, !"Debug Info Version", i32 3}
 !14 = !{!"clang version 3.6.0 (trunk 223522)"}
 !15 = !{i32 13}
-!16 = !{!"0x102"}               ; [ DW_TAG_expression ]
-!17 = !MDLocation(line: 5, column: 16, scope: !4)
-!18 = !MDLocation(line: 5, column: 3, scope: !4)
-!19 = !MDLocation(line: 6, column: 7, scope: !4)
-!20 = !MDLocation(line: 7, column: 3, scope: !4)
+!16 = !DIExpression()
+!17 = !DILocation(line: 5, column: 16, scope: !4)
+!18 = !DILocation(line: 5, column: 3, scope: !4)
+!19 = !DILocation(line: 6, column: 7, scope: !4)
+!20 = !DILocation(line: 7, column: 3, scope: !4)
 
diff --git a/test/DebugInfo/inheritance.ll b/test/DebugInfo/inheritance.ll
index ab71d25d625a..8a29d2e576a0 100644
--- a/test/DebugInfo/inheritance.ll
+++ b/test/DebugInfo/inheritance.ll
@@ -6,7 +6,7 @@
 %struct.test1 = type { i32 (...)** }
 
 @_ZTV5test1 = weak_odr constant [4 x i32 (...)*] [i32 (...)* null, i32 (...)* bitcast (%struct.__class_type_info_pseudo* @_ZTI5test1 to i32 (...)*), i32 (...)* bitcast (void (%struct.test1*)* @_ZN5test1D1Ev to i32 (...)*), i32 (...)* bitcast (void (%struct.test1*)* @_ZN5test1D0Ev to i32 (...)*)], align 32 ; <[4 x i32 (...)*]*> [#uses=1]
-@_ZTI5test1 = weak_odr constant %struct.__class_type_info_pseudo { %struct.__type_info_pseudo { i8* inttoptr (i64 add (i64 ptrtoint ([0 x i32 (...)*]* @_ZTVN10__cxxabiv117__class_type_infoE to i64), i64 16) to i8*), i8* getelementptr inbounds ([7 x i8]* @_ZTS5test1, i64 0, i64 0) } }, align 16 ; <%struct.__class_type_info_pseudo*> [#uses=1]
+@_ZTI5test1 = weak_odr constant %struct.__class_type_info_pseudo { %struct.__type_info_pseudo { i8* inttoptr (i64 add (i64 ptrtoint ([0 x i32 (...)*]* @_ZTVN10__cxxabiv117__class_type_infoE to i64), i64 16) to i8*), i8* getelementptr inbounds ([7 x i8], [7 x i8]* @_ZTS5test1, i64 0, i64 0) } }, align 16 ; <%struct.__class_type_info_pseudo*> [#uses=1]
 @_ZTVN10__cxxabiv117__class_type_infoE = external constant [0 x i32 (...)*] ; <[0 x i32 (...)*]*> [#uses=1]
 @_ZTS5test1 = weak_odr constant [7 x i8] c"5test1\00" ; <[7 x i8]*> [#uses=2]
 
@@ -16,15 +16,15 @@ entry:
   %0 = alloca i32                                 ; <i32*> [#uses=2]
   %tst = alloca %struct.test1                     ; <%struct.test1*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.declare(metadata %struct.test1* %tst, metadata !0, metadata !{!"0x102"}), !dbg !21
+  call void @llvm.dbg.declare(metadata %struct.test1* %tst, metadata !0, metadata !DIExpression()), !dbg !21
   call void @_ZN5test1C1Ev(%struct.test1* %tst) nounwind, !dbg !22
   store i32 0, i32* %0, align 4, !dbg !23
-  %1 = load i32* %0, align 4, !dbg !23            ; <i32> [#uses=1]
+  %1 = load i32, i32* %0, align 4, !dbg !23            ; <i32> [#uses=1]
   store i32 %1, i32* %retval, align 4, !dbg !23
   br label %return, !dbg !23
 
 return:                                           ; preds = %entry
-  %retval1 = load i32* %retval, !dbg !23          ; <i32> [#uses=1]
+  %retval1 = load i32, i32* %retval, !dbg !23          ; <i32> [#uses=1]
   ret i32 %retval1, !dbg !23
 }
 
@@ -32,11 +32,11 @@ define linkonce_odr void @_ZN5test1C1Ev(%struct.test1* %this) nounwind ssp align
 entry:
   %this_addr = alloca %struct.test1*              ; <%struct.test1**> [#uses=2]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.declare(metadata %struct.test1** %this_addr, metadata !24, metadata !{!"0x102"}), !dbg !28
+  call void @llvm.dbg.declare(metadata %struct.test1** %this_addr, metadata !24, metadata !DIExpression()), !dbg !28
   store %struct.test1* %this, %struct.test1** %this_addr
-  %0 = load %struct.test1** %this_addr, align 8, !dbg !28 ; <%struct.test1*> [#uses=1]
-  %1 = getelementptr inbounds %struct.test1* %0, i32 0, i32 0, !dbg !28 ; <i32 (...)***> [#uses=1]
-  store i32 (...)** getelementptr inbounds ([4 x i32 (...)*]* @_ZTV5test1, i64 0, i64 2), i32 (...)*** %1, align 8, !dbg !28
+  %0 = load %struct.test1*, %struct.test1** %this_addr, align 8, !dbg !28 ; <%struct.test1*> [#uses=1]
+  %1 = getelementptr inbounds %struct.test1, %struct.test1* %0, i32 0, i32 0, !dbg !28 ; <i32 (...)***> [#uses=1]
+  store i32 (...)** getelementptr inbounds ([4 x i32 (...)*], [4 x i32 (...)*]* @_ZTV5test1, i64 0, i64 2), i32 (...)*** %1, align 8, !dbg !28
   br label %return, !dbg !28
 
 return:                                           ; preds = %entry
@@ -49,11 +49,11 @@ define linkonce_odr void @_ZN5test1D1Ev(%struct.test1* %this) nounwind ssp align
 entry:
   %this_addr = alloca %struct.test1*              ; <%struct.test1**> [#uses=3]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.declare(metadata %struct.test1** %this_addr, metadata !32, metadata !{!"0x102"}), !dbg !34
+  call void @llvm.dbg.declare(metadata %struct.test1** %this_addr, metadata !32, metadata !DIExpression()), !dbg !34
   store %struct.test1* %this, %struct.test1** %this_addr
-  %0 = load %struct.test1** %this_addr, align 8, !dbg !35 ; <%struct.test1*> [#uses=1]
-  %1 = getelementptr inbounds %struct.test1* %0, i32 0, i32 0, !dbg !35 ; <i32 (...)***> [#uses=1]
-  store i32 (...)** getelementptr inbounds ([4 x i32 (...)*]* @_ZTV5test1, i64 0, i64 2), i32 (...)*** %1, align 8, !dbg !35
+  %0 = load %struct.test1*, %struct.test1** %this_addr, align 8, !dbg !35 ; <%struct.test1*> [#uses=1]
+  %1 = getelementptr inbounds %struct.test1, %struct.test1* %0, i32 0, i32 0, !dbg !35 ; <i32 (...)***> [#uses=1]
+  store i32 (...)** getelementptr inbounds ([4 x i32 (...)*], [4 x i32 (...)*]* @_ZTV5test1, i64 0, i64 2), i32 (...)*** %1, align 8, !dbg !35
   br label %bb, !dbg !37
 
 bb:                                               ; preds = %entry
@@ -62,7 +62,7 @@ bb:                                               ; preds = %entry
   br i1 %toBool, label %bb1, label %bb2, !dbg !37
 
 bb1:                                              ; preds = %bb
-  %3 = load %struct.test1** %this_addr, align 8, !dbg !37 ; <%struct.test1*> [#uses=1]
+  %3 = load %struct.test1*, %struct.test1** %this_addr, align 8, !dbg !37 ; <%struct.test1*> [#uses=1]
   %4 = bitcast %struct.test1* %3 to i8*, !dbg !37 ; <i8*> [#uses=1]
   call void @_ZdlPv(i8* %4) nounwind, !dbg !37
   br label %bb2, !dbg !37
@@ -78,11 +78,11 @@ define linkonce_odr void @_ZN5test1D0Ev(%struct.test1* %this) nounwind ssp align
 entry:
   %this_addr = alloca %struct.test1*              ; <%struct.test1**> [#uses=3]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.declare(metadata %struct.test1** %this_addr, metadata !38, metadata !{!"0x102"}), !dbg !40
+  call void @llvm.dbg.declare(metadata %struct.test1** %this_addr, metadata !38, metadata !DIExpression()), !dbg !40
   store %struct.test1* %this, %struct.test1** %this_addr
-  %0 = load %struct.test1** %this_addr, align 8, !dbg !41 ; <%struct.test1*> [#uses=1]
-  %1 = getelementptr inbounds %struct.test1* %0, i32 0, i32 0, !dbg !41 ; <i32 (...)***> [#uses=1]
-  store i32 (...)** getelementptr inbounds ([4 x i32 (...)*]* @_ZTV5test1, i64 0, i64 2), i32 (...)*** %1, align 8, !dbg !41
+  %0 = load %struct.test1*, %struct.test1** %this_addr, align 8, !dbg !41 ; <%struct.test1*> [#uses=1]
+  %1 = getelementptr inbounds %struct.test1, %struct.test1* %0, i32 0, i32 0, !dbg !41 ; <i32 (...)***> [#uses=1]
+  store i32 (...)** getelementptr inbounds ([4 x i32 (...)*], [4 x i32 (...)*]* @_ZTV5test1, i64 0, i64 2), i32 (...)*** %1, align 8, !dbg !41
   br label %bb, !dbg !43
 
 bb:                                               ; preds = %entry
@@ -91,7 +91,7 @@ bb:                                               ; preds = %entry
   br i1 %toBool, label %bb1, label %bb2, !dbg !43
 
 bb1:                                              ; preds = %bb
-  %3 = load %struct.test1** %this_addr, align 8, !dbg !43 ; <%struct.test1*> [#uses=1]
+  %3 = load %struct.test1*, %struct.test1** %this_addr, align 8, !dbg !43 ; <%struct.test1*> [#uses=1]
   %4 = bitcast %struct.test1* %3 to i8*, !dbg !43 ; <i8*> [#uses=1]
   call void @_ZdlPv(i8* %4) nounwind, !dbg !43
   br label %bb2, !dbg !43
@@ -105,50 +105,50 @@ return:                                           ; preds = %bb2
 
 declare void @_ZdlPv(i8*) nounwind
 
-!0 = !{!"0x100\00tst\0013\000", !1, !4, !8} ; [ DW_TAG_auto_variable ]
-!1 = !{!"0xb\000\000\000", !44, !2} ; [ DW_TAG_lexical_block ]
-!2 = !{!"0xb\000\000\000", !44, !3} ; [ DW_TAG_lexical_block ]
-!3 = !{!"0x2e\00main\00main\00main\0011\000\001\000\006\000\000\000", i32 0, !4, !5, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!4 = !{!"0x11\004\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\001\00\000\00\000", !44, !45, !45, null, null, null} ; [ DW_TAG_compile_unit ]
-!5 = !{!"0x15\00\000\000\000\000\000\000", !4, null, null, !6, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "tst", line: 13, scope: !1, file: !4, type: !8)
+!1 = distinct !DILexicalBlock(line: 0, column: 0, file: !44, scope: !2)
+!2 = distinct !DILexicalBlock(line: 0, column: 0, file: !44, scope: !3)
+!3 = !DISubprogram(name: "main", linkageName: "main", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !4, type: !5)
+!4 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 0, file: !44, enums: !45, retainedTypes: !45)
+!5 = !DISubroutineType(types: !6)
 !6 = !{!7}
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !4} ; [ DW_TAG_base_type ]
-!8 = !{!"0x13\00test1\001\0064\0064\000\000\000", !44, !4, null, !9, !8, null, null} ; [ DW_TAG_structure_type ] [test1] [line 1, size 64, align 64, offset 0] [def] [from ]
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DICompositeType(tag: DW_TAG_structure_type, name: "test1", line: 1, size: 64, align: 64, file: !44, scope: !4, elements: !9, vtableHolder: !8)
 !9 = !{!10, !14, !18}
-!10 = !{!"0xd\00_vptr$test1\001\0064\0064\000\000", !44, !8, !11} ; [ DW_TAG_member ]
-!11 = !{!"0xf\00\000\0064\0064\000\000", !4, null, !12} ; [ DW_TAG_pointer_type ]
-!12 = !{!"0xf\00__vtbl_ptr_type\000\000\000\000\000", null, !4, !5} ; [ DW_TAG_pointer_type ]
-!13 = !{!"0x11\004\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\000\00\000\00\000", !46, !45, !45, null, null, null} ; [ DW_TAG_compile_unit ]
-!14 = !{!"0x2e\00test1\00test1\00\001\000\000\000\006\001\000\000", i32 0, !8, !15, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!15 = !{!"0x15\00\000\000\000\000\000\000", !4, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!10 = !DIDerivedType(tag: DW_TAG_member, name: "_vptr$test1", line: 1, size: 64, align: 64, file: !44, scope: !8, baseType: !11)
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !4, baseType: !12)
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "__vtbl_ptr_type", scope: !4, baseType: !5)
+!13 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: false, emissionKind: 0, file: !46, enums: !45, retainedTypes: !45)
+!14 = !DISubprogram(name: "test1", line: 1, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrivate, isOptimized: false, scope: !8, type: !15)
+!15 = !DISubroutineType(types: !16)
 !16 = !{null, !17}
-!17 = !{!"0xf\00\000\0064\0064\000\0064", !4, null, !8} ; [ DW_TAG_pointer_type ]
-!18 = !{!"0x2e\00~test1\00~test1\00\004\000\000\001\006\000\000\000", i32 0, !8, !19, !8, null, null, null, null} ; [ DW_TAG_subprogram ]
-!19 = !{!"0x15\00\000\000\000\000\000\000", !4, null, null, !20, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, file: !4, baseType: !8)
+!18 = !DISubprogram(name: "~test1", line: 4, isLocal: false, isDefinition: false, virtuality: DW_VIRTUALITY_virtual, virtualIndex: 6, isOptimized: false, scope: !8, type: !19, containingType: !8)
+!19 = !DISubroutineType(types: !20)
 !20 = !{null, !17, !7}
-!21 = !MDLocation(line: 11, scope: !1)
-!22 = !MDLocation(line: 13, scope: !1)
-!23 = !MDLocation(line: 14, scope: !1)
-!24 = !{!"0x101\00this\0013\000", !25, !4, !26} ; [ DW_TAG_arg_variable ]
-!25 = !{!"0x2e\00test1\00test1\00_ZN5test1C1Ev\001\000\001\000\006\000\000\000", i32 0, !4, !15, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!26 = !{!"0x26\00\000\0064\0064\000\0064", !4, null, !27} ; [ DW_TAG_const_type ]
-!27 = !{!"0xf\00\000\0064\0064\000\000", !4, null, !8} ; [ DW_TAG_pointer_type ]
-!28 = !MDLocation(line: 1, scope: !25)
-!29 = !MDLocation(line: 1, scope: !30)
-!30 = !{!"0xb\000\000\000", !44, !31} ; [ DW_TAG_lexical_block ]
-!31 = !{!"0xb\000\000\000", !44, !25} ; [ DW_TAG_lexical_block ]
-!32 = !{!"0x101\00this\004\000", !33, !4, !26} ; [ DW_TAG_arg_variable ]
-!33 = !{!"0x2e\00~test1\00~test1\00_ZN5test1D1Ev\004\000\001\001\006\000\000\000", i32 0, !8, !15, !8, null, null, null, null} ; [ DW_TAG_subprogram ]
-!34 = !MDLocation(line: 4, scope: !33)
-!35 = !MDLocation(line: 5, scope: !36)
-!36 = !{!"0xb\000\000\000", !44, !33} ; [ DW_TAG_lexical_block ]
-!37 = !MDLocation(line: 6, scope: !36)
-!38 = !{!"0x101\00this\004\000", !39, !4, !26} ; [ DW_TAG_arg_variable ]
-!39 = !{!"0x2e\00~test1\00~test1\00_ZN5test1D0Ev\004\000\001\001\006\000\000\000", i32 0, !8, !15, !8, null, null, null, null} ; [ DW_TAG_subprogram ]
-!40 = !MDLocation(line: 4, scope: !39)
-!41 = !MDLocation(line: 5, scope: !42)
-!42 = !{!"0xb\000\000\000", !44, !39} ; [ DW_TAG_lexical_block ]
-!43 = !MDLocation(line: 6, scope: !42)
-!44 = !{!"inheritance.cpp", !"/tmp/"}
+!21 = !DILocation(line: 11, scope: !1)
+!22 = !DILocation(line: 13, scope: !1)
+!23 = !DILocation(line: 14, scope: !1)
+!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 13, arg: 0, scope: !25, file: !4, type: !26)
+!25 = !DISubprogram(name: "test1", linkageName: "_ZN5test1C1Ev", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !4, type: !15)
+!26 = !DIDerivedType(tag: DW_TAG_const_type, size: 64, align: 64, flags: DIFlagArtificial, file: !4, baseType: !27)
+!27 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !4, baseType: !8)
+!28 = !DILocation(line: 1, scope: !25)
+!29 = !DILocation(line: 1, scope: !30)
+!30 = distinct !DILexicalBlock(line: 0, column: 0, file: !44, scope: !31)
+!31 = distinct !DILexicalBlock(line: 0, column: 0, file: !44, scope: !25)
+!32 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 4, arg: 0, scope: !33, file: !4, type: !26)
+!33 = !DISubprogram(name: "~test1", linkageName: "_ZN5test1D1Ev", line: 4, isLocal: false, isDefinition: true, virtuality: DW_VIRTUALITY_virtual, virtualIndex: 6, isOptimized: false, scope: !8, type: !15, containingType: !8)
+!34 = !DILocation(line: 4, scope: !33)
+!35 = !DILocation(line: 5, scope: !36)
+!36 = distinct !DILexicalBlock(line: 0, column: 0, file: !44, scope: !33)
+!37 = !DILocation(line: 6, scope: !36)
+!38 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 4, arg: 0, scope: !39, file: !4, type: !26)
+!39 = !DISubprogram(name: "~test1", linkageName: "_ZN5test1D0Ev", line: 4, isLocal: false, isDefinition: true, virtuality: DW_VIRTUALITY_virtual, virtualIndex: 6, isOptimized: false, scope: !8, type: !15, containingType: !8)
+!40 = !DILocation(line: 4, scope: !39)
+!41 = !DILocation(line: 5, scope: !42)
+!42 = distinct !DILexicalBlock(line: 0, column: 0, file: !44, scope: !39)
+!43 = !DILocation(line: 6, scope: !42)
+!44 = !DIFile(filename: "inheritance.cpp", directory: "/tmp/")
 !45 = !{i32 0}
-!46 = !{!"<built-in>", !"/tmp/"}
+!46 = !DIFile(filename: "<built-in>", directory: "/tmp/")
diff --git a/test/DebugInfo/inline-debug-info-multiret.ll b/test/DebugInfo/inline-debug-info-multiret.ll
index 0115ecd3a8d0..110b2958f0ae 100644
--- a/test/DebugInfo/inline-debug-info-multiret.ll
+++ b/test/DebugInfo/inline-debug-info-multiret.ll
@@ -10,8 +10,8 @@
 ; CHECK: br label %invoke.cont, !dbg ![[MD]]
 ; The branch instruction has the source location of line 9 and its inlined location
 ; has the source location of line 14.
-; CHECK: ![[INL:[0-9]+]] = !MDLocation(line: 14, scope: {{.*}})
-; CHECK: ![[MD]] = !MDLocation(line: 9, scope: {{.*}}, inlinedAt: ![[INL]])
+; CHECK: ![[INL:[0-9]+]] = distinct !DILocation(line: 14, scope: {{.*}})
+; CHECK: ![[MD]] = !DILocation(line: 9, scope: {{.*}}, inlinedAt: ![[INL]])
 
 ; ModuleID = 'test.cpp'
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
@@ -27,27 +27,27 @@ entry:
   %k.addr = alloca i32, align 4
   %k2 = alloca i32, align 4
   store i32 %k, i32* %k.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %k.addr, metadata !13, metadata !{!"0x102"}), !dbg !14
-  call void @llvm.dbg.declare(metadata i32* %k2, metadata !15, metadata !{!"0x102"}), !dbg !16
-  %0 = load i32* %k.addr, align 4, !dbg !16
+  call void @llvm.dbg.declare(metadata i32* %k.addr, metadata !13, metadata !DIExpression()), !dbg !14
+  call void @llvm.dbg.declare(metadata i32* %k2, metadata !15, metadata !DIExpression()), !dbg !16
+  %0 = load i32, i32* %k.addr, align 4, !dbg !16
   %call = call i32 @_Z8test_exti(i32 %0), !dbg !16
   store i32 %call, i32* %k2, align 4, !dbg !16
-  %1 = load i32* %k2, align 4, !dbg !17
+  %1 = load i32, i32* %k2, align 4, !dbg !17
   %cmp = icmp sgt i32 %1, 100, !dbg !17
   br i1 %cmp, label %if.then, label %if.end, !dbg !17
 
 if.then:                                          ; preds = %entry
-  %2 = load i32* %k2, align 4, !dbg !18
+  %2 = load i32, i32* %k2, align 4, !dbg !18
   store i32 %2, i32* %retval, !dbg !18
   br label %return, !dbg !18
 
 if.end:                                           ; preds = %entry
   store i32 0, i32* %retval, !dbg !19
-  %3 = load i32* %retval, !dbg !20                ; hand-edited
+  %3 = load i32, i32* %retval, !dbg !20                ; hand-edited
   ret i32 %3, !dbg !20                            ; hand-edited
 
 return:                                           ; preds = %if.end, %if.then
-  %4 = load i32* %retval, !dbg !20
+  %4 = load i32, i32* %retval, !dbg !20
   ret i32 %4, !dbg !20
 }
 
@@ -62,7 +62,7 @@ entry:
   %exn.slot = alloca i8*
   %ehselector.slot = alloca i32
   %e = alloca i32, align 4
-  %0 = load i32* @global_var, align 4, !dbg !21
+  %0 = load i32, i32* @global_var, align 4, !dbg !21
   %call = invoke i32 @_Z4testi(i32 %0)
           to label %invoke.cont unwind label %lpad, !dbg !21
 
@@ -79,17 +79,17 @@ lpad:                                             ; preds = %entry
   br label %catch.dispatch, !dbg !21
 
 catch.dispatch:                                   ; preds = %lpad
-  %sel = load i32* %ehselector.slot, !dbg !23
+  %sel = load i32, i32* %ehselector.slot, !dbg !23
   %4 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) #2, !dbg !23
   %matches = icmp eq i32 %sel, %4, !dbg !23
   br i1 %matches, label %catch, label %eh.resume, !dbg !23
 
 catch:                                            ; preds = %catch.dispatch
-  call void @llvm.dbg.declare(metadata i32* %e, metadata !24, metadata !{!"0x102"}), !dbg !25
-  %exn = load i8** %exn.slot, !dbg !23
+  call void @llvm.dbg.declare(metadata i32* %e, metadata !24, metadata !DIExpression()), !dbg !25
+  %exn = load i8*, i8** %exn.slot, !dbg !23
   %5 = call i8* @__cxa_begin_catch(i8* %exn) #2, !dbg !23
   %6 = bitcast i8* %5 to i32*, !dbg !23
-  %7 = load i32* %6, align 4, !dbg !23
+  %7 = load i32, i32* %6, align 4, !dbg !23
   store i32 %7, i32* %e, align 4, !dbg !23
   store i32 0, i32* @global_var, align 4, !dbg !26
   call void @__cxa_end_catch() #2, !dbg !28
@@ -100,8 +100,8 @@ try.cont:                                         ; preds = %catch, %invoke.cont
   ret i32 0, !dbg !30
 
 eh.resume:                                        ; preds = %catch.dispatch
-  %exn1 = load i8** %exn.slot, !dbg !23
-  %sel2 = load i32* %ehselector.slot, !dbg !23
+  %exn1 = load i8*, i8** %exn.slot, !dbg !23
+  %sel2 = load i32, i32* %ehselector.slot, !dbg !23
   %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn1, 0, !dbg !23
   %lpad.val3 = insertvalue { i8*, i32 } %lpad.val, i32 %sel2, 1, !dbg !23
   resume { i8*, i32 } %lpad.val3, !dbg !23
@@ -122,35 +122,35 @@ attributes #2 = { nounwind }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!31}
 
-!0 = !{!"0x11\004\00clang version 3.3 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [<unknown>] [DW_LANG_C_plus_plus]
-!1 = !{!"<unknown>", !""}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<unknown>", directory: "")
+!2 = !{}
 !3 = !{!4, !10}
-!4 = !{!"0x2e\00test\00test\00_Z4testi\004\000\001\000\006\00256\000\004", !5, !6, !7, null, i32 (i32)* @_Z4testi, null, null, !2} ; [ DW_TAG_subprogram ] [line 4] [def] [test]
-!5 = !{!"test.cpp", !""}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [test.cpp]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "test", linkageName: "_Z4testi", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !5, scope: !6, type: !7, function: i32 (i32)* @_Z4testi, variables: !2)
+!5 = !DIFile(filename: "test.cpp", directory: "")
+!6 = !DIFile(filename: "test.cpp", directory: "")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"0x2e\00test2\00test2\00_Z5test2v\0011\000\001\000\006\00256\000\0011", !5, !6, !11, null, i32 ()* @_Z5test2v, null, null, !2} ; [ DW_TAG_subprogram ] [line 11] [def] [test2]
-!11 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DISubprogram(name: "test2", linkageName: "_Z5test2v", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 11, file: !5, scope: !6, type: !11, function: i32 ()* @_Z5test2v, variables: !2)
+!11 = !DISubroutineType(types: !12)
 !12 = !{!9}
-!13 = !{!"0x101\00k\0016777220\000", !4, !6, !9} ; [ DW_TAG_arg_variable ] [k] [line 4]
-!14 = !MDLocation(line: 4, scope: !4)
-!15 = !{!"0x100\00k2\005\000", !4, !6, !9} ; [ DW_TAG_auto_variable ] [k2] [line 5]
-!16 = !MDLocation(line: 5, scope: !4)
-!17 = !MDLocation(line: 6, scope: !4)
-!18 = !MDLocation(line: 7, scope: !4)
-!19 = !MDLocation(line: 8, scope: !4)
-!20 = !MDLocation(line: 9, scope: !4)
-!21 = !MDLocation(line: 14, scope: !22)
-!22 = !{!"0xb\0013\000\000", !5, !10} ; [ DW_TAG_lexical_block ] [test.cpp]
-!23 = !MDLocation(line: 15, scope: !22)
-!24 = !{!"0x100\00e\0016\000", !10, !6, !9} ; [ DW_TAG_auto_variable ] [e] [line 16]
-!25 = !MDLocation(line: 16, scope: !10)
-!26 = !MDLocation(line: 17, scope: !27)
-!27 = !{!"0xb\0016\000\001", !5, !10} ; [ DW_TAG_lexical_block ] [test.cpp]
-!28 = !MDLocation(line: 18, scope: !27)
-!29 = !MDLocation(line: 19, scope: !10)
-!30 = !MDLocation(line: 20, scope: !10)
-!31 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "k", line: 4, arg: 1, scope: !4, file: !6, type: !9)
+!14 = !DILocation(line: 4, scope: !4)
+!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k2", line: 5, scope: !4, file: !6, type: !9)
+!16 = !DILocation(line: 5, scope: !4)
+!17 = !DILocation(line: 6, scope: !4)
+!18 = !DILocation(line: 7, scope: !4)
+!19 = !DILocation(line: 8, scope: !4)
+!20 = !DILocation(line: 9, scope: !4)
+!21 = !DILocation(line: 14, scope: !22)
+!22 = distinct !DILexicalBlock(line: 13, column: 0, file: !5, scope: !10)
+!23 = !DILocation(line: 15, scope: !22)
+!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "e", line: 16, scope: !10, file: !6, type: !9)
+!25 = !DILocation(line: 16, scope: !10)
+!26 = !DILocation(line: 17, scope: !27)
+!27 = distinct !DILexicalBlock(line: 16, column: 0, file: !5, scope: !10)
+!28 = !DILocation(line: 18, scope: !27)
+!29 = !DILocation(line: 19, scope: !10)
+!30 = !DILocation(line: 20, scope: !10)
+!31 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/inline-debug-info.ll b/test/DebugInfo/inline-debug-info.ll
index 5d2f652034de..aa25b658efe9 100644
--- a/test/DebugInfo/inline-debug-info.ll
+++ b/test/DebugInfo/inline-debug-info.ll
@@ -28,11 +28,11 @@
 ; CHECK: _Z4testi.exit:
 ; Make sure the branch instruction created during inlining has a debug location,
 ; so the range of the inlined function is correct.
-; CHECK: br label %invoke.cont, !dbg ![[MD:[0-9]+]]
+; CHECK: br label %invoke.cont, !dbg [[MD:![0-9]+]]
 ; The branch instruction has the source location of line 9 and its inlined location
 ; has the source location of line 14.
-; CHECK: ![[INL:[0-9]+]] = !MDLocation(line: 14, scope: {{.*}})
-; CHECK: ![[MD]] = !MDLocation(line: 9, scope: {{.*}}, inlinedAt: ![[INL]])
+; CHECK: [[INL:![0-9]*]] = distinct !DILocation(line: 14, scope: {{.*}})
+; CHECK: [[MD]] = !DILocation(line: 9, scope: {{.*}}, inlinedAt: [[INL]])
 
 ; ModuleID = 'test.cpp'
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
@@ -47,17 +47,17 @@ entry:
   %k.addr = alloca i32, align 4
   %k2 = alloca i32, align 4
   store i32 %k, i32* %k.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %k.addr, metadata !13, metadata !{!"0x102"}), !dbg !14
-  call void @llvm.dbg.declare(metadata i32* %k2, metadata !15, metadata !{!"0x102"}), !dbg !16
-  %0 = load i32* %k.addr, align 4, !dbg !16
+  call void @llvm.dbg.declare(metadata i32* %k.addr, metadata !13, metadata !DIExpression()), !dbg !14
+  call void @llvm.dbg.declare(metadata i32* %k2, metadata !15, metadata !DIExpression()), !dbg !16
+  %0 = load i32, i32* %k.addr, align 4, !dbg !16
   %call = call i32 @_Z8test_exti(i32 %0), !dbg !16
   store i32 %call, i32* %k2, align 4, !dbg !16
-  %1 = load i32* %k2, align 4, !dbg !17
+  %1 = load i32, i32* %k2, align 4, !dbg !17
   %cmp = icmp sgt i32 %1, 100, !dbg !17
   br i1 %cmp, label %if.then, label %if.end, !dbg !17
 
 if.then:                                          ; preds = %entry
-  %2 = load i32* %k2, align 4, !dbg !18
+  %2 = load i32, i32* %k2, align 4, !dbg !18
   store i32 %2, i32* %retval, !dbg !18
   br label %return, !dbg !18
 
@@ -66,7 +66,7 @@ if.end:                                           ; preds = %entry
   br label %return, !dbg !19
 
 return:                                           ; preds = %if.end, %if.then
-  %3 = load i32* %retval, !dbg !20
+  %3 = load i32, i32* %retval, !dbg !20
   ret i32 %3, !dbg !20
 }
 
@@ -80,7 +80,7 @@ entry:
   %exn.slot = alloca i8*
   %ehselector.slot = alloca i32
   %e = alloca i32, align 4
-  %0 = load i32* @global_var, align 4, !dbg !21
+  %0 = load i32, i32* @global_var, align 4, !dbg !21
   %call = invoke i32 @_Z4testi(i32 %0)
           to label %invoke.cont unwind label %lpad, !dbg !21
 
@@ -97,17 +97,17 @@ lpad:                                             ; preds = %entry
   br label %catch.dispatch, !dbg !21
 
 catch.dispatch:                                   ; preds = %lpad
-  %sel = load i32* %ehselector.slot, !dbg !23
+  %sel = load i32, i32* %ehselector.slot, !dbg !23
   %4 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) #2, !dbg !23
   %matches = icmp eq i32 %sel, %4, !dbg !23
   br i1 %matches, label %catch, label %eh.resume, !dbg !23
 
 catch:                                            ; preds = %catch.dispatch
-  call void @llvm.dbg.declare(metadata i32* %e, metadata !24, metadata !{!"0x102"}), !dbg !25
-  %exn = load i8** %exn.slot, !dbg !23
+  call void @llvm.dbg.declare(metadata i32* %e, metadata !24, metadata !DIExpression()), !dbg !25
+  %exn = load i8*, i8** %exn.slot, !dbg !23
   %5 = call i8* @__cxa_begin_catch(i8* %exn) #2, !dbg !23
   %6 = bitcast i8* %5 to i32*, !dbg !23
-  %7 = load i32* %6, align 4, !dbg !23
+  %7 = load i32, i32* %6, align 4, !dbg !23
   store i32 %7, i32* %e, align 4, !dbg !23
   store i32 0, i32* @global_var, align 4, !dbg !26
   call void @__cxa_end_catch() #2, !dbg !28
@@ -118,8 +118,8 @@ try.cont:                                         ; preds = %catch, %invoke.cont
   ret i32 0, !dbg !30
 
 eh.resume:                                        ; preds = %catch.dispatch
-  %exn1 = load i8** %exn.slot, !dbg !23
-  %sel2 = load i32* %ehselector.slot, !dbg !23
+  %exn1 = load i8*, i8** %exn.slot, !dbg !23
+  %sel2 = load i32, i32* %ehselector.slot, !dbg !23
   %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn1, 0, !dbg !23
   %lpad.val3 = insertvalue { i8*, i32 } %lpad.val, i32 %sel2, 1, !dbg !23
   resume { i8*, i32 } %lpad.val3, !dbg !23
@@ -140,35 +140,35 @@ attributes #2 = { nounwind }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!31}
 
-!0 = !{!"0x11\004\00clang version 3.3 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [<unknown>] [DW_LANG_C_plus_plus]
-!1 = !{!"<unknown>", !""}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<unknown>", directory: "")
+!2 = !{}
 !3 = !{!4, !10}
-!4 = !{!"0x2e\00test\00test\00_Z4testi\004\000\001\000\006\00256\000\004", !5, !6, !7, null, i32 (i32)* @_Z4testi, null, null, !2} ; [ DW_TAG_subprogram ] [line 4] [def] [test]
-!5 = !{!"test.cpp", !""}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [test.cpp]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "test", linkageName: "_Z4testi", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !5, scope: !6, type: !7, function: i32 (i32)* @_Z4testi, variables: !2)
+!5 = !DIFile(filename: "test.cpp", directory: "")
+!6 = !DIFile(filename: "test.cpp", directory: "")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"0x2e\00test2\00test2\00_Z5test2v\0011\000\001\000\006\00256\000\0011", !5, !6, !11, null, i32 ()* @_Z5test2v, null, null, !2} ; [ DW_TAG_subprogram ] [line 11] [def] [test2]
-!11 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DISubprogram(name: "test2", linkageName: "_Z5test2v", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 11, file: !5, scope: !6, type: !11, function: i32 ()* @_Z5test2v, variables: !2)
+!11 = !DISubroutineType(types: !12)
 !12 = !{!9}
-!13 = !{!"0x101\00k\0016777220\000", !4, !6, !9} ; [ DW_TAG_arg_variable ] [k] [line 4]
-!14 = !MDLocation(line: 4, scope: !4)
-!15 = !{!"0x100\00k2\005\000", !4, !6, !9} ; [ DW_TAG_auto_variable ] [k2] [line 5]
-!16 = !MDLocation(line: 5, scope: !4)
-!17 = !MDLocation(line: 6, scope: !4)
-!18 = !MDLocation(line: 7, scope: !4)
-!19 = !MDLocation(line: 8, scope: !4)
-!20 = !MDLocation(line: 9, scope: !4)
-!21 = !MDLocation(line: 14, scope: !22)
-!22 = !{!"0xb\0013\000\000", !5, !10} ; [ DW_TAG_lexical_block ] [test.cpp]
-!23 = !MDLocation(line: 15, scope: !22)
-!24 = !{!"0x100\00e\0016\000", !10, !6, !9} ; [ DW_TAG_auto_variable ] [e] [line 16]
-!25 = !MDLocation(line: 16, scope: !10)
-!26 = !MDLocation(line: 17, scope: !27)
-!27 = !{!"0xb\0016\000\001", !5, !10} ; [ DW_TAG_lexical_block ] [test.cpp]
-!28 = !MDLocation(line: 18, scope: !27)
-!29 = !MDLocation(line: 19, scope: !10)
-!30 = !MDLocation(line: 20, scope: !10)
-!31 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "k", line: 4, arg: 1, scope: !4, file: !6, type: !9)
+!14 = !DILocation(line: 4, scope: !4)
+!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k2", line: 5, scope: !4, file: !6, type: !9)
+!16 = !DILocation(line: 5, scope: !4)
+!17 = !DILocation(line: 6, scope: !4)
+!18 = !DILocation(line: 7, scope: !4)
+!19 = !DILocation(line: 8, scope: !4)
+!20 = !DILocation(line: 9, scope: !4)
+!21 = !DILocation(line: 14, scope: !22)
+!22 = distinct !DILexicalBlock(line: 13, column: 0, file: !5, scope: !10)
+!23 = !DILocation(line: 15, scope: !22)
+!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "e", line: 16, scope: !10, file: !6, type: !9)
+!25 = !DILocation(line: 16, scope: !10)
+!26 = !DILocation(line: 17, scope: !27)
+!27 = distinct !DILexicalBlock(line: 16, column: 0, file: !5, scope: !10)
+!28 = !DILocation(line: 18, scope: !27)
+!29 = !DILocation(line: 19, scope: !10)
+!30 = !DILocation(line: 20, scope: !10)
+!31 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/inline-no-debug-info.ll b/test/DebugInfo/inline-no-debug-info.ll
index 68fd8e7a01bc..9ecd58031eb1 100644
--- a/test/DebugInfo/inline-no-debug-info.ll
+++ b/test/DebugInfo/inline-no-debug-info.ll
@@ -21,10 +21,11 @@
 
 ; Debug location of the code in caller() and of the inlined code that did not
 ; have any debug location before.
-; CHECK-DAG: [[A]] = !MDLocation(line: 4, scope: !{{[01-9]+}})
+; CHECK-DAG: [[A]] = !DILocation(line: 4, scope: !{{[0-9]+}})
 
 ; Debug location of the inlined code.
-; CHECK-DAG: [[B]] = !MDLocation(line: 2, scope: !{{[01-9]+}}, inlinedAt: [[A]])
+; CHECK-DAG: [[B]] = !DILocation(line: 2, scope: !{{[0-9]+}}, inlinedAt: [[A_INL:![0-9]*]])
+; CHECK-DAG: [[A_INL]] = distinct !DILocation(line: 4, scope: !{{[0-9]+}})
 
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@@ -54,16 +55,16 @@ attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointe
 !llvm.module.flags = !{!8, !9}
 !llvm.ident = !{!10}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 (210174)\001\00\000\00\002", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/code/llvm/build0/test.c] [DW_LANG_C99]
-!1 = !{!"test.c", !"/code/llvm/build0"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 (210174)", isOptimized: true, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.c", directory: "/code/llvm/build0")
 !2 = !{}
 !3 = !{!4, !7}
-!4 = !{!"0x2e\00caller\00caller\00\004\000\001\000\006\000\001\004", !1, !5, !6, null, void ()* @caller, null, null, !2} ; [ DW_TAG_subprogram ] [line 4] [def] [caller]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/code/llvm/build0/test.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!7 = !{!"0x2e\00callee2\00callee2\00\002\001\001\000\006\000\001\002", !1, !5, !6, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [local] [def] [callee2]
+!4 = !DISubprogram(name: "caller", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 4, file: !1, scope: !5, type: !6, function: void ()* @caller, variables: !2)
+!5 = !DIFile(filename: "test.c", directory: "/code/llvm/build0")
+!6 = !DISubroutineType(types: !2)
+!7 = !DISubprogram(name: "callee2", line: 2, isLocal: true, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 2, file: !1, scope: !5, type: !6, variables: !2)
 !8 = !{i32 2, !"Dwarf Version", i32 4}
-!9 = !{i32 2, !"Debug Info Version", i32 2}
+!9 = !{i32 2, !"Debug Info Version", i32 3}
 !10 = !{!"clang version 3.5.0 (210174)"}
-!11 = !MDLocation(line: 2, scope: !7)
-!12 = !MDLocation(line: 4, scope: !4)
+!11 = !DILocation(line: 2, scope: !7)
+!12 = !DILocation(line: 4, scope: !4)
diff --git a/test/DebugInfo/inline-scopes.ll b/test/DebugInfo/inline-scopes.ll
index ec36a2fdec62..45324f6a4b96 100644
--- a/test/DebugInfo/inline-scopes.ll
+++ b/test/DebugInfo/inline-scopes.ll
@@ -43,11 +43,11 @@ entry:
   %b.i3 = alloca i8, align 1
   %retval.i = alloca i32, align 4
   %b.i = alloca i8, align 1
-  call void @llvm.dbg.declare(metadata i8* %b.i, metadata !16, metadata !{!"0x102"}), !dbg !19
+  call void @llvm.dbg.declare(metadata i8* %b.i, metadata !16, metadata !DIExpression()), !dbg !19
   %call.i = call zeroext i1 @_Z1fv(), !dbg !19
   %frombool.i = zext i1 %call.i to i8, !dbg !19
   store i8 %frombool.i, i8* %b.i, align 1, !dbg !19
-  %0 = load i8* %b.i, align 1, !dbg !19
+  %0 = load i8, i8* %b.i, align 1, !dbg !19
   %tobool.i = trunc i8 %0 to i1, !dbg !19
   br i1 %tobool.i, label %if.then.i, label %if.end.i, !dbg !19
 
@@ -60,12 +60,12 @@ if.end.i:                                         ; preds = %entry
   br label %_Z2f1v.exit, !dbg !22
 
 _Z2f1v.exit:                                      ; preds = %if.then.i, %if.end.i
-  %1 = load i32* %retval.i, !dbg !23
-  call void @llvm.dbg.declare(metadata i8* %b.i3, metadata !24, metadata !{!"0x102"}), !dbg !27
+  %1 = load i32, i32* %retval.i, !dbg !23
+  call void @llvm.dbg.declare(metadata i8* %b.i3, metadata !24, metadata !DIExpression()), !dbg !27
   %call.i4 = call zeroext i1 @_Z1fv(), !dbg !27
   %frombool.i5 = zext i1 %call.i4 to i8, !dbg !27
   store i8 %frombool.i5, i8* %b.i3, align 1, !dbg !27
-  %2 = load i8* %b.i3, align 1, !dbg !27
+  %2 = load i8, i8* %b.i3, align 1, !dbg !27
   %tobool.i6 = trunc i8 %2 to i1, !dbg !27
   br i1 %tobool.i6, label %if.then.i7, label %if.end.i8, !dbg !27
 
@@ -78,7 +78,7 @@ if.end.i8:                                        ; preds = %_Z2f1v.exit
   br label %_Z2f2v.exit, !dbg !30
 
 _Z2f2v.exit:                                      ; preds = %if.then.i7, %if.end.i8
-  %3 = load i32* %retval.i2, !dbg !31
+  %3 = load i32, i32* %retval.i2, !dbg !31
   ret i32 0, !dbg !32
 }
 
@@ -95,36 +95,36 @@ attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n
 !llvm.module.flags = !{!13, !14}
 !llvm.ident = !{!15}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/inline-scopes.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"inline-scopes.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "inline-scopes.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4, !10, !12}
-!4 = !{!"0x2e\00main\00main\00\007\000\001\000\006\00256\000\007", !5, !6, !7, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 7] [def] [main]
-!5 = !{!"y.cc", !"/tmp/dbginfo"}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/y.cc]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "main", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !5, scope: !6, type: !7, function: i32 ()* @main, variables: !2)
+!5 = !DIFile(filename: "y.cc", directory: "/tmp/dbginfo")
+!6 = !DIFile(filename: "y.cc", directory: "/tmp/dbginfo")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"0x2e\00f2\00f2\00_Z2f2v\008\000\001\000\006\00256\000\008", !1, !11, !7, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 8] [def] [f2]
-!11 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/tmp/dbginfo/inline-scopes.cpp]
-!12 = !{!"0x2e\00f1\00f1\00_Z2f1v\002\000\001\000\006\00256\000\002", !1, !11, !7, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [f1]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DISubprogram(name: "f2", linkageName: "_Z2f2v", line: 8, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 8, file: !1, scope: !11, type: !7, variables: !2)
+!11 = !DIFile(filename: "inline-scopes.cpp", directory: "/tmp/dbginfo")
+!12 = !DISubprogram(name: "f1", linkageName: "_Z2f1v", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !11, type: !7, variables: !2)
 !13 = !{i32 2, !"Dwarf Version", i32 4}
-!14 = !{i32 1, !"Debug Info Version", i32 2}
+!14 = !{i32 1, !"Debug Info Version", i32 3}
 !15 = !{!"clang version 3.5.0 "}
-!16 = !{!"0x100\00b\003\000", !17, !11, !18} ; [ DW_TAG_auto_variable ] [b] [line 3]
-!17 = !{!"0xb\003\000\001", !1, !12} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/inline-scopes.cpp]
-!18 = !{!"0x24\00bool\000\008\008\000\000\002", null, null} ; [ DW_TAG_base_type ] [bool] [line 0, size 8, align 8, offset 0, enc DW_ATE_boolean]
-!19 = !MDLocation(line: 3, scope: !17, inlinedAt: !20)
-!20 = !MDLocation(line: 8, scope: !4)
-!21 = !MDLocation(line: 4, scope: !17, inlinedAt: !20)
-!22 = !MDLocation(line: 5, scope: !12, inlinedAt: !20)
-!23 = !MDLocation(line: 6, scope: !12, inlinedAt: !20)
-!24 = !{!"0x100\00b\002\000", !25, !6, !18} ; [ DW_TAG_auto_variable ] [b] [line 2]
-!25 = !{!"0xb\002\000\000", !5, !26} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/y.cc]
-!26 = !{!"0xb\000", !5, !10} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/y.cc]
-!27 = !MDLocation(line: 2, scope: !25, inlinedAt: !28)
-!28 = !MDLocation(line: 9, scope: !4)
-!29 = !MDLocation(line: 3, scope: !25, inlinedAt: !28)
-!30 = !MDLocation(line: 4, scope: !26, inlinedAt: !28)
-!31 = !MDLocation(line: 5, scope: !26, inlinedAt: !28)
-!32 = !MDLocation(line: 10, scope: !4)
+!16 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 3, scope: !17, file: !11, type: !18)
+!17 = distinct !DILexicalBlock(line: 3, column: 0, file: !1, scope: !12)
+!18 = !DIBasicType(tag: DW_TAG_base_type, name: "bool", size: 8, align: 8, encoding: DW_ATE_boolean)
+!19 = !DILocation(line: 3, scope: !17, inlinedAt: !20)
+!20 = !DILocation(line: 8, scope: !4)
+!21 = !DILocation(line: 4, scope: !17, inlinedAt: !20)
+!22 = !DILocation(line: 5, scope: !12, inlinedAt: !20)
+!23 = !DILocation(line: 6, scope: !12, inlinedAt: !20)
+!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 2, scope: !25, file: !6, type: !18)
+!25 = distinct !DILexicalBlock(line: 2, column: 0, file: !5, scope: !26)
+!26 = !DILexicalBlockFile(discriminator: 0, file: !5, scope: !10)
+!27 = !DILocation(line: 2, scope: !25, inlinedAt: !28)
+!28 = !DILocation(line: 9, scope: !4)
+!29 = !DILocation(line: 3, scope: !25, inlinedAt: !28)
+!30 = !DILocation(line: 4, scope: !26, inlinedAt: !28)
+!31 = !DILocation(line: 5, scope: !26, inlinedAt: !28)
+!32 = !DILocation(line: 10, scope: !4)
diff --git a/test/DebugInfo/inlined-arguments.ll b/test/DebugInfo/inlined-arguments.ll
index c705cf8e97f3..912ebb1321ee 100644
--- a/test/DebugInfo/inlined-arguments.ll
+++ b/test/DebugInfo/inlined-arguments.ll
@@ -24,16 +24,16 @@
 
 ; Function Attrs: uwtable
 define void @_Z2f2v() #0 {
-  tail call void @llvm.dbg.value(metadata i32 undef, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !18
-  tail call void @llvm.dbg.value(metadata i32 2, i64 0, metadata !20, metadata !{!"0x102"}), !dbg !18
+  tail call void @llvm.dbg.value(metadata i32 undef, i64 0, metadata !16, metadata !DIExpression()), !dbg !18
+  tail call void @llvm.dbg.value(metadata i32 2, i64 0, metadata !20, metadata !DIExpression()), !dbg !18
   tail call void @_Z2f3i(i32 2), !dbg !21
   ret void, !dbg !22
 }
 
 ; Function Attrs: uwtable
 define void @_Z2f1ii(i32 %x, i32 %y) #0 {
-  tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !23
-  tail call void @llvm.dbg.value(metadata i32 %y, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !23
+  tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !13, metadata !DIExpression()), !dbg !23
+  tail call void @llvm.dbg.value(metadata i32 %y, i64 0, metadata !14, metadata !DIExpression()), !dbg !23
   tail call void @_Z2f3i(i32 %y), !dbg !24
   ret void, !dbg !25
 }
@@ -50,30 +50,30 @@ attributes #2 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!26}
 
-!0 = !{!"0x11\004\00clang version 3.4 \001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/blaikie/dev/scratch/exp.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"exp.cpp", !"/usr/local/google/home/blaikie/dev/scratch"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "exp.cpp", directory: "/usr/local/google/home/blaikie/dev/scratch")
 !2 = !{}
 !3 = !{!4, !8}
-!4 = !{!"0x2e\00f2\00f2\00_Z2f2v\003\000\001\000\006\00256\001\003", !1, !5, !6, null, void ()* @_Z2f2v, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [f2]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/usr/local/google/home/blaikie/dev/scratch/exp.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "f2", linkageName: "_Z2f2v", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !1, scope: !5, type: !6, function: void ()* @_Z2f2v, variables: !2)
+!5 = !DIFile(filename: "exp.cpp", directory: "/usr/local/google/home/blaikie/dev/scratch")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
-!8 = !{!"0x2e\00f1\00f1\00_Z2f1ii\006\000\001\000\006\00256\001\006", !1, !5, !9, null, void (i32, i32)* @_Z2f1ii, null, null, !12} ; [ DW_TAG_subprogram ] [line 6] [def] [f1]
-!9 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = !DISubprogram(name: "f1", linkageName: "_Z2f1ii", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 6, file: !1, scope: !5, type: !9, function: void (i32, i32)* @_Z2f1ii, variables: !12)
+!9 = !DISubroutineType(types: !10)
 !10 = !{null, !11, !11}
-!11 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !12 = !{!13, !14}
-!13 = !{!"0x101\00x\0016777222\000", !8, !5, !11} ; [ DW_TAG_arg_variable ] [x] [line 6]
-!14 = !{!"0x101\00y\0033554438\000", !8, !5, !11} ; [ DW_TAG_arg_variable ] [y] [line 6]
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 6, arg: 1, scope: !8, file: !5, type: !11)
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "y", line: 6, arg: 2, scope: !8, file: !5, type: !11)
 !15 = !{i32 undef}
-!16 = !{!"0x101\00x\0016777222\000", !8, !5, !11, !17} ; [ DW_TAG_arg_variable ] [x] [line 6]
-!17 = !MDLocation(line: 4, scope: !4)
-!18 = !MDLocation(line: 6, scope: !8, inlinedAt: !17)
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 6, arg: 1, scope: !8, file: !5, type: !11)
+!17 = !DILocation(line: 4, scope: !4)
+!18 = !DILocation(line: 6, scope: !8, inlinedAt: !17)
 !19 = !{i32 2}
-!20 = !{!"0x101\00y\0033554438\000", !8, !5, !11, !17} ; [ DW_TAG_arg_variable ] [y] [line 6]
-!21 = !MDLocation(line: 7, scope: !8, inlinedAt: !17)
-!22 = !MDLocation(line: 5, scope: !4)
-!23 = !MDLocation(line: 6, scope: !8)
-!24 = !MDLocation(line: 7, scope: !8)
-!25 = !MDLocation(line: 8, scope: !8)
-!26 = !{i32 1, !"Debug Info Version", i32 2}
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "y", line: 6, arg: 2, scope: !8, file: !5, type: !11)
+!21 = !DILocation(line: 7, scope: !8, inlinedAt: !17)
+!22 = !DILocation(line: 5, scope: !4)
+!23 = !DILocation(line: 6, scope: !8)
+!24 = !DILocation(line: 7, scope: !8)
+!25 = !DILocation(line: 8, scope: !8)
+!26 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/inlined-vars.ll b/test/DebugInfo/inlined-vars.ll
index b84e12f4ce9f..8c7823748864 100644
--- a/test/DebugInfo/inlined-vars.ll
+++ b/test/DebugInfo/inlined-vars.ll
@@ -4,8 +4,8 @@
 
 define i32 @main() uwtable {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !21
-  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !22, metadata !{!"0x102"}), !dbg !23
+  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !18, metadata !DIExpression()), !dbg !21
+  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !22, metadata !DIExpression()), !dbg !23
   tail call void @smth(i32 0), !dbg !24
   tail call void @smth(i32 0), !dbg !25
   ret i32 0, !dbg !19
@@ -18,39 +18,39 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!27}
 
-!0 = !{!"0x11\004\00clang version 3.2 (trunk 159419)\001\00\000\00\000", !26, !2, !2, !3, !2,  !2} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.2 (trunk 159419)", isOptimized: true, emissionKind: 0, file: !26, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports:  !2)
 !1 = !{i32 0}
 !2 = !{}
 !3 = !{!5, !10}
-!5 = !{!"0x2e\00main\00main\00\0010\000\001\000\006\00256\001\0010", !26, !6, !7, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ]
-!6 = !{!"0x29", !26} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "main", line: 10, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 10, file: !26, scope: !6, type: !7, function: i32 ()* @main, variables: !2)
+!6 = !DIFile(filename: "inline-bug.cc", directory: "/tmp/dbginfo/pr13202")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!10 = !{!"0x2e\00f\00f\00_ZL1fi\003\001\001\000\006\00256\001\003", !26, !6, !11, null, null, null, null, !13} ; [ DW_TAG_subprogram ]
-!11 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DISubprogram(name: "f", linkageName: "_ZL1fi", line: 3, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !26, scope: !6, type: !11, variables: !13)
+!11 = !DISubroutineType(types: !12)
 !12 = !{!9, !9}
 !13 = !{!15, !16}
-!15 = !{!"0x101\00argument\0016777219\000", !10, !6, !9} ; [ DW_TAG_arg_variable ]
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argument", line: 3, arg: 1, scope: !10, file: !6, type: !9)
 
 ; Two DW_TAG_formal_parameter: one abstract and one inlined.
 ; ARGUMENT: {{.*Abbrev.*DW_TAG_formal_parameter}}
 ; ARGUMENT: {{.*Abbrev.*DW_TAG_formal_parameter}}
 ; ARGUMENT-NOT: {{.*Abbrev.*DW_TAG_formal_parameter}}
 
-!16 = !{!"0x100\00local\004\000", !10, !6, !9} ; [ DW_TAG_auto_variable ]
+!16 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "local", line: 4, scope: !10, file: !6, type: !9)
 
 ; Two DW_TAG_variable: one abstract and one inlined.
 ; VARIABLE: {{.*Abbrev.*DW_TAG_variable}}
 ; VARIABLE: {{.*Abbrev.*DW_TAG_variable}}
 ; VARIABLE-NOT: {{.*Abbrev.*DW_TAG_variable}}
 
-!18 = !{!"0x101\00argument\0016777219\000", !10, !6, !9, !19} ; [ DW_TAG_arg_variable ]
-!19 = !MDLocation(line: 11, column: 10, scope: !5)
-!21 = !MDLocation(line: 3, column: 25, scope: !10, inlinedAt: !19)
-!22 = !{!"0x100\00local\004\000", !10, !6, !9, !19} ; [ DW_TAG_auto_variable ]
-!23 = !MDLocation(line: 4, column: 16, scope: !10, inlinedAt: !19)
-!24 = !MDLocation(line: 5, column: 3, scope: !10, inlinedAt: !19)
-!25 = !MDLocation(line: 6, column: 3, scope: !10, inlinedAt: !19)
-!26 = !{!"inline-bug.cc", !"/tmp/dbginfo/pr13202"}
-!27 = !{i32 1, !"Debug Info Version", i32 2}
+!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argument", line: 3, arg: 1, scope: !10, file: !6, type: !9)
+!19 = !DILocation(line: 11, column: 10, scope: !5)
+!21 = !DILocation(line: 3, column: 25, scope: !10, inlinedAt: !19)
+!22 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "local", line: 4, scope: !10, file: !6, type: !9)
+!23 = !DILocation(line: 4, column: 16, scope: !10, inlinedAt: !19)
+!24 = !DILocation(line: 5, column: 3, scope: !10, inlinedAt: !19)
+!25 = !DILocation(line: 6, column: 3, scope: !10, inlinedAt: !19)
+!26 = !DIFile(filename: "inline-bug.cc", directory: "/tmp/dbginfo/pr13202")
+!27 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/location-verifier.ll b/test/DebugInfo/location-verifier.ll
index 0e56be42e1f9..f44a37d7fca5 100644
--- a/test/DebugInfo/location-verifier.ll
+++ b/test/DebugInfo/location-verifier.ll
@@ -15,19 +15,19 @@ attributes #0 = { nounwind ssp uwtable }
 !llvm.module.flags = !{!9, !10, !11}
 !llvm.ident = !{!12}
 
-!0 = !{!"0x11\0012\00clang version 3.7.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/test.c] [DW_LANG_C99]
-!1 = !{!"test.c", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.7.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.c", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\000\000\000\001", !1, !5, !6, null, i32 ()* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}                               ; [ DW_TAG_file_type ] [/test.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 ()* @foo, variables: !2)
+!5 = !DIFile(filename: "test.c", directory: "")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 2}
-!10 = !{i32 2, !"Debug Info Version", i32 2}
+!10 = !{i32 2, !"Debug Info Version", i32 3}
 !11 = !{i32 1, !"PIC Level", i32 2}
 !12 = !{!"clang version 3.7.0 "}
-; An old-style MDLocation should not pass verify.
-; CHECK: DISubprogram does not Verify
+; An old-style DILocation should not pass verify.
+; CHECK: invalid !dbg metadata attachment
 !13 = !{i32 2, i32 2, !4, null}
diff --git a/test/DebugInfo/lto-comp-dir.ll b/test/DebugInfo/lto-comp-dir.ll
index a79cf3248cfc..4bafb7bdd2e7 100644
--- a/test/DebugInfo/lto-comp-dir.ll
+++ b/test/DebugInfo/lto-comp-dir.ll
@@ -59,26 +59,26 @@ attributes #1 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="
 !llvm.module.flags = !{!16, !17}
 !llvm.ident = !{!18, !18}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ]
-!1 = !{!"a.cpp", !"/tmp/dbginfo/a"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "a.cpp", directory: "/tmp/dbginfo/a")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00func\00func\00_Z4funcv\001\000\001\000\006\00256\000\001", !1, !5, !6, null, void ()* @_Z4funcv, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [func]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/a/a.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "func", linkageName: "_Z4funcv", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void ()* @_Z4funcv, variables: !2)
+!5 = !DIFile(filename: "a.cpp", directory: "/tmp/dbginfo/a")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
-!8 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !9, !2, !2, !10, !2, !2} ; [ DW_TAG_compile_unit ]
-!9 = !{!"b.cpp", !"/tmp/dbginfo/b"}
+!8 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !9, enums: !2, retainedTypes: !2, subprograms: !10, globals: !2, imports: !2)
+!9 = !DIFile(filename: "b.cpp", directory: "/tmp/dbginfo/b")
 !10 = !{!11}
-!11 = !{!"0x2e\00main\00main\00\002\000\001\000\006\00256\000\002", !9, !12, !13, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [main]
-!12 = !{!"0x29", !9}         ; [ DW_TAG_file_type ] [/tmp/dbginfo/b/b.cpp]
-!13 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !14, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!11 = !DISubprogram(name: "main", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !9, scope: !12, type: !13, function: i32 ()* @main, variables: !2)
+!12 = !DIFile(filename: "b.cpp", directory: "/tmp/dbginfo/b")
+!13 = !DISubroutineType(types: !14)
 !14 = !{!15}
-!15 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!15 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !16 = !{i32 2, !"Dwarf Version", i32 4}
-!17 = !{i32 1, !"Debug Info Version", i32 2}
+!17 = !{i32 1, !"Debug Info Version", i32 3}
 !18 = !{!"clang version 3.5.0 "}
-!19 = !MDLocation(line: 2, scope: !4)
-!20 = !MDLocation(line: 3, scope: !11)
-!21 = !MDLocation(line: 4, scope: !11)
+!19 = !DILocation(line: 2, scope: !4)
+!20 = !DILocation(line: 3, scope: !11)
+!21 = !DILocation(line: 4, scope: !11)
 
diff --git a/test/DebugInfo/member-order.ll b/test/DebugInfo/member-order.ll
index ae845719cdc9..f07e4f85cded 100644
--- a/test/DebugInfo/member-order.ll
+++ b/test/DebugInfo/member-order.ll
@@ -29,8 +29,8 @@ define void @_ZN3foo2f1Ev(%struct.foo* %this) #0 align 2 {
 entry:
   %this.addr = alloca %struct.foo*, align 8
   store %struct.foo* %this, %struct.foo** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.foo** %this.addr, metadata !16, metadata !{!"0x102"}), !dbg !18
-  %this1 = load %struct.foo** %this.addr
+  call void @llvm.dbg.declare(metadata %struct.foo** %this.addr, metadata !16, metadata !DIExpression()), !dbg !18
+  %this1 = load %struct.foo*, %struct.foo** %this.addr
   ret void, !dbg !19
 }
 
@@ -43,24 +43,24 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!15, !20}
 
-!0 = !{!"0x11\004\00clang version 3.4 \000\00\000\00\000", !1, !2, !3, !13, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/member-order.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"member-order.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !13, globals: !2, imports: !2)
+!1 = !DIFile(filename: "member-order.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00foo\001\008\008\000\000\000", !1, null, null, !5, null, null, !"_ZTS3foo"} ; [ DW_TAG_structure_type ] [foo] [line 1, size 8, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo", line: 1, size: 8, align: 8, file: !1, elements: !5, identifier: "_ZTS3foo")
 !5 = !{!6, !11}
-!6 = !{!"0x2e\00f1\00f1\00_ZN3foo2f1Ev\002\000\000\000\006\00256\000\002", !1, !4, !7, null, null, null, i32 0, !10} ; [ DW_TAG_subprogram ] [line 2] [f1]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DISubprogram(name: "f1", linkageName: "_ZN3foo2f1Ev", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !4, type: !7)
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9}
-!9 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS3foo"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS3foo]
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS3foo")
 !10 = !{i32 786468}
-!11 = !{!"0x2e\00f2\00f2\00_ZN3foo2f2Ev\003\000\000\000\006\00256\000\003", !1, !4, !7, null, null, null, i32 0, !12} ; [ DW_TAG_subprogram ] [line 3] [f2]
+!11 = !DISubprogram(name: "f2", linkageName: "_ZN3foo2f2Ev", line: 3, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !4, type: !7)
 !12 = !{i32 786468}
 !13 = !{!14}
-!14 = !{!"0x2e\00f1\00f1\00_ZN3foo2f1Ev\006\000\001\000\006\00256\000\006", !1, null, !7, null, void (%struct.foo*)* @_ZN3foo2f1Ev, null, !6, !2} ; [ DW_TAG_subprogram ] [line 6] [def] [f1]
+!14 = !DISubprogram(name: "f1", linkageName: "_ZN3foo2f1Ev", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 6, file: !1, scope: null, type: !7, function: void (%struct.foo*)* @_ZN3foo2f1Ev, declaration: !6, variables: !2)
 !15 = !{i32 2, !"Dwarf Version", i32 4}
-!16 = !{!"0x101\00this\0016777216\001088", !14, null, !17} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!17 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS3foo"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS3foo]
-!18 = !MDLocation(line: 0, scope: !14)
-!19 = !MDLocation(line: 7, scope: !14)
-!20 = !{i32 1, !"Debug Info Version", i32 2}
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !14, type: !17)
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS3foo")
+!18 = !DILocation(line: 0, scope: !14)
+!19 = !DILocation(line: 7, scope: !14)
+!20 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/member-pointers.ll b/test/DebugInfo/member-pointers.ll
index 54bb0a548b76..0cf9ead84218 100644
--- a/test/DebugInfo/member-pointers.ll
+++ b/test/DebugInfo/member-pointers.ll
@@ -23,18 +23,18 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!16}
 
-!0 = !{!"0x11\004\00clang version 3.3 \000\00\000\00\000", !15, !1, !1, !1, !3,  !1} ; [ DW_TAG_compile_unit ] [/home/blaikie/Development/scratch/simple.cpp] [DW_LANG_C_plus_plus]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 ", isOptimized: false, emissionKind: 0, file: !15, enums: !1, retainedTypes: !1, subprograms: !1, globals: !3, imports:  !1)
 !1 = !{}
 !3 = !{!5, !10}
-!5 = !{!"0x34\00x\00x\00\004\000\001", null, !6, !7, i64* @x, null} ; [ DW_TAG_variable ] [x] [line 4] [def]
-!6 = !{!"0x29", !15} ; [ DW_TAG_file_type ]
-!7 = !{!"0x1f\00\000\000\000\000\000", null, null, !8, !9} ; [ DW_TAG_ptr_to_member_type ] [line 0, size 0, align 0, offset 0] [from int]
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x13\00S\001\008\008\000\000\000", !15, null, null, !1, null, null, null} ; [ DW_TAG_structure_type ] [S] [line 1, size 8, align 8, offset 0] [def] [from ]
-!10 = !{!"0x34\00y\00y\00\005\000\001", null, !6, !11, { i64, i64 }* @y, null} ; [ DW_TAG_variable ] [y] [line 5] [def]
-!11 = !{!"0x1f\00\000\000\000\000\000", null, null, !12, !9} ; [ DW_TAG_ptr_to_member_type ] [line 0, size 0, align 0, offset 0] [from ]
-!12 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !13, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DIGlobalVariable(name: "x", line: 4, isLocal: false, isDefinition: true, scope: null, file: !6, type: !7, variable: i64* @x)
+!6 = !DIFile(filename: "simple.cpp", directory: "/home/blaikie/Development/scratch")
+!7 = !DIDerivedType(tag: DW_TAG_ptr_to_member_type, baseType: !8, extraData: !9)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DICompositeType(tag: DW_TAG_structure_type, name: "S", line: 1, size: 8, align: 8, file: !15, elements: !1)
+!10 = !DIGlobalVariable(name: "y", line: 5, isLocal: false, isDefinition: true, scope: null, file: !6, type: !11, variable: { i64, i64 }* @y)
+!11 = !DIDerivedType(tag: DW_TAG_ptr_to_member_type, baseType: !12, extraData: !9)
+!12 = !DISubroutineType(types: !13)
 !13 = !{null, !14, !8}
-!14 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from S]
-!15 = !{!"simple.cpp", !"/home/blaikie/Development/scratch"}
-!16 = !{i32 1, !"Debug Info Version", i32 2}
+!14 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !9)
+!15 = !DIFile(filename: "simple.cpp", directory: "/home/blaikie/Development/scratch")
+!16 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/missing-abstract-variable.ll b/test/DebugInfo/missing-abstract-variable.ll
index dcaa2db435d9..8a576c2bfd34 100644
--- a/test/DebugInfo/missing-abstract-variable.ll
+++ b/test/DebugInfo/missing-abstract-variable.ll
@@ -99,7 +99,7 @@
 ; Function Attrs: uwtable
 define void @_Z1bv() #0 {
 entry:
-  tail call void @llvm.dbg.value(metadata i1 false, i64 0, metadata !25, metadata !{!"0x102"}), !dbg !27
+  tail call void @llvm.dbg.value(metadata i1 false, i64 0, metadata !25, metadata !DIExpression()), !dbg !27
   tail call void @_Z1fi(i32 0), !dbg !28
   ret void, !dbg !29
 }
@@ -107,13 +107,13 @@ entry:
 ; Function Attrs: uwtable
 define void @_Z1ab(i1 zeroext %u) #0 {
 entry:
-  tail call void @llvm.dbg.value(metadata i1 %u, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !30
-  tail call void @llvm.dbg.value(metadata i1 %u, i64 0, metadata !31, metadata !{!"0x102"}), !dbg !33
+  tail call void @llvm.dbg.value(metadata i1 %u, i64 0, metadata !13, metadata !DIExpression()), !dbg !30
+  tail call void @llvm.dbg.value(metadata i1 %u, i64 0, metadata !31, metadata !DIExpression()), !dbg !33
   br i1 %u, label %if.then.i, label %_Z1xb.exit, !dbg !34
 
 if.then.i:                                        ; preds = %entry
-  %0 = load i32* @t, align 4, !dbg !35, !tbaa !36
-  tail call void @llvm.dbg.value(metadata i32 %0, i64 0, metadata !40, metadata !{!"0x102"}), !dbg !35
+  %0 = load i32, i32* @t, align 4, !dbg !35, !tbaa !36
+  tail call void @llvm.dbg.value(metadata i32 %0, i64 0, metadata !40, metadata !DIExpression()), !dbg !35
   tail call void @_Z1fi(i32 %0), !dbg !41
   br label %_Z1xb.exit, !dbg !42
 
@@ -135,48 +135,48 @@ attributes #2 = { nounwind readnone }
 !llvm.module.flags = !{!21, !22}
 !llvm.ident = !{!23}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/missing-abstract-variables.cc] [DW_LANG_C_plus_plus]
-!1 = !{!"missing-abstract-variables.cc", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "missing-abstract-variables.cc", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4, !8, !14}
-!4 = !{!"0x2e\00b\00b\00_Z1bv\0013\000\001\000\006\00256\001\0013", !1, !5, !6, null, void ()* @_Z1bv, null, null, !2} ; [ DW_TAG_subprogram ] [line 13] [def] [b]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/missing-abstract-variables.cc]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "b", linkageName: "_Z1bv", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 13, file: !1, scope: !5, type: !6, function: void ()* @_Z1bv, variables: !2)
+!5 = !DIFile(filename: "missing-abstract-variables.cc", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
-!8 = !{!"0x2e\00a\00a\00_Z1ab\0017\000\001\000\006\00256\001\0017", !1, !5, !9, null, void (i1)* @_Z1ab, null, null, !12} ; [ DW_TAG_subprogram ] [line 17] [def] [a]
-!9 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = !DISubprogram(name: "a", linkageName: "_Z1ab", line: 17, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 17, file: !1, scope: !5, type: !9, function: void (i1)* @_Z1ab, variables: !12)
+!9 = !DISubroutineType(types: !10)
 !10 = !{null, !11}
-!11 = !{!"0x24\00bool\000\008\008\000\000\002", null, null} ; [ DW_TAG_base_type ] [bool] [line 0, size 8, align 8, offset 0, enc DW_ATE_boolean]
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "bool", size: 8, align: 8, encoding: DW_ATE_boolean)
 !12 = !{!13}
-!13 = !{!"0x101\00u\0016777233\000", !8, !5, !11} ; [ DW_TAG_arg_variable ] [u] [line 17]
-!14 = !{!"0x2e\00x\00x\00_Z1xb\005\000\001\000\006\00256\001\005", !1, !5, !9, null, null, null, null, !15} ; [ DW_TAG_subprogram ] [line 5] [def] [x]
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "u", line: 17, arg: 1, scope: !8, file: !5, type: !11)
+!14 = !DISubprogram(name: "x", linkageName: "_Z1xb", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !1, scope: !5, type: !9, variables: !15)
 !15 = !{!16, !17}
-!16 = !{!"0x101\00b\0016777221\000", !14, !5, !11} ; [ DW_TAG_arg_variable ] [b] [line 5]
-!17 = !{!"0x100\00s\007\000", !18, !5, !20} ; [ DW_TAG_auto_variable ] [s] [line 7]
-!18 = !{!"0xb\006\000\000", !1, !19} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/missing-abstract-variables.cc]
-!19 = !{!"0xb\006\000\000", !1, !14} ; [ DW_TAG_lexical_block ] [/tmp/dbginfo/missing-abstract-variables.cc]
-!20 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 5, arg: 1, scope: !14, file: !5, type: !11)
+!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "s", line: 7, scope: !18, file: !5, type: !20)
+!18 = distinct !DILexicalBlock(line: 6, column: 0, file: !1, scope: !19)
+!19 = distinct !DILexicalBlock(line: 6, column: 0, file: !1, scope: !14)
+!20 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !21 = !{i32 2, !"Dwarf Version", i32 4}
-!22 = !{i32 2, !"Debug Info Version", i32 2}
+!22 = !{i32 2, !"Debug Info Version", i32 3}
 !23 = !{!"clang version 3.5.0 "}
 !24 = !{i1 false}
-!25 = !{!"0x101\00b\0016777221\000", !14, !5, !11, !26} ; [ DW_TAG_arg_variable ] [b] [line 5]
-!26 = !MDLocation(line: 14, scope: !4)
-!27 = !MDLocation(line: 5, scope: !14, inlinedAt: !26)
-!28 = !MDLocation(line: 10, scope: !14, inlinedAt: !26)
-!29 = !MDLocation(line: 15, scope: !4)
-!30 = !MDLocation(line: 17, scope: !8)
-!31 = !{!"0x101\00b\0016777221\000", !14, !5, !11, !32} ; [ DW_TAG_arg_variable ] [b] [line 5]
-!32 = !MDLocation(line: 18, scope: !8)
-!33 = !MDLocation(line: 5, scope: !14, inlinedAt: !32)
-!34 = !MDLocation(line: 6, scope: !19, inlinedAt: !32)
-!35 = !MDLocation(line: 7, scope: !18, inlinedAt: !32)
+!25 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 5, arg: 1, scope: !14, file: !5, type: !11)
+!26 = !DILocation(line: 14, scope: !4)
+!27 = !DILocation(line: 5, scope: !14, inlinedAt: !26)
+!28 = !DILocation(line: 10, scope: !14, inlinedAt: !26)
+!29 = !DILocation(line: 15, scope: !4)
+!30 = !DILocation(line: 17, scope: !8)
+!31 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 5, arg: 1, scope: !14, file: !5, type: !11)
+!32 = !DILocation(line: 18, scope: !8)
+!33 = !DILocation(line: 5, scope: !14, inlinedAt: !32)
+!34 = !DILocation(line: 6, scope: !19, inlinedAt: !32)
+!35 = !DILocation(line: 7, scope: !18, inlinedAt: !32)
 !36 = !{!37, !37, i64 0}
 !37 = !{!"int", !38, i64 0}
 !38 = !{!"omnipotent char", !39, i64 0}
 !39 = !{!"Simple C/C++ TBAA"}
-!40 = !{!"0x100\00s\007\000", !18, !5, !20, !32} ; [ DW_TAG_auto_variable ] [s] [line 7]
-!41 = !MDLocation(line: 8, scope: !18, inlinedAt: !32)
-!42 = !MDLocation(line: 9, scope: !18, inlinedAt: !32)
-!43 = !MDLocation(line: 10, scope: !14, inlinedAt: !32)
-!44 = !MDLocation(line: 19, scope: !8)
+!40 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "s", line: 7, scope: !18, file: !5, type: !20)
+!41 = !DILocation(line: 8, scope: !18, inlinedAt: !32)
+!42 = !DILocation(line: 9, scope: !18, inlinedAt: !32)
+!43 = !DILocation(line: 10, scope: !14, inlinedAt: !32)
+!44 = !DILocation(line: 19, scope: !8)
diff --git a/test/DebugInfo/multiline.ll b/test/DebugInfo/multiline.ll
index e67af328416f..e6b43239fda3 100644
--- a/test/DebugInfo/multiline.ll
+++ b/test/DebugInfo/multiline.ll
@@ -44,12 +44,12 @@
 ; Function Attrs: nounwind uwtable
 define void @f2() #0 {
 entry:
-  call void (...)* @f1(), !dbg !11
-  call void (...)* @f1(), !dbg !12
-  call void (...)* @f1(), !dbg !13
-  call void (...)* @f1(), !dbg !14
-  call void (...)* @f1(), !dbg !15
-  call void (...)* @f1(), !dbg !16
+  call void (...) @f1(), !dbg !11
+  call void (...) @f1(), !dbg !12
+  call void (...) @f1(), !dbg !13
+  call void (...) @f1(), !dbg !14
+  call void (...) @f1(), !dbg !15
+  call void (...) @f1(), !dbg !16
   ret void, !dbg !17
 }
 
@@ -62,21 +62,21 @@ attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n
 !llvm.module.flags = !{!8, !9}
 !llvm.ident = !{!10}
 
-!0 = !{!"0x11\0012\00clang version 3.6.0 (trunk 225000) (llvm/trunk 224999)\000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/multiline.c] [DW_LANG_C99]
-!1 = !{!"multiline.c", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.6.0 (trunk 225000) (llvm/trunk 224999)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "multiline.c", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00f2\00f2\00\002\000\001\000\000\000\000\002", !1, !5, !6, null, void ()* @f2, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [f2]
-!5 = !{!"0x29", !1}                               ; [ DW_TAG_file_type ] [/tmp/dbginfo/multiline.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "f2", line: 2, isLocal: false, isDefinition: true, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !6, function: void ()* @f2, variables: !2)
+!5 = !DIFile(filename: "multiline.c", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
 !8 = !{i32 2, !"Dwarf Version", i32 4}
-!9 = !{i32 2, !"Debug Info Version", i32 2}
+!9 = !{i32 2, !"Debug Info Version", i32 3}
 !10 = !{!"clang version 3.6.0 (trunk 225000) (llvm/trunk 224999)"}
-!11 = !MDLocation(line: 3, column: 3, scope: !4)
-!12 = !MDLocation(line: 3, column: 9, scope: !4)
-!13 = !MDLocation(line: 3, column: 15, scope: !4)
-!14 = !MDLocation(line: 4, column: 3, scope: !4)
-!15 = !MDLocation(line: 4, column: 9, scope: !4)
-!16 = !MDLocation(line: 4, column: 15, scope: !4)
-!17 = !MDLocation(line: 5, column: 1, scope: !4)
+!11 = !DILocation(line: 3, column: 3, scope: !4)
+!12 = !DILocation(line: 3, column: 9, scope: !4)
+!13 = !DILocation(line: 3, column: 15, scope: !4)
+!14 = !DILocation(line: 4, column: 3, scope: !4)
+!15 = !DILocation(line: 4, column: 9, scope: !4)
+!16 = !DILocation(line: 4, column: 15, scope: !4)
+!17 = !DILocation(line: 5, column: 1, scope: !4)
diff --git a/test/DebugInfo/namespace.ll b/test/DebugInfo/namespace.ll
index a4fdbd27a89d..85ef7356205c 100644
--- a/test/DebugInfo/namespace.ll
+++ b/test/DebugInfo/namespace.ll
@@ -238,32 +238,32 @@ entry:
   %frombool = zext i1 %b to i8
   store i8 %frombool, i8* %b.addr, align 1
   call void @llvm.dbg.declare(metadata i8* %b.addr, metadata !66, metadata !62), !dbg !67
-  %0 = load i8* %b.addr, align 1, !dbg !68
+  %0 = load i8, i8* %b.addr, align 1, !dbg !68
   %tobool = trunc i8 %0 to i1, !dbg !68
   br i1 %tobool, label %if.then, label %if.end, !dbg !68
 
 if.then:                                          ; preds = %entry
-  %1 = load i32* @_ZN1A1B1iE, align 4, !dbg !69
+  %1 = load i32, i32* @_ZN1A1B1iE, align 4, !dbg !69
   store i32 %1, i32* %retval, !dbg !69
   br label %return, !dbg !69
 
 if.end:                                           ; preds = %entry
-  %2 = load i32* @_ZN1A1B1iE, align 4, !dbg !70
-  %3 = load i32* @_ZN1A1B1iE, align 4, !dbg !70
+  %2 = load i32, i32* @_ZN1A1B1iE, align 4, !dbg !70
+  %3 = load i32, i32* @_ZN1A1B1iE, align 4, !dbg !70
   %add = add nsw i32 %2, %3, !dbg !70
-  %4 = load i32* @_ZN1A1B1iE, align 4, !dbg !70
+  %4 = load i32, i32* @_ZN1A1B1iE, align 4, !dbg !70
   %add1 = add nsw i32 %add, %4, !dbg !70
   store i32 %add1, i32* %retval, !dbg !70
   br label %return, !dbg !70
 
 return:                                           ; preds = %if.end, %if.then
-  %5 = load i32* %retval, !dbg !71
+  %5 = load i32, i32* %retval, !dbg !71
   ret i32 %5, !dbg !71
 }
 
 define internal void @__cxx_global_var_init1() section "__TEXT,__StaticInit,regular,pure_instructions" {
 entry:
-  %0 = load i32* @_ZN1A1B1iE, align 4, !dbg !72
+  %0 = load i32, i32* @_ZN1A1B1iE, align 4, !dbg !72
   store i32 %0, i32* @_ZN1A1B7var_fwdE, align 4, !dbg !72
   ret void, !dbg !72
 }
@@ -288,79 +288,79 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!57, !58}
 !llvm.ident = !{!59}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 \000\00\000\00\001", !1, !2, !3, !9, !30, !33} ; [ DW_TAG_compile_unit ] [/tmp/debug-info-namespace.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"debug-info-namespace.cpp", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !9, globals: !30, imports: !33)
+!1 = !DIFile(filename: "debug-info-namespace.cpp", directory: "/tmp")
 !2 = !{}
 !3 = !{!4, !8}
-!4 = !{!"0x13\00foo\005\000\000\000\004\000", !5, !6, null, null, null, null, !"_ZTSN1A1B3fooE"} ; [ DW_TAG_structure_type ] [foo] [line 5, size 0, align 0, offset 0] [decl] [from ]
-!5 = !{!"foo.cpp", !"/tmp"}
-!6 = !{!"0x39\00B\001", !5, !7} ; [ DW_TAG_namespace ] [B] [line 1]
-!7 = !{!"0x39\00A\005", !1, null} ; [ DW_TAG_namespace ] [A] [line 5]
-!8 = !{!"0x13\00bar\006\008\008\000\000\000", !5, !6, null, !2, null, null, !"_ZTSN1A1B3barE"} ; [ DW_TAG_structure_type ] [bar] [line 6, size 8, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "foo", line: 5, flags: DIFlagFwdDecl, file: !5, scope: !6, identifier: "_ZTSN1A1B3fooE")
+!5 = !DIFile(filename: "foo.cpp", directory: "/tmp")
+!6 = !DINamespace(name: "B", line: 1, file: !5, scope: !7)
+!7 = !DINamespace(name: "A", line: 5, file: !1, scope: null)
+!8 = !DICompositeType(tag: DW_TAG_structure_type, name: "bar", line: 6, size: 8, align: 8, file: !5, scope: !6, elements: !2, identifier: "_ZTSN1A1B3barE")
 !9 = !{!10, !14, !17, !21, !25, !26, !27}
-!10 = !{!"0x2e\00f1\00f1\00_ZN1A1B2f1Ev\003\000\001\000\000\00256\000\003", !5, !6, !11, null, i32 ()* @_ZN1A1B2f1Ev, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [f1]
-!11 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!10 = !DISubprogram(name: "f1", linkageName: "_ZN1A1B2f1Ev", line: 3, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !5, scope: !6, type: !11, function: i32 ()* @_ZN1A1B2f1Ev, variables: !2)
+!11 = !DISubroutineType(types: !12)
 !12 = !{!13}
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!14 = !{!"0x2e\00f1\00f1\00_ZN1A1B2f1Ei\004\000\001\000\000\00256\000\004", !5, !6, !15, null, void (i32)* @_ZN1A1B2f1Ei, null, null, !2} ; [ DW_TAG_subprogram ] [line 4] [def] [f1]
-!15 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!14 = !DISubprogram(name: "f1", linkageName: "_ZN1A1B2f1Ei", line: 4, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !5, scope: !6, type: !15, function: void (i32)* @_ZN1A1B2f1Ei, variables: !2)
+!15 = !DISubroutineType(types: !16)
 !16 = !{null, !13}
-!17 = !{!"0x2e\00__cxx_global_var_init\00__cxx_global_var_init\00\0020\001\001\000\000\00256\000\0020", !5, !18, !19, null, void ()* @__cxx_global_var_init, null, null, !2} ; [ DW_TAG_subprogram ] [line 20] [local] [def] [__cxx_global_var_init]
-!18 = !{!"0x29", !5}   ; [ DW_TAG_file_type ] [/tmp/foo.cpp]
-!19 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !20, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!17 = !DISubprogram(name: "__cxx_global_var_init", line: 20, isLocal: true, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 20, file: !5, scope: !18, type: !19, function: void ()* @__cxx_global_var_init, variables: !2)
+!18 = !DIFile(filename: "foo.cpp", directory: "/tmp")
+!19 = !DISubroutineType(types: !20)
 !20 = !{null}
-!21 = !{!"0x2e\00func\00func\00_Z4funcb\0021\000\001\000\000\00256\000\0021", !5, !18, !22, null, i32 (i1)* @_Z4funcb, null, null, !2} ; [ DW_TAG_subprogram ] [line 21] [def] [func]
-!22 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !23, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!21 = !DISubprogram(name: "func", linkageName: "_Z4funcb", line: 21, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 21, file: !5, scope: !18, type: !22, function: i32 (i1)* @_Z4funcb, variables: !2)
+!22 = !DISubroutineType(types: !23)
 !23 = !{!13, !24}
-!24 = !{!"0x24\00bool\000\008\008\000\000\002", null, null} ; [ DW_TAG_base_type ] [bool] [line 0, size 8, align 8, offset 0, enc DW_ATE_boolean]
-!25 = !{!"0x2e\00__cxx_global_var_init1\00__cxx_global_var_init1\00\0044\001\001\000\000\00256\000\0044", !5, !18, !19, null, void ()* @__cxx_global_var_init1, null, null, !2} ; [ DW_TAG_subprogram ] [line 44] [local] [def] [__cxx_global_var_init1]
-!26 = !{!"0x2e\00func_fwd\00func_fwd\00_ZN1A1B8func_fwdEv\0047\000\001\000\000\00256\000\0047", !5, !6, !19, null, void ()* @_ZN1A1B8func_fwdEv, null, null, !2} ; [ DW_TAG_subprogram ] [line 47] [def] [func_fwd]
-!27 = !{!"0x2e\00\00\00_GLOBAL__sub_I_debug_info_namespace.cpp\000\001\001\000\000\0064\000\000", !1, !28, !29, null, void ()* @_GLOBAL__sub_I_debug_info_namespace.cpp, null, null, !2} ; [ DW_TAG_subprogram ] [line 0] [local] [def]
-!28 = !{!"0x29", !1}   ; [ DW_TAG_file_type ] [/tmp/debug-info-namespace.cpp]
-!29 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!24 = !DIBasicType(tag: DW_TAG_base_type, name: "bool", size: 8, align: 8, encoding: DW_ATE_boolean)
+!25 = !DISubprogram(name: "__cxx_global_var_init1", line: 44, isLocal: true, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 44, file: !5, scope: !18, type: !19, function: void ()* @__cxx_global_var_init1, variables: !2)
+!26 = !DISubprogram(name: "func_fwd", linkageName: "_ZN1A1B8func_fwdEv", line: 47, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 47, file: !5, scope: !6, type: !19, function: void ()* @_ZN1A1B8func_fwdEv, variables: !2)
+!27 = !DISubprogram(name: "", linkageName: "_GLOBAL__sub_I_debug_info_namespace.cpp", isLocal: true, isDefinition: true, flags: DIFlagArtificial, isOptimized: false, file: !1, scope: !28, type: !29, function: void ()* @_GLOBAL__sub_I_debug_info_namespace.cpp, variables: !2)
+!28 = !DIFile(filename: "debug-info-namespace.cpp", directory: "/tmp")
+!29 = !DISubroutineType(types: !2)
 !30 = !{!31, !32}
-!31 = !{!"0x34\00i\00i\00_ZN1A1B1iE\0020\000\001", !6, !18, !13, i32* @_ZN1A1B1iE, null} ; [ DW_TAG_variable ] [i] [line 20] [def]
-!32 = !{!"0x34\00var_fwd\00var_fwd\00_ZN1A1B7var_fwdE\0044\000\001", !6, !18, !13, i32* @_ZN1A1B7var_fwdE, null} ; [ DW_TAG_variable ] [var_fwd] [line 44] [def]
+!31 = !DIGlobalVariable(name: "i", linkageName: "_ZN1A1B1iE", line: 20, isLocal: false, isDefinition: true, scope: !6, file: !18, type: !13, variable: i32* @_ZN1A1B1iE)
+!32 = !DIGlobalVariable(name: "var_fwd", linkageName: "_ZN1A1B7var_fwdE", line: 44, isLocal: false, isDefinition: true, scope: !6, file: !18, type: !13, variable: i32* @_ZN1A1B7var_fwdE)
 !33 = !{!34, !35, !36, !37, !40, !41, !42, !43, !44, !45, !47, !48, !49, !51, !54, !55, !56}
-!34 = !{!"0x3a\0015\00", !7, !6} ; [ DW_TAG_imported_module ]
-!35 = !{!"0x3a\0018\00", !0, !7} ; [ DW_TAG_imported_module ]
-!36 = !{!"0x8\0019\00E", !0, !7} ; [ DW_TAG_imported_declaration ]
-!37 = !{!"0x3a\0023\00", !38, !6} ; [ DW_TAG_imported_module ]
-!38 = !{!"0xb\0022\0010\001", !5, !39} ; [ DW_TAG_lexical_block ] [/tmp/foo.cpp]
-!39 = !{!"0xb\0022\007\000", !5, !21} ; [ DW_TAG_lexical_block ] [/tmp/foo.cpp]
-!40 = !{!"0x3a\0026\00", !21, !7} ; [ DW_TAG_imported_module ]
-!41 = !{!"0x8\0027\00", !21, !"_ZTSN1A1B3fooE"} ; [ DW_TAG_imported_declaration ]
-!42 = !{!"0x8\0028\00", !21, !"_ZTSN1A1B3barE"} ; [ DW_TAG_imported_declaration ]
-!43 = !{!"0x8\0029\00", !21, !14} ; [ DW_TAG_imported_declaration ]
-!44 = !{!"0x8\0030\00", !21, !31} ; [ DW_TAG_imported_declaration ]
-!45 = !{!"0x8\0031\00", !21, !46} ; [ DW_TAG_imported_declaration ]
-!46 = !{!"0x16\00baz\007\000\000\000\000", !5, !6, !"_ZTSN1A1B3barE"} ; [ DW_TAG_typedef ] [baz] [line 7, size 0, align 0, offset 0] [from _ZTSN1A1B3barE]
-!47 = !{!"0x8\0032\00X", !21, !7} ; [ DW_TAG_imported_declaration ]
-!48 = !{!"0x8\0033\00Y", !21, !47} ; [ DW_TAG_imported_declaration ]
-!49 = !{!"0x8\0034\00", !21, !50} ; [ DW_TAG_imported_declaration ]
-!50 = !{!"0x34\00var_decl\00var_decl\00_ZN1A1B8var_declE\008\000\000", !6, !18, !13, null, null} ; [ DW_TAG_variable ] [var_decl] [line 8]
-!51 = !{!"0x8\0035\00", !21, !52} ; [ DW_TAG_imported_declaration ]
-!52 = !{!"0x2e\00func_decl\00func_decl\00_ZN1A1B9func_declEv\009\000\000\000\000\00256\000\000", !5, !6, !19, null, null, null, null, !53} ; [ DW_TAG_subprogram ] [line 9] [scope 0] [func_decl]
-!53 = !{!"0x24"}
-!54 = !{!"0x8\0036\00", !21, !32} ; [ DW_TAG_imported_declaration ]
-!55 = !{!"0x8\0037\00", !21, !26} ; [ DW_TAG_imported_declaration ]
-!56 = !{!"0x8\0042\00", !7, !31} ; [ DW_TAG_imported_declaration ]
+!34 = !DIImportedEntity(tag: DW_TAG_imported_module, line: 15, scope: !7, entity: !6)
+!35 = !DIImportedEntity(tag: DW_TAG_imported_module, line: 18, scope: !0, entity: !7)
+!36 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 19, name: "E", scope: !0, entity: !7)
+!37 = !DIImportedEntity(tag: DW_TAG_imported_module, line: 23, scope: !38, entity: !6)
+!38 = distinct !DILexicalBlock(line: 22, column: 10, file: !5, scope: !39)
+!39 = distinct !DILexicalBlock(line: 22, column: 7, file: !5, scope: !21)
+!40 = !DIImportedEntity(tag: DW_TAG_imported_module, line: 26, scope: !21, entity: !7)
+!41 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 27, scope: !21, entity: !"_ZTSN1A1B3fooE")
+!42 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 28, scope: !21, entity: !"_ZTSN1A1B3barE")
+!43 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 29, scope: !21, entity: !14)
+!44 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 30, scope: !21, entity: !31)
+!45 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 31, scope: !21, entity: !46)
+!46 = !DIDerivedType(tag: DW_TAG_typedef, name: "baz", line: 7, file: !5, scope: !6, baseType: !"_ZTSN1A1B3barE")
+!47 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 32, name: "X", scope: !21, entity: !7)
+!48 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 33, name: "Y", scope: !21, entity: !47)
+!49 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 34, scope: !21, entity: !50)
+!50 = !DIGlobalVariable(name: "var_decl", linkageName: "_ZN1A1B8var_declE", line: 8, isLocal: false, isDefinition: false, scope: !6, file: !18, type: !13)
+!51 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 35, scope: !21, entity: !52)
+!52 = !DISubprogram(name: "func_decl", linkageName: "_ZN1A1B9func_declEv", line: 9, isLocal: false, isDefinition: false, flags: DIFlagPrototyped, isOptimized: false, file: !5, scope: !6, type: !19, variables: !53)
+!53 = !{} ; previously: invalid DW_TAG_base_type
+!54 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 36, scope: !21, entity: !32)
+!55 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 37, scope: !21, entity: !26)
+!56 = !DIImportedEntity(tag: DW_TAG_imported_declaration, line: 42, scope: !7, entity: !31)
 !57 = !{i32 2, !"Dwarf Version", i32 2}
-!58 = !{i32 2, !"Debug Info Version", i32 2}
+!58 = !{i32 2, !"Debug Info Version", i32 3}
 !59 = !{!"clang version 3.6.0 "}
-!60 = !MDLocation(line: 3, column: 12, scope: !10)
-!61 = !{!"0x101\00\0016777220\000", !14, !18, !13} ; [ DW_TAG_arg_variable ] [line 4]
-!62 = !{!"0x102"}               ; [ DW_TAG_expression ]
-!63 = !MDLocation(line: 4, column: 12, scope: !14)
-!64 = !MDLocation(line: 4, column: 16, scope: !14)
-!65 = !MDLocation(line: 20, column: 12, scope: !17)
-!66 = !{!"0x101\00b\0016777237\000", !21, !18, !24} ; [ DW_TAG_arg_variable ] [b] [line 21]
-!67 = !MDLocation(line: 21, column: 15, scope: !21)
-!68 = !MDLocation(line: 22, column: 7, scope: !21)
-!69 = !MDLocation(line: 24, column: 5, scope: !38)
-!70 = !MDLocation(line: 38, column: 3, scope: !21)
-!71 = !MDLocation(line: 39, column: 1, scope: !21)
-!72 = !MDLocation(line: 44, column: 15, scope: !25)
-!73 = !MDLocation(line: 47, column: 21, scope: !26)
-!74 = !MDLocation(line: 0, scope: !75)
-!75 = !{!"0xb\000", !5, !27} ; [ DW_TAG_lexical_block ] [/tmp/foo.cpp]
+!60 = !DILocation(line: 3, column: 12, scope: !10)
+!61 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "", line: 4, arg: 1, scope: !14, file: !18, type: !13)
+!62 = !DIExpression()
+!63 = !DILocation(line: 4, column: 12, scope: !14)
+!64 = !DILocation(line: 4, column: 16, scope: !14)
+!65 = !DILocation(line: 20, column: 12, scope: !17)
+!66 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 21, arg: 1, scope: !21, file: !18, type: !24)
+!67 = !DILocation(line: 21, column: 15, scope: !21)
+!68 = !DILocation(line: 22, column: 7, scope: !21)
+!69 = !DILocation(line: 24, column: 5, scope: !38)
+!70 = !DILocation(line: 38, column: 3, scope: !21)
+!71 = !DILocation(line: 39, column: 1, scope: !21)
+!72 = !DILocation(line: 44, column: 15, scope: !25)
+!73 = !DILocation(line: 47, column: 21, scope: !26)
+!74 = !DILocation(line: 0, scope: !75)
+!75 = !DILexicalBlockFile(discriminator: 0, file: !5, scope: !27)
diff --git a/test/DebugInfo/namespace_function_definition.ll b/test/DebugInfo/namespace_function_definition.ll
index 02c55bf094a2..44340635484a 100644
--- a/test/DebugInfo/namespace_function_definition.ll
+++ b/test/DebugInfo/namespace_function_definition.ll
@@ -14,7 +14,7 @@
 ; CHECK-NOT: DW_TAG
 ; CHECK:   DW_AT_low_pc
 ; CHECK-NOT: DW_TAG
-; CHECK:   DW_AT_MIPS_linkage_name {{.*}} "_ZN2ns4funcEv"
+; CHECK:   DW_AT_linkage_name {{.*}} "_ZN2ns4funcEv"
 ; CHECK: NULL
 ; CHECK: NULL
 
@@ -30,15 +30,15 @@ attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointe
 !llvm.module.flags = !{!8, !9}
 !llvm.ident = !{!10}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/namespace_function_definition.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"namespace_function_definition.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "namespace_function_definition.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00func\00func\00_ZN2ns4funcEv\002\000\001\000\006\00256\000\002", !1, !5, !6, null, void ()* @_ZN2ns4funcEv, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [func]
-!5 = !{!"0x39\00ns\001", !1, null} ; [ DW_TAG_namespace ] [ns] [line 1]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "func", linkageName: "_ZN2ns4funcEv", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !6, function: void ()* @_ZN2ns4funcEv, variables: !2)
+!5 = !DINamespace(name: "ns", line: 1, file: !1, scope: null)
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
 !8 = !{i32 2, !"Dwarf Version", i32 4}
-!9 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !{i32 1, !"Debug Info Version", i32 3}
 !10 = !{!"clang version 3.5.0 "}
-!11 = !MDLocation(line: 3, scope: !4)
+!11 = !DILocation(line: 3, scope: !4)
diff --git a/test/DebugInfo/namespace_inline_function_definition.ll b/test/DebugInfo/namespace_inline_function_definition.ll
index b6f1b5ff2c0b..c14152065b72 100644
--- a/test/DebugInfo/namespace_inline_function_definition.ll
+++ b/test/DebugInfo/namespace_inline_function_definition.ll
@@ -17,7 +17,7 @@
 ; CHECK-NOT: DW_TAG
 ; CHECK:   DW_TAG_subprogram
 ; CHECK-NOT: DW_TAG
-; CHECK:   DW_AT_MIPS_linkage_name {{.*}} "_ZN2ns4funcEi"
+; CHECK:   DW_AT_linkage_name {{.*}} "_ZN2ns4funcEi"
 ; CHECK-NOT: DW_TAG
 ; CHECK:   DW_TAG_formal_parameter
 ; CHECK:   NULL
@@ -40,10 +40,10 @@ entry:
   %i.addr.i = alloca i32, align 4
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
-  %0 = load i32* @x, align 4, !dbg !16
+  %0 = load i32, i32* @x, align 4, !dbg !16
   store i32 %0, i32* %i.addr.i, align 4
-  call void @llvm.dbg.declare(metadata i32* %i.addr.i, metadata !17, metadata !{!"0x102"}), !dbg !18
-  %1 = load i32* %i.addr.i, align 4, !dbg !18
+  call void @llvm.dbg.declare(metadata i32* %i.addr.i, metadata !117, metadata !DIExpression()), !dbg !18
+  %1 = load i32, i32* %i.addr.i, align 4, !dbg !18
   %mul.i = mul nsw i32 %1, 2, !dbg !18
   ret i32 %mul.i, !dbg !16
 }
@@ -53,8 +53,8 @@ define i32 @_ZN2ns4funcEi(i32 %i) #1 {
 entry:
   %i.addr = alloca i32, align 4
   store i32 %i, i32* %i.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %i.addr, metadata !17, metadata !{!"0x102"}), !dbg !19
-  %0 = load i32* %i.addr, align 4, !dbg !19
+  call void @llvm.dbg.declare(metadata i32* %i.addr, metadata !17, metadata !DIExpression()), !dbg !19
+  %0 = load i32, i32* %i.addr, align 4, !dbg !19
   %mul = mul nsw i32 %0, 2, !dbg !19
   ret i32 %mul, !dbg !19
 }
@@ -70,23 +70,26 @@ attributes #2 = { nounwind readnone }
 !llvm.module.flags = !{!13, !14}
 !llvm.ident = !{!15}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/namespace_inline_function_definition.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"namespace_inline_function_definition.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "namespace_inline_function_definition.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4, !9}
-!4 = !{!"0x2e\00main\00main\00\005\000\001\000\006\00256\000\005", !1, !5, !6, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [main]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/namespace_inline_function_definition.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "main", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, function: i32 ()* @main, variables: !2)
+!5 = !DIFile(filename: "namespace_inline_function_definition.cpp", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x2e\00func\00func\00_ZN2ns4funcEi\006\000\001\000\006\00256\000\006", !1, !10, !11, null, i32 (i32)* @_ZN2ns4funcEi, null, null, !2} ; [ DW_TAG_subprogram ] [line 6] [def] [func]
-!10 = !{!"0x39\00ns\001", !1, null} ; [ DW_TAG_namespace ] [ns] [line 1]
-!11 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DISubprogram(name: "func", linkageName: "_ZN2ns4funcEi", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 6, file: !1, scope: !10, type: !11, function: i32 (i32)* @_ZN2ns4funcEi, variables: !2)
+!10 = !DINamespace(name: "ns", line: 1, file: !1, scope: null)
+!11 = !DISubroutineType(types: !12)
 !12 = !{!8, !8}
 !13 = !{i32 2, !"Dwarf Version", i32 4}
-!14 = !{i32 2, !"Debug Info Version", i32 2}
+!14 = !{i32 2, !"Debug Info Version", i32 3}
 !15 = !{!"clang version 3.5.0 "}
-!16 = !MDLocation(line: 5, scope: !4)
-!17 = !{!"0x101\00i\0016777222\000", !9, !5, !8} ; [ DW_TAG_arg_variable ] [i] [line 6]
-!18 = !MDLocation(line: 6, scope: !9, inlinedAt: !16)
-!19 = !MDLocation(line: 6, scope: !9)
+!16 = !DILocation(line: 5, scope: !4)
+!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 6, arg: 1, scope: !9, file: !5, type: !8)
+
+!117 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 6, arg: 1, scope: !9, file: !5, type: !8)
+
+!18 = !DILocation(line: 6, scope: !9, inlinedAt: !16)
+!19 = !DILocation(line: 6, scope: !9)
diff --git a/test/DebugInfo/nodebug.ll b/test/DebugInfo/nodebug.ll
index 83ce2625603c..3ef3119a0c77 100644
--- a/test/DebugInfo/nodebug.ll
+++ b/test/DebugInfo/nodebug.ll
@@ -37,15 +37,15 @@ attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="
 !llvm.module.flags = !{!8, !9}
 !llvm.ident = !{!10}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/nodebug.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"nodebug.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "nodebug.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00f1\00f1\00_Z2f1v\002\000\001\000\006\00256\000\002", !1, !5, !6, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [f1]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/nodebug.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "f1", linkageName: "_Z2f1v", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !6, variables: !2)
+!5 = !DIFile(filename: "nodebug.cpp", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
 !8 = !{i32 2, !"Dwarf Version", i32 4}
-!9 = !{i32 2, !"Debug Info Version", i32 2}
+!9 = !{i32 2, !"Debug Info Version", i32 3}
 !10 = !{!"clang version 3.5.0 "}
-!11 = !MDLocation(line: 3, scope: !4)
+!11 = !DILocation(line: 3, scope: !4)
diff --git a/test/DebugInfo/piece-verifier.ll b/test/DebugInfo/piece-verifier.ll
new file mode 100644
index 000000000000..9d7efd6a396f
--- /dev/null
+++ b/test/DebugInfo/piece-verifier.ll
@@ -0,0 +1,56 @@
+; RUN: not llvm-as -disable-output < %s 2>&1 | FileCheck %s
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.9.0"
+
+; Function Attrs: nounwind ssp uwtable
+define i32 @foo(i64 %s.coerce0, i32 %s.coerce1) #0 {
+entry:
+  call void @llvm.dbg.value(metadata i64 %s.coerce0, i64 0, metadata !20, metadata !24), !dbg !21
+  call void @llvm.dbg.value(metadata i32 %s.coerce1, i64 0, metadata !22, metadata !27), !dbg !21
+  ret i32 %s.coerce1, !dbg !23
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
+
+attributes #0 = { nounwind ssp uwtable "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!17, !18}
+!llvm.ident = !{!19}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "pieces.c", directory: "")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "foo", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !1, scope: !5, type: !6, function: i32 (i64, i32)* @foo, variables: !15)
+!5 = !DIFile(filename: "pieces.c", directory: "")
+!6 = !DISubroutineType(types: !7)
+!7 = !{!8, !9}
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_typedef, name: "S", line: 1, file: !1, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_structure_type, line: 1, size: 128, align: 64, file: !1, elements: !11)
+!11 = !{!12, !14}
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 1, size: 64, align: 64, file: !1, scope: !10, baseType: !13)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "long int", size: 64, align: 64, encoding: DW_ATE_signed)
+!14 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 1, size: 32, align: 32, offset: 64, file: !1, scope: !10, baseType: !8)
+!15 = !{!16}
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "s", line: 3, arg: 1, scope: !4, file: !5, type: !9)
+!17 = !{i32 2, !"Dwarf Version", i32 4}
+!18 = !{i32 1, !"Debug Info Version", i32 3}
+!19 = !{!"clang version 3.5 "}
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "s", line: 3, arg: 1, scope: !4, file: !5, type: !9)
+!21 = !DILocation(line: 3, scope: !4)
+!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "s", line: 3, arg: 1, scope: !4, file: !5, type: !9)
+!23 = !DILocation(line: 4, scope: !4)
+!24 = !DIExpression(DW_OP_deref, DW_OP_bit_piece, 0, 64)
+!25 = !{}
+; This expression has elements after DW_OP_bit_piece.
+; CHECK: invalid expression
+; CHECK-NEXT: !DIExpression({{[0-9]+}}, 64, 32, {{[0-9]+}})
+; CHECK-NOT: invalid expression
+!27 = !DIExpression(DW_OP_bit_piece, 64, 32, DW_OP_deref)
diff --git a/test/DebugInfo/restrict.ll b/test/DebugInfo/restrict.ll
index 54bdec7affaf..71d94f60c965 100644
--- a/test/DebugInfo/restrict.ll
+++ b/test/DebugInfo/restrict.ll
@@ -21,7 +21,7 @@ define void @_Z3fooPv(i8* noalias %dst) #0 {
 entry:
   %dst.addr = alloca i8*, align 8
   store i8* %dst, i8** %dst.addr, align 8
-  call void @llvm.dbg.declare(metadata i8** %dst.addr, metadata !13, metadata !{!"0x102"}), !dbg !14
+  call void @llvm.dbg.declare(metadata i8** %dst.addr, metadata !13, metadata !DIExpression()), !dbg !14
   ret void, !dbg !15
 }
 
@@ -35,19 +35,19 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!10, !11}
 !llvm.ident = !{!12}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/restrict.c] [DW_LANG_C_plus_plus]
-!1 = !{!"restrict.c", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "restrict.c", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00_Z3fooPv\001\000\001\000\006\00256\000\001", !1, !5, !6, null, void (i8*)* @_Z3fooPv, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/restrict.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", linkageName: "_Z3fooPv", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void (i8*)* @_Z3fooPv, variables: !2)
+!5 = !DIFile(filename: "restrict.c", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null, !8}
-!8 = !{!"0x37\00\000\000\000\000\000", null, null, !9} ; [ DW_TAG_restrict_type ] [line 0, size 0, align 0, offset 0] [from ]
-!9 = !{!"0xf\00\000\0064\0064\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
+!8 = !DIDerivedType(tag: DW_TAG_restrict_type, baseType: !9)
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: null)
 !10 = !{i32 2, !"Dwarf Version", i32 4}
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!11 = !{i32 1, !"Debug Info Version", i32 3}
 !12 = !{!"clang version 3.5.0 "}
-!13 = !{!"0x101\00dst\0016777217\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [dst] [line 1]
-!14 = !MDLocation(line: 1, scope: !4)
-!15 = !MDLocation(line: 2, scope: !4)
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "dst", line: 1, arg: 1, scope: !4, file: !5, type: !8)
+!14 = !DILocation(line: 1, scope: !4)
+!15 = !DILocation(line: 2, scope: !4)
diff --git a/test/DebugInfo/sugared-constants.ll b/test/DebugInfo/sugared-constants.ll
index 9e4f374e9fa3..421fe1dcd85c 100644
--- a/test/DebugInfo/sugared-constants.ll
+++ b/test/DebugInfo/sugared-constants.ll
@@ -24,11 +24,11 @@
 ; Function Attrs: uwtable
 define i32 @main() #0 {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 42, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !21
+  tail call void @llvm.dbg.value(metadata i32 42, i64 0, metadata !10, metadata !DIExpression()), !dbg !21
   tail call void @_Z4funci(i32 42), !dbg !22
-  tail call void @llvm.dbg.value(metadata i32 117, i64 0, metadata !12, metadata !{!"0x102"}), !dbg !24
+  tail call void @llvm.dbg.value(metadata i32 117, i64 0, metadata !12, metadata !DIExpression()), !dbg !24
   tail call void @_Z4funcj(i32 117), !dbg !25
-  tail call void @llvm.dbg.value(metadata i16 7, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !27
+  tail call void @llvm.dbg.value(metadata i16 7, i64 0, metadata !15, metadata !DIExpression()), !dbg !27
   tail call void @_Z4funcDs(i16 zeroext 7), !dbg !28
   ret i32 0, !dbg !29
 }
@@ -50,33 +50,33 @@ attributes #2 = { nounwind readnone }
 !llvm.module.flags = !{!17, !18}
 !llvm.ident = !{!19}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/const.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"const.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "const.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00main\00main\00\004\000\001\000\006\00256\001\004", !1, !5, !6, null, i32 ()* @main, null, null, !9} ; [ DW_TAG_subprogram ] [line 4] [def] [main]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/const.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "main", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 4, file: !1, scope: !5, type: !6, function: i32 ()* @main, variables: !9)
+!5 = !DIFile(filename: "const.cpp", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{!10, !12, !15}
-!10 = !{!"0x100\00i\005\000", !4, !5, !11} ; [ DW_TAG_auto_variable ] [i] [line 5]
-!11 = !{!"0x26\00\000\000\000\000\000", null, null, !8} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from int]
-!12 = !{!"0x100\00j\007\000", !4, !5, !13} ; [ DW_TAG_auto_variable ] [j] [line 7]
-!13 = !{!"0x26\00\000\000\000\000\000", null, null, !14} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from unsigned int]
-!14 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, null} ; [ DW_TAG_base_type ] [unsigned int] [line 0, size 32, align 32, offset 0, enc DW_ATE_unsigned]
-!15 = !{!"0x100\00c\009\000", !4, !5, !16} ; [ DW_TAG_auto_variable ] [c] [line 9]
-!16 = !{!"0x24\00char16_t\000\0016\0016\000\000\0016", null, null} ; [ DW_TAG_base_type ] [char16_t] [line 0, size 16, align 16, offset 0, enc DW_ATE_UTF]
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 5, scope: !4, file: !5, type: !11)
+!11 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !8)
+!12 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 7, scope: !4, file: !5, type: !13)
+!13 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !14)
+!14 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "c", line: 9, scope: !4, file: !5, type: !16)
+!16 = !DIBasicType(tag: DW_TAG_base_type, name: "char16_t", size: 16, align: 16, encoding: 16)
 !17 = !{i32 2, !"Dwarf Version", i32 4}
-!18 = !{i32 1, !"Debug Info Version", i32 2}
+!18 = !{i32 1, !"Debug Info Version", i32 3}
 !19 = !{!"clang version 3.5.0 "}
 !20 = !{i32 42}
-!21 = !MDLocation(line: 5, scope: !4)
-!22 = !MDLocation(line: 6, scope: !4)
+!21 = !DILocation(line: 5, scope: !4)
+!22 = !DILocation(line: 6, scope: !4)
 !23 = !{i32 117}
-!24 = !MDLocation(line: 7, scope: !4)
-!25 = !MDLocation(line: 8, scope: !4)
+!24 = !DILocation(line: 7, scope: !4)
+!25 = !DILocation(line: 8, scope: !4)
 !26 = !{i16 7}
-!27 = !MDLocation(line: 9, scope: !4)
-!28 = !MDLocation(line: 10, scope: !4)
-!29 = !MDLocation(line: 11, scope: !4)
+!27 = !DILocation(line: 9, scope: !4)
+!28 = !DILocation(line: 10, scope: !4)
+!29 = !DILocation(line: 11, scope: !4)
diff --git a/test/DebugInfo/template-recursive-void.ll b/test/DebugInfo/template-recursive-void.ll
index b7e72445cd7f..30eaee3f75d3 100644
--- a/test/DebugInfo/template-recursive-void.ll
+++ b/test/DebugInfo/template-recursive-void.ll
@@ -25,41 +25,37 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!36, !37}
 
-!0 = !{!"0x11\004\00clang version 3.4 (trunk 187958) (llvm/trunk 187964)\000\00\000\00\000", !1, !2, !2, !2, !3, !2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/debug-info-template-recursive.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"debug-info-template-recursive.cpp", !"/usr/local/google/home/echristo/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 (trunk 187958) (llvm/trunk 187964)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3, imports: !2)
+!1 = !DIFile(filename: "debug-info-template-recursive.cpp", directory: "/usr/local/google/home/echristo/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x34\00filters\00filters\00\0010\000\001", null, !5, !6, %class.bar* @filters, null} ; [ DW_TAG_variable ] [filters] [line 10] [def]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/usr/local/google/home/echristo/tmp/debug-info-template-recursive.cpp]
-!6 = !{!"0x2\00bar\009\008\008\000\000\000", !1, null, null, !7, null, null, null} ; [ DW_TAG_class_type ] [bar] [line 9, size 8, align 8, offset 0] [def] [from ]
+!4 = !DIGlobalVariable(name: "filters", line: 10, isLocal: false, isDefinition: true, scope: null, file: !5, type: !6, variable: %class.bar* @filters)
+!5 = !DIFile(filename: "debug-info-template-recursive.cpp", directory: "/usr/local/google/home/echristo/tmp")
+!6 = !DICompositeType(tag: DW_TAG_class_type, name: "bar", line: 9, size: 8, align: 8, file: !1, elements: !7)
 !7 = !{!8, !31}
-!8 = !{!"0x1c\00\000\000\000\000\000", null, !6, !9} ; [ DW_TAG_inheritance ] [line 0, size 0, align 0, offset 0] [from foo<void>]
-!9 = !{!"0x2\00foo<void>\005\008\008\000\000\000", !1, null, null, !10, null, !29, null} ; [ DW_TAG_class_type ] [foo<void>] [line 5, size 8, align 8, offset 0] [def] [from ]
+!8 = !DIDerivedType(tag: DW_TAG_inheritance, scope: !6, baseType: !9)
+!9 = !DICompositeType(tag: DW_TAG_class_type, name: "foo<void>", line: 5, size: 8, align: 8, file: !1, elements: !10, templateParams: !29)
 !10 = !{!11, !19, !25}
-!11 = !{!"0x1c\00\000\000\000\000\000", null, !9, !12} ; [ DW_TAG_inheritance ] [line 0, size 0, align 0, offset 0] [from base]
-!12 = !{!"0x2\00base\003\008\008\000\000\000", !1, null, null, !13, null, null, null} ; [ DW_TAG_class_type ] [base] [line 3, size 8, align 8, offset 0] [def] [from ]
+!11 = !DIDerivedType(tag: DW_TAG_inheritance, scope: !9, baseType: !12)
+!12 = !DICompositeType(tag: DW_TAG_class_type, name: "base", line: 3, size: 8, align: 8, file: !1, elements: !13)
 !13 = !{!14}
-!14 = !{!"0x2e\00base\00base\00\003\000\000\000\006\00320\000\003", !1, !12, !15, null, null, null, i32 0, !18} ; [ DW_TAG_subprogram ] [line 3] [base]
-!15 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!14 = !DISubprogram(name: "base", line: 3, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !12, type: !15)
+!15 = !DISubroutineType(types: !16)
 !16 = !{null, !17}
-!17 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !12} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from base]
-!18 = !{i32 786468}
-!19 = !{!"0x2e\00operator=\00operator=\00_ZN3fooIvEaSES0_\006\000\000\000\006\00257\000\006", !1, !9, !20, null, null, null, i32 0, !24} ; [ DW_TAG_subprogram ] [line 6] [private] [operator=]
-!20 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !21, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !12)
+!19 = !DISubprogram(name: "operator=", linkageName: "_ZN3fooIvEaSES0_", line: 6, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrivate | DIFlagPrototyped, isOptimized: false, scopeLine: 6, file: !1, scope: !9, type: !20)
+!20 = !DISubroutineType(types: !21)
 !21 = !{null, !22, !23}
-!22 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from foo<void>]
-!23 = !{!"0x26\00\000\000\000\000\000", null, null, !9} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from foo<void>]
-!24 = !{i32 786468}
-!25 = !{!"0x2e\00foo\00foo\00\005\000\000\000\006\00320\000\005", !1, !9, !26, null, null, null, i32 0, !28} ; [ DW_TAG_subprogram ] [line 5] [foo]
-!26 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !27, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!22 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !9)
+!23 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !9)
+!25 = !DISubprogram(name: "foo", line: 5, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !9, type: !26)
+!26 = !DISubroutineType(types: !27)
 !27 = !{null, !22}
-!28 = !{i32 786468}
 !29 = !{!30}
-!30 = !{!"0x2f\00T\000\000", null, null, null} ; [ DW_TAG_template_type_parameter ]
-!31 = !{!"0x2e\00bar\00bar\00\009\000\000\000\006\00320\000\009", !1, !6, !32, null, null, null, i32 0, !35} ; [ DW_TAG_subprogram ] [line 9] [bar]
-!32 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !33, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!30 = !DITemplateTypeParameter(name: "T", type: null)
+!31 = !DISubprogram(name: "bar", line: 9, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 9, file: !1, scope: !6, type: !32)
+!32 = !DISubroutineType(types: !33)
 !33 = !{null, !34}
-!34 = !{!"0xf\00\000\0064\0064\000\001088", i32 0, null, !6} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from bar]
-!35 = !{i32 786468}
+!34 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !6)
 !36 = !{i32 2, !"Dwarf Version", i32 3}
-!37 = !{i32 1, !"Debug Info Version", i32 2}
+!37 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/tu-composite.ll b/test/DebugInfo/tu-composite.ll
index 6f052ee2a82d..47fb8bc31482 100644
--- a/test/DebugInfo/tu-composite.ll
+++ b/test/DebugInfo/tu-composite.ll
@@ -84,15 +84,15 @@
 @_ZTV1C = unnamed_addr constant [3 x i8*] [i8* null, i8* bitcast ({ i8*, i8* }* @_ZTI1C to i8*), i8* bitcast (void (%struct.C*)* @_ZN1C3fooEv to i8*)]
 @_ZTVN10__cxxabiv117__class_type_infoE = external global i8*
 @_ZTS1C = constant [3 x i8] c"1C\00"
-@_ZTI1C = unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8]* @_ZTS1C, i32 0, i32 0) }
+@_ZTI1C = unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @_ZTS1C, i32 0, i32 0) }
 
 ; Function Attrs: nounwind ssp uwtable
 define void @_ZN1C3fooEv(%struct.C* %this) unnamed_addr #0 align 2 {
 entry:
   %this.addr = alloca %struct.C*, align 8
   store %struct.C* %this, %struct.C** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %struct.C** %this.addr, metadata !36, metadata !{!"0x102"}), !dbg !38
-  %this1 = load %struct.C** %this.addr
+  call void @llvm.dbg.declare(metadata %struct.C** %this.addr, metadata !36, metadata !DIExpression()), !dbg !38
+  %this1 = load %struct.C*, %struct.C** %this.addr
   ret void, !dbg !39
 }
 
@@ -108,12 +108,12 @@ entry:
   %e = alloca %"struct.D::Nested", align 1
   %p = alloca %"struct.D::Nested2"*, align 8
   %t = alloca %"struct.D::virt", align 8
-  call void @llvm.dbg.declare(metadata %struct.bar* %B, metadata !40, metadata !{!"0x102"}), !dbg !42
-  call void @llvm.dbg.declare(metadata [3 x %struct.bar]* %A, metadata !43, metadata !{!"0x102"}), !dbg !47
-  call void @llvm.dbg.declare(metadata %struct.bar* %B2, metadata !48, metadata !{!"0x102"}), !dbg !50
-  call void @llvm.dbg.declare(metadata %"struct.D::Nested"* %e, metadata !51, metadata !{!"0x102"}), !dbg !52
-  call void @llvm.dbg.declare(metadata %"struct.D::Nested2"** %p, metadata !53, metadata !{!"0x102"}), !dbg !55
-  call void @llvm.dbg.declare(metadata %"struct.D::virt"* %t, metadata !56, metadata !{!"0x102"}), !dbg !57
+  call void @llvm.dbg.declare(metadata %struct.bar* %B, metadata !40, metadata !DIExpression()), !dbg !42
+  call void @llvm.dbg.declare(metadata [3 x %struct.bar]* %A, metadata !43, metadata !DIExpression()), !dbg !47
+  call void @llvm.dbg.declare(metadata %struct.bar* %B2, metadata !48, metadata !DIExpression()), !dbg !50
+  call void @llvm.dbg.declare(metadata %"struct.D::Nested"* %e, metadata !51, metadata !DIExpression()), !dbg !52
+  call void @llvm.dbg.declare(metadata %"struct.D::Nested2"** %p, metadata !53, metadata !DIExpression()), !dbg !55
+  call void @llvm.dbg.declare(metadata %"struct.D::virt"* %t, metadata !56, metadata !DIExpression()), !dbg !57
   ret void, !dbg !58
 }
 
@@ -123,63 +123,62 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!35, !59}
 
-!0 = !{!"0x11\004\00clang version 3.4\000\00\000\00\000", !1, !2, !3, !30, !2, !2} ; [ DW_TAG_compile_unit ] [tmp.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"tmp.cpp", !"."}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !30, globals: !2, imports: !2)
+!1 = !DIFile(filename: "tmp.cpp", directory: ".")
 !2 = !{}
 !3 = !{!4, !18, !19, !22, !23, !24}
-!4 = !{!"0x13\00C\001\0064\0064\000\000\000", !1, null, null, !5, !"_ZTS1C", null, !"_ZTS1C"} ; [ DW_TAG_structure_type ] [C] [line 1, size 64, align 64, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "C", line: 1, size: 64, align: 64, file: !1, elements: !5, vtableHolder: !"_ZTS1C", identifier: "_ZTS1C")
 !5 = !{!6, !13}
-!6 = !{!"0xd\00_vptr$C\000\0064\000\000\0064", !1, !7, !8} ; [ DW_TAG_member ] [_vptr$C] [line 0, size 64, align 0, offset 0] [artificial] [from ]
-!7 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [tmp.cpp]
-!8 = !{!"0xf\00\000\0064\000\000\000", null, null, !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from __vtbl_ptr_type]
-!9 = !{!"0xf\00__vtbl_ptr_type\000\0064\000\000\000", null, null, !10} ; [ DW_TAG_pointer_type ] [__vtbl_ptr_type] [line 0, size 64, align 0, offset 0] [from ]
-!10 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DIDerivedType(tag: DW_TAG_member, name: "_vptr$C", size: 64, flags: DIFlagArtificial, file: !1, scope: !7, baseType: !8)
+!7 = !DIFile(filename: "tmp.cpp", directory: ".")
+!8 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, baseType: !9)
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "__vtbl_ptr_type", size: 64, baseType: !10)
+!10 = !DISubroutineType(types: !11)
 !11 = !{!12}
-!12 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!13 = !{!"0x2e\00foo\00foo\00_ZN1C3fooEv\002\000\000\001\006\00256\000\002", !1, !"_ZTS1C", !14, !"_ZTS1C", null, null, i32 0, !17} ; [ DW_TAG_subprogram ] [line 2] [foo]
-!14 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !15, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!13 = !DISubprogram(name: "foo", linkageName: "_ZN1C3fooEv", line: 2, isLocal: false, isDefinition: false, virtuality: DW_VIRTUALITY_virtual, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !"_ZTS1C", type: !14, containingType: !"_ZTS1C")
+!14 = !DISubroutineType(types: !15)
 !15 = !{null, !16}
-!16 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1C"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1C]
-!17 = !{i32 786468}
-!18 = !{!"0x13\00bar\007\008\008\000\000\000", !1, null, null, !2, null, null, !"_ZTS3bar"} ; [ DW_TAG_structure_type ] [bar] [line 7, size 8, align 8, offset 0] [def] [from ]
-!19 = !{!"0x13\00D\009\008\008\000\000\000", !1, null, null, !20, null, null, !"_ZTS1D"} ; [ DW_TAG_structure_type ] [D] [line 9, size 8, align 8, offset 0] [def] [from ]
+!16 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1C")
+!18 = !DICompositeType(tag: DW_TAG_structure_type, name: "bar", line: 7, size: 8, align: 8, file: !1, elements: !2, identifier: "_ZTS3bar")
+!19 = !DICompositeType(tag: DW_TAG_structure_type, name: "D", line: 9, size: 8, align: 8, file: !1, elements: !20, identifier: "_ZTS1D")
 !20 = !{!21}
-!21 = !{!"0xd\00a\0011\000\000\000\004096", !1, !"_ZTS1D", !12, null} ; [ DW_TAG_member ] [a] [line 11, size 0, align 0, offset 0] [static] [from int]
-!22 = !{!"0x13\00Nested\0012\008\008\000\000\000", !1, !"_ZTS1D", null, !2, null, null, !"_ZTSN1D6NestedE"} ; [ DW_TAG_structure_type ] [Nested] [line 12, size 8, align 8, offset 0] [def] [from ]
-!23 = !{!"0x13\00Nested2\0013\000\000\000\004\000", !1, !"_ZTS1D", null, null, null, null, !"_ZTSN1D7Nested2E"} ; [ DW_TAG_structure_type ] [Nested2] [line 13, size 0, align 0, offset 0] [decl] [from ]
-!24 = !{!"0x13\00virt<bar>\0015\0064\0064\000\000\000", !1, !"_ZTS1D", null, !25, null, !28, !"_ZTSN1D4virtI3barEE"} ; [ DW_TAG_structure_type ] [virt<bar>] [line 15, size 64, align 64, offset 0] [def] [from ]
+!21 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 11, flags: DIFlagStaticMember, file: !1, scope: !"_ZTS1D", baseType: !12)
+!22 = !DICompositeType(tag: DW_TAG_structure_type, name: "Nested", line: 12, size: 8, align: 8, file: !1, scope: !"_ZTS1D", elements: !2, identifier: "_ZTSN1D6NestedE")
+!23 = !DICompositeType(tag: DW_TAG_structure_type, name: "Nested2", line: 13, flags: DIFlagFwdDecl, file: !1, scope: !"_ZTS1D", identifier: "_ZTSN1D7Nested2E")
+!24 = !DICompositeType(tag: DW_TAG_structure_type, name: "virt<bar>", line: 15, size: 64, align: 64, file: !1, scope: !"_ZTS1D", elements: !25, templateParams: !28, identifier: "_ZTSN1D4virtI3barEE")
 !25 = !{!26}
-!26 = !{!"0xd\00values\0016\0064\0064\000\000", !1, !"_ZTSN1D4virtI3barEE", !27} ; [ DW_TAG_member ] [values] [line 16, size 64, align 64, offset 0] [from ]
-!27 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS3bar"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS3bar]
+!26 = !DIDerivedType(tag: DW_TAG_member, name: "values", line: 16, size: 64, align: 64, file: !1, scope: !"_ZTSN1D4virtI3barEE", baseType: !27)
+!27 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS3bar")
 !28 = !{!29}
-!29 = !{!"0x2f\00T\000\000", null, !"_ZTS3bar", null} ; [ DW_TAG_template_type_parameter ]
+!29 = !DITemplateTypeParameter(name: "T", type: !"_ZTS3bar")
 !30 = !{!31, !32}
-!31 = !{!"0x2e\00foo\00foo\00_ZN1C3fooEv\004\000\001\000\006\00256\000\004", !1, null, !14, null, void (%struct.C*)* @_ZN1C3fooEv, null, !13, !2} ; [ DW_TAG_subprogram ] [line 4] [def] [foo]
-!32 = !{!"0x2e\00test\00test\00_Z4testv\0020\000\001\000\006\00256\000\0020", !1, !7, !33, null, void ()* @_Z4testv, null, null, !2} ; [ DW_TAG_subprogram ] [line 20] [def] [test]
-!33 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !34, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!31 = !DISubprogram(name: "foo", linkageName: "_ZN1C3fooEv", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !1, scope: null, type: !14, function: void (%struct.C*)* @_ZN1C3fooEv, declaration: !13, variables: !2)
+!32 = !DISubprogram(name: "test", linkageName: "_Z4testv", line: 20, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 20, file: !1, scope: !7, type: !33, function: void ()* @_Z4testv, variables: !2)
+!33 = !DISubroutineType(types: !34)
 !34 = !{null}
 !35 = !{i32 2, !"Dwarf Version", i32 2}
-!36 = !{!"0x101\00this\0016777216\001088", !31, null, !37} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!37 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1C"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1C]
-!38 = !MDLocation(line: 0, scope: !31)
-!39 = !MDLocation(line: 5, scope: !31)
-!40 = !{!"0x100\00B\0021\000", !32, !7, !41} ; [ DW_TAG_auto_variable ] [B] [line 21]
-!41 = !{!"0x16\00baz\008\000\000\000\000", !1, null, !"_ZTS3bar"} ; [ DW_TAG_typedef ] [baz] [line 8, size 0, align 0, offset 0] [from _ZTS3bar]
-!42 = !MDLocation(line: 21, scope: !32)
-!43 = !{!"0x100\00A\0022\000", !32, !7, !44} ; [ DW_TAG_auto_variable ] [A] [line 22]
-!44 = !{!"0x1\00\000\0024\008\000\000", null, null, !"_ZTS3bar", !45, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 24, align 8, offset 0] [from _ZTS3bar]
+!36 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !31, type: !37)
+!37 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1C")
+!38 = !DILocation(line: 0, scope: !31)
+!39 = !DILocation(line: 5, scope: !31)
+!40 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "B", line: 21, scope: !32, file: !7, type: !41)
+!41 = !DIDerivedType(tag: DW_TAG_typedef, name: "baz", line: 8, file: !1, baseType: !"_ZTS3bar")
+!42 = !DILocation(line: 21, scope: !32)
+!43 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "A", line: 22, scope: !32, file: !7, type: !44)
+!44 = !DICompositeType(tag: DW_TAG_array_type, size: 24, align: 8, baseType: !"_ZTS3bar", elements: !45)
 !45 = !{!46}
-!46 = !{!"0x21\000\003"}        ; [ DW_TAG_subrange_type ] [0, 2]
-!47 = !MDLocation(line: 22, scope: !32)
-!48 = !{!"0x100\00B2\0023\000", !32, !7, !49} ; [ DW_TAG_auto_variable ] [B2] [line 23]
-!49 = !{!"0x16\00baz2\0010\000\000\000\000", !1, !"_ZTS1D", !"_ZTS3bar"} ; [ DW_TAG_typedef ] [baz2] [line 10, size 0, align 0, offset 0] [from _ZTS3bar]
-!50 = !MDLocation(line: 23, scope: !32)
-!51 = !{!"0x100\00e\0024\000", !32, !7, !22} ; [ DW_TAG_auto_variable ] [e] [line 24]
-!52 = !MDLocation(line: 24, scope: !32)
-!53 = !{!"0x100\00p\0025\000", !32, !7, !54} ; [ DW_TAG_auto_variable ] [p] [line 25]
-!54 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTSN1D7Nested2E"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTSN1D7Nested2E]
-!55 = !MDLocation(line: 25, scope: !32)
-!56 = !{!"0x100\00t\0026\000", !32, !7, !24} ; [ DW_TAG_auto_variable ] [t] [line 26]
-!57 = !MDLocation(line: 26, scope: !32)
-!58 = !MDLocation(line: 27, scope: !32)
-!59 = !{i32 1, !"Debug Info Version", i32 2}
+!46 = !DISubrange(count: 3)
+!47 = !DILocation(line: 22, scope: !32)
+!48 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "B2", line: 23, scope: !32, file: !7, type: !49)
+!49 = !DIDerivedType(tag: DW_TAG_typedef, name: "baz2", line: 10, file: !1, scope: !"_ZTS1D", baseType: !"_ZTS3bar")
+!50 = !DILocation(line: 23, scope: !32)
+!51 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "e", line: 24, scope: !32, file: !7, type: !22)
+!52 = !DILocation(line: 24, scope: !32)
+!53 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "p", line: 25, scope: !32, file: !7, type: !54)
+!54 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTSN1D7Nested2E")
+!55 = !DILocation(line: 25, scope: !32)
+!56 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "t", line: 26, scope: !32, file: !7, type: !24)
+!57 = !DILocation(line: 26, scope: !32)
+!58 = !DILocation(line: 27, scope: !32)
+!59 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/tu-member-pointer.ll b/test/DebugInfo/tu-member-pointer.ll
index 0e4b15a6ce16..a46c41313cf5 100644
--- a/test/DebugInfo/tu-member-pointer.ll
+++ b/test/DebugInfo/tu-member-pointer.ll
@@ -16,15 +16,15 @@
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!10, !11}
 
-!0 = !{!"0x11\004\00clang version 3.4\000\00\000\00\000", !1, !2, !3, !2, !5, !2} ; [ DW_TAG_compile_unit ] [foo.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"foo.cpp", !"."}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !2, globals: !5, imports: !2)
+!1 = !DIFile(filename: "foo.cpp", directory: ".")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00Foo\001\000\000\000\004\000", !1, null, null, null, null, null, !"_ZTS3Foo"} ; [ DW_TAG_structure_type ] [Foo] [line 1, size 0, align 0, offset 0] [decl] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "Foo", line: 1, flags: DIFlagFwdDecl, file: !1, identifier: "_ZTS3Foo")
 !5 = !{!6}
-!6 = !{!"0x34\00x\00x\00\004\000\001", null, !7, !8, i64* @x, null} ; [ DW_TAG_variable ] [x] [line 4] [def]
-!7 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [foo.cpp]
-!8 = !{!"0x1f\00\000\000\000\000\000", null, null, !9, !"_ZTS3Foo"} ; [ DW_TAG_ptr_to_member_type ] [line 0, size 0, align 0, offset 0] [from int]
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!6 = !DIGlobalVariable(name: "x", line: 4, isLocal: false, isDefinition: true, scope: null, file: !7, type: !8, variable: i64* @x)
+!7 = !DIFile(filename: "foo.cpp", directory: ".")
+!8 = !DIDerivedType(tag: DW_TAG_ptr_to_member_type, baseType: !9, extraData: !"_ZTS3Foo")
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !10 = !{i32 2, !"Dwarf Version", i32 2}
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!11 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/two-cus-from-same-file.ll b/test/DebugInfo/two-cus-from-same-file.ll
index b810a914960e..9dbd64a3fb92 100644
--- a/test/DebugInfo/two-cus-from-same-file.ll
+++ b/test/DebugInfo/two-cus-from-same-file.ll
@@ -15,7 +15,7 @@
 
 define void @foo() nounwind {
 entry:
-  %puts = tail call i32 @puts(i8* getelementptr inbounds ([4 x i8]* @str, i32 0, i32 0)), !dbg !23
+  %puts = tail call i32 @puts(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @str, i32 0, i32 0)), !dbg !23
   ret void, !dbg !25
 }
 
@@ -23,9 +23,9 @@ declare i32 @puts(i8* nocapture) nounwind
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !21, metadata !{!"0x102"}), !dbg !26
-  tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !22, metadata !{!"0x102"}), !dbg !27
-  %puts = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @str1, i32 0, i32 0)), !dbg !28
+  tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !21, metadata !DIExpression()), !dbg !26
+  tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !22, metadata !DIExpression()), !dbg !27
+  %puts = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @str1, i32 0, i32 0)), !dbg !28
   tail call void @foo() nounwind, !dbg !30
   ret i32 0, !dbg !31
 }
@@ -35,39 +35,39 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0, !9}
 !llvm.module.flags = !{!33}
 
-!0 = !{!"0x11\0012\00clang version 3.2 (trunk 156513)\001\00\000\00\001", !32, !1, !1, !3, !1, !1} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.2 (trunk 156513)", isOptimized: true, emissionKind: 1, file: !32, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports: !1)
 !1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00foo\00foo\00\005\000\001\000\006\00256\001\005", !32, !6, !7, null, void ()* @foo, null, null, !1} ; [ DW_TAG_subprogram ]
-!6 = !{!"0x29", !32} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "foo", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !32, scope: !6, type: !7, function: void ()* @foo, variables: !1)
+!6 = !DIFile(filename: "foo.c", directory: "/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null}
-!9 = !{!"0x11\0012\00clang version 3.2 (trunk 156513)\001\00\000\00\001", !32, !1, !1, !10, !1, !1} ; [ DW_TAG_compile_unit ]
+!9 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.2 (trunk 156513)", isOptimized: true, emissionKind: 1, file: !32, enums: !1, retainedTypes: !1, subprograms: !10, globals: !1, imports: !1)
 !10 = !{!12}
-!12 = !{!"0x2e\00main\00main\00\0011\000\001\000\006\00256\001\0011", !32, !6, !13, null, i32 (i32, i8**)* @main, null, null, !19} ; [ DW_TAG_subprogram ]
-!13 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !14, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = !DISubprogram(name: "main", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !32, scope: !6, type: !13, function: i32 (i32, i8**)* @main, variables: !19)
+!13 = !DISubroutineType(types: !14)
 !14 = !{!15, !15, !16}
-!15 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!16 = !{!"0xf\00\000\0032\0032\000\000", null, null, !17} ; [ DW_TAG_pointer_type ]
-!17 = !{!"0xf\00\000\0032\0032\000\000", null, null, !18} ; [ DW_TAG_pointer_type ]
-!18 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ]
+!15 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!16 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !17)
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !18)
+!18 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
 !19 = !{!21, !22}
-!21 = !{!"0x101\00argc\0016777227\000", !12, !6, !15} ; [ DW_TAG_arg_variable ]
-!22 = !{!"0x101\00argv\0033554443\000", !12, !6, !16} ; [ DW_TAG_arg_variable ]
-!23 = !MDLocation(line: 6, column: 3, scope: !24)
-!24 = !{!"0xb\005\0016\000", !32, !5} ; [ DW_TAG_lexical_block ]
-!25 = !MDLocation(line: 7, column: 1, scope: !24)
-!26 = !MDLocation(line: 11, column: 14, scope: !12)
-!27 = !MDLocation(line: 11, column: 26, scope: !12)
-!28 = !MDLocation(line: 12, column: 3, scope: !29)
-!29 = !{!"0xb\0011\0034\000", !32, !12} ; [ DW_TAG_lexical_block ]
-!30 = !MDLocation(line: 13, column: 3, scope: !29)
-!31 = !MDLocation(line: 14, column: 3, scope: !29)
-!32 = !{!"foo.c", !"/tmp"}
+!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 11, arg: 1, scope: !12, file: !6, type: !15)
+!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 11, arg: 2, scope: !12, file: !6, type: !16)
+!23 = !DILocation(line: 6, column: 3, scope: !24)
+!24 = distinct !DILexicalBlock(line: 5, column: 16, file: !32, scope: !5)
+!25 = !DILocation(line: 7, column: 1, scope: !24)
+!26 = !DILocation(line: 11, column: 14, scope: !12)
+!27 = !DILocation(line: 11, column: 26, scope: !12)
+!28 = !DILocation(line: 12, column: 3, scope: !29)
+!29 = distinct !DILexicalBlock(line: 11, column: 34, file: !32, scope: !12)
+!30 = !DILocation(line: 13, column: 3, scope: !29)
+!31 = !DILocation(line: 14, column: 3, scope: !29)
+!32 = !DIFile(filename: "foo.c", directory: "/tmp")
 
 ; This test is simple to be cross platform (many targets don't yet have
 ; sufficiently good DWARF emission and/or dumping)
 ; CHECK: {{DW_TAG_compile_unit}}
 ; CHECK: {{foo\.c}}
 
-!33 = !{i32 1, !"Debug Info Version", i32 2}
+!33 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/DebugInfo/typedef.ll b/test/DebugInfo/typedef.ll
index b8528be07bd1..591995e9b256 100644
--- a/test/DebugInfo/typedef.ll
+++ b/test/DebugInfo/typedef.ll
@@ -18,15 +18,15 @@
 !llvm.module.flags = !{!8, !9}
 !llvm.ident = !{!10}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !2, !3, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/typedef.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"typedef.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3, imports: !2)
+!1 = !DIFile(filename: "typedef.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x34\00y\00y\00\002\000\001", null, !5, !6, i8** @y, null} ; [ DW_TAG_variable ] [y] [line 2] [def]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/dbginfo/typedef.cpp]
-!6 = !{!"0xf\00\000\0064\0064\000\000", null, null, !7} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from x]
-!7 = !{!"0x16\00x\001\000\000\000\000", !1, null, null} ; [ DW_TAG_typedef ] [x] [line 1, size 0, align 0, offset 0] [from ]
+!4 = !DIGlobalVariable(name: "y", line: 2, isLocal: false, isDefinition: true, scope: null, file: !5, type: !6, variable: i8** @y)
+!5 = !DIFile(filename: "typedef.cpp", directory: "/tmp/dbginfo")
+!6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !7)
+!7 = !DIDerivedType(tag: DW_TAG_typedef, name: "x", line: 1, file: !1, baseType: null)
 !8 = !{i32 2, !"Dwarf Version", i32 4}
-!9 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !{i32 1, !"Debug Info Version", i32 3}
 !10 = !{!"clang version 3.5.0 "}
 
diff --git a/test/DebugInfo/unconditional-branch.ll b/test/DebugInfo/unconditional-branch.ll
index c82f1bab10b3..220a0e3dbe30 100644
--- a/test/DebugInfo/unconditional-branch.ll
+++ b/test/DebugInfo/unconditional-branch.ll
@@ -22,8 +22,8 @@ define void @foo(i32 %i) #0 {
 entry:
   %i.addr = alloca i32, align 4
   store i32 %i, i32* %i.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %i.addr, metadata !12, metadata !{!"0x102"}), !dbg !13
-  %0 = load i32* %i.addr, align 4, !dbg !14
+  call void @llvm.dbg.declare(metadata i32* %i.addr, metadata !12, metadata !DIExpression()), !dbg !13
+  %0 = load i32, i32* %i.addr, align 4, !dbg !14
   switch i32 %0, label %sw.default [
   ], !dbg !14
 
@@ -45,21 +45,21 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!9, !10}
 !llvm.ident = !{!11}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 (204712)\000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [D:\work\EPRs\396363/test.c] [DW_LANG_C99]
-!1 = !{!"test.c", !"D:\5Cwork\5CEPRs\5C396363"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 (204712)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.c", directory: "D:\5Cwork\5CEPRs\5C396363")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, void (i32)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [D:\work\EPRs\396363/test.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void (i32)* @foo, variables: !2)
+!5 = !DIFile(filename: "test.c", directory: "D:CworkCEPRsC396363")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 4}
-!10 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !{i32 1, !"Debug Info Version", i32 3}
 !11 = !{!"clang version 3.5.0 (204712)"}
-!12 = !{!"0x101\00i\0016777217\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [i] [line 1]
-!13 = !MDLocation(line: 1, scope: !4)
-!14 = !MDLocation(line: 2, scope: !4)
-!15 = !MDLocation(line: 4, scope: !16)
-!16 = !{!"0xb\002\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [D:\work\EPRs\396363/test.c]
-!17 = !MDLocation(line: 6, scope: !4)
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 1, arg: 1, scope: !4, file: !5, type: !8)
+!13 = !DILocation(line: 1, scope: !4)
+!14 = !DILocation(line: 2, scope: !4)
+!15 = !DILocation(line: 4, scope: !16)
+!16 = distinct !DILexicalBlock(line: 2, column: 0, file: !1, scope: !4)
+!17 = !DILocation(line: 6, scope: !4)
diff --git a/test/DebugInfo/varargs.ll b/test/DebugInfo/varargs.ll
index 907d2e309a5e..93dbfa1e0ace 100644
--- a/test/DebugInfo/varargs.ll
+++ b/test/DebugInfo/varargs.ll
@@ -55,9 +55,9 @@ define void @_Z1biz(i32 %c, ...) #0 {
   %a = alloca %struct.A, align 1
   %fptr = alloca void (i32, ...)*, align 8
   store i32 %c, i32* %1, align 4
-  call void @llvm.dbg.declare(metadata i32* %1, metadata !21, metadata !{!"0x102"}), !dbg !22
-  call void @llvm.dbg.declare(metadata %struct.A* %a, metadata !23, metadata !{!"0x102"}), !dbg !24
-  call void @llvm.dbg.declare(metadata void (i32, ...)** %fptr, metadata !25, metadata !{!"0x102"}), !dbg !27
+  call void @llvm.dbg.declare(metadata i32* %1, metadata !21, metadata !DIExpression()), !dbg !22
+  call void @llvm.dbg.declare(metadata %struct.A* %a, metadata !23, metadata !DIExpression()), !dbg !24
+  call void @llvm.dbg.declare(metadata void (i32, ...)** %fptr, metadata !25, metadata !DIExpression()), !dbg !27
   store void (i32, ...)* @_Z1biz, void (i32, ...)** %fptr, align 8, !dbg !27
   ret void, !dbg !28
 }
@@ -72,31 +72,30 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!18, !19}
 !llvm.ident = !{!20}
 
-!0 = !{!"0x11\004\00clang version 3.5 \000\00\000\00\000", !1, !2, !3, !13, !2, !2} ; [ DW_TAG_compile_unit ] [llvm/tools/clang/test/CodeGenCXX/debug-info-varargs.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"llvm/tools/clang/test/CodeGenCXX/debug-info-varargs.cpp", !"radar/13690847"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !13, globals: !2, imports: !2)
+!1 = !DIFile(filename: "llvm/tools/clang/test/CodeGenCXX/debug-info-varargs.cpp", directory: "radar/13690847")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00A\003\008\008\000\000\000", !1, null, null, !5, null, null, !"_ZTS1A"} ; [ DW_TAG_structure_type ] [A] [line 3, size 8, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "A", line: 3, size: 8, align: 8, file: !1, elements: !5, identifier: "_ZTS1A")
 !5 = !{!6}
-!6 = !{!"0x2e\00a\00a\00_ZN1A1aEiz\006\000\000\000\006\00256\000\006", !1, !"_ZTS1A", !7, null, null, null, i32 0, !12} ; [ DW_TAG_subprogram ] [line 6] [a]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DISubprogram(name: "a", linkageName: "_ZN1A1aEiz", line: 6, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 6, file: !1, scope: !"_ZTS1A", type: !7)
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9, !10, null}
-!9 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1A]
-!10 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!12 = !{i32 786468}
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1A")
+!10 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !13 = !{!14}
-!14 = !{!"0x2e\00b\00b\00_Z1biz\0013\000\001\000\006\00256\000\0013", !1, !15, !16, null, void (i32, ...)* @_Z1biz, null, null, !2} ; [ DW_TAG_subprogram ] [line 13] [def] [b]
-!15 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [llvm/tools/clang/test/CodeGenCXX/debug-info-varargs.cpp]
-!16 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !17, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!14 = !DISubprogram(name: "b", linkageName: "_Z1biz", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 13, file: !1, scope: !15, type: !16, function: void (i32, ...)* @_Z1biz, variables: !2)
+!15 = !DIFile(filename: "llvm/tools/clang/test/CodeGenCXX/debug-info-varargs.cpp", directory: "radar/13690847")
+!16 = !DISubroutineType(types: !17)
 !17 = !{null, !10, null}
 !18 = !{i32 2, !"Dwarf Version", i32 2}
-!19 = !{i32 1, !"Debug Info Version", i32 2}
+!19 = !{i32 1, !"Debug Info Version", i32 3}
 !20 = !{!"clang version 3.5 "}
-!21 = !{!"0x101\00c\0016777229\000", !14, !15, !10} ; [ DW_TAG_arg_variable ] [c] [line 13]
-!22 = !MDLocation(line: 13, scope: !14)
-!23 = !{!"0x100\00a\0016\000", !14, !15, !4} ; [ DW_TAG_auto_variable ] [a] [line 16]
-!24 = !MDLocation(line: 16, scope: !14)
-!25 = !{!"0x100\00fptr\0018\000", !14, !15, !26} ; [ DW_TAG_auto_variable ] [fptr] [line 18]
-!26 = !{!"0xf\00\000\0064\0064\000\000", null, null, !16} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!27 = !MDLocation(line: 18, scope: !14)
-!28 = !MDLocation(line: 22, scope: !14)
+!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 13, arg: 1, scope: !14, file: !15, type: !10)
+!22 = !DILocation(line: 13, scope: !14)
+!23 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 16, scope: !14, file: !15, type: !4)
+!24 = !DILocation(line: 16, scope: !14)
+!25 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "fptr", line: 18, scope: !14, file: !15, type: !26)
+!26 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !16)
+!27 = !DILocation(line: 18, scope: !14)
+!28 = !DILocation(line: 22, scope: !14)
diff --git a/test/DebugInfo/version.ll b/test/DebugInfo/version.ll
index 6ee33b6a940e..f18a3e2871e1 100644
--- a/test/DebugInfo/version.ll
+++ b/test/DebugInfo/version.ll
@@ -18,15 +18,15 @@ attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointe
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!9, !11}
 
-!0 = !{!"0x11\0012\00clang version 3.4 (trunk 185475)\000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ]
-!1 = !{!"CodeGen/dwarf-version.c", !"test"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 185475)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "CodeGen/dwarf-version.c", directory: "test")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00main\00main\00\006\000\001\000\006\00256\000\006", !1, !5, !6, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 6] [def] [main]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "main", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 6, file: !1, scope: !5, type: !6, function: i32 ()* @main, variables: !2)
+!5 = !DIFile(filename: "CodeGen/dwarf-version.c", directory: "test")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 3}
-!10 = !MDLocation(line: 7, scope: !4)
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !DILocation(line: 7, scope: !4)
+!11 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/ExecutionEngine/2002-12-16-ArgTest.ll b/test/ExecutionEngine/2002-12-16-ArgTest.ll
deleted file mode 100644
index eb2fe8c04832..000000000000
--- a/test/ExecutionEngine/2002-12-16-ArgTest.ll
+++ /dev/null
@@ -1,37 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-@.LC0 = internal global [10 x i8] c"argc: %d\0A\00"		; <[10 x i8]*> [#uses=1]
-
-declare i32 @puts(i8*)
-
-define void @getoptions(i32* %argc) {
-bb0:
-	ret void
-}
-
-declare i32 @printf(i8*, ...)
-
-define i32 @main(i32 %argc, i8** %argv) {
-bb0:
-	call i32 (i8*, ...)* @printf( i8* getelementptr ([10 x i8]* @.LC0, i64 0, i64 0), i32 %argc )		; <i32>:0 [#uses=0]
-	%cast224 = bitcast i8** %argv to i8*		; <i8*> [#uses=1]
-	%local = alloca i8*		; <i8**> [#uses=3]
-	store i8* %cast224, i8** %local
-	%cond226 = icmp sle i32 %argc, 0		; <i1> [#uses=1]
-	br i1 %cond226, label %bb3, label %bb2
-bb2:		; preds = %bb2, %bb0
-	%cann-indvar = phi i32 [ 0, %bb0 ], [ %add1-indvar, %bb2 ]		; <i32> [#uses=2]
-	%add1-indvar = add i32 %cann-indvar, 1		; <i32> [#uses=2]
-	%cann-indvar-idxcast = sext i32 %cann-indvar to i64		; <i64> [#uses=1]
-	%CT = bitcast i8** %local to i8***		; <i8***> [#uses=1]
-	%reg115 = load i8*** %CT		; <i8**> [#uses=1]
-	%cast235 = getelementptr i8** %reg115, i64 %cann-indvar-idxcast		; <i8**> [#uses=1]
-	%reg117 = load i8** %cast235		; <i8*> [#uses=1]
-	%reg236 = call i32 @puts( i8* %reg117 )		; <i32> [#uses=0]
-	%cond239 = icmp slt i32 %add1-indvar, %argc		; <i1> [#uses=1]
-	br i1 %cond239, label %bb2, label %bb3
-bb3:		; preds = %bb2, %bb0
-	%cast243 = bitcast i8** %local to i32*		; <i32*> [#uses=1]
-	call void @getoptions( i32* %cast243 )
-	ret i32 0
-}
diff --git a/test/ExecutionEngine/2003-01-04-ArgumentBug.ll b/test/ExecutionEngine/2003-01-04-ArgumentBug.ll
deleted file mode 100644
index 68fdefefa542..000000000000
--- a/test/ExecutionEngine/2003-01-04-ArgumentBug.ll
+++ /dev/null
@@ -1,13 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @foo(i32 %X, i32 %Y, double %A) {
-	%cond212 = fcmp une double %A, 1.000000e+00		; <i1> [#uses=1]
-	%cast110 = zext i1 %cond212 to i32		; <i32> [#uses=1]
-	ret i32 %cast110
-}
-
-define i32 @main() {
-	%reg212 = call i32 @foo( i32 0, i32 1, double 1.000000e+00 )		; <i32> [#uses=1]
-	ret i32 %reg212
-}
-
diff --git a/test/ExecutionEngine/2003-01-04-LoopTest.ll b/test/ExecutionEngine/2003-01-04-LoopTest.ll
deleted file mode 100644
index 5a0311dd9393..000000000000
--- a/test/ExecutionEngine/2003-01-04-LoopTest.ll
+++ /dev/null
@@ -1,20 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @main() {
-	call i32 @mylog( i32 4 )		; <i32>:1 [#uses=0]
-	ret i32 0
-}
-
-define internal i32 @mylog(i32 %num) {
-bb0:
-	br label %bb2
-bb2:		; preds = %bb2, %bb0
-	%reg112 = phi i32 [ 10, %bb2 ], [ 1, %bb0 ]		; <i32> [#uses=1]
-	%cann-indvar = phi i32 [ %cann-indvar, %bb2 ], [ 0, %bb0 ]		; <i32> [#uses=1]
-	%reg114 = add i32 %reg112, 1		; <i32> [#uses=2]
-	%cond222 = icmp slt i32 %reg114, %num		; <i1> [#uses=1]
-	br i1 %cond222, label %bb2, label %bb3
-bb3:		; preds = %bb2
-	ret i32 %reg114
-}
-
diff --git a/test/ExecutionEngine/2003-01-04-PhiTest.ll b/test/ExecutionEngine/2003-01-04-PhiTest.ll
deleted file mode 100644
index 48576e7c83e6..000000000000
--- a/test/ExecutionEngine/2003-01-04-PhiTest.ll
+++ /dev/null
@@ -1,12 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @main() {
-; <label>:0
-	br label %Loop
-Loop:		; preds = %Loop, %0
-	%X = phi i32 [ 0, %0 ], [ 1, %Loop ]		; <i32> [#uses=1]
-	br i1 true, label %Out, label %Loop
-Out:		; preds = %Loop
-	ret i32 %X
-}
-
diff --git a/test/ExecutionEngine/2003-01-09-SARTest.ll b/test/ExecutionEngine/2003-01-09-SARTest.ll
deleted file mode 100644
index ed58e1184377..000000000000
--- a/test/ExecutionEngine/2003-01-09-SARTest.ll
+++ /dev/null
@@ -1,11 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-; We were accidentally inverting the signedness of right shifts.  Whoops.
-
-define i32 @main() {
-	%X = ashr i32 -1, 16		; <i32> [#uses=1]
-	%Y = ashr i32 %X, 16		; <i32> [#uses=1]
-	%Z = add i32 %Y, 1		; <i32> [#uses=1]
-	ret i32 %Z
-}
-
diff --git a/test/ExecutionEngine/2003-01-10-FUCOM.ll b/test/ExecutionEngine/2003-01-10-FUCOM.ll
deleted file mode 100644
index 4960e5969005..000000000000
--- a/test/ExecutionEngine/2003-01-10-FUCOM.ll
+++ /dev/null
@@ -1,10 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @main() {
-	%X = fadd double 0.000000e+00, 1.000000e+00		; <double> [#uses=1]
-	%Y = fsub double 0.000000e+00, 1.000000e+00		; <double> [#uses=2]
-	%Z = fcmp oeq double %X, %Y		; <i1> [#uses=0]
-	fadd double %Y, 0.000000e+00		; <double>:1 [#uses=0]
-	ret i32 0
-}
-
diff --git a/test/ExecutionEngine/2003-01-15-AlignmentTest.ll b/test/ExecutionEngine/2003-01-15-AlignmentTest.ll
deleted file mode 100644
index 038d7500101f..000000000000
--- a/test/ExecutionEngine/2003-01-15-AlignmentTest.ll
+++ /dev/null
@@ -1,17 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @bar(i8* %X) {
-        ; pointer should be 4 byte aligned!
-	%P = alloca double		; <double*> [#uses=1]
-	%R = ptrtoint double* %P to i32		; <i32> [#uses=1]
-	%A = and i32 %R, 3		; <i32> [#uses=1]
-	ret i32 %A
-}
-
-define i32 @main() {
-	%SP = alloca i8		; <i8*> [#uses=1]
-	%X = add i32 0, 0		; <i32> [#uses=1]
-	alloca i8, i32 %X		; <i8*>:1 [#uses=0]
-	call i32 @bar( i8* %SP )		; <i32>:2 [#uses=1]
-	ret i32 %2
-}
diff --git a/test/ExecutionEngine/2003-05-06-LivenessClobber.ll b/test/ExecutionEngine/2003-05-06-LivenessClobber.ll
deleted file mode 100644
index 576ef7cf6380..000000000000
--- a/test/ExecutionEngine/2003-05-06-LivenessClobber.ll
+++ /dev/null
@@ -1,19 +0,0 @@
-; This testcase should return with an exit code of 1.
-;
-; RUN: not %lli %s
-
-@test = global i64 0		; <i64*> [#uses=1]
-
-define internal i64 @test.upgrd.1() {
-	%tmp.0 = load i64* @test		; <i64> [#uses=1]
-	%tmp.1 = add i64 %tmp.0, 1		; <i64> [#uses=1]
-	ret i64 %tmp.1
-}
-
-define i32 @main() {
-	%L = call i64 @test.upgrd.1( )		; <i64> [#uses=1]
-	%I = trunc i64 %L to i32		; <i32> [#uses=1]
-	ret i32 %I
-}
-
-
diff --git a/test/ExecutionEngine/2003-05-07-ArgumentTest.ll b/test/ExecutionEngine/2003-05-07-ArgumentTest.ll
deleted file mode 100644
index 42db5fe93fcd..000000000000
--- a/test/ExecutionEngine/2003-05-07-ArgumentTest.ll
+++ /dev/null
@@ -1,11 +0,0 @@
-; RUN: %lli %s test
-
-declare i32 @puts(i8*)
-
-define i32 @main(i32 %argc.1, i8** %argv.1) {
-	%tmp.5 = getelementptr i8** %argv.1, i64 1		; <i8**> [#uses=1]
-	%tmp.6 = load i8** %tmp.5		; <i8*> [#uses=1]
-	%tmp.0 = call i32 @puts( i8* %tmp.6 )		; <i32> [#uses=0]
-	ret i32 0
-}
-
diff --git a/test/ExecutionEngine/2003-08-15-AllocaAssertion.ll b/test/ExecutionEngine/2003-08-15-AllocaAssertion.ll
deleted file mode 100644
index bee409c14411..000000000000
--- a/test/ExecutionEngine/2003-08-15-AllocaAssertion.ll
+++ /dev/null
@@ -1,11 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-; This testcase failed to work because two variable sized allocas confused the
-; local register allocator.
-
-define i32 @main(i32 %X) {
-	%A = alloca i32, i32 %X		; <i32*> [#uses=0]
-	%B = alloca float, i32 %X		; <float*> [#uses=0]
-	ret i32 0
-}
-
diff --git a/test/ExecutionEngine/2003-08-21-EnvironmentTest.ll b/test/ExecutionEngine/2003-08-21-EnvironmentTest.ll
deleted file mode 100644
index 63303fcff7c6..000000000000
--- a/test/ExecutionEngine/2003-08-21-EnvironmentTest.ll
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-;
-; Regression Test: EnvironmentTest.ll
-;
-; Description:
-;	This is a regression test that verifies that the JIT passes the
-;	environment to the main() function.
-;
-
-
-declare i32 @strlen(i8*)
-
-define i32 @main(i32 %argc.1, i8** %argv.1, i8** %envp.1) {
-	%tmp.2 = load i8** %envp.1		; <i8*> [#uses=1]
-	%tmp.3 = call i32 @strlen( i8* %tmp.2 )		; <i32> [#uses=1]
-	%T = icmp eq i32 %tmp.3, 0		; <i1> [#uses=1]
-	%R = zext i1 %T to i32		; <i32> [#uses=1]
-	ret i32 %R
-}
-
diff --git a/test/ExecutionEngine/2003-08-23-RegisterAllocatePhysReg.ll b/test/ExecutionEngine/2003-08-23-RegisterAllocatePhysReg.ll
deleted file mode 100644
index 8fb1bbbe9d77..000000000000
--- a/test/ExecutionEngine/2003-08-23-RegisterAllocatePhysReg.ll
+++ /dev/null
@@ -1,34 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-; This testcase exposes a bug in the local register allocator where it runs out
-; of registers (due to too many overlapping live ranges), but then attempts to
-; use the ESP register (which is not allocatable) to hold a value.
-
-define i32 @main(i32 %A) {
-        ; ESP gets used again...
-	%Ap2 = alloca i32, i32 %A		; <i32*> [#uses=11]
-	; Produce lots of overlapping live ranges
-        %B = add i32 %A, 1		; <i32> [#uses=1]
-	%C = add i32 %A, 2		; <i32> [#uses=1]
-	%D = add i32 %A, 3		; <i32> [#uses=1]
-	%E = add i32 %A, 4		; <i32> [#uses=1]
-	%F = add i32 %A, 5		; <i32> [#uses=1]
-	%G = add i32 %A, 6		; <i32> [#uses=1]
-	%H = add i32 %A, 7		; <i32> [#uses=1]
-	%I = add i32 %A, 8		; <i32> [#uses=1]
-	%J = add i32 %A, 9		; <i32> [#uses=1]
-	%K = add i32 %A, 10		; <i32> [#uses=1]
-        ; Uses of all of the values
-	store i32 %A, i32* %Ap2
-	store i32 %B, i32* %Ap2
-	store i32 %C, i32* %Ap2
-	store i32 %D, i32* %Ap2
-	store i32 %E, i32* %Ap2
-	store i32 %F, i32* %Ap2
-	store i32 %G, i32* %Ap2
-	store i32 %H, i32* %Ap2
-	store i32 %I, i32* %Ap2
-	store i32 %J, i32* %Ap2
-	store i32 %K, i32* %Ap2
-	ret i32 0
-}
diff --git a/test/ExecutionEngine/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll b/test/ExecutionEngine/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll
deleted file mode 100644
index 6513540903e8..000000000000
--- a/test/ExecutionEngine/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-@A = global i32 0		; <i32*> [#uses=1]
-
-define i32 @main() {
-	%Ret = call i32 @test( i1 true, i32 0 )		; <i32> [#uses=1]
-	ret i32 %Ret
-}
-
-define i32 @test(i1 %c, i32 %A) {
-	br i1 %c, label %Taken1, label %NotTaken
-Cont:		; preds = %Taken1, %NotTaken
-	%V = phi i32 [ 0, %NotTaken ], [ sub (i32 ptrtoint (i32* @A to i32), i32 1234), %Taken1 ]		; <i32> [#uses=0]
-	ret i32 0
-NotTaken:		; preds = %0
-	br label %Cont
-Taken1:		; preds = %0
-	%B = icmp eq i32 %A, 0		; <i1> [#uses=1]
-	br i1 %B, label %Cont, label %ExitError
-ExitError:		; preds = %Taken1
-	ret i32 12
-}
-
diff --git a/test/ExecutionEngine/2005-12-02-TailCallBug.ll b/test/ExecutionEngine/2005-12-02-TailCallBug.ll
deleted file mode 100644
index 2ac8ad1795d8..000000000000
--- a/test/ExecutionEngine/2005-12-02-TailCallBug.ll
+++ /dev/null
@@ -1,21 +0,0 @@
-; PR672
-; RUN: %lli %s
-
-define i32 @main() {
-	%f = bitcast i32 (i32, i32*, i32)* @check_tail to i32*		; <i32*> [#uses=1]
-	%res = tail call fastcc i32 @check_tail( i32 10, i32* %f, i32 10 )		; <i32> [#uses=1]
-	ret i32 %res
-}
-
-define fastcc i32 @check_tail(i32 %x, i32* %f, i32 %g) {
-	%tmp1 = icmp sgt i32 %x, 0		; <i1> [#uses=1]
-	br i1 %tmp1, label %if-then, label %if-else
-if-then:		; preds = %0
-	%fun_ptr = bitcast i32* %f to i32 (i32, i32*, i32)*		; <i32 (i32, i32*, i32)*> [#uses=1]
-	%arg1 = add i32 %x, -1		; <i32> [#uses=1]
-	%res = tail call fastcc i32 %fun_ptr( i32 %arg1, i32* %f, i32 %g )		; <i32> [#uses=1]
-	ret i32 %res
-if-else:		; preds = %0
-	ret i32 %x
-}
-
diff --git a/test/ExecutionEngine/2007-12-10-APIntLoadStore.ll b/test/ExecutionEngine/2007-12-10-APIntLoadStore.ll
deleted file mode 100644
index 418361163fcf..000000000000
--- a/test/ExecutionEngine/2007-12-10-APIntLoadStore.ll
+++ /dev/null
@@ -1,19 +0,0 @@
-; RUN: %lli -force-interpreter %s
-; PR1836
-
-define i32 @main() {
-entry:
-    %retval = alloca i32        ; <i32*> [#uses=2]
-    %tmp = alloca i32       ; <i32*> [#uses=2]
-    %x = alloca i75, align 16       ; <i75*> [#uses=1]
-    %"alloca point" = bitcast i32 0 to i32      ; <i32> [#uses=0]
-    store i75 999, i75* %x, align 16
-    store i32 0, i32* %tmp, align 4
-    %tmp1 = load i32* %tmp, align 4     ; <i32> [#uses=1]
-    store i32 %tmp1, i32* %retval, align 4
-    br label %return
-
-return:     ; preds = %entry
-    %retval2 = load i32* %retval        ; <i32> [#uses=1]
-    ret i32 %retval2
-}
diff --git a/test/ExecutionEngine/2008-06-05-APInt-OverAShr.ll b/test/ExecutionEngine/2008-06-05-APInt-OverAShr.ll
deleted file mode 100644
index 349db69e4c63..000000000000
--- a/test/ExecutionEngine/2008-06-05-APInt-OverAShr.ll
+++ /dev/null
@@ -1,60 +0,0 @@
-; RUN: %lli -force-interpreter=true %s | FileCheck %s
-; CHECK: 1
-
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
-target triple = "i686-pc-linux-gnu"
-@.str = internal constant [10 x i8] c"MSB = %d\0A\00"		; <[10 x i8]*> [#uses=1]
-
-define i65 @foo(i65 %x) {
-entry:
-	%x_addr = alloca i65		; <i65*> [#uses=2]
-	%retval = alloca i65		; <i65*> [#uses=2]
-	%tmp = alloca i65		; <i65*> [#uses=2]
-	%"alloca point" = bitcast i65 0 to i65		; <i65> [#uses=0]
-	store i65 %x, i65* %x_addr
-	%tmp1 = load i65* %x_addr, align 4		; <i65> [#uses=1]
-	%tmp2 = ashr i65 %tmp1, 65		; <i65> [#uses=1]
-	store i65 %tmp2, i65* %tmp, align 4
-	%tmp3 = load i65* %tmp, align 4		; <i65> [#uses=1]
-	store i65 %tmp3, i65* %retval, align 4
-	br label %return
-
-return:		; preds = %entry
-	%retval4 = load i65* %retval		; <i65> [#uses=1]
-	ret i65 %retval4
-}
-
-define i32 @main() {
-entry:
-	%retval = alloca i32		; <i32*> [#uses=1]
-	%iftmp.0 = alloca i32		; <i32*> [#uses=3]
-	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
-	%tmp = call i65 @foo( i65 -9 )		; <i65> [#uses=1]
-	%tmp1 = lshr i65 %tmp, 64		; <i65> [#uses=1]
-	%tmp2 = xor i65 %tmp1, 1		; <i65> [#uses=1]
-	%tmp3 = and i65 %tmp2, 1		; <i65> [#uses=1]
-	%tmp34 = trunc i65 %tmp3 to i8		; <i8> [#uses=1]
-	%toBool = icmp ne i8 %tmp34, 0		; <i1> [#uses=1]
-	br i1 %toBool, label %cond_true, label %cond_false
-
-cond_true:		; preds = %entry
-	store i32 0, i32* %iftmp.0, align 4
-	br label %cond_next
-
-cond_false:		; preds = %entry
-	store i32 1, i32* %iftmp.0, align 4
-	br label %cond_next
-
-cond_next:		; preds = %cond_false, %cond_true
-	%tmp5 = getelementptr [10 x i8]* @.str, i32 0, i32 0		; <i8*> [#uses=1]
-	%tmp6 = load i32* %iftmp.0, align 4		; <i32> [#uses=1]
-	%tmp7 = call i32 (i8*, ...)* @printf( i8* noalias  %tmp5, i32 %tmp6 ) nounwind 		; <i32> [#uses=0]
-	br label %return
-
-return:		; preds = %cond_next
-    store i32 0, i32* %retval, align 4
-	%retval8 = load i32* %retval		; <i32> [#uses=1]
-	ret i32 %retval8
-}
-
-declare i32 @printf(i8* noalias , ...) nounwind 
diff --git a/test/ExecutionEngine/MCJIT/2002-12-16-ArgTest.ll b/test/ExecutionEngine/MCJIT/2002-12-16-ArgTest.ll
index eb2fe8c04832..7b1cb16def0e 100644
--- a/test/ExecutionEngine/MCJIT/2002-12-16-ArgTest.ll
+++ b/test/ExecutionEngine/MCJIT/2002-12-16-ArgTest.ll
@@ -13,7 +13,7 @@ declare i32 @printf(i8*, ...)
 
 define i32 @main(i32 %argc, i8** %argv) {
 bb0:
-	call i32 (i8*, ...)* @printf( i8* getelementptr ([10 x i8]* @.LC0, i64 0, i64 0), i32 %argc )		; <i32>:0 [#uses=0]
+	call i32 (i8*, ...) @printf( i8* getelementptr ([10 x i8], [10 x i8]* @.LC0, i64 0, i64 0), i32 %argc )		; <i32>:0 [#uses=0]
 	%cast224 = bitcast i8** %argv to i8*		; <i8*> [#uses=1]
 	%local = alloca i8*		; <i8**> [#uses=3]
 	store i8* %cast224, i8** %local
@@ -24,9 +24,9 @@ bb2:		; preds = %bb2, %bb0
 	%add1-indvar = add i32 %cann-indvar, 1		; <i32> [#uses=2]
 	%cann-indvar-idxcast = sext i32 %cann-indvar to i64		; <i64> [#uses=1]
 	%CT = bitcast i8** %local to i8***		; <i8***> [#uses=1]
-	%reg115 = load i8*** %CT		; <i8**> [#uses=1]
-	%cast235 = getelementptr i8** %reg115, i64 %cann-indvar-idxcast		; <i8**> [#uses=1]
-	%reg117 = load i8** %cast235		; <i8*> [#uses=1]
+	%reg115 = load i8**, i8*** %CT		; <i8**> [#uses=1]
+	%cast235 = getelementptr i8*, i8** %reg115, i64 %cann-indvar-idxcast		; <i8**> [#uses=1]
+	%reg117 = load i8*, i8** %cast235		; <i8*> [#uses=1]
 	%reg236 = call i32 @puts( i8* %reg117 )		; <i32> [#uses=0]
 	%cond239 = icmp slt i32 %add1-indvar, %argc		; <i1> [#uses=1]
 	br i1 %cond239, label %bb2, label %bb3
diff --git a/test/ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll b/test/ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll
index 576ef7cf6380..d714bf7367bc 100644
--- a/test/ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll
+++ b/test/ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll
@@ -5,7 +5,7 @@
 @test = global i64 0		; <i64*> [#uses=1]
 
 define internal i64 @test.upgrd.1() {
-	%tmp.0 = load i64* @test		; <i64> [#uses=1]
+	%tmp.0 = load i64, i64* @test		; <i64> [#uses=1]
 	%tmp.1 = add i64 %tmp.0, 1		; <i64> [#uses=1]
 	ret i64 %tmp.1
 }
diff --git a/test/ExecutionEngine/MCJIT/2003-05-07-ArgumentTest.ll b/test/ExecutionEngine/MCJIT/2003-05-07-ArgumentTest.ll
index 42db5fe93fcd..0538201326f9 100644
--- a/test/ExecutionEngine/MCJIT/2003-05-07-ArgumentTest.ll
+++ b/test/ExecutionEngine/MCJIT/2003-05-07-ArgumentTest.ll
@@ -3,8 +3,8 @@
 declare i32 @puts(i8*)
 
 define i32 @main(i32 %argc.1, i8** %argv.1) {
-	%tmp.5 = getelementptr i8** %argv.1, i64 1		; <i8**> [#uses=1]
-	%tmp.6 = load i8** %tmp.5		; <i8*> [#uses=1]
+	%tmp.5 = getelementptr i8*, i8** %argv.1, i64 1		; <i8**> [#uses=1]
+	%tmp.6 = load i8*, i8** %tmp.5		; <i8*> [#uses=1]
 	%tmp.0 = call i32 @puts( i8* %tmp.6 )		; <i32> [#uses=0]
 	ret i32 0
 }
diff --git a/test/ExecutionEngine/MCJIT/2003-08-21-EnvironmentTest.ll b/test/ExecutionEngine/MCJIT/2003-08-21-EnvironmentTest.ll
index 63303fcff7c6..e2c52b495d9f 100644
--- a/test/ExecutionEngine/MCJIT/2003-08-21-EnvironmentTest.ll
+++ b/test/ExecutionEngine/MCJIT/2003-08-21-EnvironmentTest.ll
@@ -12,7 +12,7 @@
 declare i32 @strlen(i8*)
 
 define i32 @main(i32 %argc.1, i8** %argv.1, i8** %envp.1) {
-	%tmp.2 = load i8** %envp.1		; <i8*> [#uses=1]
+	%tmp.2 = load i8*, i8** %envp.1		; <i8*> [#uses=1]
 	%tmp.3 = call i32 @strlen( i8* %tmp.2 )		; <i32> [#uses=1]
 	%T = icmp eq i32 %tmp.3, 0		; <i1> [#uses=1]
 	%R = zext i1 %T to i32		; <i32> [#uses=1]
diff --git a/test/ExecutionEngine/MCJIT/2007-12-10-APIntLoadStore.ll b/test/ExecutionEngine/MCJIT/2007-12-10-APIntLoadStore.ll
index 418361163fcf..d557f573dae5 100644
--- a/test/ExecutionEngine/MCJIT/2007-12-10-APIntLoadStore.ll
+++ b/test/ExecutionEngine/MCJIT/2007-12-10-APIntLoadStore.ll
@@ -9,11 +9,11 @@ entry:
     %"alloca point" = bitcast i32 0 to i32      ; <i32> [#uses=0]
     store i75 999, i75* %x, align 16
     store i32 0, i32* %tmp, align 4
-    %tmp1 = load i32* %tmp, align 4     ; <i32> [#uses=1]
+    %tmp1 = load i32, i32* %tmp, align 4     ; <i32> [#uses=1]
     store i32 %tmp1, i32* %retval, align 4
     br label %return
 
 return:     ; preds = %entry
-    %retval2 = load i32* %retval        ; <i32> [#uses=1]
+    %retval2 = load i32, i32* %retval        ; <i32> [#uses=1]
     ret i32 %retval2
 }
diff --git a/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll b/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll
index 349db69e4c63..c0a5d3b4c863 100644
--- a/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll
+++ b/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll
@@ -12,15 +12,15 @@ entry:
 	%tmp = alloca i65		; <i65*> [#uses=2]
 	%"alloca point" = bitcast i65 0 to i65		; <i65> [#uses=0]
 	store i65 %x, i65* %x_addr
-	%tmp1 = load i65* %x_addr, align 4		; <i65> [#uses=1]
+	%tmp1 = load i65, i65* %x_addr, align 4		; <i65> [#uses=1]
 	%tmp2 = ashr i65 %tmp1, 65		; <i65> [#uses=1]
 	store i65 %tmp2, i65* %tmp, align 4
-	%tmp3 = load i65* %tmp, align 4		; <i65> [#uses=1]
+	%tmp3 = load i65, i65* %tmp, align 4		; <i65> [#uses=1]
 	store i65 %tmp3, i65* %retval, align 4
 	br label %return
 
 return:		; preds = %entry
-	%retval4 = load i65* %retval		; <i65> [#uses=1]
+	%retval4 = load i65, i65* %retval		; <i65> [#uses=1]
 	ret i65 %retval4
 }
 
@@ -46,14 +46,14 @@ cond_false:		; preds = %entry
 	br label %cond_next
 
 cond_next:		; preds = %cond_false, %cond_true
-	%tmp5 = getelementptr [10 x i8]* @.str, i32 0, i32 0		; <i8*> [#uses=1]
-	%tmp6 = load i32* %iftmp.0, align 4		; <i32> [#uses=1]
-	%tmp7 = call i32 (i8*, ...)* @printf( i8* noalias  %tmp5, i32 %tmp6 ) nounwind 		; <i32> [#uses=0]
+	%tmp5 = getelementptr [10 x i8], [10 x i8]* @.str, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp6 = load i32, i32* %iftmp.0, align 4		; <i32> [#uses=1]
+	%tmp7 = call i32 (i8*, ...) @printf( i8* noalias  %tmp5, i32 %tmp6 ) nounwind 		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %cond_next
     store i32 0, i32* %retval, align 4
-	%retval8 = load i32* %retval		; <i32> [#uses=1]
+	%retval8 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval8
 }
 
diff --git a/test/ExecutionEngine/MCJIT/2010-01-15-UndefValue.ll b/test/ExecutionEngine/MCJIT/2010-01-15-UndefValue.ll
deleted file mode 100644
index 8bf03de321ba..000000000000
--- a/test/ExecutionEngine/MCJIT/2010-01-15-UndefValue.ll
+++ /dev/null
@@ -1,8 +0,0 @@
-; RUN: %lli -force-interpreter=true %s > /dev/null
-
-define i32 @main() {
-       %a = add i32 0, undef
-       %b = fadd float 0.0, undef
-       %c = fadd double 0.0, undef
-       ret i32 0
-}
diff --git a/test/ExecutionEngine/MCJIT/2013-04-04-RelocAddend.ll b/test/ExecutionEngine/MCJIT/2013-04-04-RelocAddend.ll
index d9ff347b0786..631cb2f67af0 100644
--- a/test/ExecutionEngine/MCJIT/2013-04-04-RelocAddend.ll
+++ b/test/ExecutionEngine/MCJIT/2013-04-04-RelocAddend.ll
@@ -14,12 +14,12 @@
 ; 
 
 @test = global [2 x i32] [i32 -1, i32 0], align 4
-@p = global i32* getelementptr inbounds ([2 x i32]* @test, i64 0, i64 1), align 8
+@p = global i32* getelementptr inbounds ([2 x i32], [2 x i32]* @test, i64 0, i64 1), align 8
 
 define i32 @main() {
 entry:
-  %0 = load i32** @p, align 8
-  %1 = load i32* %0, align 4
+  %0 = load i32*, i32** @p, align 8
+  %1 = load i32, i32* %0, align 4
   ret i32 %1
 }
 
diff --git a/test/ExecutionEngine/MCJIT/fpbitcast.ll b/test/ExecutionEngine/MCJIT/fpbitcast.ll
index e6d06f83db49..670c142c0ffe 100644
--- a/test/ExecutionEngine/MCJIT/fpbitcast.ll
+++ b/test/ExecutionEngine/MCJIT/fpbitcast.ll
@@ -12,8 +12,8 @@ entry:
 define i32 @main()
 {
        %res = call i32 @test(double 3.14)
-       %ptr = getelementptr [4 x i8]* @format, i32 0, i32 0
-       call i32 (i8*,...)* @printf(i8* %ptr, i32 %res)
+       %ptr = getelementptr [4 x i8], [4 x i8]* @format, i32 0, i32 0
+       call i32 (i8*,...) @printf(i8* %ptr, i32 %res)
        ret i32 0
 }
 
diff --git a/test/ExecutionEngine/MCJIT/hello-sm-pic.ll b/test/ExecutionEngine/MCJIT/hello-sm-pic.ll
deleted file mode 100644
index 7db60f7aeeb4..000000000000
--- a/test/ExecutionEngine/MCJIT/hello-sm-pic.ll
+++ /dev/null
@@ -1,12 +0,0 @@
-; RUN: %lli -relocation-model=pic -code-model=small %s > /dev/null
-; XFAIL: mips, i686, i386, darwin, aarch64, arm
-
-@.LC0 = internal global [12 x i8] c"Hello World\00"		; <[12 x i8]*> [#uses=1]
-
-declare i32 @puts(i8*)
-
-define i32 @main() {
-	%reg210 = call i32 @puts( i8* getelementptr ([12 x i8]* @.LC0, i64 0, i64 0) )		; <i32> [#uses=0]
-	ret i32 0
-}
-
diff --git a/test/ExecutionEngine/MCJIT/hello.ll b/test/ExecutionEngine/MCJIT/hello.ll
index 47e36a589563..516f57a81cd1 100644
--- a/test/ExecutionEngine/MCJIT/hello.ll
+++ b/test/ExecutionEngine/MCJIT/hello.ll
@@ -5,7 +5,7 @@
 declare i32 @puts(i8*)
 
 define i32 @main() {
-	%reg210 = call i32 @puts( i8* getelementptr ([12 x i8]* @.LC0, i64 0, i64 0) )		; <i32> [#uses=0]
+	%reg210 = call i32 @puts( i8* getelementptr ([12 x i8], [12 x i8]* @.LC0, i64 0, i64 0) )		; <i32> [#uses=0]
 	ret i32 0
 }
 
diff --git a/test/ExecutionEngine/MCJIT/hello2.ll b/test/ExecutionEngine/MCJIT/hello2.ll
index 13b25884fee7..31a1a6e7a74e 100644
--- a/test/ExecutionEngine/MCJIT/hello2.ll
+++ b/test/ExecutionEngine/MCJIT/hello2.ll
@@ -6,7 +6,7 @@
 declare void @printf([13 x i8]*, ...)
 
 define void @bar() {
-	call void ([13 x i8]*, ...)* @printf( [13 x i8]* @msg )
+	call void ([13 x i8]*, ...) @printf( [13 x i8]* @msg )
 	ret void
 }
 
diff --git a/test/ExecutionEngine/MCJIT/pr13727.ll b/test/ExecutionEngine/MCJIT/pr13727.ll
index 6f5ae3999bcd..79dd9b4ccc0e 100644
--- a/test/ExecutionEngine/MCJIT/pr13727.ll
+++ b/test/ExecutionEngine/MCJIT/pr13727.ll
@@ -31,20 +31,20 @@ entry:
   %retval = alloca i32, align 4
   %i = alloca i32, align 4
   store i32 0, i32* %retval
-  %0 = load i32* @zero_int, align 4
+  %0 = load i32, i32* @zero_int, align 4
   %add = add nsw i32 %0, 5
   %idxprom = sext i32 %add to i64
-  %arrayidx = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom
+  %arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom
   store i32 40, i32* %arrayidx, align 4
-  %1 = load double* @zero_double, align 8
+  %1 = load double, double* @zero_double, align 8
   %cmp = fcmp olt double %1, 1.100000e+00
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %2 = load i32* @zero_int, align 4
+  %2 = load i32, i32* @zero_int, align 4
   %add1 = add nsw i32 %2, 2
   %idxprom2 = sext i32 %add1 to i64
-  %arrayidx3 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom2
+  %arrayidx3 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom2
   store i32 70, i32* %arrayidx3, align 4
   br label %if.end
 
@@ -53,35 +53,35 @@ if.end:                                           ; preds = %if.then, %entry
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %if.end
-  %3 = load i32* %i, align 4
+  %3 = load i32, i32* %i, align 4
   %cmp4 = icmp slt i32 %3, 10
   br i1 %cmp4, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %sub = sub nsw i32 %4, 1
   %idxprom5 = sext i32 %sub to i64
-  %arrayidx6 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom5
-  %5 = load i32* %arrayidx6, align 4
-  %6 = load i32* %i, align 4
+  %arrayidx6 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom5
+  %5 = load i32, i32* %arrayidx6, align 4
+  %6 = load i32, i32* %i, align 4
   %idxprom7 = sext i32 %6 to i64
-  %arrayidx8 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom7
-  %7 = load i32* %arrayidx8, align 4
+  %arrayidx8 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom7
+  %7 = load i32, i32* %arrayidx8, align 4
   %add9 = add nsw i32 %5, %7
-  %8 = load i32* %i, align 4
+  %8 = load i32, i32* %i, align 4
   %idxprom10 = sext i32 %8 to i64
-  %arrayidx11 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom10
+  %arrayidx11 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom10
   store i32 %add9, i32* %arrayidx11, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %9 = load i32* %i, align 4
+  %9 = load i32, i32* %i, align 4
   %inc = add nsw i32 %9, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %10 = load i32* getelementptr inbounds ([10 x i32]* @zero_arr, i32 0, i64 9), align 4
+  %10 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @zero_arr, i32 0, i64 9), align 4
   %cmp12 = icmp eq i32 %10, 110
   %cond = select i1 %cmp12, i32 0, i32 -1
   ret i32 %cond
diff --git a/test/ExecutionEngine/MCJIT/remote/stubs-remote.ll b/test/ExecutionEngine/MCJIT/remote/stubs-remote.ll
index da4ddc6943c2..a834ac5c9850 100644
--- a/test/ExecutionEngine/MCJIT/remote/stubs-remote.ll
+++ b/test/ExecutionEngine/MCJIT/remote/stubs-remote.ll
@@ -21,14 +21,14 @@ entry:
 pass_block:
 	ret void
 fail_block:
-	call i32 @puts(i8* getelementptr([46 x i8]* @lcaic_failure, i32 0, i32 0))
+	call i32 @puts(i8* getelementptr([46 x i8], [46 x i8]* @lcaic_failure, i32 0, i32 0))
 	call void @exit(i32 1)
 	unreachable
 }
 
 define i1 @test() nounwind {
 entry:
-	%tmp = load i1 ()** @funcPtr
+	%tmp = load i1 ()*, i1 ()** @funcPtr
 	%eq = icmp eq i1 ()* %tmp, @test
 	ret i1 %eq
 }
diff --git a/test/ExecutionEngine/MCJIT/remote/stubs-sm-pic.ll b/test/ExecutionEngine/MCJIT/remote/stubs-sm-pic.ll
index f6a16078dfae..62e89cad332d 100644
--- a/test/ExecutionEngine/MCJIT/remote/stubs-sm-pic.ll
+++ b/test/ExecutionEngine/MCJIT/remote/stubs-sm-pic.ll
@@ -21,14 +21,14 @@ entry:
 pass_block:
 	ret void
 fail_block:
-	call i32 @puts(i8* getelementptr([46 x i8]* @lcaic_failure, i32 0, i32 0))
+	call i32 @puts(i8* getelementptr([46 x i8], [46 x i8]* @lcaic_failure, i32 0, i32 0))
 	call void @exit(i32 1)
 	unreachable
 }
 
 define i1 @test() nounwind {
 entry:
-	%tmp = load i1 ()** @funcPtr
+	%tmp = load i1 ()*, i1 ()** @funcPtr
 	%eq = icmp eq i1 ()* %tmp, @test
 	ret i1 %eq
 }
diff --git a/test/ExecutionEngine/MCJIT/remote/test-common-symbols-remote.ll b/test/ExecutionEngine/MCJIT/remote/test-common-symbols-remote.ll
index 0f58710603d0..fb7750adf497 100644
--- a/test/ExecutionEngine/MCJIT/remote/test-common-symbols-remote.ll
+++ b/test/ExecutionEngine/MCJIT/remote/test-common-symbols-remote.ll
@@ -31,20 +31,20 @@ entry:
   %retval = alloca i32, align 4
   %i = alloca i32, align 4
   store i32 0, i32* %retval
-  %0 = load i32* @zero_int, align 4
+  %0 = load i32, i32* @zero_int, align 4
   %add = add nsw i32 %0, 5
   %idxprom = sext i32 %add to i64
-  %arrayidx = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom
+  %arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom
   store i32 40, i32* %arrayidx, align 4
-  %1 = load double* @zero_double, align 8
+  %1 = load double, double* @zero_double, align 8
   %cmp = fcmp olt double %1, 1.000000e+00
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %2 = load i32* @zero_int, align 4
+  %2 = load i32, i32* @zero_int, align 4
   %add1 = add nsw i32 %2, 2
   %idxprom2 = sext i32 %add1 to i64
-  %arrayidx3 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom2
+  %arrayidx3 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom2
   store i32 70, i32* %arrayidx3, align 4
   br label %if.end
 
@@ -53,35 +53,35 @@ if.end:                                           ; preds = %if.then, %entry
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %if.end
-  %3 = load i32* %i, align 4
+  %3 = load i32, i32* %i, align 4
   %cmp4 = icmp slt i32 %3, 10
   br i1 %cmp4, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %sub = sub nsw i32 %4, 1
   %idxprom5 = sext i32 %sub to i64
-  %arrayidx6 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom5
-  %5 = load i32* %arrayidx6, align 4
-  %6 = load i32* %i, align 4
+  %arrayidx6 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom5
+  %5 = load i32, i32* %arrayidx6, align 4
+  %6 = load i32, i32* %i, align 4
   %idxprom7 = sext i32 %6 to i64
-  %arrayidx8 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom7
-  %7 = load i32* %arrayidx8, align 4
+  %arrayidx8 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom7
+  %7 = load i32, i32* %arrayidx8, align 4
   %add9 = add nsw i32 %5, %7
-  %8 = load i32* %i, align 4
+  %8 = load i32, i32* %i, align 4
   %idxprom10 = sext i32 %8 to i64
-  %arrayidx11 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom10
+  %arrayidx11 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom10
   store i32 %add9, i32* %arrayidx11, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %9 = load i32* %i, align 4
+  %9 = load i32, i32* %i, align 4
   %inc = add nsw i32 %9, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %10 = load i32* getelementptr inbounds ([10 x i32]* @zero_arr, i32 0, i64 9), align 4
+  %10 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @zero_arr, i32 0, i64 9), align 4
   %cmp12 = icmp eq i32 %10, 110
   %cond = select i1 %cmp12, i32 0, i32 -1
   ret i32 %cond
diff --git a/test/ExecutionEngine/MCJIT/remote/test-fp-no-external-funcs-remote.ll b/test/ExecutionEngine/MCJIT/remote/test-fp-no-external-funcs-remote.ll
index 9d11415c906f..6134b8b24641 100644
--- a/test/ExecutionEngine/MCJIT/remote/test-fp-no-external-funcs-remote.ll
+++ b/test/ExecutionEngine/MCJIT/remote/test-fp-no-external-funcs-remote.ll
@@ -1,7 +1,7 @@
 ; RUN: %lli -remote-mcjit -mcjit-remote-process=lli-child-target%exeext %s > /dev/null
 
 define double @test(double* %DP, double %Arg) nounwind {
-	%D = load double* %DP		; <double> [#uses=1]
+	%D = load double, double* %DP		; <double> [#uses=1]
 	%V = fadd double %D, 1.000000e+00		; <double> [#uses=2]
 	%W = fsub double %V, %V		; <double> [#uses=3]
 	%X = fmul double %W, %W		; <double> [#uses=2]
diff --git a/test/ExecutionEngine/MCJIT/remote/test-global-init-nonzero-remote.ll b/test/ExecutionEngine/MCJIT/remote/test-global-init-nonzero-remote.ll
index 40b514fd8e1f..5b7999c067e4 100644
--- a/test/ExecutionEngine/MCJIT/remote/test-global-init-nonzero-remote.ll
+++ b/test/ExecutionEngine/MCJIT/remote/test-global-init-nonzero-remote.ll
@@ -11,24 +11,24 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 49
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* @count, align 4
+  %1 = load i32, i32* @count, align 4
   %inc = add nsw i32 %1, 1
   store i32 %inc, i32* @count, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %2 = load i32* %i, align 4
+  %2 = load i32, i32* %i, align 4
   %inc1 = add nsw i32 %2, 1
   store i32 %inc1, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %3 = load i32* @count, align 4
+  %3 = load i32, i32* @count, align 4
   %sub = sub nsw i32 %3, 50
   ret i32 %sub
 }
diff --git a/test/ExecutionEngine/MCJIT/remote/test-global-init-nonzero-sm-pic.ll b/test/ExecutionEngine/MCJIT/remote/test-global-init-nonzero-sm-pic.ll
index 5119b72d4485..f9184b4077bb 100644
--- a/test/ExecutionEngine/MCJIT/remote/test-global-init-nonzero-sm-pic.ll
+++ b/test/ExecutionEngine/MCJIT/remote/test-global-init-nonzero-sm-pic.ll
@@ -12,24 +12,24 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 49
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* @count, align 4
+  %1 = load i32, i32* @count, align 4
   %inc = add nsw i32 %1, 1
   store i32 %inc, i32* @count, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %2 = load i32* %i, align 4
+  %2 = load i32, i32* %i, align 4
   %inc1 = add nsw i32 %2, 1
   store i32 %inc1, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %3 = load i32* @count, align 4
+  %3 = load i32, i32* @count, align 4
   %sub = sub nsw i32 %3, 50
   ret i32 %sub
 }
diff --git a/test/ExecutionEngine/MCJIT/remote/test-ptr-reloc-remote.ll b/test/ExecutionEngine/MCJIT/remote/test-ptr-reloc-remote.ll
index ba3ffff21425..ad1af93ffdef 100644
--- a/test/ExecutionEngine/MCJIT/remote/test-ptr-reloc-remote.ll
+++ b/test/ExecutionEngine/MCJIT/remote/test-ptr-reloc-remote.ll
@@ -1,14 +1,14 @@
 ; RUN: %lli -remote-mcjit -O0 -mcjit-remote-process=lli-child-target%exeext %s
 
 @.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
-@ptr = global i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), align 4
+@ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
 @.str1 = private unnamed_addr constant [6 x i8] c"data2\00", align 1
-@ptr2 = global i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0), align 4
+@ptr2 = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), align 4
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly {
 entry:
-  %0 = load i8** @ptr, align 4
-  %1 = load i8** @ptr2, align 4
+  %0 = load i8*, i8** @ptr, align 4
+  %1 = load i8*, i8** @ptr2, align 4
   %cmp = icmp eq i8* %0, %1
   %. = zext i1 %cmp to i32
   ret i32 %.
diff --git a/test/ExecutionEngine/MCJIT/remote/test-ptr-reloc-sm-pic.ll b/test/ExecutionEngine/MCJIT/remote/test-ptr-reloc-sm-pic.ll
index bbc71afdf7e3..d9a4faa8e6bd 100644
--- a/test/ExecutionEngine/MCJIT/remote/test-ptr-reloc-sm-pic.ll
+++ b/test/ExecutionEngine/MCJIT/remote/test-ptr-reloc-sm-pic.ll
@@ -2,14 +2,14 @@
 ; XFAIL: mips, aarch64, arm, i686, i386
 
 @.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
-@ptr = global i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), align 4
+@ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
 @.str1 = private unnamed_addr constant [6 x i8] c"data2\00", align 1
-@ptr2 = global i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0), align 4
+@ptr2 = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), align 4
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly {
 entry:
-  %0 = load i8** @ptr, align 4
-  %1 = load i8** @ptr2, align 4
+  %0 = load i8*, i8** @ptr, align 4
+  %1 = load i8*, i8** @ptr2, align 4
   %cmp = icmp eq i8* %0, %1
   %. = zext i1 %cmp to i32
   ret i32 %.
diff --git a/test/ExecutionEngine/MCJIT/stubs-sm-pic.ll b/test/ExecutionEngine/MCJIT/stubs-sm-pic.ll
index 9b83ed231e9e..6eebe44e3ff3 100644
--- a/test/ExecutionEngine/MCJIT/stubs-sm-pic.ll
+++ b/test/ExecutionEngine/MCJIT/stubs-sm-pic.ll
@@ -20,14 +20,14 @@ entry:
 pass_block:
 	ret void
 fail_block:
-	call i32 @puts(i8* getelementptr([46 x i8]* @lcaic_failure, i32 0, i32 0))
+	call i32 @puts(i8* getelementptr([46 x i8], [46 x i8]* @lcaic_failure, i32 0, i32 0))
 	call void @exit(i32 1)
 	unreachable
 }
 
 define i1 @test() nounwind {
 entry:
-	%tmp = load i1 ()** @funcPtr
+	%tmp = load i1 ()*, i1 ()** @funcPtr
 	%eq = icmp eq i1 ()* %tmp, @test
 	ret i1 %eq
 }
diff --git a/test/ExecutionEngine/MCJIT/stubs.ll b/test/ExecutionEngine/MCJIT/stubs.ll
index b7d922f2cb6d..5b7acc71d04c 100644
--- a/test/ExecutionEngine/MCJIT/stubs.ll
+++ b/test/ExecutionEngine/MCJIT/stubs.ll
@@ -19,14 +19,14 @@ entry:
 pass_block:
 	ret void
 fail_block:
-	call i32 @puts(i8* getelementptr([46 x i8]* @lcaic_failure, i32 0, i32 0))
+	call i32 @puts(i8* getelementptr([46 x i8], [46 x i8]* @lcaic_failure, i32 0, i32 0))
 	call void @exit(i32 1)
 	unreachable
 }
 
 define i1 @test() nounwind {
 entry:
-	%tmp = load i1 ()** @funcPtr
+	%tmp = load i1 ()*, i1 ()** @funcPtr
 	%eq = icmp eq i1 ()* %tmp, @test
 	ret i1 %eq
 }
diff --git a/test/ExecutionEngine/MCJIT/test-common-symbols-alignment.ll b/test/ExecutionEngine/MCJIT/test-common-symbols-alignment.ll
index a425b5c1e9b3..1bb074498d4a 100644
--- a/test/ExecutionEngine/MCJIT/test-common-symbols-alignment.ll
+++ b/test/ExecutionEngine/MCJIT/test-common-symbols-alignment.ll
@@ -13,7 +13,7 @@ entry:
     %ptr = alloca i32, align 4
     store i32 0, i32* %retval
     store i32 ptrtoint (i32* @CS3 to i32), i32* %ptr, align 4
-    %0 = load i32* %ptr, align 4
+    %0 = load i32, i32* %ptr, align 4
     %and = and i32 %0, 15
     %tobool = icmp ne i32 %and, 0
     br i1 %tobool, label %if.then, label %if.else
@@ -27,6 +27,6 @@ if.else:                                          ; preds = %entry
     br label %return
 
 return:                                           ; preds = %if.else, %if.then
-    %1 = load i32* %retval
+    %1 = load i32, i32* %retval
     ret i32 %1
 }
diff --git a/test/ExecutionEngine/MCJIT/test-common-symbols.ll b/test/ExecutionEngine/MCJIT/test-common-symbols.ll
index 19e2ce584689..b63c2fea6752 100644
--- a/test/ExecutionEngine/MCJIT/test-common-symbols.ll
+++ b/test/ExecutionEngine/MCJIT/test-common-symbols.ll
@@ -31,20 +31,20 @@ entry:
   %retval = alloca i32, align 4
   %i = alloca i32, align 4
   store i32 0, i32* %retval
-  %0 = load i32* @zero_int, align 4
+  %0 = load i32, i32* @zero_int, align 4
   %add = add nsw i32 %0, 5
   %idxprom = sext i32 %add to i64
-  %arrayidx = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom
+  %arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom
   store i32 40, i32* %arrayidx, align 4
-  %1 = load double* @zero_double, align 8
+  %1 = load double, double* @zero_double, align 8
   %cmp = fcmp olt double %1, 1.000000e+00
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %2 = load i32* @zero_int, align 4
+  %2 = load i32, i32* @zero_int, align 4
   %add1 = add nsw i32 %2, 2
   %idxprom2 = sext i32 %add1 to i64
-  %arrayidx3 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom2
+  %arrayidx3 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom2
   store i32 70, i32* %arrayidx3, align 4
   br label %if.end
 
@@ -53,35 +53,35 @@ if.end:                                           ; preds = %if.then, %entry
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %if.end
-  %3 = load i32* %i, align 4
+  %3 = load i32, i32* %i, align 4
   %cmp4 = icmp slt i32 %3, 10
   br i1 %cmp4, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %sub = sub nsw i32 %4, 1
   %idxprom5 = sext i32 %sub to i64
-  %arrayidx6 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom5
-  %5 = load i32* %arrayidx6, align 4
-  %6 = load i32* %i, align 4
+  %arrayidx6 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom5
+  %5 = load i32, i32* %arrayidx6, align 4
+  %6 = load i32, i32* %i, align 4
   %idxprom7 = sext i32 %6 to i64
-  %arrayidx8 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom7
-  %7 = load i32* %arrayidx8, align 4
+  %arrayidx8 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom7
+  %7 = load i32, i32* %arrayidx8, align 4
   %add9 = add nsw i32 %5, %7
-  %8 = load i32* %i, align 4
+  %8 = load i32, i32* %i, align 4
   %idxprom10 = sext i32 %8 to i64
-  %arrayidx11 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom10
+  %arrayidx11 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom10
   store i32 %add9, i32* %arrayidx11, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %9 = load i32* %i, align 4
+  %9 = load i32, i32* %i, align 4
   %inc = add nsw i32 %9, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %10 = load i32* getelementptr inbounds ([10 x i32]* @zero_arr, i32 0, i64 9), align 4
+  %10 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @zero_arr, i32 0, i64 9), align 4
   %cmp12 = icmp eq i32 %10, 110
   %cond = select i1 %cmp12, i32 0, i32 -1
   ret i32 %cond
diff --git a/test/ExecutionEngine/MCJIT/test-fp-no-external-funcs.ll b/test/ExecutionEngine/MCJIT/test-fp-no-external-funcs.ll
index adb0550a72d7..c549a4465979 100644
--- a/test/ExecutionEngine/MCJIT/test-fp-no-external-funcs.ll
+++ b/test/ExecutionEngine/MCJIT/test-fp-no-external-funcs.ll
@@ -1,7 +1,7 @@
 ; RUN: %lli %s > /dev/null
 
 define double @test(double* %DP, double %Arg) {
-	%D = load double* %DP		; <double> [#uses=1]
+	%D = load double, double* %DP		; <double> [#uses=1]
 	%V = fadd double %D, 1.000000e+00		; <double> [#uses=2]
 	%W = fsub double %V, %V		; <double> [#uses=3]
 	%X = fmul double %W, %W		; <double> [#uses=2]
diff --git a/test/ExecutionEngine/MCJIT/test-fp.ll b/test/ExecutionEngine/MCJIT/test-fp.ll
index 2bf0210d8b00..c65b5a6e96a2 100644
--- a/test/ExecutionEngine/MCJIT/test-fp.ll
+++ b/test/ExecutionEngine/MCJIT/test-fp.ll
@@ -1,7 +1,7 @@
 ; RUN: %lli %s > /dev/null
 
 define double @test(double* %DP, double %Arg) {
-	%D = load double* %DP		; <double> [#uses=1]
+	%D = load double, double* %DP		; <double> [#uses=1]
 	%V = fadd double %D, 1.000000e+00		; <double> [#uses=2]
 	%W = fsub double %V, %V		; <double> [#uses=3]
 	%X = fmul double %W, %W		; <double> [#uses=2]
diff --git a/test/ExecutionEngine/MCJIT/test-global-ctors.ll b/test/ExecutionEngine/MCJIT/test-global-ctors.ll
index ec87d155d41b..6d132716d7d8 100644
--- a/test/ExecutionEngine/MCJIT/test-global-ctors.ll
+++ b/test/ExecutionEngine/MCJIT/test-global-ctors.ll
@@ -6,7 +6,7 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @var, align 4
+  %0 = load i32, i32* @var, align 4
   ret i32 %0
 }
 
diff --git a/test/ExecutionEngine/MCJIT/test-global-init-nonzero-sm-pic.ll b/test/ExecutionEngine/MCJIT/test-global-init-nonzero-sm-pic.ll
index 26bd83808026..8ae496d0fab0 100644
--- a/test/ExecutionEngine/MCJIT/test-global-init-nonzero-sm-pic.ll
+++ b/test/ExecutionEngine/MCJIT/test-global-init-nonzero-sm-pic.ll
@@ -12,24 +12,24 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 49
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* @count, align 4
+  %1 = load i32, i32* @count, align 4
   %inc = add nsw i32 %1, 1
   store i32 %inc, i32* @count, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %2 = load i32* %i, align 4
+  %2 = load i32, i32* %i, align 4
   %inc1 = add nsw i32 %2, 1
   store i32 %inc1, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %3 = load i32* @count, align 4
+  %3 = load i32, i32* @count, align 4
   %sub = sub nsw i32 %3, 50
   ret i32 %sub
 }
diff --git a/test/ExecutionEngine/MCJIT/test-global-init-nonzero.ll b/test/ExecutionEngine/MCJIT/test-global-init-nonzero.ll
index 3877e9a58861..4595219fd247 100644
--- a/test/ExecutionEngine/MCJIT/test-global-init-nonzero.ll
+++ b/test/ExecutionEngine/MCJIT/test-global-init-nonzero.ll
@@ -11,24 +11,24 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 49
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* @count, align 4
+  %1 = load i32, i32* @count, align 4
   %inc = add nsw i32 %1, 1
   store i32 %inc, i32* @count, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %2 = load i32* %i, align 4
+  %2 = load i32, i32* %i, align 4
   %inc1 = add nsw i32 %2, 1
   store i32 %inc1, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %3 = load i32* @count, align 4
+  %3 = load i32, i32* @count, align 4
   %sub = sub nsw i32 %3, 50
   ret i32 %sub
 }
diff --git a/test/ExecutionEngine/MCJIT/test-global.ll b/test/ExecutionEngine/MCJIT/test-global.ll
index 69e545555649..2760ecd03e15 100644
--- a/test/ExecutionEngine/MCJIT/test-global.ll
+++ b/test/ExecutionEngine/MCJIT/test-global.ll
@@ -11,24 +11,24 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 50
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* @count, align 4
+  %1 = load i32, i32* @count, align 4
   %inc = add nsw i32 %1, 1
   store i32 %inc, i32* @count, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %2 = load i32* %i, align 4
+  %2 = load i32, i32* %i, align 4
   %inc1 = add nsw i32 %2, 1
   store i32 %inc1, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %3 = load i32* @count, align 4
+  %3 = load i32, i32* @count, align 4
   %sub = sub nsw i32 %3, 50
   ret i32 %sub
 }
diff --git a/test/ExecutionEngine/MCJIT/test-loadstore.ll b/test/ExecutionEngine/MCJIT/test-loadstore.ll
index 1797599a9d8d..68c85050f0ba 100644
--- a/test/ExecutionEngine/MCJIT/test-loadstore.ll
+++ b/test/ExecutionEngine/MCJIT/test-loadstore.ll
@@ -1,13 +1,13 @@
 ; RUN: %lli %s > /dev/null
 
 define void @test(i8* %P, i16* %P.upgrd.1, i32* %P.upgrd.2, i64* %P.upgrd.3) {
-	%V = load i8* %P		; <i8> [#uses=1]
+	%V = load i8, i8* %P		; <i8> [#uses=1]
 	store i8 %V, i8* %P
-	%V.upgrd.4 = load i16* %P.upgrd.1		; <i16> [#uses=1]
+	%V.upgrd.4 = load i16, i16* %P.upgrd.1		; <i16> [#uses=1]
 	store i16 %V.upgrd.4, i16* %P.upgrd.1
-	%V.upgrd.5 = load i32* %P.upgrd.2		; <i32> [#uses=1]
+	%V.upgrd.5 = load i32, i32* %P.upgrd.2		; <i32> [#uses=1]
 	store i32 %V.upgrd.5, i32* %P.upgrd.2
-	%V.upgrd.6 = load i64* %P.upgrd.3		; <i64> [#uses=1]
+	%V.upgrd.6 = load i64, i64* %P.upgrd.3		; <i64> [#uses=1]
 	store i64 %V.upgrd.6, i64* %P.upgrd.3
 	ret void
 }
@@ -16,7 +16,7 @@ define i32 @varalloca(i32 %Size) {
         ;; Variable sized alloca
 	%X = alloca i32, i32 %Size		; <i32*> [#uses=2]
 	store i32 %Size, i32* %X
-	%Y = load i32* %X		; <i32> [#uses=1]
+	%Y = load i32, i32* %X		; <i32> [#uses=1]
 	ret i32 %Y
 }
 
diff --git a/test/ExecutionEngine/MCJIT/test-local.ll b/test/ExecutionEngine/MCJIT/test-local.ll
index ec5ba165408f..832e178de153 100644
--- a/test/ExecutionEngine/MCJIT/test-local.ll
+++ b/test/ExecutionEngine/MCJIT/test-local.ll
@@ -11,24 +11,24 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 50
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %count, align 4
+  %1 = load i32, i32* %count, align 4
   %inc = add nsw i32 %1, 1
   store i32 %inc, i32* %count, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %2 = load i32* %i, align 4
+  %2 = load i32, i32* %i, align 4
   %inc1 = add nsw i32 %2, 1
   store i32 %inc1, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %3 = load i32* %count, align 4
+  %3 = load i32, i32* %count, align 4
   %sub = sub nsw i32 %3, 50
   ret i32 %sub
 }
diff --git a/test/ExecutionEngine/MCJIT/test-ptr-reloc-sm-pic.ll b/test/ExecutionEngine/MCJIT/test-ptr-reloc-sm-pic.ll
index 21bcaef3aa80..d50ba9dd5a0a 100644
--- a/test/ExecutionEngine/MCJIT/test-ptr-reloc-sm-pic.ll
+++ b/test/ExecutionEngine/MCJIT/test-ptr-reloc-sm-pic.ll
@@ -2,14 +2,14 @@
 ; XFAIL: mips, aarch64, arm, i686, i386
 
 @.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
-@ptr = global i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), align 4
+@ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
 @.str1 = private unnamed_addr constant [6 x i8] c"data2\00", align 1
-@ptr2 = global i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0), align 4
+@ptr2 = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), align 4
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly {
 entry:
-  %0 = load i8** @ptr, align 4
-  %1 = load i8** @ptr2, align 4
+  %0 = load i8*, i8** @ptr, align 4
+  %1 = load i8*, i8** @ptr2, align 4
   %cmp = icmp eq i8* %0, %1
   %. = zext i1 %cmp to i32
   ret i32 %.
diff --git a/test/ExecutionEngine/MCJIT/test-ptr-reloc.ll b/test/ExecutionEngine/MCJIT/test-ptr-reloc.ll
index f139ddf12f81..9cb427414ec1 100644
--- a/test/ExecutionEngine/MCJIT/test-ptr-reloc.ll
+++ b/test/ExecutionEngine/MCJIT/test-ptr-reloc.ll
@@ -1,14 +1,14 @@
 ; RUN: %lli -O0 %s
 
 @.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
-@ptr = global i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), align 4
+@ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
 @.str1 = private unnamed_addr constant [6 x i8] c"data2\00", align 1
-@ptr2 = global i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0), align 4
+@ptr2 = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), align 4
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly {
 entry:
-  %0 = load i8** @ptr, align 4
-  %1 = load i8** @ptr2, align 4
+  %0 = load i8*, i8** @ptr, align 4
+  %1 = load i8*, i8** @ptr2, align 4
   %cmp = icmp eq i8* %0, %1
   %. = zext i1 %cmp to i32
   ret i32 %.
diff --git a/test/ExecutionEngine/OrcLazy/anonymous_globals.ll b/test/ExecutionEngine/OrcLazy/anonymous_globals.ll
new file mode 100644
index 000000000000..c4c09a0d5a25
--- /dev/null
+++ b/test/ExecutionEngine/OrcLazy/anonymous_globals.ll
@@ -0,0 +1,18 @@
+; RUN: lli -jit-kind=orc-lazy %s
+
+define private void @0() {
+entry:
+  ret void
+}
+
+define private void @"\01L_foo"() {
+entry:
+  ret void
+}
+
+define i32 @main(i32 %argc, i8** nocapture readnone %argv) {
+entry:
+  call void @0()
+  tail call void @"\01L_foo"()
+  ret i32 0
+}
diff --git a/test/ExecutionEngine/OrcLazy/hello.ll b/test/ExecutionEngine/OrcLazy/hello.ll
new file mode 100644
index 000000000000..c3cf0f346a1d
--- /dev/null
+++ b/test/ExecutionEngine/OrcLazy/hello.ll
@@ -0,0 +1,35 @@
+; RUN: lli -jit-kind=orc-lazy -orc-lazy-debug=funcs-to-stdout %s | FileCheck %s
+;
+; CHECK: Hello
+; CHECK: [ {{.*}}main ]
+; CHECK: Goodbye
+
+%class.Foo = type { i8 }
+
+@f = global %class.Foo zeroinitializer, align 1
+@__dso_handle = external global i8
+@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @_GLOBAL__sub_I_hello.cpp, i8* null }]
+@str = private unnamed_addr constant [6 x i8] c"Hello\00"
+@str2 = private unnamed_addr constant [8 x i8] c"Goodbye\00"
+
+define linkonce_odr void @_ZN3FooD1Ev(%class.Foo* nocapture readnone %this) unnamed_addr align 2 {
+entry:
+  %puts.i = tail call i32 @puts(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @str2, i64 0, i64 0))
+  ret void
+}
+
+declare i32 @__cxa_atexit(void (i8*)*, i8*, i8*)
+
+define i32 @main(i32 %argc, i8** nocapture readnone %argv) {
+entry:
+  ret i32 0
+}
+
+define internal void @_GLOBAL__sub_I_hello.cpp() {
+entry:
+  %puts.i.i.i = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @str, i64 0, i64 0))
+  %0 = tail call i32 @__cxa_atexit(void (i8*)* bitcast (void (%class.Foo*)* @_ZN3FooD1Ev to void (i8*)*), i8* getelementptr inbounds (%class.Foo, %class.Foo* @f, i64 0, i32 0), i8* @__dso_handle)
+  ret void
+}
+
+declare i32 @puts(i8* nocapture readonly)
diff --git a/test/ExecutionEngine/OrcLazy/lit.local.cfg b/test/ExecutionEngine/OrcLazy/lit.local.cfg
new file mode 100644
index 000000000000..bf63c4f73ed6
--- /dev/null
+++ b/test/ExecutionEngine/OrcLazy/lit.local.cfg
@@ -0,0 +1,2 @@
+if config.root.host_arch not in ['x86_64']:
+    config.unsupported = True
diff --git a/test/ExecutionEngine/OrcLazy/private_linkage.ll b/test/ExecutionEngine/OrcLazy/private_linkage.ll
new file mode 100644
index 000000000000..11813dd97760
--- /dev/null
+++ b/test/ExecutionEngine/OrcLazy/private_linkage.ll
@@ -0,0 +1,12 @@
+; RUN: lli -jit-kind=orc-lazy %s
+
+define private void @_ZL3foov() {
+entry:
+  ret void
+}
+
+define i32 @main(i32 %argc, i8** nocapture readnone %argv) {
+entry:
+  tail call void @_ZL3foov()
+  ret i32 0
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/2002-12-16-ArgTest.ll b/test/ExecutionEngine/OrcMCJIT/2002-12-16-ArgTest.ll
new file mode 100644
index 000000000000..825892e9fbdd
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2002-12-16-ArgTest.ll
@@ -0,0 +1,37 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+@.LC0 = internal global [10 x i8] c"argc: %d\0A\00"		; <[10 x i8]*> [#uses=1]
+
+declare i32 @puts(i8*)
+
+define void @getoptions(i32* %argc) {
+bb0:
+	ret void
+}
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main(i32 %argc, i8** %argv) {
+bb0:
+	call i32 (i8*, ...) @printf( i8* getelementptr ([10 x i8], [10 x i8]* @.LC0, i64 0, i64 0), i32 %argc )		; <i32>:0 [#uses=0]
+	%cast224 = bitcast i8** %argv to i8*		; <i8*> [#uses=1]
+	%local = alloca i8*		; <i8**> [#uses=3]
+	store i8* %cast224, i8** %local
+	%cond226 = icmp sle i32 %argc, 0		; <i1> [#uses=1]
+	br i1 %cond226, label %bb3, label %bb2
+bb2:		; preds = %bb2, %bb0
+	%cann-indvar = phi i32 [ 0, %bb0 ], [ %add1-indvar, %bb2 ]		; <i32> [#uses=2]
+	%add1-indvar = add i32 %cann-indvar, 1		; <i32> [#uses=2]
+	%cann-indvar-idxcast = sext i32 %cann-indvar to i64		; <i64> [#uses=1]
+	%CT = bitcast i8** %local to i8***		; <i8***> [#uses=1]
+	%reg115 = load i8**, i8*** %CT		; <i8**> [#uses=1]
+	%cast235 = getelementptr i8*, i8** %reg115, i64 %cann-indvar-idxcast		; <i8**> [#uses=1]
+	%reg117 = load i8*, i8** %cast235		; <i8*> [#uses=1]
+	%reg236 = call i32 @puts( i8* %reg117 )		; <i32> [#uses=0]
+	%cond239 = icmp slt i32 %add1-indvar, %argc		; <i1> [#uses=1]
+	br i1 %cond239, label %bb2, label %bb3
+bb3:		; preds = %bb2, %bb0
+	%cast243 = bitcast i8** %local to i32*		; <i32*> [#uses=1]
+	call void @getoptions( i32* %cast243 )
+	ret i32 0
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/2003-01-04-ArgumentBug.ll b/test/ExecutionEngine/OrcMCJIT/2003-01-04-ArgumentBug.ll
new file mode 100644
index 000000000000..2061329f2521
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2003-01-04-ArgumentBug.ll
@@ -0,0 +1,13 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @foo(i32 %X, i32 %Y, double %A) {
+	%cond212 = fcmp une double %A, 1.000000e+00		; <i1> [#uses=1]
+	%cast110 = zext i1 %cond212 to i32		; <i32> [#uses=1]
+	ret i32 %cast110
+}
+
+define i32 @main() {
+	%reg212 = call i32 @foo( i32 0, i32 1, double 1.000000e+00 )		; <i32> [#uses=1]
+	ret i32 %reg212
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/2003-01-04-LoopTest.ll b/test/ExecutionEngine/OrcMCJIT/2003-01-04-LoopTest.ll
new file mode 100644
index 000000000000..a298172e6780
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2003-01-04-LoopTest.ll
@@ -0,0 +1,20 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @main() {
+	call i32 @mylog( i32 4 )		; <i32>:1 [#uses=0]
+	ret i32 0
+}
+
+define internal i32 @mylog(i32 %num) {
+bb0:
+	br label %bb2
+bb2:		; preds = %bb2, %bb0
+	%reg112 = phi i32 [ 10, %bb2 ], [ 1, %bb0 ]		; <i32> [#uses=1]
+	%cann-indvar = phi i32 [ %cann-indvar, %bb2 ], [ 0, %bb0 ]		; <i32> [#uses=1]
+	%reg114 = add i32 %reg112, 1		; <i32> [#uses=2]
+	%cond222 = icmp slt i32 %reg114, %num		; <i1> [#uses=1]
+	br i1 %cond222, label %bb2, label %bb3
+bb3:		; preds = %bb2
+	ret i32 %reg114
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/2003-01-04-PhiTest.ll b/test/ExecutionEngine/OrcMCJIT/2003-01-04-PhiTest.ll
new file mode 100644
index 000000000000..a24e188438fb
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2003-01-04-PhiTest.ll
@@ -0,0 +1,12 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @main() {
+; <label>:0
+	br label %Loop
+Loop:		; preds = %Loop, %0
+	%X = phi i32 [ 0, %0 ], [ 1, %Loop ]		; <i32> [#uses=1]
+	br i1 true, label %Out, label %Loop
+Out:		; preds = %Loop
+	ret i32 %X
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/2003-01-09-SARTest.ll b/test/ExecutionEngine/OrcMCJIT/2003-01-09-SARTest.ll
new file mode 100644
index 000000000000..8f79ff2a683a
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2003-01-09-SARTest.ll
@@ -0,0 +1,11 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+; We were accidentally inverting the signedness of right shifts.  Whoops.
+
+define i32 @main() {
+	%X = ashr i32 -1, 16		; <i32> [#uses=1]
+	%Y = ashr i32 %X, 16		; <i32> [#uses=1]
+	%Z = add i32 %Y, 1		; <i32> [#uses=1]
+	ret i32 %Z
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/2003-01-10-FUCOM.ll b/test/ExecutionEngine/OrcMCJIT/2003-01-10-FUCOM.ll
new file mode 100644
index 000000000000..7e2ce669a7e2
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2003-01-10-FUCOM.ll
@@ -0,0 +1,10 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @main() {
+	%X = fadd double 0.000000e+00, 1.000000e+00		; <double> [#uses=1]
+	%Y = fsub double 0.000000e+00, 1.000000e+00		; <double> [#uses=2]
+	%Z = fcmp oeq double %X, %Y		; <i1> [#uses=0]
+	fadd double %Y, 0.000000e+00		; <double>:1 [#uses=0]
+	ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/2003-01-15-AlignmentTest.ll b/test/ExecutionEngine/OrcMCJIT/2003-01-15-AlignmentTest.ll
new file mode 100644
index 000000000000..38d5f83af038
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2003-01-15-AlignmentTest.ll
@@ -0,0 +1,17 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @bar(i8* %X) {
+        ; pointer should be 4 byte aligned!
+	%P = alloca double		; <double*> [#uses=1]
+	%R = ptrtoint double* %P to i32		; <i32> [#uses=1]
+	%A = and i32 %R, 3		; <i32> [#uses=1]
+	ret i32 %A
+}
+
+define i32 @main() {
+	%SP = alloca i8		; <i8*> [#uses=1]
+	%X = add i32 0, 0		; <i32> [#uses=1]
+	alloca i8, i32 %X		; <i8*>:1 [#uses=0]
+	call i32 @bar( i8* %SP )		; <i32>:2 [#uses=1]
+	ret i32 %2
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/2003-05-06-LivenessClobber.ll b/test/ExecutionEngine/OrcMCJIT/2003-05-06-LivenessClobber.ll
new file mode 100644
index 000000000000..82bf97d2a929
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2003-05-06-LivenessClobber.ll
@@ -0,0 +1,19 @@
+; This testcase should return with an exit code of 1.
+;
+; RUN: not %lli -jit-kind=orc-mcjit %s
+
+@test = global i64 0		; <i64*> [#uses=1]
+
+define internal i64 @test.upgrd.1() {
+	%tmp.0 = load i64, i64* @test		; <i64> [#uses=1]
+	%tmp.1 = add i64 %tmp.0, 1		; <i64> [#uses=1]
+	ret i64 %tmp.1
+}
+
+define i32 @main() {
+	%L = call i64 @test.upgrd.1( )		; <i64> [#uses=1]
+	%I = trunc i64 %L to i32		; <i32> [#uses=1]
+	ret i32 %I
+}
+
+
diff --git a/test/ExecutionEngine/OrcMCJIT/2003-05-07-ArgumentTest.ll b/test/ExecutionEngine/OrcMCJIT/2003-05-07-ArgumentTest.ll
new file mode 100644
index 000000000000..43e9ec956b24
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2003-05-07-ArgumentTest.ll
@@ -0,0 +1,11 @@
+; RUN: %lli -jit-kind=orc-mcjit %s test
+
+declare i32 @puts(i8*)
+
+define i32 @main(i32 %argc.1, i8** %argv.1) {
+	%tmp.5 = getelementptr i8*, i8** %argv.1, i64 1		; <i8**> [#uses=1]
+	%tmp.6 = load i8*, i8** %tmp.5		; <i8*> [#uses=1]
+	%tmp.0 = call i32 @puts( i8* %tmp.6 )		; <i32> [#uses=0]
+	ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/2003-05-11-PHIRegAllocBug.ll b/test/ExecutionEngine/OrcMCJIT/2003-05-11-PHIRegAllocBug.ll
new file mode 100644
index 000000000000..47988b9c0f05
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2003-05-11-PHIRegAllocBug.ll
@@ -0,0 +1,13 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @main() {
+entry:
+	br label %endif
+then:		; No predecessors!
+	br label %endif
+endif:		; preds = %then, %entry
+	%x = phi i32 [ 4, %entry ], [ 27, %then ]		; <i32> [#uses=0]
+	%result = phi i32 [ 32, %then ], [ 0, %entry ]		; <i32> [#uses=0]
+	ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/2003-06-04-bzip2-bug.ll b/test/ExecutionEngine/OrcMCJIT/2003-06-04-bzip2-bug.ll
new file mode 100644
index 000000000000..942b8362c700
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2003-06-04-bzip2-bug.ll
@@ -0,0 +1,17 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+; Testcase distilled from 256.bzip2.
+
+define i32 @main() {
+entry:
+	br label %loopentry.0
+loopentry.0:		; preds = %loopentry.0, %entry
+	%h.0 = phi i32 [ %tmp.2, %loopentry.0 ], [ -1, %entry ]		; <i32> [#uses=1]
+	%tmp.2 = add i32 %h.0, 1		; <i32> [#uses=3]
+	%tmp.4 = icmp ne i32 %tmp.2, 0		; <i1> [#uses=1]
+	br i1 %tmp.4, label %loopentry.0, label %loopentry.1
+loopentry.1:		; preds = %loopentry.0
+	%h.1 = phi i32 [ %tmp.2, %loopentry.0 ]		; <i32> [#uses=1]
+	ret i32 %h.1
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/2003-06-05-PHIBug.ll b/test/ExecutionEngine/OrcMCJIT/2003-06-05-PHIBug.ll
new file mode 100644
index 000000000000..07bcbbde12d1
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2003-06-05-PHIBug.ll
@@ -0,0 +1,15 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+; Testcase distilled from 256.bzip2.
+
+define i32 @main() {
+entry:
+	%X = add i32 1, -1		; <i32> [#uses=3]
+	br label %Next
+Next:		; preds = %entry
+	%A = phi i32 [ %X, %entry ]		; <i32> [#uses=0]
+	%B = phi i32 [ %X, %entry ]		; <i32> [#uses=0]
+	%C = phi i32 [ %X, %entry ]		; <i32> [#uses=1]
+	ret i32 %C
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/2003-08-15-AllocaAssertion.ll b/test/ExecutionEngine/OrcMCJIT/2003-08-15-AllocaAssertion.ll
new file mode 100644
index 000000000000..43c26b7e1a09
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2003-08-15-AllocaAssertion.ll
@@ -0,0 +1,11 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+; This testcase failed to work because two variable sized allocas confused the
+; local register allocator.
+
+define i32 @main(i32 %X) {
+	%A = alloca i32, i32 %X		; <i32*> [#uses=0]
+	%B = alloca float, i32 %X		; <float*> [#uses=0]
+	ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/2003-08-21-EnvironmentTest.ll b/test/ExecutionEngine/OrcMCJIT/2003-08-21-EnvironmentTest.ll
new file mode 100644
index 000000000000..88dd46e2d631
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2003-08-21-EnvironmentTest.ll
@@ -0,0 +1,21 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+;
+; Regression Test: EnvironmentTest.ll
+;
+; Description:
+;	This is a regression test that verifies that the JIT passes the
+;	environment to the main() function.
+;
+
+
+declare i32 @strlen(i8*)
+
+define i32 @main(i32 %argc.1, i8** %argv.1, i8** %envp.1) {
+	%tmp.2 = load i8*, i8** %envp.1		; <i8*> [#uses=1]
+	%tmp.3 = call i32 @strlen( i8* %tmp.2 )		; <i32> [#uses=1]
+	%T = icmp eq i32 %tmp.3, 0		; <i1> [#uses=1]
+	%R = zext i1 %T to i32		; <i32> [#uses=1]
+	ret i32 %R
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/2003-08-23-RegisterAllocatePhysReg.ll b/test/ExecutionEngine/OrcMCJIT/2003-08-23-RegisterAllocatePhysReg.ll
new file mode 100644
index 000000000000..fc3734f151df
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2003-08-23-RegisterAllocatePhysReg.ll
@@ -0,0 +1,34 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+; This testcase exposes a bug in the local register allocator where it runs out
+; of registers (due to too many overlapping live ranges), but then attempts to
+; use the ESP register (which is not allocatable) to hold a value.
+
+define i32 @main(i32 %A) {
+        ; ESP gets used again...
+	%Ap2 = alloca i32, i32 %A		; <i32*> [#uses=11]
+	; Produce lots of overlapping live ranges
+        %B = add i32 %A, 1		; <i32> [#uses=1]
+	%C = add i32 %A, 2		; <i32> [#uses=1]
+	%D = add i32 %A, 3		; <i32> [#uses=1]
+	%E = add i32 %A, 4		; <i32> [#uses=1]
+	%F = add i32 %A, 5		; <i32> [#uses=1]
+	%G = add i32 %A, 6		; <i32> [#uses=1]
+	%H = add i32 %A, 7		; <i32> [#uses=1]
+	%I = add i32 %A, 8		; <i32> [#uses=1]
+	%J = add i32 %A, 9		; <i32> [#uses=1]
+	%K = add i32 %A, 10		; <i32> [#uses=1]
+        ; Uses of all of the values
+	store i32 %A, i32* %Ap2
+	store i32 %B, i32* %Ap2
+	store i32 %C, i32* %Ap2
+	store i32 %D, i32* %Ap2
+	store i32 %E, i32* %Ap2
+	store i32 %F, i32* %Ap2
+	store i32 %G, i32* %Ap2
+	store i32 %H, i32* %Ap2
+	store i32 %I, i32* %Ap2
+	store i32 %J, i32* %Ap2
+	store i32 %K, i32* %Ap2
+	ret i32 0
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll b/test/ExecutionEngine/OrcMCJIT/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll
new file mode 100644
index 000000000000..4e38184afe45
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll
@@ -0,0 +1,23 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+@A = global i32 0		; <i32*> [#uses=1]
+
+define i32 @main() {
+	%Ret = call i32 @test( i1 true, i32 0 )		; <i32> [#uses=1]
+	ret i32 %Ret
+}
+
+define i32 @test(i1 %c, i32 %A) {
+	br i1 %c, label %Taken1, label %NotTaken
+Cont:		; preds = %Taken1, %NotTaken
+	%V = phi i32 [ 0, %NotTaken ], [ sub (i32 ptrtoint (i32* @A to i32), i32 1234), %Taken1 ]		; <i32> [#uses=0]
+	ret i32 0
+NotTaken:		; preds = %0
+	br label %Cont
+Taken1:		; preds = %0
+	%B = icmp eq i32 %A, 0		; <i1> [#uses=1]
+	br i1 %B, label %Cont, label %ExitError
+ExitError:		; preds = %Taken1
+	ret i32 12
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/2005-12-02-TailCallBug.ll b/test/ExecutionEngine/OrcMCJIT/2005-12-02-TailCallBug.ll
new file mode 100644
index 000000000000..aff7fce9b06e
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2005-12-02-TailCallBug.ll
@@ -0,0 +1,22 @@
+; PR672
+; RUN: %lli -jit-kind=orc-mcjit %s
+; XFAIL: mcjit-ia32
+
+define i32 @main() {
+	%f = bitcast i32 (i32, i32*, i32)* @check_tail to i32*		; <i32*> [#uses=1]
+	%res = tail call fastcc i32 @check_tail( i32 10, i32* %f, i32 10 )		; <i32> [#uses=1]
+	ret i32 %res
+}
+
+define fastcc i32 @check_tail(i32 %x, i32* %f, i32 %g) {
+	%tmp1 = icmp sgt i32 %x, 0		; <i1> [#uses=1]
+	br i1 %tmp1, label %if-then, label %if-else
+if-then:		; preds = %0
+	%fun_ptr = bitcast i32* %f to i32 (i32, i32*, i32)*		; <i32 (i32, i32*, i32)*> [#uses=1]
+	%arg1 = add i32 %x, -1		; <i32> [#uses=1]
+	%res = tail call fastcc i32 %fun_ptr( i32 %arg1, i32* %f, i32 %g )		; <i32> [#uses=1]
+	ret i32 %res
+if-else:		; preds = %0
+	ret i32 %x
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/2007-12-10-APIntLoadStore.ll b/test/ExecutionEngine/OrcMCJIT/2007-12-10-APIntLoadStore.ll
new file mode 100644
index 000000000000..5bad45a587bf
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2007-12-10-APIntLoadStore.ll
@@ -0,0 +1,19 @@
+; RUN: %lli -jit-kind=orc-mcjit -force-interpreter %s
+; PR1836
+
+define i32 @main() {
+entry:
+    %retval = alloca i32        ; <i32*> [#uses=2]
+    %tmp = alloca i32       ; <i32*> [#uses=2]
+    %x = alloca i75, align 16       ; <i75*> [#uses=1]
+    %"alloca point" = bitcast i32 0 to i32      ; <i32> [#uses=0]
+    store i75 999, i75* %x, align 16
+    store i32 0, i32* %tmp, align 4
+    %tmp1 = load i32, i32* %tmp, align 4     ; <i32> [#uses=1]
+    store i32 %tmp1, i32* %retval, align 4
+    br label %return
+
+return:     ; preds = %entry
+    %retval2 = load i32, i32* %retval        ; <i32> [#uses=1]
+    ret i32 %retval2
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/2008-06-05-APInt-OverAShr.ll b/test/ExecutionEngine/OrcMCJIT/2008-06-05-APInt-OverAShr.ll
new file mode 100644
index 000000000000..f67ae6a24894
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2008-06-05-APInt-OverAShr.ll
@@ -0,0 +1,60 @@
+; RUN: %lli -jit-kind=orc-mcjit -force-interpreter=true %s | FileCheck %s
+; CHECK: 1
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i686-pc-linux-gnu"
+@.str = internal constant [10 x i8] c"MSB = %d\0A\00"		; <[10 x i8]*> [#uses=1]
+
+define i65 @foo(i65 %x) {
+entry:
+	%x_addr = alloca i65		; <i65*> [#uses=2]
+	%retval = alloca i65		; <i65*> [#uses=2]
+	%tmp = alloca i65		; <i65*> [#uses=2]
+	%"alloca point" = bitcast i65 0 to i65		; <i65> [#uses=0]
+	store i65 %x, i65* %x_addr
+	%tmp1 = load i65, i65* %x_addr, align 4		; <i65> [#uses=1]
+	%tmp2 = ashr i65 %tmp1, 65		; <i65> [#uses=1]
+	store i65 %tmp2, i65* %tmp, align 4
+	%tmp3 = load i65, i65* %tmp, align 4		; <i65> [#uses=1]
+	store i65 %tmp3, i65* %retval, align 4
+	br label %return
+
+return:		; preds = %entry
+	%retval4 = load i65, i65* %retval		; <i65> [#uses=1]
+	ret i65 %retval4
+}
+
+define i32 @main() {
+entry:
+	%retval = alloca i32		; <i32*> [#uses=1]
+	%iftmp.0 = alloca i32		; <i32*> [#uses=3]
+	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
+	%tmp = call i65 @foo( i65 -9 )		; <i65> [#uses=1]
+	%tmp1 = lshr i65 %tmp, 64		; <i65> [#uses=1]
+	%tmp2 = xor i65 %tmp1, 1		; <i65> [#uses=1]
+	%tmp3 = and i65 %tmp2, 1		; <i65> [#uses=1]
+	%tmp34 = trunc i65 %tmp3 to i8		; <i8> [#uses=1]
+	%toBool = icmp ne i8 %tmp34, 0		; <i1> [#uses=1]
+	br i1 %toBool, label %cond_true, label %cond_false
+
+cond_true:		; preds = %entry
+	store i32 0, i32* %iftmp.0, align 4
+	br label %cond_next
+
+cond_false:		; preds = %entry
+	store i32 1, i32* %iftmp.0, align 4
+	br label %cond_next
+
+cond_next:		; preds = %cond_false, %cond_true
+	%tmp5 = getelementptr [10 x i8], [10 x i8]* @.str, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp6 = load i32, i32* %iftmp.0, align 4		; <i32> [#uses=1]
+	%tmp7 = call i32 (i8*, ...) @printf( i8* noalias  %tmp5, i32 %tmp6 ) nounwind 		; <i32> [#uses=0]
+	br label %return
+
+return:		; preds = %cond_next
+    store i32 0, i32* %retval, align 4
+	%retval8 = load i32, i32* %retval		; <i32> [#uses=1]
+	ret i32 %retval8
+}
+
+declare i32 @printf(i8* noalias , ...) nounwind 
diff --git a/test/ExecutionEngine/OrcMCJIT/2013-04-04-RelocAddend.ll b/test/ExecutionEngine/OrcMCJIT/2013-04-04-RelocAddend.ll
new file mode 100644
index 000000000000..94ccf957c82e
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/2013-04-04-RelocAddend.ll
@@ -0,0 +1,25 @@
+; RUN: %lli -jit-kind=orc-mcjit %s
+;
+; Verify relocations to global symbols with addend work correctly.
+;
+; Compiled from this C code:
+;
+; int test[2] = { -1, 0 };
+; int *p = &test[1];
+; 
+; int main (void)
+; {
+;   return *p;
+; }
+; 
+
+@test = global [2 x i32] [i32 -1, i32 0], align 4
+@p = global i32* getelementptr inbounds ([2 x i32], [2 x i32]* @test, i64 0, i64 1), align 8
+
+define i32 @main() {
+entry:
+  %0 = load i32*, i32** @p, align 8
+  %1 = load i32, i32* %0, align 4
+  ret i32 %1
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/Inputs/cross-module-b.ll b/test/ExecutionEngine/OrcMCJIT/Inputs/cross-module-b.ll
new file mode 100644
index 000000000000..687011741103
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/Inputs/cross-module-b.ll
@@ -0,0 +1,7 @@
+declare i32 @FA()
+
+define i32 @FB() {
+  %r = call i32 @FA( )   ; <i32> [#uses=1]
+  ret i32 %r
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/Inputs/multi-module-b.ll b/test/ExecutionEngine/OrcMCJIT/Inputs/multi-module-b.ll
new file mode 100644
index 000000000000..103b601e7f08
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/Inputs/multi-module-b.ll
@@ -0,0 +1,7 @@
+declare i32 @FC()
+
+define i32 @FB() {
+  %r = call i32 @FC( )   ; <i32> [#uses=1]
+  ret i32 %r
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/Inputs/multi-module-c.ll b/test/ExecutionEngine/OrcMCJIT/Inputs/multi-module-c.ll
new file mode 100644
index 000000000000..b39306be9e3b
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/Inputs/multi-module-c.ll
@@ -0,0 +1,4 @@
+define i32 @FC() {
+  ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/Inputs/multi-module-eh-b.ll b/test/ExecutionEngine/OrcMCJIT/Inputs/multi-module-eh-b.ll
new file mode 100644
index 000000000000..d7dbb032b5d0
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/Inputs/multi-module-eh-b.ll
@@ -0,0 +1,30 @@
+declare i8* @__cxa_allocate_exception(i64)
+declare void @__cxa_throw(i8*, i8*, i8*)
+declare i32 @__gxx_personality_v0(...)
+declare void @__cxa_end_catch()
+declare i8* @__cxa_begin_catch(i8*)
+
+@_ZTIi = external constant i8*
+
+define void @throwException_B() {
+  %exception = tail call i8* @__cxa_allocate_exception(i64 4)
+  call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null)
+  unreachable
+}
+
+define i32 @FB() {
+entry:
+  invoke void @throwException_B()
+          to label %try.cont unwind label %lpad
+
+lpad:
+  %p = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %e = extractvalue { i8*, i32 } %p, 0
+  call i8* @__cxa_begin_catch(i8* %e)
+  call void @__cxa_end_catch()
+  br label %try.cont
+
+try.cont:
+  ret i32 0
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/cross-module-a.ll b/test/ExecutionEngine/OrcMCJIT/cross-module-a.ll
new file mode 100644
index 000000000000..451b2662ddf9
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/cross-module-a.ll
@@ -0,0 +1,13 @@
+; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/cross-module-b.ll %s > /dev/null
+
+declare i32 @FB()
+
+define i32 @FA() {
+  ret i32 0
+}
+
+define i32 @main() {
+  %r = call i32 @FB( )   ; <i32> [#uses=1]
+  ret i32 %r
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/cross-module-sm-pic-a.ll b/test/ExecutionEngine/OrcMCJIT/cross-module-sm-pic-a.ll
new file mode 100644
index 000000000000..4f5afd0ed475
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/cross-module-sm-pic-a.ll
@@ -0,0 +1,14 @@
+; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/cross-module-b.ll -relocation-model=pic -code-model=small %s > /dev/null
+; XFAIL: mips, i686, i386
+
+declare i32 @FB()
+
+define i32 @FA() {
+  ret i32 0
+}
+
+define i32 @main() {
+  %r = call i32 @FB( )   ; <i32> [#uses=1]
+  ret i32 %r
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/eh-lg-pic.ll b/test/ExecutionEngine/OrcMCJIT/eh-lg-pic.ll
new file mode 100644
index 000000000000..32b53c4847bc
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/eh-lg-pic.ll
@@ -0,0 +1,32 @@
+; RUN: %lli -jit-kind=orc-mcjit -relocation-model=pic -code-model=large %s
+; XFAIL: cygwin, win32, mingw, mips, i686, i386, aarch64, arm, asan, msan
+declare i8* @__cxa_allocate_exception(i64)
+declare void @__cxa_throw(i8*, i8*, i8*)
+declare i32 @__gxx_personality_v0(...)
+declare void @__cxa_end_catch()
+declare i8* @__cxa_begin_catch(i8*)
+
+@_ZTIi = external constant i8*
+
+define void @throwException() {
+  %exception = tail call i8* @__cxa_allocate_exception(i64 4)
+  call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null)
+  unreachable
+}
+
+define i32 @main() {
+entry:
+  invoke void @throwException()
+          to label %try.cont unwind label %lpad
+
+lpad:
+  %p = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %e = extractvalue { i8*, i32 } %p, 0
+  call i8* @__cxa_begin_catch(i8* %e)
+  call void @__cxa_end_catch()
+  br label %try.cont
+
+try.cont:
+  ret i32 0
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/eh-sm-pic.ll b/test/ExecutionEngine/OrcMCJIT/eh-sm-pic.ll
new file mode 100644
index 000000000000..a54795ead56d
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/eh-sm-pic.ll
@@ -0,0 +1,32 @@
+; RUN: %lli -jit-kind=orc-mcjit -relocation-model=pic -code-model=small %s
+; XFAIL: cygwin, win32, mingw, mips, i686, i386, darwin, aarch64, arm, asan, msan
+declare i8* @__cxa_allocate_exception(i64)
+declare void @__cxa_throw(i8*, i8*, i8*)
+declare i32 @__gxx_personality_v0(...)
+declare void @__cxa_end_catch()
+declare i8* @__cxa_begin_catch(i8*)
+
+@_ZTIi = external constant i8*
+
+define void @throwException() {
+  %exception = tail call i8* @__cxa_allocate_exception(i64 4)
+  call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null)
+  unreachable
+}
+
+define i32 @main() {
+entry:
+  invoke void @throwException()
+          to label %try.cont unwind label %lpad
+
+lpad:
+  %p = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %e = extractvalue { i8*, i32 } %p, 0
+  call i8* @__cxa_begin_catch(i8* %e)
+  call void @__cxa_end_catch()
+  br label %try.cont
+
+try.cont:
+  ret i32 0
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/eh.ll b/test/ExecutionEngine/OrcMCJIT/eh.ll
new file mode 100644
index 000000000000..2de6a517b2b3
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/eh.ll
@@ -0,0 +1,32 @@
+; RUN: %lli -jit-kind=orc-mcjit %s
+; XFAIL: arm, cygwin, win32, mingw, asan, msan
+declare i8* @__cxa_allocate_exception(i64)
+declare void @__cxa_throw(i8*, i8*, i8*)
+declare i32 @__gxx_personality_v0(...)
+declare void @__cxa_end_catch()
+declare i8* @__cxa_begin_catch(i8*)
+
+@_ZTIi = external constant i8*
+
+define void @throwException() {
+  %exception = tail call i8* @__cxa_allocate_exception(i64 4)
+  call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null)
+  unreachable
+}
+
+define i32 @main() {
+entry:
+  invoke void @throwException()
+          to label %try.cont unwind label %lpad
+
+lpad:
+  %p = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %e = extractvalue { i8*, i32 } %p, 0
+  call i8* @__cxa_begin_catch(i8* %e)
+  call void @__cxa_end_catch()
+  br label %try.cont
+
+try.cont:
+  ret i32 0
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/fpbitcast.ll b/test/ExecutionEngine/OrcMCJIT/fpbitcast.ll
new file mode 100644
index 000000000000..d2dbe316ad20
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/fpbitcast.ll
@@ -0,0 +1,21 @@
+; RUN: %lli -jit-kind=orc-mcjit -force-interpreter=true %s | FileCheck %s
+; CHECK: 40091eb8
+
+define i32 @test(double %x) {
+entry:
+	%x46.i = bitcast double %x to i64	
+	%tmp343.i = lshr i64 %x46.i, 32	
+	%tmp344.i = trunc i64 %tmp343.i to i32
+        ret i32 %tmp344.i
+}
+
+define i32 @main()
+{
+       %res = call i32 @test(double 3.14)
+       %ptr = getelementptr [4 x i8], [4 x i8]* @format, i32 0, i32 0
+       call i32 (i8*,...) @printf(i8* %ptr, i32 %res)
+       ret i32 0
+}
+
+declare i32 @printf(i8*, ...)
+@format = internal constant [4 x i8] c"%x\0A\00"
diff --git a/test/ExecutionEngine/OrcMCJIT/hello.ll b/test/ExecutionEngine/OrcMCJIT/hello.ll
new file mode 100644
index 000000000000..08413c2b5824
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/hello.ll
@@ -0,0 +1,11 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+@.LC0 = internal global [12 x i8] c"Hello World\00"		; <[12 x i8]*> [#uses=1]
+
+declare i32 @puts(i8*)
+
+define i32 @main() {
+	%reg210 = call i32 @puts( i8* getelementptr ([12 x i8], [12 x i8]* @.LC0, i64 0, i64 0) )		; <i32> [#uses=0]
+	ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/hello2.ll b/test/ExecutionEngine/OrcMCJIT/hello2.ll
new file mode 100644
index 000000000000..bb6a9cf12f7c
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/hello2.ll
@@ -0,0 +1,17 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+@X = global i32 7		; <i32*> [#uses=0]
+@msg = internal global [13 x i8] c"Hello World\0A\00"		; <[13 x i8]*> [#uses=1]
+
+declare void @printf([13 x i8]*, ...)
+
+define void @bar() {
+	call void ([13 x i8]*, ...) @printf( [13 x i8]* @msg )
+	ret void
+}
+
+define i32 @main() {
+	call void @bar( )
+	ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/lit.local.cfg b/test/ExecutionEngine/OrcMCJIT/lit.local.cfg
new file mode 100644
index 000000000000..f98140357736
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/lit.local.cfg
@@ -0,0 +1,26 @@
+root = config.root
+targets = root.targets
+if ('X86' in targets) | ('AArch64' in targets) | ('ARM' in targets) | \
+   ('Mips' in targets) | ('PowerPC' in targets) | ('SystemZ' in targets):
+    config.unsupported = False
+else:
+    config.unsupported = True
+
+# FIXME: autoconf and cmake produce different arch names. We should normalize
+# them before getting here.
+if root.host_arch not in ['i386', 'x86', 'x86_64', 'AMD64',
+                          'AArch64', 'ARM', 'Mips', 'PowerPC', 'ppc64', 'SystemZ']:
+    config.unsupported = True
+
+if 'armv7' in root.host_arch:
+    config.unsupported = False
+
+if 'i386-apple-darwin' in root.target_triple:
+    config.unsupported = True
+
+if 'powerpc' in root.target_triple and not 'powerpc64' in root.target_triple:
+    config.unsupported = True
+
+# ExecutionEngine tests are not expected to pass in a cross-compilation setup.
+if 'native' not in config.available_features:
+    config.unsupported = True
diff --git a/test/ExecutionEngine/OrcMCJIT/load-object-a.ll b/test/ExecutionEngine/OrcMCJIT/load-object-a.ll
new file mode 100644
index 000000000000..abd470df5473
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/load-object-a.ll
@@ -0,0 +1,24 @@
+; This first line will generate the .o files for the next run line
+; RUN: rm -rf %t.cachedir %t.cachedir2 %t.cachedir3
+; RUN: mkdir -p %t.cachedir %t.cachedir2 %t.cachedir3
+; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/multi-module-b.ll -extra-module=%p/Inputs/multi-module-c.ll -enable-cache-manager -object-cache-dir=%t.cachedir %s
+
+; Collect generated objects.
+; RUN: find %t.cachedir -type f -name 'multi-module-?.o' -exec mv -v '{}' %t.cachedir2 ';'
+
+; This line tests MCJIT object loading
+; RUN: %lli -jit-kind=orc-mcjit -extra-object=%t.cachedir2/multi-module-b.o -extra-object=%t.cachedir2/multi-module-c.o %s
+
+; These lines put the object files into an archive
+; RUN: llvm-ar r %t.cachedir3/load-object.a %t.cachedir2/multi-module-b.o
+; RUN: llvm-ar r %t.cachedir3/load-object.a %t.cachedir2/multi-module-c.o
+
+; This line test MCJIT archive loading
+; RUN: %lli -jit-kind=orc-mcjit -extra-archive=%t.cachedir3/load-object.a %s
+
+declare i32 @FB()
+
+define i32 @main() {
+  %r = call i32 @FB( )   ; <i32> [#uses=1]
+  ret i32 %r
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/multi-module-a.ll b/test/ExecutionEngine/OrcMCJIT/multi-module-a.ll
new file mode 100644
index 000000000000..d622efca03e5
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/multi-module-a.ll
@@ -0,0 +1,9 @@
+; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/multi-module-b.ll -extra-module=%p/Inputs/multi-module-c.ll %s > /dev/null
+
+declare i32 @FB()
+
+define i32 @main() {
+  %r = call i32 @FB( )   ; <i32> [#uses=1]
+  ret i32 %r
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/multi-module-eh-a.ll b/test/ExecutionEngine/OrcMCJIT/multi-module-eh-a.ll
new file mode 100644
index 000000000000..f77cb44a878f
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/multi-module-eh-a.ll
@@ -0,0 +1,35 @@
+; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/multi-module-eh-b.ll %s
+; XFAIL: arm, cygwin, win32, mingw, asan, msan
+declare i8* @__cxa_allocate_exception(i64)
+declare void @__cxa_throw(i8*, i8*, i8*)
+declare i32 @__gxx_personality_v0(...)
+declare void @__cxa_end_catch()
+declare i8* @__cxa_begin_catch(i8*)
+
+@_ZTIi = external constant i8*
+
+declare i32 @FB()
+
+define void @throwException() {
+  %exception = tail call i8* @__cxa_allocate_exception(i64 4)
+  call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null)
+  unreachable
+}
+
+define i32 @main() {
+entry:
+  invoke void @throwException()
+          to label %try.cont unwind label %lpad
+
+lpad:
+  %p = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %e = extractvalue { i8*, i32 } %p, 0
+  call i8* @__cxa_begin_catch(i8* %e)
+  call void @__cxa_end_catch()
+  br label %try.cont
+
+try.cont:
+  %r = call i32 @FB( )
+  ret i32 %r
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/multi-module-sm-pic-a.ll b/test/ExecutionEngine/OrcMCJIT/multi-module-sm-pic-a.ll
new file mode 100644
index 000000000000..80b8e163d5d6
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/multi-module-sm-pic-a.ll
@@ -0,0 +1,10 @@
+; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/multi-module-b.ll -extra-module=%p/Inputs/multi-module-c.ll -relocation-model=pic -code-model=small %s > /dev/null
+; XFAIL: mips, i686, i386
+
+declare i32 @FB()
+
+define i32 @main() {
+  %r = call i32 @FB( )   ; <i32> [#uses=1]
+  ret i32 %r
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/non-extern-addend.ll b/test/ExecutionEngine/OrcMCJIT/non-extern-addend.ll
new file mode 100644
index 000000000000..bb2f7e4d325e
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/non-extern-addend.ll
@@ -0,0 +1,21 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @foo(i32 %x, i32 %y, double %d) {
+entry:
+  %d.int64 = bitcast double %d to i64
+  %d.top64 = lshr i64 %d.int64, 32
+  %d.top   = trunc i64 %d.top64 to i32
+  %d.bottom = trunc i64 %d.int64 to i32
+  %topCorrect = icmp eq i32 %d.top, 3735928559
+  %bottomCorrect = icmp eq i32 %d.bottom, 4277009102
+  %right = and i1 %topCorrect, %bottomCorrect
+  %nRight = xor i1 %right, true
+  %retVal = zext i1 %nRight to i32
+  ret i32 %retVal
+}
+
+define i32 @main() {
+entry:
+  %call = call i32 @foo(i32 0, i32 1, double 0xDEADBEEFFEEDFACE)
+  ret i32 %call
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/pr13727.ll b/test/ExecutionEngine/OrcMCJIT/pr13727.ll
new file mode 100644
index 000000000000..a48c573ba28d
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/pr13727.ll
@@ -0,0 +1,88 @@
+; RUN: %lli -jit-kind=orc-mcjit -O0 -disable-lazy-compilation=false %s
+
+; The intention of this test is to verify that symbols mapped to COMMON in ELF
+; work as expected.
+;
+; Compiled from this C code:
+;
+; int zero_int;
+; double zero_double;
+; int zero_arr[10];
+; 
+; int main()
+; {
+;     zero_arr[zero_int + 5] = 40;
+; 
+;     if (zero_double < 1.1)
+;         zero_arr[zero_int + 2] = 70;
+; 
+;     for (int i = 1; i < 10; ++i) {
+;         zero_arr[i] = zero_arr[i - 1] + zero_arr[i];
+;     }
+;     return zero_arr[9] == 110 ? 0 : -1;
+; }
+
+@zero_int = common global i32 0, align 4
+@zero_arr = common global [10 x i32] zeroinitializer, align 16
+@zero_double = common global double 0.000000e+00, align 8
+
+define i32 @main() nounwind {
+entry:
+  %retval = alloca i32, align 4
+  %i = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32, i32* @zero_int, align 4
+  %add = add nsw i32 %0, 5
+  %idxprom = sext i32 %add to i64
+  %arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom
+  store i32 40, i32* %arrayidx, align 4
+  %1 = load double, double* @zero_double, align 8
+  %cmp = fcmp olt double %1, 1.100000e+00
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %2 = load i32, i32* @zero_int, align 4
+  %add1 = add nsw i32 %2, 2
+  %idxprom2 = sext i32 %add1 to i64
+  %arrayidx3 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom2
+  store i32 70, i32* %arrayidx3, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  store i32 1, i32* %i, align 4
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %if.end
+  %3 = load i32, i32* %i, align 4
+  %cmp4 = icmp slt i32 %3, 10
+  br i1 %cmp4, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %4 = load i32, i32* %i, align 4
+  %sub = sub nsw i32 %4, 1
+  %idxprom5 = sext i32 %sub to i64
+  %arrayidx6 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom5
+  %5 = load i32, i32* %arrayidx6, align 4
+  %6 = load i32, i32* %i, align 4
+  %idxprom7 = sext i32 %6 to i64
+  %arrayidx8 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom7
+  %7 = load i32, i32* %arrayidx8, align 4
+  %add9 = add nsw i32 %5, %7
+  %8 = load i32, i32* %i, align 4
+  %idxprom10 = sext i32 %8 to i64
+  %arrayidx11 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom10
+  store i32 %add9, i32* %arrayidx11, align 4
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body
+  %9 = load i32, i32* %i, align 4
+  %inc = add nsw i32 %9, 1
+  store i32 %inc, i32* %i, align 4
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  %10 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @zero_arr, i32 0, i64 9), align 4
+  %cmp12 = icmp eq i32 %10, 110
+  %cond = select i1 %cmp12, i32 0, i32 -1
+  ret i32 %cond
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/Inputs/cross-module-b.ll b/test/ExecutionEngine/OrcMCJIT/remote/Inputs/cross-module-b.ll
new file mode 100644
index 000000000000..bc13b1de8ef6
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/Inputs/cross-module-b.ll
@@ -0,0 +1,7 @@
+declare i32 @FA()
+
+define i32 @FB() nounwind {
+  %r = call i32 @FA( )   ; <i32> [#uses=1]
+  ret i32 %r
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/Inputs/multi-module-b.ll b/test/ExecutionEngine/OrcMCJIT/remote/Inputs/multi-module-b.ll
new file mode 100644
index 000000000000..0b8d5eb37adb
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/Inputs/multi-module-b.ll
@@ -0,0 +1,7 @@
+declare i32 @FC()
+
+define i32 @FB() nounwind {
+  %r = call i32 @FC( )   ; <i32> [#uses=1]
+  ret i32 %r
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/Inputs/multi-module-c.ll b/test/ExecutionEngine/OrcMCJIT/remote/Inputs/multi-module-c.ll
new file mode 100644
index 000000000000..98350a8c106e
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/Inputs/multi-module-c.ll
@@ -0,0 +1,4 @@
+define i32 @FC() nounwind {
+  ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/cross-module-a.ll b/test/ExecutionEngine/OrcMCJIT/remote/cross-module-a.ll
new file mode 100644
index 000000000000..16553ebd2ade
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/cross-module-a.ll
@@ -0,0 +1,12 @@
+; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/cross-module-b.ll -disable-lazy-compilation=true -remote-mcjit -mcjit-remote-process=lli-child-target%exeext %s > /dev/null
+
+declare i32 @FB()
+
+define i32 @FA() nounwind {
+  ret i32 0
+}
+
+define i32 @main() nounwind {
+  %r = call i32 @FB( )   ; <i32> [#uses=1]
+  ret i32 %r
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/cross-module-sm-pic-a.ll b/test/ExecutionEngine/OrcMCJIT/remote/cross-module-sm-pic-a.ll
new file mode 100644
index 000000000000..c8979043857e
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/cross-module-sm-pic-a.ll
@@ -0,0 +1,14 @@
+; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/cross-module-b.ll -disable-lazy-compilation=true -remote-mcjit -mcjit-remote-process=lli-child-target%exeext -relocation-model=pic -code-model=small %s > /dev/null
+; XFAIL: mips, i686, i386, arm
+
+declare i32 @FB()
+
+define i32 @FA() {
+  ret i32 0
+}
+
+define i32 @main() {
+  %r = call i32 @FB( )   ; <i32> [#uses=1]
+  ret i32 %r
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/lit.local.cfg b/test/ExecutionEngine/OrcMCJIT/remote/lit.local.cfg
new file mode 100644
index 000000000000..625d82dc6189
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/lit.local.cfg
@@ -0,0 +1,8 @@
+if 'armv4' in config.root.target_triple or \
+   'armv5' in config.root.target_triple:
+    config.unsupported = True
+
+# This is temporary, until Remote MCJIT works on ARM
+# See http://llvm.org/bugs/show_bug.cgi?id=18057
+#if 'armv7' in config.root.target_triple:
+#    config.unsupported = True
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/multi-module-a.ll b/test/ExecutionEngine/OrcMCJIT/remote/multi-module-a.ll
new file mode 100644
index 000000000000..aa3434862305
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/multi-module-a.ll
@@ -0,0 +1,9 @@
+; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/multi-module-b.ll -extra-module=%p/Inputs/multi-module-c.ll -disable-lazy-compilation=true -remote-mcjit -mcjit-remote-process=lli-child-target%exeext %s > /dev/null
+
+declare i32 @FB()
+
+define i32 @main() nounwind {
+  %r = call i32 @FB( )   ; <i32> [#uses=1]
+  ret i32 %r
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/multi-module-sm-pic-a.ll b/test/ExecutionEngine/OrcMCJIT/remote/multi-module-sm-pic-a.ll
new file mode 100644
index 000000000000..41812d25169c
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/multi-module-sm-pic-a.ll
@@ -0,0 +1,10 @@
+; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/multi-module-b.ll -extra-module=%p/Inputs/multi-module-c.ll -disable-lazy-compilation=true -remote-mcjit -mcjit-remote-process=lli-child-target%exeext -relocation-model=pic -code-model=small %s > /dev/null
+; XFAIL: mips, i686, i386, arm
+
+declare i32 @FB()
+
+define i32 @main() {
+  %r = call i32 @FB( )   ; <i32> [#uses=1]
+  ret i32 %r
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/simpletest-remote.ll b/test/ExecutionEngine/OrcMCJIT/remote/simpletest-remote.ll
new file mode 100644
index 000000000000..45e11fce5a6e
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/simpletest-remote.ll
@@ -0,0 +1,10 @@
+; RUN: %lli -jit-kind=orc-mcjit -remote-mcjit -mcjit-remote-process=lli-child-target%exeext %s > /dev/null
+
+define i32 @bar() nounwind {
+	ret i32 0
+}
+
+define i32 @main() nounwind {
+	%r = call i32 @bar( )		; <i32> [#uses=1]
+	ret i32 %r
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/stubs-remote.ll b/test/ExecutionEngine/OrcMCJIT/remote/stubs-remote.ll
new file mode 100644
index 000000000000..aeff011d5edb
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/stubs-remote.ll
@@ -0,0 +1,37 @@
+; RUN: %lli -jit-kind=orc-mcjit -remote-mcjit -disable-lazy-compilation=false -mcjit-remote-process=lli-child-target%exeext %s
+; XFAIL: *
+; This test should fail until remote symbol resolution is supported.
+
+define i32 @main() nounwind {
+entry:
+	call void @lazily_compiled_address_is_consistent()
+	ret i32 0
+}
+
+; Test PR3043: @test should have the same address before and after
+; it's JIT-compiled.
+@funcPtr = common global i1 ()* null, align 4
+@lcaic_failure = internal constant [46 x i8] c"@lazily_compiled_address_is_consistent failed\00"
+
+define void @lazily_compiled_address_is_consistent() nounwind {
+entry:
+	store i1 ()* @test, i1 ()** @funcPtr
+	%pass = tail call i1 @test()		; <i32> [#uses=1]
+	br i1 %pass, label %pass_block, label %fail_block
+pass_block:
+	ret void
+fail_block:
+	call i32 @puts(i8* getelementptr([46 x i8], [46 x i8]* @lcaic_failure, i32 0, i32 0))
+	call void @exit(i32 1)
+	unreachable
+}
+
+define i1 @test() nounwind {
+entry:
+	%tmp = load i1 ()*, i1 ()** @funcPtr
+	%eq = icmp eq i1 ()* %tmp, @test
+	ret i1 %eq
+}
+
+declare i32 @puts(i8*) noreturn
+declare void @exit(i32) noreturn
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/stubs-sm-pic.ll b/test/ExecutionEngine/OrcMCJIT/remote/stubs-sm-pic.ll
new file mode 100644
index 000000000000..a67edba1d231
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/stubs-sm-pic.ll
@@ -0,0 +1,37 @@
+; RUN: %lli -jit-kind=orc-mcjit -remote-mcjit -disable-lazy-compilation=false -relocation-model=pic -code-model=small %s
+; XFAIL: *
+; This function should fail until remote symbol resolution is supported.
+
+define i32 @main() nounwind {
+entry:
+	call void @lazily_compiled_address_is_consistent()
+	ret i32 0
+}
+
+; Test PR3043: @test should have the same address before and after
+; it's JIT-compiled.
+@funcPtr = common global i1 ()* null, align 4
+@lcaic_failure = internal constant [46 x i8] c"@lazily_compiled_address_is_consistent failed\00"
+
+define void @lazily_compiled_address_is_consistent() nounwind {
+entry:
+	store i1 ()* @test, i1 ()** @funcPtr
+	%pass = tail call i1 @test()		; <i32> [#uses=1]
+	br i1 %pass, label %pass_block, label %fail_block
+pass_block:
+	ret void
+fail_block:
+	call i32 @puts(i8* getelementptr([46 x i8], [46 x i8]* @lcaic_failure, i32 0, i32 0))
+	call void @exit(i32 1)
+	unreachable
+}
+
+define i1 @test() nounwind {
+entry:
+	%tmp = load i1 ()*, i1 ()** @funcPtr
+	%eq = icmp eq i1 ()* %tmp, @test
+	ret i1 %eq
+}
+
+declare i32 @puts(i8*) noreturn
+declare void @exit(i32) noreturn
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/test-common-symbols-remote.ll b/test/ExecutionEngine/OrcMCJIT/remote/test-common-symbols-remote.ll
new file mode 100644
index 000000000000..7e4dc056027c
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/test-common-symbols-remote.ll
@@ -0,0 +1,88 @@
+; RUN: %lli -jit-kind=orc-mcjit -remote-mcjit -O0 -disable-lazy-compilation=false -mcjit-remote-process=lli-child-target%exeext %s
+
+; The intention of this test is to verify that symbols mapped to COMMON in ELF
+; work as expected.
+;
+; Compiled from this C code:
+;
+; int zero_int;
+; double zero_double;
+; int zero_arr[10];
+;
+; int main()
+; {
+;     zero_arr[zero_int + 5] = 40;
+;
+;     if (zero_double < 1.0)
+;         zero_arr[zero_int + 2] = 70;
+;
+;     for (int i = 1; i < 10; ++i) {
+;         zero_arr[i] = zero_arr[i - 1] + zero_arr[i];
+;     }
+;     return zero_arr[9] == 110 ? 0 : -1;
+; }
+
+@zero_int = common global i32 0, align 4
+@zero_arr = common global [10 x i32] zeroinitializer, align 16
+@zero_double = common global double 0.000000e+00, align 8
+
+define i32 @main() nounwind {
+entry:
+  %retval = alloca i32, align 4
+  %i = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32, i32* @zero_int, align 4
+  %add = add nsw i32 %0, 5
+  %idxprom = sext i32 %add to i64
+  %arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom
+  store i32 40, i32* %arrayidx, align 4
+  %1 = load double, double* @zero_double, align 8
+  %cmp = fcmp olt double %1, 1.000000e+00
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %2 = load i32, i32* @zero_int, align 4
+  %add1 = add nsw i32 %2, 2
+  %idxprom2 = sext i32 %add1 to i64
+  %arrayidx3 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom2
+  store i32 70, i32* %arrayidx3, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  store i32 1, i32* %i, align 4
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %if.end
+  %3 = load i32, i32* %i, align 4
+  %cmp4 = icmp slt i32 %3, 10
+  br i1 %cmp4, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %4 = load i32, i32* %i, align 4
+  %sub = sub nsw i32 %4, 1
+  %idxprom5 = sext i32 %sub to i64
+  %arrayidx6 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom5
+  %5 = load i32, i32* %arrayidx6, align 4
+  %6 = load i32, i32* %i, align 4
+  %idxprom7 = sext i32 %6 to i64
+  %arrayidx8 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom7
+  %7 = load i32, i32* %arrayidx8, align 4
+  %add9 = add nsw i32 %5, %7
+  %8 = load i32, i32* %i, align 4
+  %idxprom10 = sext i32 %8 to i64
+  %arrayidx11 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom10
+  store i32 %add9, i32* %arrayidx11, align 4
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body
+  %9 = load i32, i32* %i, align 4
+  %inc = add nsw i32 %9, 1
+  store i32 %inc, i32* %i, align 4
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  %10 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @zero_arr, i32 0, i64 9), align 4
+  %cmp12 = icmp eq i32 %10, 110
+  %cond = select i1 %cmp12, i32 0, i32 -1
+  ret i32 %cond
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/test-data-align-remote.ll b/test/ExecutionEngine/OrcMCJIT/remote/test-data-align-remote.ll
new file mode 100644
index 000000000000..95c9b825a8d3
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/test-data-align-remote.ll
@@ -0,0 +1,15 @@
+; RUN:  %lli -jit-kind=orc-mcjit -remote-mcjit -O0 -mcjit-remote-process=lli-child-target%exeext %s
+
+; Check that a variable is always aligned as specified.
+
+@var = global i32 0, align 32
+define i32 @main() nounwind {
+  %addr = ptrtoint i32* @var to i64
+  %mask = and i64 %addr, 31
+  %tst = icmp eq i64 %mask, 0
+  br i1 %tst, label %good, label %bad
+good:
+  ret i32 0
+bad:
+  ret i32 1
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/test-fp-no-external-funcs-remote.ll b/test/ExecutionEngine/OrcMCJIT/remote/test-fp-no-external-funcs-remote.ll
new file mode 100644
index 000000000000..286710338841
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/test-fp-no-external-funcs-remote.ll
@@ -0,0 +1,20 @@
+; RUN: %lli -jit-kind=orc-mcjit -remote-mcjit -mcjit-remote-process=lli-child-target%exeext %s > /dev/null
+
+define double @test(double* %DP, double %Arg) nounwind {
+	%D = load double, double* %DP		; <double> [#uses=1]
+	%V = fadd double %D, 1.000000e+00		; <double> [#uses=2]
+	%W = fsub double %V, %V		; <double> [#uses=3]
+	%X = fmul double %W, %W		; <double> [#uses=2]
+	%Y = fdiv double %X, %X		; <double> [#uses=2]
+	%Q = fadd double %Y, %Arg		; <double> [#uses=1]
+	%R = bitcast double %Q to double		; <double> [#uses=1]
+	store double %Q, double* %DP
+	ret double %Y
+}
+
+define i32 @main() nounwind {
+	%X = alloca double		; <double*> [#uses=2]
+	store double 0.000000e+00, double* %X
+	call double @test( double* %X, double 2.000000e+00 )		; <double>:1 [#uses=0]
+	ret i32 0
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/test-global-init-nonzero-remote.ll b/test/ExecutionEngine/OrcMCJIT/remote/test-global-init-nonzero-remote.ll
new file mode 100644
index 000000000000..5dabb8f44d68
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/test-global-init-nonzero-remote.ll
@@ -0,0 +1,34 @@
+; RUN: %lli -jit-kind=orc-mcjit -remote-mcjit -mcjit-remote-process=lli-child-target%exeext %s > /dev/null
+
+@count = global i32 1, align 4
+
+define i32 @main() nounwind {
+entry:
+  %retval = alloca i32, align 4
+  %i = alloca i32, align 4
+  store i32 0, i32* %retval
+  store i32 0, i32* %i, align 4
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %entry
+  %0 = load i32, i32* %i, align 4
+  %cmp = icmp slt i32 %0, 49
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %1 = load i32, i32* @count, align 4
+  %inc = add nsw i32 %1, 1
+  store i32 %inc, i32* @count, align 4
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body
+  %2 = load i32, i32* %i, align 4
+  %inc1 = add nsw i32 %2, 1
+  store i32 %inc1, i32* %i, align 4
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  %3 = load i32, i32* @count, align 4
+  %sub = sub nsw i32 %3, 50
+  ret i32 %sub
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/test-global-init-nonzero-sm-pic.ll b/test/ExecutionEngine/OrcMCJIT/remote/test-global-init-nonzero-sm-pic.ll
new file mode 100644
index 000000000000..ec9e1ae1a03c
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/test-global-init-nonzero-sm-pic.ll
@@ -0,0 +1,35 @@
+; RUN: %lli -jit-kind=orc-mcjit -remote-mcjit -relocation-model=pic -code-model=small %s > /dev/null
+; XFAIL: mips, aarch64, arm, i686, i386
+
+@count = global i32 1, align 4
+
+define i32 @main() nounwind uwtable {
+entry:
+  %retval = alloca i32, align 4
+  %i = alloca i32, align 4
+  store i32 0, i32* %retval
+  store i32 0, i32* %i, align 4
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %entry
+  %0 = load i32, i32* %i, align 4
+  %cmp = icmp slt i32 %0, 49
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %1 = load i32, i32* @count, align 4
+  %inc = add nsw i32 %1, 1
+  store i32 %inc, i32* @count, align 4
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body
+  %2 = load i32, i32* %i, align 4
+  %inc1 = add nsw i32 %2, 1
+  store i32 %inc1, i32* %i, align 4
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  %3 = load i32, i32* @count, align 4
+  %sub = sub nsw i32 %3, 50
+  ret i32 %sub
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/test-ptr-reloc-remote.ll b/test/ExecutionEngine/OrcMCJIT/remote/test-ptr-reloc-remote.ll
new file mode 100644
index 000000000000..aa07db9f512d
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/test-ptr-reloc-remote.ll
@@ -0,0 +1,15 @@
+; RUN: %lli -jit-kind=orc-mcjit -remote-mcjit -O0 -mcjit-remote-process=lli-child-target%exeext %s
+
+@.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
+@ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
+@.str1 = private unnamed_addr constant [6 x i8] c"data2\00", align 1
+@ptr2 = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), align 4
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly {
+entry:
+  %0 = load i8*, i8** @ptr, align 4
+  %1 = load i8*, i8** @ptr2, align 4
+  %cmp = icmp eq i8* %0, %1
+  %. = zext i1 %cmp to i32
+  ret i32 %.
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/remote/test-ptr-reloc-sm-pic.ll b/test/ExecutionEngine/OrcMCJIT/remote/test-ptr-reloc-sm-pic.ll
new file mode 100644
index 000000000000..61321ac1b947
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/remote/test-ptr-reloc-sm-pic.ll
@@ -0,0 +1,17 @@
+; RUN: %lli -jit-kind=orc-mcjit -remote-mcjit -O0 -relocation-model=pic -code-model=small %s
+; XFAIL: mips, aarch64, arm, i686, i386
+
+@.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
+@ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
+@.str1 = private unnamed_addr constant [6 x i8] c"data2\00", align 1
+@ptr2 = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), align 4
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly {
+entry:
+  %0 = load i8*, i8** @ptr, align 4
+  %1 = load i8*, i8** @ptr2, align 4
+  %cmp = icmp eq i8* %0, %1
+  %. = zext i1 %cmp to i32
+  ret i32 %.
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/simplesttest.ll b/test/ExecutionEngine/OrcMCJIT/simplesttest.ll
new file mode 100644
index 000000000000..4a47131ada22
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/simplesttest.ll
@@ -0,0 +1,6 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @main() {
+	ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/simpletest.ll b/test/ExecutionEngine/OrcMCJIT/simpletest.ll
new file mode 100644
index 000000000000..be1148be8a54
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/simpletest.ll
@@ -0,0 +1,11 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @bar() {
+	ret i32 0
+}
+
+define i32 @main() {
+	%r = call i32 @bar( )		; <i32> [#uses=1]
+	ret i32 %r
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/stubs-sm-pic.ll b/test/ExecutionEngine/OrcMCJIT/stubs-sm-pic.ll
new file mode 100644
index 000000000000..f354a0de0935
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/stubs-sm-pic.ll
@@ -0,0 +1,36 @@
+; RUN: %lli -jit-kind=orc-mcjit -disable-lazy-compilation=false -relocation-model=pic -code-model=small %s
+; XFAIL: mips, i686, i386, aarch64, arm
+
+define i32 @main() nounwind {
+entry:
+	call void @lazily_compiled_address_is_consistent()
+	ret i32 0
+}
+
+; Test PR3043: @test should have the same address before and after
+; it's JIT-compiled.
+@funcPtr = common global i1 ()* null, align 4
+@lcaic_failure = internal constant [46 x i8] c"@lazily_compiled_address_is_consistent failed\00"
+
+define void @lazily_compiled_address_is_consistent() nounwind {
+entry:
+	store i1 ()* @test, i1 ()** @funcPtr
+	%pass = tail call i1 @test()		; <i32> [#uses=1]
+	br i1 %pass, label %pass_block, label %fail_block
+pass_block:
+	ret void
+fail_block:
+	call i32 @puts(i8* getelementptr([46 x i8], [46 x i8]* @lcaic_failure, i32 0, i32 0))
+	call void @exit(i32 1)
+	unreachable
+}
+
+define i1 @test() nounwind {
+entry:
+	%tmp = load i1 ()*, i1 ()** @funcPtr
+	%eq = icmp eq i1 ()* %tmp, @test
+	ret i1 %eq
+}
+
+declare i32 @puts(i8*) noreturn
+declare void @exit(i32) noreturn
diff --git a/test/ExecutionEngine/OrcMCJIT/stubs.ll b/test/ExecutionEngine/OrcMCJIT/stubs.ll
new file mode 100644
index 000000000000..c096f5fd7e78
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/stubs.ll
@@ -0,0 +1,35 @@
+; RUN: %lli -jit-kind=orc-mcjit -disable-lazy-compilation=false %s
+
+define i32 @main() nounwind {
+entry:
+	call void @lazily_compiled_address_is_consistent()
+	ret i32 0
+}
+
+; Test PR3043: @test should have the same address before and after
+; it's JIT-compiled.
+@funcPtr = common global i1 ()* null, align 4
+@lcaic_failure = internal constant [46 x i8] c"@lazily_compiled_address_is_consistent failed\00"
+
+define void @lazily_compiled_address_is_consistent() nounwind {
+entry:
+	store i1 ()* @test, i1 ()** @funcPtr
+	%pass = tail call i1 @test()		; <i32> [#uses=1]
+	br i1 %pass, label %pass_block, label %fail_block
+pass_block:
+	ret void
+fail_block:
+	call i32 @puts(i8* getelementptr([46 x i8], [46 x i8]* @lcaic_failure, i32 0, i32 0))
+	call void @exit(i32 1)
+	unreachable
+}
+
+define i1 @test() nounwind {
+entry:
+	%tmp = load i1 ()*, i1 ()** @funcPtr
+	%eq = icmp eq i1 ()* %tmp, @test
+	ret i1 %eq
+}
+
+declare i32 @puts(i8*) noreturn
+declare void @exit(i32) noreturn
diff --git a/test/ExecutionEngine/OrcMCJIT/test-arith.ll b/test/ExecutionEngine/OrcMCJIT/test-arith.ll
new file mode 100644
index 000000000000..c4331bf73272
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-arith.ll
@@ -0,0 +1,34 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @main() {
+	%A = add i8 0, 12		; <i8> [#uses=1]
+	%B = sub i8 %A, 1		; <i8> [#uses=2]
+	%C = mul i8 %B, %B		; <i8> [#uses=2]
+	%D = sdiv i8 %C, %C		; <i8> [#uses=2]
+	%E = srem i8 %D, %D		; <i8> [#uses=0]
+	%F = udiv i8 5, 6		; <i8> [#uses=0]
+	%G = urem i8 6, 5		; <i8> [#uses=0]
+	%A.upgrd.1 = add i16 0, 12		; <i16> [#uses=1]
+	%B.upgrd.2 = sub i16 %A.upgrd.1, 1		; <i16> [#uses=2]
+	%C.upgrd.3 = mul i16 %B.upgrd.2, %B.upgrd.2		; <i16> [#uses=2]
+	%D.upgrd.4 = sdiv i16 %C.upgrd.3, %C.upgrd.3		; <i16> [#uses=2]
+	%E.upgrd.5 = srem i16 %D.upgrd.4, %D.upgrd.4		; <i16> [#uses=0]
+	%F.upgrd.6 = udiv i16 5, 6		; <i16> [#uses=0]
+	%G.upgrd.7 = urem i32 6, 5		; <i32> [#uses=0]
+	%A.upgrd.8 = add i32 0, 12		; <i32> [#uses=1]
+	%B.upgrd.9 = sub i32 %A.upgrd.8, 1		; <i32> [#uses=2]
+	%C.upgrd.10 = mul i32 %B.upgrd.9, %B.upgrd.9		; <i32> [#uses=2]
+	%D.upgrd.11 = sdiv i32 %C.upgrd.10, %C.upgrd.10		; <i32> [#uses=2]
+	%E.upgrd.12 = srem i32 %D.upgrd.11, %D.upgrd.11		; <i32> [#uses=0]
+	%F.upgrd.13 = udiv i32 5, 6		; <i32> [#uses=0]
+	%G1 = urem i32 6, 5		; <i32> [#uses=0]
+	%A.upgrd.14 = add i64 0, 12		; <i64> [#uses=1]
+	%B.upgrd.15 = sub i64 %A.upgrd.14, 1		; <i64> [#uses=2]
+	%C.upgrd.16 = mul i64 %B.upgrd.15, %B.upgrd.15		; <i64> [#uses=2]
+	%D.upgrd.17 = sdiv i64 %C.upgrd.16, %C.upgrd.16		; <i64> [#uses=2]
+	%E.upgrd.18 = srem i64 %D.upgrd.17, %D.upgrd.17		; <i64> [#uses=0]
+	%F.upgrd.19 = udiv i64 5, 6		; <i64> [#uses=0]
+	%G.upgrd.20 = urem i64 6, 5		; <i64> [#uses=0]
+	ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/test-branch.ll b/test/ExecutionEngine/OrcMCJIT/test-branch.ll
new file mode 100644
index 000000000000..b3ef86a193ef
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-branch.ll
@@ -0,0 +1,12 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+; test unconditional branch
+define i32 @main() {
+	br label %Test
+Test:		; preds = %Test, %0
+	%X = icmp eq i32 0, 4		; <i1> [#uses=1]
+	br i1 %X, label %Test, label %Label
+Label:		; preds = %Test
+	ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/test-call-no-external-funcs.ll b/test/ExecutionEngine/OrcMCJIT/test-call-no-external-funcs.ll
new file mode 100644
index 000000000000..78c6a1bb2f9f
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-call-no-external-funcs.ll
@@ -0,0 +1,14 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @_Z14func_exit_codev() nounwind uwtable {
+entry:
+  ret i32 0
+}
+
+define i32 @main() nounwind uwtable {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  %call = call i32 @_Z14func_exit_codev()
+  ret i32 %call
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/test-call.ll b/test/ExecutionEngine/OrcMCJIT/test-call.ll
new file mode 100644
index 000000000000..5345856f5658
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-call.ll
@@ -0,0 +1,21 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+declare void @exit(i32)
+
+define i32 @test(i8 %C, i16 %S) {
+	%X = trunc i16 %S to i8		; <i8> [#uses=1]
+	%Y = zext i8 %X to i32		; <i32> [#uses=1]
+	ret i32 %Y
+}
+
+define void @FP(void (i32)* %F) {
+	%X = call i32 @test( i8 123, i16 1024 )		; <i32> [#uses=1]
+	call void %F( i32 %X )
+	ret void
+}
+
+define i32 @main() {
+	call void @FP( void (i32)* @exit )
+	ret i32 1
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/test-cast.ll b/test/ExecutionEngine/OrcMCJIT/test-cast.ll
new file mode 100644
index 000000000000..f1a521f3b626
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-cast.ll
@@ -0,0 +1,109 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @foo() {
+	ret i32 0
+}
+
+define i32 @main() {
+	icmp ne i1 true, false		; <i1>:1 [#uses=0]
+	zext i1 true to i8		; <i8>:2 [#uses=0]
+	zext i1 true to i8		; <i8>:3 [#uses=0]
+	zext i1 true to i16		; <i16>:4 [#uses=0]
+	zext i1 true to i16		; <i16>:5 [#uses=0]
+	zext i1 true to i32		; <i32>:6 [#uses=0]
+	zext i1 true to i32		; <i32>:7 [#uses=0]
+	zext i1 true to i64		; <i64>:8 [#uses=0]
+	zext i1 true to i64		; <i64>:9 [#uses=0]
+	uitofp i1 true to float		; <float>:10 [#uses=0]
+	uitofp i1 true to double		; <double>:11 [#uses=0]
+	icmp ne i8 0, 0		; <i1>:12 [#uses=0]
+	icmp ne i8 1, 0		; <i1>:13 [#uses=0]
+	bitcast i8 0 to i8		; <i8>:14 [#uses=0]
+	bitcast i8 -1 to i8		; <i8>:15 [#uses=0]
+	sext i8 4 to i16		; <i16>:16 [#uses=0]
+	sext i8 4 to i16		; <i16>:17 [#uses=0]
+	sext i8 4 to i64		; <i64>:18 [#uses=0]
+	sext i8 4 to i64		; <i64>:19 [#uses=0]
+	sitofp i8 4 to float		; <float>:20 [#uses=0]
+	sitofp i8 4 to double		; <double>:21 [#uses=0]
+	icmp ne i8 0, 0		; <i1>:22 [#uses=0]
+	icmp ne i8 1, 0		; <i1>:23 [#uses=0]
+	bitcast i8 0 to i8		; <i8>:24 [#uses=0]
+	bitcast i8 1 to i8		; <i8>:25 [#uses=0]
+	zext i8 4 to i16		; <i16>:26 [#uses=0]
+	zext i8 4 to i16		; <i16>:27 [#uses=0]
+	zext i8 4 to i64		; <i64>:28 [#uses=0]
+	zext i8 4 to i64		; <i64>:29 [#uses=0]
+	uitofp i8 0 to float		; <float>:30 [#uses=0]
+	uitofp i8 0 to double		; <double>:31 [#uses=0]
+	icmp ne i16 1, 0		; <i1>:32 [#uses=0]
+	trunc i16 -1 to i8		; <i8>:33 [#uses=0]
+	trunc i16 255 to i8		; <i8>:34 [#uses=0]
+	bitcast i16 0 to i16		; <i16>:35 [#uses=0]
+	bitcast i16 0 to i16		; <i16>:36 [#uses=0]
+	sext i16 0 to i64		; <i64>:37 [#uses=0]
+	sext i16 0 to i64		; <i64>:38 [#uses=0]
+	sitofp i16 0 to float		; <float>:39 [#uses=0]
+	sitofp i16 0 to double		; <double>:40 [#uses=0]
+	icmp ne i16 1, 0		; <i1>:41 [#uses=0]
+	trunc i16 1 to i8		; <i8>:42 [#uses=0]
+	trunc i16 255 to i8		; <i8>:43 [#uses=0]
+	bitcast i16 0 to i16		; <i16>:44 [#uses=0]
+	bitcast i16 0 to i16		; <i16>:45 [#uses=0]
+	zext i16 0 to i64		; <i64>:46 [#uses=0]
+	zext i16 0 to i64		; <i64>:47 [#uses=0]
+	uitofp i16 0 to float		; <float>:48 [#uses=0]
+	uitofp i16 0 to double		; <double>:49 [#uses=0]
+	icmp ne i32 6, 0		; <i1>:50 [#uses=0]
+	trunc i32 -6 to i8		; <i8>:51 [#uses=0]
+	trunc i32 6 to i8		; <i8>:52 [#uses=0]
+	trunc i32 6 to i16		; <i16>:53 [#uses=0]
+	bitcast i32 0 to i32		; <i32>:54 [#uses=0]
+	sext i32 0 to i64		; <i64>:55 [#uses=0]
+	sext i32 0 to i64		; <i64>:56 [#uses=0]
+	sitofp i32 0 to float		; <float>:57 [#uses=0]
+	sitofp i32 0 to double		; <double>:58 [#uses=0]
+	icmp ne i32 6, 0		; <i1>:59 [#uses=0]
+	trunc i32 7 to i8		; <i8>:60 [#uses=0]
+	trunc i32 8 to i8		; <i8>:61 [#uses=0]
+	trunc i32 9 to i16		; <i16>:62 [#uses=0]
+	bitcast i32 10 to i32		; <i32>:63 [#uses=0]
+	zext i32 0 to i64		; <i64>:64 [#uses=0]
+	zext i32 0 to i64		; <i64>:65 [#uses=0]
+	uitofp i32 0 to float		; <float>:66 [#uses=0]
+	uitofp i32 0 to double		; <double>:67 [#uses=0]
+	icmp ne i64 0, 0		; <i1>:68 [#uses=0]
+	trunc i64 0 to i8		; <i8>:69 [#uses=0]
+	trunc i64 0 to i8		; <i8>:70 [#uses=0]
+	trunc i64 0 to i16		; <i16>:71 [#uses=0]
+	trunc i64 0 to i16		; <i16>:72 [#uses=0]
+	trunc i64 0 to i32		; <i32>:73 [#uses=0]
+	trunc i64 0 to i32		; <i32>:74 [#uses=0]
+	bitcast i64 0 to i64		; <i64>:75 [#uses=0]
+	bitcast i64 0 to i64		; <i64>:76 [#uses=0]
+	sitofp i64 0 to float		; <float>:77 [#uses=0]
+	sitofp i64 0 to double		; <double>:78 [#uses=0]
+	icmp ne i64 1, 0		; <i1>:79 [#uses=0]
+	trunc i64 1 to i8		; <i8>:80 [#uses=0]
+	trunc i64 1 to i8		; <i8>:81 [#uses=0]
+	trunc i64 1 to i16		; <i16>:82 [#uses=0]
+	trunc i64 1 to i16		; <i16>:83 [#uses=0]
+	trunc i64 1 to i32		; <i32>:84 [#uses=0]
+	trunc i64 1 to i32		; <i32>:85 [#uses=0]
+	bitcast i64 1 to i64		; <i64>:86 [#uses=0]
+	bitcast i64 1 to i64		; <i64>:87 [#uses=0]
+	uitofp i64 1 to float		; <float>:88 [#uses=0]
+	uitofp i64 0 to double		; <double>:89 [#uses=0]
+	bitcast float 0.000000e+00 to float		; <float>:90 [#uses=0]
+	fpext float 0.000000e+00 to double		; <double>:91 [#uses=0]
+	fptosi double 0.000000e+00 to i8		; <i8>:92 [#uses=0]
+	fptoui double 0.000000e+00 to i8		; <i8>:93 [#uses=0]
+	fptosi double 0.000000e+00 to i16		; <i16>:94 [#uses=0]
+	fptoui double 0.000000e+00 to i16		; <i16>:95 [#uses=0]
+	fptosi double 0.000000e+00 to i32		; <i32>:96 [#uses=0]
+	fptoui double 0.000000e+00 to i32		; <i32>:97 [#uses=0]
+	fptosi double 0.000000e+00 to i64		; <i64>:98 [#uses=0]
+	fptrunc double 0.000000e+00 to float		; <float>:99 [#uses=0]
+	bitcast double 0.000000e+00 to double		; <double>:100 [#uses=0]
+	ret i32 0
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/test-common-symbols-alignment.ll b/test/ExecutionEngine/OrcMCJIT/test-common-symbols-alignment.ll
new file mode 100644
index 000000000000..cfbd2761a37f
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-common-symbols-alignment.ll
@@ -0,0 +1,32 @@
+; RUN: %lli -jit-kind=orc-mcjit -O0 %s
+
+; This test checks that common symbols have been allocated addresses honouring
+; the alignment requirement.
+
+@CS1 = common global i32 0, align 16
+@CS2 = common global i8 0, align 1
+@CS3 = common global i32 0, align 16
+
+define i32 @main() nounwind {
+entry:
+    %retval = alloca i32, align 4
+    %ptr = alloca i32, align 4
+    store i32 0, i32* %retval
+    store i32 ptrtoint (i32* @CS3 to i32), i32* %ptr, align 4
+    %0 = load i32, i32* %ptr, align 4
+    %and = and i32 %0, 15
+    %tobool = icmp ne i32 %and, 0
+    br i1 %tobool, label %if.then, label %if.else
+
+if.then:                                          ; preds = %entry
+    store i32 1, i32* %retval
+    br label %return
+
+if.else:                                          ; preds = %entry
+    store i32 0, i32* %retval
+    br label %return
+
+return:                                           ; preds = %if.else, %if.then
+    %1 = load i32, i32* %retval
+    ret i32 %1
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/test-common-symbols.ll b/test/ExecutionEngine/OrcMCJIT/test-common-symbols.ll
new file mode 100644
index 000000000000..db3c0471a8e8
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-common-symbols.ll
@@ -0,0 +1,88 @@
+; RUN: %lli -jit-kind=orc-mcjit -O0 -disable-lazy-compilation=false %s
+
+; The intention of this test is to verify that symbols mapped to COMMON in ELF
+; work as expected.
+;
+; Compiled from this C code:
+;
+; int zero_int;
+; double zero_double;
+; int zero_arr[10];
+; 
+; int main()
+; {
+;     zero_arr[zero_int + 5] = 40;
+; 
+;     if (zero_double < 1.0)
+;         zero_arr[zero_int + 2] = 70;
+; 
+;     for (int i = 1; i < 10; ++i) {
+;         zero_arr[i] = zero_arr[i - 1] + zero_arr[i];
+;     }
+;     return zero_arr[9] == 110 ? 0 : -1;
+; }
+
+@zero_int = common global i32 0, align 4
+@zero_arr = common global [10 x i32] zeroinitializer, align 16
+@zero_double = common global double 0.000000e+00, align 8
+
+define i32 @main() nounwind {
+entry:
+  %retval = alloca i32, align 4
+  %i = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32, i32* @zero_int, align 4
+  %add = add nsw i32 %0, 5
+  %idxprom = sext i32 %add to i64
+  %arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom
+  store i32 40, i32* %arrayidx, align 4
+  %1 = load double, double* @zero_double, align 8
+  %cmp = fcmp olt double %1, 1.000000e+00
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %2 = load i32, i32* @zero_int, align 4
+  %add1 = add nsw i32 %2, 2
+  %idxprom2 = sext i32 %add1 to i64
+  %arrayidx3 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom2
+  store i32 70, i32* %arrayidx3, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  store i32 1, i32* %i, align 4
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %if.end
+  %3 = load i32, i32* %i, align 4
+  %cmp4 = icmp slt i32 %3, 10
+  br i1 %cmp4, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %4 = load i32, i32* %i, align 4
+  %sub = sub nsw i32 %4, 1
+  %idxprom5 = sext i32 %sub to i64
+  %arrayidx6 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom5
+  %5 = load i32, i32* %arrayidx6, align 4
+  %6 = load i32, i32* %i, align 4
+  %idxprom7 = sext i32 %6 to i64
+  %arrayidx8 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom7
+  %7 = load i32, i32* %arrayidx8, align 4
+  %add9 = add nsw i32 %5, %7
+  %8 = load i32, i32* %i, align 4
+  %idxprom10 = sext i32 %8 to i64
+  %arrayidx11 = getelementptr inbounds [10 x i32], [10 x i32]* @zero_arr, i32 0, i64 %idxprom10
+  store i32 %add9, i32* %arrayidx11, align 4
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body
+  %9 = load i32, i32* %i, align 4
+  %inc = add nsw i32 %9, 1
+  store i32 %inc, i32* %i, align 4
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  %10 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @zero_arr, i32 0, i64 9), align 4
+  %cmp12 = icmp eq i32 %10, 110
+  %cond = select i1 %cmp12, i32 0, i32 -1
+  ret i32 %cond
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/test-constantexpr.ll b/test/ExecutionEngine/OrcMCJIT/test-constantexpr.ll
new file mode 100644
index 000000000000..9a147c2fc1a7
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-constantexpr.ll
@@ -0,0 +1,12 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+; This tests to make sure that we can evaluate weird constant expressions
+
+@A = global i32 5		; <i32*> [#uses=1]
+@B = global i32 6		; <i32*> [#uses=1]
+
+define i32 @main() {
+	%A = or i1 false, icmp slt (i32* @A, i32* @B)		; <i1> [#uses=0]
+	ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/test-data-align.ll b/test/ExecutionEngine/OrcMCJIT/test-data-align.ll
new file mode 100644
index 000000000000..f0deb56d52d6
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-data-align.ll
@@ -0,0 +1,15 @@
+; RUN: %lli -jit-kind=orc-mcjit -O0 %s
+
+; Check that a variable is always aligned as specified.
+
+@var = global i32 0, align 32
+define i32 @main() {
+  %addr = ptrtoint i32* @var to i64
+  %mask = and i64 %addr, 31
+  %tst = icmp eq i64 %mask, 0
+  br i1 %tst, label %good, label %bad
+good:
+  ret i32 0
+bad:
+  ret i32 1
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/test-fp-no-external-funcs.ll b/test/ExecutionEngine/OrcMCJIT/test-fp-no-external-funcs.ll
new file mode 100644
index 000000000000..2baadcde4b1e
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-fp-no-external-funcs.ll
@@ -0,0 +1,21 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define double @test(double* %DP, double %Arg) {
+	%D = load double, double* %DP		; <double> [#uses=1]
+	%V = fadd double %D, 1.000000e+00		; <double> [#uses=2]
+	%W = fsub double %V, %V		; <double> [#uses=3]
+	%X = fmul double %W, %W		; <double> [#uses=2]
+	%Y = fdiv double %X, %X		; <double> [#uses=2]
+	%Q = fadd double %Y, %Arg		; <double> [#uses=1]
+	%R = bitcast double %Q to double		; <double> [#uses=1]
+	store double %Q, double* %DP
+	ret double %Y
+}
+
+define i32 @main() {
+	%X = alloca double		; <double*> [#uses=2]
+	store double 0.000000e+00, double* %X
+	call double @test( double* %X, double 2.000000e+00 )		; <double>:1 [#uses=0]
+	ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/test-fp.ll b/test/ExecutionEngine/OrcMCJIT/test-fp.ll
new file mode 100644
index 000000000000..6d56e69a9972
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-fp.ll
@@ -0,0 +1,23 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define double @test(double* %DP, double %Arg) {
+	%D = load double, double* %DP		; <double> [#uses=1]
+	%V = fadd double %D, 1.000000e+00		; <double> [#uses=2]
+	%W = fsub double %V, %V		; <double> [#uses=3]
+	%X = fmul double %W, %W		; <double> [#uses=2]
+	%Y = fdiv double %X, %X		; <double> [#uses=2]
+	%Z = frem double %Y, %Y		; <double> [#uses=3]
+	%Z1 = fdiv double %Z, %W		; <double> [#uses=0]
+	%Q = fadd double %Z, %Arg		; <double> [#uses=1]
+	%R = bitcast double %Q to double		; <double> [#uses=1]
+	store double %R, double* %DP
+	ret double %Z
+}
+
+define i32 @main() {
+	%X = alloca double		; <double*> [#uses=2]
+	store double 0.000000e+00, double* %X
+	call double @test( double* %X, double 2.000000e+00 )		; <double>:1 [#uses=0]
+	ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/test-global-ctors.ll b/test/ExecutionEngine/OrcMCJIT/test-global-ctors.ll
new file mode 100644
index 000000000000..d66efc27fb41
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-global-ctors.ll
@@ -0,0 +1,22 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+; XFAIL: darwin
+@var = global i32 1, align 4
+@llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @ctor_func }]
+@llvm.global_dtors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @dtor_func }]
+
+define i32 @main() nounwind {
+entry:
+  %0 = load i32, i32* @var, align 4
+  ret i32 %0
+}
+
+define internal void @ctor_func() section ".text.startup" {
+entry:
+  store i32 0, i32* @var, align 4
+  ret void
+}
+
+define internal void @dtor_func() section ".text.startup" {
+entry:
+  ret void
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/test-global-init-nonzero-sm-pic.ll b/test/ExecutionEngine/OrcMCJIT/test-global-init-nonzero-sm-pic.ll
new file mode 100644
index 000000000000..7f66aec77078
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-global-init-nonzero-sm-pic.ll
@@ -0,0 +1,35 @@
+; RUN: %lli -jit-kind=orc-mcjit -relocation-model=pic -code-model=small %s > /dev/null
+; XFAIL: mips, aarch64, arm, i686, i386
+
+@count = global i32 1, align 4
+
+define i32 @main() nounwind uwtable {
+entry:
+  %retval = alloca i32, align 4
+  %i = alloca i32, align 4
+  store i32 0, i32* %retval
+  store i32 0, i32* %i, align 4
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %entry
+  %0 = load i32, i32* %i, align 4
+  %cmp = icmp slt i32 %0, 49
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %1 = load i32, i32* @count, align 4
+  %inc = add nsw i32 %1, 1
+  store i32 %inc, i32* @count, align 4
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body
+  %2 = load i32, i32* %i, align 4
+  %inc1 = add nsw i32 %2, 1
+  store i32 %inc1, i32* %i, align 4
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  %3 = load i32, i32* @count, align 4
+  %sub = sub nsw i32 %3, 50
+  ret i32 %sub
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/test-global-init-nonzero.ll b/test/ExecutionEngine/OrcMCJIT/test-global-init-nonzero.ll
new file mode 100644
index 000000000000..f8d43bffb8bd
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-global-init-nonzero.ll
@@ -0,0 +1,34 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+@count = global i32 1, align 4
+
+define i32 @main() nounwind uwtable {
+entry:
+  %retval = alloca i32, align 4
+  %i = alloca i32, align 4
+  store i32 0, i32* %retval
+  store i32 0, i32* %i, align 4
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %entry
+  %0 = load i32, i32* %i, align 4
+  %cmp = icmp slt i32 %0, 49
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %1 = load i32, i32* @count, align 4
+  %inc = add nsw i32 %1, 1
+  store i32 %inc, i32* @count, align 4
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body
+  %2 = load i32, i32* %i, align 4
+  %inc1 = add nsw i32 %2, 1
+  store i32 %inc1, i32* %i, align 4
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  %3 = load i32, i32* @count, align 4
+  %sub = sub nsw i32 %3, 50
+  ret i32 %sub
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/test-global.ll b/test/ExecutionEngine/OrcMCJIT/test-global.ll
new file mode 100644
index 000000000000..3e42caee12ca
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-global.ll
@@ -0,0 +1,34 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+@count = global i32 0, align 4
+
+define i32 @main() nounwind uwtable {
+entry:
+  %retval = alloca i32, align 4
+  %i = alloca i32, align 4
+  store i32 0, i32* %retval
+  store i32 0, i32* %i, align 4
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %entry
+  %0 = load i32, i32* %i, align 4
+  %cmp = icmp slt i32 %0, 50
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %1 = load i32, i32* @count, align 4
+  %inc = add nsw i32 %1, 1
+  store i32 %inc, i32* @count, align 4
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body
+  %2 = load i32, i32* %i, align 4
+  %inc1 = add nsw i32 %2, 1
+  store i32 %inc1, i32* %i, align 4
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  %3 = load i32, i32* @count, align 4
+  %sub = sub nsw i32 %3, 50
+  ret i32 %sub
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/test-loadstore.ll b/test/ExecutionEngine/OrcMCJIT/test-loadstore.ll
new file mode 100644
index 000000000000..d95d61a067ff
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-loadstore.ll
@@ -0,0 +1,31 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define void @test(i8* %P, i16* %P.upgrd.1, i32* %P.upgrd.2, i64* %P.upgrd.3) {
+	%V = load i8, i8* %P		; <i8> [#uses=1]
+	store i8 %V, i8* %P
+	%V.upgrd.4 = load i16, i16* %P.upgrd.1		; <i16> [#uses=1]
+	store i16 %V.upgrd.4, i16* %P.upgrd.1
+	%V.upgrd.5 = load i32, i32* %P.upgrd.2		; <i32> [#uses=1]
+	store i32 %V.upgrd.5, i32* %P.upgrd.2
+	%V.upgrd.6 = load i64, i64* %P.upgrd.3		; <i64> [#uses=1]
+	store i64 %V.upgrd.6, i64* %P.upgrd.3
+	ret void
+}
+
+define i32 @varalloca(i32 %Size) {
+        ;; Variable sized alloca
+	%X = alloca i32, i32 %Size		; <i32*> [#uses=2]
+	store i32 %Size, i32* %X
+	%Y = load i32, i32* %X		; <i32> [#uses=1]
+	ret i32 %Y
+}
+
+define i32 @main() {
+	%A = alloca i8		; <i8*> [#uses=1]
+	%B = alloca i16		; <i16*> [#uses=1]
+	%C = alloca i32		; <i32*> [#uses=1]
+	%D = alloca i64		; <i64*> [#uses=1]
+	call void @test( i8* %A, i16* %B, i32* %C, i64* %D )
+	call i32 @varalloca( i32 7 )		; <i32>:1 [#uses=0]
+	ret i32 0
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/test-local.ll b/test/ExecutionEngine/OrcMCJIT/test-local.ll
new file mode 100644
index 000000000000..1e63d9f231fd
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-local.ll
@@ -0,0 +1,34 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @main() nounwind uwtable {
+entry:
+  %retval = alloca i32, align 4
+  %count = alloca i32, align 4
+  %i = alloca i32, align 4
+  store i32 0, i32* %retval
+  store i32 0, i32* %count, align 4
+  store i32 0, i32* %i, align 4
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %entry
+  %0 = load i32, i32* %i, align 4
+  %cmp = icmp slt i32 %0, 50
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %1 = load i32, i32* %count, align 4
+  %inc = add nsw i32 %1, 1
+  store i32 %inc, i32* %count, align 4
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body
+  %2 = load i32, i32* %i, align 4
+  %inc1 = add nsw i32 %2, 1
+  store i32 %inc1, i32* %i, align 4
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  %3 = load i32, i32* %count, align 4
+  %sub = sub nsw i32 %3, 50
+  ret i32 %sub
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/test-logical.ll b/test/ExecutionEngine/OrcMCJIT/test-logical.ll
new file mode 100644
index 000000000000..9d53ac96e2fe
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-logical.ll
@@ -0,0 +1,18 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @main() {
+	%A = and i8 4, 8		; <i8> [#uses=2]
+	%B = or i8 %A, 7		; <i8> [#uses=1]
+	%C = xor i8 %B, %A		; <i8> [#uses=0]
+	%A.upgrd.1 = and i16 4, 8		; <i16> [#uses=2]
+	%B.upgrd.2 = or i16 %A.upgrd.1, 7		; <i16> [#uses=1]
+	%C.upgrd.3 = xor i16 %B.upgrd.2, %A.upgrd.1		; <i16> [#uses=0]
+	%A.upgrd.4 = and i32 4, 8		; <i32> [#uses=2]
+	%B.upgrd.5 = or i32 %A.upgrd.4, 7		; <i32> [#uses=1]
+	%C.upgrd.6 = xor i32 %B.upgrd.5, %A.upgrd.4		; <i32> [#uses=0]
+	%A.upgrd.7 = and i64 4, 8		; <i64> [#uses=2]
+	%B.upgrd.8 = or i64 %A.upgrd.7, 7		; <i64> [#uses=1]
+	%C.upgrd.9 = xor i64 %B.upgrd.8, %A.upgrd.7		; <i64> [#uses=0]
+	ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/test-loop.ll b/test/ExecutionEngine/OrcMCJIT/test-loop.ll
new file mode 100644
index 000000000000..dfb62d355e08
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-loop.ll
@@ -0,0 +1,14 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @main() {
+; <label>:0
+	br label %Loop
+Loop:		; preds = %Loop, %0
+	%I = phi i32 [ 0, %0 ], [ %i2, %Loop ]		; <i32> [#uses=1]
+	%i2 = add i32 %I, 1		; <i32> [#uses=2]
+	%C = icmp eq i32 %i2, 10		; <i1> [#uses=1]
+	br i1 %C, label %Out, label %Loop
+Out:		; preds = %Loop
+	ret i32 0
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/test-phi.ll b/test/ExecutionEngine/OrcMCJIT/test-phi.ll
new file mode 100644
index 000000000000..70bf8c82d448
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-phi.ll
@@ -0,0 +1,34 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+; test phi node
+@Y = global i32 6		; <i32*> [#uses=1]
+
+define void @blah(i32* %X) {
+; <label>:0
+	br label %T
+T:		; preds = %Dead, %0
+	phi i32* [ %X, %0 ], [ @Y, %Dead ]		; <i32*>:1 [#uses=0]
+	ret void
+Dead:		; No predecessors!
+	br label %T
+}
+
+define i32 @test(i1 %C) {
+; <label>:0
+	br i1 %C, label %T, label %T
+T:		; preds = %0, %0
+	%X = phi i32 [ 123, %0 ], [ 123, %0 ]		; <i32> [#uses=1]
+	ret i32 %X
+}
+
+define i32 @main() {
+; <label>:0
+	br label %Test
+Test:		; preds = %Dead, %0
+	%X = phi i32 [ 0, %0 ], [ %Y, %Dead ]		; <i32> [#uses=1]
+	ret i32 %X
+Dead:		; No predecessors!
+	%Y = ashr i32 12, 4		; <i32> [#uses=1]
+	br label %Test
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/test-ptr-reloc-sm-pic.ll b/test/ExecutionEngine/OrcMCJIT/test-ptr-reloc-sm-pic.ll
new file mode 100644
index 000000000000..6e0a425623b7
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-ptr-reloc-sm-pic.ll
@@ -0,0 +1,17 @@
+; RUN: %lli -jit-kind=orc-mcjit -O0 -relocation-model=pic -code-model=small %s
+; XFAIL: mips, aarch64, arm, i686, i386
+
+@.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
+@ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
+@.str1 = private unnamed_addr constant [6 x i8] c"data2\00", align 1
+@ptr2 = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), align 4
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly {
+entry:
+  %0 = load i8*, i8** @ptr, align 4
+  %1 = load i8*, i8** @ptr2, align 4
+  %cmp = icmp eq i8* %0, %1
+  %. = zext i1 %cmp to i32
+  ret i32 %.
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/test-ptr-reloc.ll b/test/ExecutionEngine/OrcMCJIT/test-ptr-reloc.ll
new file mode 100644
index 000000000000..a3846aa26e49
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-ptr-reloc.ll
@@ -0,0 +1,16 @@
+; RUN: %lli -jit-kind=orc-mcjit -O0 %s
+
+@.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
+@ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
+@.str1 = private unnamed_addr constant [6 x i8] c"data2\00", align 1
+@ptr2 = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), align 4
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly {
+entry:
+  %0 = load i8*, i8** @ptr, align 4
+  %1 = load i8*, i8** @ptr2, align 4
+  %cmp = icmp eq i8* %0, %1
+  %. = zext i1 %cmp to i32
+  ret i32 %.
+}
+
diff --git a/test/ExecutionEngine/OrcMCJIT/test-ret.ll b/test/ExecutionEngine/OrcMCJIT/test-ret.ll
new file mode 100644
index 000000000000..000bea02e97c
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-ret.ll
@@ -0,0 +1,46 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+; test return instructions
+define void @test1() {
+	ret void
+}
+
+define i8 @test2() {
+	ret i8 1
+}
+
+define i8 @test3() {
+	ret i8 1
+}
+
+define i16 @test4() {
+	ret i16 -1
+}
+
+define i16 @test5() {
+	ret i16 -1
+}
+
+define i32 @main() {
+	ret i32 0
+}
+
+define i32 @test6() {
+	ret i32 4
+}
+
+define i64 @test7() {
+	ret i64 0
+}
+
+define i64 @test8() {
+	ret i64 0
+}
+
+define float @test9() {
+	ret float 1.000000e+00
+}
+
+define double @test10() {
+	ret double 2.000000e+00
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/test-return.ll b/test/ExecutionEngine/OrcMCJIT/test-return.ll
new file mode 100644
index 000000000000..f7a1cdda0705
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-return.ll
@@ -0,0 +1,8 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @main() nounwind uwtable {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  ret i32 0
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/test-setcond-fp.ll b/test/ExecutionEngine/OrcMCJIT/test-setcond-fp.ll
new file mode 100644
index 000000000000..8514c8df820f
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-setcond-fp.ll
@@ -0,0 +1,24 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+
+define i32 @main() {
+	%double1 = fadd double 0.000000e+00, 0.000000e+00		; <double> [#uses=6]
+	%double2 = fadd double 0.000000e+00, 0.000000e+00		; <double> [#uses=6]
+	%float1 = fadd float 0.000000e+00, 0.000000e+00		; <float> [#uses=6]
+	%float2 = fadd float 0.000000e+00, 0.000000e+00		; <float> [#uses=6]
+	%test49 = fcmp oeq float %float1, %float2		; <i1> [#uses=0]
+	%test50 = fcmp oge float %float1, %float2		; <i1> [#uses=0]
+	%test51 = fcmp ogt float %float1, %float2		; <i1> [#uses=0]
+	%test52 = fcmp ole float %float1, %float2		; <i1> [#uses=0]
+	%test53 = fcmp olt float %float1, %float2		; <i1> [#uses=0]
+	%test54 = fcmp une float %float1, %float2		; <i1> [#uses=0]
+	%test55 = fcmp oeq double %double1, %double2		; <i1> [#uses=0]
+	%test56 = fcmp oge double %double1, %double2		; <i1> [#uses=0]
+	%test57 = fcmp ogt double %double1, %double2		; <i1> [#uses=0]
+	%test58 = fcmp ole double %double1, %double2		; <i1> [#uses=0]
+	%test59 = fcmp olt double %double1, %double2		; <i1> [#uses=0]
+	%test60 = fcmp une double %double1, %double2		; <i1> [#uses=0]
+	ret i32 0
+}
+
+
diff --git a/test/ExecutionEngine/OrcMCJIT/test-setcond-int.ll b/test/ExecutionEngine/OrcMCJIT/test-setcond-int.ll
new file mode 100644
index 000000000000..2f63d0bbef37
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-setcond-int.ll
@@ -0,0 +1,69 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @main() {
+	%int1 = add i32 0, 0		; <i32> [#uses=6]
+	%int2 = add i32 0, 0		; <i32> [#uses=6]
+	%long1 = add i64 0, 0		; <i64> [#uses=6]
+	%long2 = add i64 0, 0		; <i64> [#uses=6]
+	%sbyte1 = add i8 0, 0		; <i8> [#uses=6]
+	%sbyte2 = add i8 0, 0		; <i8> [#uses=6]
+	%short1 = add i16 0, 0		; <i16> [#uses=6]
+	%short2 = add i16 0, 0		; <i16> [#uses=6]
+	%ubyte1 = add i8 0, 0		; <i8> [#uses=6]
+	%ubyte2 = add i8 0, 0		; <i8> [#uses=6]
+	%uint1 = add i32 0, 0		; <i32> [#uses=6]
+	%uint2 = add i32 0, 0		; <i32> [#uses=6]
+	%ulong1 = add i64 0, 0		; <i64> [#uses=6]
+	%ulong2 = add i64 0, 0		; <i64> [#uses=6]
+	%ushort1 = add i16 0, 0		; <i16> [#uses=6]
+	%ushort2 = add i16 0, 0		; <i16> [#uses=6]
+	%test1 = icmp eq i8 %ubyte1, %ubyte2		; <i1> [#uses=0]
+	%test2 = icmp uge i8 %ubyte1, %ubyte2		; <i1> [#uses=0]
+	%test3 = icmp ugt i8 %ubyte1, %ubyte2		; <i1> [#uses=0]
+	%test4 = icmp ule i8 %ubyte1, %ubyte2		; <i1> [#uses=0]
+	%test5 = icmp ult i8 %ubyte1, %ubyte2		; <i1> [#uses=0]
+	%test6 = icmp ne i8 %ubyte1, %ubyte2		; <i1> [#uses=0]
+	%test7 = icmp eq i16 %ushort1, %ushort2		; <i1> [#uses=0]
+	%test8 = icmp uge i16 %ushort1, %ushort2		; <i1> [#uses=0]
+	%test9 = icmp ugt i16 %ushort1, %ushort2		; <i1> [#uses=0]
+	%test10 = icmp ule i16 %ushort1, %ushort2		; <i1> [#uses=0]
+	%test11 = icmp ult i16 %ushort1, %ushort2		; <i1> [#uses=0]
+	%test12 = icmp ne i16 %ushort1, %ushort2		; <i1> [#uses=0]
+	%test13 = icmp eq i32 %uint1, %uint2		; <i1> [#uses=0]
+	%test14 = icmp uge i32 %uint1, %uint2		; <i1> [#uses=0]
+	%test15 = icmp ugt i32 %uint1, %uint2		; <i1> [#uses=0]
+	%test16 = icmp ule i32 %uint1, %uint2		; <i1> [#uses=0]
+	%test17 = icmp ult i32 %uint1, %uint2		; <i1> [#uses=0]
+	%test18 = icmp ne i32 %uint1, %uint2		; <i1> [#uses=0]
+	%test19 = icmp eq i64 %ulong1, %ulong2		; <i1> [#uses=0]
+	%test20 = icmp uge i64 %ulong1, %ulong2		; <i1> [#uses=0]
+	%test21 = icmp ugt i64 %ulong1, %ulong2		; <i1> [#uses=0]
+	%test22 = icmp ule i64 %ulong1, %ulong2		; <i1> [#uses=0]
+	%test23 = icmp ult i64 %ulong1, %ulong2		; <i1> [#uses=0]
+	%test24 = icmp ne i64 %ulong1, %ulong2		; <i1> [#uses=0]
+	%test25 = icmp eq i8 %sbyte1, %sbyte2		; <i1> [#uses=0]
+	%test26 = icmp sge i8 %sbyte1, %sbyte2		; <i1> [#uses=0]
+	%test27 = icmp sgt i8 %sbyte1, %sbyte2		; <i1> [#uses=0]
+	%test28 = icmp sle i8 %sbyte1, %sbyte2		; <i1> [#uses=0]
+	%test29 = icmp slt i8 %sbyte1, %sbyte2		; <i1> [#uses=0]
+	%test30 = icmp ne i8 %sbyte1, %sbyte2		; <i1> [#uses=0]
+	%test31 = icmp eq i16 %short1, %short2		; <i1> [#uses=0]
+	%test32 = icmp sge i16 %short1, %short2		; <i1> [#uses=0]
+	%test33 = icmp sgt i16 %short1, %short2		; <i1> [#uses=0]
+	%test34 = icmp sle i16 %short1, %short2		; <i1> [#uses=0]
+	%test35 = icmp slt i16 %short1, %short2		; <i1> [#uses=0]
+	%test36 = icmp ne i16 %short1, %short2		; <i1> [#uses=0]
+	%test37 = icmp eq i32 %int1, %int2		; <i1> [#uses=0]
+	%test38 = icmp sge i32 %int1, %int2		; <i1> [#uses=0]
+	%test39 = icmp sgt i32 %int1, %int2		; <i1> [#uses=0]
+	%test40 = icmp sle i32 %int1, %int2		; <i1> [#uses=0]
+	%test41 = icmp slt i32 %int1, %int2		; <i1> [#uses=0]
+	%test42 = icmp ne i32 %int1, %int2		; <i1> [#uses=0]
+	%test43 = icmp eq i64 %long1, %long2		; <i1> [#uses=0]
+	%test44 = icmp sge i64 %long1, %long2		; <i1> [#uses=0]
+	%test45 = icmp sgt i64 %long1, %long2		; <i1> [#uses=0]
+	%test46 = icmp sle i64 %long1, %long2		; <i1> [#uses=0]
+	%test47 = icmp slt i64 %long1, %long2		; <i1> [#uses=0]
+	%test48 = icmp ne i64 %long1, %long2		; <i1> [#uses=0]
+	ret i32 0
+}
diff --git a/test/ExecutionEngine/OrcMCJIT/test-shift.ll b/test/ExecutionEngine/OrcMCJIT/test-shift.ll
new file mode 100644
index 000000000000..2d064211cf54
--- /dev/null
+++ b/test/ExecutionEngine/OrcMCJIT/test-shift.ll
@@ -0,0 +1,32 @@
+; RUN: %lli -jit-kind=orc-mcjit %s > /dev/null
+
+define i32 @main() {
+	%shamt = add i8 0, 1		; <i8> [#uses=8]
+	%shift.upgrd.1 = zext i8 %shamt to i32		; <i32> [#uses=1]
+	%t1.s = shl i32 1, %shift.upgrd.1		; <i32> [#uses=0]
+	%t2.s = shl i32 1, 4		; <i32> [#uses=0]
+	%shift.upgrd.2 = zext i8 %shamt to i32		; <i32> [#uses=1]
+	%t1 = shl i32 1, %shift.upgrd.2		; <i32> [#uses=0]
+	%t2 = shl i32 1, 5		; <i32> [#uses=0]
+	%t2.s.upgrd.3 = shl i64 1, 4		; <i64> [#uses=0]
+	%t2.upgrd.4 = shl i64 1, 5		; <i64> [#uses=0]
+	%shift.upgrd.5 = zext i8 %shamt to i32		; <i32> [#uses=1]
+	%tr1.s = ashr i32 1, %shift.upgrd.5		; <i32> [#uses=0]
+	%tr2.s = ashr i32 1, 4		; <i32> [#uses=0]
+	%shift.upgrd.6 = zext i8 %shamt to i32		; <i32> [#uses=1]
+	%tr1 = lshr i32 1, %shift.upgrd.6		; <i32> [#uses=0]
+	%tr2 = lshr i32 1, 5		; <i32> [#uses=0]
+	%tr1.l = ashr i64 1, 4		; <i64> [#uses=0]
+	%shift.upgrd.7 = zext i8 %shamt to i64		; <i64> [#uses=1]
+	%tr2.l = ashr i64 1, %shift.upgrd.7		; <i64> [#uses=0]
+	%tr3.l = shl i64 1, 4		; <i64> [#uses=0]
+	%shift.upgrd.8 = zext i8 %shamt to i64		; <i64> [#uses=1]
+	%tr4.l = shl i64 1, %shift.upgrd.8		; <i64> [#uses=0]
+	%tr1.u = lshr i64 1, 5		; <i64> [#uses=0]
+	%shift.upgrd.9 = zext i8 %shamt to i64		; <i64> [#uses=1]
+	%tr2.u = lshr i64 1, %shift.upgrd.9		; <i64> [#uses=0]
+	%tr3.u = shl i64 1, 5		; <i64> [#uses=0]
+	%shift.upgrd.10 = zext i8 %shamt to i64		; <i64> [#uses=1]
+	%tr4.u = shl i64 1, %shift.upgrd.10		; <i64> [#uses=0]
+	ret i32 0
+}
diff --git a/test/ExecutionEngine/RuntimeDyld/X86/COFF_x86_64 b/test/ExecutionEngine/RuntimeDyld/X86/COFF_x86_64
new file mode 100644
index 000000000000..7029cf437c5e
--- /dev/null
+++ b/test/ExecutionEngine/RuntimeDyld/X86/COFF_x86_64
@@ -0,0 +1,31 @@
+# RUN: llvm-mc -triple=x86_64-pc-win32 -filetype=obj -o %T/COFF_x86_64.o %s
+# RUN: llvm-rtdyld -triple=x86_64-pc-win32 -verify -check=%s %/T/COFF_x86_64.o
+        	.text
+	.def	 F;
+	.scl	2;
+	.type	32;
+	.endef
+	.globl	__real400921f9f01b866e
+	.section	.rdata,"dr",discard,__real400921f9f01b866e
+	.align	8
+__real400921f9f01b866e:
+	.quad	4614256650576692846     # double 3.1415899999999999
+	.text
+	.globl	F
+        .global inst1
+	.align	16, 0x90
+F:                                      # @F
+.Ltmp0:
+.seh_proc F
+# BB#0:                                 # %entry
+.Ltmp1:
+	.seh_endprologue
+# rtdyld-check: decode_operand(inst1, 4) = __real400921f9f01b866e - next_pc(inst1)
+inst1:
+	movsd	__real400921f9f01b866e(%rip), %xmm0 # xmm0 = mem[0],zero
+	retq
+.Leh_func_end0:
+.Ltmp2:
+	.seh_endproc
+
+
diff --git a/test/ExecutionEngine/RuntimeDyld/X86/ELF_x64-64_PIC_relocations.s b/test/ExecutionEngine/RuntimeDyld/X86/ELF_x64-64_PIC_relocations.s
new file mode 100644
index 000000000000..75989671a204
--- /dev/null
+++ b/test/ExecutionEngine/RuntimeDyld/X86/ELF_x64-64_PIC_relocations.s
@@ -0,0 +1,31 @@
+# RUN: llvm-mc -triple=x86_64-pc-linux -relocation-model=pic -filetype=obj -o %T/test_ELF1_x86-64.o %s
+# RUN: llvm-mc -triple=x86_64-pc-linux -relocation-model=pic -filetype=obj -o %T/test_ELF2_x86-64.o %s
+# RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -filetype=obj -o %T/test_ELF_ExternalGlobal_x86-64.o %S/Inputs/ExternalGlobal.ll
+# RUN: llvm-rtdyld -triple=x86_64-pc-linux -verify %T/test_ELF1_x86-64.o  %T/test_ELF_ExternalGlobal_x86-64.o
+# Test that we can load this code twice at memory locations more than 2GB apart
+# RUN: llvm-rtdyld -triple=x86_64-pc-linux -verify -map-section test_ELF1_x86-64.o,.got=0x10000 -map-section test_ELF2_x86-64.o,.text=0x100000000 -map-section test_ELF2_x86-64.o,.got=0x100010000 %T/test_ELF1_x86-64.o %T/test_ELF2_x86-64.o %T/test_ELF_ExternalGlobal_x86-64.o
+
+# Assembly obtained by compiling the following and adding checks:
+# @G = external global i8*
+#
+# define i8* @foo() {
+#    %ret = load i8** @G
+#    ret i32 %ret
+# }
+#
+
+#
+	.text
+	.file	"ELF_x64-64_PIC_relocations.ll"
+	.align	16, 0x90
+	.type	foo,@function
+foo:                                    # @foo
+# BB#0:
+	movq	G@GOTPCREL(%rip), %rax
+	movl	(%rax), %eax
+	retq
+.Ltmp0:
+	.size	foo, .Ltmp0-foo
+
+
+	.section	".note.GNU-stack","",@progbits
diff --git a/test/ExecutionEngine/RuntimeDyld/X86/Inputs/ExternalGlobal.ll b/test/ExecutionEngine/RuntimeDyld/X86/Inputs/ExternalGlobal.ll
new file mode 100644
index 000000000000..51002aa37bb0
--- /dev/null
+++ b/test/ExecutionEngine/RuntimeDyld/X86/Inputs/ExternalGlobal.ll
@@ -0,0 +1,2 @@
+@F = global i8 0
+@G = global i8* @F
diff --git a/test/ExecutionEngine/fma3-jit.ll b/test/ExecutionEngine/fma3-jit.ll
index 25eaa65a538b..b68b7aeb6e4f 100644
--- a/test/ExecutionEngine/fma3-jit.ll
+++ b/test/ExecutionEngine/fma3-jit.ll
@@ -9,8 +9,8 @@ declare i32 @printf(i8*, ...)
 define i32 @main() {
   %fma = tail call double @llvm.fma.f64(double 3.0, double 3.0, double 3.0) nounwind readnone
 
-  %ptr1 = getelementptr [4 x i8]* @msg_double, i32 0, i32 0
-  call i32 (i8*,...)* @printf(i8* %ptr1, double %fma)
+  %ptr1 = getelementptr [4 x i8], [4 x i8]* @msg_double, i32 0, i32 0
+  call i32 (i8*,...) @printf(i8* %ptr1, double %fma)
 
   ret i32 0
 }
diff --git a/test/ExecutionEngine/fpbitcast.ll b/test/ExecutionEngine/fpbitcast.ll
deleted file mode 100644
index e6d06f83db49..000000000000
--- a/test/ExecutionEngine/fpbitcast.ll
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: %lli -force-interpreter=true %s | FileCheck %s
-; CHECK: 40091eb8
-
-define i32 @test(double %x) {
-entry:
-	%x46.i = bitcast double %x to i64	
-	%tmp343.i = lshr i64 %x46.i, 32	
-	%tmp344.i = trunc i64 %tmp343.i to i32
-        ret i32 %tmp344.i
-}
-
-define i32 @main()
-{
-       %res = call i32 @test(double 3.14)
-       %ptr = getelementptr [4 x i8]* @format, i32 0, i32 0
-       call i32 (i8*,...)* @printf(i8* %ptr, i32 %res)
-       ret i32 0
-}
-
-declare i32 @printf(i8*, ...)
-@format = internal constant [4 x i8] c"%x\0A\00"
diff --git a/test/ExecutionEngine/frem.ll b/test/ExecutionEngine/frem.ll
index 7e0b6060f6fe..aedaae38baac 100644
--- a/test/ExecutionEngine/frem.ll
+++ b/test/ExecutionEngine/frem.ll
@@ -8,12 +8,14 @@
 @str = internal constant [18 x i8] c"Double value: %f\0A\00"
 
 declare i32 @printf(i8* nocapture, ...) nounwind
+declare i32 @fflush(i8*) nounwind
 
 define i32 @main() {
-  %flt = load float* @flt
+  %flt = load float, float* @flt
   %float2 = frem float %flt, 5.0
   %double1 = fpext float %float2 to double
-  call i32 (i8*, ...)* @printf(i8* getelementptr ([18 x i8]* @str, i32 0, i64 0), double %double1)
+  call i32 (i8*, ...) @printf(i8* getelementptr ([18 x i8], [18 x i8]* @str, i32 0, i64 0), double %double1)
+  call i32 @fflush(i8* null)
   ret i32 0
 }
 
diff --git a/test/ExecutionEngine/hello.ll b/test/ExecutionEngine/hello.ll
deleted file mode 100644
index 47e36a589563..000000000000
--- a/test/ExecutionEngine/hello.ll
+++ /dev/null
@@ -1,11 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-@.LC0 = internal global [12 x i8] c"Hello World\00"		; <[12 x i8]*> [#uses=1]
-
-declare i32 @puts(i8*)
-
-define i32 @main() {
-	%reg210 = call i32 @puts( i8* getelementptr ([12 x i8]* @.LC0, i64 0, i64 0) )		; <i32> [#uses=0]
-	ret i32 0
-}
-
diff --git a/test/ExecutionEngine/hello2.ll b/test/ExecutionEngine/hello2.ll
deleted file mode 100644
index 13b25884fee7..000000000000
--- a/test/ExecutionEngine/hello2.ll
+++ /dev/null
@@ -1,17 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-@X = global i32 7		; <i32*> [#uses=0]
-@msg = internal global [13 x i8] c"Hello World\0A\00"		; <[13 x i8]*> [#uses=1]
-
-declare void @printf([13 x i8]*, ...)
-
-define void @bar() {
-	call void ([13 x i8]*, ...)* @printf( [13 x i8]* @msg )
-	ret void
-}
-
-define i32 @main() {
-	call void @bar( )
-	ret i32 0
-}
-
diff --git a/test/ExecutionEngine/simplesttest.ll b/test/ExecutionEngine/simplesttest.ll
deleted file mode 100644
index 85c171532752..000000000000
--- a/test/ExecutionEngine/simplesttest.ll
+++ /dev/null
@@ -1,6 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @main() {
-	ret i32 0
-}
-
diff --git a/test/ExecutionEngine/simpletest.ll b/test/ExecutionEngine/simpletest.ll
deleted file mode 100644
index 167a0fdfd130..000000000000
--- a/test/ExecutionEngine/simpletest.ll
+++ /dev/null
@@ -1,11 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @bar() {
-	ret i32 0
-}
-
-define i32 @main() {
-	%r = call i32 @bar( )		; <i32> [#uses=1]
-	ret i32 %r
-}
-
diff --git a/test/ExecutionEngine/stubs.ll b/test/ExecutionEngine/stubs.ll
deleted file mode 100644
index b7d922f2cb6d..000000000000
--- a/test/ExecutionEngine/stubs.ll
+++ /dev/null
@@ -1,35 +0,0 @@
-; RUN: %lli -disable-lazy-compilation=false %s
-
-define i32 @main() nounwind {
-entry:
-	call void @lazily_compiled_address_is_consistent()
-	ret i32 0
-}
-
-; Test PR3043: @test should have the same address before and after
-; it's JIT-compiled.
-@funcPtr = common global i1 ()* null, align 4
-@lcaic_failure = internal constant [46 x i8] c"@lazily_compiled_address_is_consistent failed\00"
-
-define void @lazily_compiled_address_is_consistent() nounwind {
-entry:
-	store i1 ()* @test, i1 ()** @funcPtr
-	%pass = tail call i1 @test()		; <i32> [#uses=1]
-	br i1 %pass, label %pass_block, label %fail_block
-pass_block:
-	ret void
-fail_block:
-	call i32 @puts(i8* getelementptr([46 x i8]* @lcaic_failure, i32 0, i32 0))
-	call void @exit(i32 1)
-	unreachable
-}
-
-define i1 @test() nounwind {
-entry:
-	%tmp = load i1 ()** @funcPtr
-	%eq = icmp eq i1 ()* %tmp, @test
-	ret i1 %eq
-}
-
-declare i32 @puts(i8*) noreturn
-declare void @exit(i32) noreturn
diff --git a/test/ExecutionEngine/test-arith.ll b/test/ExecutionEngine/test-arith.ll
deleted file mode 100644
index 79f989f7265b..000000000000
--- a/test/ExecutionEngine/test-arith.ll
+++ /dev/null
@@ -1,34 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @main() {
-	%A = add i8 0, 12		; <i8> [#uses=1]
-	%B = sub i8 %A, 1		; <i8> [#uses=2]
-	%C = mul i8 %B, %B		; <i8> [#uses=2]
-	%D = sdiv i8 %C, %C		; <i8> [#uses=2]
-	%E = srem i8 %D, %D		; <i8> [#uses=0]
-	%F = udiv i8 5, 6		; <i8> [#uses=0]
-	%G = urem i8 6, 5		; <i8> [#uses=0]
-	%A.upgrd.1 = add i16 0, 12		; <i16> [#uses=1]
-	%B.upgrd.2 = sub i16 %A.upgrd.1, 1		; <i16> [#uses=2]
-	%C.upgrd.3 = mul i16 %B.upgrd.2, %B.upgrd.2		; <i16> [#uses=2]
-	%D.upgrd.4 = sdiv i16 %C.upgrd.3, %C.upgrd.3		; <i16> [#uses=2]
-	%E.upgrd.5 = srem i16 %D.upgrd.4, %D.upgrd.4		; <i16> [#uses=0]
-	%F.upgrd.6 = udiv i16 5, 6		; <i16> [#uses=0]
-	%G.upgrd.7 = urem i32 6, 5		; <i32> [#uses=0]
-	%A.upgrd.8 = add i32 0, 12		; <i32> [#uses=1]
-	%B.upgrd.9 = sub i32 %A.upgrd.8, 1		; <i32> [#uses=2]
-	%C.upgrd.10 = mul i32 %B.upgrd.9, %B.upgrd.9		; <i32> [#uses=2]
-	%D.upgrd.11 = sdiv i32 %C.upgrd.10, %C.upgrd.10		; <i32> [#uses=2]
-	%E.upgrd.12 = srem i32 %D.upgrd.11, %D.upgrd.11		; <i32> [#uses=0]
-	%F.upgrd.13 = udiv i32 5, 6		; <i32> [#uses=0]
-	%G1 = urem i32 6, 5		; <i32> [#uses=0]
-	%A.upgrd.14 = add i64 0, 12		; <i64> [#uses=1]
-	%B.upgrd.15 = sub i64 %A.upgrd.14, 1		; <i64> [#uses=2]
-	%C.upgrd.16 = mul i64 %B.upgrd.15, %B.upgrd.15		; <i64> [#uses=2]
-	%D.upgrd.17 = sdiv i64 %C.upgrd.16, %C.upgrd.16		; <i64> [#uses=2]
-	%E.upgrd.18 = srem i64 %D.upgrd.17, %D.upgrd.17		; <i64> [#uses=0]
-	%F.upgrd.19 = udiv i64 5, 6		; <i64> [#uses=0]
-	%G.upgrd.20 = urem i64 6, 5		; <i64> [#uses=0]
-	ret i32 0
-}
-
diff --git a/test/ExecutionEngine/test-branch.ll b/test/ExecutionEngine/test-branch.ll
deleted file mode 100644
index 3ae55d069b3d..000000000000
--- a/test/ExecutionEngine/test-branch.ll
+++ /dev/null
@@ -1,12 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-; test unconditional branch
-define i32 @main() {
-	br label %Test
-Test:		; preds = %Test, %0
-	%X = icmp eq i32 0, 4		; <i1> [#uses=1]
-	br i1 %X, label %Test, label %Label
-Label:		; preds = %Test
-	ret i32 0
-}
-
diff --git a/test/ExecutionEngine/test-call-no-external-funcs.ll b/test/ExecutionEngine/test-call-no-external-funcs.ll
deleted file mode 100644
index c3cb93121f6b..000000000000
--- a/test/ExecutionEngine/test-call-no-external-funcs.ll
+++ /dev/null
@@ -1,14 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @_Z14func_exit_codev() nounwind uwtable {
-entry:
-  ret i32 0
-}
-
-define i32 @main() nounwind uwtable {
-entry:
-  %retval = alloca i32, align 4
-  store i32 0, i32* %retval
-  %call = call i32 @_Z14func_exit_codev()
-  ret i32 %call
-}
diff --git a/test/ExecutionEngine/test-call.ll b/test/ExecutionEngine/test-call.ll
deleted file mode 100644
index 313a6c52367d..000000000000
--- a/test/ExecutionEngine/test-call.ll
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-declare void @exit(i32)
-
-define i32 @test(i8 %C, i16 %S) {
-	%X = trunc i16 %S to i8		; <i8> [#uses=1]
-	%Y = zext i8 %X to i32		; <i32> [#uses=1]
-	ret i32 %Y
-}
-
-define void @FP(void (i32)* %F) {
-	%X = call i32 @test( i8 123, i16 1024 )		; <i32> [#uses=1]
-	call void %F( i32 %X )
-	ret void
-}
-
-define i32 @main() {
-	call void @FP( void (i32)* @exit )
-	ret i32 1
-}
-
diff --git a/test/ExecutionEngine/test-cast.ll b/test/ExecutionEngine/test-cast.ll
deleted file mode 100644
index 667fa80a4897..000000000000
--- a/test/ExecutionEngine/test-cast.ll
+++ /dev/null
@@ -1,109 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @foo() {
-	ret i32 0
-}
-
-define i32 @main() {
-	icmp ne i1 true, false		; <i1>:1 [#uses=0]
-	zext i1 true to i8		; <i8>:2 [#uses=0]
-	zext i1 true to i8		; <i8>:3 [#uses=0]
-	zext i1 true to i16		; <i16>:4 [#uses=0]
-	zext i1 true to i16		; <i16>:5 [#uses=0]
-	zext i1 true to i32		; <i32>:6 [#uses=0]
-	zext i1 true to i32		; <i32>:7 [#uses=0]
-	zext i1 true to i64		; <i64>:8 [#uses=0]
-	zext i1 true to i64		; <i64>:9 [#uses=0]
-	uitofp i1 true to float		; <float>:10 [#uses=0]
-	uitofp i1 true to double		; <double>:11 [#uses=0]
-	icmp ne i8 0, 0		; <i1>:12 [#uses=0]
-	icmp ne i8 1, 0		; <i1>:13 [#uses=0]
-	bitcast i8 0 to i8		; <i8>:14 [#uses=0]
-	bitcast i8 -1 to i8		; <i8>:15 [#uses=0]
-	sext i8 4 to i16		; <i16>:16 [#uses=0]
-	sext i8 4 to i16		; <i16>:17 [#uses=0]
-	sext i8 4 to i64		; <i64>:18 [#uses=0]
-	sext i8 4 to i64		; <i64>:19 [#uses=0]
-	sitofp i8 4 to float		; <float>:20 [#uses=0]
-	sitofp i8 4 to double		; <double>:21 [#uses=0]
-	icmp ne i8 0, 0		; <i1>:22 [#uses=0]
-	icmp ne i8 1, 0		; <i1>:23 [#uses=0]
-	bitcast i8 0 to i8		; <i8>:24 [#uses=0]
-	bitcast i8 1 to i8		; <i8>:25 [#uses=0]
-	zext i8 4 to i16		; <i16>:26 [#uses=0]
-	zext i8 4 to i16		; <i16>:27 [#uses=0]
-	zext i8 4 to i64		; <i64>:28 [#uses=0]
-	zext i8 4 to i64		; <i64>:29 [#uses=0]
-	uitofp i8 0 to float		; <float>:30 [#uses=0]
-	uitofp i8 0 to double		; <double>:31 [#uses=0]
-	icmp ne i16 1, 0		; <i1>:32 [#uses=0]
-	trunc i16 -1 to i8		; <i8>:33 [#uses=0]
-	trunc i16 255 to i8		; <i8>:34 [#uses=0]
-	bitcast i16 0 to i16		; <i16>:35 [#uses=0]
-	bitcast i16 0 to i16		; <i16>:36 [#uses=0]
-	sext i16 0 to i64		; <i64>:37 [#uses=0]
-	sext i16 0 to i64		; <i64>:38 [#uses=0]
-	sitofp i16 0 to float		; <float>:39 [#uses=0]
-	sitofp i16 0 to double		; <double>:40 [#uses=0]
-	icmp ne i16 1, 0		; <i1>:41 [#uses=0]
-	trunc i16 1 to i8		; <i8>:42 [#uses=0]
-	trunc i16 255 to i8		; <i8>:43 [#uses=0]
-	bitcast i16 0 to i16		; <i16>:44 [#uses=0]
-	bitcast i16 0 to i16		; <i16>:45 [#uses=0]
-	zext i16 0 to i64		; <i64>:46 [#uses=0]
-	zext i16 0 to i64		; <i64>:47 [#uses=0]
-	uitofp i16 0 to float		; <float>:48 [#uses=0]
-	uitofp i16 0 to double		; <double>:49 [#uses=0]
-	icmp ne i32 6, 0		; <i1>:50 [#uses=0]
-	trunc i32 -6 to i8		; <i8>:51 [#uses=0]
-	trunc i32 6 to i8		; <i8>:52 [#uses=0]
-	trunc i32 6 to i16		; <i16>:53 [#uses=0]
-	bitcast i32 0 to i32		; <i32>:54 [#uses=0]
-	sext i32 0 to i64		; <i64>:55 [#uses=0]
-	sext i32 0 to i64		; <i64>:56 [#uses=0]
-	sitofp i32 0 to float		; <float>:57 [#uses=0]
-	sitofp i32 0 to double		; <double>:58 [#uses=0]
-	icmp ne i32 6, 0		; <i1>:59 [#uses=0]
-	trunc i32 7 to i8		; <i8>:60 [#uses=0]
-	trunc i32 8 to i8		; <i8>:61 [#uses=0]
-	trunc i32 9 to i16		; <i16>:62 [#uses=0]
-	bitcast i32 10 to i32		; <i32>:63 [#uses=0]
-	zext i32 0 to i64		; <i64>:64 [#uses=0]
-	zext i32 0 to i64		; <i64>:65 [#uses=0]
-	uitofp i32 0 to float		; <float>:66 [#uses=0]
-	uitofp i32 0 to double		; <double>:67 [#uses=0]
-	icmp ne i64 0, 0		; <i1>:68 [#uses=0]
-	trunc i64 0 to i8		; <i8>:69 [#uses=0]
-	trunc i64 0 to i8		; <i8>:70 [#uses=0]
-	trunc i64 0 to i16		; <i16>:71 [#uses=0]
-	trunc i64 0 to i16		; <i16>:72 [#uses=0]
-	trunc i64 0 to i32		; <i32>:73 [#uses=0]
-	trunc i64 0 to i32		; <i32>:74 [#uses=0]
-	bitcast i64 0 to i64		; <i64>:75 [#uses=0]
-	bitcast i64 0 to i64		; <i64>:76 [#uses=0]
-	sitofp i64 0 to float		; <float>:77 [#uses=0]
-	sitofp i64 0 to double		; <double>:78 [#uses=0]
-	icmp ne i64 1, 0		; <i1>:79 [#uses=0]
-	trunc i64 1 to i8		; <i8>:80 [#uses=0]
-	trunc i64 1 to i8		; <i8>:81 [#uses=0]
-	trunc i64 1 to i16		; <i16>:82 [#uses=0]
-	trunc i64 1 to i16		; <i16>:83 [#uses=0]
-	trunc i64 1 to i32		; <i32>:84 [#uses=0]
-	trunc i64 1 to i32		; <i32>:85 [#uses=0]
-	bitcast i64 1 to i64		; <i64>:86 [#uses=0]
-	bitcast i64 1 to i64		; <i64>:87 [#uses=0]
-	uitofp i64 1 to float		; <float>:88 [#uses=0]
-	uitofp i64 0 to double		; <double>:89 [#uses=0]
-	bitcast float 0.000000e+00 to float		; <float>:90 [#uses=0]
-	fpext float 0.000000e+00 to double		; <double>:91 [#uses=0]
-	fptosi double 0.000000e+00 to i8		; <i8>:92 [#uses=0]
-	fptoui double 0.000000e+00 to i8		; <i8>:93 [#uses=0]
-	fptosi double 0.000000e+00 to i16		; <i16>:94 [#uses=0]
-	fptoui double 0.000000e+00 to i16		; <i16>:95 [#uses=0]
-	fptosi double 0.000000e+00 to i32		; <i32>:96 [#uses=0]
-	fptoui double 0.000000e+00 to i32		; <i32>:97 [#uses=0]
-	fptosi double 0.000000e+00 to i64		; <i64>:98 [#uses=0]
-	fptrunc double 0.000000e+00 to float		; <float>:99 [#uses=0]
-	bitcast double 0.000000e+00 to double		; <double>:100 [#uses=0]
-	ret i32 0
-}
diff --git a/test/ExecutionEngine/test-common-symbols.ll b/test/ExecutionEngine/test-common-symbols.ll
deleted file mode 100644
index 19e2ce584689..000000000000
--- a/test/ExecutionEngine/test-common-symbols.ll
+++ /dev/null
@@ -1,88 +0,0 @@
-; RUN: %lli -O0 -disable-lazy-compilation=false %s
-
-; The intention of this test is to verify that symbols mapped to COMMON in ELF
-; work as expected.
-;
-; Compiled from this C code:
-;
-; int zero_int;
-; double zero_double;
-; int zero_arr[10];
-; 
-; int main()
-; {
-;     zero_arr[zero_int + 5] = 40;
-; 
-;     if (zero_double < 1.0)
-;         zero_arr[zero_int + 2] = 70;
-; 
-;     for (int i = 1; i < 10; ++i) {
-;         zero_arr[i] = zero_arr[i - 1] + zero_arr[i];
-;     }
-;     return zero_arr[9] == 110 ? 0 : -1;
-; }
-
-@zero_int = common global i32 0, align 4
-@zero_arr = common global [10 x i32] zeroinitializer, align 16
-@zero_double = common global double 0.000000e+00, align 8
-
-define i32 @main() nounwind {
-entry:
-  %retval = alloca i32, align 4
-  %i = alloca i32, align 4
-  store i32 0, i32* %retval
-  %0 = load i32* @zero_int, align 4
-  %add = add nsw i32 %0, 5
-  %idxprom = sext i32 %add to i64
-  %arrayidx = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom
-  store i32 40, i32* %arrayidx, align 4
-  %1 = load double* @zero_double, align 8
-  %cmp = fcmp olt double %1, 1.000000e+00
-  br i1 %cmp, label %if.then, label %if.end
-
-if.then:                                          ; preds = %entry
-  %2 = load i32* @zero_int, align 4
-  %add1 = add nsw i32 %2, 2
-  %idxprom2 = sext i32 %add1 to i64
-  %arrayidx3 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom2
-  store i32 70, i32* %arrayidx3, align 4
-  br label %if.end
-
-if.end:                                           ; preds = %if.then, %entry
-  store i32 1, i32* %i, align 4
-  br label %for.cond
-
-for.cond:                                         ; preds = %for.inc, %if.end
-  %3 = load i32* %i, align 4
-  %cmp4 = icmp slt i32 %3, 10
-  br i1 %cmp4, label %for.body, label %for.end
-
-for.body:                                         ; preds = %for.cond
-  %4 = load i32* %i, align 4
-  %sub = sub nsw i32 %4, 1
-  %idxprom5 = sext i32 %sub to i64
-  %arrayidx6 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom5
-  %5 = load i32* %arrayidx6, align 4
-  %6 = load i32* %i, align 4
-  %idxprom7 = sext i32 %6 to i64
-  %arrayidx8 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom7
-  %7 = load i32* %arrayidx8, align 4
-  %add9 = add nsw i32 %5, %7
-  %8 = load i32* %i, align 4
-  %idxprom10 = sext i32 %8 to i64
-  %arrayidx11 = getelementptr inbounds [10 x i32]* @zero_arr, i32 0, i64 %idxprom10
-  store i32 %add9, i32* %arrayidx11, align 4
-  br label %for.inc
-
-for.inc:                                          ; preds = %for.body
-  %9 = load i32* %i, align 4
-  %inc = add nsw i32 %9, 1
-  store i32 %inc, i32* %i, align 4
-  br label %for.cond
-
-for.end:                                          ; preds = %for.cond
-  %10 = load i32* getelementptr inbounds ([10 x i32]* @zero_arr, i32 0, i64 9), align 4
-  %cmp12 = icmp eq i32 %10, 110
-  %cond = select i1 %cmp12, i32 0, i32 -1
-  ret i32 %cond
-}
diff --git a/test/ExecutionEngine/test-constantexpr.ll b/test/ExecutionEngine/test-constantexpr.ll
deleted file mode 100644
index d01479a86cdc..000000000000
--- a/test/ExecutionEngine/test-constantexpr.ll
+++ /dev/null
@@ -1,12 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-; This tests to make sure that we can evaluate weird constant expressions
-
-@A = global i32 5		; <i32*> [#uses=1]
-@B = global i32 6		; <i32*> [#uses=1]
-
-define i32 @main() {
-	%A = or i1 false, icmp slt (i32* @A, i32* @B)		; <i1> [#uses=0]
-	ret i32 0
-}
-
diff --git a/test/ExecutionEngine/test-fp-no-external-funcs.ll b/test/ExecutionEngine/test-fp-no-external-funcs.ll
deleted file mode 100644
index 61b12c2abeb7..000000000000
--- a/test/ExecutionEngine/test-fp-no-external-funcs.ll
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: %lli  %s > /dev/null
-
-define double @test(double* %DP, double %Arg) {
-	%D = load double* %DP		; <double> [#uses=1]
-	%V = fadd double %D, 1.000000e+00		; <double> [#uses=2]
-	%W = fsub double %V, %V		; <double> [#uses=3]
-	%X = fmul double %W, %W		; <double> [#uses=2]
-	%Y = fdiv double %X, %X		; <double> [#uses=2]
-	%Q = fadd double %Y, %Arg		; <double> [#uses=1]
-	%R = bitcast double %Q to double		; <double> [#uses=1]
-	store double %Q, double* %DP
-	ret double %Y
-}
-
-define i32 @main() {
-	%X = alloca double		; <double*> [#uses=2]
-	store double 0.000000e+00, double* %X
-	call double @test( double* %X, double 2.000000e+00 )		; <double>:1 [#uses=0]
-	ret i32 0
-}
-
diff --git a/test/ExecutionEngine/test-fp.ll b/test/ExecutionEngine/test-fp.ll
deleted file mode 100644
index 2bf0210d8b00..000000000000
--- a/test/ExecutionEngine/test-fp.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define double @test(double* %DP, double %Arg) {
-	%D = load double* %DP		; <double> [#uses=1]
-	%V = fadd double %D, 1.000000e+00		; <double> [#uses=2]
-	%W = fsub double %V, %V		; <double> [#uses=3]
-	%X = fmul double %W, %W		; <double> [#uses=2]
-	%Y = fdiv double %X, %X		; <double> [#uses=2]
-	%Z = frem double %Y, %Y		; <double> [#uses=3]
-	%Z1 = fdiv double %Z, %W		; <double> [#uses=0]
-	%Q = fadd double %Z, %Arg		; <double> [#uses=1]
-	%R = bitcast double %Q to double		; <double> [#uses=1]
-	store double %R, double* %DP
-	ret double %Z
-}
-
-define i32 @main() {
-	%X = alloca double		; <double*> [#uses=2]
-	store double 0.000000e+00, double* %X
-	call double @test( double* %X, double 2.000000e+00 )		; <double>:1 [#uses=0]
-	ret i32 0
-}
-
diff --git a/test/ExecutionEngine/test-global-init-nonzero.ll b/test/ExecutionEngine/test-global-init-nonzero.ll
deleted file mode 100644
index 749a4851c5d6..000000000000
--- a/test/ExecutionEngine/test-global-init-nonzero.ll
+++ /dev/null
@@ -1,34 +0,0 @@
-; RUN: %lli  %s > /dev/null
-
-@count = global i32 1, align 4
-
-define i32 @main() nounwind uwtable {
-entry:
-  %retval = alloca i32, align 4
-  %i = alloca i32, align 4
-  store i32 0, i32* %retval
-  store i32 0, i32* %i, align 4
-  br label %for.cond
-
-for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
-  %cmp = icmp slt i32 %0, 49
-  br i1 %cmp, label %for.body, label %for.end
-
-for.body:                                         ; preds = %for.cond
-  %1 = load i32* @count, align 4
-  %inc = add nsw i32 %1, 1
-  store i32 %inc, i32* @count, align 4
-  br label %for.inc
-
-for.inc:                                          ; preds = %for.body
-  %2 = load i32* %i, align 4
-  %inc1 = add nsw i32 %2, 1
-  store i32 %inc1, i32* %i, align 4
-  br label %for.cond
-
-for.end:                                          ; preds = %for.cond
-  %3 = load i32* @count, align 4
-  %sub = sub nsw i32 %3, 50
-  ret i32 %sub
-}
diff --git a/test/ExecutionEngine/test-global.ll b/test/ExecutionEngine/test-global.ll
deleted file mode 100644
index 69e545555649..000000000000
--- a/test/ExecutionEngine/test-global.ll
+++ /dev/null
@@ -1,34 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-@count = global i32 0, align 4
-
-define i32 @main() nounwind uwtable {
-entry:
-  %retval = alloca i32, align 4
-  %i = alloca i32, align 4
-  store i32 0, i32* %retval
-  store i32 0, i32* %i, align 4
-  br label %for.cond
-
-for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
-  %cmp = icmp slt i32 %0, 50
-  br i1 %cmp, label %for.body, label %for.end
-
-for.body:                                         ; preds = %for.cond
-  %1 = load i32* @count, align 4
-  %inc = add nsw i32 %1, 1
-  store i32 %inc, i32* @count, align 4
-  br label %for.inc
-
-for.inc:                                          ; preds = %for.body
-  %2 = load i32* %i, align 4
-  %inc1 = add nsw i32 %2, 1
-  store i32 %inc1, i32* %i, align 4
-  br label %for.cond
-
-for.end:                                          ; preds = %for.cond
-  %3 = load i32* @count, align 4
-  %sub = sub nsw i32 %3, 50
-  ret i32 %sub
-}
diff --git a/test/ExecutionEngine/test-interp-vec-loadstore.ll b/test/ExecutionEngine/test-interp-vec-loadstore.ll
index 665a135d6bc9..b66a93505643 100644
--- a/test/ExecutionEngine/test-interp-vec-loadstore.ll
+++ b/test/ExecutionEngine/test-interp-vec-loadstore.ll
@@ -35,13 +35,13 @@ define i32 @main() {
   store i32 4, i32* %pint_3
   
   ; load stored scalars
-  %val_int0 = load i32* %pint_0
-  %val_int1 = load i32* %pint_1
-  %val_int2 = load i32* %pint_2
-  %val_int3 = load i32* %pint_3
+  %val_int0 = load i32, i32* %pint_0
+  %val_int1 = load i32, i32* %pint_1
+  %val_int2 = load i32, i32* %pint_2
+  %val_int3 = load i32, i32* %pint_3
 
   ; load stored vector
-  %val0 = load <4 x i32> *%a, align 16
+  %val0 = load <4 x i32> , <4 x i32> *%a, align 16
 
   ; extract integers from the loaded vector
   %res_i32_0 = extractelement <4 x i32> %val0, i32 0
@@ -72,8 +72,8 @@ define i32 @main() {
   ; if TRUE print message
   br i1 %res_i, label %Print_int, label %Double
 Print_int:
-  %ptr0 = getelementptr [17 x i8]* @msg_int, i32 0, i32 0
-  call i32 (i8*,...)* @printf(i8* %ptr0)
+  %ptr0 = getelementptr [17 x i8], [17 x i8]* @msg_int, i32 0, i32 0
+  call i32 (i8*,...) @printf(i8* %ptr0)
   br label %Double
 Double:
   store <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, <4 x double>* %b, align 16
@@ -84,12 +84,12 @@ Double:
   store double 8.0, double* %pdouble_3
 
   ; load stored vector
-  %val1 = load <4 x double> *%b, align 16
+  %val1 = load <4 x double> , <4 x double> *%b, align 16
   ; load stored scalars
-  %val_double0 = load double* %pdouble_0
-  %val_double1 = load double* %pdouble_1
-  %val_double2 = load double* %pdouble_2
-  %val_double3 = load double* %pdouble_3
+  %val_double0 = load double, double* %pdouble_0
+  %val_double1 = load double, double* %pdouble_1
+  %val_double2 = load double, double* %pdouble_2
+  %val_double3 = load double, double* %pdouble_3
 
   %res_double_0 = extractelement <4 x double> %val1, i32 0
   %res_double_1 = extractelement <4 x double> %val1, i32 1
@@ -116,8 +116,8 @@ Double:
 
   br i1 %res_double, label %Print_double, label %Float
 Print_double:
-  %ptr1 = getelementptr [20 x i8]* @msg_double, i32 0, i32 0
-  call i32 (i8*,...)* @printf(i8* %ptr1)
+  %ptr1 = getelementptr [20 x i8], [20 x i8]* @msg_double, i32 0, i32 0
+  call i32 (i8*,...) @printf(i8* %ptr1)
   br label %Float
 Float:
   store <4 x float> <float 9.0, float 10.0, float 11.0, float 12.0>, <4 x float>* %c, align 16
@@ -128,12 +128,12 @@ Float:
   store float 12.0, float* %pfloat_3
 
   ; load stored vector
-  %val2 = load <4 x float> *%c, align 16
+  %val2 = load <4 x float> , <4 x float> *%c, align 16
   ; load stored scalars
-  %val_float0 = load float* %pfloat_0
-  %val_float1 = load float* %pfloat_1
-  %val_float2 = load float* %pfloat_2
-  %val_float3 = load float* %pfloat_3
+  %val_float0 = load float, float* %pfloat_0
+  %val_float1 = load float, float* %pfloat_1
+  %val_float2 = load float, float* %pfloat_2
+  %val_float3 = load float, float* %pfloat_3
 
   %res_float_0 = extractelement <4 x float> %val2, i32 0
   %res_float_1 = extractelement <4 x float> %val2, i32 1
@@ -160,8 +160,8 @@ Float:
 
   br i1 %res_float, label %Print_float, label %Exit
 Print_float:
-  %ptr2 = getelementptr [19 x i8]* @msg_float, i32 0, i32 0
-  call i32 (i8*,...)* @printf(i8* %ptr2)
+  %ptr2 = getelementptr [19 x i8], [19 x i8]* @msg_float, i32 0, i32 0
+  call i32 (i8*,...) @printf(i8* %ptr2)
   br label %Exit
 Exit:
 
diff --git a/test/ExecutionEngine/test-loadstore.ll b/test/ExecutionEngine/test-loadstore.ll
deleted file mode 100644
index 1797599a9d8d..000000000000
--- a/test/ExecutionEngine/test-loadstore.ll
+++ /dev/null
@@ -1,31 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define void @test(i8* %P, i16* %P.upgrd.1, i32* %P.upgrd.2, i64* %P.upgrd.3) {
-	%V = load i8* %P		; <i8> [#uses=1]
-	store i8 %V, i8* %P
-	%V.upgrd.4 = load i16* %P.upgrd.1		; <i16> [#uses=1]
-	store i16 %V.upgrd.4, i16* %P.upgrd.1
-	%V.upgrd.5 = load i32* %P.upgrd.2		; <i32> [#uses=1]
-	store i32 %V.upgrd.5, i32* %P.upgrd.2
-	%V.upgrd.6 = load i64* %P.upgrd.3		; <i64> [#uses=1]
-	store i64 %V.upgrd.6, i64* %P.upgrd.3
-	ret void
-}
-
-define i32 @varalloca(i32 %Size) {
-        ;; Variable sized alloca
-	%X = alloca i32, i32 %Size		; <i32*> [#uses=2]
-	store i32 %Size, i32* %X
-	%Y = load i32* %X		; <i32> [#uses=1]
-	ret i32 %Y
-}
-
-define i32 @main() {
-	%A = alloca i8		; <i8*> [#uses=1]
-	%B = alloca i16		; <i16*> [#uses=1]
-	%C = alloca i32		; <i32*> [#uses=1]
-	%D = alloca i64		; <i64*> [#uses=1]
-	call void @test( i8* %A, i16* %B, i32* %C, i64* %D )
-	call i32 @varalloca( i32 7 )		; <i32>:1 [#uses=0]
-	ret i32 0
-}
diff --git a/test/ExecutionEngine/test-local.ll b/test/ExecutionEngine/test-local.ll
deleted file mode 100644
index ec5ba165408f..000000000000
--- a/test/ExecutionEngine/test-local.ll
+++ /dev/null
@@ -1,34 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @main() nounwind uwtable {
-entry:
-  %retval = alloca i32, align 4
-  %count = alloca i32, align 4
-  %i = alloca i32, align 4
-  store i32 0, i32* %retval
-  store i32 0, i32* %count, align 4
-  store i32 0, i32* %i, align 4
-  br label %for.cond
-
-for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
-  %cmp = icmp slt i32 %0, 50
-  br i1 %cmp, label %for.body, label %for.end
-
-for.body:                                         ; preds = %for.cond
-  %1 = load i32* %count, align 4
-  %inc = add nsw i32 %1, 1
-  store i32 %inc, i32* %count, align 4
-  br label %for.inc
-
-for.inc:                                          ; preds = %for.body
-  %2 = load i32* %i, align 4
-  %inc1 = add nsw i32 %2, 1
-  store i32 %inc1, i32* %i, align 4
-  br label %for.cond
-
-for.end:                                          ; preds = %for.cond
-  %3 = load i32* %count, align 4
-  %sub = sub nsw i32 %3, 50
-  ret i32 %sub
-}
diff --git a/test/ExecutionEngine/test-logical.ll b/test/ExecutionEngine/test-logical.ll
deleted file mode 100644
index 05b381bb53c2..000000000000
--- a/test/ExecutionEngine/test-logical.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @main() {
-	%A = and i8 4, 8		; <i8> [#uses=2]
-	%B = or i8 %A, 7		; <i8> [#uses=1]
-	%C = xor i8 %B, %A		; <i8> [#uses=0]
-	%A.upgrd.1 = and i16 4, 8		; <i16> [#uses=2]
-	%B.upgrd.2 = or i16 %A.upgrd.1, 7		; <i16> [#uses=1]
-	%C.upgrd.3 = xor i16 %B.upgrd.2, %A.upgrd.1		; <i16> [#uses=0]
-	%A.upgrd.4 = and i32 4, 8		; <i32> [#uses=2]
-	%B.upgrd.5 = or i32 %A.upgrd.4, 7		; <i32> [#uses=1]
-	%C.upgrd.6 = xor i32 %B.upgrd.5, %A.upgrd.4		; <i32> [#uses=0]
-	%A.upgrd.7 = and i64 4, 8		; <i64> [#uses=2]
-	%B.upgrd.8 = or i64 %A.upgrd.7, 7		; <i64> [#uses=1]
-	%C.upgrd.9 = xor i64 %B.upgrd.8, %A.upgrd.7		; <i64> [#uses=0]
-	ret i32 0
-}
-
diff --git a/test/ExecutionEngine/test-loop.ll b/test/ExecutionEngine/test-loop.ll
deleted file mode 100644
index e951a14ed2e9..000000000000
--- a/test/ExecutionEngine/test-loop.ll
+++ /dev/null
@@ -1,14 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @main() {
-; <label>:0
-	br label %Loop
-Loop:		; preds = %Loop, %0
-	%I = phi i32 [ 0, %0 ], [ %i2, %Loop ]		; <i32> [#uses=1]
-	%i2 = add i32 %I, 1		; <i32> [#uses=2]
-	%C = icmp eq i32 %i2, 10		; <i1> [#uses=1]
-	br i1 %C, label %Out, label %Loop
-Out:		; preds = %Loop
-	ret i32 0
-}
-
diff --git a/test/ExecutionEngine/test-phi.ll b/test/ExecutionEngine/test-phi.ll
deleted file mode 100644
index c5bdfd513edc..000000000000
--- a/test/ExecutionEngine/test-phi.ll
+++ /dev/null
@@ -1,34 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-; test phi node
-@Y = global i32 6		; <i32*> [#uses=1]
-
-define void @blah(i32* %X) {
-; <label>:0
-	br label %T
-T:		; preds = %Dead, %0
-	phi i32* [ %X, %0 ], [ @Y, %Dead ]		; <i32*>:1 [#uses=0]
-	ret void
-Dead:		; No predecessors!
-	br label %T
-}
-
-define i32 @test(i1 %C) {
-; <label>:0
-	br i1 %C, label %T, label %T
-T:		; preds = %0, %0
-	%X = phi i32 [ 123, %0 ], [ 123, %0 ]		; <i32> [#uses=1]
-	ret i32 %X
-}
-
-define i32 @main() {
-; <label>:0
-	br label %Test
-Test:		; preds = %Dead, %0
-	%X = phi i32 [ 0, %0 ], [ %Y, %Dead ]		; <i32> [#uses=1]
-	ret i32 %X
-Dead:		; No predecessors!
-	%Y = ashr i32 12, 4		; <i32> [#uses=1]
-	br label %Test
-}
-
diff --git a/test/ExecutionEngine/test-ret.ll b/test/ExecutionEngine/test-ret.ll
deleted file mode 100644
index 025f53e5cb9e..000000000000
--- a/test/ExecutionEngine/test-ret.ll
+++ /dev/null
@@ -1,46 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-; test return instructions
-define void @test1() {
-	ret void
-}
-
-define i8 @test2() {
-	ret i8 1
-}
-
-define i8 @test3() {
-	ret i8 1
-}
-
-define i16 @test4() {
-	ret i16 -1
-}
-
-define i16 @test5() {
-	ret i16 -1
-}
-
-define i32 @main() {
-	ret i32 0
-}
-
-define i32 @test6() {
-	ret i32 4
-}
-
-define i64 @test7() {
-	ret i64 0
-}
-
-define i64 @test8() {
-	ret i64 0
-}
-
-define float @test9() {
-	ret float 1.000000e+00
-}
-
-define double @test10() {
-	ret double 2.000000e+00
-}
diff --git a/test/ExecutionEngine/test-return.ll b/test/ExecutionEngine/test-return.ll
deleted file mode 100644
index d464a4b72d80..000000000000
--- a/test/ExecutionEngine/test-return.ll
+++ /dev/null
@@ -1,8 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @main() nounwind uwtable {
-entry:
-  %retval = alloca i32, align 4
-  store i32 0, i32* %retval
-  ret i32 0
-}
diff --git a/test/ExecutionEngine/test-setcond-fp.ll b/test/ExecutionEngine/test-setcond-fp.ll
deleted file mode 100644
index 68276e617a4a..000000000000
--- a/test/ExecutionEngine/test-setcond-fp.ll
+++ /dev/null
@@ -1,24 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-
-define i32 @main() {
-	%double1 = fadd double 0.000000e+00, 0.000000e+00		; <double> [#uses=6]
-	%double2 = fadd double 0.000000e+00, 0.000000e+00		; <double> [#uses=6]
-	%float1 = fadd float 0.000000e+00, 0.000000e+00		; <float> [#uses=6]
-	%float2 = fadd float 0.000000e+00, 0.000000e+00		; <float> [#uses=6]
-	%test49 = fcmp oeq float %float1, %float2		; <i1> [#uses=0]
-	%test50 = fcmp oge float %float1, %float2		; <i1> [#uses=0]
-	%test51 = fcmp ogt float %float1, %float2		; <i1> [#uses=0]
-	%test52 = fcmp ole float %float1, %float2		; <i1> [#uses=0]
-	%test53 = fcmp olt float %float1, %float2		; <i1> [#uses=0]
-	%test54 = fcmp une float %float1, %float2		; <i1> [#uses=0]
-	%test55 = fcmp oeq double %double1, %double2		; <i1> [#uses=0]
-	%test56 = fcmp oge double %double1, %double2		; <i1> [#uses=0]
-	%test57 = fcmp ogt double %double1, %double2		; <i1> [#uses=0]
-	%test58 = fcmp ole double %double1, %double2		; <i1> [#uses=0]
-	%test59 = fcmp olt double %double1, %double2		; <i1> [#uses=0]
-	%test60 = fcmp une double %double1, %double2		; <i1> [#uses=0]
-	ret i32 0
-}
-
-
diff --git a/test/ExecutionEngine/test-setcond-int.ll b/test/ExecutionEngine/test-setcond-int.ll
deleted file mode 100644
index 48dc02198ec0..000000000000
--- a/test/ExecutionEngine/test-setcond-int.ll
+++ /dev/null
@@ -1,69 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @main() {
-	%int1 = add i32 0, 0		; <i32> [#uses=6]
-	%int2 = add i32 0, 0		; <i32> [#uses=6]
-	%long1 = add i64 0, 0		; <i64> [#uses=6]
-	%long2 = add i64 0, 0		; <i64> [#uses=6]
-	%sbyte1 = add i8 0, 0		; <i8> [#uses=6]
-	%sbyte2 = add i8 0, 0		; <i8> [#uses=6]
-	%short1 = add i16 0, 0		; <i16> [#uses=6]
-	%short2 = add i16 0, 0		; <i16> [#uses=6]
-	%ubyte1 = add i8 0, 0		; <i8> [#uses=6]
-	%ubyte2 = add i8 0, 0		; <i8> [#uses=6]
-	%uint1 = add i32 0, 0		; <i32> [#uses=6]
-	%uint2 = add i32 0, 0		; <i32> [#uses=6]
-	%ulong1 = add i64 0, 0		; <i64> [#uses=6]
-	%ulong2 = add i64 0, 0		; <i64> [#uses=6]
-	%ushort1 = add i16 0, 0		; <i16> [#uses=6]
-	%ushort2 = add i16 0, 0		; <i16> [#uses=6]
-	%test1 = icmp eq i8 %ubyte1, %ubyte2		; <i1> [#uses=0]
-	%test2 = icmp uge i8 %ubyte1, %ubyte2		; <i1> [#uses=0]
-	%test3 = icmp ugt i8 %ubyte1, %ubyte2		; <i1> [#uses=0]
-	%test4 = icmp ule i8 %ubyte1, %ubyte2		; <i1> [#uses=0]
-	%test5 = icmp ult i8 %ubyte1, %ubyte2		; <i1> [#uses=0]
-	%test6 = icmp ne i8 %ubyte1, %ubyte2		; <i1> [#uses=0]
-	%test7 = icmp eq i16 %ushort1, %ushort2		; <i1> [#uses=0]
-	%test8 = icmp uge i16 %ushort1, %ushort2		; <i1> [#uses=0]
-	%test9 = icmp ugt i16 %ushort1, %ushort2		; <i1> [#uses=0]
-	%test10 = icmp ule i16 %ushort1, %ushort2		; <i1> [#uses=0]
-	%test11 = icmp ult i16 %ushort1, %ushort2		; <i1> [#uses=0]
-	%test12 = icmp ne i16 %ushort1, %ushort2		; <i1> [#uses=0]
-	%test13 = icmp eq i32 %uint1, %uint2		; <i1> [#uses=0]
-	%test14 = icmp uge i32 %uint1, %uint2		; <i1> [#uses=0]
-	%test15 = icmp ugt i32 %uint1, %uint2		; <i1> [#uses=0]
-	%test16 = icmp ule i32 %uint1, %uint2		; <i1> [#uses=0]
-	%test17 = icmp ult i32 %uint1, %uint2		; <i1> [#uses=0]
-	%test18 = icmp ne i32 %uint1, %uint2		; <i1> [#uses=0]
-	%test19 = icmp eq i64 %ulong1, %ulong2		; <i1> [#uses=0]
-	%test20 = icmp uge i64 %ulong1, %ulong2		; <i1> [#uses=0]
-	%test21 = icmp ugt i64 %ulong1, %ulong2		; <i1> [#uses=0]
-	%test22 = icmp ule i64 %ulong1, %ulong2		; <i1> [#uses=0]
-	%test23 = icmp ult i64 %ulong1, %ulong2		; <i1> [#uses=0]
-	%test24 = icmp ne i64 %ulong1, %ulong2		; <i1> [#uses=0]
-	%test25 = icmp eq i8 %sbyte1, %sbyte2		; <i1> [#uses=0]
-	%test26 = icmp sge i8 %sbyte1, %sbyte2		; <i1> [#uses=0]
-	%test27 = icmp sgt i8 %sbyte1, %sbyte2		; <i1> [#uses=0]
-	%test28 = icmp sle i8 %sbyte1, %sbyte2		; <i1> [#uses=0]
-	%test29 = icmp slt i8 %sbyte1, %sbyte2		; <i1> [#uses=0]
-	%test30 = icmp ne i8 %sbyte1, %sbyte2		; <i1> [#uses=0]
-	%test31 = icmp eq i16 %short1, %short2		; <i1> [#uses=0]
-	%test32 = icmp sge i16 %short1, %short2		; <i1> [#uses=0]
-	%test33 = icmp sgt i16 %short1, %short2		; <i1> [#uses=0]
-	%test34 = icmp sle i16 %short1, %short2		; <i1> [#uses=0]
-	%test35 = icmp slt i16 %short1, %short2		; <i1> [#uses=0]
-	%test36 = icmp ne i16 %short1, %short2		; <i1> [#uses=0]
-	%test37 = icmp eq i32 %int1, %int2		; <i1> [#uses=0]
-	%test38 = icmp sge i32 %int1, %int2		; <i1> [#uses=0]
-	%test39 = icmp sgt i32 %int1, %int2		; <i1> [#uses=0]
-	%test40 = icmp sle i32 %int1, %int2		; <i1> [#uses=0]
-	%test41 = icmp slt i32 %int1, %int2		; <i1> [#uses=0]
-	%test42 = icmp ne i32 %int1, %int2		; <i1> [#uses=0]
-	%test43 = icmp eq i64 %long1, %long2		; <i1> [#uses=0]
-	%test44 = icmp sge i64 %long1, %long2		; <i1> [#uses=0]
-	%test45 = icmp sgt i64 %long1, %long2		; <i1> [#uses=0]
-	%test46 = icmp sle i64 %long1, %long2		; <i1> [#uses=0]
-	%test47 = icmp slt i64 %long1, %long2		; <i1> [#uses=0]
-	%test48 = icmp ne i64 %long1, %long2		; <i1> [#uses=0]
-	ret i32 0
-}
diff --git a/test/ExecutionEngine/test-shift.ll b/test/ExecutionEngine/test-shift.ll
deleted file mode 100644
index 590e2620689f..000000000000
--- a/test/ExecutionEngine/test-shift.ll
+++ /dev/null
@@ -1,32 +0,0 @@
-; RUN: %lli %s > /dev/null
-
-define i32 @main() {
-	%shamt = add i8 0, 1		; <i8> [#uses=8]
-	%shift.upgrd.1 = zext i8 %shamt to i32		; <i32> [#uses=1]
-	%t1.s = shl i32 1, %shift.upgrd.1		; <i32> [#uses=0]
-	%t2.s = shl i32 1, 4		; <i32> [#uses=0]
-	%shift.upgrd.2 = zext i8 %shamt to i32		; <i32> [#uses=1]
-	%t1 = shl i32 1, %shift.upgrd.2		; <i32> [#uses=0]
-	%t2 = shl i32 1, 5		; <i32> [#uses=0]
-	%t2.s.upgrd.3 = shl i64 1, 4		; <i64> [#uses=0]
-	%t2.upgrd.4 = shl i64 1, 5		; <i64> [#uses=0]
-	%shift.upgrd.5 = zext i8 %shamt to i32		; <i32> [#uses=1]
-	%tr1.s = ashr i32 1, %shift.upgrd.5		; <i32> [#uses=0]
-	%tr2.s = ashr i32 1, 4		; <i32> [#uses=0]
-	%shift.upgrd.6 = zext i8 %shamt to i32		; <i32> [#uses=1]
-	%tr1 = lshr i32 1, %shift.upgrd.6		; <i32> [#uses=0]
-	%tr2 = lshr i32 1, 5		; <i32> [#uses=0]
-	%tr1.l = ashr i64 1, 4		; <i64> [#uses=0]
-	%shift.upgrd.7 = zext i8 %shamt to i64		; <i64> [#uses=1]
-	%tr2.l = ashr i64 1, %shift.upgrd.7		; <i64> [#uses=0]
-	%tr3.l = shl i64 1, 4		; <i64> [#uses=0]
-	%shift.upgrd.8 = zext i8 %shamt to i64		; <i64> [#uses=1]
-	%tr4.l = shl i64 1, %shift.upgrd.8		; <i64> [#uses=0]
-	%tr1.u = lshr i64 1, 5		; <i64> [#uses=0]
-	%shift.upgrd.9 = zext i8 %shamt to i64		; <i64> [#uses=1]
-	%tr2.u = lshr i64 1, %shift.upgrd.9		; <i64> [#uses=0]
-	%tr3.u = shl i64 1, 5		; <i64> [#uses=0]
-	%shift.upgrd.10 = zext i8 %shamt to i64		; <i64> [#uses=1]
-	%tr4.u = shl i64 1, %shift.upgrd.10		; <i64> [#uses=0]
-	ret i32 0
-}
diff --git a/test/Feature/alias2.ll b/test/Feature/alias2.ll
index 73c874f2b9ee..e461854e7514 100644
--- a/test/Feature/alias2.ll
+++ b/test/Feature/alias2.ll
@@ -13,7 +13,7 @@
 ; CHECK: @a1 = alias bitcast (i32* @v1 to i16*)
 
 @a2 = alias bitcast([1 x i32]* @v2 to i32*)
-; CHECK: @a2 = alias getelementptr inbounds ([1 x i32]* @v2, i32 0, i32 0)
+; CHECK: @a2 = alias getelementptr inbounds ([1 x i32], [1 x i32]* @v2, i32 0, i32 0)
 
 @a3 = alias addrspacecast (i32* @v1 to i32 addrspace(2)*)
 ; CHECK: @a3 = alias addrspacecast (i32* @v1 to i32 addrspace(2)*)
@@ -24,5 +24,5 @@
 @a5 = thread_local(localdynamic) alias i32* @v1
 ; CHECK: @a5 = thread_local(localdynamic) alias i32* @v1
 
-@a6 = alias getelementptr ([2 x i16]* @v3, i32 1, i32 1)
-; CHECK: @a6 = alias getelementptr ([2 x i16]* @v3, i32 1, i32 1)
+@a6 = alias getelementptr ([2 x i16], [2 x i16]* @v3, i32 1, i32 1)
+; CHECK: @a6 = alias getelementptr ([2 x i16], [2 x i16]* @v3, i32 1, i32 1)
diff --git a/test/Feature/aliases.ll b/test/Feature/aliases.ll
index c11fc4764254..b3b9ceba527b 100644
--- a/test/Feature/aliases.ll
+++ b/test/Feature/aliases.ll
@@ -30,12 +30,12 @@ define i32 @foo_f() {
 
 define i32 @test() {
 entry:
-   %tmp = load i32* @foo1
-   %tmp1 = load i32* @foo2
-   %tmp0 = load i32* @bar_i
+   %tmp = load i32, i32* @foo1
+   %tmp1 = load i32, i32* @foo2
+   %tmp0 = load i32, i32* @bar_i
    %tmp2 = call i32 @foo_f()
    %tmp3 = add i32 %tmp, %tmp2
-   %tmp4 = call %FunTy* @bar_f()
+   %tmp4 = call %FunTy @bar_f()
    %tmp5 = add i32 %tmp3, %tmp4
    %tmp6 = add i32 %tmp1, %tmp5
    %tmp7 = add i32 %tmp6, %tmp0
diff --git a/test/Feature/attributes.ll b/test/Feature/attributes.ll
index 7707d82be5ce..cae3cbfe79ba 100644
--- a/test/Feature/attributes.ll
+++ b/test/Feature/attributes.ll
@@ -6,7 +6,7 @@
 
 define void @foo() #0 {
 entry:
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str, i32 0, i32 0))
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str, i32 0, i32 0))
   ret void
 }
 
diff --git a/test/Feature/const_pv.ll b/test/Feature/const_pv.ll
index 272bf43a0687..15c1142b37a2 100644
--- a/test/Feature/const_pv.ll
+++ b/test/Feature/const_pv.ll
@@ -2,7 +2,7 @@
 @G = constant <3 x i64> ptrtoint (<3 x i8*> <i8* null, i8* null, i8* null> to <3 x i64>)
 
 @G1 = global i8 zeroinitializer
-@g = constant <2 x i8*> getelementptr (<2 x i8*> <i8* @G1, i8* @G1>, <2 x i32> <i32 0, i32 0>)
+@g = constant <2 x i8*> getelementptr (i8, <2 x i8*> <i8* @G1, i8* @G1>, <2 x i32> <i32 0, i32 0>)
 
 @t = constant <2 x i1> icmp eq (<2 x i32> ptrtoint (<2 x i8*> zeroinitializer to <2 x i32>), <2 x i32> zeroinitializer )
 
diff --git a/test/Feature/constexpr.ll b/test/Feature/constexpr.ll
index 13e6f365aabf..ee958ce1e38b 100644
--- a/test/Feature/constexpr.ll
+++ b/test/Feature/constexpr.ll
@@ -32,17 +32,17 @@ global float 0.0
 ;;---------------------------------------------------
 
 @array  = constant [2 x i32] [ i32 12, i32 52 ]
-@arrayPtr = global i32* getelementptr ([2 x i32]* @array, i64 0, i64 0)    ;; i32* &@array[0][0]
-@arrayPtr5 = global i32** getelementptr (i32** @arrayPtr, i64 5)    ;; i32* &@arrayPtr[5]
+@arrayPtr = global i32* getelementptr ([2 x i32], [2 x i32]* @array, i64 0, i64 0)    ;; i32* &@array[0][0]
+@arrayPtr5 = global i32** getelementptr (i32*, i32** @arrayPtr, i64 5)    ;; i32* &@arrayPtr[5]
 
 @somestr = constant [11x i8] c"hello world"
-@char5  = global i8* getelementptr([11x i8]* @somestr, i64 0, i64 5)
+@char5  = global i8* getelementptr([11x i8], [11x i8]* @somestr, i64 0, i64 5)
 
 ;; cast of getelementptr
-@char8a = global i32* bitcast (i8* getelementptr([11x i8]* @somestr, i64 0, i64 8) to i32*)
+@char8a = global i32* bitcast (i8* getelementptr([11x i8], [11x i8]* @somestr, i64 0, i64 8) to i32*)
 
 ;; getelementptr containing casts
-@char8b = global i8* getelementptr([11x i8]* @somestr, i64 sext (i8 0 to i64), i64 sext (i8 8 to i64))
+@char8b = global i8* getelementptr([11x i8], [11x i8]* @somestr, i64 sext (i8 0 to i64), i64 sext (i8 8 to i64))
 
 ;;-------------------------------------------------------
 ;; TODO: Test constant getelementpr expressions for structures
@@ -61,17 +61,17 @@ global float 0.0
 @S3  = global %SAType* @S3c		    ;; Ref. to constant S3
 
 					    ;; Pointer to float (**@S1).1.0
-@S1fld1a = global float* getelementptr (%SType* @S2c, i64 0, i32 1, i32 0)
+@S1fld1a = global float* getelementptr (%SType, %SType* @S2c, i64 0, i32 1, i32 0)
 					    ;; Another ptr to the same!
-@S1fld1b = global float* getelementptr (%SType* @S2c, i64 0, i32 1, i32 0)
+@S1fld1b = global float* getelementptr (%SType, %SType* @S2c, i64 0, i32 1, i32 0)
 
 @S1fld1bptr = global float** @S1fld1b	    ;; Ref. to previous pointer
 
 					    ;; Pointer to i8 (**@S2).1.1.0
-@S2fld3 = global i8* getelementptr (%SType* @S2c, i64 0, i32 1, i32 1, i32 0) 
+@S2fld3 = global i8* getelementptr (%SType, %SType* @S2c, i64 0, i32 1, i32 1, i32 0) 
 
 					    ;; Pointer to float (**@S2).1.0[0]
-;@S3fld3 = global float* getelementptr (%SAType** @S3, i64 0, i64 0, i32 1, i32 0, i64 0) 
+;@S3fld3 = global float* getelementptr (%SAType*, %SAType** @S3, i64 0, i64 0, i32 1, i32 0, i64 0) 
 
 ;;---------------------------------------------------------
 ;; TODO: Test constant expressions for unary and binary operators
diff --git a/test/Feature/globalvars.ll b/test/Feature/globalvars.ll
index 84b4bdfd3750..710a87998a86 100644
--- a/test/Feature/globalvars.ll
+++ b/test/Feature/globalvars.ll
@@ -11,7 +11,7 @@ external global i32             ; <i32*>:0 [#uses=0]
 
 define i32 @foo(i32 %blah) {
         store i32 5, i32* @MyVar
-        %idx = getelementptr { i32*, i32 }* @MyIntList, i64 0, i32 1             ; <i32*> [#uses=1]
+        %idx = getelementptr { i32*, i32 }, { i32*, i32 }* @MyIntList, i64 0, i32 1             ; <i32*> [#uses=1]
         store i32 12, i32* %idx
         ret i32 %blah
 }
diff --git a/test/Feature/md_on_instruction.ll b/test/Feature/md_on_instruction.ll
index 511cc8528476..e4f9f671170d 100644
--- a/test/Feature/md_on_instruction.ll
+++ b/test/Feature/md_on_instruction.ll
@@ -1,27 +1,28 @@
-; RUN: llvm-as < %s | llvm-dis | grep " !dbg " | count 4
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+
 define i32 @foo() nounwind ssp {
 entry:
-  %retval = alloca i32                            ; <i32*> [#uses=2]
-  call void @llvm.dbg.func.start(metadata !0)
-  store i32 42, i32* %retval, !dbg !3
-  br label %0, !dbg !3
+  ; CHECK: %retval = alloca i32
+  ; CHECK: store i32 42, i32* %retval, !md !0
+  ; CHECK: br label %0, !md !1
+  %retval = alloca i32
+  store i32 42, i32* %retval, !md !0
+  br label %0, !md !1
 
-; <label>:0                                       ; preds = %entry
-  call void @llvm.dbg.region.end(metadata !0)
-  %1 = load i32* %retval, !dbg !3                  ; <i32> [#uses=1]
-  ret i32 %1, !dbg !3
+; <label:0>
+  ; CHECK: %1 = load i32, i32* %retval, !md !2
+  ; CHECK: ret i32 %1, !md !3
+  %1 = load i32, i32* %retval, !md !2
+  ret i32 %1, !md !3
 }
 
-declare void @llvm.dbg.func.start(metadata) nounwind readnone
-
-declare void @llvm.dbg.region.end(metadata) nounwind readnone
-
-!llvm.module.flags = !{!6}
-
-!0 = !{!"0x2e\00foo\00foo\00foo\001\000\001\000\006\000\000\000", i32 0, !1, !2, null, null, null, null} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x11\0012\00clang 1.0\001\00\000\00\000", !4, !5, !5, !4, null, null} ; [ DW_TAG_compile_unit ]
-!2 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !1} ; [ DW_TAG_base_type ]
-!3 = !MDLocation(line: 1, column: 13, scope: !1, inlinedAt: !1)
-!4 = !{!"foo.c", !"/tmp"}
-!5 = !{i32 0}
-!6 = !{i32 1, !"Debug Info Version", i32 2}
+; CHECK: !0 = !{}
+; CHECK: !1 = distinct !{}
+; CHECK: !2 = !{!0}
+; CHECK: !3 = !{!4}
+; CHECK: !4 = !{!0, !2}
+!0 = !{}
+!1 = distinct !{}
+!2 = !{!0}
+!3 = !{!4}
+!4 = !{!0, !2}
diff --git a/test/Feature/memorymarkers.ll b/test/Feature/memorymarkers.ll
index 06b8376678fa..47dd1ee5cf6f 100644
--- a/test/Feature/memorymarkers.ll
+++ b/test/Feature/memorymarkers.ll
@@ -18,15 +18,15 @@ entry:
   ;; preceded by an alloca, but shown for completeness).
   call void @llvm.lifetime.start(i64 8, i8* %y)
 
-  %0 = getelementptr %"struct.std::pair<int,int>"* %x, i32 0, i32 0
+  %0 = getelementptr %"struct.std::pair<int,int>", %"struct.std::pair<int,int>"* %x, i32 0, i32 0
   store i32 4, i32* %0, align 8
-  %1 = getelementptr %"struct.std::pair<int,int>"* %x, i32 0, i32 1
+  %1 = getelementptr %"struct.std::pair<int,int>", %"struct.std::pair<int,int>"* %x, i32 0, i32 1
   store i32 5, i32* %1, align 4
 
   ;; Constructor has finished here.
   %inv = call {}* @llvm.invariant.start(i64 8, i8* %y)
   call void @_Z3barRKi(i32* %0) nounwind
-  %2 = load i32* %0, align 8
+  %2 = load i32, i32* %0, align 8
 
   ;; Destructor is run here.
   call void @llvm.invariant.end({}* %inv, i64 8, i8* %y)
diff --git a/test/Feature/optnone-llc.ll b/test/Feature/optnone-llc.ll
index f19fa88f9b26..b848b19d528b 100644
--- a/test/Feature/optnone-llc.ll
+++ b/test/Feature/optnone-llc.ll
@@ -17,7 +17,7 @@ entry:
   br label %while.cond
 
 while.cond:                                       ; preds = %while.body, %entry
-  %0 = load i32* %x.addr, align 4
+  %0 = load i32, i32* %x.addr, align 4
   %dec = add nsw i32 %0, -1
   store i32 %dec, i32* %x.addr, align 4
   %tobool = icmp ne i32 %0, 0
diff --git a/test/Feature/optnone-opt.ll b/test/Feature/optnone-opt.ll
index f83e68ccfef8..a17f97785f04 100644
--- a/test/Feature/optnone-opt.ll
+++ b/test/Feature/optnone-opt.ll
@@ -18,7 +18,7 @@ entry:
   br label %while.cond
 
 while.cond:                                       ; preds = %while.body, %entry
-  %0 = load i32* %x.addr, align 4
+  %0 = load i32, i32* %x.addr, align 4
   %dec = add nsw i32 %0, -1
   store i32 %dec, i32* %x.addr, align 4
   %tobool = icmp ne i32 %0, 0
diff --git a/test/Feature/packed.ll b/test/Feature/packed.ll
index b86a22792b1d..fa29535271a4 100644
--- a/test/Feature/packed.ll
+++ b/test/Feature/packed.ll
@@ -8,8 +8,8 @@
 define void @main() {
         store <4 x float> < float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00 >, <4 x float>* @foo1
         store <2 x i32> < i32 4, i32 4 >, <2 x i32>* @foo2
-        %l1 = load <4 x float>* @foo1           ; <<4 x float>> [#uses=0]
-        %l2 = load <2 x i32>* @foo2             ; <<2 x i32>> [#uses=0]
+        %l1 = load <4 x float>, <4 x float>* @foo1           ; <<4 x float>> [#uses=0]
+        %l2 = load <2 x i32>, <2 x i32>* @foo2             ; <<2 x i32>> [#uses=0]
         ret void
 }
 
diff --git a/test/Feature/packed_struct.ll b/test/Feature/packed_struct.ll
index 07666491b130..172cd3456c8b 100644
--- a/test/Feature/packed_struct.ll
+++ b/test/Feature/packed_struct.ll
@@ -16,9 +16,9 @@
 
 define i32 @main() 
 {
-        %tmp = load i32*  getelementptr (%struct.anon* @foos, i32 0, i32 1)            ; <i32> [#uses=1]
-        %tmp3 = load i32* getelementptr (%struct.anon* @foos, i32 0, i32 2)            ; <i32> [#uses=1]
-        %tmp6 = load i32* getelementptr (%struct.anon* @foos, i32 0, i32 3)            ; <i32> [#uses=1]
+        %tmp = load i32, i32*  getelementptr (%struct.anon, %struct.anon* @foos, i32 0, i32 1)            ; <i32> [#uses=1]
+        %tmp3 = load i32, i32* getelementptr (%struct.anon, %struct.anon* @foos, i32 0, i32 2)            ; <i32> [#uses=1]
+        %tmp6 = load i32, i32* getelementptr (%struct.anon, %struct.anon* @foos, i32 0, i32 3)            ; <i32> [#uses=1]
         %tmp4 = add i32 %tmp3, %tmp             ; <i32> [#uses=1]
         %tmp7 = add i32 %tmp4, %tmp6            ; <i32> [#uses=1]
         ret i32 %tmp7
@@ -26,8 +26,8 @@ define i32 @main()
 
 define i32 @bar() {
 entry:
-        %tmp = load i32* getelementptr([2 x <{ i32, i8 }>]* @bara, i32 0, i32 0, i32 0 )            ; <i32> [#uses=1]
-        %tmp4 = load i32* getelementptr ([2 x <{ i32, i8 }>]* @bara, i32 0, i32 1, i32 0)           ; <i32> [#uses=1]
+        %tmp = load i32, i32* getelementptr([2 x <{ i32, i8 }>], [2 x <{ i32, i8 }>]* @bara, i32 0, i32 0, i32 0 )            ; <i32> [#uses=1]
+        %tmp4 = load i32, i32* getelementptr ([2 x <{ i32, i8 }>], [2 x <{ i32, i8 }>]* @bara, i32 0, i32 1, i32 0)           ; <i32> [#uses=1]
         %tmp5 = add i32 %tmp4, %tmp             ; <i32> [#uses=1]
         ret i32 %tmp5
 }
diff --git a/test/Feature/paramattrs.ll b/test/Feature/paramattrs.ll
index 9860f5a6a5bf..d24791ee6732 100644
--- a/test/Feature/paramattrs.ll
+++ b/test/Feature/paramattrs.ll
@@ -14,7 +14,7 @@ declare void @exit(i32) noreturn nounwind
 
 define i32 @main(i32 inreg %argc, i8 ** inreg %argv) nounwind {
     %val = trunc i32 %argc to i16
-    %res1 = call signext i16 (i16 ) *@test(i16 signext %val) 
+    %res1 = call signext i16 (i16 )@test(i16 signext %val) 
     %two = add i16 %res1, %res1
     %res2 = call zeroext i8 @test2(i16 zeroext %two )  
     %retVal = sext i16 %two to i32
diff --git a/test/Feature/ppcld.ll b/test/Feature/ppcld.ll
index 393a491847c7..6f566190b9b3 100644
--- a/test/Feature/ppcld.ll
+++ b/test/Feature/ppcld.ll
@@ -12,15 +12,15 @@ define i32 @foo() {
 entry:
 	%retval = alloca i32, align 4		; <i32*> [#uses=1]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
-	%tmp = load float* @f		; <float> [#uses=1]
+	%tmp = load float, float* @f		; <float> [#uses=1]
 	%tmp1 = fpext float %tmp to double		; <double> [#uses=1]
-	%tmp2 = load double* @d		; <double> [#uses=1]
+	%tmp2 = load double, double* @d		; <double> [#uses=1]
 	%tmp3 = fmul double %tmp1, %tmp2		; <double> [#uses=1]
 	%tmp4 = fpext double %tmp3 to ppc_fp128		; <ppc_fp128> [#uses=1]
 	store ppc_fp128 %tmp4, ppc_fp128* @ld
 	br label %return
 
 return:		; preds = %entry
-	%retval4 = load i32* %retval		; <i32> [#uses=1]
+	%retval4 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval4
 }
diff --git a/test/Feature/recursivetype.ll b/test/Feature/recursivetype.ll
index 43db5f052c40..b04069648bc5 100644
--- a/test/Feature/recursivetype.ll
+++ b/test/Feature/recursivetype.ll
@@ -43,7 +43,7 @@ declare i8* @malloc(i32)
 
 define void @InsertIntoListTail(%list** %L, i32 %Data) {
 bb1:
-        %reg116 = load %list** %L               ; <%list*> [#uses=1]
+        %reg116 = load %list*, %list** %L               ; <%list*> [#uses=1]
         %cast1004 = inttoptr i64 0 to %list*            ; <%list*> [#uses=1]
         %cond1000 = icmp eq %list* %reg116, %cast1004           ; <i1> [#uses=1]
         br i1 %cond1000, label %bb3, label %bb2
@@ -51,8 +51,8 @@ bb1:
 bb2:            ; preds = %bb2, %bb1
         %reg117 = phi %list** [ %reg118, %bb2 ], [ %L, %bb1 ]           ; <%list**> [#uses=1]
         %cast1010 = bitcast %list** %reg117 to %list***         ; <%list***> [#uses=1]
-        %reg118 = load %list*** %cast1010               ; <%list**> [#uses=3]
-        %reg109 = load %list** %reg118          ; <%list*> [#uses=1]
+        %reg118 = load %list**, %list*** %cast1010               ; <%list**> [#uses=3]
+        %reg109 = load %list*, %list** %reg118          ; <%list*> [#uses=1]
         %cast1005 = inttoptr i64 0 to %list*            ; <%list*> [#uses=1]
         %cond1001 = icmp ne %list* %reg109, %cast1005           ; <i1> [#uses=1]
         br i1 %cond1001, label %bb2, label %bb3
@@ -87,8 +87,8 @@ bb3:            ; preds = %bb2
         ret %list* null
 
 bb4:            ; preds = %bb2
-        %idx = getelementptr %list* %reg115, i64 0, i32 1               ; <i32*> [#uses=1]
-        %reg111 = load i32* %idx                ; <i32> [#uses=1]
+        %idx = getelementptr %list, %list* %reg115, i64 0, i32 1               ; <i32*> [#uses=1]
+        %reg111 = load i32, i32* %idx                ; <i32> [#uses=1]
         %cond1013 = icmp ne i32 %reg111, %Data          ; <i1> [#uses=1]
         br i1 %cond1013, label %bb6, label %bb5
 
@@ -96,8 +96,8 @@ bb5:            ; preds = %bb4
         ret %list* %reg115
 
 bb6:            ; preds = %bb4
-        %idx2 = getelementptr %list* %reg115, i64 0, i32 0              ; <%list**> [#uses=1]
-        %reg116 = load %list** %idx2            ; <%list*> [#uses=1]
+        %idx2 = getelementptr %list, %list* %reg115, i64 0, i32 0              ; <%list**> [#uses=1]
+        %reg116 = load %list*, %list** %idx2            ; <%list*> [#uses=1]
         br label %bb2
 }
 
diff --git a/test/Feature/seh-nounwind.ll b/test/Feature/seh-nounwind.ll
new file mode 100644
index 000000000000..203471649df5
--- /dev/null
+++ b/test/Feature/seh-nounwind.ll
@@ -0,0 +1,32 @@
+; RUN: opt -S -O2 < %s | FileCheck %s
+
+; Feature test that verifies that all optimizations leave asynch personality
+; invokes of nounwind functions alone.
+; The @div function in this test can fault, even though it can't
+; throw a synchronous exception.
+
+define i32 @div(i32 %n, i32 %d) nounwind noinline {
+entry:
+  %div = sdiv i32 %n, %d
+  ret i32 %div
+}
+
+define i32 @main() nounwind {
+entry:
+  %call = invoke i32 @div(i32 10, i32 0)
+          to label %__try.cont unwind label %lpad
+
+lpad:
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+          catch i8* null
+  br label %__try.cont
+
+__try.cont:
+  %retval.0 = phi i32 [ %call, %entry ], [ 0, %lpad ]
+  ret i32 %retval.0
+}
+
+; CHECK-LABEL: define i32 @main()
+; CHECK: invoke i32 @div(i32 10, i32 0)
+
+declare i32 @__C_specific_handler(...)
diff --git a/test/Feature/sparcld.ll b/test/Feature/sparcld.ll
index 095f6f6c7c75..f5a24f51fd3b 100644
--- a/test/Feature/sparcld.ll
+++ b/test/Feature/sparcld.ll
@@ -10,15 +10,15 @@ define i32 @foo() {
 entry:
 	%retval = alloca i32, align 4		; <i32*> [#uses=1]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
-	%tmp = load float* @f		; <float> [#uses=1]
+	%tmp = load float, float* @f		; <float> [#uses=1]
 	%tmp1 = fpext float %tmp to double		; <double> [#uses=1]
-	%tmp2 = load double* @d		; <double> [#uses=1]
+	%tmp2 = load double, double* @d		; <double> [#uses=1]
 	%tmp3 = fmul double %tmp1, %tmp2		; <double> [#uses=1]
 	%tmp4 = fpext double %tmp3 to fp128		; <fp128> [#uses=1]
 	store fp128 %tmp4, fp128* @ld
 	br label %return
 
 return:		; preds = %entry
-	%retval4 = load i32* %retval		; <i32> [#uses=1]
+	%retval4 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval4
 }
diff --git a/test/Feature/testalloca.ll b/test/Feature/testalloca.ll
index 230b5a90dc4c..0405320e41ac 100644
--- a/test/Feature/testalloca.ll
+++ b/test/Feature/testalloca.ll
@@ -9,13 +9,13 @@ define i32 @testfunction(i32 %i0, i32 %j0) {
         alloca i8, i32 5                ; <i8*>:1 [#uses=0]
         %ptr = alloca i32               ; <i32*> [#uses=2]
         store i32 3, i32* %ptr
-        %val = load i32* %ptr           ; <i32> [#uses=0]
+        %val = load i32, i32* %ptr           ; <i32> [#uses=0]
         %sptr = alloca %struct          ; <%struct*> [#uses=2]
-        %nsptr = getelementptr %struct* %sptr, i64 0, i32 1             ; <%inners*> [#uses=1]
-        %ubsptr = getelementptr %inners* %nsptr, i64 0, i32 1           ; <{ i8 }*> [#uses=1]
-        %idx = getelementptr { i8 }* %ubsptr, i64 0, i32 0              ; <i8*> [#uses=1]
+        %nsptr = getelementptr %struct, %struct* %sptr, i64 0, i32 1             ; <%inners*> [#uses=1]
+        %ubsptr = getelementptr %inners, %inners* %nsptr, i64 0, i32 1           ; <{ i8 }*> [#uses=1]
+        %idx = getelementptr { i8 }, { i8 }* %ubsptr, i64 0, i32 0              ; <i8*> [#uses=1]
         store i8 4, i8* %idx
-        %fptr = getelementptr %struct* %sptr, i64 0, i32 1, i32 0               ; <float*> [#uses=1]
+        %fptr = getelementptr %struct, %struct* %sptr, i64 0, i32 1, i32 0               ; <float*> [#uses=1]
         store float 4.000000e+00, float* %fptr
         ret i32 3
 }
diff --git a/test/Feature/testconstants.ll b/test/Feature/testconstants.ll
index 6810f3de13d4..81d67f932987 100644
--- a/test/Feature/testconstants.ll
+++ b/test/Feature/testconstants.ll
@@ -11,7 +11,7 @@ define [2 x i32]* @testfunction(i32 %i0, i32 %j0) {
 }
 
 define i8* @otherfunc(i32, double) {
-        %somestr = getelementptr [11 x i8]* @somestr, i64 0, i64 0              ; <i8*> [#uses=1]
+        %somestr = getelementptr [11 x i8], [11 x i8]* @somestr, i64 0, i64 0              ; <i8*> [#uses=1]
         ret i8* %somestr
 }
 
diff --git a/test/Feature/testvarargs.ll b/test/Feature/testvarargs.ll
index a73b7ecd7d60..ccc81f6d899d 100644
--- a/test/Feature/testvarargs.ll
+++ b/test/Feature/testvarargs.ll
@@ -6,7 +6,7 @@
 declare i32 @printf(i8*, ...)   ;; Prototype for: int __builtin_printf(const char*, ...)
 
 define i32 @testvarar() {
-        call i32 (i8*, ...)* @printf( i8* null, i32 12, i8 42 )         ; <i32>:1 [#uses=1]
+        call i32 (i8*, ...) @printf( i8* null, i32 12, i8 42 )         ; <i32>:1 [#uses=1]
         ret i32 %1
 }
 
diff --git a/test/Feature/varargs_new.ll b/test/Feature/varargs_new.ll
index a46f270d86de..ca5599d369a1 100644
--- a/test/Feature/varargs_new.ll
+++ b/test/Feature/varargs_new.ll
@@ -24,7 +24,7 @@ define i32 @test(i32 %X, ...) {
         %tmp = va_arg i8** %ap, i32             ; <i32> [#uses=1]
 
         ; Demonstrate usage of llvm.va_copy and llvm_va_end
-        %apv = load i8** %ap            ; <i8*> [#uses=1]
+        %apv = load i8*, i8** %ap            ; <i8*> [#uses=1]
         %va0.upgrd.2 = bitcast i8** %aq to i8*          ; <i8*> [#uses=1]
         %va1.upgrd.3 = bitcast i8* %apv to i8*          ; <i8*> [#uses=1]
         call void @llvm.va_copy( i8* %va0.upgrd.2, i8* %va1.upgrd.3 )
diff --git a/test/Feature/weak_constant.ll b/test/Feature/weak_constant.ll
index d331bf59e833..4ac2e7e7d689 100644
--- a/test/Feature/weak_constant.ll
+++ b/test/Feature/weak_constant.ll
@@ -10,20 +10,20 @@
 @c = weak constant %0 { i32 7, i32 9 }		; <%0*> [#uses=1]
 
 define i32 @la() {
-	%v = load i32* @a		; <i32> [#uses=1]
+	%v = load i32, i32* @a		; <i32> [#uses=1]
 	ret i32 %v
 }
 
 define i32 @lb() {
-	%v = load i32* @b		; <i32> [#uses=1]
+	%v = load i32, i32* @b		; <i32> [#uses=1]
 	ret i32 %v
 }
 
 define i32 @lc() {
-	%g = getelementptr %0* @c, i32 0, i32 0		; <i32*> [#uses=1]
-	%u = load i32* %g		; <i32> [#uses=1]
-	%h = getelementptr %0* @c, i32 0, i32 1		; <i32*> [#uses=1]
-	%v = load i32* %h		; <i32> [#uses=1]
+	%g = getelementptr %0, %0* @c, i32 0, i32 0		; <i32*> [#uses=1]
+	%u = load i32, i32* %g		; <i32> [#uses=1]
+	%h = getelementptr %0, %0* @c, i32 0, i32 1		; <i32*> [#uses=1]
+	%v = load i32, i32* %h		; <i32> [#uses=1]
 	%r = add i32 %u, %v
 	ret i32 %r
 }
diff --git a/test/Feature/x86ld.ll b/test/Feature/x86ld.ll
index 32005aee305d..7f91abd6d7ff 100644
--- a/test/Feature/x86ld.ll
+++ b/test/Feature/x86ld.ll
@@ -12,15 +12,15 @@ define i32 @foo() {
 entry:
 	%retval = alloca i32, align 4		; <i32*> [#uses=1]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
-	%tmp = load float* @f		; <float> [#uses=1]
+	%tmp = load float, float* @f		; <float> [#uses=1]
 	%tmp1 = fpext float %tmp to double		; <double> [#uses=1]
-	%tmp2 = load double* @d		; <double> [#uses=1]
+	%tmp2 = load double, double* @d		; <double> [#uses=1]
 	%tmp3 = fmul double %tmp1, %tmp2		; <double> [#uses=1]
 	%tmp4 = fpext double %tmp3 to x86_fp80		; <x86_fp80> [#uses=1]
 	store x86_fp80 %tmp4, x86_fp80* @ld
 	br label %return
 
 return:		; preds = %entry
-	%retval4 = load i32* %retval		; <i32> [#uses=1]
+	%retval4 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval4
 }
diff --git a/test/FileCheck/same.txt b/test/FileCheck/same.txt
new file mode 100644
index 000000000000..7160936c466d
--- /dev/null
+++ b/test/FileCheck/same.txt
@@ -0,0 +1,23 @@
+foo bat bar
+baz
+
+RUN: FileCheck --input-file=%s --check-prefix=PASS1 %s
+PASS1: foo
+PASS1-SAME: bat
+PASS1-SAME: bar
+PASS1-NEXT: baz
+
+RUN: FileCheck --input-file=%s --check-prefix=PASS2 %s
+PASS2: foo
+PASS2-NOT: baz
+PASS2-SAME: bar
+PASS2-NEXT: baz
+
+RUN: not FileCheck --input-file=%s --check-prefix=FAIL1 %s
+FAIL1: foo
+FAIL1-SAME: baz
+
+RUN: not FileCheck --input-file=%s --check-prefix=FAIL2 %s
+FAIL2: foo
+FAIL2-NOT: bat
+FAIL2-SAME: bar
diff --git a/test/Instrumentation/AddressSanitizer/X86/asm_attr.ll b/test/Instrumentation/AddressSanitizer/X86/asm_attr.ll
index 0667a1474873..95e4125bc748 100644
--- a/test/Instrumentation/AddressSanitizer/X86/asm_attr.ll
+++ b/test/Instrumentation/AddressSanitizer/X86/asm_attr.ll
@@ -4,8 +4,8 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 ; CHECK-LABEL: mov_no_attr
-; CHECK-NOT: callq __asan_report_load@PLT
-; CHECK-NOT: callq __asan_report_store@PLT
+; CHECK-NOT: callq __asan_report_load8@PLT
+; CHECK-NOT: callq __asan_report_store8@PLT
 define void @mov_no_attr(i64* %dst, i64* %src) {
   tail call void asm sideeffect "movq ($1), %rax  \0A\09movq %rax, ($0)  \0A\09", "r,r,~{memory},~{rax},~{dirflag},~{fpsr},~{flags}"(i64* %dst, i64* %src)
   ret void
diff --git a/test/Instrumentation/AddressSanitizer/X86/asm_cpuid.ll b/test/Instrumentation/AddressSanitizer/X86/asm_cpuid.ll
new file mode 100644
index 000000000000..cfa91d4da633
--- /dev/null
+++ b/test/Instrumentation/AddressSanitizer/X86/asm_cpuid.ll
@@ -0,0 +1,53 @@
+; RUN: opt < %s -asan -S -o %t.ll
+; RUN: FileCheck %s < %t.ll
+; RUN: llc < %t.ll | FileCheck %s --check-prefix=ASM
+
+target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-S32"
+target triple = "i386-pc-windows-msvc"
+
+define void @MyCPUID(i32 %fxn, i32* %out) sanitize_address {
+  %fxn.ptr = alloca i32
+  %a.ptr = alloca i32
+  %b.ptr = alloca i32
+  %c.ptr = alloca i32
+  %d.ptr = alloca i32
+  store i32 %fxn, i32* %fxn.ptr
+  call void asm sideeffect inteldialect "xchg ebx, esi\0A\09mov eax, dword ptr $4\0A\09cpuid\0A\09mov dword ptr $0, eax\0A\09mov dword ptr $1, ebx\0A\09mov dword ptr $2, ecx\0A\09mov dword ptr $3, edx\0A\09xchg ebx, esi", "=*m,=*m,=*m,=*m,*m,~{eax},~{ebx},~{ecx},~{edx},~{esi},~{dirflag},~{fpsr},~{flags}"(i32* %a.ptr, i32* %b.ptr, i32* %c.ptr, i32* %d.ptr, i32* %fxn.ptr)
+
+  %a = load i32, i32* %a.ptr
+  %a.out = getelementptr inbounds i32, i32* %out, i32 0
+  store i32 %a, i32* %a.out
+
+  %b = load i32, i32* %b.ptr
+  %b.out = getelementptr inbounds i32, i32* %out, i32 1
+  store i32 %b, i32* %b.out
+
+  %c = load i32, i32* %c.ptr
+  %c.out = getelementptr inbounds i32, i32* %out, i32 2
+  store i32 %c, i32* %c.out
+
+  %d = load i32, i32* %d.ptr
+  %d.out = getelementptr inbounds i32, i32* %out, i32 3
+  store i32 %d, i32* %d.out
+
+  ret void
+}
+
+; We used to introduce stack mallocs for UAR detection, but that makes LLVM run
+; out of registers on 32-bit platforms. Therefore, we don't do stack malloc on
+; such functions.
+
+; CHECK-LABEL: define void @MyCPUID(i32 %fxn, i32* %out)
+; CHECK: %MyAlloca = alloca [96 x i8], align 32
+; CHECK-NOT: call {{.*}} @__asan_stack_malloc
+
+; The code generator should recognize that all operands are just stack memory.
+; This is important with MS inline asm where operand lists are implicit and all
+; local variables can be referenced freely.
+
+; ASM-LABEL: MyCPUID:
+; ASM:      cpuid
+; ASM-NEXT: movl    %eax, {{[0-9]+}}(%esp)
+; ASM-NEXT: movl    %ebx, {{[0-9]+}}(%esp)
+; ASM-NEXT: movl    %ecx, {{[0-9]+}}(%esp)
+; ASM-NEXT: movl    %edx, {{[0-9]+}}(%esp)
diff --git a/test/Instrumentation/AddressSanitizer/X86/bug_11395.ll b/test/Instrumentation/AddressSanitizer/X86/bug_11395.ll
index 3f944c340e4b..dc943fe257ce 100644
--- a/test/Instrumentation/AddressSanitizer/X86/bug_11395.ll
+++ b/test/Instrumentation/AddressSanitizer/X86/bug_11395.ll
@@ -38,7 +38,7 @@ target triple = "i386-unknown-linux-gnu"
 
 define void @ff_mlp_init_x86(%struct.DSPContext* nocapture %c, %struct.AVCodecContext* nocapture %avctx) nounwind sanitize_address {
 entry:
-  %mlp_filter_channel = getelementptr inbounds %struct.DSPContext* %c, i32 0, i32 131
+  %mlp_filter_channel = getelementptr inbounds %struct.DSPContext, %struct.DSPContext* %c, i32 0, i32 131
   store void (i32*, i32*, i32, i32, i32, i32, i32, i32*)* @mlp_filter_channel_x86, void (i32*, i32*, i32, i32, i32, i32, i32, i32*)** %mlp_filter_channel, align 4, !tbaa !0
   ret void
 }
@@ -52,11 +52,11 @@ entry:
   %iirjump = alloca i8*, align 4
   store i32 %filter_shift, i32* %filter_shift.addr, align 4, !tbaa !3
   store i32 %mask, i32* %mask.addr, align 4, !tbaa !3
-  %arrayidx = getelementptr inbounds [9 x i8*]* @firtable, i32 0, i32 %firorder
-  %0 = load i8** %arrayidx, align 4, !tbaa !0
+  %arrayidx = getelementptr inbounds [9 x i8*], [9 x i8*]* @firtable, i32 0, i32 %firorder
+  %0 = load i8*, i8** %arrayidx, align 4, !tbaa !0
   store i8* %0, i8** %firjump, align 4, !tbaa !0
-  %arrayidx1 = getelementptr inbounds [5 x i8*]* @iirtable, i32 0, i32 %iirorder
-  %1 = load i8** %arrayidx1, align 4, !tbaa !0
+  %arrayidx1 = getelementptr inbounds [5 x i8*], [5 x i8*]* @iirtable, i32 0, i32 %iirorder
+  %1 = load i8*, i8** %arrayidx1, align 4, !tbaa !0
   store i8* %1, i8** %iirjump, align 4, !tbaa !0
   %sub = sub nsw i32 0, %blocksize
   store i32 %sub, i32* %blocksize.addr, align 4, !tbaa !3
diff --git a/test/Instrumentation/AddressSanitizer/asan-vs-gvn.ll b/test/Instrumentation/AddressSanitizer/asan-vs-gvn.ll
index 75adf4061c0d..b5ef8f20689e 100644
--- a/test/Instrumentation/AddressSanitizer/asan-vs-gvn.ll
+++ b/test/Instrumentation/AddressSanitizer/asan-vs-gvn.ll
@@ -15,9 +15,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 
 define i32 @test_widening_bad(i8* %P) nounwind ssp noredzone sanitize_address {
 entry:
-  %tmp = load i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned* @f, i64 0, i32 1), align 4
+  %tmp = load i8, i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned, %struct_of_7_bytes_4_aligned* @f, i64 0, i32 1), align 4
   %conv = zext i8 %tmp to i32
-  %tmp1 = load i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned* @f, i64 0, i32 3), align 1
+  %tmp1 = load i8, i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned, %struct_of_7_bytes_4_aligned* @f, i64 0, i32 3), align 1
   %conv2 = zext i8 %tmp1 to i32
   %add = add nsw i32 %conv, %conv2
   ret i32 %add
@@ -38,9 +38,9 @@ define void @end_test_widening_bad() {
 
 define i32 @test_widening_ok(i8* %P) nounwind ssp noredzone sanitize_address {
 entry:
-  %tmp = load i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned* @f, i64 0, i32 1), align 4
+  %tmp = load i8, i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned, %struct_of_7_bytes_4_aligned* @f, i64 0, i32 1), align 4
   %conv = zext i8 %tmp to i32
-  %tmp1 = load i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned* @f, i64 0, i32 2), align 1
+  %tmp1 = load i8, i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned, %struct_of_7_bytes_4_aligned* @f, i64 0, i32 2), align 1
   %conv2 = zext i8 %tmp1 to i32
   %add = add nsw i32 %conv, %conv2
   ret i32 %add
diff --git a/test/Instrumentation/AddressSanitizer/basic.ll b/test/Instrumentation/AddressSanitizer/basic.ll
index 8020660471b0..2490510fc761 100644
--- a/test/Instrumentation/AddressSanitizer/basic.ll
+++ b/test/Instrumentation/AddressSanitizer/basic.ll
@@ -4,6 +4,7 @@
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-unknown-linux-gnu"
+; CHECK: @llvm.global_ctors = {{.*}}@asan.module_ctor
 
 define i32 @test_load(i32* %a) sanitize_address {
 ; CHECK-LABEL: @test_load
@@ -12,7 +13,7 @@ define i32 @test_load(i32* %a) sanitize_address {
 ; CHECK:   lshr i64 %[[LOAD_ADDR]], 3
 ; CHECK:   {{or|add}}
 ; CHECK:   %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr
-; CHECK:   %[[LOAD_SHADOW:[^ ]*]] = load i8* %[[LOAD_SHADOW_PTR]]
+; CHECK:   %[[LOAD_SHADOW:[^ ]*]] = load i8, i8* %[[LOAD_SHADOW_PTR]]
 ; CHECK:   icmp ne i8
 ; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}!prof ![[PROF:[0-9]+]]
 ;
@@ -28,13 +29,13 @@ define i32 @test_load(i32* %a) sanitize_address {
 ; CHECK:   unreachable
 ;
 ; The actual load.
-; CHECK:   %tmp1 = load i32* %a
+; CHECK:   %tmp1 = load i32, i32* %a
 ; CHECK:   ret i32 %tmp1
 
 
 
 entry:
-  %tmp1 = load i32* %a, align 4
+  %tmp1 = load i32, i32* %a, align 4
   ret i32 %tmp1
 }
 
@@ -45,7 +46,7 @@ define void @test_store(i32* %a) sanitize_address {
 ; CHECK:   lshr i64 %[[STORE_ADDR]], 3
 ; CHECK:   {{or|add}}
 ; CHECK:   %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
-; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8* %[[STORE_SHADOW_PTR]]
+; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]]
 ; CHECK:   icmp ne i8
 ; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
 ;
@@ -103,7 +104,7 @@ entry:
 
 define void @i40test(i40* %a, i40* %b) nounwind uwtable sanitize_address {
   entry:
-  %t = load i40* %a
+  %t = load i40, i40* %a
   store i40 %t, i40* %b, align 8
   ret void
 }
@@ -129,7 +130,7 @@ define void @i64test_align1(i64* %b) nounwind uwtable sanitize_address {
 
 define void @i80test(i80* %a, i80* %b) nounwind uwtable sanitize_address {
   entry:
-  %t = load i80* %a
+  %t = load i80, i80* %a
   store i80 %t, i80* %b, align 8
   ret void
 }
@@ -144,7 +145,7 @@ define void @i80test(i80* %a, i80* %b) nounwind uwtable sanitize_address {
 ; asan should not instrument functions with available_externally linkage.
 define available_externally i32 @f_available_externally(i32* %a) sanitize_address  {
 entry:
-  %tmp1 = load i32* %a
+  %tmp1 = load i32, i32* %a
   ret i32 %tmp1
 }
 ; CHECK-LABEL: @f_available_externally
@@ -169,5 +170,8 @@ define void @memintr_test(i8* %a, i8* %b) nounwind uwtable sanitize_address {
 ; CHECK: __asan_memcpy
 ; CHECK: ret void
 
+; CHECK: define internal void @asan.module_ctor()
+; CHECK: call void @__asan_init_v5()
+
 ; PROF
 ; CHECK: ![[PROF]] = !{!"branch_weights", i32 1, i32 100000}
diff --git a/test/Instrumentation/AddressSanitizer/debug_info.ll b/test/Instrumentation/AddressSanitizer/debug_info.ll
index c0939c5815d4..19d627857abe 100644
--- a/test/Instrumentation/AddressSanitizer/debug_info.ll
+++ b/test/Instrumentation/AddressSanitizer/debug_info.ll
@@ -10,13 +10,13 @@ define i32 @_Z3zzzi(i32 %p) nounwind uwtable sanitize_address {
 entry:
   %p.addr = alloca i32, align 4
   %r = alloca i32, align 4
-  store i32 %p, i32* %p.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %p.addr, metadata !10, metadata !{!"0x102"}), !dbg !11
-  call void @llvm.dbg.declare(metadata i32* %r, metadata !12, metadata !{!"0x102"}), !dbg !14
-  %0 = load i32* %p.addr, align 4, !dbg !14
+  store volatile i32 %p, i32* %p.addr, align 4
+  call void @llvm.dbg.declare(metadata i32* %p.addr, metadata !10, metadata !DIExpression()), !dbg !11
+  call void @llvm.dbg.declare(metadata i32* %r, metadata !12, metadata !DIExpression()), !dbg !14
+  %0 = load i32, i32* %p.addr, align 4, !dbg !14
   %add = add nsw i32 %0, 1, !dbg !14
-  store i32 %add, i32* %r, align 4, !dbg !14
-  %1 = load i32* %r, align 4, !dbg !15
+  store volatile i32 %add, i32* %r, align 4, !dbg !14
+  %1 = load i32, i32* %r, align 4, !dbg !15
   ret i32 %1, !dbg !15
 }
 
@@ -33,30 +33,30 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!17}
 
-!0 = !{!"0x11\004\00clang version 3.3 (trunk 169314)\001\00\000\00\000", !16, !1, !1, !3, !1, null} ; [ DW_TAG_compile_unit ] [/usr/local/google/llvm_cmake_clang/tmp/debuginfo/a.cc] [DW_LANG_C_plus_plus]
-!1 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 (trunk 169314)", isOptimized: true, emissionKind: 0, file: !16, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1)
+!1 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00zzz\00zzz\00_Z3zzzi\001\000\001\000\006\00256\000\001", !16, !6, !7, null, i32 (i32)* @_Z3zzzi, null, null, !1} ; [ DW_TAG_subprogram ] [line 1] [def] [zzz]
-!6 = !{!"0x29", !16} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "zzz", linkageName: "_Z3zzzi", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !16, scope: !6, type: !7, function: i32 (i32)* @_Z3zzzi, variables: !1)
+!6 = !DIFile(filename: "a.cc", directory: "/usr/local/google/llvm_cmake_clang/tmp/debuginfo")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"0x101\00p\0016777217\000", !5, !6, !9} ; [ DW_TAG_arg_variable ] [p] [line 1]
-!11 = !MDLocation(line: 1, scope: !5)
-!12 = !{!"0x100\00r\002\000", !13, !6, !9} ; [ DW_TAG_auto_variable ] [r] [line 2]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p", line: 1, arg: 1, scope: !5, file: !6, type: !9)
+!11 = !DILocation(line: 1, scope: !5)
+!12 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "r", line: 2, scope: !13, file: !6, type: !9)
 
 ; Verify that debug descriptors for argument and local variable will be replaced
 ; with descriptors that end with OpDeref (encoded as 2).
-;   CHECK: ![[ARG_ID]] = {{.*}} ; [ DW_TAG_arg_variable ] [p] [line 1]
-;   CHECK: ![[OPDEREF]] = !{!"0x102\006"}
-;   CHECK: ![[VAR_ID]] = {{.*}} ; [ DW_TAG_auto_variable ] [r] [line 2]
+;   CHECK: ![[ARG_ID]] = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p", arg: 1,{{.*}} line: 1
+;   CHECK: ![[OPDEREF]] = !DIExpression(DW_OP_deref)
+;   CHECK: ![[VAR_ID]] = !DILocalVariable(tag: DW_TAG_auto_variable, name: "r",{{.*}} line: 2
 ; Verify that there are no more variable descriptors.
-;   CHECK-NOT: DW_TAG_arg_variable
-;   CHECK-NOT: DW_TAG_auto_variable
+;   CHECK-NOT: !DILocalVariable(tag: DW_TAG_arg_variable
+;   CHECK-NOT: !DILocalVariable(tag: DW_TAG_auto_variable
 
 
-!13 = !{!"0xb\001\000\000", !16, !5} ; [ DW_TAG_lexical_block ] [/usr/local/google/llvm_cmake_clang/tmp/debuginfo/a.cc]
-!14 = !MDLocation(line: 2, scope: !13)
-!15 = !MDLocation(line: 3, scope: !13)
-!16 = !{!"a.cc", !"/usr/local/google/llvm_cmake_clang/tmp/debuginfo"}
-!17 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = distinct !DILexicalBlock(line: 1, column: 0, file: !16, scope: !5)
+!14 = !DILocation(line: 2, scope: !13)
+!15 = !DILocation(line: 3, scope: !13)
+!16 = !DIFile(filename: "a.cc", directory: "/usr/local/google/llvm_cmake_clang/tmp/debuginfo")
+!17 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Instrumentation/AddressSanitizer/do-not-instrument-promotable-allocas.ll b/test/Instrumentation/AddressSanitizer/do-not-instrument-promotable-allocas.ll
new file mode 100644
index 000000000000..9b1e2415737f
--- /dev/null
+++ b/test/Instrumentation/AddressSanitizer/do-not-instrument-promotable-allocas.ll
@@ -0,0 +1,21 @@
+; RUN: opt < %s -asan -asan-module -asan-instrument-allocas=1 -S | FileCheck %s --check-prefix=CHECK
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+define i32 @test_promotable_allocas() sanitize_address {
+entry:
+; CHECK: %0 = alloca i32, align 4
+; CHECK: store i32 0, i32* %0, align 4
+; CHECK: %1 = load i32, i32* %0, align 4
+; CHECK: ret i32 %1
+
+; CHECK-NOT: __asan_stack_malloc_0
+; CHECK-NOT: icmp
+; CHECK-NOT: call void @__asan_report_store4
+
+  %0 = alloca i32, align 4
+  store i32 0, i32* %0, align 4
+  %1 = load i32, i32* %0, align 4
+  ret i32 %1
+}
diff --git a/test/Instrumentation/AddressSanitizer/experiment-call.ll b/test/Instrumentation/AddressSanitizer/experiment-call.ll
new file mode 100644
index 000000000000..0e339cc8041a
--- /dev/null
+++ b/test/Instrumentation/AddressSanitizer/experiment-call.ll
@@ -0,0 +1,113 @@
+; Test optimization experiments.
+; -asan-force-experiment flag turns all memory accesses into experiments.
+; RUN: opt < %s -asan -asan-module -asan-force-experiment=42 -asan-instrumentation-with-call-threshold=0 -S | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @load1(i8* %p) sanitize_address {
+entry:
+  %t = load i8, i8* %p, align 1
+  ret void
+; CHECK-LABEL: define void @load1
+; CHECK: __asan_exp_load1{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @load2(i16* %p) sanitize_address {
+entry:
+  %t = load i16, i16* %p, align 2
+  ret void
+; CHECK-LABEL: define void @load2
+; CHECK: __asan_exp_load2{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @load4(i32* %p) sanitize_address {
+entry:
+  %t = load i32, i32* %p, align 4
+  ret void
+; CHECK-LABEL: define void @load4
+; CHECK: __asan_exp_load4{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @load8(i64* %p) sanitize_address {
+entry:
+  %t = load i64, i64* %p, align 8
+  ret void
+; CHECK-LABEL: define void @load8
+; CHECK: __asan_exp_load8{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @load16(i128* %p) sanitize_address {
+entry:
+  %t = load i128, i128* %p, align 16
+  ret void
+; CHECK-LABEL: define void @load16
+; CHECK: __asan_exp_load16{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @loadN(i48* %p) sanitize_address {
+entry:
+  %t = load i48, i48* %p, align 1
+  ret void
+; CHECK-LABEL: define void @loadN
+; CHECK: __asan_exp_loadN{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @store1(i8* %p) sanitize_address {
+entry:
+  store i8 1, i8* %p, align 1
+  ret void
+; CHECK-LABEL: define void @store1
+; CHECK: __asan_exp_store1{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @store2(i16* %p) sanitize_address {
+entry:
+  store i16 1, i16* %p, align 2
+  ret void
+; CHECK-LABEL: define void @store2
+; CHECK: __asan_exp_store2{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @store4(i32* %p) sanitize_address {
+entry:
+  store i32 1, i32* %p, align 4
+  ret void
+; CHECK-LABEL: define void @store4
+; CHECK: __asan_exp_store4{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @store8(i64* %p) sanitize_address {
+entry:
+  store i64 1, i64* %p, align 8
+  ret void
+; CHECK-LABEL: define void @store8
+; CHECK: __asan_exp_store8{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @store16(i128* %p) sanitize_address {
+entry:
+  store i128 1, i128* %p, align 16
+  ret void
+; CHECK-LABEL: define void @store16
+; CHECK: __asan_exp_store16{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @storeN(i48* %p) sanitize_address {
+entry:
+  store i48 1, i48* %p, align 1
+  ret void
+; CHECK-LABEL: define void @storeN
+; CHECK: __asan_exp_storeN{{.*}} i32 42
+; CHECK: ret void
+}
diff --git a/test/Instrumentation/AddressSanitizer/experiment.ll b/test/Instrumentation/AddressSanitizer/experiment.ll
new file mode 100644
index 000000000000..aaa125f5d408
--- /dev/null
+++ b/test/Instrumentation/AddressSanitizer/experiment.ll
@@ -0,0 +1,113 @@
+; Test optimization experiments.
+; -asan-force-experiment flag turns all memory accesses into experiments.
+; RUN: opt < %s -asan -asan-module -asan-force-experiment=42 -S | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @load1(i8* %p) sanitize_address {
+entry:
+  %t = load i8, i8* %p, align 1
+  ret void
+; CHECK-LABEL: define void @load1
+; CHECK: __asan_report_exp_load1{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @load2(i16* %p) sanitize_address {
+entry:
+  %t = load i16, i16* %p, align 2
+  ret void
+; CHECK-LABEL: define void @load2
+; CHECK: __asan_report_exp_load2{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @load4(i32* %p) sanitize_address {
+entry:
+  %t = load i32, i32* %p, align 4
+  ret void
+; CHECK-LABEL: define void @load4
+; CHECK: __asan_report_exp_load4{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @load8(i64* %p) sanitize_address {
+entry:
+  %t = load i64, i64* %p, align 8
+  ret void
+; CHECK-LABEL: define void @load8
+; CHECK: __asan_report_exp_load8{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @load16(i128* %p) sanitize_address {
+entry:
+  %t = load i128, i128* %p, align 16
+  ret void
+; CHECK-LABEL: define void @load16
+; CHECK: __asan_report_exp_load16{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @loadN(i48* %p) sanitize_address {
+entry:
+  %t = load i48, i48* %p, align 1
+  ret void
+; CHECK-LABEL: define void @loadN
+; CHECK: __asan_report_exp_load_n{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @store1(i8* %p) sanitize_address {
+entry:
+  store i8 1, i8* %p, align 1
+  ret void
+; CHECK-LABEL: define void @store1
+; CHECK: __asan_report_exp_store1{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @store2(i16* %p) sanitize_address {
+entry:
+  store i16 1, i16* %p, align 2
+  ret void
+; CHECK-LABEL: define void @store2
+; CHECK: __asan_report_exp_store2{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @store4(i32* %p) sanitize_address {
+entry:
+  store i32 1, i32* %p, align 4
+  ret void
+; CHECK-LABEL: define void @store4
+; CHECK: __asan_report_exp_store4{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @store8(i64* %p) sanitize_address {
+entry:
+  store i64 1, i64* %p, align 8
+  ret void
+; CHECK-LABEL: define void @store8
+; CHECK: __asan_report_exp_store8{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @store16(i128* %p) sanitize_address {
+entry:
+  store i128 1, i128* %p, align 16
+  ret void
+; CHECK-LABEL: define void @store16
+; CHECK: __asan_report_exp_store16{{.*}} i32 42
+; CHECK: ret void
+}
+
+define void @storeN(i48* %p) sanitize_address {
+entry:
+  store i48 1, i48* %p, align 1
+  ret void
+; CHECK-LABEL: define void @storeN
+; CHECK: __asan_report_exp_store_n{{.*}} i32 42
+; CHECK: ret void
+}
diff --git a/test/Instrumentation/AddressSanitizer/freebsd.ll b/test/Instrumentation/AddressSanitizer/freebsd.ll
index 359529fc8fcd..5178432d63aa 100644
--- a/test/Instrumentation/AddressSanitizer/freebsd.ll
+++ b/test/Instrumentation/AddressSanitizer/freebsd.ll
@@ -10,7 +10,7 @@
 
 define i32 @read_4_bytes(i32* %a) sanitize_address {
 entry:
-  %tmp1 = load i32* %a, align 4
+  %tmp1 = load i32, i32* %a, align 4
   ret i32 %tmp1
 }
 
diff --git a/test/Instrumentation/AddressSanitizer/global_metadata.ll b/test/Instrumentation/AddressSanitizer/global_metadata.ll
index 39017454f2ef..6cf1ee8e8d45 100644
--- a/test/Instrumentation/AddressSanitizer/global_metadata.ll
+++ b/test/Instrumentation/AddressSanitizer/global_metadata.ll
@@ -16,9 +16,9 @@ target triple = "x86_64-unknown-linux-gnu"
 ; CHECK: @.str = internal unnamed_addr constant { [14 x i8], [50 x i8] } { [14 x i8] c"Hello, world!\00", [50 x i8] zeroinitializer }, align 32
 
 ; Check emitted location descriptions:
-; CHECK: [[VARNAME:@__asan_gen_[0-9]+]] = private unnamed_addr constant [7 x i8] c"global\00", align 1
-; CHECK: [[FILENAME:@__asan_gen_[0-9]+]] = private unnamed_addr constant [22 x i8] c"/tmp/asan-globals.cpp\00", align 1
-; CHECK: [[LOCDESCR:@__asan_gen_[0-9]+]] = private unnamed_addr constant { [22 x i8]*, i32, i32 } { [22 x i8]* [[FILENAME]], i32 5, i32 5 }
+; CHECK: [[VARNAME:@__asan_gen_.[0-9]+]] = private unnamed_addr constant [7 x i8] c"global\00", align 1
+; CHECK: [[FILENAME:@__asan_gen_.[0-9]+]] = private unnamed_addr constant [22 x i8] c"/tmp/asan-globals.cpp\00", align 1
+; CHECK: [[LOCDESCR:@__asan_gen_.[0-9]+]] = private unnamed_addr constant { [22 x i8]*, i32, i32 } { [22 x i8]* [[FILENAME]], i32 5, i32 5 }
 
 ; Check that location decriptors and global names were passed into __asan_register_globals:
 ; CHECK: i64 ptrtoint ([7 x i8]* [[VARNAME]] to i64)
@@ -27,7 +27,7 @@ target triple = "x86_64-unknown-linux-gnu"
 ; Function Attrs: nounwind sanitize_address
 define internal void @__cxx_global_var_init() #0 section ".text.startup" {
 entry:
-  %0 = load i32* @global, align 4
+  %0 = load i32, i32* @global, align 4
   store i32 %0, i32* @dyn_init_global, align 4
   ret void
 }
@@ -36,7 +36,7 @@ entry:
 define void @_Z4funcv() #1 {
 entry:
   %literal = alloca i8*, align 8
-  store i8* getelementptr inbounds ([14 x i8]* @.str, i32 0, i32 0), i8** %literal, align 8
+  store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str, i32 0, i32 0), i8** %literal, align 8
   ret void
 }
 
diff --git a/test/Instrumentation/AddressSanitizer/instrument-dynamic-allocas.ll b/test/Instrumentation/AddressSanitizer/instrument-dynamic-allocas.ll
index 25807bb05a7a..18a86a9b88f7 100644
--- a/test/Instrumentation/AddressSanitizer/instrument-dynamic-allocas.ll
+++ b/test/Instrumentation/AddressSanitizer/instrument-dynamic-allocas.ll
@@ -15,10 +15,11 @@ entry:
 ; CHECK-NOALLOCA-NOT: store i32 -875836469
   %0 = alloca i32, align 4
   %1 = alloca i8*
-  store i32 %len, i32* %0, align 4
-  %2 = load i32* %0, align 4
+  store volatile i32 %len, i32* %0, align 4
+  %2 = load i32, i32* %0, align 4
   %3 = zext i32 %2 to i64
   %4 = alloca i8, i64 %3, align 32
+  store volatile i8 0, i8* %4
   ret void
 }
 
diff --git a/test/Instrumentation/AddressSanitizer/instrument-stack.ll b/test/Instrumentation/AddressSanitizer/instrument-stack.ll
new file mode 100644
index 000000000000..52978d92cb0e
--- /dev/null
+++ b/test/Instrumentation/AddressSanitizer/instrument-stack.ll
@@ -0,0 +1,48 @@
+; This test checks that we are not instrumenting direct inbound stack accesses.
+; RUN: opt < %s -asan -asan-module -asan-opt-stack -S | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+;@sink = global i32* null, align 4
+
+; Ignore direct inbounds stack access.
+define void @foo() uwtable sanitize_address {
+entry:
+  %a = alloca i32, align 4
+  store i32 42, i32* %a, align 4
+  ret void
+; CHECK-LABEL: define void @foo
+; CHECK-NOT: __asan_report
+; CHECK: ret void
+}
+
+; Don't ignore dynamic indexing.
+define void @baz(i64 %i) sanitize_address {
+entry:
+  %a = alloca [10 x i32], align 4
+  %e = getelementptr inbounds [10 x i32], [10 x i32]* %a, i32 0, i64 %i
+  store i32 42, i32* %e, align 4
+  ret void
+; CHECK-LABEL: define void @baz
+; CHECK: __asan_report
+; CHECK: ret void
+}
+
+define void @bar() sanitize_address {
+entry:
+  %a = alloca [10 x i32], align 4
+  %e = getelementptr inbounds [10 x i32], [10 x i32]* %a, i32 0, i64 12
+  store i32 42, i32* %e, align 4
+  ret void
+; CHECK-LABEL: define void @bar
+; CHECK: __asan_report
+; CHECK: ret void
+}
+
+define void @endoftests() sanitize_address {
+entry:
+  ret void
+; CHECK-LABEL: define void @endoftests
+}
+
diff --git a/test/Instrumentation/AddressSanitizer/instrument_global.ll b/test/Instrumentation/AddressSanitizer/instrument_global.ll
index 259c8153227d..7df3d22dcdea 100644
--- a/test/Instrumentation/AddressSanitizer/instrument_global.ll
+++ b/test/Instrumentation/AddressSanitizer/instrument_global.ll
@@ -20,7 +20,7 @@ target triple = "x86_64-unknown-linux-gnu"
 ; GlobSt is declared here, and has static initializer -- ok to optimize.
 define i32 @AccessGlobSt_0_2() sanitize_address {
 entry:
-    %0 = load i32* getelementptr inbounds ([10 x i32]* @GlobSt, i64 0, i64 2), align 8
+    %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @GlobSt, i64 0, i64 2), align 8
     ret i32 %0
 ; CHECK-LABEL: define i32 @AccessGlobSt_0_2
 ; CHECK-NOT: __asan_report
@@ -30,7 +30,7 @@ entry:
 ; GlobSt is accessed out of bounds -- can't optimize
 define i32 @AccessGlobSt_0_12() sanitize_address {
 entry:
-    %0 = load i32* getelementptr inbounds ([10 x i32]* @GlobSt, i64 0, i64 12), align 8
+    %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @GlobSt, i64 0, i64 12), align 8
     ret i32 %0
 ; CHECK-LABEL: define i32 @AccessGlobSt_0_12
 ; CHECK: __asan_report
@@ -40,7 +40,7 @@ entry:
 ; GlobSt is accessed with Gep that has non-0 first index -- can't optimize.
 define i32 @AccessGlobSt_1_2() sanitize_address {
 entry:
-    %0 = load i32* getelementptr inbounds ([10 x i32]* @GlobSt, i64 1, i64 2), align 8
+    %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @GlobSt, i64 1, i64 2), align 8
     ret i32 %0
 ; CHECK-LABEL: define i32 @AccessGlobSt_1_2
 ; CHECK: __asan_report
@@ -50,7 +50,7 @@ entry:
 ; GlobDy is declared with dynamic initializer -- can't optimize.
 define i32 @AccessGlobDy_0_2() sanitize_address {
 entry:
-    %0 = load i32* getelementptr inbounds ([10 x i32]* @GlobDy, i64 0, i64 2), align 8
+    %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @GlobDy, i64 0, i64 2), align 8
     ret i32 %0
 ; CHECK-LABEL: define i32 @AccessGlobDy_0_2
 ; CHECK: __asan_report
@@ -60,7 +60,7 @@ entry:
 ; GlobEx is an external global -- can't optimize.
 define i32 @AccessGlobEx_0_2() sanitize_address {
 entry:
-    %0 = load i32* getelementptr inbounds ([10 x i32]* @GlobEx, i64 0, i64 2), align 8
+    %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @GlobEx, i64 0, i64 2), align 8
     ret i32 %0
 ; CHECK-LABEL: define i32 @AccessGlobEx_0_2
 ; CHECK: __asan_report
diff --git a/test/Instrumentation/AddressSanitizer/instrument_load_then_store.ll b/test/Instrumentation/AddressSanitizer/instrument_load_then_store.ll
index 195785ff5e3b..01a7a6610caf 100644
--- a/test/Instrumentation/AddressSanitizer/instrument_load_then_store.ll
+++ b/test/Instrumentation/AddressSanitizer/instrument_load_then_store.ll
@@ -6,7 +6,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-unknown-linux-gnu"
 define void @IncrementMe(i32* %a) sanitize_address {
 entry:
-  %tmp1 = load i32* %a, align 4
+  %tmp1 = load i32, i32* %a, align 4
   %tmp2 = add i32 %tmp1,  1
   store i32 %tmp2, i32* %a, align 4
   ret void
diff --git a/test/Instrumentation/AddressSanitizer/instrumentation-with-call-threshold.ll b/test/Instrumentation/AddressSanitizer/instrumentation-with-call-threshold.ll
index adb434112cd2..8e0275d2c17d 100644
--- a/test/Instrumentation/AddressSanitizer/instrumentation-with-call-threshold.ll
+++ b/test/Instrumentation/AddressSanitizer/instrumentation-with-call-threshold.ll
@@ -20,10 +20,10 @@ entry:
 ; CHECK-CUSTOM-PREFIX: call void @__foo_load8
 ; CHECK-CUSTOM-PREFIX: call void @__foo_loadN
 ; CHECK-INLINE-NOT: call void @__asan_load
-  %tmp1 = load i32* %a, align 4
-  %tmp2 = load i64* %b, align 8
-  %tmp3 = load i512* %c, align 32
-  %tmp4 = load i80* %d, align 8
+  %tmp1 = load i32, i32* %a, align 4
+  %tmp2 = load i64, i64* %b, align 8
+  %tmp3 = load i512, i512* %c, align 32
+  %tmp4 = load i80, i80* %d, align 8
   ret void
 }
 
diff --git a/test/Instrumentation/AddressSanitizer/lifetime-uar.ll b/test/Instrumentation/AddressSanitizer/lifetime-uar.ll
index 25577de445be..efba8ce4e8c5 100644
--- a/test/Instrumentation/AddressSanitizer/lifetime-uar.ll
+++ b/test/Instrumentation/AddressSanitizer/lifetime-uar.ll
@@ -17,8 +17,8 @@ entry:
   ; Memory is unpoisoned at llvm.lifetime.start
   ; CHECK: call void @__asan_unpoison_stack_memory(i64 %{{[^ ]+}}, i64 1)
 
-  store i32 0, i32* %retval
-  store i8 0, i8* %c, align 1
+  store volatile i32 0, i32* %retval
+  store volatile i8 0, i8* %c, align 1
 
   call void @llvm.lifetime.end(i64 1, i8* %c)
   ; Memory is poisoned at llvm.lifetime.end
diff --git a/test/Instrumentation/AddressSanitizer/lifetime.ll b/test/Instrumentation/AddressSanitizer/lifetime.ll
index 175a07d51e69..ac324a98b981 100644
--- a/test/Instrumentation/AddressSanitizer/lifetime.ll
+++ b/test/Instrumentation/AddressSanitizer/lifetime.ll
@@ -12,6 +12,7 @@ entry:
   %i = alloca i32, align 4
   %i.ptr = bitcast i32* %i to i8*
   call void @llvm.lifetime.start(i64 -1, i8* %i.ptr)
+  store volatile i8 0, i8* %i.ptr
   call void @llvm.lifetime.end(i64 -1, i8* %i.ptr)
 
 ; Check that lifetime with no size are ignored.
@@ -30,6 +31,7 @@ define void @lifetime() sanitize_address {
   %i = alloca i32, align 4
   %i.ptr = bitcast i32* %i to i8*
   call void @llvm.lifetime.start(i64 3, i8* %i.ptr)
+  store volatile i8 0, i8* %i.ptr
   ; Memory is unpoisoned at llvm.lifetime.start
   ; CHECK: %[[VAR:[^ ]*]] = ptrtoint i32* %{{[^ ]+}} to i64
   ; CHECK-NEXT: call void @__asan_unpoison_stack_memory(i64 %[[VAR]], i64 3)
@@ -43,12 +45,14 @@ define void @lifetime() sanitize_address {
   %arr = alloca [10 x i32], align 16
   %arr.ptr = bitcast [10 x i32]* %arr to i8*
   call void @llvm.lifetime.start(i64 40, i8* %arr.ptr)
+  store volatile i8 0, i8* %arr.ptr
   ; CHECK: call void @__asan_unpoison_stack_memory(i64 %{{[^ ]+}}, i64 40)
   call void @llvm.lifetime.end(i64 40, i8* %arr.ptr)
   ; CHECK: call void @__asan_poison_stack_memory(i64 %{{[^ ]+}}, i64 40)
 
   ; One more lifetime start/end for the same variable %i.
   call void @llvm.lifetime.start(i64 4, i8* %i.ptr)
+  store volatile i8 0, i8* %i.ptr
   ; CHECK: call void @__asan_unpoison_stack_memory(i64 %{{[^ ]+}}, i64 4)
   call void @llvm.lifetime.end(i64 4, i8* %i.ptr)
   ; CHECK: call void @__asan_poison_stack_memory(i64 %{{[^ ]+}}, i64 4)
@@ -68,6 +72,7 @@ entry:
   %i = alloca i64, align 4
   %i.ptr = bitcast i64* %i to i8*
   call void @llvm.lifetime.start(i64 8, i8* %i.ptr)
+  store volatile i8 0, i8* %i.ptr
   ; CHECK: __asan_unpoison_stack_memory
   br i1 %x, label %bb0, label %bb1
 
diff --git a/test/Instrumentation/AddressSanitizer/stack-poisoning.ll b/test/Instrumentation/AddressSanitizer/stack-poisoning.ll
index ace12d03b70e..0c9ffe2d18f4 100644
--- a/test/Instrumentation/AddressSanitizer/stack-poisoning.ll
+++ b/test/Instrumentation/AddressSanitizer/stack-poisoning.ll
@@ -12,7 +12,7 @@ entry:
 ; CHECK-PLAIN: ret void
 
 ; CHECK-UAR-LABEL: Bar
-; CHECK-UAR: load i32* @__asan_option_detect_stack_use_after_return
+; CHECK-UAR: load i32, i32* @__asan_option_detect_stack_use_after_return
 ; CHECK-UAR: label
 ; CHECK-UAR: call i64 @__asan_stack_malloc_1
 ; CHECK-UAR: label
@@ -35,7 +35,7 @@ entry:
 ; CHECK-UAR: ret void
 
   %x = alloca [20 x i8], align 16
-  %arraydecay = getelementptr inbounds [20 x i8]* %x, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [20 x i8], [20 x i8]* %x, i64 0, i64 0
   call void @Foo(i8* %arraydecay)
   ret void
 }
diff --git a/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll b/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll
index 43711b7a1f27..9c058742dbf5 100644
--- a/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll
+++ b/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll
@@ -8,7 +8,7 @@ entry:
 ; CHECK-LABEL: Func1
 
 ; CHECK: entry:
-; CHECK: load i32* @__asan_option_detect_stack_use_after_return
+; CHECK: load i32, i32* @__asan_option_detect_stack_use_after_return
 
 ; CHECK: <label>:[[UAR_ENABLED_BB:[0-9]+]]
 ; CHECK: [[FAKE_STACK_RT:%[0-9]+]] = call i64 @__asan_stack_malloc_
@@ -26,6 +26,8 @@ entry:
 ; CHECK: ret void
 
   %XXX = alloca [20 x i8], align 1
+  %arr.ptr = bitcast [20 x i8]* %XXX to i8*
+  store volatile i8 0, i8* %arr.ptr
   ret void
 }
 
@@ -37,6 +39,8 @@ entry:
 ; CHECK: ret void
 
   %XXX = alloca [20 x i8], align 1
+  %arr.ptr = bitcast [20 x i8]* %XXX to i8*
+  store volatile i8 0, i8* %arr.ptr
   call void asm sideeffect "mov %%rbx, %%rcx", "~{dirflag},~{fpsr},~{flags}"() nounwind
   ret void
 }
diff --git a/test/Instrumentation/AddressSanitizer/stack_layout.ll b/test/Instrumentation/AddressSanitizer/stack_layout.ll
index 97e3bbb58723..6575dd62f876 100644
--- a/test/Instrumentation/AddressSanitizer/stack_layout.ll
+++ b/test/Instrumentation/AddressSanitizer/stack_layout.ll
@@ -26,6 +26,12 @@ entry:
   %XXX = alloca [10 x i8], align 1
   %YYY = alloca [20 x i8], align 1
   %ZZZ = alloca [30 x i8], align 1
+  %arr1.ptr = bitcast [10 x i8]* %XXX to i8*
+  store volatile i8 0, i8* %arr1.ptr
+  %arr2.ptr = bitcast [20 x i8]* %YYY to i8*
+  store volatile i8 0, i8* %arr2.ptr
+  %arr3.ptr = bitcast [30 x i8]* %ZZZ to i8*
+  store volatile i8 0, i8* %arr3.ptr
   ret void
 }
 
@@ -41,6 +47,12 @@ entry:
   %AAA = alloca [5 x i8], align 1
   %BBB = alloca [55 x i8], align 1
   %CCC = alloca [555 x i8], align 1
+  %arr1.ptr = bitcast [5 x i8]* %AAA to i8*
+  store volatile i8 0, i8* %arr1.ptr
+  %arr2.ptr = bitcast [55 x i8]* %BBB to i8*
+  store volatile i8 0, i8* %arr2.ptr
+  %arr3.ptr = bitcast [555 x i8]* %CCC to i8*
+  store volatile i8 0, i8* %arr3.ptr
   ret void
 }
 
@@ -57,5 +69,11 @@ entry:
   %AAA = alloca [128 x i8], align 16
   %BBB = alloca [128 x i8], align 64
   %CCC = alloca [128 x i8], align 256
+  %arr1.ptr = bitcast [128 x i8]* %AAA to i8*
+  store volatile i8 0, i8* %arr1.ptr
+  %arr2.ptr = bitcast [128 x i8]* %BBB to i8*
+  store volatile i8 0, i8* %arr2.ptr
+  %arr3.ptr = bitcast [128 x i8]* %CCC to i8*
+  store volatile i8 0, i8* %arr3.ptr
   ret void
 }
diff --git a/test/Instrumentation/AddressSanitizer/test64.ll b/test/Instrumentation/AddressSanitizer/test64.ll
index fd93f4576ae4..85a29e67eba5 100644
--- a/test/Instrumentation/AddressSanitizer/test64.ll
+++ b/test/Instrumentation/AddressSanitizer/test64.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-unknown-linux-gnu"
 define i32 @read_4_bytes(i32* %a) sanitize_address {
 entry:
-  %tmp1 = load i32* %a, align 4
+  %tmp1 = load i32, i32* %a, align 4
   ret i32 %tmp1
 }
 ; CHECK-LABEL: @read_4_bytes
diff --git a/test/Instrumentation/AddressSanitizer/ubsan.ll b/test/Instrumentation/AddressSanitizer/ubsan.ll
index 5535efe4b4dd..23b7ef4537c4 100644
--- a/test/Instrumentation/AddressSanitizer/ubsan.ll
+++ b/test/Instrumentation/AddressSanitizer/ubsan.ll
@@ -17,9 +17,9 @@ define void @_Z3BarP1A(%struct.A* %a) uwtable sanitize_address {
 ; CHECK-LABEL: define void @_Z3BarP1A
 entry:
   %0 = bitcast %struct.A* %a to void (%struct.A*)***
-  %vtable = load void (%struct.A*)*** %0, align 8
+  %vtable = load void (%struct.A*)**, void (%struct.A*)*** %0, align 8
 ; CHECK: __asan_report_load8
-  %1 = load void (%struct.A*)** %vtable, align 8
+  %1 = load void (%struct.A*)*, void (%struct.A*)** %vtable, align 8
 ; CHECK: __asan_report_load8
   %2 = ptrtoint void (%struct.A*)** %vtable to i64
   %3 = xor i64 %2, -303164226014115343, !nosanitize !0
@@ -32,9 +32,9 @@ entry:
   %10 = xor i64 %9, %8, !nosanitize !0
   %11 = mul i64 %10, -7070675565921424023, !nosanitize !0
   %12 = and i64 %11, 127, !nosanitize !0
-  %13 = getelementptr inbounds [128 x i64]* @__ubsan_vptr_type_cache, i64 0, i64 %12, !nosanitize !0
+  %13 = getelementptr inbounds [128 x i64], [128 x i64]* @__ubsan_vptr_type_cache, i64 0, i64 %12, !nosanitize !0
 ; CHECK-NOT: __asan_report_load8
-  %14 = load i64* %13, align 8, !nosanitize !0
+  %14 = load i64, i64* %13, align 8, !nosanitize !0
   %15 = icmp eq i64 %14, %11, !nosanitize !0
   br i1 %15, label %cont, label %handler.dynamic_type_cache_miss, !nosanitize !0
 
diff --git a/test/Instrumentation/BoundsChecking/many-trap.ll b/test/Instrumentation/BoundsChecking/many-trap.ll
index 0bbb9592b059..58944876e804 100644
--- a/test/Instrumentation/BoundsChecking/many-trap.ll
+++ b/test/Instrumentation/BoundsChecking/many-trap.ll
@@ -5,8 +5,8 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; CHECK: @f1
 define void @f1(i64 %x) nounwind {
   %1 = alloca i128, i64 %x
-  %2 = load i128* %1, align 4
-  %3 = load i128* %1, align 4
+  %2 = load i128, i128* %1, align 4
+  %3 = load i128, i128* %1, align 4
   ret void
 ; CHECK: call void @llvm.trap()
 ; CHECK: call void @llvm.trap()
diff --git a/test/Instrumentation/BoundsChecking/phi.ll b/test/Instrumentation/BoundsChecking/phi.ll
index 25a5ed12c62d..15361b64d77c 100644
--- a/test/Instrumentation/BoundsChecking/phi.ll
+++ b/test/Instrumentation/BoundsChecking/phi.ll
@@ -8,15 +8,15 @@ target datalayout = "e-p:64:64:64-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-
 ; CHECK-NOT: trap
 define void @f1(i8* nocapture %c) {
 entry:
-  %0 = load i8* %c, align 1
+  %0 = load i8, i8* %c, align 1
   %tobool1 = icmp eq i8 %0, 0
   br i1 %tobool1, label %while.end, label %while.body
 
 while.body:
   %c.addr.02 = phi i8* [ %incdec.ptr, %while.body ], [ %c, %entry ]
-  %incdec.ptr = getelementptr inbounds i8* %c.addr.02, i64 -1
+  %incdec.ptr = getelementptr inbounds i8, i8* %c.addr.02, i64 -1
   store i8 100, i8* %c.addr.02, align 1
-  %1 = load i8* %incdec.ptr, align 1
+  %1 = load i8, i8* %incdec.ptr, align 1
   %tobool = icmp eq i8 %1, 0
   br i1 %tobool, label %while.end, label %while.body
 
@@ -28,7 +28,7 @@ while.end:
 ; CHECK: f2
 define void @f2() {
 while.body.i.preheader:
-  %addr = getelementptr inbounds [10 x i8]* @global, i64 0, i64 9
+  %addr = getelementptr inbounds [10 x i8], [10 x i8]* @global, i64 0, i64 9
   br label %while.body.i
 
 while.body.i:
@@ -36,14 +36,14 @@ while.body.i:
 ; CHECK-NEXT: phi
 ; CHECK-NOT: phi
   %c.addr.02.i = phi i8* [ %incdec.ptr.i, %while.body.i ], [ %addr, %while.body.i.preheader ]
-  %incdec.ptr.i = getelementptr inbounds i8* %c.addr.02.i, i64 -1
+  %incdec.ptr.i = getelementptr inbounds i8, i8* %c.addr.02.i, i64 -1
 ; CHECK: sub i64 10, %0
 ; CHECK-NEXT: icmp ult i64 10, %0
 ; CHECK-NEXT: icmp ult i64 {{.*}}, 1
 ; CHECK-NEXT: or i1
 ; CHECK-NEXT: br {{.*}}, label %trap
   store i8 100, i8* %c.addr.02.i, align 1
-  %0 = load i8* %incdec.ptr.i, align 1
+  %0 = load i8, i8* %incdec.ptr.i, align 1
   %tobool.i = icmp eq i8 %0, 0
   br i1 %tobool.i, label %fn.exit, label %while.body.i
 
@@ -61,15 +61,15 @@ define void @f1_as1(i8 addrspace(1)* nocapture %c) {
 ; CHECK: add i16 undef, -1
 ; CHECK-NOT: trap
 entry:
-  %0 = load i8 addrspace(1)* %c, align 1
+  %0 = load i8, i8 addrspace(1)* %c, align 1
   %tobool1 = icmp eq i8 %0, 0
   br i1 %tobool1, label %while.end, label %while.body
 
 while.body:
   %c.addr.02 = phi i8 addrspace(1)* [ %incdec.ptr, %while.body ], [ %c, %entry ]
-  %incdec.ptr = getelementptr inbounds i8 addrspace(1)* %c.addr.02, i64 -1
+  %incdec.ptr = getelementptr inbounds i8, i8 addrspace(1)* %c.addr.02, i64 -1
   store i8 100, i8 addrspace(1)* %c.addr.02, align 1
-  %1 = load i8 addrspace(1)* %incdec.ptr, align 1
+  %1 = load i8, i8 addrspace(1)* %incdec.ptr, align 1
   %tobool = icmp eq i8 %1, 0
   br i1 %tobool, label %while.end, label %while.body
 
@@ -81,7 +81,7 @@ while.end:
 define void @f2_as1() {
 ; CHECK: @f2_as1
 while.body.i.preheader:
-  %addr = getelementptr inbounds [10 x i8] addrspace(1)* @global_as1, i16 0, i16 9
+  %addr = getelementptr inbounds [10 x i8], [10 x i8] addrspace(1)* @global_as1, i16 0, i16 9
   br label %while.body.i
 
 while.body.i:
@@ -89,14 +89,14 @@ while.body.i:
 ; CHECK-NEXT: phi
 ; CHECK-NOT: phi
   %c.addr.02.i = phi i8 addrspace(1)* [ %incdec.ptr.i, %while.body.i ], [ %addr, %while.body.i.preheader ]
-  %incdec.ptr.i = getelementptr inbounds i8 addrspace(1)* %c.addr.02.i, i16 -1
+  %incdec.ptr.i = getelementptr inbounds i8, i8 addrspace(1)* %c.addr.02.i, i16 -1
 ; CHECK: sub i16 10, %0
 ; CHECK-NEXT: icmp ult i16 10, %0
 ; CHECK-NEXT: icmp ult i16 {{.*}}, 1
 ; CHECK-NEXT: or i1
 ; CHECK-NEXT: br {{.*}}, label %trap
   store i8 100, i8 addrspace(1)* %c.addr.02.i, align 1
-  %0 = load i8 addrspace(1)* %incdec.ptr.i, align 1
+  %0 = load i8, i8 addrspace(1)* %incdec.ptr.i, align 1
   %tobool.i = icmp eq i8 %0, 0
   br i1 %tobool.i, label %fn.exit, label %while.body.i
 
diff --git a/test/Instrumentation/BoundsChecking/simple-32.ll b/test/Instrumentation/BoundsChecking/simple-32.ll
index 38b210f7e236..0fdb0a48625f 100644
--- a/test/Instrumentation/BoundsChecking/simple-32.ll
+++ b/test/Instrumentation/BoundsChecking/simple-32.ll
@@ -9,9 +9,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 define i16 @f() {
 entry:
   %packed1 = alloca %struct.s2_packed, align 8
-  %gep = getelementptr inbounds %struct.s2_packed* %packed1, i32 0, i32 4
+  %gep = getelementptr inbounds %struct.s2_packed, %struct.s2_packed* %packed1, i32 0, i32 4
   %ptr = bitcast i16* %gep to i32*
-  %val = load i32* %ptr, align 4
+  %val = load i32, i32* %ptr, align 4
   %valt = trunc i32 %val to i16
   ret i16 %valt
 }
@@ -21,9 +21,9 @@ entry:
 define i16 @f2() {
 entry:
   %packed1 = alloca %struct.s2_packed, align 8
-  %gep = getelementptr inbounds %struct.s2_packed* %packed1, i32 0, i32 4
+  %gep = getelementptr inbounds %struct.s2_packed, %struct.s2_packed* %packed1, i32 0, i32 4
   %ptr = bitcast i16* %gep to i48*
-  %val = load i48* %ptr, align 4
+  %val = load i48, i48* %ptr, align 4
   %valt = trunc i48 %val to i16
   ret i16 %valt
 }
diff --git a/test/Instrumentation/BoundsChecking/simple.ll b/test/Instrumentation/BoundsChecking/simple.ll
index ddacf6d412bd..5fae2f48c288 100644
--- a/test/Instrumentation/BoundsChecking/simple.ll
+++ b/test/Instrumentation/BoundsChecking/simple.ll
@@ -14,7 +14,7 @@ declare noalias i8* @realloc(i8* nocapture, i64) nounwind
 define void @f1() nounwind {
   %1 = tail call i8* @malloc(i64 32)
   %2 = bitcast i8* %1 to i32*
-  %idx = getelementptr inbounds i32* %2, i64 2
+  %idx = getelementptr inbounds i32, i32* %2, i64 2
 ; CHECK-NOT: trap
   store i32 3, i32* %idx, align 4
   ret void
@@ -24,7 +24,7 @@ define void @f1() nounwind {
 define void @f2() nounwind {
   %1 = tail call i8* @malloc(i64 32)
   %2 = bitcast i8* %1 to i32*
-  %idx = getelementptr inbounds i32* %2, i64 8
+  %idx = getelementptr inbounds i32, i32* %2, i64 8
 ; CHECK: trap
   store i32 3, i32* %idx, align 4
   ret void
@@ -34,7 +34,7 @@ define void @f2() nounwind {
 define void @f3(i64 %x) nounwind {
   %1 = tail call i8* @calloc(i64 4, i64 %x)
   %2 = bitcast i8* %1 to i32*
-  %idx = getelementptr inbounds i32* %2, i64 8
+  %idx = getelementptr inbounds i32, i32* %2, i64 8
 ; CHECK: mul i64 4, %
 ; CHECK: sub i64 {{.*}}, 32
 ; CHECK-NEXT: icmp ult i64 {{.*}}, 32
@@ -49,27 +49,27 @@ define void @f3(i64 %x) nounwind {
 define void @f4(i64 %x) nounwind {
   %1 = tail call i8* @realloc(i8* null, i64 %x) nounwind
   %2 = bitcast i8* %1 to i32*
-  %idx = getelementptr inbounds i32* %2, i64 8
+  %idx = getelementptr inbounds i32, i32* %2, i64 8
 ; CHECK: trap
-  %3 = load i32* %idx, align 4
+  %3 = load i32, i32* %idx, align 4
   ret void
 }
 
 ; CHECK: @f5
 define void @f5(i64 %x) nounwind {
-  %idx = getelementptr inbounds [8 x i8]* @.str, i64 0, i64 %x
+  %idx = getelementptr inbounds [8 x i8], [8 x i8]* @.str, i64 0, i64 %x
 ; CHECK: trap
-  %1 = load i8* %idx, align 4
+  %1 = load i8, i8* %idx, align 4
   ret void
 }
 
 define void @f5_as1(i64 %x) nounwind {
 ; CHECK: @f5_as1
-  %idx = getelementptr inbounds [8 x i8] addrspace(1)* @.str_as1, i64 0, i64 %x
+  %idx = getelementptr inbounds [8 x i8], [8 x i8] addrspace(1)* @.str_as1, i64 0, i64 %x
   ; CHECK: sub i16
-  ; CHECK icmp ult i16
+  ; CHECK: icmp ult i16
 ; CHECK: trap
-  %1 = load i8 addrspace(1)* %idx, align 4
+  %1 = load i8, i8 addrspace(1)* %idx, align 4
   ret void
 }
 
@@ -77,7 +77,7 @@ define void @f5_as1(i64 %x) nounwind {
 define void @f6(i64 %x) nounwind {
   %1 = alloca i128
 ; CHECK-NOT: trap
-  %2 = load i128* %1, align 4
+  %2 = load i128, i128* %1, align 4
   ret void
 }
 
@@ -86,7 +86,7 @@ define void @f7(i64 %x) nounwind {
   %1 = alloca i128, i64 %x
 ; CHECK: mul i64 16,
 ; CHECK: trap
-  %2 = load i128* %1, align 4
+  %2 = load i128, i128* %1, align 4
   ret void
 }
 
@@ -96,7 +96,7 @@ define void @f8() nounwind {
   %2 = alloca i128
   %3 = select i1 undef, i128* %1, i128* %2
 ; CHECK-NOT: trap
-  %4 = load i128* %3, align 4
+  %4 = load i128, i128* %3, align 4
   ret void
 }
 
@@ -105,7 +105,7 @@ define void @f9(i128* %arg) nounwind {
   %1 = alloca i128
   %2 = select i1 undef, i128* %arg, i128* %1
 ; CHECK-NOT: trap
-  %3 = load i128* %2, align 4
+  %3 = load i128, i128* %2, align 4
   ret void
 }
 
@@ -117,25 +117,25 @@ define void @f10(i64 %x, i64 %y) nounwind {
 ; CHECK: select
 ; CHECK: select
 ; CHECK: trap
-  %4 = load i128* %3, align 4
+  %4 = load i128, i128* %3, align 4
   ret void
 }
 
 ; CHECK: @f11
 define void @f11(i128* byval %x) nounwind {
   %1 = bitcast i128* %x to i8*
-  %2 = getelementptr inbounds i8* %1, i64 16
+  %2 = getelementptr inbounds i8, i8* %1, i64 16
 ; CHECK: br label
-  %3 = load i8* %2, align 4
+  %3 = load i8, i8* %2, align 4
   ret void
 }
 
 ; CHECK: @f11_as1
 define void @f11_as1(i128 addrspace(1)* byval %x) nounwind {
   %1 = bitcast i128 addrspace(1)* %x to i8 addrspace(1)*
-  %2 = getelementptr inbounds i8 addrspace(1)* %1, i16 16
+  %2 = getelementptr inbounds i8, i8 addrspace(1)* %1, i16 16
 ; CHECK: br label
-  %3 = load i8 addrspace(1)* %2, align 4
+  %3 = load i8, i8 addrspace(1)* %2, align 4
   ret void
 }
 
@@ -144,8 +144,8 @@ define i64 @f12(i64 %x, i64 %y) nounwind {
   %1 = tail call i8* @calloc(i64 1, i64 %x)
 ; CHECK: mul i64 %y, 8
   %2 = bitcast i8* %1 to i64*
-  %3 = getelementptr inbounds i64* %2, i64 %y
-  %4 = load i64* %3, align 8
+  %3 = getelementptr inbounds i64, i64* %2, i64 %y
+  %4 = load i64, i64* %3, align 8
   ret i64 %4
 }
 
@@ -157,9 +157,9 @@ entry:
 
 dead:
   ; Self-refential GEPs can occur in dead code.
-  %incdec.ptr = getelementptr inbounds i32* %incdec.ptr, i64 1
-  ; CHECK: %incdec.ptr = getelementptr inbounds i32* %incdec.ptr
-  %l = load i32* %incdec.ptr
+  %incdec.ptr = getelementptr inbounds i32, i32* %incdec.ptr, i64 1
+  ; CHECK: %incdec.ptr = getelementptr inbounds i32, i32* %incdec.ptr
+  %l = load i32, i32* %incdec.ptr
   br label %alive
 
 alive:
diff --git a/test/Instrumentation/DataFlowSanitizer/abilist.ll b/test/Instrumentation/DataFlowSanitizer/abilist.ll
index 9a45dbcbab0f..90103f8b9804 100644
--- a/test/Instrumentation/DataFlowSanitizer/abilist.ll
+++ b/test/Instrumentation/DataFlowSanitizer/abilist.ll
@@ -24,7 +24,7 @@ declare void @custom1(i32 %a, i32 %b)
 ; CHECK: define linkonce_odr { i32, i16 } @"dfsw$custom2"(i32, i32, i16, i16)
 ; CHECK: %[[LABELRETURN2:.*]] = alloca i16
 ; CHECK: %[[RV:.*]] = call i32 @__dfsw_custom2
-; CHECK: %[[RVSHADOW:.*]] = load i16* %[[LABELRETURN2]]
+; CHECK: %[[RVSHADOW:.*]] = load i16, i16* %[[LABELRETURN2]]
 ; CHECK: insertvalue {{.*}}[[RV]], 0
 ; CHECK: insertvalue {{.*}}[[RVSHADOW]], 1
 ; CHECK: ret { i32, i16 }
@@ -56,18 +56,18 @@ define void @f(i32 %x) {
   ; CHECK: call void @__dfsw_customcb({{.*}} @"dfst0$customcb", i8* bitcast ({{.*}} @"dfs$cb" to i8*), i16 0)
   call void @customcb(i32 (i32)* @cb)
 
-  ; CHECK: %[[LABELVA1_0:.*]] = getelementptr inbounds [2 x i16]* %[[LABELVA1]], i32 0, i32 0
+  ; CHECK: %[[LABELVA1_0:.*]] = getelementptr inbounds [2 x i16], [2 x i16]* %[[LABELVA1]], i32 0, i32 0
   ; CHECK: store i16 0, i16* %[[LABELVA1_0]]
-  ; CHECK: %[[LABELVA1_1:.*]] = getelementptr inbounds [2 x i16]* %[[LABELVA1]], i32 0, i32 1
+  ; CHECK: %[[LABELVA1_1:.*]] = getelementptr inbounds [2 x i16], [2 x i16]* %[[LABELVA1]], i32 0, i32 1
   ; CHECK: store i16 %{{.*}}, i16* %[[LABELVA1_1]]
-  ; CHECK: %[[LABELVA1_0A:.*]] = getelementptr inbounds [2 x i16]* %[[LABELVA1]], i32 0, i32 0
-  ; CHECK: call void (i32, i16, i16*, ...)* @__dfsw_custom3(i32 1, i16 0, i16* %[[LABELVA1_0A]], i32 2, i32 %{{.*}})
-  call void (i32, ...)* @custom3(i32 1, i32 2, i32 %x)
-
-  ; CHECK: %[[LABELVA2_0:.*]] = getelementptr inbounds [2 x i16]* %[[LABELVA2]], i32 0, i32 0
-  ; CHECK: %[[LABELVA2_0A:.*]] = getelementptr inbounds [2 x i16]* %[[LABELVA2]], i32 0, i32 0
-  ; CHECK: call i32 (i32, i16, i16*, i16*, ...)* @__dfsw_custom4(i32 1, i16 0, i16* %[[LABELVA2_0A]], i16* %[[LABELRETURN]], i32 2, i32 3)
-  call i32 (i32, ...)* @custom4(i32 1, i32 2, i32 3)
+  ; CHECK: %[[LABELVA1_0A:.*]] = getelementptr inbounds [2 x i16], [2 x i16]* %[[LABELVA1]], i32 0, i32 0
+  ; CHECK: call void (i32, i16, i16*, ...) @__dfsw_custom3(i32 1, i16 0, i16* %[[LABELVA1_0A]], i32 2, i32 %{{.*}})
+  call void (i32, ...) @custom3(i32 1, i32 2, i32 %x)
+
+  ; CHECK: %[[LABELVA2_0:.*]] = getelementptr inbounds [2 x i16], [2 x i16]* %[[LABELVA2]], i32 0, i32 0
+  ; CHECK: %[[LABELVA2_0A:.*]] = getelementptr inbounds [2 x i16], [2 x i16]* %[[LABELVA2]], i32 0, i32 0
+  ; CHECK: call i32 (i32, i16, i16*, i16*, ...) @__dfsw_custom4(i32 1, i16 0, i16* %[[LABELVA2_0A]], i16* %[[LABELRETURN]], i32 2, i32 3)
+  call i32 (i32, ...) @custom4(i32 1, i32 2, i32 3)
 
   ret void
 }
diff --git a/test/Instrumentation/DataFlowSanitizer/debug-nonzero-labels.ll b/test/Instrumentation/DataFlowSanitizer/debug-nonzero-labels.ll
index 16de9ccf0d53..6632eb379270 100644
--- a/test/Instrumentation/DataFlowSanitizer/debug-nonzero-labels.ll
+++ b/test/Instrumentation/DataFlowSanitizer/debug-nonzero-labels.ll
@@ -19,9 +19,9 @@ define i32 @f(i32, i32) {
   ; CHECK: [[CALLCMP:%.*]] = icmp ne i16 [[CALLLABEL]], 0
   ; CHECK: br i1 [[CALLCMP]]
   %call = call i32 @g()
-  ; CHECK: [[LOCALLABEL:%.*]] = load i16* [[LOCALLABELALLOCA]]
+  ; CHECK: [[LOCALLABEL:%.*]] = load i16, i16* [[LOCALLABELALLOCA]]
   ; CHECK: [[LOCALCMP:%.*]] = icmp ne i16 [[LOCALLABEL]], 0
   ; CHECK: br i1 [[LOCALCMP]]
-  %load = load i32* %i
+  %load = load i32, i32* %i
   ret i32 %load
 }
diff --git a/test/Instrumentation/DataFlowSanitizer/debug.ll b/test/Instrumentation/DataFlowSanitizer/debug.ll
index 837e95341f29..c18f5920fa3f 100644
--- a/test/Instrumentation/DataFlowSanitizer/debug.ll
+++ b/test/Instrumentation/DataFlowSanitizer/debug.ll
@@ -1,6 +1,6 @@
 ; RUN: opt < %s -dfsan -dfsan-abilist=%S/Inputs/debuglist.txt -S | FileCheck %s
 
-; CHECK: i32 ()* @main, {{.*}} ; [ DW_TAG_subprogram ] {{.*}} [main]
+; CHECK: !DISubprogram(name: "main",{{.*}} function: i32 ()* @main{{[,)]}}
 
 ; Generated from a simple source file compiled with clang -g:
 ; int main() {
@@ -21,16 +21,16 @@ attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointe
 !llvm.module.flags = !{!9, !10}
 !llvm.ident = !{!11}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/debug.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"debug.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "debug.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00main\00main\00\001\000\001\000\000\00256\000\001", !1, !5, !6, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [main]
-!5 = !{!"0x29", !1}    ; [ DW_TAG_file_type ] [/tmp/dbginfo/debug.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "main", line: 1, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 ()* @main, variables: !2)
+!5 = !DIFile(filename: "debug.cpp", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 4}
-!10 = !{i32 2, !"Debug Info Version", i32 2}
+!10 = !{i32 2, !"Debug Info Version", i32 3}
 !11 = !{!"clang version 3.6.0 "}
-!12 = !MDLocation(line: 2, column: 1, scope: !4)
+!12 = !DILocation(line: 2, column: 1, scope: !4)
diff --git a/test/Instrumentation/DataFlowSanitizer/load.ll b/test/Instrumentation/DataFlowSanitizer/load.ll
index 4d36c0940edf..5bb3984227df 100644
--- a/test/Instrumentation/DataFlowSanitizer/load.ll
+++ b/test/Instrumentation/DataFlowSanitizer/load.ll
@@ -11,21 +11,21 @@ define {} @load0({}* %p) {
   ; NO_COMBINE_PTR_LABEL: @"dfs$load0"
   ; NO_COMBINE_PTR_LABEL: load
   ; NO_COMBINE_PTR_LABEL-NOT: load
-  %a = load {}* %p
+  %a = load {}, {}* %p
   ret {} %a
 }
 
 define i8 @load8(i8* %p) {
   ; COMBINE_PTR_LABEL: @"dfs$load8"
-  ; COMBINE_PTR_LABEL: load i16*
+  ; COMBINE_PTR_LABEL: load i16, i16*
   ; COMBINE_PTR_LABEL: ptrtoint i8* {{.*}} to i64
   ; COMBINE_PTR_LABEL: and i64
   ; COMBINE_PTR_LABEL: mul i64
   ; COMBINE_PTR_LABEL: inttoptr i64
-  ; COMBINE_PTR_LABEL: load i16*
+  ; COMBINE_PTR_LABEL: load i16, i16*
   ; COMBINE_PTR_LABEL: icmp ne i16
   ; COMBINE_PTR_LABEL: call zeroext i16 @__dfsan_union
-  ; COMBINE_PTR_LABEL: load i8*
+  ; COMBINE_PTR_LABEL: load i8, i8*
   ; COMBINE_PTR_LABEL: store i16 {{.*}} @__dfsan_retval_tls
   ; COMBINE_PTR_LABEL: ret i8
 
@@ -34,12 +34,12 @@ define i8 @load8(i8* %p) {
   ; NO_COMBINE_PTR_LABEL: and i64
   ; NO_COMBINE_PTR_LABEL: mul i64
   ; NO_COMBINE_PTR_LABEL: inttoptr i64 {{.*}} to i16*
-  ; NO_COMBINE_PTR_LABEL: load i16*
-  ; NO_COMBINE_PTR_LABEL: load i8*
+  ; NO_COMBINE_PTR_LABEL: load i16, i16*
+  ; NO_COMBINE_PTR_LABEL: load i8, i8*
   ; NO_COMBINE_PTR_LABEL: store i16 {{.*}} @__dfsan_retval_tls
   ; NO_COMBINE_PTR_LABEL: ret i8
 
-  %a = load i8* %p
+  %a = load i8, i8* %p
   ret i8 %a
 }
 
@@ -50,13 +50,13 @@ define i16 @load16(i16* %p) {
   ; COMBINE_PTR_LABEL: mul i64
   ; COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
   ; COMBINE_PTR_LABEL: getelementptr i16
-  ; COMBINE_PTR_LABEL: load i16*
-  ; COMBINE_PTR_LABEL: load i16*
+  ; COMBINE_PTR_LABEL: load i16, i16*
+  ; COMBINE_PTR_LABEL: load i16, i16*
   ; COMBINE_PTR_LABEL: icmp ne
   ; COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union
   ; COMBINE_PTR_LABEL: icmp ne i16
   ; COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union
-  ; COMBINE_PTR_LABEL: load i16*
+  ; COMBINE_PTR_LABEL: load i16, i16*
   ; COMBINE_PTR_LABEL: store {{.*}} @__dfsan_retval_tls
   ; COMBINE_PTR_LABEL: ret i16
 
@@ -65,16 +65,16 @@ define i16 @load16(i16* %p) {
   ; NO_COMBINE_PTR_LABEL: and i64
   ; NO_COMBINE_PTR_LABEL: mul i64
   ; NO_COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
-  ; NO_COMBINE_PTR_LABEL: getelementptr i16*
-  ; NO_COMBINE_PTR_LABEL: load i16*
-  ; NO_COMBINE_PTR_LABEL: load i16*
+  ; NO_COMBINE_PTR_LABEL: getelementptr i16, i16*
+  ; NO_COMBINE_PTR_LABEL: load i16, i16*
+  ; NO_COMBINE_PTR_LABEL: load i16, i16*
   ; NO_COMBINE_PTR_LABEL: icmp ne i16
   ; NO_COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union
-  ; NO_COMBINE_PTR_LABEL: load i16*
+  ; NO_COMBINE_PTR_LABEL: load i16, i16*
   ; NO_COMBINE_PTR_LABEL: store i16 {{.*}} @__dfsan_retval_tls
   ; NO_COMBINE_PTR_LABEL: ret i16
 
-  %a = load i16* %p
+  %a = load i16, i16* %p
   ret i16 %a
 }
 
@@ -85,7 +85,7 @@ define i32 @load32(i32* %p) {
   ; COMBINE_PTR_LABEL: mul i64
   ; COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
   ; COMBINE_PTR_LABEL: bitcast i16* {{.*}} i64*
-  ; COMBINE_PTR_LABEL: load i64*
+  ; COMBINE_PTR_LABEL: load i64, i64*
   ; COMBINE_PTR_LABEL: trunc i64 {{.*}} i16
   ; COMBINE_PTR_LABEL: shl i64
   ; COMBINE_PTR_LABEL: lshr i64
@@ -93,7 +93,7 @@ define i32 @load32(i32* %p) {
   ; COMBINE_PTR_LABEL: icmp eq i64
   ; COMBINE_PTR_LABEL: icmp ne i16
   ; COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union
-  ; COMBINE_PTR_LABEL: load i32*
+  ; COMBINE_PTR_LABEL: load i32, i32*
   ; COMBINE_PTR_LABEL: store i16 {{.*}} @__dfsan_retval_tls
   ; COMBINE_PTR_LABEL: ret i32
   ; COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union_load
@@ -104,19 +104,19 @@ define i32 @load32(i32* %p) {
   ; NO_COMBINE_PTR_LABEL: mul i64
   ; NO_COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
   ; NO_COMBINE_PTR_LABEL: bitcast i16* {{.*}} i64*
-  ; NO_COMBINE_PTR_LABEL: load i64*
+  ; NO_COMBINE_PTR_LABEL: load i64, i64*
   ; NO_COMBINE_PTR_LABEL: trunc i64 {{.*}} i16
   ; NO_COMBINE_PTR_LABEL: shl i64
   ; NO_COMBINE_PTR_LABEL: lshr i64
   ; NO_COMBINE_PTR_LABEL: or i64
   ; NO_COMBINE_PTR_LABEL: icmp eq i64
-  ; NO_COMBINE_PTR_LABEL: load i32*
+  ; NO_COMBINE_PTR_LABEL: load i32, i32*
   ; NO_COMBINE_PTR_LABEL: store i16 {{.*}} @__dfsan_retval_tls
   ; NO_COMBINE_PTR_LABEL: ret i32
   ; NO_COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union_load
   
 
-  %a = load i32* %p
+  %a = load i32, i32* %p
   ret i32 %a
 }
 
@@ -127,7 +127,7 @@ define i64 @load64(i64* %p) {
   ; COMBINE_PTR_LABEL: mul i64
   ; COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
   ; COMBINE_PTR_LABEL: bitcast i16* {{.*}} i64*
-  ; COMBINE_PTR_LABEL: load i64*
+  ; COMBINE_PTR_LABEL: load i64, i64*
   ; COMBINE_PTR_LABEL: trunc i64 {{.*}} i16
   ; COMBINE_PTR_LABEL: shl i64
   ; COMBINE_PTR_LABEL: lshr i64
@@ -135,12 +135,12 @@ define i64 @load64(i64* %p) {
   ; COMBINE_PTR_LABEL: icmp eq i64
   ; COMBINE_PTR_LABEL: icmp ne i16
   ; COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union
-  ; COMBINE_PTR_LABEL: load i64*
+  ; COMBINE_PTR_LABEL: load i64, i64*
   ; COMBINE_PTR_LABEL: store i16 {{.*}} @__dfsan_retval_tls
   ; COMBINE_PTR_LABEL: ret i64
   ; COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union_load
-  ; COMBINE_PTR_LABEL: getelementptr i64* {{.*}} i64
-  ; COMBINE_PTR_LABEL: load i64*
+  ; COMBINE_PTR_LABEL: getelementptr i64, i64* {{.*}} i64
+  ; COMBINE_PTR_LABEL: load i64, i64*
   ; COMBINE_PTR_LABEL: icmp eq i64
 
   ; NO_COMBINE_PTR_LABEL: @"dfs$load64"
@@ -149,20 +149,20 @@ define i64 @load64(i64* %p) {
   ; NO_COMBINE_PTR_LABEL: mul i64
   ; NO_COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
   ; NO_COMBINE_PTR_LABEL: bitcast i16* {{.*}} i64*
-  ; NO_COMBINE_PTR_LABEL: load i64*
+  ; NO_COMBINE_PTR_LABEL: load i64, i64*
   ; NO_COMBINE_PTR_LABEL: trunc i64 {{.*}} i16
   ; NO_COMBINE_PTR_LABEL: shl i64
   ; NO_COMBINE_PTR_LABEL: lshr i64
   ; NO_COMBINE_PTR_LABEL: or i64
   ; NO_COMBINE_PTR_LABEL: icmp eq i64
-  ; NO_COMBINE_PTR_LABEL: load i64*
+  ; NO_COMBINE_PTR_LABEL: load i64, i64*
   ; NO_COMBINE_PTR_LABEL: store i16 {{.*}} @__dfsan_retval_tls
   ; NO_COMBINE_PTR_LABEL: ret i64
   ; NO_COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union_load
-  ; NO_COMBINE_PTR_LABEL: getelementptr i64* {{.*}} i64
-  ; NO_COMBINE_PTR_LABEL: load i64*
+  ; NO_COMBINE_PTR_LABEL: getelementptr i64, i64* {{.*}} i64
+  ; NO_COMBINE_PTR_LABEL: load i64, i64*
   ; NO_COMBINE_PTR_LABEL: icmp eq i64
 
-  %a = load i64* %p
+  %a = load i64, i64* %p
   ret i64 %a
 }
diff --git a/test/Instrumentation/DataFlowSanitizer/store.ll b/test/Instrumentation/DataFlowSanitizer/store.ll
index 365b62d9e107..a66cedf70b10 100644
--- a/test/Instrumentation/DataFlowSanitizer/store.ll
+++ b/test/Instrumentation/DataFlowSanitizer/store.ll
@@ -18,25 +18,25 @@ define void @store0({} %v, {}* %p) {
 
 define void @store8(i8 %v, i8* %p) {
   ; NO_COMBINE_PTR_LABEL: @"dfs$store8"
-  ; NO_COMBINE_PTR_LABEL: load i16* {{.*}} @__dfsan_arg_tls
+  ; NO_COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
   ; NO_COMBINE_PTR_LABEL: ptrtoint i8* {{.*}} i64
   ; NO_COMBINE_PTR_LABEL: and i64
   ; NO_COMBINE_PTR_LABEL: mul i64
   ; NO_COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
-  ; NO_COMBINE_PTR_LABEL: getelementptr i16*
+  ; NO_COMBINE_PTR_LABEL: getelementptr i16, i16*
   ; NO_COMBINE_PTR_LABEL: store i16
   ; NO_COMBINE_PTR_LABEL: store i8
 
   ; COMBINE_PTR_LABEL: @"dfs$store8"
-  ; COMBINE_PTR_LABEL: load i16*
-  ; COMBINE_PTR_LABEL: load i16*
+  ; COMBINE_PTR_LABEL: load i16, i16*
+  ; COMBINE_PTR_LABEL: load i16, i16*
   ; COMBINE_PTR_LABEL: icmp ne i16
   ; COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union
   ; COMBINE_PTR_LABEL: ptrtoint i8* {{.*}} i64
   ; COMBINE_PTR_LABEL: and i64
   ; COMBINE_PTR_LABEL: mul i64
   ; COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
-  ; COMBINE_PTR_LABEL: getelementptr i16*
+  ; COMBINE_PTR_LABEL: getelementptr i16, i16*
   ; COMBINE_PTR_LABEL: store i16
   ; COMBINE_PTR_LABEL: store i8
 
@@ -46,29 +46,29 @@ define void @store8(i8 %v, i8* %p) {
 
 define void @store16(i16 %v, i16* %p) {
   ; NO_COMBINE_PTR_LABEL: @"dfs$store16"
-  ; NO_COMBINE_PTR_LABEL: load i16* {{.*}} @__dfsan_arg_tls
+  ; NO_COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
   ; NO_COMBINE_PTR_LABEL: ptrtoint i16* {{.*}} i64
   ; NO_COMBINE_PTR_LABEL: and i64
   ; NO_COMBINE_PTR_LABEL: mul i64
   ; NO_COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
-  ; NO_COMBINE_PTR_LABEL: getelementptr i16*
+  ; NO_COMBINE_PTR_LABEL: getelementptr i16, i16*
   ; NO_COMBINE_PTR_LABEL: store i16
-  ; NO_COMBINE_PTR_LABEL: getelementptr i16*
+  ; NO_COMBINE_PTR_LABEL: getelementptr i16, i16*
   ; NO_COMBINE_PTR_LABEL: store i16
   ; NO_COMBINE_PTR_LABEL: store i16
 
   ; COMBINE_PTR_LABEL: @"dfs$store16"
-  ; COMBINE_PTR_LABEL: load i16* {{.*}} @__dfsan_arg_tls
-  ; COMBINE_PTR_LABEL: load i16* {{.*}} @__dfsan_arg_tls
+  ; COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
+  ; COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
   ; COMBINE_PTR_LABEL: icmp ne i16
   ; COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union
   ; COMBINE_PTR_LABEL: ptrtoint i16* {{.*}} i64
   ; COMBINE_PTR_LABEL: and i64
   ; COMBINE_PTR_LABEL: mul i64
   ; COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
-  ; COMBINE_PTR_LABEL: getelementptr i16*
+  ; COMBINE_PTR_LABEL: getelementptr i16, i16*
   ; COMBINE_PTR_LABEL: store i16
-  ; COMBINE_PTR_LABEL: getelementptr i16*
+  ; COMBINE_PTR_LABEL: getelementptr i16, i16*
   ; COMBINE_PTR_LABEL: store i16
   ; COMBINE_PTR_LABEL: store i16
 
@@ -78,37 +78,37 @@ define void @store16(i16 %v, i16* %p) {
 
 define void @store32(i32 %v, i32* %p) {
   ; NO_COMBINE_PTR_LABEL: @"dfs$store32"
-  ; NO_COMBINE_PTR_LABEL: load i16* {{.*}} @__dfsan_arg_tls
+  ; NO_COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
   ; NO_COMBINE_PTR_LABEL: ptrtoint i32* {{.*}} i64
   ; NO_COMBINE_PTR_LABEL: and i64
   ; NO_COMBINE_PTR_LABEL: mul i64
   ; NO_COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
-  ; NO_COMBINE_PTR_LABEL: getelementptr i16*
+  ; NO_COMBINE_PTR_LABEL: getelementptr i16, i16*
   ; NO_COMBINE_PTR_LABEL: store i16
-  ; NO_COMBINE_PTR_LABEL: getelementptr i16*
+  ; NO_COMBINE_PTR_LABEL: getelementptr i16, i16*
   ; NO_COMBINE_PTR_LABEL: store i16
-  ; NO_COMBINE_PTR_LABEL: getelementptr i16*
+  ; NO_COMBINE_PTR_LABEL: getelementptr i16, i16*
   ; NO_COMBINE_PTR_LABEL: store i16
-  ; NO_COMBINE_PTR_LABEL: getelementptr i16*
+  ; NO_COMBINE_PTR_LABEL: getelementptr i16, i16*
   ; NO_COMBINE_PTR_LABEL: store i16
   ; NO_COMBINE_PTR_LABEL: store i32
 
   ; COMBINE_PTR_LABEL: @"dfs$store32"
-  ; COMBINE_PTR_LABEL: load i16* {{.*}} @__dfsan_arg_tls
-  ; COMBINE_PTR_LABEL: load i16* {{.*}} @__dfsan_arg_tls
+  ; COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
+  ; COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
   ; COMBINE_PTR_LABEL: icmp ne i16
   ; COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union
   ; COMBINE_PTR_LABEL: ptrtoint i32* {{.*}} i64
   ; COMBINE_PTR_LABEL: and i64
   ; COMBINE_PTR_LABEL: mul i64
   ; COMBINE_PTR_LABEL: inttoptr i64 {{.*}} i16*
-  ; COMBINE_PTR_LABEL: getelementptr i16*
+  ; COMBINE_PTR_LABEL: getelementptr i16, i16*
   ; COMBINE_PTR_LABEL: store i16
-  ; COMBINE_PTR_LABEL: getelementptr i16*
+  ; COMBINE_PTR_LABEL: getelementptr i16, i16*
   ; COMBINE_PTR_LABEL: store i16
-  ; COMBINE_PTR_LABEL: getelementptr i16*
+  ; COMBINE_PTR_LABEL: getelementptr i16, i16*
   ; COMBINE_PTR_LABEL: store i16
-  ; COMBINE_PTR_LABEL: getelementptr i16*
+  ; COMBINE_PTR_LABEL: getelementptr i16, i16*
   ; COMBINE_PTR_LABEL: store i16
   ; COMBINE_PTR_LABEL: store i32
 
@@ -118,7 +118,7 @@ define void @store32(i32 %v, i32* %p) {
 
 define void @store64(i64 %v, i64* %p) {
   ; NO_COMBINE_PTR_LABEL: @"dfs$store64"
-  ; NO_COMBINE_PTR_LABEL: load i16* {{.*}} @__dfsan_arg_tls
+  ; NO_COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
   ; NO_COMBINE_PTR_LABEL: ptrtoint i64* {{.*}} i64
   ; NO_COMBINE_PTR_LABEL: and i64
   ; NO_COMBINE_PTR_LABEL: mul i64
@@ -135,8 +135,8 @@ define void @store64(i64 %v, i64* %p) {
   ; NO_COMBINE_PTR_LABEL: store i64
 
   ; COMBINE_PTR_LABEL: @"dfs$store64"
-  ; COMBINE_PTR_LABEL: load i16* {{.*}} @__dfsan_arg_tls
-  ; COMBINE_PTR_LABEL: load i16* {{.*}} @__dfsan_arg_tls
+  ; COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
+  ; COMBINE_PTR_LABEL: load i16, i16* {{.*}} @__dfsan_arg_tls
   ; COMBINE_PTR_LABEL: icmp ne i16
   ; COMBINE_PTR_LABEL: call {{.*}} @__dfsan_union
   ; COMBINE_PTR_LABEL: ptrtoint i64* {{.*}} i64
diff --git a/test/Instrumentation/InstrProfiling/linkage.ll b/test/Instrumentation/InstrProfiling/linkage.ll
new file mode 100644
index 000000000000..fcca7754fa8f
--- /dev/null
+++ b/test/Instrumentation/InstrProfiling/linkage.ll
@@ -0,0 +1,46 @@
+;; Check that runtime symbols get appropriate linkage.
+
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.10.0 -instrprof -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-unknown-linux -instrprof -S | FileCheck %s
+
+@__llvm_profile_name_foo = hidden constant [3 x i8] c"foo"
+@__llvm_profile_name_foo_weak = weak hidden constant [8 x i8] c"foo_weak"
+@"__llvm_profile_name_linkage.ll:foo_internal" = internal constant [23 x i8] c"linkage.ll:foo_internal"
+@__llvm_profile_name_foo_inline = linkonce_odr hidden constant [10 x i8] c"foo_inline"
+
+; CHECK: @__llvm_profile_counters_foo = hidden global
+; CHECK: @__llvm_profile_data_foo = hidden constant
+define void @foo() {
+  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @__llvm_profile_name_foo, i32 0, i32 0), i64 0, i32 1, i32 0)
+  ret void
+}
+
+; CHECK: @__llvm_profile_counters_foo_weak = weak hidden global
+; CHECK: @__llvm_profile_data_foo_weak = weak hidden constant
+define weak void @foo_weak() {
+  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @__llvm_profile_name_foo_weak, i32 0, i32 0), i64 0, i32 1, i32 0)
+  ret void
+}
+
+; CHECK: @"__llvm_profile_counters_linkage.ll:foo_internal" = internal global
+; CHECK: @"__llvm_profile_data_linkage.ll:foo_internal" = internal constant
+define internal void @foo_internal() {
+  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([23 x i8], [23 x i8]* @"__llvm_profile_name_linkage.ll:foo_internal", i32 0, i32 0), i64 0, i32 1, i32 0)
+  ret void
+}
+
+; CHECK: @__llvm_profile_counters_foo_inline = linkonce_odr hidden global
+; CHECK: @__llvm_profile_data_foo_inline = linkonce_odr hidden constant
+define linkonce_odr void @foo_inline() {
+  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @__llvm_profile_name_foo_inline, i32 0, i32 0), i64 0, i32 1, i32 0)
+  ret void
+}
+
+declare void @llvm.instrprof.increment(i8*, i64, i32, i32)
+
+; CHECK: @__llvm_profile_runtime = external global i32
+
+; CHECK: define linkonce_odr hidden i32 @__llvm_profile_runtime_user() {{.*}} {
+; CHECK:   %[[REG:.*]] = load i32, i32* @__llvm_profile_runtime
+; CHECK:   ret i32 %[[REG]]
+; CHECK: }
diff --git a/test/Instrumentation/InstrProfiling/noruntime.ll b/test/Instrumentation/InstrProfiling/noruntime.ll
index e69445dc3503..f0619c8686ff 100644
--- a/test/Instrumentation/InstrProfiling/noruntime.ll
+++ b/test/Instrumentation/InstrProfiling/noruntime.ll
@@ -2,14 +2,14 @@
 
 ; RUN: opt < %s -instrprof -S | FileCheck %s
 ; CHECK-NOT: define {{.*}} @__llvm_profile_runtime_user()
-; CHECK-NOT: load i32* @__llvm_profile_runtime
+; CHECK-NOT: load i32, i32* @__llvm_profile_runtime
 
 @__llvm_profile_runtime = global i32 0, align 4
 
 @__llvm_profile_name_foo = hidden constant [3 x i8] c"foo"
 
 define void @foo() {
-  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([3 x i8]* @__llvm_profile_name_foo, i32 0, i32 0), i64 0, i32 1, i32 0)
+  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @__llvm_profile_name_foo, i32 0, i32 0), i64 0, i32 1, i32 0)
   ret void
 }
 
diff --git a/test/Instrumentation/InstrProfiling/platform.ll b/test/Instrumentation/InstrProfiling/platform.ll
index e0327683b7f4..5f16cba91d91 100644
--- a/test/Instrumentation/InstrProfiling/platform.ll
+++ b/test/Instrumentation/InstrProfiling/platform.ll
@@ -13,7 +13,7 @@
 ; MACHO: @__llvm_profile_data_foo = hidden constant {{.*}}, section "__DATA,__llvm_prf_data", align 8
 ; ELF: @__llvm_profile_data_foo = hidden constant {{.*}}, section "__llvm_prf_data", align 8
 define void @foo() {
-  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([3 x i8]* @__llvm_profile_name_foo, i32 0, i32 0), i64 0, i32 1, i32 0)
+  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @__llvm_profile_name_foo, i32 0, i32 0), i64 0, i32 1, i32 0)
   ret void
 }
 
diff --git a/test/Instrumentation/InstrProfiling/profiling.ll b/test/Instrumentation/InstrProfiling/profiling.ll
index 246bf6b43f93..52a6eadbff09 100644
--- a/test/Instrumentation/InstrProfiling/profiling.ll
+++ b/test/Instrumentation/InstrProfiling/profiling.ll
@@ -12,23 +12,23 @@ target triple = "x86_64-apple-macosx10.10.0"
 ; CHECK: @__llvm_profile_counters_foo = hidden global [1 x i64] zeroinitializer, section "__DATA,__llvm_prf_cnts", align 8
 ; CHECK: @__llvm_profile_data_foo = hidden constant {{.*}}, section "__DATA,__llvm_prf_data", align 8
 define void @foo() {
-  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([3 x i8]* @__llvm_profile_name_foo, i32 0, i32 0), i64 0, i32 1, i32 0)
+  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @__llvm_profile_name_foo, i32 0, i32 0), i64 0, i32 1, i32 0)
   ret void
 }
 
 ; CHECK: @__llvm_profile_counters_bar = hidden global [1 x i64] zeroinitializer, section "__DATA,__llvm_prf_cnts", align 8
 ; CHECK: @__llvm_profile_data_bar = hidden constant {{.*}}, section "__DATA,__llvm_prf_data", align 8
 define void @bar() {
-  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([4 x i8]* @__llvm_profile_name_bar, i32 0, i32 0), i64 0, i32 1, i32 0)
+  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @__llvm_profile_name_bar, i32 0, i32 0), i64 0, i32 1, i32 0)
   ret void
 }
 
 ; CHECK: @__llvm_profile_counters_baz = hidden global [3 x i64] zeroinitializer, section "__DATA,__llvm_prf_cnts", align 8
 ; CHECK: @__llvm_profile_data_baz = hidden constant {{.*}}, section "__DATA,__llvm_prf_data", align 8
 define void @baz() {
-  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([3 x i8]* @baz_prof_name, i32 0, i32 0), i64 0, i32 3, i32 0)
-  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([3 x i8]* @baz_prof_name, i32 0, i32 0), i64 0, i32 3, i32 1)
-  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([3 x i8]* @baz_prof_name, i32 0, i32 0), i64 0, i32 3, i32 2)
+  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @baz_prof_name, i32 0, i32 0), i64 0, i32 3, i32 0)
+  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @baz_prof_name, i32 0, i32 0), i64 0, i32 3, i32 1)
+  call void @llvm.instrprof.increment(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @baz_prof_name, i32 0, i32 0), i64 0, i32 3, i32 2)
   ret void
 }
 
diff --git a/test/Instrumentation/MemorySanitizer/array_types.ll b/test/Instrumentation/MemorySanitizer/array_types.ll
index fa3835fac77a..e96716aaa97f 100644
--- a/test/Instrumentation/MemorySanitizer/array_types.ll
+++ b/test/Instrumentation/MemorySanitizer/array_types.ll
@@ -12,8 +12,8 @@ entry:
 }
 
 ; CHECK-LABEL: @InsertValue(
-; CHECK-DAG: [[Sy:%.*]] = load i32* {{.*}}@__msan_param_tls to i64), i64 8) to i32*)
-; CHECK-DAG: [[Sx:%.*]] = load i32* {{.*}}@__msan_param_tls to i32*)
+; CHECK-DAG: [[Sy:%.*]] = load i32, i32* {{.*}}@__msan_param_tls to i64), i64 8) to i32*)
+; CHECK-DAG: [[Sx:%.*]] = load i32, i32* {{.*}}@__msan_param_tls to i32*)
 ; CHECK: [[A:%.*]] = insertvalue [2 x i32] [i32 -1, i32 -1], i32 [[Sx]], 0
 ; CHECK: [[B:%.*]] = insertvalue [2 x i32] [[A]], i32 [[Sy]], 1
 ; CHECK: store [2 x i32] [[B]], [2 x i32]* {{.*}}@__msan_retval_tls
@@ -28,8 +28,8 @@ entry:
 }
 
 ; CHECK-LABEL: @InsertValueDouble(
-; CHECK-DAG: [[Sy:%.*]] = load i64* {{.*}}@__msan_param_tls to i64), i64 8) to i64*)
-; CHECK-DAG: [[Sx:%.*]] = load i64* getelementptr {{.*}}@__msan_param_tls, i32 0, i32 0
+; CHECK-DAG: [[Sy:%.*]] = load i64, i64* {{.*}}@__msan_param_tls to i64), i64 8) to i64*)
+; CHECK-DAG: [[Sx:%.*]] = load i64, i64* getelementptr {{.*}}@__msan_param_tls, i32 0, i32 0
 ; CHECK: [[A:%.*]] = insertvalue [2 x i64] [i64 -1, i64 -1], i64 [[Sx]], 0
 ; CHECK: [[B:%.*]] = insertvalue [2 x i64] [[A]], i64 [[Sy]], 1
 ; CHECK: store [2 x i64] [[B]], [2 x i64]* {{.*}}@__msan_retval_tls
@@ -43,7 +43,7 @@ entry:
 }
 
 ; CHECK-LABEL: @ExtractValue(
-; CHECK: [[Sa:%.*]] = load [2 x i32]* {{.*}}@__msan_param_tls to [2 x i32]*)
+; CHECK: [[Sa:%.*]] = load [2 x i32], [2 x i32]* {{.*}}@__msan_param_tls to [2 x i32]*)
 ; CHECK: [[Sx:%.*]] = extractvalue [2 x i32] [[Sa]], 1
 ; CHECK: store i32 [[Sx]], i32* {{.*}}@__msan_retval_tls
 ; CHECK: ret i32
@@ -59,7 +59,7 @@ define i32 @ArrayInStruct(%MyStruct %s) sanitize_memory {
 }
 
 ; CHECK-LABEL: @ArrayInStruct(
-; CHECK: [[Ss:%.*]] = load { i32, i32, [3 x i32] }* {{.*}}@__msan_param_tls to { i32, i32, [3 x i32] }*)
+; CHECK: [[Ss:%.*]] = load { i32, i32, [3 x i32] }, { i32, i32, [3 x i32] }* {{.*}}@__msan_param_tls to { i32, i32, [3 x i32] }*)
 ; CHECK: [[Sx:%.*]] = extractvalue { i32, i32, [3 x i32] } [[Ss]], 2, 1
 ; CHECK: store i32 [[Sx]], i32* {{.*}}@__msan_retval_tls
 ; CHECK: ret i32
@@ -71,7 +71,7 @@ define i32 @ArrayOfStructs([3 x { i32, i32 }] %a) sanitize_memory {
 }
 
 ; CHECK-LABEL: @ArrayOfStructs(
-; CHECK: [[Ss:%.*]] = load [3 x { i32, i32 }]* {{.*}}@__msan_param_tls to [3 x { i32, i32 }]*)
+; CHECK: [[Ss:%.*]] = load [3 x { i32, i32 }], [3 x { i32, i32 }]* {{.*}}@__msan_param_tls to [3 x { i32, i32 }]*)
 ; CHECK: [[Sx:%.*]] = extractvalue [3 x { i32, i32 }] [[Ss]], 2, 1
 ; CHECK: store i32 [[Sx]], i32* {{.*}}@__msan_retval_tls
 ; CHECK: ret i32
@@ -83,7 +83,7 @@ define <8 x i16> @ArrayOfVectors([3 x <8 x i16>] %a) sanitize_memory {
 }
 
 ; CHECK-LABEL: @ArrayOfVectors(
-; CHECK: [[Ss:%.*]] = load [3 x <8 x i16>]* {{.*}}@__msan_param_tls to [3 x <8 x i16>]*)
+; CHECK: [[Ss:%.*]] = load [3 x <8 x i16>], [3 x <8 x i16>]* {{.*}}@__msan_param_tls to [3 x <8 x i16>]*)
 ; CHECK: [[Sx:%.*]] = extractvalue [3 x <8 x i16>] [[Ss]], 1
 ; CHECK: store <8 x i16> [[Sx]], <8 x i16>* {{.*}}@__msan_retval_tls
 ; CHECK: ret <8 x i16>
diff --git a/test/Instrumentation/MemorySanitizer/atomics.ll b/test/Instrumentation/MemorySanitizer/atomics.ll
index 28736ad79029..e896eaebdd3d 100644
--- a/test/Instrumentation/MemorySanitizer/atomics.ll
+++ b/test/Instrumentation/MemorySanitizer/atomics.ll
@@ -77,13 +77,13 @@ entry:
 
 define i32 @AtomicLoad(i32* %p) sanitize_memory {
 entry:
-  %0 = load atomic i32* %p seq_cst, align 16
+  %0 = load atomic i32, i32* %p seq_cst, align 16
   ret i32 %0
 }
 
 ; CHECK: @AtomicLoad
-; CHECK: load atomic i32* {{.*}} seq_cst, align 16
-; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32* {{.*}}, align 16
+; CHECK: load atomic i32, i32* {{.*}} seq_cst, align 16
+; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16
 ; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
 ; CHECK: ret i32
 
@@ -92,13 +92,13 @@ entry:
 
 define i32 @AtomicLoadAcquire(i32* %p) sanitize_memory {
 entry:
-  %0 = load atomic i32* %p acquire, align 16
+  %0 = load atomic i32, i32* %p acquire, align 16
   ret i32 %0
 }
 
 ; CHECK: @AtomicLoadAcquire
-; CHECK: load atomic i32* {{.*}} acquire, align 16
-; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32* {{.*}}, align 16
+; CHECK: load atomic i32, i32* {{.*}} acquire, align 16
+; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16
 ; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
 ; CHECK: ret i32
 
@@ -107,13 +107,13 @@ entry:
 
 define i32 @AtomicLoadMonotonic(i32* %p) sanitize_memory {
 entry:
-  %0 = load atomic i32* %p monotonic, align 16
+  %0 = load atomic i32, i32* %p monotonic, align 16
   ret i32 %0
 }
 
 ; CHECK: @AtomicLoadMonotonic
-; CHECK: load atomic i32* {{.*}} acquire, align 16
-; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32* {{.*}}, align 16
+; CHECK: load atomic i32, i32* {{.*}} acquire, align 16
+; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16
 ; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
 ; CHECK: ret i32
 
@@ -122,13 +122,13 @@ entry:
 
 define i32 @AtomicLoadUnordered(i32* %p) sanitize_memory {
 entry:
-  %0 = load atomic i32* %p unordered, align 16
+  %0 = load atomic i32, i32* %p unordered, align 16
   ret i32 %0
 }
 
 ; CHECK: @AtomicLoadUnordered
-; CHECK: load atomic i32* {{.*}} acquire, align 16
-; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32* {{.*}}, align 16
+; CHECK: load atomic i32, i32* {{.*}} acquire, align 16
+; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16
 ; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
 ; CHECK: ret i32
 
diff --git a/test/Instrumentation/MemorySanitizer/check-constant-shadow.ll b/test/Instrumentation/MemorySanitizer/check-constant-shadow.ll
index 11e44106d8fb..f1479440faf6 100644
--- a/test/Instrumentation/MemorySanitizer/check-constant-shadow.ll
+++ b/test/Instrumentation/MemorySanitizer/check-constant-shadow.ll
@@ -1,10 +1,11 @@
-; RUN: opt < %s -msan -msan-check-constant-shadow=1 -S | FileCheck %s
+; RUN: opt < %s -msan -msan-check-access-address=0 -msan-check-constant-shadow=1 -msan-track-origins=1 -S | FileCheck %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 ; Test that returning a literal undef from main() triggers an MSan warning.
 
+; main() is special: it inserts check for the return value
 define i32 @main() nounwind uwtable sanitize_memory {
 entry:
   ret i32 undef
@@ -13,3 +14,40 @@ entry:
 ; CHECK-LABEL: @main
 ; CHECK: call void @__msan_warning_noreturn
 ; CHECK: ret i32 undef
+
+
+; This function stores known initialized value.
+; Expect 2 stores: one for the shadow (0), one for the value (42), but no origin.
+define void @StoreConstant(i32* nocapture %p) nounwind uwtable sanitize_memory {
+entry:
+  store i32 42, i32* %p, align 4
+  ret void
+}
+
+; CHECK-LABEL: @StoreConstant
+; CHECK-NOT: store i32
+; CHECK: store i32 0,
+; CHECK-NOT: store i32
+; CHECK: store i32 42,
+; CHECK-NOT: store i32
+; CHECK: ret void
+
+
+; This function stores known uninitialized value.
+; Expect 3 stores: shadow, value and origin.
+; Expect no icmp(s): everything here is unconditional.
+define void @StoreUndef(i32* nocapture %p) nounwind uwtable sanitize_memory {
+entry:
+  store i32 undef, i32* %p, align 4
+  ret void
+}
+
+; CHECK-LABEL: @StoreUndef
+; CHECK-NOT: icmp
+; CHECK: store i32
+; CHECK-NOT: icmp
+; CHECK: store i32
+; CHECK-NOT: icmp
+; CHECK: store i32
+; CHECK-NOT: icmp
+; CHECK: ret void
diff --git a/test/Instrumentation/MemorySanitizer/check_access_address.ll b/test/Instrumentation/MemorySanitizer/check_access_address.ll
index 566022600ea4..5e1a3f4442f2 100644
--- a/test/Instrumentation/MemorySanitizer/check_access_address.ll
+++ b/test/Instrumentation/MemorySanitizer/check_access_address.ll
@@ -8,7 +8,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define <2 x i64> @ByValArgumentShadowLargeAlignment(<2 x i64>* byval %p) sanitize_memory {
 entry:
-  %x = load <2 x i64>* %p
+  %x = load <2 x i64>, <2 x i64>* %p
   ret <2 x i64> %x
 }
 
@@ -19,7 +19,7 @@ entry:
 
 define i16 @ByValArgumentShadowSmallAlignment(i16* byval %p) sanitize_memory {
 entry:
-  %x = load i16* %p
+  %x = load i16, i16* %p
   ret i16 %x
 }
 
diff --git a/test/Instrumentation/MemorySanitizer/instrumentation-with-call-threshold.ll b/test/Instrumentation/MemorySanitizer/instrumentation-with-call-threshold.ll
index beb3c5fad735..855125a88de8 100644
--- a/test/Instrumentation/MemorySanitizer/instrumentation-with-call-threshold.ll
+++ b/test/Instrumentation/MemorySanitizer/instrumentation-with-call-threshold.ll
@@ -11,12 +11,12 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define void @LoadAndCmp(i32* nocapture %a) nounwind uwtable sanitize_memory {
 entry:
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry
-  tail call void (...)* @foo() nounwind
+  tail call void (...) @foo() nounwind
   br label %if.end
 
 if.end:                                           ; preds = %entry, %if.then
diff --git a/test/Instrumentation/MemorySanitizer/missing_origin.ll b/test/Instrumentation/MemorySanitizer/missing_origin.ll
index f7385b9dd4ce..08289ab67c66 100644
--- a/test/Instrumentation/MemorySanitizer/missing_origin.ll
+++ b/test/Instrumentation/MemorySanitizer/missing_origin.ll
@@ -14,7 +14,7 @@ entry:
 }
 
 ; CHECK-LABEL: @Shuffle(
-; CHECK: [[A:%.*]] = load i32* {{.*}}@__msan_param_origin_tls,
+; CHECK: [[A:%.*]] = load i32, i32* {{.*}}@__msan_param_origin_tls,
 ; CHECK: store i32 [[A]], i32* @__msan_retval_origin_tls
 ; CHECK: ret <4 x i32>
 
diff --git a/test/Instrumentation/MemorySanitizer/msan_basic.ll b/test/Instrumentation/MemorySanitizer/msan_basic.ll
index 0faf45d70c59..8b8e29709599 100644
--- a/test/Instrumentation/MemorySanitizer/msan_basic.ll
+++ b/test/Instrumentation/MemorySanitizer/msan_basic.ll
@@ -4,8 +4,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
-; Check the presence of __msan_init
-; CHECK: @llvm.global_ctors {{.*}} @__msan_init
+; CHECK: @llvm.global_ctors {{.*}} @msan.module_ctor
 
 ; Check the presence and the linkage type of __msan_track_origins and
 ; other interface symbols.
@@ -70,12 +69,12 @@ entry:
 ; load followed by cmp: check that we load the shadow and call __msan_warning.
 define void @LoadAndCmp(i32* nocapture %a) nounwind uwtable sanitize_memory {
 entry:
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry
-  tail call void (...)* @foo() nounwind
+  tail call void (...) @foo() nounwind
   br label %if.end
 
 if.end:                                           ; preds = %entry, %if.then
@@ -124,11 +123,11 @@ entry:
   br i1 %tobool, label %if.else, label %if.then
 
   if.then:                                          ; preds = %entry
-  %0 = load i32* %b, align 4
+  %0 = load i32, i32* %b, align 4
   br label %if.end
 
   if.else:                                          ; preds = %entry
-  %1 = load i32* %c, align 4
+  %1 = load i32, i32* %c, align 4
   br label %if.end
 
   if.end:                                           ; preds = %if.else, %if.then
@@ -147,7 +146,7 @@ entry:
 ; Compute shadow for "x << 10"
 define void @ShlConst(i32* nocapture %x) nounwind uwtable sanitize_memory {
 entry:
-  %0 = load i32* %x, align 4
+  %0 = load i32, i32* %x, align 4
   %1 = shl i32 %0, 10
   store i32 %1, i32* %x, align 4
   ret void
@@ -165,7 +164,7 @@ entry:
 ; Compute shadow for "10 << x": it should have 'sext i1'.
 define void @ShlNonConst(i32* nocapture %x) nounwind uwtable sanitize_memory {
 entry:
-  %0 = load i32* %x, align 4
+  %0 = load i32, i32* %x, align 4
   %1 = shl i32 10, %0
   store i32 %1, i32* %x, align 4
   ret void
@@ -182,7 +181,7 @@ entry:
 ; SExt
 define void @SExt(i32* nocapture %a, i16* nocapture %b) nounwind uwtable sanitize_memory {
 entry:
-  %0 = load i16* %b, align 2
+  %0 = load i16, i16* %b, align 2
   %1 = sext i16 %0 to i32
   store i32 %1, i32* %a, align 4
   ret void
@@ -345,8 +344,8 @@ entry:
 }
 
 ; CHECK: @IntToPtr
-; CHECK: load i64*{{.*}}__msan_param_tls
-; CHECK-ORIGINS-NEXT: load i32*{{.*}}__msan_param_origin_tls
+; CHECK: load i64, i64*{{.*}}__msan_param_tls
+; CHECK-ORIGINS-NEXT: load i32, i32*{{.*}}__msan_param_origin_tls
 ; CHECK-NEXT: inttoptr
 ; CHECK-NEXT: store i64{{.*}}__msan_retval_tls
 ; CHECK: ret i8*
@@ -359,7 +358,7 @@ entry:
 }
 
 ; CHECK: @IntToPtr_ZExt
-; CHECK: load i16*{{.*}}__msan_param_tls
+; CHECK: load i16, i16*{{.*}}__msan_param_tls
 ; CHECK: zext
 ; CHECK-NEXT: inttoptr
 ; CHECK-NEXT: store i64{{.*}}__msan_retval_tls
@@ -475,25 +474,25 @@ entry:
 
 define i32 @ShadowLoadAlignmentLarge() nounwind uwtable sanitize_memory {
   %y = alloca i32, align 64
-  %1 = load volatile i32* %y, align 64
+  %1 = load volatile i32, i32* %y, align 64
   ret i32 %1
 }
 
 ; CHECK: @ShadowLoadAlignmentLarge
-; CHECK: load volatile i32* {{.*}} align 64
-; CHECK: load i32* {{.*}} align 64
+; CHECK: load volatile i32, i32* {{.*}} align 64
+; CHECK: load i32, i32* {{.*}} align 64
 ; CHECK: ret i32
 
 define i32 @ShadowLoadAlignmentSmall() nounwind uwtable sanitize_memory {
   %y = alloca i32, align 2
-  %1 = load volatile i32* %y, align 2
+  %1 = load volatile i32, i32* %y, align 2
   ret i32 %1
 }
 
 ; CHECK: @ShadowLoadAlignmentSmall
-; CHECK: load volatile i32* {{.*}} align 2
-; CHECK: load i32* {{.*}} align 2
-; CHECK-ORIGINS: load i32* {{.*}} align 4
+; CHECK: load volatile i32, i32* {{.*}} align 2
+; CHECK: load i32, i32* {{.*}} align 2
+; CHECK-ORIGINS: load i32, i32* {{.*}} align 4
 ; CHECK: ret i32
 
 
@@ -580,8 +579,8 @@ define <16 x i8> @LoadIntrinsic(i8* %p) nounwind uwtable sanitize_memory {
 declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p) nounwind
 
 ; CHECK: @LoadIntrinsic
-; CHECK: load <16 x i8>* {{.*}} align 1
-; CHECK-ORIGINS: [[ORIGIN:%[01-9a-z]+]] = load i32* {{.*}}
+; CHECK: load <16 x i8>, <16 x i8>* {{.*}} align 1
+; CHECK-ORIGINS: [[ORIGIN:%[01-9a-z]+]] = load i32, i32* {{.*}}
 ; CHECK-NOT: br
 ; CHECK-NOT: = or
 ; CHECK: call <16 x i8> @llvm.x86.sse3.ldu.dq
@@ -602,10 +601,10 @@ define <8 x i16> @Paddsw128(<8 x i16> %a, <8 x i16> %b) nounwind uwtable sanitiz
 declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a, <8 x i16> %b) nounwind
 
 ; CHECK: @Paddsw128
-; CHECK-NEXT: load <8 x i16>* {{.*}} @__msan_param_tls
-; CHECK-ORIGINS: load i32* {{.*}} @__msan_param_origin_tls
-; CHECK-NEXT: load <8 x i16>* {{.*}} @__msan_param_tls
-; CHECK-ORIGINS: load i32* {{.*}} @__msan_param_origin_tls
+; CHECK-NEXT: load <8 x i16>, <8 x i16>* {{.*}} @__msan_param_tls
+; CHECK-ORIGINS: load i32, i32* {{.*}} @__msan_param_origin_tls
+; CHECK-NEXT: load <8 x i16>, <8 x i16>* {{.*}} @__msan_param_tls
+; CHECK-ORIGINS: load i32, i32* {{.*}} @__msan_param_origin_tls
 ; CHECK-NEXT: = or <8 x i16>
 ; CHECK-ORIGINS: = bitcast <8 x i16> {{.*}} to i128
 ; CHECK-ORIGINS-NEXT: = icmp ne i128 {{.*}}, 0
@@ -620,13 +619,13 @@ declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a, <8 x i16> %b) nounwind
 ; Check that shadow of such vector is a vector of integers.
 
 define <8 x i8*> @VectorOfPointers(<8 x i8*>* %p) nounwind uwtable sanitize_memory {
-  %x = load <8 x i8*>* %p
+  %x = load <8 x i8*>, <8 x i8*>* %p
   ret <8 x i8*> %x
 }
 
 ; CHECK: @VectorOfPointers
-; CHECK: load <8 x i8*>*
-; CHECK: load <8 x i64>*
+; CHECK: load <8 x i8*>, <8 x i8*>*
+; CHECK: load <8 x i64>, <8 x i64>*
 ; CHECK: store <8 x i64> {{.*}} @__msan_retval_tls
 ; CHECK: ret <8 x i8*>
 
@@ -656,7 +655,7 @@ entry:
   %x.addr = alloca i32, align 4
   %va = alloca [1 x %struct.__va_list_tag], align 16
   store i32 %x, i32* %x.addr, align 4
-  %arraydecay = getelementptr inbounds [1 x %struct.__va_list_tag]* %va, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %va, i32 0, i32 0
   %arraydecay1 = bitcast %struct.__va_list_tag* %arraydecay to i8*
   call void @llvm.va_start(i8* %arraydecay1)
   ret void
@@ -772,7 +771,7 @@ cond.end:                                         ; preds = %cond.false, %cond.t
 
 define i32 @NoSanitizeMemoryParamTLS(i32* nocapture readonly %x) {
 entry:
-  %0 = load i32* %x, align 4
+  %0 = load i32, i32* %x, align 4
   %call = tail call i32 @NoSanitizeMemoryParamTLSHelper(i32 %0)
   ret i32 %call
 }
@@ -792,7 +791,7 @@ entry:
 }
 
 ; CHECK: @ArgumentShadowAlignment
-; CHECK: load <2 x i64>* {{.*}} @__msan_param_tls {{.*}}, align 8
+; CHECK: load <2 x i64>, <2 x i64>* {{.*}} @__msan_param_tls {{.*}}, align 8
 ; CHECK: store <2 x i64> {{.*}} @__msan_retval_tls {{.*}}, align 8
 ; CHECK: ret <2 x i64>
 
@@ -835,13 +834,13 @@ entry:
   %agg.tmp2 = alloca %struct.StructByVal, align 8
   %0 = bitcast %struct.StructByVal* %s to i8*
   %agg.tmp.sroa.0.0..sroa_cast = bitcast %struct.StructByVal* %s to i64*
-  %agg.tmp.sroa.0.0.copyload = load i64* %agg.tmp.sroa.0.0..sroa_cast, align 4
-  %agg.tmp.sroa.2.0..sroa_idx = getelementptr inbounds %struct.StructByVal* %s, i64 0, i32 2
+  %agg.tmp.sroa.0.0.copyload = load i64, i64* %agg.tmp.sroa.0.0..sroa_cast, align 4
+  %agg.tmp.sroa.2.0..sroa_idx = getelementptr inbounds %struct.StructByVal, %struct.StructByVal* %s, i64 0, i32 2
   %agg.tmp.sroa.2.0..sroa_cast = bitcast i32* %agg.tmp.sroa.2.0..sroa_idx to i64*
-  %agg.tmp.sroa.2.0.copyload = load i64* %agg.tmp.sroa.2.0..sroa_cast, align 4
+  %agg.tmp.sroa.2.0.copyload = load i64, i64* %agg.tmp.sroa.2.0..sroa_cast, align 4
   %1 = bitcast %struct.StructByVal* %agg.tmp2 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %0, i64 16, i32 4, i1 false)
-  call void (i32, ...)* @VAArgStructFn(i32 undef, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, %struct.StructByVal* byval align 8 %agg.tmp2)
+  call void (i32, ...) @VAArgStructFn(i32 undef, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, %struct.StructByVal* byval align 8 %agg.tmp2)
   ret void
 }
 
@@ -862,7 +861,7 @@ entry:
 ; CHECK: bitcast { i32, i32, i32, i32 }* {{.*}}@__msan_va_arg_tls {{.*}}, i64 176
 ; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64
 ; CHECK: store i64 16, i64* @__msan_va_arg_overflow_size_tls
-; CHECK: call void (i32, ...)* @VAArgStructFn
+; CHECK: call void (i32, ...) @VAArgStructFn
 ; CHECK: ret void
 
 declare i32 @InnerTailCall(i32 %a)
@@ -878,3 +877,6 @@ define void @MismatchedReturnTypeTailCall(i32 %a) sanitize_memory {
 ; CHECK-LABEL: define void @MismatchedReturnTypeTailCall
 ; CHECK: tail call i32 @InnerTailCall
 ; CHECK: ret void
+
+; CHECK-LABEL: define internal void @msan.module_ctor
+; CHECK: call void @__msan_init()
diff --git a/test/Instrumentation/MemorySanitizer/store-long-origin.ll b/test/Instrumentation/MemorySanitizer/store-long-origin.ll
new file mode 100644
index 000000000000..23ba4a18e6bc
--- /dev/null
+++ b/test/Instrumentation/MemorySanitizer/store-long-origin.ll
@@ -0,0 +1,89 @@
+; RUN: opt < %s -msan -msan-check-access-address=0 -msan-track-origins=1 -S | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+
+; Test origin for longer stores.
+
+define void @Store8(i64* nocapture %p, i64 %x) sanitize_memory {
+entry:
+  store i64 %x, i64* %p, align 8
+  ret void
+}
+
+; Single 8-byte origin store
+; CHECK-LABEL: define void @Store8(
+; CHECK: store i64 {{.*}}, align 8
+; CHECK: store i64 {{.*}}, align 8
+; CHECK: store i64 {{.*}}, align 8
+; CHECK: ret void
+
+define void @Store8_align4(i64* nocapture %p, i64 %x) sanitize_memory {
+entry:
+  store i64 %x, i64* %p, align 4
+  ret void
+}
+
+; Two 4-byte origin stores
+; CHECK-LABEL: define void @Store8_align4(
+; CHECK: store i64 {{.*}}, align 4
+; CHECK: store i32 {{.*}}, align 4
+; CHECK: getelementptr i32, i32* {{.*}}, i32 1
+; CHECK: store i32 {{.*}}, align 4
+; CHECK: store i64 {{.*}}, align 4
+; CHECK: ret void
+
+%struct.S = type { i32, i32, i32 }
+
+define void @StoreAgg(%struct.S* nocapture %p, %struct.S %x) sanitize_memory {
+entry:
+  store %struct.S %x, %struct.S* %p, align 4
+  ret void
+}
+
+; Three 4-byte origin stores
+; CHECK-LABEL: define void @StoreAgg(
+; CHECK: store { i32, i32, i32 }  {{.*}}, align 4
+; CHECK: store i32 {{.*}}, align 4
+; CHECK: getelementptr i32, i32* {{.*}}, i32 1
+; CHECK: store i32 {{.*}}, align 4
+; CHECK: getelementptr i32, i32* {{.*}}, i32 2
+; CHECK: store i32 {{.*}}, align 4
+; CHECK: store %struct.S {{.*}}, align 4
+; CHECK: ret void
+
+
+define void @StoreAgg8(%struct.S* nocapture %p, %struct.S %x) sanitize_memory {
+entry:
+  store %struct.S %x, %struct.S* %p, align 8
+  ret void
+}
+
+; 8-byte + 4-byte origin stores
+; CHECK-LABEL: define void @StoreAgg8(
+; CHECK: store { i32, i32, i32 }  {{.*}}, align 8
+; CHECK: store i64 {{.*}}, align 8
+; CHECK: getelementptr i32, i32* {{.*}}, i32 2
+; CHECK: store i32 {{.*}}, align 8
+; CHECK: store %struct.S {{.*}}, align 8
+; CHECK: ret void
+
+
+%struct.Q = type { i64, i64, i64 }
+define void @StoreAgg24(%struct.Q* nocapture %p, %struct.Q %x) sanitize_memory {
+entry:
+  store %struct.Q %x, %struct.Q* %p, align 8
+  ret void
+}
+
+; 3 8-byte origin stores
+; CHECK-LABEL: define void @StoreAgg24(
+; CHECK: store { i64, i64, i64 }  {{.*}}, align 8
+; CHECK: store i64 {{.*}}, align 8
+; CHECK: getelementptr i64, i64* {{.*}}, i32 1
+; CHECK: store i64 {{.*}}, align 8
+; CHECK: getelementptr i64, i64* {{.*}}, i32 2
+; CHECK: store i64 {{.*}}, align 8
+; CHECK: store %struct.Q {{.*}}, align 8
+; CHECK: ret void
diff --git a/test/Instrumentation/MemorySanitizer/store-origin.ll b/test/Instrumentation/MemorySanitizer/store-origin.ll
index c2948b1dbc50..cdfe280bc8cb 100644
--- a/test/Instrumentation/MemorySanitizer/store-origin.ll
+++ b/test/Instrumentation/MemorySanitizer/store-origin.ll
@@ -11,8 +11,8 @@ target triple = "x86_64-unknown-linux-gnu"
 ; Function Attrs: nounwind
 define void @Store(i32* nocapture %p, i32 %x) #0 {
 entry:
-  tail call void @llvm.dbg.value(metadata i32* %p, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !16
-  tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !12, metadata !{!"0x102"}), !dbg !16
+  tail call void @llvm.dbg.value(metadata i32* %p, i64 0, metadata !11, metadata !DIExpression()), !dbg !16
+  tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !12, metadata !DIExpression()), !dbg !16
   store i32 %x, i32* %p, align 4, !dbg !17, !tbaa !18
   ret void, !dbg !22
 }
@@ -27,29 +27,29 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!13, !14}
 !llvm.ident = !{!15}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 (204220)\001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/build0/../2.cc] [DW_LANG_C99]
-!1 = !{!"../2.cc", !"/tmp/build0"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 (204220)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "../2.cc", directory: "/tmp/build0")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00Store\00Store\00\001\000\001\000\006\00256\001\001", !1, !5, !6, null, void (i32*, i32)* @Store, null, null, !10} ; [ DW_TAG_subprogram ] [line 1] [def] [Store]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/build0/../2.cc]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "Store", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !1, scope: !5, type: !6, function: void (i32*, i32)* @Store, variables: !10)
+!5 = !DIFile(filename: "../2.cc", directory: "/tmp/build0")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null, !8, !9}
-!8 = !{!"0xf\00\000\0064\0064\000\000", null, null, !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !9)
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !10 = !{!11, !12}
-!11 = !{!"0x101\00p\0016777217\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [p] [line 1]
-!12 = !{!"0x101\00x\0033554433\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [x] [line 1]
+!11 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p", line: 1, arg: 1, scope: !4, file: !5, type: !8)
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 1, arg: 2, scope: !4, file: !5, type: !9)
 !13 = !{i32 2, !"Dwarf Version", i32 4}
-!14 = !{i32 1, !"Debug Info Version", i32 2}
+!14 = !{i32 1, !"Debug Info Version", i32 3}
 !15 = !{!"clang version 3.5.0 (204220)"}
-!16 = !MDLocation(line: 1, scope: !4)
-!17 = !MDLocation(line: 2, scope: !4)
+!16 = !DILocation(line: 1, scope: !4)
+!17 = !DILocation(line: 2, scope: !4)
 !18 = !{!19, !19, i64 0}
 !19 = !{!"int", !20, i64 0}
 !20 = !{!"omnipotent char", !21, i64 0}
 !21 = !{!"Simple C/C++ TBAA"}
-!22 = !MDLocation(line: 3, scope: !4)
+!22 = !DILocation(line: 3, scope: !4)
 
 
 ; CHECK: @Store
diff --git a/test/Instrumentation/MemorySanitizer/unreachable.ll b/test/Instrumentation/MemorySanitizer/unreachable.ll
index c8130717c7da..e9a79ce0d0e1 100644
--- a/test/Instrumentation/MemorySanitizer/unreachable.ll
+++ b/test/Instrumentation/MemorySanitizer/unreachable.ll
@@ -10,7 +10,7 @@ entry:
   br label %exit
 
 unreachable:
-  %x = load i32* %p
+  %x = load i32, i32* %p
   br label %exit
 
 exit:
diff --git a/test/Instrumentation/MemorySanitizer/vector_cvt.ll b/test/Instrumentation/MemorySanitizer/vector_cvt.ll
index 9425e25bde5b..a7d5f2115015 100644
--- a/test/Instrumentation/MemorySanitizer/vector_cvt.ll
+++ b/test/Instrumentation/MemorySanitizer/vector_cvt.ll
@@ -34,7 +34,7 @@ entry:
 }
 
 ; CHECK: @test_cvtsi2sd
-; CHECK: [[Sa:%[_01-9a-z]+]] = load i32* {{.*}} @__msan_param_tls
+; CHECK: [[Sa:%[_01-9a-z]+]] = load i32, i32* {{.*}} @__msan_param_tls
 ; CHECK: [[Sout0:%[_01-9a-z]+]] = insertelement <2 x i64> <i64 -1, i64 -1>, i64 {{.*}}, i32 1
 ; Clear low half of result shadow
 ; CHECK: [[Sout:%[_01-9a-z]+]] = insertelement <2 x i64> {{.*}}[[Sout0]], i64 0, i32 0
diff --git a/test/Instrumentation/SanitizerCoverage/cmp-tracing.ll b/test/Instrumentation/SanitizerCoverage/cmp-tracing.ll
new file mode 100644
index 000000000000..a37cdec985e5
--- /dev/null
+++ b/test/Instrumentation/SanitizerCoverage/cmp-tracing.ll
@@ -0,0 +1,13 @@
+; Test -sanitizer-coverage-experimental-trace-compares=1
+; RUN: opt < %s -sancov -sanitizer-coverage-level=1 -sanitizer-coverage-experimental-trace-compares=1  -S | FileCheck %s --check-prefix=CHECK
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+define i32 @foo(i32 %a, i32 %b) #0 {
+entry:
+  %cmp = icmp slt i32 %a, %b
+; CHECK: call void @__sanitizer_cov_trace_cmp
+; CHECK-NEXT: icmp slt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
diff --git a/test/Instrumentation/SanitizerCoverage/coverage-dbg.ll b/test/Instrumentation/SanitizerCoverage/coverage-dbg.ll
index a1b23f1b13f2..45b4c8cb0a61 100644
--- a/test/Instrumentation/SanitizerCoverage/coverage-dbg.ll
+++ b/test/Instrumentation/SanitizerCoverage/coverage-dbg.ll
@@ -16,7 +16,7 @@
 
 ; Test that __sanitizer_cov call has !dbg pointing to the opening { of A::f().
 ; CHECK: call void @__sanitizer_cov(i32*{{.*}}), !dbg [[A:!.*]]
-; CHECK: [[A]] = !MDLocation(line: 6, scope: !{{.*}})
+; CHECK: [[A]] = !DILocation(line: 6, scope: !{{.*}})
 
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@@ -27,9 +27,9 @@ target triple = "x86_64-unknown-linux-gnu"
 ; Function Attrs: nounwind readonly uwtable
 define i32 @_ZN1A1fEv(%struct.A* nocapture readonly %this) #0 align 2 {
 entry:
-  tail call void @llvm.dbg.value(metadata %struct.A* %this, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !20
-  %x = getelementptr inbounds %struct.A* %this, i64 0, i32 0, !dbg !21
-  %0 = load i32* %x, align 4, !dbg !21
+  tail call void @llvm.dbg.value(metadata %struct.A* %this, i64 0, metadata !15, metadata !DIExpression()), !dbg !20
+  %x = getelementptr inbounds %struct.A, %struct.A* %this, i64 0, i32 0, !dbg !21
+  %0 = load i32, i32* %x, align 4, !dbg !21
   ret i32 %0, !dbg !21
 }
 
@@ -43,25 +43,25 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!17, !18}
 !llvm.ident = !{!19}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 (210251)\001\00\000\00\001", !1, !2, !3, !12, !2, !2} ; [ DW_TAG_compile_unit ] [/code/llvm/build0/../1.cc] [DW_LANG_C_plus_plus]
-!1 = !{!"../1.cc", !"/code/llvm/build0"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 (210251)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !12, globals: !2, imports: !2)
+!1 = !DIFile(filename: "../1.cc", directory: "/code/llvm/build0")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00A\001\0032\0032\000\000\000", !1, null, null, !5, null, null, !"_ZTS1A"} ; [ DW_TAG_structure_type ] [A] [line 1, size 32, align 32, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "A", line: 1, size: 32, align: 32, file: !1, elements: !5, identifier: "_ZTS1A")
 !5 = !{!6, !8}
-!6 = !{!"0xd\00x\003\0032\0032\000\000", !1, !"_ZTS1A", !7} ; [ DW_TAG_member ] [x] [line 3, size 32, align 32, offset 0] [from int]
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!8 = !{!"0x2e\00f\00f\00_ZN1A1fEv\002\000\000\000\006\00256\001\002", !1, !"_ZTS1A", !9, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 2] [f]
-!9 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 3, size: 32, align: 32, file: !1, scope: !"_ZTS1A", baseType: !7)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DISubprogram(name: "f", linkageName: "_ZN1A1fEv", line: 2, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2, file: !1, scope: !"_ZTS1A", type: !9)
+!9 = !DISubroutineType(types: !10)
 !10 = !{!7, !11}
-!11 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1A]
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1A")
 !12 = !{!13}
-!13 = !{!"0x2e\00f\00f\00_ZN1A1fEv\006\000\001\000\006\00256\001\006", !1, !"_ZTS1A", !9, null, i32 (%struct.A*)* @_ZN1A1fEv, null, !8, !14} ; [ DW_TAG_subprogram ] [line 6] [def] [f]
+!13 = !DISubprogram(name: "f", linkageName: "_ZN1A1fEv", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 6, file: !1, scope: !"_ZTS1A", type: !9, function: i32 (%struct.A*)* @_ZN1A1fEv, declaration: !8, variables: !14)
 !14 = !{!15}
-!15 = !{!"0x101\00this\0016777216\001088", !13, null, !16} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!16 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1A]
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !13, type: !16)
+!16 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1A")
 !17 = !{i32 2, !"Dwarf Version", i32 4}
-!18 = !{i32 2, !"Debug Info Version", i32 2}
+!18 = !{i32 2, !"Debug Info Version", i32 3}
 !19 = !{!"clang version 3.5.0 (210251)"}
-!20 = !MDLocation(line: 0, scope: !13)
-!21 = !MDLocation(line: 7, scope: !13)
+!20 = !DILocation(line: 0, scope: !13)
+!21 = !DILocation(line: 7, scope: !13)
diff --git a/test/Instrumentation/SanitizerCoverage/coverage.ll b/test/Instrumentation/SanitizerCoverage/coverage.ll
index 77e781e5474a..b2f0ab0680bf 100644
--- a/test/Instrumentation/SanitizerCoverage/coverage.ll
+++ b/test/Instrumentation/SanitizerCoverage/coverage.ll
@@ -2,17 +2,16 @@
 ; RUN: opt < %s -sancov -sanitizer-coverage-level=1 -S | FileCheck %s --check-prefix=CHECK1
 ; RUN: opt < %s -sancov -sanitizer-coverage-level=2 -S | FileCheck %s --check-prefix=CHECK2
 ; RUN: opt < %s -sancov -sanitizer-coverage-level=2 -sanitizer-coverage-block-threshold=10 -S | FileCheck %s --check-prefix=CHECK2
-; RUN: opt < %s -sancov -sanitizer-coverage-level=2 -sanitizer-coverage-block-threshold=1  -S | FileCheck %s --check-prefix=CHECK1
+; RUN: opt < %s -sancov -sanitizer-coverage-level=2 -sanitizer-coverage-block-threshold=0  -S | FileCheck %s --check-prefix=CHECK_WITH_CHECK
+; RUN: opt < %s -sancov -sanitizer-coverage-level=2 -sanitizer-coverage-block-threshold=1  -S | FileCheck %s --check-prefix=CHECK_WITH_CHECK
 ; RUN: opt < %s -sancov -sanitizer-coverage-level=3 -sanitizer-coverage-block-threshold=10 -S | FileCheck %s --check-prefix=CHECK3
 ; RUN: opt < %s -sancov -sanitizer-coverage-level=4 -S | FileCheck %s --check-prefix=CHECK4
+; RUN: opt < %s -sancov -sanitizer-coverage-level=3 -sanitizer-coverage-8bit-counters=1  -S | FileCheck %s --check-prefix=CHECK-8BIT
 
-; RUN: opt < %s -sancov -sanitizer-coverage-level=0  -S | FileCheck %s --check-prefix=CHECK0
-; RUN: opt < %s -sancov -sanitizer-coverage-level=1  -S | FileCheck %s --check-prefix=CHECK1
-; RUN: opt < %s -sancov -sanitizer-coverage-level=2  -S | FileCheck %s --check-prefix=CHECK2
 ; RUN: opt < %s -sancov -sanitizer-coverage-level=2 -sanitizer-coverage-block-threshold=10 \
 ; RUN:      -S | FileCheck %s --check-prefix=CHECK2
 ; RUN: opt < %s -sancov -sanitizer-coverage-level=2 -sanitizer-coverage-block-threshold=1 \
-; RUN:      -S | FileCheck %s --check-prefix=CHECK1
+; RUN:      -S | FileCheck %s --check-prefix=CHECK_WITH_CHECK
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-unknown-linux-gnu"
@@ -29,11 +28,15 @@ entry:
   ret void
 }
 
+; CHECK0-NOT: @llvm.global_ctors = {{.*}}{ i32 2, void ()* @sancov.module_ctor }
+; CHECK1: @llvm.global_ctors = {{.*}}{ i32 2, void ()* @sancov.module_ctor }
+; CHECK2: @llvm.global_ctors = {{.*}}{ i32 2, void ()* @sancov.module_ctor }
+
 ; CHECK0-NOT: call void @__sanitizer_cov(
 ; CHECK0-NOT: call void @__sanitizer_cov_module_init(
 
 ; CHECK1-LABEL: define void @foo
-; CHECK1: %0 = load atomic i32* {{.*}} monotonic, align 4, !nosanitize
+; CHECK1: %0 = load atomic i32, i32* {{.*}} monotonic, align 4, !nosanitize
 ; CHECK1: %1 = icmp sge i32 0, %0
 ; CHECK1: br i1 %1, label %2, label %3
 ; CHECK1: call void @__sanitizer_cov(i32*{{.*}})
@@ -43,9 +46,16 @@ entry:
 
 ; CHECK1-LABEL: define internal void @sancov.module_ctor
 ; CHECK1-NOT: ret
-; CHECK1: call void @__sanitizer_cov_module_init({{.*}}, i64 2)
+; CHECK1: call void @__sanitizer_cov_module_init({{.*}}, i64 2,
 ; CHECK1: ret
 
+; CHECK_WITH_CHECK-LABEL: define void @foo
+; CHECK_WITH_CHECK: __sanitizer_cov_with_check
+; CHECK_WITH_CHECK: ret void
+; CHECK_WITH_CHECK-LABEL: define internal void @sancov.module_ctor
+; CHECK_WITH_CHECK-NOT: ret
+; CHECK_WITH_CHECK: call void @__sanitizer_cov_module_init({{.*}}, i64 4,
+; CHECK_WITH_CHECK: ret
 
 ; CHECK2-LABEL: define void @foo
 ; CHECK2: call void @__sanitizer_cov
@@ -59,7 +69,7 @@ entry:
 
 ; CHECK2-LABEL: define internal void @sancov.module_ctor
 ; CHECK2-NOT: ret
-; CHECK2: call void @__sanitizer_cov_module_init({{.*}}, i64 4)
+; CHECK2: call void @__sanitizer_cov_module_init({{.*}}, i64 4,
 ; CHECK2: ret
 
 ; CHECK3-LABEL: define void @foo
@@ -71,14 +81,32 @@ entry:
 ; CHECK3-NOT: call void @__sanitizer_cov
 ; CHECK3: ret void
 
+; test -sanitizer-coverage-8bit-counters=1
+; CHECK-8BIT-LABEL: define void @foo
+
+; CHECK-8BIT: [[V11:%[0-9]*]] = load i8{{.*}}!nosanitize
+; CHECK-8BIT: [[V12:%[0-9]*]] = add i8 [[V11]], 1
+; CHECK-8BIT: store i8 [[V12]]{{.*}}!nosanitize
+; CHECK-8BIT: [[V21:%[0-9]*]] = load i8{{.*}}!nosanitize
+; CHECK-8BIT: [[V22:%[0-9]*]] = add i8 [[V21]], 1
+; CHECK-8BIT: store i8 [[V22]]{{.*}}!nosanitize
+; CHECK-8BIT: [[V31:%[0-9]*]] = load i8{{.*}}!nosanitize
+; CHECK-8BIT: [[V32:%[0-9]*]] = add i8 [[V31]], 1
+; CHECK-8BIT: store i8 [[V32]]{{.*}}!nosanitize
+; CHECK-8BIT: [[V41:%[0-9]*]] = load i8{{.*}}!nosanitize
+; CHECK-8BIT: [[V42:%[0-9]*]] = add i8 [[V41]], 1
+; CHECK-8BIT: store i8 [[V42]]{{.*}}!nosanitize
+
+; CHECK-8BIT: ret void
+
 
 %struct.StructWithVptr = type { i32 (...)** }
 
 define void @CallViaVptr(%struct.StructWithVptr* %foo) uwtable sanitize_address {
 entry:
   %0 = bitcast %struct.StructWithVptr* %foo to void (%struct.StructWithVptr*)***
-  %vtable = load void (%struct.StructWithVptr*)*** %0, align 8
-  %1 = load void (%struct.StructWithVptr*)** %vtable, align 8
+  %vtable = load void (%struct.StructWithVptr*)**, void (%struct.StructWithVptr*)*** %0, align 8
+  %1 = load void (%struct.StructWithVptr*)*, void (%struct.StructWithVptr*)** %vtable, align 8
   tail call void %1(%struct.StructWithVptr* %foo)
   tail call void %1(%struct.StructWithVptr* %foo)
   tail call void asm sideeffect "", ""()
diff --git a/test/Instrumentation/SanitizerCoverage/coverage2-dbg.ll b/test/Instrumentation/SanitizerCoverage/coverage2-dbg.ll
index cb436a8c948c..f9b8e712688c 100644
--- a/test/Instrumentation/SanitizerCoverage/coverage2-dbg.ll
+++ b/test/Instrumentation/SanitizerCoverage/coverage2-dbg.ll
@@ -21,13 +21,13 @@ target triple = "x86_64-unknown-linux-gnu"
 ; CHECK: call void @__sanitizer_cov(i32*{{.*}}), !dbg [[B:!.*]]
 ; CHECK: call void @__sanitizer_cov(i32*{{.*}}), !dbg [[C:!.*]]
 ; CHECK: ret void
-; CHECK: [[A]] = !MDLocation(line: 1, scope: !{{.*}})
-; CHECK: [[B]] = !MDLocation(line: 3, column: 5, scope: !{{.*}})
-; CHECK: [[C]] = !MDLocation(line: 4, column: 1, scope: !{{.*}})
+; CHECK: [[A]] = !DILocation(line: 1, scope: !{{.*}})
+; CHECK: [[B]] = !DILocation(line: 3, column: 5, scope: !{{.*}})
+; CHECK: [[C]] = !DILocation(line: 4, column: 1, scope: !{{.*}})
 
 define void @_Z3fooPi(i32* %a) #0 {
 entry:
-  tail call void @llvm.dbg.value(metadata i32* %a, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !15
+  tail call void @llvm.dbg.value(metadata i32* %a, i64 0, metadata !11, metadata !DIExpression()), !dbg !15
   %tobool = icmp eq i32* %a, null, !dbg !16
   br i1 %tobool, label %if.end, label %if.then, !dbg !16
 
@@ -49,27 +49,27 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!12, !13}
 !llvm.ident = !{!14}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 (217079)\001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [FOO/if.cc] [DW_LANG_C_plus_plus]
-!1 = !{!"if.cc", !"FOO"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 (217079)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "if.cc", directory: "FOO")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00_Z3fooPi\001\000\001\000\006\00256\001\001", !1, !5, !6, null, void (i32*)* @_Z3fooPi, null, null, !10} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [FOO/if.cc]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", linkageName: "_Z3fooPi", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !1, scope: !5, type: !6, function: void (i32*)* @_Z3fooPi, variables: !10)
+!5 = !DIFile(filename: "if.cc", directory: "FOO")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null, !8}
-!8 = !{!"0xf\00\000\0064\0064\000\000", null, null, !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !9)
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !10 = !{!11}
-!11 = !{!"0x101\00a\0016777217\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [a] [line 1]
+!11 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 1, arg: 1, scope: !4, file: !5, type: !8)
 !12 = !{i32 2, !"Dwarf Version", i32 4}
-!13 = !{i32 2, !"Debug Info Version", i32 2}
+!13 = !{i32 2, !"Debug Info Version", i32 3}
 !14 = !{!"clang version 3.6.0 (217079)"}
-!15 = !MDLocation(line: 1, column: 15, scope: !4)
-!16 = !MDLocation(line: 2, column: 7, scope: !17)
-!17 = !{!"0xb\002\007\000", !1, !4} ; [ DW_TAG_lexical_block ] [FOO/if.cc]
-!18 = !MDLocation(line: 3, column: 5, scope: !17)
+!15 = !DILocation(line: 1, column: 15, scope: !4)
+!16 = !DILocation(line: 2, column: 7, scope: !17)
+!17 = distinct !DILexicalBlock(line: 2, column: 7, file: !1, scope: !4)
+!18 = !DILocation(line: 3, column: 5, scope: !17)
 !19 = !{!20, !20, i64 0}
 !20 = !{!"int", !21, i64 0}
 !21 = !{!"omnipotent char", !22, i64 0}
 !22 = !{!"Simple C/C++ TBAA"}
-!23 = !MDLocation(line: 4, column: 1, scope: !4)
+!23 = !DILocation(line: 4, column: 1, scope: !4)
diff --git a/test/Instrumentation/ThreadSanitizer/atomic.ll b/test/Instrumentation/ThreadSanitizer/atomic.ll
index e40268f97b99..1d6ac3851e23 100644
--- a/test/Instrumentation/ThreadSanitizer/atomic.ll
+++ b/test/Instrumentation/ThreadSanitizer/atomic.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 define i8 @atomic8_load_unordered(i8* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i8* %a unordered, align 1
+  %0 = load atomic i8, i8* %a unordered, align 1
   ret i8 %0
 }
 ; CHECK: atomic8_load_unordered
@@ -12,7 +12,7 @@ entry:
 
 define i8 @atomic8_load_monotonic(i8* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i8* %a monotonic, align 1
+  %0 = load atomic i8, i8* %a monotonic, align 1
   ret i8 %0
 }
 ; CHECK: atomic8_load_monotonic
@@ -20,7 +20,7 @@ entry:
 
 define i8 @atomic8_load_acquire(i8* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i8* %a acquire, align 1
+  %0 = load atomic i8, i8* %a acquire, align 1
   ret i8 %0
 }
 ; CHECK: atomic8_load_acquire
@@ -28,7 +28,7 @@ entry:
 
 define i8 @atomic8_load_seq_cst(i8* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i8* %a seq_cst, align 1
+  %0 = load atomic i8, i8* %a seq_cst, align 1
   ret i8 %0
 }
 ; CHECK: atomic8_load_seq_cst
@@ -388,7 +388,7 @@ entry:
 
 define i16 @atomic16_load_unordered(i16* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i16* %a unordered, align 2
+  %0 = load atomic i16, i16* %a unordered, align 2
   ret i16 %0
 }
 ; CHECK: atomic16_load_unordered
@@ -396,7 +396,7 @@ entry:
 
 define i16 @atomic16_load_monotonic(i16* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i16* %a monotonic, align 2
+  %0 = load atomic i16, i16* %a monotonic, align 2
   ret i16 %0
 }
 ; CHECK: atomic16_load_monotonic
@@ -404,7 +404,7 @@ entry:
 
 define i16 @atomic16_load_acquire(i16* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i16* %a acquire, align 2
+  %0 = load atomic i16, i16* %a acquire, align 2
   ret i16 %0
 }
 ; CHECK: atomic16_load_acquire
@@ -412,7 +412,7 @@ entry:
 
 define i16 @atomic16_load_seq_cst(i16* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i16* %a seq_cst, align 2
+  %0 = load atomic i16, i16* %a seq_cst, align 2
   ret i16 %0
 }
 ; CHECK: atomic16_load_seq_cst
@@ -772,7 +772,7 @@ entry:
 
 define i32 @atomic32_load_unordered(i32* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i32* %a unordered, align 4
+  %0 = load atomic i32, i32* %a unordered, align 4
   ret i32 %0
 }
 ; CHECK: atomic32_load_unordered
@@ -780,7 +780,7 @@ entry:
 
 define i32 @atomic32_load_monotonic(i32* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i32* %a monotonic, align 4
+  %0 = load atomic i32, i32* %a monotonic, align 4
   ret i32 %0
 }
 ; CHECK: atomic32_load_monotonic
@@ -788,7 +788,7 @@ entry:
 
 define i32 @atomic32_load_acquire(i32* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i32* %a acquire, align 4
+  %0 = load atomic i32, i32* %a acquire, align 4
   ret i32 %0
 }
 ; CHECK: atomic32_load_acquire
@@ -796,7 +796,7 @@ entry:
 
 define i32 @atomic32_load_seq_cst(i32* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i32* %a seq_cst, align 4
+  %0 = load atomic i32, i32* %a seq_cst, align 4
   ret i32 %0
 }
 ; CHECK: atomic32_load_seq_cst
@@ -1156,7 +1156,7 @@ entry:
 
 define i64 @atomic64_load_unordered(i64* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i64* %a unordered, align 8
+  %0 = load atomic i64, i64* %a unordered, align 8
   ret i64 %0
 }
 ; CHECK: atomic64_load_unordered
@@ -1164,7 +1164,7 @@ entry:
 
 define i64 @atomic64_load_monotonic(i64* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i64* %a monotonic, align 8
+  %0 = load atomic i64, i64* %a monotonic, align 8
   ret i64 %0
 }
 ; CHECK: atomic64_load_monotonic
@@ -1172,7 +1172,7 @@ entry:
 
 define i64 @atomic64_load_acquire(i64* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i64* %a acquire, align 8
+  %0 = load atomic i64, i64* %a acquire, align 8
   ret i64 %0
 }
 ; CHECK: atomic64_load_acquire
@@ -1180,7 +1180,7 @@ entry:
 
 define i64 @atomic64_load_seq_cst(i64* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i64* %a seq_cst, align 8
+  %0 = load atomic i64, i64* %a seq_cst, align 8
   ret i64 %0
 }
 ; CHECK: atomic64_load_seq_cst
@@ -1540,7 +1540,7 @@ entry:
 
 define i128 @atomic128_load_unordered(i128* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i128* %a unordered, align 16
+  %0 = load atomic i128, i128* %a unordered, align 16
   ret i128 %0
 }
 ; CHECK: atomic128_load_unordered
@@ -1548,7 +1548,7 @@ entry:
 
 define i128 @atomic128_load_monotonic(i128* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i128* %a monotonic, align 16
+  %0 = load atomic i128, i128* %a monotonic, align 16
   ret i128 %0
 }
 ; CHECK: atomic128_load_monotonic
@@ -1556,7 +1556,7 @@ entry:
 
 define i128 @atomic128_load_acquire(i128* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i128* %a acquire, align 16
+  %0 = load atomic i128, i128* %a acquire, align 16
   ret i128 %0
 }
 ; CHECK: atomic128_load_acquire
@@ -1564,7 +1564,7 @@ entry:
 
 define i128 @atomic128_load_seq_cst(i128* %a) nounwind uwtable {
 entry:
-  %0 = load atomic i128* %a seq_cst, align 16
+  %0 = load atomic i128, i128* %a seq_cst, align 16
   ret i128 %0
 }
 ; CHECK: atomic128_load_seq_cst
diff --git a/test/Instrumentation/ThreadSanitizer/capture.ll b/test/Instrumentation/ThreadSanitizer/capture.ll
new file mode 100644
index 000000000000..038b8c0cbc92
--- /dev/null
+++ b/test/Instrumentation/ThreadSanitizer/capture.ll
@@ -0,0 +1,91 @@
+; RUN: opt < %s -tsan -S | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+declare void @escape(i32*)
+
+@sink = global i32* null, align 4
+
+define void @captured0() nounwind uwtable sanitize_thread {
+entry:
+  %ptr = alloca i32, align 4
+  ; escapes due to call
+  call void @escape(i32* %ptr)
+  store i32 42, i32* %ptr, align 4
+  ret void
+}
+; CHECK-LABEL: define void @captured0
+; CHECK: __tsan_write
+; CHECK: ret void
+
+define void @captured1() nounwind uwtable sanitize_thread {
+entry:
+  %ptr = alloca i32, align 4
+  ; escapes due to store into global
+  store i32* %ptr, i32** @sink, align 8
+  store i32 42, i32* %ptr, align 4
+  ret void
+}
+; CHECK-LABEL: define void @captured1
+; CHECK: __tsan_write
+; CHECK: __tsan_write
+; CHECK: ret void
+
+define void @captured2() nounwind uwtable sanitize_thread {
+entry:
+  %ptr = alloca i32, align 4
+  %tmp = alloca i32*, align 8
+  ; transitive escape
+  store i32* %ptr, i32** %tmp, align 8
+  %0 = load i32*, i32** %tmp, align 8
+  store i32* %0, i32** @sink, align 8
+  store i32 42, i32* %ptr, align 4
+  ret void
+}
+; CHECK-LABEL: define void @captured2
+; CHECK: __tsan_write
+; CHECK: __tsan_write
+; CHECK: ret void
+
+define void @notcaptured0() nounwind uwtable sanitize_thread {
+entry:
+  %ptr = alloca i32, align 4
+  store i32 42, i32* %ptr, align 4
+  ; escapes due to call
+  call void @escape(i32* %ptr)
+  ret void
+}
+; CHECK-LABEL: define void @notcaptured0
+; CHECK: __tsan_write
+; CHECK: ret void
+
+define void @notcaptured1() nounwind uwtable sanitize_thread {
+entry:
+  %ptr = alloca i32, align 4
+  store i32 42, i32* %ptr, align 4
+  ; escapes due to store into global
+  store i32* %ptr, i32** @sink, align 8
+  ret void
+}
+; CHECK-LABEL: define void @notcaptured1
+; CHECK: __tsan_write
+; CHECK: __tsan_write
+; CHECK: ret void
+
+define void @notcaptured2() nounwind uwtable sanitize_thread {
+entry:
+  %ptr = alloca i32, align 4
+  %tmp = alloca i32*, align 8
+  store i32 42, i32* %ptr, align 4
+  ; transitive escape
+  store i32* %ptr, i32** %tmp, align 8
+  %0 = load i32*, i32** %tmp, align 8
+  store i32* %0, i32** @sink, align 8
+  ret void
+}
+; CHECK-LABEL: define void @notcaptured2
+; CHECK: __tsan_write
+; CHECK: __tsan_write
+; CHECK: ret void
+
+
diff --git a/test/Instrumentation/ThreadSanitizer/no_sanitize_thread.ll b/test/Instrumentation/ThreadSanitizer/no_sanitize_thread.ll
index 3949fd50a97d..a90a56064a08 100644
--- a/test/Instrumentation/ThreadSanitizer/no_sanitize_thread.ll
+++ b/test/Instrumentation/ThreadSanitizer/no_sanitize_thread.ll
@@ -6,20 +6,20 @@ target triple = "x86_64-unknown-linux-gnu"
 ; no sanitize_thread attribute here
 define i32 @read_4_bytes(i32* %a) {
 entry:
-  %tmp1 = load i32* %a, align 4
+  %tmp1 = load i32, i32* %a, align 4
   ret i32 %tmp1
 }
 
 ; CHECK: define i32 @read_4_bytes(i32* %a) {
 ; CHECK-NEXT: entry:
-; CHECK-NEXT:   %tmp1 = load i32* %a, align 4
+; CHECK-NEXT:   %tmp1 = load i32, i32* %a, align 4
 ; CHECK: ret i32 %tmp1
 
 ; no sanitize_thread attribute here
 define i32 @read_4_bytes_and_call(i32* %a) {
 entry:
   call void @foo()
-  %tmp1 = load i32* %a, align 4
+  %tmp1 = load i32, i32* %a, align 4
   ret i32 %tmp1
 }
 
@@ -28,7 +28,7 @@ entry:
 ; CHECK-NEXT:   %0 = call i8* @llvm.returnaddress(i32 0)
 ; CHECK-NEXT:   call void @__tsan_func_entry(i8* %0)
 ; CHECK-NEXT:   call void @foo()
-; CHECK-NEXT:   %tmp1 = load i32* %a, align 4
+; CHECK-NEXT:   %tmp1 = load i32, i32* %a, align 4
 ; CHECK-NEXT:   call void @__tsan_func_exit()
 ; CHECK-NEXT:   ret i32 %tmp1
 
diff --git a/test/Instrumentation/ThreadSanitizer/read_before_write.ll b/test/Instrumentation/ThreadSanitizer/read_before_write.ll
index cb6603bc1438..c15ab13ff1bd 100644
--- a/test/Instrumentation/ThreadSanitizer/read_before_write.ll
+++ b/test/Instrumentation/ThreadSanitizer/read_before_write.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 define void @IncrementMe(i32* nocapture %ptr) nounwind uwtable sanitize_thread {
 entry:
-  %0 = load i32* %ptr, align 4
+  %0 = load i32, i32* %ptr, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %ptr, align 4
   ret void
@@ -16,7 +16,7 @@ entry:
 
 define void @IncrementMeWithCallInBetween(i32* nocapture %ptr) nounwind uwtable sanitize_thread {
 entry:
-  %0 = load i32* %ptr, align 4
+  %0 = load i32, i32* %ptr, align 4
   %inc = add nsw i32 %0, 1
   call void @foo()
   store i32 %inc, i32* %ptr, align 4
diff --git a/test/Instrumentation/ThreadSanitizer/read_from_global.ll b/test/Instrumentation/ThreadSanitizer/read_from_global.ll
index 037dd56ffb73..76ee50c91fd2 100644
--- a/test/Instrumentation/ThreadSanitizer/read_from_global.ll
+++ b/test/Instrumentation/ThreadSanitizer/read_from_global.ll
@@ -6,7 +6,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 @const_global = external constant i32
 define i32 @read_from_const_global() nounwind uwtable sanitize_thread readnone {
 entry:
-  %0 = load i32* @const_global, align 4
+  %0 = load i32, i32* @const_global, align 4
   ret i32 %0
 }
 ; CHECK: define i32 @read_from_const_global
@@ -16,7 +16,7 @@ entry:
 @non_const_global = global i32 0, align 4
 define i32 @read_from_non_const_global() nounwind uwtable sanitize_thread readonly {
 entry:
-  %0 = load i32* @non_const_global, align 4
+  %0 = load i32, i32* @non_const_global, align 4
   ret i32 %0
 }
 
@@ -28,8 +28,8 @@ entry:
 define i32 @read_from_const_global_array(i32 %idx) nounwind uwtable sanitize_thread readnone {
 entry:
   %idxprom = sext i32 %idx to i64
-  %arrayidx = getelementptr inbounds [10 x i32]* @const_global_array, i64 0, i64 %idxprom
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* @const_global_array, i64 0, i64 %idxprom
+  %0 = load i32, i32* %arrayidx, align 4
   ret i32 %0
 }
 
@@ -41,8 +41,8 @@ entry:
 define void @call_virtual_func(%struct.Foo* %f) uwtable sanitize_thread {
 entry:
   %0 = bitcast %struct.Foo* %f to void (%struct.Foo*)***
-  %vtable = load void (%struct.Foo*)*** %0, align 8, !tbaa !2
-  %1 = load void (%struct.Foo*)** %vtable, align 8
+  %vtable = load void (%struct.Foo*)**, void (%struct.Foo*)*** %0, align 8, !tbaa !2
+  %1 = load void (%struct.Foo*)*, void (%struct.Foo*)** %vtable, align 8
   call void %1(%struct.Foo* %f)
   ret void
 }
diff --git a/test/Instrumentation/ThreadSanitizer/tsan-vs-gvn.ll b/test/Instrumentation/ThreadSanitizer/tsan-vs-gvn.ll
index a83a274bcf6e..df7608dd449c 100644
--- a/test/Instrumentation/ThreadSanitizer/tsan-vs-gvn.ll
+++ b/test/Instrumentation/ThreadSanitizer/tsan-vs-gvn.ll
@@ -12,9 +12,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 
 define i32 @test_widening_bad(i8* %P) nounwind ssp noredzone sanitize_thread {
 entry:
-  %tmp = load i8* getelementptr inbounds (%struct_of_8_bytes_4_aligned* @f, i64 0, i32 1), align 4
+  %tmp = load i8, i8* getelementptr inbounds (%struct_of_8_bytes_4_aligned, %struct_of_8_bytes_4_aligned* @f, i64 0, i32 1), align 4
   %conv = zext i8 %tmp to i32
-  %tmp1 = load i8* getelementptr inbounds (%struct_of_8_bytes_4_aligned* @f, i64 0, i32 3), align 1
+  %tmp1 = load i8, i8* getelementptr inbounds (%struct_of_8_bytes_4_aligned, %struct_of_8_bytes_4_aligned* @f, i64 0, i32 3), align 1
   %conv2 = zext i8 %tmp1 to i32
   %add = add nsw i32 %conv, %conv2
   ret i32 %add
diff --git a/test/Instrumentation/ThreadSanitizer/tsan_basic.ll b/test/Instrumentation/ThreadSanitizer/tsan_basic.ll
index dc6e43e3ecb9..7e049c548f22 100644
--- a/test/Instrumentation/ThreadSanitizer/tsan_basic.ll
+++ b/test/Instrumentation/ThreadSanitizer/tsan_basic.ll
@@ -5,17 +5,17 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @read_4_bytes(i32* %a) sanitize_thread {
 entry:
-  %tmp1 = load i32* %a, align 4
+  %tmp1 = load i32, i32* %a, align 4
   ret i32 %tmp1
 }
 
-; CHECK: @llvm.global_ctors = {{.*}}@__tsan_init
+; CHECK: @llvm.global_ctors = {{.*}}@tsan.module_ctor
 
 ; CHECK: define i32 @read_4_bytes(i32* %a)
 ; CHECK:        call void @__tsan_func_entry(i8* %0)
 ; CHECK-NEXT:   %1 = bitcast i32* %a to i8*
 ; CHECK-NEXT:   call void @__tsan_read4(i8* %1)
-; CHECK-NEXT:   %tmp1 = load i32* %a, align 4
+; CHECK-NEXT:   %tmp1 = load i32, i32* %a, align 4
 ; CHECK-NEXT:   call void @__tsan_func_exit()
 ; CHECK: ret i32
 
@@ -53,3 +53,6 @@ entry:
 ; CHECK: call i8* @memset
 ; CHECK: ret void
 }
+
+; CHECK: define internal void @tsan.module_ctor()
+; CHECK: call void @__tsan_init()
diff --git a/test/Instrumentation/ThreadSanitizer/unaligned.ll b/test/Instrumentation/ThreadSanitizer/unaligned.ll
new file mode 100644
index 000000000000..89461b4b274e
--- /dev/null
+++ b/test/Instrumentation/ThreadSanitizer/unaligned.ll
@@ -0,0 +1,143 @@
+; RUN: opt < %s -tsan -S | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+define i16 @test_unaligned_read2(i16* %a) sanitize_thread {
+entry:
+  %tmp1 = load i16, i16* %a, align 1
+  ret i16 %tmp1
+}
+
+; CHECK-LABEL: define i16 @test_unaligned_read2(i16* %a)
+; CHECK:        call void @__tsan_func_entry(i8* %0)
+; CHECK-NEXT:   %1 = bitcast i16* %a to i8*
+; CHECK-NEXT:   call void @__tsan_unaligned_read2(i8* %1)
+; CHECK-NEXT:   %tmp1 = load i16, i16* %a, align 1
+; CHECK-NEXT:   call void @__tsan_func_exit()
+; CHECK: ret i16
+
+define i32 @test_unaligned_read4(i32* %a) sanitize_thread {
+entry:
+  %tmp1 = load i32, i32* %a, align 2
+  ret i32 %tmp1
+}
+
+; CHECK-LABEL: define i32 @test_unaligned_read4(i32* %a)
+; CHECK:        call void @__tsan_func_entry(i8* %0)
+; CHECK-NEXT:   %1 = bitcast i32* %a to i8*
+; CHECK-NEXT:   call void @__tsan_unaligned_read4(i8* %1)
+; CHECK-NEXT:   %tmp1 = load i32, i32* %a, align 2
+; CHECK-NEXT:   call void @__tsan_func_exit()
+; CHECK: ret i32
+
+define i64 @test_unaligned_read8(i64* %a) sanitize_thread {
+entry:
+  %tmp1 = load i64, i64* %a, align 4
+  ret i64 %tmp1
+}
+
+; CHECK-LABEL: define i64 @test_unaligned_read8(i64* %a)
+; CHECK:        call void @__tsan_func_entry(i8* %0)
+; CHECK-NEXT:   %1 = bitcast i64* %a to i8*
+; CHECK-NEXT:   call void @__tsan_unaligned_read8(i8* %1)
+; CHECK-NEXT:   %tmp1 = load i64, i64* %a, align 4
+; CHECK-NEXT:   call void @__tsan_func_exit()
+; CHECK: ret i64
+
+define i128 @test_unaligned_read16(i128* %a) sanitize_thread {
+entry:
+  %tmp1 = load i128, i128* %a, align 1
+  ret i128 %tmp1
+}
+
+; CHECK-LABEL: define i128 @test_unaligned_read16(i128* %a)
+; CHECK:        call void @__tsan_func_entry(i8* %0)
+; CHECK-NEXT:   %1 = bitcast i128* %a to i8*
+; CHECK-NEXT:   call void @__tsan_unaligned_read16(i8* %1)
+; CHECK-NEXT:   %tmp1 = load i128, i128* %a, align 1
+; CHECK-NEXT:   call void @__tsan_func_exit()
+; CHECK: ret i128
+
+define i128 @test_aligned_read16(i128* %a) sanitize_thread {
+entry:
+  %tmp1 = load i128, i128* %a, align 8
+  ret i128 %tmp1
+}
+
+; CHECK-LABEL: define i128 @test_aligned_read16(i128* %a)
+; CHECK:        call void @__tsan_func_entry(i8* %0)
+; CHECK-NEXT:   %1 = bitcast i128* %a to i8*
+; CHECK-NEXT:   call void @__tsan_read16(i8* %1)
+; CHECK-NEXT:   %tmp1 = load i128, i128* %a, align 8
+; CHECK-NEXT:   call void @__tsan_func_exit()
+; CHECK: ret i128
+
+define void @test_unaligned_write2(i16* %a) sanitize_thread {
+entry:
+  store i16 1, i16* %a, align 1
+  ret void
+}
+
+; CHECK-LABEL: define void @test_unaligned_write2(i16* %a)
+; CHECK:        call void @__tsan_func_entry(i8* %0)
+; CHECK-NEXT:   %1 = bitcast i16* %a to i8*
+; CHECK-NEXT:   call void @__tsan_unaligned_write2(i8* %1)
+; CHECK-NEXT:   store i16 1, i16* %a, align 1
+; CHECK-NEXT:   call void @__tsan_func_exit()
+; CHECK: ret void
+
+define void @test_unaligned_write4(i32* %a) sanitize_thread {
+entry:
+  store i32 1, i32* %a, align 1
+  ret void
+}
+
+; CHECK-LABEL: define void @test_unaligned_write4(i32* %a)
+; CHECK:        call void @__tsan_func_entry(i8* %0)
+; CHECK-NEXT:   %1 = bitcast i32* %a to i8*
+; CHECK-NEXT:   call void @__tsan_unaligned_write4(i8* %1)
+; CHECK-NEXT:   store i32 1, i32* %a, align 1
+; CHECK-NEXT:   call void @__tsan_func_exit()
+; CHECK: ret void
+
+define void @test_unaligned_write8(i64* %a) sanitize_thread {
+entry:
+  store i64 1, i64* %a, align 1
+  ret void
+}
+
+; CHECK-LABEL: define void @test_unaligned_write8(i64* %a)
+; CHECK:        call void @__tsan_func_entry(i8* %0)
+; CHECK-NEXT:   %1 = bitcast i64* %a to i8*
+; CHECK-NEXT:   call void @__tsan_unaligned_write8(i8* %1)
+; CHECK-NEXT:   store i64 1, i64* %a, align 1
+; CHECK-NEXT:   call void @__tsan_func_exit()
+; CHECK: ret void
+
+define void @test_unaligned_write16(i128* %a) sanitize_thread {
+entry:
+  store i128 1, i128* %a, align 1
+  ret void
+}
+
+; CHECK-LABEL: define void @test_unaligned_write16(i128* %a)
+; CHECK:        call void @__tsan_func_entry(i8* %0)
+; CHECK-NEXT:   %1 = bitcast i128* %a to i8*
+; CHECK-NEXT:   call void @__tsan_unaligned_write16(i8* %1)
+; CHECK-NEXT:   store i128 1, i128* %a, align 1
+; CHECK-NEXT:   call void @__tsan_func_exit()
+; CHECK: ret void
+
+define void @test_aligned_write16(i128* %a) sanitize_thread {
+entry:
+  store i128 1, i128* %a, align 8
+  ret void
+}
+
+; CHECK-LABEL: define void @test_aligned_write16(i128* %a)
+; CHECK:        call void @__tsan_func_entry(i8* %0)
+; CHECK-NEXT:   %1 = bitcast i128* %a to i8*
+; CHECK-NEXT:   call void @__tsan_write16(i8* %1)
+; CHECK-NEXT:   store i128 1, i128* %a, align 8
+; CHECK-NEXT:   call void @__tsan_func_exit()
+; CHECK: ret void
diff --git a/test/Instrumentation/ThreadSanitizer/vptr_read.ll b/test/Instrumentation/ThreadSanitizer/vptr_read.ll
index cccdeb8245d9..6ed64c6acdfc 100644
--- a/test/Instrumentation/ThreadSanitizer/vptr_read.ll
+++ b/test/Instrumentation/ThreadSanitizer/vptr_read.ll
@@ -5,7 +5,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 define i8 @Foo(i8* %a) nounwind uwtable sanitize_thread {
 entry:
 ; CHECK: call void @__tsan_vptr_read
-  %0 = load i8* %a, align 8, !tbaa !0
+  %0 = load i8, i8* %a, align 8, !tbaa !0
   ret i8 %0
 }
 !0 = !{!2, !2, i64 0}
diff --git a/test/Integer/2007-01-19-TruncSext.ll b/test/Integer/2007-01-19-TruncSext.ll
index e6d89ddaf33e..d8248713dff0 100644
--- a/test/Integer/2007-01-19-TruncSext.ll
+++ b/test/Integer/2007-01-19-TruncSext.ll
@@ -11,7 +11,7 @@ declare i32 @printf(i8* %format, ...)
 
 define void @multiply(i32 %index, i32 %X, i32 %Y) {
   %Z = mul i32 %X, %Y
-  %P = getelementptr [20 x i17]* @ARRAY, i32 0, i32 %index
+  %P = getelementptr [20 x i17], [20 x i17]* @ARRAY, i32 0, i32 %index
   %Result = trunc i32 %Z to i17
   store i17 %Result, i17* %P
   ret void
@@ -20,11 +20,11 @@ define void @multiply(i32 %index, i32 %X, i32 %Y) {
 define i32 @main(i32 %argc, i8** %argv) {
   %i = bitcast i32 0 to i32
   call void @multiply(i32 %i, i32 -1, i32 255) 
-  %P = getelementptr [20 x i17]* @ARRAY, i32 0, i32 0
-  %X = load i17* %P
+  %P = getelementptr [20 x i17], [20 x i17]* @ARRAY, i32 0, i32 0
+  %X = load i17, i17* %P
   %result = sext i17 %X to i32
-  %fmt = getelementptr [4 x i8]* @FORMAT, i32 0, i32 0
-  call i32 (i8*,...)* @printf(i8* %fmt, i32 %result)
+  %fmt = getelementptr [4 x i8], [4 x i8]* @FORMAT, i32 0, i32 0
+  call i32 (i8*,...) @printf(i8* %fmt, i32 %result)
   ret i32 0
 }
 
diff --git a/test/Integer/BitPacked.ll b/test/Integer/BitPacked.ll
index e6e453ab0c24..def0a839a094 100644
--- a/test/Integer/BitPacked.ll
+++ b/test/Integer/BitPacked.ll
@@ -10,8 +10,8 @@ define void @main()
 {
         store <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, <4 x float>* @foo1
         store <2 x i10> <i10 4, i10 4>, <2 x i10>* @foo2
-	%l1 = load <4 x float>* @foo1
-        %l2 = load <2 x i10>* @foo2
+	%l1 = load <4 x float>, <4 x float>* @foo1
+        %l2 = load <2 x i10>, <2 x i10>* @foo2
         %r1 = extractelement <2 x i10> %l2, i32 1    
         %r2 = extractelement <2 x i10> %l2, i32 0
         %t = mul i10 %r1, %r2
diff --git a/test/Integer/constexpr_bt.ll b/test/Integer/constexpr_bt.ll
index fc8b06d4f406..36094df9ed1e 100644
--- a/test/Integer/constexpr_bt.ll
+++ b/test/Integer/constexpr_bt.ll
@@ -34,17 +34,17 @@ global float 0.0
 ;;---------------------------------------------------
 
 @array  = constant [2 x i33] [ i33 12, i33 52 ]
-@arrayPtr = global i33* getelementptr ([2 x i33]* @array, i64 0, i64 0)    ;; i33* &@array[0][0]
-@arrayPtr5 = global i33** getelementptr (i33** @arrayPtr, i64 5)    ;; i33* &@arrayPtr[5]
+@arrayPtr = global i33* getelementptr ([2 x i33], [2 x i33]* @array, i64 0, i64 0)    ;; i33* &@array[0][0]
+@arrayPtr5 = global i33** getelementptr (i33*, i33** @arrayPtr, i64 5)    ;; i33* &@arrayPtr[5]
 
 @somestr = constant [11x i8] c"hello world"
-@char5  = global i8* getelementptr([11x i8]* @somestr, i64 0, i64 5)
+@char5  = global i8* getelementptr([11x i8], [11x i8]* @somestr, i64 0, i64 5)
 
 ;; cast of getelementptr
-@char8a = global i33* bitcast (i8* getelementptr([11x i8]* @somestr, i64 0, i64 8) to i33*)
+@char8a = global i33* bitcast (i8* getelementptr([11x i8], [11x i8]* @somestr, i64 0, i64 8) to i33*)
 
 ;; getelementptr containing casts
-@char8b = global i8* getelementptr([11x i8]* @somestr, i64 sext (i8 0 to i64), i64 sext (i8 8 to i64))
+@char8b = global i8* getelementptr([11x i8], [11x i8]* @somestr, i64 sext (i8 0 to i64), i64 sext (i8 8 to i64))
 
 ;;-------------------------------------------------------
 ;; TODO: Test constant getelementpr expressions for structures
@@ -63,17 +63,17 @@ global float 0.0
 @S3  = global %SAType* @S3c		    ;; Ref. to constant S3
 
 					    ;; Pointer to float (**@S1).1.0
-@S1fld1a = global float* getelementptr (%SType* @S2c, i64 0, i32 1, i32 0)
+@S1fld1a = global float* getelementptr (%SType, %SType* @S2c, i64 0, i32 1, i32 0)
 					    ;; Another ptr to the same!
-@S1fld1b = global float* getelementptr (%SType* @S2c, i64 0, i32 1, i32 0)
+@S1fld1b = global float* getelementptr (%SType, %SType* @S2c, i64 0, i32 1, i32 0)
 
 @S1fld1bptr = global float** @S1fld1b	    ;; Ref. to previous pointer
 
 					    ;; Pointer to i8 (**@S2).1.1.0
-@S2fld3 = global i8* getelementptr (%SType* @S2c, i64 0, i32 1, i32 1, i32 0) 
+@S2fld3 = global i8* getelementptr (%SType, %SType* @S2c, i64 0, i32 1, i32 1, i32 0) 
 
 					    ;; Pointer to float (**@S2).1.0[0]
-;@S3fld3 = global float* getelementptr (%SAType** @S3, i64 0, i64 0, i32 1, i32 0, i64 0) 
+;@S3fld3 = global float* getelementptr (%SAType*, %SAType** @S3, i64 0, i64 0, i32 1, i32 0, i64 0) 
 
 ;;---------------------------------------------------------
 ;; TODO: Test constant expressions for unary and binary operators
diff --git a/test/Integer/packed_bt.ll b/test/Integer/packed_bt.ll
index f6ea87ce6ce3..ecaf621ac846 100644
--- a/test/Integer/packed_bt.ll
+++ b/test/Integer/packed_bt.ll
@@ -10,7 +10,7 @@ define void @main()
 {
         store <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, <4 x float>* @foo1
         store <2 x i10> <i10 4, i10 4>, <2 x i10>* @foo2
-	%l1 = load <4 x float>* @foo1
-        %l2 = load <2 x i10>* @foo2
+	%l1 = load <4 x float>, <4 x float>* @foo1
+        %l2 = load <2 x i10>, <2 x i10>* @foo2
         ret void
 }
diff --git a/test/Integer/packed_struct_bt.ll b/test/Integer/packed_struct_bt.ll
index b8301bab545c..ae9a04c69a34 100644
--- a/test/Integer/packed_struct_bt.ll
+++ b/test/Integer/packed_struct_bt.ll
@@ -16,9 +16,9 @@
 
 define i35 @main() 
 {
-        %tmp = load i35*  getelementptr (%struct.anon* @foos, i32 0, i32 1)            ; <i35> [#uses=1]
-        %tmp3 = load i35* getelementptr (%struct.anon* @foos, i32 0, i32 2)            ; <i35> [#uses=1]
-        %tmp6 = load i35* getelementptr (%struct.anon* @foos, i32 0, i32 3)            ; <i35> [#uses=1]
+        %tmp = load i35, i35*  getelementptr (%struct.anon, %struct.anon* @foos, i32 0, i32 1)            ; <i35> [#uses=1]
+        %tmp3 = load i35, i35* getelementptr (%struct.anon, %struct.anon* @foos, i32 0, i32 2)            ; <i35> [#uses=1]
+        %tmp6 = load i35, i35* getelementptr (%struct.anon, %struct.anon* @foos, i32 0, i32 3)            ; <i35> [#uses=1]
         %tmp4 = add i35 %tmp3, %tmp             ; <i35> [#uses=1]
         %tmp7 = add i35 %tmp4, %tmp6            ; <i35> [#uses=1]
         ret i35 %tmp7
@@ -26,8 +26,8 @@ define i35 @main()
 
 define i35 @bar() {
 entry:
-        %tmp = load i35* getelementptr([2 x <{ i35, i8 }>]* @bara, i32 0, i32 0, i32 0 )            ; <i35> [#uses=1]
-        %tmp4 = load i35* getelementptr ([2 x <{ i35, i8 }>]* @bara, i32 0, i32 1, i32 0)           ; <i35> [#uses=1]
+        %tmp = load i35, i35* getelementptr([2 x <{ i35, i8 }>], [2 x <{ i35, i8 }>]* @bara, i32 0, i32 0, i32 0 )            ; <i35> [#uses=1]
+        %tmp4 = load i35, i35* getelementptr ([2 x <{ i35, i8 }>], [2 x <{ i35, i8 }>]* @bara, i32 0, i32 1, i32 0)           ; <i35> [#uses=1]
         %tmp5 = add i35 %tmp4, %tmp             ; <i35> [#uses=1]
         ret i35 %tmp5
 }
diff --git a/test/JitListener/multiple.ll b/test/JitListener/multiple.ll
index ae5460802f30..2ba06ef1f0db 100644
--- a/test/JitListener/multiple.ll
+++ b/test/JitListener/multiple.ll
@@ -55,7 +55,7 @@ entry:
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
   call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !15, metadata !16), !dbg !17
-  %0 = load i32* %a.addr, align 4, !dbg !18
+  %0 = load i32, i32* %a.addr, align 4, !dbg !18
   ret i32 %0, !dbg !19
 }
 
@@ -69,7 +69,7 @@ entry:
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
   call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !20, metadata !16), !dbg !21
-  %0 = load i32* %a.addr, align 4, !dbg !22
+  %0 = load i32, i32* %a.addr, align 4, !dbg !22
   %cmp = icmp eq i32 %0, 0, !dbg !22
   br i1 %cmp, label %if.then, label %if.end, !dbg !24
 
@@ -78,13 +78,13 @@ if.then:                                          ; preds = %entry
   br label %return, !dbg !25
 
 if.end:                                           ; preds = %entry
-  %1 = load i32* %a.addr, align 4, !dbg !27
+  %1 = load i32, i32* %a.addr, align 4, !dbg !27
   %div = sdiv i32 100, %1, !dbg !28
   store i32 %div, i32* %retval, !dbg !29
   br label %return, !dbg !29
 
 return:                                           ; preds = %if.end, %if.then
-  %2 = load i32* %retval, !dbg !30
+  %2 = load i32, i32* %retval, !dbg !30
   ret i32 %2, !dbg !30
 }
 
@@ -95,7 +95,7 @@ entry:
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
   call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !31, metadata !16), !dbg !32
-  %0 = load i32* %a.addr, align 4, !dbg !33
+  %0 = load i32, i32* %a.addr, align 4, !dbg !33
   switch i32 %0, label %sw.default [
     i32 0, label %sw.bb
     i32 1, label %sw.bb1
@@ -114,7 +114,7 @@ sw.default:                                       ; preds = %entry
   br label %return, !dbg !38
 
 return:                                           ; preds = %sw.default, %sw.bb1, %sw.bb
-  %1 = load i32* %retval, !dbg !39
+  %1 = load i32, i32* %retval, !dbg !39
   ret i32 %1, !dbg !39
 }
 
@@ -125,43 +125,43 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!11, !12, !13}
 !llvm.ident = !{!14}
 
-!0 = !{!"0x11\0012\00clang version 3.6.0 (trunk)\000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [F:\users\akaylor\llvm-s\llvm\test\JitListener/multiple.c] [DW_LANG_C99]
-!1 = !{!"multiple.c", !"F:\5Cusers\5Cakaylor\5Cllvm-s\5Cllvm\5Ctest\5CJitListener"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.6.0 (trunk)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "multiple.c", directory: "F:\5Cusers\5Cakaylor\5Cllvm-s\5Cllvm\5Ctest\5CJitListener")
 !2 = !{}
 !3 = !{!4, !9, !10}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\000\00256\000\001", !1, !5, !6, null, i32 (i32)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}                               ; [ DW_TAG_file_type ] [F:\users\akaylor\llvm-s\llvm\test\JitListener/multiple.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 (i32)* @foo, variables: !2)
+!5 = !DIFile(filename: "multiple.c", directory: "F:CusersCakaylorCllvm-sCllvmCtestCJitListener")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x2e\00bar\00bar\00\005\000\001\000\000\00256\000\005", !1, !5, !6, null, i32 (i32)* @bar, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [bar]
-!10 = !{!"0x2e\00fubar\00fubar\00\0012\000\001\000\000\00256\000\0012", !1, !5, !6, null, i32 (i32)* @fubar, null, null, !2} ; [ DW_TAG_subprogram ] [line 12] [def] [fubar]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DISubprogram(name: "bar", line: 5, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, function: i32 (i32)* @bar, variables: !2)
+!10 = !DISubprogram(name: "fubar", line: 12, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 12, file: !1, scope: !5, type: !6, function: i32 (i32)* @fubar, variables: !2)
 !11 = !{i32 2, !"Dwarf Version", i32 4}
-!12 = !{i32 2, !"Debug Info Version", i32 2}
+!12 = !{i32 2, !"Debug Info Version", i32 3}
 !13 = !{i32 1, !"PIC Level", i32 2}
 !14 = !{!"clang version 3.6.0 (trunk)"}
-!15 = !{!"0x101\00a\0016777217\000", !4, !5, !8}  ; [ DW_TAG_arg_variable ] [a] [line 1]
-!16 = !{!"0x102"}                                 ; [ DW_TAG_expression ]
-!17 = !MDLocation(line: 1, column: 13, scope: !4)
-!18 = !MDLocation(line: 2, column: 10, scope: !4)
-!19 = !MDLocation(line: 2, column: 3, scope: !4)
-!20 = !{!"0x101\00a\0016777221\000", !9, !5, !8}  ; [ DW_TAG_arg_variable ] [a] [line 5]
-!21 = !MDLocation(line: 5, column: 13, scope: !9)
-!22 = !MDLocation(line: 6, column: 7, scope: !23)
-!23 = !{!"0xb\006\007\000", !1, !9}               ; [ DW_TAG_lexical_block ] [F:\users\akaylor\llvm-s\llvm\test\JitListener/multiple.c]
-!24 = !MDLocation(line: 6, column: 7, scope: !9)
-!25 = !MDLocation(line: 7, column: 5, scope: !26)
-!26 = !{!"0xb\006\0015\001", !1, !23}             ; [ DW_TAG_lexical_block ] [F:\users\akaylor\llvm-s\llvm\test\JitListener/multiple.c]
-!27 = !MDLocation(line: 9, column: 14, scope: !9)
-!28 = !MDLocation(line: 9, column: 10, scope: !9)
-!29 = !MDLocation(line: 9, column: 3, scope: !9)
-!30 = !MDLocation(line: 10, column: 1, scope: !9)
-!31 = !{!"0x101\00a\0016777228\000", !10, !5, !8} ; [ DW_TAG_arg_variable ] [a] [line 12]
-!32 = !MDLocation(line: 12, column: 15, scope: !10)
-!33 = !MDLocation(line: 13, column: 11, scope: !10)
-!34 = !MDLocation(line: 13, column: 3, scope: !10)
-!35 = !MDLocation(line: 15, column: 7, scope: !36)
-!36 = !{!"0xb\0013\0014\002", !1, !10}            ; [ DW_TAG_lexical_block ] [F:\users\akaylor\llvm-s\llvm\test\JitListener/multiple.c]
-!37 = !MDLocation(line: 17, column: 7, scope: !36)
-!38 = !MDLocation(line: 19, column: 7, scope: !36)
-!39 = !MDLocation(line: 21, column: 1, scope: !10)
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 1, arg: 1, scope: !4, file: !5, type: !8)
+!16 = !DIExpression()
+!17 = !DILocation(line: 1, column: 13, scope: !4)
+!18 = !DILocation(line: 2, column: 10, scope: !4)
+!19 = !DILocation(line: 2, column: 3, scope: !4)
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 5, arg: 1, scope: !9, file: !5, type: !8)
+!21 = !DILocation(line: 5, column: 13, scope: !9)
+!22 = !DILocation(line: 6, column: 7, scope: !23)
+!23 = distinct !DILexicalBlock(line: 6, column: 7, file: !1, scope: !9)
+!24 = !DILocation(line: 6, column: 7, scope: !9)
+!25 = !DILocation(line: 7, column: 5, scope: !26)
+!26 = distinct !DILexicalBlock(line: 6, column: 15, file: !1, scope: !23)
+!27 = !DILocation(line: 9, column: 14, scope: !9)
+!28 = !DILocation(line: 9, column: 10, scope: !9)
+!29 = !DILocation(line: 9, column: 3, scope: !9)
+!30 = !DILocation(line: 10, column: 1, scope: !9)
+!31 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 12, arg: 1, scope: !10, file: !5, type: !8)
+!32 = !DILocation(line: 12, column: 15, scope: !10)
+!33 = !DILocation(line: 13, column: 11, scope: !10)
+!34 = !DILocation(line: 13, column: 3, scope: !10)
+!35 = !DILocation(line: 15, column: 7, scope: !36)
+!36 = distinct !DILexicalBlock(line: 13, column: 14, file: !1, scope: !10)
+!37 = !DILocation(line: 17, column: 7, scope: !36)
+!38 = !DILocation(line: 19, column: 7, scope: !36)
+!39 = !DILocation(line: 21, column: 1, scope: !10)
diff --git a/test/JitListener/simple.ll b/test/JitListener/simple.ll
index 1732170a9654..d98eef54e4ac 100644
--- a/test/JitListener/simple.ll
+++ b/test/JitListener/simple.ll
@@ -21,7 +21,7 @@ entry:
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
   call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !12, metadata !13), !dbg !14
-  %0 = load i32* %a.addr, align 4, !dbg !15
+  %0 = load i32, i32* %a.addr, align 4, !dbg !15
   ret i32 %0, !dbg !16
 }
 
@@ -35,20 +35,20 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!9, !10}
 !llvm.ident = !{!11}
 
-!0 = !{!"0x11\0012\00clang version 3.6.0 (trunk)\000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [F:\users\akaylor\llvm-s\llvm\test\JitListener/simple.c] [DW_LANG_C99]
-!1 = !{!"simple.c", !"F:\5Cusers\5Cakaylor\5Cllvm-s\5Cllvm\5Ctest\5CJitListener"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.6.0 (trunk)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "simple.c", directory: "F:\5Cusers\5Cakaylor\5Cllvm-s\5Cllvm\5Ctest\5CJitListener")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\000\00256\000\001", !1, !5, !6, null, i32 (i32)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}                               ; [ DW_TAG_file_type ] [F:\users\akaylor\llvm-s\llvm\test\JitListener/simple.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 (i32)* @foo, variables: !2)
+!5 = !DIFile(filename: "simple.c", directory: "F:CusersCakaylorCllvm-sCllvmCtestCJitListener")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 4}
-!10 = !{i32 2, !"Debug Info Version", i32 2}
+!10 = !{i32 2, !"Debug Info Version", i32 3}
 !11 = !{!"clang version 3.6.0 (trunk)"}
-!12 = !{!"0x101\00a\0016777217\000", !4, !5, !8}  ; [ DW_TAG_arg_variable ] [a] [line 1]
-!13 = !{!"0x102"}                                 ; [ DW_TAG_expression ]
-!14 = !MDLocation(line: 1, column: 13, scope: !4)
-!15 = !MDLocation(line: 2, column: 10, scope: !4)
-!16 = !MDLocation(line: 2, column: 3, scope: !4)
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 1, arg: 1, scope: !4, file: !5, type: !8)
+!13 = !DIExpression()
+!14 = !DILocation(line: 1, column: 13, scope: !4)
+!15 = !DILocation(line: 2, column: 10, scope: !4)
+!16 = !DILocation(line: 2, column: 3, scope: !4)
diff --git a/test/LTO/ARM/inline-asm.ll b/test/LTO/ARM/inline-asm.ll
new file mode 100644
index 000000000000..23fb90457c14
--- /dev/null
+++ b/test/LTO/ARM/inline-asm.ll
@@ -0,0 +1,9 @@
+; Check that we don't crash on target-specific inline asm directives.
+;
+; RUN: llvm-as < %s > %t
+; RUN: llvm-lto -o /dev/null %t -mcpu armv4t
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv4t-unknown-linux"
+
+module asm ".fnstart"
diff --git a/test/LTO/ARM/lit.local.cfg b/test/LTO/ARM/lit.local.cfg
new file mode 100644
index 000000000000..20e19aeb06f9
--- /dev/null
+++ b/test/LTO/ARM/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'ARM' in config.root.targets:
+  config.unsupported = True
diff --git a/test/LTO/ARM/runtime-library-subtarget.ll b/test/LTO/ARM/runtime-library-subtarget.ll
new file mode 100644
index 000000000000..aab1d90ea3b9
--- /dev/null
+++ b/test/LTO/ARM/runtime-library-subtarget.ll
@@ -0,0 +1,18 @@
+; Check that user-defined runtime library function __addsf3vfp is not removed
+;
+; RUN: llvm-as <%s >%t1
+; RUN: llvm-lto -o %t2 %t1 -mcpu arm1176jz-s
+; RUN: llvm-nm %t2 | FileCheck %s
+
+target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7-apple-ios"
+
+; CHECK: ___addsf3vfp
+
+define float @__addsf3vfp(float %a, float %b) #0 {
+entry:
+  %add = fadd float %a, %b
+  ret float %add
+}
+
+attributes #0 = { "target-cpu"="arm1176jzf-s"}
diff --git a/test/LTO/Inputs/bcsection.macho.s b/test/LTO/X86/Inputs/bcsection.macho.s
index cb7fe03b3e73..cb7fe03b3e73 100644
--- a/test/LTO/Inputs/bcsection.macho.s
+++ b/test/LTO/X86/Inputs/bcsection.macho.s
diff --git a/test/LTO/Inputs/bcsection.s b/test/LTO/X86/Inputs/bcsection.s
index ede1e5c532dd..ede1e5c532dd 100644
--- a/test/LTO/Inputs/bcsection.s
+++ b/test/LTO/X86/Inputs/bcsection.s
diff --git a/test/LTO/Inputs/invalid.ll.bc b/test/LTO/X86/Inputs/invalid.ll.bc
index a85c3644b3ab..a85c3644b3ab 100644
--- a/test/LTO/Inputs/invalid.ll.bc
+++ b/test/LTO/X86/Inputs/invalid.ll.bc
diff --git a/test/LTO/Inputs/list-symbols.ll b/test/LTO/X86/Inputs/list-symbols.ll
index 9443d535503a..9443d535503a 100644
--- a/test/LTO/Inputs/list-symbols.ll
+++ b/test/LTO/X86/Inputs/list-symbols.ll
diff --git a/test/LTO/attrs.ll b/test/LTO/X86/attrs.ll
index d1967470cdd3..d1967470cdd3 100644
--- a/test/LTO/attrs.ll
+++ b/test/LTO/X86/attrs.ll
diff --git a/test/LTO/bcsection.ll b/test/LTO/X86/bcsection.ll
index e65ade623536..e65ade623536 100644
--- a/test/LTO/bcsection.ll
+++ b/test/LTO/X86/bcsection.ll
diff --git a/test/LTO/X86/cfi_endproc.ll b/test/LTO/X86/cfi_endproc.ll
new file mode 100644
index 000000000000..57d822b047e3
--- /dev/null
+++ b/test/LTO/X86/cfi_endproc.ll
@@ -0,0 +1,42 @@
+; RUN: llvm-as < %s >%t1
+; RUN: llvm-lto -o %t2 %t1
+; RUN: llvm-nm %t2 | FileCheck %s -check-prefix=NOEXPORT
+; RUN: llvm-lto -o %t3 -exported-symbol=main %t1
+; RUN: llvm-nm %t3 | FileCheck %s -check-prefix=EXPORT
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+module asm ".text"
+module asm ".align 16, 0x90"
+module asm ".type PR14512, @function"
+module asm "PR14512:.cfi_startproc"
+module asm "ret"
+module asm ".cfi_endproc"
+
+declare void @PR14512()
+
+; Without -exported-symbol, main should be eliminated by LTO.
+; With -exported-symbol=main, main should be preserved by LTO.
+define i32 @main(i32 %argc, i8** %argv) {
+; NOEXPORT-NOT: main
+; EXPORT: main
+  call void @PR14512()
+  ret i32 0
+}
+
+; RUN: llvm-lto -o %t -dso-symbol=zed1 -dso-symbol=zed2 %t1 -O0
+; RUN: llvm-nm %t | FileCheck %s -check-prefix=ZED1_AND_ZED2
+; ZED1_AND_ZED2: V zed1
+@zed1 = linkonce_odr global i32 42
+define i32* @get_zed1() {
+  ret i32* @zed1
+}
+
+; ZED1_AND_ZED2: d zed2
+@zed2 = linkonce_odr unnamed_addr global i32 42
+
+define i32 @useZed2() {
+  %x = load i32, i32* @zed2
+  ret i32 %x
+}
diff --git a/test/LTO/current-section.ll b/test/LTO/X86/current-section.ll
index f79b378318df..f79b378318df 100644
--- a/test/LTO/current-section.ll
+++ b/test/LTO/X86/current-section.ll
diff --git a/test/LTO/diagnostic-handler-remarks.ll b/test/LTO/X86/diagnostic-handler-remarks.ll
index 4da9101117ec..4da9101117ec 100644
--- a/test/LTO/diagnostic-handler-remarks.ll
+++ b/test/LTO/X86/diagnostic-handler-remarks.ll
diff --git a/test/LTO/invalid.ll b/test/LTO/X86/invalid.ll
index 5b6996d4ad35..5b6996d4ad35 100644
--- a/test/LTO/invalid.ll
+++ b/test/LTO/X86/invalid.ll
diff --git a/test/LTO/X86/keep-used-puts-during-instcombine.ll b/test/LTO/X86/keep-used-puts-during-instcombine.ll
new file mode 100644
index 000000000000..26249477ce24
--- /dev/null
+++ b/test/LTO/X86/keep-used-puts-during-instcombine.ll
@@ -0,0 +1,36 @@
+; RUN: opt -S -instcombine <%s | FileCheck %s
+; rdar://problem/16165191
+; llvm.compiler.used functions should not be renamed
+
+target triple = "x86_64-apple-darwin11"
+
+@llvm.compiler.used = appending global [1 x i8*] [
+  i8* bitcast (i32(i8*)* @puts to i8*)
+  ], section "llvm.metadata"
+@llvm.used = appending global [1 x i8*] [
+  i8* bitcast (i32(i32)* @uses_printf to i8*)
+  ], section "llvm.metadata"
+
+@str = private unnamed_addr constant [13 x i8] c"hello world\0A\00"
+
+define i32 @uses_printf(i32 %i) {
+entry:
+  %s = getelementptr [13 x i8], [13 x i8]* @str, i64 0, i64 0
+  call i32 (i8*, ...) @printf(i8* %s)
+  ret i32 0
+}
+
+define internal i32 @printf(i8* readonly nocapture %fmt, ...) {
+entry:
+  %ret = call i32 @bar(i8* %fmt)
+  ret i32 %ret
+}
+
+; CHECK: define {{.*}} @puts(
+define internal i32 @puts(i8* %s) {
+entry:
+  %ret = call i32 @bar(i8* %s)
+  ret i32 %ret
+}
+
+declare i32 @bar(i8*)
diff --git a/test/LTO/X86/linkonce_odr_func.ll b/test/LTO/X86/linkonce_odr_func.ll
new file mode 100644
index 000000000000..7fa6527f47c7
--- /dev/null
+++ b/test/LTO/X86/linkonce_odr_func.ll
@@ -0,0 +1,61 @@
+; RUN: llvm-as < %s >%t1
+; RUN: llvm-lto -o %t2 -dso-symbol=foo1 -dso-symbol=foo2 -dso-symbol=foo3 \
+; RUN:     -dso-symbol=foo4 -dso-symbol=v1 -dso-symbol=v2 %t1 -O0
+; RUN: llvm-nm %t2 | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; CHECK: t foo1
+define linkonce_odr void @foo1() noinline {
+  ret void
+}
+
+; CHECK: W foo2
+define linkonce_odr void @foo2() noinline {
+  ret void
+}
+
+; CHECK: t foo3
+define linkonce_odr void @foo3() noinline {
+  ret void
+}
+
+; CHECK: W foo4
+define linkonce_odr void @foo4() noinline {
+  ret void
+}
+
+; CHECK: r v1
+@v1 = linkonce_odr constant i32 32
+
+define i32 @useV1() {
+  %x = load i32, i32* @v1
+  ret i32 %x
+}
+
+; CHECK: V v2
+@v2 = linkonce_odr global i32 32
+
+define i32 @useV2() {
+  %x = load i32, i32* @v2
+  ret i32 %x
+}
+
+declare void @f(void()*)
+
+declare void @p()
+
+define void @bar() {
+bb0:
+  call void @foo1()
+  call void @f(void()* @foo2)
+  invoke void @foo3() to label %bb1 unwind label %clean
+bb1:
+  invoke void @f(void()* @foo4) to label %bb2 unwind label %clean
+bb2:
+  ret void
+clean:
+  landingpad {i32, i32} personality void()* @p cleanup
+  ret void
+}
diff --git a/test/LTO/list-symbols.ll b/test/LTO/X86/list-symbols.ll
index 41b7d00deecc..41b7d00deecc 100644
--- a/test/LTO/list-symbols.ll
+++ b/test/LTO/X86/list-symbols.ll
diff --git a/test/LTO/lit.local.cfg b/test/LTO/X86/lit.local.cfg
index afde89be896d..afde89be896d 100644
--- a/test/LTO/lit.local.cfg
+++ b/test/LTO/X86/lit.local.cfg
diff --git a/test/LTO/X86/no-undefined-puts-when-implemented.ll b/test/LTO/X86/no-undefined-puts-when-implemented.ll
new file mode 100644
index 000000000000..132ec671d5ba
--- /dev/null
+++ b/test/LTO/X86/no-undefined-puts-when-implemented.ll
@@ -0,0 +1,40 @@
+; RUN: llvm-as <%s >%t1
+; RUN: llvm-lto -exported-symbol=_uses_puts -exported-symbol=_uses_printf -o - %t1 | \
+; RUN: llvm-nm - | \
+; RUN: FileCheck %s
+; rdar://problem/16165191
+; runtime library implementations should not be renamed
+
+target triple = "x86_64-apple-darwin11"
+
+@str = private unnamed_addr constant [13 x i8] c"hello world\0A\00"
+
+; CHECK-NOT: U _puts
+; CHECK: T _uses_printf
+; CHECK: T _uses_puts
+define i32 @uses_puts(i32 %i) {
+entry:
+  %s = call i8* @foo(i32 %i)
+  %ret = call i32 @puts(i8* %s)
+  ret i32 %ret
+}
+define i32 @uses_printf(i32 %i) {
+entry:
+  %s = getelementptr [13 x i8], [13 x i8]* @str, i64 0, i64 0
+  call i32 (i8*, ...) @printf(i8* %s)
+  ret i32 0
+}
+
+define hidden i32 @printf(i8* readonly nocapture %fmt, ...) {
+entry:
+  %ret = call i32 @bar(i8* %fmt)
+  ret i32 %ret
+}
+define hidden i32 @puts(i8* %s) {
+entry:
+  %ret = call i32 @bar(i8* %s)
+  ret i32 %ret
+}
+
+declare i8* @foo(i32)
+declare i32 @bar(i8*)
diff --git a/test/LTO/private-symbol.ll b/test/LTO/X86/private-symbol.ll
index e13a393442d3..e13a393442d3 100644
--- a/test/LTO/private-symbol.ll
+++ b/test/LTO/X86/private-symbol.ll
diff --git a/test/LTO/runtime-library.ll b/test/LTO/X86/runtime-library.ll
index 76fc6f0cc47b..76fc6f0cc47b 100644
--- a/test/LTO/runtime-library.ll
+++ b/test/LTO/X86/runtime-library.ll
diff --git a/test/LTO/X86/set-merged.ll b/test/LTO/X86/set-merged.ll
new file mode 100644
index 000000000000..aaafc5e912a4
--- /dev/null
+++ b/test/LTO/X86/set-merged.ll
@@ -0,0 +1,36 @@
+; RUN: llvm-as < %s >%t1
+; RUN: llvm-lto -exported-symbol=_main -set-merged-module -o %t2 %t1
+; RUN: llvm-objdump -d %t2 | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+; CHECK: _main
+; CHECK: movl $132
+define i32 @_Z3fooi(i32 %a) {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4
+  %1 = load i32, i32* %a.addr, align 4
+  %call = call i32 @_Z4bar2i(i32 %1)
+  %add = add nsw i32 %0, %call
+  ret i32 %add
+}
+
+define i32 @_Z4bar2i(i32 %a) {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4
+  %mul = mul nsw i32 2, %0
+  ret i32 %mul
+}
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  %call = call i32 @_Z3fooi(i32 44)
+  ret i32 %call
+}
diff --git a/test/LTO/symver-asm.ll b/test/LTO/X86/symver-asm.ll
index 03dda2bedd96..03dda2bedd96 100644
--- a/test/LTO/symver-asm.ll
+++ b/test/LTO/X86/symver-asm.ll
diff --git a/test/LTO/triple-init.ll b/test/LTO/X86/triple-init.ll
index e0ad87967ba2..e0ad87967ba2 100644
--- a/test/LTO/triple-init.ll
+++ b/test/LTO/X86/triple-init.ll
diff --git a/test/LTO/cfi_endproc.ll b/test/LTO/cfi_endproc.ll
deleted file mode 100644
index 1a69bf60f54b..000000000000
--- a/test/LTO/cfi_endproc.ll
+++ /dev/null
@@ -1,42 +0,0 @@
-; RUN: llvm-as < %s >%t1
-; RUN: llvm-lto -o %t2 %t1
-; RUN: llvm-nm %t2 | FileCheck %s -check-prefix=NOEXPORT
-; RUN: llvm-lto -o %t3 -exported-symbol=main %t1
-; RUN: llvm-nm %t3 | FileCheck %s -check-prefix=EXPORT
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
-target triple = "x86_64-unknown-linux-gnu"
-
-module asm ".text"
-module asm ".align 16, 0x90"
-module asm ".type PR14512, @function"
-module asm "PR14512:.cfi_startproc"
-module asm "ret"
-module asm ".cfi_endproc"
-
-declare void @PR14512()
-
-; Without -exported-symbol, main should be eliminated by LTO.
-; With -exported-symbol=main, main should be preserved by LTO.
-define i32 @main(i32 %argc, i8** %argv) {
-; NOEXPORT-NOT: main
-; EXPORT: main
-  call void @PR14512()
-  ret i32 0
-}
-
-; RUN: llvm-lto -o %t -dso-symbol=zed1 -dso-symbol=zed2 %t1 -disable-opt
-; RUN: llvm-nm %t | FileCheck %s -check-prefix=ZED1_AND_ZED2
-; ZED1_AND_ZED2: V zed1
-@zed1 = linkonce_odr global i32 42
-define i32* @get_zed1() {
-  ret i32* @zed1
-}
-
-; ZED1_AND_ZED2: d zed2
-@zed2 = linkonce_odr unnamed_addr global i32 42
-
-define i32 @useZed2() {
-  %x = load i32* @zed2
-  ret i32 %x
-}
diff --git a/test/LTO/jump-table-type.ll b/test/LTO/jump-table-type.ll
deleted file mode 100644
index a806c303f8c5..000000000000
--- a/test/LTO/jump-table-type.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; RUN: llvm-as <%s >%t1
-; RUN: llvm-lto -o %t2 %t1 -jump-table-type=arity
-; RUN: llvm-nm %t2 | FileCheck %s
-
-; CHECK: t __llvm_jump_instr_table_0_1
-; CHECK: t __llvm_jump_instr_table_1_1
-
-target triple = "x86_64-unknown-linux-gnu"
-
-define i32 @g(i32 %a) unnamed_addr jumptable {
-  ret i32 %a
-}
-
-define i32 @f() unnamed_addr jumptable {
-  ret i32 0
-}
-
-define i32 @main() {
-  ret i32 0
-}
-
-@llvm.used = appending global [2 x i8*]  [i8* bitcast (i32(i32)* @g to i8*),
-                                          i8* bitcast (i32()* @f to i8*)]
diff --git a/test/LTO/keep-used-puts-during-instcombine.ll b/test/LTO/keep-used-puts-during-instcombine.ll
deleted file mode 100644
index 69ce3ee3fae5..000000000000
--- a/test/LTO/keep-used-puts-during-instcombine.ll
+++ /dev/null
@@ -1,36 +0,0 @@
-; RUN: opt -S -instcombine <%s | FileCheck %s
-; rdar://problem/16165191
-; llvm.compiler.used functions should not be renamed
-
-target triple = "x86_64-apple-darwin11"
-
-@llvm.compiler.used = appending global [1 x i8*] [
-  i8* bitcast (i32(i8*)* @puts to i8*)
-  ], section "llvm.metadata"
-@llvm.used = appending global [1 x i8*] [
-  i8* bitcast (i32(i32)* @uses_printf to i8*)
-  ], section "llvm.metadata"
-
-@str = private unnamed_addr constant [13 x i8] c"hello world\0A\00"
-
-define i32 @uses_printf(i32 %i) {
-entry:
-  %s = getelementptr [13 x i8]* @str, i64 0, i64 0
-  call i32 (i8*, ...)* @printf(i8* %s)
-  ret i32 0
-}
-
-define internal i32 @printf(i8* readonly nocapture %fmt, ...) {
-entry:
-  %ret = call i32 @bar(i8* %fmt)
-  ret i32 %ret
-}
-
-; CHECK: define {{.*}} @puts(
-define internal i32 @puts(i8* %s) {
-entry:
-  %ret = call i32 @bar(i8* %s)
-  ret i32 %ret
-}
-
-declare i32 @bar(i8*)
diff --git a/test/LTO/linkonce_odr_func.ll b/test/LTO/linkonce_odr_func.ll
deleted file mode 100644
index 48da7953885f..000000000000
--- a/test/LTO/linkonce_odr_func.ll
+++ /dev/null
@@ -1,61 +0,0 @@
-; RUN: llvm-as < %s >%t1
-; RUN: llvm-lto -o %t2 -dso-symbol=foo1 -dso-symbol=foo2 -dso-symbol=foo3 \
-; RUN:     -dso-symbol=foo4 -dso-symbol=v1 -dso-symbol=v2 %t1 -disable-opt
-; RUN: llvm-nm %t2 | FileCheck %s
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
-target triple = "x86_64-unknown-linux-gnu"
-
-; CHECK: t foo1
-define linkonce_odr void @foo1() noinline {
-  ret void
-}
-
-; CHECK: W foo2
-define linkonce_odr void @foo2() noinline {
-  ret void
-}
-
-; CHECK: t foo3
-define linkonce_odr void @foo3() noinline {
-  ret void
-}
-
-; CHECK: W foo4
-define linkonce_odr void @foo4() noinline {
-  ret void
-}
-
-; CHECK: r v1
-@v1 = linkonce_odr constant i32 32
-
-define i32 @useV1() {
-  %x = load i32* @v1
-  ret i32 %x
-}
-
-; CHECK: V v2
-@v2 = linkonce_odr global i32 32
-
-define i32 @useV2() {
-  %x = load i32* @v2
-  ret i32 %x
-}
-
-declare void @f(void()*)
-
-declare void @p()
-
-define void @bar() {
-bb0:
-  call void @foo1()
-  call void @f(void()* @foo2)
-  invoke void @foo3() to label %bb1 unwind label %clean
-bb1:
-  invoke void @f(void()* @foo4) to label %bb2 unwind label %clean
-bb2:
-  ret void
-clean:
-  landingpad {i32, i32} personality void()* @p cleanup
-  ret void
-}
diff --git a/test/LTO/no-undefined-puts-when-implemented.ll b/test/LTO/no-undefined-puts-when-implemented.ll
deleted file mode 100644
index 29db8a63d1dd..000000000000
--- a/test/LTO/no-undefined-puts-when-implemented.ll
+++ /dev/null
@@ -1,40 +0,0 @@
-; RUN: llvm-as <%s >%t1
-; RUN: llvm-lto -exported-symbol=_uses_puts -exported-symbol=_uses_printf -o - %t1 | \
-; RUN: llvm-nm - | \
-; RUN: FileCheck %s
-; rdar://problem/16165191
-; runtime library implementations should not be renamed
-
-target triple = "x86_64-apple-darwin11"
-
-@str = private unnamed_addr constant [13 x i8] c"hello world\0A\00"
-
-; CHECK-NOT: U _puts
-; CHECK: T _uses_printf
-; CHECK: T _uses_puts
-define i32 @uses_puts(i32 %i) {
-entry:
-  %s = call i8* @foo(i32 %i)
-  %ret = call i32 @puts(i8* %s)
-  ret i32 %ret
-}
-define i32 @uses_printf(i32 %i) {
-entry:
-  %s = getelementptr [13 x i8]* @str, i64 0, i64 0
-  call i32 (i8*, ...)* @printf(i8* %s)
-  ret i32 0
-}
-
-define hidden i32 @printf(i8* readonly nocapture %fmt, ...) {
-entry:
-  %ret = call i32 @bar(i8* %fmt)
-  ret i32 %ret
-}
-define hidden i32 @puts(i8* %s) {
-entry:
-  %ret = call i32 @bar(i8* %s)
-  ret i32 %ret
-}
-
-declare i8* @foo(i32)
-declare i32 @bar(i8*)
diff --git a/test/Linker/2002-08-20-ConstantExpr.ll b/test/Linker/2002-08-20-ConstantExpr.ll
index 5672014ff663..f8217930678a 100644
--- a/test/Linker/2002-08-20-ConstantExpr.ll
+++ b/test/Linker/2002-08-20-ConstantExpr.ll
@@ -5,5 +5,5 @@
 ; RUN: llvm-link %t.LinkTest.bc %t.bc
 
 @work = global i32 4		; <i32*> [#uses=1]
-@test = global i32* getelementptr (i32* @work, i64 1)		; <i32**> [#uses=0]
+@test = global i32* getelementptr (i32, i32* @work, i64 1)		; <i32**> [#uses=0]
 
diff --git a/test/Linker/2004-05-07-TypeResolution1.ll b/test/Linker/2004-05-07-TypeResolution1.ll
index 4cff9ace430a..b8ce2d9baedb 100644
--- a/test/Linker/2004-05-07-TypeResolution1.ll
+++ b/test/Linker/2004-05-07-TypeResolution1.ll
@@ -30,6 +30,6 @@ declare void @func(%struct2*)
 
 define void @tty_init() {
 entry:
-	store volatile void (%struct2*)* @func, void (%struct2*)** getelementptr (%struct1* @driver1, i64 0, i32 1)
+	store volatile void (%struct2*)* @func, void (%struct2*)** getelementptr (%struct1, %struct1* @driver1, i64 0, i32 1)
 	ret void
 }
diff --git a/test/Linker/2004-05-07-TypeResolution2.ll b/test/Linker/2004-05-07-TypeResolution2.ll
index 380712717817..2b672761458d 100644
--- a/test/Linker/2004-05-07-TypeResolution2.ll
+++ b/test/Linker/2004-05-07-TypeResolution2.ll
@@ -8,8 +8,8 @@ target datalayout = "e-p:32:32"
 
 define internal void @f1(%struct1* %tty) {
 loopentry.preheader:
-	%tmp.2.i.i = getelementptr %struct1* %tty, i64 0, i32 1		; <void (%struct2*)**> [#uses=1]
-	%tmp.3.i.i = load volatile void (%struct2*)** %tmp.2.i.i		; <void (%struct2*)*> [#uses=0]
+	%tmp.2.i.i = getelementptr %struct1, %struct1* %tty, i64 0, i32 1		; <void (%struct2*)**> [#uses=1]
+	%tmp.3.i.i = load volatile void (%struct2*)*, void (%struct2*)** %tmp.2.i.i		; <void (%struct2*)*> [#uses=0]
 	ret void
 }
 
diff --git a/test/Linker/2008-03-05-AliasReference.ll b/test/Linker/2008-03-05-AliasReference.ll
index 8ce1ccb33857..078479424b02 100644
--- a/test/Linker/2008-03-05-AliasReference.ll
+++ b/test/Linker/2008-03-05-AliasReference.ll
@@ -12,6 +12,6 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @baz() nounwind  {
 entry:
-	%tmp1 = load i32* @bar, align 4		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* @bar, align 4		; <i32> [#uses=1]
 	ret i32 %tmp1
 }
diff --git a/test/Linker/2009-09-03-mdnode.ll b/test/Linker/2009-09-03-mdnode.ll
index 1f308e77e9dd..ec444d316b78 100644
--- a/test/Linker/2009-09-03-mdnode.ll
+++ b/test/Linker/2009-09-03-mdnode.ll
@@ -14,7 +14,7 @@ entry:
   br label %return
 
 return:                                           ; preds = %entry
-  %0 = load i32* %retval                          ; <i32> [#uses=1]
+  %0 = load i32, i32* %retval                          ; <i32> [#uses=1]
   call void @llvm.dbg.stoppoint(i32 5, i32 1, metadata !1)
   call void @llvm.dbg.region.end(metadata !0)
   ret i32 %0
@@ -26,6 +26,6 @@ declare void @llvm.dbg.stoppoint(i32, i32, metadata) nounwind readnone
 
 declare void @llvm.dbg.region.end(metadata) nounwind readnone
 
-!0 = !{!"0x2e\00main\00main\00main\002\000\001\000\006\000\000\000", i32 0, !1, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x11\0012\00ellcc 0.1.0\001\00\000\00\000", !2, null, null, null, null, null} ; [ DW_TAG_compile_unit ]
-!2 = !{!"a.c", !"/home/rich/ellcc/test/source"}
+!0 = !DISubprogram(name: "main", linkageName: "main", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !1)
+!1 = !DICompileUnit(language: DW_LANG_C99, producer: "ellcc 0.1.0", isOptimized: true, emissionKind: 0, file: !2)
+!2 = !DIFile(filename: "a.c", directory: "/home/rich/ellcc/test/source")
diff --git a/test/Linker/2009-09-03-mdnode2.ll b/test/Linker/2009-09-03-mdnode2.ll
index 68e329432a0a..d9d52680b7b0 100644
--- a/test/Linker/2009-09-03-mdnode2.ll
+++ b/test/Linker/2009-09-03-mdnode2.ll
@@ -9,7 +9,7 @@ entry:
   br label %return
 
 return:                                           ; preds = %entry
-  %0 = load i32* %retval                          ; <i32> [#uses=1]
+  %0 = load i32, i32* %retval                          ; <i32> [#uses=1]
   call void @llvm.dbg.stoppoint(i32 3, i32 1, metadata !1)
   call void @llvm.dbg.region.end(metadata !0)
   ret i32 %0
@@ -21,6 +21,6 @@ declare void @llvm.dbg.stoppoint(i32, i32, metadata) nounwind readnone
 
 declare void @llvm.dbg.region.end(metadata) nounwind readnone
 
-!0 = !{!"0x2e\00f\00f\00f\001\000\001\000\006\000\000\000", i32 0, !1, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x11\0012\00ellcc 0.1.0\001\00\000\00\000", !2, null, null, null, null, null} ; [ DW_TAG_compile_unit ]
-!2 = !{!"b.c", !"/home/rich/ellcc/test/source"}
+!0 = !DISubprogram(name: "f", linkageName: "f", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !1)
+!1 = !DICompileUnit(language: DW_LANG_C99, producer: "ellcc 0.1.0", isOptimized: true, emissionKind: 0, file: !2)
+!2 = !DIFile(filename: "b.c", directory: "/home/rich/ellcc/test/source")
diff --git a/test/Linker/2011-08-04-DebugLoc.ll b/test/Linker/2011-08-04-DebugLoc.ll
index 85b9e17c5666..710ddf7774ff 100644
--- a/test/Linker/2011-08-04-DebugLoc.ll
+++ b/test/Linker/2011-08-04-DebugLoc.ll
@@ -17,15 +17,15 @@ define i32 @foo() nounwind ssp {
 !llvm.module.flags = !{!11}
 !llvm.dbg.sp = !{!1}
 
-!0 = !{!"0x11\0012\00Apple clang version 3.0 (tags/Apple/clang-209.11) (based on LLVM 3.0svn)\001\00\000\00\000", !8, !9, !9, !10, null, null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"0x2e\00foo\00foo\00\002\000\001\000\006\000\000\000", !8, !2, !3, null, i32 ()* @foo, null, null, null} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 0] [foo]
-!2 = !{!"0x29", !8} ; [ DW_TAG_file_type ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !8, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "Apple clang version 3.0 (tags/Apple/clang-209.11) (based on LLVM 3.0svn)", isOptimized: true, emissionKind: 0, file: !8, enums: !9, retainedTypes: !9, subprograms: !10)
+!1 = !DISubprogram(name: "foo", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !8, scope: !2, type: !3, function: i32 ()* @foo)
+!2 = !DIFile(filename: "a.c", directory: "/private/tmp")
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ]
-!6 = !MDLocation(line: 2, column: 13, scope: !7)
-!7 = !{!"0xb\002\0011\000", !8, !1} ; [ DW_TAG_lexical_block ]
-!8 = !{!"a.c", !"/private/tmp"}
-!9 = !{i32 0}
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DILocation(line: 2, column: 13, scope: !7)
+!7 = distinct !DILexicalBlock(line: 2, column: 11, file: !8, scope: !1)
+!8 = !DIFile(filename: "a.c", directory: "/private/tmp")
+!9 = !{}
 !10 = !{!1}
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!11 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/2011-08-04-DebugLoc2.ll b/test/Linker/2011-08-04-DebugLoc2.ll
index a3cd00100920..bc524dae91de 100644
--- a/test/Linker/2011-08-04-DebugLoc2.ll
+++ b/test/Linker/2011-08-04-DebugLoc2.ll
@@ -14,15 +14,15 @@ define i32 @bar() nounwind ssp {
 !llvm.module.flags = !{!11}
 !llvm.dbg.sp = !{!1}
 
-!0 = !{!"0x11\0012\00Apple clang version 3.0 (tags/Apple/clang-209.11) (based on LLVM 3.0svn)\001\00\000\00\000", !8, !9, !9, !10, null, null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"0x2e\00bar\00bar\00\001\000\001\000\006\000\000\000", !8, !2, !3, null, i32 ()* @bar, null, null, null} ; [ DW_TAG_subprogram ] [line 1] [def] [scope 0] [bar]
-!2 = !{!"0x29", !8} ; [ DW_TAG_file_type ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !8, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "Apple clang version 3.0 (tags/Apple/clang-209.11) (based on LLVM 3.0svn)", isOptimized: true, emissionKind: 0, file: !8, enums: !9, retainedTypes: !9, subprograms: !10)
+!1 = !DISubprogram(name: "bar", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !8, scope: !2, type: !3, function: i32 ()* @bar)
+!2 = !DIFile(filename: "b.c", directory: "/private/tmp")
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ]
-!6 = !MDLocation(line: 1, column: 13, scope: !7)
-!7 = !{!"0xb\001\0011\000", !8, !1} ; [ DW_TAG_lexical_block ]
-!8 = !{!"b.c", !"/private/tmp"}
-!9 = !{i32 0}
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DILocation(line: 1, column: 13, scope: !7)
+!7 = distinct !DILexicalBlock(line: 1, column: 11, file: !8, scope: !1)
+!8 = !DIFile(filename: "b.c", directory: "/private/tmp")
+!9 = !{}
 !10 = !{!1}
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!11 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/2011-08-04-Metadata.ll b/test/Linker/2011-08-04-Metadata.ll
index da98f20e3f18..fc1af754abd4 100644
--- a/test/Linker/2011-08-04-Metadata.ll
+++ b/test/Linker/2011-08-04-Metadata.ll
@@ -2,8 +2,12 @@
 ; RUN: llvm-dis < %t.bc | FileCheck %s
 ; Test if internal global variable's debug info is merged appropriately or not.
 
-;CHECK:   !"0x34\00x\00x\00\002\001\001", !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, i32* @x}
-;CHECK:   !"0x34\00x\00x\00\001\001\001", !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, i32* @x1}
+; CHECK: !DIGlobalVariable(name: "x",
+; CHECK-NOT:               linkageName:
+; CHECK-SAME:              variable: i32* @x{{[,)]}}
+; CHECK: !DIGlobalVariable(name: "x",
+; CHECK-NOT:               linkageName:
+; CHECK-SAME:              variable: i32* @x.1{{[,)]}}
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-macosx10.7.0"
 
@@ -20,15 +24,15 @@ entry:
 !llvm.dbg.sp = !{!1}
 !llvm.dbg.gv = !{!5}
 
-!0 = !{!"0x11\0012\00clang version 3.0 ()\001\00\000\00\000", !9, !4, !4, !10, null, null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"0x2e\00foo\00foo\00\003\000\001\000\006\000\000\000", !9, !2, !3, null, void ()* @foo, null, null, null} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 0] [foo]
-!2 = !{!"0x29", !9} ; [ DW_TAG_file_type ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !9, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 ()", isOptimized: true, emissionKind: 0, file: !9, enums: !{}, retainedTypes: !{}, subprograms: !10)
+!1 = !DISubprogram(name: "foo", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !9, scope: !2, type: !3, function: void ()* @foo)
+!2 = !DIFile(filename: "/tmp/one.c", directory: "/Volumes/Lalgate/Slate/D")
+!3 = !DISubroutineType(types: !4)
 !4 = !{null}
-!5 = !{!"0x34\00x\00x\00\002\001\001", !0, !2, !6, i32* @x} ; [ DW_TAG_variable ]
-!6 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ]
-!7 = !MDLocation(line: 3, column: 14, scope: !8)
-!8 = !{!"0xb\003\0012\000", !9, !1} ; [ DW_TAG_lexical_block ]
-!9 = !{!"/tmp/one.c", !"/Volumes/Lalgate/Slate/D"}
+!5 = !DIGlobalVariable(name: "x", line: 2, isLocal: true, isDefinition: true, scope: !0, file: !2, type: !6, variable: i32* @x)
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!7 = !DILocation(line: 3, column: 14, scope: !8)
+!8 = distinct !DILexicalBlock(line: 3, column: 12, file: !9, scope: !1)
+!9 = !DIFile(filename: "/tmp/one.c", directory: "/Volumes/Lalgate/Slate/D")
 !10 = !{!1}
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!11 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/2011-08-04-Metadata2.ll b/test/Linker/2011-08-04-Metadata2.ll
index fb196d96df71..5eb231b2e364 100644
--- a/test/Linker/2011-08-04-Metadata2.ll
+++ b/test/Linker/2011-08-04-Metadata2.ll
@@ -19,15 +19,15 @@ entry:
 !llvm.dbg.sp = !{!1}
 !llvm.dbg.gv = !{!5}
 
-!0 = !{!"0x11\0012\00clang version 3.0 ()\001\00\000\00\000", !9, !4, !4, !10, null, null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"0x2e\00bar\00bar\00\002\000\001\000\006\000\000\000", !9, !2, !3, null, void ()* @bar, null, null, null} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 0] [bar]
-!2 = !{!"0x29", !9} ; [ DW_TAG_file_type ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !9, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 ()", isOptimized: true, emissionKind: 0, file: !9, enums: !{}, retainedTypes: !{}, subprograms: !10)
+!1 = !DISubprogram(name: "bar", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !9, scope: !2, type: !3, function: void ()* @bar)
+!2 = !DIFile(filename: "/tmp/two.c", directory: "/Volumes/Lalgate/Slate/D")
+!3 = !DISubroutineType(types: !4)
 !4 = !{null}
-!5 = !{!"0x34\00x\00x\00\001\001\001", !0, !2, !6, i32* @x} ; [ DW_TAG_variable ]
-!6 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ]
-!7 = !MDLocation(line: 2, column: 14, scope: !8)
-!8 = !{!"0xb\002\0012\000", !9, !1} ; [ DW_TAG_lexical_block ]
-!9 = !{!"/tmp/two.c", !"/Volumes/Lalgate/Slate/D"}
+!5 = !DIGlobalVariable(name: "x", line: 1, isLocal: true, isDefinition: true, scope: !0, file: !2, type: !6, variable: i32* @x)
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!7 = !DILocation(line: 2, column: 14, scope: !8)
+!8 = distinct !DILexicalBlock(line: 2, column: 12, file: !9, scope: !1)
+!9 = !DIFile(filename: "/tmp/two.c", directory: "/Volumes/Lalgate/Slate/D")
 !10 = !{!1}
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+!11 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/2011-08-18-unique-class-type.ll b/test/Linker/2011-08-18-unique-class-type.ll
index a8f13500a754..1692a90bf7e6 100644
--- a/test/Linker/2011-08-18-unique-class-type.ll
+++ b/test/Linker/2011-08-18-unique-class-type.ll
@@ -11,7 +11,7 @@ target triple = "x86_64-apple-macosx10.7.0"
 define void @_Z3fooN2N11AE() nounwind uwtable ssp {
 entry:
   %mya = alloca %"class.N1::A", align 1
-  call void @llvm.dbg.declare(metadata %"class.N1::A"* %mya, metadata !9, metadata !{!"0x102"}), !dbg !13
+  call void @llvm.dbg.declare(metadata %"class.N1::A"* %mya, metadata !9, metadata !DIExpression()), !dbg !13
   ret void, !dbg !14
 }
 
@@ -20,21 +20,21 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!18}
 
-!0 = !{!"0x11\004\00clang version 3.0 (trunk 137954)\001\00\000\00\000", !16, !2, !2, !3, !2, null} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.0 (trunk 137954)", isOptimized: true, emissionKind: 0, file: !16, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2)
 !1 = !{!2}
-!2 = !{i32 0}
+!2 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00foo\00foo\00_Z3fooN2N11AE\004\000\001\000\006\00256\000\000", !16, !6, !7, null, void ()* @_Z3fooN2N11AE, null, null, null} ; [ DW_TAG_subprogram ] [line 4] [def] [scope 0] [foo]
-!6 = !{!"0x29", !16} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", !16, !6, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "foo", linkageName: "_Z3fooN2N11AE", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !16, scope: !6, type: !7, function: void ()* @_Z3fooN2N11AE)
+!6 = !DIFile(filename: "n1.c", directory: "/private/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null}
-!9 = !{!"0x101\00mya\0016777220\000", !5, !6, !10} ; [ DW_TAG_arg_variable ]
-!10 = !{!"0x2\00A\003\008\008\000\000\000", !17, !11, null, !2, null, null, null} ; [ DW_TAG_class_type ] [A] [line 3, size 8, align 8, offset 0] [def] [from ]
-!11 = !{!"0x39\00N1\002", !17, null} ; [ DW_TAG_namespace ]
-!12 = !{!"0x29", !17} ; [ DW_TAG_file_type ]
-!13 = !MDLocation(line: 4, column: 12, scope: !5)
-!14 = !MDLocation(line: 4, column: 18, scope: !15)
-!15 = !{!"0xb\004\0017\000", !16, !5} ; [ DW_TAG_lexical_block ]
-!16 = !{!"n1.c", !"/private/tmp"}
-!17 = !{!"./n.h", !"/private/tmp"}
-!18 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "mya", line: 4, arg: 1, scope: !5, file: !6, type: !10)
+!10 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 3, size: 8, align: 8, file: !17, scope: !11, elements: !2)
+!11 = !DINamespace(name: "N1", line: 2, file: !17, scope: null)
+!12 = !DIFile(filename: "./n.h", directory: "/private/tmp")
+!13 = !DILocation(line: 4, column: 12, scope: !5)
+!14 = !DILocation(line: 4, column: 18, scope: !15)
+!15 = distinct !DILexicalBlock(line: 4, column: 17, file: !16, scope: !5)
+!16 = !DIFile(filename: "n1.c", directory: "/private/tmp")
+!17 = !DIFile(filename: "./n.h", directory: "/private/tmp")
+!18 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/2011-08-18-unique-class-type2.ll b/test/Linker/2011-08-18-unique-class-type2.ll
index dd0df5889ec6..1befb4deacc9 100644
--- a/test/Linker/2011-08-18-unique-class-type2.ll
+++ b/test/Linker/2011-08-18-unique-class-type2.ll
@@ -9,7 +9,7 @@ target triple = "x86_64-apple-macosx10.7.0"
 define void @_Z3barN2N11AE() nounwind uwtable ssp {
 entry:
   %youra = alloca %"class.N1::A", align 1
-  call void @llvm.dbg.declare(metadata %"class.N1::A"* %youra, metadata !9, metadata !{!"0x102"}), !dbg !13
+  call void @llvm.dbg.declare(metadata %"class.N1::A"* %youra, metadata !9, metadata !DIExpression()), !dbg !13
   ret void, !dbg !14
 }
 
@@ -18,21 +18,21 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!18}
 
-!0 = !{!"0x11\004\00clang version 3.0 (trunk 137954)\001\00\000\00\000", !16, !2, !2, !3, !2, null} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.0 (trunk 137954)", isOptimized: true, emissionKind: 0, file: !16, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2)
 !1 = !{!2}
-!2 = !{i32 0}
+!2 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00bar\00bar\00_Z3barN2N11AE\004\000\001\000\006\00256\000\000", i32 0, !6, !7, null, void ()* @_Z3barN2N11AE, null, null, null} ; [ DW_TAG_subprogram ] [line 4] [def] [scope 0] [bar]
-!6 = !{!"0x29", !16} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", !16, !6, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "bar", linkageName: "_Z3barN2N11AE", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scope: !6, type: !7, function: void ()* @_Z3barN2N11AE)
+!6 = !DIFile(filename: "n2.c", directory: "/private/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null}
-!9 = !{!"0x101\00youra\0016777220\000", !5, !6, !10} ; [ DW_TAG_arg_variable ]
-!10 = !{!"0x2\00A\003\008\008\000\000\000", !17, !11, null, !2, null, null, null} ; [ DW_TAG_class_type ] [A] [line 3, size 8, align 8, offset 0] [def] [from ]
-!11 = !{!"0x39\00N1\002", !17, null} ; [ DW_TAG_namespace ]
-!12 = !{!"0x29", !17} ; [ DW_TAG_file_type ]
-!13 = !MDLocation(line: 4, column: 12, scope: !5)
-!14 = !MDLocation(line: 4, column: 20, scope: !15)
-!15 = !{!"0xb\004\0019\000", !16, !5} ; [ DW_TAG_lexical_block ]
-!16 = !{!"n2.c", !"/private/tmp"}
-!17 = !{!"./n.h", !"/private/tmp"}
-!18 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "youra", line: 4, arg: 1, scope: !5, file: !6, type: !10)
+!10 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 3, size: 8, align: 8, file: !17, scope: !11, elements: !2)
+!11 = !DINamespace(name: "N1", line: 2, file: !17, scope: null)
+!12 = !DIFile(filename: "./n.h", directory: "/private/tmp")
+!13 = !DILocation(line: 4, column: 12, scope: !5)
+!14 = !DILocation(line: 4, column: 20, scope: !15)
+!15 = distinct !DILexicalBlock(line: 4, column: 19, file: !16, scope: !5)
+!16 = !DIFile(filename: "n2.c", directory: "/private/tmp")
+!17 = !DIFile(filename: "./n.h", directory: "/private/tmp")
+!18 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/2011-08-18-unique-debug-type.ll b/test/Linker/2011-08-18-unique-debug-type.ll
index c1b3a1d79395..b1da9354f8ce 100644
--- a/test/Linker/2011-08-18-unique-debug-type.ll
+++ b/test/Linker/2011-08-18-unique-debug-type.ll
@@ -1,6 +1,6 @@
 ; RUN: llvm-link %s %p/2011-08-18-unique-debug-type2.ll -S -o - | FileCheck %s
 ; Test to check only one MDNode for "int" after linking.
-; CHECK: !"0x24\00int\00{{.*}}"
+; CHECK: !DIBasicType(name: "int"
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-macosx10.7.0"
 
@@ -12,16 +12,16 @@ entry:
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!13}
 
-!0 = !{!"0x11\0012\00clang version 3.0 (trunk 137954)\001\00\000\00\000", !12, !2, !2, !3, !2, null} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 137954)", isOptimized: true, emissionKind: 0, file: !12, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2)
 !1 = !{!2}
-!2 = !{i32 0}
+!2 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\000\000\000", !12, !6, !7, null, i32 ()* @foo, null, null, null} ; [ DW_TAG_subprogram ] [line 1] [def] [scope 0] [foo]
-!6 = !{!"0x29", !12} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", !12, !6, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !12, scope: !6, type: !7, function: i32 ()* @foo)
+!6 = !DIFile(filename: "one.c", directory: "/private/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!10 = !MDLocation(line: 1, column: 13, scope: !11)
-!11 = !{!"0xb\001\0011\000", !12, !5} ; [ DW_TAG_lexical_block ]
-!12 = !{!"one.c", !"/private/tmp"}
-!13 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DILocation(line: 1, column: 13, scope: !11)
+!11 = distinct !DILexicalBlock(line: 1, column: 11, file: !12, scope: !5)
+!12 = !DIFile(filename: "one.c", directory: "/private/tmp")
+!13 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/2011-08-18-unique-debug-type2.ll b/test/Linker/2011-08-18-unique-debug-type2.ll
index 49c0a5cf6568..40958dabf880 100644
--- a/test/Linker/2011-08-18-unique-debug-type2.ll
+++ b/test/Linker/2011-08-18-unique-debug-type2.ll
@@ -12,16 +12,16 @@ entry:
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!13}
 
-!0 = !{!"0x11\0012\00clang version 3.0 (trunk 137954)\001\00\000\00\000", !12, !2, !2, !3, !2, null} ; [ DW_TAG_compile_unit ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 137954)", isOptimized: true, emissionKind: 0, file: !12, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2)
 !1 = !{!2}
-!2 = !{i32 0}
+!2 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00bar\00bar\00\001\000\001\000\006\000\000\000", !12, !6, !7, null, i32 ()* @bar, null, null, null} ; [ DW_TAG_subprogram ] [line 1] [def] [scope 0] [bar]
-!6 = !{!"0x29", !12} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", !12, !6, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "bar", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !12, scope: !6, type: !7, function: i32 ()* @bar)
+!6 = !DIFile(filename: "two.c", directory: "/private/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!10 = !MDLocation(line: 1, column: 13, scope: !11)
-!11 = !{!"0xb\001\0011\000", !12, !5} ; [ DW_TAG_lexical_block ]
-!12 = !{!"two.c", !"/private/tmp"}
-!13 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DILocation(line: 1, column: 13, scope: !11)
+!11 = distinct !DILexicalBlock(line: 1, column: 11, file: !12, scope: !5)
+!12 = !DIFile(filename: "two.c", directory: "/private/tmp")
+!13 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/2011-08-22-ResolveAlias.ll b/test/Linker/2011-08-22-ResolveAlias.ll
deleted file mode 100644
index d6df82d45cfc..000000000000
--- a/test/Linker/2011-08-22-ResolveAlias.ll
+++ /dev/null
@@ -1,89 +0,0 @@
-; PR10663
-; RUN: llvm-link %s %p/2011-08-22-ResolveAlias2.ll
-
-%union.pthread_attr_t = type { [56 x i8] }
-%union.pthread_mutex_t = type { [40 x i8] }
-%struct.timespec = type { i64, i64 }
-%union.pthread_mutexattr_t = type { [4 x i8] }
-%union.pthread_cond_t = type { [48 x i8] }
-
-@_ZL20__gthrw_pthread_oncePiPFvvE = weak alias i32 (i32*, void ()*)* @pthread_once
-@_ZL27__gthrw_pthread_getspecificj = weak alias i8* (i32)* @pthread_getspecific
-@_ZL27__gthrw_pthread_setspecificjPKv = weak alias i32 (i32, i8*)* @pthread_setspecific
-@_ZL22__gthrw_pthread_createPmPK14pthread_attr_tPFPvS3_ES3_ = weak alias i32 (i64*, %union.pthread_attr_t*, i8* (i8*)*, i8*)* @pthread_create
-@_ZL20__gthrw_pthread_joinmPPv = weak alias i32 (i64, i8**)* @pthread_join
-@_ZL21__gthrw_pthread_equalmm = weak alias i32 (i64, i64)* @pthread_equal
-@_ZL20__gthrw_pthread_selfv = weak alias i64 ()* @pthread_self
-@_ZL22__gthrw_pthread_detachm = weak alias i32 (i64)* @pthread_detach
-@_ZL22__gthrw_pthread_cancelm = weak alias i32 (i64)* @pthread_cancel
-@_ZL19__gthrw_sched_yieldv = weak alias i32 ()* @sched_yield
-@_ZL26__gthrw_pthread_mutex_lockP15pthread_mutex_t = weak alias i32 (%union.pthread_mutex_t*)* @pthread_mutex_lock
-@_ZL29__gthrw_pthread_mutex_trylockP15pthread_mutex_t = weak alias i32 (%union.pthread_mutex_t*)* @pthread_mutex_trylock
-@_ZL31__gthrw_pthread_mutex_timedlockP15pthread_mutex_tPK8timespec = weak alias i32 (%union.pthread_mutex_t*, %struct.timespec*)* @pthread_mutex_timedlock
-@_ZL28__gthrw_pthread_mutex_unlockP15pthread_mutex_t = weak alias i32 (%union.pthread_mutex_t*)* @pthread_mutex_unlock
-@_ZL26__gthrw_pthread_mutex_initP15pthread_mutex_tPK19pthread_mutexattr_t = weak alias i32 (%union.pthread_mutex_t*, %union.pthread_mutexattr_t*)* @pthread_mutex_init
-@_ZL29__gthrw_pthread_mutex_destroyP15pthread_mutex_t = weak alias i32 (%union.pthread_mutex_t*)* @pthread_mutex_destroy
-@_ZL30__gthrw_pthread_cond_broadcastP14pthread_cond_t = weak alias i32 (%union.pthread_cond_t*)* @pthread_cond_broadcast
-@_ZL27__gthrw_pthread_cond_signalP14pthread_cond_t = weak alias i32 (%union.pthread_cond_t*)* @pthread_cond_signal
-@_ZL25__gthrw_pthread_cond_waitP14pthread_cond_tP15pthread_mutex_t = weak alias i32 (%union.pthread_cond_t*, %union.pthread_mutex_t*)* @pthread_cond_wait
-@_ZL30__gthrw_pthread_cond_timedwaitP14pthread_cond_tP15pthread_mutex_tPK8timespec = weak alias i32 (%union.pthread_cond_t*, %union.pthread_mutex_t*, %struct.timespec*)* @pthread_cond_timedwait
-@_ZL28__gthrw_pthread_cond_destroyP14pthread_cond_t = weak alias i32 (%union.pthread_cond_t*)* @pthread_cond_destroy
-@_ZL26__gthrw_pthread_key_createPjPFvPvE = weak alias i32 (i32*, void (i8*)*)* @pthread_key_create
-@_ZL26__gthrw_pthread_key_deletej = weak alias i32 (i32)* @pthread_key_delete
-@_ZL30__gthrw_pthread_mutexattr_initP19pthread_mutexattr_t = weak alias i32 (%union.pthread_mutexattr_t*)* @pthread_mutexattr_init
-@_ZL33__gthrw_pthread_mutexattr_settypeP19pthread_mutexattr_ti = weak alias i32 (%union.pthread_mutexattr_t*, i32)* @pthread_mutexattr_settype
-@_ZL33__gthrw_pthread_mutexattr_destroyP19pthread_mutexattr_t = weak alias i32 (%union.pthread_mutexattr_t*)* @pthread_mutexattr_destroy
-
-declare extern_weak i32 @pthread_once(i32*, void ()*)
-
-declare extern_weak i8* @pthread_getspecific(i32)
-
-declare extern_weak i32 @pthread_setspecific(i32, i8*)
-
-declare extern_weak i32 @pthread_create(i64*, %union.pthread_attr_t*, i8* (i8*)*, i8*)
-
-declare extern_weak i32 @pthread_join(i64, i8**)
-
-declare extern_weak i32 @pthread_equal(i64, i64)
-
-declare extern_weak i64 @pthread_self()
-
-declare extern_weak i32 @pthread_detach(i64)
-
-declare extern_weak i32 @pthread_cancel(i64)
-
-declare extern_weak i32 @sched_yield()
-
-declare extern_weak i32 @pthread_mutex_lock(%union.pthread_mutex_t*)
-
-declare extern_weak i32 @pthread_mutex_trylock(%union.pthread_mutex_t*)
-
-declare extern_weak i32 @pthread_mutex_timedlock(%union.pthread_mutex_t*, %struct.timespec*)
-
-declare extern_weak i32 @pthread_mutex_unlock(%union.pthread_mutex_t*)
-
-declare extern_weak i32 @pthread_mutex_init(%union.pthread_mutex_t*, %union.pthread_mutexattr_t*)
-
-declare extern_weak i32 @pthread_mutex_destroy(%union.pthread_mutex_t*)
-
-declare extern_weak i32 @pthread_cond_broadcast(%union.pthread_cond_t*)
-
-declare extern_weak i32 @pthread_cond_signal(%union.pthread_cond_t*)
-
-declare extern_weak i32 @pthread_cond_wait(%union.pthread_cond_t*, %union.pthread_mutex_t*)
-
-declare extern_weak i32 @pthread_cond_timedwait(%union.pthread_cond_t*, %union.pthread_mutex_t*, %struct.timespec*)
-
-declare extern_weak i32 @pthread_cond_destroy(%union.pthread_cond_t*)
-
-declare extern_weak i32 @pthread_key_create(i32*, void (i8*)*)
-
-declare extern_weak i32 @pthread_key_delete(i32)
-
-declare extern_weak i32 @pthread_mutexattr_init(%union.pthread_mutexattr_t*)
-
-declare extern_weak i32 @pthread_mutexattr_settype(%union.pthread_mutexattr_t*, i32)
-
-declare extern_weak i32 @pthread_mutexattr_destroy(%union.pthread_mutexattr_t*)
-
-declare void @_GLOBAL__sub_I__ZN10BitBoard64coEv() nounwind uwtable
diff --git a/test/Linker/2011-08-22-ResolveAlias2.ll b/test/Linker/2011-08-22-ResolveAlias2.ll
deleted file mode 100644
index c380c23abe41..000000000000
--- a/test/Linker/2011-08-22-ResolveAlias2.ll
+++ /dev/null
@@ -1,146 +0,0 @@
-; This file is used by 2011-08-22-ResolveAlias.ll
-; RUN: true
-
-%struct.HexxagonBoard = type { %struct.BitBoard64, %struct.BitBoard64 }
-%struct.BitBoard64 = type { i32, i32 }
-%union.pthread_attr_t = type { [56 x i8] }
-%union.pthread_mutex_t = type { [40 x i8] }
-%struct.timespec = type { i64, i64 }
-%union.pthread_mutexattr_t = type { [4 x i8] }
-%union.pthread_cond_t = type { [48 x i8] }
-
-@_ZN13HexxagonBoardC1ERKS_ = alias void (%struct.HexxagonBoard*, %struct.HexxagonBoard*)* @_ZN13HexxagonBoardC2ERKS_
-@_ZL20__gthrw_pthread_oncePiPFvvE = weak alias i32 (i32*, void ()*)* @pthread_once
-@_ZL27__gthrw_pthread_getspecificj = weak alias i8* (i32)* @pthread_getspecific
-@_ZL27__gthrw_pthread_setspecificjPKv = weak alias i32 (i32, i8*)* @pthread_setspecific
-@_ZL22__gthrw_pthread_createPmPK14pthread_attr_tPFPvS3_ES3_ = weak alias i32 (i64*, %union.pthread_attr_t*, i8* (i8*)*, i8*)* @pthread_create
-@_ZL20__gthrw_pthread_joinmPPv = weak alias i32 (i64, i8**)* @pthread_join
-@_ZL21__gthrw_pthread_equalmm = weak alias i32 (i64, i64)* @pthread_equal
-@_ZL20__gthrw_pthread_selfv = weak alias i64 ()* @pthread_self
-@_ZL22__gthrw_pthread_detachm = weak alias i32 (i64)* @pthread_detach
-@_ZL22__gthrw_pthread_cancelm = weak alias i32 (i64)* @pthread_cancel
-@_ZL19__gthrw_sched_yieldv = weak alias i32 ()* @sched_yield
-@_ZL26__gthrw_pthread_mutex_lockP15pthread_mutex_t = weak alias i32 (%union.pthread_mutex_t*)* @pthread_mutex_lock
-@_ZL29__gthrw_pthread_mutex_trylockP15pthread_mutex_t = weak alias i32 (%union.pthread_mutex_t*)* @pthread_mutex_trylock
-@_ZL31__gthrw_pthread_mutex_timedlockP15pthread_mutex_tPK8timespec = weak alias i32 (%union.pthread_mutex_t*, %struct.timespec*)* @pthread_mutex_timedlock
-@_ZL28__gthrw_pthread_mutex_unlockP15pthread_mutex_t = weak alias i32 (%union.pthread_mutex_t*)* @pthread_mutex_unlock
-@_ZL26__gthrw_pthread_mutex_initP15pthread_mutex_tPK19pthread_mutexattr_t = weak alias i32 (%union.pthread_mutex_t*, %union.pthread_mutexattr_t*)* @pthread_mutex_init
-@_ZL29__gthrw_pthread_mutex_destroyP15pthread_mutex_t = weak alias i32 (%union.pthread_mutex_t*)* @pthread_mutex_destroy
-@_ZL30__gthrw_pthread_cond_broadcastP14pthread_cond_t = weak alias i32 (%union.pthread_cond_t*)* @pthread_cond_broadcast
-@_ZL27__gthrw_pthread_cond_signalP14pthread_cond_t = weak alias i32 (%union.pthread_cond_t*)* @pthread_cond_signal
-@_ZL25__gthrw_pthread_cond_waitP14pthread_cond_tP15pthread_mutex_t = weak alias i32 (%union.pthread_cond_t*, %union.pthread_mutex_t*)* @pthread_cond_wait
-@_ZL30__gthrw_pthread_cond_timedwaitP14pthread_cond_tP15pthread_mutex_tPK8timespec = weak alias i32 (%union.pthread_cond_t*, %union.pthread_mutex_t*, %struct.timespec*)* @pthread_cond_timedwait
-@_ZL28__gthrw_pthread_cond_destroyP14pthread_cond_t = weak alias i32 (%union.pthread_cond_t*)* @pthread_cond_destroy
-@_ZL26__gthrw_pthread_key_createPjPFvPvE = weak alias i32 (i32*, void (i8*)*)* @pthread_key_create
-@_ZL26__gthrw_pthread_key_deletej = weak alias i32 (i32)* @pthread_key_delete
-@_ZL30__gthrw_pthread_mutexattr_initP19pthread_mutexattr_t = weak alias i32 (%union.pthread_mutexattr_t*)* @pthread_mutexattr_init
-@_ZL33__gthrw_pthread_mutexattr_settypeP19pthread_mutexattr_ti = weak alias i32 (%union.pthread_mutexattr_t*, i32)* @pthread_mutexattr_settype
-@_ZL33__gthrw_pthread_mutexattr_destroyP19pthread_mutexattr_t = weak alias i32 (%union.pthread_mutexattr_t*)* @pthread_mutexattr_destroy
-
-define void @_ZN13HexxagonBoardC2ERKS_(%struct.HexxagonBoard*, %struct.HexxagonBoard*) uwtable align 2 {
-  ret void
-}
-
-define weak i32 @pthread_once(i32*, void ()*) {
-  ret i32 0
-}
-
-define weak i8* @pthread_getspecific(i32) {
-  ret i8* null
-}
-
-define weak i32 @pthread_setspecific(i32, i8*) {
-  ret i32 0
-}
-
-define weak i32 @pthread_create(i64*, %union.pthread_attr_t*, i8* (i8*)*, i8*) {
-  ret i32 0
-}
-
-define weak i32 @pthread_join(i64, i8**) {
-  ret i32 0
-}
-
-define weak i32 @pthread_equal(i64, i64) {
-  ret i32 0
-}
-
-define weak i64 @pthread_self() {
-  ret i64 0
-}
-
-define weak i32 @pthread_detach(i64) {
-  ret i32 0
-}
-
-define weak i32 @pthread_cancel(i64) {
-  ret i32 0
-}
-
-define weak i32 @sched_yield() {
-  ret i32 0
-}
-
-define weak i32 @pthread_mutex_lock(%union.pthread_mutex_t*) {
-  ret i32 0
-}
-
-define weak i32 @pthread_mutex_trylock(%union.pthread_mutex_t*) {
-  ret i32 0
-}
-
-define weak i32 @pthread_mutex_timedlock(%union.pthread_mutex_t*, %struct.timespec*) {
-  ret i32 0
-}
-
-define weak i32 @pthread_mutex_unlock(%union.pthread_mutex_t*) {
-  ret i32 0
-}
-
-define weak i32 @pthread_mutex_init(%union.pthread_mutex_t*, %union.pthread_mutexattr_t*) {
-  ret i32 0
-}
-
-define weak i32 @pthread_mutex_destroy(%union.pthread_mutex_t*) {
-  ret i32 0
-}
-
-define weak i32 @pthread_cond_broadcast(%union.pthread_cond_t*) {
-  ret i32 0
-}
-
-define weak i32 @pthread_cond_signal(%union.pthread_cond_t*) {
-  ret i32 0
-}
-
-define weak i32 @pthread_cond_wait(%union.pthread_cond_t*, %union.pthread_mutex_t*) {
-  ret i32 0
-}
-
-define weak i32 @pthread_cond_timedwait(%union.pthread_cond_t*, %union.pthread_mutex_t*, %struct.timespec*) {
-  ret i32 0
-}
-
-define weak i32 @pthread_cond_destroy(%union.pthread_cond_t*) {
-  ret i32 0
-}
-
-define weak i32 @pthread_key_create(i32*, void (i8*)*) {
-  ret i32 0
-}
-
-define weak i32 @pthread_key_delete(i32) {
-  ret i32 0
-}
-
-define weak i32 @pthread_mutexattr_init(%union.pthread_mutexattr_t*) {
-  ret i32 0
-}
-
-define weak i32 @pthread_mutexattr_settype(%union.pthread_mutexattr_t*, i32) {
-  ret i32 0
-}
-
-define weak i32 @pthread_mutexattr_destroy(%union.pthread_mutexattr_t*) {
-  ret i32 0
-}
diff --git a/test/Linker/AppendingLinkage.ll b/test/Linker/AppendingLinkage.ll
index 5beff5a10777..a3db5d28cd22 100644
--- a/test/Linker/AppendingLinkage.ll
+++ b/test/Linker/AppendingLinkage.ll
@@ -7,10 +7,10 @@
 ; CHECK: [i32 7, i32 4, i32 8]
 
 @X = appending global [2 x i32] [ i32 7, i32 4 ]		; <[2 x i32]*> [#uses=2]
-@Y = global i32* getelementptr ([2 x i32]* @X, i64 0, i64 0)		; <i32**> [#uses=0]
+@Y = global i32* getelementptr ([2 x i32], [2 x i32]* @X, i64 0, i64 0)		; <i32**> [#uses=0]
 
 define void @foo(i64 %V) {
-	%Y = getelementptr [2 x i32]* @X, i64 0, i64 %V		; <i32*> [#uses=0]
+	%Y = getelementptr [2 x i32], [2 x i32]* @X, i64 0, i64 %V		; <i32*> [#uses=0]
 	ret void
 }
 
diff --git a/test/Linker/DbgDeclare.ll b/test/Linker/DbgDeclare.ll
index de5ac9e97b25..a6ffa915c071 100644
--- a/test/Linker/DbgDeclare.ll
+++ b/test/Linker/DbgDeclare.ll
@@ -21,11 +21,11 @@ entry:
   %argv.addr = alloca i8**, align 8
   store i32 0, i32* %retval
   store i32 %argc, i32* %argc.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %argc.addr, metadata !14, metadata !{!"0x102"}), !dbg !15
+  call void @llvm.dbg.declare(metadata i32* %argc.addr, metadata !14, metadata !DIExpression()), !dbg !15
   store i8** %argv, i8*** %argv.addr, align 8
-  call void @llvm.dbg.declare(metadata i8*** %argv.addr, metadata !16, metadata !{!"0x102"}), !dbg !15
-  %0 = load i32* %argc.addr, align 4, !dbg !17
-  %1 = load i8*** %argv.addr, align 8, !dbg !17
+  call void @llvm.dbg.declare(metadata i8*** %argv.addr, metadata !16, metadata !DIExpression()), !dbg !15
+  %0 = load i32, i32* %argc.addr, align 4, !dbg !17
+  %1 = load i8**, i8*** %argv.addr, align 8, !dbg !17
   call void @test(i32 %0, i8** %1), !dbg !17
   ret i32 0, !dbg !19
 }
@@ -37,24 +37,23 @@ declare void @test(i32, i8**)
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!21}
 
-!0 = !{!"0x11\004\00clang version 3.3 (trunk 173515)\001\00\000\00\000", !20, !2, !2, !3, !2, null} ; [ DW_TAG_compile_unit ]
-!1 = !{!2}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 (trunk 173515)", isOptimized: true, emissionKind: 0, file: !20, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2)
+!2 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00main\00main\00\003\000\001\000\006\00256\000\004", !20, null, !7, null, i32 (i32, i8**)* @main, null, null, !1} ; [ DW_TAG_subprogram ]
-!6 = !{!"0x29", !20} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "main", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !20, scope: null, type: !7, function: i32 (i32, i8**)* @main, variables: !2)
+!6 = !DIFile(filename: "main.cpp", directory: "/private/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !9, !10}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!10 = !{!"0xf\00\000\0064\0064\000\000", null, null, !11} ; [ DW_TAG_pointer_type ]
-!11 = !{!"0xf\00\000\0064\0064\000\000", null, null, !12} ; [ DW_TAG_pointer_type ]
-!12 = !{!"0x26\00\000\000\000\000\000", null, null, !13} ; [ DW_TAG_const_type ]
-!13 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ]
-!14 = !{!"0x101\00argc\0016777219\000", !5, !6, !9} ; [ DW_TAG_arg_variable ]
-!15 = !MDLocation(line: 3, scope: !5)
-!16 = !{!"0x101\00argv\0033554435\000", !5, !6, !10} ; [ DW_TAG_arg_variable ]
-!17 = !MDLocation(line: 5, scope: !18)
-!18 = !{!"0xb\004\000\000", !20, !5} ; [ DW_TAG_lexical_block ]
-!19 = !MDLocation(line: 6, scope: !18)
-!20 = !{!"main.cpp", !"/private/tmp"}
-!21 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !11)
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !12)
+!12 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !13)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 3, arg: 1, scope: !5, file: !6, type: !9)
+!15 = !DILocation(line: 3, scope: !5)
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 3, arg: 2, scope: !5, file: !6, type: !10)
+!17 = !DILocation(line: 5, scope: !18)
+!18 = distinct !DILexicalBlock(line: 4, column: 0, file: !20, scope: !5)
+!19 = !DILocation(line: 6, scope: !18)
+!20 = !DIFile(filename: "main.cpp", directory: "/private/tmp")
+!21 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/DbgDeclare2.ll b/test/Linker/DbgDeclare2.ll
index 2f01b0eaea2e..b716833ecc66 100644
--- a/test/Linker/DbgDeclare2.ll
+++ b/test/Linker/DbgDeclare2.ll
@@ -11,30 +11,30 @@ entry:
   %argv.addr = alloca i8**, align 8
   %i = alloca i32, align 4
   store i32 %argc, i32* %argc.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %argc.addr, metadata !14, metadata !{!"0x102"}), !dbg !15
+  call void @llvm.dbg.declare(metadata i32* %argc.addr, metadata !14, metadata !DIExpression()), !dbg !15
   store i8** %argv, i8*** %argv.addr, align 8
-  call void @llvm.dbg.declare(metadata i8*** %argv.addr, metadata !16, metadata !{!"0x102"}), !dbg !15
-  call void @llvm.dbg.declare(metadata i32* %i, metadata !17, metadata !{!"0x102"}), !dbg !20
+  call void @llvm.dbg.declare(metadata i8*** %argv.addr, metadata !16, metadata !DIExpression()), !dbg !15
+  call void @llvm.dbg.declare(metadata i32* %i, metadata !17, metadata !DIExpression()), !dbg !20
   store i32 0, i32* %i, align 4, !dbg !20
   br label %for.cond, !dbg !20
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4, !dbg !20
-  %1 = load i32* %argc.addr, align 4, !dbg !20
+  %0 = load i32, i32* %i, align 4, !dbg !20
+  %1 = load i32, i32* %argc.addr, align 4, !dbg !20
   %cmp = icmp slt i32 %0, %1, !dbg !20
   br i1 %cmp, label %for.body, label %for.end, !dbg !20
 
 for.body:                                         ; preds = %for.cond
-  %2 = load i32* %i, align 4, !dbg !21
+  %2 = load i32, i32* %i, align 4, !dbg !21
   %idxprom = sext i32 %2 to i64, !dbg !21
-  %3 = load i8*** %argv.addr, align 8, !dbg !21
-  %arrayidx = getelementptr inbounds i8** %3, i64 %idxprom, !dbg !21
-  %4 = load i8** %arrayidx, align 8, !dbg !21
+  %3 = load i8**, i8*** %argv.addr, align 8, !dbg !21
+  %arrayidx = getelementptr inbounds i8*, i8** %3, i64 %idxprom, !dbg !21
+  %4 = load i8*, i8** %arrayidx, align 8, !dbg !21
   %call = call i32 @puts(i8* %4), !dbg !21
   br label %for.inc, !dbg !23
 
 for.inc:                                          ; preds = %for.body
-  %5 = load i32* %i, align 4, !dbg !20
+  %5 = load i32, i32* %i, align 4, !dbg !20
   %inc = add nsw i32 %5, 1, !dbg !20
   store i32 %inc, i32* %i, align 4, !dbg !20
   br label %for.cond, !dbg !20
@@ -50,30 +50,29 @@ declare i32 @puts(i8*)
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!27}
 
-!0 = !{!"0x11\004\00clang version 3.3 (trunk 173515)\001\00\000\00\000", !25, !2, !2, !3, !2, null} ; [ DW_TAG_compile_unit ]
-!1 = !{!2}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 (trunk 173515)", isOptimized: true, emissionKind: 0, file: !25, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2)
+!2 = !{}
 !3 = !{!5}
-!5 = !{!"0x2e\00print_args\00print_args\00test\004\000\001\000\006\00256\000\005", !26, null, !7, null, void (i32, i8**)* @test, null, null, !1} ; [ DW_TAG_subprogram ]
-!6 = !{!"0x29", !26} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "print_args", linkageName: "test", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !26, scope: null, type: !7, function: void (i32, i8**)* @test, variables: !2)
+!6 = !DIFile(filename: "test.cpp", directory: "/private/tmp")
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9, !10}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
-!10 = !{!"0xf\00\000\0064\0064\000\000", null, null, !11} ; [ DW_TAG_pointer_type ]
-!11 = !{!"0xf\00\000\0064\0064\000\000", null, null, !12} ; [ DW_TAG_pointer_type ]
-!12 = !{!"0x26\00\000\000\000\000\000", null, null, !13} ; [ DW_TAG_const_type ]
-!13 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ]
-!14 = !{!"0x101\00argc\0016777220\000", !5, !6, !9} ; [ DW_TAG_arg_variable ]
-!15 = !MDLocation(line: 4, scope: !5)
-!16 = !{!"0x101\00argv\0033554436\000", !5, !6, !10} ; [ DW_TAG_arg_variable ]
-!17 = !{!"0x100\00i\006\000", !18, !6, !9} ; [ DW_TAG_auto_variable ]
-!18 = !{!"0xb\006\000\001", !26, !19} ; [ DW_TAG_lexical_block ]
-!19 = !{!"0xb\005\000\000", !26, !5} ; [ DW_TAG_lexical_block ]
-!20 = !MDLocation(line: 6, scope: !18)
-!21 = !MDLocation(line: 8, scope: !22)
-!22 = !{!"0xb\007\000\002", !26, !18} ; [ DW_TAG_lexical_block ]
-!23 = !MDLocation(line: 9, scope: !22)
-!24 = !MDLocation(line: 10, scope: !19)
-!25 = !{!"main.cpp", !"/private/tmp"}
-!26 = !{!"test.cpp", !"/private/tmp"}
-!27 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !11)
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !12)
+!12 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !13)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 4, arg: 1, scope: !5, file: !6, type: !9)
+!15 = !DILocation(line: 4, scope: !5)
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 4, arg: 2, scope: !5, file: !6, type: !10)
+!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 6, scope: !18, file: !6, type: !9)
+!18 = distinct !DILexicalBlock(line: 6, column: 0, file: !26, scope: !19)
+!19 = distinct !DILexicalBlock(line: 5, column: 0, file: !26, scope: !5)
+!20 = !DILocation(line: 6, scope: !18)
+!21 = !DILocation(line: 8, scope: !22)
+!22 = distinct !DILexicalBlock(line: 7, column: 0, file: !26, scope: !18)
+!23 = !DILocation(line: 9, scope: !22)
+!24 = !DILocation(line: 10, scope: !19)
+!25 = !DIFile(filename: "main.cpp", directory: "/private/tmp")
+!26 = !DIFile(filename: "test.cpp", directory: "/private/tmp")
+!27 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/Inputs/PR11464.b.ll b/test/Linker/Inputs/PR11464.b.ll
index 7ef5a361291a..2c74d9c4c3bc 100644
--- a/test/Linker/Inputs/PR11464.b.ll
+++ b/test/Linker/Inputs/PR11464.b.ll
@@ -3,7 +3,7 @@
 
 define i32 @bug_a(%bug_type* %fp) nounwind uwtable {
 entry:
-  %d_stream = getelementptr inbounds %bug_type* %fp, i64 0, i32 0
+  %d_stream = getelementptr inbounds %bug_type, %bug_type* %fp, i64 0, i32 0
   ret i32 0
 }
 
diff --git a/test/Linker/Inputs/apple-version/1.ll b/test/Linker/Inputs/apple-version/1.ll
new file mode 100644
index 000000000000..5cafa5ecc1fe
--- /dev/null
+++ b/test/Linker/Inputs/apple-version/1.ll
@@ -0,0 +1 @@
+target triple = "x86_64-apple-macosx10.10.0"
diff --git a/test/Linker/Inputs/apple-version/2.ll b/test/Linker/Inputs/apple-version/2.ll
new file mode 100644
index 000000000000..b63ea1f8b233
--- /dev/null
+++ b/test/Linker/Inputs/apple-version/2.ll
@@ -0,0 +1 @@
+target triple = "x86_64-apple-macosx10.8.0"
diff --git a/test/Linker/Inputs/apple-version/3.ll b/test/Linker/Inputs/apple-version/3.ll
new file mode 100644
index 000000000000..68e58caead9c
--- /dev/null
+++ b/test/Linker/Inputs/apple-version/3.ll
@@ -0,0 +1 @@
+target triple = "i386-apple-macosx10.9.0"
diff --git a/test/Linker/Inputs/apple-version/4.ll b/test/Linker/Inputs/apple-version/4.ll
new file mode 100644
index 000000000000..467a634a32bd
--- /dev/null
+++ b/test/Linker/Inputs/apple-version/4.ll
@@ -0,0 +1 @@
+target triple = "x86_64h-apple-macosx10.9.0"
diff --git a/test/Linker/Inputs/basiclink.b.ll b/test/Linker/Inputs/basiclink.b.ll
index 0d2abc771c6d..407aa944837a 100644
--- a/test/Linker/Inputs/basiclink.b.ll
+++ b/test/Linker/Inputs/basiclink.b.ll
@@ -1,6 +1,6 @@
 declare i32* @foo(...)
 define i32* @bar() {
-	%ret = call i32* (...)* @foo( i32 123 )
+	%ret = call i32* (...) @foo( i32 123 )
 	ret i32* %ret
 }
 @baz = global i32 0
diff --git a/test/Linker/Inputs/comdat5.ll b/test/Linker/Inputs/comdat5.ll
index 98c42b7be0c6..19739eb1b5da 100644
--- a/test/Linker/Inputs/comdat5.ll
+++ b/test/Linker/Inputs/comdat5.ll
@@ -4,6 +4,6 @@ $foo = comdat largest
 
 @zed = external constant i8
 @some_name = private unnamed_addr constant [2 x i8*] [i8* @zed, i8* bitcast (void ()* @bar to i8*)], comdat($foo)
-@foo = alias getelementptr([2 x i8*]* @some_name, i32 0, i32 1)
+@foo = alias getelementptr([2 x i8*], [2 x i8*]* @some_name, i32 0, i32 1)
 
 declare void @bar() unnamed_addr
diff --git a/test/Linker/Inputs/drop-debug.bc b/test/Linker/Inputs/drop-debug.bc
new file mode 100644
index 000000000000..f9c471f8e0d1
--- /dev/null
+++ b/test/Linker/Inputs/drop-debug.bc
diff --git a/test/Linker/Inputs/linkage.b.ll b/test/Linker/Inputs/linkage.b.ll
index 0ada3f4cb428..9c1d06660220 100644
--- a/test/Linker/Inputs/linkage.b.ll
+++ b/test/Linker/Inputs/linkage.b.ll
@@ -3,7 +3,7 @@
 declare i32 @foo() 
 
 define void @bar() {
-	load i32* @X
+	load i32, i32* @X
 	call i32 @foo()
 	ret void
 }
diff --git a/test/Linker/Inputs/mdlocation.ll b/test/Linker/Inputs/mdlocation.ll
index f85c1dc7475d..22473db46097 100644
--- a/test/Linker/Inputs/mdlocation.ll
+++ b/test/Linker/Inputs/mdlocation.ll
@@ -1,13 +1,13 @@
 !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9}
 
-!0 = !{} ; Use this as a scope.
-!1 = !MDLocation(line: 3, column: 7, scope: !0)
-!2 = !MDLocation(line: 3, column: 7, scope: !0, inlinedAt: !1)
-!3 = !MDLocation(line: 3, column: 7, scope: !0, inlinedAt: !2)
-!4 = distinct !{} ; Test actual remapping.
-!5 = !MDLocation(line: 3, column: 7, scope: !4)
-!6 = !MDLocation(line: 3, column: 7, scope: !4, inlinedAt: !5)
-!7 = !MDLocation(line: 3, column: 7, scope: !4, inlinedAt: !6)
+!0 = !DISubprogram() ; Use this as a scope.
+!1 = !DILocation(line: 3, column: 7, scope: !0)
+!2 = !DILocation(line: 3, column: 7, scope: !0, inlinedAt: !1)
+!3 = !DILocation(line: 3, column: 7, scope: !0, inlinedAt: !2)
+!4 = distinct !DISubprogram() ; Test actual remapping.
+!5 = !DILocation(line: 3, column: 7, scope: !4)
+!6 = !DILocation(line: 3, column: 7, scope: !4, inlinedAt: !5)
+!7 = !DILocation(line: 3, column: 7, scope: !4, inlinedAt: !6)
 ; Test distinct nodes.
-!8 = distinct !MDLocation(line: 3, column: 7, scope: !0)
-!9 = distinct !MDLocation(line: 3, column: 7, scope: !0, inlinedAt: !8)
+!8 = distinct !DILocation(line: 3, column: 7, scope: !0)
+!9 = distinct !DILocation(line: 3, column: 7, scope: !0, inlinedAt: !8)
diff --git a/test/Linker/Inputs/metadata-function.ll b/test/Linker/Inputs/metadata-function.ll
new file mode 100644
index 000000000000..8572ff119837
--- /dev/null
+++ b/test/Linker/Inputs/metadata-function.ll
@@ -0,0 +1,13 @@
+define weak void @foo() !weak !0 {
+  unreachable
+}
+
+define void @baz() !baz !0 {
+  unreachable
+}
+
+define void @b() !b !0 {
+  unreachable
+}
+
+!0 = !{!"b"}
diff --git a/test/Linker/Inputs/opaque.ll b/test/Linker/Inputs/opaque.ll
index 2b0d7d3cea8b..f164abd586d1 100644
--- a/test/Linker/Inputs/opaque.ll
+++ b/test/Linker/Inputs/opaque.ll
@@ -8,6 +8,6 @@
 @g3 = external global %B
 
 define void @f1()  {
-  getelementptr %A* null, i32 0
+  getelementptr %A, %A* null, i32 0
   ret void
 }
diff --git a/test/Linker/Inputs/override-different-linkage.ll b/test/Linker/Inputs/override-different-linkage.ll
new file mode 100644
index 000000000000..bc1514091801
--- /dev/null
+++ b/test/Linker/Inputs/override-different-linkage.ll
@@ -0,0 +1,4 @@
+define linkonce i32 @foo(i32 %i) {
+entry:
+  ret i32 4
+}
diff --git a/test/Linker/Inputs/override-with-internal-linkage-2.ll b/test/Linker/Inputs/override-with-internal-linkage-2.ll
new file mode 100644
index 000000000000..2f54a1511fa1
--- /dev/null
+++ b/test/Linker/Inputs/override-with-internal-linkage-2.ll
@@ -0,0 +1,4 @@
+define internal i32 @foo(i32 %i) {
+entry:
+  ret i32 4
+}
diff --git a/test/Linker/Inputs/override-with-internal-linkage.ll b/test/Linker/Inputs/override-with-internal-linkage.ll
new file mode 100644
index 000000000000..6e06fa5c4f75
--- /dev/null
+++ b/test/Linker/Inputs/override-with-internal-linkage.ll
@@ -0,0 +1,4 @@
+define i32 @foo(i32 %i) {
+entry:
+  ret i32 4
+}
diff --git a/test/Linker/Inputs/override.ll b/test/Linker/Inputs/override.ll
new file mode 100644
index 000000000000..6e06fa5c4f75
--- /dev/null
+++ b/test/Linker/Inputs/override.ll
@@ -0,0 +1,4 @@
+define i32 @foo(i32 %i) {
+entry:
+  ret i32 4
+}
diff --git a/test/Linker/Inputs/pr22807-1.ll b/test/Linker/Inputs/pr22807-1.ll
new file mode 100644
index 000000000000..4081a9b00e43
--- /dev/null
+++ b/test/Linker/Inputs/pr22807-1.ll
@@ -0,0 +1,6 @@
+%struct.A = type { %struct.B* }
+%struct.B = type opaque
+
+define i32 @foo(%struct.A** %A) {
+  ret i32 0
+}
diff --git a/test/Linker/Inputs/pr22807-2.ll b/test/Linker/Inputs/pr22807-2.ll
new file mode 100644
index 000000000000..7739b77df255
--- /dev/null
+++ b/test/Linker/Inputs/pr22807-2.ll
@@ -0,0 +1,6 @@
+%struct.A = type { %struct.B* }
+%struct.B = type opaque
+
+define i32 @bar(%struct.A* %A) {
+   ret i32 0
+}
diff --git a/test/Linker/Inputs/replaced-function-matches-first-subprogram.ll b/test/Linker/Inputs/replaced-function-matches-first-subprogram.ll
index a5de89f5a605..efa8ec9c67b0 100644
--- a/test/Linker/Inputs/replaced-function-matches-first-subprogram.ll
+++ b/test/Linker/Inputs/replaced-function-matches-first-subprogram.ll
@@ -4,7 +4,7 @@ define weak_odr i32 @_ZN5ClassIiE3fooEv(%struct.Class* %this) align 2 {
 entry:
   %this.addr = alloca %struct.Class*, align 8
   store %struct.Class* %this, %struct.Class** %this.addr, align 8
-  %this1 = load %struct.Class** %this.addr
+  %this1 = load %struct.Class*, %struct.Class** %this.addr
   ret i32 0, !dbg !12
 }
 
@@ -12,16 +12,16 @@ entry:
 !llvm.module.flags = !{!8, !9, !10}
 !llvm.ident = !{!11}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 (trunk 224193) (llvm/trunk 224197)\000\00\000\00\002", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d2/t2.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"t2.cpp", !"/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d2"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 (trunk 224193) (llvm/trunk 224197)", isOptimized: false, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "t2.cpp", directory: "/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d2")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\002\000\001\000\000\00256\000\002", !5, !6, !7, null, i32 (%struct.Class*)* @_ZN5ClassIiE3fooEv, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [foo]
-!5 = !{!"../t.h", !"/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d2"}
-!6 = !{!"0x29", !5}    ; [ DW_TAG_file_type ] [/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d2/../t.h]
-!7 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 2, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !5, scope: !6, type: !7, function: i32 (%struct.Class*)* @_ZN5ClassIiE3fooEv, variables: !2)
+!5 = !DIFile(filename: "../t.h", directory: "/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d2")
+!6 = !DIFile(filename: "../t.h", directory: "/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d2")
+!7 = !DISubroutineType(types: !2)
 !8 = !{i32 2, !"Dwarf Version", i32 2}
-!9 = !{i32 2, !"Debug Info Version", i32 2}
+!9 = !{i32 2, !"Debug Info Version", i32 3}
 !10 = !{i32 1, !"PIC Level", i32 2}
 !11 = !{!"clang version 3.6.0 (trunk 224193) (llvm/trunk 224197)"}
-!12 = !MDLocation(line: 2, column: 15, scope: !4)
+!12 = !DILocation(line: 2, column: 15, scope: !4)
diff --git a/test/Linker/Inputs/subprogram-linkonce-weak-odr.ll b/test/Linker/Inputs/subprogram-linkonce-weak-odr.ll
new file mode 100644
index 000000000000..71c080173a3d
--- /dev/null
+++ b/test/Linker/Inputs/subprogram-linkonce-weak-odr.ll
@@ -0,0 +1,15 @@
+define weak_odr i32 @foo(i32 %a, i32 %b) {
+entry:
+  %sum = add i32 %a, %b, !dbg !DILocation(line: 2, scope: !3)
+  ret i32 %sum, !dbg !DILocation(line: 3, scope: !3)
+}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+
+!llvm.dbg.cu = !{!1}
+!1 = !DICompileUnit(language: DW_LANG_C99, file: !2, subprograms: !{!3}, emissionKind: 1)
+!2 = !DIFile(filename: "foo.c", directory: "/path/to/dir")
+!3 = !DISubprogram(file: !4, scope: !4, line: 1, name: "foo", function: i32 (i32, i32)* @foo, type: !5)
+!4 = !DIFile(filename: "foo.h", directory: "/path/to/dir")
+!5 = !DISubroutineType(types: !{})
diff --git a/test/Linker/Inputs/subprogram-linkonce-weak.ll b/test/Linker/Inputs/subprogram-linkonce-weak.ll
new file mode 100644
index 000000000000..f5399e244a9c
--- /dev/null
+++ b/test/Linker/Inputs/subprogram-linkonce-weak.ll
@@ -0,0 +1,16 @@
+define weak i32 @foo(i32 %a, i32 %b) {
+entry:
+  %sum = call i32 @fastadd(i32 %a, i32 %b), !dbg !DILocation(line: 52, scope: !3)
+  ret i32 %sum, !dbg !DILocation(line: 53, scope: !3)
+}
+
+declare i32 @fastadd(i32, i32)
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+
+!llvm.dbg.cu = !{!1}
+!1 = !DICompileUnit(language: DW_LANG_C99, file: !2, subprograms: !{!3}, emissionKind: 1)
+!2 = !DIFile(filename: "foo.c", directory: "/path/to/dir")
+!3 = !DISubprogram(file: !2, scope: !2, line: 51, name: "foo", function: i32 (i32, i32)* @foo, type: !4)
+!4 = !DISubroutineType(types: !{})
diff --git a/test/Linker/Inputs/targettriple-a.ll b/test/Linker/Inputs/targettriple-a.ll
index 296d2df3ab6a..b8c7901d3177 100644
--- a/test/Linker/Inputs/targettriple-a.ll
+++ b/test/Linker/Inputs/targettriple-a.ll
@@ -1 +1 @@
-target triple = "e"
+target triple = "x86_64-unknown-linux-gnu"
diff --git a/test/Linker/Inputs/targettriple-b.ll b/test/Linker/Inputs/targettriple-b.ll
index cca872ec9662..0122b4ac56d9 100644
--- a/test/Linker/Inputs/targettriple-b.ll
+++ b/test/Linker/Inputs/targettriple-b.ll
@@ -1 +1 @@
-target triple = "E"
+target triple = "i386-unknown-linux-gnu"
diff --git a/test/Linker/Inputs/targettriple-c.ll b/test/Linker/Inputs/targettriple-c.ll
new file mode 100644
index 000000000000..e669a4c40ea0
--- /dev/null
+++ b/test/Linker/Inputs/targettriple-c.ll
@@ -0,0 +1 @@
+target triple = "x86_64h-unknown-linux-gnu"
diff --git a/test/Linker/Inputs/testlink.ll b/test/Linker/Inputs/testlink.ll
index 89f02ba95904..263d9e77d1ab 100644
--- a/test/Linker/Inputs/testlink.ll
+++ b/test/Linker/Inputs/testlink.ll
@@ -32,9 +32,9 @@
 
 define i32 @foo(i32 %blah) {
   store i32 %blah, i32* @MyVar
-  %idx = getelementptr %intlist* @MyIntList, i64 0, i32 1
+  %idx = getelementptr %intlist, %intlist* @MyIntList, i64 0, i32 1
   store i32 12, i32* %idx
-  %ack = load i32* @0
+  %ack = load i32, i32* @0
   %fzo = add i32 %ack, %blah
   ret i32 %fzo
 }
diff --git a/test/Linker/Inputs/type-unique-inheritance-a.ll b/test/Linker/Inputs/type-unique-inheritance-a.ll
index c503919349ff..75cc7e1c838a 100644
--- a/test/Linker/Inputs/type-unique-inheritance-a.ll
+++ b/test/Linker/Inputs/type-unique-inheritance-a.ll
@@ -1,7 +1,7 @@
-; CHECK: [ DW_TAG_class_type ] [A]
-; CHECK: [ DW_TAG_class_type ] [Base]
-; CHECK: [ DW_TAG_class_type ] [B]
-; CHECK-NOT: DW_TAG_class_type
+; CHECK: !DICompositeType(tag: DW_TAG_class_type, name: "A"
+; CHECK: !DICompositeType(tag: DW_TAG_class_type, name: "Base"
+; CHECK: !DICompositeType(tag: DW_TAG_class_type, name: "B"
+; CHECK-NOT: !DICompositeType(tag: DW_TAG_class_type
 ; Content of header files:
 ; 
 ; class Base;
@@ -52,8 +52,8 @@ entry:
   %a.addr = alloca i32, align 4
   %t = alloca %class.A, align 4
   store i32 %a, i32* %a.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !20, metadata !{!"0x102"}), !dbg !21
-  call void @llvm.dbg.declare(metadata %class.A* %t, metadata !22, metadata !{!"0x102"}), !dbg !23
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !20, metadata !DIExpression()), !dbg !21
+  call void @llvm.dbg.declare(metadata %class.A* %t, metadata !22, metadata !DIExpression()), !dbg !23
   ret void, !dbg !24
 }
 
@@ -66,29 +66,29 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!19, !25}
 
-!0 = !{!"0x11\004\00clang version 3.4 (http://llvm.org/git/clang.git f54e02f969d02d640103db73efc30c45439fceab) (http://llvm.org/git/llvm.git 284353b55896cb1babfaa7add7c0a363245342d2)\000\00\000\00\000", !1, !2, !3, !14, !2, !2} ; [ DW_TAG_compile_unit ] [/Users/mren/c_testing/type_unique_air/inher/foo.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"foo.cpp", !"/Users/mren/c_testing/type_unique_air/inher"}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 (http://llvm.org/git/clang.git f54e02f969d02d640103db73efc30c45439fceab) (http://llvm.org/git/llvm.git 284353b55896cb1babfaa7add7c0a363245342d2)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !14, globals: !2, imports: !2)
+!1 = !DIFile(filename: "foo.cpp", directory: "/Users/mren/c_testing/type_unique_air/inher")
+!2 = !{}
 !3 = !{!4, !8}
-!4 = !{!"0x2\00A\003\0064\0032\000\000\000", !5, null, null, !6, null, null, !"_ZTS1A"} ; [ DW_TAG_class_type ] [A] [line 3, size 64, align 32, offset 0] [def] [from ]
-!5 = !{!"./a.hpp", !"/Users/mren/c_testing/type_unique_air/inher"}
+!4 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 3, size: 64, align: 32, file: !5, elements: !6, identifier: "_ZTS1A")
+!5 = !DIFile(filename: "./a.hpp", directory: "/Users/mren/c_testing/type_unique_air/inher")
 !6 = !{!7, !13}
-!7 = !{!"0x1c\00\000\000\000\000\001", null, !"_ZTS1A", !8} ; [ DW_TAG_inheritance ] [line 0, size 0, align 0, offset 0] [private] [from Base]
-!8 = !{!"0x2\00Base\003\0032\0032\000\000\000", !9, null, null, !10, null, null, !"_ZTS4Base"} ; [ DW_TAG_class_type ] [Base] [line 3, size 32, align 32, offset 0] [def] [from ]
-!9 = !{!"./b.hpp", !"/Users/mren/c_testing/type_unique_air/inher"}
+!7 = !DIDerivedType(tag: DW_TAG_inheritance, flags: DIFlagPrivate, scope: !"_ZTS1A", baseType: !8)
+!8 = !DICompositeType(tag: DW_TAG_class_type, name: "Base", line: 3, size: 32, align: 32, file: !9, elements: !10, identifier: "_ZTS4Base")
+!9 = !DIFile(filename: "./b.hpp", directory: "/Users/mren/c_testing/type_unique_air/inher")
 !10 = !{!11}
-!11 = !{!"0xd\00b\004\0032\0032\000\001", !9, !"_ZTS4Base", !12} ; [ DW_TAG_member ] [b] [line 4, size 32, align 32, offset 0] [private] [from int]
-!12 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!13 = !{!"0xd\00x\004\0032\0032\0032\001", !5, !"_ZTS1A", !12} ; [ DW_TAG_member ] [x] [line 4, size 32, align 32, offset 32] [private] [from int]
+!11 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 4, size: 32, align: 32, flags: DIFlagPrivate, file: !9, scope: !"_ZTS4Base", baseType: !12)
+!12 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!13 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 4, size: 32, align: 32, offset: 32, flags: DIFlagPrivate, file: !5, scope: !"_ZTS1A", baseType: !12)
 !14 = !{!15}
-!15 = !{!"0x2e\00f\00f\00_Z1fi\005\000\001\000\006\00256\000\005", !1, !16, !17, null, void (i32)* @_Z1fi, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [f]
-!16 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/Users/mren/c_testing/type_unique_air/inher/foo.cpp]
-!17 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !18, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!15 = !DISubprogram(name: "f", linkageName: "_Z1fi", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !16, type: !17, function: void (i32)* @_Z1fi, variables: !2)
+!16 = !DIFile(filename: "foo.cpp", directory: "/Users/mren/c_testing/type_unique_air/inher")
+!17 = !DISubroutineType(types: !18)
 !18 = !{null, !12}
 !19 = !{i32 2, !"Dwarf Version", i32 2}
-!20 = !{!"0x101\00a\0016777221\000", !15, !16, !12} ; [ DW_TAG_arg_variable ] [a] [line 5]
-!21 = !MDLocation(line: 5, scope: !15)
-!22 = !{!"0x100\00t\006\000", !15, !16, !4} ; [ DW_TAG_auto_variable ] [t] [line 6]
-!23 = !MDLocation(line: 6, scope: !15)
-!24 = !MDLocation(line: 7, scope: !15)
-!25 = !{i32 1, !"Debug Info Version", i32 2}
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 5, arg: 1, scope: !15, file: !16, type: !12)
+!21 = !DILocation(line: 5, scope: !15)
+!22 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "t", line: 6, scope: !15, file: !16, type: !4)
+!23 = !DILocation(line: 6, scope: !15)
+!24 = !DILocation(line: 7, scope: !15)
+!25 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/Inputs/type-unique-inheritance-b.ll b/test/Linker/Inputs/type-unique-inheritance-b.ll
index d3b9dead03cd..dd89b8dd42df 100644
--- a/test/Linker/Inputs/type-unique-inheritance-b.ll
+++ b/test/Linker/Inputs/type-unique-inheritance-b.ll
@@ -10,8 +10,8 @@ entry:
   %a.addr = alloca i32, align 4
   %t = alloca %class.B, align 8
   store i32 %a, i32* %a.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !28, metadata !{!"0x102"}), !dbg !29
-  call void @llvm.dbg.declare(metadata %class.B* %t, metadata !30, metadata !{!"0x102"}), !dbg !31
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !28, metadata !DIExpression()), !dbg !29
+  call void @llvm.dbg.declare(metadata %class.B* %t, metadata !30, metadata !DIExpression()), !dbg !31
   ret void, !dbg !32
 }
 
@@ -24,7 +24,7 @@ entry:
   %retval = alloca i32, align 4
   %a = alloca %class.A, align 4
   store i32 0, i32* %retval
-  call void @llvm.dbg.declare(metadata %class.A* %a, metadata !33, metadata !{!"0x102"}), !dbg !34
+  call void @llvm.dbg.declare(metadata %class.A* %a, metadata !33, metadata !DIExpression()), !dbg !34
   call void @_Z1fi(i32 0), !dbg !35
   call void @_Z1gi(i32 1), !dbg !36
   ret i32 0, !dbg !37
@@ -40,42 +40,42 @@ attributes #3 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!27, !38}
 
-!0 = !{!"0x11\004\00clang version 3.4 (http://llvm.org/git/clang.git f54e02f969d02d640103db73efc30c45439fceab) (http://llvm.org/git/llvm.git 284353b55896cb1babfaa7add7c0a363245342d2)\000\00\000\00\000", !1, !2, !3, !19, !2, !2} ; [ DW_TAG_compile_unit ] [/Users/mren/c_testing/type_unique_air/inher/bar.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"bar.cpp", !"/Users/mren/c_testing/type_unique_air/inher"}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 (http://llvm.org/git/clang.git f54e02f969d02d640103db73efc30c45439fceab) (http://llvm.org/git/llvm.git 284353b55896cb1babfaa7add7c0a363245342d2)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !19, globals: !2, imports: !2)
+!1 = !DIFile(filename: "bar.cpp", directory: "/Users/mren/c_testing/type_unique_air/inher")
+!2 = !{}
 !3 = !{!4, !11, !15}
-!4 = !{!"0x2\00B\007\00128\0064\000\000\000", !5, null, null, !6, null, null, !"_ZTS1B"} ; [ DW_TAG_class_type ] [B] [line 7, size 128, align 64, offset 0] [def] [from ]
-!5 = !{!"./b.hpp", !"/Users/mren/c_testing/type_unique_air/inher"}
+!4 = !DICompositeType(tag: DW_TAG_class_type, name: "B", line: 7, size: 128, align: 64, file: !5, elements: !6, identifier: "_ZTS1B")
+!5 = !DIFile(filename: "./b.hpp", directory: "/Users/mren/c_testing/type_unique_air/inher")
 !6 = !{!7, !9}
-!7 = !{!"0xd\00bb\008\0032\0032\000\001", !5, !"_ZTS1B", !8} ; [ DW_TAG_member ] [bb] [line 8, size 32, align 32, offset 0] [private] [from int]
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0xd\00a\009\0064\0064\0064\001", !5, !"_ZTS1B", !10} ; [ DW_TAG_member ] [a] [line 9, size 64, align 64, offset 64] [private] [from ]
-!10 = !{!"0xf\00\000\0064\0064\000\000", null, null, !11} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from A]
-!11 = !{!"0x2\00A\003\0064\0032\000\000\000", !12, null, null, !13, null, null, !"_ZTS1A"} ; [ DW_TAG_class_type ] [A] [line 3, size 64, align 32, offset 0] [def] [from ]
-!12 = !{!"./a.hpp", !"/Users/mren/c_testing/type_unique_air/inher"}
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "bb", line: 8, size: 32, align: 32, flags: DIFlagPrivate, file: !5, scope: !"_ZTS1B", baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 9, size: 64, align: 64, offset: 64, flags: DIFlagPrivate, file: !5, scope: !"_ZTS1B", baseType: !10)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !11)
+!11 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 3, size: 64, align: 32, file: !12, elements: !13, identifier: "_ZTS1A")
+!12 = !DIFile(filename: "./a.hpp", directory: "/Users/mren/c_testing/type_unique_air/inher")
 !13 = !{!14, !18}
-!14 = !{!"0x1c\00\000\000\000\000\001", null, !"_ZTS1A", !15} ; [ DW_TAG_inheritance ] [line 0, size 0, align 0, offset 0] [private] [from Base]
-!15 = !{!"0x2\00Base\003\0032\0032\000\000\000", !5, null, null, !16, null, null, !"_ZTS4Base"} ; [ DW_TAG_class_type ] [Base] [line 3, size 32, align 32, offset 0] [def] [from ]
+!14 = !DIDerivedType(tag: DW_TAG_inheritance, flags: DIFlagPrivate, scope: !"_ZTS1A", baseType: !15)
+!15 = !DICompositeType(tag: DW_TAG_class_type, name: "Base", line: 3, size: 32, align: 32, file: !5, elements: !16, identifier: "_ZTS4Base")
 !16 = !{!17}
-!17 = !{!"0xd\00b\004\0032\0032\000\001", !5, !"_ZTS4Base", !8} ; [ DW_TAG_member ] [b] [line 4, size 32, align 32, offset 0] [private] [from int]
-!18 = !{!"0xd\00x\004\0032\0032\0032\001", !12, !"_ZTS1A", !8} ; [ DW_TAG_member ] [x] [line 4, size 32, align 32, offset 32] [private] [from int]
+!17 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 4, size: 32, align: 32, flags: DIFlagPrivate, file: !5, scope: !"_ZTS4Base", baseType: !8)
+!18 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 4, size: 32, align: 32, offset: 32, flags: DIFlagPrivate, file: !12, scope: !"_ZTS1A", baseType: !8)
 !19 = !{!20, !24}
-!20 = !{!"0x2e\00g\00g\00_Z1gi\004\000\001\000\006\00256\000\004", !1, !21, !22, null, void (i32)* @_Z1gi, null, null, !2} ; [ DW_TAG_subprogram ] [line 4] [def] [g]
-!21 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/Users/mren/c_testing/type_unique_air/inher/bar.cpp]
-!22 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !23, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!20 = !DISubprogram(name: "g", linkageName: "_Z1gi", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !1, scope: !21, type: !22, function: void (i32)* @_Z1gi, variables: !2)
+!21 = !DIFile(filename: "bar.cpp", directory: "/Users/mren/c_testing/type_unique_air/inher")
+!22 = !DISubroutineType(types: !23)
 !23 = !{null, !8}
-!24 = !{!"0x2e\00main\00main\00\009\000\001\000\006\00256\000\009", !1, !21, !25, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 9] [def] [main]
-!25 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !26, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!24 = !DISubprogram(name: "main", line: 9, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 9, file: !1, scope: !21, type: !25, function: i32 ()* @main, variables: !2)
+!25 = !DISubroutineType(types: !26)
 !26 = !{!8}
 !27 = !{i32 2, !"Dwarf Version", i32 2}
-!28 = !{!"0x101\00a\0016777220\000", !20, !21, !8} ; [ DW_TAG_arg_variable ] [a] [line 4]
-!29 = !MDLocation(line: 4, scope: !20)
-!30 = !{!"0x100\00t\005\000", !20, !21, !4} ; [ DW_TAG_auto_variable ] [t] [line 5]
-!31 = !MDLocation(line: 5, scope: !20)
-!32 = !MDLocation(line: 6, scope: !20)
-!33 = !{!"0x100\00a\0010\000", !24, !21, !11} ; [ DW_TAG_auto_variable ] [a] [line 10]
-!34 = !MDLocation(line: 10, scope: !24)
-!35 = !MDLocation(line: 11, scope: !24)
-!36 = !MDLocation(line: 12, scope: !24)
-!37 = !MDLocation(line: 13, scope: !24)
-!38 = !{i32 1, !"Debug Info Version", i32 2}
+!28 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 4, arg: 1, scope: !20, file: !21, type: !8)
+!29 = !DILocation(line: 4, scope: !20)
+!30 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "t", line: 5, scope: !20, file: !21, type: !4)
+!31 = !DILocation(line: 5, scope: !20)
+!32 = !DILocation(line: 6, scope: !20)
+!33 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 10, scope: !24, file: !21, type: !11)
+!34 = !DILocation(line: 10, scope: !24)
+!35 = !DILocation(line: 11, scope: !24)
+!36 = !DILocation(line: 12, scope: !24)
+!37 = !DILocation(line: 13, scope: !24)
+!38 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/Inputs/type-unique-simple2-a.ll b/test/Linker/Inputs/type-unique-simple2-a.ll
index 6d6e93c68f00..c07157bf87b6 100644
--- a/test/Linker/Inputs/type-unique-simple2-a.ll
+++ b/test/Linker/Inputs/type-unique-simple2-a.ll
@@ -49,8 +49,8 @@ entry:
   %a.addr = alloca i32, align 4
   %t = alloca %struct.Base, align 8
   store i32 %a, i32* %a.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !17, metadata !{!"0x102"}), !dbg !18
-  call void @llvm.dbg.declare(metadata %struct.Base* %t, metadata !19, metadata !{!"0x102"}), !dbg !20
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !17, metadata !DIExpression()), !dbg !18
+  call void @llvm.dbg.declare(metadata %struct.Base* %t, metadata !19, metadata !DIExpression()), !dbg !20
   ret void, !dbg !21
 }
 
@@ -63,26 +63,26 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!16, !22}
 
-!0 = !{!"0x11\004\00clang version 3.4 (http://llvm.org/git/clang.git 8a3f9e46cb988d2c664395b21910091e3730ae82) (http://llvm.org/git/llvm.git 4699e9549358bc77824a59114548eecc3f7c523c)\000\00\000\00\000", !1, !2, !3, !11, !2, !2} ; [ DW_TAG_compile_unit ] [foo.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"foo.cpp", !"."}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 (http://llvm.org/git/clang.git 8a3f9e46cb988d2c664395b21910091e3730ae82) (http://llvm.org/git/llvm.git 4699e9549358bc77824a59114548eecc3f7c523c)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !11, globals: !2, imports: !2)
+!1 = !DIFile(filename: "foo.cpp", directory: ".")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00Base\001\00128\0064\000\000\000", !5, null, null, !6, null, null, !"_ZTS4Base"} ; [ DW_TAG_structure_type ] [Base] [line 1, size 128, align 64, offset 0] [def] [from ]
-!5 = !{!"./a.hpp", !"."}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "Base", line: 1, size: 128, align: 64, file: !5, elements: !6, identifier: "_ZTS4Base")
+!5 = !DIFile(filename: "./a.hpp", directory: ".")
 !6 = !{!7, !9}
-!7 = !{!"0xd\00a\002\0032\0032\000\000", !5, !"_ZTS4Base", !8} ; [ DW_TAG_member ] [a] [line 2, size 32, align 32, offset 0] [from int]
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0xd\00b\003\0064\0064\0064\000", !5, !"_ZTS4Base", !10} ; [ DW_TAG_member ] [b] [line 3, size 64, align 64, offset 64] [from ]
-!10 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS4Base"} ; [ DW_TAG_pointer_type ]
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 2, size: 32, align: 32, file: !5, scope: !"_ZTS4Base", baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 3, size: 64, align: 64, offset: 64, file: !5, scope: !"_ZTS4Base", baseType: !10)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS4Base")
 !11 = !{!12}
-!12 = !{!"0x2e\00f\00f\00_Z1fi\003\000\001\000\006\00256\000\003", !1, !13, !14, null, void (i32)* @_Z1fi, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [f]
-!13 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [foo.cpp]
-!14 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !15, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = !DISubprogram(name: "f", linkageName: "_Z1fi", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !13, type: !14, function: void (i32)* @_Z1fi, variables: !2)
+!13 = !DIFile(filename: "foo.cpp", directory: ".")
+!14 = !DISubroutineType(types: !15)
 !15 = !{null, !8}
 !16 = !{i32 2, !"Dwarf Version", i32 2}
-!17 = !{!"0x101\00a\0016777219\000", !12, !13, !8} ; [ DW_TAG_arg_variable ] [a] [line 3]
-!18 = !MDLocation(line: 3, scope: !12)
-!19 = !{!"0x100\00t\004\000", !12, !13, !4} ; [ DW_TAG_auto_variable ] [t] [line 4]
-!20 = !MDLocation(line: 4, scope: !12)
-!21 = !MDLocation(line: 5, scope: !12)
-!22 = !{i32 1, !"Debug Info Version", i32 2}
+!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 3, arg: 1, scope: !12, file: !13, type: !8)
+!18 = !DILocation(line: 3, scope: !12)
+!19 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "t", line: 4, scope: !12, file: !13, type: !4)
+!20 = !DILocation(line: 4, scope: !12)
+!21 = !DILocation(line: 5, scope: !12)
+!22 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/Inputs/type-unique-simple2-b.ll b/test/Linker/Inputs/type-unique-simple2-b.ll
index d3b2f7e514c6..817f88704de5 100644
--- a/test/Linker/Inputs/type-unique-simple2-b.ll
+++ b/test/Linker/Inputs/type-unique-simple2-b.ll
@@ -8,8 +8,8 @@ entry:
   %a.addr = alloca i32, align 4
   %t = alloca %struct.Base, align 8
   store i32 %a, i32* %a.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !20, metadata !{!"0x102"}), !dbg !21
-  call void @llvm.dbg.declare(metadata %struct.Base* %t, metadata !22, metadata !{!"0x102"}), !dbg !23
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !20, metadata !DIExpression()), !dbg !21
+  call void @llvm.dbg.declare(metadata %struct.Base* %t, metadata !22, metadata !DIExpression()), !dbg !23
   ret void, !dbg !24
 }
 
@@ -36,32 +36,32 @@ attributes #3 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!19, !28}
 
-!0 = !{!"0x11\004\00clang version 3.4 (http://llvm.org/git/clang.git 8a3f9e46cb988d2c664395b21910091e3730ae82) (http://llvm.org/git/llvm.git 4699e9549358bc77824a59114548eecc3f7c523c)\000\00\000\00\000", !1, !2, !3, !11, !2, !2} ; [ DW_TAG_compile_unit ] [bar.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"bar.cpp", !"."}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 (http://llvm.org/git/clang.git 8a3f9e46cb988d2c664395b21910091e3730ae82) (http://llvm.org/git/llvm.git 4699e9549358bc77824a59114548eecc3f7c523c)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !11, globals: !2, imports: !2)
+!1 = !DIFile(filename: "bar.cpp", directory: ".")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00Base\001\00128\0064\000\000\000", !5, null, null, !6, null, null, !"_ZTS4Base"} ; [ DW_TAG_structure_type ] [Base] [line 1, size 128, align 64, offset 0] [def] [from ]
-!5 = !{!"./a.hpp", !"."}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "Base", line: 1, size: 128, align: 64, file: !5, elements: !6, identifier: "_ZTS4Base")
+!5 = !DIFile(filename: "./a.hpp", directory: ".")
 !6 = !{!7, !9}
-!7 = !{!"0xd\00a\002\0032\0032\000\000", !5, !"_ZTS4Base", !8} ; [ DW_TAG_member ] [a] [line 2, size 32, align 32, offset 0] [from int]
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0xd\00b\003\0064\0064\0064\000", !5, !"_ZTS4Base", !10} ; [ DW_TAG_member ] [b] [line 3, size 64, align 64, offset 64] [from ]
-!10 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS4Base"} ; [ DW_TAG_pointer_type ]
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 2, size: 32, align: 32, file: !5, scope: !"_ZTS4Base", baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "b", line: 3, size: 64, align: 64, offset: 64, file: !5, scope: !"_ZTS4Base", baseType: !10)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS4Base")
 !11 = !{!12, !16}
-!12 = !{!"0x2e\00g\00g\00_Z1gi\004\000\001\000\006\00256\000\004", !1, !13, !14, null, void (i32)* @_Z1gi, null, null, !2} ; [ DW_TAG_subprogram ] [line 4] [def] [g]
-!13 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [bar.cpp]
-!14 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !15, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = !DISubprogram(name: "g", linkageName: "_Z1gi", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !1, scope: !13, type: !14, function: void (i32)* @_Z1gi, variables: !2)
+!13 = !DIFile(filename: "bar.cpp", directory: ".")
+!14 = !DISubroutineType(types: !15)
 !15 = !{null, !8}
-!16 = !{!"0x2e\00main\00main\00\007\000\001\000\006\00256\000\007", !1, !13, !17, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 7] [def] [main]
-!17 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !18, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!16 = !DISubprogram(name: "main", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !1, scope: !13, type: !17, function: i32 ()* @main, variables: !2)
+!17 = !DISubroutineType(types: !18)
 !18 = !{!8}
 !19 = !{i32 2, !"Dwarf Version", i32 2}
-!20 = !{!"0x101\00a\0016777220\000", !12, !13, !8} ; [ DW_TAG_arg_variable ] [a] [line 4]
-!21 = !MDLocation(line: 4, scope: !12)
-!22 = !{!"0x100\00t\005\000", !12, !13, !4} ; [ DW_TAG_auto_variable ] [t] [line 5]
-!23 = !MDLocation(line: 5, scope: !12)
-!24 = !MDLocation(line: 6, scope: !12)
-!25 = !MDLocation(line: 8, scope: !16)
-!26 = !MDLocation(line: 9, scope: !16)
-!27 = !MDLocation(line: 10, scope: !16)
-!28 = !{i32 1, !"Debug Info Version", i32 2}
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 4, arg: 1, scope: !12, file: !13, type: !8)
+!21 = !DILocation(line: 4, scope: !12)
+!22 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "t", line: 5, scope: !12, file: !13, type: !4)
+!23 = !DILocation(line: 5, scope: !12)
+!24 = !DILocation(line: 6, scope: !12)
+!25 = !DILocation(line: 8, scope: !16)
+!26 = !DILocation(line: 9, scope: !16)
+!27 = !DILocation(line: 10, scope: !16)
+!28 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/apple-version.ll b/test/Linker/apple-version.ll
new file mode 100644
index 000000000000..4dbc866ac3d7
--- /dev/null
+++ b/test/Linker/apple-version.ll
@@ -0,0 +1,24 @@
+; RUN: llvm-link %s %S/Inputs/apple-version/1.ll -S -o - 2>%t.err | FileCheck %s -check-prefix=CHECK1
+; RUN: cat %t.err | FileCheck --check-prefix=WARN1 --allow-empty %s
+; RUN: llvm-link %s %S/Inputs/apple-version/2.ll -S -o - 2>%t.err | FileCheck %s -check-prefix=CHECK2
+; RUN: cat %t.err | FileCheck --check-prefix=WARN2 --allow-empty %s
+; RUN: llvm-link %s %S/Inputs/apple-version/3.ll -S -o /dev/null 2>%t.err
+; RUN: cat %t.err | FileCheck --check-prefix=WARN3 %s
+; RUN: llvm-link %s %S/Inputs/apple-version/4.ll -S -o /dev/null 2>%t.err
+; RUN: cat %t.err | FileCheck --check-prefix=WARN4 --allow-empty %s
+
+; Check that the triple that has the larger version number is chosen and no
+; warnings are issued when the Triples differ only in version numbers.
+
+; CHECK1: target triple = "x86_64-apple-macosx10.10.0"
+; WARN1-NOT: WARNING
+; CHECK2: target triple = "x86_64-apple-macosx10.9.0"
+; WARN2-NOT: WARNING
+
+; i386 and x86_64 map to different ArchType enums.
+; WARN3: WARNING: Linking two modules of different target triples
+
+; x86_64h and x86_64 map to the same ArchType enum.
+; WARN4-NOT: WARNING
+
+target triple = "x86_64-apple-macosx10.9.0"
diff --git a/test/Linker/broken.ll b/test/Linker/broken.ll
new file mode 100644
index 000000000000..8aefe4e6a37d
--- /dev/null
+++ b/test/Linker/broken.ll
@@ -0,0 +1,8 @@
+; RUN: not llvm-link -o /dev/null %s 2>&1 | FileCheck %s
+
+; CHECK: broken.ll: error: input module is broken!
+define i32 @foo(i32 %v) {
+  %first = add i32 %v, %second
+  %second = add i32 %v, 3
+  ret i32 %first
+}
diff --git a/test/Linker/comdat3.ll b/test/Linker/comdat3.ll
deleted file mode 100644
index 3b5db0a39a0b..000000000000
--- a/test/Linker/comdat3.ll
+++ /dev/null
@@ -1,5 +0,0 @@
-; RUN: not llvm-link %s %p/Inputs/comdat2.ll -S -o - 2>&1 | FileCheck %s
-
-$foo = comdat largest
-@foo = global i32 43, comdat($foo)
-; CHECK: Linking COMDATs named 'foo': can't do size dependent selection without DataLayout!
diff --git a/test/Linker/comdat6.ll b/test/Linker/comdat6.ll
index b5360a7c7da3..15be2fe58036 100644
--- a/test/Linker/comdat6.ll
+++ b/test/Linker/comdat6.ll
@@ -5,6 +5,6 @@ target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"
 $foo = comdat largest
 @foo = linkonce_odr unnamed_addr constant [1 x i8*] [i8* bitcast (void ()* @bar to i8*)], comdat($foo)
 
-; CHECK: @foo = alias getelementptr inbounds ([2 x i8*]* @some_name, i32 0, i32 1)
+; CHECK: @foo = alias getelementptr inbounds ([2 x i8*], [2 x i8*]* @some_name, i32 0, i32 1)
 
 declare void @bar() unnamed_addr
diff --git a/test/Linker/datalayout.ll b/test/Linker/datalayout.ll
index 8cbfc198a684..cba28776eb57 100644
--- a/test/Linker/datalayout.ll
+++ b/test/Linker/datalayout.ll
@@ -1,13 +1,12 @@
 ; REQUIRES: shell
-; RUN: llvm-link %s %S/Inputs/datalayout-a.ll -S -o - 2>%t.a.err | FileCheck %s
+; RUN: llvm-link %s %S/Inputs/datalayout-a.ll -S -o - 2>%t.a.err
 ; RUN: (echo foo ;cat %t.a.err) | FileCheck --check-prefix=WARN-A %s
 
-; RUN: llvm-link %s %S/Inputs/datalayout-b.ll -S -o - 2>%t.b.err | FileCheck %s
+; RUN: llvm-link %s %S/Inputs/datalayout-b.ll -S -o - 2>%t.b.err
 ; RUN: cat %t.b.err | FileCheck --check-prefix=WARN-B %s
 
 target datalayout = "e"
 
-; CHECK: target datalayout = "e"
 
 ; WARN-A-NOT: WARNING
 
diff --git a/test/Linker/debug-info-version-a.ll b/test/Linker/debug-info-version-a.ll
index 352fcdcb77ca..8cc85b167f71 100644
--- a/test/Linker/debug-info-version-a.ll
+++ b/test/Linker/debug-info-version-a.ll
@@ -3,14 +3,14 @@
 ; Test linking of incompatible debug info versions. The debug info
 ; from the other file should be dropped.
 
-; CHECK-NOT: metadata !{metadata !"b.c", metadata !""}
-; CHECK:  !"a.c", !""}
-; CHECK-NOT: metadata !{metadata !"b.c", metadata !""}
+; CHECK-NOT: !DIFile(filename: "b.c", directory: "")
+; CHECK:     !DIFile(filename: "a.c", directory: "")
+; CHECK-NOT: !DIFile(filename: "b.c", directory: "")
 
 !llvm.module.flags = !{ !0 }
 !llvm.dbg.cu = !{!1}
 
-!0 = !{i32 2, !"Debug Info Version", i32 2}
-!1 = !{!"0x11\0012\00clang\001\00\000\00\000", !2, !3, !3, !3, null, null} ; [ DW_TAG_compile_unit ]
-!2 = !{!"a.c", !""}
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !DICompileUnit(language: DW_LANG_C99, producer: "clang", isOptimized: true, emissionKind: 0, file: !2, enums: !3, retainedTypes: !3, subprograms: !3)
+!2 = !DIFile(filename: "a.c", directory: "")
 !3 = !{}
diff --git a/test/Linker/debug-info-version-b.ll b/test/Linker/debug-info-version-b.ll
index e4944202f421..b2452f437023 100644
--- a/test/Linker/debug-info-version-b.ll
+++ b/test/Linker/debug-info-version-b.ll
@@ -5,6 +5,6 @@
 !llvm.dbg.cu = !{!1}
 
 !0 = !{i32 2, !"Debug Info Version", i32 42}
-!1 = !{!"0x11\0012\00clang\000\00", !"I AM UNEXPECTED!"} ; [ DW_TAG_compile_unit ]
+!1 = !DICompileUnit(language: DW_LANG_C99, producer: "clang", isOptimized: false, file: !"I AM UNEXPECTED!")
 !2 = !{!"b.c", !""}
 !3 = !{}
diff --git a/test/Linker/drop-debug.ll b/test/Linker/drop-debug.ll
new file mode 100644
index 000000000000..9c1072a75de2
--- /dev/null
+++ b/test/Linker/drop-debug.ll
@@ -0,0 +1,6 @@
+; RUN: llvm-link %p/Inputs/drop-debug.bc -o %t 2>&1 | FileCheck %s
+
+;; drop-debug.bc was created from "void f(void) {}" with clang 3.5 and
+; -gline-tables-only, so it contains old debug info.
+
+; CHECK: warning: ignoring debug info with an invalid version (1) in {{.*}}/Inputs/drop-debug.bc
diff --git a/test/Linker/link-global-to-func.ll b/test/Linker/link-global-to-func.ll
index 4d83fe59e894..f7adde94c139 100644
--- a/test/Linker/link-global-to-func.ll
+++ b/test/Linker/link-global-to-func.ll
@@ -9,6 +9,6 @@
 @__eprintf = external global i8*		; <i8**> [#uses=1]
 
 define i8* @test() {
-	%A = load i8** @__eprintf		; <i8*> [#uses=1]
+	%A = load i8*, i8** @__eprintf		; <i8*> [#uses=1]
 	ret i8* %A
 }
diff --git a/test/Linker/mdlocation.ll b/test/Linker/mdlocation.ll
index 5ee366cbb433..9acc6701599b 100644
--- a/test/Linker/mdlocation.ll
+++ b/test/Linker/mdlocation.ll
@@ -1,34 +1,34 @@
 ; RUN: llvm-link %s %S/Inputs/mdlocation.ll -o - -S | FileCheck %s
 
-; Test that MDLocations are remapped properly.
+; Test that DILocations are remapped properly.
 
 ; CHECK: !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9, !0, !1, !2, !3, !10, !11, !12, !13, !14, !15}
 !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9}
 
-; CHECK:      !0 = !{}
-; CHECK-NEXT: !1 = !MDLocation(line: 3, column: 7, scope: !0)
-; CHECK-NEXT: !2 = !MDLocation(line: 3, column: 7, scope: !0, inlinedAt: !1)
-; CHECK-NEXT: !3 = !MDLocation(line: 3, column: 7, scope: !0, inlinedAt: !2)
-; CHECK-NEXT: !4 = distinct !{}
-; CHECK-NEXT: !5 = !MDLocation(line: 3, column: 7, scope: !4)
-; CHECK-NEXT: !6 = !MDLocation(line: 3, column: 7, scope: !4, inlinedAt: !5)
-; CHECK-NEXT: !7 = !MDLocation(line: 3, column: 7, scope: !4, inlinedAt: !6)
-; CHECK-NEXT: !8 = distinct !MDLocation(line: 3, column: 7, scope: !0)
-; CHECK-NEXT: !9 = distinct !MDLocation(line: 3, column: 7, scope: !0, inlinedAt: !8)
-; CHECK-NEXT: !10 = distinct !{}
-; CHECK-NEXT: !11 = !MDLocation(line: 3, column: 7, scope: !10)
-; CHECK-NEXT: !12 = !MDLocation(line: 3, column: 7, scope: !10, inlinedAt: !11)
-; CHECK-NEXT: !13 = !MDLocation(line: 3, column: 7, scope: !10, inlinedAt: !12)
-; CHECK-NEXT: !14 = distinct !MDLocation(line: 3, column: 7, scope: !0)
-; CHECK-NEXT: !15 = distinct !MDLocation(line: 3, column: 7, scope: !0, inlinedAt: !14)
-!0 = !{} ; Use this as a scope.
-!1 = !MDLocation(line: 3, column: 7, scope: !0)
-!2 = !MDLocation(line: 3, column: 7, scope: !0, inlinedAt: !1)
-!3 = !MDLocation(line: 3, column: 7, scope: !0, inlinedAt: !2)
-!4 = distinct !{} ; Test actual remapping.
-!5 = !MDLocation(line: 3, column: 7, scope: !4)
-!6 = !MDLocation(line: 3, column: 7, scope: !4, inlinedAt: !5)
-!7 = !MDLocation(line: 3, column: 7, scope: !4, inlinedAt: !6)
+; CHECK:      !0 = !DISubprogram(
+; CHECK-NEXT: !1 = !DILocation(line: 3, column: 7, scope: !0)
+; CHECK-NEXT: !2 = !DILocation(line: 3, column: 7, scope: !0, inlinedAt: !1)
+; CHECK-NEXT: !3 = !DILocation(line: 3, column: 7, scope: !0, inlinedAt: !2)
+; CHECK-NEXT: !4 = distinct !DISubprogram(
+; CHECK-NEXT: !5 = !DILocation(line: 3, column: 7, scope: !4)
+; CHECK-NEXT: !6 = !DILocation(line: 3, column: 7, scope: !4, inlinedAt: !5)
+; CHECK-NEXT: !7 = !DILocation(line: 3, column: 7, scope: !4, inlinedAt: !6)
+; CHECK-NEXT: !8 = distinct !DILocation(line: 3, column: 7, scope: !0)
+; CHECK-NEXT: !9 = distinct !DILocation(line: 3, column: 7, scope: !0, inlinedAt: !8)
+; CHECK-NEXT: !10 = distinct !DISubprogram(
+; CHECK-NEXT: !11 = !DILocation(line: 3, column: 7, scope: !10)
+; CHECK-NEXT: !12 = !DILocation(line: 3, column: 7, scope: !10, inlinedAt: !11)
+; CHECK-NEXT: !13 = !DILocation(line: 3, column: 7, scope: !10, inlinedAt: !12)
+; CHECK-NEXT: !14 = distinct !DILocation(line: 3, column: 7, scope: !0)
+; CHECK-NEXT: !15 = distinct !DILocation(line: 3, column: 7, scope: !0, inlinedAt: !14)
+!0 = !DISubprogram() ; Use this as a scope.
+!1 = !DILocation(line: 3, column: 7, scope: !0)
+!2 = !DILocation(line: 3, column: 7, scope: !0, inlinedAt: !1)
+!3 = !DILocation(line: 3, column: 7, scope: !0, inlinedAt: !2)
+!4 = distinct !DISubprogram() ; Test actual remapping.
+!5 = !DILocation(line: 3, column: 7, scope: !4)
+!6 = !DILocation(line: 3, column: 7, scope: !4, inlinedAt: !5)
+!7 = !DILocation(line: 3, column: 7, scope: !4, inlinedAt: !6)
 ; Test distinct nodes.
-!8 = distinct !MDLocation(line: 3, column: 7, scope: !0)
-!9 = distinct !MDLocation(line: 3, column: 7, scope: !0, inlinedAt: !8)
+!8 = distinct !DILocation(line: 3, column: 7, scope: !0)
+!9 = distinct !DILocation(line: 3, column: 7, scope: !0, inlinedAt: !8)
diff --git a/test/Linker/metadata-function.ll b/test/Linker/metadata-function.ll
new file mode 100644
index 000000000000..0b17e0c58588
--- /dev/null
+++ b/test/Linker/metadata-function.ll
@@ -0,0 +1,26 @@
+; RUN: llvm-link %s %S/Inputs/metadata-function.ll -S | FileCheck %s
+; RUN: llvm-link %S/Inputs/metadata-function.ll %s -S | FileCheck %s
+
+; CHECK-DAG: define weak void @foo() !weak ![[B:[0-9]+]] {
+define linkonce void @foo() !linkonce !0 {
+  unreachable
+}
+
+; CHECK-DAG: define void @bar() !bar ![[A:[0-9]+]] {
+define void @bar() !bar !0 {
+  call void @baz()
+  unreachable
+}
+
+; CHECK-DAG: define void @baz() !baz ![[B]] {
+declare void @baz()
+
+; CHECK-DAG: define void @a() !a ![[A]] {
+; CHECK-DAG: define void @b() !b ![[B]] {
+define void @a() !a !0 {
+  unreachable
+}
+
+; CHECK-DAG: ![[A]] = !{!"a"}
+; CHECK-DAG: ![[B]] = !{!"b"}
+!0 = !{!"a"}
diff --git a/test/Linker/module-flags-3-b.ll b/test/Linker/module-flags-3-b.ll
index 2e6e5297eada..a983db20e5af 100644
--- a/test/Linker/module-flags-3-b.ll
+++ b/test/Linker/module-flags-3-b.ll
@@ -2,5 +2,6 @@
 ; RUN: true
 
 !0 = !{i32 3, !"foo", !{!"bar", i32 42}}
+!1 = !{i32 1, !"bar", i32 42}
 
-!llvm.module.flags = !{ !0 }
+!llvm.module.flags = !{ !0, !1 }
diff --git a/test/Linker/module-flags-4-b.ll b/test/Linker/module-flags-4-b.ll
index 25aaf190dc81..02d26033b51a 100644
--- a/test/Linker/module-flags-4-b.ll
+++ b/test/Linker/module-flags-4-b.ll
@@ -2,5 +2,6 @@
 ; RUN: true
 
 !0 = !{i32 3, !"foo", !{!"bar", i32 42}}
+!1 = !{i32 2, !"bar", i32 42}
 
-!llvm.module.flags = !{ !0 }
+!llvm.module.flags = !{ !0, !1 }
diff --git a/test/Linker/opaque.ll b/test/Linker/opaque.ll
index 1ba878c6a36f..4f3f398f8f1b 100644
--- a/test/Linker/opaque.ll
+++ b/test/Linker/opaque.ll
@@ -11,7 +11,7 @@
 ; CHECK-DAG: @g2 = external global %A
 ; CHECK-DAG: @g3 = external global %B.1
 
-; CHECK-DAG: getelementptr %A* null, i32 0
+; CHECK-DAG: getelementptr %A, %A* null, i32 0
 
 %A = type opaque
 %B = type { %C, %C, %B* }
diff --git a/test/Linker/override-different-linkage.ll b/test/Linker/override-different-linkage.ll
new file mode 100644
index 000000000000..19961f2486a0
--- /dev/null
+++ b/test/Linker/override-different-linkage.ll
@@ -0,0 +1,19 @@
+; RUN: llvm-link %s -override %S/Inputs/override-different-linkage.ll -S | FileCheck %s
+; RUN: llvm-link -override %S/Inputs/override-different-linkage.ll %s -S | FileCheck %s
+
+
+; CHECK-LABEL: define linkonce i32 @foo
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret i32 4
+define weak i32 @foo(i32 %i) {
+entry:
+  %add = add nsw i32 %i, %i
+  ret i32 %add
+}
+
+; Function Attrs: nounwind ssp uwtable
+define i32 @main(i32 %argc, i8** %argv) {
+entry:
+  %a = call i32 @foo(i32 2)
+  ret i32 %a
+}
diff --git a/test/Linker/override-with-internal-linkage-2.ll b/test/Linker/override-with-internal-linkage-2.ll
new file mode 100644
index 000000000000..45b131fe5797
--- /dev/null
+++ b/test/Linker/override-with-internal-linkage-2.ll
@@ -0,0 +1,23 @@
+; RUN: llvm-link %s -override %S/Inputs/override-with-internal-linkage-2.ll -S | FileCheck %s
+; RUN: llvm-link -override %S/Inputs/override-with-internal-linkage-2.ll %s -S | FileCheck %s
+
+; CHECK-LABEL: define i32 @foo
+; CHECK-NEXT: entry:
+; CHECK-NEXT: %add = add nsw i32 %i, %i
+; CHECK-NEXT: ret i32 %add
+define i32 @foo(i32 %i) {
+entry:
+  %add = add nsw i32 %i, %i
+  ret i32 %add
+}
+
+; CHECK-LABEL: define internal i32 @foo.1
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret i32 4
+
+; Function Attrs: nounwind ssp uwtable
+define i32 @main(i32 %argc, i8** %argv) {
+entry:
+  %a = call i32 @foo(i32 2)
+  ret i32 %a
+}
diff --git a/test/Linker/override-with-internal-linkage.ll b/test/Linker/override-with-internal-linkage.ll
new file mode 100644
index 000000000000..d3a794799322
--- /dev/null
+++ b/test/Linker/override-with-internal-linkage.ll
@@ -0,0 +1,25 @@
+; RUN: llvm-link %s -override %S/Inputs/override-with-internal-linkage.ll -S | FileCheck %s
+; RUN: llvm-link -override %S/Inputs/override-with-internal-linkage.ll %s -S | FileCheck %s
+
+; CHECK-LABEL: define i32 @main(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: call i32 @foo2(
+define i32 @main(i32 %argc, i8** %argv) {
+entry:
+  %a = call i32 @foo(i32 2)
+  ret i32 %a
+}
+
+; CHECK-LABEL: define internal i32 @foo2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: %add = add nsw i32 %i, %i
+; CHECK-NEXT: ret i32 %add
+define internal i32 @foo(i32 %i) {
+entry:
+  %add = add nsw i32 %i, %i
+  ret i32 %add
+}
+
+; CHECK-LABEL: define i32 @foo(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret i32 4
diff --git a/test/Linker/override.ll b/test/Linker/override.ll
new file mode 100644
index 000000000000..015cb4c382a9
--- /dev/null
+++ b/test/Linker/override.ll
@@ -0,0 +1,19 @@
+; RUN: llvm-link %s -override %S/Inputs/override.ll -S | FileCheck %s
+; RUN: llvm-link -override %S/Inputs/override.ll %s -S | FileCheck %s
+
+
+; CHECK-LABEL: define i32 @foo
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret i32 4
+define i32 @foo(i32 %i) {
+entry:
+  %add = add nsw i32 %i, %i
+  ret i32 %add
+}
+
+; Function Attrs: nounwind ssp uwtable
+define i32 @main(i32 %argc, i8** %argv) {
+entry:
+  %a = call i32 @foo(i32 2)
+  ret i32 %a
+}
diff --git a/test/Linker/partial-type-refinement-link.ll b/test/Linker/partial-type-refinement-link.ll
index 320ef969f83a..0c921110f9e3 100644
--- a/test/Linker/partial-type-refinement-link.ll
+++ b/test/Linker/partial-type-refinement-link.ll
@@ -15,6 +15,6 @@
 
 define void @f(%"SmallVImpl<const PI*>"* %this) {
 entry:
-  %x = getelementptr inbounds %"SmallVImpl<const PI*>"* %this, i64 0, i32 1
+  %x = getelementptr inbounds %"SmallVImpl<const PI*>", %"SmallVImpl<const PI*>"* %this, i64 0, i32 1
   ret void
 }
diff --git a/test/Linker/partial-type-refinement.ll b/test/Linker/partial-type-refinement.ll
index b995f11533fe..e9a645b077ea 100644
--- a/test/Linker/partial-type-refinement.ll
+++ b/test/Linker/partial-type-refinement.ll
@@ -1,7 +1,7 @@
 ; RUN: llvm-link %s %p/partial-type-refinement-link.ll -S | FileCheck %s
 ; PR4954
 
-; CHECK: load %PI** getelementptr inbounds (%"RegisterP<LowerArrayLength>"* @_ZN3mvmL1XE, i64 0, i32 0, i32 6, i32 0, i32 0, i32 0), align 16
+; CHECK: load %PI*, %PI** getelementptr inbounds (%"RegisterP<LowerArrayLength>", %"RegisterP<LowerArrayLength>"* @_ZN3mvmL1XE, i64 0, i32 0, i32 6, i32 0, i32 0, i32 0), align 16
 
 %AnalysisResolver = type { i8, %PMDataManager* }
 %"DenseMap<P*,AU*>" = type { i64, %"pair<P*,AU*>"*, i64, i64 }
@@ -19,6 +19,6 @@
 
 define void @__tcf_0() nounwind {
 entry:
-  %0 = load %PI** getelementptr inbounds (%"RegisterP<LowerArrayLength>"* @_ZN3mvmL1XE, i64 0, i32 0, i32 6, i32 0, i32 0, i32 0), align 16
+  %0 = load %PI*, %PI** getelementptr inbounds (%"RegisterP<LowerArrayLength>", %"RegisterP<LowerArrayLength>"* @_ZN3mvmL1XE, i64 0, i32 0, i32 6, i32 0, i32 0, i32 0), align 16
   ret void
 }
diff --git a/test/Linker/pr22807.ll b/test/Linker/pr22807.ll
new file mode 100644
index 000000000000..bb4ca2b4ccfb
--- /dev/null
+++ b/test/Linker/pr22807.ll
@@ -0,0 +1,13 @@
+; RUN: llvm-link -S -o - %p/pr22807.ll %p/Inputs/pr22807-1.ll %p/Inputs/pr22807-2.ll | FileCheck %s
+
+; CHECK-NOT: type
+; CHECK: %struct.B = type { %struct.A* }
+; CHECK-NEXT: %struct.A = type { %struct.B* }
+; CHECK-NOT: type
+
+%struct.B = type { %struct.A* }
+%struct.A = type opaque
+
+define i32 @baz(%struct.B* %BB) {
+  ret i32 0
+}
diff --git a/test/Linker/replaced-function-matches-first-subprogram.ll b/test/Linker/replaced-function-matches-first-subprogram.ll
index c0ec5f3cd228..fc7e653786e6 100644
--- a/test/Linker/replaced-function-matches-first-subprogram.ll
+++ b/test/Linker/replaced-function-matches-first-subprogram.ll
@@ -29,7 +29,7 @@ define linkonce_odr i32 @_ZN5ClassIiE3fooEv(%struct.Class* %this) align 2 {
 entry:
   %this.addr = alloca %struct.Class*, align 8
   store %struct.Class* %this, %struct.Class** %this.addr, align 8
-  %this1 = load %struct.Class** %this.addr
+  %this1 = load %struct.Class*, %struct.Class** %this.addr
   ret i32 0, !dbg !15
 }
 
@@ -39,37 +39,41 @@ entry:
 !llvm.ident = !{!13}
 
 ; Extract out the list of subprograms from each compile unit.
-; CHECK-DAG: ![[CU1]] = !{!"0x11{{[^"]+}}", {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, ![[SPs1:[0-9]+]],
-; CHECK-DAG: ![[CU2]] = !{!"0x11{{[^"]+}}", {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, ![[SPs2:[0-9]+]],
-!0 = !{!"0x11\004\00clang version 3.6.0 (trunk 224193) (llvm/trunk 224197)\000\00\000\00\002", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d1/t1.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"t1.cpp", !"/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d1"}
+; CHECK-DAG: ![[CU1]] = !DICompileUnit({{.*}} subprograms: ![[SPs1:[0-9]+]]
+; CHECK-DAG: ![[CU2]] = !DICompileUnit({{.*}} subprograms: ![[SPs2:[0-9]+]]
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 (trunk 224193) (llvm/trunk 224197)", isOptimized: false, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "t1.cpp", directory: "/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d1")
 !2 = !{}
 
-; Extract out each compile unit's single subprogram.  The replaced subprogram
-; should be dropped by the first compile unit.
-; CHECK-DAG: ![[SPs1]] = !{![[SP1:[0-9]+]]}
+; Extract out each compile unit's single subprogram.  The replaced subprogram's
+; function should drop to null in the first compile unit.
+; CHECK-DAG: ![[SPs1]] = !{![[SP1:[0-9]+]], ![[SP2r:[0-9]+]]}
 ; CHECK-DAG: ![[SPs2]] = !{![[SP2:[0-9]+]]}
 !3 = !{!4, !7}
-!4 = !{!"0x2e\00foo\00foo\00\002\000\001\000\000\00256\000\002", !1, !5, !6, null, i32 ()* @_Z3foov, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [foo]
-!5 = !{!"0x29", !1}    ; [ DW_TAG_file_type ] [/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d1/t1.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 2, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !6, function: i32 ()* @_Z3foov, variables: !2)
+!5 = !DIFile(filename: "t1.cpp", directory: "/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d1")
+!6 = !DISubroutineType(types: !2)
 
 ; Extract out the file from the replaced subprogram.  Confirm that each
 ; subprogram is pointing at the correct function.
-; CHECK-DAG: ![[SP1]] = !{!"0x2e{{[^"]+}}", {{.*}}, i32 ()* @_Z3foov,
-; CHECK-DAG: ![[SP2]] = !{!"0x2e{{[^"]+}}", ![[FILE:[0-9]+]], {{.*}}, i32 (%struct.Class*)* @_ZN5ClassIiE3fooEv,
-!7 = !{!"0x2e\00foo\00foo\00\002\000\001\000\000\00256\000\002", !8, !9, !6, null, i32 (%struct.Class*)* @_ZN5ClassIiE3fooEv, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [foo]
+; CHECK-DAG: ![[SP1]] = !DISubprogram({{.*}} function: i32 ()* @_Z3foov
+; CHECK-DAG: ![[SP2]] = !DISubprogram({{.*}} file: ![[FILE:[0-9]+]],{{.*}} function: i32 (%struct.Class*)* @_ZN5ClassIiE3fooEv
+
+; We can't use CHECK-NOT/CHECK-SAME with a CHECK-DAG, so rely on field order to
+; prove that there's no function: here.
+; CHECK-DAG: ![[SP2r]] = {{.*}}!DISubprogram({{.*}} isOptimized: false, variables:
+!7 = !DISubprogram(name: "foo", line: 2, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !8, scope: !9, type: !6, function: i32 (%struct.Class*)* @_ZN5ClassIiE3fooEv, variables: !2)
 
 ; The new subprogram should be pointing at the new directory.
-; CHECK-DAG: ![[FILE]] = !{!"../t.h", !"/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d2"}
-!8 = !{!"../t.h", !"/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d1"}
-!9 = !{!"0x29", !8}    ; [ DW_TAG_file_type ] [/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d1/../t.h]
+; CHECK-DAG: ![[FILE]] = !DIFile(filename: "../t.h", directory: "/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d2")
+!8 = !DIFile(filename: "../t.h", directory: "/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d1")
+!9 = !DIFile(filename: "../t.h", directory: "/Users/dexonsmith/data/llvm/staging/test/Linker/repro/d1")
 !10 = !{i32 2, !"Dwarf Version", i32 2}
-!11 = !{i32 2, !"Debug Info Version", i32 2}
+!11 = !{i32 2, !"Debug Info Version", i32 3}
 !12 = !{i32 1, !"PIC Level", i32 2}
 !13 = !{!"clang version 3.6.0 (trunk 224193) (llvm/trunk 224197)"}
-!14 = !MDLocation(line: 2, column: 20, scope: !4)
+!14 = !DILocation(line: 2, column: 20, scope: !4)
 
 ; The same subprogram should be pointed to by inside the !dbg reference.
-; CHECK: ![[LOC]] = !MDLocation(line: 2, column: 15, scope: ![[SP2]])
-!15 = !MDLocation(line: 2, column: 15, scope: !7)
+; CHECK: ![[LOC]] = !DILocation(line: 2, column: 15, scope: ![[SP2]])
+!15 = !DILocation(line: 2, column: 15, scope: !7)
diff --git a/test/Linker/subprogram-linkonce-weak-odr.ll b/test/Linker/subprogram-linkonce-weak-odr.ll
new file mode 100644
index 000000000000..c1fa0a5adeb5
--- /dev/null
+++ b/test/Linker/subprogram-linkonce-weak-odr.ll
@@ -0,0 +1,177 @@
+; RUN: llvm-link %s %S/Inputs/subprogram-linkonce-weak-odr.ll -S -o %t1
+; RUN: FileCheck %s -check-prefix=LW -check-prefix=CHECK <%t1
+; RUN: llvm-link %S/Inputs/subprogram-linkonce-weak-odr.ll %s -S -o %t2
+; RUN: FileCheck %s -check-prefix=WL -check-prefix=CHECK <%t2
+
+; This testcase tests the following flow:
+;  - File A defines a linkonce_odr version of @foo which has inlined into @bar.
+;  - File B defines a weak_odr version of @foo (identical definition).
+;  - Linkage rules state File B version of @foo wins.
+;  - Debug info for the subprograms of @foo match exactly.  Without
+;    intervention, the same subprogram would show up in both compile units, and
+;    it would get associated with the compile unit where it was linkonce.
+;  - @bar has inlined debug info related to the linkonce_odr @foo.
+;
+; This checks a corner case for the fix for PR22792, where subprograms match
+; exactly.  It's a companion for subprogram-linkonce-weak.ll.
+
+; The LW prefix means linkonce (this file) first, then weak (the other file).
+; The WL prefix means weak (the other file) first, then linkonce (this file).
+
+; We'll see @bar before @foo if this file is first.
+; LW-LABEL: define i32 @bar(
+; LW: %sum = add i32 %a, %b, !dbg ![[FOOINBAR:[0-9]+]]
+; LW: ret i32 %sum, !dbg ![[BARRET:[0-9]+]]
+; LW-LABEL: define weak_odr i32 @foo(
+; LW: %sum = add i32 %a, %b, !dbg ![[FOOADD:[0-9]+]]
+; LW: ret i32 %sum, !dbg ![[FOORET:[0-9]+]]
+
+; We'll see @foo before @bar if this file is second.
+; WL-LABEL: define weak_odr i32 @foo(
+; WL: %sum = add i32 %a, %b, !dbg ![[FOOADD:[0-9]+]]
+; WL: ret i32 %sum, !dbg ![[FOORET:[0-9]+]]
+; WL-LABEL: define i32 @bar(
+; WL: %sum = add i32 %a, %b, !dbg ![[FOOINBAR:[0-9]+]]
+; WL: ret i32 %sum, !dbg ![[BARRET:[0-9]+]]
+
+define i32 @bar(i32 %a, i32 %b) {
+entry:
+  %sum = add i32 %a, %b, !dbg !DILocation(line: 2, scope: !4,
+                                          inlinedAt: !DILocation(line: 12, scope: !3))
+  ret i32 %sum, !dbg !DILocation(line: 13, scope: !3)
+}
+
+define linkonce_odr i32 @foo(i32 %a, i32 %b) {
+entry:
+  %sum = add i32 %a, %b, !dbg !DILocation(line: 2, scope: !4)
+  ret i32 %sum, !dbg !DILocation(line: 3, scope: !4)
+}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+
+; CHECK-LABEL: !llvm.dbg.cu =
+; LW-SAME: !{![[LCU:[0-9]+]], ![[WCU:[0-9]+]]}
+; WL-SAME: !{![[WCU:[0-9]+]], ![[LCU:[0-9]+]]}
+!llvm.dbg.cu = !{!1}
+
+; LW: ![[LCU]] = !DICompileUnit({{.*}} subprograms: ![[LSPs:[0-9]+]]
+; LW: ![[LSPs]] = !{![[BARSP:[0-9]+]], ![[FOOSP:[0-9]+]]}
+; LW: ![[BARSP]] = !DISubprogram(name: "bar",
+; LW-SAME: function: i32 (i32, i32)* @bar
+; LW: ![[FOOSP]] = {{.*}}!DISubprogram(name: "foo",
+; LW-NOT: function:
+; LW-SAME: ){{$}}
+; LW: ![[WCU]] = !DICompileUnit({{.*}} subprograms: ![[WSPs:[0-9]+]]
+; LW: ![[WSPs]] = !{![[WEAKFOOSP:[0-9]+]]}
+; LW: ![[WEAKFOOSP]] = !DISubprogram(name: "foo",
+; LW-SAME: function: i32 (i32, i32)* @foo
+; LW: ![[FOOINBAR]] = !DILocation(line: 2, scope: ![[FOOSP]], inlinedAt: ![[BARIA:[0-9]+]])
+; LW: ![[BARIA]] = !DILocation(line: 12, scope: ![[BARSP]])
+; LW: ![[BARRET]] = !DILocation(line: 13, scope: ![[BARSP]])
+; LW: ![[FOOADD]] = !DILocation(line: 2, scope: ![[WEAKFOOSP]])
+; LW: ![[FOORET]] = !DILocation(line: 3, scope: ![[WEAKFOOSP]])
+
+; Same as above, but reordered.
+; WL: ![[WCU]] = !DICompileUnit({{.*}} subprograms: ![[WSPs:[0-9]+]]
+; WL: ![[WSPs]] = !{![[WEAKFOOSP:[0-9]+]]}
+; WL: ![[WEAKFOOSP]] = !DISubprogram(name: "foo",
+; WL-SAME: function: i32 (i32, i32)* @foo
+; WL: ![[LCU]] = !DICompileUnit({{.*}} subprograms: ![[LSPs:[0-9]+]]
+; Note: for symmetry, LSPs would have a different copy of the subprogram.
+; WL: ![[LSPs]] = !{![[BARSP:[0-9]+]], ![[WEAKFOOSP:[0-9]+]]}
+; WL: ![[BARSP]] = !DISubprogram(name: "bar",
+; WL-SAME: function: i32 (i32, i32)* @bar
+; WL: ![[FOOADD]] = !DILocation(line: 2, scope: ![[WEAKFOOSP]])
+; WL: ![[FOORET]] = !DILocation(line: 3, scope: ![[WEAKFOOSP]])
+; WL: ![[FOOINBAR]] = !DILocation(line: 2, scope: ![[WEAKFOOSP]], inlinedAt: ![[BARIA:[0-9]+]])
+; WL: ![[BARIA]] = !DILocation(line: 12, scope: ![[BARSP]])
+; WL: ![[BARRET]] = !DILocation(line: 13, scope: ![[BARSP]])
+
+!1 = !DICompileUnit(language: DW_LANG_C99, file: !2, subprograms: !{!3, !4}, emissionKind: 1)
+!2 = !DIFile(filename: "bar.c", directory: "/path/to/dir")
+!3 = !DISubprogram(file: !2, scope: !2, line: 11, name: "bar", function: i32 (i32, i32)* @bar, type: !6)
+!4 = !DISubprogram(file: !5, scope: !5, line: 1, name: "foo", function: i32 (i32, i32)* @foo, type: !6)
+!5 = !DIFile(filename: "foo.h", directory: "/path/to/dir")
+!6 = !DISubroutineType(types: !{})
+
+; Crasher for llc.
+; REQUIRES: object-emission
+; RUN: %llc_dwarf -filetype=obj -O0 %t1 -o %t1.o
+; RUN: llvm-dwarfdump %t1.o -debug-dump=all | FileCheck %s -check-prefix=DWLW -check-prefix=DW
+; RUN: %llc_dwarf -filetype=obj -O0 %t2 -o %t2.o
+; RUN: llvm-dwarfdump %t2.o -debug-dump=all | FileCheck %s -check-prefix=DWWL -check-prefix=DW
+; Check that the debug info puts the subprogram (with PCs) in the correct
+; compile unit.
+
+; DW-LABEL: .debug_info contents:
+; DWLW:     DW_TAG_compile_unit
+; DWLW:       DW_AT_name {{.*}}"bar.c"
+; Note: If we stop emitting foo here, the comment below for DWWL (and the
+; check) should be copied up here.
+; DWLW:       DW_TAG_subprogram
+; DWLW-NOT:     DW_AT_low_pc
+; DWLW-NOT:     DW_AT_high_pc
+; DWLW:         DW_AT_name {{.*}}foo
+; DWLW:         DW_AT_decl_file {{.*}}"/path/to/dir{{/|\\}}foo.h"
+; DWLW:         DW_AT_decl_line {{.*}}(1)
+; DWLW:       DW_TAG_subprogram
+; DWLW:         DW_AT_low_pc
+; DWLW:         DW_AT_high_pc
+; DWLW:         DW_AT_name {{.*}}bar
+; DWLW:         DW_AT_decl_file {{.*}}"/path/to/dir{{/|\\}}bar.c"
+; DWLW:         DW_AT_decl_line {{.*}}(11)
+; DWLW:         DW_TAG_inlined_subroutine
+; DWLW:           DW_AT_abstract_origin
+; DWLW:     DW_TAG_compile_unit
+; DWLW:       DW_AT_name {{.*}}"foo.c"
+; DWLW:       DW_TAG_subprogram
+; DWLW:         DW_AT_low_pc
+; DWLW:         DW_AT_high_pc
+; DWLW:         DW_AT_name {{.*}}foo
+; DWLW:         DW_AT_decl_file {{.*}}"/path/to/dir{{/|\\}}foo.h"
+; DWLW:         DW_AT_decl_line {{.*}}(1)
+
+; The DWARF output is already symmetric (just reordered).
+; DWWL:     DW_TAG_compile_unit
+; DWWL:       DW_AT_name {{.*}}"foo.c"
+; DWWL:       DW_TAG_subprogram
+; DWWL:         DW_AT_low_pc
+; DWWL:         DW_AT_high_pc
+; DWWL:         DW_AT_name {{.*}}foo
+; DWWL:         DW_AT_decl_file {{.*}}"/path/to/dir{{/|\\}}foo.h"
+; DWWL:         DW_AT_decl_line {{.*}}(1)
+; DWWL:     DW_TAG_compile_unit
+; DWWL:       DW_AT_name {{.*}}"bar.c"
+; Note: for symmetry, foo would also show up in this compile unit
+; (alternatively, it wouldn't show up in the DWLW case).  If we start emitting
+; foo here, this should be updated by checking that we don't emit low_pc and
+; high_pc for it.
+; DWWL-NOT:     DW_AT_name {{.*}}foo
+; DWWL:       DW_TAG_subprogram
+; DWWL-NOT:     DW_AT_name {{.*}}foo
+; DWWL:         DW_AT_low_pc
+; DWWL:         DW_AT_high_pc
+; DWWL-NOT:     DW_AT_name {{.*}}foo
+; DWWL:         DW_AT_name {{.*}}bar
+; DWWL:         DW_AT_decl_file {{.*}}"/path/to/dir{{/|\\}}bar.c"
+; DWWL:         DW_AT_decl_line {{.*}}(11)
+; DWWL:         DW_TAG_inlined_subroutine
+; DWWL:           DW_AT_abstract_origin
+
+; DW-LABEL:   .debug_line contents:
+; Check that we have the right things in the line table as well.
+
+; DWLW-LABEL: file_names[{{ *}}1]{{.*}} bar.c
+; DWLW-LABEL: file_names[{{ *}}2]{{.*}} foo.h
+; DWLW:        2 0 2 0 0 is_stmt prologue_end
+; DWLW-LABEL: file_names[{{ *}}1]{{.*}} foo.h
+; DWLW:        2 0 1 0 0 is_stmt prologue_end
+; DWLW-NOT:                      prologue_end
+
+; DWWL-LABEL: file_names[{{ *}}1]{{.*}} foo.h
+; DWWL:        2 0 1 0 0 is_stmt prologue_end
+; DWWL-LABEL: file_names[{{ *}}1]{{.*}} bar.c
+; DWWL-LABEL: file_names[{{ *}}2]{{.*}} foo.h
+; DWWL:        2 0 2 0 0 is_stmt prologue_end
+; DWWL-NOT:                      prologue_end
diff --git a/test/Linker/subprogram-linkonce-weak.ll b/test/Linker/subprogram-linkonce-weak.ll
new file mode 100644
index 000000000000..598cea7afeb0
--- /dev/null
+++ b/test/Linker/subprogram-linkonce-weak.ll
@@ -0,0 +1,171 @@
+; RUN: llvm-link %s %S/Inputs/subprogram-linkonce-weak.ll -S -o %t1
+; RUN: FileCheck %s -check-prefix=LW -check-prefix=CHECK <%t1
+; RUN: llvm-link %S/Inputs/subprogram-linkonce-weak.ll %s -S -o %t2
+; RUN: FileCheck %s -check-prefix=WL -check-prefix=CHECK <%t2
+
+; This testcase tests the following flow:
+;  - File A defines a linkonce version of @foo which has inlined into @bar.
+;  - File B defines a weak version of @foo (different definition).
+;  - Linkage rules state File B version of @foo wins.
+;  - @bar still has inlined debug info related to the linkonce @foo.
+;
+; This should fix PR22792, although the testcase was hand-written.  There's a
+; RUN line with a crasher for llc at the end with checks for the DWARF output.
+
+; The LW prefix means linkonce (this file) first, then weak (the other file).
+; The WL prefix means weak (the other file) first, then linkonce (this file).
+
+; We'll see @bar before @foo if this file is first.
+; LW-LABEL: define i32 @bar(
+; LW: %sum = add i32 %a, %b, !dbg ![[FOOINBAR:[0-9]+]]
+; LW: ret i32 %sum, !dbg ![[BARRET:[0-9]+]]
+; LW-LABEL: define weak i32 @foo(
+; LW: %sum = call i32 @fastadd(i32 %a, i32 %b), !dbg ![[FOOCALL:[0-9]+]]
+; LW: ret i32 %sum, !dbg ![[FOORET:[0-9]+]]
+
+; We'll see @foo before @bar if this file is second.
+; WL-LABEL: define weak i32 @foo(
+; WL: %sum = call i32 @fastadd(i32 %a, i32 %b), !dbg ![[FOOCALL:[0-9]+]]
+; WL: ret i32 %sum, !dbg ![[FOORET:[0-9]+]]
+; WL-LABEL: define i32 @bar(
+; WL: %sum = add i32 %a, %b, !dbg ![[FOOINBAR:[0-9]+]]
+; WL: ret i32 %sum, !dbg ![[BARRET:[0-9]+]]
+
+define i32 @bar(i32 %a, i32 %b) {
+entry:
+  %sum = add i32 %a, %b, !dbg !DILocation(line: 2, scope: !4,
+                                          inlinedAt: !DILocation(line: 12, scope: !3))
+  ret i32 %sum, !dbg !DILocation(line: 13, scope: !3)
+}
+
+define linkonce i32 @foo(i32 %a, i32 %b) {
+entry:
+  %sum = add i32 %a, %b, !dbg !DILocation(line: 2, scope: !4)
+  ret i32 %sum, !dbg !DILocation(line: 3, scope: !4)
+}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+
+; CHECK-LABEL: !llvm.dbg.cu =
+; LW-SAME: !{![[LCU:[0-9]+]], ![[WCU:[0-9]+]]}
+; WL-SAME: !{![[WCU:[0-9]+]], ![[LCU:[0-9]+]]}
+!llvm.dbg.cu = !{!1}
+
+; LW: ![[LCU]] = !DICompileUnit({{.*}} subprograms: ![[LSPs:[0-9]+]]
+; LW: ![[LSPs]] = !{![[BARSP:[0-9]+]], ![[FOOSP:[0-9]+]]}
+; LW: ![[BARSP]] = !DISubprogram(name: "bar",
+; LW-SAME: function: i32 (i32, i32)* @bar
+; LW: ![[FOOSP]] = {{.*}}!DISubprogram(name: "foo",
+; LW-NOT: function:
+; LW-SAME: ){{$}}
+; LW: ![[WCU]] = !DICompileUnit({{.*}} subprograms: ![[WSPs:[0-9]+]]
+; LW: ![[WSPs]] = !{![[WEAKFOOSP:[0-9]+]]}
+; LW: ![[WEAKFOOSP]] = !DISubprogram(name: "foo",
+; LW-SAME: function: i32 (i32, i32)* @foo
+; LW: ![[FOOINBAR]] = !DILocation(line: 2, scope: ![[FOOSP]], inlinedAt: ![[BARIA:[0-9]+]])
+; LW: ![[BARIA]] = !DILocation(line: 12, scope: ![[BARSP]])
+; LW: ![[BARRET]] = !DILocation(line: 13, scope: ![[BARSP]])
+; LW: ![[FOOCALL]] = !DILocation(line: 52, scope: ![[WEAKFOOSP]])
+; LW: ![[FOORET]] = !DILocation(line: 53, scope: ![[WEAKFOOSP]])
+
+; Same as above, but reordered.
+; WL: ![[WCU]] = !DICompileUnit({{.*}} subprograms: ![[WSPs:[0-9]+]]
+; WL: ![[WSPs]] = !{![[WEAKFOOSP:[0-9]+]]}
+; WL: ![[WEAKFOOSP]] = !DISubprogram(name: "foo",
+; WL-SAME: function: i32 (i32, i32)* @foo
+; WL: ![[LCU]] = !DICompileUnit({{.*}} subprograms: ![[LSPs:[0-9]+]]
+; WL: ![[LSPs]] = !{![[BARSP:[0-9]+]], ![[FOOSP:[0-9]+]]}
+; WL: ![[BARSP]] = !DISubprogram(name: "bar",
+; WL-SAME: function: i32 (i32, i32)* @bar
+; WL: ![[FOOSP]] = {{.*}}!DISubprogram(name: "foo",
+; Note, for symmetry, this should be "NOT: function:" and "SAME: ){{$}}".
+; WL-SAME: function: i32 (i32, i32)* @foo
+; WL: ![[FOOCALL]] = !DILocation(line: 52, scope: ![[WEAKFOOSP]])
+; WL: ![[FOORET]] = !DILocation(line: 53, scope: ![[WEAKFOOSP]])
+; WL: ![[FOOINBAR]] = !DILocation(line: 2, scope: ![[FOOSP]], inlinedAt: ![[BARIA:[0-9]+]])
+; WL: ![[BARIA]] = !DILocation(line: 12, scope: ![[BARSP]])
+; WL: ![[BARRET]] = !DILocation(line: 13, scope: ![[BARSP]])
+
+!1 = !DICompileUnit(language: DW_LANG_C99, file: !2, subprograms: !{!3, !4}, emissionKind: 1)
+!2 = !DIFile(filename: "bar.c", directory: "/path/to/dir")
+!3 = !DISubprogram(file: !2, scope: !2, line: 11, name: "bar", function: i32 (i32, i32)* @bar, type: !5)
+!4 = !DISubprogram(file: !2, scope: !2, line: 1, name: "foo", function: i32 (i32, i32)* @foo, type: !5)
+!5 = !DISubroutineType(types: !{})
+
+; Crasher for llc.
+; REQUIRES: object-emission
+; RUN: %llc_dwarf -filetype=obj -O0 %t1 -o %t1.o
+; RUN: llvm-dwarfdump %t1.o -debug-dump=all | FileCheck %s -check-prefix=DWLW -check-prefix=DW
+; RUN: %llc_dwarf -filetype=obj -O0 %t2 -o %t2.o
+; RUN: llvm-dwarfdump %t2.o -debug-dump=all | FileCheck %s -check-prefix=DWWL -check-prefix=DW
+; Check that the debug info for the discarded linkonce version of @foo doesn't
+; reference any code, and that the other subprograms look correct.
+
+; DW-LABEL: .debug_info contents:
+; DWLW:     DW_TAG_compile_unit
+; DWLW:       DW_AT_name {{.*}}"bar.c"
+; DWLW:       DW_TAG_subprogram
+; DWLW-NOT:     DW_AT_low_pc
+; DWLW-NOT:     DW_AT_high_pc
+; DWLW:         DW_AT_name {{.*}}foo
+; DWLW:         DW_AT_decl_file {{.*}}"/path/to/dir{{/|\\}}bar.c"
+; DWLW:         DW_AT_decl_line {{.*}}(1)
+; DWLW:       DW_TAG_subprogram
+; DWLW:         DW_AT_low_pc
+; DWLW:         DW_AT_high_pc
+; DWLW:         DW_AT_name {{.*}}bar
+; DWLW:         DW_AT_decl_file {{.*}}"/path/to/dir{{/|\\}}bar.c"
+; DWLW:         DW_AT_decl_line {{.*}}(11)
+
+; DWLW:         DW_TAG_inlined_subroutine
+; DWLW:           DW_AT_abstract_origin
+; DWLW:     DW_TAG_compile_unit
+; DWLW:       DW_AT_name {{.*}}"foo.c"
+; DWLW:       DW_TAG_subprogram
+; DWLW:         DW_AT_low_pc
+; DWLW:         DW_AT_high_pc
+; DWLW:         DW_AT_name {{.*}}foo
+; DWLW:         DW_AT_decl_file {{.*}}"/path/to/dir{{/|\\}}foo.c"
+; DWLW:         DW_AT_decl_line {{.*}}(51)
+
+; The DWARF output is already symmetric (just reordered).
+; DWWL:     DW_TAG_compile_unit
+; DWWL:       DW_AT_name {{.*}}"foo.c"
+; DWWL:       DW_TAG_subprogram
+; DWWL:         DW_AT_low_pc
+; DWWL:         DW_AT_high_pc
+; DWWL:         DW_AT_name {{.*}}foo
+; DWWL:         DW_AT_decl_file {{.*}}"/path/to/dir{{/|\\}}foo.c"
+; DWWL:         DW_AT_decl_line {{.*}}(51)
+; DWWL:     DW_TAG_compile_unit
+; DWWL:       DW_AT_name {{.*}}"bar.c"
+; DWWL:       DW_TAG_subprogram
+; DWWL-NOT:     DW_AT_low_pc
+; DWWL-NOT:     DW_AT_high_pc
+; DWWL:         DW_AT_name {{.*}}foo
+; DWWL:         DW_AT_decl_file {{.*}}"/path/to/dir{{/|\\}}bar.c"
+; DWWL:         DW_AT_decl_line {{.*}}(1)
+; DWWL:       DW_TAG_subprogram
+; DWWL:         DW_AT_low_pc
+; DWWL:         DW_AT_high_pc
+; DWWL:         DW_AT_name {{.*}}bar
+; DWWL:         DW_AT_decl_file {{.*}}"/path/to/dir{{/|\\}}bar.c"
+; DWWL:         DW_AT_decl_line {{.*}}(11)
+; DWWL:         DW_TAG_inlined_subroutine
+; DWWL:           DW_AT_abstract_origin
+
+; DW-LABEL:   .debug_line contents:
+; Check that we have the right things in the line table as well.
+
+; DWLW-LABEL: file_names[{{ *}}1]{{.*}} bar.c
+; DWLW:        2 0 1 0 0 is_stmt prologue_end
+; DWLW-LABEL: file_names[{{ *}}1]{{.*}} foo.c
+; DWLW:       52 0 1 0 0 is_stmt prologue_end
+; DWLW-NOT:                      prologue_end
+
+; DWWL-LABEL: file_names[{{ *}}1]{{.*}} foo.c
+; DWWL:       52 0 1 0 0 is_stmt prologue_end
+; DWWL-LABEL: file_names[{{ *}}1]{{.*}} bar.c
+; DWWL:        2 0 1 0 0 is_stmt prologue_end
+; DWWL-NOT:                      prologue_end
diff --git a/test/Linker/targettriple.ll b/test/Linker/targettriple.ll
index c544a14a19d3..a159797856c8 100644
--- a/test/Linker/targettriple.ll
+++ b/test/Linker/targettriple.ll
@@ -1,17 +1,22 @@
-; REQUIRES: shell
 ; RUN: llvm-link %s %S/Inputs/targettriple-a.ll -S -o - 2>%t.a.err | FileCheck %s
-; RUN: (echo foo ;cat %t.a.err) | FileCheck --check-prefix=WARN-A %s
+; RUN: cat %t.a.err | FileCheck --check-prefix=WARN-A %s --allow-empty
 
 ; RUN: llvm-link %s %S/Inputs/targettriple-b.ll -S -o - 2>%t.b.err | FileCheck %s
 ; RUN: cat %t.b.err | FileCheck --check-prefix=WARN-B %s
+; RUN: llvm-link %s %S/Inputs/targettriple-c.ll -S -o - 2>%t.c.err | FileCheck %s
+; RUN: cat %t.c.err | FileCheck --check-prefix=WARN-C %s --allow-empty
 
 ; RUN: llvm-link -suppress-warnings %s %S/Inputs/targettriple-b.ll -S -o - 2>%t.no-warn.err | FileCheck %s
-; RUN: (echo foo ;cat %t.no-warn.err) | FileCheck --check-prefix=WARN-A %s
+; RUN: cat %t.no-warn.err | FileCheck --check-prefix=WARN-A %s --allow-empty
 
-target triple = "e"
+target triple = "x86_64-unknown-linux-gnu"
 
-; CHECK: target triple = "e"
+; CHECK: target triple = "x86_64-unknown-linux-gnu"
 
 ; WARN-A-NOT: WARNING
 
+; i386 and x86_64 map to different ArchType enums.
 ; WARN-B: WARNING: Linking two modules of different target triples:
+
+; x86_64h and x86_64 map to the same ArchType enum.
+; WARN-C-NOT: WARNING
diff --git a/test/Linker/testlink.ll b/test/Linker/testlink.ll
index aad4b9bfb07a..2e9447ddfd37 100644
--- a/test/Linker/testlink.ll
+++ b/test/Linker/testlink.ll
@@ -61,7 +61,7 @@
 @AConst = linkonce constant i32 123
 
 ; Renamed version of Intern1.
-; CHECK-DAG: @Intern1{{[0-9]+}} = internal constant i32 52
+; CHECK-DAG: @Intern1.{{[0-9]+}} = internal constant i32 52
 
 
 ; Globals linked from testlink2.
@@ -76,15 +76,15 @@ declare i32 @foo(i32)
 declare void @print(i32)
 
 define void @main() {
-  %v1 = load i32* @MyVar
+  %v1 = load i32, i32* @MyVar
   call void @print(i32 %v1)
-  %idx = getelementptr %intlist* @MyIntList, i64 0, i32 1
-  %v2 = load i32* %idx
+  %idx = getelementptr %intlist, %intlist* @MyIntList, i64 0, i32 1
+  %v2 = load i32, i32* %idx
   call void @print(i32 %v2)
   %1 = call i32 @foo(i32 5)
-  %v3 = load i32* @MyVar
+  %v3 = load i32, i32* @MyVar
   call void @print(i32 %v3)
-  %v4 = load i32* %idx
+  %v4 = load i32, i32* %idx
   call void @print(i32 %v4)
   ret void
 }
diff --git a/test/Linker/type-unique-odr-a.ll b/test/Linker/type-unique-odr-a.ll
index 900b03592647..fa6b6bb4f221 100644
--- a/test/Linker/type-unique-odr-a.ll
+++ b/test/Linker/type-unique-odr-a.ll
@@ -30,15 +30,15 @@
 ; CHECK-NOT:  DW_TAG
 ; CHECK:      DW_TAG_subprogram
 ; CHECK-NOT: DW_TAG
-; CHECK:   DW_AT_MIPS_linkage_name {{.*}} "_ZN1A6getFooEv"
+; CHECK:   DW_AT_linkage_name {{.*}} "_ZN1A6getFooEv"
 ; CHECK-NOT: DW_TAG
 ; CHECK:   DW_AT_name {{.*}} "getFoo"
 ; CHECK:      DW_TAG_subprogram
 ; CHECK-NOT: DW_TAG
-; CHECK:   DW_AT_MIPS_linkage_name {{.*}} "_Z3bazv"
+; CHECK:   DW_AT_linkage_name {{.*}} "_Z3bazv"
 ; CHECK:      DW_TAG_subprogram
 ; CHECK-NOT: DW_TAG
-; CHECK:   DW_AT_MIPS_linkage_name {{.*}} "_ZL3barv"
+; CHECK:   DW_AT_linkage_name {{.*}} "_ZL3barv"
 
 ; getFoo and A may only appear once.
 ; CHECK-NOT:  AT_name{{.*(getFoo)|("A")}}
@@ -59,7 +59,7 @@ entry:
 define internal void @_ZL3barv() #0 {
 entry:
   %a = alloca %class.A, align 4
-  call void @llvm.dbg.declare(metadata %class.A* %a, metadata !24, metadata !{!"0x102"}), !dbg !25
+  call void @llvm.dbg.declare(metadata %class.A* %a, metadata !24, metadata !DIExpression()), !dbg !25
   ret void, !dbg !26
 }
 
@@ -73,30 +73,29 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!20, !21}
 !llvm.ident = !{!22}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !3, !14, !2, !2} ; [ DW_TAG_compile_unit ] [<unknown>] [DW_LANG_C_plus_plus]
-!1 = !{!"<unknown>", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !14, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<unknown>", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2\00A\001\0032\0032\000\000\000", !5, null, null, !6, null, null, !"_ZTS1A"} ; [ DW_TAG_class_type ] [A] [line 1, size 32, align 32, offset 0] [def] [from ]
-!5 = !{!"type-unique-odr-a.cpp", !""}
+!4 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 1, size: 32, align: 32, file: !5, elements: !6, identifier: "_ZTS1A")
+!5 = !DIFile(filename: "type-unique-odr-a.cpp", directory: "")
 !6 = !{!7, !9}
-!7 = !{!"0xd\00data\002\0032\0032\000\001", !5, !"_ZTS1A", !8} ; [ DW_TAG_member ] [data] [line 2, size 32, align 32, offset 0] [private] [from int]
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x2e\00getFoo\00getFoo\00_ZN1A6getFooEv\004\000\000\000\006\00258\000\004", !5, !"_ZTS1A", !10, null, null, null, i32 0, !13} ; [ DW_TAG_subprogram ] [line 4] [protected] [getFoo]
-!10 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "data", line: 2, size: 32, align: 32, flags: DIFlagPrivate, file: !5, scope: !"_ZTS1A", baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DISubprogram(name: "getFoo", linkageName: "_ZN1A6getFooEv", line: 4, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagProtected | DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !5, scope: !"_ZTS1A", type: !10)
+!10 = !DISubroutineType(types: !11)
 !11 = !{null, !12}
-!12 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1A]
-!13 = !{i32 786468}
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1A")
 !14 = !{!15, !19}
-!15 = !{!"0x2e\00baz\00baz\00_Z3bazv\0011\000\001\000\006\00256\000\0011", !5, !16, !17, null, void ()* @_Z3bazv, null, null, !2} ; [ DW_TAG_subprogram ] [line 11] [def] [baz]
-!16 = !{!"0x29", !5}         ; [ DW_TAG_file_type ] [type-unique-odr-a.cpp]
-!17 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !18, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!15 = !DISubprogram(name: "baz", linkageName: "_Z3bazv", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 11, file: !5, scope: !16, type: !17, function: void ()* @_Z3bazv, variables: !2)
+!16 = !DIFile(filename: "type-unique-odr-a.cpp", directory: "")
+!17 = !DISubroutineType(types: !18)
 !18 = !{null}
-!19 = !{!"0x2e\00bar\00bar\00_ZL3barv\007\001\001\000\006\00256\000\007", !5, !16, !17, null, void ()* @_ZL3barv, null, null, !2} ; [ DW_TAG_subprogram ] [line 7] [local] [def] [bar]
+!19 = !DISubprogram(name: "bar", linkageName: "_ZL3barv", line: 7, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !5, scope: !16, type: !17, function: void ()* @_ZL3barv, variables: !2)
 !20 = !{i32 2, !"Dwarf Version", i32 4}
-!21 = !{i32 1, !"Debug Info Version", i32 2}
+!21 = !{i32 1, !"Debug Info Version", i32 3}
 !22 = !{!"clang version 3.5.0 "}
-!23 = !MDLocation(line: 11, scope: !15)
-!24 = !{!"0x100\00a\008\000", !19, !16, !"_ZTS1A"} ; [ DW_TAG_auto_variable ] [a] [line 8]
-!25 = !MDLocation(line: 8, scope: !19)
-!26 = !MDLocation(line: 9, scope: !19)
+!23 = !DILocation(line: 11, scope: !15)
+!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", line: 8, scope: !19, file: !16, type: !"_ZTS1A")
+!25 = !DILocation(line: 8, scope: !19)
+!26 = !DILocation(line: 9, scope: !19)
diff --git a/test/Linker/type-unique-odr-b.ll b/test/Linker/type-unique-odr-b.ll
index b262191b91fc..f57c21da824b 100644
--- a/test/Linker/type-unique-odr-b.ll
+++ b/test/Linker/type-unique-odr-b.ll
@@ -26,8 +26,8 @@ define void @_ZN1A6getFooEv(%class.A* %this) #0 align 2 {
 entry:
   %this.addr = alloca %class.A*, align 8
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !24, metadata !{!"0x102"}), !dbg !26
-  %this1 = load %class.A** %this.addr
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !24, metadata !DIExpression()), !dbg !26
+  %this1 = load %class.A*, %class.A** %this.addr
   ret void, !dbg !27
 }
 
@@ -54,33 +54,32 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!21, !22}
 !llvm.ident = !{!23}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !3, !14, !2, !2} ; [ DW_TAG_compile_unit ] [<unknown>] [DW_LANG_C_plus_plus]
-!1 = !{!"<unknown>", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !14, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<unknown>", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2\00A\002\0032\0032\000\000\000", !5, null, null, !6, null, null, !"_ZTS1A"} ; [ DW_TAG_class_type ] [A] [line 2, size 32, align 32, offset 0] [def] [from ]
-!5 = !{!"type-unique-odr-b.cpp", !""}
+!4 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 2, size: 32, align: 32, file: !5, elements: !6, identifier: "_ZTS1A")
+!5 = !DIFile(filename: "type-unique-odr-b.cpp", directory: "")
 !6 = !{!7, !9}
-!7 = !{!"0xd\00data\003\0032\0032\000\001", !5, !"_ZTS1A", !8} ; [ DW_TAG_member ] [data] [line 3, size 32, align 32, offset 0] [private] [from int]
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x2e\00getFoo\00getFoo\00_ZN1A6getFooEv\005\000\000\000\006\00258\000\005", !5, !"_ZTS1A", !10, null, null, null, i32 0, !13} ; [ DW_TAG_subprogram ] [line 5] [protected] [getFoo]
-!10 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "data", line: 3, size: 32, align: 32, flags: DIFlagPrivate, file: !5, scope: !"_ZTS1A", baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DISubprogram(name: "getFoo", linkageName: "_ZN1A6getFooEv", line: 5, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagProtected | DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !5, scope: !"_ZTS1A", type: !10)
+!10 = !DISubroutineType(types: !11)
 !11 = !{null, !12}
-!12 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1A]
-!13 = !{i32 786468}
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1A")
 !14 = !{!15, !16, !20}
-!15 = !{!"0x2e\00getFoo\00getFoo\00_ZN1A6getFooEv\008\000\001\000\006\00256\000\008", !5, !"_ZTS1A", !10, null, void (%class.A*)* @_ZN1A6getFooEv, null, !9, !2} ; [ DW_TAG_subprogram ] [line 8] [def] [getFoo]
-!16 = !{!"0x2e\00f\00f\00_Z1fv\0011\000\001\000\006\00256\000\0011", !5, !17, !18, null, void ()* @_Z1fv, null, null, !2} ; [ DW_TAG_subprogram ] [line 11] [def] [f]
-!17 = !{!"0x29", !5}         ; [ DW_TAG_file_type ] [type-unique-odr-b.cpp]
-!18 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !19, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!15 = !DISubprogram(name: "getFoo", linkageName: "_ZN1A6getFooEv", line: 8, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 8, file: !5, scope: !"_ZTS1A", type: !10, function: void (%class.A*)* @_ZN1A6getFooEv, declaration: !9, variables: !2)
+!16 = !DISubprogram(name: "f", linkageName: "_Z1fv", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 11, file: !5, scope: !17, type: !18, function: void ()* @_Z1fv, variables: !2)
+!17 = !DIFile(filename: "type-unique-odr-b.cpp", directory: "")
+!18 = !DISubroutineType(types: !19)
 !19 = !{null}
-!20 = !{!"0x2e\00bar\00bar\00_ZL3barv\0010\001\001\000\006\00256\000\0010", !5, !17, !18, null, void ()* @_ZL3barv, null, null, !2} ; [ DW_TAG_subprogram ] [line 10] [local] [def] [bar]
+!20 = !DISubprogram(name: "bar", linkageName: "_ZL3barv", line: 10, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 10, file: !5, scope: !17, type: !18, function: void ()* @_ZL3barv, variables: !2)
 !21 = !{i32 2, !"Dwarf Version", i32 4}
-!22 = !{i32 1, !"Debug Info Version", i32 2}
+!22 = !{i32 1, !"Debug Info Version", i32 3}
 !23 = !{!"clang version 3.5.0 "}
-!24 = !{!"0x101\00this\0016777216\001088", !15, null, !25} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!25 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1A]
-!26 = !MDLocation(line: 0, scope: !15)
-!27 = !MDLocation(line: 8, scope: !15)
-!28 = !MDLocation(line: 11, scope: !16)
-!29 = !MDLocation(line: 10, scope: !20)
+!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !15, type: !25)
+!25 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1A")
+!26 = !DILocation(line: 0, scope: !15)
+!27 = !DILocation(line: 8, scope: !15)
+!28 = !DILocation(line: 11, scope: !16)
+!29 = !DILocation(line: 10, scope: !20)
diff --git a/test/Linker/type-unique-simple-a.ll b/test/Linker/type-unique-simple-a.ll
index ef29cd9781d7..1ab43d657e15 100644
--- a/test/Linker/type-unique-simple-a.ll
+++ b/test/Linker/type-unique-simple-a.ll
@@ -54,8 +54,8 @@ entry:
   %a.addr = alloca i32, align 4
   %t = alloca %struct.Base, align 4
   store i32 %a, i32* %a.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !15, metadata !{!"0x102"}), !dbg !16
-  call void @llvm.dbg.declare(metadata %struct.Base* %t, metadata !17, metadata !{!"0x102"}), !dbg !18
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !15, metadata !DIExpression()), !dbg !16
+  call void @llvm.dbg.declare(metadata %struct.Base* %t, metadata !17, metadata !DIExpression()), !dbg !18
   ret void, !dbg !19
 }
 
@@ -68,24 +68,24 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!14, !20}
 
-!0 = !{!"0x11\004\00clang version 3.4 (http://llvm.org/git/clang.git c23b1db6268c8e7ce64026d57d1510c1aac200a0) (http://llvm.org/git/llvm.git 09b98fe3978eddefc2145adc1056cf21580ce945)\000\00\000\00\000", !1, !2, !3, !9, !2, !2} ; [ DW_TAG_compile_unit ] [/Users/mren/c_testing/type_unique_air/simple/foo.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"foo.cpp", !"/Users/mren/c_testing/type_unique_air/simple"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 (http://llvm.org/git/clang.git c23b1db6268c8e7ce64026d57d1510c1aac200a0) (http://llvm.org/git/llvm.git 09b98fe3978eddefc2145adc1056cf21580ce945)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !9, globals: !2, imports: !2)
+!1 = !DIFile(filename: "foo.cpp", directory: "/Users/mren/c_testing/type_unique_air/simple")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00Base\001\0032\0032\000\000\000", !5, null, null, !6, null, null, !"_ZTS4Base"} ; [ DW_TAG_structure_type ] [Base] [line 1, size 32, align 32, offset 0] [def] [from ]
-!5 = !{!"./a.hpp", !"/Users/mren/c_testing/type_unique_air/simple"}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "Base", line: 1, size: 32, align: 32, file: !5, elements: !6, identifier: "_ZTS4Base")
+!5 = !DIFile(filename: "./a.hpp", directory: "/Users/mren/c_testing/type_unique_air/simple")
 !6 = !{!7}
-!7 = !{!"0xd\00a\002\0032\0032\000\000", !5, !"_ZTS4Base", !8} ; [ DW_TAG_member ] [a] [line 2, size 32, align 32, offset 0] [from int]
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 2, size: 32, align: 32, file: !5, scope: !"_ZTS4Base", baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{!10}
-!10 = !{!"0x2e\00f\00f\00_Z1fi\003\000\001\000\006\00256\000\003", !1, !11, !12, null, void (i32)* @_Z1fi, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [f]
-!11 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/Users/mren/c_testing/type_unique_air/simple/foo.cpp]
-!12 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !13, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!10 = !DISubprogram(name: "f", linkageName: "_Z1fi", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !11, type: !12, function: void (i32)* @_Z1fi, variables: !2)
+!11 = !DIFile(filename: "foo.cpp", directory: "/Users/mren/c_testing/type_unique_air/simple")
+!12 = !DISubroutineType(types: !13)
 !13 = !{null, !8}
 !14 = !{i32 2, !"Dwarf Version", i32 2}
-!15 = !{!"0x101\00a\0016777219\000", !10, !11, !8} ; [ DW_TAG_arg_variable ] [a] [line 3]
-!16 = !MDLocation(line: 3, scope: !10)
-!17 = !{!"0x100\00t\004\000", !10, !11, !4} ; [ DW_TAG_auto_variable ] [t] [line 4]
-!18 = !MDLocation(line: 4, scope: !10)
-!19 = !MDLocation(line: 5, scope: !10)
-!20 = !{i32 1, !"Debug Info Version", i32 2}
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 3, arg: 1, scope: !10, file: !11, type: !8)
+!16 = !DILocation(line: 3, scope: !10)
+!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "t", line: 4, scope: !10, file: !11, type: !4)
+!18 = !DILocation(line: 4, scope: !10)
+!19 = !DILocation(line: 5, scope: !10)
+!20 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/type-unique-simple-b.ll b/test/Linker/type-unique-simple-b.ll
index fb1a5292975f..c12b91845299 100644
--- a/test/Linker/type-unique-simple-b.ll
+++ b/test/Linker/type-unique-simple-b.ll
@@ -10,8 +10,8 @@ entry:
   %a.addr = alloca i32, align 4
   %t = alloca %struct.Base, align 4
   store i32 %a, i32* %a.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !18, metadata !{!"0x102"}), !dbg !19
-  call void @llvm.dbg.declare(metadata %struct.Base* %t, metadata !20, metadata !{!"0x102"}), !dbg !21
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !18, metadata !DIExpression()), !dbg !19
+  call void @llvm.dbg.declare(metadata %struct.Base* %t, metadata !20, metadata !DIExpression()), !dbg !21
   ret void, !dbg !22
 }
 
@@ -38,30 +38,30 @@ attributes #3 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!17, !26}
 
-!0 = !{!"0x11\004\00clang version 3.4 (http://llvm.org/git/clang.git c23b1db6268c8e7ce64026d57d1510c1aac200a0) (http://llvm.org/git/llvm.git 09b98fe3978eddefc2145adc1056cf21580ce945)\000\00\000\00\000", !1, !2, !3, !9, !2, !2} ; [ DW_TAG_compile_unit ] [/Users/mren/c_testing/type_unique_air/simple/bar.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"bar.cpp", !"/Users/mren/c_testing/type_unique_air/simple"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 (http://llvm.org/git/clang.git c23b1db6268c8e7ce64026d57d1510c1aac200a0) (http://llvm.org/git/llvm.git 09b98fe3978eddefc2145adc1056cf21580ce945)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !9, globals: !2, imports: !2)
+!1 = !DIFile(filename: "bar.cpp", directory: "/Users/mren/c_testing/type_unique_air/simple")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00Base\001\0032\0032\000\000\000", !5, null, null, !6, null, null, !"_ZTS4Base"} ; [ DW_TAG_structure_type ] [Base] [line 1, size 32, align 32, offset 0] [def] [from ]
-!5 = !{!"./a.hpp", !"/Users/mren/c_testing/type_unique_air/simple"}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "Base", line: 1, size: 32, align: 32, file: !5, elements: !6, identifier: "_ZTS4Base")
+!5 = !DIFile(filename: "./a.hpp", directory: "/Users/mren/c_testing/type_unique_air/simple")
 !6 = !{!7}
-!7 = !{!"0xd\00a\002\0032\0032\000\000", !5, !"_ZTS4Base", !8} ; [ DW_TAG_member ] [a] [line 2, size 32, align 32, offset 0] [from int]
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 2, size: 32, align: 32, file: !5, scope: !"_ZTS4Base", baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{!10, !14}
-!10 = !{!"0x2e\00g\00g\00_Z1gi\004\000\001\000\006\00256\000\004", !1, !11, !12, null, void (i32)* @_Z1gi, null, null, !2} ; [ DW_TAG_subprogram ] [line 4] [def] [g]
-!11 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [/Users/mren/c_testing/type_unique_air/simple/bar.cpp]
-!12 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !13, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!10 = !DISubprogram(name: "g", linkageName: "_Z1gi", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !1, scope: !11, type: !12, function: void (i32)* @_Z1gi, variables: !2)
+!11 = !DIFile(filename: "bar.cpp", directory: "/Users/mren/c_testing/type_unique_air/simple")
+!12 = !DISubroutineType(types: !13)
 !13 = !{null, !8}
-!14 = !{!"0x2e\00main\00main\00\007\000\001\000\006\00256\000\007", !1, !11, !15, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 7] [def] [main]
-!15 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!14 = !DISubprogram(name: "main", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !1, scope: !11, type: !15, function: i32 ()* @main, variables: !2)
+!15 = !DISubroutineType(types: !16)
 !16 = !{!8}
 !17 = !{i32 2, !"Dwarf Version", i32 2}
-!18 = !{!"0x101\00a\0016777220\000", !10, !11, !8} ; [ DW_TAG_arg_variable ] [a] [line 4]
-!19 = !MDLocation(line: 4, scope: !10)
-!20 = !{!"0x100\00t\005\000", !10, !11, !4} ; [ DW_TAG_auto_variable ] [t] [line 5]
-!21 = !MDLocation(line: 5, scope: !10)
-!22 = !MDLocation(line: 6, scope: !10)
-!23 = !MDLocation(line: 8, scope: !14)
-!24 = !MDLocation(line: 9, scope: !14)
-!25 = !MDLocation(line: 10, scope: !14)
-!26 = !{i32 1, !"Debug Info Version", i32 2}
+!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 4, arg: 1, scope: !10, file: !11, type: !8)
+!19 = !DILocation(line: 4, scope: !10)
+!20 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "t", line: 5, scope: !10, file: !11, type: !4)
+!21 = !DILocation(line: 5, scope: !10)
+!22 = !DILocation(line: 6, scope: !10)
+!23 = !DILocation(line: 8, scope: !14)
+!24 = !DILocation(line: 9, scope: !14)
+!25 = !DILocation(line: 10, scope: !14)
+!26 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Linker/type-unique-simple2-a.ll b/test/Linker/type-unique-simple2-a.ll
index 72a776bba0c1..f9170ab5f7fa 100644
--- a/test/Linker/type-unique-simple2-a.ll
+++ b/test/Linker/type-unique-simple2-a.ll
@@ -48,8 +48,8 @@ define linkonce_odr void @_ZN1AC1Ev(%class.A* %this) unnamed_addr #2 align 2 {
 entry:
   %this.addr = alloca %class.A*, align 8
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !39, metadata !{!"0x102"}), !dbg !41
-  %this1 = load %class.A** %this.addr
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !39, metadata !DIExpression()), !dbg !41
+  %this1 = load %class.A*, %class.A** %this.addr
   call void @_ZN1AC2Ev(%class.A* %this1) #1, !dbg !42
   ret void, !dbg !42
 }
@@ -64,10 +64,10 @@ define linkonce_odr void @_ZN1AC2Ev(%class.A* %this) unnamed_addr #2 align 2 {
 entry:
   %this.addr = alloca %class.A*, align 8
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !44, metadata !{!"0x102"}), !dbg !45
-  %this1 = load %class.A** %this.addr
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !44, metadata !DIExpression()), !dbg !45
+  %this1 = load %class.A*, %class.A** %this.addr
   %0 = bitcast %class.A* %this1 to i8***, !dbg !46
-  store i8** getelementptr inbounds ([4 x i8*]* @_ZTV1A, i64 0, i64 2), i8*** %0, !dbg !46
+  store i8** getelementptr inbounds ([4 x i8*], [4 x i8*]* @_ZTV1A, i64 0, i64 2), i8*** %0, !dbg !46
   ret void, !dbg !46
 }
 
@@ -80,50 +80,47 @@ attributes #4 = { nounwind readnone }
 !llvm.module.flags = !{!35, !36}
 !llvm.ident = !{!37}
 
-!0 = !{!"0x11\004\00clang version 3.5 \000\00\000\00\000", !1, !2, !3, !26, !2, !2} ; [ DW_TAG_compile_unit ] [/<unknown>] [DW_LANG_C_plus_plus]
-!1 = !{!"<unknown>", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !26, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<unknown>", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2\00A\002\0064\0064\000\000\000", !5, null, null, !6, !"_ZTS1A", null, !"_ZTS1A"} ; [ DW_TAG_class_type ] [A] [line 2, size 64, align 64, offset 0] [def] [from ]
-!5 = !{!"./ab.h", !""}
+!4 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 2, size: 64, align: 64, file: !5, elements: !6, vtableHolder: !"_ZTS1A", identifier: "_ZTS1A")
+!5 = !DIFile(filename: "./ab.h", directory: "")
 !6 = !{!7, !14, !19}
-!7 = !{!"0xd\00_vptr$A\000\0064\000\000\0064", !5, !8, !9} ; [ DW_TAG_member ] [_vptr$A] [line 0, size 64, align 0, offset 0] [artificial] [from ]
-!8 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [/./ab.h]
-!9 = !{!"0xf\00\000\0064\000\000\000", null, null, !10} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from __vtbl_ptr_type]
-!10 = !{!"0xf\00__vtbl_ptr_type\000\0064\000\000\000", null, null, !11} ; [ DW_TAG_pointer_type ] [__vtbl_ptr_type] [line 0, size 64, align 0, offset 0] [from ]
-!11 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "_vptr$A", size: 64, flags: DIFlagArtificial, file: !5, scope: !8, baseType: !9)
+!8 = !DIFile(filename: "./ab.h", directory: "")
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, baseType: !10)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "__vtbl_ptr_type", size: 64, baseType: !11)
+!11 = !DISubroutineType(types: !12)
 !12 = !{!13}
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!14 = !{!"0x2e\00setFoo\00setFoo\00_ZN1A6setFooEv\004\000\000\001\006\00259\000\004", !5, !"_ZTS1A", !15, !"_ZTS1A", null, null, i32 0, !18} ; [ DW_TAG_subprogram ] [line 4] [setFoo]
-!15 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!14 = !DISubprogram(name: "setFoo", linkageName: "_ZN1A6setFooEv", line: 4, isLocal: false, isDefinition: false, virtuality: DW_VIRTUALITY_virtual, virtualIndex: 6, flags: DIFlagPublic | DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !5, scope: !"_ZTS1A", type: !15, containingType: !"_ZTS1A")
+!15 = !DISubroutineType(types: !16)
 !16 = !{null, !17}
-!17 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1A]
-!18 = !{i32 786468}
-!19 = !{!"0x2e\00getFoo\00getFoo\00_ZN1A6getFooEv\005\000\000\001\006\00259\000\005", !5, !"_ZTS1A", !20, !"_ZTS1A", null, null, i32 0, !25} ; [ DW_TAG_subprogram ] [line 5] [getFoo]
-!20 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !21, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1A")
+!19 = !DISubprogram(name: "getFoo", linkageName: "_ZN1A6getFooEv", line: 5, isLocal: false, isDefinition: false, virtuality: DW_VIRTUALITY_virtual, virtualIndex: 6, flags: DIFlagPublic | DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !5, scope: !"_ZTS1A", type: !20, containingType: !"_ZTS1A")
+!20 = !DISubroutineType(types: !21)
 !21 = !{!22, !17}
-!22 = !{!"0x26\00\000\000\000\000\000", null, null, !23} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from foo_t]
-!23 = !{!"0x16\00foo_t\001\000\000\000\000", !24, null, !13} ; [ DW_TAG_typedef ] [foo_t] [line 1, size 0, align 0, offset 0] [from int]
-!24 = !{!"a.cpp", !""}
-!25 = !{i32 786468}
+!22 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !23)
+!23 = !DIDerivedType(tag: DW_TAG_typedef, name: "foo_t", line: 1, file: !24, baseType: !13)
+!24 = !DIFile(filename: "a.cpp", directory: "")
 !26 = !{!27, !31, !34}
-!27 = !{!"0x2e\00bar\00bar\00_Z3barv\002\000\001\000\006\00256\000\002", !24, !28, !29, null, i32 ()* @_Z3barv, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [bar]
-!28 = !{!"0x29", !24}        ; [ DW_TAG_file_type ] [/a.cpp]
-!29 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !30, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!27 = !DISubprogram(name: "bar", linkageName: "_Z3barv", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !24, scope: !28, type: !29, function: i32 ()* @_Z3barv, variables: !2)
+!28 = !DIFile(filename: "a.cpp", directory: "")
+!29 = !DISubroutineType(types: !30)
 !30 = !{!23}
-!31 = !{!"0x2e\00A\00A\00_ZN1AC1Ev\002\000\001\000\006\00320\000\002", !5, !"_ZTS1A", !15, null, void (%class.A*)* @_ZN1AC1Ev, null, !32, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [A]
-!32 = !{!"0x2e\00A\00A\00\000\000\000\000\006\00320\000\000", null, !"_ZTS1A", !15, null, null, null, i32 0, !33} ; [ DW_TAG_subprogram ] [line 0] [A]
-!33 = !{i32 786468}
-!34 = !{!"0x2e\00A\00A\00_ZN1AC2Ev\002\000\001\000\006\00320\000\002", !5, !"_ZTS1A", !15, null, void (%class.A*)* @_ZN1AC2Ev, null, !32, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [A]
+!31 = !DISubprogram(name: "A", linkageName: "_ZN1AC1Ev", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !5, scope: !"_ZTS1A", type: !15, function: void (%class.A*)* @_ZN1AC1Ev, declaration: !32, variables: !2)
+!32 = !DISubprogram(name: "A", isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scope: !"_ZTS1A", type: !15)
+!34 = !DISubprogram(name: "A", linkageName: "_ZN1AC2Ev", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !5, scope: !"_ZTS1A", type: !15, function: void (%class.A*)* @_ZN1AC2Ev, declaration: !32, variables: !2)
 !35 = !{i32 2, !"Dwarf Version", i32 2}
-!36 = !{i32 1, !"Debug Info Version", i32 2}
+!36 = !{i32 1, !"Debug Info Version", i32 3}
 !37 = !{!"clang version 3.5 "}
-!38 = !MDLocation(line: 3, scope: !27)
-!39 = !{!"0x101\00this\0016777216\001088", !31, null, !40} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!40 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1A]
-!41 = !MDLocation(line: 0, scope: !31)
-!42 = !MDLocation(line: 2, scope: !43)
-!43 = !{!"0xb\000", !5, !31} ; [ DW_TAG_lexical_block ] [/./ab.h]
-!44 = !{!"0x101\00this\0016777216\001088", !34, null, !40} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!45 = !MDLocation(line: 0, scope: !34)
-!46 = !MDLocation(line: 2, scope: !34)
+!38 = !DILocation(line: 3, scope: !27)
+!39 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !31, type: !40)
+!40 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1A")
+!41 = !DILocation(line: 0, scope: !31)
+!42 = !DILocation(line: 2, scope: !43)
+!43 = !DILexicalBlockFile(discriminator: 0, file: !5, scope: !31)
+!44 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !34, type: !40)
+!45 = !DILocation(line: 0, scope: !34)
+!46 = !DILocation(line: 2, scope: !34)
diff --git a/test/Linker/type-unique-simple2-b.ll b/test/Linker/type-unique-simple2-b.ll
index 25e67d424ea8..5539fb4adb35 100644
--- a/test/Linker/type-unique-simple2-b.ll
+++ b/test/Linker/type-unique-simple2-b.ll
@@ -15,15 +15,15 @@
 @_ZTV1A = unnamed_addr constant [4 x i8*] [i8* null, i8* bitcast ({ i8*, i8* }* @_ZTI1A to i8*), i8* bitcast (void (%class.A*)* @_ZN1A6setFooEv to i8*), i8* bitcast (i32 (%class.A*)* @_ZN1A6getFooEv to i8*)]
 @_ZTVN10__cxxabiv117__class_type_infoE = external global i8*
 @_ZTS1A = constant [3 x i8] c"1A\00"
-@_ZTI1A = unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8]* @_ZTS1A, i32 0, i32 0) }
+@_ZTI1A = unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @_ZTS1A, i32 0, i32 0) }
 
 ; Function Attrs: nounwind
 define void @_ZN1A6setFooEv(%class.A* %this) unnamed_addr #0 align 2 {
 entry:
   %this.addr = alloca %class.A*, align 8
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !32, metadata !{!"0x102"}), !dbg !34
-  %this1 = load %class.A** %this.addr
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !32, metadata !DIExpression()), !dbg !34
+  %this1 = load %class.A*, %class.A** %this.addr
   ret void, !dbg !35
 }
 
@@ -35,8 +35,8 @@ define i32 @_ZN1A6getFooEv(%class.A* %this) unnamed_addr #0 align 2 {
 entry:
   %this.addr = alloca %class.A*, align 8
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !36, metadata !{!"0x102"}), !dbg !37
-  %this1 = load %class.A** %this.addr
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !36, metadata !DIExpression()), !dbg !37
+  %this1 = load %class.A*, %class.A** %this.addr
   ret i32 1, !dbg !38
 }
 
@@ -47,42 +47,40 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!29, !30}
 !llvm.ident = !{!31}
 
-!0 = !{!"0x11\004\00clang version 3.5 \000\00\000\00\000", !1, !2, !3, !25, !2, !2} ; [ DW_TAG_compile_unit ] [/<unknown>] [DW_LANG_C_plus_plus]
-!1 = !{!"<unknown>", !""}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !3, subprograms: !25, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<unknown>", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2\00A\002\0064\0064\000\000\000", !5, null, null, !6, !"_ZTS1A", null, !"_ZTS1A"} ; [ DW_TAG_class_type ] [A] [line 2, size 64, align 64, offset 0] [def] [from ]
-!5 = !{!"./ab.h", !""}
+!4 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 2, size: 64, align: 64, file: !5, elements: !6, vtableHolder: !"_ZTS1A", identifier: "_ZTS1A")
+!5 = !DIFile(filename: "./ab.h", directory: "")
 !6 = !{!7, !14, !19}
-!7 = !{!"0xd\00_vptr$A\000\0064\000\000\0064", !5, !8, !9} ; [ DW_TAG_member ] [_vptr$A] [line 0, size 64, align 0, offset 0] [artificial] [from ]
-!8 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [/./ab.h]
-!9 = !{!"0xf\00\000\0064\000\000\000", null, null, !10} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from __vtbl_ptr_type]
-!10 = !{!"0xf\00__vtbl_ptr_type\000\0064\000\000\000", null, null, !11} ; [ DW_TAG_pointer_type ] [__vtbl_ptr_type] [line 0, size 64, align 0, offset 0] [from ]
-!11 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "_vptr$A", size: 64, flags: DIFlagArtificial, file: !5, scope: !8, baseType: !9)
+!8 = !DIFile(filename: "./ab.h", directory: "")
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, baseType: !10)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "__vtbl_ptr_type", size: 64, baseType: !11)
+!11 = !DISubroutineType(types: !12)
 !12 = !{!13}
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!14 = !{!"0x2e\00setFoo\00setFoo\00_ZN1A6setFooEv\004\000\000\001\006\00259\000\004", !5, !"_ZTS1A", !15, !"_ZTS1A", null, null, i32 0, !18} ; [ DW_TAG_subprogram ] [line 4] [setFoo]
-!15 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !16, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!14 = !DISubprogram(name: "setFoo", linkageName: "_ZN1A6setFooEv", line: 4, isLocal: false, isDefinition: false, virtuality: DW_VIRTUALITY_virtual, virtualIndex: 6, flags: DIFlagPublic | DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !5, scope: !"_ZTS1A", type: !15, containingType: !"_ZTS1A")
+!15 = !DISubroutineType(types: !16)
 !16 = !{null, !17}
-!17 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1A]
-!18 = !{i32 786468}
-!19 = !{!"0x2e\00getFoo\00getFoo\00_ZN1A6getFooEv\005\000\000\001\006\00259\000\005", !5, !"_ZTS1A", !20, !"_ZTS1A", null, null, i32 0, !24} ; [ DW_TAG_subprogram ] [line 5] [getFoo]
-!20 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !21, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!17 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1A")
+!19 = !DISubprogram(name: "getFoo", linkageName: "_ZN1A6getFooEv", line: 5, isLocal: false, isDefinition: false, virtuality: DW_VIRTUALITY_virtual, virtualIndex: 6, flags: DIFlagPublic | DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !5, scope: !"_ZTS1A", type: !20, containingType: !"_ZTS1A")
+!20 = !DISubroutineType(types: !21)
 !21 = !{!22, !17}
-!22 = !{!"0x26\00\000\000\000\000\000", null, null, !23} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from foo_t]
-!23 = !{!"0x16\00foo_t\001\000\000\000\000", !5, null, !13} ; [ DW_TAG_typedef ] [foo_t] [line 1, size 0, align 0, offset 0] [from int]
-!24 = !{i32 786468}
+!22 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !23)
+!23 = !DIDerivedType(tag: DW_TAG_typedef, name: "foo_t", line: 1, file: !5, baseType: !13)
 !25 = !{!26, !28}
-!26 = !{!"0x2e\00setFoo\00setFoo\00_ZN1A6setFooEv\002\000\001\000\006\00259\000\002", !27, !"_ZTS1A", !15, null, void (%class.A*)* @_ZN1A6setFooEv, null, !14, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [setFoo]
-!27 = !{!"b.cpp", !""}
-!28 = !{!"0x2e\00getFoo\00getFoo\00_ZN1A6getFooEv\004\000\001\000\006\00259\000\004", !27, !"_ZTS1A", !20, null, i32 (%class.A*)* @_ZN1A6getFooEv, null, !19, !2} ; [ DW_TAG_subprogram ] [line 4] [def] [getFoo]
+!26 = !DISubprogram(name: "setFoo", linkageName: "_ZN1A6setFooEv", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPublic | DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !27, scope: !"_ZTS1A", type: !15, function: void (%class.A*)* @_ZN1A6setFooEv, declaration: !14, variables: !2)
+!27 = !DIFile(filename: "b.cpp", directory: "")
+!28 = !DISubprogram(name: "getFoo", linkageName: "_ZN1A6getFooEv", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPublic | DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !27, scope: !"_ZTS1A", type: !20, function: i32 (%class.A*)* @_ZN1A6getFooEv, declaration: !19, variables: !2)
 !29 = !{i32 2, !"Dwarf Version", i32 2}
-!30 = !{i32 1, !"Debug Info Version", i32 2}
+!30 = !{i32 1, !"Debug Info Version", i32 3}
 !31 = !{!"clang version 3.5 "}
-!32 = !{!"0x101\00this\0016777216\001088", !26, null, !33} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!33 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1A]
-!34 = !MDLocation(line: 0, scope: !26)
-!35 = !MDLocation(line: 2, scope: !26)
-!36 = !{!"0x101\00this\0016777216\001088", !28, null, !33} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!37 = !MDLocation(line: 0, scope: !28)
-!38 = !MDLocation(line: 4, scope: !28)
+!32 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !26, type: !33)
+!33 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1A")
+!34 = !DILocation(line: 0, scope: !26)
+!35 = !DILocation(line: 2, scope: !26)
+!36 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !28, type: !33)
+!37 = !DILocation(line: 0, scope: !28)
+!38 = !DILocation(line: 4, scope: !28)
diff --git a/test/Linker/type-unique-src-type.ll b/test/Linker/type-unique-src-type.ll
index 01b33a21bd74..110ecc87e1b1 100644
--- a/test/Linker/type-unique-src-type.ll
+++ b/test/Linker/type-unique-src-type.ll
@@ -11,14 +11,14 @@
 ; CHECK-NEXT: %A = type { i8 }
 
 ; CHECK: @g1 = external global %C.0
-; CHECK:  getelementptr %C.0* null, i64 0, i32 0, i32 0
+; CHECK:  getelementptr %C.0, %C.0* null, i64 0, i32 0, i32 0
 
 %A   = type { i8 }
 %B   = type { %A }
 %C   = type { %B }
 %C.0 = type { %B }
 define void @f1() {
-  getelementptr %C* null, i64 0, i32 0, i32 0
+  getelementptr %C, %C* null, i64 0, i32 0, i32 0
   ret void
 }
 @g1 = external global %C.0
diff --git a/test/Linker/type-unique-type-array-a.ll b/test/Linker/type-unique-type-array-a.ll
index 9e2de8821b4d..98c8d657743d 100644
--- a/test/Linker/type-unique-type-array-a.ll
+++ b/test/Linker/type-unique-type-array-a.ll
@@ -48,17 +48,17 @@ entry:
   %sa = alloca %struct.SA, align 4
   %a.addr = alloca %class.A*, align 8
   %agg.tmp = alloca %struct.SA, align 4
-  %coerce.dive = getelementptr %struct.SA* %sa, i32 0, i32 0
+  %coerce.dive = getelementptr %struct.SA, %struct.SA* %sa, i32 0, i32 0
   store i32 %sa.coerce, i32* %coerce.dive
   store %class.A* %a, %class.A** %a.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %a.addr, metadata !24, metadata !{!"0x102"}), !dbg !25
-  call void @llvm.dbg.declare(metadata %struct.SA* %sa, metadata !26, metadata !{!"0x102"}), !dbg !27
-  %0 = load %class.A** %a.addr, align 8, !dbg !28
+  call void @llvm.dbg.declare(metadata %class.A** %a.addr, metadata !24, metadata !DIExpression()), !dbg !25
+  call void @llvm.dbg.declare(metadata %struct.SA* %sa, metadata !26, metadata !DIExpression()), !dbg !27
+  %0 = load %class.A*, %class.A** %a.addr, align 8, !dbg !28
   %1 = bitcast %struct.SA* %agg.tmp to i8*, !dbg !28
   %2 = bitcast %struct.SA* %sa to i8*, !dbg !28
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 4, i32 4, i1 false), !dbg !28
-  %coerce.dive1 = getelementptr %struct.SA* %agg.tmp, i32 0, i32 0, !dbg !28
-  %3 = load i32* %coerce.dive1, !dbg !28
+  %coerce.dive1 = getelementptr %struct.SA, %struct.SA* %agg.tmp, i32 0, i32 0, !dbg !28
+  %3 = load i32, i32* %coerce.dive1, !dbg !28
   call void @_ZN1A5testAE2SA(%class.A* %0, i32 %3), !dbg !28
   ret void, !dbg !29
 }
@@ -71,12 +71,12 @@ define linkonce_odr void @_ZN1A5testAE2SA(%class.A* %this, i32 %a.coerce) #2 ali
 entry:
   %a = alloca %struct.SA, align 4
   %this.addr = alloca %class.A*, align 8
-  %coerce.dive = getelementptr %struct.SA* %a, i32 0, i32 0
+  %coerce.dive = getelementptr %struct.SA, %struct.SA* %a, i32 0, i32 0
   store i32 %a.coerce, i32* %coerce.dive
   store %class.A* %this, %class.A** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !30, metadata !{!"0x102"}), !dbg !31
-  call void @llvm.dbg.declare(metadata %struct.SA* %a, metadata !32, metadata !{!"0x102"}), !dbg !33
-  %this1 = load %class.A** %this.addr
+  call void @llvm.dbg.declare(metadata %class.A** %this.addr, metadata !30, metadata !DIExpression()), !dbg !31
+  call void @llvm.dbg.declare(metadata %struct.SA* %a, metadata !32, metadata !DIExpression()), !dbg !33
+  %this1 = load %class.A*, %class.A** %this.addr
   ret void, !dbg !34
 }
 
@@ -92,38 +92,38 @@ attributes #3 = { nounwind }
 !llvm.module.flags = !{!21, !22}
 !llvm.ident = !{!23}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 (trunk 214102:214113M) (llvm/trunk 214102:214115M)\000\00\000\00\001", !1, !2, !3, !14, !2, !2} ; [ DW_TAG_compile_unit ] [a.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"a.cpp", !"/Users/manmanren/test-Nov/type_unique/rdar_di_array"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 (trunk 214102:214113M) (llvm/trunk 214102:214115M)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !14, globals: !2, imports: !2)
+!1 = !DIFile(filename: "a.cpp", directory: "/Users/manmanren/test-Nov/type_unique/rdar_di_array")
 !2 = !{}
 !3 = !{!4, !10}
-!4 = !{!"0x2\00A\005\008\008\000\000\000", !1, null, null, !5, null, null, !"_ZTS1A"} ; [ DW_TAG_class_type ] [A] [line 5, size 8, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_class_type, name: "A", line: 5, size: 8, align: 8, file: !1, elements: !5, identifier: "_ZTS1A")
 !5 = !{!6}
-!6 = !{!"0x2e\00testA\00testA\00_ZN1A5testAE2SA\007\000\000\000\006\00256\000\007", !1, !"_ZTS1A", !7, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 7] [testA]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DISubprogram(name: "testA", linkageName: "_ZN1A5testAE2SA", line: 7, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !1, scope: !"_ZTS1A", type: !7)
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9, !"_ZTS2SA"}
-!9 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1A]
-!10 = !{!"0x13\00SA\001\0032\0032\000\000\000", !1, null, null, !11, null, null, !"_ZTS2SA"} ; [ DW_TAG_structure_type ] [SA] [line 1, size 32, align 32, offset 0] [def] [from ]
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1A")
+!10 = !DICompositeType(tag: DW_TAG_structure_type, name: "SA", line: 1, size: 32, align: 32, file: !1, elements: !11, identifier: "_ZTS2SA")
 !11 = !{!12}
-!12 = !{!"0xd\00a\002\0032\0032\000\000", !1, !"_ZTS2SA", !13} ; [ DW_TAG_member ] [a] [line 2, size 32, align 32, offset 0] [from int]
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 2, size: 32, align: 32, file: !1, scope: !"_ZTS2SA", baseType: !13)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !14 = !{!15, !20}
-!15 = !{!"0x2e\00topA\00topA\00_Z4topAP1A2SA\0011\000\001\000\006\00256\000\0011", !1, !16, !17, null, void (%class.A*, i32)* @_Z4topAP1A2SA, null, null, !2} ; [ DW_TAG_subprogram ] [line 11] [def] [topA]
-!16 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [a.cpp]
-!17 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !18, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!15 = !DISubprogram(name: "topA", linkageName: "_Z4topAP1A2SA", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 11, file: !1, scope: !16, type: !17, function: void (%class.A*, i32)* @_Z4topAP1A2SA, variables: !2)
+!16 = !DIFile(filename: "a.cpp", directory: "/Users/manmanren/test-Nov/type_unique/rdar_di_array")
+!17 = !DISubroutineType(types: !18)
 !18 = !{null, !19, !"_ZTS2SA"}
-!19 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1A]
-!20 = !{!"0x2e\00testA\00testA\00_ZN1A5testAE2SA\007\000\001\000\006\00256\000\007", !1, !"_ZTS1A", !7, null, void (%class.A*, i32)* @_ZN1A5testAE2SA, null, !6, !2} ; [ DW_TAG_subprogram ] [line 7] [def] [testA]
+!19 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1A")
+!20 = !DISubprogram(name: "testA", linkageName: "_ZN1A5testAE2SA", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !1, scope: !"_ZTS1A", type: !7, function: void (%class.A*, i32)* @_ZN1A5testAE2SA, declaration: !6, variables: !2)
 !21 = !{i32 2, !"Dwarf Version", i32 2}
-!22 = !{i32 2, !"Debug Info Version", i32 2}
+!22 = !{i32 2, !"Debug Info Version", i32 3}
 !23 = !{!"clang version 3.5.0 (trunk 214102:214113M) (llvm/trunk 214102:214115M)"}
-!24 = !{!"0x101\00a\0016777227\000", !15, !16, !19} ; [ DW_TAG_arg_variable ] [a] [line 11]
-!25 = !MDLocation(line: 11, column: 14, scope: !15)
-!26 = !{!"0x101\00sa\0033554443\000", !15, !16, !"_ZTS2SA"} ; [ DW_TAG_arg_variable ] [sa] [line 11]
-!27 = !MDLocation(line: 11, column: 20, scope: !15)
-!28 = !MDLocation(line: 12, column: 3, scope: !15)
-!29 = !MDLocation(line: 13, column: 1, scope: !15)
-!30 = !{!"0x101\00this\0016777216\001088", !20, null, !19} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!31 = !MDLocation(line: 0, scope: !20)
-!32 = !{!"0x101\00a\0033554439\000", !20, !16, !"_ZTS2SA"} ; [ DW_TAG_arg_variable ] [a] [line 7]
-!33 = !MDLocation(line: 7, column: 17, scope: !20)
-!34 = !MDLocation(line: 8, column: 3, scope: !20)
+!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 11, arg: 1, scope: !15, file: !16, type: !19)
+!25 = !DILocation(line: 11, column: 14, scope: !15)
+!26 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "sa", line: 11, arg: 2, scope: !15, file: !16, type: !"_ZTS2SA")
+!27 = !DILocation(line: 11, column: 20, scope: !15)
+!28 = !DILocation(line: 12, column: 3, scope: !15)
+!29 = !DILocation(line: 13, column: 1, scope: !15)
+!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !20, type: !19)
+!31 = !DILocation(line: 0, scope: !20)
+!32 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 7, arg: 2, scope: !20, file: !16, type: !"_ZTS2SA")
+!33 = !DILocation(line: 7, column: 17, scope: !20)
+!34 = !DILocation(line: 8, column: 3, scope: !20)
diff --git a/test/Linker/type-unique-type-array-b.ll b/test/Linker/type-unique-type-array-b.ll
index 0fdae2abfe92..14ce59b3c127 100644
--- a/test/Linker/type-unique-type-array-b.ll
+++ b/test/Linker/type-unique-type-array-b.ll
@@ -27,17 +27,17 @@ entry:
   %sa = alloca %struct.SA, align 4
   %b.addr = alloca %class.B*, align 8
   %agg.tmp = alloca %struct.SA, align 4
-  %coerce.dive = getelementptr %struct.SA* %sa, i32 0, i32 0
+  %coerce.dive = getelementptr %struct.SA, %struct.SA* %sa, i32 0, i32 0
   store i32 %sa.coerce, i32* %coerce.dive
   store %class.B* %b, %class.B** %b.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.B** %b.addr, metadata !24, metadata !{!"0x102"}), !dbg !25
-  call void @llvm.dbg.declare(metadata %struct.SA* %sa, metadata !26, metadata !{!"0x102"}), !dbg !27
-  %0 = load %class.B** %b.addr, align 8, !dbg !28
+  call void @llvm.dbg.declare(metadata %class.B** %b.addr, metadata !24, metadata !DIExpression()), !dbg !25
+  call void @llvm.dbg.declare(metadata %struct.SA* %sa, metadata !26, metadata !DIExpression()), !dbg !27
+  %0 = load %class.B*, %class.B** %b.addr, align 8, !dbg !28
   %1 = bitcast %struct.SA* %agg.tmp to i8*, !dbg !28
   %2 = bitcast %struct.SA* %sa to i8*, !dbg !28
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 4, i32 4, i1 false), !dbg !28
-  %coerce.dive1 = getelementptr %struct.SA* %agg.tmp, i32 0, i32 0, !dbg !28
-  %3 = load i32* %coerce.dive1, !dbg !28
+  %coerce.dive1 = getelementptr %struct.SA, %struct.SA* %agg.tmp, i32 0, i32 0, !dbg !28
+  %3 = load i32, i32* %coerce.dive1, !dbg !28
   call void @_ZN1B5testBE2SA(%class.B* %0, i32 %3), !dbg !28
   ret void, !dbg !29
 }
@@ -50,12 +50,12 @@ define linkonce_odr void @_ZN1B5testBE2SA(%class.B* %this, i32 %sa.coerce) #2 al
 entry:
   %sa = alloca %struct.SA, align 4
   %this.addr = alloca %class.B*, align 8
-  %coerce.dive = getelementptr %struct.SA* %sa, i32 0, i32 0
+  %coerce.dive = getelementptr %struct.SA, %struct.SA* %sa, i32 0, i32 0
   store i32 %sa.coerce, i32* %coerce.dive
   store %class.B* %this, %class.B** %this.addr, align 8
-  call void @llvm.dbg.declare(metadata %class.B** %this.addr, metadata !30, metadata !{!"0x102"}), !dbg !31
-  call void @llvm.dbg.declare(metadata %struct.SA* %sa, metadata !32, metadata !{!"0x102"}), !dbg !33
-  %this1 = load %class.B** %this.addr
+  call void @llvm.dbg.declare(metadata %class.B** %this.addr, metadata !30, metadata !DIExpression()), !dbg !31
+  call void @llvm.dbg.declare(metadata %struct.SA* %sa, metadata !32, metadata !DIExpression()), !dbg !33
+  %this1 = load %class.B*, %class.B** %this.addr
   ret void, !dbg !34
 }
 
@@ -71,38 +71,38 @@ attributes #3 = { nounwind }
 !llvm.module.flags = !{!21, !22}
 !llvm.ident = !{!23}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 (trunk 214102:214113M) (llvm/trunk 214102:214115M)\000\00\000\00\001", !1, !2, !3, !14, !2, !2} ; [ DW_TAG_compile_unit ] [b.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"b.cpp", !"/Users/manmanren/test-Nov/type_unique/rdar_di_array"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 (trunk 214102:214113M) (llvm/trunk 214102:214115M)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !14, globals: !2, imports: !2)
+!1 = !DIFile(filename: "b.cpp", directory: "/Users/manmanren/test-Nov/type_unique/rdar_di_array")
 !2 = !{}
 !3 = !{!4, !10}
-!4 = !{!"0x2\00B\005\008\008\000\000\000", !1, null, null, !5, null, null, !"_ZTS1B"} ; [ DW_TAG_class_type ] [B] [line 5, size 8, align 8, offset 0] [def] [from ]
+!4 = !DICompositeType(tag: DW_TAG_class_type, name: "B", line: 5, size: 8, align: 8, file: !1, elements: !5, identifier: "_ZTS1B")
 !5 = !{!6}
-!6 = !{!"0x2e\00testB\00testB\00_ZN1B5testBE2SA\007\000\000\000\006\00256\000\007", !1, !"_ZTS1B", !7, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 7] [testB]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DISubprogram(name: "testB", linkageName: "_ZN1B5testBE2SA", line: 7, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !1, scope: !"_ZTS1B", type: !7)
+!7 = !DISubroutineType(types: !8)
 !8 = !{null, !9, !"_ZTS2SA"}
-!9 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS1B"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1B]
-!10 = !{!"0x13\00SA\001\0032\0032\000\000\000", !1, null, null, !11, null, null, !"_ZTS2SA"} ; [ DW_TAG_structure_type ] [SA] [line 1, size 32, align 32, offset 0] [def] [from ]
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS1B")
+!10 = !DICompositeType(tag: DW_TAG_structure_type, name: "SA", line: 1, size: 32, align: 32, file: !1, elements: !11, identifier: "_ZTS2SA")
 !11 = !{!12}
-!12 = !{!"0xd\00a\002\0032\0032\000\000", !1, !"_ZTS2SA", !13} ; [ DW_TAG_member ] [a] [line 2, size 32, align 32, offset 0] [from int]
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!12 = !DIDerivedType(tag: DW_TAG_member, name: "a", line: 2, size: 32, align: 32, file: !1, scope: !"_ZTS2SA", baseType: !13)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !14 = !{!15, !20}
-!15 = !{!"0x2e\00topB\00topB\00_Z4topBP1B2SA\0011\000\001\000\006\00256\000\0011", !1, !16, !17, null, void (%class.B*, i32)* @_Z4topBP1B2SA, null, null, !2} ; [ DW_TAG_subprogram ] [line 11] [def] [topB]
-!16 = !{!"0x29", !1}         ; [ DW_TAG_file_type ] [b.cpp]
-!17 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !18, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!15 = !DISubprogram(name: "topB", linkageName: "_Z4topBP1B2SA", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 11, file: !1, scope: !16, type: !17, function: void (%class.B*, i32)* @_Z4topBP1B2SA, variables: !2)
+!16 = !DIFile(filename: "b.cpp", directory: "/Users/manmanren/test-Nov/type_unique/rdar_di_array")
+!17 = !DISubroutineType(types: !18)
 !18 = !{null, !19, !"_ZTS2SA"}
-!19 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1B"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1B]
-!20 = !{!"0x2e\00testB\00testB\00_ZN1B5testBE2SA\007\000\001\000\006\00256\000\007", !1, !"_ZTS1B", !7, null, void (%class.B*, i32)* @_ZN1B5testBE2SA, null, !6, !2} ; [ DW_TAG_subprogram ] [line 7] [def] [testB]
+!19 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !"_ZTS1B")
+!20 = !DISubprogram(name: "testB", linkageName: "_ZN1B5testBE2SA", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !1, scope: !"_ZTS1B", type: !7, function: void (%class.B*, i32)* @_ZN1B5testBE2SA, declaration: !6, variables: !2)
 !21 = !{i32 2, !"Dwarf Version", i32 2}
-!22 = !{i32 2, !"Debug Info Version", i32 2}
+!22 = !{i32 2, !"Debug Info Version", i32 3}
 !23 = !{!"clang version 3.5.0 (trunk 214102:214113M) (llvm/trunk 214102:214115M)"}
-!24 = !{!"0x101\00b\0016777227\000", !15, !16, !19} ; [ DW_TAG_arg_variable ] [b] [line 11]
-!25 = !MDLocation(line: 11, column: 14, scope: !15)
-!26 = !{!"0x101\00sa\0033554443\000", !15, !16, !"_ZTS2SA"} ; [ DW_TAG_arg_variable ] [sa] [line 11]
-!27 = !MDLocation(line: 11, column: 20, scope: !15)
-!28 = !MDLocation(line: 12, column: 3, scope: !15)
-!29 = !MDLocation(line: 13, column: 1, scope: !15)
-!30 = !{!"0x101\00this\0016777216\001088", !20, null, !19} ; [ DW_TAG_arg_variable ] [this] [line 0]
-!31 = !MDLocation(line: 0, scope: !20)
-!32 = !{!"0x101\00sa\0033554439\000", !20, !16, !"_ZTS2SA"} ; [ DW_TAG_arg_variable ] [sa] [line 7]
-!33 = !MDLocation(line: 7, column: 17, scope: !20)
-!34 = !MDLocation(line: 8, column: 3, scope: !20)
+!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 11, arg: 1, scope: !15, file: !16, type: !19)
+!25 = !DILocation(line: 11, column: 14, scope: !15)
+!26 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "sa", line: 11, arg: 2, scope: !15, file: !16, type: !"_ZTS2SA")
+!27 = !DILocation(line: 11, column: 20, scope: !15)
+!28 = !DILocation(line: 12, column: 3, scope: !15)
+!29 = !DILocation(line: 13, column: 1, scope: !15)
+!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, flags: DIFlagArtificial | DIFlagObjectPointer, scope: !20, type: !19)
+!31 = !DILocation(line: 0, scope: !20)
+!32 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "sa", line: 7, arg: 2, scope: !20, file: !16, type: !"_ZTS2SA")
+!33 = !DILocation(line: 7, column: 17, scope: !20)
+!34 = !DILocation(line: 8, column: 3, scope: !20)
diff --git a/test/MC/AArch64/arm64-elf-reloc-condbr.s b/test/MC/AArch64/arm64-elf-reloc-condbr.s
index 9b70a20e1bc2..318204507025 100644
--- a/test/MC/AArch64/arm64-elf-reloc-condbr.s
+++ b/test/MC/AArch64/arm64-elf-reloc-condbr.s
@@ -4,7 +4,7 @@
         b.eq somewhere
 
 // OBJ:      Relocations [
-// OBJ-NEXT:   Section (2) .rela.text {
+// OBJ-NEXT:   Section {{.*}} .rela.text {
 // OBJ-NEXT:     0x0 R_AARCH64_CONDBR19 somewhere 0x0
 // OBJ-NEXT:   }
 // OBJ-NEXT: ]
diff --git a/test/MC/AArch64/arm64-fp-encoding-error.s b/test/MC/AArch64/arm64-fp-encoding-error.s
new file mode 100644
index 000000000000..ad3012797445
--- /dev/null
+++ b/test/MC/AArch64/arm64-fp-encoding-error.s
@@ -0,0 +1,8 @@
+; RUN: not llvm-mc -triple arm64-apple-ios8.0 %s -o /dev/null 2>&1 | FileCheck %s
+
+        fmov s0, #-0.0
+; CHECK: error: expected compatible register or floating-point constant
+
+        fmov d0, #-0.0
+; CHECK: error: expected compatible register or floating-point constant
+
diff --git a/test/MC/AArch64/armv8.1a-lor.s b/test/MC/AArch64/armv8.1a-lor.s
new file mode 100644
index 000000000000..1db2c02e2720
--- /dev/null
+++ b/test/MC/AArch64/armv8.1a-lor.s
@@ -0,0 +1,79 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.1a < %s 2>%t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERROR %s <%t
+
+
+//------------------------------------------------------------------------------
+// Load acquire / store release
+//------------------------------------------------------------------------------
+        ldlarb w0,[x1]
+        ldlarh w0,[x1]
+        ldlar  w0,[x1]
+        ldlar  x0,[x1]
+// CHECK:   ldlarb w0, [x1]   // encoding: [0x20,0x7c,0xdf,0x08]
+// CHECK:   ldlarh w0, [x1]   // encoding: [0x20,0x7c,0xdf,0x48]
+// CHECK:   ldlar  w0, [x1]   // encoding: [0x20,0x7c,0xdf,0x88]
+// CHECK:   ldlar  x0, [x1]   // encoding: [0x20,0x7c,0xdf,0xc8]
+        stllrb w0,[x1]
+        stllrh w0,[x1]
+        stllr  w0,[x1]
+        stllr  x0,[x1]
+// CHECK:   stllrb w0, [x1]   // encoding: [0x20,0x7c,0x9f,0x08]
+// CHECK:   stllrh w0, [x1]   // encoding: [0x20,0x7c,0x9f,0x48]
+// CHECK:   stllr  w0, [x1]   // encoding: [0x20,0x7c,0x9f,0x88]
+// CHECK:   stllr  x0, [x1]   // encoding: [0x20,0x7c,0x9f,0xc8]
+
+        msr    LORSA_EL1, x0
+        msr    LOREA_EL1, x0
+        msr    LORN_EL1, x0
+        msr    LORC_EL1, x0
+        mrs    x0, LORID_EL1
+// CHECK:   msr    LORSA_EL1, x0 // encoding: [0x00,0xa4,0x18,0xd5]
+// CHECK:   msr    LOREA_EL1, x0 // encoding: [0x20,0xa4,0x18,0xd5]
+// CHECK:   msr    LORN_EL1, x0  // encoding: [0x40,0xa4,0x18,0xd5]
+// CHECK:   msr    LORC_EL1, x0  // encoding: [0x60,0xa4,0x18,0xd5]
+// CHECK:   mrs    x0, LORID_EL1 // encoding: [0xe0,0xa4,0x38,0xd5]
+
+        ldlarb w0,[w1]
+        ldlarh x0,[x1]
+        stllrb w0,[w1]
+        stllrh x0,[x1]
+        stllr  w0,[w1]
+        msr    LORSA_EL1, #0
+        msr    LOREA_EL1, #0
+        msr    LORN_EL1, #0
+        msr    LORC_EL1, #0
+        msr    LORID_EL1, x0
+        mrs    LORID_EL1, #0
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         ldlarb w0,[w1]
+// CHECK-ERROR:                    ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         ldlarh x0,[x1]
+// CHECK-ERROR:                ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         stllrb w0,[w1]
+// CHECK-ERROR:                    ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         stllrh x0,[x1]
+// CHECK-ERROR:                ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         stllr  w0,[w1]
+// CHECK-ERROR:                    ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         msr     LORSA_EL1, #0
+// CHECK-ERROR:                            ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         msr     LOREA_EL1, #0
+// CHECK-ERROR:                            ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         msr     LORN_EL1, #0
+// CHECK-ERROR:                           ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         msr     LORC_EL1, #0
+// CHECK-ERROR:                           ^
+// CHECK-ERROR: error: expected writable system register or pstate
+// CHECK-ERROR:         msr     LORID_EL1, x0
+// CHECK-ERROR:                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         mrs     LORID_EL1, #0
+// CHECK-ERROR:                 ^
diff --git a/test/MC/AArch64/armv8.1a-pan.s b/test/MC/AArch64/armv8.1a-pan.s
new file mode 100644
index 000000000000..2068c81d939f
--- /dev/null
+++ b/test/MC/AArch64/armv8.1a-pan.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a -show-encoding < %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
+
+  .text
+
+  msr pan, #0
+// CHECK:  msr PAN, #0           // encoding: [0x9f,0x40,0x00,0xd5]
+  msr pan, #1
+// CHECK:  msr PAN, #1           // encoding: [0x9f,0x41,0x00,0xd5]
+  msr pan, x5
+// CHECK:  msr PAN, x5           // encoding: [0x65,0x42,0x18,0xd5]
+  mrs x13, pan
+// CHECK:  mrs x13, PAN          // encoding: [0x6d,0x42,0x38,0xd5]
+
+  msr pan, #-1
+  msr pan, #20
+  msr pan, w0
+  mrs w0, pan
+// CHECK-ERROR: error: immediate must be an integer in range [0, 15].
+// CHECK-ERROR:   msr pan, #-1
+// CHECK-ERROR:            ^
+// CHECK-ERROR: error: immediate must be an integer in range [0, 15].
+// CHECK-ERROR:   msr pan, #20
+// CHECK-ERROR:            ^
+// CHECK-ERROR: error: immediate must be an integer in range [0, 15].
+// CHECK-ERROR:   msr pan, w0
+// CHECK-ERROR:            ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:   mrs w0, pan
+// CHECK-ERROR:       ^
diff --git a/test/MC/AArch64/armv8.1a-rdma.s b/test/MC/AArch64/armv8.1a-rdma.s
new file mode 100644
index 000000000000..1de2a0fb15dd
--- /dev/null
+++ b/test/MC/AArch64/armv8.1a-rdma.s
@@ -0,0 +1,154 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a -show-encoding < %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
+  .text
+
+  //AdvSIMD RDMA vector
+  sqrdmlah v0.4h, v1.4h, v2.4h
+  sqrdmlsh v0.4h, v1.4h, v2.4h
+  sqrdmlah v0.2s, v1.2s, v2.2s
+  sqrdmlsh v0.2s, v1.2s, v2.2s
+  sqrdmlah v0.4s, v1.4s, v2.4s
+  sqrdmlsh v0.4s, v1.4s, v2.4s
+  sqrdmlah v0.8h, v1.8h, v2.8h
+  sqrdmlsh v0.8h, v1.8h, v2.8h
+// CHECK: sqrdmlah  v0.4h, v1.4h, v2.4h // encoding: [0x20,0x84,0x42,0x2e]
+// CHECK: sqrdmlsh  v0.4h, v1.4h, v2.4h // encoding: [0x20,0x8c,0x42,0x2e]
+// CHECK: sqrdmlah  v0.2s, v1.2s, v2.2s // encoding: [0x20,0x84,0x82,0x2e]
+// CHECK: sqrdmlsh  v0.2s, v1.2s, v2.2s // encoding: [0x20,0x8c,0x82,0x2e]
+// CHECK: sqrdmlah  v0.4s, v1.4s, v2.4s // encoding: [0x20,0x84,0x82,0x6e]
+// CHECK: sqrdmlsh  v0.4s, v1.4s, v2.4s // encoding: [0x20,0x8c,0x82,0x6e]
+// CHECK: sqrdmlah  v0.8h, v1.8h, v2.8h // encoding: [0x20,0x84,0x42,0x6e]
+// CHECK: sqrdmlsh  v0.8h, v1.8h, v2.8h // encoding: [0x20,0x8c,0x42,0x6e]
+
+  sqrdmlah v0.2h, v1.2h, v2.2h
+  sqrdmlsh v0.2h, v1.2h, v2.2h
+  sqrdmlah v0.8s, v1.8s, v2.8s
+  sqrdmlsh v0.8s, v1.8s, v2.8s
+  sqrdmlah v0.2s, v1.4h, v2.8h
+  sqrdmlsh v0.4s, v1.8h, v2.2s
+// CHECK-ERROR: error: invalid vector kind qualifier
+// CHECK-ERROR:   sqrdmlah v0.2h, v1.2h, v2.2h
+// CHECK-ERROR:            ^
+// CHECK-ERROR: error: invalid vector kind qualifier
+// CHECK-ERROR:   sqrdmlah v0.2h, v1.2h, v2.2h
+// CHECK-ERROR:                   ^
+// CHECK-ERROR: error: invalid vector kind qualifier
+// CHECK-ERROR:   sqrdmlah v0.2h, v1.2h, v2.2h
+// CHECK-ERROR:                          ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:   sqrdmlah v0.2h, v1.2h, v2.2h
+// CHECK-ERROR:            ^
+// CHECK-ERROR: error: invalid vector kind qualifier
+// CHECK-ERROR:   sqrdmlsh v0.2h, v1.2h, v2.2h
+// CHECK-ERROR:            ^
+// CHECK-ERROR: error: invalid vector kind qualifier
+// CHECK-ERROR:   sqrdmlsh v0.2h, v1.2h, v2.2h
+// CHECK-ERROR:                   ^
+// CHECK-ERROR: error: invalid vector kind qualifier
+// CHECK-ERROR:   sqrdmlsh v0.2h, v1.2h, v2.2h
+// CHECK-ERROR:                          ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:   sqrdmlsh v0.2h, v1.2h, v2.2h
+// CHECK-ERROR:            ^
+// CHECK-ERROR: error: invalid vector kind qualifier
+// CHECK-ERROR:   sqrdmlah v0.8s, v1.8s, v2.8s
+// CHECK-ERROR:            ^
+// CHECK-ERROR: error: invalid vector kind qualifier
+// CHECK-ERROR:   sqrdmlah v0.8s, v1.8s, v2.8s
+// CHECK-ERROR:                   ^
+// CHECK-ERROR: error: invalid vector kind qualifier
+// CHECK-ERROR:   sqrdmlah v0.8s, v1.8s, v2.8s
+// CHECK-ERROR:                          ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:   sqrdmlah v0.8s, v1.8s, v2.8s
+// CHECK-ERROR:            ^
+// CHECK-ERROR: error: invalid vector kind qualifier
+// CHECK-ERROR:   sqrdmlsh v0.8s, v1.8s, v2.8s
+// CHECK-ERROR:            ^
+// CHECK-ERROR: error: invalid vector kind qualifier
+// CHECK-ERROR:   sqrdmlsh v0.8s, v1.8s, v2.8s
+// CHECK-ERROR:                   ^
+// CHECK-ERROR: error: invalid vector kind qualifier
+// CHECK-ERROR:   sqrdmlsh v0.8s, v1.8s, v2.8s
+// CHECK-ERROR:                          ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:   sqrdmlsh v0.8s, v1.8s, v2.8s
+// CHECK-ERROR:            ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:   sqrdmlah v0.2s, v1.4h, v2.8h
+// CHECK-ERROR:                   ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:   sqrdmlsh v0.4s, v1.8h, v2.2s
+// CHECK-ERROR:                   ^
+
+  //AdvSIMD RDMA scalar
+  sqrdmlah h0, h1, h2
+  sqrdmlsh h0, h1, h2
+  sqrdmlah s0, s1, s2
+  sqrdmlsh s0, s1, s2
+// CHECK: sqrdmlah h0, h1, h2  // encoding: [0x20,0x84,0x42,0x7e]
+// CHECK: sqrdmlsh h0, h1, h2  // encoding: [0x20,0x8c,0x42,0x7e]
+// CHECK: sqrdmlah s0, s1, s2  // encoding: [0x20,0x84,0x82,0x7e]
+// CHECK: sqrdmlsh s0, s1, s2  // encoding: [0x20,0x8c,0x82,0x7e]
+
+  //AdvSIMD RDMA vector by-element
+  sqrdmlah v0.4h, v1.4h, v2.h[3]
+  sqrdmlsh v0.4h, v1.4h, v2.h[3]
+  sqrdmlah v0.2s, v1.2s, v2.s[1]
+  sqrdmlsh v0.2s, v1.2s, v2.s[1]
+  sqrdmlah v0.8h, v1.8h, v2.h[3]
+  sqrdmlsh v0.8h, v1.8h, v2.h[3]
+  sqrdmlah v0.4s, v1.4s, v2.s[3]
+  sqrdmlsh v0.4s, v1.4s, v2.s[3]
+// CHECK: sqrdmlah v0.4h, v1.4h, v2.h[3]  // encoding: [0x20,0xd0,0x72,0x2f]
+// CHECK: sqrdmlsh v0.4h, v1.4h, v2.h[3]  // encoding: [0x20,0xf0,0x72,0x2f]
+// CHECK: sqrdmlah v0.2s, v1.2s, v2.s[1]  // encoding: [0x20,0xd0,0xa2,0x2f]
+// CHECK: sqrdmlsh v0.2s, v1.2s, v2.s[1]  // encoding: [0x20,0xf0,0xa2,0x2f]
+// CHECK: sqrdmlah v0.8h, v1.8h, v2.h[3]  // encoding: [0x20,0xd0,0x72,0x6f]
+// CHECK: sqrdmlsh v0.8h, v1.8h, v2.h[3]  // encoding: [0x20,0xf0,0x72,0x6f]
+// CHECK: sqrdmlah v0.4s, v1.4s, v2.s[3]  // encoding: [0x20,0xd8,0xa2,0x6f]
+// CHECK: sqrdmlsh v0.4s, v1.4s, v2.s[3]  // encoding: [0x20,0xf8,0xa2,0x6f]
+
+  sqrdmlah v0.4s, v1.2s, v2.s[1]
+  sqrdmlsh v0.2s, v1.2d, v2.s[1]
+  sqrdmlah v0.8h, v1.8h, v2.s[3]
+  sqrdmlsh v0.8h, v1.8h, v2.h[8]
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:   sqrdmlah v0.4s, v1.2s, v2.s[1]
+// CHECK-ERROR:                   ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:   sqrdmlsh v0.2s, v1.2d, v2.s[1]
+// CHECK-ERROR:                   ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:   sqrdmlah v0.8h, v1.8h, v2.s[3]
+// CHECK-ERROR:                          ^
+// CHECK-ERROR: error: vector lane must be an integer in range [0, 7].
+// CHECK-ERROR:   sqrdmlsh v0.8h, v1.8h, v2.h[8]
+// CHECK-ERROR:                              ^
+
+  //AdvSIMD RDMA scalar by-element
+  sqrdmlah h0, h1, v2.h[3]
+  sqrdmlsh h0, h1, v2.h[3]
+  sqrdmlah s0, s1, v2.s[3]
+  sqrdmlsh s0, s1, v2.s[3]
+// CHECK: sqrdmlah h0, h1, v2.h[3]  // encoding: [0x20,0xd0,0x72,0x7f]
+// CHECK: sqrdmlsh h0, h1, v2.h[3]  // encoding: [0x20,0xf0,0x72,0x7f]
+// CHECK: sqrdmlah s0, s1, v2.s[3]  // encoding: [0x20,0xd8,0xa2,0x7f]
+// CHECK: sqrdmlsh s0, s1, v2.s[3]  // encoding: [0x20,0xf8,0xa2,0x7f]
+
+  sqrdmlah b0, h1, v2.h[3]
+  sqrdmlah s0, d1, v2.s[3]
+  sqrdmlsh h0, h1, v2.s[3]
+  sqrdmlsh s0, s1, v2.s[4]
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:   sqrdmlah b0, h1, v2.h[3]
+// CHECK-ERROR:            ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:   sqrdmlah s0, d1, v2.s[3]
+// CHECK-ERROR:                ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:   sqrdmlsh h0, h1, v2.s[3]
+// CHECK-ERROR:                    ^
+// CHECK-ERROR: error: vector lane must be an integer in range [0, 3].
+// CHECK-ERROR:   sqrdmlsh s0, s1, v2.s[4]
+// CHECK-ERROR:                        ^
diff --git a/test/MC/AArch64/armv8.1a-vhe.s b/test/MC/AArch64/armv8.1a-vhe.s
new file mode 100644
index 000000000000..2bee4e213299
--- /dev/null
+++ b/test/MC/AArch64/armv8.1a-vhe.s
@@ -0,0 +1,61 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.1a < %s | FileCheck %s
+
+
+//------------------------------------------------------------------------------
+// Virtualization Host Extensions
+//------------------------------------------------------------------------------
+    msr TTBR1_EL2, x0
+    msr CONTEXTIDR_EL2, x0
+    msr CNTHV_TVAL_EL2, x0
+    msr CNTHV_CVAL_EL2, x0
+    msr CNTHV_CTL_EL2, x0
+    msr SCTLR_EL12, x0
+    msr CPACR_EL12, x0
+    msr TTBR0_EL12, x0
+    msr TTBR1_EL12, x0
+    msr TCR_EL12, x0
+    msr AFSR0_EL12, x0
+    msr AFSR1_EL12, x0
+    msr ESR_EL12, x0
+    msr FAR_EL12, x0
+    msr MAIR_EL12, x0
+    msr AMAIR_EL12, x0
+    msr VBAR_EL12, x0
+    msr CONTEXTIDR_EL12, x0
+    msr CNTKCTL_EL12, x0
+    msr CNTP_TVAL_EL02, x0
+    msr CNTP_CTL_EL02, x0
+    msr CNTP_CVAL_EL02, x0
+    msr CNTV_TVAL_EL02, x0
+    msr CNTV_CTL_EL02, x0
+    msr CNTV_CVAL_EL02, x0
+    msr SPSR_EL12, x0
+    msr ELR_EL12, x0
+
+// CHECK:   msr TTBR1_EL2, x0           // encoding: [0x20,0x20,0x1c,0xd5]
+// CHECK:   msr CONTEXTIDR_EL2, x0      // encoding: [0x20,0xd0,0x1c,0xd5]
+// CHECK:   msr CNTHV_TVAL_EL2, x0      // encoding: [0x00,0xe3,0x1c,0xd5]
+// CHECK:   msr CNTHV_CVAL_EL2, x0      // encoding: [0x40,0xe3,0x1c,0xd5]
+// CHECK:   msr CNTHV_CTL_EL2, x0       // encoding: [0x20,0xe3,0x1c,0xd5]
+// CHECK:   msr SCTLR_EL12, x0          // encoding: [0x00,0x10,0x1d,0xd5]
+// CHECK:   msr CPACR_EL12, x0          // encoding: [0x40,0x10,0x1d,0xd5]
+// CHECK:   msr TTBR0_EL12, x0          // encoding: [0x00,0x20,0x1d,0xd5]
+// CHECK:   msr TTBR1_EL12, x0          // encoding: [0x20,0x20,0x1d,0xd5]
+// CHECK:   msr TCR_EL12, x0            // encoding: [0x40,0x20,0x1d,0xd5]
+// CHECK:   msr AFSR0_EL12, x0          // encoding: [0x00,0x51,0x1d,0xd5]
+// CHECK:   msr AFSR1_EL12, x0          // encoding: [0x20,0x51,0x1d,0xd5]
+// CHECK:   msr ESR_EL12, x0            // encoding: [0x00,0x52,0x1d,0xd5]
+// CHECK:   msr FAR_EL12, x0            // encoding: [0x00,0x60,0x1d,0xd5]
+// CHECK:   msr MAIR_EL12, x0           // encoding: [0x00,0xa2,0x1d,0xd5]
+// CHECK:   msr AMAIR_EL12, x0          // encoding: [0x00,0xa3,0x1d,0xd5]
+// CHECK:   msr VBAR_EL12, x0           // encoding: [0x00,0xc0,0x1d,0xd5]
+// CHECK:   msr CONTEXTIDR_EL12, x0     // encoding: [0x20,0xd0,0x1d,0xd5]
+// CHECK:   msr CNTKCTL_EL12, x0        // encoding: [0x00,0xe1,0x1d,0xd5]
+// CHECK:   msr CNTP_TVAL_EL02, x0      // encoding: [0x00,0xe2,0x1d,0xd5]
+// CHECK:   msr CNTP_CTL_EL02, x0       // encoding: [0x20,0xe2,0x1d,0xd5]
+// CHECK:   msr CNTP_CVAL_EL02, x0      // encoding: [0x40,0xe2,0x1d,0xd5]
+// CHECK:   msr CNTV_TVAL_EL02, x0      // encoding: [0x00,0xe3,0x1d,0xd5]
+// CHECK:   msr CNTV_CTL_EL02, x0       // encoding: [0x20,0xe3,0x1d,0xd5]
+// CHECK:   msr CNTV_CVAL_EL02, x0      // encoding: [0x40,0xe3,0x1d,0xd5]
+// CHECK:   msr SPSR_EL12, x0           // encoding: [0x00,0x40,0x1d,0xd5]
+// CHECK:   msr ELR_EL12, x0            // encoding: [0x20,0x40,0x1d,0xd5]
diff --git a/test/MC/AArch64/basic-a64-diagnostics.s b/test/MC/AArch64/basic-a64-diagnostics.s
index 07e6d012e934..1d7ba710a9a1 100644
--- a/test/MC/AArch64/basic-a64-diagnostics.s
+++ b/test/MC/AArch64/basic-a64-diagnostics.s
@@ -1088,6 +1088,23 @@
 // CHECK-ERROR-NEXT:         ubfx w3, wsp, #10, #8
 // CHECK-ERROR-NEXT:                  ^
 
+        bfc wsp, #3, #6
+        bfc w4, #2, #31
+        bfc sp, #0, #1
+        bfc x6, #0, #0
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR-NEXT:        bfc wsp, #3, #6
+// CHECK-ERROR-NEXT:            ^
+// CHECK-ERROR-NEXT: error: requested insert overflows register
+// CHECK-ERROR-NEXT:         bfc w4, #2, #31
+// CHECK-ERROR-NEXT:                     ^
+// CHECK-ERROR-NEXT: error: invalid operand for instruction
+// CHECK-ERROR-NEXT:         bfc sp, #0, #1
+// CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: error: expected integer in range [1, 32]
+// CHECK-ERROR-NEXT:         bfc x6, #0, #0
+// CHECK-ERROR-NEXT:                     ^
+
 //------------------------------------------------------------------------------
 // Compare & branch (immediate)
 //------------------------------------------------------------------------------
diff --git a/test/MC/AArch64/basic-a64-instructions.s b/test/MC/AArch64/basic-a64-instructions.s
index dd8dfd4e36d1..75c86efd2071 100644
--- a/test/MC/AArch64/basic-a64-instructions.s
+++ b/test/MC/AArch64/basic-a64-instructions.s
@@ -978,7 +978,7 @@ _func:
         bfm x5, x6, #12, #63
 // CHECK: bfi      x4, x5, #52, #11           // encoding: [0xa4,0x28,0x4c,0xb3]
 // CHECK: bfxil    xzr, x4, #0, #1            // encoding: [0x9f,0x00,0x40,0xb3]
-// CHECK: bfi      x4, xzr, #1, #6            // encoding: [0xe4,0x17,0x7f,0xb3]
+// CHECK: bfc      x4, #1, #6                 // encoding: [0xe4,0x17,0x7f,0xb3]
 // CHECK: bfxil    x5, x6, #12, #52           // encoding: [0xc5,0xfc,0x4c,0xb3]
 
         sxtb w1, w2
@@ -1078,7 +1078,7 @@ _func:
 // CHECK: bfxil    w9, w10, #0, #32           // encoding: [0x49,0x7d,0x00,0x33]
 // CHECK: bfi      w11, w12, #31, #1          // encoding: [0x8b,0x01,0x01,0x33]
 // CHECK: bfi      w13, w14, #29, #3          // encoding: [0xcd,0x09,0x03,0x33]
-// CHECK: bfi      xzr, xzr, #10, #11         // encoding: [0xff,0x2b,0x76,0xb3]
+// CHECK: bfc      xzr, #10, #11              // encoding: [0xff,0x2b,0x76,0xb3]
 
         bfxil w9, w10, #0, #1
         bfxil x2, x3, #63, #1
@@ -1132,6 +1132,16 @@ _func:
 // CHECK: lsr     w11, w12, #31           // encoding: [0x8b,0x7d,0x1f,0x53]
 // CHECK: lsr     w13, w14, #29           // encoding: [0xcd,0x7d,0x1d,0x53]
 // CHECK: ubfx    xzr, xzr, #10, #11      // encoding: [0xff,0x53,0x4a,0xd3]
+
+        bfc w3, #0, #32
+        bfc wzr, #31, #1
+        bfc x0, #5, #9
+        bfc xzr, #63, #1
+// CHECK: bfc w3, #0, #32             // encoding: [0xe3,0x7f,0x00,0x33]
+// CHECK: bfc wzr, #31, #1            // encoding: [0xff,0x03,0x01,0x33]
+// CHECK: bfc x0, #5, #9              // encoding: [0xe0,0x23,0x7b,0xb3]
+// CHECK: bfc xzr, #63, #1            // encoding: [0xff,0x03,0x41,0xb3]
+
 //------------------------------------------------------------------------------
 // Compare & branch (immediate)
 //------------------------------------------------------------------------------
diff --git a/test/MC/AArch64/dot-req.s b/test/MC/AArch64/dot-req.s
index 947f945bded8..a557f0c67589 100644
--- a/test/MC/AArch64/dot-req.s
+++ b/test/MC/AArch64/dot-req.s
@@ -1,7 +1,9 @@
-// RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s 2>&1 | FileCheck %s
 
 bar:
         fred .req x5
+// CHECK-NOT: ignoring redefinition of register alias 'fred'
+        fred .req x5
         mov fred, x11
         .unreq fred
         fred .req w6
diff --git a/test/MC/AArch64/elf-extern.s b/test/MC/AArch64/elf-extern.s
index dfa3fb002ed5..14c26c1b9977 100644
--- a/test/MC/AArch64/elf-extern.s
+++ b/test/MC/AArch64/elf-extern.s
@@ -27,7 +27,7 @@ check_extern:                           // @check_extern
 
 
 // CHECK: Relocations [
-// CHECK:   Section (2) .rela.text {
+// CHECK:   Section {{.*}} .rela.text {
 // CHECK:     0x{{[0-9,A-F]+}} R_AARCH64_CALL26 memcpy
 // CHECK:   }
 // CHECK: ]
diff --git a/test/MC/AArch64/elf-globaladdress.ll b/test/MC/AArch64/elf-globaladdress.ll
index 7d031e6a3160..d8a0b5b8d5e7 100644
--- a/test/MC/AArch64/elf-globaladdress.ll
+++ b/test/MC/AArch64/elf-globaladdress.ll
@@ -12,16 +12,16 @@
 @var64 = global i64 0
 
 define void @loadstore() {
-    %val8 = load i8* @var8
+    %val8 = load i8, i8* @var8
     store volatile i8 %val8, i8* @var8
 
-    %val16 = load i16* @var16
+    %val16 = load i16, i16* @var16
     store volatile i16 %val16, i16* @var16
 
-    %val32 = load i32* @var32
+    %val32 = load i32, i32* @var32
     store volatile i32 %val32, i32* @var32
 
-    %val64 = load i64* @var64
+    %val64 = load i64, i64* @var64
     store volatile i64 %val64, i64* @var64
 
     ret void
@@ -40,7 +40,7 @@ define void @address() {
 ; OBJ: }
 
 ; OBJ: Relocations [
-; OBJ:   Section (2) .rela.text {
+; OBJ:   Section {{.*}} .rela.text {
 ; OBJ:     0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21   var8
 ; OBJ:     0x{{[0-9,A-F]+}} R_AARCH64_LDST8_ABS_LO12_NC  var8
 ; OBJ:     0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21   var16
diff --git a/test/MC/AArch64/elf-reloc-addsubimm.s b/test/MC/AArch64/elf-reloc-addsubimm.s
index e37991bfba1c..58e9a6e227be 100644
--- a/test/MC/AArch64/elf-reloc-addsubimm.s
+++ b/test/MC/AArch64/elf-reloc-addsubimm.s
@@ -4,7 +4,7 @@
         add x2, x3, #:lo12:some_label
 
 // OBJ:      Relocations [
-// OBJ-NEXT:   Section (2) .rela.text {
+// OBJ-NEXT:   Section {{.*}} .rela.text {
 // OBJ-NEXT:     0x0 R_AARCH64_ADD_ABS_LO12_NC some_label 0x0
 // OBJ-NEXT:   }
 // OBJ-NEXT: ]
diff --git a/test/MC/AArch64/elf-reloc-ldrlit.s b/test/MC/AArch64/elf-reloc-ldrlit.s
index d4c3a4eb50d0..017d66cb2a2d 100644
--- a/test/MC/AArch64/elf-reloc-ldrlit.s
+++ b/test/MC/AArch64/elf-reloc-ldrlit.s
@@ -7,7 +7,7 @@
         prfm pldl3keep, some_label
 
 // OBJ:      Relocations [
-// OBJ-NEXT:   Section (2) .rela.text {
+// OBJ-NEXT:   Section {{.*}} .rela.text {
 // OBJ-NEXT:     0x0 R_AARCH64_LD_PREL_LO19 some_label 0x0
 // OBJ-NEXT:     0x4 R_AARCH64_LD_PREL_LO19 some_label 0x0
 // OBJ-NEXT:     0x8 R_AARCH64_LD_PREL_LO19 some_label 0x0
diff --git a/test/MC/AArch64/elf-reloc-ldstunsimm.s b/test/MC/AArch64/elf-reloc-ldstunsimm.s
index 371e7e51f245..e68937ceddb8 100644
--- a/test/MC/AArch64/elf-reloc-ldstunsimm.s
+++ b/test/MC/AArch64/elf-reloc-ldstunsimm.s
@@ -8,7 +8,7 @@
         str q0, [sp, #:lo12:some_label]
 
 // OBJ:      Relocations [
-// OBJ-NEXT:   Section (2) .rela.text {
+// OBJ-NEXT:   Section {{.*}} .rela.text {
 // OBJ-NEXT:     0x0  R_AARCH64_LDST8_ABS_LO12_NC   some_label 0x0
 // OBJ-NEXT:     0x4  R_AARCH64_LDST16_ABS_LO12_NC  some_label 0x0
 // OBJ-NEXT:     0x8  R_AARCH64_LDST32_ABS_LO12_NC  some_label 0x0
diff --git a/test/MC/AArch64/elf-reloc-movw.s b/test/MC/AArch64/elf-reloc-movw.s
index 333159562c0f..fda160fb831c 100644
--- a/test/MC/AArch64/elf-reloc-movw.s
+++ b/test/MC/AArch64/elf-reloc-movw.s
@@ -23,7 +23,7 @@
         movn x19, #:abs_g2_s:some_label
 
 // OBJ:      Relocations [
-// OBJ-NEXT:   Section (2) .rela.text {
+// OBJ-NEXT:   Section {{.*}} .rela.text {
 // OBJ-NEXT:     0x0  R_AARCH64_MOVW_UABS_G0    some_label 0x0
 // OBJ-NEXT:     0x4  R_AARCH64_MOVW_UABS_G0_NC some_label 0x0
 // OBJ-NEXT:     0x8  R_AARCH64_MOVW_UABS_G1    some_label 0x0
diff --git a/test/MC/AArch64/elf-reloc-pcreladdressing.s b/test/MC/AArch64/elf-reloc-pcreladdressing.s
index 093891d931aa..30acb6d664b5 100644
--- a/test/MC/AArch64/elf-reloc-pcreladdressing.s
+++ b/test/MC/AArch64/elf-reloc-pcreladdressing.s
@@ -8,7 +8,7 @@
         ldr x0, [x5, #:got_lo12:some_label]
 
 // OBJ:      Relocations [
-// OBJ-NEXT:   Section (2) .rela.text {
+// OBJ-NEXT:   Section {{.*}} .rela.text {
 // OBJ-NEXT:     0x0 R_AARCH64_ADR_PREL_LO21    some_label 0x0
 // OBJ-NEXT:     0x4 R_AARCH64_ADR_PREL_PG_HI21 some_label 0x0
 // OBJ-NEXT:     0x8 R_AARCH64_ADR_GOT_PAGE     some_label 0x0
diff --git a/test/MC/AArch64/elf-reloc-tstb.s b/test/MC/AArch64/elf-reloc-tstb.s
index 25c98163b584..e6828e69171c 100644
--- a/test/MC/AArch64/elf-reloc-tstb.s
+++ b/test/MC/AArch64/elf-reloc-tstb.s
@@ -5,7 +5,7 @@
         tbnz w3, #15, somewhere
 
 // OBJ:      Relocations [
-// OBJ-NEXT:   Section (2) .rela.text {
+// OBJ-NEXT:   Section {{.*}} .rela.text {
 // OBJ-NEXT:     0x0  R_AARCH64_TSTBR14 somewhere 0x0
 // OBJ-NEXT:     0x4  R_AARCH64_TSTBR14 somewhere 0x0
 // OBJ-NEXT:   }
diff --git a/test/MC/AArch64/elf-reloc-uncondbrimm.s b/test/MC/AArch64/elf-reloc-uncondbrimm.s
index 9ac66bd876a7..ff852be37b60 100644
--- a/test/MC/AArch64/elf-reloc-uncondbrimm.s
+++ b/test/MC/AArch64/elf-reloc-uncondbrimm.s
@@ -5,7 +5,7 @@
         bl somewhere
 
 // OBJ:      Relocations [
-// OBJ-NEXT:   Section (2) .rela.text {
+// OBJ-NEXT:   Section {{.*}} .rela.text {
 // OBJ-NEXT:     0x0 R_AARCH64_JUMP26 somewhere 0x0
 // OBJ-NEXT:     0x4 R_AARCH64_CALL26 somewhere 0x0
 // OBJ-NEXT:   }
diff --git a/test/MC/AArch64/expr-shr.s b/test/MC/AArch64/expr-shr.s
new file mode 100644
index 000000000000..aa23878e5adc
--- /dev/null
+++ b/test/MC/AArch64/expr-shr.s
@@ -0,0 +1,8 @@
+// RUN: llvm-mc -triple aarch64-unknown-unknown-elf %s | FileCheck %s --check-prefix=ELF
+// RUN: llvm-mc -triple aarch64-unknown-darwin %s | FileCheck %s --check-prefix=DARWIN
+
+.data
+
+// ELF: .xword 3
+// DARWIN: .quad 3
+.quad (~0 >> 62)
diff --git a/test/MC/AArch64/inst-directive.s b/test/MC/AArch64/inst-directive.s
index 6a4b64eeaaf0..3bb620f689d1 100644
--- a/test/MC/AArch64/inst-directive.s
+++ b/test/MC/AArch64/inst-directive.s
@@ -15,7 +15,7 @@ aarch64_inst:
 // CHECK-ASM:        .globl  aarch64_inst
 // CHECK-ASM:        .type   aarch64_inst,@function
 // CHECK-ASM: aarch64_inst:
-// CHECK-ASM:        .inst   0x5E104020
+// CHECK-ASM:        .inst   0x5e104020
 
 // CHECK-OBJ: Section {
 // CHECK-OBJ:   Name: .inst.aarch64_inst
diff --git a/test/MC/AArch64/tls-relocs.s b/test/MC/AArch64/tls-relocs.s
index 9e94a52e5afe..bac4f20cbecc 100644
--- a/test/MC/AArch64/tls-relocs.s
+++ b/test/MC/AArch64/tls-relocs.s
@@ -18,7 +18,7 @@
 // CHECK:                                 //   fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw
 
 // CHECK-ELF:      Relocations [
-// CHECK-ELF-NEXT:   Section (2) .rela.text {
+// CHECK-ELF-NEXT:   Section {{.*}} .rela.text {
 // CHECK-ELF-NEXT:     0x0 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM:[^ ]+]]
 // CHECK-ELF-NEXT:     0x4 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]]
 // CHECK-ELF-NEXT:     0x8 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]]
diff --git a/test/MC/ARM/2010-11-30-reloc-movt.s b/test/MC/ARM/2010-11-30-reloc-movt.s
index 9de88f08b6d0..dc6960ba6b88 100644
--- a/test/MC/ARM/2010-11-30-reloc-movt.s
+++ b/test/MC/ARM/2010-11-30-reloc-movt.s
@@ -34,6 +34,7 @@ barf:                                   @ @barf
 // CHECK-NEXT:       0000: 00482DE9 000000E3 000040E3 FEFFFFEB
 // CHECK-NEXT:       0010: 0088BDE8
 // CHECK-NEXT:     )
+// CHECK:          Name: .rel.text
 // CHECK:          Relocations [
 // CHECK-NEXT:       0x4 R_ARM_MOVW_ABS_NC a
 // CHECK-NEXT:       0x8 R_ARM_MOVT_ABS
diff --git a/test/MC/ARM/Windows/invalid-relocation.s b/test/MC/ARM/Windows/invalid-relocation.s
new file mode 100644
index 000000000000..4f4c59839a6a
--- /dev/null
+++ b/test/MC/ARM/Windows/invalid-relocation.s
@@ -0,0 +1,14 @@
+# RUN: not llvm-mc -triple thumbv7-windows -filetype obj -o /dev/null 2>&1 %s \
+# RUN:     | FileCheck %s
+
+	.def invalid_relocation
+		.type 32
+		.scl 2
+	.endef
+	.global invalid_relocation
+	.thumb_func
+invalid_relocation:
+	adr r0, invalid_relocation+1
+
+# CHECK: LLVM ERROR: unsupported relocation type: fixup_t2_adr_pcrel_12
+
diff --git a/test/MC/ARM/arm-elf-symver.s b/test/MC/ARM/arm-elf-symver.s
index 5fb1f6a0f3eb..4303540e82aa 100644
--- a/test/MC/ARM/arm-elf-symver.s
+++ b/test/MC/ARM/arm-elf-symver.s
@@ -23,7 +23,7 @@ defined3:
 global1:
 
 @ CHECK: Relocations [
-@ CHECK-NEXT:   Section (2) .rel.text {
+@ CHECK-NEXT:   Section {{.*}} .rel.text {
 @ CHECK-NEXT:     0x0 R_ARM_ABS32 .text 0x0
 @ CHECK-NEXT:     0x4 R_ARM_ABS32 bar2@zed 0x0
 @ CHECK-NEXT:     0x8 R_ARM_ABS32 .text 0x0
@@ -39,7 +39,7 @@ global1:
 @ CHECK-NEXT:     Binding: Local (0x0)
 @ CHECK-NEXT:     Type: None (0x0)
 @ CHECK-NEXT:     Other: 0
-@ CHECK-NEXT:     Section: .text (0x1)
+@ CHECK-NEXT:     Section: .text
 @ CHECK-NEXT:   }
 @ CHECK-NEXT:   Symbol {
 @ CHECK-NEXT:     Name: bar3@@zed
@@ -48,7 +48,7 @@ global1:
 @ CHECK-NEXT:     Binding: Local (0x0)
 @ CHECK-NEXT:     Type: None (0x0)
 @ CHECK-NEXT:     Other: 0
-@ CHECK-NEXT:     Section: .text (0x1)
+@ CHECK-NEXT:     Section: .text
 @ CHECK-NEXT:   }
 @ CHECK-NEXT:   Symbol {
 @ CHECK-NEXT:     Name: bar5@@zed
@@ -57,7 +57,7 @@ global1:
 @ CHECK-NEXT:     Binding: Local (0x0)
 @ CHECK-NEXT:     Type: None (0x0)
 @ CHECK-NEXT:     Other: 0
-@ CHECK-NEXT:     Section: .text (0x1)
+@ CHECK-NEXT:     Section: .text
 @ CHECK-NEXT:   }
 @ CHECK-NEXT:   Symbol {
 @ CHECK-NEXT:     Name: defined1
@@ -66,7 +66,7 @@ global1:
 @ CHECK-NEXT:     Binding: Local (0x0)
 @ CHECK-NEXT:     Type: None (0x0)
 @ CHECK-NEXT:     Other: 0
-@ CHECK-NEXT:     Section: .text (0x1)
+@ CHECK-NEXT:     Section: .text
 @ CHECK-NEXT:   }
 @ CHECK-NEXT:   Symbol {
 @ CHECK-NEXT:     Name: defined2
@@ -75,7 +75,7 @@ global1:
 @ CHECK-NEXT:     Binding: Local (0x0)
 @ CHECK-NEXT:     Type: None (0x0)
 @ CHECK-NEXT:     Other: 0
-@ CHECK-NEXT:     Section: .text (0x1)
+@ CHECK-NEXT:     Section: .text
 @ CHECK-NEXT:   }
 @ CHECK-NEXT:   Symbol {
 @ CHECK-NEXT:     Name: .text (0)
@@ -84,7 +84,7 @@ global1:
 @ CHECK-NEXT:     Binding: Local (0x0)
 @ CHECK-NEXT:     Type: Section (0x3)
 @ CHECK-NEXT:     Other: 0
-@ CHECK-NEXT:     Section: .text (0x1)
+@ CHECK-NEXT:     Section: .text
 @ CHECK-NEXT:   }
 @ CHECK-NEXT:   Symbol {
 @ CHECK-NEXT:     Name: .data (0)
@@ -93,7 +93,7 @@ global1:
 @ CHECK-NEXT:     Binding: Local (0x0)
 @ CHECK-NEXT:     Type: Section (0x3)
 @ CHECK-NEXT:     Other: 0
-@ CHECK-NEXT:     Section: .data (0x3)
+@ CHECK-NEXT:     Section: .data
 @ CHECK-NEXT:   }
 @ CHECK-NEXT:   Symbol {
 @ CHECK-NEXT:     Name: .bss (0)
@@ -102,7 +102,7 @@ global1:
 @ CHECK-NEXT:     Binding: Local (0x0)
 @ CHECK-NEXT:     Type: Section (0x3)
 @ CHECK-NEXT:     Other: 0
-@ CHECK-NEXT:     Section: .bss (0x4)
+@ CHECK-NEXT:     Section: .bss
 @ CHECK-NEXT:   }
 @ CHECK-NEXT:   Symbol {
 @ CHECK-NEXT:     Name: g1@@zed
@@ -111,7 +111,7 @@ global1:
 @ CHECK-NEXT:     Binding: Global (0x1)
 @ CHECK-NEXT:     Type: None (0x0)
 @ CHECK-NEXT:     Other: 0
-@ CHECK-NEXT:     Section: .text (0x1)
+@ CHECK-NEXT:     Section: .text
 @ CHECK-NEXT:   }
 @ CHECK-NEXT:   Symbol {
 @ CHECK-NEXT:     Name: global1
@@ -120,7 +120,7 @@ global1:
 @ CHECK-NEXT:     Binding: Global (0x1)
 @ CHECK-NEXT:     Type: None (0x0)
 @ CHECK-NEXT:     Other: 0
-@ CHECK-NEXT:     Section: .text (0x1)
+@ CHECK-NEXT:     Section: .text
 @ CHECK-NEXT:   }
 @ CHECK-NEXT:   Symbol {
 @ CHECK-NEXT:     Name: bar2@zed
diff --git a/test/MC/ARM/arm-thumb-cpus.s b/test/MC/ARM/arm-thumb-cpus.s
index 9005c7f2a174..459b5c5fe00e 100644
--- a/test/MC/ARM/arm-thumb-cpus.s
+++ b/test/MC/ARM/arm-thumb-cpus.s
@@ -16,6 +16,9 @@
 @ RUN: not llvm-mc -show-encoding -triple=armv6m-eabi < %s 2>&1 \
 @ RUN:  | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
 
+@ RUN: not llvm-mc -show-encoding -triple=armv6sm-eabi < %s 2>&1 \
+@ RUN:  | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
+
         @ Make sure correct diagnostics are given for CPUs without support for
         @ one or other of the execution states.
         .thumb
diff --git a/test/MC/ARM/arm11-hint-instr.s b/test/MC/ARM/arm11-hint-instr.s
new file mode 100644
index 000000000000..6f5a374e417c
--- /dev/null
+++ b/test/MC/ARM/arm11-hint-instr.s
@@ -0,0 +1,69 @@
+@ RUN: not llvm-mc -triple=armv6 -show-encoding < %s > %t1 2> %t2
+@ RUN: FileCheck --check-prefix=CHECK-V6 %s < %t1
+@ RUN: FileCheck --check-prefix=CHECK-ERROR-V6 %s < %t2
+@ RUN: llvm-mc -triple=armv6k -show-encoding < %s \
+@ RUN:     | FileCheck --check-prefix=CHECK-ARM %s
+@ RUN: llvm-mc -triple=armv6t2 -show-encoding < %s \
+@ RUN:     | FileCheck --check-prefix=CHECK-ARM %s
+@ RUN: llvm-mc -triple=thumb -mcpu=arm1156t2-s -show-encoding < %s \
+@ RUN:     | FileCheck --check-prefix=CHECK-THUMB %s
+@ RUN: llvm-mc -triple=armv6m -show-encoding < %s \
+@ RUN:     | FileCheck --check-prefix=CHECK-V6M %s
+
+  .syntax unified
+
+@------------------------------------------------------------------------------
+@ YIELD/WFE/WFI/SEV - are not supported pre v6K
+@------------------------------------------------------------------------------
+        nop
+        yield
+        wfe
+        wfi
+        sev
+
+
+@------------------------------------------------------------------------------
+@ v6 using ARM encoding
+@------------------------------------------------------------------------------
+@ CHECK-V6: mov	r0, r0                  @ encoding: [0x00,0x00,0xa0,0xe1]
+@ CHECK-ERROR-V6: error: instruction requires: armv6k
+@ CHECK-ERROR-V6: yield
+@ CHECK-ERROR-V6: ^
+@ CHECK-ERROR-V6: error: instruction requires: armv6k
+@ CHECK-ERROR-V6: wfe
+@ CHECK-ERROR-V6: ^
+@ CHECK-ERROR-V6: error: instruction requires: armv6k
+@ CHECK-ERROR-V6: wfi
+@ CHECK-ERROR-V6: error: instruction requires: armv6k
+@ CHECK-ERROR-V6: sev
+@ CHECK-ERROR-V6: ^
+
+@------------------------------------------------------------------------------
+@ v6K using ARM encoding
+@------------------------------------------------------------------------------
+@------------------------------------------------------------------------------
+@ v6T2 using ARM encoding (arm triple)
+@------------------------------------------------------------------------------
+@ CHECK-ARM: nop                             @ encoding: [0x00,0xf0,0x20,0xe3]
+@ CHECK-ARM: yield                           @ encoding: [0x01,0xf0,0x20,0xe3]
+@ CHECK-ARM: wfe                             @ encoding: [0x02,0xf0,0x20,0xe3]
+@ CHECK-ARM: wfi                             @ encoding: [0x03,0xf0,0x20,0xe3]
+@ CHECK-ARM: sev                             @ encoding: [0x04,0xf0,0x20,0xe3]
+
+@------------------------------------------------------------------------------
+@ v6T2 using THUMB encoding (thumb triple)
+@------------------------------------------------------------------------------
+@ CHECK-THUMB: nop                             @ encoding: [0x00,0xbf]
+@ CHECK-THUMB: yield                           @ encoding: [0x10,0xbf]
+@ CHECK-THUMB: wfe                             @ encoding: [0x20,0xbf]
+@ CHECK-THUMB: wfi                             @ encoding: [0x30,0xbf]
+@ CHECK-THUMB: sev                             @ encoding: [0x40,0xbf]
+
+@------------------------------------------------------------------------------
+@ v6M using THUMB encoding
+@------------------------------------------------------------------------------
+@ CHECK-V6M: nop                             @ encoding: [0x00,0xbf]
+@ CHECK-V6M: yield                           @ encoding: [0x10,0xbf]
+@ CHECK-V6M: wfe                             @ encoding: [0x20,0xbf]
+@ CHECK-V6M: wfi                             @ encoding: [0x30,0xbf]
+@ CHECK-V6M: sev                             @ encoding: [0x40,0xbf]
diff --git a/test/MC/ARM/basic-arm-instructions-v8.1a.s b/test/MC/ARM/basic-arm-instructions-v8.1a.s
new file mode 100644
index 000000000000..005f27bb3983
--- /dev/null
+++ b/test/MC/ARM/basic-arm-instructions-v8.1a.s
@@ -0,0 +1,206 @@
+//RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8.1a -mattr=neon -show-encoding < %s 2>%t | FileCheck %s --check-prefix=CHECK-V81aTHUMB
+//RUN: FileCheck --check-prefix=CHECK-ERROR <%t %s
+//RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.1a -mattr=neon -show-encoding < %s 2>%t | FileCheck %s --check-prefix=CHECK-V81aARM
+//RUN: FileCheck --check-prefix=CHECK-ERROR <%t %s
+
+//RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8 -mattr=neon -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8
+//RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8 -mattr=neon -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8
+
+
+  .text
+//CHECK-V8THUMB: .text
+
+  vqrdmlah.i8   q0, q1, q2
+  vqrdmlah.u16  d0, d1, d2
+  vqrdmlsh.f32  q3, q4, q5
+  vqrdmlsh.f64  d3, d5, d5
+
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlah.i8   q0, q1, q2
+//CHECK-ERROR:           ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlah.u16  d0, d1, d2
+//CHECK-ERROR:           ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlsh.f32  q3, q4, q5
+//CHECK-ERROR:           ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlsh.f64  d3, d5, d5
+//CHECK-ERROR:           ^
+//CHECK-V8: error: invalid operand for instruction
+//CHECK-V8:   vqrdmlah.i8   q0, q1, q2
+//CHECK-V8:           ^
+//CHECK-V8: error: invalid operand for instruction
+//CHECK-V8:   vqrdmlah.u16  d0, d1, d2
+//CHECK-V8:           ^
+//CHECK-V8: error: invalid operand for instruction
+//CHECK-V8:   vqrdmlsh.f32  q3, q4, q5
+//CHECK-V8:           ^
+//CHECK-V8: error: invalid operand for instruction
+//CHECK-V8   vqrdmlsh.f64  d3, d5, d5
+//CHECK-V8:           ^
+
+  vqrdmlah.s16    d0, d1, d2
+//CHECK-V81aARM:   vqrdmlah.s16  d0, d1, d2      @ encoding: [0x12,0x0b,0x11,0xf3]
+//CHECK-V81aTHUMB: vqrdmlah.s16  d0, d1, d2      @ encoding: [0x11,0xff,0x12,0x0b]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlah.s16    d0, d1, d2
+//CHECK-V8:  ^
+
+  vqrdmlah.s32  d0, d1, d2
+//CHECK-V81aARM:   vqrdmlah.s32  d0, d1, d2      @ encoding: [0x12,0x0b,0x21,0xf3]
+//CHECK-V81aTHUMB: vqrdmlah.s32  d0, d1, d2      @ encoding: [0x21,0xff,0x12,0x0b]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlah.s32  d0, d1, d2
+//CHECK-V8:  ^
+
+  vqrdmlah.s16  q0, q1, q2
+//CHECK-V81aARM:   vqrdmlah.s16  q0, q1, q2      @ encoding: [0x54,0x0b,0x12,0xf3]
+//CHECK-V81aTHUMB: vqrdmlah.s16  q0, q1, q2      @ encoding: [0x12,0xff,0x54,0x0b]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlah.s16  q0, q1, q2
+//CHECK-V8:  ^
+
+  vqrdmlah.s32  q2, q3, q0
+//CHECK-V81aARM:   vqrdmlah.s32  q2, q3, q0      @ encoding: [0x50,0x4b,0x26,0xf3]
+//CHECK-V81aTHUMB: vqrdmlah.s32  q2, q3, q0      @ encoding: [0x26,0xff,0x50,0x4b]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlah.s32  q2, q3, q0
+//CHECK-V8:  ^
+
+
+  vqrdmlsh.s16  d7, d6, d5
+//CHECK-V81aARM:   vqrdmlsh.s16  d7, d6, d5      @ encoding: [0x15,0x7c,0x16,0xf3]
+//CHECK-V81aTHUMB: vqrdmlsh.s16  d7, d6, d5      @ encoding: [0x16,0xff,0x15,0x7c]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlsh.s16  d7, d6, d5
+//CHECK-V8:  ^
+
+  vqrdmlsh.s32  d0, d1, d2
+//CHECK-V81aARM:   vqrdmlsh.s32  d0, d1, d2      @ encoding: [0x12,0x0c,0x21,0xf3]
+//CHECK-V81aTHUMB: vqrdmlsh.s32  d0, d1, d2      @ encoding: [0x21,0xff,0x12,0x0c]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlsh.s32  d0, d1, d2
+//CHECK-V8:  ^
+
+  vqrdmlsh.s16  q0, q1, q2
+//CHECK-V81aARM:   vqrdmlsh.s16  q0, q1, q2      @ encoding: [0x54,0x0c,0x12,0xf3]
+//CHECK-V81aTHUMB: vqrdmlsh.s16  q0, q1, q2      @ encoding: [0x12,0xff,0x54,0x0c]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlsh.s16  q0, q1, q2
+//CHECK-V8:  ^
+
+  vqrdmlsh.s32    q3, q4, q5
+//CHECK-V81aARM:   vqrdmlsh.s32  q3, q4, q5      @ encoding: [0x5a,0x6c,0x28,0xf3]
+//CHECK-V81aTHUMB: vqrdmlsh.s32  q3, q4, q5      @ encoding: [0x28,0xff,0x5a,0x6c]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlsh.s32  q3, q4, q5
+//CHECK-V8:  ^
+
+
+  vqrdmlah.i8   q0, q1, d9[7]
+  vqrdmlah.u16  d0, d1, d2[3]
+  vqrdmlsh.f32  q3, q4, d5[1]
+  vqrdmlsh.f64  d3, d5, d5[0]
+
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlah.i8   q0, q1, d9[7]
+//CHECK-ERROR:           ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlah.u16  d0, d1, d2[3]
+//CHECK-ERROR:           ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlsh.f32  q3, q4, d5[1]
+//CHECK-ERROR:           ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlsh.f64  d3, d5, d5[0]
+//CHECK-ERROR:           ^
+
+  vqrdmlah.s16  d0, d1, d2[0]
+//CHECK-V81aARM:   vqrdmlah.s16 d0, d1, d2[0]    @ encoding: [0x42,0x0e,0x91,0xf2]
+//CHECK-V81aTHUMB: vqrdmlah.s16  d0, d1, d2[0]   @ encoding: [0x91,0xef,0x42,0x0e]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlah.s16  d0, d1, d2[0]
+//CHECK-V8:  ^
+
+  vqrdmlah.s32  d0, d1, d2[0]
+//CHECK-V81aARM:   vqrdmlah.s32 d0, d1, d2[0]    @ encoding: [0x42,0x0e,0xa1,0xf2]
+//CHECK-V81aTHUMB: vqrdmlah.s32  d0, d1, d2[0]   @ encoding: [0xa1,0xef,0x42,0x0e]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlah.s32  d0, d1, d2[0]
+//CHECK-V8:  ^
+
+  vqrdmlah.s16  q0, q1, d2[0]
+//CHECK-V81aARM:   vqrdmlah.s16  q0, q1, d2[0]   @ encoding: [0x42,0x0e,0x92,0xf3]
+//CHECK-V81aTHUMB: vqrdmlah.s16  q0, q1, d2[0]   @ encoding: [0x92,0xff,0x42,0x0e]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlah.s16  q0, q1, d2[0]
+//CHECK-V8:  ^
+
+  vqrdmlah.s32  q0, q1, d2[0]
+//CHECK-V81aARM:   vqrdmlah.s32  q0, q1, d2[0]   @ encoding: [0x42,0x0e,0xa2,0xf3]
+//CHECK-V81aTHUMB: vqrdmlah.s32  q0, q1, d2[0]   @ encoding: [0xa2,0xff,0x42,0x0e]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlah.s32  q0, q1, d2[0]
+//CHECK-V8:  ^
+
+
+  vqrdmlsh.s16  d0, d1, d2[0]
+//CHECK-V81aARM:   vqrdmlsh.s16 d0, d1, d2[0]    @ encoding: [0x42,0x0f,0x91,0xf2]
+//CHECK-V81aTHUMB: vqrdmlsh.s16  d0, d1, d2[0]   @ encoding: [0x91,0xef,0x42,0x0f]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlsh.s16  d0, d1, d2[0]
+//CHECK-V8:  ^
+
+  vqrdmlsh.s32  d0, d1, d2[0]
+//CHECK-V81aARM:   vqrdmlsh.s32 d0, d1, d2[0]    @ encoding: [0x42,0x0f,0xa1,0xf2]
+//CHECK-V81aTHUMB: vqrdmlsh.s32  d0, d1, d2[0]   @ encoding: [0xa1,0xef,0x42,0x0f]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlsh.s32  d0, d1, d2[0]
+//CHECK-V8:  ^
+
+  vqrdmlsh.s16  q0, q1, d2[0]
+//CHECK-V81aARM:   vqrdmlsh.s16 q0, q1, d2[0]    @ encoding: [0x42,0x0f,0x92,0xf3]
+//CHECK-V81aTHUMB: vqrdmlsh.s16  q0, q1, d2[0]   @ encoding: [0x92,0xff,0x42,0x0f]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlsh.s16  q0, q1, d2[0]
+//CHECK-V8:  ^
+
+  vqrdmlsh.s32  q0, q1, d2[0]
+//CHECK-V81aARM:   vqrdmlsh.s32 q0, q1, d2[0]    @ encoding: [0x42,0x0f,0xa2,0xf3]
+//CHECK-V81aTHUMB: vqrdmlsh.s32  q0, q1, d2[0]   @ encoding: [0xa2,0xff,0x42,0x0f]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  vqrdmlsh.s32  q0, q1, d2[0]
+//CHECK-V8:  ^
+
+  setpan  #0
+//CHECK-V81aTHUMB:  setpan  #0                @       encoding: [0x10,0xb6]
+//CHECK-V81aARM:    setpan  #0                @       encoding: [0x00,0x00,0x10,0xf1]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  setpan  #0
+//CHECK-V8:  ^
+
+  setpan  #1
+//CHECK-V81aTHUMB:  setpan  #1                @       encoding: [0x18,0xb6]
+//CHECK-V81aARM:    setpan  #1                @       encoding: [0x00,0x02,0x10,0xf1]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8:  setpan  #1
+//CHECK-V8:  ^
+  setpan
+  setpan #-1
+  setpan #2
+//CHECK-ERROR: error: too few operands for instruction
+//CHECK-ERROR:  setpan
+//CHECK-ERROR:  ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:  setpan #-1
+//CHECK-ERROR:         ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:  setpan #2
+//CHECK-ERROR:         ^
+
+  it eq
+  setpaneq #0
+//CHECK-THUMB-ERROR: error: instruction 'setpan' is not predicable, but condition code specified
+//CHECK-THUMB-ERROR:  setpaneq #0
+//CHECK-THUMB-ERROR:  ^
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 616674e56350..a1f13b76dda3 100644
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -1509,6 +1509,7 @@ Lforward:
         mvn r3, $7
         mvn r3, 7
         mvn r3, -7
+        mvn r7, #~0xffffff00
         mvn r4, #0xff0
         mvn r5, #0xff0000
 	mvn r7, #(0xff << 16)
@@ -1526,6 +1527,7 @@ Lforward:
 @ CHECK: mvn	r3, #7                  @ encoding: [0x07,0x30,0xe0,0xe3]
 @ CHECK: mvn	r3, #7                  @ encoding: [0x07,0x30,0xe0,0xe3]
 @ CHECK: mov	r3, #6                  @ encoding: [0x06,0x30,0xa0,0xe3]
+@ CHECK: mvn    r7, #255                @ encoding: [0xff,0x70,0xe0,0xe3]
 @ CHECK: mvn	r4, #4080               @ encoding: [0xff,0x4e,0xe0,0xe3]
 @ CHECK: mvn	r5, #16711680           @ encoding: [0xff,0x58,0xe0,0xe3]
 @ CHECK: mvn	r7, #16711680           @ encoding: [0xff,0x78,0xe0,0xe3]
diff --git a/test/MC/ARM/bracket-exprs.s b/test/MC/ARM/bracket-exprs.s
index 922bf7037019..74f3323cd2d5 100644
--- a/test/MC/ARM/bracket-exprs.s
+++ b/test/MC/ARM/bracket-exprs.s
@@ -1,7 +1,7 @@
 // RUN: llvm-mc -triple arm-unknown-linux %s | FileCheck %s
 
 // CHECK: .byte 1
-.if [~0 >> 1] == -1
+.if [~0 >> 63] == 1
 .byte 1
 .else
 .byte 2
diff --git a/test/MC/ARM/coff-debugging-secrel.ll b/test/MC/ARM/coff-debugging-secrel.ll
index 7323fc6828bb..1b8b7310171e 100644
--- a/test/MC/ARM/coff-debugging-secrel.ll
+++ b/test/MC/ARM/coff-debugging-secrel.ll
@@ -16,17 +16,17 @@ entry:
 !llvm.dbg.cu = !{!7}
 !llvm.module.flags = !{!9, !10}
 
-!0 = !MDLocation(line: 1, scope: !1)
-!1 = !{!"0x2e\00function\00function\00\001\000\001\000\006\000\000\001", !2, !3, !4, null, void ()* @function, null, null, !6} ; [ DW_TAG_subprogram ], [line 1], [def], [function]
-!2 = !{!"/Users/compnerd/work/llvm/test/MC/ARM/reduced.c", !"/Users/compnerd/work/llvm"}
-!3 = !{!"0x29", !2} ; [ DW_TAG_file_type] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c]
-!4 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ], [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocation(line: 1, scope: !1)
+!1 = !DISubprogram(name: "function", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !2, scope: !3, type: !4, function: void ()* @function, variables: !6)
+!2 = !DIFile(filename: "/Users/compnerd/work/llvm/test/MC/ARM/reduced.c", directory: "/Users/compnerd/work/llvm")
+!3 = !DIFile(filename: "/Users/compnerd/work/llvm/test/MC/ARM/reduced.c", directory: "/Users/compnerd/work/llvm")
+!4 = !DISubroutineType(types: !5)
 !5 = !{null}
 !6 = !{}
-!7 = !{!"0x11\0012\00clang version 3.5.0\000\00\000\00\001", !2, !6, !6, !8, !6, !6} ; [ DW_TAG_compile_unit ] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c] [DW_LANG_C99]
+!7 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0", isOptimized: false, emissionKind: 1, file: !2, enums: !6, retainedTypes: !6, subprograms: !8, globals: !6, imports: !6)
 !8 = !{!1}
 !9 = !{i32 2, !"Dwarf Version", i32 4}
-!10 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !{i32 1, !"Debug Info Version", i32 3}
 
 ; CHECK-ITANIUM: Relocations [
 ; CHECK-ITANIUM:   Section {{.*}} .debug_info {
diff --git a/test/MC/ARM/cpu-test.s b/test/MC/ARM/cpu-test.s
index 766e454d080a..7a6190758884 100644
--- a/test/MC/ARM/cpu-test.s
+++ b/test/MC/ARM/cpu-test.s
@@ -11,3 +11,7 @@ dsb
 dsb
 // CHECK-ERROR: error: Unknown CPU name
 .cpu foobar
+// CHECK: .cpu cortex-m3
+.cpu cortex-m3
+// CHECK: sub sp, #16
+sub sp,#16
diff --git a/test/MC/ARM/data-in-code.ll b/test/MC/ARM/data-in-code.ll
index 3bb017d7513f..c4910ff20e61 100644
--- a/test/MC/ARM/data-in-code.ll
+++ b/test/MC/ARM/data-in-code.ll
@@ -1,8 +1,8 @@
-;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort \
+;; RUN: llc -verify-machineinstrs \
 ;; RUN:   -mtriple=armv7-linux-gnueabi -filetype=obj %s -o - | \
 ;; RUN:   llvm-readobj -t | FileCheck -check-prefix=ARM %s
 
-;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort \
+;; RUN: llc -verify-machineinstrs \
 ;; RUN:   -mtriple=thumbv7-linux-gnueabi -filetype=obj %s -o - | \
 ;; RUN:   llvm-readobj -t | FileCheck -check-prefix=TMB %s
 
@@ -10,103 +10,26 @@
 ;; marking the data-in-code region.
 
 define void @foo(i32* %ptr) nounwind ssp {
-  %tmp = load i32* %ptr, align 4
-  switch i32 %tmp, label %default [
-    i32 11, label %bb0
-    i32 10, label %bb1
-    i32 8, label %bb2
-    i32 4, label %bb3
-    i32 2, label %bb4
-    i32 6, label %bb5
-    i32 9, label %bb6
-    i32 15, label %bb7
-    i32 1, label %bb8
-    i32 3, label %bb9
-    i32 5, label %bb10
-    i32 30, label %bb11
-    i32 31, label %bb12
-    i32 13, label %bb13
-    i32 14, label %bb14
-    i32 20, label %bb15
-    i32 19, label %bb16
-    i32 17, label %bb17
-    i32 18, label %bb18
-    i32 21, label %bb19
-    i32 22, label %bb20
-    i32 16, label %bb21
-    i32 24, label %bb22
-    i32 25, label %bb23
-    i32 26, label %bb24
-    i32 27, label %bb25
-    i32 28, label %bb26
-    i32 23, label %bb27
-    i32 12, label %bb28
+  %tmp = load i32, i32* %ptr, align 4
+  switch i32 %tmp, label %exit [
+    i32 0, label %bb0
+    i32 1, label %bb1
+    i32 2, label %bb2
+    i32 3, label %bb3
   ]
-
-default:
-  br label %exit
 bb0:
+  store i32 0, i32* %ptr, align 4
   br label %exit
 bb1:
+  store i32 1, i32* %ptr, align 4
   br label %exit
 bb2:
+  store i32 2, i32* %ptr, align 4
   br label %exit
 bb3:
+  store i32 3, i32* %ptr, align 4
   br label %exit
-bb4:
-  br label %exit
-bb5:
-  br label %exit
-bb6:
-  br label %exit
-bb7:
-  br label %exit
-bb8:
-  br label %exit
-bb9:
-  br label %exit
-bb10:
-  br label %exit
-bb11:
-  br label %exit
-bb12:
-  br label %exit
-bb13:
-  br label %exit
-bb14:
-  br label %exit
-bb15:
-  br label %exit
-bb16:
-  br label %exit
-bb17:
-  br label %exit
-bb18:
-  br label %exit
-bb19:
-  br label %exit
-bb20:
-  br label %exit
-bb21:
-  br label %exit
-bb22:
-  br label %exit
-bb23:
-  br label %exit
-bb24:
-  br label %exit
-bb25:
-  br label %exit
-bb26:
-  br label %exit
-bb27:
-  br label %exit
-bb28:
-  br label %exit
-
-
 exit:
-
   ret void
 }
 
diff --git a/test/MC/ARM/directive-arch-armv6k.s b/test/MC/ARM/directive-arch-armv6k.s
new file mode 100644
index 000000000000..ee433fa283e1
--- /dev/null
+++ b/test/MC/ARM/directive-arch-armv6k.s
@@ -0,0 +1,34 @@
+@ Test the .arch directive for armv6k
+
+@ This test case will check the default .ARM.attributes value for the
+@ armv6k architecture.
+
+@ RUN: llvm-mc -triple arm-eabi -filetype asm %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-ASM
+@ RUN: llvm-mc -triple arm-eabi -filetype obj %s \
+@ RUN:   | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
+
+	.syntax	unified
+	.arch	armv6k
+
+@ CHECK-ASM: 	.arch	armv6k
+
+@ CHECK-ATTR: FileAttributes {
+@ CHECK-ATTR:   Attribute {
+@ CHECK-ATTR:     TagName: CPU_name
+@ CHECK-ATTR:     Value: 6K
+@ CHECK-ATTR:   }
+@ CHECK-ATTR:   Attribute {
+@ CHECK-ATTR:     TagName: CPU_arch
+@ CHECK-ATTR:     Description: ARM v6K
+@ CHECK-ATTR:   }
+@ CHECK-ATTR:   Attribute {
+@ CHECK-ATTR:     TagName: ARM_ISA_use
+@ CHECK-ATTR:     Description: Permitted
+@ CHECK-ATTR:   }
+@ CHECK-ATTR:   Attribute {
+@ CHECK-ATTR:     TagName: THUMB_ISA_use
+@ CHECK-ATTR:     Description: Thumb-1
+@ CHECK-ATTR:   }
+@ CHECK-ATTR: }
+
diff --git a/test/MC/ARM/directive-fpu-diagnostics.s b/test/MC/ARM/directive-fpu-diagnostics.s
new file mode 100644
index 000000000000..67c612982219
--- /dev/null
+++ b/test/MC/ARM/directive-fpu-diagnostics.s
@@ -0,0 +1,10 @@
+@ RUN: not llvm-mc -triple armv7 -filetype asm -o /dev/null %s 2>&1 \
+@ RUN:     | FileCheck %s -strict-whitespace
+
+	.text
+	.thumb
+
+	.fpu invalid
+@ CHECK: error: Unknown FPU name
+@ CHECK: .fpu invalid
+@ CHECK:      ^
diff --git a/test/MC/ARM/dot-req.s b/test/MC/ARM/dot-req.s
index 3b4cf5c80c00..848c1241affd 100644
--- a/test/MC/ARM/dot-req.s
+++ b/test/MC/ARM/dot-req.s
@@ -1,6 +1,9 @@
 @ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s
         .syntax unified
 bar:
+@ The line is duplicated on purpose, it is legal to redefine a req with
+@ the same value.
+fred .req r5
 fred .req r5
         mov r11, fred
 .unreq fred
diff --git a/test/MC/ARM/dwarf-cfi-initial-state.s b/test/MC/ARM/dwarf-cfi-initial-state.s
index 0d1c08af7282..d3f7ce420f92 100644
--- a/test/MC/ARM/dwarf-cfi-initial-state.s
+++ b/test/MC/ARM/dwarf-cfi-initial-state.s
@@ -13,5 +13,8 @@ bx lr
 # When llvm-dwarfdump prints the full info for the DW_CFA_def_cfa
 # field, we can check that here too.
 # CHECK: DW_CFA_def_cfa:
+# The following 2 DW_CFA_nop instructions are "padding"
+# CHECK: DW_CFA_nop:
+# CHECK: DW_CFA_nop:
 # CHECK-NOT: DW_CFA
 # CHECK: FDE
diff --git a/test/MC/ARM/eh-compact-pr0.s b/test/MC/ARM/eh-compact-pr0.s
index 1d825bf3ddc1..9c0581a722e8 100644
--- a/test/MC/ARM/eh-compact-pr0.s
+++ b/test/MC/ARM/eh-compact-pr0.s
@@ -1,5 +1,7 @@
 @ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
-@ RUN:   | llvm-readobj -s -sd -sr | FileCheck %s
+@ RUN:   | llvm-readobj -s -sd -sr > %t
+@ RUN: FileCheck %s < %t
+@ RUN: FileCheck --check-prefix=RELOC %s < %t
 
 @ Check the compact pr0 model
 
@@ -63,10 +65,13 @@ func2:
 @ another relocation entry for __aeabi_unwind_cpp_pr0, so that the linker
 @ will keep __aeabi_unwind_cpp_pr0.
 @-------------------------------------------------------------------------------
-@ CHECK:     Relocations [
-@ CHECK:       0x0 R_ARM_PREL31 .TEST1 0x0
-@ CHECK:       0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
-@ CHECK:     ]
+@ RELOC:   Section {
+@ RELOC:     Name: .rel.ARM.exidx.TEST1
+@ RELOC:     Relocations [
+@ RELOC:       0x0 R_ARM_PREL31 .TEST1 0x0
+@ RELOC:       0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
+@ RELOC:     ]
+@ RELOC:   }
 
 
 @-------------------------------------------------------------------------------
@@ -92,13 +97,15 @@ func2:
 @ CHECK:       0000: 00000000 B0808480                    |........|
 @ CHECK:     )
 @ CHECK:   }
-@ CHECK: ]
 @-------------------------------------------------------------------------------
 @ The first word should be relocated to .TEST2 section.  Besides, there is
 @ another relocation entry for __aeabi_unwind_cpp_pr0, so that the linker
 @ will keep __aeabi_unwind_cpp_pr0.
 @-------------------------------------------------------------------------------
-@ CHECK:     Relocations [
-@ CHECK:       0x0 R_ARM_PREL31 .TEST2 0x0
-@ CHECK:       0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
-@ CHECK:     ]
+@ RELOC:   Section {
+@ RELOC:     Name: .rel.ARM.exidx.TEST2
+@ RELOC:     Relocations [
+@ RELOC:       0x0 R_ARM_PREL31 .TEST2 0x0
+@ RELOC:       0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
+@ RELOC:     ]
+@ RELOC:   }
diff --git a/test/MC/ARM/eh-directive-handlerdata.s b/test/MC/ARM/eh-directive-handlerdata.s
index 793d357bac76..980a5f056760 100644
--- a/test/MC/ARM/eh-directive-handlerdata.s
+++ b/test/MC/ARM/eh-directive-handlerdata.s
@@ -1,5 +1,7 @@
 @ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
-@ RUN:   | llvm-readobj -s -sd -sr | FileCheck %s
+@ RUN:   | llvm-readobj -s -sd -sr > %t
+@ RUN: FileCheck %s < %t
+@ RUN: FileCheck --check-prefix=RELOC %s < %t
 
 @ Check the .handlerdata directive (without .personality directive)
 
@@ -43,11 +45,14 @@ func1:
 @ We should see a relocation entry to __aeabi_unwind_cpp_pr0, so that the
 @ linker can keep __aeabi_unwind_cpp_pr0.
 @-------------------------------------------------------------------------------
-@ CHECK:  Relocations [
-@ CHECK:    0x0 R_ARM_PREL31 .TEST1 0x0
-@ CHECK:    0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
-@ CHECK:    0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
-@ CHECK:  ]
+@ RELOC: Section {
+@ RELOC:  Name: .rel.ARM.exidx.TEST1
+@ RELOC:  Relocations [
+@ RELOC:    0x0 R_ARM_PREL31 .TEST1 0x0
+@ RELOC:    0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
+@ RELOC:    0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
+@ RELOC:  ]
+@ RELOC: }
 
 
 
@@ -100,8 +105,11 @@ func2:
 @ We should see a relocation entry to __aeabi_unwind_cpp_pr0, so that the
 @ linker can keep __aeabi_unwind_cpp_pr0.
 @-------------------------------------------------------------------------------
-@ CHECK:  Relocations [
-@ CHECK:    0x0 R_ARM_PREL31 .TEST2 0x0
-@ CHECK:    0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0
-@ CHECK:    0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0
-@ CHECK:  ]
+@ RELOC: Section {
+@ RELOC:  Name: .rel.ARM.exidx.TEST2
+@ RELOC:  Relocations [
+@ RELOC:    0x0 R_ARM_PREL31 .TEST2 0x0
+@ RELOC:    0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0
+@ RELOC:    0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0
+@ RELOC:  ]
+@ RELOC: }
diff --git a/test/MC/ARM/eh-directive-personality.s b/test/MC/ARM/eh-directive-personality.s
index f49372295748..84e62bdfd68b 100644
--- a/test/MC/ARM/eh-directive-personality.s
+++ b/test/MC/ARM/eh-directive-personality.s
@@ -1,5 +1,7 @@
 @ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
-@ RUN:   | llvm-readobj -s -sd -sr | FileCheck %s
+@ RUN:   | llvm-readobj -s -sd -sr > %t
+@ RUN: FileCheck %s < %t
+@ RUN: FileCheck --check-prefix=RELOC %s < %t
 
 @ Check the .personality directive.
 
@@ -32,19 +34,28 @@ func1:
 @ CHECK:     0000: 00000000 B0B0B000                    |........|
 @ CHECK:   )
 @ CHECK: }
-@ CHECK:   Relocations [
-@ CHECK:     0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
-@ CHECK:   ]
+
+@ RELOC: Section {
+@ RELOC:   Name: .rel.ARM.extab.TEST1
+@ RELOC:   Relocations [
+@ RELOC:     0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
+@ RELOC:   ]
+@ RELOC: }
+
 @ CHECK: Section {
 @ CHECK:   Name: .ARM.exidx.TEST1
 @ CHECK:   SectionData (
 @ CHECK:     0000: 00000000 00000000                    |........|
 @ CHECK:   )
 @ CHECK: }
-@ CHECK:   Relocations [
-@ CHECK:     0x0 R_ARM_PREL31 .TEST1 0x0
-@ CHECK:     0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
-@ CHECK:   ]
+
+@ RELOC: Section {
+@ RELOC:   Name: .rel.ARM.exidx.TEST1
+@ RELOC:   Relocations [
+@ RELOC:     0x0 R_ARM_PREL31 .TEST1 0x0
+@ RELOC:     0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
+@ RELOC:   ]
+@ RELOC: }
 
 
 @-------------------------------------------------------------------------------
@@ -74,16 +85,25 @@ func2:
 @ CHECK:     0000: 00000000 B0B0B000                    |........|
 @ CHECK:   )
 @ CHECK: }
-@ CHECK:   Relocations [
-@ CHECK:     0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
-@ CHECK:   ]
+
+@ RELOC: Section {
+@ RELOC:   Name: .rel.ARM.extab.TEST2
+@ RELOC:   Relocations [
+@ RELOC:     0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
+@ RELOC:   ]
+@ RELOC: }
+
 @ CHECK: Section {
 @ CHECK:   Name: .ARM.exidx.TEST2
 @ CHECK:   SectionData (
 @ CHECK:     0000: 00000000 00000000                    |........|
 @ CHECK:   )
 @ CHECK: }
-@ CHECK:   Relocations [
-@ CHECK:     0x0 R_ARM_PREL31 .TEST2 0x0
-@ CHECK:     0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0
-@ CHECK:   ]
+
+@ RELOC: Section {
+@ RELOC:   Name: .rel.ARM.exidx.TEST2
+@ RELOC:   Relocations [
+@ RELOC:     0x0 R_ARM_PREL31 .TEST2 0x0
+@ RELOC:     0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0
+@ RELOC:   ]
+@ RELOC: }
diff --git a/test/MC/ARM/eh-directive-personalityindex.s b/test/MC/ARM/eh-directive-personalityindex.s
index 551722750933..6db942503c6d 100644
--- a/test/MC/ARM/eh-directive-personalityindex.s
+++ b/test/MC/ARM/eh-directive-personalityindex.s
@@ -1,5 +1,7 @@
 @ RUN: llvm-mc -triple armv7-linux-eabi -filetype obj -o - %s \
-@ RUN:   | llvm-readobj -s -sd -sr | FileCheck %s
+@ RUN:   | llvm-readobj -s -sd -sr > %t
+@ RUN: FileCheck %s < %t
+@ RUN: FileCheck --check-prefix=RELOC %s < %t
 
 	.syntax unified
 	.thumb
@@ -23,13 +25,13 @@ pr0:
 @ CHECK:   )
 @ CHECK: }
 
-@ CHECK: Section {
-@ CHECK:   Name: .rel.ARM.exidx.pr0
-@ CHECK:   Relocations [
-@ CHECK:     0x0 R_ARM_PREL31 .pr0 0x0
-@ CHECK:     0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
-@ CHECK:   ]
-@ CHECK: }
+@ RELOC: Section {
+@ RELOC:   Name: .rel.ARM.exidx.pr0
+@ RELOC:   Relocations [
+@ RELOC:     0x0 R_ARM_PREL31 .pr0 0x0
+@ RELOC:     0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
+@ RELOC:   ]
+@ RELOC: }
 
 	.section .pr0.nontrivial
 
@@ -52,13 +54,13 @@ pr0_nontrivial:
 @ CHECK:   )
 @ CHECK: }
 
-@ CHECK: Section {
-@ CHECK:   Name: .rel.ARM.exidx.pr0.nontrivial
-@ CHECK:   Relocations [
-@ CHECK:     0x0 R_ARM_PREL31 .pr0.nontrivial 0x0
-@ CHECK:     0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
-@ CHECK:   ]
-@ CHECK: }
+@ RELOC: Section {
+@ RELOC:   Name: .rel.ARM.exidx.pr0.nontrivial
+@ RELOC:   Relocations [
+@ RELOC:     0x0 R_ARM_PREL31 .pr0.nontrivial 0x0
+@ RELOC:     0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
+@ RELOC:   ]
+@ RELOC: }
 
 	.section .pr1
 
@@ -85,14 +87,14 @@ pr1:
 @ CHECK:   )
 @ CHECK: }
 
-@ CHECK: Section {
-@ CHECK:   Name: .rel.ARM.exidx.pr1
-@ CHECK:   Relocations [
-@ CHECK:     0x0 R_ARM_PREL31 .pr1 0x0
-@ CHECK:     0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0
-@ CHECK:     0x4 R_ARM_PREL31 .ARM.extab.pr1 0x0
-@ CHECK:   ]
-@ CHECK: }
+@ RELOC: Section {
+@ RELOC:   Name: .rel.ARM.exidx.pr1
+@ RELOC:   Relocations [
+@ RELOC:     0x0 R_ARM_PREL31 .pr1 0x0
+@ RELOC:     0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0
+@ RELOC:     0x4 R_ARM_PREL31 .ARM.extab.pr1 0x0
+@ RELOC:   ]
+@ RELOC: }
 
 	.section .pr1.nontrivial
 
@@ -122,14 +124,14 @@ pr1_nontrivial:
 @ CHECK:   )
 @ CHECK: }
 
-@ CHECK: Section {
-@ CHECK:   Name: .rel.ARM.exidx.pr1.nontrivial
-@ CHECK:   Relocations [
-@ CHECK:     0x0 R_ARM_PREL31 .pr1.nontrivial 0x0
-@ CHECK:     0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0
-@ CHECK:     0x4 R_ARM_PREL31 .ARM.extab.pr1.nontrivial 0x0
-@ CHECK:   ]
-@ CHECK: }
+@ RELOC: Section {
+@ RELOC:   Name: .rel.ARM.exidx.pr1.nontrivial
+@ RELOC:   Relocations [
+@ RELOC:     0x0 R_ARM_PREL31 .pr1.nontrivial 0x0
+@ RELOC:     0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0
+@ RELOC:     0x4 R_ARM_PREL31 .ARM.extab.pr1.nontrivial 0x0
+@ RELOC:   ]
+@ RELOC: }
 
 	.section .pr2
 
@@ -156,14 +158,14 @@ pr2:
 @ CHECK:   )
 @ CHECK: }
 
-@ CHECK: Section {
-@ CHECK:   Name: .rel.ARM.exidx.pr2
-@ CHECK:   Relocations [
-@ CHECK:     0x0 R_ARM_PREL31 .pr2 0x0
-@ CHECK:     0x0 R_ARM_NONE __aeabi_unwind_cpp_pr2 0x0
-@ CHECK:     0x4 R_ARM_PREL31 .ARM.extab.pr2 0x0
-@ CHECK:   ]
-@ CHECK: }
+@ RELOC: Section {
+@ RELOC:   Name: .rel.ARM.exidx.pr2
+@ RELOC:   Relocations [
+@ RELOC:     0x0 R_ARM_PREL31 .pr2 0x0
+@ RELOC:     0x0 R_ARM_NONE __aeabi_unwind_cpp_pr2 0x0
+@ RELOC:     0x4 R_ARM_PREL31 .ARM.extab.pr2 0x0
+@ RELOC:   ]
+@ RELOC: }
 
 	.section .pr2.nontrivial
 	.type pr2_nontrivial,%function
@@ -191,12 +193,11 @@ pr2_nontrivial:
 @ CHECK:   )
 @ CHECK: }
 
-@ CHECK: Section {
-@ CHECK:   Name: .rel.ARM.exidx.pr2.nontrivial
-@ CHECK:   Relocations [
-@ CHECK:     0x0 R_ARM_PREL31 .pr2.nontrivial 0x0
-@ CHECK:     0x0 R_ARM_NONE __aeabi_unwind_cpp_pr2 0x0
-@ CHECK:     0x4 R_ARM_PREL31 .ARM.extab.pr2.nontrivial 0x0
-@ CHECK:   ]
-@ CHECK: }
-
+@ RELOC: Section {
+@ RELOC:   Name: .rel.ARM.exidx.pr2.nontrivial
+@ RELOC:   Relocations [
+@ RELOC:     0x0 R_ARM_PREL31 .pr2.nontrivial 0x0
+@ RELOC:     0x0 R_ARM_NONE __aeabi_unwind_cpp_pr2 0x0
+@ RELOC:     0x4 R_ARM_PREL31 .ARM.extab.pr2.nontrivial 0x0
+@ RELOC:   ]
+@ RELOC: }
diff --git a/test/MC/ARM/eh-directive-section-comdat.s b/test/MC/ARM/eh-directive-section-comdat.s
index 296718f096ca..9c7160ea5e74 100644
--- a/test/MC/ARM/eh-directive-section-comdat.s
+++ b/test/MC/ARM/eh-directive-section-comdat.s
@@ -47,13 +47,15 @@ func1:
 @ CHECK:     Type: SHT_GROUP (0x11)
 @ CHECK:     Flags [ (0x0)
 @ CHECK:     ]
+@ CHECK:     Size: 24
 @ CHECK:     SectionData (
 @-------------------------------------------------------------------------------
-@ The second, third, and fourth word should correspond to the section index
-@ of .TEST1, .ARM.extab.TEST1, and .ARM.exidx.TEST1.
+@ These are the section indexes of .TEST1, .ARM.extab.TEST1, .ARM.exidx.TEST1,
+@ .rel.ARM.extab.TEST1, and .rel.ARM.exidx.TEST1.
 @-------------------------------------------------------------------------------
-@ CHECK:       0000: 01000000 05000000 06000000 08000000  |................|
-@ CHECK:     )
+@ CHECK-NEXT:     0000: 01000000 06000000 07000000 08000000
+@ CHECK-NEXT:     0010: 09000000 0A000000
+@ CHECK-NEXT:     )
 @ CHECK:   }
 
 
@@ -61,8 +63,8 @@ func1:
 @ Check the .TEST1 section
 @-------------------------------------------------------------------------------
 @ CHECK:   Section {
-@ CHECK:     Index: 5
-@ CHECK:     Name: .TEST1
+@ CHECK:     Index: 6
+@ CHECK-NEXT:     Name: .TEST1
 @ CHECK:     Type: SHT_PROGBITS (0x1)
 @-------------------------------------------------------------------------------
 @ The flags should contain SHF_GROUP.
@@ -79,8 +81,8 @@ func1:
 @ Check the .ARM.extab.TEST1 section
 @-------------------------------------------------------------------------------
 @ CHECK:   Section {
-@ CHECK:     Index: 6
-@ CHECK:     Name: .ARM.extab.TEST1
+@ CHECK:     Index: 7
+@ CHECK-NEXT:     Name: .ARM.extab.TEST1
 @ CHECK:     Type: SHT_PROGBITS (0x1)
 @-------------------------------------------------------------------------------
 @ The flags should contain SHF_GROUP.
@@ -91,13 +93,17 @@ func1:
 @ CHECK:     ]
 @ CHECK:   }
 
+@ CHECK:   Section {
+@ CHECK:     Index: 8
+@ CHECK-NEXT:     Name: .rel.ARM.extab.TEST1
+@ CHECK: }
 
 @-------------------------------------------------------------------------------
 @ Check the .ARM.exidx.TEST1 section
 @-------------------------------------------------------------------------------
 @ CHECK:   Section {
-@ CHECK:     Index: 8
-@ CHECK:     Name: .ARM.exidx.TEST1
+@ CHECK:     Index: 9
+@ CHECK-NEXT:     Name: .ARM.exidx.TEST1
 @ CHECK:     Type: SHT_ARM_EXIDX (0x70000001)
 @-------------------------------------------------------------------------------
 @ The flags should contain SHF_GROUP.
@@ -107,11 +113,16 @@ func1:
 @ CHECK:       SHF_GROUP (0x200)
 @ CHECK:       SHF_LINK_ORDER (0x80)
 @ CHECK:     ]
-@ CHECK:     Link: 5
+@ CHECK:     Link: 6
 @ CHECK:   }
-@ CHECK: ]
 
 
+@ CHECK:   Section {
+@ CHECK:     Index: 10
+@ CHECK-NEXT:     Name: .rel.ARM.exidx.TEST1
+@ CHECK: }
+
+@ CHECK: ]
 
 @-------------------------------------------------------------------------------
 @ Check symbol func1.  It should be weak binding, and belong to .TEST1 section.
@@ -121,6 +132,6 @@ func1:
 @ CHECK:     Name: func1
 @ CHECK:     Binding: Weak (0x2)
 @ CHECK:     Type: Function (0x2)
-@ CHECK:     Section: .TEST1 (0x5)
+@ CHECK:     Section: .TEST1
 @ CHECK:   }
 @ CHECK: ]
diff --git a/test/MC/ARM/eh-directive-section-multiple-func.s b/test/MC/ARM/eh-directive-section-multiple-func.s
index 9f632b8b89a6..e5307cf9190c 100644
--- a/test/MC/ARM/eh-directive-section-multiple-func.s
+++ b/test/MC/ARM/eh-directive-section-multiple-func.s
@@ -1,5 +1,7 @@
 @ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
-@ RUN:   | llvm-readobj -s -sd -sr -t | FileCheck %s
+@ RUN:   | llvm-readobj -s -sd -sr -t > %t
+@ RUN: FileCheck %s < %t
+@ RUN: FileCheck --check-prefix=RELOC %s < %t
 
 @ Check whether the section is switched back properly.
 
@@ -52,7 +54,8 @@ func2:
 @ Check the .TEST1 section.  There should be two "bx lr" instructions.
 @-------------------------------------------------------------------------------
 @ CHECK:   Section {
-@ CHECK:     Name: .TEST1
+@ CHECK:     Index: 5
+@ CHECK-NEXT:     Name: .TEST1
 @ CHECK:     SectionData (
 @ CHECK:       0000: 1EFF2FE1 1EFF2FE1                    |../.../.|
 @ CHECK:     )
@@ -69,10 +72,14 @@ func2:
 @ CHECK:       0000: 00000000 B0B0B000 00000000 B0B0B000  |................|
 @ CHECK:     )
 @ CHECK:   }
-@ CHECK:     Relocations [
-@ CHECK:       0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
-@ CHECK:       0x8 R_ARM_PREL31 __gxx_personality_v0 0x0
-@ CHECK:     ]
+
+@ RELOC:   Section {
+@ RELOC:     Name: .rel.ARM.extab.TEST1
+@ RELOC:     Relocations [
+@ RELOC:       0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
+@ RELOC:       0x8 R_ARM_PREL31 __gxx_personality_v0 0x0
+@ RELOC:     ]
+@ RELOC:   }
 
 
 @-------------------------------------------------------------------------------
@@ -80,7 +87,7 @@ func2:
 @-------------------------------------------------------------------------------
 @ CHECK:   Section {
 @ CHECK:     Name: .ARM.exidx.TEST1
-@ CHECK:     Link: 4
+@ CHECK:     Link: 5
 @-------------------------------------------------------------------------------
 @ The first word should be the offset to .TEST1.
 @ The second word should be the offset to .ARM.extab.TEST1
@@ -89,18 +96,21 @@ func2:
 @ CHECK:       0000: 00000000 00000000 04000000 08000000  |................|
 @ CHECK:     )
 @ CHECK:   }
-@ CHECK: ]
 @-------------------------------------------------------------------------------
 @ The first word of each entry should be relocated to .TEST1 section.
 @ The second word of each entry should be relocated to
 @ .ARM.extab.TESET1 section.
 @-------------------------------------------------------------------------------
-@ CHECK:     Relocations [
-@ CHECK:       0x0 R_ARM_PREL31 .TEST1 0x0
-@ CHECK:       0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
-@ CHECK:       0x8 R_ARM_PREL31 .TEST1 0x0
-@ CHECK:       0xC R_ARM_PREL31 .ARM.extab.TEST1 0x0
-@ CHECK:     ]
+
+@ RELOC:   Section {
+@ RELOC:     Name: .rel.ARM.exidx.TEST1
+@ RELOC:     Relocations [
+@ RELOC:       0x0 R_ARM_PREL31 .TEST1 0x0
+@ RELOC:       0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
+@ RELOC:       0x8 R_ARM_PREL31 .TEST1 0x0
+@ RELOC:       0xC R_ARM_PREL31 .ARM.extab.TEST1 0x0
+@ RELOC:     ]
+@ RELOC:   }
 
 
 @-------------------------------------------------------------------------------
@@ -114,7 +124,7 @@ func2:
 @ CHECK:     Binding: Global (0x1)
 @ CHECK:     Type: Function (0x2)
 @ CHECK:     Other: 0
-@ CHECK:     Section: .TEST1 (0x4)
+@ CHECK:     Section: .TEST1
 @ CHECK:   }
 @ CHECK:   Symbol {
 @ CHECK:     Name: func2
@@ -123,6 +133,6 @@ func2:
 @ CHECK:     Binding: Global (0x1)
 @ CHECK:     Type: Function (0x2)
 @ CHECK:     Other: 0
-@ CHECK:     Section: .TEST1 (0x4)
+@ CHECK:     Section: .TEST1
 @ CHECK:   }
 @ CHECK: ]
diff --git a/test/MC/ARM/eh-directive-section.s b/test/MC/ARM/eh-directive-section.s
index 7c1f32ee39d4..e36d9a99aaf5 100644
--- a/test/MC/ARM/eh-directive-section.s
+++ b/test/MC/ARM/eh-directive-section.s
@@ -1,5 +1,7 @@
 @ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
-@ RUN:   | llvm-readobj -s -sd -sr -t | FileCheck %s
+@ RUN:   | llvm-readobj -s -sd -sr -t > %t
+@ RUN: FileCheck %s < %t
+@ RUN: FileCheck --check-prefix=RELOC %s < %t
 
 @ Check the combination of .section, .fnstart, and .fnend directives.
 
@@ -48,8 +50,8 @@ func2:
 @-------------------------------------------------------------------------------
 @ CHECK: Sections [
 @ CHECK:   Section {
-@ CHECK:     Index: 4
-@ CHECK:     Name: .TEST1
+@ CHECK:     Index: 5
+@ CHECK-NEXT:     Name: .TEST1
 @ CHECK:     SectionData (
 @ CHECK:       0000: 1EFF2FE1                             |../.|
 @ CHECK:     )
@@ -64,9 +66,13 @@ func2:
 @ CHECK:       0000: 00000000 B0B0B000                    |........|
 @ CHECK:     )
 @ CHECK:   }
-@ CHECK:     Relocations [
-@ CHECK:       0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
-@ CHECK:     ]
+
+@ RELOC:   Section {
+@ RELOC:     Name: .rel.ARM.extab.TEST1
+@ RELOC:     Relocations [
+@ RELOC:       0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
+@ RELOC:     ]
+@ RELOC:   }
 
 
 @-------------------------------------------------------------------------------
@@ -78,7 +84,7 @@ func2:
 @-------------------------------------------------------------------------------
 @ This section should linked with .TEST1 section.
 @-------------------------------------------------------------------------------
-@ CHECK:     Link: 4
+@ CHECK:     Link: 5
 
 @-------------------------------------------------------------------------------
 @ The first word should be relocated to the code address in .TEST1 section.
@@ -89,18 +95,22 @@ func2:
 @ CHECK:       0000: 00000000 00000000                    |........|
 @ CHECK:     )
 @ CHECK:   }
-@ CHECK:     Relocations [
-@ CHECK:       0x0 R_ARM_PREL31 .TEST1 0x0
-@ CHECK:       0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
-@ CHECK:     ]
+
+@ RELOC:   Section {
+@ RELOC:     Name: .rel.ARM.exidx.TEST1
+@ RELOC:     Relocations [
+@ RELOC:       0x0 R_ARM_PREL31 .TEST1 0x0
+@ RELOC:       0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
+@ RELOC:     ]
+@ RELOC:   }
 
 
 @-------------------------------------------------------------------------------
 @ Check the TEST2 section (without the dot in the beginning)
 @-------------------------------------------------------------------------------
 @ CHECK:   Section {
-@ CHECK:     Index: 9
-@ CHECK:     Name: TEST2
+@ CHECK:     Index: 10
+@ CHECK-NEXT:     Name: TEST2
 @ CHECK:     SectionData (
 @ CHECK:       0000: 1EFF2FE1                             |../.|
 @ CHECK:     )
@@ -115,9 +125,13 @@ func2:
 @ CHECK:       0000: 00000000 B0B0B000                    |........|
 @ CHECK:     )
 @ CHECK:   }
-@ CHECK:     Relocations [
-@ CHECK:       0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
-@ CHECK:     ]
+
+@ RELOC:   Section {
+@ RELOC:     Name: .rel.ARM.extabTEST2
+@ RELOC:     Relocations [
+@ RELOC:       0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
+@ RELOC:     ]
+@ RELOC:   }
 
 
 @-------------------------------------------------------------------------------
@@ -129,7 +143,7 @@ func2:
 @-------------------------------------------------------------------------------
 @ This section should linked with TEST2 section.
 @-------------------------------------------------------------------------------
-@ CHECK:     Link: 9
+@ CHECK:     Link: 10
 
 @-------------------------------------------------------------------------------
 @ The first word should be relocated to the code address in TEST2 section.
@@ -140,11 +154,14 @@ func2:
 @ CHECK:       0000: 00000000 00000000                    |........|
 @ CHECK:     )
 @ CHECK:   }
-@ CHECK: ]
-@ CHECK:     Relocations [
-@ CHECK:       0x0 R_ARM_PREL31 TEST2 0x0
-@ CHECK:       0x4 R_ARM_PREL31 .ARM.extabTEST2 0x0
-@ CHECK:     ]
+
+@ RELOC:   Section {
+@ RELOC:     Name: .rel.ARM.exidxTEST2
+@ RELOC:     Relocations [
+@ RELOC:       0x0 R_ARM_PREL31 TEST2 0x0
+@ RELOC:       0x4 R_ARM_PREL31 .ARM.extabTEST2 0x0
+@ RELOC:     ]
+@ RELOC:   }
 
 
 
@@ -154,10 +171,10 @@ func2:
 @ CHECK: Symbols [
 @ CHECK:   Symbol {
 @ CHECK:     Name: func1
-@ CHECK:     Section: .TEST1 (0x4)
+@ CHECK:     Section: .TEST1
 @ CHECK:   }
 @ CHECK:   Symbol {
 @ CHECK:     Name: func2
-@ CHECK:     Section: TEST2 (0x9)
+@ CHECK:     Section: TEST2
 @ CHECK:   }
 @ CHECK: ]
diff --git a/test/MC/ARM/eh-directive-text-section-multiple-func.s b/test/MC/ARM/eh-directive-text-section-multiple-func.s
index 50e09f5f11b7..7ab401c5043a 100644
--- a/test/MC/ARM/eh-directive-text-section-multiple-func.s
+++ b/test/MC/ARM/eh-directive-text-section-multiple-func.s
@@ -72,10 +72,10 @@ func2:
 @ CHECK: Symbols [
 @ CHECK:   Symbol {
 @ CHECK:     Name: func1
-@ CHECK:     Section: .text (0x1)
+@ CHECK:     Section: .text
 @ CHECK:   }
 @ CHECK:   Symbol {
 @ CHECK:     Name: func2
-@ CHECK:     Section: .text (0x1)
+@ CHECK:     Section: .text
 @ CHECK:   }
 @ CHECK: ]
diff --git a/test/MC/ARM/eh-directive-text-section.s b/test/MC/ARM/eh-directive-text-section.s
index 4a073aa81151..32696d5a1dad 100644
--- a/test/MC/ARM/eh-directive-text-section.s
+++ b/test/MC/ARM/eh-directive-text-section.s
@@ -29,8 +29,8 @@ func1:
 @-------------------------------------------------------------------------------
 @ Check the index of .text section.  This will be used in .ARM.exidx.
 @-------------------------------------------------------------------------------
-@ CHECK:     Index: 1
-@ CHECK:     Name: .text
+@ CHECK:     Index: 2
+@ CHECK-NEXT:     Name: .text
 @ CHECK:     Type: SHT_PROGBITS (0x1)
 @ CHECK:     Flags [ (0x6)
 @ CHECK:       SHF_ALLOC (0x2)
@@ -58,7 +58,7 @@ func1:
 @ Check the linked section of the EXIDX section.  This should be the index
 @ of the .text section.
 @-------------------------------------------------------------------------------
-@ CHECK:     Link: 1
+@ CHECK:     Link: 2
 
 @-------------------------------------------------------------------------------
 @ The first word should be the offset to .text.  The second word should be
diff --git a/test/MC/ARM/eh-link.s b/test/MC/ARM/eh-link.s
new file mode 100644
index 000000000000..e14fb0638b91
--- /dev/null
+++ b/test/MC/ARM/eh-link.s
@@ -0,0 +1,90 @@
+@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
+@ RUN:   | llvm-readobj -s  | FileCheck %s
+
+@ Test that the ARM_EXIDX sections point (Link) to the corresponding text
+@ sections.
+
+@ FIXME: The section numbers are not important. If llvm-readobj printed the
+@ name first we could use a FileCheck variable.
+
+@ CHECK:      Section {
+@ CHECK:        Index: 6
+@ CHECK-NEXT:   Name: .text
+@ CHECK-NEXT:   Type: SHT_PROGBITS
+@ CHECK-NEXT:   Flags [
+@ CHECK-NEXT:     SHF_ALLOC
+@ CHECK-NEXT:     SHF_EXECINSTR
+@ CHECK-NEXT:     SHF_GROUP
+@ CHECK-NEXT:   ]
+@ CHECK-NEXT:   Address: 0x0
+@ CHECK-NEXT:   Offset:
+@ CHECK-NEXT:   Size: 4
+@ CHECK-NEXT:   Link: 0
+@ CHECK-NEXT:   Info: 0
+@ CHECK-NEXT:   AddressAlignment: 1
+@ CHECK-NEXT:   EntrySize: 0
+@ CHECK-NEXT: }
+@ CHECK-NEXT: Section {
+@ CHECK-NEXT:   Index: 7
+@ CHECK-NEXT:   Name: .ARM.exidx
+@ CHECK-NEXT:   Type: SHT_ARM_EXIDX
+@ CHECK-NEXT:   Flags [
+@ CHECK-NEXT:     SHF_ALLOC
+@ CHECK-NEXT:     SHF_GROUP
+@ CHECK-NEXT:     SHF_LINK_ORDER
+@ CHECK-NEXT:   ]
+@ CHECK-NEXT:   Address: 0x0
+@ CHECK-NEXT:   Offset:
+@ CHECK-NEXT:   Size: 8
+@ CHECK-NEXT:   Link: 6
+@ CHECK-NEXT:   Info: 0
+@ CHECK-NEXT:   AddressAlignment: 4
+@ CHECK-NEXT:   EntrySize: 0
+@ CHECK-NEXT: }
+
+@ CHECK:      Section {
+@ CHECK:        Index: 10
+@ CHECK-NEXT:   Name: .text
+@ CHECK-NEXT:   Type: SHT_PROGBITS
+@ CHECK-NEXT:   Flags [
+@ CHECK-NEXT:     SHF_ALLOC
+@ CHECK-NEXT:     SHF_EXECINSTR
+@ CHECK-NEXT:     SHF_GROUP
+@ CHECK-NEXT:   ]
+@ CHECK-NEXT:   Address: 0x0
+@ CHECK-NEXT:   Offset:
+@ CHECK-NEXT:   Size: 4
+@ CHECK-NEXT:   Link: 0
+@ CHECK-NEXT:   Info: 0
+@ CHECK-NEXT:   AddressAlignment: 1
+@ CHECK-NEXT:   EntrySize: 0
+@ CHECK-NEXT: }
+@ CHECK-NEXT: Section {
+@ CHECK-NEXT:   Index: 11
+@ CHECK-NEXT:   Name: .ARM.exidx
+@ CHECK-NEXT:   Type: SHT_ARM_EXIDX
+@ CHECK-NEXT:   Flags [
+@ CHECK-NEXT:     SHF_ALLOC
+@ CHECK-NEXT:     SHF_GROUP
+@ CHECK-NEXT:     SHF_LINK_ORDER
+@ CHECK-NEXT:   ]
+@ CHECK-NEXT:   Address: 0x0
+@ CHECK-NEXT:   Offset:
+@ CHECK-NEXT:   Size: 8
+@ CHECK-NEXT:   Link: 10
+@ CHECK-NEXT:   Info: 0
+@ CHECK-NEXT:   AddressAlignment: 4
+@ CHECK-NEXT:   EntrySize: 0
+@ CHECK-NEXT: }
+
+	.section	.text,"axG",%progbits,f,comdat
+f:
+	.fnstart
+	mov	pc, lr
+	.fnend
+
+	.section	.text,"axG",%progbits,g,comdat
+g:
+	.fnstart
+	mov	pc, lr
+	.fnend
diff --git a/test/MC/ARM/elf-movt.s b/test/MC/ARM/elf-movt.s
index 0080db4ac8a0..0fd77754795b 100644
--- a/test/MC/ARM/elf-movt.s
+++ b/test/MC/ARM/elf-movt.s
@@ -35,17 +35,17 @@ barf:                                   @ @barf
 @ OBJ-NEXT:       0000: F00F0FE3 F40F4FE3
 @ OBJ-NEXT:     )
 @ OBJ-NEXT:   }
-@ OBJ-NEXT:   Section {
-@ OBJ-NEXT:     Index: 2
-@ OBJ-NEXT:     Name: .rel.text (1)
+@ OBJ:        Section {
+@ OBJ:          Index:
+@ OBJ:          Name: .rel.text
 @ OBJ-NEXT:     Type: SHT_REL (0x9)
 @ OBJ-NEXT:     Flags [ (0x0)
 @ OBJ-NEXT:     ]
 @ OBJ-NEXT:     Address: 0x0
-@ OBJ-NEXT:     Offset: 0x22C
+@ OBJ-NEXT:     Offset:
 @ OBJ-NEXT:     Size: 16
-@ OBJ-NEXT:     Link: 6
-@ OBJ-NEXT:     Info: 1
+@ OBJ-NEXT:     Link:
+@ OBJ-NEXT:     Info:
 @ OBJ-NEXT:     AddressAlignment: 4
 @ OBJ-NEXT:     EntrySize: 8
 @ OBJ-NEXT:     Relocations [
diff --git a/test/MC/ARM/elf-reloc-01.ll b/test/MC/ARM/elf-reloc-01.ll
index 28be85b7db12..7f3cc185af1c 100644
--- a/test/MC/ARM/elf-reloc-01.ll
+++ b/test/MC/ARM/elf-reloc-01.ll
@@ -61,7 +61,7 @@ bb3:                                              ; preds = %bb, %entry
 declare void @exit(i32) noreturn nounwind
 
 ; OBJ: Relocations [
-; OBJ:   Section (2) .rel.text {
+; OBJ:   Section {{.*}} .rel.text {
 ; OBJ:     0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC _MergedGlobals
 ; OBJ:   }
 ; OBJ: ]
diff --git a/test/MC/ARM/elf-reloc-02.ll b/test/MC/ARM/elf-reloc-02.ll
index 7eb49cc5510f..0ffb6237d61a 100644
--- a/test/MC/ARM/elf-reloc-02.ll
+++ b/test/MC/ARM/elf-reloc-02.ll
@@ -29,10 +29,10 @@ declare void @myhextochar(i32 %n, i8* nocapture %buffer) nounwind
 
 define i32 @main() nounwind {
 entry:
-  %0 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), i32 6) nounwind
-  %1 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([8 x i8]* @.str1, i32 0, i32 0), i32 7) nounwind
-  %2 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([13 x i8]* @.str2, i32 0, i32 0), i32 12) nounwind
-  %3 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([7 x i8]* @.str3, i32 0, i32 0), i32 6) nounwind
+  %0 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 6) nounwind
+  %1 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str1, i32 0, i32 0), i32 7) nounwind
+  %2 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str2, i32 0, i32 0), i32 12) nounwind
+  %3 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str3, i32 0, i32 0), i32 6) nounwind
   tail call void @exit(i32 55) noreturn nounwind
   unreachable
 }
@@ -42,7 +42,7 @@ declare i32 @write(...)
 declare void @exit(i32) noreturn nounwind
 
 ;; OBJ:      Relocations [
-;; OBJ:        Section (2) .rel.text {
+;; OBJ:        Section {{.*}} .rel.text {
 ;; OBJ-NEXT:     0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC .L.str
 ;; OBJ:        }
 ;; OBJ:      ]
diff --git a/test/MC/ARM/elf-reloc-03.ll b/test/MC/ARM/elf-reloc-03.ll
index ee5e59eb340c..4beb91f193f6 100644
--- a/test/MC/ARM/elf-reloc-03.ll
+++ b/test/MC/ARM/elf-reloc-03.ll
@@ -78,10 +78,10 @@ entry:
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @startval, align 4
-  %1 = getelementptr inbounds [10 x i32 (...)*]* @vtable, i32 0, i32 %0
-  %2 = load i32 (...)** %1, align 4
-  %3 = tail call i32 (...)* %2() nounwind
+  %0 = load i32, i32* @startval, align 4
+  %1 = getelementptr inbounds [10 x i32 (...)*], [10 x i32 (...)*]* @vtable, i32 0, i32 %0
+  %2 = load i32 (...)*, i32 (...)** %1, align 4
+  %3 = tail call i32 (...) %2() nounwind
   tail call void @exit(i32 %3) noreturn nounwind
   unreachable
 }
@@ -89,7 +89,7 @@ entry:
 declare void @exit(i32) noreturn nounwind
 
 ;; OBJ: Relocations [
-;; OBJ:   Section (2) .rel.text {
+;; OBJ:   Section {{.*}} .rel.text {
 ;; OBJ:     0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC vtable
 ;; OBJ:   }
 ;; OBJ: ]
diff --git a/test/MC/ARM/elf-reloc-condcall.s b/test/MC/ARM/elf-reloc-condcall.s
index a0402bdc3814..c4818b89c23d 100644
--- a/test/MC/ARM/elf-reloc-condcall.s
+++ b/test/MC/ARM/elf-reloc-condcall.s
@@ -8,7 +8,7 @@
         b some_label
 
 // OBJ:      Relocations [
-// OBJ-NEXT:   Section (2) .rel.text {
+// OBJ-NEXT:   Section {{.*}} .rel.text {
 // OBJ-NEXT:     0x0  R_ARM_JUMP24 some_label 0x0
 // OBJ-NEXT:     0x4  R_ARM_CALL   some_label 0x0
 // OBJ-NEXT:     0x8  R_ARM_CALL   some_label 0x0
diff --git a/test/MC/ARM/elf-thumbfunc-reloc.ll b/test/MC/ARM/elf-thumbfunc-reloc.ll
index f502739a2afd..52579581875e 100644
--- a/test/MC/ARM/elf-thumbfunc-reloc.ll
+++ b/test/MC/ARM/elf-thumbfunc-reloc.ll
@@ -24,15 +24,15 @@ entry:
 ; make sure that bl 0 <foo> (fff7feff) is correctly encoded
 ; CHECK: Sections [
 ; CHECK:   SectionData (
-; CHECK:     0000: 704700BF 2DE90048 FFF7FEFF BDE80088
+; CHECK:     0000: 704780B5 FFF7FEFF 80BD
 ; CHECK:   )
 ; CHECK: ]
 
 ; CHECK:      Relocations [
-; CHECK-NEXT:   Section (2) .rel.text {
-; CHECK-NEXT:     0x8 R_ARM_THM_CALL foo 0x0
+; CHECK-NEXT:   Section {{.*}} .rel.text {
+; CHECK-NEXT:     0x4 R_ARM_THM_CALL foo 0x0
 ; CHECK-NEXT:   }
-; CHECK-NEXT:   Section (7) .rel.ARM.exidx {
+; CHECK-NEXT:   Section {{.*}} .rel.ARM.exidx {
 ; CHECK-NEXT:     0x0 R_ARM_PREL31 .text 0x0
 ; CHECK-NEXT:     0x8 R_ARM_PREL31 .text 0x0
 ; CHECK-NEXT:   }
diff --git a/test/MC/ARM/elf-thumbfunc-reloc.s b/test/MC/ARM/elf-thumbfunc-reloc.s
index ea7d507a7e83..70aa8c66b96a 100644
--- a/test/MC/ARM/elf-thumbfunc-reloc.s
+++ b/test/MC/ARM/elf-thumbfunc-reloc.s
@@ -22,14 +22,14 @@ ptr:
 
 @@ make sure an R_ARM_THM_CALL relocation is generated for the call to g
 @CHECK:      Relocations [
-@CHECK-NEXT:   Section (2) .rel.text {
+@CHECK-NEXT:   Section {{.*}} .rel.text {
 @CHECK-NEXT:     0x4 R_ARM_THM_CALL g 0x0
 @CHECK-NEXT:   }
 
 
 @@ make sure the relocation is with f. That is one way to make sure it includes
 @@ the thumb bit.
-@CHECK-NEXT:   Section (6) .rel.data.rel.local {
+@CHECK-NEXT:   Section ({{.*}}) .rel.data.rel.local {
 @CHECK-NEXT:     0x0 R_ARM_ABS32 f 0x0
 @CHECK-NEXT:   }
 @CHECK-NEXT: ]
diff --git a/test/MC/ARM/inst-directive-emit.s b/test/MC/ARM/inst-directive-emit.s
index 13b7edfa1f3a..63fdd15ee388 100644
--- a/test/MC/ARM/inst-directive-emit.s
+++ b/test/MC/ARM/inst-directive-emit.s
@@ -15,6 +15,6 @@ emit_asm:
 @ CHECK: 	.globl	emit_asm
 @ CHECK: 	.type	emit_asm,%function
 @ CHECK: emit_asm:
-@ CHECK: 	inst.w 0xF2400000
-@ CHECK: 	inst.w 0xF2C00000
+@ CHECK: 	inst.w 0xf2400000
+@ CHECK: 	inst.w 0xf2c00000
 
diff --git a/test/MC/ARM/thumb-diagnostics.s b/test/MC/ARM/thumb-diagnostics.s
index bd26d06865ca..5dcac90a901b 100644
--- a/test/MC/ARM/thumb-diagnostics.s
+++ b/test/MC/ARM/thumb-diagnostics.s
@@ -235,13 +235,17 @@ error: invalid operand for instruction
 @ CHECK-ERRORS: error: branch target out of range
 
 @------------------------------------------------------------------------------
-@ WFE/WFI/YIELD - are not supported pre v6T2
+@ SEV/WFE/WFI/YIELD - are not supported pre v6M or v6T2
 @------------------------------------------------------------------------------
+        sev
         wfe
         wfi
         yield
 
 @ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2
+@ CHECK-ERRORS: sev
+@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2
 @ CHECK-ERRORS: wfe
 @ CHECK-ERRORS: ^
 @ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2
diff --git a/test/MC/ARM/thumb1-relax-adr.s b/test/MC/ARM/thumb1-relax-adr.s
new file mode 100644
index 000000000000..80b93ec8eae1
--- /dev/null
+++ b/test/MC/ARM/thumb1-relax-adr.s
@@ -0,0 +1,9 @@
+@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1  | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: not llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+
+        .global func1
+_func1:
+        adr r0, _func2
+@ CHECK-ERROR: unsupported relocation on symbol
+
diff --git a/test/MC/ARM/thumb1-relax-bcc.s b/test/MC/ARM/thumb1-relax-bcc.s
new file mode 100644
index 000000000000..02fde2e040ea
--- /dev/null
+++ b/test/MC/ARM/thumb1-relax-bcc.s
@@ -0,0 +1,12 @@
+@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o %t %s
+@ RUN:    llvm-objdump -d -r -triple thumbv7m-none-eabi %t | FileCheck --check-prefix=CHECK-ELF %s
+
+        .global func1
+_func1:
+        bne _func2
+@ CHECK-ERROR: unsupported relocation on symbol
+
+@ CHECK-ELF: 7f f4 fe af        bne.w #-4
+@ CHECK-ELF-NEXT: R_ARM_THM_JUMP24 _func2
diff --git a/test/MC/ARM/thumb1-relax-br.s b/test/MC/ARM/thumb1-relax-br.s
new file mode 100644
index 000000000000..92a827527388
--- /dev/null
+++ b/test/MC/ARM/thumb1-relax-br.s
@@ -0,0 +1,19 @@
+@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: llvm-mc -triple thumbv7m-none-macho -filetype=obj -o %t %s
+@ RUN:    llvm-objdump -d -r -triple thumbv7m-none-macho %t | FileCheck --check-prefix=CHECK-MACHO %s
+@ RUN: llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o %t %s
+@ RUN:    llvm-objdump -d -r -triple thumbv7m-none-eabi %t | FileCheck --check-prefix=CHECK-ELF %s
+
+        .global func1
+_func1:
+        @ There is no MachO relocation for Thumb1's unconditional branch, so
+        @ this is unrepresentable. FIXME: I think ELF could represent this.
+        b _func2
+
+@ CHECK-ERROR: unsupported relocation on symbol
+
+@ CHECK-MACHO: ff f7 fe bf        b.w #-4
+@ CHECK-MACHO-NEXT: ARM_THUMB_RELOC_BR22
+
+@ CHECK-ELF: ff f7 fe bf        b.w #-4
+@ CHECK-ELF-NEXT: R_ARM_THM_JUMP24 _func2
diff --git a/test/MC/ARM/thumb1-relax-ldrlit.s b/test/MC/ARM/thumb1-relax-ldrlit.s
new file mode 100644
index 000000000000..96c5aa036f28
--- /dev/null
+++ b/test/MC/ARM/thumb1-relax-ldrlit.s
@@ -0,0 +1,9 @@
+@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: not llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+
+        .global func1
+_func1:
+        ldr r0, _func2
+@ CHECK-ERROR: unsupported relocation on symbol
+
diff --git a/test/MC/ARM/thumb2-bxj-v8.s b/test/MC/ARM/thumb2-bxj-v8.s
new file mode 100644
index 000000000000..4420b6f15c15
--- /dev/null
+++ b/test/MC/ARM/thumb2-bxj-v8.s
@@ -0,0 +1,11 @@
+@ RUN: not llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
+@ RUN: not llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s 2>&1  | FileCheck %s --check-prefix=UNDEF
+@ RUN: not llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s 2>&1  | FileCheck %s --check-prefix=UNDEF
+@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1  | FileCheck %s --check-prefix=ARM_MODE
+@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s 2>&1  | FileCheck %s
+
+bxj r13
+
+@ CHECK: bxj	sp                      @ encoding: [0xcd,0xf3,0x00,0x8f]
+@ UNDEF:  error: r13 (SP) is an unpredictable operand to BXJ
+@ ARM_MODE: error: instruction requires: arm-mode
diff --git a/test/MC/ARM/thumb2-bxj.s b/test/MC/ARM/thumb2-bxj.s
index e60d1a447cba..76879399ed87 100644
--- a/test/MC/ARM/thumb2-bxj.s
+++ b/test/MC/ARM/thumb2-bxj.s
@@ -1,8 +1,8 @@
 @ RUN: llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s | FileCheck %s
 @ RUN: llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s | FileCheck %s
 @ RUN: llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s | FileCheck %s
 @ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
-@ RUN: not llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
 
         bxj r2
 
diff --git a/test/MC/ARM/thumb2-diagnostics.s b/test/MC/ARM/thumb2-diagnostics.s
index b2b14bc13d6a..8fd161c2cc53 100644
--- a/test/MC/ARM/thumb2-diagnostics.s
+++ b/test/MC/ARM/thumb2-diagnostics.s
@@ -87,4 +87,7 @@ foo2:
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: invalid operand for instruction
 
-
+ssat r0, #1, r0, asr #32
+usat r0, #1, r0, asr #32
+@ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode
+@ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode
diff --git a/test/MC/ARM/thumb2-dsp-diag.s b/test/MC/ARM/thumb2-dsp-diag.s
new file mode 100644
index 000000000000..a87c2120d5ad
--- /dev/null
+++ b/test/MC/ARM/thumb2-dsp-diag.s
@@ -0,0 +1,34 @@
+@ RUN: not llvm-mc -triple=thumbv7m 2>&1 < %s | FileCheck --check-prefix=CHECK-ERRORS %s
+@ RUN: llvm-mc -triple=thumbv7em -show-encoding < %s | FileCheck --check-prefix=CHECK-7EM %s
+
+sxtab r0, r0, r0
+sxtah r0, r0, r0
+sxtab16 r0, r0, r0
+sxtb16 r0, r0
+sxtb16 r0, r0, ror #8
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-7EM: sxtab	r0, r0, r0              @ encoding: [0x40,0xfa,0x80,0xf0]
+@ CHECK-7EM: sxtah	r0, r0, r0              @ encoding: [0x00,0xfa,0x80,0xf0]
+@ CHECK-7EM: sxtab16	r0, r0, r0              @ encoding: [0x20,0xfa,0x80,0xf0]
+@ CHECK-7EM: sxtb16	r0, r0                  @ encoding: [0x2f,0xfa,0x80,0xf0]
+@ CHECK-7EM: sxtb16	r0, r0, ror #8          @ encoding: [0x2f,0xfa,0x90,0xf0]
+
+uxtab r0, r0, r0
+uxtah r0, r0, r0
+uxtab16 r0, r0, r0
+uxtb16 r0, r0
+uxtb16 r0, r0, ror #8
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-7EM: uxtab	r0, r0, r0              @ encoding: [0x50,0xfa,0x80,0xf0]
+@ CHECK-7EM: uxtah	r0, r0, r0              @ encoding: [0x10,0xfa,0x80,0xf0]
+@ CHECK-7EM: uxtab16	r0, r0, r0              @ encoding: [0x30,0xfa,0x80,0xf0]
+@ CHECK-7EM: uxtb16	r0, r0                  @ encoding: [0x3f,0xfa,0x80,0xf0]
+@ CHECK-7EM: uxtb16	r0, r0, ror #8          @ encoding: [0x3f,0xfa,0x90,0xf0]
diff --git a/test/MC/AsmParser/at-pseudo-variable-bad.s b/test/MC/AsmParser/at-pseudo-variable-bad.s
new file mode 100644
index 000000000000..885f18b2d4f4
--- /dev/null
+++ b/test/MC/AsmParser/at-pseudo-variable-bad.s
@@ -0,0 +1,23 @@
+# RUN: not llvm-mc -triple i386-unknown-unknown < %s 2>&1 | FileCheck %s
+
+add  $1\@, %eax
+# CHECK: :[[@LINE-1]]:8: error: unexpected token in argument list
+
+.macro A @
+  mov  %eax, %eax
+.endm
+# CHECK: :[[@LINE-3]]:11: error: expected identifier in '.macro' directive
+
+.rept 2
+  addi $8, $8, \@
+.endr
+# CHECK: error: unknown token in expression
+# CHECK: :[[@LINE-4]]:1: note: while in macro instantiation
+# CHECK-NEXT: .rept 2
+
+.rep 3
+  addi $9, $9, \@
+.endr
+# CHECK: error: unknown token in expression
+# CHECK: :[[@LINE-4]]:1: note: while in macro instantiation
+# CHECK-NEXT: .rep 3
diff --git a/test/MC/AsmParser/at-pseudo-variable.s b/test/MC/AsmParser/at-pseudo-variable.s
new file mode 100644
index 000000000000..b0966e137170
--- /dev/null
+++ b/test/MC/AsmParser/at-pseudo-variable.s
@@ -0,0 +1,64 @@
+# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s
+
+.macro A
+  add  $1\@, %eax
+.endm
+
+.macro B
+  sub  $1\@, %eax
+.endm
+
+  A
+# CHECK: addl  $10, %eax
+  A
+# CHECK: addl  $11, %eax
+  B
+# CHECK: subl  $12, %eax
+  B
+# CHECK: subl  $13, %eax
+
+# The following uses of \@ are undocumented, but valid:
+.irpc foo,234
+  add  $\foo\@, %eax
+.endr
+# CHECK: addl  $24, %eax
+# CHECK: addl  $34, %eax
+# CHECK: addl  $44, %eax
+
+.irp reg,%eax,%ebx
+  sub  $2\@, \reg
+.endr
+# CHECK: subl  $24, %eax
+# CHECK: subl  $24, %ebx
+
+# Test that .irp(c) and .rep(t) do not increase \@.
+# Only the use of A should increase \@, so we can test that it increases by 1
+# each time.
+
+.irpc foo,123
+  sub  $\foo, %eax
+.endr
+
+  A
+# CHECK: addl  $14, %eax
+
+.irp reg,%eax,%ebx
+  sub  $4, \reg
+.endr
+
+  A
+# CHECK: addl  $15, %eax
+
+.rept 2
+  sub  $5, %eax
+.endr
+
+  A
+# CHECK: addl  $16, %eax
+
+.rep 3
+  sub  $6, %eax
+.endr
+
+  A
+# CHECK: addl  $17, %eax
diff --git a/test/MC/AsmParser/expr-shr.s b/test/MC/AsmParser/expr-shr.s
new file mode 100644
index 000000000000..fc117b64e95a
--- /dev/null
+++ b/test/MC/AsmParser/expr-shr.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown-elf %s | FileCheck %s --check-prefix=CHECK
+// RUN: llvm-mc -triple x86_64-pc-windows-msvc %s | FileCheck %s --check-prefix=MSVC
+// RUN: llvm-mc -triple x86_64-unknown-darwin %s | FileCheck %s --check-prefix=DARWIN
+
+.data
+
+// CHECK: .quad 3
+
+// Both COFF and Darwin still use AShr.
+// MSVC: .quad -1
+// DARWIN: .quad -1
+
+.quad (~0 >> 62)
diff --git a/test/MC/AsmParser/ifeqs-diagnostics.s b/test/MC/AsmParser/ifeqs-diagnostics.s
index 1e5e8c3751f6..dcc43ff052e7 100644
--- a/test/MC/AsmParser/ifeqs-diagnostics.s
+++ b/test/MC/AsmParser/ifeqs-diagnostics.s
@@ -20,3 +20,20 @@
 
 // CHECK-NOT: error: unmatched .ifs or .elses
 
+.ifnes
+
+// CHECK: error: expected string parameter for '.ifnes' directive
+// CHECK: .ifnes
+// CHECK:       ^
+
+.ifnes "string1"
+
+// CHECK: error: expected comma after first string for '.ifnes' directive
+// CHECK: .ifnes "string1"
+// CHECK:                 ^
+
+.ifnes "string1",
+
+// CHECK: error: expected string parameter for '.ifnes' directive
+// CHECK: .ifnes "string1",
+// CHECK:                  ^
diff --git a/test/MC/AsmParser/ifnes.s b/test/MC/AsmParser/ifnes.s
new file mode 100644
index 000000000000..7a3cbe0264e1
--- /dev/null
+++ b/test/MC/AsmParser/ifnes.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s
+
+# CHECK-NOT: .byte 0
+# CHECK: .byte 1
+.ifnes "foo space", "foo space"
+	.byte 0
+.else
+	.byte 1
+.endif
+
+# CHECK-NOT: .byte 0
+# CHECK: .byte 1
+.ifnes "unequal", "unEqual"
+	.byte 1
+.else
+	.byte 0
+.endif
+
+# CHECK-NOT: .byte 0
+# CHECK: .byte 1
+.ifnes "equal", "equal" ; .byte 0 ; .else ; .byte 1 ; .endif
+
diff --git a/test/MC/AsmParser/rename.s b/test/MC/AsmParser/rename.s
index 934cee808bd9..c794d8bdfa3e 100644
--- a/test/MC/AsmParser/rename.s
+++ b/test/MC/AsmParser/rename.s
@@ -10,5 +10,5 @@
 // CHECK: .size  bar, .Ltmp0-bar
 // CHECK: .Ltmp01
 // CHECK: .size foo, .Ltmp01-foo
-// CHECK: .Ltmp02
-// CHECK: .size qux, .Ltmp02-qux
+// CHECK: .Ltmp00
+// CHECK: .size qux, .Ltmp00-qux
diff --git a/test/MC/AsmParser/section.s b/test/MC/AsmParser/section.s
index 0c3828d714a7..2ef545b822cc 100644
--- a/test/MC/AsmParser/section.s
+++ b/test/MC/AsmParser/section.s
@@ -48,7 +48,7 @@
 
 # CHECK:      Sections [
 # CHECK:        Section {
-# CHECK:          Name: test1 (68)
+# CHECK:          Name: test1
 # CHECK-NEXT:     Type: SHT_PROGBITS
 # CHECK-NEXT:     Flags [ (0x0)
 # CHECK-NEXT:     ]
@@ -64,7 +64,7 @@
 # CHECK-NEXT:     )
 # CHECK-NEXT:   }
 # CHECK:        Section {
-# CHECK:          Name: test2 (62)
+# CHECK:          Name: test2
 # CHECK-NEXT:     Type: SHT_PROGBITS
 # CHECK-NEXT:     Flags [ (0x0)
 # CHECK-NEXT:     ]
@@ -80,7 +80,7 @@
 # CHECK-NEXT:     )
 # CHECK-NEXT:   }
 # CHECK:        Section {
-# CHECK:          Name: test3 (56)
+# CHECK:          Name: test3
 # CHECK-NEXT:     Type: SHT_PROGBITS
 # CHECK-NEXT:     Flags [ (0x0)
 # CHECK-NEXT:     ]
@@ -96,7 +96,7 @@
 # CHECK-NEXT:     )
 # CHECK-NEXT:   }
 # CHECK:        Section {
-# CHECK:          Name: test4 (50)
+# CHECK:          Name: test4
 # CHECK-NEXT:     Type: SHT_PROGBITS
 # CHECK-NEXT:     Flags [ (0x0)
 # CHECK-NEXT:     ]
@@ -112,7 +112,7 @@
 # CHECK-NEXT:     )
 # CHECK-NEXT:   }
 # CHECK:        Section {
-# CHECK:          Name: test5 (44)
+# CHECK:          Name: test5
 # CHECK-NEXT:     Type: SHT_PROGBITS
 # CHECK-NEXT:     Flags [ (0x0)
 # CHECK-NEXT:     ]
diff --git a/test/MC/COFF/bss_section.ll b/test/MC/COFF/bss_section.ll
index 477b3dfbd3a6..d3a8aec45dbc 100644
--- a/test/MC/COFF/bss_section.ll
+++ b/test/MC/COFF/bss_section.ll
@@ -5,5 +5,6 @@
 @"\01?thingy@@3Ufoo@@B" = global %struct.foo zeroinitializer, align 4
 ; CHECK: .bss
 
-@thingy_linkonce = linkonce_odr global %struct.foo zeroinitializer, align 4
+$thingy_linkonce = comdat any
+@thingy_linkonce = linkonce_odr global %struct.foo zeroinitializer, comdat, align 4
 ; CHECK: .section .bss,"bw",discard,_thingy_linkonce
diff --git a/test/MC/COFF/const-gv-with-rel-init.ll b/test/MC/COFF/const-gv-with-rel-init.ll
index 5d0460dbaeff..fde5a17ad515 100644
--- a/test/MC/COFF/const-gv-with-rel-init.ll
+++ b/test/MC/COFF/const-gv-with-rel-init.ll
@@ -8,4 +8,4 @@ define void @f() {
 ; CHECK:  .section  .CRT$XLB,"dr"
 
 @weak_array = weak_odr unnamed_addr constant [1 x i8*] [i8* bitcast (void ()* @f to i8*)]
-; CHECK:  .section  .rdata,"dr",discard,weak_array
+; CHECK:  .section  .rdata,"dr"
diff --git a/test/MC/COFF/cross-section-relative.ll b/test/MC/COFF/cross-section-relative.ll
new file mode 100644
index 000000000000..18823f8b29a1
--- /dev/null
+++ b/test/MC/COFF/cross-section-relative.ll
@@ -0,0 +1,97 @@
+; Verify the assembler produces the expected expressions
+; RUN: llc -mtriple=x86_64-pc-win32 %s -o - | FileCheck %s
+; Verify the .fix data section conveys the right offsets and the right relocations
+; RUN: llc -mtriple=x86_64-pc-win32 -filetype=obj %s -o - | llvm-readobj -relocations -expand-relocs -sections -section-data | FileCheck %s --check-prefix=READOBJ
+
+;;;; some globals
+
+@g1 = constant i32 1;
+@g2 = constant i32 2;
+@g3 = constant i32 3;
+@g4 = constant i32 4;
+@__ImageBase = external global i64*;
+
+;;;; cross-section relative relocations
+
+; CHECK: .quad (g3-t1)+4
+@t1 = global i64 add(i64 sub(i64 ptrtoint(i32* @g3 to i64), i64 ptrtoint(i64* @t1 to i64)), i64 4), section ".fix"
+; CHECK: .quad g3-t2
+@t2 = global i64 sub(i64 ptrtoint(i32* @g3 to i64), i64 ptrtoint(i64* @t2 to i64)), section ".fix"
+; CHECK: .quad (g3-t3)-4
+@t3 = global i64 sub(i64 sub(i64 ptrtoint(i32* @g3 to i64), i64 ptrtoint(i64* @t3 to i64)), i64 4), section ".fix"
+; CHECK: .long g3-t4
+@t4 = global i32 trunc(i64 sub(i64 ptrtoint(i32* @g3 to i64), i64 ptrtoint(i32* @t4 to i64)) to i32), section ".fix"
+
+;;;; image base relocation
+
+; CHECK: .long g3@IMGREL
+@t5 = global i32 trunc(i64 sub(i64 ptrtoint(i32* @g3 to i64), i64 ptrtoint(i64** @__ImageBase to i64)) to i32), section ".fix"
+
+;;;; cross-section relative with source offset
+
+%struct.EEType = type { [2 x i8], i64, i32}
+
+; CHECK: .long g3-(t6+16)
+@t6 = global %struct.EEType { 
+        [2 x i8] c"\01\02", 
+        i64 256,
+        i32 trunc(i64 sub(i64 ptrtoint(i32* @g3 to i64), i64 ptrtoint(i32* getelementptr inbounds (%struct.EEType, %struct.EEType* @t6, i32 0, i32 2) to i64)) to i32 )
+}, section ".fix"
+
+; READOBJ:  Section {
+; READOBJ:    Number: 5
+; READOBJ:    Name: .fix (2E 66 69 78 00 00 00 00)
+; READOBJ:    VirtualSize: 0x0
+; READOBJ:    VirtualAddress: 0x0
+; READOBJ:    RawDataSize: 56
+; READOBJ:    PointerToRawData: 0xEC
+; READOBJ:    PointerToRelocations: 0x124
+; READOBJ:    PointerToLineNumbers: 0x0
+; READOBJ:    RelocationCount: 6
+; READOBJ:    LineNumberCount: 0
+; READOBJ:    Characteristics [ (0xC0500040)
+; READOBJ:      IMAGE_SCN_ALIGN_16BYTES (0x500000)
+; READOBJ:      IMAGE_SCN_CNT_INITIALIZED_DATA (0x40)
+; READOBJ:      IMAGE_SCN_MEM_READ (0x40000000)
+; READOBJ:      IMAGE_SCN_MEM_WRITE (0x80000000)
+; READOBJ:    ]
+; READOBJ:    SectionData (
+; READOBJ:      0000: 10000000 00000000 0C000000 00000000  |................|
+; READOBJ:      0010: 08000000 00000000 0C000000 00000000  |................|
+; READOBJ:      0020: 01020000 00000000 00010000 00000000  |................|
+; READOBJ:      0030: 0C000000 00000000                    |........|
+; READOBJ:    )
+; READOBJ:  }
+; READOBJ:  ]
+; READOBJ:  Relocations [
+; READOBJ:  Section (5) .fix {
+; READOBJ:    Relocation {
+; READOBJ:      Offset: 0x0
+; READOBJ:      Type: IMAGE_REL_AMD64_REL32 (4)
+; READOBJ:      Symbol: .rdata
+; READOBJ:    }
+; READOBJ:    Relocation {
+; READOBJ:      Offset: 0x8
+; READOBJ:      Type: IMAGE_REL_AMD64_REL32 (4)
+; READOBJ:      Symbol: .rdata
+; READOBJ:    }
+; READOBJ:    Relocation {
+; READOBJ:      Offset: 0x10
+; READOBJ:      Type: IMAGE_REL_AMD64_REL32 (4)
+; READOBJ:      Symbol: .rdata
+; READOBJ:    }
+; READOBJ:    Relocation {
+; READOBJ:      Offset: 0x18
+; READOBJ:      Type: IMAGE_REL_AMD64_REL32 (4)
+; READOBJ:      Symbol: .rdata
+; READOBJ:    }
+; READOBJ:    Relocation {
+; READOBJ:      Offset: 0x1C
+; READOBJ:      Type: IMAGE_REL_AMD64_ADDR32NB (3)
+; READOBJ:      Symbol: g3
+; READOBJ:    }
+; READOBJ:    Relocation {
+; READOBJ:      Offset: 0x30
+; READOBJ:      Type: IMAGE_REL_AMD64_REL32 (4)
+; READOBJ:      Symbol: .rdata
+; READOBJ:    }
diff --git a/test/MC/COFF/directive-section-characteristics.ll b/test/MC/COFF/directive-section-characteristics.ll
index ca8102af641d..a44c81d22627 100644
--- a/test/MC/COFF/directive-section-characteristics.ll
+++ b/test/MC/COFF/directive-section-characteristics.ll
@@ -7,7 +7,13 @@ entry:
 }
 
 ; CHECK: Section {
+; CHECK:   Name: .text
+; CHECK:   PointerToRawData: 0xB4
+; CHECK: }
+
+; CHECK: Section {
 ; CHECK:   Name: .drectve
+; CHECK:   PointerToRawData: 0xB8
 ; CHECK:   Characteristics [
 ; CHECK:     IMAGE_SCN_ALIGN_1BYTES
 ; CHECK:     IMAGE_SCN_LNK_INFO
diff --git a/test/MC/COFF/global_ctors_dtors.ll b/test/MC/COFF/global_ctors_dtors.ll
index be92c27c0d8a..e8f49867e52d 100644
--- a/test/MC/COFF/global_ctors_dtors.ll
+++ b/test/MC/COFF/global_ctors_dtors.ll
@@ -21,7 +21,7 @@
 declare i32 @puts(i8*)
 
 define void @a_global_ctor() nounwind {
-  %1 = call i32 @puts(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0))
+  %1 = call i32 @puts(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0))
   ret void
 }
 
@@ -40,12 +40,12 @@ define void @c_global_ctor() nounwind {
 }
 
 define void @a_global_dtor() nounwind {
-  %1 = call i32 @puts(i8* getelementptr inbounds ([12 x i8]* @.str2, i32 0, i32 0))
+  %1 = call i32 @puts(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str2, i32 0, i32 0))
   ret void
 }
 
 define i32 @main() nounwind {
-  %1 = call i32 @puts(i8* getelementptr inbounds ([5 x i8]* @.str3, i32 0, i32 0))
+  %1 = call i32 @puts(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str3, i32 0, i32 0))
   ret i32 0
 }
 
diff --git a/test/MC/COFF/ir-to-imgrel.ll b/test/MC/COFF/ir-to-imgrel.ll
index dfc88b2a6752..21198cf51323 100644
--- a/test/MC/COFF/ir-to-imgrel.ll
+++ b/test/MC/COFF/ir-to-imgrel.ll
@@ -4,3 +4,8 @@
 
 ; X64: .quad   "?x@@3HA"@IMGREL
 @"\01?x@@3HA" = global i64 sub nsw (i64 ptrtoint (i64* @"\01?x@@3HA" to i64), i64 ptrtoint (i8* @__ImageBase to i64)), align 8
+
+declare void @f()
+
+; X64: .quad   f@IMGREL
+@fp = global i64 sub nsw (i64 ptrtoint (void ()* @f to i64), i64 ptrtoint (i8* @__ImageBase to i64)), align 8
diff --git a/test/MC/COFF/linker-options.ll b/test/MC/COFF/linker-options.ll
index a5b866632cc9..afc55af692d2 100755
--- a/test/MC/COFF/linker-options.ll
+++ b/test/MC/COFF/linker-options.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -O0 -mtriple=i386-pc-win32 -filetype=asm -o - %s | FileCheck %s
 
-!0 = !{i32 6, !"Linker Options", !{!{!"/DEFAULTLIB:msvcrt.lib"}, !{!"/DEFAULTLIB:msvcrt.lib", !"/DEFAULTLIB:secur32.lib"}, !{!"/DEFAULTLIB:C:\5Cpath to\5Casan_rt.lib"}, !{!"/with spaces"}, !{!"\22/quoted spaces\22"}}}
+!0 = !{i32 6, !"Linker Options", !{!{!"/DEFAULTLIB:msvcrt.lib"}, !{!"/DEFAULTLIB:msvcrt.lib", !"/DEFAULTLIB:secur32.lib"}, !{!"/DEFAULTLIB:\22C:\5Cpath to\5Casan_rt.lib\22"}, !{!"\22/with spaces\22"}}}
 
 !llvm.module.flags = !{ !0 }
 
@@ -12,7 +12,6 @@ define dllexport void @foo() {
 ; CHECK: .ascii   " /DEFAULTLIB:msvcrt.lib"
 ; CHECK: .ascii   " /DEFAULTLIB:msvcrt.lib"
 ; CHECK: .ascii   " /DEFAULTLIB:secur32.lib"
-; CHECK: .ascii   " \"/DEFAULTLIB:C:\\path to\\asan_rt.lib\""
+; CHECK: .ascii   " /DEFAULTLIB:\"C:\\path to\\asan_rt.lib\""
 ; CHECK: .ascii   " \"/with spaces\""
-; CHECK: .ascii   " \"/quoted spaces\""
 ; CHECK: .ascii   " /EXPORT:_foo"
diff --git a/test/MC/COFF/pr23025.s b/test/MC/COFF/pr23025.s
new file mode 100644
index 000000000000..f0d007543a47
--- /dev/null
+++ b/test/MC/COFF/pr23025.s
@@ -0,0 +1,23 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-windows-msvc < %s | llvm-readobj -r | FileCheck %s
+
+// CHECK:      Relocations [
+// CHECK-NEXT:   Section {{.*}} .text {
+// CHECK-NEXT:     0x3 IMAGE_REL_AMD64_REL32 zed
+// CHECK-NEXT:     0xA IMAGE_REL_AMD64_REL32 zed2
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
+
+foo:
+	leaq	zed(%rip), %rax
+	leaq	zed2(%rip), %rax
+	retq
+
+	.section	.rdata,"dr",discard,zed
+Lbar:
+	.zero	2
+
+	.globl	zed
+zed = Lbar+1
+
+	.globl	zed2
+zed2 = Lbar
diff --git a/test/MC/COFF/tricky-names.ll b/test/MC/COFF/tricky-names.ll
index 458aa41fb2be..f34b76a278e7 100644
--- a/test/MC/COFF/tricky-names.ll
+++ b/test/MC/COFF/tricky-names.ll
@@ -10,9 +10,9 @@
 @"\01@foo.bar" = global i32 0
 
 define weak i32 @"\01??_B?$num_put@_WV?$back_insert_iterator@V?$basic_string@_WU?$char_traits@_W@std@@V?$allocator@_W@2@@std@@@std@@@std@@51"() section ".text" {
-  %a = load i32* @"\01??__E_Generic_object@?$_Error_objects@H@std@@YAXXZ"
-  %b = load i32* @"\01__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4"
-  %c = load i32* @"\01@foo.bar"
+  %a = load i32, i32* @"\01??__E_Generic_object@?$_Error_objects@H@std@@YAXXZ"
+  %b = load i32, i32* @"\01__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4"
+  %c = load i32, i32* @"\01@foo.bar"
   %x = add i32 %a, %b
   %y = add i32 %x, %c
   ret i32 %y
diff --git a/test/MC/COFF/weak-symbol.ll b/test/MC/COFF/weak-symbol.ll
deleted file mode 100644
index 0ab860cad462..000000000000
--- a/test/MC/COFF/weak-symbol.ll
+++ /dev/null
@@ -1,48 +0,0 @@
-; Test that weak functions and globals are placed into selectany COMDAT

-; sections with the mangled name as suffix. Ensure that the weak linkage

-; type is not ignored by the backend if the section was specialized.

-;

-; RUN: llc -mtriple=i686-pc-win32 %s     -o - | FileCheck %s --check-prefix=X86

-; RUN: llc -mtriple=i686-pc-mingw32 %s   -o - | FileCheck %s --check-prefix=X86

-; RUN: llc -mtriple=x86_64-pc-win32 %s   -o - | FileCheck %s --check-prefix=X64

-; RUN: llc -mtriple=x86_64-pc-mingw32 %s -o - | FileCheck %s --check-prefix=X64

-

-; Mangled function

-; X86: .section .text,"xr",discard,__Z3foo

-; X86: .globl __Z3foo

-;

-; X64: .section .text,"xr",discard,_Z3foo

-; X64: .globl _Z3foo

-define weak void @_Z3foo() {

-  ret void

-}

-

-; Unmangled function

-; X86: .section .sect,"xr",discard,_f

-; X86: .globl _f

-;

-; X64: .section .sect,"xr",discard,f

-; X64: .globl f

-define weak void @f() section ".sect" {

-  ret void

-}

-

-; Weak global

-; X86: .section .data,"dr",discard,_a

-; X86: .globl _a

-; X86: .zero 12

-;

-; X64: .section .data,"dr",discard,a

-; X64: .globl a

-; X64: .zero 12

-@a = weak unnamed_addr constant { i32, i32, i32 } { i32 0, i32 0, i32 0}, section ".data"

-

-; X86:  .section        .tls$,"dw",discard,_b

-; X86:  .globl  _b

-; X86:  .long   0

-;

-; X64:  .section        .tls$,"dw",discard,b

-; X64:  .globl  b

-; X64:  .long   0

-

-@b = weak_odr thread_local global i32 0, align 4

diff --git a/test/MC/Disassembler/AArch64/arm64-advsimd.txt b/test/MC/Disassembler/AArch64/arm64-advsimd.txt
index cceee672dfd7..ef125c8e32f3 100644
--- a/test/MC/Disassembler/AArch64/arm64-advsimd.txt
+++ b/test/MC/Disassembler/AArch64/arm64-advsimd.txt
@@ -169,6 +169,43 @@
 # CHECK: ins.h v2[7], v15[3]
 # CHECK: ins.b v2[10], v15[5]
 
+# INS/DUP (non-standard)
+0x60 0x0c 0x08 0x4e
+0x60 0x0c 0x0c 0x4e
+0x60 0x0c 0x0c 0x0e
+0x60 0x0c 0x0e 0x4e
+0x60 0x0c 0x0e 0x0e
+0x60 0x0c 0x0f 0x4e
+0x60 0x0c 0x0f 0x0e
+
+# CHECK: dup.2d  v0, x3
+# CHECK: dup.4s  v0, w3
+# CHECK: dup.2s  v0, w3
+# CHECK: dup.8h  v0, w3
+# CHECK: dup.4h  v0, w3
+# CHECK: dup.16b v0, w3
+# CHECK: dup.8b  v0, w3
+
+0xe2 0x75 0x18 0x6e
+0xe2 0x35 0x0c 0x6e
+0xe2 0x15 0x06 0x6e
+0xe2 0x0d 0x03 0x6e
+
+0xe2 0x05 0x18 0x6e
+0xe2 0x55 0x1c 0x6e
+0xe2 0x35 0x1e 0x6e
+0xe2 0x2d 0x15 0x6e
+
+# CHECK: ins.d v2[1], v15[1]
+# CHECK: ins.s v2[1], v15[1]
+# CHECK: ins.h v2[1], v15[1]
+# CHECK: ins.b v2[1], v15[1]
+
+# CHECK: ins.d v2[1], v15[0]
+# CHECK: ins.s v2[3], v15[2]
+# CHECK: ins.h v2[7], v15[3]
+# CHECK: ins.b v2[10], v15[5]
+
 0x00 0x1c 0x20 0x0e
 0x00 0x1c 0x20 0x4e
 
diff --git a/test/MC/Disassembler/AArch64/armv8.1a-lor.txt b/test/MC/Disassembler/AArch64/armv8.1a-lor.txt
new file mode 100644
index 000000000000..1194351eab94
--- /dev/null
+++ b/test/MC/Disassembler/AArch64/armv8.1a-lor.txt
@@ -0,0 +1,38 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s
+
+0x20,0x7c,0xdf,0x08
+0x20,0x7c,0xdf,0x48
+0x20,0x7c,0xdf,0x88
+0x20,0x7c,0xdf,0xc8
+0x20,0x7c,0x9f,0x08
+0x20,0x7c,0x9f,0x48
+0x20,0x7c,0x9f,0x88
+0x20,0x7c,0x9f,0xc8
+# CHECK:   ldlarb w0, [x1]
+# CHECK:   ldlarh w0, [x1]
+# CHECK:   ldlar  w0, [x1]
+# CHECK:   ldlar  x0, [x1]
+# CHECK:   stllrb w0, [x1]
+# CHECK:   stllrh w0, [x1]
+# CHECK:   stllr  w0, [x1]
+# CHECK:   stllr  x0, [x1]
+0x00,0xa4,0x18,0xd5
+0x20,0xa4,0x18,0xd5
+0x40,0xa4,0x18,0xd5
+0x60,0xa4,0x18,0xd5
+0xe0,0xa4,0x18,0xd5
+# CHECK:   msr LORSA_EL1, x0
+# CHECK:   msr LOREA_EL1, x0
+# CHECK:   msr LORN_EL1, x0
+# CHECK:   msr LORC_EL1, x0
+# CHECK:   msr S3_0_C10_C4_7, x0
+0x00,0xa4,0x38,0xd5
+0x20,0xa4,0x38,0xd5
+0x40,0xa4,0x38,0xd5
+0x60,0xa4,0x38,0xd5
+0xe0,0xa4,0x38,0xd5
+# CHECK:   mrs x0, LORSA_EL1
+# CHECK:   mrs x0, LOREA_EL1
+# CHECK:   mrs x0, LORN_EL1
+# CHECK:   mrs x0, LORC_EL1
+# CHECK:   mrs x0, LORID_EL1
diff --git a/test/MC/Disassembler/AArch64/armv8.1a-pan.txt b/test/MC/Disassembler/AArch64/armv8.1a-pan.txt
new file mode 100644
index 000000000000..2af5c2aa21ef
--- /dev/null
+++ b/test/MC/Disassembler/AArch64/armv8.1a-pan.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s
+
+0x9f,0x40,0x00,0xd5
+0x9f,0x41,0x00,0xd5
+0x65,0x42,0x18,0xd5
+0x6d,0x42,0x38,0xd5
+# CHECK:  msr PAN, #0
+# CHECK:  msr PAN, #1
+# CHECK:  msr PAN, x5
+# CHECK:  mrs x13, PAN
diff --git a/test/MC/Disassembler/AArch64/armv8.1a-rdma.txt b/test/MC/Disassembler/AArch64/armv8.1a-rdma.txt
new file mode 100644
index 000000000000..5e1272f66f3f
--- /dev/null
+++ b/test/MC/Disassembler/AArch64/armv8.1a-rdma.txt
@@ -0,0 +1,129 @@
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s
+
+[0x20,0x84,0x02,0x2e] # sqrdmlah  v0.8b, v1.8b, v2.8b
+[0x20,0x8c,0x02,0x2e] # sqrdmlsh  v0.8b, v1.8b, v2.8b
+[0x20,0x84,0xc2,0x2e] # sqrdmlah  v0.1d, v1.1d, v2.1d
+[0x20,0x8c,0xc2,0x2e] # sqrdmlsh  v0.1d, v1.1d, v2.1d
+[0x20,0x84,0x02,0x6e] # sqrdmlah  v0.16b, v1.16b, v2.16b
+[0x20,0x8c,0x02,0x6e] # sqrdmlsh  v0.16b, v1.16b, v2.16b
+[0x20,0x84,0xc2,0x6e] # sqrdmlah  v0.2d, v1.2d, v2.2d
+[0x20,0x8c,0xc2,0x6e] # sqrdmlsh  v0.2d, v1.2d, v2.2d
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0x84,0x02,0x2e]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0x8c,0x02,0x2e]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0x84,0xc2,0x2e]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0x8c,0xc2,0x2e]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0x84,0x02,0x6e]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0x8c,0x02,0x6e]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0x84,0xc2,0x6e]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0x8c,0xc2,0x6e]
+
+[0x20,0x84,0x02,0x7e] # sqrdmlah b0, b1, b2
+[0x20,0x8c,0x02,0x7e] # sqrdmlsh b0, b1, b2
+[0x20,0x84,0xc2,0x7e] # sqrdmlah d0, d1, d2
+[0x20,0x8c,0xc2,0x7e] # sqrdmlsh d0, d1, d2
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0x84,0x02,0x7e]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0x8c,0x02,0x7e]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0x84,0xc2,0x7e]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0x8c,0xc2,0x7e]
+
+[0x20,0xd0,0x32,0x2f] # sqrdmlah v0.8b, v1.8b, v2.b[3]
+[0x20,0xf0,0x32,0x2f] # sqrdmlsh v0.8b, v1.8b, v2.b[3]
+[0x20,0xd0,0xe2,0x2f] # sqrdmlah v0.1d, v1.1d, v2.d[1]
+[0x20,0xf0,0xe2,0x2f] # sqrdmlsh v0.1d, v1.1d, v2.d[1]
+[0x20,0xd0,0x32,0x6f] # sqrdmlah v0.16b, v1.16b, v2.b[3]
+[0x20,0xf0,0x32,0x6f] # sqrdmlsh v0.16b, v1.16b, v2.b[3]
+[0x20,0xd8,0xe2,0x6f] # sqrdmlah v0.2d, v1.2d, v2.d[3]
+[0x20,0xf8,0xe2,0x6f] # sqrdmlsh v0.2d, v1.2d, v2.d[3]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0xd0,0x32,0x2f]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0xf0,0x32,0x2f]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0xd0,0xe2,0x2f]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0xf0,0xe2,0x2f]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0xd0,0x32,0x6f]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0xf0,0x32,0x6f]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0xd8,0xe2,0x6f]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0xf8,0xe2,0x6f]
+
+[0x20,0xd0,0x32,0x7f] # sqrdmlah b0, b1, v2.b[3]
+[0x20,0xf0,0x32,0x7f] # sqrdmlsh b0, b1, v2.b[3]
+[0x20,0xd8,0xe2,0x7f] # sqrdmlah d0, d1, v2.d[3]
+[0x20,0xf8,0xe2,0x7f] # sqrdmlsh d0, d1, v2.d[3]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0xd0,0x32,0x7f]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0xf0,0x32,0x7f]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0xd8,0xe2,0x7f]
+# CHECK: warning: invalid instruction encoding
+# CHECK: [0x20,0xf8,0xe2,0x7f]
+
+[0x20,0x84,0x42,0x2e]
+[0x20,0x8c,0x42,0x2e]
+[0x20,0x84,0x82,0x2e]
+[0x20,0x8c,0x82,0x2e]
+[0x20,0x84,0x42,0x6e]
+[0x20,0x8c,0x42,0x6e]
+[0x20,0x84,0x82,0x6e]
+[0x20,0x8c,0x82,0x6e]
+# CHECK: sqrdmlah  v0.4h, v1.4h, v2.4h
+# CHECK: sqrdmlsh  v0.4h, v1.4h, v2.4h
+# CHECK: sqrdmlah  v0.2s, v1.2s, v2.2s
+# CHECK: sqrdmlsh  v0.2s, v1.2s, v2.2s
+# CHECK: sqrdmlah  v0.8h, v1.8h, v2.8h
+# CHECK: sqrdmlsh  v0.8h, v1.8h, v2.8h
+# CHECK: sqrdmlah  v0.4s, v1.4s, v2.4s
+# CHECK: sqrdmlsh  v0.4s, v1.4s, v2.4s
+
+[0x20,0x84,0x42,0x7e]
+[0x20,0x8c,0x42,0x7e]
+[0x20,0x84,0x82,0x7e]
+[0x20,0x8c,0x82,0x7e]
+# CHECK: sqrdmlah h0, h1, h2
+# CHECK: sqrdmlsh h0, h1, h2
+# CHECK: sqrdmlah s0, s1, s2
+# CHECK: sqrdmlsh s0, s1, s2
+
+0x20,0xd0,0x72,0x2f
+0x20,0xf0,0x72,0x2f
+0x20,0xd0,0xa2,0x2f
+0x20,0xf0,0xa2,0x2f
+0x20,0xd0,0x72,0x6f
+0x20,0xf0,0x72,0x6f
+0x20,0xd8,0xa2,0x6f
+0x20,0xf8,0xa2,0x6f
+# CHECK: sqrdmlah v0.4h, v1.4h, v2.h[3]
+# CHECK: sqrdmlsh v0.4h, v1.4h, v2.h[3]
+# CHECK: sqrdmlah v0.2s, v1.2s, v2.s[1]
+# CHECK: sqrdmlsh v0.2s, v1.2s, v2.s[1]
+# CHECK: sqrdmlah v0.8h, v1.8h, v2.h[3]
+# CHECK: sqrdmlsh v0.8h, v1.8h, v2.h[3]
+# CHECK: sqrdmlah v0.4s, v1.4s, v2.s[3]
+# CHECK: sqrdmlsh v0.4s, v1.4s, v2.s[3]
+
+0x20,0xd0,0x72,0x7f
+0x20,0xf0,0x72,0x7f
+0x20,0xd8,0xa2,0x7f
+0x20,0xf8,0xa2,0x7f
+# CHECK: sqrdmlah h0, h1, v2.h[3]
+# CHECK: sqrdmlsh h0, h1, v2.h[3]
+# CHECK: sqrdmlah s0, s1, v2.s[3]
+# CHECK: sqrdmlsh s0, s1, v2.s[3]
diff --git a/test/MC/Disassembler/AArch64/armv8.1a-vhe.txt b/test/MC/Disassembler/AArch64/armv8.1a-vhe.txt
new file mode 100644
index 000000000000..e4bf59c2b322
--- /dev/null
+++ b/test/MC/Disassembler/AArch64/armv8.1a-vhe.txt
@@ -0,0 +1,56 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s
+
+0x20,0x20,0x1c,0xd5
+0x20,0xd0,0x1c,0xd5
+0x00,0xe3,0x1c,0xd5
+0x40,0xe3,0x1c,0xd5
+0x20,0xe3,0x1c,0xd5
+0x00,0x10,0x1d,0xd5
+0x40,0x10,0x1d,0xd5
+0x00,0x20,0x1d,0xd5
+0x20,0x20,0x1d,0xd5
+0x40,0x20,0x1d,0xd5
+0x00,0x51,0x1d,0xd5
+0x20,0x51,0x1d,0xd5
+0x00,0x52,0x1d,0xd5
+0x00,0x60,0x1d,0xd5
+0x00,0xa2,0x1d,0xd5
+0x00,0xa3,0x1d,0xd5
+0x00,0xc0,0x1d,0xd5
+0x20,0xd0,0x1d,0xd5
+0x00,0xe1,0x1d,0xd5
+0x00,0xe2,0x1d,0xd5
+0x20,0xe2,0x1d,0xd5
+0x40,0xe2,0x1d,0xd5
+0x00,0xe3,0x1d,0xd5
+0x20,0xe3,0x1d,0xd5
+0x40,0xe3,0x1d,0xd5
+0x00,0x40,0x1d,0xd5
+0x20,0x40,0x1d,0xd5
+# CHECK:   msr TTBR1_EL2, x0
+# CHECK:   msr CONTEXTIDR_EL2, x0
+# CHECK:   msr CNTHV_TVAL_EL2, x0
+# CHECK:   msr CNTHV_CVAL_EL2, x0
+# CHECK:   msr CNTHV_CTL_EL2, x0
+# CHECK:   msr SCTLR_EL12, x0
+# CHECK:   msr CPACR_EL12, x0
+# CHECK:   msr TTBR0_EL12, x0
+# CHECK:   msr TTBR1_EL12, x0
+# CHECK:   msr TCR_EL12, x0
+# CHECK:   msr AFSR0_EL12, x0
+# CHECK:   msr AFSR1_EL12, x0
+# CHECK:   msr ESR_EL12, x0
+# CHECK:   msr FAR_EL12, x0
+# CHECK:   msr MAIR_EL12, x0
+# CHECK:   msr AMAIR_EL12, x0
+# CHECK:   msr VBAR_EL12, x0
+# CHECK:   msr CONTEXTIDR_EL12, x0
+# CHECK:   msr CNTKCTL_EL12, x0
+# CHECK:   msr CNTP_TVAL_EL02, x0
+# CHECK:   msr CNTP_CTL_EL02, x0
+# CHECK:   msr CNTP_CVAL_EL02, x0
+# CHECK:   msr CNTV_TVAL_EL02, x0
+# CHECK:   msr CNTV_CTL_EL02, x0
+# CHECK:   msr CNTV_CVAL_EL02, x0
+# CHECK:   msr SPSR_EL12, x0
+# CHECK:   msr ELR_EL12, x0
diff --git a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
index 23da001accb6..c777f7aa6494 100644
--- a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
+++ b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -622,7 +622,7 @@
 
 # CHECK: bfi      x4, x5, #52, #11
 # CHECK: bfxil    xzr, x4, #0, #1
-# CHECK: bfi      x4, xzr, #1, #6
+# CHECK: bfc      x4, #1, #6
 # CHECK: bfxil    x5, x6, #12, #52
 0xa4 0x28 0x4c 0xb3
 0x9f 0x0 0x40 0xb3
@@ -715,7 +715,7 @@
 # CHECK: bfxil    w9, w10, #0, #32
 # CHECK: bfi      w11, w12, #31, #1
 # CHECK: bfi      w13, w14, #29, #3
-# CHECK: bfi      xzr, xzr, #10, #11
+# CHECK: bfc      xzr, #10, #11
 0x49 0x1 0x0 0x33
 0x62 0x0 0x41 0xb3
 0x93 0xfe 0x40 0xb3
diff --git a/test/MC/Disassembler/ARM/armv8.1a.txt b/test/MC/Disassembler/ARM/armv8.1a.txt
new file mode 100644
index 000000000000..929643bd5610
--- /dev/null
+++ b/test/MC/Disassembler/ARM/armv8.1a.txt
@@ -0,0 +1,52 @@
+# RUN: llvm-mc -triple armv8 -mattr=+v8.1a  --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V81a
+# RUN: not llvm-mc -triple armv8 -mattr=+v8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8
+
+[0x54,0x0b,0x12,0xf3]
+[0x12,0x0b,0x21,0xf3]
+[0x54,0x0c,0x12,0xf3]
+[0x12,0x0c,0x21,0xf3]
+# CHECK-V81a:  vqrdmlah.s16  q0, q1, q2
+# CHECK-V81a:  vqrdmlah.s32  d0, d1, d2
+# CHECK-V81a:  vqrdmlsh.s16  q0, q1, q2
+# CHECK-V81a:  vqrdmlsh.s32  d0, d1, d2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x54,0x0b,0x12,0xf3]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x12,0x0b,0x21,0xf3]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x54,0x0c,0x12,0xf3]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x12,0x0c,0x21,0xf3]
+
+[0x42,0x0e,0x92,0xf3]
+[0x42,0x0e,0xa1,0xf2]
+[0x42,0x0f,0x92,0xf3]
+[0x42,0x0f,0xa1,0xf2]
+# CHECK-V81a:  vqrdmlah.s16 q0, q1, d2[0]
+# CHECK-V81a:  vqrdmlah.s32 d0, d1, d2[0]
+# CHECK-V81a:  vqrdmlsh.s16 q0, q1, d2[0]
+# CHECK-V81a:  vqrdmlsh.s32 d0, d1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x42,0x0e,0x92,0xf3]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x42,0x0e,0xa1,0xf2]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x42,0x0f,0x92,0xf3]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x42,0x0f,0xa1,0xf2]
+
+# The SETPAN(v8.1a) and TST(v8) instructions occupy the same space, but SETPAN 
+# uses the encoding for the invalid NV predicate operand. This test checks that 
+# the disassembler is correctly disambiguating and decoding these instructions.
+
+[0x00 0x00 0x10 0xf1]
+# CHECK: setpan #0
+
+[0x00 0x02 0x10 0xf1]
+# CHECK: setpan #1
+
+[0x00 0x00 0x10 0xe1]
+# CHECK: tst r0, r0
+
+[0x00 0x02 0x10 0xe1]
+# CHECK: tst r0, r0, lsl #4
diff --git a/test/MC/Disassembler/ARM/invalid-armv8.1a.txt b/test/MC/Disassembler/ARM/invalid-armv8.1a.txt
new file mode 100644
index 000000000000..1a9f2754fc9a
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-armv8.1a.txt
@@ -0,0 +1,83 @@
+# RUN: not llvm-mc -triple armv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s
+
+# Check, if sizes 00 and 11 are undefined for RDMA
+[0x12,0x0b,0x01,0xf3] # vqrdmlah.s8   d0, d1, d2
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x12,0x0b,0x01,0xf3] # vqrdmlah.s8   d0, d1, d2
+# CHECK-NEXT:  ^
+
+[0x12,0x0b,0x31,0xf3] # vqrdmlah.s64  d0, d1, d2
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x12,0x0b,0x31,0xf3] # vqrdmlah.s64  d0, d1, d2
+# CHECK-NEXT:  ^
+
+[0x54,0x0b,0x02,0xf3] # vqrdmlah.s8   q0, q1, q2
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x54,0x0b,0x02,0xf3] # vqrdmlah.s8   q0, q1, q2
+# CHECK-NEXT:  ^
+
+[0x54,0x0b,0x32,0xf3] # vqrdmlah.s64  q2, q3, q0
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x54,0x0b,0x32,0xf3] # vqrdmlah.s64  q2, q3, q0
+# CHECK-NEXT:  ^
+
+[0x15,0x7c,0x06,0xf3] # vqrdmlsh.s8   d0, d1, d2
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x15,0x7c,0x06,0xf3] # vqrdmlsh.s8   d0, d1, d2
+# CHECK-NEXT:  ^
+
+[0x15,0x7c,0x36,0xf3] # vqrdmlsh.s64  d0, d1, d2
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x15,0x7c,0x36,0xf3] # vqrdmlsh.s64  d0, d1, d2
+# CHECK-NEXT:  ^
+
+[0x54,0x0c,0x02,0xf3] # vqrdmlsh.s8   q0, q1, q2
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x54,0x0c,0x02,0xf3] # vqrdmlsh.s8   q0, q1, q2
+# CHECK-NEXT:  ^
+
+[0x54,0x0c,0x32,0xf3] # vqrdmlsh.s64  q0, q1, q2
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x54,0x0c,0x32,0xf3] # vqrdmlsh.s64  q0, q1, q2
+# CHECK-NEXT:  ^
+
+[0x42,0x0e,0x81,0xf2] # vqrdmlah.s8   d0, d1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0e,0x81,0xf2] # vqrdmlah.s8   d0, d1, d2[0]
+# CHECK-NEXT:  ^
+
+[0x42,0x0e,0xb1,0xf2] # vqrdmlah.s64  d0, d1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0e,0xb1,0xf2] # vqrdmlah.s64  d0, d1, d2[0]
+# CHECK-NEXT:  ^
+
+[0x42,0x0e,0x82,0xf3] # vqrdmlah.s8   q0, q1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0e,0x82,0xf3] # vqrdmlah.s8   q0, q1, d2[0]
+# CHECK-NEXT:  ^
+
+[0x42,0x0e,0xb2,0xf3] # vqrdmlah.s64  q0, q1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0e,0xb2,0xf3] # vqrdmlah.s64  q0, q1, d2[0]
+# CHECK-NEXT:  ^
+
+
+[0x42,0x0f,0x81,0xf2] # vqrdmlsh.s8   d0, d1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0f,0x81,0xf2] # vqrdmlsh.s8   d0, d1, d2[0]
+# CHECK-NEXT:  ^
+
+[0x42,0x0f,0xb1,0xf2] # vqrdmlsh.s64  d0, d1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0f,0xb1,0xf2] # vqrdmlsh.s64  d0, d1, d2[0]
+# CHECK-NEXT:  ^
+
+[0x42,0x0f,0x82,0xf3] # vqrdmlsh.s8   q0, q1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0f,0x82,0xf3] # vqrdmlsh.s8   q0, q1, d2[0]
+# CHECK-NEXT:  ^
+
+[0x42,0x0f,0xb2,0xf3] # vqrdmlsh.s64  q0, q1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0f,0xb2,0xf3] # vqrdmlsh.s64  q0, q1, d2[0]
+# CHECK-NEXT:  ^
diff --git a/test/MC/Disassembler/ARM/invalid-thumbv8.1a.txt b/test/MC/Disassembler/ARM/invalid-thumbv8.1a.txt
new file mode 100644
index 000000000000..555b8c3c54d1
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-thumbv8.1a.txt
@@ -0,0 +1,72 @@
+# RUN: not llvm-mc -triple thumbv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s
+
+# Check, if sizes 00 and 11 are undefined for RDMA
+[0x01,0xff,0x12,0x0b] # vqrdmlah.s8   d0, d1, d2
+[0x31,0xff,0x12,0x0b] # vqrdmlah.s64  d0, d1, d2
+[0x02,0xff,0x54,0x0b] # vqrdmlah.s8   q0, q1, q2
+[0x06,0xff,0x50,0x4b] # vqrdmlah.s64  q2, q3, q0
+
+[0x01,0xff,0x12,0x0c] # vqrdmlsh.s8   d0, d1, d2
+[0x31,0xff,0x12,0x0c] # vqrdmlsh.s64  d0, d1, d2
+[0x02,0xff,0x54,0x0c] # vqrdmlsh.s8   q0, q1, q2
+[0x32,0xff,0x54,0x0c] # vqrdmlsh.s64  q0, q1, q2
+
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x01,0xff,0x12,0x0b] # vqrdmlah.s8   d0, d1, d2
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x31,0xff,0x12,0x0b] # vqrdmlah.s64  d0, d1, d2
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x02,0xff,0x54,0x0b] # vqrdmlah.s8   q0, q1, q2
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x06,0xff,0x50,0x4b] # vqrdmlah.s64  q2, q3, q0
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x01,0xff,0x12,0x0c] # vqrdmlsh.s8   d0, d1, d2
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x31,0xff,0x12,0x0c] # vqrdmlsh.s64  d0, d1, d2
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x02,0xff,0x54,0x0c] # vqrdmlsh.s8   q0, q1, q2
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x32,0xff,0x54,0x0c] # vqrdmlsh.s64  q0, q1, q2
+# CHECK-NEXT:  ^
+
+[0x81,0xef,0x42,0x0e] # vqrdmlah.s8   d0, d1, d2[0]
+[0xb1,0xef,0x42,0x0e] # vqrdmlah.s64  d0, d1, d2[0]
+[0x82,0xff,0x42,0x0e] # vqrdmlah.s8   q0, q1, d2[0]
+[0xb2,0xff,0x42,0x0e] # vqrdmlah.s64  q0, q1, d2[0]
+
+[0x81,0xef,0x42,0x0f] # vqrdmlsh.s8   d0, d1, d2[0]
+[0xb1,0xef,0x42,0x0f] # vqrdmlsh.s64  d0, d1, d2[0]
+[0x82,0xff,0x42,0x0f] # vqrdmlsh.s8   q0, q1, d2[0]
+[0xb2,0xff,0x42,0x0f] # vqrdmlsh.s64  q0, q1, d2[0]
+
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x81,0xef,0x42,0x0e] # vqrdmlah.s8   d0, d1, d2[0]
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0xb1,0xef,0x42,0x0e] # vqrdmlah.s64  d0, d1, d2[0]
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x82,0xff,0x42,0x0e] # vqrdmlah.s8   q0, q1, d2[0]
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0xb2,0xff,0x42,0x0e] # vqrdmlah.s64  q0, q1, d2[0]
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x81,0xef,0x42,0x0f] # vqrdmlsh.s8   d0, d1, d2[0]
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0xb1,0xef,0x42,0x0f] # vqrdmlsh.s64  d0, d1, d2[0]
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x82,0xff,0x42,0x0f] # vqrdmlsh.s8   q0, q1, d2[0]
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0xb2,0xff,0x42,0x0f] # vqrdmlsh.s64  q0, q1, d2[0]
+# CHECK-NEXT:  ^
diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt
index e493fbaefc53..536095f6a37b 100644
--- a/test/MC/Disassembler/ARM/neont2.txt
+++ b/test/MC/Disassembler/ARM/neont2.txt
@@ -1631,11 +1631,11 @@
 
 # rdar://10798451
 0xe7 0xf9 0x32 0x1d
-# CHECK vld2.8	{d17[], d19[]}, [r7:16], r2
+# CHECK: vld2.8	{d17[], d19[]}, [r7:16], r2
 0xe7 0xf9 0x3d 0x1d
-# CHECK vld2.8	{d17[], d19[]}, [r7:16]!
+# CHECK: vld2.8	{d17[], d19[]}, [r7:16]!
 0xe7 0xf9 0x3f 0x1d
-# CHECK vld2.8	{d17[], d19[]}, [r7:16]
+# CHECK: vld2.8	{d17[], d19[]}, [r7:16]
 
 # rdar://11034702
 0x04 0xf9 0x0d 0x87
diff --git a/test/MC/Disassembler/ARM/thumb-v8.1a.txt b/test/MC/Disassembler/ARM/thumb-v8.1a.txt
new file mode 100644
index 000000000000..3de8c272ffa9
--- /dev/null
+++ b/test/MC/Disassembler/ARM/thumb-v8.1a.txt
@@ -0,0 +1,110 @@
+# RUN: llvm-mc -triple thumbv8 -mattr=+v8.1a  --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V81a
+# RUN: not llvm-mc -triple thumbv8 -mattr=+v8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8
+
+[0x11,0xff,0x12,0x0b]
+# CHECK-V81a: vqrdmlah.s16  d0, d1, d2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x11,0xff,0x12,0x0b]
+# CHECK-V8: ^
+
+[0x21,0xff,0x12,0x0b]
+# CHECK-V81a: vqrdmlah.s32  d0, d1, d2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x21,0xff,0x12,0x0b]
+# CHECK-V8: ^
+
+[0x12,0xff,0x54,0x0b]
+# CHECK-V81a: vqrdmlah.s16  q0, q1, q2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x12,0xff,0x54,0x0b]
+# CHECK-V8: ^
+
+[0x26,0xff,0x50,0x4b]
+# CHECK-V81a: vqrdmlah.s32  q2, q3, q0
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x26,0xff,0x50,0x4b]
+# CHECK-V8: ^
+
+[0x16,0xff,0x15,0x7c]
+# CHECK-V81a: vqrdmlsh.s16  d7, d6, d5
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x16,0xff,0x15,0x7c]
+# CHECK-V8: ^
+
+[0x21,0xff,0x12,0x0c]
+# CHECK-V81a: vqrdmlsh.s32  d0, d1, d2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x21,0xff,0x12,0x0c]
+# CHECK-V8: ^
+
+[0x12,0xff,0x54,0x0c]
+# CHECK-V81a: vqrdmlsh.s16  q0, q1, q2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x12,0xff,0x54,0x0c]
+# CHECK-V8: ^
+
+[0x28,0xff,0x5a,0x6c]
+# CHECK-V81a: vqrdmlsh.s32  q3, q4, q5
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x28,0xff,0x5a,0x6c]
+# CHECK-V8: ^
+
+[0x91,0xef,0x42,0x0e]
+# CHECK-V81a: vqrdmlah.s16  d0, d1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x91,0xef,0x42,0x0e]
+# CHECK-V8: ^
+
+[0xa1,0xef,0x42,0x0e]
+# CHECK-V81a: vqrdmlah.s32  d0, d1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0xa1,0xef,0x42,0x0e]
+# CHECK-V8: ^
+
+[0x92,0xff,0x42,0x0e]
+# CHECK-V81a: vqrdmlah.s16  q0, q1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x92,0xff,0x42,0x0e]
+# CHECK-V8: ^
+
+[0xa2,0xff,0x42,0x0e]
+# CHECK-V81a: vqrdmlah.s32  q0, q1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0xa2,0xff,0x42,0x0e]
+# CHECK-V8: ^
+
+[0x91,0xef,0x42,0x0f]
+# CHECK-V81a: vqrdmlsh.s16  d0, d1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x91,0xef,0x42,0x0f]
+# CHECK-V8: ^
+
+[0xa1,0xef,0x42,0x0f]
+# CHECK-V81a: vqrdmlsh.s32  d0, d1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0xa1,0xef,0x42,0x0f]
+# CHECK-V8: ^
+
+[0x92,0xff,0x42,0x0f]
+# CHECK-V81a: vqrdmlsh.s16  q0, q1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x92,0xff,0x42,0x0f]
+# CHECK-V8: ^
+
+[0xa2,0xff,0x42,0x0f]
+# CHECK-V81a: vqrdmlsh.s32  q0, q1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0xa2,0xff,0x42,0x0f]
+# CHECK-V8: ^
+
+[0x10,0xb6]
+# CHECK-V81a: setpan #0
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x10,0xb6]
+# CHECK-V8: ^
+
+[0x18,0xb6]
+# CHECK-V81a: setpan #1
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x18,0xb6]
+# CHECK-V8: ^
diff --git a/test/MC/Disassembler/Hexagon/alu32_alu.txt b/test/MC/Disassembler/Hexagon/alu32_alu.txt
index 7fd400779292..4dde7df0759a 100644
--- a/test/MC/Disassembler/Hexagon/alu32_alu.txt
+++ b/test/MC/Disassembler/Hexagon/alu32_alu.txt
@@ -1,11 +1,15 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.1.1 ALU32/ALU
 
+# Add
 0xf1 0xc3 0x15 0xb0
 # CHECK: r17 = add(r21, #31)
 0x11 0xdf 0x15 0xf3
 # CHECK: r17 = add(r21, r31)
 0x11 0xdf 0x55 0xf6
 # CHECK: r17 = add(r21, r31):sat
+
+# And
 0xf1 0xc3 0x15 0x76
 # CHECK: r17 = and(r21, #31)
 0xf1 0xc3 0x95 0x76
@@ -20,16 +24,24 @@
 # CHECK: r17 = and(r21, ~r31)
 0x11 0xd5 0xbf 0xf1
 # CHECK: r17 = or(r21, ~r31)
+
+# Nop
 0x00 0xc0 0x00 0x7f
 # CHECK: nop
+
+# Subtract
 0xb1 0xc2 0x5f 0x76
 # CHECK: r17 = sub(#21, r31)
 0x11 0xdf 0x35 0xf3
 # CHECK: r17 = sub(r31, r21)
 0x11 0xdf 0xd5 0xf6
 # CHECK: r17 = sub(r31, r21):sat
+
+# Sign extend
 0x11 0xc0 0xbf 0x70
 # CHECK: r17 = sxtb(r31)
+
+# Transfer immediate
 0x15 0xc0 0x31 0x72
 # CHECK: r17.h = #21
 0x15 0xc0 0x31 0x71
@@ -38,7 +50,35 @@
 # CHECK: r17 = #32767
 0xf1 0xff 0xdf 0x78
 # CHECK: r17 = ##65535
+
+# Transfer register
 0x11 0xc0 0x75 0x70
 # CHECK: r17 = r21
+
+# Vector add halfwords
+0x11 0xdf 0x15 0xf6
+# CHECK: r17 = vaddh(r21, r31)
+0x11 0xdf 0x35 0xf6
+# CHECK: r17 = vaddh(r21, r31):sat
+0x11 0xdf 0x75 0xf6
+# CHECK: r17 = vadduh(r21, r31):sat
+
+# Vector average halfwords
+0x11 0xdf 0x15 0xf7
+# CHECK: r17 = vavgh(r21, r31)
+0x11 0xdf 0x35 0xf7
+# CHECK: r17 = vavgh(r21, r31):rnd
+0x11 0xdf 0x75 0xf7
+# CHECK: r17 = vnavgh(r31, r21)
+
+# Vector subtract halfwords
+0x11 0xdf 0x95 0xf6
+# CHECK: r17 = vsubh(r31, r21)
+0x11 0xdf 0xb5 0xf6
+# CHECK: r17 = vsubh(r31, r21):sat
+0x11 0xdf 0xf5 0xf6
+# CHECK: r17 = vsubuh(r31, r21):sat
+
+# Zero extend
 0x11 0xc0 0xd5 0x70
 # CHECK: r17 = zxth(r21)
diff --git a/test/MC/Disassembler/Hexagon/alu32_perm.txt b/test/MC/Disassembler/Hexagon/alu32_perm.txt
index 15977edbd6b7..a2953506c599 100644
--- a/test/MC/Disassembler/Hexagon/alu32_perm.txt
+++ b/test/MC/Disassembler/Hexagon/alu32_perm.txt
@@ -1,5 +1,7 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.1.2 ALU32/PERM
 
+# Combine words in to doublewords
 0x11 0xdf 0x95 0xf3
 # CHECK: r17 = combine(r31.h, r21.h)
 0x11 0xdf 0xb5 0xf3
@@ -16,6 +18,8 @@
 # CHECK: r17:16 = combine(r21, #31)
 0x10 0xdf 0x15 0xf5
 # CHECK: r17:16 = combine(r21, r31)
+
+# Mux
 0xf1 0xc3 0x75 0x73
 # CHECK: r17 = mux(p3, r21, #31)
 0xb1 0xc2 0xff 0x73
@@ -24,9 +28,13 @@
 # CHECK: r17 = mux(p3, #21, #31)
 0x71 0xdf 0x15 0xf4
 # CHECK: r17 = mux(p3, r21, r31)
+
+# Shift word by 16
 0x11 0xc0 0x15 0x70
 # CHECK: r17 = aslh(r21)
 0x11 0xc0 0x35 0x70
 # CHECK: r17 = asrh(r21)
+
+# Pack high and low halfwords
 0x10 0xdf 0x95 0xf5
 # CHECK: r17:16 = packhl(r21, r31)
diff --git a/test/MC/Disassembler/Hexagon/alu32_pred.txt b/test/MC/Disassembler/Hexagon/alu32_pred.txt
index 28a800359ea1..084b39d8cbf5 100644
--- a/test/MC/Disassembler/Hexagon/alu32_pred.txt
+++ b/test/MC/Disassembler/Hexagon/alu32_pred.txt
@@ -1,11 +1,51 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.1.3 ALU32/PRED
 
+# Conditional add
+0xf1 0xc3 0x75 0x74
+# CHECK: if (p3) r17 = add(r21, #31)
+0x03 0x40 0x45 0x85 0xf1 0xe3 0x75 0x74
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = add(r21, #31)
+0xf1 0xc3 0xf5 0x74
+# CHECK: if (!p3) r17 = add(r21, #31)
+0x03 0x40 0x45 0x85 0xf1 0xe3 0xf5 0x74
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = add(r21, #31)
 0x71 0xdf 0x15 0xfb
 # CHECK: if (p3) r17 = add(r21, r31)
+0x03 0x40 0x45 0x85 0x71 0xff 0x15 0xfb
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = add(r21, r31)
+0xf1 0xdf 0x15 0xfb
+# CHECK: if (!p3) r17 = add(r21, r31)
+0x03 0x40 0x45 0x85 0xf1 0xff 0x15 0xfb
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = add(r21, r31)
+
+# Conditional shift halfword
 0x11 0xe3 0x15 0x70
 # CHECK: if (p3) r17 = aslh(r21)
+0x03 0x40 0x45 0x85 0x11 0xe7 0x15 0x70
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = aslh(r21)
+0x11 0xeb 0x15 0x70
+# CHECK: if (!p3) r17 = aslh(r21)
+0x03 0x40 0x45 0x85 0x11 0xef 0x15 0x70
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = aslh(r21)
 0x11 0xe3 0x35 0x70
 # CHECK: if (p3) r17 = asrh(r21)
+0x03 0x40 0x45 0x85 0x11 0xe7 0x35 0x70
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = asrh(r21)
+0x11 0xeb 0x35 0x70
+# CHECK: if (!p3) r17 = asrh(r21)
+0x03 0x40 0x45 0x85 0x11 0xef 0x35 0x70
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = asrh(r21)
+
+# Conditional combine
 0x70 0xdf 0x15 0xfd
 # CHECK: if (p3) r17:16 = combine(r21, r31)
 0xf0 0xdf 0x15 0xfd
@@ -16,24 +56,74 @@
 0x03 0x40 0x45 0x85 0xf0 0xff 0x15 0xfd
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17:16 = combine(r21, r31)
-0x03 0x40 0x45 0x85 0x70 0xff 0x15 0xfd
-# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17:16 = combine(r21, r31)
-0x03 0x40 0x45 0x85 0xf0 0xff 0x15 0xfd
-# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17:16 = combine(r21, r31)
+
+# Conditional logical operations
 0x71 0xdf 0x15 0xf9
 # CHECK: if (p3) r17 = and(r21, r31)
+0xf1 0xdf 0x15 0xf9
+# CHECK: if (!p3) r17 = and(r21, r31)
+0x03 0x40 0x45 0x85 0x71 0xff 0x15 0xf9
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = and(r21, r31)
+0x03 0x40 0x45 0x85 0xf1 0xff 0x15 0xf9
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = and(r21, r31)
 0x71 0xdf 0x35 0xf9
 # CHECK: if (p3) r17 = or(r21, r31)
+0xf1 0xdf 0x35 0xf9
+# CHECK: if (!p3) r17 = or(r21, r31)
+0x03 0x40 0x45 0x85 0x71 0xff 0x35 0xf9
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = or(r21, r31)
+0x03 0x40 0x45 0x85 0xf1 0xff 0x35 0xf9
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = or(r21, r31)
 0x71 0xdf 0x75 0xf9
 # CHECK: if (p3) r17 = xor(r21, r31)
+0xf1 0xdf 0x75 0xf9
+# CHECK: if (!p3) r17 = xor(r21, r31)
+0x03 0x40 0x45 0x85 0x71 0xff 0x75 0xf9
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = xor(r21, r31)
+0x03 0x40 0x45 0x85 0xf1 0xff 0x75 0xf9
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = xor(r21, r31)
+
+# Conditional subtract
 0x71 0xdf 0x35 0xfb
 # CHECK: if (p3) r17 = sub(r31, r21)
+0xf1 0xdf 0x35 0xfb
+# CHECK: if (!p3) r17 = sub(r31, r21)
+0x03 0x40 0x45 0x85 0x71 0xff 0x35 0xfb
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = sub(r31, r21)
+0x03 0x40 0x45 0x85 0xf1 0xff 0x35 0xfb
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = sub(r31, r21)
+
+# Conditional sign extend
 0x11 0xe3 0xb5 0x70
 # CHECK: if (p3) r17 = sxtb(r21)
+0x11 0xeb 0xb5 0x70
+# CHECK: if (!p3) r17 = sxtb(r21)
+0x03 0x40 0x45 0x85 0x11 0xe7 0xb5 0x70
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = sxtb(r21)
+0x03 0x40 0x45 0x85 0x11 0xef 0xb5 0x70
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = sxtb(r21)
 0x11 0xe3 0xf5 0x70
 # CHECK: if (p3) r17 = sxth(r21)
+0x11 0xeb 0xf5 0x70
+# CHECK: if (!p3) r17 = sxth(r21)
+0x03 0x40 0x45 0x85 0x11 0xe7 0xf5 0x70
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = sxth(r21)
+0x03 0x40 0x45 0x85 0x11 0xef 0xf5 0x70
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = sxth(r21)
+
+# Conditional transfer
 0xb1 0xc2 0x60 0x7e
 # CHECK: if (p3) r17 = #21
 0xb1 0xc2 0xe0 0x7e
@@ -44,10 +134,42 @@
 0x03 0x40 0x45 0x85 0xb1 0xe2 0xe0 0x7e
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17 = #21
+
+# Conditional zero extend
 0x11 0xe3 0x95 0x70
 # CHECK: if (p3) r17 = zxtb(r21)
+0x11 0xeb 0x95 0x70
+# CHECK: if (!p3) r17 = zxtb(r21)
+0x03 0x40 0x45 0x85 0x11 0xe7 0x95 0x70
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = zxtb(r21)
+0x03 0x40 0x45 0x85 0x11 0xef 0x95 0x70
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = zxtb(r21)
 0x11 0xe3 0xd5 0x70
 # CHECK: if (p3) r17 = zxth(r21)
+0x11 0xeb 0xd5 0x70
+# CHECK: if (!p3) r17 = zxth(r21)
+0x03 0x40 0x45 0x85 0x11 0xe7 0xd5 0x70
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = zxth(r21)
+0x03 0x40 0x45 0x85 0x11 0xef 0xd5 0x70
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = zxth(r21)
+
+# Compare
+0xe3 0xc3 0x15 0x75
+# CHECK: p3 = cmp.eq(r21, #31)
+0xf3 0xc3 0x15 0x75
+# CHECK: p3 = !cmp.eq(r21, #31)
+0xe3 0xc3 0x55 0x75
+# CHECK: p3 = cmp.gt(r21, #31)
+0xf3 0xc3 0x55 0x75
+# CHECK: p3 = !cmp.gt(r21, #31)
+0xe3 0xc3 0x95 0x75
+# CHECK: p3 = cmp.gtu(r21, #31)
+0xf3 0xc3 0x95 0x75
+# CHECK: p3 = !cmp.gtu(r21, #31)
 0x03 0xdf 0x15 0xf2
 # CHECK: p3 = cmp.eq(r21, r31)
 0x13 0xdf 0x15 0xf2
@@ -60,6 +182,8 @@
 # CHECK: p3 = cmp.gtu(r21, r31)
 0x13 0xdf 0x75 0xf2
 # CHECK: p3 = !cmp.gtu(r21, r31)
+
+# Compare to general register
 0xf1 0xe3 0x55 0x73
 # CHECK: r17 = cmp.eq(r21, #31)
 0xf1 0xe3 0x75 0x73
diff --git a/test/MC/Disassembler/Hexagon/cr.txt b/test/MC/Disassembler/Hexagon/cr.txt
index 89157156cffd..6cf2b5fda399 100644
--- a/test/MC/Disassembler/Hexagon/cr.txt
+++ b/test/MC/Disassembler/Hexagon/cr.txt
@@ -1,13 +1,19 @@
 # RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.2 CR
 
+# Corner detection acceleration
 0x93 0xe1 0x12 0x6b
 # CHECK: p3 = !fastcorner9(p2, p1)
 0x91 0xe3 0x02 0x6b
 # CHECK: p1 = fastcorner9(p2, p3)
+
+# Logical reductions on predicates
 0x01 0xc0 0x82 0x6b
 # CHECK: p1 = any8(p2)
 0x01 0xc0 0xa2 0x6b
 # CHECK: p1 = all8(p2)
+
+# Looping instructions
 0x08 0xc4 0x15 0x60
 # CHECK: loop0
 0x08 0xc4 0x35 0x60
@@ -16,6 +22,12 @@
 # CHECK: loop0
 0x68 0xc4 0x20 0x69
 # CHECK: loop1
+
+# Add to PC
+0x91 0xca 0x49 0x6a
+# CHECK: r17 = add(pc, #21)
+
+# Pipelined loop instructions
 0x08 0xc4 0xb5 0x60
 # CHECK: p3 = sp1loop0
 0x08 0xc4 0xd5 0x60
@@ -28,23 +40,21 @@
 # CHECK: p3 = sp2loop0
 0xa9 0xc4 0xe0 0x69
 # CHECK: p3 = sp3loop0
+
+# Logical operations on predicates
 0x01 0xc3 0x02 0x6b
 # CHECK: p1 = and(p3, p2)
 0xc1 0xc3 0x12 0x6b
 # CHECK: p1 = and(p2, and(p3, p3))
-0x01 0xc3 0x62 0x6b
-# CHECK: p1 = and(p3, !p2)
 0x01 0xc3 0x22 0x6b
 # CHECK: p1 = or(p3, p2)
 0xc1 0xc3 0x32 0x6b
 # CHECK: p1 = and(p2, or(p3, p3))
-0x01 0xc3 0xe2 0x6b
-# CHECK: p1 = or(p3, !p2)
-0x01 0xc2 0x43 0x6b
-# CHECK: p1 = xor(p3, p2)
+0x01 0xc3 0x42 0x6b
+# CHECK: p1 = xor(p2, p3)
 0xc1 0xc3 0x52 0x6b
 # CHECK: p1 = or(p2, and(p3, p3))
-0x01 0xc2 0x63 0x6b 
+0x01 0xc2 0x63 0x6b
 # CHECK: p1 = and(p2, !p3)
 0xc1 0xc3 0x72 0x6b
 # CHECK: p1 = or(p2, or(p3, p3))
@@ -60,6 +70,8 @@
 # CHECK: p1 = or(p2, !p3)
 0xc1 0xc3 0xf2 0x6b
 # CHECK: p1 = or(p2, or(p3, !p3))
+
+# User control register transfer
 0x0d 0xc0 0x35 0x62
 # CHECK: cs1 = r21
 0x11 0xc0 0x0d 0x6a
diff --git a/test/MC/Disassembler/Hexagon/j.txt b/test/MC/Disassembler/Hexagon/j.txt
index c14d0341547c..0c2cc7a4cf34 100644
--- a/test/MC/Disassembler/Hexagon/j.txt
+++ b/test/MC/Disassembler/Hexagon/j.txt
@@ -1,11 +1,15 @@
 # RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.4 J
 
+# Call subroutine
 0x22 0xc0 0x00 0x5a
 # CHECK: call
 0x22 0xc3 0x00 0x5d
 # CHECK: if (p3) call
 0x22 0xc3 0x20 0x5d
 # CHECK: if (!p3) call
+
+# Compare and jump
 0x00 0xc0 0x89 0x11
 # CHECK: p0 = cmp.eq(r9,#-1); if (p0.new) jump:nt
 0x00 0xc1 0x89 0x11
@@ -150,6 +154,48 @@
 # CHECK: p0 = cmp.gtu(r9, r13); if (!p0.new) jump:t
 0x00 0xfd 0x49 0x15
 # CHECK: p1 = cmp.gtu(r9, r13); if (!p1.new) jump:t
+
+# Jump to address
+0x22 0xc0 0x00 0x58
+# CHECK: jump
+0x22 0xc3 0x00 0x5c
+# CHECK: if (p3) jump
+0x22 0xc3 0x20 0x5c
+# CHECK: if (!p3) jump
+
+# Jump to address conditioned on new predicate
+0x03 0x40 0x45 0x85 0x00 0xcb 0x00 0x5c
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) jump:nt
+0x03 0x40 0x45 0x85 0x00 0xdb 0x00 0x5c
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) jump:t
+0x03 0x40 0x45 0x85 0x00 0xcb 0x20 0x5c
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) jump:nt
+0x03 0x40 0x45 0x85 0x00 0xdb 0x20 0x5c
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) jump:t
+
+# Jump to address conditioned on register value
+0x00 0xc0 0x11 0x61
+# CHECK: if (r17!=#0) jump:nt
+0x00 0xd0 0x11 0x61
+# CHECK: if (r17!=#0) jump:t
+0x00 0xc0 0x51 0x61
+# CHECK: if (r17>=#0) jump:nt
+0x00 0xd0 0x51 0x61
+# CHECK: if (r17>=#0) jump:t
+0x00 0xc0 0x91 0x61
+# CHECK: if (r17==#0) jump:nt
+0x00 0xd0 0x91 0x61
+# CHECK: if (r17==#0) jump:t
+0x00 0xc0 0xd1 0x61
+# CHECK: if (r17<=#0) jump:nt
+0x00 0xd0 0xd1 0x61
+# CHECK: if (r17<=#0) jump:t
+
+# Transfer and jump
 0x00 0xd5 0x09 0x16
 # CHECK: r9 = #21 ; jump
 0x00 0xc9 0x0d 0x17
diff --git a/test/MC/Disassembler/Hexagon/jr.txt b/test/MC/Disassembler/Hexagon/jr.txt
index 880a3399297b..c9deb5fdd7e3 100644
--- a/test/MC/Disassembler/Hexagon/jr.txt
+++ b/test/MC/Disassembler/Hexagon/jr.txt
@@ -1,11 +1,19 @@
 # RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.3 JR
 
+# Call subroutine from register
 0x00 0xc0 0xb5 0x50
 # CHECK: callr r21
 0x00 0xc1 0x15 0x51
 # CHECK: if (p1) callr r21
 0x00 0xc3 0x35 0x51
 # CHECK: if (!p3) callr r21
+
+# Hint an indirect jump address
+0x00 0xc0 0xb5 0x52
+# CHECK: hintjr(r21)
+
+# Jump to address from register
 0x00 0xc0 0x95 0x52
 # CHECK: jumpr r21
 0x00 0xc1 0x55 0x53
diff --git a/test/MC/Disassembler/Hexagon/ld.txt b/test/MC/Disassembler/Hexagon/ld.txt
index 9440480e4e31..15c23b644886 100644
--- a/test/MC/Disassembler/Hexagon/ld.txt
+++ b/test/MC/Disassembler/Hexagon/ld.txt
@@ -1,5 +1,7 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.5 LD
 
+# Load doubleword
 0x90 0xff 0xd5 0x3a
 # CHECK: r17:16 = memd(r21 + r31<<#3)
 0x10 0xc5 0xc0 0x49
@@ -14,6 +16,8 @@
 # CHECK: r17:16 = memd(r21++m1)
 0x10 0xe0 0xd5 0x9f
 # CHECK: r17:16 = memd(r21 ++ m1:brev)
+
+# Load doubleword conditionally
 0xf0 0xff 0xd5 0x30
 # CHECK: if (p3) r17:16 = memd(r21+r31<<#3)
 0xf0 0xff 0xd5 0x31
@@ -45,6 +49,7 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17:16 = memd(r21++#40)
 
+# Load byte
 0x91 0xff 0x15 0x3a
 # CHECK: r17 = memb(r21 + r31<<#3)
 0xb1 0xc2 0x00 0x49
@@ -61,6 +66,8 @@
 # CHECK: r17 = memb(r21++m1)
 0x11 0xe0 0x15 0x9f
 # CHECK: r17 = memb(r21 ++ m1:brev)
+
+# Load byte conditionally
 0xf1 0xff 0x15 0x30
 # CHECK: if (p3) r17 = memb(r21+r31<<#3)
 0xf1 0xff 0x15 0x31
@@ -92,6 +99,7 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17 = memb(r21++#5)
 
+# Load halfword
 0x91 0xff 0x55 0x3a
 # CHECK: r17 = memh(r21 + r31<<#3)
 0x51 0xc5 0x40 0x49
@@ -108,6 +116,8 @@
 # CHECK: r17 = memh(r21++m1)
 0x11 0xe0 0x55 0x9f
 # CHECK: r17 = memh(r21 ++ m1:brev)
+
+# Load halfword conditionally
 0xf1 0xff 0x55 0x30
 # CHECK: if (p3) r17 = memh(r21+r31<<#3)
 0xf1 0xff 0x55 0x31
@@ -129,6 +139,7 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17 = memh(r21++#10)
 
+# Load unsigned byte
 0x91 0xff 0x35 0x3a
 # CHECK: r17 = memub(r21 + r31<<#3)
 0xb1 0xc2 0x20 0x49
@@ -145,6 +156,8 @@
 # CHECK: r17 = memub(r21++m1)
 0x11 0xe0 0x35 0x9f
 # CHECK: r17 = memub(r21 ++ m1:brev)
+
+# Load unsigned byte conditionally
 0xf1 0xff 0x35 0x30
 # CHECK: if (p3) r17 = memub(r21+r31<<#3)
 0xf1 0xff 0x35 0x31
@@ -176,6 +189,7 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17 = memub(r21++#5)
 
+# Load unsigned halfword
 0x91 0xff 0x75 0x3a
 # CHECK: r17 = memuh(r21 + r31<<#3)
 0x51 0xc5 0x60 0x49
@@ -192,6 +206,8 @@
 # CHECK: r17 = memuh(r21++m1)
 0x11 0xe0 0x75 0x9f
 # CHECK: r17 = memuh(r21 ++ m1:brev)
+
+# Load unsigned halfword conditionally
 0xf1 0xff 0x75 0x30
 # CHECK: if (p3) r17 = memuh(r21+r31<<#3)
 0xf1 0xff 0x75 0x31
@@ -223,6 +239,7 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17 = memuh(r21++#10)
 
+# Load word
 0x91 0xff 0x95 0x3a
 # CHECK: r17 = memw(r21 + r31<<#3)
 0x91 0xc2 0x80 0x49
@@ -239,6 +256,8 @@
 # CHECK: r17 = memw(r21++m1)
 0x11 0xe0 0x95 0x9f
 # CHECK: r17 = memw(r21 ++ m1:brev)
+
+# Load word conditionally
 0xf1 0xff 0x95 0x30
 # CHECK: if (p3) r17 = memw(r21+r31<<#3)
 0xf1 0xff 0x95 0x31
@@ -270,8 +289,11 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17 = memw(r21++#20)
 
+# Deallocate stack frame
 0x1e 0xc0 0x1e 0x90
 # CHECK: deallocframe
+
+# Deallocate stack frame and return
 0x1e 0xc0 0x1e 0x96
 # CHECK: dealloc_return
 0x03 0x40 0x45 0x85 0x1e 0xcb 0x1e 0x96
@@ -290,3 +312,53 @@
 0x03 0x40 0x45 0x85 0x1e 0xfb 0x1e 0x96
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) dealloc_return:t
+
+# Load and unpack bytes to halfwords
+0xf1 0xc3 0x35 0x90
+# CHECK: r17 = membh(r21 + #62)
+0xf1 0xc3 0x75 0x90
+# CHECK: r17 = memubh(r21 + #62)
+0xf0 0xc3 0xb5 0x90
+# CHECK: r17:16 = memubh(r21 + #124)
+0xf0 0xc3 0xf5 0x90
+# CHECK: r17:16 = membh(r21 + #124)
+0xb1 0xe0 0x35 0x98
+# CHECK: r17 = membh(r21 ++ #10:circ(m1))
+0x11 0xe2 0x35 0x98
+# CHECK: r17 = membh(r21 ++ I:circ(m1))
+0xb1 0xe0 0x75 0x98
+# CHECK: r17 = memubh(r21 ++ #10:circ(m1))
+0x11 0xe2 0x75 0x98
+# CHECK: r17 = memubh(r21 ++ I:circ(m1))
+0xb0 0xe0 0xf5 0x98
+# CHECK: r17:16 = membh(r21 ++ #20:circ(m1))
+0x10 0xe2 0xf5 0x98
+# CHECK: r17:16 = membh(r21 ++ I:circ(m1))
+0xb0 0xe0 0xb5 0x98
+# CHECK: r17:16 = memubh(r21 ++ #20:circ(m1))
+0x10 0xe2 0xb5 0x98
+# CHECK: r17:16 = memubh(r21 ++ I:circ(m1))
+0xb1 0xc0 0x35 0x9a
+# CHECK: r17 = membh(r21++#10)
+0xb1 0xc0 0x75 0x9a
+# CHECK: r17 = memubh(r21++#10)
+0xb0 0xc0 0xb5 0x9a
+# CHECK: r17:16 = memubh(r21++#20)
+0xb0 0xc0 0xf5 0x9a
+# CHECK: r17:16 = membh(r21++#20)
+0x11 0xe0 0x35 0x9c
+# CHECK: r17 = membh(r21++m1)
+0x11 0xe0 0x75 0x9c
+# CHECK: r17 = memubh(r21++m1)
+0x10 0xe0 0xf5 0x9c
+# CHECK: r17:16 = membh(r21++m1)
+0x10 0xe0 0xb5 0x9c
+# CHECK: r17:16 = memubh(r21++m1)
+0x11 0xe0 0x35 0x9e
+# CHECK: r17 = membh(r21 ++ m1:brev)
+0x11 0xe0 0x75 0x9e
+# CHECK: r17 = memubh(r21 ++ m1:brev)
+0x10 0xe0 0xb5 0x9e
+# CHECK: r17:16 = memubh(r21 ++ m1:brev)
+0x10 0xe0 0xf5 0x9e
+# CHECK: r17:16 = membh(r21 ++ m1:brev)
diff --git a/test/MC/Disassembler/Hexagon/memop.txt b/test/MC/Disassembler/Hexagon/memop.txt
index 7c944121ddcc..47dfd9338c6d 100644
--- a/test/MC/Disassembler/Hexagon/memop.txt
+++ b/test/MC/Disassembler/Hexagon/memop.txt
@@ -1,5 +1,7 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.6 MEMOP
 
+# Operation on memory byte
 0x95 0xd9 0x11 0x3e
 # CHECK: memb(r17+#51) += r21
 0xb5 0xd9 0x11 0x3e
@@ -16,6 +18,8 @@
 # CHECK: memb(r17+#51) = clrbit(#21)
 0xf5 0xd9 0x11 0x3f
 # CHECK: memb(r17+#51) = setbit(#21)
+
+# Operation on memory halfword
 0x95 0xd9 0x31 0x3e
 # CHECK: memh(r17+#102) += r21
 0xb5 0xd9 0x31 0x3e
@@ -32,6 +36,8 @@
 # CHECK: memh(r17+#102) = clrbit(#21)
 0xf5 0xd9 0x31 0x3f
 # CHECK: memh(r17+#102) = setbit(#21)
+
+# Operation on memory word
 0x95 0xd9 0x51 0x3e
 # CHECK: memw(r17+#204) += r21
 0xb5 0xd9 0x51 0x3e
diff --git a/test/MC/Disassembler/Hexagon/nv_j.txt b/test/MC/Disassembler/Hexagon/nv_j.txt
index e5cee4d44384..a6773c3f3c56 100644
--- a/test/MC/Disassembler/Hexagon/nv_j.txt
+++ b/test/MC/Disassembler/Hexagon/nv_j.txt
@@ -1,5 +1,7 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.7.1 NV/J
 
+# Jump to address conditioned on new register value
 0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x20
 # CHECK: r17 = r17
 # CHECK-NEXT: if (cmp.eq(r2.new, r21)) jump:nt
diff --git a/test/MC/Disassembler/Hexagon/nv_st.txt b/test/MC/Disassembler/Hexagon/nv_st.txt
index 830570987340..ef49455b80b1 100644
--- a/test/MC/Disassembler/Hexagon/nv_st.txt
+++ b/test/MC/Disassembler/Hexagon/nv_st.txt
@@ -1,17 +1,30 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.7.2 NV/ST
 
+# Store new-value byte
 0x1f 0x40 0x7f 0x70 0x82 0xf5 0xb1 0x3b
 # CHECK: r31 = r31
 # CHECK-NEXT: memb(r17 + r21<<#3) = r2.new
 0x1f 0x40 0x7f 0x70 0x15 0xc2 0xb1 0xa1
 # CHECK: r31 = r31
 # CHECK-NEXT: memb(r17+#21) = r2.new
+0x1f 0x40 0x7f 0x70 0x02 0xe2 0xb1 0xa9
+# CHECK: r31 = r31
+# CHECK-NEXT: memb(r17 ++ I:circ(m1)) = r2.new
+0x1f 0x40 0x7f 0x70 0x28 0xe2 0xb1 0xa9
+# CHECK: r31 = r31
+# CHECK-NEXT: memb(r17 ++ #5:circ(m1)) = r2.new
 0x1f 0x40 0x7f 0x70 0x28 0xc2 0xb1 0xab
 # CHECK: r31 = r31
 # CHECK-NEXT: memb(r17++#5) = r2.new
 0x1f 0x40 0x7f 0x70 0x00 0xe2 0xb1 0xad
 # CHECK: r31 = r31
 # CHECK-NEXT: memb(r17++m1) = r2.new
+0x1f 0x40 0x7f 0x70 0x00 0xe2 0xb1 0xaf
+# CHECK: r31 = r31
+# CHECK-NEXT: memb(r17 ++ m1:brev) = r2.new
+
+# Store new-value byte conditionally
 0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x34
 # CHECK: r31 = r31
 # CHECK-NEXT: if (p3) memb(r17+r21<<#3) = r2.new
@@ -55,18 +68,30 @@
 # CHECK-NEXT: r31 = r31
 # CHECK-NEXT: if (!p3.new) memb(r17++#5) = r2.new
 
+# Store new-value halfword
 0x1f 0x40 0x7f 0x70 0x8a 0xf5 0xb1 0x3b
 # CHECK: r31 = r31
 # CHECK-NEXT: memh(r17 + r21<<#3) = r2.new
 0x1f 0x40 0x7f 0x70 0x15 0xca 0xb1 0xa1
 # CHECK: r31 = r31
 # CHECK-NEXT: memh(r17+#42) = r2.new
+0x1f 0x40 0x7f 0x70 0x02 0xea 0xb1 0xa9
+# CHECK: r31 = r31
+# CHECK-NEXT: memh(r17 ++ I:circ(m1)) = r2.new
+0x1f 0x40 0x7f 0x70 0x28 0xea 0xb1 0xa9
+# CHECK: r31 = r31
+# CHECK-NEXT: memh(r17 ++ #10:circ(m1)) = r2.new
 0x1f 0x40 0x7f 0x70 0x28 0xca 0xb1 0xab
 # CHECK: r31 = r31
 # CHECK-NEXT: memh(r17++#10) = r2.new
 0x1f 0x40 0x7f 0x70 0x00 0xea 0xb1 0xad
 # CHECK: r31 = r31
 # CHECK-NEXT: memh(r17++m1) = r2.new
+0x1f 0x40 0x7f 0x70 0x00 0xea 0xb1 0xaf
+# CHECK: r31 = r31
+# CHECK-NEXT: memh(r17 ++ m1:brev) = r2.new
+
+# Store new-value halfword conditionally
 0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x34
 # CHECK: r31 = r31
 # CHECK-NEXT: if (p3) memh(r17+r21<<#3) = r2.new
@@ -110,18 +135,30 @@
 # CHECK-NEXT: r31 = r31
 # CHECK-NEXT: if (!p3.new) memh(r17++#10) = r2.new
 
+# Store new-value word
 0x1f 0x40 0x7f 0x70 0x92 0xf5 0xb1 0x3b
 # CHECK: r31 = r31
 # CHECK-NEXT: memw(r17 + r21<<#3) = r2.new
 0x1f 0x40 0x7f 0x70 0x15 0xd2 0xb1 0xa1
 # CHECK: r31 = r31
 # CHECK-NEXT: memw(r17+#84) = r2.new
+0x1f 0x40 0x7f 0x70 0x28 0xf2 0xb1 0xa9
+# CHECK: r31 = r31
+# CHECK-NEXT: memw(r17 ++ #20:circ(m1)) = r2.new
+0x1f 0x40 0x7f 0x70 0x02 0xf2 0xb1 0xa9
+# CHECK: r31 = r31
+# CHECK-NEXT: memw(r17 ++ I:circ(m1)) = r2.new
 0x1f 0x40 0x7f 0x70 0x28 0xd2 0xb1 0xab
 # CHECK: r31 = r31
 # CHECK-NEXT: memw(r17++#20) = r2.new
 0x1f 0x40 0x7f 0x70 0x00 0xf2 0xb1 0xad
 # CHECK: r31 = r31
 # CHECK-NEXT: memw(r17++m1) = r2.new
+0x1f 0x40 0x7f 0x70 0x00 0xf2 0xb1 0xaf
+# CHECK: r31 = r31
+# CHECK-NEXT: memw(r17 ++ m1:brev) = r2.new
+
+# Store new-value word conditionally
 0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x34
 # CHECK: r31 = r31
 # CHECK-NEXT: if (p3) memw(r17+r21<<#3) = r2.new
diff --git a/test/MC/Disassembler/Hexagon/st.txt b/test/MC/Disassembler/Hexagon/st.txt
index 4d1a491b344a..3b809d3465a8 100644
--- a/test/MC/Disassembler/Hexagon/st.txt
+++ b/test/MC/Disassembler/Hexagon/st.txt
@@ -1,5 +1,7 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.8 ST
 
+# Store doubleword
 0x9e 0xf5 0xd1 0x3b
 # CHECK: memd(r17 + r21<<#3) = r31:30
 0x28 0xd4 0xc0 0x48
@@ -16,6 +18,8 @@
 # CHECK: memd(r17++m1) = r21:20
 0x00 0xf4 0xd1 0xaf
 # CHECK: memd(r17 ++ m1:brev) = r21:20
+
+# Store doubleword conditionally
 0xfe 0xf5 0xd1 0x34
 # CHECK: if (p3) memd(r17+r21<<#3) = r31:30
 0xfe 0xf5 0xd1 0x35
@@ -47,6 +51,7 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) memd(r17++#40) = r21:20
 
+# Store byte
 0x9f 0xf5 0x11 0x3b
 # CHECK: memb(r17 + r21<<#3) = r31
 0x9f 0xca 0x11 0x3c
@@ -65,6 +70,8 @@
 # CHECK: memb(r17++m1) = r21
 0x00 0xf5 0x11 0xaf
 # CHECK: memb(r17 ++ m1:brev) = r21
+
+# Store byte conditionally
 0xff 0xf5 0x11 0x34
 # CHECK: if (p3) memb(r17+r21<<#3) = r31
 0xff 0xf5 0x11 0x35
@@ -106,6 +113,7 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) memb(r17++#5) = r21
 
+# Store halfword
 0x9f 0xf5 0x51 0x3b
 # CHECK: memh(r17 + r21<<#3) = r31
 0x9f 0xf5 0x71 0x3b
@@ -140,6 +148,8 @@
 # CHECK: memh(r17 ++ m1:brev) = r21
 0x00 0xf5 0x71 0xaf
 # CHECK: memh(r17 ++ m1:brev) = r21.h
+
+# Store halfword conditionally
 0xff 0xf5 0x51 0x34
 # CHECK: if (p3) memh(r17+r21<<#3) = r31
 0xff 0xf5 0x71 0x34
@@ -211,6 +221,7 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) memh(r17++#10) = r21.h
 
+# Store word
 0x9f 0xf5 0x91 0x3b
 # CHECK: memw(r17 + r21<<#3) = r31
 0x9f 0xca 0x51 0x3c
@@ -229,6 +240,8 @@
 # CHECK: memw(r17++m1) = r21
 0x00 0xf5 0x91 0xaf
 # CHECK: memw(r17 ++ m1:brev) = r21
+
+# Store word conditionally
 0xff 0xf5 0x91 0x34
 # CHECK: if (p3) memw(r17+r21<<#3) = r31
 0xff 0xf5 0x91 0x35
@@ -270,5 +283,6 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (p3.new) memw(r17++#20) = r21
 
+# Allocate stack frame
 0x1f 0xc0 0x9d 0xa0
 # CHECK: allocframe(#248)
\ No newline at end of file
diff --git a/test/MC/Disassembler/Hexagon/system_user.txt b/test/MC/Disassembler/Hexagon/system_user.txt
index 51d082a9e180..d55a94e939b5 100644
--- a/test/MC/Disassembler/Hexagon/system_user.txt
+++ b/test/MC/Disassembler/Hexagon/system_user.txt
@@ -1,12 +1,26 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.9.1 SYSTEM/USER
 
+# Load locked
 0x11 0xc0 0x15 0x92
 # CHECK: r17 = memw_locked(r21)
 0x10 0xd0 0x15 0x92
 # CHECK: r17:16 = memd_locked(r21)
+
+# Store conditional
+0x03 0xd5 0xb1 0xa0
+# CHECK: memw_locked(r17, p3) = r21
+0x03 0xd4 0xf1 0xa0
+# CHECK: memd_locked(r17, p3) = r21:20
+
+# Memory barrier
 0x00 0xc0 0x00 0xa8
 # CHECK: barrier
+
+# Data cache prefetch
 0x15 0xc0 0x11 0x94
 # CHECK: dcfetch(r17 + #168)
+
+# Send value to ETM trace
 0x00 0xc0 0x51 0x62
 # CHECK: trace(r17)
diff --git a/test/MC/Disassembler/Hexagon/xtype_alu.txt b/test/MC/Disassembler/Hexagon/xtype_alu.txt
index d39260c63228..03d0f0518a3d 100644
--- a/test/MC/Disassembler/Hexagon/xtype_alu.txt
+++ b/test/MC/Disassembler/Hexagon/xtype_alu.txt
@@ -1,11 +1,15 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.10.1 XTYPE/ALU
 
+# Absolute value doubleword
 0xd0 0xc0 0x94 0x80
 # CHECK: r17:16 = abs(r21:20)
 0x91 0xc0 0x95 0x8c
 # CHECK: r17 = abs(r21)
 0xb1 0xc0 0x95 0x8c
 # CHECK: r17 = abs(r21):sat
+
+# Add and accumulate
 0xff 0xd1 0x35 0xdb
 # CHECK: r17 = add(r21, add(r31, #23))
 0xff 0xd1 0xb5 0xdb
@@ -18,8 +22,18 @@
 # CHECK: r17 += add(r21, r31)
 0x31 0xdf 0x95 0xef
 # CHECK: r17 -= add(r21, r31)
+
+# Add doublewords
 0xf0 0xde 0x14 0xd3
 # CHECK: r17:16 = add(r21:20, r31:30)
+0xb0 0xde 0x74 0xd3
+# CHECK: r17:16 = add(r21:20, r31:30):sat
+0xd0 0xde 0x74 0xd3
+# CHECK: r17:16 = add(r21:20, r31:30):raw:lo
+0xf0 0xde 0x74 0xd3
+# CHECK: r17:16 = add(r21:20, r31:30):raw:hi
+
+# Add halfword
 0x11 0xd5 0x1f 0xd5
 # CHECK: r17 = add(r21.l, r31.l)
 0x51 0xd5 0x1f 0xd5
@@ -44,20 +58,16 @@
 # CHECK: r17 = add(r21.h, r31.l):sat:<<16
 0xf1 0xd5 0x5f 0xd5
 # CHECK: r17 = add(r21.h, r31.h):sat:<<16
+
+# Add or subtract doublewords with carry
 0x70 0xde 0xd4 0xc2
 # CHECK: r17:16 = add(r21:20, r31:30, p3):carry
 0x70 0xde 0xf4 0xc2
 # CHECK: r17:16 = sub(r21:20, r31:30, p3):carry
+
+# Logical doublewords
 0x90 0xc0 0x94 0x80
 # CHECK: r17:16 = not(r21:20)
-0xf0 0xde 0x14 0xd3
-# CHECK: r17:16 = add(r21:20, r31:30)
-0xb0 0xde 0x74 0xd3
-# CHECK: r17:16 = add(r21:20, r31:30):sat
-0xd0 0xde 0x74 0xd3
-# CHECK: r17:16 = add(r21:20, r31:30):raw:lo
-0xf0 0xde 0x74 0xd3
-# CHECK: r17:16 = add(r21:20, r31:30):raw:hi
 0x10 0xde 0xf4 0xd3
 # CHECK: r17:16 = and(r21:20, r31:30)
 0x30 0xd4 0xfe 0xd3
@@ -66,8 +76,14 @@
 # CHECK: r17:16 = or(r21:20, r31:30)
 0x70 0xd4 0xfe 0xd3
 # CHECK: r17:16 = or(r21:20, ~r31:30)
+0x90 0xde 0xf4 0xd3
+# CHECK: r17:16 = xor(r21:20, r31:30)
+
+# Logical-logical doublewords
 0x10 0xde 0x94 0xca
 # CHECK: r17:16 ^= xor(r21:20, r31:30)
+
+# Logical-logical words
 0xf1 0xc3 0x15 0xda
 # CHECK: r17 |= and(r21, #31)
 0xf5 0xc3 0x51 0xda
@@ -98,28 +114,44 @@
 # CHECK: r17 ^= and(r21, r31)
 0x71 0xdf 0xd5 0xef
 # CHECK: r17 ^= or(r21, r31)
+
+# Maximum words
 0x11 0xdf 0xd5 0xd5
 # CHECK: r17 = max(r21, r31)
 0x91 0xdf 0xd5 0xd5
 # CHECK: r17 = maxu(r21, r31)
+
+# Maximum doublewords
 0x90 0xde 0xd4 0xd3
 # CHECK: r17:16 = max(r21:20, r31:30)
 0xb0 0xde 0xd4 0xd3
 # CHECK: r17:16 = maxu(r21:20, r31:30)
+
+# Minimum words
 0x11 0xd5 0xbf 0xd5
 # CHECK: r17 = min(r21, r31)
 0x91 0xd5 0xbf 0xd5
 # CHECK: r17 = minu(r21, r31)
+
+# Minimum doublewords
 0xd0 0xd4 0xbe 0xd3
 # CHECK: r17:16 = min(r21:20, r31:30)
 0xf0 0xd4 0xbe 0xd3
 # CHECK: r17:16 = minu(r21:20, r31:30)
+
+# Module wrap
 0xf1 0xdf 0xf5 0xd3
 # CHECK: r17 = modwrap(r21, r31)
+
+# Negate
 0xb0 0xc0 0x94 0x80
 # CHECK: r17:16 = neg(r21:20)
 0xd1 0xc0 0x95 0x8c
 # CHECK: r17 = neg(r21):sat
+
+# Round
+0x31 0xc0 0xd4 0x88
+# CHECK: r17 = round(r21:20):sat
 0x11 0xdf 0xf5 0x8c
 # CHECK: r17 = cround(r21, #31)
 0x91 0xdf 0xf5 0x8c
@@ -132,8 +164,16 @@
 # CHECK: r17 = round(r21, r31)
 0xd1 0xdf 0xd5 0xc6
 # CHECK: r17 = round(r21, r31):sat
+
+# Subtract doublewords
+0xf0 0xd4 0x3e 0xd3
+# CHECK: r17:16 = sub(r21:20, r31:30)
+
+# Subtract and accumulate words
 0x71 0xd5 0x1f 0xef
 # CHECK: r17 += sub(r21, r31)
+
+# Subtract halfword
 0x11 0xd5 0x3f 0xd5
 # CHECK: r17 = sub(r21.l, r31.l)
 0x51 0xd5 0x3f 0xd5
@@ -158,7 +198,198 @@
 # CHECK: r17 = sub(r21.h, r31.l):sat:<<16
 0xf1 0xd5 0x7f 0xd5
 # CHECK: r17 = sub(r21.h, r31.h):sat:<<16
+
+# Sign extend word to doubleword
 0x10 0xc0 0x55 0x84
 # CHECK: r17:16 = sxtw(r21)
-0x90 0xde 0xf4 0xd3
-# CHECK: r17:16 = xor(r21:20, r31:30)
+
+# Vector absolute value halfwords
+0x90 0xc0 0x54 0x80
+# CHECK: r17:16 = vabsh(r21:20)
+0xb0 0xc0 0x54 0x80
+# CHECK: r17:16 = vabsh(r21:20):sat
+
+# Vector absolute value words
+0xd0 0xc0 0x54 0x80
+# CHECK: r17:16 = vabsw(r21:20)
+0xf0 0xc0 0x54 0x80
+# CHECK: r17:16 = vabsw(r21:20):sat
+
+# Vector absolute difference halfwords
+0x10 0xd4 0x7e 0xe8
+# CHECK: r17:16 = vabsdiffh(r21:20, r31:30)
+
+# Vector absolute difference words
+0x10 0xd4 0x3e 0xe8
+# CHECK: r17:16 = vabsdiffw(r21:20, r31:30)
+
+# Vector add halfwords
+0x50 0xde 0x14 0xd3
+# CHECK: r17:16 = vaddh(r21:20, r31:30)
+0x70 0xde 0x14 0xd3
+# CHECK: r17:16 = vaddh(r21:20, r31:30):sat
+0x90 0xde 0x14 0xd3
+# CHECK: r17:16 = vadduh(r21:20, r31:30):sat
+
+# Vector add halfwords with saturate and pack to unsigned bytes
+0x31 0xde 0x54 0xc1
+# CHECK: r17 = vaddhub(r21:20, r31:30):sat
+
+# Vector reduce add unsigned bytes
+0x30 0xde 0x54 0xe8
+# CHECK: r17:16 = vraddub(r21:20, r31:30)
+0x30 0xde 0x54 0xea
+# CHECK: r17:16 += vraddub(r21:20, r31:30)
+
+# Vector reduce add halfwords
+0x31 0xde 0x14 0xe9
+# CHECK: r17 = vradduh(r21:20, r31:30)
+0xf1 0xde 0x34 0xe9
+# CHECK: r17 = vraddh(r21:20, r31:30)
+
+# Vector add bytes
+0x10 0xde 0x14 0xd3
+# CHECK: r17:16 = vaddub(r21:20, r31:30)
+0x30 0xde 0x14 0xd3
+# CHECK: r17:16 = vaddub(r21:20, r31:30):sat
+
+# Vector add words
+0xb0 0xde 0x14 0xd3
+# CHECK: r17:16 = vaddw(r21:20, r31:30)
+0xd0 0xde 0x14 0xd3
+# CHECK: r17:16 = vaddw(r21:20, r31:30):sat
+
+# Vector average halfwords
+0x50 0xde 0x54 0xd3
+# CHECK: r17:16 = vavgh(r21:20, r31:30)
+0x70 0xde 0x54 0xd3
+# CHECK: r17:16 = vavgh(r21:20, r31:30):rnd
+0x90 0xde 0x54 0xd3
+# CHECK: r17:16 = vavgh(r21:20, r31:30):crnd
+0xb0 0xde 0x54 0xd3
+# CHECK: r17:16 = vavguh(r21:20, r31:30)
+0xd0 0xde 0x54 0xd3
+# CHECK: r17:16 = vavguh(r21:20, r31:30):rnd
+0x10 0xd4 0x9e 0xd3
+# CHECK: r17:16 = vnavgh(r21:20, r31:30)
+0x30 0xd4 0x9e 0xd3
+# CHECK: r17:16 = vnavgh(r21:20, r31:30):rnd:sat
+0x50 0xd4 0x9e 0xd3
+# CHECK: r17:16 = vnavgh(r21:20, r31:30):crnd:sat
+
+# Vector average unsigned bytes
+0x10 0xde 0x54 0xd3
+# CHECK: r17:16 = vavgub(r21:20, r31:30)
+0x30 0xde 0x54 0xd3
+# CHECK: r17:16 = vavgub(r21:20, r31:30):rnd
+
+# Vector average words
+0x10 0xde 0x74 0xd3
+# CHECK: r17:16 = vavgw(r21:20, r31:30)
+0x30 0xde 0x74 0xd3
+# CHECK: r17:16 = vavgw(r21:20, r31:30):rnd
+0x50 0xde 0x74 0xd3
+# CHECK: r17:16 = vavgw(r21:20, r31:30):crnd
+0x70 0xde 0x74 0xd3
+# CHECK: r17:16 = vavguw(r21:20, r31:30)
+0x90 0xde 0x74 0xd3
+# CHECK: r17:16 = vavguw(r21:20, r31:30):rnd
+0x70 0xd4 0x9e 0xd3
+# CHECK: r17:16 = vnavgw(r21:20, r31:30)
+0x90 0xd4 0x9e 0xd3
+# CHECK: r17:16 = vnavgw(r21:20, r31:30):rnd:sat
+0xd0 0xd4 0x9e 0xd3
+# CHECK: r17:16 = vnavgw(r21:20, r31:30):crnd:sat
+
+# Vector conditional negate
+0x50 0xdf 0xd4 0xc3
+# CHECK: r17:16 = vcnegh(r21:20, r31)
+
+0xf0 0xff 0x34 0xcb
+# CHECK: r17:16 += vrcnegh(r21:20, r31)
+
+# Vector maximum bytes
+0x10 0xd4 0xde 0xd3
+# CHECK: r17:16 = vmaxub(r21:20, r31:30)
+0xd0 0xd4 0xde 0xd3
+# CHECK: r17:16 = vmaxb(r21:20, r31:30)
+
+# Vector maximum halfwords
+0x30 0xd4 0xde 0xd3
+# CHECK: r17:16 = vmaxh(r21:20, r31:30)
+0x50 0xd4 0xde 0xd3
+# CHECK: r17:16 = vmaxuh(r21:20, r31:30)
+
+# Vector reduce maximum halfwords
+0x3f 0xd0 0x34 0xcb
+# CHECK: r17:16 = vrmaxh(r21:20, r31)
+0x3f 0xf0 0x34 0xcb
+# CHECK: r17:16 = vrmaxuh(r21:20, r31)
+
+# Vector reduce maximum words
+0x5f 0xd0 0x34 0xcb
+# CHECK: r17:16 = vrmaxw(r21:20, r31)
+0x5f 0xf0 0x34 0xcb
+# CHECK: r17:16 = vrmaxuw(r21:20, r31)
+
+# Vector maximum words
+0xb0 0xd4 0xbe 0xd3
+# CHECK: r17:16 = vmaxuw(r21:20, r31:30)
+0x70 0xd4 0xde 0xd3
+# CHECK: r17:16 = vmaxw(r21:20, r31:30)
+
+# Vector minimum bytes
+0x10 0xd4 0xbe 0xd3
+# CHECK: r17:16 = vminub(r21:20, r31:30)
+0xf0 0xd4 0xde 0xd3
+# CHECK: r17:16 = vminb(r21:20, r31:30)
+
+# Vector minimum halfwords
+0x30 0xd4 0xbe 0xd3
+# CHECK: r17:16 = vminh(r21:20, r31:30)
+0x50 0xd4 0xbe 0xd3
+# CHECK: r17:16 = vminuh(r21:20, r31:30)
+
+# Vector reduce minimum halfwords
+0xbf 0xd0 0x34 0xcb
+# CHECK: r17:16 = vrminh(r21:20, r31)
+0xbf 0xf0 0x34 0xcb
+# CHECK: r17:16 = vrminuh(r21:20, r31)
+
+# Vector reduce minimum words
+0xdf 0xd0 0x34 0xcb
+# CHECK: r17:16 = vrminw(r21:20, r31)
+0xdf 0xf0 0x34 0xcb
+# CHECK: r17:16 = vrminuw(r21:20, r31)
+
+# Vector minimum words
+0x70 0xd4 0xbe 0xd3
+# CHECK: r17:16 = vminw(r21:20, r31:30)
+0x90 0xd4 0xbe 0xd3
+# CHECK: r17:16 = vminuw(r21:20, r31:30)
+
+# Vector sum of absolute differences unsigned bytes
+0x50 0xde 0x54 0xe8
+# CHECK: r17:16 = vrsadub(r21:20, r31:30)
+0x50 0xde 0x54 0xea
+# CHECK: r17:16 += vrsadub(r21:20, r31:30)
+
+# Vector subtract halfwords
+0x50 0xd4 0x3e 0xd3
+# CHECK: r17:16 = vsubh(r21:20, r31:30)
+0x70 0xd4 0x3e 0xd3
+# CHECK: r17:16 = vsubh(r21:20, r31:30):sat
+0x90 0xd4 0x3e 0xd3
+# CHECK: r17:16 = vsubuh(r21:20, r31:30):sat
+
+# Vector subtract bytes
+0x10 0xd4 0x3e 0xd3
+# CHECK: r17:16 = vsubub(r21:20, r31:30)
+0x30 0xd4 0x3e 0xd3
+# CHECK: r17:16 = vsubub(r21:20, r31:30):sat
+
+# Vector subtract words
+0xb0 0xd4 0x3e 0xd3
+# CHECK: r17:16 = vsubw(r21:20, r31:30)
+0xd0 0xd4 0x3e 0xd3
+# CHECK: r17:16 = vsubw(r21:20, r31:30):sat
diff --git a/test/MC/Disassembler/Hexagon/xtype_bit.txt b/test/MC/Disassembler/Hexagon/xtype_bit.txt
index d1ec38e02183..89b6906afa92 100644
--- a/test/MC/Disassembler/Hexagon/xtype_bit.txt
+++ b/test/MC/Disassembler/Hexagon/xtype_bit.txt
@@ -1,5 +1,7 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.10.2 XTYPE/BIT
 
+# Count leading
 0x11 0xc0 0x54 0x88
 # CHECK: r17 = clb(r21:20)
 0x51 0xc0 0x54 0x88
@@ -20,8 +22,12 @@
 # CHECK: r17 = cl1(r21)
 0xf1 0xc0 0x15 0x8c
 # CHECK: r17 = normamt(r21)
+
+# Count population
 0x71 0xc0 0x74 0x88
 # CHECK: r17 = popcount(r21:20)
+
+# Count trailing
 0x51 0xc0 0xf4 0x88
 # CHECK: r17 = ct0(r21:20)
 0x91 0xc0 0xf4 0x88
@@ -30,6 +36,8 @@
 # CHECK: r17 = ct0(r21)
 0xb1 0xc0 0x55 0x8c
 # CHECK: r17 = ct1(r21)
+
+# Extract bitfield
 0xf0 0xdf 0x54 0x81
 # CHECK: r17:16 = extractu(r21:20, #31, #23)
 0xf0 0xdf 0x54 0x8a
@@ -46,6 +54,8 @@
 # CHECK: r17 = extractu(r21, r31:30)
 0x51 0xde 0x15 0xc9
 # CHECK: r17 = extract(r21, r31:30)
+
+# Insert bitfield
 0xf0 0xdf 0x54 0x83
 # CHECK: r17:16 = insert(r21:20, #31, #23)
 0xf1 0xdf 0x55 0x8f
@@ -54,18 +64,30 @@
 # CHECK: r17 = insert(r21, r31:30)
 0x10 0xde 0x14 0xca
 # CHECK: r17:16 = insert(r21:20, r31:30)
+
+# Interleave/deinterleave
 0x90 0xc0 0xd4 0x80
 # CHECK: r17:16 = deinterleave(r21:20)
 0xb0 0xc0 0xd4 0x80
 # CHECK: r17:16 = interleave(r21:20)
+
+# Linear feedback-shift iteration
 0xd0 0xde 0x94 0xc1
 # CHECK: r17:16 = lfs(r21:20, r31:30)
+
+# Masked parity
 0x11 0xde 0x14 0xd0
 # CHECK: r17 = parity(r21:20, r31:30)
 0x11 0xdf 0xf5 0xd5
 # CHECK: r17 = parity(r21, r31)
+
+# Bit reverse
 0xd0 0xc0 0xd4 0x80
 # CHECK: r17:16 = brev(r21:20)
+0xd1 0xc0 0x55 0x8c
+# CHECK: r17 = brev(r21)
+
+# Set/clear/toggle bit
 0x11 0xdf 0xd5 0x8c
 # CHECK: r17 = setbit(r21, #31)
 0x31 0xdf 0xd5 0x8c
@@ -78,10 +100,14 @@
 # CHECK: r17 = clrbit(r21, r31)
 0x91 0xdf 0x95 0xc6
 # CHECK: r17 = togglebit(r21, r31)
+
+# Split bitfield
 0x90 0xdf 0xd5 0x88
 # CHECK: r17:16 = bitsplit(r21, #31)
 0x10 0xdf 0x35 0xd4
 # CHECK: r17:16 = bitsplit(r21, r31)
+
+# Table index
 0xf1 0xcd 0x15 0x87
 # CHECK: r17 = tableidxb(r21, #7, #13):raw
 0xf1 0xcd 0x55 0x87
diff --git a/test/MC/Disassembler/Hexagon/xtype_complex.txt b/test/MC/Disassembler/Hexagon/xtype_complex.txt
new file mode 100644
index 000000000000..2332082d835e
--- /dev/null
+++ b/test/MC/Disassembler/Hexagon/xtype_complex.txt
@@ -0,0 +1,128 @@
+# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.10.3 XTYPE/COMPLEX
+
+# Complex add/sub halfwords
+0x90 0xde 0x54 0xc1
+# CHECK: r17:16 = vxaddsubh(r21:20, r31:30):sat
+0xd0 0xde 0x54 0xc1
+# CHECK: r17:16 = vxsubaddh(r21:20, r31:30):sat
+0x10 0xde 0xd4 0xc1
+# CHECK: r17:16 = vxaddsubh(r21:20, r31:30):rnd:>>1:sat
+0x50 0xde 0xd4 0xc1
+# CHECK: r17:16 = vxsubaddh(r21:20, r31:30):rnd:>>1:sat
+
+# Complex add/sub words
+0x10 0xde 0x54 0xc1
+# CHECK: r17:16 = vxaddsubw(r21:20, r31:30):sat
+0x50 0xde 0x54 0xc1
+# CHECK: r17:16 = vxsubaddw(r21:20, r31:30):sat
+
+# Complex multiply
+0xd0 0xdf 0x15 0xe5
+# CHECK: r17:16 = cmpy(r21, r31):sat
+0xd0 0xdf 0x95 0xe5
+# CHECK: r17:16 = cmpy(r21, r31):<<1:sat
+0xd0 0xdf 0x55 0xe5
+# CHECK: r17:16 = cmpy(r21, r31*):sat
+0xd0 0xdf 0xd5 0xe5
+# CHECK: r17:16 = cmpy(r21, r31*):<<1:sat
+0xd0 0xdf 0x15 0xe7
+# CHECK: r17:16 += cmpy(r21, r31):sat
+0xd0 0xdf 0x95 0xe7
+# CHECK: r17:16 += cmpy(r21, r31):<<1:sat
+0xf0 0xdf 0x15 0xe7
+# CHECK: r17:16 -= cmpy(r21, r31):sat
+0xf0 0xdf 0x95 0xe7
+# CHECK: r17:16 -= cmpy(r21, r31):<<1:sat
+0xd0 0xdf 0x55 0xe7
+# CHECK: r17:16 += cmpy(r21, r31*):sat
+0xd0 0xdf 0xd5 0xe7
+# CHECK: r17:16 += cmpy(r21, r31*):<<1:sat
+0xf0 0xdf 0x55 0xe7
+# CHECK: r17:16 -= cmpy(r21, r31*):sat
+0xf0 0xdf 0xd5 0xe7
+# CHECK: r17:16 -= cmpy(r21, r31*):<<1:sat
+
+# Complex multiply real or imaginary
+0x30 0xdf 0x15 0xe5
+# CHECK: r17:16 = cmpyi(r21, r31)
+0x50 0xdf 0x15 0xe5
+# CHECK: r17:16 = cmpyr(r21, r31)
+0x30 0xdf 0x15 0xe7
+# CHECK: r17:16 += cmpyi(r21, r31)
+0x50 0xdf 0x15 0xe7
+# CHECK: r17:16 += cmpyr(r21, r31)
+
+# Complex multiply with round and pack
+0xd1 0xdf 0x35 0xed
+# CHECK: r17 = cmpy(r21, r31):rnd:sat
+0xd1 0xdf 0xb5 0xed
+# CHECK: r17 = cmpy(r21, r31):<<1:rnd:sat
+0xd1 0xdf 0x75 0xed
+# CHECK: r17 = cmpy(r21, r31*):rnd:sat
+0xd1 0xdf 0xf5 0xed
+# CHECK: r17 = cmpy(r21, r31*):<<1:rnd:sat
+
+# Complex multiply 32x16
+0x91 0xdf 0x14 0xc5
+# CHECK: r17 = cmpyiwh(r21:20, r31):<<1:rnd:sat
+0xb1 0xdf 0x14 0xc5
+# CHECK: r17 = cmpyiwh(r21:20, r31*):<<1:rnd:sat
+0xd1 0xdf 0x14 0xc5
+# CHECK: r17 = cmpyrwh(r21:20, r31):<<1:rnd:sat
+0xf1 0xdf 0x14 0xc5
+# CHECK: r17 = cmpyrwh(r21:20, r31*):<<1:rnd:sat
+
+# Vector complex multiply real or imaginary
+0xd0 0xde 0x34 0xe8
+# CHECK: r17:16 = vcmpyr(r21:20, r31:30):sat
+0xd0 0xde 0xb4 0xe8
+# CHECK: r17:16 = vcmpyr(r21:20, r31:30):<<1:sat
+0xd0 0xde 0x54 0xe8
+# CHECK: r17:16 = vcmpyi(r21:20, r31:30):sat
+0xd0 0xde 0xd4 0xe8
+# CHECK: r17:16 = vcmpyi(r21:20, r31:30):<<1:sat
+0x90 0xde 0x34 0xea
+# CHECK: r17:16 += vcmpyr(r21:20, r31:30):sat
+0x90 0xde 0x54 0xea
+# CHECK: r17:16 += vcmpyi(r21:20, r31:30):sat
+
+# Vector complex conjugate
+0xf0 0xc0 0x94 0x80
+# CHECK: r17:16 = vconj(r21:20):sat
+
+# Vector complex rotate
+0x10 0xdf 0xd4 0xc3
+# CHECK: r17:16 = vcrotate(r21:20, r31)
+
+# Vector reduce complex multiply real or imaginary
+0x10 0xde 0x14 0xe8
+# CHECK: r17:16 = vrcmpyi(r21:20, r31:30)
+0x30 0xde 0x14 0xe8
+# CHECK: r17:16 = vrcmpyr(r21:20, r31:30)
+0x10 0xde 0x54 0xe8
+# CHECK: r17:16 = vrcmpyi(r21:20, r31:30*)
+0x30 0xde 0x74 0xe8
+# CHECK: r17:16 = vrcmpyr(r21:20, r31:30*)
+
+# Vector reduce complex multiply by scalar
+0x90 0xde 0xb4 0xe8
+# CHECK: r17:16 = vrcmpys(r21:20, r31:30):<<1:sat:raw:hi
+0x90 0xde 0xf4 0xe8
+# CHECK: r17:16 = vrcmpys(r21:20, r31:30):<<1:sat:raw:lo
+0x90 0xde 0xb4 0xea
+# CHECK: r17:16 += vrcmpys(r21:20, r31:30):<<1:sat:raw:hi
+0x90 0xde 0xf4 0xea
+# CHECK: r17:16 += vrcmpys(r21:20, r31:30):<<1:sat:raw:lo
+
+# Vector reduce complex multiply by scalar with round and pack
+0xd1 0xde 0xb4 0xe9
+# CHECK: r17 = vrcmpys(r21:20, r31:30):<<1:rnd:sat:raw:hi
+0xf1 0xde 0xb4 0xe9
+# CHECK: r17 = vrcmpys(r21:20, r31:30):<<1:rnd:sat:raw:lo
+
+# Vector reduce complex rotate
+0xf0 0xff 0xd4 0xc3
+# CHECK: r17:16 = vrcrotate(r21:20, r31, #3)
+0x30 0xff 0xb4 0xcb
+# CHECK: r17:16 += vrcrotate(r21:20, r31, #3)
diff --git a/test/MC/Disassembler/Hexagon/xtype_fp.txt b/test/MC/Disassembler/Hexagon/xtype_fp.txt
index 97c072730bd4..70074208edad 100644
--- a/test/MC/Disassembler/Hexagon/xtype_fp.txt
+++ b/test/MC/Disassembler/Hexagon/xtype_fp.txt
@@ -1,11 +1,17 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.10.4 XTYPE/FP
 
+# Floating point addition
 0x11 0xdf 0x15 0xeb
 # CHECK: r17 = sfadd(r21, r31)
+
+# Classify floating-point value
 0x03 0xd5 0xf1 0x85
 # CHECK: p3 = sfclass(r17, #21)
 0xb3 0xc2 0x90 0xdc
 # CHECK: p3 = dfclass(r17:16, #21)
+
+# Compare floating-point value
 0x03 0xd5 0xf1 0xc7
 # CHECK: p3 = sfcmp.ge(r17, r21)
 0x23 0xd5 0xf1 0xc7
@@ -22,10 +28,14 @@
 # CHECK: p3 = dfcmp.ge(r17:16, r21:20)
 0x63 0xd4 0xf0 0xd2
 # CHECK: p3 = dfcmp.uo(r17:16, r21:20)
+
+# Convert floating-point value to other format
 0x10 0xc0 0x95 0x84
 # CHECK: r17:16 = convert_sf2df(r21)
 0x31 0xc0 0x14 0x88
 # CHECK: r17 = convert_df2sf(r21:20)
+
+# Convert integer to floating-point value
 0x50 0xc0 0xf4 0x80
 # CHECK: r17:16 = convert_ud2df(r21:20)
 0x70 0xc0 0xf4 0x80
@@ -42,6 +52,8 @@
 # CHECK: r17 = convert_uw2sf(r21)
 0x11 0xc0 0x55 0x8b
 # CHECK: r17 = convert_w2sf(r21)
+
+# Convert floating-point value to integer
 0x10 0xc0 0xf4 0x80
 # CHECK: r17:16 = convert_df2d(r21:20)
 0x30 0xc0 0xf4 0x80
@@ -74,22 +86,36 @@
 # CHECK: r17 = convert_sf2w(r21)
 0x31 0xc0 0x95 0x8b
 # CHECK: r17 = convert_sf2w(r21):chop
+
+# Floating point extreme value assistance
 0x11 0xc0 0xb5 0x8b
 # CHECK: r17 = sffixupr(r21)
 0x11 0xdf 0xd5 0xeb
 # CHECK: r17 = sffixupn(r21, r31)
 0x31 0xdf 0xd5 0xeb
 # CHECK: r17 = sffixupd(r21, r31)
+
+# Floating point fused multiply-add
 0x91 0xdf 0x15 0xef
 # CHECK: r17 += sfmpy(r21, r31)
 0xb1 0xdf 0x15 0xef
 # CHECK: r17 -= sfmpy(r21, r31)
+
+# Floating point fused multiply-add with scaling
 0xf1 0xdf 0x75 0xef
 # CHECK: r17 += sfmpy(r21, r31, p3):scale
+
+# Floating point reciprocal square root approximation
+0x71 0xc0 0xf5 0x8b
+# CHECK: r17, p3 = sfinvsqrta(r21)
+
+# Floating point fused multiply-add for library routines
 0xd1 0xdf 0x15 0xef
 # CHECK: r17 += sfmpy(r21, r31):lib
 0xf1 0xdf 0x15 0xef
 # CHECK: r17 -= sfmpy(r21, r31):lib
+
+# Create floating-point constant
 0xb1 0xc2 0x00 0xd6
 # CHECK: r17 = sfmake(#21):pos
 0xb1 0xc2 0x40 0xd6
@@ -98,13 +124,23 @@
 # CHECK: r17:16 = dfmake(#21):pos
 0xb0 0xc2 0x40 0xd9
 # CHECK: r17:16 = dfmake(#21):neg
+
+# Floating point maximum
 0x11 0xdf 0x95 0xeb
 # CHECK: r17 = sfmax(r21, r31)
+
+# Floating point minimum
 0x31 0xdf 0x95 0xeb
 # CHECK: r17 = sfmin(r21, r31)
+
+# Floating point multiply
 0x11 0xdf 0x55 0xeb
 # CHECK: r17 = sfmpy(r21, r31)
+
+# Floating point reciprocal approximation
 0xf1 0xdf 0xf5 0xeb
 # CHECK: r17, p3 = sfrecipa(r21, r31)
+
+# Floating point subtraction
 0x31 0xdf 0x15 0xeb
 # CHECK: r17 = sfsub(r21, r31)
diff --git a/test/MC/Disassembler/Hexagon/xtype_mpy.txt b/test/MC/Disassembler/Hexagon/xtype_mpy.txt
index b6ccaa6f31e0..ada32162a81e 100644
--- a/test/MC/Disassembler/Hexagon/xtype_mpy.txt
+++ b/test/MC/Disassembler/Hexagon/xtype_mpy.txt
@@ -1,5 +1,7 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.10.5 XTYPE/MPY
 
+# Multiply and use lower result
 0xb1 0xdf 0x35 0xd7
 # CHECK: r17 = add(#21, mpyi(r21, r31))
 0xbf 0xd1 0x35 0xd8
@@ -22,6 +24,76 @@
 # CHECK: r17 = mpyi(r21, r31)
 0x11 0xdf 0x15 0xef
 # CHECK: r17 += mpyi(r21, r31)
+
+# Vector multiply word by signed half (32x16)
+0xb0 0xde 0x14 0xe8
+# CHECK: r17:16 = vmpyweh(r21:20, r31:30):sat
+0xb0 0xde 0x94 0xe8
+# CHECK: r17:16 = vmpyweh(r21:20, r31:30):<<1:sat
+0xf0 0xde 0x14 0xe8
+# CHECK: r17:16 = vmpywoh(r21:20, r31:30):sat
+0xf0 0xde 0x94 0xe8
+# CHECK: r17:16 = vmpywoh(r21:20, r31:30):<<1:sat
+0xb0 0xde 0x34 0xe8
+# CHECK: r17:16 = vmpyweh(r21:20, r31:30):rnd:sat
+0xb0 0xde 0xb4 0xe8
+# CHECK: r17:16 = vmpyweh(r21:20, r31:30):<<1:rnd:sat
+0xf0 0xde 0x34 0xe8
+# CHECK: r17:16 = vmpywoh(r21:20, r31:30):rnd:sat
+0xf0 0xde 0xb4 0xe8
+# CHECK: r17:16 = vmpywoh(r21:20, r31:30):<<1:rnd:sat
+0xb0 0xde 0x14 0xea
+# CHECK: r17:16 += vmpyweh(r21:20, r31:30):sat
+0xb0 0xde 0x94 0xea
+# CHECK: r17:16 += vmpyweh(r21:20, r31:30):<<1:sat
+0xf0 0xde 0x14 0xea
+# CHECK: r17:16 += vmpywoh(r21:20, r31:30):sat
+0xf0 0xde 0x94 0xea
+# CHECK: r17:16 += vmpywoh(r21:20, r31:30):<<1:sat
+0xb0 0xde 0x34 0xea
+# CHECK: r17:16 += vmpyweh(r21:20, r31:30):rnd:sat
+0xb0 0xde 0xb4 0xea
+# CHECK: r17:16 += vmpyweh(r21:20, r31:30):<<1:rnd:sat
+0xf0 0xde 0x34 0xea
+# CHECK: r17:16 += vmpywoh(r21:20, r31:30):rnd:sat
+0xf0 0xde 0xb4 0xea
+# CHECK: r17:16 += vmpywoh(r21:20, r31:30):<<1:rnd:sat
+
+# Vector multiply word by unsigned half (32x16)
+0xb0 0xde 0x54 0xe8
+# CHECK: r17:16 = vmpyweuh(r21:20, r31:30):sat
+0xb0 0xde 0xd4 0xe8
+# CHECK: r17:16 = vmpyweuh(r21:20, r31:30):<<1:sat
+0xf0 0xde 0x54 0xe8
+# CHECK: r17:16 = vmpywouh(r21:20, r31:30):sat
+0xf0 0xde 0xd4 0xe8
+# CHECK: r17:16 = vmpywouh(r21:20, r31:30):<<1:sat
+0xb0 0xde 0x74 0xe8
+# CHECK: r17:16 = vmpyweuh(r21:20, r31:30):rnd:sat
+0xb0 0xde 0xf4 0xe8
+# CHECK: r17:16 = vmpyweuh(r21:20, r31:30):<<1:rnd:sat
+0xf0 0xde 0x74 0xe8
+# CHECK: r17:16 = vmpywouh(r21:20, r31:30):rnd:sat
+0xf0 0xde 0xf4 0xe8
+# CHECK: r17:16 = vmpywouh(r21:20, r31:30):<<1:rnd:sat
+0xb0 0xde 0x54 0xea
+# CHECK: r17:16 += vmpyweuh(r21:20, r31:30):sat
+0xb0 0xde 0xd4 0xea
+# CHECK: r17:16 += vmpyweuh(r21:20, r31:30):<<1:sat
+0xf0 0xde 0x54 0xea
+# CHECK: r17:16 += vmpywouh(r21:20, r31:30):sat
+0xf0 0xde 0xd4 0xea
+# CHECK: r17:16 += vmpywouh(r21:20, r31:30):<<1:sat
+0xb0 0xde 0x74 0xea
+# CHECK: r17:16 += vmpyweuh(r21:20, r31:30):rnd:sat
+0xb0 0xde 0xf4 0xea
+# CHECK: r17:16 += vmpyweuh(r21:20, r31:30):<<1:rnd:sat
+0xf0 0xde 0x74 0xea
+# CHECK: r17:16 += vmpywouh(r21:20, r31:30):rnd:sat
+0xf0 0xde 0xf4 0xea
+# CHECK: r17:16 += vmpywouh(r21:20, r31:30):<<1:rnd:sat
+
+# Multiply signed halfwords
 0x10 0xdf 0x95 0xe4
 # CHECK: r17:16 = mpy(r21.l, r31.l):<<1
 0x30 0xdf 0x95 0xe4
@@ -118,6 +190,8 @@
 # CHECK: r17 -= mpy(r21.h, r31.l):<<1:sat
 0xf1 0xdf 0xb5 0xee
 # CHECK: r17 -= mpy(r21.h, r31.h):<<1:sat
+
+# Multiply unsigned halfwords
 0x10 0xdf 0xd5 0xe4
 # CHECK: r17:16 = mpyu(r21.l, r31.l):<<1
 0x30 0xdf 0xd5 0xe4
@@ -166,6 +240,32 @@
 # CHECK: r17 -= mpyu(r21.h, r31.l):<<1
 0x71 0xdf 0xf5 0xee
 # CHECK: r17 -= mpyu(r21.h, r31.h):<<1
+
+# Polynomial multiply words
+0xf0 0xdf 0x55 0xe5
+# CHECK: r17:16 = pmpyw(r21, r31)
+0xf0 0xdf 0x35 0xe7
+# CHECK: r17:16 ^= pmpyw(r21, r31)
+
+# Vector reduce multiply word by signed half (32x16)
+0x50 0xde 0x34 0xe8
+# CHECK: r17:16 = vrmpywoh(r21:20, r31:30)
+0x50 0xde 0xb4 0xe8
+# CHECK: r17:16 = vrmpywoh(r21:20, r31:30):<<1
+0x90 0xde 0x54 0xe8
+# CHECK: r17:16 = vrmpyweh(r21:20, r31:30)
+0x90 0xde 0xd4 0xe8
+# CHECK: r17:16 = vrmpyweh(r21:20, r31:30):<<1
+0xd0 0xde 0x74 0xea
+# CHECK: r17:16 += vrmpywoh(r21:20, r31:30)
+0xd0 0xde 0xf4 0xea
+# CHECK: r17:16 += vrmpywoh(r21:20, r31:30):<<1
+0xd0 0xde 0x34 0xea
+# CHECK: r17:16 += vrmpyweh(r21:20, r31:30)
+0xd0 0xde 0xb4 0xea
+# CHECK: r17:16 += vrmpyweh(r21:20, r31:30):<<1
+
+# Multiply and use upper result
 0x31 0xdf 0x15 0xed
 # CHECK: r17 = mpy(r21, r31)
 0x31 0xdf 0x35 0xed
@@ -178,16 +278,20 @@
 # CHECK: r17 = mpy(r21, r31.h):<<1:sat
 0x31 0xdf 0xb5 0xed
 # CHECK: r17 = mpy(r21, r31.l):<<1:sat
-0x11 0xdf 0xf5 0xed
-# CHECK: r17 = mpy(r21, r31):<<1:sat
 0x91 0xdf 0xb5 0xed
 # CHECK: r17 = mpy(r21, r31.h):<<1:rnd:sat
+0x11 0xdf 0xf5 0xed
+# CHECK: r17 = mpy(r21, r31):<<1:sat
 0x91 0xdf 0xf5 0xed
 # CHECK: r17 = mpy(r21, r31.l):<<1:rnd:sat
+0x51 0xdf 0xb5 0xed
+# CHECK: r17 = mpy(r21, r31):<<1
 0x11 0xdf 0x75 0xef
 # CHECK: r17 += mpy(r21, r31):<<1:sat
 0x31 0xdf 0x75 0xef
 # CHECK: r17 -= mpy(r21, r31):<<1:sat
+
+# Multiply and use full result
 0x10 0xdf 0x15 0xe5
 # CHECK: r17:16 = mpy(r21, r31)
 0x10 0xdf 0x55 0xe5
@@ -200,3 +304,97 @@
 # CHECK: r17:16 += mpyu(r21, r31)
 0x10 0xdf 0x75 0xe7
 # CHECK: r17:16 -= mpyu(r21, r31)
+
+# Vector dual multiply
+0x90 0xde 0x14 0xe8
+# CHECK: r17:16 = vdmpy(r21:20, r31:30):sat
+0x90 0xde 0x94 0xe8
+# CHECK: r17:16 = vdmpy(r21:20, r31:30):<<1:sat
+0x90 0xde 0x14 0xea
+# CHECK: r17:16 += vdmpy(r21:20, r31:30):sat
+0x90 0xde 0x94 0xea
+# CHECK: r17:16 += vdmpy(r21:20, r31:30):<<1:sat
+
+# Vector dual multiply with round and pack
+0x11 0xde 0x14 0xe9
+# CHECK: r17 = vdmpy(r21:20, r31:30):rnd:sat
+0x11 0xde 0x94 0xe9
+# CHECK: r17 = vdmpy(r21:20, r31:30):<<1:rnd:sat
+
+# Vector reduce multiply bytes
+0x30 0xde 0x94 0xe8
+# CHECK: r17:16 = vrmpybu(r21:20, r31:30)
+0x30 0xde 0xd4 0xe8
+# CHECK: r17:16 = vrmpybsu(r21:20, r31:30)
+0x30 0xde 0x94 0xea
+# CHECK: r17:16 += vrmpybu(r21:20, r31:30)
+0x30 0xde 0xd4 0xea
+# CHECK: r17:16 += vrmpybsu(r21:20, r31:30)
+
+# Vector dual multiply signed by unsigned bytes
+0x30 0xde 0xb4 0xe8
+# CHECK: r17:16 = vdmpybsu(r21:20, r31:30):sat
+0x30 0xde 0x34 0xea
+# CHECK: r17:16 += vdmpybsu(r21:20, r31:30):sat
+
+# Vector multiply even haldwords
+0xd0 0xde 0x14 0xe8
+# CHECK: r17:16 = vmpyeh(r21:20, r31:30):sat
+0xd0 0xde 0x94 0xe8
+# CHECK: r17:16 = vmpyeh(r21:20, r31:30):<<1:sat
+0x50 0xde 0x34 0xea
+# CHECK: r17:16 += vmpyeh(r21:20, r31:30)
+0xd0 0xde 0x14 0xea
+# CHECK: r17:16 += vmpyeh(r21:20, r31:30):sat
+0xd0 0xde 0x94 0xea
+# CHECK: r17:16 += vmpyeh(r21:20, r31:30):<<1:sat
+
+# Vector multiply halfwords
+0xb0 0xdf 0x15 0xe5
+# CHECK: r17:16 = vmpyh(r21, r31):sat
+0xb0 0xdf 0x95 0xe5
+# CHECK: r17:16 = vmpyh(r21, r31):<<1:sat
+0x30 0xdf 0x35 0xe7
+# CHECK: r17:16 += vmpyh(r21, r31)
+0xb0 0xdf 0x15 0xe7
+# CHECK: r17:16 += vmpyh(r21, r31):sat
+0xb0 0xdf 0x95 0xe7
+# CHECK: r17:16 += vmpyh(r21, r31):<<1:sat
+
+# Vector multiply halfwords with round and pack
+0xf1 0xdf 0x35 0xed
+# CHECK: r17 = vmpyh(r21, r31):rnd:sat
+0xf1 0xdf 0xb5 0xed
+# CHECK: r17 = vmpyh(r21, r31):<<1:rnd:sat
+
+# Vector multiply halfwords signed by unsigned
+0xf0 0xdf 0x15 0xe5
+# CHECK: r17:16 = vmpyhsu(r21, r31):sat
+0xf0 0xdf 0x95 0xe5
+# CHECK: r17:16 = vmpyhsu(r21, r31):<<1:sat
+0xb0 0xdf 0x75 0xe7
+# CHECK: r17:16 += vmpyhsu(r21, r31):sat
+0xb0 0xdf 0xf5 0xe7
+# CHECK: r17:16 += vmpyhsu(r21, r31):<<1:sat
+
+# Vector reduce multiply halfwords
+0x50 0xde 0x14 0xe8
+# CHECK: r17:16 = vrmpyh(r21:20, r31:30)
+0x50 0xde 0x14 0xea
+# CHECK: r17:16 += vrmpyh(r21:20, r31:30)
+
+# Vector multiply bytes
+0x30 0xdf 0x55 0xe5
+# CHECK: r17:16 = vmpybsu(r21, r31)
+0x30 0xdf 0x95 0xe5
+# CHECK: r17:16 = vmpybu(r21, r31)
+0x30 0xdf 0x95 0xe7
+# CHECK: r17:16 += vmpybu(r21, r31)
+0x30 0xdf 0xd5 0xe7
+# CHECK: r17:16 += vmpybsu(r21, r31)
+
+# Vector polynomial multiply halfwords
+0xf0 0xdf 0xd5 0xe5
+# CHECK: r17:16 = vpmpyh(r21, r31)
+0xf0 0xdf 0xb5 0xe7
+# CHECK: r17:16 ^= vpmpyh(r21, r31)
diff --git a/test/MC/Disassembler/Hexagon/xtype_perm.txt b/test/MC/Disassembler/Hexagon/xtype_perm.txt
index 1de3d11d820a..91d2fc5ae698 100644
--- a/test/MC/Disassembler/Hexagon/xtype_perm.txt
+++ b/test/MC/Disassembler/Hexagon/xtype_perm.txt
@@ -1,5 +1,11 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.10.6 XTYPE/PERM
 
+# CABAC decode bin
+0xd0 0xde 0xd4 0xc1
+# CHECK: r17:16 = decbin(r21:20, r31:30)
+
+# Saturate
 0x11 0xc0 0xd4 0x88
 # CHECK: r17 = sat(r21:20)
 0x91 0xc0 0xd5 0x8c
@@ -10,5 +16,89 @@
 # CHECK: r17 = satub(r21)
 0xf1 0xc0 0xd5 0x8c
 # CHECK: r17 = satb(r21)
+
+# Swizzle bytes
 0xf1 0xc0 0x95 0x8c
 # CHECK: r17 = swiz(r21)
+
+# Vector align
+0x70 0xd4 0x1e 0xc2
+# CHECK: r17:16 = valignb(r21:20, r31:30, p3)
+0x70 0xde 0x94 0xc2
+# CHECK: r17:16 = vspliceb(r21:20, r31:30, p3)
+
+# Vector round and pack
+0x91 0xc0 0x94 0x88
+# CHECK: r17 = vrndwh(r21:20)
+0xd1 0xc0 0x94 0x88
+# CHECK: r17 = vrndwh(r21:20):sat
+
+# Vector saturate and pack
+0x11 0xc0 0x14 0x88
+# CHECK: r17 = vsathub(r21:20)
+0x51 0xc0 0x14 0x88
+# CHECK: r17 = vsatwh(r21:20)
+0x91 0xc0 0x14 0x88
+# CHECK: r17 = vsatwuh(r21:20)
+0xd1 0xc0 0x14 0x88
+# CHECK: r17 = vsathb(r21:20)
+0x11 0xc0 0x95 0x8c
+# CHECK: r17 = vsathb(r21)
+0x51 0xc0 0x95 0x8c
+# CHECK: r17 = vsathub(r21)
+
+# Vector saturate without pack
+0x90 0xc0 0x14 0x80
+# CHECK: r17:16 = vsathub(r21:20)
+0xb0 0xc0 0x14 0x80
+# CHECK: r17:16 = vsatwuh(r21:20)
+0xd0 0xc0 0x14 0x80
+# CHECK: r17:16 = vsatwh(r21:20)
+0xf0 0xc0 0x14 0x80
+# CHECK: r17:16 = vsathb(r21:20)
+
+# Vector shuffle
+0x50 0xde 0x14 0xc1
+# CHECK: r17:16 = shuffeb(r21:20, r31:30)
+0x90 0xd4 0x1e 0xc1
+# CHECK: r17:16 = shuffob(r21:20, r31:30)
+0xd0 0xde 0x14 0xc1
+# CHECK: r17:16 = shuffeh(r21:20, r31:30)
+0x10 0xd4 0x9e 0xc1
+# CHECK: r17:16 = shuffoh(r21:20, r31:30)
+
+# Vector splat bytes
+0xf1 0xc0 0x55 0x8c
+# CHECK: r17 = vsplatb(r21)
+
+# Vector splat halfwords
+0x50 0xc0 0x55 0x84
+# CHECK: r17:16 = vsplath(r21)
+
+# Vector splice
+0x70 0xde 0x94 0xc0
+# CHECK: r17:16 = vspliceb(r21:20, r31:30, #3)
+0x70 0xde 0x94 0xc2
+# CHECK: r17:16 = vspliceb(r21:20, r31:30, p3)
+
+# Vector sign extend
+0x10 0xc0 0x15 0x84
+# CHECK: r17:16 = vsxtbh(r21)
+0x90 0xc0 0x15 0x84
+# CHECK: r17:16 = vsxthw(r21)
+
+# Vector truncate
+0x11 0xc0 0x94 0x88
+# CHECK: r17 = vtrunohb(r21:20)
+0x51 0xc0 0x94 0x88
+# CHECK: r17 = vtrunehb(r21:20)
+0x50 0xde 0x94 0xc1
+# CHECK: r17:16 = vtrunewh(r21:20, r31:30)
+0x90 0xde 0x94 0xc1
+# CHECK: r17:16 = vtrunowh(r21:20, r31:30)
+
+# Vector zero extend
+0x50 0xc0 0x15 0x84
+# CHECK: r17:16 = vzxtbh(r21)
+0xd0 0xc0 0x15 0x84
+# CHECK: r17:16 = vzxthw(r21)
diff --git a/test/MC/Disassembler/Hexagon/xtype_pred.txt b/test/MC/Disassembler/Hexagon/xtype_pred.txt
index 0fa4f05bce82..cec6d1be0f10 100644
--- a/test/MC/Disassembler/Hexagon/xtype_pred.txt
+++ b/test/MC/Disassembler/Hexagon/xtype_pred.txt
@@ -1,9 +1,13 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.10.7 XTYPE/PRED
 
+# Bounds check
 0x83 0xf4 0x10 0xd2
 # CHECK: p3 = boundscheck(r17:16, r21:20):raw:lo
 0xa3 0xf4 0x10 0xd2
 # CHECK: p3 = boundscheck(r17:16, r21:20):raw:hi
+
+# Compare byte
 0x43 0xd5 0xd1 0xc7
 # CHECK: p3 = cmpb.gt(r17, r21)
 0xc3 0xd5 0xd1 0xc7
@@ -16,6 +20,8 @@
 # CHECK: p3 = cmpb.gt(r17, #21)
 0xa3 0xc2 0x51 0xdd
 # CHECK: p3 = cmpb.gtu(r17, #21)
+
+# Compare half
 0x63 0xd5 0xd1 0xc7
 # CHECK: p3 = cmph.eq(r17, r21)
 0x83 0xd5 0xd1 0xc7
@@ -28,12 +34,16 @@
 # CHECK: p3 = cmph.gt(r17, #21)
 0xab 0xc2 0x51 0xdd
 # CHECK: p3 = cmph.gtu(r17, #21)
+
+# Compare doublewords
 0x03 0xde 0x94 0xd2
 # CHECK: p3 = cmp.eq(r21:20, r31:30)
 0x43 0xde 0x94 0xd2
 # CHECK: p3 = cmp.gt(r21:20, r31:30)
 0x83 0xde 0x94 0xd2
 # CHECK: p3 = cmp.gtu(r21:20, r31:30)
+
+# Compare bitmask
 0x03 0xd5 0x91 0x85
 # CHECK: p3 = bitsclr(r17, #21)
 0x03 0xd5 0xb1 0x85
@@ -46,14 +56,22 @@
 # CHECK: p3 = bitsclr(r17, r21)
 0x03 0xd5 0xb1 0xc7
 # CHECK: p3 = !bitsclr(r17, r21)
+
+# mask generate from predicate
 0x10 0xc3 0x00 0x86
 # CHECK: r17:16 = mask(p3)
+
+# Check for TLB match
 0x63 0xf5 0x10 0xd2
 # CHECK: p3 = tlbmatch(r17:16, r21)
+
+# Predicate Transfer
 0x03 0xc0 0x45 0x85
 # CHECK: p3 = r5
 0x05 0xc0 0x43 0x89
 # CHECK: r5 = p3
+
+# Test bit
 0x03 0xd5 0x11 0x85
 # CHECK: p3 = tstbit(r17, #21)
 0x03 0xd5 0x31 0x85
@@ -62,5 +80,57 @@
 # CHECK: p3 = tstbit(r17, r21)
 0x03 0xd5 0x31 0xc7
 # CHECK: p3 = !tstbit(r17, r21)
+
+# Vector compare halfwords
+0x63 0xde 0x14 0xd2
+# CHECK: p3 = vcmph.eq(r21:20, r31:30)
+0x83 0xde 0x14 0xd2
+# CHECK: p3 = vcmph.gt(r21:20, r31:30)
+0xa3 0xde 0x14 0xd2
+# CHECK: p3 = vcmph.gtu(r21:20, r31:30)
+0xeb 0xc3 0x14 0xdc
+# CHECK: p3 = vcmph.eq(r21:20, #31)
+0xeb 0xc3 0x34 0xdc
+# CHECK: p3 = vcmph.gt(r21:20, #31)
+0xeb 0xc3 0x54 0xdc
+# CHECK: p3 = vcmph.gtu(r21:20, #31)
+
+# Vector compare bytes for any match
+0x03 0xfe 0x14 0xd2
+# CHECK: p3 = any8(vcmpb.eq(r21:20, r31:30))
+
+# Vector compare bytes
+0x63 0xde 0x14 0xd2
+# CHECK: p3 = vcmph.eq(r21:20, r31:30)
+0x83 0xde 0x14 0xd2
+# CHECK: p3 = vcmph.gt(r21:20, r31:30)
+0xa3 0xde 0x14 0xd2
+# CHECK: p3 = vcmph.gtu(r21:20, r31:30)
+0xeb 0xc3 0x14 0xdc
+# CHECK: p3 = vcmph.eq(r21:20, #31)
+0xeb 0xc3 0x34 0xdc
+# CHECK: p3 = vcmph.gt(r21:20, #31)
+0xeb 0xc3 0x54 0xdc
+# CHECK: p3 = vcmph.gtu(r21:20, #31)
+
+# Vector compare words
+0x03 0xde 0x14 0xd2
+# CHECK: p3 = vcmpw.eq(r21:20, r31:30)
+0x23 0xde 0x14 0xd2
+# CHECK: p3 = vcmpw.gt(r21:20, r31:30)
+0x43 0xde 0x14 0xd2
+# CHECK: p3 = vcmpw.gtu(r21:20, r31:30)
+0xf3 0xc3 0x14 0xdc
+# CHECK: p3 = vcmpw.eq(r21:20, #31)
+0xf3 0xc3 0x34 0xdc
+# CHECK: p3 = vcmpw.gt(r21:20, #31)
+0xf3 0xc3 0x54 0xdc
+# CHECK: p3 = vcmpw.gtu(r21:20, #31)
+
+# Viterbi pack even and odd predicate bits
 0x11 0xc2 0x03 0x89
-# CHECK: r17 = vitpack(p3, p2)
\ No newline at end of file
+# CHECK: r17 = vitpack(p3, p2)
+
+# Vector mux
+0x70 0xde 0x14 0xd1
+# CHECK: r17:16 = vmux(p3, r21:20, r31:30)
diff --git a/test/MC/Disassembler/Hexagon/xtype_shift.txt b/test/MC/Disassembler/Hexagon/xtype_shift.txt
index 9912fd3f1f41..e2d6816c1cac 100644
--- a/test/MC/Disassembler/Hexagon/xtype_shift.txt
+++ b/test/MC/Disassembler/Hexagon/xtype_shift.txt
@@ -1,5 +1,7 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.10.8 XTYPE/SHIFT
 
+# Shift by immediate
 0x10 0xdf 0x14 0x80
 # CHECK: r17:16 = asr(r21:20, #31)
 0x30 0xdf 0x14 0x80
@@ -12,6 +14,8 @@
 # CHECK: r17 = lsr(r21, #31)
 0x51 0xdf 0x15 0x8c
 # CHECK: r17 = asl(r21, #31)
+
+# Shift by immediate and accumulate
 0x10 0xdf 0x14 0x82
 # CHECK: r17:16 -= asr(r21:20, #31)
 0x30 0xdf 0x14 0x82
@@ -44,8 +48,12 @@
 # CHECK: r17 = add(#21, lsr(r17, #23))
 0x5e 0xf7 0x11 0xde
 # CHECK: r17 = sub(#21, lsr(r17, #23))
+
+# Shift by immediate and add
 0xf1 0xd5 0x1f 0xc4
 # CHECK: r17 = addasl(r21, r31, #7)
+
+# Shift by immediate and logical
 0x10 0xdf 0x54 0x82
 # CHECK: r17:16 &= asr(r21:20, #31)
 0x30 0xdf 0x54 0x82
@@ -62,14 +70,6 @@
 # CHECK: r17:16 ^= lsr(r21:20, #31)
 0x50 0xdf 0x94 0x82
 # CHECK: r17:16 ^= asl(r21:20, #31)
-0x48 0xff 0x11 0xde
-# CHECK: r17 = and(#21, asl(r17, #31))
-0x4a 0xff 0x11 0xde
-# CHECK: r17 = or(#21, asl(r17, #31))
-0x58 0xff 0x11 0xde
-# CHECK: r17 = and(#21, lsr(r17, #31))
-0x5a 0xff 0x11 0xde
-# CHECK: r17 = or(#21, lsr(r17, #31))
 0x11 0xdf 0x55 0x8e
 # CHECK: r17 &= asr(r21, #31)
 0x31 0xdf 0x55 0x8e
@@ -86,12 +86,26 @@
 # CHECK: r17 ^= lsr(r21, #31)
 0x51 0xdf 0x95 0x8e
 # CHECK: r17 ^= asl(r21, #31)
+0x48 0xff 0x11 0xde
+# CHECK: r17 = and(#21, asl(r17, #31))
+0x4a 0xff 0x11 0xde
+# CHECK: r17 = or(#21, asl(r17, #31))
+0x58 0xff 0x11 0xde
+# CHECK: r17 = and(#21, lsr(r17, #31))
+0x5a 0xff 0x11 0xde
+# CHECK: r17 = or(#21, lsr(r17, #31))
+
+# Shift right by immediate with rounding
 0xf0 0xdf 0xd4 0x80
 # CHECK: r17:16 = asr(r21:20, #31):rnd
 0x11 0xdf 0x55 0x8c
 # CHECK: r17 = asr(r21, #31):rnd
+
+# Shift left by immediate with saturation
 0x51 0xdf 0x55 0x8c
 # CHECK: r17 = asl(r21, #31):sat
+
+# Shift by register
 0x10 0xdf 0x94 0xc3
 # CHECK: r17:16 = asr(r21:20, r31)
 0x50 0xdf 0x94 0xc3
@@ -110,6 +124,8 @@
 # CHECK: r17 = lsl(r21, r31)
 0xf1 0xdf 0x8a 0xc6
 # CHECK: r17 = lsl(#21, r31)
+
+# Shift by register and accumulate
 0x10 0xdf 0x94 0xcb
 # CHECK: r17:16 -= asr(r21:20, r31)
 0x50 0xdf 0x94 0xcb
@@ -142,6 +158,8 @@
 # CHECK: r17 += asl(r21, r31)
 0xd1 0xdf 0xd5 0xcc
 # CHECK: r17 += lsl(r21, r31)
+
+# Shift by register and logical
 0x10 0xdf 0x14 0xcb
 # CHECK: r17:16 |= asr(r21:20, r31)
 0x50 0xdf 0x14 0xcb
@@ -182,7 +200,61 @@
 # CHECK: r17 &= asl(r21, r31)
 0xd1 0xdf 0x55 0xcc
 # CHECK: r17 &= lsl(r21, r31)
+
+# Shift by register with saturation
 0x11 0xdf 0x15 0xc6
 # CHECK: r17 = asr(r21, r31):sat
 0x91 0xdf 0x15 0xc6
 # CHECK: r17 = asl(r21, r31):sat
+
+# Vector shift halfwords by immediate
+0x10 0xc5 0x94 0x80
+# CHECK: r17:16 = vasrh(r21:20, #5)
+0x30 0xc5 0x94 0x80
+# CHECK: r17:16 = vlsrh(r21:20, #5)
+0x50 0xc5 0x94 0x80
+# CHECK: r17:16 = vaslh(r21:20, #5)
+
+# Vector arithmetic shift halfwords with round
+0x10 0xc5 0x34 0x80
+# CHECK: r17:16 = vasrh(r21:20, #5):raw
+
+# Vector arithmetic shift halfwords with saturate and pack
+0x91 0xc5 0x74 0x88
+# CHECK: r17 = vasrhub(r21:20, #5):raw
+0xb1 0xc5 0x74 0x88
+# CHECK: r17 = vasrhub(r21:20, #5):sat
+
+# Vector shift halfwords by register
+0x10 0xdf 0x54 0xc3
+# CHECK: r17:16 = vasrh(r21:20, r31)
+0x50 0xdf 0x54 0xc3
+# CHECK: r17:16 = vlsrh(r21:20, r31)
+0x90 0xdf 0x54 0xc3
+# CHECK: r17:16 = vaslh(r21:20, r31)
+0xd0 0xdf 0x54 0xc3
+# CHECK: r17:16 = vlslh(r21:20, r31)
+
+# Vector shift words by immediate
+0x10 0xdf 0x54 0x80
+# CHECK: r17:16 = vasrw(r21:20, #31)
+0x30 0xdf 0x54 0x80
+# CHECK: r17:16 = vlsrw(r21:20, #31)
+0x50 0xdf 0x54 0x80
+# CHECK: r17:16 = vaslw(r21:20, #31)
+
+# Vector shift words by register
+0x10 0xdf 0x14 0xc3
+# CHECK: r17:16 = vasrw(r21:20, r31)
+0x50 0xdf 0x14 0xc3
+# CHECK: r17:16 = vlsrw(r21:20, r31)
+0x90 0xdf 0x14 0xc3
+# CHECK: r17:16 = vaslw(r21:20, r31)
+0xd0 0xdf 0x14 0xc3
+# CHECK: r17:16 = vlslw(r21:20, r31)
+
+# Vector shift words with truncate and pack
+0x51 0xdf 0xd4 0x88
+# CHECK: r17 = vasrw(r21:20, #31)
+0x51 0xdf 0x14 0xc5
+# CHECK: r17 = vasrw(r21:20, r31)
diff --git a/test/MC/Disassembler/Mips/micromips.txt b/test/MC/Disassembler/Mips/micromips.txt
index 07c1df91441a..2b75d46b3bcf 100644
--- a/test/MC/Disassembler/Mips/micromips.txt
+++ b/test/MC/Disassembler/Mips/micromips.txt
@@ -373,6 +373,15 @@
 # CHECK: nop
 0x00 0x00 0x00 0x00
 
+# CHECK: addiupc $2, 20
+0x79 0x00 0x00 0x05
+
+# CHECK: addiupc $7, 16777212
+0x7b 0xbf 0xff 0xff
+
+# CHECK: addiupc $7, -16777216
+0x7b 0xc0 0x00 0x00
+
 # CHECK: addu16 $6, $17, $4
 0x07 0x42
 
@@ -474,3 +483,24 @@
 
 # CHECK: bnez16 $6, 20
 0xaf 0x0a
+
+# CHECK: b16 132
+0xcc 0x42
+
+# CHECK: lw $3, 32($gp)
+0x65 0x88
+
+# CHECK: lwm16 $16, $17, $ra, 8($sp)
+0x45 0x12
+
+# CHECK: swm16 $16, $17, $ra, 8($sp)
+0x45 0x52
+
+# CHECK: break16 8
+0x46 0x88
+
+# CHECK: sdbbp16 14
+0x46 0xce
+
+# CHECK: movep $5, $6, $2, $3
+0x84 0x34
diff --git a/test/MC/Disassembler/Mips/micromips32r6.txt b/test/MC/Disassembler/Mips/micromips32r6.txt
new file mode 100644
index 000000000000..dee6fbef4090
--- /dev/null
+++ b/test/MC/Disassembler/Mips/micromips32r6.txt
@@ -0,0 +1,99 @@
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips | FileCheck %s
+
+0x00 0xa4 0x19 0x10 # CHECK: add $3, $4, $5
+
+0x30 0x64 0x04 0xd2 # CHECK: addiu $3, $4, 1234
+
+0x00 0xa4 0x19 0x50 # CHECK: addu $3, $4, $5
+
+0x78 0x80 0x00 0x19 # CHECK: addiupc $4, 100
+
+0x78 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
+
+0x78 0x7e 0xff 0xff # CHECK: auipc $3, -1
+
+0x00 0x43 0x24 0x1f # CHECK: align $4, $2, $3, 2
+
+0x00 0xa4 0x1a 0x50 # CHECK: and $3, $4, $5
+
+0xd0 0x64 0x04 0xd2 # CHECK: andi $3, $4, 1234
+
+0x10 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23
+
+0x74 0x40 0x02 0x9a # CHECK: beqzalc $2, 1332
+
+0x7c 0x40 0x02 0x9a # CHECK: bnezalc $2, 1332
+
+0xc0 0x42 0x02 0x9a # CHECK: bgezalc $2, 1332
+
+0xe0 0x40 0x02 0x9a # CHECK: bgtzalc $2, 1332
+
+0xe0 0x42 0x02 0x9a # CHECK: bltzalc $2, 1332
+
+0xc0 0x40 0x02 0x9a # CHECK: blezalc $2, 1332
+
+# CHECK: balc 14572256
+0xb4 0x37 0x96 0xb8
+
+# CHECK: bc 14572256
+0x94 0x37 0x96 0xb8
+
+# CHECK: bitswap $4, $2
+0x00 0x44 0x0b 0x3c
+
+# CHECK: cache 1, 8($5)
+0x20 0x25 0x60 0x08
+
+0x01 0x65 0x4b 0x3c # CHECK: clo $11, $5
+
+0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
+
+0x00 0xa4 0x19 0x18 # CHECK: div $3, $4, $5
+
+0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5
+
+0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256
+
+0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256
+
+0x78 0x48 0x00 0x43 # CHECK: lwpc $2, 268
+
+0x00 0x43 0x26 0x0f # CHECK: lsa $2, $3, $4, 3
+
+0x00 0xa4 0x19 0x58 # CHECK: mod $3, $4, $5
+
+0x00 0xa4 0x19 0xd8 # CHECK: modu $3, $4, $5
+
+0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5
+
+0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5
+
+0x00 0xa4 0x18 0x98 # CHECK: mulu $3, $4, $5
+
+0x00 0xa4,0x18,0xd8 # CHECK: muhu $3, $4, $5
+
+0x00 0xa4 0x1a 0xd0 # CHECK: nor $3, $4, $5
+
+0x00,0xa4,0x1a,0x90 # CHECK: or $3, $4, $5
+
+0x50 0x64 0x04 0xd2 # CHECK: ori $3, $4, 1234
+
+# CHECK: pref 1, 8($5)
+0x60 0x25 0x20 0x08
+
+0x00 0x83 0x11 0x40 # CHECK: seleqz $2, $3, $4
+
+0x00 0x83 0x11 0x80 # CHECK: selnez $2, $3, $4
+
+0x00 0xa4 0x19 0x90 # CHECK: sub $3, $4, $5
+
+0x00 0xa4 0x19 0xd0 # CHECK: subu $3, $4, $5
+
+0x00 0xa4 0x1b 0x10 # CHECK: xor $3, $4, $5
+
+0x70 0x64 0x04 0xd2 # CHECK: xori $3, $4, 1234
+
+0x00 0x64 0x2b 0x3c # CHECK: seb $3, $4
+
+0x00 0x64 0x3b 0x3c # CHECK: seh $3, $4
+
diff --git a/test/MC/Disassembler/Mips/micromips_le.txt b/test/MC/Disassembler/Mips/micromips_le.txt
index 9a8c4a94530c..3f3b3255972b 100644
--- a/test/MC/Disassembler/Mips/micromips_le.txt
+++ b/test/MC/Disassembler/Mips/micromips_le.txt
@@ -373,6 +373,15 @@
 # CHECK: nop
 0x00 0x00 0x00 0x00
 
+# CHECK: addiupc $2, 20
+0x00 0x79 0x05 0x00
+
+# CHECK: addiupc $7, 16777212
+0xbf 0x7b 0xff 0xff
+
+# CHECK: addiupc $7, -16777216
+0xc0 0x7b 0x00 0x00
+
 # CHECK: addu16 $6, $17, $4
 0x42 0x07
 
@@ -474,3 +483,24 @@
 
 # CHECK: bnez16 $6, 20
 0x0a 0xaf
+
+# CHECK: b16 132
+0x42 0xcc
+
+# CHECK: lw $3, 32($gp)
+0x88 0x65
+
+# CHECK: lwm16 $16, $17, $ra, 8($sp)
+0x12 0x45
+
+# CHECK: swm16 $16, $17, $ra, 8($sp)
+0x52 0x45
+
+# CHECK: break16 8
+0x88 0x46
+
+# CHECK: sdbbp16 14
+0xce 0x46
+
+# CHECK: movep $5, $6, $2, $3
+0x34 0x84
diff --git a/test/MC/Disassembler/Mips/mips3/valid-mips3.txt b/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
index cb602a35f7e6..0bec08550b30 100644
--- a/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
+++ b/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
@@ -70,6 +70,8 @@
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
+0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
+0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
 0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
diff --git a/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt b/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt
index a946ad0351f6..d0eb13c5afd5 100644
--- a/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt
+++ b/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt
@@ -1,4 +1,7 @@
 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 | FileCheck %s
+# Try a mips64* triple to confirm that mips* vs mips64* triples no longer have
+# an effect on the disassembler behaviour.
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mcpu=mips32r2 | FileCheck %s
 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
 0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
 0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
diff --git a/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
index ec75a2ea9d61..96378357d19b 100644
--- a/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
+++ b/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
@@ -1,4 +1,7 @@
 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 | FileCheck %s
+# Try a mips64* triple to confirm that mips* vs mips64* triples no longer have
+# an effect on the disassembler behaviour.
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips32r2 | FileCheck %s
 0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
 0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
 0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7
diff --git a/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt b/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt
new file mode 100644
index 000000000000..1909e2a21270
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt
@@ -0,0 +1,169 @@
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r3 | FileCheck %s
+0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
+0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
+0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
+0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
+0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
+0x67 0x45 0xc9 0x20 # CHECK: addi $9, $6, 17767
+0x67 0xc5 0xc9 0x24 # CHECK: addiu $9, $6, -15001
+0x21 0x48 0xc7 0x00 # CHECK: addu $9, $6, $7
+0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
+0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
+0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
+0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
+0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
+0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
+0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
+0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
+0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
+0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
+0x4c 0x01 0x26 0x15 # CHECK: bne $9, $6, 1332
+0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
+0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
+0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
+0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
+0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
+0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
+0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
+0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
+0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
+0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
+0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
+0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
+0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
+0x39 0x30 0x07 0x46 # CHECK: c.ngle.s $f6, $f7
+0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
+0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
+0x36 0x60 0x2e 0x46 # CHECK: c.ole.d $f12, $f14
+0x36 0x30 0x07 0x46 # CHECK: c.ole.s $f6, $f7
+0x34 0x60 0x2e 0x46 # CHECK: c.olt.d $f12, $f14
+0x34 0x30 0x07 0x46 # CHECK: c.olt.s $f6, $f7
+0x3a 0x60 0x2e 0x46 # CHECK: c.seq.d $f12, $f14
+0x3a 0x30 0x07 0x46 # CHECK: c.seq.s $f6, $f7
+0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
+0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
+0x33 0x60 0x2e 0x46 # CHECK: c.ueq.d $f12, $f14
+0x33 0xe0 0x12 0x46 # CHECK: c.ueq.s $f28, $f18
+0x37 0x60 0x2e 0x46 # CHECK: c.ule.d $f12, $f14
+0x37 0x30 0x07 0x46 # CHECK: c.ule.s $f6, $f7
+0x35 0x60 0x2e 0x46 # CHECK: c.ult.d $f12, $f14
+0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7
+0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14
+0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7
+0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14
+0x8e 0x39 0x00 0x46 # CHECK: ceil.w.s $f6, $f7
+0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7
+0x21 0x30 0xe6 0x70 # CHECK: clo $6, $7
+0x20 0x30 0xe6 0x70 # CHECK: clz $6, $7
+0x00 0x38 0xc6 0x44 # CHECK: ctc1 $6, $7
+0xa1 0x39 0x00 0x46 # CHECK: cvt.d.s $f6, $f7
+0x21 0x73 0x80 0x46 # CHECK: cvt.d.w $f12, $f14
+0x25 0x73 0x20 0x46 # CHECK: cvt.l.d $f12, $f14
+0xa5 0x39 0x00 0x46 # CHECK: cvt.l.s $f6, $f7
+0x20 0x73 0x20 0x46 # CHECK: cvt.s.d $f12, $f14
+0xa0 0x39 0x80 0x46 # CHECK: cvt.s.w $f6, $f7
+0x24 0x73 0x20 0x46 # CHECK: cvt.w.d $f12, $f14
+0xa4 0x39 0x00 0x46 # CHECK: cvt.w.s $f6, $f7
+0x00 0x60 0x7e 0x41 # CHECK: di $fp
+0x00 0x60 0x60 0x41 # CHECK: di
+0x20 0x60 0x6e 0x41 # CHECK: ei $14
+0x20 0x60 0x60 0x41 # CHECK: ei
+0x0f 0x73 0x20 0x46 # CHECK: floor.w.d $f12, $f14
+0x8f 0x39 0x00 0x46 # CHECK: floor.w.s $f6, $f7
+0x84 0x61 0x33 0x7d # CHECK: ins $19, $9, 6, 7
+0x4c 0x01 0x00 0x08 # CHECK: j 1328
+0x4c 0x01 0x00 0x0c # CHECK: jal 1328
+0x4c 0x01 0x00 0x74 # CHECK: jalx 1328
+0x09 0xf8 0xe0 0x00 # CHECK: jalr $7
+0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
+0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
+0x08 0x00 0xe0 0x00 # CHECK: jr $7
+0xc6 0x23 0xa4 0x80 # CHECK: lb $4, 9158($5)
+0x06 0x00 0xa4 0x90 # CHECK: lbu $4, 6($5)
+0xc6 0x23 0xe9 0xd4 # CHECK: ldc1 $f9, 9158($7)
+0x01 0x02 0xf7 0x4d # CHECK: ldxc1 $f8, $23($15)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0xc6 0x23 0xe9 0xc0 # CHECK: ll $9, 9158($7)
+0x67 0x45 0x06 0x3c # CHECK: lui $6, 17767
+0x05 0x00 0xa6 0x4c # CHECK: luxc1 $f0, $6($5)
+0x18 0x00 0xa4 0x8c # CHECK: lw $4, 24($5)
+0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
+0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
+0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
+0x00 0x05 0xcc 0x4d # CHECK: lwxc1 $f20, $12($14)
+0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
+0xa1 0xd4 0x94 0x4e # CHECK: madd.d $f18, $f20, $f26, $f20
+0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
+0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
+0x10 0x28 0x00 0x00 # CHECK: mfhi $5
+0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
+0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
+0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
+0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
+0xa9 0xf2 0x52 0x4c # CHECK: msub.d $f10, $f2, $f30, $f18
+0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
+0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
+0x11 0x00 0xe0 0x00 # CHECK: mthi $7
+0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
+0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
+0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
+0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
+0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
+0x18 0x00 0x65 0x00 # CHECK: mult $3, $5
+0x19 0x00 0x65 0x00 # CHECK: multu $3, $5
+0x07 0x73 0x20 0x46 # CHECK: neg.d $f12, $f14
+0x87 0x39 0x00 0x46 # CHECK: neg.s $f6, $f7
+0xb1 0x74 0x54 0x4d # CHECK: nmadd.d $f18, $f10, $f14, $f20
+0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7
+0xb9 0x87 0x1e 0x4d # CHECK: nmsub.d $f30, $f8, $f16, $f30
+0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
+0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
+0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
+0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
+0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
+0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
+0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
+0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7)
+0x09 0x40 0x24 0x4f # CHECK: sdxc1 $f8, $4($25)
+0x20 0x34 0x07 0x7c # CHECK: seb $6, $7
+0x20 0x36 0x07 0x7c # CHECK: seh $6, $7
+0xc6 0x23 0xa4 0xa4 # CHECK: sh $4, 9158($5)
+0xc0 0x21 0x03 0x00 # CHECK: sll $4, $3, 7
+0x04 0x10 0xa3 0x00 # CHECK: sllv $2, $3, $5
+0x2a 0x18 0x65 0x00 # CHECK: slt $3, $3, $5
+0x67 0x00 0x63 0x28 # CHECK: slti $3, $3, 103
+0x67 0x00 0x63 0x2c # CHECK: sltiu $3, $3, 103
+0x2b 0x18 0x65 0x00 # CHECK: sltu $3, $3, $5
+0x04 0x73 0x20 0x46 # CHECK: sqrt.d $f12, $f14
+0x84 0x39 0x00 0x46 # CHECK: sqrt.s $f6, $f7
+0xc3 0x21 0x03 0x00 # CHECK: sra $4, $3, 7
+0x07 0x10 0xa3 0x00 # CHECK: srav $2, $3, $5
+0xc2 0x21 0x03 0x00 # CHECK: srl $4, $3, 7
+0x06 0x10 0xa3 0x00 # CHECK: srlv $2, $3, $5
+0x01 0x62 0x2e 0x46 # CHECK: sub.d $f8, $f12, $f14
+0x41 0x32 0x07 0x46 # CHECK: sub.s $f9, $f6, $f7
+0x22 0x48 0xc7 0x00 # CHECK: sub $9, $6, $7
+0x23 0x20 0x65 0x00 # CHECK: subu $4, $3, $5
+0x0d 0x20 0xb8 0x4c # CHECK: suxc1 $f4, $24($5)
+0x18 0x00 0xa4 0xac # CHECK: sw $4, 24($5)
+0xc6 0x23 0xe9 0xe4 # CHECK: swc1 $f9, 9158($7)
+0x10 0x00 0xa4 0xa8 # CHECK: swl $4, 16($5)
+0x10 0x00 0xe6 0xb8 # CHECK: swr $6, 16($7)
+0x08 0xd0 0xd2 0x4e # CHECK: swxc1 $f26, $18($22)
+0xcf 0x01 0x00 0x00 # CHECK: sync 7
+0x0d 0x73 0x20 0x46 # CHECK: trunc.w.d $f12, $f14
+0x8d 0x39 0x00 0x46 # CHECK: trunc.w.s $f6, $f7
+0xa0 0x30 0x07 0x7c # CHECK: wsbh $6, $7
+0x26 0x18 0x65 0x00 # CHECK: xor $3, $3, $5
+0x67 0x45 0xc9 0x38 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt b/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
new file mode 100644
index 000000000000..a273c24f9c90
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
@@ -0,0 +1,169 @@
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r3 | FileCheck %s
+0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
+0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
+0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7
+0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14
+0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7
+0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767
+0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001
+0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7
+0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7
+0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767
+0x10 0x00 0x01 0x4c # CHECK: b 1332
+0x45 0x00 0x01 0x4c # CHECK: bc1f 1332
+0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332
+0x45 0x01 0x01 0x4c # CHECK: bc1t 1332
+0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332
+0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332
+0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
+0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
+0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332
+0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332
+0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332
+0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14
+0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7
+0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14
+0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7
+0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14
+0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
+0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14
+0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7
+0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14
+0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7
+0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14
+0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7
+0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14
+0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7
+0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14
+0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7
+0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14
+0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7
+0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14
+0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7
+0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14
+0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7
+0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14
+0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
+0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14
+0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18
+0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14
+0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7
+0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14
+0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7
+0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14
+0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
+0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14
+0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7
+0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7
+0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7
+0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7
+0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7
+0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7
+0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
+0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14
+0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7
+0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14
+0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7
+0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14
+0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7
+0x41 0x7e 0x60 0x00 # CHECK: di $fp
+0x41 0x60 0x60 0x00 # CHECK: di
+0x41 0x6e 0x60 0x20 # CHECK: ei $14
+0x41 0x60 0x60 0x20 # CHECK: ei
+0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14
+0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7
+0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7
+0x08 0x00 0x01 0x4c # CHECK: j 1328
+0x0c 0x00 0x01 0x4c # CHECK: jal 1328
+0x74 0x00 0x01 0x4c # CHECK: jalx 1328
+0x00 0xe0 0xf8 0x09 # CHECK: jalr $7
+0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
+0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
+0x00 0xe0 0x00 0x08 # CHECK: jr $7
+0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5)
+0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5)
+0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7)
+0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7)
+0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767
+0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
+0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5)
+0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
+0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
+0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
+0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
+0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
+0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
+0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
+0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
+0x00 0x00 0x28 0x10 # CHECK: mfhi $5
+0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
+0x00 0x00 0x28 0x12 # CHECK: mflo $5
+0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
+0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
+0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
+0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
+0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
+0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
+0x00 0xe0 0x00 0x11 # CHECK: mthi $7
+0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
+0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
+0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
+0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
+0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
+0x00 0x65 0x00 0x18 # CHECK: mult $3, $5
+0x00 0x65 0x00 0x19 # CHECK: multu $3, $5
+0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
+0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
+0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
+0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7
+0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
+0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5
+0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767
+0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7
+0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7
+0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14
+0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7
+0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5)
+0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5)
+0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7)
+0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7)
+0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25)
+0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7
+0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7
+0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5)
+0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7
+0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
+0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5
+0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103
+0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
+0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
+0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
+0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7
+0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7
+0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5
+0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7
+0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5
+0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14
+0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7
+0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7
+0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5
+0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5)
+0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5)
+0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7)
+0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5)
+0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7)
+0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22)
+0x00 0x00 0x01 0xcf # CHECK: sync 7
+0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14
+0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7
+0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7
+0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5
+0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt b/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt
new file mode 100644
index 000000000000..7623bba364fc
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt
@@ -0,0 +1,83 @@
+# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips32r3 | FileCheck %s
+# XFAIL: *
+0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
+0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
+0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
+0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
+0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
+0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
+0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
+0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
+0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
+0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
+0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
+0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
+0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
+0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
+0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
+0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
+0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
+0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
+0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
+0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
+0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
+0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
+0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
+0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
+0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
+0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
+0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
+0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
+0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8
+0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
+0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10
+0x46 0xcc 0x66 0x30 # CHECK: c.f.ps $fcc6, $f12, $f12
+0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20
+0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
+0x46 0xda 0x10 0x3d # CHECK: c.nge.ps $f2, $f26
+0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
+0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20
+0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
+0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8
+0x46 0xd0 0x32 0x34 # CHECK: c.olt.ps $fcc2, $f6, $f16
+0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
+0x46 0xc6 0x26 0x38 # CHECK: c.sf.ps $fcc6, $f4, $f6
+0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
+0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2
+0x46 0xc0 0x76 0x35 # CHECK: c.ult.ps $fcc6, $f14, $f0
+0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
+0x46 0x20 0x20 0x8a # CHECK: ceil.l.d $f2, $f4
+0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
+0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
+0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
+0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
+0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
+0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
+0x46 0x20 0x36 0x8b # CHECK: floor.l.d $f26, $f6
+0x46 0x00 0x23 0x0b # CHECK: floor.l.s $f12, $f4
+0x4c 0x42 0x75 0xa6 # CHECK: madd.ps $f22, $f2, $f14, $f2
+0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16
+0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
+0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
+0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
+0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
+0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16
+0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
+0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
+0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
+0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
+0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
+0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
+0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
+0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
+0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
+0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
+0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
+0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
+0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
+0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
diff --git a/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-le.txt b/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-le.txt
new file mode 100644
index 000000000000..62977dc3266e
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-le.txt
@@ -0,0 +1,169 @@
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r5 | FileCheck %s
+0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
+0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
+0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
+0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
+0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
+0x67 0x45 0xc9 0x20 # CHECK: addi $9, $6, 17767
+0x67 0xc5 0xc9 0x24 # CHECK: addiu $9, $6, -15001
+0x21 0x48 0xc7 0x00 # CHECK: addu $9, $6, $7
+0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
+0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
+0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
+0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
+0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
+0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
+0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
+0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
+0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
+0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
+0x4c 0x01 0x26 0x15 # CHECK: bne $9, $6, 1332
+0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
+0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
+0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
+0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
+0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
+0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
+0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
+0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
+0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
+0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
+0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
+0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
+0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
+0x39 0x30 0x07 0x46 # CHECK: c.ngle.s $f6, $f7
+0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
+0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
+0x36 0x60 0x2e 0x46 # CHECK: c.ole.d $f12, $f14
+0x36 0x30 0x07 0x46 # CHECK: c.ole.s $f6, $f7
+0x34 0x60 0x2e 0x46 # CHECK: c.olt.d $f12, $f14
+0x34 0x30 0x07 0x46 # CHECK: c.olt.s $f6, $f7
+0x3a 0x60 0x2e 0x46 # CHECK: c.seq.d $f12, $f14
+0x3a 0x30 0x07 0x46 # CHECK: c.seq.s $f6, $f7
+0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
+0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
+0x33 0x60 0x2e 0x46 # CHECK: c.ueq.d $f12, $f14
+0x33 0xe0 0x12 0x46 # CHECK: c.ueq.s $f28, $f18
+0x37 0x60 0x2e 0x46 # CHECK: c.ule.d $f12, $f14
+0x37 0x30 0x07 0x46 # CHECK: c.ule.s $f6, $f7
+0x35 0x60 0x2e 0x46 # CHECK: c.ult.d $f12, $f14
+0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7
+0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14
+0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7
+0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14
+0x8e 0x39 0x00 0x46 # CHECK: ceil.w.s $f6, $f7
+0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7
+0x21 0x30 0xe6 0x70 # CHECK: clo $6, $7
+0x20 0x30 0xe6 0x70 # CHECK: clz $6, $7
+0x00 0x38 0xc6 0x44 # CHECK: ctc1 $6, $7
+0xa1 0x39 0x00 0x46 # CHECK: cvt.d.s $f6, $f7
+0x21 0x73 0x80 0x46 # CHECK: cvt.d.w $f12, $f14
+0x25 0x73 0x20 0x46 # CHECK: cvt.l.d $f12, $f14
+0xa5 0x39 0x00 0x46 # CHECK: cvt.l.s $f6, $f7
+0x20 0x73 0x20 0x46 # CHECK: cvt.s.d $f12, $f14
+0xa0 0x39 0x80 0x46 # CHECK: cvt.s.w $f6, $f7
+0x24 0x73 0x20 0x46 # CHECK: cvt.w.d $f12, $f14
+0xa4 0x39 0x00 0x46 # CHECK: cvt.w.s $f6, $f7
+0x00 0x60 0x7e 0x41 # CHECK: di $fp
+0x00 0x60 0x60 0x41 # CHECK: di
+0x20 0x60 0x6e 0x41 # CHECK: ei $14
+0x20 0x60 0x60 0x41 # CHECK: ei
+0x0f 0x73 0x20 0x46 # CHECK: floor.w.d $f12, $f14
+0x8f 0x39 0x00 0x46 # CHECK: floor.w.s $f6, $f7
+0x84 0x61 0x33 0x7d # CHECK: ins $19, $9, 6, 7
+0x4c 0x01 0x00 0x08 # CHECK: j 1328
+0x4c 0x01 0x00 0x0c # CHECK: jal 1328
+0x4c 0x01 0x00 0x74 # CHECK: jalx 1328
+0x09 0xf8 0xe0 0x00 # CHECK: jalr $7
+0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
+0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
+0x08 0x00 0xe0 0x00 # CHECK: jr $7
+0xc6 0x23 0xa4 0x80 # CHECK: lb $4, 9158($5)
+0x06 0x00 0xa4 0x90 # CHECK: lbu $4, 6($5)
+0xc6 0x23 0xe9 0xd4 # CHECK: ldc1 $f9, 9158($7)
+0x01 0x02 0xf7 0x4d # CHECK: ldxc1 $f8, $23($15)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0xc6 0x23 0xe9 0xc0 # CHECK: ll $9, 9158($7)
+0x67 0x45 0x06 0x3c # CHECK: lui $6, 17767
+0x05 0x00 0xa6 0x4c # CHECK: luxc1 $f0, $6($5)
+0x18 0x00 0xa4 0x8c # CHECK: lw $4, 24($5)
+0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
+0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
+0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
+0x00 0x05 0xcc 0x4d # CHECK: lwxc1 $f20, $12($14)
+0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
+0xa1 0xd4 0x94 0x4e # CHECK: madd.d $f18, $f20, $f26, $f20
+0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
+0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
+0x10 0x28 0x00 0x00 # CHECK: mfhi $5
+0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
+0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
+0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
+0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
+0xa9 0xf2 0x52 0x4c # CHECK: msub.d $f10, $f2, $f30, $f18
+0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
+0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
+0x11 0x00 0xe0 0x00 # CHECK: mthi $7
+0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
+0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
+0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
+0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
+0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
+0x18 0x00 0x65 0x00 # CHECK: mult $3, $5
+0x19 0x00 0x65 0x00 # CHECK: multu $3, $5
+0x07 0x73 0x20 0x46 # CHECK: neg.d $f12, $f14
+0x87 0x39 0x00 0x46 # CHECK: neg.s $f6, $f7
+0xb1 0x74 0x54 0x4d # CHECK: nmadd.d $f18, $f10, $f14, $f20
+0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7
+0xb9 0x87 0x1e 0x4d # CHECK: nmsub.d $f30, $f8, $f16, $f30
+0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
+0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
+0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
+0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
+0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
+0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
+0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
+0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7)
+0x09 0x40 0x24 0x4f # CHECK: sdxc1 $f8, $4($25)
+0x20 0x34 0x07 0x7c # CHECK: seb $6, $7
+0x20 0x36 0x07 0x7c # CHECK: seh $6, $7
+0xc6 0x23 0xa4 0xa4 # CHECK: sh $4, 9158($5)
+0xc0 0x21 0x03 0x00 # CHECK: sll $4, $3, 7
+0x04 0x10 0xa3 0x00 # CHECK: sllv $2, $3, $5
+0x2a 0x18 0x65 0x00 # CHECK: slt $3, $3, $5
+0x67 0x00 0x63 0x28 # CHECK: slti $3, $3, 103
+0x67 0x00 0x63 0x2c # CHECK: sltiu $3, $3, 103
+0x2b 0x18 0x65 0x00 # CHECK: sltu $3, $3, $5
+0x04 0x73 0x20 0x46 # CHECK: sqrt.d $f12, $f14
+0x84 0x39 0x00 0x46 # CHECK: sqrt.s $f6, $f7
+0xc3 0x21 0x03 0x00 # CHECK: sra $4, $3, 7
+0x07 0x10 0xa3 0x00 # CHECK: srav $2, $3, $5
+0xc2 0x21 0x03 0x00 # CHECK: srl $4, $3, 7
+0x06 0x10 0xa3 0x00 # CHECK: srlv $2, $3, $5
+0x01 0x62 0x2e 0x46 # CHECK: sub.d $f8, $f12, $f14
+0x41 0x32 0x07 0x46 # CHECK: sub.s $f9, $f6, $f7
+0x22 0x48 0xc7 0x00 # CHECK: sub $9, $6, $7
+0x23 0x20 0x65 0x00 # CHECK: subu $4, $3, $5
+0x0d 0x20 0xb8 0x4c # CHECK: suxc1 $f4, $24($5)
+0x18 0x00 0xa4 0xac # CHECK: sw $4, 24($5)
+0xc6 0x23 0xe9 0xe4 # CHECK: swc1 $f9, 9158($7)
+0x10 0x00 0xa4 0xa8 # CHECK: swl $4, 16($5)
+0x10 0x00 0xe6 0xb8 # CHECK: swr $6, 16($7)
+0x08 0xd0 0xd2 0x4e # CHECK: swxc1 $f26, $18($22)
+0xcf 0x01 0x00 0x00 # CHECK: sync 7
+0x0d 0x73 0x20 0x46 # CHECK: trunc.w.d $f12, $f14
+0x8d 0x39 0x00 0x46 # CHECK: trunc.w.s $f6, $f7
+0xa0 0x30 0x07 0x7c # CHECK: wsbh $6, $7
+0x26 0x18 0x65 0x00 # CHECK: xor $3, $3, $5
+0x67 0x45 0xc9 0x38 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt b/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
new file mode 100644
index 000000000000..39c46440946e
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
@@ -0,0 +1,169 @@
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r5 | FileCheck %s
+0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
+0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
+0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7
+0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14
+0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7
+0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767
+0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001
+0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7
+0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7
+0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767
+0x10 0x00 0x01 0x4c # CHECK: b 1332
+0x45 0x00 0x01 0x4c # CHECK: bc1f 1332
+0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332
+0x45 0x01 0x01 0x4c # CHECK: bc1t 1332
+0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332
+0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332
+0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
+0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
+0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332
+0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332
+0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332
+0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14
+0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7
+0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14
+0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7
+0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14
+0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
+0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14
+0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7
+0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14
+0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7
+0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14
+0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7
+0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14
+0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7
+0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14
+0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7
+0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14
+0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7
+0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14
+0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7
+0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14
+0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7
+0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14
+0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
+0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14
+0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18
+0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14
+0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7
+0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14
+0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7
+0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14
+0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
+0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14
+0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7
+0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7
+0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7
+0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7
+0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7
+0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7
+0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
+0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14
+0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7
+0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14
+0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7
+0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14
+0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7
+0x41 0x7e 0x60 0x00 # CHECK: di $fp
+0x41 0x60 0x60 0x00 # CHECK: di
+0x41 0x6e 0x60 0x20 # CHECK: ei $14
+0x41 0x60 0x60 0x20 # CHECK: ei
+0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14
+0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7
+0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7
+0x08 0x00 0x01 0x4c # CHECK: j 1328
+0x0c 0x00 0x01 0x4c # CHECK: jal 1328
+0x74 0x00 0x01 0x4c # CHECK: jalx 1328
+0x00 0xe0 0xf8 0x09 # CHECK: jalr $7
+0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
+0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
+0x00 0xe0 0x00 0x08 # CHECK: jr $7
+0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5)
+0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5)
+0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7)
+0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7)
+0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767
+0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
+0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5)
+0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
+0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
+0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
+0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
+0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
+0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
+0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
+0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
+0x00 0x00 0x28 0x10 # CHECK: mfhi $5
+0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
+0x00 0x00 0x28 0x12 # CHECK: mflo $5
+0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
+0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
+0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
+0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
+0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
+0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
+0x00 0xe0 0x00 0x11 # CHECK: mthi $7
+0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
+0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
+0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
+0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
+0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
+0x00 0x65 0x00 0x18 # CHECK: mult $3, $5
+0x00 0x65 0x00 0x19 # CHECK: multu $3, $5
+0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
+0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
+0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
+0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7
+0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
+0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5
+0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767
+0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7
+0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7
+0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14
+0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7
+0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5)
+0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5)
+0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7)
+0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7)
+0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25)
+0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7
+0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7
+0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5)
+0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7
+0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
+0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5
+0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103
+0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
+0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
+0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
+0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7
+0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7
+0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5
+0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7
+0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5
+0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14
+0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7
+0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7
+0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5
+0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5)
+0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5)
+0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7)
+0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5)
+0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7)
+0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22)
+0x00 0x00 0x01 0xcf # CHECK: sync 7
+0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14
+0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7
+0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7
+0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5
+0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt b/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt
new file mode 100644
index 000000000000..27f5498ea661
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt
@@ -0,0 +1,83 @@
+# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips32r5 | FileCheck %s
+# XFAIL: *
+0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
+0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
+0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
+0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
+0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
+0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
+0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
+0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
+0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
+0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
+0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
+0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
+0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
+0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
+0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
+0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
+0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
+0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
+0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
+0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
+0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
+0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
+0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
+0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
+0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
+0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
+0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
+0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
+0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8
+0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
+0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10
+0x46 0xcc 0x66 0x30 # CHECK: c.f.ps $fcc6, $f12, $f12
+0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20
+0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
+0x46 0xda 0x10 0x3d # CHECK: c.nge.ps $f2, $f26
+0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
+0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20
+0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
+0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8
+0x46 0xd0 0x32 0x34 # CHECK: c.olt.ps $fcc2, $f6, $f16
+0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
+0x46 0xc6 0x26 0x38 # CHECK: c.sf.ps $fcc6, $f4, $f6
+0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
+0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2
+0x46 0xc0 0x76 0x35 # CHECK: c.ult.ps $fcc6, $f14, $f0
+0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
+0x46 0x20 0x20 0x8a # CHECK: ceil.l.d $f2, $f4
+0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
+0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
+0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
+0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
+0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
+0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
+0x46 0x20 0x36 0x8b # CHECK: floor.l.d $f26, $f6
+0x46 0x00 0x23 0x0b # CHECK: floor.l.s $f12, $f4
+0x4c 0x42 0x75 0xa6 # CHECK: madd.ps $f22, $f2, $f14, $f2
+0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16
+0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
+0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
+0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
+0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
+0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16
+0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
+0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
+0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
+0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
+0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
+0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
+0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
+0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
+0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
+0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
+0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
+0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
+0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
+0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
diff --git a/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt b/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt
index e5b95d8be554..e9afd03ddd60 100644
--- a/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt
+++ b/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt
@@ -1,7 +1,7 @@
 # Instructions that should be valid but currently fail for known reasons (e.g.
 # they aren't implemented yet).
 #
-# RUN: not llvm-mc %s -disassemble -triple=mips-unknown-linux -mcpu=mips32r6 | not FileCheck %s
+# RUN: llvm-mc %s -disassemble -triple=mips-unknown-linux -mcpu=mips32r6 | FileCheck %s
 # XFAIL: *
 0x20 0x40 0x00 0x01 # CHECK: bovc $0, $2, 4
 0x20 0x82 0x00 0x01 # CHECK: bovc $2, $4, 4
diff --git a/test/MC/Disassembler/Mips/mips4/valid-mips4.txt b/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
index c8c35e9334ed..2f7cbe9f9530 100644
--- a/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
+++ b/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
@@ -74,6 +74,8 @@
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
+0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
+0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
 0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
diff --git a/test/MC/Disassembler/Mips/mips64/valid-mips64.txt b/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
index b0809d8150f4..953e31f94634 100644
--- a/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
+++ b/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
@@ -86,6 +86,8 @@
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
+0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
+0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
 0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
diff --git a/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt b/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
index 405222e0f613..6509456b07ee 100644
--- a/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
+++ b/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
@@ -1,4 +1,7 @@
 # RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mcpu=mips64r2 | FileCheck %s
+# Try a mips* triple to confirm that mips* vs mips64* triples no longer have
+# an effect on the disassembler behaviour.
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips64r2 | FileCheck %s
 # CHECK: .text
 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
 0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
diff --git a/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt b/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
index d364238e885b..79fcc769063c 100644
--- a/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
+++ b/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
@@ -1,4 +1,7 @@
 # RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r2 | FileCheck %s
+# Try a mips* triple to confirm that mips* vs mips64* triples no longer have
+# an effect on the disassembler behaviour.
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips64r2 | FileCheck %s
 # CHECK: .text
 0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
 0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
@@ -89,6 +92,8 @@
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
+0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
+0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
 0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
diff --git a/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt b/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt
index bc69512c0130..cbc2eee3fe19 100644
--- a/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt
+++ b/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips32r2 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips64r2 | FileCheck %s
 # XFAIL: *
 0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
diff --git a/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
new file mode 100644
index 000000000000..52374af28933
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
@@ -0,0 +1,234 @@
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mcpu=mips64r3 | FileCheck %s
+# CHECK: .text
+0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
+0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
+0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
+0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
+0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
+0x67 0x45 0xc9 0x20 # CHECK: addi $9, $6, 17767
+0x67 0xc5 0xc9 0x24 # CHECK: addiu $9, $6, -15001
+0x21 0x48 0xc7 0x00 # CHECK: addu $9, $6, $7
+0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
+0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
+0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
+0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
+0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
+0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
+0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
+0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
+0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
+0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
+0x4c 0x01 0x26 0x15 # CHECK: bne $9, $6, 1332
+0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
+0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
+0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
+0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
+0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
+0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
+0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
+0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
+0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
+0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
+0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
+0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
+0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
+0x39 0x30 0x07 0x46 # CHECK: c.ngle.s $f6, $f7
+0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
+0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
+0x36 0x60 0x2e 0x46 # CHECK: c.ole.d $f12, $f14
+0x36 0x30 0x07 0x46 # CHECK: c.ole.s $f6, $f7
+0x34 0x60 0x2e 0x46 # CHECK: c.olt.d $f12, $f14
+0x34 0x30 0x07 0x46 # CHECK: c.olt.s $f6, $f7
+0x3a 0x60 0x2e 0x46 # CHECK: c.seq.d $f12, $f14
+0x3a 0x30 0x07 0x46 # CHECK: c.seq.s $f6, $f7
+0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
+0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
+0x33 0x60 0x2e 0x46 # CHECK: c.ueq.d $f12, $f14
+0x33 0xe0 0x12 0x46 # CHECK: c.ueq.s $f28, $f18
+0x37 0x60 0x2e 0x46 # CHECK: c.ule.d $f12, $f14
+0x37 0x30 0x07 0x46 # CHECK: c.ule.s $f6, $f7
+0x35 0x60 0x2e 0x46 # CHECK: c.ult.d $f12, $f14
+0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7
+0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14
+0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7
+0x4a 0x18 0x20 0x46 # CHECK: ceil.l.d $f1, $f3
+0x8a 0x6c 0x00 0x46 # CHECK: ceil.l.s $f18, $f13
+0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14
+0x8e 0x39 0x00 0x46 # CHECK: ceil.w.s $f6, $f7
+0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7
+0x21 0x30 0xe6 0x70 # CHECK: clo $6, $7
+0x20 0x30 0xe6 0x70 # CHECK: clz $6, $7
+0x00 0x38 0xc6 0x44 # CHECK: ctc1 $6, $7
+0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16
+0xa1 0x39 0x00 0x46 # CHECK: cvt.d.s $f6, $f7
+0x21 0x73 0x80 0x46 # CHECK: cvt.d.w $f12, $f14
+0x25 0x73 0x20 0x46 # CHECK: cvt.l.d $f12, $f14
+0xa5 0x39 0x00 0x46 # CHECK: cvt.l.s $f6, $f7
+0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
+0x20 0x73 0x20 0x46 # CHECK: cvt.s.d $f12, $f14
+0xa0 0x39 0x80 0x46 # CHECK: cvt.s.w $f6, $f7
+0x24 0x73 0x20 0x46 # CHECK: cvt.w.d $f12, $f14
+0xa4 0x39 0x00 0x46 # CHECK: cvt.w.s $f6, $f7
+0x2c 0x98 0x3f 0x00 # CHECK: dadd $19, $1, $ra
+0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
+0xc7 0x93 0xbd 0x63 # CHECK: daddi $sp, $sp, -27705
+0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
+0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
+0xc7 0x93 0xbd 0x63 # CHECK: daddi $sp, $sp, -27705
+0x16 0xee 0xda 0x66 # CHECK: daddiu $26, $22, -4586
+0x2d 0x98 0x3f 0x00 # CHECK: daddu $19, $1, $ra
+0x9f 0x46 0x58 0x64 # CHECK: daddiu $24, $2, 18079
+0x3f 0x69 0x73 0x66 # CHECK: daddiu $19, $19, 26943
+0x25 0x90 0xd2 0x70 # CHECK: dclo $18, $6
+0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
+0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
+0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17
+0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
+0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
+0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
+0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6
+0xb8 0x04 0x00 0x00 # CHECK: dsll $zero, $zero, 18
+0xb8 0x04 0x14 0x00 # CHECK: dsll $zero, $20, 18
+0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
+0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18
+0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18
+0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
+0xbb 0xe2 0x1c 0x00 # CHECK: dsra $gp, $gp, 10
+0xbb 0xe2 0x12 0x00 # CHECK: dsra $gp, $18, 10
+0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
+0xbf 0xe2 0x1c 0x00 # CHECK: dsra32 $gp, $gp, 10
+0xbf 0xe2 0x12 0x00 # CHECK: dsra32 $gp, $18, 10
+0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
+0xfa 0x9d 0x13 0x00 # CHECK: dsrl $19, $19, 23
+0xfa 0x9d 0x06 0x00 # CHECK: dsrl $19, $6, 23
+0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
+0xfe 0x9d 0x13 0x00 # CHECK: dsrl32 $19, $19, 23
+0xfe 0x9d 0x06 0x00 # CHECK: dsrl32 $19, $6, 23
+0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
+0x2e 0x38 0xc8 0x02 # CHECK: dsub $7, $22, $8
+0xa4 0x18 0x0e 0x7c # CHECK: dsbh $3, $14
+0x64 0x11 0x1d 0x7c # CHECK: dshd $2, $sp
+0x39 0x6c 0x9d 0x62 # CHECK: daddi $sp, $20, 27705
+0x39 0x6c 0xbd 0x63 # CHECK: daddi $sp, $sp, 27705
+0x2f 0x28 0xba 0x00 # CHECK: dsubu $5, $5, $26
+0x5f 0xec 0x6f 0x65 # CHECK: daddiu $15, $11, -5025
+0xea 0x11 0xce 0x65 # CHECK: daddiu $14, $14, 4586
+0x00 0x60 0x7e 0x41 # CHECK: di $fp
+0x00 0x60 0x60 0x41 # CHECK: di
+0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15
+0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
+0xfe 0x0b 0x21 0x00 # CHECK: drotr32 $1, $1, 15
+0xfe 0x0b 0x2e 0x00 # CHECK: drotr32 $1, $14, 15
+0x56 0x08 0xee 0x01 # CHECK: drotrv $1, $14, $15
+0x20 0x60 0x6e 0x41 # CHECK: ei $14
+0x20 0x60 0x60 0x41 # CHECK: ei
+0x8b 0x3e 0x20 0x46 # CHECK: floor.l.d $f26, $f7
+0x0b 0x2b 0x00 0x46 # CHECK: floor.l.s $f12, $f5
+0x0f 0x73 0x20 0x46 # CHECK: floor.w.d $f12, $f14
+0x8f 0x39 0x00 0x46 # CHECK: floor.w.s $f6, $f7
+0x84 0x61 0x33 0x7d # CHECK: ins $19, $9, 6, 7
+0x4c 0x01 0x00 0x08 # CHECK: j 1328
+0x4c 0x01 0x00 0x0c # CHECK: jal 1328
+0x4c 0x01 0x00 0x74 # CHECK: jalx 1328
+0x09 0xf8 0xe0 0x00 # CHECK: jalr $7
+0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
+0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
+0x08 0x00 0xe0 0x00 # CHECK: jr $7
+0xc6 0x23 0xa4 0x80 # CHECK: lb $4, 9158($5)
+0x06 0x00 0xa4 0x90 # CHECK: lbu $4, 6($5)
+0x1b 0x90 0x3d 0xde # CHECK: ld $sp, -28645($17)
+0xb9 0xef 0x18 0x6b # CHECK: ldl $24, -4167($24)
+0x6a 0x89 0x8e 0x6e # CHECK: ldr $14, -30358($20)
+0xc6 0x23 0xe9 0xd4 # CHECK: ldc1 $f9, 9158($7)
+0x01 0x02 0xf7 0x4d # CHECK: ldxc1 $f8, $23($15)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0xc6 0x23 0xe9 0xc0 # CHECK: ll $9, 9158($7)
+0x70 0xc6 0xe0 0xd3 # CHECK: lld $zero, -14736($ra)
+0x67 0x45 0x06 0x3c # CHECK: lui $6, 17767
+0x05 0x00 0xa6 0x4c # CHECK: luxc1 $f0, $6($5)
+0x18 0x00 0xa4 0x8c # CHECK: lw $4, 24($5)
+0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
+0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
+0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
+0x00 0x05 0xcc 0x4d # CHECK: lwxc1 $f20, $12($14)
+0xea 0xa1 0x73 0x9c # CHECK: lwu $19, -24086($3)
+0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
+0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
+0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
+0x10 0x28 0x00 0x00 # CHECK: mfhi $5
+0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
+0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
+0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
+0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
+0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
+0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
+0x11 0x00 0xe0 0x00 # CHECK: mthi $7
+0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
+0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
+0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
+0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
+0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
+0x18 0x00 0x65 0x00 # CHECK: mult $3, $5
+0x19 0x00 0x65 0x00 # CHECK: multu $3, $5
+0x07 0x73 0x20 0x46 # CHECK: neg.d $f12, $f14
+0x87 0x39 0x00 0x46 # CHECK: neg.s $f6, $f7
+0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7
+0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
+0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
+0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
+0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
+0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
+0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
+0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
+0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
+0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
+0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp)
+0xcb 0x16 0x4c 0xfd # CHECK: sd $12, 5835($10)
+0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7)
+0x1f 0xae 0xc7 0xb3 # CHECK: sdl $7, -20961($fp)
+0x39 0xb0 0x8b 0xb5 # CHECK: sdr $11, -20423($12)
+0x09 0x40 0x24 0x4f # CHECK: sdxc1 $f8, $4($25)
+0x20 0x34 0x07 0x7c # CHECK: seb $6, $7
+0x20 0x36 0x07 0x7c # CHECK: seh $6, $7
+0xc6 0x23 0xa4 0xa4 # CHECK: sh $4, 9158($5)
+0xc0 0x21 0x03 0x00 # CHECK: sll $4, $3, 7
+0x04 0x10 0xa3 0x00 # CHECK: sllv $2, $3, $5
+0x2a 0x18 0x65 0x00 # CHECK: slt $3, $3, $5
+0x67 0x00 0x63 0x28 # CHECK: slti $3, $3, 103
+0x67 0x00 0x63 0x2c # CHECK: sltiu $3, $3, 103
+0x2b 0x18 0x65 0x00 # CHECK: sltu $3, $3, $5
+0x04 0x73 0x20 0x46 # CHECK: sqrt.d $f12, $f14
+0x84 0x39 0x00 0x46 # CHECK: sqrt.s $f6, $f7
+0xc3 0x21 0x03 0x00 # CHECK: sra $4, $3, 7
+0x07 0x10 0xa3 0x00 # CHECK: srav $2, $3, $5
+0xc2 0x21 0x03 0x00 # CHECK: srl $4, $3, 7
+0x06 0x10 0xa3 0x00 # CHECK: srlv $2, $3, $5
+0x01 0x62 0x2e 0x46 # CHECK: sub.d $f8, $f12, $f14
+0x41 0x32 0x07 0x46 # CHECK: sub.s $f9, $f6, $f7
+0x22 0x48 0xc7 0x00 # CHECK: sub $9, $6, $7
+0x23 0x20 0x65 0x00 # CHECK: subu $4, $3, $5
+0x0d 0x20 0xb8 0x4c # CHECK: suxc1 $f4, $24($5)
+0x18 0x00 0xa4 0xac # CHECK: sw $4, 24($5)
+0xc6 0x23 0xe9 0xe4 # CHECK: swc1 $f9, 9158($7)
+0x10 0x00 0xa4 0xa8 # CHECK: swl $4, 16($5)
+0x10 0x00 0xe6 0xb8 # CHECK: swr $6, 16($7)
+0x08 0xd0 0xd2 0x4e # CHECK: swxc1 $f26, $18($22)
+0xcf 0x01 0x00 0x00 # CHECK: sync 7
+0xc9 0xbd 0x20 0x46 # CHECK: trunc.l.d $f23, $f23
+0x09 0xff 0x00 0x46 # CHECK: trunc.l.s $f28, $f31
+0x0d 0x73 0x20 0x46 # CHECK: trunc.w.d $f12, $f14
+0x8d 0x39 0x00 0x46 # CHECK: trunc.w.s $f6, $f7
+0xa0 0x30 0x07 0x7c # CHECK: wsbh $6, $7
+0x26 0x18 0x65 0x00 # CHECK: xor $3, $3, $5
+0x67 0x45 0xc9 0x38 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
new file mode 100644
index 000000000000..acd59fc721e3
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
@@ -0,0 +1,236 @@
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r3 | FileCheck %s
+# CHECK: .text
+0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
+0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
+0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7
+0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14
+0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7
+0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767
+0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001
+0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7
+0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7
+0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767
+0x10 0x00 0x01 0x4c # CHECK: b 1332
+0x45 0x00 0x01 0x4c # CHECK: bc1f 1332
+0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332
+0x45 0x01 0x01 0x4c # CHECK: bc1t 1332
+0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332
+0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332
+0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
+0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
+0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332
+0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332
+0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332
+0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14
+0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7
+0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14
+0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7
+0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14
+0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
+0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14
+0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7
+0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14
+0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7
+0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14
+0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7
+0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14
+0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7
+0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14
+0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7
+0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14
+0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7
+0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14
+0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7
+0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14
+0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7
+0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14
+0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
+0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14
+0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18
+0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14
+0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7
+0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14
+0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7
+0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14
+0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
+0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3
+0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
+0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14
+0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7
+0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7
+0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7
+0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7
+0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7
+0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
+0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7
+0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
+0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14
+0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7
+0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
+0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14
+0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7
+0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14
+0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7
+0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra
+0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705
+0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705
+0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705
+0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705
+0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705
+0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586
+0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra
+0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079
+0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
+0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6
+0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
+0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
+0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
+0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
+0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
+0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
+0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
+0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
+0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
+0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
+0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
+0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
+0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
+0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
+0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
+0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10
+0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10
+0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
+0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10
+0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10
+0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
+0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23
+0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23
+0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
+0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23
+0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23
+0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
+0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8
+0x7c 0x0e 0x18 0xa4 # CHECK: dsbh $3, $14
+0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
+0x62 0x9d 0x6c 0x39 # CHECK: daddi $sp, $20, 27705
+0x63 0xbd 0x6c 0x39 # CHECK: daddi $sp, $sp, 27705
+0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26
+0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025
+0x65 0xce 0x11 0xea # CHECK: daddiu $14, $14, 4586
+0x41 0x7e 0x60 0x00 # CHECK: di $fp
+0x41 0x60 0x60 0x00 # CHECK: di
+0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15
+0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15
+0x00 0x21 0x0b 0xfe # CHECK: drotr32 $1, $1, 15
+0x00 0x2e 0x0b 0xfe # CHECK: drotr32 $1, $14, 15
+0x01 0xee 0x08 0x56 # CHECK: drotrv $1, $14, $15
+0x41 0x6e 0x60 0x20 # CHECK: ei $14
+0x41 0x60 0x60 0x20 # CHECK: ei
+0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7
+0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5
+0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14
+0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7
+0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7
+0x08 0x00 0x01 0x4c # CHECK: j 1328
+0x0c 0x00 0x01 0x4c # CHECK: jal 1328
+0x74 0x00 0x01 0x4c # CHECK: jalx 1328
+0x00 0xe0 0xf8 0x09 # CHECK: jalr $7
+0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
+0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
+0x00 0xe0 0x00 0x08 # CHECK: jr $7
+0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5)
+0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5)
+0xde 0x3d 0x90 0x1b # CHECK: ld $sp, -28645($17)
+0x6b 0x18 0xef 0xb9 # CHECK: ldl $24, -4167($24)
+0x6e 0x8e 0x89 0x6a # CHECK: ldr $14, -30358($20)
+0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7)
+0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7)
+0xd3 0xe0 0xc6 0x70 # CHECK: lld $zero, -14736($ra)
+0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767
+0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
+0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5)
+0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
+0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
+0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
+0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
+0x9c 0x73 0xa1 0xea # CHECK: lwu $19, -24086($3)
+0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
+0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
+0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
+0x00 0x00 0x28 0x10 # CHECK: mfhi $5
+0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
+0x00 0x00 0x28 0x12 # CHECK: mflo $5
+0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
+0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
+0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
+0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
+0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
+0x00 0xe0 0x00 0x11 # CHECK: mthi $7
+0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
+0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
+0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
+0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
+0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
+0x00 0x65 0x00 0x18 # CHECK: mult $3, $5
+0x00 0x65 0x00 0x19 # CHECK: multu $3, $5
+0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
+0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
+0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7
+0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5
+0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767
+0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7
+0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7
+0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1
+0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5
+0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14
+0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7
+0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5)
+0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5)
+0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7)
+0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp)
+0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10)
+0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7)
+0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp)
+0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12)
+0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25)
+0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7
+0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7
+0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5)
+0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7
+0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
+0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5
+0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103
+0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
+0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
+0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
+0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7
+0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7
+0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5
+0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7
+0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5
+0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14
+0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7
+0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7
+0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5
+0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5)
+0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5)
+0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7)
+0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5)
+0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7)
+0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22)
+0x00 0x00 0x01 0xcf # CHECK: sync 7
+0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23
+0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
+0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14
+0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7
+0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7
+0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5
+0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt b/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt
new file mode 100644
index 000000000000..8c58eb1c9e3b
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt
@@ -0,0 +1,76 @@
+# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips64r3 | FileCheck %s
+# XFAIL: *
+0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
+0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
+0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
+0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
+0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
+0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
+0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
+0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
+0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
+0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
+0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
+0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
+0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
+0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
+0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
+0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
+0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
+0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
+0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
+0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
+0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
+0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
+0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
+0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
+0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
+0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
+0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
+0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
+0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8
+0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
+0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10
+0x46 0xcc 0x66 0x30 # CHECK: c.f.ps $fcc6, $f12, $f12
+0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20
+0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
+0x46 0xda 0x10 0x3d # CHECK: c.nge.ps $f2, $f26
+0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
+0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20
+0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
+0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8
+0x46 0xd0 0x32 0x34 # CHECK: c.olt.ps $fcc2, $f6, $f16
+0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
+0x46 0xc6 0x26 0x38 # CHECK: c.sf.ps $fcc6, $f4, $f6
+0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
+0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2
+0x46 0xc0 0x76 0x35 # CHECK: c.ult.ps $fcc6, $f14, $f0
+0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
+0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
+0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
+0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
+0x4c 0x42 0x75 0xa6 # CHECK: madd.ps $f22, $f2, $f14, $f2
+0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16
+0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
+0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
+0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
+0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
+0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
+0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16
+0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
+0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
+0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
+0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
+0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
+0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
+0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
+0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
+0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
+0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
+0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
+0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
diff --git a/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
new file mode 100644
index 000000000000..3d97a2b30ce3
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
@@ -0,0 +1,234 @@
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mcpu=mips64r5 | FileCheck %s
+# CHECK: .text
+0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
+0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
+0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
+0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
+0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
+0x67 0x45 0xc9 0x20 # CHECK: addi $9, $6, 17767
+0x67 0xc5 0xc9 0x24 # CHECK: addiu $9, $6, -15001
+0x21 0x48 0xc7 0x00 # CHECK: addu $9, $6, $7
+0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
+0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
+0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
+0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
+0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
+0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
+0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
+0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
+0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
+0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
+0x4c 0x01 0x26 0x15 # CHECK: bne $9, $6, 1332
+0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
+0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
+0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
+0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
+0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
+0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
+0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
+0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
+0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
+0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
+0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
+0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
+0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
+0x39 0x30 0x07 0x46 # CHECK: c.ngle.s $f6, $f7
+0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
+0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
+0x36 0x60 0x2e 0x46 # CHECK: c.ole.d $f12, $f14
+0x36 0x30 0x07 0x46 # CHECK: c.ole.s $f6, $f7
+0x34 0x60 0x2e 0x46 # CHECK: c.olt.d $f12, $f14
+0x34 0x30 0x07 0x46 # CHECK: c.olt.s $f6, $f7
+0x3a 0x60 0x2e 0x46 # CHECK: c.seq.d $f12, $f14
+0x3a 0x30 0x07 0x46 # CHECK: c.seq.s $f6, $f7
+0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
+0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
+0x33 0x60 0x2e 0x46 # CHECK: c.ueq.d $f12, $f14
+0x33 0xe0 0x12 0x46 # CHECK: c.ueq.s $f28, $f18
+0x37 0x60 0x2e 0x46 # CHECK: c.ule.d $f12, $f14
+0x37 0x30 0x07 0x46 # CHECK: c.ule.s $f6, $f7
+0x35 0x60 0x2e 0x46 # CHECK: c.ult.d $f12, $f14
+0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7
+0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14
+0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7
+0x4a 0x18 0x20 0x46 # CHECK: ceil.l.d $f1, $f3
+0x8a 0x6c 0x00 0x46 # CHECK: ceil.l.s $f18, $f13
+0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14
+0x8e 0x39 0x00 0x46 # CHECK: ceil.w.s $f6, $f7
+0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7
+0x21 0x30 0xe6 0x70 # CHECK: clo $6, $7
+0x20 0x30 0xe6 0x70 # CHECK: clz $6, $7
+0x00 0x38 0xc6 0x44 # CHECK: ctc1 $6, $7
+0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16
+0xa1 0x39 0x00 0x46 # CHECK: cvt.d.s $f6, $f7
+0x21 0x73 0x80 0x46 # CHECK: cvt.d.w $f12, $f14
+0x25 0x73 0x20 0x46 # CHECK: cvt.l.d $f12, $f14
+0xa5 0x39 0x00 0x46 # CHECK: cvt.l.s $f6, $f7
+0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
+0x20 0x73 0x20 0x46 # CHECK: cvt.s.d $f12, $f14
+0xa0 0x39 0x80 0x46 # CHECK: cvt.s.w $f6, $f7
+0x24 0x73 0x20 0x46 # CHECK: cvt.w.d $f12, $f14
+0xa4 0x39 0x00 0x46 # CHECK: cvt.w.s $f6, $f7
+0x2c 0x98 0x3f 0x00 # CHECK: dadd $19, $1, $ra
+0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
+0xc7 0x93 0xbd 0x63 # CHECK: daddi $sp, $sp, -27705
+0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
+0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
+0xc7 0x93 0xbd 0x63 # CHECK: daddi $sp, $sp, -27705
+0x16 0xee 0xda 0x66 # CHECK: daddiu $26, $22, -4586
+0x2d 0x98 0x3f 0x00 # CHECK: daddu $19, $1, $ra
+0x9f 0x46 0x58 0x64 # CHECK: daddiu $24, $2, 18079
+0x3f 0x69 0x73 0x66 # CHECK: daddiu $19, $19, 26943
+0x25 0x90 0xd2 0x70 # CHECK: dclo $18, $6
+0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
+0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
+0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17
+0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
+0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
+0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
+0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6
+0xb8 0x04 0x00 0x00 # CHECK: dsll $zero, $zero, 18
+0xb8 0x04 0x14 0x00 # CHECK: dsll $zero, $20, 18
+0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
+0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18
+0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18
+0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
+0xbb 0xe2 0x1c 0x00 # CHECK: dsra $gp, $gp, 10
+0xbb 0xe2 0x12 0x00 # CHECK: dsra $gp, $18, 10
+0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
+0xbf 0xe2 0x1c 0x00 # CHECK: dsra32 $gp, $gp, 10
+0xbf 0xe2 0x12 0x00 # CHECK: dsra32 $gp, $18, 10
+0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
+0xfa 0x9d 0x13 0x00 # CHECK: dsrl $19, $19, 23
+0xfa 0x9d 0x06 0x00 # CHECK: dsrl $19, $6, 23
+0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
+0xfe 0x9d 0x13 0x00 # CHECK: dsrl32 $19, $19, 23
+0xfe 0x9d 0x06 0x00 # CHECK: dsrl32 $19, $6, 23
+0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
+0x2e 0x38 0xc8 0x02 # CHECK: dsub $7, $22, $8
+0xa4 0x18 0x0e 0x7c # CHECK: dsbh $3, $14
+0x64 0x11 0x1d 0x7c # CHECK: dshd $2, $sp
+0x39 0x6c 0x9d 0x62 # CHECK: daddi $sp, $20, 27705
+0x39 0x6c 0xbd 0x63 # CHECK: daddi $sp, $sp, 27705
+0x2f 0x28 0xba 0x00 # CHECK: dsubu $5, $5, $26
+0x5f 0xec 0x6f 0x65 # CHECK: daddiu $15, $11, -5025
+0xea 0x11 0xce 0x65 # CHECK: daddiu $14, $14, 4586
+0x00 0x60 0x7e 0x41 # CHECK: di $fp
+0x00 0x60 0x60 0x41 # CHECK: di
+0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15
+0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
+0xfe 0x0b 0x21 0x00 # CHECK: drotr32 $1, $1, 15
+0xfe 0x0b 0x2e 0x00 # CHECK: drotr32 $1, $14, 15
+0x56 0x08 0xee 0x01 # CHECK: drotrv $1, $14, $15
+0x20 0x60 0x6e 0x41 # CHECK: ei $14
+0x20 0x60 0x60 0x41 # CHECK: ei
+0x8b 0x3e 0x20 0x46 # CHECK: floor.l.d $f26, $f7
+0x0b 0x2b 0x00 0x46 # CHECK: floor.l.s $f12, $f5
+0x0f 0x73 0x20 0x46 # CHECK: floor.w.d $f12, $f14
+0x8f 0x39 0x00 0x46 # CHECK: floor.w.s $f6, $f7
+0x84 0x61 0x33 0x7d # CHECK: ins $19, $9, 6, 7
+0x4c 0x01 0x00 0x08 # CHECK: j 1328
+0x4c 0x01 0x00 0x0c # CHECK: jal 1328
+0x4c 0x01 0x00 0x74 # CHECK: jalx 1328
+0x09 0xf8 0xe0 0x00 # CHECK: jalr $7
+0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
+0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
+0x08 0x00 0xe0 0x00 # CHECK: jr $7
+0xc6 0x23 0xa4 0x80 # CHECK: lb $4, 9158($5)
+0x06 0x00 0xa4 0x90 # CHECK: lbu $4, 6($5)
+0x1b 0x90 0x3d 0xde # CHECK: ld $sp, -28645($17)
+0xb9 0xef 0x18 0x6b # CHECK: ldl $24, -4167($24)
+0x6a 0x89 0x8e 0x6e # CHECK: ldr $14, -30358($20)
+0xc6 0x23 0xe9 0xd4 # CHECK: ldc1 $f9, 9158($7)
+0x01 0x02 0xf7 0x4d # CHECK: ldxc1 $f8, $23($15)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0xc6 0x23 0xe9 0xc0 # CHECK: ll $9, 9158($7)
+0x70 0xc6 0xe0 0xd3 # CHECK: lld $zero, -14736($ra)
+0x67 0x45 0x06 0x3c # CHECK: lui $6, 17767
+0x05 0x00 0xa6 0x4c # CHECK: luxc1 $f0, $6($5)
+0x18 0x00 0xa4 0x8c # CHECK: lw $4, 24($5)
+0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
+0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
+0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
+0x00 0x05 0xcc 0x4d # CHECK: lwxc1 $f20, $12($14)
+0xea 0xa1 0x73 0x9c # CHECK: lwu $19, -24086($3)
+0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
+0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
+0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
+0x10 0x28 0x00 0x00 # CHECK: mfhi $5
+0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
+0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
+0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
+0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
+0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
+0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
+0x11 0x00 0xe0 0x00 # CHECK: mthi $7
+0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
+0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
+0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
+0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
+0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
+0x18 0x00 0x65 0x00 # CHECK: mult $3, $5
+0x19 0x00 0x65 0x00 # CHECK: multu $3, $5
+0x07 0x73 0x20 0x46 # CHECK: neg.d $f12, $f14
+0x87 0x39 0x00 0x46 # CHECK: neg.s $f6, $f7
+0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7
+0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
+0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
+0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
+0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
+0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
+0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
+0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
+0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
+0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
+0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp)
+0xcb 0x16 0x4c 0xfd # CHECK: sd $12, 5835($10)
+0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7)
+0x1f 0xae 0xc7 0xb3 # CHECK: sdl $7, -20961($fp)
+0x39 0xb0 0x8b 0xb5 # CHECK: sdr $11, -20423($12)
+0x09 0x40 0x24 0x4f # CHECK: sdxc1 $f8, $4($25)
+0x20 0x34 0x07 0x7c # CHECK: seb $6, $7
+0x20 0x36 0x07 0x7c # CHECK: seh $6, $7
+0xc6 0x23 0xa4 0xa4 # CHECK: sh $4, 9158($5)
+0xc0 0x21 0x03 0x00 # CHECK: sll $4, $3, 7
+0x04 0x10 0xa3 0x00 # CHECK: sllv $2, $3, $5
+0x2a 0x18 0x65 0x00 # CHECK: slt $3, $3, $5
+0x67 0x00 0x63 0x28 # CHECK: slti $3, $3, 103
+0x67 0x00 0x63 0x2c # CHECK: sltiu $3, $3, 103
+0x2b 0x18 0x65 0x00 # CHECK: sltu $3, $3, $5
+0x04 0x73 0x20 0x46 # CHECK: sqrt.d $f12, $f14
+0x84 0x39 0x00 0x46 # CHECK: sqrt.s $f6, $f7
+0xc3 0x21 0x03 0x00 # CHECK: sra $4, $3, 7
+0x07 0x10 0xa3 0x00 # CHECK: srav $2, $3, $5
+0xc2 0x21 0x03 0x00 # CHECK: srl $4, $3, 7
+0x06 0x10 0xa3 0x00 # CHECK: srlv $2, $3, $5
+0x01 0x62 0x2e 0x46 # CHECK: sub.d $f8, $f12, $f14
+0x41 0x32 0x07 0x46 # CHECK: sub.s $f9, $f6, $f7
+0x22 0x48 0xc7 0x00 # CHECK: sub $9, $6, $7
+0x23 0x20 0x65 0x00 # CHECK: subu $4, $3, $5
+0x0d 0x20 0xb8 0x4c # CHECK: suxc1 $f4, $24($5)
+0x18 0x00 0xa4 0xac # CHECK: sw $4, 24($5)
+0xc6 0x23 0xe9 0xe4 # CHECK: swc1 $f9, 9158($7)
+0x10 0x00 0xa4 0xa8 # CHECK: swl $4, 16($5)
+0x10 0x00 0xe6 0xb8 # CHECK: swr $6, 16($7)
+0x08 0xd0 0xd2 0x4e # CHECK: swxc1 $f26, $18($22)
+0xcf 0x01 0x00 0x00 # CHECK: sync 7
+0xc9 0xbd 0x20 0x46 # CHECK: trunc.l.d $f23, $f23
+0x09 0xff 0x00 0x46 # CHECK: trunc.l.s $f28, $f31
+0x0d 0x73 0x20 0x46 # CHECK: trunc.w.d $f12, $f14
+0x8d 0x39 0x00 0x46 # CHECK: trunc.w.s $f6, $f7
+0xa0 0x30 0x07 0x7c # CHECK: wsbh $6, $7
+0x26 0x18 0x65 0x00 # CHECK: xor $3, $3, $5
+0x67 0x45 0xc9 0x38 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
new file mode 100644
index 000000000000..ce414edc345c
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
@@ -0,0 +1,236 @@
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r5 | FileCheck %s
+# CHECK: .text
+0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
+0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
+0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7
+0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14
+0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7
+0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767
+0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001
+0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7
+0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7
+0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767
+0x10 0x00 0x01 0x4c # CHECK: b 1332
+0x45 0x00 0x01 0x4c # CHECK: bc1f 1332
+0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332
+0x45 0x01 0x01 0x4c # CHECK: bc1t 1332
+0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332
+0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332
+0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
+0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
+0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332
+0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332
+0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332
+0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14
+0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7
+0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14
+0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7
+0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14
+0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
+0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14
+0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7
+0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14
+0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7
+0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14
+0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7
+0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14
+0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7
+0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14
+0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7
+0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14
+0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7
+0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14
+0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7
+0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14
+0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7
+0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14
+0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
+0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14
+0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18
+0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14
+0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7
+0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14
+0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7
+0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14
+0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
+0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3
+0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
+0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14
+0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7
+0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7
+0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7
+0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7
+0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7
+0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
+0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7
+0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
+0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14
+0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7
+0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
+0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14
+0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7
+0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14
+0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7
+0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra
+0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705
+0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705
+0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705
+0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705
+0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705
+0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586
+0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra
+0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079
+0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
+0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6
+0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
+0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
+0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
+0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
+0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
+0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
+0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
+0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
+0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
+0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
+0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
+0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
+0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
+0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
+0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
+0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10
+0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10
+0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
+0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10
+0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10
+0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
+0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23
+0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23
+0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
+0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23
+0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23
+0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
+0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8
+0x7c 0x0e 0x18 0xa4 # CHECK: dsbh $3, $14
+0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
+0x62 0x9d 0x6c 0x39 # CHECK: daddi $sp, $20, 27705
+0x63 0xbd 0x6c 0x39 # CHECK: daddi $sp, $sp, 27705
+0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26
+0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025
+0x65 0xce 0x11 0xea # CHECK: daddiu $14, $14, 4586
+0x41 0x7e 0x60 0x00 # CHECK: di $fp
+0x41 0x60 0x60 0x00 # CHECK: di
+0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15
+0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15
+0x00 0x21 0x0b 0xfe # CHECK: drotr32 $1, $1, 15
+0x00 0x2e 0x0b 0xfe # CHECK: drotr32 $1, $14, 15
+0x01 0xee 0x08 0x56 # CHECK: drotrv $1, $14, $15
+0x41 0x6e 0x60 0x20 # CHECK: ei $14
+0x41 0x60 0x60 0x20 # CHECK: ei
+0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7
+0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5
+0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14
+0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7
+0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7
+0x08 0x00 0x01 0x4c # CHECK: j 1328
+0x0c 0x00 0x01 0x4c # CHECK: jal 1328
+0x74 0x00 0x01 0x4c # CHECK: jalx 1328
+0x00 0xe0 0xf8 0x09 # CHECK: jalr $7
+0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
+0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
+0x00 0xe0 0x00 0x08 # CHECK: jr $7
+0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5)
+0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5)
+0xde 0x3d 0x90 0x1b # CHECK: ld $sp, -28645($17)
+0x6b 0x18 0xef 0xb9 # CHECK: ldl $24, -4167($24)
+0x6e 0x8e 0x89 0x6a # CHECK: ldr $14, -30358($20)
+0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7)
+0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7)
+0xd3 0xe0 0xc6 0x70 # CHECK: lld $zero, -14736($ra)
+0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767
+0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
+0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5)
+0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
+0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
+0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
+0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
+0x9c 0x73 0xa1 0xea # CHECK: lwu $19, -24086($3)
+0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
+0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
+0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
+0x00 0x00 0x28 0x10 # CHECK: mfhi $5
+0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
+0x00 0x00 0x28 0x12 # CHECK: mflo $5
+0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
+0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
+0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
+0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
+0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
+0x00 0xe0 0x00 0x11 # CHECK: mthi $7
+0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
+0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
+0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
+0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
+0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
+0x00 0x65 0x00 0x18 # CHECK: mult $3, $5
+0x00 0x65 0x00 0x19 # CHECK: multu $3, $5
+0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
+0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
+0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7
+0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5
+0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767
+0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7
+0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7
+0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1
+0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5
+0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14
+0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7
+0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5)
+0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5)
+0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7)
+0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp)
+0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10)
+0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7)
+0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp)
+0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12)
+0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25)
+0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7
+0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7
+0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5)
+0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7
+0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
+0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5
+0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103
+0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
+0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
+0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
+0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7
+0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7
+0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5
+0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7
+0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5
+0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14
+0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7
+0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7
+0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5
+0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5)
+0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5)
+0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7)
+0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5)
+0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7)
+0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22)
+0x00 0x00 0x01 0xcf # CHECK: sync 7
+0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23
+0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
+0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14
+0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7
+0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7
+0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5
+0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt b/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt
new file mode 100644
index 000000000000..b8a98bdf73e7
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt
@@ -0,0 +1,76 @@
+# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips64r5 | FileCheck %s
+# XFAIL: *
+0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
+0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
+0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
+0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
+0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
+0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
+0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
+0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
+0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
+0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
+0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
+0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
+0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
+0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
+0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
+0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
+0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
+0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
+0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
+0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
+0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
+0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
+0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
+0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
+0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
+0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
+0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
+0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
+0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8
+0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
+0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10
+0x46 0xcc 0x66 0x30 # CHECK: c.f.ps $fcc6, $f12, $f12
+0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20
+0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
+0x46 0xda 0x10 0x3d # CHECK: c.nge.ps $f2, $f26
+0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
+0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20
+0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
+0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8
+0x46 0xd0 0x32 0x34 # CHECK: c.olt.ps $fcc2, $f6, $f16
+0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
+0x46 0xc6 0x26 0x38 # CHECK: c.sf.ps $fcc6, $f4, $f6
+0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
+0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2
+0x46 0xc0 0x76 0x35 # CHECK: c.ult.ps $fcc6, $f14, $f0
+0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
+0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
+0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
+0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
+0x4c 0x42 0x75 0xa6 # CHECK: madd.ps $f22, $f2, $f14, $f2
+0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16
+0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
+0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
+0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
+0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
+0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
+0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16
+0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
+0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
+0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
+0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
+0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
+0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
+0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
+0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
+0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
+0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
+0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
+0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
diff --git a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
index b92c79387d63..4afd9cc5c4f5 100644
--- a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
+++ b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
@@ -1,9 +1,9 @@
 # RUN: llvm-mc %s -disassemble -triple=mipsel-unknown-linux -mcpu=mips64r6 | FileCheck %s
-0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
-0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100
 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
+0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100
 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2
 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56
+0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
 0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, -23
 0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1
 0x9b 0x14 0x11 0x04 # CHECK: bal 21104
@@ -19,148 +19,148 @@
 0x02 0x00 0xbf 0x49 # CHECK: bc2nez $31, 12
 0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 256
 0x4d 0x01 0x02 0x20 # CHECK: beqzalc $2, 1332
-0x40 0x00 0xa6 0x60 # CHECK: bnec $5, $6, 256
-0x4d 0x01 0x02 0x60 # CHECK: bnezalc $2, 1332
 0x90 0x46 0xa0 0xd8 # CHECK: beqzc $5, 72256
 0x40 0x00 0x43 0x58 # CHECK: bgec $2, $3, 256
 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 256
 0x4d 0x01 0x42 0x18 # CHECK: bgezalc $2, 1332
-0x90 0x46 0xa0 0xf8 # CHECK: bnezc $5, 72256
-0x40 0x00 0xa5 0x5c # CHECK: bltzc $5, 256
 0x40 0x00 0xa5 0x58 # CHECK: bgezc $5, 256
 0x4d 0x01 0x02 0x1c # CHECK: bgtzalc $2, 1332
-0x40 0x00 0x05 0x58 # CHECK: blezc $5, 256
-0x4d 0x01 0x42 0x1c # CHECK: bltzalc $2, 1332
 0x40 0x00 0x05 0x5c # CHECK: bgtzc $5, 256
 0x20 0x20 0x02 0x7c # CHECK: bitswap $4, $2
 0x4d 0x01 0x02 0x18 # CHECK: blezalc $2, 1332
+0x40 0x00 0x05 0x58 # CHECK: blezc $5, 256
 0x40 0x00 0xa6 0x5c # CHECK: bltc $5, $6, 256
 0x40 0x00 0xa6 0x1c # CHECK: bltuc $5, $6, 256
-0x01 0x00 0x00 0x60 # CHECK: bnvc $zero, $zero, 4
+0x4d 0x01 0x42 0x1c # CHECK: bltzalc $2, 1332
+0x40 0x00 0xa5 0x5c # CHECK: bltzc $5, 256
+0x40 0x00 0xa6 0x60 # CHECK: bnec $5, $6, 256
+0x4d 0x01 0x02 0x60 # CHECK: bnezalc $2, 1332
+0x90 0x46 0xa0 0xf8 # CHECK: bnezc $5, 72256
 0x01 0x00 0x40 0x60 # CHECK: bnvc $2, $zero, 4
 0x01 0x00 0x82 0x60 # CHECK: bnvc $4, $2, 4
-0x01 0x00 0x00 0x20 # CHECK: bovc $zero, $zero, 4
+0x01 0x00 0x00 0x60 # CHECK: bnvc $zero, $zero, 4
 0x01 0x00 0x40 0x20 # CHECK: bovc $2, $zero, 4
 0x01 0x00 0x82 0x20 # CHECK: bovc $4, $2, 4
-0x80 0x18 0x84 0x46 # CHECK: cmp.af.s $f2, $f3, $f4
+0x01 0x00 0x00 0x20 # CHECK: bovc $zero, $zero, 4
+0x25 0x04 0xa1 0x7c # CHECK: cache 1, 8($5)
+0x9b 0x20 0x20 0x46 # CHECK: class.d $f2, $f4
+0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4
+0x51 0x58 0xa0 0x00 # CHECK: clo $11, $5
+0x50 0xe8 0x80 0x03 # CHECK: clz $sp, $gp
 0x80 0x18 0xa4 0x46 # CHECK: cmp.af.d $f2, $f3, $f4
-0x81 0x18 0x84 0x46 # CHECK: cmp.un.s $f2, $f3, $f4
-0x81 0x18 0xa4 0x46 # CHECK: cmp.un.d $f2, $f3, $f4
-0x82 0x18 0x84 0x46 # CHECK: cmp.eq.s $f2, $f3, $f4
+0x80 0x18 0x84 0x46 # CHECK: cmp.af.s $f2, $f3, $f4
 0x82 0x18 0xa4 0x46 # CHECK: cmp.eq.d $f2, $f3, $f4
-0x83 0x18 0x84 0x46 # CHECK: cmp.ueq.s $f2, $f3, $f4
-0x83 0x18 0xa4 0x46 # CHECK: cmp.ueq.d $f2, $f3, $f4
-0x84 0x18 0x84 0x46 # CHECK: cmp.lt.s $f2, $f3, $f4
-0x84 0x18 0xa4 0x46 # CHECK: cmp.lt.d $f2, $f3, $f4
-0x85 0x18 0x84 0x46 # CHECK: cmp.ult.s $f2, $f3, $f4
-0x85 0x18 0xa4 0x46 # CHECK: cmp.ult.d $f2, $f3, $f4
-0x86 0x18 0x84 0x46 # CHECK: cmp.le.s $f2, $f3, $f4
+0x82 0x18 0x84 0x46 # CHECK: cmp.eq.s $f2, $f3, $f4
 0x86 0x18 0xa4 0x46 # CHECK: cmp.le.d $f2, $f3, $f4
-0x87 0x18 0x84 0x46 # CHECK: cmp.ule.s $f2, $f3, $f4
-0x87 0x18 0xa4 0x46 # CHECK: cmp.ule.d $f2, $f3, $f4
-0x88 0x18 0x84 0x46 # CHECK: cmp.saf.s $f2, $f3, $f4
+0x86 0x18 0x84 0x46 # CHECK: cmp.le.s $f2, $f3, $f4
+0x84 0x18 0xa4 0x46 # CHECK: cmp.lt.d $f2, $f3, $f4
+0x84 0x18 0x84 0x46 # CHECK: cmp.lt.s $f2, $f3, $f4
 0x88 0x18 0xa4 0x46 # CHECK: cmp.saf.d $f2, $f3, $f4
-0x89 0x18 0x84 0x46 # CHECK: cmp.sun.s $f2, $f3, $f4
-0x89 0x18 0xa4 0x46 # CHECK: cmp.sun.d $f2, $f3, $f4
-0x8a 0x18 0x84 0x46 # CHECK: cmp.seq.s $f2, $f3, $f4
+0x88 0x18 0x84 0x46 # CHECK: cmp.saf.s $f2, $f3, $f4
 0x8a 0x18 0xa4 0x46 # CHECK: cmp.seq.d $f2, $f3, $f4
-0x8b 0x18 0x84 0x46 # CHECK: cmp.sueq.s $f2, $f3, $f4
-0x8b 0x18 0xa4 0x46 # CHECK: cmp.sueq.d $f2, $f3, $f4
-0x8c 0x18 0x84 0x46 # CHECK: cmp.slt.s $f2, $f3, $f4
-0x8c 0x18 0xa4 0x46 # CHECK: cmp.slt.d $f2, $f3, $f4
-0x8d 0x18 0x84 0x46 # CHECK: cmp.sult.s $f2, $f3, $f4
-0x8d 0x18 0xa4 0x46 # CHECK: cmp.sult.d $f2, $f3, $f4
-0x8e 0x18 0x84 0x46 # CHECK: cmp.sle.s $f2, $f3, $f4
+0x8a 0x18 0x84 0x46 # CHECK: cmp.seq.s $f2, $f3, $f4
 0x8e 0x18 0xa4 0x46 # CHECK: cmp.sle.d $f2, $f3, $f4
-0x8f 0x18 0x84 0x46 # CHECK: cmp.sule.s $f2, $f3, $f4
+0x8e 0x18 0x84 0x46 # CHECK: cmp.sle.s $f2, $f3, $f4
+0x8c 0x18 0xa4 0x46 # CHECK: cmp.slt.d $f2, $f3, $f4
+0x8c 0x18 0x84 0x46 # CHECK: cmp.slt.s $f2, $f3, $f4
+0x8b 0x18 0xa4 0x46 # CHECK: cmp.sueq.d $f2, $f3, $f4
+0x8b 0x18 0x84 0x46 # CHECK: cmp.sueq.s $f2, $f3, $f4
 0x8f 0x18 0xa4 0x46 # CHECK: cmp.sule.d $f2, $f3, $f4
+0x8f 0x18 0x84 0x46 # CHECK: cmp.sule.s $f2, $f3, $f4
+0x8d 0x18 0xa4 0x46 # CHECK: cmp.sult.d $f2, $f3, $f4
+0x8d 0x18 0x84 0x46 # CHECK: cmp.sult.s $f2, $f3, $f4
+0x89 0x18 0xa4 0x46 # CHECK: cmp.sun.d $f2, $f3, $f4
+0x89 0x18 0x84 0x46 # CHECK: cmp.sun.s $f2, $f3, $f4
+0x83 0x18 0xa4 0x46 # CHECK: cmp.ueq.d $f2, $f3, $f4
+0x83 0x18 0x84 0x46 # CHECK: cmp.ueq.s $f2, $f3, $f4
+0x87 0x18 0xa4 0x46 # CHECK: cmp.ule.d $f2, $f3, $f4
+0x87 0x18 0x84 0x46 # CHECK: cmp.ule.s $f2, $f3, $f4
+0x85 0x18 0xa4 0x46 # CHECK: cmp.ult.d $f2, $f3, $f4
+0x85 0x18 0x84 0x46 # CHECK: cmp.ult.s $f2, $f3, $f4
+0x81 0x18 0xa4 0x46 # CHECK: cmp.un.d $f2, $f3, $f4
+0x81 0x18 0x84 0x46 # CHECK: cmp.un.s $f2, $f3, $f4
+0x78 0x56 0x66 0x04 # CHECK: dahi $3, 22136
 0x64 0x23 0x43 0x7c # CHECK: dalign $4, $2, $3, 5
 0x34 0x12 0x62 0x74 # CHECK: daui $3, $2, 4660
-0x78 0x56 0x66 0x04 # CHECK: dahi $3, 22136
 0x24 0x20 0x02 0x7c # CHECK: dbitswap $4, $2
-0x00 0x60 0x7e 0x41 # CHECK: di $fp
+0x53 0x90 0xc0 0x00 # CHECK: dclo $18, $6
+0x52 0x80 0x20 0x03 # CHECK: dclz $16, $25
+0x9e 0x10 0x64 0x00 # CHECK: ddiv $2, $3, $4
+0x9f 0x10 0x64 0x00 # CHECK: ddivu $2, $3, $4
 0x00 0x60 0x60 0x41 # CHECK: di
+0x00 0x60 0x7e 0x41 # CHECK: di $fp
 0x9a 0x10 0x64 0x00 # CHECK: div $2, $3, $4
 0x9b 0x10 0x64 0x00 # CHECK: divu $2, $3, $4
-0x20 0x60 0x6e 0x41 # CHECK: ei $14
-0x20 0x60 0x60 0x41 # CHECK: ei
-0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4
-0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4
-0x9e 0x10 0x64 0x00 # CHECK: ddiv $2, $3, $4
-0x9f 0x10 0x64 0x00 # CHECK: ddivu $2, $3, $4
+0xd5 0x10 0x64 0x00 # CHECK: dlsa $2, $3, $4, 3
 0xde 0x10 0x64 0x00 # CHECK: dmod $2, $3, $4
 0xdf 0x10 0x64 0x00 # CHECK: dmodu $2, $3, $4
-0xc5 0x10 0x64 0x00 # CHECK: lsa $2, $3, $4, 3
-0xd5 0x10 0x64 0x00 # CHECK: dlsa $2, $3, $4, 3
+0xdc 0x10 0x64 0x00 # CHECK: dmuh $2, $3, $4
+0xdd 0x10 0x64 0x00 # CHECK: dmuhu $2, $3, $4
+0x9c 0x10 0x64 0x00 # CHECK: dmul $2, $3, $4
+0x9d 0x10 0x64 0x00 # CHECK: dmulu $2, $3, $4
+0x20 0x60 0x60 0x41 # CHECK: ei
+0x20 0x60 0x6e 0x41 # CHECK: ei $14
+0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
+0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
+0x00 0x01 0x05 0xf8 # CHECK: jialc $5, 256
+0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256
+0x09 0x04 0x80 0x00 # CHECK: jr.hb $4
+0x43 0x0d 0xc8 0x49 # CHECK: ldc2 $8, -701($1)
 0x48 0x3c 0x58 0xec # CHECK: ldpc $2, 123456
+0xb6 0xb3 0x42 0x7e # CHECK: ll $2, -153($18)
+0x37 0x38 0xe0 0x7f # CHECK: lld $zero, 112($ra)
+0xc5 0x10 0x64 0x00 # CHECK: lsa $2, $3, $4, 3
+0xb7 0x34 0x52 0x49 # CHECK: lwc2 $18, -841($6)
 0x43 0x00 0x48 0xec # CHECK: lwpc $2, 268
 0x43 0x00 0x50 0xec # CHECK: lwupc $2, 268
-0x98 0x10 0x64 0x00 # CHECK: mul $2, $3, $4
-0xd8 0x10 0x64 0x00 # CHECK: muh $2, $3, $4
-0x99 0x10 0x64 0x00 # CHECK: mulu $2, $3, $4
-0xd9 0x10 0x64 0x00 # CHECK: muhu $2, $3, $4
-0x9c 0x10 0x64 0x00 # CHECK: dmul $2, $3, $4
-0xdc 0x10 0x64 0x00 # CHECK: dmuh $2, $3, $4
-0x9d 0x10 0x64 0x00 # CHECK: dmulu $2, $3, $4
-0xdd 0x10 0x64 0x00 # CHECK: dmuhu $2, $3, $4
-0x98 0x18 0x04 0x46 # CHECK: maddf.s $f2, $f3, $f4
 0x98 0x18 0x24 0x46 # CHECK: maddf.d $f2, $f3, $f4
-0x99 0x18 0x04 0x46 # CHECK: msubf.s $f2, $f3, $f4
-0x99 0x18 0x24 0x46 # CHECK: msubf.d $f2, $f3, $f4
-0x10 0x08 0x22 0x46 # CHECK: sel.d $f0, $f1, $f2
-0x10 0x08 0x02 0x46 # CHECK: sel.s $f0, $f1, $f2
-0x35 0x10 0x64 0x00 # CHECK: seleqz $2, $3, $4
-0x37 0x10 0x64 0x00 # CHECK: selnez $2, $3, $4
-0x1d 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4
+0x98 0x18 0x04 0x46 # CHECK: maddf.s $f2, $f3, $f4
 0x1d 0x10 0x24 0x46 # CHECK: max.d $f0, $f2, $f4
-0x1c 0x10 0x04 0x46 # CHECK: min.s $f0, $f2, $f4
-0x1c 0x10 0x24 0x46 # CHECK: min.d $f0, $f2, $f4
-0x1f 0x10 0x04 0x46 # CHECK: maxa.s $f0, $f2, $f4
+0x1d 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4
 0x1f 0x10 0x24 0x46 # CHECK: maxa.d $f0, $f2, $f4
-0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4
+0x1f 0x10 0x04 0x46 # CHECK: maxa.s $f0, $f2, $f4
+0x1c 0x10 0x24 0x46 # CHECK: min.d $f0, $f2, $f4
+0x1c 0x10 0x04 0x46 # CHECK: min.s $f0, $f2, $f4
 0x1e 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4
+0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4
+0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4
+0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4
+0x99 0x18 0x24 0x46 # CHECK: msubf.d $f2, $f3, $f4
+0x99 0x18 0x04 0x46 # CHECK: msubf.s $f2, $f3, $f4
+0xd8 0x10 0x64 0x00 # CHECK: muh $2, $3, $4
+0xd9 0x10 0x64 0x00 # CHECK: muhu $2, $3, $4
+0x98 0x10 0x64 0x00 # CHECK: mul $2, $3, $4
+0x99 0x10 0x64 0x00 # CHECK: mulu $2, $3, $4
 0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4
-0x14 0x10 0x04 0x46 # CHECK: seleqz.s $f0, $f2, $f4
-0x14 0x10 0x24 0x46 # CHECK: seleqz.d $f0, $f2, $f4
-0x17 0x10 0x04 0x46 # CHECK: selnez.s $f0, $f2, $f4
-0x17 0x10 0x24 0x46 # CHECK: selnez.d $f0, $f2, $f4
-0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4
+0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5)
 0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4
-0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4
-0x9b 0x20 0x20 0x46 # CHECK: class.d $f2, $f4
-0x09 0x04 0x80 0x00 # CHECK: jr.hb $4
-0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
-0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
-0xb6 0xb3 0x42 0x7e # CHECK: ll $2, -153($18)
-0x37 0x38 0xe0 0x7f # CHECK: lld $zero, 112($ra)
+0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4
 0x26 0xec 0x6f 0x7e # CHECK: sc $15, -40($19)
 0xa7 0xe6 0xaf 0x7f # CHECK: scd $15, -51($sp)
-0x51 0x58 0xa0 0x00 # CHECK: clo $11, $5
-0x50 0xe8 0x80 0x03 # CHECK: clz $sp, $gp
-0x53 0x90 0xc0 0x00 # CHECK: dclo $18, $6
-0x52 0x80 0x20 0x03 # CHECK: dclz $16, $25
-0x40 0x00 0x00 0x00 # CHECK: ssnop
 0x0e 0x00 0x00 0x00 # CHECK: sdbbp
 0x8e 0x08 0x00 0x00 # CHECK: sdbbp 34
+0x75 0x92 0xf4 0x49 # CHECK: sdc2 $20, 629($18)
+0x10 0x08 0x22 0x46 # CHECK: sel.d $f0, $f1, $f2
+0x10 0x08 0x02 0x46 # CHECK: sel.s $f0, $f1, $f2
+0x35 0x10 0x64 0x00 # CHECK: seleqz $2, $3, $4
+0x14 0x10 0x24 0x46 # CHECK: seleqz.d $f0, $f2, $f4
+0x14 0x10 0x04 0x46 # CHECK: seleqz.s $f0, $f2, $f4
+0x37 0x10 0x64 0x00 # CHECK: selnez $2, $3, $4
+0x17 0x10 0x24 0x46 # CHECK: selnez.d $f0, $f2, $f4
+0x17 0x10 0x04 0x46 # CHECK: selnez.s $f0, $f2, $f4
+0x40 0x00 0x00 0x00 # CHECK: ssnop
+0x30 0x81 0x79 0x49 # CHECK: swc2 $25, 304($16)
 0x0f 0x00 0x00 0x00 # CHECK: sync
 0x4f 0x00 0x00 0x00 # CHECK: sync 1
-0x34 0x00 0x03 0x00 # CHECK: teq $zero, $3
 0x34 0x9b 0xa7 0x00 # CHECK: teq $5, $7, 620
-0x30 0x00 0xea 0x00 # CHECK: tge $7, $10
+0x34 0x00 0x03 0x00 # CHECK: teq $zero, $3
 0x30 0x55 0xb3 0x00 # CHECK: tge $5, $19, 340
-0x31 0x00 0xdc 0x02 # CHECK: tgeu $22, $gp
+0x30 0x00 0xea 0x00 # CHECK: tge $7, $10
 0xf1 0x5e 0x8e 0x02 # CHECK: tgeu $20, $14, 379
+0x31 0x00 0xdc 0x02 # CHECK: tgeu $22, $gp
 0x32 0x00 0xed 0x01 # CHECK: tlt $15, $13
 0x72 0x21 0x53 0x00 # CHECK: tlt $2, $19, 133
 0x33 0x00 0x70 0x01 # CHECK: tltu $11, $16
 0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016
 0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17
 0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885
-0x43 0x0d 0xc8 0x49 # CHECK: ldc2 $8, -701($1)
-0xb7 0x34 0x52 0x49 # CHECK: lwc2 $18, -841($6)
-0x75 0x92 0xf4 0x49 # CHECK: sdc2 $20, 629($18)
-0x30 0x81 0x79 0x49 # CHECK: swc2 $25, 304($16)
-0x00 0x01 0x05 0xf8 # CHECK: jialc $5, 256
-0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256
-0x25 0x04 0xa1 0x7c # CHECK: cache 1, 8($5)
-0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5)
diff --git a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
index debbe5027ffc..c41ba990122e 100644
--- a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
+++ b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
@@ -1,9 +1,9 @@
 # RUN: llvm-mc %s -disassemble -triple=mips-unknown-linux -mcpu=mips64r6 | FileCheck %s
-0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4
-0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100
 0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10
+0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100
 0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2
 0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
+0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4
 0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23
 0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1
 0x04 0x11 0x14 0x9b # CHECK: bal 21104
@@ -19,148 +19,150 @@
 0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, 12
 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256
 0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, 1332
-0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256
-0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, 1332
 0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256
 0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 256
 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256
 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1332
-0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256
-0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256
 0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 256
 0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, 1332
-0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256
-0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, 1332
 0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256
 0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2
 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1332
+0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256
 0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256
 0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 256
-0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4
+0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, 1332
+0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256
+0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256
+0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, 1332
+0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256
 0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4
 0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4
-0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4
+0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4
 0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4
 0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4
-0x46 0x84 0x18 0x80 # CHECK: cmp.af.s $f2, $f3, $f4
+0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4
+0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
+0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4
+0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4
+0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5
+0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
 0x46 0xa4 0x18 0x80 # CHECK: cmp.af.d $f2, $f3, $f4
-0x46 0x84 0x18 0x81 # CHECK: cmp.un.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4
-0x46 0x84 0x18 0x82 # CHECK: cmp.eq.s $f2, $f3, $f4
+0x46 0x84 0x18 0x80 # CHECK: cmp.af.s $f2, $f3, $f4
 0x46 0xa4 0x18 0x82 # CHECK: cmp.eq.d $f2, $f3, $f4
-0x46 0x84 0x18 0x83 # CHECK: cmp.ueq.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4
-0x46 0x84 0x18 0x84 # CHECK: cmp.lt.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x84 # CHECK: cmp.lt.d $f2, $f3, $f4
-0x46 0x84 0x18 0x85 # CHECK: cmp.ult.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4
-0x46 0x84 0x18 0x86 # CHECK: cmp.le.s $f2, $f3, $f4
+0x46 0x84 0x18 0x82 # CHECK: cmp.eq.s $f2, $f3, $f4
 0x46 0xa4 0x18 0x86 # CHECK: cmp.le.d $f2, $f3, $f4
-0x46 0x84 0x18 0x87 # CHECK: cmp.ule.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4
-0x46 0x84 0x18 0x88 # CHECK: cmp.saf.s $f2, $f3, $f4
+0x46 0x84 0x18 0x86 # CHECK: cmp.le.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x84 # CHECK: cmp.lt.d $f2, $f3, $f4
+0x46 0x84 0x18 0x84 # CHECK: cmp.lt.s $f2, $f3, $f4
 0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4
-0x46 0x84 0x18 0x89 # CHECK: cmp.sun.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8a # CHECK: cmp.seq.s $f2, $f3, $f4
+0x46 0x84 0x18 0x88 # CHECK: cmp.saf.s $f2, $f3, $f4
 0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8b # CHECK: cmp.sueq.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8c # CHECK: cmp.slt.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8d # CHECK: cmp.sult.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8e # CHECK: cmp.sle.s $f2, $f3, $f4
+0x46 0x84 0x18 0x8a # CHECK: cmp.seq.s $f2, $f3, $f4
 0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8f # CHECK: cmp.sule.s $f2, $f3, $f4
+0x46 0x84 0x18 0x8e # CHECK: cmp.sle.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4
+0x46 0x84 0x18 0x8c # CHECK: cmp.slt.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4
+0x46 0x84 0x18 0x8b # CHECK: cmp.sueq.s $f2, $f3, $f4
 0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
+0x46 0x84 0x18 0x8f # CHECK: cmp.sule.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
+0x46 0x84 0x18 0x8d # CHECK: cmp.sult.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4
+0x46 0x84 0x18 0x89 # CHECK: cmp.sun.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4
+0x46 0x84 0x18 0x83 # CHECK: cmp.ueq.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4
+0x46 0x84 0x18 0x87 # CHECK: cmp.ule.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4
+0x46 0x84 0x18 0x85 # CHECK: cmp.ult.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4
+0x46 0x84 0x18 0x81 # CHECK: cmp.un.s $f2, $f3, $f4
+0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136
 0x7c 0x43 0x23 0x64 # CHECK: dalign $4, $2, $3, 5
 0x74 0x62 0x12 0x34 # CHECK: daui $3, $2, 4660
-0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136
 0x7c 0x02 0x20 0x24 # CHECK: dbitswap $4, $2
-0x41 0x7e 0x60 0x00 # CHECK: di $fp
+0x00 0xc0 0x90 0x53 # CHECK: dclo $18, $6
+0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25
+0x00 0x64 0x10 0x9e # CHECK: ddiv $2, $3, $4
+0x00 0x64 0x10 0x9f # CHECK: ddivu $2, $3, $4
 0x41 0x60 0x60 0x00 # CHECK: di
+0x41 0x7e 0x60 0x00 # CHECK: di $fp
 0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4
 0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4
-0x41 0x6e 0x60 0x20 # CHECK: ei $14
-0x41 0x60 0x60 0x20 # CHECK: ei
-0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4
-0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4
-0x00 0x64 0x10 0x9e # CHECK: ddiv $2, $3, $4
-0x00 0x64 0x10 0x9f # CHECK: ddivu $2, $3, $4
+0x00 0x64 0x10 0xd5 # CHECK: dlsa $2, $3, $4, 3
 0x00 0x64 0x10 0xde # CHECK: dmod $2, $3, $4
 0x00 0x64 0x10 0xdf # CHECK: dmodu $2, $3, $4
-0x00 0x64 0x10 0xc5 # CHECK: lsa $2, $3, $4, 3
-0x00 0x64 0x10 0xd5 # CHECK: dlsa $2, $3, $4, 3
+0x00 0x64 0x10 0xdc # CHECK: dmuh $2, $3, $4
+0x00 0x64 0x10 0xdd # CHECK: dmuhu $2, $3, $4
+0x00 0x64 0x10 0x9c # CHECK: dmul $2, $3, $4
+0x00 0x64 0x10 0x9d # CHECK: dmulu $2, $3, $4
+0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
+0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
+0x41 0x60 0x60 0x20 # CHECK: ei
+0x41 0x6e 0x60 0x20 # CHECK: ei $14
+0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
+0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
+0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
+0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
+0x00 0x80 0x04 0x09 # CHECK: jr.hb $4
+0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
 0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456
+0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18)
+0x7f 0xe0 0x38 0x37 # CHECK: lld $zero, 112($ra)
+0x00 0x64 0x10 0xc5 # CHECK: lsa $2, $3, $4, 3
+0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6)
 0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268
 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
-0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4
-0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4
-0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4
-0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4
-0x00 0x64 0x10 0x9c # CHECK: dmul $2, $3, $4
-0x00 0x64 0x10 0xdc # CHECK: dmuh $2, $3, $4
-0x00 0x64 0x10 0x9d # CHECK: dmulu $2, $3, $4
-0x00 0x64 0x10 0xdd # CHECK: dmuhu $2, $3, $4
-0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4
 0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4
-0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4
-0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4
-0x46 0x22 0x08 0x10 # CHECK: sel.d $f0, $f1, $f2
-0x46 0x02 0x08 0x10 # CHECK: sel.s $f0, $f1, $f2
-0x00 0x64 0x10 0x35 # CHECK: seleqz $2, $3, $4
-0x00 0x64 0x10 0x37 # CHECK: selnez $2, $3, $4
-0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4
+0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4
 0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4
-0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4
-0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4
-0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4
+0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4
 0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4
-0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4
+0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4
+0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4
+0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4
 0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4
+0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4
+0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4
+0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4
+0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4
+0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4
+0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4
+0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4
+0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4
+0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4
 0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4
-0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4
-0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4
-0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4
-0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4
-0x46 0x00 0x20 0x9a # CHECK: rint.s $f2, $f4
+0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
 0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4
-0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4
-0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4
-0x00 0x80 0x04 0x09 # CHECK: jr.hb $4
-0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
-0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
-0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18)
-0x7f 0xe0 0x38 0x37 # CHECK: lld $zero, 112($ra)
+0x46 0x00 0x20 0x9a # CHECK: rint.s $f2, $f4
 0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19)
 0x7f 0xaf 0xe6 0xa7 # CHECK: scd $15, -51($sp)
-0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5
-0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
-0x00 0xc0 0x90 0x53 # CHECK: dclo $18, $6
-0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25
-0x00 0x00 0x00 0x40 # CHECK: ssnop
 0x00 0x00 0x00 0x0e # CHECK: sdbbp
 0x00 0x00 0x08 0x8e # CHECK: sdbbp 34
+0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
+0x46 0x22 0x08 0x10 # CHECK: sel.d $f0, $f1, $f2
+0x46 0x02 0x08 0x10 # CHECK: sel.s $f0, $f1, $f2
+0x00 0x64 0x10 0x35 # CHECK: seleqz $2, $3, $4
+0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4
+0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4
+0x00 0x64 0x10 0x37 # CHECK: selnez $2, $3, $4
+0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4
+0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4
+0x00 0x00 0x00 0x40 # CHECK: ssnop
+0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16)
 0x00 0x00 0x00 0x0f # CHECK: sync
 0x00 0x00 0x00 0x4f # CHECK: sync 1
-0x00 0x03 0x00 0x34 # CHECK: teq $zero, $3
 0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620
-0x00 0xea 0x00 0x30 # CHECK: tge $7, $10
+0x00 0x03 0x00 0x34 # CHECK: teq $zero, $3
 0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340
-0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp
+0x00 0xea 0x00 0x30 # CHECK: tge $7, $10
 0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379
+0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp
 0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13
 0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133
 0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16
 0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016
 0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
 0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
-0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
-0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6)
-0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
-0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16)
-0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
-0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
-0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
-0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
diff --git a/test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt b/test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt
index e8982472029e..8ca8b815414c 100644
--- a/test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt
+++ b/test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt
@@ -1,7 +1,7 @@
 # Instructions that should be valid but currently fail for known reasons (e.g.
 # they aren't implemented yet).
 #
-# RUN: not llvm-mc %s -disassemble -triple=mips-unknown-linux -mcpu=mips64r6 | not FileCheck %s
+# RUN: llvm-mc %s -disassemble -triple=mips-unknown-linux -mcpu=mips64r6 | FileCheck %s
 # XFAIL: *
 0x20 0x40 0x00 0x01 # CHECK: bovc $0, $2, 4
 0x20 0x82 0x00 0x01 # CHECK: bovc $2, $4, 4
diff --git a/test/MC/Disassembler/PowerPC/dcbt.txt b/test/MC/Disassembler/PowerPC/dcbt.txt
new file mode 100644
index 000000000000..3289637ca605
--- /dev/null
+++ b/test/MC/Disassembler/PowerPC/dcbt.txt
@@ -0,0 +1,20 @@
+# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s -check-prefix=SERVER
+# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=a2 | FileCheck %s -check-prefix=EMBEDDED
+
+# SERVER: dcbt 2, 3
+# EMBEDDED: dcbt 2, 3
+0x7c 0x02 0x1a 0x2c
+
+# SERVER: dcbtst 2, 3
+# EMBEDDED: dcbtst 2, 3
+0x7c 0x02 0x19 0xec
+
+# SERVER: dcbt 2, 3, 10
+# EMBEDDED: dcbt 10, 2, 3
+0x7d 0x42 0x1a 0x2c
+
+# SERVER: dcbtst 2, 3, 10
+# EMBEDDED: dcbtst 10, 2, 3
+0x7d 0x42 0x19 0xec
+
+
diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-4xx.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-4xx.txt
index 92e88f8e7a58..22eef5669c92 100644
--- a/test/MC/Disassembler/PowerPC/ppc64-encoding-4xx.txt
+++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-4xx.txt
@@ -5,14 +5,14 @@
 # CHECK: mtdcr 178, 3
 0x7c 0x72 0x2b 0x86
 
-# CHECK: tlbre 2, 3, 0
+# CHECK: tlbrehi 2, 3
 0x7c 0x43 0x07 0x64
-# CHECK: tlbre 2, 3, 1
+# CHECK: tlbrelo 2, 3
 0x7c 0x43 0x0f 0x64
 
-# CHECK: tlbwe 2, 3, 0
+# CHECK: tlbwehi 2, 3
 0x7c 0x43 0x07 0xa4
-# CHECK: tlbwe 2, 3, 1
+# CHECK: tlbwelo 2, 3
 0x7c 0x43 0x0f 0xa4
 
 # CHECK: tlbsx 2, 3, 1
diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
index 7a30b5cb2b69..480681c67f1d 100644
--- a/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
+++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
@@ -12,6 +12,12 @@
 # CHECK: dcbtst 2, 3                     
 0x7c 0x02 0x19 0xec
 
+# CHECK: dcbt 2, 3, 10
+0x7d 0x42 0x1a 0x2c
+
+# CHECK: dcbtst 2, 3, 10
+0x7d 0x42 0x19 0xec
+
 # CHECK: dcbz 2, 3                       
 0x7c 0x02 0x1f 0xec
 
@@ -27,13 +33,13 @@
 # CHECK: stdcx. 2, 3, 4                  
 0x7c 0x43 0x21 0xad
 
-# CHECK: sync 2                          
+# CHECK: ptesync
 0x7c 0x40 0x04 0xac
 
 # CHECK: eieio                           
 0x7c 0x00 0x06 0xac
 
-# CHECK: wait 2                          
+# CHECK: waitimpl
 0x7c 0x40 0x00 0x7c
 
 # CHECK: mbar 1
@@ -42,31 +48,49 @@
 # CHECK: dcbf 2, 3                       
 0x7c 0x02 0x18 0xac
 
-# CHECK: lwarx 2, 3, 4                   
+# CHECK: lbarx 2, 3, 4
+0x7c 0x43 0x20 0x68
+
+# CHECK: lharx 2, 3, 4
+0x7c 0x43 0x20 0xe8
+
+# CHECK: lwarx 2, 3, 4
 0x7c 0x43 0x20 0x28
 
-# CHECK: ldarx 2, 3, 4                   
+# CHECK: ldarx 2, 3, 4
 0x7c 0x43 0x20 0xa8
 
-# CHECK: sync 0                          
+# CHECK: lbarx 2, 3, 4, 1
+0x7c 0x43 0x20 0x69
+
+# CHECK: lharx 2, 3, 4, 1
+0x7c 0x43 0x20 0xe9
+
+# CHECK: lwarx 2, 3, 4, 1
+0x7c 0x43 0x20 0x29
+
+# CHECK: ldarx 2, 3, 4, 1
+0x7c 0x43 0x20 0xa9
+
+# CHECK: sync
 0x7c 0x00 0x04 0xac
 
-# CHECK: sync 0                          
+# CHECK: sync
 0x7c 0x00 0x04 0xac
 
-# CHECK: sync 1                          
+# CHECK: lwsync
 0x7c 0x20 0x04 0xac
 
-# CHECK: sync 2                          
+# CHECK: ptesync
 0x7c 0x40 0x04 0xac
 
-# CHECK: wait 0                          
+# CHECK: wait
 0x7c 0x00 0x00 0x7c
 
-# CHECK: wait 1                          
+# CHECK: waitrsv
 0x7c 0x20 0x00 0x7c
 
-# CHECK: wait 2                          
+# CHECK: waitimpl
 0x7c 0x40 0x00 0x7c
 
 # CHECK: mftb 2, 123                     
@@ -75,6 +99,6 @@
 # CHECK: mftb 2, 268                     
 0x7c 0x4c 0x42 0xe6
 
-# CHECK: mftb 2, 269                     
+# CHECK: mftbu 2
 0x7c 0x4d 0x42 0xe6
 
diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt
index 7996ed178a12..04308f951ec7 100644
--- a/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt
+++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt
@@ -1,6 +1,6 @@
 # RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s
 
-# CHECK: mtmsr 4, 0                       
+# CHECK: mtmsr 4
 0x7c 0x80 0x01 0x24
 
 # CHECK: mtmsr 4, 1                       
@@ -9,7 +9,7 @@
 # CHECK: mfmsr 4                         
 0x7c 0x80 0x00 0xa6
 
-# CHECK: mtmsrd 4, 0                     
+# CHECK: mtmsrd 4
 0x7c 0x80 0x01 0x64
 
 # CHECK: mtmsrd 4, 1                     
@@ -60,7 +60,7 @@
 # CHECK: mtspr 22, 4                     
 0x7c 0x96 0x03 0xa6
 
-# CHECK: mfspr 4, 287                    
+# CHECK: mfpvr 4
 0x7c 0x9f 0x42 0xa6
 
 # CHECK: mfspr 4, 25                     
@@ -99,10 +99,10 @@
 # CHECK: tlbiel 4                        
 0x7c 0x00 0x22 0x24
 
-# CHECK: tlbie 4,0                       
+# CHECK: tlbie 4
 0x7c 0x00 0x22 0x64
 
-# CHECK: tlbie 4,0                       
+# CHECK: tlbie 4
 0x7c 0x00 0x22 0x64
 
 # CHECK: rfi
diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
index 4f10c742db97..e976aab49661 100644
--- a/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
+++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
@@ -1,155 +1,155 @@
 # RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s
 
 # FIXME: decode as beqlr 0
-# CHECK: bclr 12, 2, 0
+# CHECK: bclr 12, 2
 0x4d 0x82 0x00 0x20
 
 # FIXME: decode as beqlr 1
-# CHECK: bclr 12, 6, 0
+# CHECK: bclr 12, 6
 0x4d 0x86 0x00 0x20
 
 # FIXME: decode as beqlr 2
-# CHECK: bclr 12, 10, 0
+# CHECK: bclr 12, 10
 0x4d 0x8a 0x00 0x20
 
 # FIXME: decode as beqlr 3
-# CHECK: bclr 12, 14, 0
+# CHECK: bclr 12, 14
 0x4d 0x8e 0x00 0x20
 
 # FIXME: decode as beqlr 4
-# CHECK: bclr 12, 18, 0
+# CHECK: bclr 12, 18
 0x4d 0x92 0x00 0x20
 
 # FIXME: decode as beqlr 5
-# CHECK: bclr 12, 22, 0
+# CHECK: bclr 12, 22
 0x4d 0x96 0x00 0x20
 
 # FIXME: decode as beqlr 6
-# CHECK: bclr 12, 26, 0
+# CHECK: bclr 12, 26
 0x4d 0x9a 0x00 0x20
 
 # FIXME: decode as beqlr 7
-# CHECK: bclr 12, 30, 0
+# CHECK: bclr 12, 30
 0x4d 0x9e 0x00 0x20
 
-# CHECK: bclr 12, 0, 0
+# CHECK: bclr 12, 0
 0x4d 0x80 0x00 0x20
 
-# CHECK: bclr 12, 1, 0
+# CHECK: bclr 12, 1
 0x4d 0x81 0x00 0x20
 
-# CHECK: bclr 12, 2, 0
+# CHECK: bclr 12, 2
 0x4d 0x82 0x00 0x20
 
-# CHECK: bclr 12, 3, 0
+# CHECK: bclr 12, 3
 0x4d 0x83 0x00 0x20
 
-# CHECK: bclr 12, 3, 0
+# CHECK: bclr 12, 3
 0x4d 0x83 0x00 0x20
 
-# CHECK: bclr 12, 4, 0
+# CHECK: bclr 12, 4
 0x4d 0x84 0x00 0x20
 
-# CHECK: bclr 12, 5, 0
+# CHECK: bclr 12, 5
 0x4d 0x85 0x00 0x20
 
-# CHECK: bclr 12, 6, 0
+# CHECK: bclr 12, 6
 0x4d 0x86 0x00 0x20
 
-# CHECK: bclr 12, 7, 0
+# CHECK: bclr 12, 7
 0x4d 0x87 0x00 0x20
 
-# CHECK: bclr 12, 7, 0
+# CHECK: bclr 12, 7
 0x4d 0x87 0x00 0x20
 
-# CHECK: bclr 12, 8, 0
+# CHECK: bclr 12, 8
 0x4d 0x88 0x00 0x20
 
-# CHECK: bclr 12, 9, 0
+# CHECK: bclr 12, 9
 0x4d 0x89 0x00 0x20
 
-# CHECK: bclr 12, 10, 0
+# CHECK: bclr 12, 10
 0x4d 0x8a 0x00 0x20
 
-# CHECK: bclr 12, 11, 0
+# CHECK: bclr 12, 11
 0x4d 0x8b 0x00 0x20
 
-# CHECK: bclr 12, 11, 0
+# CHECK: bclr 12, 11
 0x4d 0x8b 0x00 0x20
 
-# CHECK: bclr 12, 12, 0
+# CHECK: bclr 12, 12
 0x4d 0x8c 0x00 0x20
 
-# CHECK: bclr 12, 13, 0
+# CHECK: bclr 12, 13
 0x4d 0x8d 0x00 0x20
 
-# CHECK: bclr 12, 14, 0
+# CHECK: bclr 12, 14
 0x4d 0x8e 0x00 0x20
 
-# CHECK: bclr 12, 15, 0
+# CHECK: bclr 12, 15
 0x4d 0x8f 0x00 0x20
 
-# CHECK: bclr 12, 15, 0
+# CHECK: bclr 12, 15
 0x4d 0x8f 0x00 0x20
 
-# CHECK: bclr 12, 16, 0
+# CHECK: bclr 12, 16
 0x4d 0x90 0x00 0x20
 
-# CHECK: bclr 12, 17, 0
+# CHECK: bclr 12, 17
 0x4d 0x91 0x00 0x20
 
-# CHECK: bclr 12, 18, 0
+# CHECK: bclr 12, 18
 0x4d 0x92 0x00 0x20
 
-# CHECK: bclr 12, 19, 0
+# CHECK: bclr 12, 19
 0x4d 0x93 0x00 0x20
 
-# CHECK: bclr 12, 19, 0
+# CHECK: bclr 12, 19
 0x4d 0x93 0x00 0x20
 
-# CHECK: bclr 12, 20, 0
+# CHECK: bclr 12, 20
 0x4d 0x94 0x00 0x20
 
-# CHECK: bclr 12, 21, 0
+# CHECK: bclr 12, 21
 0x4d 0x95 0x00 0x20
 
-# CHECK: bclr 12, 22, 0
+# CHECK: bclr 12, 22
 0x4d 0x96 0x00 0x20
 
-# CHECK: bclr 12, 23, 0
+# CHECK: bclr 12, 23
 0x4d 0x97 0x00 0x20
 
-# CHECK: bclr 12, 23, 0
+# CHECK: bclr 12, 23
 0x4d 0x97 0x00 0x20
 
-# CHECK: bclr 12, 24, 0
+# CHECK: bclr 12, 24
 0x4d 0x98 0x00 0x20
 
-# CHECK: bclr 12, 25, 0
+# CHECK: bclr 12, 25
 0x4d 0x99 0x00 0x20
 
-# CHECK: bclr 12, 26, 0
+# CHECK: bclr 12, 26
 0x4d 0x9a 0x00 0x20
 
-# CHECK: bclr 12, 27, 0
+# CHECK: bclr 12, 27
 0x4d 0x9b 0x00 0x20
 
-# CHECK: bclr 12, 27, 0
+# CHECK: bclr 12, 27
 0x4d 0x9b 0x00 0x20
 
-# CHECK: bclr 12, 28, 0
+# CHECK: bclr 12, 28
 0x4d 0x9c 0x00 0x20
 
-# CHECK: bclr 12, 29, 0
+# CHECK: bclr 12, 29
 0x4d 0x9d 0x00 0x20
 
-# CHECK: bclr 12, 30, 0
+# CHECK: bclr 12, 30
 0x4d 0x9e 0x00 0x20
 
-# CHECK: bclr 12, 31, 0
+# CHECK: bclr 12, 31
 0x4d 0x9f 0x00 0x20
 
-# CHECK: bclr 12, 31, 0
+# CHECK: bclr 12, 31
 0x4d 0x9f 0x00 0x20
 
 # CHECK: blr
@@ -164,76 +164,76 @@
 # CHECK: bctrl
 0x4e 0x80 0x04 0x21
 
-# CHECK: bclr 12, 2, 0
+# CHECK: bclr 12, 2
 0x4d 0x82 0x00 0x20
 
-# CHECK: bcctr 12, 2, 0
+# CHECK: bcctr 12, 2
 0x4d 0x82 0x04 0x20
 
-# CHECK: bclrl 12, 2, 0
+# CHECK: bclrl 12, 2
 0x4d 0x82 0x00 0x21
 
-# CHECK: bcctrl 12, 2, 0
+# CHECK: bcctrl 12, 2
 0x4d 0x82 0x04 0x21
 
-# CHECK: bclr 15, 2, 0
+# CHECK: bclr 15, 2
 0x4d 0xe2 0x00 0x20
 
-# CHECK: bcctr 15, 2, 0
+# CHECK: bcctr 15, 2
 0x4d 0xe2 0x04 0x20
 
-# CHECK: bclrl 15, 2, 0
+# CHECK: bclrl 15, 2
 0x4d 0xe2 0x00 0x21
 
-# CHECK: bcctrl 15, 2, 0
+# CHECK: bcctrl 15, 2
 0x4d 0xe2 0x04 0x21
 
-# CHECK: bclr 14, 2, 0
+# CHECK: bclr 14, 2
 0x4d 0xc2 0x00 0x20
 
-# CHECK: bcctr 14, 2, 0
+# CHECK: bcctr 14, 2
 0x4d 0xc2 0x04 0x20
 
-# CHECK: bclrl 14, 2, 0
+# CHECK: bclrl 14, 2
 0x4d 0xc2 0x00 0x21
 
-# CHECK: bcctrl 14, 2, 0
+# CHECK: bcctrl 14, 2
 0x4d 0xc2 0x04 0x21
 
-# CHECK: bclr 4, 2, 0
+# CHECK: bclr 4, 2
 0x4c 0x82 0x00 0x20
 
-# CHECK: bcctr 4, 2, 0
+# CHECK: bcctr 4, 2
 0x4c 0x82 0x04 0x20
 
-# CHECK: bclrl 4, 2, 0
+# CHECK: bclrl 4, 2
 0x4c 0x82 0x00 0x21
 
-# CHECK: bcctrl 4, 2, 0
+# CHECK: bcctrl 4, 2
 0x4c 0x82 0x04 0x21
 
-# CHECK: bclr 7, 2, 0
+# CHECK: bclr 7, 2
 0x4c 0xe2 0x00 0x20
 
-# CHECK: bcctr 7, 2, 0
+# CHECK: bcctr 7, 2
 0x4c 0xe2 0x04 0x20
 
-# CHECK: bclrl 7, 2, 0
+# CHECK: bclrl 7, 2
 0x4c 0xe2 0x00 0x21
 
-# CHECK: bcctrl 7, 2, 0
+# CHECK: bcctrl 7, 2
 0x4c 0xe2 0x04 0x21
 
-# CHECK: bclr 6, 2, 0
+# CHECK: bclr 6, 2
 0x4c 0xc2 0x00 0x20
 
-# CHECK: bcctr 6, 2, 0
+# CHECK: bcctr 6, 2
 0x4c 0xc2 0x04 0x20
 
-# CHECK: bclrl 6, 2, 0
+# CHECK: bclrl 6, 2
 0x4c 0xc2 0x00 0x21
 
-# CHECK: bcctrl 6, 2, 0
+# CHECK: bcctrl 6, 2
 0x4c 0xc2 0x04 0x21
 
 # CHECK: bdnzlr
@@ -254,16 +254,16 @@
 # CHECK: bdnzlrl-
 0x4f 0x00 0x00 0x21
 
-# CHECK: bclr 8, 2, 0
+# CHECK: bclr 8, 2
 0x4d 0x02 0x00 0x20
 
-# CHECK: bclrl 8, 2, 0
+# CHECK: bclrl 8, 2
 0x4d 0x02 0x00 0x21
 
-# CHECK: bclr 0, 2, 0
+# CHECK: bclr 0, 2
 0x4c 0x02 0x00 0x20
 
-# CHECK: bclrl 0, 2, 0
+# CHECK: bclrl 0, 2
 0x4c 0x02 0x00 0x21
 
 # CHECK: bdzlr
@@ -284,1168 +284,1168 @@
 # CHECK: bdzlrl-
 0x4f 0x40 0x00 0x21
 
-# CHECK: bclr 10, 2, 0
+# CHECK: bclr 10, 2
 0x4d 0x42 0x00 0x20
 
-# CHECK: bclrl 10, 2, 0
+# CHECK: bclrl 10, 2
 0x4d 0x42 0x00 0x21
 
-# CHECK: bclr 2, 2, 0
+# CHECK: bclr 2, 2
 0x4c 0x42 0x00 0x20
 
-# CHECK: bclrl 2, 2, 0
+# CHECK: bclrl 2, 2
 0x4c 0x42 0x00 0x21
 
 # FIXME: decode as bltlr 2
-# CHECK: bclr 12, 8, 0
+# CHECK: bclr 12, 8
 0x4d 0x88 0x00 0x20
 
 # FIXME: decode as bltlr 0
-# CHECK: bclr 12, 0, 0
+# CHECK: bclr 12, 0
 0x4d 0x80 0x00 0x20
 
 # FIXME: decode as bltctr 2
-# CHECK: bcctr 12, 8, 0
+# CHECK: bcctr 12, 8
 0x4d 0x88 0x04 0x20
 
 # FIXME: decode as bltctr 0
-# CHECK: bcctr 12, 0, 0
+# CHECK: bcctr 12, 0
 0x4d 0x80 0x04 0x20
 
 # FIXME: decode as bltlrl 2
-# CHECK: bclrl 12, 8, 0
+# CHECK: bclrl 12, 8
 0x4d 0x88 0x00 0x21
 
 # FIXME: decode as bltlrl 0
-# CHECK: bclrl 12, 0, 0
+# CHECK: bclrl 12, 0
 0x4d 0x80 0x00 0x21
 
 # FIXME: decode as bltctrl 2
-# CHECK: bcctrl 12, 8, 0
+# CHECK: bcctrl 12, 8
 0x4d 0x88 0x04 0x21
 
 # FIXME: decode as bltctrl 0
-# CHECK: bcctrl 12, 0, 0
+# CHECK: bcctrl 12, 0
 0x4d 0x80 0x04 0x21
 
 # FIXME: decode as bltlr+ 2
-# CHECK: bclr 15, 8, 0
+# CHECK: bclr 15, 8
 0x4d 0xe8 0x00 0x20
 
 # FIXME: decode as bltlr+ 0
-# CHECK: bclr 15, 0, 0
+# CHECK: bclr 15, 0
 0x4d 0xe0 0x00 0x20
 
 # FIXME: decode as bltctr+ 2
-# CHECK: bcctr 15, 8, 0
+# CHECK: bcctr 15, 8
 0x4d 0xe8 0x04 0x20
 
 # FIXME: decode as bltctr+ 0
-# CHECK: bcctr 15, 0, 0
+# CHECK: bcctr 15, 0
 0x4d 0xe0 0x04 0x20
 
 # FIXME: decode as bltlrl+ 2
-# CHECK: bclrl 15, 8, 0
+# CHECK: bclrl 15, 8
 0x4d 0xe8 0x00 0x21
 
 # FIXME: decode as bltlrl+ 0
-# CHECK: bclrl 15, 0, 0
+# CHECK: bclrl 15, 0
 0x4d 0xe0 0x00 0x21
 
 # FIXME: decode as bltctrl+ 2
-# CHECK: bcctrl 15, 8, 0
+# CHECK: bcctrl 15, 8
 0x4d 0xe8 0x04 0x21
 
 # FIXME: decode as bltctrl+ 0
-# CHECK: bcctrl 15, 0, 0
+# CHECK: bcctrl 15, 0
 0x4d 0xe0 0x04 0x21
 
 # FIXME: decode as bltlr- 2
-# CHECK: bclr 14, 8, 0
+# CHECK: bclr 14, 8
 0x4d 0xc8 0x00 0x20
 
 # FIXME: decode as bltlr- 0
-# CHECK: bclr 14, 0, 0
+# CHECK: bclr 14, 0
 0x4d 0xc0 0x00 0x20
 
 # FIXME: decode as bltctr- 2
-# CHECK: bcctr 14, 8, 0
+# CHECK: bcctr 14, 8
 0x4d 0xc8 0x04 0x20
 
 # FIXME: decode as bltctr- 0
-# CHECK: bcctr 14, 0, 0
+# CHECK: bcctr 14, 0
 0x4d 0xc0 0x04 0x20
 
 # FIXME: decode as bltlrl- 2
-# CHECK: bclrl 14, 8, 0
+# CHECK: bclrl 14, 8
 0x4d 0xc8 0x00 0x21
 
 # FIXME: decode as bltlrl- 0
-# CHECK: bclrl 14, 0, 0
+# CHECK: bclrl 14, 0
 0x4d 0xc0 0x00 0x21
 
 # FIXME: decode as bltctrl- 2
-# CHECK: bcctrl 14, 8, 0
+# CHECK: bcctrl 14, 8
 0x4d 0xc8 0x04 0x21
 
 # FIXME: decode as bltctrl- 0
-# CHECK: bcctrl 14, 0, 0
+# CHECK: bcctrl 14, 0
 0x4d 0xc0 0x04 0x21
 
 # FIXME: decode as blelr 2
-# CHECK: bclr 4, 9, 0
+# CHECK: bclr 4, 9
 0x4c 0x89 0x00 0x20
 
 # FIXME: decode as blelr 0
-# CHECK: bclr 4, 1, 0
+# CHECK: bclr 4, 1
 0x4c 0x81 0x00 0x20
 
 # FIXME: decode as blectr 2
-# CHECK: bcctr 4, 9, 0
+# CHECK: bcctr 4, 9
 0x4c 0x89 0x04 0x20
 
 # FIXME: decode as blectr 0
-# CHECK: bcctr 4, 1, 0
+# CHECK: bcctr 4, 1
 0x4c 0x81 0x04 0x20
 
 # FIXME: decode as blelrl 2
-# CHECK: bclrl 4, 9, 0
+# CHECK: bclrl 4, 9
 0x4c 0x89 0x00 0x21
 
 # FIXME: decode as blelrl 0
-# CHECK: bclrl 4, 1, 0
+# CHECK: bclrl 4, 1
 0x4c 0x81 0x00 0x21
 
 # FIXME: decode as blectrl 2
-# CHECK: bcctrl 4, 9, 0
+# CHECK: bcctrl 4, 9
 0x4c 0x89 0x04 0x21
 
 # FIXME: decode as blectrl 0
-# CHECK: bcctrl 4, 1, 0
+# CHECK: bcctrl 4, 1
 0x4c 0x81 0x04 0x21
 
 # FIXME: decode as blelr+ 2
-# CHECK: bclr 7, 9, 0
+# CHECK: bclr 7, 9
 0x4c 0xe9 0x00 0x20
 
 # FIXME: decode as blelr+ 0
-# CHECK: bclr 7, 1, 0
+# CHECK: bclr 7, 1
 0x4c 0xe1 0x00 0x20
 
 # FIXME: decode as blectr+ 2
-# CHECK: bcctr 7, 9, 0
+# CHECK: bcctr 7, 9
 0x4c 0xe9 0x04 0x20
 
 # FIXME: decode as blectr+ 0
-# CHECK: bcctr 7, 1, 0
+# CHECK: bcctr 7, 1
 0x4c 0xe1 0x04 0x20
 
 # FIXME: decode as blelrl+ 2
-# CHECK: bclrl 7, 9, 0
+# CHECK: bclrl 7, 9
 0x4c 0xe9 0x00 0x21
 
 # FIXME: decode as blelrl+ 0
-# CHECK: bclrl 7, 1, 0
+# CHECK: bclrl 7, 1
 0x4c 0xe1 0x00 0x21
 
 # FIXME: decode as blectrl+ 2
-# CHECK: bcctrl 7, 9, 0
+# CHECK: bcctrl 7, 9
 0x4c 0xe9 0x04 0x21
 
 # FIXME: decode as blectrl+ 0
-# CHECK: bcctrl 7, 1, 0
+# CHECK: bcctrl 7, 1
 0x4c 0xe1 0x04 0x21
 
 # FIXME: decode as blelr- 2
-# CHECK: bclr 6, 9, 0
+# CHECK: bclr 6, 9
 0x4c 0xc9 0x00 0x20
 
 # FIXME: decode as blelr- 0
-# CHECK: bclr 6, 1, 0
+# CHECK: bclr 6, 1
 0x4c 0xc1 0x00 0x20
 
 # FIXME: decode as blectr- 2
-# CHECK: bcctr 6, 9, 0
+# CHECK: bcctr 6, 9
 0x4c 0xc9 0x04 0x20
 
 # FIXME: decode as blectr- 0
-# CHECK: bcctr 6, 1, 0
+# CHECK: bcctr 6, 1
 0x4c 0xc1 0x04 0x20
 
 # FIXME: decode as blelrl- 2
-# CHECK: bclrl 6, 9, 0
+# CHECK: bclrl 6, 9
 0x4c 0xc9 0x00 0x21
 
 # FIXME: decode as blelrl- 0
-# CHECK: bclrl 6, 1, 0
+# CHECK: bclrl 6, 1
 0x4c 0xc1 0x00 0x21
 
 # FIXME: decode as blectrl- 2
-# CHECK: bcctrl 6, 9, 0
+# CHECK: bcctrl 6, 9
 0x4c 0xc9 0x04 0x21
 
 # FIXME: decode as blectrl- 0
-# CHECK: bcctrl 6, 1, 0
+# CHECK: bcctrl 6, 1
 0x4c 0xc1 0x04 0x21
 
 # FIXME: decode as beqlr 2
-# CHECK: bclr 12, 10, 0
+# CHECK: bclr 12, 10
 0x4d 0x8a 0x00 0x20
 
 # FIXME: decode as beqlr 0
-# CHECK: bclr 12, 2, 0
+# CHECK: bclr 12, 2
 0x4d 0x82 0x00 0x20
 
 # FIXME: decode as beqctr 2
-# CHECK: bcctr 12, 10, 0
+# CHECK: bcctr 12, 10
 0x4d 0x8a 0x04 0x20
 
 # FIXME: decode as beqctr 0
-# CHECK: bcctr 12, 2, 0
+# CHECK: bcctr 12, 2
 0x4d 0x82 0x04 0x20
 
 # FIXME: decode as beqlrl 2
-# CHECK: bclrl 12, 10, 0
+# CHECK: bclrl 12, 10
 0x4d 0x8a 0x00 0x21
 
 # FIXME: decode as beqlrl 0
-# CHECK: bclrl 12, 2, 0
+# CHECK: bclrl 12, 2
 0x4d 0x82 0x00 0x21
 
 # FIXME: decode as beqctrl 2
-# CHECK: bcctrl 12, 10, 0
+# CHECK: bcctrl 12, 10
 0x4d 0x8a 0x04 0x21
 
 # FIXME: decode as beqctrl 0
-# CHECK: bcctrl 12, 2, 0
+# CHECK: bcctrl 12, 2
 0x4d 0x82 0x04 0x21
 
 # FIXME: decode as beqlr+ 2
-# CHECK: bclr 15, 10, 0
+# CHECK: bclr 15, 10
 0x4d 0xea 0x00 0x20
 
 # FIXME: decode as beqlr+ 0
-# CHECK: bclr 15, 2, 0
+# CHECK: bclr 15, 2
 0x4d 0xe2 0x00 0x20
 
 # FIXME: decode as beqctr+ 2
-# CHECK: bcctr 15, 10, 0
+# CHECK: bcctr 15, 10
 0x4d 0xea 0x04 0x20
 
 # FIXME: decode as beqctr+ 0
-# CHECK: bcctr 15, 2, 0
+# CHECK: bcctr 15, 2
 0x4d 0xe2 0x04 0x20
 
 # FIXME: decode as beqlrl+ 2
-# CHECK: bclrl 15, 10, 0
+# CHECK: bclrl 15, 10
 0x4d 0xea 0x00 0x21
 
 # FIXME: decode as beqlrl+ 0
-# CHECK: bclrl 15, 2, 0
+# CHECK: bclrl 15, 2
 0x4d 0xe2 0x00 0x21
 
 # FIXME: decode as beqctrl+ 2
-# CHECK: bcctrl 15, 10, 0
+# CHECK: bcctrl 15, 10
 0x4d 0xea 0x04 0x21
 
 # FIXME: decode as beqctrl+ 0
-# CHECK: bcctrl 15, 2, 0
+# CHECK: bcctrl 15, 2
 0x4d 0xe2 0x04 0x21
 
 # FIXME: decode as beqlr- 2
-# CHECK: bclr 14, 10, 0
+# CHECK: bclr 14, 10
 0x4d 0xca 0x00 0x20
 
 # FIXME: decode as beqlr- 0
-# CHECK: bclr 14, 2, 0
+# CHECK: bclr 14, 2
 0x4d 0xc2 0x00 0x20
 
 # FIXME: decode as beqctr- 2
-# CHECK: bcctr 14, 10, 0
+# CHECK: bcctr 14, 10
 0x4d 0xca 0x04 0x20
 
 # FIXME: decode as beqctr- 0
-# CHECK: bcctr 14, 2, 0
+# CHECK: bcctr 14, 2
 0x4d 0xc2 0x04 0x20
 
 # FIXME: decode as beqlrl- 2
-# CHECK: bclrl 14, 10, 0
+# CHECK: bclrl 14, 10
 0x4d 0xca 0x00 0x21
 
 # FIXME: decode as beqlrl- 0
-# CHECK: bclrl 14, 2, 0
+# CHECK: bclrl 14, 2
 0x4d 0xc2 0x00 0x21
 
 # FIXME: decode as beqctrl- 2
-# CHECK: bcctrl 14, 10, 0
+# CHECK: bcctrl 14, 10
 0x4d 0xca 0x04 0x21
 
 # FIXME: decode as beqctrl- 0
-# CHECK: bcctrl 14, 2, 0
+# CHECK: bcctrl 14, 2
 0x4d 0xc2 0x04 0x21
 
 # FIXME: decode as bgelr 2
-# CHECK: bclr 4, 8, 0
+# CHECK: bclr 4, 8
 0x4c 0x88 0x00 0x20
 
 # FIXME: decode as bgelr 0
-# CHECK: bclr 4, 0, 0
+# CHECK: bclr 4, 0
 0x4c 0x80 0x00 0x20
 
 # FIXME: decode as bgectr 2
-# CHECK: bcctr 4, 8, 0
+# CHECK: bcctr 4, 8
 0x4c 0x88 0x04 0x20
 
 # FIXME: decode as bgectr 0
-# CHECK: bcctr 4, 0, 0
+# CHECK: bcctr 4, 0
 0x4c 0x80 0x04 0x20
 
 # FIXME: decode as bgelrl 2
-# CHECK: bclrl 4, 8, 0
+# CHECK: bclrl 4, 8
 0x4c 0x88 0x00 0x21
 
 # FIXME: decode as bgelrl 0
-# CHECK: bclrl 4, 0, 0
+# CHECK: bclrl 4, 0
 0x4c 0x80 0x00 0x21
 
 # FIXME: decode as bgectrl 2
-# CHECK: bcctrl 4, 8, 0
+# CHECK: bcctrl 4, 8
 0x4c 0x88 0x04 0x21
 
 # FIXME: decode as bgectrl 0
-# CHECK: bcctrl 4, 0, 0
+# CHECK: bcctrl 4, 0
 0x4c 0x80 0x04 0x21
 
 # FIXME: decode as bgelr+ 2
-# CHECK: bclr 7, 8, 0
+# CHECK: bclr 7, 8
 0x4c 0xe8 0x00 0x20
 
 # FIXME: decode as bgelr+ 0
-# CHECK: bclr 7, 0, 0
+# CHECK: bclr 7, 0
 0x4c 0xe0 0x00 0x20
 
 # FIXME: decode as bgectr+ 2
-# CHECK: bcctr 7, 8, 0
+# CHECK: bcctr 7, 8
 0x4c 0xe8 0x04 0x20
 
 # FIXME: decode as bgectr+ 0
-# CHECK: bcctr 7, 0, 0
+# CHECK: bcctr 7, 0
 0x4c 0xe0 0x04 0x20
 
 # FIXME: decode as bgelrl+ 2
-# CHECK: bclrl 7, 8, 0
+# CHECK: bclrl 7, 8
 0x4c 0xe8 0x00 0x21
 
 # FIXME: decode as bgelrl+ 0
-# CHECK: bclrl 7, 0, 0
+# CHECK: bclrl 7, 0
 0x4c 0xe0 0x00 0x21
 
 # FIXME: decode as bgectrl+ 2
-# CHECK: bcctrl 7, 8, 0
+# CHECK: bcctrl 7, 8
 0x4c 0xe8 0x04 0x21
 
 # FIXME: decode as bgectrl+ 0
-# CHECK: bcctrl 7, 0, 0
+# CHECK: bcctrl 7, 0
 0x4c 0xe0 0x04 0x21
 
 # FIXME: decode as bgelr- 2
-# CHECK: bclr 6, 8, 0
+# CHECK: bclr 6, 8
 0x4c 0xc8 0x00 0x20
 
 # FIXME: decode as bgelr- 0
-# CHECK: bclr 6, 0, 0
+# CHECK: bclr 6, 0
 0x4c 0xc0 0x00 0x20
 
 # FIXME: decode as bgectr- 2
-# CHECK: bcctr 6, 8, 0
+# CHECK: bcctr 6, 8
 0x4c 0xc8 0x04 0x20
 
 # FIXME: decode as bgectr- 0
-# CHECK: bcctr 6, 0, 0
+# CHECK: bcctr 6, 0
 0x4c 0xc0 0x04 0x20
 
 # FIXME: decode as bgelrl- 2
-# CHECK: bclrl 6, 8, 0
+# CHECK: bclrl 6, 8
 0x4c 0xc8 0x00 0x21
 
 # FIXME: decode as bgelrl- 0
-# CHECK: bclrl 6, 0, 0
+# CHECK: bclrl 6, 0
 0x4c 0xc0 0x00 0x21
 
 # FIXME: decode as bgectrl- 2
-# CHECK: bcctrl 6, 8, 0
+# CHECK: bcctrl 6, 8
 0x4c 0xc8 0x04 0x21
 
 # FIXME: decode as bgectrl- 0
-# CHECK: bcctrl 6, 0, 0
+# CHECK: bcctrl 6, 0
 0x4c 0xc0 0x04 0x21
 
 # FIXME: decode as bgtlr 2
-# CHECK: bclr 12, 9, 0
+# CHECK: bclr 12, 9
 0x4d 0x89 0x00 0x20
 
 # FIXME: decode as bgtlr 0
-# CHECK: bclr 12, 1, 0
+# CHECK: bclr 12, 1
 0x4d 0x81 0x00 0x20
 
 # FIXME: decode as bgtctr 2
-# CHECK: bcctr 12, 9, 0
+# CHECK: bcctr 12, 9
 0x4d 0x89 0x04 0x20
 
 # FIXME: decode as bgtctr 0
-# CHECK: bcctr 12, 1, 0
+# CHECK: bcctr 12, 1
 0x4d 0x81 0x04 0x20
 
 # FIXME: decode as bgtlrl 2
-# CHECK: bclrl 12, 9, 0
+# CHECK: bclrl 12, 9
 0x4d 0x89 0x00 0x21
 
 # FIXME: decode as bgtlrl 0
-# CHECK: bclrl 12, 1, 0
+# CHECK: bclrl 12, 1
 0x4d 0x81 0x00 0x21
 
 # FIXME: decode as bgtctrl 2
-# CHECK: bcctrl 12, 9, 0
+# CHECK: bcctrl 12, 9
 0x4d 0x89 0x04 0x21
 
 # FIXME: decode as bgtctrl 0
-# CHECK: bcctrl 12, 1, 0
+# CHECK: bcctrl 12, 1
 0x4d 0x81 0x04 0x21
 
 # FIXME: decode as bgtlr+ 2
-# CHECK: bclr 15, 9, 0
+# CHECK: bclr 15, 9
 0x4d 0xe9 0x00 0x20
 
 # FIXME: decode as bgtlr+ 0
-# CHECK: bclr 15, 1, 0
+# CHECK: bclr 15, 1
 0x4d 0xe1 0x00 0x20
 
 # FIXME: decode as bgtctr+ 2
-# CHECK: bcctr 15, 9, 0
+# CHECK: bcctr 15, 9
 0x4d 0xe9 0x04 0x20
 
 # FIXME: decode as bgtctr+ 0
-# CHECK: bcctr 15, 1, 0
+# CHECK: bcctr 15, 1
 0x4d 0xe1 0x04 0x20
 
 # FIXME: decode as bgtlrl+ 2
-# CHECK: bclrl 15, 9, 0
+# CHECK: bclrl 15, 9
 0x4d 0xe9 0x00 0x21
 
 # FIXME: decode as bgtlrl+ 0
-# CHECK: bclrl 15, 1, 0
+# CHECK: bclrl 15, 1
 0x4d 0xe1 0x00 0x21
 
 # FIXME: decode as bgtctrl+ 2
-# CHECK: bcctrl 15, 9, 0
+# CHECK: bcctrl 15, 9
 0x4d 0xe9 0x04 0x21
 
 # FIXME: decode as bgtctrl+ 0
-# CHECK: bcctrl 15, 1, 0
+# CHECK: bcctrl 15, 1
 0x4d 0xe1 0x04 0x21
 
 # FIXME: decode as bgtlr- 2
-# CHECK: bclr 14, 9, 0
+# CHECK: bclr 14, 9
 0x4d 0xc9 0x00 0x20
 
 # FIXME: decode as bgtlr- 0
-# CHECK: bclr 14, 1, 0
+# CHECK: bclr 14, 1
 0x4d 0xc1 0x00 0x20
 
 # FIXME: decode as bgtctr- 2
-# CHECK: bcctr 14, 9, 0
+# CHECK: bcctr 14, 9
 0x4d 0xc9 0x04 0x20
 
 # FIXME: decode as bgtctr- 0
-# CHECK: bcctr 14, 1, 0
+# CHECK: bcctr 14, 1
 0x4d 0xc1 0x04 0x20
 
 # FIXME: decode as bgtlrl- 2
-# CHECK: bclrl 14, 9, 0
+# CHECK: bclrl 14, 9
 0x4d 0xc9 0x00 0x21
 
 # FIXME: decode as bgtlrl- 0
-# CHECK: bclrl 14, 1, 0
+# CHECK: bclrl 14, 1
 0x4d 0xc1 0x00 0x21
 
 # FIXME: decode as bgtctrl- 2
-# CHECK: bcctrl 14, 9, 0
+# CHECK: bcctrl 14, 9
 0x4d 0xc9 0x04 0x21
 
 # FIXME: decode as bgtctrl- 0
-# CHECK: bcctrl 14, 1, 0
+# CHECK: bcctrl 14, 1
 0x4d 0xc1 0x04 0x21
 
 # FIXME: decode as bgelr 2
-# CHECK: bclr 4, 8, 0
+# CHECK: bclr 4, 8
 0x4c 0x88 0x00 0x20
 
 # FIXME: decode as bgelr 0
-# CHECK: bclr 4, 0, 0
+# CHECK: bclr 4, 0
 0x4c 0x80 0x00 0x20
 
 # FIXME: decode as bgectr 2
-# CHECK: bcctr 4, 8, 0
+# CHECK: bcctr 4, 8
 0x4c 0x88 0x04 0x20
 
 # FIXME: decode as bgectr 0
-# CHECK: bcctr 4, 0, 0
+# CHECK: bcctr 4, 0
 0x4c 0x80 0x04 0x20
 
 # FIXME: decode as bgelrl 2
-# CHECK: bclrl 4, 8, 0
+# CHECK: bclrl 4, 8
 0x4c 0x88 0x00 0x21
 
 # FIXME: decode as bgelrl 0
-# CHECK: bclrl 4, 0, 0
+# CHECK: bclrl 4, 0
 0x4c 0x80 0x00 0x21
 
 # FIXME: decode as bgectrl 2
-# CHECK: bcctrl 4, 8, 0
+# CHECK: bcctrl 4, 8
 0x4c 0x88 0x04 0x21
 
 # FIXME: decode as bgectrl 0
-# CHECK: bcctrl 4, 0, 0
+# CHECK: bcctrl 4, 0
 0x4c 0x80 0x04 0x21
 
 # FIXME: decode as bgelr+ 2
-# CHECK: bclr 7, 8, 0
+# CHECK: bclr 7, 8
 0x4c 0xe8 0x00 0x20
 
 # FIXME: decode as bgelr+ 0
-# CHECK: bclr 7, 0, 0
+# CHECK: bclr 7, 0
 0x4c 0xe0 0x00 0x20
 
 # FIXME: decode as bgectr+ 2
-# CHECK: bcctr 7, 8, 0
+# CHECK: bcctr 7, 8
 0x4c 0xe8 0x04 0x20
 
 # FIXME: decode as bgectr+ 0
-# CHECK: bcctr 7, 0, 0
+# CHECK: bcctr 7, 0
 0x4c 0xe0 0x04 0x20
 
 # FIXME: decode as bgelrl+ 2
-# CHECK: bclrl 7, 8, 0
+# CHECK: bclrl 7, 8
 0x4c 0xe8 0x00 0x21
 
 # FIXME: decode as bgelrl+ 0
-# CHECK: bclrl 7, 0, 0
+# CHECK: bclrl 7, 0
 0x4c 0xe0 0x00 0x21
 
 # FIXME: decode as bgectrl+ 2
-# CHECK: bcctrl 7, 8, 0
+# CHECK: bcctrl 7, 8
 0x4c 0xe8 0x04 0x21
 
 # FIXME: decode as bgectrl+ 0
-# CHECK: bcctrl 7, 0, 0
+# CHECK: bcctrl 7, 0
 0x4c 0xe0 0x04 0x21
 
 # FIXME: decode as bgelr- 2
-# CHECK: bclr 6, 8, 0
+# CHECK: bclr 6, 8
 0x4c 0xc8 0x00 0x20
 
 # FIXME: decode as bgelr- 0
-# CHECK: bclr 6, 0, 0
+# CHECK: bclr 6, 0
 0x4c 0xc0 0x00 0x20
 
 # FIXME: decode as bgectr- 2
-# CHECK: bcctr 6, 8, 0
+# CHECK: bcctr 6, 8
 0x4c 0xc8 0x04 0x20
 
 # FIXME: decode as bgectr- 0
-# CHECK: bcctr 6, 0, 0
+# CHECK: bcctr 6, 0
 0x4c 0xc0 0x04 0x20
 
 # FIXME: decode as bgelrl- 2
-# CHECK: bclrl 6, 8, 0
+# CHECK: bclrl 6, 8
 0x4c 0xc8 0x00 0x21
 
 # FIXME: decode as bgelrl- 0
-# CHECK: bclrl 6, 0, 0
+# CHECK: bclrl 6, 0
 0x4c 0xc0 0x00 0x21
 
 # FIXME: decode as bgectrl- 2
-# CHECK: bcctrl 6, 8, 0
+# CHECK: bcctrl 6, 8
 0x4c 0xc8 0x04 0x21
 
 # FIXME: decode as bgectrl- 0
-# CHECK: bcctrl 6, 0, 0
+# CHECK: bcctrl 6, 0
 0x4c 0xc0 0x04 0x21
 
 # FIXME: decode as bnelr 2
-# CHECK: bclr 4, 10, 0
+# CHECK: bclr 4, 10
 0x4c 0x8a 0x00 0x20
 
 # FIXME: decode as bnelr 0
-# CHECK: bclr 4, 2, 0
+# CHECK: bclr 4, 2
 0x4c 0x82 0x00 0x20
 
 # FIXME: decode as bnectr 2
-# CHECK: bcctr 4, 10, 0
+# CHECK: bcctr 4, 10
 0x4c 0x8a 0x04 0x20
 
 # FIXME: decode as bnectr 0
-# CHECK: bcctr 4, 2, 0
+# CHECK: bcctr 4, 2
 0x4c 0x82 0x04 0x20
 
 # FIXME: decode as bnelrl 2
-# CHECK: bclrl 4, 10, 0
+# CHECK: bclrl 4, 10
 0x4c 0x8a 0x00 0x21
 
 # FIXME: decode as bnelrl 0
-# CHECK: bclrl 4, 2, 0
+# CHECK: bclrl 4, 2
 0x4c 0x82 0x00 0x21
 
 # FIXME: decode as bnectrl 2
-# CHECK: bcctrl 4, 10, 0
+# CHECK: bcctrl 4, 10
 0x4c 0x8a 0x04 0x21
 
 # FIXME: decode as bnectrl 0
-# CHECK: bcctrl 4, 2, 0
+# CHECK: bcctrl 4, 2
 0x4c 0x82 0x04 0x21
 
 # FIXME: decode as bnelr+ 2
-# CHECK: bclr 7, 10, 0
+# CHECK: bclr 7, 10
 0x4c 0xea 0x00 0x20
 
 # FIXME: decode as bnelr+ 0
-# CHECK: bclr 7, 2, 0
+# CHECK: bclr 7, 2
 0x4c 0xe2 0x00 0x20
 
 # FIXME: decode as bnectr+ 2
-# CHECK: bcctr 7, 10, 0
+# CHECK: bcctr 7, 10
 0x4c 0xea 0x04 0x20
 
 # FIXME: decode as bnectr+ 0
-# CHECK: bcctr 7, 2, 0
+# CHECK: bcctr 7, 2
 0x4c 0xe2 0x04 0x20
 
 # FIXME: decode as bnelrl+ 2
-# CHECK: bclrl 7, 10, 0
+# CHECK: bclrl 7, 10
 0x4c 0xea 0x00 0x21
 
 # FIXME: decode as bnelrl+ 0
-# CHECK: bclrl 7, 2, 0
+# CHECK: bclrl 7, 2
 0x4c 0xe2 0x00 0x21
 
 # FIXME: decode as bnectrl+ 2
-# CHECK: bcctrl 7, 10, 0
+# CHECK: bcctrl 7, 10
 0x4c 0xea 0x04 0x21
 
 # FIXME: decode as bnectrl+ 0
-# CHECK: bcctrl 7, 2, 0
+# CHECK: bcctrl 7, 2
 0x4c 0xe2 0x04 0x21
 
 # FIXME: decode as bnelr- 2
-# CHECK: bclr 6, 10, 0
+# CHECK: bclr 6, 10
 0x4c 0xca 0x00 0x20
 
 # FIXME: decode as bnelr- 0
-# CHECK: bclr 6, 2, 0
+# CHECK: bclr 6, 2
 0x4c 0xc2 0x00 0x20
 
 # FIXME: decode as bnectr- 2
-# CHECK: bcctr 6, 10, 0
+# CHECK: bcctr 6, 10
 0x4c 0xca 0x04 0x20
 
 # FIXME: decode as bnectr- 0
-# CHECK: bcctr 6, 2, 0
+# CHECK: bcctr 6, 2
 0x4c 0xc2 0x04 0x20
 
 # FIXME: decode as bnelrl- 2
-# CHECK: bclrl 6, 10, 0
+# CHECK: bclrl 6, 10
 0x4c 0xca 0x00 0x21
 
 # FIXME: decode as bnelrl- 0
-# CHECK: bclrl 6, 2, 0
+# CHECK: bclrl 6, 2
 0x4c 0xc2 0x00 0x21
 
 # FIXME: decode as bnectrl- 2
-# CHECK: bcctrl 6, 10, 0
+# CHECK: bcctrl 6, 10
 0x4c 0xca 0x04 0x21
 
 # FIXME: decode as bnectrl- 0
-# CHECK: bcctrl 6, 2, 0
+# CHECK: bcctrl 6, 2
 0x4c 0xc2 0x04 0x21
 
 # FIXME: decode as blelr 2
-# CHECK: bclr 4, 9, 0
+# CHECK: bclr 4, 9
 0x4c 0x89 0x00 0x20
 
 # FIXME: decode as blelr 0
-# CHECK: bclr 4, 1, 0
+# CHECK: bclr 4, 1
 0x4c 0x81 0x00 0x20
 
 # FIXME: decode as blectr 2
-# CHECK: bcctr 4, 9, 0
+# CHECK: bcctr 4, 9
 0x4c 0x89 0x04 0x20
 
 # FIXME: decode as blectr 0
-# CHECK: bcctr 4, 1, 0
+# CHECK: bcctr 4, 1
 0x4c 0x81 0x04 0x20
 
 # FIXME: decode as blelrl 2
-# CHECK: bclrl 4, 9, 0
+# CHECK: bclrl 4, 9
 0x4c 0x89 0x00 0x21
 
 # FIXME: decode as blelrl 0
-# CHECK: bclrl 4, 1, 0
+# CHECK: bclrl 4, 1
 0x4c 0x81 0x00 0x21
 
 # FIXME: decode as blectrl 2
-# CHECK: bcctrl 4, 9, 0
+# CHECK: bcctrl 4, 9
 0x4c 0x89 0x04 0x21
 
 # FIXME: decode as blectrl 0
-# CHECK: bcctrl 4, 1, 0
+# CHECK: bcctrl 4, 1
 0x4c 0x81 0x04 0x21
 
 # FIXME: decode as blelr+ 2
-# CHECK: bclr 7, 9, 0
+# CHECK: bclr 7, 9
 0x4c 0xe9 0x00 0x20
 
 # FIXME: decode as blelr+ 0
-# CHECK: bclr 7, 1, 0
+# CHECK: bclr 7, 1
 0x4c 0xe1 0x00 0x20
 
 # FIXME: decode as blectr+ 2
-# CHECK: bcctr 7, 9, 0
+# CHECK: bcctr 7, 9
 0x4c 0xe9 0x04 0x20
 
 # FIXME: decode as blectr+ 0
-# CHECK: bcctr 7, 1, 0
+# CHECK: bcctr 7, 1
 0x4c 0xe1 0x04 0x20
 
 # FIXME: decode as blelrl+ 2
-# CHECK: bclrl 7, 9, 0
+# CHECK: bclrl 7, 9
 0x4c 0xe9 0x00 0x21
 
 # FIXME: decode as blelrl+ 0
-# CHECK: bclrl 7, 1, 0
+# CHECK: bclrl 7, 1
 0x4c 0xe1 0x00 0x21
 
 # FIXME: decode as blectrl+ 2
-# CHECK: bcctrl 7, 9, 0
+# CHECK: bcctrl 7, 9
 0x4c 0xe9 0x04 0x21
 
 # FIXME: decode as blectrl+ 0
-# CHECK: bcctrl 7, 1, 0
+# CHECK: bcctrl 7, 1
 0x4c 0xe1 0x04 0x21
 
 # FIXME: decode as blelr- 2
-# CHECK: bclr 6, 9, 0
+# CHECK: bclr 6, 9
 0x4c 0xc9 0x00 0x20
 
 # FIXME: decode as blelr- 0
-# CHECK: bclr 6, 1, 0
+# CHECK: bclr 6, 1
 0x4c 0xc1 0x00 0x20
 
 # FIXME: decode as blectr- 2
-# CHECK: bcctr 6, 9, 0
+# CHECK: bcctr 6, 9
 0x4c 0xc9 0x04 0x20
 
 # FIXME: decode as blectr- 0
-# CHECK: bcctr 6, 1, 0
+# CHECK: bcctr 6, 1
 0x4c 0xc1 0x04 0x20
 
 # FIXME: decode as blelrl- 2
-# CHECK: bclrl 6, 9, 0
+# CHECK: bclrl 6, 9
 0x4c 0xc9 0x00 0x21
 
 # FIXME: decode as blelrl- 0
-# CHECK: bclrl 6, 1, 0
+# CHECK: bclrl 6, 1
 0x4c 0xc1 0x00 0x21
 
 # FIXME: decode as blectrl- 2
-# CHECK: bcctrl 6, 9, 0
+# CHECK: bcctrl 6, 9
 0x4c 0xc9 0x04 0x21
 
 # FIXME: decode as blectrl- 0
-# CHECK: bcctrl 6, 1, 0
+# CHECK: bcctrl 6, 1
 0x4c 0xc1 0x04 0x21
 
 # FIXME: decode as bunlr 2
-# CHECK: bclr 12, 11, 0
+# CHECK: bclr 12, 11
 0x4d 0x8b 0x00 0x20
 
 # FIXME: decode as bunlr 0
-# CHECK: bclr 12, 3, 0
+# CHECK: bclr 12, 3
 0x4d 0x83 0x00 0x20
 
 # FIXME: decode as bunctr 2
-# CHECK: bcctr 12, 11, 0
+# CHECK: bcctr 12, 11
 0x4d 0x8b 0x04 0x20
 
 # FIXME: decode as bunctr 0
-# CHECK: bcctr 12, 3, 0
+# CHECK: bcctr 12, 3
 0x4d 0x83 0x04 0x20
 
 # FIXME: decode as bunlrl 2
-# CHECK: bclrl 12, 11, 0
+# CHECK: bclrl 12, 11
 0x4d 0x8b 0x00 0x21
 
 # FIXME: decode as bunlrl 0
-# CHECK: bclrl 12, 3, 0
+# CHECK: bclrl 12, 3
 0x4d 0x83 0x00 0x21
 
 # FIXME: decode as bunctrl 2
-# CHECK: bcctrl 12, 11, 0
+# CHECK: bcctrl 12, 11
 0x4d 0x8b 0x04 0x21
 
 # FIXME: decode as bunctrl 0
-# CHECK: bcctrl 12, 3, 0
+# CHECK: bcctrl 12, 3
 0x4d 0x83 0x04 0x21
 
 # FIXME: decode as bunlr+ 2
-# CHECK: bclr 15, 11, 0
+# CHECK: bclr 15, 11
 0x4d 0xeb 0x00 0x20
 
 # FIXME: decode as bunlr+ 0
-# CHECK: bclr 15, 3, 0
+# CHECK: bclr 15, 3
 0x4d 0xe3 0x00 0x20
 
 # FIXME: decode as bunctr+ 2
-# CHECK: bcctr 15, 11, 0
+# CHECK: bcctr 15, 11
 0x4d 0xeb 0x04 0x20
 
 # FIXME: decode as bunctr+ 0
-# CHECK: bcctr 15, 3, 0
+# CHECK: bcctr 15, 3
 0x4d 0xe3 0x04 0x20
 
 # FIXME: decode as bunlrl+ 2
-# CHECK: bclrl 15, 11, 0
+# CHECK: bclrl 15, 11
 0x4d 0xeb 0x00 0x21
 
 # FIXME: decode as bunlrl+ 0
-# CHECK: bclrl 15, 3, 0
+# CHECK: bclrl 15, 3
 0x4d 0xe3 0x00 0x21
 
 # FIXME: decode as bunctrl+ 2
-# CHECK: bcctrl 15, 11, 0
+# CHECK: bcctrl 15, 11
 0x4d 0xeb 0x04 0x21
 
 # FIXME: decode as bunctrl+ 0
-# CHECK: bcctrl 15, 3, 0
+# CHECK: bcctrl 15, 3
 0x4d 0xe3 0x04 0x21
 
 # FIXME: decode as bunlr- 2
-# CHECK: bclr 14, 11, 0
+# CHECK: bclr 14, 11
 0x4d 0xcb 0x00 0x20
 
 # FIXME: decode as bunlr- 0
-# CHECK: bclr 14, 3, 0
+# CHECK: bclr 14, 3
 0x4d 0xc3 0x00 0x20
 
 # FIXME: decode as bunctr- 2
-# CHECK: bcctr 14, 11, 0
+# CHECK: bcctr 14, 11
 0x4d 0xcb 0x04 0x20
 
 # FIXME: decode as bunctr- 0
-# CHECK: bcctr 14, 3, 0
+# CHECK: bcctr 14, 3
 0x4d 0xc3 0x04 0x20
 
 # FIXME: decode as bunlrl- 2
-# CHECK: bclrl 14, 11, 0
+# CHECK: bclrl 14, 11
 0x4d 0xcb 0x00 0x21
 
 # FIXME: decode as bunlrl- 0
-# CHECK: bclrl 14, 3, 0
+# CHECK: bclrl 14, 3
 0x4d 0xc3 0x00 0x21
 
 # FIXME: decode as bunctrl- 2
-# CHECK: bcctrl 14, 11, 0
+# CHECK: bcctrl 14, 11
 0x4d 0xcb 0x04 0x21
 
 # FIXME: decode as bunctrl- 0
-# CHECK: bcctrl 14, 3, 0
+# CHECK: bcctrl 14, 3
 0x4d 0xc3 0x04 0x21
 
 # FIXME: decode as bnulr 2
-# CHECK: bclr 4, 11, 0
+# CHECK: bclr 4, 11
 0x4c 0x8b 0x00 0x20
 
 # FIXME: decode as bnulr 0
-# CHECK: bclr 4, 3, 0
+# CHECK: bclr 4, 3
 0x4c 0x83 0x00 0x20
 
 # FIXME: decode as bnuctr 2
-# CHECK: bcctr 4, 11, 0
+# CHECK: bcctr 4, 11
 0x4c 0x8b 0x04 0x20
 
 # FIXME: decode as bnuctr 0
-# CHECK: bcctr 4, 3, 0
+# CHECK: bcctr 4, 3
 0x4c 0x83 0x04 0x20
 
 # FIXME: decode as bnulrl 2
-# CHECK: bclrl 4, 11, 0
+# CHECK: bclrl 4, 11
 0x4c 0x8b 0x00 0x21
 
 # FIXME: decode as bnulrl 0
-# CHECK: bclrl 4, 3, 0
+# CHECK: bclrl 4, 3
 0x4c 0x83 0x00 0x21
 
 # FIXME: decode as bnuctrl 2
-# CHECK: bcctrl 4, 11, 0
+# CHECK: bcctrl 4, 11
 0x4c 0x8b 0x04 0x21
 
 # FIXME: decode as bnuctrl 0
-# CHECK: bcctrl 4, 3, 0
+# CHECK: bcctrl 4, 3
 0x4c 0x83 0x04 0x21
 
 # FIXME: decode as bnulr+ 2
-# CHECK: bclr 7, 11, 0
+# CHECK: bclr 7, 11
 0x4c 0xeb 0x00 0x20
 
 # FIXME: decode as bnulr+ 0
-# CHECK: bclr 7, 3, 0
+# CHECK: bclr 7, 3
 0x4c 0xe3 0x00 0x20
 
 # FIXME: decode as bnuctr+ 2
-# CHECK: bcctr 7, 11, 0
+# CHECK: bcctr 7, 11
 0x4c 0xeb 0x04 0x20
 
 # FIXME: decode as bnuctr+ 0
-# CHECK: bcctr 7, 3, 0
+# CHECK: bcctr 7, 3
 0x4c 0xe3 0x04 0x20
 
 # FIXME: decode as bnulrl+ 2
-# CHECK: bclrl 7, 11, 0
+# CHECK: bclrl 7, 11
 0x4c 0xeb 0x00 0x21
 
 # FIXME: decode as bnulrl+ 0
-# CHECK: bclrl 7, 3, 0
+# CHECK: bclrl 7, 3
 0x4c 0xe3 0x00 0x21
 
 # FIXME: decode as bnuctrl+ 2
-# CHECK: bcctrl 7, 11, 0
+# CHECK: bcctrl 7, 11
 0x4c 0xeb 0x04 0x21
 
 # FIXME: decode as bnuctrl+ 0
-# CHECK: bcctrl 7, 3, 0
+# CHECK: bcctrl 7, 3
 0x4c 0xe3 0x04 0x21
 
 # FIXME: decode as bnulr- 2
-# CHECK: bclr 6, 11, 0
+# CHECK: bclr 6, 11
 0x4c 0xcb 0x00 0x20
 
 # FIXME: decode as bnulr- 0
-# CHECK: bclr 6, 3, 0
+# CHECK: bclr 6, 3
 0x4c 0xc3 0x00 0x20
 
 # FIXME: decode as bnuctr- 2
-# CHECK: bcctr 6, 11, 0
+# CHECK: bcctr 6, 11
 0x4c 0xcb 0x04 0x20
 
 # FIXME: decode as bnuctr- 0
-# CHECK: bcctr 6, 3, 0
+# CHECK: bcctr 6, 3
 0x4c 0xc3 0x04 0x20
 
 # FIXME: decode as bnulrl- 2
-# CHECK: bclrl 6, 11, 0
+# CHECK: bclrl 6, 11
 0x4c 0xcb 0x00 0x21
 
 # FIXME: decode as bnulrl- 0
-# CHECK: bclrl 6, 3, 0
+# CHECK: bclrl 6, 3
 0x4c 0xc3 0x00 0x21
 
 # FIXME: decode as bnuctrl- 2
-# CHECK: bcctrl 6, 11, 0
+# CHECK: bcctrl 6, 11
 0x4c 0xcb 0x04 0x21
 
 # FIXME: decode as bnuctrl- 0
-# CHECK: bcctrl 6, 3, 0
+# CHECK: bcctrl 6, 3
 0x4c 0xc3 0x04 0x21
 
 # FIXME: decode as bunlr 2
-# CHECK: bclr 12, 11, 0
+# CHECK: bclr 12, 11
 0x4d 0x8b 0x00 0x20
 
 # FIXME: decode as bunlr 0
-# CHECK: bclr 12, 3, 0
+# CHECK: bclr 12, 3
 0x4d 0x83 0x00 0x20
 
 # FIXME: decode as bunctr 2
-# CHECK: bcctr 12, 11, 0
+# CHECK: bcctr 12, 11
 0x4d 0x8b 0x04 0x20
 
 # FIXME: decode as bunctr 0
-# CHECK: bcctr 12, 3, 0
+# CHECK: bcctr 12, 3
 0x4d 0x83 0x04 0x20
 
 # FIXME: decode as bunlrl 2
-# CHECK: bclrl 12, 11, 0
+# CHECK: bclrl 12, 11
 0x4d 0x8b 0x00 0x21
 
 # FIXME: decode as bunlrl 0
-# CHECK: bclrl 12, 3, 0
+# CHECK: bclrl 12, 3
 0x4d 0x83 0x00 0x21
 
 # FIXME: decode as bunctrl 2
-# CHECK: bcctrl 12, 11, 0
+# CHECK: bcctrl 12, 11
 0x4d 0x8b 0x04 0x21
 
 # FIXME: decode as bunctrl 0
-# CHECK: bcctrl 12, 3, 0
+# CHECK: bcctrl 12, 3
 0x4d 0x83 0x04 0x21
 
 # FIXME: decode as bunlr+ 2
-# CHECK: bclr 15, 11, 0
+# CHECK: bclr 15, 11
 0x4d 0xeb 0x00 0x20
 
 # FIXME: decode as bunlr+ 0
-# CHECK: bclr 15, 3, 0
+# CHECK: bclr 15, 3
 0x4d 0xe3 0x00 0x20
 
 # FIXME: decode as bunctr+ 2
-# CHECK: bcctr 15, 11, 0
+# CHECK: bcctr 15, 11
 0x4d 0xeb 0x04 0x20
 
 # FIXME: decode as bunctr+ 0
-# CHECK: bcctr 15, 3, 0
+# CHECK: bcctr 15, 3
 0x4d 0xe3 0x04 0x20
 
 # FIXME: decode as bunlrl+ 2
-# CHECK: bclrl 15, 11, 0
+# CHECK: bclrl 15, 11
 0x4d 0xeb 0x00 0x21
 
 # FIXME: decode as bunlrl+ 0
-# CHECK: bclrl 15, 3, 0
+# CHECK: bclrl 15, 3
 0x4d 0xe3 0x00 0x21
 
 # FIXME: decode as bunctrl+ 2
-# CHECK: bcctrl 15, 11, 0
+# CHECK: bcctrl 15, 11
 0x4d 0xeb 0x04 0x21
 
 # FIXME: decode as bunctrl+ 0
-# CHECK: bcctrl 15, 3, 0
+# CHECK: bcctrl 15, 3
 0x4d 0xe3 0x04 0x21
 
 # FIXME: decode as bunlr- 2
-# CHECK: bclr 14, 11, 0
+# CHECK: bclr 14, 11
 0x4d 0xcb 0x00 0x20
 
 # FIXME: decode as bunlr- 0
-# CHECK: bclr 14, 3, 0
+# CHECK: bclr 14, 3
 0x4d 0xc3 0x00 0x20
 
 # FIXME: decode as bunctr- 2
-# CHECK: bcctr 14, 11, 0
+# CHECK: bcctr 14, 11
 0x4d 0xcb 0x04 0x20
 
 # FIXME: decode as bunctr- 0
-# CHECK: bcctr 14, 3, 0
+# CHECK: bcctr 14, 3
 0x4d 0xc3 0x04 0x20
 
 # FIXME: decode as bunlrl- 2
-# CHECK: bclrl 14, 11, 0
+# CHECK: bclrl 14, 11
 0x4d 0xcb 0x00 0x21
 
 # FIXME: decode as bunlrl- 0
-# CHECK: bclrl 14, 3, 0
+# CHECK: bclrl 14, 3
 0x4d 0xc3 0x00 0x21
 
 # FIXME: decode as bunctrl- 2
-# CHECK: bcctrl 14, 11, 0
+# CHECK: bcctrl 14, 11
 0x4d 0xcb 0x04 0x21
 
 # FIXME: decode as bunctrl- 0
-# CHECK: bcctrl 14, 3, 0
+# CHECK: bcctrl 14, 3
 0x4d 0xc3 0x04 0x21
 
 # FIXME: decode as bnulr 2
-# CHECK: bclr 4, 11, 0
+# CHECK: bclr 4, 11
 0x4c 0x8b 0x00 0x20
 
 # FIXME: decode as bnulr 0
-# CHECK: bclr 4, 3, 0
+# CHECK: bclr 4, 3
 0x4c 0x83 0x00 0x20
 
 # FIXME: decode as bnuctr 2
-# CHECK: bcctr 4, 11, 0
+# CHECK: bcctr 4, 11
 0x4c 0x8b 0x04 0x20
 
 # FIXME: decode as bnuctr 0
-# CHECK: bcctr 4, 3, 0
+# CHECK: bcctr 4, 3
 0x4c 0x83 0x04 0x20
 
 # FIXME: decode as bnulrl 2
-# CHECK: bclrl 4, 11, 0
+# CHECK: bclrl 4, 11
 0x4c 0x8b 0x00 0x21
 
 # FIXME: decode as bnulrl 0
-# CHECK: bclrl 4, 3, 0
+# CHECK: bclrl 4, 3
 0x4c 0x83 0x00 0x21
 
 # FIXME: decode as bnuctrl 2
-# CHECK: bcctrl 4, 11, 0
+# CHECK: bcctrl 4, 11
 0x4c 0x8b 0x04 0x21
 
 # FIXME: decode as bnuctrl 0
-# CHECK: bcctrl 4, 3, 0
+# CHECK: bcctrl 4, 3
 0x4c 0x83 0x04 0x21
 
 # FIXME: decode as bnulr+ 2
-# CHECK: bclr 7, 11, 0
+# CHECK: bclr 7, 11
 0x4c 0xeb 0x00 0x20
 
 # FIXME: decode as bnulr+ 0
-# CHECK: bclr 7, 3, 0
+# CHECK: bclr 7, 3
 0x4c 0xe3 0x00 0x20
 
 # FIXME: decode as bnuctr+ 2
-# CHECK: bcctr 7, 11, 0
+# CHECK: bcctr 7, 11
 0x4c 0xeb 0x04 0x20
 
 # FIXME: decode as bnuctr+ 0
-# CHECK: bcctr 7, 3, 0
+# CHECK: bcctr 7, 3
 0x4c 0xe3 0x04 0x20
 
 # FIXME: decode as bnulrl+ 2
-# CHECK: bclrl 7, 11, 0
+# CHECK: bclrl 7, 11
 0x4c 0xeb 0x00 0x21
 
 # FIXME: decode as bnulrl+ 0
-# CHECK: bclrl 7, 3, 0
+# CHECK: bclrl 7, 3
 0x4c 0xe3 0x00 0x21
 
 # FIXME: decode as bnuctrl+ 2
-# CHECK: bcctrl 7, 11, 0
+# CHECK: bcctrl 7, 11
 0x4c 0xeb 0x04 0x21
 
 # FIXME: decode as bnuctrl+ 0
-# CHECK: bcctrl 7, 3, 0
+# CHECK: bcctrl 7, 3
 0x4c 0xe3 0x04 0x21
 
 # FIXME: decode as bnulr- 2
-# CHECK: bclr 6, 11, 0
+# CHECK: bclr 6, 11
 0x4c 0xcb 0x00 0x20
 
 # FIXME: decode as bnulr- 0
-# CHECK: bclr 6, 3, 0
+# CHECK: bclr 6, 3
 0x4c 0xc3 0x00 0x20
 
 # FIXME: decode as bnuctr- 2
-# CHECK: bcctr 6, 11, 0
+# CHECK: bcctr 6, 11
 0x4c 0xcb 0x04 0x20
 
 # FIXME: decode as bnuctr- 0
-# CHECK: bcctr 6, 3, 0
+# CHECK: bcctr 6, 3
 0x4c 0xc3 0x04 0x20
 
 # FIXME: decode as bnulrl- 2
-# CHECK: bclrl 6, 11, 0
+# CHECK: bclrl 6, 11
 0x4c 0xcb 0x00 0x21
 
 # FIXME: decode as bnulrl- 0
-# CHECK: bclrl 6, 3, 0
+# CHECK: bclrl 6, 3
 0x4c 0xc3 0x00 0x21
 
 # FIXME: decode as bnuctrl- 2
-# CHECK: bcctrl 6, 11, 0
+# CHECK: bcctrl 6, 11
 0x4c 0xcb 0x04 0x21
 
 # FIXME: decode as bnuctrl- 0
-# CHECK: bcctrl 6, 3, 0
+# CHECK: bcctrl 6, 3
 0x4c 0xc3 0x04 0x21
 
 # FIXME: test bc 12, 2, target
@@ -1801,16 +1801,16 @@
 # FIXME: test bnula- 2, target
 # FIXME: test bnula- 0, target
 
-# CHECK: creqv 2, 2, 2
+# CHECK: crset 2
 0x4c 0x42 0x12 0x42
 
-# CHECK: crxor 2, 2, 2
+# CHECK: crclr 2
 0x4c 0x42 0x11 0x82
 
-# CHECK: cror 2, 3, 3
+# CHECK: crmove 2, 3
 0x4c 0x43 0x1b 0x82
 
-# CHECK: crnor 2, 3, 3
+# CHECK: crnot 2, 3
 0x4c 0x43 0x18 0x42
 
 # CHECK: addi 2, 3, -128
@@ -1840,61 +1840,61 @@
 # CHECK: cmpdi 2, 3, 128
 0x2d 0x23 0x00 0x80
 
-# CHECK: cmpdi 0, 3, 128
+# CHECK: cmpdi 3, 128
 0x2c 0x23 0x00 0x80
 
 # CHECK: cmpd 2, 3, 4
 0x7d 0x23 0x20 0x00
 
-# CHECK: cmpd 0, 3, 4
+# CHECK: cmpd 3, 4
 0x7c 0x23 0x20 0x00
 
 # CHECK: cmpldi 2, 3, 128
 0x29 0x23 0x00 0x80
 
-# CHECK: cmpldi 0, 3, 128
+# CHECK: cmpldi 3, 128
 0x28 0x23 0x00 0x80
 
 # CHECK: cmpld 2, 3, 4
 0x7d 0x23 0x20 0x40
 
-# CHECK: cmpld 0, 3, 4
+# CHECK: cmpld 3, 4
 0x7c 0x23 0x20 0x40
 
 # CHECK: cmpwi 2, 3, 128
 0x2d 0x03 0x00 0x80
 
-# CHECK: cmpwi 0, 3, 128
+# CHECK: cmpwi 3, 128
 0x2c 0x03 0x00 0x80
 
 # CHECK: cmpw 2, 3, 4
 0x7d 0x03 0x20 0x00
 
-# CHECK: cmpw 0, 3, 4
+# CHECK: cmpw 3, 4
 0x7c 0x03 0x20 0x00
 
 # CHECK: cmplwi 2, 3, 128
 0x29 0x03 0x00 0x80
 
-# CHECK: cmplwi 0, 3, 128
+# CHECK: cmplwi 3, 128
 0x28 0x03 0x00 0x80
 
 # CHECK: cmplw 2, 3, 4
 0x7d 0x03 0x20 0x40
 
-# CHECK: cmplw 0, 3, 4
+# CHECK: cmplw 3, 4
 0x7c 0x03 0x20 0x40
 
-# CHECK: twi 16, 3, 4
+# CHECK: twlti 3, 4
 0x0e 0x03 0x00 0x04
 
-# CHECK: tw 16, 3, 4
+# CHECK: twlt 3, 4
 0x7e 0x03 0x20 0x08
 
-# CHECK: tdi 16, 3, 4
+# CHECK: tdlti 3, 4
 0x0a 0x03 0x00 0x04
 
-# CHECK: td 16, 3, 4
+# CHECK: tdlt 3, 4
 0x7e 0x03 0x20 0x88
 
 # CHECK: twi 20, 3, 4
@@ -1909,16 +1909,16 @@
 # CHECK: td 20, 3, 4
 0x7e 0x83 0x20 0x88
 
-# CHECK: twi 4, 3, 4
+# CHECK: tweqi 3, 4
 0x0c 0x83 0x00 0x04
 
-# CHECK: tw 4, 3, 4
+# CHECK: tweq 3, 4
 0x7c 0x83 0x20 0x08
 
-# CHECK: tdi 4, 3, 4
+# CHECK: tdeqi 3, 4
 0x08 0x83 0x00 0x04
 
-# CHECK: td 4, 3, 4
+# CHECK: tdeq 3, 4
 0x7c 0x83 0x20 0x88
 
 # CHECK: twi 12, 3, 4
@@ -1933,16 +1933,16 @@
 # CHECK: td 12, 3, 4
 0x7d 0x83 0x20 0x88
 
-# CHECK: twi 8, 3, 4
+# CHECK: twgti 3, 4
 0x0d 0x03 0x00 0x04
 
-# CHECK: tw 8, 3, 4
+# CHECK: twgt 3, 4
 0x7d 0x03 0x20 0x08
 
-# CHECK: tdi 8, 3, 4
+# CHECK: tdgti 3, 4
 0x09 0x03 0x00 0x04
 
-# CHECK: td 8, 3, 4
+# CHECK: tdgt 3, 4
 0x7d 0x03 0x20 0x88
 
 # CHECK: twi 12, 3, 4
@@ -1957,16 +1957,16 @@
 # CHECK: td 12, 3, 4
 0x7d 0x83 0x20 0x88
 
-# CHECK: twi 24, 3, 4
+# CHECK: twnei 3, 4
 0x0f 0x03 0x00 0x04
 
-# CHECK: tw 24, 3, 4
+# CHECK: twne 3, 4
 0x7f 0x03 0x20 0x08
 
-# CHECK: tdi 24, 3, 4
+# CHECK: tdnei 3, 4
 0x0b 0x03 0x00 0x04
 
-# CHECK: td 24, 3, 4
+# CHECK: tdne 3, 4
 0x7f 0x03 0x20 0x88
 
 # CHECK: twi 20, 3, 4
@@ -1981,16 +1981,16 @@
 # CHECK: td 20, 3, 4
 0x7e 0x83 0x20 0x88
 
-# CHECK: twi 2, 3, 4
+# CHECK: twllti 3, 4
 0x0c 0x43 0x00 0x04
 
-# CHECK: tw 2, 3, 4
+# CHECK: twllt 3, 4
 0x7c 0x43 0x20 0x08
 
-# CHECK: tdi 2, 3, 4
+# CHECK: tdllti 3, 4
 0x08 0x43 0x00 0x04
 
-# CHECK: td 2, 3, 4
+# CHECK: tdllt 3, 4
 0x7c 0x43 0x20 0x88
 
 # CHECK: twi 6, 3, 4
@@ -2017,16 +2017,16 @@
 # CHECK: td 5, 3, 4
 0x7c 0xa3 0x20 0x88
 
-# CHECK: twi 1, 3, 4
+# CHECK: twlgti 3, 4
 0x0c 0x23 0x00 0x04
 
-# CHECK: tw 1, 3, 4
+# CHECK: twlgt 3, 4
 0x7c 0x23 0x20 0x08
 
-# CHECK: tdi 1, 3, 4
+# CHECK: tdlgti 3, 4
 0x08 0x23 0x00 0x04
 
-# CHECK: td 1, 3, 4
+# CHECK: tdlgt 3, 4
 0x7c 0x23 0x20 0x88
 
 # CHECK: twi 5, 3, 4
@@ -2053,16 +2053,16 @@
 # CHECK: td 6, 3, 4
 0x7c 0xc3 0x20 0x88
 
-# CHECK: twi 31, 3, 4
+# CHECK: twui 3, 4
 0x0f 0xe3 0x00 0x04
 
-# CHECK: tw 31, 3, 4
+# CHECK: twu 3, 4
 0x7f 0xe3 0x20 0x08
 
-# CHECK: tdi 31, 3, 4
+# CHECK: tdui 3, 4
 0x0b 0xe3 0x00 0x04
 
-# CHECK: td 31, 3, 4
+# CHECK: tdu 3, 4
 0x7f 0xe3 0x20 0x88
 
 # CHECK: trap
@@ -2086,22 +2086,22 @@
 # CHECK: rldimi. 2, 3, 55, 5
 0x78 0x62 0xb9 0x4f
 
-# CHECK: rldicl 2, 3, 4, 0
+# CHECK: rotldi 2, 3, 4
 0x78 0x62 0x20 0x00
 
-# CHECK: rldicl. 2, 3, 4, 0
+# CHECK: rotldi. 2, 3, 4
 0x78 0x62 0x20 0x01
 
-# CHECK: rldicl 2, 3, 60, 0
+# CHECK: rotldi 2, 3, 60
 0x78 0x62 0xe0 0x02
 
-# CHECK: rldicl. 2, 3, 60, 0
+# CHECK: rotldi. 2, 3, 60
 0x78 0x62 0xe0 0x03
 
-# CHECK: rldcl 2, 3, 4, 0
+# CHECK: rotld 2, 3, 4
 0x78 0x62 0x20 0x10
 
-# CHECK: rldcl. 2, 3, 4, 0
+# CHECK: rotld. 2, 3, 4
 0x78 0x62 0x20 0x11
 
 # CHECK: sldi 2, 3, 4
@@ -2116,10 +2116,10 @@
 # CHECK: rldicl. 2, 3, 60, 4
 0x78 0x62 0xe1 0x03
 
-# CHECK: rldicl 2, 3, 0, 4
+# CHECK: clrldi 2, 3, 4
 0x78 0x62 0x01 0x00
 
-# CHECK: rldicl. 2, 3, 0, 4
+# CHECK: clrldi. 2, 3, 4
 0x78 0x62 0x01 0x01
 
 # CHECK: rldicr 2, 3, 0, 59
@@ -2158,22 +2158,22 @@
 # CHECK: rlwimi. 2, 3, 23, 5, 8
 0x50 0x62 0xb9 0x51
 
-# CHECK: rlwinm 2, 3, 4, 0, 31
+# CHECK: rotlwi 2, 3, 4
 0x54 0x62 0x20 0x3e
 
-# CHECK: rlwinm. 2, 3, 4, 0, 31
+# CHECK: rotlwi. 2, 3, 4
 0x54 0x62 0x20 0x3f
 
-# CHECK: rlwinm 2, 3, 28, 0, 31
+# CHECK: rotlwi 2, 3, 28
 0x54 0x62 0xe0 0x3e
 
-# CHECK: rlwinm. 2, 3, 28, 0, 31
+# CHECK: rotlwi. 2, 3, 28
 0x54 0x62 0xe0 0x3f
 
-# CHECK: rlwnm 2, 3, 4, 0, 31
+# CHECK: rotlw 2, 3, 4
 0x5c 0x62 0x20 0x3e
 
-# CHECK: rlwnm. 2, 3, 4, 0, 31
+# CHECK: rotlw. 2, 3, 4
 0x5c 0x62 0x20 0x3f
 
 # CHECK: slwi 2, 3, 4
@@ -2188,10 +2188,10 @@
 # CHECK: rlwinm. 2, 3, 28, 4, 31
 0x54 0x62 0xe1 0x3f
 
-# CHECK: rlwinm 2, 3, 0, 4, 31
+# CHECK: clrlwi 2, 3, 4
 0x54 0x62 0x01 0x3e
 
-# CHECK: rlwinm. 2, 3, 0, 4, 31
+# CHECK: clrlwi. 2, 3, 4
 0x54 0x62 0x01 0x3f
 
 # CHECK: rlwinm 2, 3, 0, 0, 27
@@ -2206,10 +2206,10 @@
 # CHECK: rlwinm. 2, 3, 4, 1, 27
 0x54 0x62 0x20 0x77
 
-# CHECK: mtspr 1, 2
+# CHECK: mtxer 2
 0x7c 0x41 0x03 0xa6
 
-# CHECK: mfspr 2, 1
+# CHECK: mfxer 2
 0x7c 0x41 0x02 0xa6
 
 # CHECK: mtlr 2
@@ -2227,7 +2227,7 @@
 # CHECK: nop
 0x60 0x00 0x00 0x00
 
-# CHECK: xori 0, 0, 0
+# CHECK: xnop
 0x68 0x00 0x00 0x00
 
 # CHECK: li 2, 128
diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt
index 1c01c9dcf82a..0487e3fdfc23 100644
--- a/test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt
+++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt
@@ -321,6 +321,24 @@
 # CHECK: mffs 2                          
 0xfc 0x40 0x04 0x8e
 
+# CHECK: mffs. 7
+0xfc 0xe0 0x04 0x8f
+
+# CHECK: mcrfs 4, 5
+0xfe 0x14 0x00 0x80
+
+# CHECK: mtfsfi 5, 2, 1
+0xfe 0x81 0x21 0x0c
+
+# CHECK: mtfsfi. 5, 2, 1
+0xfe 0x81 0x21 0x0d
+
+# CHECK: mtfsf 127, 8, 1, 1
+0xfe 0xff 0x45 0x8e
+
+# CHECK: mtfsf. 125, 8, 1, 1
+0xfe 0xfb 0x45 0x8f
+
 # CHECK: mtfsb0 31                       
 0xff 0xe0 0x00 0x8c
 
diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-p8vector.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-p8vector.txt
new file mode 100644
index 000000000000..eeea2db673f2
--- /dev/null
+++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-p8vector.txt
@@ -0,0 +1,19 @@
+# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr8 | FileCheck %s
+
+# CHECK: vpksdss 2, 3, 4
+0x10 0x43 0x25 0xce
+
+# CHECK: vpksdus 2, 3, 4
+0x10 0x43 0x25 0x4e
+
+# CHECK: vpkudus 2, 3, 4
+0x10 0x43 0x24 0xce
+
+# CHECK: vpkudum 2, 3, 4
+0x10 0x43 0x24 0x4e
+
+# CHECK: vupkhsw 2, 3
+0x10 0x40 0x1e 0x4e
+
+# CHECK: vupklsw 2, 3
+0x10 0x40 0x1e 0xce
diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
index 3896bf755434..a6e2367efcdb 100644
--- a/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
+++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
@@ -120,6 +120,42 @@
 # CHECK: vperm 2, 3, 4, 5                
 0x10 0x43 0x21 0x6b
 
+# CHECK: vpermxor 2, 3, 4, 5
+0x10 0x43 0x21 0x6d
+
+# CHECK: vsbox 2, 5
+0x10 0x45 0x05 0xc8
+
+# CHECK: vcipher 2, 5, 17
+0x10 0x45 0x8d 0x08
+
+# CHECK: vcipherlast 2, 5, 17
+0x10 0x45 0x8d 0x09
+
+# CHECK: vncipher 2, 5, 17
+0x10,0x45,0x8d,0x48
+
+# CHECK: vncipherlast 2, 5, 17
+0x10,0x45,0x8d,0x49
+
+# CHECK: vpmsumb 2, 5, 17
+0x10 0x45 0x8c 0x08
+
+# CHECK: vpmsumh 2, 5, 17
+0x10 0x45 0x8c 0x48
+
+# CHECK: vpmsumw 2, 5, 17
+0x10 0x45 0x8c 0x88
+
+# CHECK: vpmsumd 2, 5, 17
+0x10 0x45 0x8c 0xc8
+
+# CHECK: vshasigmaw 2, 3, 0, 11
+0x10 0x43 0x5e 0x82
+
+# CHECK: vshasigmad 2, 3, 1, 15
+0x10 0x43 0xfe 0xc2
+
 # CHECK: vsel 2, 3, 4, 5                 
 0x10 0x43 0x21 0x6a
 
@@ -159,6 +195,9 @@
 # CHECK: vadduwm 2, 3, 4                 
 0x10 0x43 0x20 0x80
 
+# CHECK: vaddudm 2, 3, 4
+0x10 0x43 0x20 0xc0
+
 # CHECK: vaddubs 2, 3, 4                 
 0x10 0x43 0x22 0x00
 
@@ -168,6 +207,18 @@
 # CHECK: vadduws 2, 3, 4                 
 0x10 0x43 0x22 0x80
 
+# CHECK: vadduqm 2, 3, 4
+0x10 0x43 0x21 0x00
+
+# CHECK: vaddeuqm 2, 3, 4, 5
+0x10 0x43 0x21 0x7c
+
+# CHECK: vaddcuq 2, 3, 4
+0x10 0x43 0x21 0x40
+
+# CHECK: vaddecuq 2, 3, 4, 5
+0x10 0x43 0x21 0x7d
+
 # CHECK: vsubcuw 2, 3, 4                 
 0x10 0x43 0x25 0x80
 
@@ -189,6 +240,9 @@
 # CHECK: vsubuwm 2, 3, 4                 
 0x10 0x43 0x24 0x80
 
+# CHECK: vsubudm 2, 3, 4
+0x10 0x43 0x24 0xc0
+
 # CHECK: vsububs 2, 3, 4                 
 0x10 0x43 0x26 0x00
 
@@ -198,30 +252,57 @@
 # CHECK: vsubuws 2, 3, 4                 
 0x10 0x43 0x26 0x80
 
+# CHECK: vsubuqm 2, 3, 4
+0x10 0x43 0x25 0x00
+
+# CHECK: vsubeuqm 2, 3, 4, 5
+0x10 0x43 0x21 0x7e
+
+# CHECK: vsubcuq 2, 3, 4
+0x10 0x43 0x25 0x40
+
+# CHECK: vsubecuq 2, 3, 4, 5
+0x10 0x43 0x21 0x7f
+
 # CHECK: vmulesb 2, 3, 4                 
 0x10 0x43 0x23 0x08
 
 # CHECK: vmulesh 2, 3, 4                 
 0x10 0x43 0x23 0x48
 
+# CHECK: vmulesw 2, 3, 4
+0x10 0x43 0x23 0x88
+
 # CHECK: vmuleub 2, 3, 4                 
 0x10 0x43 0x22 0x08
 
 # CHECK: vmuleuh 2, 3, 4                 
 0x10 0x43 0x22 0x48
 
+# CHECK: vmuleuw 2, 3, 4
+0x10 0x43 0x22 0x88
+
 # CHECK: vmulosb 2, 3, 4                 
 0x10 0x43 0x21 0x08
 
 # CHECK: vmulosh 2, 3, 4                 
 0x10 0x43 0x21 0x48
 
+# CHECK: vmulosw 2, 3, 4
+0x10 0x43 0x21 0x88
+
 # CHECK: vmuloub 2, 3, 4                 
 0x10 0x43 0x20 0x08
 
 # CHECK: vmulouh 2, 3, 4                 
 0x10 0x43 0x20 0x48
 
+# CHECK: vmulouw 2, 3, 4
+0x10 0x43 0x20 0x88
+
+# CHECK: vmuluwm 2, 3, 4
+0x10 0x43 0x20 0x89
+
 # CHECK: vmhaddshs 2, 3, 4, 5            
 0x10 0x43 0x21 0x60
 
@@ -291,6 +372,9 @@
 # CHECK: vmaxsw 2, 3, 4                  
 0x10 0x43 0x21 0x82
 
+# CHECK: vmaxsd 2, 3, 4
+0x10 0x43 0x21 0xc2
+
 # CHECK: vmaxub 2, 3, 4                  
 0x10 0x43 0x20 0x02
 
@@ -300,6 +384,9 @@
 # CHECK: vmaxuw 2, 3, 4                  
 0x10 0x43 0x20 0x82
 
+# CHECK: vmaxud 2, 3, 4
+0x10 0x43 0x20 0xc2
+
 # CHECK: vminsb 2, 3, 4                  
 0x10 0x43 0x23 0x02
 
@@ -309,6 +396,9 @@
 # CHECK: vminsw 2, 3, 4                  
 0x10 0x43 0x23 0x82
 
+# CHECK: vminsd 2, 3, 4
+0x10 0x43 0x23 0xc2
+
 # CHECK: vminub 2, 3, 4                  
 0x10 0x43 0x22 0x02
 
@@ -318,6 +408,9 @@
 # CHECK: vminuw 2, 3, 4                  
 0x10 0x43 0x22 0x82
 
+# CHECK: vminud 2, 3, 4
+0x10 0x43 0x22 0xc2
+
 # CHECK: vcmpequb 2, 3, 4                
 0x10 0x43 0x20 0x06
 
@@ -336,6 +429,12 @@
 # CHECK: vcmpequw. 2, 3, 4               
 0x10 0x43 0x24 0x86
 
+# CHECK: vcmpequd 2, 3, 4
+0x10 0x43 0x20 0xc7
+
+# CHECK: vcmpequd. 2, 3, 4
+0x10 0x43 0x24 0xc7
+
 # CHECK: vcmpgtsb 2, 3, 4                
 0x10 0x43 0x23 0x06
 
@@ -354,6 +453,12 @@
 # CHECK: vcmpgtsw. 2, 3, 4               
 0x10 0x43 0x27 0x86
 
+# CHECK: vcmpgtsd 2, 3, 4
+0x10 0x43 0x23 0xc7
+
+# CHECK: vcmpgtsd. 2, 3, 4
+0x10 0x43 0x27 0xc7
+
 # CHECK: vcmpgtub 2, 3, 4                
 0x10 0x43 0x22 0x06
 
@@ -372,12 +477,27 @@
 # CHECK: vcmpgtuw. 2, 3, 4               
 0x10 0x43 0x26 0x86
 
+# CHECK: vcmpgtud 2, 3, 4
+0x10 0x43 0x22 0xc7
+
+# CHECK: vcmpgtud. 2, 3, 4
+0x10 0x43 0x26 0xc7
+
 # CHECK: vand 2, 3, 4                    
 0x10 0x43 0x24 0x04
 
 # CHECK: vandc 2, 3, 4                   
 0x10 0x43 0x24 0x44
 
+# CHECK: veqv 2, 3, 4
+0x10 0x43 0x26 0x84
+
+# CHECK: vnand 2, 3, 4
+0x10 0x43 0x25 0x84
+
+# CHECK: vorc 2, 3, 4
+0x10 0x43 0x25 0x44
+
 # CHECK: vnor 2, 3, 4                    
 0x10 0x43 0x25 0x04
 
@@ -405,6 +525,9 @@
 # CHECK: vslw 2, 3, 4                    
 0x10 0x43 0x21 0x84
 
+# CHECK: vrld 2, 3, 4
+0x10 0x43 0x20 0xc4
+
 # CHECK: vsrb 2, 3, 4                    
 0x10 0x43 0x22 0x04
 
@@ -414,6 +537,9 @@
 # CHECK: vsrw 2, 3, 4                    
 0x10 0x43 0x22 0x84
 
+# CHECK: vsrd 2, 3, 4
+0x10 0x43 0x26 0xc4
+
 # CHECK: vsrab 2, 3, 4                   
 0x10 0x43 0x23 0x04
 
@@ -423,6 +549,9 @@
 # CHECK: vsraw 2, 3, 4                   
 0x10 0x43 0x23 0x84
 
+# CHECK: vsrad 2, 3, 4
+0x10 0x43 0x23 0xc4
+
 # CHECK: vaddfp 2, 3, 4                  
 0x10 0x43 0x20 0x0a
 
@@ -501,6 +630,30 @@
 # CHECK: vrsqrtefp 2, 3                  
 0x10 0x40 0x19 0x4a
 
+# CHECK: vclzb 2, 3
+0x10 0x40 0x1f 0x02
+
+# CHECK: vclzh 2, 3
+0x10 0x40 0x1f 0x42
+
+# CHECK: vclzw 2, 3
+0x10 0x40 0x1f 0x82
+
+# CHECK: vclzd 2, 3
+0x10 0x40 0x1f 0xc2
+
+# CHECK: vpopcntb 2, 3
+0x10 0x40 0x1f 0x03
+
+# CHECK: vpopcnth 2, 3
+0x10 0x40 0x1f 0x43
+
+# CHECK: vpopcntw 2, 3
+0x10 0x40 0x1f 0x83
+
+# CHECK: vpopcntd 2, 3
+0x10 0x40 0x1f 0xc3
+
 # CHECK: mtvscr 2                        
 0x10 0x00 0x16 0x44
 
diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
index e99d49bbf45c..f235c242fbce 100644
--- a/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
+++ b/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
@@ -19,25 +19,25 @@
 # CHECK: bclr 4, 10, 3                   
 0x4c 0x8a 0x18 0x20
 
-# CHECK: bclr 4, 10, 0                   
+# CHECK: bclr 4, 10
 0x4c 0x8a 0x00 0x20
 
 # CHECK: bclrl 4, 10, 3                  
 0x4c 0x8a 0x18 0x21
 
-# CHECK: bclrl 4, 10, 0                  
+# CHECK: bclrl 4, 10
 0x4c 0x8a 0x00 0x21
 
 # CHECK: bcctr 4, 10, 3                  
 0x4c 0x8a 0x1c 0x20
 
-# CHECK: bcctr 4, 10, 0                  
+# CHECK: bcctr 4, 10
 0x4c 0x8a 0x04 0x20
 
 # CHECK: bcctrl 4, 10, 3                 
 0x4c 0x8a 0x1c 0x21
 
-# CHECK: bcctrl 4, 10, 0                 
+# CHECK: bcctrl 4, 10
 0x4c 0x8a 0x04 0x21
 
 # CHECK: crand 2, 3, 4                   
@@ -70,9 +70,18 @@
 # CHECK: sc 1                            
 0x44 0x00 0x00 0x22
 
-# CHECK: sc 0                            
+# CHECK: sc
 0x44 0x00 0x00 0x02
 
+# CHECK: clrbhrb
+0x7c 0x00 0x03 0x5c
+
+# CHECK: mfbhrbe 9, 983
+0x7d 0x3e 0xba 0x5c
+
+# CHECK: rfebb 1
+0x4c 0x00 0x09 0x24
+
 # CHECK: lbz 2, 128(4)                   
 0x88 0x44 0x00 0x80
 
@@ -328,6 +337,18 @@
 # CHECK: divwu. 2, 3, 4                  
 0x7c 0x43 0x23 0x97
 
+# CHECK: divwe 2, 3, 4
+0x7c 0x43 0x23 0x56
+
+# CHECK: divwe. 2, 3, 4
+0x7c 0x43 0x23 0x57
+
+# CHECK: divweu 2, 3, 4
+0x7c 0x43 0x23 0x16
+
+# CHECK: divweu. 2, 3, 4
+0x7c 0x43 0x23 0x17
+
 # CHECK: mulld 2, 3, 4                   
 0x7c 0x43 0x21 0xd2
 
@@ -358,6 +379,18 @@
 # CHECK: divdu. 2, 3, 4                  
 0x7c 0x43 0x23 0x93
 
+# CHECK: divde 2, 3, 4
+0x7c 0x43 0x23 0x52
+
+# CHECK: divde. 2, 3, 4
+0x7c 0x43 0x23 0x53
+
+# CHECK: divdeu 2, 3, 4
+0x7c 0x43 0x23 0x12
+
+# CHECK: divdeu. 2, 3, 4
+0x7c 0x43 0x23 0x13
+
 # CHECK: cmpdi 2, 3, 128                 
 0x2d 0x23 0x00 0x80
 
@@ -382,16 +415,16 @@
 # CHECK: cmplw 2, 3, 4                   
 0x7d 0x03 0x20 0x40
 
-# CHECK: twi 2, 3, 4                     
+# CHECK: twllti 3, 4
 0x0c 0x43 0x00 0x04
 
-# CHECK: tw 2, 3, 4                      
+# CHECK: twllt 3, 4
 0x7c 0x43 0x20 0x08
 
-# CHECK: tdi 2, 3, 4                     
+# CHECK: tdllti 3, 4
 0x08 0x43 0x00 0x04
 
-# CHECK: td 2, 3, 4                      
+# CHECK: tdllt 3, 4
 0x7c 0x43 0x20 0x88
 
 # CHECK: isel 2, 3, 4, 5                 
@@ -475,10 +508,10 @@
 # CHECK: extsh. 2, 3                     
 0x7c 0x62 0x07 0x35
 
-# CHECK: cntlzw 2, 3                     
+# CHECK: cntlz 2, 3
 0x7c 0x62 0x00 0x34
 
-# CHECK: cntlzw. 2, 3                    
+# CHECK: cntlz. 2, 3
 0x7c 0x62 0x00 0x35
 
 # CHECK: popcntw 2, 3                    
@@ -499,6 +532,9 @@
 # CHECK: popcntd 2, 3                    
 0x7c 0x62 0x03 0xf4
 
+# CHECK: bpermd 2, 3, 4
+0x7c 0x62 0x21 0xf8
+
 # CHECK: cmpb 7, 21, 4
 0x7e 0xa7 0x23 0xf8
 
diff --git a/test/MC/Disassembler/PowerPC/ppc64-operands.txt b/test/MC/Disassembler/PowerPC/ppc64-operands.txt
index a2da3227f7cd..3fcba735584b 100644
--- a/test/MC/Disassembler/PowerPC/ppc64-operands.txt
+++ b/test/MC/Disassembler/PowerPC/ppc64-operands.txt
@@ -85,10 +85,10 @@
 0x48 0x00 0x04 0x02
 
 # FIXME: decode as beq 0, .+1024
-# CHECK: bc 12, 2, .+1024
+# CHECK: bt 2, .+1024
 0x41 0x82 0x04 0x00
 
 # FIXME: decode as beqa 0, 1024
-# CHECK: bca 12, 2, 1024
+# CHECK: bta 2, 1024
 0x41 0x82 0x04 0x02
 
diff --git a/test/MC/Disassembler/PowerPC/qpx.txt b/test/MC/Disassembler/PowerPC/qpx.txt
new file mode 100644
index 000000000000..00e598bd4356
--- /dev/null
+++ b/test/MC/Disassembler/PowerPC/qpx.txt
@@ -0,0 +1,371 @@
+# RUN: llvm-mc --disassemble %s -triple powerpc64-bgq-linux -mcpu=a2q | FileCheck %s
+
+# CHECK: qvfabs 3, 5
+0x10 0x60 0x2a 0x10
+
+# CHECK: qvfadd 3, 4, 5
+0x10 0x64 0x28 0x2a
+
+# CHECK: qvfadds 3, 4, 5
+0x00 0x64 0x28 0x2a
+
+# CHECK: qvfandc 3, 4, 5
+0x10 0x64 0x2a 0x08
+
+# CHECK: qvfand 3, 4, 5
+0x10 0x64 0x28 0x88
+
+# CHECK: qvfcfid 3, 5
+0x10 0x60 0x2e 0x9c
+
+# CHECK: qvfcfids 3, 5
+0x00 0x60 0x2e 0x9c
+
+# CHECK: qvfcfidu 3, 5
+0x10 0x60 0x2f 0x9c
+
+# CHECK: qvfcfidus 3, 5
+0x00 0x60 0x2f 0x9c
+
+# CHECK: qvfclr 3
+0x10 0x63 0x18 0x08
+
+# CHECK: qvfcpsgn 3, 4, 5
+0x10 0x64 0x28 0x10
+
+# CHECK: qvfctfb 3, 4
+0x10 0x64 0x22 0x88
+
+# CHECK: qvfctid 3, 5
+0x10 0x60 0x2e 0x5c
+
+# CHECK: qvfctidu 3, 5
+0x10 0x60 0x2f 0x5c
+
+# CHECK: qvfctiduz 3, 5
+0x10 0x60 0x2f 0x5e
+
+# CHECK: qvfctidz 3, 5
+0x10 0x60 0x2e 0x5e
+
+# CHECK: qvfctiw 3, 5
+0x10 0x60 0x28 0x1c
+
+# CHECK: qvfctiwu 3, 5
+0x10 0x60 0x29 0x1c
+
+# CHECK: qvfctiwuz 3, 5
+0x10 0x60 0x29 0x1e
+
+# CHECK: qvfctiwz 3, 5
+0x10 0x60 0x28 0x1e
+
+# CHECK: qvfequ 3, 4, 5
+0x10 0x64 0x2c 0x88
+
+# CHECK: qvflogical 3, 4, 5, 12
+0x10 0x64 0x2e 0x08
+
+# CHECK: qvfmadd 3, 4, 6, 5
+0x10 0x64 0x29 0xba
+
+# CHECK: qvfmadds 3, 4, 6, 5
+0x00 0x64 0x29 0xba
+
+# CHECK: qvfmr 3, 5
+0x10 0x60 0x28 0x90
+
+# CHECK: qvfmsub 3, 4, 6, 5
+0x10 0x64 0x29 0xb8
+
+# CHECK: qvfmsubs 3, 4, 6, 5
+0x00 0x64 0x29 0xb8
+
+# CHECK: qvfmul 3, 4, 6
+0x10 0x64 0x01 0xb2
+
+# CHECK: qvfmuls 3, 4, 6
+0x00 0x64 0x01 0xb2
+
+# CHECK: qvfnabs 3, 5
+0x10 0x60 0x29 0x10
+
+# CHECK: qvfnand 3, 4, 5
+0x10 0x64 0x2f 0x08
+
+# CHECK: qvfneg 3, 5
+0x10 0x60 0x28 0x50
+
+# CHECK: qvfnmadd 3, 4, 6, 5
+0x10 0x64 0x29 0xbe
+
+# CHECK: qvfnmadds 3, 4, 6, 5
+0x00 0x64 0x29 0xbe
+
+# CHECK: qvfnmsub 3, 4, 6, 5
+0x10 0x64 0x29 0xbc
+
+# CHECK: qvfnmsubs 3, 4, 6, 5
+0x00 0x64 0x29 0xbc
+
+# CHECK: qvfnor 3, 4, 5
+0x10 0x64 0x2c 0x08
+
+# CHECK: qvfnot 3, 4
+0x10 0x64 0x25 0x08
+
+# CHECK: qvforc 3, 4, 5
+0x10 0x64 0x2e 0x88
+
+# CHECK: qvfor 3, 4, 5
+0x10 0x64 0x2b 0x88
+
+# CHECK: qvfperm 3, 4, 5, 6
+0x10 0x64 0x29 0x8c
+
+# CHECK: qvfre 3, 5
+0x10 0x60 0x28 0x30
+
+# CHECK: qvfres 3, 5
+0x00 0x60 0x28 0x30
+
+# CHECK: qvfrim 3, 5
+0x10 0x60 0x2b 0xd0
+
+# CHECK: qvfrin 3, 5
+0x10 0x60 0x2b 0x10
+
+# CHECK: qvfrip 3, 5
+0x10 0x60 0x2b 0x90
+
+# CHECK: qvfriz 3, 5
+0x10 0x60 0x2b 0x50
+
+# CHECK: qvfrsp 3, 5
+0x10 0x60 0x28 0x18
+
+# CHECK: qvfrsqrte 3, 5
+0x10 0x60 0x28 0x34
+
+# CHECK: qvfrsqrtes 3, 5
+0x00 0x60 0x28 0x34
+
+# CHECK: qvfsel 3, 4, 6, 5
+0x10 0x64 0x29 0xae
+
+# CHECK: qvfset 3
+0x10 0x63 0x1f 0x88
+
+# CHECK: qvfsub 3, 4, 5
+0x10 0x64 0x28 0x28
+
+# CHECK: qvfsubs 3, 4, 5
+0x00 0x64 0x28 0x28
+
+# CHECK: qvfxmadd 3, 4, 6, 5
+0x10 0x64 0x29 0x92
+
+# CHECK: qvfxmadds 3, 4, 6, 5
+0x00 0x64 0x29 0x92
+
+# CHECK: qvfxmul 3, 4, 6
+0x10 0x64 0x01 0xa2
+
+# CHECK: qvfxmuls 3, 4, 6
+0x00 0x64 0x01 0xa2
+
+# CHECK: qvfxor 3, 4, 5
+0x10 0x64 0x2b 0x08
+
+# CHECK: qvfxxcpnmadd 3, 4, 6, 5
+0x10 0x64 0x29 0x86
+
+# CHECK: qvfxxcpnmadds 3, 4, 6, 5
+0x00 0x64 0x29 0x86
+
+# CHECK: qvfxxmadd 3, 4, 6, 5
+0x10 0x64 0x29 0x82
+
+# CHECK: qvfxxmadds 3, 4, 6, 5
+0x00 0x64 0x29 0x82
+
+# CHECK: qvfxxnpmadd 3, 4, 6, 5
+0x10 0x64 0x29 0x96
+
+# CHECK: qvfxxnpmadds 3, 4, 6, 5
+0x00 0x64 0x29 0x96
+
+# CHECK: qvlfcduxa 3, 9, 11
+0x7c 0x69 0x58 0xcf
+
+# CHECK: qvlfcdux 3, 9, 11
+0x7c 0x69 0x58 0xce
+
+# CHECK: qvlfcdxa 3, 10, 11
+0x7c 0x6a 0x58 0x8f
+
+# CHECK: qvlfcdx 3, 10, 11
+0x7c 0x6a 0x58 0x8e
+
+# CHECK: qvlfcsuxa 3, 9, 11
+0x7c 0x69 0x58 0x4f
+
+# CHECK: qvlfcsux 3, 9, 11
+0x7c 0x69 0x58 0x4e
+
+# CHECK: qvlfcsxa 3, 10, 11
+0x7c 0x6a 0x58 0x0f
+
+# CHECK: qvlfcsx 3, 10, 11
+0x7c 0x6a 0x58 0x0e
+
+# CHECK: qvlfduxa 3, 9, 11
+0x7c 0x69 0x5c 0xcf
+
+# CHECK: qvlfdux 3, 9, 11
+0x7c 0x69 0x5c 0xce
+
+# CHECK: qvlfdxa 3, 10, 11
+0x7c 0x6a 0x5c 0x8f
+
+# CHECK: qvlfdx 3, 10, 11
+0x7c 0x6a 0x5c 0x8e
+
+# CHECK: qvlfiwaxa 3, 10, 11
+0x7c 0x6a 0x5e 0xcf
+
+# CHECK: qvlfiwax 3, 10, 11
+0x7c 0x6a 0x5e 0xce
+
+# CHECK: qvlfiwzxa 3, 10, 11
+0x7c 0x6a 0x5e 0x8f
+
+# CHECK: qvlfiwzx 3, 10, 11
+0x7c 0x6a 0x5e 0x8e
+
+# CHECK: qvlfsuxa 3, 9, 11
+0x7c 0x69 0x5c 0x4f
+
+# CHECK: qvlfsux 3, 9, 11
+0x7c 0x69 0x5c 0x4e
+
+# CHECK: qvlfsxa 3, 10, 11
+0x7c 0x6a 0x5c 0x0f
+
+# CHECK: qvlfsx 3, 10, 11
+0x7c 0x6a 0x5c 0x0e
+
+# CHECK: qvlpcldx 3, 10, 11
+0x7c 0x6a 0x5c 0x8c
+
+# CHECK: qvlpclsx 3, 10, 11
+0x7c 0x6a 0x5c 0x0c
+
+# CHECK: qvlpcrdx 3, 10, 11
+0x7c 0x6a 0x58 0x8c
+
+# CHECK: qvlpcrsx 3, 10, 11
+0x7c 0x6a 0x58 0x0c
+
+# CHECK: qvstfcduxa 2, 9, 11
+0x7c 0x49 0x59 0xcf
+
+# CHECK: qvstfcduxia 2, 9, 11
+0x7c 0x49 0x59 0xcb
+
+# CHECK: qvstfcduxi 2, 9, 11
+0x7c 0x49 0x59 0xca
+
+# CHECK: qvstfcdux 2, 9, 11
+0x7c 0x49 0x59 0xce
+
+# CHECK: qvstfcdxa 2, 10, 11
+0x7c 0x4a 0x59 0x8f
+
+# CHECK: qvstfcdxia 2, 10, 11
+0x7c 0x4a 0x59 0x8b
+
+# CHECK: qvstfcdxi 2, 10, 11
+0x7c 0x4a 0x59 0x8a
+
+# CHECK: qvstfcdx 2, 10, 11
+0x7c 0x4a 0x59 0x8e
+
+# CHECK: qvstfcsuxa 2, 9, 11
+0x7c 0x49 0x59 0x4f
+
+# CHECK: qvstfcsuxia 2, 9, 11
+0x7c 0x49 0x59 0x4b
+
+# CHECK: qvstfcsuxi 2, 9, 11
+0x7c 0x49 0x59 0x4a
+
+# CHECK: qvstfcsux 2, 9, 11
+0x7c 0x49 0x59 0x4e
+
+# CHECK: qvstfcsxa 2, 10, 11
+0x7c 0x4a 0x59 0x0f
+
+# CHECK: qvstfcsxia 2, 10, 11
+0x7c 0x4a 0x59 0x0b
+
+# CHECK: qvstfcsxi 2, 10, 11
+0x7c 0x4a 0x59 0x0a
+
+# CHECK: qvstfcsx 2, 10, 11
+0x7c 0x4a 0x59 0x0e
+
+# CHECK: qvstfduxa 2, 9, 11
+0x7c 0x49 0x5d 0xcf
+
+# CHECK: qvstfduxia 2, 9, 11
+0x7c 0x49 0x5d 0xcb
+
+# CHECK: qvstfduxi 2, 9, 11
+0x7c 0x49 0x5d 0xca
+
+# CHECK: qvstfdux 2, 9, 11
+0x7c 0x49 0x5d 0xce
+
+# CHECK: qvstfdxa 2, 10, 11
+0x7c 0x4a 0x5d 0x8f
+
+# CHECK: qvstfdxia 2, 10, 11
+0x7c 0x4a 0x5d 0x8b
+
+# CHECK: qvstfdxi 2, 10, 11
+0x7c 0x4a 0x5d 0x8a
+
+# CHECK: qvstfdx 2, 10, 11
+0x7c 0x4a 0x5d 0x8e
+
+# CHECK: qvstfiwxa 2, 10, 11
+0x7c 0x4a 0x5f 0x8f
+
+# CHECK: qvstfiwx 2, 10, 11
+0x7c 0x4a 0x5f 0x8e
+
+# CHECK: qvstfsuxa 2, 9, 11
+0x7c 0x49 0x5d 0x4f
+
+# CHECK: qvstfsuxia 2, 9, 11
+0x7c 0x49 0x5d 0x4b
+
+# CHECK: qvstfsuxi 2, 9, 11
+0x7c 0x49 0x5d 0x4a
+
+# CHECK: qvstfsux 2, 9, 11
+0x7c 0x49 0x5d 0x4e
+
+# CHECK: qvstfsxa 2, 10, 11
+0x7c 0x4a 0x5d 0x0f
+
+# CHECK: qvstfsxia 2, 10, 11
+0x7c 0x4a 0x5d 0x0b
+
+# CHECK: qvstfsxi 2, 10, 11
+0x7c 0x4a 0x5d 0x0a
+
+# CHECK: qvstfsx 2, 10, 11
+0x7c 0x4a 0x5d 0x0e
+
diff --git a/test/MC/Disassembler/PowerPC/vsx.txt b/test/MC/Disassembler/PowerPC/vsx.txt
index b5e2751225e4..04b2eeb0dd2a 100644
--- a/test/MC/Disassembler/PowerPC/vsx.txt
+++ b/test/MC/Disassembler/PowerPC/vsx.txt
@@ -3,6 +3,15 @@
 # CHECK: lxsdx 7, 5, 31
 0x7c 0xe5 0xfc 0x98
 
+# CHECK: lxsiwax 7, 5, 31
+0x7c 0xe5 0xf8 0x98
+
+# CHECK: lxsiwzx 7, 5, 31
+0x7c 0xe5 0xf8 0x18
+
+# CHECK: lxsspx 7, 5, 31
+0x7c 0xe5 0xfc 0x18
+
 # CHECK: lxvd2x 7, 5, 31
 0x7c 0xe5 0xfe 0x98
 
@@ -15,6 +24,12 @@
 # CHECK: stxsdx 8, 5, 31
 0x7d 0x05 0xfd 0x98
 
+# CHECK: stxsiwx 8, 5, 31
+0x7d 0x05 0xf9 0x18
+
+# CHECK: stxsspx 8, 5, 31
+0x7d 0x05 0xfd 0x18
+
 # CHECK: stxvd2x 8, 5, 31
 0x7d 0x05 0xff 0x98
 
@@ -24,6 +39,9 @@
 # CHECK: xsabsdp 7, 27
 0xf0 0xe0 0xdd 0x64
 
+# CHECK: xsaddsp 7, 63, 27
+0xf0 0xff 0xd8 0x04
+
 # CHECK: xsadddp 7, 63, 27
 0xf0 0xff 0xd9 0x04
 
@@ -60,6 +78,9 @@
 # CHECK: xscvuxddp 7, 27
 0xf0 0xe0 0xdd 0xa0
 
+# CHECK: xsdivsp 7, 63, 27
+0xf0 0xff 0xd8 0xc4
+
 # CHECK: xsdivdp 7, 63, 27
 0xf0 0xff 0xd9 0xc4
 
@@ -81,6 +102,9 @@
 # CHECK: xsmsubmdp 7, 63, 27
 0xf0 0xff 0xd9 0xcc
 
+# CHECK: xsmulsp 7, 63, 27
+0xf0 0xff 0xd8 0x84
+
 # CHECK: xsmuldp 7, 63, 27
 0xf0 0xff 0xd9 0x84
 
@@ -117,15 +141,27 @@
 # CHECK: xsrdpiz 7, 27
 0xf0 0xe0 0xd9 0x64
 
+# CHECK: xsresp 7, 27
+0xf0 0xe0 0xd8 0x68
+
 # CHECK: xsredp 7, 27
 0xf0 0xe0 0xd9 0x68
 
+# CHECK: xsrsqrtesp 7, 27
+0xf0 0xe0 0xd8 0x28
+
 # CHECK: xsrsqrtedp 7, 27
 0xf0 0xe0 0xd9 0x28
 
+# CHECK: xssqrtsp 7, 27
+0xf0 0xe0 0xd8 0x2c
+
 # CHECK: xssqrtdp 7, 27
 0xf0 0xe0 0xd9 0x2c
 
+# CHECK: xssubsp 7, 63, 27
+0xf0 0xff 0xd8 0x44
+
 # CHECK: xssubdp 7, 63, 27
 0xf0 0xff 0xd9 0x44
 
@@ -273,12 +309,10 @@
 # CHECK: xvminsp 7, 63, 27
 0xf0 0xff 0xde 0x44
 
-# FIXME: decode as xvmovdp 7, 63
-# CHECK:  xvcpsgndp 7, 63, 63
+# CHECK: xvmovdp 7, 63
 0xf0 0xff 0xff 0x86
 
-# FIXME: decode as xvmovsp 7, 63
-# CHECK:  xvcpsgnsp 7, 63, 63
+# CHECK: xvmovsp 7, 63
 0xf0 0xff 0xfe 0x86
 
 # CHECK: xvmsubadp 7, 63, 27
@@ -404,6 +438,15 @@
 # CHECK: xxland 7, 63, 27
 0xf0 0xff 0xdc 0x14
 
+# CHECK: xxleqv 7, 63, 27
+0xf0 0xff 0xdd 0xd4
+
+# CHECK: xxlnand 7, 63, 27
+0xf0 0xff 0xdd 0x94
+
+# CHECK: xxlorc 7, 63, 27
+0xf0 0xff 0xdd 0x54
+
 # CHECK: xxlandc 7, 63, 27
 0xf0 0xff 0xdc 0x54
 
@@ -416,15 +459,13 @@
 # CHECK: xxlxor 7, 63, 27
 0xf0 0xff 0xdc 0xd4
 
-# FIXME: decode as xxmrghd 7, 63, 27
-# CHECK: xxpermdi 7, 63, 27, 0
+# CHECK: xxmrghd 7, 63, 27
 0xf0 0xff 0xd8 0x54
 
 # CHECK: xxmrghw 7, 63, 27
 0xf0 0xff 0xd8 0x94
 
-# FIXME: decode as xxmrgld 7, 63, 27
-# CHECK:  xxpermdi 7, 63, 27, 3
+# CHECK: xxmrgld 7, 63, 27
 0xf0 0xff 0xdb 0x54
 
 # CHECK: xxmrglw 7, 63, 27
@@ -439,14 +480,26 @@
 # CHECK: xxsldwi 7, 63, 27, 1
 0xf0 0xff 0xd9 0x14
 
-# FIXME: decode as xxspltd 7, 63, 1
-# CHECK: xxpermdi 7, 63, 63, 3
+# CHECK: xxspltd 7, 63, 1
 0xf0 0xff 0xfb 0x56
 
 # CHECK: xxspltw 7, 27, 3
 0xf0 0xe3 0xda 0x90
 
-# FIXME: decode as xxswapd 7, 63
-# CHECK: xxpermdi 7, 63, 63, 2
+# CHECK: xxswapd 7, 63
 0xf0 0xff 0xfa 0x56
 
+# CHECK: mfvsrd 3, 0
+0x7c 0x03 0x00 0x66
+
+# CHECK: mfvsrwz 5, 0
+0x7c 0x05 0x00 0xe6
+
+# CHECK: mtvsrd 0, 3
+0x7c 0x03 0x01 0x66
+
+# CHECK: mtvsrwa 0, 3
+0x7c 0x03 0x01 0xa6
+
+# CHECK: mtvsrwz 0, 3
+0x7c 0x03 0x01 0xe6
diff --git a/test/MC/Disassembler/Sparc/sparc-mem.txt b/test/MC/Disassembler/Sparc/sparc-mem.txt
index 6ad4be167214..5f8886ef8b76 100644
--- a/test/MC/Disassembler/Sparc/sparc-mem.txt
+++ b/test/MC/Disassembler/Sparc/sparc-mem.txt
@@ -9,6 +9,9 @@
 # CHECK:      ldsb [%g1], %o4
 0xd8 0x48 0x60 0x00
 
+# CHECK:      ldsb [%g1], %o4
+0xd8 0x48 0x40 0x00
+
 # CHECK:      ldsh [%i0+%l6], %o2
 0xd4 0x56 0x00 0x16
 
@@ -18,6 +21,9 @@
 # CHECK:      ldsh [%g1], %o4
 0xd8 0x50 0x60 0x00
 
+# CHECK:      ldsh [%g1], %o4
+0xd8 0x50 0x40 0x00
+
 # CHECK:      ldub [%i0+%l6], %o2
 0xd4 0x0e 0x00 0x16
 
@@ -27,6 +33,9 @@
 # CHECK:      ldub [%g1], %o2
 0xd4 0x08 0x60 0x00
 
+# CHECK:      ldub [%g1], %o2
+0xd4 0x08 0x40 0x00
+
 # CHECK:      lduh [%i0+%l6], %o2
 0xd4 0x16 0x00 0x16
 
@@ -36,6 +45,9 @@
 # CHECK:      lduh [%g1], %o2
 0xd4 0x10 0x60 0x00
 
+# CHECK:      lduh [%g1], %o2
+0xd4 0x10 0x40 0x00
+
 # CHECK:      ld [%i0+%l6], %o2
 0xd4 0x06 0x00 0x16
 
@@ -45,6 +57,9 @@
 # CHECK:      ld [%g1], %o2
 0xd4 0x00 0x60 0x00
 
+# CHECK:      ld [%g1], %o2
+0xd4 0x00 0x40 0x00
+
 # CHECK:     ld [%i0+%l6], %f2
 0xc5 0x06 0x00 0x16
 
@@ -54,6 +69,9 @@
 # CHECK:     ld [%g1], %f2
 0xc5 0x00 0x60 0x00
 
+# CHECK:     ld [%g1], %f2
+0xc5 0x00 0x40 0x00
+
 # CHECK:     ldd [%i0+%l6], %f2
 0xc5 0x1e 0x00 0x16
 
@@ -63,6 +81,9 @@
 # CHECK:     ldd [%g1], %f2
 0xc5 0x18 0x60 0x00
 
+# CHECK:     ldd [%g1], %f2
+0xc5 0x18 0x40 0x00
+
 # CHECK:     ldq [%i0+%l6], %f4
 0xc9 0x16 0x00 0x16
 
@@ -72,6 +93,9 @@
 # CHECK:     ldq [%g1], %f4
 0xc9 0x10 0x60 0x00
 
+# CHECK:     ldq [%g1], %f4
+0xc9 0x10 0x40 0x00
+
 # CHECK:     ldx [%i0+%l6], %o2
 0xd4 0x5e 0x00 0x16
 
@@ -81,6 +105,9 @@
 # CHECK:     ldx [%g1], %o2
 0xd4 0x58 0x60 0x00
 
+# CHECK:     ldx [%g1], %o2
+0xd4 0x58 0x40 0x00
+
 # CHECK:     ldsw [%i0+%l6], %o2
 0xd4 0x46 0x00 0x16
 
@@ -90,6 +117,9 @@
 # CHECK:     ldsw [%g1], %o2
 0xd4 0x40 0x60 0x00
 
+# CHECK:     ldsw [%g1], %o2
+0xd4 0x40 0x40 0x00
+
 # CHECK:      stb %o2, [%i0+%l6]
 0xd4 0x2e 0x00 0x16
 
@@ -99,6 +129,9 @@
 # CHECK:      stb %o2, [%g1]
 0xd4 0x28 0x60 0x00
 
+# CHECK:      stb %o2, [%g1]
+0xd4 0x28 0x40 0x00
+
 # CHECK:      sth %o2, [%i0+%l6]
 0xd4 0x36 0x00 0x16
 
@@ -108,6 +141,9 @@
 # CHECK:      sth %o2, [%g1]
 0xd4 0x30 0x60 0x00
 
+# CHECK:      sth %o2, [%g1]
+0xd4 0x30 0x40 0x00
+
 # CHECK:      st %o2, [%i0+%l6]
 0xd4 0x26 0x00 0x16
 
@@ -117,6 +153,9 @@
 # CHECK:      st %o2, [%g1]
 0xd4 0x20 0x60 0x00
 
+# CHECK:      st %o2, [%g1]
+0xd4 0x20 0x40 0x00
+
 # CHECK:      st %f2, [%i0+%l6]
 0xc5 0x26 0x00 0x16
 
@@ -126,6 +165,9 @@
 # CHECK:      st %f2, [%g1]
 0xc5 0x20 0x60 0x00
 
+# CHECK:      st %f2, [%g1]
+0xc5 0x20 0x40 0x00
+
 # CHECK:      std %f2, [%i0+%l6]
 0xc5 0x3e 0x00 0x16
 
@@ -135,6 +177,9 @@
 # CHECK:      std %f2, [%g1]
 0xc5 0x38 0x60 0x00
 
+# CHECK:      std %f2, [%g1]
+0xc5 0x38 0x40 0x00
+
 # CHECK:      stq %f4, [%i0+%l6]
 0xc9 0x36 0x00 0x16
 
@@ -144,6 +189,9 @@
 # CHECK:      stq %f4, [%g1]
 0xc9 0x30 0x60 0x00
 
+# CHECK:      stq %f4, [%g1]
+0xc9 0x30 0x40 0x00
+
 # CHECK:      stx %o2, [%i0+%l6]
 0xd4 0x76 0x00 0x16
 
@@ -153,6 +201,9 @@
 # CHECK:      stx %o2, [%g1]
 0xd4 0x70 0x60 0x00
 
+# CHECK:      stx %o2, [%g1]
+0xd4 0x70 0x40 0x00
+
 # CHECK:     swap [%i0+%l6], %o2
 0xd4 0x7e 0x00 0x16
 
@@ -161,3 +212,12 @@
 
 # CHECK:     swap [%g1], %o2
 0xd4 0x78 0x60 0x00
+
+# CHECK:     swap [%g1], %o2
+0xd4 0x78 0x40 0x00
+
+# CHECK:     swapa [%i0+%l6] 131, %o2
+0xd4 0xfe 0x10 0x76
+
+# CHECK:     swapa [%g1] 131, %o2
+0xd4 0xf8 0x50 0x60
diff --git a/test/MC/Disassembler/Sparc/sparc-special-registers.txt b/test/MC/Disassembler/Sparc/sparc-special-registers.txt
new file mode 100644
index 000000000000..f653dbda605d
--- /dev/null
+++ b/test/MC/Disassembler/Sparc/sparc-special-registers.txt
@@ -0,0 +1,34 @@
+# RUN: llvm-mc --disassemble %s -triple=sparc-unknown-linux | FileCheck %s
+
+# CHECK: wr %g1, -2, %y
+0x81 0x80 0x7f 0xfe
+
+# CHECK: rd %y, %i0
+0xb1 0x40 0x00 0x00
+
+# CHECK: rd %asr1, %i0
+0xb1 0x40 0x40 0x00
+
+# CHECK: wr %i0, 5, %y
+0x81 0x86 0x20 0x05
+
+# CHECK: wr %i0, %i1, %asr15
+0x9f 0x86 0x00 0x19
+
+# CHECK: rd %psr, %i0
+0xb1 0x48 0x00 0x00
+
+# CHECK: rd %wim, %i0
+0xb1 0x50 0x00 0x00
+
+# CHECK: rd %tbr, %i0
+0xb1 0x58 0x00 0x00
+
+# CHECK: wr %i0, 5, %psr
+0x81 0x8e 0x20 0x05
+
+# CHECK: wr %i0, 5, %wim
+0x81 0x96 0x20 0x05
+
+# CHECK: wr %i0, 5, %tbr
+0x81 0x9e 0x20 0x05
diff --git a/test/MC/Disassembler/Sparc/sparc.txt b/test/MC/Disassembler/Sparc/sparc.txt
index a9420246361f..6724ebf8bf25 100644
--- a/test/MC/Disassembler/Sparc/sparc.txt
+++ b/test/MC/Disassembler/Sparc/sparc.txt
@@ -183,9 +183,6 @@
 # CHECK: cmp %g1, -2
 0x80 0xa0 0x7f 0xfe
 
-# CHECK: wr %g1, -2, %y
-0x81 0x80 0x7f 0xfe
-
 # CHECK: unimp 12
 0x00 0x00 0x00 0x0c
 
@@ -200,3 +197,6 @@
 
 # CHECK:  rett %i7+8
 0x81 0xcf 0xe0 0x08
+
+# CHECK: stbar
+0x81 0x43 0xc0 0x00
diff --git a/test/MC/Disassembler/SystemZ/insns-z13-bad.txt b/test/MC/Disassembler/SystemZ/insns-z13-bad.txt
new file mode 100644
index 000000000000..e1cf033f4b7e
--- /dev/null
+++ b/test/MC/Disassembler/SystemZ/insns-z13-bad.txt
@@ -0,0 +1,39 @@
+# Test z13 instructions that don't have PC-relative operands.
+# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=z13 2>&1 \
+# RUN:   | FileCheck %s
+
+# This would be "vlef %v0, 0, 4", but element 4 is invalid.
+#
+#CHECK: warning: invalid instruction encoding
+#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0x40 0x03
+0xe7 0x00 0x00 0x00 0x40 0x03
+
+# ...and again with element 15
+#
+#CHECK: warning: invalid instruction encoding
+#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x03
+0xe7 0x00 0x00 0x00 0xf0 0x03
+
+# This would be "vleg %v0, 0, 2", but element 2 is invalid.
+#
+#CHECK: warning: invalid instruction encoding
+#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0x20 0x02
+0xe7 0x00 0x00 0x00 0x20 0x02
+
+# ...and again with element 15
+#
+#CHECK: warning: invalid instruction encoding
+#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x02
+0xe7 0x00 0x00 0x00 0xf0 0x02
+
+# This would be "vleh %v0, 0, 8", but element 8 is invalid.
+#
+#CHECK: warning: invalid instruction encoding
+#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0x80 0x01
+0xe7 0x00 0x00 0x00 0x80 0x01
+
+# ...and again with element 15
+#
+#CHECK: warning: invalid instruction encoding
+#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x01
+0xe7 0x00 0x00 0x00 0xf0 0x01
diff --git a/test/MC/Disassembler/SystemZ/insns-z13.txt b/test/MC/Disassembler/SystemZ/insns-z13.txt
new file mode 100644
index 000000000000..71e77664abb2
--- /dev/null
+++ b/test/MC/Disassembler/SystemZ/insns-z13.txt
@@ -0,0 +1,3315 @@
+# Test z13 instructions that don't have PC-relative operands.
+# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=z13 \
+# RUN:   | FileCheck %s
+
+#CHECK: lcbb    %r0, 0, 0
+0xe7 0x00 0x00 0x00 0x00 0x27
+
+#CHECK: lcbb    %r1, 2475(%r7,%r8), 12
+0xe7 0x17 0x89 0xab 0xc0 0x27
+
+#CHECK: lcbb    %r15, 4095(%r15,%r15), 15
+0xe7 0xff 0xff 0xff 0xf0 0x27
+
+#CHECK: vab     %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xf3
+
+#CHECK: vab     %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xf3
+
+#CHECK: vab     %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xf3
+
+#CHECK: vaccb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xf1
+
+#CHECK: vaccb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xf1
+
+#CHECK: vaccb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xf1
+
+#CHECK: vacccq  %v0, %v0, %v0, %v0
+0xe7 0x00 0x04 0x00 0x00 0xb9
+
+#CHECK: vacccq  %v3, %v20, %v5, %v22
+0xe7 0x34 0x54 0x00 0x65 0xb9
+
+#CHECK: vacccq  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf4 0x00 0xff 0xb9
+
+#CHECK: vaccf   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xf1
+
+#CHECK: vaccf   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xf1
+
+#CHECK: vaccf   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xf1
+
+#CHECK: vaccg   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xf1
+
+#CHECK: vaccg   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xf1
+
+#CHECK: vaccg   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xf1
+
+#CHECK: vacch   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xf1
+
+#CHECK: vacch   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xf1
+
+#CHECK: vacch   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xf1
+
+#CHECK: vaccq   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x40 0xf1
+
+#CHECK: vaccq   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x4a 0xf1
+
+#CHECK: vaccq   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x4e 0xf1
+
+#CHECK: vacq    %v0, %v0, %v0, %v0
+0xe7 0x00 0x04 0x00 0x00 0xbb
+
+#CHECK: vacq    %v3, %v20, %v5, %v22
+0xe7 0x34 0x54 0x00 0x65 0xbb
+
+#CHECK: vacq    %v31, %v31, %v31, %v31
+0xe7 0xff 0xf4 0x00 0xff 0xbb
+
+#CHECK: vaf     %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xf3
+
+#CHECK: vaf     %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xf3
+
+#CHECK: vaf     %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xf3
+
+#CHECK: vag     %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xf3
+
+#CHECK: vag     %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xf3
+
+#CHECK: vag     %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xf3
+
+#CHECK: vah     %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xf3
+
+#CHECK: vah     %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xf3
+
+#CHECK: vah     %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xf3
+
+#CHECK: vaq     %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x40 0xf3
+
+#CHECK: vaq     %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x4a 0xf3
+
+#CHECK: vaq     %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x4e 0xf3
+
+#CHECK: vavgb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xf2
+
+#CHECK: vavgb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xf2
+
+#CHECK: vavgb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xf2
+
+#CHECK: vavgf   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xf2
+
+#CHECK: vavgf   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xf2
+
+#CHECK: vavgf   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xf2
+
+#CHECK: vavgg   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xf2
+
+#CHECK: vavgg   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xf2
+
+#CHECK: vavgg   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xf2
+
+#CHECK: vavgh   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xf2
+
+#CHECK: vavgh   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xf2
+
+#CHECK: vavgh   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xf2
+
+#CHECK: vavglb  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xf0
+
+#CHECK: vavglb  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xf0
+
+#CHECK: vavglb  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xf0
+
+#CHECK: vavglf  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xf0
+
+#CHECK: vavglf  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xf0
+
+#CHECK: vavglf  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xf0
+
+#CHECK: vavglg  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xf0
+
+#CHECK: vavglg  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xf0
+
+#CHECK: vavglg  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xf0
+
+#CHECK: vavglh  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xf0
+
+#CHECK: vavglh  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xf0
+
+#CHECK: vavglh  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xf0
+
+#CHECK: vcdgb   %v0, %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x30 0xc3
+
+#CHECK: vcdgb   %v19, %v14, 4, 10
+0xe7 0x3e 0x00 0xa4 0x38 0xc3
+
+#CHECK: vcdgb   %v31, %v31, 7, 15
+0xe7 0xff 0x00 0xf7 0x3c 0xc3
+
+#CHECK: vcdlgb  %v0, %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x30 0xc1
+
+#CHECK: vcdlgb  %v19, %v14, 4, 10
+0xe7 0x3e 0x00 0xa4 0x38 0xc1
+
+#CHECK: vcdlgb  %v31, %v31, 7, 15
+0xe7 0xff 0x00 0xf7 0x3c 0xc1
+
+#CHECK: vceqb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xf8
+
+#CHECK: vceqb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xf8
+
+#CHECK: vceqbs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x04 0xf8
+
+#CHECK: vceqb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xf8
+
+#CHECK: vceqf   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xf8
+
+#CHECK: vceqf   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xf8
+
+#CHECK: vceqfs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x24 0xf8
+
+#CHECK: vceqf   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xf8
+
+#CHECK: vceqg   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xf8
+
+#CHECK: vceqg   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xf8
+
+#CHECK: vceqgs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x34 0xf8
+
+#CHECK: vceqg   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xf8
+
+#CHECK: vceqh   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xf8
+
+#CHECK: vceqh   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xf8
+
+#CHECK: vceqhs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x14 0xf8
+
+#CHECK: vceqh   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xf8
+
+#CHECK: vcgdb   %v0, %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x30 0xc2
+
+#CHECK: vcgdb   %v19, %v14, 4, 10
+0xe7 0x3e 0x00 0xa4 0x38 0xc2
+
+#CHECK: vcgdb   %v31, %v31, 7, 15
+0xe7 0xff 0x00 0xf7 0x3c 0xc2
+
+#CHECK: vchb    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xfb
+
+#CHECK: vchb    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xfb
+
+#CHECK: vchbs   %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x04 0xfb
+
+#CHECK: vchb    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xfb
+
+#CHECK: vchf    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xfb
+
+#CHECK: vchf    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xfb
+
+#CHECK: vchfs   %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x24 0xfb
+
+#CHECK: vchf    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xfb
+
+#CHECK: vchg    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xfb
+
+#CHECK: vchg    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xfb
+
+#CHECK: vchgs   %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x34 0xfb
+
+#CHECK: vchg    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xfb
+
+#CHECK: vchh    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xfb
+
+#CHECK: vchh    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xfb
+
+#CHECK: vchhs   %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x14 0xfb
+
+#CHECK: vchh    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xfb
+
+#CHECK: vchlb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xf9
+
+#CHECK: vchlb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xf9
+
+#CHECK: vchlbs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x04 0xf9
+
+#CHECK: vchlb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xf9
+
+#CHECK: vchlf   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xf9
+
+#CHECK: vchlf   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xf9
+
+#CHECK: vchlfs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x24 0xf9
+
+#CHECK: vchlf   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xf9
+
+#CHECK: vchlg   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xf9
+
+#CHECK: vchlg   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xf9
+
+#CHECK: vchlgs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x34 0xf9
+
+#CHECK: vchlg   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xf9
+
+#CHECK: vchlh   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xf9
+
+#CHECK: vchlh   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xf9
+
+#CHECK: vchlhs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x14 0xf9
+
+#CHECK: vchlh   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xf9
+
+#CHECK: vcksm   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x66
+
+#CHECK: vcksm   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x66
+
+#CHECK: vcksm   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x66
+
+#CHECK: vclgdb  %v0, %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x30 0xc0
+
+#CHECK: vclgdb  %v19, %v14, 4, 10
+0xe7 0x3e 0x00 0xa4 0x38 0xc0
+
+#CHECK: vclgdb  %v31, %v31, 7, 15
+0xe7 0xff 0x00 0xf7 0x3c 0xc0
+
+#CHECK: vclzb   %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x53
+
+#CHECK: vclzb   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x08 0x53
+
+#CHECK: vclzb   %v31, %v31
+0xe7 0xff 0x00 0x00 0x0c 0x53
+
+#CHECK: vclzf   %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x53
+
+#CHECK: vclzf   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x28 0x53
+
+#CHECK: vclzf   %v31, %v31
+0xe7 0xff 0x00 0x00 0x2c 0x53
+
+#CHECK: vclzg   %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0x53
+
+#CHECK: vclzg   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x38 0x53
+
+#CHECK: vclzg   %v31, %v31
+0xe7 0xff 0x00 0x00 0x3c 0x53
+
+#CHECK: vclzh   %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x53
+
+#CHECK: vclzh   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x18 0x53
+
+#CHECK: vclzh   %v31, %v31
+0xe7 0xff 0x00 0x00 0x1c 0x53
+
+#CHECK: vctzb   %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x52
+
+#CHECK: vctzb   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x08 0x52
+
+#CHECK: vctzb   %v31, %v31
+0xe7 0xff 0x00 0x00 0x0c 0x52
+
+#CHECK: vctzf   %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x52
+
+#CHECK: vctzf   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x28 0x52
+
+#CHECK: vctzf   %v31, %v31
+0xe7 0xff 0x00 0x00 0x2c 0x52
+
+#CHECK: vctzg   %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0x52
+
+#CHECK: vctzg   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x38 0x52
+
+#CHECK: vctzg   %v31, %v31
+0xe7 0xff 0x00 0x00 0x3c 0x52
+
+#CHECK: vctzh   %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x52
+
+#CHECK: vctzh   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x18 0x52
+
+#CHECK: vctzh   %v31, %v31
+0xe7 0xff 0x00 0x00 0x1c 0x52
+
+#CHECK: vecb    %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xdb
+
+#CHECK: vecb    %v19, %v14
+0xe7 0x3e 0x00 0x00 0x08 0xdb
+
+#CHECK: vecb    %v31, %v31
+0xe7 0xff 0x00 0x00 0x0c 0xdb
+
+#CHECK: vecf    %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xdb
+
+#CHECK: vecf    %v19, %v14
+0xe7 0x3e 0x00 0x00 0x28 0xdb
+
+#CHECK: vecf    %v31, %v31
+0xe7 0xff 0x00 0x00 0x2c 0xdb
+
+#CHECK: vecg    %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xdb
+
+#CHECK: vecg    %v19, %v14
+0xe7 0x3e 0x00 0x00 0x38 0xdb
+
+#CHECK: vecg    %v31, %v31
+0xe7 0xff 0x00 0x00 0x3c 0xdb
+
+#CHECK: vech    %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xdb
+
+#CHECK: vech    %v19, %v14
+0xe7 0x3e 0x00 0x00 0x18 0xdb
+
+#CHECK: vech    %v31, %v31
+0xe7 0xff 0x00 0x00 0x1c 0xdb
+
+#CHECK: veclb   %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xd9
+
+#CHECK: veclb   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x08 0xd9
+
+#CHECK: veclb   %v31, %v31
+0xe7 0xff 0x00 0x00 0x0c 0xd9
+
+#CHECK: veclf   %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xd9
+
+#CHECK: veclf   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x28 0xd9
+
+#CHECK: veclf   %v31, %v31
+0xe7 0xff 0x00 0x00 0x2c 0xd9
+
+#CHECK: veclg   %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xd9
+
+#CHECK: veclg   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x38 0xd9
+
+#CHECK: veclg   %v31, %v31
+0xe7 0xff 0x00 0x00 0x3c 0xd9
+
+#CHECK: veclh   %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xd9
+
+#CHECK: veclh   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x18 0xd9
+
+#CHECK: veclh   %v31, %v31
+0xe7 0xff 0x00 0x00 0x1c 0xd9
+
+#CHECK: verimb  %v0, %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x72
+
+#CHECK: verimb  %v3, %v20, %v5, 103
+0xe7 0x34 0x50 0x67 0x04 0x72
+
+#CHECK: verimb  %v31, %v31, %v31, 255
+0xe7 0xff 0xf0 0xff 0x0e 0x72
+
+#CHECK: verimf  %v0, %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x20 0x72
+
+#CHECK: verimf  %v3, %v20, %v5, 103
+0xe7 0x34 0x50 0x67 0x24 0x72
+
+#CHECK: verimf  %v31, %v31, %v31, 255
+0xe7 0xff 0xf0 0xff 0x2e 0x72
+
+#CHECK: verimg  %v0, %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x30 0x72
+
+#CHECK: verimg  %v3, %v20, %v5, 103
+0xe7 0x34 0x50 0x67 0x34 0x72
+
+#CHECK: verimg  %v31, %v31, %v31, 255
+0xe7 0xff 0xf0 0xff 0x3e 0x72
+
+#CHECK: verimh  %v0, %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x10 0x72
+
+#CHECK: verimh  %v3, %v20, %v5, 103
+0xe7 0x34 0x50 0x67 0x14 0x72
+
+#CHECK: verimh  %v31, %v31, %v31, 255
+0xe7 0xff 0xf0 0xff 0x1e 0x72
+
+#CHECK: verllvb %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x73
+
+#CHECK: verllvb %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x73
+
+#CHECK: verllvb %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x73
+
+#CHECK: verllvf %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x73
+
+#CHECK: verllvf %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0x73
+
+#CHECK: verllvf %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0x73
+
+#CHECK: verllvg %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0x73
+
+#CHECK: verllvg %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0x73
+
+#CHECK: verllvg %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0x73
+
+#CHECK: verllvh %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x73
+
+#CHECK: verllvh %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0x73
+
+#CHECK: verllvh %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0x73
+
+#CHECK: verllb  %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x33
+
+#CHECK: verllb  %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x04 0x33
+
+#CHECK: verllb  %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x0c 0x33
+
+#CHECK: verllf  %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x20 0x33
+
+#CHECK: verllf  %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x24 0x33
+
+#CHECK: verllf  %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x2c 0x33
+
+#CHECK: verllg  %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x30 0x33
+
+#CHECK: verllg  %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x34 0x33
+
+#CHECK: verllg  %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x3c 0x33
+
+#CHECK: verllh  %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x10 0x33
+
+#CHECK: verllh  %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x14 0x33
+
+#CHECK: verllh  %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x1c 0x33
+
+#CHECK: veslvb  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x70
+
+#CHECK: veslvb  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x70
+
+#CHECK: veslvb  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x70
+
+#CHECK: veslvf  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x70
+
+#CHECK: veslvf  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0x70
+
+#CHECK: veslvf  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0x70
+
+#CHECK: veslvg  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0x70
+
+#CHECK: veslvg  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0x70
+
+#CHECK: veslvg  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0x70
+
+#CHECK: veslvh  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x70
+
+#CHECK: veslvh  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0x70
+
+#CHECK: veslvh  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0x70
+
+#CHECK: veslb   %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x30
+
+#CHECK: veslb   %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x04 0x30
+
+#CHECK: veslb   %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x0c 0x30
+
+#CHECK: veslf   %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x20 0x30
+
+#CHECK: veslf   %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x24 0x30
+
+#CHECK: veslf   %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x2c 0x30
+
+#CHECK: veslg   %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x30 0x30
+
+#CHECK: veslg   %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x34 0x30
+
+#CHECK: veslg   %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x3c 0x30
+
+#CHECK: veslh   %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x10 0x30
+
+#CHECK: veslh   %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x14 0x30
+
+#CHECK: veslh   %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x1c 0x30
+
+#CHECK: vesravb %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x7a
+
+#CHECK: vesravb %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x7a
+
+#CHECK: vesravb %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x7a
+
+#CHECK: vesravf %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x7a
+
+#CHECK: vesravf %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0x7a
+
+#CHECK: vesravf %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0x7a
+
+#CHECK: vesravg %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0x7a
+
+#CHECK: vesravg %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0x7a
+
+#CHECK: vesravg %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0x7a
+
+#CHECK: vesravh %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x7a
+
+#CHECK: vesravh %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0x7a
+
+#CHECK: vesravh %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0x7a
+
+#CHECK: vesrab  %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x3a
+
+#CHECK: vesrab  %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x04 0x3a
+
+#CHECK: vesrab  %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x0c 0x3a
+
+#CHECK: vesraf  %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x20 0x3a
+
+#CHECK: vesraf  %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x24 0x3a
+
+#CHECK: vesraf  %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x2c 0x3a
+
+#CHECK: vesrag  %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x30 0x3a
+
+#CHECK: vesrag  %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x34 0x3a
+
+#CHECK: vesrag  %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x3c 0x3a
+
+#CHECK: vesrah  %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x10 0x3a
+
+#CHECK: vesrah  %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x14 0x3a
+
+#CHECK: vesrah  %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x1c 0x3a
+
+#CHECK: vesrlvb %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x78
+
+#CHECK: vesrlvb %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x78
+
+#CHECK: vesrlvb %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x78
+
+#CHECK: vesrlvf %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x78
+
+#CHECK: vesrlvf %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0x78
+
+#CHECK: vesrlvf %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0x78
+
+#CHECK: vesrlvg %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0x78
+
+#CHECK: vesrlvg %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0x78
+
+#CHECK: vesrlvg %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0x78
+
+#CHECK: vesrlvh %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x78
+
+#CHECK: vesrlvh %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0x78
+
+#CHECK: vesrlvh %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0x78
+
+#CHECK: vesrlb  %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x38
+
+#CHECK: vesrlb  %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x04 0x38
+
+#CHECK: vesrlb  %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x0c 0x38
+
+#CHECK: vesrlf  %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x20 0x38
+
+#CHECK: vesrlf  %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x24 0x38
+
+#CHECK: vesrlf  %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x2c 0x38
+
+#CHECK: vesrlg  %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x30 0x38
+
+#CHECK: vesrlg  %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x34 0x38
+
+#CHECK: vesrlg  %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x3c 0x38
+
+#CHECK: vesrlh  %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x10 0x38
+
+#CHECK: vesrlh  %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x14 0x38
+
+#CHECK: vesrlh  %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x1c 0x38
+
+#CHECK: vfadb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xe3
+
+#CHECK: vfadb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xe3
+
+#CHECK: vfadb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xe3
+
+#CHECK: vfaeb   %v0, %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x82
+
+#CHECK: vfaeb   %v0, %v0, %v0, 12
+0xe7 0x00 0x00 0xc0 0x00 0x82
+
+#CHECK: vfaeb   %v18, %v3, %v20, 0
+0xe7 0x23 0x40 0x00 0x0a 0x82
+
+#CHECK: vfaeb   %v31, %v31, %v31, 4
+0xe7 0xff 0xf0 0x40 0x0e 0x82
+
+#CHECK: vfaebs  %v31, %v31, %v31, 8
+0xe7 0xff 0xf0 0x90 0x0e 0x82
+
+#CHECK: vfaezb  %v31, %v31, %v31, 4
+0xe7 0xff 0xf0 0x60 0x0e 0x82
+
+#CHECK: vfaezbs %v31, %v31, %v31, 8
+0xe7 0xff 0xf0 0xb0 0x0e 0x82
+
+#CHECK: vfaef   %v0, %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x20 0x82
+
+#CHECK: vfaef   %v0, %v0, %v0, 12
+0xe7 0x00 0x00 0xc0 0x20 0x82
+
+#CHECK: vfaef   %v18, %v3, %v20, 0
+0xe7 0x23 0x40 0x00 0x2a 0x82
+
+#CHECK: vfaef   %v31, %v31, %v31, 4
+0xe7 0xff 0xf0 0x40 0x2e 0x82
+
+#CHECK: vfaefs  %v31, %v31, %v31, 8
+0xe7 0xff 0xf0 0x90 0x2e 0x82
+
+#CHECK: vfaezf  %v31, %v31, %v31, 4
+0xe7 0xff 0xf0 0x60 0x2e 0x82
+
+#CHECK: vfaezfs %v31, %v31, %v31, 8
+0xe7 0xff 0xf0 0xb0 0x2e 0x82
+
+#CHECK: vfaeh   %v0, %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x10 0x82
+
+#CHECK: vfaeh   %v0, %v0, %v0, 12
+0xe7 0x00 0x00 0xc0 0x10 0x82
+
+#CHECK: vfaeh   %v18, %v3, %v20, 0
+0xe7 0x23 0x40 0x00 0x1a 0x82
+
+#CHECK: vfaeh   %v31, %v31, %v31, 4
+0xe7 0xff 0xf0 0x40 0x1e 0x82
+
+#CHECK: vfaehs  %v31, %v31, %v31, 8
+0xe7 0xff 0xf0 0x90 0x1e 0x82
+
+#CHECK: vfaezh  %v31, %v31, %v31, 4
+0xe7 0xff 0xf0 0x60 0x1e 0x82
+
+#CHECK: vfaezhs %v31, %v31, %v31, 8
+0xe7 0xff 0xf0 0xb0 0x1e 0x82
+
+#CHECK: vfcedb  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xe8
+
+#CHECK: vfcedb  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xe8
+
+#CHECK: vfcedb  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xe8
+
+#CHECK: vfcedbs %v0, %v0, %v0
+0xe7 0x00 0x00 0x10 0x30 0xe8
+
+#CHECK: vfcedbs %v18, %v3, %v20
+0xe7 0x23 0x40 0x10 0x3a 0xe8
+
+#CHECK: vfcedbs %v31, %v31, %v31
+0xe7 0xff 0xf0 0x10 0x3e 0xe8
+
+#CHECK: vfchdb  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xeb
+
+#CHECK: vfchdb  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xeb
+
+#CHECK: vfchdb  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xeb
+
+#CHECK: vfchdbs %v0, %v0, %v0
+0xe7 0x00 0x00 0x10 0x30 0xeb
+
+#CHECK: vfchdbs %v18, %v3, %v20
+0xe7 0x23 0x40 0x10 0x3a 0xeb
+
+#CHECK: vfchdbs %v31, %v31, %v31
+0xe7 0xff 0xf0 0x10 0x3e 0xeb
+
+#CHECK: vfchedb %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xea
+
+#CHECK: vfchedb %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xea
+
+#CHECK: vfchedb %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xea
+
+#CHECK: vfchedbs %v0, %v0, %v0
+0xe7 0x00 0x00 0x10 0x30 0xea
+
+#CHECK: vfchedbs %v18, %v3, %v20
+0xe7 0x23 0x40 0x10 0x3a 0xea
+
+#CHECK: vfchedbs %v31, %v31, %v31
+0xe7 0xff 0xf0 0x10 0x3e 0xea
+
+#CHECK: vfddb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xe5
+
+#CHECK: vfddb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xe5
+
+#CHECK: vfddb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xe5
+
+#CHECK: vfeeb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x80
+
+#CHECK: vfeeb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x80
+
+#CHECK: vfeebs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x04 0x80
+
+#CHECK: vfeezb  %v18, %v3, %v20
+0xe7 0x23 0x40 0x20 0x0a 0x80
+
+#CHECK: vfeezbs %v7, %v24, %v9
+0xe7 0x78 0x90 0x30 0x04 0x80
+
+#CHECK: vfeeb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x80
+
+#CHECK: vfeef   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x80
+
+#CHECK: vfeef   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0x80
+
+#CHECK: vfeefs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x24 0x80
+
+#CHECK: vfeezf  %v18, %v3, %v20
+0xe7 0x23 0x40 0x20 0x2a 0x80
+
+#CHECK: vfeezfs %v7, %v24, %v9
+0xe7 0x78 0x90 0x30 0x24 0x80
+
+#CHECK: vfeef   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0x80
+
+#CHECK: vfeeh   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x80
+
+#CHECK: vfeeh   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0x80
+
+#CHECK: vfeehs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x14 0x80
+
+#CHECK: vfeezh  %v18, %v3, %v20
+0xe7 0x23 0x40 0x20 0x1a 0x80
+
+#CHECK: vfeezhs %v7, %v24, %v9
+0xe7 0x78 0x90 0x30 0x14 0x80
+
+#CHECK: vfeeh   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0x80
+
+#CHECK: vfeneb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x81
+
+#CHECK: vfeneb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x81
+
+#CHECK: vfenebs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x04 0x81
+
+#CHECK: vfenezb  %v18, %v3, %v20
+0xe7 0x23 0x40 0x20 0x0a 0x81
+
+#CHECK: vfenezbs %v7, %v24, %v9
+0xe7 0x78 0x90 0x30 0x04 0x81
+
+#CHECK: vfeneb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x81
+
+#CHECK: vfenef   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x81
+
+#CHECK: vfenef   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0x81
+
+#CHECK: vfenefs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x24 0x81
+
+#CHECK: vfenezf  %v18, %v3, %v20
+0xe7 0x23 0x40 0x20 0x2a 0x81
+
+#CHECK: vfenezfs %v7, %v24, %v9
+0xe7 0x78 0x90 0x30 0x24 0x81
+
+#CHECK: vfenef   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0x81
+
+#CHECK: vfeneh   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x81
+
+#CHECK: vfeneh   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0x81
+
+#CHECK: vfenehs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x14 0x81
+
+#CHECK: vfenezh  %v18, %v3, %v20
+0xe7 0x23 0x40 0x20 0x1a 0x81
+
+#CHECK: vfenezhs %v7, %v24, %v9
+0xe7 0x78 0x90 0x30 0x14 0x81
+
+#CHECK: vfeneh   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0x81
+
+#CHECK: vfidb   %v0, %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x30 0xc7
+
+#CHECK: vfidb   %v19, %v14, 4, 10
+0xe7 0x3e 0x00 0xa4 0x38 0xc7
+
+#CHECK: vfidb   %v31, %v31, 7, 15
+0xe7 0xff 0x00 0xf7 0x3c 0xc7
+
+#CHECK: vistrb  %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x5c
+
+#CHECK: vistrb  %v18, %v3
+0xe7 0x23 0x00 0x00 0x08 0x5c
+
+#CHECK: vistrbs %v7, %v24
+0xe7 0x78 0x00 0x10 0x04 0x5c
+
+#CHECK: vistrb  %v31, %v31
+0xe7 0xff 0x00 0x00 0x0c 0x5c
+
+#CHECK: vistrf  %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x5c
+
+#CHECK: vistrf  %v18, %v3
+0xe7 0x23 0x00 0x00 0x28 0x5c
+
+#CHECK: vistrfs %v7, %v24
+0xe7 0x78 0x00 0x10 0x24 0x5c
+
+#CHECK: vistrf  %v31, %v31
+0xe7 0xff 0x00 0x00 0x2c 0x5c
+
+#CHECK: vistrh  %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x5c
+
+#CHECK: vistrh  %v18, %v3
+0xe7 0x23 0x00 0x00 0x18 0x5c
+
+#CHECK: vistrhs %v7, %v24
+0xe7 0x78 0x00 0x10 0x14 0x5c
+
+#CHECK: vistrh  %v31, %v31
+0xe7 0xff 0x00 0x00 0x1c 0x5c
+
+#CHECK: vfmadb  %v0, %v0, %v0, %v0
+0xe7 0x00 0x03 0x00 0x00 0x8f
+
+#CHECK: vfmadb  %v3, %v20, %v5, %v22
+0xe7 0x34 0x53 0x00 0x65 0x8f
+
+#CHECK: vfmadb  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf3 0x00 0xff 0x8f
+
+#CHECK: vfmdb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xe7
+
+#CHECK: vfmdb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xe7
+
+#CHECK: vfmdb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xe7
+
+#CHECK: vfmsdb  %v0, %v0, %v0, %v0
+0xe7 0x00 0x03 0x00 0x00 0x8e
+
+#CHECK: vfmsdb  %v3, %v20, %v5, %v22
+0xe7 0x34 0x53 0x00 0x65 0x8e
+
+#CHECK: vfmsdb  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf3 0x00 0xff 0x8e
+
+#CHECK: vfsdb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xe2
+
+#CHECK: vfsdb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xe2
+
+#CHECK: vfsdb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xe2
+
+#CHECK: vzero   %v0
+0xe7 0x00 0x00 0x00 0x00 0x44
+
+#CHECK: vgbm    %v0, 1
+0xe7 0x00 0x00 0x01 0x00 0x44
+
+#CHECK: vgbm    %v0, 65534
+0xe7 0x00 0xff 0xfe 0x00 0x44
+
+#CHECK: vone    %v0
+0xe7 0x00 0xff 0xff 0x00 0x44
+
+#CHECK: vgbm    %v17, 4660
+0xe7 0x10 0x12 0x34 0x08 0x44
+
+#CHECK: vone    %v31
+0xe7 0xf0 0xff 0xff 0x08 0x44
+
+#CHECK: vgef    %v0, 0(%v0), 0
+0xe7 0x00 0x00 0x00 0x00 0x13
+
+#CHECK: vgef    %v10, 1000(%v19,%r7), 2
+0xe7 0xa3 0x73 0xe8 0x24 0x13
+
+#CHECK: vgef    %v31, 4095(%v31,%r15), 3
+0xe7 0xff 0xff 0xff 0x3c 0x13
+
+#CHECK: vgeg    %v0, 0(%v0), 0
+0xe7 0x00 0x00 0x00 0x00 0x12
+
+#CHECK: vgeg    %v10, 1000(%v19,%r7), 1
+0xe7 0xa3 0x73 0xe8 0x14 0x12
+
+#CHECK: vgeg    %v31, 4095(%v31,%r15), 1
+0xe7 0xff 0xff 0xff 0x1c 0x12
+
+#CHECK: vgfmab  %v0, %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xbc
+
+#CHECK: vgfmab  %v3, %v20, %v5, %v22
+0xe7 0x34 0x50 0x00 0x65 0xbc
+
+#CHECK: vgfmab  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0xff 0xbc
+
+#CHECK: vgfmaf  %v0, %v0, %v0, %v0
+0xe7 0x00 0x02 0x00 0x00 0xbc
+
+#CHECK: vgfmaf  %v3, %v20, %v5, %v22
+0xe7 0x34 0x52 0x00 0x65 0xbc
+
+#CHECK: vgfmaf  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf2 0x00 0xff 0xbc
+
+#CHECK: vgfmag  %v0, %v0, %v0, %v0
+0xe7 0x00 0x03 0x00 0x00 0xbc
+
+#CHECK: vgfmag  %v3, %v20, %v5, %v22
+0xe7 0x34 0x53 0x00 0x65 0xbc
+
+#CHECK: vgfmag  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf3 0x00 0xff 0xbc
+
+#CHECK: vgfmah  %v0, %v0, %v0, %v0
+0xe7 0x00 0x01 0x00 0x00 0xbc
+
+#CHECK: vgfmah  %v3, %v20, %v5, %v22
+0xe7 0x34 0x51 0x00 0x65 0xbc
+
+#CHECK: vgfmah  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf1 0x00 0xff 0xbc
+
+#CHECK: vgfmb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xb4
+
+#CHECK: vgfmb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xb4
+
+#CHECK: vgfmb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xb4
+
+#CHECK: vgfmf   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xb4
+
+#CHECK: vgfmf   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xb4
+
+#CHECK: vgfmf   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xb4
+
+#CHECK: vgfmg   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xb4
+
+#CHECK: vgfmg   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xb4
+
+#CHECK: vgfmg   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xb4
+
+#CHECK: vgfmh   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xb4
+
+#CHECK: vgfmh   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xb4
+
+#CHECK: vgfmh   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xb4
+
+#CHECK: vgmb    %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x00 0x46
+
+#CHECK: vgmb    %v22, 55, 66
+0xe7 0x60 0x37 0x42 0x08 0x46
+
+#CHECK: vgmb    %v31, 255, 255
+0xe7 0xf0 0xff 0xff 0x08 0x46
+
+#CHECK: vgmf    %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x20 0x46
+
+#CHECK: vgmf    %v22, 55, 66
+0xe7 0x60 0x37 0x42 0x28 0x46
+
+#CHECK: vgmf    %v31, 255, 255
+0xe7 0xf0 0xff 0xff 0x28 0x46
+
+#CHECK: vgmg    %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x30 0x46
+
+#CHECK: vgmg    %v22, 55, 66
+0xe7 0x60 0x37 0x42 0x38 0x46
+
+#CHECK: vgmg    %v31, 255, 255
+0xe7 0xf0 0xff 0xff 0x38 0x46
+
+#CHECK: vgmh    %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x10 0x46
+
+#CHECK: vgmh    %v22, 55, 66
+0xe7 0x60 0x37 0x42 0x18 0x46
+
+#CHECK: vgmh    %v31, 255, 255
+0xe7 0xf0 0xff 0xff 0x18 0x46
+
+#CHECK: vl      %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x06
+
+#CHECK: vl      %v17, 2475(%r7,%r8)
+0xe7 0x17 0x89 0xab 0x08 0x06
+
+#CHECK: vl      %v31, 4095(%r15,%r15)
+0xe7 0xff 0xff 0xff 0x08 0x06
+
+#CHECK: vlbb    %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x00 0x07
+
+#CHECK: vlbb    %v17, 2475(%r7,%r8), 12
+0xe7 0x17 0x89 0xab 0xc8 0x07
+
+#CHECK: vlbb    %v31, 4095(%r15,%r15), 15
+0xe7 0xff 0xff 0xff 0xf8 0x07
+
+#CHECK: vlcb    %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xde
+
+#CHECK: vlcb    %v19, %v14
+0xe7 0x3e 0x00 0x00 0x08 0xde
+
+#CHECK: vlcb    %v31, %v31
+0xe7 0xff 0x00 0x00 0x0c 0xde
+
+#CHECK: vlcf    %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xde
+
+#CHECK: vlcf    %v19, %v14
+0xe7 0x3e 0x00 0x00 0x28 0xde
+
+#CHECK: vlcf    %v31, %v31
+0xe7 0xff 0x00 0x00 0x2c 0xde
+
+#CHECK: vlcg    %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xde
+
+#CHECK: vlcg    %v19, %v14
+0xe7 0x3e 0x00 0x00 0x38 0xde
+
+#CHECK: vlcg    %v31, %v31
+0xe7 0xff 0x00 0x00 0x3c 0xde
+
+#CHECK: vlch    %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xde
+
+#CHECK: vlch    %v19, %v14
+0xe7 0x3e 0x00 0x00 0x18 0xde
+
+#CHECK: vlch    %v31, %v31
+0xe7 0xff 0x00 0x00 0x1c 0xde
+
+#CHECK: vldeb   %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xc4
+
+#CHECK: vldeb   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x28 0xc4
+
+#CHECK: vldeb   %v31, %v31
+0xe7 0xff 0x00 0x00 0x2c 0xc4
+
+#CHECK: vleb    %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x00 0x00
+
+#CHECK: vleb    %v17, 2475(%r7,%r8), 12
+0xe7 0x17 0x89 0xab 0xc8 0x00
+
+#CHECK: vleb    %v31, 4095(%r15,%r15), 15
+0xe7 0xff 0xff 0xff 0xf8 0x00
+
+#CHECK: vledb   %v0, %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x30 0xc5
+
+#CHECK: vledb   %v19, %v14, 4, 10
+0xe7 0x3e 0x00 0xa4 0x38 0xc5
+
+#CHECK: vledb   %v31, %v31, 7, 15
+0xe7 0xff 0x00 0xf7 0x3c 0xc5
+
+#CHECK: vlef    %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x00 0x03
+
+#CHECK: vlef    %v17, 2475(%r7,%r8), 2
+0xe7 0x17 0x89 0xab 0x28 0x03
+
+#CHECK: vlef    %v31, 4095(%r15,%r15), 3
+0xe7 0xff 0xff 0xff 0x38 0x03
+
+#CHECK: vleg    %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x00 0x02
+
+#CHECK: vleg    %v17, 2475(%r7,%r8), 1
+0xe7 0x17 0x89 0xab 0x18 0x02
+
+#CHECK: vleg    %v31, 4095(%r15,%r15), 1
+0xe7 0xff 0xff 0xff 0x18 0x02
+
+#CHECK: vleh    %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x00 0x01
+
+#CHECK: vleh    %v17, 2475(%r7,%r8), 5
+0xe7 0x17 0x89 0xab 0x58 0x01
+
+#CHECK: vleh    %v31, 4095(%r15,%r15), 7
+0xe7 0xff 0xff 0xff 0x78 0x01
+
+#CHECK: vleib   %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x00 0x40
+
+#CHECK: vleib   %v23, -30293, 12
+0xe7 0x70 0x89 0xab 0xc8 0x40
+
+#CHECK: vleib   %v31, -1, 15
+0xe7 0xf0 0xff 0xff 0xf8 0x40
+
+#CHECK: vleif   %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x00 0x43
+
+#CHECK: vleif   %v23, -30293, 2
+0xe7 0x70 0x89 0xab 0x28 0x43
+
+#CHECK: vleif   %v31, -1, 3
+0xe7 0xf0 0xff 0xff 0x38 0x43
+
+#CHECK: vleig   %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x00 0x42
+
+#CHECK: vleig   %v23, -30293, 1
+0xe7 0x70 0x89 0xab 0x18 0x42
+
+#CHECK: vleig   %v31, -1, 1
+0xe7 0xf0 0xff 0xff 0x18 0x42
+
+#CHECK: vleih   %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x00 0x41
+
+#CHECK: vleih   %v23, -30293, 5
+0xe7 0x70 0x89 0xab 0x58 0x41
+
+#CHECK: vleih   %v31, -1, 7
+0xe7 0xf0 0xff 0xff 0x78 0x41
+
+#CHECK: vflcdb  %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xcc
+
+#CHECK: vflcdb  %v19, %v14
+0xe7 0x3e 0x00 0x00 0x38 0xcc
+
+#CHECK: vflcdb  %v31, %v31
+0xe7 0xff 0x00 0x00 0x3c 0xcc
+
+#CHECK: vflndb  %v0, %v0
+0xe7 0x00 0x00 0x10 0x30 0xcc
+
+#CHECK: vflndb  %v19, %v14
+0xe7 0x3e 0x00 0x10 0x38 0xcc
+
+#CHECK: vflndb  %v31, %v31
+0xe7 0xff 0x00 0x10 0x3c 0xcc
+
+#CHECK: vflpdb  %v0, %v0
+0xe7 0x00 0x00 0x20 0x30 0xcc
+
+#CHECK: vflpdb  %v19, %v14
+0xe7 0x3e 0x00 0x20 0x38 0xcc
+
+#CHECK: vflpdb  %v31, %v31
+0xe7 0xff 0x00 0x20 0x3c 0xcc
+
+#CHECK: vlgvb   %r0, %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x21
+
+#CHECK: vlgvb   %r2, %v19, 1383(%r4)
+0xe7 0x23 0x45 0x67 0x04 0x21
+
+#CHECK: vlgvb   %r15, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x04 0x21
+
+#CHECK: vlgvf   %r0, %v0, 0
+0xe7 0x00 0x00 0x00 0x20 0x21
+
+#CHECK: vlgvf   %r2, %v19, 1383(%r4)
+0xe7 0x23 0x45 0x67 0x24 0x21
+
+#CHECK: vlgvf   %r15, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x24 0x21
+
+#CHECK: vlgvg   %r0, %v0, 0
+0xe7 0x00 0x00 0x00 0x30 0x21
+
+#CHECK: vlgvg   %r2, %v19, 1383(%r4)
+0xe7 0x23 0x45 0x67 0x34 0x21
+
+#CHECK: vlgvg   %r15, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x34 0x21
+
+#CHECK: vlgvh   %r0, %v0, 0
+0xe7 0x00 0x00 0x00 0x10 0x21
+
+#CHECK: vlgvh   %r2, %v19, 1383(%r4)
+0xe7 0x23 0x45 0x67 0x14 0x21
+
+#CHECK: vlgvh   %r15, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x14 0x21
+
+#CHECK: vfsqdb  %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xce
+
+#CHECK: vfsqdb  %v19, %v14
+0xe7 0x3e 0x00 0x00 0x38 0xce
+
+#CHECK: vfsqdb  %v31, %v31
+0xe7 0xff 0x00 0x00 0x3c 0xce
+
+#CHECK: vftcidb %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x30 0x4a
+
+#CHECK: vftcidb %v19, %v4, 1383
+0xe7 0x34 0x56 0x70 0x38 0x4a
+
+#CHECK: vftcidb %v31, %v31, 4095
+0xe7 0xff 0xff 0xf0 0x3c 0x4a
+
+#CHECK: vll     %v0, %r0, 0
+0xe7 0x00 0x00 0x00 0x00 0x37
+
+#CHECK: vll     %v18, %r3, 1383(%r4)
+0xe7 0x23 0x45 0x67 0x08 0x37
+
+#CHECK: vll     %v31, %r15, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x08 0x37
+
+#CHECK: vllezb  %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x04
+
+#CHECK: vllezb  %v17, 2475(%r7,%r8)
+0xe7 0x17 0x89 0xab 0x08 0x04
+
+#CHECK: vllezb  %v31, 4095(%r15,%r15)
+0xe7 0xff 0xff 0xff 0x08 0x04
+
+#CHECK: vllezf  %v0, 0
+0xe7 0x00 0x00 0x00 0x20 0x04
+
+#CHECK: vllezf  %v17, 2475(%r7,%r8)
+0xe7 0x17 0x89 0xab 0x28 0x04
+
+#CHECK: vllezf  %v31, 4095(%r15,%r15)
+0xe7 0xff 0xff 0xff 0x28 0x04
+
+#CHECK: vllezg  %v0, 0
+0xe7 0x00 0x00 0x00 0x30 0x04
+
+#CHECK: vllezg  %v17, 2475(%r7,%r8)
+0xe7 0x17 0x89 0xab 0x38 0x04
+
+#CHECK: vllezg  %v31, 4095(%r15,%r15)
+0xe7 0xff 0xff 0xff 0x38 0x04
+
+#CHECK: vllezh  %v0, 0
+0xe7 0x00 0x00 0x00 0x10 0x04
+
+#CHECK: vllezh  %v17, 2475(%r7,%r8)
+0xe7 0x17 0x89 0xab 0x18 0x04
+
+#CHECK: vllezh  %v31, 4095(%r15,%r15)
+0xe7 0xff 0xff 0xff 0x18 0x04
+
+#CHECK: vlm     %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x36
+
+#CHECK: vlm     %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x04 0x36
+
+#CHECK: vlm     %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x0c 0x36
+
+#CHECK: vlpb    %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xdf
+
+#CHECK: vlpb    %v19, %v14
+0xe7 0x3e 0x00 0x00 0x08 0xdf
+
+#CHECK: vlpb    %v31, %v31
+0xe7 0xff 0x00 0x00 0x0c 0xdf
+
+#CHECK: vlpf    %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xdf
+
+#CHECK: vlpf    %v19, %v14
+0xe7 0x3e 0x00 0x00 0x28 0xdf
+
+#CHECK: vlpf    %v31, %v31
+0xe7 0xff 0x00 0x00 0x2c 0xdf
+
+#CHECK: vlpg    %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xdf
+
+#CHECK: vlpg    %v19, %v14
+0xe7 0x3e 0x00 0x00 0x38 0xdf
+
+#CHECK: vlpg    %v31, %v31
+0xe7 0xff 0x00 0x00 0x3c 0xdf
+
+#CHECK: vlph    %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xdf
+
+#CHECK: vlph    %v19, %v14
+0xe7 0x3e 0x00 0x00 0x18 0xdf
+
+#CHECK: vlph    %v31, %v31
+0xe7 0xff 0x00 0x00 0x1c 0xdf
+
+#CHECK: vlr     %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x56
+
+#CHECK: vlr     %v19, %v14
+0xe7 0x3e 0x00 0x00 0x08 0x56
+
+#CHECK: vlr     %v31, %v31
+0xe7 0xff 0x00 0x00 0x0c 0x56
+
+#CHECK: vlrepb   %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x05
+
+#CHECK: vlrepb   %v17, 2475(%r7,%r8)
+0xe7 0x17 0x89 0xab 0x08 0x05
+
+#CHECK: vlrepb   %v31, 4095(%r15,%r15)
+0xe7 0xff 0xff 0xff 0x08 0x05
+
+#CHECK: vlrepf   %v0, 0
+0xe7 0x00 0x00 0x00 0x20 0x05
+
+#CHECK: vlrepf   %v17, 2475(%r7,%r8)
+0xe7 0x17 0x89 0xab 0x28 0x05
+
+#CHECK: vlrepf   %v31, 4095(%r15,%r15)
+0xe7 0xff 0xff 0xff 0x28 0x05
+
+#CHECK: vlrepg   %v0, 0
+0xe7 0x00 0x00 0x00 0x30 0x05
+
+#CHECK: vlrepg   %v17, 2475(%r7,%r8)
+0xe7 0x17 0x89 0xab 0x38 0x05
+
+#CHECK: vlrepg   %v31, 4095(%r15,%r15)
+0xe7 0xff 0xff 0xff 0x38 0x05
+
+#CHECK: vlreph   %v0, 0
+0xe7 0x00 0x00 0x00 0x10 0x05
+
+#CHECK: vlreph   %v17, 2475(%r7,%r8)
+0xe7 0x17 0x89 0xab 0x18 0x05
+
+#CHECK: vlreph   %v31, 4095(%r15,%r15)
+0xe7 0xff 0xff 0xff 0x18 0x05
+
+#CHECK: vlvgb   %v0, %r0, 0
+0xe7 0x00 0x00 0x00 0x00 0x22
+
+#CHECK: vlvgb   %v18, %r3, 1383(%r4)
+0xe7 0x23 0x45 0x67 0x08 0x22
+
+#CHECK: vlvgb   %v31, %r15, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x08 0x22
+
+#CHECK: vlvgf   %v0, %r0, 0
+0xe7 0x00 0x00 0x00 0x20 0x22
+
+#CHECK: vlvgf   %v18, %r3, 1383(%r4)
+0xe7 0x23 0x45 0x67 0x28 0x22
+
+#CHECK: vlvgf   %v31, %r15, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x28 0x22
+
+#CHECK: vlvgg   %v0, %r0, 0
+0xe7 0x00 0x00 0x00 0x30 0x22
+
+#CHECK: vlvgg   %v18, %r3, 1383(%r4)
+0xe7 0x23 0x45 0x67 0x38 0x22
+
+#CHECK: vlvgg   %v31, %r15, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x38 0x22
+
+#CHECK: vlvgh   %v0, %r0, 0
+0xe7 0x00 0x00 0x00 0x10 0x22
+
+#CHECK: vlvgh   %v18, %r3, 1383(%r4)
+0xe7 0x23 0x45 0x67 0x18 0x22
+
+#CHECK: vlvgh   %v31, %r15, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x18 0x22
+
+#CHECK: vlvgp   %v0, %r0, %r0
+0xe7 0x00 0x00 0x00 0x00 0x62
+
+#CHECK: vlvgp   %v18, %r3, %r4
+0xe7 0x23 0x40 0x00 0x08 0x62
+
+#CHECK: vlvgp   %v31, %r15, %r15
+0xe7 0xff 0xf0 0x00 0x08 0x62
+
+#CHECK: vmaeb   %v0, %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xae
+
+#CHECK: vmaeb   %v3, %v20, %v5, %v22
+0xe7 0x34 0x50 0x00 0x65 0xae
+
+#CHECK: vmaeb   %v31, %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0xff 0xae
+
+#CHECK: vmaef   %v0, %v0, %v0, %v0
+0xe7 0x00 0x02 0x00 0x00 0xae
+
+#CHECK: vmaef   %v3, %v20, %v5, %v22
+0xe7 0x34 0x52 0x00 0x65 0xae
+
+#CHECK: vmaef   %v31, %v31, %v31, %v31
+0xe7 0xff 0xf2 0x00 0xff 0xae
+
+#CHECK: vmaeh   %v0, %v0, %v0, %v0
+0xe7 0x00 0x01 0x00 0x00 0xae
+
+#CHECK: vmaeh   %v3, %v20, %v5, %v22
+0xe7 0x34 0x51 0x00 0x65 0xae
+
+#CHECK: vmaeh   %v31, %v31, %v31, %v31
+0xe7 0xff 0xf1 0x00 0xff 0xae
+
+#CHECK: vmahb   %v0, %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xab
+
+#CHECK: vmahb   %v3, %v20, %v5, %v22
+0xe7 0x34 0x50 0x00 0x65 0xab
+
+#CHECK: vmahb   %v31, %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0xff 0xab
+
+#CHECK: vmahf   %v0, %v0, %v0, %v0
+0xe7 0x00 0x02 0x00 0x00 0xab
+
+#CHECK: vmahf   %v3, %v20, %v5, %v22
+0xe7 0x34 0x52 0x00 0x65 0xab
+
+#CHECK: vmahf   %v31, %v31, %v31, %v31
+0xe7 0xff 0xf2 0x00 0xff 0xab
+
+#CHECK: vmahh   %v0, %v0, %v0, %v0
+0xe7 0x00 0x01 0x00 0x00 0xab
+
+#CHECK: vmahh   %v3, %v20, %v5, %v22
+0xe7 0x34 0x51 0x00 0x65 0xab
+
+#CHECK: vmahh   %v31, %v31, %v31, %v31
+0xe7 0xff 0xf1 0x00 0xff 0xab
+
+#CHECK: vmalb   %v0, %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xaa
+
+#CHECK: vmalb   %v3, %v20, %v5, %v22
+0xe7 0x34 0x50 0x00 0x65 0xaa
+
+#CHECK: vmalb   %v31, %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0xff 0xaa
+
+#CHECK: vmaleb  %v0, %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xac
+
+#CHECK: vmaleb  %v3, %v20, %v5, %v22
+0xe7 0x34 0x50 0x00 0x65 0xac
+
+#CHECK: vmaleb  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0xff 0xac
+
+#CHECK: vmalef  %v0, %v0, %v0, %v0
+0xe7 0x00 0x02 0x00 0x00 0xac
+
+#CHECK: vmalef  %v3, %v20, %v5, %v22
+0xe7 0x34 0x52 0x00 0x65 0xac
+
+#CHECK: vmalef  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf2 0x00 0xff 0xac
+
+#CHECK: vmaleh  %v0, %v0, %v0, %v0
+0xe7 0x00 0x01 0x00 0x00 0xac
+
+#CHECK: vmaleh  %v3, %v20, %v5, %v22
+0xe7 0x34 0x51 0x00 0x65 0xac
+
+#CHECK: vmaleh  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf1 0x00 0xff 0xac
+
+#CHECK: vmalf   %v0, %v0, %v0, %v0
+0xe7 0x00 0x02 0x00 0x00 0xaa
+
+#CHECK: vmalf   %v3, %v20, %v5, %v22
+0xe7 0x34 0x52 0x00 0x65 0xaa
+
+#CHECK: vmalf   %v31, %v31, %v31, %v31
+0xe7 0xff 0xf2 0x00 0xff 0xaa
+
+#CHECK: vmalhb  %v0, %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xa9
+
+#CHECK: vmalhb  %v3, %v20, %v5, %v22
+0xe7 0x34 0x50 0x00 0x65 0xa9
+
+#CHECK: vmalhb  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0xff 0xa9
+
+#CHECK: vmalhf  %v0, %v0, %v0, %v0
+0xe7 0x00 0x02 0x00 0x00 0xa9
+
+#CHECK: vmalhf  %v3, %v20, %v5, %v22
+0xe7 0x34 0x52 0x00 0x65 0xa9
+
+#CHECK: vmalhf  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf2 0x00 0xff 0xa9
+
+#CHECK: vmalhh  %v0, %v0, %v0, %v0
+0xe7 0x00 0x01 0x00 0x00 0xa9
+
+#CHECK: vmalhh  %v3, %v20, %v5, %v22
+0xe7 0x34 0x51 0x00 0x65 0xa9
+
+#CHECK: vmalhh  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf1 0x00 0xff 0xa9
+
+#CHECK: vmalhw  %v0, %v0, %v0, %v0
+0xe7 0x00 0x01 0x00 0x00 0xaa
+
+#CHECK: vmalhw  %v3, %v20, %v5, %v22
+0xe7 0x34 0x51 0x00 0x65 0xaa
+
+#CHECK: vmalhw  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf1 0x00 0xff 0xaa
+
+#CHECK: vmalob  %v0, %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xad
+
+#CHECK: vmalob  %v3, %v20, %v5, %v22
+0xe7 0x34 0x50 0x00 0x65 0xad
+
+#CHECK: vmalob  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0xff 0xad
+
+#CHECK: vmalof  %v0, %v0, %v0, %v0
+0xe7 0x00 0x02 0x00 0x00 0xad
+
+#CHECK: vmalof  %v3, %v20, %v5, %v22
+0xe7 0x34 0x52 0x00 0x65 0xad
+
+#CHECK: vmalof  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf2 0x00 0xff 0xad
+
+#CHECK: vmaloh  %v0, %v0, %v0, %v0
+0xe7 0x00 0x01 0x00 0x00 0xad
+
+#CHECK: vmaloh  %v3, %v20, %v5, %v22
+0xe7 0x34 0x51 0x00 0x65 0xad
+
+#CHECK: vmaloh  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf1 0x00 0xff 0xad
+
+#CHECK: vmaob   %v0, %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xaf
+
+#CHECK: vmaob   %v3, %v20, %v5, %v22
+0xe7 0x34 0x50 0x00 0x65 0xaf
+
+#CHECK: vmaob   %v31, %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0xff 0xaf
+
+#CHECK: vmaof   %v0, %v0, %v0, %v0
+0xe7 0x00 0x02 0x00 0x00 0xaf
+
+#CHECK: vmaof   %v3, %v20, %v5, %v22
+0xe7 0x34 0x52 0x00 0x65 0xaf
+
+#CHECK: vmaof   %v31, %v31, %v31, %v31
+0xe7 0xff 0xf2 0x00 0xff 0xaf
+
+#CHECK: vmaoh   %v0, %v0, %v0, %v0
+0xe7 0x00 0x01 0x00 0x00 0xaf
+
+#CHECK: vmaoh   %v3, %v20, %v5, %v22
+0xe7 0x34 0x51 0x00 0x65 0xaf
+
+#CHECK: vmaoh   %v31, %v31, %v31, %v31
+0xe7 0xff 0xf1 0x00 0xff 0xaf
+
+#CHECK: vmeb    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xa6
+
+#CHECK: vmeb    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xa6
+
+#CHECK: vmeb    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xa6
+
+#CHECK: vmef    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xa6
+
+#CHECK: vmef    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xa6
+
+#CHECK: vmef    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xa6
+
+#CHECK: vmeh    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xa6
+
+#CHECK: vmeh    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xa6
+
+#CHECK: vmeh    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xa6
+
+#CHECK: vmhb    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xa3
+
+#CHECK: vmhb    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xa3
+
+#CHECK: vmhb    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xa3
+
+#CHECK: vmhf    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xa3
+
+#CHECK: vmhf    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xa3
+
+#CHECK: vmhf    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xa3
+
+#CHECK: vmhh    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xa3
+
+#CHECK: vmhh    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xa3
+
+#CHECK: vmhh    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xa3
+
+#CHECK: vmlb    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xa2
+
+#CHECK: vmlb    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xa2
+
+#CHECK: vmlb    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xa2
+
+#CHECK: vmlf    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xa2
+
+#CHECK: vmlf    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xa2
+
+#CHECK: vmlf    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xa2
+
+#CHECK: vmleb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xa4
+
+#CHECK: vmleb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xa4
+
+#CHECK: vmleb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xa4
+
+#CHECK: vmlef   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xa4
+
+#CHECK: vmlef   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xa4
+
+#CHECK: vmlef   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xa4
+
+#CHECK: vmleh   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xa4
+
+#CHECK: vmleh   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xa4
+
+#CHECK: vmleh   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xa4
+
+#CHECK: vmlhb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xa1
+
+#CHECK: vmlhb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xa1
+
+#CHECK: vmlhb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xa1
+
+#CHECK: vmlhf   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xa1
+
+#CHECK: vmlhf   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xa1
+
+#CHECK: vmlhf   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xa1
+
+#CHECK: vmlhh   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xa1
+
+#CHECK: vmlhh   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xa1
+
+#CHECK: vmlhh   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xa1
+
+#CHECK: vmlhw   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xa2
+
+#CHECK: vmlhw   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xa2
+
+#CHECK: vmlhw   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xa2
+
+#CHECK: vmlob   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xa5
+
+#CHECK: vmlob   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xa5
+
+#CHECK: vmlob   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xa5
+
+#CHECK: vmlof   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xa5
+
+#CHECK: vmlof   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xa5
+
+#CHECK: vmlof   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xa5
+
+#CHECK: vmloh   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xa5
+
+#CHECK: vmloh   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xa5
+
+#CHECK: vmloh   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xa5
+
+#CHECK: vmnb    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xfe
+
+#CHECK: vmnb    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xfe
+
+#CHECK: vmnb    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xfe
+
+#CHECK: vmnf    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xfe
+
+#CHECK: vmnf    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xfe
+
+#CHECK: vmnf    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xfe
+
+#CHECK: vmng    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xfe
+
+#CHECK: vmng    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xfe
+
+#CHECK: vmng    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xfe
+
+#CHECK: vmnh    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xfe
+
+#CHECK: vmnh    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xfe
+
+#CHECK: vmnh    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xfe
+
+#CHECK: vmnlb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xfc
+
+#CHECK: vmnlb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xfc
+
+#CHECK: vmnlb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xfc
+
+#CHECK: vmnlf   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xfc
+
+#CHECK: vmnlf   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xfc
+
+#CHECK: vmnlf   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xfc
+
+#CHECK: vmnlg   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xfc
+
+#CHECK: vmnlg   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xfc
+
+#CHECK: vmnlg   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xfc
+
+#CHECK: vmnlh   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xfc
+
+#CHECK: vmnlh   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xfc
+
+#CHECK: vmnlh   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xfc
+
+#CHECK: vmob    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xa7
+
+#CHECK: vmob    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xa7
+
+#CHECK: vmob    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xa7
+
+#CHECK: vmof    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xa7
+
+#CHECK: vmof    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xa7
+
+#CHECK: vmof    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xa7
+
+#CHECK: vmoh    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xa7
+
+#CHECK: vmoh    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xa7
+
+#CHECK: vmoh    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xa7
+
+#CHECK: vmrhb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x61
+
+#CHECK: vmrhb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x61
+
+#CHECK: vmrhb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x61
+
+#CHECK: vmrhf   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x61
+
+#CHECK: vmrhf   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0x61
+
+#CHECK: vmrhf   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0x61
+
+#CHECK: vmrhg   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0x61
+
+#CHECK: vmrhg   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0x61
+
+#CHECK: vmrhg   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0x61
+
+#CHECK: vmrhh   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x61
+
+#CHECK: vmrhh   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0x61
+
+#CHECK: vmrhh   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0x61
+
+#CHECK: vmrlb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x60
+
+#CHECK: vmrlb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x60
+
+#CHECK: vmrlb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x60
+
+#CHECK: vmrlf   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x60
+
+#CHECK: vmrlf   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0x60
+
+#CHECK: vmrlf   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0x60
+
+#CHECK: vmrlg   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0x60
+
+#CHECK: vmrlg   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0x60
+
+#CHECK: vmrlg   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0x60
+
+#CHECK: vmrlh   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x60
+
+#CHECK: vmrlh   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0x60
+
+#CHECK: vmrlh   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0x60
+
+#CHECK: vmxb    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xff
+
+#CHECK: vmxb    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xff
+
+#CHECK: vmxb    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xff
+
+#CHECK: vmxf    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xff
+
+#CHECK: vmxf    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xff
+
+#CHECK: vmxf    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xff
+
+#CHECK: vmxg    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xff
+
+#CHECK: vmxg    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xff
+
+#CHECK: vmxg    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xff
+
+#CHECK: vmxh    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xff
+
+#CHECK: vmxh    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xff
+
+#CHECK: vmxh    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xff
+
+#CHECK: vmxlb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xfd
+
+#CHECK: vmxlb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xfd
+
+#CHECK: vmxlb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xfd
+
+#CHECK: vmxlf   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xfd
+
+#CHECK: vmxlf   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xfd
+
+#CHECK: vmxlf   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xfd
+
+#CHECK: vmxlg   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xfd
+
+#CHECK: vmxlg   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xfd
+
+#CHECK: vmxlg   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xfd
+
+#CHECK: vmxlh   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xfd
+
+#CHECK: vmxlh   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xfd
+
+#CHECK: vmxlh   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xfd
+
+#CHECK: vn      %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x68
+
+#CHECK: vn      %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x68
+
+#CHECK: vn      %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x68
+
+#CHECK: vnc     %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x69
+
+#CHECK: vnc     %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x69
+
+#CHECK: vnc     %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x69
+
+#CHECK: vno     %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x6b
+
+#CHECK: vno     %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x6b
+
+#CHECK: vno     %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x6b
+
+#CHECK: vo      %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x6a
+
+#CHECK: vo      %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x6a
+
+#CHECK: vo      %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x6a
+
+#CHECK: vpdi    %v0, %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x84
+
+#CHECK: vpdi    %v3, %v20, %v5, 4
+0xe7 0x34 0x50 0x00 0x44 0x84
+
+#CHECK: vpdi    %v31, %v31, %v31, 15
+0xe7 0xff 0xf0 0x00 0xfe 0x84
+
+#CHECK: vperm   %v0, %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x8c
+
+#CHECK: vperm   %v3, %v20, %v5, %v22
+0xe7 0x34 0x50 0x00 0x65 0x8c
+
+#CHECK: vperm   %v31, %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0xff 0x8c
+
+#CHECK: vpkf    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x94
+
+#CHECK: vpkf    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0x94
+
+#CHECK: vpkf    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0x94
+
+#CHECK: vpkg    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0x94
+
+#CHECK: vpkg    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0x94
+
+#CHECK: vpkg    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0x94
+
+#CHECK: vpkh    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x94
+
+#CHECK: vpkh    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0x94
+
+#CHECK: vpkh    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0x94
+
+#CHECK: vpklsf  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x95
+
+#CHECK: vpklsf  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0x95
+
+#CHECK: vpklsfs %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x24 0x95
+
+#CHECK: vpklsf  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0x95
+
+#CHECK: vpklsg  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0x95
+
+#CHECK: vpklsg  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0x95
+
+#CHECK: vpklsgs %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x34 0x95
+
+#CHECK: vpklsg  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0x95
+
+#CHECK: vpklsh  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x95
+
+#CHECK: vpklsh  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0x95
+
+#CHECK: vpklshs %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x14 0x95
+
+#CHECK: vpklsh  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0x95
+
+#CHECK: vpksf   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x97
+
+#CHECK: vpksf   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0x97
+
+#CHECK: vpksfs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x24 0x97
+
+#CHECK: vpksf   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0x97
+
+#CHECK: vpksg   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0x97
+
+#CHECK: vpksg   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0x97
+
+#CHECK: vpksgs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x34 0x97
+
+#CHECK: vpksg   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0x97
+
+#CHECK: vpksh   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x97
+
+#CHECK: vpksh   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0x97
+
+#CHECK: vpkshs  %v7, %v24, %v9
+0xe7 0x78 0x90 0x10 0x14 0x97
+
+#CHECK: vpksh   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0x97
+
+#CHECK: vpopct  %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x50
+
+#CHECK: vpopct  %v19, %v14, 0
+0xe7 0x3e 0x00 0x00 0x08 0x50
+
+#CHECK: vpopct  %v31, %v31
+0xe7 0xff 0x00 0x00 0x0c 0x50
+
+#CHECK: vrepb   %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x4d
+
+#CHECK: vrepb   %v19, %v4, 22136
+0xe7 0x34 0x56 0x78 0x08 0x4d
+
+#CHECK: vrepb   %v31, %v31, 65535
+0xe7 0xff 0xff 0xff 0x0c 0x4d
+
+#CHECK: vrepf   %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x20 0x4d
+
+#CHECK: vrepf   %v19, %v4, 22136
+0xe7 0x34 0x56 0x78 0x28 0x4d
+
+#CHECK: vrepf   %v31, %v31, 65535
+0xe7 0xff 0xff 0xff 0x2c 0x4d
+
+#CHECK: vrepg   %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x30 0x4d
+
+#CHECK: vrepg   %v19, %v4, 22136
+0xe7 0x34 0x56 0x78 0x38 0x4d
+
+#CHECK: vrepg   %v31, %v31, 65535
+0xe7 0xff 0xff 0xff 0x3c 0x4d
+
+#CHECK: vreph   %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x10 0x4d
+
+#CHECK: vreph   %v19, %v4, 22136
+0xe7 0x34 0x56 0x78 0x18 0x4d
+
+#CHECK: vreph   %v31, %v31, 65535
+0xe7 0xff 0xff 0xff 0x1c 0x4d
+
+#CHECK: vrepib  %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x45
+
+#CHECK: vrepib  %v23, -30293
+0xe7 0x70 0x89 0xab 0x08 0x45
+
+#CHECK: vrepib  %v31, -1
+0xe7 0xf0 0xff 0xff 0x08 0x45
+
+#CHECK: vrepif  %v0, 0
+0xe7 0x00 0x00 0x00 0x20 0x45
+
+#CHECK: vrepif  %v23, -30293
+0xe7 0x70 0x89 0xab 0x28 0x45
+
+#CHECK: vrepif  %v31, -1
+0xe7 0xf0 0xff 0xff 0x28 0x45
+
+#CHECK: vrepig  %v0, 0
+0xe7 0x00 0x00 0x00 0x30 0x45
+
+#CHECK: vrepig  %v23, -30293
+0xe7 0x70 0x89 0xab 0x38 0x45
+
+#CHECK: vrepig  %v31, -1
+0xe7 0xf0 0xff 0xff 0x38 0x45
+
+#CHECK: vrepih  %v0, 0
+0xe7 0x00 0x00 0x00 0x10 0x45
+
+#CHECK: vrepih  %v23, -30293
+0xe7 0x70 0x89 0xab 0x18 0x45
+
+#CHECK: vrepih  %v31, -1
+0xe7 0xf0 0xff 0xff 0x18 0x45
+
+#CHECK: vsb     %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xf7
+
+#CHECK: vsb     %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xf7
+
+#CHECK: vsb     %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xf7
+
+#CHECK: vsbiq   %v0, %v0, %v0, %v0
+0xe7 0x00 0x04 0x00 0x00 0xbf
+
+#CHECK: vsbiq   %v3, %v20, %v5, %v22
+0xe7 0x34 0x54 0x00 0x65 0xbf
+
+#CHECK: vsbiq   %v31, %v31, %v31, %v31
+0xe7 0xff 0xf4 0x00 0xff 0xbf
+
+#CHECK: vsbcbiq %v0, %v0, %v0, %v0
+0xe7 0x00 0x04 0x00 0x00 0xbd
+
+#CHECK: vsbcbiq %v3, %v20, %v5, %v22
+0xe7 0x34 0x54 0x00 0x65 0xbd
+
+#CHECK: vsbcbiq %v31, %v31, %v31, %v31
+0xe7 0xff 0xf4 0x00 0xff 0xbd
+
+#CHECK: vscbib  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xf5
+
+#CHECK: vscbib  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0xf5
+
+#CHECK: vscbib  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0xf5
+
+#CHECK: vscbif  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xf5
+
+#CHECK: vscbif  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xf5
+
+#CHECK: vscbif  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xf5
+
+#CHECK: vscbig  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xf5
+
+#CHECK: vscbig  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xf5
+
+#CHECK: vscbig  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xf5
+
+#CHECK: vscbih  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xf5
+
+#CHECK: vscbih  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xf5
+
+#CHECK: vscbih  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xf5
+
+#CHECK: vscbiq  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x40 0xf5
+
+#CHECK: vscbiq  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x4a 0xf5
+
+#CHECK: vscbiq  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x4e 0xf5
+
+#CHECK: vscef   %v0, 0(%v0), 0
+0xe7 0x00 0x00 0x00 0x00 0x1b
+
+#CHECK: vscef   %v10, 1000(%v19,%r7), 2
+0xe7 0xa3 0x73 0xe8 0x24 0x1b
+
+#CHECK: vscef   %v31, 4095(%v31,%r15), 3
+0xe7 0xff 0xff 0xff 0x3c 0x1b
+
+#CHECK: vsceg   %v0, 0(%v0), 0
+0xe7 0x00 0x00 0x00 0x00 0x1a
+
+#CHECK: vsceg   %v10, 1000(%v19,%r7), 1
+0xe7 0xa3 0x73 0xe8 0x14 0x1a
+
+#CHECK: vsceg   %v31, 4095(%v31,%r15), 1
+0xe7 0xff 0xff 0xff 0x1c 0x1a
+
+#CHECK: vsegb   %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x5f
+
+#CHECK: vsegb   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x08 0x5f
+
+#CHECK: vsegb   %v31, %v31
+0xe7 0xff 0x00 0x00 0x0c 0x5f
+
+#CHECK: vsegf   %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x5f
+
+#CHECK: vsegf   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x28 0x5f
+
+#CHECK: vsegf   %v31, %v31
+0xe7 0xff 0x00 0x00 0x2c 0x5f
+
+#CHECK: vsegh   %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x5f
+
+#CHECK: vsegh   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x18 0x5f
+
+#CHECK: vsegh   %v31, %v31
+0xe7 0xff 0x00 0x00 0x1c 0x5f
+
+#CHECK: vsel    %v0, %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x8d
+
+#CHECK: vsel    %v3, %v20, %v5, %v22
+0xe7 0x34 0x50 0x00 0x65 0x8d
+
+#CHECK: vsel    %v31, %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0xff 0x8d
+
+#CHECK: vsf     %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xf7
+
+#CHECK: vsf     %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0xf7
+
+#CHECK: vsf     %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0xf7
+
+#CHECK: vsg     %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0xf7
+
+#CHECK: vsg     %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0xf7
+
+#CHECK: vsg     %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0xf7
+
+#CHECK: vsh     %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xf7
+
+#CHECK: vsh     %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0xf7
+
+#CHECK: vsh     %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0xf7
+
+#CHECK: vsl     %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x74
+
+#CHECK: vsl     %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x74
+
+#CHECK: vsl     %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x74
+
+#CHECK: vslb    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x75
+
+#CHECK: vslb    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x75
+
+#CHECK: vslb    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x75
+
+#CHECK: vsldb   %v0, %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x77
+
+#CHECK: vsldb   %v3, %v20, %v5, 103
+0xe7 0x34 0x50 0x67 0x04 0x77
+
+#CHECK: vsldb   %v31, %v31, %v31, 255
+0xe7 0xff 0xf0 0xff 0x0e 0x77
+
+#CHECK: vsq     %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x40 0xf7
+
+#CHECK: vsq     %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x4a 0xf7
+
+#CHECK: vsq     %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x4e 0xf7
+
+#CHECK: vsra    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x7e
+
+#CHECK: vsra    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x7e
+
+#CHECK: vsra    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x7e
+
+#CHECK: vsrab   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x7f
+
+#CHECK: vsrab   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x7f
+
+#CHECK: vsrab   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x7f
+
+#CHECK: vsrl    %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x7c
+
+#CHECK: vsrl    %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x7c
+
+#CHECK: vsrl    %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x7c
+
+#CHECK: vsrlb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x7d
+
+#CHECK: vsrlb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x7d
+
+#CHECK: vsrlb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x7d
+
+#CHECK: vst     %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x0E
+
+#CHECK: vst     %v17, 2475(%r7,%r8)
+0xe7 0x17 0x89 0xab 0x08 0x0E
+
+#CHECK: vst     %v31, 4095(%r15,%r15)
+0xe7 0xff 0xff 0xff 0x08 0x0E
+
+#CHECK: vsteb   %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x00 0x08
+
+#CHECK: vsteb   %v17, 2475(%r7,%r8), 12
+0xe7 0x17 0x89 0xab 0xc8 0x08
+
+#CHECK: vsteb   %v31, 4095(%r15,%r15), 15
+0xe7 0xff 0xff 0xff 0xf8 0x08
+
+#CHECK: vstef   %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x00 0x0b
+
+#CHECK: vstef   %v17, 2475(%r7,%r8), 2
+0xe7 0x17 0x89 0xab 0x28 0x0b
+
+#CHECK: vstef   %v31, 4095(%r15,%r15), 3
+0xe7 0xff 0xff 0xff 0x38 0x0b
+
+#CHECK: vsteg   %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x00 0x0a
+
+#CHECK: vsteg   %v17, 2475(%r7,%r8), 1
+0xe7 0x17 0x89 0xab 0x18 0x0a
+
+#CHECK: vsteg   %v31, 4095(%r15,%r15), 1
+0xe7 0xff 0xff 0xff 0x18 0x0a
+
+#CHECK: vsteh   %v0, 0, 0
+0xe7 0x00 0x00 0x00 0x00 0x09
+
+#CHECK: vsteh   %v17, 2475(%r7,%r8), 5
+0xe7 0x17 0x89 0xab 0x58 0x09
+
+#CHECK: vsteh   %v31, 4095(%r15,%r15), 7
+0xe7 0xff 0xff 0xff 0x78 0x09
+
+#CHECK: vstl    %v0, %r0, 0
+0xe7 0x00 0x00 0x00 0x00 0x3f
+
+#CHECK: vstl    %v18, %r3, 1383(%r4)
+0xe7 0x23 0x45 0x67 0x08 0x3f
+
+#CHECK: vstl    %v31, %r15, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x08 0x3f
+
+#CHECK: vstm    %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x3e
+
+#CHECK: vstm    %v12, %v18, 1110(%r3)
+0xe7 0xc2 0x34 0x56 0x04 0x3e
+
+#CHECK: vstm    %v31, %v31, 4095(%r15)
+0xe7 0xff 0xff 0xff 0x0c 0x3e
+
+#CHECK: vstrcb   %v0, %v0, %v0, %v0, 0
+0xe7 0x00 0x00 0x00 0x00 0x8a
+
+#CHECK: vstrcb   %v0, %v0, %v0, %v0, 12
+0xe7 0x00 0x00 0xc0 0x00 0x8a
+
+#CHECK: vstrcb   %v18, %v3, %v20, %v5, 0
+0xe7 0x23 0x40 0x00 0x5a 0x8a
+
+#CHECK: vstrcb   %v31, %v31, %v31, %v31, 4
+0xe7 0xff 0xf0 0x40 0xff 0x8a
+
+#CHECK: vstrcbs  %v31, %v31, %v31, %v31, 8
+0xe7 0xff 0xf0 0x90 0xff 0x8a
+
+#CHECK: vstrczb  %v31, %v31, %v31, %v31, 4
+0xe7 0xff 0xf0 0x60 0xff 0x8a
+
+#CHECK: vstrczbs %v31, %v31, %v31, %v31, 8
+0xe7 0xff 0xf0 0xb0 0xff 0x8a
+
+#CHECK: vstrcf   %v0, %v0, %v0, %v0, 0
+0xe7 0x00 0x02 0x00 0x00 0x8a
+
+#CHECK: vstrcf   %v0, %v0, %v0, %v0, 12
+0xe7 0x00 0x02 0xc0 0x00 0x8a
+
+#CHECK: vstrcf   %v18, %v3, %v20, %v5, 0
+0xe7 0x23 0x42 0x00 0x5a 0x8a
+
+#CHECK: vstrcf   %v31, %v31, %v31, %v31, 4
+0xe7 0xff 0xf2 0x40 0xff 0x8a
+
+#CHECK: vstrcfs  %v31, %v31, %v31, %v31, 8
+0xe7 0xff 0xf2 0x90 0xff 0x8a
+
+#CHECK: vstrczf  %v31, %v31, %v31, %v31, 4
+0xe7 0xff 0xf2 0x60 0xff 0x8a
+
+#CHECK: vstrczfs %v31, %v31, %v31, %v31, 8
+0xe7 0xff 0xf2 0xb0 0xff 0x8a
+
+#CHECK: vstrch   %v0, %v0, %v0, %v0, 0
+0xe7 0x00 0x01 0x00 0x00 0x8a
+
+#CHECK: vstrch   %v0, %v0, %v0, %v0, 12
+0xe7 0x00 0x01 0xc0 0x00 0x8a
+
+#CHECK: vstrch   %v18, %v3, %v20, %v5, 0
+0xe7 0x23 0x41 0x00 0x5a 0x8a
+
+#CHECK: vstrch   %v31, %v31, %v31, %v31, 4
+0xe7 0xff 0xf1 0x40 0xff 0x8a
+
+#CHECK: vstrchs  %v31, %v31, %v31, %v31, 8
+0xe7 0xff 0xf1 0x90 0xff 0x8a
+
+#CHECK: vstrczh  %v31, %v31, %v31, %v31, 4
+0xe7 0xff 0xf1 0x60 0xff 0x8a
+
+#CHECK: vstrczhs %v31, %v31, %v31, %v31, 8
+0xe7 0xff 0xf1 0xb0 0xff 0x8a
+
+#CHECK: vsumgh  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x65
+
+#CHECK: vsumgh  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0x65
+
+#CHECK: vsumgh  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0x65
+
+#CHECK: vsumgf  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x65
+
+#CHECK: vsumgf  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0x65
+
+#CHECK: vsumgf  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0x65
+
+#CHECK: vsumqf  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0x67
+
+#CHECK: vsumqf  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x2a 0x67
+
+#CHECK: vsumqf  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x2e 0x67
+
+#CHECK: vsumqg  %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x30 0x67
+
+#CHECK: vsumqg  %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x3a 0x67
+
+#CHECK: vsumqg  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x3e 0x67
+
+#CHECK: vsumb   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x64
+
+#CHECK: vsumb   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x64
+
+#CHECK: vsumb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x64
+
+#CHECK: vsumh   %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0x64
+
+#CHECK: vsumh   %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x1a 0x64
+
+#CHECK: vsumh   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x1e 0x64
+
+#CHECK: vtm     %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xd8
+
+#CHECK: vtm     %v19, %v14
+0xe7 0x3e 0x00 0x00 0x08 0xd8
+
+#CHECK: vtm     %v31, %v31
+0xe7 0xff 0x00 0x00 0x0c 0xd8
+
+#CHECK: vuphb   %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xd7
+
+#CHECK: vuphb   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x08 0xd7
+
+#CHECK: vuphb   %v31, %v31
+0xe7 0xff 0x00 0x00 0x0c 0xd7
+
+#CHECK: vuphf   %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xd7
+
+#CHECK: vuphf   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x28 0xd7
+
+#CHECK: vuphf   %v31, %v31
+0xe7 0xff 0x00 0x00 0x2c 0xd7
+
+#CHECK: vuphh   %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xd7
+
+#CHECK: vuphh   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x18 0xd7
+
+#CHECK: vuphh   %v31, %v31
+0xe7 0xff 0x00 0x00 0x1c 0xd7
+
+#CHECK: vuplhb  %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xd5
+
+#CHECK: vuplhb  %v19, %v14
+0xe7 0x3e 0x00 0x00 0x08 0xd5
+
+#CHECK: vuplhb  %v31, %v31
+0xe7 0xff 0x00 0x00 0x0c 0xd5
+
+#CHECK: vuplhf  %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xd5
+
+#CHECK: vuplhf  %v19, %v14
+0xe7 0x3e 0x00 0x00 0x28 0xd5
+
+#CHECK: vuplhf  %v31, %v31
+0xe7 0xff 0x00 0x00 0x2c 0xd5
+
+#CHECK: vuplhh  %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xd5
+
+#CHECK: vuplhh  %v19, %v14
+0xe7 0x3e 0x00 0x00 0x18 0xd5
+
+#CHECK: vuplhh  %v31, %v31
+0xe7 0xff 0x00 0x00 0x1c 0xd5
+
+#CHECK: vuplb   %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xd6
+
+#CHECK: vuplb   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x08 0xd6
+
+#CHECK: vuplb   %v31, %v31
+0xe7 0xff 0x00 0x00 0x0c 0xd6
+
+#CHECK: vuplf   %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xd6
+
+#CHECK: vuplf   %v19, %v14
+0xe7 0x3e 0x00 0x00 0x28 0xd6
+
+#CHECK: vuplf   %v31, %v31
+0xe7 0xff 0x00 0x00 0x2c 0xd6
+
+#CHECK: vuplhw  %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xd6
+
+#CHECK: vuplhw  %v19, %v14
+0xe7 0x3e 0x00 0x00 0x18 0xd6
+
+#CHECK: vuplhw  %v31, %v31
+0xe7 0xff 0x00 0x00 0x1c 0xd6
+
+#CHECK: vupllb  %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0xd4
+
+#CHECK: vupllb  %v19, %v14
+0xe7 0x3e 0x00 0x00 0x08 0xd4
+
+#CHECK: vupllb  %v31, %v31
+0xe7 0xff 0x00 0x00 0x0c 0xd4
+
+#CHECK: vupllf  %v0, %v0
+0xe7 0x00 0x00 0x00 0x20 0xd4
+
+#CHECK: vupllf  %v19, %v14
+0xe7 0x3e 0x00 0x00 0x28 0xd4
+
+#CHECK: vupllf  %v31, %v31
+0xe7 0xff 0x00 0x00 0x2c 0xd4
+
+#CHECK: vupllh  %v0, %v0
+0xe7 0x00 0x00 0x00 0x10 0xd4
+
+#CHECK: vupllh  %v19, %v14
+0xe7 0x3e 0x00 0x00 0x18 0xd4
+
+#CHECK: vupllh  %v31, %v31
+0xe7 0xff 0x00 0x00 0x1c 0xd4
+
+#CHECK: vx      %v0, %v0, %v0
+0xe7 0x00 0x00 0x00 0x00 0x6d
+
+#CHECK: vx      %v18, %v3, %v20
+0xe7 0x23 0x40 0x00 0x0a 0x6d
+
+#CHECK: vx      %v31, %v31, %v31
+0xe7 0xff 0xf0 0x00 0x0e 0x6d
+
+#CHECK: wcdgb   %f0, %f0, 0, 0
+0xe7 0x00 0x00 0x08 0x30 0xc3
+
+#CHECK: wcdgb   %v19, %f14, 4, 10
+0xe7 0x3e 0x00 0xac 0x38 0xc3
+
+#CHECK: wcdgb   %v31, %v31, 7, 15
+0xe7 0xff 0x00 0xff 0x3c 0xc3
+
+#CHECK: wcdlgb  %f0, %f0, 0, 0
+0xe7 0x00 0x00 0x08 0x30 0xc1
+
+#CHECK: wcdlgb  %v19, %f14, 4, 10
+0xe7 0x3e 0x00 0xac 0x38 0xc1
+
+#CHECK: wcdlgb  %v31, %v31, 7, 15
+0xe7 0xff 0x00 0xff 0x3c 0xc1
+
+#CHECK: wcgdb   %f0, %f0, 0, 0
+0xe7 0x00 0x00 0x08 0x30 0xc2
+
+#CHECK: wcgdb   %v19, %f14, 4, 10
+0xe7 0x3e 0x00 0xac 0x38 0xc2
+
+#CHECK: wcgdb   %v31, %v31, 7, 15
+0xe7 0xff 0x00 0xff 0x3c 0xc2
+
+#CHECK: wclgdb  %f0, %f0, 0, 0
+0xe7 0x00 0x00 0x08 0x30 0xc0
+
+#CHECK: wclgdb  %v19, %f14, 4, 10
+0xe7 0x3e 0x00 0xac 0x38 0xc0
+
+#CHECK: wclgdb  %v31, %v31, 7, 15
+0xe7 0xff 0x00 0xff 0x3c 0xc0
+
+#CHECK: wfadb   %f0, %f0, %f0
+0xe7 0x00 0x00 0x08 0x30 0xe3
+
+#CHECK: wfadb   %v18, %f3, %v20
+0xe7 0x23 0x40 0x08 0x3a 0xe3
+
+#CHECK: wfadb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x08 0x3e 0xe3
+
+#CHECK: wfcdb   %f0, %f0
+0xe7 0x00 0x00 0x00 0x30 0xcb
+
+#CHECK: wfcdb   %v19, %f14
+0xe7 0x3e 0x00 0x00 0x38 0xcb
+
+#CHECK: wfcdb   %v31, %v31
+0xe7 0xff 0x00 0x00 0x3c 0xcb
+
+#CHECK: wfcedb  %f0, %f0, %f0
+0xe7 0x00 0x00 0x08 0x30 0xe8
+
+#CHECK: wfcedb  %v18, %f3, %v20
+0xe7 0x23 0x40 0x08 0x3a 0xe8
+
+#CHECK: wfcedb  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x08 0x3e 0xe8
+
+#CHECK: wfcedbs %f0, %f0, %f0
+0xe7 0x00 0x00 0x18 0x30 0xe8
+
+#CHECK: wfcedbs %v18, %f3, %v20
+0xe7 0x23 0x40 0x18 0x3a 0xe8
+
+#CHECK: wfcedbs %v31, %v31, %v31
+0xe7 0xff 0xf0 0x18 0x3e 0xe8
+
+#CHECK: wfchdb  %f0, %f0, %f0
+0xe7 0x00 0x00 0x08 0x30 0xeb
+
+#CHECK: wfchdb  %v18, %f3, %v20
+0xe7 0x23 0x40 0x08 0x3a 0xeb
+
+#CHECK: wfchdb  %v31, %v31, %v31
+0xe7 0xff 0xf0 0x08 0x3e 0xeb
+
+#CHECK: wfchdbs %f0, %f0, %f0
+0xe7 0x00 0x00 0x18 0x30 0xeb
+
+#CHECK: wfchdbs %v18, %f3, %v20
+0xe7 0x23 0x40 0x18 0x3a 0xeb
+
+#CHECK: wfchdbs %v31, %v31, %v31
+0xe7 0xff 0xf0 0x18 0x3e 0xeb
+
+#CHECK: wfchedb %f0, %f0, %f0
+0xe7 0x00 0x00 0x08 0x30 0xea
+
+#CHECK: wfchedb %v18, %f3, %v20
+0xe7 0x23 0x40 0x08 0x3a 0xea
+
+#CHECK: wfchedb %v31, %v31, %v31
+0xe7 0xff 0xf0 0x08 0x3e 0xea
+
+#CHECK: wfchedbs %f0, %f0, %f0
+0xe7 0x00 0x00 0x18 0x30 0xea
+
+#CHECK: wfchedbs %v18, %f3, %v20
+0xe7 0x23 0x40 0x18 0x3a 0xea
+
+#CHECK: wfchedbs %v31, %v31, %v31
+0xe7 0xff 0xf0 0x18 0x3e 0xea
+
+#CHECK: wfddb   %f0, %f0, %f0
+0xe7 0x00 0x00 0x08 0x30 0xe5
+
+#CHECK: wfddb   %v18, %f3, %v20
+0xe7 0x23 0x40 0x08 0x3a 0xe5
+
+#CHECK: wfddb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x08 0x3e 0xe5
+
+#CHECK: wfidb   %f0, %f0, 0, 0
+0xe7 0x00 0x00 0x08 0x30 0xc7
+
+#CHECK: wfidb   %v19, %f14, 4, 10
+0xe7 0x3e 0x00 0xac 0x38 0xc7
+
+#CHECK: wfidb   %v31, %v31, 7, 15
+0xe7 0xff 0x00 0xff 0x3c 0xc7
+
+#CHECK: wfkdb   %f0, %f0
+0xe7 0x00 0x00 0x00 0x30 0xca
+
+#CHECK: wfkdb   %v19, %f14
+0xe7 0x3e 0x00 0x00 0x38 0xca
+
+#CHECK: wfkdb   %v31, %v31
+0xe7 0xff 0x00 0x00 0x3c 0xca
+
+#CHECK: wflcdb  %f0, %f0
+0xe7 0x00 0x00 0x08 0x30 0xcc
+
+#CHECK: wflcdb  %v19, %f14
+0xe7 0x3e 0x00 0x08 0x38 0xcc
+
+#CHECK: wflcdb  %v31, %v31
+0xe7 0xff 0x00 0x08 0x3c 0xcc
+
+#CHECK: wflndb  %f0, %f0
+0xe7 0x00 0x00 0x18 0x30 0xcc
+
+#CHECK: wflndb  %v19, %f14
+0xe7 0x3e 0x00 0x18 0x38 0xcc
+
+#CHECK: wflndb  %v31, %v31
+0xe7 0xff 0x00 0x18 0x3c 0xcc
+
+#CHECK: wflpdb  %f0, %f0
+0xe7 0x00 0x00 0x28 0x30 0xcc
+
+#CHECK: wflpdb  %v19, %f14
+0xe7 0x3e 0x00 0x28 0x38 0xcc
+
+#CHECK: wflpdb  %v31, %v31
+0xe7 0xff 0x00 0x28 0x3c 0xcc
+
+#CHECK: wfmadb  %f0, %f0, %f0, %f0
+0xe7 0x00 0x03 0x08 0x00 0x8f
+
+#CHECK: wfmadb  %f3, %v20, %f5, %v22
+0xe7 0x34 0x53 0x08 0x65 0x8f
+
+#CHECK: wfmadb  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf3 0x08 0xff 0x8f
+
+#CHECK: wfmdb   %f0, %f0, %f0
+0xe7 0x00 0x00 0x08 0x30 0xe7
+
+#CHECK: wfmdb   %v18, %f3, %v20
+0xe7 0x23 0x40 0x08 0x3a 0xe7
+
+#CHECK: wfmdb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x08 0x3e 0xe7
+
+#CHECK: wfmsdb  %f0, %f0, %f0, %f0
+0xe7 0x00 0x03 0x08 0x00 0x8e
+
+#CHECK: wfmsdb  %f3, %v20, %f5, %v22
+0xe7 0x34 0x53 0x08 0x65 0x8e
+
+#CHECK: wfmsdb  %v31, %v31, %v31, %v31
+0xe7 0xff 0xf3 0x08 0xff 0x8e
+
+#CHECK: wfsdb   %f0, %f0, %f0
+0xe7 0x00 0x00 0x08 0x30 0xe2
+
+#CHECK: wfsdb   %v18, %f3, %v20
+0xe7 0x23 0x40 0x08 0x3a 0xe2
+
+#CHECK: wfsdb   %v31, %v31, %v31
+0xe7 0xff 0xf0 0x08 0x3e 0xe2
+
+#CHECK: wfsqdb  %f0, %f0
+0xe7 0x00 0x00 0x08 0x30 0xce
+
+#CHECK: wfsqdb  %v19, %f14
+0xe7 0x3e 0x00 0x08 0x38 0xce
+
+#CHECK: wfsqdb  %v31, %v31
+0xe7 0xff 0x00 0x08 0x3c 0xce
+
+#CHECK: wftcidb %f0, %f0, 0
+0xe7 0x00 0x00 0x08 0x30 0x4a
+
+#CHECK: wftcidb %v19, %f4, 1383
+0xe7 0x34 0x56 0x78 0x38 0x4a
+
+#CHECK: wftcidb %v31, %v31, 4095
+0xe7 0xff 0xff 0xf8 0x3c 0x4a
+
+#CHECK: wldeb   %f0, %f0
+0xe7 0x00 0x00 0x08 0x20 0xc4
+
+#CHECK: wldeb   %v19, %f14
+0xe7 0x3e 0x00 0x08 0x28 0xc4
+
+#CHECK: wldeb   %v31, %v31
+0xe7 0xff 0x00 0x08 0x2c 0xc4
+
+#CHECK: wledb   %f0, %f0, 0, 0
+0xe7 0x00 0x00 0x08 0x30 0xc5
+
+#CHECK: wledb   %v19, %f14, 4, 10
+0xe7 0x3e 0x00 0xac 0x38 0xc5
+
+#CHECK: wledb   %v31, %v31, 7, 15
+0xe7 0xff 0x00 0xff 0x3c 0xc5
diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt
index 54a3c5b1d6a1..9d3f2b08743a 100644
--- a/test/MC/Disassembler/SystemZ/insns.txt
+++ b/test/MC/Disassembler/SystemZ/insns.txt
@@ -2503,6 +2503,15 @@
 # CHECK: ear %r15, %a15
 0xb2 0x4f 0x00 0xff
 
+# CHECK: etnd %r0
+0xb2 0xec 0x00 0x00
+
+# CHECK: etnd %r15
+0xb2 0xec 0x00 0xf0
+
+# CHECK: etnd %r7
+0xb2 0xec 0x00 0x70
+
 # CHECK: fidbr %f0, 0, %f0
 0xb3 0x5f 0x00 0x00
 
@@ -6034,6 +6043,36 @@
 # CHECK: ny %r15, 0
 0xe3 0xf0 0x00 0x00 0x00 0x54
 
+# CHECK: ntstg %r0, -524288
+0xe3 0x00 0x00 0x00 0x80 0x25
+
+# CHECK: ntstg %r0, -1
+0xe3 0x00 0x0f 0xff 0xff 0x25
+
+# CHECK: ntstg %r0, 0
+0xe3 0x00 0x00 0x00 0x00 0x25
+
+# CHECK: ntstg %r0, 1
+0xe3 0x00 0x00 0x01 0x00 0x25
+
+# CHECK: ntstg %r0, 524287
+0xe3 0x00 0x0f 0xff 0x7f 0x25
+
+# CHECK: ntstg %r0, 0(%r1)
+0xe3 0x00 0x10 0x00 0x00 0x25
+
+# CHECK: ntstg %r0, 0(%r15)
+0xe3 0x00 0xf0 0x00 0x00 0x25
+
+# CHECK: ntstg %r0, 524287(%r1,%r15)
+0xe3 0x01 0xff 0xff 0x7f 0x25
+
+# CHECK: ntstg %r0, 524287(%r15,%r1)
+0xe3 0x0f 0x1f 0xff 0x7f 0x25
+
+# CHECK: ntstg %r15, 0
+0xe3 0xf0 0x00 0x00 0x00 0x25
+
 # CHECK: oc 0(1), 0
 0xd6 0x00 0x00 0x00 0x00 0x00
 
@@ -6334,6 +6373,33 @@
 # CHECK: pfd 15, 0
 0xe3 0xf0 0x00 0x00 0x00 0x36
 
+# CHECK: popcnt %r0, %r0
+0xb9 0xe1 0x00 0x00
+
+# CHECK: popcnt %r0, %r15
+0xb9 0xe1 0x00 0x0f
+
+# CHECK: popcnt %r15, %r0
+0xb9 0xe1 0x00 0xf0
+
+# CHECK: popcnt %r7, %r8
+0xb9 0xe1 0x00 0x78
+
+# CHECK: ppa %r0, %r0, 0
+0xb2 0xe8 0x00 0x00
+
+# CHECK: ppa %r0, %r0, 15
+0xb2 0xe8 0xf0 0x00
+
+# CHECK: ppa %r0, %r15, 0
+0xb2 0xe8 0x00 0x0f
+
+# CHECK: ppa %r4, %r6, 7
+0xb2 0xe8 0x70 0x46
+
+# CHECK: ppa %r15, %r0, 0
+0xb2 0xe8 0x00 0xf0
+
 # CHECK: risbg %r0, %r0, 0, 0, 0
 0xec 0x00 0x00 0x00 0x00 0x55
 
@@ -6355,6 +6421,27 @@
 # CHECK: risbg %r4, %r5, 6, 7, 8
 0xec 0x45 0x06 0x07 0x08 0x55
 
+# CHECK: risbgn %r0, %r0, 0, 0, 0
+0xec 0x00 0x00 0x00 0x00 0x59
+
+# CHECK: risbgn %r0, %r0, 0, 0, 63
+0xec 0x00 0x00 0x00 0x3f 0x59
+
+# CHECK: risbgn %r0, %r0, 0, 255, 0
+0xec 0x00 0x00 0xff 0x00 0x59
+
+# CHECK: risbgn %r0, %r0, 255, 0, 0
+0xec 0x00 0xff 0x00 0x00 0x59
+
+# CHECK: risbgn %r0, %r15, 0, 0, 0
+0xec 0x0f 0x00 0x00 0x00 0x59
+
+# CHECK: risbgn %r15, %r0, 0, 0, 0
+0xec 0xf0 0x00 0x00 0x00 0x59
+
+# CHECK: risbgn %r4, %r5, 6, 7, 8
+0xec 0x45 0x06 0x07 0x08 0x59
+
 # CHECK: risbhg %r0, %r0, 0, 0, 0
 0xec 0x00 0x00 0x00 0x00 0x5d
 
@@ -8029,6 +8116,93 @@
 # CHECK: sy %r15, 0
 0xe3 0xf0 0x00 0x00 0x00 0x5b
 
+# CHECK: tabort 0
+0xb2 0xfc 0x00 0x00
+
+# CHECK: tabort 0(%r1)
+0xb2 0xfc 0x10 0x00
+
+# CHECK: tabort 0(%r15)
+0xb2 0xfc 0xf0 0x00
+
+# CHECK: tabort 4095
+0xb2 0xfc 0x0f 0xff
+
+# CHECK: tabort 4095(%r1)
+0xb2 0xfc 0x1f 0xff
+
+# CHECK: tabort 4095(%r15)
+0xb2 0xfc 0xff 0xff
+
+# CHECK: tbegin 0, 0
+0xe5 0x60 0x00 0x00 0x00 0x00
+
+# CHECK: tbegin 4095, 0
+0xe5 0x60 0x0f 0xff 0x00 0x00
+
+# CHECK: tbegin 0, 0
+0xe5 0x60 0x00 0x00 0x00 0x00
+
+# CHECK: tbegin 0, 1
+0xe5 0x60 0x00 0x00 0x00 0x01
+
+# CHECK: tbegin 0, 32767
+0xe5 0x60 0x00 0x00 0x7f 0xff
+
+# CHECK: tbegin 0, 32768
+0xe5 0x60 0x00 0x00 0x80 0x00
+
+# CHECK: tbegin 0, 65535
+0xe5 0x60 0x00 0x00 0xff 0xff
+
+# CHECK: tbegin 0(%r1), 42
+0xe5 0x60 0x10 0x00 0x00 0x2a
+
+# CHECK: tbegin 0(%r15), 42
+0xe5 0x60 0xf0 0x00 0x00 0x2a
+
+# CHECK: tbegin 4095(%r1), 42
+0xe5 0x60 0x1f 0xff 0x00 0x2a
+
+# CHECK: tbegin 4095(%r15), 42
+0xe5 0x60 0xff 0xff 0x00 0x2a
+
+# CHECK: tbeginc 0, 0
+0xe5 0x61 0x00 0x00 0x00 0x00
+
+# CHECK: tbeginc 4095, 0
+0xe5 0x61 0x0f 0xff 0x00 0x00
+
+# CHECK: tbeginc 0, 0
+0xe5 0x61 0x00 0x00 0x00 0x00
+
+# CHECK: tbeginc 0, 1
+0xe5 0x61 0x00 0x00 0x00 0x01
+
+# CHECK: tbeginc 0, 32767
+0xe5 0x61 0x00 0x00 0x7f 0xff
+
+# CHECK: tbeginc 0, 32768
+0xe5 0x61 0x00 0x00 0x80 0x00
+
+# CHECK: tbeginc 0, 65535
+0xe5 0x61 0x00 0x00 0xff 0xff
+
+# CHECK: tbeginc 0(%r1), 42
+0xe5 0x61 0x10 0x00 0x00 0x2a
+
+# CHECK: tbeginc 0(%r15), 42
+0xe5 0x61 0xf0 0x00 0x00 0x2a
+
+# CHECK: tbeginc 4095(%r1), 42
+0xe5 0x61 0x1f 0xff 0x00 0x2a
+
+# CHECK: tbeginc 4095(%r15), 42
+0xe5 0x61 0xff 0xff 0x00 0x2a
+
+# CHECK: tend
+0xb2 0xf8 0x00 0x00
+
 # CHECK: tm 0, 0
 0x91 0x00 0x00 0x00
 
diff --git a/test/MC/Disassembler/X86/avx-512.txt b/test/MC/Disassembler/X86/avx-512.txt
index 62fc35bd1cff..d618e7e59335 100644
--- a/test/MC/Disassembler/X86/avx-512.txt
+++ b/test/MC/Disassembler/X86/avx-512.txt
@@ -109,3 +109,33 @@
 
 # CHECK: vaddss 1024(%rdx), %xmm0, %xmm16
 0x62 0xe1 0x7e 0x08 0x58 0x82 0x00 0x04 0x00 0x00
+
+# CHECK: vpcmpeqd %zmm10, %zmm25, %k5
+0x62 0xd3 0x35 0x40 0x1f 0xea 0x0
+
+# CHECK: vpcmpltd %zmm10, %zmm25, %k5
+0x62 0xd3 0x35 0x40 0x1f 0xea 0x1
+
+# CHECK: vpcmpled %zmm10, %zmm25, %k5
+0x62 0xd3 0x35 0x40 0x1f 0xea 0x2
+
+# CHECK: vpcmpd $3, %zmm10, %zmm25, %k5
+0x62 0xd3 0x35 0x40 0x1f 0xea 0x3
+
+# CHECK: vpcmpneqd %zmm10, %zmm25, %k5
+0x62 0xd3 0x35 0x40 0x1f 0xea 0x4
+
+# CHECK: vpcmpnltd %zmm10, %zmm25, %k5
+0x62 0xd3 0x35 0x40 0x1f 0xea 0x5
+
+# CHECK: vpcmpnled %zmm10, %zmm25, %k5
+0x62 0xd3 0x35 0x40 0x1f 0xea 0x6
+
+# CHECK: vpcmpd $7, %zmm10, %zmm25, %k5
+0x62 0xd3 0x35 0x40 0x1f 0xea 0x7
+
+# CHECK: vpcmpd $8, %zmm10, %zmm25, %k5
+0x62 0xd3 0x35 0x40 0x1f 0xea 0x8
+
+# CHECK: vcmppd	$127,{sae}, %zmm27, %zmm11, %k4
+0x62 0x91 0xa5 0x58 0xc2 0xe3 0x7f
diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt
index 8fab6c9febcb..875c5b711a90 100644
--- a/test/MC/Disassembler/X86/simple-tests.txt
+++ b/test/MC/Disassembler/X86/simple-tests.txt
@@ -911,6 +911,12 @@
 # CHECK: vpcmov %ymm1, (%rax), %ymm3, %ymm4
 0x8f 0xe8 0x64 0xa2 0x20 0x10
 
+# CHECK: vpcomeqb  %xmm6, %xmm4, %xmm2
+0x8f 0xe8 0x58 0xcc 0xd6 0x04
+
+# CHECK: vpcomneqb 8(%rax), %xmm3, %xmm2
+0x8f 0xe8 0x60 0xcc 0x50 0x08 0x05
+
 # CHECK: vpcomb $55, %xmm6, %xmm4, %xmm2
 0x8f 0xe8 0x58 0xcc 0xd6 0x37
 
diff --git a/test/MC/Disassembler/X86/x86-16.txt b/test/MC/Disassembler/X86/x86-16.txt
index 93974d433e3d..c6844cd3cef4 100644
--- a/test/MC/Disassembler/X86/x86-16.txt
+++ b/test/MC/Disassembler/X86/x86-16.txt
@@ -30,7 +30,7 @@
 # CHECK: movl %eax, -16(%ebp)
 0x67 0x66 0x89 0x45 0xf0
 
-# CHECK: testb %bl, %cl
+# CHECK: testb %cl, %bl
 0x84 0xcb
 
 # CHECK: cmpl %eax, %ebx
diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt
index 35c8cce9cbd7..830b83066302 100644
--- a/test/MC/Disassembler/X86/x86-32.txt
+++ b/test/MC/Disassembler/X86/x86-32.txt
@@ -490,6 +490,27 @@
 # CHECK: xsaveopt (%eax)
 0x0f 0xae 0x30
 
+# CHECK: xsaves (%eax)
+0x0f 0xc7 0x28
+
+# CHECK: xrstors (%eax)
+0x0f 0xc7 0x18
+
+# CHECK: xsavec (%eax)
+0x0f 0xc7 0x20
+
+# CHECK: clflush (%eax)
+0x0f 0xae 0x38
+
+# CHECK: clflushopt (%eax)
+0x66 0x0f 0xae 0x38
+
+# CHECK: clwb (%eax)
+0x66 0x0f 0xae 0x30
+
+# CHECK: pcommit
+0x66 0x0f 0xae 0xf8
+
 # CHECK: vcvtph2ps %xmm0, %xmm0
 0xc4 0xe2 0x79 0x13 0xc0
 
@@ -712,7 +733,7 @@
 # CHECK: movq %mm0, %mm1
 0x0f 0x7f 0xc1
 
-# CHECK: vpermq $-18, %ymm2, %ymm2
+# CHECK: vpermq $238, %ymm2, %ymm2
 0xc4 0xe3 0xfd 0x00 0xd2 0xee
 
 # CHECK: cmpps $8, %xmm7, %xmm0
@@ -740,3 +761,6 @@
 0x82 0x35 0x38 0x87 0x50 0x00 0x26
 # CHECK: cmpb $38, 5277496
 0x82 0x3d 0x38 0x87 0x50 0x00 0x26
+
+#CHECK: getsec
+0x0f 0x37
diff --git a/test/MC/Disassembler/X86/x86-64.txt b/test/MC/Disassembler/X86/x86-64.txt
index e67a4f9383e0..5699f40d2d33 100644
--- a/test/MC/Disassembler/X86/x86-64.txt
+++ b/test/MC/Disassembler/X86/x86-64.txt
@@ -116,13 +116,13 @@
 # CHECK: xabort $13
 0xc6 0xf8 0x0d
 
-# CHECK: xsaveq (%rax)
+# CHECK: xsave64 (%rax)
 0x48 0x0f 0xae 0x20
 
-# CHECK: xrstorq (%rax)
+# CHECK: xrstor64 (%rax)
 0x48 0x0f 0xae 0x28
 
-# CHECK: xsaveoptq (%rax)
+# CHECK: xsaveopt64 (%rax)
 0x48 0x0f 0xae 0x30
 
 # CHECK: clac
@@ -236,6 +236,27 @@
 # CHECK: vmovq %xmm0, %rax
 0xc4 0xe1 0xf9 0x7e 0xc0
 
+# CHECK: movd (%rax), %mm0
+0x48 0x0f 0x6e 0x00
+
+# CHECK: movd %rax, %mm0
+0x48 0x0f 0x6e 0xc0
+
+# CHECK: movd %mm0, (%rax)
+0x48 0x0f 0x7e 0x00
+
+# CHECK: movd %mm0, %rax
+0x48 0x0f 0x7e 0xc0
+
+# CHECK: movd (%rax), %xmm0
+0x66 0x48 0x0f 0x6e 0x00
+
+# CHECK: movd %rax, %xmm0
+0x66 0x48 0x0f 0x6e 0xc0
+
+# CHECK: movd %xmm0, (%rax)
+0x66 0x48 0x0f 0x7e 0x00
+
 # CHECK: movd %xmm0, %rax
 0x66 0x48 0x0f 0x7e 0xc0
 
@@ -280,3 +301,41 @@
 
 # CHECK: movq %rax, 1515870810
 0x67, 0x48 0xa3 0x5a 0x5a 0x5a 0x5a
+
+# CHECK: addq 255(%rip), %rbx
+0x49, 0x03, 0x1d, 0xff, 0x00, 0x00, 0x00
+
+# The following 4 encodings are equivalent, as confirmed by the 'xed64'
+# decoder tool provided by Intel, which we assume to be canonical even
+# if the real silicon does something different. If that should happen,
+# then we'll all have disassembler bugs to repair.
+
+# Try all combinations of EVEX.x and REX.b:
+# CHECK: vaddps	287453952(%rip), %zmm20, %zmm15
+0x62 0x11 0x5c 0x40 0x58 0x3d 0x00 0x33 0x22 0x11
+# CHECK: vaddps	287453952(%rip), %zmm20, %zmm15
+0x62 0x31 0x5c 0x40 0x58 0x3d 0x00 0x33 0x22 0x11
+# CHECK: vaddps	287453952(%rip), %zmm20, %zmm15
+0x62 0x51 0x5c 0x40 0x58 0x3d 0x00 0x33 0x22 0x11
+# CHECK: vaddps	287453952(%rip), %zmm20, %zmm15
+0x62 0x71 0x5c 0x40 0x58 0x3d 0x00 0x33 0x22 0x11
+
+# Known bugs: these use a SIB byte. The index register is incorrectly
+# printed as an xmm register. Indeed there are "gather" load instructions
+# taking a vector of indices, but ONLY those instructions can do that.
+# The CHECK lines test the current incorrect output; FIXME is desired.
+# CHECK: vaddps (%r10,%xmm9), %zmm20, %zmm15
+# FIXME: vaddps (%r10,%r9), %zmm20, %zmm15
+0x62 0x11 0x5c 0x40 0x58 0x3c 0x0a
+
+# CHECK: vaddps (%rdx,%xmm9), %zmm20, %zmm15
+# FIXME: vaddps (%rdx,%r9), %zmm20, %zmm15
+0x62 0x31 0x5c 0x40 0x58 0x3c 0x0a
+
+# CHECK: vaddps (%r10,%xmm1), %zmm20, %zmm15
+# FIXME: vaddps (%r10,%rcx), %zmm20, %zmm15
+0x62 0x51 0x5c 0x40 0x58 0x3c 0x0a
+
+# CHECK: vaddps (%rdx,%xmm1), %zmm20, %zmm15
+# FIXME: vaddps (%rdx,%rcx), %zmm20, %zmm15
+0x62 0x71 0x5c 0x40 0x58 0x3c 0x0a
diff --git a/test/MC/ELF/alias-to-local.s b/test/MC/ELF/alias-to-local.s
new file mode 100644
index 000000000000..4983833b33af
--- /dev/null
+++ b/test/MC/ELF/alias-to-local.s
@@ -0,0 +1,18 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu < %s | llvm-readobj -r | FileCheck %s
+
+// CHECK:      Relocations [
+// CHECK-NEXT:   Section {{.*}} .rela.text {
+// CHECK-NEXT:     0x1 R_X86_64_32 zed 0x0
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
+
+foo:
+	movl	$zed, %eax
+
+
+	.section	.data.bar,"aGw",@progbits,zed,comdat
+bar:
+	.byte	42
+
+	.globl	zed
+zed = bar
diff --git a/test/MC/ELF/alias.s b/test/MC/ELF/alias.s
index 8e1318230bb8..0ab6dd4b5b8e 100644
--- a/test/MC/ELF/alias.s
+++ b/test/MC/ELF/alias.s
@@ -24,6 +24,15 @@ bar5 = bar4
 bar6 = bar5
 bar6:
 
+// Test that indirect local aliases do not appear as symbols.
+.data
+.Llocal:
+
+.text
+leaq .Llocal1(%rip), %rdi
+.Llocal1 = .Llocal2
+.Llocal2 = .Llocal
+
 // CHECK:      Symbols [
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name:  (0)
@@ -99,12 +108,15 @@ bar6:
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: .text (0)
+// CHECK-NOT: Symbol {
 // CHECK:        }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: .data (0)
+// CHECK-NOT: Symbol {
 // CHECK:        }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: .bss (0)
+// CHECK-NOT: Symbol {
 // CHECK:        }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: bar3
diff --git a/test/MC/ELF/align.s b/test/MC/ELF/align.s
index 46be3df62f2d..43f5b548d9ee 100644
--- a/test/MC/ELF/align.s
+++ b/test/MC/ELF/align.s
@@ -23,7 +23,7 @@
 // CHECK-NEXT:     EntrySize: 0
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section {
-// CHECK-NEXT:     Index: 4
+// CHECK-NEXT:     Index:
 // CHECK-NEXT:     Name: .rodata
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
diff --git a/test/MC/ELF/basic-elf-32.s b/test/MC/ELF/basic-elf-32.s
index e12fc526369e..16266af7f445 100644
--- a/test/MC/ELF/basic-elf-32.s
+++ b/test/MC/ELF/basic-elf-32.s
@@ -45,7 +45,7 @@ main:                                   # @main
 // CHECK:     Name: .rel.text
 
 // CHECK: Relocations [
-// CHECK:   Section (2) .rel.text {
+// CHECK:   Section {{.*}} .rel.text {
 // CHECK:     0x6  R_386_32   .L.str1
 // CHECK:     0xB  R_386_PC32 puts
 // CHECK:     0x12 R_386_32   .L.str2
diff --git a/test/MC/ELF/basic-elf-64.s b/test/MC/ELF/basic-elf-64.s
index a77f3e63e093..d99125e06a91 100644
--- a/test/MC/ELF/basic-elf-64.s
+++ b/test/MC/ELF/basic-elf-64.s
@@ -45,7 +45,7 @@ main:                                   # @main
 // CHECK:     Name: .rela.text
 
 // CHECK: Relocations [
-// CHECK:   Section (2) .rela.text {
+// CHECK:   Section {{.*}} .rela.text {
 // CHECK:     0x5  R_X86_64_32   .rodata.str1.1 0x0
 // CHECK:     0xA  R_X86_64_PC32 puts           0xFFFFFFFFFFFFFFFC
 // CHECK:     0xF  R_X86_64_32   .rodata.str1.1 0x6
diff --git a/test/MC/ELF/bracket-exprs.s b/test/MC/ELF/bracket-exprs.s
index 96f9f9aa450a..e7299fde7009 100644
--- a/test/MC/ELF/bracket-exprs.s
+++ b/test/MC/ELF/bracket-exprs.s
@@ -1,7 +1,7 @@
 // RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s
 
 // CHECK: .byte 1
-.if [~0 >> 1] == -1
+.if [~0 >> 63] == 1
 .byte 1
 .else
 .byte 2
diff --git a/test/MC/ELF/cfi-adjust-cfa-offset.s b/test/MC/ELF/cfi-adjust-cfa-offset.s
index 9d639f70d8dd..398ad54fe75b 100644
--- a/test/MC/ELF/cfi-adjust-cfa-offset.s
+++ b/test/MC/ELF/cfi-adjust-cfa-offset.s
@@ -11,16 +11,26 @@ f:
 	ret
 	.cfi_endproc
 
+        .cfi_startproc
+	nop
+	.cfi_adjust_cfa_offset 4
+	.cfi_endproc
+
+        .cfi_startproc
+	nop
+	.cfi_adjust_cfa_offset 4
+	.cfi_endproc
+
 // CHECK:        Section {
-// CHECK:          Index: 4
-// CHECK-NEXT:     Name: .eh_frame
+// CHECK:          Index:
+// CHECK:          Name: .eh_frame
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
 // CHECK-NEXT:     Offset: 0x50
-// CHECK-NEXT:     Size: 56
+// CHECK-NEXT:     Size: 96
 // CHECK-NEXT:     Link: 0
 // CHECK-NEXT:     Info: 0
 // CHECK-NEXT:     AddressAlignment: 8
@@ -28,26 +38,30 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
-// CHECK-NEXT:       0010: 1B0C0708 90010000 1C000000 1C000000
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
+// CHECK-NEXT:       0010: 1B0C0708 90010000 18000000 1C000000
 // CHECK-NEXT:       0020: 00000000 0A000000 00440E10 410E1444
-// CHECK-NEXT:       0030: 0E080000 00000000
+// CHECK-NEXT:       0030: 0E080000 10000000 38000000 00000000
+// CHECK-NEXT:       0040: 01000000 00410E0C 14000000 4C000000
+// CHECK-NEXT:       0050: 00000000 01000000 00410E0C 00000000
 // CHECK-NEXT:     )
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section {
-// CHECK-NEXT:     Index: 5
+// CHECK-NEXT:     Index:
 // CHECK-NEXT:     Name: .rela.eh_frame
 // CHECK-NEXT:     Type: SHT_RELA
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x3A0
-// CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Offset:
+// CHECK-NEXT:     Size: 72
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:       0x20 R_X86_64_PC32 .text 0x0
+// CHECK-NEXT:       0x3C R_X86_64_PC32 .text 0x
+// CHECK-NEXT:       0x50 R_X86_64_PC32 .text 0x
 // CHECK-NEXT:     ]
 // CHECK:        }
diff --git a/test/MC/ELF/cfi-advance-loc2.s b/test/MC/ELF/cfi-advance-loc2.s
index 98caa0185f59..133979201273 100644
--- a/test/MC/ELF/cfi-advance-loc2.s
+++ b/test/MC/ELF/cfi-advance-loc2.s
@@ -26,7 +26,7 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
 // CHECK-NEXT:       0010: 1B0C0708 90010000 14000000 1C000000
 // CHECK-NEXT:       0020: 00000000 01010000 00030001 0E080000
 // CHECK-NEXT:     )
@@ -38,10 +38,10 @@ f:
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x490
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/cfi-def-cfa-offset.s b/test/MC/ELF/cfi-def-cfa-offset.s
index 59f740055d47..3e4ca57a5161 100644
--- a/test/MC/ELF/cfi-def-cfa-offset.s
+++ b/test/MC/ELF/cfi-def-cfa-offset.s
@@ -11,8 +11,8 @@ f:
 	.cfi_endproc
 
 // CHECK:        Section {
-// CHECK:          Index: 4
-// CHECK-NEXT:     Name: .eh_frame
+// CHECK:          Index:
+// CHECK:          Name: .eh_frame
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
@@ -27,23 +27,23 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
 // CHECK-NEXT:       0010: 1B0C0708 90010000 14000000 1C000000
 // CHECK-NEXT:       0020: 00000000 0A000000 00440E10 450E0800
 // CHECK-NEXT:     )
 // CHECK-NEXT:   }
 
 // CHECK:        Section {
-// CHECK:          Index: 5
-// CHECK-NEXT:     Name: .rela.eh_frame
+// CHECK:          Index:
+// CHECK:          Name: .rela.eh_frame
 // CHECK-NEXT:     Type: SHT_RELA
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x398
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/cfi-def-cfa-register.s b/test/MC/ELF/cfi-def-cfa-register.s
index 178ba32882dc..53174cb2f552 100644
--- a/test/MC/ELF/cfi-def-cfa-register.s
+++ b/test/MC/ELF/cfi-def-cfa-register.s
@@ -23,7 +23,7 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
 // CHECK-NEXT:       0010: 1B0C0708 90010000 14000000 1C000000
 // CHECK-NEXT:       0020: 00000000 02000000 00410D06 00000000
 // CHECK-NEXT:     )
@@ -35,10 +35,10 @@ f:
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x390
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/cfi-def-cfa.s b/test/MC/ELF/cfi-def-cfa.s
index dfb0d4b59396..9706c4da097b 100644
--- a/test/MC/ELF/cfi-def-cfa.s
+++ b/test/MC/ELF/cfi-def-cfa.s
@@ -23,7 +23,7 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
 // CHECK-NEXT:       0010: 1B0C0708 90010000 14000000 1C000000
 // CHECK-NEXT:       0020: 00000000 02000000 00410C07 08000000
 // CHECK-NEXT:     )
@@ -35,10 +35,10 @@ f:
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x390
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/cfi-escape.s b/test/MC/ELF/cfi-escape.s
index 5394ee414aa7..e93d5f7be5f0 100644
--- a/test/MC/ELF/cfi-escape.s
+++ b/test/MC/ELF/cfi-escape.s
@@ -8,8 +8,8 @@ f:
 	.cfi_endproc
 
 // CHECK:        Section {
-// CHECK:          Index: 4
-// CHECK-NEXT:     Name: .eh_frame
+// CHECK:          Index:
+// CHECK:          Name: .eh_frame
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
@@ -24,22 +24,22 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
 // CHECK-NEXT:       0010: 1B0C0708 90010000 14000000 1C000000
 // CHECK-NEXT:       0020: 00000000 02000000 00411507 7F000000
 // CHECK-NEXT:     )
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section {
-// CHECK-NEXT:     Index: 5
+// CHECK-NEXT:     Index:
 // CHECK-NEXT:     Name: .rela.eh_frame
 // CHECK-NEXT:     Type: SHT_RELA
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x390
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/cfi-large-model.s b/test/MC/ELF/cfi-large-model.s
index 16073ad7f0ee..f4a20c26267c 100644
--- a/test/MC/ELF/cfi-large-model.s
+++ b/test/MC/ELF/cfi-large-model.s
@@ -16,7 +16,7 @@
 // CHECK-NEXT:   AddressAlignment: 8
 // CHECK-NEXT:   EntrySize: 0
 // CHECK-NEXT:   SectionData (
-// CHECK-NEXT:     0000: 14000000 00000000 037A5200 01781001  |.........zR..x..|
+// CHECK-NEXT:     0000: 14000000 00000000 017A5200 01781001  |.........zR..x..|
 // CHECK-NEXT:     0010: 1C0C0708 90010000 1C000000 1C000000  |................|
 // CHECK-NEXT:     0020: 00000000 00000000 00000000 00000000  |................|
 // CHECK-NEXT:     0030: 00000000 00000000                    |........|
diff --git a/test/MC/ELF/cfi-offset.s b/test/MC/ELF/cfi-offset.s
index a65b4fc783c7..9038def03a64 100644
--- a/test/MC/ELF/cfi-offset.s
+++ b/test/MC/ELF/cfi-offset.s
@@ -23,7 +23,7 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
 // CHECK-NEXT:       0010: 1B0C0708 90010000 14000000 1C000000
 // CHECK-NEXT:       0020: 00000000 02000000 00418602 00000000
 // CHECK-NEXT:     )
@@ -35,10 +35,10 @@ f:
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x390
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/cfi-register.s b/test/MC/ELF/cfi-register.s
index 94417702c13c..be60e2ea2e81 100644
--- a/test/MC/ELF/cfi-register.s
+++ b/test/MC/ELF/cfi-register.s
@@ -8,8 +8,8 @@ f:
 	.cfi_endproc
 
 // CHECK:        Section {
-// CHECK:          Index: 4
-// CHECK-NEXT:     Name: .eh_frame
+// CHECK:          Index:
+// CHECK:          Name: .eh_frame
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
@@ -24,22 +24,22 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
 // CHECK-NEXT:       0010: 1B0C0708 90010000 14000000 1C000000
 // CHECK-NEXT:       0020: 00000000 02000000 00410906 00000000
 // CHECK-NEXT:     )
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section {
-// CHECK-NEXT:     Index: 5
+// CHECK-NEXT:     Index:
 // CHECK-NEXT:     Name: .rela.eh_frame
 // CHECK-NEXT:     Type: SHT_RELA
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x390
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/cfi-rel-offset.s b/test/MC/ELF/cfi-rel-offset.s
index 0dc69c89cf4c..892cda165ba6 100644
--- a/test/MC/ELF/cfi-rel-offset.s
+++ b/test/MC/ELF/cfi-rel-offset.s
@@ -15,8 +15,8 @@ f:
 	.cfi_endproc
 
 // CHECK:        Section {
-// CHECK:          Index: 4
-// CHECK-NEXT:     Name: .eh_frame
+// CHECK:          Index:
+// CHECK:          Name: .eh_frame
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
@@ -31,23 +31,23 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
 // CHECK-NEXT:       0010: 1B0C0708 90010000 24000000 1C000000
 // CHECK-NEXT:       0020: 00000000 05000000 00410E08 410D0641
 // CHECK-NEXT:       0030: 11067F41 0E104186 02000000 00000000
 // CHECK-NEXT:     )
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section {
-// CHECK-NEXT:     Index: 5
+// CHECK-NEXT:     Index:
 // CHECK-NEXT:     Name: .rela.eh_frame
 // CHECK-NEXT:     Type: SHT_RELA
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x3A0
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/cfi-rel-offset2.s b/test/MC/ELF/cfi-rel-offset2.s
index 360e7b0ea0f5..805b0b290bc8 100644
--- a/test/MC/ELF/cfi-rel-offset2.s
+++ b/test/MC/ELF/cfi-rel-offset2.s
@@ -7,8 +7,8 @@ f:
 	.cfi_endproc
 
 // CHECK:        Section {
-// CHECK:          Index: 4
-// CHECK-NEXT:     Name: .eh_frame
+// CHECK:          Index:
+// CHECK:          Name: .eh_frame
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
@@ -23,22 +23,22 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
 // CHECK-NEXT:       0010: 1B0C0708 90010000 14000000 1C000000
 // CHECK-NEXT:       0020: 00000000 01000000 00411106 7F000000
 // CHECK-NEXT:     )
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section {
-// CHECK-NEXT:     Index: 5
+// CHECK-NEXT:     Index:
 // CHECK-NEXT:     Name: .rela.eh_frame
 // CHECK-NEXT:     Type: SHT_RELA
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x390
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/cfi-remember.s b/test/MC/ELF/cfi-remember.s
index 3a38948b6a3e..ae112f59ebef 100644
--- a/test/MC/ELF/cfi-remember.s
+++ b/test/MC/ELF/cfi-remember.s
@@ -10,8 +10,8 @@ f:
 	.cfi_endproc
 
 // CHECK:        Section {
-// CHECK:          Index: 4
-// CHECK-NEXT:     Name: .eh_frame
+// CHECK:          Index:
+// CHECK:          Name: .eh_frame
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
@@ -26,22 +26,22 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
 // CHECK-NEXT:       0010: 1B0C0708 90010000 14000000 1C000000
 // CHECK-NEXT:       0020: 00000000 03000000 00410A41 0B000000
 // CHECK-NEXT:     )
 // CHECK-NEXT:   }
 // CHECK:        Section {
-// CHECK:          Index: 5
+// CHECK:          Index:
 // CHECK-NEXT:     Name: .rela.eh_frame
 // CHECK-NEXT:     Type: SHT_RELA
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x390
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/cfi-restore.s b/test/MC/ELF/cfi-restore.s
index e225797f54d6..2bc87cf691a1 100644
--- a/test/MC/ELF/cfi-restore.s
+++ b/test/MC/ELF/cfi-restore.s
@@ -8,8 +8,8 @@ f:
 	.cfi_endproc
 
 // CHECK:        Section {
-// CHECK:          Index: 4
-// CHECK-NEXT:     Name: .eh_frame
+// CHECK:          Index:
+// CHECK:          Name: .eh_frame
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
@@ -24,22 +24,22 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
 // CHECK-NEXT:       0010: 1B0C0708 90010000 14000000 1C000000
 // CHECK-NEXT:       0020: 00000000 02000000 0041C600 00000000
 // CHECK-NEXT:     )
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section {
-// CHECK-NEXT:     Index: 5
+// CHECK-NEXT:     Index:
 // CHECK-NEXT:     Name: .rela.eh_frame
 // CHECK-NEXT:     Type: SHT_RELA
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x390
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/cfi-same-value.s b/test/MC/ELF/cfi-same-value.s
index 2d37f4d0b43e..7df4cbbb6dd1 100644
--- a/test/MC/ELF/cfi-same-value.s
+++ b/test/MC/ELF/cfi-same-value.s
@@ -8,8 +8,8 @@ f:
 	.cfi_endproc
 
 // CHECK:        Section {
-// CHECK:          Index: 4
-// CHECK-NEXT:     Name: .eh_frame
+// CHECK:          Index:
+// CHECK:          Name: .eh_frame
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
@@ -24,22 +24,22 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
 // CHECK-NEXT:       0010: 1B0C0708 90010000 14000000 1C000000
 // CHECK-NEXT:       0020: 00000000 02000000 00410806 00000000
 // CHECK-NEXT:     )
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section {
-// CHECK-NEXT:     Index: 5
+// CHECK-NEXT:     Index:
 // CHECK-NEXT:     Name: .rela.eh_frame
 // CHECK-NEXT:     Type: SHT_RELA
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x390
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/cfi-sections.s b/test/MC/ELF/cfi-sections.s
index b0ba543e5bdb..830fe260ec2c 100644
--- a/test/MC/ELF/cfi-sections.s
+++ b/test/MC/ELF/cfi-sections.s
@@ -1,5 +1,11 @@
-// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck -check-prefix=ELF_64 %s
-// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck -check-prefix=ELF_32 %s
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -dwarf-version 2 %s -o - | llvm-readobj -s -sd | FileCheck -check-prefix=ELF_64 -check-prefix=ELF_64_DWARF_2 %s
+// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -dwarf-version 2 %s -o - | llvm-readobj -s -sd | FileCheck -check-prefix=ELF_32 -check-prefix=ELF_32_DWARF_2 %s
+
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -dwarf-version 3 %s -o - | llvm-readobj -s -sd | FileCheck -check-prefix=ELF_64 -check-prefix=ELF_64_DWARF_3 %s
+// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -dwarf-version 3 %s -o - | llvm-readobj -s -sd | FileCheck -check-prefix=ELF_32 -check-prefix=ELF_32_DWARF_3 %s
+
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -dwarf-version 4 %s -o - | llvm-readobj -s -sd | FileCheck -check-prefix=ELF_64 -check-prefix=ELF_64_DWARF_4 %s
+// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -dwarf-version 4 %s -o - | llvm-readobj -s -sd | FileCheck -check-prefix=ELF_32 -check-prefix=ELF_32_DWARF_4 %s
 
 .cfi_sections .debug_frame
 
@@ -26,8 +32,12 @@ f2:
 // ELF_64-NEXT:     AddressAlignment: 8
 // ELF_64-NEXT:     EntrySize: 0
 // ELF_64-NEXT:     SectionData (
-// ELF_64-NEXT:       0000: 14000000 FFFFFFFF 03000178 100C0708
-// ELF_64-NEXT:       0010: 90010000 00000000 14000000 00000000
+// ELF_64_DWARF_2-NEXT:       0000: 14000000 FFFFFFFF 01000178 100C0708
+// ELF_64_DWARF_2-NEXT:       0010: 90010000 00000000 14000000 00000000
+// ELF_64_DWARF_3-NEXT:       0000: 14000000 FFFFFFFF 03000178 100C0708
+// ELF_64_DWARF_3-NEXT:       0010: 90010000 00000000 14000000 00000000
+// ELF_64_DWARF_4-NEXT:       0000: 14000000 FFFFFFFF 04000800 0178100C
+// ELF_64_DWARF_4-NEXT:       0010: 07089001 00000000 14000000 00000000
 // ELF_64-NEXT:       0020: 00000000 00000000 01000000 00000000
 // ELF_64-NEXT:       0030: 14000000 00000000 00000000 00000000
 // ELF_64-NEXT:       0040: 01000000 00000000
@@ -47,9 +57,14 @@ f2:
 // ELF_32-NEXT:     AddressAlignment: 4
 // ELF_32-NEXT:     EntrySize: 0
 // ELF_32-NEXT:     SectionData (
-// ELF_32-NEXT:       0000: 10000000 FFFFFFFF 0300017C 080C0404
-// ELF_32-NEXT:       0010: 88010000 0C000000 00000000 00000000
+// ELF_32_DWARF_2-NEXT:       0000: 10000000 FFFFFFFF 0100017C 080C0404
+// ELF_32_DWARF_2-NEXT:       0010: 88010000 0C000000 00000000 00000000
+// ELF_32_DWARF_3-NEXT:       0000: 10000000 FFFFFFFF 0300017C 080C0404
+// ELF_32_DWARF_3-NEXT:       0010: 88010000 0C000000 00000000 00000000
+// ELF_32_DWARF_4-NEXT:       0000: 10000000 FFFFFFFF 04000400 017C080C
+// ELF_32_DWARF_4-NEXT:       0010: 04048801 0C000000 00000000 00000000
 // ELF_32-NEXT:       0020: 01000000 0C000000 00000000 01000000
 // ELF_32-NEXT:       0030: 01000000
+
 // ELF_32-NEXT:     )
 // ELF_32-NEXT:   }
diff --git a/test/MC/ELF/cfi-signal-frame.s b/test/MC/ELF/cfi-signal-frame.s
index 98deb0a1de5c..023311962189 100644
--- a/test/MC/ELF/cfi-signal-frame.s
+++ b/test/MC/ELF/cfi-signal-frame.s
@@ -23,10 +23,10 @@ g:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 0
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5253 00017810
+// CHECK-NEXT:       0000: 14000000 00000000 017A5253 00017810
 // CHECK-NEXT:       0010: 011B0C07 08900100 10000000 1C000000
 // CHECK-NEXT:       0020: 00000000 00000000 00000000 14000000
-// CHECK-NEXT:       0030: 00000000 037A5200 01781001 1B0C0708
+// CHECK-NEXT:       0030: 00000000 017A5200 01781001 1B0C0708
 // CHECK-NEXT:       0040: 90010000 10000000 1C000000 00000000
 // CHECK-NEXT:       0050: 00000000 00000000
 // CHECK-NEXT:     )
diff --git a/test/MC/ELF/cfi-undefined.s b/test/MC/ELF/cfi-undefined.s
index 568b3159cc44..9a7012310ade 100644
--- a/test/MC/ELF/cfi-undefined.s
+++ b/test/MC/ELF/cfi-undefined.s
@@ -8,8 +8,8 @@ f:
 	.cfi_endproc
 
 // CHECK:        Section {
-// CHECK:          Index: 4
-// CHECK-NEXT:     Name: .eh_frame
+// CHECK:          Index:
+// CHECK:          Name: .eh_frame
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
@@ -24,22 +24,22 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
 // CHECK-NEXT:       0010: 1B0C0708 90010000 14000000 1C000000
 // CHECK-NEXT:       0020: 00000000 02000000 00410706 00000000
 // CHECK-NEXT:     )
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section {
-// CHECK-NEXT:     Index: 5
+// CHECK-NEXT:     Index:
 // CHECK-NEXT:     Name: .rela.eh_frame
 // CHECK-NEXT:     Type: SHT_RELA
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x390
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/cfi-version.ll b/test/MC/ELF/cfi-version.ll
index c8a9978d7292..9ea7be4a42b5 100644
--- a/test/MC/ELF/cfi-version.ll
+++ b/test/MC/ELF/cfi-version.ll
@@ -1,6 +1,6 @@
 ; RUN: %llc_dwarf %s -o - -dwarf-version 2 -filetype=obj | llvm-dwarfdump - | FileCheck %s --check-prefix=DWARF2
-; RUN: %llc_dwarf %s -o - -dwarf-version 3 -filetype=obj | llvm-dwarfdump - | FileCheck %s --check-prefix=DWARF34
-; RUN: %llc_dwarf %s -o - -dwarf-version 4 -filetype=obj | llvm-dwarfdump - | FileCheck %s --check-prefix=DWARF34
+; RUN: %llc_dwarf %s -o - -dwarf-version 3 -filetype=obj | llvm-dwarfdump - | FileCheck %s --check-prefix=DWARF3
+; RUN: %llc_dwarf %s -o - -dwarf-version 4 -filetype=obj | llvm-dwarfdump - | FileCheck %s --check-prefix=DWARF4
 
 ; .debug_frame is not emitted for targeting Windows x64.
 ; REQUIRES: debug_frame
@@ -22,24 +22,34 @@ attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n
 !llvm.module.flags = !{!9, !10}
 !llvm.ident = !{!11}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/test.c] [DW_LANG_C99]
-!1 = !{!"test.c", !"/tmp"}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.c", directory: "/tmp")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\002\000\001\000\006\00256\000\002", !1, !5, !6, null, i32 ()* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp/test.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !6, function: i32 ()* @foo, variables: !2)
+!5 = !DIFile(filename: "test.c", directory: "/tmp")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{i32 2, !"Dwarf Version", i32 4}
-!10 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !{i32 1, !"Debug Info Version", i32 3}
 !11 = !{!"clang version 3.5.0 "}
-!12 = !MDLocation(line: 2, scope: !4)
+!12 = !DILocation(line: 2, scope: !4)
 
 ; DWARF2:      .debug_frame contents:
 ; DWARF2:        Version:               1
 ; DWARF2-NEXT:   Augmentation:
-
-; DWARF34:      .debug_frame contents:
-; DWARF34:        Version:               3
-; DWARF34-NEXT:   Augmentation:
+; DWARF2-NOT:    Address size:
+; DWARF2-NOT:    Segment desc size:
+
+; DWARF3:      .debug_frame contents:
+; DWARF3:        Version:               3
+; DWARF3-NEXT:   Augmentation:
+; DWARF3-NOT:    Address size:
+; DWARF3-NOT:    Segment desc size:
+
+; DWARF4:      .debug_frame contents:
+; DWARF4:        Version:               4
+; DWARF4-NEXT:   Augmentation:
+; DWARF4:        Address size:
+; DWARF4:        Segment desc size:
diff --git a/test/MC/ELF/cfi-window-save.s b/test/MC/ELF/cfi-window-save.s
index b083901c137a..fb38ecd85608 100644
--- a/test/MC/ELF/cfi-window-save.s
+++ b/test/MC/ELF/cfi-window-save.s
@@ -26,7 +26,7 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
 // CHECK-NEXT:       0010: 1B0C0708 90010000 14000000 1C000000
 // CHECK-NEXT:       0020: 00000000 02000000 00412D00 00000000
 // CHECK-NEXT:     )
@@ -38,10 +38,10 @@ f:
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x390
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/cfi-zero-addr-delta.s b/test/MC/ELF/cfi-zero-addr-delta.s
index 8662839b5274..1e5c5e7e5680 100644
--- a/test/MC/ELF/cfi-zero-addr-delta.s
+++ b/test/MC/ELF/cfi-zero-addr-delta.s
@@ -30,7 +30,7 @@ f:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A5200 01781001
+// CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
 // CHECK-NEXT:       0010: 1B0C0708 90010000 1C000000 1C000000
 // CHECK-NEXT:       0020: 00000000 04000000 00410E10 410A0E08
 // CHECK-NEXT:       0030: 410B0000 00000000
@@ -43,10 +43,10 @@ f:
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x398
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/cfi.s b/test/MC/ELF/cfi.s
index 21be615c5f39..10587e030521 100644
--- a/test/MC/ELF/cfi.s
+++ b/test/MC/ELF/cfi.s
@@ -218,8 +218,8 @@ f37:
         .cfi_endproc
 
 // CHECK:        Section {
-// CHECK:          Index: 4
-// CHECK-NEXT:     Name: .eh_frame
+// CHECK:          Index:
+// CHECK:          Name: .eh_frame
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
@@ -234,131 +234,131 @@ f37:
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: 14000000 00000000 037A4C52 00017810
+// CHECK-NEXT:       0000: 14000000 00000000 017A4C52 00017810
 // CHECK-NEXT:       0010: 02031B0C 07089001 14000000 1C000000
 // CHECK-NEXT:       0020: 00000000 01000000 04000000 00000000
-// CHECK-NEXT:       0030: 20000000 00000000 037A504C 52000178
+// CHECK-NEXT:       0030: 20000000 00000000 017A504C 52000178
 // CHECK-NEXT:       0040: 100B0000 00000000 00000003 1B0C0708
 // CHECK-NEXT:       0050: 90010000 14000000 28000000 00000000
 // CHECK-NEXT:       0060: 01000000 04000000 00000000 14000000
 // CHECK-NEXT:       0070: 70000000 00000000 01000000 04000000
-// CHECK-NEXT:       0080: 00000000 20000000 00000000 037A504C
+// CHECK-NEXT:       0080: 00000000 20000000 00000000 017A504C
 // CHECK-NEXT:       0090: 52000178 100B0000 00000000 00000002
 // CHECK-NEXT:       00A0: 1B0C0708 90010000 10000000 28000000
 // CHECK-NEXT:       00B0: 00000000 01000000 02000000 18000000
-// CHECK-NEXT:       00C0: 00000000 037A5052 00017810 04020000
+// CHECK-NEXT:       00C0: 00000000 017A5052 00017810 04020000
 // CHECK-NEXT:       00D0: 1B0C0708 90010000 10000000 20000000
 // CHECK-NEXT:       00E0: 00000000 01000000 00000000 18000000
-// CHECK-NEXT:       00F0: 00000000 037A5052 00017810 06030000
+// CHECK-NEXT:       00F0: 00000000 017A5052 00017810 06030000
 // CHECK-NEXT:       0100: 00001B0C 07089001 10000000 20000000
 // CHECK-NEXT:       0110: 00000000 01000000 00000000 1C000000
-// CHECK-NEXT:       0120: 00000000 037A5052 00017810 0A040000
+// CHECK-NEXT:       0120: 00000000 017A5052 00017810 0A040000
 // CHECK-NEXT:       0130: 00000000 00001B0C 07089001 10000000
 // CHECK-NEXT:       0140: 24000000 00000000 01000000 00000000
-// CHECK-NEXT:       0150: 18000000 00000000 037A5052 00017810
+// CHECK-NEXT:       0150: 18000000 00000000 017A5052 00017810
 // CHECK-NEXT:       0160: 040A0000 1B0C0708 90010000 10000000
 // CHECK-NEXT:       0170: 20000000 00000000 01000000 00000000
-// CHECK-NEXT:       0180: 18000000 00000000 037A5052 00017810
+// CHECK-NEXT:       0180: 18000000 00000000 017A5052 00017810
 // CHECK-NEXT:       0190: 060B0000 00001B0C 07089001 10000000
 // CHECK-NEXT:       01A0: 20000000 00000000 01000000 00000000
-// CHECK-NEXT:       01B0: 1C000000 00000000 037A5052 00017810
+// CHECK-NEXT:       01B0: 1C000000 00000000 017A5052 00017810
 // CHECK-NEXT:       01C0: 0A0C0000 00000000 00001B0C 07089001
 // CHECK-NEXT:       01D0: 10000000 24000000 00000000 01000000
-// CHECK-NEXT:       01E0: 00000000 1C000000 00000000 037A5052
+// CHECK-NEXT:       01E0: 00000000 1C000000 00000000 017A5052
 // CHECK-NEXT:       01F0: 00017810 0A080000 00000000 00001B0C
 // CHECK-NEXT:       0200: 07089001 10000000 24000000 00000000
 // CHECK-NEXT:       0210: 01000000 00000000 1C000000 00000000
-// CHECK-NEXT:       0220: 037A5052 00017810 0A100000 00000000
+// CHECK-NEXT:       0220: 017A5052 00017810 0A100000 00000000
 // CHECK-NEXT:       0230: 00001B0C 07089001 10000000 24000000
 // CHECK-NEXT:       0240: 00000000 01000000 00000000 18000000
-// CHECK-NEXT:       0250: 00000000 037A5052 00017810 04120000
+// CHECK-NEXT:       0250: 00000000 017A5052 00017810 04120000
 // CHECK-NEXT:       0260: 1B0C0708 90010000 10000000 20000000
 // CHECK-NEXT:       0270: 00000000 01000000 00000000 18000000
-// CHECK-NEXT:       0280: 00000000 037A5052 00017810 06130000
+// CHECK-NEXT:       0280: 00000000 017A5052 00017810 06130000
 // CHECK-NEXT:       0290: 00001B0C 07089001 10000000 20000000
 // CHECK-NEXT:       02A0: 00000000 01000000 00000000 1C000000
-// CHECK-NEXT:       02B0: 00000000 037A5052 00017810 0A140000
+// CHECK-NEXT:       02B0: 00000000 017A5052 00017810 0A140000
 // CHECK-NEXT:       02C0: 00000000 00001B0C 07089001 10000000
 // CHECK-NEXT:       02D0: 24000000 00000000 01000000 00000000
-// CHECK-NEXT:       02E0: 18000000 00000000 037A5052 00017810
+// CHECK-NEXT:       02E0: 18000000 00000000 017A5052 00017810
 // CHECK-NEXT:       02F0: 041A0000 1B0C0708 90010000 10000000
 // CHECK-NEXT:       0300: 20000000 00000000 01000000 00000000
-// CHECK-NEXT:       0310: 18000000 00000000 037A5052 00017810
+// CHECK-NEXT:       0310: 18000000 00000000 017A5052 00017810
 // CHECK-NEXT:       0320: 061B0000 00001B0C 07089001 10000000
 // CHECK-NEXT:       0330: 20000000 00000000 01000000 00000000
-// CHECK-NEXT:       0340: 1C000000 00000000 037A5052 00017810
+// CHECK-NEXT:       0340: 1C000000 00000000 017A5052 00017810
 // CHECK-NEXT:       0350: 0A1C0000 00000000 00001B0C 07089001
 // CHECK-NEXT:       0360: 10000000 24000000 00000000 01000000
-// CHECK-NEXT:       0370: 00000000 1C000000 00000000 037A5052
+// CHECK-NEXT:       0370: 00000000 1C000000 00000000 017A5052
 // CHECK-NEXT:       0380: 00017810 0A180000 00000000 00001B0C
 // CHECK-NEXT:       0390: 07089001 10000000 24000000 00000000
 // CHECK-NEXT:       03A0: 01000000 00000000 1C000000 00000000
-// CHECK-NEXT:       03B0: 037A5052 00017810 0A800000 00000000
+// CHECK-NEXT:       03B0: 017A5052 00017810 0A800000 00000000
 // CHECK-NEXT:       03C0: 00001B0C 07089001 10000000 24000000
 // CHECK-NEXT:       03D0: 00000000 01000000 00000000 18000000
-// CHECK-NEXT:       03E0: 00000000 037A5052 00017810 04820000
+// CHECK-NEXT:       03E0: 00000000 017A5052 00017810 04820000
 // CHECK-NEXT:       03F0: 1B0C0708 90010000 10000000 20000000
 // CHECK-NEXT:       0400: 00000000 01000000 00000000 18000000
-// CHECK-NEXT:       0410: 00000000 037A5052 00017810 06830000
+// CHECK-NEXT:       0410: 00000000 017A5052 00017810 06830000
 // CHECK-NEXT:       0420: 00001B0C 07089001 10000000 20000000
 // CHECK-NEXT:       0430: 00000000 01000000 00000000 1C000000
-// CHECK-NEXT:       0440: 00000000 037A5052 00017810 0A840000
+// CHECK-NEXT:       0440: 00000000 017A5052 00017810 0A840000
 // CHECK-NEXT:       0450: 00000000 00001B0C 07089001 10000000
 // CHECK-NEXT:       0460: 24000000 00000000 01000000 00000000
-// CHECK-NEXT:       0470: 18000000 00000000 037A5052 00017810
+// CHECK-NEXT:       0470: 18000000 00000000 017A5052 00017810
 // CHECK-NEXT:       0480: 048A0000 1B0C0708 90010000 10000000
 // CHECK-NEXT:       0490: 20000000 00000000 01000000 00000000
-// CHECK-NEXT:       04A0: 18000000 00000000 037A5052 00017810
+// CHECK-NEXT:       04A0: 18000000 00000000 017A5052 00017810
 // CHECK-NEXT:       04B0: 068B0000 00001B0C 07089001 10000000
 // CHECK-NEXT:       04C0: 20000000 00000000 01000000 00000000
-// CHECK-NEXT:       04D0: 1C000000 00000000 037A5052 00017810
+// CHECK-NEXT:       04D0: 1C000000 00000000 017A5052 00017810
 // CHECK-NEXT:       04E0: 0A8C0000 00000000 00001B0C 07089001
 // CHECK-NEXT:       04F0: 10000000 24000000 00000000 01000000
-// CHECK-NEXT:       0500: 00000000 1C000000 00000000 037A5052
+// CHECK-NEXT:       0500: 00000000 1C000000 00000000 017A5052
 // CHECK-NEXT:       0510: 00017810 0A880000 00000000 00001B0C
 // CHECK-NEXT:       0520: 07089001 10000000 24000000 00000000
 // CHECK-NEXT:       0530: 01000000 00000000 1C000000 00000000
-// CHECK-NEXT:       0540: 037A5052 00017810 0A900000 00000000
+// CHECK-NEXT:       0540: 017A5052 00017810 0A900000 00000000
 // CHECK-NEXT:       0550: 00001B0C 07089001 10000000 24000000
 // CHECK-NEXT:       0560: 00000000 01000000 00000000 18000000
-// CHECK-NEXT:       0570: 00000000 037A5052 00017810 04920000
+// CHECK-NEXT:       0570: 00000000 017A5052 00017810 04920000
 // CHECK-NEXT:       0580: 1B0C0708 90010000 10000000 20000000
 // CHECK-NEXT:       0590: 00000000 01000000 00000000 18000000
-// CHECK-NEXT:       05A0: 00000000 037A5052 00017810 06930000
+// CHECK-NEXT:       05A0: 00000000 017A5052 00017810 06930000
 // CHECK-NEXT:       05B0: 00001B0C 07089001 10000000 20000000
 // CHECK-NEXT:       05C0: 00000000 01000000 00000000 1C000000
-// CHECK-NEXT:       05D0: 00000000 037A5052 00017810 0A940000
+// CHECK-NEXT:       05D0: 00000000 017A5052 00017810 0A940000
 // CHECK-NEXT:       05E0: 00000000 00001B0C 07089001 10000000
 // CHECK-NEXT:       05F0: 24000000 00000000 01000000 00000000
-// CHECK-NEXT:       0600: 18000000 00000000 037A5052 00017810
+// CHECK-NEXT:       0600: 18000000 00000000 017A5052 00017810
 // CHECK-NEXT:       0610: 049A0000 1B0C0708 90010000 10000000
 // CHECK-NEXT:       0620: 20000000 00000000 01000000 00000000
-// CHECK-NEXT:       0630: 18000000 00000000 037A5052 00017810
+// CHECK-NEXT:       0630: 18000000 00000000 017A5052 00017810
 // CHECK-NEXT:       0640: 069B0000 00001B0C 07089001 10000000
 // CHECK-NEXT:       0650: 20000000 00000000 01000000 00000000
-// CHECK-NEXT:       0660: 1C000000 00000000 037A5052 00017810
+// CHECK-NEXT:       0660: 1C000000 00000000 017A5052 00017810
 // CHECK-NEXT:       0670: 0A9C0000 00000000 00001B0C 07089001
 // CHECK-NEXT:       0680: 10000000 24000000 00000000 01000000
-// CHECK-NEXT:       0690: 00000000 1C000000 00000000 037A5052
+// CHECK-NEXT:       0690: 00000000 1C000000 00000000 017A5052
 // CHECK-NEXT:       06A0: 00017810 0A980000 00000000 00001B0C
 // CHECK-NEXT:       06B0: 07089001 10000000 24000000 00000000
 // CHECK-NEXT:       06C0: 01000000 00000000 10000000 00000000
-// CHECK-NEXT:       06D0: 037A5200 01781001 1B000000 10000000
+// CHECK-NEXT:       06D0: 017A5200 01781001 1B000000 10000000
 // CHECK-NEXT:       06E0: 18000000 00000000 01000000 00000000
 // CHECK-NEXT:     )
 // CHECK-NEXT:   }
 
 // CHECK:        Section {
-// CHECK:          Index: 5
-// CHECK-NEXT:     Name: .rela.eh_frame
+// CHECK:          Index:
+// CHECK:          Name: .rela.eh_frame
 // CHECK-NEXT:     Type: SHT_RELA
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0xE70
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 1752
-// CHECK-NEXT:     Link: 7
-// CHECK-NEXT:     Info: 4
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/comdat-dup-group-name.s b/test/MC/ELF/comdat-dup-group-name.s
index 1181e2eab02a..a2dc4cc33d98 100644
--- a/test/MC/ELF/comdat-dup-group-name.s
+++ b/test/MC/ELF/comdat-dup-group-name.s
@@ -2,27 +2,27 @@
 
 // Test that we produce two foo sections, each in separate groups
 
-// CHECK: Index: 1
-// CHECK-NEXT: Name: .group
-
-// CHECK: Index: 2
+// CHECK: Index: 5
 // CHECK-NEXT: Name: .group
 
 // CHECK: Index: 6
 // CHECK-NEXT: Name: .foo
 
 // CHECK: Index: 7
+// CHECK-NEXT: Name: .group
+
+// CHECK: Index: 8
 // CHECK-NEXT: Name: .foo
 
 // CHECK: Symbols [
 
 // CHECK: Name: f1
 // CHECK-NOT: }
-// CHECK: Section: .group (0x1)
+// CHECK: Section: .group (0x5)
 
 // CHECK: Name: f2
 // CHECK-NOT: }
-// CHECK: Section: .group (0x2)
+// CHECK: Section: .group (0x7)
 
 // CHECK: Name: .foo
 // CHECK-NOT: }
@@ -30,7 +30,7 @@
 
 // CHECK: Name: .foo
 // CHECK-NOT: }
-// CHECK: Section: .foo (0x7)
+// CHECK: Section: .foo (0x8)
 
 
 	.section	.foo,"axG",@progbits,f1,comdat
diff --git a/test/MC/ELF/comdat-reloc.s b/test/MC/ELF/comdat-reloc.s
index d893a7b149ef..1ea3d1e57efa 100644
--- a/test/MC/ELF/comdat-reloc.s
+++ b/test/MC/ELF/comdat-reloc.s
@@ -16,14 +16,14 @@ world:
 // CHECK:  Name: .group
 // CHECK-NOT: SectionData
 // CHECK: SectionData
-// CHECK-NEXT: 0000: 01000000 06000000 07000000
+// CHECK-NEXT: 0000: 01000000 07000000 08000000
 
-// CHECK: Index: 6
+// CHECK: Index: 7
 // CHECK-NEXT: Name: .text.world
 // CHECK-NOT: Section {
 // CHECK: SHF_GROUP
 
-// CHECK: Index: 7
+// CHECK: Index: 8
 // CHECK-NEXT: Name: .rela.text.world
 // CHECK-NOT: Section {
 // CHECK: SHF_GROUP
diff --git a/test/MC/ELF/comdat.s b/test/MC/ELF/comdat.s
index 479667552204..e71dea089c4d 100644
--- a/test/MC/ELF/comdat.s
+++ b/test/MC/ELF/comdat.s
@@ -1,49 +1,57 @@
-// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -t | FileCheck %s
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -t -sd | FileCheck %s
 
-// Test that we produce the group sections and that they are at the beginning
-// of the file.
+// Test that we produce the group sections and that they are before the members
 
 // CHECK:        Section {
-// CHECK:          Index: 1
+// CHECK:          Index: 5
 // CHECK-NEXT:     Name: .group
 // CHECK-NEXT:     Type: SHT_GROUP
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x40
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 12
-// CHECK-NEXT:     Link: 13
+// CHECK-NEXT:     Link:
 // CHECK-NEXT:     Info: 1
 // CHECK-NEXT:     AddressAlignment: 4
 // CHECK-NEXT:     EntrySize: 4
+// CHECK-NEXT:     SectionData (
+// CHECK-NEXT:       0000:    01000000 06000000 07000000
+// CHECK-NEXT:     )
 // CHECK-NEXT:   }
-// CHECK-NEXT:   Section {
-// CHECK-NEXT:     Index: 2
+// CHECK:        Section {
+// CHECK:          Index: 8
 // CHECK-NEXT:     Name: .group
 // CHECK-NEXT:     Type: SHT_GROUP
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x4C
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 8
-// CHECK-NEXT:     Link: 13
+// CHECK-NEXT:     Link:
 // CHECK-NEXT:     Info: 2
 // CHECK-NEXT:     AddressAlignment: 4
 // CHECK-NEXT:     EntrySize: 4
+// CHECK-NEXT:     SectionData (
+// CHECK-NEXT:       0000:    01000000 09000000
+// CHECK-NEXT:     )
 // CHECK-NEXT:   }
-// CHECK-NEXT:   Section {
-// CHECK-NEXT:     Index: 3
+// CHECK:        Section {
+// CHECK:          Index: 10
 // CHECK-NEXT:     Name: .group
 // CHECK-NEXT:     Type: SHT_GROUP
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x54
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 12
-// CHECK-NEXT:     Link: 13
+// CHECK-NEXT:     Link:
 // CHECK-NEXT:     Info: 10
 // CHECK-NEXT:     AddressAlignment: 4
 // CHECK-NEXT:     EntrySize: 4
+// CHECK-NEXT:     SectionData (
+// CHECK-NEXT:       0000:    01000000 0B000000 0C000000
+// CHECK-NEXT:     )
 // CHECK-NEXT:   }
 
 // Test that g1 and g2 are local, but g3 is an undefined global.
@@ -55,7 +63,7 @@
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .foo (0x7)
+// CHECK-NEXT:     Section: .foo
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: g2
@@ -64,7 +72,7 @@
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .group (0x2)
+// CHECK-NEXT:     Section: .group (0x8)
 // CHECK-NEXT:   }
 
 // CHECK:        Symbol {
diff --git a/test/MC/ELF/common-error1.s b/test/MC/ELF/common-error1.s
new file mode 100644
index 000000000000..a413885b0165
--- /dev/null
+++ b/test/MC/ELF/common-error1.s
@@ -0,0 +1,6 @@
+// RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux < %s 2>&1 | FileCheck %s
+
+        .comm   C,4,4
+        .set    A,C
+
+// CHECK: Common symbol C cannot be used in assignment expr
diff --git a/test/MC/ELF/common-error2.s b/test/MC/ELF/common-error2.s
new file mode 100644
index 000000000000..d666feedee6a
--- /dev/null
+++ b/test/MC/ELF/common-error2.s
@@ -0,0 +1,6 @@
+// RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux < %s 2>&1 | FileCheck %s
+
+        .set    A,C
+        .comm   C,4,4
+
+// CHECK: Common symbol C cannot be used in assignment expr
diff --git a/test/MC/ELF/common.s b/test/MC/ELF/common.s
index bd96564a5ca1..b7e6ba074f4d 100644
--- a/test/MC/ELF/common.s
+++ b/test/MC/ELF/common.s
@@ -45,7 +45,7 @@
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: Object
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .bss (0x4)
+// CHECK-NEXT:     Section: .bss
 // CHECK-NEXT:   }
 
 
diff --git a/test/MC/ELF/common2.s b/test/MC/ELF/common2.s
index 526ebc2a95ff..26c32a7c8408 100644
--- a/test/MC/ELF/common2.s
+++ b/test/MC/ELF/common2.s
@@ -10,7 +10,7 @@
 	.align	8
 
 // CHECK:        Section {
-// CHECK:          Name: .bss (7)
+// CHECK:          Name: .bss
 // CHECK-NEXT:     Type:
 // CHECK-NEXT:     Flags [
 // CHECK:          ]
diff --git a/test/MC/ELF/compression.s b/test/MC/ELF/compression.s
index 07b689eef1f1..5560ba78c68f 100644
--- a/test/MC/ELF/compression.s
+++ b/test/MC/ELF/compression.s
@@ -10,7 +10,6 @@
 // Check for the 'ZLIB' file magic at the start of the section only
 // CHECK-NEXT: ZLIB
 // CHECK-NOT: ZLIB
-// CHECK: Contents of
 
 // Don't compress small sections, such as this simple debug_abbrev example
 // CHECK: Contents of section .debug_abbrev:
diff --git a/test/MC/ELF/debug-line.s b/test/MC/ELF/debug-line.s
index 38ef8284a0df..072265c5c701 100644
--- a/test/MC/ELF/debug-line.s
+++ b/test/MC/ELF/debug-line.s
@@ -17,7 +17,7 @@
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x50
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 57
 // CHECK-NEXT:     Link: 0
 // CHECK-NEXT:     Info: 0
diff --git a/test/MC/ELF/debug-loc.s b/test/MC/ELF/debug-loc.s
index b24fa169deb2..ea8eb3ec70cd 100644
--- a/test/MC/ELF/debug-loc.s
+++ b/test/MC/ELF/debug-loc.s
@@ -8,8 +8,8 @@
 // FIXME2: We need a debug_line dumper so that we can test the actual contents.
 
 // CHECK:        Section {
-// CHECK:          Index: 4
-// CHECK-NEXT:     Name: .debug_line
+// CHECK:          Index:
+// CHECK:          Name: .debug_line
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
diff --git a/test/MC/ELF/empty-dwarf-lines.s b/test/MC/ELF/empty-dwarf-lines.s
index 241580bb3b83..19305709cda6 100644
--- a/test/MC/ELF/empty-dwarf-lines.s
+++ b/test/MC/ELF/empty-dwarf-lines.s
@@ -8,8 +8,8 @@ c:
         .asciz   "hi\n"
 
 // CHECK:        Section {
-// CHECK:          Index: 4
-// CHECK-NEXT:     Name: .debug_line
+// CHECK:          Index:
+// CHECK:          Name: .debug_line
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
diff --git a/test/MC/ELF/empty.s b/test/MC/ELF/empty.s
index c421fe844882..6ddbd8c942a2 100644
--- a/test/MC/ELF/empty.s
+++ b/test/MC/ELF/empty.s
@@ -1,9 +1,32 @@
 // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s | FileCheck %s
+// RUN: llvm-mc -filetype=obj -triple x86_64-apple-darwin14.0.0-elf %s -o - | llvm-readobj -s | FileCheck %s -check-prefix=DARWIN
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32-elf %s -o - | llvm-readobj -s | FileCheck %s -check-prefix=WINDOWS
+
+// Check that we can create ELF files for darwin/windows, even though
+// it is not the default file format.
+
+// DARWIN:       Format: ELF64-x86-64
+// WINDOWS:      Format: ELF64-x86-64
+// DARWIN-NEXT:  Arch: x86_64
+// WINDOWS-NEXT: Arch: x86_64
 
 // Test that like gnu as we create text, data and bss by default. Also test
-// that shstrtab, symtab and strtab are listed in that order.
+// that symtab and strtab are listed.
 
 // CHECK:        Section {
+// CHECK:          Name: .strtab
+// CHECK-NEXT:     Type: SHT_STRTAB
+// CHECK-NEXT:     Flags [
+// CHECK-NEXT:     ]
+// CHECK-NEXT:     Address: 0x0
+// CHECK-NEXT:     Offset:
+// CHECK-NEXT:     Size: 34
+// CHECK-NEXT:     Link: 0
+// CHECK-NEXT:     Info: 0
+// CHECK-NEXT:     AddressAlignment: 1
+// CHECK-NEXT:     EntrySize: 0
+// CHECK-NEXT:   }
+// CHECK:        Section {
 // CHECK:          Name: .text
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
@@ -49,19 +72,6 @@
 // CHECK-NEXT:     EntrySize: 0
 // CHECK-NEXT:   }
 // CHECK:        Section {
-// CHECK:          Name: .shstrtab
-// CHECK-NEXT:     Type: SHT_STRTAB
-// CHECK-NEXT:     Flags [
-// CHECK-NEXT:     ]
-// CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x40
-// CHECK-NEXT:     Size: 44
-// CHECK-NEXT:     Link: 0
-// CHECK-NEXT:     Info: 0
-// CHECK-NEXT:     AddressAlignment: 1
-// CHECK-NEXT:     EntrySize: 0
-// CHECK-NEXT:   }
-// CHECK:        Section {
 // CHECK:          Name: .symtab
 // CHECK-NEXT:     Type: SHT_SYMTAB
 // CHECK-NEXT:     Flags [
@@ -69,21 +79,8 @@
 // CHECK-NEXT:     Address: 0x0
 // CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 96
-// CHECK-NEXT:     Link: 6
+// CHECK-NEXT:     Link:
 // CHECK-NEXT:     Info: 4
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:   }
-// CHECK:        Section {
-// CHECK:          Name: .strtab
-// CHECK-NEXT:     Type: SHT_STRTAB
-// CHECK-NEXT:     Flags [
-// CHECK-NEXT:     ]
-// CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset:
-// CHECK-NEXT:     Size: 1
-// CHECK-NEXT:     Link: 0
-// CHECK-NEXT:     Info: 0
-// CHECK-NEXT:     AddressAlignment: 1
-// CHECK-NEXT:     EntrySize: 0
-// CHECK-NEXT:   }
diff --git a/test/MC/ELF/entsize.ll b/test/MC/ELF/entsize.ll
index 2bf9fa9fb594..941a300bdda5 100644
--- a/test/MC/ELF/entsize.ll
+++ b/test/MC/ELF/entsize.ll
@@ -8,10 +8,10 @@
 @.c8b = private unnamed_addr constant [1 x i64] [i64 42]
 
 define i32 @main() nounwind {
-  %1 = call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0))
-  %2 = call i32 @puts(i8* getelementptr inbounds ([7 x i8]* @.str2, i32 0, i32 0))
-  call void @foo(i64* getelementptr inbounds ([1 x i64]* @.c8a, i32 0, i32 0))
-  call void @foo(i64* getelementptr inbounds ([1 x i64]* @.c8b, i32 0, i32 0))
+  %1 = call i32 @puts(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0))
+  %2 = call i32 @puts(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str2, i32 0, i32 0))
+  call void @foo(i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.c8a, i32 0, i32 0))
+  call void @foo(i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.c8b, i32 0, i32 0))
   ret i32 0
 }
 
diff --git a/test/MC/ELF/entsize.s b/test/MC/ELF/entsize.s
index 8e084e24b255..1dc6103189da 100644
--- a/test/MC/ELF/entsize.s
+++ b/test/MC/ELF/entsize.s
@@ -33,8 +33,8 @@
     .quad 42
 
 // CHECK:        Section {
-// CHECK:          Index: 4
-// CHECK-NEXT:     Name: .rodata.str1.1
+// CHECK:          Index:
+// CHECK:          Name: .rodata.str1.1
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
@@ -50,8 +50,8 @@
 // CHECK-NEXT:     EntrySize: 1
 // CHECK-NEXT:   }
 // CHECK:        Section {
-// CHECK:          Index: 5
-// CHECK-NEXT:     Name: .rodata.str2.1
+// CHECK:          Index:
+// CHECK:          Name: .rodata.str2.1
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
@@ -67,8 +67,8 @@
 // CHECK-NEXT:     EntrySize: 2
 // CHECK-NEXT:   }
 // CHECK:        Section {
-// CHECK:          Index: 6
-// CHECK-NEXT:     Name: .rodata.cst8
+// CHECK:          Index:
+// CHECK:          Name: .rodata.cst8
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
diff --git a/test/MC/ELF/file-double.s b/test/MC/ELF/file-double.s
index b5da8c5a8588..8ea5fc759b37 100644
--- a/test/MC/ELF/file-double.s
+++ b/test/MC/ELF/file-double.s
@@ -34,7 +34,7 @@ bar.c:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK:        Symbol {
 // CHECK:        Name: foo.c
@@ -43,5 +43,5 @@ bar.c:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
diff --git a/test/MC/ELF/file.s b/test/MC/ELF/file.s
index 6b6cb44e2b28..b19bda7c42ca 100644
--- a/test/MC/ELF/file.s
+++ b/test/MC/ELF/file.s
@@ -6,7 +6,7 @@
 foa:
 
 // CHECK:        Symbol {
-// CHECK:          Name: foo (1)
+// CHECK:          Name: foo
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
@@ -15,11 +15,11 @@ foa:
 // CHECK-NEXT:     Section: Absolute (0xFFF1)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foa (5)
+// CHECK-NEXT:     Name: foa
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
diff --git a/test/MC/ELF/gen-dwarf.s b/test/MC/ELF/gen-dwarf.s
index 7f0c0594ce95..4e773c79af28 100644
--- a/test/MC/ELF/gen-dwarf.s
+++ b/test/MC/ELF/gen-dwarf.s
@@ -34,6 +34,7 @@ foo:
 // ASM: .section .debug_info
 
 // ASM: .section .debug_abbrev
+// ASM-NEXT: .Lsection_abbrev:
 // ASM-NEXT: [[ABBREV_LABEL:.Ltmp[0-9]+]]
 
 // Second instance of the section has the CU
diff --git a/test/MC/ELF/ifunc-reloc.s b/test/MC/ELF/ifunc-reloc.s
index 01954631cca1..6f1d79b22c47 100644
--- a/test/MC/ELF/ifunc-reloc.s
+++ b/test/MC/ELF/ifunc-reloc.s
@@ -10,7 +10,7 @@ alias:
         callq sym
 
 // CHECK: Relocations [
-// CHECK-NEXT:   Section (2) .rela.text {
+// CHECK-NEXT:   Section {{.*}} .rela.text {
 // CHECK-NEXT:     0x1 R_X86_64_PC32 sym 0xFFFFFFFFFFFFFFFC
 // CHECK-NEXT:   }
 // CHECK-NEXT: ]
diff --git a/test/MC/ELF/lcomm.s b/test/MC/ELF/lcomm.s
index 7d8ac3fcafa0..94bd5ea19976 100644
--- a/test/MC/ELF/lcomm.s
+++ b/test/MC/ELF/lcomm.s
@@ -10,7 +10,7 @@
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: Object
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .bss (0x3)
+// CHECK-NEXT:     Section: .bss
 // CHECK-NEXT:   }
 // CHECK:        Symbol {
 // CHECK:          Name: B
@@ -19,5 +19,5 @@
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: Object
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .bss (0x3)
+// CHECK-NEXT:     Section: .bss
 // CHECK-NEXT:   }
diff --git a/test/MC/ELF/local-reloc.s b/test/MC/ELF/local-reloc.s
index 19b950986680..ce0b674364c2 100644
--- a/test/MC/ELF/local-reloc.s
+++ b/test/MC/ELF/local-reloc.s
@@ -7,7 +7,7 @@
 foo:
 
 // CHECK:      Relocations [
-// CHECK:        Section (2) .rela.text {
+// CHECK:        Section {{.*}} .rela.text {
 // CHECK-NEXT:     0x{{[^ ]+}} R_X86_64_32S .text 0x{{[^ ]+}}
 // CHECK-NEXT:   }
 // CHECK-NEXT: ]
diff --git a/test/MC/ELF/many-sections-2.s b/test/MC/ELF/many-sections-2.s
index 88a4822c3869..b52c01af4905 100644
--- a/test/MC/ELF/many-sections-2.s
+++ b/test/MC/ELF/many-sections-2.s
@@ -18,7 +18,7 @@
 // SYMBOLS-NEXT:    Binding: Local (0x0)
 // SYMBOLS-NEXT:    Type: None (0x0)
 // SYMBOLS-NEXT:    Other: 0
-// SYMBOLS-NEXT:    Section: last (0xFF00)
+// SYMBOLS-NEXT:    Section: dm (0xFF00)
 // SYMBOLS-NEXT:  }
 // SYMBOLS-NEXT:  Symbol {
 // SYMBOLS-NEXT:    Name: b
@@ -27,18 +27,18 @@
 // SYMBOLS-NEXT:    Binding: Local (0x0)
 // SYMBOLS-NEXT:    Type: None (0x0)
 // SYMBOLS-NEXT:    Other: 0
-// SYMBOLS-NEXT:    Section: last (0xFF00)
+// SYMBOLS-NEXT:    Section: dm (0xFF00)
 // SYMBOLS-NEXT:  }
 
 
 // Test that this file has one section too many.
-// SYMBOLS:         Name: last
+// SYMBOLS:         Name: dm
 // SYMBOLS-NEXT:    Value: 0x0
 // SYMBOLS-NEXT:    Size: 0
 // SYMBOLS-NEXT:    Binding: Local (0x0)
 // SYMBOLS-NEXT:    Type: Section (0x3)
 // SYMBOLS-NEXT:    Other: 0
-// SYMBOLS-NEXT:    Section: last (0xFF00)
+// SYMBOLS-NEXT:    Section: dm (0xFF00)
 // SYMBOLS-NEXT:  }
 // SYMBOLS-NEXT:]
 
@@ -128,6 +128,5 @@ gen_sections16 k
 gen_sections8 l
 gen_sections4 m
 
-.section last
 a:
 b = a + 1
diff --git a/test/MC/ELF/many-sections.s b/test/MC/ELF/many-sections.s
index 93ea8e7821e2..dbba8711fdf6 100644
--- a/test/MC/ELF/many-sections.s
+++ b/test/MC/ELF/many-sections.s
@@ -9,13 +9,13 @@
 
 // Check the last referenced section.
 
-// SYMBOLS:         Name: dm (0)
+// SYMBOLS:         Name: zed
 // SYMBOLS-NEXT:    Value: 0x0
 // SYMBOLS-NEXT:    Size: 0
 // SYMBOLS-NEXT:    Binding: Local (0x0)
 // SYMBOLS-NEXT:    Type: Section (0x3)
 // SYMBOLS-NEXT:    Other: 0
-// SYMBOLS-NEXT:    Section: dm (0xFEFF)
+// SYMBOLS-NEXT:    Section: zed (0xFEFF)
 // SYMBOLS-NEXT:  }
 // SYMBOLS-NEXT:]
 
@@ -103,4 +103,6 @@ gen_sections64 i
 gen_sections32 j
 gen_sections16 k
 gen_sections8 l
-gen_sections4 m
+        .section foo
+        .section bar
+        .section zed
diff --git a/test/MC/ELF/merge.s b/test/MC/ELF/merge.s
index d6e0b7c4b7dc..e787728ae197 100644
--- a/test/MC/ELF/merge.s
+++ b/test/MC/ELF/merge.s
@@ -21,7 +21,7 @@ zed:
 foo:
 
 // CHECK:      Relocations [
-// CHECK-NEXT:   Section (2) .rela.text {
+// CHECK-NEXT:   Section {{.*}} .rela.text {
 // CHECK-NEXT:     0x{{[^ ]+}} R_X86_64_PC32    .Lfoo 0x{{[^ ]+}}
 // CHECK-NEXT:     0x{{[^ ]+}} R_X86_64_32      .sec1 0x{{[^ ]+}}
 // CHECK-NEXT:     0x{{[^ ]+}} R_X86_64_32      .Lfoo 0x{{[^ ]+}}
diff --git a/test/MC/ELF/n_bytes.s b/test/MC/ELF/n_bytes.s
index e658de09a2fa..fcbd0e88c2c7 100644
--- a/test/MC/ELF/n_bytes.s
+++ b/test/MC/ELF/n_bytes.s
@@ -6,8 +6,8 @@
         .int 42, 1, 2, 3
 
 // CHECK:        Section {
-// CHECK:          Index: 1
-// CHECK-NEXT:     Name: .text
+// CHECK:          Index:
+// CHECK:          Name: .text
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
diff --git a/test/MC/ELF/noexec.s b/test/MC/ELF/noexec.s
index 28f50cb7f692..3769427a3b1a 100644
--- a/test/MC/ELF/noexec.s
+++ b/test/MC/ELF/noexec.s
@@ -1,8 +1,8 @@
 // RUN: llvm-mc -no-exec-stack -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -t | FileCheck  %s
 
 // CHECK:        Section {
-// CHECK:          Index: 4
-// CHECK-NEXT:     Name: .note.GNU-stack
+// CHECK:          Index:
+// CHECK:          Name: .note.GNU-stack
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
@@ -22,5 +22,5 @@
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: Section
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .note.GNU-stack (0x4)
+// CHECK-NEXT:     Section: .note.GNU-stack
 // CHECK-NEXT:   }
diff --git a/test/MC/ELF/norelocation.s b/test/MC/ELF/norelocation.s
index 137038292802..054fc5f95cb2 100644
--- a/test/MC/ELF/norelocation.s
+++ b/test/MC/ELF/norelocation.s
@@ -1,26 +1,7 @@
-// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd -sr | FileCheck  %s
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -r | FileCheck  %s
 
         call bar
 bar:
 
-// CHECK:        Section {
-// CHECK:          Name: .text
-// CHECK-NEXT:     Type: SHT_PROGBITS
-// CHECK-NEXT:     Flags [ (0x6)
-// CHECK-NEXT:       SHF_ALLOC
-// CHECK-NEXT:       SHF_EXECINSTR
-// CHECK-NEXT:     ]
-// CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x40
-// CHECK-NEXT:     Size: 5
-// CHECK-NEXT:     Link: 0
-// CHECK-NEXT:     Info: 0
-// CHECK-NEXT:     AddressAlignment: 4
-// CHECK-NEXT:     EntrySize: 0
-// CHECK-NEXT:     Relocations [
-// CHECK-NEXT:     ]
-// CHECK-NEXT:     SectionData (
-// CHECK-NEXT:       0000: E8000000 00
-// CHECK-NEXT:     )
-// CHECK-NEXT:   }
-// CHECK: shstrtab
+// CHECK:      Relocations [
+// CHECK-NEXT: ]
diff --git a/test/MC/ELF/pr19430.s b/test/MC/ELF/pr19430.s
index a1e524662a96..3ba6d729b4be 100644
--- a/test/MC/ELF/pr19430.s
+++ b/test/MC/ELF/pr19430.s
@@ -8,7 +8,7 @@
  .cfi_endproc
 
 // CHECK:      Relocations [
-// CHECK-NEXT:   Section (5) .rela.eh_frame {
+// CHECK-NEXT:   Section ({{.*}}) .rela.eh_frame {
 // CHECK-NEXT:     0x20 R_X86_64_PC32 .text 0x3E8
 // CHECK-NEXT:   }
 // CHECK-NEXT: ]
diff --git a/test/MC/ELF/pr19582.s b/test/MC/ELF/pr19582.s
new file mode 100644
index 000000000000..304cacb2972c
--- /dev/null
+++ b/test/MC/ELF/pr19582.s
@@ -0,0 +1,8 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -r | FileCheck %s
+
+a:
+    .section foo
+    c = b
+b:
+    // CHECK: 0x0 R_X86_64_PC32 .text 0x0
+    .long a - c
diff --git a/test/MC/ELF/relax.s b/test/MC/ELF/relax.s
index 49ee8e2eefe0..93db0fe9b944 100644
--- a/test/MC/ELF/relax.s
+++ b/test/MC/ELF/relax.s
@@ -30,4 +30,4 @@ foo:
 // CHECK-NEXT:     )
 // CHECK-NEXT:   }
 // CHECK:        Symbol {
-// CHECK:          Name: foo (5)
+// CHECK:          Name: foo
diff --git a/test/MC/ELF/relocation-386.s b/test/MC/ELF/relocation-386.s
index 83c524b9d07b..2af6addc3d2b 100644
--- a/test/MC/ELF/relocation-386.s
+++ b/test/MC/ELF/relocation-386.s
@@ -4,7 +4,7 @@
 // correctly point to the section or the symbol.
 
 // CHECK:      Relocations [
-// CHECK-NEXT:   Section (2) .rel.text {
+// CHECK-NEXT:   Section {{.*}} .rel.text {
 // CHECK-NEXT:     0x2          R_386_GOTOFF     .Lfoo 0x0
 // CHECK-NEXT:     0x{{[^ ]+}}  R_386_PLT32      bar2 0x0
 // CHECK-NEXT:     0x{{[^ ]+}}  R_386_GOTPC      _GLOBAL_OFFSET_TABLE_ 0x0
@@ -65,6 +65,9 @@
 // CHECK-NEXT:     0xA3         R_386_GOTOFF     und_symbol 0x0
 // Relocation 29 (zed@PLT) is of type R_386_PLT32 and uses the symbol
 // CHECK-NEXT:     0xA9         R_386_PLT32      zed 0x0
+// CHECK-NEXT:     0xAF         R_386_PC32       tr_start 0x0
+// CHECK-NEXT:     0xB3         R_386_16         foo      0x0
+// CHECK-NEXT:     0xB5         R_386_8          foo      0x0
 // CHECK-NEXT:   }
 // CHECK-NEXT: ]
 
@@ -76,7 +79,7 @@
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: TLS
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: zedsec (0x5)
+// CHECK-NEXT:     Section: zedsec
 // CHECK-NEXT:   }
 // Symbol 7 is section 4
 // CHECK:        Symbol {
@@ -86,7 +89,7 @@
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: Section
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .bss (0x4)
+// CHECK-NEXT:     Section: .bss
 // CHECK-NEXT:   }
 
         .text
@@ -133,6 +136,12 @@ bar2:
         leal 1 + und_symbol@GOTOFF, %edi
         movl zed@PLT(%eax), %eax
 
+        .code64
+        jmpq *tr_start(%rip)
+
+        .word foo
+        .byte foo
+
         .section        zedsec,"awT",@progbits
 zed:
         .long 0
diff --git a/test/MC/ELF/relocation-pc.s b/test/MC/ELF/relocation-pc.s
index 0ce32010cf0e..ca7addf3a620 100644
--- a/test/MC/ELF/relocation-pc.s
+++ b/test/MC/ELF/relocation-pc.s
@@ -6,23 +6,16 @@
 	jmp	-256              # R_X86_64_PC32
 
 // CHECK:        Section {
-// CHECK:          Index: 1
-// CHECK-NEXT:     Name: .text
-// CHECK:          Relocations [
-// CHECK-NEXT:     ]
-// CHECK-NEXT:   }
-
-// CHECK:        Section {
-// CHECK:          Index: 2
-// CHECK-NEXT:     Name: .rela.text
+// CHECK:          Index:
+// CHECK:          Name: .rela.text
 // CHECK-NEXT:     Type: SHT_RELA
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x2E8
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 48
-// CHECK-NEXT:     Link: 6
-// CHECK-NEXT:     Info: 1
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
diff --git a/test/MC/ELF/relocation.s b/test/MC/ELF/relocation.s
index c0e6007dc4e7..2841612f2e11 100644
--- a/test/MC/ELF/relocation.s
+++ b/test/MC/ELF/relocation.s
@@ -2,6 +2,14 @@
 
 // Test that we produce the correct relocation.
 
+
+        .section	.pr23272,"aGw",@progbits,pr23272,comdat
+	.globl pr23272
+pr23272:
+pr23272_2:
+pr23272_3 = pr23272_2
+
+        .text
 bar:
         movl	$bar, %edx        # R_X86_64_32
         movq	$bar, %rdx        # R_X86_64_32S
@@ -34,6 +42,18 @@ bar:
         movl  $_GLOBAL_OFFSET_TABLE_, %eax
         movabs  $_GLOBAL_OFFSET_TABLE_, %rax
 
+        .quad    blah@SIZE                        # R_X86_64_SIZE64
+        .quad    blah@SIZE + 32                   # R_X86_64_SIZE64
+        .quad    blah@SIZE - 32                   # R_X86_64_SIZE64
+         movl    blah@SIZE, %eax                  # R_X86_64_SIZE32
+         movl    blah@SIZE + 32, %eax             # R_X86_64_SIZE32
+         movl    blah@SIZE - 32, %eax             # R_X86_64_SIZE32
+
+        .long   foo@gotpcrel
+        .long foo@plt
+
+        .quad	pr23272_2 - pr23272
+        .quad	pr23272_3 - pr23272
 // CHECK:        Section {
 // CHECK:          Name: .rela.text
 // CHECK:          Relocations [
@@ -62,6 +82,14 @@ bar:
 // CHECK-NEXT:       0x98 R_X86_64_PC32 foo 0xFFFFFFFFFFFFFFFB
 // CHECK-NEXT:       0x9D R_X86_64_GOTPC32 _GLOBAL_OFFSET_TABLE_ 0x1
 // CHECK-NEXT:       0xA3 R_X86_64_GOTPC64 _GLOBAL_OFFSET_TABLE_ 0x2
+// CHECK-NEXT:       0xAB R_X86_64_SIZE64 blah 0x0
+// CHECK-NEXT:       0xB3 R_X86_64_SIZE64 blah 0x20
+// CHECK-NEXT:       0xBB R_X86_64_SIZE64 blah 0xFFFFFFFFFFFFFFE0
+// CHECK-NEXT:       0xC6 R_X86_64_SIZE32 blah 0x0
+// CHECK-NEXT:       0xCD R_X86_64_SIZE32 blah 0x20
+// CHECK-NEXT:       0xD4 R_X86_64_SIZE32 blah 0xFFFFFFFFFFFFFFE0
+// CHECK-NEXT:       0xD8 R_X86_64_GOTPCREL foo 0x0
+// CHECK-NEXT:       0xDC R_X86_64_PLT32 foo 0x0
 // CHECK-NEXT:     ]
 // CHECK-NEXT:   }
 
@@ -72,5 +100,5 @@ bar:
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: Section
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
diff --git a/test/MC/ELF/rename.s b/test/MC/ELF/rename.s
index 5364dde9f460..8be06424cf27 100644
--- a/test/MC/ELF/rename.s
+++ b/test/MC/ELF/rename.s
@@ -15,51 +15,20 @@ defined3:
 
         .global defined1
 
-// Section 1 is .text
 // CHECK:        Section {
-// CHECK:          Index: 1
-// CHECK-NEXT:     Name: .text
-// CHECK-NEXT:     Type: SHT_PROGBITS
-// CHECK-NEXT:     Flags [
-// CHECK-NEXT:       SHF_ALLOC
-// CHECK-NEXT:       SHF_EXECINSTR
-// CHECK-NEXT:     ]
-// CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x40
-// CHECK-NEXT:     Size: 4
-// CHECK-NEXT:     Link: 0
-// CHECK-NEXT:     Info: 0
-// CHECK-NEXT:     AddressAlignment: 4
-// CHECK-NEXT:     EntrySize: 0
-// CHECK-NEXT:     Relocations [
-// CHECK-NEXT:     ]
-// CHECK-NEXT:   }
-// CHECK-NEXT:   Section {
-// CHECK-NEXT:     Index: 2
-// CHECK-NEXT:     Name: .rela.text (1)
+// CHECK:          Index:
+// CHECK:          Name: .rela.text
 // CHECK-NEXT:     Type: SHT_RELA (0x4)
 // CHECK-NEXT:     Flags [ (0x0)
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x320
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
-// CHECK-NEXT:     Link: 6
-// CHECK-NEXT:     Info: 1
+// CHECK-NEXT:     Link:
+// CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:       0x0 R_X86_64_32 .text 0x0
 // CHECK-NEXT:     ]
 // CHECK-NEXT:   }
-
-
-// Symbol 2 is section 1
-// CHECK:        Symbol {
-// CHECK:          Name: .text (0)
-// CHECK-NEXT:     Value: 0x0
-// CHECK-NEXT:     Size: 0
-// CHECK-NEXT:     Binding: Local
-// CHECK-NEXT:     Type: Section
-// CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
-// CHECK-NEXT:   }
diff --git a/test/MC/ELF/section-sym.s b/test/MC/ELF/section-sym.s
index 3b76d813fe7c..f012b2f1bed7 100644
--- a/test/MC/ELF/section-sym.s
+++ b/test/MC/ELF/section-sym.s
@@ -17,22 +17,22 @@
 // CHECK-NEXT:     SHF_GROUP (0x200)
 // CHECK-NEXT:   ]
 // CHECK-NEXT:   Address:         0x0
-// CHECK-NEXT:   Offset:  0x50
+// CHECK-NEXT:   Offset:
 // CHECK-NEXT:   Size:    0
 // CHECK-NEXT:   Link:    0
 // CHECK-NEXT:   Info:    0
 // CHECK-NEXT:   AddressAlignment:        1
 // CHECK-NEXT:   EntrySize:       0
 // CHECK-NEXT: }
-// CHECK-NEXT: Section {
-// CHECK-NEXT:   Index:   7
+// CHECK:      Section {
+// CHECK:        Index:   8
 // CHECK-NEXT:   Name:    foo (28)
 // CHECK-NEXT:   Type:    SHT_PROGBITS (0x1)
 // CHECK-NEXT:   Flags [ (0x200)
 // CHECK-NEXT:     SHF_GROUP (0x200)
 // CHECK-NEXT:   ]
 // CHECK-NEXT:   Address:         0x0
-// CHECK-NEXT:   Offset:  0x50
+// CHECK-NEXT:   Offset:
 // CHECK-NEXT:   Size:    0
 // CHECK-NEXT:   Link:    0
 // CHECK-NEXT:   Info:    0
@@ -42,7 +42,7 @@
 
 // The relocation points to symbol 6
 // CHECK:      Relocations [
-// CHECK-NEXT:   Section (9) .relabar {
+// CHECK-NEXT:   Section ({{.*}}) .relabar {
 // CHECK-NEXT:     Relocation {
 // CHECK-NEXT:       Offset:  0x0
 // CHECK-NEXT:       Type:    R_X86_64_32 (10)
@@ -88,4 +88,4 @@
 // symbol 7
 // CHECK-NOT: Name
 // CHECK: Name:    foo
-// CHECK: Section: foo (0x7)
+// CHECK: Section: foo (0x8)
diff --git a/test/MC/ELF/section-sym2.s b/test/MC/ELF/section-sym2.s
index acdb7d9547d0..f62e3f9f8a30 100644
--- a/test/MC/ELF/section-sym2.s
+++ b/test/MC/ELF/section-sym2.s
@@ -6,7 +6,7 @@ mov .rodata, %rsi
 .section .rodata
 
 // CHECK:Relocations [
-// CHECK:  Section (2) .rela.text {
+// CHECK:  Section {{.*}} .rela.text {
 // CHECK:    Relocation {
 // CHECK:      Offset: 0x4
 // CHECK:      Type: R_X86_64_32S (11)
diff --git a/test/MC/ELF/section-unique-err1.s b/test/MC/ELF/section-unique-err1.s
new file mode 100644
index 000000000000..3a997d177667
--- /dev/null
+++ b/test/MC/ELF/section-unique-err1.s
@@ -0,0 +1,5 @@
+// RUN: not llvm-mc -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
+
+// CHECK:  error: expected absolute expression
+
+        .section	.text,"ax",@progbits,unique, "abc"
diff --git a/test/MC/ELF/section-unique-err2.s b/test/MC/ELF/section-unique-err2.s
new file mode 100644
index 000000000000..7b7cd5f79d9d
--- /dev/null
+++ b/test/MC/ELF/section-unique-err2.s
@@ -0,0 +1,5 @@
+// RUN: not llvm-mc -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
+
+// CHECK:  error: unique id must be positive
+
+        .section	.text,"ax",@progbits,unique, -1
diff --git a/test/MC/ELF/section-unique-err3.s b/test/MC/ELF/section-unique-err3.s
new file mode 100644
index 000000000000..bbccd24b4afd
--- /dev/null
+++ b/test/MC/ELF/section-unique-err3.s
@@ -0,0 +1,5 @@
+// RUN: not llvm-mc -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
+
+// CHECK:  error: unique id is too large
+
+        .section	.text,"ax",@progbits,unique, 4294967295
diff --git a/test/MC/ELF/section-unique-err4.s b/test/MC/ELF/section-unique-err4.s
new file mode 100644
index 000000000000..3c82682e15aa
--- /dev/null
+++ b/test/MC/ELF/section-unique-err4.s
@@ -0,0 +1,5 @@
+// RUN: not llvm-mc -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
+
+// CHECK:  error: expected commma
+
+        .section	.text,"ax",@progbits,unique 1
diff --git a/test/MC/ELF/section-unique.s b/test/MC/ELF/section-unique.s
new file mode 100644
index 000000000000..bd15148f6d83
--- /dev/null
+++ b/test/MC/ELF/section-unique.s
@@ -0,0 +1,39 @@
+// RUN: llvm-mc -triple x86_64-pc-linux-gnu %s -o - | FileCheck %s
+// RUN: llvm-mc -triple x86_64-pc-linux-gnu %s -filetype=obj -o - | llvm-readobj -t | FileCheck %s --check-prefix=OBJ
+
+	.section	.text,"ax",@progbits,unique, 4294967293
+        .globl	f
+f:
+        nop
+
+	.section	.text,"ax",@progbits,unique, 4294967294
+        .globl	g
+g:
+        nop
+
+// test that f and g are in different sections.
+
+// CHECK: .section	.text,"ax",@progbits,unique,4294967293
+// CHECK: f:
+
+// CHECK: .section	.text,"ax",@progbits,unique,4294967294
+// CHECK: g:
+
+// OBJ: Symbol {
+// OBJ:   Name:    f
+// OBJ:   Value:   0x0
+// OBJ:   Size:    0
+// OBJ:   Binding: Global
+// OBJ:   Type:    None
+// OBJ:   Other:   0
+// OBJ:   Section: .text (0x5)
+// OBJ: }
+// OBJ: Symbol {
+// OBJ:   Name:    g
+// OBJ:   Value:   0x0
+// OBJ:   Size:    0
+// OBJ:   Binding: Global
+// OBJ:   Type:    None
+// OBJ:   Other:   0
+// OBJ:   Section: .text (0x6)
+// OBJ: }
diff --git a/test/MC/ELF/section.s b/test/MC/ELF/section.s
index 7dc23c2e596a..ab3fe0387400 100644
--- a/test/MC/ELF/section.s
+++ b/test/MC/ELF/section.s
@@ -7,10 +7,10 @@
 .section	.note.GNU-,"",@progbits
 .section	-.note.GNU,"","progbits"
 
-// CHECK: Name: .note.GNU-stack (56)
-// CHECK: Name: .note.GNU-stack2 (153)
-// CHECK: Name: .note.GNU- (170)
-// CHECK: Name: -.note.GNU (142)
+// CHECK: Name: .note.GNU-stack
+// CHECK: Name: .note.GNU-stack2
+// CHECK: Name: .note.GNU-
+// CHECK: Name: -.note.GNU
 
 // Test that the defaults are used
 
@@ -27,7 +27,7 @@
 // CHECK-NEXT:       SHF_EXECINSTR
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x50
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Link: 0
 // CHECK-NEXT:     Info: 0
@@ -35,7 +35,7 @@
 // CHECK-NEXT:     EntrySize: 0
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section {
-// CHECK-NEXT:     Index: 11
+// CHECK-NEXT:     Index:
 // CHECK-NEXT:     Name: .fini
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
@@ -43,7 +43,7 @@
 // CHECK-NEXT:       SHF_EXECINSTR
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x50
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Link: 0
 // CHECK-NEXT:     Info: 0
@@ -51,14 +51,14 @@
 // CHECK-NEXT:     EntrySize: 0
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section {
-// CHECK-NEXT:     Index: 12
+// CHECK-NEXT:     Index:
 // CHECK-NEXT:     Name: .rodata
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x50
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Link: 0
 // CHECK-NEXT:     Info: 0
@@ -66,13 +66,13 @@
 // CHECK-NEXT:     EntrySize: 0
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section {
-// CHECK-NEXT:     Index: 13
+// CHECK-NEXT:     Index:
 // CHECK-NEXT:     Name: zed
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x50
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Link: 0
 // CHECK-NEXT:     Info: 0
@@ -87,7 +87,7 @@
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x50
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Link: 0
 // CHECK-NEXT:     Info: 0
@@ -112,7 +112,7 @@ bar:
 // CHECK-NEXT:       SHF_ALLOC
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
-// CHECK-NEXT:     Offset: 0x50
+// CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Link: 0
 // CHECK-NEXT:     Info: 0
@@ -129,7 +129,7 @@ bar:
 // CHECK-NEXT:     SHF_EXCLUDE (0x80000000)
 // CHECK-NEXT:   ]
 // CHECK-NEXT:   Address: 0x0
-// CHECK-NEXT:   Offset: 0x50
+// CHECK-NEXT:   Offset:
 // CHECK-NEXT:   Size: 0
 // CHECK-NEXT:   Link: 0
 // CHECK-NEXT:   Info: 0
@@ -142,6 +142,6 @@ bar:
 .section "foo"
 
 // CHECK:        Section {
-// CHECK:          Name: bar-"foo" (181)
+// CHECK:          Name: bar-"foo"
 // CHECK:        Section {
-// CHECK:          Name: foo (52)
+// CHECK:          Name: foo
diff --git a/test/MC/ELF/size.s b/test/MC/ELF/size.s
new file mode 100644
index 000000000000..7bbf66163226
--- /dev/null
+++ b/test/MC/ELF/size.s
@@ -0,0 +1,15 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux < %s | llvm-readobj -t | FileCheck %s
+
+foo:
+bar = .
+	.size	foo, . - bar + 42
+
+// CHECK:       Symbol {
+// CHECK:         Name: foo
+// CHECK-NEXT:    Value: 0x0
+// CHECK-NEXT:    Size: 42
+// CHECK-NEXT:    Binding: Local
+// CHECK-NEXT:    Type: None
+// CHECK-NEXT:    Other: 0
+// CHECK-NEXT:    Section: .text
+// CHECK-NEXT:  }
diff --git a/test/MC/ELF/strtab-suffix-opt.s b/test/MC/ELF/strtab-suffix-opt.s
index eb5da8a01552..052465644603 100644
--- a/test/MC/ELF/strtab-suffix-opt.s
+++ b/test/MC/ELF/strtab-suffix-opt.s
@@ -16,6 +16,6 @@ foobar:
 .Ltmp3:
 	.size	foobar, .Ltmp3-foobar
 
-// CHECK:     Name: foobar (1)
-// CHECK:     Name: bar (4)
-// CHECK:     Name: foo (8)
+// CHECK:     Name: foobar (16)
+// CHECK:     Name: bar (19)
+// CHECK:     Name: foo (23)
diff --git a/test/MC/ELF/symver-msvc.s b/test/MC/ELF/symver-msvc.s
new file mode 100644
index 000000000000..354ece140be8
--- /dev/null
+++ b/test/MC/ELF/symver-msvc.s
@@ -0,0 +1,59 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-windows-elf %s -o - | llvm-readobj -r -t | FileCheck %s
+
+// Verify that MSVC C++ mangled symbols are not affected by the ELF
+// GNU-style symbol versioning. The ELF format is used on Windows by
+// the MCJIT execution engine.
+
+        .long "??_R0?AVexception@std@@@8"
+        .long "@??_R0?AVinvalid_argument@std@@@8"
+        .long "__imp_??_R0?AVlogic_error@std@@@8"
+        .long "__imp_@??_R0PAVexception@std@@@8"
+
+
+// CHECK:       Relocations [
+// CHECK-NEXT:    Section {{.*}} .rela.text {
+// CHECK-NEXT:      0x0 R_X86_64_32 ??_R0?AVexception@std@@@8 0x0
+// CHECK-NEXT:      0x4 R_X86_64_32 @??_R0?AVinvalid_argument@std@@@8 0x0
+// CHECK-NEXT:      0x8 R_X86_64_32 __imp_??_R0?AVlogic_error@std@@@8 0x0
+// CHECK-NEXT:      0xC R_X86_64_32 __imp_@??_R0PAVexception@std@@@8 0x0
+// CHECK-NEXT:    }
+// CHECK-NEXT:  ]
+
+// CHECK:       Symbols [
+// CHECK:         Symbol {
+// CHECK:           Name: ??_R0?AVexception@std@@@8
+// CHECK-NEXT:      Value: 0x0
+// CHECK-NEXT:      Size: 0
+// CHECK-NEXT:      Binding: Global (0x1)
+// CHECK-NEXT:      Type: None (0x0)
+// CHECK-NEXT:      Other: 0
+// CHECK-NEXT:      Section: Undefined (0x0)
+// CHECK-NEXT:    }
+// CHECK-NEXT:    Symbol {
+// CHECK-NEXT:      Name: @??_R0?AVinvalid_argument@std@@@8
+// CHECK-NEXT:      Value: 0x0
+// CHECK-NEXT:      Size: 0
+// CHECK-NEXT:      Binding: Global (0x1)
+// CHECK-NEXT:      Type: None (0x0)
+// CHECK-NEXT:      Other: 0
+// CHECK-NEXT:      Section: Undefined (0x0)
+// CHECK-NEXT:    }
+// CHECK-NEXT:    Symbol {
+// CHECK-NEXT:      Name: __imp_??_R0?AVlogic_error@std@@@8
+// CHECK-NEXT:      Value: 0x0
+// CHECK-NEXT:      Size: 0
+// CHECK-NEXT:      Binding: Global (0x1)
+// CHECK-NEXT:      Type: None (0x0)
+// CHECK-NEXT:      Other: 0
+// CHECK-NEXT:      Section: Undefined (0x0)
+// CHECK-NEXT:    }
+// CHECK-NEXT:    Symbol {
+// CHECK-NEXT:      Name: __imp_@??_R0PAVexception@std@@@8
+// CHECK-NEXT:      Value: 0x0
+// CHECK-NEXT:      Size: 0
+// CHECK-NEXT:      Binding: Global (0x1)
+// CHECK-NEXT:      Type: None (0x0)
+// CHECK-NEXT:      Other: 0
+// CHECK-NEXT:      Section: Undefined (0x0)
+// CHECK-NEXT:    }
+// CHECK-NEXT:  ]
diff --git a/test/MC/ELF/symver.s b/test/MC/ELF/symver.s
index 6e5825f24313..80d71fd0e069 100644
--- a/test/MC/ELF/symver.s
+++ b/test/MC/ELF/symver.s
@@ -22,7 +22,7 @@ defined3:
 global1:
 
 // CHECK:      Relocations [
-// CHECK-NEXT:   Section (2) .rela.text {
+// CHECK-NEXT:   Section {{.*}} .rela.text {
 // CHECK-NEXT:     0x0 R_X86_64_32 .text 0x0
 // CHECK-NEXT:     0x4 R_X86_64_32 bar2@zed 0x0
 // CHECK-NEXT:     0x8 R_X86_64_32 .text 0x0
diff --git a/test/MC/ELF/tls.s b/test/MC/ELF/tls.s
index 79865cd17be1..940827bf7c59 100644
--- a/test/MC/ELF/tls.s
+++ b/test/MC/ELF/tls.s
@@ -19,7 +19,7 @@ foobar:
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: TLS
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .zed (0x5)
+// CHECK-NEXT:     Section: .zed
 // CHECK-NEXT:   }
 
 // CHECK:        Symbol {
diff --git a/test/MC/ELF/type-propagate.s b/test/MC/ELF/type-propagate.s
index 15d05af7f2fa..ecfab6dbcdaf 100644
--- a/test/MC/ELF/type-propagate.s
+++ b/test/MC/ELF/type-propagate.s
@@ -36,7 +36,7 @@ sym10:
 // CHECK-NEXT:    Binding: Local (0x0)
 // CHECK-NEXT:    Type: Object (0x1)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym02
@@ -45,7 +45,7 @@ sym10:
 // CHECK-NEXT:    Binding: Local (0x0)
 // CHECK-NEXT:    Type: Function (0x2)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym03
@@ -54,7 +54,7 @@ sym10:
 // CHECK-NEXT:    Binding: Local (0x0)
 // CHECK-NEXT:    Type: Function (0x2)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym04
@@ -63,7 +63,7 @@ sym10:
 // CHECK-NEXT:    Binding: Local (0x0)
 // CHECK-NEXT:    Type: Object (0x1)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym05
@@ -75,7 +75,7 @@ sym10:
 // CHECK-NEXT:    Type: Object (0x1)
 
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym06
@@ -102,7 +102,7 @@ sym10:
 // CHECK-NEXT:    Binding: Local (0x0)
 // CHECK-NEXT:    Type: Function (0x2)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym09
@@ -114,7 +114,7 @@ sym10:
 // CHECK-NEXT:    Type: Function (0x2)
 
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym10
@@ -123,7 +123,7 @@ sym10:
 // CHECK-NEXT:    Binding: Local (0x0)
 // CHECK-NEXT:    Type: Function (0x2)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym11
@@ -135,7 +135,7 @@ sym10:
 // CHECK-NEXT:    Type: Function (0x2)
 
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym12
@@ -147,5 +147,5 @@ sym10:
 // CHECK-NEXT:    Type: Function (0x2)
 
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
diff --git a/test/MC/ELF/type.s b/test/MC/ELF/type.s
index c82d3006cfe0..a9cc3ebc777d 100644
--- a/test/MC/ELF/type.s
+++ b/test/MC/ELF/type.s
@@ -9,8 +9,8 @@ foo:
         .type bar,@object
 bar:
 
-// Test that gnu_unique_object is accepted.
         .type zed,@gnu_unique_object
+zed:
 
 obj:
         .global obj
@@ -137,7 +137,7 @@ alias12:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: Object
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: foo
@@ -146,7 +146,7 @@ alias12:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: Function
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: func
@@ -155,7 +155,7 @@ alias12:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: Function
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: ifunc
@@ -164,7 +164,7 @@ alias12:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: GNU_IFunc
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: obj
@@ -173,7 +173,7 @@ alias12:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: Object
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym1
@@ -182,7 +182,7 @@ alias12:
 // CHECK-NEXT:    Binding: Global (0x1)
 // CHECK-NEXT:    Type: GNU_IFunc (0xA)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym10
@@ -191,7 +191,7 @@ alias12:
 // CHECK-NEXT:    Binding: Global (0x1)
 // CHECK-NEXT:    Type: TLS (0x6)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym11
@@ -200,7 +200,7 @@ alias12:
 // CHECK-NEXT:    Binding: Global (0x1)
 // CHECK-NEXT:    Type: TLS (0x6)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym12
@@ -209,7 +209,7 @@ alias12:
 // CHECK-NEXT:    Binding: Global (0x1)
 // CHECK-NEXT:    Type: TLS (0x6)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym2
@@ -218,7 +218,7 @@ alias12:
 // CHECK-NEXT:    Binding: Global (0x1)
 // CHECK-NEXT:    Type: GNU_IFunc (0xA)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym3
@@ -227,7 +227,7 @@ alias12:
 // CHECK-NEXT:    Binding: Global (0x1)
 // CHECK-NEXT:    Type: GNU_IFunc (0xA)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym4
@@ -236,7 +236,7 @@ alias12:
 // CHECK-NEXT:    Binding: Global (0x1)
 // CHECK-NEXT:    Type: Function (0x2)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym5
@@ -245,7 +245,7 @@ alias12:
 // CHECK-NEXT:    Binding: Global (0x1)
 // CHECK-NEXT:    Type: Function (0x2)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym6
@@ -254,7 +254,7 @@ alias12:
 // CHECK-NEXT:    Binding: Global (0x1)
 // CHECK-NEXT:    Type: Object (0x1)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym7
@@ -263,7 +263,7 @@ alias12:
 // CHECK-NEXT:    Binding: Global (0x1)
 // CHECK-NEXT:    Type: GNU_IFunc (0xA)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym8
@@ -272,7 +272,7 @@ alias12:
 // CHECK-NEXT:    Binding: Global (0x1)
 // CHECK-NEXT:    Type: Function (0x2)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: sym9
@@ -281,7 +281,7 @@ alias12:
 // CHECK-NEXT:    Binding: Global (0x1)
 // CHECK-NEXT:    Type: TLS (0x6)
 // CHECK-NEXT:    Other: 0
-// CHECK-NEXT:    Section: .text (0x1)
+// CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: tls
@@ -290,7 +290,7 @@ alias12:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: TLS
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: tls_quoted
@@ -299,7 +299,7 @@ alias12:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: TLS
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: tls_upper_case
@@ -308,5 +308,15 @@ alias12:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: TLS
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
+// CHECK-NEXT:   Symbol {
+// CHECK-NEXT:     Name: zed
+// CHECK-NEXT:     Value: 0x0
+// CHECK-NEXT:     Size: 0
+// CHECK-NEXT:     Binding: Unique (0xA)
+// CHECK-NEXT:     Type: Object (0x1)
+// CHECK-NEXT:     Other: 0
+// CHECK-NEXT:     Section: .text
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
diff --git a/test/MC/ELF/weak-diff.s b/test/MC/ELF/weak-diff.s
new file mode 100644
index 000000000000..ded89b8f8338
--- /dev/null
+++ b/test/MC/ELF/weak-diff.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu < %s | llvm-readobj -r | FileCheck %s
+
+// CHECK:      Relocations [
+// CHECK-NEXT:   Section ({{.*}}) .rela.text {
+// CHECK-NEXT:     0x1D R_X86_64_PC32 f2 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
+
+.weak f
+.weak g
+f:
+    nop
+g:
+    nop
+
+.quad g - f
+
+
+.weak f2
+f2:
+    nop
+g2:
+    nop
+.quad g2 - f2
+.quad f2 - g2
+call f2
diff --git a/test/MC/ELF/weakref-reloc.s b/test/MC/ELF/weakref-reloc.s
index 582c6946c609..484167f0434e 100644
--- a/test/MC/ELF/weakref-reloc.s
+++ b/test/MC/ELF/weakref-reloc.s
@@ -16,7 +16,7 @@
 
 // CHECK:      Symbols [
 // CHECK:        Symbol {
-// CHECK:          Name: _GLOBAL_OFFSET_TABLE_ (9)
+// CHECK:          Name: _GLOBAL_OFFSET_TABLE_
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
@@ -25,7 +25,7 @@
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: foo (1)
+// CHECK-NEXT:     Name: foo
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Weak
@@ -34,7 +34,7 @@
 // CHECK-NEXT:     Section: Undefined (0x0)
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
-// CHECK-NEXT:     Name: zed (5)
+// CHECK-NEXT:     Name: zed
 // CHECK-NEXT:     Value: 0x0
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Global
diff --git a/test/MC/ELF/weakref.s b/test/MC/ELF/weakref.s
index 2288264bd6c7..d263af31a0df 100644
--- a/test/MC/ELF/weakref.s
+++ b/test/MC/ELF/weakref.s
@@ -86,7 +86,7 @@ bar15:
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: bar7
@@ -95,7 +95,7 @@ bar15:
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: bar8
@@ -104,7 +104,7 @@ bar15:
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: bar9
@@ -113,7 +113,7 @@ bar15:
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: .text
@@ -122,7 +122,7 @@ bar15:
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: Section
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: .data
@@ -131,7 +131,7 @@ bar15:
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: Section
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .data (0x3)
+// CHECK-NEXT:     Section: .data
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: .bss
@@ -140,7 +140,7 @@ bar15:
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: Section
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .bss (0x4)
+// CHECK-NEXT:     Section: .bss
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: bar10
@@ -149,7 +149,7 @@ bar15:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: bar11
@@ -158,7 +158,7 @@ bar15:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: bar12
@@ -167,7 +167,7 @@ bar15:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: bar13
@@ -176,7 +176,7 @@ bar15:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: bar14
@@ -185,7 +185,7 @@ bar15:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: bar15
@@ -194,7 +194,7 @@ bar15:
 // CHECK-NEXT:     Binding: Global
 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other: 0
-// CHECK-NEXT:     Section: .text (0x1)
+// CHECK-NEXT:     Section: .text
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Symbol {
 // CHECK-NEXT:     Name: bar2
diff --git a/test/MC/Hexagon/inst_select.ll b/test/MC/Hexagon/inst_select.ll
index 7e88c65a8185..29a2db0723bd 100644
--- a/test/MC/Hexagon/inst_select.ll
+++ b/test/MC/Hexagon/inst_select.ll
@@ -7,4 +7,4 @@ define i32 @foo (i1 %a, i32 %b, i32 %c)
   ret i32 %1
 }
 
-; CHECK:  0000 00400085 004201f4 00c09f52
+; CHECK:  0000 00400085 00600174 00608274 00c09f52
diff --git a/test/MC/MachO/AArch64/classrefs.s b/test/MC/MachO/AArch64/classrefs.s
new file mode 100644
index 000000000000..5edc82ca0b12
--- /dev/null
+++ b/test/MC/MachO/AArch64/classrefs.s
@@ -0,0 +1,25 @@
+; RUN: llvm-mc -triple arm64-apple-darwin10 %s -filetype=obj -o - | llvm-readobj -r --expand-relocs | FileCheck %s
+
+; Test that we produce an external relocation with Lbar. We could also produce
+; an internal relocation. We just have to be careful to not use another symbol.
+
+// CHECK:      Relocations [
+// CHECK-NEXT:   Section __data {
+// CHECK-NEXT:     Relocation {
+// CHECK-NEXT:       Offset: 0x0
+// CHECK-NEXT:       PCRel: 0
+// CHECK-NEXT:       Length: 3
+// CHECK-NEXT:       Extern: 1
+// CHECK-NEXT:       Type: ARM64_RELOC_UNSIGNED (0)
+// CHECK-NEXT:       Symbol: Lbar
+// CHECK-NEXT:       Scattered: 0
+// CHECK-NEXT:     }
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
+
+        .section        __DATA,__objc_classrefs,regular,no_dead_strip
+Lbar:
+
+        .section        __DATA,__data
+        .quad   Lbar
+
diff --git a/test/MC/MachO/AArch64/cstexpr-gotpcrel.ll b/test/MC/MachO/AArch64/cstexpr-gotpcrel.ll
new file mode 100644
index 000000000000..b52a5abecab2
--- /dev/null
+++ b/test/MC/MachO/AArch64/cstexpr-gotpcrel.ll
@@ -0,0 +1,92 @@
+; RUN: llc -mtriple=arm64-apple-darwin %s -o - | FileCheck %s
+
+; GOT equivalent globals references can be replaced by the GOT entry of the
+; final symbol instead.
+
+%struct.data = type { i32, %struct.anon }
+%struct.anon = type { i32, i32 }
+
+@localfoo = global i32 42
+@localgotequiv = private unnamed_addr constant i32* @localfoo
+
+@extfoo = external global i32
+@extgotequiv = private unnamed_addr constant i32* @extfoo
+
+; Don't replace GOT equivalent usage within instructions and emit the GOT
+; equivalent since it can't be replaced by the GOT entry. @bargotequiv is
+; used by an instruction inside @t0.
+;
+; CHECK: l_bargotequiv:
+; CHECK-NEXT:  .quad   _extbar
+@extbar = external global i32
+@bargotequiv = private unnamed_addr constant i32* @extbar
+
+@table = global [4 x %struct.data] [
+; CHECK-LABEL: _table
+  %struct.data { i32 1, %struct.anon { i32 2, i32 3 } },
+; Test GOT equivalent usage inside nested constant arrays.
+
+; CHECK: .long   5
+; CHECK-NOT: .long   _localgotequiv-(_table+20)
+; CHECK-NEXT: Ltmp1:
+; CHECK-NEXT: .long _localfoo@GOT-Ltmp1
+  %struct.data { i32 4, %struct.anon { i32 5,
+    i32 trunc (i64 sub (i64 ptrtoint (i32** @localgotequiv to i64),
+                        i64 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i64 1, i32 1, i32 1) to i64))
+                        to i32)}
+  },
+
+; CHECK: .long   5
+; CHECK-NOT: _extgotequiv-(_table+32)
+; CHECK-NEXT: Ltmp2:
+; CHECK-NEXT: _extfoo@GOT-Ltmp2
+  %struct.data { i32 4, %struct.anon { i32 5,
+    i32 trunc (i64 sub (i64 ptrtoint (i32** @extgotequiv to i64),
+                        i64 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i64 2, i32 1, i32 1) to i64))
+                        to i32)}
+  },
+; Test support for arbitrary constants into the GOTPCREL offset, which is
+; supported on x86-64 but not on ARM64
+
+; CHECK: .long   5
+; CHECK-NEXT: .long (l_extgotequiv-(_table+44))+24
+  %struct.data { i32 4, %struct.anon { i32 5,
+    i32 add (i32 trunc (i64 sub (i64 ptrtoint (i32** @extgotequiv to i64),
+                                 i64 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i64 3, i32 1, i32 1) to i64))
+                                 to i32), i32 24)}
+  }
+], align 16
+
+; Test multiple uses of GOT equivalents.
+
+; CHECK-LABEL: _delta
+; CHECK: Ltmp3:
+; CHECK-NEXT:  .long _extfoo@GOT-Ltmp3
+@delta = global i32 trunc (i64 sub (i64 ptrtoint (i32** @extgotequiv to i64),
+                                    i64 ptrtoint (i32* @delta to i64))
+                           to i32)
+
+; CHECK-LABEL: _deltaplus:
+; CHECK: .long  (l_localgotequiv-_deltaplus)+55
+@deltaplus = global i32 add (i32 trunc (i64 sub (i64 ptrtoint (i32** @localgotequiv to i64),
+                                        i64 ptrtoint (i32* @deltaplus to i64))
+                                        to i32), i32 55)
+
+define i32 @t0(i32 %a) {
+  %x = add i32 trunc (i64 sub (i64 ptrtoint (i32** @bargotequiv to i64),
+                               i64 ptrtoint (i32 (i32)* @t0 to i64))
+                           to i32), %a
+  ret i32 %x
+}
+
+; Check that these got equivalent symbols are emitted on ARM64. Since ARM64
+; does not support encoding an extra offset with @GOT, we still need to emit the
+; equivalents for use by such IR constructs. Check them at the end of the test
+; since they will start out as GOT equivalent candidates, but they are actually
+; needed and are therefore emitted at the end.
+
+; CHECK-LABEL: l_localgotequiv:
+; CHECK-NEXT: .quad   _localfoo
+
+; CHECK-LABEL: l_extgotequiv:
+; CHECK-NEXT: .quad   _extfoo
diff --git a/test/MC/MachO/AArch64/ld64-workaround.s b/test/MC/MachO/AArch64/ld64-workaround.s
new file mode 100644
index 000000000000..a33cacc075bd
--- /dev/null
+++ b/test/MC/MachO/AArch64/ld64-workaround.s
@@ -0,0 +1,68 @@
+; RUN: llvm-mc -triple arm64-apple-darwin10 %s -filetype=obj -o - | llvm-readobj -r --expand-relocs | FileCheck %s
+
+; Test that we produce an external relocation. This is a known and temporary bug
+; in ld64, where it mishandles pointer-sized internal relocations. We should be
+; able to remove this entirely soon.
+
+// CHECK:      Relocations [
+// CHECK-NEXT:   Section __data {
+// CHECK-NEXT:     Relocation {
+// CHECK-NEXT:       Offset: 0x18
+// CHECK-NEXT:       PCRel: 0
+// CHECK-NEXT:       Length: 3
+// CHECK-NEXT:       Extern: 1
+// CHECK-NEXT:       Type: ARM64_RELOC_UNSIGNED (0)
+// CHECK-NEXT:       Symbol: Llit16
+// CHECK-NEXT:       Scattered: 0
+// CHECK-NEXT:     }
+// CHECK-NEXT:     Relocation {
+// CHECK-NEXT:       Offset: 0x10
+// CHECK-NEXT:       PCRel: 0
+// CHECK-NEXT:       Length: 3
+// CHECK-NEXT:       Extern: 1
+// CHECK-NEXT:       Type: ARM64_RELOC_UNSIGNED (0)
+// CHECK-NEXT:       Symbol: Llit8
+// CHECK-NEXT:       Scattered: 0
+// CHECK-NEXT:     }
+// CHECK-NEXT:     Relocation {
+// CHECK-NEXT:       Offset: 0x8
+// CHECK-NEXT:       PCRel: 0
+// CHECK-NEXT:       Length: 3
+// CHECK-NEXT:       Extern: 1
+// CHECK-NEXT:       Type: ARM64_RELOC_UNSIGNED (0)
+// CHECK-NEXT:       Symbol: Llit4
+// CHECK-NEXT:       Scattered: 0
+// CHECK-NEXT:     }
+// CHECK-NEXT:     Relocation {
+// CHECK-NEXT:       Offset: 0x0
+// CHECK-NEXT:       PCRel: 0
+// CHECK-NEXT:       Length: 3
+// CHECK-NEXT:       Extern: 1
+// CHECK-NEXT:       Type: ARM64_RELOC_UNSIGNED (0)
+// CHECK-NEXT:       Symbol: Lcfstring
+// CHECK-NEXT:       Scattered: 0
+// CHECK-NEXT:     }
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
+
+        .section        __DATA,__cfstring
+Lcfstring:
+
+        .section        __DATA,__literal4,4byte_literals
+Llit4:
+        .word 42
+
+        .section        __DATA,__literal8,8byte_literals
+Llit8:
+        .quad 42
+
+        .section        __DATA,__literal16,16byte_literals
+Llit16:
+        .quad 42
+        .quad 42
+
+        .section        __DATA,__data
+        .quad   Lcfstring
+        .quad   Llit4
+        .quad   Llit8
+        .quad   Llit16
diff --git a/test/MC/MachO/AArch64/mergeable.s b/test/MC/MachO/AArch64/mergeable.s
new file mode 100644
index 000000000000..fcd839527568
--- /dev/null
+++ b/test/MC/MachO/AArch64/mergeable.s
@@ -0,0 +1,61 @@
+// RUN: llvm-mc -triple aarch64-apple-darwin14 %s -filetype=obj -o - | llvm-readobj -r --expand-relocs | FileCheck %s
+// FIXME: the final relocation should be internal, but the linker doesn't
+// currently handle the it correctly.
+
+// Test that we "S + K" produce a relocation with a symbol, but just S produces
+// a relocation with the section.
+
+	.section	__TEXT,__literal4,4byte_literals
+L0:
+	.long	42
+
+	.section	__TEXT,__cstring,cstring_literals
+L1:
+	.asciz	"42"
+
+	.section	__DATA,__data
+	.quad	L0
+	.quad	L0 + 1
+	.quad	L1
+	.quad	L1 + 1
+
+// CHECK:      Relocations [
+// CHECK-NEXT:   Section __data {
+// CHECK-NEXT:     Relocation {
+// CHECK-NEXT:       Offset: 0x18
+// CHECK-NEXT:       PCRel: 0
+// CHECK-NEXT:       Length: 3
+// CHECK-NEXT:       Extern: 1
+// CHECK-NEXT:       Type: ARM64_RELOC_UNSIGNED (0)
+// CHECK-NEXT:       Symbol: L1
+// CHECK-NEXT:       Scattered: 0
+// CHECK-NEXT:     }
+// CHECK-NEXT:     Relocation {
+// CHECK-NEXT:       Offset: 0x10
+// CHECK-NEXT:       PCRel: 0
+// CHECK-NEXT:       Length: 3
+// CHECK-NEXT:       Extern: 1
+// CHECK-NEXT:       Type: ARM64_RELOC_UNSIGNED (0)
+// CHECK-NEXT:       Symbol: L1
+// CHECK-NEXT:       Scattered: 0
+// CHECK-NEXT:     }
+// CHECK-NEXT:     Relocation {
+// CHECK-NEXT:       Offset: 0x8
+// CHECK-NEXT:       PCRel: 0
+// CHECK-NEXT:       Length: 3
+// CHECK-NEXT:       Extern: 1
+// CHECK-NEXT:       Type: ARM64_RELOC_UNSIGNED (0)
+// CHECK-NEXT:       Symbol: L0
+// CHECK-NEXT:       Scattered: 0
+// CHECK-NEXT:     }
+// CHECK-NEXT:     Relocation {
+// CHECK-NEXT:       Offset: 0x0
+// CHECK-NEXT:       PCRel: 0
+// CHECK-NEXT:       Length: 3
+// CHECK-NEXT:       Extern: 1
+// CHECK-NEXT:       Type: ARM64_RELOC_UNSIGNED (0)
+// CHECK-NEXT:       Symbol: L0
+// CHECK-NEXT:       Scattered: 0
+// CHECK-NEXT:     }
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
diff --git a/test/MC/MachO/ARM/aliased-symbols.s b/test/MC/MachO/ARM/aliased-symbols.s
index e87b81c6a150..cc2e200ce8ad 100644
--- a/test/MC/MachO/ARM/aliased-symbols.s
+++ b/test/MC/MachO/ARM/aliased-symbols.s
@@ -45,9 +45,9 @@ Ltmp0:
 // CHECK-NEXT:   Value: 0x[[DEFINED_EARLY]]
 // CHECK-NEXT: }
 
-        // defined_late was defined. Just after defined_early.
+        // alias_to_late was an alias to defined_late. But we can resolve it.
 // CHECK: Symbol {
-// CHECK-NEXT:   Name: defined_late
+// CHECK-NEXT:   Name: alias_to_late
 // CHECK-NEXT:   Type: Section (0xE)
 // CHECK-NEXT:   Section: __data (0x2)
 // CHECK-NEXT:   RefType: UndefinedNonLazy (0x0)
@@ -56,9 +56,9 @@ Ltmp0:
 // CHECK-NEXT:   Value: 0x[[DEFINED_LATE:[0-9A-F]+]]
 // CHECK-NEXT: }
 
-        // alias_to_late was an alias to defined_late. But we can resolve it.
+        // defined_late was defined. Just after defined_early.
 // CHECK: Symbol {
-// CHECK-NEXT:   Name: alias_to_late
+// CHECK-NEXT:   Name: defined_late
 // CHECK-NEXT:   Type: Section (0xE)
 // CHECK-NEXT:   Section: __data (0x2)
 // CHECK-NEXT:   RefType: UndefinedNonLazy (0x0)
@@ -72,7 +72,7 @@ Ltmp0:
 // CHECK: Symbol {
 // CHECK-NEXT:   Name: alias_to_local (42)
 // CHECK-NEXT:   Type: Section (0xE)
-// CHECK-NEXT:   Section:  (0x0)
+// CHECK-NEXT:   Section: __data (0x2)
 // CHECK-NEXT:   RefType: UndefinedNonLazy (0x0)
 // CHECK-NEXT:   Flags [ (0x0)
 // CHECK-NEXT:   ]
diff --git a/test/MC/MachO/ARM/cstexpr-gotpcrel.ll b/test/MC/MachO/ARM/cstexpr-gotpcrel.ll
new file mode 100644
index 000000000000..95d830ccfaa8
--- /dev/null
+++ b/test/MC/MachO/ARM/cstexpr-gotpcrel.ll
@@ -0,0 +1,74 @@
+; RUN: llc -mtriple=arm-apple-darwin %s -o %t
+; RUN:  FileCheck %s < %t
+; RUN:  FileCheck %s -check-prefix=GOT-EQUIV < %t
+
+; GOT equivalent globals references can be replaced by the GOT entry of the
+; final symbol instead.
+
+%struct.data = type { i32, %struct.anon }
+%struct.anon = type { i32, i32 }
+
+; Check that these got equivalent symbols are never emitted or used
+; GOT-EQUIV-NOT: _localgotequiv
+; GOT-EQUIV-NOT: _extgotequiv
+@localfoo = global i32 42
+@localgotequiv = private unnamed_addr constant i32* @localfoo
+
+@extfoo = external global i32
+@extgotequiv = private unnamed_addr constant i32* @extfoo
+
+; Don't replace GOT equivalent usage within instructions and emit the GOT
+; equivalent since it can't be replaced by the GOT entry. @bargotequiv is
+; used by an instruction inside @t0.
+;
+; CHECK: l_bargotequiv:
+; CHECK-NEXT:  .long   _extbar
+@extbar = external global i32
+@bargotequiv = private unnamed_addr constant i32* @extbar
+
+@table = global [4 x %struct.data] [
+; CHECK-LABEL: _table
+  %struct.data { i32 1, %struct.anon { i32 2, i32 3 } },
+; Test GOT equivalent usage inside nested constant arrays.
+; CHECK: .long   5
+; CHECK-NOT: l_localgotequiv-(_table+20)
+; CHECK-NEXT: L_localfoo$non_lazy_ptr-(_table+20)
+  %struct.data { i32 4, %struct.anon { i32 5,
+    i32 sub (i32 ptrtoint (i32** @localgotequiv to i32),
+             i32 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i32 1, i32 1, i32 1) to i32))}
+  },
+; CHECK: .long   5
+; CHECK-NOT: l_extgotequiv-(_table+32)
+; CHECK-NEXT: L_extfoo$non_lazy_ptr-(_table+32)
+  %struct.data { i32 4, %struct.anon { i32 5,
+    i32 sub (i32 ptrtoint (i32** @extgotequiv to i32),
+             i32 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i32 2, i32 1, i32 1) to i32))}
+  },
+; Test support for arbitrary constants into the GOTPCREL offset
+; CHECK: .long   5
+; CHECK-NOT: (l_extgotequiv-(_table+44))+24
+; CHECK-NEXT: L_extfoo$non_lazy_ptr-(_table+20)
+  %struct.data { i32 4, %struct.anon { i32 5,
+    i32 add (i32 sub (i32 ptrtoint (i32** @extgotequiv to i32),
+                      i32 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i32 3, i32 1, i32 1) to i32)),
+                      i32 24)}
+  }
+], align 16
+
+; Test multiple uses of GOT equivalents.
+; CHECK-LABEL: _delta
+; CHECK: .long   L_extfoo$non_lazy_ptr-_delta
+@delta = global i32 sub (i32 ptrtoint (i32** @extgotequiv to i32),
+                         i32 ptrtoint (i32* @delta to i32))
+
+; CHECK-LABEL: _deltaplus:
+; CHECK: .long   L_localfoo$non_lazy_ptr-(_deltaplus-55)
+@deltaplus = global i32 add (i32 sub (i32 ptrtoint (i32** @localgotequiv to i32),
+                             i32 ptrtoint (i32* @deltaplus to i32)),
+                             i32 55)
+
+define i32 @t0(i32 %a) {
+  %x = add i32 sub (i32 ptrtoint (i32** @bargotequiv to i32),
+                    i32 ptrtoint (i32 (i32)* @t0 to i32)), %a
+  ret i32 %x
+}
diff --git a/test/MC/MachO/cstexpr-gotpcrel-32.ll b/test/MC/MachO/cstexpr-gotpcrel-32.ll
new file mode 100644
index 000000000000..8e00b4ace067
--- /dev/null
+++ b/test/MC/MachO/cstexpr-gotpcrel-32.ll
@@ -0,0 +1,74 @@
+; RUN: llc -mtriple=i386-apple-darwin %s -o %t
+; RUN:  FileCheck %s < %t
+; RUN:  FileCheck %s -check-prefix=GOT-EQUIV < %t
+
+; GOT equivalent globals references can be replaced by the GOT entry of the
+; final symbol instead.
+
+%struct.data = type { i32, %struct.anon }
+%struct.anon = type { i32, i32 }
+
+; Check that these got equivalent symbols are never emitted or used
+; GOT-EQUIV-NOT: _localgotequiv
+; GOT-EQUIV-NOT: _extgotequiv
+@localfoo = global i32 42
+@localgotequiv = private unnamed_addr constant i32* @localfoo
+
+@extfoo = external global i32
+@extgotequiv = private unnamed_addr constant i32* @extfoo
+
+; Don't replace GOT equivalent usage within instructions and emit the GOT
+; equivalent since it can't be replaced by the GOT entry. @bargotequiv is
+; used by an instruction inside @t0.
+;
+; CHECK: l_bargotequiv:
+; CHECK-NEXT:  .long   _extbar
+@extbar = external global i32
+@bargotequiv = private unnamed_addr constant i32* @extbar
+
+@table = global [4 x %struct.data] [
+; CHECK-LABEL: _table
+  %struct.data { i32 1, %struct.anon { i32 2, i32 3 } },
+; Test GOT equivalent usage inside nested constant arrays.
+; CHECK: .long   5
+; CHECK-NOT: l_localgotequiv-(_table+20)
+; CHECK-NEXT: L_localfoo$non_lazy_ptr-(_table+20)
+  %struct.data { i32 4, %struct.anon { i32 5,
+    i32 sub (i32 ptrtoint (i32** @localgotequiv to i32),
+             i32 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i32 1, i32 1, i32 1) to i32))}
+  },
+; CHECK: .long   5
+; CHECK-NOT: l_extgotequiv-(_table+32)
+; CHECK-NEXT: L_extfoo$non_lazy_ptr-(_table+32)
+  %struct.data { i32 4, %struct.anon { i32 5,
+    i32 sub (i32 ptrtoint (i32** @extgotequiv to i32),
+             i32 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i32 2, i32 1, i32 1) to i32))}
+  },
+; Test support for arbitrary constants into the GOTPCREL offset
+; CHECK: .long   5
+; CHECK-NOT: (l_extgotequiv-(_table+44))+24
+; CHECK-NEXT: L_extfoo$non_lazy_ptr-(_table+20)
+  %struct.data { i32 4, %struct.anon { i32 5,
+    i32 add (i32 sub (i32 ptrtoint (i32** @extgotequiv to i32),
+                      i32 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i32 3, i32 1, i32 1) to i32)),
+                      i32 24)}
+  }
+], align 16
+
+; Test multiple uses of GOT equivalents.
+; CHECK-LABEL: _delta
+; CHECK: .long   L_extfoo$non_lazy_ptr-_delta
+@delta = global i32 sub (i32 ptrtoint (i32** @extgotequiv to i32),
+                         i32 ptrtoint (i32* @delta to i32))
+
+; CHECK-LABEL: _deltaplus:
+; CHECK: .long   L_localfoo$non_lazy_ptr-(_deltaplus-55)
+@deltaplus = global i32 add (i32 sub (i32 ptrtoint (i32** @localgotequiv to i32),
+                             i32 ptrtoint (i32* @deltaplus to i32)),
+                             i32 55)
+
+define i32 @t0(i32 %a) {
+  %x = add i32 sub (i32 ptrtoint (i32** @bargotequiv to i32),
+                    i32 ptrtoint (i32 (i32)* @t0 to i32)), %a
+  ret i32 %x
+}
diff --git a/test/MC/MachO/cstexpr-gotpcrel-64.ll b/test/MC/MachO/cstexpr-gotpcrel-64.ll
new file mode 100644
index 000000000000..bf155647f12a
--- /dev/null
+++ b/test/MC/MachO/cstexpr-gotpcrel-64.ll
@@ -0,0 +1,86 @@
+; RUN: llc -mtriple=x86_64-apple-darwin %s -o %t
+; RUN:  FileCheck %s -check-prefix=X86 < %t
+; RUN:  FileCheck %s -check-prefix=X86-GOT-EQUIV < %t
+
+; GOT equivalent globals references can be replaced by the GOT entry of the
+; final symbol instead.
+
+%struct.data = type { i32, %struct.anon }
+%struct.anon = type { i32, i32 }
+
+; Check that these got equivalent symbols are never emitted.
+
+; X86-GOT-EQUIV-NOT: L_localgotequiv
+; X86-GOT-EQUIV-NOT: l_extgotequiv
+@localfoo = global i32 42
+@localgotequiv = private unnamed_addr constant i32* @localfoo
+
+@extfoo = external global i32
+@extgotequiv = private unnamed_addr constant i32* @extfoo
+
+; Don't replace GOT equivalent usage within instructions and emit the GOT
+; equivalent since it can't be replaced by the GOT entry. @bargotequiv is
+; used by an instruction inside @t0.
+;
+; X86: l_bargotequiv:
+; X86-NEXT:  .quad   _extbar
+@extbar = external global i32
+@bargotequiv = private unnamed_addr constant i32* @extbar
+
+@table = global [4 x %struct.data] [
+  %struct.data { i32 1, %struct.anon { i32 2, i32 3 } },
+; Test GOT equivalent usage inside nested constant arrays.
+
+; X86: .long   5
+; X86-NOT: .long   _localgotequiv-(_table+20)
+; X86-NEXT: .long   _localfoo@GOTPCREL+4
+  %struct.data { i32 4, %struct.anon { i32 5,
+    i32 trunc (i64 sub (i64 ptrtoint (i32** @localgotequiv to i64),
+                        i64 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i64 1, i32 1, i32 1) to i64))
+                        to i32)}
+  },
+; X86: .long   5
+; X86-NOT: _extgotequiv-(_table+32)
+; X86-NEXT: .long   _extfoo@GOTPCREL+4
+  %struct.data { i32 4, %struct.anon { i32 5,
+    i32 trunc (i64 sub (i64 ptrtoint (i32** @extgotequiv to i64),
+                        i64 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i64 2, i32 1, i32 1) to i64))
+                        to i32)}
+  },
+; Test support for arbitrary constants into the GOTPCREL offset.
+
+; X86: .long   5
+; X86-NOT: _extgotequiv-(_table+44)
+; X86-NEXT: .long   _extfoo@GOTPCREL+28
+  %struct.data { i32 4, %struct.anon { i32 5,
+    i32 add (i32 trunc (i64 sub (i64 ptrtoint (i32** @extgotequiv to i64),
+                                 i64 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i64 3, i32 1, i32 1) to i64))
+                                 to i32), i32 24)}
+  }
+], align 16
+
+; Test multiple uses of GOT equivalents.
+
+; X86-LABEL: _delta
+; X86: .long   _extfoo@GOTPCREL+4
+@delta = global i32 trunc (i64 sub (i64 ptrtoint (i32** @extgotequiv to i64),
+                                    i64 ptrtoint (i32* @delta to i64))
+                           to i32)
+
+; X86-LABEL: _deltaplus:
+; X86: .long   _localfoo@GOTPCREL+59
+@deltaplus = global i32 add (i32 trunc (i64 sub (i64 ptrtoint (i32** @localgotequiv to i64),
+                                        i64 ptrtoint (i32* @deltaplus to i64))
+                                        to i32), i32 55)
+
+define i32 @t0(i32 %a) {
+  %x = add i32 trunc (i64 sub (i64 ptrtoint (i32** @bargotequiv to i64),
+                               i64 ptrtoint (i32 (i32)* @t0 to i64))
+                           to i32), %a
+  ret i32 %x
+}
+
+; Also test direct instruction uses.
+define i32** @t1() {
+  ret i32** @bargotequiv
+}
diff --git a/test/MC/MachO/tlv-bss.ll b/test/MC/MachO/tlv-bss.ll
index af620f9e3048..3dbf4b07e16e 100644
--- a/test/MC/MachO/tlv-bss.ll
+++ b/test/MC/MachO/tlv-bss.ll
@@ -26,7 +26,7 @@ define i8* @_Z1fi(i32 %x) #0 {
 entry:
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %0 = load i8** @_ZN3TlsIlE3valE, align 8
+  %0 = load i8*, i8** @_ZN3TlsIlE3valE, align 8
   ret i8* %0
 }
 
diff --git a/test/MC/MachO/x86-data-in-code.ll b/test/MC/MachO/x86-data-in-code.ll
index 2410974c5ca3..c2e136fbeb08 100644
--- a/test/MC/MachO/x86-data-in-code.ll
+++ b/test/MC/MachO/x86-data-in-code.ll
@@ -6,7 +6,7 @@
 ; CHECK-NOT: (('command', 41)
 
 define void @foo(i32* %ptr) nounwind ssp {
-  %tmp = load i32* %ptr, align 4
+  %tmp = load i32, i32* %ptr, align 4
   switch i32 %tmp, label %default [
     i32 11, label %bb0
     i32 10, label %bb1
diff --git a/test/MC/MachO/x86_64-mergeable.s b/test/MC/MachO/x86_64-mergeable.s
new file mode 100644
index 000000000000..972477693ed2
--- /dev/null
+++ b/test/MC/MachO/x86_64-mergeable.s
@@ -0,0 +1,59 @@
+// RUN: llvm-mc -triple x86_64-apple-darwin14 %s -filetype=obj -o - | llvm-readobj -r --expand-relocs | FileCheck %s
+
+// Test that we "S + K" produce a relocation with a symbol, but just S produces
+// a relocation with the section.
+
+	.section	__TEXT,__literal4,4byte_literals
+L0:
+	.long	42
+
+	.section	__TEXT,__cstring,cstring_literals
+L1:
+	.asciz	"42"
+
+	.section	__DATA,__data
+	.quad	L0
+	.quad	L0 + 1
+	.quad	L1
+	.quad	L1 + 1
+
+// CHECK:      Relocations [
+// CHECK-NEXT:   Section __data {
+// CHECK-NEXT:     Relocation {
+// CHECK-NEXT:       Offset: 0x18
+// CHECK-NEXT:       PCRel: 0
+// CHECK-NEXT:       Length: 3
+// CHECK-NEXT:       Extern: 1
+// CHECK-NEXT:       Type: X86_64_RELOC_UNSIGNED (0)
+// CHECK-NEXT:       Symbol: L1
+// CHECK-NEXT:       Scattered: 0
+// CHECK-NEXT:     }
+// CHECK-NEXT:     Relocation {
+// CHECK-NEXT:       Offset: 0x10
+// CHECK-NEXT:       PCRel: 0
+// CHECK-NEXT:       Length: 3
+// CHECK-NEXT:       Extern: 0
+// CHECK-NEXT:       Type: X86_64_RELOC_UNSIGNED (0)
+// CHECK-NEXT:       Symbol: 0x3
+// CHECK-NEXT:       Scattered: 0
+// CHECK-NEXT:     }
+// CHECK-NEXT:     Relocation {
+// CHECK-NEXT:       Offset: 0x8
+// CHECK-NEXT:       PCRel: 0
+// CHECK-NEXT:       Length: 3
+// CHECK-NEXT:       Extern: 1
+// CHECK-NEXT:       Type: X86_64_RELOC_UNSIGNED (0)
+// CHECK-NEXT:       Symbol: L0
+// CHECK-NEXT:       Scattered: 0
+// CHECK-NEXT:     }
+// CHECK-NEXT:     Relocation {
+// CHECK-NEXT:       Offset: 0x0
+// CHECK-NEXT:       PCRel: 0
+// CHECK-NEXT:       Length: 3
+// CHECK-NEXT:       Extern: 0
+// CHECK-NEXT:       Type: X86_64_RELOC_UNSIGNED (0)
+// CHECK-NEXT:       Symbol: 0x2
+// CHECK-NEXT:       Scattered: 0
+// CHECK-NEXT:     }
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
diff --git a/test/MC/MachO/x86_64-symbols.s b/test/MC/MachO/x86_64-symbols.s
index e2dcc440fb5f..f40183df853c 100644
--- a/test/MC/MachO/x86_64-symbols.s
+++ b/test/MC/MachO/x86_64-symbols.s
@@ -121,6 +121,12 @@ D38:
 //L39:
 //D39:
 
+        .section foo, bar
+        .long L4 + 1
+        .long L35 + 1
+        .long L36 + 1
+        .long L37 + 1
+        .long L38 + 1
 
 // CHECK: Symbols [
 // CHECK-NEXT:   Symbol {
diff --git a/test/MC/Mips/asciiz-directive-bad.s b/test/MC/Mips/asciiz-directive-bad.s
new file mode 100644
index 000000000000..0f30cfbee630
--- /dev/null
+++ b/test/MC/Mips/asciiz-directive-bad.s
@@ -0,0 +1,8 @@
+# RUN: not llvm-mc -triple mips-unknown-linux %s 2>&1 | FileCheck %s
+
+  .asciiz 12
+# CHECK: :[[@LINE-1]]:11: error: expected string in '.asciiz' directive
+  .asciiz "a"3
+# CHECK: :[[@LINE-1]]:14: error: unexpected token in '.asciiz' directive
+  .asciiz "a",
+# CHECK: :[[@LINE-1]]:15: error: expected string in '.asciiz' directive
diff --git a/test/MC/Mips/asciiz-directive.s b/test/MC/Mips/asciiz-directive.s
new file mode 100644
index 000000000000..0e582145c718
--- /dev/null
+++ b/test/MC/Mips/asciiz-directive.s
@@ -0,0 +1,28 @@
+# RUN: llvm-mc -triple mips-unknown-linux %s | FileCheck %s
+# .asciiz is exactly the same as .asciz, except it's MIPS-specific.
+
+t1:
+  .asciiz
+# CHECK-LABEL: t1
+
+t2:
+  .asciiz "a"
+# CHECK-LABEL: t2
+# CHECK: .byte 97
+# CHECK: .byte 0
+
+t3:
+  .asciiz "a", "b", "c"
+# CHECK-LABEL: t3
+# CHECK: .byte 97
+# CHECK: .byte 0
+# CHECK: .byte 98
+# CHECK: .byte 0
+# CHECK: .byte 99
+# CHECK: .byte 0
+
+t4:
+  .asciiz "abcdefghijklmnop"
+# CHECK-LABEL: t4
+# CHECK: .ascii "abcdefghijklmnop"
+# CHECK: .byte 0
diff --git a/test/MC/Mips/cpload.s b/test/MC/Mips/cpload.s
index 46b3ee4c7955..842e0c7937c0 100644
--- a/test/MC/Mips/cpload.s
+++ b/test/MC/Mips/cpload.s
@@ -4,7 +4,7 @@
 # RUN:  llvm-objdump -d -r -arch=mips - | \
 # RUN:    FileCheck %s -check-prefix=OBJ-O32
 
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=-n64,+n32 -filetype=obj -o -| \
+# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -target-abi n32 -filetype=obj -o -| \
 # RUN:  llvm-objdump -d -r -arch=mips - | \
 # RUN:    FileCheck %s -check-prefix=OBJ-N32
 
diff --git a/test/MC/Mips/cpsetup-bad.s b/test/MC/Mips/cpsetup-bad.s
index 09252a1310ed..ec6525a195f1 100644
--- a/test/MC/Mips/cpsetup-bad.s
+++ b/test/MC/Mips/cpsetup-bad.s
@@ -12,3 +12,11 @@ t1:
 # ASM: :[[@LINE-1]]:23: error: expected save register or stack offset
         .cpsetup $31, $32, __cerror
 # ASM: :[[@LINE-1]]:23: error: invalid register
+        .cpsetup $25, $2, $3
+# ASM: :[[@LINE-1]]:28: error: expected expression
+        .cpsetup $25, $2, 4
+# ASM: :[[@LINE-1]]:28: error: expected symbol
+        .cpsetup $25, $2, 4+65
+# ASM: :[[@LINE-1]]:31: error: expected symbol
+        .cpsetup $25, $2, foo+4
+# ASM: :[[@LINE-1]]:32: error: expected symbol
diff --git a/test/MC/Mips/cpsetup.s b/test/MC/Mips/cpsetup.s
index a21a1e3b2a3e..a3ffae67aaec 100644
--- a/test/MC/Mips/cpsetup.s
+++ b/test/MC/Mips/cpsetup.s
@@ -1,19 +1,19 @@
-# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+o32 -filetype=obj -o - %s | \
+# RUN: llvm-mc -triple mips64-unknown-unknown -target-abi o32 -filetype=obj -o - %s | \
 # RUN:   llvm-objdump -d -r -arch=mips64 - | \
 # RUN:     FileCheck -check-prefix=O32 %s
 
-# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+o32 %s | \
+# RUN: llvm-mc -triple mips64-unknown-unknown -target-abi o32 %s | \
 # RUN:   FileCheck -check-prefix=ASM %s
 
-# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+n32 -filetype=obj -o - %s | \
-# RUN:   llvm-objdump -d -r -arch=mips64 - | \
+# RUN: llvm-mc -triple mips64-unknown-unknown -target-abi n32 -filetype=obj -o - %s | \
+# RUN:   llvm-objdump -d -r -t -arch=mips64 - | \
 # RUN:     FileCheck -check-prefix=NXX -check-prefix=N32 %s
 
-# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+n32 %s | \
+# RUN: llvm-mc -triple mips64-unknown-unknown -target-abi n32 %s | \
 # RUN:   FileCheck -check-prefix=ASM %s
 
 # RUN: llvm-mc -triple mips64-unknown-unknown %s -filetype=obj -o - | \
-# RUN:   llvm-objdump -d -r -arch=mips64 - | \
+# RUN:   llvm-objdump -d -r -t -arch=mips64 - | \
 # RUN:     FileCheck -check-prefix=NXX -check-prefix=N64 %s
 
 # RUN: llvm-mc -triple mips64-unknown-unknown %s | \
@@ -61,6 +61,35 @@ t2:
 
 # ASM: .cpsetup $25, $2, __cerror
 
+# .cpsetup with local labels (PR22518):
+1:
+        .cpsetup $25, $2, 1b
+        nop
+        sub $3, $3, $2
+        nop
+
+# O32: t2:
+# O32:   nop
+# O32:   sub $3, $3, $2
+# O32:   nop
+
+# FIXME: Direct object emission for N32 is still under development.
+# N32 doesn't allow 3 operations to be specified in the same relocation
+# record like N64 does.
+
+# NXX: move     $2, $gp
+# NXX: lui      $gp, 0
+# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16  $tmp0
+# NXX: addiu    $gp, $gp, 0
+# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16  $tmp0
+# N32: addu     $gp, $gp, $25
+# N64: daddu    $gp, $gp, $25
+# NXX: nop
+# NXX: sub $3, $3, $2
+# NXX: nop
+
+# ASM: .cpsetup $25, $2, $tmp0
+
 t3:
         .option pic0
         nop
@@ -76,3 +105,7 @@ t3:
 # ASM: nop
 # ASM: .cpsetup $25, 8, __cerror
 # ASM: nop
+
+# For .cpsetup with local labels, we need to check if $tmp0 is in the symbol
+# table:
+# NXX: .text  00000000 $tmp0
diff --git a/test/MC/Mips/do_switch3.s b/test/MC/Mips/do_switch3.s
index 02ad08714639..c0d9dc62fe6e 100644
--- a/test/MC/Mips/do_switch3.s
+++ b/test/MC/Mips/do_switch3.s
@@ -2,7 +2,7 @@
 // produced. This was not handled for direct object and an assertion
 // to occur. This is a variation on test case test/CodeGen/Mips/do_switch.ll
 
-// RUN: llvm-mc < %s -filetype=obj -triple=mips64-pc-linux -relocation-model=pic -mcpu=mips64 -mattr=n64
+// RUN: llvm-mc < %s -filetype=obj -triple=mips64-pc-linux -relocation-model=pic -mcpu=mips64 -target-abi=n64
 
 	.text
 	.abicalls
diff --git a/test/MC/Mips/eh-frame.s b/test/MC/Mips/eh-frame.s
index d6b9cf0a5405..167159885d72 100644
--- a/test/MC/Mips/eh-frame.s
+++ b/test/MC/Mips/eh-frame.s
@@ -31,7 +31,7 @@ func:
 // MIPS32: 00000000
 
 // Version
-// MIPS32: 03
+// MIPS32: 01
 
 // Augmentation String
 // MIPS32: 7a5200
@@ -67,7 +67,7 @@ func:
 // MIPS32EL: 00000000
 
 // Version
-// MIPS32EL: 03
+// MIPS32EL: 01
 
 // Augmentation String
 // MIPS32EL: 7a5200
@@ -103,7 +103,7 @@ func:
 // MIPS64: 00000000
 
 // Version
-// MIPS64: 03
+// MIPS64: 01
 
 // Augmentation String
 // MIPS64: 7a5200
@@ -141,7 +141,7 @@ func:
 // MIPS64EL: 00000000
 
 // Version
-// MIPS64EL: 03
+// MIPS64EL: 01
 
 // Augmentation String
 // MIPS64EL: 7a5200
diff --git a/test/MC/Mips/elf-bigendian.ll b/test/MC/Mips/elf-bigendian.ll
index a92fe339f88b..4990f4e5b75a 100644
--- a/test/MC/Mips/elf-bigendian.ll
+++ b/test/MC/Mips/elf-bigendian.ll
@@ -43,16 +43,16 @@ target triple = "mips-unknown-linux"
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @x, align 4
+  %0 = load i32, i32* @x, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %if.end, label %foo
 
 if.end:                                           ; preds = %entry
-  %puts = tail call i32 @puts(i8* getelementptr inbounds ([4 x i8]* @str, i32 0, i32 0))
+  %puts = tail call i32 @puts(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @str, i32 0, i32 0))
   br label %foo
 
 foo:                                              ; preds = %entry, %if.end
-  %puts2 = tail call i32 @puts(i8* getelementptr inbounds ([4 x i8]* @str2, i32 0, i32 0))
+  %puts2 = tail call i32 @puts(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @str2, i32 0, i32 0))
   ret i32 0
 }
 
diff --git a/test/MC/Mips/elf-tls.s b/test/MC/Mips/elf-tls.s
index d32a699fb08f..d50f62c20990 100644
--- a/test/MC/Mips/elf-tls.s
+++ b/test/MC/Mips/elf-tls.s
@@ -3,7 +3,7 @@
 // Check that the appropriate relocations were created.
 
 // CHECK: Relocations [
-// CHECK:   Section (2) .rel.text {
+// CHECK:   Section {{.*}} .rel.text {
 // CHECK:     R_MIPS_TLS_LDM
 // CHECK:     R_MIPS_TLS_DTPREL_HI16
 // CHECK:     R_MIPS_TLS_DTPREL_LO16
diff --git a/test/MC/Mips/elf_eflags.s b/test/MC/Mips/elf_eflags.s
index 1f28ee0ff89c..708894fee802 100644
--- a/test/MC/Mips/elf_eflags.s
+++ b/test/MC/Mips/elf_eflags.s
@@ -8,9 +8,13 @@
 # MIPSEL-MIPS64R6-NAN2008: Flags [ (0xA0000406)
 
 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r3 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r5 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2 %s
 # MIPSEL-MIPS64R2: Flags [ (0x80000006)
 
 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2-NAN2008 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r3 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2-NAN2008 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r5 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2-NAN2008 %s
 # MIPSEL-MIPS64R2-NAN2008: Flags [ (0x80000406)
 
 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64 %s
@@ -26,9 +30,13 @@
 # MIPSEL-MIPS32R6-NAN2008: Flags [ (0x90001404)
 
 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r3 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r5 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2 %s
 # MIPSEL-MIPS32R2: Flags [ (0x70001004)
 
 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2-NAN2008 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r3 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2-NAN2008 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r5 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2-NAN2008 %s
 # MIPSEL-MIPS32R2-NAN2008: Flags [ (0x70001404)
 
 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32 %s
@@ -37,35 +45,35 @@
 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32-NAN2008 %s
 # MIPSEL-MIPS32-NAN2008: Flags [ (0x50001404)
 
-# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 -mattr=-n64,n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32 %s
-# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 -target-abi n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32 %s
+# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -target-abi n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32 %s
 # MIPS64EL-MIPS64R2-N32: Flags [ (0x80000024)
 
-# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,n32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32-NAN2008 %s
+# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -target-abi n32 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32-NAN2008 %s
 # MIPS64EL-MIPS64R2-N32-NAN2008: Flags [ (0x80000424)
 
-# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=-n64,n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N32 %s
+# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -target-abi n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N32 %s
 # MIPS64EL-MIPS64-N32: Flags [ (0x60000024)
 
-# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=-n64,n32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N32-NAN2008 %s
+# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -target-abi n32 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N32-NAN2008 %s
 # MIPS64EL-MIPS64-N32-NAN2008: Flags [ (0x60000424)
 
-# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=n64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N64 %s
+# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -target-abi n64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N64 %s
 # MIPS64EL-MIPS64R2-N64: Flags [ (0x80000006)
 
-# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=n64,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N64-NAN2008 %s
+# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -target-abi n64 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N64-NAN2008 %s
 # MIPS64EL-MIPS64R2-N64-NAN2008: Flags [ (0x80000406)
 
-# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=n64 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N64 %s
+# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -target-abi n64 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N64 %s
 # MIPS64EL-MIPS64-N64: Flags [ (0x60000006)
 
-# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=n64,+nan2008 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N64-NAN2008 %s
+# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -target-abi n64 -mattr=+nan2008 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N64-NAN2008 %s
 # MIPS64EL-MIPS64-N64-NAN2008: Flags [ (0x60000406)
 
-# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,o32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-O32 %s
+# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -target-abi o32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-O32 %s
 # MIPS64EL-MIPS64R2-O32: Flags [ (0x80001104)
 
-# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,o32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-O32-NAN2008 %s
+# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -target-abi o32 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-O32-NAN2008 %s
 # MIPS64EL-MIPS64R2-O32-NAN2008: Flags [ (0x80001504)
 
 # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips5 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS5 %s
@@ -98,10 +106,10 @@
  # RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips1 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS1-NAN2008 %s
 # MIPS1-NAN2008: Flags [ (0x1404)
 
-# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=-n64,o32 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-O32 %s
+# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -target-abi o32 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-O32 %s
 # MIPS64EL-MIPS64-O32: Flags [ (0x60001104)
 
-# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=-n64,o32,+nan2008 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-O32-NAN2008 %s
+# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -target-abi o32 -mattr=+nan2008 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-O32-NAN2008 %s
 # MIPS64EL-MIPS64-O32-NAN2008: Flags [ (0x60001504)
 
 # Default ABI for MIPS64 is N64 as opposed to GCC/GAS (N32)
diff --git a/test/MC/Mips/elf_reginfo.s b/test/MC/Mips/elf_reginfo.s
index ba4788a39d9b..8a4ed3b96942 100644
--- a/test/MC/Mips/elf_reginfo.s
+++ b/test/MC/Mips/elf_reginfo.s
@@ -1,9 +1,9 @@
 # These *MUST* match the output of gas compiled with the same triple and
 # corresponding options (-mabi=64 -> -mattr=+n64 for example).
 
-# RUN: llvm-mc -filetype=obj -triple=mips64el-linux -mattr=-n64,+n64 %s -o - \
+# RUN: llvm-mc -filetype=obj -triple=mips64el-linux -target-abi n64 %s -o - \
 # RUN: | llvm-readobj -s | FileCheck --check-prefix=CHECK_64 %s
-# RUN: llvm-mc -filetype=obj -triple=mipsel %s -mattr=-o32,+n32 -o - \
+# RUN: llvm-mc -filetype=obj -triple=mipsel %s -target-abi n32 -o - \
 # RUN: | llvm-readobj -s | FileCheck --check-prefix=CHECK_32 %s
 
 # Check for register information sections.
diff --git a/test/MC/Mips/expr1.s b/test/MC/Mips/expr1.s
index 67664c1a2ae4..7959315a809a 100644
--- a/test/MC/Mips/expr1.s
+++ b/test/MC/Mips/expr1.s
@@ -1,18 +1,36 @@
-# RUN: llvm-mc  %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
+# RUN: llvm-mc  %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -show-encoding | \
+# RUN:   FileCheck %s --check-prefix=32R2-EL
+# RUN: llvm-mc  %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=micromips -show-encoding | \
+# RUN:   FileCheck %s --check-prefix=MM-32R2-EL
+
 # Check that the assembler can handle the expressions as operands.
-# CHECK:  .text
-# CHECK:  .globl  foo
-# CHECK:  foo:
-# CHECK:  lw   $4, %lo(foo)($4)    # encoding: [A,A,0x84,0x8c]
-# CHECK:                           #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16
-# CHECK:  lw   $4, 56($4)          # encoding: [0x38,0x00,0x84,0x8c]
-# CHECK:  lw   $4, %lo(foo+8)($4)  # encoding: [0x08'A',A,0x84,0x8c]
-# CHECK:                           #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16
-# CHECK:  lw   $4, %lo(foo+8)($4)  # encoding: [0x08'A',A,0x84,0x8c]
-# CHECK:                           #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16
-# CHECK:  lw   $4, %lo(foo+8)($4)  # encoding: [0x08'A',A,0x84,0x8c]
-# CHECK:                           #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16
-# CHECK:  .space  64
+# 32R2-EL: .text
+# 32R2-EL: .globl  foo
+# 32R2-EL: foo:
+# 32R2-EL: lw   $4, %lo(foo)($4)       # encoding: [A,A,0x84,0x8c]
+# 32R2-EL:                             #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16
+# 32R2-EL: lw   $4, 56($4)             # encoding: [0x38,0x00,0x84,0x8c]
+# 32R2-EL: lw   $4, %lo(foo+8)($4)     # encoding: [0x08'A',A,0x84,0x8c]
+# 32R2-EL:                             #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16
+# 32R2-EL: lw   $4, %lo(foo+8)($4)     # encoding: [0x08'A',A,0x84,0x8c]
+# 32R2-EL:                             #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16
+# 32R2-EL: lw   $4, %lo(foo+8)($4)     # encoding: [0x08'A',A,0x84,0x8c]
+# 32R2-EL:                             #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16
+# 32R2-EL: .space  64
+
+# MM-32R2-EL: .text
+# MM-32R2-EL: .globl  foo
+# MM-32R2-EL: foo:
+# MM-32R2-EL: lw   $4, %lo(foo)($4)    # encoding: [0x84'A',0xfc'A',0x00,0x00]
+# MM-32R2-EL:                          #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_MICROMIPS_LO16
+# MM-32R2-EL: lw   $4, 56($4)          # encoding: [0x84,0xfc,0x38,0x00]
+# MM-32R2-EL: lw   $4, %lo(foo+8)($4)  # encoding: [0x84'A',0xfc'A',0x08,0x00]
+# MM-32R2-EL:                          #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_MICROMIPS_LO16
+# MM-32R2-EL: lw   $4, %lo(foo+8)($4)  # encoding: [0x84'A',0xfc'A',0x08,0x00]
+# MM-32R2-EL:                          #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_MICROMIPS_LO16
+# MM-32R2-EL: lw   $4, %lo(foo+8)($4)  # encoding: [0x84'A',0xfc'A',0x08,0x00]
+# MM-32R2-EL:                          #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_MICROMIPS_LO16
+# MM-32R2-EL: .space  64
 
   .globl  foo
   .ent  foo
diff --git a/test/MC/Mips/insn-directive.s b/test/MC/Mips/insn-directive.s
new file mode 100644
index 000000000000..760a27399bfb
--- /dev/null
+++ b/test/MC/Mips/insn-directive.s
@@ -0,0 +1,98 @@
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 | FileCheck %s --check-prefix=ASM
+
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
+# RUN:   llvm-readobj -symbols - | FileCheck %s --check-prefix=OBJ
+
+  .set micromips
+
+  .global f_mm_insn_data
+  .type f_mm_insn_data, @function
+f_mm_insn_data:
+  .insn
+  .word 0x00e73910   # add $7, $7, $7
+
+  .global f_mm_insn_instr
+  .type f_mm_insn_instr, @function
+f_mm_insn_instr:
+  .insn
+  add $7, $7, $7
+
+  .global o_mm_insn_data
+  .type o_mm_insn_data, @object
+o_mm_insn_data:
+  .insn
+  .word 0x00e73910   # add $7, $7, $7
+
+  .global o_mm_insn_instr
+  .type o_mm_insn_instr, @object
+o_mm_insn_instr:
+  .insn
+  add $7, $7, $7
+
+  .set nomicromips
+
+  .global f_normal_insn_data
+  .type f_normal_insn_data, @function
+f_normal_insn_data:
+  .insn
+  .word 0x00e73820   # add $7, $7, $7
+
+  .global f_normal_insn_instr
+  .type f_normal_insn_instr, @function
+f_normal_insn_instr:
+  .insn
+  add $7, $7, $7
+
+  .global o_normal_insn_data
+  .type o_normal_insn_data, @object
+o_normal_insn_data:
+  .insn
+  .word 0x00e73820   # add $7, $7, $7
+
+  .global o_normal_insn_instr
+  .type o_normal_insn_instr, @object
+o_normal_insn_instr:
+  .insn
+  add $7, $7, $7
+
+# Verify that .insn causes the currently saved labels to be cleared by checking
+# that foo doesn't get marked.
+  .set nomicromips
+foo:
+  .insn
+  .word 0x00e73820   # add $7, $7, $7
+
+  .set micromips
+bar:
+  add $7, $7, $7
+
+# ASM: .insn
+
+# OBJ: Symbols [
+# OBJ: Name: foo
+# OBJ: Other: 0
+
+# OBJ: Name: f_mm_insn_data
+# OBJ: Other: 128
+
+# OBJ: Name: f_mm_insn_instr
+# OBJ: Other: 128
+
+# OBJ: Name: f_normal_insn_data
+# OBJ: Other: 0
+
+# OBJ: Name: f_normal_insn_instr
+# OBJ: Other: 0
+
+# OBJ: Name: o_mm_insn_data
+# OBJ: Other: 128
+
+# OBJ: Name: o_mm_insn_instr
+# OBJ: Other: 128
+
+# OBJ: Name: o_normal_insn_data
+# OBJ: Other: 0
+
+# OBJ: Name: o_normal_insn_instr
+# OBJ: Other: 0
+# OBJ: ]
diff --git a/test/MC/Mips/micromips-16-bit-instructions.s b/test/MC/Mips/micromips-16-bit-instructions.s
index 8fd6d450ac90..25fbfdb92ad3 100644
--- a/test/MC/Mips/micromips-16-bit-instructions.s
+++ b/test/MC/Mips/micromips-16-bit-instructions.s
@@ -26,6 +26,7 @@
 # CHECK-EL: sh16    $4, 8($17)      # encoding: [0x14,0xaa]
 # CHECK-EL: sw16    $4, 4($17)      # encoding: [0x11,0xea]
 # CHECK-EL: sw16    $zero, 4($17)   # encoding: [0x11,0xe8]
+# CHECK-EL: lw      $3, 32($gp)     # encoding: [0x88,0x65]
 # CHECK-EL: lw      $3, 32($sp)     # encoding: [0x68,0x48]
 # CHECK-EL: sw      $4, 124($sp)    # encoding: [0x9f,0xc8]
 # CHECK-EL: li16    $3, -1          # encoding: [0xff,0xed]
@@ -42,6 +43,7 @@
 # CHECK-EL: mfhi    $9              # encoding: [0x09,0x46]
 # CHECK-EL: mflo    $9              # encoding: [0x49,0x46]
 # CHECK-EL: move    $25, $1         # encoding: [0x21,0x0f]
+# CHECK-EL: movep   $5, $6, $2, $3  # encoding: [0x34,0x84]
 # CHECK-EL: jrc     $9              # encoding: [0xa9,0x45]
 # CHECK-NEXT: jalr    $9            # encoding: [0xc9,0x45]
 # CHECK-EL: jraddiusp 20            # encoding: [0x05,0x47]
@@ -53,6 +55,10 @@
 # CHECK-EL: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EL: bnez16 $6, 20           # encoding: [0x0a,0xaf]
 # CHECK-EL: nop                     # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-EL: b16 132                 # encoding: [0x42,0xcc]
+# CHECK-EL: nop
+# CHECK-EL: b16 132                 # encoding: [0x42,0xcc]
+# CHECK-EL: nop
 # CHECK-EL: break16 8               # encoding: [0x88,0x46]
 # CHECK-EL: sdbbp16 14              # encoding: [0xce,0x46]
 #------------------------------------------------------------------------------
@@ -75,6 +81,7 @@
 # CHECK-EB: sh16    $4, 8($17)      # encoding: [0xaa,0x14]
 # CHECK-EB: sw16    $4, 4($17)      # encoding: [0xea,0x11]
 # CHECK-EB: sw16    $zero, 4($17)   # encoding: [0xe8,0x11]
+# CHECK-EB: lw      $3, 32($gp)     # encoding: [0x65,0x88]
 # CHECK-EB: lw      $3, 32($sp)     # encoding: [0x48,0x68]
 # CHECK-EB: sw      $4, 124($sp)    # encoding: [0xc8,0x9f]
 # CHECK-EB: li16    $3, -1          # encoding: [0xed,0xff]
@@ -91,6 +98,7 @@
 # CHECK-EB: mfhi    $9              # encoding: [0x46,0x09]
 # CHECK-EB: mflo    $9              # encoding: [0x46,0x49]
 # CHECK-EB: move    $25, $1         # encoding: [0x0f,0x21]
+# CHECK-EB: movep   $5, $6, $2, $3  # encoding: [0x84,0x34]
 # CHECK-EB: jrc     $9              # encoding: [0x45,0xa9]
 # CHECK-NEXT: jalr    $9            # encoding: [0x45,0xc9]
 # CHECK-EB: jraddiusp 20            # encoding: [0x47,0x05]
@@ -102,6 +110,10 @@
 # CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: bnez16 $6, 20           # encoding: [0xaf,0x0a]
 # CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-EB: b16 132                 # encoding: [0xcc,0x42]
+# CHECK-EB: nop
+# CHECK-EB: b16 132                 # encoding: [0xcc,0x42]
+# CHECK-EB: nop
 # CHECK-EB: break16 8               # encoding: [0x46,0x88]
 # CHECK-EB: sdbbp16 14              # encoding: [0x46,0xce]
 
@@ -122,6 +134,7 @@
     sh16    $4, 8($17)
     sw16    $4, 4($17)
     sw16    $0, 4($17)
+    lw      $3, 32($gp)
     lw      $3, 32($sp)
     sw      $4, 124($sp)
     li16    $3, -1
@@ -138,6 +151,7 @@
     mfhi    $9
     mflo    $9
     move    $25, $1
+    movep   $5, $6, $2, $3
     jrc     $9
     jalr    $9
     jraddiusp 20
@@ -145,5 +159,7 @@
     jr16    $9
     beqz16 $6, 20
     bnez16 $6, 20
+    b   132
+    b16 132
     break16 8
     sdbbp16 14
diff --git a/test/MC/Mips/micromips-alias.s b/test/MC/Mips/micromips-alias.s
index c0bf4b3a8e33..256b3b68aa61 100644
--- a/test/MC/Mips/micromips-alias.s
+++ b/test/MC/Mips/micromips-alias.s
@@ -14,3 +14,15 @@ f:
   nop
   .globl bar
 bar = f
+
+# CHECK: Name: foo
+# CHECK: Other: 128
+  .type  o,@object
+  .set   micromips
+o:
+  .insn
+  .word 0x00000000
+  .set   nomicromips
+
+  .globl foo
+foo = o
diff --git a/test/MC/Mips/micromips-alu-instructions.s b/test/MC/Mips/micromips-alu-instructions.s
index 1131d1f3eae9..aeab09e78fa9 100644
--- a/test/MC/Mips/micromips-alu-instructions.s
+++ b/test/MC/Mips/micromips-alu-instructions.s
@@ -38,6 +38,9 @@
 # CHECK-EL: multu  $9, $7         # encoding: [0xe9,0x00,0x3c,0x9b]
 # CHECK-EL: div    $zero, $9, $7  # encoding: [0xe9,0x00,0x3c,0xab]
 # CHECK-EL: divu   $zero, $9, $7  # encoding: [0xe9,0x00,0x3c,0xbb]
+# CHECK-EL: addiupc $2, 20        # encoding: [0x00,0x79,0x05,0x00]
+# CHECK-EL: addiupc $7, 16777212  # encoding: [0xbf,0x7b,0xff,0xff]
+# CHECK-EL: addiupc $7, -16777216 # encoding: [0xc0,0x7b,0x00,0x00]
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
@@ -72,6 +75,9 @@
 # CHECK-EB:  multu $9, $7         # encoding: [0x00,0xe9,0x9b,0x3c]
 # CHECK-EB: div  $zero, $9, $7    # encoding: [0x00,0xe9,0xab,0x3c]
 # CHECK-EB: divu $zero, $9, $7    # encoding: [0x00,0xe9,0xbb,0x3c]
+# CHECK-EB: addiupc $2, 20        # encoding: [0x79,0x00,0x00,0x05]
+# CHECK-EB: addiupc $7, 16777212  # encoding: [0x7b,0xbf,0xff,0xff]
+# CHECK-EB: addiupc $7, -16777216 # encoding: [0x7b,0xc0,0x00,0x00]
     add    $9, $6, $7
     add    $9, $6, 17767
     addu   $9, $6, -15001
@@ -104,3 +110,6 @@
     multu  $9, $7
     div    $0, $9, $7
     divu   $0, $9, $7
+    addiupc $2, 20
+    addiupc $7, 16777212
+    addiupc $7, -16777216
diff --git a/test/MC/Mips/micromips-branch-fixup.s b/test/MC/Mips/micromips-branch-fixup.s
new file mode 100644
index 000000000000..98b48421b05e
--- /dev/null
+++ b/test/MC/Mips/micromips-branch-fixup.s
@@ -0,0 +1,91 @@
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding \
+# RUN: -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP
+# RUN: llvm-mc %s -filetype=obj -triple=mipsel-unknown-linux \
+# RUN: -mattr=micromips | llvm-readobj -r \
+# RUN: | FileCheck %s -check-prefix=CHECK-ELF
+#------------------------------------------------------------------------------
+# Check that the assembler can handle the documented syntax
+# for relocations.
+#------------------------------------------------------------------------------
+# CHECK-FIXUP: beqz16 $6, bar  # encoding: [0b0AAAAAAA,0x8f]
+# CHECK-FIXUP:                 #   fixup A - offset: 0,
+# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC7_S1
+# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-FIXUP: bnez16 $6, bar  # encoding: [0b0AAAAAAA,0xaf]
+# CHECK-FIXUP:                 #   fixup A - offset: 0,
+# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC7_S1
+# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-FIXUP: b16         bar # encoding: [A,0b110011AA]
+# CHECK-FIXUP:                 #   fixup A - offset: 0,
+# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC10_S1
+# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-FIXUP: b   bar         # encoding: [A,0x94'A',0x00,0x00]
+# CHECK-FIXUP:                 #   fixup A - offset: 0,
+# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
+# CHECK-FIXUP: nop             # encoding: [0x00,0x0c]
+# CHECK-FIXUP: beq $3, $4, bar # encoding: [0x83'A',0x94'A',0x00,0x00]
+# CHECK-FIXUP:                 #   fixup A - offset: 0,
+# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
+# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-FIXUP: bne $3, $4, bar # encoding: [0x83'A',0xb4'A',0x00,0x00]
+# CHECK-FIXUP:                 #   fixup A - offset: 0,
+# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
+# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-FIXUP: bgez    $4, bar # encoding: [0x44'A',0x40'A',0x00,0x00]
+# CHECK-FIXUP:                 #   fixup A - offset: 0,
+# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
+# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-FIXUP: bgtz    $4, bar # encoding: [0xc4'A',0x40'A',0x00,0x00]
+# CHECK-FIXUP:                 #   fixup A - offset: 0,
+# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
+# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-FIXUP: blez    $4, bar # encoding: [0x84'A',0x40'A',0x00,0x00]
+# CHECK-FIXUP:                 #   fixup A - offset: 0,
+# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
+# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-FIXUP: bltz    $4, bar # encoding: [0x04'A',0x40'A',0x00,0x00]
+# CHECK-FIXUP:                 #   fixup A - offset: 0,
+# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
+# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-FIXUP: bgezal  $4, bar # encoding: [0x64'A',0x40'A',0x00,0x00]
+# CHECK-FIXUP:                 #   fixup A - offset: 0,
+# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
+# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-FIXUP: bltzal  $4, bar # encoding: [0x24'A',0x40'A',0x00,0x00]
+# CHECK-FIXUP:                 #   fixup A - offset: 0,
+# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
+# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
+#------------------------------------------------------------------------------
+# Check that the appropriate relocations were created.
+#------------------------------------------------------------------------------
+# CHECK-ELF: Relocations [
+# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC7_S1
+# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC7_S1
+# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC10_S1
+# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
+# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
+# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
+# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
+# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
+# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
+# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
+# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
+# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
+# CHECK-ELF: ]
+
+  .text
+  .type main, @function
+  .set micromips
+main:
+  beqz16  $6, bar
+  bnez16  $6, bar
+  b16     bar
+  b       bar
+  beq     $3, $4, bar
+  bne     $3, $4, bar
+  bgez    $4, bar
+  bgtz    $4, bar
+  blez    $4, bar
+  bltz    $4, bar
+  bgezal  $4, bar
+  bltzal  $4, bar
diff --git a/test/MC/Mips/micromips-branch-instructions.s b/test/MC/Mips/micromips-branch-instructions.s
index d1e78988901a..e85b92521ea2 100644
--- a/test/MC/Mips/micromips-branch-instructions.s
+++ b/test/MC/Mips/micromips-branch-instructions.s
@@ -9,8 +9,8 @@
 #------------------------------------------------------------------------------
 # Little endian
 #------------------------------------------------------------------------------
-# CHECK-EL: b 1332               # encoding: [0x00,0x94,0x9a,0x02]
-# CHECK-EL: nop                  # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-EL: b   1332             # encoding: [0x00,0x94,0x9a,0x02]
+# CHECK-EL: nop                  # encoding: [0x00,0x0c]
 # CHECK-EL: beq $9, $6, 1332     # encoding: [0xc9,0x94,0x9a,0x02]
 # CHECK-EL: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EL: bgez $6, 1332        # encoding: [0x46,0x40,0x9a,0x02]
@@ -36,8 +36,8 @@
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
-# CHECK-EB: b 1332               # encoding: [0x94,0x00,0x02,0x9a]
-# CHECK-EB: nop                  # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-EB: b   1332             # encoding: [0x94,0x00,0x02,0x9a]
+# CHECK-EB: nop                  # encoding: [0x0c,0x00]
 # CHECK-EB: beq $9, $6, 1332     # encoding: [0x94,0xc9,0x02,0x9a]
 # CHECK-EB: nop                  # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: bgez $6, 1332        # encoding: [0x40,0x46,0x02,0x9a]
@@ -61,6 +61,10 @@
 # CHECK-EB: bltzals $6, 1332     # encoding: [0x42,0x26,0x02,0x9a]
 # CHECK-EB: nop                  # encoding: [0x0c,0x00]
 
+    .text
+    .type main, @function
+    .set micromips
+main:
      b      1332
      beq    $9,$6,1332
      bgez   $6,1332
diff --git a/test/MC/Mips/micromips-branch16.s b/test/MC/Mips/micromips-branch16.s
deleted file mode 100644
index 321ee8640f70..000000000000
--- a/test/MC/Mips/micromips-branch16.s
+++ /dev/null
@@ -1,69 +0,0 @@
-# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding \
-# RUN: -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP
-# RUN: llvm-mc %s -filetype=obj -triple=mipsel-unknown-linux \
-# RUN: -mattr=micromips | llvm-readobj -r \
-# RUN: | FileCheck %s -check-prefix=CHECK-ELF
-#------------------------------------------------------------------------------
-# Check that the assembler can handle the documented syntax
-# for relocations.
-#------------------------------------------------------------------------------
-# CHECK-FIXUP: b           bar # encoding: [A,0x94'A',0x00,0x00]
-# CHECK-FIXUP:                 #   fixup A - offset: 0,
-# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
-# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
-# CHECK-FIXUP: beq $3, $4, bar # encoding: [0x83'A',0x94'A',0x00,0x00]
-# CHECK-FIXUP:                 #   fixup A - offset: 0,
-# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
-# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
-# CHECK-FIXUP: bne $3, $4, bar # encoding: [0x83'A',0xb4'A',0x00,0x00]
-# CHECK-FIXUP:                 #   fixup A - offset: 0,
-# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
-# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
-# CHECK-FIXUP: bgez    $4, bar # encoding: [0x44'A',0x40'A',0x00,0x00]
-# CHECK-FIXUP:                 #   fixup A - offset: 0,
-# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
-# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
-# CHECK-FIXUP: bgtz    $4, bar # encoding: [0xc4'A',0x40'A',0x00,0x00]
-# CHECK-FIXUP:                 #   fixup A - offset: 0,
-# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
-# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
-# CHECK-FIXUP: blez    $4, bar # encoding: [0x84'A',0x40'A',0x00,0x00]
-# CHECK-FIXUP:                 #   fixup A - offset: 0,
-# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
-# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
-# CHECK-FIXUP: bltz    $4, bar # encoding: [0x04'A',0x40'A',0x00,0x00]
-# CHECK-FIXUP:                 #   fixup A - offset: 0,
-# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
-# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
-# CHECK-FIXUP: bgezal  $4, bar # encoding: [0x64'A',0x40'A',0x00,0x00]
-# CHECK-FIXUP:                 #   fixup A - offset: 0,
-# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
-# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
-# CHECK-FIXUP: bltzal  $4, bar # encoding: [0x24'A',0x40'A',0x00,0x00]
-# CHECK-FIXUP:                 #   fixup A - offset: 0,
-# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC16_S1
-# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
-#------------------------------------------------------------------------------
-# Check that the appropriate relocations were created.
-#------------------------------------------------------------------------------
-# CHECK-ELF: Relocations [
-# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
-# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
-# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
-# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
-# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
-# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
-# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
-# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
-# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
-# CHECK-ELF: ]
-
-  b       bar
-  beq     $3, $4, bar
-  bne     $3, $4, bar
-  bgez    $4, bar
-  bgtz    $4, bar
-  blez    $4, bar
-  bltz    $4, bar
-  bgezal  $4, bar
-  bltzal  $4, bar
diff --git a/test/MC/Mips/micromips-branch7.s b/test/MC/Mips/micromips-branch7.s
deleted file mode 100644
index deb7307e938c..000000000000
--- a/test/MC/Mips/micromips-branch7.s
+++ /dev/null
@@ -1,27 +0,0 @@
-# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding \
-# RUN: -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP
-# RUN: llvm-mc %s -filetype=obj -triple=mipsel-unknown-linux \
-# RUN: -mattr=micromips | llvm-readobj -r \
-# RUN: | FileCheck %s -check-prefix=CHECK-ELF
-#------------------------------------------------------------------------------
-# Check that the assembler can handle the documented syntax
-# for relocations.
-#------------------------------------------------------------------------------
-# CHECK-FIXUP: beqz16 $6, bar  # encoding: [0b0AAAAAAA,0x8f]
-# CHECK-FIXUP:                 #   fixup A - offset: 0,
-# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC7_S1
-# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
-# CHECK-FIXUP: bnez16 $6, bar  # encoding: [0b0AAAAAAA,0xaf]
-# CHECK-FIXUP:                 #   fixup A - offset: 0,
-# CHECK-FIXUP:                     value: bar, kind: fixup_MICROMIPS_PC7_S1
-# CHECK-FIXUP: nop             # encoding: [0x00,0x00,0x00,0x00]
-#------------------------------------------------------------------------------
-# Check that the appropriate relocations were created.
-#------------------------------------------------------------------------------
-# CHECK-ELF: Relocations [
-# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC7_S1
-# CHECK-ELF:     0x{{[0-9,A-F]+}} R_MICROMIPS_PC7_S1
-# CHECK-ELF: ]
-
-  beqz16 $6, bar
-  bnez16 $6, bar
diff --git a/test/MC/Mips/micromips-diagnostic-fixup.s b/test/MC/Mips/micromips-diagnostic-fixup.s
index f8fe447c283c..041338ac2d3b 100644
--- a/test/MC/Mips/micromips-diagnostic-fixup.s
+++ b/test/MC/Mips/micromips-diagnostic-fixup.s
@@ -4,7 +4,7 @@
 
 .text
   b foo
-  .space 65536 - 8, 1   # -8 = size of b instr plus size of automatically inserted nop
+  .space 65536 - 6, 1   # -6 = size of b instr plus size of automatically inserted nop
   nop                   # This instr makes the branch too long to fit into a 17-bit offset
 foo:
   add $0,$0,$0
diff --git a/test/MC/Mips/micromips-expansions.s b/test/MC/Mips/micromips-expansions.s
index af4d3b579003..5024850abc4d 100644
--- a/test/MC/Mips/micromips-expansions.s
+++ b/test/MC/Mips/micromips-expansions.s
@@ -9,10 +9,10 @@
 # CHECK: addiu $6, $zero, -2345      # encoding: [0xc0,0x30,0xd7,0xf6]
 # CHECK: lui   $7, 1                 # encoding: [0xa7,0x41,0x01,0x00]
 # CHECK: ori   $7, $7, 2             # encoding: [0xe7,0x50,0x02,0x00]
-# CHECK: addiu $4, $zero, 20         # encoding: [0x80,0x30,0x14,0x00]
+# CHECK: ori   $4, $zero, 20         # encoding: [0x80,0x50,0x14,0x00]
 # CHECK: lui   $7, 1                 # encoding: [0xa7,0x41,0x01,0x00]
 # CHECK: ori   $7, $7, 2             # encoding: [0xe7,0x50,0x02,0x00]
-# CHECK: addiu $4, $5, 20            # encoding: [0x85,0x30,0x14,0x00]
+# CHECK: ori   $4, $5, 20            # encoding: [0x85,0x50,0x14,0x00]
 # CHECK: lui   $7, 1                 # encoding: [0xa7,0x41,0x01,0x00]
 # CHECK: ori   $7, $7, 2             # encoding: [0xe7,0x50,0x02,0x00]
 # CHECK: addu  $7, $7, $8            # encoding: [0x07,0x01,0x50,0x39]
diff --git a/test/MC/Mips/micromips-expressions.s b/test/MC/Mips/micromips-expressions.s
deleted file mode 100644
index 509e98072bb4..000000000000
--- a/test/MC/Mips/micromips-expressions.s
+++ /dev/null
@@ -1,35 +0,0 @@
-# RUN: llvm-mc  %s -triple=mipsel-unknown-linux -show-encoding \
-# RUN: -mcpu=mips32r2 -mattr=micromips | FileCheck %s
-# Check that the assembler can handle the expressions as operands.
-# CHECK:  .text
-# CHECK:  .globl  foo
-# CHECK:  foo:
-# CHECK:  lw   $4, %lo(foo)($4)    # encoding: [0x84'A',0xfc'A',0x00,0x00]
-# CHECK:                           # fixup A - offset: 0,
-# CHECK:                             value: foo@ABS_LO,
-# CHECK:                             kind: fixup_MICROMIPS_LO16
-# CHECK:  lw   $4, 56($4)          # encoding: [0x84,0xfc,0x38,0x00]
-# CHECK:  lw   $4, %lo(foo+8)($4)  # encoding: [0x84'A',0xfc'A',0x08,0x00]
-# CHECK:                           # fixup A - offset: 0,
-# CHECK:                             value: foo@ABS_LO,
-# CHECK:                             kind: fixup_MICROMIPS_LO16
-# CHECK:  lw   $4, %lo(foo+8)($4)  # encoding: [0x84'A',0xfc'A',0x08,0x00]
-# CHECK:                           # fixup A - offset: 0,
-# CHECK:                             value: foo@ABS_LO,
-# CHECK:                             kind: fixup_MICROMIPS_LO16
-# CHECK:  lw   $4, %lo(foo+8)($4)  # encoding: [0x84'A',0xfc'A',0x08,0x00]
-# CHECK:                           # fixup A - offset: 0,
-# CHECK:                             value: foo@ABS_LO,
-# CHECK:                             kind: fixup_MICROMIPS_LO16
-# CHECK:  .space  64
-
-  .globl  foo
-  .ent  foo
-foo:
-  lw  $4,%lo(foo)($4)
-  lw  $4,((10 + 4) * 4)($4)
-  lw  $4,%lo (2 * 4) + foo($4)
-  lw  $4,%lo((2 * 4) + foo)($4)
-  lw  $4,(((%lo ((2 * 4) + foo))))($4)
-  .space  64
-  .end  foo
diff --git a/test/MC/Mips/micromips-invalid.s b/test/MC/Mips/micromips-invalid.s
index 1dbfb113a2c9..4321574b5bff 100644
--- a/test/MC/Mips/micromips-invalid.s
+++ b/test/MC/Mips/micromips-invalid.s
@@ -38,6 +38,9 @@
   swm32   $16, $19, 8($4)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
   swm32   $16-$25, 8($4)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
   lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
+  addiupc $7, 16777216  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+  addiupc $6, -16777220 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+  addiupc $3, 3         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   lbu16 $9, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   lhu16 $9, 4($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   lw16  $9, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
@@ -66,3 +69,7 @@
   pref 256, 8($5)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   beqz16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   bnez16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  movep   $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  movep   $8, $6, $2, $3  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  movep   $5, $6, $5, $3  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  movep   $5, $6, $2, $9  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/test/MC/Mips/micromips-jump-instructions.s b/test/MC/Mips/micromips-jump-instructions.s
index 76f85abafe79..3147a3f256d4 100644
--- a/test/MC/Mips/micromips-jump-instructions.s
+++ b/test/MC/Mips/micromips-jump-instructions.s
@@ -19,10 +19,16 @@
 # CHECK-EL: nop         # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EL: jr $7       # encoding: [0x07,0x00,0x3c,0x0f]
 # CHECK-EL: nop         # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-EL: jalx 1328   # encoding: [0x00,0xf0,0x4c,0x01]
+# CHECK-EL: nop         # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EL: jals 1328         # encoding: [0x00,0x74,0x98,0x02]
 # CHECK-EL: nop               # encoding: [0x00,0x0c]
 # CHECK-EL: jalrs $ra, $6     # encoding: [0xe6,0x03,0x3c,0x4f]
 # CHECK-EL: nop               # encoding: [0x00,0x0c]
+# CHECK-EL: jalr $25          # encoding: [0xd9,0x45]
+# CHECK-EL: nop               # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-EL: jalr $4, $25      # encoding: [0x99,0x00,0x3c,0x0f]
+# CHECK-EL: nop               # encoding: [0x00,0x00,0x00,0x00]
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
@@ -36,15 +42,24 @@
 # CHECK-EB: nop         # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: jr $7       # encoding: [0x00,0x07,0x0f,0x3c]
 # CHECK-EB: nop         # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-EB: jalx 1328   # encoding: [0xf0,0x00,0x01,0x4c]
+# CHECK-EB: nop         # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: jals 1328         # encoding: [0x74,0x00,0x02,0x98]
 # CHECK-EB: nop               # encoding: [0x0c,0x00]
 # CHECK-EB: jalrs $ra, $6     # encoding: [0x03,0xe6,0x4f,0x3c]
 # CHECK-EB: nop               # encoding: [0x0c,0x00]
+# CHECK-EB: jalr $25          # encoding: [0x45,0xd9]
+# CHECK-EB: nop               # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-EB: jalr $4, $25      # encoding: [0x00,0x99,0x0f,0x3c]
+# CHECK-EB: nop               # encoding: [0x00,0x00,0x00,0x00]
 
      j 1328
      jal 1328
      jalr $ra, $6
      jr $7
      j $7
+     jalx 1328
      jals 1328
      jalrs $ra, $6
+     jal $25
+     jal $4, $25
diff --git a/test/MC/Mips/micromips-loadstore-instructions.s b/test/MC/Mips/micromips-loadstore-instructions.s
index 995af035dde5..f22719dff94e 100644
--- a/test/MC/Mips/micromips-loadstore-instructions.s
+++ b/test/MC/Mips/micromips-loadstore-instructions.s
@@ -19,6 +19,7 @@
 # CHECK-EL: sh     $2, 8($4)                  # encoding: [0x44,0x38,0x08,0x00]
 # CHECK-EL: sw     $5, 4($6)                  # encoding: [0xa6,0xf8,0x04,0x00]
 # CHECK-EL: sw     $5, 123($sp)               # encoding: [0xbd,0xf8,0x7b,0x00]
+# CHECK-EL: sw     $3, 32($gp)                # encoding: [0x7c,0xf8,0x20,0x00]
 # CHECK-EL: ll     $2, 8($4)                  # encoding: [0x44,0x60,0x08,0x30]
 # CHECK-EL: sc     $2, 8($4)                  # encoding: [0x44,0x60,0x08,0xb0]
 # CHECK-EL: lwu    $2, 8($4)                  # encoding: [0x44,0x60,0x08,0xe0]
@@ -33,6 +34,14 @@
 # CHECK-EL: swm32  $16, $17, $18, $19, 8($4)  # encoding: [0x84,0x20,0x08,0xd0]
 # CHECK-EL: lwm16  $16, $17, $ra, 8($sp)      # encoding: [0x12,0x45]
 # CHECK-EL: swm16  $16, $17, $ra, 8($sp)      # encoding: [0x52,0x45]
+# CHECK-EL: lwm16  $16, $17, $ra, 8($sp)      # encoding: [0x12,0x45]
+# CHECK-EL: lwm32  $16, $17, $ra, 64($sp)     # encoding: [0x5d,0x22,0x40,0x50]
+# CHECK-EL: lwm32  $16, $17, $ra, 8($4)       # encoding: [0x44,0x22,0x08,0x50]
+# CHECK-EL: lwm32  $16, $17, 8($sp)           # encoding: [0x5d,0x20,0x08,0x50]
+# CHECK-EL: swm16  $16, $17, $ra, 8($sp)      # encoding: [0x52,0x45]
+# CHECK-EL: swm32  $16, $17, $ra, 64($sp)     # encoding: [0x5d,0x22,0x40,0xd0]
+# CHECK-EL: swm32  $16, $17, $ra, 8($4)       # encoding: [0x44,0x22,0x08,0xd0]
+# CHECK-EL: swm32  $16, $17, 8($sp)           # encoding: [0x5d,0x20,0x08,0xd0]
 # CHECK-EL: swp    $16, 8($4)                 # encoding: [0x04,0x22,0x08,0x90]
 # CHECK-EL: lwp    $16, 8($4)                 # encoding: [0x04,0x22,0x08,0x10]
 #------------------------------------------------------------------------------
@@ -48,6 +57,7 @@
 # CHECK-EB: sh     $2, 8($4)                 # encoding: [0x38,0x44,0x00,0x08]
 # CHECK-EB: sw     $5, 4($6)                 # encoding: [0xf8,0xa6,0x00,0x04]
 # CHECK-EB: sw     $5, 123($sp)              # encoding: [0xf8,0xbd,0x00,0x7b]
+# CHECK-EB: sw     $3, 32($gp)               # encoding: [0xf8,0x7c,0x00,0x20]
 # CHECK-EB: ll     $2, 8($4)                 # encoding: [0x60,0x44,0x30,0x08]
 # CHECK-EB: sc     $2, 8($4)                 # encoding: [0x60,0x44,0xb0,0x08]
 # CHECK-EB: lwu    $2, 8($4)                 # encoding: [0x60,0x44,0xe0,0x08]
@@ -62,6 +72,14 @@
 # CHECK-EB: swm32  $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
 # CHECK-EB: lwm16  $16, $17, $ra, 8($sp)     # encoding: [0x45,0x12]
 # CHECK-EB: swm16  $16, $17, $ra, 8($sp)     # encoding: [0x45,0x52]
+# CHECK-EB: lwm16  $16, $17, $ra, 8($sp)     # encoding: [0x45,0x12]
+# CHECK-EB: lwm32  $16, $17, $ra, 64($sp)    # encoding: [0x22,0x5d,0x50,0x40]
+# CHECK-EB: lwm32  $16, $17, $ra, 8($4)      # encoding: [0x22,0x44,0x50,0x08]
+# CHECK-EB: lwm32  $16, $17, 8($sp)          # encoding: [0x20,0x5d,0x50,0x08]
+# CHECK-EB: swm16  $16, $17, $ra, 8($sp)     # encoding: [0x45,0x52]
+# CHECK-EB: swm32  $16, $17, $ra, 64($sp)    # encoding: [0x22,0x5d,0xd0,0x40]
+# CHECK-EB: swm32  $16, $17, $ra, 8($4)      # encoding: [0x22,0x44,0xd0,0x08]
+# CHECK-EB: swm32  $16, $17, 8($sp)          # encoding: [0x20,0x5d,0xd0,0x08]
 # CHECK-EB: swp    $16, 8($4)                # encoding: [0x22,0x04,0x90,0x08]
 # CHECK-EB: lwp    $16, 8($4)                # encoding: [0x22,0x04,0x10,0x08]
      lb     $5, 8($4)
@@ -74,6 +92,7 @@
      sh     $2, 8($4)
      sw     $5, 4($6)
      sw     $5, 123($sp)
+     sw     $3, 32($gp)
      ll     $2, 8($4)
      sc     $2, 8($4)
      lwu    $2, 8($4)
@@ -88,5 +107,13 @@
      swm32  $16 - $19, 8($4)
      lwm16  $16, $17, $ra, 8($sp)
      swm16  $16, $17, $ra, 8($sp)
+     lwm    $16, $17, $ra, 8($sp)
+     lwm    $16, $17, $ra, 64($sp)
+     lwm    $16, $17, $ra, 8($4)
+     lwm    $16, $17, 8($sp)
+     swm    $16, $17, $ra, 8($sp)
+     swm    $16, $17, $ra, 64($sp)
+     swm    $16, $17, $ra, 8($4)
+     swm    $16, $17, 8($sp)
      swp    $16, 8($4)
      lwp    $16, 8($4)
diff --git a/test/MC/Mips/micromips32r6/valid.s b/test/MC/Mips/micromips32r6/valid.s
new file mode 100644
index 000000000000..f4e8eef8f23b
--- /dev/null
+++ b/test/MC/Mips/micromips32r6/valid.s
@@ -0,0 +1,50 @@
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
+
+  .set noat
+  add $3, $4, $5           # CHECK: add $3, $4, $5      # encoding: [0x00,0xa4,0x19,0x10]
+  addiu $3, $4, 1234       # CHECK: addiu $3, $4, 1234  # encoding: [0x30,0x64,0x04,0xd2]
+  addu $3, $4, $5          # CHECK: addu $3, $4, $5     # encoding: [0x00,0xa4,0x19,0x50]
+  addiupc $4, 100          # CHECK: addiupc $4, 100     # encoding: [0x78,0x80,0x00,0x19]
+  aluipc $3, 56            # CHECK: aluipc $3, 56       # encoding: [0x78,0x7f,0x00,0x38]
+  and $3, $4, $5           # CHECK: and $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0x50]
+  andi $3, $4, 1234        # CHECK: andi $3, $4, 1234   # encoding: [0xd0,0x64,0x04,0xd2]
+  auipc $3, -1             # CHECK: auipc $3, -1        # encoding: [0x78,0x7e,0xff,0xff]
+  align $4, $2, $3, 2      # CHECK: align $4, $2, $3, 2 # encoding: [0x00,0x43,0x24,0x1f]
+  aui $3,$2,-23            # CHECK: aui $3, $2, -23     # encoding: [0x10,0x62,0xff,0xe9]
+  beqzalc $2, 1332         # CHECK: beqzalc $2, 1332    # encoding: [0x74,0x40,0x02,0x9a]
+  bnezalc $2, 1332         # CHECK: bnezalc $2, 1332    # encoding: [0x7c,0x40,0x02,0x9a]
+  bgezalc $2, 1332         # CHECK: bgezalc $2, 1332    # encoding: [0xc0,0x42,0x02,0x9a]
+  bgtzalc $2, 1332         # CHECK: bgtzalc $2, 1332    # encoding: [0xe0,0x40,0x02,0x9a]
+  bltzalc $2, 1332         # CHECK: bltzalc $2, 1332    # encoding: [0xe0,0x42,0x02,0x9a]
+  blezalc $2, 1332         # CHECK: blezalc $2, 1332    # encoding: [0xc0,0x40,0x02,0x9a]
+  balc 14572256            # CHECK: balc 14572256       # encoding: [0xb4,0x37,0x96,0xb8]
+  bc 14572256              # CHECK: bc 14572256         # encoding: [0x94,0x37,0x96,0xb8]
+  bitswap $4, $2           # CHECK: bitswap $4, $2      # encoding: [0x00,0x44,0x0b,0x3c]
+  cache 1, 8($5)           # CHECK: cache 1, 8($5)      # encoding: [0x20,0x25,0x60,0x08]
+  clo $11, $a1             # CHECK: clo $11, $5         # encoding: [0x01,0x65,0x4b,0x3c]
+  clz $sp, $gp             # CHECK: clz $sp, $gp        # encoding: [0x03,0x80,0xe8,0x50]
+  div $3, $4, $5           # CHECK: div $3, $4, $5      # encoding: [0x00,0xa4,0x19,0x18]
+  divu $3, $4, $5          # CHECK: divu $3, $4, $5     # encoding: [0x00,0xa4,0x19,0x98]
+  jialc $5, 256            # CHECK: jialc $5, 256       # encoding: [0x80,0x05,0x01,0x00]
+  jic   $5, 256            # CHECK: jic $5, 256         # encoding: [0xa0,0x05,0x01,0x00]
+  lsa $2, $3, $4, 3        # CHECK: lsa  $2, $3, $4, 3  # encoding: [0x00,0x43,0x26,0x0f]
+  lwpc    $2,268           # CHECK: lwpc $2, 268        # encoding: [0x78,0x48,0x00,0x43]
+  mod $3, $4, $5           # CHECK: mod $3, $4, $5      # encoding: [0x00,0xa4,0x19,0x58]
+  modu $3, $4, $5          # CHECK: modu $3, $4, $5     # encoding: [0x00,0xa4,0x19,0xd8]
+  mul $3, $4, $5           # CHECK mul $3, $4, $5       # encoding: [0x00,0xa4,0x18,0x18]
+  muh $3, $4, $5           # CHECK muh $3, $4, $5       # encoding: [0x00,0xa4,0x18,0x58]
+  mulu $3, $4, $5          # CHECK mulu $3, $4, $5      # encoding: [0x00,0xa4,0x18,0x98]
+  muhu $3, $4, $5          # CHECK muhu $3, $4, $5      # encoding: [0x00,0xa4,0x18,0xd8]
+  nor $3, $4, $5           # CHECK: nor $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0xd0]
+  or $3, $4, $5            # CHECK: or $3, $4, $5       # encoding: [0x00,0xa4,0x1a,0x90]
+  ori $3, $4, 1234         # CHECK: ori $3, $4, 1234    # encoding: [0x50,0x64,0x04,0xd2]
+  pref 1, 8($5)            # CHECK: pref 1, 8($5)       # encoding: [0x60,0x25,0x20,0x08]
+  seb $3, $4               # CHECK: seb $3, $4          # encoding: [0x00,0x64,0x2b,0x3c]
+  seh $3, $4               # CHECK: seh $3, $4          # encoding: [0x00,0x64,0x3b,0x3c]
+  seleqz $2,$3,$4          # CHECK: seleqz $2, $3, $4   # encoding: [0x00,0x83,0x11,0x40]
+  selnez $2,$3,$4          # CHECK: selnez $2, $3, $4   # encoding: [0x00,0x83,0x11,0x80]
+  sub $3, $4, $5           # CHECK: sub $3, $4, $5      # encoding: [0x00,0xa4,0x19,0x90]
+  subu $3, $4, $5          # CHECK: subu $3, $4, $5     # encoding: [0x00,0xa4,0x19,0xd0]
+  xor $3, $4, $5           # CHECK: xor $3, $4, $5      # encoding: [0x00,0xa4,0x1b,0x10]
+  xori $3, $4, 1234        # CHECK: xori $3, $4, 1234   # encoding: [0x70,0x64,0x04,0xd2]
+
diff --git a/test/MC/Mips/mips-abi-bad.s b/test/MC/Mips/mips-abi-bad.s
index ba6564fb7e1b..0e065bfba708 100644
--- a/test/MC/Mips/mips-abi-bad.s
+++ b/test/MC/Mips/mips-abi-bad.s
@@ -22,9 +22,3 @@
 # CHECK: :[[@LINE-1]]:13: error: expected .module option identifier
 # CHECK-NEXT: .module 34
 # CHECK-NEXT:         ^
-
-    .set mips16
-    .module fp=32
-# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
-# CHECK-NEXT: .module fp=32
-# CHECK-NEXT:         ^
diff --git a/test/MC/Mips/mips-data-directives.s b/test/MC/Mips/mips-data-directives.s
index 8b3e0b3aa19a..abff7c21c611 100644
--- a/test/MC/Mips/mips-data-directives.s
+++ b/test/MC/Mips/mips-data-directives.s
@@ -12,7 +12,7 @@
 
 # Checking if the data and reloations were correctly emitted
 # CHECK-OBJ:  Section {
-# CHECK-OBJ:    Name: .data (66)
+# CHECK-OBJ:    Name: .data
 # CHECK-OBJ:    SectionData (
 # CHECK-OBJ:      0000: DEADC0DE DEADC0DE DEADBEEF 00000000
 # CHECK-OBJ:      0010: 00000000 00000000
@@ -20,7 +20,7 @@
 # CHECK-OBJ:  }
 
 # CHECK-OBJ:  Section {
-# CHECK-OBJ:    Name: .rel.data (62)
+# CHECK-OBJ:    Name: .rel.data
 # CHECK-OBJ:    Relocations [
 # CHECK-OBJ:      0xC R_MIPS_32 .data 0x0
 # CHECK-OBJ:      0x10 R_MIPS_64 .data 0x0
diff --git a/test/MC/Mips/mips-expansions-bad.s b/test/MC/Mips/mips-expansions-bad.s
index 8d8516926f2d..6bbde263f5f8 100644
--- a/test/MC/Mips/mips-expansions-bad.s
+++ b/test/MC/Mips/mips-expansions-bad.s
@@ -1,6 +1,24 @@
 # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
-# RUN: FileCheck %s < %t1
+# RUN: FileCheck %s < %t1 --check-prefix=32-BIT
+# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 | \
+# RUN:   FileCheck %s --check-prefix=64-BIT --check-prefix=N32-ONLY
+# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 | \
+# RUN:   FileCheck %s --check-prefix=64-BIT --check-prefix=N64-ONLY
 
-        .text
-        li $5, 0x100000000 # CHECK: :[[@LINE]]:9: error: instruction requires a 64-bit architecture
-        dli $5, 1 # CHECK: :[[@LINE]]:9: error: instruction requires a 64-bit architecture
+  .text
+  li $5, 0x100000000
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
+  # 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
+  la $5, 0x100000000
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
+  # 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
+  la $5, 0x100000000($6)
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
+  # 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
+  la $5, symbol
+  # N64-ONLY: :[[@LINE-1]]:3: warning: instruction loads the 32-bit address of a 64-bit symbol
+  # N32-ONLY-NOT: :[[@LINE-2]]:3: warning: instruction loads the 32-bit address of a 64-bit symbol
+  # 64-BIT: lui $5, %hi(symbol)
+  # 64-BIT: ori $5, $5, %lo(symbol)
+  dli $5, 1
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
diff --git a/test/MC/Mips/mips-expansions.s b/test/MC/Mips/mips-expansions.s
index bdc76fb44fa1..b6dc32ed5e34 100644
--- a/test/MC/Mips/mips-expansions.s
+++ b/test/MC/Mips/mips-expansions.s
@@ -4,35 +4,27 @@
 #------------------------------------------------------------------------------
 # Load immediate instructions
 #------------------------------------------------------------------------------
-# CHECK: ori     $5, $zero, 123      # encoding: [0x7b,0x00,0x05,0x34]
-# CHECK: addiu   $6, $zero, -2345    # encoding: [0xd7,0xf6,0x06,0x24]
-# CHECK: lui     $7, 1               # encoding: [0x01,0x00,0x07,0x3c]
-# CHECK: ori     $7, $7, 2           # encoding: [0x02,0x00,0xe7,0x34]
-# CHECK: addiu   $8, $zero, -8       # encoding: [0xf8,0xff,0x08,0x24]
+# CHECK:     ori     $5, $zero, 123   # encoding: [0x7b,0x00,0x05,0x34]
+# CHECK:     addiu   $6, $zero, -2345 # encoding: [0xd7,0xf6,0x06,0x24]
+# CHECK:     lui     $7, 1            # encoding: [0x01,0x00,0x07,0x3c]
+# CHECK:     ori     $7, $7, 2        # encoding: [0x02,0x00,0xe7,0x34]
+# CHECK:     addiu   $8, $zero, -8    # encoding: [0xf8,0xff,0x08,0x24]
+# CHECK:     lui     $9, 1            # encoding: [0x01,0x00,0x09,0x3c]
+# CHECK-NOT: ori $9, $9, 0            # encoding: [0x00,0x00,0x29,0x35]
+# CHECK:     lui     $10, 65519       # encoding: [0xef,0xff,0x0a,0x3c]
+# CHECK:     ori     $10, $10, 61423  # encoding: [0xef,0xef,0x4a,0x35]
 
-# CHECK: addiu   $4, $zero, 20       # encoding: [0x14,0x00,0x04,0x24]
+# CHECK: ori     $4, $zero, 20       # encoding: [0x14,0x00,0x04,0x34]
 # CHECK: lui     $7, 1               # encoding: [0x01,0x00,0x07,0x3c]
 # CHECK: ori     $7, $7, 2           # encoding: [0x02,0x00,0xe7,0x34]
-# CHECK: addiu   $4, $5, 20          # encoding: [0x14,0x00,0xa4,0x24]
+# CHECK: ori     $4, $5, 20          # encoding: [0x14,0x00,0xa4,0x34]
 # CHECK: lui     $7, 1               # encoding: [0x01,0x00,0x07,0x3c]
 # CHECK: ori     $7, $7, 2           # encoding: [0x02,0x00,0xe7,0x34]
 # CHECK: addu    $7, $7, $8          # encoding: [0x21,0x38,0xe8,0x00]
 # CHECK: lui     $8, %hi(symbol)     # encoding: [A,A,0x08,0x3c]
-                                     #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
+# CHECK:                             #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
 # CHECK: ori     $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35]
-                                     #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
-# CHECK: .set    mips64
-# CHECK: lui     $8, %highest(symbol)    # encoding: [A,A,0x08,0x3c]
-                                         #   fixup A - offset: 0, value: symbol@HIGHEST, kind: fixup_Mips_HIGHEST
-# CHECK: ori     $8, $8, %higher(symbol) # encoding: [A,A,0x08,0x35]
-                                         #   fixup A - offset: 0, value: symbol@HIGHER, kind: fixup_Mips_HIGHER
-# CHECK: dsll    $8, $8, 16              # encoding: [0x38,0x44,0x08,0x00]
-# CHECK: ori     $8, $8, %hi(symbol)     # encoding: [A,A,0x08,0x35]
-                                         #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
-# CHECK: dsll    $8, $8, 16              # encoding: [0x38,0x44,0x08,0x00]
-# CHECK: ori     $8, $8, %lo(symbol)     # encoding: [A,A,0x08,0x35]
-                                         #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
-# CHECK: .set    mips32r2
+# CHECK:                             #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
 # CHECK: lui     $10, %hi(symbol)        # encoding: [A,A,0x0a,0x3c]
 # CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
 # CHECK: addu    $10, $10, $4            # encoding: [0x21,0x50,0x44,0x01]
@@ -50,6 +42,17 @@
 # CHECK: addu    $1, $1, $9              # encoding: [0x21,0x08,0x29,0x00]
 # CHECK: sw      $10, 57920($1)          # encoding: [0x40,0xe2,0x2a,0xac]
 
+# CHECK:     lui     $8, %hi(symbol)     # encoding: [A,A,0x08,0x3c]
+# CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
+# CHECK-NOT: move    $8, $8              # encoding: [0x21,0x40,0x00,0x01]
+# CHECK:     lw      $8, %lo(symbol)($8) # encoding: [A,A,0x08,0x8d]
+# CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
+# CHECK:     lui     $1, %hi(symbol)     # encoding: [A,A,0x01,0x3c]
+# CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
+# CHECK-NOT: move    $1, $1              # encoding: [0x21,0x08,0x20,0x00]
+# CHECK:     sw      $8, %lo(symbol)($1) # encoding: [A,A,0x28,0xac]
+# CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
+
 # CHECK: lui     $1, %hi(symbol)
 # CHECK: ldc1    $f0, %lo(symbol)($1)
 # CHECK: lui     $1, %hi(symbol)
@@ -59,15 +62,14 @@
     li $6,-2345
     li $7,65538
     li $8, ~7
+    li $9, 0x10000
+    li $10, ~(0x101010)
 
     la $a0, 20
     la $7,65538
     la $a0, 20($a1)
     la $7,65538($8)
     la $t0, symbol
-    .set mips64
-    la $t0, symbol
-    .set mips32r2
 
     .set noat
     lw  $t2, symbol($a0)
@@ -77,5 +79,8 @@
     lw  $t2, 655483($a0)
     sw  $t2, 123456($t1)
 
+    lw  $8, symbol
+    sw  $8, symbol
+
     ldc1 $f0, symbol
     sdc1 $f0, symbol
diff --git a/test/MC/Mips/mips-jump-delay-slots.s b/test/MC/Mips/mips-jump-delay-slots.s
index 49f6c159b680..c52416fe1564 100644
--- a/test/MC/Mips/mips-jump-delay-slots.s
+++ b/test/MC/Mips/mips-jump-delay-slots.s
@@ -68,9 +68,15 @@
         # CHECK: beql $9, $6, 1332
         # CHECK-NOT: nop
         beql $9,$6,1332
+        # CHECK: beql $9, $zero, 1332
+        # CHECK-NOT: nop
+        beqzl $9,1332
         # CHECK: bnel $9, $6, 1332
         # CHECK-NOT: nop
         bnel $9,$6,1332
+        # CHECK: bnel $9, $zero, 1332
+        # CHECK-NOT: nop
+        bnezl $9,1332
         # CHECK: bgezl $6, 1332
         # CHECK-NOT: nop
         bgezl $6,1332
diff --git a/test/MC/Mips/mips-noat.s b/test/MC/Mips/mips-noat.s
index f9d4efde185c..3a937c73eeb5 100644
--- a/test/MC/Mips/mips-noat.s
+++ b/test/MC/Mips/mips-noat.s
@@ -7,6 +7,8 @@
 # CHECK:  lui   $1, 1
 # CHECK:  addu  $1, $1, $2
 # CHECK:  lw    $2, 0($1)
+# CHECK-LABEL: test2:
+# CHECK:  .set noat
 test1:
         lw      $2, 65536($2)
 
@@ -20,6 +22,8 @@ test2:
 # CHECK:  lui   $1, 1
 # CHECK:  addu  $1, $1, $2
 # CHECK:  lw    $2, 0($1)
+# CHECK-LABEL: test4:
+# CHECK:  .set  at=$0
 test3:
         .set at
         lw      $2, 65536($2)
diff --git a/test/MC/Mips/mips-reginfo-fp64.s b/test/MC/Mips/mips-reginfo-fp64.s
index b60e54ea405c..ba2bf7973943 100644
--- a/test/MC/Mips/mips-reginfo-fp64.s
+++ b/test/MC/Mips/mips-reginfo-fp64.s
@@ -2,11 +2,11 @@
 # RUN:   llvm-readobj -s -section-data | \
 # RUN:     FileCheck %s -check-prefix=ELF32
 
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64,-n64,+n32 -filetype=obj -o - | \
+# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n32 -filetype=obj -o - | \
 # RUN:   llvm-readobj -s -section-data | \
 # RUN:     FileCheck %s -check-prefix=ELF32
 
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64,+n64 -filetype=obj -o - | \
+# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n64 -filetype=obj -o - | \
 # RUN:   llvm-readobj -s -section-data | \
 # RUN:     FileCheck %s -check-prefix=ELF64
 
diff --git a/test/MC/Mips/mips1/invalid-mips3.s b/test/MC/Mips/mips1/invalid-mips3.s
index d4be08e48fbd..d9400edaa17c 100644
--- a/test/MC/Mips/mips1/invalid-mips3.s
+++ b/test/MC/Mips/mips1/invalid-mips3.s
@@ -26,6 +26,9 @@
         dmfc1     $12,$f13          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dmtc1     $s0,$f14          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dmultu    $a1,$a2           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dneg      $2                # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dneg      $2,$3             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dnegu     $2,$3             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll      $zero,18          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll      $zero,$s4,18      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll      $zero,$s4,$12     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/test/MC/Mips/mips1/valid.s b/test/MC/Mips/mips1/valid.s
index 53ff6a0740a3..e2feeac4dd56 100644
--- a/test/MC/Mips/mips1/valid.s
+++ b/test/MC/Mips/mips1/valid.s
@@ -1,7 +1,7 @@
 # Instructions that are valid
 #
 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s
-
+a:
         .set noat
         abs.d     $f7,$f25             # CHECK: encoding:
         abs.s     $f9,$f16
@@ -41,6 +41,11 @@
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
         ehb                            # CHECK: ehb # encoding:  [0x00,0x00,0x00,0xc0]
+        j         1f                   # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
+        j         a                    # CHECK: j a     # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
+        j         1328                 # CHECK: j 1328  # encoding: [0x08,0x00,0x01,0x4c]
         lb        $24,-14515($10)
         lbu       $8,30195($v1)
         lh        $11,-8556($s5)
@@ -116,3 +121,6 @@
         tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
         tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
         xor       $s2,$a0,$s8
+        xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
+
+1:
diff --git a/test/MC/Mips/mips2/invalid-mips3.s b/test/MC/Mips/mips2/invalid-mips3.s
index e72b228c67ec..67f9d5399841 100644
--- a/test/MC/Mips/mips2/invalid-mips3.s
+++ b/test/MC/Mips/mips2/invalid-mips3.s
@@ -22,6 +22,9 @@
         dmfc1      $t0,$f13          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dmtc1      $s0,$f14          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dmultu     $a1,$a2           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dneg       $2                # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dneg       $2,$3             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dnegu      $2,$3             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll       $zero,18          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll       $zero,$s4,18      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll       $zero,$s4,$t0     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/test/MC/Mips/mips2/valid.s b/test/MC/Mips/mips2/valid.s
index 34843bc9f777..93fdbafdfcd0 100644
--- a/test/MC/Mips/mips2/valid.s
+++ b/test/MC/Mips/mips2/valid.s
@@ -1,7 +1,7 @@
 # Instructions that are valid
 #
 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s
-
+a:
         .set noat
         abs.d     $f7,$f25             # CHECK: encoding:
         abs.s     $f9,$f16
@@ -57,6 +57,11 @@
         ehb                            # CHECK: ehb # encoding:  [0x00,0x00,0x00,0xc0]
         floor.w.d $f14,$f11
         floor.w.s $f8,$f9
+        j         1f                   # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
+        j         a                    # CHECK: j a     # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
+        j         1328                 # CHECK: j 1328  # encoding: [0x08,0x00,0x01,0x4c]
         lb        $24,-14515($10)
         lbu       $8,30195($v1)
         ldc1      $f11,16391($s0)
@@ -165,3 +170,6 @@
         trunc.w.d $f22,$f15
         trunc.w.s $f28,$f30
         xor       $s2,$a0,$s8
+        xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
+
+1:
diff --git a/test/MC/Mips/mips3/valid.s b/test/MC/Mips/mips3/valid.s
index a55576d9e673..1c878c97d158 100644
--- a/test/MC/Mips/mips3/valid.s
+++ b/test/MC/Mips/mips3/valid.s
@@ -1,7 +1,7 @@
 # Instructions that are valid
 #
 # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 | FileCheck %s
-
+a:
         .set noat
         abs.d     $f7,$f25             # CHECK: encoding:
         abs.s     $f9,$f16
@@ -77,6 +77,9 @@
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
         dsll      $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
         dsll      $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
@@ -109,6 +112,11 @@
         floor.l.s $f12,$f5
         floor.w.d $f14,$f11
         floor.w.s $f8,$f9
+        j         1f                   # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
+        j         a                    # CHECK: j a     # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
+        j         1328                 # CHECK: j 1328  # encoding: [0x08,0x00,0x01,0x4c]
         lb        $24,-14515($10)
         lbu       $8,30195($v1)
         ld        $sp,-28645($s1)
@@ -228,3 +236,6 @@
         trunc.w.d $f22,$f15
         trunc.w.s $f28,$f30
         xor       $s2,$a0,$s8
+        xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
+
+1:
diff --git a/test/MC/Mips/mips32/invalid-mips64.s b/test/MC/Mips/mips32/invalid-mips64.s
index 41040edb7db1..0af782060a9e 100644
--- a/test/MC/Mips/mips32/invalid-mips64.s
+++ b/test/MC/Mips/mips32/invalid-mips64.s
@@ -7,3 +7,6 @@
 	.set noat
 	dclo	$s2,$a2    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
 	dclz	$s0,$t9    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dneg      $2       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dneg      $2,$3    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dnegu     $2,$3    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/test/MC/Mips/mips32/valid.s b/test/MC/Mips/mips32/valid.s
index d79c390c47ec..3765044339c9 100644
--- a/test/MC/Mips/mips32/valid.s
+++ b/test/MC/Mips/mips32/valid.s
@@ -1,7 +1,7 @@
 # Instructions that are valid
 #
 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
-
+a:
         .set noat
         abs.d     $f7,$f25             # CHECK: encoding:
         abs.s     $f9,$f16
@@ -66,6 +66,11 @@
         eret
         floor.w.d $f14,$f11
         floor.w.s $f8,$f9
+        j         1f                   # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
+        j         a                    # CHECK: j a     # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
+        j         1328                 # CHECK: j 1328  # encoding: [0x08,0x00,0x01,0x4c]
         lb        $24,-14515($10)
         lbu       $8,30195($v1)
         ldc1      $f11,16391($s0)
@@ -195,3 +200,6 @@
         trunc.w.d $f22,$f15
         trunc.w.s $f28,$f30
         xor       $s2,$a0,$s8
+        xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
+
+1:
diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s
index 97cfa36e7122..ee7af3f3ec00 100644
--- a/test/MC/Mips/mips32r2/valid.s
+++ b/test/MC/Mips/mips32r2/valid.s
@@ -1,7 +1,7 @@
 # Instructions that are valid
 #
 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
-
+a:
         .set noat
         abs.d     $f7,$f25             # CHECK: encoding:
         abs.s     $f9,$f16
@@ -72,6 +72,11 @@
         eret
         floor.w.d $f14,$f11
         floor.w.s $f8,$f9
+        j         1f                   # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
+        j         a                    # CHECK: j a     # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
+        j         1328                 # CHECK: j 1328  # encoding: [0x08,0x00,0x01,0x4c]
         jr.hb     $4                   # CHECK: jr.hb  $4 # encoding: [0x00,0x80,0x04,0x08]
         jalr.hb   $4                   # CHECK: jalr.hb  $4 # encoding: [0x00,0x80,0xfc,0x09]
         jalr.hb   $4, $5               # CHECK: jalr.hb  $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
@@ -233,4 +238,7 @@
         trunc.w.s $f28,$f30
         wsbh      $k1,$9
         xor       $s2,$a0,$s8
+        xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
         synci     -15842($a2)          # CHECK: synci -15842($6)        # encoding: [0x04,0xdf,0xc2,0x1e]
+
+1:
diff --git a/test/MC/Mips/mips32r3/abiflags.s b/test/MC/Mips/mips32r3/abiflags.s
new file mode 100644
index 000000000000..a6c7057809f5
--- /dev/null
+++ b/test/MC/Mips/mips32r3/abiflags.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r3 | \
+# RUN:   FileCheck %s -check-prefix=CHECK-ASM
+#
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r3 -filetype=obj -o - | \
+# RUN:   llvm-readobj -sections -section-data -section-relocations - | \
+# RUN:     FileCheck %s -check-prefix=CHECK-OBJ
+
+# CHECK-ASM: .module fp=32
+# CHECK-ASM: .set fp=64
+
+# Checking if the Mips.abiflags were correctly emitted.
+# CHECK-OBJ:       Section {
+# CHECK-OBJ:         Index: 5
+# CHECK-OBJ-LABEL:   Name: .MIPS.abiflags (12)
+# CHECK-OBJ:         Type: SHT_MIPS_ABIFLAGS (0x7000002A)
+# CHECK-OBJ:          Flags [ (0x2)
+# CHECK-OBJ:           SHF_ALLOC (0x2)
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         Address: 0x0
+# CHECK-OBJ:         Size: 24
+# CHECK-OBJ:         Link: 0
+# CHECK-OBJ:         Info: 0
+# CHECK-OBJ:         AddressAlignment: 8
+# CHECK-OBJ:         EntrySize: 24
+# CHECK-OBJ:         Relocations [
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         SectionData (
+# CHECK-OBJ:           0000: 00002003 01010001 00000000 00000000  |.. .............|
+# CHECK-OBJ:           0010: 00000001 00000000                    |........|
+# CHECK-OBJ:         )
+# CHECK-OBJ-LABEL: }
+
+        .module fp=32
+        .set fp=64
+# FIXME: Test should include gnu_attributes directive when implemented.
+#        An explicit .gnu_attribute must be checked against the effective
+#        command line options and any inconsistencies reported via a warning.
diff --git a/test/MC/Mips/mips32r3/invalid-mips64r2.s b/test/MC/Mips/mips32r3/invalid-mips64r2.s
new file mode 100644
index 000000000000..0f007e27748a
--- /dev/null
+++ b/test/MC/Mips/mips32r3/invalid-mips64r2.s
@@ -0,0 +1,10 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding \
+# RUN:     -mcpu=mips32r3 2>%t1
+# RUN: FileCheck %s < %t1
+
+	.set noat
+	dsbh	$v1,$t6    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+	dshd	$v0,$sp    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+
diff --git a/test/MC/Mips/mips32r3/invalid.s b/test/MC/Mips/mips32r3/invalid.s
new file mode 100644
index 000000000000..f67f4c55ecb3
--- /dev/null
+++ b/test/MC/Mips/mips32r3/invalid.s
@@ -0,0 +1,10 @@
+# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g.
+# invalid set of operands or operand's restrictions not met).
+
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r3 2>%t1
+# RUN: FileCheck %s < %t1 -check-prefix=ASM
+
+        .text
+        .set noreorder
+        jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
+        jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
diff --git a/test/MC/Mips/mips32r3/valid-xfail.s b/test/MC/Mips/mips32r3/valid-xfail.s
new file mode 100644
index 000000000000..b0fc3a1d23f7
--- /dev/null
+++ b/test/MC/Mips/mips32r3/valid-xfail.s
@@ -0,0 +1,308 @@
+# Instructions that should be valid but currently fail for known reasons (e.g.
+# they aren't implemented yet).
+# This test is set up to XPASS if any instruction generates an encoding.
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 | not FileCheck %s
+# CHECK-NOT: encoding
+# XFAIL: *
+
+        .set noat
+        abs.ps          $f22,$f8
+        absq_s.ph       $8,$a0
+        absq_s.qb       $15,$s1
+        absq_s.w        $s3,$ra
+        add.ps          $f25,$f27,$f13
+        addq.ph         $s1,$15,$at
+        addq_s.ph       $s3,$s6,$s2
+        addq_s.w        $a2,$8,$at
+        addqh.ph        $s4,$14,$s1
+        addqh.w         $s7,$s7,$k1
+        addqh_r.ph      $sp,$25,$s8
+        addqh_r.w       $8,$v1,$zero
+        addsc           $s8,$15,$12
+        addu.ph         $a2,$14,$s3
+        addu.qb         $s6,$v1,$v1
+        addu_s.ph       $a3,$s3,$gp
+        addu_s.qb       $s4,$s8,$s1
+        adduh.qb        $a1,$a1,$at
+        adduh_r.qb      $a0,$9,$12
+        addwc           $k0,$s6,$s7
+        alnv.ps         $f12,$f18,$f30,$12
+        and.v           $w10,$w25,$w29
+        bitrev          $14,$at
+        bmnz.v          $w15,$w2,$w28
+        bmz.v           $w13,$w11,$w21
+        bsel.v          $w28,$w7,$w0
+        c.eq.d          $fcc1,$f15,$f15
+        c.eq.ps         $fcc5,$f0,$f9
+        c.eq.s          $fcc5,$f24,$f17
+        c.f.d           $fcc4,$f11,$f21
+        c.f.ps          $fcc6,$f11,$f11
+        c.f.s           $fcc4,$f30,$f7
+        c.le.d          $fcc4,$f18,$f1
+        c.le.ps         $fcc1,$f7,$f20
+        c.le.s          $fcc6,$f24,$f4
+        c.lt.d          $fcc3,$f9,$f3
+        c.lt.ps         $f19,$f5
+        c.lt.s          $fcc2,$f17,$f14
+        c.nge.d         $fcc5,$f21,$f16
+        c.nge.ps        $f1,$f26
+        c.nge.s         $fcc3,$f11,$f8
+        c.ngl.ps        $f21,$f30
+        c.ngl.s         $fcc2,$f31,$f23
+        c.ngle.ps       $fcc7,$f12,$f20
+        c.ngle.s        $fcc2,$f18,$f23
+        c.ngt.d         $fcc4,$f24,$f7
+        c.ngt.ps        $fcc5,$f30,$f6
+        c.ngt.s         $fcc5,$f8,$f13
+        c.ole.d         $fcc2,$f16,$f31
+        c.ole.ps        $fcc7,$f21,$f8
+        c.ole.s         $fcc3,$f7,$f20
+        c.olt.d         $fcc4,$f19,$f28
+        c.olt.ps        $fcc3,$f7,$f16
+        c.olt.s         $fcc6,$f20,$f7
+        c.seq.d         $fcc4,$f31,$f7
+        c.seq.ps        $fcc6,$f31,$f14
+        c.seq.s         $fcc7,$f1,$f25
+        c.sf.ps         $fcc6,$f4,$f6
+        c.ueq.d         $fcc4,$f13,$f25
+        c.ueq.ps        $fcc1,$f5,$f29
+        c.ueq.s         $fcc6,$f3,$f30
+        c.ule.d         $fcc7,$f25,$f18
+        c.ule.ps        $fcc6,$f17,$f3
+        c.ule.s         $fcc7,$f21,$f30
+        c.ult.d         $fcc6,$f6,$f17
+        c.ult.ps        $fcc7,$f14,$f0
+        c.ult.s         $fcc7,$f24,$f10
+        c.un.d          $fcc6,$f23,$f24
+        c.un.ps         $fcc4,$f2,$f26
+        c.un.s          $fcc1,$f30,$f4
+        ceil.l.d        $f1,$f3
+        ceil.l.s        $f18,$f13
+        cfcmsa          $s6,$19
+        cmp.eq.ph       $s7,$14
+        cmp.le.ph       $8,$14
+        cmp.lt.ph       $k0,$sp
+        cmpgdu.eq.qb    $s3,$zero,$k0
+        cmpgdu.le.qb    $v1,$15,$s2
+        cmpgdu.lt.qb    $s0,$gp,$sp
+        cmpgu.eq.qb     $14,$s6,$s8
+        cmpgu.le.qb     $9,$a3,$s4
+        cmpgu.lt.qb     $sp,$at,$8
+        cmpu.eq.qb      $v0,$24
+        cmpu.le.qb      $s1,$a1
+        cmpu.lt.qb      $at,$a3
+        ctcmsa          $31,$s7
+        cvt.d.l         $f4,$f16
+        cvt.ps.s        $f3,$f18,$f19
+        cvt.s.l         $f15,$f30
+        cvt.s.pl        $f30,$f1
+        cvt.s.pu        $f14,$f25
+        dmt $k0
+        dpa.w.ph        $ac1,$s7,$k0
+        dpaq_s.w.ph     $ac2,$a0,$13
+        dpaq_sa.l.w     $ac0,$a2,$14
+        dpaqx_s.w.ph    $ac3,$a0,$24
+        dpaqx_sa.w.ph   $ac1,$zero,$s5
+        dpau.h.qbl      $ac1,$10,$24
+        dpau.h.qbr      $ac1,$s7,$s6
+        dpax.w.ph       $ac3,$a0,$k0
+        dps.w.ph        $ac1,$a3,$a1
+        dpsq_s.w.ph     $ac0,$gp,$k0
+        dpsq_sa.l.w     $ac0,$a3,$15
+        dpsqx_s.w.ph    $ac3,$13,$a3
+        dpsqx_sa.w.ph   $ac3,$sp,$s2
+        dpsu.h.qbl      $ac2,$14,$10
+        dpsu.h.qbr      $ac2,$a1,$s6
+        dpsx.w.ph       $ac0,$s7,$gp
+        dvpe            $s6
+        emt $8
+        evpe            $v0
+        extpdpv         $s6,$ac0,$s8
+        extpv           $13,$ac0,$14
+        extrv.w         $8,$ac3,$at
+        extrv_r.w       $8,$ac1,$s6
+        extrv_rs.w      $gp,$ac1,$s6
+        extrv_s.h       $s2,$ac1,$14
+        fclass.d        $w14,$w27
+        fclass.w        $w19,$w28
+        fexupl.d        $w10,$w29
+        fexupl.w        $w12,$w27
+        fexupr.d        $w31,$w15
+        fexupr.w        $w29,$w12
+        ffint_s.d       $w1,$w30
+        ffint_s.w       $w16,$w14
+        ffint_u.d       $w23,$w18
+        ffint_u.w       $w19,$w12
+        ffql.d          $w2,$w3
+        ffql.w          $w9,$w0
+        ffqr.d          $w25,$w24
+        ffqr.w          $w10,$w6
+        fill.b          $w9,$v1
+        fill.h          $w9,$8
+        fill.w          $w31,$15
+        flog2.d         $w12,$w16
+        flog2.w         $w19,$w23
+        floor.l.d       $f26,$f7
+        floor.l.s       $f12,$f5
+        fork            $s2,$8,$a0
+        frcp.d          $w12,$w4
+        frcp.w          $w30,$w8
+        frint.d         $w20,$w8
+        frint.w         $w11,$w29
+        frsqrt.d        $w29,$w2
+        frsqrt.w        $w9,$w8
+        fsqrt.d         $w3,$w1
+        fsqrt.w         $w5,$w15
+        ftint_s.d       $w31,$w26
+        ftint_s.w       $w27,$w14
+        ftint_u.d       $w5,$w31
+        ftint_u.w       $w12,$w29
+        ftrunc_s.d      $w4,$w22
+        ftrunc_s.w      $w24,$w7
+        ftrunc_u.d      $w20,$w25
+        ftrunc_u.w      $w7,$w26
+        insv            $s2,$at
+        iret
+        lbe             $14,122($9)
+        lbue            $11,-108($10)
+        lbux            $9,$14($v0)
+        lhe             $s6,219($v1)
+        lhue            $gp,118($11)
+        lhx             $sp,$k0($15)
+        lle             $gp,-237($ra)
+        lwe             $ra,-145($14)
+        lwle            $11,-42($11)
+        lwre            $sp,-152($24)
+        lwx             $12,$12($s4)
+        madd.ps         $f22,$f3,$f14,$f3
+        maq_s.w.phl     $ac2,$25,$11
+        maq_s.w.phr     $ac0,$10,$25
+        maq_sa.w.phl    $ac3,$a1,$v1
+        maq_sa.w.phr    $ac1,$at,$10
+        mfgc0           $s6,c0_datahi1
+        mflo            $9,$ac2
+        modsub          $a3,$12,$a3
+        mov.ps          $f22,$f17
+        move.v          $w8,$w17
+        movf.ps         $f10,$f28,$fcc6
+        movn.ps         $f31,$f31,$s3
+        movt.ps         $f20,$f25,$fcc2
+        movz.ps         $f18,$f17,$ra
+        msub            $ac2,$sp,$14
+        msub.ps         $f12,$f14,$f29,$f17
+        msubu           $ac2,$a1,$24
+        mtc0            $9,c0_datahi1
+        mtgc0           $s4,$21,7
+        mthi            $v0,$ac1
+        mthlip          $a3,$ac0
+        mul.ph          $s4,$24,$s0
+        mul.ps          $f14,$f0,$f16
+        mul_s.ph        $10,$14,$15
+        muleq_s.w.phl   $11,$s4,$s4
+        muleq_s.w.phr   $s6,$a0,$s8
+        muleu_s.ph.qbl  $a2,$14,$8
+        muleu_s.ph.qbr  $a1,$ra,$9
+        mulq_rs.ph      $s2,$14,$15
+        mulq_rs.w       $at,$s4,$25
+        mulq_s.ph       $s0,$k1,$15
+        mulq_s.w        $9,$a3,$s0
+        mulsa.w.ph      $ac1,$s4,$s6
+        mulsaq_s.w.ph   $ac0,$ra,$s2
+        neg.ps          $f19,$f13
+        nloc.b          $w12,$w30
+        nloc.d          $w16,$w7
+        nloc.h          $w21,$w17
+        nloc.w          $w17,$w16
+        nlzc.b          $w12,$w7
+        nlzc.d          $w14,$w14
+        nlzc.h          $w24,$w24
+        nlzc.w          $w10,$w4
+        nmadd.ps        $f27,$f4,$f9,$f25
+        nmsub.ps        $f6,$f12,$f14,$f17
+        nor.v           $w20,$w20,$w15
+        or.v            $w13,$w23,$w12
+        packrl.ph       $ra,$24,$14
+        pcnt.b          $w30,$w15
+        pcnt.d          $w5,$w16
+        pcnt.h          $w20,$w24
+        pcnt.w          $w22,$w20
+        pick.ph         $ra,$a2,$gp
+        pick.qb         $11,$a0,$gp
+        pll.ps          $f25,$f9,$f30
+        plu.ps          $f1,$f26,$f29
+        preceq.w.phl    $s8,$gp
+        preceq.w.phr    $s5,$15
+        precequ.ph.qbl  $s7,$ra
+        precequ.ph.qbla $a0,$9
+        precequ.ph.qbr  $ra,$s3
+        precequ.ph.qbra $24,$8
+        preceu.ph.qbl   $sp,$8
+        preceu.ph.qbla  $s6,$11
+        preceu.ph.qbr   $gp,$s1
+        preceu.ph.qbra  $k1,$s0
+        precr.qb.ph     $v0,$12,$s8
+        precrq.ph.w     $14,$s8,$24
+        precrq.qb.ph    $a2,$12,$12
+        precrq_rs.ph.w  $a1,$k0,$a3
+        precrqu_s.qb.ph $zero,$gp,$s5
+        pul.ps          $f9,$f30,$f26
+        puu.ps          $f24,$f9,$f2
+        raddu.w.qb      $25,$s3
+        rdpgpr          $s3,$9
+        recip.d         $f19,$f6
+        recip.s         $f3,$f30
+        repl.ph         $at,-307
+        replv.ph        $v1,$s7
+        replv.qb        $25,$12
+        rorv            $13,$a3,$s5
+        round.l.d       $f12,$f1
+        round.l.s       $f25,$f5
+        rsqrt.d         $f3,$f28
+        rsqrt.s         $f4,$f8
+        sbe             $s7,33($s1)
+        sce             $sp,189($10)
+        she             $24,105($v0)
+        shilo           $ac1,26
+        shilov          $ac2,$10
+        shllv.ph        $10,$s0,$s0
+        shllv.qb        $gp,$v1,$zero
+        shllv_s.ph      $k1,$at,$13
+        shllv_s.w       $s1,$ra,$k0
+        shrav.ph        $25,$s2,$s1
+        shrav.qb        $zero,$24,$11
+        shrav_r.ph      $s3,$11,$25
+        shrav_r.qb      $a0,$sp,$s5
+        shrav_r.w       $s7,$s4,$s6
+        shrlv.ph        $14,$10,$9
+        shrlv.qb        $a2,$s2,$11
+        sub.ps          $f5,$f14,$f26
+        subq.ph         $ra,$9,$s8
+        subq_s.ph       $13,$s8,$s5
+        subq_s.w        $k1,$a2,$a3
+        subqh.ph        $10,$at,$9
+        subqh.w         $v0,$a2,$zero
+        subqh_r.ph      $a0,$12,$s6
+        subqh_r.w       $10,$a2,$gp
+        subu.ph         $9,$s6,$s4
+        subu.qb         $s6,$a2,$s6
+        subu_s.ph       $v1,$a1,$s3
+        subu_s.qb       $s1,$at,$ra
+        subuh.qb        $zero,$gp,$gp
+        subuh_r.qb      $s4,$s8,$s6
+        swe             $24,94($k0)
+        swle            $v1,-209($gp)
+        swre            $k0,-202($s2)
+        tlbginv
+        tlbginvf
+        tlbgp
+        tlbgr
+        tlbgwi
+        tlbgwr
+        tlbinv
+        tlbinvf
+        trunc.l.d       $f23,$f23
+        trunc.l.s       $f28,$f31
+        wrpgpr          $zero,$13
+        xor.v           $w20,$w21,$w30
+        yield           $v1,$s0
diff --git a/test/MC/Mips/mips32r3/valid.s b/test/MC/Mips/mips32r3/valid.s
new file mode 100644
index 000000000000..0a4e5b19aeff
--- /dev/null
+++ b/test/MC/Mips/mips32r3/valid.s
@@ -0,0 +1,244 @@
+# Instructions that are valid
+#
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 | FileCheck %s
+a:
+        .set noat
+        abs.d     $f7,$f25             # CHECK: encoding:
+        abs.s     $f9,$f16
+        add       $s7,$s2,$a1
+        add       $9,$14,15176         # CHECK: addi $9, $14, 15176   # encoding: [0x21,0xc9,0x3b,0x48]
+        add       $24,-7193            # CHECK: addi $24, $24, -7193  # encoding: [0x23,0x18,0xe3,0xe7]
+        add.d     $f1,$f7,$f29
+        add.s     $f8,$f21,$f24
+        addi      $13,$9,26322
+        addi      $8,$8,~1             # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
+        addu      $9,$a0,$a2
+        addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
+        and       $s7,$v0,$12
+        and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
+        bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1fl     $fcc0,4688           # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     4688                 # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     $fcc7,27             # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06]
+        bc1t      $fcc0, 4             # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1t      $fcc1, 4             # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
+        bc1t      4                    # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1tl     $fcc0,4688           # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     4688                 # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     $fcc7,27             # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06]
+        bal       21100                # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $0, 21100            # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $6, 21100            # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
+        bltzal    $6, 21100            # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
+        beql      $14,$s3,12544        # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40]
+        bgezall   $12,7293             # CHECK: bgezall $12, 7293    # encoding: [0x05,0x93,0x07,0x1f]
+        bgezl     $4,-6858             # CHECK: bgezl $4, -6858      # encoding: [0x04,0x83,0xf9,0x4d]
+        bgtzl     $10,-3738            # CHECK: bgtzl $10, -3738     # encoding: [0x5d,0x40,0xfc,0x59]
+        blezl     $6,2974              # CHECK: blezl $6, 2974       # encoding: [0x58,0xc0,0x02,0xe7]
+        bltzall   $6,488               # CHECK: bltzall $6, 488      # encoding: [0x04,0xd2,0x00,0x7a]
+        bltzl     $s1,-9964            # CHECK: bltzl $17, -9964     # encoding: [0x06,0x22,0xf6,0x45]
+        bnel      $gp,$s4,5107         # CHECK: bnel $gp, $20, 5107  # encoding: [0x57,0x94,0x04,0xfc]
+        cache     1, 8($5)             # CHECK: cache 1, 8($5)   # encoding: [0xbc,0xa1,0x00,0x08]
+        c.ngl.d   $f29,$f29
+        c.ngle.d  $f0,$f16
+        c.sf.d    $f30,$f0
+        c.sf.s    $f14,$f22
+        ceil.w.d  $f11,$f25
+        ceil.w.s  $f6,$f20
+        cfc1      $s1,$21
+        clo       $11,$a1              # CHECK: clo $11, $5   # encoding: [0x70,0xab,0x58,0x21]
+        clz       $sp,$gp              # CHECK: clz $sp, $gp  # encoding: [0x73,0x9d,0xe8,0x20]
+        ctc1      $a2,$26
+        cvt.d.s   $f22,$f28
+        cvt.d.w   $f26,$f11
+        cvt.l.d   $f24,$f15
+        cvt.l.s   $f11,$f29
+        cvt.s.d   $f26,$f8
+        cvt.s.w   $f22,$f15
+        cvt.w.d   $f20,$f14
+        cvt.w.s   $f20,$f24
+        deret
+        di        $s8                  # CHECK: di  $fp       # encoding: [0x41,0x7e,0x60,0x00]
+        di                             # CHECK: di            # encoding: [0x41,0x60,0x60,0x00]
+        div       $zero,$25,$11
+        div.d     $f29,$f20,$f27
+        div.s     $f4,$f5,$f15
+        divu      $zero,$25,$15
+        ehb                            # CHECK: ehb # encoding:  [0x00,0x00,0x00,0xc0]
+        ei        $14                  # CHECK: ei  $14       # encoding: [0x41,0x6e,0x60,0x20]
+        ei                             # CHECK: ei            # encoding: [0x41,0x60,0x60,0x20]
+        eret
+        floor.w.d $f14,$f11
+        floor.w.s $f8,$f9
+        j         1f                   # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
+        j         a                    # CHECK: j a     # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
+        j         1328                 # CHECK: j 1328  # encoding: [0x08,0x00,0x01,0x4c]
+        jr.hb     $4                   # CHECK: jr.hb  $4 # encoding: [0x00,0x80,0x04,0x08]
+        jalr.hb   $4                   # CHECK: jalr.hb  $4 # encoding: [0x00,0x80,0xfc,0x09]
+        jalr.hb   $4, $5               # CHECK: jalr.hb  $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
+        lb        $24,-14515($10)
+        lbu       $8,30195($v1)
+        ldc1      $f11,16391($s0)
+        ldc2      $8,-21181($at)        # CHECK: ldc2 $8, -21181($1)   # encoding: [0xd8,0x28,0xad,0x43]
+        ldxc1     $f8,$s7($15)
+        lh        $11,-8556($s5)
+        lhu       $s3,-22851($v0)
+        li        $at,-29773
+        li        $zero,-29889
+        ll        $v0,-7321($s2)       # CHECK: ll $2, -7321($18)     # encoding: [0xc2,0x42,0xe3,0x67]
+        luxc1     $f19,$s6($s5)
+        lw        $8,5674($a1)
+        lwc1      $f16,10225($k0)
+        lwc2      $18,-841($a2)        # CHECK: lwc2 $18, -841($6)     # encoding: [0xc8,0xd2,0xfc,0xb7]
+        lwl       $s4,-4231($15)
+        lwr       $zero,-19147($gp)
+        lwxc1     $f12,$s1($s8)
+        madd      $s6,$13
+        madd      $zero,$9
+        madd.d    $f18,$f19,$f26,$f20
+        madd.s    $f1,$f31,$f19,$f25
+        maddu     $s3,$gp
+        maddu     $24,$s2
+        mfc0      $a2,$14,1
+        mfc1      $a3,$f27
+        mfhc1     $s8,$f24
+        mfhi      $s3
+        mfhi      $sp
+        mflo      $s1
+        mov.d     $f20,$f14
+        mov.s     $f2,$f27
+        move      $s8,$a0
+        move      $25,$a2
+        movf      $gp,$8,$fcc7
+        movf.d    $f6,$f11,$fcc5
+        movf.s    $f23,$f5,$fcc6
+        movn      $v1,$s1,$s0
+        movn.d    $f27,$f21,$k0
+        movn.s    $f12,$f0,$s7
+        movt      $zero,$s4,$fcc5
+        movt.d    $f0,$f2,$fcc0
+        movt.s    $f30,$f2,$fcc1
+        movz      $a1,$s6,$9
+        movz.d    $f12,$f29,$9
+        movz.s    $f25,$f7,$v1
+        msub      $s7,$k1
+        msub.d    $f10,$f1,$f31,$f18
+        msub.s    $f12,$f19,$f10,$f16
+        msubu     $15,$a1
+        mtc0      $9,$29,3
+        mtc1      $s8,$f9
+        mthc1     $zero,$f16
+        mthi      $s1
+        mtlo      $sp
+        mtlo      $25
+        mul       $s0,$s4,$at
+        mul.d     $f20,$f20,$f16
+        mul.s     $f30,$f10,$f2
+        mult      $sp,$s4
+        mult      $sp,$v0
+        multu     $gp,$k0
+        multu     $9,$s2
+        negu      $2                   # CHECK: negu $2, $2            # encoding: [0x00,0x02,0x10,0x23]
+        negu      $2,$3                # CHECK: negu $2, $3            # encoding: [0x00,0x03,0x10,0x23]
+        neg.d     $f27,$f18
+        neg.s     $f1,$f15
+        nmadd.d   $f18,$f9,$f14,$f19
+        nmadd.s   $f0,$f5,$f25,$f12
+        nmsub.d   $f30,$f8,$f16,$f30
+        nmsub.s   $f1,$f24,$f19,$f4
+        nop
+        nor       $a3,$zero,$a3
+        or        $12,$s0,$sp
+        or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
+        pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
+        pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
+        # FIXME: Use the code generator in order to print the .set directives
+        #        instead of the instruction printer.
+        rdhwr     $sp,$11              # CHECK:      .set  push
+                                       # CHECK-NEXT: .set  mips32r2
+                                       # CHECK-NEXT: rdhwr $sp, $11
+                                       # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
+        rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
+        rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
+        rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
+        round.w.d $f6,$f4
+        round.w.s $f27,$f28
+        sb        $s6,-19857($14)
+        sc        $15,18904($s3)       # CHECK: sc $15, 18904($19)     # encoding: [0xe2,0x6f,0x49,0xd8]
+        sdbbp                          # CHECK: sdbbp                  # encoding: [0x70,0x00,0x00,0x3f]
+        sdbbp     34                   # CHECK: sdbbp 34               # encoding: [0x70,0x00,0x08,0xbf]
+        sdc1      $f31,30574($13)
+        sdc2      $20,23157($s2)       # CHECK: sdc2 $20, 23157($18)   # encoding: [0xfa,0x54,0x5a,0x75]
+        sdxc1     $f11,$10($14)
+        seb       $25,$15
+        seh       $v1,$12
+        sh        $14,-6704($15)
+        sll       $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
+        sll       $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+        sll       $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        sllv      $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        slt       $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+        slti      $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+        sltiu     $25,$25,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+        sltu      $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+        sltu      $24,$25,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
+        sqrt.d    $f17,$f22
+        sqrt.s    $f0,$f1
+        sra       $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
+        sra       $s1,$s7,15           # CHECK: sra $17, $23, 15       # encoding: [0x00,0x17,0x8b,0xc3]
+        sra       $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srav      $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srl       $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        srlv      $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        ssnop                          # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
+        sub       $s6,$s3,$12
+        sub       $22,$17,-3126        # CHECK: addi $22, $17, 3126    # encoding: [0x22,0x36,0x0c,0x36]
+        sub       $13,6512             # CHECK: addi $13, $13, -6512   # encoding: [0x21,0xad,0xe6,0x90]
+        sub.d     $f18,$f3,$f17
+        sub.s     $f23,$f22,$f22
+        subu      $sp,$s6,$s6
+        suxc1     $f12,$k1($13)
+        sw        $ra,-10160($sp)
+        swc1      $f6,-8465($24)
+        swc2      $25,24880($s0)       # CHECK: swc2 $25, 24880($16)   # encoding: [0xea,0x19,0x61,0x30]
+        swl       $15,13694($s3)
+        swr       $s1,-26590($14)
+        swxc1     $f19,$12($k0)
+        sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
+        teq       $5,$7,620            # CHECK: teq $5, $7, 620        # encoding: [0x00,0xa7,0x9b,0x34]
+        teqi      $s5,-17504
+        tge       $7,$10               # CHECK: tge $7, $10            # encoding: [0x00,0xea,0x00,0x30]
+        tge       $5,$19,340           # CHECK: tge $5, $19, 340       # encoding: [0x00,0xb3,0x55,0x30]
+        tgei      $s1,5025
+        tgeiu     $sp,-28621
+        tgeu      $22,$28              # CHECK: tgeu $22, $gp          # encoding: [0x02,0xdc,0x00,0x31]
+        tgeu      $20,$14,379          # CHECK: tgeu $20, $14, 379     # encoding: [0x02,0x8e,0x5e,0xf1]
+        tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+        tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+        tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+        tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $15,$13              # CHECK: tlt $15, $13           # encoding: [0x01,0xed,0x00,0x32]
+        tlt       $2,$19,133           # CHECK: tlt $2, $19, 133       # encoding: [0x00,0x53,0x21,0x72]
+        tlti      $14,-21059
+        tltiu     $ra,-5076
+        tltu      $11,$16              # CHECK: tltu $11, $16          # encoding: [0x01,0x70,0x00,0x33]
+        tltu      $16,$29,1016         # CHECK: tltu $16, $sp, 1016    # encoding: [0x02,0x1d,0xfe,0x33]
+        tne       $6,$17               # CHECK: tne $6, $17            # encoding: [0x00,0xd1,0x00,0x36]
+        tne       $7,$8,885            # CHECK: tne $7, $8, 885        # encoding: [0x00,0xe8,0xdd,0x76]
+        tnei      $12,-29647
+        trunc.w.d $f22,$f15
+        trunc.w.s $f28,$f30
+        wsbh      $k1,$9
+        xor       $s2,$a0,$s8
+        xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
+        synci     -15842($a2)          # CHECK: synci -15842($6)        # encoding: [0x04,0xdf,0xc2,0x1e]
+
+1:
diff --git a/test/MC/Mips/mips32r5/abiflags.s b/test/MC/Mips/mips32r5/abiflags.s
new file mode 100644
index 000000000000..fa5befeaddb6
--- /dev/null
+++ b/test/MC/Mips/mips32r5/abiflags.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r5 | \
+# RUN:   FileCheck %s -check-prefix=CHECK-ASM
+#
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r5 -filetype=obj -o - | \
+# RUN:   llvm-readobj -sections -section-data -section-relocations - | \
+# RUN:     FileCheck %s -check-prefix=CHECK-OBJ
+
+# CHECK-ASM: .module fp=32
+# CHECK-ASM: .set fp=64
+
+# Checking if the Mips.abiflags were correctly emitted.
+# CHECK-OBJ:       Section {
+# CHECK-OBJ:         Index: 5
+# CHECK-OBJ-LABEL:   Name: .MIPS.abiflags (12)
+# CHECK-OBJ:         Type: SHT_MIPS_ABIFLAGS (0x7000002A)
+# CHECK-OBJ:          Flags [ (0x2)
+# CHECK-OBJ:           SHF_ALLOC (0x2)
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         Address: 0x0
+# CHECK-OBJ:         Size: 24
+# CHECK-OBJ:         Link: 0
+# CHECK-OBJ:         Info: 0
+# CHECK-OBJ:         AddressAlignment: 8
+# CHECK-OBJ:         EntrySize: 24
+# CHECK-OBJ:         Relocations [
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         SectionData (
+# CHECK-OBJ:           0000: 00002005 01010001 00000000 00000000  |.. .............|
+# CHECK-OBJ:           0010: 00000001 00000000                    |........|
+# CHECK-OBJ:         )
+# CHECK-OBJ-LABEL: }
+
+        .module fp=32
+        .set fp=64
+# FIXME: Test should include gnu_attributes directive when implemented.
+#        An explicit .gnu_attribute must be checked against the effective
+#        command line options and any inconsistencies reported via a warning.
diff --git a/test/MC/Mips/mips32r5/invalid-mips64r2.s b/test/MC/Mips/mips32r5/invalid-mips64r2.s
new file mode 100644
index 000000000000..ed8f5c743b98
--- /dev/null
+++ b/test/MC/Mips/mips32r5/invalid-mips64r2.s
@@ -0,0 +1,10 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding \
+# RUN:     -mcpu=mips32r5 2>%t1
+# RUN: FileCheck %s < %t1
+
+	.set noat
+	dsbh	$v1,$t6    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+	dshd	$v0,$sp    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+
diff --git a/test/MC/Mips/mips32r5/invalid.s b/test/MC/Mips/mips32r5/invalid.s
new file mode 100644
index 000000000000..fec30e1426cd
--- /dev/null
+++ b/test/MC/Mips/mips32r5/invalid.s
@@ -0,0 +1,10 @@
+# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g.
+# invalid set of operands or operand's restrictions not met).
+
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r5 2>%t1
+# RUN: FileCheck %s < %t1 -check-prefix=ASM
+
+        .text
+        .set noreorder
+        jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
+        jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
diff --git a/test/MC/Mips/mips32r5/valid-xfail.s b/test/MC/Mips/mips32r5/valid-xfail.s
new file mode 100644
index 000000000000..a821dddb85ca
--- /dev/null
+++ b/test/MC/Mips/mips32r5/valid-xfail.s
@@ -0,0 +1,308 @@
+# Instructions that should be valid but currently fail for known reasons (e.g.
+# they aren't implemented yet).
+# This test is set up to XPASS if any instruction generates an encoding.
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r5 | not FileCheck %s
+# CHECK-NOT: encoding
+# XFAIL: *
+
+        .set noat
+        abs.ps          $f22,$f8
+        absq_s.ph       $8,$a0
+        absq_s.qb       $15,$s1
+        absq_s.w        $s3,$ra
+        add.ps          $f25,$f27,$f13
+        addq.ph         $s1,$15,$at
+        addq_s.ph       $s3,$s6,$s2
+        addq_s.w        $a2,$8,$at
+        addqh.ph        $s4,$14,$s1
+        addqh.w         $s7,$s7,$k1
+        addqh_r.ph      $sp,$25,$s8
+        addqh_r.w       $8,$v1,$zero
+        addsc           $s8,$15,$12
+        addu.ph         $a2,$14,$s3
+        addu.qb         $s6,$v1,$v1
+        addu_s.ph       $a3,$s3,$gp
+        addu_s.qb       $s4,$s8,$s1
+        adduh.qb        $a1,$a1,$at
+        adduh_r.qb      $a0,$9,$12
+        addwc           $k0,$s6,$s7
+        alnv.ps         $f12,$f18,$f30,$12
+        and.v           $w10,$w25,$w29
+        bitrev          $14,$at
+        bmnz.v          $w15,$w2,$w28
+        bmz.v           $w13,$w11,$w21
+        bsel.v          $w28,$w7,$w0
+        c.eq.d          $fcc1,$f15,$f15
+        c.eq.ps         $fcc5,$f0,$f9
+        c.eq.s          $fcc5,$f24,$f17
+        c.f.d           $fcc4,$f11,$f21
+        c.f.ps          $fcc6,$f11,$f11
+        c.f.s           $fcc4,$f30,$f7
+        c.le.d          $fcc4,$f18,$f1
+        c.le.ps         $fcc1,$f7,$f20
+        c.le.s          $fcc6,$f24,$f4
+        c.lt.d          $fcc3,$f9,$f3
+        c.lt.ps         $f19,$f5
+        c.lt.s          $fcc2,$f17,$f14
+        c.nge.d         $fcc5,$f21,$f16
+        c.nge.ps        $f1,$f26
+        c.nge.s         $fcc3,$f11,$f8
+        c.ngl.ps        $f21,$f30
+        c.ngl.s         $fcc2,$f31,$f23
+        c.ngle.ps       $fcc7,$f12,$f20
+        c.ngle.s        $fcc2,$f18,$f23
+        c.ngt.d         $fcc4,$f24,$f7
+        c.ngt.ps        $fcc5,$f30,$f6
+        c.ngt.s         $fcc5,$f8,$f13
+        c.ole.d         $fcc2,$f16,$f31
+        c.ole.ps        $fcc7,$f21,$f8
+        c.ole.s         $fcc3,$f7,$f20
+        c.olt.d         $fcc4,$f19,$f28
+        c.olt.ps        $fcc3,$f7,$f16
+        c.olt.s         $fcc6,$f20,$f7
+        c.seq.d         $fcc4,$f31,$f7
+        c.seq.ps        $fcc6,$f31,$f14
+        c.seq.s         $fcc7,$f1,$f25
+        c.sf.ps         $fcc6,$f4,$f6
+        c.ueq.d         $fcc4,$f13,$f25
+        c.ueq.ps        $fcc1,$f5,$f29
+        c.ueq.s         $fcc6,$f3,$f30
+        c.ule.d         $fcc7,$f25,$f18
+        c.ule.ps        $fcc6,$f17,$f3
+        c.ule.s         $fcc7,$f21,$f30
+        c.ult.d         $fcc6,$f6,$f17
+        c.ult.ps        $fcc7,$f14,$f0
+        c.ult.s         $fcc7,$f24,$f10
+        c.un.d          $fcc6,$f23,$f24
+        c.un.ps         $fcc4,$f2,$f26
+        c.un.s          $fcc1,$f30,$f4
+        ceil.l.d        $f1,$f3
+        ceil.l.s        $f18,$f13
+        cfcmsa          $s6,$19
+        cmp.eq.ph       $s7,$14
+        cmp.le.ph       $8,$14
+        cmp.lt.ph       $k0,$sp
+        cmpgdu.eq.qb    $s3,$zero,$k0
+        cmpgdu.le.qb    $v1,$15,$s2
+        cmpgdu.lt.qb    $s0,$gp,$sp
+        cmpgu.eq.qb     $14,$s6,$s8
+        cmpgu.le.qb     $9,$a3,$s4
+        cmpgu.lt.qb     $sp,$at,$8
+        cmpu.eq.qb      $v0,$24
+        cmpu.le.qb      $s1,$a1
+        cmpu.lt.qb      $at,$a3
+        ctcmsa          $31,$s7
+        cvt.d.l         $f4,$f16
+        cvt.ps.s        $f3,$f18,$f19
+        cvt.s.l         $f15,$f30
+        cvt.s.pl        $f30,$f1
+        cvt.s.pu        $f14,$f25
+        dmt $k0
+        dpa.w.ph        $ac1,$s7,$k0
+        dpaq_s.w.ph     $ac2,$a0,$13
+        dpaq_sa.l.w     $ac0,$a2,$14
+        dpaqx_s.w.ph    $ac3,$a0,$24
+        dpaqx_sa.w.ph   $ac1,$zero,$s5
+        dpau.h.qbl      $ac1,$10,$24
+        dpau.h.qbr      $ac1,$s7,$s6
+        dpax.w.ph       $ac3,$a0,$k0
+        dps.w.ph        $ac1,$a3,$a1
+        dpsq_s.w.ph     $ac0,$gp,$k0
+        dpsq_sa.l.w     $ac0,$a3,$15
+        dpsqx_s.w.ph    $ac3,$13,$a3
+        dpsqx_sa.w.ph   $ac3,$sp,$s2
+        dpsu.h.qbl      $ac2,$14,$10
+        dpsu.h.qbr      $ac2,$a1,$s6
+        dpsx.w.ph       $ac0,$s7,$gp
+        dvpe            $s6
+        emt $8
+        evpe            $v0
+        extpdpv         $s6,$ac0,$s8
+        extpv           $13,$ac0,$14
+        extrv.w         $8,$ac3,$at
+        extrv_r.w       $8,$ac1,$s6
+        extrv_rs.w      $gp,$ac1,$s6
+        extrv_s.h       $s2,$ac1,$14
+        fclass.d        $w14,$w27
+        fclass.w        $w19,$w28
+        fexupl.d        $w10,$w29
+        fexupl.w        $w12,$w27
+        fexupr.d        $w31,$w15
+        fexupr.w        $w29,$w12
+        ffint_s.d       $w1,$w30
+        ffint_s.w       $w16,$w14
+        ffint_u.d       $w23,$w18
+        ffint_u.w       $w19,$w12
+        ffql.d          $w2,$w3
+        ffql.w          $w9,$w0
+        ffqr.d          $w25,$w24
+        ffqr.w          $w10,$w6
+        fill.b          $w9,$v1
+        fill.h          $w9,$8
+        fill.w          $w31,$15
+        flog2.d         $w12,$w16
+        flog2.w         $w19,$w23
+        floor.l.d       $f26,$f7
+        floor.l.s       $f12,$f5
+        fork            $s2,$8,$a0
+        frcp.d          $w12,$w4
+        frcp.w          $w30,$w8
+        frint.d         $w20,$w8
+        frint.w         $w11,$w29
+        frsqrt.d        $w29,$w2
+        frsqrt.w        $w9,$w8
+        fsqrt.d         $w3,$w1
+        fsqrt.w         $w5,$w15
+        ftint_s.d       $w31,$w26
+        ftint_s.w       $w27,$w14
+        ftint_u.d       $w5,$w31
+        ftint_u.w       $w12,$w29
+        ftrunc_s.d      $w4,$w22
+        ftrunc_s.w      $w24,$w7
+        ftrunc_u.d      $w20,$w25
+        ftrunc_u.w      $w7,$w26
+        insv            $s2,$at
+        iret
+        lbe             $14,122($9)
+        lbue            $11,-108($10)
+        lbux            $9,$14($v0)
+        lhe             $s6,219($v1)
+        lhue            $gp,118($11)
+        lhx             $sp,$k0($15)
+        lle             $gp,-237($ra)
+        lwe             $ra,-145($14)
+        lwle            $11,-42($11)
+        lwre            $sp,-152($24)
+        lwx             $12,$12($s4)
+        madd.ps         $f22,$f3,$f14,$f3
+        maq_s.w.phl     $ac2,$25,$11
+        maq_s.w.phr     $ac0,$10,$25
+        maq_sa.w.phl    $ac3,$a1,$v1
+        maq_sa.w.phr    $ac1,$at,$10
+        mfgc0           $s6,c0_datahi1
+        mflo            $9,$ac2
+        modsub          $a3,$12,$a3
+        mov.ps          $f22,$f17
+        move.v          $w8,$w17
+        movf.ps         $f10,$f28,$fcc6
+        movn.ps         $f31,$f31,$s3
+        movt.ps         $f20,$f25,$fcc2
+        movz.ps         $f18,$f17,$ra
+        msub            $ac2,$sp,$14
+        msub.ps         $f12,$f14,$f29,$f17
+        msubu           $ac2,$a1,$24
+        mtc0            $9,c0_datahi1
+        mtgc0           $s4,$21,7
+        mthi            $v0,$ac1
+        mthlip          $a3,$ac0
+        mul.ph          $s4,$24,$s0
+        mul.ps          $f14,$f0,$f16
+        mul_s.ph        $10,$14,$15
+        muleq_s.w.phl   $11,$s4,$s4
+        muleq_s.w.phr   $s6,$a0,$s8
+        muleu_s.ph.qbl  $a2,$14,$8
+        muleu_s.ph.qbr  $a1,$ra,$9
+        mulq_rs.ph      $s2,$14,$15
+        mulq_rs.w       $at,$s4,$25
+        mulq_s.ph       $s0,$k1,$15
+        mulq_s.w        $9,$a3,$s0
+        mulsa.w.ph      $ac1,$s4,$s6
+        mulsaq_s.w.ph   $ac0,$ra,$s2
+        neg.ps          $f19,$f13
+        nloc.b          $w12,$w30
+        nloc.d          $w16,$w7
+        nloc.h          $w21,$w17
+        nloc.w          $w17,$w16
+        nlzc.b          $w12,$w7
+        nlzc.d          $w14,$w14
+        nlzc.h          $w24,$w24
+        nlzc.w          $w10,$w4
+        nmadd.ps        $f27,$f4,$f9,$f25
+        nmsub.ps        $f6,$f12,$f14,$f17
+        nor.v           $w20,$w20,$w15
+        or.v            $w13,$w23,$w12
+        packrl.ph       $ra,$24,$14
+        pcnt.b          $w30,$w15
+        pcnt.d          $w5,$w16
+        pcnt.h          $w20,$w24
+        pcnt.w          $w22,$w20
+        pick.ph         $ra,$a2,$gp
+        pick.qb         $11,$a0,$gp
+        pll.ps          $f25,$f9,$f30
+        plu.ps          $f1,$f26,$f29
+        preceq.w.phl    $s8,$gp
+        preceq.w.phr    $s5,$15
+        precequ.ph.qbl  $s7,$ra
+        precequ.ph.qbla $a0,$9
+        precequ.ph.qbr  $ra,$s3
+        precequ.ph.qbra $24,$8
+        preceu.ph.qbl   $sp,$8
+        preceu.ph.qbla  $s6,$11
+        preceu.ph.qbr   $gp,$s1
+        preceu.ph.qbra  $k1,$s0
+        precr.qb.ph     $v0,$12,$s8
+        precrq.ph.w     $14,$s8,$24
+        precrq.qb.ph    $a2,$12,$12
+        precrq_rs.ph.w  $a1,$k0,$a3
+        precrqu_s.qb.ph $zero,$gp,$s5
+        pul.ps          $f9,$f30,$f26
+        puu.ps          $f24,$f9,$f2
+        raddu.w.qb      $25,$s3
+        rdpgpr          $s3,$9
+        recip.d         $f19,$f6
+        recip.s         $f3,$f30
+        repl.ph         $at,-307
+        replv.ph        $v1,$s7
+        replv.qb        $25,$12
+        rorv            $13,$a3,$s5
+        round.l.d       $f12,$f1
+        round.l.s       $f25,$f5
+        rsqrt.d         $f3,$f28
+        rsqrt.s         $f4,$f8
+        sbe             $s7,33($s1)
+        sce             $sp,189($10)
+        she             $24,105($v0)
+        shilo           $ac1,26
+        shilov          $ac2,$10
+        shllv.ph        $10,$s0,$s0
+        shllv.qb        $gp,$v1,$zero
+        shllv_s.ph      $k1,$at,$13
+        shllv_s.w       $s1,$ra,$k0
+        shrav.ph        $25,$s2,$s1
+        shrav.qb        $zero,$24,$11
+        shrav_r.ph      $s3,$11,$25
+        shrav_r.qb      $a0,$sp,$s5
+        shrav_r.w       $s7,$s4,$s6
+        shrlv.ph        $14,$10,$9
+        shrlv.qb        $a2,$s2,$11
+        sub.ps          $f5,$f14,$f26
+        subq.ph         $ra,$9,$s8
+        subq_s.ph       $13,$s8,$s5
+        subq_s.w        $k1,$a2,$a3
+        subqh.ph        $10,$at,$9
+        subqh.w         $v0,$a2,$zero
+        subqh_r.ph      $a0,$12,$s6
+        subqh_r.w       $10,$a2,$gp
+        subu.ph         $9,$s6,$s4
+        subu.qb         $s6,$a2,$s6
+        subu_s.ph       $v1,$a1,$s3
+        subu_s.qb       $s1,$at,$ra
+        subuh.qb        $zero,$gp,$gp
+        subuh_r.qb      $s4,$s8,$s6
+        swe             $24,94($k0)
+        swle            $v1,-209($gp)
+        swre            $k0,-202($s2)
+        tlbginv
+        tlbginvf
+        tlbgp
+        tlbgr
+        tlbgwi
+        tlbgwr
+        tlbinv
+        tlbinvf
+        trunc.l.d       $f23,$f23
+        trunc.l.s       $f28,$f31
+        wrpgpr          $zero,$13
+        xor.v           $w20,$w21,$w30
+        yield           $v1,$s0
diff --git a/test/MC/Mips/mips32r5/valid.s b/test/MC/Mips/mips32r5/valid.s
new file mode 100644
index 000000000000..036b908c8efc
--- /dev/null
+++ b/test/MC/Mips/mips32r5/valid.s
@@ -0,0 +1,244 @@
+# Instructions that are valid
+#
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r5 | FileCheck %s
+a:
+        .set noat
+        abs.d     $f7,$f25             # CHECK: encoding:
+        abs.s     $f9,$f16
+        add       $s7,$s2,$a1
+        add       $9,$14,15176         # CHECK: addi $9, $14, 15176   # encoding: [0x21,0xc9,0x3b,0x48]
+        add       $24,-7193            # CHECK: addi $24, $24, -7193  # encoding: [0x23,0x18,0xe3,0xe7]
+        add.d     $f1,$f7,$f29
+        add.s     $f8,$f21,$f24
+        addi      $13,$9,26322
+        addi      $8,$8,~1             # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
+        addu      $9,$a0,$a2
+        addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
+        and       $s7,$v0,$12
+        and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
+        bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1fl     $fcc0,4688           # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     4688                 # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     $fcc7,27             # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06]
+        bc1t      $fcc0, 4             # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1t      $fcc1, 4             # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
+        bc1t      4                    # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1tl     $fcc0,4688           # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     4688                 # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     $fcc7,27             # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06]
+        bal       21100                # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $0, 21100            # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $6, 21100            # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
+        bltzal    $6, 21100            # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
+        beql      $14,$s3,12544        # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40]
+        bgezall   $12,7293             # CHECK: bgezall $12, 7293    # encoding: [0x05,0x93,0x07,0x1f]
+        bgezl     $4,-6858             # CHECK: bgezl $4, -6858      # encoding: [0x04,0x83,0xf9,0x4d]
+        bgtzl     $10,-3738            # CHECK: bgtzl $10, -3738     # encoding: [0x5d,0x40,0xfc,0x59]
+        blezl     $6,2974              # CHECK: blezl $6, 2974       # encoding: [0x58,0xc0,0x02,0xe7]
+        bltzall   $6,488               # CHECK: bltzall $6, 488      # encoding: [0x04,0xd2,0x00,0x7a]
+        bltzl     $s1,-9964            # CHECK: bltzl $17, -9964     # encoding: [0x06,0x22,0xf6,0x45]
+        bnel      $gp,$s4,5107         # CHECK: bnel $gp, $20, 5107  # encoding: [0x57,0x94,0x04,0xfc]
+        cache     1, 8($5)             # CHECK: cache 1, 8($5)   # encoding: [0xbc,0xa1,0x00,0x08]
+        c.ngl.d   $f29,$f29
+        c.ngle.d  $f0,$f16
+        c.sf.d    $f30,$f0
+        c.sf.s    $f14,$f22
+        ceil.w.d  $f11,$f25
+        ceil.w.s  $f6,$f20
+        cfc1      $s1,$21
+        clo       $11,$a1              # CHECK: clo $11, $5   # encoding: [0x70,0xab,0x58,0x21]
+        clz       $sp,$gp              # CHECK: clz $sp, $gp  # encoding: [0x73,0x9d,0xe8,0x20]
+        ctc1      $a2,$26
+        cvt.d.s   $f22,$f28
+        cvt.d.w   $f26,$f11
+        cvt.l.d   $f24,$f15
+        cvt.l.s   $f11,$f29
+        cvt.s.d   $f26,$f8
+        cvt.s.w   $f22,$f15
+        cvt.w.d   $f20,$f14
+        cvt.w.s   $f20,$f24
+        deret
+        di        $s8                  # CHECK: di  $fp       # encoding: [0x41,0x7e,0x60,0x00]
+        di                             # CHECK: di            # encoding: [0x41,0x60,0x60,0x00]
+        div       $zero,$25,$11
+        div.d     $f29,$f20,$f27
+        div.s     $f4,$f5,$f15
+        divu      $zero,$25,$15
+        ehb                            # CHECK: ehb # encoding:  [0x00,0x00,0x00,0xc0]
+        ei        $14                  # CHECK: ei  $14       # encoding: [0x41,0x6e,0x60,0x20]
+        ei                             # CHECK: ei            # encoding: [0x41,0x60,0x60,0x20]
+        eret
+        floor.w.d $f14,$f11
+        floor.w.s $f8,$f9
+        j         1f                   # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
+        j         a                    # CHECK: j a     # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
+        j         1328                 # CHECK: j 1328  # encoding: [0x08,0x00,0x01,0x4c]
+        jr.hb     $4                   # CHECK: jr.hb  $4 # encoding: [0x00,0x80,0x04,0x08]
+        jalr.hb   $4                   # CHECK: jalr.hb  $4 # encoding: [0x00,0x80,0xfc,0x09]
+        jalr.hb   $4, $5               # CHECK: jalr.hb  $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
+        lb        $24,-14515($10)
+        lbu       $8,30195($v1)
+        ldc1      $f11,16391($s0)
+        ldc2      $8,-21181($at)        # CHECK: ldc2 $8, -21181($1)   # encoding: [0xd8,0x28,0xad,0x43]
+        ldxc1     $f8,$s7($15)
+        lh        $11,-8556($s5)
+        lhu       $s3,-22851($v0)
+        li        $at,-29773
+        li        $zero,-29889
+        ll        $v0,-7321($s2)       # CHECK: ll $2, -7321($18)     # encoding: [0xc2,0x42,0xe3,0x67]
+        luxc1     $f19,$s6($s5)
+        lw        $8,5674($a1)
+        lwc1      $f16,10225($k0)
+        lwc2      $18,-841($a2)        # CHECK: lwc2 $18, -841($6)     # encoding: [0xc8,0xd2,0xfc,0xb7]
+        lwl       $s4,-4231($15)
+        lwr       $zero,-19147($gp)
+        lwxc1     $f12,$s1($s8)
+        madd      $s6,$13
+        madd      $zero,$9
+        madd.d    $f18,$f19,$f26,$f20
+        madd.s    $f1,$f31,$f19,$f25
+        maddu     $s3,$gp
+        maddu     $24,$s2
+        mfc0      $a2,$14,1
+        mfc1      $a3,$f27
+        mfhc1     $s8,$f24
+        mfhi      $s3
+        mfhi      $sp
+        mflo      $s1
+        mov.d     $f20,$f14
+        mov.s     $f2,$f27
+        move      $s8,$a0
+        move      $25,$a2
+        movf      $gp,$8,$fcc7
+        movf.d    $f6,$f11,$fcc5
+        movf.s    $f23,$f5,$fcc6
+        movn      $v1,$s1,$s0
+        movn.d    $f27,$f21,$k0
+        movn.s    $f12,$f0,$s7
+        movt      $zero,$s4,$fcc5
+        movt.d    $f0,$f2,$fcc0
+        movt.s    $f30,$f2,$fcc1
+        movz      $a1,$s6,$9
+        movz.d    $f12,$f29,$9
+        movz.s    $f25,$f7,$v1
+        msub      $s7,$k1
+        msub.d    $f10,$f1,$f31,$f18
+        msub.s    $f12,$f19,$f10,$f16
+        msubu     $15,$a1
+        mtc0      $9,$29,3
+        mtc1      $s8,$f9
+        mthc1     $zero,$f16
+        mthi      $s1
+        mtlo      $sp
+        mtlo      $25
+        mul       $s0,$s4,$at
+        mul.d     $f20,$f20,$f16
+        mul.s     $f30,$f10,$f2
+        mult      $sp,$s4
+        mult      $sp,$v0
+        multu     $gp,$k0
+        multu     $9,$s2
+        negu      $2                   # CHECK: negu $2, $2            # encoding: [0x00,0x02,0x10,0x23]
+        negu      $2,$3                # CHECK: negu $2, $3            # encoding: [0x00,0x03,0x10,0x23]
+        neg.d     $f27,$f18
+        neg.s     $f1,$f15
+        nmadd.d   $f18,$f9,$f14,$f19
+        nmadd.s   $f0,$f5,$f25,$f12
+        nmsub.d   $f30,$f8,$f16,$f30
+        nmsub.s   $f1,$f24,$f19,$f4
+        nop
+        nor       $a3,$zero,$a3
+        or        $12,$s0,$sp
+        or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
+        pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
+        pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
+        # FIXME: Use the code generator in order to print the .set directives
+        #        instead of the instruction printer.
+        rdhwr     $sp,$11              # CHECK:      .set  push
+                                       # CHECK-NEXT: .set  mips32r2
+                                       # CHECK-NEXT: rdhwr $sp, $11
+                                       # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
+        rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
+        rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
+        rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
+        round.w.d $f6,$f4
+        round.w.s $f27,$f28
+        sb        $s6,-19857($14)
+        sc        $15,18904($s3)       # CHECK: sc $15, 18904($19)     # encoding: [0xe2,0x6f,0x49,0xd8]
+        sdbbp                          # CHECK: sdbbp                  # encoding: [0x70,0x00,0x00,0x3f]
+        sdbbp     34                   # CHECK: sdbbp 34               # encoding: [0x70,0x00,0x08,0xbf]
+        sdc1      $f31,30574($13)
+        sdc2      $20,23157($s2)       # CHECK: sdc2 $20, 23157($18)   # encoding: [0xfa,0x54,0x5a,0x75]
+        sdxc1     $f11,$10($14)
+        seb       $25,$15
+        seh       $v1,$12
+        sh        $14,-6704($15)
+        sll       $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
+        sll       $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+        sll       $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        sllv      $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        slt       $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+        slti      $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+        sltiu     $25,$25,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+        sltu      $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+        sltu      $24,$25,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
+        sqrt.d    $f17,$f22
+        sqrt.s    $f0,$f1
+        sra       $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
+        sra       $s1,$s7,15           # CHECK: sra $17, $23, 15       # encoding: [0x00,0x17,0x8b,0xc3]
+        sra       $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srav      $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srl       $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        srlv      $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        ssnop                          # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
+        sub       $s6,$s3,$12
+        sub       $22,$17,-3126        # CHECK: addi $22, $17, 3126    # encoding: [0x22,0x36,0x0c,0x36]
+        sub       $13,6512             # CHECK: addi $13, $13, -6512   # encoding: [0x21,0xad,0xe6,0x90]
+        sub.d     $f18,$f3,$f17
+        sub.s     $f23,$f22,$f22
+        subu      $sp,$s6,$s6
+        suxc1     $f12,$k1($13)
+        sw        $ra,-10160($sp)
+        swc1      $f6,-8465($24)
+        swc2      $25,24880($s0)       # CHECK: swc2 $25, 24880($16)   # encoding: [0xea,0x19,0x61,0x30]
+        swl       $15,13694($s3)
+        swr       $s1,-26590($14)
+        swxc1     $f19,$12($k0)
+        sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
+        teq       $5,$7,620            # CHECK: teq $5, $7, 620        # encoding: [0x00,0xa7,0x9b,0x34]
+        teqi      $s5,-17504
+        tge       $7,$10               # CHECK: tge $7, $10            # encoding: [0x00,0xea,0x00,0x30]
+        tge       $5,$19,340           # CHECK: tge $5, $19, 340       # encoding: [0x00,0xb3,0x55,0x30]
+        tgei      $s1,5025
+        tgeiu     $sp,-28621
+        tgeu      $22,$28              # CHECK: tgeu $22, $gp          # encoding: [0x02,0xdc,0x00,0x31]
+        tgeu      $20,$14,379          # CHECK: tgeu $20, $14, 379     # encoding: [0x02,0x8e,0x5e,0xf1]
+        tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+        tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+        tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+        tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $15,$13              # CHECK: tlt $15, $13           # encoding: [0x01,0xed,0x00,0x32]
+        tlt       $2,$19,133           # CHECK: tlt $2, $19, 133       # encoding: [0x00,0x53,0x21,0x72]
+        tlti      $14,-21059
+        tltiu     $ra,-5076
+        tltu      $11,$16              # CHECK: tltu $11, $16          # encoding: [0x01,0x70,0x00,0x33]
+        tltu      $16,$29,1016         # CHECK: tltu $16, $sp, 1016    # encoding: [0x02,0x1d,0xfe,0x33]
+        tne       $6,$17               # CHECK: tne $6, $17            # encoding: [0x00,0xd1,0x00,0x36]
+        tne       $7,$8,885            # CHECK: tne $7, $8, 885        # encoding: [0x00,0xe8,0xdd,0x76]
+        tnei      $12,-29647
+        trunc.w.d $f22,$f15
+        trunc.w.s $f28,$f30
+        wsbh      $k1,$9
+        xor       $s2,$a0,$s8
+        xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
+        synci     -15842($a2)          # CHECK: synci -15842($6)        # encoding: [0x04,0xdf,0xc2,0x1e]
+
+1:
diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s
index 362785ba7ef2..2c3a5b2a7a43 100644
--- a/test/MC/Mips/mips32r6/valid.s
+++ b/test/MC/Mips/mips32r6/valid.s
@@ -12,7 +12,7 @@
 #
 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 2> %t0 | FileCheck %s
 # RUN: FileCheck %s -check-prefix=WARNING < %t0
-
+a:
         .set noat
         # FIXME: Add the instructions carried forward from older ISA's
         and     $2,4             # CHECK: andi $2, $2, 4      # encoding: [0x30,0x42,0x00,0x04]
@@ -146,6 +146,11 @@
         rint.d $f2, $f4          # CHECK: rint.d $f2, $f4        # encoding: [0x46,0x20,0x20,0x9a]
         class.s $f2, $f4         # CHECK: class.s $f2, $f4       # encoding: [0x46,0x00,0x20,0x9b]
         class.d $f2, $f4         # CHECK: class.d $f2, $f4       # encoding: [0x46,0x20,0x20,0x9b]
+        j       1f               # CHECK: j $tmp0                # encoding: [0b000010AA,A,A,A]
+                                 # CHECK:                        #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
+        j       a                # CHECK: j a                    # encoding: [0b000010AA,A,A,A]
+                                 # CHECK:                        #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
+        j       1328             # CHECK: j 1328                 # encoding: [0x08,0x00,0x01,0x4c]
         jr.hb   $4               # CHECK: jr.hb $4               # encoding: [0x00,0x80,0x04,0x09]
         jalr.hb $4               # CHECK: jalr.hb $4             # encoding: [0x00,0x80,0xfc,0x09]
         jalr.hb $4, $5           # CHECK: jalr.hb $4, $5         # encoding: [0x00,0xa0,0x24,0x09]
@@ -175,3 +180,6 @@
         tltu    $16,$29,1016     # CHECK: tltu $16, $sp, 1016    # encoding: [0x02,0x1d,0xfe,0x33]
         tne     $6,$17           # CHECK: tne $6, $17            # encoding: [0x00,0xd1,0x00,0x36]
         tne     $7,$8,885        # CHECK: tne $7, $8, 885        # encoding: [0x00,0xe8,0xdd,0x76]
+        xor     $2, 4            # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
+
+1:
diff --git a/test/MC/Mips/mips4/valid.s b/test/MC/Mips/mips4/valid.s
index fc747a58ce8a..b89026dd714a 100644
--- a/test/MC/Mips/mips4/valid.s
+++ b/test/MC/Mips/mips4/valid.s
@@ -1,7 +1,7 @@
 # Instructions that are valid
 #
 # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | FileCheck %s
-
+a:
         .set noat
         abs.d     $f7,$f25             # CHECK: encoding:
         abs.s     $f9,$f16
@@ -81,6 +81,9 @@
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
         dsll      $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
         dsll      $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
@@ -113,6 +116,11 @@
         floor.l.s $f12,$f5
         floor.w.d $f14,$f11
         floor.w.s $f8,$f9
+        j         1f                   # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
+        j         a                    # CHECK: j a     # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
+        j         1328                 # CHECK: j 1328  # encoding: [0x08,0x00,0x01,0x4c]
         lb        $24,-14515($10)
         lbu       $8,30195($v1)
         ld        $sp,-28645($s1)
@@ -257,3 +265,6 @@
         trunc.w.d $f22,$f15
         trunc.w.s $f28,$f30
         xor       $s2,$a0,$s8
+        xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
+
+1:
diff --git a/test/MC/Mips/mips5/valid.s b/test/MC/Mips/mips5/valid.s
index 995d1a52a06c..b444274d78ec 100644
--- a/test/MC/Mips/mips5/valid.s
+++ b/test/MC/Mips/mips5/valid.s
@@ -1,7 +1,7 @@
 # Instructions that are valid
 #
 # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | FileCheck %s
-
+a:
         .set noat
         abs.d     $f7,$f25             # CHECK: encoding:
         abs.s     $f9,$f16
@@ -81,6 +81,9 @@
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
         dsll      $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
         dsll      $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
@@ -113,6 +116,11 @@
         floor.l.s $f12,$f5
         floor.w.d $f14,$f11
         floor.w.s $f8,$f9
+        j         1f                   # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
+        j         a                    # CHECK: j a     # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
+        j         1328                 # CHECK: j 1328  # encoding: [0x08,0x00,0x01,0x4c]
         lb        $24,-14515($10)
         lbu       $8,30195($v1)
         ld        $sp,-28645($s1)
@@ -259,3 +267,6 @@
         trunc.w.d $f22,$f15
         trunc.w.s $f28,$f30
         xor       $s2,$a0,$s8
+        xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
+
+1:
diff --git a/test/MC/Mips/mips64-expansions.s b/test/MC/Mips/mips64-expansions.s
index 0efdd2fa5c81..62a95200f247 100644
--- a/test/MC/Mips/mips64-expansions.s
+++ b/test/MC/Mips/mips64-expansions.s
@@ -1,209 +1,195 @@
 # RUN: llvm-mc %s -triple=mips64el-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
 #
-# The GNU assembler implements 'dli' and 'dla' variants on 'li' and 'la'
-# supporting double-word lengths.  Test that not only are they present, bu
-# that they also seem to handle 64-bit values.
-#
-# XXXRW: Does using powers of ten make me a bad person?
-#
-# CHECK: ori	$12, $zero, 1           # encoding: [0x01,0x00,0x0c,0x34]
-# CHECK: ori	$12, $zero, 10          # encoding: [0x0a,0x00,0x0c,0x34]
-# CHECK: ori	$12, $zero, 100         # encoding: [0x64,0x00,0x0c,0x34]
-# CHECK: ori	$12, $zero, 1000        # encoding: [0xe8,0x03,0x0c,0x34]
-# CHECK: ori	$12, $zero, 10000       # encoding: [0x10,0x27,0x0c,0x34]
-# CHECK: lui	$12, 1                  # encoding: [0x01,0x00,0x0c,0x3c]
-# CHECK: ori	$12, $12, 34464         # encoding: [0xa0,0x86,0x8c,0x35]
-# CHECK: lui	$12, 15                 # encoding: [0x0f,0x00,0x0c,0x3c]
-# CHECK: ori	$12, $12, 16960         # encoding: [0x40,0x42,0x8c,0x35]
-# CHECK: lui	$12, 152                # encoding: [0x98,0x00,0x0c,0x3c]
-# CHECK: ori	$12, $12, 38528         # encoding: [0x80,0x96,0x8c,0x35]
-# CHECK: lui	$12, 1525               # encoding: [0xf5,0x05,0x0c,0x3c]
-# CHECK: ori	$12, $12, 57600         # encoding: [0x00,0xe1,0x8c,0x35]
-# CHECK: lui	$12, 15258              # encoding: [0x9a,0x3b,0x0c,0x3c]
-# CHECK: ori	$12, $12, 51712         # encoding: [0x00,0xca,0x8c,0x35]
-# CHECK: lui	$12, 2                  # encoding: [0x02,0x00,0x0c,0x3c]
-# CHECK: ori	$12, $12, 21515         # encoding: [0x0b,0x54,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 58368         # encoding: [0x00,0xe4,0x8c,0x35]
-# CHECK: lui	$12, 23                 # encoding: [0x17,0x00,0x0c,0x3c]
-# CHECK: ori	$12, $12, 18550         # encoding: [0x76,0x48,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 59392         # encoding: [0x00,0xe8,0x8c,0x35]
-# CHECK: lui	$12, 232                # encoding: [0xe8,0x00,0x0c,0x3c]
-# CHECK: ori	$12, $12, 54437         # encoding: [0xa5,0xd4,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 4096          # encoding: [0x00,0x10,0x8c,0x35]
-# CHECK: lui	$12, 2328               # encoding: [0x18,0x09,0x0c,0x3c]
-# CHECK: ori	$12, $12, 20082         # encoding: [0x72,0x4e,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 40960         # encoding: [0x00,0xa0,0x8c,0x35]
-# CHECK: lui	$12, 23283              # encoding: [0xf3,0x5a,0x0c,0x3c]
-# CHECK: ori	$12, $12, 4218          # encoding: [0x7a,0x10,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 16384         # encoding: [0x00,0x40,0x8c,0x35]
-# CHECK: lui	$12, 3                  # encoding: [0x03,0x00,0x0c,0x3c]
-# CHECK: ori	$12, $12, 36222         # encoding: [0x7e,0x8d,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 42182         # encoding: [0xc6,0xa4,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 32768         # encoding: [0x00,0x80,0x8c,0x35]
-# CHECK: lui	$12, 35                 # encoding: [0x23,0x00,0x0c,0x3c]
-# CHECK: ori	$12, $12, 34546         # encoding: [0xf2,0x86,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 28609         # encoding: [0xc1,0x6f,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 0             # encoding: [0x00,0x00,0x8c,0x35]
-# CHECK: lui	$12, 355                # encoding: [0x63,0x01,0x0c,0x3c]
-# CHECK: ori	$12, $12, 17784         # encoding: [0x78,0x45,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 23946         # encoding: [0x8a,0x5d,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 0             # encoding: [0x00,0x00,0x8c,0x35]
-# CHECK: lui	$12, 3552               # encoding: [0xe0,0x0d,0x0c,0x3c]
-# CHECK: ori	$12, $12, 46771         # encoding: [0xb3,0xb6,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 42852         # encoding: [0x64,0xa7,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 0             # encoding: [0x00,0x00,0x8c,0x35]
-# CHECK: lui	$12, 35527              # encoding: [0xc7,0x8a,0x0c,0x3c]
-# CHECK: ori	$12, $12, 8964          # encoding: [0x04,0x23,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 35304         # encoding: [0xe8,0x89,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 0             # encoding: [0x00,0x00,0x8c,0x35]
-# CHECK: addiu	$12, $zero, -1          # encoding: [0xff,0xff,0x0c,0x24]
-# CHECK: addiu	$12, $zero, -10         # encoding: [0xf6,0xff,0x0c,0x24]
-# CHECK: addiu	$12, $zero, -100        # encoding: [0x9c,0xff,0x0c,0x24]
-# CHECK: addiu	$12, $zero, -1000       # encoding: [0x18,0xfc,0x0c,0x24]
-# CHECK: addiu	$12, $zero, -10000      # encoding: [0xf0,0xd8,0x0c,0x24]
-# CHECK: lui	$12, 65535              # encoding: [0xff,0xff,0x0c,0x3c]
-# CHECK: ori	$12, $12, 65535         # encoding: [0xff,0xff,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 65534         # encoding: [0xfe,0xff,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 31072         # encoding: [0x60,0x79,0x8c,0x35]
-# CHECK: lui	$12, 65535              # encoding: [0xff,0xff,0x0c,0x3c]
-# CHECK: ori	$12, $12, 65535         # encoding: [0xff,0xff,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 65520         # encoding: [0xf0,0xff,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 48576         # encoding: [0xc0,0xbd,0x8c,0x35]
-# CHECK: lui	$12, 65535              # encoding: [0xff,0xff,0x0c,0x3c]
-# CHECK: ori	$12, $12, 65535         # encoding: [0xff,0xff,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 65383         # encoding: [0x67,0xff,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 27008         # encoding: [0x80,0x69,0x8c,0x35]
-# CHECK: lui	$12, 65535              # encoding: [0xff,0xff,0x0c,0x3c]
-# CHECK: ori	$12, $12, 65535         # encoding: [0xff,0xff,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 64010         # encoding: [0x0a,0xfa,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 7936          # encoding: [0x00,0x1f,0x8c,0x35]
-# CHECK: lui	$12, 65535              # encoding: [0xff,0xff,0x0c,0x3c]
-# CHECK: ori	$12, $12, 65535         # encoding: [0xff,0xff,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 50277         # encoding: [0x65,0xc4,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 13824         # encoding: [0x00,0x36,0x8c,0x35]
-# CHECK: lui	$12, 65535              # encoding: [0xff,0xff,0x0c,0x3c]
-# CHECK: ori	$12, $12, 65533         # encoding: [0xfd,0xff,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 44020         # encoding: [0xf4,0xab,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 7168          # encoding: [0x00,0x1c,0x8c,0x35]
-# CHECK: lui	$12, 65535              # encoding: [0xff,0xff,0x0c,0x3c]
-# CHECK: ori	$12, $12, 65512         # encoding: [0xe8,0xff,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 46985         # encoding: [0x89,0xb7,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 6144          # encoding: [0x00,0x18,0x8c,0x35]
-# CHECK: lui	$12, 65535              # encoding: [0xff,0xff,0x0c,0x3c]
-# CHECK: ori	$12, $12, 65303         # encoding: [0x17,0xff,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 11098         # encoding: [0x5a,0x2b,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 61440         # encoding: [0x00,0xf0,0x8c,0x35]
-# CHECK: lui	$12, 65535              # encoding: [0xff,0xff,0x0c,0x3c]
-# CHECK: ori	$12, $12, 63207         # encoding: [0xe7,0xf6,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 45453         # encoding: [0x8d,0xb1,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 24576         # encoding: [0x00,0x60,0x8c,0x35]
-# CHECK: lui	$12, 65535              # encoding: [0xff,0xff,0x0c,0x3c]
-# CHECK: ori	$12, $12, 42252         # encoding: [0x0c,0xa5,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 61317         # encoding: [0x85,0xef,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 49152         # encoding: [0x00,0xc0,0x8c,0x35]
-# CHECK: lui	$12, 65532              # encoding: [0xfc,0xff,0x0c,0x3c]
-# CHECK: ori	$12, $12, 29313         # encoding: [0x81,0x72,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 23353         # encoding: [0x39,0x5b,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 32768         # encoding: [0x00,0x80,0x8c,0x35]
-# CHECK: lui	$12, 65500              # encoding: [0xdc,0xff,0x0c,0x3c]
-# CHECK: ori	$12, $12, 30989         # encoding: [0x0d,0x79,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 36927         # encoding: [0x3f,0x90,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 0             # encoding: [0x00,0x00,0x8c,0x35]
-# CHECK: lui	$12, 65180              # encoding: [0x9c,0xfe,0x0c,0x3c]
-# CHECK: ori	$12, $12, 47751         # encoding: [0x87,0xba,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 41590         # encoding: [0x76,0xa2,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 0             # encoding: [0x00,0x00,0x8c,0x35]
-# CHECK: lui	$12, 61983              # encoding: [0x1f,0xf2,0x0c,0x3c]
-# CHECK: ori	$12, $12, 18764         # encoding: [0x4c,0x49,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 22684         # encoding: [0x9c,0x58,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 0             # encoding: [0x00,0x00,0x8c,0x35]
-# CHECK: lui	$12, 30008              # encoding: [0x38,0x75,0x0c,0x3c]
-# CHECK: ori	$12, $12, 56571         # encoding: [0xfb,0xdc,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 30232         # encoding: [0x18,0x76,0x8c,0x35]
-# CHECK: dsll	$12, $12, 16            # encoding: [0x38,0x64,0x0c,0x00]
-# CHECK: ori	$12, $12, 0             # encoding: [0x00,0x00,0x8c,0x35]
-
-	dli	$t0, 1
-	dli	$t0, 10
-	dli	$t0, 100
-	dli	$t0, 1000
-	dli	$t0, 10000
-	dli	$t0, 100000
-	dli	$t0, 1000000
-	dli	$t0, 10000000
-	dli	$t0, 100000000
-	dli	$t0, 1000000000
-	dli	$t0, 10000000000
-	dli	$t0, 100000000000
-	dli	$t0, 1000000000000
-	dli	$t0, 10000000000000
-	dli	$t0, 100000000000000
-	dli	$t0, 1000000000000000
-	dli	$t0, 10000000000000000
-	dli	$t0, 100000000000000000
-	dli	$t0, 1000000000000000000
-	dli	$t0, 10000000000000000000
-	dli	$t0, -1
-	dli	$t0, -10
-	dli	$t0, -100
-	dli	$t0, -1000
-	dli	$t0, -10000
-	dli	$t0, -100000
-	dli	$t0, -1000000
-	dli	$t0, -10000000
-	dli	$t0, -100000000
-	dli	$t0, -1000000000
-	dli	$t0, -10000000000
-	dli	$t0, -100000000000
-	dli	$t0, -1000000000000
-	dli	$t0, -10000000000000
-	dli	$t0, -100000000000000
-	dli	$t0, -1000000000000000
-	dli	$t0, -10000000000000000
-	dli	$t0, -100000000000000000
-	dli	$t0, -1000000000000000000
-	dli	$t0, -10000000000000000000
+# Test the 'dli' and 'dla' 64-bit variants of 'li' and 'la'.
+
+# Immediate is <= 32 bits.
+  dli $5, 123
+# CHECK:     ori   $5, $zero, 123   # encoding: [0x7b,0x00,0x05,0x34]
+
+  dli $6, -2345
+# CHECK:     addiu $6, $zero, -2345 # encoding: [0xd7,0xf6,0x06,0x24]
+
+  dli $7, 65538
+# CHECK:     lui   $7, 1            # encoding: [0x01,0x00,0x07,0x3c]
+# CHECK:     ori   $7, $7, 2        # encoding: [0x02,0x00,0xe7,0x34]
+
+  dli $8, ~7
+# CHECK:     addiu $8, $zero, -8    # encoding: [0xf8,0xff,0x08,0x24]
+
+  dli $9, 0x10000
+# CHECK:     lui   $9, 1            # encoding: [0x01,0x00,0x09,0x3c]
+# CHECK-NOT: ori   $9, $9, 0        # encoding: [0x00,0x00,0x29,0x35]
+
+
+# Positive immediate which is => 32 bits and <= 48 bits.
+  dli $8, 0x100000000
+# CHECK: lui  $8, 1                 # encoding: [0x01,0x00,0x08,0x3c]
+# CHECK: dsll $8, $8, 16            # encoding: [0x38,0x44,0x08,0x00]
+
+  dli $8, 0x100000001
+# CHECK: lui  $8, 1                 # encoding: [0x01,0x00,0x08,0x3c]
+# CHECK: dsll $8, $8, 16            # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori  $8, $8, 1             # encoding: [0x01,0x00,0x08,0x35]
+
+  dli $8, 0x100010000
+# CHECK: lui  $8, 1                 # encoding: [0x01,0x00,0x08,0x3c]
+# CHECK: ori  $8, $8, 1             # encoding: [0x01,0x00,0x08,0x35]
+# CHECK: dsll $8, $8, 16            # encoding: [0x38,0x44,0x08,0x00]
+
+  dli $8, 0x100010001
+# CHECK: lui  $8, 1                 # encoding: [0x01,0x00,0x08,0x3c]
+# CHECK: ori  $8, $8, 1             # encoding: [0x01,0x00,0x08,0x35]
+# CHECK: dsll $8, $8, 16            # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori  $8, $8, 1             # encoding: [0x01,0x00,0x08,0x35]
+
+
+# Positive immediate which is > 48 bits.
+  dli $8, 0x1000000000000
+# CHECK: lui    $8, 1               # encoding: [0x01,0x00,0x08,0x3c]
+# CHECK: dsll32 $8, $8, 0           # encoding: [0x3c,0x40,0x08,0x00]
+
+  dli $8, 0x1000000000001
+# CHECK: lui    $8, 1               # encoding: [0x01,0x00,0x08,0x3c]
+# CHECK: dsll32 $8, $8, 0           # encoding: [0x3c,0x40,0x08,0x00]
+# CHECK: ori    $8, $8, 1           # encoding: [0x01,0x00,0x08,0x35]
+
+  dli $8, 0x1000000010000
+# CHECK: lui    $8, 1               # encoding: [0x01,0x00,0x08,0x3c]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 1           # encoding: [0x01,0x00,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+
+  dli $8, 0x1000100000000
+# CHECK: lui    $8, 1               # encoding: [0x01,0x00,0x08,0x3c]
+# CHECK: ori    $8, $8, 1           # encoding: [0x01,0x00,0x08,0x35]
+# CHECK: dsll32 $8, $8, 0           # encoding: [0x3c,0x40,0x08,0x00]
+
+  dli $8, 0x1000000010001
+# CHECK: lui    $8, 1               # encoding: [0x01,0x00,0x08,0x3c]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 1           # encoding: [0x01,0x00,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 1           # encoding: [0x01,0x00,0x08,0x35]
+
+  dli $8, 0x1000100010000
+# CHECK: lui    $8, 1               # encoding: [0x01,0x00,0x08,0x3c]
+# CHECK: ori    $8, $8, 1           # encoding: [0x01,0x00,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 1           # encoding: [0x01,0x00,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+
+  dli $8, 0x1000100000001
+# CHECK: lui    $8, 1               # encoding: [0x01,0x00,0x08,0x3c]
+# CHECK: ori    $8, $8, 1           # encoding: [0x01,0x00,0x08,0x35]
+# CHECK: dsll32 $8, $8, 0           # encoding: [0x3c,0x40,0x08,0x00]
+# CHECK: ori    $8, $8, 1           # encoding: [0x01,0x00,0x08,0x35]
+
+  dli $8, 0x1000100010001
+# CHECK: lui    $8, 1               # encoding: [0x01,0x00,0x08,0x3c]
+# CHECK: ori    $8, $8, 1           # encoding: [0x01,0x00,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 1           # encoding: [0x01,0x00,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 1           # encoding: [0x01,0x00,0x08,0x35]
+
+
+# Negative immediate which is => 32 bits and <= 48 bits.
+  dli $8, -0x100000000
+# CHECK: lui    $8, 65535           # encoding: [0xff,0xff,0x08,0x3c]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+# CHECK: dsll32 $8, $8, 0           # encoding: [0x3c,0x40,0x08,0x00]
+
+  dli $8, -0x100000001
+# CHECK: lui    $8, 65535           # encoding: [0xff,0xff,0x08,0x3c]
+# CHECK: ori    $8, $8, 65534       # encoding: [0xfe,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+
+  dli $8, -0x100010000
+# CHECK: lui    $8, 65535           # encoding: [0xff,0xff,0x08,0x3c]
+# CHECK: ori    $8, $8, 65534       # encoding: [0xfe,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+
+  dli $8, -0x100010001
+# CHECK: lui    $8, 65535           # encoding: [0xff,0xff,0x08,0x3c]
+# CHECK: ori    $8, $8, 65534       # encoding: [0xfe,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 65534       # encoding: [0xfe,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+
+
+# Negative immediate which is > 48 bits.
+  dli $8, -0x1000000000000
+# CHECK: lui    $8, 65535           # encoding: [0xff,0xff,0x08,0x3c]
+# CHECK: dsll32 $8, $8, 0           # encoding: [0x3c,0x40,0x08,0x00]
+
+  dli $8, -0x1000000000001
+# CHECK: lui    $8, 65534           # encoding: [0xfe,0xff,0x08,0x3c]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+
+  dli $8, -0x1000000010000
+# CHECK: lui    $8, 65534           # encoding: [0xfe,0xff,0x08,0x3c]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+
+  dli $8, -0x1000100000000
+# CHECK: lui    $8, 65534           # encoding: [0xfe,0xff,0x08,0x3c]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+# CHECK: dsll32 $8, $8, 0           # encoding: [0x3c,0x40,0x08,0x00]
+
+  dli $8, -0x1000000010001
+# CHECK: lui    $8, 65534           # encoding: [0xfe,0xff,0x08,0x3c]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 65534       # encoding: [0xfe,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+
+  dli $8, -0x1000100010000
+# CHECK: lui    $8, 65534           # encoding: [0xfe,0xff,0x08,0x3c]
+# CHECK: ori    $8, $8, 65534       # encoding: [0xfe,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+
+  dli $8, -0x1000100000001
+# CHECK: lui    $8, 65534           # encoding: [0xfe,0xff,0x08,0x3c]
+# CHECK: ori    $8, $8, 65534       # encoding: [0xfe,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+
+  dli $8, -0x1000100010001
+# CHECK: lui    $8, 65534           # encoding: [0xfe,0xff,0x08,0x3c]
+# CHECK: ori    $8, $8, 65534       # encoding: [0xfe,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 65534       # encoding: [0xfe,0xff,0x08,0x35]
+# CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
+# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+
+# Check that signed negative 32-bit immediates are loaded correctly:
+  li $10, ~(0x101010)
+# CHECK: lui $10, 65519        # encoding: [0xef,0xff,0x0a,0x3c]
+# CHECK: ori $10, $10, 61423   # encoding: [0xef,0xef,0x4a,0x35]
+# CHECK-NOT: dsll
+
+  dli $10, ~(0x202020)
+# CHECK: lui $10, 65503        # encoding: [0xdf,0xff,0x0a,0x3c]
+# CHECK: ori $10, $10, 57311   # encoding: [0xdf,0xdf,0x4a,0x35]
+# CHECK-NOT: dsll
+
+  dli $9, 0x80000000
+# CHECK: ori  $9, $zero, 32768 # encoding: [0x00,0x80,0x09,0x34]
+# CHECK: dsll $9, $9, 16       # encoding: [0x38,0x4c,0x09,0x00]
diff --git a/test/MC/Mips/mips64-register-names-n32-n64.s b/test/MC/Mips/mips64-register-names-n32-n64.s
index efe1cdb48043..fb2c426c625c 100644
--- a/test/MC/Mips/mips64-register-names-n32-n64.s
+++ b/test/MC/Mips/mips64-register-names-n32-n64.s
@@ -3,7 +3,7 @@
 # RUN: FileCheck -check-prefix=WARNING %s < %t0
 #
 # RUN: llvm-mc %s -triple=mips64-unknown-freebsd -show-encoding \
-# RUN:     -mattr=-n64,+n32 2>%t1 | FileCheck %s
+# RUN:     -target-abi n32 2>%t1 | FileCheck %s
 # RUN: FileCheck -check-prefix=WARNING %s < %t1
 #
 # Check that the register names are mapped to their correct numbers for n32/n64
diff --git a/test/MC/Mips/mips64-register-names-o32.s b/test/MC/Mips/mips64-register-names-o32.s
index c17057816ed3..f5df527c18cd 100644
--- a/test/MC/Mips/mips64-register-names-o32.s
+++ b/test/MC/Mips/mips64-register-names-o32.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc %s -triple=mips64-unknown-freebsd -show-encoding \
-# RUN:     -mattr=-n64,+o32 | FileCheck %s
+# RUN:     -target-abi o32 | FileCheck %s
 
 # Check that the register names are mapped to their correct numbers for o32
 # Second byte of daddiu with $zero at rt contains the number of the source
diff --git a/test/MC/Mips/mips64/valid.s b/test/MC/Mips/mips64/valid.s
index f481a28eeed2..0bb9f17f02b4 100644
--- a/test/MC/Mips/mips64/valid.s
+++ b/test/MC/Mips/mips64/valid.s
@@ -1,7 +1,7 @@
 # Instructions that are valid
 #
 # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s
-
+a:
         .set noat
         abs.d     $f7,$f25             # CHECK: encoding:
         abs.s     $f9,$f16
@@ -86,6 +86,9 @@
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
         dsll      $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
         dsll      $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
@@ -118,6 +121,11 @@
         floor.l.s $f12,$f5
         floor.w.d $f14,$f11
         floor.w.s $f8,$f9
+        j         1f                   # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
+        j         a                    # CHECK: j a     # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
+        j         1328                 # CHECK: j 1328  # encoding: [0x08,0x00,0x01,0x4c]
         lb        $24,-14515($10)
         lbu       $8,30195($v1)
         ld        $sp,-28645($s1)
@@ -276,3 +284,6 @@
         trunc.w.d $f22,$f15
         trunc.w.s $f28,$f30
         xor       $s2,$a0,$s8
+        xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
+
+1:
diff --git a/test/MC/Mips/mips64extins.ll b/test/MC/Mips/mips64extins.ll
index ebe8f86513fd..093bc87b90bc 100644
--- a/test/MC/Mips/mips64extins.ll
+++ b/test/MC/Mips/mips64extins.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -mattr=n64 %s -o - \
+; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -target-abi=n64 %s -o - \
 ; RUN: | llvm-objdump -disassemble -triple mips64el -mattr +mips64r2 - \
 ; RUN: | FileCheck %s
 
diff --git a/test/MC/Mips/mips64r2/valid.s b/test/MC/Mips/mips64r2/valid.s
index 77172380bdfc..aad8e2850f90 100644
--- a/test/MC/Mips/mips64r2/valid.s
+++ b/test/MC/Mips/mips64r2/valid.s
@@ -1,7 +1,7 @@
 # Instructions that are valid
 #
 # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
-
+a:
         .set noat
         abs.d     $f7,$f25             # CHECK: encoding:
         abs.s     $f9,$f16
@@ -88,6 +88,9 @@
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         drotr     $1,15                # CHECK: drotr $1, $1, 15            # encoding: [0x00,0x21,0x0b,0xfa]
         drotr     $1,$14,15            # CHECK: drotr $1, $14, 15           # encoding: [0x00,0x2e,0x0b,0xfa]
         drotr32   $1,15                # CHECK: drotr32 $1, $1, 15          # encoding: [0x00,0x21,0x0b,0xfe]
@@ -131,6 +134,11 @@
         floor.l.s $f12,$f5
         floor.w.d $f14,$f11
         floor.w.s $f8,$f9
+        j         1f                   # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
+        j         a                    # CHECK: j a     # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
+        j         1328                 # CHECK: j 1328  # encoding: [0x08,0x00,0x01,0x4c]
         jr.hb     $4                   # CHECK: jr.hb  $4 # encoding: [0x00,0x80,0x04,0x08]
         jalr.hb   $4                   # CHECK: jalr.hb  $4 # encoding: [0x00,0x80,0xfc,0x09]
         jalr.hb   $4, $5               # CHECK: jalr.hb  $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
@@ -302,4 +310,7 @@
         trunc.w.d $f22,$f15
         trunc.w.s $f28,$f30
         xor       $s2,$a0,$s8
+        xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
         wsbh      $k1,$9
+
+1:
diff --git a/test/MC/Mips/mips64r3/abi-bad.s b/test/MC/Mips/mips64r3/abi-bad.s
new file mode 100644
index 000000000000..7691601bf29b
--- /dev/null
+++ b/test/MC/Mips/mips64r3/abi-bad.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc %s -triple mips-unknown-linux -mcpu=mips64r3 2>&1 | FileCheck %s
+        .set fp=xx
+# CHECK: error: '.set fp=xx' requires the O32 ABI
+# CHECK: .set fp=xx
+# CHECK:          ^
diff --git a/test/MC/Mips/mips64r3/abiflags.s b/test/MC/Mips/mips64r3/abiflags.s
new file mode 100644
index 000000000000..e89be29ca2b9
--- /dev/null
+++ b/test/MC/Mips/mips64r3/abiflags.s
@@ -0,0 +1,36 @@
+# RUN: llvm-mc %s -arch=mips -mcpu=mips64r3 | \
+# RUN:   FileCheck %s -check-prefix=CHECK-ASM
+#
+# RUN: llvm-mc %s -arch=mips -mcpu=mips64r3 -filetype=obj -o - | \
+# RUN:   llvm-readobj -sections -section-data -section-relocations - | \
+# RUN:     FileCheck %s -check-prefix=CHECK-OBJ
+
+# CHECK-ASM: .module fp=64
+
+# Checking if the Mips.abiflags were correctly emitted.
+# CHECK-OBJ:       Section {
+# CHECK-OBJ:         Index: 5
+# CHECK-OBJ-LABEL:   Name: .MIPS.abiflags
+# CHECK-OBJ:         Type: SHT_MIPS_ABIFLAGS (0x7000002A)
+# CHECK-OBJ:          Flags [ (0x2)
+# CHECK-OBJ:           SHF_ALLOC (0x2)
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         Address: 0x0
+# CHECK-OBJ:         Size: 24
+# CHECK-OBJ:         Link: 0
+# CHECK-OBJ:         Info: 0
+# CHECK-OBJ:         AddressAlignment: 8
+# CHECK-OBJ:         EntrySize: 24
+# CHECK-OBJ:         Relocations [
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         SectionData (
+# CHECK-OBJ:           0000: 00004003 02020001 00000000 00000000  |..@.............|
+# CHECK-OBJ:           0010: 00000001 00000000                    |........|
+# CHECK-OBJ:         )
+# CHECK-OBJ-LABEL: }
+
+        .module fp=64
+
+# FIXME: Test should include gnu_attributes directive when implemented.
+#        An explicit .gnu_attribute must be checked against the effective
+#        command line options and any inconsistencies reported via a warning.
diff --git a/test/MC/Mips/mips64r3/invalid.s b/test/MC/Mips/mips64r3/invalid.s
new file mode 100644
index 000000000000..99cd0803d202
--- /dev/null
+++ b/test/MC/Mips/mips64r3/invalid.s
@@ -0,0 +1,10 @@
+# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g.
+# invalid set of operands or operand's restrictions not met).
+
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r3 2>%t1
+# RUN: FileCheck %s < %t1 -check-prefix=ASM
+
+        .text
+        .set noreorder
+        jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
+        jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
diff --git a/test/MC/Mips/mips64r3/valid-xfail.s b/test/MC/Mips/mips64r3/valid-xfail.s
new file mode 100644
index 000000000000..f2949c4f2dda
--- /dev/null
+++ b/test/MC/Mips/mips64r3/valid-xfail.s
@@ -0,0 +1,306 @@
+# Instructions that should be valid but currently fail for known reasons (e.g.
+# they aren't implemented yet).
+# This test is set up to XPASS if any instruction generates an encoding.
+#
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r3 | not FileCheck %s
+# CHECK-NOT: encoding
+# XFAIL: *
+
+        .set noat
+        abs.ps          $f22,$f8
+        absq_s.ph       $8,$a0
+        absq_s.qb       $15,$s1
+        absq_s.w        $s3,$ra
+        add.ps          $f25,$f27,$f13
+        addq.ph         $s1,$15,$at
+        addq_s.ph       $s3,$s6,$s2
+        addq_s.w        $a2,$8,$at
+        addqh.ph        $s4,$14,$s1
+        addqh.w         $s7,$s7,$k1
+        addqh_r.ph      $sp,$25,$s8
+        addqh_r.w       $8,$v1,$zero
+        addsc           $s8,$15,$12
+        addu.ph         $a2,$14,$s3
+        addu.qb         $s6,$v1,$v1
+        addu_s.ph       $a3,$s3,$gp
+        addu_s.qb       $s4,$s8,$s1
+        adduh.qb        $a1,$a1,$at
+        adduh_r.qb      $a0,$9,$12
+        addwc           $k0,$s6,$s7
+        alnv.ob         $v22,$v19,$v30,$v1
+        alnv.ob         $v31,$v23,$v30,$at
+        alnv.ob         $v8,$v17,$v30,$a1
+        alnv.ps         $f12,$f18,$f30,$12
+        and.v           $w10,$w25,$w29
+        bitrev          $14,$at
+        bmnz.v          $w15,$w2,$w28
+        bmz.v           $w13,$w11,$w21
+        bsel.v          $w28,$w7,$w0
+        c.eq.d          $fcc1,$f15,$f15
+        c.eq.ps         $fcc5,$f0,$f9
+        c.eq.s          $fcc5,$f24,$f17
+        c.f.d           $fcc4,$f11,$f21
+        c.f.ps          $fcc6,$f11,$f11
+        c.f.s           $fcc4,$f30,$f7
+        c.le.d          $fcc4,$f18,$f1
+        c.le.ps         $fcc1,$f7,$f20
+        c.le.s          $fcc6,$f24,$f4
+        c.lt.d          $fcc3,$f9,$f3
+        c.lt.ps         $f19,$f5
+        c.lt.s          $fcc2,$f17,$f14
+        c.nge.d         $fcc5,$f21,$f16
+        c.nge.ps        $f1,$f26
+        c.nge.s         $fcc3,$f11,$f8
+        c.ngl.ps        $f21,$f30
+        c.ngl.s         $fcc2,$f31,$f23
+        c.ngle.ps       $fcc7,$f12,$f20
+        c.ngle.s        $fcc2,$f18,$f23
+        c.ngt.d         $fcc4,$f24,$f7
+        c.ngt.ps        $fcc5,$f30,$f6
+        c.ngt.s         $fcc5,$f8,$f13
+        c.ole.d         $fcc2,$f16,$f31
+        c.ole.ps        $fcc7,$f21,$f8
+        c.ole.s         $fcc3,$f7,$f20
+        c.olt.d         $fcc4,$f19,$f28
+        c.olt.ps        $fcc3,$f7,$f16
+        c.olt.s         $fcc6,$f20,$f7
+        c.seq.d         $fcc4,$f31,$f7
+        c.seq.ps        $fcc6,$f31,$f14
+        c.seq.s         $fcc7,$f1,$f25
+        c.sf.ps         $fcc6,$f4,$f6
+        c.ueq.d         $fcc4,$f13,$f25
+        c.ueq.ps        $fcc1,$f5,$f29
+        c.ueq.s         $fcc6,$f3,$f30
+        c.ule.d         $fcc7,$f25,$f18
+        c.ule.ps        $fcc6,$f17,$f3
+        c.ule.s         $fcc7,$f21,$f30
+        c.ult.d         $fcc6,$f6,$f17
+        c.ult.ps        $fcc7,$f14,$f0
+        c.ult.s         $fcc7,$f24,$f10
+        c.un.d          $fcc6,$f23,$f24
+        c.un.ps         $fcc4,$f2,$f26
+        c.un.s          $fcc1,$f30,$f4
+        cvt.ps.s        $f3,$f18,$f19
+        cmp.eq.ph       $s7,$14
+        cmp.le.ph       $8,$14
+        cmp.lt.ph       $k0,$sp
+        cmpgdu.eq.qb    $s3,$zero,$k0
+        cmpgdu.le.qb    $v1,$15,$s2
+        cmpgdu.lt.qb    $s0,$gp,$sp
+        cmpgu.eq.qb     $14,$s6,$s8
+        cmpgu.le.qb     $9,$a3,$s4
+        cmpgu.lt.qb     $sp,$at,$8
+        cmpu.eq.qb      $v0,$24
+        cmpu.le.qb      $s1,$a1
+        cmpu.lt.qb      $at,$a3
+        cvt.s.pl        $f30,$f1
+        cvt.s.pu        $f14,$f25
+        dmfc0           $10,c0_watchhi,2
+        dmfgc0          $gp,c0_perfcnt,6
+        dmt $k0
+        dmtc0           $15,c0_datalo
+        dmtgc0          $a2,c0_watchlo,2
+        dpa.w.ph        $ac1,$s7,$k0
+        dpaq_s.w.ph     $ac2,$a0,$13
+        dpaq_sa.l.w     $ac0,$a2,$14
+        dpaqx_s.w.ph    $ac3,$a0,$24
+        dpaqx_sa.w.ph   $ac1,$zero,$s5
+        dpau.h.qbl      $ac1,$10,$24
+        dpau.h.qbr      $ac1,$s7,$s6
+        dpax.w.ph       $ac3,$a0,$k0
+        dps.w.ph        $ac1,$a3,$a1
+        dpsq_s.w.ph     $ac0,$gp,$k0
+        dpsq_sa.l.w     $ac0,$a3,$15
+        dpsqx_s.w.ph    $ac3,$13,$a3
+        dpsqx_sa.w.ph   $ac3,$sp,$s2
+        dpsu.h.qbl      $ac2,$14,$10
+        dpsu.h.qbr      $ac2,$a1,$s6
+        dpsx.w.ph       $ac0,$s7,$gp
+        drorv           $at,$a1,$s7
+        dvpe            $s6
+        emt $8
+        evpe            $v0
+        extpdpv         $s6,$ac0,$s8
+        extpv           $13,$ac0,$14
+        extrv.w         $8,$ac3,$at
+        extrv_r.w       $8,$ac1,$s6
+        extrv_rs.w      $gp,$ac1,$s6
+        extrv_s.h       $s2,$ac1,$14
+        fclass.d        $w14,$w27
+        fclass.w        $w19,$w28
+        fexupl.d        $w10,$w29
+        fexupl.w        $w12,$w27
+        fexupr.d        $w31,$w15
+        fexupr.w        $w29,$w12
+        ffint_s.d       $w1,$w30
+        ffint_s.w       $w16,$w14
+        ffint_u.d       $w23,$w18
+        ffint_u.w       $w19,$w12
+        ffql.d          $w2,$w3
+        ffql.w          $w9,$w0
+        ffqr.d          $w25,$w24
+        ffqr.w          $w10,$w6
+        fill.b          $w9,$v1
+        fill.d          $w28,$8
+        fill.h          $w9,$8
+        fill.w          $w31,$15
+        flog2.d         $w12,$w16
+        flog2.w         $w19,$w23
+        fork            $s2,$8,$a0
+        frcp.d          $w12,$w4
+        frcp.w          $w30,$w8
+        frint.d         $w20,$w8
+        frint.w         $w11,$w29
+        frsqrt.d        $w29,$w2
+        frsqrt.w        $w9,$w8
+        fsqrt.d         $w3,$w1
+        fsqrt.w         $w5,$w15
+        ftint_s.d       $w31,$w26
+        ftint_s.w       $w27,$w14
+        ftint_u.d       $w5,$w31
+        ftint_u.w       $w12,$w29
+        ftrunc_s.d      $w4,$w22
+        ftrunc_s.w      $w24,$w7
+        ftrunc_u.d      $w20,$w25
+        ftrunc_u.w      $w7,$w26
+        insv            $s2,$at
+        iret
+        lbe $14,122($9)
+        lbue            $11,-108($10)
+        lbux            $9,$14($v0)
+        lhe $s6,219($v1)
+        lhue            $gp,118($11)
+        lhx $sp,$k0($15)
+        lle $gp,-237($ra)
+        lwe $ra,-145($14)
+        lwle            $11,-42($11)
+        lwre            $sp,-152($24)
+        lwx $12,$12($s4)
+        madd.ps         $f22,$f3,$f14,$f3
+        maq_s.w.phl     $ac2,$25,$11
+        maq_s.w.phr     $ac0,$10,$25
+        maq_sa.w.phl    $ac3,$a1,$v1
+        maq_sa.w.phr    $ac1,$at,$10
+        mfgc0           $s6,c0_datahi1
+        mflo            $9,$ac2
+        modsub          $a3,$12,$a3
+        mov.ps          $f22,$f17
+        movf.ps         $f10,$f28,$fcc6
+        movn.ps         $f31,$f31,$s3
+        movt.ps         $f20,$f25,$fcc2
+        movz.ps         $f18,$f17,$ra
+        msgn.qh         $v0,$v24,$v20
+        msgn.qh         $v12,$v21,$v0[1]
+        msub            $ac2,$sp,$14
+        msub.ps         $f12,$f14,$f29,$f17
+        msubu           $ac2,$a1,$24
+        mtc0            $9,c0_datahi1
+        mtgc0           $s4,$21,7
+        mthi            $v0,$ac1
+        mthlip          $a3,$ac0
+        mul.ph          $s4,$24,$s0
+        mul.ps          $f14,$f0,$f16
+        mul_s.ph        $10,$14,$15
+        muleq_s.w.phl   $11,$s4,$s4
+        muleq_s.w.phr   $s6,$a0,$s8
+        muleu_s.ph.qbl  $a2,$14,$8
+        muleu_s.ph.qbr  $a1,$ra,$9
+        mulq_rs.ph      $s2,$14,$15
+        mulq_rs.w       $at,$s4,$25
+        mulq_s.ph       $s0,$k1,$15
+        mulq_s.w        $9,$a3,$s0
+        mulsa.w.ph      $ac1,$s4,$s6
+        mulsaq_s.w.ph   $ac0,$ra,$s2
+        neg.ps          $f19,$f13
+        nloc.b          $w12,$w30
+        nloc.d          $w16,$w7
+        nloc.h          $w21,$w17
+        nloc.w          $w17,$w16
+        nlzc.b          $w12,$w7
+        nlzc.d          $w14,$w14
+        nlzc.h          $w24,$w24
+        nlzc.w          $w10,$w4
+        nmadd.ps        $f27,$f4,$f9,$f25
+        nmsub.ps        $f6,$f12,$f14,$f17
+        nor.v           $w20,$w20,$w15
+        or.v            $w13,$w23,$w12
+        packrl.ph       $ra,$24,$14
+        pcnt.b          $w30,$w15
+        pcnt.d          $w5,$w16
+        pcnt.h          $w20,$w24
+        pcnt.w          $w22,$w20
+        pick.ph         $ra,$a2,$gp
+        pick.qb         $11,$a0,$gp
+        pll.ps          $f25,$f9,$f30
+        plu.ps          $f1,$f26,$f29
+        preceq.w.phl    $s8,$gp
+        preceq.w.phr    $s5,$15
+        precequ.ph.qbl  $s7,$ra
+        precequ.ph.qbla $a0,$9
+        precequ.ph.qbr  $ra,$s3
+        precequ.ph.qbra $24,$8
+        preceu.ph.qbl   $sp,$8
+        preceu.ph.qbla  $s6,$11
+        preceu.ph.qbr   $gp,$s1
+        preceu.ph.qbra  $k1,$s0
+        precr.qb.ph     $v0,$12,$s8
+        precrq.ph.w     $14,$s8,$24
+        precrq.qb.ph    $a2,$12,$12
+        precrq_rs.ph.w  $a1,$k0,$a3
+        precrqu_s.qb.ph $zero,$gp,$s5
+        pul.ps          $f9,$f30,$f26
+        puu.ps          $f24,$f9,$f2
+        raddu.w.qb      $25,$s3
+        rdpgpr          $s3,$9
+        recip.d         $f19,$f6
+        recip.s         $f3,$f30
+        repl.ph         $at,-307
+        replv.ph        $v1,$s7
+        replv.qb        $25,$12
+        rorv            $13,$a3,$s5
+        rsqrt.d         $f3,$f28
+        rsqrt.s         $f4,$f8
+        sbe $s7,33($s1)
+        sce $sp,189($10)
+        she $24,105($v0)
+        shilo           $ac1,26
+        shilov          $ac2,$10
+        shllv.ph        $10,$s0,$s0
+        shllv.qb        $gp,$v1,$zero
+        shllv_s.ph      $k1,$at,$13
+        shllv_s.w       $s1,$ra,$k0
+        shrav.ph        $25,$s2,$s1
+        shrav.qb        $zero,$24,$11
+        shrav_r.ph      $s3,$11,$25
+        shrav_r.qb      $a0,$sp,$s5
+        shrav_r.w       $s7,$s4,$s6
+        shrlv.ph        $14,$10,$9
+        shrlv.qb        $a2,$s2,$11
+        sub.ps          $f5,$f14,$f26
+        subq.ph         $ra,$9,$s8
+        subq_s.ph       $13,$s8,$s5
+        subq_s.w        $k1,$a2,$a3
+        subqh.ph        $10,$at,$9
+        subqh.w         $v0,$a2,$zero
+        subqh_r.ph      $a0,$12,$s6
+        subqh_r.w       $10,$a2,$gp
+        subu.ph         $9,$s6,$s4
+        subu.qb         $s6,$a2,$s6
+        subu_s.ph       $v1,$a1,$s3
+        subu_s.qb       $s1,$at,$ra
+        subuh.qb        $zero,$gp,$gp
+        subuh_r.qb      $s4,$s8,$s6
+        swe $24,94($k0)
+        swle            $v1,-209($gp)
+        swre            $k0,-202($s2)
+        tlbginv
+        tlbginvf
+        tlbgp
+        tlbgr
+        tlbgwi
+        tlbgwr
+        tlbinv
+        tlbinvf
+        wrpgpr          $zero,$13
+        xor.v           $w20,$w21,$w30
+        yield           $v1,$s0
diff --git a/test/MC/Mips/mips64r3/valid.s b/test/MC/Mips/mips64r3/valid.s
new file mode 100644
index 000000000000..359205500a8f
--- /dev/null
+++ b/test/MC/Mips/mips64r3/valid.s
@@ -0,0 +1,316 @@
+# Instructions that are valid
+#
+# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r3 | FileCheck %s
+a:
+        .set noat
+        abs.d     $f7,$f25             # CHECK: encoding:
+        abs.s     $f9,$f16
+        add       $s7,$s2,$a1
+        add       $9,$14,15176         # CHECK: addi $9, $14, 15176   # encoding: [0x21,0xc9,0x3b,0x48]
+        add       $24,-7193            # CHECK: addi $24, $24, -7193  # encoding: [0x23,0x18,0xe3,0xe7]
+        add.d     $f1,$f7,$f29
+        add.s     $f8,$f21,$f24
+        addi      $13,$9,26322
+        addi      $8,$8,~1             # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
+        addu      $9,$a0,$a2
+        addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
+        and       $s7,$v0,$12
+        and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
+        bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1fl     $fcc0,4688           # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     4688                 # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     $fcc7,27             # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06]
+        bc1t      $fcc0, 4             # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1t      $fcc1, 4             # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
+        bc1t      4                    # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1tl     $fcc0,4688           # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     4688                 # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     $fcc7,27             # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06]
+        bal       21100                # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $0, 21100            # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $6, 21100            # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
+        bltzal    $6, 21100            # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
+        beql      $14,$s3,12544        # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40]
+        bgezall   $12,7293             # CHECK: bgezall $12, 7293    # encoding: [0x05,0x93,0x07,0x1f]
+        bgezl     $4,-6858             # CHECK: bgezl $4, -6858      # encoding: [0x04,0x83,0xf9,0x4d]
+        bgtzl     $10,-3738            # CHECK: bgtzl $10, -3738     # encoding: [0x5d,0x40,0xfc,0x59]
+        blezl     $6,2974              # CHECK: blezl $6, 2974       # encoding: [0x58,0xc0,0x02,0xe7]
+        bltzall   $6,488               # CHECK: bltzall $6, 488      # encoding: [0x04,0xd2,0x00,0x7a]
+        bltzl     $s1,-9964            # CHECK: bltzl $17, -9964     # encoding: [0x06,0x22,0xf6,0x45]
+        bnel      $gp,$s4,5107         # CHECK: bnel $gp, $20, 5107  # encoding: [0x57,0x94,0x04,0xfc]
+        cache     1, 8($5)             # CHECK: cache 1, 8($5)   # encoding: [0xbc,0xa1,0x00,0x08]
+        c.ngl.d   $f29,$f29
+        c.ngle.d  $f0,$f16
+        c.sf.d    $f30,$f0
+        c.sf.s    $f14,$f22
+        ceil.l.d  $f1,$f3
+        ceil.l.s  $f18,$f13
+        ceil.w.d  $f11,$f25
+        ceil.w.s  $f6,$f20
+        cfc1      $s1,$21
+        clo       $11,$a1              # CHECK: clo $11, $5   # encoding: [0x70,0xab,0x58,0x21]
+        clz       $sp,$gp              # CHECK: clz $sp, $gp  # encoding: [0x73,0x9d,0xe8,0x20]
+        ctc1      $a2,$26
+        cvt.d.l   $f4,$f16
+        cvt.d.s   $f22,$f28
+        cvt.d.w   $f26,$f11
+        cvt.l.d   $f24,$f15
+        cvt.l.s   $f11,$f29
+        cvt.s.d   $f26,$f8
+        cvt.s.l   $f15,$f30
+        cvt.s.w   $f22,$f15
+        cvt.w.d   $f20,$f14
+        cvt.w.s   $f20,$f24
+        dadd      $s3,$at,$ra
+        dadd      $sp,$s4,-27705       # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
+        dadd      $sp,-27705           # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
+        daddi     $sp,$s4,-27705
+        daddi     $sp,$s4,-27705       # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
+        daddi     $sp,-27705           # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
+        daddiu    $k0,$s6,-4586
+        daddu     $s3,$at,$ra
+        daddu     $24,$2,18079         # CHECK: daddiu $24, $2, 18079  # encoding: [0x64,0x58,0x46,0x9f]
+        daddu     $19,26943            # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f]
+        dclo      $s2,$a2              # CHECK: dclo $18, $6   # encoding: [0x70,0xd2,0x90,0x25]
+        dclz      $s0,$25              # CHECK: dclz $16, $25  # encoding: [0x73,0x30,0x80,0x24]
+        deret
+        di        $s8                  # CHECK: di  $fp        # encoding: [0x41,0x7e,0x60,0x00]
+        di                             # CHECK: di             # encoding: [0x41,0x60,0x60,0x00]
+        ddiv      $zero,$k0,$s3
+        ddivu     $zero,$s0,$s1
+        div       $zero,$25,$11
+        div.d     $f29,$f20,$f27
+        div.s     $f4,$f5,$f15
+        divu      $zero,$25,$15
+        dmfc1     $12,$f13
+        dmtc1     $s0,$f14
+        dmult     $s7,$9
+        dmultu    $a1,$a2
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
+        drotr     $1,15                # CHECK: drotr $1, $1, 15            # encoding: [0x00,0x21,0x0b,0xfa]
+        drotr     $1,$14,15            # CHECK: drotr $1, $14, 15           # encoding: [0x00,0x2e,0x0b,0xfa]
+        drotr32   $1,15                # CHECK: drotr32 $1, $1, 15          # encoding: [0x00,0x21,0x0b,0xfe]
+        drotr32   $1,$14,15            # CHECK: drotr32 $1, $14, 15         # encoding: [0x00,0x2e,0x0b,0xfe]
+        drotrv    $1,$14,$15           # CHECK: drotrv $1, $14, $15         # encoding: [0x01,0xee,0x08,0x56]
+        dsbh      $v1,$14
+        dshd      $v0,$sp
+        dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
+        dsll      $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
+        dsll      $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
+        dsll32    $zero,18             # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
+        dsll32    $zero,$zero,18       # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
+        dsllv     $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
+        dsra      $gp,10               # CHECK: dsra $gp, $gp, 10           # encoding: [0x00,0x1c,0xe2,0xbb]
+        dsra      $gp,$s2,10           # CHECK: dsra $gp, $18, 10           # encoding: [0x00,0x12,0xe2,0xbb]
+        dsra      $gp,$s2,$s3          # CHECK: dsrav $gp, $18, $19         # encoding: [0x02,0x72,0xe0,0x17]
+        dsra32    $gp,10               # CHECK: dsra32 $gp, $gp, 10         # encoding: [0x00,0x1c,0xe2,0xbf]
+        dsra32    $gp,$s2,10           # CHECK: dsra32 $gp, $18, 10         # encoding: [0x00,0x12,0xe2,0xbf]
+        dsrav     $gp,$s2,$s3          # CHECK: dsrav $gp, $18, $19         # encoding: [0x02,0x72,0xe0,0x17]
+        dsrl      $s3,23               # CHECK: dsrl $19, $19, 23           # encoding: [0x00,0x13,0x9d,0xfa]
+        dsrl      $s3,$6,23            # CHECK: dsrl $19, $6, 23            # encoding: [0x00,0x06,0x9d,0xfa]
+        dsrl      $s3,$6,$s4           # CHECK: dsrlv $19, $6, $20          # encoding: [0x02,0x86,0x98,0x16]
+        dsrl32    $s3,23               # CHECK: dsrl32 $19, $19, 23         # encoding: [0x00,0x13,0x9d,0xfe]
+        dsrl32    $s3,$6,23            # CHECK: dsrl32 $19, $6, 23          # encoding: [0x00,0x06,0x9d,0xfe]
+        dsrlv     $s3,$6,$s4           # CHECK: dsrlv $19, $6, $20          # encoding: [0x02,0x86,0x98,0x16]
+        dsub      $a3,$s6,$8
+        dsub      $a3,$s6,$8
+        dsub      $sp,$s4,-27705       # CHECK: daddi $sp, $20, 27705  # encoding: [0x62,0x9d,0x6c,0x39]
+        dsub      $sp,-27705           # CHECK: daddi $sp, $sp, 27705  # encoding: [0x63,0xbd,0x6c,0x39]
+        dsubi     $sp,$s4,-27705       # CHECK: daddi $sp, $20, 27705  # encoding: [0x62,0x9d,0x6c,0x39]
+        dsubi     $sp,-27705           # CHECK: daddi $sp, $sp, 27705  # encoding: [0x63,0xbd,0x6c,0x39]
+        dsubu     $a1,$a1,$k0
+        dsubu     $a1,$a1,$k0
+        dsubu     $15,$11,5025         # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
+        dsubu     $14,-4586            # CHECK: daddiu $14, $14, 4586  # encoding: [0x65,0xce,0x11,0xea]
+        ehb                            # CHECK: ehb # encoding:  [0x00,0x00,0x00,0xc0]
+        ei        $14                  # CHECK: ei  $14       # encoding: [0x41,0x6e,0x60,0x20]
+        ei                             # CHECK: ei            # encoding: [0x41,0x60,0x60,0x20]
+        eret
+        floor.l.d $f26,$f7
+        floor.l.s $f12,$f5
+        floor.w.d $f14,$f11
+        floor.w.s $f8,$f9
+        j         1f                   # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
+        j         a                    # CHECK: j a     # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
+        j         1328                 # CHECK: j 1328  # encoding: [0x08,0x00,0x01,0x4c]
+        jr.hb     $4                   # CHECK: jr.hb  $4 # encoding: [0x00,0x80,0x04,0x08]
+        jalr.hb   $4                   # CHECK: jalr.hb  $4 # encoding: [0x00,0x80,0xfc,0x09]
+        jalr.hb   $4, $5               # CHECK: jalr.hb  $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
+        lb        $24,-14515($10)
+        lbu       $8,30195($v1)
+        ld        $sp,-28645($s1)
+        ldc1      $f11,16391($s0)
+        ldc2      $8,-21181($at)        # CHECK: ldc2 $8, -21181($1)   # encoding: [0xd8,0x28,0xad,0x43]
+        ldl       $24,-4167($24)
+        ldr       $14,-30358($s4)
+        ldxc1     $f8,$s7($15)
+        lh        $11,-8556($s5)
+        lhu       $s3,-22851($v0)
+        li        $at,-29773
+        li        $zero,-29889
+        ll        $v0,-7321($s2)       # CHECK: ll $2, -7321($18)     # encoding: [0xc2,0x42,0xe3,0x67]
+        lld       $zero,-14736($ra)    # CHECK: lld $zero, -14736($ra) # encoding: [0xd3,0xe0,0xc6,0x70]
+        luxc1     $f19,$s6($s5)
+        lw        $8,5674($a1)
+        lwc1      $f16,10225($k0)
+        lwc2      $18,-841($a2)        # CHECK: lwc2 $18, -841($6)     # encoding: [0xc8,0xd2,0xfc,0xb7]
+        lwl       $s4,-4231($15)
+        lwr       $zero,-19147($gp)
+        lwu       $s3,-24086($v1)
+        lwxc1     $f12,$s1($s8)
+        madd      $s6,$13
+        madd      $zero,$9
+        madd.s    $f1,$f31,$f19,$f25
+        maddu     $s3,$gp
+        maddu     $24,$s2
+        mfc0      $a2,$14,1
+        mfc1      $a3,$f27
+        mfhc1     $s8,$f24
+        mfhi      $s3
+        mfhi      $sp
+        mflo      $s1
+        mov.d     $f20,$f14
+        mov.s     $f2,$f27
+        move      $a0,$a3
+        move      $s5,$a0
+        move      $s8,$a0
+        move      $25,$a2
+        movf      $gp,$8,$fcc7
+        movf.d    $f6,$f11,$fcc5
+        movf.s    $f23,$f5,$fcc6
+        movn      $v1,$s1,$s0
+        movn.d    $f27,$f21,$k0
+        movn.s    $f12,$f0,$s7
+        movt      $zero,$s4,$fcc5
+        movt.d    $f0,$f2,$fcc0
+        movt.s    $f30,$f2,$fcc1
+        movz      $a1,$s6,$9
+        movz.d    $f12,$f29,$9
+        movz.s    $f25,$f7,$v1
+        msub      $s7,$k1
+        msub.s    $f12,$f19,$f10,$f16
+        msubu     $15,$a1
+        mtc0      $9,$29,3
+        mtc1      $s8,$f9
+        mthc1     $zero,$f16
+        mthi      $s1
+        mtlo      $sp
+        mtlo      $25
+        mul       $s0,$s4,$at
+        mul.d     $f20,$f20,$f16
+        mul.s     $f30,$f10,$f2
+        mult      $sp,$s4
+        mult      $sp,$v0
+        multu     $gp,$k0
+        multu     $9,$s2
+        negu      $2                   # CHECK: negu $2, $2            # encoding: [0x00,0x02,0x10,0x23]
+        negu      $2,$3                # CHECK: negu $2, $3            # encoding: [0x00,0x03,0x10,0x23]
+        neg.d     $f27,$f18
+        neg.s     $f1,$f15
+        nmadd.s   $f0,$f5,$f25,$f12
+        nmsub.s   $f1,$f24,$f19,$f4
+        nop
+        nor       $a3,$zero,$a3
+        or        $12,$s0,$sp
+        or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
+        pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
+        pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
+        # FIXME: Use the code generator in order to print the .set directives
+        #        instead of the instruction printer.
+        rdhwr     $sp,$11              # CHECK:      .set  push
+                                       # CHECK-NEXT: .set  mips32r2
+                                       # CHECK-NEXT: rdhwr $sp, $11
+                                       # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
+        rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
+        rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
+        rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
+        round.l.d $f12,$f1
+        round.l.s $f25,$f5
+        round.w.d $f6,$f4
+        round.w.s $f27,$f28
+        sb        $s6,-19857($14)
+        sc        $15,18904($s3)       # CHECK: sc $15, 18904($19)     # encoding: [0xe2,0x6f,0x49,0xd8]
+        scd       $15,-8243($sp)       # CHECK: scd $15, -8243($sp)    # encoding: [0xf3,0xaf,0xdf,0xcd]
+        sdbbp                          # CHECK: sdbbp                  # encoding: [0x70,0x00,0x00,0x3f]
+        sdbbp     34                   # CHECK: sdbbp 34               # encoding: [0x70,0x00,0x08,0xbf]
+        sd        $12,5835($10)
+        sdc1      $f31,30574($13)
+        sdc2      $20,23157($s2)       # CHECK: sdc2 $20, 23157($18)   # encoding: [0xfa,0x54,0x5a,0x75]
+        sdl       $a3,-20961($s8)
+        sdr       $11,-20423($12)
+        sdxc1     $f11,$10($14)
+        seb       $25,$15
+        seh       $v1,$12
+        sh        $14,-6704($15)
+        sll       $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
+        sll       $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+        sll       $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        sllv      $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        slt       $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+        slti      $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+        sltiu     $25,$25,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+        sltu      $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+        sltu      $24,$25,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
+        sqrt.d    $f17,$f22
+        sqrt.s    $f0,$f1
+        sra       $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
+        sra       $s1,$s7,15           # CHECK: sra $17, $23, 15       # encoding: [0x00,0x17,0x8b,0xc3]
+        sra       $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srav      $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srl       $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        srlv      $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        ssnop                          # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
+        sub       $s6,$s3,$12
+        sub       $22,$17,-3126        # CHECK: addi $22, $17, 3126    # encoding: [0x22,0x36,0x0c,0x36]
+        sub       $13,6512             # CHECK: addi $13, $13, -6512   # encoding: [0x21,0xad,0xe6,0x90]
+        sub.d     $f18,$f3,$f17
+        sub.s     $f23,$f22,$f22
+        subu      $sp,$s6,$s6
+        suxc1     $f12,$k1($13)
+        sw        $ra,-10160($sp)
+        swc1      $f6,-8465($24)
+        swc2      $25,24880($s0)       # CHECK: swc2 $25, 24880($16)   # encoding: [0xea,0x19,0x61,0x30]
+        swl       $15,13694($s3)
+        swr       $s1,-26590($14)
+        swxc1     $f19,$12($k0)
+        sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
+        teq       $5,$7,620            # CHECK: teq $5, $7, 620        # encoding: [0x00,0xa7,0x9b,0x34]
+        teqi      $s5,-17504
+        tge       $7,$10               # CHECK: tge $7, $10            # encoding: [0x00,0xea,0x00,0x30]
+        tge       $5,$19,340           # CHECK: tge $5, $19, 340       # encoding: [0x00,0xb3,0x55,0x30]
+        tgei      $s1,5025
+        tgeiu     $sp,-28621
+        tgeu      $22,$28              # CHECK: tgeu $22, $gp          # encoding: [0x02,0xdc,0x00,0x31]
+        tgeu      $20,$14,379          # CHECK: tgeu $20, $14, 379     # encoding: [0x02,0x8e,0x5e,0xf1]
+        tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+        tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+        tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+        tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $15,$13              # CHECK: tlt $15, $13           # encoding: [0x01,0xed,0x00,0x32]
+        tlt       $2,$19,133           # CHECK: tlt $2, $19, 133       # encoding: [0x00,0x53,0x21,0x72]
+        tlti      $14,-21059
+        tltiu     $ra,-5076
+        tltu      $11,$16              # CHECK: tltu $11, $16          # encoding: [0x01,0x70,0x00,0x33]
+        tltu      $16,$29,1016         # CHECK: tltu $16, $sp, 1016    # encoding: [0x02,0x1d,0xfe,0x33]
+        tne       $6,$17               # CHECK: tne $6, $17            # encoding: [0x00,0xd1,0x00,0x36]
+        tne       $7,$8,885            # CHECK: tne $7, $8, 885        # encoding: [0x00,0xe8,0xdd,0x76]
+        tnei      $12,-29647
+        trunc.l.d $f23,$f23
+        trunc.l.s $f28,$f31
+        trunc.w.d $f22,$f15
+        trunc.w.s $f28,$f30
+        xor       $s2,$a0,$s8
+        xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
+        wsbh      $k1,$9
+
+1:
diff --git a/test/MC/Mips/mips64r5/abi-bad.s b/test/MC/Mips/mips64r5/abi-bad.s
new file mode 100644
index 000000000000..c6bb29a8b20d
--- /dev/null
+++ b/test/MC/Mips/mips64r5/abi-bad.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc %s -triple mips-unknown-linux -mcpu=mips64r5 2>&1 | FileCheck %s
+        .set fp=xx
+# CHECK: error: '.set fp=xx' requires the O32 ABI
+# CHECK: .set fp=xx
+# CHECK:          ^
diff --git a/test/MC/Mips/mips64r5/abiflags.s b/test/MC/Mips/mips64r5/abiflags.s
new file mode 100644
index 000000000000..43a5fe618bcc
--- /dev/null
+++ b/test/MC/Mips/mips64r5/abiflags.s
@@ -0,0 +1,36 @@
+# RUN: llvm-mc %s -arch=mips -mcpu=mips64r5 | \
+# RUN:   FileCheck %s -check-prefix=CHECK-ASM
+#
+# RUN: llvm-mc %s -arch=mips -mcpu=mips64r5 -filetype=obj -o - | \
+# RUN:   llvm-readobj -sections -section-data -section-relocations - | \
+# RUN:     FileCheck %s -check-prefix=CHECK-OBJ
+
+# CHECK-ASM: .module fp=64
+
+# Checking if the Mips.abiflags were correctly emitted.
+# CHECK-OBJ:       Section {
+# CHECK-OBJ:         Index: 5
+# CHECK-OBJ-LABEL:   Name: .MIPS.abiflags
+# CHECK-OBJ:         Type: SHT_MIPS_ABIFLAGS (0x7000002A)
+# CHECK-OBJ:          Flags [ (0x2)
+# CHECK-OBJ:           SHF_ALLOC (0x2)
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         Address: 0x0
+# CHECK-OBJ:         Size: 24
+# CHECK-OBJ:         Link: 0
+# CHECK-OBJ:         Info: 0
+# CHECK-OBJ:         AddressAlignment: 8
+# CHECK-OBJ:         EntrySize: 24
+# CHECK-OBJ:         Relocations [
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         SectionData (
+# CHECK-OBJ:           0000: 00004005 02020001 00000000 00000000  |..@.............|
+# CHECK-OBJ:           0010: 00000001 00000000                    |........|
+# CHECK-OBJ:         )
+# CHECK-OBJ-LABEL: }
+
+        .module fp=64
+
+# FIXME: Test should include gnu_attributes directive when implemented.
+#        An explicit .gnu_attribute must be checked against the effective
+#        command line options and any inconsistencies reported via a warning.
diff --git a/test/MC/Mips/mips64r5/invalid.s b/test/MC/Mips/mips64r5/invalid.s
new file mode 100644
index 000000000000..8319debaa30c
--- /dev/null
+++ b/test/MC/Mips/mips64r5/invalid.s
@@ -0,0 +1,10 @@
+# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g.
+# invalid set of operands or operand's restrictions not met).
+
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r5 2>%t1
+# RUN: FileCheck %s < %t1 -check-prefix=ASM
+
+        .text
+        .set noreorder
+        jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
+        jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
diff --git a/test/MC/Mips/mips64r5/valid-xfail.s b/test/MC/Mips/mips64r5/valid-xfail.s
new file mode 100644
index 000000000000..04221ddb8630
--- /dev/null
+++ b/test/MC/Mips/mips64r5/valid-xfail.s
@@ -0,0 +1,306 @@
+# Instructions that should be valid but currently fail for known reasons (e.g.
+# they aren't implemented yet).
+# This test is set up to XPASS if any instruction generates an encoding.
+#
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r5 | not FileCheck %s
+# CHECK-NOT: encoding
+# XFAIL: *
+
+        .set noat
+        abs.ps          $f22,$f8
+        absq_s.ph       $8,$a0
+        absq_s.qb       $15,$s1
+        absq_s.w        $s3,$ra
+        add.ps          $f25,$f27,$f13
+        addq.ph         $s1,$15,$at
+        addq_s.ph       $s3,$s6,$s2
+        addq_s.w        $a2,$8,$at
+        addqh.ph        $s4,$14,$s1
+        addqh.w         $s7,$s7,$k1
+        addqh_r.ph      $sp,$25,$s8
+        addqh_r.w       $8,$v1,$zero
+        addsc           $s8,$15,$12
+        addu.ph         $a2,$14,$s3
+        addu.qb         $s6,$v1,$v1
+        addu_s.ph       $a3,$s3,$gp
+        addu_s.qb       $s4,$s8,$s1
+        adduh.qb        $a1,$a1,$at
+        adduh_r.qb      $a0,$9,$12
+        addwc           $k0,$s6,$s7
+        alnv.ob         $v22,$v19,$v30,$v1
+        alnv.ob         $v31,$v23,$v30,$at
+        alnv.ob         $v8,$v17,$v30,$a1
+        alnv.ps         $f12,$f18,$f30,$12
+        and.v           $w10,$w25,$w29
+        bitrev          $14,$at
+        bmnz.v          $w15,$w2,$w28
+        bmz.v           $w13,$w11,$w21
+        bsel.v          $w28,$w7,$w0
+        c.eq.d          $fcc1,$f15,$f15
+        c.eq.ps         $fcc5,$f0,$f9
+        c.eq.s          $fcc5,$f24,$f17
+        c.f.d           $fcc4,$f11,$f21
+        c.f.ps          $fcc6,$f11,$f11
+        c.f.s           $fcc4,$f30,$f7
+        c.le.d          $fcc4,$f18,$f1
+        c.le.ps         $fcc1,$f7,$f20
+        c.le.s          $fcc6,$f24,$f4
+        c.lt.d          $fcc3,$f9,$f3
+        c.lt.ps         $f19,$f5
+        c.lt.s          $fcc2,$f17,$f14
+        c.nge.d         $fcc5,$f21,$f16
+        c.nge.ps        $f1,$f26
+        c.nge.s         $fcc3,$f11,$f8
+        c.ngl.ps        $f21,$f30
+        c.ngl.s         $fcc2,$f31,$f23
+        c.ngle.ps       $fcc7,$f12,$f20
+        c.ngle.s        $fcc2,$f18,$f23
+        c.ngt.d         $fcc4,$f24,$f7
+        c.ngt.ps        $fcc5,$f30,$f6
+        c.ngt.s         $fcc5,$f8,$f13
+        c.ole.d         $fcc2,$f16,$f31
+        c.ole.ps        $fcc7,$f21,$f8
+        c.ole.s         $fcc3,$f7,$f20
+        c.olt.d         $fcc4,$f19,$f28
+        c.olt.ps        $fcc3,$f7,$f16
+        c.olt.s         $fcc6,$f20,$f7
+        c.seq.d         $fcc4,$f31,$f7
+        c.seq.ps        $fcc6,$f31,$f14
+        c.seq.s         $fcc7,$f1,$f25
+        c.sf.ps         $fcc6,$f4,$f6
+        c.ueq.d         $fcc4,$f13,$f25
+        c.ueq.ps        $fcc1,$f5,$f29
+        c.ueq.s         $fcc6,$f3,$f30
+        c.ule.d         $fcc7,$f25,$f18
+        c.ule.ps        $fcc6,$f17,$f3
+        c.ule.s         $fcc7,$f21,$f30
+        c.ult.d         $fcc6,$f6,$f17
+        c.ult.ps        $fcc7,$f14,$f0
+        c.ult.s         $fcc7,$f24,$f10
+        c.un.d          $fcc6,$f23,$f24
+        c.un.ps         $fcc4,$f2,$f26
+        c.un.s          $fcc1,$f30,$f4
+        cvt.ps.s        $f3,$f18,$f19
+        cmp.eq.ph       $s7,$14
+        cmp.le.ph       $8,$14
+        cmp.lt.ph       $k0,$sp
+        cmpgdu.eq.qb    $s3,$zero,$k0
+        cmpgdu.le.qb    $v1,$15,$s2
+        cmpgdu.lt.qb    $s0,$gp,$sp
+        cmpgu.eq.qb     $14,$s6,$s8
+        cmpgu.le.qb     $9,$a3,$s4
+        cmpgu.lt.qb     $sp,$at,$8
+        cmpu.eq.qb      $v0,$24
+        cmpu.le.qb      $s1,$a1
+        cmpu.lt.qb      $at,$a3
+        cvt.s.pl        $f30,$f1
+        cvt.s.pu        $f14,$f25
+        dmfc0           $10,c0_watchhi,2
+        dmfgc0          $gp,c0_perfcnt,6
+        dmt $k0
+        dmtc0           $15,c0_datalo
+        dmtgc0          $a2,c0_watchlo,2
+        dpa.w.ph        $ac1,$s7,$k0
+        dpaq_s.w.ph     $ac2,$a0,$13
+        dpaq_sa.l.w     $ac0,$a2,$14
+        dpaqx_s.w.ph    $ac3,$a0,$24
+        dpaqx_sa.w.ph   $ac1,$zero,$s5
+        dpau.h.qbl      $ac1,$10,$24
+        dpau.h.qbr      $ac1,$s7,$s6
+        dpax.w.ph       $ac3,$a0,$k0
+        dps.w.ph        $ac1,$a3,$a1
+        dpsq_s.w.ph     $ac0,$gp,$k0
+        dpsq_sa.l.w     $ac0,$a3,$15
+        dpsqx_s.w.ph    $ac3,$13,$a3
+        dpsqx_sa.w.ph   $ac3,$sp,$s2
+        dpsu.h.qbl      $ac2,$14,$10
+        dpsu.h.qbr      $ac2,$a1,$s6
+        dpsx.w.ph       $ac0,$s7,$gp
+        drorv           $at,$a1,$s7
+        dvpe            $s6
+        emt $8
+        evpe            $v0
+        extpdpv         $s6,$ac0,$s8
+        extpv           $13,$ac0,$14
+        extrv.w         $8,$ac3,$at
+        extrv_r.w       $8,$ac1,$s6
+        extrv_rs.w      $gp,$ac1,$s6
+        extrv_s.h       $s2,$ac1,$14
+        fclass.d        $w14,$w27
+        fclass.w        $w19,$w28
+        fexupl.d        $w10,$w29
+        fexupl.w        $w12,$w27
+        fexupr.d        $w31,$w15
+        fexupr.w        $w29,$w12
+        ffint_s.d       $w1,$w30
+        ffint_s.w       $w16,$w14
+        ffint_u.d       $w23,$w18
+        ffint_u.w       $w19,$w12
+        ffql.d          $w2,$w3
+        ffql.w          $w9,$w0
+        ffqr.d          $w25,$w24
+        ffqr.w          $w10,$w6
+        fill.b          $w9,$v1
+        fill.d          $w28,$8
+        fill.h          $w9,$8
+        fill.w          $w31,$15
+        flog2.d         $w12,$w16
+        flog2.w         $w19,$w23
+        fork            $s2,$8,$a0
+        frcp.d          $w12,$w4
+        frcp.w          $w30,$w8
+        frint.d         $w20,$w8
+        frint.w         $w11,$w29
+        frsqrt.d        $w29,$w2
+        frsqrt.w        $w9,$w8
+        fsqrt.d         $w3,$w1
+        fsqrt.w         $w5,$w15
+        ftint_s.d       $w31,$w26
+        ftint_s.w       $w27,$w14
+        ftint_u.d       $w5,$w31
+        ftint_u.w       $w12,$w29
+        ftrunc_s.d      $w4,$w22
+        ftrunc_s.w      $w24,$w7
+        ftrunc_u.d      $w20,$w25
+        ftrunc_u.w      $w7,$w26
+        insv            $s2,$at
+        iret
+        lbe $14,122($9)
+        lbue            $11,-108($10)
+        lbux            $9,$14($v0)
+        lhe $s6,219($v1)
+        lhue            $gp,118($11)
+        lhx $sp,$k0($15)
+        lle $gp,-237($ra)
+        lwe $ra,-145($14)
+        lwle            $11,-42($11)
+        lwre            $sp,-152($24)
+        lwx $12,$12($s4)
+        madd.ps         $f22,$f3,$f14,$f3
+        maq_s.w.phl     $ac2,$25,$11
+        maq_s.w.phr     $ac0,$10,$25
+        maq_sa.w.phl    $ac3,$a1,$v1
+        maq_sa.w.phr    $ac1,$at,$10
+        mfgc0           $s6,c0_datahi1
+        mflo            $9,$ac2
+        modsub          $a3,$12,$a3
+        mov.ps          $f22,$f17
+        movf.ps         $f10,$f28,$fcc6
+        movn.ps         $f31,$f31,$s3
+        movt.ps         $f20,$f25,$fcc2
+        movz.ps         $f18,$f17,$ra
+        msgn.qh         $v0,$v24,$v20
+        msgn.qh         $v12,$v21,$v0[1]
+        msub            $ac2,$sp,$14
+        msub.ps         $f12,$f14,$f29,$f17
+        msubu           $ac2,$a1,$24
+        mtc0            $9,c0_datahi1
+        mtgc0           $s4,$21,7
+        mthi            $v0,$ac1
+        mthlip          $a3,$ac0
+        mul.ph          $s4,$24,$s0
+        mul.ps          $f14,$f0,$f16
+        mul_s.ph        $10,$14,$15
+        muleq_s.w.phl   $11,$s4,$s4
+        muleq_s.w.phr   $s6,$a0,$s8
+        muleu_s.ph.qbl  $a2,$14,$8
+        muleu_s.ph.qbr  $a1,$ra,$9
+        mulq_rs.ph      $s2,$14,$15
+        mulq_rs.w       $at,$s4,$25
+        mulq_s.ph       $s0,$k1,$15
+        mulq_s.w        $9,$a3,$s0
+        mulsa.w.ph      $ac1,$s4,$s6
+        mulsaq_s.w.ph   $ac0,$ra,$s2
+        neg.ps          $f19,$f13
+        nloc.b          $w12,$w30
+        nloc.d          $w16,$w7
+        nloc.h          $w21,$w17
+        nloc.w          $w17,$w16
+        nlzc.b          $w12,$w7
+        nlzc.d          $w14,$w14
+        nlzc.h          $w24,$w24
+        nlzc.w          $w10,$w4
+        nmadd.ps        $f27,$f4,$f9,$f25
+        nmsub.ps        $f6,$f12,$f14,$f17
+        nor.v           $w20,$w20,$w15
+        or.v            $w13,$w23,$w12
+        packrl.ph       $ra,$24,$14
+        pcnt.b          $w30,$w15
+        pcnt.d          $w5,$w16
+        pcnt.h          $w20,$w24
+        pcnt.w          $w22,$w20
+        pick.ph         $ra,$a2,$gp
+        pick.qb         $11,$a0,$gp
+        pll.ps          $f25,$f9,$f30
+        plu.ps          $f1,$f26,$f29
+        preceq.w.phl    $s8,$gp
+        preceq.w.phr    $s5,$15
+        precequ.ph.qbl  $s7,$ra
+        precequ.ph.qbla $a0,$9
+        precequ.ph.qbr  $ra,$s3
+        precequ.ph.qbra $24,$8
+        preceu.ph.qbl   $sp,$8
+        preceu.ph.qbla  $s6,$11
+        preceu.ph.qbr   $gp,$s1
+        preceu.ph.qbra  $k1,$s0
+        precr.qb.ph     $v0,$12,$s8
+        precrq.ph.w     $14,$s8,$24
+        precrq.qb.ph    $a2,$12,$12
+        precrq_rs.ph.w  $a1,$k0,$a3
+        precrqu_s.qb.ph $zero,$gp,$s5
+        pul.ps          $f9,$f30,$f26
+        puu.ps          $f24,$f9,$f2
+        raddu.w.qb      $25,$s3
+        rdpgpr          $s3,$9
+        recip.d         $f19,$f6
+        recip.s         $f3,$f30
+        repl.ph         $at,-307
+        replv.ph        $v1,$s7
+        replv.qb        $25,$12
+        rorv            $13,$a3,$s5
+        rsqrt.d         $f3,$f28
+        rsqrt.s         $f4,$f8
+        sbe $s7,33($s1)
+        sce $sp,189($10)
+        she $24,105($v0)
+        shilo           $ac1,26
+        shilov          $ac2,$10
+        shllv.ph        $10,$s0,$s0
+        shllv.qb        $gp,$v1,$zero
+        shllv_s.ph      $k1,$at,$13
+        shllv_s.w       $s1,$ra,$k0
+        shrav.ph        $25,$s2,$s1
+        shrav.qb        $zero,$24,$11
+        shrav_r.ph      $s3,$11,$25
+        shrav_r.qb      $a0,$sp,$s5
+        shrav_r.w       $s7,$s4,$s6
+        shrlv.ph        $14,$10,$9
+        shrlv.qb        $a2,$s2,$11
+        sub.ps          $f5,$f14,$f26
+        subq.ph         $ra,$9,$s8
+        subq_s.ph       $13,$s8,$s5
+        subq_s.w        $k1,$a2,$a3
+        subqh.ph        $10,$at,$9
+        subqh.w         $v0,$a2,$zero
+        subqh_r.ph      $a0,$12,$s6
+        subqh_r.w       $10,$a2,$gp
+        subu.ph         $9,$s6,$s4
+        subu.qb         $s6,$a2,$s6
+        subu_s.ph       $v1,$a1,$s3
+        subu_s.qb       $s1,$at,$ra
+        subuh.qb        $zero,$gp,$gp
+        subuh_r.qb      $s4,$s8,$s6
+        swe $24,94($k0)
+        swle            $v1,-209($gp)
+        swre            $k0,-202($s2)
+        tlbginv
+        tlbginvf
+        tlbgp
+        tlbgr
+        tlbgwi
+        tlbgwr
+        tlbinv
+        tlbinvf
+        wrpgpr          $zero,$13
+        xor.v           $w20,$w21,$w30
+        yield           $v1,$s0
diff --git a/test/MC/Mips/mips64r5/valid.s b/test/MC/Mips/mips64r5/valid.s
new file mode 100644
index 000000000000..844663080b35
--- /dev/null
+++ b/test/MC/Mips/mips64r5/valid.s
@@ -0,0 +1,316 @@
+# Instructions that are valid
+#
+# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r5 | FileCheck %s
+a:
+        .set noat
+        abs.d     $f7,$f25             # CHECK: encoding:
+        abs.s     $f9,$f16
+        add       $s7,$s2,$a1
+        add       $9,$14,15176         # CHECK: addi $9, $14, 15176   # encoding: [0x21,0xc9,0x3b,0x48]
+        add       $24,-7193            # CHECK: addi $24, $24, -7193  # encoding: [0x23,0x18,0xe3,0xe7]
+        add.d     $f1,$f7,$f29
+        add.s     $f8,$f21,$f24
+        addi      $13,$9,26322
+        addi      $8,$8,~1             # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
+        addu      $9,$a0,$a2
+        addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
+        and       $s7,$v0,$12
+        and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
+        bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1fl     $fcc0,4688           # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     4688                 # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     $fcc7,27             # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06]
+        bc1t      $fcc0, 4             # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1t      $fcc1, 4             # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
+        bc1t      4                    # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1tl     $fcc0,4688           # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     4688                 # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     $fcc7,27             # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06]
+        bal       21100                # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $0, 21100            # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $6, 21100            # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
+        bltzal    $6, 21100            # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
+        beql      $14,$s3,12544        # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40]
+        bgezall   $12,7293             # CHECK: bgezall $12, 7293    # encoding: [0x05,0x93,0x07,0x1f]
+        bgezl     $4,-6858             # CHECK: bgezl $4, -6858      # encoding: [0x04,0x83,0xf9,0x4d]
+        bgtzl     $10,-3738            # CHECK: bgtzl $10, -3738     # encoding: [0x5d,0x40,0xfc,0x59]
+        blezl     $6,2974              # CHECK: blezl $6, 2974       # encoding: [0x58,0xc0,0x02,0xe7]
+        bltzall   $6,488               # CHECK: bltzall $6, 488      # encoding: [0x04,0xd2,0x00,0x7a]
+        bltzl     $s1,-9964            # CHECK: bltzl $17, -9964     # encoding: [0x06,0x22,0xf6,0x45]
+        bnel      $gp,$s4,5107         # CHECK: bnel $gp, $20, 5107  # encoding: [0x57,0x94,0x04,0xfc]
+        cache     1, 8($5)             # CHECK: cache 1, 8($5)   # encoding: [0xbc,0xa1,0x00,0x08]
+        c.ngl.d   $f29,$f29
+        c.ngle.d  $f0,$f16
+        c.sf.d    $f30,$f0
+        c.sf.s    $f14,$f22
+        ceil.l.d  $f1,$f3
+        ceil.l.s  $f18,$f13
+        ceil.w.d  $f11,$f25
+        ceil.w.s  $f6,$f20
+        cfc1      $s1,$21
+        clo       $11,$a1              # CHECK: clo $11, $5   # encoding: [0x70,0xab,0x58,0x21]
+        clz       $sp,$gp              # CHECK: clz $sp, $gp  # encoding: [0x73,0x9d,0xe8,0x20]
+        ctc1      $a2,$26
+        cvt.d.l   $f4,$f16
+        cvt.d.s   $f22,$f28
+        cvt.d.w   $f26,$f11
+        cvt.l.d   $f24,$f15
+        cvt.l.s   $f11,$f29
+        cvt.s.d   $f26,$f8
+        cvt.s.l   $f15,$f30
+        cvt.s.w   $f22,$f15
+        cvt.w.d   $f20,$f14
+        cvt.w.s   $f20,$f24
+        dadd      $s3,$at,$ra
+        dadd      $sp,$s4,-27705       # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
+        dadd      $sp,-27705           # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
+        daddi     $sp,$s4,-27705
+        daddi     $sp,$s4,-27705       # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
+        daddi     $sp,-27705           # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
+        daddiu    $k0,$s6,-4586
+        daddu     $s3,$at,$ra
+        daddu     $24,$2,18079         # CHECK: daddiu $24, $2, 18079  # encoding: [0x64,0x58,0x46,0x9f]
+        daddu     $19,26943            # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f]
+        dclo      $s2,$a2              # CHECK: dclo $18, $6   # encoding: [0x70,0xd2,0x90,0x25]
+        dclz      $s0,$25              # CHECK: dclz $16, $25  # encoding: [0x73,0x30,0x80,0x24]
+        deret
+        di        $s8                  # CHECK: di  $fp        # encoding: [0x41,0x7e,0x60,0x00]
+        di                             # CHECK: di             # encoding: [0x41,0x60,0x60,0x00]
+        ddiv      $zero,$k0,$s3
+        ddivu     $zero,$s0,$s1
+        div       $zero,$25,$11
+        div.d     $f29,$f20,$f27
+        div.s     $f4,$f5,$f15
+        divu      $zero,$25,$15
+        dmfc1     $12,$f13
+        dmtc1     $s0,$f14
+        dmult     $s7,$9
+        dmultu    $a1,$a2
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
+        drotr     $1,15                # CHECK: drotr $1, $1, 15            # encoding: [0x00,0x21,0x0b,0xfa]
+        drotr     $1,$14,15            # CHECK: drotr $1, $14, 15           # encoding: [0x00,0x2e,0x0b,0xfa]
+        drotr32   $1,15                # CHECK: drotr32 $1, $1, 15          # encoding: [0x00,0x21,0x0b,0xfe]
+        drotr32   $1,$14,15            # CHECK: drotr32 $1, $14, 15         # encoding: [0x00,0x2e,0x0b,0xfe]
+        drotrv    $1,$14,$15           # CHECK: drotrv $1, $14, $15         # encoding: [0x01,0xee,0x08,0x56]
+        dsbh      $v1,$14
+        dshd      $v0,$sp
+        dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
+        dsll      $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
+        dsll      $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
+        dsll32    $zero,18             # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
+        dsll32    $zero,$zero,18       # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
+        dsllv     $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
+        dsra      $gp,10               # CHECK: dsra $gp, $gp, 10           # encoding: [0x00,0x1c,0xe2,0xbb]
+        dsra      $gp,$s2,10           # CHECK: dsra $gp, $18, 10           # encoding: [0x00,0x12,0xe2,0xbb]
+        dsra      $gp,$s2,$s3          # CHECK: dsrav $gp, $18, $19         # encoding: [0x02,0x72,0xe0,0x17]
+        dsra32    $gp,10               # CHECK: dsra32 $gp, $gp, 10         # encoding: [0x00,0x1c,0xe2,0xbf]
+        dsra32    $gp,$s2,10           # CHECK: dsra32 $gp, $18, 10         # encoding: [0x00,0x12,0xe2,0xbf]
+        dsrav     $gp,$s2,$s3          # CHECK: dsrav $gp, $18, $19         # encoding: [0x02,0x72,0xe0,0x17]
+        dsrl      $s3,23               # CHECK: dsrl $19, $19, 23           # encoding: [0x00,0x13,0x9d,0xfa]
+        dsrl      $s3,$6,23            # CHECK: dsrl $19, $6, 23            # encoding: [0x00,0x06,0x9d,0xfa]
+        dsrl      $s3,$6,$s4           # CHECK: dsrlv $19, $6, $20          # encoding: [0x02,0x86,0x98,0x16]
+        dsrl32    $s3,23               # CHECK: dsrl32 $19, $19, 23         # encoding: [0x00,0x13,0x9d,0xfe]
+        dsrl32    $s3,$6,23            # CHECK: dsrl32 $19, $6, 23          # encoding: [0x00,0x06,0x9d,0xfe]
+        dsrlv     $s3,$6,$s4           # CHECK: dsrlv $19, $6, $20          # encoding: [0x02,0x86,0x98,0x16]
+        dsub      $a3,$s6,$8
+        dsub      $a3,$s6,$8
+        dsub      $sp,$s4,-27705       # CHECK: daddi $sp, $20, 27705  # encoding: [0x62,0x9d,0x6c,0x39]
+        dsub      $sp,-27705           # CHECK: daddi $sp, $sp, 27705  # encoding: [0x63,0xbd,0x6c,0x39]
+        dsubi     $sp,$s4,-27705       # CHECK: daddi $sp, $20, 27705  # encoding: [0x62,0x9d,0x6c,0x39]
+        dsubi     $sp,-27705           # CHECK: daddi $sp, $sp, 27705  # encoding: [0x63,0xbd,0x6c,0x39]
+        dsubu     $a1,$a1,$k0
+        dsubu     $a1,$a1,$k0
+        dsubu     $15,$11,5025         # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
+        dsubu     $14,-4586            # CHECK: daddiu $14, $14, 4586  # encoding: [0x65,0xce,0x11,0xea]
+        ehb                            # CHECK: ehb # encoding:  [0x00,0x00,0x00,0xc0]
+        ei        $14                  # CHECK: ei  $14       # encoding: [0x41,0x6e,0x60,0x20]
+        ei                             # CHECK: ei            # encoding: [0x41,0x60,0x60,0x20]
+        eret
+        floor.l.d $f26,$f7
+        floor.l.s $f12,$f5
+        floor.w.d $f14,$f11
+        floor.w.s $f8,$f9
+        j         1f                   # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
+        j         a                    # CHECK: j a     # encoding: [0b000010AA,A,A,A]
+                                       # CHECK:         #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
+        j         1328                 # CHECK: j 1328  # encoding: [0x08,0x00,0x01,0x4c]
+        jr.hb     $4                   # CHECK: jr.hb  $4 # encoding: [0x00,0x80,0x04,0x08]
+        jalr.hb   $4                   # CHECK: jalr.hb  $4 # encoding: [0x00,0x80,0xfc,0x09]
+        jalr.hb   $4, $5               # CHECK: jalr.hb  $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
+        lb        $24,-14515($10)
+        lbu       $8,30195($v1)
+        ld        $sp,-28645($s1)
+        ldc1      $f11,16391($s0)
+        ldc2      $8,-21181($at)        # CHECK: ldc2 $8, -21181($1)   # encoding: [0xd8,0x28,0xad,0x43]
+        ldl       $24,-4167($24)
+        ldr       $14,-30358($s4)
+        ldxc1     $f8,$s7($15)
+        lh        $11,-8556($s5)
+        lhu       $s3,-22851($v0)
+        li        $at,-29773
+        li        $zero,-29889
+        ll        $v0,-7321($s2)       # CHECK: ll $2, -7321($18)     # encoding: [0xc2,0x42,0xe3,0x67]
+        lld       $zero,-14736($ra)    # CHECK: lld $zero, -14736($ra) # encoding: [0xd3,0xe0,0xc6,0x70]
+        luxc1     $f19,$s6($s5)
+        lw        $8,5674($a1)
+        lwc1      $f16,10225($k0)
+        lwc2      $18,-841($a2)        # CHECK: lwc2 $18, -841($6)     # encoding: [0xc8,0xd2,0xfc,0xb7]
+        lwl       $s4,-4231($15)
+        lwr       $zero,-19147($gp)
+        lwu       $s3,-24086($v1)
+        lwxc1     $f12,$s1($s8)
+        madd      $s6,$13
+        madd      $zero,$9
+        madd.s    $f1,$f31,$f19,$f25
+        maddu     $s3,$gp
+        maddu     $24,$s2
+        mfc0      $a2,$14,1
+        mfc1      $a3,$f27
+        mfhc1     $s8,$f24
+        mfhi      $s3
+        mfhi      $sp
+        mflo      $s1
+        mov.d     $f20,$f14
+        mov.s     $f2,$f27
+        move      $a0,$a3
+        move      $s5,$a0
+        move      $s8,$a0
+        move      $25,$a2
+        movf      $gp,$8,$fcc7
+        movf.d    $f6,$f11,$fcc5
+        movf.s    $f23,$f5,$fcc6
+        movn      $v1,$s1,$s0
+        movn.d    $f27,$f21,$k0
+        movn.s    $f12,$f0,$s7
+        movt      $zero,$s4,$fcc5
+        movt.d    $f0,$f2,$fcc0
+        movt.s    $f30,$f2,$fcc1
+        movz      $a1,$s6,$9
+        movz.d    $f12,$f29,$9
+        movz.s    $f25,$f7,$v1
+        msub      $s7,$k1
+        msub.s    $f12,$f19,$f10,$f16
+        msubu     $15,$a1
+        mtc0      $9,$29,3
+        mtc1      $s8,$f9
+        mthc1     $zero,$f16
+        mthi      $s1
+        mtlo      $sp
+        mtlo      $25
+        mul       $s0,$s4,$at
+        mul.d     $f20,$f20,$f16
+        mul.s     $f30,$f10,$f2
+        mult      $sp,$s4
+        mult      $sp,$v0
+        multu     $gp,$k0
+        multu     $9,$s2
+        negu      $2                   # CHECK: negu $2, $2            # encoding: [0x00,0x02,0x10,0x23]
+        negu      $2,$3                # CHECK: negu $2, $3            # encoding: [0x00,0x03,0x10,0x23]
+        neg.d     $f27,$f18
+        neg.s     $f1,$f15
+        nmadd.s   $f0,$f5,$f25,$f12
+        nmsub.s   $f1,$f24,$f19,$f4
+        nop
+        nor       $a3,$zero,$a3
+        or        $12,$s0,$sp
+        or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
+        pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
+        pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
+        # FIXME: Use the code generator in order to print the .set directives
+        #        instead of the instruction printer.
+        rdhwr     $sp,$11              # CHECK:      .set  push
+                                       # CHECK-NEXT: .set  mips32r2
+                                       # CHECK-NEXT: rdhwr $sp, $11
+                                       # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
+        rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
+        rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
+        rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
+        round.l.d $f12,$f1
+        round.l.s $f25,$f5
+        round.w.d $f6,$f4
+        round.w.s $f27,$f28
+        sb        $s6,-19857($14)
+        sc        $15,18904($s3)       # CHECK: sc $15, 18904($19)     # encoding: [0xe2,0x6f,0x49,0xd8]
+        scd       $15,-8243($sp)       # CHECK: scd $15, -8243($sp)    # encoding: [0xf3,0xaf,0xdf,0xcd]
+        sdbbp                          # CHECK: sdbbp                  # encoding: [0x70,0x00,0x00,0x3f]
+        sdbbp     34                   # CHECK: sdbbp 34               # encoding: [0x70,0x00,0x08,0xbf]
+        sd        $12,5835($10)
+        sdc1      $f31,30574($13)
+        sdc2      $20,23157($s2)       # CHECK: sdc2 $20, 23157($18)   # encoding: [0xfa,0x54,0x5a,0x75]
+        sdl       $a3,-20961($s8)
+        sdr       $11,-20423($12)
+        sdxc1     $f11,$10($14)
+        seb       $25,$15
+        seh       $v1,$12
+        sh        $14,-6704($15)
+        sll       $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
+        sll       $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+        sll       $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        sllv      $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        slt       $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+        slti      $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+        sltiu     $25,$25,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+        sltu      $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+        sltu      $24,$25,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
+        sqrt.d    $f17,$f22
+        sqrt.s    $f0,$f1
+        sra       $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
+        sra       $s1,$s7,15           # CHECK: sra $17, $23, 15       # encoding: [0x00,0x17,0x8b,0xc3]
+        sra       $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srav      $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srl       $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        srlv      $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        ssnop                          # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
+        sub       $s6,$s3,$12
+        sub       $22,$17,-3126        # CHECK: addi $22, $17, 3126    # encoding: [0x22,0x36,0x0c,0x36]
+        sub       $13,6512             # CHECK: addi $13, $13, -6512   # encoding: [0x21,0xad,0xe6,0x90]
+        sub.d     $f18,$f3,$f17
+        sub.s     $f23,$f22,$f22
+        subu      $sp,$s6,$s6
+        suxc1     $f12,$k1($13)
+        sw        $ra,-10160($sp)
+        swc1      $f6,-8465($24)
+        swc2      $25,24880($s0)       # CHECK: swc2 $25, 24880($16)   # encoding: [0xea,0x19,0x61,0x30]
+        swl       $15,13694($s3)
+        swr       $s1,-26590($14)
+        swxc1     $f19,$12($k0)
+        sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
+        teq       $5,$7,620            # CHECK: teq $5, $7, 620        # encoding: [0x00,0xa7,0x9b,0x34]
+        teqi      $s5,-17504
+        tge       $7,$10               # CHECK: tge $7, $10            # encoding: [0x00,0xea,0x00,0x30]
+        tge       $5,$19,340           # CHECK: tge $5, $19, 340       # encoding: [0x00,0xb3,0x55,0x30]
+        tgei      $s1,5025
+        tgeiu     $sp,-28621
+        tgeu      $22,$28              # CHECK: tgeu $22, $gp          # encoding: [0x02,0xdc,0x00,0x31]
+        tgeu      $20,$14,379          # CHECK: tgeu $20, $14, 379     # encoding: [0x02,0x8e,0x5e,0xf1]
+        tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+        tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+        tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+        tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $15,$13              # CHECK: tlt $15, $13           # encoding: [0x01,0xed,0x00,0x32]
+        tlt       $2,$19,133           # CHECK: tlt $2, $19, 133       # encoding: [0x00,0x53,0x21,0x72]
+        tlti      $14,-21059
+        tltiu     $ra,-5076
+        tltu      $11,$16              # CHECK: tltu $11, $16          # encoding: [0x01,0x70,0x00,0x33]
+        tltu      $16,$29,1016         # CHECK: tltu $16, $sp, 1016    # encoding: [0x02,0x1d,0xfe,0x33]
+        tne       $6,$17               # CHECK: tne $6, $17            # encoding: [0x00,0xd1,0x00,0x36]
+        tne       $7,$8,885            # CHECK: tne $7, $8, 885        # encoding: [0x00,0xe8,0xdd,0x76]
+        tnei      $12,-29647
+        trunc.l.d $f23,$f23
+        trunc.l.s $f28,$f31
+        trunc.w.d $f22,$f15
+        trunc.w.s $f28,$f30
+        xor       $s2,$a0,$s8
+        xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
+        wsbh      $k1,$9
+
+1:
diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s
index 3e8fc4156262..cdcb50bb3ead 100644
--- a/test/MC/Mips/mips64r6/valid.s
+++ b/test/MC/Mips/mips64r6/valid.s
@@ -12,14 +12,14 @@
 #
 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 2> %t0 | FileCheck %s
 # RUN: FileCheck %s -check-prefix=WARNING < %t0
-
+a:
         .set noat
         # FIXME: Add the instructions carried forward from older ISA's
-        and     $2,4           # CHECK: andi $2, $2, 4        # encoding: [0x30,0x42,0x00,0x04]
         addiupc $4, 100          # CHECK: addiupc $4, 100     # encoding: [0xec,0x80,0x00,0x19]
         addu    $9,10            # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         align   $4, $2, $3, 2    # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0]
         aluipc  $3, 56           # CHECK: aluipc $3, 56       # encoding: [0xec,0x7f,0x00,0x38]
+        and     $2,4             # CHECK: andi $2, $2, 4      # encoding: [0x30,0x42,0x00,0x04]
         aui     $3,$2,-23        # CHECK: aui $3, $2, -23     # encoding: [0x3c,0x62,0xff,0xe9]
         auipc   $3, -1           # CHECK: auipc $3, -1        # encoding: [0xec,0x7e,0xff,0xff]
         bal     21100            # CHECK: bal 21100           # encoding: [0x04,0x11,0x14,0x9b]
@@ -39,23 +39,23 @@
         beqzalc $2, 1332         # CHECK: beqzalc $2, 1332    # encoding: [0x20,0x02,0x01,0x4d]
         # bnec requires rs < rt && rs != 0 but we accept when this is not true. See also bnvc
         # FIXME: Testcases are in valid-xfail.s at the moment
-        bnec $5, $6, 256         # CHECK: bnec $5, $6, 256    # encoding: [0x60,0xa6,0x00,0x40]
-        bnezalc $2, 1332         # CHECK: bnezalc $2, 1332    # encoding: [0x60,0x02,0x01,0x4d]
         beqzc $5, 72256          # CHECK: beqzc $5, 72256     # encoding: [0xd8,0xa0,0x46,0x90]
         bgec $2, $3, 256         # CHECK: bgec $2, $3, 256    # encoding: [0x58,0x43,0x00,0x40]
         bgeuc $2, $3, 256        # CHECK: bgeuc $2, $3, 256   # encoding: [0x18,0x43,0x00,0x40]
         bgezalc $2, 1332         # CHECK: bgezalc $2, 1332    # encoding: [0x18,0x42,0x01,0x4d]
-        bnezc $5, 72256          # CHECK: bnezc $5, 72256     # encoding: [0xf8,0xa0,0x46,0x90]
-        bltzc $5, 256            # CHECK: bltzc $5, 256       # encoding: [0x5c,0xa5,0x00,0x40]
         bgezc $5, 256            # CHECK: bgezc $5, 256       # encoding: [0x58,0xa5,0x00,0x40]
         bgtzalc $2, 1332         # CHECK: bgtzalc $2, 1332    # encoding: [0x1c,0x02,0x01,0x4d]
-        blezc $5, 256            # CHECK: blezc $5, 256       # encoding: [0x58,0x05,0x00,0x40]
-        bltzalc $2, 1332         # CHECK: bltzalc $2, 1332    # encoding: [0x1c,0x42,0x01,0x4d]
         bgtzc $5, 256            # CHECK: bgtzc $5, 256       # encoding: [0x5c,0x05,0x00,0x40]
         bitswap $4, $2           # CHECK: bitswap $4, $2      # encoding: [0x7c,0x02,0x20,0x20]
         blezalc $2, 1332         # CHECK: blezalc $2, 1332    # encoding: [0x18,0x02,0x01,0x4d]
+        blezc $5, 256            # CHECK: blezc $5, 256       # encoding: [0x58,0x05,0x00,0x40]
         bltc $5, $6, 256         # CHECK: bltc $5, $6, 256    # encoding: [0x5c,0xa6,0x00,0x40]
         bltuc $5, $6, 256        # CHECK: bltuc $5, $6, 256   # encoding: [0x1c,0xa6,0x00,0x40]
+        bltzalc $2, 1332         # CHECK: bltzalc $2, 1332    # encoding: [0x1c,0x42,0x01,0x4d]
+        bltzc $5, 256            # CHECK: bltzc $5, 256       # encoding: [0x5c,0xa5,0x00,0x40]
+        bnec $5, $6, 256         # CHECK: bnec $5, $6, 256    # encoding: [0x60,0xa6,0x00,0x40]
+        bnezalc $2, 1332         # CHECK: bnezalc $2, 1332    # encoding: [0x60,0x02,0x01,0x4d]
+        bnezc $5, 72256          # CHECK: bnezc $5, 72256     # encoding: [0xf8,0xa0,0x46,0x90]
         # bnvc requires that rs >= rt but we accept both. See also bnec
         bnvc     $0, $0, 4       # CHECK: bnvc $zero, $zero, 4 # encoding: [0x60,0x00,0x00,0x01]
         bnvc     $2, $0, 4       # CHECK: bnvc $2, $zero, 4    # encoding: [0x60,0x40,0x00,0x01]
@@ -65,136 +65,147 @@
         bovc     $2, $0, 4       # CHECK: bovc $2, $zero, 4    # encoding: [0x20,0x40,0x00,0x01]
         bovc     $4, $2, 4       # CHECK: bovc $4, $2, 4      # encoding: [0x20,0x82,0x00,0x01]
         cache      1, 8($5)         # CHECK: cache 1, 8($5)         # encoding: [0x7c,0xa1,0x04,0x25]
-        cmp.af.s   $f2,$f3,$f4      # CHECK: cmp.af.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x80]
+        class.d $f2, $f4         # CHECK: class.d $f2, $f4       # encoding: [0x46,0x20,0x20,0x9b]
+        class.s $f2, $f4         # CHECK: class.s $f2, $f4       # encoding: [0x46,0x00,0x20,0x9b]
+        clo     $11,$a1          # CHECK: clo $11, $5            # encoding: [0x00,0xa0,0x58,0x51]
+        clz     $sp,$gp          # CHECK: clz $sp, $gp           # encoding: [0x03,0x80,0xe8,0x50]
         cmp.af.d   $f2,$f3,$f4      # CHECK: cmp.af.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x80]
-        cmp.un.s   $f2,$f3,$f4      # CHECK: cmp.un.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x81]
-        cmp.un.d   $f2,$f3,$f4      # CHECK: cmp.un.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x81]
-        cmp.eq.s   $f2,$f3,$f4      # CHECK: cmp.eq.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x82]
+        cmp.af.s   $f2,$f3,$f4      # CHECK: cmp.af.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x80]
         cmp.eq.d   $f2,$f3,$f4      # CHECK: cmp.eq.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x82]
-        cmp.ueq.s  $f2,$f3,$f4      # CHECK: cmp.ueq.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x83]
-        cmp.ueq.d  $f2,$f3,$f4      # CHECK: cmp.ueq.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x83]
-        cmp.lt.s   $f2,$f3,$f4      # CHECK: cmp.lt.s  $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x84]
-        cmp.lt.d   $f2,$f3,$f4      # CHECK: cmp.lt.d  $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x84]
-        cmp.ult.s  $f2,$f3,$f4      # CHECK: cmp.ult.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x85]
-        cmp.ult.d  $f2,$f3,$f4      # CHECK: cmp.ult.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x85]
-        cmp.le.s   $f2,$f3,$f4      # CHECK: cmp.le.s  $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x86]
+        cmp.eq.s   $f2,$f3,$f4      # CHECK: cmp.eq.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x82]
         cmp.le.d   $f2,$f3,$f4      # CHECK: cmp.le.d  $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x86]
-        cmp.ule.s  $f2,$f3,$f4      # CHECK: cmp.ule.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x87]
-        cmp.ule.d  $f2,$f3,$f4      # CHECK: cmp.ule.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x87]
-        cmp.saf.s  $f2,$f3,$f4      # CHECK: cmp.saf.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x88]
+        cmp.le.s   $f2,$f3,$f4      # CHECK: cmp.le.s  $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x86]
+        cmp.lt.d   $f2,$f3,$f4      # CHECK: cmp.lt.d  $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x84]
+        cmp.lt.s   $f2,$f3,$f4      # CHECK: cmp.lt.s  $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x84]
         cmp.saf.d  $f2,$f3,$f4      # CHECK: cmp.saf.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x88]
-        cmp.sun.s  $f2,$f3,$f4      # CHECK: cmp.sun.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x89]
-        cmp.sun.d  $f2,$f3,$f4      # CHECK: cmp.sun.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x89]
-        cmp.seq.s  $f2,$f3,$f4      # CHECK: cmp.seq.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x8a]
+        cmp.saf.s  $f2,$f3,$f4      # CHECK: cmp.saf.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x88]
         cmp.seq.d  $f2,$f3,$f4      # CHECK: cmp.seq.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x8a]
-        cmp.sueq.s $f2,$f3,$f4      # CHECK: cmp.sueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8b]
-        cmp.sueq.d $f2,$f3,$f4      # CHECK: cmp.sueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8b]
-        cmp.slt.s  $f2,$f3,$f4      # CHECK: cmp.slt.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x8c]
-        cmp.slt.d  $f2,$f3,$f4      # CHECK: cmp.slt.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x8c]
-        cmp.sult.s $f2,$f3,$f4      # CHECK: cmp.sult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8d]
-        cmp.sult.d $f2,$f3,$f4      # CHECK: cmp.sult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8d]
-        cmp.sle.s  $f2,$f3,$f4      # CHECK: cmp.sle.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x8e]
+        cmp.seq.s  $f2,$f3,$f4      # CHECK: cmp.seq.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x8a]
         cmp.sle.d  $f2,$f3,$f4      # CHECK: cmp.sle.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x8e]
-        cmp.sule.s $f2,$f3,$f4      # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f]
+        cmp.sle.s  $f2,$f3,$f4      # CHECK: cmp.sle.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x8e]
+        cmp.slt.d  $f2,$f3,$f4      # CHECK: cmp.slt.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x8c]
+        cmp.slt.s  $f2,$f3,$f4      # CHECK: cmp.slt.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x8c]
+        cmp.sueq.d $f2,$f3,$f4      # CHECK: cmp.sueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8b]
+        cmp.sueq.s $f2,$f3,$f4      # CHECK: cmp.sueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8b]
         cmp.sule.d $f2,$f3,$f4      # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f]
-        daddu   $24,$2,18079     # CHECK: daddiu $24, $2, 18079  # encoding: [0x64,0x58,0x46,0x9f]
+        cmp.sule.s $f2,$f3,$f4      # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f]
+        cmp.sult.d $f2,$f3,$f4      # CHECK: cmp.sult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8d]
+        cmp.sult.s $f2,$f3,$f4      # CHECK: cmp.sult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8d]
+        cmp.sun.d  $f2,$f3,$f4      # CHECK: cmp.sun.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x89]
+        cmp.sun.s  $f2,$f3,$f4      # CHECK: cmp.sun.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x89]
+        cmp.ueq.d  $f2,$f3,$f4      # CHECK: cmp.ueq.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x83]
+        cmp.ueq.s  $f2,$f3,$f4      # CHECK: cmp.ueq.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x83]
+        cmp.ule.d  $f2,$f3,$f4      # CHECK: cmp.ule.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x87]
+        cmp.ule.s  $f2,$f3,$f4      # CHECK: cmp.ule.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x87]
+        cmp.ult.d  $f2,$f3,$f4      # CHECK: cmp.ult.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x85]
+        cmp.ult.s  $f2,$f3,$f4      # CHECK: cmp.ult.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x85]
+        cmp.un.d   $f2,$f3,$f4      # CHECK: cmp.un.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x81]
+        cmp.un.s   $f2,$f3,$f4      # CHECK: cmp.un.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x81]
         daddu   $19,26943        # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f]
-        dalign  $4,$2,$3,5       # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64]
-        daui    $3,$2,0x1234     # CHECK: daui $3, $2, 4660  # encoding: [0x74,0x62,0x12,0x34]
+        daddu   $24,$2,18079     # CHECK: daddiu $24, $2, 18079  # encoding: [0x64,0x58,0x46,0x9f]
         dahi     $3,0x5678       # CHECK: dahi $3, 22136     # encoding: [0x04,0x66,0x56,0x78]
+        dalign  $4,$2,$3,5       # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64]
         dati     $3,0xabcd       # CHECK: dati $3, 43981     # encoding: [0x04,0x7e,0xab,0xcd]
+        daui    $3,$2,0x1234     # CHECK: daui $3, $2, 4660  # encoding: [0x74,0x62,0x12,0x34]
         dbitswap $4, $2          # CHECK: dbitswap $4, $2    # encoding: [0x7c,0x02,0x20,0x24]
-        di      $s8              # CHECK: di  $fp          # encoding: [0x41,0x7e,0x60,0x00]
+        dclo    $s2,$a2          # CHECK: dclo $18, $6           # encoding: [0x00,0xc0,0x90,0x53]
+        dclz    $s0,$25          # CHECK: dclz $16, $25          # encoding: [0x03,0x20,0x80,0x52]
+        ddiv    $2,$3,$4         # CHECK: ddiv $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9e]
+        ddivu   $2,$3,$4         # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f]
         di                       # CHECK: di               # encoding: [0x41,0x60,0x60,0x00]
+        di      $s8              # CHECK: di  $fp          # encoding: [0x41,0x7e,0x60,0x00]
         div     $2,$3,$4         # CHECK: div $2, $3, $4   # encoding: [0x00,0x64,0x10,0x9a]
         divu    $2,$3,$4         # CHECK: divu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9b]
-        dsubu   $15,$11,5025     # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
+        dlsa    $2, $3, $4, 3    # CHECK: dlsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xd5]
+        dmod    $2,$3,$4         # CHECK: dmod $2, $3, $4  # encoding: [0x00,0x64,0x10,0xde]
+        dmodu   $2,$3,$4         # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf]
+        dmuh    $2,$3,$4         # CHECK: dmuh $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdc]
+        dmuhu   $2,$3,$4         # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdd]
+        dmul    $2,$3,$4         # CHECK: dmul $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9c]
+        dmulu   $2,$3,$4         # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9d]
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         dsubu   $14,-4586        # CHECK: daddiu $14, $14, 4586  # encoding: [0x65,0xce,0x11,0xea]
-        ei      $14              # CHECK: ei  $14          # encoding: [0x41,0x6e,0x60,0x20]
+        dsubu   $15,$11,5025     # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
         ei                       # CHECK: ei               # encoding: [0x41,0x60,0x60,0x20]
+        ei      $14              # CHECK: ei  $14          # encoding: [0x41,0x6e,0x60,0x20]
+        j       1f               # CHECK: j $tmp0                # encoding: [0b000010AA,A,A,A]
+                                 # CHECK:                        #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
+        j       a                # CHECK: j a                    # encoding: [0b000010AA,A,A,A]
+                                 # CHECK:                        #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
+        j       1328             # CHECK: j 1328                 # encoding: [0x08,0x00,0x01,0x4c]
+        jr.hb   $4               # CHECK: jr.hb $4               # encoding: [0x00,0x80,0x04,0x09]
+        jalr.hb $4               # CHECK: jalr.hb $4             # encoding: [0x00,0x80,0xfc,0x09]
+        jalr.hb $4, $5           # CHECK: jalr.hb $4, $5         # encoding: [0x00,0xa0,0x24,0x09]
         jialc   $5, 256          # CHECK: jialc $5, 256    # encoding: [0xf8,0x05,0x01,0x00]
         jic     $5, 256          # CHECK: jic $5, 256      # encoding: [0xd8,0x05,0x01,0x00]
-        mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]
-        modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]
-        ddiv    $2,$3,$4         # CHECK: ddiv $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9e]
-        ddivu   $2,$3,$4         # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f]
-        dmod    $2,$3,$4         # CHECK: dmod $2, $3, $4  # encoding: [0x00,0x64,0x10,0xde]
-        dmodu   $2,$3,$4         # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf]
-        lsa     $2, $3, $4, 3    # CHECK: lsa  $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5]
-        dlsa    $2, $3, $4, 3    # CHECK: dlsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xd5]
+        ldc2    $8, -701($at)    # CHECK: ldc2 $8, -701($1)      # encoding: [0x49,0xc8,0x0d,0x43]
         ldpc    $2,123456        # CHECK: ldpc $2, 123456  # encoding: [0xec,0x58,0x3c,0x48]
+        ll      $v0,-153($s2)    # CHECK: ll $2, -153($18)       # encoding: [0x7e,0x42,0xb3,0xb6]
+        lld     $zero,112($ra)   # CHECK: lld $zero, 112($ra)    # encoding: [0x7f,0xe0,0x38,0x37]
+        lsa     $2, $3, $4, 3    # CHECK: lsa  $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5]
+        lwc2    $18,-841($a2)    # CHECK: lwc2 $18, -841($6)     # encoding: [0x49,0x52,0x34,0xb7]
         lwpc    $2,268           # CHECK: lwpc $2, 268     # encoding: [0xec,0x48,0x00,0x43]
         lwupc   $2,268           # CHECK: lwupc $2, 268    # encoding: [0xec,0x50,0x00,0x43]
-        mul     $2,$3,$4         # CHECK: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]
-        muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]
-        mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]
-        muhu    $2,$3,$4         # CHECK: muhu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xd9]
-        dmul    $2,$3,$4         # CHECK: dmul $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9c]
-        dmuh    $2,$3,$4         # CHECK: dmuh $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdc]
-        dmulu   $2,$3,$4         # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9d]
-        dmuhu   $2,$3,$4         # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdd]
-        maddf.s $f2,$f3,$f4      # CHECK: maddf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x98]
         maddf.d $f2,$f3,$f4      # CHECK: maddf.d $f2, $f3, $f4  # encoding: [0x46,0x24,0x18,0x98]
-        msubf.s $f2,$f3,$f4      # CHECK: msubf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x99]
-        msubf.d $f2,$f3,$f4      # CHECK: msubf.d $f2, $f3, $f4  # encoding: [0x46,0x24,0x18,0x99]
-        pref    1, 8($5)         # CHECK: pref 1, 8($5)          # encoding: [0x7c,0xa1,0x04,0x35]
-        sel.d   $f0,$f1,$f2      # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
-        sel.s   $f0,$f1,$f2      # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10]
-        seleqz  $2,$3,$4         # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35]
-        selnez  $2,$3,$4         # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37]
-        max.s   $f0, $f2, $f4    # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d]
+        maddf.s $f2,$f3,$f4      # CHECK: maddf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x98]
         max.d   $f0, $f2, $f4    # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d]
-        min.s   $f0, $f2, $f4    # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c]
-        min.d   $f0, $f2, $f4    # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c]
-        maxa.s  $f0, $f2, $f4    # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f]
+        max.s   $f0, $f2, $f4    # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d]
         maxa.d  $f0, $f2, $f4    # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f]
-        mina.s  $f0, $f2, $f4    # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e]
+        maxa.s  $f0, $f2, $f4    # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f]
+        min.d   $f0, $f2, $f4    # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c]
+        min.s   $f0, $f2, $f4    # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c]
         mina.d  $f0, $f2, $f4    # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e]
+        mina.s  $f0, $f2, $f4    # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e]
+        mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]
+        modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]
+        msubf.d $f2,$f3,$f4      # CHECK: msubf.d $f2, $f3, $f4  # encoding: [0x46,0x24,0x18,0x99]
+        msubf.s $f2,$f3,$f4      # CHECK: msubf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x99]
+        muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]
+        muhu    $2,$3,$4         # CHECK: muhu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xd9]
+        mul     $2,$3,$4         # CHECK: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]
+        mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]
         or      $2, 4            # CHECK: ori $2, $2, 4          # encoding: [0x34,0x42,0x00,0x04]
-        seleqz.s $f0, $f2, $f4   # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14]
-        seleqz.d $f0, $f2, $f4   # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14]
-        selnez.s $f0, $f2, $f4   # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17]
-        selnez.d $f0, $f2, $f4   # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17]
+        pref    1, 8($5)         # CHECK: pref 1, 8($5)          # encoding: [0x7c,0xa1,0x04,0x35]
         # FIXME: Use the code generator in order to print the .set directives
         #        instead of the instruction printer.
         rdhwr   $sp,$11          # CHECK:      .set  push
                                  # CHECK-NEXT: .set  mips32r2
                                  # CHECK-NEXT: rdhwr $sp, $11
                                  # CHECK-NEXT: .set  pop         # encoding: [0x7c,0x1d,0x58,0x3b]
-        rint.s $f2, $f4          # CHECK: rint.s $f2, $f4        # encoding: [0x46,0x00,0x20,0x9a]
         rint.d $f2, $f4          # CHECK: rint.d $f2, $f4        # encoding: [0x46,0x20,0x20,0x9a]
-        class.s $f2, $f4         # CHECK: class.s $f2, $f4       # encoding: [0x46,0x00,0x20,0x9b]
-        class.d $f2, $f4         # CHECK: class.d $f2, $f4       # encoding: [0x46,0x20,0x20,0x9b]
-        jr.hb   $4               # CHECK: jr.hb $4               # encoding: [0x00,0x80,0x04,0x09]
-        jalr.hb $4               # CHECK: jalr.hb $4             # encoding: [0x00,0x80,0xfc,0x09]
-        jalr.hb $4, $5           # CHECK: jalr.hb $4, $5         # encoding: [0x00,0xa0,0x24,0x09]
-        ldc2    $8, -701($at)    # CHECK: ldc2 $8, -701($1)      # encoding: [0x49,0xc8,0x0d,0x43]
-        lwc2    $18,-841($a2)    # CHECK: lwc2 $18, -841($6)     # encoding: [0x49,0x52,0x34,0xb7]
-        sdc2    $20,629($s2)     # CHECK: sdc2 $20, 629($18)     # encoding: [0x49,0xf4,0x92,0x75]
-        swc2    $25,304($s0)     # CHECK: swc2 $25, 304($16)     # encoding: [0x49,0x79,0x81,0x30]
-        ll      $v0,-153($s2)    # CHECK: ll $2, -153($18)       # encoding: [0x7e,0x42,0xb3,0xb6]
-        lld     $zero,112($ra)   # CHECK: lld $zero, 112($ra)    # encoding: [0x7f,0xe0,0x38,0x37]
+        rint.s $f2, $f4          # CHECK: rint.s $f2, $f4        # encoding: [0x46,0x00,0x20,0x9a]
         sc      $15,-40($s3)     # CHECK: sc $15, -40($19)       # encoding: [0x7e,0x6f,0xec,0x26]
         scd     $15,-51($sp)     # CHECK: scd $15, -51($sp)      # encoding: [0x7f,0xaf,0xe6,0xa7]
-        clo     $11,$a1          # CHECK: clo $11, $5            # encoding: [0x00,0xa0,0x58,0x51]
-        clz     $sp,$gp          # CHECK: clz $sp, $gp           # encoding: [0x03,0x80,0xe8,0x50]
-        dclo    $s2,$a2          # CHECK: dclo $18, $6           # encoding: [0x00,0xc0,0x90,0x53]
-        dclz    $s0,$25          # CHECK: dclz $16, $25          # encoding: [0x03,0x20,0x80,0x52]
-        ssnop                    # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction
-        ssnop                    # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
         sdbbp                    # CHECK: sdbbp                  # encoding: [0x00,0x00,0x00,0x0e]
         sdbbp     34             # CHECK: sdbbp 34               # encoding: [0x00,0x00,0x08,0x8e]
+        sdc2    $20,629($s2)     # CHECK: sdc2 $20, 629($18)     # encoding: [0x49,0xf4,0x92,0x75]
+        sel.d   $f0,$f1,$f2      # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
+        sel.s   $f0,$f1,$f2      # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10]
+        seleqz  $2,$3,$4         # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35]
+        seleqz.d $f0, $f2, $f4   # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14]
+        seleqz.s $f0, $f2, $f4   # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14]
+        selnez  $2,$3,$4         # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37]
+        selnez.d $f0, $f2, $f4   # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17]
+        selnez.s $f0, $f2, $f4   # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17]
+        ssnop                    # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
+        ssnop                    # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction
+        swc2    $25,304($s0)     # CHECK: swc2 $25, 304($16)     # encoding: [0x49,0x79,0x81,0x30]
         sync                     # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
         sync    1                # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
         teq     $0,$3            # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
         teq     $5,$7,620        # CHECK: teq $5, $7, 620        # encoding: [0x00,0xa7,0x9b,0x34]
-        tge     $7,$10           # CHECK: tge $7, $10            # encoding: [0x00,0xea,0x00,0x30]
         tge     $5,$19,340       # CHECK: tge $5, $19, 340       # encoding: [0x00,0xb3,0x55,0x30]
-        tgeu    $22,$28          # CHECK: tgeu $22, $gp          # encoding: [0x02,0xdc,0x00,0x31]
+        tge     $7,$10           # CHECK: tge $7, $10            # encoding: [0x00,0xea,0x00,0x30]
         tgeu    $20,$14,379      # CHECK: tgeu $20, $14, 379     # encoding: [0x02,0x8e,0x5e,0xf1]
+        tgeu    $22,$28          # CHECK: tgeu $22, $gp          # encoding: [0x02,0xdc,0x00,0x31]
         tlt     $15,$13          # CHECK: tlt $15, $13           # encoding: [0x01,0xed,0x00,0x32]
         tlt     $2,$19,133       # CHECK: tlt $2, $19, 133       # encoding: [0x00,0x53,0x21,0x72]
         tltu    $11,$16          # CHECK: tltu $11, $16          # encoding: [0x01,0x70,0x00,0x33]
         tltu    $16,$29,1016     # CHECK: tltu $16, $sp, 1016    # encoding: [0x02,0x1d,0xfe,0x33]
         tne     $6,$17           # CHECK: tne $6, $17            # encoding: [0x00,0xd1,0x00,0x36]
         tne     $7,$8,885        # CHECK: tne $7, $8, 885        # encoding: [0x00,0xe8,0xdd,0x76]
+        xor     $2, 4            # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
+
+1:
diff --git a/test/MC/Mips/mips_directives.s b/test/MC/Mips/mips_directives.s
index 1a7d61f3ad4f..2ea37822f764 100644
--- a/test/MC/Mips/mips_directives.s
+++ b/test/MC/Mips/mips_directives.s
@@ -17,6 +17,7 @@ $BB0_2:
 # CHECK-NOT: nop
 # CHECK:   jal 1328             # encoding: [0x0c,0x00,0x01,0x4c]
 # CHECK-NOT: nop
+# CHECK: .set nomacro
 
     .set    noreorder
      b 1332
@@ -33,6 +34,7 @@ $JTI0_0:
 # CHECK:     .4byte    2013265916
     .set  at=$12
     .set macro
+# CHECK:   .set macro
 # CHECK:   .set reorder
 # CHECK:   b 1332               # encoding: [0x10,0x00,0x01,0x4d]
 # CHECK:   nop                  # encoding: [0x00,0x00,0x00,0x00]
diff --git a/test/MC/Mips/module-directive-bad.s b/test/MC/Mips/module-directive-bad.s
new file mode 100644
index 000000000000..74dc6d22793b
--- /dev/null
+++ b/test/MC/Mips/module-directive-bad.s
@@ -0,0 +1,262 @@
+# RUN: not llvm-mc -triple mips-unknown-unknown %s 2>%t1
+# RUN: FileCheck %s < %t1
+
+    .set mips0
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set mips1
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set mips2
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set mips3
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set mips4
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set mips5
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set mips32
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set mips32r2
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set mips32r6
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set mips64
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set mips64r2
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set mips64r6
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set arch=mips32
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set mips16
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set nomips16
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set micromips
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set nomicromips
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set msa
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set nomsa
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set dsp
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set nodsp
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set push
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set pop
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set reorder
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set noreorder
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set macro
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set nomacro
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set at
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set at=$3
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set noat
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set fp=32
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .cpload $25
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .llvm_internal_mips_reallow_module_directive
+    .module fp=32
+# CHECK-NOT: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .cpsetup $25, 8, __cerror
+    .module fp=64
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
diff --git a/test/MC/Mips/nabi-regs.s b/test/MC/Mips/nabi-regs.s
index d79df4e28463..c2658098af5a 100644
--- a/test/MC/Mips/nabi-regs.s
+++ b/test/MC/Mips/nabi-regs.s
@@ -7,10 +7,10 @@
 # RUN:   -mcpu=mips64r2 -arch=mips64 | FileCheck %s
 #
 # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding \
-# RUN:   -mcpu=mips64r2 -arch=mips64 -mattr=-n64,+n32 | FileCheck %s
+# RUN:   -mcpu=mips64r2 -arch=mips64 -target-abi n32 | FileCheck %s
 #
 # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding \
-# RUN:   -mcpu=mips64r2 -arch=mips64 -mattr=-n64,+n64 | FileCheck %s
+# RUN:   -mcpu=mips64r2 -arch=mips64 -target-abi n64 | FileCheck %s
 
     .text
 foo:
diff --git a/test/MC/Mips/nooddspreg-cmdarg.s b/test/MC/Mips/nooddspreg-cmdarg.s
index 52b040e96f12..74c9d4da1967 100644
--- a/test/MC/Mips/nooddspreg-cmdarg.s
+++ b/test/MC/Mips/nooddspreg-cmdarg.s
@@ -5,7 +5,7 @@
 # RUN:   llvm-readobj -sections -section-data -section-relocations - | \
 # RUN:     FileCheck %s -check-prefix=CHECK-OBJ
 
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -mattr=-n64,+n32,+nooddspreg 2> %t0
+# RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -target-abi n32 -mattr=+nooddspreg 2> %t0
 # RUN: FileCheck %s -check-prefix=INVALID < %t0
 #
 # RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -mattr=+nooddspreg 2> %t0
diff --git a/test/MC/Mips/nooddspreg.s b/test/MC/Mips/nooddspreg.s
index f268ef48297d..6332b7042987 100644
--- a/test/MC/Mips/nooddspreg.s
+++ b/test/MC/Mips/nooddspreg.s
@@ -5,7 +5,7 @@
 # RUN:   llvm-readobj -sections -section-data -section-relocations - | \
 # RUN:     FileCheck %s -check-prefix=CHECK-OBJ
 
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -mattr=-n64,n32 2> %t1
+# RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -target-abi n32 2> %t1
 # RUN: FileCheck %s -check-prefix=INVALID < %t1
 #
 # RUN: not llvm-mc %s -arch=mips -mcpu=mips64 2> %t2
diff --git a/test/MC/Mips/octeon-instructions.s b/test/MC/Mips/octeon-instructions.s
index 2922744c9076..34830c0fc6eb 100644
--- a/test/MC/Mips/octeon-instructions.s
+++ b/test/MC/Mips/octeon-instructions.s
@@ -3,10 +3,18 @@
 # CHECK: baddu $9, $6, $7             # encoding: [0x70,0xc7,0x48,0x28]
 # CHECK: baddu $17, $18, $19          # encoding: [0x72,0x53,0x88,0x28]
 # CHECK: baddu $2, $2, $3             # encoding: [0x70,0x43,0x10,0x28]
+# CHECK: bbit0 $19, 22, foo           # encoding: [0xca,0x76,A,A]
+# CHECK: bbit032 $fp, 11, foo         # encoding: [0xdb,0xcb,A,A]
+# CHECK: bbit032 $8, 10, foo          # encoding: [0xd9,0x0a,A,A]
+# CHECK: bbit1 $3, 31, foo            # encoding: [0xe8,0x7f,A,A]
+# CHECK: bbit132 $24, 10, foo         # encoding: [0xfb,0x0a,A,A]
+# CHECK: bbit132 $14, 14, foo         # encoding: [0xf9,0xce,A,A]
 # CHECK: cins  $25, $10, 22, 2        # encoding: [0x71,0x59,0x15,0xb2]
 # CHECK: cins  $9, $9, 17, 29         # encoding: [0x71,0x29,0xec,0x72]
 # CHECK: cins32 $15, $2, 18, 8        # encoding: [0x70,0x4f,0x44,0xb3]
 # CHECK: cins32 $22, $22, 9, 22       # encoding: [0x72,0xd6,0xb2,0x73]
+# CHECK: cins32 $24, $ra, 0, 31       # encoding: [0x73,0xf8,0xf8,0x33]
+# CHECK: cins32 $15, $15, 5, 5        # encoding: [0x71,0xef,0x29,0x73]
 # CHECK: dmul  $9, $6, $7             # encoding: [0x70,0xc7,0x48,0x03]
 # CHECK: dmul  $19, $24, $25          # encoding: [0x73,0x19,0x98,0x03]
 # CHECK: dmul  $9, $9, $6             # encoding: [0x71,0x26,0x48,0x03]
@@ -18,6 +26,8 @@
 # CHECK: exts  $15, $15, 17, 6        # encoding: [0x71,0xef,0x34,0x7a]
 # CHECK: exts32 $4, $13, 10, 8        # encoding: [0x71,0xa4,0x42,0xbb]
 # CHECK: exts32 $15, $15, 11, 20      # encoding: [0x71,0xef,0xa2,0xfb]
+# CHECK: exts32 $7, $4, 22, 9         # encoding: [0x70,0x87,0x4d,0xbb]
+# CHECK: exts32 $25, $25, 5, 25       # encoding: [0x73,0x39,0xc9,0x7b]
 # CHECK: mtm0  $15                    # encoding: [0x71,0xe0,0x00,0x08]
 # CHECK: mtm1  $16                    # encoding: [0x72,0x00,0x00,0x0c]
 # CHECK: mtm2  $17                    # encoding: [0x72,0x20,0x00,0x0d]
@@ -46,13 +56,22 @@
 # CHECK: vmulu $sp, $10, $17          # encoding: [0x71,0x51,0xe8,0x0f]
 # CHECK: vmulu $27, $27, $6           # encoding: [0x73,0x66,0xd8,0x0f]
 
+foo:
   baddu $9, $6, $7
   baddu $17, $18, $19
   baddu $2, $3
+  bbit0 $19, 22, foo
+  bbit032 $30, 11, foo
+  bbit0 $8, 42, foo
+  bbit1 $3, 31, foo
+  bbit132 $24, 10, foo
+  bbit1 $14, 46, foo
   cins  $25, $10, 22, 2
   cins  $9, 17, 29
   cins32 $15, $2, 18, 8
   cins32 $22, 9, 22
+  cins  $24, $31, 32, 31
+  cins  $15, 37, 5
   dmul  $9, $6, $7
   dmul  $19, $24, $25
   dmul  $9, $6
@@ -64,6 +83,8 @@
   exts  $15, 17, 6
   exts32 $4, $13, 10, 8
   exts32 $15, 11, 20
+  exts  $7, $4, 54, 9
+  exts  $25, 37, 25
   mtm0  $15
   mtm1  $16
   mtm2  $17
diff --git a/test/MC/Mips/oddspreg.s b/test/MC/Mips/oddspreg.s
index 32ba9e0a3f93..a3902f621e44 100644
--- a/test/MC/Mips/oddspreg.s
+++ b/test/MC/Mips/oddspreg.s
@@ -5,10 +5,10 @@
 # RUN:   llvm-readobj -sections -section-data -section-relocations - | \
 # RUN:     FileCheck %s -check-prefix=CHECK-OBJ-ALL -check-prefix=CHECK-OBJ-O32
 #
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -mattr=-n64,+n32 | \
+# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 | \
 # RUN:   FileCheck %s -check-prefix=CHECK-ASM
 #
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -mattr=-n64,+n32 -filetype=obj -o - | \
+# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 -filetype=obj -o - | \
 # RUN:   llvm-readobj -sections -section-data -section-relocations - | \
 # RUN:     FileCheck %s -check-prefix=CHECK-OBJ-ALL -check-prefix=CHECK-OBJ-N32
 
@@ -25,7 +25,7 @@
 # RUN:   llvm-readobj -sections -section-data -section-relocations - | \
 # RUN:     FileCheck %s -check-prefix=CHECK-OBJ-ALL -check-prefix=CHECK-OBJ-O32
 #
-# RUN: llvm-mc /dev/null -arch=mips64 -mcpu=mips64 -mattr=-n64,+n32 -filetype=obj -o - | \
+# RUN: llvm-mc /dev/null -arch=mips64 -mcpu=mips64 -target-abi n32 -filetype=obj -o - | \
 # RUN:   llvm-readobj -sections -section-data -section-relocations - | \
 # RUN:     FileCheck %s -check-prefix=CHECK-OBJ-ALL -check-prefix=CHECK-OBJ-N32
 
diff --git a/test/MC/Mips/set-arch.s b/test/MC/Mips/set-arch.s
index 626746836add..834718c5d55c 100644
--- a/test/MC/Mips/set-arch.s
+++ b/test/MC/Mips/set-arch.s
@@ -16,12 +16,24 @@
     clo         $2, $2
     .set arch=mips32r2
     rotr        $2, $2, 15
+    .set arch=mips32
+    .set arch=mips32r3
+    rotr        $2, $2, 15
+    .set arch=mips32
+    .set arch=mips32r5
+    rotr        $2, $2, 15
     .set arch=mips32r6
     mod         $2, $4, $6
     .set arch=mips64
     daddi       $2, $2, 10
     .set arch=mips64r2
     drotr32     $1, $14, 15
+    .set arch=mips64
+    .set arch=mips64r3
+    drotr32     $1, $14, 15
+    .set arch=mips64
+    .set arch=mips64r5
+    drotr32     $1, $14, 15
     .set arch=mips64r6
     mod         $2, $4, $6
     .set arch=cnmips
diff --git a/test/MC/Mips/set-at-directive-explicit-at.s b/test/MC/Mips/set-at-directive-explicit-at.s
index 797a2b782c37..d2d1c1d4627b 100644
--- a/test/MC/Mips/set-at-directive-explicit-at.s
+++ b/test/MC/Mips/set-at-directive-explicit-at.s
@@ -1,23 +1,35 @@
 # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 \
 # RUN:     2>%t1 | FileCheck %s
 # RUN: FileCheck -check-prefix=WARNINGS %s < %t1
-# Check that the assembler can handle the documented syntax
-# for ".set at" and set the correct value. The correct value for $at is always
-# $1 when written by the user.
+
+# Check that the assembler can handle the documented syntax for ".set at" and
+# will set the correct value for $at.
+# Note that writing $at is always the same as writing $1.
+
     .text
 foo:
 # CHECK:   jr    $1                      # encoding: [0x08,0x00,0x20,0x00]
-# WARNINGS: :[[@LINE+2]]:11: warning: used $at without ".set noat"
+# WARNINGS: :[[@LINE+2]]:11: warning: used $at (currently $1) without ".set noat"
     .set    at=$1
     jr    $at
 
 # CHECK:   jr    $1                      # encoding: [0x08,0x00,0x20,0x00]
-# WARNINGS: :[[@LINE+2]]:11: warning: used $at without ".set noat"
+# WARNINGS: :[[@LINE+2]]:11: warning: used $at (currently $1) without ".set noat"
     .set    at=$1
     jr    $1
-# WARNINGS-NOT: warning: used $at without ".set noat"
 
 # CHECK:   jr    $1                      # encoding: [0x08,0x00,0x20,0x00]
+# WARNINGS: :[[@LINE+2]]:11: warning: used $at (currently $1) without ".set noat"
+    .set    at=$at
+    jr    $at
+
+# CHECK:   jr    $1                      # encoding: [0x08,0x00,0x20,0x00]
+# WARNINGS: :[[@LINE+2]]:11: warning: used $at (currently $1) without ".set noat"
+    .set    at=$at
+    jr    $1
+
+# WARNINGS-NOT: warning: used $at (currently ${{[0-9]+}}) without ".set noat"
+# CHECK:   jr    $1                      # encoding: [0x08,0x00,0x20,0x00]
     .set    at=$2
     jr    $at
 # CHECK:   jr    $1                      # encoding: [0x08,0x00,0x20,0x00]
@@ -31,12 +43,11 @@ foo:
     jr    $at
 
 # CHECK:   jr    $16                     # encoding: [0x08,0x00,0x00,0x02]
-# WARNINGS: :[[@LINE+2]]:11: warning: used $16 with ".set at=$16"
+# WARNINGS: :[[@LINE+2]]:11: warning: used $at (currently $16) without ".set noat"
     .set    at=$16
     jr    $s0
 
 # CHECK:   jr    $16                     # encoding: [0x08,0x00,0x00,0x02]
-# WARNINGS: :[[@LINE+2]]:11: warning: used $16 with ".set at=$16"
+# WARNINGS: :[[@LINE+2]]:11: warning: used $at (currently $16) without ".set noat"
     .set    at=$16
     jr    $16
-# WARNINGS-NOT: warning
diff --git a/test/MC/Mips/set-at-directive.s b/test/MC/Mips/set-at-directive.s
index 7e93f765ac79..1bfc4738d58a 100644
--- a/test/MC/Mips/set-at-directive.s
+++ b/test/MC/Mips/set-at-directive.s
@@ -4,156 +4,187 @@
 # for ".set at" and set the correct value.
     .text
 foo:
+# CHECK: .set at=$1
 # CHECK: lui  $1, 1
 # CHECK: addu $1, $1, $2
 # CHECK: lw   $2, 0($1)
     .set    at=$1
         lw      $2, 65536($2)
+# CHECK: .set at=$2
 # CHECK: lui  $2, 1
 # CHECK: addu $2, $2, $1
 # CHECK: lw   $1, 0($2)
     .set    at=$2
         lw      $1, 65536($1)
+# CHECK: .set at=$3
 # CHECK: lui  $3, 1
 # CHECK: addu $3, $3, $1
 # CHECK: lw   $1, 0($3)
     .set    at=$3
         lw      $1, 65536($1)
+# CHECK: .set at=$4
 # CHECK: lui  $4, 1
 # CHECK: addu $4, $4, $1
 # CHECK: lw   $1, 0($4)
     .set    at=$a0
         lw      $1, 65536($1)
+# CHECK: .set at=$5
 # CHECK: lui  $5, 1
 # CHECK: addu $5, $5, $1
 # CHECK: lw   $1, 0($5)
     .set    at=$a1
         lw      $1, 65536($1)
+# CHECK: .set at=$6
 # CHECK: lui  $6, 1
 # CHECK: addu $6, $6, $1
 # CHECK: lw   $1, 0($6)
     .set    at=$a2
         lw      $1, 65536($1)
+# CHECK: .set at=$7
 # CHECK: lui  $7, 1
 # CHECK: addu $7, $7, $1
 # CHECK: lw   $1, 0($7)
     .set    at=$a3
         lw      $1, 65536($1)
+# CHECK: .set at=$8
 # CHECK: lui  $8, 1
 # CHECK: addu $8, $8, $1
 # CHECK: lw   $1, 0($8)
     .set    at=$8
         lw      $1, 65536($1)
+# CHECK: .set at=$9
 # CHECK: lui  $9, 1
 # CHECK: addu $9, $9, $1
 # CHECK: lw   $1, 0($9)
     .set    at=$9
         lw      $1, 65536($1)
+# CHECK: .set at=$10
 # CHECK: lui  $10, 1
 # CHECK: addu $10, $10, $1
 # CHECK: lw   $1, 0($10)
     .set    at=$10
         lw      $1, 65536($1)
+# CHECK: .set at=$11
 # CHECK: lui  $11, 1
 # CHECK: addu $11, $11, $1
 # CHECK: lw   $1, 0($11)
     .set    at=$11
         lw      $1, 65536($1)
+# CHECK: .set at=$12
 # CHECK: lui  $12, 1
 # CHECK: addu $12, $12, $1
 # CHECK: lw   $1, 0($12)
     .set    at=$12
         lw      $1, 65536($1)
+# CHECK: .set at=$13
 # CHECK: lui  $13, 1
 # CHECK: addu $13, $13, $1
 # CHECK: lw   $1, 0($13)
     .set    at=$13
         lw      $1, 65536($1)
+# CHECK: .set at=$14
 # CHECK: lui  $14, 1
 # CHECK: addu $14, $14, $1
 # CHECK: lw   $1, 0($14)
     .set    at=$14
         lw      $1, 65536($1)
+# CHECK: .set at=$15
 # CHECK: lui  $15, 1
 # CHECK: addu $15, $15, $1
 # CHECK: lw   $1, 0($15)
     .set    at=$15
         lw      $1, 65536($1)
+# CHECK: .set at=$16
 # CHECK: lui  $16, 1
 # CHECK: addu $16, $16, $1
 # CHECK: lw   $1, 0($16)
     .set    at=$s0
         lw      $1, 65536($1)
+# CHECK: .set at=$17
 # CHECK: lui  $17, 1
 # CHECK: addu $17, $17, $1
 # CHECK: lw   $1, 0($17)
     .set    at=$s1
         lw      $1, 65536($1)
+# CHECK: .set at=$18
 # CHECK: lui  $18, 1
 # CHECK: addu $18, $18, $1
 # CHECK: lw   $1, 0($18)
     .set    at=$s2
         lw      $1, 65536($1)
+# CHECK: .set at=$19
 # CHECK: lui  $19, 1
 # CHECK: addu $19, $19, $1
 # CHECK: lw   $1, 0($19)
     .set    at=$s3
         lw      $1, 65536($1)
+# CHECK: .set at=$20
 # CHECK: lui  $20, 1
 # CHECK: addu $20, $20, $1
 # CHECK: lw   $1, 0($20)
     .set    at=$s4
         lw      $1, 65536($1)
+# CHECK: .set at=$21
 # CHECK: lui  $21, 1
 # CHECK: addu $21, $21, $1
 # CHECK: lw   $1, 0($21)
     .set    at=$s5
         lw      $1, 65536($1)
+# CHECK: .set at=$22
 # CHECK: lui  $22, 1
 # CHECK: addu $22, $22, $1
 # CHECK: lw   $1, 0($22)
     .set    at=$s6
         lw      $1, 65536($1)
+# CHECK: .set at=$23
 # CHECK: lui  $23, 1
 # CHECK: addu $23, $23, $1
 # CHECK: lw   $1, 0($23)
     .set    at=$s7
         lw      $1, 65536($1)
+# CHECK: .set at=$24
 # CHECK: lui  $24, 1
 # CHECK: addu $24, $24, $1
 # CHECK: lw   $1, 0($24)
     .set    at=$24
         lw      $1, 65536($1)
+# CHECK: .set at=$25
 # CHECK: lui  $25, 1
 # CHECK: addu $25, $25, $1
 # CHECK: lw   $1, 0($25)
     .set    at=$25
         lw      $1, 65536($1)
+# CHECK: .set at=$26
 # CHECK: lui  $26, 1
 # CHECK: addu $26, $26, $1
 # CHECK: lw   $1, 0($26)
     .set    at=$26
         lw      $1, 65536($1)
+# CHECK: .set at=$27
 # CHECK: lui  $27, 1
 # CHECK: addu $27, $27, $1
 # CHECK: lw   $1, 0($27)
     .set    at=$27
         lw      $1, 65536($1)
+# CHECK: .set at=$28
 # CHECK: lui  $gp, 1
 # CHECK: addu $gp, $gp, $1
 # CHECK: lw   $1, 0($gp)
     .set    at=$gp
         lw      $1, 65536($1)
+# CHECK: .set at=$30
 # CHECK: lui  $fp, 1
 # CHECK: addu $fp, $fp, $1
 # CHECK: lw   $1, 0($fp)
     .set    at=$fp
         lw      $1, 65536($1)
+# CHECK: .set at=$29
 # CHECK: lui  $sp, 1
 # CHECK: addu $sp, $sp, $1
 # CHECK: lw   $1, 0($sp)
     .set    at=$sp
         lw      $1, 65536($1)
+# CHECK: .set at=$31
 # CHECK: lui  $ra, 1
 # CHECK: addu $ra, $ra, $1
 # CHECK: lw   $1, 0($ra)
diff --git a/test/MC/Mips/set-at-noat-bad-syntax.s b/test/MC/Mips/set-at-noat-bad-syntax.s
new file mode 100644
index 000000000000..47f5be74f9ad
--- /dev/null
+++ b/test/MC/Mips/set-at-noat-bad-syntax.s
@@ -0,0 +1,29 @@
+# RUN: not llvm-mc %s -triple=mips-unknown-unknown -mcpu=mips32 2>%t1
+# RUN: FileCheck %s < %t1
+
+.set at~
+# CHECK: error: unexpected token, expected equals sign
+
+.set at=
+# CHECK: error: no register specified
+
+.set at=~
+# CHECK: error: unexpected token, expected dollar sign '$'
+
+.set at=$
+# CHECK: error: unexpected token, expected identifier or integer
+
+.set at=$-4
+# CHECK: error: unexpected token, expected identifier or integer
+
+.set at=$1000
+# CHECK: error: invalid register
+
+.set at=$foo
+# CHECK: error: invalid register
+
+.set at=$2bar
+# CHECK: error: unexpected token, expected end of statement
+
+.set noat bar
+# CHECK: error: unexpected token, expected end of statement
diff --git a/test/MC/Mips/set-defined-symbol.s b/test/MC/Mips/set-defined-symbol.s
new file mode 100644
index 000000000000..54db45da27b9
--- /dev/null
+++ b/test/MC/Mips/set-defined-symbol.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
+# RUN:   llvm-objdump -d -r -arch=mips - | FileCheck %s
+
+  .global foo
+  .weak bar
+  .set bar, b
+  .set foo, b
+  .set foo, a
+a:
+  nop
+# CHECK-NOT: a:
+# CHECK: foo:
+
+b:
+  nop
+# CHECK-NOT: b:
+# CHECK-NOT: foo:
+# CHECK: bar:
diff --git a/test/MC/Mips/set-mips-directives-bad.s b/test/MC/Mips/set-mips-directives-bad.s
index 672698756599..68a0da856b28 100644
--- a/test/MC/Mips/set-mips-directives-bad.s
+++ b/test/MC/Mips/set-mips-directives-bad.s
@@ -21,10 +21,22 @@
         rotr    $2,15 # CHECK: error: instruction requires a CPU feature not currently enabled
         .set mips32r2
         mod $2, $4, $6 # CHECK: error:instruction requires a CPU feature not currently enabled
+        .set mips64r3
+        .set mips32r3
+        daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled
+        .set mips64r3
+        .set mips32r5
+        daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled
         .set mips32r6
         daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled
         .set mips64
         drotr32 $1,$14,15 # CHECK: error: instruction requires a CPU feature not currently enabled
         .set mips64r2
         mod $2, $4, $6 # CHECK: error: instruction requires a CPU feature not currently enabled
+        .set mips64r6
+        .set mips64r3
+        mod $2, $4, $6 # CHECK: error: instruction requires a CPU feature not currently enabled
+        .set mips64r6
+        .set mips64r5
+        mod $2, $4, $6 # CHECK: error: instruction requires a CPU feature not currently enabled
 
diff --git a/test/MC/Mips/set-mips-directives.s b/test/MC/Mips/set-mips-directives.s
index 96c23088676e..5225968aadd0 100644
--- a/test/MC/Mips/set-mips-directives.s
+++ b/test/MC/Mips/set-mips-directives.s
@@ -17,12 +17,24 @@
         clo  $2,$2
         .set mips32r2
         rotr    $2,15
+        .set mips32
+        .set mips32r3
+        rotr    $2,15
+        .set mips32
+        .set mips32r5
+        rotr    $2,15
         .set mips32r6
         mod $2, $4, $6
         .set mips64
         daddi $2, $2, 10
         .set mips64r2
         drotr32 $1,$14,15
+        .set mips64
+        .set mips64r3
+        drotr32 $1,$14,15
+        .set mips64
+        .set mips64r5
+        drotr32 $1,$14,15
         .set mips64r6
         mod $2, $4, $6
 
@@ -41,11 +53,23 @@
 # CHECK: clo $2, $2
 # CHECK: .set mips32r2
 # CHECK: rotr $2, $2, 15
+# CHECK: .set mips32
+# CHECK: .set mips32r3
+# CHECK: rotr $2, $2, 15
+# CHECK: .set mips32
+# CHECK: .set mips32r5
+# CHECK: rotr $2, $2, 15
 # CHECK: .set mips32r6
 # CHECK: mod $2, $4, $6
 # CHECK: .set mips64
 # CHECK: daddi $2, $2, 10
 # CHECK: .set mips64r2
 # CHECK:  drotr32 $1, $14, 15
+# CHECK: .set mips64
+# CHECK: .set mips64r3
+# CHECK:  drotr32 $1, $14, 15
+# CHECK: .set mips64
+# CHECK: .set mips64r5
+# CHECK:  drotr32 $1, $14, 15
 # CHECK: .set mips64r6
 # CHECK: mod $2, $4, $6
diff --git a/test/MC/Mips/set-nomacro-micromips.s b/test/MC/Mips/set-nomacro-micromips.s
new file mode 100644
index 000000000000..c4d8b7c2d3e5
--- /dev/null
+++ b/test/MC/Mips/set-nomacro-micromips.s
@@ -0,0 +1,33 @@
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=micromips 2>&1 | FileCheck %s
+
+  .text
+  .type main, @function
+  .set micromips
+main:
+# CHECK-NOT: warning: macro instruction expanded into multiple instructions
+  .set macro
+  b 132
+  b 1332
+  b bar
+
+  lwm $16, $17, 8($sp)
+  swm $16, $17, 8($sp)
+
+  add $4, $5, $6
+
+  .set noreorder
+  .set nomacro
+  b 132
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  b 1332
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  b bar
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  lwm $16, $17, 8($sp)
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  swm $16, $17, 8($sp)
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  add $4, $5, $6
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
diff --git a/test/MC/Mips/set-nomacro.s b/test/MC/Mips/set-nomacro.s
new file mode 100644
index 000000000000..d81048ff12e1
--- /dev/null
+++ b/test/MC/Mips/set-nomacro.s
@@ -0,0 +1,46 @@
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 2>&1 | FileCheck %s
+
+# CHECK-NOT: warning: macro instruction expanded into multiple instructions
+  .set macro
+  li  $8, -16
+  li  $8, 16
+  li  $8, 161616
+
+  la  $8, 16
+  la  $8, 161616
+  la  $8, 16($9)
+  la  $8, 161616($9)
+  la  $8, symbol
+
+  jal $25
+  jal $4, $25
+
+  add $4, $5, $6
+
+  .set noreorder
+  .set nomacro
+  li  $8, -16
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  li  $8, 16
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  li  $8, 161616
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  la  $8, 16
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  la  $8, 161616
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  la  $8, 16($9)
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  la  $8, 161616($9)
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  la  $8, symbol
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  jal $25
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  jal $4, $25
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  add $4, $5, $6
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
diff --git a/test/MC/Mips/sort-relocation-table.s b/test/MC/Mips/sort-relocation-table.s
new file mode 100644
index 000000000000..590f8fddf480
--- /dev/null
+++ b/test/MC/Mips/sort-relocation-table.s
@@ -0,0 +1,125 @@
+# RUN: llvm-mc -filetype=obj -arch mipsel %s | llvm-readobj -r | FileCheck %s
+
+# Test the order of records in the relocation table.
+# *HI16 and local *GOT16 relocations should be immediately followed by the
+# corresponding *LO16 relocation against the same symbol.
+#
+# We try to implement the same semantics as gas, ie. to order the relocation
+# table the same way as gas.
+#
+# gnu as command line:
+# mips-linux-gnu-as -EL sort-relocation-table.s -o sort-relocation-table.o
+#
+# TODO: Add mips16 and micromips tests.
+# Note: offsets are part of expected output, so it's simpler to add new test
+#       cases at the bottom of the file.
+
+# CHECK:       Relocations [
+# CHECK-NEXT:  {
+
+# Put HI before LO.
+addiu $2,$2,%lo(sym1)
+lui $2,%hi(sym1)
+
+# CHECK-NEXT:    0x4 R_MIPS_HI16 sym1
+# CHECK-NEXT:    0x0 R_MIPS_LO16 sym1
+
+# When searching for a matching LO, ignore LOs against a different symbol.
+addiu $2,$2,%lo(sym2)
+lui $2,%hi(sym2)
+addiu $2,$2,%lo(sym2_d)
+
+# CHECK-NEXT:    0xC R_MIPS_HI16 sym2
+# CHECK-NEXT:    0x8 R_MIPS_LO16 sym2
+# CHECK-NEXT:    0x10 R_MIPS_LO16 sym2_d
+
+# Match HI with 2nd LO because it has higher offset (than the 1st LO).
+addiu $2,$2,%lo(sym3)
+addiu $2,$2,%lo(sym3)
+lui $2,%hi(sym3)
+
+# CHECK-NEXT:    0x14 R_MIPS_LO16 sym3
+# CHECK-NEXT:    0x1C R_MIPS_HI16 sym3
+# CHECK-NEXT:    0x18 R_MIPS_LO16 sym3
+
+# HI is already followed by a matching LO, so don't look further, ie. ignore the
+# "free" LO with higher offset.
+lui $2,%hi(sym4)
+addiu $2,$2,%lo(sym4)
+addiu $2,$2,%lo(sym4)
+
+# CHECK-NEXT:    0x20 R_MIPS_HI16 sym4
+# CHECK-NEXT:    0x24 R_MIPS_LO16 sym4
+# CHECK-NEXT:    0x28 R_MIPS_LO16 sym4
+
+# Match 2nd HI with 2nd LO, since it's the one with highest offset among the
+# "free" ones.
+addiu $2,$2,%lo(sym5)
+addiu $2,$2,%lo(sym5)
+lui $2,%hi(sym5)
+addiu $2,$2,%lo(sym5)
+lui $2,%hi(sym5)
+
+# CHECK-NEXT:    0x2C R_MIPS_LO16 sym5
+# CHECK-NEXT:    0x3C R_MIPS_HI16 sym5
+# CHECK-NEXT:    0x30 R_MIPS_LO16 sym5
+# CHECK-NEXT:    0x34 R_MIPS_HI16 sym5
+# CHECK-NEXT:    0x38 R_MIPS_LO16 sym5
+
+# When more HIs are matched with one LO, sort them in descending order of
+# offset.
+addiu $2,$2,%lo(sym6)
+lui $2,%hi(sym6)
+lui $2,%hi(sym6)
+
+# CHECK-NEXT:    0x48 R_MIPS_HI16 sym6
+# CHECK-NEXT:    0x44 R_MIPS_HI16 sym6
+# CHECK-NEXT:    0x40 R_MIPS_LO16 sym6
+
+#  sym7 is a local symbol, so GOT relocation against it needs a matching LO.
+sym7:
+addiu $2,$2,%lo(sym7)
+lui $2,%got(sym7)
+
+# CHECK-NEXT:    0x50 R_MIPS_GOT16 sym7
+# CHECK-NEXT:    0x4C R_MIPS_LO16 sym7
+
+# sym8 is not a local symbol, don't look for a matching LO for GOT.
+.global sym8
+addiu $2,$2,%lo(sym8)
+lui $2,%got(sym8)
+
+# CHECK-NEXT:    0x54 R_MIPS_LO16 sym8
+# CHECK-NEXT:    0x58 R_MIPS_GOT16 sym8
+
+# A small combination of previous checks.
+symc1:
+addiu $2,$2,%lo(symc1)
+addiu $2,$2,%lo(symc1)
+addiu $2,$2,%lo(symc1)
+lui $2,%hi(symc1)
+lui $2,%got(symc1)
+addiu $2,$2,%lo(symc2)
+lui $2,%hi(symc1)
+lui $2,%hi(symc1)
+lui $2,%got(symc2)
+lui $2,%hi(symc1)
+addiu $2,$2,%lo(symc1)
+addiu $2,$2,%lo(symc2)
+lui $2,%hi(symc1)
+lui $2,%hi(symc1)
+
+# CHECK-NEXT:    0x78 R_MIPS_HI16 symc1
+# CHECK-NEXT:    0x74 R_MIPS_HI16 symc1
+# CHECK-NEXT:    0x6C R_MIPS_GOT16 symc1
+# CHECK-NEXT:    0x68 R_MIPS_HI16 symc1
+# CHECK-NEXT:    0x5C R_MIPS_LO16 symc1
+# CHECK-NEXT:    0x8C R_MIPS_HI16 symc1
+# CHECK-NEXT:    0x60 R_MIPS_LO16 symc1
+# CHECK-NEXT:    0x90 R_MIPS_HI16 symc1
+# CHECK-NEXT:    0x64 R_MIPS_LO16 symc1
+# CHECK-NEXT:    0x70 R_MIPS_LO16 symc2
+# CHECK-NEXT:    0x7C R_MIPS_GOT16 symc2
+# CHECK-NEXT:    0x80 R_MIPS_HI16 symc1
+# CHECK-NEXT:    0x84 R_MIPS_LO16 symc1
+# CHECK-NEXT:    0x88 R_MIPS_LO16 symc2
diff --git a/test/MC/Mips/sym-offset.ll b/test/MC/Mips/sym-offset.ll
index c7450f74ae41..55adc22d971c 100644
--- a/test/MC/Mips/sym-offset.ll
+++ b/test/MC/Mips/sym-offset.ll
@@ -17,7 +17,7 @@ entry:
 ; CHECK:            0000: 00001C3C 00009C27 21E09903 0000828F
 ; CHECK-NEXT:       0010: 0E004188 0B004198
 
-  %call = tail call i32 @memcmp(i8* getelementptr inbounds ([11 x i8]* @string1, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @string2, i32 0, i32 0), i32 4) nounwind readonly
+  %call = tail call i32 @memcmp(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @string1, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8], [10 x i8]* @string2, i32 0, i32 0), i32 4) nounwind readonly
   %cmp = icmp eq i32 %call, 0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
diff --git a/test/MC/Mips/target-soft-float.s b/test/MC/Mips/target-soft-float.s
new file mode 100644
index 000000000000..5865d5ab1269
--- /dev/null
+++ b/test/MC/Mips/target-soft-float.s
@@ -0,0 +1,331 @@
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32 -mattr=+soft-float 2>&1 |\
+# RUN:   FileCheck %s --check-prefix=32
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips64 -mattr=+soft-float 2>&1 |\
+# RUN:   FileCheck %s --check-prefix=64
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+soft-float 2>&1 |\
+# RUN:   FileCheck %s --check-prefix=R2
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=+soft-float 2>&1 |\
+# RUN:   FileCheck %s --check-prefix=R6
+
+foo:
+  dmfc1      $7, $f2
+  # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  dmtc1      $6, $f2
+  # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+
+  ceil.l.d   $f2, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  ceil.l.s   $f2, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cvt.d.l    $f2, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cvt.l.d    $f2, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cvt.l.s    $f2, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cvt.s.l    $f2, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  floor.l.d  $f2, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  floor.l.s  $f2, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  ldxc1      $f2, $4($6)
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  luxc1      $f2, $4($6)
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  lwxc1      $f2, $4($6)
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  mfhc1      $7, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  msub.s     $f2, $f2, $f2, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  mthc1      $7, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  nmadd.s    $f2, $f2, $f2, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  nmsub.s    $f2, $f2, $f2, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  round.l.s  $f2, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  sdxc1      $f2, $4($6)
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  suxc1      $f2, $4($6)
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  swxc1      $f2, $4($6)
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  trunc.l.d  $f2, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  trunc.l.s  $f2, $f2
+  # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+
+  bc1eqz     $f2, 123
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  bc1nez     $f2, 456
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  class.d    $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  class.s    $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.af.d   $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.af.s   $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.eq.d   $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.eq.s   $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.le.d   $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.le.s   $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.lt.d   $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.lt.s   $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.saf.d  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.saf.s  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.seq.d  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.seq.s  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.sle.d  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.sle.s  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.slt.d  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.slt.s  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.sueq.d $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.sueq.s $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.sule.d $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.sule.s $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.sult.d $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.sult.s $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.sun.d  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.sun.s  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.ueq.d  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.ueq.s  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.ule.d  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.ule.s  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.ult.d  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.ult.s  $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.un.d   $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cmp.un.s   $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  maddf.d    $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  maddf.s    $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  max.d      $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  max.s      $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  maxa.d     $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  maxa.s     $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  min.d      $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  min.s      $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  mina.d     $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  mina.s     $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  msubf.d    $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  msubf.s    $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  rint.d     $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  rint.s     $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  sel.d      $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  sel.s      $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  seleqz.d   $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  seleqz.s   $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  selnez.d   $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  selnez.s   $f2, $f2, $f2
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+
+  abs.d      $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  abs.s      $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  add.d      $f2, $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  add.s      $f2, $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.eq.d     $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.eq.s     $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.f.d      $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.f.s      $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.le.d     $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.le.s     $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.lt.d     $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.lt.s     $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.nge.d    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.nge.s    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.ngl.d    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.ngl.s    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.ngle.d   $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.ngle.s   $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.ngt.d    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.ngt.s    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.ole.d    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.ole.s    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.olt.d    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.olt.s    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.seq.d    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.seq.s    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.sf.d     $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.sf.s     $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.ueq.d    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.ueq.s    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.ule.d    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.ule.s    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.ult.d    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.ult.s    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.un.d     $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  c.un.s     $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  ceil.w.d   $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  ceil.w.s   $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cvt.d.s    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cvt.d.w    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cvt.s.d    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cvt.s.w    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cvt.w.d    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  cvt.w.s    $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  div.d      $f2, $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  div.s      $f2, $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  floor.w.d  $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  floor.w.s  $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  ldc1       $f2, 16($7)
+  # FIXME: LDC1 is correctly rejected but the wrong error message is emitted.
+  # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
+  lwc1       $f2, 16($7)
+  # FIXME: LWC1 is correctly rejected but the wrong error message is emitted.
+  # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
+  madd.s     $f2, $f2, $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  mfc1       $7, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  mov.d      $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  mov.s      $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  movf.d     $f2, $f2, $fcc2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  movf.s     $f2, $f2, $fcc5
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  movn.d     $f2, $f2, $6
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  movn.s     $f2, $f2, $6
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  movt.d     $f2, $f2, $fcc0
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  movt.s     $f2, $f2, $fcc1
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  movz.d     $f2, $f2, $6
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  movz.s     $f2, $f2, $6
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  mtc1       $7, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  mul.d      $f2, $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  mul.s      $f2, $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  neg.d      $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  neg.s      $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  round.w.d  $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  round.w.s  $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  sdc1       $f2, 16($7)
+  # FIXME: SDC1 is correctly rejected but the wrong error message is emitted.
+  # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
+  sqrt.d     $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  sqrt.s     $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  sub.d      $f2, $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  sub.s      $f2, $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  swc1       $f2, 16($7)
+  # FIXME: SWC1 is correctly rejected but the wrong error message is emitted.
+  # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
+  trunc.w.d  $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  trunc.w.s  $f2, $f2
+  # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
diff --git a/test/MC/Mips/xgot.s b/test/MC/Mips/xgot.s
index 30848066ce3a..3380a856375f 100644
--- a/test/MC/Mips/xgot.s
+++ b/test/MC/Mips/xgot.s
@@ -9,8 +9,8 @@
 // CHECK:   0x14 R_MIPS_GOT_HI16 ext_1
 // CHECK:   0x1C R_MIPS_GOT_LO16 ext_1
 // CHECK:   0x24 R_MIPS_CALL_HI16 printf
-// CHECK:   0x2C R_MIPS_GOT16 $.str
 // CHECK:   0x30 R_MIPS_CALL_LO16 printf
+// CHECK:   0x2C R_MIPS_GOT16 $.str
 // CHECK:   0x38 R_MIPS_LO16 $.str
 // CHECK: ]
 
diff --git a/test/MC/PowerPC/dcbt.s b/test/MC/PowerPC/dcbt.s
new file mode 100644
index 000000000000..66f7fa07b031
--- /dev/null
+++ b/test/MC/PowerPC/dcbt.s
@@ -0,0 +1,13 @@
+# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=SERVER %s
+# RUN: llvm-mc -mcpu=a2 -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=EMBEDDED %s
+
+# SERVER: dcbt 2, 3, 10                   # encoding: [0x7d,0x42,0x1a,0x2c]
+          dcbt 2, 3, 10
+# SERVER: dcbtst 2, 3, 10                 # encoding: [0x7d,0x42,0x19,0xec]
+          dcbtst 2, 3, 10
+
+# EMBEDDED: dcbt 10, 2, 3                 # encoding: [0x7d,0x42,0x1a,0x2c]
+            dcbt 10, 2, 3
+# EMBEDDED: dcbtst 10, 2, 3               # encoding: [0x7d,0x42,0x19,0xec]
+            dcbtst 10, 2, 3
+
diff --git a/test/MC/PowerPC/htm.s b/test/MC/PowerPC/htm.s
new file mode 100644
index 000000000000..f99ff3cd5362
--- /dev/null
+++ b/test/MC/PowerPC/htm.s
@@ -0,0 +1,53 @@
+# RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
+# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
+
+# CHECK-BE: tbegin. 0                      # encoding: [0x7c,0x00,0x05,0x1d]
+# CHECK-LE: tbegin. 0                      # encoding: [0x1d,0x05,0x00,0x7c]
+            tbegin. 0
+# CHECK-BE: tbegin. 1                      # encoding: [0x7c,0x20,0x05,0x1d]
+# CHECK-LE: tbegin. 1                      # encoding: [0x1d,0x05,0x20,0x7c]
+            tbegin. 1
+
+# CHECK-BE: tend. 0                        # encoding: [0x7c,0x00,0x05,0x5d]
+# CHECK-LE: tend. 0                        # encoding: [0x5d,0x05,0x00,0x7c]
+            tend. 0
+# CHECK-BE: tend. 1                        # encoding: [0x7e,0x00,0x05,0x5d]
+# CHECK-LE: tend. 1                        # encoding: [0x5d,0x05,0x00,0x7e]
+            tend. 1
+
+# CHECK-BE: tabort. 9                      # encoding: [0x7c,0x09,0x07,0x1d]
+# CHECK-LE: tabort. 9                      # encoding: [0x1d,0x07,0x09,0x7c]
+            tabort. 9
+# CHECK-BE: tabortdc. 0, 9, 9              # encoding: [0x7c,0x09,0x4e,0x5d]
+# CHECK-LE: tabortdc. 0, 9, 9              # encoding: [0x5d,0x4e,0x09,0x7c]
+            tabortdc. 0, 9, 9
+# CHECK-BE: tabortdci. 0, 9, 0             # encoding: [0x7c,0x09,0x06,0xdd]
+# CHECK-LE: tabortdci. 0, 9, 0             # encoding: [0xdd,0x06,0x09,0x7c]
+            tabortdci. 0, 9, 0
+# CHECK-BE: tabortwc. 0, 9, 9              # encoding: [0x7c,0x09,0x4e,0x1d]
+# CHECK-LE: tabortwc. 0, 9, 9              # encoding: [0x1d,0x4e,0x09,0x7c]
+            tabortwc. 0, 9, 9
+# CHECK-BE: tabortwci. 0, 9, 0             # encoding: [0x7c,0x09,0x06,0x9d]
+# CHECK-LE: tabortwci. 0, 9, 0             # encoding: [0x9d,0x06,0x09,0x7c]
+            tabortwci. 0, 9, 0
+
+# CHECK-BE: tsr. 0                         # encoding: [0x7c,0x00,0x05,0xdd]
+# CHECK-LE: tsr. 0                         # encoding: [0xdd,0x05,0x00,0x7c]
+            tsr. 0
+# CHECK-BE: tsr. 1                         # encoding: [0x7c,0x20,0x05,0xdd]
+# CHECK-LE: tsr. 1                         # encoding: [0xdd,0x05,0x20,0x7c]
+            tsr. 1
+
+# CHECK-BE: tcheck 0                       # encoding: [0x7c,0x00,0x05,0x9c]
+# CHECK-LE: tcheck 0                       # encoding: [0x9c,0x05,0x00,0x7c]
+            tcheck 0
+# CHECK-BE: tcheck 3                       # encoding: [0x7d,0x80,0x05,0x9c]
+# CHECK-LE: tcheck 3                       # encoding: [0x9c,0x05,0x80,0x7d]
+            tcheck 3
+
+# CHECK-BE: treclaim. 9                    # encoding: [0x7c,0x09,0x07,0x5d]
+# CHECK-LE: treclaim. 9                    # encoding: [0x5d,0x07,0x09,0x7c]
+            treclaim. 9
+# CHECK-BE: trechkpt.                      # encoding: [0x7c,0x00,0x07,0xdd]
+# CHECK-LE: trechkpt.                      # encoding: [0xdd,0x07,0x00,0x7c]
+            trechkpt.
diff --git a/test/MC/PowerPC/ppc-reloc.s b/test/MC/PowerPC/ppc-reloc.s
index e7dd1e20b613..999d33ec5759 100644
--- a/test/MC/PowerPC/ppc-reloc.s
+++ b/test/MC/PowerPC/ppc-reloc.s
@@ -12,7 +12,7 @@ foo:
 	.size foo, . - foo
 
 # CHECK:      Relocations [
-# CHECK-NEXT:   Section (2) .rela.text {
+# CHECK-NEXT:   Section {{.*}} .rela.text {
 # CHECK-NEXT:     0x0 R_PPC_PLTREL24 printf 0x0
 # CHECK-NEXT:     0x4 R_PPC_LOCAL24PC _GLOBAL_OFFSET_TABLE_ 0xFFFFFFFC
 # CHECK-NEXT:   }
diff --git a/test/MC/PowerPC/ppc64-encoding-4xx.s b/test/MC/PowerPC/ppc64-encoding-4xx.s
index 5414e1a49bfb..46fa5524a8f8 100644
--- a/test/MC/PowerPC/ppc64-encoding-4xx.s
+++ b/test/MC/PowerPC/ppc64-encoding-4xx.s
@@ -10,30 +10,30 @@
 # CHECK-LE: mtdcr 178, 3                     # encoding: [0x86,0x2b,0x72,0x7c]
             mtdcr 178,3
 
-# CHECK-BE: tlbre 2, 3, 0                    # encoding: [0x7c,0x43,0x07,0x64]
-# CHECK-LE: tlbre 2, 3, 0                    # encoding: [0x64,0x07,0x43,0x7c]
+# CHECK-BE: tlbrehi 2, 3                     # encoding: [0x7c,0x43,0x07,0x64]
+# CHECK-LE: tlbrehi 2, 3                     # encoding: [0x64,0x07,0x43,0x7c]
             tlbre %r2, %r3, 0
-# CHECK-BE: tlbre 2, 3, 1                    # encoding: [0x7c,0x43,0x0f,0x64]
-# CHECK-LE: tlbre 2, 3, 1                    # encoding: [0x64,0x0f,0x43,0x7c]
+# CHECK-BE: tlbrelo 2, 3                     # encoding: [0x7c,0x43,0x0f,0x64]
+# CHECK-LE: tlbrelo 2, 3                     # encoding: [0x64,0x0f,0x43,0x7c]
             tlbre %r2, %r3, 1
-# CHECK-BE: tlbre 2, 3, 0                    # encoding: [0x7c,0x43,0x07,0x64]
-# CHECK-LE: tlbre 2, 3, 0                    # encoding: [0x64,0x07,0x43,0x7c]
+# CHECK-BE: tlbrehi 2, 3                     # encoding: [0x7c,0x43,0x07,0x64]
+# CHECK-LE: tlbrehi 2, 3                     # encoding: [0x64,0x07,0x43,0x7c]
             tlbrehi %r2, %r3
-# CHECK-BE: tlbre 2, 3, 1                    # encoding: [0x7c,0x43,0x0f,0x64]
-# CHECK-LE: tlbre 2, 3, 1                    # encoding: [0x64,0x0f,0x43,0x7c]
+# CHECK-BE: tlbrelo 2, 3                     # encoding: [0x7c,0x43,0x0f,0x64]
+# CHECK-LE: tlbrelo 2, 3                     # encoding: [0x64,0x0f,0x43,0x7c]
             tlbrelo %r2, %r3
 
-# CHECK-BE: tlbwe 2, 3, 0                    # encoding: [0x7c,0x43,0x07,0xa4]
-# CHECK-LE: tlbwe 2, 3, 0                    # encoding: [0xa4,0x07,0x43,0x7c]
+# CHECK-BE: tlbwehi 2, 3                     # encoding: [0x7c,0x43,0x07,0xa4]
+# CHECK-LE: tlbwehi 2, 3                     # encoding: [0xa4,0x07,0x43,0x7c]
             tlbwe %r2, %r3, 0
-# CHECK-BE: tlbwe 2, 3, 1                    # encoding: [0x7c,0x43,0x0f,0xa4]
-# CHECK-LE: tlbwe 2, 3, 1                    # encoding: [0xa4,0x0f,0x43,0x7c]
+# CHECK-BE: tlbwelo 2, 3                     # encoding: [0x7c,0x43,0x0f,0xa4]
+# CHECK-LE: tlbwelo 2, 3                     # encoding: [0xa4,0x0f,0x43,0x7c]
             tlbwe %r2, %r3, 1
-# CHECK-BE: tlbwe 2, 3, 0                    # encoding: [0x7c,0x43,0x07,0xa4]
-# CHECK-LE: tlbwe 2, 3, 0                    # encoding: [0xa4,0x07,0x43,0x7c]
+# CHECK-BE: tlbwehi 2, 3                     # encoding: [0x7c,0x43,0x07,0xa4]
+# CHECK-LE: tlbwehi 2, 3                     # encoding: [0xa4,0x07,0x43,0x7c]
             tlbwehi %r2, %r3
-# CHECK-BE: tlbwe 2, 3, 1                    # encoding: [0x7c,0x43,0x0f,0xa4]
-# CHECK-LE: tlbwe 2, 3, 1                    # encoding: [0xa4,0x0f,0x43,0x7c]
+# CHECK-BE: tlbwelo 2, 3                     # encoding: [0x7c,0x43,0x0f,0xa4]
+# CHECK-LE: tlbwelo 2, 3                     # encoding: [0xa4,0x0f,0x43,0x7c]
             tlbwelo %r2, %r3
 
 # CHECK-BE: tlbsx 2, 3, 1                    # encoding: [0x7c,0x43,0x0f,0x24]
@@ -43,52 +43,52 @@
 # CHECK-LE: tlbsx. 2, 3, 1                   # encoding: [0x25,0x0f,0x43,0x7c]
             tlbsx. %r2, %r3, %r1
 
-# CHECK-BE: mfspr 2, 1018                    # encoding: [0x7c,0x5a,0xfa,0xa6]
-# CHECK-LE: mfspr 2, 1018                    # encoding: [0xa6,0xfa,0x5a,0x7c]
+# CHECK-BE: mfdccr 2                         # encoding: [0x7c,0x5a,0xfa,0xa6]
+# CHECK-LE: mfdccr 2                         # encoding: [0xa6,0xfa,0x5a,0x7c]
             mfdccr %r2
-# CHECK-BE: mtspr 1018, 2                    # encoding: [0x7c,0x5a,0xfb,0xa6]
-# CHECK-LE: mtspr 1018, 2                    # encoding: [0xa6,0xfb,0x5a,0x7c]
+# CHECK-BE: mtdccr 2                         # encoding: [0x7c,0x5a,0xfb,0xa6]
+# CHECK-LE: mtdccr 2                         # encoding: [0xa6,0xfb,0x5a,0x7c]
             mtdccr %r2
 
-# CHECK-BE: mfspr 2, 1019                    # encoding: [0x7c,0x5b,0xfa,0xa6]
-# CHECK-LE: mfspr 2, 1019                    # encoding: [0xa6,0xfa,0x5b,0x7c]
+# CHECK-BE: mficcr 2                         # encoding: [0x7c,0x5b,0xfa,0xa6]
+# CHECK-LE: mficcr 2                         # encoding: [0xa6,0xfa,0x5b,0x7c]
             mficcr %r2
-# CHECK-BE: mtspr 1019, 2                    # encoding: [0x7c,0x5b,0xfb,0xa6]
-# CHECK-LE: mtspr 1019, 2                    # encoding: [0xa6,0xfb,0x5b,0x7c]
+# CHECK-BE: mticcr 2                         # encoding: [0x7c,0x5b,0xfb,0xa6]
+# CHECK-LE: mticcr 2                         # encoding: [0xa6,0xfb,0x5b,0x7c]
             mticcr %r2
 
-# CHECK-BE: mfspr 2, 981                    # encoding: [0x7c,0x55,0xf2,0xa6]
-# CHECK-LE: mfspr 2, 981                    # encoding: [0xa6,0xf2,0x55,0x7c]
+# CHECK-BE: mfdear 2                        # encoding: [0x7c,0x55,0xf2,0xa6]
+# CHECK-LE: mfdear 2                        # encoding: [0xa6,0xf2,0x55,0x7c]
             mfdear %r2
-# CHECK-BE: mtspr 981, 2                    # encoding: [0x7c,0x55,0xf3,0xa6]
-# CHECK-LE: mtspr 981, 2                    # encoding: [0xa6,0xf3,0x55,0x7c]
+# CHECK-BE: mtdear 2                        # encoding: [0x7c,0x55,0xf3,0xa6]
+# CHECK-LE: mtdear 2                        # encoding: [0xa6,0xf3,0x55,0x7c]
             mtdear %r2
 
-# CHECK-BE: mfspr 2, 980                    # encoding: [0x7c,0x54,0xf2,0xa6]
-# CHECK-LE: mfspr 2, 980                    # encoding: [0xa6,0xf2,0x54,0x7c]
+# CHECK-BE: mfesr 2                         # encoding: [0x7c,0x54,0xf2,0xa6]
+# CHECK-LE: mfesr 2                         # encoding: [0xa6,0xf2,0x54,0x7c]
             mfesr %r2
-# CHECK-BE: mtspr 980, 2                    # encoding: [0x7c,0x54,0xf3,0xa6]
-# CHECK-LE: mtspr 980, 2                    # encoding: [0xa6,0xf3,0x54,0x7c]
+# CHECK-BE: mtesr 2                         # encoding: [0x7c,0x54,0xf3,0xa6]
+# CHECK-LE: mtesr 2                         # encoding: [0xa6,0xf3,0x54,0x7c]
             mtesr %r2
 
-# CHECK-BE: mfspr 2, 986                    # encoding: [0x7c,0x5a,0xf2,0xa6]
-# CHECK-LE: mfspr 2, 986                    # encoding: [0xa6,0xf2,0x5a,0x7c]
+# CHECK-BE: mftcr 2                         # encoding: [0x7c,0x5a,0xf2,0xa6]
+# CHECK-LE: mftcr 2                         # encoding: [0xa6,0xf2,0x5a,0x7c]
             mftcr %r2
-# CHECK-BE: mtspr 986, 2                    # encoding: [0x7c,0x5a,0xf3,0xa6]
-# CHECK-LE: mtspr 986, 2                    # encoding: [0xa6,0xf3,0x5a,0x7c]
+# CHECK-BE: mttcr 2                         # encoding: [0x7c,0x5a,0xf3,0xa6]
+# CHECK-LE: mttcr 2                         # encoding: [0xa6,0xf3,0x5a,0x7c]
             mttcr %r2
 
-# CHECK-BE: mfspr 2, 989                    # encoding: [0x7c,0x5d,0xf2,0xa6]
-# CHECK-LE: mfspr 2, 989                    # encoding: [0xa6,0xf2,0x5d,0x7c]
+# CHECK-BE: mftblo 2                        # encoding: [0x7c,0x5d,0xf2,0xa6]
+# CHECK-LE: mftblo 2                        # encoding: [0xa6,0xf2,0x5d,0x7c]
             mftblo %r2
-# CHECK-BE: mtspr 989, 2                    # encoding: [0x7c,0x5d,0xf3,0xa6]
-# CHECK-LE: mtspr 989, 2                    # encoding: [0xa6,0xf3,0x5d,0x7c]
+# CHECK-BE: mttblo 2                        # encoding: [0x7c,0x5d,0xf3,0xa6]
+# CHECK-LE: mttblo 2                        # encoding: [0xa6,0xf3,0x5d,0x7c]
             mttblo %r2
-# CHECK-BE: mfspr 2, 988                    # encoding: [0x7c,0x5c,0xf2,0xa6]
-# CHECK-LE: mfspr 2, 988                    # encoding: [0xa6,0xf2,0x5c,0x7c]
+# CHECK-BE: mftbhi 2                        # encoding: [0x7c,0x5c,0xf2,0xa6]
+# CHECK-LE: mftbhi 2                        # encoding: [0xa6,0xf2,0x5c,0x7c]
             mftbhi %r2
-# CHECK-BE: mtspr 988, 2                    # encoding: [0x7c,0x5c,0xf3,0xa6]
-# CHECK-LE: mtspr 988, 2                    # encoding: [0xa6,0xf3,0x5c,0x7c]
+# CHECK-BE: mttbhi 2                        # encoding: [0x7c,0x5c,0xf3,0xa6]
+# CHECK-LE: mttbhi 2                        # encoding: [0xa6,0xf3,0x5c,0x7c]
             mttbhi %r2
 
 # CHECK-BE: dccci 5, 6                      # encoding: [0x7c,0x05,0x33,0x8c]
@@ -104,64 +104,64 @@
 # CHECK-LE: iccci 0, 0                      # encoding: [0x8c,0x07,0x00,0x7c]
             ici 0
 
-# CHECK-BE: mfspr 2, 990                    # encoding: [0x7c,0x5e,0xf2,0xa6]
-# CHECK-LE: mfspr 2, 990                    # encoding: [0xa6,0xf2,0x5e,0x7c]
+# CHECK-BE: mfsrr2 2                        # encoding: [0x7c,0x5e,0xf2,0xa6]
+# CHECK-LE: mfsrr2 2                        # encoding: [0xa6,0xf2,0x5e,0x7c]
             mfsrr2 2
-# CHECK-BE: mtspr 990, 2                    # encoding: [0x7c,0x5e,0xf3,0xa6]
-# CHECK-LE: mtspr 990, 2                    # encoding: [0xa6,0xf3,0x5e,0x7c]
+# CHECK-BE: mtsrr2 2                        # encoding: [0x7c,0x5e,0xf3,0xa6]
+# CHECK-LE: mtsrr2 2                        # encoding: [0xa6,0xf3,0x5e,0x7c]
             mtsrr2 2
-# CHECK-BE: mfspr 2, 991                    # encoding: [0x7c,0x5f,0xf2,0xa6]
-# CHECK-LE: mfspr 2, 991                    # encoding: [0xa6,0xf2,0x5f,0x7c]
+# CHECK-BE: mfsrr3 2                        # encoding: [0x7c,0x5f,0xf2,0xa6]
+# CHECK-LE: mfsrr3 2                        # encoding: [0xa6,0xf2,0x5f,0x7c]
             mfsrr3 2
-# CHECK-BE: mtspr 991, 2                    # encoding: [0x7c,0x5f,0xf3,0xa6]
-# CHECK-LE: mtspr 991, 2                    # encoding: [0xa6,0xf3,0x5f,0x7c]
+# CHECK-BE: mtsrr3 2                        # encoding: [0x7c,0x5f,0xf3,0xa6]
+# CHECK-LE: mtsrr3 2                        # encoding: [0xa6,0xf3,0x5f,0x7c]
             mtsrr3 2
 
-# CHECK-BE: mfdcr 5, 128                    # encoding: [0x7c,0xa0,0x22,0x86]
-# CHECK-LE: mfdcr 5, 128                    # encoding: [0x86,0x22,0xa0,0x7c]
+# CHECK-BE: mfbr0 5                         # encoding: [0x7c,0xa0,0x22,0x86]
+# CHECK-LE: mfbr0 5                         # encoding: [0x86,0x22,0xa0,0x7c]
             mfbr0 %r5
-# CHECK-BE: mtdcr 128, 5                    # encoding: [0x7c,0xa0,0x23,0x86]
-# CHECK-LE: mtdcr 128, 5                    # encoding: [0x86,0x23,0xa0,0x7c]
+# CHECK-BE: mtbr0 5                         # encoding: [0x7c,0xa0,0x23,0x86]
+# CHECK-LE: mtbr0 5                         # encoding: [0x86,0x23,0xa0,0x7c]
             mtbr0 %r5
-# CHECK-BE: mfdcr 5, 129                    # encoding: [0x7c,0xa1,0x22,0x86]
-# CHECK-LE: mfdcr 5, 129                    # encoding: [0x86,0x22,0xa1,0x7c]
+# CHECK-BE: mfbr1 5                         # encoding: [0x7c,0xa1,0x22,0x86]
+# CHECK-LE: mfbr1 5                         # encoding: [0x86,0x22,0xa1,0x7c]
             mfbr1 %r5
-# CHECK-BE: mtdcr 129, 5                    # encoding: [0x7c,0xa1,0x23,0x86]
-# CHECK-LE: mtdcr 129, 5                    # encoding: [0x86,0x23,0xa1,0x7c]
+# CHECK-BE: mtbr1 5                         # encoding: [0x7c,0xa1,0x23,0x86]
+# CHECK-LE: mtbr1 5                         # encoding: [0x86,0x23,0xa1,0x7c]
             mtbr1 %r5
-# CHECK-BE: mfdcr 5, 130                    # encoding: [0x7c,0xa2,0x22,0x86]
-# CHECK-LE: mfdcr 5, 130                    # encoding: [0x86,0x22,0xa2,0x7c]
+# CHECK-BE: mfbr2 5                         # encoding: [0x7c,0xa2,0x22,0x86]
+# CHECK-LE: mfbr2 5                         # encoding: [0x86,0x22,0xa2,0x7c]
             mfbr2 %r5
-# CHECK-BE: mtdcr 130, 5                    # encoding: [0x7c,0xa2,0x23,0x86]
-# CHECK-LE: mtdcr 130, 5                    # encoding: [0x86,0x23,0xa2,0x7c]
+# CHECK-BE: mtbr2 5                         # encoding: [0x7c,0xa2,0x23,0x86]
+# CHECK-LE: mtbr2 5                         # encoding: [0x86,0x23,0xa2,0x7c]
             mtbr2 %r5
-# CHECK-BE: mfdcr 5, 131                    # encoding: [0x7c,0xa3,0x22,0x86]
-# CHECK-LE: mfdcr 5, 131                    # encoding: [0x86,0x22,0xa3,0x7c]
+# CHECK-BE: mfbr3 5                         # encoding: [0x7c,0xa3,0x22,0x86]
+# CHECK-LE: mfbr3 5                         # encoding: [0x86,0x22,0xa3,0x7c]
             mfbr3 %r5
-# CHECK-BE: mtdcr 131, 5                    # encoding: [0x7c,0xa3,0x23,0x86]
-# CHECK-LE: mtdcr 131, 5                    # encoding: [0x86,0x23,0xa3,0x7c]
+# CHECK-BE: mtbr3 5                         # encoding: [0x7c,0xa3,0x23,0x86]
+# CHECK-LE: mtbr3 5                         # encoding: [0x86,0x23,0xa3,0x7c]
             mtbr3 %r5
-# CHECK-BE: mfdcr 5, 132                    # encoding: [0x7c,0xa4,0x22,0x86]
-# CHECK-LE: mfdcr 5, 132                    # encoding: [0x86,0x22,0xa4,0x7c]
+# CHECK-BE: mfbr4 5                         # encoding: [0x7c,0xa4,0x22,0x86]
+# CHECK-LE: mfbr4 5                         # encoding: [0x86,0x22,0xa4,0x7c]
             mfbr4 %r5
-# CHECK-BE: mtdcr 132, 5                    # encoding: [0x7c,0xa4,0x23,0x86]
-# CHECK-LE: mtdcr 132, 5                    # encoding: [0x86,0x23,0xa4,0x7c]
+# CHECK-BE: mtbr4 5                         # encoding: [0x7c,0xa4,0x23,0x86]
+# CHECK-LE: mtbr4 5                         # encoding: [0x86,0x23,0xa4,0x7c]
             mtbr4 %r5
-# CHECK-BE: mfdcr 5, 133                    # encoding: [0x7c,0xa5,0x22,0x86]
-# CHECK-LE: mfdcr 5, 133                    # encoding: [0x86,0x22,0xa5,0x7c]
+# CHECK-BE: mfbr5 5                         # encoding: [0x7c,0xa5,0x22,0x86]
+# CHECK-LE: mfbr5 5                         # encoding: [0x86,0x22,0xa5,0x7c]
             mfbr5 %r5
-# CHECK-BE: mtdcr 133, 5                    # encoding: [0x7c,0xa5,0x23,0x86]
-# CHECK-LE: mtdcr 133, 5                    # encoding: [0x86,0x23,0xa5,0x7c]
+# CHECK-BE: mtbr5 5                         # encoding: [0x7c,0xa5,0x23,0x86]
+# CHECK-LE: mtbr5 5                         # encoding: [0x86,0x23,0xa5,0x7c]
             mtbr5 %r5
-# CHECK-BE: mfdcr 5, 134                    # encoding: [0x7c,0xa6,0x22,0x86]
-# CHECK-LE: mfdcr 5, 134                    # encoding: [0x86,0x22,0xa6,0x7c]
+# CHECK-BE: mfbr6 5                         # encoding: [0x7c,0xa6,0x22,0x86]
+# CHECK-LE: mfbr6 5                         # encoding: [0x86,0x22,0xa6,0x7c]
             mfbr6 %r5
-# CHECK-BE: mtdcr 134, 5                    # encoding: [0x7c,0xa6,0x23,0x86]
-# CHECK-LE: mtdcr 134, 5                    # encoding: [0x86,0x23,0xa6,0x7c]
+# CHECK-BE: mtbr6 5                         # encoding: [0x7c,0xa6,0x23,0x86]
+# CHECK-LE: mtbr6 5                         # encoding: [0x86,0x23,0xa6,0x7c]
             mtbr6 %r5
-# CHECK-BE: mfdcr 5, 135                    # encoding: [0x7c,0xa7,0x22,0x86]
-# CHECK-LE: mfdcr 5, 135                    # encoding: [0x86,0x22,0xa7,0x7c]
+# CHECK-BE: mfbr7 5                         # encoding: [0x7c,0xa7,0x22,0x86]
+# CHECK-LE: mfbr7 5                         # encoding: [0x86,0x22,0xa7,0x7c]
             mfbr7 %r5
-# CHECK-BE: mtdcr 135, 5                    # encoding: [0x7c,0xa7,0x23,0x86]
-# CHECK-LE: mtdcr 135, 5                    # encoding: [0x86,0x23,0xa7,0x7c]
+# CHECK-BE: mtbr7 5                         # encoding: [0x7c,0xa7,0x23,0x86]
+# CHECK-LE: mtbr7 5                         # encoding: [0x86,0x23,0xa7,0x7c]
             mtbr7 %r5
diff --git a/test/MC/PowerPC/ppc64-encoding-6xx.s b/test/MC/PowerPC/ppc64-encoding-6xx.s
index 3a5e7a126b84..657eaf3f5da9 100644
--- a/test/MC/PowerPC/ppc64-encoding-6xx.s
+++ b/test/MC/PowerPC/ppc64-encoding-6xx.s
@@ -3,102 +3,102 @@
 
 # Instructions specific to the PowerPC 6xx family:
 
-# CHECK-BE: mfspr 12, 528                    # encoding: [0x7d,0x90,0x82,0xa6]
-# CHECK-LE: mfspr 12, 528                    # encoding: [0xa6,0x82,0x90,0x7d]
+# CHECK-BE: mfibatu 12, 0                    # encoding: [0x7d,0x90,0x82,0xa6]
+# CHECK-LE: mfibatu 12, 0                    # encoding: [0xa6,0x82,0x90,0x7d]
 mfibatu %r12, 0
-# CHECK-BE: mfspr 12, 529                    # encoding: [0x7d,0x91,0x82,0xa6]
-# CHECK-LE: mfspr 12, 529                    # encoding: [0xa6,0x82,0x91,0x7d]
+# CHECK-BE: mfibatl 12, 0                    # encoding: [0x7d,0x91,0x82,0xa6]
+# CHECK-LE: mfibatl 12, 0                    # encoding: [0xa6,0x82,0x91,0x7d]
 mfibatl %r12, 0
-# CHECK-BE: mfspr 12, 530                    # encoding: [0x7d,0x92,0x82,0xa6]
-# CHECK-LE: mfspr 12, 530                    # encoding: [0xa6,0x82,0x92,0x7d]
+# CHECK-BE: mfibatu 12, 1                    # encoding: [0x7d,0x92,0x82,0xa6]
+# CHECK-LE: mfibatu 12, 1                    # encoding: [0xa6,0x82,0x92,0x7d]
 mfibatu %r12, 1
-# CHECK-BE: mfspr 12, 531                    # encoding: [0x7d,0x93,0x82,0xa6]
-# CHECK-LE: mfspr 12, 531                    # encoding: [0xa6,0x82,0x93,0x7d]
+# CHECK-BE: mfibatl 12, 1                    # encoding: [0x7d,0x93,0x82,0xa6]
+# CHECK-LE: mfibatl 12, 1                    # encoding: [0xa6,0x82,0x93,0x7d]
 mfibatl %r12, 1
-# CHECK-BE: mfspr 12, 532                    # encoding: [0x7d,0x94,0x82,0xa6]
-# CHECK-LE: mfspr 12, 532                    # encoding: [0xa6,0x82,0x94,0x7d]
+# CHECK-BE: mfibatu 12, 2                    # encoding: [0x7d,0x94,0x82,0xa6]
+# CHECK-LE: mfibatu 12, 2                    # encoding: [0xa6,0x82,0x94,0x7d]
 mfibatu %r12, 2
-# CHECK-BE: mfspr 12, 533                    # encoding: [0x7d,0x95,0x82,0xa6]
-# CHECK-LE: mfspr 12, 533                    # encoding: [0xa6,0x82,0x95,0x7d]
+# CHECK-BE: mfibatl 12, 2                    # encoding: [0x7d,0x95,0x82,0xa6]
+# CHECK-LE: mfibatl 12, 2                    # encoding: [0xa6,0x82,0x95,0x7d]
 mfibatl %r12, 2
-# CHECK-BE: mfspr 12, 534                    # encoding: [0x7d,0x96,0x82,0xa6]
-# CHECK-LE: mfspr 12, 534                    # encoding: [0xa6,0x82,0x96,0x7d]
+# CHECK-BE: mfibatu 12, 3                    # encoding: [0x7d,0x96,0x82,0xa6]
+# CHECK-LE: mfibatu 12, 3                    # encoding: [0xa6,0x82,0x96,0x7d]
 mfibatu %r12, 3
-# CHECK-BE: mfspr 12, 535                    # encoding: [0x7d,0x97,0x82,0xa6]
-# CHECK-LE: mfspr 12, 535                    # encoding: [0xa6,0x82,0x97,0x7d]
+# CHECK-BE: mfibatl 12, 3                    # encoding: [0x7d,0x97,0x82,0xa6]
+# CHECK-LE: mfibatl 12, 3                    # encoding: [0xa6,0x82,0x97,0x7d]
 mfibatl %r12, 3
-# CHECK-BE: mtspr 528, 12                    # encoding: [0x7d,0x90,0x83,0xa6]
-# CHECK-LE: mtspr 528, 12                    # encoding: [0xa6,0x83,0x90,0x7d]
+# CHECK-BE: mtibatu 0, 12                    # encoding: [0x7d,0x90,0x83,0xa6]
+# CHECK-LE: mtibatu 0, 12                    # encoding: [0xa6,0x83,0x90,0x7d]
 mtibatu 0, %r12
-# CHECK-BE: mtspr 529, 12                    # encoding: [0x7d,0x91,0x83,0xa6]
-# CHECK-LE: mtspr 529, 12                    # encoding: [0xa6,0x83,0x91,0x7d]
+# CHECK-BE: mtibatl 0, 12                    # encoding: [0x7d,0x91,0x83,0xa6]
+# CHECK-LE: mtibatl 0, 12                    # encoding: [0xa6,0x83,0x91,0x7d]
 mtibatl 0, %r12
-# CHECK-BE: mtspr 530, 12                    # encoding: [0x7d,0x92,0x83,0xa6]
-# CHECK-LE: mtspr 530, 12                    # encoding: [0xa6,0x83,0x92,0x7d]
+# CHECK-BE: mtibatu 1, 12                    # encoding: [0x7d,0x92,0x83,0xa6]
+# CHECK-LE: mtibatu 1, 12                    # encoding: [0xa6,0x83,0x92,0x7d]
 mtibatu 1, %r12
-# CHECK-BE: mtspr 531, 12                    # encoding: [0x7d,0x93,0x83,0xa6]
-# CHECK-LE: mtspr 531, 12                    # encoding: [0xa6,0x83,0x93,0x7d]
+# CHECK-BE: mtibatl 1, 12                    # encoding: [0x7d,0x93,0x83,0xa6]
+# CHECK-LE: mtibatl 1, 12                    # encoding: [0xa6,0x83,0x93,0x7d]
 mtibatl 1, %r12
-# CHECK-BE: mtspr 532, 12                    # encoding: [0x7d,0x94,0x83,0xa6]
-# CHECK-LE: mtspr 532, 12                    # encoding: [0xa6,0x83,0x94,0x7d]
+# CHECK-BE: mtibatu 2, 12                    # encoding: [0x7d,0x94,0x83,0xa6]
+# CHECK-LE: mtibatu 2, 12                    # encoding: [0xa6,0x83,0x94,0x7d]
 mtibatu 2, %r12
-# CHECK-BE: mtspr 533, 12                    # encoding: [0x7d,0x95,0x83,0xa6]
-# CHECK-LE: mtspr 533, 12                    # encoding: [0xa6,0x83,0x95,0x7d]
+# CHECK-BE: mtibatl 2, 12                    # encoding: [0x7d,0x95,0x83,0xa6]
+# CHECK-LE: mtibatl 2, 12                    # encoding: [0xa6,0x83,0x95,0x7d]
 mtibatl 2, %r12
-# CHECK-BE: mtspr 534, 12                    # encoding: [0x7d,0x96,0x83,0xa6]
-# CHECK-LE: mtspr 534, 12                    # encoding: [0xa6,0x83,0x96,0x7d]
+# CHECK-BE: mtibatu 3, 12                    # encoding: [0x7d,0x96,0x83,0xa6]
+# CHECK-LE: mtibatu 3, 12                    # encoding: [0xa6,0x83,0x96,0x7d]
 mtibatu 3, %r12
-# CHECK-BE: mtspr 535, 12                    # encoding: [0x7d,0x97,0x83,0xa6]
-# CHECK-LE: mtspr 535, 12                    # encoding: [0xa6,0x83,0x97,0x7d]
+# CHECK-BE: mtibatl 3, 12                    # encoding: [0x7d,0x97,0x83,0xa6]
+# CHECK-LE: mtibatl 3, 12                    # encoding: [0xa6,0x83,0x97,0x7d]
 mtibatl 3, %r12
 
-# CHECK-BE: mfspr 12, 536                    # encoding: [0x7d,0x98,0x82,0xa6]
-# CHECK-LE: mfspr 12, 536                    # encoding: [0xa6,0x82,0x98,0x7d]
+# CHECK-BE: mfdbatu 12, 0                    # encoding: [0x7d,0x98,0x82,0xa6]
+# CHECK-LE: mfdbatu 12, 0                    # encoding: [0xa6,0x82,0x98,0x7d]
 mfdbatu %r12, 0
-# CHECK-BE: mfspr 12, 537                    # encoding: [0x7d,0x99,0x82,0xa6]
-# CHECK-LE: mfspr 12, 537                    # encoding: [0xa6,0x82,0x99,0x7d]
+# CHECK-BE: mfdbatl 12, 0                    # encoding: [0x7d,0x99,0x82,0xa6]
+# CHECK-LE: mfdbatl 12, 0                    # encoding: [0xa6,0x82,0x99,0x7d]
 mfdbatl %r12, 0
-# CHECK-BE: mfspr 12, 538                    # encoding: [0x7d,0x9a,0x82,0xa6]
-# CHECK-LE: mfspr 12, 538                    # encoding: [0xa6,0x82,0x9a,0x7d]
+# CHECK-BE: mfdbatu 12, 1                    # encoding: [0x7d,0x9a,0x82,0xa6]
+# CHECK-LE: mfdbatu 12, 1                    # encoding: [0xa6,0x82,0x9a,0x7d]
 mfdbatu %r12, 1
-# CHECK-BE: mfspr 12, 539                    # encoding: [0x7d,0x9b,0x82,0xa6]
-# CHECK-LE: mfspr 12, 539                    # encoding: [0xa6,0x82,0x9b,0x7d]
+# CHECK-BE: mfdbatl 12, 1                    # encoding: [0x7d,0x9b,0x82,0xa6]
+# CHECK-LE: mfdbatl 12, 1                    # encoding: [0xa6,0x82,0x9b,0x7d]
 mfdbatl %r12, 1
-# CHECK-BE: mfspr 12, 540                    # encoding: [0x7d,0x9c,0x82,0xa6]
-# CHECK-LE: mfspr 12, 540                    # encoding: [0xa6,0x82,0x9c,0x7d]
+# CHECK-BE: mfdbatu 12, 2                    # encoding: [0x7d,0x9c,0x82,0xa6]
+# CHECK-LE: mfdbatu 12, 2                    # encoding: [0xa6,0x82,0x9c,0x7d]
 mfdbatu %r12, 2
-# CHECK-BE: mfspr 12, 541                    # encoding: [0x7d,0x9d,0x82,0xa6]
-# CHECK-LE: mfspr 12, 541                    # encoding: [0xa6,0x82,0x9d,0x7d]
+# CHECK-BE: mfdbatl 12, 2                    # encoding: [0x7d,0x9d,0x82,0xa6]
+# CHECK-LE: mfdbatl 12, 2                    # encoding: [0xa6,0x82,0x9d,0x7d]
 mfdbatl %r12, 2
-# CHECK-BE: mfspr 12, 542                    # encoding: [0x7d,0x9e,0x82,0xa6]
-# CHECK-LE: mfspr 12, 542                    # encoding: [0xa6,0x82,0x9e,0x7d]
+# CHECK-BE: mfdbatu 12, 3                    # encoding: [0x7d,0x9e,0x82,0xa6]
+# CHECK-LE: mfdbatu 12, 3                    # encoding: [0xa6,0x82,0x9e,0x7d]
 mfdbatu %r12, 3
-# CHECK-BE: mfspr 12, 543                    # encoding: [0x7d,0x9f,0x82,0xa6]
-# CHECK-LE: mfspr 12, 543                    # encoding: [0xa6,0x82,0x9f,0x7d]
+# CHECK-BE: mfdbatl 12, 3                    # encoding: [0x7d,0x9f,0x82,0xa6]
+# CHECK-LE: mfdbatl 12, 3                    # encoding: [0xa6,0x82,0x9f,0x7d]
 mfdbatl %r12, 3
-# CHECK-BE: mtspr 536, 12                    # encoding: [0x7d,0x98,0x83,0xa6]
-# CHECK-LE: mtspr 536, 12                    # encoding: [0xa6,0x83,0x98,0x7d]
+# CHECK-BE: mtdbatu 0, 12                    # encoding: [0x7d,0x98,0x83,0xa6]
+# CHECK-LE: mtdbatu 0, 12                    # encoding: [0xa6,0x83,0x98,0x7d]
 mtdbatu 0, %r12
-# CHECK-BE: mtspr 537, 12                    # encoding: [0x7d,0x99,0x83,0xa6]
-# CHECK-LE: mtspr 537, 12                    # encoding: [0xa6,0x83,0x99,0x7d]
+# CHECK-BE: mtdbatl 0, 12                    # encoding: [0x7d,0x99,0x83,0xa6]
+# CHECK-LE: mtdbatl 0, 12                    # encoding: [0xa6,0x83,0x99,0x7d]
 mtdbatl 0, %r12
-# CHECK-BE: mtspr 538, 12                    # encoding: [0x7d,0x9a,0x83,0xa6]
-# CHECK-LE: mtspr 538, 12                    # encoding: [0xa6,0x83,0x9a,0x7d]
+# CHECK-BE: mtdbatu 1, 12                    # encoding: [0x7d,0x9a,0x83,0xa6]
+# CHECK-LE: mtdbatu 1, 12                    # encoding: [0xa6,0x83,0x9a,0x7d]
 mtdbatu 1, %r12
-# CHECK-BE: mtspr 539, 12                    # encoding: [0x7d,0x9b,0x83,0xa6]
-# CHECK-LE: mtspr 539, 12                    # encoding: [0xa6,0x83,0x9b,0x7d]
+# CHECK-BE: mtdbatl 1, 12                    # encoding: [0x7d,0x9b,0x83,0xa6]
+# CHECK-LE: mtdbatl 1, 12                    # encoding: [0xa6,0x83,0x9b,0x7d]
 mtdbatl 1, %r12
-# CHECK-BE: mtspr 540, 12                    # encoding: [0x7d,0x9c,0x83,0xa6]
-# CHECK-LE: mtspr 540, 12                    # encoding: [0xa6,0x83,0x9c,0x7d]
+# CHECK-BE: mtdbatu 2, 12                    # encoding: [0x7d,0x9c,0x83,0xa6]
+# CHECK-LE: mtdbatu 2, 12                    # encoding: [0xa6,0x83,0x9c,0x7d]
 mtdbatu 2, %r12
-# CHECK-BE: mtspr 541, 12                    # encoding: [0x7d,0x9d,0x83,0xa6]
-# CHECK-LE: mtspr 541, 12                    # encoding: [0xa6,0x83,0x9d,0x7d]
+# CHECK-BE: mtdbatl 2, 12                    # encoding: [0x7d,0x9d,0x83,0xa6]
+# CHECK-LE: mtdbatl 2, 12                    # encoding: [0xa6,0x83,0x9d,0x7d]
 mtdbatl 2, %r12
-# CHECK-BE: mtspr 542, 12                    # encoding: [0x7d,0x9e,0x83,0xa6]
-# CHECK-LE: mtspr 542, 12                    # encoding: [0xa6,0x83,0x9e,0x7d]
+# CHECK-BE: mtdbatu 3, 12                    # encoding: [0x7d,0x9e,0x83,0xa6]
+# CHECK-LE: mtdbatu 3, 12                    # encoding: [0xa6,0x83,0x9e,0x7d]
 mtdbatu 3, %r12
-# CHECK-BE: mtspr 543, 12                    # encoding: [0x7d,0x9f,0x83,0xa6]
-# CHECK-LE: mtspr 543, 12                    # encoding: [0xa6,0x83,0x9f,0x7d]
+# CHECK-BE: mtdbatl 3, 12                    # encoding: [0x7d,0x9f,0x83,0xa6]
+# CHECK-LE: mtdbatl 3, 12                    # encoding: [0xa6,0x83,0x9f,0x7d]
 mtdbatl 3, %r12
 
 # CHECK-BE: tlbld 4                        # encoding: [0x7c,0x00,0x27,0xa4]
diff --git a/test/MC/PowerPC/ppc64-encoding-bookII.s b/test/MC/PowerPC/ppc64-encoding-bookII.s
index 20eba7083f6d..9b68dcc7e8d1 100644
--- a/test/MC/PowerPC/ppc64-encoding-bookII.s
+++ b/test/MC/PowerPC/ppc64-encoding-bookII.s
@@ -12,14 +12,48 @@
 # CHECK-LE: icbt 0, 5, 31                   # encoding: [0x2c,0xf8,0x05,0x7c]
             icbt 0, 5, 31
 
-# FIXME:    dcbt 2, 3, 10
+# CHECK-BE: dcbt 2, 3, 10                   # encoding: [0x7d,0x42,0x1a,0x2c]
+# CHECK-LE: dcbt 2, 3, 10                   # encoding: [0x2c,0x1a,0x42,0x7d]
+            dcbt 2, 3, 10
+# CHECK-BE: dcbt 2, 3, 10                   # encoding: [0x7d,0x42,0x1a,0x2c]
+# CHECK-LE: dcbt 2, 3, 10                   # encoding: [0x2c,0x1a,0x42,0x7d]
+            dcbtct 2, 3, 10
+# CHECK-BE: dcbt 2, 3, 10                   # encoding: [0x7d,0x42,0x1a,0x2c]
+# CHECK-LE: dcbt 2, 3, 10                   # encoding: [0x2c,0x1a,0x42,0x7d]
+            dcbtds 2, 3, 10
 # CHECK-BE: dcbt 2, 3                       # encoding: [0x7c,0x02,0x1a,0x2c]
 # CHECK-LE: dcbt 2, 3                       # encoding: [0x2c,0x1a,0x02,0x7c]
             dcbt 2, 3
-# FIXME:    dcbtst 2, 3, 10
+# CHECK-BE: dcbt 2, 3                       # encoding: [0x7c,0x02,0x1a,0x2c]
+# CHECK-LE: dcbt 2, 3                       # encoding: [0x2c,0x1a,0x02,0x7c]
+            dcbt 2, 3, 0
+# CHECK-BE: dcbtt 2, 3                      # encoding: [0x7e,0x02,0x1a,0x2c]
+# CHECK-LE: dcbtt 2, 3                      # encoding: [0x2c,0x1a,0x02,0x7e]
+            dcbtt 2, 3
+# CHECK-BE: dcbtt 2, 3                      # encoding: [0x7e,0x02,0x1a,0x2c]
+# CHECK-LE: dcbtt 2, 3                      # encoding: [0x2c,0x1a,0x02,0x7e]
+            dcbt 2, 3, 16
+# CHECK-BE: dcbtst 2, 3, 10                 # encoding: [0x7d,0x42,0x19,0xec]
+# CHECK-LE: dcbtst 2, 3, 10                 # encoding: [0xec,0x19,0x42,0x7d]
+            dcbtst 2, 3, 10
+# CHECK-BE: dcbtst 2, 3, 10                 # encoding: [0x7d,0x42,0x19,0xec]
+# CHECK-LE: dcbtst 2, 3, 10                 # encoding: [0xec,0x19,0x42,0x7d]
+            dcbtstct 2, 3, 10
+# CHECK-BE: dcbtst 2, 3, 10                 # encoding: [0x7d,0x42,0x19,0xec]
+# CHECK-LE: dcbtst 2, 3, 10                 # encoding: [0xec,0x19,0x42,0x7d]
+            dcbtstds 2, 3, 10
 # CHECK-BE: dcbtst 2, 3                     # encoding: [0x7c,0x02,0x19,0xec]
 # CHECK-LE: dcbtst 2, 3                     # encoding: [0xec,0x19,0x02,0x7c]
             dcbtst 2, 3
+# CHECK-BE: dcbtst 2, 3                     # encoding: [0x7c,0x02,0x19,0xec]
+# CHECK-LE: dcbtst 2, 3                     # encoding: [0xec,0x19,0x02,0x7c]
+            dcbtst 2, 3, 0
+# CHECK-BE: dcbtstt 2, 3                    # encoding: [0x7e,0x02,0x19,0xec]
+# CHECK-LE: dcbtstt 2, 3                    # encoding: [0xec,0x19,0x02,0x7e]
+            dcbtstt 2, 3
+# CHECK-BE: dcbtstt 2, 3                    # encoding: [0x7e,0x02,0x19,0xec]
+# CHECK-LE: dcbtstt 2, 3                    # encoding: [0xec,0x19,0x02,0x7e]
+            dcbtst 2, 3, 16
 # CHECK-BE: dcbz 2, 3                       # encoding: [0x7c,0x02,0x1f,0xec]
 # CHECK-LE: dcbz 2, 3                       # encoding: [0xec,0x1f,0x02,0x7c]
             dcbz 2, 3
@@ -34,11 +68,6 @@
 # CHECK-LE: isync                           # encoding: [0x2c,0x01,0x00,0x4c]
             isync
 
-# FIXME:    lbarx 2, 3, 4, 1
-# FIXME:    lharx 2, 3, 4, 1
-# FIXME:    lwarx 2, 3, 4, 1
-# FIXME:    ldarx 2, 3, 4, 1
-
 # FIXME:    stbcx. 2, 3, 4
 # FIXME:    sthcx. 2, 3, 4
 # CHECK-BE: stwcx. 2, 3, 4                  # encoding: [0x7c,0x43,0x21,0x2d]
@@ -48,19 +77,19 @@
 # CHECK-LE: stdcx. 2, 3, 4                  # encoding: [0xad,0x21,0x43,0x7c]
             stdcx. 2, 3, 4
 
-# CHECK-BE: sync 2                          # encoding: [0x7c,0x40,0x04,0xac]
-# CHECK-LE: sync 2                          # encoding: [0xac,0x04,0x40,0x7c]
+# CHECK-BE: ptesync                         # encoding: [0x7c,0x40,0x04,0xac]
+# CHECK-LE: ptesync                         # encoding: [0xac,0x04,0x40,0x7c]
             sync 2
 # CHECK-BE: eieio                           # encoding: [0x7c,0x00,0x06,0xac]
 # CHECK-LE: eieio                           # encoding: [0xac,0x06,0x00,0x7c]
             eieio
-# CHECK-BE: wait 2                          # encoding: [0x7c,0x40,0x00,0x7c]
-# CHECK-LE: wait 2                          # encoding: [0x7c,0x00,0x40,0x7c]
+# CHECK-BE: waitimpl                        # encoding: [0x7c,0x40,0x00,0x7c]
+# CHECK-LE: waitimpl                        # encoding: [0x7c,0x00,0x40,0x7c]
             wait 2
 # CHECK-BE: mbar 1                          # encoding: [0x7c,0x20,0x06,0xac]
 # CHECK-LE: mbar 1                          # encoding: [0xac,0x06,0x20,0x7c]
             mbar 1
-# CHECK-BE: mbar 0
+# CHECK-BE: mbar                            # encoding: [0x7c,0x00,0x06,0xac]
             mbar
 
 # Extended mnemonics
@@ -70,36 +99,59 @@
             dcbf 2, 3
 # FIXME:    dcbfl 2, 3
 
-# FIXME:    lbarx 2, 3, 4
-# FIXME:    lharx 2, 3, 4
+# CHECK-BE: lbarx 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0x68]
+# CHECK-LE: lbarx 2, 3, 4                   # encoding: [0x68,0x20,0x43,0x7c]
+            lbarx 2, 3, 4
+
+# CHECK-BE: lharx 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0xe8]
+# CHECK-LE: lharx 2, 3, 4                   # encoding: [0xe8,0x20,0x43,0x7c]
+            lharx 2, 3, 4
+
 # CHECK-BE: lwarx 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0x28]
 # CHECK-LE: lwarx 2, 3, 4                   # encoding: [0x28,0x20,0x43,0x7c]
             lwarx 2, 3, 4
+
 # CHECK-BE: ldarx 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0xa8]
 # CHECK-LE: ldarx 2, 3, 4                   # encoding: [0xa8,0x20,0x43,0x7c]
             ldarx 2, 3, 4
 
-# CHECK-BE: sync 0                          # encoding: [0x7c,0x00,0x04,0xac]
-# CHECK-LE: sync 0                          # encoding: [0xac,0x04,0x00,0x7c]
+# CHECK-BE: lbarx 2, 3, 4, 1                # encoding: [0x7c,0x43,0x20,0x69]
+# CHECK-LE: lbarx 2, 3, 4, 1                # encoding: [0x69,0x20,0x43,0x7c]
+            lbarx 2, 3, 4, 1
+
+# CHECK-BE: lharx 2, 3, 4, 1                # encoding: [0x7c,0x43,0x20,0xe9]
+# CHECK-LE: lharx 2, 3, 4, 1                # encoding: [0xe9,0x20,0x43,0x7c]
+            lharx 2, 3, 4, 1
+
+# CHECK-BE: lwarx 2, 3, 4, 1                # encoding: [0x7c,0x43,0x20,0x29]
+# CHECK-LE: lwarx 2, 3, 4, 1                # encoding: [0x29,0x20,0x43,0x7c]
+            lwarx 2, 3, 4, 1
+
+# CHECK-BE: ldarx 2, 3, 4, 1                # encoding: [0x7c,0x43,0x20,0xa9]
+# CHECK-LE: ldarx 2, 3, 4, 1                # encoding: [0xa9,0x20,0x43,0x7c]
+            ldarx 2, 3, 4, 1
+
+# CHECK-BE: sync                            # encoding: [0x7c,0x00,0x04,0xac]
+# CHECK-LE: sync                            # encoding: [0xac,0x04,0x00,0x7c]
             sync
-# CHECK-BE: sync 0                          # encoding: [0x7c,0x00,0x04,0xac]
-# CHECK-LE: sync 0                          # encoding: [0xac,0x04,0x00,0x7c]
+# CHECK-BE: sync                            # encoding: [0x7c,0x00,0x04,0xac]
+# CHECK-LE: sync                            # encoding: [0xac,0x04,0x00,0x7c]
             msync
-# CHECK-BE: sync 1                          # encoding: [0x7c,0x20,0x04,0xac]
-# CHECK-LE: sync 1                          # encoding: [0xac,0x04,0x20,0x7c]
+# CHECK-BE: lwsync                          # encoding: [0x7c,0x20,0x04,0xac]
+# CHECK-LE: lwsync                          # encoding: [0xac,0x04,0x20,0x7c]
             lwsync
-# CHECK-BE: sync 2                          # encoding: [0x7c,0x40,0x04,0xac]
-# CHECK-LE: sync 2                          # encoding: [0xac,0x04,0x40,0x7c]
+# CHECK-BE: ptesync                         # encoding: [0x7c,0x40,0x04,0xac]
+# CHECK-LE: ptesync                         # encoding: [0xac,0x04,0x40,0x7c]
             ptesync
 
-# CHECK-BE: wait 0                          # encoding: [0x7c,0x00,0x00,0x7c]
-# CHECK-LE: wait 0                          # encoding: [0x7c,0x00,0x00,0x7c]
+# CHECK-BE: wait                            # encoding: [0x7c,0x00,0x00,0x7c]
+# CHECK-LE: wait                            # encoding: [0x7c,0x00,0x00,0x7c]
             wait
-# CHECK-BE: wait 1                          # encoding: [0x7c,0x20,0x00,0x7c]
-# CHECK-LE: wait 1                          # encoding: [0x7c,0x00,0x20,0x7c]
+# CHECK-BE: waitrsv                         # encoding: [0x7c,0x20,0x00,0x7c]
+# CHECK-LE: waitrsv                         # encoding: [0x7c,0x00,0x20,0x7c]
             waitrsv
-# CHECK-BE: wait 2                          # encoding: [0x7c,0x40,0x00,0x7c]
-# CHECK-LE: wait 2                          # encoding: [0x7c,0x00,0x40,0x7c]
+# CHECK-BE: waitimpl                        # encoding: [0x7c,0x40,0x00,0x7c]
+# CHECK-LE: waitimpl                        # encoding: [0x7c,0x00,0x40,0x7c]
             waitimpl
 
 # Time base instructions
@@ -113,13 +165,13 @@
 # CHECK-BE: mftb 2, 268                     # encoding: [0x7c,0x4c,0x42,0xe6]
 # CHECK-LE: mftb 2, 268                     # encoding: [0xe6,0x42,0x4c,0x7c]
             mftbl 2
-# CHECK-BE: mftb 2, 269                     # encoding: [0x7c,0x4d,0x42,0xe6]
-# CHECK-LE: mftb 2, 269                     # encoding: [0xe6,0x42,0x4d,0x7c]
+# CHECK-BE: mftbu 2                         # encoding: [0x7c,0x4d,0x42,0xe6]
+# CHECK-LE: mftbu 2                         # encoding: [0xe6,0x42,0x4d,0x7c]
             mftbu 2
 
-# CHECK-BE: mtspr 284, 3                    # encoding: [0x7c,0x7c,0x43,0xa6]
-# CHECK-LE: mtspr 284, 3                    # encoding: [0xa6,0x43,0x7c,0x7c]
+# CHECK-BE: mttbl 3                         # encoding: [0x7c,0x7c,0x43,0xa6]
+# CHECK-LE: mttbl 3                         # encoding: [0xa6,0x43,0x7c,0x7c]
             mttbl 3
-# CHECK-BE: mtspr 285, 3                    # encoding: [0x7c,0x7d,0x43,0xa6]
-# CHECK-LE: mtspr 285, 3                    # encoding: [0xa6,0x43,0x7d,0x7c]
+# CHECK-BE: mttbu 3                         # encoding: [0x7c,0x7d,0x43,0xa6]
+# CHECK-LE: mttbu 3                         # encoding: [0xa6,0x43,0x7d,0x7c]
             mttbu 3
diff --git a/test/MC/PowerPC/ppc64-encoding-bookIII.s b/test/MC/PowerPC/ppc64-encoding-bookIII.s
index 9e784dbb5e98..d110d4ab6c61 100644
--- a/test/MC/PowerPC/ppc64-encoding-bookIII.s
+++ b/test/MC/PowerPC/ppc64-encoding-bookIII.s
@@ -1,8 +1,8 @@
 # RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
 # RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
 
-# CHECK-BE: mtmsr 4, 0                       # encoding: [0x7c,0x80,0x01,0x24]
-# CHECK-LE: mtmsr 4, 0                       # encoding: [0x24,0x01,0x80,0x7c]
+# CHECK-BE: mtmsr 4                          # encoding: [0x7c,0x80,0x01,0x24]
+# CHECK-LE: mtmsr 4                          # encoding: [0x24,0x01,0x80,0x7c]
             mtmsr %r4
 
 # CHECK-BE: mtmsr 4, 1                       # encoding: [0x7c,0x81,0x01,0x24]
@@ -13,8 +13,8 @@
 # CHECK-LE: mfmsr 4                         # encoding: [0xa6,0x00,0x80,0x7c]
             mfmsr %r4
 
-# CHECK-BE: mtmsrd 4, 0                     # encoding: [0x7c,0x80,0x01,0x64]
-# CHECK-LE: mtmsrd 4, 0                     # encoding: [0x64,0x01,0x80,0x7c]
+# CHECK-BE: mtmsrd 4                        # encoding: [0x7c,0x80,0x01,0x64]
+# CHECK-LE: mtmsrd 4                        # encoding: [0x64,0x01,0x80,0x7c]
             mtmsrd %r4
 
 # CHECK-BE: mtmsrd 4, 1                     # encoding: [0x7c,0x81,0x01,0x64]
@@ -94,8 +94,8 @@
 # CHECK-LE: mtspr 22, 4                     # encoding: [0xa6,0x03,0x96,0x7c]
             mtdec %r4
 
-# CHECK-BE: mfspr 4, 287                    # encoding: [0x7c,0x9f,0x42,0xa6]
-# CHECK-LE: mfspr 4, 287                    # encoding: [0xa6,0x42,0x9f,0x7c]
+# CHECK-BE: mfpvr 4                         # encoding: [0x7c,0x9f,0x42,0xa6]
+# CHECK-LE: mfpvr 4                         # encoding: [0xa6,0x42,0x9f,0x7c]
             mfpvr %r4
 
 # CHECK-BE: mfspr 4, 25                     # encoding: [0x7c,0x99,0x02,0xa6]
@@ -146,12 +146,12 @@
 # CHECK-LE: tlbiel 4                        # encoding: [0x24,0x22,0x00,0x7c]
             tlbiel %r4
 
-# CHECK-BE: tlbie 4,0                       # encoding: [0x7c,0x00,0x22,0x64]
-# CHECK-LE: tlbie 4,0                       # encoding: [0x64,0x22,0x00,0x7c]
+# CHECK-BE: tlbie 4                         # encoding: [0x7c,0x00,0x22,0x64]
+# CHECK-LE: tlbie 4                         # encoding: [0x64,0x22,0x00,0x7c]
             tlbie %r4, 0
 
-# CHECK-BE: tlbie 4,0                       # encoding: [0x7c,0x00,0x22,0x64]
-# CHECK-LE: tlbie 4,0                       # encoding: [0x64,0x22,0x00,0x7c]
+# CHECK-BE: tlbie 4                         # encoding: [0x7c,0x00,0x22,0x64]
+# CHECK-LE: tlbie 4                         # encoding: [0x64,0x22,0x00,0x7c]
             tlbie %r4
 
 # CHECK-BE: rfi                             # encoding: [0x4c,0x00,0x00,0x64]
diff --git a/test/MC/PowerPC/ppc64-encoding-ext.s b/test/MC/PowerPC/ppc64-encoding-ext.s
index dca8a652674f..143a30606f06 100644
--- a/test/MC/PowerPC/ppc64-encoding-ext.s
+++ b/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -29,125 +29,125 @@
 # CHECK-LE: beqlr 7                         # encoding: [0x20,0x00,0x9e,0x4d]
             beqlr cr7
 
-# CHECK-BE: bclr 12, 0, 0                   # encoding: [0x4d,0x80,0x00,0x20]
-# CHECK-LE: bclr 12, 0, 0                   # encoding: [0x20,0x00,0x80,0x4d]
+# CHECK-BE: bclr 12, 0                      # encoding: [0x4d,0x80,0x00,0x20]
+# CHECK-LE: bclr 12, 0                      # encoding: [0x20,0x00,0x80,0x4d]
             btlr 4*cr0+lt
-# CHECK-BE: bclr 12, 1, 0                   # encoding: [0x4d,0x81,0x00,0x20]
-# CHECK-LE: bclr 12, 1, 0                   # encoding: [0x20,0x00,0x81,0x4d]
+# CHECK-BE: bclr 12, 1                      # encoding: [0x4d,0x81,0x00,0x20]
+# CHECK-LE: bclr 12, 1                      # encoding: [0x20,0x00,0x81,0x4d]
             btlr 4*cr0+gt
-# CHECK-BE: bclr 12, 2, 0                   # encoding: [0x4d,0x82,0x00,0x20]
-# CHECK-LE: bclr 12, 2, 0                   # encoding: [0x20,0x00,0x82,0x4d]
+# CHECK-BE: bclr 12, 2                      # encoding: [0x4d,0x82,0x00,0x20]
+# CHECK-LE: bclr 12, 2                      # encoding: [0x20,0x00,0x82,0x4d]
             btlr 4*cr0+eq
-# CHECK-BE: bclr 12, 3, 0                   # encoding: [0x4d,0x83,0x00,0x20]
-# CHECK-LE: bclr 12, 3, 0                   # encoding: [0x20,0x00,0x83,0x4d]
+# CHECK-BE: bclr 12, 3                      # encoding: [0x4d,0x83,0x00,0x20]
+# CHECK-LE: bclr 12, 3                      # encoding: [0x20,0x00,0x83,0x4d]
             btlr 4*cr0+so
-# CHECK-BE: bclr 12, 3, 0                   # encoding: [0x4d,0x83,0x00,0x20]
-# CHECK-LE: bclr 12, 3, 0                   # encoding: [0x20,0x00,0x83,0x4d]
+# CHECK-BE: bclr 12, 3                      # encoding: [0x4d,0x83,0x00,0x20]
+# CHECK-LE: bclr 12, 3                      # encoding: [0x20,0x00,0x83,0x4d]
             btlr 4*cr0+un
-# CHECK-BE: bclr 12, 4, 0                   # encoding: [0x4d,0x84,0x00,0x20]
-# CHECK-LE: bclr 12, 4, 0                   # encoding: [0x20,0x00,0x84,0x4d]
+# CHECK-BE: bclr 12, 4                      # encoding: [0x4d,0x84,0x00,0x20]
+# CHECK-LE: bclr 12, 4                      # encoding: [0x20,0x00,0x84,0x4d]
             btlr 4*cr1+lt
-# CHECK-BE: bclr 12, 5, 0                   # encoding: [0x4d,0x85,0x00,0x20]
-# CHECK-LE: bclr 12, 5, 0                   # encoding: [0x20,0x00,0x85,0x4d]
+# CHECK-BE: bclr 12, 5                      # encoding: [0x4d,0x85,0x00,0x20]
+# CHECK-LE: bclr 12, 5                      # encoding: [0x20,0x00,0x85,0x4d]
             btlr 4*cr1+gt
-# CHECK-BE: bclr 12, 6, 0                   # encoding: [0x4d,0x86,0x00,0x20]
-# CHECK-LE: bclr 12, 6, 0                   # encoding: [0x20,0x00,0x86,0x4d]
+# CHECK-BE: bclr 12, 6                      # encoding: [0x4d,0x86,0x00,0x20]
+# CHECK-LE: bclr 12, 6                      # encoding: [0x20,0x00,0x86,0x4d]
             btlr 4*cr1+eq
-# CHECK-BE: bclr 12, 7, 0                   # encoding: [0x4d,0x87,0x00,0x20]
-# CHECK-LE: bclr 12, 7, 0                   # encoding: [0x20,0x00,0x87,0x4d]
+# CHECK-BE: bclr 12, 7                      # encoding: [0x4d,0x87,0x00,0x20]
+# CHECK-LE: bclr 12, 7                      # encoding: [0x20,0x00,0x87,0x4d]
             btlr 4*cr1+so
-# CHECK-BE: bclr 12, 7, 0                   # encoding: [0x4d,0x87,0x00,0x20]
-# CHECK-LE: bclr 12, 7, 0                   # encoding: [0x20,0x00,0x87,0x4d]
+# CHECK-BE: bclr 12, 7                      # encoding: [0x4d,0x87,0x00,0x20]
+# CHECK-LE: bclr 12, 7                      # encoding: [0x20,0x00,0x87,0x4d]
             btlr 4*cr1+un
-# CHECK-BE: bclr 12, 8, 0                   # encoding: [0x4d,0x88,0x00,0x20]
-# CHECK-LE: bclr 12, 8, 0                   # encoding: [0x20,0x00,0x88,0x4d]
+# CHECK-BE: bclr 12, 8                      # encoding: [0x4d,0x88,0x00,0x20]
+# CHECK-LE: bclr 12, 8                      # encoding: [0x20,0x00,0x88,0x4d]
             btlr 4*cr2+lt
-# CHECK-BE: bclr 12, 9, 0                   # encoding: [0x4d,0x89,0x00,0x20]
-# CHECK-LE: bclr 12, 9, 0                   # encoding: [0x20,0x00,0x89,0x4d]
+# CHECK-BE: bclr 12, 9                      # encoding: [0x4d,0x89,0x00,0x20]
+# CHECK-LE: bclr 12, 9                      # encoding: [0x20,0x00,0x89,0x4d]
             btlr 4*cr2+gt
-# CHECK-BE: bclr 12, 10, 0                  # encoding: [0x4d,0x8a,0x00,0x20]
-# CHECK-LE: bclr 12, 10, 0                  # encoding: [0x20,0x00,0x8a,0x4d]
+# CHECK-BE: bclr 12, 10                     # encoding: [0x4d,0x8a,0x00,0x20]
+# CHECK-LE: bclr 12, 10                     # encoding: [0x20,0x00,0x8a,0x4d]
             btlr 4*cr2+eq
-# CHECK-BE: bclr 12, 11, 0                  # encoding: [0x4d,0x8b,0x00,0x20]
-# CHECK-LE: bclr 12, 11, 0                  # encoding: [0x20,0x00,0x8b,0x4d]
+# CHECK-BE: bclr 12, 11                     # encoding: [0x4d,0x8b,0x00,0x20]
+# CHECK-LE: bclr 12, 11                     # encoding: [0x20,0x00,0x8b,0x4d]
             btlr 4*cr2+so
-# CHECK-BE: bclr 12, 11, 0                  # encoding: [0x4d,0x8b,0x00,0x20]
-# CHECK-LE: bclr 12, 11, 0                  # encoding: [0x20,0x00,0x8b,0x4d]
+# CHECK-BE: bclr 12, 11                     # encoding: [0x4d,0x8b,0x00,0x20]
+# CHECK-LE: bclr 12, 11                     # encoding: [0x20,0x00,0x8b,0x4d]
             btlr 4*cr2+un
-# CHECK-BE: bclr 12, 12, 0                  # encoding: [0x4d,0x8c,0x00,0x20]
-# CHECK-LE: bclr 12, 12, 0                  # encoding: [0x20,0x00,0x8c,0x4d]
+# CHECK-BE: bclr 12, 12                     # encoding: [0x4d,0x8c,0x00,0x20]
+# CHECK-LE: bclr 12, 12                     # encoding: [0x20,0x00,0x8c,0x4d]
             btlr 4*cr3+lt
-# CHECK-BE: bclr 12, 13, 0                  # encoding: [0x4d,0x8d,0x00,0x20]
-# CHECK-LE: bclr 12, 13, 0                  # encoding: [0x20,0x00,0x8d,0x4d]
+# CHECK-BE: bclr 12, 13                     # encoding: [0x4d,0x8d,0x00,0x20]
+# CHECK-LE: bclr 12, 13                     # encoding: [0x20,0x00,0x8d,0x4d]
             btlr 4*cr3+gt
-# CHECK-BE: bclr 12, 14, 0                  # encoding: [0x4d,0x8e,0x00,0x20]
-# CHECK-LE: bclr 12, 14, 0                  # encoding: [0x20,0x00,0x8e,0x4d]
+# CHECK-BE: bclr 12, 14                     # encoding: [0x4d,0x8e,0x00,0x20]
+# CHECK-LE: bclr 12, 14                     # encoding: [0x20,0x00,0x8e,0x4d]
             btlr 4*cr3+eq
-# CHECK-BE: bclr 12, 15, 0                  # encoding: [0x4d,0x8f,0x00,0x20]
-# CHECK-LE: bclr 12, 15, 0                  # encoding: [0x20,0x00,0x8f,0x4d]
+# CHECK-BE: bclr 12, 15                     # encoding: [0x4d,0x8f,0x00,0x20]
+# CHECK-LE: bclr 12, 15                     # encoding: [0x20,0x00,0x8f,0x4d]
             btlr 4*cr3+so
-# CHECK-BE: bclr 12, 15, 0                  # encoding: [0x4d,0x8f,0x00,0x20]
-# CHECK-LE: bclr 12, 15, 0                  # encoding: [0x20,0x00,0x8f,0x4d]
+# CHECK-BE: bclr 12, 15                     # encoding: [0x4d,0x8f,0x00,0x20]
+# CHECK-LE: bclr 12, 15                     # encoding: [0x20,0x00,0x8f,0x4d]
             btlr 4*cr3+un
-# CHECK-BE: bclr 12, 16, 0                  # encoding: [0x4d,0x90,0x00,0x20]
-# CHECK-LE: bclr 12, 16, 0                  # encoding: [0x20,0x00,0x90,0x4d]
+# CHECK-BE: bclr 12, 16                     # encoding: [0x4d,0x90,0x00,0x20]
+# CHECK-LE: bclr 12, 16                     # encoding: [0x20,0x00,0x90,0x4d]
             btlr 4*cr4+lt
-# CHECK-BE: bclr 12, 17, 0                  # encoding: [0x4d,0x91,0x00,0x20]
-# CHECK-LE: bclr 12, 17, 0                  # encoding: [0x20,0x00,0x91,0x4d]
+# CHECK-BE: bclr 12, 17                     # encoding: [0x4d,0x91,0x00,0x20]
+# CHECK-LE: bclr 12, 17                     # encoding: [0x20,0x00,0x91,0x4d]
             btlr 4*cr4+gt
-# CHECK-BE: bclr 12, 18, 0                  # encoding: [0x4d,0x92,0x00,0x20]
-# CHECK-LE: bclr 12, 18, 0                  # encoding: [0x20,0x00,0x92,0x4d]
+# CHECK-BE: bclr 12, 18                     # encoding: [0x4d,0x92,0x00,0x20]
+# CHECK-LE: bclr 12, 18                     # encoding: [0x20,0x00,0x92,0x4d]
             btlr 4*cr4+eq
-# CHECK-BE: bclr 12, 19, 0                  # encoding: [0x4d,0x93,0x00,0x20]
-# CHECK-LE: bclr 12, 19, 0                  # encoding: [0x20,0x00,0x93,0x4d]
+# CHECK-BE: bclr 12, 19                     # encoding: [0x4d,0x93,0x00,0x20]
+# CHECK-LE: bclr 12, 19                     # encoding: [0x20,0x00,0x93,0x4d]
             btlr 4*cr4+so
-# CHECK-BE: bclr 12, 19, 0                  # encoding: [0x4d,0x93,0x00,0x20]
-# CHECK-LE: bclr 12, 19, 0                  # encoding: [0x20,0x00,0x93,0x4d]
+# CHECK-BE: bclr 12, 19                     # encoding: [0x4d,0x93,0x00,0x20]
+# CHECK-LE: bclr 12, 19                     # encoding: [0x20,0x00,0x93,0x4d]
             btlr 4*cr4+un
-# CHECK-BE: bclr 12, 20, 0                  # encoding: [0x4d,0x94,0x00,0x20]
-# CHECK-LE: bclr 12, 20, 0                  # encoding: [0x20,0x00,0x94,0x4d]
+# CHECK-BE: bclr 12, 20                     # encoding: [0x4d,0x94,0x00,0x20]
+# CHECK-LE: bclr 12, 20                     # encoding: [0x20,0x00,0x94,0x4d]
             btlr 4*cr5+lt
-# CHECK-BE: bclr 12, 21, 0                  # encoding: [0x4d,0x95,0x00,0x20]
-# CHECK-LE: bclr 12, 21, 0                  # encoding: [0x20,0x00,0x95,0x4d]
+# CHECK-BE: bclr 12, 21                     # encoding: [0x4d,0x95,0x00,0x20]
+# CHECK-LE: bclr 12, 21                     # encoding: [0x20,0x00,0x95,0x4d]
             btlr 4*cr5+gt
-# CHECK-BE: bclr 12, 22, 0                  # encoding: [0x4d,0x96,0x00,0x20]
-# CHECK-LE: bclr 12, 22, 0                  # encoding: [0x20,0x00,0x96,0x4d]
+# CHECK-BE: bclr 12, 22                     # encoding: [0x4d,0x96,0x00,0x20]
+# CHECK-LE: bclr 12, 22                     # encoding: [0x20,0x00,0x96,0x4d]
             btlr 4*cr5+eq
-# CHECK-BE: bclr 12, 23, 0                  # encoding: [0x4d,0x97,0x00,0x20]
-# CHECK-LE: bclr 12, 23, 0                  # encoding: [0x20,0x00,0x97,0x4d]
+# CHECK-BE: bclr 12, 23                     # encoding: [0x4d,0x97,0x00,0x20]
+# CHECK-LE: bclr 12, 23                     # encoding: [0x20,0x00,0x97,0x4d]
             btlr 4*cr5+so
-# CHECK-BE: bclr 12, 23, 0                  # encoding: [0x4d,0x97,0x00,0x20]
-# CHECK-LE: bclr 12, 23, 0                  # encoding: [0x20,0x00,0x97,0x4d]
+# CHECK-BE: bclr 12, 23                     # encoding: [0x4d,0x97,0x00,0x20]
+# CHECK-LE: bclr 12, 23                     # encoding: [0x20,0x00,0x97,0x4d]
             btlr 4*cr5+un
-# CHECK-BE: bclr 12, 24, 0                  # encoding: [0x4d,0x98,0x00,0x20]
-# CHECK-LE: bclr 12, 24, 0                  # encoding: [0x20,0x00,0x98,0x4d]
+# CHECK-BE: bclr 12, 24                     # encoding: [0x4d,0x98,0x00,0x20]
+# CHECK-LE: bclr 12, 24                     # encoding: [0x20,0x00,0x98,0x4d]
             btlr 4*cr6+lt
-# CHECK-BE: bclr 12, 25, 0                  # encoding: [0x4d,0x99,0x00,0x20]
-# CHECK-LE: bclr 12, 25, 0                  # encoding: [0x20,0x00,0x99,0x4d]
+# CHECK-BE: bclr 12, 25                     # encoding: [0x4d,0x99,0x00,0x20]
+# CHECK-LE: bclr 12, 25                     # encoding: [0x20,0x00,0x99,0x4d]
             btlr 4*cr6+gt
-# CHECK-BE: bclr 12, 26, 0                  # encoding: [0x4d,0x9a,0x00,0x20]
-# CHECK-LE: bclr 12, 26, 0                  # encoding: [0x20,0x00,0x9a,0x4d]
+# CHECK-BE: bclr 12, 26                     # encoding: [0x4d,0x9a,0x00,0x20]
+# CHECK-LE: bclr 12, 26                     # encoding: [0x20,0x00,0x9a,0x4d]
             btlr 4*cr6+eq
-# CHECK-BE: bclr 12, 27, 0                  # encoding: [0x4d,0x9b,0x00,0x20]
-# CHECK-LE: bclr 12, 27, 0                  # encoding: [0x20,0x00,0x9b,0x4d]
+# CHECK-BE: bclr 12, 27                     # encoding: [0x4d,0x9b,0x00,0x20]
+# CHECK-LE: bclr 12, 27                     # encoding: [0x20,0x00,0x9b,0x4d]
             btlr 4*cr6+so
-# CHECK-BE: bclr 12, 27, 0                  # encoding: [0x4d,0x9b,0x00,0x20]
-# CHECK-LE: bclr 12, 27, 0                  # encoding: [0x20,0x00,0x9b,0x4d]
+# CHECK-BE: bclr 12, 27                     # encoding: [0x4d,0x9b,0x00,0x20]
+# CHECK-LE: bclr 12, 27                     # encoding: [0x20,0x00,0x9b,0x4d]
             btlr 4*cr6+un
-# CHECK-BE: bclr 12, 28, 0                  # encoding: [0x4d,0x9c,0x00,0x20]
-# CHECK-LE: bclr 12, 28, 0                  # encoding: [0x20,0x00,0x9c,0x4d]
+# CHECK-BE: bclr 12, 28                     # encoding: [0x4d,0x9c,0x00,0x20]
+# CHECK-LE: bclr 12, 28                     # encoding: [0x20,0x00,0x9c,0x4d]
             btlr 4*cr7+lt
-# CHECK-BE: bclr 12, 29, 0                  # encoding: [0x4d,0x9d,0x00,0x20]
-# CHECK-LE: bclr 12, 29, 0                  # encoding: [0x20,0x00,0x9d,0x4d]
+# CHECK-BE: bclr 12, 29                     # encoding: [0x4d,0x9d,0x00,0x20]
+# CHECK-LE: bclr 12, 29                     # encoding: [0x20,0x00,0x9d,0x4d]
             btlr 4*cr7+gt
-# CHECK-BE: bclr 12, 30, 0                  # encoding: [0x4d,0x9e,0x00,0x20]
-# CHECK-LE: bclr 12, 30, 0                  # encoding: [0x20,0x00,0x9e,0x4d]
+# CHECK-BE: bclr 12, 30                     # encoding: [0x4d,0x9e,0x00,0x20]
+# CHECK-LE: bclr 12, 30                     # encoding: [0x20,0x00,0x9e,0x4d]
             btlr 4*cr7+eq
-# CHECK-BE: bclr 12, 31, 0                  # encoding: [0x4d,0x9f,0x00,0x20]
-# CHECK-LE: bclr 12, 31, 0                  # encoding: [0x20,0x00,0x9f,0x4d]
+# CHECK-BE: bclr 12, 31                     # encoding: [0x4d,0x9f,0x00,0x20]
+# CHECK-LE: bclr 12, 31                     # encoding: [0x20,0x00,0x9f,0x4d]
             btlr 4*cr7+so
-# CHECK-BE: bclr 12, 31, 0                  # encoding: [0x4d,0x9f,0x00,0x20]
-# CHECK-LE: bclr 12, 31, 0                  # encoding: [0x20,0x00,0x9f,0x4d]
+# CHECK-BE: bclr 12, 31                     # encoding: [0x4d,0x9f,0x00,0x20]
+# CHECK-LE: bclr 12, 31                     # encoding: [0x20,0x00,0x9f,0x4d]
             btlr 4*cr7+un
 
 # Branch mnemonics
@@ -165,202 +165,202 @@
 # CHECK-LE: bctrl                           # encoding: [0x21,0x04,0x80,0x4e]
             bctrl
 
-# CHECK-BE: bc 12, 2, target                # encoding: [0x41,0x82,A,0bAAAAAA00]
-# CHECK-LE: bc 12, 2, target                # encoding: [0bAAAAAA00,A,0x82,0x41]
+# CHECK-BE: bt 2, target                    # encoding: [0x41,0x82,A,0bAAAAAA00]
+# CHECK-LE: bt 2, target                    # encoding: [0bAAAAAA00,A,0x82,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bt 2, target
-# CHECK-BE: bca 12, 2, target               # encoding: [0x41,0x82,A,0bAAAAAA10]
-# CHECK-LE: bca 12, 2, target               # encoding: [0bAAAAAA10,A,0x82,0x41]
+# CHECK-BE: bta 2, target                   # encoding: [0x41,0x82,A,0bAAAAAA10]
+# CHECK-LE: bta 2, target                   # encoding: [0bAAAAAA10,A,0x82,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bta 2, target
-# CHECK-BE: bclr 12, 2, 0                   # encoding: [0x4d,0x82,0x00,0x20]
-# CHECK-LE: bclr 12, 2, 0                   # encoding: [0x20,0x00,0x82,0x4d]
+# CHECK-BE: bclr 12, 2                      # encoding: [0x4d,0x82,0x00,0x20]
+# CHECK-LE: bclr 12, 2                      # encoding: [0x20,0x00,0x82,0x4d]
             btlr 2
-# CHECK-BE: bcctr 12, 2, 0                  # encoding: [0x4d,0x82,0x04,0x20]
-# CHECK-LE: bcctr 12, 2, 0                  # encoding: [0x20,0x04,0x82,0x4d]
+# CHECK-BE: bcctr 12, 2                     # encoding: [0x4d,0x82,0x04,0x20]
+# CHECK-LE: bcctr 12, 2                     # encoding: [0x20,0x04,0x82,0x4d]
             btctr 2
-# CHECK-BE: bcl 12, 2, target               # encoding: [0x41,0x82,A,0bAAAAAA01]
-# CHECK-LE: bcl 12, 2, target               # encoding: [0bAAAAAA01,A,0x82,0x41]
+# CHECK-BE: btl 2, target                   # encoding: [0x41,0x82,A,0bAAAAAA01]
+# CHECK-LE: btl 2, target                   # encoding: [0bAAAAAA01,A,0x82,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             btl 2, target
-# CHECK-BE: bcla 12, 2, target              # encoding: [0x41,0x82,A,0bAAAAAA11]
-# CHECK-LE: bcla 12, 2, target              # encoding: [0bAAAAAA11,A,0x82,0x41]
+# CHECK-BE: btla 2, target                  # encoding: [0x41,0x82,A,0bAAAAAA11]
+# CHECK-LE: btla 2, target                  # encoding: [0bAAAAAA11,A,0x82,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             btla 2, target
-# CHECK-BE: bclrl 12, 2, 0                  # encoding: [0x4d,0x82,0x00,0x21]
-# CHECK-LE: bclrl 12, 2, 0                  # encoding: [0x21,0x00,0x82,0x4d]
+# CHECK-BE: bclrl 12, 2                     # encoding: [0x4d,0x82,0x00,0x21]
+# CHECK-LE: bclrl 12, 2                     # encoding: [0x21,0x00,0x82,0x4d]
             btlrl 2
-# CHECK-BE: bcctrl 12, 2, 0                 # encoding: [0x4d,0x82,0x04,0x21]
-# CHECK-LE: bcctrl 12, 2, 0                 # encoding: [0x21,0x04,0x82,0x4d]
+# CHECK-BE: bcctrl 12, 2                    # encoding: [0x4d,0x82,0x04,0x21]
+# CHECK-LE: bcctrl 12, 2                    # encoding: [0x21,0x04,0x82,0x4d]
             btctrl 2
 
-# CHECK-BE: bc 15, 2, target                # encoding: [0x41,0xe2,A,0bAAAAAA00]
-# CHECK-LE: bc 15, 2, target                # encoding: [0bAAAAAA00,A,0xe2,0x41]
+# CHECK-BE: bt+ 2, target                   # encoding: [0x41,0xe2,A,0bAAAAAA00]
+# CHECK-LE: bt+ 2, target                   # encoding: [0bAAAAAA00,A,0xe2,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bt+ 2, target
-# CHECK-BE: bca 15, 2, target               # encoding: [0x41,0xe2,A,0bAAAAAA10]
-# CHECK-LE: bca 15, 2, target               # encoding: [0bAAAAAA10,A,0xe2,0x41]
+# CHECK-BE: bta+ 2, target                  # encoding: [0x41,0xe2,A,0bAAAAAA10]
+# CHECK-LE: bta+ 2, target                  # encoding: [0bAAAAAA10,A,0xe2,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bta+ 2, target
-# CHECK-BE: bclr 15, 2, 0                   # encoding: [0x4d,0xe2,0x00,0x20]
-# CHECK-LE: bclr 15, 2, 0                   # encoding: [0x20,0x00,0xe2,0x4d]
+# CHECK-BE: bclr 15, 2                      # encoding: [0x4d,0xe2,0x00,0x20]
+# CHECK-LE: bclr 15, 2                      # encoding: [0x20,0x00,0xe2,0x4d]
             btlr+ 2
-# CHECK-BE: bcctr 15, 2, 0                  # encoding: [0x4d,0xe2,0x04,0x20]
-# CHECK-LE: bcctr 15, 2, 0                  # encoding: [0x20,0x04,0xe2,0x4d]
+# CHECK-BE: bcctr 15, 2                     # encoding: [0x4d,0xe2,0x04,0x20]
+# CHECK-LE: bcctr 15, 2                     # encoding: [0x20,0x04,0xe2,0x4d]
             btctr+ 2
-# CHECK-BE: bcl 15, 2, target               # encoding: [0x41,0xe2,A,0bAAAAAA01]
-# CHECK-LE: bcl 15, 2, target               # encoding: [0bAAAAAA01,A,0xe2,0x41]
+# CHECK-BE: btl+ 2, target                  # encoding: [0x41,0xe2,A,0bAAAAAA01]
+# CHECK-LE: btl+ 2, target                  # encoding: [0bAAAAAA01,A,0xe2,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             btl+ 2, target
-# CHECK-BE: bcla 15, 2, target              # encoding: [0x41,0xe2,A,0bAAAAAA11]
-# CHECK-LE: bcla 15, 2, target              # encoding: [0bAAAAAA11,A,0xe2,0x41]
+# CHECK-BE: btla+ 2, target                 # encoding: [0x41,0xe2,A,0bAAAAAA11]
+# CHECK-LE: btla+ 2, target                 # encoding: [0bAAAAAA11,A,0xe2,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             btla+ 2, target
-# CHECK-BE: bclrl 15, 2, 0                  # encoding: [0x4d,0xe2,0x00,0x21]
-# CHECK-LE: bclrl 15, 2, 0                  # encoding: [0x21,0x00,0xe2,0x4d]
+# CHECK-BE: bclrl 15, 2                     # encoding: [0x4d,0xe2,0x00,0x21]
+# CHECK-LE: bclrl 15, 2                     # encoding: [0x21,0x00,0xe2,0x4d]
             btlrl+ 2
-# CHECK-BE: bcctrl 15, 2, 0                 # encoding: [0x4d,0xe2,0x04,0x21]
-# CHECK-LE: bcctrl 15, 2, 0                 # encoding: [0x21,0x04,0xe2,0x4d]
+# CHECK-BE: bcctrl 15, 2                    # encoding: [0x4d,0xe2,0x04,0x21]
+# CHECK-LE: bcctrl 15, 2                    # encoding: [0x21,0x04,0xe2,0x4d]
             btctrl+ 2
 
-# CHECK-BE: bc 14, 2, target                # encoding: [0x41,0xc2,A,0bAAAAAA00]
-# CHECK-LE: bc 14, 2, target                # encoding: [0bAAAAAA00,A,0xc2,0x41]
+# CHECK-BE: bt- 2, target                   # encoding: [0x41,0xc2,A,0bAAAAAA00]
+# CHECK-LE: bt- 2, target                   # encoding: [0bAAAAAA00,A,0xc2,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bt- 2, target
-# CHECK-BE: bca 14, 2, target               # encoding: [0x41,0xc2,A,0bAAAAAA10]
-# CHECK-LE: bca 14, 2, target               # encoding: [0bAAAAAA10,A,0xc2,0x41]
+# CHECK-BE: bta- 2, target                  # encoding: [0x41,0xc2,A,0bAAAAAA10]
+# CHECK-LE: bta- 2, target                  # encoding: [0bAAAAAA10,A,0xc2,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bta- 2, target
-# CHECK-BE: bclr 14, 2, 0                   # encoding: [0x4d,0xc2,0x00,0x20]
-# CHECK-LE: bclr 14, 2, 0                   # encoding: [0x20,0x00,0xc2,0x4d]
+# CHECK-BE: bclr 14, 2                      # encoding: [0x4d,0xc2,0x00,0x20]
+# CHECK-LE: bclr 14, 2                      # encoding: [0x20,0x00,0xc2,0x4d]
             btlr- 2
-# CHECK-BE: bcctr 14, 2, 0                  # encoding: [0x4d,0xc2,0x04,0x20]
-# CHECK-LE: bcctr 14, 2, 0                  # encoding: [0x20,0x04,0xc2,0x4d]
+# CHECK-BE: bcctr 14, 2                     # encoding: [0x4d,0xc2,0x04,0x20]
+# CHECK-LE: bcctr 14, 2                     # encoding: [0x20,0x04,0xc2,0x4d]
             btctr- 2
-# CHECK-BE: bcl 14, 2, target               # encoding: [0x41,0xc2,A,0bAAAAAA01]
-# CHECK-LE: bcl 14, 2, target               # encoding: [0bAAAAAA01,A,0xc2,0x41]
+# CHECK-BE: btl- 2, target                  # encoding: [0x41,0xc2,A,0bAAAAAA01]
+# CHECK-LE: btl- 2, target                  # encoding: [0bAAAAAA01,A,0xc2,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             btl- 2, target
-# CHECK-BE: bcla 14, 2, target              # encoding: [0x41,0xc2,A,0bAAAAAA11]
-# CHECK-LE: bcla 14, 2, target              # encoding: [0bAAAAAA11,A,0xc2,0x41]
+# CHECK-BE: btla- 2, target                 # encoding: [0x41,0xc2,A,0bAAAAAA11]
+# CHECK-LE: btla- 2, target                 # encoding: [0bAAAAAA11,A,0xc2,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             btla- 2, target
-# CHECK-BE: bclrl 14, 2, 0                  # encoding: [0x4d,0xc2,0x00,0x21]
-# CHECK-LE: bclrl 14, 2, 0                  # encoding: [0x21,0x00,0xc2,0x4d]
+# CHECK-BE: bclrl 14, 2                     # encoding: [0x4d,0xc2,0x00,0x21]
+# CHECK-LE: bclrl 14, 2                     # encoding: [0x21,0x00,0xc2,0x4d]
             btlrl- 2
-# CHECK-BE: bcctrl 14, 2, 0                 # encoding: [0x4d,0xc2,0x04,0x21]
-# CHECK-LE: bcctrl 14, 2, 0                 # encoding: [0x21,0x04,0xc2,0x4d]
+# CHECK-BE: bcctrl 14, 2                    # encoding: [0x4d,0xc2,0x04,0x21]
+# CHECK-LE: bcctrl 14, 2                    # encoding: [0x21,0x04,0xc2,0x4d]
             btctrl- 2
 
-# CHECK-BE: bc 4, 2, target                 # encoding: [0x40,0x82,A,0bAAAAAA00]
-# CHECK-LE: bc 4, 2, target                 # encoding: [0bAAAAAA00,A,0x82,0x40]
+# CHECK-BE: bf 2, target                    # encoding: [0x40,0x82,A,0bAAAAAA00]
+# CHECK-LE: bf 2, target                    # encoding: [0bAAAAAA00,A,0x82,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bf 2, target
-# CHECK-BE: bca 4, 2, target                # encoding: [0x40,0x82,A,0bAAAAAA10]
-# CHECK-LE: bca 4, 2, target                # encoding: [0bAAAAAA10,A,0x82,0x40]
+# CHECK-BE: bfa 2, target                   # encoding: [0x40,0x82,A,0bAAAAAA10]
+# CHECK-LE: bfa 2, target                   # encoding: [0bAAAAAA10,A,0x82,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bfa 2, target
-# CHECK-BE: bclr 4, 2, 0                    # encoding: [0x4c,0x82,0x00,0x20]
-# CHECK-LE: bclr 4, 2, 0                    # encoding: [0x20,0x00,0x82,0x4c]
+# CHECK-BE: bclr 4, 2                       # encoding: [0x4c,0x82,0x00,0x20]
+# CHECK-LE: bclr 4, 2                       # encoding: [0x20,0x00,0x82,0x4c]
             bflr 2
-# CHECK-BE: bcctr 4, 2, 0                   # encoding: [0x4c,0x82,0x04,0x20]
-# CHECK-LE: bcctr 4, 2, 0                   # encoding: [0x20,0x04,0x82,0x4c]
+# CHECK-BE: bcctr 4, 2                      # encoding: [0x4c,0x82,0x04,0x20]
+# CHECK-LE: bcctr 4, 2                      # encoding: [0x20,0x04,0x82,0x4c]
             bfctr 2
-# CHECK-BE: bcl 4, 2, target                # encoding: [0x40,0x82,A,0bAAAAAA01]
-# CHECK-LE: bcl 4, 2, target                # encoding: [0bAAAAAA01,A,0x82,0x40]
+# CHECK-BE: bfl 2, target                   # encoding: [0x40,0x82,A,0bAAAAAA01]
+# CHECK-LE: bfl 2, target                   # encoding: [0bAAAAAA01,A,0x82,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bfl 2, target
-# CHECK-BE: bcla 4, 2, target               # encoding: [0x40,0x82,A,0bAAAAAA11]
-# CHECK-LE: bcla 4, 2, target               # encoding: [0bAAAAAA11,A,0x82,0x40]
+# CHECK-BE: bfla 2, target                  # encoding: [0x40,0x82,A,0bAAAAAA11]
+# CHECK-LE: bfla 2, target                  # encoding: [0bAAAAAA11,A,0x82,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bfla 2, target
-# CHECK-BE: bclrl 4, 2, 0                   # encoding: [0x4c,0x82,0x00,0x21]
-# CHECK-LE: bclrl 4, 2, 0                   # encoding: [0x21,0x00,0x82,0x4c]
+# CHECK-BE: bclrl 4, 2                      # encoding: [0x4c,0x82,0x00,0x21]
+# CHECK-LE: bclrl 4, 2                      # encoding: [0x21,0x00,0x82,0x4c]
             bflrl 2
-# CHECK-BE: bcctrl 4, 2, 0                  # encoding: [0x4c,0x82,0x04,0x21]
-# CHECK-LE: bcctrl 4, 2, 0                  # encoding: [0x21,0x04,0x82,0x4c]
+# CHECK-BE: bcctrl 4, 2                     # encoding: [0x4c,0x82,0x04,0x21]
+# CHECK-LE: bcctrl 4, 2                     # encoding: [0x21,0x04,0x82,0x4c]
             bfctrl 2
 
-# CHECK-BE: bc 7, 2, target                 # encoding: [0x40,0xe2,A,0bAAAAAA00]
-# CHECK-LE: bc 7, 2, target                 # encoding: [0bAAAAAA00,A,0xe2,0x40]
+# CHECK-BE: bf+ 2, target                   # encoding: [0x40,0xe2,A,0bAAAAAA00]
+# CHECK-LE: bf+ 2, target                   # encoding: [0bAAAAAA00,A,0xe2,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bf+ 2, target
-# CHECK-BE: bca 7, 2, target                # encoding: [0x40,0xe2,A,0bAAAAAA10]
-# CHECK-LE: bca 7, 2, target                # encoding: [0bAAAAAA10,A,0xe2,0x40]
+# CHECK-BE: bfa+ 2, target                  # encoding: [0x40,0xe2,A,0bAAAAAA10]
+# CHECK-LE: bfa+ 2, target                  # encoding: [0bAAAAAA10,A,0xe2,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bfa+ 2, target
-# CHECK-BE: bclr 7, 2, 0                    # encoding: [0x4c,0xe2,0x00,0x20]
-# CHECK-LE: bclr 7, 2, 0                    # encoding: [0x20,0x00,0xe2,0x4c]
+# CHECK-BE: bclr 7, 2                       # encoding: [0x4c,0xe2,0x00,0x20]
+# CHECK-LE: bclr 7, 2                       # encoding: [0x20,0x00,0xe2,0x4c]
             bflr+ 2
-# CHECK-BE: bcctr 7, 2, 0                   # encoding: [0x4c,0xe2,0x04,0x20]
-# CHECK-LE: bcctr 7, 2, 0                   # encoding: [0x20,0x04,0xe2,0x4c]
+# CHECK-BE: bcctr 7, 2                      # encoding: [0x4c,0xe2,0x04,0x20]
+# CHECK-LE: bcctr 7, 2                      # encoding: [0x20,0x04,0xe2,0x4c]
             bfctr+ 2
-# CHECK-BE: bcl 7, 2, target                # encoding: [0x40,0xe2,A,0bAAAAAA01]
-# CHECK-LE: bcl 7, 2, target                # encoding: [0bAAAAAA01,A,0xe2,0x40]
+# CHECK-BE: bfl+ 2, target                  # encoding: [0x40,0xe2,A,0bAAAAAA01]
+# CHECK-LE: bfl+ 2, target                  # encoding: [0bAAAAAA01,A,0xe2,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bfl+ 2, target
-# CHECK-BE: bcla 7, 2, target               # encoding: [0x40,0xe2,A,0bAAAAAA11]
-# CHECK-LE: bcla 7, 2, target               # encoding: [0bAAAAAA11,A,0xe2,0x40]
+# CHECK-BE: bfla+ 2, target                 # encoding: [0x40,0xe2,A,0bAAAAAA11]
+# CHECK-LE: bfla+ 2, target                 # encoding: [0bAAAAAA11,A,0xe2,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bfla+ 2, target
-# CHECK-BE: bclrl 7, 2, 0                   # encoding: [0x4c,0xe2,0x00,0x21]
-# CHECK-LE: bclrl 7, 2, 0                   # encoding: [0x21,0x00,0xe2,0x4c]
+# CHECK-BE: bclrl 7, 2                      # encoding: [0x4c,0xe2,0x00,0x21]
+# CHECK-LE: bclrl 7, 2                      # encoding: [0x21,0x00,0xe2,0x4c]
             bflrl+ 2
-# CHECK-BE: bcctrl 7, 2, 0                  # encoding: [0x4c,0xe2,0x04,0x21]
-# CHECK-LE: bcctrl 7, 2, 0                  # encoding: [0x21,0x04,0xe2,0x4c]
+# CHECK-BE: bcctrl 7, 2                     # encoding: [0x4c,0xe2,0x04,0x21]
+# CHECK-LE: bcctrl 7, 2                     # encoding: [0x21,0x04,0xe2,0x4c]
             bfctrl+ 2
 
-# CHECK-BE: bc 6, 2, target                 # encoding: [0x40,0xc2,A,0bAAAAAA00]
-# CHECK-LE: bc 6, 2, target                 # encoding: [0bAAAAAA00,A,0xc2,0x40]
+# CHECK-BE: bf- 2, target                   # encoding: [0x40,0xc2,A,0bAAAAAA00]
+# CHECK-LE: bf- 2, target                   # encoding: [0bAAAAAA00,A,0xc2,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bf- 2, target
-# CHECK-BE: bca 6, 2, target                # encoding: [0x40,0xc2,A,0bAAAAAA10]
-# CHECK-LE: bca 6, 2, target                # encoding: [0bAAAAAA10,A,0xc2,0x40]
+# CHECK-BE: bfa- 2, target                  # encoding: [0x40,0xc2,A,0bAAAAAA10]
+# CHECK-LE: bfa- 2, target                  # encoding: [0bAAAAAA10,A,0xc2,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bfa- 2, target
-# CHECK-BE: bclr 6, 2, 0                    # encoding: [0x4c,0xc2,0x00,0x20]
-# CHECK-LE: bclr 6, 2, 0                    # encoding: [0x20,0x00,0xc2,0x4c]
+# CHECK-BE: bclr 6, 2                       # encoding: [0x4c,0xc2,0x00,0x20]
+# CHECK-LE: bclr 6, 2                       # encoding: [0x20,0x00,0xc2,0x4c]
             bflr- 2
-# CHECK-BE: bcctr 6, 2, 0                   # encoding: [0x4c,0xc2,0x04,0x20]
-# CHECK-LE: bcctr 6, 2, 0                   # encoding: [0x20,0x04,0xc2,0x4c]
+# CHECK-BE: bcctr 6, 2                      # encoding: [0x4c,0xc2,0x04,0x20]
+# CHECK-LE: bcctr 6, 2                      # encoding: [0x20,0x04,0xc2,0x4c]
             bfctr- 2
-# CHECK-BE: bcl 6, 2, target                # encoding: [0x40,0xc2,A,0bAAAAAA01]
-# CHECK-LE: bcl 6, 2, target                # encoding: [0bAAAAAA01,A,0xc2,0x40]
+# CHECK-BE: bfl- 2, target                  # encoding: [0x40,0xc2,A,0bAAAAAA01]
+# CHECK-LE: bfl- 2, target                  # encoding: [0bAAAAAA01,A,0xc2,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bfl- 2, target
-# CHECK-BE: bcla 6, 2, target               # encoding: [0x40,0xc2,A,0bAAAAAA11]
-# CHECK-LE: bcla 6, 2, target               # encoding: [0bAAAAAA11,A,0xc2,0x40]
+# CHECK-BE: bfla- 2, target                 # encoding: [0x40,0xc2,A,0bAAAAAA11]
+# CHECK-LE: bfla- 2, target                 # encoding: [0bAAAAAA11,A,0xc2,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bfla- 2, target
-# CHECK-BE: bclrl 6, 2, 0                   # encoding: [0x4c,0xc2,0x00,0x21]
-# CHECK-LE: bclrl 6, 2, 0                   # encoding: [0x21,0x00,0xc2,0x4c]
+# CHECK-BE: bclrl 6, 2                      # encoding: [0x4c,0xc2,0x00,0x21]
+# CHECK-LE: bclrl 6, 2                      # encoding: [0x21,0x00,0xc2,0x4c]
             bflrl- 2
-# CHECK-BE: bcctrl 6, 2, 0                  # encoding: [0x4c,0xc2,0x04,0x21]
-# CHECK-LE: bcctrl 6, 2, 0                  # encoding: [0x21,0x04,0xc2,0x4c]
+# CHECK-BE: bcctrl 6, 2                     # encoding: [0x4c,0xc2,0x04,0x21]
+# CHECK-LE: bcctrl 6, 2                     # encoding: [0x21,0x04,0xc2,0x4c]
             bfctrl- 2
 
 # CHECK-BE: bdnz target                     # encoding: [0x42,0x00,A,0bAAAAAA00]
@@ -444,58 +444,58 @@
 # CHECK-LE: bdnzlrl-                        # encoding: [0x21,0x00,0x00,0x4f]
             bdnzlrl-
 
-# CHECK-BE: bc 8, 2, target                 # encoding: [0x41,0x02,A,0bAAAAAA00]
-# CHECK-LE: bc 8, 2, target                 # encoding: [0bAAAAAA00,A,0x02,0x41]
+# CHECK-BE: bdnzt 2, target                 # encoding: [0x41,0x02,A,0bAAAAAA00]
+# CHECK-LE: bdnzt 2, target                 # encoding: [0bAAAAAA00,A,0x02,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bdnzt 2, target
-# CHECK-BE: bca 8, 2, target                # encoding: [0x41,0x02,A,0bAAAAAA10]
-# CHECK-LE: bca 8, 2, target                # encoding: [0bAAAAAA10,A,0x02,0x41]
+# CHECK-BE: bdnzta 2, target                # encoding: [0x41,0x02,A,0bAAAAAA10]
+# CHECK-LE: bdnzta 2, target                # encoding: [0bAAAAAA10,A,0x02,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bdnzta 2, target
-# CHECK-BE: bclr 8, 2, 0                    # encoding: [0x4d,0x02,0x00,0x20]
-# CHECK-LE: bclr 8, 2, 0                    # encoding: [0x20,0x00,0x02,0x4d]
+# CHECK-BE: bclr 8, 2                       # encoding: [0x4d,0x02,0x00,0x20]
+# CHECK-LE: bclr 8, 2                       # encoding: [0x20,0x00,0x02,0x4d]
             bdnztlr 2
-# CHECK-BE: bcl 8, 2, target                # encoding: [0x41,0x02,A,0bAAAAAA01]
-# CHECK-LE: bcl 8, 2, target                # encoding: [0bAAAAAA01,A,0x02,0x41]
+# CHECK-BE: bdnztl 2, target                # encoding: [0x41,0x02,A,0bAAAAAA01]
+# CHECK-LE: bdnztl 2, target                # encoding: [0bAAAAAA01,A,0x02,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bdnztl 2, target
-# CHECK-BE: bcla 8, 2, target               # encoding: [0x41,0x02,A,0bAAAAAA11]
-# CHECK-LE: bcla 8, 2, target               # encoding: [0bAAAAAA11,A,0x02,0x41]
+# CHECK-BE: bdnztla 2, target               # encoding: [0x41,0x02,A,0bAAAAAA11]
+# CHECK-LE: bdnztla 2, target               # encoding: [0bAAAAAA11,A,0x02,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bdnztla 2, target
-# CHECK-BE: bclrl 8, 2, 0                   # encoding: [0x4d,0x02,0x00,0x21]
-# CHECK-LE: bclrl 8, 2, 0                   # encoding: [0x21,0x00,0x02,0x4d]
+# CHECK-BE: bclrl 8, 2                      # encoding: [0x4d,0x02,0x00,0x21]
+# CHECK-LE: bclrl 8, 2                      # encoding: [0x21,0x00,0x02,0x4d]
             bdnztlrl 2
 
-# CHECK-BE: bc 0, 2, target                 # encoding: [0x40,0x02,A,0bAAAAAA00]
-# CHECK-LE: bc 0, 2, target                 # encoding: [0bAAAAAA00,A,0x02,0x40]
+# CHECK-BE: bdnzf 2, target                 # encoding: [0x40,0x02,A,0bAAAAAA00]
+# CHECK-LE: bdnzf 2, target                 # encoding: [0bAAAAAA00,A,0x02,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bdnzf 2, target
-# CHECK-BE: bca 0, 2, target                # encoding: [0x40,0x02,A,0bAAAAAA10]
-# CHECK-LE: bca 0, 2, target                # encoding: [0bAAAAAA10,A,0x02,0x40]
+# CHECK-BE: bdnzfa 2, target                # encoding: [0x40,0x02,A,0bAAAAAA10]
+# CHECK-LE: bdnzfa 2, target                # encoding: [0bAAAAAA10,A,0x02,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bdnzfa 2, target
-# CHECK-BE: bclr 0, 2, 0                    # encoding: [0x4c,0x02,0x00,0x20]
-# CHECK-LE: bclr 0, 2, 0                    # encoding: [0x20,0x00,0x02,0x4c]
+# CHECK-BE: bclr 0, 2                       # encoding: [0x4c,0x02,0x00,0x20]
+# CHECK-LE: bclr 0, 2                       # encoding: [0x20,0x00,0x02,0x4c]
             bdnzflr 2
-# CHECK-BE: bcl 0, 2, target                # encoding: [0x40,0x02,A,0bAAAAAA01]
-# CHECK-LE: bcl 0, 2, target                # encoding: [0bAAAAAA01,A,0x02,0x40]
+# CHECK-BE: bdnzfl 2, target                # encoding: [0x40,0x02,A,0bAAAAAA01]
+# CHECK-LE: bdnzfl 2, target                # encoding: [0bAAAAAA01,A,0x02,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bdnzfl 2, target
-# CHECK-BE: bcla 0, 2, target               # encoding: [0x40,0x02,A,0bAAAAAA11]
-# CHECK-LE: bcla 0, 2, target               # encoding: [0bAAAAAA11,A,0x02,0x40]
+# CHECK-BE: bdnzfla 2, target               # encoding: [0x40,0x02,A,0bAAAAAA11]
+# CHECK-LE: bdnzfla 2, target               # encoding: [0bAAAAAA11,A,0x02,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bdnzfla 2, target
-# CHECK-BE: bclrl 0, 2, 0                   # encoding: [0x4c,0x02,0x00,0x21]
-# CHECK-LE: bclrl 0, 2, 0                   # encoding: [0x21,0x00,0x02,0x4c]
+# CHECK-BE: bclrl 0, 2                      # encoding: [0x4c,0x02,0x00,0x21]
+# CHECK-LE: bclrl 0, 2                      # encoding: [0x21,0x00,0x02,0x4c]
             bdnzflrl 2
 
 # CHECK-BE: bdz target                      # encoding: [0x42,0x40,A,0bAAAAAA00]
@@ -579,58 +579,58 @@
 # CHECK-LE: bdzlrl-                         # encoding: [0x21,0x00,0x40,0x4f]
             bdzlrl-
 
-# CHECK-BE: bc 10, 2, target                # encoding: [0x41,0x42,A,0bAAAAAA00]
-# CHECK-LE: bc 10, 2, target                # encoding: [0bAAAAAA00,A,0x42,0x41]
+# CHECK-BE: bdzt 2, target                  # encoding: [0x41,0x42,A,0bAAAAAA00]
+# CHECK-LE: bdzt 2, target                  # encoding: [0bAAAAAA00,A,0x42,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bdzt 2, target
-# CHECK-BE: bca 10, 2, target               # encoding: [0x41,0x42,A,0bAAAAAA10]
-# CHECK-LE: bca 10, 2, target               # encoding: [0bAAAAAA10,A,0x42,0x41]
+# CHECK-BE: bdzta 2, target                 # encoding: [0x41,0x42,A,0bAAAAAA10]
+# CHECK-LE: bdzta 2, target                 # encoding: [0bAAAAAA10,A,0x42,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bdzta 2, target
-# CHECK-BE: bclr 10, 2, 0                   # encoding: [0x4d,0x42,0x00,0x20]
-# CHECK-LE: bclr 10, 2, 0                   # encoding: [0x20,0x00,0x42,0x4d]
+# CHECK-BE: bclr 10, 2                      # encoding: [0x4d,0x42,0x00,0x20]
+# CHECK-LE: bclr 10, 2                      # encoding: [0x20,0x00,0x42,0x4d]
             bdztlr 2
-# CHECK-BE: bcl 10, 2, target               # encoding: [0x41,0x42,A,0bAAAAAA01]
-# CHECK-LE: bcl 10, 2, target               # encoding: [0bAAAAAA01,A,0x42,0x41]
+# CHECK-BE: bdztl 2, target                 # encoding: [0x41,0x42,A,0bAAAAAA01]
+# CHECK-LE: bdztl 2, target                 # encoding: [0bAAAAAA01,A,0x42,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bdztl 2, target
-# CHECK-BE: bcla 10, 2, target              # encoding: [0x41,0x42,A,0bAAAAAA11]
-# CHECK-LE: bcla 10, 2, target              # encoding: [0bAAAAAA11,A,0x42,0x41]
+# CHECK-BE: bdztla 2, target                # encoding: [0x41,0x42,A,0bAAAAAA11]
+# CHECK-LE: bdztla 2, target                # encoding: [0bAAAAAA11,A,0x42,0x41]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bdztla 2, target
-# CHECK-BE: bclrl 10, 2, 0                  # encoding: [0x4d,0x42,0x00,0x21]
-# CHECK-LE: bclrl 10, 2, 0                  # encoding: [0x21,0x00,0x42,0x4d]
+# CHECK-BE: bclrl 10, 2                     # encoding: [0x4d,0x42,0x00,0x21]
+# CHECK-LE: bclrl 10, 2                     # encoding: [0x21,0x00,0x42,0x4d]
             bdztlrl 2
 
-# CHECK-BE: bc 2, 2, target                 # encoding: [0x40,0x42,A,0bAAAAAA00]
-# CHECK-LE: bc 2, 2, target                 # encoding: [0bAAAAAA00,A,0x42,0x40]
+# CHECK-BE: bdzf 2, target                  # encoding: [0x40,0x42,A,0bAAAAAA00]
+# CHECK-LE: bdzf 2, target                  # encoding: [0bAAAAAA00,A,0x42,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bdzf 2, target
-# CHECK-BE: bca 2, 2, target                # encoding: [0x40,0x42,A,0bAAAAAA10]
-# CHECK-LE: bca 2, 2, target                # encoding: [0bAAAAAA10,A,0x42,0x40]
+# CHECK-BE: bdzfa 2, target                 # encoding: [0x40,0x42,A,0bAAAAAA10]
+# CHECK-LE: bdzfa 2, target                 # encoding: [0bAAAAAA10,A,0x42,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bdzfa 2, target
-# CHECK-BE: bclr 2, 2, 0                    # encoding: [0x4c,0x42,0x00,0x20]
-# CHECK-LE: bclr 2, 2, 0                    # encoding: [0x20,0x00,0x42,0x4c]
+# CHECK-BE: bclr 2, 2                       # encoding: [0x4c,0x42,0x00,0x20]
+# CHECK-LE: bclr 2, 2                       # encoding: [0x20,0x00,0x42,0x4c]
             bdzflr 2
-# CHECK-BE: bcl 2, 2, target                # encoding: [0x40,0x42,A,0bAAAAAA01]
-# CHECK-LE: bcl 2, 2, target                # encoding: [0bAAAAAA01,A,0x42,0x40]
+# CHECK-BE: bdzfl 2, target                 # encoding: [0x40,0x42,A,0bAAAAAA01]
+# CHECK-LE: bdzfl 2, target                 # encoding: [0bAAAAAA01,A,0x42,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bdzfl 2, target
-# CHECK-BE: bcla 2, 2, target               # encoding: [0x40,0x42,A,0bAAAAAA11]
-# CHECK-LE: bcla 2, 2, target               # encoding: [0bAAAAAA11,A,0x42,0x40]
+# CHECK-BE: bdzfla 2, target                # encoding: [0x40,0x42,A,0bAAAAAA11]
+# CHECK-LE: bdzfla 2, target                # encoding: [0bAAAAAA11,A,0x42,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bdzfla 2, target
-# CHECK-BE: bclrl 2, 2, 0                   # encoding: [0x4c,0x42,0x00,0x21]
-# CHECK-LE: bclrl 2, 2, 0                   # encoding: [0x21,0x00,0x42,0x4c]
+# CHECK-BE: bclrl 2, 2                      # encoding: [0x4c,0x42,0x00,0x21]
+# CHECK-LE: bclrl 2, 2                      # encoding: [0x21,0x00,0x42,0x4c]
             bdzflrl 2
 
 # CHECK-BE: blt 2, target                   # encoding: [0x41,0x88,A,0bAAAAAA00]
@@ -2975,17 +2975,17 @@
 
 # Condition register logical mnemonics
 
-# CHECK-BE: creqv 2, 2, 2                   # encoding: [0x4c,0x42,0x12,0x42]
-# CHECK-LE: creqv 2, 2, 2                   # encoding: [0x42,0x12,0x42,0x4c]
+# CHECK-BE: crset 2                         # encoding: [0x4c,0x42,0x12,0x42]
+# CHECK-LE: crset 2                         # encoding: [0x42,0x12,0x42,0x4c]
             crset 2
-# CHECK-BE: crxor 2, 2, 2                   # encoding: [0x4c,0x42,0x11,0x82]
-# CHECK-LE: crxor 2, 2, 2                   # encoding: [0x82,0x11,0x42,0x4c]
+# CHECK-BE: crclr 2                         # encoding: [0x4c,0x42,0x11,0x82]
+# CHECK-LE: crclr 2                         # encoding: [0x82,0x11,0x42,0x4c]
             crclr 2
-# CHECK-BE: cror 2, 3, 3                    # encoding: [0x4c,0x43,0x1b,0x82]
-# CHECK-LE: cror 2, 3, 3                    # encoding: [0x82,0x1b,0x43,0x4c]
+# CHECK-BE: crmove 2, 3                     # encoding: [0x4c,0x43,0x1b,0x82]
+# CHECK-LE: crmove 2, 3                     # encoding: [0x82,0x1b,0x43,0x4c]
             crmove 2, 3
-# CHECK-BE: crnor 2, 3, 3                   # encoding: [0x4c,0x43,0x18,0x42]
-# CHECK-LE: crnor 2, 3, 3                   # encoding: [0x42,0x18,0x43,0x4c]
+# CHECK-BE: crnot 2, 3                      # encoding: [0x4c,0x43,0x18,0x42]
+# CHECK-LE: crnot 2, 3                      # encoding: [0x42,0x18,0x43,0x4c]
             crnot 2, 3
 
 # Subtract mnemonics
@@ -3003,17 +3003,17 @@
 # CHECK-LE: addic. 2, 3, -128               # encoding: [0x80,0xff,0x43,0x34]
             subic. 2, 3, 128
 
-# CHECK-BE: subf 2, 4, 3                    # encoding: [0x7c,0x44,0x18,0x50]
-# CHECK-LE: subf 2, 4, 3                    # encoding: [0x50,0x18,0x44,0x7c]
+# CHECK-BE: sub 2, 3, 4                     # encoding: [0x7c,0x44,0x18,0x50]
+# CHECK-LE: sub 2, 3, 4                     # encoding: [0x50,0x18,0x44,0x7c]
             sub 2, 3, 4
-# CHECK-BE: subf. 2, 4, 3                   # encoding: [0x7c,0x44,0x18,0x51]
-# CHECK-LE: subf. 2, 4, 3                   # encoding: [0x51,0x18,0x44,0x7c]
+# CHECK-BE: sub. 2, 3, 4                    # encoding: [0x7c,0x44,0x18,0x51]
+# CHECK-LE: sub. 2, 3, 4                    # encoding: [0x51,0x18,0x44,0x7c]
             sub. 2, 3, 4
-# CHECK-BE: subfc 2, 4, 3                   # encoding: [0x7c,0x44,0x18,0x10]
-# CHECK-LE: subfc 2, 4, 3                   # encoding: [0x10,0x18,0x44,0x7c]
+# CHECK-BE: subc 2, 3, 4                    # encoding: [0x7c,0x44,0x18,0x10]
+# CHECK-LE: subc 2, 3, 4                    # encoding: [0x10,0x18,0x44,0x7c]
             subc 2, 3, 4
-# CHECK-BE: subfc. 2, 4, 3                  # encoding: [0x7c,0x44,0x18,0x11]
-# CHECK-LE: subfc. 2, 4, 3                  # encoding: [0x11,0x18,0x44,0x7c]
+# CHECK-BE: subc. 2, 3, 4                   # encoding: [0x7c,0x44,0x18,0x11]
+# CHECK-LE: subc. 2, 3, 4                   # encoding: [0x11,0x18,0x44,0x7c]
             subc. 2, 3, 4
 
 # Compare mnemonics
@@ -3021,66 +3021,66 @@
 # CHECK-BE: cmpdi 2, 3, 128                 # encoding: [0x2d,0x23,0x00,0x80]
 # CHECK-LE: cmpdi 2, 3, 128                 # encoding: [0x80,0x00,0x23,0x2d]
             cmpdi 2, 3, 128
-# CHECK-BE: cmpdi 0, 3, 128                 # encoding: [0x2c,0x23,0x00,0x80]
-# CHECK-LE: cmpdi 0, 3, 128                 # encoding: [0x80,0x00,0x23,0x2c]
+# CHECK-BE: cmpdi 3, 128                    # encoding: [0x2c,0x23,0x00,0x80]
+# CHECK-LE: cmpdi 3, 128                    # encoding: [0x80,0x00,0x23,0x2c]
             cmpdi 3, 128
 # CHECK-BE: cmpd 2, 3, 4                    # encoding: [0x7d,0x23,0x20,0x00]
 # CHECK-LE: cmpd 2, 3, 4                    # encoding: [0x00,0x20,0x23,0x7d]
             cmpd 2, 3, 4
-# CHECK-BE: cmpd 0, 3, 4                    # encoding: [0x7c,0x23,0x20,0x00]
-# CHECK-LE: cmpd 0, 3, 4                    # encoding: [0x00,0x20,0x23,0x7c]
+# CHECK-BE: cmpd 3, 4                       # encoding: [0x7c,0x23,0x20,0x00]
+# CHECK-LE: cmpd 3, 4                       # encoding: [0x00,0x20,0x23,0x7c]
             cmpd 3, 4
 # CHECK-BE: cmpldi 2, 3, 128                # encoding: [0x29,0x23,0x00,0x80]
 # CHECK-LE: cmpldi 2, 3, 128                # encoding: [0x80,0x00,0x23,0x29]
             cmpldi 2, 3, 128
-# CHECK-BE: cmpldi 0, 3, 128                # encoding: [0x28,0x23,0x00,0x80]
-# CHECK-LE: cmpldi 0, 3, 128                # encoding: [0x80,0x00,0x23,0x28]
+# CHECK-BE: cmpldi 3, 128                   # encoding: [0x28,0x23,0x00,0x80]
+# CHECK-LE: cmpldi 3, 128                   # encoding: [0x80,0x00,0x23,0x28]
             cmpldi 3, 128
 # CHECK-BE: cmpld 2, 3, 4                   # encoding: [0x7d,0x23,0x20,0x40]
 # CHECK-LE: cmpld 2, 3, 4                   # encoding: [0x40,0x20,0x23,0x7d]
             cmpld 2, 3, 4
-# CHECK-BE: cmpld 0, 3, 4                   # encoding: [0x7c,0x23,0x20,0x40]
-# CHECK-LE: cmpld 0, 3, 4                   # encoding: [0x40,0x20,0x23,0x7c]
+# CHECK-BE: cmpld 3, 4                      # encoding: [0x7c,0x23,0x20,0x40]
+# CHECK-LE: cmpld 3, 4                      # encoding: [0x40,0x20,0x23,0x7c]
             cmpld 3, 4
 
 # CHECK-BE: cmpwi 2, 3, 128                 # encoding: [0x2d,0x03,0x00,0x80]
 # CHECK-LE: cmpwi 2, 3, 128                 # encoding: [0x80,0x00,0x03,0x2d]
             cmpwi 2, 3, 128
-# CHECK-BE: cmpwi 0, 3, 128                 # encoding: [0x2c,0x03,0x00,0x80]
-# CHECK-LE: cmpwi 0, 3, 128                 # encoding: [0x80,0x00,0x03,0x2c]
+# CHECK-BE: cmpwi 3, 128                    # encoding: [0x2c,0x03,0x00,0x80]
+# CHECK-LE: cmpwi 3, 128                    # encoding: [0x80,0x00,0x03,0x2c]
             cmpwi 3, 128
 # CHECK-BE: cmpw 2, 3, 4                    # encoding: [0x7d,0x03,0x20,0x00]
 # CHECK-LE: cmpw 2, 3, 4                    # encoding: [0x00,0x20,0x03,0x7d]
             cmpw 2, 3, 4
-# CHECK-BE: cmpw 0, 3, 4                    # encoding: [0x7c,0x03,0x20,0x00]
-# CHECK-LE: cmpw 0, 3, 4                    # encoding: [0x00,0x20,0x03,0x7c]
+# CHECK-BE: cmpw 3, 4                       # encoding: [0x7c,0x03,0x20,0x00]
+# CHECK-LE: cmpw 3, 4                       # encoding: [0x00,0x20,0x03,0x7c]
             cmpw 3, 4
 # CHECK-BE: cmplwi 2, 3, 128                # encoding: [0x29,0x03,0x00,0x80]
 # CHECK-LE: cmplwi 2, 3, 128                # encoding: [0x80,0x00,0x03,0x29]
             cmplwi 2, 3, 128
-# CHECK-BE: cmplwi 0, 3, 128                # encoding: [0x28,0x03,0x00,0x80]
-# CHECK-LE: cmplwi 0, 3, 128                # encoding: [0x80,0x00,0x03,0x28]
+# CHECK-BE: cmplwi 3, 128                   # encoding: [0x28,0x03,0x00,0x80]
+# CHECK-LE: cmplwi 3, 128                   # encoding: [0x80,0x00,0x03,0x28]
             cmplwi 3, 128
 # CHECK-BE: cmplw 2, 3, 4                   # encoding: [0x7d,0x03,0x20,0x40]
 # CHECK-LE: cmplw 2, 3, 4                   # encoding: [0x40,0x20,0x03,0x7d]
             cmplw 2, 3, 4
-# CHECK-BE: cmplw 0, 3, 4                   # encoding: [0x7c,0x03,0x20,0x40]
-# CHECK-LE: cmplw 0, 3, 4                   # encoding: [0x40,0x20,0x03,0x7c]
+# CHECK-BE: cmplw 3, 4                      # encoding: [0x7c,0x03,0x20,0x40]
+# CHECK-LE: cmplw 3, 4                      # encoding: [0x40,0x20,0x03,0x7c]
             cmplw 3, 4
 
 # Trap mnemonics
 
-# CHECK-BE: twi 16, 3, 4                    # encoding: [0x0e,0x03,0x00,0x04]
-# CHECK-LE: twi 16, 3, 4                    # encoding: [0x04,0x00,0x03,0x0e]
+# CHECK-BE: twlti 3, 4                      # encoding: [0x0e,0x03,0x00,0x04]
+# CHECK-LE: twlti 3, 4                      # encoding: [0x04,0x00,0x03,0x0e]
             twlti 3, 4
-# CHECK-BE: tw 16, 3, 4                     # encoding: [0x7e,0x03,0x20,0x08]
-# CHECK-LE: tw 16, 3, 4                     # encoding: [0x08,0x20,0x03,0x7e]
+# CHECK-BE: twlt 3, 4                       # encoding: [0x7e,0x03,0x20,0x08]
+# CHECK-LE: twlt 3, 4                       # encoding: [0x08,0x20,0x03,0x7e]
             twlt 3, 4
-# CHECK-BE: tdi 16, 3, 4                    # encoding: [0x0a,0x03,0x00,0x04]
-# CHECK-LE: tdi 16, 3, 4                    # encoding: [0x04,0x00,0x03,0x0a]
+# CHECK-BE: tdlti 3, 4                      # encoding: [0x0a,0x03,0x00,0x04]
+# CHECK-LE: tdlti 3, 4                      # encoding: [0x04,0x00,0x03,0x0a]
             tdlti 3, 4
-# CHECK-BE: td 16, 3, 4                     # encoding: [0x7e,0x03,0x20,0x88]
-# CHECK-LE: td 16, 3, 4                     # encoding: [0x88,0x20,0x03,0x7e]
+# CHECK-BE: tdlt 3, 4                       # encoding: [0x7e,0x03,0x20,0x88]
+# CHECK-LE: tdlt 3, 4                       # encoding: [0x88,0x20,0x03,0x7e]
             tdlt 3, 4
 
 # CHECK-BE: twi 20, 3, 4                    # encoding: [0x0e,0x83,0x00,0x04]
@@ -3096,17 +3096,17 @@
 # CHECK-LE: td 20, 3, 4                     # encoding: [0x88,0x20,0x83,0x7e]
             tdle 3, 4
 
-# CHECK-BE: twi 4, 3, 4                     # encoding: [0x0c,0x83,0x00,0x04]
-# CHECK-LE: twi 4, 3, 4                     # encoding: [0x04,0x00,0x83,0x0c]
+# CHECK-BE: tweqi 3, 4                      # encoding: [0x0c,0x83,0x00,0x04]
+# CHECK-LE: tweqi 3, 4                      # encoding: [0x04,0x00,0x83,0x0c]
             tweqi 3, 4
-# CHECK-BE: tw 4, 3, 4                      # encoding: [0x7c,0x83,0x20,0x08]
-# CHECK-LE: tw 4, 3, 4                      # encoding: [0x08,0x20,0x83,0x7c]
+# CHECK-BE: tweq 3, 4                       # encoding: [0x7c,0x83,0x20,0x08]
+# CHECK-LE: tweq 3, 4                       # encoding: [0x08,0x20,0x83,0x7c]
             tweq 3, 4
-# CHECK-BE: tdi 4, 3, 4                     # encoding: [0x08,0x83,0x00,0x04]
-# CHECK-LE: tdi 4, 3, 4                     # encoding: [0x04,0x00,0x83,0x08]
+# CHECK-BE: tdeqi 3, 4                      # encoding: [0x08,0x83,0x00,0x04]
+# CHECK-LE: tdeqi 3, 4                      # encoding: [0x04,0x00,0x83,0x08]
             tdeqi 3, 4
-# CHECK-BE: td 4, 3, 4                      # encoding: [0x7c,0x83,0x20,0x88]
-# CHECK-LE: td 4, 3, 4                      # encoding: [0x88,0x20,0x83,0x7c]
+# CHECK-BE: tdeq 3, 4                       # encoding: [0x7c,0x83,0x20,0x88]
+# CHECK-LE: tdeq 3, 4                       # encoding: [0x88,0x20,0x83,0x7c]
             tdeq 3, 4
 
 # CHECK-BE: twi 12, 3, 4                    # encoding: [0x0d,0x83,0x00,0x04]
@@ -3122,17 +3122,17 @@
 # CHECK-LE: td 12, 3, 4                     # encoding: [0x88,0x20,0x83,0x7d]
             tdge 3, 4
 
-# CHECK-BE: twi 8, 3, 4                     # encoding: [0x0d,0x03,0x00,0x04]
-# CHECK-LE: twi 8, 3, 4                     # encoding: [0x04,0x00,0x03,0x0d]
+# CHECK-BE: twgti 3, 4                      # encoding: [0x0d,0x03,0x00,0x04]
+# CHECK-LE: twgti 3, 4                      # encoding: [0x04,0x00,0x03,0x0d]
             twgti 3, 4
-# CHECK-BE: tw 8, 3, 4                      # encoding: [0x7d,0x03,0x20,0x08]
-# CHECK-LE: tw 8, 3, 4                      # encoding: [0x08,0x20,0x03,0x7d]
+# CHECK-BE: twgt 3, 4                       # encoding: [0x7d,0x03,0x20,0x08]
+# CHECK-LE: twgt 3, 4                       # encoding: [0x08,0x20,0x03,0x7d]
             twgt 3, 4
-# CHECK-BE: tdi 8, 3, 4                     # encoding: [0x09,0x03,0x00,0x04]
-# CHECK-LE: tdi 8, 3, 4                     # encoding: [0x04,0x00,0x03,0x09]
+# CHECK-BE: tdgti 3, 4                      # encoding: [0x09,0x03,0x00,0x04]
+# CHECK-LE: tdgti 3, 4                      # encoding: [0x04,0x00,0x03,0x09]
             tdgti 3, 4
-# CHECK-BE: td 8, 3, 4                      # encoding: [0x7d,0x03,0x20,0x88]
-# CHECK-LE: td 8, 3, 4                      # encoding: [0x88,0x20,0x03,0x7d]
+# CHECK-BE: tdgt 3, 4                       # encoding: [0x7d,0x03,0x20,0x88]
+# CHECK-LE: tdgt 3, 4                       # encoding: [0x88,0x20,0x03,0x7d]
             tdgt 3, 4
 
 # CHECK-BE: twi 12, 3, 4                    # encoding: [0x0d,0x83,0x00,0x04]
@@ -3148,17 +3148,17 @@
 # CHECK-LE: td 12, 3, 4                     # encoding: [0x88,0x20,0x83,0x7d]
             tdnl 3, 4
 
-# CHECK-BE: twi 24, 3, 4                    # encoding: [0x0f,0x03,0x00,0x04]
-# CHECK-LE: twi 24, 3, 4                    # encoding: [0x04,0x00,0x03,0x0f]
+# CHECK-BE: twnei 3, 4                      # encoding: [0x0f,0x03,0x00,0x04]
+# CHECK-LE: twnei 3, 4                      # encoding: [0x04,0x00,0x03,0x0f]
             twnei 3, 4
-# CHECK-BE: tw 24, 3, 4                     # encoding: [0x7f,0x03,0x20,0x08]
-# CHECK-LE: tw 24, 3, 4                     # encoding: [0x08,0x20,0x03,0x7f]
+# CHECK-BE: twne 3, 4                       # encoding: [0x7f,0x03,0x20,0x08]
+# CHECK-LE: twne 3, 4                       # encoding: [0x08,0x20,0x03,0x7f]
             twne 3, 4
-# CHECK-BE: tdi 24, 3, 4                    # encoding: [0x0b,0x03,0x00,0x04]
-# CHECK-LE: tdi 24, 3, 4                    # encoding: [0x04,0x00,0x03,0x0b]
+# CHECK-BE: tdnei 3, 4                      # encoding: [0x0b,0x03,0x00,0x04]
+# CHECK-LE: tdnei 3, 4                      # encoding: [0x04,0x00,0x03,0x0b]
             tdnei 3, 4
-# CHECK-BE: td 24, 3, 4                     # encoding: [0x7f,0x03,0x20,0x88]
-# CHECK-LE: td 24, 3, 4                     # encoding: [0x88,0x20,0x03,0x7f]
+# CHECK-BE: tdne 3, 4                       # encoding: [0x7f,0x03,0x20,0x88]
+# CHECK-LE: tdne 3, 4                       # encoding: [0x88,0x20,0x03,0x7f]
             tdne 3, 4
 
 # CHECK-BE: twi 20, 3, 4                    # encoding: [0x0e,0x83,0x00,0x04]
@@ -3174,17 +3174,17 @@
 # CHECK-LE: td 20, 3, 4                     # encoding: [0x88,0x20,0x83,0x7e]
             tdng 3, 4
 
-# CHECK-BE: twi 2, 3, 4                     # encoding: [0x0c,0x43,0x00,0x04]
-# CHECK-LE: twi 2, 3, 4                     # encoding: [0x04,0x00,0x43,0x0c]
+# CHECK-BE: twllti 3, 4                     # encoding: [0x0c,0x43,0x00,0x04]
+# CHECK-LE: twllti 3, 4                     # encoding: [0x04,0x00,0x43,0x0c]
             twllti 3, 4
-# CHECK-BE: tw 2, 3, 4                      # encoding: [0x7c,0x43,0x20,0x08]
-# CHECK-LE: tw 2, 3, 4                      # encoding: [0x08,0x20,0x43,0x7c]
+# CHECK-BE: twllt 3, 4                      # encoding: [0x7c,0x43,0x20,0x08]
+# CHECK-LE: twllt 3, 4                      # encoding: [0x08,0x20,0x43,0x7c]
             twllt 3, 4
-# CHECK-BE: tdi 2, 3, 4                     # encoding: [0x08,0x43,0x00,0x04]
-# CHECK-LE: tdi 2, 3, 4                     # encoding: [0x04,0x00,0x43,0x08]
+# CHECK-BE: tdllti 3, 4                     # encoding: [0x08,0x43,0x00,0x04]
+# CHECK-LE: tdllti 3, 4                     # encoding: [0x04,0x00,0x43,0x08]
             tdllti 3, 4
-# CHECK-BE: td 2, 3, 4                      # encoding: [0x7c,0x43,0x20,0x88]
-# CHECK-LE: td 2, 3, 4                      # encoding: [0x88,0x20,0x43,0x7c]
+# CHECK-BE: tdllt 3, 4                      # encoding: [0x7c,0x43,0x20,0x88]
+# CHECK-LE: tdllt 3, 4                      # encoding: [0x88,0x20,0x43,0x7c]
             tdllt 3, 4
 
 # CHECK-BE: twi 6, 3, 4                     # encoding: [0x0c,0xc3,0x00,0x04]
@@ -3213,17 +3213,17 @@
 # CHECK-LE: td 5, 3, 4                      # encoding: [0x88,0x20,0xa3,0x7c]
             tdlge 3, 4
 
-# CHECK-BE: twi 1, 3, 4                     # encoding: [0x0c,0x23,0x00,0x04]
-# CHECK-LE: twi 1, 3, 4                     # encoding: [0x04,0x00,0x23,0x0c]
+# CHECK-BE: twlgti 3, 4                     # encoding: [0x0c,0x23,0x00,0x04]
+# CHECK-LE: twlgti 3, 4                     # encoding: [0x04,0x00,0x23,0x0c]
             twlgti 3, 4
-# CHECK-BE: tw 1, 3, 4                      # encoding: [0x7c,0x23,0x20,0x08]
-# CHECK-LE: tw 1, 3, 4                      # encoding: [0x08,0x20,0x23,0x7c]
+# CHECK-BE: twlgt 3, 4                      # encoding: [0x7c,0x23,0x20,0x08]
+# CHECK-LE: twlgt 3, 4                      # encoding: [0x08,0x20,0x23,0x7c]
             twlgt 3, 4
-# CHECK-BE: tdi 1, 3, 4                     # encoding: [0x08,0x23,0x00,0x04]
-# CHECK-LE: tdi 1, 3, 4                     # encoding: [0x04,0x00,0x23,0x08]
+# CHECK-BE: tdlgti 3, 4                     # encoding: [0x08,0x23,0x00,0x04]
+# CHECK-LE: tdlgti 3, 4                     # encoding: [0x04,0x00,0x23,0x08]
             tdlgti 3, 4
-# CHECK-BE: td 1, 3, 4                      # encoding: [0x7c,0x23,0x20,0x88]
-# CHECK-LE: td 1, 3, 4                      # encoding: [0x88,0x20,0x23,0x7c]
+# CHECK-BE: tdlgt 3, 4                      # encoding: [0x7c,0x23,0x20,0x88]
+# CHECK-LE: tdlgt 3, 4                      # encoding: [0x88,0x20,0x23,0x7c]
             tdlgt 3, 4
 
 # CHECK-BE: twi 5, 3, 4                     # encoding: [0x0c,0xa3,0x00,0x04]
@@ -3252,17 +3252,17 @@
 # CHECK-LE: td 6, 3, 4                      # encoding: [0x88,0x20,0xc3,0x7c]
             tdlng 3, 4
 
-# CHECK-BE: twi 31, 3, 4                    # encoding: [0x0f,0xe3,0x00,0x04]
-# CHECK-LE: twi 31, 3, 4                    # encoding: [0x04,0x00,0xe3,0x0f]
+# CHECK-BE: twui 3, 4                       # encoding: [0x0f,0xe3,0x00,0x04]
+# CHECK-LE: twui 3, 4                       # encoding: [0x04,0x00,0xe3,0x0f]
             twui 3, 4
-# CHECK-BE: tw 31, 3, 4                     # encoding: [0x7f,0xe3,0x20,0x08]
-# CHECK-LE: tw 31, 3, 4                     # encoding: [0x08,0x20,0xe3,0x7f]
+# CHECK-BE: twu 3, 4                        # encoding: [0x7f,0xe3,0x20,0x08]
+# CHECK-LE: twu 3, 4                        # encoding: [0x08,0x20,0xe3,0x7f]
             twu 3, 4
-# CHECK-BE: tdi 31, 3, 4                    # encoding: [0x0b,0xe3,0x00,0x04]
-# CHECK-LE: tdi 31, 3, 4                    # encoding: [0x04,0x00,0xe3,0x0b]
+# CHECK-BE: tdui 3, 4                       # encoding: [0x0b,0xe3,0x00,0x04]
+# CHECK-LE: tdui 3, 4                       # encoding: [0x04,0x00,0xe3,0x0b]
             tdui 3, 4
-# CHECK-BE: td 31, 3, 4                     # encoding: [0x7f,0xe3,0x20,0x88]
-# CHECK-LE: td 31, 3, 4                     # encoding: [0x88,0x20,0xe3,0x7f]
+# CHECK-BE: tdu 3, 4                         # encoding: [0x7f,0xe3,0x20,0x88]
+# CHECK-LE: tdu 3, 4                         # encoding: [0x88,0x20,0xe3,0x7f]
             tdu 3, 4
 
 # CHECK-BE: trap                            # encoding: [0x7f,0xe0,0x00,0x08]
@@ -3289,23 +3289,23 @@
 # CHECK-BE: rldimi. 2, 3, 55, 5             # encoding: [0x78,0x62,0xb9,0x4f]
 # CHECK-LE: rldimi. 2, 3, 55, 5             # encoding: [0x4f,0xb9,0x62,0x78]
             insrdi. 2, 3, 4, 5
-# CHECK-BE: rldicl 2, 3, 4, 0               # encoding: [0x78,0x62,0x20,0x00]
-# CHECK-LE: rldicl 2, 3, 4, 0               # encoding: [0x00,0x20,0x62,0x78]
+# CHECK-BE: rotldi 2, 3, 4                  # encoding: [0x78,0x62,0x20,0x00]
+# CHECK-LE: rotldi 2, 3, 4                  # encoding: [0x00,0x20,0x62,0x78]
             rotldi 2, 3, 4
-# CHECK-BE: rldicl. 2, 3, 4, 0              # encoding: [0x78,0x62,0x20,0x01]
-# CHECK-LE: rldicl. 2, 3, 4, 0              # encoding: [0x01,0x20,0x62,0x78]
+# CHECK-BE: rotldi. 2, 3, 4                 # encoding: [0x78,0x62,0x20,0x01]
+# CHECK-LE: rotldi. 2, 3, 4                 # encoding: [0x01,0x20,0x62,0x78]
             rotldi. 2, 3, 4
-# CHECK-BE: rldicl 2, 3, 60, 0              # encoding: [0x78,0x62,0xe0,0x02]
-# CHECK-LE: rldicl 2, 3, 60, 0              # encoding: [0x02,0xe0,0x62,0x78]
+# CHECK-BE: rotldi 2, 3, 60                 # encoding: [0x78,0x62,0xe0,0x02]
+# CHECK-LE: rotldi 2, 3, 60                 # encoding: [0x02,0xe0,0x62,0x78]
             rotrdi 2, 3, 4
-# CHECK-BE: rldicl. 2, 3, 60, 0             # encoding: [0x78,0x62,0xe0,0x03]
-# CHECK-LE: rldicl. 2, 3, 60, 0             # encoding: [0x03,0xe0,0x62,0x78]
+# CHECK-BE: rotldi. 2, 3, 60                # encoding: [0x78,0x62,0xe0,0x03]
+# CHECK-LE: rotldi. 2, 3, 60                # encoding: [0x03,0xe0,0x62,0x78]
             rotrdi. 2, 3, 4
-# CHECK-BE: rldcl 2, 3, 4, 0                # encoding: [0x78,0x62,0x20,0x10]
-# CHECK-LE: rldcl 2, 3, 4, 0                # encoding: [0x10,0x20,0x62,0x78]
+# CHECK-BE: rotld 2, 3, 4                   # encoding: [0x78,0x62,0x20,0x10]
+# CHECK-LE: rotld 2, 3, 4                   # encoding: [0x10,0x20,0x62,0x78]
             rotld 2, 3, 4
-# CHECK-BE: rldcl. 2, 3, 4, 0               # encoding: [0x78,0x62,0x20,0x11]
-# CHECK-LE: rldcl. 2, 3, 4, 0               # encoding: [0x11,0x20,0x62,0x78]
+# CHECK-BE: rotld. 2, 3, 4                  # encoding: [0x78,0x62,0x20,0x11]
+# CHECK-LE: rotld. 2, 3, 4                  # encoding: [0x11,0x20,0x62,0x78]
             rotld. 2, 3, 4
 # CHECK-BE: sldi 2, 3, 4                    # encoding: [0x78,0x62,0x26,0xe4]
 # CHECK-LE: sldi 2, 3, 4                    # encoding: [0xe4,0x26,0x62,0x78]
@@ -3319,11 +3319,11 @@
 # CHECK-BE: rldicl. 2, 3, 60, 4             # encoding: [0x78,0x62,0xe1,0x03]
 # CHECK-LE: rldicl. 2, 3, 60, 4             # encoding: [0x03,0xe1,0x62,0x78]
             srdi. 2, 3, 4
-# CHECK-BE: rldicl 2, 3, 0, 4               # encoding: [0x78,0x62,0x01,0x00]
-# CHECK-LE: rldicl 2, 3, 0, 4               # encoding: [0x00,0x01,0x62,0x78]
+# CHECK-BE: clrldi 2, 3, 4                  # encoding: [0x78,0x62,0x01,0x00]
+# CHECK-LE: clrldi 2, 3, 4                  # encoding: [0x00,0x01,0x62,0x78]
             clrldi 2, 3, 4
-# CHECK-BE: rldicl. 2, 3, 0, 4              # encoding: [0x78,0x62,0x01,0x01]
-# CHECK-LE: rldicl. 2, 3, 0, 4              # encoding: [0x01,0x01,0x62,0x78]
+# CHECK-BE: clrldi. 2, 3, 4                 # encoding: [0x78,0x62,0x01,0x01]
+# CHECK-LE: clrldi. 2, 3, 4                 # encoding: [0x01,0x01,0x62,0x78]
             clrldi. 2, 3, 4
 # CHECK-BE: rldicr 2, 3, 0, 59              # encoding: [0x78,0x62,0x06,0xe4]
 # CHECK-LE: rldicr 2, 3, 0, 59              # encoding: [0xe4,0x06,0x62,0x78]
@@ -3362,23 +3362,23 @@
 # CHECK-BE: rlwimi. 2, 3, 23, 5, 8          # encoding: [0x50,0x62,0xb9,0x51]
 # CHECK-LE: rlwimi. 2, 3, 23, 5, 8          # encoding: [0x51,0xb9,0x62,0x50]
             insrwi. 2, 3, 4, 5
-# CHECK-BE: rlwinm 2, 3, 4, 0, 31           # encoding: [0x54,0x62,0x20,0x3e]
-# CHECK-LE: rlwinm 2, 3, 4, 0, 31           # encoding: [0x3e,0x20,0x62,0x54]
+# CHECK-BE: rotlwi 2, 3, 4                  # encoding: [0x54,0x62,0x20,0x3e]
+# CHECK-LE: rotlwi 2, 3, 4                  # encoding: [0x3e,0x20,0x62,0x54]
             rotlwi 2, 3, 4
-# CHECK-BE: rlwinm. 2, 3, 4, 0, 31          # encoding: [0x54,0x62,0x20,0x3f]
-# CHECK-LE: rlwinm. 2, 3, 4, 0, 31          # encoding: [0x3f,0x20,0x62,0x54]
+# CHECK-BE: rotlwi. 2, 3, 4                 # encoding: [0x54,0x62,0x20,0x3f]
+# CHECK-LE: rotlwi. 2, 3, 4                 # encoding: [0x3f,0x20,0x62,0x54]
             rotlwi. 2, 3, 4
-# CHECK-BE: rlwinm 2, 3, 28, 0, 31          # encoding: [0x54,0x62,0xe0,0x3e]
-# CHECK-LE: rlwinm 2, 3, 28, 0, 31          # encoding: [0x3e,0xe0,0x62,0x54]
+# CHECK-BE: rotlwi 2, 3, 28                 # encoding: [0x54,0x62,0xe0,0x3e]
+# CHECK-LE: rotlwi 2, 3, 28                 # encoding: [0x3e,0xe0,0x62,0x54]
             rotrwi 2, 3, 4
-# CHECK-BE: rlwinm. 2, 3, 28, 0, 31         # encoding: [0x54,0x62,0xe0,0x3f]
-# CHECK-LE: rlwinm. 2, 3, 28, 0, 31         # encoding: [0x3f,0xe0,0x62,0x54]
+# CHECK-BE: rotlwi. 2, 3, 28                # encoding: [0x54,0x62,0xe0,0x3f]
+# CHECK-LE: rotlwi. 2, 3, 28                # encoding: [0x3f,0xe0,0x62,0x54]
             rotrwi. 2, 3, 4
-# CHECK-BE: rlwnm 2, 3, 4, 0, 31            # encoding: [0x5c,0x62,0x20,0x3e]
-# CHECK-LE: rlwnm 2, 3, 4, 0, 31            # encoding: [0x3e,0x20,0x62,0x5c]
+# CHECK-BE: rotlw 2, 3, 4                   # encoding: [0x5c,0x62,0x20,0x3e]
+# CHECK-LE: rotlw 2, 3, 4                   # encoding: [0x3e,0x20,0x62,0x5c]
             rotlw 2, 3, 4
-# CHECK-BE: rlwnm. 2, 3, 4, 0, 31           # encoding: [0x5c,0x62,0x20,0x3f]
-# CHECK-LE: rlwnm. 2, 3, 4, 0, 31           # encoding: [0x3f,0x20,0x62,0x5c]
+# CHECK-BE: rotlw. 2, 3, 4                  # encoding: [0x5c,0x62,0x20,0x3f]
+# CHECK-LE: rotlw. 2, 3, 4                  # encoding: [0x3f,0x20,0x62,0x5c]
             rotlw. 2, 3, 4
 # CHECK-BE: slwi 2, 3, 4                    # encoding: [0x54,0x62,0x20,0x36]
 # CHECK-LE: slwi 2, 3, 4                    # encoding: [0x36,0x20,0x62,0x54]
@@ -3392,11 +3392,11 @@
 # CHECK-BE: rlwinm. 2, 3, 28, 4, 31         # encoding: [0x54,0x62,0xe1,0x3f]
 # CHECK-LE: rlwinm. 2, 3, 28, 4, 31         # encoding: [0x3f,0xe1,0x62,0x54]
             srwi. 2, 3, 4
-# CHECK-BE: rlwinm 2, 3, 0, 4, 31           # encoding: [0x54,0x62,0x01,0x3e]
-# CHECK-LE: rlwinm 2, 3, 0, 4, 31           # encoding: [0x3e,0x01,0x62,0x54]
+# CHECK-BE: clrlwi 2, 3, 4                  # encoding: [0x54,0x62,0x01,0x3e]
+# CHECK-LE: clrlwi 2, 3, 4                  # encoding: [0x3e,0x01,0x62,0x54]
             clrlwi 2, 3, 4
-# CHECK-BE: rlwinm. 2, 3, 0, 4, 31          # encoding: [0x54,0x62,0x01,0x3f]
-# CHECK-LE: rlwinm. 2, 3, 0, 4, 31          # encoding: [0x3f,0x01,0x62,0x54]
+# CHECK-BE: clrlwi. 2, 3, 4                 # encoding: [0x54,0x62,0x01,0x3f]
+# CHECK-LE: clrlwi. 2, 3, 4                 # encoding: [0x3f,0x01,0x62,0x54]
             clrlwi. 2, 3, 4
 # CHECK-BE: rlwinm 2, 3, 0, 0, 27           # encoding: [0x54,0x62,0x00,0x36]
 # CHECK-LE: rlwinm 2, 3, 0, 0, 27           # encoding: [0x36,0x00,0x62,0x54]
@@ -3413,35 +3413,35 @@
 
 # Move to/from special purpose register mnemonics
 
-# CHECK-BE: mtspr 1, 2                      # encoding: [0x7c,0x41,0x03,0xa6]
-# CHECK-LE: mtspr 1, 2                      # encoding: [0xa6,0x03,0x41,0x7c]
+# CHECK-BE: mtxer 2                         # encoding: [0x7c,0x41,0x03,0xa6]
+# CHECK-LE: mtxer 2                         # encoding: [0xa6,0x03,0x41,0x7c]
             mtxer 2
-# CHECK-BE: mfspr 2, 1                      # encoding: [0x7c,0x41,0x02,0xa6]
-# CHECK-LE: mfspr 2, 1                      # encoding: [0xa6,0x02,0x41,0x7c]
+# CHECK-BE: mfxer 2                         # encoding: [0x7c,0x41,0x02,0xa6]
+# CHECK-LE: mfxer 2                         # encoding: [0xa6,0x02,0x41,0x7c]
             mfxer 2
-# CHECK-BE: mfspr 2, 4                      # encoding: [0x7c,0x44,0x02,0xa6]
-# CHECK-LE: mfspr 2, 4                      # encoding: [0xa6,0x02,0x44,0x7c]
+# CHECK-BE: mfrtcu 2                        # encoding: [0x7c,0x44,0x02,0xa6]
+# CHECK-LE: mfrtcu 2                        # encoding: [0xa6,0x02,0x44,0x7c]
             mfrtcu 2
-# CHECK-BE: mfspr 2, 5                      # encoding: [0x7c,0x45,0x02,0xa6]
-# CHECK-LE: mfspr 2, 5                      # encoding: [0xa6,0x02,0x45,0x7c]
+# CHECK-BE: mfrtcl 2                        # encoding: [0x7c,0x45,0x02,0xa6]
+# CHECK-LE: mfrtcl 2                        # encoding: [0xa6,0x02,0x45,0x7c]
             mfrtcl 2
-# CHECK-BE: mtspr 17, 2                     # encoding: [0x7c,0x51,0x03,0xa6]
-# CHECK-LE: mtspr 17, 2                     # encoding: [0xa6,0x03,0x51,0x7c]
+# CHECK-BE: mtdscr 2                        # encoding: [0x7c,0x51,0x03,0xa6]
+# CHECK-LE: mtdscr 2                        # encoding: [0xa6,0x03,0x51,0x7c]
             mtdscr 2
-# CHECK-BE: mfspr 2, 17                     # encoding: [0x7c,0x51,0x02,0xa6]
-# CHECK-LE: mfspr 2, 17                     # encoding: [0xa6,0x02,0x51,0x7c]
+# CHECK-BE: mfdscr 2                        # encoding: [0x7c,0x51,0x02,0xa6]
+# CHECK-LE: mfdscr 2                        # encoding: [0xa6,0x02,0x51,0x7c]
             mfdscr 2
-# CHECK-BE: mtspr 18, 2                     # encoding: [0x7c,0x52,0x03,0xa6]
-# CHECK-LE: mtspr 18, 2                     # encoding: [0xa6,0x03,0x52,0x7c]
+# CHECK-BE: mtdsisr 2                       # encoding: [0x7c,0x52,0x03,0xa6]
+# CHECK-LE: mtdsisr 2                       # encoding: [0xa6,0x03,0x52,0x7c]
             mtdsisr 2
-# CHECK-BE: mfspr 2, 18                     # encoding: [0x7c,0x52,0x02,0xa6]
-# CHECK-LE: mfspr 2, 18                     # encoding: [0xa6,0x02,0x52,0x7c]
+# CHECK-BE: mfdsisr 2                       # encoding: [0x7c,0x52,0x02,0xa6]
+# CHECK-LE: mfdsisr 2                       # encoding: [0xa6,0x02,0x52,0x7c]
             mfdsisr 2
-# CHECK-BE: mtspr 19, 2                     # encoding: [0x7c,0x53,0x03,0xa6]
-# CHECK-LE: mtspr 19, 2                     # encoding: [0xa6,0x03,0x53,0x7c]
+# CHECK-BE: mtdar 2                         # encoding: [0x7c,0x53,0x03,0xa6]
+# CHECK-LE: mtdar 2                         # encoding: [0xa6,0x03,0x53,0x7c]
             mtdar 2
-# CHECK-BE: mfspr 2, 19                     # encoding: [0x7c,0x53,0x02,0xa6]
-# CHECK-LE: mfspr 2, 19                     # encoding: [0xa6,0x02,0x53,0x7c]
+# CHECK-BE: mfdar 2                         # encoding: [0x7c,0x53,0x02,0xa6]
+# CHECK-LE: mfdar 2                         # encoding: [0xa6,0x02,0x53,0x7c]
             mfdar 2
 # CHECK-BE: mtspr 22, 2                     # encoding: [0x7c,0x56,0x03,0xa6]
 # CHECK-LE: mtspr 22, 2                     # encoding: [0xa6,0x03,0x56,0x7c]
@@ -3467,23 +3467,23 @@
 # CHECK-BE: mfspr 2, 27                     # encoding: [0x7c,0x5b,0x02,0xa6]
 # CHECK-LE: mfspr 2, 27                     # encoding: [0xa6,0x02,0x5b,0x7c]
             mfsrr1 2
-# CHECK-BE: mtspr 28, 2                     # encoding: [0x7c,0x5c,0x03,0xa6]
-# CHECK-LE: mtspr 28, 2                     # encoding: [0xa6,0x03,0x5c,0x7c]
+# CHECK-BE: mtcfar 2                        # encoding: [0x7c,0x5c,0x03,0xa6]
+# CHECK-LE: mtcfar 2                        # encoding: [0xa6,0x03,0x5c,0x7c]
             mtcfar 2
-# CHECK-BE: mfspr 2, 28                     # encoding: [0x7c,0x5c,0x02,0xa6]
-# CHECK-LE: mfspr 2, 28                     # encoding: [0xa6,0x02,0x5c,0x7c]
+# CHECK-BE: mfcfar 2                        # encoding: [0x7c,0x5c,0x02,0xa6]
+# CHECK-LE: mfcfar 2                        # encoding: [0xa6,0x02,0x5c,0x7c]
             mfcfar 2
-# CHECK-BE: mtspr 29, 2                     # encoding: [0x7c,0x5d,0x03,0xa6]
-# CHECK-LE: mtspr 29, 2                     # encoding: [0xa6,0x03,0x5d,0x7c]
+# CHECK-BE: mtamr 2                         # encoding: [0x7c,0x5d,0x03,0xa6]
+# CHECK-LE: mtamr 2                         # encoding: [0xa6,0x03,0x5d,0x7c]
             mtamr 2
-# CHECK-BE: mfspr 2, 29                     # encoding: [0x7c,0x5d,0x02,0xa6]
-# CHECK-LE: mfspr 2, 29                     # encoding: [0xa6,0x02,0x5d,0x7c]
+# CHECK-BE: mfamr 2                         # encoding: [0x7c,0x5d,0x02,0xa6]
+# CHECK-LE: mfamr 2                         # encoding: [0xa6,0x02,0x5d,0x7c]
             mfamr 2
-# CHECK-BE: mtspr 48, 2                     # encoding: [0x7c,0x50,0x0b,0xa6]
-# CHECK-LE: mtspr 48, 2                     # encoding: [0xa6,0x0b,0x50,0x7c]
+# CHECK-BE: mtpid 2                         # encoding: [0x7c,0x50,0x0b,0xa6]
+# CHECK-LE: mtpid 2                         # encoding: [0xa6,0x0b,0x50,0x7c]
             mtpid 2
-# CHECK-BE: mfspr 2, 48                     # encoding: [0x7c,0x50,0x0a,0xa6]
-# CHECK-LE: mfspr 2, 48                     # encoding: [0xa6,0x0a,0x50,0x7c]
+# CHECK-BE: mfpid 2                         # encoding: [0x7c,0x50,0x0a,0xa6]
+# CHECK-LE: mfpid 2                         # encoding: [0xa6,0x0a,0x50,0x7c]
             mfpid 2
 # CHECK-BE: mtlr 2                          # encoding: [0x7c,0x48,0x03,0xa6]
 # CHECK-LE: mtlr 2                          # encoding: [0xa6,0x03,0x48,0x7c]
@@ -3503,8 +3503,8 @@
 # CHECK-BE: nop                             # encoding: [0x60,0x00,0x00,0x00]
 # CHECK-LE: nop                             # encoding: [0x00,0x00,0x00,0x60]
             nop
-# CHECK-BE: xori 0, 0, 0                    # encoding: [0x68,0x00,0x00,0x00]
-# CHECK-LE: xori 0, 0, 0                    # encoding: [0x00,0x00,0x00,0x68]
+# CHECK-BE: xnop                            # encoding: [0x68,0x00,0x00,0x00]
+# CHECK-LE: xnop                            # encoding: [0x00,0x00,0x00,0x68]
             xnop
 # CHECK-BE: li 2, 128                       # encoding: [0x38,0x40,0x00,0x80]
 # CHECK-LE: li 2, 128                       # encoding: [0x80,0x00,0x40,0x38]
@@ -3518,17 +3518,17 @@
 # CHECK-BE: mr 2, 3                         # encoding: [0x7c,0x62,0x1b,0x78]
 # CHECK-LE: mr 2, 3                         # encoding: [0x78,0x1b,0x62,0x7c]
             mr 2, 3
-# CHECK-BE: or. 2, 3, 3                     # encoding: [0x7c,0x62,0x1b,0x79]
-# CHECK-LE: or. 2, 3, 3                     # encoding: [0x79,0x1b,0x62,0x7c]
+# CHECK-BE: mr. 2, 3                        # encoding: [0x7c,0x62,0x1b,0x79]
+# CHECK-LE: mr. 2, 3                        # encoding: [0x79,0x1b,0x62,0x7c]
             mr. 2, 3
-# CHECK-BE: nor 2, 3, 3                     # encoding: [0x7c,0x62,0x18,0xf8]
-# CHECK-LE: nor 2, 3, 3                     # encoding: [0xf8,0x18,0x62,0x7c]
+# CHECK-BE: not 2, 3                        # encoding: [0x7c,0x62,0x18,0xf8]
+# CHECK-LE: not 2, 3                        # encoding: [0xf8,0x18,0x62,0x7c]
             not 2, 3
-# CHECK-BE: nor. 2, 3, 3                    # encoding: [0x7c,0x62,0x18,0xf9]
-# CHECK-LE: nor. 2, 3, 3                    # encoding: [0xf9,0x18,0x62,0x7c]
+# CHECK-BE: not. 2, 3                       # encoding: [0x7c,0x62,0x18,0xf9]
+# CHECK-LE: not. 2, 3                       # encoding: [0xf9,0x18,0x62,0x7c]
             not. 2, 3
-# CHECK-BE: mtcrf 255, 2                    # encoding: [0x7c,0x4f,0xf1,0x20]
-# CHECK-LE: mtcrf 255, 2                    # encoding: [0x20,0xf1,0x4f,0x7c]
+# CHECK-BE: mtcr 2                          # encoding: [0x7c,0x4f,0xf1,0x20]
+# CHECK-LE: mtcr 2                          # encoding: [0x20,0xf1,0x4f,0x7c]
             mtcr 2
 
 # CHECK-BE: mfspr 4, 272                    # encoding: [0x7c,0x90,0x42,0xa6]
@@ -3623,12 +3623,12 @@
 # CHECK-LE: stswi 8, 6, 7                    # encoding: [0xaa,0x3d,0x06,0x7d]
             stswi %r8, %r6, 7
 
-# CHECK-BE: rfid                            # encoding: [0x4c,0x00,0x00,0x24]
-# CHECK-LE: rfid                            # encoding: [0x24,0x00,0x00,0x4c]
+# CHECK-BE: rfid                             # encoding: [0x4c,0x00,0x00,0x24]
+# CHECK-LE: rfid                             # encoding: [0x24,0x00,0x00,0x4c]
             rfid
 
-# CHECK-BE: mfspr 2, 280                     # encoding: [0x7c,0x58,0x42,0xa6]
-# CHECK-LE: mfspr 2, 280                     # encoding: [0xa6,0x42,0x58,0x7c]
+# CHECK-BE: mfasr 2                          # encoding: [0x7c,0x58,0x42,0xa6]
+# CHECK-LE: mfasr 2                          # encoding: [0xa6,0x42,0x58,0x7c]
             mfasr 2
 # CHECK-BE: mtspr 280, 2                     # encoding: [0x7c,0x58,0x43,0xa6]
 # CHECK-LE: mtspr 280, 2                     # encoding: [0xa6,0x43,0x58,0x7c]
diff --git a/test/MC/PowerPC/ppc64-encoding-fp.s b/test/MC/PowerPC/ppc64-encoding-fp.s
index c19f9b327642..48384845715d 100644
--- a/test/MC/PowerPC/ppc64-encoding-fp.s
+++ b/test/MC/PowerPC/ppc64-encoding-fp.s
@@ -359,15 +359,36 @@
 # CHECK-BE: mffs 2                          # encoding: [0xfc,0x40,0x04,0x8e]
 # CHECK-LE: mffs 2                          # encoding: [0x8e,0x04,0x40,0xfc]
             mffs 2
-# FIXME:    mffs. 2
-
-# FIXME:    mcrfs 2, 3
-
-# FIXME:    mtfsfi 2, 3, 1
-# FIXME:    mtfsfi. 2, 3, 1
-# FIXME:    mtfsf 2, 3, 1, 1
-# FIXME:    mtfsf. 2, 3, 1, 1
-
+# CHECK-BE: mffs. 7                         # encoding: [0xfc,0xe0,0x04,0x8f]
+# CHECK-LE: mffs. 7                         # encoding: [0x8f,0x04,0xe0,0xfc]
+            mffs. 7
+# CHECK-BE: mcrfs 4, 5                      # encoding: [0xfe,0x14,0x00,0x80]
+# CHECK-LE: mcrfs 4, 5                      # encoding: [0x80,0x00,0x14,0xfe]
+            mcrfs 4, 5
+# CHECK-BE: mtfsfi 5, 2, 1                  # encoding: [0xfe,0x81,0x21,0x0c]
+# CHECK-LE: mtfsfi 5, 2, 1                  # encoding: [0x0c,0x21,0x81,0xfe]
+            mtfsfi 5, 2, 1
+# CHECK-BE: mtfsfi. 5, 2, 1                 # encoding: [0xfe,0x81,0x21,0x0d]
+# CHECK-LE: mtfsfi. 5, 2, 1                 # encoding: [0x0d,0x21,0x81,0xfe]
+            mtfsfi. 5, 2, 1
+# CHECK-BE: mtfsfi 6, 2                     # encoding: [0xff,0x00,0x21,0x0c]
+# CHECK-LE: mtfsfi 6, 2                     # encoding: [0x0c,0x21,0x00,0xff]
+            mtfsfi 6, 2
+# CHECK-BE: mtfsfi. 6, 2                    # encoding: [0xff,0x00,0x21,0x0d]
+# CHECK-LE: mtfsfi. 6, 2                    # encoding: [0x0d,0x21,0x00,0xff]
+            mtfsfi. 6, 2
+# CHECK-BE: mtfsf 127, 8, 1, 1              # encoding: [0xfe,0xff,0x45,0x8e]
+# CHECK-LE: mtfsf 127, 8, 1, 1              # encoding: [0x8e,0x45,0xff,0xfe]
+            mtfsf 127, 8, 1, 1
+# CHECK-BE: mtfsf. 125, 8, 1, 1             # encoding: [0xfe,0xfb,0x45,0x8f]
+# CHECK-LE: mtfsf. 125, 8, 1, 1             # encoding: [0x8f,0x45,0xfb,0xfe]
+            mtfsf. 125, 8, 1, 1
+# CHECK-BE: mtfsf 127, 6                    # encoding: [0xfc,0xfe,0x35,0x8e]
+# CHECK-LE: mtfsf 127, 6                    # encoding: [0x8e,0x35,0xfe,0xfc]
+            mtfsf 127, 6
+# CHECK-BE: mtfsf. 125, 6                   # encoding: [0xfc,0xfa,0x35,0x8f]
+# CHECK-LE: mtfsf. 125, 6                   # encoding: [0x8f,0x35,0xfa,0xfc]
+            mtfsf. 125, 6
 # CHECK-BE: mtfsb0 31                       # encoding: [0xff,0xe0,0x00,0x8c]
 # CHECK-LE: mtfsb0 31                       # encoding: [0x8c,0x00,0xe0,0xff]
             mtfsb0 31
diff --git a/test/MC/PowerPC/ppc64-encoding-p8vector.s b/test/MC/PowerPC/ppc64-encoding-p8vector.s
new file mode 100644
index 000000000000..657b7378fb48
--- /dev/null
+++ b/test/MC/PowerPC/ppc64-encoding-p8vector.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
+# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
+
+# CHECK-BE: vpksdss 2, 3, 4                 # encoding: [0x10,0x43,0x25,0xce]
+# CHECK-LE: vpksdss 2, 3, 4                 # encoding: [0xce,0x25,0x43,0x10]
+            vpksdss 2, 3, 4
+
+# CHECK-BE: vpksdus 2, 3, 4                 # encoding: [0x10,0x43,0x25,0x4e]
+# CHECK-LE: vpksdus 2, 3, 4                 # encoding: [0x4e,0x25,0x43,0x10]
+            vpksdus 2, 3, 4
+
+# CHECK-BE: vpkudus 2, 3, 4                 # encoding: [0x10,0x43,0x24,0xce]
+# CHECK-LE: vpkudus 2, 3, 4                 # encoding: [0xce,0x24,0x43,0x10]
+            vpkudus 2, 3, 4
+
+# CHECK-BE: vpkudum 2, 3, 4                 # encoding: [0x10,0x43,0x24,0x4e]
+# CHECK-LE: vpkudum 2, 3, 4                 # encoding: [0x4e,0x24,0x43,0x10]
+            vpkudum 2, 3, 4
+
+# CHECK-BE: vupkhsw 2, 3                    # encoding: [0x10,0x40,0x1e,0x4e]
+# CHECK-LE: vupkhsw 2, 3                    # encoding: [0x4e,0x1e,0x40,0x10]
+            vupkhsw 2, 3
+
+# CHECK-BE: vupklsw 2, 3                    # encoding: [0x10,0x40,0x1e,0xce]
+# CHECK-LE: vupklsw 2, 3                    # encoding: [0xce,0x1e,0x40,0x10]
+            vupklsw 2, 3
diff --git a/test/MC/PowerPC/ppc64-encoding-vmx.s b/test/MC/PowerPC/ppc64-encoding-vmx.s
index 3d2df8414157..51cae3fd2df9 100644
--- a/test/MC/PowerPC/ppc64-encoding-vmx.s
+++ b/test/MC/PowerPC/ppc64-encoding-vmx.s
@@ -133,6 +133,55 @@
 # CHECK-BE: vperm 2, 3, 4, 5                # encoding: [0x10,0x43,0x21,0x6b]
 # CHECK-LE: vperm 2, 3, 4, 5                # encoding: [0x6b,0x21,0x43,0x10]
             vperm 2, 3, 4, 5
+
+# CHECK-BE: vpermxor 2, 3, 4, 5             # encoding: [0x10,0x43,0x21,0x6d]
+# CHECK-LE: vpermxor 2, 3, 4, 5             # encoding: [0x6d,0x21,0x43,0x10]
+            vpermxor 2, 3, 4, 5
+
+# CHECK-BE: vsbox 2, 5                      # encoding: [0x10,0x45,0x05,0xc8]
+# CHECK-LE: vsbox 2, 5                      # encoding: [0xc8,0x05,0x45,0x10]
+            vsbox 2, 5
+
+# CHECK-BE: vcipher 2, 5, 17                # encoding: [0x10,0x45,0x8d,0x08]
+# CHECK-LE: vcipher 2, 5, 17                # encoding: [0x08,0x8d,0x45,0x10]
+            vcipher 2, 5, 17
+
+# CHECK-BE: vcipherlast 2, 5, 17            # encoding: [0x10,0x45,0x8d,0x09]
+# CHECK-LE: vcipherlast 2, 5, 17            # encoding: [0x09,0x8d,0x45,0x10]
+            vcipherlast 2, 5, 17
+
+# CHECK-BE: vncipher 2, 5, 17               # encoding: [0x10,0x45,0x8d,0x48]
+# CHECK-LE: vncipher 2, 5, 17               # encoding: [0x48,0x8d,0x45,0x10]
+            vncipher 2, 5, 17
+
+# CHECK-BE: vncipherlast 2, 5, 17           # encoding: [0x10,0x45,0x8d,0x49]
+# CHECK-LE: vncipherlast 2, 5, 17           # encoding: [0x49,0x8d,0x45,0x10]
+            vncipherlast 2, 5, 17
+
+# CHECK-BE: vpmsumb 2, 5, 17                # encoding: [0x10,0x45,0x8c,0x08]
+# CHECK-LE: vpmsumb 2, 5, 17                # encoding: [0x08,0x8c,0x45,0x10]
+            vpmsumb 2, 5, 17
+
+# CHECK-BE: vpmsumh 2, 5, 17                # encoding: [0x10,0x45,0x8c,0x48]
+# CHECK-LE: vpmsumh 2, 5, 17                # encoding: [0x48,0x8c,0x45,0x10]
+            vpmsumh 2, 5, 17
+
+# CHECK-BE: vpmsumw 2, 5, 17                # encoding: [0x10,0x45,0x8c,0x88]
+# CHECK-LE: vpmsumw 2, 5, 17                # encoding: [0x88,0x8c,0x45,0x10]
+            vpmsumw 2, 5, 17
+
+# CHECK-BE: vpmsumd 2, 5, 17                # encoding: [0x10,0x45,0x8c,0xc8]
+# CHECK-LE: vpmsumd 2, 5, 17                # encoding: [0xc8,0x8c,0x45,0x10]
+            vpmsumd 2, 5, 17
+
+# CHECK-BE: vshasigmaw 2, 3, 0, 11          # encoding: [0x10,0x43,0x5e,0x82]
+# CHECK-LE: vshasigmaw 2, 3, 0, 11          # encoding: [0x82,0x5e,0x43,0x10]
+            vshasigmaw 2, 3, 0, 11
+
+# CHECK-BE: vshasigmad 2, 3, 1, 15          # encoding: [0x10,0x43,0xfe,0xc2]
+# CHECK-LE: vshasigmad 2, 3, 1, 15          # encoding: [0xc2,0xfe,0x43,0x10]
+            vshasigmad 2, 3, 1, 15
+
 # CHECK-BE: vsel 2, 3, 4, 5                 # encoding: [0x10,0x43,0x21,0x6a]
 # CHECK-LE: vsel 2, 3, 4, 5                 # encoding: [0x6a,0x21,0x43,0x10]
             vsel 2, 3, 4, 5
@@ -176,6 +225,9 @@
 # CHECK-BE: vadduwm 2, 3, 4                 # encoding: [0x10,0x43,0x20,0x80]
 # CHECK-LE: vadduwm 2, 3, 4                 # encoding: [0x80,0x20,0x43,0x10]
             vadduwm 2, 3, 4
+# CHECK-BE: vaddudm 2, 3, 4                 # encoding: [0x10,0x43,0x20,0xc0]
+# CHECK-LE: vaddudm 2, 3, 4                 # encoding: [0xc0,0x20,0x43,0x10]
+            vaddudm 2, 3, 4
 # CHECK-BE: vaddubs 2, 3, 4                 # encoding: [0x10,0x43,0x22,0x00]
 # CHECK-LE: vaddubs 2, 3, 4                 # encoding: [0x00,0x22,0x43,0x10]
             vaddubs 2, 3, 4
@@ -185,7 +237,19 @@
 # CHECK-BE: vadduws 2, 3, 4                 # encoding: [0x10,0x43,0x22,0x80]
 # CHECK-LE: vadduws 2, 3, 4                 # encoding: [0x80,0x22,0x43,0x10]
             vadduws 2, 3, 4
-
+# CHECK-BE: vadduqm 2, 3, 4                 # encoding: [0x10,0x43,0x21,0x00]
+# CHECK-LE: vadduqm 2, 3, 4                 # encoding: [0x00,0x21,0x43,0x10]
+            vadduqm 2, 3, 4
+# CHECK-BE: vaddeuqm 2, 3, 4, 5             # encoding: [0x10,0x43,0x21,0x7c]
+# CHECK-LE: vaddeuqm 2, 3, 4, 5             # encoding:	[0x7c,0x21,0x43,0x10]
+            vaddeuqm 2, 3, 4, 5
+# CHECK-BE: vaddcuq 2, 3, 4                 # encoding: [0x10,0x43,0x21,0x40]
+# CHECK-LE: vaddcuq 2, 3, 4                 # encoding: [0x40,0x21,0x43,0x10]
+            vaddcuq 2, 3, 4
+# CHECK-BE: vaddecuq 2, 3, 4, 5             # encoding: [0x10,0x43,0x21,0x7d]
+# CHECK-LE: vaddecuq 2, 3, 4, 5             # encoding: [0x7d,0x21,0x43,0x10]
+            vaddecuq 2, 3, 4, 5   
+	
 # CHECK-BE: vsubcuw 2, 3, 4                 # encoding: [0x10,0x43,0x25,0x80]
 # CHECK-LE: vsubcuw 2, 3, 4                 # encoding: [0x80,0x25,0x43,0x10]
             vsubcuw 2, 3, 4
@@ -207,6 +271,9 @@
 # CHECK-BE: vsubuwm 2, 3, 4                 # encoding: [0x10,0x43,0x24,0x80]
 # CHECK-LE: vsubuwm 2, 3, 4                 # encoding: [0x80,0x24,0x43,0x10]
             vsubuwm 2, 3, 4
+# CHECK-BE: vsubudm 2, 3, 4                 # encoding: [0x10,0x43,0x24,0xc0]
+# CHECK-LE: vsubudm 2, 3, 4                 # encoding: [0xc0,0x24,0x43,0x10]
+            vsubudm 2, 3, 4
 # CHECK-BE: vsububs 2, 3, 4                 # encoding: [0x10,0x43,0x26,0x00]
 # CHECK-LE: vsububs 2, 3, 4                 # encoding: [0x00,0x26,0x43,0x10]
             vsububs 2, 3, 4
@@ -216,31 +283,58 @@
 # CHECK-BE: vsubuws 2, 3, 4                 # encoding: [0x10,0x43,0x26,0x80]
 # CHECK-LE: vsubuws 2, 3, 4                 # encoding: [0x80,0x26,0x43,0x10]
             vsubuws 2, 3, 4
-
+# CHECK-BE: vsubuqm 2, 3, 4                 # encoding: [0x10,0x43,0x25,0x00]
+# CHECK-LE: vsubuqm 2, 3, 4                 # encoding: [0x00,0x25,0x43,0x10]
+            vsubuqm 2, 3, 4
+# CHECK-BE: vsubeuqm 2, 3, 4, 5             # encoding: [0x10,0x43,0x21,0x7e]
+# CHECK-LE: vsubeuqm 2, 3, 4, 5             # encoding: [0x7e,0x21,0x43,0x10]
+            vsubeuqm 2, 3, 4, 5
+# CHECK-BE: vsubcuq 2, 3, 4                 # encoding: [0x10,0x43,0x25,0x40] 
+# CHECK-LE: vsubcuq 2, 3, 4                 # encoding: [0x40,0x25,0x43,0x10]
+            vsubcuq 2, 3, 4
+# CHECK-BE: vsubecuq 2, 3, 4, 5             # encoding: [0x10,0x43,0x21,0x7f]
+# CHECK-LE: vsubecuq 2, 3, 4, 5             # encoding: [0x7f,0x21,0x43,0x10]
+            vsubecuq 2, 3, 4, 5	
+	
 # CHECK-BE: vmulesb 2, 3, 4                 # encoding: [0x10,0x43,0x23,0x08]
 # CHECK-LE: vmulesb 2, 3, 4                 # encoding: [0x08,0x23,0x43,0x10]
             vmulesb 2, 3, 4
 # CHECK-BE: vmulesh 2, 3, 4                 # encoding: [0x10,0x43,0x23,0x48]
 # CHECK-LE: vmulesh 2, 3, 4                 # encoding: [0x48,0x23,0x43,0x10]
             vmulesh 2, 3, 4
+# CHECK-BE: vmulesw 2, 3, 4                 # encoding: [0x10,0x43,0x23,0x88]
+# CHECK-LE: vmulesw 2, 3, 4                 # encoding: [0x88,0x23,0x43,0x10]
+            vmulesw 2, 3, 4
 # CHECK-BE: vmuleub 2, 3, 4                 # encoding: [0x10,0x43,0x22,0x08]
 # CHECK-LE: vmuleub 2, 3, 4                 # encoding: [0x08,0x22,0x43,0x10]
             vmuleub 2, 3, 4
 # CHECK-BE: vmuleuh 2, 3, 4                 # encoding: [0x10,0x43,0x22,0x48]
 # CHECK-LE: vmuleuh 2, 3, 4                 # encoding: [0x48,0x22,0x43,0x10]
             vmuleuh 2, 3, 4
+# CHECK-BE: vmuleuw 2, 3, 4                 # encoding: [0x10,0x43,0x22,0x88]
+# CHECK-LE: vmuleuw 2, 3, 4                 # encoding: [0x88,0x22,0x43,0x10]
+            vmuleuw 2, 3, 4
 # CHECK-BE: vmulosb 2, 3, 4                 # encoding: [0x10,0x43,0x21,0x08]
 # CHECK-LE: vmulosb 2, 3, 4                 # encoding: [0x08,0x21,0x43,0x10]
             vmulosb 2, 3, 4
 # CHECK-BE: vmulosh 2, 3, 4                 # encoding: [0x10,0x43,0x21,0x48]
 # CHECK-LE: vmulosh 2, 3, 4                 # encoding: [0x48,0x21,0x43,0x10]
             vmulosh 2, 3, 4
+# CHECK-BE: vmulosw 2, 3, 4                 # encoding: [0x10,0x43,0x21,0x88]
+# CHECK-LE: vmulosw 2, 3, 4                 # encoding: [0x88,0x21,0x43,0x10]
+            vmulosw 2, 3, 4
 # CHECK-BE: vmuloub 2, 3, 4                 # encoding: [0x10,0x43,0x20,0x08]
 # CHECK-LE: vmuloub 2, 3, 4                 # encoding: [0x08,0x20,0x43,0x10]
             vmuloub 2, 3, 4
 # CHECK-BE: vmulouh 2, 3, 4                 # encoding: [0x10,0x43,0x20,0x48]
 # CHECK-LE: vmulouh 2, 3, 4                 # encoding: [0x48,0x20,0x43,0x10]
             vmulouh 2, 3, 4
+# CHECK-BE: vmulouw 2, 3, 4                 # encoding: [0x10,0x43,0x20,0x88]
+# CHECK-LE: vmulouw 2, 3, 4                 # encoding: [0x88,0x20,0x43,0x10]
+            vmulouw 2, 3, 4
+# CHECK-BE: vmuluwm 2, 3, 4                 # encoding: [0x10,0x43,0x20,0x89]
+# CHECK-LE: vmuluwm 2, 3, 4                 # encoding: [0x89,0x20,0x43,0x10]
+            vmuluwm 2, 3, 4
 
 # CHECK-BE: vmhaddshs 2, 3, 4, 5            # encoding: [0x10,0x43,0x21,0x60]
 # CHECK-LE: vmhaddshs 2, 3, 4, 5            # encoding: [0x60,0x21,0x43,0x10]
@@ -314,6 +408,9 @@
 # CHECK-BE: vmaxsw 2, 3, 4                  # encoding: [0x10,0x43,0x21,0x82]
 # CHECK-LE: vmaxsw 2, 3, 4                  # encoding: [0x82,0x21,0x43,0x10]
             vmaxsw 2, 3, 4
+# CHECK-BE: vmaxsd 2, 3, 4                  # encoding: [0x10,0x43,0x21,0xc2]
+# CHECK-LE: vmaxsd 2, 3, 4                    # encoding: [0xc2,0x21,0x43,0x10]
+            vmaxsd 2, 3, 4
 # CHECK-BE: vmaxub 2, 3, 4                  # encoding: [0x10,0x43,0x20,0x02]
 # CHECK-LE: vmaxub 2, 3, 4                  # encoding: [0x02,0x20,0x43,0x10]
             vmaxub 2, 3, 4
@@ -323,7 +420,10 @@
 # CHECK-BE: vmaxuw 2, 3, 4                  # encoding: [0x10,0x43,0x20,0x82]
 # CHECK-LE: vmaxuw 2, 3, 4                  # encoding: [0x82,0x20,0x43,0x10]
             vmaxuw 2, 3, 4
-
+# CHECK-BE: vmaxud 2, 3, 4                  # encoding: [0x10,0x43,0x20,0xc2]
+# CHECK-LE: vmaxud 2, 3, 4                  # encoding: [0xc2,0x20,0x43,0x10]
+            vmaxud 2, 3, 4
+        
 # CHECK-BE: vminsb 2, 3, 4                  # encoding: [0x10,0x43,0x23,0x02]
 # CHECK-LE: vminsb 2, 3, 4                  # encoding: [0x02,0x23,0x43,0x10]
             vminsb 2, 3, 4
@@ -333,6 +433,9 @@
 # CHECK-BE: vminsw 2, 3, 4                  # encoding: [0x10,0x43,0x23,0x82]
 # CHECK-LE: vminsw 2, 3, 4                  # encoding: [0x82,0x23,0x43,0x10]
             vminsw 2, 3, 4
+# CHECK-BE: vminsd 2, 3, 4                  # encoding: [0x10,0x43,0x23,0xc2]
+# CHECK-LE: vminsd 2, 3, 4                  # encoding: [0xc2,0x23,0x43,0x10]
+            vminsd 2, 3, 4
 # CHECK-BE: vminub 2, 3, 4                  # encoding: [0x10,0x43,0x22,0x02]
 # CHECK-LE: vminub 2, 3, 4                  # encoding: [0x02,0x22,0x43,0x10]
             vminub 2, 3, 4
@@ -342,6 +445,9 @@
 # CHECK-BE: vminuw 2, 3, 4                  # encoding: [0x10,0x43,0x22,0x82]
 # CHECK-LE: vminuw 2, 3, 4                  # encoding: [0x82,0x22,0x43,0x10]
             vminuw 2, 3, 4
+# CHECK-BE: vminud 2, 3, 4                  # encoding: [0x10,0x43,0x22,0xc2]
+# CHECK-LE: vminud 2, 3, 4                  # encoding: [0xc2,0x22,0x43,0x10]
+            vminud 2, 3, 4
 
 # Vector integer compare instructions
 
@@ -363,6 +469,12 @@
 # CHECK-BE: vcmpequw. 2, 3, 4               # encoding: [0x10,0x43,0x24,0x86]
 # CHECK-LE: vcmpequw. 2, 3, 4               # encoding: [0x86,0x24,0x43,0x10]
             vcmpequw. 2, 3, 4
+# CHECK-BE: vcmpequd 2, 3, 4                # encoding: [0x10,0x43,0x20,0xc7]
+# CHECK-LE: vcmpequd 2, 3, 4                # encoding: [0xc7,0x20,0x43,0x10]
+            vcmpequd 2, 3, 4
+# CHECK-BE: vcmpequd. 2, 3, 4               # encoding: [0x10,0x43,0x24,0xc7]
+# CHECK-LE: vcmpequd. 2, 3, 4               # encoding: [0xc7,0x24,0x43,0x10]
+            vcmpequd. 2, 3, 4
 # CHECK-BE: vcmpgtsb 2, 3, 4                # encoding: [0x10,0x43,0x23,0x06]
 # CHECK-LE: vcmpgtsb 2, 3, 4                # encoding: [0x06,0x23,0x43,0x10]
             vcmpgtsb 2, 3, 4
@@ -381,6 +493,12 @@
 # CHECK-BE: vcmpgtsw. 2, 3, 4               # encoding: [0x10,0x43,0x27,0x86]
 # CHECK-LE: vcmpgtsw. 2, 3, 4               # encoding: [0x86,0x27,0x43,0x10]
             vcmpgtsw. 2, 3, 4
+# CHECK-BE: vcmpgtsd 2, 3, 4                # encoding: [0x10,0x43,0x23,0xc7]
+# CHECK-LE: vcmpgtsd 2, 3, 4                # encoding: [0xc7,0x23,0x43,0x10]
+            vcmpgtsd 2, 3, 4
+# CHECK-BE: vcmpgtsd. 2, 3, 4               # encoding: [0x10,0x43,0x27,0xc7]
+# CHECK-LE: vcmpgtsd. 2, 3, 4               # encoding: [0xc7,0x27,0x43,0x10]
+            vcmpgtsd. 2, 3, 4
 # CHECK-BE: vcmpgtub 2, 3, 4                # encoding: [0x10,0x43,0x22,0x06]
 # CHECK-LE: vcmpgtub 2, 3, 4                # encoding: [0x06,0x22,0x43,0x10]
             vcmpgtub 2, 3, 4
@@ -399,7 +517,13 @@
 # CHECK-BE: vcmpgtuw. 2, 3, 4               # encoding: [0x10,0x43,0x26,0x86]
 # CHECK-LE: vcmpgtuw. 2, 3, 4               # encoding: [0x86,0x26,0x43,0x10]
             vcmpgtuw. 2, 3, 4
-
+# CHECK-BE: vcmpgtud 2, 3, 4                # encoding: [0x10,0x43,0x22,0xc7]
+# CHECK-LE: vcmpgtud 2, 3, 4                # encoding: [0xc7,0x22,0x43,0x10]
+            vcmpgtud 2, 3, 4
+# CHECK-BE: vcmpgtud. 2, 3, 4               # encoding: [0x10,0x43,0x26,0xc7]
+# CHECK-LE: vcmpgtud. 2, 3, 4               # encoding: [0xc7,0x26,0x43,0x10]
+            vcmpgtud. 2, 3, 4
+        
 # Vector integer logical instructions
 
 # CHECK-BE: vand 2, 3, 4                    # encoding: [0x10,0x43,0x24,0x04]
@@ -408,6 +532,15 @@
 # CHECK-BE: vandc 2, 3, 4                   # encoding: [0x10,0x43,0x24,0x44]
 # CHECK-LE: vandc 2, 3, 4                   # encoding: [0x44,0x24,0x43,0x10]
             vandc 2, 3, 4
+# CHECK-BE: veqv 2, 3, 4                    # encoding: [0x10,0x43,0x26,0x84]
+# CHECK-LE: veqv 2, 3, 4                    # encoding: [0x84,0x26,0x43,0x10]
+            veqv 2, 3, 4
+# CHECK-BE: vnand 2, 3, 4                   # encoding: [0x10,0x43,0x25,0x84]
+# CHECK-LE: vnand 2, 3, 4                   # encoding: [0x84,0x25,0x43,0x10]
+            vnand 2, 3, 4
+# CHECK-BE: vorc 2, 3, 4                    # encoding: [0x10,0x43,0x25,0x44]
+# CHECK-LE: vorc 2, 3, 4                    # encoding: [0x44,0x25,0x43,0x10]
+            vorc 2, 3, 4
 # CHECK-BE: vnor 2, 3, 4                    # encoding: [0x10,0x43,0x25,0x04]
 # CHECK-LE: vnor 2, 3, 4                    # encoding: [0x04,0x25,0x43,0x10]
             vnor 2, 3, 4
@@ -429,7 +562,9 @@
 # CHECK-BE: vrlw 2, 3, 4                    # encoding: [0x10,0x43,0x20,0x84]
 # CHECK-LE: vrlw 2, 3, 4                    # encoding: [0x84,0x20,0x43,0x10]
             vrlw 2, 3, 4
-
+# CHECK-BE: vrld 2, 3, 4                    # encoding: [0x10,0x43,0x20,0xc4]
+# CHECK-LE: vrld 2, 3, 4                    # encoding: [0xc4,0x20,0x43,0x10]
+            vrld 2, 3, 4
 # CHECK-BE: vslb 2, 3, 4                    # encoding: [0x10,0x43,0x21,0x04]
 # CHECK-LE: vslb 2, 3, 4                    # encoding: [0x04,0x21,0x43,0x10]
             vslb 2, 3, 4
@@ -439,6 +574,9 @@
 # CHECK-BE: vslw 2, 3, 4                    # encoding: [0x10,0x43,0x21,0x84]
 # CHECK-LE: vslw 2, 3, 4                    # encoding: [0x84,0x21,0x43,0x10]
             vslw 2, 3, 4
+# CHECK-BE: vsld 2, 3, 4                    # encoding: [0x10,0x43,0x25,0xc4]
+# CHECK-LE: vsld 2, 3, 4                    # encoding: [0xc4,0x25,0x43,0x10]
+            vsld 2, 3, 4
 # CHECK-BE: vsrb 2, 3, 4                    # encoding: [0x10,0x43,0x22,0x04]
 # CHECK-LE: vsrb 2, 3, 4                    # encoding: [0x04,0x22,0x43,0x10]
             vsrb 2, 3, 4
@@ -448,6 +586,9 @@
 # CHECK-BE: vsrw 2, 3, 4                    # encoding: [0x10,0x43,0x22,0x84]
 # CHECK-LE: vsrw 2, 3, 4                    # encoding: [0x84,0x22,0x43,0x10]
             vsrw 2, 3, 4
+# CHECK-BE: vsrd 2, 3, 4                    # encoding: [0x10,0x43,0x26,0xc4]
+# CHECK-LE: vsrd 2, 3, 4                    # encoding: [0xc4,0x26,0x43,0x10]
+            vsrd 2, 3, 4
 # CHECK-BE: vsrab 2, 3, 4                   # encoding: [0x10,0x43,0x23,0x04]
 # CHECK-LE: vsrab 2, 3, 4                   # encoding: [0x04,0x23,0x43,0x10]
             vsrab 2, 3, 4
@@ -457,6 +598,9 @@
 # CHECK-BE: vsraw 2, 3, 4                   # encoding: [0x10,0x43,0x23,0x84]
 # CHECK-LE: vsraw 2, 3, 4                   # encoding: [0x84,0x23,0x43,0x10]
             vsraw 2, 3, 4
+# CHECK-BE: vsrad 2, 3, 4                   # encoding: [0x10,0x43,0x23,0xc4]
+# CHECK-LE: vsrad 2, 3, 4                   # encoding: [0xc4,0x23,0x43,0x10]
+            vsrad 2, 3, 4
 
 # Vector floating-point instructions
 
@@ -543,6 +687,40 @@
 # CHECK-LE: vrsqrtefp 2, 3                  # encoding: [0x4a,0x19,0x40,0x10]
             vrsqrtefp 2, 3
 
+# Vector count leading zero instructions
+# CHECK-BE: vclzb 2, 3                      # encoding: [0x10,0x40,0x1f,0x02]
+# CHECK-LE: vclzb 2, 3                      # encoding: [0x02,0x1f,0x40,0x10]
+            vclzb 2, 3
+
+# CHECK-BE: vclzh 2, 3                      # encoding: [0x10,0x40,0x1f,0x42]
+# CHECK-LE: vclzh 2, 3                      # encoding: [0x42,0x1f,0x40,0x10]
+            vclzh 2, 3
+
+# CHECK-BE: vclzw 2, 3                      # encoding: [0x10,0x40,0x1f,0x82]
+# CHECK-LE: vclzw 2, 3                      # encoding: [0x82,0x1f,0x40,0x10]
+            vclzw 2, 3
+
+# CHECK-BE: vclzd 2, 3                      # encoding: [0x10,0x40,0x1f,0xc2]
+# CHECK-LE: vclzd 2, 3                      # encoding: [0xc2,0x1f,0x40,0x10]
+            vclzd 2, 3                      
+
+# Vector population count instructions
+# CHECK-BE: vpopcntb 2, 3                   # encoding: [0x10,0x40,0x1f,0x03]
+# CHECK-LE: vpopcntb 2, 3                   # encoding: [0x03,0x1f,0x40,0x10]
+            vpopcntb 2, 3
+
+# CHECK-BE: vpopcnth 2, 3                   # encoding: [0x10,0x40,0x1f,0x43]
+# CHECK-LE: vpopcnth 2, 3                   # encoding: [0x43,0x1f,0x40,0x10]
+            vpopcnth 2, 3
+
+# CHECK-BE: vpopcntw 2, 3                   # encoding: [0x10,0x40,0x1f,0x83]
+# CHECK-LE: vpopcntw 2, 3                   # encoding: [0x83,0x1f,0x40,0x10]
+            vpopcntw 2, 3
+        
+# BCHECK-BE: vpopcntd 2, 3                   # encoding: [0x10,0x40,0x1f,0xC3]
+# BCHECK-LE: vpopcntd 2, 3                   # encoding: [0xC3,0x1f,0x40,0x10]
+#            vpopcntd 2, 3
+        
 # Vector status and control register instructions
 
 # CHECK-BE: mtvscr 2                        # encoding: [0x10,0x00,0x16,0x44]
diff --git a/test/MC/PowerPC/ppc64-encoding.s b/test/MC/PowerPC/ppc64-encoding.s
index 6d09dfd8e5fc..4a698adadda3 100644
--- a/test/MC/PowerPC/ppc64-encoding.s
+++ b/test/MC/PowerPC/ppc64-encoding.s
@@ -27,23 +27,23 @@
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs
             bla target
 
-# CHECK-BE: bc 4, 10, target                # encoding: [0x40,0x8a,A,0bAAAAAA00]
-# CHECK-LE: bc 4, 10, target                # encoding: [0bAAAAAA00,A,0x8a,0x40]
+# CHECK-BE: bf 10, target                   # encoding: [0x40,0x8a,A,0bAAAAAA00]
+# CHECK-LE: bf 10, target                   # encoding: [0bAAAAAA00,A,0x8a,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bc 4, 10, target
-# CHECK-BE: bca 4, 10, target               # encoding: [0x40,0x8a,A,0bAAAAAA10]
-# CHECK-LE: bca 4, 10, target               # encoding: [0bAAAAAA10,A,0x8a,0x40]
+# CHECK-BE: bfa 10, target                  # encoding: [0x40,0x8a,A,0bAAAAAA10]
+# CHECK-LE: bfa 10, target                  # encoding: [0bAAAAAA10,A,0x8a,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bca 4, 10, target
-# CHECK-BE: bcl 4, 10, target               # encoding: [0x40,0x8a,A,0bAAAAAA01]
-# CHECK-LE: bcl 4, 10, target               # encoding: [0bAAAAAA01,A,0x8a,0x40]
+# CHECK-BE: bfl 10, target                  # encoding: [0x40,0x8a,A,0bAAAAAA01]
+# CHECK-LE: bfl 10, target                  # encoding: [0bAAAAAA01,A,0x8a,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
             bcl 4, 10, target
-# CHECK-BE: bcla 4, 10, target              # encoding: [0x40,0x8a,A,0bAAAAAA11]
-# CHECK-LE: bcla 4, 10, target              # encoding: [0bAAAAAA11,A,0x8a,0x40]
+# CHECK-BE: bfla 10, target                 # encoding: [0x40,0x8a,A,0bAAAAAA11]
+# CHECK-LE: bfla 10, target                 # encoding: [0bAAAAAA11,A,0x8a,0x40]
 # CHECK-BE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
 # CHECK-LE-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
             bcla 4, 10, target
@@ -51,26 +51,26 @@
 # CHECK-BE: bclr 4, 10, 3                   # encoding: [0x4c,0x8a,0x18,0x20]
 # CHECK-LE: bclr 4, 10, 3                   # encoding: [0x20,0x18,0x8a,0x4c]
             bclr 4, 10, 3
-# CHECK-BE: bclr 4, 10, 0                   # encoding: [0x4c,0x8a,0x00,0x20]
-# CHECK-LE: bclr 4, 10, 0                   # encoding: [0x20,0x00,0x8a,0x4c]
+# CHECK-BE: bclr 4, 10                      # encoding: [0x4c,0x8a,0x00,0x20]
+# CHECK-LE: bclr 4, 10                      # encoding: [0x20,0x00,0x8a,0x4c]
             bclr 4, 10
 # CHECK-BE: bclrl 4, 10, 3                  # encoding: [0x4c,0x8a,0x18,0x21]
 # CHECK-LE: bclrl 4, 10, 3                  # encoding: [0x21,0x18,0x8a,0x4c]
             bclrl 4, 10, 3
-# CHECK-BE: bclrl 4, 10, 0                  # encoding: [0x4c,0x8a,0x00,0x21]
-# CHECK-LE: bclrl 4, 10, 0                  # encoding: [0x21,0x00,0x8a,0x4c]
+# CHECK-BE: bclrl 4, 10                     # encoding: [0x4c,0x8a,0x00,0x21]
+# CHECK-LE: bclrl 4, 10                     # encoding: [0x21,0x00,0x8a,0x4c]
             bclrl 4, 10
 # CHECK-BE: bcctr 4, 10, 3                  # encoding: [0x4c,0x8a,0x1c,0x20]
 # CHECK-LE: bcctr 4, 10, 3                  # encoding: [0x20,0x1c,0x8a,0x4c]
             bcctr 4, 10, 3
-# CHECK-BE: bcctr 4, 10, 0                  # encoding: [0x4c,0x8a,0x04,0x20]
-# CHECK-LE: bcctr 4, 10, 0                  # encoding: [0x20,0x04,0x8a,0x4c]
+# CHECK-BE: bcctr 4, 10                     # encoding: [0x4c,0x8a,0x04,0x20]
+# CHECK-LE: bcctr 4, 10                     # encoding: [0x20,0x04,0x8a,0x4c]
             bcctr 4, 10
 # CHECK-BE: bcctrl 4, 10, 3                 # encoding: [0x4c,0x8a,0x1c,0x21]
 # CHECK-LE: bcctrl 4, 10, 3                 # encoding: [0x21,0x1c,0x8a,0x4c]
             bcctrl 4, 10, 3
-# CHECK-BE: bcctrl 4, 10, 0                 # encoding: [0x4c,0x8a,0x04,0x21]
-# CHECK-LE: bcctrl 4, 10, 0                 # encoding: [0x21,0x04,0x8a,0x4c]
+# CHECK-BE: bcctrl 4, 10                    # encoding: [0x4c,0x8a,0x04,0x21]
+# CHECK-LE: bcctrl 4, 10                    # encoding: [0x21,0x04,0x8a,0x4c]
             bcctrl 4, 10
 
 # Condition register instructions
@@ -108,10 +108,22 @@
 # CHECK-BE: sc 1                            # encoding: [0x44,0x00,0x00,0x22]
 # CHECK-LE: sc 1                            # encoding: [0x22,0x00,0x00,0x44]
             sc 1
-# CHECK-BE: sc 0                            # encoding: [0x44,0x00,0x00,0x02]
-# CHECK-LE: sc 0                            # encoding: [0x02,0x00,0x00,0x44]
+# CHECK-BE: sc                              # encoding: [0x44,0x00,0x00,0x02]
+# CHECK-LE: sc                              # encoding: [0x02,0x00,0x00,0x44]
             sc
 
+# Branch history rolling buffer
+
+# CHECK-BE: clrbhrb                         # encoding: [0x7c,0x00,0x03,0x5c]
+# CHECK-LE: clrbhrb                         # encoding: [0x5c,0x03,0x00,0x7c]
+            clrbhrb
+# CHECK-BE: mfbhrbe 9, 983                  # encoding: [0x7d,0x3e,0xba,0x5c]
+# CHECK-LE: mfbhrbe 9, 983                  # encoding: [0x5c,0xba,0x3e,0x7d]
+            mfbhrbe 9, 983
+# CHECK-BE: rfebb 1                         # encoding: [0x4c,0x00,0x09,0x24]
+# CHECK-LE: rfebb 1                         # encoding: [0x24,0x09,0x00,0x4c]
+            rfebb 1
+
 # Fixed-point facility
 
 # Fixed-point load instructions
@@ -420,12 +432,20 @@
             divwu. 2, 3, 4
 # FIXME:    divwuo 2, 3, 4
 # FIXME:    divwuo. 2, 3, 4
-# FIXME:    divwe 2, 3, 4
-# FIXME:    divwe. 2, 3, 4
+# CHECK-BE: divwe 2, 3, 4                   # encoding: [0x7c,0x43,0x23,0x56]
+# CHECK-LE: divwe 2, 3, 4                   # encoding: [0x56,0x23,0x43,0x7c]
+            divwe 2, 3, 4
+# CHECK-BE: divwe. 2, 3, 4                  # encoding: [0x7c,0x43,0x23,0x57]
+# CHECK-LE: divwe. 2, 3, 4                  # encoding: [0x57,0x23,0x43,0x7c]
+            divwe. 2, 3, 4
 # FIXME:    divweo 2, 3, 4
 # FIXME:    divweo. 2, 3, 4
-# FIXME:    divweu 2, 3, 4
-# FIXME:    divweu. 2, 3, 4
+# CHECK-BE: divweu 2, 3, 4                  # encoding: [0x7c,0x43,0x23,0x16]
+# CHECK-LE: divweu 2, 3, 4                  # encoding: [0x16,0x23,0x43,0x7c]
+            divweu 2, 3, 4
+# CHECK-BE: divweu. 2, 3, 4                 # encoding: [0x7c,0x43,0x23,0x17]
+# CHECK-LE: divweu. 2, 3, 4                 # encoding: [0x17,0x23,0x43,0x7c]
+            divweu. 2, 3, 4
 # FIXME:    divweuo 2, 3, 4
 # FIXME:    divweuo. 2, 3, 4
 
@@ -466,12 +486,20 @@
             divdu. 2, 3, 4
 # FIXME:    divduo 2, 3, 4
 # FIXME:    divduo. 2, 3, 4
-# FIXME:    divde 2, 3, 4
-# FIXME:    divde. 2, 3, 4
+# CHECK-BE: divde 2, 3, 4                   # encoding: [0x7c,0x43,0x23,0x52]
+# CHECK-LE: divde 2, 3, 4                   # encoding: [0x52,0x23,0x43,0x7c]
+            divde 2, 3, 4
+# CHECK-BE: divde. 2, 3, 4                  # encoding: [0x7c,0x43,0x23,0x53]
+# CHECK-LE: divde. 2, 3, 4                  # encoding: [0x53,0x23,0x43,0x7c]
+            divde. 2, 3, 4
 # FIXME:    divdeo 2, 3, 4
 # FIXME:    divdeo. 2, 3, 4
-# FIXME:    divdeu 2, 3, 4
-# FIXME:    divdeu. 2, 3, 4
+# CHECK-BE: divdeu 2, 3, 4                  # encoding: [0x7c,0x43,0x23,0x12]
+# CHECK-LE: divdeu 2, 3, 4                  # encoding: [0x12,0x23,0x43,0x7c]
+            divdeu 2, 3, 4
+# CHECK-BE: divdeu. 2, 3, 4                 # encoding: [0x7c,0x43,0x23,0x13]
+# CHECK-LE: divdeu. 2, 3, 4                 # encoding: [0x13,0x23,0x43,0x7c]
+            divdeu. 2, 3, 4
 # FIXME:    divdeuo 2, 3, 4
 # FIXME:    divdeuo. 2, 3, 4
 
@@ -505,17 +533,17 @@
 
 # Fixed-point trap instructions
 
-# CHECK-BE: twi 2, 3, 4                     # encoding: [0x0c,0x43,0x00,0x04]
-# CHECK-LE: twi 2, 3, 4                     # encoding: [0x04,0x00,0x43,0x0c]
+# CHECK-BE: twllti 3, 4                     # encoding: [0x0c,0x43,0x00,0x04]
+# CHECK-LE: twllti 3, 4                     # encoding: [0x04,0x00,0x43,0x0c]
             twi 2, 3, 4
-# CHECK-BE: tw 2, 3, 4                      # encoding: [0x7c,0x43,0x20,0x08]
-# CHECK-LE: tw 2, 3, 4                      # encoding: [0x08,0x20,0x43,0x7c]
+# CHECK-BE: twllt 3, 4                      # encoding: [0x7c,0x43,0x20,0x08]
+# CHECK-LE: twllt 3, 4                      # encoding: [0x08,0x20,0x43,0x7c]
             tw 2, 3, 4
-# CHECK-BE: tdi 2, 3, 4                     # encoding: [0x08,0x43,0x00,0x04]
-# CHECK-LE: tdi 2, 3, 4                     # encoding: [0x04,0x00,0x43,0x08]
+# CHECK-BE: tdllti 3, 4                     # encoding: [0x08,0x43,0x00,0x04]
+# CHECK-LE: tdllti 3, 4                     # encoding: [0x04,0x00,0x43,0x08]
             tdi 2, 3, 4
-# CHECK-BE: td 2, 3, 4                      # encoding: [0x7c,0x43,0x20,0x88]
-# CHECK-LE: td 2, 3, 4                      # encoding: [0x88,0x20,0x43,0x7c]
+# CHECK-BE: tdllt 3, 4                      # encoding: [0x7c,0x43,0x20,0x88]
+# CHECK-LE: tdllt 3, 4                      # encoding: [0x88,0x20,0x43,0x7c]
             td 2, 3, 4
 
 # Fixed-point select
@@ -606,12 +634,18 @@
 # CHECK-LE: extsh. 2, 3                     # encoding: [0x35,0x07,0x62,0x7c]
             extsh. 2, 3
 
-# CHECK-BE: cntlzw 2, 3                     # encoding: [0x7c,0x62,0x00,0x34]
-# CHECK-LE: cntlzw 2, 3                     # encoding: [0x34,0x00,0x62,0x7c]
+# CHECK-BE: cntlz 2, 3                     # encoding: [0x7c,0x62,0x00,0x34]
+# CHECK-LE: cntlz 2, 3                     # encoding: [0x34,0x00,0x62,0x7c]
             cntlzw 2, 3
-# CHECK-BE: cntlzw. 2, 3                    # encoding: [0x7c,0x62,0x00,0x35]
-# CHECK-LE: cntlzw. 2, 3                    # encoding: [0x35,0x00,0x62,0x7c]
+# CHECK-BE: cntlz. 2, 3                    # encoding: [0x7c,0x62,0x00,0x35]
+# CHECK-LE: cntlz. 2, 3                    # encoding: [0x35,0x00,0x62,0x7c]
             cntlzw. 2, 3
+# CHECK-BE: cntlz 2, 3                     # encoding: [0x7c,0x62,0x00,0x34]
+# CHECK-LE: cntlz 2, 3                     # encoding: [0x34,0x00,0x62,0x7c]
+            cntlz  2, 3
+# CHECK-BE: cntlz. 2, 3                    # encoding: [0x7c,0x62,0x00,0x35]
+# CHECK-LE: cntlz. 2, 3                    # encoding: [0x35,0x00,0x62,0x7c]
+            cntlz.  2, 3
             cmpb 7, 21, 4
 # CHECK-BE: cmpb 7, 21, 4                   # encoding: [0x7e,0xa7,0x23,0xf8]
 # CHECK-LE: cmpb 7, 21, 4                   # encoding: [0xf8,0x23,0xa7,0x7e]
@@ -638,7 +672,9 @@
 # CHECK-BE: popcntd 2, 3                    # encoding: [0x7c,0x62,0x03,0xf4]
 # CHECK-LE: popcntd 2, 3                    # encoding: [0xf4,0x03,0x62,0x7c]
             popcntd 2, 3
-# FIXME:    bpermd 2, 3, 4
+# CHECK-BE: bpermd 2, 3, 4                  # encoding: [0x7c,0x62,0x21,0xf8]
+# CHECK-LE: bpermd 2, 3, 4                  # encoding: [0xf8,0x21,0x62,0x7c]
+            bpermd 2, 3, 4
 
 # Fixed-point rotate and shift instructions
 
@@ -697,6 +733,33 @@
 # CHECK-LE: rldimi. 2, 3, 4, 5              # encoding: [0x4d,0x21,0x62,0x78]
             rldimi. 2, 3, 4, 5
 
+# Aliases that take bit masks...
+
+# CHECK-BE: rlwinm  0, 0, 30, 31, 31        # encoding: [0x54,0x00,0xf7,0xfe]
+            rlwinm  0, 0, 30, 1
+# CHECK-BE: rlwinm. 0, 0, 30, 31, 31        # encoding: [0x54,0x00,0xf7,0xff]
+            rlwinm. 0, 0, 30, 1
+# CHECK-BE: rlwinm  0, 0, 30, 31, 0         # encoding: [0x54,0x00,0xf7,0xc0]
+            rlwinm  0, 0, 30, 2147483649
+# CHECK-BE: rlwinm. 0, 0, 30, 31, 0         # encoding: [0x54,0x00,0xf7,0xc1]
+            rlwinm. 0, 0, 30, 2147483649
+# CHECK-BE: rlwimi  0, 0, 30, 31, 31        # encoding: [0x50,0x00,0xf7,0xfe]
+            rlwimi  0, 0, 30, 1
+# CHECK-BE: rlwimi. 0, 0, 30, 31, 31        # encoding: [0x50,0x00,0xf7,0xff]
+            rlwimi. 0, 0, 30, 1
+# CHECK-BE: rlwimi  0, 0, 30, 31, 0         # encoding: [0x50,0x00,0xf7,0xc0]
+            rlwimi  0, 0, 30, 2147483649
+# CHECK-BE: rlwimi. 0, 0, 30, 31, 0         # encoding: [0x50,0x00,0xf7,0xc1]
+            rlwimi. 0, 0, 30, 2147483649
+# CHECK-BE: rlwnm   0, 0, 30, 31, 31        # encoding: [0x5c,0x00,0xf7,0xfe]
+            rlwnm  0, 0, 30, 1
+# CHECK-BE: rlwnm.  0, 0, 30, 31, 31        # encoding: [0x5c,0x00,0xf7,0xff]
+            rlwnm. 0, 0, 30, 1
+# CHECK-BE: rlwnm   0, 0, 30, 31, 0         # encoding: [0x5c,0x00,0xf7,0xc0]
+            rlwnm  0, 0, 30, 2147483649
+# CHECK-BE: rlwnm.  0, 0, 30, 31, 0         # encoding: [0x5c,0x00,0xf7,0xc1]
+            rlwnm. 0, 0, 30, 2147483649
+
 # CHECK-BE: slw 2, 3, 4                     # encoding: [0x7c,0x62,0x20,0x30]
 # CHECK-LE: slw 2, 3, 4                     # encoding: [0x30,0x20,0x62,0x7c]
             slw 2, 3, 4
diff --git a/test/MC/PowerPC/ppc64-initial-cfa.s b/test/MC/PowerPC/ppc64-initial-cfa.s
index d0bc6b3ecd74..ca97e1b96b07 100644
--- a/test/MC/PowerPC/ppc64-initial-cfa.s
+++ b/test/MC/PowerPC/ppc64-initial-cfa.s
@@ -28,8 +28,8 @@ _proc:
 # STATIC-NEXT:   Relocations [
 # STATIC-NEXT:   ]
 # STATIC-NEXT:   SectionData (
-# STATIC-BE-NEXT:  0000: 00000010 00000000 037A5200 04784101
-# STATIC-LE-NEXT:  0000: 10000000 00000000 037A5200 04784101
+# STATIC-BE-NEXT:  0000: 00000010 00000000 017A5200 04784101
+# STATIC-LE-NEXT:  0000: 10000000 00000000 017A5200 04784101
 # STATIC-BE-NEXT:  0010: 1B0C0100 00000010 00000018 00000000
 # STATIC-LE-NEXT:  0010: 1B0C0100 10000000 18000000 00000000
 # STATIC-BE-NEXT:  0020: 00000004 00000000
@@ -69,8 +69,8 @@ _proc:
 # PIC-NEXT:   Relocations [
 # PIC-NEXT:   ]
 # PIC-NEXT:   SectionData (
-# PIC-BE-NEXT:  0000: 00000010 00000000 037A5200 04784101
-# PIC-LE-NEXT:  0000: 10000000 00000000 037A5200 04784101
+# PIC-BE-NEXT:  0000: 00000010 00000000 017A5200 04784101
+# PIC-LE-NEXT:  0000: 10000000 00000000 017A5200 04784101
 # PIC-BE-NEXT:  0010: 1B0C0100 00000010 00000018 00000000
 # PIC-LE-NEXT:  0010: 1B0C0100 10000000 18000000 00000000
 # PIC-BE-NEXT:  0020: 00000004 00000000
diff --git a/test/MC/PowerPC/qpx.s b/test/MC/PowerPC/qpx.s
new file mode 100644
index 000000000000..a1fb2090f8ff
--- /dev/null
+++ b/test/MC/PowerPC/qpx.s
@@ -0,0 +1,252 @@
+# RUN: llvm-mc -triple powerpc64-bgq-linux --show-encoding %s | FileCheck %s
+
+# CHECK: qvfabs 3, 5                     # encoding: [0x10,0x60,0x2a,0x10]
+         qvfabs %q3, %q5
+
+# CHECK: qvfabs 3, 5                     # encoding: [0x10,0x60,0x2a,0x10]
+         qvfabs 3, 5
+# CHECK: qvfadd 3, 4, 5                  # encoding: [0x10,0x64,0x28,0x2a]
+         qvfadd 3, 4, 5
+# CHECK: qvfadds 3, 4, 5                 # encoding: [0x00,0x64,0x28,0x2a]
+         qvfadds 3, 4, 5
+# CHECK: qvfandc 3, 4, 5                 # encoding: [0x10,0x64,0x2a,0x08]
+         qvfandc 3, 4, 5
+# CHECK: qvfand 3, 4, 5                  # encoding: [0x10,0x64,0x28,0x88]
+         qvfand 3, 4, 5
+# CHECK: qvfcfid 3, 5                    # encoding: [0x10,0x60,0x2e,0x9c]
+         qvfcfid 3, 5
+# CHECK: qvfcfids 3, 5                   # encoding: [0x00,0x60,0x2e,0x9c]
+         qvfcfids 3, 5
+# CHECK: qvfcfidu 3, 5                   # encoding: [0x10,0x60,0x2f,0x9c]
+         qvfcfidu 3, 5
+# CHECK: qvfcfidus 3, 5                  # encoding: [0x00,0x60,0x2f,0x9c]
+         qvfcfidus 3, 5
+# CHECK: qvfclr 3                        # encoding: [0x10,0x63,0x18,0x08]
+         qvfclr 3
+# CHECK: qvfcpsgn 3, 4, 5                # encoding: [0x10,0x64,0x28,0x10]
+         qvfcpsgn 3, 4, 5
+# CHECK: qvfctfb 3, 4                    # encoding: [0x10,0x64,0x22,0x88]
+         qvfctfb 3, 4
+# CHECK: qvfctid 3, 5                    # encoding: [0x10,0x60,0x2e,0x5c]
+         qvfctid 3, 5
+# CHECK: qvfctidu 3, 5                   # encoding: [0x10,0x60,0x2f,0x5c]
+         qvfctidu 3, 5
+# CHECK: qvfctiduz 3, 5                  # encoding: [0x10,0x60,0x2f,0x5e]
+         qvfctiduz 3, 5
+# CHECK: qvfctidz 3, 5                   # encoding: [0x10,0x60,0x2e,0x5e]
+         qvfctidz 3, 5
+# CHECK: qvfctiw 3, 5                    # encoding: [0x10,0x60,0x28,0x1c]
+         qvfctiw 3, 5
+# CHECK: qvfctiwu 3, 5                   # encoding: [0x10,0x60,0x29,0x1c]
+         qvfctiwu 3, 5
+# CHECK: qvfctiwuz 3, 5                  # encoding: [0x10,0x60,0x29,0x1e]
+         qvfctiwuz 3, 5
+# CHECK: qvfctiwz 3, 5                   # encoding: [0x10,0x60,0x28,0x1e]
+         qvfctiwz 3, 5
+# CHECK: qvfequ 3, 4, 5                  # encoding: [0x10,0x64,0x2c,0x88]
+         qvfequ 3, 4, 5
+# CHECK: qvflogical 3, 4, 5, 12          # encoding: [0x10,0x64,0x2e,0x08]
+         qvflogical 3, 4, 5, 12
+# CHECK: qvfmadd 3, 4, 6, 5              # encoding: [0x10,0x64,0x29,0xba]
+         qvfmadd 3, 4, 6, 5
+# CHECK: qvfmadds 3, 4, 6, 5             # encoding: [0x00,0x64,0x29,0xba]
+         qvfmadds 3, 4, 6, 5
+# CHECK: qvfmr 3, 5                      # encoding: [0x10,0x60,0x28,0x90]
+         qvfmr 3, 5
+# CHECK: qvfmsub 3, 4, 6, 5              # encoding: [0x10,0x64,0x29,0xb8]
+         qvfmsub 3, 4, 6, 5
+# CHECK: qvfmsubs 3, 4, 6, 5             # encoding: [0x00,0x64,0x29,0xb8]
+         qvfmsubs 3, 4, 6, 5
+# CHECK: qvfmul 3, 4, 6                  # encoding: [0x10,0x64,0x01,0xb2]
+         qvfmul 3, 4, 6
+# CHECK: qvfmuls 3, 4, 6                 # encoding: [0x00,0x64,0x01,0xb2]
+         qvfmuls 3, 4, 6
+# CHECK: qvfnabs 3, 5                    # encoding: [0x10,0x60,0x29,0x10]
+         qvfnabs 3, 5
+# CHECK: qvfnand 3, 4, 5                 # encoding: [0x10,0x64,0x2f,0x08]
+         qvfnand 3, 4, 5
+# CHECK: qvfneg 3, 5                     # encoding: [0x10,0x60,0x28,0x50]
+         qvfneg 3, 5
+# CHECK: qvfnmadd 3, 4, 6, 5             # encoding: [0x10,0x64,0x29,0xbe]
+         qvfnmadd 3, 4, 6, 5
+# CHECK: qvfnmadds 3, 4, 6, 5            # encoding: [0x00,0x64,0x29,0xbe]
+         qvfnmadds 3, 4, 6, 5
+# CHECK: qvfnmsub 3, 4, 6, 5             # encoding: [0x10,0x64,0x29,0xbc]
+         qvfnmsub 3, 4, 6, 5
+# CHECK: qvfnmsubs 3, 4, 6, 5            # encoding: [0x00,0x64,0x29,0xbc]
+         qvfnmsubs 3, 4, 6, 5
+# CHECK: qvfnor 3, 4, 5                  # encoding: [0x10,0x64,0x2c,0x08]
+         qvfnor 3, 4, 5
+# CHECK: qvfnot 3, 4                     # encoding: [0x10,0x64,0x25,0x08]
+         qvfnot 3, 4
+# CHECK: qvforc 3, 4, 5                  # encoding: [0x10,0x64,0x2e,0x88]
+         qvforc 3, 4, 5
+# CHECK: qvfor 3, 4, 5                   # encoding: [0x10,0x64,0x2b,0x88]
+         qvfor 3, 4, 5
+# CHECK: qvfperm 3, 4, 5, 6              # encoding: [0x10,0x64,0x29,0x8c]
+         qvfperm 3, 4, 5, 6
+# CHECK: qvfre 3, 5                      # encoding: [0x10,0x60,0x28,0x30]
+         qvfre 3, 5
+# CHECK: qvfres 3, 5                     # encoding: [0x00,0x60,0x28,0x30]
+         qvfres 3, 5
+# CHECK: qvfrim 3, 5                     # encoding: [0x10,0x60,0x2b,0xd0]
+         qvfrim 3, 5
+# CHECK: qvfrin 3, 5                     # encoding: [0x10,0x60,0x2b,0x10]
+         qvfrin 3, 5
+# CHECK: qvfrip 3, 5                     # encoding: [0x10,0x60,0x2b,0x90]
+         qvfrip 3, 5
+# CHECK: qvfriz 3, 5                     # encoding: [0x10,0x60,0x2b,0x50]
+         qvfriz 3, 5
+# CHECK: qvfrsp 3, 5                     # encoding: [0x10,0x60,0x28,0x18]
+         qvfrsp 3, 5
+# CHECK: qvfrsqrte 3, 5                  # encoding: [0x10,0x60,0x28,0x34]
+         qvfrsqrte 3, 5
+# CHECK: qvfrsqrtes 3, 5                 # encoding: [0x00,0x60,0x28,0x34]
+         qvfrsqrtes 3, 5
+# CHECK: qvfsel 3, 4, 6, 5               # encoding: [0x10,0x64,0x29,0xae]
+         qvfsel 3, 4, 6, 5
+# CHECK: qvfset 3                        # encoding: [0x10,0x63,0x1f,0x88]
+         qvfset 3
+# CHECK: qvfsub 3, 4, 5                  # encoding: [0x10,0x64,0x28,0x28]
+         qvfsub 3, 4, 5
+# CHECK: qvfsubs 3, 4, 5                 # encoding: [0x00,0x64,0x28,0x28]
+         qvfsubs 3, 4, 5
+# CHECK: qvfxmadd 3, 4, 6, 5             # encoding: [0x10,0x64,0x29,0x92]
+         qvfxmadd 3, 4, 6, 5
+# CHECK: qvfxmadds 3, 4, 6, 5            # encoding: [0x00,0x64,0x29,0x92]
+         qvfxmadds 3, 4, 6, 5
+# CHECK: qvfxmul 3, 4, 6                 # encoding: [0x10,0x64,0x01,0xa2]
+         qvfxmul 3, 4, 6
+# CHECK: qvfxmuls 3, 4, 6                # encoding: [0x00,0x64,0x01,0xa2]
+         qvfxmuls 3, 4, 6
+# CHECK: qvfxor 3, 4, 5                  # encoding: [0x10,0x64,0x2b,0x08]
+         qvfxor 3, 4, 5
+# CHECK: qvfxxcpnmadd 3, 4, 6, 5         # encoding: [0x10,0x64,0x29,0x86]
+         qvfxxcpnmadd 3, 4, 6, 5
+# CHECK: qvfxxcpnmadds 3, 4, 6, 5        # encoding: [0x00,0x64,0x29,0x86]
+         qvfxxcpnmadds 3, 4, 6, 5
+# CHECK: qvfxxmadd 3, 4, 6, 5            # encoding: [0x10,0x64,0x29,0x82]
+         qvfxxmadd 3, 4, 6, 5
+# CHECK: qvfxxmadds 3, 4, 6, 5           # encoding: [0x00,0x64,0x29,0x82]
+         qvfxxmadds 3, 4, 6, 5
+# CHECK: qvfxxnpmadd 3, 4, 6, 5          # encoding: [0x10,0x64,0x29,0x96]
+         qvfxxnpmadd 3, 4, 6, 5
+# CHECK: qvfxxnpmadds 3, 4, 6, 5         # encoding: [0x00,0x64,0x29,0x96]
+         qvfxxnpmadds 3, 4, 6, 5
+# CHECK: qvlfcduxa 3, 9, 11              # encoding: [0x7c,0x69,0x58,0xcf]
+         qvlfcduxa 3, 9, 11
+# CHECK: qvlfcdux 3, 9, 11               # encoding: [0x7c,0x69,0x58,0xce]
+         qvlfcdux 3, 9, 11
+# CHECK: qvlfcdxa 3, 10, 11              # encoding: [0x7c,0x6a,0x58,0x8f]
+         qvlfcdxa 3, 10, 11
+# CHECK: qvlfcdx 3, 10, 11               # encoding: [0x7c,0x6a,0x58,0x8e]
+         qvlfcdx 3, 10, 11
+# CHECK: qvlfcsuxa 3, 9, 11              # encoding: [0x7c,0x69,0x58,0x4f]
+         qvlfcsuxa 3, 9, 11
+# CHECK: qvlfcsux 3, 9, 11               # encoding: [0x7c,0x69,0x58,0x4e]
+         qvlfcsux 3, 9, 11
+# CHECK: qvlfcsxa 3, 10, 11              # encoding: [0x7c,0x6a,0x58,0x0f]
+         qvlfcsxa 3, 10, 11
+# CHECK: qvlfcsx 3, 10, 11               # encoding: [0x7c,0x6a,0x58,0x0e]
+         qvlfcsx 3, 10, 11
+# CHECK: qvlfduxa 3, 9, 11               # encoding: [0x7c,0x69,0x5c,0xcf]
+         qvlfduxa 3, 9, 11
+# CHECK: qvlfdux 3, 9, 11                # encoding: [0x7c,0x69,0x5c,0xce]
+         qvlfdux 3, 9, 11
+# CHECK: qvlfdxa 3, 10, 11               # encoding: [0x7c,0x6a,0x5c,0x8f]
+         qvlfdxa 3, 10, 11
+# CHECK: qvlfdx 3, 10, 11                # encoding: [0x7c,0x6a,0x5c,0x8e]
+         qvlfdx 3, 10, 11
+# CHECK: qvlfiwaxa 3, 10, 11             # encoding: [0x7c,0x6a,0x5e,0xcf]
+         qvlfiwaxa 3, 10, 11
+# CHECK: qvlfiwax 3, 10, 11              # encoding: [0x7c,0x6a,0x5e,0xce]
+         qvlfiwax 3, 10, 11
+# CHECK: qvlfiwzxa 3, 10, 11             # encoding: [0x7c,0x6a,0x5e,0x8f]
+         qvlfiwzxa 3, 10, 11
+# CHECK: qvlfiwzx 3, 10, 11              # encoding: [0x7c,0x6a,0x5e,0x8e]
+         qvlfiwzx 3, 10, 11
+# CHECK: qvlfsuxa 3, 9, 11               # encoding: [0x7c,0x69,0x5c,0x4f]
+         qvlfsuxa 3, 9, 11
+# CHECK: qvlfsux 3, 9, 11                # encoding: [0x7c,0x69,0x5c,0x4e]
+         qvlfsux 3, 9, 11
+# CHECK: qvlfsxa 3, 10, 11               # encoding: [0x7c,0x6a,0x5c,0x0f]
+         qvlfsxa 3, 10, 11
+# CHECK: qvlfsx 3, 10, 11                # encoding: [0x7c,0x6a,0x5c,0x0e]
+         qvlfsx 3, 10, 11
+# CHECK: qvlpcldx 3, 10, 11              # encoding: [0x7c,0x6a,0x5c,0x8c]
+         qvlpcldx 3, 10, 11
+# CHECK: qvlpclsx 3, 10, 11              # encoding: [0x7c,0x6a,0x5c,0x0c]
+         qvlpclsx 3, 10, 11
+# CHECK: qvlpcrdx 3, 10, 11              # encoding: [0x7c,0x6a,0x58,0x8c]
+         qvlpcrdx 3, 10, 11
+# CHECK: qvlpcrsx 3, 10, 11              # encoding: [0x7c,0x6a,0x58,0x0c]
+         qvlpcrsx 3, 10, 11
+# CHECK: qvstfcduxa 2, 9, 11             # encoding: [0x7c,0x49,0x59,0xcf]
+         qvstfcduxa 2, 9, 11
+# CHECK: qvstfcduxia 2, 9, 11            # encoding: [0x7c,0x49,0x59,0xcb]
+         qvstfcduxia 2, 9, 11
+# CHECK: qvstfcduxi 2, 9, 11             # encoding: [0x7c,0x49,0x59,0xca]
+         qvstfcduxi 2, 9, 11
+# CHECK: qvstfcdux 2, 9, 11              # encoding: [0x7c,0x49,0x59,0xce]
+         qvstfcdux 2, 9, 11
+# CHECK: qvstfcdxa 2, 10, 11             # encoding: [0x7c,0x4a,0x59,0x8f]
+         qvstfcdxa 2, 10, 11
+# CHECK: qvstfcdxia 2, 10, 11            # encoding: [0x7c,0x4a,0x59,0x8b]
+         qvstfcdxia 2, 10, 11
+# CHECK: qvstfcdxi 2, 10, 11             # encoding: [0x7c,0x4a,0x59,0x8a]
+         qvstfcdxi 2, 10, 11
+# CHECK: qvstfcdx 2, 10, 11              # encoding: [0x7c,0x4a,0x59,0x8e]
+         qvstfcdx 2, 10, 11
+# CHECK: qvstfcsuxa 2, 9, 11             # encoding: [0x7c,0x49,0x59,0x4f]
+         qvstfcsuxa 2, 9, 11
+# CHECK: qvstfcsuxia 2, 9, 11            # encoding: [0x7c,0x49,0x59,0x4b]
+         qvstfcsuxia 2, 9, 11
+# CHECK: qvstfcsuxi 2, 9, 11             # encoding: [0x7c,0x49,0x59,0x4a]
+         qvstfcsuxi 2, 9, 11
+# CHECK: qvstfcsux 2, 9, 11              # encoding: [0x7c,0x49,0x59,0x4e]
+         qvstfcsux 2, 9, 11
+# CHECK: qvstfcsxa 2, 10, 11             # encoding: [0x7c,0x4a,0x59,0x0f]
+         qvstfcsxa 2, 10, 11
+# CHECK: qvstfcsxia 2, 10, 11            # encoding: [0x7c,0x4a,0x59,0x0b]
+         qvstfcsxia 2, 10, 11
+# CHECK: qvstfcsxi 2, 10, 11             # encoding: [0x7c,0x4a,0x59,0x0a]
+         qvstfcsxi 2, 10, 11
+# CHECK: qvstfcsx 2, 10, 11              # encoding: [0x7c,0x4a,0x59,0x0e]
+         qvstfcsx 2, 10, 11
+# CHECK: qvstfduxa 2, 9, 11              # encoding: [0x7c,0x49,0x5d,0xcf]
+         qvstfduxa 2, 9, 11
+# CHECK: qvstfduxia 2, 9, 11             # encoding: [0x7c,0x49,0x5d,0xcb]
+         qvstfduxia 2, 9, 11
+# CHECK: qvstfduxi 2, 9, 11              # encoding: [0x7c,0x49,0x5d,0xca]
+         qvstfduxi 2, 9, 11
+# CHECK: qvstfdux 2, 9, 11               # encoding: [0x7c,0x49,0x5d,0xce]
+         qvstfdux 2, 9, 11
+# CHECK: qvstfdxa 2, 10, 11              # encoding: [0x7c,0x4a,0x5d,0x8f]
+         qvstfdxa 2, 10, 11
+# CHECK: qvstfdxia 2, 10, 11             # encoding: [0x7c,0x4a,0x5d,0x8b]
+         qvstfdxia 2, 10, 11
+# CHECK: qvstfdxi 2, 10, 11              # encoding: [0x7c,0x4a,0x5d,0x8a]
+         qvstfdxi 2, 10, 11
+# CHECK: qvstfdx 2, 10, 11               # encoding: [0x7c,0x4a,0x5d,0x8e]
+         qvstfdx 2, 10, 11
+# CHECK: qvstfiwxa 2, 10, 11             # encoding: [0x7c,0x4a,0x5f,0x8f]
+         qvstfiwxa 2, 10, 11
+# CHECK: qvstfiwx 2, 10, 11              # encoding: [0x7c,0x4a,0x5f,0x8e]
+         qvstfiwx 2, 10, 11
+# CHECK: qvstfsuxa 2, 9, 11              # encoding: [0x7c,0x49,0x5d,0x4f]
+         qvstfsuxa 2, 9, 11
+# CHECK: qvstfsuxia 2, 9, 11             # encoding: [0x7c,0x49,0x5d,0x4b]
+         qvstfsuxia 2, 9, 11
+# CHECK: qvstfsuxi 2, 9, 11              # encoding: [0x7c,0x49,0x5d,0x4a]
+         qvstfsuxi 2, 9, 11
+# CHECK: qvstfsux 2, 9, 11               # encoding: [0x7c,0x49,0x5d,0x4e]
+         qvstfsux 2, 9, 11
+# CHECK: qvstfsxa 2, 10, 11              # encoding: [0x7c,0x4a,0x5d,0x0f]
+         qvstfsxa 2, 10, 11
+# CHECK: qvstfsxia 2, 10, 11             # encoding: [0x7c,0x4a,0x5d,0x0b]
+         qvstfsxia 2, 10, 11
+# CHECK: qvstfsxi 2, 10, 11              # encoding: [0x7c,0x4a,0x5d,0x0a]
+         qvstfsxi 2, 10, 11
+# CHECK: qvstfsx 2, 10, 11               # encoding: [0x7c,0x4a,0x5d,0x0e]
+         qvstfsx 2, 10, 11
+
diff --git a/test/MC/PowerPC/tls-gd-obj.s b/test/MC/PowerPC/tls-gd-obj.s
index 63d47ee62935..fb4ab8b351e0 100644
--- a/test/MC/PowerPC/tls-gd-obj.s
+++ b/test/MC/PowerPC/tls-gd-obj.s
@@ -47,7 +47,7 @@ a:
 // for the call to __tls_get_addr.
 //
 // CHECK: Relocations [
-// CHECK:   Section (2) .rela.text {
+// CHECK:   Section {{.*}} .rela.text {
 // CHECK:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_HA a
 // CHECK:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_LO a
 // CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TLSGD          a
diff --git a/test/MC/PowerPC/tls-ie-obj.s b/test/MC/PowerPC/tls-ie-obj.s
index c8c5d91573ac..f7de644630cf 100644
--- a/test/MC/PowerPC/tls-ie-obj.s
+++ b/test/MC/PowerPC/tls-ie-obj.s
@@ -36,7 +36,7 @@ main:                                   # @main
 // accessing external variable a.
 //
 // CHECK: Relocations [
-// CHECK:   Section (2) .rela.text {
+// CHECK:   Section {{.*}} .rela.text {
 // CHECK:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA    a
 // CHECK:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS a
 // CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TLS               a
diff --git a/test/MC/PowerPC/tls-ld-obj.s b/test/MC/PowerPC/tls-ld-obj.s
index b0c4a7a528fb..1fa371dfac22 100644
--- a/test/MC/PowerPC/tls-ld-obj.s
+++ b/test/MC/PowerPC/tls-ld-obj.s
@@ -50,7 +50,7 @@ a:
 // __tls_get_addr.
 //
 // CHECK: Relocations [
-// CHECK:   Section (2) .rela.text {
+// CHECK:   Section {{.*}} .rela.text {
 // CHECK:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_HA a
 // CHECK:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_LO a
 // CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TLSLD          a
diff --git a/test/MC/PowerPC/vsx.s b/test/MC/PowerPC/vsx.s
index b355ba37b801..773fc9eef6d1 100644
--- a/test/MC/PowerPC/vsx.s
+++ b/test/MC/PowerPC/vsx.s
@@ -1,30 +1,52 @@
 # RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
 # RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
 
-# CHECK-BE: lxsdx 39, 5, 31                     # encoding: [0x7c,0xe5,0xfc,0x99]
-# CHECK-LE: lxsdx 39, 5, 31                     # encoding: [0x99,0xfc,0xe5,0x7c]
+# CHECK-BE: xxswapd 7, 63                      # encoding: [0xf0,0xff,0xfa,0x56]
+# CHECK-LE: xxswapd 7, 63                      # encoding: [0x56,0xfa,0xff,0xf0]
+            xxswapd %vs7, %vs63
+
+# CHECK-BE: lxsdx 39, 5, 31                    # encoding: [0x7c,0xe5,0xfc,0x99]
+# CHECK-LE: lxsdx 39, 5, 31                    # encoding: [0x99,0xfc,0xe5,0x7c]
             lxsdx 39, 5, 31
-# CHECK-BE: lxvd2x 39, 5, 31                    # encoding: [0x7c,0xe5,0xfe,0x99]
-# CHECK-LE: lxvd2x 39, 5, 31                    # encoding: [0x99,0xfe,0xe5,0x7c]
+# CHECK-BE: lxsiwax 39, 5, 31                  # encoding: [0x7c,0xe5,0xf8,0x99]
+# CHECK-LE: lxsiwax 39, 5, 31                  # encoding: [0x99,0xf8,0xe5,0x7c]
+            lxsiwax 39, 5, 31
+# CHECK-BE: lxsiwzx 39, 5, 31                  # encoding: [0x7c,0xe5,0xf8,0x19]
+# CHECK-LE: lxsiwzx 39, 5, 31                  # encoding: [0x19,0xf8,0xe5,0x7c]
+            lxsiwzx 39, 5, 31
+# CHECK-BE: lxsspx 39, 5, 31                   # encoding: [0x7c,0xe5,0xfc,0x19]
+# CHECK-LE: lxsspx 39, 5, 31                   # encoding: [0x19,0xfc,0xe5,0x7c]
+            lxsspx 39, 5, 31
+# CHECK-BE: lxvd2x 39, 5, 31                   # encoding: [0x7c,0xe5,0xfe,0x99]
+# CHECK-LE: lxvd2x 39, 5, 31                   # encoding: [0x99,0xfe,0xe5,0x7c]
             lxvd2x 39, 5, 31
-# CHECK-BE: lxvdsx 39, 5, 31                    # encoding: [0x7c,0xe5,0xfa,0x99]
-# CHECK-LE: lxvdsx 39, 5, 31                    # encoding: [0x99,0xfa,0xe5,0x7c]
+# CHECK-BE: lxvdsx 39, 5, 31                   # encoding: [0x7c,0xe5,0xfa,0x99]
+# CHECK-LE: lxvdsx 39, 5, 31                   # encoding: [0x99,0xfa,0xe5,0x7c]
             lxvdsx 39, 5, 31
-# CHECK-BE: lxvw4x 39, 5, 31                    # encoding: [0x7c,0xe5,0xfe,0x19]
-# CHECK-LE: lxvw4x 39, 5, 31                    # encoding: [0x19,0xfe,0xe5,0x7c]
+# CHECK-BE: lxvw4x 39, 5, 31                   # encoding: [0x7c,0xe5,0xfe,0x19]
+# CHECK-LE: lxvw4x 39, 5, 31                   # encoding: [0x19,0xfe,0xe5,0x7c]
             lxvw4x 39, 5, 31
-# CHECK-BE: stxsdx 40, 5, 31                    # encoding: [0x7d,0x05,0xfd,0x99]
-# CHECK-LE: stxsdx 40, 5, 31                    # encoding: [0x99,0xfd,0x05,0x7d]
+# CHECK-BE: stxsdx 40, 5, 31                   # encoding: [0x7d,0x05,0xfd,0x99]
+# CHECK-LE: stxsdx 40, 5, 31                   # encoding: [0x99,0xfd,0x05,0x7d]
             stxsdx 40, 5, 31
-# CHECK-BE: stxvd2x 40, 5, 31                   # encoding: [0x7d,0x05,0xff,0x99]
-# CHECK-LE: stxvd2x 40, 5, 31                   # encoding: [0x99,0xff,0x05,0x7d]
+# CHECK-BE: stxsiwx 40, 5, 31                  # encoding: [0x7d,0x05,0xf9,0x19]
+# CHECK-LE: stxsiwx 40, 5, 31                  # encoding: [0x19,0xf9,0x05,0x7d]
+            stxsiwx 40, 5, 31
+# CHECK-BE: stxsspx 40, 5, 31                  # encoding: [0x7d,0x05,0xfd,0x19]
+# CHECK-LE: stxsspx 40, 5, 31                  # encoding: [0x19,0xfd,0x05,0x7d]
+            stxsspx 40, 5, 31
+# CHECK-BE: stxvd2x 40, 5, 31                  # encoding: [0x7d,0x05,0xff,0x99]
+# CHECK-LE: stxvd2x 40, 5, 31                  # encoding: [0x99,0xff,0x05,0x7d]
             stxvd2x 40, 5, 31
-# CHECK-BE: stxvw4x 40, 5, 31                   # encoding: [0x7d,0x05,0xff,0x19]
-# CHECK-LE: stxvw4x 40, 5, 31                   # encoding: [0x19,0xff,0x05,0x7d]
+# CHECK-BE: stxvw4x 40, 5, 31                  # encoding: [0x7d,0x05,0xff,0x19]
+# CHECK-LE: stxvw4x 40, 5, 31                  # encoding: [0x19,0xff,0x05,0x7d]
             stxvw4x 40, 5, 31
 # CHECK-BE: xsabsdp 7, 27                      # encoding: [0xf0,0xe0,0xdd,0x64]
 # CHECK-LE: xsabsdp 7, 27                      # encoding: [0x64,0xdd,0xe0,0xf0]
             xsabsdp 7, 27
+# CHECK-BE: xsaddsp 7, 63, 27                  # encoding: [0xf0,0xff,0xd8,0x04]
+# CHECK-LE: xsaddsp 7, 63, 27                  # encoding: [0x04,0xd8,0xff,0xf0]
+            xsaddsp 7, 63, 27
 # CHECK-BE: xsadddp 7, 63, 27                  # encoding: [0xf0,0xff,0xd9,0x04]
 # CHECK-LE: xsadddp 7, 63, 27                  # encoding: [0x04,0xd9,0xff,0xf0]
             xsadddp 7, 63, 27
@@ -61,6 +83,9 @@
 # CHECK-BE: xscvuxddp 7, 27                    # encoding: [0xf0,0xe0,0xdd,0xa0]
 # CHECK-LE: xscvuxddp 7, 27                    # encoding: [0xa0,0xdd,0xe0,0xf0]
             xscvuxddp 7, 27
+# CHECK-BE: xsdivsp 7, 63, 27                  # encoding: [0xf0,0xff,0xd8,0xc4]
+# CHECK-LE: xsdivsp 7, 63, 27                  # encoding: [0xc4,0xd8,0xff,0xf0]
+            xsdivsp 7, 63, 27
 # CHECK-BE: xsdivdp 7, 63, 27                  # encoding: [0xf0,0xff,0xd9,0xc4]
 # CHECK-LE: xsdivdp 7, 63, 27                  # encoding: [0xc4,0xd9,0xff,0xf0]
             xsdivdp 7, 63, 27
@@ -82,6 +107,9 @@
 # CHECK-BE: xsmsubmdp 7, 63, 27                # encoding: [0xf0,0xff,0xd9,0xcc]
 # CHECK-LE: xsmsubmdp 7, 63, 27                # encoding: [0xcc,0xd9,0xff,0xf0]
             xsmsubmdp 7, 63, 27
+# CHECK-BE: xsmulsp 7, 63, 27                  # encoding: [0xf0,0xff,0xd8,0x84]
+# CHECK-LE: xsmulsp 7, 63, 27                  # encoding: [0x84,0xd8,0xff,0xf0]
+            xsmulsp 7, 63, 27
 # CHECK-BE: xsmuldp 7, 63, 27                  # encoding: [0xf0,0xff,0xd9,0x84]
 # CHECK-LE: xsmuldp 7, 63, 27                  # encoding: [0x84,0xd9,0xff,0xf0]
             xsmuldp 7, 63, 27
@@ -118,15 +146,27 @@
 # CHECK-BE: xsrdpiz 7, 27                      # encoding: [0xf0,0xe0,0xd9,0x64]
 # CHECK-LE: xsrdpiz 7, 27                      # encoding: [0x64,0xd9,0xe0,0xf0]
             xsrdpiz 7, 27
+# CHECK-BE: xsresp 7, 27                       # encoding: [0xf0,0xe0,0xd8,0x68]
+# CHECK-LE: xsresp 7, 27                       # encoding: [0x68,0xd8,0xe0,0xf0]
+            xsresp 7, 27
 # CHECK-BE: xsredp 7, 27                       # encoding: [0xf0,0xe0,0xd9,0x68]
 # CHECK-LE: xsredp 7, 27                       # encoding: [0x68,0xd9,0xe0,0xf0]
             xsredp 7, 27
+# CHECK-BE: xsrsqrtesp 7, 27                   # encoding: [0xf0,0xe0,0xd8,0x28]
+# CHECK-LE: xsrsqrtesp 7, 27                   # encoding: [0x28,0xd8,0xe0,0xf0]
+            xsrsqrtesp 7, 27
 # CHECK-BE: xsrsqrtedp 7, 27                   # encoding: [0xf0,0xe0,0xd9,0x28]
 # CHECK-LE: xsrsqrtedp 7, 27                   # encoding: [0x28,0xd9,0xe0,0xf0]
             xsrsqrtedp 7, 27
+# CHECK-BE: xssqrtsp 7, 27                     # encoding: [0xf0,0xe0,0xd8,0x2c]
+# CHECK-LE: xssqrtsp 7, 27                     # encoding: [0x2c,0xd8,0xe0,0xf0]
+            xssqrtsp 7, 27
 # CHECK-BE: xssqrtdp 7, 27                     # encoding: [0xf0,0xe0,0xd9,0x2c]
 # CHECK-LE: xssqrtdp 7, 27                     # encoding: [0x2c,0xd9,0xe0,0xf0]
             xssqrtdp 7, 27
+# CHECK-BE: xssubsp 7, 63, 27                  # encoding: [0xf0,0xff,0xd8,0x44]
+# CHECK-LE: xssubsp 7, 63, 27                  # encoding: [0x44,0xd8,0xff,0xf0]
+            xssubsp 7, 63, 27
 # CHECK-BE: xssubdp 7, 63, 27                  # encoding: [0xf0,0xff,0xd9,0x44]
 # CHECK-LE: xssubdp 7, 63, 27                  # encoding: [0x44,0xd9,0xff,0xf0]
             xssubdp 7, 63, 27
@@ -274,11 +314,11 @@
 # CHECK-BE: xvminsp 7, 63, 27                  # encoding: [0xf0,0xff,0xde,0x44]
 # CHECK-LE: xvminsp 7, 63, 27                  # encoding: [0x44,0xde,0xff,0xf0]
             xvminsp 7, 63, 27
-# CHECK-BE: xvcpsgndp 7, 63, 63                # encoding: [0xf0,0xff,0xff,0x86]
-# CHECK-LE: xvcpsgndp 7, 63, 63                # encoding: [0x86,0xff,0xff,0xf0]
+# CHECK-BE: xvmovdp 7, 63                      # encoding: [0xf0,0xff,0xff,0x86]
+# CHECK-LE: xvmovdp 7, 63                      # encoding: [0x86,0xff,0xff,0xf0]
             xvmovdp 7, 63
-# CHECK-BE: xvcpsgnsp 7, 63, 63                # encoding: [0xf0,0xff,0xfe,0x86]
-# CHECK-LE: xvcpsgnsp 7, 63, 63                # encoding: [0x86,0xfe,0xff,0xf0]
+# CHECK-BE: xvmovsp 7, 63                      # encoding: [0xf0,0xff,0xfe,0x86]
+# CHECK-LE: xvmovsp 7, 63                      # encoding: [0x86,0xfe,0xff,0xf0]
             xvmovsp 7, 63
 # CHECK-BE: xvmsubadp 7, 63, 27                # encoding: [0xf0,0xff,0xdb,0x8c]
 # CHECK-LE: xvmsubadp 7, 63, 27                # encoding: [0x8c,0xdb,0xff,0xf0]
@@ -403,6 +443,15 @@
 # CHECK-BE: xxland 7, 63, 27                   # encoding: [0xf0,0xff,0xdc,0x14]
 # CHECK-LE: xxland 7, 63, 27                   # encoding: [0x14,0xdc,0xff,0xf0]
             xxland 7, 63, 27
+# CHECK-BE: xxleqv 7, 63, 27                   # encoding: [0xf0,0xff,0xdd,0xd4]
+# CHECK-LE: xxleqv 7, 63, 27                   # encoding: [0xd4,0xdd,0xff,0xf0]
+            xxleqv 7, 63, 27
+# CHECK-BE: xxlnand 7, 63, 27                  # encoding: [0xf0,0xff,0xdd,0x94]
+# CHECK-LE: xxlnand 7, 63, 27                  # encoding: [0x94,0xdd,0xff,0xf0]
+            xxlnand 7, 63, 27
+# CHECK-BE: xxlorc 7, 63, 27                   # encoding: [0xf0,0xff,0xdd,0x54]
+# CHECK-LE: xxlorc 7, 63, 27                   # encoding: [0x54,0xdd,0xff,0xf0]
+            xxlorc 7, 63, 27
 # CHECK-BE: xxlandc 7, 63, 27                  # encoding: [0xf0,0xff,0xdc,0x54]
 # CHECK-LE: xxlandc 7, 63, 27                  # encoding: [0x54,0xdc,0xff,0xf0]
             xxlandc 7, 63, 27
@@ -415,14 +464,14 @@
 # CHECK-BE: xxlxor 7, 63, 27                   # encoding: [0xf0,0xff,0xdc,0xd4]
 # CHECK-LE: xxlxor 7, 63, 27                   # encoding: [0xd4,0xdc,0xff,0xf0]
             xxlxor 7, 63, 27
-# CHECK-BE: xxpermdi 7, 63, 27, 0              # encoding: [0xf0,0xff,0xd8,0x54]
-# CHECK-LE: xxpermdi 7, 63, 27, 0              # encoding: [0x54,0xd8,0xff,0xf0]
+# CHECK-BE: xxmrghd 7, 63, 27                  # encoding: [0xf0,0xff,0xd8,0x54]
+# CHECK-LE: xxmrghd 7, 63, 27                  # encoding: [0x54,0xd8,0xff,0xf0]
             xxmrghd 7, 63, 27
 # CHECK-BE: xxmrghw 7, 63, 27                  # encoding: [0xf0,0xff,0xd8,0x94]
 # CHECK-LE: xxmrghw 7, 63, 27                  # encoding: [0x94,0xd8,0xff,0xf0]
             xxmrghw 7, 63, 27
-# CHECK-BE: xxpermdi 7, 63, 27, 3              # encoding: [0xf0,0xff,0xdb,0x54]
-# CHECK-LE: xxpermdi 7, 63, 27, 3              # encoding: [0x54,0xdb,0xff,0xf0]
+# CHECK-BE: xxmrgld 7, 63, 27                  # encoding: [0xf0,0xff,0xdb,0x54]
+# CHECK-LE: xxmrgld 7, 63, 27                  # encoding: [0x54,0xdb,0xff,0xf0]
             xxmrgld 7, 63, 27
 # CHECK-BE: xxmrglw 7, 63, 27                  # encoding: [0xf0,0xff,0xd9,0x94]
 # CHECK-LE: xxmrglw 7, 63, 27                  # encoding: [0x94,0xd9,0xff,0xf0]
@@ -436,12 +485,29 @@
 # CHECK-BE: xxsldwi 7, 63, 27, 1               # encoding: [0xf0,0xff,0xd9,0x14]
 # CHECK-LE: xxsldwi 7, 63, 27, 1               # encoding: [0x14,0xd9,0xff,0xf0]
             xxsldwi 7, 63, 27, 1
-# CHECK-BE: xxpermdi 7, 63, 63, 3              # encoding: [0xf0,0xff,0xfb,0x56]
-# CHECK-LE: xxpermdi 7, 63, 63, 3              # encoding: [0x56,0xfb,0xff,0xf0]
+# CHECK-BE: xxspltd 7, 63, 1                   # encoding: [0xf0,0xff,0xfb,0x56]
+# CHECK-LE: xxspltd 7, 63, 1                   # encoding: [0x56,0xfb,0xff,0xf0]
             xxspltd 7, 63, 1
 # CHECK-BE: xxspltw 7, 27, 3                   # encoding: [0xf0,0xe3,0xda,0x90]
 # CHECK-LE: xxspltw 7, 27, 3                   # encoding: [0x90,0xda,0xe3,0xf0]
             xxspltw 7, 27, 3
-# CHECK-BE: xxpermdi 7, 63, 63, 2              # encoding: [0xf0,0xff,0xfa,0x56]
-# CHECK-LE: xxpermdi 7, 63, 63, 2              # encoding: [0x56,0xfa,0xff,0xf0]
+# CHECK-BE: xxswapd 7, 63                      # encoding: [0xf0,0xff,0xfa,0x56]
+# CHECK-LE: xxswapd 7, 63                      # encoding: [0x56,0xfa,0xff,0xf0]
             xxswapd 7, 63
+
+# Move to/from VSR
+# CHECK-BE: mfvsrd 3, 0                        # encoding: [0x7c,0x03,0x00,0x66]
+# CHECK-LE: mfvsrd 3, 0                        # encoding: [0x66,0x00,0x03,0x7c]
+            mfvsrd 3, 0
+# CHECK-BE: mfvsrwz 5, 0                       # encoding: [0x7c,0x05,0x00,0xe6]
+# CHECK-LE: mfvsrwz 5, 0                       # encoding: [0xe6,0x00,0x05,0x7c]
+            mfvsrwz 5, 0
+# CHECK-BE: mtvsrd 0, 3                        # encoding: [0x7c,0x03,0x01,0x66]
+# CHECK-LE: mtvsrd 0, 3                        # encoding: [0x66,0x01,0x03,0x7c]
+            mtvsrd 0, 3
+# CHECK-BE: mtvsrwa 0, 3                       # encoding: [0x7c,0x03,0x01,0xa6]
+# CHECK-LE: mtvsrwa 0, 3                       # encoding: [0xa6,0x01,0x03,0x7c]
+            mtvsrwa 0, 3
+# CHECK-BE: mtvsrwz 0, 3                       # encoding: [0x7c,0x03,0x01,0xe6]
+# CHECK-LE: mtvsrwz 0, 3                       # encoding: [0xe6,0x01,0x03,0x7c]
+            mtvsrwz 0, 3
diff --git a/test/MC/R600/ds-err.s b/test/MC/R600/ds-err.s
new file mode 100644
index 000000000000..52c2740bec25
--- /dev/null
+++ b/test/MC/R600/ds-err.s
@@ -0,0 +1,23 @@
+// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s
+
+// offset too big
+// CHECK: invalid operand for instruction
+ds_add_u32 v2, v4 offset:1000000000
+
+// offset0 twice
+// CHECK:  error: not a valid operand.
+ds_write2_b32 v2, v4, v6 offset0:4 offset0:8
+
+// offset1 twice
+// CHECK:  error: not a valid operand.
+ds_write2_b32 v2, v4, v6 offset1:4 offset1:8
+
+// offset0 too big
+// CHECK: invalid operand for instruction
+ds_write2_b32 v2, v4, v6 offset0:1000000000
+
+// offset1 too big
+// CHECK: invalid operand for instruction
+ds_write2_b32 v2, v4, v6 offset1:1000000000
+
diff --git a/test/MC/R600/ds.s b/test/MC/R600/ds.s
new file mode 100644
index 000000000000..ad63229ba2e1
--- /dev/null
+++ b/test/MC/R600/ds.s
@@ -0,0 +1,337 @@
+// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=SI  -show-encoding %s | FileCheck %s
+
+//===----------------------------------------------------------------------===//
+// Checks for 16-bit Offsets
+//===----------------------------------------------------------------------===//
+
+ds_add_u32 v2, v4 offset:16
+// CHECK: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
+
+//===----------------------------------------------------------------------===//
+// Checks for 2 8-bit Offsets
+//===----------------------------------------------------------------------===//
+
+ds_write2_b32 v2, v4, v6 offset0:4
+// CHECK: ds_write2_b32 v2, v4, v6 offset0:4 ; encoding: [0x04,0x00,0x38,0xd8,0x02,0x04,0x06,0x00]
+
+ds_write2_b32 v2, v4, v6 offset0:4 offset1:8
+// CHECK: ds_write2_b32 v2, v4, v6 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x38,0xd8,0x02,0x04,0x06,0x00]
+
+ds_write2_b32 v2, v4, v6 offset1:8
+// CHECK: ds_write2_b32 v2, v4, v6 offset1:8 ; encoding: [0x00,0x08,0x38,0xd8,0x02,0x04,0x06,0x00]
+
+ds_read2_b32 v[8:9], v2 offset0:4
+// CHECK: ds_read2_b32 v[8:9], v2 offset0:4 ; encoding: [0x04,0x00,0xdc,0xd8,0x02,0x00,0x00,0x08]
+
+ds_read2_b32 v[8:9], v2 offset0:4 offset1:8
+// CHECK: ds_read2_b32 v[8:9], v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0xdc,0xd8,0x02,0x00,0x00,0x08]
+
+ds_read2_b32 v[8:9], v2 offset1:8
+// CHECK: ds_read2_b32 v[8:9], v2 offset1:8 ; encoding: [0x00,0x08,0xdc,0xd8,0x02,0x00,0x00,0x08]
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+ds_add_u32 v2, v4
+// CHECK: ds_add_u32 v2, v4 ; encoding: [0x00,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
+
+ds_sub_u32 v2, v4
+// CHECK: ds_sub_u32 v2, v4 ; encoding: [0x00,0x00,0x04,0xd8,0x02,0x04,0x00,0x00]
+
+ds_rsub_u32 v2, v4
+// CHECK: ds_rsub_u32 v2, v4 ; encoding: [0x00,0x00,0x08,0xd8,0x02,0x04,0x00,0x00]
+
+ds_inc_u32 v2, v4
+// CHECK: ds_inc_u32 v2, v4 ; encoding: [0x00,0x00,0x0c,0xd8,0x02,0x04,0x00,0x00]
+
+ds_dec_u32 v2, v4
+// CHECK: ds_dec_u32 v2, v4 ; encoding: [0x00,0x00,0x10,0xd8,0x02,0x04,0x00,0x00]
+
+ds_min_i32 v2, v4
+// CHECK: ds_min_i32 v2, v4 ; encoding: [0x00,0x00,0x14,0xd8,0x02,0x04,0x00,0x00]
+
+ds_max_i32 v2, v4
+// CHECK: ds_max_i32 v2, v4 ; encoding: [0x00,0x00,0x18,0xd8,0x02,0x04,0x00,0x00]
+
+ds_min_u32 v2, v4
+// CHECK: ds_min_u32 v2, v4 ; encoding: [0x00,0x00,0x1c,0xd8,0x02,0x04,0x00,0x00]
+
+ds_max_u32 v2, v4
+// CHECK: ds_max_u32 v2, v4 ; encoding: [0x00,0x00,0x20,0xd8,0x02,0x04,0x00,0x00]
+
+ds_and_b32 v2, v4
+// CHECK: ds_and_b32 v2, v4 ; encoding: [0x00,0x00,0x24,0xd8,0x02,0x04,0x00,0x00]
+
+ds_or_b32 v2, v4
+// CHECK: ds_or_b32 v2, v4 ; encoding: [0x00,0x00,0x28,0xd8,0x02,0x04,0x00,0x00]
+
+ds_xor_b32 v2, v4
+// CHECK: ds_xor_b32 v2, v4 ; encoding: [0x00,0x00,0x2c,0xd8,0x02,0x04,0x00,0x00]
+
+ds_mskor_b32 v2, v4, v6
+// CHECK: ds_mskor_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x30,0xd8,0x02,0x04,0x06,0x00]
+
+ds_write_b32 v2, v4
+// CHECK: ds_write_b32 v2, v4 ; encoding: [0x00,0x00,0x34,0xd8,0x02,0x04,0x00,0x00]
+
+ds_write2_b32 v2, v4, v6
+// CHECK: ds_write2_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x38,0xd8,0x02,0x04,0x06,0x00]
+
+ds_write2st64_b32 v2, v4, v6
+// CHECK: ds_write2st64_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x3c,0xd8,0x02,0x04,0x06,0x00]
+
+ds_cmpst_b32 v2, v4, v6
+// CHECK: ds_cmpst_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x40,0xd8,0x02,0x04,0x06,0x00]
+
+ds_cmpst_f32 v2, v4, v6
+// CHECK: ds_cmpst_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x44,0xd8,0x02,0x04,0x06,0x00]
+
+ds_min_f32 v2, v4, v6
+// CHECK: ds_min_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x48,0xd8,0x02,0x04,0x06,0x00]
+
+ds_max_f32 v2, v4, v6
+// CHECK: ds_max_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x4c,0xd8,0x02,0x04,0x06,0x00]
+
+ds_gws_init v2 gds
+// CHECK: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x00,0x00,0x00]
+
+ds_gws_sema_v v2 gds
+// CHECK: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x00,0x00,0x00]
+
+ds_gws_sema_br v2 gds
+// CHECK: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x6e,0xd8,0x02,0x00,0x00,0x00]
+
+ds_gws_sema_p v2 gds
+// CHECK: ds_gws_sema_p v2 gds ; encoding: [0x00,0x00,0x72,0xd8,0x02,0x00,0x00,0x00]
+
+ds_gws_barrier v2 gds
+// CHECK: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x76,0xd8,0x02,0x00,0x00,0x00]
+
+ds_write_b8 v2, v4
+// CHECK: ds_write_b8 v2, v4 ; encoding: [0x00,0x00,0x78,0xd8,0x02,0x04,0x00,0x00]
+
+ds_write_b16 v2, v4
+// CHECK: ds_write_b16 v2, v4 ; encoding: [0x00,0x00,0x7c,0xd8,0x02,0x04,0x00,0x00]
+
+ds_add_rtn_u32 v8, v2, v4
+// CHECK: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x80,0xd8,0x02,0x04,0x00,0x08]
+
+ds_sub_rtn_u32 v8, v2, v4
+// CHECK: ds_sub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x84,0xd8,0x02,0x04,0x00,0x08]
+
+ds_rsub_rtn_u32 v8, v2, v4
+// CHECK: ds_rsub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x88,0xd8,0x02,0x04,0x00,0x08]
+
+ds_inc_rtn_u32 v8, v2, v4
+// CHECK: ds_inc_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x8c,0xd8,0x02,0x04,0x00,0x08]
+
+ds_dec_rtn_u32 v8, v2, v4
+// CHECK: ds_dec_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x90,0xd8,0x02,0x04,0x00,0x08]
+
+ds_min_rtn_i32 v8, v2, v4
+// CHECK: ds_min_rtn_i32 v8, v2, v4 ; encoding: [0x00,0x00,0x94,0xd8,0x02,0x04,0x00,0x08]
+
+ds_max_rtn_i32 v8, v2, v4
+// CHECK: ds_max_rtn_i32 v8, v2, v4 ; encoding: [0x00,0x00,0x98,0xd8,0x02,0x04,0x00,0x08]
+
+ds_min_rtn_u32 v8, v2, v4
+// CHECK: ds_min_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x9c,0xd8,0x02,0x04,0x00,0x08]
+
+ds_max_rtn_u32 v8, v2, v4
+// CHECK: ds_max_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0xa0,0xd8,0x02,0x04,0x00,0x08]
+
+ds_and_rtn_b32 v8, v2, v4
+// CHECK: ds_and_rtn_b32 v8, v2, v4 ; encoding: [0x00,0x00,0xa4,0xd8,0x02,0x04,0x00,0x08]
+
+ds_or_rtn_b32 v8, v2, v4
+// CHECK: ds_or_rtn_b32 v8, v2, v4 ; encoding: [0x00,0x00,0xa8,0xd8,0x02,0x04,0x00,0x08]
+
+ds_xor_rtn_b32 v8, v2, v4
+// CHECK: ds_xor_rtn_b32 v8, v2, v4 ; encoding: [0x00,0x00,0xac,0xd8,0x02,0x04,0x00,0x08]
+
+ds_mskor_rtn_b32 v8, v2, v4, v6
+// CHECK: ds_mskor_rtn_b32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xb0,0xd8,0x02,0x04,0x06,0x08]
+
+ds_wrxchg_rtn_b32 v8, v2, v4
+// CHECK: ds_wrxchg_rtn_b32 v8, v2, v4 ; encoding: [0x00,0x00,0xb4,0xd8,0x02,0x04,0x00,0x08]
+
+ds_wrxchg2_rtn_b32 v[8:9], v2, v4, v6
+// CHECK: ds_wrxchg2_rtn_b32 v[8:9], v2, v4, v6 ; encoding: [0x00,0x00,0xb8,0xd8,0x02,0x04,0x06,0x08]
+
+ds_wrxchg2st64_rtn_b32 v[8:9] v2, v4, v6
+// CHECK: ds_wrxchg2st64_rtn_b32 v[8:9], v2, v4, v6 ; encoding: [0x00,0x00,0xbc,0xd8,0x02,0x04,0x06,0x08]
+
+ds_cmpst_rtn_b32 v8, v2, v4, v6
+// CHECK: ds_cmpst_rtn_b32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc0,0xd8,0x02,0x04,0x06,0x08]
+
+ds_cmpst_rtn_f32 v8, v2, v4, v6
+// CHECK: ds_cmpst_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc4,0xd8,0x02,0x04,0x06,0x08]
+
+ds_min_rtn_f32 v8, v2, v4, v6
+// CHECK: ds_min_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc8,0xd8,0x02,0x04,0x06,0x08]
+
+ds_max_rtn_f32 v8, v2, v4, v6
+// CHECK: ds_max_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xcc,0xd8,0x02,0x04,0x06,0x08]
+
+ds_swizzle_b32 v8, v2
+// CHECK: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
+
+ds_read_b32 v8, v2
+// CHECK: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0xd8,0xd8,0x02,0x00,0x00,0x08]
+
+ds_read2_b32 v[8:9], v2
+// CHECK: ds_read2_b32 v[8:9], v2 ; encoding: [0x00,0x00,0xdc,0xd8,0x02,0x00,0x00,0x08]
+
+ds_read2st64_b32 v[8:9], v2
+// CHECK: ds_read2st64_b32 v[8:9], v2 ; encoding: [0x00,0x00,0xe0,0xd8,0x02,0x00,0x00,0x08]
+
+ds_read_i8 v8, v2
+// CHECK: ds_read_i8 v8, v2 ; encoding: [0x00,0x00,0xe4,0xd8,0x02,0x00,0x00,0x08]
+
+ds_read_u8 v8, v2
+// CHECK: ds_read_u8 v8, v2 ; encoding: [0x00,0x00,0xe8,0xd8,0x02,0x00,0x00,0x08]
+
+ds_read_i16 v8, v2
+// CHECK: ds_read_i16 v8, v2 ; encoding: [0x00,0x00,0xec,0xd8,0x02,0x00,0x00,0x08]
+
+ds_read_u16 v8, v2
+// CHECK: ds_read_u16 v8, v2 ; encoding: [0x00,0x00,0xf0,0xd8,0x02,0x00,0x00,0x08]
+
+ds_consume v8
+// CHECK: ds_consume v8 ; encoding: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x08]
+
+ds_append v8
+// CHECK: ds_append v8 ; encoding: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x08]
+
+ds_ordered_count v8, v2 gds
+// CHECK: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0xfe,0xd8,0x02,0x00,0x00,0x08]
+
+ds_add_u64 v2, v[4:5]
+// CHECK: ds_add_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x00,0xd9,0x02,0x04,0x00,0x00]
+
+ds_sub_u64 v2, v[4:5]
+// CHECK: ds_sub_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x04,0xd9,0x02,0x04,0x00,0x00]
+
+ds_rsub_u64 v2, v[4:5]
+// CHECK: ds_rsub_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x08,0xd9,0x02,0x04,0x00,0x00]
+
+ds_inc_u64 v2, v[4:5]
+// CHECK: ds_inc_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x0c,0xd9,0x02,0x04,0x00,0x00]
+
+ds_dec_u64 v2, v[4:5]
+// CHECK: ds_dec_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x10,0xd9,0x02,0x04,0x00,0x00]
+
+ds_min_i64 v2, v[4:5]
+// CHECK: ds_min_i64 v2, v[4:5] ; encoding: [0x00,0x00,0x14,0xd9,0x02,0x04,0x00,0x00]
+
+ds_max_i64 v2, v[4:5]
+// CHECK: ds_max_i64 v2, v[4:5] ; encoding: [0x00,0x00,0x18,0xd9,0x02,0x04,0x00,0x00]
+
+ds_min_u64 v2, v[4:5]
+// CHECK: ds_min_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x1c,0xd9,0x02,0x04,0x00,0x00]
+
+ds_max_u64 v2, v[4:5]
+// CHECK: ds_max_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x20,0xd9,0x02,0x04,0x00,0x00]
+
+ds_and_b64 v2, v[4:5]
+// CHECK: ds_and_b64 v2, v[4:5] ; encoding: [0x00,0x00,0x24,0xd9,0x02,0x04,0x00,0x00]
+
+ds_or_b64 v2, v[4:5]
+// CHECK: ds_or_b64 v2, v[4:5] ; encoding: [0x00,0x00,0x28,0xd9,0x02,0x04,0x00,0x00]
+
+ds_xor_b64 v2, v[4:5]
+// CHECK: ds_xor_b64 v2, v[4:5] ; encoding: [0x00,0x00,0x2c,0xd9,0x02,0x04,0x00,0x00]
+
+ds_mskor_b64 v2, v[4:5], v[6:7]
+// CHECK: ds_mskor_b64 v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0x30,0xd9,0x02,0x04,0x06,0x00]
+
+ds_write_b64 v2, v[4:5]
+// CHECK: ds_write_b64 v2, v[4:5] ; encoding: [0x00,0x00,0x34,0xd9,0x02,0x04,0x00,0x00]
+
+ds_write2_b64 v2, v[4:5], v[6:7]
+// CHECK: ds_write2_b64 v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0x38,0xd9,0x02,0x04,0x06,0x00]
+
+ds_write2st64_b64 v2, v[4:5], v[6:7]
+// CHECK: ds_write2st64_b64 v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0x3c,0xd9,0x02,0x04,0x06,0x00]
+
+ds_cmpst_b64 v2, v[4:5], v[6:7]
+// CHECK: ds_cmpst_b64 v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0x40,0xd9,0x02,0x04,0x06,0x00]
+
+ds_cmpst_f64 v2, v[4:5], v[6:7]
+// CHECK: ds_cmpst_f64 v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0x44,0xd9,0x02,0x04,0x06,0x00]
+
+ds_min_f64 v2, v[4:5]
+// CHECK: ds_min_f64 v2, v[4:5] ; encoding: [0x00,0x00,0x48,0xd9,0x02,0x04,0x00,0x00]
+
+ds_max_f64 v2, v[4:5]
+// CHECK: ds_max_f64 v2, v[4:5] ; encoding: [0x00,0x00,0x4c,0xd9,0x02,0x04,0x00,0x00]
+
+ds_add_rtn_u64 v[8:9], v2, v[4:5]
+// CHECK: ds_add_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x80,0xd9,0x02,0x04,0x00,0x08]
+
+ds_sub_rtn_u64 v[8:9], v2, v[4:5]
+// CHECK: ds_sub_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x84,0xd9,0x02,0x04,0x00,0x08]
+
+ds_rsub_rtn_u64 v[8:9], v2, v[4:5]
+// CHECK: ds_rsub_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x88,0xd9,0x02,0x04,0x00,0x08]
+
+ds_inc_rtn_u64 v[8:9], v2, v[4:5]
+// CHECK: ds_inc_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x8c,0xd9,0x02,0x04,0x00,0x08]
+
+ds_dec_rtn_u64 v[8:9] v2, v[4:5]
+// CHECK: ds_dec_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x90,0xd9,0x02,0x04,0x00,0x08]
+
+ds_min_rtn_i64 v[8:9], v2, v[4:5]
+// CHECK: ds_min_rtn_i64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x94,0xd9,0x02,0x04,0x00,0x08]
+
+ds_max_rtn_i64 v[8:9], v2, v[4:5]
+// CHECK: ds_max_rtn_i64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x98,0xd9,0x02,0x04,0x00,0x08]
+
+ds_min_rtn_u64 v[8:9], v2, v[4:5]
+// CHECK: ds_min_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x9c,0xd9,0x02,0x04,0x00,0x08]
+
+ds_max_rtn_u64 v[8:9], v2, v[4:5]
+// CHECK: ds_max_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xa0,0xd9,0x02,0x04,0x00,0x08]
+
+ds_and_rtn_b64 v[8:9], v2, v[4:5]
+// CHECK: ds_and_rtn_b64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xa4,0xd9,0x02,0x04,0x00,0x08]
+
+ds_or_rtn_b64 v[8:9], v2, v[4:5]
+// CHECK: ds_or_rtn_b64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xa8,0xd9,0x02,0x04,0x00,0x08]
+
+ds_xor_rtn_b64 v[8:9], v2, v[4:5]
+// CHECK: ds_xor_rtn_b64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xac,0xd9,0x02,0x04,0x00,0x08]
+
+ds_mskor_rtn_b64 v[8:9], v2, v[4:5], v[6:7]
+// CHECK: ds_mskor_rtn_b64 v[8:9], v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0xb0,0xd9,0x02,0x04,0x06,0x08]
+
+ds_wrxchg_rtn_b64 v[8:9], v2, v[4:5]
+// CHECK: ds_wrxchg_rtn_b64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xb4,0xd9,0x02,0x04,0x00,0x08]
+
+ds_wrxchg2_rtn_b64 v[8:11], v2, v[4:5], v[6:7]
+// CHECK: ds_wrxchg2_rtn_b64 v[8:11], v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0xb8,0xd9,0x02,0x04,0x06,0x08]
+
+ds_wrxchg2st64_rtn_b64 v[8:11], v2, v[4:5], v[6:7]
+// CHECK: ds_wrxchg2st64_rtn_b64 v[8:11], v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0xbc,0xd9,0x02,0x04,0x06,0x08]
+
+ds_cmpst_rtn_b64 v[8:9], v2, v[4:5], v[6:7]
+// CHECK: ds_cmpst_rtn_b64 v[8:9], v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0xc0,0xd9,0x02,0x04,0x06,0x08]
+
+ds_cmpst_rtn_f64 v[8:9], v2, v[4:5], v[6:7]
+// CHECK: ds_cmpst_rtn_f64 v[8:9], v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0xc4,0xd9,0x02,0x04,0x06,0x08]
+
+ds_min_rtn_f64 v[8:9], v2, v[4:5]
+// CHECK: ds_min_rtn_f64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xc8,0xd9,0x02,0x04,0x00,0x08]
+
+ds_max_rtn_f64 v[8:9], v2, v[4:5]
+// CHECK: ds_max_rtn_f64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xcc,0xd9,0x02,0x04,0x00,0x08]
+
+ds_read_b64 v[8:9], v2
+// CHECK: ds_read_b64 v[8:9], v2 ; encoding: [0x00,0x00,0xd8,0xd9,0x02,0x00,0x00,0x08]
+
+ds_read2_b64 v[8:11], v2
+// CHECK: ds_read2_b64 v[8:11], v2 ; encoding: [0x00,0x00,0xdc,0xd9,0x02,0x00,0x00,0x08]
+
+ds_read2st64_b64 v[8:11], v2
+// CHECK: ds_read2st64_b64 v[8:11], v2 ; encoding: [0x00,0x00,0xe0,0xd9,0x02,0x00,0x00,0x08]
diff --git a/test/MC/R600/mubuf.s b/test/MC/R600/mubuf.s
new file mode 100644
index 000000000000..78d365abef13
--- /dev/null
+++ b/test/MC/R600/mubuf.s
@@ -0,0 +1,352 @@
+// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s
+
+//===----------------------------------------------------------------------===//
+// Test for different operand combinations
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// load - immediate offset only
+//===----------------------------------------------------------------------===//
+
+buffer_load_dword v1, s[4:7], s1
+// CHECK: buffer_load_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_load_dword v1, s[4:7], s1 offset:4
+// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_load_dword v1, s[4:7], s1 offset:4 glc
+// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_load_dword v1, s[4:7], s1 offset:4 slc
+// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x41,0x01]
+
+buffer_load_dword v1, s[4:7], s1 offset:4 tfe
+// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x81,0x01]
+
+buffer_load_dword v1, s[4:7], s1 tfe glc
+// CHECK: buffer_load_dword v1, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x30,0xe0,0x00,0x01,0x81,0x01]
+
+buffer_load_dword v1, s[4:7], s1 offset:4 glc tfe slc
+// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xc1,0x01]
+
+buffer_load_dword v1, s[4:7], s1 glc tfe slc offset:4
+// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xc1,0x01]
+
+//===----------------------------------------------------------------------===//
+// load - vgpr offset
+//===----------------------------------------------------------------------===//
+
+buffer_load_dword v1, v2, s[4:7], s1 offen
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen ; encoding: [0x00,0x10,0x30,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_load_dword v1, v2, s[4:7], s1 offen offset:4
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 ; encoding: [0x04,0x10,0x30,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen  offset:4 glc ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc ; encoding: [0x04,0x10,0x30,0xe0,0x02,0x01,0x41,0x01]
+
+buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 tfe
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 tfe ; encoding: [0x04,0x10,0x30,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_load_dword v1, v2, s[4:7], s1 offen tfe glc
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x30,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc tfe slc
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0xc1,0x01]
+
+buffer_load_dword v1, v2, s[4:7], s1 offen glc tfe slc offset:4
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0xc1,0x01]
+
+//===----------------------------------------------------------------------===//
+// load - vgpr index
+//===----------------------------------------------------------------------===//
+
+buffer_load_dword v1, v2, s[4:7], s1 idxen
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen ; encoding: [0x00,0x20,0x30,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 ; encoding: [0x04,0x20,0x30,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x30,0xe0,0x02,0x01,0x41,0x01]
+
+buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 tfe
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 tfe ; encoding: [0x04,0x20,0x30,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_load_dword v1, v2, s[4:7], s1 idxen tfe glc
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x30,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc tfe slc
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0xc1,0x01]
+
+buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe slc offset:4
+// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0xc1,0x01]
+
+//===----------------------------------------------------------------------===//
+// load - vgpr index and offset
+//===----------------------------------------------------------------------===//
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen ; encoding: [0x00,0x30,0x30,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 ; encoding: [0x04,0x30,0x30,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x30,0xe0,0x02,0x01,0x41,0x01]
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe ; encoding: [0x04,0x30,0x30,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen tfe glc
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe ; encoding: [0x00,0x70,0x30,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc tfe slc
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0xc1,0x01]
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe slc offset:4
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0xc1,0x01]
+
+//===----------------------------------------------------------------------===//
+// load - addr64
+//===----------------------------------------------------------------------===//
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 addr64
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 ; encoding: [0x00,0x80,0x30,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 ; encoding: [0x04,0x80,0x30,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc ; encoding: [0x04,0x80,0x30,0xe0,0x02,0x01,0x41,0x01]
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe ; encoding: [0x04,0x80,0x30,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 tfe glc
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe ; encoding: [0x00,0xc0,0x30,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc tfe slc
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xc1,0x01]
+
+buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe slc offset:4
+// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xc1,0x01]
+
+//===----------------------------------------------------------------------===//
+// store - immediate offset only
+//===----------------------------------------------------------------------===//
+
+buffer_store_dword v1, s[4:7], s1
+// CHECK: buffer_store_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x70,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_store_dword v1, s[4:7], s1 offset:4
+// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_store_dword v1, s[4:7], s1 offset:4 glc
+// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_store_dword v1, s[4:7], s1 offset:4 slc
+// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x41,0x01]
+
+buffer_store_dword v1, s[4:7], s1 offset:4 tfe
+// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x81,0x01]
+
+buffer_store_dword v1, s[4:7], s1 tfe glc
+// CHECK: buffer_store_dword v1, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x70,0xe0,0x00,0x01,0x81,0x01]
+
+buffer_store_dword v1, s[4:7], s1 offset:4 glc tfe slc
+// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xc1,0x01]
+
+buffer_store_dword v1, s[4:7], s1 glc tfe slc offset:4
+// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xc1,0x01]
+
+//===----------------------------------------------------------------------===//
+// store - vgpr offset
+//===----------------------------------------------------------------------===//
+
+buffer_store_dword v1, v2, s[4:7], s1 offen
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen ; encoding: [0x00,0x10,0x70,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_store_dword v1, v2, s[4:7], s1 offen offset:4
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen  offset:4 glc ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 slc
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 slc ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x41,0x01]
+
+buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 tfe
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 tfe ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_store_dword v1, v2, s[4:7], s1 offen tfe glc
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x70,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc tfe slc
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xc1,0x01]
+
+buffer_store_dword v1, v2, s[4:7], s1 offen glc tfe slc offset:4
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xc1,0x01]
+
+//===----------------------------------------------------------------------===//
+// store - vgpr index
+//===----------------------------------------------------------------------===//
+
+buffer_store_dword v1, v2, s[4:7], s1 idxen
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen ; encoding: [0x00,0x20,0x70,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 slc
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x41,0x01]
+
+buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 tfe
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 tfe ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_store_dword v1, v2, s[4:7], s1 idxen tfe glc
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x70,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc tfe slc
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xc1,0x01]
+
+buffer_store_dword v1, v2, s[4:7], s1 idxen glc tfe slc offset:4
+// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xc1,0x01]
+
+//===----------------------------------------------------------------------===//
+// store - vgpr index and offset
+//===----------------------------------------------------------------------===//
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen ; encoding: [0x00,0x30,0x70,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x41,0x01]
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen tfe glc
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe ; encoding: [0x00,0x70,0x70,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc tfe slc
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xc1,0x01]
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe slc offset:4
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xc1,0x01]
+
+//===----------------------------------------------------------------------===//
+// store - addr64
+//===----------------------------------------------------------------------===//
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 addr64
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 ; encoding: [0x00,0x80,0x70,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0x01,0x01]
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x41,0x01]
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 tfe glc
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe ; encoding: [0x00,0xc0,0x70,0xe0,0x02,0x01,0x81,0x01]
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc tfe slc
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xc1,0x01]
+
+buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe slc offset:4
+// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xc1,0x01]
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+buffer_load_format_x v1, s[4:7], s1
+// CHECK: buffer_load_format_x v1, s[4:7], s1 ; encoding: [0x00,0x00,0x00,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_load_format_xy v[1:2], s[4:7], s1
+// CHECK: buffer_load_format_xy v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x04,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_load_format_xyz v[1:3], s[4:7], s1
+// CHECK: buffer_load_format_xyz v[1:3], s[4:7], s1 ; encoding: [0x00,0x00,0x08,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_load_format_xyzw v[1:4], s[4:7], s1
+// CHECK: buffer_load_format_xyzw v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x0c,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_store_format_x v1, s[4:7], s1
+// CHECK: buffer_store_format_x v1, s[4:7], s1 ; encoding: [0x00,0x00,0x10,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_store_format_xy v[1:2], s[4:7], s1
+// CHECK: buffer_store_format_xy v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x14,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_store_format_xyz v[1:3], s[4:7], s1
+// CHECK: buffer_store_format_xyz v[1:3], s[4:7], s1 ; encoding: [0x00,0x00,0x18,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_store_format_xyzw v[1:4], s[4:7], s1
+// CHECK: buffer_store_format_xyzw v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_load_ubyte v1, s[4:7], s1
+// CHECK: buffer_load_ubyte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_load_sbyte v1, s[4:7], s1
+// CHECK: buffer_load_sbyte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x24,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_load_ushort v1, s[4:7], s1
+// CHECK: buffer_load_ushort v1, s[4:7], s1 ; encoding: [0x00,0x00,0x28,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_load_sshort v1, s[4:7], s1
+// CHECK: buffer_load_sshort v1, s[4:7], s1 ; encoding: [0x00,0x00,0x2c,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_load_dword v1, s[4:7], s1
+// CHECK: buffer_load_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_load_dwordx2 v[1:2], s[4:7], s1
+// CHECK: buffer_load_dwordx2 v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x34,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_load_dwordx4 v[1:4], s[4:7], s1
+// CHECK: buffer_load_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x38,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_store_byte v1, s[4:7], s1
+// CHECK: buffer_store_byte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_store_short v1, s[4:7], s1
+// CHECK: buffer_store_short v1, s[4:7], s1 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_store_dword v1 s[4:7], s1
+// CHECK: buffer_store_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x70,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_store_dwordx2 v[1:2], s[4:7], s1
+// CHECK: buffer_store_dwordx2 v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x74,0xe0,0x00,0x01,0x01,0x01]
+
+buffer_store_dwordx4 v[1:4], s[4:7], s1
+// CHECK: buffer_store_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x78,0xe0,0x00,0x01,0x01,0x01]
+
+// TODO: Atomics
diff --git a/test/MC/R600/smrd.s b/test/MC/R600/smrd.s
new file mode 100644
index 000000000000..b67abf7e6890
--- /dev/null
+++ b/test/MC/R600/smrd.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s
+
+s_load_dword s1, s[2:3], 1
+// CHECK: s_load_dword s1, s[2:3], 0x1 ; encoding: [0x01,0x83,0x00,0xc0]
+
+s_load_dword s1, s[2:3], s4
+// CHECK: s_load_dword s1, s[2:3], s4 ; encoding: [0x04,0x82,0x00,0xc0]
+
+s_load_dwordx2 s[2:3], s[2:3], 1
+// CHECK: s_load_dwordx2 s[2:3], s[2:3], 0x1 ; encoding: [0x01,0x03,0x41,0xc0]
+
+s_load_dwordx2 s[2:3], s[2:3], s4
+// CHECK: s_load_dwordx2 s[2:3], s[2:3], s4 ; encoding: [0x04,0x02,0x41,0xc0]
+
+s_load_dwordx4 s[4:7], s[2:3], 1
+// CHECK: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x03,0x82,0xc0]
+
+s_load_dwordx4 s[4:7], s[2:3], s4
+// CHECK: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x04,0x02,0x82,0xc0]
+
+s_load_dwordx8 s[8:15], s[2:3], 1
+// CHECK: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x03,0xc4,0xc0]
+
+s_load_dwordx8 s[8:15], s[2:3], s4
+// CHECK: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x04,0x02,0xc4,0xc0]
+
+s_load_dwordx16 s[16:31], s[2:3], 1
+// CHECK: s_load_dwordx16 s[16:31], s[2:3], 0x1 ; encoding: [0x01,0x03,0x08,0xc1]
+
+s_load_dwordx16 s[16:31], s[2:3], s4
+// CHECK: s_load_dwordx16 s[16:31], s[2:3], s4 ; encoding: [0x04,0x02,0x08,0xc1]
diff --git a/test/MC/R600/sop1-err.s b/test/MC/R600/sop1-err.s
new file mode 100644
index 000000000000..f892356b623d
--- /dev/null
+++ b/test/MC/R600/sop1-err.s
@@ -0,0 +1,37 @@
+// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s
+
+s_mov_b32 v1, s2
+// CHECK: error: invalid operand for instruction
+
+s_mov_b32 s1, v0
+// CHECK: error: invalid operand for instruction
+
+s_mov_b32 s[1:2], s0
+// CHECK: error: invalid operand for instruction
+
+s_mov_b32 s0, s[1:2]
+// CHECK: error: invalid operand for instruction
+
+s_mov_b32 s220, s0
+// CHECK: error: invalid operand for instruction
+
+s_mov_b32 s0, s220
+// CHECK: error: invalid operand for instruction
+
+s_mov_b64 s1, s[0:1]
+// CHECK: error: invalid operand for instruction
+
+s_mov_b64 s[0:1], s1
+// CHECK: error: invalid operand for instruction
+
+// Immediate greater than 32-bits
+s_mov_b32 s1, 0xfffffffff
+// CHECK: error: invalid immediate: only 32-bit values are legal
+
+// Immediate greater than 32-bits
+s_mov_b64 s[0:1], 0xfffffffff
+// CHECK: error: invalid immediate: only 32-bit values are legal
+
+// Out of range register
+s_mov_b32 s
diff --git a/test/MC/R600/sop1.s b/test/MC/R600/sop1.s
new file mode 100644
index 000000000000..92ca73f25004
--- /dev/null
+++ b/test/MC/R600/sop1.s
@@ -0,0 +1,177 @@
+// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s
+
+s_mov_b32 s1, s2
+// CHECK: s_mov_b32 s1, s2 ; encoding: [0x02,0x03,0x81,0xbe]
+
+s_mov_b32 s1, 1
+// CHECK: s_mov_b32 s1, 1 ; encoding: [0x81,0x03,0x81,0xbe]
+
+s_mov_b32 s1, 100
+// CHECK: s_mov_b32 s1, 0x64 ; encoding: [0xff,0x03,0x81,0xbe,0x64,0x00,0x00,0x00]
+
+s_mov_b64 s[2:3], s[4:5]
+// CHECK: s_mov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x04,0x82,0xbe]
+
+s_mov_b64 s[2:3], 0xffffffffffffffff
+// CHECK: s_mov_b64 s[2:3], -1 ; encoding: [0xc1,0x04,0x82,0xbe]
+
+s_cmov_b32 s1, 200
+// CHECK: s_cmov_b32 s1, 0xc8 ; encoding: [0xff,0x05,0x81,0xbe,0xc8,0x00,0x00,0x00]
+
+s_cmov_b32 s1, 1.0
+// CHECK: s_cmov_b32 s1, 1.0 ; encoding: [0xf2,0x05,0x81,0xbe]
+
+//s_cmov_b64 s[2:3], 1.0
+//CHECK-FIXME: s_cmov_b64 s[2:3], 1.0 ; encoding: [0xf2,0x05,0x82,0xb3]
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+s_mov_b32 s1, s2
+// CHECK: s_mov_b32 s1, s2 ; encoding: [0x02,0x03,0x81,0xbe]
+
+s_mov_b64 s[2:3], s[4:5]
+// CHECK: s_mov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x04,0x82,0xbe]
+
+s_cmov_b32 s1, s2
+// CHECK: s_cmov_b32 s1, s2 ; encoding: [0x02,0x05,0x81,0xbe]
+
+s_cmov_b64 s[2:3], s[4:5]
+// CHECK: s_cmov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x06,0x82,0xbe]
+
+s_not_b32 s1, s2
+// CHECK: s_not_b32 s1, s2 ; encoding: [0x02,0x07,0x81,0xbe]
+
+s_not_b64 s[2:3], s[4:5]
+// CHECK: s_not_b64 s[2:3], s[4:5] ; encoding: [0x04,0x08,0x82,0xbe]
+
+s_wqm_b32 s1, s2
+// CHECK: s_wqm_b32 s1, s2 ; encoding: [0x02,0x09,0x81,0xbe]
+
+s_wqm_b64 s[2:3], s[4:5]
+// CHECK: s_wqm_b64 s[2:3], s[4:5] ; encoding: [0x04,0x0a,0x82,0xbe]
+
+s_brev_b32 s1, s2
+// CHECK: s_brev_b32 s1, s2 ; encoding: [0x02,0x0b,0x81,0xbe]
+
+s_brev_b64 s[2:3], s[4:5]
+// CHECK: s_brev_b64 s[2:3], s[4:5] ; encoding: [0x04,0x0c,0x82,0xbe]
+
+s_bcnt0_i32_b32 s1, s2
+// CHECK: s_bcnt0_i32_b32 s1, s2 ; encoding: [0x02,0x0d,0x81,0xbe]
+
+s_bcnt0_i32_b64 s1, s[2:3]
+// CHECK: s_bcnt0_i32_b64 s1, s[2:3] ; encoding: [0x02,0x0e,0x81,0xbe]
+
+s_bcnt1_i32_b32 s1, s2
+// CHECK: s_bcnt1_i32_b32 s1, s2 ; encoding: [0x02,0x0f,0x81,0xbe]
+
+s_bcnt1_i32_b64 s1, s[2:3]
+// CHECK: s_bcnt1_i32_b64 s1, s[2:3] ; encoding: [0x02,0x10,0x81,0xbe]
+
+s_ff0_i32_b32 s1, s2
+// CHECK: s_ff0_i32_b32 s1, s2 ; encoding: [0x02,0x11,0x81,0xbe]
+
+s_ff0_i32_b64 s1, s[2:3]
+// CHECK: s_ff0_i32_b64 s1, s[2:3] ; encoding: [0x02,0x12,0x81,0xbe]
+
+s_ff1_i32_b32 s1, s2
+// CHECK: s_ff1_i32_b32 s1, s2 ; encoding: [0x02,0x13,0x81,0xbe]
+
+s_ff1_i32_b64 s1, s[2:3]
+// CHECK: s_ff1_i32_b64 s1, s[2:3] ; encoding: [0x02,0x14,0x81,0xbe]
+
+s_flbit_i32_b32 s1, s2
+// CHECK: s_flbit_i32_b32 s1, s2 ; encoding: [0x02,0x15,0x81,0xbe]
+
+s_flbit_i32_b64 s1, s[2:3]
+// CHECK: s_flbit_i32_b64 s1, s[2:3] ; encoding: [0x02,0x16,0x81,0xbe]
+
+s_flbit_i32 s1, s2
+// CHECK: s_flbit_i32 s1, s2 ; encoding: [0x02,0x17,0x81,0xbe]
+
+s_flbit_i32_i64 s1, s[2:3]
+// CHECK: s_flbit_i32_i64 s1, s[2:3] ; encoding: [0x02,0x18,0x81,0xbe]
+
+s_sext_i32_i8 s1, s2
+// CHECK: s_sext_i32_i8 s1, s2 ; encoding: [0x02,0x19,0x81,0xbe]
+
+s_sext_i32_i16 s1, s2
+// CHECK: s_sext_i32_i16 s1, s2 ; encoding: [0x02,0x1a,0x81,0xbe]
+
+s_bitset0_b32 s1, s2
+// CHECK: s_bitset0_b32 s1, s2 ; encoding: [0x02,0x1b,0x81,0xbe]
+
+s_bitset0_b64 s[2:3], s[4:5]
+// CHECK: s_bitset0_b64 s[2:3], s[4:5] ; encoding: [0x04,0x1c,0x82,0xbe]
+
+s_bitset1_b32 s1, s2
+// CHECK: s_bitset1_b32 s1, s2 ; encoding: [0x02,0x1d,0x81,0xbe]
+
+s_bitset1_b64 s[2:3], s[4:5]
+// CHECK: s_bitset1_b64 s[2:3], s[4:5] ; encoding: [0x04,0x1e,0x82,0xbe]
+
+s_getpc_b64 s[2:3]
+// CHECK: s_getpc_b64 s[2:3] ; encoding: [0x00,0x1f,0x82,0xbe]
+
+s_setpc_b64 s[2:3], s[4:5]
+// CHECK: s_setpc_b64 s[2:3], s[4:5] ; encoding: [0x04,0x20,0x82,0xbe]
+
+s_swappc_b64 s[2:3], s[4:5]
+// CHECK: s_swappc_b64 s[2:3], s[4:5] ; encoding: [0x04,0x21,0x82,0xbe]
+
+s_rfe_b64 s[2:3], s[4:5]
+// CHECK: s_rfe_b64 s[2:3], s[4:5] ; encoding: [0x04,0x22,0x82,0xbe]
+
+s_and_saveexec_b64 s[2:3], s[4:5]
+// CHECK: s_and_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x24,0x82,0xbe]
+
+s_or_saveexec_b64 s[2:3], s[4:5]
+// CHECK: s_or_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x25,0x82,0xbe]
+
+s_xor_saveexec_b64 s[2:3], s[4:5]
+// CHECK: s_xor_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x26,0x82,0xbe]
+
+s_andn2_saveexec_b64 s[2:3], s[4:5]
+// CHECK: s_andn2_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x27,0x82,0xbe]
+
+s_orn2_saveexec_b64 s[2:3], s[4:5]
+// CHECK: s_orn2_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x28,0x82,0xbe]
+
+s_nand_saveexec_b64 s[2:3], s[4:5]
+// CHECK: s_nand_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x29,0x82,0xbe]
+
+s_nor_saveexec_b64 s[2:3], s[4:5]
+// CHECK: s_nor_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2a,0x82,0xbe]
+
+s_xnor_saveexec_b64 s[2:3], s[4:5]
+// CHECK: s_xnor_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2b,0x82,0xbe]
+
+s_quadmask_b32 s1, s2
+// CHECK: s_quadmask_b32 s1, s2 ; encoding: [0x02,0x2c,0x81,0xbe]
+
+s_quadmask_b64 s[2:3], s[4:5]
+// CHECK: s_quadmask_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2d,0x82,0xbe]
+
+s_movrels_b32 s1, s2
+// CHECK: s_movrels_b32 s1, s2 ; encoding: [0x02,0x2e,0x81,0xbe]
+
+s_movrels_b64 s[2:3], s[4:5]
+// CHECK: s_movrels_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2f,0x82,0xbe]
+
+s_movreld_b32 s1, s2
+// CHECK: s_movreld_b32 s1, s2 ; encoding: [0x02,0x30,0x81,0xbe]
+
+s_movreld_b64 s[2:3], s[4:5]
+// CHECK: s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x31,0x82,0xbe]
+
+s_cbranch_join s[4:5]
+// CHECK: s_cbranch_join s[4:5] ; encoding: [0x04,0x32,0x80,0xbe]
+
+s_abs_i32 s1, s2
+// CHECK: s_abs_i32 s1, s2 ; encoding: [0x02,0x34,0x81,0xbe]
+
+s_mov_fed_b32 s1, s2
+// CHECK: s_mov_fed_b32 s1, s2 ; encoding: [0x02,0x35,0x81,0xbe]
diff --git a/test/MC/R600/sop2.s b/test/MC/R600/sop2.s
new file mode 100644
index 000000000000..9a7a1c01064b
--- /dev/null
+++ b/test/MC/R600/sop2.s
@@ -0,0 +1,131 @@
+// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s
+
+// CHECK: s_add_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x80]
+s_add_u32 s1, s2, s3
+
+// CHECK: s_sub_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x81,0x80]
+s_sub_u32 s1, s2, s3
+
+// CHECK: s_add_i32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x81]
+s_add_i32 s1, s2, s3
+
+// CHECK: s_sub_i32 s1, s2, s3 ; encoding: [0x02,0x03,0x81,0x81]
+s_sub_i32 s1, s2, s3
+
+// CHECK: s_addc_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x82]
+s_addc_u32 s1, s2, s3
+
+// CHECK: s_subb_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x81,0x82]
+s_subb_u32 s1, s2, s3
+
+// CHECK: s_min_i32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x83]
+s_min_i32 s1, s2, s3
+
+// CHECK: s_min_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x81,0x83]
+s_min_u32 s1, s2, s3
+
+// CHECK: s_max_i32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x84]
+s_max_i32 s1, s2, s3
+
+// CHECK: s_max_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x81,0x84]
+s_max_u32 s1, s2, s3
+
+// CHECK: s_cselect_b32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x85]
+s_cselect_b32 s1, s2, s3
+
+// CHECK: s_cselect_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x85]
+s_cselect_b64 s[2:3], s[4:5], s[6:7]
+
+// CHECK: s_and_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x87]
+s_and_b32 s2, s4, s6
+
+// CHECK: s_and_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x87]
+s_and_b64 s[2:3], s[4:5], s[6:7]
+
+// CHECK: s_or_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x88]
+s_or_b32 s2, s4, s6
+
+// CHECK: s_or_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x88]
+s_or_b64 s[2:3], s[4:5], s[6:7]
+
+// CHECK: s_xor_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x89]
+s_xor_b32 s2, s4, s6
+
+// CHECK: s_xor_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x89]
+s_xor_b64 s[2:3], s[4:5], s[6:7]
+
+// CHECK: s_andn2_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8a]
+s_andn2_b32 s2, s4, s6
+
+// CHECK: s_andn2_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x8a]
+s_andn2_b64 s[2:3], s[4:5], s[6:7]
+
+// CHECK: s_orn2_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8b]
+s_orn2_b32 s2, s4, s6
+
+// CHECK: s_orn2_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x8b]
+s_orn2_b64 s[2:3], s[4:5], s[6:7]
+
+// CHECK: s_nand_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8c]
+s_nand_b32 s2, s4, s6
+
+// CHECK: s_nand_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x8c]
+s_nand_b64 s[2:3], s[4:5], s[6:7]
+
+// CHECK: s_nor_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8d]
+s_nor_b32 s2, s4, s6
+
+// CHECK: s_nor_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x8d]
+s_nor_b64 s[2:3], s[4:5], s[6:7]
+
+// CHECK: s_xnor_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8e]
+s_xnor_b32 s2, s4, s6
+
+// CHECK: s_xnor_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x8e]
+s_xnor_b64 s[2:3], s[4:5], s[6:7]
+
+// CHECK: s_lshl_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8f]
+s_lshl_b32 s2, s4, s6
+
+// CHECK: s_lshl_b64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x82,0x8f]
+s_lshl_b64 s[2:3], s[4:5], s6
+
+// CHECK: s_lshr_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x90]
+s_lshr_b32 s2, s4, s6
+
+// CHECK: s_lshr_b64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x82,0x90]
+s_lshr_b64 s[2:3], s[4:5], s6
+
+// CHECK: s_ashr_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x91]
+s_ashr_i32 s2, s4, s6
+
+// CHECK: s_ashr_i64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x82,0x91]
+s_ashr_i64 s[2:3], s[4:5], s6
+
+// CHECK: s_bfm_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x92]
+s_bfm_b32 s2, s4, s6
+
+// CHECK: s_bfm_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x92]
+s_bfm_b64 s[2:3], s[4:5], s[6:7]
+
+// CHECK: s_mul_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x93]
+s_mul_i32 s2, s4, s6
+
+// CHECK: s_bfe_u32 s2, s4, s6 ; encoding: [0x04,0x06,0x82,0x93]
+s_bfe_u32 s2, s4, s6
+
+// CHECK: s_bfe_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x94]
+s_bfe_i32 s2, s4, s6
+
+// CHECK: s_bfe_u64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x94]
+s_bfe_u64 s[2:3], s[4:5], s[6:7]
+
+// CHECK: s_bfe_i64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x02,0x95]
+s_bfe_i64 s[2:3], s[4:5], s6
+
+// CHECK: s_cbranch_g_fork s[4:5], s[6:7] ; encoding: [0x04,0x06,0x80,0x95]
+s_cbranch_g_fork s[4:5], s[6:7]
+
+// CHECK: s_absdiff_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x96]
+s_absdiff_i32 s2, s4, s6
diff --git a/test/MC/R600/sopc.s b/test/MC/R600/sopc.s
new file mode 100644
index 000000000000..0899c1a2eede
--- /dev/null
+++ b/test/MC/R600/sopc.s
@@ -0,0 +1,9 @@
+// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+s_cmp_eq_i32 s1, s2
+// CHECK: s_cmp_eq_i32 s1, s2 ; encoding: [0x01,0x02,0x00,0xbf]
diff --git a/test/MC/R600/sopk.s b/test/MC/R600/sopk.s
new file mode 100644
index 000000000000..6c27aaccb80c
--- /dev/null
+++ b/test/MC/R600/sopk.s
@@ -0,0 +1,66 @@
+// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+s_movk_i32 s2, 0x6
+// CHECK: s_movk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb0]
+
+s_cmovk_i32 s2, 0x6
+// CHECK: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1]
+
+s_cmpk_eq_i32 s2, 0x6
+// CHECK: s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1]
+
+s_cmpk_lg_i32 s2, 0x6
+// CHECK: s_cmpk_lg_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb2]
+
+s_cmpk_gt_i32 s2, 0x6
+// CHECK: s_cmpk_gt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb2]
+
+s_cmpk_ge_i32 s2, 0x6
+// CHECK: s_cmpk_ge_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb3]
+
+s_cmpk_lt_i32 s2, 0x6
+// CHECK: s_cmpk_lt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb3]
+
+s_cmpk_le_i32 s2, 0x6
+// CHECK: s_cmpk_le_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb4]
+
+s_cmpk_eq_u32 s2, 0x6
+// CHECK: s_cmpk_eq_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb4]
+
+s_cmpk_lg_u32 s2, 0x6
+// CHECK: s_cmpk_lg_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb5]
+
+s_cmpk_gt_u32 s2, 0x6
+// CHECK: s_cmpk_gt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb5]
+
+s_cmpk_ge_u32 s2, 0x6
+// CHECK: s_cmpk_ge_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb6]
+
+s_cmpk_lt_u32 s2, 0x6
+// CHECK: s_cmpk_lt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb6]
+
+s_cmpk_le_u32 s2, 0x6
+// CHECK: s_cmpk_le_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb7]
+
+s_addk_i32 s2, 0x6
+// CHECK: s_addk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7]
+
+s_mulk_i32 s2, 0x6
+// CHECK: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
+
+s_cbranch_i_fork s[2:3], 0x6
+// CHECK: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x82,0xb8]
+
+s_getreg_b32 s2, 0x6
+// CHECK: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9]
+
+s_setreg_b32 s2, 0x6
+// CHECK: s_setreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb9]
+
+s_setreg_imm32_b32 0xff, 0x6
+// CHECK: s_setreg_imm32_b32 0xff, 0x6 ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00]
diff --git a/test/MC/R600/sopp.s b/test/MC/R600/sopp.s
index 0f186b17b2d8..b072c16fdb24 100644
--- a/test/MC/R600/sopp.s
+++ b/test/MC/R600/sopp.s
@@ -1,4 +1,16 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=SI  -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s
+
+//===----------------------------------------------------------------------===//
+// Edge Cases
+//===----------------------------------------------------------------------===//
+
+s_nop 0       // CHECK: s_nop 0 ; encoding: [0x00,0x00,0x80,0xbf] 
+s_nop 0xffff  // CHECK: s_nop 0xffff ; encoding: [0xff,0xff,0x80,0xbf]
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
 
   s_nop 1            // CHECK: s_nop 1 ; encoding: [0x01,0x00,0x80,0xbf]
   s_endpgm           // CHECK: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
diff --git a/test/MC/R600/vop1.s b/test/MC/R600/vop1.s
new file mode 100644
index 000000000000..d0b00fcd1897
--- /dev/null
+++ b/test/MC/R600/vop1.s
@@ -0,0 +1,357 @@
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=CIVI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI
+
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s -check-prefix=NOVI
+
+
+// GCN: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
+v_nop
+
+// GCN: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
+v_mov_b32 v1, v2
+
+// GCN: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
+v_readfirstlane_b32 s1, v2
+
+// GCN: v_cvt_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x07,0x02,0x7e]
+v_cvt_i32_f64 v1, v[2:3]
+
+// GCN: v_cvt_f64_i32_e32 v[1:2], v2 ; encoding: [0x02,0x09,0x02,0x7e]
+v_cvt_f64_i32 v[1:2], v2
+
+// GCN: v_cvt_f32_i32_e32 v1, v2 ; encoding: [0x02,0x0b,0x02,0x7e]
+v_cvt_f32_i32 v1, v2
+
+// GCN: v_cvt_f32_u32_e32 v1, v2 ; encoding: [0x02,0x0d,0x02,0x7e]
+v_cvt_f32_u32 v1, v2
+
+// GCN: v_cvt_u32_f32_e32 v1, v2 ; encoding: [0x02,0x0f,0x02,0x7e
+v_cvt_u32_f32 v1, v2
+
+// GCN: v_cvt_i32_f32_e32 v1, v2 ; encoding: [0x02,0x11,0x02,0x7e]
+v_cvt_i32_f32 v1, v2
+
+// SICI: v_mov_fed_b32_e32 v1, v2 ; encoding: [0x02,0x13,0x02,0x7e]
+// NOVI: error: instruction not supported on this GPU
+v_mov_fed_b32 v1, v2
+
+// GCN: v_cvt_f16_f32_e32 v1, v2 ; encoding: [0x02,0x15,0x02,0x7e]
+v_cvt_f16_f32 v1, v2
+
+// GCN: v_cvt_f32_f16_e32 v1, v2 ; encoding: [0x02,0x17,0x02,0x7e]
+v_cvt_f32_f16 v1, v2
+
+// GCN: v_cvt_rpi_i32_f32_e32 v1, v2 ; encoding: [0x02,0x19,0x02,0x7e]
+v_cvt_rpi_i32_f32 v1, v2
+
+// GCN: v_cvt_flr_i32_f32_e32 v1, v2 ; encoding: [0x02,0x1b,0x02,0x7e]
+v_cvt_flr_i32_f32 v1, v2
+
+// GCN: v_cvt_off_f32_i4_e32 v1, v2 ; encoding: [0x02,0x1d,0x02,0x7e]
+v_cvt_off_f32_i4_e32 v1, v2
+
+// GCN: v_cvt_f32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x1f,0x02,0x7e]
+v_cvt_f32_f64 v1, v[2:3]
+
+// GCN: v_cvt_f64_f32_e32 v[1:2], v2 ; encoding: [0x02,0x21,0x02,0x7e]
+v_cvt_f64_f32 v[1:2], v2
+
+// GCN: v_cvt_f32_ubyte0_e32 v1, v2 ; encoding: [0x02,0x23,0x02,0x7e]
+v_cvt_f32_ubyte0 v1, v2
+
+// GCN: v_cvt_f32_ubyte1_e32 v1, v2 ; encoding: [0x02,0x25,0x02,0x7e]
+v_cvt_f32_ubyte1_e32 v1, v2
+
+// GCN: v_cvt_f32_ubyte2_e32 v1, v2 ; encoding: [0x02,0x27,0x02,0x7e]
+v_cvt_f32_ubyte2 v1, v2
+
+// GCN: v_cvt_f32_ubyte3_e32 v1, v2 ; encoding: [0x02,0x29,0x02,0x7e]
+v_cvt_f32_ubyte3 v1, v2
+
+// GCN: v_cvt_u32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x2b,0x02,0x7e]
+v_cvt_u32_f64 v1, v[2:3]
+
+// GCN: v_cvt_f64_u32_e32 v[1:2], v2 ; encoding: [0x02,0x2d,0x02,0x7e]
+v_cvt_f64_u32 v[1:2], v2
+
+// NOSI: error: instruction not supported on this GPU
+// NOSI: v_trunc_f64_e32 v[1:2], v[2:3]
+// CIVI: v_trunc_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x2f,0x02,0x7e]
+v_trunc_f64_e32 v[1:2], v[2:3]
+
+// NOSI: error: instruction not supported on this GPU
+// NOSI: v_ceil_f64_e32 v[1:2], v[2:3]
+// CIVI: v_ceil_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x31,0x02,0x7e]
+v_ceil_f64_e32 v[1:2], v[2:3]
+
+// NOSI: error: instruction not supported on this GPU
+// NOSI: v_rndne_f64_e32 v[1:2], v[2:3]
+// CIVI: v_rndne_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x33,0x02,0x7e]
+v_rndne_f64_e32 v[1:2], v[2:3]
+
+// NOSI: error: instruction not supported on this GPU
+// NOSI: v_floor_f64_e32 v[1:2], v[2:3]
+// CIVI: v_floor_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x35,0x02,0x7e]
+v_floor_f64_e32 v[1:2], v[2:3]
+
+// SICI: v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x41,0x02,0x7e]
+// VI:   v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x37,0x02,0x7e]
+v_fract_f32 v1, v2
+
+// SICI: v_trunc_f32_e32 v1, v2 ; encoding: [0x02,0x43,0x02,0x7e]
+// VI:   v_trunc_f32_e32 v1, v2 ; encoding: [0x02,0x39,0x02,0x7e]
+v_trunc_f32 v1, v2
+
+// SICI: v_ceil_f32_e32 v1, v2 ; encoding: [0x02,0x45,0x02,0x7e]
+// VI:   v_ceil_f32_e32 v1, v2 ; encoding: [0x02,0x3b,0x02,0x7e]
+v_ceil_f32 v1, v2
+
+// SICI: v_rndne_f32_e32 v1, v2 ; encoding: [0x02,0x47,0x02,0x7e]
+// VI:   v_rndne_f32_e32 v1, v2 ; encoding: [0x02,0x3d,0x02,0x7e]
+v_rndne_f32 v1, v2
+
+// SICI: v_floor_f32_e32 v1, v2 ; encoding: [0x02,0x49,0x02,0x7e]
+// VI:   v_floor_f32_e32 v1, v2 ; encoding: [0x02,0x3f,0x02,0x7e]
+v_floor_f32_e32 v1, v2
+
+// SICI: v_exp_f32_e32 v1, v2 ; encoding: [0x02,0x4b,0x02,0x7e]
+// VI:   v_exp_f32_e32 v1, v2 ; encoding: [0x02,0x41,0x02,0x7e]
+v_exp_f32 v1, v2
+
+// SICI: v_log_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x4d,0x02,0x7e]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_log_clamp_f32 v1, v2
+v_log_clamp_f32 v1, v2
+
+// SICI: v_log_f32_e32 v1, v2 ; encoding: [0x02,0x4f,0x02,0x7e]
+// VI:   v_log_f32_e32 v1, v2 ; encoding: [0x02,0x43,0x02,0x7e]
+v_log_f32 v1, v2
+
+// SICI: v_rcp_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x51,0x02,0x7e]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_rcp_clamp_f32 v1, v2
+v_rcp_clamp_f32 v1, v2
+
+// SICI: v_rcp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x53,0x02,0x7e]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_rcp_legacy_f32 v1, v2
+v_rcp_legacy_f32 v1, v2
+
+// SICI: v_rcp_f32_e32 v1, v2 ; encoding: [0x02,0x55,0x02,0x7e]
+// VI:   v_rcp_f32_e32 v1, v2 ; encoding: [0x02,0x45,0x02,0x7e]
+v_rcp_f32 v1, v2
+
+// SICI: v_rcp_iflag_f32_e32 v1, v2 ; encoding: [0x02,0x57,0x02,0x7e]
+// VI:   v_rcp_iflag_f32_e32 v1, v2 ; encoding: [0x02,0x47,0x02,0x7e]
+v_rcp_iflag_f32 v1, v2
+
+// SICI: v_rsq_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x59,0x02,0x7e]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_rsq_clamp_f32 v1, v2
+v_rsq_clamp_f32 v1, v2
+
+// SICI: v_rsq_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x5b,0x02,0x7e]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_rsq_legacy_f32 v1, v2
+v_rsq_legacy_f32 v1, v2
+
+// SICI: v_rsq_f32_e32 v1, v2 ; encoding: [0x02,0x5d,0x02,0x7e]
+// VI:   v_rsq_f32_e32 v1, v2 ; encoding: [0x02,0x49,0x02,0x7e]
+v_rsq_f32_e32 v1, v2
+
+// SICI: v_rcp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x5f,0x02,0x7e]
+// VI:   v_rcp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x4b,0x02,0x7e]
+v_rcp_f64 v[1:2], v[2:3]
+
+// SICI: v_rcp_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x61,0x02,0x7e]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_rcp_clamp_f64 v[1:2], v[2:3]
+v_rcp_clamp_f64 v[1:2], v[2:3]
+
+// SICI: v_rsq_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e]
+// VI:   v_rsq_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x4d,0x02,0x7e]
+v_rsq_f64 v[1:2], v[2:3]
+
+// SICI: v_rsq_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x65,0x02,0x7e]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_rsq_clamp_f64 v[1:2], v[2:3]
+v_rsq_clamp_f64 v[1:2], v[2:3]
+
+// SICI: v_sqrt_f32_e32 v1, v2 ; encoding: [0x02,0x67,0x02,0x7e]
+// VI:   v_sqrt_f32_e32 v1, v2 ; encoding: [0x02,0x4f,0x02,0x7e]
+v_sqrt_f32 v1, v2
+
+// SICI: v_sqrt_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x69,0x02,0x7e]
+// VI:   v_sqrt_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x51,0x02,0x7e]
+v_sqrt_f64 v[1:2], v[2:3]
+
+// SICI: v_sin_f32_e32 v1, v2 ; encoding: [0x02,0x6b,0x02,0x7e]
+// VI:   v_sin_f32_e32 v1, v2 ; encoding: [0x02,0x53,0x02,0x7e]
+v_sin_f32 v1, v2
+
+// SICI: v_cos_f32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e]
+// VI:   v_cos_f32_e32 v1, v2 ; encoding: [0x02,0x55,0x02,0x7e]
+v_cos_f32 v1, v2
+
+// SICI: v_not_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e]
+// VI:   v_not_b32_e32 v1, v2 ; encoding: [0x02,0x57,0x02,0x7e]
+v_not_b32 v1, v2
+
+// SICI: v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e]
+// VI:   v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x59,0x02,0x7e]
+v_bfrev_b32 v1, v2
+
+// SICI: v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e]
+// VI:   v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x5b,0x02,0x7e]
+v_ffbh_u32 v1, v2
+
+// SICI: v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e]
+// VI:   v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x5d,0x02,0x7e]
+v_ffbl_b32 v1, v2
+
+// SICI: v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e]
+// VI:   v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x5f,0x02,0x7e]
+v_ffbh_i32_e32 v1, v2
+
+// SICI: v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x79,0x02,0x7e]
+// VI:   v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x61,0x02,0x7e]
+v_frexp_exp_i32_f64 v1, v[2:3]
+
+// SICI: v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7b,0x02,0x7e]
+// VI;   v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e]
+v_frexp_mant_f64 v[1:2], v[2:3]
+
+// SICI: v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7d,0x02,0x7e]
+// VI:   v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x65,0x02,0x7e]
+v_fract_f64 v[1:2], v[2:3]
+
+// SICI: v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e]
+// VI:   v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x67,0x02,0x7e]
+v_frexp_exp_i32_f32 v1, v2
+
+// SICI: v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e]
+// VI:   v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x69,0x02,0x7e]
+v_frexp_mant_f32 v1, v2
+
+// SICI: v_clrexcp ; encoding: [0x00,0x82,0x00,0x7e]
+// VI:   v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
+v_clrexcp
+
+// SICI: v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e]
+// VI:   v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e]
+v_movreld_b32 v1, v2
+
+// SICI: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e]
+// VI:   v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e]
+v_movrels_b32 v1, v2
+
+// SICI: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e]
+// VI:   v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e]
+v_movrelsd_b32 v1, v2
+
+// NOSI: error: instruction not supported on this GPU
+// NOSI: v_log_legacy_f32 v1, v2
+// CI: v_log_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x8b,0x02,0x7e]
+// VI: v_log_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x99,0x02,0x7e]
+v_log_legacy_f32 v1, v2
+
+// NOSI: error: instruction not supported on this GPU
+// NOSI: v_exp_legacy_f32 v1, v2
+// CI: v_exp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x8d,0x02,0x7e]
+// VI: v_exp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x97,0x02,0x7e]
+v_exp_legacy_f32 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_cvt_f16_u16 v1, v2
+// VI: v_cvt_f16_u16_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e]
+v_cvt_f16_u16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_cvt_f16_i16 v1, v2
+// VI: v_cvt_f16_i16_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e]
+v_cvt_f16_i16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_cvt_u16_f16 v1, v2
+// VI: v_cvt_u16_f16_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e]
+v_cvt_u16_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_cvt_i16_f16 v1, v2
+// VI: v_cvt_i16_f16_e32 v1, v2 ; encoding: [0x02,0x79,0x02,0x7e]
+v_cvt_i16_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_rcp_f16 v1, v2
+// VI: v_rcp_f16_e32 v1, v2 ; encoding: [0x02,0x7b,0x02,0x7e]
+v_rcp_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_sqrt_f16 v1, v2
+// VI: v_sqrt_f16_e32 v1, v2 ; encoding: [0x02,0x7d,0x02,0x7e]
+v_sqrt_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_rsq_f16 v1, v2
+// VI: v_rsq_f16_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e]
+v_rsq_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_log_f16 v1, v2
+// VI: v_log_f16_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e]
+v_log_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_exp_f16 v1, v2
+// VI: v_exp_f16_e32 v1, v2 ; encoding: [0x02,0x83,0x02,0x7e]
+v_exp_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_frexp_mant_f16 v1, v2
+// VI: v_frexp_mant_f16_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e]
+v_frexp_mant_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_frexp_exp_i16_f16 v1, v2
+// VI: v_frexp_exp_i16_f16_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e]
+v_frexp_exp_i16_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_floor_f16 v1, v2
+// VI: v_floor_f16_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e]
+v_floor_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_ceil_f16 v1, v2
+// VI: v_ceil_f16_e32 v1, v2 ; encoding: [0x02,0x8b,0x02,0x7e]
+v_ceil_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_trunc_f16 v1, v2
+// VI: v_trunc_f16_e32 v1, v2 ; encoding: [0x02,0x8d,0x02,0x7e]
+v_trunc_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_rndne_f16 v1, v2
+// VI: v_rndne_f16_e32 v1, v2 ; encoding: [0x02,0x8f,0x02,0x7e]
+v_rndne_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_fract_f16 v1, v2
+// VI: v_fract_f16_e32 v1, v2 ; encoding: [0x02,0x91,0x02,0x7e]
+v_fract_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_sin_f16 v1, v2
+// VI: v_sin_f16_e32 v1, v2 ; encoding: [0x02,0x93,0x02,0x7e]
+v_sin_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_cos_f16 v1, v2
+// VI: v_cos_f16_e32 v1, v2 ; encoding: [0x02,0x95,0x02,0x7e]
+v_cos_f16 v1, v2
diff --git a/test/MC/R600/vop2-err.s b/test/MC/R600/vop2-err.s
new file mode 100644
index 000000000000..a1131000a909
--- /dev/null
+++ b/test/MC/R600/vop2-err.s
@@ -0,0 +1,35 @@
+// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s
+
+//===----------------------------------------------------------------------===//
+// Generic checks
+//===----------------------------------------------------------------------===//
+
+v_mul_i32_i24 v1, v2, 100
+// CHECK: error: invalid operand for instruction
+
+//===----------------------------------------------------------------------===//
+// _e32 checks
+//===----------------------------------------------------------------------===//
+
+// Immediate src1
+v_mul_i32_i24_e32 v1, v2, 100
+// CHECK: error: invalid operand for instruction
+
+// sgpr src1
+v_mul_i32_i24_e32 v1, v2, s3
+// CHECK: error: invalid operand for instruction
+
+//===----------------------------------------------------------------------===//
+// _e64 checks
+//===----------------------------------------------------------------------===//
+
+// Immediate src0
+v_mul_i32_i24_e64 v1, 100, v3
+// CHECK: error: invalid operand for instruction
+
+// Immediate src1
+v_mul_i32_i24_e64 v1, v2, 100
+// CHECK: error: invalid operand for instruction
+
+// TODO: Constant bus restrictions
diff --git a/test/MC/R600/vop2.s b/test/MC/R600/vop2.s
new file mode 100644
index 000000000000..a1f3b8d89365
--- /dev/null
+++ b/test/MC/R600/vop2.s
@@ -0,0 +1,421 @@
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI
+
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s -check-prefix=NOVI
+
+//===----------------------------------------------------------------------===//
+// Generic Checks for floating-point instructions (These have modifiers).
+//===----------------------------------------------------------------------===//
+
+// TODO: 64-bit encoding of instructions with modifiers
+
+// _e32 suffix
+// SICI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
+v_add_f32_e32 v1, v2, v3
+
+// src0 inline immediate
+// SICI: v_add_f32_e32 v1, 1.0, v3 ; encoding: [0xf2,0x06,0x02,0x06]
+v_add_f32 v1, 1.0, v3
+
+// src0 negative inline immediate
+// SICI: v_add_f32_e32 v1, -1.0, v3 ; encoding: [0xf3,0x06,0x02,0x06]
+v_add_f32 v1, -1.0, v3
+
+// src0 literal
+// SICI: v_add_f32_e32 v1, 0x42c80000, v3 ; encoding: [0xff,0x06,0x02,0x06,0x00,0x00,0xc8,0x42]
+v_add_f32 v1, 100.0, v3
+
+// src0 negative literal
+// SICI: v_add_f32_e32 v1, 0xc2c80000, v3 ; encoding: [0xff,0x06,0x02,0x06,0x00,0x00,0xc8,0xc2]
+v_add_f32 v1, -100.0, v3
+
+//===----------------------------------------------------------------------===//
+// Generic Checks for integer instructions (These don't have modifiers).
+//===----------------------------------------------------------------------===//
+
+// _e32 suffix
+// SICI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
+v_mul_i32_i24_e32 v1, v2, v3
+
+// _e64 suffix
+// SICI: v_mul_i32_i24_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x02,0x00]
+v_mul_i32_i24_e64 v1, v2, v3
+
+// src0 inline
+// SICI: v_mul_i32_i24_e32 v1, 3, v3 ; encoding: [0x83,0x06,0x02,0x12]
+v_mul_i32_i24 v1, 3, v3
+
+// src0 negative inline
+// SICI: v_mul_i32_i24_e32 v1, -3, v3 ; encoding: [0xc3,0x06,0x02,0x12]
+v_mul_i32_i24 v1, -3, v3
+
+// src1 inline
+// SICI: v_mul_i32_i24_e64 v1, v2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x01,0x00]
+v_mul_i32_i24 v1, v2, 3
+
+// src1 negative inline
+// SICI: v_mul_i32_i24_e64 v1, v2, -3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x87,0x01,0x00]
+v_mul_i32_i24 v1, v2, -3
+
+// src0 literal
+// SICI: v_mul_i32_i24_e32 v1, 0x64, v3 ; encoding: [0xff,0x06,0x02,0x12,0x64,0x00,0x00,0x00]
+v_mul_i32_i24 v1, 100, v3
+
+// src1 negative literal
+// SICI: v_mul_i32_i24_e32 v1, 0xffffff9c, v3 ; encoding: [0xff,0x06,0x02,0x12,0x9c,0xff,0xff,0xff]
+v_mul_i32_i24 v1, -100, v3
+
+//===----------------------------------------------------------------------===//
+// Checks for legal operands
+//===----------------------------------------------------------------------===//
+
+// src0 sgpr
+// SICI: v_mul_i32_i24_e32 v1, s2, v3 ; encoding: [0x02,0x06,0x02,0x12]
+v_mul_i32_i24 v1, s2, v3
+
+// src1 sgpr
+// SICI: v_mul_i32_i24_e64 v1, v2, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x00,0x00]
+v_mul_i32_i24 v1, v2, s3
+
+// src0, src1 same sgpr
+// SICI: v_mul_i32_i24_e64 v1, s2, s2 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x04,0x00,0x00]
+v_mul_i32_i24 v1, s2, s2
+
+// src0 sgpr, src1 inline
+// SICI: v_mul_i32_i24_e64 v1, s2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x06,0x01,0x00]
+v_mul_i32_i24 v1, s2, 3
+
+// src0 inline src1 sgpr
+// SICI: v_mul_i32_i24_e64 v1, 3, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x83,0x06,0x00,0x00]
+v_mul_i32_i24 v1, 3, s3
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+// GCN: v_cndmask_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x00]
+v_cndmask_b32 v1, v2, v3
+
+// SICI: v_readlane_b32 s1, v2, s3 ; encoding: [0x02,0x07,0x02,0x02]
+// VI:   v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
+v_readlane_b32 s1, v2, s3
+
+// SICI: v_writelane_b32 v1, s2, s3 ; encoding: [0x02,0x06,0x02,0x04]
+// VI:   v_writelane_b32 v1, s2, s3 ; encoding: [0x01,0x00,0x8a,0xd2,0x02,0x06,0x00,0x00]
+v_writelane_b32 v1, s2, s3
+
+// SICI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
+// VI:   v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x02]
+v_add_f32 v1, v2, v3
+
+// SICI: v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x08]
+// VI:   v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x04]
+v_sub_f32 v1, v2, v3
+
+// SICI: v_subrev_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a]
+// VI:   v_subrev_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
+v_subrev_f32 v1, v2, v3
+
+// SICI: v_mac_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_mac_legacy_f32 v1, v2, v3
+v_mac_legacy_f32 v1, v2, v3
+
+// SICI: v_mul_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e]
+// VI:   v_mul_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x08]
+v_mul_legacy_f32_e32 v1, v2, v3
+
+// SICI: v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10]
+// VI:   v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a]
+v_mul_f32 v1, v2, v3
+
+// SICI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
+// VI:   v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
+v_mul_i32_i24 v1, v2, v3
+
+// SICI: v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14]
+// VI:   v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e]
+v_mul_hi_i32_i24 v1, v2, v3
+
+// SICI: v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16]
+// VI:   v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10]
+v_mul_u32_u24 v1, v2, v3
+
+// SICI: v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18]
+// VI:   v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
+v_mul_hi_u32_u24 v1, v2, v3
+
+// SICI: v_min_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_min_legacy_f32_e32 v1, v2, v3
+v_min_legacy_f32_e32 v1, v2, v3
+
+// SICI: v_max_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1c]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_max_legacy_f32 v1, v2, v3
+v_max_legacy_f32 v1, v2, v3
+
+// SICI: v_min_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1e]
+// VI:   v_min_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14]
+v_min_f32_e32 v1, v2, v3
+
+// SICI: v_max_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x20]
+// VI:   v_max_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16]
+v_max_f32 v1, v2 v3
+
+// SICI: v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22]
+// VI:   v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18]
+v_min_i32 v1, v2, v3
+
+// SICI: v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24]
+// VI:   v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a]
+v_max_i32 v1, v2, v3
+
+// SICI: v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26]
+// VI:   v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1c]
+v_min_u32 v1, v2, v3
+
+// SICI: v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28]
+// VI:   v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1e]
+v_max_u32 v1, v2, v3
+
+// SICI: v_lshr_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_lshr_b32 v1, v2, v3
+v_lshr_b32 v1, v2, v3
+
+// SICI: v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c]
+// VI:   v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x20]
+v_lshrrev_b32 v1, v2, v3
+
+// SICI: v_ashr_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2e]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_ashr_i32 v1, v2, v3
+v_ashr_i32 v1, v2, v3
+
+// SICI: v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x30]
+// VI:   v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22]
+v_ashrrev_i32 v1, v2, v3
+
+// SICI: v_lshl_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x32]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_lshl_b32_e32 v1, v2, v3
+v_lshl_b32_e32 v1, v2, v3
+
+// SICI: v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x34]
+// VI:   v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24]
+v_lshlrev_b32 v1, v2, v3
+
+// SICI: v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x36]
+// VI:   v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26]
+v_and_b32 v1, v2, v3
+
+// SICI: v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x38]
+// VI:   v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28]
+v_or_b32 v1, v2, v3
+
+// SICI: v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3a]
+// VI:   v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a]
+v_xor_b32 v1, v2, v3
+
+// SICI: v_bfm_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3c]
+// VI:   v_bfm_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x93,0xd2,0x02,0x07,0x02,0x00]
+v_bfm_b32 v1, v2, v3
+
+// SICI: v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e]
+// VI:   v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c]
+v_mac_f32 v1, v2, v3
+
+// SICI: v_madmk_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x40,0x00,0x00,0x80,0x42]
+// VI:   v_madmk_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x2e,0x00,0x00,0x80,0x42]
+v_madmk_f32 v1, v2, v3, 64.0
+
+// SICI: v_madak_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x42,0x00,0x00,0x80,0x42]
+// VI:  v_madak_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x30,0x00,0x00,0x80,0x42]
+v_madak_f32 v1, v2, v3, 64.0
+
+// SICI: v_bcnt_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44]
+// VI:   v_bcnt_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8b,0xd2,0x02,0x07,0x02,0x00]
+v_bcnt_u32_b32 v1, v2, v3
+
+// SICI: v_mbcnt_lo_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46]
+// VI:   v_mbcnt_lo_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8c,0xd2,0x02,0x07,0x02,0x00]
+v_mbcnt_lo_u32_b32 v1, v2, v3
+
+// SICI: v_mbcnt_hi_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x48]
+// VI:   v_mbcnt_hi_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8d,0xd2,0x02,0x07,0x02,0x00]
+v_mbcnt_hi_u32_b32 v1, v2, v3
+
+// SICI: v_add_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4a]
+// VI:   v_add_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x32]
+v_add_i32 v1, v2, v3
+
+// SICI: v_add_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4a]
+// VI:   v_add_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x32]
+v_add_u32 v1, v2, v3
+
+// SICI: v_sub_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c]
+// VI:   v_sub_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x34]
+v_sub_i32 v1, v2, v3
+
+// SICI: v_sub_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c]
+// VI:   v_sub_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x34]
+v_sub_u32 v1, v2, v3
+
+// SICI: v_subrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e]
+// VI:   v_subrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x36]
+v_subrev_i32 v1, v2, v3
+
+// SICI: v_subrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e]
+// VI:   v_subrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x36]
+v_subrev_u32 v1, v2, v3
+
+// SICI: v_addc_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50]
+// VI:   v_addc_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x38]
+v_addc_u32 v1, v2, v3
+
+// SICI: v_subb_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x52]
+// VI:   v_subb_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3a]
+v_subb_u32 v1, v2, v3
+
+// SICI: v_subbrev_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54]
+// VI:   v_subbrev_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3c]
+v_subbrev_u32 v1, v2, v3
+
+// SICI: v_ldexp_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
+// VI:   v_ldexp_f32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x88,0xd2,0x02,0x07,0x02,0x00]
+v_ldexp_f32 v1, v2, v3
+
+// SICI: v_cvt_pkaccum_u8_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
+// VI:   v_cvt_pkaccum_u8_f32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0xf0,0xd1,0x02,0x07,0x02,0x00]
+v_cvt_pkaccum_u8_f32 v1, v2, v3
+
+// SICI: v_cvt_pknorm_i16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
+// VI:   v_cvt_pknorm_i16_f32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x94,0xd2,0x02,0x07,0x02,0x00]
+v_cvt_pknorm_i16_f32 v1, v2, v3
+
+// SICI: v_cvt_pknorm_u16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c]
+// VI:   v_cvt_pknorm_u16_f32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x95,0xd2,0x02,0x07,0x02,0x00]
+v_cvt_pknorm_u16_f32 v1, v2, v3
+
+// SICI: v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5e]
+// VI:   v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x96,0xd2,0x02,0x07,0x02,0x00]
+v_cvt_pkrtz_f16_f32 v1, v2, v3
+
+// SICI: v_cvt_pk_u16_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x60]
+// VI:   v_cvt_pk_u16_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x97,0xd2,0x02,0x07,0x02,0x00]
+v_cvt_pk_u16_u32 v1, v2, v3
+
+// SICI: v_cvt_pk_i16_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x62]
+// VI:   v_cvt_pk_i16_i32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x98,0xd2,0x02,0x07,0x02,0x00]
+v_cvt_pk_i16_i32 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_add_f16 v1, v2, v3
+// VI:     v_add_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e]
+v_add_f16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_sub_f16 v1, v2, v3
+// VI:     v_sub_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x40]
+v_sub_f16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_subrev_f16 v1, v2, v3
+// VI:     v_subrev_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x42]
+v_subrev_f16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_mul_f16 v1, v2, v3
+// VI:     v_mul_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44]
+v_mul_f16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_mac_f16 v1, v2, v3
+// VI:     v_mac_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46]
+v_mac_f16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_madmk_f16 v1, v2, v3, 64.0
+// VI:     v_madmk_f16_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x48,0x00,0x00,0x80,0x42]
+v_madmk_f16 v1, v2, v3, 64.0
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_madak_f16 v1, v2, v3, 64.0
+// VI:     v_madak_f16_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x4a,0x00,0x00,0x80,0x42]
+v_madak_f16 v1, v2, v3, 64.0
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_add_u16 v1, v2, v3
+// VI:     v_add_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c]
+v_add_u16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_sub_u16 v1, v2, v3
+// VI:     v_sub_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e]
+v_sub_u16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_subrev_u16 v1, v2, v3
+// VI:     v_subrev_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50]
+v_subrev_u16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_mul_lo_u16 v1, v2, v3
+// VI:     v_mul_lo_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x52]
+v_mul_lo_u16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_lshlrev_b16 v1, v2, v3
+// VI:     v_lshlrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54]
+v_lshlrev_b16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_lshrrev_b16 v1, v2, v3
+// VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
+v_lshrrev_b16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_ashrrev_b16 v1, v2, v3
+// VI:     v_ashrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
+v_ashrrev_b16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_max_f16 v1, v2, v3
+// VI:     v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
+v_max_f16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_min_f16 v1, v2, v3
+// VI:     v_min_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c]
+v_min_f16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_max_u16 v1, v2, v3
+// VI:     v_max_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5e]
+v_max_u16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_max_i16 v1, v2, v3
+// VI:     v_max_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x60]
+v_max_i16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_min_u16 v1, v2, v3
+// VI:     v_min_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x62]
+v_min_u16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_min_i16 v1, v2, v3
+// VI:     v_min_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x64]
+v_min_i16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_ldexp_f16 v1, v2, v3
+// VI:     v_ldexp_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x66]
+v_ldexp_f16 v1, v2, v3
diff --git a/test/MC/R600/vop3-errs.s b/test/MC/R600/vop3-errs.s
new file mode 100644
index 000000000000..b57fe6d5314b
--- /dev/null
+++ b/test/MC/R600/vop3-errs.s
@@ -0,0 +1,5 @@
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s
+
+v_add_f32_e64 v0, v1
+// CHECK: error: too few operands for instruction
diff --git a/test/MC/R600/vop3.s b/test/MC/R600/vop3.s
new file mode 100644
index 000000000000..205623359748
--- /dev/null
+++ b/test/MC/R600/vop3.s
@@ -0,0 +1,149 @@
+// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s
+
+//===----------------------------------------------------------------------===//
+// VOPC Instructions
+//===----------------------------------------------------------------------===//
+
+// Test forced e64 encoding
+
+v_cmp_lt_f32_e64 s[2:3], v4, -v6
+// CHECK: v_cmp_lt_f32_e64 s[2:3], v4, -v6 ; encoding: [0x02,0x00,0x02,0xd0,0x04,0x0d,0x02,0x40]
+
+//
+// Modifier tests:
+//
+
+v_cmp_lt_f32 s[2:3] -v4, v6
+// CHECK: v_cmp_lt_f32_e64 s[2:3], -v4, v6 ; encoding: [0x02,0x00,0x02,0xd0,0x04,0x0d,0x02,0x20] 
+
+v_cmp_lt_f32 s[2:3]  v4, -v6
+// CHECK: v_cmp_lt_f32_e64 s[2:3], v4, -v6 ; encoding: [0x02,0x00,0x02,0xd0,0x04,0x0d,0x02,0x40]
+
+v_cmp_lt_f32 s[2:3] -v4, -v6
+// CHECK: v_cmp_lt_f32_e64 s[2:3], -v4, -v6 ; encoding: [0x02,0x00,0x02,0xd0,0x04,0x0d,0x02,0x60]
+
+v_cmp_lt_f32 s[2:3] |v4|, v6
+// CHECK: v_cmp_lt_f32_e64 s[2:3], |v4|, v6 ; encoding: [0x02,0x01,0x02,0xd0,0x04,0x0d,0x02,0x00]
+
+v_cmp_lt_f32 s[2:3] v4, |v6|
+// CHECK: v_cmp_lt_f32_e64 s[2:3], v4, |v6| ; encoding: [0x02,0x02,0x02,0xd0,0x04,0x0d,0x02,0x00]
+
+v_cmp_lt_f32 s[2:3] |v4|, |v6|
+// CHECK: v_cmp_lt_f32_e64 s[2:3], |v4|, |v6| ; encoding: [0x02,0x03,0x02,0xd0,0x04,0x0d,0x02,0x00]
+
+v_cmp_lt_f32 s[2:3] -|v4|, v6
+// CHECK: v_cmp_lt_f32_e64 s[2:3], -|v4|, v6 ; encoding: [0x02,0x01,0x02,0xd0,0x04,0x0d,0x02,0x20]
+
+v_cmp_lt_f32 s[2:3] v4, -|v6|
+// CHECK: v_cmp_lt_f32_e64 s[2:3], v4, -|v6| ; encoding: [0x02,0x02,0x02,0xd0,0x04,0x0d,0x02,0x40]
+
+v_cmp_lt_f32 s[2:3] -|v4|, -|v6|
+// CHECK: v_cmp_lt_f32_e64 s[2:3], -|v4|, -|v6| ; encoding: [0x02,0x03,0x02,0xd0,0x04,0x0d,0x02,0x60]
+
+//
+// Instruction tests:
+//
+
+v_cmp_f_f32 s[2:3], v4, v6
+// CHECK: v_cmp_f_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x00,0xd0,0x04,0x0d,0x02,0x00]
+
+v_cmp_lt_f32 s[2:3], v4, v6
+// CHECK: v_cmp_lt_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x02,0xd0,0x04,0x0d,0x02,0x00]
+
+v_cmp_eq_f32 s[2:3], v4, v6
+// CHECK: v_cmp_eq_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x04,0xd0,0x04,0x0d,0x02,0x00]
+
+v_cmp_le_f32 s[2:3], v4, v6
+// CHECK: v_cmp_le_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x06,0xd0,0x04,0x0d,0x02,0x00]
+
+v_cmp_gt_f32 s[2:3], v4, v6
+// CHECK: v_cmp_gt_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x08,0xd0,0x04,0x0d,0x02,0x00]
+
+v_cmp_lg_f32 s[2:3], v4, v6
+// CHECK: v_cmp_lg_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x0a,0xd0,0x04,0x0d,0x02,0x00]
+
+v_cmp_ge_f32 s[2:3], v4, v6
+// CHECK: v_cmp_ge_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x0c,0xd0,0x04,0x0d,0x02,0x00]
+
+// TODO: Finish VOPC
+
+//===----------------------------------------------------------------------===//
+// VOP1 Instructions
+//===----------------------------------------------------------------------===//
+
+//
+// Modifier tests:
+// 
+
+v_fract_f32 v1, -v2
+// CHECK: v_fract_f32_e64 v1, -v2 ; encoding: [0x01,0x00,0x40,0xd3,0x02,0x01,0x00,0x20]
+
+v_fract_f32 v1, |v2|
+// CHECK: v_fract_f32_e64 v1, |v2| ; encoding: [0x01,0x01,0x40,0xd3,0x02,0x01,0x00,0x00]
+
+v_fract_f32 v1, -|v2|
+// CHECK: v_fract_f32_e64 v1, -|v2| ; encoding: [0x01,0x01,0x40,0xd3,0x02,0x01,0x00,0x20]
+
+v_fract_f32 v1, v2 clamp
+// CHECK: v_fract_f32_e64 v1, v2 clamp ; encoding: [0x01,0x08,0x40,0xd3,0x02,0x01,0x00,0x00]
+
+v_fract_f32 v1, v2 mul:2
+// CHECK: v_fract_f32_e64 v1, v2 mul:2 ; encoding: [0x01,0x00,0x40,0xd3,0x02,0x01,0x00,0x08]
+
+v_fract_f32 v1, v2, div:2 clamp
+// CHECK: v_fract_f32_e64 v1, v2 clamp div:2 ; encoding: [0x01,0x08,0x40,0xd3,0x02,0x01,0x00,0x18]
+
+// TODO: Finish VOP1
+
+///===---------------------------------------------------------------------===//
+// VOP2 Instructions
+///===---------------------------------------------------------------------===//
+
+// Test forced e64 encoding with e32 operands
+
+v_ldexp_f32_e64 v1, v3, v5
+// CHECK: v_ldexp_f32_e64 v1, v3, v5 ; encoding: [0x01,0x00,0x56,0xd2,0x03,0x0b,0x02,0x00]
+
+
+// TODO: Modifier tests
+
+v_cndmask_b32 v1, v3, v5, s[4:5]
+// CHECK: v_cndmask_b32_e64 v1, v3, v5, s[4:5] ; encoding: [0x01,0x00,0x00,0xd2,0x03,0x0b,0x12,0x00]
+
+//TODO: readlane, writelane
+
+v_add_f32 v1, v3, s5
+// CHECK: v_add_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x06,0xd2,0x03,0x0b,0x00,0x00]
+
+v_sub_f32 v1, v3, s5
+// CHECK: v_sub_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x08,0xd2,0x03,0x0b,0x00,0x00]
+
+v_subrev_f32 v1, v3, s5
+// CHECK: v_subrev_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x0a,0xd2,0x03,0x0b,0x00,0x00]
+
+v_mac_legacy_f32 v1, v3, s5
+// CHECK: v_mac_legacy_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x0c,0xd2,0x03,0x0b,0x00,0x00]
+
+v_mul_legacy_f32 v1, v3, s5
+// CHECK: v_mul_legacy_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x0e,0xd2,0x03,0x0b,0x00,0x00]
+
+v_mul_f32 v1, v3, s5
+// CHECK: v_mul_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x10,0xd2,0x03,0x0b,0x00,0x00]
+
+v_mul_i32_i24 v1, v3, s5
+// CHECK: v_mul_i32_i24_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x12,0xd2,0x03,0x0b,0x00,0x00]
+
+///===---------------------------------------------------------------------===//
+// VOP3 Instructions
+///===---------------------------------------------------------------------===//
+
+// TODO: Modifier tests
+
+v_mad_legacy_f32 v2, v4, v6, v8
+// CHECK: v_mad_legacy_f32 v2, v4, v6, v8 ; encoding: [0x02,0x00,0x80,0xd2,0x04,0x0d,0x22,0x04]
+
+
+
+
+
diff --git a/test/MC/R600/vopc.s b/test/MC/R600/vopc.s
new file mode 100644
index 000000000000..f44919a4f1e0
--- /dev/null
+++ b/test/MC/R600/vopc.s
@@ -0,0 +1,40 @@
+// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s
+
+//===----------------------------------------------------------------------===//
+// Generic Checks
+//===----------------------------------------------------------------------===//
+
+// src0 sgpr
+v_cmp_lt_f32 vcc, s2, v4
+// CHECK: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x02,0x7c]
+
+// src0 inline immediate
+v_cmp_lt_f32 vcc, 0, v4
+// CHECK: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x02,0x7c]
+
+// src0 literal
+v_cmp_lt_f32 vcc, 10.0, v4
+// CHECK: v_cmp_lt_f32_e32 vcc, 0x41200000, v4 ; encoding: [0xff,0x08,0x02,0x7c,0x00,0x00,0x20,0x41]
+
+// src0, src1 max vgpr
+v_cmp_lt_f32 vcc, v255, v255
+// CHECK: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x03,0x7c]
+
+// force 32-bit encoding
+v_cmp_lt_f32_e32 vcc, v2, v4
+// CHECK: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c]
+
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+v_cmp_f_f32 vcc, v2, v4
+// CHECK: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x00,0x7c]
+
+v_cmp_lt_f32 vcc, v2, v4
+// CHECK: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c]
+
+// TODO: Add tests for the rest of the instructions.
+
diff --git a/test/MC/Sparc/sparc-assembly-exprs.s b/test/MC/Sparc/sparc-assembly-exprs.s
new file mode 100644
index 000000000000..7fdc5a50345f
--- /dev/null
+++ b/test/MC/Sparc/sparc-assembly-exprs.s
@@ -0,0 +1,6 @@
+! RUN: llvm-mc %s -arch=sparc   -show-encoding | FileCheck %s
+
+        ! CHECK: mov 1033, %o1  ! encoding: [0x92,0x10,0x24,0x09]
+        mov      (0x400|9), %o1
+        ! CHECK: mov 60, %o2    ! encoding: [0x94,0x10,0x20,0x3c]
+        mov      (12+3<<2), %o2
diff --git a/test/MC/Sparc/sparc-atomic-instructions.s b/test/MC/Sparc/sparc-atomic-instructions.s
index 5c46067ea3bc..17f97d4b5354 100644
--- a/test/MC/Sparc/sparc-atomic-instructions.s
+++ b/test/MC/Sparc/sparc-atomic-instructions.s
@@ -1,7 +1,5 @@
 ! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
-
-        ! CHECK: membar 15             ! encoding: [0x81,0x43,0xe0,0x0f]
-        membar 15
+! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
 
         ! CHECK: stbar                 ! encoding: [0x81,0x43,0xc0,0x00]
         stbar
@@ -12,8 +10,5 @@
         ! CHECK: swap [%i0+32], %o2    ! encoding: [0xd4,0x7e,0x20,0x20]
         swap [%i0+32], %o2
 
-        ! CHECK: cas [%i0], %l6, %o2   ! encoding: [0xd5,0xe6,0x10,0x16]
-        cas [%i0], %l6, %o2
-
-        ! CHECK: casx [%i0], %l6, %o2  ! encoding: [0xd5,0xf6,0x10,0x16]
-        casx [%i0], %l6, %o2
+        ! CHECK: swapa [%i0+%l6] 131, %o2   ! encoding: [0xd4,0xfe,0x10,0x76]
+        swapa [%i0+%l6] 131, %o2
diff --git a/test/MC/Sparc/sparc-ctrl-instructions.s b/test/MC/Sparc/sparc-ctrl-instructions.s
index cf92e7045d43..a2608fdba608 100644
--- a/test/MC/Sparc/sparc-ctrl-instructions.s
+++ b/test/MC/Sparc/sparc-ctrl-instructions.s
@@ -11,7 +11,7 @@
         ! CHECK: call %o1+8   ! encoding: [0x9f,0xc2,0x60,0x08]
         call %o1 + 8
 
-        ! CHECK: call %g1     ! encoding: [0x9f,0xc0,0x60,0x00]
+        ! CHECK: call %g1     ! encoding: [0x9f,0xc0,0x40,0x00]
         call %g1
 
         ! CHECK: call %g1+%lo(sym)   ! encoding: [0x9f,0xc0,0b011000AA,A]
@@ -24,7 +24,7 @@
         ! CHECK: jmp %o1+8    ! encoding: [0x81,0xc2,0x60,0x08]
         jmp %o1 + 8
 
-        ! CHECK: jmp %g1      ! encoding: [0x81,0xc0,0x60,0x00]
+        ! CHECK: jmp %g1      ! encoding: [0x81,0xc0,0x40,0x00]
         jmp %g1
 
         ! CHECK: jmp %g1+%lo(sym)   ! encoding: [0x81,0xc0,0b011000AA,A]
@@ -37,7 +37,7 @@
         ! CHECK: jmpl %o1+8, %g2    ! encoding: [0x85,0xc2,0x60,0x08]
         jmpl %o1 + 8, %g2
 
-        ! CHECK: jmpl %g1, %g2      ! encoding: [0x85,0xc0,0x60,0x00]
+        ! CHECK: jmpl %g1, %g2      ! encoding: [0x85,0xc0,0x40,0x00]
         jmpl %g1, %g2
 
         ! CHECK: jmpl %g1+%lo(sym), %g2   ! encoding: [0x85,0xc0,0b011000AA,A]
@@ -52,10 +52,18 @@
         ! CHECK-NEXT:         ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
         bne .BB0
 
+        ! CHECK: bne .BB0     ! encoding: [0x12,0b10AAAAAA,A,A]
+        ! CHECK-NEXT:         ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
+        bnz .BB0
+
         ! CHECK: be .BB0      ! encoding: [0x02,0b10AAAAAA,A,A]
         ! CHECK-NEXT:         ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
         be .BB0
 
+        ! CHECK: be .BB0      ! encoding: [0x02,0b10AAAAAA,A,A]
+        ! CHECK-NEXT:         ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
+        bz .BB0
+
         ! CHECK: bg .BB0      ! encoding: [0x14,0b10AAAAAA,A,A]
         ! CHECK-NEXT:         ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
         bg .BB0
@@ -84,10 +92,18 @@
         ! CHECK-NEXT:         ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
         bcc .BB0
 
+        ! CHECK: bcc .BB0      ! encoding: [0x1a,0b10AAAAAA,A,A]
+        ! CHECK-NEXT:         ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
+        bgeu .BB0
+
         ! CHECK: bcs .BB0      ! encoding: [0x0a,0b10AAAAAA,A,A]
         ! CHECK-NEXT:         ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
         bcs .BB0
 
+        ! CHECK: bcs .BB0      ! encoding: [0x0a,0b10AAAAAA,A,A]
+        ! CHECK-NEXT:         ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
+        blu .BB0
+
         ! CHECK: bpos .BB0      ! encoding: [0x1c,0b10AAAAAA,A,A]
         ! CHECK-NEXT:         ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
         bpos .BB0
@@ -131,10 +147,18 @@
         ! CHECK-NEXT:                                        !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
         fbne .BB0
 
+        ! CHECK:             fbne .BB0                       ! encoding: [0x03,0b10AAAAAA,A,A]
+        ! CHECK-NEXT:                                        !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
+        fbnz .BB0
+
         ! CHECK:             fbe .BB0                        ! encoding: [0x13,0b10AAAAAA,A,A]
         ! CHECK-NEXT:                                        !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
         fbe .BB0
 
+        ! CHECK:             fbe .BB0                        ! encoding: [0x13,0b10AAAAAA,A,A]
+        ! CHECK-NEXT:                                        !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
+        fbz .BB0
+
         ! CHECK:             fbue .BB0                       ! encoding: [0x15,0b10AAAAAA,A,A]
         ! CHECK-NEXT:                                        !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
         fbue .BB0
diff --git a/test/MC/Sparc/sparc-little-endian.s b/test/MC/Sparc/sparc-little-endian.s
new file mode 100644
index 000000000000..18ced35c8883
--- /dev/null
+++ b/test/MC/Sparc/sparc-little-endian.s
@@ -0,0 +1,18 @@
+! RUN: llvm-mc %s -arch=sparcel -show-encoding | FileCheck %s
+! RUN: llvm-mc -arch=sparcel -filetype=obj < %s | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-OBJ
+
+        ! CHECK-OBJ: .text:
+        .BB0:
+
+        ! Ensure instructions are emitted in reversed byte order:
+
+        ! CHECK: call %g1     ! encoding: [0x00,0x40,0xc0,0x9f]
+        ! CHECK-OBJ: 0: 00 40 c0 9f  call %g1
+        call %g1
+
+        ! ...and that fixups are applied to the correct bytes.
+
+        ! CHECK: ba .BB0      ! encoding: [A,A,0b10AAAAAA,0x10]
+        ! CHECK-NEXT:         ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
+        ! CHECK-OBJ: 4: ff ff bf 10  ba 4194303
+        ba .BB0
diff --git a/test/MC/Sparc/sparc-mem-instructions.s b/test/MC/Sparc/sparc-mem-instructions.s
index e8eb5933c3a1..ba4c0f2d1048 100644
--- a/test/MC/Sparc/sparc-mem-instructions.s
+++ b/test/MC/Sparc/sparc-mem-instructions.s
@@ -5,54 +5,70 @@
         ldsb [%i0 + %l6], %o2
         ! CHECK: ldsb [%i0+32], %o2   ! encoding: [0xd4,0x4e,0x20,0x20]
         ldsb [%i0 + 32], %o2
-        ! CHECK: ldsb [%g1], %o4      ! encoding: [0xd8,0x48,0x60,0x00]
+        ! CHECK: ldsb [%g1], %o4      ! encoding: [0xd8,0x48,0x40,0x00]
         ldsb [%g1], %o4
+        ! CHECK: ldsba [%i0+%l6] 131, %o2  ! encoding: [0xd4,0xce,0x10,0x76]
+        ldsba [%i0 + %l6] 131, %o2
 
         ! CHECK: ldsh [%i0+%l6], %o2  ! encoding: [0xd4,0x56,0x00,0x16]
         ldsh [%i0 + %l6], %o2
         ! CHECK: ldsh [%i0+32], %o2   ! encoding: [0xd4,0x56,0x20,0x20]
         ldsh [%i0 + 32], %o2
-        ! CHECK: ldsh [%g1], %o4      ! encoding: [0xd8,0x50,0x60,0x00]
+        ! CHECK: ldsh [%g1], %o4      ! encoding: [0xd8,0x50,0x40,0x00]
         ldsh [%g1], %o4
+        ! CHECK: ldsha [%i0+%l6] 131, %o2 ! encoding: [0xd4,0xd6,0x10,0x76]
+        ldsha [%i0 + %l6] 131, %o2
 
         ! CHECK: ldub [%i0+%l6], %o2  ! encoding: [0xd4,0x0e,0x00,0x16]
         ldub [%i0 + %l6], %o2
         ! CHECK: ldub [%i0+32], %o2   ! encoding: [0xd4,0x0e,0x20,0x20]
         ldub [%i0 + 32], %o2
-        ! CHECK: ldub [%g1], %o2      ! encoding: [0xd4,0x08,0x60,0x00]
+        ! CHECK: ldub [%g1], %o2      ! encoding: [0xd4,0x08,0x40,0x00]
         ldub [%g1], %o2
+        ! CHECK: lduba [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x8e,0x10,0x76]
+        lduba [%i0 + %l6] 131, %o2
 
         ! CHECK: lduh [%i0+%l6], %o2  ! encoding: [0xd4,0x16,0x00,0x16]
         lduh [%i0 + %l6], %o2
         ! CHECK: lduh [%i0+32], %o2   ! encoding: [0xd4,0x16,0x20,0x20]
         lduh [%i0 + 32], %o2
-        ! CHECK: lduh [%g1], %o2      ! encoding: [0xd4,0x10,0x60,0x00]
+        ! CHECK: lduh [%g1], %o2      ! encoding: [0xd4,0x10,0x40,0x00]
         lduh [%g1], %o2
+        ! CHECK: lduha [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x96,0x10,0x76]
+        lduha [%i0 + %l6] 131, %o2
 
         ! CHECK: ld [%i0+%l6], %o2    ! encoding: [0xd4,0x06,0x00,0x16]
         ld [%i0 + %l6], %o2
         ! CHECK: ld [%i0+32], %o2     ! encoding: [0xd4,0x06,0x20,0x20]
         ld [%i0 + 32], %o2
-        ! CHECK: ld [%g1], %o2        ! encoding: [0xd4,0x00,0x60,0x00]
+        ! CHECK: ld [%g1], %o2        ! encoding: [0xd4,0x00,0x40,0x00]
         ld [%g1], %o2
+        ! CHECK: lda [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x86,0x10,0x76]
+        lda [%i0 + %l6] 131, %o2
 
         ! CHECK: stb %o2, [%i0+%l6]   ! encoding: [0xd4,0x2e,0x00,0x16]
         stb %o2, [%i0 + %l6]
         ! CHECK: stb %o2, [%i0+32]    ! encoding: [0xd4,0x2e,0x20,0x20]
         stb %o2, [%i0 + 32]
-        ! CHECK: stb %o2, [%g1]       ! encoding: [0xd4,0x28,0x60,0x00]
+        ! CHECK: stb %o2, [%g1]       ! encoding: [0xd4,0x28,0x40,0x00]
         stb %o2, [%g1]
+        ! CHECK: stba %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xae,0x10,0x76]
+        stba %o2, [%i0 + %l6] 131
 
         ! CHECK: sth %o2, [%i0+%l6]   ! encoding: [0xd4,0x36,0x00,0x16]
         sth %o2, [%i0 + %l6]
         ! CHECK: sth %o2, [%i0+32]    ! encoding: [0xd4,0x36,0x20,0x20]
         sth %o2, [%i0 + 32]
-        ! CHECK: sth %o2, [%g1]       ! encoding: [0xd4,0x30,0x60,0x00]
+        ! CHECK: sth %o2, [%g1]       ! encoding: [0xd4,0x30,0x40,0x00]
         sth %o2, [%g1]
+        ! CHECK: stha %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xb6,0x10,0x76]
+        stha %o2, [%i0 + %l6] 131
 
         ! CHECK: st %o2, [%i0+%l6]    ! encoding: [0xd4,0x26,0x00,0x16]
         st %o2, [%i0 + %l6]
         ! CHECK: st %o2, [%i0+32]     ! encoding: [0xd4,0x26,0x20,0x20]
         st %o2, [%i0 + 32]
-        ! CHECK: st %o2, [%g1]        ! encoding: [0xd4,0x20,0x60,0x00]
+        ! CHECK: st %o2, [%g1]        ! encoding: [0xd4,0x20,0x40,0x00]
         st %o2, [%g1]
+        ! CHECK: sta %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xa6,0x10,0x76]
+        sta %o2, [%i0 + %l6] 131
diff --git a/test/MC/Sparc/sparc-special-registers.s b/test/MC/Sparc/sparc-special-registers.s
new file mode 100644
index 000000000000..2cb57d720c4f
--- /dev/null
+++ b/test/MC/Sparc/sparc-special-registers.s
@@ -0,0 +1,35 @@
+! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
+
+        ! CHECK: rd %y, %i0            ! encoding: [0xb1,0x40,0x00,0x00]
+        rd %y, %i0
+
+        ! CHECK: rd %asr1, %i0         ! encoding: [0xb1,0x40,0x40,0x00]
+        rd %asr1, %i0
+
+        ! CHECK: wr %i0, 5, %y         ! encoding: [0x81,0x86,0x20,0x05]
+        wr %i0, 5, %y
+
+        ! CHECK: wr %i0, %i1, %asr15   ! encoding: [0x9f,0x86,0x00,0x19]
+        wr %i0, %i1, %asr15
+
+        ! CHECK: rd %asr15, %g0        ! encoding: [0x81,0x43,0xc0,0x00]
+        rd %asr15, %g0
+
+        ! CHECK: rd %psr, %i0          ! encoding: [0xb1,0x48,0x00,0x00]
+        rd %psr, %i0
+
+        ! CHECK: rd %wim, %i0          ! encoding: [0xb1,0x50,0x00,0x00]
+        rd %wim, %i0
+
+        ! CHECK: rd %tbr, %i0          ! encoding: [0xb1,0x58,0x00,0x00]
+        rd %tbr, %i0
+
+        ! CHECK: wr %i0, 5, %psr          ! encoding: [0x81,0x8e,0x20,0x05]
+        wr %i0, 5, %psr
+
+        ! CHECK: wr %i0, 5, %wim          ! encoding: [0x81,0x96,0x20,0x05]
+        wr %i0, 5, %wim
+
+        ! CHECK: wr %i0, 5, %tbr          ! encoding: [0x81,0x9e,0x20,0x05]
+        wr %i0, 5, %tbr
diff --git a/test/MC/Sparc/sparc-synthetic-instructions.s b/test/MC/Sparc/sparc-synthetic-instructions.s
new file mode 100644
index 000000000000..5b5a1a77db98
--- /dev/null
+++ b/test/MC/Sparc/sparc-synthetic-instructions.s
@@ -0,0 +1,17 @@
+! RUN: llvm-mc %s -arch=sparc   -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
+
+! Section A.3 Synthetic Instructions
+        ! CHECK: sethi %hi(40000), %g1            ! encoding: [0x03,0b00AAAAAA,A,A]
+        ! CHECK:                                  !   fixup A - offset: 0, value: %hi(40000), kind: fixup_sparc_hi22
+        ! CHECK: or %g1, %lo(40000), %g1          ! encoding: [0x82,0x10,0b011000AA,A]
+        ! CHECK:                                  !   fixup A - offset: 0, value: %lo(40000), kind: fixup_sparc_lo10
+        set 40000, %g1
+        ! CHECK: mov      %lo(1), %g1             ! encoding: [0x82,0x10,0b001000AA,A]
+        ! CHECK:                                  !   fixup A - offset: 0, value: %lo(1), kind: fixup_sparc_lo10
+        set 1, %g1
+
+        ! CHECK: sethi %hi(32768), %g1            ! encoding: [0x03,0b00AAAAAA,A,A]
+        ! CHECK:                                  !   fixup A - offset: 0, value: %hi(32768), kind: fixup_sparc_hi22
+        set 32768, %g1
+
diff --git a/test/MC/Sparc/sparcv9-atomic-instructions.s b/test/MC/Sparc/sparcv9-atomic-instructions.s
new file mode 100644
index 000000000000..40619a75548e
--- /dev/null
+++ b/test/MC/Sparc/sparcv9-atomic-instructions.s
@@ -0,0 +1,10 @@
+! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
+
+        ! CHECK: membar 15             ! encoding: [0x81,0x43,0xe0,0x0f]
+        membar 15
+
+        ! CHECK: cas [%i0], %l6, %o2   ! encoding: [0xd5,0xe6,0x10,0x16]
+        cas [%i0], %l6, %o2
+
+        ! CHECK: casx [%i0], %l6, %o2  ! encoding: [0xd5,0xf6,0x10,0x16]
+        casx [%i0], %l6, %o2
diff --git a/test/MC/SystemZ/fixups.s b/test/MC/SystemZ/fixups.s
new file mode 100644
index 000000000000..8354121a01e9
--- /dev/null
+++ b/test/MC/SystemZ/fixups.s
@@ -0,0 +1,119 @@
+
+# RUN: llvm-mc -triple s390x-unknown-unknown --show-encoding %s | FileCheck %s
+
+# RUN: llvm-mc -triple s390x-unknown-unknown -filetype=obj %s | \
+# RUN: llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
+
+# CHECK: larl %r14, target                      # encoding: [0xc0,0xe0,A,A,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: target+2, kind: FK_390_PC32DBL
+# CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_PC32DBL target 0x2
+	.align 16
+	larl %r14, target
+
+# CHECK: larl %r14, target@GOT                  # encoding: [0xc0,0xe0,A,A,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: target@GOT+2, kind: FK_390_PC32DBL
+# CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_GOTENT target 0x2
+	.align 16
+	larl %r14, target@got
+
+# CHECK: larl %r14, target@INDNTPOFF            # encoding: [0xc0,0xe0,A,A,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: target@INDNTPOFF+2, kind: FK_390_PC32DBL
+# CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_TLS_IEENT target 0x2
+	.align 16
+	larl %r14, target@indntpoff
+
+# CHECK: brasl %r14, target                     # encoding: [0xc0,0xe5,A,A,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: target+2, kind: FK_390_PC32DBL
+# CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_PC32DBL target 0x2
+	.align 16
+	brasl %r14, target
+
+# CHECK: brasl %r14, target@PLT                 # encoding: [0xc0,0xe5,A,A,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: target@PLT+2, kind: FK_390_PC32DBL
+# CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_PLT32DBL target 0x2
+	.align 16
+	brasl %r14, target@plt
+
+# CHECK: brasl %r14, target@PLT:tls_gdcall:sym  # encoding: [0xc0,0xe5,A,A,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: target@PLT+2, kind: FK_390_PC32DBL
+# CHECK-NEXT:                                   # fixup B - offset: 0, value: sym@TLSGD, kind: FK_390_TLS_CALL
+# CHECK-REL:                                    0x{{[0-9A-F]*0}} R_390_TLS_GDCALL sym 0x0
+# CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_PLT32DBL target 0x2
+	.align 16
+	brasl %r14, target@plt:tls_gdcall:sym
+
+# CHECK: brasl %r14, target@PLT:tls_ldcall:sym  # encoding: [0xc0,0xe5,A,A,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: target@PLT+2, kind: FK_390_PC32DBL
+# CHECK-NEXT:                                   # fixup B - offset: 0, value: sym@TLSLDM, kind: FK_390_TLS_CALL
+# CHECK-REL:                                    0x{{[0-9A-F]*0}} R_390_TLS_LDCALL sym 0x0
+# CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_PLT32DBL target 0x2
+	.align 16
+	brasl %r14, target@plt:tls_ldcall:sym
+
+# CHECK: bras %r14, target                      # encoding: [0xa7,0xe5,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: target+2, kind: FK_390_PC16DBL
+# CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_PC16DBL target 0x2
+	.align 16
+	bras %r14, target
+
+# CHECK: bras %r14, target@PLT                  # encoding: [0xa7,0xe5,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: target@PLT+2, kind: FK_390_PC16DBL
+# CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_PLT16DBL target 0x2
+	.align 16
+	bras %r14, target@plt
+
+# CHECK: bras %r14, target@PLT:tls_gdcall:sym   # encoding: [0xa7,0xe5,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: target@PLT+2, kind: FK_390_PC16DBL
+# CHECK-NEXT:                                   # fixup B - offset: 0, value: sym@TLSGD, kind: FK_390_TLS_CALL
+# CHECK-REL:                                    0x{{[0-9A-F]*0}} R_390_TLS_GDCALL sym 0x0
+# CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_PLT16DBL target 0x2
+	.align 16
+	bras %r14, target@plt:tls_gdcall:sym
+
+# CHECK: bras %r14, target@PLT:tls_ldcall:sym   # encoding: [0xa7,0xe5,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: target@PLT+2, kind: FK_390_PC16DBL
+# CHECK-NEXT:                                   # fixup B - offset: 0, value: sym@TLSLDM, kind: FK_390_TLS_CALL
+# CHECK-REL:                                    0x{{[0-9A-F]*0}} R_390_TLS_LDCALL sym 0x0
+# CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_PLT16DBL target 0x2
+	.align 16
+	bras %r14, target@plt:tls_ldcall:sym
+
+
+# Data relocs
+# llvm-mc does not show any "encoding" string for data, so we just check the relocs
+
+# CHECK-REL: .rela.data
+	.data
+
+# CHECK-REL: 0x{{[0-9A-F]*0}} R_390_TLS_LE64 target 0x0
+	.align 16
+	.quad target@ntpoff
+
+# CHECK-REL: 0x{{[0-9A-F]*0}} R_390_TLS_LDO64 target 0x0
+	.align 16
+	.quad target@dtpoff
+
+# CHECK-REL: 0x{{[0-9A-F]*0}} R_390_TLS_LDM64 target 0x0
+	.align 16
+	.quad target@tlsldm
+
+# CHECK-REL: 0x{{[0-9A-F]*0}} R_390_TLS_GD64 target 0x0
+	.align 16
+	.quad target@tlsgd
+
+# CHECK-REL: 0x{{[0-9A-F]*0}} R_390_TLS_LE32 target 0x0
+	.align 16
+	.long target@ntpoff
+
+# CHECK-REL: 0x{{[0-9A-F]*0}} R_390_TLS_LDO32 target 0x0
+	.align 16
+	.long target@dtpoff
+
+# CHECK-REL: 0x{{[0-9A-F]*0}} R_390_TLS_LDM32 target 0x0
+	.align 16
+	.long target@tlsldm
+
+# CHECK-REL: 0x{{[0-9A-F]*0}} R_390_TLS_GD32 target 0x0
+	.align 16
+	.long target@tlsgd
+
diff --git a/test/MC/SystemZ/insn-bad-z13.s b/test/MC/SystemZ/insn-bad-z13.s
new file mode 100644
index 000000000000..6468e3ae2ba0
--- /dev/null
+++ b/test/MC/SystemZ/insn-bad-z13.s
@@ -0,0 +1,1201 @@
+# For z13 only.
+# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=z13 < %s 2> %t
+# RUN: FileCheck < %t %s
+
+#CHECK: error: invalid operand
+#CHECK: lcbb	%r0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: lcbb	%r0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: lcbb	%r0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: lcbb	%r0, 4096, 0
+#CHECK: error: invalid use of vector addressing
+#CHECK: lcbb	%r0, 0(%v1,%r2), 0
+
+	lcbb	%r0, 0, -1
+	lcbb	%r0, 0, 16
+	lcbb	%r0, -1, 0
+	lcbb	%r0, 4096, 0
+	lcbb	%r0, 0(%v1,%r2), 0
+
+#CHECK: error: invalid operand
+#CHECK: vcdgb	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vcdgb	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vcdgb	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vcdgb	%v0, %v0, 16, 0
+
+	vcdgb	%v0, %v0, 0, -1
+	vcdgb	%v0, %v0, 0, 16
+	vcdgb	%v0, %v0, -1, 0
+	vcdgb	%v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: vcdlgb	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vcdlgb	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vcdlgb	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vcdlgb	%v0, %v0, 16, 0
+
+	vcdlgb	%v0, %v0, 0, -1
+	vcdlgb	%v0, %v0, 0, 16
+	vcdlgb	%v0, %v0, -1, 0
+	vcdlgb	%v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: vcgdb	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vcgdb	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vcgdb	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vcgdb	%v0, %v0, 16, 0
+
+	vcgdb	%v0, %v0, 0, -1
+	vcgdb	%v0, %v0, 0, 16
+	vcgdb	%v0, %v0, -1, 0
+	vcgdb	%v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: vclgdb	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vclgdb	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vclgdb	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vclgdb	%v0, %v0, 16, 0
+
+	vclgdb	%v0, %v0, 0, -1
+	vclgdb	%v0, %v0, 0, 16
+	vclgdb	%v0, %v0, -1, 0
+	vclgdb	%v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: verimb	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: verimb	%v0, %v0, %v0, 256
+
+	verimb	%v0, %v0, %v0, -1
+	verimb	%v0, %v0, %v0, 256
+
+#CHECK: error: invalid operand
+#CHECK: verimf	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: verimf	%v0, %v0, %v0, 256
+
+	verimf	%v0, %v0, %v0, -1
+	verimf	%v0, %v0, %v0, 256
+
+#CHECK: error: invalid operand
+#CHECK: verimg	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: verimg	%v0, %v0, %v0, 256
+
+	verimg	%v0, %v0, %v0, -1
+	verimg	%v0, %v0, %v0, 256
+
+#CHECK: error: invalid operand
+#CHECK: verimh	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: verimh	%v0, %v0, %v0, 256
+
+	verimh	%v0, %v0, %v0, -1
+	verimh	%v0, %v0, %v0, 256
+
+#CHECK: error: invalid operand
+#CHECK: verllb	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: verllb	%v0, %v0, 4096
+
+	verllb	%v0, %v0, -1
+	verllb	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: verllf	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: verllf	%v0, %v0, 4096
+
+	verllf	%v0, %v0, -1
+	verllf	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: verllg	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: verllg	%v0, %v0, 4096
+
+	verllg	%v0, %v0, -1
+	verllg	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: verllh	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: verllh	%v0, %v0, 4096
+
+	verllh	%v0, %v0, -1
+	verllh	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: veslb	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: veslb	%v0, %v0, 4096
+
+	veslb	%v0, %v0, -1
+	veslb	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: veslf	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: veslf	%v0, %v0, 4096
+
+	veslf	%v0, %v0, -1
+	veslf	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: veslg	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: veslg	%v0, %v0, 4096
+
+	veslg	%v0, %v0, -1
+	veslg	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: veslh	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: veslh	%v0, %v0, 4096
+
+	veslh	%v0, %v0, -1
+	veslh	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: vesrab	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vesrab	%v0, %v0, 4096
+
+	vesrab	%v0, %v0, -1
+	vesrab	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: vesraf	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vesraf	%v0, %v0, 4096
+
+	vesraf	%v0, %v0, -1
+	vesraf	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: vesrag	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vesrag	%v0, %v0, 4096
+
+	vesrag	%v0, %v0, -1
+	vesrag	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: vesrah	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vesrah	%v0, %v0, 4096
+
+	vesrah	%v0, %v0, -1
+	vesrah	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: vesrlb	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vesrlb	%v0, %v0, 4096
+
+	vesrlb	%v0, %v0, -1
+	vesrlb	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: vesrlf	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vesrlf	%v0, %v0, 4096
+
+	vesrlf	%v0, %v0, -1
+	vesrlf	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: vesrlg	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vesrlg	%v0, %v0, 4096
+
+	vesrlg	%v0, %v0, -1
+	vesrlg	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: vesrlh	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vesrlh	%v0, %v0, 4096
+
+	vesrlh	%v0, %v0, -1
+	vesrlh	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: vfaeb	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vfaeb	%v0, %v0, %v0, 16
+#CHECK: error: too few operands
+#CHECK: vfaeb	%v0, %v0
+#CHECK: error: invalid operand
+#CHECK: vfaeb	%v0, %v0, %v0, 0, 0
+
+	vfaeb	%v0, %v0, %v0, -1
+	vfaeb	%v0, %v0, %v0, 16
+	vfaeb	%v0, %v0
+	vfaeb	%v0, %v0, %v0, 0, 0
+
+#CHECK: error: invalid operand
+#CHECK: vfaebs	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vfaebs	%v0, %v0, %v0, 16
+#CHECK: error: too few operands
+#CHECK: vfaebs	%v0, %v0
+#CHECK: error: invalid operand
+#CHECK: vfaebs	%v0, %v0, %v0, 0, 0
+
+	vfaebs	%v0, %v0, %v0, -1
+	vfaebs	%v0, %v0, %v0, 16
+	vfaebs	%v0, %v0
+	vfaebs	%v0, %v0, %v0, 0, 0
+
+#CHECK: error: invalid operand
+#CHECK: vfaef	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vfaef	%v0, %v0, %v0, 16
+#CHECK: error: too few operands
+#CHECK: vfaef	%v0, %v0
+#CHECK: error: invalid operand
+#CHECK: vfaef	%v0, %v0, %v0, 0, 0
+
+	vfaef	%v0, %v0, %v0, -1
+	vfaef	%v0, %v0, %v0, 16
+	vfaef	%v0, %v0
+	vfaef	%v0, %v0, %v0, 0, 0
+
+#CHECK: error: invalid operand
+#CHECK: vfaeh	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vfaeh	%v0, %v0, %v0, 16
+#CHECK: error: too few operands
+#CHECK: vfaeh	%v0, %v0
+#CHECK: error: invalid operand
+#CHECK: vfaeh	%v0, %v0, %v0, 0, 0
+
+	vfaeh	%v0, %v0, %v0, -1
+	vfaeh	%v0, %v0, %v0, 16
+	vfaeh	%v0, %v0
+	vfaeh	%v0, %v0, %v0, 0, 0
+
+#CHECK: error: invalid operand
+#CHECK: vfaezh	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vfaezh	%v0, %v0, %v0, 16
+#CHECK: error: too few operands
+#CHECK: vfaezh	%v0, %v0
+#CHECK: error: invalid operand
+#CHECK: vfaezh	%v0, %v0, %v0, 0, 0
+
+	vfaezh	%v0, %v0, %v0, -1
+	vfaezh	%v0, %v0, %v0, 16
+	vfaezh	%v0, %v0
+	vfaezh	%v0, %v0, %v0, 0, 0
+
+#CHECK: error: invalid operand
+#CHECK: vfaezfs	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vfaezfs	%v0, %v0, %v0, 16
+#CHECK: error: too few operands
+#CHECK: vfaezfs	%v0, %v0
+#CHECK: error: invalid operand
+#CHECK: vfaezfs	%v0, %v0, %v0, 0, 0
+
+	vfaezfs	%v0, %v0, %v0, -1
+	vfaezfs	%v0, %v0, %v0, 16
+	vfaezfs	%v0, %v0
+	vfaezfs	%v0, %v0, %v0, 0, 0
+
+#CHECK: error: invalid operand
+#CHECK: vfidb	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vfidb	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vfidb	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vfidb	%v0, %v0, 16, 0
+
+	vfidb	%v0, %v0, 0, -1
+	vfidb	%v0, %v0, 0, 16
+	vfidb	%v0, %v0, -1, 0
+	vfidb	%v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: vftcidb	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vftcidb	%v0, %v0, 4096
+
+	vftcidb	%v0, %v0, -1
+	vftcidb	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: vgbm	%v0, -1
+#CHECK: error: invalid operand
+#CHECK: vgbm	%v0, 0x10000
+
+	vgbm	%v0, -1
+	vgbm	%v0, 0x10000
+
+#CHECK: error: vector index required
+#CHECK: vgef	%v0, 0(%r1), 0
+#CHECK: error: vector index required
+#CHECK: vgef	%v0, 0(%r2,%r1), 0
+#CHECK: error: invalid operand
+#CHECK: vgef	%v0, 0(%v0,%r1), -1
+#CHECK: error: invalid operand
+#CHECK: vgef	%v0, 0(%v0,%r1), 4
+#CHECK: error: invalid operand
+#CHECK: vgef	%v0, -1(%v0,%r1), 0
+#CHECK: error: invalid operand
+#CHECK: vgef	%v0, 4096(%v0,%r1), 0
+
+	vgef	%v0, 0(%r1), 0
+	vgef	%v0, 0(%r2,%r1), 0
+	vgef	%v0, 0(%v0,%r1), -1
+	vgef	%v0, 0(%v0,%r1), 4
+	vgef	%v0, -1(%v0,%r1), 0
+	vgef	%v0, 4096(%v0,%r1), 0
+
+#CHECK: error: vector index required
+#CHECK: vgeg	%v0, 0(%r1), 0
+#CHECK: error: vector index required
+#CHECK: vgeg	%v0, 0(%r2,%r1), 0
+#CHECK: error: invalid operand
+#CHECK: vgeg	%v0, 0(%v0,%r1), -1
+#CHECK: error: invalid operand
+#CHECK: vgeg	%v0, 0(%v0,%r1), 2
+#CHECK: error: invalid operand
+#CHECK: vgeg	%v0, -1(%v0,%r1), 0
+#CHECK: error: invalid operand
+#CHECK: vgeg	%v0, 4096(%v0,%r1), 0
+
+	vgeg	%v0, 0(%r1), 0
+	vgeg	%v0, 0(%r2,%r1), 0
+	vgeg	%v0, 0(%v0,%r1), -1
+	vgeg	%v0, 0(%v0,%r1), 2
+	vgeg	%v0, -1(%v0,%r1), 0
+	vgeg	%v0, 4096(%v0,%r1), 0
+
+#CHECK: error: invalid operand
+#CHECK: vgmb	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vgmb	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vgmb	%v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vgmb	%v0, 256, 0
+
+	vgmb	%v0, 0, -1
+	vgmb	%v0, 0, -1
+	vgmb	%v0, -1, 0
+	vgmb	%v0, 256, 0
+
+#CHECK: error: invalid operand
+#CHECK: vgmf	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vgmf	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vgmf	%v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vgmf	%v0, 256, 0
+
+	vgmf	%v0, 0, -1
+	vgmf	%v0, 0, -1
+	vgmf	%v0, -1, 0
+	vgmf	%v0, 256, 0
+
+#CHECK: error: invalid operand
+#CHECK: vgmg	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vgmg	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vgmg	%v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vgmg	%v0, 256, 0
+
+	vgmg	%v0, 0, -1
+	vgmg	%v0, 0, -1
+	vgmg	%v0, -1, 0
+	vgmg	%v0, 256, 0
+
+#CHECK: error: invalid operand
+#CHECK: vgmh	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vgmh	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vgmh	%v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vgmh	%v0, 256, 0
+
+	vgmh	%v0, 0, -1
+	vgmh	%v0, 0, -1
+	vgmh	%v0, -1, 0
+	vgmh	%v0, 256, 0
+
+#CHECK: error: invalid operand
+#CHECK: vl	%v0, -1
+#CHECK: error: invalid operand
+#CHECK: vl	%v0, 4096
+#CHECK: error: invalid use of vector addressing
+#CHECK: vl	%v0, 0(%v1,%r2)
+
+	vl	%v0, -1
+	vl	%v0, 4096
+	vl	%v0, 0(%v1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: vlbb	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vlbb	%v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vlbb	%v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vlbb	%v0, 4096, 0
+#CHECK: error: invalid use of vector addressing
+#CHECK: vlbb	%v0, 0(%v1,%r2), 0
+
+	vlbb	%v0, 0, -1
+	vlbb	%v0, 0, 16
+	vlbb	%v0, -1, 0
+	vlbb	%v0, 4096, 0
+	vlbb	%v0, 0(%v1,%r2), 0
+
+#CHECK: error: invalid operand
+#CHECK: vleb	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vleb	%v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vleb	%v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vleb	%v0, 4096, 0
+#CHECK: error: invalid use of vector addressing
+#CHECK: vleb	%v0, 0(%v1,%r2), 0
+
+	vleb	%v0, 0, -1
+	vleb	%v0, 0, 16
+	vleb	%v0, -1, 0
+	vleb	%v0, 4096, 0
+	vleb	%v0, 0(%v1,%r2), 0
+
+#CHECK: error: invalid operand
+#CHECK: vledb	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vledb	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vledb	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vledb	%v0, %v0, 16, 0
+
+	vledb	%v0, %v0, 0, -1
+	vledb	%v0, %v0, 0, 16
+	vledb	%v0, %v0, -1, 0
+	vledb	%v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: vlef	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vlef	%v0, 0, 4
+#CHECK: error: invalid operand
+#CHECK: vlef	%v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vlef	%v0, 4096, 0
+#CHECK: error: invalid use of vector addressing
+#CHECK: vlef	%v0, 0(%v1,%r2), 0
+
+	vlef	%v0, 0, -1
+	vlef	%v0, 0, 4
+	vlef	%v0, -1, 0
+	vlef	%v0, 4096, 0
+	vlef	%v0, 0(%v1,%r2), 0
+
+#CHECK: error: invalid operand
+#CHECK: vleg	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vleg	%v0, 0, 2
+#CHECK: error: invalid operand
+#CHECK: vleg	%v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vleg	%v0, 4096, 0
+#CHECK: error: invalid use of vector addressing
+#CHECK: vleg	%v0, 0(%v1,%r2), 0
+
+	vleg	%v0, 0, -1
+	vleg	%v0, 0, 2
+	vleg	%v0, -1, 0
+	vleg	%v0, 4096, 0
+	vleg	%v0, 0(%v1,%r2), 0
+
+#CHECK: error: invalid operand
+#CHECK: vleh	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vleh	%v0, 0, 8
+#CHECK: error: invalid operand
+#CHECK: vleh	%v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vleh	%v0, 4096, 0
+#CHECK: error: invalid use of vector addressing
+#CHECK: vleh	%v0, 0(%v1,%r2), 0
+
+	vleh	%v0, 0, -1
+	vleh	%v0, 0, 8
+	vleh	%v0, -1, 0
+	vleh	%v0, 4096, 0
+	vleh	%v0, 0(%v1,%r2), 0
+
+#CHECK: error: invalid operand
+#CHECK: vleib	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vleib	%v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vleib	%v0, -32769, 0
+#CHECK: error: invalid operand
+#CHECK: vleib	%v0, 32768, 0
+
+	vleib	%v0, 0, -1
+	vleib	%v0, 0, 16
+	vleib	%v0, -32769, 0
+	vleib	%v0, 32768, 0
+
+#CHECK: error: invalid operand
+#CHECK: vleif	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vleif	%v0, 0, 4
+#CHECK: error: invalid operand
+#CHECK: vleif	%v0, -32769, 0
+#CHECK: error: invalid operand
+#CHECK: vleif	%v0, 32768, 0
+
+	vleif	%v0, 0, -1
+	vleif	%v0, 0, 4
+	vleif	%v0, -32769, 0
+	vleif	%v0, 32768, 0
+
+#CHECK: error: invalid operand
+#CHECK: vleig	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vleig	%v0, 0, 2
+#CHECK: error: invalid operand
+#CHECK: vleig	%v0, -32769, 0
+#CHECK: error: invalid operand
+#CHECK: vleig	%v0, 32768, 0
+
+	vleig	%v0, 0, -1
+	vleig	%v0, 0, 2
+	vleig	%v0, -32769, 0
+	vleig	%v0, 32768, 0
+
+#CHECK: error: invalid operand
+#CHECK: vleih	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vleih	%v0, 0, 8
+#CHECK: error: invalid operand
+#CHECK: vleih	%v0, -32769, 0
+#CHECK: error: invalid operand
+#CHECK: vleih	%v0, 32768, 0
+
+	vleih	%v0, 0, -1
+	vleih	%v0, 0, 8
+	vleih	%v0, -32769, 0
+	vleih	%v0, 32768, 0
+
+#CHECK: error: invalid operand
+#CHECK: vlgvb	%r0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vlgvb	%r0, %v0, 4096
+#CHECK: error: %r0 used in an address
+#CHECK: vlgvb	%r0, %v0, 0(%r0)
+
+	vlgvb	%r0, %v0, -1
+	vlgvb	%r0, %v0, 4096
+	vlgvb	%r0, %v0, 0(%r0)
+
+#CHECK: error: invalid operand
+#CHECK: vlgvf	%r0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vlgvf	%r0, %v0, 4096
+#CHECK: error: %r0 used in an address
+#CHECK: vlgvf	%r0, %v0, 0(%r0)
+
+	vlgvf	%r0, %v0, -1
+	vlgvf	%r0, %v0, 4096
+	vlgvf	%r0, %v0, 0(%r0)
+
+#CHECK: error: invalid operand
+#CHECK: vlgvg	%r0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vlgvg	%r0, %v0, 4096
+#CHECK: error: %r0 used in an address
+#CHECK: vlgvg	%r0, %v0, 0(%r0)
+
+	vlgvg	%r0, %v0, -1
+	vlgvg	%r0, %v0, 4096
+	vlgvg	%r0, %v0, 0(%r0)
+
+#CHECK: error: invalid operand
+#CHECK: vlgvh	%r0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vlgvh	%r0, %v0, 4096
+#CHECK: error: %r0 used in an address
+#CHECK: vlgvh	%r0, %v0, 0(%r0)
+
+	vlgvh	%r0, %v0, -1
+	vlgvh	%r0, %v0, 4096
+	vlgvh	%r0, %v0, 0(%r0)
+
+#CHECK: error: invalid operand
+#CHECK: vll	%v0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: vll	%v0, %r0, 4096
+#CHECK: error: %r0 used in an address
+#CHECK: vll	%v0, %r0, 0(%r0)
+
+	vll	%v0, %r0, -1
+	vll	%v0, %r0, 4096
+	vll	%v0, %r0, 0(%r0)
+
+#CHECK: error: invalid operand
+#CHECK: vllezb	%v0, -1
+#CHECK: error: invalid operand
+#CHECK: vllezb	%v0, 4096
+#CHECK: error: invalid use of vector addressing
+#CHECK: vllezb	%v0, 0(%v1,%r2)
+
+	vllezb	%v0, -1
+	vllezb	%v0, 4096
+	vllezb	%v0, 0(%v1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: vllezf	%v0, -1
+#CHECK: error: invalid operand
+#CHECK: vllezf	%v0, 4096
+#CHECK: error: invalid use of vector addressing
+#CHECK: vllezf	%v0, 0(%v1,%r2)
+
+	vllezf	%v0, -1
+	vllezf	%v0, 4096
+	vllezf	%v0, 0(%v1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: vllezg	%v0, -1
+#CHECK: error: invalid operand
+#CHECK: vllezg	%v0, 4096
+#CHECK: error: invalid use of vector addressing
+#CHECK: vllezg	%v0, 0(%v1,%r2)
+
+	vllezg	%v0, -1
+	vllezg	%v0, 4096
+	vllezg	%v0, 0(%v1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: vllezh	%v0, -1
+#CHECK: error: invalid operand
+#CHECK: vllezh	%v0, 4096
+#CHECK: error: invalid use of vector addressing
+#CHECK: vllezh	%v0, 0(%v1,%r2)
+
+	vllezh	%v0, -1
+	vllezh	%v0, 4096
+	vllezh	%v0, 0(%v1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: vlm	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vlm	%v0, %v0, 4096
+
+	vlm	%v0, %v0, -1
+	vlm	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: vlrepb	%v0, -1
+#CHECK: error: invalid operand
+#CHECK: vlrepb	%v0, 4096
+#CHECK: error: invalid use of vector addressing
+#CHECK: vlrepb	%v0, 0(%v1,%r2)
+
+	vlrepb	%v0, -1
+	vlrepb	%v0, 4096
+	vlrepb	%v0, 0(%v1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: vlrepf	%v0, -1
+#CHECK: error: invalid operand
+#CHECK: vlrepf	%v0, 4096
+#CHECK: error: invalid use of vector addressing
+#CHECK: vlrepf	%v0, 0(%v1,%r2)
+
+	vlrepf	%v0, -1
+	vlrepf	%v0, 4096
+	vlrepf	%v0, 0(%v1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: vlrepg	%v0, -1
+#CHECK: error: invalid operand
+#CHECK: vlrepg	%v0, 4096
+#CHECK: error: invalid use of vector addressing
+#CHECK: vlrepg	%v0, 0(%v1,%r2)
+
+	vlrepg	%v0, -1
+	vlrepg	%v0, 4096
+	vlrepg	%v0, 0(%v1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: vlreph	%v0, -1
+#CHECK: error: invalid operand
+#CHECK: vlreph	%v0, 4096
+#CHECK: error: invalid use of vector addressing
+#CHECK: vlreph	%v0, 0(%v1,%r2)
+
+	vlreph	%v0, -1
+	vlreph	%v0, 4096
+	vlreph	%v0, 0(%v1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: vlvgb	%v0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: vlvgb	%v0, %r0, 4096
+#CHECK: error: %r0 used in an address
+#CHECK: vlvgb	%v0, %r0, 0(%r0)
+
+	vlvgb	%v0, %r0, -1
+	vlvgb	%v0, %r0, 4096
+	vlvgb	%v0, %r0, 0(%r0)
+
+#CHECK: error: invalid operand
+#CHECK: vlvgf	%v0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: vlvgf	%v0, %r0, 4096
+#CHECK: error: %r0 used in an address
+#CHECK: vlvgf	%v0, %r0, 0(%r0)
+
+	vlvgf	%v0, %r0, -1
+	vlvgf	%v0, %r0, 4096
+	vlvgf	%v0, %r0, 0(%r0)
+
+#CHECK: error: invalid operand
+#CHECK: vlvgg	%v0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: vlvgg	%v0, %r0, 4096
+#CHECK: error: %r0 used in an address
+#CHECK: vlvgg	%v0, %r0, 0(%r0)
+
+	vlvgg	%v0, %r0, -1
+	vlvgg	%v0, %r0, 4096
+	vlvgg	%v0, %r0, 0(%r0)
+
+#CHECK: error: invalid operand
+#CHECK: vlvgh	%v0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: vlvgh	%v0, %r0, 4096
+#CHECK: error: %r0 used in an address
+#CHECK: vlvgh	%v0, %r0, 0(%r0)
+
+	vlvgh	%v0, %r0, -1
+	vlvgh	%v0, %r0, 4096
+	vlvgh	%v0, %r0, 0(%r0)
+
+#CHECK: error: invalid operand
+#CHECK: vpdi	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vpdi	%v0, %v0, %v0, 16
+
+	vpdi	%v0, %v0, %v0, -1
+	vpdi	%v0, %v0, %v0, 16
+
+#CHECK: error: invalid operand
+#CHECK: vrepb	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vrepb	%v0, %v0, 65536
+
+	vrepb	%v0, %v0, -1
+	vrepb	%v0, %v0, 65536
+
+#CHECK: error: invalid operand
+#CHECK: vrepf	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vrepf	%v0, %v0, 65536
+
+	vrepf	%v0, %v0, -1
+	vrepf	%v0, %v0, 65536
+
+#CHECK: error: invalid operand
+#CHECK: vrepg	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vrepg	%v0, %v0, 65536
+
+	vrepg	%v0, %v0, -1
+	vrepg	%v0, %v0, 65536
+
+#CHECK: error: invalid operand
+#CHECK: vreph	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vreph	%v0, %v0, 65536
+
+	vreph	%v0, %v0, -1
+	vreph	%v0, %v0, 65536
+
+#CHECK: error: invalid operand
+#CHECK: vrepib	%v0, -32769
+#CHECK: error: invalid operand
+#CHECK: vrepib	%v0, 32768
+
+	vrepib	%v0, -32769
+	vrepib	%v0, 32768
+
+#CHECK: error: invalid operand
+#CHECK: vrepif	%v0, -32769
+#CHECK: error: invalid operand
+#CHECK: vrepif	%v0, 32768
+
+	vrepif	%v0, -32769
+	vrepif	%v0, 32768
+
+#CHECK: error: invalid operand
+#CHECK: vrepig	%v0, -32769
+#CHECK: error: invalid operand
+#CHECK: vrepig	%v0, 32768
+
+	vrepig	%v0, -32769
+	vrepig	%v0, 32768
+
+#CHECK: error: invalid operand
+#CHECK: vrepih	%v0, -32769
+#CHECK: error: invalid operand
+#CHECK: vrepih	%v0, 32768
+
+	vrepih	%v0, -32769
+	vrepih	%v0, 32768
+
+#CHECK: error: vector index required
+#CHECK: vscef	%v0, 0(%r1), 0
+#CHECK: error: vector index required
+#CHECK: vscef	%v0, 0(%r2,%r1), 0
+#CHECK: error: invalid operand
+#CHECK: vscef	%v0, 0(%v0,%r1), -1
+#CHECK: error: invalid operand
+#CHECK: vscef	%v0, 0(%v0,%r1), 4
+#CHECK: error: invalid operand
+#CHECK: vscef	%v0, -1(%v0,%r1), 0
+#CHECK: error: invalid operand
+#CHECK: vscef	%v0, 4096(%v0,%r1), 0
+
+	vscef	%v0, 0(%r1), 0
+	vscef	%v0, 0(%r2,%r1), 0
+	vscef	%v0, 0(%v0,%r1), -1
+	vscef	%v0, 0(%v0,%r1), 4
+	vscef	%v0, -1(%v0,%r1), 0
+	vscef	%v0, 4096(%v0,%r1), 0
+
+#CHECK: error: vector index required
+#CHECK: vsceg	%v0, 0(%r1), 0
+#CHECK: error: vector index required
+#CHECK: vsceg	%v0, 0(%r2,%r1), 0
+#CHECK: error: invalid operand
+#CHECK: vsceg	%v0, 0(%v0,%r1), -1
+#CHECK: error: invalid operand
+#CHECK: vsceg	%v0, 0(%v0,%r1), 2
+#CHECK: error: invalid operand
+#CHECK: vsceg	%v0, -1(%v0,%r1), 0
+#CHECK: error: invalid operand
+#CHECK: vsceg	%v0, 4096(%v0,%r1), 0
+
+	vsceg	%v0, 0(%r1), 0
+	vsceg	%v0, 0(%r2,%r1), 0
+	vsceg	%v0, 0(%v0,%r1), -1
+	vsceg	%v0, 0(%v0,%r1), 2
+	vsceg	%v0, -1(%v0,%r1), 0
+	vsceg	%v0, 4096(%v0,%r1), 0
+
+#CHECK: error: invalid operand
+#CHECK: vsldb	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vsldb	%v0, %v0, %v0, 256
+
+	vsldb	%v0, %v0, %v0, -1
+	vsldb	%v0, %v0, %v0, 256
+
+#CHECK: error: invalid operand
+#CHECK: vst	%v0, -1
+#CHECK: error: invalid operand
+#CHECK: vst	%v0, 4096
+#CHECK: error: invalid use of vector addressing
+#CHECK: vst	%v0, 0(%v1,%r2)
+
+	vst	%v0, -1
+	vst	%v0, 4096
+	vst	%v0, 0(%v1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: vsteb	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vsteb	%v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vsteb	%v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vsteb	%v0, 4096, 0
+#CHECK: error: invalid use of vector addressing
+#CHECK: vsteb	%v0, 0(%v1,%r2), 0
+
+	vsteb	%v0, 0, -1
+	vsteb	%v0, 0, 16
+	vsteb	%v0, -1, 0
+	vsteb	%v0, 4096, 0
+	vsteb	%v0, 0(%v1,%r2), 0
+
+#CHECK: error: invalid operand
+#CHECK: vstef	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vstef	%v0, 0, 4
+#CHECK: error: invalid operand
+#CHECK: vstef	%v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vstef	%v0, 4096, 0
+#CHECK: error: invalid use of vector addressing
+#CHECK: vstef	%v0, 0(%v1,%r2), 0
+
+	vstef	%v0, 0, -1
+	vstef	%v0, 0, 4
+	vstef	%v0, -1, 0
+	vstef	%v0, 4096, 0
+	vstef	%v0, 0(%v1,%r2), 0
+
+#CHECK: error: invalid operand
+#CHECK: vsteg	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vsteg	%v0, 0, 2
+#CHECK: error: invalid operand
+#CHECK: vsteg	%v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vsteg	%v0, 4096, 0
+#CHECK: error: invalid use of vector addressing
+#CHECK: vsteg	%v0, 0(%v1,%r2), 0
+
+	vsteg	%v0, 0, -1
+	vsteg	%v0, 0, 2
+	vsteg	%v0, -1, 0
+	vsteg	%v0, 4096, 0
+	vsteg	%v0, 0(%v1,%r2), 0
+
+#CHECK: error: invalid operand
+#CHECK: vsteh	%v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vsteh	%v0, 0, 8
+#CHECK: error: invalid operand
+#CHECK: vsteh	%v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vsteh	%v0, 4096, 0
+#CHECK: error: invalid use of vector addressing
+#CHECK: vsteh	%v0, 0(%v1,%r2), 0
+
+	vsteh	%v0, 0, -1
+	vsteh	%v0, 0, 8
+	vsteh	%v0, -1, 0
+	vsteh	%v0, 4096, 0
+	vsteh	%v0, 0(%v1,%r2), 0
+
+#CHECK: error: invalid operand
+#CHECK: vstl	%v0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: vstl	%v0, %r0, 4096
+#CHECK: error: %r0 used in an address
+#CHECK: vstl	%v0, %r0, 0(%r0)
+
+	vstl	%v0, %r0, -1
+	vstl	%v0, %r0, 4096
+	vstl	%v0, %r0, 0(%r0)
+
+#CHECK: error: invalid operand
+#CHECK: vstm	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vstm	%v0, %v0, 4096
+
+	vstm	%v0, %v0, -1
+	vstm	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: vstrcb   %v0, %v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vstrcb   %v0, %v0, %v0, %v0, 16
+#CHECK: error: too few operands
+#CHECK: vstrcb   %v0, %v0, %v0
+#CHECK: error: invalid operand
+#CHECK: vstrcb   %v0, %v0, %v0, %v0, 0, 0
+
+        vstrcb   %v0, %v0, %v0, %v0, -1
+        vstrcb   %v0, %v0, %v0, %v0, 16
+        vstrcb   %v0, %v0, %v0
+        vstrcb   %v0, %v0, %v0, %v0, 0, 0
+
+#CHECK: error: invalid operand
+#CHECK: vstrcbs  %v0, %v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vstrcbs  %v0, %v0, %v0, %v0, 16
+#CHECK: error: too few operands
+#CHECK: vstrcbs  %v0, %v0, %v0
+#CHECK: error: invalid operand
+#CHECK: vstrcbs  %v0, %v0, %v0, %v0, 0, 0
+
+        vstrcbs  %v0, %v0, %v0, %v0, -1
+        vstrcbs  %v0, %v0, %v0, %v0, 16
+        vstrcbs  %v0, %v0, %v0
+        vstrcbs  %v0, %v0, %v0, %v0, 0, 0
+
+#CHECK: error: invalid operand
+#CHECK: vstrcf   %v0, %v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vstrcf   %v0, %v0, %v0, %v0, 16
+#CHECK: error: too few operands
+#CHECK: vstrcf   %v0, %v0, %v0
+#CHECK: error: invalid operand
+#CHECK: vstrcf   %v0, %v0, %v0, %v0, 0, 0
+
+        vstrcf   %v0, %v0, %v0, %v0, -1
+        vstrcf   %v0, %v0, %v0, %v0, 16
+        vstrcf   %v0, %v0, %v0
+        vstrcf   %v0, %v0, %v0, %v0, 0, 0
+
+#CHECK: error: invalid operand
+#CHECK: vstrch   %v0, %v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vstrch   %v0, %v0, %v0, %v0, 16
+#CHECK: error: too few operands
+#CHECK: vstrch   %v0, %v0, %v0
+#CHECK: error: invalid operand
+#CHECK: vstrch   %v0, %v0, %v0, %v0, 0, 0
+
+        vstrch   %v0, %v0, %v0, %v0, -1
+        vstrch   %v0, %v0, %v0, %v0, 16
+        vstrch   %v0, %v0, %v0
+        vstrch   %v0, %v0, %v0, %v0, 0, 0
+
+#CHECK: error: invalid operand
+#CHECK: vstrczh  %v0, %v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vstrczh  %v0, %v0, %v0, %v0, 16
+#CHECK: error: too few operands
+#CHECK: vstrczh  %v0, %v0, %v0
+#CHECK: error: invalid operand
+#CHECK: vstrczh  %v0, %v0, %v0, %v0, 0, 0
+
+        vstrczh  %v0, %v0, %v0, %v0, -1
+        vstrczh  %v0, %v0, %v0, %v0, 16
+        vstrczh  %v0, %v0, %v0
+        vstrczh  %v0, %v0, %v0, %v0, 0, 0
+
+#CHECK: error: invalid operand
+#CHECK: vstrczfs %v0, %v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vstrczfs %v0, %v0, %v0, %v0, 16
+#CHECK: error: too few operands
+#CHECK: vstrczfs %v0, %v0, %v0
+#CHECK: error: invalid operand
+#CHECK: vstrczfs %v0, %v0, %v0, %v0, 0, 0
+
+        vstrczfs %v0, %v0, %v0, %v0, -1
+        vstrczfs %v0, %v0, %v0, %v0, 16
+        vstrczfs %v0, %v0, %v0
+        vstrczfs %v0, %v0, %v0, %v0, 0, 0
+
+#CHECK: error: invalid operand
+#CHECK: wcdgb	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: wcdgb	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: wcdgb	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: wcdgb	%v0, %v0, 16, 0
+
+	wcdgb	%v0, %v0, 0, -1
+	wcdgb	%v0, %v0, 0, 16
+	wcdgb	%v0, %v0, -1, 0
+	wcdgb	%v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: wcdlgb	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: wcdlgb	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: wcdlgb	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: wcdlgb	%v0, %v0, 16, 0
+
+	wcdlgb	%v0, %v0, 0, -1
+	wcdlgb	%v0, %v0, 0, 16
+	wcdlgb	%v0, %v0, -1, 0
+	wcdlgb	%v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: wcgdb	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: wcgdb	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: wcgdb	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: wcgdb	%v0, %v0, 16, 0
+
+	wcgdb	%v0, %v0, 0, -1
+	wcgdb	%v0, %v0, 0, 16
+	wcgdb	%v0, %v0, -1, 0
+	wcgdb	%v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: wclgdb	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: wclgdb	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: wclgdb	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: wclgdb	%v0, %v0, 16, 0
+
+	wclgdb	%v0, %v0, 0, -1
+	wclgdb	%v0, %v0, 0, 16
+	wclgdb	%v0, %v0, -1, 0
+	wclgdb	%v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: wfidb	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: wfidb	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: wfidb	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: wfidb	%v0, %v0, 16, 0
+
+	wfidb	%v0, %v0, 0, -1
+	wfidb	%v0, %v0, 0, 16
+	wfidb	%v0, %v0, -1, 0
+	wfidb	%v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: wftcidb	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: wftcidb	%v0, %v0, 4096
+
+	wftcidb	%v0, %v0, -1
+	wftcidb	%v0, %v0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: wledb	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: wledb	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: wledb	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: wledb	%v0, %v0, 16, 0
+
+	wledb	%v0, %v0, 0, -1
+	wledb	%v0, %v0, 0, 16
+	wledb	%v0, %v0, -1, 0
+	wledb	%v0, %v0, 16, 0
diff --git a/test/MC/SystemZ/insn-bad-z196.s b/test/MC/SystemZ/insn-bad-z196.s
index 47dbe08b2525..1bd70a871ed2 100644
--- a/test/MC/SystemZ/insn-bad-z196.s
+++ b/test/MC/SystemZ/insn-bad-z196.s
@@ -244,6 +244,11 @@
 	cxlgbr	%f0, 16, %r0, 0
 	cxlgbr	%f2, 0, %r0, 0
 
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: etnd	%r7
+
+	etnd	%r7
+
 #CHECK: error: invalid operand
 #CHECK: fidbra	%f0, 0, %f0, -1
 #CHECK: error: invalid operand
@@ -546,6 +551,21 @@
 	locr	%r0,%r0,-1
 	locr	%r0,%r0,16
 
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: ntstg	%r0, 524287(%r1,%r15)
+
+	ntstg	%r0, 524287(%r1,%r15)
+
+#CHECK: error: {{(instruction requires: processor-assist)?}}
+#CHECK: ppa	%r4, %r6, 7
+
+	ppa	%r4, %r6, 7
+
+#CHECK: error: {{(instruction requires: miscellaneous-extensions)?}}
+#CHECK: risbgn	%r1, %r2, 0, 0, 0
+
+	risbgn	%r1, %r2, 0, 0, 0
+
 #CHECK: error: invalid operand
 #CHECK: risbhg	%r0,%r0,0,0,-1
 #CHECK: error: invalid operand
@@ -685,3 +705,24 @@
 	stocg	%r0,-524289,1
 	stocg	%r0,524288,1
 	stocg	%r0,0(%r1,%r2),1
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tabort	4095(%r1)
+
+	tabort	4095(%r1)
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tbegin	4095(%r1), 42
+
+	tbegin	4095(%r1), 42
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tbeginc	4095(%r1), 42
+
+	tbeginc	4095(%r1), 42
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tend
+
+	tend
+
diff --git a/test/MC/SystemZ/insn-bad-zEC12.s b/test/MC/SystemZ/insn-bad-zEC12.s
new file mode 100644
index 000000000000..ee31f5707af1
--- /dev/null
+++ b/test/MC/SystemZ/insn-bad-zEC12.s
@@ -0,0 +1,1578 @@
+# For zEC12 only.
+# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 < %s 2> %t
+# RUN: FileCheck < %t %s
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: lcbb	%r0, 0, 0
+
+	lcbb	%r0, 0, 0
+
+#CHECK: error: invalid operand
+#CHECK: ntstg	%r0, -524289
+#CHECK: error: invalid operand
+#CHECK: ntstg	%r0, 524288
+
+	ntstg	%r0, -524289
+	ntstg	%r0, 524288
+
+#CHECK: error: invalid operand
+#CHECK: ppa	%r0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: ppa	%r0, %r0, 16
+
+	ppa	%r0, %r0, -1
+	ppa	%r0, %r0, 16
+
+#CHECK: error: invalid operand
+#CHECK: risbgn	%r0,%r0,0,0,-1
+#CHECK: error: invalid operand
+#CHECK: risbgn	%r0,%r0,0,0,64
+#CHECK: error: invalid operand
+#CHECK: risbgn	%r0,%r0,0,-1,0
+#CHECK: error: invalid operand
+#CHECK: risbgn	%r0,%r0,0,256,0
+#CHECK: error: invalid operand
+#CHECK: risbgn	%r0,%r0,-1,0,0
+#CHECK: error: invalid operand
+#CHECK: risbgn	%r0,%r0,256,0,0
+
+	risbgn	%r0,%r0,0,0,-1
+	risbgn	%r0,%r0,0,0,64
+	risbgn	%r0,%r0,0,-1,0
+	risbgn	%r0,%r0,0,256,0
+	risbgn	%r0,%r0,-1,0,0
+	risbgn	%r0,%r0,256,0,0
+
+#CHECK: error: invalid operand
+#CHECK: tabort	-1
+#CHECK: error: invalid operand
+#CHECK: tabort	4096
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tabort	0(%r1,%r2)
+
+	tabort	-1
+	tabort	4096
+	tabort	0(%r1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: tbegin	-1, 0
+#CHECK: error: invalid operand
+#CHECK: tbegin	4096, 0
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tbegin	0(%r1,%r2), 0
+#CHECK: error: invalid operand
+#CHECK: tbegin	0, -1
+#CHECK: error: invalid operand
+#CHECK: tbegin	0, 65536
+
+	tbegin	-1, 0
+	tbegin	4096, 0
+	tbegin	0(%r1,%r2), 0
+	tbegin	0, -1
+	tbegin	0, 65536
+
+#CHECK: error: invalid operand
+#CHECK: tbeginc	-1, 0
+#CHECK: error: invalid operand
+#CHECK: tbeginc	4096, 0
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tbeginc	0(%r1,%r2), 0
+#CHECK: error: invalid operand
+#CHECK: tbeginc	0, -1
+#CHECK: error: invalid operand
+#CHECK: tbeginc	0, 65536
+
+	tbeginc	-1, 0
+	tbeginc	4096, 0
+	tbeginc	0(%r1,%r2), 0
+	tbeginc	0, -1
+	tbeginc	0, 65536
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vab	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vaf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vag	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vah	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vaq	%v0, %v0, %v0
+
+	vab	%v0, %v0, %v0
+	vaf	%v0, %v0, %v0
+	vag	%v0, %v0, %v0
+	vah	%v0, %v0, %v0
+	vaq	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vaccb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vaccf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vaccg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vacch	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vaccq	%v0, %v0, %v0
+
+	vaccb	%v0, %v0, %v0
+	vaccf	%v0, %v0, %v0
+	vaccg	%v0, %v0, %v0
+	vacch	%v0, %v0, %v0
+	vaccq	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vacccq	%v0, %v0, %v0
+
+	vacccq	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vacq	%v0, %v0, %v0
+
+	vacq	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vavgb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vavgf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vavgg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vavgh	%v0, %v0, %v0
+
+	vavgb	%v0, %v0, %v0
+	vavgf	%v0, %v0, %v0
+	vavgg	%v0, %v0, %v0
+	vavgh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vavglb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vavglf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vavglg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vavglh	%v0, %v0, %v0
+
+	vavglb	%v0, %v0, %v0
+	vavglf	%v0, %v0, %v0
+	vavglg	%v0, %v0, %v0
+	vavglh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vcdgb	%v0, %v0, 0, 0
+
+	vcdgb	%v0, %v0, 0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vcdlgb	%v0, %v0, 0, 0
+
+	vcdlgb	%v0, %v0, 0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vceqb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vceqf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vceqg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vceqh	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vceqbs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vceqhs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vceqfs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vceqgs	%v0, %v0, %v0
+
+	vceqb	%v0, %v0, %v0
+	vceqf	%v0, %v0, %v0
+	vceqg	%v0, %v0, %v0
+	vceqh	%v0, %v0, %v0
+	vceqbs	%v0, %v0, %v0
+	vceqhs	%v0, %v0, %v0
+	vceqfs	%v0, %v0, %v0
+	vceqgs	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vcgdb	%v0, %v0, 0, 0
+
+	vcgdb	%v0, %v0, 0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchh	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchbs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchhs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchfs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchgs	%v0, %v0, %v0
+
+	vchb	%v0, %v0, %v0
+	vchf	%v0, %v0, %v0
+	vchg	%v0, %v0, %v0
+	vchh	%v0, %v0, %v0
+	vchbs	%v0, %v0, %v0
+	vchhs	%v0, %v0, %v0
+	vchfs	%v0, %v0, %v0
+	vchgs	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchlb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchlf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchlg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchlh	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchlbs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchlhs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchlfs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vchlgs	%v0, %v0, %v0
+
+	vchlb	%v0, %v0, %v0
+	vchlf	%v0, %v0, %v0
+	vchlg	%v0, %v0, %v0
+	vchlh	%v0, %v0, %v0
+	vchlbs	%v0, %v0, %v0
+	vchlhs	%v0, %v0, %v0
+	vchlfs	%v0, %v0, %v0
+	vchlgs	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vcksm	%v0, %v0, %v0
+
+	vcksm	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vclgdb	%v0, %v0, 0, 0
+
+	vclgdb	%v0, %v0, 0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vclzb	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vclzf	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vclzg	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vclzh	%v0, %v0
+
+	vclzb	%v0, %v0
+	vclzf	%v0, %v0
+	vclzg	%v0, %v0
+	vclzh	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vctzb	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vctzf	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vctzg	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vctzh	%v0, %v0
+
+	vctzb	%v0, %v0
+	vctzf	%v0, %v0
+	vctzg	%v0, %v0
+	vctzh	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vecb	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vecf	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vecg	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vech	%v0, %v0
+
+	vecb	%v0, %v0
+	vecf	%v0, %v0
+	vecg	%v0, %v0
+	vech	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: verimb	%v0, %v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: verimf	%v0, %v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: verimg	%v0, %v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: verimh	%v0, %v0, %v0, 0
+
+	verimb	%v0, %v0, %v0, 0
+	verimf	%v0, %v0, %v0, 0
+	verimg	%v0, %v0, %v0, 0
+	verimh	%v0, %v0, %v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: veclb	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: veclf	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: veclg	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: veclh	%v0, %v0
+
+	veclb	%v0, %v0
+	veclf	%v0, %v0
+	veclg	%v0, %v0
+	veclh	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: verllvb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: verllvf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: verllvg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: verllvh	%v0, %v0, %v0
+
+	verllvb	%v0, %v0, %v0
+	verllvf	%v0, %v0, %v0
+	verllvg	%v0, %v0, %v0
+	verllvh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: verllb	%v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: verllf	%v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: verllg	%v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: verllh	%v0, %v0, 0
+
+	verllb	%v0, %v0, 0
+	verllf	%v0, %v0, 0
+	verllg	%v0, %v0, 0
+	verllh	%v0, %v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: veslvb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: veslvf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: veslvg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: veslvh	%v0, %v0, %v0
+
+	veslvb	%v0, %v0, %v0
+	veslvf	%v0, %v0, %v0
+	veslvg	%v0, %v0, %v0
+	veslvh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: veslb	%v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: veslf	%v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: veslg	%v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: veslh	%v0, %v0, 0
+
+	veslb	%v0, %v0, 0
+	veslf	%v0, %v0, 0
+	veslg	%v0, %v0, 0
+	veslh	%v0, %v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesravb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesravf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesravg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesravh	%v0, %v0, %v0
+
+	vesravb	%v0, %v0, %v0
+	vesravf	%v0, %v0, %v0
+	vesravg	%v0, %v0, %v0
+	vesravh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesrab	%v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesraf	%v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesrag	%v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesrah	%v0, %v0, 0
+
+	vesrab	%v0, %v0, 0
+	vesraf	%v0, %v0, 0
+	vesrag	%v0, %v0, 0
+	vesrah	%v0, %v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesrlvb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesrlvf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesrlvg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesrlvh	%v0, %v0, %v0
+
+	vesrlvb	%v0, %v0, %v0
+	vesrlvf	%v0, %v0, %v0
+	vesrlvg	%v0, %v0, %v0
+	vesrlvh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesrlb	%v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesrlf	%v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesrlg	%v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vesrlh	%v0, %v0, 0
+
+	vesrlb	%v0, %v0, 0
+	vesrlf	%v0, %v0, 0
+	vesrlg	%v0, %v0, 0
+	vesrlh	%v0, %v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfadb	%v0, %v0, %v0
+
+	vfadb	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfcedb	%v0, %v0, %v0
+#CHECK: vfcedbs	%v0, %v0, %v0
+
+	vfcedb	%v0, %v0, %v0
+	vfcedbs	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfchdb	%v0, %v0, %v0
+#CHECK: vfchdbs	%v0, %v0, %v0
+
+	vfchdb	%v0, %v0, %v0
+	vfchdbs	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfddb	%v0, %v0, %v0
+
+	vfddb	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfaeb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfaezb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfaebs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfaezbs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfaeh	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfaezh	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfaehs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfaezhs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfaef	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfaezf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfaefs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfaezfs	%v0, %v0, %v0
+
+	vfaeb	%v0, %v0, %v0
+	vfaezb	%v0, %v0, %v0
+	vfaebs	%v0, %v0, %v0
+	vfaezbs	%v0, %v0, %v0
+	vfaeh	%v0, %v0, %v0
+	vfaezh	%v0, %v0, %v0
+	vfaehs	%v0, %v0, %v0
+	vfaezhs	%v0, %v0, %v0
+	vfaef	%v0, %v0, %v0
+	vfaezf	%v0, %v0, %v0
+	vfaefs	%v0, %v0, %v0
+	vfaezfs	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfeeb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfeezb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfeebs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfeezbs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfeeh	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfeezh	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfeehs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfeezhs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfeef	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfeezf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfeefs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfeezfs	%v0, %v0, %v0
+
+	vfeeb	%v0, %v0, %v0
+	vfeezb	%v0, %v0, %v0
+	vfeebs	%v0, %v0, %v0
+	vfeezbs	%v0, %v0, %v0
+	vfeeh	%v0, %v0, %v0
+	vfeezh	%v0, %v0, %v0
+	vfeehs	%v0, %v0, %v0
+	vfeezhs	%v0, %v0, %v0
+	vfeef	%v0, %v0, %v0
+	vfeezf	%v0, %v0, %v0
+	vfeefs	%v0, %v0, %v0
+	vfeezfs	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfeneb   %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfenezb  %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfenebs  %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfenezbs %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfeneh   %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfenezh  %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfenehs  %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfenezhs %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfenef   %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfenezf  %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfenefs  %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfenezfs %v0, %v0, %v0
+
+	vfeneb   %v0, %v0, %v0
+	vfenezb  %v0, %v0, %v0
+	vfenebs  %v0, %v0, %v0
+	vfenezbs %v0, %v0, %v0
+	vfeneh   %v0, %v0, %v0
+	vfenezh  %v0, %v0, %v0
+	vfenehs  %v0, %v0, %v0
+	vfenezhs %v0, %v0, %v0
+	vfenef   %v0, %v0, %v0
+	vfenezf  %v0, %v0, %v0
+	vfenefs  %v0, %v0, %v0
+	vfenezfs %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfidb	%v0, %v0, 0, 0
+
+	vfidb	%v0, %v0, 0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vistrb	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vistrbs	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vistrh	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vistrhs	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vistrf	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vistrfs	%v0, %v0
+
+	vistrb	%v0, %v0
+	vistrbs	%v0, %v0
+	vistrh	%v0, %v0
+	vistrhs	%v0, %v0
+	vistrf	%v0, %v0
+	vistrfs	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vflcdb	%v0, %v0
+
+	vflcdb	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vflndb	%v0, %v0
+
+	vflndb	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vflpdb	%v0, %v0
+
+	vflpdb	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfmadb	%v0, %v0, %v0, %v0
+
+	vfmadb	%v0, %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfmdb	%v0, %v0, %v0
+
+	vfmdb	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfmsdb	%v0, %v0, %v0, %v0
+
+	vfmsdb	%v0, %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfsdb	%v0, %v0, %v0
+
+	vfsdb	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vfsqdb	%v0, %v0
+
+	vfsqdb	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vftcidb	%v0, %v0, 0
+
+	vftcidb	%v0, %v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vgbm	%v0, 0
+
+	vgbm	%v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vgef	%v0, 0(%v0, %r1), 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vgeg	%v0, 0(%v0, %r1), 0
+
+	vgef	%v0, 0(%v0, %r1), 0
+	vgeg	%v0, 0(%v0, %r1), 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vgfmab	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vgfmaf	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vgfmag	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vgfmah	%v0, %v0, %v0, %v0
+
+	vgfmab	%v0, %v0, %v0, %v0
+	vgfmaf	%v0, %v0, %v0, %v0
+	vgfmag	%v0, %v0, %v0, %v0
+	vgfmah	%v0, %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vgfmb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vgfmf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vgfmg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vgfmh	%v0, %v0, %v0
+
+	vgfmb	%v0, %v0, %v0
+	vgfmf	%v0, %v0, %v0
+	vgfmg	%v0, %v0, %v0
+	vgfmh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vgmb	%v0, 0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vgmf	%v0, 0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vgmg	%v0, 0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vgmh	%v0, 0, 0
+
+	vgmb	%v0, 0, 0
+	vgmf	%v0, 0, 0
+	vgmg	%v0, 0, 0
+	vgmh	%v0, 0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vl	%v0, 0
+
+	vl	%v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlbb	%v0, 0, 0
+
+	vlbb	%v0, 0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlcb	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlcf	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlcg	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlch	%v0, %v0
+
+	vlcb	%v0, %v0
+	vlcf	%v0, %v0
+	vlcg	%v0, %v0
+	vlch	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vldeb	%v0, %v0
+
+	vldeb	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vleb	%v0, 0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlef	%v0, 0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vleg	%v0, 0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vleh	%v0, 0, 0
+
+	vleb	%v0, 0, 0
+	vlef	%v0, 0, 0
+	vleg	%v0, 0, 0
+	vleh	%v0, 0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vledb	%v0, %v0, 0, 0
+
+	vledb	%v0, %v0, 0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vleib	%v0, 0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vleif	%v0, 0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vleig	%v0, 0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vleih	%v0, 0, 0
+
+	vleib	%v0, 0, 0
+	vleif	%v0, 0, 0
+	vleig	%v0, 0, 0
+	vleih	%v0, 0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlgvb	%r0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlgvf	%r0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlgvg	%r0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlgvh	%r0, %v0, 0
+
+	vlgvb	%r0, %v0, 0
+	vlgvf	%r0, %v0, 0
+	vlgvg	%r0, %v0, 0
+	vlgvh	%r0, %v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vll	%v0, %r0, 0
+
+	vll	%v0, %r0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vllezb	%v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vllezf	%v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vllezg	%v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vllezh	%v0, 0
+
+	vllezb	%v0, 0
+	vllezf	%v0, 0
+	vllezg	%v0, 0
+	vllezh	%v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlm	%v0, %v0, 0
+
+	vlm	%v0, %v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlpb	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlpf	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlpg	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlph	%v0, %v0
+
+	vlpb	%v0, %v0
+	vlpf	%v0, %v0
+	vlpg	%v0, %v0
+	vlph	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlr	%v0, %v0
+
+	vlr	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlrepb	%v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlrepf	%v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlrepg	%v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlreph	%v0, 0
+
+	vlrepb	%v0, 0
+	vlrepf	%v0, 0
+	vlrepg	%v0, 0
+	vlreph	%v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlvgb	%v0, %r0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlvgf	%v0, %r0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlvgg	%v0, %r0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlvgh	%v0, %r0, 0
+
+	vlvgb	%v0, %r0, 0
+	vlvgf	%v0, %r0, 0
+	vlvgg	%v0, %r0, 0
+	vlvgh	%v0, %r0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vlvgp	%v0, %r0, %r0
+
+	vlvgp	%v0, %r0, %r0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmaeb	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmaef	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmaeh	%v0, %v0, %v0, %v0
+
+	vmaeb	%v0, %v0, %v0, %v0
+	vmaef	%v0, %v0, %v0, %v0
+	vmaeh	%v0, %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmahb	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmahf	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmahh	%v0, %v0, %v0, %v0
+
+	vmahb	%v0, %v0, %v0, %v0
+	vmahf	%v0, %v0, %v0, %v0
+	vmahh	%v0, %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmalb	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmalf	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmalhw	%v0, %v0, %v0, %v0
+
+	vmalb	%v0, %v0, %v0, %v0
+	vmalf	%v0, %v0, %v0, %v0
+	vmalhw	%v0, %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmaleb	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmalef	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmaleh	%v0, %v0, %v0, %v0
+
+	vmaleb	%v0, %v0, %v0, %v0
+	vmalef	%v0, %v0, %v0, %v0
+	vmaleh	%v0, %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmalhb	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmalhf	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmalhh	%v0, %v0, %v0, %v0
+
+	vmalhb	%v0, %v0, %v0, %v0
+	vmalhf	%v0, %v0, %v0, %v0
+	vmalhh	%v0, %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmalob	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmalof	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmaloh	%v0, %v0, %v0, %v0
+
+	vmalob	%v0, %v0, %v0, %v0
+	vmalof	%v0, %v0, %v0, %v0
+	vmaloh	%v0, %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmaob	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmaof	%v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmaoh	%v0, %v0, %v0, %v0
+
+	vmaob	%v0, %v0, %v0, %v0
+	vmaof	%v0, %v0, %v0, %v0
+	vmaoh	%v0, %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmeb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmef	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmeh	%v0, %v0, %v0
+
+	vmeb	%v0, %v0, %v0
+	vmef	%v0, %v0, %v0
+	vmeh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmhb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmhf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmhh	%v0, %v0, %v0
+
+	vmhb	%v0, %v0, %v0
+	vmhf	%v0, %v0, %v0
+	vmhh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmlb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmlf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmlh	%v0, %v0, %v0
+
+	vmlb	%v0, %v0, %v0
+	vmlf	%v0, %v0, %v0
+	vmlh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmleb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmlef	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmleh	%v0, %v0, %v0
+
+	vmleb	%v0, %v0, %v0
+	vmlef	%v0, %v0, %v0
+	vmleh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmlhb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmlhf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmlhh	%v0, %v0, %v0
+
+	vmlhb	%v0, %v0, %v0
+	vmlhf	%v0, %v0, %v0
+	vmlhh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmlob	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmlof	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmloh	%v0, %v0, %v0
+
+	vmlob	%v0, %v0, %v0
+	vmlof	%v0, %v0, %v0
+	vmloh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmnb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmnf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmng	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmnh	%v0, %v0, %v0
+
+	vmnb	%v0, %v0, %v0
+	vmnf	%v0, %v0, %v0
+	vmng	%v0, %v0, %v0
+	vmnh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmnlb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmnlf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmnlg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmnlh	%v0, %v0, %v0
+
+	vmnlb	%v0, %v0, %v0
+	vmnlf	%v0, %v0, %v0
+	vmnlg	%v0, %v0, %v0
+	vmnlh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmob	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmof	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmoh	%v0, %v0, %v0
+
+	vmob	%v0, %v0, %v0
+	vmof	%v0, %v0, %v0
+	vmoh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmrhb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmrhf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmrhg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmrhh	%v0, %v0, %v0
+
+	vmrhb	%v0, %v0, %v0
+	vmrhf	%v0, %v0, %v0
+	vmrhg	%v0, %v0, %v0
+	vmrhh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmrlb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmrlf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmrlg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmrlh	%v0, %v0, %v0
+
+	vmrlb	%v0, %v0, %v0
+	vmrlf	%v0, %v0, %v0
+	vmrlg	%v0, %v0, %v0
+	vmrlh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmxb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmxf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmxg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmxh	%v0, %v0, %v0
+
+	vmxb	%v0, %v0, %v0
+	vmxf	%v0, %v0, %v0
+	vmxg	%v0, %v0, %v0
+	vmxh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmxlb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmxlf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmxlg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vmxlh	%v0, %v0, %v0
+
+	vmxlb	%v0, %v0, %v0
+	vmxlf	%v0, %v0, %v0
+	vmxlg	%v0, %v0, %v0
+	vmxlh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vn	%v0, %v0, %v0
+
+	vn	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vnc	%v0, %v0, %v0
+
+	vnc	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vno	%v0, %v0, %v0
+
+	vno	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vo	%v0, %v0, %v0
+
+	vo	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vone	%v0
+
+	vone	%v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpdi	%v0, %v0, %v0, 0
+
+	vpdi	%v0, %v0, %v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vperm	%v0, %v0, %v0, %v0
+
+	vperm	%v0, %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpkf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpkg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpkh	%v0, %v0, %v0
+
+	vpkf	%v0, %v0, %v0
+	vpkg	%v0, %v0, %v0
+	vpkh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpksf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpksg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpksh	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpksfs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpksgs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpkshs	%v0, %v0, %v0
+
+	vpksf	%v0, %v0, %v0
+	vpksg	%v0, %v0, %v0
+	vpksh	%v0, %v0, %v0
+	vpksfs	%v0, %v0, %v0
+	vpksgs	%v0, %v0, %v0
+	vpkshs	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpklsf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpklsg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpklsh	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpklsfs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpklsgs	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpklshs	%v0, %v0, %v0
+
+	vpklsf	%v0, %v0, %v0
+	vpklsg	%v0, %v0, %v0
+	vpklsh	%v0, %v0, %v0
+	vpklsfs	%v0, %v0, %v0
+	vpklsgs	%v0, %v0, %v0
+	vpklshs	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vpopct	%v0, %v0
+
+	vpopct	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vrepb	%v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vrepf	%v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vrepg	%v0, %v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vreph	%v0, %v0, 0
+
+	vrepb	%v0, %v0, 0
+	vrepf	%v0, %v0, 0
+	vrepg	%v0, %v0, 0
+	vreph	%v0, %v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vrepib	%v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vrepif	%v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vrepig	%v0, 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vrepih	%v0, 0
+
+	vrepib	%v0, 0
+	vrepif	%v0, 0
+	vrepig	%v0, 0
+	vrepih	%v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsg	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsh	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsq	%v0, %v0, %v0
+
+	vsb	%v0, %v0, %v0
+	vsf	%v0, %v0, %v0
+	vsg	%v0, %v0, %v0
+	vsh	%v0, %v0, %v0
+	vsq	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsbcbiq	%v0, %v0, %v0
+
+	vsbcbiq	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsbiq	%v0, %v0, %v0
+
+	vsbiq	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vscbib	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vscbif	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vscbig	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vscbih	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vscbiq	%v0, %v0, %v0
+
+	vscbib	%v0, %v0, %v0
+	vscbif	%v0, %v0, %v0
+	vscbig	%v0, %v0, %v0
+	vscbih	%v0, %v0, %v0
+	vscbiq	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vscef	%v0, 0(%v0, %r1), 0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsceg	%v0, 0(%v0, %r1), 0
+
+	vscef	%v0, 0(%v0, %r1), 0
+	vsceg	%v0, 0(%v0, %r1), 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsegb	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsegf	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsegh	%v0, %v0
+
+	vsegb	%v0, %v0
+	vsegf	%v0, %v0
+	vsegh	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsel	%v0, %v0, %v0, %v0
+
+	vsel	%v0, %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsl	%v0, %v0, %v0
+
+	vsl	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vslb	%v0, %v0, %v0
+
+	vslb	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsldb	%v0, %v0, %v0, 0
+
+	vsldb	%v0, %v0, %v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsra	%v0, %v0, %v0
+
+	vsra	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsrab	%v0, %v0, %v0
+
+	vsrab	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsrl	%v0, %v0, %v0
+
+	vsrl	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsrlb	%v0, %v0, %v0
+
+	vsrlb	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vst	%v0, 0
+
+	vst	%v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vstl	%v0, %r0, 0
+
+	vstl	%v0, %r0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vstm	%v0, %v0, 0
+
+	vstm	%v0, %v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vstrcb   %v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vstrczb  %v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vstrcbs  %v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vstrczbs %v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vstrch   %v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vstrczh  %v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vstrchs  %v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vstrczhs %v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vstrcf   %v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vstrczf  %v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vstrcfs  %v0, %v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vstrczfs %v0, %v0, %v0, %v0
+
+        vstrcb   %v0, %v0, %v0, %v0
+        vstrczb  %v0, %v0, %v0, %v0
+        vstrcbs  %v0, %v0, %v0, %v0
+        vstrczbs %v0, %v0, %v0, %v0
+        vstrch   %v0, %v0, %v0, %v0
+        vstrczh  %v0, %v0, %v0, %v0
+        vstrchs  %v0, %v0, %v0, %v0
+        vstrczhs %v0, %v0, %v0, %v0
+        vstrcf   %v0, %v0, %v0, %v0
+        vstrczf  %v0, %v0, %v0, %v0
+        vstrcfs  %v0, %v0, %v0, %v0
+        vstrczfs %v0, %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsumgh	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsumgf	%v0, %v0, %v0
+
+	vsumgh	%v0, %v0, %v0
+	vsumgf	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsumqf	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsumqg	%v0, %v0, %v0
+
+	vsumqf	%v0, %v0, %v0
+	vsumqg	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsumb	%v0, %v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vsumh	%v0, %v0, %v0
+
+	vsumb	%v0, %v0, %v0
+	vsumh	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vtm	%v0, %v0
+
+	vtm	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vuphb	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vuphf	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vuphh	%v0, %v0
+
+	vuphb	%v0, %v0
+	vuphf	%v0, %v0
+	vuphh	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vuplhb	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vuplhf	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vuplhh	%v0, %v0
+
+	vuplhb	%v0, %v0
+	vuplhf	%v0, %v0
+	vuplhh	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vuplb	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vuplf	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vuplhw	%v0, %v0
+
+	vuplb	%v0, %v0
+	vuplf	%v0, %v0
+	vuplhw	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vupllb	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vupllf	%v0, %v0
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vupllh	%v0, %v0
+
+	vupllb	%v0, %v0
+	vupllf	%v0, %v0
+	vupllh	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vx	%v0, %v0, %v0
+
+	vx	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: vzero	%v0
+
+	vzero	%v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wcdgb	%v0, %v0, 0, 0
+
+	wcdgb	%v0, %v0, 0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wcdlgb	%v0, %v0, 0, 0
+
+	wcdlgb	%v0, %v0, 0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wcgdb	%v0, %v0, 0, 0
+
+	wcgdb	%v0, %v0, 0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wclgdb	%v0, %v0, 0, 0
+
+	wclgdb	%v0, %v0, 0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wfadb	%v0, %v0, %v0
+
+	wfadb	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wfcdb	%v0, %v0
+
+	wfcdb	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wfcedb	%v0, %v0, %v0
+#CHECK: wfcedbs	%v0, %v0, %v0
+
+	wfcedb	%v0, %v0, %v0
+	wfcedbs	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wfchdb	%v0, %v0, %v0
+#CHECK: wfchdbs	%v0, %v0, %v0
+
+	wfchdb	%v0, %v0, %v0
+	wfchdbs	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wfchedb	%v0, %v0, %v0
+#CHECK: wfchedbs %v0, %v0, %v0
+
+	wfchedb	%v0, %v0, %v0
+	wfchedbs %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wfddb	%v0, %v0, %v0
+
+	wfddb	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wfidb	%v0, %v0, 0, 0
+
+	wfidb	%v0, %v0, 0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wfkdb	%v0, %v0
+
+	wfkdb	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wflcdb	%v0, %v0
+
+	wflcdb	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wflndb	%v0, %v0
+
+	wflndb	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wflpdb	%v0, %v0
+
+	wflpdb	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wfmadb	%v0, %v0, %v0, %v0
+
+	wfmadb	%v0, %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wfmdb	%v0, %v0, %v0
+
+	wfmdb	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wfmsdb	%v0, %v0, %v0, %v0
+
+	wfmsdb	%v0, %v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wfsdb	%v0, %v0, %v0
+
+	wfsdb	%v0, %v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wfsqdb	%v0, %v0
+
+	wfsqdb	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wftcidb	%v0, %v0, 0
+
+	wftcidb	%v0, %v0, 0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wldeb	%v0, %v0
+
+	wldeb	%v0, %v0
+
+#CHECK: error: {{(instruction requires: vector)?}}
+#CHECK: wledb	%v0, %v0, 0, 0
+
+	wledb	%v0, %v0, 0, 0
diff --git a/test/MC/SystemZ/insn-bad.s b/test/MC/SystemZ/insn-bad.s
index a08cb34da832..0410a411167e 100644
--- a/test/MC/SystemZ/insn-bad.s
+++ b/test/MC/SystemZ/insn-bad.s
@@ -2666,6 +2666,11 @@
 	pfdrl	1, 1
 	pfdrl	1, 0x100000000
 
+#CHECK: error: {{(instruction requires: population-count)?}}
+#CHECK: popcnt	%r0, %r0
+
+	popcnt	%r0, %r0
+
 #CHECK: error: invalid operand
 #CHECK: risbg	%r0,%r0,0,0,-1
 #CHECK: error: invalid operand
diff --git a/test/MC/SystemZ/insn-good-z13.s b/test/MC/SystemZ/insn-good-z13.s
new file mode 100644
index 000000000000..621b946d19dd
--- /dev/null
+++ b/test/MC/SystemZ/insn-good-z13.s
@@ -0,0 +1,5039 @@
+# For z13 and above.
+# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z13 -show-encoding %s \
+# RUN:   | FileCheck %s
+
+#CHECK: lcbb    %r0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x27]
+#CHECK: lcbb    %r0, 0, 15              # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x27]
+#CHECK: lcbb    %r0, 4095, 0            # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x27]
+#CHECK: lcbb    %r0, 0(%r15), 0         # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x27]
+#CHECK: lcbb    %r0, 0(%r15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x27]
+#CHECK: lcbb    %r15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x27]
+#CHECK: lcbb    %r2, 1383(%r3,%r4), 8   # encoding: [0xe7,0x23,0x45,0x67,0x80,0x27]
+
+	lcbb	%r0, 0, 0
+	lcbb	%r0, 0, 15
+	lcbb	%r0, 4095, 0
+	lcbb	%r0, 0(%r15), 0
+	lcbb	%r0, 0(%r15,%r1), 0
+	lcbb	%r15, 0, 0
+	lcbb	%r2, 1383(%r3,%r4), 8
+
+#CHECK: vab     %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf3]
+#CHECK: vab     %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf3]
+#CHECK: vab     %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf3]
+#CHECK: vab     %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf3]
+#CHECK: vab     %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf3]
+
+	vab	%v0, %v0, %v0
+	vab	%v0, %v0, %v31
+	vab	%v0, %v31, %v0
+	vab	%v31, %v0, %v0
+	vab	%v18, %v3, %v20
+
+#CHECK: vaccb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf1]
+#CHECK: vaccb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf1]
+#CHECK: vaccb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf1]
+#CHECK: vaccb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf1]
+#CHECK: vaccb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf1]
+
+	vaccb	%v0, %v0, %v0
+	vaccb	%v0, %v0, %v31
+	vaccb	%v0, %v31, %v0
+	vaccb	%v31, %v0, %v0
+	vaccb	%v18, %v3, %v20
+
+#CHECK: vacccq  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x04,0x00,0x00,0xb9]
+#CHECK: vacccq  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x04,0x00,0xf1,0xb9]
+#CHECK: vacccq  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf4,0x00,0x02,0xb9]
+#CHECK: vacccq  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x04,0x00,0x04,0xb9]
+#CHECK: vacccq  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x04,0x00,0x08,0xb9]
+#CHECK: vacccq  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x54,0x00,0x97,0xb9]
+
+	vacccq	%v0, %v0, %v0, %v0
+	vacccq	%v0, %v0, %v0, %v31
+	vacccq	%v0, %v0, %v31, %v0
+	vacccq	%v0, %v31, %v0, %v0
+	vacccq	%v31, %v0, %v0, %v0
+	vacccq	%v13, %v17, %v21, %v25
+
+#CHECK: vaccf   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf1]
+#CHECK: vaccf   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf1]
+#CHECK: vaccf   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf1]
+#CHECK: vaccf   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf1]
+#CHECK: vaccf   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf1]
+
+	vaccf	%v0, %v0, %v0
+	vaccf	%v0, %v0, %v31
+	vaccf	%v0, %v31, %v0
+	vaccf	%v31, %v0, %v0
+	vaccf	%v18, %v3, %v20
+
+#CHECK: vaccg   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf1]
+#CHECK: vaccg   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf1]
+#CHECK: vaccg   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf1]
+#CHECK: vaccg   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf1]
+#CHECK: vaccg   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf1]
+
+	vaccg	%v0, %v0, %v0
+	vaccg	%v0, %v0, %v31
+	vaccg	%v0, %v31, %v0
+	vaccg	%v31, %v0, %v0
+	vaccg	%v18, %v3, %v20
+
+#CHECK: vacch   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf1]
+#CHECK: vacch   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf1]
+#CHECK: vacch   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf1]
+#CHECK: vacch   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf1]
+#CHECK: vacch   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf1]
+
+	vacch	%v0, %v0, %v0
+	vacch	%v0, %v0, %v31
+	vacch	%v0, %v31, %v0
+	vacch	%v31, %v0, %v0
+	vacch	%v18, %v3, %v20
+
+#CHECK: vaccq   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x40,0xf1]
+#CHECK: vaccq   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x42,0xf1]
+#CHECK: vaccq   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x44,0xf1]
+#CHECK: vaccq   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x48,0xf1]
+#CHECK: vaccq   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x4a,0xf1]
+
+	vaccq	%v0, %v0, %v0
+	vaccq	%v0, %v0, %v31
+	vaccq	%v0, %v31, %v0
+	vaccq	%v31, %v0, %v0
+	vaccq	%v18, %v3, %v20
+
+#CHECK: vacq    %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x04,0x00,0x00,0xbb]
+#CHECK: vacq    %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x04,0x00,0xf1,0xbb]
+#CHECK: vacq    %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf4,0x00,0x02,0xbb]
+#CHECK: vacq    %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x04,0x00,0x04,0xbb]
+#CHECK: vacq    %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x04,0x00,0x08,0xbb]
+#CHECK: vacq    %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x54,0x00,0x97,0xbb]
+
+	vacq	%v0, %v0, %v0, %v0
+	vacq	%v0, %v0, %v0, %v31
+	vacq	%v0, %v0, %v31, %v0
+	vacq	%v0, %v31, %v0, %v0
+	vacq	%v31, %v0, %v0, %v0
+	vacq	%v13, %v17, %v21, %v25
+
+#CHECK: vaf     %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf3]
+#CHECK: vaf     %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf3]
+#CHECK: vaf     %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf3]
+#CHECK: vaf     %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf3]
+#CHECK: vaf     %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf3]
+
+	vaf	%v0, %v0, %v0
+	vaf	%v0, %v0, %v31
+	vaf	%v0, %v31, %v0
+	vaf	%v31, %v0, %v0
+	vaf	%v18, %v3, %v20
+
+#CHECK: vag     %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf3]
+#CHECK: vag     %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf3]
+#CHECK: vag     %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf3]
+#CHECK: vag     %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf3]
+#CHECK: vag     %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf3]
+
+	vag	%v0, %v0, %v0
+	vag	%v0, %v0, %v31
+	vag	%v0, %v31, %v0
+	vag	%v31, %v0, %v0
+	vag	%v18, %v3, %v20
+
+#CHECK: vah     %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf3]
+#CHECK: vah     %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf3]
+#CHECK: vah     %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf3]
+#CHECK: vah     %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf3]
+#CHECK: vah     %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf3]
+
+	vah	%v0, %v0, %v0
+	vah	%v0, %v0, %v31
+	vah	%v0, %v31, %v0
+	vah	%v31, %v0, %v0
+	vah	%v18, %v3, %v20
+
+#CHECK: vaq     %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x40,0xf3]
+#CHECK: vaq     %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x42,0xf3]
+#CHECK: vaq     %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x44,0xf3]
+#CHECK: vaq     %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x48,0xf3]
+#CHECK: vaq     %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x4a,0xf3]
+
+	vaq	%v0, %v0, %v0
+	vaq	%v0, %v0, %v31
+	vaq	%v0, %v31, %v0
+	vaq	%v31, %v0, %v0
+	vaq	%v18, %v3, %v20
+
+#CHECK: vavgb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf2]
+#CHECK: vavgb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf2]
+#CHECK: vavgb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf2]
+#CHECK: vavgb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf2]
+#CHECK: vavgb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf2]
+
+	vavgb	%v0, %v0, %v0
+	vavgb	%v0, %v0, %v31
+	vavgb	%v0, %v31, %v0
+	vavgb	%v31, %v0, %v0
+	vavgb	%v18, %v3, %v20
+
+#CHECK: vavgf   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf2]
+#CHECK: vavgf   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf2]
+#CHECK: vavgf   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf2]
+#CHECK: vavgf   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf2]
+#CHECK: vavgf   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf2]
+
+	vavgf	%v0, %v0, %v0
+	vavgf	%v0, %v0, %v31
+	vavgf	%v0, %v31, %v0
+	vavgf	%v31, %v0, %v0
+	vavgf	%v18, %v3, %v20
+
+#CHECK: vavgg   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf2]
+#CHECK: vavgg   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf2]
+#CHECK: vavgg   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf2]
+#CHECK: vavgg   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf2]
+#CHECK: vavgg   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf2]
+
+	vavgg	%v0, %v0, %v0
+	vavgg	%v0, %v0, %v31
+	vavgg	%v0, %v31, %v0
+	vavgg	%v31, %v0, %v0
+	vavgg	%v18, %v3, %v20
+
+#CHECK: vavgh   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf2]
+#CHECK: vavgh   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf2]
+#CHECK: vavgh   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf2]
+#CHECK: vavgh   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf2]
+#CHECK: vavgh   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf2]
+
+	vavgh	%v0, %v0, %v0
+	vavgh	%v0, %v0, %v31
+	vavgh	%v0, %v31, %v0
+	vavgh	%v31, %v0, %v0
+	vavgh	%v18, %v3, %v20
+
+#CHECK: vavglb  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf0]
+#CHECK: vavglb  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf0]
+#CHECK: vavglb  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf0]
+#CHECK: vavglb  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf0]
+#CHECK: vavglb  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf0]
+
+	vavglb	%v0, %v0, %v0
+	vavglb	%v0, %v0, %v31
+	vavglb	%v0, %v31, %v0
+	vavglb	%v31, %v0, %v0
+	vavglb	%v18, %v3, %v20
+
+#CHECK: vavglf  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf0]
+#CHECK: vavglf  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf0]
+#CHECK: vavglf  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf0]
+#CHECK: vavglf  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf0]
+#CHECK: vavglf  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf0]
+
+	vavglf	%v0, %v0, %v0
+	vavglf	%v0, %v0, %v31
+	vavglf	%v0, %v31, %v0
+	vavglf	%v31, %v0, %v0
+	vavglf	%v18, %v3, %v20
+
+#CHECK: vavglg  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf0]
+#CHECK: vavglg  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf0]
+#CHECK: vavglg  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf0]
+#CHECK: vavglg  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf0]
+#CHECK: vavglg  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf0]
+
+	vavglg	%v0, %v0, %v0
+	vavglg	%v0, %v0, %v31
+	vavglg	%v0, %v31, %v0
+	vavglg	%v31, %v0, %v0
+	vavglg	%v18, %v3, %v20
+
+#CHECK: vavglh  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf0]
+#CHECK: vavglh  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf0]
+#CHECK: vavglh  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf0]
+#CHECK: vavglh  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf0]
+#CHECK: vavglh  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf0]
+
+	vavglh	%v0, %v0, %v0
+	vavglh	%v0, %v0, %v31
+	vavglh	%v0, %v31, %v0
+	vavglh	%v31, %v0, %v0
+	vavglh	%v18, %v3, %v20
+
+#CHECK: vcdgb   %v0, %v0, 0, 0          # encoding: [0xe7,0x00,0x00,0x00,0x30,0xc3]
+#CHECK: vcdgb   %v0, %v0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf0,0x30,0xc3]
+#CHECK: vcdgb   %v0, %v0, 4, 0          # encoding: [0xe7,0x00,0x00,0x04,0x30,0xc3]
+#CHECK: vcdgb   %v0, %v0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc3]
+#CHECK: vcdgb   %v0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xc3]
+#CHECK: vcdgb   %v31, %v0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xc3]
+#CHECK: vcdgb   %v14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xa4,0x34,0xc3]
+
+	vcdgb	%v0, %v0, 0, 0
+	vcdgb	%v0, %v0, 0, 15
+	vcdgb	%v0, %v0, 4, 0
+	vcdgb	%v0, %v0, 12, 0
+	vcdgb	%v0, %v31, 0, 0
+	vcdgb	%v31, %v0, 0, 0
+	vcdgb	%v14, %v17, 4, 10
+
+#CHECK: vcdlgb  %v0, %v0, 0, 0          # encoding: [0xe7,0x00,0x00,0x00,0x30,0xc1]
+#CHECK: vcdlgb  %v0, %v0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf0,0x30,0xc1]
+#CHECK: vcdlgb  %v0, %v0, 4, 0          # encoding: [0xe7,0x00,0x00,0x04,0x30,0xc1]
+#CHECK: vcdlgb  %v0, %v0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc1]
+#CHECK: vcdlgb  %v0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xc1]
+#CHECK: vcdlgb  %v31, %v0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xc1]
+#CHECK: vcdlgb  %v14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xa4,0x34,0xc1]
+
+	vcdlgb	%v0, %v0, 0, 0
+	vcdlgb	%v0, %v0, 0, 15
+	vcdlgb	%v0, %v0, 4, 0
+	vcdlgb	%v0, %v0, 12, 0
+	vcdlgb	%v0, %v31, 0, 0
+	vcdlgb	%v31, %v0, 0, 0
+	vcdlgb	%v14, %v17, 4, 10
+
+#CHECK: vcksm   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x66]
+#CHECK: vcksm   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x66]
+#CHECK: vcksm   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x66]
+#CHECK: vcksm   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x66]
+#CHECK: vcksm   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x66]
+
+	vcksm	%v0, %v0, %v0
+	vcksm	%v0, %v0, %v31
+	vcksm	%v0, %v31, %v0
+	vcksm	%v31, %v0, %v0
+	vcksm	%v18, %v3, %v20
+
+#CHECK: vceqb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf8]
+#CHECK: vceqb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf8]
+#CHECK: vceqb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf8]
+#CHECK: vceqb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf8]
+#CHECK: vceqb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf8]
+#CHECK: vceqbs  %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x04,0xf8]
+
+	vceqb	%v0, %v0, %v0
+	vceqb	%v0, %v0, %v31
+	vceqb	%v0, %v31, %v0
+	vceqb	%v31, %v0, %v0
+	vceqb	%v18, %v3, %v20
+	vceqbs	%v5, %v22, %v7
+
+#CHECK: vceqf   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf8]
+#CHECK: vceqf   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf8]
+#CHECK: vceqf   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf8]
+#CHECK: vceqf   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf8]
+#CHECK: vceqf   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf8]
+#CHECK: vceqfs  %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x24,0xf8]
+
+	vceqf	%v0, %v0, %v0
+	vceqf	%v0, %v0, %v31
+	vceqf	%v0, %v31, %v0
+	vceqf	%v31, %v0, %v0
+	vceqf	%v18, %v3, %v20
+	vceqfs	%v5, %v22, %v7
+
+#CHECK: vceqg   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf8]
+#CHECK: vceqg   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf8]
+#CHECK: vceqg   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf8]
+#CHECK: vceqg   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf8]
+#CHECK: vceqg   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf8]
+#CHECK: vceqgs  %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x34,0xf8]
+
+	vceqg	%v0, %v0, %v0
+	vceqg	%v0, %v0, %v31
+	vceqg	%v0, %v31, %v0
+	vceqg	%v31, %v0, %v0
+	vceqg	%v18, %v3, %v20
+	vceqgs	%v5, %v22, %v7
+
+#CHECK: vceqh   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf8]
+#CHECK: vceqh   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf8]
+#CHECK: vceqh   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf8]
+#CHECK: vceqh   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf8]
+#CHECK: vceqh   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf8]
+#CHECK: vceqhs  %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x14,0xf8]
+
+	vceqh	%v0, %v0, %v0
+	vceqh	%v0, %v0, %v31
+	vceqh	%v0, %v31, %v0
+	vceqh	%v31, %v0, %v0
+	vceqh	%v18, %v3, %v20
+	vceqhs	%v5, %v22, %v7
+
+#CHECK: vcgdb   %v0, %v0, 0, 0          # encoding: [0xe7,0x00,0x00,0x00,0x30,0xc2]
+#CHECK: vcgdb   %v0, %v0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf0,0x30,0xc2]
+#CHECK: vcgdb   %v0, %v0, 4, 0          # encoding: [0xe7,0x00,0x00,0x04,0x30,0xc2]
+#CHECK: vcgdb   %v0, %v0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc2]
+#CHECK: vcgdb   %v0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xc2]
+#CHECK: vcgdb   %v31, %v0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xc2]
+#CHECK: vcgdb   %v14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xa4,0x34,0xc2]
+
+	vcgdb	%v0, %v0, 0, 0
+	vcgdb	%v0, %v0, 0, 15
+	vcgdb	%v0, %v0, 4, 0
+	vcgdb	%v0, %v0, 12, 0
+	vcgdb	%v0, %v31, 0, 0
+	vcgdb	%v31, %v0, 0, 0
+	vcgdb	%v14, %v17, 4, 10
+
+#CHECK: vchb    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xfb]
+#CHECK: vchb    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xfb]
+#CHECK: vchb    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xfb]
+#CHECK: vchb    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xfb]
+#CHECK: vchb    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xfb]
+#CHECK: vchbs   %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x04,0xfb]
+
+	vchb	%v0, %v0, %v0
+	vchb	%v0, %v0, %v31
+	vchb	%v0, %v31, %v0
+	vchb	%v31, %v0, %v0
+	vchb	%v18, %v3, %v20
+	vchbs	%v5, %v22, %v7
+
+#CHECK: vchf    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xfb]
+#CHECK: vchf    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xfb]
+#CHECK: vchf    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xfb]
+#CHECK: vchf    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xfb]
+#CHECK: vchf    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xfb]
+#CHECK: vchfs   %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x24,0xfb]
+
+	vchf	%v0, %v0, %v0
+	vchf	%v0, %v0, %v31
+	vchf	%v0, %v31, %v0
+	vchf	%v31, %v0, %v0
+	vchf	%v18, %v3, %v20
+	vchfs	%v5, %v22, %v7
+
+#CHECK: vchg    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xfb]
+#CHECK: vchg    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xfb]
+#CHECK: vchg    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xfb]
+#CHECK: vchg    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xfb]
+#CHECK: vchg    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xfb]
+#CHECK: vchgs   %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x34,0xfb]
+
+	vchg	%v0, %v0, %v0
+	vchg	%v0, %v0, %v31
+	vchg	%v0, %v31, %v0
+	vchg	%v31, %v0, %v0
+	vchg	%v18, %v3, %v20
+	vchgs	%v5, %v22, %v7
+
+#CHECK: vchh    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xfb]
+#CHECK: vchh    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xfb]
+#CHECK: vchh    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xfb]
+#CHECK: vchh    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xfb]
+#CHECK: vchh    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xfb]
+#CHECK: vchhs   %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x14,0xfb]
+
+	vchh	%v0, %v0, %v0
+	vchh	%v0, %v0, %v31
+	vchh	%v0, %v31, %v0
+	vchh	%v31, %v0, %v0
+	vchh	%v18, %v3, %v20
+	vchhs	%v5, %v22, %v7
+
+#CHECK: vchlb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf9]
+#CHECK: vchlb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf9]
+#CHECK: vchlb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf9]
+#CHECK: vchlb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf9]
+#CHECK: vchlb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf9]
+#CHECK: vchlbs  %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x04,0xf9]
+
+	vchlb	%v0, %v0, %v0
+	vchlb	%v0, %v0, %v31
+	vchlb	%v0, %v31, %v0
+	vchlb	%v31, %v0, %v0
+	vchlb	%v18, %v3, %v20
+	vchlbs	%v5, %v22, %v7
+
+#CHECK: vchlf   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf9]
+#CHECK: vchlf   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf9]
+#CHECK: vchlf   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf9]
+#CHECK: vchlf   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf9]
+#CHECK: vchlf   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf9]
+#CHECK: vchlfs  %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x24,0xf9]
+
+	vchlf	%v0, %v0, %v0
+	vchlf	%v0, %v0, %v31
+	vchlf	%v0, %v31, %v0
+	vchlf	%v31, %v0, %v0
+	vchlf	%v18, %v3, %v20
+	vchlfs	%v5, %v22, %v7
+
+#CHECK: vchlg   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf9]
+#CHECK: vchlg   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf9]
+#CHECK: vchlg   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf9]
+#CHECK: vchlg   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf9]
+#CHECK: vchlg   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf9]
+#CHECK: vchlgs  %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x34,0xf9]
+
+	vchlg	%v0, %v0, %v0
+	vchlg	%v0, %v0, %v31
+	vchlg	%v0, %v31, %v0
+	vchlg	%v31, %v0, %v0
+	vchlg	%v18, %v3, %v20
+	vchlgs	%v5, %v22, %v7
+
+#CHECK: vchlh   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf9]
+#CHECK: vchlh   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf9]
+#CHECK: vchlh   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf9]
+#CHECK: vchlh   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf9]
+#CHECK: vchlh   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf9]
+#CHECK: vchlhs  %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x14,0xf9]
+
+	vchlh	%v0, %v0, %v0
+	vchlh	%v0, %v0, %v31
+	vchlh	%v0, %v31, %v0
+	vchlh	%v31, %v0, %v0
+	vchlh	%v18, %v3, %v20
+	vchlhs	%v5, %v22, %v7
+
+#CHECK: vclgdb  %v0, %v0, 0, 0          # encoding: [0xe7,0x00,0x00,0x00,0x30,0xc0]
+#CHECK: vclgdb  %v0, %v0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf0,0x30,0xc0]
+#CHECK: vclgdb  %v0, %v0, 4, 0          # encoding: [0xe7,0x00,0x00,0x04,0x30,0xc0]
+#CHECK: vclgdb  %v0, %v0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc0]
+#CHECK: vclgdb  %v0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xc0]
+#CHECK: vclgdb  %v31, %v0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xc0]
+#CHECK: vclgdb  %v14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xa4,0x34,0xc0]
+
+	vclgdb	%v0, %v0, 0, 0
+	vclgdb	%v0, %v0, 0, 15
+	vclgdb	%v0, %v0, 4, 0
+	vclgdb	%v0, %v0, 12, 0
+	vclgdb	%v0, %v31, 0, 0
+	vclgdb	%v31, %v0, 0, 0
+	vclgdb	%v14, %v17, 4, 10
+
+#CHECK: vclzb   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x00,0x53]
+#CHECK: vclzb   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x53]
+#CHECK: vclzb   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x53]
+#CHECK: vclzb   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x53]
+#CHECK: vclzb   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x53]
+#CHECK: vclzb   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x04,0x53]
+
+	vclzb	%v0, %v0
+	vclzb	%v0, %v15
+	vclzb	%v0, %v31
+	vclzb	%v15, %v0
+	vclzb	%v31, %v0
+	vclzb	%v14, %v17
+
+#CHECK: vclzf   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x20,0x53]
+#CHECK: vclzf   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x53]
+#CHECK: vclzf   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x53]
+#CHECK: vclzf   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x53]
+#CHECK: vclzf   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x53]
+#CHECK: vclzf   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x24,0x53]
+
+	vclzf	%v0, %v0
+	vclzf	%v0, %v15
+	vclzf	%v0, %v31
+	vclzf	%v15, %v0
+	vclzf	%v31, %v0
+	vclzf	%v14, %v17
+
+#CHECK: vclzg   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x30,0x53]
+#CHECK: vclzg   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x53]
+#CHECK: vclzg   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x53]
+#CHECK: vclzg   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x53]
+#CHECK: vclzg   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x53]
+#CHECK: vclzg   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x34,0x53]
+
+	vclzg	%v0, %v0
+	vclzg	%v0, %v15
+	vclzg	%v0, %v31
+	vclzg	%v15, %v0
+	vclzg	%v31, %v0
+	vclzg	%v14, %v17
+
+#CHECK: vclzh   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x10,0x53]
+#CHECK: vclzh   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x53]
+#CHECK: vclzh   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x53]
+#CHECK: vclzh   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x53]
+#CHECK: vclzh   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x53]
+#CHECK: vclzh   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x14,0x53]
+
+	vclzh	%v0, %v0
+	vclzh	%v0, %v15
+	vclzh	%v0, %v31
+	vclzh	%v15, %v0
+	vclzh	%v31, %v0
+	vclzh	%v14, %v17
+
+#CHECK: vctzb   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x00,0x52]
+#CHECK: vctzb   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x52]
+#CHECK: vctzb   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x52]
+#CHECK: vctzb   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x52]
+#CHECK: vctzb   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x52]
+#CHECK: vctzb   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x04,0x52]
+
+	vctzb	%v0, %v0
+	vctzb	%v0, %v15
+	vctzb	%v0, %v31
+	vctzb	%v15, %v0
+	vctzb	%v31, %v0
+	vctzb	%v14, %v17
+
+#CHECK: vctzf   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x20,0x52]
+#CHECK: vctzf   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x52]
+#CHECK: vctzf   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x52]
+#CHECK: vctzf   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x52]
+#CHECK: vctzf   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x52]
+#CHECK: vctzf   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x24,0x52]
+
+	vctzf	%v0, %v0
+	vctzf	%v0, %v15
+	vctzf	%v0, %v31
+	vctzf	%v15, %v0
+	vctzf	%v31, %v0
+	vctzf	%v14, %v17
+
+#CHECK: vctzg   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x30,0x52]
+#CHECK: vctzg   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x52]
+#CHECK: vctzg   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x52]
+#CHECK: vctzg   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x52]
+#CHECK: vctzg   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x52]
+#CHECK: vctzg   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x34,0x52]
+
+	vctzg	%v0, %v0
+	vctzg	%v0, %v15
+	vctzg	%v0, %v31
+	vctzg	%v15, %v0
+	vctzg	%v31, %v0
+	vctzg	%v14, %v17
+
+#CHECK: vctzh   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x10,0x52]
+#CHECK: vctzh   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x52]
+#CHECK: vctzh   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x52]
+#CHECK: vctzh   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x52]
+#CHECK: vctzh   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x52]
+#CHECK: vctzh   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x14,0x52]
+
+	vctzh	%v0, %v0
+	vctzh	%v0, %v15
+	vctzh	%v0, %v31
+	vctzh	%v15, %v0
+	vctzh	%v31, %v0
+	vctzh	%v14, %v17
+
+#CHECK: vecb    %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x00,0xdb]
+#CHECK: vecb    %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xdb]
+#CHECK: vecb    %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xdb]
+#CHECK: vecb    %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xdb]
+#CHECK: vecb    %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xdb]
+#CHECK: vecb    %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xdb]
+
+	vecb	%v0, %v0
+	vecb	%v0, %v15
+	vecb	%v0, %v31
+	vecb	%v15, %v0
+	vecb	%v31, %v0
+	vecb	%v14, %v17
+
+#CHECK: vecf    %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x20,0xdb]
+#CHECK: vecf    %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xdb]
+#CHECK: vecf    %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xdb]
+#CHECK: vecf    %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xdb]
+#CHECK: vecf    %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xdb]
+#CHECK: vecf    %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xdb]
+
+	vecf	%v0, %v0
+	vecf	%v0, %v15
+	vecf	%v0, %v31
+	vecf	%v15, %v0
+	vecf	%v31, %v0
+	vecf	%v14, %v17
+
+#CHECK: vecg    %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x30,0xdb]
+#CHECK: vecg    %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xdb]
+#CHECK: vecg    %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xdb]
+#CHECK: vecg    %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xdb]
+#CHECK: vecg    %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xdb]
+#CHECK: vecg    %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xdb]
+
+	vecg	%v0, %v0
+	vecg	%v0, %v15
+	vecg	%v0, %v31
+	vecg	%v15, %v0
+	vecg	%v31, %v0
+	vecg	%v14, %v17
+
+#CHECK: vech    %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x10,0xdb]
+#CHECK: vech    %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xdb]
+#CHECK: vech    %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xdb]
+#CHECK: vech    %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xdb]
+#CHECK: vech    %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xdb]
+#CHECK: vech    %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xdb]
+
+	vech	%v0, %v0
+	vech	%v0, %v15
+	vech	%v0, %v31
+	vech	%v15, %v0
+	vech	%v31, %v0
+	vech	%v14, %v17
+
+#CHECK: veclb   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x00,0xd9]
+#CHECK: veclb   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xd9]
+#CHECK: veclb   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xd9]
+#CHECK: veclb   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xd9]
+#CHECK: veclb   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xd9]
+#CHECK: veclb   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xd9]
+
+	veclb	%v0, %v0
+	veclb	%v0, %v15
+	veclb	%v0, %v31
+	veclb	%v15, %v0
+	veclb	%v31, %v0
+	veclb	%v14, %v17
+
+#CHECK: veclf   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x20,0xd9]
+#CHECK: veclf   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xd9]
+#CHECK: veclf   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xd9]
+#CHECK: veclf   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xd9]
+#CHECK: veclf   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xd9]
+#CHECK: veclf   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xd9]
+
+	veclf	%v0, %v0
+	veclf	%v0, %v15
+	veclf	%v0, %v31
+	veclf	%v15, %v0
+	veclf	%v31, %v0
+	veclf	%v14, %v17
+
+#CHECK: veclg   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x30,0xd9]
+#CHECK: veclg   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xd9]
+#CHECK: veclg   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xd9]
+#CHECK: veclg   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xd9]
+#CHECK: veclg   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xd9]
+#CHECK: veclg   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xd9]
+
+	veclg	%v0, %v0
+	veclg	%v0, %v15
+	veclg	%v0, %v31
+	veclg	%v15, %v0
+	veclg	%v31, %v0
+	veclg	%v14, %v17
+
+#CHECK: veclh   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x10,0xd9]
+#CHECK: veclh   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xd9]
+#CHECK: veclh   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xd9]
+#CHECK: veclh   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xd9]
+#CHECK: veclh   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xd9]
+#CHECK: veclh   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xd9]
+
+	veclh	%v0, %v0
+	veclh	%v0, %v15
+	veclh	%v0, %v31
+	veclh	%v15, %v0
+	veclh	%v31, %v0
+	veclh	%v14, %v17
+
+#CHECK: verimb  %v0, %v0, %v0, 0        # encoding: [0xe7,0x00,0x00,0x00,0x00,0x72]
+#CHECK: verimb  %v0, %v0, %v0, 255      # encoding: [0xe7,0x00,0x00,0xff,0x00,0x72]
+#CHECK: verimb  %v0, %v0, %v31, 0       # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x72]
+#CHECK: verimb  %v0, %v31, %v0, 0       # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x72]
+#CHECK: verimb  %v31, %v0, %v0, 0       # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x72]
+#CHECK: verimb  %v13, %v17, %v21, 121   # encoding: [0xe7,0xd1,0x50,0x79,0x06,0x72]
+
+	verimb	%v0, %v0, %v0, 0
+	verimb	%v0, %v0, %v0, 255
+	verimb	%v0, %v0, %v31, 0
+	verimb	%v0, %v31, %v0, 0
+	verimb	%v31, %v0, %v0, 0
+	verimb 	%v13, %v17, %v21, 0x79
+
+#CHECK: verimf  %v0, %v0, %v0, 0        # encoding: [0xe7,0x00,0x00,0x00,0x20,0x72]
+#CHECK: verimf  %v0, %v0, %v0, 255      # encoding: [0xe7,0x00,0x00,0xff,0x20,0x72]
+#CHECK: verimf  %v0, %v0, %v31, 0       # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x72]
+#CHECK: verimf  %v0, %v31, %v0, 0       # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x72]
+#CHECK: verimf  %v31, %v0, %v0, 0       # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x72]
+#CHECK: verimf  %v13, %v17, %v21, 121   # encoding: [0xe7,0xd1,0x50,0x79,0x26,0x72]
+
+	verimf	%v0, %v0, %v0, 0
+	verimf	%v0, %v0, %v0, 255
+	verimf	%v0, %v0, %v31, 0
+	verimf	%v0, %v31, %v0, 0
+	verimf	%v31, %v0, %v0, 0
+	verimf 	%v13, %v17, %v21, 0x79
+
+#CHECK: verimg  %v0, %v0, %v0, 0        # encoding: [0xe7,0x00,0x00,0x00,0x30,0x72]
+#CHECK: verimg  %v0, %v0, %v0, 255      # encoding: [0xe7,0x00,0x00,0xff,0x30,0x72]
+#CHECK: verimg  %v0, %v0, %v31, 0       # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x72]
+#CHECK: verimg  %v0, %v31, %v0, 0       # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x72]
+#CHECK: verimg  %v31, %v0, %v0, 0       # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x72]
+#CHECK: verimg  %v13, %v17, %v21, 121   # encoding: [0xe7,0xd1,0x50,0x79,0x36,0x72]
+
+	verimg	%v0, %v0, %v0, 0
+	verimg	%v0, %v0, %v0, 255
+	verimg	%v0, %v0, %v31, 0
+	verimg	%v0, %v31, %v0, 0
+	verimg	%v31, %v0, %v0, 0
+	verimg 	%v13, %v17, %v21, 0x79
+
+#CHECK: verimh  %v0, %v0, %v0, 0        # encoding: [0xe7,0x00,0x00,0x00,0x10,0x72]
+#CHECK: verimh  %v0, %v0, %v0, 255      # encoding: [0xe7,0x00,0x00,0xff,0x10,0x72]
+#CHECK: verimh  %v0, %v0, %v31, 0       # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x72]
+#CHECK: verimh  %v0, %v31, %v0, 0       # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x72]
+#CHECK: verimh  %v31, %v0, %v0, 0       # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x72]
+#CHECK: verimh  %v13, %v17, %v21, 121   # encoding: [0xe7,0xd1,0x50,0x79,0x16,0x72]
+
+	verimh	%v0, %v0, %v0, 0
+	verimh	%v0, %v0, %v0, 255
+	verimh	%v0, %v0, %v31, 0
+	verimh	%v0, %v31, %v0, 0
+	verimh	%v31, %v0, %v0, 0
+	verimh 	%v13, %v17, %v21, 0x79
+
+#CHECK: verllvb %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x73]
+#CHECK: verllvb %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x73]
+#CHECK: verllvb %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x73]
+#CHECK: verllvb %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x73]
+#CHECK: verllvb %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x73]
+
+	verllvb	%v0, %v0, %v0
+	verllvb	%v0, %v0, %v31
+	verllvb	%v0, %v31, %v0
+	verllvb	%v31, %v0, %v0
+	verllvb	%v18, %v3, %v20
+
+#CHECK: verllvf %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0x73]
+#CHECK: verllvf %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x73]
+#CHECK: verllvf %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x73]
+#CHECK: verllvf %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x73]
+#CHECK: verllvf %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x73]
+
+	verllvf	%v0, %v0, %v0
+	verllvf	%v0, %v0, %v31
+	verllvf	%v0, %v31, %v0
+	verllvf	%v31, %v0, %v0
+	verllvf	%v18, %v3, %v20
+
+#CHECK: verllvg %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0x73]
+#CHECK: verllvg %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x73]
+#CHECK: verllvg %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x73]
+#CHECK: verllvg %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x73]
+#CHECK: verllvg %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x73]
+
+	verllvg	%v0, %v0, %v0
+	verllvg	%v0, %v0, %v31
+	verllvg	%v0, %v31, %v0
+	verllvg	%v31, %v0, %v0
+	verllvg	%v18, %v3, %v20
+
+#CHECK: verllvh %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0x73]
+#CHECK: verllvh %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x73]
+#CHECK: verllvh %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x73]
+#CHECK: verllvh %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x73]
+#CHECK: verllvh %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x73]
+
+	verllvh	%v0, %v0, %v0
+	verllvh	%v0, %v0, %v31
+	verllvh	%v0, %v31, %v0
+	verllvh	%v31, %v0, %v0
+	verllvh	%v18, %v3, %v20
+
+#CHECK: verllb  %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x00,0x33]
+#CHECK: verllb  %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x33]
+#CHECK: verllb  %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x33]
+#CHECK: verllb  %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x33]
+#CHECK: verllb  %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x33]
+#CHECK: verllb  %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x04,0x33]
+
+	verllb	%v0, %v0, 0
+	verllb	%v0, %v0, 4095
+	verllb	%v0, %v0, 0(%r15)
+	verllb	%v0, %v31, 0
+	verllb	%v31, %v0, 0
+	verllb	%v14, %v17, 1074(%r5)
+
+#CHECK: verllf  %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x20,0x33]
+#CHECK: verllf  %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x33]
+#CHECK: verllf  %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x33]
+#CHECK: verllf  %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x33]
+#CHECK: verllf  %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x33]
+#CHECK: verllf  %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x24,0x33]
+
+	verllf	%v0, %v0, 0
+	verllf	%v0, %v0, 4095
+	verllf	%v0, %v0, 0(%r15)
+	verllf	%v0, %v31, 0
+	verllf	%v31, %v0, 0
+	verllf	%v14, %v17, 1074(%r5)
+
+#CHECK: verllg  %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x30,0x33]
+#CHECK: verllg  %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x33]
+#CHECK: verllg  %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x33]
+#CHECK: verllg  %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x33]
+#CHECK: verllg  %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x33]
+#CHECK: verllg  %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x34,0x33]
+
+	verllg	%v0, %v0, 0
+	verllg	%v0, %v0, 4095
+	verllg	%v0, %v0, 0(%r15)
+	verllg	%v0, %v31, 0
+	verllg	%v31, %v0, 0
+	verllg	%v14, %v17, 1074(%r5)
+
+#CHECK: verllh  %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x10,0x33]
+#CHECK: verllh  %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x33]
+#CHECK: verllh  %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x33]
+#CHECK: verllh  %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x33]
+#CHECK: verllh  %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x33]
+#CHECK: verllh  %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x14,0x33]
+
+	verllh	%v0, %v0, 0
+	verllh	%v0, %v0, 4095
+	verllh	%v0, %v0, 0(%r15)
+	verllh	%v0, %v31, 0
+	verllh	%v31, %v0, 0
+	verllh	%v14, %v17, 1074(%r5)
+
+#CHECK: veslvb  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x70]
+#CHECK: veslvb  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x70]
+#CHECK: veslvb  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x70]
+#CHECK: veslvb  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x70]
+#CHECK: veslvb  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x70]
+
+	veslvb	%v0, %v0, %v0
+	veslvb	%v0, %v0, %v31
+	veslvb	%v0, %v31, %v0
+	veslvb	%v31, %v0, %v0
+	veslvb	%v18, %v3, %v20
+
+#CHECK: veslvf  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0x70]
+#CHECK: veslvf  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x70]
+#CHECK: veslvf  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x70]
+#CHECK: veslvf  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x70]
+#CHECK: veslvf  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x70]
+
+	veslvf	%v0, %v0, %v0
+	veslvf	%v0, %v0, %v31
+	veslvf	%v0, %v31, %v0
+	veslvf	%v31, %v0, %v0
+	veslvf	%v18, %v3, %v20
+
+#CHECK: veslvg  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0x70]
+#CHECK: veslvg  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x70]
+#CHECK: veslvg  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x70]
+#CHECK: veslvg  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x70]
+#CHECK: veslvg  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x70]
+
+	veslvg	%v0, %v0, %v0
+	veslvg	%v0, %v0, %v31
+	veslvg	%v0, %v31, %v0
+	veslvg	%v31, %v0, %v0
+	veslvg	%v18, %v3, %v20
+
+#CHECK: veslvh  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0x70]
+#CHECK: veslvh  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x70]
+#CHECK: veslvh  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x70]
+#CHECK: veslvh  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x70]
+#CHECK: veslvh  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x70]
+
+	veslvh	%v0, %v0, %v0
+	veslvh	%v0, %v0, %v31
+	veslvh	%v0, %v31, %v0
+	veslvh	%v31, %v0, %v0
+	veslvh	%v18, %v3, %v20
+
+#CHECK: veslb   %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x00,0x30]
+#CHECK: veslb   %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x30]
+#CHECK: veslb   %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x30]
+#CHECK: veslb   %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x30]
+#CHECK: veslb   %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x30]
+#CHECK: veslb   %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x04,0x30]
+
+	veslb	%v0, %v0, 0
+	veslb	%v0, %v0, 4095
+	veslb	%v0, %v0, 0(%r15)
+	veslb	%v0, %v31, 0
+	veslb	%v31, %v0, 0
+	veslb	%v14, %v17, 1074(%r5)
+
+#CHECK: veslf   %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x20,0x30]
+#CHECK: veslf   %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x30]
+#CHECK: veslf   %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x30]
+#CHECK: veslf   %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x30]
+#CHECK: veslf   %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x30]
+#CHECK: veslf   %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x24,0x30]
+
+	veslf	%v0, %v0, 0
+	veslf	%v0, %v0, 4095
+	veslf	%v0, %v0, 0(%r15)
+	veslf	%v0, %v31, 0
+	veslf	%v31, %v0, 0
+	veslf	%v14, %v17, 1074(%r5)
+
+#CHECK: veslg   %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x30,0x30]
+#CHECK: veslg   %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x30]
+#CHECK: veslg   %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x30]
+#CHECK: veslg   %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x30]
+#CHECK: veslg   %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x30]
+#CHECK: veslg   %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x34,0x30]
+
+	veslg	%v0, %v0, 0
+	veslg	%v0, %v0, 4095
+	veslg	%v0, %v0, 0(%r15)
+	veslg	%v0, %v31, 0
+	veslg	%v31, %v0, 0
+	veslg	%v14, %v17, 1074(%r5)
+
+#CHECK: veslh   %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x10,0x30]
+#CHECK: veslh   %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x30]
+#CHECK: veslh   %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x30]
+#CHECK: veslh   %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x30]
+#CHECK: veslh   %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x30]
+#CHECK: veslh   %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x14,0x30]
+
+	veslh	%v0, %v0, 0
+	veslh	%v0, %v0, 4095
+	veslh	%v0, %v0, 0(%r15)
+	veslh	%v0, %v31, 0
+	veslh	%v31, %v0, 0
+	veslh	%v14, %v17, 1074(%r5)
+
+#CHECK: vesravb %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x7a]
+#CHECK: vesravb %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x7a]
+#CHECK: vesravb %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x7a]
+#CHECK: vesravb %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x7a]
+#CHECK: vesravb %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x7a]
+
+	vesravb	%v0, %v0, %v0
+	vesravb	%v0, %v0, %v31
+	vesravb	%v0, %v31, %v0
+	vesravb	%v31, %v0, %v0
+	vesravb	%v18, %v3, %v20
+
+#CHECK: vesravf %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0x7a]
+#CHECK: vesravf %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x7a]
+#CHECK: vesravf %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x7a]
+#CHECK: vesravf %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x7a]
+#CHECK: vesravf %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x7a]
+
+	vesravf	%v0, %v0, %v0
+	vesravf	%v0, %v0, %v31
+	vesravf	%v0, %v31, %v0
+	vesravf	%v31, %v0, %v0
+	vesravf	%v18, %v3, %v20
+
+#CHECK: vesravg %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0x7a]
+#CHECK: vesravg %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x7a]
+#CHECK: vesravg %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x7a]
+#CHECK: vesravg %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x7a]
+#CHECK: vesravg %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x7a]
+
+	vesravg	%v0, %v0, %v0
+	vesravg	%v0, %v0, %v31
+	vesravg	%v0, %v31, %v0
+	vesravg	%v31, %v0, %v0
+	vesravg	%v18, %v3, %v20
+
+#CHECK: vesravh %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0x7a]
+#CHECK: vesravh %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x7a]
+#CHECK: vesravh %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x7a]
+#CHECK: vesravh %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x7a]
+#CHECK: vesravh %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x7a]
+
+	vesravh	%v0, %v0, %v0
+	vesravh	%v0, %v0, %v31
+	vesravh	%v0, %v31, %v0
+	vesravh	%v31, %v0, %v0
+	vesravh	%v18, %v3, %v20
+
+#CHECK: vesrab  %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x00,0x3a]
+#CHECK: vesrab  %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x3a]
+#CHECK: vesrab  %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x3a]
+#CHECK: vesrab  %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x3a]
+#CHECK: vesrab  %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x3a]
+#CHECK: vesrab  %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x04,0x3a]
+
+	vesrab	%v0, %v0, 0
+	vesrab	%v0, %v0, 4095
+	vesrab	%v0, %v0, 0(%r15)
+	vesrab	%v0, %v31, 0
+	vesrab	%v31, %v0, 0
+	vesrab	%v14, %v17, 1074(%r5)
+
+#CHECK: vesraf  %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x20,0x3a]
+#CHECK: vesraf  %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x3a]
+#CHECK: vesraf  %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x3a]
+#CHECK: vesraf  %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x3a]
+#CHECK: vesraf  %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x3a]
+#CHECK: vesraf  %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x24,0x3a]
+
+	vesraf	%v0, %v0, 0
+	vesraf	%v0, %v0, 4095
+	vesraf	%v0, %v0, 0(%r15)
+	vesraf	%v0, %v31, 0
+	vesraf	%v31, %v0, 0
+	vesraf	%v14, %v17, 1074(%r5)
+
+#CHECK: vesrag  %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x30,0x3a]
+#CHECK: vesrag  %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x3a]
+#CHECK: vesrag  %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x3a]
+#CHECK: vesrag  %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x3a]
+#CHECK: vesrag  %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x3a]
+#CHECK: vesrag  %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x34,0x3a]
+
+	vesrag	%v0, %v0, 0
+	vesrag	%v0, %v0, 4095
+	vesrag	%v0, %v0, 0(%r15)
+	vesrag	%v0, %v31, 0
+	vesrag	%v31, %v0, 0
+	vesrag	%v14, %v17, 1074(%r5)
+
+#CHECK: vesrah  %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x10,0x3a]
+#CHECK: vesrah  %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x3a]
+#CHECK: vesrah  %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x3a]
+#CHECK: vesrah  %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x3a]
+#CHECK: vesrah  %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x3a]
+#CHECK: vesrah  %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x14,0x3a]
+
+	vesrah	%v0, %v0, 0
+	vesrah	%v0, %v0, 4095
+	vesrah	%v0, %v0, 0(%r15)
+	vesrah	%v0, %v31, 0
+	vesrah	%v31, %v0, 0
+	vesrah	%v14, %v17, 1074(%r5)
+
+#CHECK: vesrlvb %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x78]
+#CHECK: vesrlvb %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x78]
+#CHECK: vesrlvb %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x78]
+#CHECK: vesrlvb %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x78]
+#CHECK: vesrlvb %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x78]
+
+	vesrlvb	%v0, %v0, %v0
+	vesrlvb	%v0, %v0, %v31
+	vesrlvb	%v0, %v31, %v0
+	vesrlvb	%v31, %v0, %v0
+	vesrlvb	%v18, %v3, %v20
+
+#CHECK: vesrlvf %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0x78]
+#CHECK: vesrlvf %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x78]
+#CHECK: vesrlvf %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x78]
+#CHECK: vesrlvf %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x78]
+#CHECK: vesrlvf %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x78]
+
+	vesrlvf	%v0, %v0, %v0
+	vesrlvf	%v0, %v0, %v31
+	vesrlvf	%v0, %v31, %v0
+	vesrlvf	%v31, %v0, %v0
+	vesrlvf	%v18, %v3, %v20
+
+#CHECK: vesrlvg %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0x78]
+#CHECK: vesrlvg %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x78]
+#CHECK: vesrlvg %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x78]
+#CHECK: vesrlvg %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x78]
+#CHECK: vesrlvg %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x78]
+
+	vesrlvg	%v0, %v0, %v0
+	vesrlvg	%v0, %v0, %v31
+	vesrlvg	%v0, %v31, %v0
+	vesrlvg	%v31, %v0, %v0
+	vesrlvg	%v18, %v3, %v20
+
+#CHECK: vesrlvh %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0x78]
+#CHECK: vesrlvh %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x78]
+#CHECK: vesrlvh %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x78]
+#CHECK: vesrlvh %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x78]
+#CHECK: vesrlvh %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x78]
+
+	vesrlvh	%v0, %v0, %v0
+	vesrlvh	%v0, %v0, %v31
+	vesrlvh	%v0, %v31, %v0
+	vesrlvh	%v31, %v0, %v0
+	vesrlvh	%v18, %v3, %v20
+
+#CHECK: vesrlb  %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x00,0x38]
+#CHECK: vesrlb  %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x38]
+#CHECK: vesrlb  %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x38]
+#CHECK: vesrlb  %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x38]
+#CHECK: vesrlb  %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x38]
+#CHECK: vesrlb  %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x04,0x38]
+
+	vesrlb	%v0, %v0, 0
+	vesrlb	%v0, %v0, 4095
+	vesrlb	%v0, %v0, 0(%r15)
+	vesrlb	%v0, %v31, 0
+	vesrlb	%v31, %v0, 0
+	vesrlb	%v14, %v17, 1074(%r5)
+
+#CHECK: vesrlf  %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x20,0x38]
+#CHECK: vesrlf  %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x38]
+#CHECK: vesrlf  %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x38]
+#CHECK: vesrlf  %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x38]
+#CHECK: vesrlf  %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x38]
+#CHECK: vesrlf  %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x24,0x38]
+
+	vesrlf	%v0, %v0, 0
+	vesrlf	%v0, %v0, 4095
+	vesrlf	%v0, %v0, 0(%r15)
+	vesrlf	%v0, %v31, 0
+	vesrlf	%v31, %v0, 0
+	vesrlf	%v14, %v17, 1074(%r5)
+
+#CHECK: vesrlg  %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x30,0x38]
+#CHECK: vesrlg  %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x38]
+#CHECK: vesrlg  %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x38]
+#CHECK: vesrlg  %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x38]
+#CHECK: vesrlg  %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x38]
+#CHECK: vesrlg  %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x34,0x38]
+
+	vesrlg	%v0, %v0, 0
+	vesrlg	%v0, %v0, 4095
+	vesrlg	%v0, %v0, 0(%r15)
+	vesrlg	%v0, %v31, 0
+	vesrlg	%v31, %v0, 0
+	vesrlg	%v14, %v17, 1074(%r5)
+
+#CHECK: vesrlh  %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x10,0x38]
+#CHECK: vesrlh  %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x38]
+#CHECK: vesrlh  %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x38]
+#CHECK: vesrlh  %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x38]
+#CHECK: vesrlh  %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x38]
+#CHECK: vesrlh  %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x14,0x38]
+
+	vesrlh	%v0, %v0, 0
+	vesrlh	%v0, %v0, 4095
+	vesrlh	%v0, %v0, 0(%r15)
+	vesrlh	%v0, %v31, 0
+	vesrlh	%v31, %v0, 0
+	vesrlh	%v14, %v17, 1074(%r5)
+
+#CHECK: vfadb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xe3]
+#CHECK: vfadb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xe3]
+#CHECK: vfadb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xe3]
+#CHECK: vfadb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xe3]
+#CHECK: vfadb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xe3]
+
+	vfadb	%v0, %v0, %v0
+	vfadb	%v0, %v0, %v31
+	vfadb	%v0, %v31, %v0
+	vfadb	%v31, %v0, %v0
+	vfadb	%v18, %v3, %v20
+
+#CHECK: vfaeb   %v0, %v0, %v0, 0        # encoding: [0xe7,0x00,0x00,0x00,0x00,0x82]
+#CHECK: vfaeb   %v0, %v0, %v0, 0        # encoding: [0xe7,0x00,0x00,0x00,0x00,0x82]
+#CHECK: vfaeb   %v0, %v0, %v0, 12       # encoding: [0xe7,0x00,0x00,0xc0,0x00,0x82]
+#CHECK: vfaeb   %v0, %v0, %v15, 0       # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x82]
+#CHECK: vfaeb   %v0, %v0, %v31, 0       # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x82]
+#CHECK: vfaeb   %v0, %v15, %v0, 0       # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x82]
+#CHECK: vfaeb   %v0, %v31, %v0, 0       # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x82]
+#CHECK: vfaeb   %v15, %v0, %v0, 0       # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x82]
+#CHECK: vfaeb   %v31, %v0, %v0, 0       # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x82]
+#CHECK: vfaeb   %v18, %v3, %v20, 4      # encoding: [0xe7,0x23,0x40,0x40,0x0a,0x82]
+#CHECK: vfaeb   %v18, %v3, %v20, 15     # encoding: [0xe7,0x23,0x40,0xf0,0x0a,0x82]
+#CHECK: vfaebs  %v18, %v3, %v20, 8      # encoding: [0xe7,0x23,0x40,0x90,0x0a,0x82]
+#CHECK: vfaezb  %v18, %v3, %v20, 4      # encoding: [0xe7,0x23,0x40,0x60,0x0a,0x82]
+#CHECK: vfaezbs %v18, %v3, %v20, 8      # encoding: [0xe7,0x23,0x40,0xb0,0x0a,0x82]
+#CHECK: vfaezbs %v18, %v3, %v20, 15     # encoding: [0xe7,0x23,0x40,0xf0,0x0a,0x82]
+
+	vfaeb	%v0, %v0, %v0
+	vfaeb	%v0, %v0, %v0, 0
+	vfaeb	%v0, %v0, %v0, 12
+	vfaeb	%v0, %v0, %v15
+	vfaeb	%v0, %v0, %v31
+	vfaeb	%v0, %v15, %v0
+	vfaeb	%v0, %v31, %v0
+	vfaeb	%v15, %v0, %v0
+	vfaeb	%v31, %v0, %v0
+	vfaeb	%v18, %v3, %v20, 4
+	vfaeb	%v18, %v3, %v20, 15
+	vfaebs	%v18, %v3, %v20, 8
+	vfaezb	%v18, %v3, %v20, 4
+	vfaezbs	%v18, %v3, %v20, 8
+	vfaezbs	%v18, %v3, %v20, 15
+
+#CHECK: vfaef   %v0, %v0, %v0, 0        # encoding: [0xe7,0x00,0x00,0x00,0x20,0x82]
+#CHECK: vfaef   %v0, %v0, %v0, 0        # encoding: [0xe7,0x00,0x00,0x00,0x20,0x82]
+#CHECK: vfaef   %v0, %v0, %v0, 12       # encoding: [0xe7,0x00,0x00,0xc0,0x20,0x82]
+#CHECK: vfaef   %v0, %v0, %v15, 0       # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x82]
+#CHECK: vfaef   %v0, %v0, %v31, 0       # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x82]
+#CHECK: vfaef   %v0, %v15, %v0, 0       # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x82]
+#CHECK: vfaef   %v0, %v31, %v0, 0       # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x82]
+#CHECK: vfaef   %v15, %v0, %v0, 0       # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x82]
+#CHECK: vfaef   %v31, %v0, %v0, 0       # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x82]
+#CHECK: vfaef   %v18, %v3, %v20, 4      # encoding: [0xe7,0x23,0x40,0x40,0x2a,0x82]
+#CHECK: vfaef   %v18, %v3, %v20, 15     # encoding: [0xe7,0x23,0x40,0xf0,0x2a,0x82]
+#CHECK: vfaefs  %v18, %v3, %v20, 8      # encoding: [0xe7,0x23,0x40,0x90,0x2a,0x82]
+#CHECK: vfaezf  %v18, %v3, %v20, 4      # encoding: [0xe7,0x23,0x40,0x60,0x2a,0x82]
+#CHECK: vfaezfs %v18, %v3, %v20, 8      # encoding: [0xe7,0x23,0x40,0xb0,0x2a,0x82]
+#CHECK: vfaezfs %v18, %v3, %v20, 15     # encoding: [0xe7,0x23,0x40,0xf0,0x2a,0x82]
+
+	vfaef	%v0, %v0, %v0
+	vfaef	%v0, %v0, %v0, 0
+	vfaef	%v0, %v0, %v0, 12
+	vfaef	%v0, %v0, %v15
+	vfaef	%v0, %v0, %v31
+	vfaef	%v0, %v15, %v0
+	vfaef	%v0, %v31, %v0
+	vfaef	%v15, %v0, %v0
+	vfaef	%v31, %v0, %v0
+	vfaef	%v18, %v3, %v20, 4
+	vfaef	%v18, %v3, %v20, 15
+	vfaefs	%v18, %v3, %v20, 8
+	vfaezf	%v18, %v3, %v20, 4
+	vfaezfs	%v18, %v3, %v20, 8
+	vfaezfs	%v18, %v3, %v20, 15
+
+#CHECK: vfaeh   %v0, %v0, %v0, 0        # encoding: [0xe7,0x00,0x00,0x00,0x10,0x82]
+#CHECK: vfaeh   %v0, %v0, %v0, 0        # encoding: [0xe7,0x00,0x00,0x00,0x10,0x82]
+#CHECK: vfaeh   %v0, %v0, %v0, 12       # encoding: [0xe7,0x00,0x00,0xc0,0x10,0x82]
+#CHECK: vfaeh   %v0, %v0, %v15, 0       # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x82]
+#CHECK: vfaeh   %v0, %v0, %v31, 0       # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x82]
+#CHECK: vfaeh   %v0, %v15, %v0, 0       # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x82]
+#CHECK: vfaeh   %v0, %v31, %v0, 0       # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x82]
+#CHECK: vfaeh   %v15, %v0, %v0, 0       # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x82]
+#CHECK: vfaeh   %v31, %v0, %v0, 0       # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x82]
+#CHECK: vfaeh   %v18, %v3, %v20, 4      # encoding: [0xe7,0x23,0x40,0x40,0x1a,0x82]
+#CHECK: vfaeh   %v18, %v3, %v20, 15     # encoding: [0xe7,0x23,0x40,0xf0,0x1a,0x82]
+#CHECK: vfaehs  %v18, %v3, %v20, 8      # encoding: [0xe7,0x23,0x40,0x90,0x1a,0x82]
+#CHECK: vfaezh  %v18, %v3, %v20, 4      # encoding: [0xe7,0x23,0x40,0x60,0x1a,0x82]
+#CHECK: vfaezhs %v18, %v3, %v20, 8      # encoding: [0xe7,0x23,0x40,0xb0,0x1a,0x82]
+#CHECK: vfaezhs %v18, %v3, %v20, 15     # encoding: [0xe7,0x23,0x40,0xf0,0x1a,0x82]
+
+	vfaeh	%v0, %v0, %v0
+	vfaeh	%v0, %v0, %v0, 0
+	vfaeh	%v0, %v0, %v0, 12
+	vfaeh	%v0, %v0, %v15
+	vfaeh	%v0, %v0, %v31
+	vfaeh	%v0, %v15, %v0
+	vfaeh	%v0, %v31, %v0
+	vfaeh	%v15, %v0, %v0
+	vfaeh	%v31, %v0, %v0
+	vfaeh	%v18, %v3, %v20, 4
+	vfaeh	%v18, %v3, %v20, 15
+	vfaehs	%v18, %v3, %v20, 8
+	vfaezh	%v18, %v3, %v20, 4
+	vfaezhs	%v18, %v3, %v20, 8
+	vfaezhs	%v18, %v3, %v20, 15
+
+#CHECK: vfcedb  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xe8]
+#CHECK: vfcedb  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xe8]
+#CHECK: vfcedb  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xe8]
+#CHECK: vfcedb  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xe8]
+#CHECK: vfcedb  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xe8]
+
+	vfcedb	%v0, %v0, %v0
+	vfcedb	%v0, %v0, %v31
+	vfcedb	%v0, %v31, %v0
+	vfcedb	%v31, %v0, %v0
+	vfcedb	%v18, %v3, %v20
+
+#CHECK: vfcedbs %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x10,0x30,0xe8]
+#CHECK: vfcedbs %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x10,0x32,0xe8]
+#CHECK: vfcedbs %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x10,0x34,0xe8]
+#CHECK: vfcedbs %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x10,0x38,0xe8]
+#CHECK: vfcedbs %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x10,0x3a,0xe8]
+
+	vfcedbs	%v0, %v0, %v0
+	vfcedbs	%v0, %v0, %v31
+	vfcedbs	%v0, %v31, %v0
+	vfcedbs	%v31, %v0, %v0
+	vfcedbs	%v18, %v3, %v20
+
+#CHECK: vfchdb  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xeb]
+#CHECK: vfchdb  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xeb]
+#CHECK: vfchdb  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xeb]
+#CHECK: vfchdb  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xeb]
+#CHECK: vfchdb  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xeb]
+
+	vfchdb	%v0, %v0, %v0
+	vfchdb	%v0, %v0, %v31
+	vfchdb	%v0, %v31, %v0
+	vfchdb	%v31, %v0, %v0
+	vfchdb	%v18, %v3, %v20
+
+#CHECK: vfchdbs %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x10,0x30,0xeb]
+#CHECK: vfchdbs %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x10,0x32,0xeb]
+#CHECK: vfchdbs %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x10,0x34,0xeb]
+#CHECK: vfchdbs %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x10,0x38,0xeb]
+#CHECK: vfchdbs %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x10,0x3a,0xeb]
+
+	vfchdbs	%v0, %v0, %v0
+	vfchdbs	%v0, %v0, %v31
+	vfchdbs	%v0, %v31, %v0
+	vfchdbs	%v31, %v0, %v0
+	vfchdbs	%v18, %v3, %v20
+
+#CHECK: vfchedb %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xea]
+#CHECK: vfchedb %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xea]
+#CHECK: vfchedb %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xea]
+#CHECK: vfchedb %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xea]
+#CHECK: vfchedb %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xea]
+
+	vfchedb	%v0, %v0, %v0
+	vfchedb	%v0, %v0, %v31
+	vfchedb	%v0, %v31, %v0
+	vfchedb	%v31, %v0, %v0
+	vfchedb	%v18, %v3, %v20
+
+#CHECK: vfchedbs %v0, %v0, %v0          # encoding: [0xe7,0x00,0x00,0x10,0x30,0xea]
+#CHECK: vfchedbs %v0, %v0, %v31         # encoding: [0xe7,0x00,0xf0,0x10,0x32,0xea]
+#CHECK: vfchedbs %v0, %v31, %v0         # encoding: [0xe7,0x0f,0x00,0x10,0x34,0xea]
+#CHECK: vfchedbs %v31, %v0, %v0         # encoding: [0xe7,0xf0,0x00,0x10,0x38,0xea]
+#CHECK: vfchedbs %v18, %v3, %v20        # encoding: [0xe7,0x23,0x40,0x10,0x3a,0xea]
+
+	vfchedbs %v0, %v0, %v0
+	vfchedbs %v0, %v0, %v31
+	vfchedbs %v0, %v31, %v0
+	vfchedbs %v31, %v0, %v0
+	vfchedbs %v18, %v3, %v20
+
+#CHECK: vfddb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xe5]
+#CHECK: vfddb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xe5]
+#CHECK: vfddb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xe5]
+#CHECK: vfddb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xe5]
+#CHECK: vfddb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xe5]
+
+	vfddb	%v0, %v0, %v0
+	vfddb	%v0, %v0, %v31
+	vfddb	%v0, %v31, %v0
+	vfddb	%v31, %v0, %v0
+	vfddb	%v18, %v3, %v20
+
+#CHECK: vfeeb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x80]
+#CHECK: vfeeb   %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x80]
+#CHECK: vfeeb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x80]
+#CHECK: vfeeb   %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x80]
+#CHECK: vfeeb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x80]
+#CHECK: vfeeb   %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x80]
+#CHECK: vfeeb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x80]
+#CHECK: vfeeb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x80]
+#CHECK: vfeebs  %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x04,0x80]
+#CHECK: vfeezb  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x20,0x0a,0x80]
+#CHECK: vfeezbs %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x30,0x04,0x80]
+
+	vfeeb	%v0, %v0, %v0
+	vfeeb	%v0, %v0, %v15
+	vfeeb	%v0, %v0, %v31
+	vfeeb	%v0, %v15, %v0
+	vfeeb	%v0, %v31, %v0
+	vfeeb	%v15, %v0, %v0
+	vfeeb	%v31, %v0, %v0
+	vfeeb	%v18, %v3, %v20
+	vfeebs	%v5, %v22, %v7
+	vfeezb	%v18, %v3, %v20
+	vfeezbs	%v5, %v22, %v7
+
+#CFECK: vfeef   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0x80]
+#CFECK: vfeef   %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x80]
+#CFECK: vfeef   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x80]
+#CFECK: vfeef   %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x80]
+#CFECK: vfeef   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x80]
+#CFECK: vfeef   %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x80]
+#CFECK: vfeef   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x80]
+#CFECK: vfeef   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x80]
+#CFECK: vfeefs  %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x24,0x80]
+#CFECK: vfeezf  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x20,0x2a,0x80]
+#CFECK: vfeezfs %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x30,0x24,0x80]
+
+	vfeef	%v0, %v0, %v0
+	vfeef	%v0, %v0, %v15
+	vfeef	%v0, %v0, %v31
+	vfeef	%v0, %v15, %v0
+	vfeef	%v0, %v31, %v0
+	vfeef	%v15, %v0, %v0
+	vfeef	%v31, %v0, %v0
+	vfeef	%v18, %v3, %v20
+	vfeefs	%v5, %v22, %v7
+	vfeezf	%v18, %v3, %v20
+	vfeezfs	%v5, %v22, %v7
+
+#CHECK: vfeeh   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0x80]
+#CHECK: vfeeh   %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x80]
+#CHECK: vfeeh   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x80]
+#CHECK: vfeeh   %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x80]
+#CHECK: vfeeh   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x80]
+#CHECK: vfeeh   %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x80]
+#CHECK: vfeeh   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x80]
+#CHECK: vfeeh   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x80]
+#CHECK: vfeehs  %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x14,0x80]
+#CHECK: vfeezh  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x20,0x1a,0x80]
+#CHECK: vfeezhs %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x30,0x14,0x80]
+
+	vfeeh	%v0, %v0, %v0
+	vfeeh	%v0, %v0, %v15
+	vfeeh	%v0, %v0, %v31
+	vfeeh	%v0, %v15, %v0
+	vfeeh	%v0, %v31, %v0
+	vfeeh	%v15, %v0, %v0
+	vfeeh	%v31, %v0, %v0
+	vfeeh	%v18, %v3, %v20
+	vfeehs	%v5, %v22, %v7
+	vfeezh	%v18, %v3, %v20
+	vfeezhs	%v5, %v22, %v7
+
+#CHECK: vfeneb   %v0, %v0, %v0          # encoding: [0xe7,0x00,0x00,0x00,0x00,0x81]
+#CHECK: vfeneb   %v0, %v0, %v15         # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x81]
+#CHECK: vfeneb   %v0, %v0, %v31         # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x81]
+#CHECK: vfeneb   %v0, %v15, %v0         # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x81]
+#CHECK: vfeneb   %v0, %v31, %v0         # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x81]
+#CHECK: vfeneb   %v15, %v0, %v0         # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x81]
+#CHECK: vfeneb   %v31, %v0, %v0         # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x81]
+#CHECK: vfeneb   %v18, %v3, %v20        # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x81]
+#CHECK: vfenebs  %v5, %v22, %v7         # encoding: [0xe7,0x56,0x70,0x10,0x04,0x81]
+#CHECK: vfenezb  %v18, %v3, %v20        # encoding: [0xe7,0x23,0x40,0x20,0x0a,0x81]
+#CHECK: vfenezbs %v5, %v22, %v7         # encoding: [0xe7,0x56,0x70,0x30,0x04,0x81]
+
+	vfeneb   %v0, %v0, %v0
+	vfeneb   %v0, %v0, %v15
+	vfeneb   %v0, %v0, %v31
+	vfeneb   %v0, %v15, %v0
+	vfeneb   %v0, %v31, %v0
+	vfeneb   %v15, %v0, %v0
+	vfeneb   %v31, %v0, %v0
+	vfeneb   %v18, %v3, %v20
+	vfenebs  %v5, %v22, %v7
+	vfenezb  %v18, %v3, %v20
+	vfenezbs %v5, %v22, %v7
+
+#CFECK: vfenef   %v0, %v0, %v0          # encoding: [0xe7,0x00,0x00,0x00,0x20,0x81]
+#CFECK: vfenef   %v0, %v0, %v15         # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x81]
+#CFECK: vfenef   %v0, %v0, %v31         # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x81]
+#CFECK: vfenef   %v0, %v15, %v0         # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x81]
+#CFECK: vfenef   %v0, %v31, %v0         # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x81]
+#CFECK: vfenef   %v15, %v0, %v0         # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x81]
+#CFECK: vfenef   %v31, %v0, %v0         # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x81]
+#CFECK: vfenef   %v18, %v3, %v20        # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x81]
+#CFECK: vfenefs  %v5, %v22, %v7         # encoding: [0xe7,0x56,0x70,0x10,0x24,0x81]
+#CFECK: vfenezf  %v18, %v3, %v20        # encoding: [0xe7,0x23,0x40,0x20,0x2a,0x81]
+#CFECK: vfenezfs %v5, %v22, %v7         # encoding: [0xe7,0x56,0x70,0x30,0x24,0x81]
+
+	vfenef   %v0, %v0, %v0
+	vfenef   %v0, %v0, %v15
+	vfenef   %v0, %v0, %v31
+	vfenef   %v0, %v15, %v0
+	vfenef   %v0, %v31, %v0
+	vfenef   %v15, %v0, %v0
+	vfenef   %v31, %v0, %v0
+	vfenef   %v18, %v3, %v20
+	vfenefs  %v5, %v22, %v7
+	vfenezf  %v18, %v3, %v20
+	vfenezfs %v5, %v22, %v7
+
+#CHECK: vfeneh   %v0, %v0, %v0          # encoding: [0xe7,0x00,0x00,0x00,0x10,0x81]
+#CHECK: vfeneh   %v0, %v0, %v15         # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x81]
+#CHECK: vfeneh   %v0, %v0, %v31         # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x81]
+#CHECK: vfeneh   %v0, %v15, %v0         # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x81]
+#CHECK: vfeneh   %v0, %v31, %v0         # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x81]
+#CHECK: vfeneh   %v15, %v0, %v0         # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x81]
+#CHECK: vfeneh   %v31, %v0, %v0         # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x81]
+#CHECK: vfeneh   %v18, %v3, %v20        # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x81]
+#CHECK: vfenehs  %v5, %v22, %v7         # encoding: [0xe7,0x56,0x70,0x10,0x14,0x81]
+#CHECK: vfenezh  %v18, %v3, %v20        # encoding: [0xe7,0x23,0x40,0x20,0x1a,0x81]
+#CHECK: vfenezhs %v5, %v22, %v7         # encoding: [0xe7,0x56,0x70,0x30,0x14,0x81]
+
+	vfeneh   %v0, %v0, %v0
+	vfeneh   %v0, %v0, %v15
+	vfeneh   %v0, %v0, %v31
+	vfeneh   %v0, %v15, %v0
+	vfeneh   %v0, %v31, %v0
+	vfeneh   %v15, %v0, %v0
+	vfeneh   %v31, %v0, %v0
+	vfeneh   %v18, %v3, %v20
+	vfenehs  %v5, %v22, %v7
+	vfenezh  %v18, %v3, %v20
+	vfenezhs %v5, %v22, %v7
+
+#CHECK: vfidb   %v0, %v0, 0, 0          # encoding: [0xe7,0x00,0x00,0x00,0x30,0xc7]
+#CHECK: vfidb   %v0, %v0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf0,0x30,0xc7]
+#CHECK: vfidb   %v0, %v0, 4, 0          # encoding: [0xe7,0x00,0x00,0x04,0x30,0xc7]
+#CHECK: vfidb   %v0, %v0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc7]
+#CHECK: vfidb   %v0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xc7]
+#CHECK: vfidb   %v31, %v0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xc7]
+#CHECK: vfidb   %v14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xa4,0x34,0xc7]
+
+	vfidb	%v0, %v0, 0, 0
+	vfidb	%v0, %v0, 0, 15
+	vfidb	%v0, %v0, 4, 0
+	vfidb	%v0, %v0, 12, 0
+	vfidb	%v0, %v31, 0, 0
+	vfidb	%v31, %v0, 0, 0
+	vfidb	%v14, %v17, 4, 10
+
+#CHECK: vistrb   %v0, %v0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x5c]
+#CHECK: vistrb   %v0, %v15              # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x5c]
+#CHECK: vistrb   %v0, %v31              # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x5c]
+#CHECK: vistrb   %v15, %v0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x5c]
+#CHECK: vistrb   %v31, %v0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x5c]
+#CHECK: vistrb   %v18, %v3              # encoding: [0xe7,0x23,0x00,0x00,0x08,0x5c]
+#CHECK: vistrbs  %v5, %v22              # encoding: [0xe7,0x56,0x00,0x10,0x04,0x5c]
+
+	vistrb   %v0, %v0
+	vistrb   %v0, %v15
+	vistrb   %v0, %v31
+	vistrb   %v15, %v0
+	vistrb   %v31, %v0
+	vistrb   %v18, %v3
+	vistrbs  %v5, %v22
+
+#CBECK: vistrf   %v0, %v0               # encoding: [0xe7,0x00,0x00,0x00,0x20,0x5c]
+#CBECK: vistrf   %v0, %v15              # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x5c]
+#CBECK: vistrf   %v0, %v31              # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x5c]
+#CBECK: vistrf   %v15, %v0              # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x5c]
+#CBECK: vistrf   %v31, %v0              # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x5c]
+#CBECK: vistrf   %v18, %v3              # encoding: [0xe7,0x23,0x00,0x00,0x28,0x5c]
+#CBECK: vistrfs  %v5, %v22              # encoding: [0xe7,0x56,0x00,0x10,0x24,0x5c]
+
+	vistrf   %v0, %v0
+	vistrf   %v0, %v15
+	vistrf   %v0, %v31
+	vistrf   %v15, %v0
+	vistrf   %v31, %v0
+	vistrf   %v18, %v3
+	vistrfs  %v5, %v22
+
+#CHECK: vistrh   %v0, %v0               # encoding: [0xe7,0x00,0x00,0x00,0x10,0x5c]
+#CHECK: vistrh   %v0, %v15              # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x5c]
+#CHECK: vistrh   %v0, %v31              # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x5c]
+#CHECK: vistrh   %v15, %v0              # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x5c]
+#CHECK: vistrh   %v31, %v0              # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x5c]
+#CHECK: vistrh   %v18, %v3              # encoding: [0xe7,0x23,0x00,0x00,0x18,0x5c]
+#CHECK: vistrhs  %v5, %v22              # encoding: [0xe7,0x56,0x00,0x10,0x14,0x5c]
+
+	vistrh   %v0, %v0
+	vistrh   %v0, %v15
+	vistrh   %v0, %v31
+	vistrh   %v15, %v0
+	vistrh   %v31, %v0
+	vistrh   %v18, %v3
+	vistrhs  %v5, %v22
+
+#CHECK: vflcdb  %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x30,0xcc]
+#CHECK: vflcdb  %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xcc]
+#CHECK: vflcdb  %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xcc]
+#CHECK: vflcdb  %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xcc]
+#CHECK: vflcdb  %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xcc]
+#CHECK: vflcdb  %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xcc]
+
+	vflcdb	%v0, %v0
+	vflcdb	%v0, %v15
+	vflcdb	%v0, %v31
+	vflcdb	%v15, %v0
+	vflcdb	%v31, %v0
+	vflcdb	%v14, %v17
+
+#CHECK: vflndb  %v0, %v0                # encoding: [0xe7,0x00,0x00,0x10,0x30,0xcc]
+#CHECK: vflndb  %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x10,0x30,0xcc]
+#CHECK: vflndb  %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x10,0x34,0xcc]
+#CHECK: vflndb  %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x10,0x30,0xcc]
+#CHECK: vflndb  %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x10,0x38,0xcc]
+#CHECK: vflndb  %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x10,0x34,0xcc]
+
+	vflndb	%v0, %v0
+	vflndb	%v0, %v15
+	vflndb	%v0, %v31
+	vflndb	%v15, %v0
+	vflndb	%v31, %v0
+	vflndb	%v14, %v17
+
+#CHECK: vflpdb  %v0, %v0                # encoding: [0xe7,0x00,0x00,0x20,0x30,0xcc]
+#CHECK: vflpdb  %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x20,0x30,0xcc]
+#CHECK: vflpdb  %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x20,0x34,0xcc]
+#CHECK: vflpdb  %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x20,0x30,0xcc]
+#CHECK: vflpdb  %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x20,0x38,0xcc]
+#CHECK: vflpdb  %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x20,0x34,0xcc]
+
+	vflpdb	%v0, %v0
+	vflpdb	%v0, %v15
+	vflpdb	%v0, %v31
+	vflpdb	%v15, %v0
+	vflpdb	%v31, %v0
+	vflpdb	%v14, %v17
+
+#CHECK: vfmadb  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x03,0x00,0x00,0x8f]
+#CHECK: vfmadb  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x03,0x00,0xf1,0x8f]
+#CHECK: vfmadb  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf3,0x00,0x02,0x8f]
+#CHECK: vfmadb  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x03,0x00,0x04,0x8f]
+#CHECK: vfmadb  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x03,0x00,0x08,0x8f]
+#CHECK: vfmadb  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x53,0x00,0x97,0x8f]
+
+	vfmadb	%v0, %v0, %v0, %v0
+	vfmadb	%v0, %v0, %v0, %v31
+	vfmadb	%v0, %v0, %v31, %v0
+	vfmadb	%v0, %v31, %v0, %v0
+	vfmadb	%v31, %v0, %v0, %v0
+	vfmadb	%v13, %v17, %v21, %v25
+
+#CHECK: vfmdb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xe7]
+#CHECK: vfmdb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xe7]
+#CHECK: vfmdb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xe7]
+#CHECK: vfmdb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xe7]
+#CHECK: vfmdb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xe7]
+
+	vfmdb	%v0, %v0, %v0
+	vfmdb	%v0, %v0, %v31
+	vfmdb	%v0, %v31, %v0
+	vfmdb	%v31, %v0, %v0
+	vfmdb	%v18, %v3, %v20
+
+#CHECK: vfmsdb  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x03,0x00,0x00,0x8e]
+#CHECK: vfmsdb  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x03,0x00,0xf1,0x8e]
+#CHECK: vfmsdb  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf3,0x00,0x02,0x8e]
+#CHECK: vfmsdb  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x03,0x00,0x04,0x8e]
+#CHECK: vfmsdb  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x03,0x00,0x08,0x8e]
+#CHECK: vfmsdb  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x53,0x00,0x97,0x8e]
+
+	vfmsdb	%v0, %v0, %v0, %v0
+	vfmsdb	%v0, %v0, %v0, %v31
+	vfmsdb	%v0, %v0, %v31, %v0
+	vfmsdb	%v0, %v31, %v0, %v0
+	vfmsdb	%v31, %v0, %v0, %v0
+	vfmsdb	%v13, %v17, %v21, %v25
+
+#CHECK: vfsdb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xe2]
+#CHECK: vfsdb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xe2]
+#CHECK: vfsdb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xe2]
+#CHECK: vfsdb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xe2]
+#CHECK: vfsdb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xe2]
+
+	vfsdb	%v0, %v0, %v0
+	vfsdb	%v0, %v0, %v31
+	vfsdb	%v0, %v31, %v0
+	vfsdb	%v31, %v0, %v0
+	vfsdb	%v18, %v3, %v20
+
+#CHECK: vfsqdb  %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x30,0xce]
+#CHECK: vfsqdb  %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xce]
+#CHECK: vfsqdb  %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xce]
+#CHECK: vfsqdb  %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xce]
+#CHECK: vfsqdb  %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xce]
+#CHECK: vfsqdb  %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xce]
+
+	vfsqdb	%v0, %v0
+	vfsqdb	%v0, %v15
+	vfsqdb	%v0, %v31
+	vfsqdb	%v15, %v0
+	vfsqdb	%v31, %v0
+	vfsqdb	%v14, %v17
+
+#CHECK: vftcidb %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x30,0x4a]
+#CHECK: vftcidb %v0, %v0, 4095          # encoding: [0xe7,0x00,0xff,0xf0,0x30,0x4a]
+#CHECK: vftcidb %v0, %v15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x4a]
+#CHECK: vftcidb %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x4a]
+#CHECK: vftcidb %v15, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x4a]
+#CHECK: vftcidb %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x4a]
+#CHECK: vftcidb %v4, %v21, 1656         # encoding: [0xe7,0x45,0x67,0x80,0x34,0x4a]
+
+	vftcidb	%v0, %v0, 0
+	vftcidb	%v0, %v0, 4095
+	vftcidb	%v0, %v15, 0
+	vftcidb	%v0, %v31, 0
+	vftcidb	%v15, %v0, 0
+	vftcidb	%v31, %v0, 0
+	vftcidb	%v4, %v21, 0x678
+
+#CHECK: vgbm    %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x00,0x44]
+#CHECK: vgbm    %v0, 65535              # encoding: [0xe7,0x00,0xff,0xff,0x00,0x44]
+#CHECK: vgbm    %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x44]
+#CHECK: vgbm    %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x44]
+#CHECK: vgbm    %v17, 4660              # encoding: [0xe7,0x10,0x12,0x34,0x08,0x44]
+
+	vgbm	%v0, 0
+	vgbm	%v0, 0xffff
+	vgbm	%v15, 0
+	vgbm	%v31, 0
+	vgbm	%v17, 0x1234
+
+#CHECK: vgef    %v0, 0(%v0), 0          # encoding: [0xe7,0x00,0x00,0x00,0x00,0x13]
+#CHECK: vgef    %v0, 0(%v0,%r1), 0      # encoding: [0xe7,0x00,0x10,0x00,0x00,0x13]
+#CHECK: vgef    %v0, 0(%v0,%r1), 3      # encoding: [0xe7,0x00,0x10,0x00,0x30,0x13]
+#CHECK: vgef    %v0, 0(%v0,%r15), 0     # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x13]
+#CHECK: vgef    %v0, 0(%v15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x13]
+#CHECK: vgef    %v0, 0(%v31,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x04,0x13]
+#CHECK: vgef    %v0, 4095(%v0,%r1), 0   # encoding: [0xe7,0x00,0x1f,0xff,0x00,0x13]
+#CHECK: vgef    %v15, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x00,0x13]
+#CHECK: vgef    %v31, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x13]
+#CHECK: vgef    %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x13]
+
+	vgef	%v0, 0(%v0), 0
+	vgef	%v0, 0(%v0,%r1), 0
+	vgef	%v0, 0(%v0,%r1), 3
+	vgef	%v0, 0(%v0,%r15), 0
+	vgef	%v0, 0(%v15,%r1), 0
+	vgef	%v0, 0(%v31,%r1), 0
+	vgef	%v0, 4095(%v0, %r1), 0
+	vgef	%v15, 0(%v0,%r1), 0
+	vgef	%v31, 0(%v0,%r1), 0
+	vgef	%v10, 1000(%v19,%r7), 1
+
+#CHECK: vgeg    %v0, 0(%v0), 0          # encoding: [0xe7,0x00,0x00,0x00,0x00,0x12]
+#CHECK: vgeg    %v0, 0(%v0,%r1), 0      # encoding: [0xe7,0x00,0x10,0x00,0x00,0x12]
+#CHECK: vgeg    %v0, 0(%v0,%r1), 1      # encoding: [0xe7,0x00,0x10,0x00,0x10,0x12]
+#CHECK: vgeg    %v0, 0(%v0,%r15), 0     # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x12]
+#CHECK: vgeg    %v0, 0(%v15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x12]
+#CHECK: vgeg    %v0, 0(%v31,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x04,0x12]
+#CHECK: vgeg    %v0, 4095(%v0,%r1), 0   # encoding: [0xe7,0x00,0x1f,0xff,0x00,0x12]
+#CHECK: vgeg    %v15, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x00,0x12]
+#CHECK: vgeg    %v31, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x12]
+#CHECK: vgeg    %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x12]
+
+	vgeg	%v0, 0(%v0), 0
+	vgeg	%v0, 0(%v0,%r1), 0
+	vgeg	%v0, 0(%v0,%r1), 1
+	vgeg	%v0, 0(%v0,%r15), 0
+	vgeg	%v0, 0(%v15,%r1), 0
+	vgeg	%v0, 0(%v31,%r1), 0
+	vgeg	%v0, 4095(%v0,%r1), 0
+	vgeg	%v15, 0(%v0,%r1), 0
+	vgeg	%v31, 0(%v0,%r1), 0
+	vgeg	%v10, 1000(%v19,%r7), 1
+
+#CHECK: vgfmab  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x00,0x00,0x00,0xbc]
+#CHECK: vgfmab  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xbc]
+#CHECK: vgfmab  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xbc]
+#CHECK: vgfmab  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xbc]
+#CHECK: vgfmab  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xbc]
+#CHECK: vgfmab  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xbc]
+
+	vgfmab	%v0, %v0, %v0, %v0
+	vgfmab	%v0, %v0, %v0, %v31
+	vgfmab	%v0, %v0, %v31, %v0
+	vgfmab	%v0, %v31, %v0, %v0
+	vgfmab	%v31, %v0, %v0, %v0
+	vgfmab	%v13, %v17, %v21, %v25
+
+#CHECK: vgfmaf  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x02,0x00,0x00,0xbc]
+#CHECK: vgfmaf  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xbc]
+#CHECK: vgfmaf  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xbc]
+#CHECK: vgfmaf  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xbc]
+#CHECK: vgfmaf  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xbc]
+#CHECK: vgfmaf  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xbc]
+
+	vgfmaf	%v0, %v0, %v0, %v0
+	vgfmaf	%v0, %v0, %v0, %v31
+	vgfmaf	%v0, %v0, %v31, %v0
+	vgfmaf	%v0, %v31, %v0, %v0
+	vgfmaf	%v31, %v0, %v0, %v0
+	vgfmaf	%v13, %v17, %v21, %v25
+
+#CHECK: vgfmag  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x03,0x00,0x00,0xbc]
+#CHECK: vgfmag  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x03,0x00,0xf1,0xbc]
+#CHECK: vgfmag  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf3,0x00,0x02,0xbc]
+#CHECK: vgfmag  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x03,0x00,0x04,0xbc]
+#CHECK: vgfmag  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x03,0x00,0x08,0xbc]
+#CHECK: vgfmag  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x53,0x00,0x97,0xbc]
+
+	vgfmag	%v0, %v0, %v0, %v0
+	vgfmag	%v0, %v0, %v0, %v31
+	vgfmag	%v0, %v0, %v31, %v0
+	vgfmag	%v0, %v31, %v0, %v0
+	vgfmag	%v31, %v0, %v0, %v0
+	vgfmag	%v13, %v17, %v21, %v25
+
+#CHECK: vgfmah  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x01,0x00,0x00,0xbc]
+#CHECK: vgfmah  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xbc]
+#CHECK: vgfmah  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xbc]
+#CHECK: vgfmah  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xbc]
+#CHECK: vgfmah  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xbc]
+#CHECK: vgfmah  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xbc]
+
+	vgfmah	%v0, %v0, %v0, %v0
+	vgfmah	%v0, %v0, %v0, %v31
+	vgfmah	%v0, %v0, %v31, %v0
+	vgfmah	%v0, %v31, %v0, %v0
+	vgfmah	%v31, %v0, %v0, %v0
+	vgfmah	%v13, %v17, %v21, %v25
+
+#CHECK: vgfmb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xb4]
+#CHECK: vgfmb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xb4]
+#CHECK: vgfmb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xb4]
+#CHECK: vgfmb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xb4]
+#CHECK: vgfmb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xb4]
+
+	vgfmb	%v0, %v0, %v0
+	vgfmb	%v0, %v0, %v31
+	vgfmb	%v0, %v31, %v0
+	vgfmb	%v31, %v0, %v0
+	vgfmb	%v18, %v3, %v20
+
+#CHECK: vgfmf   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xb4]
+#CHECK: vgfmf   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xb4]
+#CHECK: vgfmf   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xb4]
+#CHECK: vgfmf   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xb4]
+#CHECK: vgfmf   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xb4]
+
+	vgfmf	%v0, %v0, %v0
+	vgfmf	%v0, %v0, %v31
+	vgfmf	%v0, %v31, %v0
+	vgfmf	%v31, %v0, %v0
+	vgfmf	%v18, %v3, %v20
+
+#CHECK: vgfmg   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xb4]
+#CHECK: vgfmg   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xb4]
+#CHECK: vgfmg   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xb4]
+#CHECK: vgfmg   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xb4]
+#CHECK: vgfmg   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xb4]
+
+	vgfmg	%v0, %v0, %v0
+	vgfmg	%v0, %v0, %v31
+	vgfmg	%v0, %v31, %v0
+	vgfmg	%v31, %v0, %v0
+	vgfmg	%v18, %v3, %v20
+
+#CHECK: vgfmh   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xb4]
+#CHECK: vgfmh   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xb4]
+#CHECK: vgfmh   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xb4]
+#CHECK: vgfmh   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xb4]
+#CHECK: vgfmh   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xb4]
+
+	vgfmh	%v0, %v0, %v0
+	vgfmh	%v0, %v0, %v31
+	vgfmh	%v0, %v31, %v0
+	vgfmh	%v31, %v0, %v0
+	vgfmh	%v18, %v3, %v20
+
+#CHECK: vgmb    %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x46]
+#CHECK: vgmb    %v0, 0, 255             # encoding: [0xe7,0x00,0x00,0xff,0x00,0x46]
+#CHECK: vgmb    %v0, 255, 0             # encoding: [0xe7,0x00,0xff,0x00,0x00,0x46]
+#CHECK: vgmb    %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x46]
+#CHECK: vgmb    %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x46]
+#CHECK: vgmb    %v21, 2, 3              # encoding: [0xe7,0x50,0x02,0x03,0x08,0x46]
+
+	vgmb	%v0, 0, 0
+	vgmb	%v0, 0, 255
+	vgmb	%v0, 255, 0
+	vgmb	%v15, 0, 0
+	vgmb	%v31, 0, 0
+	vgmb	%v21, 2, 3
+
+#CHECK: vgmf    %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x20,0x46]
+#CHECK: vgmf    %v0, 0, 255             # encoding: [0xe7,0x00,0x00,0xff,0x20,0x46]
+#CHECK: vgmf    %v0, 255, 0             # encoding: [0xe7,0x00,0xff,0x00,0x20,0x46]
+#CHECK: vgmf    %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x46]
+#CHECK: vgmf    %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x46]
+#CHECK: vgmf    %v21, 2, 3              # encoding: [0xe7,0x50,0x02,0x03,0x28,0x46]
+
+	vgmf	%v0, 0, 0
+	vgmf	%v0, 0, 255
+	vgmf	%v0, 255, 0
+	vgmf	%v15, 0, 0
+	vgmf	%v31, 0, 0
+	vgmf	%v21, 2, 3
+
+#CHECK: vgmg    %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x30,0x46]
+#CHECK: vgmg    %v0, 0, 255             # encoding: [0xe7,0x00,0x00,0xff,0x30,0x46]
+#CHECK: vgmg    %v0, 255, 0             # encoding: [0xe7,0x00,0xff,0x00,0x30,0x46]
+#CHECK: vgmg    %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x46]
+#CHECK: vgmg    %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x46]
+#CHECK: vgmg    %v21, 2, 3              # encoding: [0xe7,0x50,0x02,0x03,0x38,0x46]
+
+	vgmg	%v0, 0, 0
+	vgmg	%v0, 0, 255
+	vgmg	%v0, 255, 0
+	vgmg	%v15, 0, 0
+	vgmg	%v31, 0, 0
+	vgmg	%v21, 2, 3
+
+#CHECK: vgmh    %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x10,0x46]
+#CHECK: vgmh    %v0, 0, 255             # encoding: [0xe7,0x00,0x00,0xff,0x10,0x46]
+#CHECK: vgmh    %v0, 255, 0             # encoding: [0xe7,0x00,0xff,0x00,0x10,0x46]
+#CHECK: vgmh    %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x46]
+#CHECK: vgmh    %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x46]
+#CHECK: vgmh    %v21, 2, 3              # encoding: [0xe7,0x50,0x02,0x03,0x18,0x46]
+
+	vgmh	%v0, 0, 0
+	vgmh	%v0, 0, 255
+	vgmh	%v0, 255, 0
+	vgmh	%v15, 0, 0
+	vgmh	%v31, 0, 0
+	vgmh	%v21, 2, 3
+
+#CHECK: vl      %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x00,0x06]
+#CHECK: vl      %v0, 4095               # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x06]
+#CHECK: vl      %v0, 0(%r15)            # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x06]
+#CHECK: vl      %v0, 0(%r15,%r1)        # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x06]
+#CHECK: vl      %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x06]
+#CHECK: vl      %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x06]
+#CHECK: vl      %v18, 1383(%r3,%r4)     # encoding: [0xe7,0x23,0x45,0x67,0x08,0x06]
+
+	vl	%v0, 0
+	vl	%v0, 4095
+	vl	%v0, 0(%r15)
+	vl	%v0, 0(%r15,%r1)
+	vl	%v15, 0
+	vl	%v31, 0
+	vl	%v18, 0x567(%r3,%r4)
+
+#CHECK: vlbb    %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x07]
+#CHECK: vlbb    %v0, 0, 15              # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x07]
+#CHECK: vlbb    %v0, 4095, 0            # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x07]
+#CHECK: vlbb    %v0, 0(%r15), 0         # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x07]
+#CHECK: vlbb    %v0, 0(%r15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x07]
+#CHECK: vlbb    %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x07]
+#CHECK: vlbb    %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x07]
+#CHECK: vlbb    %v18, 1383(%r3,%r4), 8  # encoding: [0xe7,0x23,0x45,0x67,0x88,0x07]
+
+	vlbb	%v0, 0, 0
+	vlbb	%v0, 0, 15
+	vlbb	%v0, 4095, 0
+	vlbb	%v0, 0(%r15), 0
+	vlbb	%v0, 0(%r15,%r1), 0
+	vlbb	%v15, 0, 0
+	vlbb	%v31, 0, 0
+	vlbb	%v18, 1383(%r3,%r4), 8
+
+#CHECK: vlcb    %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x00,0xde]
+#CHECK: vlcb    %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xde]
+#CHECK: vlcb    %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xde]
+#CHECK: vlcb    %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xde]
+#CHECK: vlcb    %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xde]
+#CHECK: vlcb    %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xde]
+
+	vlcb	%v0, %v0
+	vlcb	%v0, %v15
+	vlcb	%v0, %v31
+	vlcb	%v15, %v0
+	vlcb	%v31, %v0
+	vlcb	%v14, %v17
+
+#CHECK: vlcf    %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x20,0xde]
+#CHECK: vlcf    %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xde]
+#CHECK: vlcf    %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xde]
+#CHECK: vlcf    %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xde]
+#CHECK: vlcf    %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xde]
+#CHECK: vlcf    %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xde]
+
+	vlcf	%v0, %v0
+	vlcf	%v0, %v15
+	vlcf	%v0, %v31
+	vlcf	%v15, %v0
+	vlcf	%v31, %v0
+	vlcf	%v14, %v17
+
+#CHECK: vlcg    %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x30,0xde]
+#CHECK: vlcg    %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xde]
+#CHECK: vlcg    %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xde]
+#CHECK: vlcg    %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xde]
+#CHECK: vlcg    %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xde]
+#CHECK: vlcg    %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xde]
+
+	vlcg	%v0, %v0
+	vlcg	%v0, %v15
+	vlcg	%v0, %v31
+	vlcg	%v15, %v0
+	vlcg	%v31, %v0
+	vlcg	%v14, %v17
+
+#CHECK: vlch    %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x10,0xde]
+#CHECK: vlch    %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xde]
+#CHECK: vlch    %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xde]
+#CHECK: vlch    %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xde]
+#CHECK: vlch    %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xde]
+#CHECK: vlch    %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xde]
+
+	vlch	%v0, %v0
+	vlch	%v0, %v15
+	vlch	%v0, %v31
+	vlch	%v15, %v0
+	vlch	%v31, %v0
+	vlch	%v14, %v17
+
+#CHECK: vldeb   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x20,0xc4]
+#CHECK: vldeb   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xc4]
+#CHECK: vldeb   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xc4]
+#CHECK: vldeb   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xc4]
+#CHECK: vldeb   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xc4]
+#CHECK: vldeb   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xc4]
+
+	vldeb	%v0, %v0
+	vldeb	%v0, %v15
+	vldeb	%v0, %v31
+	vldeb	%v15, %v0
+	vldeb	%v31, %v0
+	vldeb	%v14, %v17
+
+#CHECK: vleb    %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x00]
+#CHECK: vleb    %v0, 0, 15              # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x00]
+#CHECK: vleb    %v0, 4095, 0            # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x00]
+#CHECK: vleb    %v0, 0(%r15), 0         # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x00]
+#CHECK: vleb    %v0, 0(%r15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x00]
+#CHECK: vleb    %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x00]
+#CHECK: vleb    %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x00]
+#CHECK: vleb    %v18, 1383(%r3,%r4), 8  # encoding: [0xe7,0x23,0x45,0x67,0x88,0x00]
+
+	vleb	%v0, 0, 0
+	vleb	%v0, 0, 15
+	vleb	%v0, 4095, 0
+	vleb	%v0, 0(%r15), 0
+	vleb	%v0, 0(%r15,%r1), 0
+	vleb	%v15, 0, 0
+	vleb	%v31, 0, 0
+	vleb	%v18, 1383(%r3,%r4), 8
+
+#CHECK: vledb   %v0, %v0, 0, 0          # encoding: [0xe7,0x00,0x00,0x00,0x30,0xc5]
+#CHECK: vledb   %v0, %v0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf0,0x30,0xc5]
+#CHECK: vledb   %v0, %v0, 4, 0          # encoding: [0xe7,0x00,0x00,0x04,0x30,0xc5]
+#CHECK: vledb   %v0, %v0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc5]
+#CHECK: vledb   %v0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xc5]
+#CHECK: vledb   %v31, %v0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xc5]
+#CHECK: vledb   %v14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xa4,0x34,0xc5]
+
+	vledb	%v0, %v0, 0, 0
+	vledb	%v0, %v0, 0, 15
+	vledb	%v0, %v0, 4, 0
+	vledb	%v0, %v0, 12, 0
+	vledb	%v0, %v31, 0, 0
+	vledb	%v31, %v0, 0, 0
+	vledb	%v14, %v17, 4, 10
+
+#CHECK: vlef    %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x03]
+#CHECK: vlef    %v0, 0, 3               # encoding: [0xe7,0x00,0x00,0x00,0x30,0x03]
+#CHECK: vlef    %v0, 4095, 0            # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x03]
+#CHECK: vlef    %v0, 0(%r15), 0         # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x03]
+#CHECK: vlef    %v0, 0(%r15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x03]
+#CHECK: vlef    %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x03]
+#CHECK: vlef    %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x03]
+#CHECK: vlef    %v18, 1383(%r3,%r4), 2  # encoding: [0xe7,0x23,0x45,0x67,0x28,0x03]
+
+	vlef	%v0, 0, 0
+	vlef	%v0, 0, 3
+	vlef	%v0, 4095, 0
+	vlef	%v0, 0(%r15), 0
+	vlef	%v0, 0(%r15,%r1), 0
+	vlef	%v15, 0, 0
+	vlef	%v31, 0, 0
+	vlef	%v18, 1383(%r3,%r4), 2
+
+#CHECK: vleg    %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x02]
+#CHECK: vleg    %v0, 0, 1               # encoding: [0xe7,0x00,0x00,0x00,0x10,0x02]
+#CHECK: vleg    %v0, 4095, 0            # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x02]
+#CHECK: vleg    %v0, 0(%r15), 0         # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x02]
+#CHECK: vleg    %v0, 0(%r15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x02]
+#CHECK: vleg    %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x02]
+#CHECK: vleg    %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x02]
+#CHECK: vleg    %v18, 1383(%r3,%r4), 1  # encoding: [0xe7,0x23,0x45,0x67,0x18,0x02]
+
+	vleg	%v0, 0, 0
+	vleg	%v0, 0, 1
+	vleg	%v0, 4095, 0
+	vleg	%v0, 0(%r15), 0
+	vleg	%v0, 0(%r15,%r1), 0
+	vleg	%v15, 0, 0
+	vleg	%v31, 0, 0
+	vleg	%v18, 1383(%r3,%r4), 1
+
+#CHECK: vleh    %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x01]
+#CHECK: vleh    %v0, 0, 7               # encoding: [0xe7,0x00,0x00,0x00,0x70,0x01]
+#CHECK: vleh    %v0, 4095, 0            # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x01]
+#CHECK: vleh    %v0, 0(%r15), 0         # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x01]
+#CHECK: vleh    %v0, 0(%r15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x01]
+#CHECK: vleh    %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x01]
+#CHECK: vleh    %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x01]
+#CHECK: vleh    %v18, 1383(%r3,%r4), 4  # encoding: [0xe7,0x23,0x45,0x67,0x48,0x01]
+
+	vleh	%v0, 0, 0
+	vleh	%v0, 0, 7
+	vleh	%v0, 4095, 0
+	vleh	%v0, 0(%r15), 0
+	vleh	%v0, 0(%r15,%r1), 0
+	vleh	%v15, 0, 0
+	vleh	%v31, 0, 0
+	vleh	%v18, 1383(%r3,%r4), 4
+
+#CHECK: vleib   %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x40]
+#CHECK: vleib   %v0, 0, 15              # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x40]
+#CHECK: vleib   %v0, -32768, 0          # encoding: [0xe7,0x00,0x80,0x00,0x00,0x40]
+#CHECK: vleib   %v0, 32767, 0           # encoding: [0xe7,0x00,0x7f,0xff,0x00,0x40]
+#CHECK: vleib   %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x40]
+#CHECK: vleib   %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x40]
+#CHECK: vleib   %v18, 13398, 11         # encoding: [0xe7,0x20,0x34,0x56,0xb8,0x40]
+
+	vleib	%v0, 0, 0
+	vleib	%v0, 0, 15
+	vleib	%v0, -32768, 0
+	vleib	%v0, 32767, 0
+	vleib	%v15, 0, 0
+	vleib	%v31, 0, 0
+	vleib	%v18, 0x3456, 11
+
+#CHECK: vleif   %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x43]
+#CHECK: vleif   %v0, 0, 3               # encoding: [0xe7,0x00,0x00,0x00,0x30,0x43]
+#CHECK: vleif   %v0, -32768, 0          # encoding: [0xe7,0x00,0x80,0x00,0x00,0x43]
+#CHECK: vleif   %v0, 32767, 0           # encoding: [0xe7,0x00,0x7f,0xff,0x00,0x43]
+#CHECK: vleif   %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x43]
+#CHECK: vleif   %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x43]
+#CHECK: vleif   %v18, 13398, 3          # encoding: [0xe7,0x20,0x34,0x56,0x38,0x43]
+
+	vleif	%v0, 0, 0
+	vleif	%v0, 0, 3
+	vleif	%v0, -32768, 0
+	vleif	%v0, 32767, 0
+	vleif	%v15, 0, 0
+	vleif	%v31, 0, 0
+	vleif	%v18, 0x3456, 3
+
+#CHECK: vleig   %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x42]
+#CHECK: vleig   %v0, 0, 1               # encoding: [0xe7,0x00,0x00,0x00,0x10,0x42]
+#CHECK: vleig   %v0, -32768, 0          # encoding: [0xe7,0x00,0x80,0x00,0x00,0x42]
+#CHECK: vleig   %v0, 32767, 0           # encoding: [0xe7,0x00,0x7f,0xff,0x00,0x42]
+#CHECK: vleig   %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x42]
+#CHECK: vleig   %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x42]
+#CHECK: vleig   %v18, 13398, 1          # encoding: [0xe7,0x20,0x34,0x56,0x18,0x42]
+
+	vleig	%v0, 0, 0
+	vleig	%v0, 0, 1
+	vleig	%v0, -32768, 0
+	vleig	%v0, 32767, 0
+	vleig	%v15, 0, 0
+	vleig	%v31, 0, 0
+	vleig	%v18, 0x3456, 1
+
+#CHECK: vleih   %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x41]
+#CHECK: vleih   %v0, 0, 7               # encoding: [0xe7,0x00,0x00,0x00,0x70,0x41]
+#CHECK: vleih   %v0, -32768, 0          # encoding: [0xe7,0x00,0x80,0x00,0x00,0x41]
+#CHECK: vleih   %v0, 32767, 0           # encoding: [0xe7,0x00,0x7f,0xff,0x00,0x41]
+#CHECK: vleih   %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x41]
+#CHECK: vleih   %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x41]
+#CHECK: vleih   %v18, 13398, 7          # encoding: [0xe7,0x20,0x34,0x56,0x78,0x41]
+
+	vleih	%v0, 0, 0
+	vleih	%v0, 0, 7
+	vleih	%v0, -32768, 0
+	vleih	%v0, 32767, 0
+	vleih	%v15, 0, 0
+	vleih	%v31, 0, 0
+	vleih	%v18, 0x3456, 7
+
+#CHECK: vlgvb   %r0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x00,0x21]
+#CHECK: vlgvb   %r0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x21]
+#CHECK: vlgvb   %r0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x21]
+#CHECK: vlgvb   %r0, %v15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x21]
+#CHECK: vlgvb   %r0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x21]
+#CHECK: vlgvb   %r15, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x21]
+#CHECK: vlgvb   %r2, %v19, 1383(%r4)    # encoding: [0xe7,0x23,0x45,0x67,0x04,0x21]
+
+	vlgvb	%r0, %v0, 0
+	vlgvb	%r0, %v0, 4095
+	vlgvb	%r0, %v0, 0(%r15)
+	vlgvb	%r0, %v15, 0
+	vlgvb	%r0, %v31, 0
+	vlgvb	%r15, %v0, 0
+	vlgvb	%r2, %v19, 1383(%r4)
+
+#CHECK: vlgvf   %r0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x20,0x21]
+#CHECK: vlgvf   %r0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x21]
+#CHECK: vlgvf   %r0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x21]
+#CHECK: vlgvf   %r0, %v15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x21]
+#CHECK: vlgvf   %r0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x21]
+#CHECK: vlgvf   %r15, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x21]
+#CHECK: vlgvf   %r2, %v19, 1383(%r4)    # encoding: [0xe7,0x23,0x45,0x67,0x24,0x21]
+
+	vlgvf	%r0, %v0, 0
+	vlgvf	%r0, %v0, 4095
+	vlgvf	%r0, %v0, 0(%r15)
+	vlgvf	%r0, %v15, 0
+	vlgvf	%r0, %v31, 0
+	vlgvf	%r15, %v0, 0
+	vlgvf	%r2, %v19, 1383(%r4)
+
+#CHECK: vlgvg   %r0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x30,0x21]
+#CHECK: vlgvg   %r0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x21]
+#CHECK: vlgvg   %r0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x21]
+#CHECK: vlgvg   %r0, %v15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x21]
+#CHECK: vlgvg   %r0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x21]
+#CHECK: vlgvg   %r15, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x21]
+#CHECK: vlgvg   %r2, %v19, 1383(%r4)    # encoding: [0xe7,0x23,0x45,0x67,0x34,0x21]
+
+	vlgvg	%r0, %v0, 0
+	vlgvg	%r0, %v0, 4095
+	vlgvg	%r0, %v0, 0(%r15)
+	vlgvg	%r0, %v15, 0
+	vlgvg	%r0, %v31, 0
+	vlgvg	%r15, %v0, 0
+	vlgvg	%r2, %v19, 1383(%r4)
+
+#CHECK: vlgvh   %r0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x10,0x21]
+#CHECK: vlgvh   %r0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x21]
+#CHECK: vlgvh   %r0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x21]
+#CHECK: vlgvh   %r0, %v15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x21]
+#CHECK: vlgvh   %r0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x21]
+#CHECK: vlgvh   %r15, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x21]
+#CHECK: vlgvh   %r2, %v19, 1383(%r4)    # encoding: [0xe7,0x23,0x45,0x67,0x14,0x21]
+
+	vlgvh	%r0, %v0, 0
+	vlgvh	%r0, %v0, 4095
+	vlgvh	%r0, %v0, 0(%r15)
+	vlgvh	%r0, %v15, 0
+	vlgvh	%r0, %v31, 0
+	vlgvh	%r15, %v0, 0
+	vlgvh	%r2, %v19, 1383(%r4)
+
+#CHECK: vll     %v0, %r0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x00,0x37]
+#CHECK: vll     %v0, %r0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x37]
+#CHECK: vll     %v0, %r0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x37]
+#CHECK: vll     %v0, %r15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x37]
+#CHECK: vll     %v15, %r0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x37]
+#CHECK: vll     %v31, %r0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x37]
+#CHECK: vll     %v18, %r3, 1383(%r4)    # encoding: [0xe7,0x23,0x45,0x67,0x08,0x37]
+
+	vll	%v0, %r0, 0
+	vll	%v0, %r0, 4095
+	vll	%v0, %r0, 0(%r15)
+	vll	%v0, %r15, 0
+	vll	%v15, %r0, 0
+	vll	%v31, %r0, 0
+	vll	%v18, %r3, 1383(%r4)
+
+#CHECK: vllezb  %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x00,0x04]
+#CHECK: vllezb  %v0, 4095               # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x04]
+#CHECK: vllezb  %v0, 0(%r15)            # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x04]
+#CHECK: vllezb  %v0, 0(%r15,%r1)        # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x04]
+#CHECK: vllezb  %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x04]
+#CHECK: vllezb  %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x04]
+#CHECK: vllezb  %v18, 1383(%r3,%r4)     # encoding: [0xe7,0x23,0x45,0x67,0x08,0x04]
+
+	vllezb	%v0, 0
+	vllezb	%v0, 4095
+	vllezb	%v0, 0(%r15)
+	vllezb	%v0, 0(%r15,%r1)
+	vllezb	%v15, 0
+	vllezb	%v31, 0
+	vllezb	%v18, 0x567(%r3,%r4)
+
+#CHECK: vllezf  %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x20,0x04]
+#CHECK: vllezf  %v0, 4095               # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x04]
+#CHECK: vllezf  %v0, 0(%r15)            # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x04]
+#CHECK: vllezf  %v0, 0(%r15,%r1)        # encoding: [0xe7,0x0f,0x10,0x00,0x20,0x04]
+#CHECK: vllezf  %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x04]
+#CHECK: vllezf  %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x04]
+#CHECK: vllezf  %v18, 1383(%r3,%r4)     # encoding: [0xe7,0x23,0x45,0x67,0x28,0x04]
+
+	vllezf	%v0, 0
+	vllezf	%v0, 4095
+	vllezf	%v0, 0(%r15)
+	vllezf	%v0, 0(%r15,%r1)
+	vllezf	%v15, 0
+	vllezf	%v31, 0
+	vllezf	%v18, 0x567(%r3,%r4)
+
+#CHECK: vllezg  %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x30,0x04]
+#CHECK: vllezg  %v0, 4095               # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x04]
+#CHECK: vllezg  %v0, 0(%r15)            # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x04]
+#CHECK: vllezg  %v0, 0(%r15,%r1)        # encoding: [0xe7,0x0f,0x10,0x00,0x30,0x04]
+#CHECK: vllezg  %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x04]
+#CHECK: vllezg  %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x04]
+#CHECK: vllezg  %v18, 1383(%r3,%r4)     # encoding: [0xe7,0x23,0x45,0x67,0x38,0x04]
+
+	vllezg	%v0, 0
+	vllezg	%v0, 4095
+	vllezg	%v0, 0(%r15)
+	vllezg	%v0, 0(%r15,%r1)
+	vllezg	%v15, 0
+	vllezg	%v31, 0
+	vllezg	%v18, 0x567(%r3,%r4)
+
+#CHECK: vllezh  %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x10,0x04]
+#CHECK: vllezh  %v0, 4095               # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x04]
+#CHECK: vllezh  %v0, 0(%r15)            # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x04]
+#CHECK: vllezh  %v0, 0(%r15,%r1)        # encoding: [0xe7,0x0f,0x10,0x00,0x10,0x04]
+#CHECK: vllezh  %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x04]
+#CHECK: vllezh  %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x04]
+#CHECK: vllezh  %v18, 1383(%r3,%r4)     # encoding: [0xe7,0x23,0x45,0x67,0x18,0x04]
+
+	vllezh	%v0, 0
+	vllezh	%v0, 4095
+	vllezh	%v0, 0(%r15)
+	vllezh	%v0, 0(%r15,%r1)
+	vllezh	%v15, 0
+	vllezh	%v31, 0
+	vllezh	%v18, 0x567(%r3,%r4)
+
+#CHECK: vlm     %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x00,0x36]
+#CHECK: vlm     %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x36]
+#CHECK: vlm     %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x36]
+#CHECK: vlm     %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x36]
+#CHECK: vlm     %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x36]
+#CHECK: vlm     %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x04,0x36]
+
+	vlm	%v0, %v0, 0
+	vlm	%v0, %v0, 4095
+	vlm	%v0, %v0, 0(%r15)
+	vlm	%v0, %v31, 0
+	vlm	%v31, %v0, 0
+	vlm	%v14, %v17, 1074(%r5)
+
+#CHECK: vlpb    %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x00,0xdf]
+#CHECK: vlpb    %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xdf]
+#CHECK: vlpb    %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xdf]
+#CHECK: vlpb    %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xdf]
+#CHECK: vlpb    %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xdf]
+#CHECK: vlpb    %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xdf]
+
+	vlpb	%v0, %v0
+	vlpb	%v0, %v15
+	vlpb	%v0, %v31
+	vlpb	%v15, %v0
+	vlpb	%v31, %v0
+	vlpb	%v14, %v17
+
+#CHECK: vlpf    %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x20,0xdf]
+#CHECK: vlpf    %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xdf]
+#CHECK: vlpf    %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xdf]
+#CHECK: vlpf    %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xdf]
+#CHECK: vlpf    %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xdf]
+#CHECK: vlpf    %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xdf]
+
+	vlpf	%v0, %v0
+	vlpf	%v0, %v15
+	vlpf	%v0, %v31
+	vlpf	%v15, %v0
+	vlpf	%v31, %v0
+	vlpf	%v14, %v17
+
+#CHECK: vlpg    %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x30,0xdf]
+#CHECK: vlpg    %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xdf]
+#CHECK: vlpg    %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xdf]
+#CHECK: vlpg    %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xdf]
+#CHECK: vlpg    %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xdf]
+#CHECK: vlpg    %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xdf]
+
+	vlpg	%v0, %v0
+	vlpg	%v0, %v15
+	vlpg	%v0, %v31
+	vlpg	%v15, %v0
+	vlpg	%v31, %v0
+	vlpg	%v14, %v17
+
+#CHECK: vlph    %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x10,0xdf]
+#CHECK: vlph    %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xdf]
+#CHECK: vlph    %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xdf]
+#CHECK: vlph    %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xdf]
+#CHECK: vlph    %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xdf]
+#CHECK: vlph    %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xdf]
+
+	vlph	%v0, %v0
+	vlph	%v0, %v15
+	vlph	%v0, %v31
+	vlph	%v15, %v0
+	vlph	%v31, %v0
+	vlph	%v14, %v17
+
+#CHECK: vlr     %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x00,0x56]
+#CHECK: vlr     %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x56]
+#CHECK: vlr     %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x56]
+#CHECK: vlr     %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x56]
+#CHECK: vlr     %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x56]
+#CHECK: vlr     %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x04,0x56]
+
+	vlr	%v0, %v0
+	vlr	%v0, %v15
+	vlr	%v0, %v31
+	vlr	%v15, %v0
+	vlr	%v31, %v0
+	vlr	%v14, %v17
+
+#CHECK: vlrepb  %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x00,0x05]
+#CHECK: vlrepb  %v0, 4095               # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x05]
+#CHECK: vlrepb  %v0, 0(%r15)            # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x05]
+#CHECK: vlrepb  %v0, 0(%r15,%r1)        # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x05]
+#CHECK: vlrepb  %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x05]
+#CHECK: vlrepb  %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x05]
+#CHECK: vlrepb  %v18, 1383(%r3,%r4)     # encoding: [0xe7,0x23,0x45,0x67,0x08,0x05]
+
+	vlrepb	%v0, 0
+	vlrepb	%v0, 4095
+	vlrepb	%v0, 0(%r15)
+	vlrepb	%v0, 0(%r15,%r1)
+	vlrepb	%v15, 0
+	vlrepb	%v31, 0
+	vlrepb	%v18, 0x567(%r3,%r4)
+
+#CHECK: vlrepf  %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x20,0x05]
+#CHECK: vlrepf  %v0, 4095               # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x05]
+#CHECK: vlrepf  %v0, 0(%r15)            # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x05]
+#CHECK: vlrepf  %v0, 0(%r15,%r1)        # encoding: [0xe7,0x0f,0x10,0x00,0x20,0x05]
+#CHECK: vlrepf  %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x05]
+#CHECK: vlrepf  %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x05]
+#CHECK: vlrepf  %v18, 1383(%r3,%r4)     # encoding: [0xe7,0x23,0x45,0x67,0x28,0x05]
+
+	vlrepf	%v0, 0
+	vlrepf	%v0, 4095
+	vlrepf	%v0, 0(%r15)
+	vlrepf	%v0, 0(%r15,%r1)
+	vlrepf	%v15, 0
+	vlrepf	%v31, 0
+	vlrepf	%v18, 0x567(%r3,%r4)
+
+#CHECK: vlrepg  %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x30,0x05]
+#CHECK: vlrepg  %v0, 4095               # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x05]
+#CHECK: vlrepg  %v0, 0(%r15)            # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x05]
+#CHECK: vlrepg  %v0, 0(%r15,%r1)        # encoding: [0xe7,0x0f,0x10,0x00,0x30,0x05]
+#CHECK: vlrepg  %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x05]
+#CHECK: vlrepg  %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x05]
+#CHECK: vlrepg  %v18, 1383(%r3,%r4)     # encoding: [0xe7,0x23,0x45,0x67,0x38,0x05]
+
+	vlrepg	%v0, 0
+	vlrepg	%v0, 4095
+	vlrepg	%v0, 0(%r15)
+	vlrepg	%v0, 0(%r15,%r1)
+	vlrepg	%v15, 0
+	vlrepg	%v31, 0
+	vlrepg	%v18, 0x567(%r3,%r4)
+
+#CHECK: vlreph  %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x10,0x05]
+#CHECK: vlreph  %v0, 4095               # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x05]
+#CHECK: vlreph  %v0, 0(%r15)            # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x05]
+#CHECK: vlreph  %v0, 0(%r15,%r1)        # encoding: [0xe7,0x0f,0x10,0x00,0x10,0x05]
+#CHECK: vlreph  %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x05]
+#CHECK: vlreph  %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x05]
+#CHECK: vlreph  %v18, 1383(%r3,%r4)     # encoding: [0xe7,0x23,0x45,0x67,0x18,0x05]
+
+	vlreph	%v0, 0
+	vlreph	%v0, 4095
+	vlreph	%v0, 0(%r15)
+	vlreph	%v0, 0(%r15,%r1)
+	vlreph	%v15, 0
+	vlreph	%v31, 0
+	vlreph	%v18, 0x567(%r3,%r4)
+
+#CHECK: vlvgb   %v0, %r0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x00,0x22]
+#CHECK: vlvgb   %v0, %r0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x22]
+#CHECK: vlvgb   %v0, %r0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x22]
+#CHECK: vlvgb   %v0, %r15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x22]
+#CHECK: vlvgb   %v15, %r0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x22]
+#CHECK: vlvgb   %v31, %r0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x22]
+#CHECK: vlvgb   %v18, %r3, 1383(%r4)    # encoding: [0xe7,0x23,0x45,0x67,0x08,0x22]
+
+	vlvgb	%v0, %r0, 0
+	vlvgb	%v0, %r0, 4095
+	vlvgb	%v0, %r0, 0(%r15)
+	vlvgb	%v0, %r15, 0
+	vlvgb	%v15, %r0, 0
+	vlvgb	%v31, %r0, 0
+	vlvgb	%v18, %r3, 1383(%r4)
+
+#CHECK: vlvgf   %v0, %r0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x20,0x22]
+#CHECK: vlvgf   %v0, %r0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x22]
+#CHECK: vlvgf   %v0, %r0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x22]
+#CHECK: vlvgf   %v0, %r15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x22]
+#CHECK: vlvgf   %v15, %r0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x22]
+#CHECK: vlvgf   %v31, %r0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x22]
+#CHECK: vlvgf   %v18, %r3, 1383(%r4)    # encoding: [0xe7,0x23,0x45,0x67,0x28,0x22]
+
+	vlvgf	%v0, %r0, 0
+	vlvgf	%v0, %r0, 4095
+	vlvgf	%v0, %r0, 0(%r15)
+	vlvgf	%v0, %r15, 0
+	vlvgf	%v15, %r0, 0
+	vlvgf	%v31, %r0, 0
+	vlvgf	%v18, %r3, 1383(%r4)
+
+#CHECK: vlvgg   %v0, %r0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x30,0x22]
+#CHECK: vlvgg   %v0, %r0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x22]
+#CHECK: vlvgg   %v0, %r0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x22]
+#CHECK: vlvgg   %v0, %r15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x22]
+#CHECK: vlvgg   %v15, %r0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x22]
+#CHECK: vlvgg   %v31, %r0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x22]
+#CHECK: vlvgg   %v18, %r3, 1383(%r4)    # encoding: [0xe7,0x23,0x45,0x67,0x38,0x22]
+
+	vlvgg	%v0, %r0, 0
+	vlvgg	%v0, %r0, 4095
+	vlvgg	%v0, %r0, 0(%r15)
+	vlvgg	%v0, %r15, 0
+	vlvgg	%v15, %r0, 0
+	vlvgg	%v31, %r0, 0
+	vlvgg	%v18, %r3, 1383(%r4)
+
+#CHECK: vlvgh   %v0, %r0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x10,0x22]
+#CHECK: vlvgh   %v0, %r0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x22]
+#CHECK: vlvgh   %v0, %r0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x22]
+#CHECK: vlvgh   %v0, %r15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x22]
+#CHECK: vlvgh   %v15, %r0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x22]
+#CHECK: vlvgh   %v31, %r0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x22]
+#CHECK: vlvgh   %v18, %r3, 1383(%r4)    # encoding: [0xe7,0x23,0x45,0x67,0x18,0x22]
+
+	vlvgh	%v0, %r0, 0
+	vlvgh	%v0, %r0, 4095
+	vlvgh	%v0, %r0, 0(%r15)
+	vlvgh	%v0, %r15, 0
+	vlvgh	%v15, %r0, 0
+	vlvgh	%v31, %r0, 0
+	vlvgh	%v18, %r3, 1383(%r4)
+
+#CHECK: vlvgp   %v0, %r0, %r0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x62]
+#CHECK: vlvgp   %v0, %r0, %r15          # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x62]
+#CHECK: vlvgp   %v0, %r15, %r0          # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x62]
+#CHECK: vlvgp   %v15, %r0, %r0          # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x62]
+#CHECK: vlvgp   %v31, %r0, %r0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x62]
+#CHECK: vlvgp   %v18, %r3, %r4          # encoding: [0xe7,0x23,0x40,0x00,0x08,0x62]
+
+	vlvgp	%v0, %r0, %r0
+	vlvgp	%v0, %r0, %r15
+	vlvgp	%v0, %r15, %r0
+	vlvgp	%v15, %r0, %r0
+	vlvgp	%v31, %r0, %r0
+	vlvgp	%v18, %r3, %r4
+
+#CHECK: vmaeb   %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x00,0x00,0x00,0xae]
+#CHECK: vmaeb   %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xae]
+#CHECK: vmaeb   %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xae]
+#CHECK: vmaeb   %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xae]
+#CHECK: vmaeb   %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xae]
+#CHECK: vmaeb   %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xae]
+
+	vmaeb	%v0, %v0, %v0, %v0
+	vmaeb	%v0, %v0, %v0, %v31
+	vmaeb	%v0, %v0, %v31, %v0
+	vmaeb	%v0, %v31, %v0, %v0
+	vmaeb	%v31, %v0, %v0, %v0
+	vmaeb	%v13, %v17, %v21, %v25
+
+#CHECK: vmaef   %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x02,0x00,0x00,0xae]
+#CHECK: vmaef   %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xae]
+#CHECK: vmaef   %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xae]
+#CHECK: vmaef   %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xae]
+#CHECK: vmaef   %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xae]
+#CHECK: vmaef   %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xae]
+
+	vmaef	%v0, %v0, %v0, %v0
+	vmaef	%v0, %v0, %v0, %v31
+	vmaef	%v0, %v0, %v31, %v0
+	vmaef	%v0, %v31, %v0, %v0
+	vmaef	%v31, %v0, %v0, %v0
+	vmaef	%v13, %v17, %v21, %v25
+
+#CHECK: vmaeh   %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x01,0x00,0x00,0xae]
+#CHECK: vmaeh   %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xae]
+#CHECK: vmaeh   %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xae]
+#CHECK: vmaeh   %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xae]
+#CHECK: vmaeh   %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xae]
+#CHECK: vmaeh   %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xae]
+
+	vmaeh	%v0, %v0, %v0, %v0
+	vmaeh	%v0, %v0, %v0, %v31
+	vmaeh	%v0, %v0, %v31, %v0
+	vmaeh	%v0, %v31, %v0, %v0
+	vmaeh	%v31, %v0, %v0, %v0
+	vmaeh	%v13, %v17, %v21, %v25
+
+#CHECK: vmahb   %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x00,0x00,0x00,0xab]
+#CHECK: vmahb   %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xab]
+#CHECK: vmahb   %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xab]
+#CHECK: vmahb   %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xab]
+#CHECK: vmahb   %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xab]
+#CHECK: vmahb   %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xab]
+
+	vmahb	%v0, %v0, %v0, %v0
+	vmahb	%v0, %v0, %v0, %v31
+	vmahb	%v0, %v0, %v31, %v0
+	vmahb	%v0, %v31, %v0, %v0
+	vmahb	%v31, %v0, %v0, %v0
+	vmahb	%v13, %v17, %v21, %v25
+
+#CHECK: vmahf   %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x02,0x00,0x00,0xab]
+#CHECK: vmahf   %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xab]
+#CHECK: vmahf   %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xab]
+#CHECK: vmahf   %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xab]
+#CHECK: vmahf   %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xab]
+#CHECK: vmahf   %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xab]
+
+	vmahf	%v0, %v0, %v0, %v0
+	vmahf	%v0, %v0, %v0, %v31
+	vmahf	%v0, %v0, %v31, %v0
+	vmahf	%v0, %v31, %v0, %v0
+	vmahf	%v31, %v0, %v0, %v0
+	vmahf	%v13, %v17, %v21, %v25
+
+#CHECK: vmahh   %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x01,0x00,0x00,0xab]
+#CHECK: vmahh   %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xab]
+#CHECK: vmahh   %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xab]
+#CHECK: vmahh   %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xab]
+#CHECK: vmahh   %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xab]
+#CHECK: vmahh   %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xab]
+
+	vmahh	%v0, %v0, %v0, %v0
+	vmahh	%v0, %v0, %v0, %v31
+	vmahh	%v0, %v0, %v31, %v0
+	vmahh	%v0, %v31, %v0, %v0
+	vmahh	%v31, %v0, %v0, %v0
+	vmahh	%v13, %v17, %v21, %v25
+
+#CHECK: vmalb   %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x00,0x00,0x00,0xaa]
+#CHECK: vmalb   %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xaa]
+#CHECK: vmalb   %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xaa]
+#CHECK: vmalb   %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xaa]
+#CHECK: vmalb   %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xaa]
+#CHECK: vmalb   %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xaa]
+
+	vmalb	%v0, %v0, %v0, %v0
+	vmalb	%v0, %v0, %v0, %v31
+	vmalb	%v0, %v0, %v31, %v0
+	vmalb	%v0, %v31, %v0, %v0
+	vmalb	%v31, %v0, %v0, %v0
+	vmalb	%v13, %v17, %v21, %v25
+
+#CHECK: vmaleb  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x00,0x00,0x00,0xac]
+#CHECK: vmaleb  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xac]
+#CHECK: vmaleb  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xac]
+#CHECK: vmaleb  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xac]
+#CHECK: vmaleb  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xac]
+#CHECK: vmaleb  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xac]
+
+	vmaleb	%v0, %v0, %v0, %v0
+	vmaleb	%v0, %v0, %v0, %v31
+	vmaleb	%v0, %v0, %v31, %v0
+	vmaleb	%v0, %v31, %v0, %v0
+	vmaleb	%v31, %v0, %v0, %v0
+	vmaleb	%v13, %v17, %v21, %v25
+
+#CHECK: vmalef  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x02,0x00,0x00,0xac]
+#CHECK: vmalef  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xac]
+#CHECK: vmalef  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xac]
+#CHECK: vmalef  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xac]
+#CHECK: vmalef  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xac]
+#CHECK: vmalef  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xac]
+
+	vmalef	%v0, %v0, %v0, %v0
+	vmalef	%v0, %v0, %v0, %v31
+	vmalef	%v0, %v0, %v31, %v0
+	vmalef	%v0, %v31, %v0, %v0
+	vmalef	%v31, %v0, %v0, %v0
+	vmalef	%v13, %v17, %v21, %v25
+
+#CHECK: vmaleh  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x01,0x00,0x00,0xac]
+#CHECK: vmaleh  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xac]
+#CHECK: vmaleh  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xac]
+#CHECK: vmaleh  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xac]
+#CHECK: vmaleh  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xac]
+#CHECK: vmaleh  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xac]
+
+	vmaleh	%v0, %v0, %v0, %v0
+	vmaleh	%v0, %v0, %v0, %v31
+	vmaleh	%v0, %v0, %v31, %v0
+	vmaleh	%v0, %v31, %v0, %v0
+	vmaleh	%v31, %v0, %v0, %v0
+	vmaleh	%v13, %v17, %v21, %v25
+
+#CHECK: vmalf   %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x02,0x00,0x00,0xaa]
+#CHECK: vmalf   %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xaa]
+#CHECK: vmalf   %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xaa]
+#CHECK: vmalf   %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xaa]
+#CHECK: vmalf   %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xaa]
+#CHECK: vmalf   %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xaa]
+
+	vmalf	%v0, %v0, %v0, %v0
+	vmalf	%v0, %v0, %v0, %v31
+	vmalf	%v0, %v0, %v31, %v0
+	vmalf	%v0, %v31, %v0, %v0
+	vmalf	%v31, %v0, %v0, %v0
+	vmalf	%v13, %v17, %v21, %v25
+
+#CHECK: vmalhb  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa9]
+#CHECK: vmalhb  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xa9]
+#CHECK: vmalhb  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa9]
+#CHECK: vmalhb  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa9]
+#CHECK: vmalhb  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa9]
+#CHECK: vmalhb  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xa9]
+
+	vmalhb	%v0, %v0, %v0, %v0
+	vmalhb	%v0, %v0, %v0, %v31
+	vmalhb	%v0, %v0, %v31, %v0
+	vmalhb	%v0, %v31, %v0, %v0
+	vmalhb	%v31, %v0, %v0, %v0
+	vmalhb	%v13, %v17, %v21, %v25
+
+#CHECK: vmalhf  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x02,0x00,0x00,0xa9]
+#CHECK: vmalhf  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xa9]
+#CHECK: vmalhf  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xa9]
+#CHECK: vmalhf  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xa9]
+#CHECK: vmalhf  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xa9]
+#CHECK: vmalhf  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xa9]
+
+	vmalhf	%v0, %v0, %v0, %v0
+	vmalhf	%v0, %v0, %v0, %v31
+	vmalhf	%v0, %v0, %v31, %v0
+	vmalhf	%v0, %v31, %v0, %v0
+	vmalhf	%v31, %v0, %v0, %v0
+	vmalhf	%v13, %v17, %v21, %v25
+
+#CHECK: vmalhh  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x01,0x00,0x00,0xa9]
+#CHECK: vmalhh  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xa9]
+#CHECK: vmalhh  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xa9]
+#CHECK: vmalhh  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xa9]
+#CHECK: vmalhh  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xa9]
+#CHECK: vmalhh  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xa9]
+
+	vmalhh	%v0, %v0, %v0, %v0
+	vmalhh	%v0, %v0, %v0, %v31
+	vmalhh	%v0, %v0, %v31, %v0
+	vmalhh	%v0, %v31, %v0, %v0
+	vmalhh	%v31, %v0, %v0, %v0
+	vmalhh	%v13, %v17, %v21, %v25
+
+#CHECK: vmalhw  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x01,0x00,0x00,0xaa]
+#CHECK: vmalhw  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xaa]
+#CHECK: vmalhw  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xaa]
+#CHECK: vmalhw  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xaa]
+#CHECK: vmalhw  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xaa]
+#CHECK: vmalhw  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xaa]
+
+	vmalhw	%v0, %v0, %v0, %v0
+	vmalhw	%v0, %v0, %v0, %v31
+	vmalhw	%v0, %v0, %v31, %v0
+	vmalhw	%v0, %v31, %v0, %v0
+	vmalhw	%v31, %v0, %v0, %v0
+	vmalhw	%v13, %v17, %v21, %v25
+
+#CHECK: vmalob  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x00,0x00,0x00,0xad]
+#CHECK: vmalob  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xad]
+#CHECK: vmalob  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xad]
+#CHECK: vmalob  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xad]
+#CHECK: vmalob  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xad]
+#CHECK: vmalob  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xad]
+
+	vmalob	%v0, %v0, %v0, %v0
+	vmalob	%v0, %v0, %v0, %v31
+	vmalob	%v0, %v0, %v31, %v0
+	vmalob	%v0, %v31, %v0, %v0
+	vmalob	%v31, %v0, %v0, %v0
+	vmalob	%v13, %v17, %v21, %v25
+
+#CHECK: vmalof  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x02,0x00,0x00,0xad]
+#CHECK: vmalof  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xad]
+#CHECK: vmalof  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xad]
+#CHECK: vmalof  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xad]
+#CHECK: vmalof  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xad]
+#CHECK: vmalof  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xad]
+
+	vmalof	%v0, %v0, %v0, %v0
+	vmalof	%v0, %v0, %v0, %v31
+	vmalof	%v0, %v0, %v31, %v0
+	vmalof	%v0, %v31, %v0, %v0
+	vmalof	%v31, %v0, %v0, %v0
+	vmalof	%v13, %v17, %v21, %v25
+
+#CHECK: vmaloh  %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x01,0x00,0x00,0xad]
+#CHECK: vmaloh  %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xad]
+#CHECK: vmaloh  %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xad]
+#CHECK: vmaloh  %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xad]
+#CHECK: vmaloh  %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xad]
+#CHECK: vmaloh  %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xad]
+
+	vmaloh	%v0, %v0, %v0, %v0
+	vmaloh	%v0, %v0, %v0, %v31
+	vmaloh	%v0, %v0, %v31, %v0
+	vmaloh	%v0, %v31, %v0, %v0
+	vmaloh	%v31, %v0, %v0, %v0
+	vmaloh	%v13, %v17, %v21, %v25
+
+#CHECK: vmaob   %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x00,0x00,0x00,0xaf]
+#CHECK: vmaob   %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xaf]
+#CHECK: vmaob   %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xaf]
+#CHECK: vmaob   %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xaf]
+#CHECK: vmaob   %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xaf]
+#CHECK: vmaob   %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xaf]
+
+	vmaob	%v0, %v0, %v0, %v0
+	vmaob	%v0, %v0, %v0, %v31
+	vmaob	%v0, %v0, %v31, %v0
+	vmaob	%v0, %v31, %v0, %v0
+	vmaob	%v31, %v0, %v0, %v0
+	vmaob	%v13, %v17, %v21, %v25
+
+#CHECK: vmaof   %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x02,0x00,0x00,0xaf]
+#CHECK: vmaof   %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xaf]
+#CHECK: vmaof   %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xaf]
+#CHECK: vmaof   %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xaf]
+#CHECK: vmaof   %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xaf]
+#CHECK: vmaof   %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xaf]
+
+	vmaof	%v0, %v0, %v0, %v0
+	vmaof	%v0, %v0, %v0, %v31
+	vmaof	%v0, %v0, %v31, %v0
+	vmaof	%v0, %v31, %v0, %v0
+	vmaof	%v31, %v0, %v0, %v0
+	vmaof	%v13, %v17, %v21, %v25
+
+#CHECK: vmaoh   %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x01,0x00,0x00,0xaf]
+#CHECK: vmaoh   %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xaf]
+#CHECK: vmaoh   %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xaf]
+#CHECK: vmaoh   %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xaf]
+#CHECK: vmaoh   %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xaf]
+#CHECK: vmaoh   %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xaf]
+
+	vmaoh	%v0, %v0, %v0, %v0
+	vmaoh	%v0, %v0, %v0, %v31
+	vmaoh	%v0, %v0, %v31, %v0
+	vmaoh	%v0, %v31, %v0, %v0
+	vmaoh	%v31, %v0, %v0, %v0
+	vmaoh	%v13, %v17, %v21, %v25
+
+#CHECK: vmeb    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa6]
+#CHECK: vmeb    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa6]
+#CHECK: vmeb    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa6]
+#CHECK: vmeb    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa6]
+#CHECK: vmeb    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xa6]
+
+	vmeb	%v0, %v0, %v0
+	vmeb	%v0, %v0, %v31
+	vmeb	%v0, %v31, %v0
+	vmeb	%v31, %v0, %v0
+	vmeb	%v18, %v3, %v20
+
+#CHECK: vmef    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xa6]
+#CHECK: vmef    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xa6]
+#CHECK: vmef    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xa6]
+#CHECK: vmef    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xa6]
+#CHECK: vmef    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xa6]
+
+	vmef	%v0, %v0, %v0
+	vmef	%v0, %v0, %v31
+	vmef	%v0, %v31, %v0
+	vmef	%v31, %v0, %v0
+	vmef	%v18, %v3, %v20
+
+#CHECK: vmeh    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xa6]
+#CHECK: vmeh    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xa6]
+#CHECK: vmeh    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xa6]
+#CHECK: vmeh    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xa6]
+#CHECK: vmeh    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xa6]
+
+	vmeh	%v0, %v0, %v0
+	vmeh	%v0, %v0, %v31
+	vmeh	%v0, %v31, %v0
+	vmeh	%v31, %v0, %v0
+	vmeh	%v18, %v3, %v20
+
+#CHECK: vmhb    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa3]
+#CHECK: vmhb    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa3]
+#CHECK: vmhb    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa3]
+#CHECK: vmhb    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa3]
+#CHECK: vmhb    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xa3]
+
+	vmhb	%v0, %v0, %v0
+	vmhb	%v0, %v0, %v31
+	vmhb	%v0, %v31, %v0
+	vmhb	%v31, %v0, %v0
+	vmhb	%v18, %v3, %v20
+
+#CHECK: vmhf    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xa3]
+#CHECK: vmhf    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xa3]
+#CHECK: vmhf    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xa3]
+#CHECK: vmhf    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xa3]
+#CHECK: vmhf    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xa3]
+
+	vmhf	%v0, %v0, %v0
+	vmhf	%v0, %v0, %v31
+	vmhf	%v0, %v31, %v0
+	vmhf	%v31, %v0, %v0
+	vmhf	%v18, %v3, %v20
+
+#CHECK: vmhh    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xa3]
+#CHECK: vmhh    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xa3]
+#CHECK: vmhh    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xa3]
+#CHECK: vmhh    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xa3]
+#CHECK: vmhh    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xa3]
+
+	vmhh	%v0, %v0, %v0
+	vmhh	%v0, %v0, %v31
+	vmhh	%v0, %v31, %v0
+	vmhh	%v31, %v0, %v0
+	vmhh	%v18, %v3, %v20
+
+#CHECK: vmlb    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa2]
+#CHECK: vmlb    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa2]
+#CHECK: vmlb    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa2]
+#CHECK: vmlb    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa2]
+#CHECK: vmlb    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xa2]
+
+	vmlb	%v0, %v0, %v0
+	vmlb	%v0, %v0, %v31
+	vmlb	%v0, %v31, %v0
+	vmlb	%v31, %v0, %v0
+	vmlb	%v18, %v3, %v20
+
+#CHECK: vmleb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa4]
+#CHECK: vmleb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa4]
+#CHECK: vmleb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa4]
+#CHECK: vmleb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa4]
+#CHECK: vmleb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xa4]
+
+	vmleb	%v0, %v0, %v0
+	vmleb	%v0, %v0, %v31
+	vmleb	%v0, %v31, %v0
+	vmleb	%v31, %v0, %v0
+	vmleb	%v18, %v3, %v20
+
+#CHECK: vmlef   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xa4]
+#CHECK: vmlef   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xa4]
+#CHECK: vmlef   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xa4]
+#CHECK: vmlef   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xa4]
+#CHECK: vmlef   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xa4]
+
+	vmlef	%v0, %v0, %v0
+	vmlef	%v0, %v0, %v31
+	vmlef	%v0, %v31, %v0
+	vmlef	%v31, %v0, %v0
+	vmlef	%v18, %v3, %v20
+
+#CHECK: vmleh   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xa4]
+#CHECK: vmleh   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xa4]
+#CHECK: vmleh   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xa4]
+#CHECK: vmleh   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xa4]
+#CHECK: vmleh   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xa4]
+
+	vmleh	%v0, %v0, %v0
+	vmleh	%v0, %v0, %v31
+	vmleh	%v0, %v31, %v0
+	vmleh	%v31, %v0, %v0
+	vmleh	%v18, %v3, %v20
+
+#CHECK: vmlf    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xa2]
+#CHECK: vmlf    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xa2]
+#CHECK: vmlf    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xa2]
+#CHECK: vmlf    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xa2]
+#CHECK: vmlf    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xa2]
+
+	vmlf	%v0, %v0, %v0
+	vmlf	%v0, %v0, %v31
+	vmlf	%v0, %v31, %v0
+	vmlf	%v31, %v0, %v0
+	vmlf	%v18, %v3, %v20
+
+#CHECK: vmlhb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa1]
+#CHECK: vmlhb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa1]
+#CHECK: vmlhb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa1]
+#CHECK: vmlhb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa1]
+#CHECK: vmlhb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xa1]
+
+	vmlhb	%v0, %v0, %v0
+	vmlhb	%v0, %v0, %v31
+	vmlhb	%v0, %v31, %v0
+	vmlhb	%v31, %v0, %v0
+	vmlhb	%v18, %v3, %v20
+
+#CHECK: vmlhf   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xa1]
+#CHECK: vmlhf   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xa1]
+#CHECK: vmlhf   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xa1]
+#CHECK: vmlhf   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xa1]
+#CHECK: vmlhf   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xa1]
+
+	vmlhf	%v0, %v0, %v0
+	vmlhf	%v0, %v0, %v31
+	vmlhf	%v0, %v31, %v0
+	vmlhf	%v31, %v0, %v0
+	vmlhf	%v18, %v3, %v20
+
+#CHECK: vmlhh   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xa1]
+#CHECK: vmlhh   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xa1]
+#CHECK: vmlhh   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xa1]
+#CHECK: vmlhh   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xa1]
+#CHECK: vmlhh   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xa1]
+
+	vmlhh	%v0, %v0, %v0
+	vmlhh	%v0, %v0, %v31
+	vmlhh	%v0, %v31, %v0
+	vmlhh	%v31, %v0, %v0
+	vmlhh	%v18, %v3, %v20
+
+#CHECK: vmlhw   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xa2]
+#CHECK: vmlhw   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xa2]
+#CHECK: vmlhw   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xa2]
+#CHECK: vmlhw   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xa2]
+#CHECK: vmlhw   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xa2]
+
+	vmlhw	%v0, %v0, %v0
+	vmlhw	%v0, %v0, %v31
+	vmlhw	%v0, %v31, %v0
+	vmlhw	%v31, %v0, %v0
+	vmlhw	%v18, %v3, %v20
+
+#CHECK: vmlob   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa5]
+#CHECK: vmlob   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa5]
+#CHECK: vmlob   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa5]
+#CHECK: vmlob   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa5]
+#CHECK: vmlob   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xa5]
+
+	vmlob	%v0, %v0, %v0
+	vmlob	%v0, %v0, %v31
+	vmlob	%v0, %v31, %v0
+	vmlob	%v31, %v0, %v0
+	vmlob	%v18, %v3, %v20
+
+#CHECK: vmlof   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xa5]
+#CHECK: vmlof   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xa5]
+#CHECK: vmlof   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xa5]
+#CHECK: vmlof   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xa5]
+#CHECK: vmlof   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xa5]
+
+	vmlof	%v0, %v0, %v0
+	vmlof	%v0, %v0, %v31
+	vmlof	%v0, %v31, %v0
+	vmlof	%v31, %v0, %v0
+	vmlof	%v18, %v3, %v20
+
+#CHECK: vmloh   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xa5]
+#CHECK: vmloh   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xa5]
+#CHECK: vmloh   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xa5]
+#CHECK: vmloh   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xa5]
+#CHECK: vmloh   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xa5]
+
+	vmloh	%v0, %v0, %v0
+	vmloh	%v0, %v0, %v31
+	vmloh	%v0, %v31, %v0
+	vmloh	%v31, %v0, %v0
+	vmloh	%v18, %v3, %v20
+
+#CHECK: vmnb    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xfe]
+#CHECK: vmnb    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xfe]
+#CHECK: vmnb    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xfe]
+#CHECK: vmnb    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xfe]
+#CHECK: vmnb    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xfe]
+
+	vmnb	%v0, %v0, %v0
+	vmnb	%v0, %v0, %v31
+	vmnb	%v0, %v31, %v0
+	vmnb	%v31, %v0, %v0
+	vmnb	%v18, %v3, %v20
+
+#CHECK: vmnf    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xfe]
+#CHECK: vmnf    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xfe]
+#CHECK: vmnf    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xfe]
+#CHECK: vmnf    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xfe]
+#CHECK: vmnf    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xfe]
+
+	vmnf	%v0, %v0, %v0
+	vmnf	%v0, %v0, %v31
+	vmnf	%v0, %v31, %v0
+	vmnf	%v31, %v0, %v0
+	vmnf	%v18, %v3, %v20
+
+#CHECK: vmng    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xfe]
+#CHECK: vmng    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xfe]
+#CHECK: vmng    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xfe]
+#CHECK: vmng    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xfe]
+#CHECK: vmng    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xfe]
+
+	vmng	%v0, %v0, %v0
+	vmng	%v0, %v0, %v31
+	vmng	%v0, %v31, %v0
+	vmng	%v31, %v0, %v0
+	vmng	%v18, %v3, %v20
+
+#CHECK: vmnh    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xfe]
+#CHECK: vmnh    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xfe]
+#CHECK: vmnh    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xfe]
+#CHECK: vmnh    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xfe]
+#CHECK: vmnh    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xfe]
+
+	vmnh	%v0, %v0, %v0
+	vmnh	%v0, %v0, %v31
+	vmnh	%v0, %v31, %v0
+	vmnh	%v31, %v0, %v0
+	vmnh	%v18, %v3, %v20
+
+#CHECK: vmnlb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xfc]
+#CHECK: vmnlb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xfc]
+#CHECK: vmnlb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xfc]
+#CHECK: vmnlb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xfc]
+#CHECK: vmnlb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xfc]
+
+	vmnlb	%v0, %v0, %v0
+	vmnlb	%v0, %v0, %v31
+	vmnlb	%v0, %v31, %v0
+	vmnlb	%v31, %v0, %v0
+	vmnlb	%v18, %v3, %v20
+
+#CHECK: vmnlf   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xfc]
+#CHECK: vmnlf   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xfc]
+#CHECK: vmnlf   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xfc]
+#CHECK: vmnlf   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xfc]
+#CHECK: vmnlf   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xfc]
+
+	vmnlf	%v0, %v0, %v0
+	vmnlf	%v0, %v0, %v31
+	vmnlf	%v0, %v31, %v0
+	vmnlf	%v31, %v0, %v0
+	vmnlf	%v18, %v3, %v20
+
+#CHECK: vmnlg   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xfc]
+#CHECK: vmnlg   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xfc]
+#CHECK: vmnlg   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xfc]
+#CHECK: vmnlg   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xfc]
+#CHECK: vmnlg   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xfc]
+
+	vmnlg	%v0, %v0, %v0
+	vmnlg	%v0, %v0, %v31
+	vmnlg	%v0, %v31, %v0
+	vmnlg	%v31, %v0, %v0
+	vmnlg	%v18, %v3, %v20
+
+#CHECK: vmnlh   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xfc]
+#CHECK: vmnlh   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xfc]
+#CHECK: vmnlh   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xfc]
+#CHECK: vmnlh   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xfc]
+#CHECK: vmnlh   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xfc]
+
+	vmnlh	%v0, %v0, %v0
+	vmnlh	%v0, %v0, %v31
+	vmnlh	%v0, %v31, %v0
+	vmnlh	%v31, %v0, %v0
+	vmnlh	%v18, %v3, %v20
+
+#CHECK: vmob    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa7]
+#CHECK: vmob    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa7]
+#CHECK: vmob    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa7]
+#CHECK: vmob    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa7]
+#CHECK: vmob    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xa7]
+
+	vmob	%v0, %v0, %v0
+	vmob	%v0, %v0, %v31
+	vmob	%v0, %v31, %v0
+	vmob	%v31, %v0, %v0
+	vmob	%v18, %v3, %v20
+
+#CHECK: vmof    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xa7]
+#CHECK: vmof    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xa7]
+#CHECK: vmof    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xa7]
+#CHECK: vmof    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xa7]
+#CHECK: vmof    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xa7]
+
+	vmof	%v0, %v0, %v0
+	vmof	%v0, %v0, %v31
+	vmof	%v0, %v31, %v0
+	vmof	%v31, %v0, %v0
+	vmof	%v18, %v3, %v20
+
+#CHECK: vmoh    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xa7]
+#CHECK: vmoh    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xa7]
+#CHECK: vmoh    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xa7]
+#CHECK: vmoh    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xa7]
+#CHECK: vmoh    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xa7]
+
+	vmoh	%v0, %v0, %v0
+	vmoh	%v0, %v0, %v31
+	vmoh	%v0, %v31, %v0
+	vmoh	%v31, %v0, %v0
+	vmoh	%v18, %v3, %v20
+
+#CHECK: vmrhb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x61]
+#CHECK: vmrhb   %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x61]
+#CHECK: vmrhb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x61]
+#CHECK: vmrhb   %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x61]
+#CHECK: vmrhb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x61]
+#CHECK: vmrhb   %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x61]
+#CHECK: vmrhb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x61]
+#CHECK: vmrhb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x61]
+
+	vmrhb	%v0, %v0, %v0
+	vmrhb	%v0, %v0, %v15
+	vmrhb	%v0, %v0, %v31
+	vmrhb	%v0, %v15, %v0
+	vmrhb	%v0, %v31, %v0
+	vmrhb	%v15, %v0, %v0
+	vmrhb	%v31, %v0, %v0
+	vmrhb	%v18, %v3, %v20
+
+#CHECK: vmrhf   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0x61]
+#CHECK: vmrhf   %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x61]
+#CHECK: vmrhf   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x61]
+#CHECK: vmrhf   %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x61]
+#CHECK: vmrhf   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x61]
+#CHECK: vmrhf   %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x61]
+#CHECK: vmrhf   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x61]
+#CHECK: vmrhf   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x61]
+
+	vmrhf	%v0, %v0, %v0
+	vmrhf	%v0, %v0, %v15
+	vmrhf	%v0, %v0, %v31
+	vmrhf	%v0, %v15, %v0
+	vmrhf	%v0, %v31, %v0
+	vmrhf	%v15, %v0, %v0
+	vmrhf	%v31, %v0, %v0
+	vmrhf	%v18, %v3, %v20
+
+#CHECK: vmrhg   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0x61]
+#CHECK: vmrhg   %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x61]
+#CHECK: vmrhg   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x61]
+#CHECK: vmrhg   %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x61]
+#CHECK: vmrhg   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x61]
+#CHECK: vmrhg   %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x61]
+#CHECK: vmrhg   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x61]
+#CHECK: vmrhg   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x61]
+
+	vmrhg	%v0, %v0, %v0
+	vmrhg	%v0, %v0, %v15
+	vmrhg	%v0, %v0, %v31
+	vmrhg	%v0, %v15, %v0
+	vmrhg	%v0, %v31, %v0
+	vmrhg	%v15, %v0, %v0
+	vmrhg	%v31, %v0, %v0
+	vmrhg	%v18, %v3, %v20
+
+#CHECK: vmrhh   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0x61]
+#CHECK: vmrhh   %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x61]
+#CHECK: vmrhh   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x61]
+#CHECK: vmrhh   %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x61]
+#CHECK: vmrhh   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x61]
+#CHECK: vmrhh   %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x61]
+#CHECK: vmrhh   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x61]
+#CHECK: vmrhh   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x61]
+
+	vmrhh	%v0, %v0, %v0
+	vmrhh	%v0, %v0, %v15
+	vmrhh	%v0, %v0, %v31
+	vmrhh	%v0, %v15, %v0
+	vmrhh	%v0, %v31, %v0
+	vmrhh	%v15, %v0, %v0
+	vmrhh	%v31, %v0, %v0
+	vmrhh	%v18, %v3, %v20
+
+#CHECK: vmrlb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x60]
+#CHECK: vmrlb   %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x60]
+#CHECK: vmrlb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x60]
+#CHECK: vmrlb   %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x60]
+#CHECK: vmrlb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x60]
+#CHECK: vmrlb   %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x60]
+#CHECK: vmrlb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x60]
+#CHECK: vmrlb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x60]
+
+	vmrlb	%v0, %v0, %v0
+	vmrlb	%v0, %v0, %v15
+	vmrlb	%v0, %v0, %v31
+	vmrlb	%v0, %v15, %v0
+	vmrlb	%v0, %v31, %v0
+	vmrlb	%v15, %v0, %v0
+	vmrlb	%v31, %v0, %v0
+	vmrlb	%v18, %v3, %v20
+
+#CHECK: vmrlf   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0x60]
+#CHECK: vmrlf   %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x60]
+#CHECK: vmrlf   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x60]
+#CHECK: vmrlf   %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x60]
+#CHECK: vmrlf   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x60]
+#CHECK: vmrlf   %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x60]
+#CHECK: vmrlf   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x60]
+#CHECK: vmrlf   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x60]
+
+	vmrlf	%v0, %v0, %v0
+	vmrlf	%v0, %v0, %v15
+	vmrlf	%v0, %v0, %v31
+	vmrlf	%v0, %v15, %v0
+	vmrlf	%v0, %v31, %v0
+	vmrlf	%v15, %v0, %v0
+	vmrlf	%v31, %v0, %v0
+	vmrlf	%v18, %v3, %v20
+
+#CHECK: vmrlg   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0x60]
+#CHECK: vmrlg   %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x60]
+#CHECK: vmrlg   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x60]
+#CHECK: vmrlg   %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x60]
+#CHECK: vmrlg   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x60]
+#CHECK: vmrlg   %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x60]
+#CHECK: vmrlg   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x60]
+#CHECK: vmrlg   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x60]
+
+	vmrlg	%v0, %v0, %v0
+	vmrlg	%v0, %v0, %v15
+	vmrlg	%v0, %v0, %v31
+	vmrlg	%v0, %v15, %v0
+	vmrlg	%v0, %v31, %v0
+	vmrlg	%v15, %v0, %v0
+	vmrlg	%v31, %v0, %v0
+	vmrlg	%v18, %v3, %v20
+
+#CHECK: vmrlh   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0x60]
+#CHECK: vmrlh   %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x60]
+#CHECK: vmrlh   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x60]
+#CHECK: vmrlh   %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x60]
+#CHECK: vmrlh   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x60]
+#CHECK: vmrlh   %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x60]
+#CHECK: vmrlh   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x60]
+#CHECK: vmrlh   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x60]
+
+	vmrlh	%v0, %v0, %v0
+	vmrlh	%v0, %v0, %v15
+	vmrlh	%v0, %v0, %v31
+	vmrlh	%v0, %v15, %v0
+	vmrlh	%v0, %v31, %v0
+	vmrlh	%v15, %v0, %v0
+	vmrlh	%v31, %v0, %v0
+	vmrlh	%v18, %v3, %v20
+
+#CHECK: vmxb    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xff]
+#CHECK: vmxb    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xff]
+#CHECK: vmxb    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xff]
+#CHECK: vmxb    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xff]
+#CHECK: vmxb    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xff]
+
+	vmxb	%v0, %v0, %v0
+	vmxb	%v0, %v0, %v31
+	vmxb	%v0, %v31, %v0
+	vmxb	%v31, %v0, %v0
+	vmxb	%v18, %v3, %v20
+
+#CHECK: vmxf    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xff]
+#CHECK: vmxf    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xff]
+#CHECK: vmxf    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xff]
+#CHECK: vmxf    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xff]
+#CHECK: vmxf    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xff]
+
+	vmxf	%v0, %v0, %v0
+	vmxf	%v0, %v0, %v31
+	vmxf	%v0, %v31, %v0
+	vmxf	%v31, %v0, %v0
+	vmxf	%v18, %v3, %v20
+
+#CHECK: vmxg    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xff]
+#CHECK: vmxg    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xff]
+#CHECK: vmxg    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xff]
+#CHECK: vmxg    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xff]
+#CHECK: vmxg    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xff]
+
+	vmxg	%v0, %v0, %v0
+	vmxg	%v0, %v0, %v31
+	vmxg	%v0, %v31, %v0
+	vmxg	%v31, %v0, %v0
+	vmxg	%v18, %v3, %v20
+
+#CHECK: vmxh    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xff]
+#CHECK: vmxh    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xff]
+#CHECK: vmxh    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xff]
+#CHECK: vmxh    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xff]
+#CHECK: vmxh    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xff]
+
+	vmxh	%v0, %v0, %v0
+	vmxh	%v0, %v0, %v31
+	vmxh	%v0, %v31, %v0
+	vmxh	%v31, %v0, %v0
+	vmxh	%v18, %v3, %v20
+
+#CHECK: vmxlb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xfd]
+#CHECK: vmxlb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xfd]
+#CHECK: vmxlb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xfd]
+#CHECK: vmxlb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xfd]
+#CHECK: vmxlb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xfd]
+
+	vmxlb	%v0, %v0, %v0
+	vmxlb	%v0, %v0, %v31
+	vmxlb	%v0, %v31, %v0
+	vmxlb	%v31, %v0, %v0
+	vmxlb	%v18, %v3, %v20
+
+#CHECK: vmxlf   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xfd]
+#CHECK: vmxlf   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xfd]
+#CHECK: vmxlf   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xfd]
+#CHECK: vmxlf   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xfd]
+#CHECK: vmxlf   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xfd]
+
+	vmxlf	%v0, %v0, %v0
+	vmxlf	%v0, %v0, %v31
+	vmxlf	%v0, %v31, %v0
+	vmxlf	%v31, %v0, %v0
+	vmxlf	%v18, %v3, %v20
+
+#CHECK: vmxlg   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xfd]
+#CHECK: vmxlg   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xfd]
+#CHECK: vmxlg   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xfd]
+#CHECK: vmxlg   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xfd]
+#CHECK: vmxlg   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xfd]
+
+	vmxlg	%v0, %v0, %v0
+	vmxlg	%v0, %v0, %v31
+	vmxlg	%v0, %v31, %v0
+	vmxlg	%v31, %v0, %v0
+	vmxlg	%v18, %v3, %v20
+
+#CHECK: vmxlh   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xfd]
+#CHECK: vmxlh   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xfd]
+#CHECK: vmxlh   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xfd]
+#CHECK: vmxlh   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xfd]
+#CHECK: vmxlh   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xfd]
+
+	vmxlh	%v0, %v0, %v0
+	vmxlh	%v0, %v0, %v31
+	vmxlh	%v0, %v31, %v0
+	vmxlh	%v31, %v0, %v0
+	vmxlh	%v18, %v3, %v20
+
+#CHECK: vn      %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x68]
+#CHECK: vn      %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x68]
+#CHECK: vn      %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x68]
+#CHECK: vn      %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x68]
+#CHECK: vn      %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x68]
+
+	vn	%v0, %v0, %v0
+	vn	%v0, %v0, %v31
+	vn	%v0, %v31, %v0
+	vn	%v31, %v0, %v0
+	vn	%v18, %v3, %v20
+
+#CHECK: vnc     %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x69]
+#CHECK: vnc     %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x69]
+#CHECK: vnc     %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x69]
+#CHECK: vnc     %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x69]
+#CHECK: vnc     %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x69]
+
+	vnc	%v0, %v0, %v0
+	vnc	%v0, %v0, %v31
+	vnc	%v0, %v31, %v0
+	vnc	%v31, %v0, %v0
+	vnc	%v18, %v3, %v20
+
+#CHECK: vno     %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x6b]
+#CHECK: vno     %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x6b]
+#CHECK: vno     %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x6b]
+#CHECK: vno     %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x6b]
+#CHECK: vno     %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x6b]
+
+	vno	%v0, %v0, %v0
+	vno	%v0, %v0, %v31
+	vno	%v0, %v31, %v0
+	vno	%v31, %v0, %v0
+	vno	%v18, %v3, %v20
+
+#CHECK: vo      %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x6a]
+#CHECK: vo      %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x6a]
+#CHECK: vo      %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x6a]
+#CHECK: vo      %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x6a]
+#CHECK: vo      %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x6a]
+
+	vo	%v0, %v0, %v0
+	vo	%v0, %v0, %v31
+	vo	%v0, %v31, %v0
+	vo	%v31, %v0, %v0
+	vo	%v18, %v3, %v20
+
+#CHECK: vone    %v0                     # encoding: [0xe7,0x00,0xff,0xff,0x00,0x44]
+#CHECK: vone    %v15                    # encoding: [0xe7,0xf0,0xff,0xff,0x00,0x44]
+#CHECK: vone    %v22                    # encoding: [0xe7,0x60,0xff,0xff,0x08,0x44]
+#CHECK: vone    %v31                    # encoding: [0xe7,0xf0,0xff,0xff,0x08,0x44]
+
+	vone	%v0
+	vone	%v15
+	vone	%v22
+	vone	%v31
+
+#CHECK: vpdi    %v0, %v0, %v0, 0        # encoding: [0xe7,0x00,0x00,0x00,0x00,0x84]
+#CHECK: vpdi    %v0, %v0, %v0, 5        # encoding: [0xe7,0x00,0x00,0x00,0x50,0x84]
+#CHECK: vpdi    %v0, %v0, %v31, 0       # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x84]
+#CHECK: vpdi    %v0, %v31, %v0, 0       # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x84]
+#CHECK: vpdi    %v31, %v0, %v0, 0       # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x84]
+#CHECK: vpdi    %v13, %v17, %v21, 4     # encoding: [0xe7,0xd1,0x50,0x00,0x46,0x84]
+
+	vpdi	%v0, %v0, %v0, 0
+	vpdi	%v0, %v0, %v0, 5
+	vpdi	%v0, %v0, %v31, 0
+	vpdi	%v0, %v31, %v0, 0
+	vpdi	%v31, %v0, %v0, 0
+	vpdi	%v13, %v17, %v21, 4
+
+#CHECK: vperm   %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x00,0x00,0x00,0x8c]
+#CHECK: vperm   %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x00,0x00,0xf1,0x8c]
+#CHECK: vperm   %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x8c]
+#CHECK: vperm   %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x8c]
+#CHECK: vperm   %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x8c]
+#CHECK: vperm   %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x50,0x00,0x97,0x8c]
+
+	vperm	%v0, %v0, %v0, %v0
+	vperm	%v0, %v0, %v0, %v31
+	vperm	%v0, %v0, %v31, %v0
+	vperm	%v0, %v31, %v0, %v0
+	vperm	%v31, %v0, %v0, %v0
+	vperm	%v13, %v17, %v21, %v25
+
+#CHECK: vpkf    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0x94]
+#CHECK: vpkf    %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x94]
+#CHECK: vpkf    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x94]
+#CHECK: vpkf    %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x94]
+#CHECK: vpkf    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x94]
+#CHECK: vpkf    %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x94]
+#CHECK: vpkf    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x94]
+#CHECK: vpkf    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x94]
+
+	vpkf	%v0, %v0, %v0
+	vpkf	%v0, %v0, %v15
+	vpkf	%v0, %v0, %v31
+	vpkf	%v0, %v15, %v0
+	vpkf	%v0, %v31, %v0
+	vpkf	%v15, %v0, %v0
+	vpkf	%v31, %v0, %v0
+	vpkf	%v18, %v3, %v20
+
+#CHECK: vpkg    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0x94]
+#CHECK: vpkg    %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x94]
+#CHECK: vpkg    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x94]
+#CHECK: vpkg    %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x94]
+#CHECK: vpkg    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x94]
+#CHECK: vpkg    %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x94]
+#CHECK: vpkg    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x94]
+#CHECK: vpkg    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x94]
+
+	vpkg	%v0, %v0, %v0
+	vpkg	%v0, %v0, %v15
+	vpkg	%v0, %v0, %v31
+	vpkg	%v0, %v15, %v0
+	vpkg	%v0, %v31, %v0
+	vpkg	%v15, %v0, %v0
+	vpkg	%v31, %v0, %v0
+	vpkg	%v18, %v3, %v20
+
+#CHECK: vpkh    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0x94]
+#CHECK: vpkh    %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x94]
+#CHECK: vpkh    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x94]
+#CHECK: vpkh    %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x94]
+#CHECK: vpkh    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x94]
+#CHECK: vpkh    %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x94]
+#CHECK: vpkh    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x94]
+#CHECK: vpkh    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x94]
+
+	vpkh	%v0, %v0, %v0
+	vpkh	%v0, %v0, %v15
+	vpkh	%v0, %v0, %v31
+	vpkh	%v0, %v15, %v0
+	vpkh	%v0, %v31, %v0
+	vpkh	%v15, %v0, %v0
+	vpkh	%v31, %v0, %v0
+	vpkh	%v18, %v3, %v20
+
+#CHECK: vpklsf  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0x95]
+#CHECK: vpklsf  %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x95]
+#CHECK: vpklsf  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x95]
+#CHECK: vpklsf  %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x95]
+#CHECK: vpklsf  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x95]
+#CHECK: vpklsf  %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x95]
+#CHECK: vpklsf  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x95]
+#CHECK: vpklsf  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x95]
+#CHECK: vpklsfs %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x24,0x95]
+
+	vpklsf	%v0, %v0, %v0
+	vpklsf	%v0, %v0, %v15
+	vpklsf	%v0, %v0, %v31
+	vpklsf	%v0, %v15, %v0
+	vpklsf	%v0, %v31, %v0
+	vpklsf	%v15, %v0, %v0
+	vpklsf	%v31, %v0, %v0
+	vpklsf	%v18, %v3, %v20
+	vpklsfs	%v5, %v22, %v7
+
+#CHECK: vpklsg  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0x95]
+#CHECK: vpklsg  %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x95]
+#CHECK: vpklsg  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x95]
+#CHECK: vpklsg  %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x95]
+#CHECK: vpklsg  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x95]
+#CHECK: vpklsg  %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x95]
+#CHECK: vpklsg  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x95]
+#CHECK: vpklsg  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x95]
+#CHECK: vpklsgs %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x34,0x95]
+
+	vpklsg	%v0, %v0, %v0
+	vpklsg	%v0, %v0, %v15
+	vpklsg	%v0, %v0, %v31
+	vpklsg	%v0, %v15, %v0
+	vpklsg	%v0, %v31, %v0
+	vpklsg	%v15, %v0, %v0
+	vpklsg	%v31, %v0, %v0
+	vpklsg	%v18, %v3, %v20
+	vpklsgs	%v5, %v22, %v7
+
+#CHECK: vpklsh  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0x95]
+#CHECK: vpklsh  %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x95]
+#CHECK: vpklsh  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x95]
+#CHECK: vpklsh  %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x95]
+#CHECK: vpklsh  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x95]
+#CHECK: vpklsh  %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x95]
+#CHECK: vpklsh  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x95]
+#CHECK: vpklsh  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x95]
+#CHECK: vpklshs %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x14,0x95]
+
+	vpklsh	%v0, %v0, %v0
+	vpklsh	%v0, %v0, %v15
+	vpklsh	%v0, %v0, %v31
+	vpklsh	%v0, %v15, %v0
+	vpklsh	%v0, %v31, %v0
+	vpklsh	%v15, %v0, %v0
+	vpklsh	%v31, %v0, %v0
+	vpklsh	%v18, %v3, %v20
+	vpklshs	%v5, %v22, %v7
+
+#CHECK: vpksf   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0x97]
+#CHECK: vpksf   %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x97]
+#CHECK: vpksf   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x97]
+#CHECK: vpksf   %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x97]
+#CHECK: vpksf   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x97]
+#CHECK: vpksf   %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x97]
+#CHECK: vpksf   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x97]
+#CHECK: vpksf   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x97]
+#CHECK: vpksfs  %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x24,0x97]
+
+	vpksf	%v0, %v0, %v0
+	vpksf	%v0, %v0, %v15
+	vpksf	%v0, %v0, %v31
+	vpksf	%v0, %v15, %v0
+	vpksf	%v0, %v31, %v0
+	vpksf	%v15, %v0, %v0
+	vpksf	%v31, %v0, %v0
+	vpksf	%v18, %v3, %v20
+	vpksfs	%v5, %v22, %v7
+
+#CHECK: vpksg   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0x97]
+#CHECK: vpksg   %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x97]
+#CHECK: vpksg   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x97]
+#CHECK: vpksg   %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x97]
+#CHECK: vpksg   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x97]
+#CHECK: vpksg   %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x97]
+#CHECK: vpksg   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x97]
+#CHECK: vpksg   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x97]
+#CHECK: vpksgs  %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x34,0x97]
+
+	vpksg	%v0, %v0, %v0
+	vpksg	%v0, %v0, %v15
+	vpksg	%v0, %v0, %v31
+	vpksg	%v0, %v15, %v0
+	vpksg	%v0, %v31, %v0
+	vpksg	%v15, %v0, %v0
+	vpksg	%v31, %v0, %v0
+	vpksg	%v18, %v3, %v20
+	vpksgs	%v5, %v22, %v7
+
+#CHECK: vpksh   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0x97]
+#CHECK: vpksh   %v0, %v0, %v15          # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x97]
+#CHECK: vpksh   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x97]
+#CHECK: vpksh   %v0, %v15, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x97]
+#CHECK: vpksh   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x97]
+#CHECK: vpksh   %v15, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x97]
+#CHECK: vpksh   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x97]
+#CHECK: vpksh   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x97]
+#CHECK: vpkshs  %v5, %v22, %v7          # encoding: [0xe7,0x56,0x70,0x10,0x14,0x97]
+
+	vpksh	%v0, %v0, %v0
+	vpksh	%v0, %v0, %v15
+	vpksh	%v0, %v0, %v31
+	vpksh	%v0, %v15, %v0
+	vpksh	%v0, %v31, %v0
+	vpksh	%v15, %v0, %v0
+	vpksh	%v31, %v0, %v0
+	vpksh	%v18, %v3, %v20
+	vpkshs	%v5, %v22, %v7
+
+#CHECK: vpopct  %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x00,0x50]
+#CHECK: vpopct  %v0, %v15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x50]
+#CHECK: vpopct  %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x50]
+#CHECK: vpopct  %v15, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x50]
+#CHECK: vpopct  %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x50]
+#CHECK: vpopct  %v14, %v17, 0           # encoding: [0xe7,0xe1,0x00,0x00,0x04,0x50]
+
+	vpopct	%v0, %v0, 0
+	vpopct	%v0, %v15, 0
+	vpopct	%v0, %v31, 0
+	vpopct	%v15, %v0, 0
+	vpopct	%v31, %v0, 0
+	vpopct	%v14, %v17, 0
+
+#CHECK: vrepb   %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x00,0x4d]
+#CHECK: vrepb   %v0, %v0, 65535         # encoding: [0xe7,0x00,0xff,0xff,0x00,0x4d]
+#CHECK: vrepb   %v0, %v15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x4d]
+#CHECK: vrepb   %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x4d]
+#CHECK: vrepb   %v15, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x4d]
+#CHECK: vrepb   %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x4d]
+#CHECK: vrepb   %v4, %v21, 26505        # encoding: [0xe7,0x45,0x67,0x89,0x04,0x4d]
+
+	vrepb	%v0, %v0, 0
+	vrepb	%v0, %v0, 65535
+	vrepb	%v0, %v15, 0
+	vrepb	%v0, %v31, 0
+	vrepb	%v15, %v0, 0
+	vrepb	%v31, %v0, 0
+	vrepb	%v4, %v21, 0x6789
+
+#CHECK: vrepf   %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x20,0x4d]
+#CHECK: vrepf   %v0, %v0, 65535         # encoding: [0xe7,0x00,0xff,0xff,0x20,0x4d]
+#CHECK: vrepf   %v0, %v15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x4d]
+#CHECK: vrepf   %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x4d]
+#CHECK: vrepf   %v15, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x4d]
+#CHECK: vrepf   %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x4d]
+#CHECK: vrepf   %v4, %v21, 26505        # encoding: [0xe7,0x45,0x67,0x89,0x24,0x4d]
+
+	vrepf	%v0, %v0, 0
+	vrepf	%v0, %v0, 65535
+	vrepf	%v0, %v15, 0
+	vrepf	%v0, %v31, 0
+	vrepf	%v15, %v0, 0
+	vrepf	%v31, %v0, 0
+	vrepf	%v4, %v21, 0x6789
+
+#CHECK: vrepg   %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x30,0x4d]
+#CHECK: vrepg   %v0, %v0, 65535         # encoding: [0xe7,0x00,0xff,0xff,0x30,0x4d]
+#CHECK: vrepg   %v0, %v15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x4d]
+#CHECK: vrepg   %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x4d]
+#CHECK: vrepg   %v15, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x4d]
+#CHECK: vrepg   %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x4d]
+#CHECK: vrepg   %v4, %v21, 26505        # encoding: [0xe7,0x45,0x67,0x89,0x34,0x4d]
+
+	vrepg	%v0, %v0, 0
+	vrepg	%v0, %v0, 65535
+	vrepg	%v0, %v15, 0
+	vrepg	%v0, %v31, 0
+	vrepg	%v15, %v0, 0
+	vrepg	%v31, %v0, 0
+	vrepg	%v4, %v21, 0x6789
+
+#CHECK: vreph   %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x10,0x4d]
+#CHECK: vreph   %v0, %v0, 65535         # encoding: [0xe7,0x00,0xff,0xff,0x10,0x4d]
+#CHECK: vreph   %v0, %v15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x4d]
+#CHECK: vreph   %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x4d]
+#CHECK: vreph   %v15, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x4d]
+#CHECK: vreph   %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x4d]
+#CHECK: vreph   %v4, %v21, 26505        # encoding: [0xe7,0x45,0x67,0x89,0x14,0x4d]
+
+	vreph	%v0, %v0, 0
+	vreph	%v0, %v0, 65535
+	vreph	%v0, %v15, 0
+	vreph	%v0, %v31, 0
+	vreph	%v15, %v0, 0
+	vreph	%v31, %v0, 0
+	vreph	%v4, %v21, 0x6789
+
+#CHECK: vrepib  %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x00,0x45]
+#CHECK: vrepib  %v0, -32768             # encoding: [0xe7,0x00,0x80,0x00,0x00,0x45]
+#CHECK: vrepib  %v0, 32767              # encoding: [0xe7,0x00,0x7f,0xff,0x00,0x45]
+#CHECK: vrepib  %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x45]
+#CHECK: vrepib  %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x45]
+#CHECK: vrepib  %v18, 13398             # encoding: [0xe7,0x20,0x34,0x56,0x08,0x45]
+
+	vrepib	%v0, 0
+	vrepib	%v0, -32768
+	vrepib	%v0, 32767
+	vrepib	%v15, 0
+	vrepib	%v31, 0
+	vrepib	%v18, 0x3456
+
+#CHECK: vrepif  %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x20,0x45]
+#CHECK: vrepif  %v0, -32768             # encoding: [0xe7,0x00,0x80,0x00,0x20,0x45]
+#CHECK: vrepif  %v0, 32767              # encoding: [0xe7,0x00,0x7f,0xff,0x20,0x45]
+#CHECK: vrepif  %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x45]
+#CHECK: vrepif  %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x45]
+#CHECK: vrepif  %v18, 13398             # encoding: [0xe7,0x20,0x34,0x56,0x28,0x45]
+
+	vrepif	%v0, 0
+	vrepif	%v0, -32768
+	vrepif	%v0, 32767
+	vrepif	%v15, 0
+	vrepif	%v31, 0
+	vrepif	%v18, 0x3456
+
+#CHECK: vrepig  %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x30,0x45]
+#CHECK: vrepig  %v0, -32768             # encoding: [0xe7,0x00,0x80,0x00,0x30,0x45]
+#CHECK: vrepig  %v0, 32767              # encoding: [0xe7,0x00,0x7f,0xff,0x30,0x45]
+#CHECK: vrepig  %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x45]
+#CHECK: vrepig  %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x45]
+#CHECK: vrepig  %v18, 13398             # encoding: [0xe7,0x20,0x34,0x56,0x38,0x45]
+
+	vrepig	%v0, 0
+	vrepig	%v0, -32768
+	vrepig	%v0, 32767
+	vrepig	%v15, 0
+	vrepig	%v31, 0
+	vrepig	%v18, 0x3456
+
+#CHECK: vrepih  %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x10,0x45]
+#CHECK: vrepih  %v0, -32768             # encoding: [0xe7,0x00,0x80,0x00,0x10,0x45]
+#CHECK: vrepih  %v0, 32767              # encoding: [0xe7,0x00,0x7f,0xff,0x10,0x45]
+#CHECK: vrepih  %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x45]
+#CHECK: vrepih  %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x45]
+#CHECK: vrepih  %v18, 13398             # encoding: [0xe7,0x20,0x34,0x56,0x18,0x45]
+
+	vrepih	%v0, 0
+	vrepih	%v0, -32768
+	vrepih	%v0, 32767
+	vrepih	%v15, 0
+	vrepih	%v31, 0
+	vrepih	%v18, 0x3456
+
+#CHECK: vsb     %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf7]
+#CHECK: vsb     %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf7]
+#CHECK: vsb     %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf7]
+#CHECK: vsb     %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf7]
+#CHECK: vsb     %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf7]
+
+	vsb	%v0, %v0, %v0
+	vsb	%v0, %v0, %v31
+	vsb	%v0, %v31, %v0
+	vsb	%v31, %v0, %v0
+	vsb	%v18, %v3, %v20
+
+#CHECK: vsbcbiq %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x04,0x00,0x00,0xbd]
+#CHECK: vsbcbiq %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x04,0x00,0xf1,0xbd]
+#CHECK: vsbcbiq %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf4,0x00,0x02,0xbd]
+#CHECK: vsbcbiq %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x04,0x00,0x04,0xbd]
+#CHECK: vsbcbiq %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x04,0x00,0x08,0xbd]
+#CHECK: vsbcbiq %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x54,0x00,0x97,0xbd]
+
+	vsbcbiq	%v0, %v0, %v0, %v0
+	vsbcbiq	%v0, %v0, %v0, %v31
+	vsbcbiq	%v0, %v0, %v31, %v0
+	vsbcbiq	%v0, %v31, %v0, %v0
+	vsbcbiq	%v31, %v0, %v0, %v0
+	vsbcbiq	%v13, %v17, %v21, %v25
+
+#CHECK: vsbiq   %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x04,0x00,0x00,0xbf]
+#CHECK: vsbiq   %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x04,0x00,0xf1,0xbf]
+#CHECK: vsbiq   %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf4,0x00,0x02,0xbf]
+#CHECK: vsbiq   %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x04,0x00,0x04,0xbf]
+#CHECK: vsbiq   %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x04,0x00,0x08,0xbf]
+#CHECK: vsbiq   %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x54,0x00,0x97,0xbf]
+
+	vsbiq	%v0, %v0, %v0, %v0
+	vsbiq	%v0, %v0, %v0, %v31
+	vsbiq	%v0, %v0, %v31, %v0
+	vsbiq	%v0, %v31, %v0, %v0
+	vsbiq	%v31, %v0, %v0, %v0
+	vsbiq	%v13, %v17, %v21, %v25
+
+#CHECK: vscbib  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf5]
+#CHECK: vscbib  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf5]
+#CHECK: vscbib  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf5]
+#CHECK: vscbib  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf5]
+#CHECK: vscbib  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf5]
+
+	vscbib	%v0, %v0, %v0
+	vscbib	%v0, %v0, %v31
+	vscbib	%v0, %v31, %v0
+	vscbib	%v31, %v0, %v0
+	vscbib	%v18, %v3, %v20
+
+#CHECK: vscbif  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf5]
+#CHECK: vscbif  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf5]
+#CHECK: vscbif  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf5]
+#CHECK: vscbif  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf5]
+#CHECK: vscbif  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf5]
+
+	vscbif	%v0, %v0, %v0
+	vscbif	%v0, %v0, %v31
+	vscbif	%v0, %v31, %v0
+	vscbif	%v31, %v0, %v0
+	vscbif	%v18, %v3, %v20
+
+#CHECK: vscbig  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf5]
+#CHECK: vscbig  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf5]
+#CHECK: vscbig  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf5]
+#CHECK: vscbig  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf5]
+#CHECK: vscbig  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf5]
+
+	vscbig	%v0, %v0, %v0
+	vscbig	%v0, %v0, %v31
+	vscbig	%v0, %v31, %v0
+	vscbig	%v31, %v0, %v0
+	vscbig	%v18, %v3, %v20
+
+#CHECK: vscbih  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf5]
+#CHECK: vscbih  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf5]
+#CHECK: vscbih  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf5]
+#CHECK: vscbih  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf5]
+#CHECK: vscbih  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf5]
+
+	vscbih	%v0, %v0, %v0
+	vscbih	%v0, %v0, %v31
+	vscbih	%v0, %v31, %v0
+	vscbih	%v31, %v0, %v0
+	vscbih	%v18, %v3, %v20
+
+#CHECK: vscbiq  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x40,0xf5]
+#CHECK: vscbiq  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x42,0xf5]
+#CHECK: vscbiq  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x44,0xf5]
+#CHECK: vscbiq  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x48,0xf5]
+#CHECK: vscbiq  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x4a,0xf5]
+
+	vscbiq	%v0, %v0, %v0
+	vscbiq	%v0, %v0, %v31
+	vscbiq	%v0, %v31, %v0
+	vscbiq	%v31, %v0, %v0
+	vscbiq	%v18, %v3, %v20
+
+#CHECK: vscef   %v0, 0(%v0), 0          # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1b]
+#CHECK: vscef   %v0, 0(%v0,%r1), 0      # encoding: [0xe7,0x00,0x10,0x00,0x00,0x1b]
+#CHECK: vscef   %v0, 0(%v0,%r1), 3      # encoding: [0xe7,0x00,0x10,0x00,0x30,0x1b]
+#CHECK: vscef   %v0, 0(%v0,%r15), 0     # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x1b]
+#CHECK: vscef   %v0, 0(%v15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x1b]
+#CHECK: vscef   %v0, 0(%v31,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x04,0x1b]
+#CHECK: vscef   %v0, 4095(%v0,%r1), 0   # encoding: [0xe7,0x00,0x1f,0xff,0x00,0x1b]
+#CHECK: vscef   %v15, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x00,0x1b]
+#CHECK: vscef   %v31, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x1b]
+#CHECK: vscef   %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x1b]
+
+	vscef	%v0, 0(%v0), 0
+	vscef	%v0, 0(%v0,%r1), 0
+	vscef	%v0, 0(%v0,%r1), 3
+	vscef	%v0, 0(%v0,%r15), 0
+	vscef	%v0, 0(%v15,%r1), 0
+	vscef	%v0, 0(%v31,%r1), 0
+	vscef	%v0, 4095(%v0, %r1), 0
+	vscef	%v15, 0(%v0,%r1), 0
+	vscef	%v31, 0(%v0,%r1), 0
+	vscef	%v10, 1000(%v19,%r7), 1
+
+#CHECK: vsceg   %v0, 0(%v0), 0          # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1a]
+#CHECK: vsceg   %v0, 0(%v0,%r1), 0      # encoding: [0xe7,0x00,0x10,0x00,0x00,0x1a]
+#CHECK: vsceg   %v0, 0(%v0,%r1), 1      # encoding: [0xe7,0x00,0x10,0x00,0x10,0x1a]
+#CHECK: vsceg   %v0, 0(%v0,%r15), 0     # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x1a]
+#CHECK: vsceg   %v0, 0(%v15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x1a]
+#CHECK: vsceg   %v0, 0(%v31,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x04,0x1a]
+#CHECK: vsceg   %v0, 4095(%v0,%r1), 0   # encoding: [0xe7,0x00,0x1f,0xff,0x00,0x1a]
+#CHECK: vsceg   %v15, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x00,0x1a]
+#CHECK: vsceg   %v31, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x1a]
+#CHECK: vsceg   %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x1a]
+
+	vsceg	%v0, 0(%v0), 0
+	vsceg	%v0, 0(%v0,%r1), 0
+	vsceg	%v0, 0(%v0,%r1), 1
+	vsceg	%v0, 0(%v0,%r15), 0
+	vsceg	%v0, 0(%v15,%r1), 0
+	vsceg	%v0, 0(%v31,%r1), 0
+	vsceg	%v0, 4095(%v0,%r1), 0
+	vsceg	%v15, 0(%v0,%r1), 0
+	vsceg	%v31, 0(%v0,%r1), 0
+	vsceg	%v10, 1000(%v19,%r7), 1
+
+#CHECK: vsel    %v0, %v0, %v0, %v0      # encoding: [0xe7,0x00,0x00,0x00,0x00,0x8d]
+#CHECK: vsel    %v0, %v0, %v0, %v31     # encoding: [0xe7,0x00,0x00,0x00,0xf1,0x8d]
+#CHECK: vsel    %v0, %v0, %v31, %v0     # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x8d]
+#CHECK: vsel    %v0, %v31, %v0, %v0     # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x8d]
+#CHECK: vsel    %v31, %v0, %v0, %v0     # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x8d]
+#CHECK: vsel    %v13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x50,0x00,0x97,0x8d]
+
+	vsel	%v0, %v0, %v0, %v0
+	vsel	%v0, %v0, %v0, %v31
+	vsel	%v0, %v0, %v31, %v0
+	vsel	%v0, %v31, %v0, %v0
+	vsel	%v31, %v0, %v0, %v0
+	vsel 	%v13, %v17, %v21, %v25
+
+#CHECK: vsegb   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x00,0x5f]
+#CHECK: vsegb   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x5f]
+#CHECK: vsegb   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x5f]
+#CHECK: vsegb   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x5f]
+#CHECK: vsegb   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x5f]
+#CHECK: vsegb   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x04,0x5f]
+
+	vsegb	%v0, %v0
+	vsegb	%v0, %v15
+	vsegb	%v0, %v31
+	vsegb	%v15, %v0
+	vsegb	%v31, %v0
+	vsegb	%v14, %v17
+
+#CHECK: vsegf   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x20,0x5f]
+#CHECK: vsegf   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x5f]
+#CHECK: vsegf   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x5f]
+#CHECK: vsegf   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x5f]
+#CHECK: vsegf   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x5f]
+#CHECK: vsegf   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x24,0x5f]
+
+	vsegf	%v0, %v0
+	vsegf	%v0, %v15
+	vsegf	%v0, %v31
+	vsegf	%v15, %v0
+	vsegf	%v31, %v0
+	vsegf	%v14, %v17
+
+#CHECK: vsegh   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x10,0x5f]
+#CHECK: vsegh   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x5f]
+#CHECK: vsegh   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x5f]
+#CHECK: vsegh   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x5f]
+#CHECK: vsegh   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x5f]
+#CHECK: vsegh   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x14,0x5f]
+
+	vsegh	%v0, %v0
+	vsegh	%v0, %v15
+	vsegh	%v0, %v31
+	vsegh	%v15, %v0
+	vsegh	%v31, %v0
+	vsegh	%v14, %v17
+
+#CHECK: vsf     %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf7]
+#CHECK: vsf     %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf7]
+#CHECK: vsf     %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf7]
+#CHECK: vsf     %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf7]
+#CHECK: vsf     %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf7]
+
+	vsf	%v0, %v0, %v0
+	vsf	%v0, %v0, %v31
+	vsf	%v0, %v31, %v0
+	vsf	%v31, %v0, %v0
+	vsf	%v18, %v3, %v20
+
+#CHECK: vsg     %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf7]
+#CHECK: vsg     %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf7]
+#CHECK: vsg     %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf7]
+#CHECK: vsg     %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf7]
+#CHECK: vsg     %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf7]
+
+	vsg	%v0, %v0, %v0
+	vsg	%v0, %v0, %v31
+	vsg	%v0, %v31, %v0
+	vsg	%v31, %v0, %v0
+	vsg	%v18, %v3, %v20
+
+#CHECK: vsh     %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf7]
+#CHECK: vsh     %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf7]
+#CHECK: vsh     %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf7]
+#CHECK: vsh     %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf7]
+#CHECK: vsh     %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf7]
+
+	vsh	%v0, %v0, %v0
+	vsh	%v0, %v0, %v31
+	vsh	%v0, %v31, %v0
+	vsh	%v31, %v0, %v0
+	vsh	%v18, %v3, %v20
+
+#CHECK: vsl     %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x74]
+#CHECK: vsl     %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x74]
+#CHECK: vsl     %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x74]
+#CHECK: vsl     %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x74]
+#CHECK: vsl     %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x74]
+
+	vsl	%v0, %v0, %v0
+	vsl	%v0, %v0, %v31
+	vsl	%v0, %v31, %v0
+	vsl	%v31, %v0, %v0
+	vsl	%v18, %v3, %v20
+
+#CHECK: vslb    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x75]
+#CHECK: vslb    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x75]
+#CHECK: vslb    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x75]
+#CHECK: vslb    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x75]
+#CHECK: vslb    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x75]
+
+	vslb	%v0, %v0, %v0
+	vslb	%v0, %v0, %v31
+	vslb	%v0, %v31, %v0
+	vslb	%v31, %v0, %v0
+	vslb	%v18, %v3, %v20
+
+#CHECK: vsldb   %v0, %v0, %v0, 0        # encoding: [0xe7,0x00,0x00,0x00,0x00,0x77]
+#CHECK: vsldb   %v0, %v0, %v0, 255      # encoding: [0xe7,0x00,0x00,0xff,0x00,0x77]
+#CHECK: vsldb   %v0, %v0, %v31, 0       # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x77]
+#CHECK: vsldb   %v0, %v31, %v0, 0       # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x77]
+#CHECK: vsldb   %v31, %v0, %v0, 0       # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x77]
+#CHECK: vsldb   %v13, %v17, %v21, 121   # encoding: [0xe7,0xd1,0x50,0x79,0x06,0x77]
+
+	vsldb	%v0, %v0, %v0, 0
+	vsldb	%v0, %v0, %v0, 255
+	vsldb	%v0, %v0, %v31, 0
+	vsldb	%v0, %v31, %v0, 0
+	vsldb	%v31, %v0, %v0, 0
+	vsldb 	%v13, %v17, %v21, 0x79
+
+#CHECK: vsq     %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x40,0xf7]
+#CHECK: vsq     %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x42,0xf7]
+#CHECK: vsq     %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x44,0xf7]
+#CHECK: vsq     %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x48,0xf7]
+#CHECK: vsq     %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x4a,0xf7]
+
+	vsq	%v0, %v0, %v0
+	vsq	%v0, %v0, %v31
+	vsq	%v0, %v31, %v0
+	vsq	%v31, %v0, %v0
+	vsq	%v18, %v3, %v20
+
+#CHECK: vsra    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x7e]
+#CHECK: vsra    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x7e]
+#CHECK: vsra    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x7e]
+#CHECK: vsra    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x7e]
+#CHECK: vsra    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x7e]
+
+	vsra	%v0, %v0, %v0
+	vsra	%v0, %v0, %v31
+	vsra	%v0, %v31, %v0
+	vsra	%v31, %v0, %v0
+	vsra	%v18, %v3, %v20
+
+#CHECK: vsrab   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x7f]
+#CHECK: vsrab   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x7f]
+#CHECK: vsrab   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x7f]
+#CHECK: vsrab   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x7f]
+#CHECK: vsrab   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x7f]
+
+	vsrab	%v0, %v0, %v0
+	vsrab	%v0, %v0, %v31
+	vsrab	%v0, %v31, %v0
+	vsrab	%v31, %v0, %v0
+	vsrab	%v18, %v3, %v20
+
+#CHECK: vsrl    %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x7c]
+#CHECK: vsrl    %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x7c]
+#CHECK: vsrl    %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x7c]
+#CHECK: vsrl    %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x7c]
+#CHECK: vsrl    %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x7c]
+
+	vsrl	%v0, %v0, %v0
+	vsrl	%v0, %v0, %v31
+	vsrl	%v0, %v31, %v0
+	vsrl	%v31, %v0, %v0
+	vsrl	%v18, %v3, %v20
+
+#CHECK: vsrlb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x7d]
+#CHECK: vsrlb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x7d]
+#CHECK: vsrlb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x7d]
+#CHECK: vsrlb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x7d]
+#CHECK: vsrlb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x7d]
+
+	vsrlb	%v0, %v0, %v0
+	vsrlb	%v0, %v0, %v31
+	vsrlb	%v0, %v31, %v0
+	vsrlb	%v31, %v0, %v0
+	vsrlb	%v18, %v3, %v20
+
+#CHECK: vst     %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x00,0x0e]
+#CHECK: vst     %v0, 4095               # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x0e]
+#CHECK: vst     %v0, 0(%r15)            # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x0e]
+#CHECK: vst     %v0, 0(%r15,%r1)        # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x0e]
+#CHECK: vst     %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x0e]
+#CHECK: vst     %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x0e]
+#CHECK: vst     %v18, 1383(%r3,%r4)     # encoding: [0xe7,0x23,0x45,0x67,0x08,0x0e]
+
+	vst	%v0, 0
+	vst	%v0, 4095
+	vst	%v0, 0(%r15)
+	vst	%v0, 0(%r15,%r1)
+	vst	%v15, 0
+	vst	%v31, 0
+	vst	%v18, 0x567(%r3,%r4)
+
+#CHECK: vsteb   %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x08]
+#CHECK: vsteb   %v0, 0, 15              # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x08]
+#CHECK: vsteb   %v0, 4095, 0            # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x08]
+#CHECK: vsteb   %v0, 0(%r15), 0         # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x08]
+#CHECK: vsteb   %v0, 0(%r15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x08]
+#CHECK: vsteb   %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x08]
+#CHECK: vsteb   %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x08]
+#CHECK: vsteb   %v18, 1383(%r3,%r4), 8  # encoding: [0xe7,0x23,0x45,0x67,0x88,0x08]
+
+	vsteb	%v0, 0, 0
+	vsteb	%v0, 0, 15
+	vsteb	%v0, 4095, 0
+	vsteb	%v0, 0(%r15), 0
+	vsteb	%v0, 0(%r15,%r1), 0
+	vsteb	%v15, 0, 0
+	vsteb	%v31, 0, 0
+	vsteb	%v18, 1383(%r3,%r4), 8
+
+#CHECK: vstef   %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x0b]
+#CHECK: vstef   %v0, 0, 3               # encoding: [0xe7,0x00,0x00,0x00,0x30,0x0b]
+#CHECK: vstef   %v0, 4095, 0            # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x0b]
+#CHECK: vstef   %v0, 0(%r15), 0         # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x0b]
+#CHECK: vstef   %v0, 0(%r15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x0b]
+#CHECK: vstef   %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x0b]
+#CHECK: vstef   %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x0b]
+#CHECK: vstef   %v18, 1383(%r3,%r4), 2  # encoding: [0xe7,0x23,0x45,0x67,0x28,0x0b]
+
+	vstef	%v0, 0, 0
+	vstef	%v0, 0, 3
+	vstef	%v0, 4095, 0
+	vstef	%v0, 0(%r15), 0
+	vstef	%v0, 0(%r15,%r1), 0
+	vstef	%v15, 0, 0
+	vstef	%v31, 0, 0
+	vstef	%v18, 1383(%r3,%r4), 2
+
+#CHECK: vsteg   %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x0a]
+#CHECK: vsteg   %v0, 0, 1               # encoding: [0xe7,0x00,0x00,0x00,0x10,0x0a]
+#CHECK: vsteg   %v0, 4095, 0            # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x0a]
+#CHECK: vsteg   %v0, 0(%r15), 0         # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x0a]
+#CHECK: vsteg   %v0, 0(%r15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x0a]
+#CHECK: vsteg   %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x0a]
+#CHECK: vsteg   %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x0a]
+#CHECK: vsteg   %v18, 1383(%r3,%r4), 1  # encoding: [0xe7,0x23,0x45,0x67,0x18,0x0a]
+
+	vsteg	%v0, 0, 0
+	vsteg	%v0, 0, 1
+	vsteg	%v0, 4095, 0
+	vsteg	%v0, 0(%r15), 0
+	vsteg	%v0, 0(%r15,%r1), 0
+	vsteg	%v15, 0, 0
+	vsteg	%v31, 0, 0
+	vsteg	%v18, 1383(%r3,%r4), 1
+
+#CHECK: vsteh   %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x09]
+#CHECK: vsteh   %v0, 0, 7               # encoding: [0xe7,0x00,0x00,0x00,0x70,0x09]
+#CHECK: vsteh   %v0, 4095, 0            # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x09]
+#CHECK: vsteh   %v0, 0(%r15), 0         # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x09]
+#CHECK: vsteh   %v0, 0(%r15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x09]
+#CHECK: vsteh   %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x09]
+#CHECK: vsteh   %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x09]
+#CHECK: vsteh   %v18, 1383(%r3,%r4), 4  # encoding: [0xe7,0x23,0x45,0x67,0x48,0x09]
+
+	vsteh	%v0, 0, 0
+	vsteh	%v0, 0, 7
+	vsteh	%v0, 4095, 0
+	vsteh	%v0, 0(%r15), 0
+	vsteh	%v0, 0(%r15,%r1), 0
+	vsteh	%v15, 0, 0
+	vsteh	%v31, 0, 0
+	vsteh	%v18, 1383(%r3,%r4), 4
+
+#CHECK: vstl    %v0, %r0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x00,0x3f]
+#CHECK: vstl    %v0, %r0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x3f]
+#CHECK: vstl    %v0, %r0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x3f]
+#CHECK: vstl    %v0, %r15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x3f]
+#CHECK: vstl    %v15, %r0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x3f]
+#CHECK: vstl    %v31, %r0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x3f]
+#CHECK: vstl    %v18, %r3, 1383(%r4)    # encoding: [0xe7,0x23,0x45,0x67,0x08,0x3f]
+
+	vstl	%v0, %r0, 0
+	vstl	%v0, %r0, 4095
+	vstl	%v0, %r0, 0(%r15)
+	vstl	%v0, %r15, 0
+	vstl	%v15, %r0, 0
+	vstl	%v31, %r0, 0
+	vstl	%v18, %r3, 1383(%r4)
+
+#CHECK: vstm    %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x00,0x3e]
+#CHECK: vstm    %v0, %v0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x3e]
+#CHECK: vstm    %v0, %v0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x3e]
+#CHECK: vstm    %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x3e]
+#CHECK: vstm    %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x3e]
+#CHECK: vstm    %v14, %v17, 1074(%r5)   # encoding: [0xe7,0xe1,0x54,0x32,0x04,0x3e]
+
+	vstm	%v0, %v0, 0
+	vstm	%v0, %v0, 4095
+	vstm	%v0, %v0, 0(%r15)
+	vstm	%v0, %v31, 0
+	vstm	%v31, %v0, 0
+	vstm	%v14, %v17, 1074(%r5)
+
+#CHECK: vstrcb   %v0, %v0, %v0, %v0, 0   # encoding: [0xe7,0x00,0x00,0x00,0x00,0x8a]
+#CHECK: vstrcb   %v0, %v0, %v0, %v0, 0   # encoding: [0xe7,0x00,0x00,0x00,0x00,0x8a]
+#CHECK: vstrcb   %v0, %v0, %v0, %v0, 12  # encoding: [0xe7,0x00,0x00,0xc0,0x00,0x8a]
+#CHECK: vstrcb   %v0, %v0, %v0, %v15, 0  # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x8a]
+#CHECK: vstrcb   %v0, %v0, %v0, %v31, 0  # encoding: [0xe7,0x00,0x00,0x00,0xf1,0x8a]
+#CHECK: vstrcb   %v0, %v0, %v15, %v0, 0  # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x8a]
+#CHECK: vstrcb   %v0, %v0, %v31, %v0, 0  # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x8a]
+#CHECK: vstrcb   %v0, %v15, %v0, %v0, 0  # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x8a]
+#CHECK: vstrcb   %v0, %v31, %v0, %v0, 0  # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x8a]
+#CHECK: vstrcb   %v15, %v0, %v0, %v0, 0  # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x8a]
+#CHECK: vstrcb   %v31, %v0, %v0, %v0, 0  # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x8a]
+#CHECK: vstrcb   %v18, %v3, %v20, %v5, 4 # encoding: [0xe7,0x23,0x40,0x40,0x5a,0x8a]
+#CHECK: vstrcb   %v18, %v3, %v20, %v5, 15 # encoding: [0xe7,0x23,0x40,0xf0,0x5a,0x8a]
+#CHECK: vstrcbs  %v18, %v3, %v20, %v5, 8 # encoding: [0xe7,0x23,0x40,0x90,0x5a,0x8a]
+#CHECK: vstrczb  %v18, %v3, %v20, %v5, 4 # encoding: [0xe7,0x23,0x40,0x60,0x5a,0x8a]
+#CHECK: vstrczbs %v18, %v3, %v20, %v5, 8 # encoding: [0xe7,0x23,0x40,0xb0,0x5a,0x8a]
+#CHECK: vstrczbs %v18, %v3, %v20, %v5, 15 # encoding: [0xe7,0x23,0x40,0xf0,0x5a,0x8a]
+
+        vstrcb   %v0, %v0, %v0, %v0
+        vstrcb   %v0, %v0, %v0, %v0, 0
+        vstrcb   %v0, %v0, %v0, %v0, 12
+        vstrcb   %v0, %v0, %v0, %v15
+        vstrcb   %v0, %v0, %v0, %v31
+        vstrcb   %v0, %v0, %v15, %v0
+        vstrcb   %v0, %v0, %v31, %v0
+        vstrcb   %v0, %v15, %v0, %v0
+        vstrcb   %v0, %v31, %v0, %v0
+        vstrcb   %v15, %v0, %v0, %v0
+        vstrcb   %v31, %v0, %v0, %v0
+        vstrcb   %v18, %v3, %v20, %v5, 4
+        vstrcb   %v18, %v3, %v20, %v5, 15
+        vstrcbs  %v18, %v3, %v20, %v5, 8
+        vstrczb  %v18, %v3, %v20, %v5, 4
+        vstrczbs %v18, %v3, %v20, %v5, 8
+        vstrczbs %v18, %v3, %v20, %v5, 15
+
+#CHECK: vstrcf   %v0, %v0, %v0, %v0, 0   # encoding: [0xe7,0x00,0x02,0x00,0x00,0x8a]
+#CHECK: vstrcf   %v0, %v0, %v0, %v0, 0   # encoding: [0xe7,0x00,0x02,0x00,0x00,0x8a]
+#CHECK: vstrcf   %v0, %v0, %v0, %v0, 12  # encoding: [0xe7,0x00,0x02,0xc0,0x00,0x8a]
+#CHECK: vstrcf   %v0, %v0, %v0, %v15, 0  # encoding: [0xe7,0x00,0x02,0x00,0xf0,0x8a]
+#CHECK: vstrcf   %v0, %v0, %v0, %v31, 0  # encoding: [0xe7,0x00,0x02,0x00,0xf1,0x8a]
+#CHECK: vstrcf   %v0, %v0, %v15, %v0, 0  # encoding: [0xe7,0x00,0xf2,0x00,0x00,0x8a]
+#CHECK: vstrcf   %v0, %v0, %v31, %v0, 0  # encoding: [0xe7,0x00,0xf2,0x00,0x02,0x8a]
+#CHECK: vstrcf   %v0, %v15, %v0, %v0, 0  # encoding: [0xe7,0x0f,0x02,0x00,0x00,0x8a]
+#CHECK: vstrcf   %v0, %v31, %v0, %v0, 0  # encoding: [0xe7,0x0f,0x02,0x00,0x04,0x8a]
+#CHECK: vstrcf   %v15, %v0, %v0, %v0, 0  # encoding: [0xe7,0xf0,0x02,0x00,0x00,0x8a]
+#CHECK: vstrcf   %v31, %v0, %v0, %v0, 0  # encoding: [0xe7,0xf0,0x02,0x00,0x08,0x8a]
+#CHECK: vstrcf   %v18, %v3, %v20, %v5, 4 # encoding: [0xe7,0x23,0x42,0x40,0x5a,0x8a]
+#CHECK: vstrcf   %v18, %v3, %v20, %v5, 15 # encoding: [0xe7,0x23,0x42,0xf0,0x5a,0x8a]
+#CHECK: vstrcfs  %v18, %v3, %v20, %v5, 8 # encoding: [0xe7,0x23,0x42,0x90,0x5a,0x8a]
+#CHECK: vstrczf  %v18, %v3, %v20, %v5, 4 # encoding: [0xe7,0x23,0x42,0x60,0x5a,0x8a]
+#CHECK: vstrczfs %v18, %v3, %v20, %v5, 8 # encoding: [0xe7,0x23,0x42,0xb0,0x5a,0x8a]
+#CHECK: vstrczfs %v18, %v3, %v20, %v5, 15 # encoding: [0xe7,0x23,0x42,0xf0,0x5a,0x8a]
+
+        vstrcf   %v0, %v0, %v0, %v0
+        vstrcf   %v0, %v0, %v0, %v0, 0
+        vstrcf   %v0, %v0, %v0, %v0, 12
+        vstrcf   %v0, %v0, %v0, %v15
+        vstrcf   %v0, %v0, %v0, %v31
+        vstrcf   %v0, %v0, %v15, %v0
+        vstrcf   %v0, %v0, %v31, %v0
+        vstrcf   %v0, %v15, %v0, %v0
+        vstrcf   %v0, %v31, %v0, %v0
+        vstrcf   %v15, %v0, %v0, %v0
+        vstrcf   %v31, %v0, %v0, %v0
+        vstrcf   %v18, %v3, %v20, %v5, 4
+        vstrcf   %v18, %v3, %v20, %v5, 15
+        vstrcfs  %v18, %v3, %v20, %v5, 8
+        vstrczf  %v18, %v3, %v20, %v5, 4
+        vstrczfs %v18, %v3, %v20, %v5, 8
+        vstrczfs %v18, %v3, %v20, %v5, 15
+
+#CHECK: vstrch   %v0, %v0, %v0, %v0, 0   # encoding: [0xe7,0x00,0x01,0x00,0x00,0x8a]
+#CHECK: vstrch   %v0, %v0, %v0, %v0, 0   # encoding: [0xe7,0x00,0x01,0x00,0x00,0x8a]
+#CHECK: vstrch   %v0, %v0, %v0, %v0, 12  # encoding: [0xe7,0x00,0x01,0xc0,0x00,0x8a]
+#CHECK: vstrch   %v0, %v0, %v0, %v15, 0  # encoding: [0xe7,0x00,0x01,0x00,0xf0,0x8a]
+#CHECK: vstrch   %v0, %v0, %v0, %v31, 0  # encoding: [0xe7,0x00,0x01,0x00,0xf1,0x8a]
+#CHECK: vstrch   %v0, %v0, %v15, %v0, 0  # encoding: [0xe7,0x00,0xf1,0x00,0x00,0x8a]
+#CHECK: vstrch   %v0, %v0, %v31, %v0, 0  # encoding: [0xe7,0x00,0xf1,0x00,0x02,0x8a]
+#CHECK: vstrch   %v0, %v15, %v0, %v0, 0  # encoding: [0xe7,0x0f,0x01,0x00,0x00,0x8a]
+#CHECK: vstrch   %v0, %v31, %v0, %v0, 0  # encoding: [0xe7,0x0f,0x01,0x00,0x04,0x8a]
+#CHECK: vstrch   %v15, %v0, %v0, %v0, 0  # encoding: [0xe7,0xf0,0x01,0x00,0x00,0x8a]
+#CHECK: vstrch   %v31, %v0, %v0, %v0, 0  # encoding: [0xe7,0xf0,0x01,0x00,0x08,0x8a]
+#CHECK: vstrch   %v18, %v3, %v20, %v5, 4 # encoding: [0xe7,0x23,0x41,0x40,0x5a,0x8a]
+#CHECK: vstrch   %v18, %v3, %v20, %v5, 15 # encoding: [0xe7,0x23,0x41,0xf0,0x5a,0x8a]
+#CHECK: vstrchs  %v18, %v3, %v20, %v5, 8 # encoding: [0xe7,0x23,0x41,0x90,0x5a,0x8a]
+#CHECK: vstrczh  %v18, %v3, %v20, %v5, 4 # encoding: [0xe7,0x23,0x41,0x60,0x5a,0x8a]
+#CHECK: vstrczhs %v18, %v3, %v20, %v5, 8 # encoding: [0xe7,0x23,0x41,0xb0,0x5a,0x8a]
+#CHECK: vstrczhs %v18, %v3, %v20, %v5, 15 # encoding: [0xe7,0x23,0x41,0xf0,0x5a,0x8a]
+
+        vstrch   %v0, %v0, %v0, %v0
+        vstrch   %v0, %v0, %v0, %v0, 0
+        vstrch   %v0, %v0, %v0, %v0, 12
+        vstrch   %v0, %v0, %v0, %v15
+        vstrch   %v0, %v0, %v0, %v31
+        vstrch   %v0, %v0, %v15, %v0
+        vstrch   %v0, %v0, %v31, %v0
+        vstrch   %v0, %v15, %v0, %v0
+        vstrch   %v0, %v31, %v0, %v0
+        vstrch   %v15, %v0, %v0, %v0
+        vstrch   %v31, %v0, %v0, %v0
+        vstrch   %v18, %v3, %v20, %v5, 4
+        vstrch   %v18, %v3, %v20, %v5, 15
+        vstrchs  %v18, %v3, %v20, %v5, 8
+        vstrczh  %v18, %v3, %v20, %v5, 4
+        vstrczhs %v18, %v3, %v20, %v5, 8
+        vstrczhs %v18, %v3, %v20, %v5, 15
+
+#CHECK: vsumgh  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0x65]
+#CHECK: vsumgh  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x65]
+#CHECK: vsumgh  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x65]
+#CHECK: vsumgh  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x65]
+#CHECK: vsumgh  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x65]
+
+	vsumgh	%v0, %v0, %v0
+	vsumgh	%v0, %v0, %v31
+	vsumgh	%v0, %v31, %v0
+	vsumgh	%v31, %v0, %v0
+	vsumgh	%v18, %v3, %v20
+
+#CHECK: vsumgf  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0x65]
+#CHECK: vsumgf  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x65]
+#CHECK: vsumgf  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x65]
+#CHECK: vsumgf  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x65]
+#CHECK: vsumgf  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x65]
+
+	vsumgf	%v0, %v0, %v0
+	vsumgf	%v0, %v0, %v31
+	vsumgf	%v0, %v31, %v0
+	vsumgf	%v31, %v0, %v0
+	vsumgf	%v18, %v3, %v20
+
+#CHECK: vsumqf  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x20,0x67]
+#CHECK: vsumqf  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x67]
+#CHECK: vsumqf  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x67]
+#CHECK: vsumqf  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x67]
+#CHECK: vsumqf  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x67]
+
+	vsumqf	%v0, %v0, %v0
+	vsumqf	%v0, %v0, %v31
+	vsumqf	%v0, %v31, %v0
+	vsumqf	%v31, %v0, %v0
+	vsumqf	%v18, %v3, %v20
+
+#CHECK: vsumqg  %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x30,0x67]
+#CHECK: vsumqg  %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x67]
+#CHECK: vsumqg  %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x67]
+#CHECK: vsumqg  %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x67]
+#CHECK: vsumqg  %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x67]
+
+	vsumqg	%v0, %v0, %v0
+	vsumqg	%v0, %v0, %v31
+	vsumqg	%v0, %v31, %v0
+	vsumqg	%v31, %v0, %v0
+	vsumqg	%v18, %v3, %v20
+
+#CHECK: vsumb   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x64]
+#CHECK: vsumb   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x64]
+#CHECK: vsumb   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x64]
+#CHECK: vsumb   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x64]
+#CHECK: vsumb   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x64]
+
+	vsumb	%v0, %v0, %v0
+	vsumb	%v0, %v0, %v31
+	vsumb	%v0, %v31, %v0
+	vsumb	%v31, %v0, %v0
+	vsumb	%v18, %v3, %v20
+
+#CHECK: vsumh   %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x10,0x64]
+#CHECK: vsumh   %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x64]
+#CHECK: vsumh   %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x64]
+#CHECK: vsumh   %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x64]
+#CHECK: vsumh   %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x64]
+
+	vsumh	%v0, %v0, %v0
+	vsumh	%v0, %v0, %v31
+	vsumh	%v0, %v31, %v0
+	vsumh	%v31, %v0, %v0
+	vsumh	%v18, %v3, %v20
+
+#CHECK: vtm     %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x00,0xd8]
+#CHECK: vtm     %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xd8]
+#CHECK: vtm     %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xd8]
+#CHECK: vtm     %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xd8]
+#CHECK: vtm     %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xd8]
+#CHECK: vtm     %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xd8]
+
+	vtm	%v0, %v0
+	vtm	%v0, %v15
+	vtm	%v0, %v31
+	vtm	%v15, %v0
+	vtm	%v31, %v0
+	vtm	%v14, %v17
+
+#CHECK: vuphb   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x00,0xd7]
+#CHECK: vuphb   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xd7]
+#CHECK: vuphb   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xd7]
+#CHECK: vuphb   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xd7]
+#CHECK: vuphb   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xd7]
+#CHECK: vuphb   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xd7]
+
+	vuphb	%v0, %v0
+	vuphb	%v0, %v15
+	vuphb	%v0, %v31
+	vuphb	%v15, %v0
+	vuphb	%v31, %v0
+	vuphb	%v14, %v17
+
+#CHECK: vuphf   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x20,0xd7]
+#CHECK: vuphf   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xd7]
+#CHECK: vuphf   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xd7]
+#CHECK: vuphf   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xd7]
+#CHECK: vuphf   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xd7]
+#CHECK: vuphf   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xd7]
+
+	vuphf	%v0, %v0
+	vuphf	%v0, %v15
+	vuphf	%v0, %v31
+	vuphf	%v15, %v0
+	vuphf	%v31, %v0
+	vuphf	%v14, %v17
+
+#CHECK: vuphh   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x10,0xd7]
+#CHECK: vuphh   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xd7]
+#CHECK: vuphh   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xd7]
+#CHECK: vuphh   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xd7]
+#CHECK: vuphh   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xd7]
+#CHECK: vuphh   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xd7]
+
+	vuphh	%v0, %v0
+	vuphh	%v0, %v15
+	vuphh	%v0, %v31
+	vuphh	%v15, %v0
+	vuphh	%v31, %v0
+	vuphh	%v14, %v17
+
+#CHECK: vuplhb  %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x00,0xd5]
+#CHECK: vuplhb  %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xd5]
+#CHECK: vuplhb  %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xd5]
+#CHECK: vuplhb  %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xd5]
+#CHECK: vuplhb  %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xd5]
+#CHECK: vuplhb  %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xd5]
+
+	vuplhb	%v0, %v0
+	vuplhb	%v0, %v15
+	vuplhb	%v0, %v31
+	vuplhb	%v15, %v0
+	vuplhb	%v31, %v0
+	vuplhb	%v14, %v17
+
+#CHECK: vuplhf  %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x20,0xd5]
+#CHECK: vuplhf  %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xd5]
+#CHECK: vuplhf  %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xd5]
+#CHECK: vuplhf  %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xd5]
+#CHECK: vuplhf  %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xd5]
+#CHECK: vuplhf  %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xd5]
+
+	vuplhf	%v0, %v0
+	vuplhf	%v0, %v15
+	vuplhf	%v0, %v31
+	vuplhf	%v15, %v0
+	vuplhf	%v31, %v0
+	vuplhf	%v14, %v17
+
+#CHECK: vuplhh  %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x10,0xd5]
+#CHECK: vuplhh  %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xd5]
+#CHECK: vuplhh  %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xd5]
+#CHECK: vuplhh  %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xd5]
+#CHECK: vuplhh  %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xd5]
+#CHECK: vuplhh  %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xd5]
+
+	vuplhh	%v0, %v0
+	vuplhh	%v0, %v15
+	vuplhh	%v0, %v31
+	vuplhh	%v15, %v0
+	vuplhh	%v31, %v0
+	vuplhh	%v14, %v17
+
+#CHECK: vuplb   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x00,0xd6]
+#CHECK: vuplb   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xd6]
+#CHECK: vuplb   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xd6]
+#CHECK: vuplb   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xd6]
+#CHECK: vuplb   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xd6]
+#CHECK: vuplb   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xd6]
+
+	vuplb	%v0, %v0
+	vuplb	%v0, %v15
+	vuplb	%v0, %v31
+	vuplb	%v15, %v0
+	vuplb	%v31, %v0
+	vuplb	%v14, %v17
+
+#CHECK: vuplf   %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x20,0xd6]
+#CHECK: vuplf   %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xd6]
+#CHECK: vuplf   %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xd6]
+#CHECK: vuplf   %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xd6]
+#CHECK: vuplf   %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xd6]
+#CHECK: vuplf   %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xd6]
+
+	vuplf	%v0, %v0
+	vuplf	%v0, %v15
+	vuplf	%v0, %v31
+	vuplf	%v15, %v0
+	vuplf	%v31, %v0
+	vuplf	%v14, %v17
+
+#CHECK: vuplhw  %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x10,0xd6]
+#CHECK: vuplhw  %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xd6]
+#CHECK: vuplhw  %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xd6]
+#CHECK: vuplhw  %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xd6]
+#CHECK: vuplhw  %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xd6]
+#CHECK: vuplhw  %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xd6]
+
+	vuplhw	%v0, %v0
+	vuplhw	%v0, %v15
+	vuplhw	%v0, %v31
+	vuplhw	%v15, %v0
+	vuplhw	%v31, %v0
+	vuplhw	%v14, %v17
+
+#CHECK: vupllb  %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x00,0xd4]
+#CHECK: vupllb  %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xd4]
+#CHECK: vupllb  %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xd4]
+#CHECK: vupllb  %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xd4]
+#CHECK: vupllb  %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xd4]
+#CHECK: vupllb  %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xd4]
+
+	vupllb	%v0, %v0
+	vupllb	%v0, %v15
+	vupllb	%v0, %v31
+	vupllb	%v15, %v0
+	vupllb	%v31, %v0
+	vupllb	%v14, %v17
+
+#CHECK: vupllf  %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x20,0xd4]
+#CHECK: vupllf  %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xd4]
+#CHECK: vupllf  %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xd4]
+#CHECK: vupllf  %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xd4]
+#CHECK: vupllf  %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xd4]
+#CHECK: vupllf  %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xd4]
+
+	vupllf	%v0, %v0
+	vupllf	%v0, %v15
+	vupllf	%v0, %v31
+	vupllf	%v15, %v0
+	vupllf	%v31, %v0
+	vupllf	%v14, %v17
+
+#CHECK: vupllh  %v0, %v0                # encoding: [0xe7,0x00,0x00,0x00,0x10,0xd4]
+#CHECK: vupllh  %v0, %v15               # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xd4]
+#CHECK: vupllh  %v0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xd4]
+#CHECK: vupllh  %v15, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xd4]
+#CHECK: vupllh  %v31, %v0               # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xd4]
+#CHECK: vupllh  %v14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xd4]
+
+	vupllh	%v0, %v0
+	vupllh	%v0, %v15
+	vupllh	%v0, %v31
+	vupllh	%v15, %v0
+	vupllh	%v31, %v0
+	vupllh	%v14, %v17
+
+#CHECK: vx      %v0, %v0, %v0           # encoding: [0xe7,0x00,0x00,0x00,0x00,0x6d]
+#CHECK: vx      %v0, %v0, %v31          # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x6d]
+#CHECK: vx      %v0, %v31, %v0          # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x6d]
+#CHECK: vx      %v31, %v0, %v0          # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x6d]
+#CHECK: vx      %v18, %v3, %v20         # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x6d]
+
+	vx	%v0, %v0, %v0
+	vx	%v0, %v0, %v31
+	vx	%v0, %v31, %v0
+	vx	%v31, %v0, %v0
+	vx	%v18, %v3, %v20
+
+#CHECK: vzero   %v0                     # encoding: [0xe7,0x00,0x00,0x00,0x00,0x44]
+#CHECK: vzero   %v11                    # encoding: [0xe7,0xb0,0x00,0x00,0x00,0x44]
+#CHECK: vzero   %v15                    # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x44]
+#CHECK: vzero   %v31                    # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x44]
+
+	vzero	%v0
+	vzero	%v11
+	vzero	%v15
+	vzero	%v31
+
+#CHECK: wcdgb   %f0, %f0, 0, 0          # encoding: [0xe7,0x00,0x00,0x08,0x30,0xc3]
+#CHECK: wcdgb   %f0, %f0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf8,0x30,0xc3]
+#CHECK: wcdgb   %f0, %f0, 4, 0          # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc3]
+#CHECK: wcdgb   %f0, %f0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc3]
+#CHECK: wcdgb   %f0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xc3]
+#CHECK: wcdgb   %v31, %f0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xc3]
+#CHECK: wcdgb   %f14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xac,0x34,0xc3]
+
+	wcdgb	%v0, %v0, 0, 0
+ 	wcdgb	%v0, %v0, 0, 15
+	wcdgb	%v0, %v0, 4, 0
+	wcdgb	%v0, %v0, 12, 0
+	wcdgb	%v0, %v31, 0, 0
+	wcdgb	%v31, %v0, 0, 0
+	wcdgb	%v14, %v17, 4, 10
+
+#CHECK: wcdlgb  %f0, %f0, 0, 0          # encoding: [0xe7,0x00,0x00,0x08,0x30,0xc1]
+#CHECK: wcdlgb  %f0, %f0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf8,0x30,0xc1]
+#CHECK: wcdlgb  %f0, %f0, 4, 0          # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc1]
+#CHECK: wcdlgb  %f0, %f0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc1]
+#CHECK: wcdlgb  %f0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xc1]
+#CHECK: wcdlgb  %v31, %f0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xc1]
+#CHECK: wcdlgb  %f14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xac,0x34,0xc1]
+
+	wcdlgb	%v0, %v0, 0, 0
+ 	wcdlgb	%v0, %v0, 0, 15
+	wcdlgb	%v0, %v0, 4, 0
+	wcdlgb	%v0, %v0, 12, 0
+	wcdlgb	%v0, %v31, 0, 0
+	wcdlgb	%v31, %v0, 0, 0
+	wcdlgb	%v14, %v17, 4, 10
+
+#CHECK: wcgdb   %f0, %f0, 0, 0          # encoding: [0xe7,0x00,0x00,0x08,0x30,0xc2]
+#CHECK: wcgdb   %f0, %f0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf8,0x30,0xc2]
+#CHECK: wcgdb   %f0, %f0, 4, 0          # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc2]
+#CHECK: wcgdb   %f0, %f0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc2]
+#CHECK: wcgdb   %f0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xc2]
+#CHECK: wcgdb   %v31, %f0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xc2]
+#CHECK: wcgdb   %f14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xac,0x34,0xc2]
+
+	wcgdb	%v0, %v0, 0, 0
+ 	wcgdb	%v0, %v0, 0, 15
+	wcgdb	%v0, %v0, 4, 0
+	wcgdb	%v0, %v0, 12, 0
+	wcgdb	%v0, %v31, 0, 0
+	wcgdb	%v31, %v0, 0, 0
+	wcgdb	%v14, %v17, 4, 10
+
+#CHECK: wclgdb  %f0, %f0, 0, 0          # encoding: [0xe7,0x00,0x00,0x08,0x30,0xc0]
+#CHECK: wclgdb  %f0, %f0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf8,0x30,0xc0]
+#CHECK: wclgdb  %f0, %f0, 4, 0          # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc0]
+#CHECK: wclgdb  %f0, %f0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc0]
+#CHECK: wclgdb  %f0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xc0]
+#CHECK: wclgdb  %v31, %f0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xc0]
+#CHECK: wclgdb  %f14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xac,0x34,0xc0]
+
+	wclgdb	%v0, %v0, 0, 0
+ 	wclgdb	%v0, %v0, 0, 15
+	wclgdb	%v0, %v0, 4, 0
+	wclgdb	%v0, %v0, 12, 0
+	wclgdb	%v0, %v31, 0, 0
+	wclgdb	%v31, %v0, 0, 0
+	wclgdb	%v14, %v17, 4, 10
+
+#CHECK: wfadb   %f0, %f0, %f0           # encoding: [0xe7,0x00,0x00,0x08,0x30,0xe3]
+#CHECK: wfadb   %f0, %f0, %v31          # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xe3]
+#CHECK: wfadb   %f0, %v31, %f0          # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xe3]
+#CHECK: wfadb   %v31, %f0, %f0          # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xe3]
+#CHECK: wfadb   %v18, %f3, %v20         # encoding: [0xe7,0x23,0x40,0x08,0x3a,0xe3]
+
+	wfadb	%v0, %v0, %v0
+	wfadb	%v0, %v0, %v31
+	wfadb	%v0, %v31, %v0
+	wfadb	%v31, %v0, %v0
+	wfadb	%v18, %v3, %v20
+
+#CHECK: wfcdb   %f0, %f0                # encoding: [0xe7,0x00,0x00,0x00,0x30,0xcb]
+#CHECK: wfcdb   %f0, %f15               # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xcb]
+#CHECK: wfcdb   %f0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xcb]
+#CHECK: wfcdb   %f15, %f0               # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xcb]
+#CHECK: wfcdb   %v31, %f0               # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xcb]
+#CHECK: wfcdb   %f14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xcb]
+
+	wfcdb	%v0, %v0
+	wfcdb	%v0, %v15
+	wfcdb	%v0, %v31
+	wfcdb	%v15, %v0
+	wfcdb	%v31, %v0
+	wfcdb	%v14, %v17
+
+#CHECK: wfcedb  %f0, %f0, %f0           # encoding: [0xe7,0x00,0x00,0x08,0x30,0xe8]
+#CHECK: wfcedb  %f0, %f0, %v31          # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xe8]
+#CHECK: wfcedb  %f0, %v31, %f0          # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xe8]
+#CHECK: wfcedb  %v31, %f0, %f0          # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xe8]
+#CHECK: wfcedb  %v18, %f3, %v20         # encoding: [0xe7,0x23,0x40,0x08,0x3a,0xe8]
+
+	wfcedb	%v0, %v0, %v0
+	wfcedb	%v0, %v0, %v31
+	wfcedb	%v0, %v31, %v0
+	wfcedb	%v31, %v0, %v0
+	wfcedb	%v18, %v3, %v20
+
+#CHECK: wfcedbs %f0, %f0, %f0           # encoding: [0xe7,0x00,0x00,0x18,0x30,0xe8]
+#CHECK: wfcedbs %f0, %f0, %v31          # encoding: [0xe7,0x00,0xf0,0x18,0x32,0xe8]
+#CHECK: wfcedbs %f0, %v31, %f0          # encoding: [0xe7,0x0f,0x00,0x18,0x34,0xe8]
+#CHECK: wfcedbs %v31, %f0, %f0          # encoding: [0xe7,0xf0,0x00,0x18,0x38,0xe8]
+#CHECK: wfcedbs %v18, %f3, %v20         # encoding: [0xe7,0x23,0x40,0x18,0x3a,0xe8]
+
+	wfcedbs	%v0, %v0, %v0
+	wfcedbs	%v0, %v0, %v31
+	wfcedbs	%v0, %v31, %v0
+	wfcedbs	%v31, %v0, %v0
+	wfcedbs	%v18, %v3, %v20
+
+#CHECK: wfchdb  %f0, %f0, %f0           # encoding: [0xe7,0x00,0x00,0x08,0x30,0xeb]
+#CHECK: wfchdb  %f0, %f0, %v31          # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xeb]
+#CHECK: wfchdb  %f0, %v31, %f0          # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xeb]
+#CHECK: wfchdb  %v31, %f0, %f0          # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xeb]
+#CHECK: wfchdb  %v18, %f3, %v20         # encoding: [0xe7,0x23,0x40,0x08,0x3a,0xeb]
+
+	wfchdb	%v0, %v0, %v0
+	wfchdb	%v0, %v0, %v31
+	wfchdb	%v0, %v31, %v0
+	wfchdb	%v31, %v0, %v0
+	wfchdb	%v18, %v3, %v20
+
+#CHECK: wfchdbs %f0, %f0, %f0           # encoding: [0xe7,0x00,0x00,0x18,0x30,0xeb]
+#CHECK: wfchdbs %f0, %f0, %v31          # encoding: [0xe7,0x00,0xf0,0x18,0x32,0xeb]
+#CHECK: wfchdbs %f0, %v31, %f0          # encoding: [0xe7,0x0f,0x00,0x18,0x34,0xeb]
+#CHECK: wfchdbs %v31, %f0, %f0          # encoding: [0xe7,0xf0,0x00,0x18,0x38,0xeb]
+#CHECK: wfchdbs %v18, %f3, %v20         # encoding: [0xe7,0x23,0x40,0x18,0x3a,0xeb]
+
+	wfchdbs	%v0, %v0, %v0
+	wfchdbs	%v0, %v0, %v31
+	wfchdbs	%v0, %v31, %v0
+	wfchdbs	%v31, %v0, %v0
+	wfchdbs	%v18, %v3, %v20
+
+#CHECK: wfchedb %f0, %f0, %f0           # encoding: [0xe7,0x00,0x00,0x08,0x30,0xea]
+#CHECK: wfchedb %f0, %f0, %v31          # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xea]
+#CHECK: wfchedb %f0, %v31, %f0          # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xea]
+#CHECK: wfchedb %v31, %f0, %f0          # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xea]
+#CHECK: wfchedb %v18, %f3, %v20         # encoding: [0xe7,0x23,0x40,0x08,0x3a,0xea]
+
+	wfchedb	%v0, %v0, %v0
+	wfchedb	%v0, %v0, %v31
+	wfchedb	%v0, %v31, %v0
+	wfchedb	%v31, %v0, %v0
+	wfchedb	%v18, %v3, %v20
+
+#CHECK: wfchedbs %f0, %f0, %f0          # encoding: [0xe7,0x00,0x00,0x18,0x30,0xea]
+#CHECK: wfchedbs %f0, %f0, %v31         # encoding: [0xe7,0x00,0xf0,0x18,0x32,0xea]
+#CHECK: wfchedbs %f0, %v31, %f0         # encoding: [0xe7,0x0f,0x00,0x18,0x34,0xea]
+#CHECK: wfchedbs %v31, %f0, %f0         # encoding: [0xe7,0xf0,0x00,0x18,0x38,0xea]
+#CHECK: wfchedbs %v18, %f3, %v20        # encoding: [0xe7,0x23,0x40,0x18,0x3a,0xea]
+
+	wfchedbs %v0, %v0, %v0
+	wfchedbs %v0, %v0, %v31
+	wfchedbs %v0, %v31, %v0
+	wfchedbs %v31, %v0, %v0
+	wfchedbs %v18, %v3, %v20
+
+#CHECK: wfddb   %f0, %f0, %f0           # encoding: [0xe7,0x00,0x00,0x08,0x30,0xe5]
+#CHECK: wfddb   %f0, %f0, %v31          # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xe5]
+#CHECK: wfddb   %f0, %v31, %f0          # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xe5]
+#CHECK: wfddb   %v31, %f0, %f0          # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xe5]
+#CHECK: wfddb   %v18, %f3, %v20         # encoding: [0xe7,0x23,0x40,0x08,0x3a,0xe5]
+
+	wfddb	%v0, %v0, %v0
+	wfddb	%v0, %v0, %v31
+	wfddb	%v0, %v31, %v0
+	wfddb	%v31, %v0, %v0
+	wfddb	%v18, %v3, %v20
+
+#CHECK: wfidb   %f0, %f0, 0, 0          # encoding: [0xe7,0x00,0x00,0x08,0x30,0xc7]
+#CHECK: wfidb   %f0, %f0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf8,0x30,0xc7]
+#CHECK: wfidb   %f0, %f0, 4, 0          # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc7]
+#CHECK: wfidb   %f0, %f0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc7]
+#CHECK: wfidb   %f0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xc7]
+#CHECK: wfidb   %v31, %f0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xc7]
+#CHECK: wfidb   %f14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xac,0x34,0xc7]
+
+	wfidb	%v0, %v0, 0, 0
+ 	wfidb	%v0, %v0, 0, 15
+	wfidb	%v0, %v0, 4, 0
+	wfidb	%v0, %v0, 12, 0
+	wfidb	%v0, %v31, 0, 0
+	wfidb	%v31, %v0, 0, 0
+	wfidb	%v14, %v17, 4, 10
+
+#CHECK: wfkdb   %f0, %f0                # encoding: [0xe7,0x00,0x00,0x00,0x30,0xca]
+#CHECK: wfkdb   %f0, %f15               # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xca]
+#CHECK: wfkdb   %f0, %v31               # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xca]
+#CHECK: wfkdb   %f15, %f0               # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xca]
+#CHECK: wfkdb   %v31, %f0               # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xca]
+#CHECK: wfkdb   %f14, %v17              # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xca]
+
+	wfkdb	%v0, %v0
+	wfkdb	%v0, %v15
+	wfkdb	%v0, %v31
+	wfkdb	%v15, %v0
+	wfkdb	%v31, %v0
+	wfkdb	%v14, %v17
+
+#CHECK: wflcdb  %f0, %f0                # encoding: [0xe7,0x00,0x00,0x08,0x30,0xcc]
+#CHECK: wflcdb  %f0, %f15               # encoding: [0xe7,0x0f,0x00,0x08,0x30,0xcc]
+#CHECK: wflcdb  %f0, %v31               # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xcc]
+#CHECK: wflcdb  %f15, %f0               # encoding: [0xe7,0xf0,0x00,0x08,0x30,0xcc]
+#CHECK: wflcdb  %v31, %f0               # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xcc]
+#CHECK: wflcdb  %f14, %v17              # encoding: [0xe7,0xe1,0x00,0x08,0x34,0xcc]
+
+	wflcdb	%v0, %v0
+	wflcdb	%v0, %v15
+	wflcdb	%v0, %v31
+	wflcdb	%v15, %v0
+	wflcdb	%v31, %v0
+	wflcdb	%v14, %v17
+
+#CHECK: wflndb  %f0, %f0                # encoding: [0xe7,0x00,0x00,0x18,0x30,0xcc]
+#CHECK: wflndb  %f0, %f15               # encoding: [0xe7,0x0f,0x00,0x18,0x30,0xcc]
+#CHECK: wflndb  %f0, %v31               # encoding: [0xe7,0x0f,0x00,0x18,0x34,0xcc]
+#CHECK: wflndb  %f15, %f0               # encoding: [0xe7,0xf0,0x00,0x18,0x30,0xcc]
+#CHECK: wflndb  %v31, %f0               # encoding: [0xe7,0xf0,0x00,0x18,0x38,0xcc]
+#CHECK: wflndb  %f14, %v17              # encoding: [0xe7,0xe1,0x00,0x18,0x34,0xcc]
+
+	wflndb	%v0, %v0
+	wflndb	%v0, %v15
+	wflndb	%v0, %v31
+	wflndb	%v15, %v0
+	wflndb	%v31, %v0
+	wflndb	%v14, %v17
+
+#CHECK: wflpdb  %f0, %f0                # encoding: [0xe7,0x00,0x00,0x28,0x30,0xcc]
+#CHECK: wflpdb  %f0, %f15               # encoding: [0xe7,0x0f,0x00,0x28,0x30,0xcc]
+#CHECK: wflpdb  %f0, %v31               # encoding: [0xe7,0x0f,0x00,0x28,0x34,0xcc]
+#CHECK: wflpdb  %f15, %f0               # encoding: [0xe7,0xf0,0x00,0x28,0x30,0xcc]
+#CHECK: wflpdb  %v31, %f0               # encoding: [0xe7,0xf0,0x00,0x28,0x38,0xcc]
+#CHECK: wflpdb  %f14, %v17              # encoding: [0xe7,0xe1,0x00,0x28,0x34,0xcc]
+
+	wflpdb	%v0, %v0
+	wflpdb	%v0, %v15
+	wflpdb	%v0, %v31
+	wflpdb	%v15, %v0
+	wflpdb	%v31, %v0
+	wflpdb	%v14, %v17
+
+#CHECK: wfmadb  %f0, %f0, %f0, %f0      # encoding: [0xe7,0x00,0x03,0x08,0x00,0x8f]
+#CHECK: wfmadb  %f0, %f0, %f0, %v31     # encoding: [0xe7,0x00,0x03,0x08,0xf1,0x8f]
+#CHECK: wfmadb  %f0, %f0, %v31, %f0     # encoding: [0xe7,0x00,0xf3,0x08,0x02,0x8f]
+#CHECK: wfmadb  %f0, %v31, %f0, %f0     # encoding: [0xe7,0x0f,0x03,0x08,0x04,0x8f]
+#CHECK: wfmadb  %v31, %f0, %f0, %f0     # encoding: [0xe7,0xf0,0x03,0x08,0x08,0x8f]
+#CHECK: wfmadb  %f13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x53,0x08,0x97,0x8f]
+
+	wfmadb	%v0, %v0, %v0, %v0
+	wfmadb	%v0, %v0, %v0, %v31
+	wfmadb	%v0, %v0, %v31, %v0
+	wfmadb	%v0, %v31, %v0, %v0
+	wfmadb	%v31, %v0, %v0, %v0
+	wfmadb	%v13, %v17, %v21, %v25
+
+#CHECK: wfmdb   %f0, %f0, %f0           # encoding: [0xe7,0x00,0x00,0x08,0x30,0xe7]
+#CHECK: wfmdb   %f0, %f0, %v31          # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xe7]
+#CHECK: wfmdb   %f0, %v31, %f0          # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xe7]
+#CHECK: wfmdb   %v31, %f0, %f0          # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xe7]
+#CHECK: wfmdb   %v18, %f3, %v20         # encoding: [0xe7,0x23,0x40,0x08,0x3a,0xe7]
+
+	wfmdb	%v0, %v0, %v0
+	wfmdb	%v0, %v0, %v31
+	wfmdb	%v0, %v31, %v0
+	wfmdb	%v31, %v0, %v0
+	wfmdb	%v18, %v3, %v20
+
+#CHECK: wfmsdb  %f0, %f0, %f0, %f0      # encoding: [0xe7,0x00,0x03,0x08,0x00,0x8e]
+#CHECK: wfmsdb  %f0, %f0, %f0, %v31     # encoding: [0xe7,0x00,0x03,0x08,0xf1,0x8e]
+#CHECK: wfmsdb  %f0, %f0, %v31, %f0     # encoding: [0xe7,0x00,0xf3,0x08,0x02,0x8e]
+#CHECK: wfmsdb  %f0, %v31, %f0, %f0     # encoding: [0xe7,0x0f,0x03,0x08,0x04,0x8e]
+#CHECK: wfmsdb  %v31, %f0, %f0, %f0     # encoding: [0xe7,0xf0,0x03,0x08,0x08,0x8e]
+#CHECK: wfmsdb  %f13, %v17, %v21, %v25  # encoding: [0xe7,0xd1,0x53,0x08,0x97,0x8e]
+
+	wfmsdb	%v0, %v0, %v0, %v0
+	wfmsdb	%v0, %v0, %v0, %v31
+	wfmsdb	%v0, %v0, %v31, %v0
+	wfmsdb	%v0, %v31, %v0, %v0
+	wfmsdb	%v31, %v0, %v0, %v0
+	wfmsdb	%v13, %v17, %v21, %v25
+
+#CHECK: wfsdb   %f0, %f0, %f0           # encoding: [0xe7,0x00,0x00,0x08,0x30,0xe2]
+#CHECK: wfsdb   %f0, %f0, %v31          # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xe2]
+#CHECK: wfsdb   %f0, %v31, %f0          # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xe2]
+#CHECK: wfsdb   %v31, %f0, %f0          # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xe2]
+#CHECK: wfsdb   %v18, %f3, %v20         # encoding: [0xe7,0x23,0x40,0x08,0x3a,0xe2]
+
+	wfsdb	%v0, %v0, %v0
+	wfsdb	%v0, %v0, %v31
+	wfsdb	%v0, %v31, %v0
+	wfsdb	%v31, %v0, %v0
+	wfsdb	%v18, %v3, %v20
+
+#CHECK: wfsqdb  %f0, %f0                # encoding: [0xe7,0x00,0x00,0x08,0x30,0xce]
+#CHECK: wfsqdb  %f0, %f15               # encoding: [0xe7,0x0f,0x00,0x08,0x30,0xce]
+#CHECK: wfsqdb  %f0, %v31               # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xce]
+#CHECK: wfsqdb  %f15, %f0               # encoding: [0xe7,0xf0,0x00,0x08,0x30,0xce]
+#CHECK: wfsqdb  %v31, %f0               # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xce]
+#CHECK: wfsqdb  %f14, %v17              # encoding: [0xe7,0xe1,0x00,0x08,0x34,0xce]
+
+	wfsqdb	%v0, %v0
+	wfsqdb	%v0, %v15
+	wfsqdb	%v0, %v31
+	wfsqdb	%v15, %v0
+	wfsqdb	%v31, %v0
+	wfsqdb	%v14, %v17
+
+#CHECK: wftcidb %f0, %f0, 0             # encoding: [0xe7,0x00,0x00,0x08,0x30,0x4a]
+#CHECK: wftcidb %f0, %f0, 4095          # encoding: [0xe7,0x00,0xff,0xf8,0x30,0x4a]
+#CHECK: wftcidb %f0, %f15, 0            # encoding: [0xe7,0x0f,0x00,0x08,0x30,0x4a]
+#CHECK: wftcidb %f0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x08,0x34,0x4a]
+#CHECK: wftcidb %f15, %f0, 0            # encoding: [0xe7,0xf0,0x00,0x08,0x30,0x4a]
+#CHECK: wftcidb %v31, %f0, 0            # encoding: [0xe7,0xf0,0x00,0x08,0x38,0x4a]
+#CHECK: wftcidb %f4, %v21, 1656         # encoding: [0xe7,0x45,0x67,0x88,0x34,0x4a]
+
+	wftcidb	%v0, %v0, 0
+	wftcidb	%v0, %v0, 4095
+	wftcidb	%v0, %v15, 0
+	wftcidb	%v0, %v31, 0
+	wftcidb	%v15, %v0, 0
+	wftcidb	%v31, %v0, 0
+	wftcidb	%v4, %v21, 0x678
+
+#CHECK: wldeb   %f0, %f0                # encoding: [0xe7,0x00,0x00,0x08,0x20,0xc4]
+#CHECK: wldeb   %f0, %f15               # encoding: [0xe7,0x0f,0x00,0x08,0x20,0xc4]
+#CHECK: wldeb   %f0, %v31               # encoding: [0xe7,0x0f,0x00,0x08,0x24,0xc4]
+#CHECK: wldeb   %f15, %f0               # encoding: [0xe7,0xf0,0x00,0x08,0x20,0xc4]
+#CHECK: wldeb   %v31, %f0               # encoding: [0xe7,0xf0,0x00,0x08,0x28,0xc4]
+#CHECK: wldeb   %f14, %v17              # encoding: [0xe7,0xe1,0x00,0x08,0x24,0xc4]
+
+	wldeb	%v0, %v0
+	wldeb	%v0, %v15
+	wldeb	%v0, %v31
+	wldeb	%v15, %v0
+	wldeb	%v31, %v0
+	wldeb	%v14, %v17
+
+#CHECK: wledb   %f0, %f0, 0, 0          # encoding: [0xe7,0x00,0x00,0x08,0x30,0xc5]
+#CHECK: wledb   %f0, %f0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf8,0x30,0xc5]
+#CHECK: wledb   %f0, %f0, 4, 0          # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc5]
+#CHECK: wledb   %f0, %f0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc5]
+#CHECK: wledb   %f0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xc5]
+#CHECK: wledb   %v31, %f0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xc5]
+#CHECK: wledb   %f14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xac,0x34,0xc5]
+
+	wledb	%v0, %v0, 0, 0
+ 	wledb	%v0, %v0, 0, 15
+	wledb	%v0, %v0, 4, 0
+	wledb	%v0, %v0, 12, 0
+	wledb	%v0, %v31, 0, 0
+	wledb	%v31, %v0, 0, 0
+	wledb	%v14, %v17, 4, 10
diff --git a/test/MC/SystemZ/insn-good-z196.s b/test/MC/SystemZ/insn-good-z196.s
index db5ecdd238ca..36bea38f5fee 100644
--- a/test/MC/SystemZ/insn-good-z196.s
+++ b/test/MC/SystemZ/insn-good-z196.s
@@ -1021,6 +1021,16 @@
 	ork	%r15,%r0,%r0
 	ork	%r7,%r8,%r9
 
+#CHECK: popcnt	%r0, %r0                # encoding: [0xb9,0xe1,0x00,0x00]
+#CHECK: popcnt	%r0, %r15               # encoding: [0xb9,0xe1,0x00,0x0f]
+#CHECK: popcnt	%r15, %r0               # encoding: [0xb9,0xe1,0x00,0xf0]
+#CHECK: popcnt	%r7, %r8                # encoding: [0xb9,0xe1,0x00,0x78]
+
+	popcnt	%r0,%r0
+	popcnt	%r0,%r15
+	popcnt	%r15,%r0
+	popcnt	%r7,%r8
+
 #CHECK: risbhg	%r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x5d]
 #CHECK: risbhg	%r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x5d]
 #CHECK: risbhg	%r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x5d]
diff --git a/test/MC/SystemZ/insn-good-zEC12.s b/test/MC/SystemZ/insn-good-zEC12.s
new file mode 100644
index 000000000000..0610de3020b5
--- /dev/null
+++ b/test/MC/SystemZ/insn-good-zEC12.s
@@ -0,0 +1,126 @@
+# For zEC12 and above.
+# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 -show-encoding %s | FileCheck %s
+
+#CHECK: etnd	%r0                     # encoding: [0xb2,0xec,0x00,0x00]
+#CHECK: etnd	%r15                    # encoding: [0xb2,0xec,0x00,0xf0]
+#CHECK: etnd	%r7                     # encoding: [0xb2,0xec,0x00,0x70]
+
+	etnd	%r0
+	etnd	%r15
+	etnd	%r7
+
+#CHECK: ntstg	%r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x25]
+#CHECK: ntstg	%r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x25]
+#CHECK: ntstg	%r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x25]
+#CHECK: ntstg	%r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x25]
+#CHECK: ntstg	%r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x25]
+#CHECK: ntstg	%r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x25]
+#CHECK: ntstg	%r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x25]
+#CHECK: ntstg	%r0, 524287(%r1,%r15)   # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x25]
+#CHECK: ntstg	%r0, 524287(%r15,%r1)   # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x25]
+#CHECK: ntstg	%r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x25]
+
+	ntstg	%r0, -524288
+	ntstg	%r0, -1
+	ntstg	%r0, 0
+	ntstg	%r0, 1
+	ntstg	%r0, 524287
+	ntstg	%r0, 0(%r1)
+	ntstg	%r0, 0(%r15)
+	ntstg	%r0, 524287(%r1,%r15)
+	ntstg	%r0, 524287(%r15,%r1)
+	ntstg	%r15, 0
+
+#CHECK: ppa	%r0, %r0, 0             # encoding: [0xb2,0xe8,0x00,0x00]
+#CHECK: ppa	%r0, %r0, 15            # encoding: [0xb2,0xe8,0xf0,0x00]
+#CHECK: ppa	%r0, %r15, 0            # encoding: [0xb2,0xe8,0x00,0x0f]
+#CHECK: ppa	%r4, %r6, 7             # encoding: [0xb2,0xe8,0x70,0x46]
+#CHECK: ppa	%r15, %r0, 0            # encoding: [0xb2,0xe8,0x00,0xf0]
+
+	ppa	%r0, %r0, 0
+	ppa	%r0, %r0, 15
+	ppa	%r0, %r15, 0
+	ppa	%r4, %r6, 7
+	ppa	%r15, %r0, 0
+
+#CHECK: risbgn	%r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x59]
+#CHECK: risbgn	%r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59]
+#CHECK: risbgn	%r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x59]
+#CHECK: risbgn	%r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x59]
+#CHECK: risbgn	%r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x59]
+#CHECK: risbgn	%r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x59]
+#CHECK: risbgn	%r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x59]
+
+	risbgn	%r0,%r0,0,0,0
+	risbgn	%r0,%r0,0,0,63
+	risbgn	%r0,%r0,0,255,0
+	risbgn	%r0,%r0,255,0,0
+	risbgn	%r0,%r15,0,0,0
+	risbgn	%r15,%r0,0,0,0
+	risbgn	%r4,%r5,6,7,8
+
+#CHECK: tabort	0                       # encoding: [0xb2,0xfc,0x00,0x00]
+#CHECK: tabort	0(%r1)                  # encoding: [0xb2,0xfc,0x10,0x00]
+#CHECK: tabort	0(%r15)                 # encoding: [0xb2,0xfc,0xf0,0x00]
+#CHECK: tabort	4095                    # encoding: [0xb2,0xfc,0x0f,0xff]
+#CHECK: tabort	4095(%r1)               # encoding: [0xb2,0xfc,0x1f,0xff]
+#CHECK: tabort	4095(%r15)              # encoding: [0xb2,0xfc,0xff,0xff]
+
+	tabort	0
+	tabort	0(%r1)
+	tabort	0(%r15)
+	tabort	4095
+	tabort	4095(%r1)
+	tabort	4095(%r15)
+
+#CHECK: tbegin	0, 0                    # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00]
+#CHECK: tbegin	4095, 0                 # encoding: [0xe5,0x60,0x0f,0xff,0x00,0x00]
+#CHECK: tbegin	0, 0                    # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00]
+#CHECK: tbegin	0, 1                    # encoding: [0xe5,0x60,0x00,0x00,0x00,0x01]
+#CHECK: tbegin	0, 32767                # encoding: [0xe5,0x60,0x00,0x00,0x7f,0xff]
+#CHECK: tbegin	0, 32768                # encoding: [0xe5,0x60,0x00,0x00,0x80,0x00]
+#CHECK: tbegin	0, 65535                # encoding: [0xe5,0x60,0x00,0x00,0xff,0xff]
+#CHECK: tbegin	0(%r1), 42              # encoding: [0xe5,0x60,0x10,0x00,0x00,0x2a]
+#CHECK: tbegin	0(%r15), 42             # encoding: [0xe5,0x60,0xf0,0x00,0x00,0x2a]
+#CHECK: tbegin	4095(%r1), 42           # encoding: [0xe5,0x60,0x1f,0xff,0x00,0x2a]
+#CHECK: tbegin	4095(%r15), 42          # encoding: [0xe5,0x60,0xff,0xff,0x00,0x2a]
+
+	tbegin	0, 0
+	tbegin	4095, 0
+	tbegin	0, 0
+	tbegin	0, 1
+	tbegin	0, 32767
+	tbegin	0, 32768
+	tbegin	0, 65535
+	tbegin	0(%r1), 42
+	tbegin	0(%r15), 42
+	tbegin	4095(%r1), 42
+	tbegin	4095(%r15), 42
+
+#CHECK: tbeginc	0, 0                    # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00]
+#CHECK: tbeginc	4095, 0                 # encoding: [0xe5,0x61,0x0f,0xff,0x00,0x00]
+#CHECK: tbeginc	0, 0                    # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00]
+#CHECK: tbeginc	0, 1                    # encoding: [0xe5,0x61,0x00,0x00,0x00,0x01]
+#CHECK: tbeginc	0, 32767                # encoding: [0xe5,0x61,0x00,0x00,0x7f,0xff]
+#CHECK: tbeginc	0, 32768                # encoding: [0xe5,0x61,0x00,0x00,0x80,0x00]
+#CHECK: tbeginc	0, 65535                # encoding: [0xe5,0x61,0x00,0x00,0xff,0xff]
+#CHECK: tbeginc	0(%r1), 42              # encoding: [0xe5,0x61,0x10,0x00,0x00,0x2a]
+#CHECK: tbeginc	0(%r15), 42             # encoding: [0xe5,0x61,0xf0,0x00,0x00,0x2a]
+#CHECK: tbeginc	4095(%r1), 42           # encoding: [0xe5,0x61,0x1f,0xff,0x00,0x2a]
+#CHECK: tbeginc	4095(%r15), 42          # encoding: [0xe5,0x61,0xff,0xff,0x00,0x2a]
+
+	tbeginc	0, 0
+	tbeginc	4095, 0
+	tbeginc	0, 0
+	tbeginc	0, 1
+	tbeginc	0, 32767
+	tbeginc	0, 32768
+	tbeginc	0, 65535
+	tbeginc	0(%r1), 42
+	tbeginc	0(%r15), 42
+	tbeginc	4095(%r1), 42
+	tbeginc	4095(%r15), 42
+
+#CHECK: tend                            # encoding: [0xb2,0xf8,0x00,0x00]
+
+	tend
diff --git a/test/MC/SystemZ/tokens.s b/test/MC/SystemZ/tokens.s
index 2719752b7366..ceadcdb4b1d4 100644
--- a/test/MC/SystemZ/tokens.s
+++ b/test/MC/SystemZ/tokens.s
@@ -13,10 +13,16 @@
 #CHECK: foo	100(200,%r0), 300
 #CHECK: error: invalid instruction
 #CHECK: foo	100(200,%r1), 300
-#CHECK: error: invalid operand
+#CHECK: error: invalid address register
 #CHECK: foo	100(%a0), 200
 #CHECK: error: %r0 used in an address
 #CHECK: foo	100(%r0), 200
+#CHECK: error: %r0 used in an address
+#CHECK: foo	100(%v1,%r0), 200
+#CHECK: error: invalid instruction
+#CHECK: foo	100(%v0,%r1), 200
+#CHECK: error: invalid instruction
+#CHECK: foo	100(%v31), 200
 #CHECK: error: invalid operand
 #CHECK: foo	100(%r1,%a0), 200
 #CHECK: error: %r0 used in an address
@@ -45,6 +51,12 @@
 #CHECK: foo	%a15, 200
 #CHECK: error: invalid register
 #CHECK: foo	%a16, 200
+#CHECK: error: invalid instruction
+#CHECK: foo	%v0, 200
+#CHECK: error: invalid instruction
+#CHECK: foo	%v31, 200
+#CHECK: error: invalid register
+#CHECK: foo	%v32, 200
 #CHECK: error: invalid register
 #CHECK: foo	%c, 200
 #CHECK: error: invalid register
@@ -60,6 +72,9 @@
 	foo	100(200,%r1), 300
 	foo	100(%a0), 200
 	foo	100(%r0), 200
+	foo	100(%v1,%r0), 200
+	foo	100(%v0,%r1), 200
+	foo	100(%v31), 200
 	foo	100(%r1,%a0), 200
 	foo	100(%r1,%r0), 200
 	foo	100(%r1,%r2, 200
@@ -74,6 +89,9 @@
 	foo	%a0, 200
 	foo	%a15, 200
 	foo	%a16, 200
+	foo	%v0, 200
+	foo	%v31, 200
+	foo	%v32, 200
 	foo	%c, 200
 	foo	%, 200
 	foo	{, 200
diff --git a/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s b/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s
index a9a78a79569f..5ce788098f36 100644
--- a/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s
+++ b/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s
@@ -1,4 +1,5 @@
 # RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
+# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - 2>&1 | FileCheck %s
 
 # CHECK: ERROR: Fragment can't be larger than a bundle size
 
diff --git a/test/MC/X86/AlignedBundling/different-sections.s b/test/MC/X86/AlignedBundling/different-sections.s
index 3e9fcf376d2d..e12153210042 100644
--- a/test/MC/X86/AlignedBundling/different-sections.s
+++ b/test/MC/X86/AlignedBundling/different-sections.s
@@ -1,5 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
 
 # Test two different executable sections with bundling.
 
diff --git a/test/MC/X86/AlignedBundling/labeloffset.s b/test/MC/X86/AlignedBundling/labeloffset.s
index 65a008651f19..5b2efe079650 100644
--- a/test/MC/X86/AlignedBundling/labeloffset.s
+++ b/test/MC/X86/AlignedBundling/labeloffset.s
@@ -2,6 +2,8 @@
 # RUN: llvm-objdump -disassemble -no-show-raw-insn -r - | FileCheck %s
 # RUN: llvm-mc -triple=i686-nacl -filetype=obj %s -o - | \
 # RUN: llvm-objdump -disassemble -no-show-raw-insn -r - | FileCheck %s
+# RUN: llvm-mc -triple=i686-nacl -filetype=obj -mc-relax-all %s -o - | \
+# RUN: llvm-objdump -disassemble -no-show-raw-insn -r - | FileCheck %s
 
         .bundle_align_mode 5
         .text
diff --git a/test/MC/X86/AlignedBundling/long-nop-pad.s b/test/MC/X86/AlignedBundling/long-nop-pad.s
index 9b1ec1184b05..36e4f4b553fb 100644
--- a/test/MC/X86/AlignedBundling/long-nop-pad.s
+++ b/test/MC/X86/AlignedBundling/long-nop-pad.s
@@ -1,5 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
 
 # Test that long nops are generated for padding where possible.
 
diff --git a/test/MC/X86/AlignedBundling/nesting.s b/test/MC/X86/AlignedBundling/nesting.s
index 8996170a1d19..74b8fe9ff49b 100644
--- a/test/MC/X86/AlignedBundling/nesting.s
+++ b/test/MC/X86/AlignedBundling/nesting.s
@@ -1,5 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
 
 # Will be bundle-aligning to 16 byte boundaries
   .bundle_align_mode 4
diff --git a/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s b/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s
index 6ca4046f0c7b..158cde8cd450 100644
--- a/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s
+++ b/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s
@@ -1,5 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
 
 # Test some variations of padding to the end of a bundle.
 
diff --git a/test/MC/X86/AlignedBundling/pad-bundle-groups.s b/test/MC/X86/AlignedBundling/pad-bundle-groups.s
index b65ee7a5cc74..7a9e30c053ec 100644
--- a/test/MC/X86/AlignedBundling/pad-bundle-groups.s
+++ b/test/MC/X86/AlignedBundling/pad-bundle-groups.s
@@ -1,5 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
 
 # Test some variations of padding for bundle-locked groups.
 
diff --git a/test/MC/X86/AlignedBundling/relax-at-bundle-end.s b/test/MC/X86/AlignedBundling/relax-at-bundle-end.s
index ab4affbbeac8..f59ecb08a3d1 100644
--- a/test/MC/X86/AlignedBundling/relax-at-bundle-end.s
+++ b/test/MC/X86/AlignedBundling/relax-at-bundle-end.s
@@ -1,5 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
 
 # Test that an instruction near a bundle end gets properly padded
 # after it is relaxed.
diff --git a/test/MC/X86/AlignedBundling/relax-in-bundle-group.s b/test/MC/X86/AlignedBundling/relax-in-bundle-group.s
index 0a99bb5ce563..d07619063f00 100644
--- a/test/MC/X86/AlignedBundling/relax-in-bundle-group.s
+++ b/test/MC/X86/AlignedBundling/relax-in-bundle-group.s
@@ -1,5 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
 # RUN:   | llvm-objdump -disassemble - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN:   | llvm-objdump -disassemble - | FileCheck %s
 
 # Test that instructions inside bundle-locked groups are relaxed even if their
 # fixup is short enough not to warrant relaxation on its own.
diff --git a/test/MC/X86/AlignedBundling/section-alignment.s b/test/MC/X86/AlignedBundling/section-alignment.s
new file mode 100644
index 000000000000..9ee5f6776c1e
--- /dev/null
+++ b/test/MC/X86/AlignedBundling/section-alignment.s
@@ -0,0 +1,23 @@
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
+# RUN:   | llvm-readobj -sections | FileCheck %s
+
+# Test that bundle-aligned sections with instructions are aligned
+
+  .bundle_align_mode 5
+# CHECK: Sections
+# Check that the empty .text section has the default alignment
+# CHECK-LABEL: Name: .text
+# CHECK-NOT: Name
+# CHECK: AddressAlignment: 4
+
+  .section text1, "x"
+  imull $17, %ebx, %ebp
+# CHECK-LABEL: Name: text1
+# CHECK-NOT: Name
+# CHECK: AddressAlignment: 32
+
+  .section text2, "x"
+  imull $17, %ebx, %ebp
+# CHECK-LABEL: Name: text2
+# CHECK-NOT: Name
+# CHECK: AddressAlignment: 32
diff --git a/test/MC/X86/AlignedBundling/single-inst-bundling.s b/test/MC/X86/AlignedBundling/single-inst-bundling.s
index c0275f4d1ecb..a7df2c96a8eb 100644
--- a/test/MC/X86/AlignedBundling/single-inst-bundling.s
+++ b/test/MC/X86/AlignedBundling/single-inst-bundling.s
@@ -1,5 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck -check-prefix=CHECK -check-prefix=CHECK-OPT %s
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck -check-prefix=CHECK -check-prefix=CHECK-RELAX %s
 
 # Test simple NOP insertion for single instructions.
 
@@ -24,14 +26,17 @@ foo:
   movl    %ebx, %edi
   callq   bar
   cmpl    %r14d, %ebp
+# CHECK-RELAX:   nopl
   jle     .L_ELSE
 # Due to the padding that's inserted before the addl, the jump target
 # becomes farther by one byte.
-# CHECK:         jle 5
+# CHECK-OPT:     jle 5
+# CHECK-RELAX:   jle 7
 
   addl    %ebp, %eax
-# CHECK:          nop
-# CHECK-NEXT:     20: addl
+# CHECK-OPT:     nop
+# CHECK-OPT-NEXT:20: addl
+# CHECK-RELAX:   26: addl
 
   jmp     .L_RET
 .L_ELSE:
diff --git a/test/MC/X86/avx512-encodings.s b/test/MC/X86/avx512-encodings.s
index 4f4dc702bea9..cb71a00381b1 100644
--- a/test/MC/X86/avx512-encodings.s
+++ b/test/MC/X86/avx512-encodings.s
@@ -1,5 +1,4 @@
-// RUN: not llvm-mc -triple x86_64-unknown-unknown -mcpu=knl --show-encoding %s 2> %t.err | FileCheck %s
-// RUN: FileCheck --check-prefix=ERR < %t.err %s
+// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=knl --show-encoding < %s  | FileCheck %s
 
 // CHECK: vaddpd %zmm6, %zmm27, %zmm8
 // CHECK:  encoding: [0x62,0x71,0xa5,0x40,0x58,0xc6]
@@ -1605,6 +1604,266 @@
 // CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0xaa,0xfc,0xfd,0xff,0xff,0x7b]
           vpcmpd $123, -516(%rdx){1to16}, %zmm25, %k5
 
+// CHECK: vpcmpltd %zmm7, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0xd7,0x01]
+          vpcmpltd %zmm7, %zmm25, %k2
+
+// CHECK: vpcmpltd %zmm7, %zmm25, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x35,0x41,0x1f,0xd7,0x01]
+          vpcmpltd %zmm7, %zmm25, %k2 {%k1}
+
+// CHECK: vpcmpltd (%rcx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x11,0x01]
+          vpcmpltd (%rcx), %zmm25, %k2
+
+// CHECK: vpcmpltd 291(%rax,%r14,8), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xb3,0x35,0x40,0x1f,0x94,0xf0,0x23,0x01,0x00,0x00,0x01]
+          vpcmpltd 291(%rax,%r14,8), %zmm25, %k2
+
+// CHECK: vpcmpltd (%rcx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x11,0x01]
+          vpcmpltd (%rcx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpltd 8128(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x52,0x7f,0x01]
+          vpcmpltd 8128(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpltd 8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x92,0x00,0x20,0x00,0x00,0x01]
+          vpcmpltd 8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpltd -8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x52,0x80,0x01]
+          vpcmpltd -8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpltd -8256(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x92,0xc0,0xdf,0xff,0xff,0x01]
+          vpcmpltd -8256(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpltd 508(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x52,0x7f,0x01]
+          vpcmpltd 508(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpltd 512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x92,0x00,0x02,0x00,0x00,0x01]
+          vpcmpltd 512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpltd -512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x52,0x80,0x01]
+          vpcmpltd -512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpltd -516(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x92,0xfc,0xfd,0xff,0xff,0x01]
+          vpcmpltd -516(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpled %zmm7, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0xd7,0x02]
+          vpcmpled %zmm7, %zmm25, %k2
+
+// CHECK: vpcmpled %zmm7, %zmm25, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x35,0x41,0x1f,0xd7,0x02]
+          vpcmpled %zmm7, %zmm25, %k2 {%k1}
+
+// CHECK: vpcmpled (%rcx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x11,0x02]
+          vpcmpled (%rcx), %zmm25, %k2
+
+// CHECK: vpcmpled 291(%rax,%r14,8), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xb3,0x35,0x40,0x1f,0x94,0xf0,0x23,0x01,0x00,0x00,0x02]
+          vpcmpled 291(%rax,%r14,8), %zmm25, %k2
+
+// CHECK: vpcmpled (%rcx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x11,0x02]
+          vpcmpled (%rcx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpled 8128(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x52,0x7f,0x02]
+          vpcmpled 8128(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpled 8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x92,0x00,0x20,0x00,0x00,0x02]
+          vpcmpled 8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpled -8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x52,0x80,0x02]
+          vpcmpled -8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpled -8256(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x92,0xc0,0xdf,0xff,0xff,0x02]
+          vpcmpled -8256(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpled 508(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x52,0x7f,0x02]
+          vpcmpled 508(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpled 512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x92,0x00,0x02,0x00,0x00,0x02]
+          vpcmpled 512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpled -512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x52,0x80,0x02]
+          vpcmpled -512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpled -516(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x92,0xfc,0xfd,0xff,0xff,0x02]
+          vpcmpled -516(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpneqd %zmm7, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0xd7,0x04]
+          vpcmpneqd %zmm7, %zmm25, %k2
+
+// CHECK: vpcmpneqd %zmm7, %zmm25, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x35,0x41,0x1f,0xd7,0x04]
+          vpcmpneqd %zmm7, %zmm25, %k2 {%k1}
+
+// CHECK: vpcmpneqd (%rcx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x11,0x04]
+          vpcmpneqd (%rcx), %zmm25, %k2
+
+// CHECK: vpcmpneqd 291(%rax,%r14,8), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xb3,0x35,0x40,0x1f,0x94,0xf0,0x23,0x01,0x00,0x00,0x04]
+          vpcmpneqd 291(%rax,%r14,8), %zmm25, %k2
+
+// CHECK: vpcmpneqd (%rcx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x11,0x04]
+          vpcmpneqd (%rcx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpneqd 8128(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x52,0x7f,0x04]
+          vpcmpneqd 8128(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpneqd 8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x92,0x00,0x20,0x00,0x00,0x04]
+          vpcmpneqd 8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpneqd -8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x52,0x80,0x04]
+          vpcmpneqd -8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpneqd -8256(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x92,0xc0,0xdf,0xff,0xff,0x04]
+          vpcmpneqd -8256(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpneqd 508(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x52,0x7f,0x04]
+          vpcmpneqd 508(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpneqd 512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x92,0x00,0x02,0x00,0x00,0x04]
+          vpcmpneqd 512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpneqd -512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x52,0x80,0x04]
+          vpcmpneqd -512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpneqd -516(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x92,0xfc,0xfd,0xff,0xff,0x04]
+          vpcmpneqd -516(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnltd %zmm7, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0xd7,0x05]
+          vpcmpnltd %zmm7, %zmm25, %k2
+
+// CHECK: vpcmpnltd %zmm7, %zmm25, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x35,0x41,0x1f,0xd7,0x05]
+          vpcmpnltd %zmm7, %zmm25, %k2 {%k1}
+
+// CHECK: vpcmpnltd (%rcx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x11,0x05]
+          vpcmpnltd (%rcx), %zmm25, %k2
+
+// CHECK: vpcmpnltd 291(%rax,%r14,8), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xb3,0x35,0x40,0x1f,0x94,0xf0,0x23,0x01,0x00,0x00,0x05]
+          vpcmpnltd 291(%rax,%r14,8), %zmm25, %k2
+
+// CHECK: vpcmpnltd (%rcx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x11,0x05]
+          vpcmpnltd (%rcx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnltd 8128(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x52,0x7f,0x05]
+          vpcmpnltd 8128(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnltd 8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x92,0x00,0x20,0x00,0x00,0x05]
+          vpcmpnltd 8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnltd -8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x52,0x80,0x05]
+          vpcmpnltd -8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnltd -8256(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x92,0xc0,0xdf,0xff,0xff,0x05]
+          vpcmpnltd -8256(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnltd 508(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x52,0x7f,0x05]
+          vpcmpnltd 508(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnltd 512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x92,0x00,0x02,0x00,0x00,0x05]
+          vpcmpnltd 512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnltd -512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x52,0x80,0x05]
+          vpcmpnltd -512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnltd -516(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x92,0xfc,0xfd,0xff,0xff,0x05]
+          vpcmpnltd -516(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnled %zmm7, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0xd7,0x06]
+          vpcmpnled %zmm7, %zmm25, %k2
+
+// CHECK: vpcmpnled %zmm7, %zmm25, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x35,0x41,0x1f,0xd7,0x06]
+          vpcmpnled %zmm7, %zmm25, %k2 {%k1}
+
+// CHECK: vpcmpnled (%rcx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x11,0x06]
+          vpcmpnled (%rcx), %zmm25, %k2
+
+// CHECK: vpcmpnled 291(%rax,%r14,8), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xb3,0x35,0x40,0x1f,0x94,0xf0,0x23,0x01,0x00,0x00,0x06]
+          vpcmpnled 291(%rax,%r14,8), %zmm25, %k2
+
+// CHECK: vpcmpnled (%rcx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x11,0x06]
+          vpcmpnled (%rcx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnled 8128(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x52,0x7f,0x06]
+          vpcmpnled 8128(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnled 8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x92,0x00,0x20,0x00,0x00,0x06]
+          vpcmpnled 8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnled -8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x52,0x80,0x06]
+          vpcmpnled -8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnled -8256(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1f,0x92,0xc0,0xdf,0xff,0xff,0x06]
+          vpcmpnled -8256(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnled 508(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x52,0x7f,0x06]
+          vpcmpnled 508(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnled 512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x92,0x00,0x02,0x00,0x00,0x06]
+          vpcmpnled 512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnled -512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x52,0x80,0x06]
+          vpcmpnled -512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnled -516(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1f,0x92,0xfc,0xfd,0xff,0xff,0x06]
+          vpcmpnled -516(%rdx){1to16}, %zmm25, %k2
+
 // CHECK: vpcmpeqd %zmm10, %zmm2, %k5
 // CHECK:  encoding: [0x62,0xd1,0x6d,0x48,0x76,0xea]
           vpcmpeqd %zmm10, %zmm2, %k5
@@ -1869,6 +2128,266 @@
 // CHECK:  encoding: [0x62,0xf3,0x9d,0x50,0x1f,0xaa,0xf8,0xfb,0xff,0xff,0x7b]
           vpcmpq $123, -1032(%rdx){1to8}, %zmm28, %k5
 
+// CHECK: vpcmpltq %zmm7, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0xd7,0x01]
+          vpcmpltq %zmm7, %zmm14, %k2
+
+// CHECK: vpcmpltq %zmm7, %zmm14, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x49,0x1f,0xd7,0x01]
+          vpcmpltq %zmm7, %zmm14, %k2 {%k1}
+
+// CHECK: vpcmpltq (%rcx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x11,0x01]
+          vpcmpltq (%rcx), %zmm14, %k2
+
+// CHECK: vpcmpltq 291(%rax,%r14,8), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xb3,0x8d,0x48,0x1f,0x94,0xf0,0x23,0x01,0x00,0x00,0x01]
+          vpcmpltq 291(%rax,%r14,8), %zmm14, %k2
+
+// CHECK: vpcmpltq (%rcx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x11,0x01]
+          vpcmpltq (%rcx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpltq 8128(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x52,0x7f,0x01]
+          vpcmpltq 8128(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpltq 8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x92,0x00,0x20,0x00,0x00,0x01]
+          vpcmpltq 8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpltq -8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x52,0x80,0x01]
+          vpcmpltq -8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpltq -8256(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x92,0xc0,0xdf,0xff,0xff,0x01]
+          vpcmpltq -8256(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpltq 1016(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x52,0x7f,0x01]
+          vpcmpltq 1016(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpltq 1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x92,0x00,0x04,0x00,0x00,0x01]
+          vpcmpltq 1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpltq -1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x52,0x80,0x01]
+          vpcmpltq -1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpltq -1032(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x92,0xf8,0xfb,0xff,0xff,0x01]
+          vpcmpltq -1032(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpleq %zmm7, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0xd7,0x02]
+          vpcmpleq %zmm7, %zmm14, %k2
+
+// CHECK: vpcmpleq %zmm7, %zmm14, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x49,0x1f,0xd7,0x02]
+          vpcmpleq %zmm7, %zmm14, %k2 {%k1}
+
+// CHECK: vpcmpleq (%rcx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x11,0x02]
+          vpcmpleq (%rcx), %zmm14, %k2
+
+// CHECK: vpcmpleq 291(%rax,%r14,8), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xb3,0x8d,0x48,0x1f,0x94,0xf0,0x23,0x01,0x00,0x00,0x02]
+          vpcmpleq 291(%rax,%r14,8), %zmm14, %k2
+
+// CHECK: vpcmpleq (%rcx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x11,0x02]
+          vpcmpleq (%rcx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpleq 8128(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x52,0x7f,0x02]
+          vpcmpleq 8128(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpleq 8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x92,0x00,0x20,0x00,0x00,0x02]
+          vpcmpleq 8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpleq -8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x52,0x80,0x02]
+          vpcmpleq -8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpleq -8256(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x92,0xc0,0xdf,0xff,0xff,0x02]
+          vpcmpleq -8256(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpleq 1016(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x52,0x7f,0x02]
+          vpcmpleq 1016(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpleq 1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x92,0x00,0x04,0x00,0x00,0x02]
+          vpcmpleq 1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpleq -1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x52,0x80,0x02]
+          vpcmpleq -1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpleq -1032(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x92,0xf8,0xfb,0xff,0xff,0x02]
+          vpcmpleq -1032(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpneqq %zmm7, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0xd7,0x04]
+          vpcmpneqq %zmm7, %zmm14, %k2
+
+// CHECK: vpcmpneqq %zmm7, %zmm14, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x49,0x1f,0xd7,0x04]
+          vpcmpneqq %zmm7, %zmm14, %k2 {%k1}
+
+// CHECK: vpcmpneqq (%rcx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x11,0x04]
+          vpcmpneqq (%rcx), %zmm14, %k2
+
+// CHECK: vpcmpneqq 291(%rax,%r14,8), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xb3,0x8d,0x48,0x1f,0x94,0xf0,0x23,0x01,0x00,0x00,0x04]
+          vpcmpneqq 291(%rax,%r14,8), %zmm14, %k2
+
+// CHECK: vpcmpneqq (%rcx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x11,0x04]
+          vpcmpneqq (%rcx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpneqq 8128(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x52,0x7f,0x04]
+          vpcmpneqq 8128(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpneqq 8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x92,0x00,0x20,0x00,0x00,0x04]
+          vpcmpneqq 8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpneqq -8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x52,0x80,0x04]
+          vpcmpneqq -8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpneqq -8256(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x92,0xc0,0xdf,0xff,0xff,0x04]
+          vpcmpneqq -8256(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpneqq 1016(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x52,0x7f,0x04]
+          vpcmpneqq 1016(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpneqq 1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x92,0x00,0x04,0x00,0x00,0x04]
+          vpcmpneqq 1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpneqq -1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x52,0x80,0x04]
+          vpcmpneqq -1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpneqq -1032(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x92,0xf8,0xfb,0xff,0xff,0x04]
+          vpcmpneqq -1032(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnltq %zmm7, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0xd7,0x05]
+          vpcmpnltq %zmm7, %zmm14, %k2
+
+// CHECK: vpcmpnltq %zmm7, %zmm14, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x49,0x1f,0xd7,0x05]
+          vpcmpnltq %zmm7, %zmm14, %k2 {%k1}
+
+// CHECK: vpcmpnltq (%rcx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x11,0x05]
+          vpcmpnltq (%rcx), %zmm14, %k2
+
+// CHECK: vpcmpnltq 291(%rax,%r14,8), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xb3,0x8d,0x48,0x1f,0x94,0xf0,0x23,0x01,0x00,0x00,0x05]
+          vpcmpnltq 291(%rax,%r14,8), %zmm14, %k2
+
+// CHECK: vpcmpnltq (%rcx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x11,0x05]
+          vpcmpnltq (%rcx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnltq 8128(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x52,0x7f,0x05]
+          vpcmpnltq 8128(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnltq 8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x92,0x00,0x20,0x00,0x00,0x05]
+          vpcmpnltq 8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnltq -8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x52,0x80,0x05]
+          vpcmpnltq -8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnltq -8256(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x92,0xc0,0xdf,0xff,0xff,0x05]
+          vpcmpnltq -8256(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnltq 1016(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x52,0x7f,0x05]
+          vpcmpnltq 1016(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnltq 1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x92,0x00,0x04,0x00,0x00,0x05]
+          vpcmpnltq 1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnltq -1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x52,0x80,0x05]
+          vpcmpnltq -1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnltq -1032(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x92,0xf8,0xfb,0xff,0xff,0x05]
+          vpcmpnltq -1032(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnleq %zmm7, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0xd7,0x06]
+          vpcmpnleq %zmm7, %zmm14, %k2
+
+// CHECK: vpcmpnleq %zmm7, %zmm14, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x49,0x1f,0xd7,0x06]
+          vpcmpnleq %zmm7, %zmm14, %k2 {%k1}
+
+// CHECK: vpcmpnleq (%rcx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x11,0x06]
+          vpcmpnleq (%rcx), %zmm14, %k2
+
+// CHECK: vpcmpnleq 291(%rax,%r14,8), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xb3,0x8d,0x48,0x1f,0x94,0xf0,0x23,0x01,0x00,0x00,0x06]
+          vpcmpnleq 291(%rax,%r14,8), %zmm14, %k2
+
+// CHECK: vpcmpnleq (%rcx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x11,0x06]
+          vpcmpnleq (%rcx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnleq 8128(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x52,0x7f,0x06]
+          vpcmpnleq 8128(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnleq 8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x92,0x00,0x20,0x00,0x00,0x06]
+          vpcmpnleq 8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnleq -8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x52,0x80,0x06]
+          vpcmpnleq -8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnleq -8256(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1f,0x92,0xc0,0xdf,0xff,0xff,0x06]
+          vpcmpnleq -8256(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnleq 1016(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x52,0x7f,0x06]
+          vpcmpnleq 1016(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnleq 1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x92,0x00,0x04,0x00,0x00,0x06]
+          vpcmpnleq 1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnleq -1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x52,0x80,0x06]
+          vpcmpnleq -1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnleq -1032(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1f,0x92,0xf8,0xfb,0xff,0xff,0x06]
+          vpcmpnleq -1032(%rdx){1to8}, %zmm14, %k2
+
 // CHECK: vpcmpud $171, %zmm7, %zmm25, %k2
 // CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0xd7,0xab]
           vpcmpud $171, %zmm7, %zmm25, %k2
@@ -1925,6 +2444,318 @@
 // CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x92,0xfc,0xfd,0xff,0xff,0x7b]
           vpcmpud $123, -516(%rdx){1to16}, %zmm25, %k2
 
+// CHECK: vpcmpequd %zmm7, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0xd7,0x00]
+          vpcmpequd %zmm7, %zmm25, %k2
+
+// CHECK: vpcmpequd %zmm7, %zmm25, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x35,0x41,0x1e,0xd7,0x00]
+          vpcmpequd %zmm7, %zmm25, %k2 {%k1}
+
+// CHECK: vpcmpequd (%rcx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x11,0x00]
+          vpcmpequd (%rcx), %zmm25, %k2
+
+// CHECK: vpcmpequd 291(%rax,%r14,8), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xb3,0x35,0x40,0x1e,0x94,0xf0,0x23,0x01,0x00,0x00,0x00]
+          vpcmpequd 291(%rax,%r14,8), %zmm25, %k2
+
+// CHECK: vpcmpequd (%rcx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x11,0x00]
+          vpcmpequd (%rcx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpequd 8128(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x52,0x7f,0x00]
+          vpcmpequd 8128(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpequd 8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x92,0x00,0x20,0x00,0x00,0x00]
+          vpcmpequd 8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpequd -8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x52,0x80,0x00]
+          vpcmpequd -8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpequd -8256(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x92,0xc0,0xdf,0xff,0xff,0x00]
+          vpcmpequd -8256(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpequd 508(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x52,0x7f,0x00]
+          vpcmpequd 508(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpequd 512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x92,0x00,0x02,0x00,0x00,0x00]
+          vpcmpequd 512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpequd -512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x52,0x80,0x00]
+          vpcmpequd -512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpequd -516(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x92,0xfc,0xfd,0xff,0xff,0x00]
+          vpcmpequd -516(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpltud %zmm7, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0xd7,0x01]
+          vpcmpltud %zmm7, %zmm25, %k2
+
+// CHECK: vpcmpltud %zmm7, %zmm25, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x35,0x41,0x1e,0xd7,0x01]
+          vpcmpltud %zmm7, %zmm25, %k2 {%k1}
+
+// CHECK: vpcmpltud (%rcx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x11,0x01]
+          vpcmpltud (%rcx), %zmm25, %k2
+
+// CHECK: vpcmpltud 291(%rax,%r14,8), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xb3,0x35,0x40,0x1e,0x94,0xf0,0x23,0x01,0x00,0x00,0x01]
+          vpcmpltud 291(%rax,%r14,8), %zmm25, %k2
+
+// CHECK: vpcmpltud (%rcx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x11,0x01]
+          vpcmpltud (%rcx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpltud 8128(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x52,0x7f,0x01]
+          vpcmpltud 8128(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpltud 8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x92,0x00,0x20,0x00,0x00,0x01]
+          vpcmpltud 8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpltud -8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x52,0x80,0x01]
+          vpcmpltud -8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpltud -8256(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x92,0xc0,0xdf,0xff,0xff,0x01]
+          vpcmpltud -8256(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpltud 508(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x52,0x7f,0x01]
+          vpcmpltud 508(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpltud 512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x92,0x00,0x02,0x00,0x00,0x01]
+          vpcmpltud 512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpltud -512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x52,0x80,0x01]
+          vpcmpltud -512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpltud -516(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x92,0xfc,0xfd,0xff,0xff,0x01]
+          vpcmpltud -516(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpleud %zmm7, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0xd7,0x02]
+          vpcmpleud %zmm7, %zmm25, %k2
+
+// CHECK: vpcmpleud %zmm7, %zmm25, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x35,0x41,0x1e,0xd7,0x02]
+          vpcmpleud %zmm7, %zmm25, %k2 {%k1}
+
+// CHECK: vpcmpleud (%rcx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x11,0x02]
+          vpcmpleud (%rcx), %zmm25, %k2
+
+// CHECK: vpcmpleud 291(%rax,%r14,8), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xb3,0x35,0x40,0x1e,0x94,0xf0,0x23,0x01,0x00,0x00,0x02]
+          vpcmpleud 291(%rax,%r14,8), %zmm25, %k2
+
+// CHECK: vpcmpleud (%rcx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x11,0x02]
+          vpcmpleud (%rcx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpleud 8128(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x52,0x7f,0x02]
+          vpcmpleud 8128(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpleud 8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x92,0x00,0x20,0x00,0x00,0x02]
+          vpcmpleud 8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpleud -8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x52,0x80,0x02]
+          vpcmpleud -8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpleud -8256(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x92,0xc0,0xdf,0xff,0xff,0x02]
+          vpcmpleud -8256(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpleud 508(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x52,0x7f,0x02]
+          vpcmpleud 508(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpleud 512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x92,0x00,0x02,0x00,0x00,0x02]
+          vpcmpleud 512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpleud -512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x52,0x80,0x02]
+          vpcmpleud -512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpleud -516(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x92,0xfc,0xfd,0xff,0xff,0x02]
+          vpcmpleud -516(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnequd %zmm7, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0xd7,0x04]
+          vpcmpnequd %zmm7, %zmm25, %k2
+
+// CHECK: vpcmpnequd %zmm7, %zmm25, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x35,0x41,0x1e,0xd7,0x04]
+          vpcmpnequd %zmm7, %zmm25, %k2 {%k1}
+
+// CHECK: vpcmpnequd (%rcx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x11,0x04]
+          vpcmpnequd (%rcx), %zmm25, %k2
+
+// CHECK: vpcmpnequd 291(%rax,%r14,8), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xb3,0x35,0x40,0x1e,0x94,0xf0,0x23,0x01,0x00,0x00,0x04]
+          vpcmpnequd 291(%rax,%r14,8), %zmm25, %k2
+
+// CHECK: vpcmpnequd (%rcx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x11,0x04]
+          vpcmpnequd (%rcx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnequd 8128(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x52,0x7f,0x04]
+          vpcmpnequd 8128(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnequd 8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x92,0x00,0x20,0x00,0x00,0x04]
+          vpcmpnequd 8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnequd -8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x52,0x80,0x04]
+          vpcmpnequd -8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnequd -8256(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x92,0xc0,0xdf,0xff,0xff,0x04]
+          vpcmpnequd -8256(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnequd 508(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x52,0x7f,0x04]
+          vpcmpnequd 508(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnequd 512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x92,0x00,0x02,0x00,0x00,0x04]
+          vpcmpnequd 512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnequd -512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x52,0x80,0x04]
+          vpcmpnequd -512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnequd -516(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x92,0xfc,0xfd,0xff,0xff,0x04]
+          vpcmpnequd -516(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnltud %zmm7, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0xd7,0x05]
+          vpcmpnltud %zmm7, %zmm25, %k2
+
+// CHECK: vpcmpnltud %zmm7, %zmm25, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x35,0x41,0x1e,0xd7,0x05]
+          vpcmpnltud %zmm7, %zmm25, %k2 {%k1}
+
+// CHECK: vpcmpnltud (%rcx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x11,0x05]
+          vpcmpnltud (%rcx), %zmm25, %k2
+
+// CHECK: vpcmpnltud 291(%rax,%r14,8), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xb3,0x35,0x40,0x1e,0x94,0xf0,0x23,0x01,0x00,0x00,0x05]
+          vpcmpnltud 291(%rax,%r14,8), %zmm25, %k2
+
+// CHECK: vpcmpnltud (%rcx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x11,0x05]
+          vpcmpnltud (%rcx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnltud 8128(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x52,0x7f,0x05]
+          vpcmpnltud 8128(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnltud 8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x92,0x00,0x20,0x00,0x00,0x05]
+          vpcmpnltud 8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnltud -8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x52,0x80,0x05]
+          vpcmpnltud -8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnltud -8256(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x92,0xc0,0xdf,0xff,0xff,0x05]
+          vpcmpnltud -8256(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnltud 508(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x52,0x7f,0x05]
+          vpcmpnltud 508(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnltud 512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x92,0x00,0x02,0x00,0x00,0x05]
+          vpcmpnltud 512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnltud -512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x52,0x80,0x05]
+          vpcmpnltud -512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnltud -516(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x92,0xfc,0xfd,0xff,0xff,0x05]
+          vpcmpnltud -516(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnleud %zmm7, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0xd7,0x06]
+          vpcmpnleud %zmm7, %zmm25, %k2
+
+// CHECK: vpcmpnleud %zmm7, %zmm25, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x35,0x41,0x1e,0xd7,0x06]
+          vpcmpnleud %zmm7, %zmm25, %k2 {%k1}
+
+// CHECK: vpcmpnleud (%rcx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x11,0x06]
+          vpcmpnleud (%rcx), %zmm25, %k2
+
+// CHECK: vpcmpnleud 291(%rax,%r14,8), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xb3,0x35,0x40,0x1e,0x94,0xf0,0x23,0x01,0x00,0x00,0x06]
+          vpcmpnleud 291(%rax,%r14,8), %zmm25, %k2
+
+// CHECK: vpcmpnleud (%rcx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x11,0x06]
+          vpcmpnleud (%rcx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnleud 8128(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x52,0x7f,0x06]
+          vpcmpnleud 8128(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnleud 8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x92,0x00,0x20,0x00,0x00,0x06]
+          vpcmpnleud 8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnleud -8192(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x52,0x80,0x06]
+          vpcmpnleud -8192(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnleud -8256(%rdx), %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x40,0x1e,0x92,0xc0,0xdf,0xff,0xff,0x06]
+          vpcmpnleud -8256(%rdx), %zmm25, %k2
+
+// CHECK: vpcmpnleud 508(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x52,0x7f,0x06]
+          vpcmpnleud 508(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnleud 512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x92,0x00,0x02,0x00,0x00,0x06]
+          vpcmpnleud 512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnleud -512(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x52,0x80,0x06]
+          vpcmpnleud -512(%rdx){1to16}, %zmm25, %k2
+
+// CHECK: vpcmpnleud -516(%rdx){1to16}, %zmm25, %k2
+// CHECK:  encoding: [0x62,0xf3,0x35,0x50,0x1e,0x92,0xfc,0xfd,0xff,0xff,0x06]
+          vpcmpnleud -516(%rdx){1to16}, %zmm25, %k2
+
 // CHECK: vpcmpuq $171, %zmm8, %zmm14, %k3
 // CHECK:  encoding: [0x62,0xd3,0x8d,0x48,0x1e,0xd8,0xab]
           vpcmpuq $171, %zmm8, %zmm14, %k3
@@ -1981,6 +2812,318 @@
 // CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x9a,0xf8,0xfb,0xff,0xff,0x7b]
           vpcmpuq $123, -1032(%rdx){1to8}, %zmm14, %k3
 
+// CHECK: vpcmpequq %zmm7, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0xd7,0x00]
+          vpcmpequq %zmm7, %zmm14, %k2
+
+// CHECK: vpcmpequq %zmm7, %zmm14, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x49,0x1e,0xd7,0x00]
+          vpcmpequq %zmm7, %zmm14, %k2 {%k1}
+
+// CHECK: vpcmpequq (%rcx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x11,0x00]
+          vpcmpequq (%rcx), %zmm14, %k2
+
+// CHECK: vpcmpequq 291(%rax,%r14,8), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xb3,0x8d,0x48,0x1e,0x94,0xf0,0x23,0x01,0x00,0x00,0x00]
+          vpcmpequq 291(%rax,%r14,8), %zmm14, %k2
+
+// CHECK: vpcmpequq (%rcx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x11,0x00]
+          vpcmpequq (%rcx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpequq 8128(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x52,0x7f,0x00]
+          vpcmpequq 8128(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpequq 8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x92,0x00,0x20,0x00,0x00,0x00]
+          vpcmpequq 8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpequq -8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x52,0x80,0x00]
+          vpcmpequq -8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpequq -8256(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x92,0xc0,0xdf,0xff,0xff,0x00]
+          vpcmpequq -8256(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpequq 1016(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x52,0x7f,0x00]
+          vpcmpequq 1016(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpequq 1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x92,0x00,0x04,0x00,0x00,0x00]
+          vpcmpequq 1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpequq -1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x52,0x80,0x00]
+          vpcmpequq -1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpequq -1032(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x92,0xf8,0xfb,0xff,0xff,0x00]
+          vpcmpequq -1032(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpltuq %zmm7, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0xd7,0x01]
+          vpcmpltuq %zmm7, %zmm14, %k2
+
+// CHECK: vpcmpltuq %zmm7, %zmm14, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x49,0x1e,0xd7,0x01]
+          vpcmpltuq %zmm7, %zmm14, %k2 {%k1}
+
+// CHECK: vpcmpltuq (%rcx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x11,0x01]
+          vpcmpltuq (%rcx), %zmm14, %k2
+
+// CHECK: vpcmpltuq 291(%rax,%r14,8), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xb3,0x8d,0x48,0x1e,0x94,0xf0,0x23,0x01,0x00,0x00,0x01]
+          vpcmpltuq 291(%rax,%r14,8), %zmm14, %k2
+
+// CHECK: vpcmpltuq (%rcx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x11,0x01]
+          vpcmpltuq (%rcx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpltuq 8128(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x52,0x7f,0x01]
+          vpcmpltuq 8128(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpltuq 8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x92,0x00,0x20,0x00,0x00,0x01]
+          vpcmpltuq 8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpltuq -8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x52,0x80,0x01]
+          vpcmpltuq -8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpltuq -8256(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x92,0xc0,0xdf,0xff,0xff,0x01]
+          vpcmpltuq -8256(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpltuq 1016(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x52,0x7f,0x01]
+          vpcmpltuq 1016(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpltuq 1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x92,0x00,0x04,0x00,0x00,0x01]
+          vpcmpltuq 1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpltuq -1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x52,0x80,0x01]
+          vpcmpltuq -1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpltuq -1032(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x92,0xf8,0xfb,0xff,0xff,0x01]
+          vpcmpltuq -1032(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpleuq %zmm7, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0xd7,0x02]
+          vpcmpleuq %zmm7, %zmm14, %k2
+
+// CHECK: vpcmpleuq %zmm7, %zmm14, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x49,0x1e,0xd7,0x02]
+          vpcmpleuq %zmm7, %zmm14, %k2 {%k1}
+
+// CHECK: vpcmpleuq (%rcx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x11,0x02]
+          vpcmpleuq (%rcx), %zmm14, %k2
+
+// CHECK: vpcmpleuq 291(%rax,%r14,8), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xb3,0x8d,0x48,0x1e,0x94,0xf0,0x23,0x01,0x00,0x00,0x02]
+          vpcmpleuq 291(%rax,%r14,8), %zmm14, %k2
+
+// CHECK: vpcmpleuq (%rcx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x11,0x02]
+          vpcmpleuq (%rcx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpleuq 8128(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x52,0x7f,0x02]
+          vpcmpleuq 8128(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpleuq 8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x92,0x00,0x20,0x00,0x00,0x02]
+          vpcmpleuq 8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpleuq -8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x52,0x80,0x02]
+          vpcmpleuq -8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpleuq -8256(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x92,0xc0,0xdf,0xff,0xff,0x02]
+          vpcmpleuq -8256(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpleuq 1016(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x52,0x7f,0x02]
+          vpcmpleuq 1016(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpleuq 1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x92,0x00,0x04,0x00,0x00,0x02]
+          vpcmpleuq 1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpleuq -1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x52,0x80,0x02]
+          vpcmpleuq -1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpleuq -1032(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x92,0xf8,0xfb,0xff,0xff,0x02]
+          vpcmpleuq -1032(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnequq %zmm7, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0xd7,0x04]
+          vpcmpnequq %zmm7, %zmm14, %k2
+
+// CHECK: vpcmpnequq %zmm7, %zmm14, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x49,0x1e,0xd7,0x04]
+          vpcmpnequq %zmm7, %zmm14, %k2 {%k1}
+
+// CHECK: vpcmpnequq (%rcx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x11,0x04]
+          vpcmpnequq (%rcx), %zmm14, %k2
+
+// CHECK: vpcmpnequq 291(%rax,%r14,8), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xb3,0x8d,0x48,0x1e,0x94,0xf0,0x23,0x01,0x00,0x00,0x04]
+          vpcmpnequq 291(%rax,%r14,8), %zmm14, %k2
+
+// CHECK: vpcmpnequq (%rcx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x11,0x04]
+          vpcmpnequq (%rcx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnequq 8128(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x52,0x7f,0x04]
+          vpcmpnequq 8128(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnequq 8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x92,0x00,0x20,0x00,0x00,0x04]
+          vpcmpnequq 8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnequq -8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x52,0x80,0x04]
+          vpcmpnequq -8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnequq -8256(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x92,0xc0,0xdf,0xff,0xff,0x04]
+          vpcmpnequq -8256(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnequq 1016(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x52,0x7f,0x04]
+          vpcmpnequq 1016(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnequq 1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x92,0x00,0x04,0x00,0x00,0x04]
+          vpcmpnequq 1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnequq -1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x52,0x80,0x04]
+          vpcmpnequq -1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnequq -1032(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x92,0xf8,0xfb,0xff,0xff,0x04]
+          vpcmpnequq -1032(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnltuq %zmm7, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0xd7,0x05]
+          vpcmpnltuq %zmm7, %zmm14, %k2
+
+// CHECK: vpcmpnltuq %zmm7, %zmm14, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x49,0x1e,0xd7,0x05]
+          vpcmpnltuq %zmm7, %zmm14, %k2 {%k1}
+
+// CHECK: vpcmpnltuq (%rcx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x11,0x05]
+          vpcmpnltuq (%rcx), %zmm14, %k2
+
+// CHECK: vpcmpnltuq 291(%rax,%r14,8), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xb3,0x8d,0x48,0x1e,0x94,0xf0,0x23,0x01,0x00,0x00,0x05]
+          vpcmpnltuq 291(%rax,%r14,8), %zmm14, %k2
+
+// CHECK: vpcmpnltuq (%rcx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x11,0x05]
+          vpcmpnltuq (%rcx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnltuq 8128(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x52,0x7f,0x05]
+          vpcmpnltuq 8128(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnltuq 8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x92,0x00,0x20,0x00,0x00,0x05]
+          vpcmpnltuq 8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnltuq -8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x52,0x80,0x05]
+          vpcmpnltuq -8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnltuq -8256(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x92,0xc0,0xdf,0xff,0xff,0x05]
+          vpcmpnltuq -8256(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnltuq 1016(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x52,0x7f,0x05]
+          vpcmpnltuq 1016(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnltuq 1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x92,0x00,0x04,0x00,0x00,0x05]
+          vpcmpnltuq 1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnltuq -1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x52,0x80,0x05]
+          vpcmpnltuq -1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnltuq -1032(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x92,0xf8,0xfb,0xff,0xff,0x05]
+          vpcmpnltuq -1032(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnleuq %zmm7, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0xd7,0x06]
+          vpcmpnleuq %zmm7, %zmm14, %k2
+
+// CHECK: vpcmpnleuq %zmm7, %zmm14, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x49,0x1e,0xd7,0x06]
+          vpcmpnleuq %zmm7, %zmm14, %k2 {%k1}
+
+// CHECK: vpcmpnleuq (%rcx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x11,0x06]
+          vpcmpnleuq (%rcx), %zmm14, %k2
+
+// CHECK: vpcmpnleuq 291(%rax,%r14,8), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xb3,0x8d,0x48,0x1e,0x94,0xf0,0x23,0x01,0x00,0x00,0x06]
+          vpcmpnleuq 291(%rax,%r14,8), %zmm14, %k2
+
+// CHECK: vpcmpnleuq (%rcx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x11,0x06]
+          vpcmpnleuq (%rcx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnleuq 8128(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x52,0x7f,0x06]
+          vpcmpnleuq 8128(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnleuq 8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x92,0x00,0x20,0x00,0x00,0x06]
+          vpcmpnleuq 8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnleuq -8192(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x52,0x80,0x06]
+          vpcmpnleuq -8192(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnleuq -8256(%rdx), %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x48,0x1e,0x92,0xc0,0xdf,0xff,0xff,0x06]
+          vpcmpnleuq -8256(%rdx), %zmm14, %k2
+
+// CHECK: vpcmpnleuq 1016(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x52,0x7f,0x06]
+          vpcmpnleuq 1016(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnleuq 1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x92,0x00,0x04,0x00,0x00,0x06]
+          vpcmpnleuq 1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnleuq -1024(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x52,0x80,0x06]
+          vpcmpnleuq -1024(%rdx){1to8}, %zmm14, %k2
+
+// CHECK: vpcmpnleuq -1032(%rdx){1to8}, %zmm14, %k2
+// CHECK:  encoding: [0x62,0xf3,0x8d,0x58,0x1e,0x92,0xf8,0xfb,0xff,0xff,0x06]
+          vpcmpnleuq -1032(%rdx){1to8}, %zmm14, %k2
+
 // CHECK: vpmaxsd %zmm16, %zmm8, %zmm6
 // CHECK:  encoding: [0x62,0xb2,0x3d,0x48,0x3d,0xf0]
           vpmaxsd %zmm16, %zmm8, %zmm6
@@ -4665,14 +5808,6 @@ vinserti32x4  $1, %xmm21, %zmm5, %zmm17
 // CHECK: encoding: [0x62,0xe3,0x1d,0x40,0x38,0x4f,0x10,0x01]
 vinserti32x4  $1, 256(%rdi), %zmm28, %zmm17
 
-// CHECK: vinserti32x8
-// CHECK: encoding: [0x62,0xd3,0x4d,0x40,0x3a,0xdb,0x01]
-vinserti32x8  $1, %ymm11, %zmm22, %zmm3
-
-// CHECK: vinsertf64x2
-// CHECK: encoding: [0x62,0xf3,0xed,0x48,0x18,0x4f,0x10,0x01]
-vinsertf64x2  $1, 256(%rdi), %zmm2, %zmm1
-
 // CHECK: vextracti32x4
 // CHECK: encoding: [0x62,0x33,0x7d,0x48,0x39,0xc9,0x01]
 vextracti32x4  $1, %zmm9, %xmm17
@@ -4705,13 +5840,129 @@ vpsrad 512(%rdi, %rsi, 4), %zmm12, %zmm25
 // CHECK: encoding: [0x62,0xf2,0x7d,0xc9,0x58,0xc8]
 vpbroadcastd  %xmm0, %zmm1 {%k1} {z}
 
-// CHECK: vbroadcasti32x4 {{.*}} {%k7} {z}
-// CHECK: encoding: [0x67,0x62,0xf2,0x7d,0xcf,0x5a,0x52,0x02]
-vbroadcasti32x4 0x20(%edx), %zmm2 {%k7} {z}
+// CHECK: vbroadcastf32x4 (%rcx), %zmm3
+// CHECK:  encoding: [0x62,0xf2,0x7d,0x48,0x1a,0x19]
+          vbroadcastf32x4 (%rcx), %zmm3
+
+// CHECK: vbroadcastf32x4 (%rcx), %zmm3 {%k7}
+// CHECK:  encoding: [0x62,0xf2,0x7d,0x4f,0x1a,0x19]
+          vbroadcastf32x4 (%rcx), %zmm3 {%k7}
+
+// CHECK: vbroadcastf32x4 (%rcx), %zmm3 {%k7} {z}
+// CHECK:  encoding: [0x62,0xf2,0x7d,0xcf,0x1a,0x19]
+          vbroadcastf32x4 (%rcx), %zmm3 {%k7} {z}
+
+// CHECK: vbroadcastf32x4 291(%rax,%r14,8), %zmm3
+// CHECK:  encoding: [0x62,0xb2,0x7d,0x48,0x1a,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vbroadcastf32x4 291(%rax,%r14,8), %zmm3
+
+// CHECK: vbroadcastf32x4 2032(%rdx), %zmm3
+// CHECK:  encoding: [0x62,0xf2,0x7d,0x48,0x1a,0x5a,0x7f]
+          vbroadcastf32x4 2032(%rdx), %zmm3
+
+// CHECK: vbroadcastf32x4 2048(%rdx), %zmm3
+// CHECK:  encoding: [0x62,0xf2,0x7d,0x48,0x1a,0x9a,0x00,0x08,0x00,0x00]
+          vbroadcastf32x4 2048(%rdx), %zmm3
+
+// CHECK: vbroadcastf32x4 -2048(%rdx), %zmm3
+// CHECK:  encoding: [0x62,0xf2,0x7d,0x48,0x1a,0x5a,0x80]
+          vbroadcastf32x4 -2048(%rdx), %zmm3
+
+// CHECK: vbroadcastf32x4 -2064(%rdx), %zmm3
+// CHECK:  encoding: [0x62,0xf2,0x7d,0x48,0x1a,0x9a,0xf0,0xf7,0xff,0xff]
+          vbroadcastf32x4 -2064(%rdx), %zmm3
+
+// CHECK: vbroadcastf64x4 (%rcx), %zmm25
+// CHECK:  encoding: [0x62,0x62,0xfd,0x48,0x1b,0x09]
+          vbroadcastf64x4 (%rcx), %zmm25
 
-// CHECK: vbroadcasti64x4 {{.*}} %zmm22
-// CHECK: encoding: [0x62,0xe2,0xfd,0x48,0x5b,0x72,0x02]
-vbroadcasti64x4 0x40(%rdx), %zmm22
+// CHECK: vbroadcastf64x4 (%rcx), %zmm25 {%k6}
+// CHECK:  encoding: [0x62,0x62,0xfd,0x4e,0x1b,0x09]
+          vbroadcastf64x4 (%rcx), %zmm25 {%k6}
+
+// CHECK: vbroadcastf64x4 (%rcx), %zmm25 {%k6} {z}
+// CHECK:  encoding: [0x62,0x62,0xfd,0xce,0x1b,0x09]
+          vbroadcastf64x4 (%rcx), %zmm25 {%k6} {z}
+
+// CHECK: vbroadcastf64x4 291(%rax,%r14,8), %zmm25
+// CHECK:  encoding: [0x62,0x22,0xfd,0x48,0x1b,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vbroadcastf64x4 291(%rax,%r14,8), %zmm25
+
+// CHECK: vbroadcastf64x4 4064(%rdx), %zmm25
+// CHECK:  encoding: [0x62,0x62,0xfd,0x48,0x1b,0x4a,0x7f]
+          vbroadcastf64x4 4064(%rdx), %zmm25
+
+// CHECK: vbroadcastf64x4 4096(%rdx), %zmm25
+// CHECK:  encoding: [0x62,0x62,0xfd,0x48,0x1b,0x8a,0x00,0x10,0x00,0x00]
+          vbroadcastf64x4 4096(%rdx), %zmm25
+
+// CHECK: vbroadcastf64x4 -4096(%rdx), %zmm25
+// CHECK:  encoding: [0x62,0x62,0xfd,0x48,0x1b,0x4a,0x80]
+          vbroadcastf64x4 -4096(%rdx), %zmm25
+
+// CHECK: vbroadcastf64x4 -4128(%rdx), %zmm25
+// CHECK:  encoding: [0x62,0x62,0xfd,0x48,0x1b,0x8a,0xe0,0xef,0xff,0xff]
+          vbroadcastf64x4 -4128(%rdx), %zmm25
+
+// CHECK: vbroadcasti32x4 (%rcx), %zmm30
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x5a,0x31]
+          vbroadcasti32x4 (%rcx), %zmm30
+
+// CHECK: vbroadcasti32x4 (%rcx), %zmm30 {%k3}
+// CHECK:  encoding: [0x62,0x62,0x7d,0x4b,0x5a,0x31]
+          vbroadcasti32x4 (%rcx), %zmm30 {%k3}
+
+// CHECK: vbroadcasti32x4 (%rcx), %zmm30 {%k3} {z}
+// CHECK:  encoding: [0x62,0x62,0x7d,0xcb,0x5a,0x31]
+          vbroadcasti32x4 (%rcx), %zmm30 {%k3} {z}
+
+// CHECK: vbroadcasti32x4 291(%rax,%r14,8), %zmm30
+// CHECK:  encoding: [0x62,0x22,0x7d,0x48,0x5a,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vbroadcasti32x4 291(%rax,%r14,8), %zmm30
+
+// CHECK: vbroadcasti32x4 2032(%rdx), %zmm30
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x5a,0x72,0x7f]
+          vbroadcasti32x4 2032(%rdx), %zmm30
+
+// CHECK: vbroadcasti32x4 2048(%rdx), %zmm30
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x5a,0xb2,0x00,0x08,0x00,0x00]
+          vbroadcasti32x4 2048(%rdx), %zmm30
+
+// CHECK: vbroadcasti32x4 -2048(%rdx), %zmm30
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x5a,0x72,0x80]
+          vbroadcasti32x4 -2048(%rdx), %zmm30
+
+// CHECK: vbroadcasti32x4 -2064(%rdx), %zmm30
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x5a,0xb2,0xf0,0xf7,0xff,0xff]
+          vbroadcasti32x4 -2064(%rdx), %zmm30
+
+// CHECK: vbroadcasti64x4 (%rcx), %zmm13
+// CHECK:  encoding: [0x62,0x72,0xfd,0x48,0x5b,0x29]
+          vbroadcasti64x4 (%rcx), %zmm13
+
+// CHECK: vbroadcasti64x4 (%rcx), %zmm13 {%k4}
+// CHECK:  encoding: [0x62,0x72,0xfd,0x4c,0x5b,0x29]
+          vbroadcasti64x4 (%rcx), %zmm13 {%k4}
+
+// CHECK: vbroadcasti64x4 (%rcx), %zmm13 {%k4} {z}
+// CHECK:  encoding: [0x62,0x72,0xfd,0xcc,0x5b,0x29]
+          vbroadcasti64x4 (%rcx), %zmm13 {%k4} {z}
+
+// CHECK: vbroadcasti64x4 291(%rax,%r14,8), %zmm13
+// CHECK:  encoding: [0x62,0x32,0xfd,0x48,0x5b,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vbroadcasti64x4 291(%rax,%r14,8), %zmm13
+
+// CHECK: vbroadcasti64x4 4064(%rdx), %zmm13
+// CHECK:  encoding: [0x62,0x72,0xfd,0x48,0x5b,0x6a,0x7f]
+          vbroadcasti64x4 4064(%rdx), %zmm13
+
+// CHECK: vbroadcasti64x4 4096(%rdx), %zmm13
+// CHECK:  encoding: [0x62,0x72,0xfd,0x48,0x5b,0xaa,0x00,0x10,0x00,0x00]
+          vbroadcasti64x4 4096(%rdx), %zmm13
+
+// CHECK: vbroadcasti64x4 -4096(%rdx), %zmm13
+// CHECK:  encoding: [0x62,0x72,0xfd,0x48,0x5b,0x6a,0x80]
+          vbroadcasti64x4 -4096(%rdx), %zmm13
 
 // CHECK: vmovdqu64 {{.*}} {%k3}
 // CHECK: encoding: [0x62,0xf1,0xfe,0x4b,0x7f,0x07]
@@ -4761,11 +6012,11 @@ vmovntpd %zmm6, 4(%rdx)
 // CHECK: encoding: [0x62,0x51,0x7c,0x48,0x2b,0x5c,0x8d,0x00]
 vmovntps %zmm11, (%r13,%rcx,4)
 
-// CHECK: vcmpps $14
+// CHECK: vcmpgtps %zmm17, %zmm5, %k2
 // CHECK: encoding: [0x62,0xb1,0x54,0x48,0xc2,0xd1,0x0e]
 vcmpgtps %zmm17, %zmm5, %k2
 
-// CHECK: vcmppd $13
+// CHECK: vcmpgepd 128(%r14), %zmm17, %k6
 // CHECK: encoding: [0x62,0xd1,0xf5,0x40,0xc2,0x76,0x02,0x0d]
 vcmpgepd 0x80(%r14), %zmm17, %k6
 
@@ -4777,9 +6028,6 @@ vpcmpd $1, %zmm24, %zmm7, %k5{%k4}
 // CHECK: encoding: [0x62,0xf3,0xf5,0x47,0x1e,0x72,0x01,0x02]
 vpcmpuq $2, 0x40(%rdx), %zmm17, %k6{%k7}
 
-// ERR: invalid operand for instruction
-vpcmpd $1, %zmm24, %zmm7, %k5{%k0}
-
 // CHECK: vpermi2d
 // CHECK: encoding: [0x62,0x42,0x6d,0x4b,0x76,0xd6]
 vpermi2d %zmm14, %zmm2, %zmm26 {%k3}
@@ -4851,3 +6099,1628 @@ vpermilps 0x400(%rbx), %zmm2, %zmm3
 // CHECK: vpermilpd
 // CHECK: encoding: [0x62,0xf3,0xfd,0x48,0x05,0x53,0x10,0x23]
 vpermilpd $0x23, 0x400(%rbx), %zmm2
+
+// CHECK: vcmppd $171, %zmm26, %zmm12, %k2
+// CHECK:  encoding: [0x62,0x91,0x9d,0x48,0xc2,0xd2,0xab]
+          vcmppd $0xab, %zmm26, %zmm12, %k2
+
+// CHECK: vcmppd $171, %zmm26, %zmm12, %k2 {%k3}
+// CHECK:  encoding: [0x62,0x91,0x9d,0x4b,0xc2,0xd2,0xab]
+          vcmppd $0xab, %zmm26, %zmm12, %k2 {%k3}
+
+// CHECK: vcmppd $171,{sae}, %zmm26, %zmm12, %k2
+// CHECK:  encoding: [0x62,0x91,0x9d,0x18,0xc2,0xd2,0xab]
+          vcmppd $0xab,{sae}, %zmm26, %zmm12, %k2
+
+// CHECK: vcmppd $123, %zmm26, %zmm12, %k2
+// CHECK:  encoding: [0x62,0x91,0x9d,0x48,0xc2,0xd2,0x7b]
+          vcmppd $0x7b, %zmm26, %zmm12, %k2
+
+// CHECK: vcmppd $123,{sae}, %zmm26, %zmm12, %k2
+// CHECK:  encoding: [0x62,0x91,0x9d,0x18,0xc2,0xd2,0x7b]
+          vcmppd $0x7b,{sae}, %zmm26, %zmm12, %k2
+
+// CHECK: vcmppd $123, (%rcx), %zmm12, %k2
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x48,0xc2,0x11,0x7b]
+          vcmppd $0x7b, (%rcx), %zmm12, %k2
+
+// CHECK: vcmppd $123, 291(%rax,%r14,8), %zmm12, %k2
+// CHECK:  encoding: [0x62,0xb1,0x9d,0x48,0xc2,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vcmppd $0x7b, 291(%rax,%r14,8), %zmm12, %k2
+
+// CHECK: vcmppd $123, (%rcx){1to8}, %zmm12, %k2
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x58,0xc2,0x11,0x7b]
+          vcmppd $0x7b, (%rcx){1to8}, %zmm12, %k2
+
+// CHECK: vcmppd $123, 8128(%rdx), %zmm12, %k2
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x48,0xc2,0x52,0x7f,0x7b]
+          vcmppd $0x7b, 8128(%rdx), %zmm12, %k2
+
+// CHECK: vcmppd $123, 8192(%rdx), %zmm12, %k2
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x48,0xc2,0x92,0x00,0x20,0x00,0x00,0x7b]
+          vcmppd $0x7b, 8192(%rdx), %zmm12, %k2
+
+// CHECK: vcmppd $123, -8192(%rdx), %zmm12, %k2
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x48,0xc2,0x52,0x80,0x7b]
+          vcmppd $0x7b, -8192(%rdx), %zmm12, %k2
+
+// CHECK: vcmppd $123, -8256(%rdx), %zmm12, %k2
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x48,0xc2,0x92,0xc0,0xdf,0xff,0xff,0x7b]
+          vcmppd $0x7b, -8256(%rdx), %zmm12, %k2
+
+// CHECK: vcmppd $123, 1016(%rdx){1to8}, %zmm12, %k2
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x58,0xc2,0x52,0x7f,0x7b]
+          vcmppd $0x7b, 1016(%rdx){1to8}, %zmm12, %k2
+
+// CHECK: vcmppd $123, 1024(%rdx){1to8}, %zmm12, %k2
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x58,0xc2,0x92,0x00,0x04,0x00,0x00,0x7b]
+          vcmppd $0x7b, 1024(%rdx){1to8}, %zmm12, %k2
+
+// CHECK: vcmppd $123, -1024(%rdx){1to8}, %zmm12, %k2
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x58,0xc2,0x52,0x80,0x7b]
+          vcmppd $0x7b, -1024(%rdx){1to8}, %zmm12, %k2
+
+// CHECK: vcmppd $123, -1032(%rdx){1to8}, %zmm12, %k2
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x58,0xc2,0x92,0xf8,0xfb,0xff,0xff,0x7b]
+          vcmppd $0x7b, -1032(%rdx){1to8}, %zmm12, %k2
+
+// CHECK: vcmpps $171, %zmm22, %zmm17, %k2
+// CHECK:  encoding: [0x62,0xb1,0x74,0x40,0xc2,0xd6,0xab]
+          vcmpps $0xab, %zmm22, %zmm17, %k2
+
+// CHECK: vcmpps $171, %zmm22, %zmm17, %k2 {%k3}
+// CHECK:  encoding: [0x62,0xb1,0x74,0x43,0xc2,0xd6,0xab]
+          vcmpps $0xab, %zmm22, %zmm17, %k2 {%k3}
+
+// CHECK: vcmpps $171,{sae}, %zmm22, %zmm17, %k2
+// CHECK:  encoding: [0x62,0xb1,0x74,0x10,0xc2,0xd6,0xab]
+          vcmpps $0xab,{sae}, %zmm22, %zmm17, %k2
+
+// CHECK: vcmpps $123, %zmm22, %zmm17, %k2
+// CHECK:  encoding: [0x62,0xb1,0x74,0x40,0xc2,0xd6,0x7b]
+          vcmpps $0x7b, %zmm22, %zmm17, %k2
+
+// CHECK: vcmpps $123,{sae}, %zmm22, %zmm17, %k2
+// CHECK:  encoding: [0x62,0xb1,0x74,0x10,0xc2,0xd6,0x7b]
+          vcmpps $0x7b,{sae}, %zmm22, %zmm17, %k2
+
+// CHECK: vcmpps $123, (%rcx), %zmm17, %k2
+// CHECK:  encoding: [0x62,0xf1,0x74,0x40,0xc2,0x11,0x7b]
+          vcmpps $0x7b, (%rcx), %zmm17, %k2
+
+// CHECK: vcmpps $123, 291(%rax,%r14,8), %zmm17, %k2
+// CHECK:  encoding: [0x62,0xb1,0x74,0x40,0xc2,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vcmpps $0x7b, 291(%rax,%r14,8), %zmm17, %k2
+
+// CHECK: vcmpps $123, (%rcx){1to16}, %zmm17, %k2
+// CHECK:  encoding: [0x62,0xf1,0x74,0x50,0xc2,0x11,0x7b]
+          vcmpps $0x7b, (%rcx){1to16}, %zmm17, %k2
+
+// CHECK: vcmpps $123, 8128(%rdx), %zmm17, %k2
+// CHECK:  encoding: [0x62,0xf1,0x74,0x40,0xc2,0x52,0x7f,0x7b]
+          vcmpps $0x7b, 8128(%rdx), %zmm17, %k2
+
+// CHECK: vcmpps $123, 8192(%rdx), %zmm17, %k2
+// CHECK:  encoding: [0x62,0xf1,0x74,0x40,0xc2,0x92,0x00,0x20,0x00,0x00,0x7b]
+          vcmpps $0x7b, 8192(%rdx), %zmm17, %k2
+
+// CHECK: vcmpps $123, -8192(%rdx), %zmm17, %k2
+// CHECK:  encoding: [0x62,0xf1,0x74,0x40,0xc2,0x52,0x80,0x7b]
+          vcmpps $0x7b, -8192(%rdx), %zmm17, %k2
+
+// CHECK: vcmpps $123, -8256(%rdx), %zmm17, %k2
+// CHECK:  encoding: [0x62,0xf1,0x74,0x40,0xc2,0x92,0xc0,0xdf,0xff,0xff,0x7b]
+          vcmpps $0x7b, -8256(%rdx), %zmm17, %k2
+
+// CHECK: vcmpps $123, 508(%rdx){1to16}, %zmm17, %k2
+// CHECK:  encoding: [0x62,0xf1,0x74,0x50,0xc2,0x52,0x7f,0x7b]
+          vcmpps $0x7b, 508(%rdx){1to16}, %zmm17, %k2
+
+// CHECK: vcmpps $123, 512(%rdx){1to16}, %zmm17, %k2
+// CHECK:  encoding: [0x62,0xf1,0x74,0x50,0xc2,0x92,0x00,0x02,0x00,0x00,0x7b]
+          vcmpps $0x7b, 512(%rdx){1to16}, %zmm17, %k2
+
+// CHECK: vcmpps $123, -512(%rdx){1to16}, %zmm17, %k2
+// CHECK:  encoding: [0x62,0xf1,0x74,0x50,0xc2,0x52,0x80,0x7b]
+          vcmpps $0x7b, -512(%rdx){1to16}, %zmm17, %k2
+
+// CHECK: vcmpps $123, -516(%rdx){1to16}, %zmm17, %k2
+// CHECK:  encoding: [0x62,0xf1,0x74,0x50,0xc2,0x92,0xfc,0xfd,0xff,0xff,0x7b]
+          vcmpps $0x7b, -516(%rdx){1to16}, %zmm17, %k2
+
+// CHECK: vaddpd {rn-sae}, %zmm6, %zmm27, %zmm8
+// CHECK:  encoding: [0x62,0x71,0xa5,0x10,0x58,0xc6]
+          vaddpd {rn-sae}, %zmm6, %zmm27, %zmm8
+
+// CHECK: vaddpd {ru-sae}, %zmm6, %zmm27, %zmm8
+// CHECK:  encoding: [0x62,0x71,0xa5,0x50,0x58,0xc6]
+          vaddpd {ru-sae}, %zmm6, %zmm27, %zmm8
+
+// CHECK: vaddpd {rd-sae}, %zmm6, %zmm27, %zmm8
+// CHECK:  encoding: [0x62,0x71,0xa5,0x30,0x58,0xc6]
+          vaddpd {rd-sae}, %zmm6, %zmm27, %zmm8
+
+// CHECK: vaddpd {rz-sae}, %zmm6, %zmm27, %zmm8
+// CHECK:  encoding: [0x62,0x71,0xa5,0x70,0x58,0xc6]
+          vaddpd {rz-sae}, %zmm6, %zmm27, %zmm8
+
+// CHECK: vaddps {rn-sae}, %zmm2, %zmm13, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x14,0x18,0x58,0xd2]
+          vaddps {rn-sae}, %zmm2, %zmm13, %zmm18
+
+// CHECK: vaddps {ru-sae}, %zmm2, %zmm13, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x14,0x58,0x58,0xd2]
+          vaddps {ru-sae}, %zmm2, %zmm13, %zmm18
+
+// CHECK: vaddps {rd-sae}, %zmm2, %zmm13, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x14,0x38,0x58,0xd2]
+          vaddps {rd-sae}, %zmm2, %zmm13, %zmm18
+
+// CHECK: vaddps {rz-sae}, %zmm2, %zmm13, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x14,0x78,0x58,0xd2]
+          vaddps {rz-sae}, %zmm2, %zmm13, %zmm18
+
+// CHECK: vaddsd %xmm8, %xmm17, %xmm3
+// CHECK:  encoding: [0x62,0xd1,0xf7,0x00,0x58,0xd8]
+          vaddsd %xmm8, %xmm17, %xmm3
+
+// CHECK: vaddsd %xmm8, %xmm17, %xmm3 {%k3}
+// CHECK:  encoding: [0x62,0xd1,0xf7,0x03,0x58,0xd8]
+          vaddsd %xmm8, %xmm17, %xmm3 {%k3}
+
+// CHECK: vaddsd %xmm8, %xmm17, %xmm3 {%k3} {z}
+// CHECK:  encoding: [0x62,0xd1,0xf7,0x83,0x58,0xd8]
+          vaddsd %xmm8, %xmm17, %xmm3 {%k3} {z}
+
+// CHECK: vaddsd {rn-sae}, %xmm8, %xmm17, %xmm3
+// CHECK:  encoding: [0x62,0xd1,0xf7,0x10,0x58,0xd8]
+          vaddsd {rn-sae}, %xmm8, %xmm17, %xmm3
+
+// CHECK: vaddsd {ru-sae}, %xmm8, %xmm17, %xmm3
+// CHECK:  encoding: [0x62,0xd1,0xf7,0x50,0x58,0xd8]
+          vaddsd {ru-sae}, %xmm8, %xmm17, %xmm3
+
+// CHECK: vaddsd {rd-sae}, %xmm8, %xmm17, %xmm3
+// CHECK:  encoding: [0x62,0xd1,0xf7,0x30,0x58,0xd8]
+          vaddsd {rd-sae}, %xmm8, %xmm17, %xmm3
+
+// CHECK: vaddsd {rz-sae}, %xmm8, %xmm17, %xmm3
+// CHECK:  encoding: [0x62,0xd1,0xf7,0x70,0x58,0xd8]
+          vaddsd {rz-sae}, %xmm8, %xmm17, %xmm3
+
+// CHECK: vaddsd (%rcx), %xmm17, %xmm3
+// CHECK:  encoding: [0x62,0xf1,0xf7,0x00,0x58,0x19]
+          vaddsd (%rcx), %xmm17, %xmm3
+
+// CHECK: vaddsd 291(%rax,%r14,8), %xmm17, %xmm3
+// CHECK:  encoding: [0x62,0xb1,0xf7,0x00,0x58,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vaddsd 291(%rax,%r14,8), %xmm17, %xmm3
+
+// CHECK: vaddsd 1016(%rdx), %xmm17, %xmm3
+// CHECK:  encoding: [0x62,0xf1,0xf7,0x00,0x58,0x5a,0x7f]
+          vaddsd 1016(%rdx), %xmm17, %xmm3
+
+// CHECK: vaddsd 1024(%rdx), %xmm17, %xmm3
+// CHECK:  encoding: [0x62,0xf1,0xf7,0x00,0x58,0x9a,0x00,0x04,0x00,0x00]
+          vaddsd 1024(%rdx), %xmm17, %xmm3
+
+// CHECK: vaddsd -1024(%rdx), %xmm17, %xmm3
+// CHECK:  encoding: [0x62,0xf1,0xf7,0x00,0x58,0x5a,0x80]
+          vaddsd -1024(%rdx), %xmm17, %xmm3
+
+// CHECK: vaddsd -1032(%rdx), %xmm17, %xmm3
+// CHECK:  encoding: [0x62,0xf1,0xf7,0x00,0x58,0x9a,0xf8,0xfb,0xff,0xff]
+          vaddsd -1032(%rdx), %xmm17, %xmm3
+
+// CHECK: vaddss %xmm19, %xmm5, %xmm7
+// CHECK:  encoding: [0x62,0xb1,0x56,0x08,0x58,0xfb]
+          vaddss %xmm19, %xmm5, %xmm7
+
+// CHECK: vaddss %xmm19, %xmm5, %xmm7 {%k2}
+// CHECK:  encoding: [0x62,0xb1,0x56,0x0a,0x58,0xfb]
+          vaddss %xmm19, %xmm5, %xmm7 {%k2}
+
+// CHECK: vaddss %xmm19, %xmm5, %xmm7 {%k2} {z}
+// CHECK:  encoding: [0x62,0xb1,0x56,0x8a,0x58,0xfb]
+          vaddss %xmm19, %xmm5, %xmm7 {%k2} {z}
+
+// CHECK: vaddss {rn-sae}, %xmm19, %xmm5, %xmm7
+// CHECK:  encoding: [0x62,0xb1,0x56,0x18,0x58,0xfb]
+          vaddss {rn-sae}, %xmm19, %xmm5, %xmm7
+
+// CHECK: vaddss {ru-sae}, %xmm19, %xmm5, %xmm7
+// CHECK:  encoding: [0x62,0xb1,0x56,0x58,0x58,0xfb]
+          vaddss {ru-sae}, %xmm19, %xmm5, %xmm7
+
+// CHECK: vaddss {rd-sae}, %xmm19, %xmm5, %xmm7
+// CHECK:  encoding: [0x62,0xb1,0x56,0x38,0x58,0xfb]
+          vaddss {rd-sae}, %xmm19, %xmm5, %xmm7
+
+// CHECK: vaddss {rz-sae}, %xmm19, %xmm5, %xmm7
+// CHECK:  encoding: [0x62,0xb1,0x56,0x78,0x58,0xfb]
+          vaddss {rz-sae}, %xmm19, %xmm5, %xmm7
+
+// CHECK: vaddss (%rcx), %xmm5, %xmm7
+// CHECK:  encoding: [0x62,0xf1,0x56,0x08,0x58,0x39]
+          vaddss (%rcx), %xmm5, %xmm7
+
+// CHECK: vaddss 291(%rax,%r14,8), %xmm5, %xmm7
+// CHECK:  encoding: [0x62,0xb1,0x56,0x08,0x58,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vaddss 291(%rax,%r14,8), %xmm5, %xmm7
+
+// CHECK: vaddss 508(%rdx), %xmm5, %xmm7
+// CHECK:  encoding: [0x62,0xf1,0x56,0x08,0x58,0x7a,0x7f]
+          vaddss 508(%rdx), %xmm5, %xmm7
+
+// CHECK: vaddss 512(%rdx), %xmm5, %xmm7
+// CHECK:  encoding: [0x62,0xf1,0x56,0x08,0x58,0xba,0x00,0x02,0x00,0x00]
+          vaddss 512(%rdx), %xmm5, %xmm7
+
+// CHECK: vaddss -512(%rdx), %xmm5, %xmm7
+// CHECK:  encoding: [0x62,0xf1,0x56,0x08,0x58,0x7a,0x80]
+          vaddss -512(%rdx), %xmm5, %xmm7
+
+// CHECK: vaddss -516(%rdx), %xmm5, %xmm7
+// CHECK:  encoding: [0x62,0xf1,0x56,0x08,0x58,0xba,0xfc,0xfd,0xff,0xff]
+          vaddss -516(%rdx), %xmm5, %xmm7
+
+// CHECK: vdivpd {rn-sae}, %zmm11, %zmm6, %zmm18
+// CHECK:  encoding: [0x62,0xc1,0xcd,0x18,0x5e,0xd3]
+          vdivpd {rn-sae}, %zmm11, %zmm6, %zmm18
+
+// CHECK: vdivpd {ru-sae}, %zmm11, %zmm6, %zmm18
+// CHECK:  encoding: [0x62,0xc1,0xcd,0x58,0x5e,0xd3]
+          vdivpd {ru-sae}, %zmm11, %zmm6, %zmm18
+
+// CHECK: vdivpd {rd-sae}, %zmm11, %zmm6, %zmm18
+// CHECK:  encoding: [0x62,0xc1,0xcd,0x38,0x5e,0xd3]
+          vdivpd {rd-sae}, %zmm11, %zmm6, %zmm18
+
+// CHECK: vdivpd {rz-sae}, %zmm11, %zmm6, %zmm18
+// CHECK:  encoding: [0x62,0xc1,0xcd,0x78,0x5e,0xd3]
+          vdivpd {rz-sae}, %zmm11, %zmm6, %zmm18
+
+// CHECK: vdivps {rn-sae}, %zmm28, %zmm23, %zmm23
+// CHECK:  encoding: [0x62,0x81,0x44,0x10,0x5e,0xfc]
+          vdivps {rn-sae}, %zmm28, %zmm23, %zmm23
+
+// CHECK: vdivps {ru-sae}, %zmm28, %zmm23, %zmm23
+// CHECK:  encoding: [0x62,0x81,0x44,0x50,0x5e,0xfc]
+          vdivps {ru-sae}, %zmm28, %zmm23, %zmm23
+
+// CHECK: vdivps {rd-sae}, %zmm28, %zmm23, %zmm23
+// CHECK:  encoding: [0x62,0x81,0x44,0x30,0x5e,0xfc]
+          vdivps {rd-sae}, %zmm28, %zmm23, %zmm23
+
+// CHECK: vdivps {rz-sae}, %zmm28, %zmm23, %zmm23
+// CHECK:  encoding: [0x62,0x81,0x44,0x70,0x5e,0xfc]
+          vdivps {rz-sae}, %zmm28, %zmm23, %zmm23
+
+// CHECK: vdivsd %xmm22, %xmm13, %xmm29
+// CHECK:  encoding: [0x62,0x21,0x97,0x08,0x5e,0xee]
+          vdivsd %xmm22, %xmm13, %xmm29
+
+// CHECK: vdivsd %xmm22, %xmm13, %xmm29 {%k3}
+// CHECK:  encoding: [0x62,0x21,0x97,0x0b,0x5e,0xee]
+          vdivsd %xmm22, %xmm13, %xmm29 {%k3}
+
+// CHECK: vdivsd %xmm22, %xmm13, %xmm29 {%k3} {z}
+// CHECK:  encoding: [0x62,0x21,0x97,0x8b,0x5e,0xee]
+          vdivsd %xmm22, %xmm13, %xmm29 {%k3} {z}
+
+// CHECK: vdivsd {rn-sae}, %xmm22, %xmm13, %xmm29
+// CHECK:  encoding: [0x62,0x21,0x97,0x18,0x5e,0xee]
+          vdivsd {rn-sae}, %xmm22, %xmm13, %xmm29
+
+// CHECK: vdivsd {ru-sae}, %xmm22, %xmm13, %xmm29
+// CHECK:  encoding: [0x62,0x21,0x97,0x58,0x5e,0xee]
+          vdivsd {ru-sae}, %xmm22, %xmm13, %xmm29
+
+// CHECK: vdivsd {rd-sae}, %xmm22, %xmm13, %xmm29
+// CHECK:  encoding: [0x62,0x21,0x97,0x38,0x5e,0xee]
+          vdivsd {rd-sae}, %xmm22, %xmm13, %xmm29
+
+// CHECK: vdivsd {rz-sae}, %xmm22, %xmm13, %xmm29
+// CHECK:  encoding: [0x62,0x21,0x97,0x78,0x5e,0xee]
+          vdivsd {rz-sae}, %xmm22, %xmm13, %xmm29
+
+// CHECK: vdivsd (%rcx), %xmm13, %xmm29
+// CHECK:  encoding: [0x62,0x61,0x97,0x08,0x5e,0x29]
+          vdivsd (%rcx), %xmm13, %xmm29
+
+// CHECK: vdivsd 291(%rax,%r14,8), %xmm13, %xmm29
+// CHECK:  encoding: [0x62,0x21,0x97,0x08,0x5e,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vdivsd 291(%rax,%r14,8), %xmm13, %xmm29
+
+// CHECK: vdivsd 1016(%rdx), %xmm13, %xmm29
+// CHECK:  encoding: [0x62,0x61,0x97,0x08,0x5e,0x6a,0x7f]
+          vdivsd 1016(%rdx), %xmm13, %xmm29
+
+// CHECK: vdivsd 1024(%rdx), %xmm13, %xmm29
+// CHECK:  encoding: [0x62,0x61,0x97,0x08,0x5e,0xaa,0x00,0x04,0x00,0x00]
+          vdivsd 1024(%rdx), %xmm13, %xmm29
+
+// CHECK: vdivsd -1024(%rdx), %xmm13, %xmm29
+// CHECK:  encoding: [0x62,0x61,0x97,0x08,0x5e,0x6a,0x80]
+          vdivsd -1024(%rdx), %xmm13, %xmm29
+
+// CHECK: vdivsd -1032(%rdx), %xmm13, %xmm29
+// CHECK:  encoding: [0x62,0x61,0x97,0x08,0x5e,0xaa,0xf8,0xfb,0xff,0xff]
+          vdivsd -1032(%rdx), %xmm13, %xmm29
+
+// CHECK: vdivss %xmm17, %xmm6, %xmm21
+// CHECK:  encoding: [0x62,0xa1,0x4e,0x08,0x5e,0xe9]
+          vdivss %xmm17, %xmm6, %xmm21
+
+// CHECK: vdivss %xmm17, %xmm6, %xmm21 {%k5}
+// CHECK:  encoding: [0x62,0xa1,0x4e,0x0d,0x5e,0xe9]
+          vdivss %xmm17, %xmm6, %xmm21 {%k5}
+
+// CHECK: vdivss %xmm17, %xmm6, %xmm21 {%k5} {z}
+// CHECK:  encoding: [0x62,0xa1,0x4e,0x8d,0x5e,0xe9]
+          vdivss %xmm17, %xmm6, %xmm21 {%k5} {z}
+
+// CHECK: vdivss {rn-sae}, %xmm17, %xmm6, %xmm21
+// CHECK:  encoding: [0x62,0xa1,0x4e,0x18,0x5e,0xe9]
+          vdivss {rn-sae}, %xmm17, %xmm6, %xmm21
+
+// CHECK: vdivss {ru-sae}, %xmm17, %xmm6, %xmm21
+// CHECK:  encoding: [0x62,0xa1,0x4e,0x58,0x5e,0xe9]
+          vdivss {ru-sae}, %xmm17, %xmm6, %xmm21
+
+// CHECK: vdivss {rd-sae}, %xmm17, %xmm6, %xmm21
+// CHECK:  encoding: [0x62,0xa1,0x4e,0x38,0x5e,0xe9]
+          vdivss {rd-sae}, %xmm17, %xmm6, %xmm21
+
+// CHECK: vdivss {rz-sae}, %xmm17, %xmm6, %xmm21
+// CHECK:  encoding: [0x62,0xa1,0x4e,0x78,0x5e,0xe9]
+          vdivss {rz-sae}, %xmm17, %xmm6, %xmm21
+
+// CHECK: vdivss (%rcx), %xmm6, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x4e,0x08,0x5e,0x29]
+          vdivss (%rcx), %xmm6, %xmm21
+
+// CHECK: vdivss 291(%rax,%r14,8), %xmm6, %xmm21
+// CHECK:  encoding: [0x62,0xa1,0x4e,0x08,0x5e,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vdivss 291(%rax,%r14,8), %xmm6, %xmm21
+
+// CHECK: vdivss 508(%rdx), %xmm6, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x4e,0x08,0x5e,0x6a,0x7f]
+          vdivss 508(%rdx), %xmm6, %xmm21
+
+// CHECK: vdivss 512(%rdx), %xmm6, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x4e,0x08,0x5e,0xaa,0x00,0x02,0x00,0x00]
+          vdivss 512(%rdx), %xmm6, %xmm21
+
+// CHECK: vdivss -512(%rdx), %xmm6, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x4e,0x08,0x5e,0x6a,0x80]
+          vdivss -512(%rdx), %xmm6, %xmm21
+
+// CHECK: vdivss -516(%rdx), %xmm6, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x4e,0x08,0x5e,0xaa,0xfc,0xfd,0xff,0xff]
+          vdivss -516(%rdx), %xmm6, %xmm21
+
+// CHECK: vmaxpd {sae}, %zmm20, %zmm28, %zmm30
+// CHECK:  encoding: [0x62,0x21,0x9d,0x10,0x5f,0xf4]
+          vmaxpd {sae}, %zmm20, %zmm28, %zmm30
+
+// CHECK: vmaxps {sae}, %zmm20, %zmm6, %zmm25
+// CHECK:  encoding: [0x62,0x21,0x4c,0x18,0x5f,0xcc]
+          vmaxps {sae}, %zmm20, %zmm6, %zmm25
+
+// CHECK: vmaxsd %xmm25, %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0x81,0xe7,0x00,0x5f,0xe1]
+          vmaxsd %xmm25, %xmm19, %xmm20
+
+// CHECK: vmaxsd %xmm25, %xmm19, %xmm20 {%k3}
+// CHECK:  encoding: [0x62,0x81,0xe7,0x03,0x5f,0xe1]
+          vmaxsd %xmm25, %xmm19, %xmm20 {%k3}
+
+// CHECK: vmaxsd %xmm25, %xmm19, %xmm20 {%k3} {z}
+// CHECK:  encoding: [0x62,0x81,0xe7,0x83,0x5f,0xe1]
+          vmaxsd %xmm25, %xmm19, %xmm20 {%k3} {z}
+
+// CHECK: vmaxsd {sae}, %xmm25, %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0x81,0xe7,0x10,0x5f,0xe1]
+          vmaxsd {sae}, %xmm25, %xmm19, %xmm20
+
+// CHECK: vmaxsd (%rcx), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0xe7,0x00,0x5f,0x21]
+          vmaxsd (%rcx), %xmm19, %xmm20
+
+// CHECK: vmaxsd 291(%rax,%r14,8), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0xe7,0x00,0x5f,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vmaxsd 291(%rax,%r14,8), %xmm19, %xmm20
+
+// CHECK: vmaxsd 1016(%rdx), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0xe7,0x00,0x5f,0x62,0x7f]
+          vmaxsd 1016(%rdx), %xmm19, %xmm20
+
+// CHECK: vmaxsd 1024(%rdx), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0xe7,0x00,0x5f,0xa2,0x00,0x04,0x00,0x00]
+          vmaxsd 1024(%rdx), %xmm19, %xmm20
+
+// CHECK: vmaxsd -1024(%rdx), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0xe7,0x00,0x5f,0x62,0x80]
+          vmaxsd -1024(%rdx), %xmm19, %xmm20
+
+// CHECK: vmaxsd -1032(%rdx), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0xe7,0x00,0x5f,0xa2,0xf8,0xfb,0xff,0xff]
+          vmaxsd -1032(%rdx), %xmm19, %xmm20
+
+// CHECK: vmaxss %xmm6, %xmm4, %xmm8
+// CHECK:  encoding: [0xc5,0x5a,0x5f,0xc6]
+          vmaxss %xmm6, %xmm4, %xmm8
+
+// CHECK: vmaxss %xmm6, %xmm4, %xmm8 {%k4}
+// CHECK:  encoding: [0x62,0x71,0x5e,0x0c,0x5f,0xc6]
+          vmaxss %xmm6, %xmm4, %xmm8 {%k4}
+
+// CHECK: vmaxss %xmm6, %xmm4, %xmm8 {%k4} {z}
+// CHECK:  encoding: [0x62,0x71,0x5e,0x8c,0x5f,0xc6]
+          vmaxss %xmm6, %xmm4, %xmm8 {%k4} {z}
+
+// CHECK: vmaxss {sae}, %xmm6, %xmm4, %xmm8
+// CHECK:  encoding: [0x62,0x71,0x5e,0x18,0x5f,0xc6]
+          vmaxss {sae}, %xmm6, %xmm4, %xmm8
+
+// CHECK: vmaxss (%rcx), %xmm4, %xmm8
+// CHECK:  encoding: [0x62,0x71,0x5e,0x08,0x5f,0x01]
+          vmaxss (%rcx), %xmm4, %xmm8
+
+// CHECK: vmaxss 291(%rax,%r14,8), %xmm4, %xmm8
+// CHECK:  encoding: [0x62,0x31,0x5e,0x08,0x5f,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vmaxss 291(%rax,%r14,8), %xmm4, %xmm8
+
+// CHECK: vmaxss 508(%rdx), %xmm4, %xmm8
+// CHECK:  encoding: [0x62,0x71,0x5e,0x08,0x5f,0x42,0x7f]
+          vmaxss 508(%rdx), %xmm4, %xmm8
+
+// CHECK: vmaxss 512(%rdx), %xmm4, %xmm8
+// CHECK:  encoding: [0x62,0x71,0x5e,0x08,0x5f,0x82,0x00,0x02,0x00,0x00]
+          vmaxss 512(%rdx), %xmm4, %xmm8
+
+// CHECK: vmaxss -512(%rdx), %xmm4, %xmm8
+// CHECK:  encoding: [0x62,0x71,0x5e,0x08,0x5f,0x42,0x80]
+          vmaxss -512(%rdx), %xmm4, %xmm8
+
+// CHECK: vmaxss -516(%rdx), %xmm4, %xmm8
+// CHECK:  encoding: [0x62,0x71,0x5e,0x08,0x5f,0x82,0xfc,0xfd,0xff,0xff]
+          vmaxss -516(%rdx), %xmm4, %xmm8
+
+// CHECK: vminpd {sae}, %zmm22, %zmm6, %zmm6
+// CHECK:  encoding: [0x62,0xb1,0xcd,0x18,0x5d,0xf6]
+          vminpd {sae}, %zmm22, %zmm6, %zmm6
+
+// CHECK: vminps {sae}, %zmm7, %zmm3, %zmm3
+// CHECK:  encoding: [0x62,0xf1,0x64,0x18,0x5d,0xdf]
+          vminps {sae}, %zmm7, %zmm3, %zmm3
+
+// CHECK: vminsd %xmm26, %xmm25, %xmm5
+// CHECK:  encoding: [0x62,0x91,0xb7,0x00,0x5d,0xea]
+          vminsd %xmm26, %xmm25, %xmm5
+
+// CHECK: vminsd %xmm26, %xmm25, %xmm5 {%k3}
+// CHECK:  encoding: [0x62,0x91,0xb7,0x03,0x5d,0xea]
+          vminsd %xmm26, %xmm25, %xmm5 {%k3}
+
+// CHECK: vminsd %xmm26, %xmm25, %xmm5 {%k3} {z}
+// CHECK:  encoding: [0x62,0x91,0xb7,0x83,0x5d,0xea]
+          vminsd %xmm26, %xmm25, %xmm5 {%k3} {z}
+
+// CHECK: vminsd {sae}, %xmm26, %xmm25, %xmm5
+// CHECK:  encoding: [0x62,0x91,0xb7,0x10,0x5d,0xea]
+          vminsd {sae}, %xmm26, %xmm25, %xmm5
+
+// CHECK: vminsd (%rcx), %xmm25, %xmm5
+// CHECK:  encoding: [0x62,0xf1,0xb7,0x00,0x5d,0x29]
+          vminsd (%rcx), %xmm25, %xmm5
+
+// CHECK: vminsd 291(%rax,%r14,8), %xmm25, %xmm5
+// CHECK:  encoding: [0x62,0xb1,0xb7,0x00,0x5d,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vminsd 291(%rax,%r14,8), %xmm25, %xmm5
+
+// CHECK: vminsd 1016(%rdx), %xmm25, %xmm5
+// CHECK:  encoding: [0x62,0xf1,0xb7,0x00,0x5d,0x6a,0x7f]
+          vminsd 1016(%rdx), %xmm25, %xmm5
+
+// CHECK: vminsd 1024(%rdx), %xmm25, %xmm5
+// CHECK:  encoding: [0x62,0xf1,0xb7,0x00,0x5d,0xaa,0x00,0x04,0x00,0x00]
+          vminsd 1024(%rdx), %xmm25, %xmm5
+
+// CHECK: vminsd -1024(%rdx), %xmm25, %xmm5
+// CHECK:  encoding: [0x62,0xf1,0xb7,0x00,0x5d,0x6a,0x80]
+          vminsd -1024(%rdx), %xmm25, %xmm5
+
+// CHECK: vminsd -1032(%rdx), %xmm25, %xmm5
+// CHECK:  encoding: [0x62,0xf1,0xb7,0x00,0x5d,0xaa,0xf8,0xfb,0xff,0xff]
+          vminsd -1032(%rdx), %xmm25, %xmm5
+
+// CHECK: vminss %xmm19, %xmm17, %xmm10
+// CHECK:  encoding: [0x62,0x31,0x76,0x00,0x5d,0xd3]
+          vminss %xmm19, %xmm17, %xmm10
+
+// CHECK: vminss %xmm19, %xmm17, %xmm10 {%k5}
+// CHECK:  encoding: [0x62,0x31,0x76,0x05,0x5d,0xd3]
+          vminss %xmm19, %xmm17, %xmm10 {%k5}
+
+// CHECK: vminss %xmm19, %xmm17, %xmm10 {%k5} {z}
+// CHECK:  encoding: [0x62,0x31,0x76,0x85,0x5d,0xd3]
+          vminss %xmm19, %xmm17, %xmm10 {%k5} {z}
+
+// CHECK: vminss {sae}, %xmm19, %xmm17, %xmm10
+// CHECK:  encoding: [0x62,0x31,0x76,0x10,0x5d,0xd3]
+          vminss {sae}, %xmm19, %xmm17, %xmm10
+
+// CHECK: vminss (%rcx), %xmm17, %xmm10
+// CHECK:  encoding: [0x62,0x71,0x76,0x00,0x5d,0x11]
+          vminss (%rcx), %xmm17, %xmm10
+
+// CHECK: vminss 291(%rax,%r14,8), %xmm17, %xmm10
+// CHECK:  encoding: [0x62,0x31,0x76,0x00,0x5d,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vminss 291(%rax,%r14,8), %xmm17, %xmm10
+
+// CHECK: vminss 508(%rdx), %xmm17, %xmm10
+// CHECK:  encoding: [0x62,0x71,0x76,0x00,0x5d,0x52,0x7f]
+          vminss 508(%rdx), %xmm17, %xmm10
+
+// CHECK: vminss 512(%rdx), %xmm17, %xmm10
+// CHECK:  encoding: [0x62,0x71,0x76,0x00,0x5d,0x92,0x00,0x02,0x00,0x00]
+          vminss 512(%rdx), %xmm17, %xmm10
+
+// CHECK: vminss -512(%rdx), %xmm17, %xmm10
+// CHECK:  encoding: [0x62,0x71,0x76,0x00,0x5d,0x52,0x80]
+          vminss -512(%rdx), %xmm17, %xmm10
+
+// CHECK: vminss -516(%rdx), %xmm17, %xmm10
+// CHECK:  encoding: [0x62,0x71,0x76,0x00,0x5d,0x92,0xfc,0xfd,0xff,0xff]
+          vminss -516(%rdx), %xmm17, %xmm10
+
+// CHECK: vmulpd {rn-sae}, %zmm23, %zmm4, %zmm24
+// CHECK:  encoding: [0x62,0x21,0xdd,0x18,0x59,0xc7]
+          vmulpd {rn-sae}, %zmm23, %zmm4, %zmm24
+
+// CHECK: vmulpd {ru-sae}, %zmm23, %zmm4, %zmm24
+// CHECK:  encoding: [0x62,0x21,0xdd,0x58,0x59,0xc7]
+          vmulpd {ru-sae}, %zmm23, %zmm4, %zmm24
+
+// CHECK: vmulpd {rd-sae}, %zmm23, %zmm4, %zmm24
+// CHECK:  encoding: [0x62,0x21,0xdd,0x38,0x59,0xc7]
+          vmulpd {rd-sae}, %zmm23, %zmm4, %zmm24
+
+// CHECK: vmulpd {rz-sae}, %zmm23, %zmm4, %zmm24
+// CHECK:  encoding: [0x62,0x21,0xdd,0x78,0x59,0xc7]
+          vmulpd {rz-sae}, %zmm23, %zmm4, %zmm24
+
+// CHECK: vmulps {rn-sae}, %zmm24, %zmm6, %zmm3
+// CHECK:  encoding: [0x62,0x91,0x4c,0x18,0x59,0xd8]
+          vmulps {rn-sae}, %zmm24, %zmm6, %zmm3
+
+// CHECK: vmulps {ru-sae}, %zmm24, %zmm6, %zmm3
+// CHECK:  encoding: [0x62,0x91,0x4c,0x58,0x59,0xd8]
+          vmulps {ru-sae}, %zmm24, %zmm6, %zmm3
+
+// CHECK: vmulps {rd-sae}, %zmm24, %zmm6, %zmm3
+// CHECK:  encoding: [0x62,0x91,0x4c,0x38,0x59,0xd8]
+          vmulps {rd-sae}, %zmm24, %zmm6, %zmm3
+
+// CHECK: vmulps {rz-sae}, %zmm24, %zmm6, %zmm3
+// CHECK:  encoding: [0x62,0x91,0x4c,0x78,0x59,0xd8]
+          vmulps {rz-sae}, %zmm24, %zmm6, %zmm3
+
+// CHECK: vmulsd %xmm18, %xmm4, %xmm13
+// CHECK:  encoding: [0x62,0x31,0xdf,0x08,0x59,0xea]
+          vmulsd %xmm18, %xmm4, %xmm13
+
+// CHECK: vmulsd %xmm18, %xmm4, %xmm13 {%k2}
+// CHECK:  encoding: [0x62,0x31,0xdf,0x0a,0x59,0xea]
+          vmulsd %xmm18, %xmm4, %xmm13 {%k2}
+
+// CHECK: vmulsd %xmm18, %xmm4, %xmm13 {%k2} {z}
+// CHECK:  encoding: [0x62,0x31,0xdf,0x8a,0x59,0xea]
+          vmulsd %xmm18, %xmm4, %xmm13 {%k2} {z}
+
+// CHECK: vmulsd {rn-sae}, %xmm18, %xmm4, %xmm13
+// CHECK:  encoding: [0x62,0x31,0xdf,0x18,0x59,0xea]
+          vmulsd {rn-sae}, %xmm18, %xmm4, %xmm13
+
+// CHECK: vmulsd {ru-sae}, %xmm18, %xmm4, %xmm13
+// CHECK:  encoding: [0x62,0x31,0xdf,0x58,0x59,0xea]
+          vmulsd {ru-sae}, %xmm18, %xmm4, %xmm13
+
+// CHECK: vmulsd {rd-sae}, %xmm18, %xmm4, %xmm13
+// CHECK:  encoding: [0x62,0x31,0xdf,0x38,0x59,0xea]
+          vmulsd {rd-sae}, %xmm18, %xmm4, %xmm13
+
+// CHECK: vmulsd {rz-sae}, %xmm18, %xmm4, %xmm13
+// CHECK:  encoding: [0x62,0x31,0xdf,0x78,0x59,0xea]
+          vmulsd {rz-sae}, %xmm18, %xmm4, %xmm13
+
+// CHECK: vmulsd (%rcx), %xmm4, %xmm13
+// CHECK:  encoding: [0x62,0x71,0xdf,0x08,0x59,0x29]
+          vmulsd (%rcx), %xmm4, %xmm13
+
+// CHECK: vmulsd 291(%rax,%r14,8), %xmm4, %xmm13
+// CHECK:  encoding: [0x62,0x31,0xdf,0x08,0x59,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vmulsd 291(%rax,%r14,8), %xmm4, %xmm13
+
+// CHECK: vmulsd 1016(%rdx), %xmm4, %xmm13
+// CHECK:  encoding: [0x62,0x71,0xdf,0x08,0x59,0x6a,0x7f]
+          vmulsd 1016(%rdx), %xmm4, %xmm13
+
+// CHECK: vmulsd 1024(%rdx), %xmm4, %xmm13
+// CHECK:  encoding: [0x62,0x71,0xdf,0x08,0x59,0xaa,0x00,0x04,0x00,0x00]
+          vmulsd 1024(%rdx), %xmm4, %xmm13
+
+// CHECK: vmulsd -1024(%rdx), %xmm4, %xmm13
+// CHECK:  encoding: [0x62,0x71,0xdf,0x08,0x59,0x6a,0x80]
+          vmulsd -1024(%rdx), %xmm4, %xmm13
+
+// CHECK: vmulsd -1032(%rdx), %xmm4, %xmm13
+// CHECK:  encoding: [0x62,0x71,0xdf,0x08,0x59,0xaa,0xf8,0xfb,0xff,0xff]
+          vmulsd -1032(%rdx), %xmm4, %xmm13
+
+// CHECK: vmulss %xmm14, %xmm10, %xmm22
+// CHECK:  encoding: [0x62,0xc1,0x2e,0x08,0x59,0xf6]
+          vmulss %xmm14, %xmm10, %xmm22
+
+// CHECK: vmulss %xmm14, %xmm10, %xmm22 {%k4}
+// CHECK:  encoding: [0x62,0xc1,0x2e,0x0c,0x59,0xf6]
+          vmulss %xmm14, %xmm10, %xmm22 {%k4}
+
+// CHECK: vmulss %xmm14, %xmm10, %xmm22 {%k4} {z}
+// CHECK:  encoding: [0x62,0xc1,0x2e,0x8c,0x59,0xf6]
+          vmulss %xmm14, %xmm10, %xmm22 {%k4} {z}
+
+// CHECK: vmulss {rn-sae}, %xmm14, %xmm10, %xmm22
+// CHECK:  encoding: [0x62,0xc1,0x2e,0x18,0x59,0xf6]
+          vmulss {rn-sae}, %xmm14, %xmm10, %xmm22
+
+// CHECK: vmulss {ru-sae}, %xmm14, %xmm10, %xmm22
+// CHECK:  encoding: [0x62,0xc1,0x2e,0x58,0x59,0xf6]
+          vmulss {ru-sae}, %xmm14, %xmm10, %xmm22
+
+// CHECK: vmulss {rd-sae}, %xmm14, %xmm10, %xmm22
+// CHECK:  encoding: [0x62,0xc1,0x2e,0x38,0x59,0xf6]
+          vmulss {rd-sae}, %xmm14, %xmm10, %xmm22
+
+// CHECK: vmulss {rz-sae}, %xmm14, %xmm10, %xmm22
+// CHECK:  encoding: [0x62,0xc1,0x2e,0x78,0x59,0xf6]
+          vmulss {rz-sae}, %xmm14, %xmm10, %xmm22
+
+// CHECK: vmulss (%rcx), %xmm10, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x2e,0x08,0x59,0x31]
+          vmulss (%rcx), %xmm10, %xmm22
+
+// CHECK: vmulss 291(%rax,%r14,8), %xmm10, %xmm22
+// CHECK:  encoding: [0x62,0xa1,0x2e,0x08,0x59,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vmulss 291(%rax,%r14,8), %xmm10, %xmm22
+
+// CHECK: vmulss 508(%rdx), %xmm10, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x2e,0x08,0x59,0x72,0x7f]
+          vmulss 508(%rdx), %xmm10, %xmm22
+
+// CHECK: vmulss 512(%rdx), %xmm10, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x2e,0x08,0x59,0xb2,0x00,0x02,0x00,0x00]
+          vmulss 512(%rdx), %xmm10, %xmm22
+
+// CHECK: vmulss -512(%rdx), %xmm10, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x2e,0x08,0x59,0x72,0x80]
+          vmulss -512(%rdx), %xmm10, %xmm22
+
+// CHECK: vmulss -516(%rdx), %xmm10, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x2e,0x08,0x59,0xb2,0xfc,0xfd,0xff,0xff]
+          vmulss -516(%rdx), %xmm10, %xmm22
+
+// CHECK: vpslld %xmm3, %zmm6, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x48,0xf2,0xcb]
+          vpslld %xmm3, %zmm6, %zmm17
+
+// CHECK: vpslld %xmm3, %zmm6, %zmm17 {%k3}
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x4b,0xf2,0xcb]
+          vpslld %xmm3, %zmm6, %zmm17 {%k3}
+
+// CHECK: vpslld %xmm3, %zmm6, %zmm17 {%k3} {z}
+// CHECK:  encoding: [0x62,0xe1,0x4d,0xcb,0xf2,0xcb]
+          vpslld %xmm3, %zmm6, %zmm17 {%k3} {z}
+
+// CHECK: vpslld (%rcx), %zmm6, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x48,0xf2,0x09]
+          vpslld (%rcx), %zmm6, %zmm17
+
+// CHECK: vpslld 291(%rax,%r14,8), %zmm6, %zmm17
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x48,0xf2,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpslld 291(%rax,%r14,8), %zmm6, %zmm17
+
+// CHECK: vpslld 2032(%rdx), %zmm6, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x48,0xf2,0x4a,0x7f]
+          vpslld 2032(%rdx), %zmm6, %zmm17
+
+// CHECK: vpslld 2048(%rdx), %zmm6, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x48,0xf2,0x8a,0x00,0x08,0x00,0x00]
+          vpslld 2048(%rdx), %zmm6, %zmm17
+
+// CHECK: vpslld -2048(%rdx), %zmm6, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x48,0xf2,0x4a,0x80]
+          vpslld -2048(%rdx), %zmm6, %zmm17
+
+// CHECK: vpslld -2064(%rdx), %zmm6, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x48,0xf2,0x8a,0xf0,0xf7,0xff,0xff]
+          vpslld -2064(%rdx), %zmm6, %zmm17
+
+// CHECK: vpsllq %xmm23, %zmm17, %zmm26
+// CHECK:  encoding: [0x62,0x21,0xf5,0x40,0xf3,0xd7]
+          vpsllq %xmm23, %zmm17, %zmm26
+
+// CHECK: vpsllq %xmm23, %zmm17, %zmm26 {%k6}
+// CHECK:  encoding: [0x62,0x21,0xf5,0x46,0xf3,0xd7]
+          vpsllq %xmm23, %zmm17, %zmm26 {%k6}
+
+// CHECK: vpsllq %xmm23, %zmm17, %zmm26 {%k6} {z}
+// CHECK:  encoding: [0x62,0x21,0xf5,0xc6,0xf3,0xd7]
+          vpsllq %xmm23, %zmm17, %zmm26 {%k6} {z}
+
+// CHECK: vpsllq (%rcx), %zmm17, %zmm26
+// CHECK:  encoding: [0x62,0x61,0xf5,0x40,0xf3,0x11]
+          vpsllq (%rcx), %zmm17, %zmm26
+
+// CHECK: vpsllq 291(%rax,%r14,8), %zmm17, %zmm26
+// CHECK:  encoding: [0x62,0x21,0xf5,0x40,0xf3,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vpsllq 291(%rax,%r14,8), %zmm17, %zmm26
+
+// CHECK: vpsllq 2032(%rdx), %zmm17, %zmm26
+// CHECK:  encoding: [0x62,0x61,0xf5,0x40,0xf3,0x52,0x7f]
+          vpsllq 2032(%rdx), %zmm17, %zmm26
+
+// CHECK: vpsllq 2048(%rdx), %zmm17, %zmm26
+// CHECK:  encoding: [0x62,0x61,0xf5,0x40,0xf3,0x92,0x00,0x08,0x00,0x00]
+          vpsllq 2048(%rdx), %zmm17, %zmm26
+
+// CHECK: vpsllq -2048(%rdx), %zmm17, %zmm26
+// CHECK:  encoding: [0x62,0x61,0xf5,0x40,0xf3,0x52,0x80]
+          vpsllq -2048(%rdx), %zmm17, %zmm26
+
+// CHECK: vpsllq -2064(%rdx), %zmm17, %zmm26
+// CHECK:  encoding: [0x62,0x61,0xf5,0x40,0xf3,0x92,0xf0,0xf7,0xff,0xff]
+          vpsllq -2064(%rdx), %zmm17, %zmm26
+
+// CHECK: vpsllvd %zmm22, %zmm12, %zmm10
+// CHECK:  encoding: [0x62,0x32,0x1d,0x48,0x47,0xd6]
+          vpsllvd %zmm22, %zmm12, %zmm10
+
+// CHECK: vpsllvd %zmm22, %zmm12, %zmm10 {%k6}
+// CHECK:  encoding: [0x62,0x32,0x1d,0x4e,0x47,0xd6]
+          vpsllvd %zmm22, %zmm12, %zmm10 {%k6}
+
+// CHECK: vpsllvd %zmm22, %zmm12, %zmm10 {%k6} {z}
+// CHECK:  encoding: [0x62,0x32,0x1d,0xce,0x47,0xd6]
+          vpsllvd %zmm22, %zmm12, %zmm10 {%k6} {z}
+
+// CHECK: vpsllvd (%rcx), %zmm12, %zmm10
+// CHECK:  encoding: [0x62,0x72,0x1d,0x48,0x47,0x11]
+          vpsllvd (%rcx), %zmm12, %zmm10
+
+// CHECK: vpsllvd 291(%rax,%r14,8), %zmm12, %zmm10
+// CHECK:  encoding: [0x62,0x32,0x1d,0x48,0x47,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vpsllvd 291(%rax,%r14,8), %zmm12, %zmm10
+
+// CHECK: vpsllvd (%rcx){1to16}, %zmm12, %zmm10
+// CHECK:  encoding: [0x62,0x72,0x1d,0x58,0x47,0x11]
+          vpsllvd (%rcx){1to16}, %zmm12, %zmm10
+
+// CHECK: vpsllvd 8128(%rdx), %zmm12, %zmm10
+// CHECK:  encoding: [0x62,0x72,0x1d,0x48,0x47,0x52,0x7f]
+          vpsllvd 8128(%rdx), %zmm12, %zmm10
+
+// CHECK: vpsllvd 8192(%rdx), %zmm12, %zmm10
+// CHECK:  encoding: [0x62,0x72,0x1d,0x48,0x47,0x92,0x00,0x20,0x00,0x00]
+          vpsllvd 8192(%rdx), %zmm12, %zmm10
+
+// CHECK: vpsllvd -8192(%rdx), %zmm12, %zmm10
+// CHECK:  encoding: [0x62,0x72,0x1d,0x48,0x47,0x52,0x80]
+          vpsllvd -8192(%rdx), %zmm12, %zmm10
+
+// CHECK: vpsllvd -8256(%rdx), %zmm12, %zmm10
+// CHECK:  encoding: [0x62,0x72,0x1d,0x48,0x47,0x92,0xc0,0xdf,0xff,0xff]
+          vpsllvd -8256(%rdx), %zmm12, %zmm10
+
+// CHECK: vpsllvd 508(%rdx){1to16}, %zmm12, %zmm10
+// CHECK:  encoding: [0x62,0x72,0x1d,0x58,0x47,0x52,0x7f]
+          vpsllvd 508(%rdx){1to16}, %zmm12, %zmm10
+
+// CHECK: vpsllvd 512(%rdx){1to16}, %zmm12, %zmm10
+// CHECK:  encoding: [0x62,0x72,0x1d,0x58,0x47,0x92,0x00,0x02,0x00,0x00]
+          vpsllvd 512(%rdx){1to16}, %zmm12, %zmm10
+
+// CHECK: vpsllvd -512(%rdx){1to16}, %zmm12, %zmm10
+// CHECK:  encoding: [0x62,0x72,0x1d,0x58,0x47,0x52,0x80]
+          vpsllvd -512(%rdx){1to16}, %zmm12, %zmm10
+
+// CHECK: vpsllvd -516(%rdx){1to16}, %zmm12, %zmm10
+// CHECK:  encoding: [0x62,0x72,0x1d,0x58,0x47,0x92,0xfc,0xfd,0xff,0xff]
+          vpsllvd -516(%rdx){1to16}, %zmm12, %zmm10
+
+// CHECK: vpsllvq %zmm26, %zmm5, %zmm16
+// CHECK:  encoding: [0x62,0x82,0xd5,0x48,0x47,0xc2]
+          vpsllvq %zmm26, %zmm5, %zmm16
+
+// CHECK: vpsllvq %zmm26, %zmm5, %zmm16 {%k5}
+// CHECK:  encoding: [0x62,0x82,0xd5,0x4d,0x47,0xc2]
+          vpsllvq %zmm26, %zmm5, %zmm16 {%k5}
+
+// CHECK: vpsllvq %zmm26, %zmm5, %zmm16 {%k5} {z}
+// CHECK:  encoding: [0x62,0x82,0xd5,0xcd,0x47,0xc2]
+          vpsllvq %zmm26, %zmm5, %zmm16 {%k5} {z}
+
+// CHECK: vpsllvq (%rcx), %zmm5, %zmm16
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x48,0x47,0x01]
+          vpsllvq (%rcx), %zmm5, %zmm16
+
+// CHECK: vpsllvq 291(%rax,%r14,8), %zmm5, %zmm16
+// CHECK:  encoding: [0x62,0xa2,0xd5,0x48,0x47,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vpsllvq 291(%rax,%r14,8), %zmm5, %zmm16
+
+// CHECK: vpsllvq (%rcx){1to8}, %zmm5, %zmm16
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x58,0x47,0x01]
+          vpsllvq (%rcx){1to8}, %zmm5, %zmm16
+
+// CHECK: vpsllvq 8128(%rdx), %zmm5, %zmm16
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x48,0x47,0x42,0x7f]
+          vpsllvq 8128(%rdx), %zmm5, %zmm16
+
+// CHECK: vpsllvq 8192(%rdx), %zmm5, %zmm16
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x48,0x47,0x82,0x00,0x20,0x00,0x00]
+          vpsllvq 8192(%rdx), %zmm5, %zmm16
+
+// CHECK: vpsllvq -8192(%rdx), %zmm5, %zmm16
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x48,0x47,0x42,0x80]
+          vpsllvq -8192(%rdx), %zmm5, %zmm16
+
+// CHECK: vpsllvq -8256(%rdx), %zmm5, %zmm16
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x48,0x47,0x82,0xc0,0xdf,0xff,0xff]
+          vpsllvq -8256(%rdx), %zmm5, %zmm16
+
+// CHECK: vpsllvq 1016(%rdx){1to8}, %zmm5, %zmm16
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x58,0x47,0x42,0x7f]
+          vpsllvq 1016(%rdx){1to8}, %zmm5, %zmm16
+
+// CHECK: vpsllvq 1024(%rdx){1to8}, %zmm5, %zmm16
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x58,0x47,0x82,0x00,0x04,0x00,0x00]
+          vpsllvq 1024(%rdx){1to8}, %zmm5, %zmm16
+
+// CHECK: vpsllvq -1024(%rdx){1to8}, %zmm5, %zmm16
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x58,0x47,0x42,0x80]
+          vpsllvq -1024(%rdx){1to8}, %zmm5, %zmm16
+
+// CHECK: vpsllvq -1032(%rdx){1to8}, %zmm5, %zmm16
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x58,0x47,0x82,0xf8,0xfb,0xff,0xff]
+          vpsllvq -1032(%rdx){1to8}, %zmm5, %zmm16
+
+// CHECK: vpsrad %xmm6, %zmm14, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x0d,0x48,0xe2,0xd6]
+          vpsrad %xmm6, %zmm14, %zmm18
+
+// CHECK: vpsrad %xmm6, %zmm14, %zmm18 {%k1}
+// CHECK:  encoding: [0x62,0xe1,0x0d,0x49,0xe2,0xd6]
+          vpsrad %xmm6, %zmm14, %zmm18 {%k1}
+
+// CHECK: vpsrad %xmm6, %zmm14, %zmm18 {%k1} {z}
+// CHECK:  encoding: [0x62,0xe1,0x0d,0xc9,0xe2,0xd6]
+          vpsrad %xmm6, %zmm14, %zmm18 {%k1} {z}
+
+// CHECK: vpsrad (%rcx), %zmm14, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x0d,0x48,0xe2,0x11]
+          vpsrad (%rcx), %zmm14, %zmm18
+
+// CHECK: vpsrad 291(%rax,%r14,8), %zmm14, %zmm18
+// CHECK:  encoding: [0x62,0xa1,0x0d,0x48,0xe2,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vpsrad 291(%rax,%r14,8), %zmm14, %zmm18
+
+// CHECK: vpsrad 2032(%rdx), %zmm14, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x0d,0x48,0xe2,0x52,0x7f]
+          vpsrad 2032(%rdx), %zmm14, %zmm18
+
+// CHECK: vpsrad 2048(%rdx), %zmm14, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x0d,0x48,0xe2,0x92,0x00,0x08,0x00,0x00]
+          vpsrad 2048(%rdx), %zmm14, %zmm18
+
+// CHECK: vpsrad -2048(%rdx), %zmm14, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x0d,0x48,0xe2,0x52,0x80]
+          vpsrad -2048(%rdx), %zmm14, %zmm18
+
+// CHECK: vpsrad -2064(%rdx), %zmm14, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x0d,0x48,0xe2,0x92,0xf0,0xf7,0xff,0xff]
+          vpsrad -2064(%rdx), %zmm14, %zmm18
+
+// CHECK: vpsraq %xmm22, %zmm17, %zmm21
+// CHECK:  encoding: [0x62,0xa1,0xf5,0x40,0xe2,0xee]
+          vpsraq %xmm22, %zmm17, %zmm21
+
+// CHECK: vpsraq %xmm22, %zmm17, %zmm21 {%k3}
+// CHECK:  encoding: [0x62,0xa1,0xf5,0x43,0xe2,0xee]
+          vpsraq %xmm22, %zmm17, %zmm21 {%k3}
+
+// CHECK: vpsraq %xmm22, %zmm17, %zmm21 {%k3} {z}
+// CHECK:  encoding: [0x62,0xa1,0xf5,0xc3,0xe2,0xee]
+          vpsraq %xmm22, %zmm17, %zmm21 {%k3} {z}
+
+// CHECK: vpsraq (%rcx), %zmm17, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0xf5,0x40,0xe2,0x29]
+          vpsraq (%rcx), %zmm17, %zmm21
+
+// CHECK: vpsraq 291(%rax,%r14,8), %zmm17, %zmm21
+// CHECK:  encoding: [0x62,0xa1,0xf5,0x40,0xe2,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpsraq 291(%rax,%r14,8), %zmm17, %zmm21
+
+// CHECK: vpsraq 2032(%rdx), %zmm17, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0xf5,0x40,0xe2,0x6a,0x7f]
+          vpsraq 2032(%rdx), %zmm17, %zmm21
+
+// CHECK: vpsraq 2048(%rdx), %zmm17, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0xf5,0x40,0xe2,0xaa,0x00,0x08,0x00,0x00]
+          vpsraq 2048(%rdx), %zmm17, %zmm21
+
+// CHECK: vpsraq -2048(%rdx), %zmm17, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0xf5,0x40,0xe2,0x6a,0x80]
+          vpsraq -2048(%rdx), %zmm17, %zmm21
+
+// CHECK: vpsraq -2064(%rdx), %zmm17, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0xf5,0x40,0xe2,0xaa,0xf0,0xf7,0xff,0xff]
+          vpsraq -2064(%rdx), %zmm17, %zmm21
+
+// CHECK: vpsravd %zmm17, %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x22,0x15,0x40,0x46,0xe9]
+          vpsravd %zmm17, %zmm29, %zmm29
+
+// CHECK: vpsravd %zmm17, %zmm29, %zmm29 {%k2}
+// CHECK:  encoding: [0x62,0x22,0x15,0x42,0x46,0xe9]
+          vpsravd %zmm17, %zmm29, %zmm29 {%k2}
+
+// CHECK: vpsravd %zmm17, %zmm29, %zmm29 {%k2} {z}
+// CHECK:  encoding: [0x62,0x22,0x15,0xc2,0x46,0xe9]
+          vpsravd %zmm17, %zmm29, %zmm29 {%k2} {z}
+
+// CHECK: vpsravd (%rcx), %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x62,0x15,0x40,0x46,0x29]
+          vpsravd (%rcx), %zmm29, %zmm29
+
+// CHECK: vpsravd 291(%rax,%r14,8), %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x22,0x15,0x40,0x46,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpsravd 291(%rax,%r14,8), %zmm29, %zmm29
+
+// CHECK: vpsravd (%rcx){1to16}, %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x62,0x15,0x50,0x46,0x29]
+          vpsravd (%rcx){1to16}, %zmm29, %zmm29
+
+// CHECK: vpsravd 8128(%rdx), %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x62,0x15,0x40,0x46,0x6a,0x7f]
+          vpsravd 8128(%rdx), %zmm29, %zmm29
+
+// CHECK: vpsravd 8192(%rdx), %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x62,0x15,0x40,0x46,0xaa,0x00,0x20,0x00,0x00]
+          vpsravd 8192(%rdx), %zmm29, %zmm29
+
+// CHECK: vpsravd -8192(%rdx), %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x62,0x15,0x40,0x46,0x6a,0x80]
+          vpsravd -8192(%rdx), %zmm29, %zmm29
+
+// CHECK: vpsravd -8256(%rdx), %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x62,0x15,0x40,0x46,0xaa,0xc0,0xdf,0xff,0xff]
+          vpsravd -8256(%rdx), %zmm29, %zmm29
+
+// CHECK: vpsravd 508(%rdx){1to16}, %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x62,0x15,0x50,0x46,0x6a,0x7f]
+          vpsravd 508(%rdx){1to16}, %zmm29, %zmm29
+
+// CHECK: vpsravd 512(%rdx){1to16}, %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x62,0x15,0x50,0x46,0xaa,0x00,0x02,0x00,0x00]
+          vpsravd 512(%rdx){1to16}, %zmm29, %zmm29
+
+// CHECK: vpsravd -512(%rdx){1to16}, %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x62,0x15,0x50,0x46,0x6a,0x80]
+          vpsravd -512(%rdx){1to16}, %zmm29, %zmm29
+
+// CHECK: vpsravd -516(%rdx){1to16}, %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x62,0x15,0x50,0x46,0xaa,0xfc,0xfd,0xff,0xff]
+          vpsravd -516(%rdx){1to16}, %zmm29, %zmm29
+
+// CHECK: vpsravq %zmm2, %zmm20, %zmm22
+// CHECK:  encoding: [0x62,0xe2,0xdd,0x40,0x46,0xf2]
+          vpsravq %zmm2, %zmm20, %zmm22
+
+// CHECK: vpsravq %zmm2, %zmm20, %zmm22 {%k2}
+// CHECK:  encoding: [0x62,0xe2,0xdd,0x42,0x46,0xf2]
+          vpsravq %zmm2, %zmm20, %zmm22 {%k2}
+
+// CHECK: vpsravq %zmm2, %zmm20, %zmm22 {%k2} {z}
+// CHECK:  encoding: [0x62,0xe2,0xdd,0xc2,0x46,0xf2]
+          vpsravq %zmm2, %zmm20, %zmm22 {%k2} {z}
+
+// CHECK: vpsravq (%rcx), %zmm20, %zmm22
+// CHECK:  encoding: [0x62,0xe2,0xdd,0x40,0x46,0x31]
+          vpsravq (%rcx), %zmm20, %zmm22
+
+// CHECK: vpsravq 291(%rax,%r14,8), %zmm20, %zmm22
+// CHECK:  encoding: [0x62,0xa2,0xdd,0x40,0x46,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpsravq 291(%rax,%r14,8), %zmm20, %zmm22
+
+// CHECK: vpsravq (%rcx){1to8}, %zmm20, %zmm22
+// CHECK:  encoding: [0x62,0xe2,0xdd,0x50,0x46,0x31]
+          vpsravq (%rcx){1to8}, %zmm20, %zmm22
+
+// CHECK: vpsravq 8128(%rdx), %zmm20, %zmm22
+// CHECK:  encoding: [0x62,0xe2,0xdd,0x40,0x46,0x72,0x7f]
+          vpsravq 8128(%rdx), %zmm20, %zmm22
+
+// CHECK: vpsravq 8192(%rdx), %zmm20, %zmm22
+// CHECK:  encoding: [0x62,0xe2,0xdd,0x40,0x46,0xb2,0x00,0x20,0x00,0x00]
+          vpsravq 8192(%rdx), %zmm20, %zmm22
+
+// CHECK: vpsravq -8192(%rdx), %zmm20, %zmm22
+// CHECK:  encoding: [0x62,0xe2,0xdd,0x40,0x46,0x72,0x80]
+          vpsravq -8192(%rdx), %zmm20, %zmm22
+
+// CHECK: vpsravq -8256(%rdx), %zmm20, %zmm22
+// CHECK:  encoding: [0x62,0xe2,0xdd,0x40,0x46,0xb2,0xc0,0xdf,0xff,0xff]
+          vpsravq -8256(%rdx), %zmm20, %zmm22
+
+// CHECK: vpsravq 1016(%rdx){1to8}, %zmm20, %zmm22
+// CHECK:  encoding: [0x62,0xe2,0xdd,0x50,0x46,0x72,0x7f]
+          vpsravq 1016(%rdx){1to8}, %zmm20, %zmm22
+
+// CHECK: vpsravq 1024(%rdx){1to8}, %zmm20, %zmm22
+// CHECK:  encoding: [0x62,0xe2,0xdd,0x50,0x46,0xb2,0x00,0x04,0x00,0x00]
+          vpsravq 1024(%rdx){1to8}, %zmm20, %zmm22
+
+// CHECK: vpsravq -1024(%rdx){1to8}, %zmm20, %zmm22
+// CHECK:  encoding: [0x62,0xe2,0xdd,0x50,0x46,0x72,0x80]
+          vpsravq -1024(%rdx){1to8}, %zmm20, %zmm22
+
+// CHECK: vpsravq -1032(%rdx){1to8}, %zmm20, %zmm22
+// CHECK:  encoding: [0x62,0xe2,0xdd,0x50,0x46,0xb2,0xf8,0xfb,0xff,0xff]
+          vpsravq -1032(%rdx){1to8}, %zmm20, %zmm22
+
+// CHECK: vpsrld %xmm25, %zmm17, %zmm1
+// CHECK:  encoding: [0x62,0x91,0x75,0x40,0xd2,0xc9]
+          vpsrld %xmm25, %zmm17, %zmm1
+
+// CHECK: vpsrld %xmm25, %zmm17, %zmm1 {%k4}
+// CHECK:  encoding: [0x62,0x91,0x75,0x44,0xd2,0xc9]
+          vpsrld %xmm25, %zmm17, %zmm1 {%k4}
+
+// CHECK: vpsrld %xmm25, %zmm17, %zmm1 {%k4} {z}
+// CHECK:  encoding: [0x62,0x91,0x75,0xc4,0xd2,0xc9]
+          vpsrld %xmm25, %zmm17, %zmm1 {%k4} {z}
+
+// CHECK: vpsrld (%rcx), %zmm17, %zmm1
+// CHECK:  encoding: [0x62,0xf1,0x75,0x40,0xd2,0x09]
+          vpsrld (%rcx), %zmm17, %zmm1
+
+// CHECK: vpsrld 291(%rax,%r14,8), %zmm17, %zmm1
+// CHECK:  encoding: [0x62,0xb1,0x75,0x40,0xd2,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpsrld 291(%rax,%r14,8), %zmm17, %zmm1
+
+// CHECK: vpsrld 2032(%rdx), %zmm17, %zmm1
+// CHECK:  encoding: [0x62,0xf1,0x75,0x40,0xd2,0x4a,0x7f]
+          vpsrld 2032(%rdx), %zmm17, %zmm1
+
+// CHECK: vpsrld 2048(%rdx), %zmm17, %zmm1
+// CHECK:  encoding: [0x62,0xf1,0x75,0x40,0xd2,0x8a,0x00,0x08,0x00,0x00]
+          vpsrld 2048(%rdx), %zmm17, %zmm1
+
+// CHECK: vpsrld -2048(%rdx), %zmm17, %zmm1
+// CHECK:  encoding: [0x62,0xf1,0x75,0x40,0xd2,0x4a,0x80]
+          vpsrld -2048(%rdx), %zmm17, %zmm1
+
+// CHECK: vpsrld -2064(%rdx), %zmm17, %zmm1
+// CHECK:  encoding: [0x62,0xf1,0x75,0x40,0xd2,0x8a,0xf0,0xf7,0xff,0xff]
+          vpsrld -2064(%rdx), %zmm17, %zmm1
+
+// CHECK: vpsrlq %xmm3, %zmm11, %zmm9
+// CHECK:  encoding: [0x62,0x71,0xa5,0x48,0xd3,0xcb]
+          vpsrlq %xmm3, %zmm11, %zmm9
+
+// CHECK: vpsrlq %xmm3, %zmm11, %zmm9 {%k5}
+// CHECK:  encoding: [0x62,0x71,0xa5,0x4d,0xd3,0xcb]
+          vpsrlq %xmm3, %zmm11, %zmm9 {%k5}
+
+// CHECK: vpsrlq %xmm3, %zmm11, %zmm9 {%k5} {z}
+// CHECK:  encoding: [0x62,0x71,0xa5,0xcd,0xd3,0xcb]
+          vpsrlq %xmm3, %zmm11, %zmm9 {%k5} {z}
+
+// CHECK: vpsrlq (%rcx), %zmm11, %zmm9
+// CHECK:  encoding: [0x62,0x71,0xa5,0x48,0xd3,0x09]
+          vpsrlq (%rcx), %zmm11, %zmm9
+
+// CHECK: vpsrlq 291(%rax,%r14,8), %zmm11, %zmm9
+// CHECK:  encoding: [0x62,0x31,0xa5,0x48,0xd3,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpsrlq 291(%rax,%r14,8), %zmm11, %zmm9
+
+// CHECK: vpsrlq 2032(%rdx), %zmm11, %zmm9
+// CHECK:  encoding: [0x62,0x71,0xa5,0x48,0xd3,0x4a,0x7f]
+          vpsrlq 2032(%rdx), %zmm11, %zmm9
+
+// CHECK: vpsrlq 2048(%rdx), %zmm11, %zmm9
+// CHECK:  encoding: [0x62,0x71,0xa5,0x48,0xd3,0x8a,0x00,0x08,0x00,0x00]
+          vpsrlq 2048(%rdx), %zmm11, %zmm9
+
+// CHECK: vpsrlq -2048(%rdx), %zmm11, %zmm9
+// CHECK:  encoding: [0x62,0x71,0xa5,0x48,0xd3,0x4a,0x80]
+          vpsrlq -2048(%rdx), %zmm11, %zmm9
+
+// CHECK: vpsrlq -2064(%rdx), %zmm11, %zmm9
+// CHECK:  encoding: [0x62,0x71,0xa5,0x48,0xd3,0x8a,0xf0,0xf7,0xff,0xff]
+          vpsrlq -2064(%rdx), %zmm11, %zmm9
+
+// CHECK: vpsrlvd %zmm28, %zmm14, %zmm8
+// CHECK:  encoding: [0x62,0x12,0x0d,0x48,0x45,0xc4]
+          vpsrlvd %zmm28, %zmm14, %zmm8
+
+// CHECK: vpsrlvd %zmm28, %zmm14, %zmm8 {%k4}
+// CHECK:  encoding: [0x62,0x12,0x0d,0x4c,0x45,0xc4]
+          vpsrlvd %zmm28, %zmm14, %zmm8 {%k4}
+
+// CHECK: vpsrlvd %zmm28, %zmm14, %zmm8 {%k4} {z}
+// CHECK:  encoding: [0x62,0x12,0x0d,0xcc,0x45,0xc4]
+          vpsrlvd %zmm28, %zmm14, %zmm8 {%k4} {z}
+
+// CHECK: vpsrlvd (%rcx), %zmm14, %zmm8
+// CHECK:  encoding: [0x62,0x72,0x0d,0x48,0x45,0x01]
+          vpsrlvd (%rcx), %zmm14, %zmm8
+
+// CHECK: vpsrlvd 291(%rax,%r14,8), %zmm14, %zmm8
+// CHECK:  encoding: [0x62,0x32,0x0d,0x48,0x45,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vpsrlvd 291(%rax,%r14,8), %zmm14, %zmm8
+
+// CHECK: vpsrlvd (%rcx){1to16}, %zmm14, %zmm8
+// CHECK:  encoding: [0x62,0x72,0x0d,0x58,0x45,0x01]
+          vpsrlvd (%rcx){1to16}, %zmm14, %zmm8
+
+// CHECK: vpsrlvd 8128(%rdx), %zmm14, %zmm8
+// CHECK:  encoding: [0x62,0x72,0x0d,0x48,0x45,0x42,0x7f]
+          vpsrlvd 8128(%rdx), %zmm14, %zmm8
+
+// CHECK: vpsrlvd 8192(%rdx), %zmm14, %zmm8
+// CHECK:  encoding: [0x62,0x72,0x0d,0x48,0x45,0x82,0x00,0x20,0x00,0x00]
+          vpsrlvd 8192(%rdx), %zmm14, %zmm8
+
+// CHECK: vpsrlvd -8192(%rdx), %zmm14, %zmm8
+// CHECK:  encoding: [0x62,0x72,0x0d,0x48,0x45,0x42,0x80]
+          vpsrlvd -8192(%rdx), %zmm14, %zmm8
+
+// CHECK: vpsrlvd -8256(%rdx), %zmm14, %zmm8
+// CHECK:  encoding: [0x62,0x72,0x0d,0x48,0x45,0x82,0xc0,0xdf,0xff,0xff]
+          vpsrlvd -8256(%rdx), %zmm14, %zmm8
+
+// CHECK: vpsrlvd 508(%rdx){1to16}, %zmm14, %zmm8
+// CHECK:  encoding: [0x62,0x72,0x0d,0x58,0x45,0x42,0x7f]
+          vpsrlvd 508(%rdx){1to16}, %zmm14, %zmm8
+
+// CHECK: vpsrlvd 512(%rdx){1to16}, %zmm14, %zmm8
+// CHECK:  encoding: [0x62,0x72,0x0d,0x58,0x45,0x82,0x00,0x02,0x00,0x00]
+          vpsrlvd 512(%rdx){1to16}, %zmm14, %zmm8
+
+// CHECK: vpsrlvd -512(%rdx){1to16}, %zmm14, %zmm8
+// CHECK:  encoding: [0x62,0x72,0x0d,0x58,0x45,0x42,0x80]
+          vpsrlvd -512(%rdx){1to16}, %zmm14, %zmm8
+
+// CHECK: vpsrlvd -516(%rdx){1to16}, %zmm14, %zmm8
+// CHECK:  encoding: [0x62,0x72,0x0d,0x58,0x45,0x82,0xfc,0xfd,0xff,0xff]
+          vpsrlvd -516(%rdx){1to16}, %zmm14, %zmm8
+
+// CHECK: vpsrlvq %zmm26, %zmm7, %zmm20
+// CHECK:  encoding: [0x62,0x82,0xc5,0x48,0x45,0xe2]
+          vpsrlvq %zmm26, %zmm7, %zmm20
+
+// CHECK: vpsrlvq %zmm26, %zmm7, %zmm20 {%k5}
+// CHECK:  encoding: [0x62,0x82,0xc5,0x4d,0x45,0xe2]
+          vpsrlvq %zmm26, %zmm7, %zmm20 {%k5}
+
+// CHECK: vpsrlvq %zmm26, %zmm7, %zmm20 {%k5} {z}
+// CHECK:  encoding: [0x62,0x82,0xc5,0xcd,0x45,0xe2]
+          vpsrlvq %zmm26, %zmm7, %zmm20 {%k5} {z}
+
+// CHECK: vpsrlvq (%rcx), %zmm7, %zmm20
+// CHECK:  encoding: [0x62,0xe2,0xc5,0x48,0x45,0x21]
+          vpsrlvq (%rcx), %zmm7, %zmm20
+
+// CHECK: vpsrlvq 291(%rax,%r14,8), %zmm7, %zmm20
+// CHECK:  encoding: [0x62,0xa2,0xc5,0x48,0x45,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsrlvq 291(%rax,%r14,8), %zmm7, %zmm20
+
+// CHECK: vpsrlvq (%rcx){1to8}, %zmm7, %zmm20
+// CHECK:  encoding: [0x62,0xe2,0xc5,0x58,0x45,0x21]
+          vpsrlvq (%rcx){1to8}, %zmm7, %zmm20
+
+// CHECK: vpsrlvq 8128(%rdx), %zmm7, %zmm20
+// CHECK:  encoding: [0x62,0xe2,0xc5,0x48,0x45,0x62,0x7f]
+          vpsrlvq 8128(%rdx), %zmm7, %zmm20
+
+// CHECK: vpsrlvq 8192(%rdx), %zmm7, %zmm20
+// CHECK:  encoding: [0x62,0xe2,0xc5,0x48,0x45,0xa2,0x00,0x20,0x00,0x00]
+          vpsrlvq 8192(%rdx), %zmm7, %zmm20
+
+// CHECK: vpsrlvq -8192(%rdx), %zmm7, %zmm20
+// CHECK:  encoding: [0x62,0xe2,0xc5,0x48,0x45,0x62,0x80]
+          vpsrlvq -8192(%rdx), %zmm7, %zmm20
+
+// CHECK: vpsrlvq -8256(%rdx), %zmm7, %zmm20
+// CHECK:  encoding: [0x62,0xe2,0xc5,0x48,0x45,0xa2,0xc0,0xdf,0xff,0xff]
+          vpsrlvq -8256(%rdx), %zmm7, %zmm20
+
+// CHECK: vpsrlvq 1016(%rdx){1to8}, %zmm7, %zmm20
+// CHECK:  encoding: [0x62,0xe2,0xc5,0x58,0x45,0x62,0x7f]
+          vpsrlvq 1016(%rdx){1to8}, %zmm7, %zmm20
+
+// CHECK: vpsrlvq 1024(%rdx){1to8}, %zmm7, %zmm20
+// CHECK:  encoding: [0x62,0xe2,0xc5,0x58,0x45,0xa2,0x00,0x04,0x00,0x00]
+          vpsrlvq 1024(%rdx){1to8}, %zmm7, %zmm20
+
+// CHECK: vpsrlvq -1024(%rdx){1to8}, %zmm7, %zmm20
+// CHECK:  encoding: [0x62,0xe2,0xc5,0x58,0x45,0x62,0x80]
+          vpsrlvq -1024(%rdx){1to8}, %zmm7, %zmm20
+
+// CHECK: vpsrlvq -1032(%rdx){1to8}, %zmm7, %zmm20
+// CHECK:  encoding: [0x62,0xe2,0xc5,0x58,0x45,0xa2,0xf8,0xfb,0xff,0xff]
+          vpsrlvq -1032(%rdx){1to8}, %zmm7, %zmm20
+
+// CHECK: vpsrld $171, %zmm5, %zmm3
+// CHECK:  encoding: [0x62,0xf1,0x65,0x48,0x72,0xd5,0xab]
+          vpsrld $171, %zmm5, %zmm3
+
+// CHECK: vpsrld $171, %zmm5, %zmm3 {%k4}
+// CHECK:  encoding: [0x62,0xf1,0x65,0x4c,0x72,0xd5,0xab]
+          vpsrld $171, %zmm5, %zmm3 {%k4}
+
+// CHECK: vpsrld $171, %zmm5, %zmm3 {%k4} {z}
+// CHECK:  encoding: [0x62,0xf1,0x65,0xcc,0x72,0xd5,0xab]
+          vpsrld $171, %zmm5, %zmm3 {%k4} {z}
+
+// CHECK: vpsrld $123, %zmm5, %zmm3
+// CHECK:  encoding: [0x62,0xf1,0x65,0x48,0x72,0xd5,0x7b]
+          vpsrld $123, %zmm5, %zmm3
+
+// CHECK: vpsrld $123, (%rcx), %zmm3
+// CHECK:  encoding: [0x62,0xf1,0x65,0x48,0x72,0x11,0x7b]
+          vpsrld $123, (%rcx), %zmm3
+
+// CHECK: vpsrld $123, 291(%rax,%r14,8), %zmm3
+// CHECK:  encoding: [0x62,0xb1,0x65,0x48,0x72,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpsrld $123, 291(%rax,%r14,8), %zmm3
+
+// CHECK: vpsrld $123, (%rcx){1to16}, %zmm3
+// CHECK:  encoding: [0x62,0xf1,0x65,0x58,0x72,0x11,0x7b]
+          vpsrld $123, (%rcx){1to16}, %zmm3
+
+// CHECK: vpsrld $123, 8128(%rdx), %zmm3
+// CHECK:  encoding: [0x62,0xf1,0x65,0x48,0x72,0x52,0x7f,0x7b]
+          vpsrld $123, 8128(%rdx), %zmm3
+
+// CHECK: vpsrld $123, 8192(%rdx), %zmm3
+// CHECK:  encoding: [0x62,0xf1,0x65,0x48,0x72,0x92,0x00,0x20,0x00,0x00,0x7b]
+          vpsrld $123, 8192(%rdx), %zmm3
+
+// CHECK: vpsrld $123, -8192(%rdx), %zmm3
+// CHECK:  encoding: [0x62,0xf1,0x65,0x48,0x72,0x52,0x80,0x7b]
+          vpsrld $123, -8192(%rdx), %zmm3
+
+// CHECK: vpsrld $123, -8256(%rdx), %zmm3
+// CHECK:  encoding: [0x62,0xf1,0x65,0x48,0x72,0x92,0xc0,0xdf,0xff,0xff,0x7b]
+          vpsrld $123, -8256(%rdx), %zmm3
+
+// CHECK: vpsrld $123, 508(%rdx){1to16}, %zmm3
+// CHECK:  encoding: [0x62,0xf1,0x65,0x58,0x72,0x52,0x7f,0x7b]
+          vpsrld $123, 508(%rdx){1to16}, %zmm3
+
+// CHECK: vpsrld $123, 512(%rdx){1to16}, %zmm3
+// CHECK:  encoding: [0x62,0xf1,0x65,0x58,0x72,0x92,0x00,0x02,0x00,0x00,0x7b]
+          vpsrld $123, 512(%rdx){1to16}, %zmm3
+
+// CHECK: vpsrld $123, -512(%rdx){1to16}, %zmm3
+// CHECK:  encoding: [0x62,0xf1,0x65,0x58,0x72,0x52,0x80,0x7b]
+          vpsrld $123, -512(%rdx){1to16}, %zmm3
+
+// CHECK: vpsrld $123, -516(%rdx){1to16}, %zmm3
+// CHECK:  encoding: [0x62,0xf1,0x65,0x58,0x72,0x92,0xfc,0xfd,0xff,0xff,0x7b]
+          vpsrld $123, -516(%rdx){1to16}, %zmm3
+
+// CHECK: vpsrlq $171, %zmm25, %zmm18
+// CHECK:  encoding: [0x62,0x91,0xed,0x40,0x73,0xd1,0xab]
+          vpsrlq $171, %zmm25, %zmm18
+
+// CHECK: vpsrlq $171, %zmm25, %zmm18 {%k1}
+// CHECK:  encoding: [0x62,0x91,0xed,0x41,0x73,0xd1,0xab]
+          vpsrlq $171, %zmm25, %zmm18 {%k1}
+
+// CHECK: vpsrlq $171, %zmm25, %zmm18 {%k1} {z}
+// CHECK:  encoding: [0x62,0x91,0xed,0xc1,0x73,0xd1,0xab]
+          vpsrlq $171, %zmm25, %zmm18 {%k1} {z}
+
+// CHECK: vpsrlq $123, %zmm25, %zmm18
+// CHECK:  encoding: [0x62,0x91,0xed,0x40,0x73,0xd1,0x7b]
+          vpsrlq $123, %zmm25, %zmm18
+
+// CHECK: vpsrlq $123, (%rcx), %zmm18
+// CHECK:  encoding: [0x62,0xf1,0xed,0x40,0x73,0x11,0x7b]
+          vpsrlq $123, (%rcx), %zmm18
+
+// CHECK: vpsrlq $123, 291(%rax,%r14,8), %zmm18
+// CHECK:  encoding: [0x62,0xb1,0xed,0x40,0x73,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpsrlq $123, 291(%rax,%r14,8), %zmm18
+
+// CHECK: vpsrlq $123, (%rcx){1to8}, %zmm18
+// CHECK:  encoding: [0x62,0xf1,0xed,0x50,0x73,0x11,0x7b]
+          vpsrlq $123, (%rcx){1to8}, %zmm18
+
+// CHECK: vpsrlq $123, 8128(%rdx), %zmm18
+// CHECK:  encoding: [0x62,0xf1,0xed,0x40,0x73,0x52,0x7f,0x7b]
+          vpsrlq $123, 8128(%rdx), %zmm18
+
+// CHECK: vpsrlq $123, 8192(%rdx), %zmm18
+// CHECK:  encoding: [0x62,0xf1,0xed,0x40,0x73,0x92,0x00,0x20,0x00,0x00,0x7b]
+          vpsrlq $123, 8192(%rdx), %zmm18
+
+// CHECK: vpsrlq $123, -8192(%rdx), %zmm18
+// CHECK:  encoding: [0x62,0xf1,0xed,0x40,0x73,0x52,0x80,0x7b]
+          vpsrlq $123, -8192(%rdx), %zmm18
+
+// CHECK: vpsrlq $123, -8256(%rdx), %zmm18
+// CHECK:  encoding: [0x62,0xf1,0xed,0x40,0x73,0x92,0xc0,0xdf,0xff,0xff,0x7b]
+          vpsrlq $123, -8256(%rdx), %zmm18
+
+// CHECK: vpsrlq $123, 1016(%rdx){1to8}, %zmm18
+// CHECK:  encoding: [0x62,0xf1,0xed,0x50,0x73,0x52,0x7f,0x7b]
+          vpsrlq $123, 1016(%rdx){1to8}, %zmm18
+
+// CHECK: vpsrlq $123, 1024(%rdx){1to8}, %zmm18
+// CHECK:  encoding: [0x62,0xf1,0xed,0x50,0x73,0x92,0x00,0x04,0x00,0x00,0x7b]
+          vpsrlq $123, 1024(%rdx){1to8}, %zmm18
+
+// CHECK: vpsrlq $123, -1024(%rdx){1to8}, %zmm18
+// CHECK:  encoding: [0x62,0xf1,0xed,0x50,0x73,0x52,0x80,0x7b]
+          vpsrlq $123, -1024(%rdx){1to8}, %zmm18
+
+// CHECK: vpsrlq $123, -1032(%rdx){1to8}, %zmm18
+// CHECK:  encoding: [0x62,0xf1,0xed,0x50,0x73,0x92,0xf8,0xfb,0xff,0xff,0x7b]
+          vpsrlq $123, -1032(%rdx){1to8}, %zmm18
+
+// CHECK: vpslld $171, %zmm24, %zmm29
+// CHECK:  encoding: [0x62,0x91,0x15,0x40,0x72,0xf0,0xab]
+          vpslld $171, %zmm24, %zmm29
+
+// CHECK: vpslld $171, %zmm24, %zmm29 {%k6}
+// CHECK:  encoding: [0x62,0x91,0x15,0x46,0x72,0xf0,0xab]
+          vpslld $171, %zmm24, %zmm29 {%k6}
+
+// CHECK: vpslld $171, %zmm24, %zmm29 {%k6} {z}
+// CHECK:  encoding: [0x62,0x91,0x15,0xc6,0x72,0xf0,0xab]
+          vpslld $171, %zmm24, %zmm29 {%k6} {z}
+
+// CHECK: vpslld $123, %zmm24, %zmm29
+// CHECK:  encoding: [0x62,0x91,0x15,0x40,0x72,0xf0,0x7b]
+          vpslld $123, %zmm24, %zmm29
+
+// CHECK: vpslld $123, (%rcx), %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x40,0x72,0x31,0x7b]
+          vpslld $123, (%rcx), %zmm29
+
+// CHECK: vpslld $123, 291(%rax,%r14,8), %zmm29
+// CHECK:  encoding: [0x62,0xb1,0x15,0x40,0x72,0xb4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpslld $123, 291(%rax,%r14,8), %zmm29
+
+// CHECK: vpslld $123, (%rcx){1to16}, %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x50,0x72,0x31,0x7b]
+          vpslld $123, (%rcx){1to16}, %zmm29
+
+// CHECK: vpslld $123, 8128(%rdx), %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x40,0x72,0x72,0x7f,0x7b]
+          vpslld $123, 8128(%rdx), %zmm29
+
+// CHECK: vpslld $123, 8192(%rdx), %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x40,0x72,0xb2,0x00,0x20,0x00,0x00,0x7b]
+          vpslld $123, 8192(%rdx), %zmm29
+
+// CHECK: vpslld $123, -8192(%rdx), %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x40,0x72,0x72,0x80,0x7b]
+          vpslld $123, -8192(%rdx), %zmm29
+
+// CHECK: vpslld $123, -8256(%rdx), %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x40,0x72,0xb2,0xc0,0xdf,0xff,0xff,0x7b]
+          vpslld $123, -8256(%rdx), %zmm29
+
+// CHECK: vpslld $123, 508(%rdx){1to16}, %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x50,0x72,0x72,0x7f,0x7b]
+          vpslld $123, 508(%rdx){1to16}, %zmm29
+
+// CHECK: vpslld $123, 512(%rdx){1to16}, %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x50,0x72,0xb2,0x00,0x02,0x00,0x00,0x7b]
+          vpslld $123, 512(%rdx){1to16}, %zmm29
+
+// CHECK: vpslld $123, -512(%rdx){1to16}, %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x50,0x72,0x72,0x80,0x7b]
+          vpslld $123, -512(%rdx){1to16}, %zmm29
+
+// CHECK: vpslld $123, -516(%rdx){1to16}, %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x50,0x72,0xb2,0xfc,0xfd,0xff,0xff,0x7b]
+          vpslld $123, -516(%rdx){1to16}, %zmm29
+
+// CHECK: vpsllq $171, %zmm11, %zmm6
+// CHECK:  encoding: [0x62,0xd1,0xcd,0x48,0x73,0xf3,0xab]
+          vpsllq $171, %zmm11, %zmm6
+
+// CHECK: vpsllq $171, %zmm11, %zmm6 {%k2}
+// CHECK:  encoding: [0x62,0xd1,0xcd,0x4a,0x73,0xf3,0xab]
+          vpsllq $171, %zmm11, %zmm6 {%k2}
+
+// CHECK: vpsllq $171, %zmm11, %zmm6 {%k2} {z}
+// CHECK:  encoding: [0x62,0xd1,0xcd,0xca,0x73,0xf3,0xab]
+          vpsllq $171, %zmm11, %zmm6 {%k2} {z}
+
+// CHECK: vpsllq $123, %zmm11, %zmm6
+// CHECK:  encoding: [0x62,0xd1,0xcd,0x48,0x73,0xf3,0x7b]
+          vpsllq $123, %zmm11, %zmm6
+
+// CHECK: vpsllq $123, (%rcx), %zmm6
+// CHECK:  encoding: [0x62,0xf1,0xcd,0x48,0x73,0x31,0x7b]
+          vpsllq $123, (%rcx), %zmm6
+
+// CHECK: vpsllq $123, 291(%rax,%r14,8), %zmm6
+// CHECK:  encoding: [0x62,0xb1,0xcd,0x48,0x73,0xb4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpsllq $123, 291(%rax,%r14,8), %zmm6
+
+// CHECK: vpsllq $123, (%rcx){1to8}, %zmm6
+// CHECK:  encoding: [0x62,0xf1,0xcd,0x58,0x73,0x31,0x7b]
+          vpsllq $123, (%rcx){1to8}, %zmm6
+
+// CHECK: vpsllq $123, 8128(%rdx), %zmm6
+// CHECK:  encoding: [0x62,0xf1,0xcd,0x48,0x73,0x72,0x7f,0x7b]
+          vpsllq $123, 8128(%rdx), %zmm6
+
+// CHECK: vpsllq $123, 8192(%rdx), %zmm6
+// CHECK:  encoding: [0x62,0xf1,0xcd,0x48,0x73,0xb2,0x00,0x20,0x00,0x00,0x7b]
+          vpsllq $123, 8192(%rdx), %zmm6
+
+// CHECK: vpsllq $123, -8192(%rdx), %zmm6
+// CHECK:  encoding: [0x62,0xf1,0xcd,0x48,0x73,0x72,0x80,0x7b]
+          vpsllq $123, -8192(%rdx), %zmm6
+
+// CHECK: vpsllq $123, -8256(%rdx), %zmm6
+// CHECK:  encoding: [0x62,0xf1,0xcd,0x48,0x73,0xb2,0xc0,0xdf,0xff,0xff,0x7b]
+          vpsllq $123, -8256(%rdx), %zmm6
+
+// CHECK: vpsllq $123, 1016(%rdx){1to8}, %zmm6
+// CHECK:  encoding: [0x62,0xf1,0xcd,0x58,0x73,0x72,0x7f,0x7b]
+          vpsllq $123, 1016(%rdx){1to8}, %zmm6
+
+// CHECK: vpsllq $123, 1024(%rdx){1to8}, %zmm6
+// CHECK:  encoding: [0x62,0xf1,0xcd,0x58,0x73,0xb2,0x00,0x04,0x00,0x00,0x7b]
+          vpsllq $123, 1024(%rdx){1to8}, %zmm6
+
+// CHECK: vpsllq $123, -1024(%rdx){1to8}, %zmm6
+// CHECK:  encoding: [0x62,0xf1,0xcd,0x58,0x73,0x72,0x80,0x7b]
+          vpsllq $123, -1024(%rdx){1to8}, %zmm6
+
+// CHECK: vpsllq $123, -1032(%rdx){1to8}, %zmm6
+// CHECK:  encoding: [0x62,0xf1,0xcd,0x58,0x73,0xb2,0xf8,0xfb,0xff,0xff,0x7b]
+          vpsllq $123, -1032(%rdx){1to8}, %zmm6
+
+// CHECK: vpsrad $171, %zmm5, %zmm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x40,0x72,0xe5,0xab]
+          vpsrad $171, %zmm5, %zmm27
+
+// CHECK: vpsrad $171, %zmm5, %zmm27 {%k5}
+// CHECK:  encoding: [0x62,0xf1,0x25,0x45,0x72,0xe5,0xab]
+          vpsrad $171, %zmm5, %zmm27 {%k5}
+
+// CHECK: vpsrad $171, %zmm5, %zmm27 {%k5} {z}
+// CHECK:  encoding: [0x62,0xf1,0x25,0xc5,0x72,0xe5,0xab]
+          vpsrad $171, %zmm5, %zmm27 {%k5} {z}
+
+// CHECK: vpsrad $123, %zmm5, %zmm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x40,0x72,0xe5,0x7b]
+          vpsrad $123, %zmm5, %zmm27
+
+// CHECK: vpsrad $123, (%rcx), %zmm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x40,0x72,0x21,0x7b]
+          vpsrad $123, (%rcx), %zmm27
+
+// CHECK: vpsrad $123, 291(%rax,%r14,8), %zmm27
+// CHECK:  encoding: [0x62,0xb1,0x25,0x40,0x72,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpsrad $123, 291(%rax,%r14,8), %zmm27
+
+// CHECK: vpsrad $123, (%rcx){1to16}, %zmm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x50,0x72,0x21,0x7b]
+          vpsrad $123, (%rcx){1to16}, %zmm27
+
+// CHECK: vpsrad $123, 8128(%rdx), %zmm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x40,0x72,0x62,0x7f,0x7b]
+          vpsrad $123, 8128(%rdx), %zmm27
+
+// CHECK: vpsrad $123, 8192(%rdx), %zmm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x40,0x72,0xa2,0x00,0x20,0x00,0x00,0x7b]
+          vpsrad $123, 8192(%rdx), %zmm27
+
+// CHECK: vpsrad $123, -8192(%rdx), %zmm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x40,0x72,0x62,0x80,0x7b]
+          vpsrad $123, -8192(%rdx), %zmm27
+
+// CHECK: vpsrad $123, -8256(%rdx), %zmm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x40,0x72,0xa2,0xc0,0xdf,0xff,0xff,0x7b]
+          vpsrad $123, -8256(%rdx), %zmm27
+
+// CHECK: vpsrad $123, 508(%rdx){1to16}, %zmm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x50,0x72,0x62,0x7f,0x7b]
+          vpsrad $123, 508(%rdx){1to16}, %zmm27
+
+// CHECK: vpsrad $123, 512(%rdx){1to16}, %zmm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x50,0x72,0xa2,0x00,0x02,0x00,0x00,0x7b]
+          vpsrad $123, 512(%rdx){1to16}, %zmm27
+
+// CHECK: vpsrad $123, -512(%rdx){1to16}, %zmm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x50,0x72,0x62,0x80,0x7b]
+          vpsrad $123, -512(%rdx){1to16}, %zmm27
+
+// CHECK: vpsrad $123, -516(%rdx){1to16}, %zmm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x50,0x72,0xa2,0xfc,0xfd,0xff,0xff,0x7b]
+          vpsrad $123, -516(%rdx){1to16}, %zmm27
+
+// CHECK: vpsraq $171, %zmm5, %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x40,0x72,0xe5,0xab]
+          vpsraq $171, %zmm5, %zmm29
+
+// CHECK: vpsraq $171, %zmm5, %zmm29 {%k4}
+// CHECK:  encoding: [0x62,0xf1,0x95,0x44,0x72,0xe5,0xab]
+          vpsraq $171, %zmm5, %zmm29 {%k4}
+
+// CHECK: vpsraq $171, %zmm5, %zmm29 {%k4} {z}
+// CHECK:  encoding: [0x62,0xf1,0x95,0xc4,0x72,0xe5,0xab]
+          vpsraq $171, %zmm5, %zmm29 {%k4} {z}
+
+// CHECK: vpsraq $123, %zmm5, %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x40,0x72,0xe5,0x7b]
+          vpsraq $123, %zmm5, %zmm29
+
+// CHECK: vpsraq $123, (%rcx), %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x40,0x72,0x21,0x7b]
+          vpsraq $123, (%rcx), %zmm29
+
+// CHECK: vpsraq $123, 291(%rax,%r14,8), %zmm29
+// CHECK:  encoding: [0x62,0xb1,0x95,0x40,0x72,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpsraq $123, 291(%rax,%r14,8), %zmm29
+
+// CHECK: vpsraq $123, (%rcx){1to8}, %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x50,0x72,0x21,0x7b]
+          vpsraq $123, (%rcx){1to8}, %zmm29
+
+// CHECK: vpsraq $123, 8128(%rdx), %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x40,0x72,0x62,0x7f,0x7b]
+          vpsraq $123, 8128(%rdx), %zmm29
+
+// CHECK: vpsraq $123, 8192(%rdx), %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x40,0x72,0xa2,0x00,0x20,0x00,0x00,0x7b]
+          vpsraq $123, 8192(%rdx), %zmm29
+
+// CHECK: vpsraq $123, -8192(%rdx), %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x40,0x72,0x62,0x80,0x7b]
+          vpsraq $123, -8192(%rdx), %zmm29
+
+// CHECK: vpsraq $123, -8256(%rdx), %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x40,0x72,0xa2,0xc0,0xdf,0xff,0xff,0x7b]
+          vpsraq $123, -8256(%rdx), %zmm29
+
+// CHECK: vpsraq $123, 1016(%rdx){1to8}, %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x50,0x72,0x62,0x7f,0x7b]
+          vpsraq $123, 1016(%rdx){1to8}, %zmm29
+
+// CHECK: vpsraq $123, 1024(%rdx){1to8}, %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x50,0x72,0xa2,0x00,0x04,0x00,0x00,0x7b]
+          vpsraq $123, 1024(%rdx){1to8}, %zmm29
+
+// CHECK: vpsraq $123, -1024(%rdx){1to8}, %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x50,0x72,0x62,0x80,0x7b]
+          vpsraq $123, -1024(%rdx){1to8}, %zmm29
+
+// CHECK: vpsraq $123, -1032(%rdx){1to8}, %zmm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x50,0x72,0xa2,0xf8,0xfb,0xff,0xff,0x7b]
+          vpsraq $123, -1032(%rdx){1to8}, %zmm29
+
diff --git a/test/MC/X86/avx512-err.s b/test/MC/X86/avx512-err.s
new file mode 100644
index 000000000000..bfe6e39ee31d
--- /dev/null
+++ b/test/MC/X86/avx512-err.s
@@ -0,0 +1,6 @@
+// RUN: not llvm-mc -triple x86_64-unknown-unknown -mcpu=knl -mattr=+avx512dq --show-encoding %s 2> %t.err
+// RUN: FileCheck --check-prefix=ERR < %t.err %s
+
+// ERR: invalid operand for instruction
+vpcmpd $1, %zmm24, %zmm7, %k5{%k0}
+
diff --git a/test/MC/X86/avx512bw-encoding.s b/test/MC/X86/avx512bw-encoding.s
index 06397fbebdf7..954e0bd6e81f 100644
--- a/test/MC/X86/avx512bw-encoding.s
+++ b/test/MC/X86/avx512bw-encoding.s
@@ -71,3 +71,212 @@
 // CHECK: vpblendmw -8256(%rdx), %zmm20, %zmm26
 // CHECK:  encoding: [0x62,0x62,0xdd,0x40,0x66,0x92,0xc0,0xdf,0xff,0xff]
           vpblendmw -8256(%rdx), %zmm20, %zmm26
+
+// CHECK: vptestmb %zmm19, %zmm17, %k5
+// CHECK:  encoding: [0x62,0xb2,0x75,0x40,0x26,0xeb]
+          vptestmb %zmm19, %zmm17, %k5
+
+// CHECK: vptestmb %zmm19, %zmm17, %k5 {%k3}
+// CHECK:  encoding: [0x62,0xb2,0x75,0x43,0x26,0xeb]
+          vptestmb %zmm19, %zmm17, %k5 {%k3}
+
+// CHECK: vptestmb (%rcx), %zmm17, %k5
+// CHECK:  encoding: [0x62,0xf2,0x75,0x40,0x26,0x29]
+          vptestmb (%rcx), %zmm17, %k5
+
+// CHECK: vptestmb 291(%rax,%r14,8), %zmm17, %k5
+// CHECK:  encoding: [0x62,0xb2,0x75,0x40,0x26,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vptestmb 291(%rax,%r14,8), %zmm17, %k5
+
+// CHECK: vptestmb 8128(%rdx), %zmm17, %k5
+// CHECK:  encoding: [0x62,0xf2,0x75,0x40,0x26,0x6a,0x7f]
+          vptestmb 8128(%rdx), %zmm17, %k5
+
+// CHECK: vptestmb 8192(%rdx), %zmm17, %k5
+// CHECK:  encoding: [0x62,0xf2,0x75,0x40,0x26,0xaa,0x00,0x20,0x00,0x00]
+          vptestmb 8192(%rdx), %zmm17, %k5
+
+// CHECK: vptestmb -8192(%rdx), %zmm17, %k5
+// CHECK:  encoding: [0x62,0xf2,0x75,0x40,0x26,0x6a,0x80]
+          vptestmb -8192(%rdx), %zmm17, %k5
+
+// CHECK: vptestmb -8256(%rdx), %zmm17, %k5
+// CHECK:  encoding: [0x62,0xf2,0x75,0x40,0x26,0xaa,0xc0,0xdf,0xff,0xff]
+          vptestmb -8256(%rdx), %zmm17, %k5
+
+// CHECK: vptestmw %zmm19, %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb2,0x95,0x40,0x26,0xe3]
+          vptestmw %zmm19, %zmm29, %k4
+
+// CHECK: vptestmw %zmm19, %zmm29, %k4 {%k2}
+// CHECK:  encoding: [0x62,0xb2,0x95,0x42,0x26,0xe3]
+          vptestmw %zmm19, %zmm29, %k4 {%k2}
+
+// CHECK: vptestmw (%rcx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf2,0x95,0x40,0x26,0x21]
+          vptestmw (%rcx), %zmm29, %k4
+
+// CHECK: vptestmw 291(%rax,%r14,8), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb2,0x95,0x40,0x26,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vptestmw 291(%rax,%r14,8), %zmm29, %k4
+
+// CHECK: vptestmw 8128(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf2,0x95,0x40,0x26,0x62,0x7f]
+          vptestmw 8128(%rdx), %zmm29, %k4
+
+// CHECK: vptestmw 8192(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf2,0x95,0x40,0x26,0xa2,0x00,0x20,0x00,0x00]
+          vptestmw 8192(%rdx), %zmm29, %k4
+
+// CHECK: vptestmw -8192(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf2,0x95,0x40,0x26,0x62,0x80]
+          vptestmw -8192(%rdx), %zmm29, %k4
+
+// CHECK: vptestmw -8256(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf2,0x95,0x40,0x26,0xa2,0xc0,0xdf,0xff,0xff]
+          vptestmw -8256(%rdx), %zmm29, %k4
+
+// CHECK: vptestnmb %zmm23, %zmm24, %k2
+// CHECK:  encoding: [0x62,0xb2,0x3e,0x40,0x26,0xd7]
+          vptestnmb %zmm23, %zmm24, %k2
+
+// CHECK: vptestnmb %zmm23, %zmm24, %k2 {%k7}
+// CHECK:  encoding: [0x62,0xb2,0x3e,0x47,0x26,0xd7]
+          vptestnmb %zmm23, %zmm24, %k2 {%k7}
+
+// CHECK: vptestnmb (%rcx), %zmm24, %k2
+// CHECK:  encoding: [0x62,0xf2,0x3e,0x40,0x26,0x11]
+          vptestnmb (%rcx), %zmm24, %k2
+
+// CHECK: vptestnmb 291(%rax,%r14,8), %zmm24, %k2
+// CHECK:  encoding: [0x62,0xb2,0x3e,0x40,0x26,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vptestnmb 291(%rax,%r14,8), %zmm24, %k2
+
+// CHECK: vptestnmb 8128(%rdx), %zmm24, %k2
+// CHECK:  encoding: [0x62,0xf2,0x3e,0x40,0x26,0x52,0x7f]
+          vptestnmb 8128(%rdx), %zmm24, %k2
+
+// CHECK: vptestnmb 8192(%rdx), %zmm24, %k2
+// CHECK:  encoding: [0x62,0xf2,0x3e,0x40,0x26,0x92,0x00,0x20,0x00,0x00]
+          vptestnmb 8192(%rdx), %zmm24, %k2
+
+// CHECK: vptestnmb -8192(%rdx), %zmm24, %k2
+// CHECK:  encoding: [0x62,0xf2,0x3e,0x40,0x26,0x52,0x80]
+          vptestnmb -8192(%rdx), %zmm24, %k2
+
+// CHECK: vptestnmb -8256(%rdx), %zmm24, %k2
+// CHECK:  encoding: [0x62,0xf2,0x3e,0x40,0x26,0x92,0xc0,0xdf,0xff,0xff]
+          vptestnmb -8256(%rdx), %zmm24, %k2
+
+// CHECK: vptestnmw %zmm27, %zmm18, %k4
+// CHECK:  encoding: [0x62,0x92,0xee,0x40,0x26,0xe3]
+          vptestnmw %zmm27, %zmm18, %k4
+
+// CHECK: vptestnmw %zmm27, %zmm18, %k4 {%k5}
+// CHECK:  encoding: [0x62,0x92,0xee,0x45,0x26,0xe3]
+          vptestnmw %zmm27, %zmm18, %k4 {%k5}
+
+// CHECK: vptestnmw (%rcx), %zmm18, %k4
+// CHECK:  encoding: [0x62,0xf2,0xee,0x40,0x26,0x21]
+          vptestnmw (%rcx), %zmm18, %k4
+
+// CHECK: vptestnmw 291(%rax,%r14,8), %zmm18, %k4
+// CHECK:  encoding: [0x62,0xb2,0xee,0x40,0x26,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vptestnmw 291(%rax,%r14,8), %zmm18, %k4
+
+// CHECK: vptestnmw 8128(%rdx), %zmm18, %k4
+// CHECK:  encoding: [0x62,0xf2,0xee,0x40,0x26,0x62,0x7f]
+          vptestnmw 8128(%rdx), %zmm18, %k4
+
+// CHECK: vptestnmw 8192(%rdx), %zmm18, %k4
+// CHECK:  encoding: [0x62,0xf2,0xee,0x40,0x26,0xa2,0x00,0x20,0x00,0x00]
+          vptestnmw 8192(%rdx), %zmm18, %k4
+
+// CHECK: vptestnmw -8192(%rdx), %zmm18, %k4
+// CHECK:  encoding: [0x62,0xf2,0xee,0x40,0x26,0x62,0x80]
+          vptestnmw -8192(%rdx), %zmm18, %k4
+
+// CHECK: vptestnmw -8256(%rdx), %zmm18, %k4
+// CHECK:  encoding: [0x62,0xf2,0xee,0x40,0x26,0xa2,0xc0,0xdf,0xff,0xff]
+          vptestnmw -8256(%rdx), %zmm18, %k4
+
+// CHECK: vptestnmb %zmm19, %zmm27, %k3
+// CHECK:  encoding: [0x62,0xb2,0x26,0x40,0x26,0xdb]
+          vptestnmb %zmm19, %zmm27, %k3
+
+// CHECK: vptestnmb %zmm19, %zmm27, %k3 {%k2}
+// CHECK:  encoding: [0x62,0xb2,0x26,0x42,0x26,0xdb]
+          vptestnmb %zmm19, %zmm27, %k3 {%k2}
+
+// CHECK: vptestnmb (%rcx), %zmm27, %k3
+// CHECK:  encoding: [0x62,0xf2,0x26,0x40,0x26,0x19]
+          vptestnmb (%rcx), %zmm27, %k3
+
+// CHECK: vptestnmb 4660(%rax,%r14,8), %zmm27, %k3
+// CHECK:  encoding: [0x62,0xb2,0x26,0x40,0x26,0x9c,0xf0,0x34,0x12,0x00,0x00]
+          vptestnmb 4660(%rax,%r14,8), %zmm27, %k3
+
+// CHECK: vptestnmb 8128(%rdx), %zmm27, %k3
+// CHECK:  encoding: [0x62,0xf2,0x26,0x40,0x26,0x5a,0x7f]
+          vptestnmb 8128(%rdx), %zmm27, %k3
+
+// CHECK: vptestnmb 8192(%rdx), %zmm27, %k3
+// CHECK:  encoding: [0x62,0xf2,0x26,0x40,0x26,0x9a,0x00,0x20,0x00,0x00]
+          vptestnmb 8192(%rdx), %zmm27, %k3
+
+// CHECK: vptestnmb -8192(%rdx), %zmm27, %k3
+// CHECK:  encoding: [0x62,0xf2,0x26,0x40,0x26,0x5a,0x80]
+          vptestnmb -8192(%rdx), %zmm27, %k3
+
+// CHECK: vptestnmb -8256(%rdx), %zmm27, %k3
+// CHECK:  encoding: [0x62,0xf2,0x26,0x40,0x26,0x9a,0xc0,0xdf,0xff,0xff]
+          vptestnmb -8256(%rdx), %zmm27, %k3
+
+// CHECK: vptestnmw %zmm21, %zmm17, %k2
+// CHECK:  encoding: [0x62,0xb2,0xf6,0x40,0x26,0xd5]
+          vptestnmw %zmm21, %zmm17, %k2
+
+// CHECK: vptestnmw %zmm21, %zmm17, %k2 {%k4}
+// CHECK:  encoding: [0x62,0xb2,0xf6,0x44,0x26,0xd5]
+          vptestnmw %zmm21, %zmm17, %k2 {%k4}
+
+// CHECK: vptestnmw (%rcx), %zmm17, %k2
+// CHECK:  encoding: [0x62,0xf2,0xf6,0x40,0x26,0x11]
+          vptestnmw (%rcx), %zmm17, %k2
+
+// CHECK: vptestnmw 4660(%rax,%r14,8), %zmm17, %k2
+// CHECK:  encoding: [0x62,0xb2,0xf6,0x40,0x26,0x94,0xf0,0x34,0x12,0x00,0x00]
+          vptestnmw 4660(%rax,%r14,8), %zmm17, %k2
+
+// CHECK: vptestnmw 8128(%rdx), %zmm17, %k2
+// CHECK:  encoding: [0x62,0xf2,0xf6,0x40,0x26,0x52,0x7f]
+          vptestnmw 8128(%rdx), %zmm17, %k2
+
+// CHECK: vptestnmw 8192(%rdx), %zmm17, %k2
+// CHECK:  encoding: [0x62,0xf2,0xf6,0x40,0x26,0x92,0x00,0x20,0x00,0x00]
+          vptestnmw 8192(%rdx), %zmm17, %k2
+
+// CHECK: vptestnmw -8192(%rdx), %zmm17, %k2
+// CHECK:  encoding: [0x62,0xf2,0xf6,0x40,0x26,0x52,0x80]
+          vptestnmw -8192(%rdx), %zmm17, %k2
+
+// CHECK: vptestnmw -8256(%rdx), %zmm17, %k2
+// CHECK:  encoding: [0x62,0xf2,0xf6,0x40,0x26,0x92,0xc0,0xdf,0xff,0xff]
+          vptestnmw -8256(%rdx), %zmm17, %k2
+
+// CHECK: vpmovb2m %zmm28, %k5
+// CHECK:  encoding: [0x62,0x92,0x7e,0x48,0x29,0xec]
+          vpmovb2m %zmm28, %k5
+
+// CHECK: vpmovw2m %zmm30, %k3
+// CHECK:  encoding: [0x62,0x92,0xfe,0x48,0x29,0xde]
+          vpmovw2m %zmm30, %k3
+
+// CHECK: vpmovm2b %k3, %zmm18
+// CHECK:  encoding: [0x62,0xe2,0x7e,0x48,0x28,0xd3]
+          vpmovm2b %k3, %zmm18
+
+// CHECK: vpmovm2w %k5, %zmm24
+// CHECK:  encoding: [0x62,0x62,0xfe,0x48,0x28,0xc5]
+          vpmovm2w %k5, %zmm24
+
diff --git a/test/MC/X86/avx512vl-encoding.s b/test/MC/X86/avx512vl-encoding.s
index acea70cb12ae..dd1ac24b04ea 100644
--- a/test/MC/X86/avx512vl-encoding.s
+++ b/test/MC/X86/avx512vl-encoding.s
@@ -447,3 +447,447 @@
 // CHECK: vpblendmq -1032(%rdx){1to4}, %ymm23, %ymm21
 // CHECK:  encoding: [0x62,0xe2,0xc5,0x30,0x64,0xaa,0xf8,0xfb,0xff,0xff]
           vpblendmq -1032(%rdx){1to4}, %ymm23, %ymm21
+
+// CHECK: vptestmd %xmm20, %xmm20, %k2
+// CHECK:  encoding: [0x62,0xb2,0x5d,0x00,0x27,0xd4]
+          vptestmd %xmm20, %xmm20, %k2
+
+// CHECK: vptestmd %xmm20, %xmm20, %k2 {%k7}
+// CHECK:  encoding: [0x62,0xb2,0x5d,0x07,0x27,0xd4]
+          vptestmd %xmm20, %xmm20, %k2 {%k7}
+
+// CHECK: vptestmd (%rcx), %xmm20, %k2
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x00,0x27,0x11]
+          vptestmd (%rcx), %xmm20, %k2
+
+// CHECK: vptestmd 291(%rax,%r14,8), %xmm20, %k2
+// CHECK:  encoding: [0x62,0xb2,0x5d,0x00,0x27,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vptestmd 291(%rax,%r14,8), %xmm20, %k2
+
+// CHECK: vptestmd (%rcx){1to4}, %xmm20, %k2
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x10,0x27,0x11]
+          vptestmd (%rcx){1to4}, %xmm20, %k2
+
+// CHECK: vptestmd 2032(%rdx), %xmm20, %k2
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x00,0x27,0x52,0x7f]
+          vptestmd 2032(%rdx), %xmm20, %k2
+
+// CHECK: vptestmd 2048(%rdx), %xmm20, %k2
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x00,0x27,0x92,0x00,0x08,0x00,0x00]
+          vptestmd 2048(%rdx), %xmm20, %k2
+
+// CHECK: vptestmd -2048(%rdx), %xmm20, %k2
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x00,0x27,0x52,0x80]
+          vptestmd -2048(%rdx), %xmm20, %k2
+
+// CHECK: vptestmd -2064(%rdx), %xmm20, %k2
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x00,0x27,0x92,0xf0,0xf7,0xff,0xff]
+          vptestmd -2064(%rdx), %xmm20, %k2
+
+// CHECK: vptestmd 508(%rdx){1to4}, %xmm20, %k2
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x10,0x27,0x52,0x7f]
+          vptestmd 508(%rdx){1to4}, %xmm20, %k2
+
+// CHECK: vptestmd 512(%rdx){1to4}, %xmm20, %k2
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x10,0x27,0x92,0x00,0x02,0x00,0x00]
+          vptestmd 512(%rdx){1to4}, %xmm20, %k2
+
+// CHECK: vptestmd -512(%rdx){1to4}, %xmm20, %k2
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x10,0x27,0x52,0x80]
+          vptestmd -512(%rdx){1to4}, %xmm20, %k2
+
+// CHECK: vptestmd -516(%rdx){1to4}, %xmm20, %k2
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x10,0x27,0x92,0xfc,0xfd,0xff,0xff]
+          vptestmd -516(%rdx){1to4}, %xmm20, %k2
+
+// CHECK: vptestmd %ymm17, %ymm20, %k3
+// CHECK:  encoding: [0x62,0xb2,0x5d,0x20,0x27,0xd9]
+          vptestmd %ymm17, %ymm20, %k3
+
+// CHECK: vptestmd %ymm17, %ymm20, %k3 {%k5}
+// CHECK:  encoding: [0x62,0xb2,0x5d,0x25,0x27,0xd9]
+          vptestmd %ymm17, %ymm20, %k3 {%k5}
+
+// CHECK: vptestmd (%rcx), %ymm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x20,0x27,0x19]
+          vptestmd (%rcx), %ymm20, %k3
+
+// CHECK: vptestmd 291(%rax,%r14,8), %ymm20, %k3
+// CHECK:  encoding: [0x62,0xb2,0x5d,0x20,0x27,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vptestmd 291(%rax,%r14,8), %ymm20, %k3
+
+// CHECK: vptestmd (%rcx){1to8}, %ymm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x30,0x27,0x19]
+          vptestmd (%rcx){1to8}, %ymm20, %k3
+
+// CHECK: vptestmd 4064(%rdx), %ymm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x20,0x27,0x5a,0x7f]
+          vptestmd 4064(%rdx), %ymm20, %k3
+
+// CHECK: vptestmd 4096(%rdx), %ymm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x20,0x27,0x9a,0x00,0x10,0x00,0x00]
+          vptestmd 4096(%rdx), %ymm20, %k3
+
+// CHECK: vptestmd -4096(%rdx), %ymm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x20,0x27,0x5a,0x80]
+          vptestmd -4096(%rdx), %ymm20, %k3
+
+// CHECK: vptestmd -4128(%rdx), %ymm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x20,0x27,0x9a,0xe0,0xef,0xff,0xff]
+          vptestmd -4128(%rdx), %ymm20, %k3
+
+// CHECK: vptestmd 508(%rdx){1to8}, %ymm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x30,0x27,0x5a,0x7f]
+          vptestmd 508(%rdx){1to8}, %ymm20, %k3
+
+// CHECK: vptestmd 512(%rdx){1to8}, %ymm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x30,0x27,0x9a,0x00,0x02,0x00,0x00]
+          vptestmd 512(%rdx){1to8}, %ymm20, %k3
+
+// CHECK: vptestmd -512(%rdx){1to8}, %ymm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x30,0x27,0x5a,0x80]
+          vptestmd -512(%rdx){1to8}, %ymm20, %k3
+
+// CHECK: vptestmd -516(%rdx){1to8}, %ymm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5d,0x30,0x27,0x9a,0xfc,0xfd,0xff,0xff]
+          vptestmd -516(%rdx){1to8}, %ymm20, %k3
+
+// CHECK: vptestmq %xmm28, %xmm22, %k4
+// CHECK:  encoding: [0x62,0x92,0xcd,0x00,0x27,0xe4]
+          vptestmq %xmm28, %xmm22, %k4
+
+// CHECK: vptestmq %xmm28, %xmm22, %k4 {%k3}
+// CHECK:  encoding: [0x62,0x92,0xcd,0x03,0x27,0xe4]
+          vptestmq %xmm28, %xmm22, %k4 {%k3}
+
+// CHECK: vptestmq (%rcx), %xmm22, %k4
+// CHECK:  encoding: [0x62,0xf2,0xcd,0x00,0x27,0x21]
+          vptestmq (%rcx), %xmm22, %k4
+
+// CHECK: vptestmq 291(%rax,%r14,8), %xmm22, %k4
+// CHECK:  encoding: [0x62,0xb2,0xcd,0x00,0x27,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vptestmq 291(%rax,%r14,8), %xmm22, %k4
+
+// CHECK: vptestmq (%rcx){1to2}, %xmm22, %k4
+// CHECK:  encoding: [0x62,0xf2,0xcd,0x10,0x27,0x21]
+          vptestmq (%rcx){1to2}, %xmm22, %k4
+
+// CHECK: vptestmq 2032(%rdx), %xmm22, %k4
+// CHECK:  encoding: [0x62,0xf2,0xcd,0x00,0x27,0x62,0x7f]
+          vptestmq 2032(%rdx), %xmm22, %k4
+
+// CHECK: vptestmq 2048(%rdx), %xmm22, %k4
+// CHECK:  encoding: [0x62,0xf2,0xcd,0x00,0x27,0xa2,0x00,0x08,0x00,0x00]
+          vptestmq 2048(%rdx), %xmm22, %k4
+
+// CHECK: vptestmq -2048(%rdx), %xmm22, %k4
+// CHECK:  encoding: [0x62,0xf2,0xcd,0x00,0x27,0x62,0x80]
+          vptestmq -2048(%rdx), %xmm22, %k4
+
+// CHECK: vptestmq -2064(%rdx), %xmm22, %k4
+// CHECK:  encoding: [0x62,0xf2,0xcd,0x00,0x27,0xa2,0xf0,0xf7,0xff,0xff]
+          vptestmq -2064(%rdx), %xmm22, %k4
+
+// CHECK: vptestmq 1016(%rdx){1to2}, %xmm22, %k4
+// CHECK:  encoding: [0x62,0xf2,0xcd,0x10,0x27,0x62,0x7f]
+          vptestmq 1016(%rdx){1to2}, %xmm22, %k4
+
+// CHECK: vptestmq 1024(%rdx){1to2}, %xmm22, %k4
+// CHECK:  encoding: [0x62,0xf2,0xcd,0x10,0x27,0xa2,0x00,0x04,0x00,0x00]
+          vptestmq 1024(%rdx){1to2}, %xmm22, %k4
+
+// CHECK: vptestmq -1024(%rdx){1to2}, %xmm22, %k4
+// CHECK:  encoding: [0x62,0xf2,0xcd,0x10,0x27,0x62,0x80]
+          vptestmq -1024(%rdx){1to2}, %xmm22, %k4
+
+// CHECK: vptestmq -1032(%rdx){1to2}, %xmm22, %k4
+// CHECK:  encoding: [0x62,0xf2,0xcd,0x10,0x27,0xa2,0xf8,0xfb,0xff,0xff]
+          vptestmq -1032(%rdx){1to2}, %xmm22, %k4
+
+// CHECK: vptestmq %ymm20, %ymm21, %k3
+// CHECK:  encoding: [0x62,0xb2,0xd5,0x20,0x27,0xdc]
+          vptestmq %ymm20, %ymm21, %k3
+
+// CHECK: vptestmq %ymm20, %ymm21, %k3 {%k7}
+// CHECK:  encoding: [0x62,0xb2,0xd5,0x27,0x27,0xdc]
+          vptestmq %ymm20, %ymm21, %k3 {%k7}
+
+// CHECK: vptestmq (%rcx), %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0xd5,0x20,0x27,0x19]
+          vptestmq (%rcx), %ymm21, %k3
+
+// CHECK: vptestmq 291(%rax,%r14,8), %ymm21, %k3
+// CHECK:  encoding: [0x62,0xb2,0xd5,0x20,0x27,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vptestmq 291(%rax,%r14,8), %ymm21, %k3
+
+// CHECK: vptestmq (%rcx){1to4}, %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0xd5,0x30,0x27,0x19]
+          vptestmq (%rcx){1to4}, %ymm21, %k3
+
+// CHECK: vptestmq 4064(%rdx), %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0xd5,0x20,0x27,0x5a,0x7f]
+          vptestmq 4064(%rdx), %ymm21, %k3
+
+// CHECK: vptestmq 4096(%rdx), %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0xd5,0x20,0x27,0x9a,0x00,0x10,0x00,0x00]
+          vptestmq 4096(%rdx), %ymm21, %k3
+
+// CHECK: vptestmq -4096(%rdx), %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0xd5,0x20,0x27,0x5a,0x80]
+          vptestmq -4096(%rdx), %ymm21, %k3
+
+// CHECK: vptestmq -4128(%rdx), %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0xd5,0x20,0x27,0x9a,0xe0,0xef,0xff,0xff]
+          vptestmq -4128(%rdx), %ymm21, %k3
+
+// CHECK: vptestmq 1016(%rdx){1to4}, %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0xd5,0x30,0x27,0x5a,0x7f]
+          vptestmq 1016(%rdx){1to4}, %ymm21, %k3
+
+// CHECK: vptestmq 1024(%rdx){1to4}, %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0xd5,0x30,0x27,0x9a,0x00,0x04,0x00,0x00]
+          vptestmq 1024(%rdx){1to4}, %ymm21, %k3
+
+// CHECK: vptestmq -1024(%rdx){1to4}, %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0xd5,0x30,0x27,0x5a,0x80]
+          vptestmq -1024(%rdx){1to4}, %ymm21, %k3
+
+// CHECK: vptestnmd %xmm22, %xmm20, %k3
+// CHECK:  encoding: [0x62,0xb2,0x5e,0x00,0x27,0xde]
+          vptestnmd %xmm22, %xmm20, %k3
+
+// CHECK: vptestnmd %xmm22, %xmm20, %k3 {%k7}
+// CHECK:  encoding: [0x62,0xb2,0x5e,0x07,0x27,0xde]
+          vptestnmd %xmm22, %xmm20, %k3 {%k7}
+
+// CHECK: vptestnmd (%rcx), %xmm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5e,0x00,0x27,0x19]
+          vptestnmd (%rcx), %xmm20, %k3
+
+// CHECK: vptestnmd 291(%rax,%r14,8), %xmm20, %k3
+// CHECK:  encoding: [0x62,0xb2,0x5e,0x00,0x27,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vptestnmd 291(%rax,%r14,8), %xmm20, %k3
+
+// CHECK: vptestnmd (%rcx){1to4}, %xmm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5e,0x10,0x27,0x19]
+          vptestnmd (%rcx){1to4}, %xmm20, %k3
+
+// CHECK: vptestnmd 2032(%rdx), %xmm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5e,0x00,0x27,0x5a,0x7f]
+          vptestnmd 2032(%rdx), %xmm20, %k3
+
+// CHECK: vptestnmd 2048(%rdx), %xmm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5e,0x00,0x27,0x9a,0x00,0x08,0x00,0x00]
+          vptestnmd 2048(%rdx), %xmm20, %k3
+
+// CHECK: vptestnmd -2048(%rdx), %xmm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5e,0x00,0x27,0x5a,0x80]
+          vptestnmd -2048(%rdx), %xmm20, %k3
+
+// CHECK: vptestnmd -2064(%rdx), %xmm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5e,0x00,0x27,0x9a,0xf0,0xf7,0xff,0xff]
+          vptestnmd -2064(%rdx), %xmm20, %k3
+
+// CHECK: vptestnmd 508(%rdx){1to4}, %xmm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5e,0x10,0x27,0x5a,0x7f]
+          vptestnmd 508(%rdx){1to4}, %xmm20, %k3
+
+// CHECK: vptestnmd 512(%rdx){1to4}, %xmm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5e,0x10,0x27,0x9a,0x00,0x02,0x00,0x00]
+          vptestnmd 512(%rdx){1to4}, %xmm20, %k3
+
+// CHECK: vptestnmd -512(%rdx){1to4}, %xmm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5e,0x10,0x27,0x5a,0x80]
+          vptestnmd -512(%rdx){1to4}, %xmm20, %k3
+
+// CHECK: vptestnmd -516(%rdx){1to4}, %xmm20, %k3
+// CHECK:  encoding: [0x62,0xf2,0x5e,0x10,0x27,0x9a,0xfc,0xfd,0xff,0xff]
+          vptestnmd -516(%rdx){1to4}, %xmm20, %k3
+
+// CHECK: vptestnmd %ymm23, %ymm21, %k3
+// CHECK:  encoding: [0x62,0xb2,0x56,0x20,0x27,0xdf]
+          vptestnmd %ymm23, %ymm21, %k3
+
+// CHECK: vptestnmd %ymm23, %ymm21, %k3 {%k7}
+// CHECK:  encoding: [0x62,0xb2,0x56,0x27,0x27,0xdf]
+          vptestnmd %ymm23, %ymm21, %k3 {%k7}
+
+// CHECK: vptestnmd (%rcx), %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0x56,0x20,0x27,0x19]
+          vptestnmd (%rcx), %ymm21, %k3
+
+// CHECK: vptestnmd 291(%rax,%r14,8), %ymm21, %k3
+// CHECK:  encoding: [0x62,0xb2,0x56,0x20,0x27,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vptestnmd 291(%rax,%r14,8), %ymm21, %k3
+
+// CHECK: vptestnmd (%rcx){1to8}, %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0x56,0x30,0x27,0x19]
+          vptestnmd (%rcx){1to8}, %ymm21, %k3
+
+// CHECK: vptestnmd 4064(%rdx), %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0x56,0x20,0x27,0x5a,0x7f]
+          vptestnmd 4064(%rdx), %ymm21, %k3
+
+// CHECK: vptestnmd 4096(%rdx), %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0x56,0x20,0x27,0x9a,0x00,0x10,0x00,0x00]
+          vptestnmd 4096(%rdx), %ymm21, %k3
+
+// CHECK: vptestnmd -4096(%rdx), %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0x56,0x20,0x27,0x5a,0x80]
+          vptestnmd -4096(%rdx), %ymm21, %k3
+
+// CHECK: vptestnmd -4128(%rdx), %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0x56,0x20,0x27,0x9a,0xe0,0xef,0xff,0xff]
+          vptestnmd -4128(%rdx), %ymm21, %k3
+
+// CHECK: vptestnmd 508(%rdx){1to8}, %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0x56,0x30,0x27,0x5a,0x7f]
+          vptestnmd 508(%rdx){1to8}, %ymm21, %k3
+
+// CHECK: vptestnmd 512(%rdx){1to8}, %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0x56,0x30,0x27,0x9a,0x00,0x02,0x00,0x00]
+          vptestnmd 512(%rdx){1to8}, %ymm21, %k3
+
+// CHECK: vptestnmd -512(%rdx){1to8}, %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0x56,0x30,0x27,0x5a,0x80]
+          vptestnmd -512(%rdx){1to8}, %ymm21, %k3
+
+// CHECK: vptestnmd -516(%rdx){1to8}, %ymm21, %k3
+// CHECK:  encoding: [0x62,0xf2,0x56,0x30,0x27,0x9a,0xfc,0xfd,0xff,0xff]
+          vptestnmd -516(%rdx){1to8}, %ymm21, %k3
+
+// CHECK: vptestnmq %xmm21, %xmm20, %k5
+// CHECK:  encoding: [0x62,0xb2,0xde,0x00,0x27,0xed]
+          vptestnmq %xmm21, %xmm20, %k5
+
+// CHECK: vptestnmq %xmm21, %xmm20, %k5 {%k5}
+// CHECK:  encoding: [0x62,0xb2,0xde,0x05,0x27,0xed]
+          vptestnmq %xmm21, %xmm20, %k5 {%k5}
+
+// CHECK: vptestnmq (%rcx), %xmm20, %k5
+// CHECK:  encoding: [0x62,0xf2,0xde,0x00,0x27,0x29]
+          vptestnmq (%rcx), %xmm20, %k5
+
+// CHECK: vptestnmq 291(%rax,%r14,8), %xmm20, %k5
+// CHECK:  encoding: [0x62,0xb2,0xde,0x00,0x27,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vptestnmq 291(%rax,%r14,8), %xmm20, %k5
+
+// CHECK: vptestnmq (%rcx){1to2}, %xmm20, %k5
+// CHECK:  encoding: [0x62,0xf2,0xde,0x10,0x27,0x29]
+          vptestnmq (%rcx){1to2}, %xmm20, %k5
+
+// CHECK: vptestnmq 2032(%rdx), %xmm20, %k5
+// CHECK:  encoding: [0x62,0xf2,0xde,0x00,0x27,0x6a,0x7f]
+          vptestnmq 2032(%rdx), %xmm20, %k5
+
+// CHECK: vptestnmq 2048(%rdx), %xmm20, %k5
+// CHECK:  encoding: [0x62,0xf2,0xde,0x00,0x27,0xaa,0x00,0x08,0x00,0x00]
+          vptestnmq 2048(%rdx), %xmm20, %k5
+
+// CHECK: vptestnmq -2048(%rdx), %xmm20, %k5
+// CHECK:  encoding: [0x62,0xf2,0xde,0x00,0x27,0x6a,0x80]
+          vptestnmq -2048(%rdx), %xmm20, %k5
+
+// CHECK: vptestnmq -2064(%rdx), %xmm20, %k5
+// CHECK:  encoding: [0x62,0xf2,0xde,0x00,0x27,0xaa,0xf0,0xf7,0xff,0xff]
+          vptestnmq -2064(%rdx), %xmm20, %k5
+
+// CHECK: vptestnmq 1016(%rdx){1to2}, %xmm20, %k5
+// CHECK:  encoding: [0x62,0xf2,0xde,0x10,0x27,0x6a,0x7f]
+          vptestnmq 1016(%rdx){1to2}, %xmm20, %k5
+
+// CHECK: vptestnmq 1024(%rdx){1to2}, %xmm20, %k5
+// CHECK:  encoding: [0x62,0xf2,0xde,0x10,0x27,0xaa,0x00,0x04,0x00,0x00]
+          vptestnmq 1024(%rdx){1to2}, %xmm20, %k5
+
+// CHECK: vptestnmq -1024(%rdx){1to2}, %xmm20, %k5
+// CHECK:  encoding: [0x62,0xf2,0xde,0x10,0x27,0x6a,0x80]
+          vptestnmq -1024(%rdx){1to2}, %xmm20, %k5
+
+// CHECK: vptestnmq -1032(%rdx){1to2}, %xmm20, %k5
+// CHECK:  encoding: [0x62,0xf2,0xde,0x10,0x27,0xaa,0xf8,0xfb,0xff,0xff]
+          vptestnmq -1032(%rdx){1to2}, %xmm20, %k5
+
+// CHECK: vptestnmq %ymm21, %ymm24, %k4
+// CHECK:  encoding: [0x62,0xb2,0xbe,0x20,0x27,0xe5]
+          vptestnmq %ymm21, %ymm24, %k4
+
+// CHECK: vptestnmq %ymm21, %ymm24, %k4 {%k3}
+// CHECK:  encoding: [0x62,0xb2,0xbe,0x23,0x27,0xe5]
+          vptestnmq %ymm21, %ymm24, %k4 {%k3}
+
+// CHECK: vptestnmq (%rcx), %ymm24, %k4
+// CHECK:  encoding: [0x62,0xf2,0xbe,0x20,0x27,0x21]
+          vptestnmq (%rcx), %ymm24, %k4
+
+// CHECK: vptestnmq 291(%rax,%r14,8), %ymm24, %k4
+// CHECK:  encoding: [0x62,0xb2,0xbe,0x20,0x27,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vptestnmq 291(%rax,%r14,8), %ymm24, %k4
+
+// CHECK: vptestnmq (%rcx){1to4}, %ymm24, %k4
+// CHECK:  encoding: [0x62,0xf2,0xbe,0x30,0x27,0x21]
+          vptestnmq (%rcx){1to4}, %ymm24, %k4
+
+// CHECK: vptestnmq 4064(%rdx), %ymm24, %k4
+// CHECK:  encoding: [0x62,0xf2,0xbe,0x20,0x27,0x62,0x7f]
+          vptestnmq 4064(%rdx), %ymm24, %k4
+
+// CHECK: vptestnmq 4096(%rdx), %ymm24, %k4
+// CHECK:  encoding: [0x62,0xf2,0xbe,0x20,0x27,0xa2,0x00,0x10,0x00,0x00]
+          vptestnmq 4096(%rdx), %ymm24, %k4
+
+// CHECK: vptestnmq -4096(%rdx), %ymm24, %k4
+// CHECK:  encoding: [0x62,0xf2,0xbe,0x20,0x27,0x62,0x80]
+          vptestnmq -4096(%rdx), %ymm24, %k4
+
+// CHECK: vptestnmq -4128(%rdx), %ymm24, %k4
+// CHECK:  encoding: [0x62,0xf2,0xbe,0x20,0x27,0xa2,0xe0,0xef,0xff,0xff]
+          vptestnmq -4128(%rdx), %ymm24, %k4
+
+// CHECK: vptestnmq 1016(%rdx){1to4}, %ymm24, %k4
+// CHECK:  encoding: [0x62,0xf2,0xbe,0x30,0x27,0x62,0x7f]
+          vptestnmq 1016(%rdx){1to4}, %ymm24, %k4
+
+// CHECK: vptestnmq 1024(%rdx){1to4}, %ymm24, %k4
+// CHECK:  encoding: [0x62,0xf2,0xbe,0x30,0x27,0xa2,0x00,0x04,0x00,0x00]
+          vptestnmq 1024(%rdx){1to4}, %ymm24, %k4
+
+// CHECK: vptestnmq -1024(%rdx){1to4}, %ymm24, %k4
+// CHECK:  encoding: [0x62,0xf2,0xbe,0x30,0x27,0x62,0x80]
+          vptestnmq -1024(%rdx){1to4}, %ymm24, %k4
+
+// CHECK: vptestnmq -1032(%rdx){1to4}, %ymm24, %k4
+// CHECK:  encoding: [0x62,0xf2,0xbe,0x30,0x27,0xa2,0xf8,0xfb,0xff,0xff]
+          vptestnmq -1032(%rdx){1to4}, %ymm24, %k4
+
+// CHECK: vpmovd2m %xmm27, %k3
+// CHECK:  encoding: [0x62,0x92,0x7e,0x08,0x39,0xdb]
+          vpmovd2m %xmm27, %k3
+
+// CHECK: vpmovd2m %ymm28, %k4
+// CHECK:  encoding: [0x62,0x92,0x7e,0x28,0x39,0xe4]
+          vpmovd2m %ymm28, %k4
+
+// CHECK: vpmovq2m %xmm28, %k5
+// CHECK:  encoding: [0x62,0x92,0xfe,0x08,0x39,0xec]
+          vpmovq2m %xmm28, %k5
+
+// CHECK: vpmovq2m %ymm29, %k4
+// CHECK:  encoding: [0x62,0x92,0xfe,0x28,0x39,0xe5]
+          vpmovq2m %ymm29, %k4
+
+// CHECK: vpmovm2d %k2, %xmm29
+// CHECK:  encoding: [0x62,0x62,0x7e,0x08,0x38,0xea]
+          vpmovm2d %k2, %xmm29
+
+// CHECK: vpmovm2d %k5, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0x7e,0x28,0x38,0xe5]
+          vpmovm2d %k5, %ymm20
+
+// CHECK: vpmovm2q %k5, %xmm17
+// CHECK:  encoding: [0x62,0xe2,0xfe,0x08,0x38,0xcd]
+          vpmovm2q %k5, %xmm17
+
+// CHECK: vpmovm2q %k2, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xfe,0x28,0x38,0xf2]
+          vpmovm2q %k2, %ymm30
diff --git a/test/MC/X86/expand-var.s b/test/MC/X86/expand-var.s
new file mode 100644
index 000000000000..8d5529a9a469
--- /dev/null
+++ b/test/MC/X86/expand-var.s
@@ -0,0 +1,18 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux < %s | llvm-readobj -r | FileCheck %s
+
+// CHECK:       Section {{.*}} .rela.text {
+// CHECK-NEXT:    0x0 R_X86_64_32 d 0x0
+// CHECK-NEXT:  }
+
+a:
+        b = a
+        c = a
+        d = a
+        .weak d
+        .long d + (b - c)
+
+
+a2:
+        .weak b2
+        b2 = a2
+        c2 = b2 - a2
diff --git a/test/MC/X86/i386-darwin-frame-register.ll b/test/MC/X86/i386-darwin-frame-register.ll
new file mode 100644
index 000000000000..c994a1efd203
--- /dev/null
+++ b/test/MC/X86/i386-darwin-frame-register.ll
@@ -0,0 +1,38 @@
+; RUN: llc -filetype=obj %s -o - | llvm-dwarfdump -debug-dump=frames - | FileCheck %s
+
+; IR reduced from a dummy:
+; void foo() {}
+
+; x86 Darwin uses different register mappings for eh_frame and debug_frame
+; sections. Check that the right mapping is used in debug_frame.
+; In the debug_frame mapping, regsiter 4 is ESP, thus the below tests that
+; the CFA is ESP+4 upon function entry.
+
+; CHECK: .debug_frame contents:
+; CHECK: ffffffff CIE
+; CHECK-NOT: {{CIE|FDE}}
+; CHECK:   DW_CFA_def_cfa: reg4 +4
+
+; ModuleID = 'foo.c'
+target datalayout = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"
+target triple = "i386-apple-macosx10.10.0"
+
+; Function Attrs: nounwind ssp
+define void @foo() #0 {
+entry:
+  ret void
+}
+
+attributes #0 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4, !5}
+!llvm.ident = !{!6}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.7.0 (trunk 230514) (llvm/trunk 230518)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !2, imports: !2)
+!1 = !DIFile(filename: "foo.c", directory: "/tmp")
+!2 = !{}
+!3 = !{i32 2, !"Dwarf Version", i32 2}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
+!5 = !{i32 1, !"PIC Level", i32 2}
+!6 = !{!"clang version 3.7.0 (trunk 230514) (llvm/trunk 230518)"}
diff --git a/test/MC/X86/intel-syntax-avx512.s b/test/MC/X86/intel-syntax-avx512.s
index b382994a097a..ffdbd20b77ea 100644
--- a/test/MC/X86/intel-syntax-avx512.s
+++ b/test/MC/X86/intel-syntax-avx512.s
@@ -1,5 +1,175 @@
-// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -mcpu=knl --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 -mcpu=knl --show-encoding %s | FileCheck %s
 
-// CHECK: vaddps (%rax), %zmm1, %zmm1
+// CHECK: vaddps  zmm1 , zmm1, zmmword ptr [rax]
 // CHECK: encoding: [0x62,0xf1,0x74,0x48,0x58,0x08]
 vaddps zmm1, zmm1, zmmword ptr [rax]
+
+// CHECK: vaddpd  zmm1 , zmm1, zmm2
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x48,0x58,0xca]
+vaddpd zmm1,zmm1,zmm2
+
+// CHECK: vaddpd  zmm1 {k5}, zmm1, zmm2
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x4d,0x58,0xca]
+vaddpd zmm1{k5},zmm1,zmm2
+
+// CHECK: vaddpd zmm1 {k5} {z}, zmm1, zmm2
+// CHECK:  encoding: [0x62,0xf1,0xf5,0xcd,0x58,0xca]
+vaddpd zmm1{k5} {z},zmm1,zmm2
+
+// CHECK: vaddpd zmm1 , zmm1, zmm2, {rn-sae}
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x18,0x58,0xca]
+vaddpd zmm1,zmm1,zmm2,{rn-sae}
+
+// CHECK: vaddpd zmm1 , zmm1, zmm2, {ru-sae}
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x58,0x58,0xca]
+vaddpd zmm1,zmm1,zmm2,{ru-sae}
+
+// CHECK:  vaddpd zmm1 , zmm1, zmm2, {rd-sae}
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x38,0x58,0xca]
+vaddpd zmm1,zmm1,zmm2,{rd-sae}
+
+// CHECK: vaddpd zmm1 , zmm1, zmm2, {rz-sae}
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x78,0x58,0xca]
+vaddpd zmm1,zmm1,zmm2,{rz-sae}
+
+// CHECK: vcmppd k2 , zmm12, zmm26, 171
+// CHECK:  encoding: [0x62,0x91,0x9d,0x48,0xc2,0xd2,0xab]
+          vcmppd k2,zmm12,zmm26,0xab
+
+// CHECK: vcmppd k2 {k3}, zmm12, zmm26, 171
+// CHECK:  encoding: [0x62,0x91,0x9d,0x4b,0xc2,0xd2,0xab]
+          vcmppd k2{k3},zmm12,zmm26,0xab
+
+// CHECK: vcmppd k2 , zmm12, zmm26,{sae}, 171
+// CHECK:  encoding: [0x62,0x91,0x9d,0x18,0xc2,0xd2,0xab]
+          vcmppd k2,zmm12,zmm26,{sae},0xab
+
+// CHECK: vcmppd k2 , zmm12, zmm26, 123
+// CHECK:  encoding: [0x62,0x91,0x9d,0x48,0xc2,0xd2,0x7b]
+          vcmppd k2 ,zmm12,zmm26,0x7b
+
+// CHECK: vcmppd k2 , zmm12, zmm26,{sae}, 123
+// CHECK:  encoding: [0x62,0x91,0x9d,0x18,0xc2,0xd2,0x7b]
+          vcmppd k2,zmm12,zmm26,{sae},0x7b
+
+// CHECK: vcmppd k2 , zmm12, zmmword ptr [rcx], 123
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x48,0xc2,0x11,0x7b]
+          vcmppd k2,zmm12,zmmword PTR [rcx],0x7b
+
+// CHECK: vcmppd  k2 , zmm12, zmmword ptr [rax + 8*r14 + 291], 123
+// CHECK:  encoding: [0x62,0xb1,0x9d,0x48,0xc2,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vcmppd k2 ,zmm12,zmmword PTR [rax+r14*8+0x123],0x7b
+
+// CHECK: vcmppd  k2 , zmm12, qword ptr [rcx]{1to8}, 123
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x58,0xc2,0x11,0x7b]
+          vcmppd k2,zmm12,QWORD PTR [rcx]{1to8},0x7b
+
+// CHECK: vcmppd  k2 , zmm12, zmmword ptr [rdx + 8128], 123
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x48,0xc2,0x52,0x7f,0x7b]
+          vcmppd k2,zmm12,zmmword PTR [rdx+0x1fc0],0x7b
+
+// CHECK: vcmppd  k2 , zmm12, zmmword ptr [rdx + 8192], 123
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x48,0xc2,0x92,0x00,0x20,0x00,0x00,0x7b]
+          vcmppd k2,zmm12,zmmword PTR [rdx+0x2000],0x7b
+
+// CHECK: vcmppd  k2 , zmm12, zmmword ptr [rdx - 8192], 123
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x48,0xc2,0x52,0x80,0x7b]
+          vcmppd k2,zmm12,zmmword PTR [rdx-0x2000],0x7b
+
+// CHECK: vcmppd  k2 , zmm12, zmmword ptr [rdx - 8256], 123
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x48,0xc2,0x92,0xc0,0xdf,0xff,0xff,0x7b]
+          vcmppd k2,zmm12,zmmword PTR [rdx-0x2040],0x7b
+
+// CHECK: vcmppd  k2 , zmm12, qword ptr [rdx + 1016]{1to8}, 123
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x58,0xc2,0x52,0x7f,0x7b]
+          vcmppd k2,zmm12,QWORD PTR [rdx+0x3f8]{1to8},0x7b
+
+// CHECK: vcmppd  k2 , zmm12, qword ptr [rdx + 1024]{1to8}, 123
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x58,0xc2,0x92,0x00,0x04,0x00,0x00,0x7b]
+          vcmppd k2,zmm12,QWORD PTR [rdx+0x400]{1to8},0x7b
+
+// CHECK: vcmppd  k2 , zmm12, qword ptr [rdx - 1024]{1to8}, 123
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x58,0xc2,0x52,0x80,0x7b]
+          vcmppd k2,zmm12,QWORD PTR [rdx-0x400]{1to8},0x7b
+
+// CHECK: vcmppd  k2 , zmm12, qword ptr [rdx - 1032]{1to8}, 123
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x58,0xc2,0x92,0xf8,0xfb,0xff,0xff,0x7b]
+          vcmppd k2,zmm12,QWORD PTR [rdx-0x408]{1to8},0x7b
+
+// CHECK: vcmpps  k2 , zmm17, zmm22, 171
+// CHECK:  encoding: [0x62,0xb1,0x74,0x40,0xc2,0xd6,0xab]
+          vcmpps k2,zmm17,zmm22,0xab
+
+// CHECK: vcmpps  k2 {k3}, zmm17, zmm22, 171
+// CHECK:  encoding: [0x62,0xb1,0x74,0x43,0xc2,0xd6,0xab]
+          vcmpps k2{k3},zmm17,zmm22,0xab
+
+// CHECK: vcmpps  k2 , zmm17, zmm22,{sae}, 171
+// CHECK:  encoding: [0x62,0xb1,0x74,0x10,0xc2,0xd6,0xab]
+          vcmpps k2,zmm17,zmm22,{sae},0xab
+
+// CHECK: vcmpps  k2 , zmm17, zmm22, 123
+// CHECK:  encoding: [0x62,0xb1,0x74,0x40,0xc2,0xd6,0x7b]
+          vcmpps k2,zmm17,zmm22,0x7b
+
+// CHECK: vcmpps  k2 , zmm17, zmm22,{sae}, 123
+// CHECK:  encoding: [0x62,0xb1,0x74,0x10,0xc2,0xd6,0x7b]
+          vcmpps k2,zmm17,zmm22,{sae},0x7b
+
+// CHECK: vcmpps  k2 , zmm17, zmmword ptr [rcx], 123
+// CHECK:  encoding: [0x62,0xf1,0x74,0x40,0xc2,0x11,0x7b]
+          vcmpps k2,zmm17,zmmword PTR [rcx],0x7b
+
+// CHECK: vcmpps  k2 , zmm17, zmmword ptr [rax + 8*r14 + 291], 123
+// CHECK:  encoding: [0x62,0xb1,0x74,0x40,0xc2,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vcmpps k2,zmm17,zmmword PTR [rax+r14*8+0x123],0x7b
+
+// CHECK: vcmpps  k2 , zmm17, dword ptr [rcx]{1to16}, 123
+// CHECK:  encoding: [0x62,0xf1,0x74,0x50,0xc2,0x11,0x7b]
+          vcmpps k2,zmm17,DWORD PTR [rcx]{1to16},0x7b
+
+// CHECK: vcmpps  k2 , zmm17, zmmword ptr [rdx + 8128], 123
+// CHECK:  encoding: [0x62,0xf1,0x74,0x40,0xc2,0x52,0x7f,0x7b]
+          vcmpps k2,zmm17,zmmword PTR [rdx+0x1fc0],0x7b
+
+// CHECK: vcmpps  k2 , zmm17, zmmword ptr [rdx + 8192], 123
+// CHECK:  encoding: [0x62,0xf1,0x74,0x40,0xc2,0x92,0x00,0x20,0x00,0x00,0x7b]
+          vcmpps k2,zmm17,zmmword PTR [rdx+0x2000],0x7b
+
+// CHECK: vcmpps  k2 , zmm17, zmmword ptr [rdx - 8192], 123
+// CHECK:  encoding: [0x62,0xf1,0x74,0x40,0xc2,0x52,0x80,0x7b]
+          vcmpps k2,zmm17,zmmword PTR [rdx-0x2000],0x7b
+
+// CHECK: vcmpps  k2 , zmm17, zmmword ptr [rdx - 8256], 123
+// CHECK:  encoding: [0x62,0xf1,0x74,0x40,0xc2,0x92,0xc0,0xdf,0xff,0xff,0x7b]
+          vcmpps k2,zmm17,zmmword PTR [rdx-0x2040],0x7b
+
+// CHECK: vcmpps  k2 , zmm17, dword ptr [rdx + 508]{1to16}, 123
+// CHECK:  encoding: [0x62,0xf1,0x74,0x50,0xc2,0x52,0x7f,0x7b]
+          vcmpps k2,zmm17,DWORD PTR [rdx+0x1fc]{1to16},0x7b
+
+// CHECK: vcmpps  k2 , zmm17, dword ptr [rdx + 512]{1to16}, 123
+// CHECK:  encoding: [0x62,0xf1,0x74,0x50,0xc2,0x92,0x00,0x02,0x00,0x00,0x7b]
+          vcmpps k2,zmm17,DWORD PTR [rdx+0x200]{1to16},0x7b
+
+// CHECK: vcmpps  k2 , zmm17, dword ptr [rdx - 512]{1to16}, 123
+// CHECK:  encoding: [0x62,0xf1,0x74,0x50,0xc2,0x52,0x80,0x7b]
+          vcmpps k2,zmm17,DWORD PTR [rdx-0x200]{1to16},0x7b
+
+// CHECK: vcmpps  k2 , zmm17, dword ptr [rdx - 516]{1to16}, 123
+// CHECK:  encoding: [0x62,0xf1,0x74,0x50,0xc2,0x92,0xfc,0xfd,0xff,0xff,0x7b]
+          vcmpps k2,zmm17,DWORD PTR [rdx-0x204]{1to16},0x7b
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s b/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s
new file mode 100644
index 000000000000..6de59da40b30
--- /dev/null
+++ b/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s
@@ -0,0 +1,225 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=knl -mattr=+avx512vl -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vcmppd k3 , xmm27, xmm23, 171
+// CHECK:  encoding: [0x62,0xb1,0xa5,0x00,0xc2,0xdf,0xab]
+          vcmppd k3,xmm27,xmm23,0xab
+
+// CHECK:  vcmppd k3 {k5}, xmm27, xmm23, 171
+// CHECK:  encoding: [0x62,0xb1,0xa5,0x05,0xc2,0xdf,0xab]
+          vcmppd k3{k5},xmm27,xmm23,0xab
+
+// CHECK:  vcmppd k3 , xmm27, xmm23, 123
+// CHECK:  encoding: [0x62,0xb1,0xa5,0x00,0xc2,0xdf,0x7b]
+          vcmppd k3,xmm27,xmm23,0x7b
+
+// CHECK:  vcmppd k3 , xmm27, xmmword ptr [rcx], 123
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x00,0xc2,0x19,0x7b]
+          vcmppd k3,xmm27,XMMWORD PTR [rcx],0x7b
+
+// CHECK:  vcmppd k3 , xmm27, xmmword ptr [rax + 8*r14 + 291], 123
+// CHECK:  encoding: [0x62,0xb1,0xa5,0x00,0xc2,0x9c,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vcmppd k3,xmm27,XMMWORD PTR [rax+r14*8+0x123],0x7b
+
+// CHECK:  vcmppd k3 , xmm27, qword ptr [rcx]{1to2}, 123
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x10,0xc2,0x19,0x7b]
+          vcmppd k3,xmm27,QWORD PTR [rcx]{1to2},0x7b
+
+// CHECK:  vcmppd k3 , xmm27, xmmword ptr [rdx + 2032], 123
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x00,0xc2,0x5a,0x7f,0x7b]
+          vcmppd k3,xmm27,XMMWORD PTR [rdx+0x7f0],0x7b
+
+// CHECK:  vcmppd k3 , xmm27, xmmword ptr [rdx + 2048], 123
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x00,0xc2,0x9a,0x00,0x08,0x00,0x00,0x7b]
+          vcmppd k3,xmm27,XMMWORD PTR [rdx+0x800],0x7b
+
+// CHECK:  vcmppd k3 , xmm27, xmmword ptr [rdx - 2048], 123
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x00,0xc2,0x5a,0x80,0x7b]
+          vcmppd k3,xmm27,XMMWORD PTR [rdx-0x800],0x7b
+
+// CHECK:  vcmppd k3 , xmm27, xmmword ptr [rdx - 2064], 123
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x00,0xc2,0x9a,0xf0,0xf7,0xff,0xff,0x7b]
+          vcmppd k3,xmm27,XMMWORD PTR [rdx-0x810],0x7b
+
+// CHECK:  vcmppd k3 , xmm27, qword ptr [rdx + 1016]{1to2}, 123
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x10,0xc2,0x5a,0x7f,0x7b]
+          vcmppd k3,xmm27,QWORD PTR [rdx+0x3f8]{1to2},0x7b
+
+// CHECK:  vcmppd k3 , xmm27, qword ptr [rdx + 1024]{1to2}, 123
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x10,0xc2,0x9a,0x00,0x04,0x00,0x00,0x7b]
+          vcmppd k3,xmm27,QWORD PTR [rdx+0x400]{1to2},0x7b
+
+// CHECK:  vcmppd k3 , xmm27, qword ptr [rdx - 1024]{1to2}, 123
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x10,0xc2,0x5a,0x80,0x7b]
+          vcmppd k3,xmm27,QWORD PTR [rdx-0x400]{1to2},0x7b
+
+// CHECK:  vcmppd k3 , xmm27, qword ptr [rdx - 1032]{1to2}, 123
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x10,0xc2,0x9a,0xf8,0xfb,0xff,0xff,0x7b]
+          vcmppd k3,xmm27,QWORD PTR [rdx-0x408]{1to2},0x7b
+
+// CHECK:  vcmppd k4 , ymm17, ymm27, 171
+// CHECK:  encoding: [0x62,0x91,0xf5,0x20,0xc2,0xe3,0xab]
+          vcmppd k4,ymm17,ymm27,0xab
+
+// CHECK:  vcmppd k4 {k7}, ymm17, ymm27, 171
+// CHECK:  encoding: [0x62,0x91,0xf5,0x27,0xc2,0xe3,0xab]
+          vcmppd k4{k7},ymm17,ymm27,0xab
+
+// CHECK:  vcmppd k4 , ymm17, ymm27, 123
+// CHECK:  encoding: [0x62,0x91,0xf5,0x20,0xc2,0xe3,0x7b]
+          vcmppd k4,ymm17,ymm27,0x7b
+
+// CHECK:  vcmppd k4 , ymm17, ymmword ptr [rcx], 123
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x20,0xc2,0x21,0x7b]
+          vcmppd k4,ymm17,YMMWORD PTR [rcx],0x7b
+
+// CHECK:  vcmppd k4 , ymm17, ymmword ptr [rax + 8*r14 + 291], 123
+// CHECK:  encoding: [0x62,0xb1,0xf5,0x20,0xc2,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vcmppd k4,ymm17,YMMWORD PTR [rax+r14*8+0x123],0x7b
+
+// CHECK:  vcmppd k4 , ymm17, qword ptr [rcx]{1to4}, 123
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x30,0xc2,0x21,0x7b]
+          vcmppd k4,ymm17,QWORD PTR [rcx]{1to4},0x7b
+
+// CHECK:  vcmppd k4 , ymm17, ymmword ptr [rdx + 4064], 123
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x20,0xc2,0x62,0x7f,0x7b]
+          vcmppd k4,ymm17,YMMWORD PTR [rdx+0xfe0],0x7b
+
+// CHECK:  vcmppd k4 , ymm17, ymmword ptr [rdx + 4096], 123
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x20,0xc2,0xa2,0x00,0x10,0x00,0x00,0x7b]
+          vcmppd k4,ymm17,YMMWORD PTR [rdx+0x1000],0x7b
+
+// CHECK:  vcmppd k4 , ymm17, ymmword ptr [rdx - 4096], 123
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x20,0xc2,0x62,0x80,0x7b]
+          vcmppd k4,ymm17,YMMWORD PTR [rdx-0x1000],0x7b
+
+// CHECK:  vcmppd k4 , ymm17, ymmword ptr [rdx - 4128], 123
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x20,0xc2,0xa2,0xe0,0xef,0xff,0xff,0x7b]
+          vcmppd k4,ymm17,YMMWORD PTR [rdx-0x1020],0x7b
+
+// CHECK:  vcmppd k4 , ymm17, qword ptr [rdx + 1016]{1to4}, 123
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x30,0xc2,0x62,0x7f,0x7b]
+          vcmppd k4,ymm17,QWORD PTR [rdx+0x3f8]{1to4},0x7b
+
+// CHECK:  vcmppd k4 , ymm17, qword ptr [rdx + 1024]{1to4}, 123
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x30,0xc2,0xa2,0x00,0x04,0x00,0x00,0x7b]
+          vcmppd k4,ymm17,QWORD PTR [rdx+0x400]{1to4},0x7b
+
+// CHECK:  vcmppd k4 , ymm17, qword ptr [rdx - 1024]{1to4}, 123
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x30,0xc2,0x62,0x80,0x7b]
+          vcmppd k4,ymm17,QWORD PTR [rdx-0x400]{1to4},0x7b
+
+// CHECK:  vcmppd k4 , ymm17, qword ptr [rdx - 1032]{1to4}, 123
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x30,0xc2,0xa2,0xf8,0xfb,0xff,0xff,0x7b]
+          vcmppd k4,ymm17,QWORD PTR [rdx-0x408]{1to4},0x7b
+
+// CHECK:  vcmpps k4 , xmm29, xmm28, 171
+// CHECK:  encoding: [0x62,0x91,0x14,0x00,0xc2,0xe4,0xab]
+          vcmpps k4,xmm29,xmm28,0xab
+
+// CHECK:  vcmpps k4 {k2}, xmm29, xmm28, 171
+// CHECK:  encoding: [0x62,0x91,0x14,0x02,0xc2,0xe4,0xab]
+          vcmpps k4{k2},xmm29,xmm28,0xab
+
+// CHECK:  vcmpps k4 , xmm29, xmm28, 123
+// CHECK:  encoding: [0x62,0x91,0x14,0x00,0xc2,0xe4,0x7b]
+          vcmpps k4,xmm29,xmm28,0x7b
+
+// CHECK:  vcmpps k4 , xmm29, xmmword ptr [rcx], 123
+// CHECK:  encoding: [0x62,0xf1,0x14,0x00,0xc2,0x21,0x7b]
+          vcmpps k4,xmm29,XMMWORD PTR [rcx],0x7b
+
+// CHECK:  vcmpps k4 , xmm29, xmmword ptr [rax + 8*r14 + 291], 123
+// CHECK:  encoding: [0x62,0xb1,0x14,0x00,0xc2,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vcmpps k4,xmm29,XMMWORD PTR [rax+r14*8+0x123],0x7b
+
+// CHECK:  vcmpps k4 , xmm29, dword ptr [rcx]{1to4}, 123
+// CHECK:  encoding: [0x62,0xf1,0x14,0x10,0xc2,0x21,0x7b]
+          vcmpps k4,xmm29,DWORD PTR [rcx]{1to4},0x7b
+
+// CHECK:  vcmpps k4 , xmm29, xmmword ptr [rdx + 2032], 123
+// CHECK:  encoding: [0x62,0xf1,0x14,0x00,0xc2,0x62,0x7f,0x7b]
+          vcmpps k4,xmm29,XMMWORD PTR [rdx+0x7f0],0x7b
+
+// CHECK:  vcmpps k4 , xmm29, xmmword ptr [rdx + 2048], 123
+// CHECK:  encoding: [0x62,0xf1,0x14,0x00,0xc2,0xa2,0x00,0x08,0x00,0x00,0x7b]
+          vcmpps k4,xmm29,XMMWORD PTR [rdx+0x800],0x7b
+
+// CHECK:  vcmpps k4 , xmm29, xmmword ptr [rdx - 2048], 123
+// CHECK:  encoding: [0x62,0xf1,0x14,0x00,0xc2,0x62,0x80,0x7b]
+          vcmpps k4,xmm29,XMMWORD PTR [rdx-0x800],0x7b
+
+// CHECK:  vcmpps k4 , xmm29, xmmword ptr [rdx - 2064], 123
+// CHECK:  encoding: [0x62,0xf1,0x14,0x00,0xc2,0xa2,0xf0,0xf7,0xff,0xff,0x7b]
+          vcmpps k4,xmm29,XMMWORD PTR [rdx-0x810],0x7b
+
+// CHECK:  vcmpps k4 , xmm29, dword ptr [rdx + 508]{1to4}, 123
+// CHECK:  encoding: [0x62,0xf1,0x14,0x10,0xc2,0x62,0x7f,0x7b]
+          vcmpps k4,xmm29,DWORD PTR [rdx+0x1fc]{1to4},0x7b
+
+// CHECK:  vcmpps k4 , xmm29, dword ptr [rdx + 512]{1to4}, 123
+// CHECK:  encoding: [0x62,0xf1,0x14,0x10,0xc2,0xa2,0x00,0x02,0x00,0x00,0x7b]
+          vcmpps k4,xmm29,DWORD PTR [rdx+0x200]{1to4},0x7b
+
+// CHECK:  vcmpps k4 , xmm29, dword ptr [rdx - 512]{1to4}, 123
+// CHECK:  encoding: [0x62,0xf1,0x14,0x10,0xc2,0x62,0x80,0x7b]
+          vcmpps k4,xmm29,DWORD PTR [rdx-0x200]{1to4},0x7b
+
+// CHECK:  vcmpps k4 , xmm29, dword ptr [rdx - 516]{1to4}, 123
+// CHECK:  encoding: [0x62,0xf1,0x14,0x10,0xc2,0xa2,0xfc,0xfd,0xff,0xff,0x7b]
+          vcmpps k4,xmm29,DWORD PTR [rdx-0x204]{1to4},0x7b
+
+// CHECK:  vcmpps k4 , ymm19, ymm18, 171
+// CHECK:  encoding: [0x62,0xb1,0x64,0x20,0xc2,0xe2,0xab]
+          vcmpps k4,ymm19,ymm18,0xab
+
+// CHECK:  vcmpps k4 {k1}, ymm19, ymm18, 171
+// CHECK:  encoding: [0x62,0xb1,0x64,0x21,0xc2,0xe2,0xab]
+          vcmpps k4{k1},ymm19,ymm18,0xab
+
+// CHECK:  vcmpps k4 , ymm19, ymm18, 123
+// CHECK:  encoding: [0x62,0xb1,0x64,0x20,0xc2,0xe2,0x7b]
+          vcmpps k4,ymm19,ymm18,0x7b
+
+// CHECK:  vcmpps k4 , ymm19, ymmword ptr [rcx], 123
+// CHECK:  encoding: [0x62,0xf1,0x64,0x20,0xc2,0x21,0x7b]
+          vcmpps k4,ymm19,YMMWORD PTR [rcx],0x7b
+
+// CHECK:  vcmpps k4 , ymm19, ymmword ptr [rax + 8*r14 + 291], 123
+// CHECK:  encoding: [0x62,0xb1,0x64,0x20,0xc2,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vcmpps k4,ymm19,YMMWORD PTR [rax+r14*8+0x123],0x7b
+
+// CHECK: vcmpps k4 , ymm19, dword ptr [rcx]{1to8}, 123
+// CHECK:  encoding: [0x62,0xf1,0x64,0x30,0xc2,0x21,0x7b]
+          vcmpps k4,ymm19,DWORD PTR [rcx]{1to8},0x7b
+
+// CHECK:  vcmpps k4 , ymm19, ymmword ptr [rdx + 4064], 123
+// CHECK:  encoding: [0x62,0xf1,0x64,0x20,0xc2,0x62,0x7f,0x7b]
+          vcmpps k4,ymm19,YMMWORD PTR [rdx+0xfe0],0x7b
+
+// CHECK:  vcmpps k4 , ymm19, ymmword ptr [rdx + 4096], 123
+// CHECK:  encoding: [0x62,0xf1,0x64,0x20,0xc2,0xa2,0x00,0x10,0x00,0x00,0x7b]
+          vcmpps k4,ymm19,YMMWORD PTR [rdx+0x1000],0x7b
+
+// CHECK:  vcmpps k4 , ymm19, ymmword ptr [rdx - 4096], 123
+// CHECK:  encoding: [0x62,0xf1,0x64,0x20,0xc2,0x62,0x80,0x7b]
+          vcmpps k4,ymm19,YMMWORD PTR [rdx-0x1000],0x7b
+
+// CHECK:  vcmpps k4 , ymm19, ymmword ptr [rdx - 4128], 123
+// CHECK:  encoding: [0x62,0xf1,0x64,0x20,0xc2,0xa2,0xe0,0xef,0xff,0xff,0x7b]
+          vcmpps k4,ymm19,YMMWORD PTR [rdx-0x1020],0x7b
+
+// CHECK:  vcmpps k4 , ymm19, dword ptr [rdx + 508]{1to8}, 123
+// CHECK:  encoding: [0x62,0xf1,0x64,0x30,0xc2,0x62,0x7f,0x7b]
+          vcmpps k4,ymm19,DWORD PTR [rdx+0x1fc]{1to8},0x7b
+
+// CHECK:  vcmpps k4 , ymm19, dword ptr [rdx + 512]{1to8}, 123
+// CHECK:  encoding: [0x62,0xf1,0x64,0x30,0xc2,0xa2,0x00,0x02,0x00,0x00,0x7b]
+          vcmpps k4,ymm19,DWORD PTR [rdx+0x200]{1to8},0x7b
+
+// CHECK:  vcmpps k4 , ymm19, dword ptr [rdx - 512]{1to8}, 123
+// CHECK:  encoding: [0x62,0xf1,0x64,0x30,0xc2,0x62,0x80,0x7b]
+          vcmpps k4,ymm19,DWORD PTR [rdx-0x200]{1to8},0x7b
+
+// CHECK:  vcmpps k4 , ymm19, dword ptr [rdx - 516]{1to8}, 123
+// CHECK:  encoding: [0x62,0xf1,0x64,0x30,0xc2,0xa2,0xfc,0xfd,0xff,0xff,0x7b]
+          vcmpps k4,ymm19,DWORD PTR [rdx-0x204]{1to8},0x7b
diff --git a/test/MC/X86/intel-syntax.s b/test/MC/X86/intel-syntax.s
index c027aa426f3b..fce0c65781cd 100644
--- a/test/MC/X86/intel-syntax.s
+++ b/test/MC/X86/intel-syntax.s
@@ -586,8 +586,8 @@ fdiv ST(1)
 fdivr ST(1)
 
 
-// CHECK: fxsaveq (%rax)
-// CHECK: fxrstorq (%rax)
+// CHECK: fxsave64 (%rax)
+// CHECK: fxrstor64 (%rax)
 fxsave64 opaque ptr [rax]
 fxrstor64 opaque ptr [rax]
 
diff --git a/test/MC/X86/invalid-sleb.s b/test/MC/X86/invalid-sleb.s
new file mode 100644
index 000000000000..ad27444d608f
--- /dev/null
+++ b/test/MC/X86/invalid-sleb.s
@@ -0,0 +1,5 @@
+// RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux %s -o %t 2>&1 | FileCheck %s
+
+// CHECK:  sleb128 and uleb128 expressions must be absolute
+
+        .sleb128 undefined
diff --git a/test/MC/X86/reloc-undef-global.s b/test/MC/X86/reloc-undef-global.s
index a4854d4a3593..24de90452526 100644
--- a/test/MC/X86/reloc-undef-global.s
+++ b/test/MC/X86/reloc-undef-global.s
@@ -7,7 +7,7 @@ bar = foo + 4
 	.long bar
 
 // ELF:      Relocations [
-// ELF-NEXT:   Section (2) .rela.text {
+// ELF-NEXT:   Section {{.*}} .rela.text {
 // ELF-NEXT:     0x0 R_X86_64_32 foo 0x4
 // ELF-NEXT:   }
 // ELF-NEXT: ]
diff --git a/test/MC/X86/stackmap-nops.ll b/test/MC/X86/stackmap-nops.ll
index a0d441866035..33ef8624f1f5 100644
--- a/test/MC/X86/stackmap-nops.ll
+++ b/test/MC/X86/stackmap-nops.ll
@@ -25,26 +25,26 @@ entry:
 ; CHECK: 7c: 5d
 ; CHECK: 7d: c3
 
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  0, i32  0)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  1, i32  1)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  2, i32  2)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  3, i32  3)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  4, i32  4)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  5, i32  5)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  6, i32  6)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  7, i32  7)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  8, i32  8)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  9, i32  9)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 10, i32 10)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 11, i32 11)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 12, i32 12)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 13, i32 13)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 14, i32 14)
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 15, i32 15)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  0, i32  0)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  1, i32  1)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  2, i32  2)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  3, i32  3)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  4, i32  4)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  5, i32  5)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  6, i32  6)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  7, i32  7)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  8, i32  8)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64  9, i32  9)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 10, i32 10)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 11, i32 11)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 12)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 13, i32 13)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 14)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 15, i32 15)
 ; Add an extra stackmap with a zero-length shadow to thwart the shadow
 ; optimization. This will force all 15 bytes of the previous shadow to be
 ; padded with nops.
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 16, i32 0)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 0)
   ret void
 }
 
diff --git a/test/MC/X86/x86-16.s b/test/MC/X86/x86-16.s
index 1f87c8159f67..9789cd268aaf 100644
--- a/test/MC/X86/x86-16.s
+++ b/test/MC/X86/x86-16.s
@@ -30,7 +30,7 @@
 // CHECK: movl	%eax, -16(%ebp)          # encoding: [0x67,0x66,0x89,0x45,0xf0]
 	movl	%eax, -16(%ebp)
 
-// CHECK: testb	%bl, %cl                # encoding: [0x84,0xcb]
+// CHECK: testb	%bl, %cl                # encoding: [0x84,0xd9]
         testb %bl, %cl
 
 // CHECK: cmpl	%eax, %ebx              # encoding: [0x66,0x39,0xc3]
diff --git a/test/MC/X86/x86-32-avx.s b/test/MC/X86/x86-32-avx.s
index ec4abdbb2a8b..a2f47d45d8a4 100644
--- a/test/MC/X86/x86-32-avx.s
+++ b/test/MC/X86/x86-32-avx.s
@@ -343,131 +343,131 @@
 // CHECK: encoding: [0xc5,0xe9,0xc6,0x5c,0xcb,0xfc,0x08]
           vshufpd  $8, -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpps  $0, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpeqps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x00]
           vcmpeqps   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $2, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpleps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x02]
           vcmpleps   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $1, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpltps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x01]
           vcmpltps   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $4, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpneqps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x04]
           vcmpneqps   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $6, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpnleps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x06]
           vcmpnleps   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $5, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpnltps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x05]
           vcmpnltps   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $7, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpordps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x07]
           vcmpordps   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $3, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpunordps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x03]
           vcmpunordps   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $0, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpeqps  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x00]
           vcmpeqps   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpps  $2, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpleps  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x02]
           vcmpleps   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpps  $1, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpltps  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x01]
           vcmpltps   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpps  $4, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpneqps  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x04]
           vcmpneqps   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpps  $6, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpnleps  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x06]
           vcmpnleps   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpps  $5, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpnltps  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x05]
           vcmpnltps   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpps  $7, -4(%ebx,%ecx,8), %xmm6, %xmm2
+// CHECK: vcmpordps  -4(%ebx,%ecx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x07]
           vcmpordps   -4(%ebx,%ecx,8), %xmm6, %xmm2
 
-// CHECK: vcmpps  $3, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpunordps  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x03]
           vcmpunordps   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmppd  $0, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpeqpd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x00]
           vcmpeqpd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmppd  $2, %xmm1, %xmm2, %xmm3
+// CHECK: vcmplepd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x02]
           vcmplepd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmppd  $1, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpltpd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x01]
           vcmpltpd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmppd  $4, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpneqpd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x04]
           vcmpneqpd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmppd  $6, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpnlepd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x06]
           vcmpnlepd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmppd  $5, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpnltpd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x05]
           vcmpnltpd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmppd  $7, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpordpd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x07]
           vcmpordpd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmppd  $3, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpunordpd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x03]
           vcmpunordpd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmppd  $0, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpeqpd  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x00]
           vcmpeqpd   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmppd  $2, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmplepd  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x02]
           vcmplepd   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmppd  $1, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpltpd  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x01]
           vcmpltpd   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmppd  $4, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpneqpd  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x04]
           vcmpneqpd   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmppd  $6, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpnlepd  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x06]
           vcmpnlepd   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmppd  $5, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpnltpd  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x05]
           vcmpnltpd   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmppd  $7, -4(%ebx,%ecx,8), %xmm6, %xmm2
+// CHECK: vcmpordpd  -4(%ebx,%ecx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x07]
           vcmpordpd   -4(%ebx,%ecx,8), %xmm6, %xmm2
 
-// CHECK: vcmppd  $3, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpunordpd  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x03]
           vcmpunordpd   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
@@ -487,131 +487,131 @@
 // CHECK: encoding: [0xc5,0xfd,0x50,0xc2]
           vmovmskpd  %ymm2, %eax
 
-// CHECK: vcmpss  $0, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpeqss  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x00]
           vcmpeqss   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpss  $2, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpless   %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x02]
           vcmpless   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpss  $1, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpltss  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x01]
           vcmpltss   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpss  $4, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpneqss  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x04]
           vcmpneqss   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpss  $6, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpnless  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x06]
           vcmpnless   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpss  $5, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpnltss  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x05]
           vcmpnltss   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpss  $7, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpordss  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x07]
           vcmpordss   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpss  $3, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpunordss  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x03]
           vcmpunordss   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpss  $0, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpeqss  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x00]
           vcmpeqss   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpss  $2, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpless  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x02]
           vcmpless   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpss  $1, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpltss  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x01]
           vcmpltss   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpss  $4, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpneqss  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x04]
           vcmpneqss   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpss  $6, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpnless  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x06]
           vcmpnless   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpss  $5, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpnltss  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x05]
           vcmpnltss   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpss  $7, -4(%ebx,%ecx,8), %xmm6, %xmm2
+// CHECK: vcmpordss  -4(%ebx,%ecx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x07]
           vcmpordss   -4(%ebx,%ecx,8), %xmm6, %xmm2
 
-// CHECK: vcmpss  $3, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpunordss  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x03]
           vcmpunordss   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpsd  $0, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpeqsd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x00]
           vcmpeqsd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpsd  $2, %xmm1, %xmm2, %xmm3
+// CHECK: vcmplesd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x02]
           vcmplesd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpsd  $1, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpltsd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x01]
           vcmpltsd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpsd  $4, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpneqsd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x04]
           vcmpneqsd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpsd  $6, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpnlesd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x06]
           vcmpnlesd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpsd  $5, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpnltsd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x05]
           vcmpnltsd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpsd  $7, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpordsd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x07]
           vcmpordsd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpsd  $3, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpunordsd  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x03]
           vcmpunordsd   %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpsd  $0, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpeqsd  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x00]
           vcmpeqsd   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpsd  $2, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmplesd  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x02]
           vcmplesd   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpsd  $1, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpltsd  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x01]
           vcmpltsd   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpsd  $4, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpneqsd  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x04]
           vcmpneqsd   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpsd  $6, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpnlesd  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x06]
           vcmpnlesd   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpsd  $5, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpnltsd  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x05]
           vcmpnltsd   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
-// CHECK: vcmpsd  $7, -4(%ebx,%ecx,8), %xmm6, %xmm2
+// CHECK: vcmpordsd  -4(%ebx,%ecx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x07]
           vcmpordsd   -4(%ebx,%ecx,8), %xmm6, %xmm2
 
-// CHECK: vcmpsd  $3, -4(%ebx,%ecx,8), %xmm2, %xmm3
+// CHECK: vcmpunordsd  -4(%ebx,%ecx,8), %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x03]
           vcmpunordsd   -4(%ebx,%ecx,8), %xmm2, %xmm3
 
@@ -2195,99 +2195,99 @@
 // CHECK: encoding: [0xc4,0xe3,0x79,0xdf,0x28,0x07]
           vaeskeygenassist  $7, (%eax), %xmm5
 
-// CHECK: vcmpps  $8, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpeq_uqps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x08]
           vcmpeq_uqps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $9, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpngeps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x09]
           vcmpngeps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $10, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpngtps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0a]
           vcmpngtps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $11, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpfalseps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0b]
           vcmpfalseps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $12, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpneq_oqps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0c]
           vcmpneq_oqps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $13, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpgeps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0d]
           vcmpgeps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $14, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpgtps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0e]
           vcmpgtps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $15, %xmm1, %xmm2, %xmm3
+// CHECK: vcmptrueps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0f]
           vcmptrueps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $16, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpeq_osps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x10]
           vcmpeq_osps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $17, %xmm1, %xmm2, %xmm3
+// CHECK: vcmplt_oqps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x11]
           vcmplt_oqps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $18, %xmm1, %xmm2, %xmm3
+// CHECK: vcmple_oqps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x12]
           vcmple_oqps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $19, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpunord_sps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x13]
           vcmpunord_sps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $20, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpneq_usps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x14]
           vcmpneq_usps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $21, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpnlt_uqps   %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x15]
           vcmpnlt_uqps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $22, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpnle_uqps   %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x16]
           vcmpnle_uqps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $23, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpord_sps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x17]
           vcmpord_sps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $24, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpeq_usps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x18]
           vcmpeq_usps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $25, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpnge_uqps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x19]
           vcmpnge_uqps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $26, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpngt_uqps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1a]
           vcmpngt_uqps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $27, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpfalse_osps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1b]
           vcmpfalse_osps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $28, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpneq_osps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1c]
           vcmpneq_osps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $29, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpge_oqps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1d]
           vcmpge_oqps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $30, %xmm1, %xmm2, %xmm3
+// CHECK: vcmpgt_oqps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1e]
           vcmpgt_oqps %xmm1, %xmm2, %xmm3
 
-// CHECK: vcmpps  $31, %xmm1, %xmm2, %xmm3
+// CHECK: vcmptrue_usps  %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1f]
           vcmptrue_usps %xmm1, %xmm2, %xmm3
 
@@ -2687,227 +2687,227 @@
 // CHECK: encoding: [0xc5,0xfb,0xe6,0x08]
           vcvtpd2dqx  (%eax), %xmm1
 
-// CHECK: vcmpps  $0, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpeqps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x00]
           vcmpeqps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $2, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpleps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x02]
           vcmpleps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $1, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpltps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x01]
           vcmpltps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $4, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpneqps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x04]
           vcmpneqps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $6, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpnleps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x06]
           vcmpnleps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $5, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpnltps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x05]
           vcmpnltps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $7, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpordps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x07]
           vcmpordps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $3, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpunordps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x03]
           vcmpunordps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $0, -4(%ebx,%ecx,8), %ymm2, %ymm3
+// CHECK: vcmpeqps  -4(%ebx,%ecx,8), %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x00]
           vcmpeqps -4(%ebx,%ecx,8), %ymm2, %ymm3
 
-// CHECK: vcmpps  $2, -4(%ebx,%ecx,8), %ymm2, %ymm3
+// CHECK: vcmpleps  -4(%ebx,%ecx,8), %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x02]
           vcmpleps -4(%ebx,%ecx,8), %ymm2, %ymm3
 
-// CHECK: vcmpps  $1, -4(%ebx,%ecx,8), %ymm2, %ymm3
+// CHECK: vcmpltps  -4(%ebx,%ecx,8), %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x01]
           vcmpltps -4(%ebx,%ecx,8), %ymm2, %ymm3
 
-// CHECK: vcmpps  $4, -4(%ebx,%ecx,8), %ymm2, %ymm3
+// CHECK: vcmpneqps  -4(%ebx,%ecx,8), %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x04]
           vcmpneqps -4(%ebx,%ecx,8), %ymm2, %ymm3
 
-// CHECK: vcmpps  $6, -4(%ebx,%ecx,8), %ymm2, %ymm3
+// CHECK: vcmpnleps  -4(%ebx,%ecx,8), %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x06]
           vcmpnleps -4(%ebx,%ecx,8), %ymm2, %ymm3
 
-// CHECK: vcmpps  $5, -4(%ebx,%ecx,8), %ymm2, %ymm3
+// CHECK: vcmpnltps  -4(%ebx,%ecx,8), %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x05]
           vcmpnltps -4(%ebx,%ecx,8), %ymm2, %ymm3
 
-// CHECK: vcmpps  $7, -4(%ebx,%ecx,8), %ymm6, %ymm2
+// CHECK: vcmpordps  -4(%ebx,%ecx,8), %ymm6, %ymm2
 // CHECK: encoding: [0xc5,0xcc,0xc2,0x54,0xcb,0xfc,0x07]
           vcmpordps -4(%ebx,%ecx,8), %ymm6, %ymm2
 
-// CHECK: vcmpps  $3, -4(%ebx,%ecx,8), %ymm2, %ymm3
+// CHECK: vcmpunordps  -4(%ebx,%ecx,8), %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x03]
           vcmpunordps -4(%ebx,%ecx,8), %ymm2, %ymm3
 
-// CHECK: vcmppd  $0, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpeqpd  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x00]
           vcmpeqpd %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmppd  $2, %ymm1, %ymm2, %ymm3
+// CHECK: vcmplepd  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x02]
           vcmplepd %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmppd  $1, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpltpd  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x01]
           vcmpltpd %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmppd  $4, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpneqpd  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x04]
           vcmpneqpd %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmppd  $6, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpnlepd  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x06]
           vcmpnlepd %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmppd  $5, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpnltpd  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x05]
           vcmpnltpd %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmppd  $7, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpordpd  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x07]
           vcmpordpd %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmppd  $3, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpunordpd  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x03]
           vcmpunordpd %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmppd  $0, -4(%ebx,%ecx,8), %ymm2, %ymm3
+// CHECK: vcmpeqpd  -4(%ebx,%ecx,8), %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x00]
           vcmpeqpd -4(%ebx,%ecx,8), %ymm2, %ymm3
 
-// CHECK: vcmppd  $2, -4(%ebx,%ecx,8), %ymm2, %ymm3
+// CHECK: vcmplepd  -4(%ebx,%ecx,8), %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x02]
           vcmplepd -4(%ebx,%ecx,8), %ymm2, %ymm3
 
-// CHECK: vcmppd  $1, -4(%ebx,%ecx,8), %ymm2, %ymm3
+// CHECK: vcmpltpd  -4(%ebx,%ecx,8), %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x01]
           vcmpltpd -4(%ebx,%ecx,8), %ymm2, %ymm3
 
-// CHECK: vcmppd  $4, -4(%ebx,%ecx,8), %ymm2, %ymm3
+// CHECK: vcmpneqpd  -4(%ebx,%ecx,8), %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x04]
           vcmpneqpd -4(%ebx,%ecx,8), %ymm2, %ymm3
 
-// CHECK: vcmppd  $6, -4(%ebx,%ecx,8), %ymm2, %ymm3
+// CHECK: vcmpnlepd  -4(%ebx,%ecx,8), %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x06]
           vcmpnlepd -4(%ebx,%ecx,8), %ymm2, %ymm3
 
-// CHECK: vcmppd  $5, -4(%ebx,%ecx,8), %ymm2, %ymm3
+// CHECK: vcmpnltpd  -4(%ebx,%ecx,8), %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x05]
           vcmpnltpd -4(%ebx,%ecx,8), %ymm2, %ymm3
 
-// CHECK: vcmppd  $7, -4(%ebx,%ecx,8), %ymm6, %ymm2
+// CHECK: vcmpordpd  -4(%ebx,%ecx,8), %ymm6, %ymm2
 // CHECK: encoding: [0xc5,0xcd,0xc2,0x54,0xcb,0xfc,0x07]
           vcmpordpd -4(%ebx,%ecx,8), %ymm6, %ymm2
 
-// CHECK: vcmppd  $3, -4(%ebx,%ecx,8), %ymm2, %ymm3
+// CHECK: vcmpunordpd  -4(%ebx,%ecx,8), %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x03]
           vcmpunordpd -4(%ebx,%ecx,8), %ymm2, %ymm3
 
-// CHECK: vcmpps  $8, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpeq_uqps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x08]
           vcmpeq_uqps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $9, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpngeps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x09]
           vcmpngeps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $10, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpngtps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x0a]
           vcmpngtps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $11, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpfalseps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x0b]
           vcmpfalseps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $12, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpneq_oqps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x0c]
           vcmpneq_oqps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $13, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpgeps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x0d]
           vcmpgeps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $14, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpgtps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x0e]
           vcmpgtps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $15, %ymm1, %ymm2, %ymm3
+// CHECK: vcmptrueps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x0f]
           vcmptrueps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $16, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpeq_osps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x10]
           vcmpeq_osps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $17, %ymm1, %ymm2, %ymm3
+// CHECK: vcmplt_oqps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x11]
           vcmplt_oqps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $18, %ymm1, %ymm2, %ymm3
+// CHECK: vcmple_oqps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x12]
           vcmple_oqps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $19, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpunord_sps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x13]
           vcmpunord_sps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $20, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpneq_usps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x14]
           vcmpneq_usps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $21, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpnlt_uqps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x15]
           vcmpnlt_uqps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $22, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpnle_uqps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x16]
           vcmpnle_uqps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $23, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpord_sps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x17]
           vcmpord_sps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $24, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpeq_usps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x18]
           vcmpeq_usps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $25, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpnge_uqps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x19]
           vcmpnge_uqps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $26, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpngt_uqps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x1a]
           vcmpngt_uqps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $27, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpfalse_osps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x1b]
           vcmpfalse_osps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $28, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpneq_osps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x1c]
           vcmpneq_osps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $29, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpge_oqps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x1d]
           vcmpge_oqps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $30, %ymm1, %ymm2, %ymm3
+// CHECK: vcmpgt_oqps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x1e]
           vcmpgt_oqps %ymm1, %ymm2, %ymm3
 
-// CHECK: vcmpps  $31, %ymm1, %ymm2, %ymm3
+// CHECK: vcmptrue_usps  %ymm1, %ymm2, %ymm3
 // CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x1f]
           vcmptrue_usps %ymm1, %ymm2, %ymm3
 
@@ -3351,3 +3351,15 @@
           vdppd $0x81, %xmm2, %xmm5, %xmm1
 // CHECK: vinsertps $129, %xmm3, %xmm2, %xmm1
           vinsertps $0x81, %xmm3, %xmm2, %xmm1
+
+// CHECK: vcmpps $128, %xmm2, %xmm1, %xmm0
+// CHECK: encoding: [0xc5,0xf0,0xc2,0xc2,0x80]
+vcmpps $-128, %xmm2, %xmm1, %xmm0
+
+// CHECK: vcmpps $128, %xmm2, %xmm1, %xmm0
+// CHECK: encoding: [0xc5,0xf0,0xc2,0xc2,0x80]
+vcmpps $128, %xmm2, %xmm1, %xmm0
+
+// CHECK: vcmpps $255, %xmm2, %xmm1, %xmm0
+// CHECK: encoding: [0xc5,0xf0,0xc2,0xc2,0xff]
+vcmpps $255, %xmm2, %xmm1, %xmm0
diff --git a/test/MC/X86/x86-32-coverage.s b/test/MC/X86/x86-32-coverage.s
index 80c34ece624f..e14031d67f1e 100644
--- a/test/MC/X86/x86-32-coverage.s
+++ b/test/MC/X86/x86-32-coverage.s
@@ -1,377 +1,5 @@
 // RUN: llvm-mc -triple i386-unknown-unknown %s --show-encoding  | FileCheck %s
 
-// CHECK: 	movb	$127, 3735928559(%ebx,%ecx,8)
-        	movb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movw	$31438, 3735928559(%ebx,%ecx,8)
-        	movw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	movl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movl	$324478056, 3735928559(%ebx,%ecx,8)
-        	movl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movsbl	3735928559(%ebx,%ecx,8), %ecx
-        	movsbl	0xdeadbeef(%ebx,%ecx,8),%ecx
-
-// CHECK: 	movswl	3735928559(%ebx,%ecx,8), %ecx
-        	movswl	0xdeadbeef(%ebx,%ecx,8),%ecx
-
-// CHECK: 	movzbl	3735928559(%ebx,%ecx,8), %ecx
-        	movzbl	0xdeadbeef(%ebx,%ecx,8),%ecx
-
-// CHECK: 	movzwl	3735928559(%ebx,%ecx,8), %ecx
-        	movzwl	0xdeadbeef(%ebx,%ecx,8),%ecx
-
-// CHECK: 	pushl	3735928559(%ebx,%ecx,8)
-        	pushl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	popl	3735928559(%ebx,%ecx,8)
-        	popl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	lahf
-        	lahf
-
-// CHECK: 	sahf
-        	sahf
-
-// CHECK: 	addb	$254, 3735928559(%ebx,%ecx,8)
-        	addb	$0xfe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	addb	$127, 3735928559(%ebx,%ecx,8)
-        	addb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	addw	$31438, 3735928559(%ebx,%ecx,8)
-        	addw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	addl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	addl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	addl	$324478056, 3735928559(%ebx,%ecx,8)
-        	addl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	incl	3735928559(%ebx,%ecx,8)
-        	incl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	subb	$254, 3735928559(%ebx,%ecx,8)
-        	subb	$0xfe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	subb	$127, 3735928559(%ebx,%ecx,8)
-        	subb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	subw	$31438, 3735928559(%ebx,%ecx,8)
-        	subw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	subl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	subl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	subl	$324478056, 3735928559(%ebx,%ecx,8)
-        	subl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	decl	3735928559(%ebx,%ecx,8)
-        	decl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sbbw	$31438, 3735928559(%ebx,%ecx,8)
-        	sbbw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sbbl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	sbbl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sbbl	$324478056, 3735928559(%ebx,%ecx,8)
-        	sbbl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	cmpb	$254, 3735928559(%ebx,%ecx,8)
-        	cmpb	$0xfe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	cmpb	$127, 3735928559(%ebx,%ecx,8)
-        	cmpb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	cmpw	$31438, 3735928559(%ebx,%ecx,8)
-        	cmpw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	cmpl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	cmpl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	cmpl	$324478056, 3735928559(%ebx,%ecx,8)
-        	cmpl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	testb	$127, 3735928559(%ebx,%ecx,8)
-        	testb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	testw	$31438, 3735928559(%ebx,%ecx,8)
-        	testw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	testl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	testl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	testl	$324478056, 3735928559(%ebx,%ecx,8)
-        	testl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	andb	$254, 3735928559(%ebx,%ecx,8)
-        	andb	$0xfe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	andb	$127, 3735928559(%ebx,%ecx,8)
-        	andb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	andw	$31438, 3735928559(%ebx,%ecx,8)
-        	andw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	andl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	andl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	andl	$324478056, 3735928559(%ebx,%ecx,8)
-        	andl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	orb	$254, 3735928559(%ebx,%ecx,8)
-        	orb	$0xfe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	orb	$127, 3735928559(%ebx,%ecx,8)
-        	orb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	orw	$31438, 3735928559(%ebx,%ecx,8)
-        	orw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	orl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	orl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	orl	$324478056, 3735928559(%ebx,%ecx,8)
-        	orl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	xorb	$254, 3735928559(%ebx,%ecx,8)
-        	xorb	$0xfe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	xorb	$127, 3735928559(%ebx,%ecx,8)
-        	xorb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	xorw	$31438, 3735928559(%ebx,%ecx,8)
-        	xorw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	xorl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	xorl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	xorl	$324478056, 3735928559(%ebx,%ecx,8)
-        	xorl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	adcb	$254, 3735928559(%ebx,%ecx,8)
-        	adcb	$0xfe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	adcb	$127, 3735928559(%ebx,%ecx,8)
-        	adcb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	adcw	$31438, 3735928559(%ebx,%ecx,8)
-        	adcw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	adcl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	adcl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	adcl	$324478056, 3735928559(%ebx,%ecx,8)
-        	adcl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	negl	3735928559(%ebx,%ecx,8)
-        	negl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	notl	3735928559(%ebx,%ecx,8)
-        	notl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	cbtw
-        	cbtw
-
-// CHECK: 	cwtl
-        	cwtl
-
-// CHECK: 	cwtd
-        	cwtd
-
-// CHECK: 	cltd
-        	cltd
-
-// CHECK: 	mull	3735928559(%ebx,%ecx,8)
-        	mull	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	imull	3735928559(%ebx,%ecx,8)
-        	imull	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	divl	3735928559(%ebx,%ecx,8)
-        	divl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	idivl	3735928559(%ebx,%ecx,8)
-        	idivl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	roll	$0, 3735928559(%ebx,%ecx,8)
-        	roll	$0,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	rolb	$127, 3735928559(%ebx,%ecx,8)
-        	rolb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	roll	3735928559(%ebx,%ecx,8)
-        	roll	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	rorl	$0, 3735928559(%ebx,%ecx,8)
-        	rorl	$0,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	rorb	$127, 3735928559(%ebx,%ecx,8)
-        	rorb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	rorl	3735928559(%ebx,%ecx,8)
-        	rorl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	shll	$0, 3735928559(%ebx,%ecx,8)
-        	shll	$0,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	shlb	$127, 3735928559(%ebx,%ecx,8)
-        	shlb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	shll	3735928559(%ebx,%ecx,8)
-        	shll	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	shrl	$0, 3735928559(%ebx,%ecx,8)
-        	shrl	$0,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	shrb	$127, 3735928559(%ebx,%ecx,8)
-        	shrb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	shrl	3735928559(%ebx,%ecx,8)
-        	shrl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sarl	$0, 3735928559(%ebx,%ecx,8)
-        	sarl	$0,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sarb	$127, 3735928559(%ebx,%ecx,8)
-        	sarb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sarl	3735928559(%ebx,%ecx,8)
-        	sarl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	calll	*%ecx
-        	call	*%ecx
-
-// CHECK: 	calll	*3735928559(%ebx,%ecx,8)
-        	call	*0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	calll	*3735928559(%ebx,%ecx,8)
-        	call	*0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	jmpl	*3735928559(%ebx,%ecx,8)
-        	jmp	*0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	jmpl	*3735928559(%ebx,%ecx,8)
-        	jmp	*0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	ljmpl	*3735928559(%ebx,%ecx,8)
-        	ljmpl	*0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	lret
-        	lret
-
-// CHECK: 	leave
-        	leave
-
-// CHECK: 	leave
-        	leavel
-
-// CHECK: 	seto	%bl
-        	seto	%bl
-
-// CHECK: 	seto	3735928559(%ebx,%ecx,8)
-        	seto	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setno	%bl
-        	setno	%bl
-
-// CHECK: 	setno	3735928559(%ebx,%ecx,8)
-        	setno	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setb	%bl
-        	setb	%bl
-
-// CHECK: 	setb	3735928559(%ebx,%ecx,8)
-        	setb	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setae	%bl
-        	setae	%bl
-
-// CHECK: 	setae	3735928559(%ebx,%ecx,8)
-        	setae	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sete	%bl
-        	sete	%bl
-
-// CHECK: 	sete	3735928559(%ebx,%ecx,8)
-        	sete	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setne	%bl
-        	setne	%bl
-
-// CHECK: 	setne	3735928559(%ebx,%ecx,8)
-        	setne	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setbe	%bl
-        	setbe	%bl
-
-// CHECK: 	setbe	3735928559(%ebx,%ecx,8)
-        	setbe	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	seta	%bl
-        	seta	%bl
-
-// CHECK: 	seta	3735928559(%ebx,%ecx,8)
-        	seta	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sets	%bl
-        	sets	%bl
-
-// CHECK: 	sets	3735928559(%ebx,%ecx,8)
-        	sets	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setns	%bl
-        	setns	%bl
-
-// CHECK: 	setns	3735928559(%ebx,%ecx,8)
-        	setns	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setp	%bl
-        	setp	%bl
-
-// CHECK: 	setp	3735928559(%ebx,%ecx,8)
-        	setp	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setnp	%bl
-        	setnp	%bl
-
-// CHECK: 	setnp	3735928559(%ebx,%ecx,8)
-        	setnp	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setl	%bl
-        	setl	%bl
-
-// CHECK: 	setl	3735928559(%ebx,%ecx,8)
-        	setl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setge	%bl
-        	setge	%bl
-
-// CHECK: 	setge	3735928559(%ebx,%ecx,8)
-        	setge	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setle	%bl
-        	setle	%bl
-
-// CHECK: 	setle	3735928559(%ebx,%ecx,8)
-        	setle	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setg	%bl
-        	setg	%bl
-
-// CHECK: 	setg	3735928559(%ebx,%ecx,8)
-        	setg	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	nopl	3735928559(%ebx,%ecx,8)
-        	nopl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	nop
-        	nop
-
 // CHECK: flds	(%edi)
 // CHECK:  encoding: [0xd9,0x07]
         	flds	(%edi)
@@ -380,1270 +8,6 @@
 // CHECK:  encoding: [0xdf,0x07]
         	filds	(%edi)
 
-// CHECK: 	fldl	3735928559(%ebx,%ecx,8)
-        	fldl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fildl	3735928559(%ebx,%ecx,8)
-        	fildl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fildll	3735928559(%ebx,%ecx,8)
-        	fildll	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fldt	3735928559(%ebx,%ecx,8)
-        	fldt	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fbld	3735928559(%ebx,%ecx,8)
-        	fbld	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fstl	3735928559(%ebx,%ecx,8)
-        	fstl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fistl	3735928559(%ebx,%ecx,8)
-        	fistl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fstpl	3735928559(%ebx,%ecx,8)
-        	fstpl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fistpl	3735928559(%ebx,%ecx,8)
-        	fistpl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fistpll	3735928559(%ebx,%ecx,8)
-        	fistpll	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fstpt	3735928559(%ebx,%ecx,8)
-        	fstpt	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fbstp	3735928559(%ebx,%ecx,8)
-        	fbstp	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	ficoml	3735928559(%ebx,%ecx,8)
-        	ficoml	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	ficompl	3735928559(%ebx,%ecx,8)
-        	ficompl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fucompp
-        	fucompp
-
-// CHECK: 	ftst
-        	ftst
-
-// CHECK: 	fld1
-        	fld1
-
-// CHECK: 	fldz
-        	fldz
-
-// CHECK: 	faddl	3735928559(%ebx,%ecx,8)
-        	faddl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fiaddl	3735928559(%ebx,%ecx,8)
-        	fiaddl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fsubl	3735928559(%ebx,%ecx,8)
-        	fsubl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fisubl	3735928559(%ebx,%ecx,8)
-        	fisubl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fsubrl	3735928559(%ebx,%ecx,8)
-        	fsubrl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fisubrl	3735928559(%ebx,%ecx,8)
-        	fisubrl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fmull	3735928559(%ebx,%ecx,8)
-        	fmull	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fimull	3735928559(%ebx,%ecx,8)
-        	fimull	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fdivl	3735928559(%ebx,%ecx,8)
-        	fdivl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fidivl	3735928559(%ebx,%ecx,8)
-        	fidivl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fdivrl	3735928559(%ebx,%ecx,8)
-        	fdivrl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fidivrl	3735928559(%ebx,%ecx,8)
-        	fidivrl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fsqrt
-        	fsqrt
-
-// CHECK: 	fsin
-        	fsin
-
-// CHECK: 	fcos
-        	fcos
-
-// CHECK: 	fchs
-        	fchs
-
-// CHECK: 	fabs
-        	fabs
-
-// CHECK: 	fldcw	3735928559(%ebx,%ecx,8)
-        	fldcw	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fnstcw	3735928559(%ebx,%ecx,8)
-        	fnstcw	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	rdtsc
-        	rdtsc
-
-// CHECK: 	sysenter
-        	sysenter
-
-// CHECK: 	sysexit
-        	sysexit
-
-// CHECK: 	sysexitl
-        	sysexitl
-
-// CHECK: 	ud2
-        	ud2
-
-// CHECK: 	movntil	%ecx, 3735928559(%ebx,%ecx,8)
-        	movnti	%ecx,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	clflush	3735928559(%ebx,%ecx,8)
-        	clflush	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	emms
-        	emms
-
-// CHECK: 	movd	%ecx, %mm3
-        	movd	%ecx,%mm3
-
-// CHECK: 	movd	3735928559(%ebx,%ecx,8), %mm3
-        	movd	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	movd	%ecx, %xmm5
-        	movd	%ecx,%xmm5
-
-// CHECK: 	movd	3735928559(%ebx,%ecx,8), %xmm5
-        	movd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movd	%xmm5, %ecx
-        	movd	%xmm5,%ecx
-
-// CHECK: 	movd	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movd	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movq	3735928559(%ebx,%ecx,8), %mm3
-        	movq	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	movq	%mm3, %mm3
-        	movq	%mm3,%mm3
-
-// CHECK: 	movq	%mm3, %mm3
-        	movq	%mm3,%mm3
-
-// CHECK: 	movq	%xmm5, %xmm5
-        	movq	%xmm5,%xmm5
-
-// CHECK: 	movq	%xmm5, %xmm5
-        	movq	%xmm5,%xmm5
-
-// CHECK: 	packssdw	%mm3, %mm3
-        	packssdw	%mm3,%mm3
-
-// CHECK: 	packssdw	%xmm5, %xmm5
-        	packssdw	%xmm5,%xmm5
-
-// CHECK: 	packsswb	%mm3, %mm3
-        	packsswb	%mm3,%mm3
-
-// CHECK: 	packsswb	%xmm5, %xmm5
-        	packsswb	%xmm5,%xmm5
-
-// CHECK: 	packuswb	%mm3, %mm3
-        	packuswb	%mm3,%mm3
-
-// CHECK: 	packuswb	%xmm5, %xmm5
-        	packuswb	%xmm5,%xmm5
-
-// CHECK: 	paddb	%mm3, %mm3
-        	paddb	%mm3,%mm3
-
-// CHECK: 	paddb	%xmm5, %xmm5
-        	paddb	%xmm5,%xmm5
-
-// CHECK: 	paddw	%mm3, %mm3
-        	paddw	%mm3,%mm3
-
-// CHECK: 	paddw	%xmm5, %xmm5
-        	paddw	%xmm5,%xmm5
-
-// CHECK: 	paddd	%mm3, %mm3
-        	paddd	%mm3,%mm3
-
-// CHECK: 	paddd	%xmm5, %xmm5
-        	paddd	%xmm5,%xmm5
-
-// CHECK: 	paddq	%mm3, %mm3
-        	paddq	%mm3,%mm3
-
-// CHECK: 	paddq	%xmm5, %xmm5
-        	paddq	%xmm5,%xmm5
-
-// CHECK: 	paddsb	%mm3, %mm3
-        	paddsb	%mm3,%mm3
-
-// CHECK: 	paddsb	%xmm5, %xmm5
-        	paddsb	%xmm5,%xmm5
-
-// CHECK: 	paddsw	%mm3, %mm3
-        	paddsw	%mm3,%mm3
-
-// CHECK: 	paddsw	%xmm5, %xmm5
-        	paddsw	%xmm5,%xmm5
-
-// CHECK: 	paddusb	%mm3, %mm3
-        	paddusb	%mm3,%mm3
-
-// CHECK: 	paddusb	%xmm5, %xmm5
-        	paddusb	%xmm5,%xmm5
-
-// CHECK: 	paddusw	%mm3, %mm3
-        	paddusw	%mm3,%mm3
-
-// CHECK: 	paddusw	%xmm5, %xmm5
-        	paddusw	%xmm5,%xmm5
-
-// CHECK: 	pand	%mm3, %mm3
-        	pand	%mm3,%mm3
-
-// CHECK: 	pand	%xmm5, %xmm5
-        	pand	%xmm5,%xmm5
-
-// CHECK: 	pandn	%mm3, %mm3
-        	pandn	%mm3,%mm3
-
-// CHECK: 	pandn	%xmm5, %xmm5
-        	pandn	%xmm5,%xmm5
-
-// CHECK: 	pcmpeqb	%mm3, %mm3
-        	pcmpeqb	%mm3,%mm3
-
-// CHECK: 	pcmpeqb	%xmm5, %xmm5
-        	pcmpeqb	%xmm5,%xmm5
-
-// CHECK: 	pcmpeqw	%mm3, %mm3
-        	pcmpeqw	%mm3,%mm3
-
-// CHECK: 	pcmpeqw	%xmm5, %xmm5
-        	pcmpeqw	%xmm5,%xmm5
-
-// CHECK: 	pcmpeqd	%mm3, %mm3
-        	pcmpeqd	%mm3,%mm3
-
-// CHECK: 	pcmpeqd	%xmm5, %xmm5
-        	pcmpeqd	%xmm5,%xmm5
-
-// CHECK: 	pcmpgtb	%mm3, %mm3
-        	pcmpgtb	%mm3,%mm3
-
-// CHECK: 	pcmpgtb	%xmm5, %xmm5
-        	pcmpgtb	%xmm5,%xmm5
-
-// CHECK: 	pcmpgtw	%mm3, %mm3
-        	pcmpgtw	%mm3,%mm3
-
-// CHECK: 	pcmpgtw	%xmm5, %xmm5
-        	pcmpgtw	%xmm5,%xmm5
-
-// CHECK: 	pcmpgtd	%mm3, %mm3
-        	pcmpgtd	%mm3,%mm3
-
-// CHECK: 	pcmpgtd	%xmm5, %xmm5
-        	pcmpgtd	%xmm5,%xmm5
-
-// CHECK: 	pmaddwd	%mm3, %mm3
-        	pmaddwd	%mm3,%mm3
-
-// CHECK: 	pmaddwd	%xmm5, %xmm5
-        	pmaddwd	%xmm5,%xmm5
-
-// CHECK: 	pmulhw	%mm3, %mm3
-        	pmulhw	%mm3,%mm3
-
-// CHECK: 	pmulhw	%xmm5, %xmm5
-        	pmulhw	%xmm5,%xmm5
-
-// CHECK: 	pmullw	%mm3, %mm3
-        	pmullw	%mm3,%mm3
-
-// CHECK: 	pmullw	%xmm5, %xmm5
-        	pmullw	%xmm5,%xmm5
-
-// CHECK: 	por	%mm3, %mm3
-        	por	%mm3,%mm3
-
-// CHECK: 	por	%xmm5, %xmm5
-        	por	%xmm5,%xmm5
-
-// CHECK: 	psllw	%mm3, %mm3
-        	psllw	%mm3,%mm3
-
-// CHECK: 	psllw	%xmm5, %xmm5
-        	psllw	%xmm5,%xmm5
-
-// CHECK: 	psllw	$127, %mm3
-        	psllw	$0x7f,%mm3
-
-// CHECK: 	psllw	$127, %xmm5
-        	psllw	$0x7f,%xmm5
-
-// CHECK: 	pslld	%mm3, %mm3
-        	pslld	%mm3,%mm3
-
-// CHECK: 	pslld	%xmm5, %xmm5
-        	pslld	%xmm5,%xmm5
-
-// CHECK: 	pslld	$127, %mm3
-        	pslld	$0x7f,%mm3
-
-// CHECK: 	pslld	$127, %xmm5
-        	pslld	$0x7f,%xmm5
-
-// CHECK: 	psllq	%mm3, %mm3
-        	psllq	%mm3,%mm3
-
-// CHECK: 	psllq	%xmm5, %xmm5
-        	psllq	%xmm5,%xmm5
-
-// CHECK: 	psllq	$127, %mm3
-        	psllq	$0x7f,%mm3
-
-// CHECK: 	psllq	$127, %xmm5
-        	psllq	$0x7f,%xmm5
-
-// CHECK: 	psraw	%mm3, %mm3
-        	psraw	%mm3,%mm3
-
-// CHECK: 	psraw	%xmm5, %xmm5
-        	psraw	%xmm5,%xmm5
-
-// CHECK: 	psraw	$127, %mm3
-        	psraw	$0x7f,%mm3
-
-// CHECK: 	psraw	$127, %xmm5
-        	psraw	$0x7f,%xmm5
-
-// CHECK: 	psrad	%mm3, %mm3
-        	psrad	%mm3,%mm3
-
-// CHECK: 	psrad	%xmm5, %xmm5
-        	psrad	%xmm5,%xmm5
-
-// CHECK: 	psrad	$127, %mm3
-        	psrad	$0x7f,%mm3
-
-// CHECK: 	psrad	$127, %xmm5
-        	psrad	$0x7f,%xmm5
-
-// CHECK: 	psrlw	%mm3, %mm3
-        	psrlw	%mm3,%mm3
-
-// CHECK: 	psrlw	%xmm5, %xmm5
-        	psrlw	%xmm5,%xmm5
-
-// CHECK: 	psrlw	$127, %mm3
-        	psrlw	$0x7f,%mm3
-
-// CHECK: 	psrlw	$127, %xmm5
-        	psrlw	$0x7f,%xmm5
-
-// CHECK: 	psrld	%mm3, %mm3
-        	psrld	%mm3,%mm3
-
-// CHECK: 	psrld	%xmm5, %xmm5
-        	psrld	%xmm5,%xmm5
-
-// CHECK: 	psrld	$127, %mm3
-        	psrld	$0x7f,%mm3
-
-// CHECK: 	psrld	$127, %xmm5
-        	psrld	$0x7f,%xmm5
-
-// CHECK: 	psrlq	%mm3, %mm3
-        	psrlq	%mm3,%mm3
-
-// CHECK: 	psrlq	%xmm5, %xmm5
-        	psrlq	%xmm5,%xmm5
-
-// CHECK: 	psrlq	$127, %mm3
-        	psrlq	$0x7f,%mm3
-
-// CHECK: 	psrlq	$127, %xmm5
-        	psrlq	$0x7f,%xmm5
-
-// CHECK: 	psubb	%mm3, %mm3
-        	psubb	%mm3,%mm3
-
-// CHECK: 	psubb	%xmm5, %xmm5
-        	psubb	%xmm5,%xmm5
-
-// CHECK: 	psubw	%mm3, %mm3
-        	psubw	%mm3,%mm3
-
-// CHECK: 	psubw	%xmm5, %xmm5
-        	psubw	%xmm5,%xmm5
-
-// CHECK: 	psubd	%mm3, %mm3
-        	psubd	%mm3,%mm3
-
-// CHECK: 	psubd	%xmm5, %xmm5
-        	psubd	%xmm5,%xmm5
-
-// CHECK: 	psubq	%mm3, %mm3
-        	psubq	%mm3,%mm3
-
-// CHECK: 	psubq	%xmm5, %xmm5
-        	psubq	%xmm5,%xmm5
-
-// CHECK: 	psubsb	%mm3, %mm3
-        	psubsb	%mm3,%mm3
-
-// CHECK: 	psubsb	%xmm5, %xmm5
-        	psubsb	%xmm5,%xmm5
-
-// CHECK: 	psubsw	%mm3, %mm3
-        	psubsw	%mm3,%mm3
-
-// CHECK: 	psubsw	%xmm5, %xmm5
-        	psubsw	%xmm5,%xmm5
-
-// CHECK: 	psubusb	%mm3, %mm3
-        	psubusb	%mm3,%mm3
-
-// CHECK: 	psubusb	%xmm5, %xmm5
-        	psubusb	%xmm5,%xmm5
-
-// CHECK: 	psubusw	%mm3, %mm3
-        	psubusw	%mm3,%mm3
-
-// CHECK: 	psubusw	%xmm5, %xmm5
-        	psubusw	%xmm5,%xmm5
-
-// CHECK: 	punpckhbw	%mm3, %mm3
-        	punpckhbw	%mm3,%mm3
-
-// CHECK: 	punpckhbw	%xmm5, %xmm5
-        	punpckhbw	%xmm5,%xmm5
-
-// CHECK: 	punpckhwd	%mm3, %mm3
-        	punpckhwd	%mm3,%mm3
-
-// CHECK: 	punpckhwd	%xmm5, %xmm5
-        	punpckhwd	%xmm5,%xmm5
-
-// CHECK: 	punpckhdq	%mm3, %mm3
-        	punpckhdq	%mm3,%mm3
-
-// CHECK: 	punpckhdq	%xmm5, %xmm5
-        	punpckhdq	%xmm5,%xmm5
-
-// CHECK: 	punpcklbw	%mm3, %mm3
-        	punpcklbw	%mm3,%mm3
-
-// CHECK: 	punpcklbw	%xmm5, %xmm5
-        	punpcklbw	%xmm5,%xmm5
-
-// CHECK: 	punpcklwd	%mm3, %mm3
-        	punpcklwd	%mm3,%mm3
-
-// CHECK: 	punpcklwd	%xmm5, %xmm5
-        	punpcklwd	%xmm5,%xmm5
-
-// CHECK: 	punpckldq	%mm3, %mm3
-        	punpckldq	%mm3,%mm3
-
-// CHECK: 	punpckldq	%xmm5, %xmm5
-        	punpckldq	%xmm5,%xmm5
-
-// CHECK: 	pxor	%mm3, %mm3
-        	pxor	%mm3,%mm3
-
-// CHECK: 	pxor	%xmm5, %xmm5
-        	pxor	%xmm5,%xmm5
-
-// CHECK: 	addps	%xmm5, %xmm5
-        	addps	%xmm5,%xmm5
-
-// CHECK: 	addss	%xmm5, %xmm5
-        	addss	%xmm5,%xmm5
-
-// CHECK: 	andnps	%xmm5, %xmm5
-        	andnps	%xmm5,%xmm5
-
-// CHECK: 	andps	%xmm5, %xmm5
-        	andps	%xmm5,%xmm5
-
-// CHECK: 	cvtpi2ps	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtpi2ps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtpi2ps	%mm3, %xmm5
-        	cvtpi2ps	%mm3,%xmm5
-
-// CHECK: 	cvtps2pi	3735928559(%ebx,%ecx,8), %mm3
-        	cvtps2pi	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	cvtps2pi	%xmm5, %mm3
-        	cvtps2pi	%xmm5,%mm3
-
-// CHECK: 	cvtsi2ssl	%ecx, %xmm5
-        	cvtsi2ssl	%ecx,%xmm5
-
-// CHECK: 	cvtsi2ssl	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtsi2ssl	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvttps2pi	3735928559(%ebx,%ecx,8), %mm3
-        	cvttps2pi	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	cvttps2pi	%xmm5, %mm3
-        	cvttps2pi	%xmm5,%mm3
-
-// CHECK: 	cvttss2si	3735928559(%ebx,%ecx,8), %ecx
-        	cvttss2si	0xdeadbeef(%ebx,%ecx,8),%ecx
-
-// CHECK: 	cvttss2si	%xmm5, %ecx
-        	cvttss2si	%xmm5,%ecx
-
-// CHECK: 	divps	%xmm5, %xmm5
-        	divps	%xmm5,%xmm5
-
-// CHECK: 	divss	%xmm5, %xmm5
-        	divss	%xmm5,%xmm5
-
-// CHECK: 	ldmxcsr	3735928559(%ebx,%ecx,8)
-        	ldmxcsr	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	maskmovq	%mm3, %mm3
-        	maskmovq	%mm3,%mm3
-
-// CHECK: 	maxps	%xmm5, %xmm5
-        	maxps	%xmm5,%xmm5
-
-// CHECK: 	maxss	%xmm5, %xmm5
-        	maxss	%xmm5,%xmm5
-
-// CHECK: 	minps	%xmm5, %xmm5
-        	minps	%xmm5,%xmm5
-
-// CHECK: 	minss	%xmm5, %xmm5
-        	minss	%xmm5,%xmm5
-
-// CHECK: 	movaps	3735928559(%ebx,%ecx,8), %xmm5
-        	movaps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movaps	%xmm5, %xmm5
-        	movaps	%xmm5,%xmm5
-
-// CHECK: 	movaps	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movaps	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movaps	%xmm5, %xmm5
-        	movaps	%xmm5,%xmm5
-
-// CHECK: 	movhlps	%xmm5, %xmm5
-        	movhlps	%xmm5,%xmm5
-
-// CHECK: 	movhps	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movhps	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movlhps	%xmm5, %xmm5
-        	movlhps	%xmm5,%xmm5
-
-// CHECK: 	movlps	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movlps	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movmskps	%xmm5, %ecx
-        	movmskps	%xmm5,%ecx
-
-// CHECK: 	movntps	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movntps	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movntq	%mm3, 3735928559(%ebx,%ecx,8)
-        	movntq	%mm3,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movntdq	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movntdq	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movss	3735928559(%ebx,%ecx,8), %xmm5
-        	movss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movss	%xmm5, %xmm5
-        	movss	%xmm5,%xmm5
-
-// CHECK: 	movss	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movss	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movss	%xmm5, %xmm5
-        	movss	%xmm5,%xmm5
-
-// CHECK: 	movups	3735928559(%ebx,%ecx,8), %xmm5
-        	movups	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movups	%xmm5, %xmm5
-        	movups	%xmm5,%xmm5
-
-// CHECK: 	movups	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movups	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movups	%xmm5, %xmm5
-        	movups	%xmm5,%xmm5
-
-// CHECK: 	mulps	%xmm5, %xmm5
-        	mulps	%xmm5,%xmm5
-
-// CHECK: 	mulss	%xmm5, %xmm5
-        	mulss	%xmm5,%xmm5
-
-// CHECK: 	orps	%xmm5, %xmm5
-        	orps	%xmm5,%xmm5
-
-// CHECK: 	pavgb	%mm3, %mm3
-        	pavgb	%mm3,%mm3
-
-// CHECK: 	pavgb	%xmm5, %xmm5
-        	pavgb	%xmm5,%xmm5
-
-// CHECK: 	pavgw	%mm3, %mm3
-        	pavgw	%mm3,%mm3
-
-// CHECK: 	pavgw	%xmm5, %xmm5
-        	pavgw	%xmm5,%xmm5
-
-// CHECK: 	pmaxsw	%mm3, %mm3
-        	pmaxsw	%mm3,%mm3
-
-// CHECK: 	pmaxsw	%xmm5, %xmm5
-        	pmaxsw	%xmm5,%xmm5
-
-// CHECK: 	pmaxub	%mm3, %mm3
-        	pmaxub	%mm3,%mm3
-
-// CHECK: 	pmaxub	%xmm5, %xmm5
-        	pmaxub	%xmm5,%xmm5
-
-// CHECK: 	pminsw	%mm3, %mm3
-        	pminsw	%mm3,%mm3
-
-// CHECK: 	pminsw	%xmm5, %xmm5
-        	pminsw	%xmm5,%xmm5
-
-// CHECK: 	pminub	%mm3, %mm3
-        	pminub	%mm3,%mm3
-
-// CHECK: 	pminub	%xmm5, %xmm5
-        	pminub	%xmm5,%xmm5
-
-// CHECK: 	pmovmskb	%mm3, %ecx
-        	pmovmskb	%mm3,%ecx
-
-// CHECK: 	pmovmskb	%xmm5, %ecx
-        	pmovmskb	%xmm5,%ecx
-
-// CHECK: 	pmulhuw	%mm3, %mm3
-        	pmulhuw	%mm3,%mm3
-
-// CHECK: 	pmulhuw	%xmm5, %xmm5
-        	pmulhuw	%xmm5,%xmm5
-
-// CHECK: 	prefetchnta	3735928559(%ebx,%ecx,8)
-        	prefetchnta	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	prefetcht0	3735928559(%ebx,%ecx,8)
-        	prefetcht0	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	prefetcht1	3735928559(%ebx,%ecx,8)
-        	prefetcht1	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	prefetcht2	3735928559(%ebx,%ecx,8)
-        	prefetcht2	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	psadbw	%mm3, %mm3
-        	psadbw	%mm3,%mm3
-
-// CHECK: 	psadbw	%xmm5, %xmm5
-        	psadbw	%xmm5,%xmm5
-
-// CHECK: 	rcpps	3735928559(%ebx,%ecx,8), %xmm5
-        	rcpps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	rcpps	%xmm5, %xmm5
-        	rcpps	%xmm5,%xmm5
-
-// CHECK: 	rcpss	3735928559(%ebx,%ecx,8), %xmm5
-        	rcpss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	rcpss	%xmm5, %xmm5
-        	rcpss	%xmm5,%xmm5
-
-// CHECK: 	rsqrtps	3735928559(%ebx,%ecx,8), %xmm5
-        	rsqrtps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	rsqrtps	%xmm5, %xmm5
-        	rsqrtps	%xmm5,%xmm5
-
-// CHECK: 	rsqrtss	3735928559(%ebx,%ecx,8), %xmm5
-        	rsqrtss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	rsqrtss	%xmm5, %xmm5
-        	rsqrtss	%xmm5,%xmm5
-
-// CHECK: 	sqrtps	3735928559(%ebx,%ecx,8), %xmm5
-        	sqrtps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	sqrtps	%xmm5, %xmm5
-        	sqrtps	%xmm5,%xmm5
-
-// CHECK: 	sqrtss	3735928559(%ebx,%ecx,8), %xmm5
-        	sqrtss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	sqrtss	%xmm5, %xmm5
-        	sqrtss	%xmm5,%xmm5
-
-// CHECK: 	stmxcsr	3735928559(%ebx,%ecx,8)
-        	stmxcsr	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	subps	%xmm5, %xmm5
-        	subps	%xmm5,%xmm5
-
-// CHECK: 	subss	%xmm5, %xmm5
-        	subss	%xmm5,%xmm5
-
-// CHECK: 	ucomiss	3735928559(%ebx,%ecx,8), %xmm5
-        	ucomiss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	ucomiss	%xmm5, %xmm5
-        	ucomiss	%xmm5,%xmm5
-
-// CHECK: 	unpckhps	%xmm5, %xmm5
-        	unpckhps	%xmm5,%xmm5
-
-// CHECK: 	unpcklps	%xmm5, %xmm5
-        	unpcklps	%xmm5,%xmm5
-
-// CHECK: 	xorps	%xmm5, %xmm5
-        	xorps	%xmm5,%xmm5
-
-// CHECK: 	addpd	%xmm5, %xmm5
-        	addpd	%xmm5,%xmm5
-
-// CHECK: 	addsd	%xmm5, %xmm5
-        	addsd	%xmm5,%xmm5
-
-// CHECK: 	andnpd	%xmm5, %xmm5
-        	andnpd	%xmm5,%xmm5
-
-// CHECK: 	andpd	%xmm5, %xmm5
-        	andpd	%xmm5,%xmm5
-
-// CHECK: 	comisd	3735928559(%ebx,%ecx,8), %xmm5
-        	comisd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	comisd	%xmm5, %xmm5
-        	comisd	%xmm5,%xmm5
-
-// CHECK: 	cvtpi2pd	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtpi2pd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtpi2pd	%mm3, %xmm5
-        	cvtpi2pd	%mm3,%xmm5
-
-// CHECK: 	cvtsi2sdl	%ecx, %xmm5
-        	cvtsi2sdl	%ecx,%xmm5
-
-// CHECK: 	cvtsi2sdl	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtsi2sdl	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	divpd	%xmm5, %xmm5
-        	divpd	%xmm5,%xmm5
-
-// CHECK: 	divsd	%xmm5, %xmm5
-        	divsd	%xmm5,%xmm5
-
-// CHECK: 	maxpd	%xmm5, %xmm5
-        	maxpd	%xmm5,%xmm5
-
-// CHECK: 	maxsd	%xmm5, %xmm5
-        	maxsd	%xmm5,%xmm5
-
-// CHECK: 	minpd	%xmm5, %xmm5
-        	minpd	%xmm5,%xmm5
-
-// CHECK: 	minsd	%xmm5, %xmm5
-        	minsd	%xmm5,%xmm5
-
-// CHECK: 	movapd	3735928559(%ebx,%ecx,8), %xmm5
-        	movapd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movapd	%xmm5, %xmm5
-        	movapd	%xmm5,%xmm5
-
-// CHECK: 	movapd	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movapd	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movapd	%xmm5, %xmm5
-        	movapd	%xmm5,%xmm5
-
-// CHECK: 	movhpd	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movhpd	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movlpd	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movlpd	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movmskpd	%xmm5, %ecx
-        	movmskpd	%xmm5,%ecx
-
-// CHECK: 	movntpd	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movntpd	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movsd	3735928559(%ebx,%ecx,8), %xmm5
-        	movsd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movsd	%xmm5, %xmm5
-        	movsd	%xmm5,%xmm5
-
-// CHECK: 	movsd	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movsd	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movsd	%xmm5, %xmm5
-        	movsd	%xmm5,%xmm5
-
-// CHECK: 	movupd	3735928559(%ebx,%ecx,8), %xmm5
-        	movupd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movupd	%xmm5, %xmm5
-        	movupd	%xmm5,%xmm5
-
-// CHECK: 	movupd	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movupd	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movupd	%xmm5, %xmm5
-        	movupd	%xmm5,%xmm5
-
-// CHECK: 	mulpd	%xmm5, %xmm5
-        	mulpd	%xmm5,%xmm5
-
-// CHECK: 	mulsd	%xmm5, %xmm5
-        	mulsd	%xmm5,%xmm5
-
-// CHECK: 	orpd	%xmm5, %xmm5
-        	orpd	%xmm5,%xmm5
-
-// CHECK: 	sqrtpd	3735928559(%ebx,%ecx,8), %xmm5
-        	sqrtpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	sqrtpd	%xmm5, %xmm5
-        	sqrtpd	%xmm5,%xmm5
-
-// CHECK: 	sqrtsd	3735928559(%ebx,%ecx,8), %xmm5
-        	sqrtsd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	sqrtsd	%xmm5, %xmm5
-        	sqrtsd	%xmm5,%xmm5
-
-// CHECK: 	subpd	%xmm5, %xmm5
-        	subpd	%xmm5,%xmm5
-
-// CHECK: 	subsd	%xmm5, %xmm5
-        	subsd	%xmm5,%xmm5
-
-// CHECK: 	ucomisd	3735928559(%ebx,%ecx,8), %xmm5
-        	ucomisd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	ucomisd	%xmm5, %xmm5
-        	ucomisd	%xmm5,%xmm5
-
-// CHECK: 	unpckhpd	%xmm5, %xmm5
-        	unpckhpd	%xmm5,%xmm5
-
-// CHECK: 	unpcklpd	%xmm5, %xmm5
-        	unpcklpd	%xmm5,%xmm5
-
-// CHECK: 	xorpd	%xmm5, %xmm5
-        	xorpd	%xmm5,%xmm5
-
-// CHECK: 	cvtdq2pd	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtdq2pd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtdq2pd	%xmm5, %xmm5
-        	cvtdq2pd	%xmm5,%xmm5
-
-// CHECK: 	cvtpd2dq	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtpd2dq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtpd2dq	%xmm5, %xmm5
-        	cvtpd2dq	%xmm5,%xmm5
-
-// CHECK: 	cvtdq2ps	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtdq2ps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtdq2ps	%xmm5, %xmm5
-        	cvtdq2ps	%xmm5,%xmm5
-
-// CHECK: 	cvtpd2pi	3735928559(%ebx,%ecx,8), %mm3
-        	cvtpd2pi	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	cvtpd2pi	%xmm5, %mm3
-        	cvtpd2pi	%xmm5,%mm3
-
-// CHECK: 	cvtps2dq	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtps2dq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtps2dq	%xmm5, %xmm5
-        	cvtps2dq	%xmm5,%xmm5
-
-// CHECK: 	cvtsd2ss	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtsd2ss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtsd2ss	%xmm5, %xmm5
-        	cvtsd2ss	%xmm5,%xmm5
-
-// CHECK: 	cvtss2sd	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtss2sd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtss2sd	%xmm5, %xmm5
-        	cvtss2sd	%xmm5,%xmm5
-
-// CHECK: 	cvttpd2pi	3735928559(%ebx,%ecx,8), %mm3
-        	cvttpd2pi	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	cvttpd2pi	%xmm5, %mm3
-        	cvttpd2pi	%xmm5,%mm3
-
-// CHECK: 	cvttsd2si	3735928559(%ebx,%ecx,8), %ecx
-        	cvttsd2si	0xdeadbeef(%ebx,%ecx,8),%ecx
-
-// CHECK: 	cvttsd2si	%xmm5, %ecx
-        	cvttsd2si	%xmm5,%ecx
-
-// CHECK: 	maskmovdqu	%xmm5, %xmm5
-        	maskmovdqu	%xmm5,%xmm5
-
-// CHECK: 	movdqa	3735928559(%ebx,%ecx,8), %xmm5
-        	movdqa	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movdqa	%xmm5, %xmm5
-        	movdqa	%xmm5,%xmm5
-
-// CHECK: 	movdqa	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movdqa	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movdqa	%xmm5, %xmm5
-        	movdqa	%xmm5,%xmm5
-
-// CHECK: 	movdqu	3735928559(%ebx,%ecx,8), %xmm5
-        	movdqu	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movdqu	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movdqu	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movdq2q	%xmm5, %mm3
-        	movdq2q	%xmm5,%mm3
-
-// CHECK: 	movq2dq	%mm3, %xmm5
-        	movq2dq	%mm3,%xmm5
-
-// CHECK: 	pmuludq	%mm3, %mm3
-        	pmuludq	%mm3,%mm3
-
-// CHECK: 	pmuludq	%xmm5, %xmm5
-        	pmuludq	%xmm5,%xmm5
-
-// CHECK: 	pslldq	$127, %xmm5
-        	pslldq	$0x7f,%xmm5
-
-// CHECK: 	psrldq	$127, %xmm5
-        	psrldq	$0x7f,%xmm5
-
-// CHECK: 	punpckhqdq	%xmm5, %xmm5
-        	punpckhqdq	%xmm5,%xmm5
-
-// CHECK: 	punpcklqdq	%xmm5, %xmm5
-        	punpcklqdq	%xmm5,%xmm5
-
-// CHECK: 	addsubpd	%xmm5, %xmm5
-        	addsubpd	%xmm5,%xmm5
-
-// CHECK: 	addsubps	%xmm5, %xmm5
-        	addsubps	%xmm5,%xmm5
-
-// CHECK: 	haddpd	%xmm5, %xmm5
-        	haddpd	%xmm5,%xmm5
-
-// CHECK: 	haddps	%xmm5, %xmm5
-        	haddps	%xmm5,%xmm5
-
-// CHECK: 	hsubpd	%xmm5, %xmm5
-        	hsubpd	%xmm5,%xmm5
-
-// CHECK: 	hsubps	%xmm5, %xmm5
-        	hsubps	%xmm5,%xmm5
-
-// CHECK: 	lddqu	3735928559(%ebx,%ecx,8), %xmm5
-        	lddqu	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movddup	3735928559(%ebx,%ecx,8), %xmm5
-        	movddup	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movddup	%xmm5, %xmm5
-        	movddup	%xmm5,%xmm5
-
-// CHECK: 	movshdup	3735928559(%ebx,%ecx,8), %xmm5
-        	movshdup	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movshdup	%xmm5, %xmm5
-        	movshdup	%xmm5,%xmm5
-
-// CHECK: 	movsldup	3735928559(%ebx,%ecx,8), %xmm5
-        	movsldup	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movsldup	%xmm5, %xmm5
-        	movsldup	%xmm5,%xmm5
-
-// CHECK: 	phaddw	%mm3, %mm3
-        	phaddw	%mm3,%mm3
-
-// CHECK: 	phaddw	%xmm5, %xmm5
-        	phaddw	%xmm5,%xmm5
-
-// CHECK: 	phaddd	%mm3, %mm3
-        	phaddd	%mm3,%mm3
-
-// CHECK: 	phaddd	%xmm5, %xmm5
-        	phaddd	%xmm5,%xmm5
-
-// CHECK: 	phaddsw	%mm3, %mm3
-        	phaddsw	%mm3,%mm3
-
-// CHECK: 	phaddsw	%xmm5, %xmm5
-        	phaddsw	%xmm5,%xmm5
-
-// CHECK: 	phsubw	%mm3, %mm3
-        	phsubw	%mm3,%mm3
-
-// CHECK: 	phsubw	%xmm5, %xmm5
-        	phsubw	%xmm5,%xmm5
-
-// CHECK: 	phsubd	%mm3, %mm3
-        	phsubd	%mm3,%mm3
-
-// CHECK: 	phsubd	%xmm5, %xmm5
-        	phsubd	%xmm5,%xmm5
-
-// CHECK: 	phsubsw	%mm3, %mm3
-        	phsubsw	%mm3,%mm3
-
-// CHECK: 	phsubsw	%xmm5, %xmm5
-        	phsubsw	%xmm5,%xmm5
-
-// CHECK: 	pmaddubsw	%mm3, %mm3
-        	pmaddubsw	%mm3,%mm3
-
-// CHECK: 	pmaddubsw	%xmm5, %xmm5
-        	pmaddubsw	%xmm5,%xmm5
-
-// CHECK: 	pmulhrsw	%mm3, %mm3
-        	pmulhrsw	%mm3,%mm3
-
-// CHECK: 	pmulhrsw	%xmm5, %xmm5
-        	pmulhrsw	%xmm5,%xmm5
-
-// CHECK: 	pshufb	%mm3, %mm3
-        	pshufb	%mm3,%mm3
-
-// CHECK: 	pshufb	%xmm5, %xmm5
-        	pshufb	%xmm5,%xmm5
-
-// CHECK: 	psignb	%mm3, %mm3
-        	psignb	%mm3,%mm3
-
-// CHECK: 	psignb	%xmm5, %xmm5
-        	psignb	%xmm5,%xmm5
-
-// CHECK: 	psignw	%mm3, %mm3
-        	psignw	%mm3,%mm3
-
-// CHECK: 	psignw	%xmm5, %xmm5
-        	psignw	%xmm5,%xmm5
-
-// CHECK: 	psignd	%mm3, %mm3
-        	psignd	%mm3,%mm3
-
-// CHECK: 	psignd	%xmm5, %xmm5
-        	psignd	%xmm5,%xmm5
-
-// CHECK: 	pabsb	3735928559(%ebx,%ecx,8), %mm3
-        	pabsb	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pabsb	%mm3, %mm3
-        	pabsb	%mm3,%mm3
-
-// CHECK: 	pabsb	3735928559(%ebx,%ecx,8), %xmm5
-        	pabsb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pabsb	%xmm5, %xmm5
-        	pabsb	%xmm5,%xmm5
-
-// CHECK: 	pabsw	3735928559(%ebx,%ecx,8), %mm3
-        	pabsw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pabsw	%mm3, %mm3
-        	pabsw	%mm3,%mm3
-
-// CHECK: 	pabsw	3735928559(%ebx,%ecx,8), %xmm5
-        	pabsw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pabsw	%xmm5, %xmm5
-        	pabsw	%xmm5,%xmm5
-
-// CHECK: 	pabsd	3735928559(%ebx,%ecx,8), %mm3
-        	pabsd	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pabsd	%mm3, %mm3
-        	pabsd	%mm3,%mm3
-
-// CHECK: 	pabsd	3735928559(%ebx,%ecx,8), %xmm5
-        	pabsd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pabsd	%xmm5, %xmm5
-        	pabsd	%xmm5,%xmm5
-
-// CHECK: 	femms
-        	femms
-
-// CHECK: 	packusdw	%xmm5, %xmm5
-        	packusdw	%xmm5,%xmm5
-
-// CHECK: 	pcmpeqq	%xmm5, %xmm5
-        	pcmpeqq	%xmm5,%xmm5
-
-// CHECK: 	phminposuw	3735928559(%ebx,%ecx,8), %xmm5
-        	phminposuw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	phminposuw	%xmm5, %xmm5
-        	phminposuw	%xmm5,%xmm5
-
-// CHECK: 	pmaxsb	%xmm5, %xmm5
-        	pmaxsb	%xmm5,%xmm5
-
-// CHECK: 	pmaxsd	%xmm5, %xmm5
-        	pmaxsd	%xmm5,%xmm5
-
-// CHECK: 	pmaxud	%xmm5, %xmm5
-        	pmaxud	%xmm5,%xmm5
-
-// CHECK: 	pmaxuw	%xmm5, %xmm5
-        	pmaxuw	%xmm5,%xmm5
-
-// CHECK: 	pminsb	%xmm5, %xmm5
-        	pminsb	%xmm5,%xmm5
-
-// CHECK: 	pminsd	%xmm5, %xmm5
-        	pminsd	%xmm5,%xmm5
-
-// CHECK: 	pminud	%xmm5, %xmm5
-        	pminud	%xmm5,%xmm5
-
-// CHECK: 	pminuw	%xmm5, %xmm5
-        	pminuw	%xmm5,%xmm5
-
-// CHECK: 	pmovsxbw	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovsxbw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovsxbw	%xmm5, %xmm5
-        	pmovsxbw	%xmm5,%xmm5
-
-// CHECK: 	pmovsxbd	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovsxbd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovsxbd	%xmm5, %xmm5
-        	pmovsxbd	%xmm5,%xmm5
-
-// CHECK: 	pmovsxbq	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovsxbq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovsxbq	%xmm5, %xmm5
-        	pmovsxbq	%xmm5,%xmm5
-
-// CHECK: 	pmovsxwd	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovsxwd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovsxwd	%xmm5, %xmm5
-        	pmovsxwd	%xmm5,%xmm5
-
-// CHECK: 	pmovsxwq	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovsxwq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovsxwq	%xmm5, %xmm5
-        	pmovsxwq	%xmm5,%xmm5
-
-// CHECK: 	pmovsxdq	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovsxdq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovsxdq	%xmm5, %xmm5
-        	pmovsxdq	%xmm5,%xmm5
-
-// CHECK: 	pmovzxbw	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovzxbw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovzxbw	%xmm5, %xmm5
-        	pmovzxbw	%xmm5,%xmm5
-
-// CHECK: 	pmovzxbd	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovzxbd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovzxbd	%xmm5, %xmm5
-        	pmovzxbd	%xmm5,%xmm5
-
-// CHECK: 	pmovzxbq	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovzxbq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovzxbq	%xmm5, %xmm5
-        	pmovzxbq	%xmm5,%xmm5
-
-// CHECK: 	pmovzxwd	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovzxwd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovzxwd	%xmm5, %xmm5
-        	pmovzxwd	%xmm5,%xmm5
-
-// CHECK: 	pmovzxwq	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovzxwq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovzxwq	%xmm5, %xmm5
-        	pmovzxwq	%xmm5,%xmm5
-
-// CHECK: 	pmovzxdq	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovzxdq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovzxdq	%xmm5, %xmm5
-        	pmovzxdq	%xmm5,%xmm5
-
-// CHECK: 	pmuldq	%xmm5, %xmm5
-        	pmuldq	%xmm5,%xmm5
-
-// CHECK: 	pmulld	%xmm5, %xmm5
-        	pmulld	%xmm5,%xmm5
-
-// CHECK: 	ptest 	3735928559(%ebx,%ecx,8), %xmm5
-        	ptest	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	ptest 	%xmm5, %xmm5
-        	ptest	%xmm5,%xmm5
-
-// CHECK: 	pcmpgtq	%xmm5, %xmm5
-        	pcmpgtq	%xmm5,%xmm5
-
-
 // CHECK: movb	$127, 3735928559(%ebx,%ecx,8)
 // CHECK:  encoding: [0xc6,0x84,0xcb,0xef,0xbe,0xad,0xde,0x7f]
         	movb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
@@ -4708,10 +3072,6 @@
 // CHECK:  encoding: [0x66,0x0f,0xd6,0x2d,0x78,0x56,0x34,0x12]
         	movq	%xmm5,0x12345678
 
-// CHECK: movq	%xmm5, %xmm5
-// CHECK:  encoding: [0xf3,0x0f,0x7e,0xed]
-        	movq	%xmm5,%xmm5
-
 // CHECK: packssdw	3735928559(%ebx,%ecx,8), %mm3
 // CHECK:  encoding: [0x0f,0x6b,0x9c,0xcb,0xef,0xbe,0xad,0xde]
         	packssdw	0xdeadbeef(%ebx,%ecx,8),%mm3
@@ -7432,10 +5792,6 @@
 // CHECK:  encoding: [0x0f,0x29,0x2d,0x78,0x56,0x34,0x12]
         	movaps	%xmm5,0x12345678
 
-// CHECK: movaps	%xmm5, %xmm5
-// CHECK:  encoding: [0x0f,0x28,0xed]
-        	movaps	%xmm5,%xmm5
-
 // CHECK: movhlps	%xmm5, %xmm5
 // CHECK:  encoding: [0x0f,0x12,0xed]
         	movhlps	%xmm5,%xmm5
@@ -9986,205 +8342,205 @@
 
 // CHECK: hsubps	%xmm5, %xmm5
 // CHECK:  encoding: [0xf2,0x0f,0x7d,0xed]
-        	hsubps	%xmm5,%xmm5
+                  hsubps	%xmm5,%xmm5
 
-// CHECK: lddqu	3735928559(%ebx,%ecx,8), %xmm5
-// CHECK:  encoding: [0xf2,0x0f,0xf0,0xac,0xcb,0xef,0xbe,0xad,0xde]
-        	lddqu	0xdeadbeef(%ebx,%ecx,8),%xmm5
+  // CHECK: lddqu	3735928559(%ebx,%ecx,8), %xmm5
+  // CHECK:  encoding: [0xf2,0x0f,0xf0,0xac,0xcb,0xef,0xbe,0xad,0xde]
+                  lddqu	0xdeadbeef(%ebx,%ecx,8),%xmm5
 
-// CHECK: lddqu	69, %xmm5
-// CHECK:  encoding: [0xf2,0x0f,0xf0,0x2d,0x45,0x00,0x00,0x00]
-        	lddqu	0x45,%xmm5
+  // CHECK: lddqu	69, %xmm5
+  // CHECK:  encoding: [0xf2,0x0f,0xf0,0x2d,0x45,0x00,0x00,0x00]
+                  lddqu	0x45,%xmm5
 
-// CHECK: lddqu	32493, %xmm5
-// CHECK:  encoding: [0xf2,0x0f,0xf0,0x2d,0xed,0x7e,0x00,0x00]
-        	lddqu	0x7eed,%xmm5
+  // CHECK: lddqu	32493, %xmm5
+  // CHECK:  encoding: [0xf2,0x0f,0xf0,0x2d,0xed,0x7e,0x00,0x00]
+                  lddqu	0x7eed,%xmm5
 
-// CHECK: lddqu	3133065982, %xmm5
-// CHECK:  encoding: [0xf2,0x0f,0xf0,0x2d,0xfe,0xca,0xbe,0xba]
-        	lddqu	0xbabecafe,%xmm5
+  // CHECK: lddqu	3133065982, %xmm5
+  // CHECK:  encoding: [0xf2,0x0f,0xf0,0x2d,0xfe,0xca,0xbe,0xba]
+                  lddqu	0xbabecafe,%xmm5
 
-// CHECK: lddqu	305419896, %xmm5
-// CHECK:  encoding: [0xf2,0x0f,0xf0,0x2d,0x78,0x56,0x34,0x12]
-        	lddqu	0x12345678,%xmm5
+  // CHECK: lddqu	305419896, %xmm5
+  // CHECK:  encoding: [0xf2,0x0f,0xf0,0x2d,0x78,0x56,0x34,0x12]
+                  lddqu	0x12345678,%xmm5
 
-// CHECK: movddup	3735928559(%ebx,%ecx,8), %xmm5
-// CHECK:  encoding: [0xf2,0x0f,0x12,0xac,0xcb,0xef,0xbe,0xad,0xde]
-        	movddup	0xdeadbeef(%ebx,%ecx,8),%xmm5
+  // CHECK: movddup	3735928559(%ebx,%ecx,8), %xmm5
+  // CHECK:  encoding: [0xf2,0x0f,0x12,0xac,0xcb,0xef,0xbe,0xad,0xde]
+                  movddup	0xdeadbeef(%ebx,%ecx,8),%xmm5
 
-// CHECK: movddup	69, %xmm5
-// CHECK:  encoding: [0xf2,0x0f,0x12,0x2d,0x45,0x00,0x00,0x00]
-        	movddup	0x45,%xmm5
+  // CHECK: movddup	69, %xmm5
+  // CHECK:  encoding: [0xf2,0x0f,0x12,0x2d,0x45,0x00,0x00,0x00]
+                  movddup	0x45,%xmm5
 
-// CHECK: movddup	32493, %xmm5
-// CHECK:  encoding: [0xf2,0x0f,0x12,0x2d,0xed,0x7e,0x00,0x00]
-        	movddup	0x7eed,%xmm5
+  // CHECK: movddup	32493, %xmm5
+  // CHECK:  encoding: [0xf2,0x0f,0x12,0x2d,0xed,0x7e,0x00,0x00]
+                  movddup	0x7eed,%xmm5
 
-// CHECK: movddup	3133065982, %xmm5
-// CHECK:  encoding: [0xf2,0x0f,0x12,0x2d,0xfe,0xca,0xbe,0xba]
-        	movddup	0xbabecafe,%xmm5
+  // CHECK: movddup	3133065982, %xmm5
+  // CHECK:  encoding: [0xf2,0x0f,0x12,0x2d,0xfe,0xca,0xbe,0xba]
+                  movddup	0xbabecafe,%xmm5
 
-// CHECK: movddup	305419896, %xmm5
-// CHECK:  encoding: [0xf2,0x0f,0x12,0x2d,0x78,0x56,0x34,0x12]
-        	movddup	0x12345678,%xmm5
+  // CHECK: movddup	305419896, %xmm5
+  // CHECK:  encoding: [0xf2,0x0f,0x12,0x2d,0x78,0x56,0x34,0x12]
+                  movddup	0x12345678,%xmm5
 
-// CHECK: movddup	%xmm5, %xmm5
-// CHECK:  encoding: [0xf2,0x0f,0x12,0xed]
-        	movddup	%xmm5,%xmm5
+  // CHECK: movddup	%xmm5, %xmm5
+  // CHECK:  encoding: [0xf2,0x0f,0x12,0xed]
+                  movddup	%xmm5,%xmm5
 
-// CHECK: movshdup	3735928559(%ebx,%ecx,8), %xmm5
-// CHECK:  encoding: [0xf3,0x0f,0x16,0xac,0xcb,0xef,0xbe,0xad,0xde]
-        	movshdup	0xdeadbeef(%ebx,%ecx,8),%xmm5
+  // CHECK: movshdup	3735928559(%ebx,%ecx,8), %xmm5
+  // CHECK:  encoding: [0xf3,0x0f,0x16,0xac,0xcb,0xef,0xbe,0xad,0xde]
+                  movshdup	0xdeadbeef(%ebx,%ecx,8),%xmm5
 
-// CHECK: movshdup	69, %xmm5
-// CHECK:  encoding: [0xf3,0x0f,0x16,0x2d,0x45,0x00,0x00,0x00]
-        	movshdup	0x45,%xmm5
+  // CHECK: movshdup	69, %xmm5
+  // CHECK:  encoding: [0xf3,0x0f,0x16,0x2d,0x45,0x00,0x00,0x00]
+                  movshdup	0x45,%xmm5
 
-// CHECK: movshdup	32493, %xmm5
-// CHECK:  encoding: [0xf3,0x0f,0x16,0x2d,0xed,0x7e,0x00,0x00]
-        	movshdup	0x7eed,%xmm5
+  // CHECK: movshdup	32493, %xmm5
+  // CHECK:  encoding: [0xf3,0x0f,0x16,0x2d,0xed,0x7e,0x00,0x00]
+                  movshdup	0x7eed,%xmm5
 
-// CHECK: movshdup	3133065982, %xmm5
-// CHECK:  encoding: [0xf3,0x0f,0x16,0x2d,0xfe,0xca,0xbe,0xba]
-        	movshdup	0xbabecafe,%xmm5
+  // CHECK: movshdup	3133065982, %xmm5
+  // CHECK:  encoding: [0xf3,0x0f,0x16,0x2d,0xfe,0xca,0xbe,0xba]
+                  movshdup	0xbabecafe,%xmm5
 
-// CHECK: movshdup	305419896, %xmm5
-// CHECK:  encoding: [0xf3,0x0f,0x16,0x2d,0x78,0x56,0x34,0x12]
-        	movshdup	0x12345678,%xmm5
+  // CHECK: movshdup	305419896, %xmm5
+  // CHECK:  encoding: [0xf3,0x0f,0x16,0x2d,0x78,0x56,0x34,0x12]
+                  movshdup	0x12345678,%xmm5
 
-// CHECK: movshdup	%xmm5, %xmm5
-// CHECK:  encoding: [0xf3,0x0f,0x16,0xed]
-        	movshdup	%xmm5,%xmm5
+  // CHECK: movshdup	%xmm5, %xmm5
+  // CHECK:  encoding: [0xf3,0x0f,0x16,0xed]
+                  movshdup	%xmm5,%xmm5
 
-// CHECK: movsldup	3735928559(%ebx,%ecx,8), %xmm5
-// CHECK:  encoding: [0xf3,0x0f,0x12,0xac,0xcb,0xef,0xbe,0xad,0xde]
-        	movsldup	0xdeadbeef(%ebx,%ecx,8),%xmm5
+  // CHECK: movsldup	3735928559(%ebx,%ecx,8), %xmm5
+  // CHECK:  encoding: [0xf3,0x0f,0x12,0xac,0xcb,0xef,0xbe,0xad,0xde]
+                  movsldup	0xdeadbeef(%ebx,%ecx,8),%xmm5
 
-// CHECK: movsldup	69, %xmm5
-// CHECK:  encoding: [0xf3,0x0f,0x12,0x2d,0x45,0x00,0x00,0x00]
-        	movsldup	0x45,%xmm5
+  // CHECK: movsldup	69, %xmm5
+  // CHECK:  encoding: [0xf3,0x0f,0x12,0x2d,0x45,0x00,0x00,0x00]
+                  movsldup	0x45,%xmm5
 
-// CHECK: movsldup	32493, %xmm5
-// CHECK:  encoding: [0xf3,0x0f,0x12,0x2d,0xed,0x7e,0x00,0x00]
-        	movsldup	0x7eed,%xmm5
+  // CHECK: movsldup	32493, %xmm5
+  // CHECK:  encoding: [0xf3,0x0f,0x12,0x2d,0xed,0x7e,0x00,0x00]
+                  movsldup	0x7eed,%xmm5
 
-// CHECK: movsldup	3133065982, %xmm5
-// CHECK:  encoding: [0xf3,0x0f,0x12,0x2d,0xfe,0xca,0xbe,0xba]
-        	movsldup	0xbabecafe,%xmm5
+  // CHECK: movsldup	3133065982, %xmm5
+  // CHECK:  encoding: [0xf3,0x0f,0x12,0x2d,0xfe,0xca,0xbe,0xba]
+                  movsldup	0xbabecafe,%xmm5
 
-// CHECK: movsldup	305419896, %xmm5
-// CHECK:  encoding: [0xf3,0x0f,0x12,0x2d,0x78,0x56,0x34,0x12]
-        	movsldup	0x12345678,%xmm5
+  // CHECK: movsldup	305419896, %xmm5
+  // CHECK:  encoding: [0xf3,0x0f,0x12,0x2d,0x78,0x56,0x34,0x12]
+                  movsldup	0x12345678,%xmm5
 
-// CHECK: movsldup	%xmm5, %xmm5
-// CHECK:  encoding: [0xf3,0x0f,0x12,0xed]
-        	movsldup	%xmm5,%xmm5
+  // CHECK: movsldup	%xmm5, %xmm5
+  // CHECK:  encoding: [0xf3,0x0f,0x12,0xed]
+                  movsldup	%xmm5,%xmm5
 
-// CHECK: vmclear	3735928559(%ebx,%ecx,8)
-// CHECK:  encoding: [0x66,0x0f,0xc7,0xb4,0xcb,0xef,0xbe,0xad,0xde]
-        	vmclear	0xdeadbeef(%ebx,%ecx,8)
+  // CHECK: vmclear	3735928559(%ebx,%ecx,8)
+  // CHECK:  encoding: [0x66,0x0f,0xc7,0xb4,0xcb,0xef,0xbe,0xad,0xde]
+                  vmclear	0xdeadbeef(%ebx,%ecx,8)
 
-// CHECK: vmclear	32493
-// CHECK:  encoding: [0x66,0x0f,0xc7,0x35,0xed,0x7e,0x00,0x00]
-        	vmclear	0x7eed
+  // CHECK: vmclear	32493
+  // CHECK:  encoding: [0x66,0x0f,0xc7,0x35,0xed,0x7e,0x00,0x00]
+                  vmclear	0x7eed
 
-// CHECK: vmclear	3133065982
-// CHECK:  encoding: [0x66,0x0f,0xc7,0x35,0xfe,0xca,0xbe,0xba]
-        	vmclear	0xbabecafe
+  // CHECK: vmclear	3133065982
+  // CHECK:  encoding: [0x66,0x0f,0xc7,0x35,0xfe,0xca,0xbe,0xba]
+                  vmclear	0xbabecafe
 
-// CHECK: vmclear	305419896
-// CHECK:  encoding: [0x66,0x0f,0xc7,0x35,0x78,0x56,0x34,0x12]
-        	vmclear	0x12345678
+  // CHECK: vmclear	305419896
+  // CHECK:  encoding: [0x66,0x0f,0xc7,0x35,0x78,0x56,0x34,0x12]
+                  vmclear	0x12345678
 
-// CHECK: vmptrld	3735928559(%ebx,%ecx,8)
-// CHECK:  encoding: [0x0f,0xc7,0xb4,0xcb,0xef,0xbe,0xad,0xde]
-        	vmptrld	0xdeadbeef(%ebx,%ecx,8)
+  // CHECK: vmptrld	3735928559(%ebx,%ecx,8)
+  // CHECK:  encoding: [0x0f,0xc7,0xb4,0xcb,0xef,0xbe,0xad,0xde]
+                  vmptrld	0xdeadbeef(%ebx,%ecx,8)
 
-// CHECK: vmptrld	32493
-// CHECK:  encoding: [0x0f,0xc7,0x35,0xed,0x7e,0x00,0x00]
-        	vmptrld	0x7eed
+  // CHECK: vmptrld	32493
+  // CHECK:  encoding: [0x0f,0xc7,0x35,0xed,0x7e,0x00,0x00]
+                  vmptrld	0x7eed
 
-// CHECK: vmptrld	3133065982
-// CHECK:  encoding: [0x0f,0xc7,0x35,0xfe,0xca,0xbe,0xba]
-        	vmptrld	0xbabecafe
+  // CHECK: vmptrld	3133065982
+  // CHECK:  encoding: [0x0f,0xc7,0x35,0xfe,0xca,0xbe,0xba]
+                  vmptrld	0xbabecafe
 
-// CHECK: vmptrld	305419896
-// CHECK:  encoding: [0x0f,0xc7,0x35,0x78,0x56,0x34,0x12]
-        	vmptrld	0x12345678
+  // CHECK: vmptrld	305419896
+  // CHECK:  encoding: [0x0f,0xc7,0x35,0x78,0x56,0x34,0x12]
+                  vmptrld	0x12345678
 
-// CHECK: vmptrst	3735928559(%ebx,%ecx,8)
-// CHECK:  encoding: [0x0f,0xc7,0xbc,0xcb,0xef,0xbe,0xad,0xde]
-        	vmptrst	0xdeadbeef(%ebx,%ecx,8)
+  // CHECK: vmptrst	3735928559(%ebx,%ecx,8)
+  // CHECK:  encoding: [0x0f,0xc7,0xbc,0xcb,0xef,0xbe,0xad,0xde]
+                  vmptrst	0xdeadbeef(%ebx,%ecx,8)
 
-// CHECK: vmptrst	32493
-// CHECK:  encoding: [0x0f,0xc7,0x3d,0xed,0x7e,0x00,0x00]
-        	vmptrst	0x7eed
+  // CHECK: vmptrst	32493
+  // CHECK:  encoding: [0x0f,0xc7,0x3d,0xed,0x7e,0x00,0x00]
+                  vmptrst	0x7eed
 
-// CHECK: vmptrst	3133065982
-// CHECK:  encoding: [0x0f,0xc7,0x3d,0xfe,0xca,0xbe,0xba]
-        	vmptrst	0xbabecafe
+  // CHECK: vmptrst	3133065982
+  // CHECK:  encoding: [0x0f,0xc7,0x3d,0xfe,0xca,0xbe,0xba]
+                  vmptrst	0xbabecafe
 
-// CHECK: vmptrst	305419896
-// CHECK:  encoding: [0x0f,0xc7,0x3d,0x78,0x56,0x34,0x12]
-        	vmptrst	0x12345678
+  // CHECK: vmptrst	305419896
+  // CHECK:  encoding: [0x0f,0xc7,0x3d,0x78,0x56,0x34,0x12]
+                  vmptrst	0x12345678
 
-// CHECK: phaddw	3735928559(%ebx,%ecx,8), %mm3
-// CHECK:  encoding: [0x0f,0x38,0x01,0x9c,0xcb,0xef,0xbe,0xad,0xde]
-        	phaddw	0xdeadbeef(%ebx,%ecx,8),%mm3
+  // CHECK: phaddw	3735928559(%ebx,%ecx,8), %mm3
+  // CHECK:  encoding: [0x0f,0x38,0x01,0x9c,0xcb,0xef,0xbe,0xad,0xde]
+                  phaddw	0xdeadbeef(%ebx,%ecx,8),%mm3
 
-// CHECK: phaddw	69, %mm3
-// CHECK:  encoding: [0x0f,0x38,0x01,0x1d,0x45,0x00,0x00,0x00]
-        	phaddw	0x45,%mm3
+  // CHECK: phaddw	69, %mm3
+  // CHECK:  encoding: [0x0f,0x38,0x01,0x1d,0x45,0x00,0x00,0x00]
+                  phaddw	0x45,%mm3
 
-// CHECK: phaddw	32493, %mm3
-// CHECK:  encoding: [0x0f,0x38,0x01,0x1d,0xed,0x7e,0x00,0x00]
-        	phaddw	0x7eed,%mm3
+  // CHECK: phaddw	32493, %mm3
+  // CHECK:  encoding: [0x0f,0x38,0x01,0x1d,0xed,0x7e,0x00,0x00]
+                  phaddw	0x7eed,%mm3
 
-// CHECK: phaddw	3133065982, %mm3
-// CHECK:  encoding: [0x0f,0x38,0x01,0x1d,0xfe,0xca,0xbe,0xba]
-        	phaddw	0xbabecafe,%mm3
+  // CHECK: phaddw	3133065982, %mm3
+  // CHECK:  encoding: [0x0f,0x38,0x01,0x1d,0xfe,0xca,0xbe,0xba]
+                  phaddw	0xbabecafe,%mm3
 
-// CHECK: phaddw	305419896, %mm3
-// CHECK:  encoding: [0x0f,0x38,0x01,0x1d,0x78,0x56,0x34,0x12]
-        	phaddw	0x12345678,%mm3
+  // CHECK: phaddw	305419896, %mm3
+  // CHECK:  encoding: [0x0f,0x38,0x01,0x1d,0x78,0x56,0x34,0x12]
+                  phaddw	0x12345678,%mm3
 
-// CHECK: phaddw	%mm3, %mm3
-// CHECK:  encoding: [0x0f,0x38,0x01,0xdb]
-        	phaddw	%mm3,%mm3
+  // CHECK: phaddw	%mm3, %mm3
+  // CHECK:  encoding: [0x0f,0x38,0x01,0xdb]
+                  phaddw	%mm3,%mm3
 
-// CHECK: phaddw	3735928559(%ebx,%ecx,8), %xmm5
-// CHECK:  encoding: [0x66,0x0f,0x38,0x01,0xac,0xcb,0xef,0xbe,0xad,0xde]
-        	phaddw	0xdeadbeef(%ebx,%ecx,8),%xmm5
+  // CHECK: phaddw	3735928559(%ebx,%ecx,8), %xmm5
+  // CHECK:  encoding: [0x66,0x0f,0x38,0x01,0xac,0xcb,0xef,0xbe,0xad,0xde]
+                  phaddw	0xdeadbeef(%ebx,%ecx,8),%xmm5
 
-// CHECK: phaddw	69, %xmm5
-// CHECK:  encoding: [0x66,0x0f,0x38,0x01,0x2d,0x45,0x00,0x00,0x00]
-        	phaddw	0x45,%xmm5
+  // CHECK: phaddw	69, %xmm5
+  // CHECK:  encoding: [0x66,0x0f,0x38,0x01,0x2d,0x45,0x00,0x00,0x00]
+                  phaddw	0x45,%xmm5
 
-// CHECK: phaddw	32493, %xmm5
-// CHECK:  encoding: [0x66,0x0f,0x38,0x01,0x2d,0xed,0x7e,0x00,0x00]
-        	phaddw	0x7eed,%xmm5
+  // CHECK: phaddw	32493, %xmm5
+  // CHECK:  encoding: [0x66,0x0f,0x38,0x01,0x2d,0xed,0x7e,0x00,0x00]
+                  phaddw	0x7eed,%xmm5
 
-// CHECK: phaddw	3133065982, %xmm5
-// CHECK:  encoding: [0x66,0x0f,0x38,0x01,0x2d,0xfe,0xca,0xbe,0xba]
-        	phaddw	0xbabecafe,%xmm5
+  // CHECK: phaddw	3133065982, %xmm5
+  // CHECK:  encoding: [0x66,0x0f,0x38,0x01,0x2d,0xfe,0xca,0xbe,0xba]
+                  phaddw	0xbabecafe,%xmm5
 
-// CHECK: phaddw	305419896, %xmm5
-// CHECK:  encoding: [0x66,0x0f,0x38,0x01,0x2d,0x78,0x56,0x34,0x12]
-        	phaddw	0x12345678,%xmm5
+  // CHECK: phaddw	305419896, %xmm5
+  // CHECK:  encoding: [0x66,0x0f,0x38,0x01,0x2d,0x78,0x56,0x34,0x12]
+                  phaddw	0x12345678,%xmm5
 
-// CHECK: phaddw	%xmm5, %xmm5
-// CHECK:  encoding: [0x66,0x0f,0x38,0x01,0xed]
-        	phaddw	%xmm5,%xmm5
+  // CHECK: phaddw	%xmm5, %xmm5
+  // CHECK:  encoding: [0x66,0x0f,0x38,0x01,0xed]
+                  phaddw	%xmm5,%xmm5
 
-// CHECK: phaddd	3735928559(%ebx,%ecx,8), %mm3
-// CHECK:  encoding: [0x0f,0x38,0x02,0x9c,0xcb,0xef,0xbe,0xad,0xde]
-        	phaddd	0xdeadbeef(%ebx,%ecx,8),%mm3
+  // CHECK: phaddd	3735928559(%ebx,%ecx,8), %mm3
+  // CHECK:  encoding: [0x0f,0x38,0x02,0x9c,0xcb,0xef,0xbe,0xad,0xde]
+                  phaddd	0xdeadbeef(%ebx,%ecx,8),%mm3
 
-// CHECK: phaddd	69, %mm3
-// CHECK:  encoding: [0x0f,0x38,0x02,0x1d,0x45,0x00,0x00,0x00]
-        	phaddd	0x45,%mm3
+  // CHECK: phaddd	69, %mm3
+  // CHECK:  encoding: [0x0f,0x38,0x02,0x1d,0x45,0x00,0x00,0x00]
+                  phaddd	0x45,%mm3
 
-// CHECK: phaddd	32493, %mm3
+  // CHECK: phaddd	32493, %mm3
 // CHECK:  encoding: [0x0f,0x38,0x02,0x1d,0xed,0x7e,0x00,0x00]
         	phaddd	0x7eed,%mm3
 
@@ -11732,162 +10088,6 @@
         addw $0xFFFF, %ax
 
 
-// CHECK: 	movb	$127, 3735928559(%ebx,%ecx,8)
-        	movb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movb	$127, 69
-        	movb	$0x7f,0x45
-
-// CHECK: 	movb	$127, 32493
-        	movb	$0x7f,0x7eed
-
-// CHECK: 	movb	$127, 3133065982
-        	movb	$0x7f,0xbabecafe
-
-// CHECK: 	movb	$127, 305419896
-        	movb	$0x7f,0x12345678
-
-// CHECK: 	movw	$31438, 3735928559(%ebx,%ecx,8)
-        	movw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movw	$31438, 69
-        	movw	$0x7ace,0x45
-
-// CHECK: 	movw	$31438, 32493
-        	movw	$0x7ace,0x7eed
-
-// CHECK: 	movw	$31438, 3133065982
-        	movw	$0x7ace,0xbabecafe
-
-// CHECK: 	movw	$31438, 305419896
-        	movw	$0x7ace,0x12345678
-
-// CHECK: 	movl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	movl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movl	$2063514302, 69
-        	movl	$0x7afebabe,0x45
-
-// CHECK: 	movl	$2063514302, 32493
-        	movl	$0x7afebabe,0x7eed
-
-// CHECK: 	movl	$2063514302, 3133065982
-        	movl	$0x7afebabe,0xbabecafe
-
-// CHECK: 	movl	$2063514302, 305419896
-        	movl	$0x7afebabe,0x12345678
-
-// CHECK: 	movl	$324478056, 3735928559(%ebx,%ecx,8)
-        	movl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movl	$324478056, 69
-        	movl	$0x13572468,0x45
-
-// CHECK: 	movl	$324478056, 32493
-        	movl	$0x13572468,0x7eed
-
-// CHECK: 	movl	$324478056, 3133065982
-        	movl	$0x13572468,0xbabecafe
-
-// CHECK: 	movl	$324478056, 305419896
-        	movl	$0x13572468,0x12345678
-
-// CHECK: 	movsbl	3735928559(%ebx,%ecx,8), %ecx
-        	movsbl	0xdeadbeef(%ebx,%ecx,8),%ecx
-
-// CHECK: 	movsbl	69, %ecx
-        	movsbl	0x45,%ecx
-
-// CHECK: 	movsbl	32493, %ecx
-        	movsbl	0x7eed,%ecx
-
-// CHECK: 	movsbl	3133065982, %ecx
-        	movsbl	0xbabecafe,%ecx
-
-// CHECK: 	movsbl	305419896, %ecx
-        	movsbl	0x12345678,%ecx
-
-// CHECK: 	movsbw	3735928559(%ebx,%ecx,8), %bx
-        	movsbw	0xdeadbeef(%ebx,%ecx,8),%bx
-
-// CHECK: 	movsbw	69, %bx
-        	movsbw	0x45,%bx
-
-// CHECK: 	movsbw	32493, %bx
-        	movsbw	0x7eed,%bx
-
-// CHECK: 	movsbw	3133065982, %bx
-        	movsbw	0xbabecafe,%bx
-
-// CHECK: 	movsbw	305419896, %bx
-        	movsbw	0x12345678,%bx
-
-// CHECK: 	movswl	3735928559(%ebx,%ecx,8), %ecx
-        	movswl	0xdeadbeef(%ebx,%ecx,8),%ecx
-
-// CHECK: 	movswl	69, %ecx
-        	movswl	0x45,%ecx
-
-// CHECK: 	movswl	32493, %ecx
-        	movswl	0x7eed,%ecx
-
-// CHECK: 	movswl	3133065982, %ecx
-        	movswl	0xbabecafe,%ecx
-
-// CHECK: 	movswl	305419896, %ecx
-        	movswl	0x12345678,%ecx
-
-// CHECK: 	movzbl	3735928559(%ebx,%ecx,8), %ecx
-        	movzbl	0xdeadbeef(%ebx,%ecx,8),%ecx
-
-// CHECK: 	movzbl	69, %ecx
-        	movzbl	0x45,%ecx
-
-// CHECK: 	movzbl	32493, %ecx
-        	movzbl	0x7eed,%ecx
-
-// CHECK: 	movzbl	3133065982, %ecx
-        	movzbl	0xbabecafe,%ecx
-
-// CHECK: 	movzbl	305419896, %ecx
-        	movzbl	0x12345678,%ecx
-
-// CHECK: 	movzbw	3735928559(%ebx,%ecx,8), %bx
-        	movzbw	0xdeadbeef(%ebx,%ecx,8),%bx
-
-// CHECK: 	movzbw	69, %bx
-        	movzbw	0x45,%bx
-
-// CHECK: 	movzbw	32493, %bx
-        	movzbw	0x7eed,%bx
-
-// CHECK: 	movzbw	3133065982, %bx
-        	movzbw	0xbabecafe,%bx
-
-// CHECK: 	movzbw	305419896, %bx
-        	movzbw	0x12345678,%bx
-
-// CHECK: 	movzwl	3735928559(%ebx,%ecx,8), %ecx
-        	movzwl	0xdeadbeef(%ebx,%ecx,8),%ecx
-
-// CHECK: 	movzwl	69, %ecx
-        	movzwl	0x45,%ecx
-
-// CHECK: 	movzwl	32493, %ecx
-        	movzwl	0x7eed,%ecx
-
-// CHECK: 	movzwl	3133065982, %ecx
-        	movzwl	0xbabecafe,%ecx
-
-// CHECK: 	movzwl	305419896, %ecx
-        	movzwl	0x12345678,%ecx
-
-// CHECK: 	pushw	32493
-        	pushw	0x7eed
-
-// CHECK: 	popw	32493
-        	popw	0x7eed
-
 // CHECK: 	pushf
         	pushfl
 
@@ -11900,888 +10100,6 @@
 // CHECK: 	popfl
         	popfl
 
-// CHECK: 	clc
-        	clc
-
-// CHECK: 	cld
-        	cld
-
-// CHECK: 	cli
-        	cli
-
-// CHECK: 	clts
-        	clts
-
-// CHECK: 	cmc
-        	cmc
-
-// CHECK: 	lahf
-        	lahf
-
-// CHECK: 	sahf
-        	sahf
-
-// CHECK: 	stc
-        	stc
-
-// CHECK: 	std
-        	std
-
-// CHECK: 	sti
-        	sti
-
-// CHECK: 	addb	$254, 3735928559(%ebx,%ecx,8)
-        	addb	$0xfe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	addb	$254, 69
-        	addb	$0xfe,0x45
-
-// CHECK: 	addb	$254, 32493
-        	addb	$0xfe,0x7eed
-
-// CHECK: 	addb	$254, 3133065982
-        	addb	$0xfe,0xbabecafe
-
-// CHECK: 	addb	$254, 305419896
-        	addb	$0xfe,0x12345678
-
-// CHECK: 	addb	$127, 3735928559(%ebx,%ecx,8)
-        	addb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	addb	$127, 69
-        	addb	$0x7f,0x45
-
-// CHECK: 	addb	$127, 32493
-        	addb	$0x7f,0x7eed
-
-// CHECK: 	addb	$127, 3133065982
-        	addb	$0x7f,0xbabecafe
-
-// CHECK: 	addb	$127, 305419896
-        	addb	$0x7f,0x12345678
-
-// CHECK: 	addw	$31438, 3735928559(%ebx,%ecx,8)
-        	addw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	addw	$31438, 69
-        	addw	$0x7ace,0x45
-
-// CHECK: 	addw	$31438, 32493
-        	addw	$0x7ace,0x7eed
-
-// CHECK: 	addw	$31438, 3133065982
-        	addw	$0x7ace,0xbabecafe
-
-// CHECK: 	addw	$31438, 305419896
-        	addw	$0x7ace,0x12345678
-
-// CHECK: 	addl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	addl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	addl	$2063514302, 69
-        	addl	$0x7afebabe,0x45
-
-// CHECK: 	addl	$2063514302, 32493
-        	addl	$0x7afebabe,0x7eed
-
-// CHECK: 	addl	$2063514302, 3133065982
-        	addl	$0x7afebabe,0xbabecafe
-
-// CHECK: 	addl	$2063514302, 305419896
-        	addl	$0x7afebabe,0x12345678
-
-// CHECK: 	addl	$324478056, 3735928559(%ebx,%ecx,8)
-        	addl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	addl	$324478056, 69
-        	addl	$0x13572468,0x45
-
-// CHECK: 	addl	$324478056, 32493
-        	addl	$0x13572468,0x7eed
-
-// CHECK: 	addl	$324478056, 3133065982
-        	addl	$0x13572468,0xbabecafe
-
-// CHECK: 	addl	$324478056, 305419896
-        	addl	$0x13572468,0x12345678
-
-// CHECK: 	incl	3735928559(%ebx,%ecx,8)
-        	incl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	incw	32493
-        	incw	0x7eed
-
-// CHECK: 	incl	3133065982
-        	incl	0xbabecafe
-
-// CHECK: 	incl	305419896
-        	incl	0x12345678
-
-// CHECK: 	subb	$254, 3735928559(%ebx,%ecx,8)
-        	subb	$0xfe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	subb	$254, 69
-        	subb	$0xfe,0x45
-
-// CHECK: 	subb	$254, 32493
-        	subb	$0xfe,0x7eed
-
-// CHECK: 	subb	$254, 3133065982
-        	subb	$0xfe,0xbabecafe
-
-// CHECK: 	subb	$254, 305419896
-        	subb	$0xfe,0x12345678
-
-// CHECK: 	subb	$127, 3735928559(%ebx,%ecx,8)
-        	subb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	subb	$127, 69
-        	subb	$0x7f,0x45
-
-// CHECK: 	subb	$127, 32493
-        	subb	$0x7f,0x7eed
-
-// CHECK: 	subb	$127, 3133065982
-        	subb	$0x7f,0xbabecafe
-
-// CHECK: 	subb	$127, 305419896
-        	subb	$0x7f,0x12345678
-
-// CHECK: 	subw	$31438, 3735928559(%ebx,%ecx,8)
-        	subw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	subw	$31438, 69
-        	subw	$0x7ace,0x45
-
-// CHECK: 	subw	$31438, 32493
-        	subw	$0x7ace,0x7eed
-
-// CHECK: 	subw	$31438, 3133065982
-        	subw	$0x7ace,0xbabecafe
-
-// CHECK: 	subw	$31438, 305419896
-        	subw	$0x7ace,0x12345678
-
-// CHECK: 	subl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	subl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	subl	$2063514302, 69
-        	subl	$0x7afebabe,0x45
-
-// CHECK: 	subl	$2063514302, 32493
-        	subl	$0x7afebabe,0x7eed
-
-// CHECK: 	subl	$2063514302, 3133065982
-        	subl	$0x7afebabe,0xbabecafe
-
-// CHECK: 	subl	$2063514302, 305419896
-        	subl	$0x7afebabe,0x12345678
-
-// CHECK: 	subl	$324478056, 3735928559(%ebx,%ecx,8)
-        	subl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	subl	$324478056, 69
-        	subl	$0x13572468,0x45
-
-// CHECK: 	subl	$324478056, 32493
-        	subl	$0x13572468,0x7eed
-
-// CHECK: 	subl	$324478056, 3133065982
-        	subl	$0x13572468,0xbabecafe
-
-// CHECK: 	subl	$324478056, 305419896
-        	subl	$0x13572468,0x12345678
-
-// CHECK: 	decl	3735928559(%ebx,%ecx,8)
-        	decl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	decw	32493
-        	decw	0x7eed
-
-// CHECK: 	decl	3133065982
-        	decl	0xbabecafe
-
-// CHECK: 	decl	305419896
-        	decl	0x12345678
-
-// CHECK: 	sbbb	$254, 3735928559(%ebx,%ecx,8)
-        	sbbb	$0xfe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sbbb	$254, 69
-        	sbbb	$0xfe,0x45
-
-// CHECK: 	sbbb	$254, 32493
-        	sbbb	$0xfe,0x7eed
-
-// CHECK: 	sbbb	$254, 3133065982
-        	sbbb	$0xfe,0xbabecafe
-
-// CHECK: 	sbbb	$254, 305419896
-        	sbbb	$0xfe,0x12345678
-
-// CHECK: 	sbbb	$127, 3735928559(%ebx,%ecx,8)
-        	sbbb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sbbb	$127, 69
-        	sbbb	$0x7f,0x45
-
-// CHECK: 	sbbb	$127, 32493
-        	sbbb	$0x7f,0x7eed
-
-// CHECK: 	sbbb	$127, 3133065982
-        	sbbb	$0x7f,0xbabecafe
-
-// CHECK: 	sbbb	$127, 305419896
-        	sbbb	$0x7f,0x12345678
-
-// CHECK: 	sbbw	$31438, 3735928559(%ebx,%ecx,8)
-        	sbbw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sbbw	$31438, 69
-        	sbbw	$0x7ace,0x45
-
-// CHECK: 	sbbw	$31438, 32493
-        	sbbw	$0x7ace,0x7eed
-
-// CHECK: 	sbbw	$31438, 3133065982
-        	sbbw	$0x7ace,0xbabecafe
-
-// CHECK: 	sbbw	$31438, 305419896
-        	sbbw	$0x7ace,0x12345678
-
-// CHECK: 	sbbl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	sbbl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sbbl	$2063514302, 69
-        	sbbl	$0x7afebabe,0x45
-
-// CHECK: 	sbbl	$2063514302, 32493
-        	sbbl	$0x7afebabe,0x7eed
-
-// CHECK: 	sbbl	$2063514302, 3133065982
-        	sbbl	$0x7afebabe,0xbabecafe
-
-// CHECK: 	sbbl	$2063514302, 305419896
-        	sbbl	$0x7afebabe,0x12345678
-
-// CHECK: 	sbbl	$324478056, 3735928559(%ebx,%ecx,8)
-        	sbbl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sbbl	$324478056, 69
-        	sbbl	$0x13572468,0x45
-
-// CHECK: 	sbbl	$324478056, 32493
-        	sbbl	$0x13572468,0x7eed
-
-// CHECK: 	sbbl	$324478056, 3133065982
-        	sbbl	$0x13572468,0xbabecafe
-
-// CHECK: 	sbbl	$324478056, 305419896
-        	sbbl	$0x13572468,0x12345678
-
-// CHECK: 	cmpb	$254, 3735928559(%ebx,%ecx,8)
-        	cmpb	$0xfe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	cmpb	$254, 69
-        	cmpb	$0xfe,0x45
-
-// CHECK: 	cmpb	$254, 32493
-        	cmpb	$0xfe,0x7eed
-
-// CHECK: 	cmpb	$254, 3133065982
-        	cmpb	$0xfe,0xbabecafe
-
-// CHECK: 	cmpb	$254, 305419896
-        	cmpb	$0xfe,0x12345678
-
-// CHECK: 	cmpb	$127, 3735928559(%ebx,%ecx,8)
-        	cmpb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	cmpb	$127, 69
-        	cmpb	$0x7f,0x45
-
-// CHECK: 	cmpb	$127, 32493
-        	cmpb	$0x7f,0x7eed
-
-// CHECK: 	cmpb	$127, 3133065982
-        	cmpb	$0x7f,0xbabecafe
-
-// CHECK: 	cmpb	$127, 305419896
-        	cmpb	$0x7f,0x12345678
-
-// CHECK: 	cmpw	$31438, 3735928559(%ebx,%ecx,8)
-        	cmpw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	cmpw	$31438, 69
-        	cmpw	$0x7ace,0x45
-
-// CHECK: 	cmpw	$31438, 32493
-        	cmpw	$0x7ace,0x7eed
-
-// CHECK: 	cmpw	$31438, 3133065982
-        	cmpw	$0x7ace,0xbabecafe
-
-// CHECK: 	cmpw	$31438, 305419896
-        	cmpw	$0x7ace,0x12345678
-
-// CHECK: 	cmpl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	cmpl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	cmpl	$2063514302, 69
-        	cmpl	$0x7afebabe,0x45
-
-// CHECK: 	cmpl	$2063514302, 32493
-        	cmpl	$0x7afebabe,0x7eed
-
-// CHECK: 	cmpl	$2063514302, 3133065982
-        	cmpl	$0x7afebabe,0xbabecafe
-
-// CHECK: 	cmpl	$2063514302, 305419896
-        	cmpl	$0x7afebabe,0x12345678
-
-// CHECK: 	cmpl	$324478056, 3735928559(%ebx,%ecx,8)
-        	cmpl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	cmpl	$324478056, 69
-        	cmpl	$0x13572468,0x45
-
-// CHECK: 	cmpl	$324478056, 32493
-        	cmpl	$0x13572468,0x7eed
-
-// CHECK: 	cmpl	$324478056, 3133065982
-        	cmpl	$0x13572468,0xbabecafe
-
-// CHECK: 	cmpl	$324478056, 305419896
-        	cmpl	$0x13572468,0x12345678
-
-// CHECK: 	testb	$127, 3735928559(%ebx,%ecx,8)
-        	testb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	testb	$127, 69
-        	testb	$0x7f,0x45
-
-// CHECK: 	testb	$127, 32493
-        	testb	$0x7f,0x7eed
-
-// CHECK: 	testb	$127, 3133065982
-        	testb	$0x7f,0xbabecafe
-
-// CHECK: 	testb	$127, 305419896
-        	testb	$0x7f,0x12345678
-
-// CHECK: 	testw	$31438, 3735928559(%ebx,%ecx,8)
-        	testw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	testw	$31438, 69
-        	testw	$0x7ace,0x45
-
-// CHECK: 	testw	$31438, 32493
-        	testw	$0x7ace,0x7eed
-
-// CHECK: 	testw	$31438, 3133065982
-        	testw	$0x7ace,0xbabecafe
-
-// CHECK: 	testw	$31438, 305419896
-        	testw	$0x7ace,0x12345678
-
-// CHECK: 	testl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	testl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	testl	$2063514302, 69
-        	testl	$0x7afebabe,0x45
-
-// CHECK: 	testl	$2063514302, 32493
-        	testl	$0x7afebabe,0x7eed
-
-// CHECK: 	testl	$2063514302, 3133065982
-        	testl	$0x7afebabe,0xbabecafe
-
-// CHECK: 	testl	$2063514302, 305419896
-        	testl	$0x7afebabe,0x12345678
-
-// CHECK: 	testl	$324478056, 3735928559(%ebx,%ecx,8)
-        	testl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	testl	$324478056, 69
-        	testl	$0x13572468,0x45
-
-// CHECK: 	testl	$324478056, 32493
-        	testl	$0x13572468,0x7eed
-
-// CHECK: 	testl	$324478056, 3133065982
-        	testl	$0x13572468,0xbabecafe
-
-// CHECK: 	testl	$324478056, 305419896
-        	testl	$0x13572468,0x12345678
-
-// CHECK: 	andb	$254, 3735928559(%ebx,%ecx,8)
-        	andb	$0xfe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	andb	$254, 69
-        	andb	$0xfe,0x45
-
-// CHECK: 	andb	$254, 32493
-        	andb	$0xfe,0x7eed
-
-// CHECK: 	andb	$254, 3133065982
-        	andb	$0xfe,0xbabecafe
-
-// CHECK: 	andb	$254, 305419896
-        	andb	$0xfe,0x12345678
-
-// CHECK: 	andb	$127, 3735928559(%ebx,%ecx,8)
-        	andb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	andb	$127, 69
-        	andb	$0x7f,0x45
-
-// CHECK: 	andb	$127, 32493
-        	andb	$0x7f,0x7eed
-
-// CHECK: 	andb	$127, 3133065982
-        	andb	$0x7f,0xbabecafe
-
-// CHECK: 	andb	$127, 305419896
-        	andb	$0x7f,0x12345678
-
-// CHECK: 	andw	$31438, 3735928559(%ebx,%ecx,8)
-        	andw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	andw	$31438, 69
-        	andw	$0x7ace,0x45
-
-// CHECK: 	andw	$31438, 32493
-        	andw	$0x7ace,0x7eed
-
-// CHECK: 	andw	$31438, 3133065982
-        	andw	$0x7ace,0xbabecafe
-
-// CHECK: 	andw	$31438, 305419896
-        	andw	$0x7ace,0x12345678
-
-// CHECK: 	andl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	andl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	andl	$2063514302, 69
-        	andl	$0x7afebabe,0x45
-
-// CHECK: 	andl	$2063514302, 32493
-        	andl	$0x7afebabe,0x7eed
-
-// CHECK: 	andl	$2063514302, 3133065982
-        	andl	$0x7afebabe,0xbabecafe
-
-// CHECK: 	andl	$2063514302, 305419896
-        	andl	$0x7afebabe,0x12345678
-
-// CHECK: 	andl	$324478056, 3735928559(%ebx,%ecx,8)
-        	andl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	andl	$324478056, 69
-        	andl	$0x13572468,0x45
-
-// CHECK: 	andl	$324478056, 32493
-        	andl	$0x13572468,0x7eed
-
-// CHECK: 	andl	$324478056, 3133065982
-        	andl	$0x13572468,0xbabecafe
-
-// CHECK: 	andl	$324478056, 305419896
-        	andl	$0x13572468,0x12345678
-
-// CHECK: 	orb	$254, 3735928559(%ebx,%ecx,8)
-        	orb	$0xfe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	orb	$254, 69
-        	orb	$0xfe,0x45
-
-// CHECK: 	orb	$254, 32493
-        	orb	$0xfe,0x7eed
-
-// CHECK: 	orb	$254, 3133065982
-        	orb	$0xfe,0xbabecafe
-
-// CHECK: 	orb	$254, 305419896
-        	orb	$0xfe,0x12345678
-
-// CHECK: 	orb	$127, 3735928559(%ebx,%ecx,8)
-        	orb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	orb	$127, 69
-        	orb	$0x7f,0x45
-
-// CHECK: 	orb	$127, 32493
-        	orb	$0x7f,0x7eed
-
-// CHECK: 	orb	$127, 3133065982
-        	orb	$0x7f,0xbabecafe
-
-// CHECK: 	orb	$127, 305419896
-        	orb	$0x7f,0x12345678
-
-// CHECK: 	orw	$31438, 3735928559(%ebx,%ecx,8)
-        	orw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	orw	$31438, 69
-        	orw	$0x7ace,0x45
-
-// CHECK: 	orw	$31438, 32493
-        	orw	$0x7ace,0x7eed
-
-// CHECK: 	orw	$31438, 3133065982
-        	orw	$0x7ace,0xbabecafe
-
-// CHECK: 	orw	$31438, 305419896
-        	orw	$0x7ace,0x12345678
-
-// CHECK: 	orl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	orl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	orl	$2063514302, 69
-        	orl	$0x7afebabe,0x45
-
-// CHECK: 	orl	$2063514302, 32493
-        	orl	$0x7afebabe,0x7eed
-
-// CHECK: 	orl	$2063514302, 3133065982
-        	orl	$0x7afebabe,0xbabecafe
-
-// CHECK: 	orl	$2063514302, 305419896
-        	orl	$0x7afebabe,0x12345678
-
-// CHECK: 	orl	$324478056, 3735928559(%ebx,%ecx,8)
-        	orl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	orl	$324478056, 69
-        	orl	$0x13572468,0x45
-
-// CHECK: 	orl	$324478056, 32493
-        	orl	$0x13572468,0x7eed
-
-// CHECK: 	orl	$324478056, 3133065982
-        	orl	$0x13572468,0xbabecafe
-
-// CHECK: 	orl	$324478056, 305419896
-        	orl	$0x13572468,0x12345678
-
-// CHECK: 	xorb	$254, 3735928559(%ebx,%ecx,8)
-        	xorb	$0xfe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	xorb	$254, 69
-        	xorb	$0xfe,0x45
-
-// CHECK: 	xorb	$254, 32493
-        	xorb	$0xfe,0x7eed
-
-// CHECK: 	xorb	$254, 3133065982
-        	xorb	$0xfe,0xbabecafe
-
-// CHECK: 	xorb	$254, 305419896
-        	xorb	$0xfe,0x12345678
-
-// CHECK: 	xorb	$127, 3735928559(%ebx,%ecx,8)
-        	xorb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	xorb	$127, 69
-        	xorb	$0x7f,0x45
-
-// CHECK: 	xorb	$127, 32493
-        	xorb	$0x7f,0x7eed
-
-// CHECK: 	xorb	$127, 3133065982
-        	xorb	$0x7f,0xbabecafe
-
-// CHECK: 	xorb	$127, 305419896
-        	xorb	$0x7f,0x12345678
-
-// CHECK: 	xorw	$31438, 3735928559(%ebx,%ecx,8)
-        	xorw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	xorw	$31438, 69
-        	xorw	$0x7ace,0x45
-
-// CHECK: 	xorw	$31438, 32493
-        	xorw	$0x7ace,0x7eed
-
-// CHECK: 	xorw	$31438, 3133065982
-        	xorw	$0x7ace,0xbabecafe
-
-// CHECK: 	xorw	$31438, 305419896
-        	xorw	$0x7ace,0x12345678
-
-// CHECK: 	xorl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	xorl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	xorl	$2063514302, 69
-        	xorl	$0x7afebabe,0x45
-
-// CHECK: 	xorl	$2063514302, 32493
-        	xorl	$0x7afebabe,0x7eed
-
-// CHECK: 	xorl	$2063514302, 3133065982
-        	xorl	$0x7afebabe,0xbabecafe
-
-// CHECK: 	xorl	$2063514302, 305419896
-        	xorl	$0x7afebabe,0x12345678
-
-// CHECK: 	xorl	$324478056, 3735928559(%ebx,%ecx,8)
-        	xorl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	xorl	$324478056, 69
-        	xorl	$0x13572468,0x45
-
-// CHECK: 	xorl	$324478056, 32493
-        	xorl	$0x13572468,0x7eed
-
-// CHECK: 	xorl	$324478056, 3133065982
-        	xorl	$0x13572468,0xbabecafe
-
-// CHECK: 	xorl	$324478056, 305419896
-        	xorl	$0x13572468,0x12345678
-
-// CHECK: 	adcb	$254, 3735928559(%ebx,%ecx,8)
-        	adcb	$0xfe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	adcb	$254, 69
-        	adcb	$0xfe,0x45
-
-// CHECK: 	adcb	$254, 32493
-        	adcb	$0xfe,0x7eed
-
-// CHECK: 	adcb	$254, 3133065982
-        	adcb	$0xfe,0xbabecafe
-
-// CHECK: 	adcb	$254, 305419896
-        	adcb	$0xfe,0x12345678
-
-// CHECK: 	adcb	$127, 3735928559(%ebx,%ecx,8)
-        	adcb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	adcb	$127, 69
-        	adcb	$0x7f,0x45
-
-// CHECK: 	adcb	$127, 32493
-        	adcb	$0x7f,0x7eed
-
-// CHECK: 	adcb	$127, 3133065982
-        	adcb	$0x7f,0xbabecafe
-
-// CHECK: 	adcb	$127, 305419896
-        	adcb	$0x7f,0x12345678
-
-// CHECK: 	adcw	$31438, 3735928559(%ebx,%ecx,8)
-        	adcw	$0x7ace,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	adcw	$31438, 69
-        	adcw	$0x7ace,0x45
-
-// CHECK: 	adcw	$31438, 32493
-        	adcw	$0x7ace,0x7eed
-
-// CHECK: 	adcw	$31438, 3133065982
-        	adcw	$0x7ace,0xbabecafe
-
-// CHECK: 	adcw	$31438, 305419896
-        	adcw	$0x7ace,0x12345678
-
-// CHECK: 	adcl	$2063514302, 3735928559(%ebx,%ecx,8)
-        	adcl	$0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	adcl	$2063514302, 69
-        	adcl	$0x7afebabe,0x45
-
-// CHECK: 	adcl	$2063514302, 32493
-        	adcl	$0x7afebabe,0x7eed
-
-// CHECK: 	adcl	$2063514302, 3133065982
-        	adcl	$0x7afebabe,0xbabecafe
-
-// CHECK: 	adcl	$2063514302, 305419896
-        	adcl	$0x7afebabe,0x12345678
-
-// CHECK: 	adcl	$324478056, 3735928559(%ebx,%ecx,8)
-        	adcl	$0x13572468,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	adcl	$324478056, 69
-        	adcl	$0x13572468,0x45
-
-// CHECK: 	adcl	$324478056, 32493
-        	adcl	$0x13572468,0x7eed
-
-// CHECK: 	adcl	$324478056, 3133065982
-        	adcl	$0x13572468,0xbabecafe
-
-// CHECK: 	adcl	$324478056, 305419896
-        	adcl	$0x13572468,0x12345678
-
-// CHECK: 	negl	3735928559(%ebx,%ecx,8)
-        	negl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	negw	32493
-        	negw	0x7eed
-
-// CHECK: 	negl	3133065982
-        	negl	0xbabecafe
-
-// CHECK: 	negl	305419896
-        	negl	0x12345678
-
-// CHECK: 	notl	3735928559(%ebx,%ecx,8)
-        	notl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	notw	32493
-        	notw	0x7eed
-
-// CHECK: 	notl	3133065982
-        	notl	0xbabecafe
-
-// CHECK: 	notl	305419896
-        	notl	0x12345678
-
-// CHECK: 	cbtw
-        	cbtw
-
-// CHECK: 	cwtl
-        	cwtl
-
-// CHECK: 	cwtd
-        	cwtd
-
-// CHECK: 	cltd
-        	cltd
-
-// CHECK: 	mull	3735928559(%ebx,%ecx,8)
-        	mull	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	mulw	32493
-        	mulw	0x7eed
-
-// CHECK: 	mull	3133065982
-        	mull	0xbabecafe
-
-// CHECK: 	mull	305419896
-        	mull	0x12345678
-
-// CHECK: 	imull	3735928559(%ebx,%ecx,8)
-        	imull	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	imulw	32493
-        	imulw	0x7eed
-
-// CHECK: 	imull	3133065982
-        	imull	0xbabecafe
-
-// CHECK: 	imull	305419896
-        	imull	0x12345678
-
-// CHECK: 	divl	3735928559(%ebx,%ecx,8)
-        	divl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	divw	32493
-        	divw	0x7eed
-
-// CHECK: 	divl	3133065982
-        	divl	0xbabecafe
-
-// CHECK: 	divl	305419896
-        	divl	0x12345678
-
-// CHECK: 	idivl	3735928559(%ebx,%ecx,8)
-        	idivl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	idivw	32493
-        	idivw	0x7eed
-
-// CHECK: 	idivl	3133065982
-        	idivl	0xbabecafe
-
-// CHECK: 	idivl	305419896
-        	idivl	0x12345678
-
-// CHECK: 	roll	$0, 3735928559(%ebx,%ecx,8)
-        	roll	$0,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	roll	$0, 69
-        	roll	$0,0x45
-
-// CHECK: 	roll	$0, 32493
-        	roll	$0,0x7eed
-
-// CHECK: 	roll	$0, 3133065982
-        	roll	$0,0xbabecafe
-
-// CHECK: 	roll	$0, 305419896
-        	roll	$0,0x12345678
-
-// CHECK: 	rolb	$127, 3735928559(%ebx,%ecx,8)
-        	rolb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	rolb	$127, 69
-        	rolb	$0x7f,0x45
-
-// CHECK: 	rolb	$127, 32493
-        	rolb	$0x7f,0x7eed
-
-// CHECK: 	rolb	$127, 3133065982
-        	rolb	$0x7f,0xbabecafe
-
-// CHECK: 	rolb	$127, 305419896
-        	rolb	$0x7f,0x12345678
-
-// CHECK: 	roll	3735928559(%ebx,%ecx,8)
-        	roll	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	rolw	32493
-        	rolw	0x7eed
-
-// CHECK: 	roll	3133065982
-        	roll	0xbabecafe
-
-// CHECK: 	roll	305419896
-        	roll	0x12345678
-
-// CHECK: 	rorl	$0, 3735928559(%ebx,%ecx,8)
-        	rorl	$0,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	rorl	$0, 69
-        	rorl	$0,0x45
-
-// CHECK: 	rorl	$0, 32493
-        	rorl	$0,0x7eed
-
-// CHECK: 	rorl	$0, 3133065982
-        	rorl	$0,0xbabecafe
-
-// CHECK: 	rorl	$0, 305419896
-        	rorl	$0,0x12345678
-
-// CHECK: 	rorb	$127, 3735928559(%ebx,%ecx,8)
-        	rorb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	rorb	$127, 69
-        	rorb	$0x7f,0x45
-
-// CHECK: 	rorb	$127, 32493
-        	rorb	$0x7f,0x7eed
-
-// CHECK: 	rorb	$127, 3133065982
-        	rorb	$0x7f,0xbabecafe
-
-// CHECK: 	rorb	$127, 305419896
-        	rorb	$0x7f,0x12345678
-
-// CHECK: 	rorl	3735928559(%ebx,%ecx,8)
-        	rorl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	rorw	32493
-        	rorw	0x7eed
-
-// CHECK: 	rorl	3133065982
-        	rorl	0xbabecafe
-
-// CHECK: 	rorl	305419896
-        	rorl	0x12345678
-
 // CHECK: 	rcll	$0, 3735928559(%ebx,%ecx,8)
         	rcll	$0,0xdeadbeef(%ebx,%ecx,8)
 
@@ -12842,183 +10160,12 @@
 // CHECK: 	rcrb	$127, 305419896
         	rcrb	$0x7f,0x12345678
 
-// CHECK: 	shll	$0, 3735928559(%ebx,%ecx,8)
-        	sall	$0,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	shll	$0, 69
-        	sall	$0,0x45
-
-// CHECK: 	shll	$0, 32493
-        	sall	$0,0x7eed
-
-// CHECK: 	shll	$0, 3133065982
-        	sall	$0,0xbabecafe
-
-// CHECK: 	shll	$0, 305419896
-        	sall	$0,0x12345678
-
-// CHECK: 	shlb	$127, 3735928559(%ebx,%ecx,8)
-        	salb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	shlb	$127, 69
-        	salb	$0x7f,0x45
-
-// CHECK: 	shlb	$127, 32493
-        	salb	$0x7f,0x7eed
-
-// CHECK: 	shlb	$127, 3133065982
-        	salb	$0x7f,0xbabecafe
-
-// CHECK: 	shlb	$127, 305419896
-        	salb	$0x7f,0x12345678
-
-// CHECK: 	shll	3735928559(%ebx,%ecx,8)
-        	sall	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	shlw	32493
-        	salw	0x7eed
-
-// CHECK: 	shll	3133065982
-        	sall	0xbabecafe
-
-// CHECK: 	shll	305419896
-        	sall	0x12345678
-
-// CHECK: 	shll	$0, 3735928559(%ebx,%ecx,8)
-        	shll	$0,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	shll	$0, 69
-        	shll	$0,0x45
-
-// CHECK: 	shll	$0, 32493
-        	shll	$0,0x7eed
-
-// CHECK: 	shll	$0, 3133065982
-        	shll	$0,0xbabecafe
-
-// CHECK: 	shll	$0, 305419896
-        	shll	$0,0x12345678
-
-// CHECK: 	shlb	$127, 3735928559(%ebx,%ecx,8)
-        	shlb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	shlb	$127, 69
-        	shlb	$0x7f,0x45
-
-// CHECK: 	shlb	$127, 32493
-        	shlb	$0x7f,0x7eed
-
-// CHECK: 	shlb	$127, 3133065982
-        	shlb	$0x7f,0xbabecafe
-
-// CHECK: 	shlb	$127, 305419896
-        	shlb	$0x7f,0x12345678
-
-// CHECK: 	shll	3735928559(%ebx,%ecx,8)
-        	shll	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	shlw	32493
-        	shlw	0x7eed
-
-// CHECK: 	shll	3133065982
-        	shll	0xbabecafe
-
-// CHECK: 	shll	305419896
-        	shll	0x12345678
-
-// CHECK: 	shrl	$0, 3735928559(%ebx,%ecx,8)
-        	shrl	$0,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	shrl	$0, 69
-        	shrl	$0,0x45
-
-// CHECK: 	shrl	$0, 32493
-        	shrl	$0,0x7eed
-
-// CHECK: 	shrl	$0, 3133065982
-        	shrl	$0,0xbabecafe
-
-// CHECK: 	shrl	$0, 305419896
-        	shrl	$0,0x12345678
-
-// CHECK: 	shrb	$127, 3735928559(%ebx,%ecx,8)
-        	shrb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	shrb	$127, 69
-        	shrb	$0x7f,0x45
-
-// CHECK: 	shrb	$127, 32493
-        	shrb	$0x7f,0x7eed
-
-// CHECK: 	shrb	$127, 3133065982
-        	shrb	$0x7f,0xbabecafe
-
-// CHECK: 	shrb	$127, 305419896
-        	shrb	$0x7f,0x12345678
-
-// CHECK: 	shrl	3735928559(%ebx,%ecx,8)
-        	shrl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	shrw	32493
-        	shrw	0x7eed
-
-// CHECK: 	shrl	3133065982
-        	shrl	0xbabecafe
-
-// CHECK: 	shrl	305419896
-        	shrl	0x12345678
-
-// CHECK: 	sarl	$0, 3735928559(%ebx,%ecx,8)
-        	sarl	$0,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sarl	$0, 69
-        	sarl	$0,0x45
-
-// CHECK: 	sarl	$0, 32493
-        	sarl	$0,0x7eed
-
-// CHECK: 	sarl	$0, 3133065982
-        	sarl	$0,0xbabecafe
-
-// CHECK: 	sarl	$0, 305419896
-        	sarl	$0,0x12345678
-
-// CHECK: 	sarb	$127, 3735928559(%ebx,%ecx,8)
-        	sarb	$0x7f,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sarb	$127, 69
-        	sarb	$0x7f,0x45
-
-// CHECK: 	sarb	$127, 32493
-        	sarb	$0x7f,0x7eed
-
-// CHECK: 	sarb	$127, 3133065982
-        	sarb	$0x7f,0xbabecafe
-
-// CHECK: 	sarb	$127, 305419896
-        	sarb	$0x7f,0x12345678
-
-// CHECK: 	sarl	3735928559(%ebx,%ecx,8)
-        	sarl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sarw	32493
-        	sarw	0x7eed
-
-// CHECK: 	sarl	3133065982
-        	sarl	0xbabecafe
-
-// CHECK: 	sarl	305419896
-        	sarl	0x12345678
-
 // CHECK: 	calll	3133065982
         	calll	0xbabecafe
 
 // CHECK: 	calll	*3735928559(%ebx,%ecx,8)
         	calll	*0xdeadbeef(%ebx,%ecx,8)
 
-// CHECK: 	calll	3133065982
-        	calll	0xbabecafe
-
 // CHECK: 	calll	305419896
         	calll	0x12345678
 
@@ -13097,18 +10244,9 @@
 // CHECK: 	ljmpl	*305419896
         	ljmpl	*0x12345678
 
-// CHECK: 	ret
-        	ret
-
-// CHECK: 	lret
-        	lret
-
 // CHECK: 	enter	$31438, $127
         	enter	$0x7ace,$0x7f
 
-// CHECK: 	leave
-        	leave
-
 // CHECK: 	jo	32493
         	jo	0x7eed
 
@@ -13301,924 +10439,9 @@
 // CHECK: 	jg	-77129852792157442
         	jg	0xfeedfacebabecafe
 
-// CHECK: 	seto	%bl
-        	seto	%bl
-
-// CHECK: 	seto	3735928559(%ebx,%ecx,8)
-        	seto	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	seto	32493
-        	seto	0x7eed
-
-// CHECK: 	seto	3133065982
-        	seto	0xbabecafe
-
-// CHECK: 	seto	305419896
-        	seto	0x12345678
-
-// CHECK: 	setno	%bl
-        	setno	%bl
-
-// CHECK: 	setno	3735928559(%ebx,%ecx,8)
-        	setno	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setno	32493
-        	setno	0x7eed
-
-// CHECK: 	setno	3133065982
-        	setno	0xbabecafe
-
-// CHECK: 	setno	305419896
-        	setno	0x12345678
-
-// CHECK: 	setb	%bl
-        	setb	%bl
-
-// CHECK: 	setb	3735928559(%ebx,%ecx,8)
-        	setb	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setb	32493
-        	setb	0x7eed
-
-// CHECK: 	setb	3133065982
-        	setb	0xbabecafe
-
-// CHECK: 	setb	305419896
-        	setb	0x12345678
-
-// CHECK: 	setae	%bl
-        	setae	%bl
-
-// CHECK: 	setae	3735928559(%ebx,%ecx,8)
-        	setae	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setae	32493
-        	setae	0x7eed
-
-// CHECK: 	setae	3133065982
-        	setae	0xbabecafe
-
-// CHECK: 	setae	305419896
-        	setae	0x12345678
-
-// CHECK: 	sete	%bl
-        	sete	%bl
-
-// CHECK: 	sete	3735928559(%ebx,%ecx,8)
-        	sete	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sete	32493
-        	sete	0x7eed
-
-// CHECK: 	sete	3133065982
-        	sete	0xbabecafe
-
-// CHECK: 	sete	305419896
-        	sete	0x12345678
-
-// CHECK: 	setne	%bl
-        	setne	%bl
-
-// CHECK: 	setne	3735928559(%ebx,%ecx,8)
-        	setne	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setne	32493
-        	setne	0x7eed
-
-// CHECK: 	setne	3133065982
-        	setne	0xbabecafe
-
-// CHECK: 	setne	305419896
-        	setne	0x12345678
-
-// CHECK: 	setbe	%bl
-        	setbe	%bl
-
-// CHECK: 	setbe	3735928559(%ebx,%ecx,8)
-        	setbe	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setbe	32493
-        	setbe	0x7eed
-
-// CHECK: 	setbe	3133065982
-        	setbe	0xbabecafe
-
-// CHECK: 	setbe	305419896
-        	setbe	0x12345678
-
-// CHECK: 	seta	%bl
-        	seta	%bl
-
-// CHECK: 	seta	3735928559(%ebx,%ecx,8)
-        	seta	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	seta	32493
-        	seta	0x7eed
-
-// CHECK: 	seta	3133065982
-        	seta	0xbabecafe
-
-// CHECK: 	seta	305419896
-        	seta	0x12345678
-
-// CHECK: 	sets	%bl
-        	sets	%bl
-
-// CHECK: 	sets	3735928559(%ebx,%ecx,8)
-        	sets	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	sets	32493
-        	sets	0x7eed
-
-// CHECK: 	sets	3133065982
-        	sets	0xbabecafe
-
-// CHECK: 	sets	305419896
-        	sets	0x12345678
-
-// CHECK: 	setns	%bl
-        	setns	%bl
-
-// CHECK: 	setns	3735928559(%ebx,%ecx,8)
-        	setns	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setns	32493
-        	setns	0x7eed
-
-// CHECK: 	setns	3133065982
-        	setns	0xbabecafe
-
-// CHECK: 	setns	305419896
-        	setns	0x12345678
-
-// CHECK: 	setp	%bl
-        	setp	%bl
-
-// CHECK: 	setp	3735928559(%ebx,%ecx,8)
-        	setp	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setp	32493
-        	setp	0x7eed
-
-// CHECK: 	setp	3133065982
-        	setp	0xbabecafe
-
-// CHECK: 	setp	305419896
-        	setp	0x12345678
-
-// CHECK: 	setnp	%bl
-        	setnp	%bl
-
-// CHECK: 	setnp	3735928559(%ebx,%ecx,8)
-        	setnp	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setnp	32493
-        	setnp	0x7eed
-
-// CHECK: 	setnp	3133065982
-        	setnp	0xbabecafe
-
-// CHECK: 	setnp	305419896
-        	setnp	0x12345678
-
-// CHECK: 	setl	%bl
-        	setl	%bl
-
-// CHECK: 	setl	3735928559(%ebx,%ecx,8)
-        	setl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setl	32493
-        	setl	0x7eed
-
-// CHECK: 	setl	3133065982
-        	setl	0xbabecafe
-
-// CHECK: 	setl	305419896
-        	setl	0x12345678
-
-// CHECK: 	setge	%bl
-        	setge	%bl
-
-// CHECK: 	setge	3735928559(%ebx,%ecx,8)
-        	setge	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setge	32493
-        	setge	0x7eed
-
-// CHECK: 	setge	3133065982
-        	setge	0xbabecafe
-
-// CHECK: 	setge	305419896
-        	setge	0x12345678
-
-// CHECK: 	setle	%bl
-        	setle	%bl
-
-// CHECK: 	setle	3735928559(%ebx,%ecx,8)
-        	setle	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setle	32493
-        	setle	0x7eed
-
-// CHECK: 	setle	3133065982
-        	setle	0xbabecafe
-
-// CHECK: 	setle	305419896
-        	setle	0x12345678
-
-// CHECK: 	setg	%bl
-        	setg	%bl
-
-// CHECK: 	setg	3735928559(%ebx,%ecx,8)
-        	setg	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	setg	32493
-        	setg	0x7eed
-
-// CHECK: 	setg	3133065982
-        	setg	0xbabecafe
-
-// CHECK: 	setg	305419896
-        	setg	0x12345678
-
 // CHECK: 	int	$127
         	int	$0x7f
 
-// CHECK: 	rsm
-        	rsm
-
-// CHECK: 	hlt
-        	hlt
-
-// CHECK: 	nopl	3735928559(%ebx,%ecx,8)
-        	nopl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	nopw	32493
-        	nopw	0x7eed
-
-// CHECK: 	nopl	3133065982
-        	nopl	0xbabecafe
-
-// CHECK: 	nopl	305419896
-        	nopl	0x12345678
-
-// CHECK: 	nop
-        	nop
-
-// CHECK: 	lldtw	32493
-        	lldtw	0x7eed
-
-// CHECK: 	lmsww	32493
-        	lmsww	0x7eed
-
-// CHECK: 	ltrw	32493
-        	ltrw	0x7eed
-
-// CHECK: 	sldtw	32493
-        	sldtw	0x7eed
-
-// CHECK: 	smsww	32493
-        	smsww	0x7eed
-
-// CHECK: 	strw	32493
-        	strw	0x7eed
-
-// CHECK: 	verr	%bx
-        	verr	%bx
-
-// CHECK: 	verr	3735928559(%ebx,%ecx,8)
-        	verr	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	verr	3133065982
-        	verr	0xbabecafe
-
-// CHECK: 	verr	305419896
-        	verr	0x12345678
-
-// CHECK: 	verw	%bx
-        	verw	%bx
-
-// CHECK: 	verw	3735928559(%ebx,%ecx,8)
-        	verw	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	verw	3133065982
-        	verw	0xbabecafe
-
-// CHECK: 	verw	305419896
-        	verw	0x12345678
-
-// CHECK: 	fld	%st(2)
-        	fld	%st(2)
-
-// CHECK: 	fldl	3735928559(%ebx,%ecx,8)
-        	fldl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fldl	3133065982
-        	fldl	0xbabecafe
-
-// CHECK: 	fldl	305419896
-        	fldl	0x12345678
-
-// CHECK: 	fld	%st(2)
-        	fld	%st(2)
-
-// CHECK: 	fildl	3735928559(%ebx,%ecx,8)
-        	fildl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fildl	3133065982
-        	fildl	0xbabecafe
-
-// CHECK: 	fildl	305419896
-        	fildl	0x12345678
-
-// CHECK: 	fildll	3735928559(%ebx,%ecx,8)
-        	fildll	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fildll	32493
-        	fildll	0x7eed
-
-// CHECK: 	fildll	3133065982
-        	fildll	0xbabecafe
-
-// CHECK: 	fildll	305419896
-        	fildll	0x12345678
-
-// CHECK: 	fldt	3735928559(%ebx,%ecx,8)
-        	fldt	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fldt	32493
-        	fldt	0x7eed
-
-// CHECK: 	fldt	3133065982
-        	fldt	0xbabecafe
-
-// CHECK: 	fldt	305419896
-        	fldt	0x12345678
-
-// CHECK: 	fbld	3735928559(%ebx,%ecx,8)
-        	fbld	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fbld	32493
-        	fbld	0x7eed
-
-// CHECK: 	fbld	3133065982
-        	fbld	0xbabecafe
-
-// CHECK: 	fbld	305419896
-        	fbld	0x12345678
-
-// CHECK: 	fst	%st(2)
-        	fst	%st(2)
-
-// CHECK: 	fstl	3735928559(%ebx,%ecx,8)
-        	fstl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fstl	3133065982
-        	fstl	0xbabecafe
-
-// CHECK: 	fstl	305419896
-        	fstl	0x12345678
-
-// CHECK: 	fst	%st(2)
-        	fst	%st(2)
-
-// CHECK: 	fistl	3735928559(%ebx,%ecx,8)
-        	fistl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fistl	3133065982
-        	fistl	0xbabecafe
-
-// CHECK: 	fistl	305419896
-        	fistl	0x12345678
-
-// CHECK: 	fstp	%st(2)
-        	fstp	%st(2)
-
-// CHECK: 	fstpl	3735928559(%ebx,%ecx,8)
-        	fstpl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fstpl	3133065982
-        	fstpl	0xbabecafe
-
-// CHECK: 	fstpl	305419896
-        	fstpl	0x12345678
-
-// CHECK: 	fstp	%st(2)
-        	fstp	%st(2)
-
-// CHECK: 	fistpl	3735928559(%ebx,%ecx,8)
-        	fistpl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fistpl	3133065982
-        	fistpl	0xbabecafe
-
-// CHECK: 	fistpl	305419896
-        	fistpl	0x12345678
-
-// CHECK: 	fistpll	3735928559(%ebx,%ecx,8)
-        	fistpll	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fistpll	32493
-        	fistpll	0x7eed
-
-// CHECK: 	fistpll	3133065982
-        	fistpll	0xbabecafe
-
-// CHECK: 	fistpll	305419896
-        	fistpll	0x12345678
-
-// CHECK: 	fstpt	3735928559(%ebx,%ecx,8)
-        	fstpt	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fstpt	32493
-        	fstpt	0x7eed
-
-// CHECK: 	fstpt	3133065982
-        	fstpt	0xbabecafe
-
-// CHECK: 	fstpt	305419896
-        	fstpt	0x12345678
-
-// CHECK: 	fbstp	3735928559(%ebx,%ecx,8)
-        	fbstp	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fbstp	32493
-        	fbstp	0x7eed
-
-// CHECK: 	fbstp	3133065982
-        	fbstp	0xbabecafe
-
-// CHECK: 	fbstp	305419896
-        	fbstp	0x12345678
-
-// CHECK: 	fxch	%st(2)
-        	fxch	%st(2)
-
-// CHECK: 	fcom	%st(2)
-        	fcom	%st(2)
-
-// CHECK: 	fcoml	3735928559(%ebx,%ecx,8)
-        	fcoml	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fcoml	3133065982
-        	fcoml	0xbabecafe
-
-// CHECK: 	fcoml	305419896
-        	fcoml	0x12345678
-
-// CHECK: 	fcom	%st(2)
-        	fcom	%st(2)
-
-// CHECK: 	ficoml	3735928559(%ebx,%ecx,8)
-        	ficoml	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	ficoml	3133065982
-        	ficoml	0xbabecafe
-
-// CHECK: 	ficoml	305419896
-        	ficoml	0x12345678
-
-// CHECK: 	fcomp	%st(2)
-        	fcomp	%st(2)
-
-// CHECK: 	fcompl	3735928559(%ebx,%ecx,8)
-        	fcompl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fcompl	3133065982
-        	fcompl	0xbabecafe
-
-// CHECK: 	fcompl	305419896
-        	fcompl	0x12345678
-
-// CHECK: 	fcomp	%st(2)
-        	fcomp	%st(2)
-
-// CHECK: 	ficompl	3735928559(%ebx,%ecx,8)
-        	ficompl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	ficompl	3133065982
-        	ficompl	0xbabecafe
-
-// CHECK: 	ficompl	305419896
-        	ficompl	0x12345678
-
-// CHECK: 	fcompp
-        	fcompp
-
-// CHECK: 	fucom	%st(2)
-        	fucom	%st(2)
-
-// CHECK: 	fucomp	%st(2)
-        	fucomp	%st(2)
-
-// CHECK: 	fucompp
-        	fucompp
-
-// CHECK: 	ftst
-        	ftst
-
-// CHECK: 	fxam
-        	fxam
-
-// CHECK: 	fld1
-        	fld1
-
-// CHECK: 	fldl2t
-        	fldl2t
-
-// CHECK: 	fldl2e
-        	fldl2e
-
-// CHECK: 	fldpi
-        	fldpi
-
-// CHECK: 	fldlg2
-        	fldlg2
-
-// CHECK: 	fldln2
-        	fldln2
-
-// CHECK: 	fldz
-        	fldz
-
-// CHECK: 	fadd	%st(2)
-        	fadd	%st(2)
-
-// CHECK: 	faddl	3735928559(%ebx,%ecx,8)
-        	faddl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	faddl	3133065982
-        	faddl	0xbabecafe
-
-// CHECK: 	faddl	305419896
-        	faddl	0x12345678
-
-// CHECK: 	fiaddl	3735928559(%ebx,%ecx,8)
-        	fiaddl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fiaddl	3133065982
-        	fiaddl	0xbabecafe
-
-// CHECK: 	fiaddl	305419896
-        	fiaddl	0x12345678
-
-// CHECK: 	faddp	%st(2)
-        	faddp	%st(2)
-
-// CHECK: 	fsub	%st(2)
-        	fsub	%st(2)
-
-// CHECK: 	fsubl	3735928559(%ebx,%ecx,8)
-        	fsubl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fsubl	3133065982
-        	fsubl	0xbabecafe
-
-// CHECK: 	fsubl	305419896
-        	fsubl	0x12345678
-
-// CHECK: 	fisubl	3735928559(%ebx,%ecx,8)
-        	fisubl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fisubl	3133065982
-        	fisubl	0xbabecafe
-
-// CHECK: 	fisubl	305419896
-        	fisubl	0x12345678
-
-// CHECK: 	fsubp	%st(2)
-        	fsubp	%st(2)
-
-// CHECK: 	fsubr	%st(2)
-        	fsubr	%st(2)
-
-// CHECK: 	fsubrl	3735928559(%ebx,%ecx,8)
-        	fsubrl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fsubrl	3133065982
-        	fsubrl	0xbabecafe
-
-// CHECK: 	fsubrl	305419896
-        	fsubrl	0x12345678
-
-// CHECK: 	fisubrl	3735928559(%ebx,%ecx,8)
-        	fisubrl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fisubrl	3133065982
-        	fisubrl	0xbabecafe
-
-// CHECK: 	fisubrl	305419896
-        	fisubrl	0x12345678
-
-// CHECK: 	fsubrp	%st(2)
-        	fsubrp	%st(2)
-
-// CHECK: 	fmul	%st(2)
-        	fmul	%st(2)
-
-// CHECK: 	fmull	3735928559(%ebx,%ecx,8)
-        	fmull	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fmull	3133065982
-        	fmull	0xbabecafe
-
-// CHECK: 	fmull	305419896
-        	fmull	0x12345678
-
-// CHECK: 	fimull	3735928559(%ebx,%ecx,8)
-        	fimull	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fimull	3133065982
-        	fimull	0xbabecafe
-
-// CHECK: 	fimull	305419896
-        	fimull	0x12345678
-
-// CHECK: 	fmulp	%st(2)
-        	fmulp	%st(2)
-
-// CHECK: 	fdiv	%st(2)
-        	fdiv	%st(2)
-
-// CHECK: 	fdivl	3735928559(%ebx,%ecx,8)
-        	fdivl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fdivl	3133065982
-        	fdivl	0xbabecafe
-
-// CHECK: 	fdivl	305419896
-        	fdivl	0x12345678
-
-// CHECK: 	fidivl	3735928559(%ebx,%ecx,8)
-        	fidivl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fidivl	3133065982
-        	fidivl	0xbabecafe
-
-// CHECK: 	fidivl	305419896
-        	fidivl	0x12345678
-
-// CHECK: 	fdivp	%st(2)
-        	fdivp	%st(2)
-
-// CHECK: 	fdivr	%st(2)
-        	fdivr	%st(2)
-
-// CHECK: 	fdivrl	3735928559(%ebx,%ecx,8)
-        	fdivrl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fdivrl	3133065982
-        	fdivrl	0xbabecafe
-
-// CHECK: 	fdivrl	305419896
-        	fdivrl	0x12345678
-
-// CHECK: 	fidivrl	3735928559(%ebx,%ecx,8)
-        	fidivrl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fidivrl	3133065982
-        	fidivrl	0xbabecafe
-
-// CHECK: 	fidivrl	305419896
-        	fidivrl	0x12345678
-
-// CHECK: 	fdivrp	%st(2)
-        	fdivrp	%st(2)
-
-// CHECK: 	f2xm1
-        	f2xm1
-
-// CHECK: 	fyl2x
-        	fyl2x
-
-// CHECK: 	fptan
-        	fptan
-
-// CHECK: 	fpatan
-        	fpatan
-
-// CHECK: 	fxtract
-        	fxtract
-
-// CHECK: 	fprem1
-        	fprem1
-
-// CHECK: 	fdecstp
-        	fdecstp
-
-// CHECK: 	fincstp
-        	fincstp
-
-// CHECK: 	fprem
-        	fprem
-
-// CHECK: 	fyl2xp1
-        	fyl2xp1
-
-// CHECK: 	fsqrt
-        	fsqrt
-
-// CHECK: 	fsincos
-        	fsincos
-
-// CHECK: 	frndint
-        	frndint
-
-// CHECK: 	fscale
-        	fscale
-
-// CHECK: 	fsin
-        	fsin
-
-// CHECK: 	fcos
-        	fcos
-
-// CHECK: 	fchs
-        	fchs
-
-// CHECK: 	fabs
-        	fabs
-
-// CHECK: 	fninit
-        	fninit
-
-// CHECK: 	fldcw	3735928559(%ebx,%ecx,8)
-        	fldcw	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fldcw	3133065982
-        	fldcw	0xbabecafe
-
-// CHECK: 	fldcw	305419896
-        	fldcw	0x12345678
-
-// CHECK: 	fnstcw	3735928559(%ebx,%ecx,8)
-        	fnstcw	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fnstcw	3133065982
-        	fnstcw	0xbabecafe
-
-// CHECK: 	fnstcw	305419896
-        	fnstcw	0x12345678
-
-// CHECK: 	fnstsw	3735928559(%ebx,%ecx,8)
-        	fnstsw	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fnstsw	3133065982
-        	fnstsw	0xbabecafe
-
-// CHECK: 	fnstsw	305419896
-        	fnstsw	0x12345678
-
-// CHECK: 	fnclex
-        	fnclex
-
-// CHECK: 	fnstenv	32493
-        	fnstenv	0x7eed
-
-// CHECK: 	fldenv	32493
-        	fldenv	0x7eed
-
-// CHECK: 	fnsave	32493
-        	fnsave	0x7eed
-
-// CHECK: 	frstor	32493
-        	frstor	0x7eed
-
-// CHECK: 	ffree	%st(2)
-        	ffree	%st(2)
-
-// CHECK: 	fnop
-        	fnop
-
-// CHECK: 	invd
-        	invd
-
-// CHECK: 	wbinvd
-        	wbinvd
-
-// CHECK: 	cpuid
-        	cpuid
-
-// CHECK: 	wrmsr
-        	wrmsr
-
-// CHECK: 	rdtsc
-        	rdtsc
-
-// CHECK: 	rdmsr
-        	rdmsr
-
-// CHECK: 	cmpxchg8b	3735928559(%ebx,%ecx,8)
-        	cmpxchg8b	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	cmpxchg8b	32493
-        	cmpxchg8b	0x7eed
-
-// CHECK: 	cmpxchg8b	3133065982
-        	cmpxchg8b	0xbabecafe
-
-// CHECK: 	cmpxchg8b	305419896
-        	cmpxchg8b	0x12345678
-
-// CHECK: 	sysenter
-        	sysenter
-
-// CHECK: 	sysexit
-        	sysexit
-
-// CHECK: 	fxsave	3735928559(%ebx,%ecx,8)
-        	fxsave	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fxsave	32493
-        	fxsave	0x7eed
-
-// CHECK: 	fxsave	3133065982
-        	fxsave	0xbabecafe
-
-// CHECK: 	fxsave	305419896
-        	fxsave	0x12345678
-
-// CHECK: 	fxrstor	3735928559(%ebx,%ecx,8)
-        	fxrstor	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fxrstor	32493
-        	fxrstor	0x7eed
-
-// CHECK: 	fxrstor	3133065982
-        	fxrstor	0xbabecafe
-
-// CHECK: 	fxrstor	305419896
-        	fxrstor	0x12345678
-
-// CHECK: 	rdpmc
-        	rdpmc
-
-// CHECK: 	ud2
-        	ud2
-
-// CHECK: 	fcmovb	%st(2), %st(0)
-        	fcmovb	%st(2),%st
-
-// CHECK: 	fcmove	%st(2), %st(0)
-        	fcmove	%st(2),%st
-
-// CHECK: 	fcmovbe	%st(2), %st(0)
-        	fcmovbe	%st(2),%st
-
-// CHECK: 	fcmovu	 %st(2), %st(0)
-        	fcmovu	%st(2),%st
-
-// CHECK: 	fcmovnb	%st(2), %st(0)
-        	fcmovnb	%st(2),%st
-
-// CHECK: 	fcmovne	%st(2), %st(0)
-        	fcmovne	%st(2),%st
-
-// CHECK: 	fcmovnbe	%st(2), %st(0)
-        	fcmovnbe	%st(2),%st
-
-// CHECK: 	fcmovnu	%st(2), %st(0)
-        	fcmovnu	%st(2),%st
-
-// CHECK: 	fcomi	%st(2)
-        	fcomi	%st(2),%st
-
-// CHECK: 	fucomi	%st(2)
-        	fucomi	%st(2),%st
-
-// CHECK: 	fcompi	%st(2)
-        	fcomip	%st(2),%st
-
-// CHECK: 	fucompi	%st(2)
-        	fucomip	%st(2),%st
-
-// CHECK: 	movntil	%ecx, 3735928559(%ebx,%ecx,8)
-        	movnti	%ecx,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movntil	%ecx, 69
-        	movntil	%ecx,0x45
-
-// CHECK: 	movntil	%ecx, 32493
-        	movnti	%ecx,0x7eed
-
-// CHECK: 	movntil	%ecx, 3133065982
-        	movnti	%ecx,0xbabecafe
-
-// CHECK: 	movntil	%ecx, 305419896
-        	movnti	%ecx,0x12345678
-
-// CHECK: 	clflush	3735928559(%ebx,%ecx,8)
-        	clflush	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	clflush	32493
-        	clflush	0x7eed
-
-// CHECK: 	clflush	3133065982
-        	clflush	0xbabecafe
-
-// CHECK: 	clflush	305419896
-        	clflush	0x12345678
-
 // CHECK: 	pause
         	pause
 
@@ -14231,4185 +10454,9 @@
 // CHECK: 	mfence
         	mfence
 
-// CHECK: 	emms
-        	emms
-
-// CHECK: 	movd	%ecx, %mm3
-        	movd	%ecx,%mm3
-
-// CHECK: 	movd	3735928559(%ebx,%ecx,8), %mm3
-        	movd	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	movd	69, %mm3
-        	movd	0x45,%mm3
-
-// CHECK: 	movd	32493, %mm3
-        	movd	0x7eed,%mm3
-
-// CHECK: 	movd	3133065982, %mm3
-        	movd	0xbabecafe,%mm3
-
-// CHECK: 	movd	305419896, %mm3
-        	movd	0x12345678,%mm3
-
-// CHECK: 	movd	%mm3, %ecx
-        	movd	%mm3,%ecx
-
-// CHECK: 	movd	%mm3, 3735928559(%ebx,%ecx,8)
-        	movd	%mm3,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movd	%mm3, 69
-        	movd	%mm3,0x45
-
-// CHECK: 	movd	%mm3, 32493
-        	movd	%mm3,0x7eed
-
-// CHECK: 	movd	%mm3, 3133065982
-        	movd	%mm3,0xbabecafe
-
-// CHECK: 	movd	%mm3, 305419896
-        	movd	%mm3,0x12345678
-
-// CHECK: 	movd	%ecx, %xmm5
-        	movd	%ecx,%xmm5
-
-// CHECK: 	movd	3735928559(%ebx,%ecx,8), %xmm5
-        	movd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movd	69, %xmm5
-        	movd	0x45,%xmm5
-
-// CHECK: 	movd	32493, %xmm5
-        	movd	0x7eed,%xmm5
-
-// CHECK: 	movd	3133065982, %xmm5
-        	movd	0xbabecafe,%xmm5
-
-// CHECK: 	movd	305419896, %xmm5
-        	movd	0x12345678,%xmm5
-
-// CHECK: 	movd	%xmm5, %ecx
-        	movd	%xmm5,%ecx
-
-// CHECK: 	movd	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movd	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movd	%xmm5, 69
-        	movd	%xmm5,0x45
-
-// CHECK: 	movd	%xmm5, 32493
-        	movd	%xmm5,0x7eed
-
-// CHECK: 	movd	%xmm5, 3133065982
-        	movd	%xmm5,0xbabecafe
-
-// CHECK: 	movd	%xmm5, 305419896
-        	movd	%xmm5,0x12345678
-
-// CHECK: 	movq	3735928559(%ebx,%ecx,8), %mm3
-        	movq	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	movq	69, %mm3
-        	movq	0x45,%mm3
-
-// CHECK: 	movq	32493, %mm3
-        	movq	0x7eed,%mm3
-
-// CHECK: 	movq	3133065982, %mm3
-        	movq	0xbabecafe,%mm3
-
-// CHECK: 	movq	305419896, %mm3
-        	movq	0x12345678,%mm3
-
-// CHECK: 	movq	%mm3, %mm3
-        	movq	%mm3,%mm3
-
-// CHECK: 	movq	%mm3, 3735928559(%ebx,%ecx,8)
-        	movq	%mm3,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movq	%mm3, 69
-        	movq	%mm3,0x45
-
-// CHECK: 	movq	%mm3, 32493
-        	movq	%mm3,0x7eed
-
-// CHECK: 	movq	%mm3, 3133065982
-        	movq	%mm3,0xbabecafe
-
-// CHECK: 	movq	%mm3, 305419896
-        	movq	%mm3,0x12345678
-
-// CHECK: 	movq	%mm3, %mm3
-        	movq	%mm3,%mm3
-
-// CHECK: 	movq	3735928559(%ebx,%ecx,8), %xmm5
-        	movq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movq	69, %xmm5
-        	movq	0x45,%xmm5
-
-// CHECK: 	movq	32493, %xmm5
-        	movq	0x7eed,%xmm5
-
-// CHECK: 	movq	3133065982, %xmm5
-        	movq	0xbabecafe,%xmm5
-
-// CHECK: 	movq	305419896, %xmm5
-        	movq	0x12345678,%xmm5
-
-// CHECK: 	movq	%xmm5, %xmm5
-        	movq	%xmm5,%xmm5
-
-// CHECK: 	movq	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movq	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movq	%xmm5, 69
-        	movq	%xmm5,0x45
-
-// CHECK: 	movq	%xmm5, 32493
-        	movq	%xmm5,0x7eed
-
-// CHECK: 	movq	%xmm5, 3133065982
-        	movq	%xmm5,0xbabecafe
-
-// CHECK: 	movq	%xmm5, 305419896
-        	movq	%xmm5,0x12345678
-
-// CHECK: 	movq	%xmm5, %xmm5
-        	movq	%xmm5,%xmm5
-
-// CHECK: 	packssdw	3735928559(%ebx,%ecx,8), %mm3
-        	packssdw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	packssdw	69, %mm3
-        	packssdw	0x45,%mm3
-
-// CHECK: 	packssdw	32493, %mm3
-        	packssdw	0x7eed,%mm3
-
-// CHECK: 	packssdw	3133065982, %mm3
-        	packssdw	0xbabecafe,%mm3
-
-// CHECK: 	packssdw	305419896, %mm3
-        	packssdw	0x12345678,%mm3
-
-// CHECK: 	packssdw	%mm3, %mm3
-        	packssdw	%mm3,%mm3
-
-// CHECK: 	packssdw	3735928559(%ebx,%ecx,8), %xmm5
-        	packssdw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	packssdw	69, %xmm5
-        	packssdw	0x45,%xmm5
-
-// CHECK: 	packssdw	32493, %xmm5
-        	packssdw	0x7eed,%xmm5
-
-// CHECK: 	packssdw	3133065982, %xmm5
-        	packssdw	0xbabecafe,%xmm5
-
-// CHECK: 	packssdw	305419896, %xmm5
-        	packssdw	0x12345678,%xmm5
-
-// CHECK: 	packssdw	%xmm5, %xmm5
-        	packssdw	%xmm5,%xmm5
-
-// CHECK: 	packsswb	3735928559(%ebx,%ecx,8), %mm3
-        	packsswb	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	packsswb	69, %mm3
-        	packsswb	0x45,%mm3
-
-// CHECK: 	packsswb	32493, %mm3
-        	packsswb	0x7eed,%mm3
-
-// CHECK: 	packsswb	3133065982, %mm3
-        	packsswb	0xbabecafe,%mm3
-
-// CHECK: 	packsswb	305419896, %mm3
-        	packsswb	0x12345678,%mm3
-
-// CHECK: 	packsswb	%mm3, %mm3
-        	packsswb	%mm3,%mm3
-
-// CHECK: 	packsswb	3735928559(%ebx,%ecx,8), %xmm5
-        	packsswb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	packsswb	69, %xmm5
-        	packsswb	0x45,%xmm5
-
-// CHECK: 	packsswb	32493, %xmm5
-        	packsswb	0x7eed,%xmm5
-
-// CHECK: 	packsswb	3133065982, %xmm5
-        	packsswb	0xbabecafe,%xmm5
-
-// CHECK: 	packsswb	305419896, %xmm5
-        	packsswb	0x12345678,%xmm5
-
-// CHECK: 	packsswb	%xmm5, %xmm5
-        	packsswb	%xmm5,%xmm5
-
-// CHECK: 	packuswb	3735928559(%ebx,%ecx,8), %mm3
-        	packuswb	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	packuswb	69, %mm3
-        	packuswb	0x45,%mm3
-
-// CHECK: 	packuswb	32493, %mm3
-        	packuswb	0x7eed,%mm3
-
-// CHECK: 	packuswb	3133065982, %mm3
-        	packuswb	0xbabecafe,%mm3
-
-// CHECK: 	packuswb	305419896, %mm3
-        	packuswb	0x12345678,%mm3
-
-// CHECK: 	packuswb	%mm3, %mm3
-        	packuswb	%mm3,%mm3
-
-// CHECK: 	packuswb	3735928559(%ebx,%ecx,8), %xmm5
-        	packuswb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	packuswb	69, %xmm5
-        	packuswb	0x45,%xmm5
-
-// CHECK: 	packuswb	32493, %xmm5
-        	packuswb	0x7eed,%xmm5
-
-// CHECK: 	packuswb	3133065982, %xmm5
-        	packuswb	0xbabecafe,%xmm5
-
-// CHECK: 	packuswb	305419896, %xmm5
-        	packuswb	0x12345678,%xmm5
-
-// CHECK: 	packuswb	%xmm5, %xmm5
-        	packuswb	%xmm5,%xmm5
-
-// CHECK: 	paddb	3735928559(%ebx,%ecx,8), %mm3
-        	paddb	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	paddb	69, %mm3
-        	paddb	0x45,%mm3
-
-// CHECK: 	paddb	32493, %mm3
-        	paddb	0x7eed,%mm3
-
-// CHECK: 	paddb	3133065982, %mm3
-        	paddb	0xbabecafe,%mm3
-
-// CHECK: 	paddb	305419896, %mm3
-        	paddb	0x12345678,%mm3
-
-// CHECK: 	paddb	%mm3, %mm3
-        	paddb	%mm3,%mm3
-
-// CHECK: 	paddb	3735928559(%ebx,%ecx,8), %xmm5
-        	paddb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	paddb	69, %xmm5
-        	paddb	0x45,%xmm5
-
-// CHECK: 	paddb	32493, %xmm5
-        	paddb	0x7eed,%xmm5
-
-// CHECK: 	paddb	3133065982, %xmm5
-        	paddb	0xbabecafe,%xmm5
-
-// CHECK: 	paddb	305419896, %xmm5
-        	paddb	0x12345678,%xmm5
-
-// CHECK: 	paddb	%xmm5, %xmm5
-        	paddb	%xmm5,%xmm5
-
-// CHECK: 	paddw	3735928559(%ebx,%ecx,8), %mm3
-        	paddw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	paddw	69, %mm3
-        	paddw	0x45,%mm3
-
-// CHECK: 	paddw	32493, %mm3
-        	paddw	0x7eed,%mm3
-
-// CHECK: 	paddw	3133065982, %mm3
-        	paddw	0xbabecafe,%mm3
-
-// CHECK: 	paddw	305419896, %mm3
-        	paddw	0x12345678,%mm3
-
-// CHECK: 	paddw	%mm3, %mm3
-        	paddw	%mm3,%mm3
-
-// CHECK: 	paddw	3735928559(%ebx,%ecx,8), %xmm5
-        	paddw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	paddw	69, %xmm5
-        	paddw	0x45,%xmm5
-
-// CHECK: 	paddw	32493, %xmm5
-        	paddw	0x7eed,%xmm5
-
-// CHECK: 	paddw	3133065982, %xmm5
-        	paddw	0xbabecafe,%xmm5
-
-// CHECK: 	paddw	305419896, %xmm5
-        	paddw	0x12345678,%xmm5
-
-// CHECK: 	paddw	%xmm5, %xmm5
-        	paddw	%xmm5,%xmm5
-
-// CHECK: 	paddd	3735928559(%ebx,%ecx,8), %mm3
-        	paddd	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	paddd	69, %mm3
-        	paddd	0x45,%mm3
-
-// CHECK: 	paddd	32493, %mm3
-        	paddd	0x7eed,%mm3
-
-// CHECK: 	paddd	3133065982, %mm3
-        	paddd	0xbabecafe,%mm3
-
-// CHECK: 	paddd	305419896, %mm3
-        	paddd	0x12345678,%mm3
-
-// CHECK: 	paddd	%mm3, %mm3
-        	paddd	%mm3,%mm3
-
-// CHECK: 	paddd	3735928559(%ebx,%ecx,8), %xmm5
-        	paddd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	paddd	69, %xmm5
-        	paddd	0x45,%xmm5
-
-// CHECK: 	paddd	32493, %xmm5
-        	paddd	0x7eed,%xmm5
-
-// CHECK: 	paddd	3133065982, %xmm5
-        	paddd	0xbabecafe,%xmm5
-
-// CHECK: 	paddd	305419896, %xmm5
-        	paddd	0x12345678,%xmm5
-
-// CHECK: 	paddd	%xmm5, %xmm5
-        	paddd	%xmm5,%xmm5
-
-// CHECK: 	paddq	3735928559(%ebx,%ecx,8), %mm3
-        	paddq	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	paddq	69, %mm3
-        	paddq	0x45,%mm3
-
-// CHECK: 	paddq	32493, %mm3
-        	paddq	0x7eed,%mm3
-
-// CHECK: 	paddq	3133065982, %mm3
-        	paddq	0xbabecafe,%mm3
-
-// CHECK: 	paddq	305419896, %mm3
-        	paddq	0x12345678,%mm3
-
-// CHECK: 	paddq	%mm3, %mm3
-        	paddq	%mm3,%mm3
-
-// CHECK: 	paddq	3735928559(%ebx,%ecx,8), %xmm5
-        	paddq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	paddq	69, %xmm5
-        	paddq	0x45,%xmm5
-
-// CHECK: 	paddq	32493, %xmm5
-        	paddq	0x7eed,%xmm5
-
-// CHECK: 	paddq	3133065982, %xmm5
-        	paddq	0xbabecafe,%xmm5
-
-// CHECK: 	paddq	305419896, %xmm5
-        	paddq	0x12345678,%xmm5
-
-// CHECK: 	paddq	%xmm5, %xmm5
-        	paddq	%xmm5,%xmm5
-
-// CHECK: 	paddsb	3735928559(%ebx,%ecx,8), %mm3
-        	paddsb	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	paddsb	69, %mm3
-        	paddsb	0x45,%mm3
-
-// CHECK: 	paddsb	32493, %mm3
-        	paddsb	0x7eed,%mm3
-
-// CHECK: 	paddsb	3133065982, %mm3
-        	paddsb	0xbabecafe,%mm3
-
-// CHECK: 	paddsb	305419896, %mm3
-        	paddsb	0x12345678,%mm3
-
-// CHECK: 	paddsb	%mm3, %mm3
-        	paddsb	%mm3,%mm3
-
-// CHECK: 	paddsb	3735928559(%ebx,%ecx,8), %xmm5
-        	paddsb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	paddsb	69, %xmm5
-        	paddsb	0x45,%xmm5
-
-// CHECK: 	paddsb	32493, %xmm5
-        	paddsb	0x7eed,%xmm5
-
-// CHECK: 	paddsb	3133065982, %xmm5
-        	paddsb	0xbabecafe,%xmm5
-
-// CHECK: 	paddsb	305419896, %xmm5
-        	paddsb	0x12345678,%xmm5
-
-// CHECK: 	paddsb	%xmm5, %xmm5
-        	paddsb	%xmm5,%xmm5
-
-// CHECK: 	paddsw	3735928559(%ebx,%ecx,8), %mm3
-        	paddsw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	paddsw	69, %mm3
-        	paddsw	0x45,%mm3
-
-// CHECK: 	paddsw	32493, %mm3
-        	paddsw	0x7eed,%mm3
-
-// CHECK: 	paddsw	3133065982, %mm3
-        	paddsw	0xbabecafe,%mm3
-
-// CHECK: 	paddsw	305419896, %mm3
-        	paddsw	0x12345678,%mm3
-
-// CHECK: 	paddsw	%mm3, %mm3
-        	paddsw	%mm3,%mm3
-
-// CHECK: 	paddsw	3735928559(%ebx,%ecx,8), %xmm5
-        	paddsw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	paddsw	69, %xmm5
-        	paddsw	0x45,%xmm5
-
-// CHECK: 	paddsw	32493, %xmm5
-        	paddsw	0x7eed,%xmm5
-
-// CHECK: 	paddsw	3133065982, %xmm5
-        	paddsw	0xbabecafe,%xmm5
-
-// CHECK: 	paddsw	305419896, %xmm5
-        	paddsw	0x12345678,%xmm5
-
-// CHECK: 	paddsw	%xmm5, %xmm5
-        	paddsw	%xmm5,%xmm5
-
-// CHECK: 	paddusb	3735928559(%ebx,%ecx,8), %mm3
-        	paddusb	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	paddusb	69, %mm3
-        	paddusb	0x45,%mm3
-
-// CHECK: 	paddusb	32493, %mm3
-        	paddusb	0x7eed,%mm3
-
-// CHECK: 	paddusb	3133065982, %mm3
-        	paddusb	0xbabecafe,%mm3
-
-// CHECK: 	paddusb	305419896, %mm3
-        	paddusb	0x12345678,%mm3
-
-// CHECK: 	paddusb	%mm3, %mm3
-        	paddusb	%mm3,%mm3
-
-// CHECK: 	paddusb	3735928559(%ebx,%ecx,8), %xmm5
-        	paddusb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	paddusb	69, %xmm5
-        	paddusb	0x45,%xmm5
-
-// CHECK: 	paddusb	32493, %xmm5
-        	paddusb	0x7eed,%xmm5
-
-// CHECK: 	paddusb	3133065982, %xmm5
-        	paddusb	0xbabecafe,%xmm5
-
-// CHECK: 	paddusb	305419896, %xmm5
-        	paddusb	0x12345678,%xmm5
-
-// CHECK: 	paddusb	%xmm5, %xmm5
-        	paddusb	%xmm5,%xmm5
-
-// CHECK: 	paddusw	3735928559(%ebx,%ecx,8), %mm3
-        	paddusw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	paddusw	69, %mm3
-        	paddusw	0x45,%mm3
-
-// CHECK: 	paddusw	32493, %mm3
-        	paddusw	0x7eed,%mm3
-
-// CHECK: 	paddusw	3133065982, %mm3
-        	paddusw	0xbabecafe,%mm3
-
-// CHECK: 	paddusw	305419896, %mm3
-        	paddusw	0x12345678,%mm3
-
-// CHECK: 	paddusw	%mm3, %mm3
-        	paddusw	%mm3,%mm3
-
-// CHECK: 	paddusw	3735928559(%ebx,%ecx,8), %xmm5
-        	paddusw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	paddusw	69, %xmm5
-        	paddusw	0x45,%xmm5
-
-// CHECK: 	paddusw	32493, %xmm5
-        	paddusw	0x7eed,%xmm5
-
-// CHECK: 	paddusw	3133065982, %xmm5
-        	paddusw	0xbabecafe,%xmm5
-
-// CHECK: 	paddusw	305419896, %xmm5
-        	paddusw	0x12345678,%xmm5
-
-// CHECK: 	paddusw	%xmm5, %xmm5
-        	paddusw	%xmm5,%xmm5
-
-// CHECK: 	pand	3735928559(%ebx,%ecx,8), %mm3
-        	pand	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pand	69, %mm3
-        	pand	0x45,%mm3
-
-// CHECK: 	pand	32493, %mm3
-        	pand	0x7eed,%mm3
-
-// CHECK: 	pand	3133065982, %mm3
-        	pand	0xbabecafe,%mm3
-
-// CHECK: 	pand	305419896, %mm3
-        	pand	0x12345678,%mm3
-
-// CHECK: 	pand	%mm3, %mm3
-        	pand	%mm3,%mm3
-
-// CHECK: 	pand	3735928559(%ebx,%ecx,8), %xmm5
-        	pand	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pand	69, %xmm5
-        	pand	0x45,%xmm5
-
-// CHECK: 	pand	32493, %xmm5
-        	pand	0x7eed,%xmm5
-
-// CHECK: 	pand	3133065982, %xmm5
-        	pand	0xbabecafe,%xmm5
-
-// CHECK: 	pand	305419896, %xmm5
-        	pand	0x12345678,%xmm5
-
-// CHECK: 	pand	%xmm5, %xmm5
-        	pand	%xmm5,%xmm5
-
-// CHECK: 	pandn	3735928559(%ebx,%ecx,8), %mm3
-        	pandn	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pandn	69, %mm3
-        	pandn	0x45,%mm3
-
-// CHECK: 	pandn	32493, %mm3
-        	pandn	0x7eed,%mm3
-
-// CHECK: 	pandn	3133065982, %mm3
-        	pandn	0xbabecafe,%mm3
-
-// CHECK: 	pandn	305419896, %mm3
-        	pandn	0x12345678,%mm3
-
-// CHECK: 	pandn	%mm3, %mm3
-        	pandn	%mm3,%mm3
-
-// CHECK: 	pandn	3735928559(%ebx,%ecx,8), %xmm5
-        	pandn	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pandn	69, %xmm5
-        	pandn	0x45,%xmm5
-
-// CHECK: 	pandn	32493, %xmm5
-        	pandn	0x7eed,%xmm5
-
-// CHECK: 	pandn	3133065982, %xmm5
-        	pandn	0xbabecafe,%xmm5
-
-// CHECK: 	pandn	305419896, %xmm5
-        	pandn	0x12345678,%xmm5
-
-// CHECK: 	pandn	%xmm5, %xmm5
-        	pandn	%xmm5,%xmm5
-
-// CHECK: 	pcmpeqb	3735928559(%ebx,%ecx,8), %mm3
-        	pcmpeqb	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pcmpeqb	69, %mm3
-        	pcmpeqb	0x45,%mm3
-
-// CHECK: 	pcmpeqb	32493, %mm3
-        	pcmpeqb	0x7eed,%mm3
-
-// CHECK: 	pcmpeqb	3133065982, %mm3
-        	pcmpeqb	0xbabecafe,%mm3
-
-// CHECK: 	pcmpeqb	305419896, %mm3
-        	pcmpeqb	0x12345678,%mm3
-
-// CHECK: 	pcmpeqb	%mm3, %mm3
-        	pcmpeqb	%mm3,%mm3
-
-// CHECK: 	pcmpeqb	3735928559(%ebx,%ecx,8), %xmm5
-        	pcmpeqb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pcmpeqb	69, %xmm5
-        	pcmpeqb	0x45,%xmm5
-
-// CHECK: 	pcmpeqb	32493, %xmm5
-        	pcmpeqb	0x7eed,%xmm5
-
-// CHECK: 	pcmpeqb	3133065982, %xmm5
-        	pcmpeqb	0xbabecafe,%xmm5
-
-// CHECK: 	pcmpeqb	305419896, %xmm5
-        	pcmpeqb	0x12345678,%xmm5
-
-// CHECK: 	pcmpeqb	%xmm5, %xmm5
-        	pcmpeqb	%xmm5,%xmm5
-
-// CHECK: 	pcmpeqw	3735928559(%ebx,%ecx,8), %mm3
-        	pcmpeqw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pcmpeqw	69, %mm3
-        	pcmpeqw	0x45,%mm3
-
-// CHECK: 	pcmpeqw	32493, %mm3
-        	pcmpeqw	0x7eed,%mm3
-
-// CHECK: 	pcmpeqw	3133065982, %mm3
-        	pcmpeqw	0xbabecafe,%mm3
-
-// CHECK: 	pcmpeqw	305419896, %mm3
-        	pcmpeqw	0x12345678,%mm3
-
-// CHECK: 	pcmpeqw	%mm3, %mm3
-        	pcmpeqw	%mm3,%mm3
-
-// CHECK: 	pcmpeqw	3735928559(%ebx,%ecx,8), %xmm5
-        	pcmpeqw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pcmpeqw	69, %xmm5
-        	pcmpeqw	0x45,%xmm5
-
-// CHECK: 	pcmpeqw	32493, %xmm5
-        	pcmpeqw	0x7eed,%xmm5
-
-// CHECK: 	pcmpeqw	3133065982, %xmm5
-        	pcmpeqw	0xbabecafe,%xmm5
-
-// CHECK: 	pcmpeqw	305419896, %xmm5
-        	pcmpeqw	0x12345678,%xmm5
-
-// CHECK: 	pcmpeqw	%xmm5, %xmm5
-        	pcmpeqw	%xmm5,%xmm5
-
-// CHECK: 	pcmpeqd	3735928559(%ebx,%ecx,8), %mm3
-        	pcmpeqd	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pcmpeqd	69, %mm3
-        	pcmpeqd	0x45,%mm3
-
-// CHECK: 	pcmpeqd	32493, %mm3
-        	pcmpeqd	0x7eed,%mm3
-
-// CHECK: 	pcmpeqd	3133065982, %mm3
-        	pcmpeqd	0xbabecafe,%mm3
-
-// CHECK: 	pcmpeqd	305419896, %mm3
-        	pcmpeqd	0x12345678,%mm3
-
-// CHECK: 	pcmpeqd	%mm3, %mm3
-        	pcmpeqd	%mm3,%mm3
-
-// CHECK: 	pcmpeqd	3735928559(%ebx,%ecx,8), %xmm5
-        	pcmpeqd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pcmpeqd	69, %xmm5
-        	pcmpeqd	0x45,%xmm5
-
-// CHECK: 	pcmpeqd	32493, %xmm5
-        	pcmpeqd	0x7eed,%xmm5
-
-// CHECK: 	pcmpeqd	3133065982, %xmm5
-        	pcmpeqd	0xbabecafe,%xmm5
-
-// CHECK: 	pcmpeqd	305419896, %xmm5
-        	pcmpeqd	0x12345678,%xmm5
-
-// CHECK: 	pcmpeqd	%xmm5, %xmm5
-        	pcmpeqd	%xmm5,%xmm5
-
-// CHECK: 	pcmpgtb	3735928559(%ebx,%ecx,8), %mm3
-        	pcmpgtb	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pcmpgtb	69, %mm3
-        	pcmpgtb	0x45,%mm3
-
-// CHECK: 	pcmpgtb	32493, %mm3
-        	pcmpgtb	0x7eed,%mm3
-
-// CHECK: 	pcmpgtb	3133065982, %mm3
-        	pcmpgtb	0xbabecafe,%mm3
-
-// CHECK: 	pcmpgtb	305419896, %mm3
-        	pcmpgtb	0x12345678,%mm3
-
-// CHECK: 	pcmpgtb	%mm3, %mm3
-        	pcmpgtb	%mm3,%mm3
-
-// CHECK: 	pcmpgtb	3735928559(%ebx,%ecx,8), %xmm5
-        	pcmpgtb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pcmpgtb	69, %xmm5
-        	pcmpgtb	0x45,%xmm5
-
-// CHECK: 	pcmpgtb	32493, %xmm5
-        	pcmpgtb	0x7eed,%xmm5
-
-// CHECK: 	pcmpgtb	3133065982, %xmm5
-        	pcmpgtb	0xbabecafe,%xmm5
-
-// CHECK: 	pcmpgtb	305419896, %xmm5
-        	pcmpgtb	0x12345678,%xmm5
-
-// CHECK: 	pcmpgtb	%xmm5, %xmm5
-        	pcmpgtb	%xmm5,%xmm5
-
-// CHECK: 	pcmpgtw	3735928559(%ebx,%ecx,8), %mm3
-        	pcmpgtw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pcmpgtw	69, %mm3
-        	pcmpgtw	0x45,%mm3
-
-// CHECK: 	pcmpgtw	32493, %mm3
-        	pcmpgtw	0x7eed,%mm3
-
-// CHECK: 	pcmpgtw	3133065982, %mm3
-        	pcmpgtw	0xbabecafe,%mm3
-
-// CHECK: 	pcmpgtw	305419896, %mm3
-        	pcmpgtw	0x12345678,%mm3
-
-// CHECK: 	pcmpgtw	%mm3, %mm3
-        	pcmpgtw	%mm3,%mm3
-
-// CHECK: 	pcmpgtw	3735928559(%ebx,%ecx,8), %xmm5
-        	pcmpgtw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pcmpgtw	69, %xmm5
-        	pcmpgtw	0x45,%xmm5
-
-// CHECK: 	pcmpgtw	32493, %xmm5
-        	pcmpgtw	0x7eed,%xmm5
-
-// CHECK: 	pcmpgtw	3133065982, %xmm5
-        	pcmpgtw	0xbabecafe,%xmm5
-
-// CHECK: 	pcmpgtw	305419896, %xmm5
-        	pcmpgtw	0x12345678,%xmm5
-
-// CHECK: 	pcmpgtw	%xmm5, %xmm5
-        	pcmpgtw	%xmm5,%xmm5
-
-// CHECK: 	pcmpgtd	3735928559(%ebx,%ecx,8), %mm3
-        	pcmpgtd	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pcmpgtd	69, %mm3
-        	pcmpgtd	0x45,%mm3
-
-// CHECK: 	pcmpgtd	32493, %mm3
-        	pcmpgtd	0x7eed,%mm3
-
-// CHECK: 	pcmpgtd	3133065982, %mm3
-        	pcmpgtd	0xbabecafe,%mm3
-
-// CHECK: 	pcmpgtd	305419896, %mm3
-        	pcmpgtd	0x12345678,%mm3
-
-// CHECK: 	pcmpgtd	%mm3, %mm3
-        	pcmpgtd	%mm3,%mm3
-
-// CHECK: 	pcmpgtd	3735928559(%ebx,%ecx,8), %xmm5
-        	pcmpgtd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pcmpgtd	69, %xmm5
-        	pcmpgtd	0x45,%xmm5
-
-// CHECK: 	pcmpgtd	32493, %xmm5
-        	pcmpgtd	0x7eed,%xmm5
-
-// CHECK: 	pcmpgtd	3133065982, %xmm5
-        	pcmpgtd	0xbabecafe,%xmm5
-
-// CHECK: 	pcmpgtd	305419896, %xmm5
-        	pcmpgtd	0x12345678,%xmm5
-
-// CHECK: 	pcmpgtd	%xmm5, %xmm5
-        	pcmpgtd	%xmm5,%xmm5
-
-// CHECK: 	pmaddwd	3735928559(%ebx,%ecx,8), %mm3
-        	pmaddwd	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pmaddwd	69, %mm3
-        	pmaddwd	0x45,%mm3
-
-// CHECK: 	pmaddwd	32493, %mm3
-        	pmaddwd	0x7eed,%mm3
-
-// CHECK: 	pmaddwd	3133065982, %mm3
-        	pmaddwd	0xbabecafe,%mm3
-
-// CHECK: 	pmaddwd	305419896, %mm3
-        	pmaddwd	0x12345678,%mm3
-
-// CHECK: 	pmaddwd	%mm3, %mm3
-        	pmaddwd	%mm3,%mm3
-
-// CHECK: 	pmaddwd	3735928559(%ebx,%ecx,8), %xmm5
-        	pmaddwd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmaddwd	69, %xmm5
-        	pmaddwd	0x45,%xmm5
-
-// CHECK: 	pmaddwd	32493, %xmm5
-        	pmaddwd	0x7eed,%xmm5
-
-// CHECK: 	pmaddwd	3133065982, %xmm5
-        	pmaddwd	0xbabecafe,%xmm5
-
-// CHECK: 	pmaddwd	305419896, %xmm5
-        	pmaddwd	0x12345678,%xmm5
-
-// CHECK: 	pmaddwd	%xmm5, %xmm5
-        	pmaddwd	%xmm5,%xmm5
-
-// CHECK: 	pmulhw	3735928559(%ebx,%ecx,8), %mm3
-        	pmulhw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pmulhw	69, %mm3
-        	pmulhw	0x45,%mm3
-
-// CHECK: 	pmulhw	32493, %mm3
-        	pmulhw	0x7eed,%mm3
-
-// CHECK: 	pmulhw	3133065982, %mm3
-        	pmulhw	0xbabecafe,%mm3
-
-// CHECK: 	pmulhw	305419896, %mm3
-        	pmulhw	0x12345678,%mm3
-
-// CHECK: 	pmulhw	%mm3, %mm3
-        	pmulhw	%mm3,%mm3
-
-// CHECK: 	pmulhw	3735928559(%ebx,%ecx,8), %xmm5
-        	pmulhw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmulhw	69, %xmm5
-        	pmulhw	0x45,%xmm5
-
-// CHECK: 	pmulhw	32493, %xmm5
-        	pmulhw	0x7eed,%xmm5
-
-// CHECK: 	pmulhw	3133065982, %xmm5
-        	pmulhw	0xbabecafe,%xmm5
-
-// CHECK: 	pmulhw	305419896, %xmm5
-        	pmulhw	0x12345678,%xmm5
-
-// CHECK: 	pmulhw	%xmm5, %xmm5
-        	pmulhw	%xmm5,%xmm5
-
-// CHECK: 	pmullw	3735928559(%ebx,%ecx,8), %mm3
-        	pmullw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pmullw	69, %mm3
-        	pmullw	0x45,%mm3
-
-// CHECK: 	pmullw	32493, %mm3
-        	pmullw	0x7eed,%mm3
-
-// CHECK: 	pmullw	3133065982, %mm3
-        	pmullw	0xbabecafe,%mm3
-
-// CHECK: 	pmullw	305419896, %mm3
-        	pmullw	0x12345678,%mm3
-
-// CHECK: 	pmullw	%mm3, %mm3
-        	pmullw	%mm3,%mm3
-
-// CHECK: 	pmullw	3735928559(%ebx,%ecx,8), %xmm5
-        	pmullw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmullw	69, %xmm5
-        	pmullw	0x45,%xmm5
-
-// CHECK: 	pmullw	32493, %xmm5
-        	pmullw	0x7eed,%xmm5
-
-// CHECK: 	pmullw	3133065982, %xmm5
-        	pmullw	0xbabecafe,%xmm5
-
-// CHECK: 	pmullw	305419896, %xmm5
-        	pmullw	0x12345678,%xmm5
-
-// CHECK: 	pmullw	%xmm5, %xmm5
-        	pmullw	%xmm5,%xmm5
-
-// CHECK: 	por	3735928559(%ebx,%ecx,8), %mm3
-        	por	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	por	69, %mm3
-        	por	0x45,%mm3
-
-// CHECK: 	por	32493, %mm3
-        	por	0x7eed,%mm3
-
-// CHECK: 	por	3133065982, %mm3
-        	por	0xbabecafe,%mm3
-
-// CHECK: 	por	305419896, %mm3
-        	por	0x12345678,%mm3
-
-// CHECK: 	por	%mm3, %mm3
-        	por	%mm3,%mm3
-
-// CHECK: 	por	3735928559(%ebx,%ecx,8), %xmm5
-        	por	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	por	69, %xmm5
-        	por	0x45,%xmm5
-
-// CHECK: 	por	32493, %xmm5
-        	por	0x7eed,%xmm5
-
-// CHECK: 	por	3133065982, %xmm5
-        	por	0xbabecafe,%xmm5
-
-// CHECK: 	por	305419896, %xmm5
-        	por	0x12345678,%xmm5
-
-// CHECK: 	por	%xmm5, %xmm5
-        	por	%xmm5,%xmm5
-
-// CHECK: 	psllw	3735928559(%ebx,%ecx,8), %mm3
-        	psllw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psllw	69, %mm3
-        	psllw	0x45,%mm3
-
-// CHECK: 	psllw	32493, %mm3
-        	psllw	0x7eed,%mm3
-
-// CHECK: 	psllw	3133065982, %mm3
-        	psllw	0xbabecafe,%mm3
-
-// CHECK: 	psllw	305419896, %mm3
-        	psllw	0x12345678,%mm3
-
-// CHECK: 	psllw	%mm3, %mm3
-        	psllw	%mm3,%mm3
-
-// CHECK: 	psllw	3735928559(%ebx,%ecx,8), %xmm5
-        	psllw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psllw	69, %xmm5
-        	psllw	0x45,%xmm5
-
-// CHECK: 	psllw	32493, %xmm5
-        	psllw	0x7eed,%xmm5
-
-// CHECK: 	psllw	3133065982, %xmm5
-        	psllw	0xbabecafe,%xmm5
-
-// CHECK: 	psllw	305419896, %xmm5
-        	psllw	0x12345678,%xmm5
-
-// CHECK: 	psllw	%xmm5, %xmm5
-        	psllw	%xmm5,%xmm5
-
-// CHECK: 	psllw	$127, %mm3
-        	psllw	$0x7f,%mm3
-
-// CHECK: 	psllw	$127, %xmm5
-        	psllw	$0x7f,%xmm5
-
-// CHECK: 	pslld	3735928559(%ebx,%ecx,8), %mm3
-        	pslld	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pslld	69, %mm3
-        	pslld	0x45,%mm3
-
-// CHECK: 	pslld	32493, %mm3
-        	pslld	0x7eed,%mm3
-
-// CHECK: 	pslld	3133065982, %mm3
-        	pslld	0xbabecafe,%mm3
-
-// CHECK: 	pslld	305419896, %mm3
-        	pslld	0x12345678,%mm3
-
-// CHECK: 	pslld	%mm3, %mm3
-        	pslld	%mm3,%mm3
-
-// CHECK: 	pslld	3735928559(%ebx,%ecx,8), %xmm5
-        	pslld	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pslld	69, %xmm5
-        	pslld	0x45,%xmm5
-
-// CHECK: 	pslld	32493, %xmm5
-        	pslld	0x7eed,%xmm5
-
-// CHECK: 	pslld	3133065982, %xmm5
-        	pslld	0xbabecafe,%xmm5
-
-// CHECK: 	pslld	305419896, %xmm5
-        	pslld	0x12345678,%xmm5
-
-// CHECK: 	pslld	%xmm5, %xmm5
-        	pslld	%xmm5,%xmm5
-
-// CHECK: 	pslld	$127, %mm3
-        	pslld	$0x7f,%mm3
-
-// CHECK: 	pslld	$127, %xmm5
-        	pslld	$0x7f,%xmm5
-
-// CHECK: 	psllq	3735928559(%ebx,%ecx,8), %mm3
-        	psllq	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psllq	69, %mm3
-        	psllq	0x45,%mm3
-
-// CHECK: 	psllq	32493, %mm3
-        	psllq	0x7eed,%mm3
-
-// CHECK: 	psllq	3133065982, %mm3
-        	psllq	0xbabecafe,%mm3
-
-// CHECK: 	psllq	305419896, %mm3
-        	psllq	0x12345678,%mm3
-
-// CHECK: 	psllq	%mm3, %mm3
-        	psllq	%mm3,%mm3
-
-// CHECK: 	psllq	3735928559(%ebx,%ecx,8), %xmm5
-        	psllq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psllq	69, %xmm5
-        	psllq	0x45,%xmm5
-
-// CHECK: 	psllq	32493, %xmm5
-        	psllq	0x7eed,%xmm5
-
-// CHECK: 	psllq	3133065982, %xmm5
-        	psllq	0xbabecafe,%xmm5
-
-// CHECK: 	psllq	305419896, %xmm5
-        	psllq	0x12345678,%xmm5
-
-// CHECK: 	psllq	%xmm5, %xmm5
-        	psllq	%xmm5,%xmm5
-
-// CHECK: 	psllq	$127, %mm3
-        	psllq	$0x7f,%mm3
-
-// CHECK: 	psllq	$127, %xmm5
-        	psllq	$0x7f,%xmm5
-
-// CHECK: 	psraw	3735928559(%ebx,%ecx,8), %mm3
-        	psraw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psraw	69, %mm3
-        	psraw	0x45,%mm3
-
-// CHECK: 	psraw	32493, %mm3
-        	psraw	0x7eed,%mm3
-
-// CHECK: 	psraw	3133065982, %mm3
-        	psraw	0xbabecafe,%mm3
-
-// CHECK: 	psraw	305419896, %mm3
-        	psraw	0x12345678,%mm3
-
-// CHECK: 	psraw	%mm3, %mm3
-        	psraw	%mm3,%mm3
-
-// CHECK: 	psraw	3735928559(%ebx,%ecx,8), %xmm5
-        	psraw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psraw	69, %xmm5
-        	psraw	0x45,%xmm5
-
-// CHECK: 	psraw	32493, %xmm5
-        	psraw	0x7eed,%xmm5
-
-// CHECK: 	psraw	3133065982, %xmm5
-        	psraw	0xbabecafe,%xmm5
-
-// CHECK: 	psraw	305419896, %xmm5
-        	psraw	0x12345678,%xmm5
-
-// CHECK: 	psraw	%xmm5, %xmm5
-        	psraw	%xmm5,%xmm5
-
-// CHECK: 	psraw	$127, %mm3
-        	psraw	$0x7f,%mm3
-
-// CHECK: 	psraw	$127, %xmm5
-        	psraw	$0x7f,%xmm5
-
-// CHECK: 	psrad	3735928559(%ebx,%ecx,8), %mm3
-        	psrad	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psrad	69, %mm3
-        	psrad	0x45,%mm3
-
-// CHECK: 	psrad	32493, %mm3
-        	psrad	0x7eed,%mm3
-
-// CHECK: 	psrad	3133065982, %mm3
-        	psrad	0xbabecafe,%mm3
-
-// CHECK: 	psrad	305419896, %mm3
-        	psrad	0x12345678,%mm3
-
-// CHECK: 	psrad	%mm3, %mm3
-        	psrad	%mm3,%mm3
-
-// CHECK: 	psrad	3735928559(%ebx,%ecx,8), %xmm5
-        	psrad	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psrad	69, %xmm5
-        	psrad	0x45,%xmm5
-
-// CHECK: 	psrad	32493, %xmm5
-        	psrad	0x7eed,%xmm5
-
-// CHECK: 	psrad	3133065982, %xmm5
-        	psrad	0xbabecafe,%xmm5
-
-// CHECK: 	psrad	305419896, %xmm5
-        	psrad	0x12345678,%xmm5
-
-// CHECK: 	psrad	%xmm5, %xmm5
-        	psrad	%xmm5,%xmm5
-
-// CHECK: 	psrad	$127, %mm3
-        	psrad	$0x7f,%mm3
-
-// CHECK: 	psrad	$127, %xmm5
-        	psrad	$0x7f,%xmm5
-
-// CHECK: 	psrlw	3735928559(%ebx,%ecx,8), %mm3
-        	psrlw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psrlw	69, %mm3
-        	psrlw	0x45,%mm3
-
-// CHECK: 	psrlw	32493, %mm3
-        	psrlw	0x7eed,%mm3
-
-// CHECK: 	psrlw	3133065982, %mm3
-        	psrlw	0xbabecafe,%mm3
-
-// CHECK: 	psrlw	305419896, %mm3
-        	psrlw	0x12345678,%mm3
-
-// CHECK: 	psrlw	%mm3, %mm3
-        	psrlw	%mm3,%mm3
-
-// CHECK: 	psrlw	3735928559(%ebx,%ecx,8), %xmm5
-        	psrlw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psrlw	69, %xmm5
-        	psrlw	0x45,%xmm5
-
-// CHECK: 	psrlw	32493, %xmm5
-        	psrlw	0x7eed,%xmm5
-
-// CHECK: 	psrlw	3133065982, %xmm5
-        	psrlw	0xbabecafe,%xmm5
-
-// CHECK: 	psrlw	305419896, %xmm5
-        	psrlw	0x12345678,%xmm5
-
-// CHECK: 	psrlw	%xmm5, %xmm5
-        	psrlw	%xmm5,%xmm5
-
-// CHECK: 	psrlw	$127, %mm3
-        	psrlw	$0x7f,%mm3
-
-// CHECK: 	psrlw	$127, %xmm5
-        	psrlw	$0x7f,%xmm5
-
-// CHECK: 	psrld	3735928559(%ebx,%ecx,8), %mm3
-        	psrld	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psrld	69, %mm3
-        	psrld	0x45,%mm3
-
-// CHECK: 	psrld	32493, %mm3
-        	psrld	0x7eed,%mm3
-
-// CHECK: 	psrld	3133065982, %mm3
-        	psrld	0xbabecafe,%mm3
-
-// CHECK: 	psrld	305419896, %mm3
-        	psrld	0x12345678,%mm3
-
-// CHECK: 	psrld	%mm3, %mm3
-        	psrld	%mm3,%mm3
-
-// CHECK: 	psrld	3735928559(%ebx,%ecx,8), %xmm5
-        	psrld	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psrld	69, %xmm5
-        	psrld	0x45,%xmm5
-
-// CHECK: 	psrld	32493, %xmm5
-        	psrld	0x7eed,%xmm5
-
-// CHECK: 	psrld	3133065982, %xmm5
-        	psrld	0xbabecafe,%xmm5
-
-// CHECK: 	psrld	305419896, %xmm5
-        	psrld	0x12345678,%xmm5
-
-// CHECK: 	psrld	%xmm5, %xmm5
-        	psrld	%xmm5,%xmm5
-
-// CHECK: 	psrld	$127, %mm3
-        	psrld	$0x7f,%mm3
-
-// CHECK: 	psrld	$127, %xmm5
-        	psrld	$0x7f,%xmm5
-
-// CHECK: 	psrlq	3735928559(%ebx,%ecx,8), %mm3
-        	psrlq	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psrlq	69, %mm3
-        	psrlq	0x45,%mm3
-
-// CHECK: 	psrlq	32493, %mm3
-        	psrlq	0x7eed,%mm3
-
-// CHECK: 	psrlq	3133065982, %mm3
-        	psrlq	0xbabecafe,%mm3
-
-// CHECK: 	psrlq	305419896, %mm3
-        	psrlq	0x12345678,%mm3
-
-// CHECK: 	psrlq	%mm3, %mm3
-        	psrlq	%mm3,%mm3
-
-// CHECK: 	psrlq	3735928559(%ebx,%ecx,8), %xmm5
-        	psrlq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psrlq	69, %xmm5
-        	psrlq	0x45,%xmm5
-
-// CHECK: 	psrlq	32493, %xmm5
-        	psrlq	0x7eed,%xmm5
-
-// CHECK: 	psrlq	3133065982, %xmm5
-        	psrlq	0xbabecafe,%xmm5
-
-// CHECK: 	psrlq	305419896, %xmm5
-        	psrlq	0x12345678,%xmm5
-
-// CHECK: 	psrlq	%xmm5, %xmm5
-        	psrlq	%xmm5,%xmm5
-
-// CHECK: 	psrlq	$127, %mm3
-        	psrlq	$0x7f,%mm3
-
-// CHECK: 	psrlq	$127, %xmm5
-        	psrlq	$0x7f,%xmm5
-
-// CHECK: 	psubb	3735928559(%ebx,%ecx,8), %mm3
-        	psubb	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psubb	69, %mm3
-        	psubb	0x45,%mm3
-
-// CHECK: 	psubb	32493, %mm3
-        	psubb	0x7eed,%mm3
-
-// CHECK: 	psubb	3133065982, %mm3
-        	psubb	0xbabecafe,%mm3
-
-// CHECK: 	psubb	305419896, %mm3
-        	psubb	0x12345678,%mm3
-
-// CHECK: 	psubb	%mm3, %mm3
-        	psubb	%mm3,%mm3
-
-// CHECK: 	psubb	3735928559(%ebx,%ecx,8), %xmm5
-        	psubb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psubb	69, %xmm5
-        	psubb	0x45,%xmm5
-
-// CHECK: 	psubb	32493, %xmm5
-        	psubb	0x7eed,%xmm5
-
-// CHECK: 	psubb	3133065982, %xmm5
-        	psubb	0xbabecafe,%xmm5
-
-// CHECK: 	psubb	305419896, %xmm5
-        	psubb	0x12345678,%xmm5
-
-// CHECK: 	psubb	%xmm5, %xmm5
-        	psubb	%xmm5,%xmm5
-
-// CHECK: 	psubw	3735928559(%ebx,%ecx,8), %mm3
-        	psubw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psubw	69, %mm3
-        	psubw	0x45,%mm3
-
-// CHECK: 	psubw	32493, %mm3
-        	psubw	0x7eed,%mm3
-
-// CHECK: 	psubw	3133065982, %mm3
-        	psubw	0xbabecafe,%mm3
-
-// CHECK: 	psubw	305419896, %mm3
-        	psubw	0x12345678,%mm3
-
-// CHECK: 	psubw	%mm3, %mm3
-        	psubw	%mm3,%mm3
-
-// CHECK: 	psubw	3735928559(%ebx,%ecx,8), %xmm5
-        	psubw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psubw	69, %xmm5
-        	psubw	0x45,%xmm5
-
-// CHECK: 	psubw	32493, %xmm5
-        	psubw	0x7eed,%xmm5
-
-// CHECK: 	psubw	3133065982, %xmm5
-        	psubw	0xbabecafe,%xmm5
-
-// CHECK: 	psubw	305419896, %xmm5
-        	psubw	0x12345678,%xmm5
-
-// CHECK: 	psubw	%xmm5, %xmm5
-        	psubw	%xmm5,%xmm5
-
-// CHECK: 	psubd	3735928559(%ebx,%ecx,8), %mm3
-        	psubd	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psubd	69, %mm3
-        	psubd	0x45,%mm3
-
-// CHECK: 	psubd	32493, %mm3
-        	psubd	0x7eed,%mm3
-
-// CHECK: 	psubd	3133065982, %mm3
-        	psubd	0xbabecafe,%mm3
-
-// CHECK: 	psubd	305419896, %mm3
-        	psubd	0x12345678,%mm3
-
-// CHECK: 	psubd	%mm3, %mm3
-        	psubd	%mm3,%mm3
-
-// CHECK: 	psubd	3735928559(%ebx,%ecx,8), %xmm5
-        	psubd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psubd	69, %xmm5
-        	psubd	0x45,%xmm5
-
-// CHECK: 	psubd	32493, %xmm5
-        	psubd	0x7eed,%xmm5
-
-// CHECK: 	psubd	3133065982, %xmm5
-        	psubd	0xbabecafe,%xmm5
-
-// CHECK: 	psubd	305419896, %xmm5
-        	psubd	0x12345678,%xmm5
-
-// CHECK: 	psubd	%xmm5, %xmm5
-        	psubd	%xmm5,%xmm5
-
-// CHECK: 	psubq	3735928559(%ebx,%ecx,8), %mm3
-        	psubq	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psubq	69, %mm3
-        	psubq	0x45,%mm3
-
-// CHECK: 	psubq	32493, %mm3
-        	psubq	0x7eed,%mm3
-
-// CHECK: 	psubq	3133065982, %mm3
-        	psubq	0xbabecafe,%mm3
-
-// CHECK: 	psubq	305419896, %mm3
-        	psubq	0x12345678,%mm3
-
-// CHECK: 	psubq	%mm3, %mm3
-        	psubq	%mm3,%mm3
-
-// CHECK: 	psubq	3735928559(%ebx,%ecx,8), %xmm5
-        	psubq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psubq	69, %xmm5
-        	psubq	0x45,%xmm5
-
-// CHECK: 	psubq	32493, %xmm5
-        	psubq	0x7eed,%xmm5
-
-// CHECK: 	psubq	3133065982, %xmm5
-        	psubq	0xbabecafe,%xmm5
-
-// CHECK: 	psubq	305419896, %xmm5
-        	psubq	0x12345678,%xmm5
-
-// CHECK: 	psubq	%xmm5, %xmm5
-        	psubq	%xmm5,%xmm5
-
-// CHECK: 	psubsb	3735928559(%ebx,%ecx,8), %mm3
-        	psubsb	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psubsb	69, %mm3
-        	psubsb	0x45,%mm3
-
-// CHECK: 	psubsb	32493, %mm3
-        	psubsb	0x7eed,%mm3
-
-// CHECK: 	psubsb	3133065982, %mm3
-        	psubsb	0xbabecafe,%mm3
-
-// CHECK: 	psubsb	305419896, %mm3
-        	psubsb	0x12345678,%mm3
-
-// CHECK: 	psubsb	%mm3, %mm3
-        	psubsb	%mm3,%mm3
-
-// CHECK: 	psubsb	3735928559(%ebx,%ecx,8), %xmm5
-        	psubsb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psubsb	69, %xmm5
-        	psubsb	0x45,%xmm5
-
-// CHECK: 	psubsb	32493, %xmm5
-        	psubsb	0x7eed,%xmm5
-
-// CHECK: 	psubsb	3133065982, %xmm5
-        	psubsb	0xbabecafe,%xmm5
-
-// CHECK: 	psubsb	305419896, %xmm5
-        	psubsb	0x12345678,%xmm5
-
-// CHECK: 	psubsb	%xmm5, %xmm5
-        	psubsb	%xmm5,%xmm5
-
-// CHECK: 	psubsw	3735928559(%ebx,%ecx,8), %mm3
-        	psubsw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psubsw	69, %mm3
-        	psubsw	0x45,%mm3
-
-// CHECK: 	psubsw	32493, %mm3
-        	psubsw	0x7eed,%mm3
-
-// CHECK: 	psubsw	3133065982, %mm3
-        	psubsw	0xbabecafe,%mm3
-
-// CHECK: 	psubsw	305419896, %mm3
-        	psubsw	0x12345678,%mm3
-
-// CHECK: 	psubsw	%mm3, %mm3
-        	psubsw	%mm3,%mm3
-
-// CHECK: 	psubsw	3735928559(%ebx,%ecx,8), %xmm5
-        	psubsw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psubsw	69, %xmm5
-        	psubsw	0x45,%xmm5
-
-// CHECK: 	psubsw	32493, %xmm5
-        	psubsw	0x7eed,%xmm5
-
-// CHECK: 	psubsw	3133065982, %xmm5
-        	psubsw	0xbabecafe,%xmm5
-
-// CHECK: 	psubsw	305419896, %xmm5
-        	psubsw	0x12345678,%xmm5
-
-// CHECK: 	psubsw	%xmm5, %xmm5
-        	psubsw	%xmm5,%xmm5
-
-// CHECK: 	psubusb	3735928559(%ebx,%ecx,8), %mm3
-        	psubusb	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psubusb	69, %mm3
-        	psubusb	0x45,%mm3
-
-// CHECK: 	psubusb	32493, %mm3
-        	psubusb	0x7eed,%mm3
-
-// CHECK: 	psubusb	3133065982, %mm3
-        	psubusb	0xbabecafe,%mm3
-
-// CHECK: 	psubusb	305419896, %mm3
-        	psubusb	0x12345678,%mm3
-
-// CHECK: 	psubusb	%mm3, %mm3
-        	psubusb	%mm3,%mm3
-
-// CHECK: 	psubusb	3735928559(%ebx,%ecx,8), %xmm5
-        	psubusb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psubusb	69, %xmm5
-        	psubusb	0x45,%xmm5
-
-// CHECK: 	psubusb	32493, %xmm5
-        	psubusb	0x7eed,%xmm5
-
-// CHECK: 	psubusb	3133065982, %xmm5
-        	psubusb	0xbabecafe,%xmm5
-
-// CHECK: 	psubusb	305419896, %xmm5
-        	psubusb	0x12345678,%xmm5
-
-// CHECK: 	psubusb	%xmm5, %xmm5
-        	psubusb	%xmm5,%xmm5
-
-// CHECK: 	psubusw	3735928559(%ebx,%ecx,8), %mm3
-        	psubusw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psubusw	69, %mm3
-        	psubusw	0x45,%mm3
-
-// CHECK: 	psubusw	32493, %mm3
-        	psubusw	0x7eed,%mm3
-
-// CHECK: 	psubusw	3133065982, %mm3
-        	psubusw	0xbabecafe,%mm3
-
-// CHECK: 	psubusw	305419896, %mm3
-        	psubusw	0x12345678,%mm3
-
-// CHECK: 	psubusw	%mm3, %mm3
-        	psubusw	%mm3,%mm3
-
-// CHECK: 	psubusw	3735928559(%ebx,%ecx,8), %xmm5
-        	psubusw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psubusw	69, %xmm5
-        	psubusw	0x45,%xmm5
-
-// CHECK: 	psubusw	32493, %xmm5
-        	psubusw	0x7eed,%xmm5
-
-// CHECK: 	psubusw	3133065982, %xmm5
-        	psubusw	0xbabecafe,%xmm5
-
-// CHECK: 	psubusw	305419896, %xmm5
-        	psubusw	0x12345678,%xmm5
-
-// CHECK: 	psubusw	%xmm5, %xmm5
-        	psubusw	%xmm5,%xmm5
-
-// CHECK: 	punpckhbw	3735928559(%ebx,%ecx,8), %mm3
-        	punpckhbw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	punpckhbw	69, %mm3
-        	punpckhbw	0x45,%mm3
-
-// CHECK: 	punpckhbw	32493, %mm3
-        	punpckhbw	0x7eed,%mm3
-
-// CHECK: 	punpckhbw	3133065982, %mm3
-        	punpckhbw	0xbabecafe,%mm3
-
-// CHECK: 	punpckhbw	305419896, %mm3
-        	punpckhbw	0x12345678,%mm3
-
-// CHECK: 	punpckhbw	%mm3, %mm3
-        	punpckhbw	%mm3,%mm3
-
-// CHECK: 	punpckhbw	3735928559(%ebx,%ecx,8), %xmm5
-        	punpckhbw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	punpckhbw	69, %xmm5
-        	punpckhbw	0x45,%xmm5
-
-// CHECK: 	punpckhbw	32493, %xmm5
-        	punpckhbw	0x7eed,%xmm5
-
-// CHECK: 	punpckhbw	3133065982, %xmm5
-        	punpckhbw	0xbabecafe,%xmm5
-
-// CHECK: 	punpckhbw	305419896, %xmm5
-        	punpckhbw	0x12345678,%xmm5
-
-// CHECK: 	punpckhbw	%xmm5, %xmm5
-        	punpckhbw	%xmm5,%xmm5
-
-// CHECK: 	punpckhwd	3735928559(%ebx,%ecx,8), %mm3
-        	punpckhwd	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	punpckhwd	69, %mm3
-        	punpckhwd	0x45,%mm3
-
-// CHECK: 	punpckhwd	32493, %mm3
-        	punpckhwd	0x7eed,%mm3
-
-// CHECK: 	punpckhwd	3133065982, %mm3
-        	punpckhwd	0xbabecafe,%mm3
-
-// CHECK: 	punpckhwd	305419896, %mm3
-        	punpckhwd	0x12345678,%mm3
-
-// CHECK: 	punpckhwd	%mm3, %mm3
-        	punpckhwd	%mm3,%mm3
-
-// CHECK: 	punpckhwd	3735928559(%ebx,%ecx,8), %xmm5
-        	punpckhwd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	punpckhwd	69, %xmm5
-        	punpckhwd	0x45,%xmm5
-
-// CHECK: 	punpckhwd	32493, %xmm5
-        	punpckhwd	0x7eed,%xmm5
-
-// CHECK: 	punpckhwd	3133065982, %xmm5
-        	punpckhwd	0xbabecafe,%xmm5
-
-// CHECK: 	punpckhwd	305419896, %xmm5
-        	punpckhwd	0x12345678,%xmm5
-
-// CHECK: 	punpckhwd	%xmm5, %xmm5
-        	punpckhwd	%xmm5,%xmm5
-
-// CHECK: 	punpckhdq	3735928559(%ebx,%ecx,8), %mm3
-        	punpckhdq	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	punpckhdq	69, %mm3
-        	punpckhdq	0x45,%mm3
-
-// CHECK: 	punpckhdq	32493, %mm3
-        	punpckhdq	0x7eed,%mm3
-
-// CHECK: 	punpckhdq	3133065982, %mm3
-        	punpckhdq	0xbabecafe,%mm3
-
-// CHECK: 	punpckhdq	305419896, %mm3
-        	punpckhdq	0x12345678,%mm3
-
-// CHECK: 	punpckhdq	%mm3, %mm3
-        	punpckhdq	%mm3,%mm3
-
-// CHECK: 	punpckhdq	3735928559(%ebx,%ecx,8), %xmm5
-        	punpckhdq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	punpckhdq	69, %xmm5
-        	punpckhdq	0x45,%xmm5
-
-// CHECK: 	punpckhdq	32493, %xmm5
-        	punpckhdq	0x7eed,%xmm5
-
-// CHECK: 	punpckhdq	3133065982, %xmm5
-        	punpckhdq	0xbabecafe,%xmm5
-
-// CHECK: 	punpckhdq	305419896, %xmm5
-        	punpckhdq	0x12345678,%xmm5
-
-// CHECK: 	punpckhdq	%xmm5, %xmm5
-        	punpckhdq	%xmm5,%xmm5
-
-// CHECK: 	punpcklbw	3735928559(%ebx,%ecx,8), %mm3
-        	punpcklbw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	punpcklbw	69, %mm3
-        	punpcklbw	0x45,%mm3
-
-// CHECK: 	punpcklbw	32493, %mm3
-        	punpcklbw	0x7eed,%mm3
-
-// CHECK: 	punpcklbw	3133065982, %mm3
-        	punpcklbw	0xbabecafe,%mm3
-
-// CHECK: 	punpcklbw	305419896, %mm3
-        	punpcklbw	0x12345678,%mm3
-
-// CHECK: 	punpcklbw	%mm3, %mm3
-        	punpcklbw	%mm3,%mm3
-
-// CHECK: 	punpcklbw	3735928559(%ebx,%ecx,8), %xmm5
-        	punpcklbw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	punpcklbw	69, %xmm5
-        	punpcklbw	0x45,%xmm5
-
-// CHECK: 	punpcklbw	32493, %xmm5
-        	punpcklbw	0x7eed,%xmm5
-
-// CHECK: 	punpcklbw	3133065982, %xmm5
-        	punpcklbw	0xbabecafe,%xmm5
-
-// CHECK: 	punpcklbw	305419896, %xmm5
-        	punpcklbw	0x12345678,%xmm5
-
-// CHECK: 	punpcklbw	%xmm5, %xmm5
-        	punpcklbw	%xmm5,%xmm5
-
-// CHECK: 	punpcklwd	3735928559(%ebx,%ecx,8), %mm3
-        	punpcklwd	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	punpcklwd	69, %mm3
-        	punpcklwd	0x45,%mm3
-
-// CHECK: 	punpcklwd	32493, %mm3
-        	punpcklwd	0x7eed,%mm3
-
-// CHECK: 	punpcklwd	3133065982, %mm3
-        	punpcklwd	0xbabecafe,%mm3
-
-// CHECK: 	punpcklwd	305419896, %mm3
-        	punpcklwd	0x12345678,%mm3
-
-// CHECK: 	punpcklwd	%mm3, %mm3
-        	punpcklwd	%mm3,%mm3
-
-// CHECK: 	punpcklwd	3735928559(%ebx,%ecx,8), %xmm5
-        	punpcklwd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	punpcklwd	69, %xmm5
-        	punpcklwd	0x45,%xmm5
-
-// CHECK: 	punpcklwd	32493, %xmm5
-        	punpcklwd	0x7eed,%xmm5
-
-// CHECK: 	punpcklwd	3133065982, %xmm5
-        	punpcklwd	0xbabecafe,%xmm5
-
-// CHECK: 	punpcklwd	305419896, %xmm5
-        	punpcklwd	0x12345678,%xmm5
-
-// CHECK: 	punpcklwd	%xmm5, %xmm5
-        	punpcklwd	%xmm5,%xmm5
-
-// CHECK: 	punpckldq	3735928559(%ebx,%ecx,8), %mm3
-        	punpckldq	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	punpckldq	69, %mm3
-        	punpckldq	0x45,%mm3
-
-// CHECK: 	punpckldq	32493, %mm3
-        	punpckldq	0x7eed,%mm3
-
-// CHECK: 	punpckldq	3133065982, %mm3
-        	punpckldq	0xbabecafe,%mm3
-
-// CHECK: 	punpckldq	305419896, %mm3
-        	punpckldq	0x12345678,%mm3
-
-// CHECK: 	punpckldq	%mm3, %mm3
-        	punpckldq	%mm3,%mm3
-
-// CHECK: 	punpckldq	3735928559(%ebx,%ecx,8), %xmm5
-        	punpckldq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	punpckldq	69, %xmm5
-        	punpckldq	0x45,%xmm5
-
-// CHECK: 	punpckldq	32493, %xmm5
-        	punpckldq	0x7eed,%xmm5
-
-// CHECK: 	punpckldq	3133065982, %xmm5
-        	punpckldq	0xbabecafe,%xmm5
-
-// CHECK: 	punpckldq	305419896, %xmm5
-        	punpckldq	0x12345678,%xmm5
-
-// CHECK: 	punpckldq	%xmm5, %xmm5
-        	punpckldq	%xmm5,%xmm5
-
-// CHECK: 	pxor	3735928559(%ebx,%ecx,8), %mm3
-        	pxor	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pxor	69, %mm3
-        	pxor	0x45,%mm3
-
-// CHECK: 	pxor	32493, %mm3
-        	pxor	0x7eed,%mm3
-
-// CHECK: 	pxor	3133065982, %mm3
-        	pxor	0xbabecafe,%mm3
-
-// CHECK: 	pxor	305419896, %mm3
-        	pxor	0x12345678,%mm3
-
-// CHECK: 	pxor	%mm3, %mm3
-        	pxor	%mm3,%mm3
-
-// CHECK: 	pxor	3735928559(%ebx,%ecx,8), %xmm5
-        	pxor	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pxor	69, %xmm5
-        	pxor	0x45,%xmm5
-
-// CHECK: 	pxor	32493, %xmm5
-        	pxor	0x7eed,%xmm5
-
-// CHECK: 	pxor	3133065982, %xmm5
-        	pxor	0xbabecafe,%xmm5
-
-// CHECK: 	pxor	305419896, %xmm5
-        	pxor	0x12345678,%xmm5
-
-// CHECK: 	pxor	%xmm5, %xmm5
-        	pxor	%xmm5,%xmm5
-
-// CHECK: 	addps	3735928559(%ebx,%ecx,8), %xmm5
-        	addps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	addps	69, %xmm5
-        	addps	0x45,%xmm5
-
-// CHECK: 	addps	32493, %xmm5
-        	addps	0x7eed,%xmm5
-
-// CHECK: 	addps	3133065982, %xmm5
-        	addps	0xbabecafe,%xmm5
-
-// CHECK: 	addps	305419896, %xmm5
-        	addps	0x12345678,%xmm5
-
-// CHECK: 	addps	%xmm5, %xmm5
-        	addps	%xmm5,%xmm5
-
-// CHECK: 	addss	3735928559(%ebx,%ecx,8), %xmm5
-        	addss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	addss	69, %xmm5
-        	addss	0x45,%xmm5
-
-// CHECK: 	addss	32493, %xmm5
-        	addss	0x7eed,%xmm5
-
-// CHECK: 	addss	3133065982, %xmm5
-        	addss	0xbabecafe,%xmm5
-
-// CHECK: 	addss	305419896, %xmm5
-        	addss	0x12345678,%xmm5
-
-// CHECK: 	addss	%xmm5, %xmm5
-        	addss	%xmm5,%xmm5
-
-// CHECK: 	andnps	3735928559(%ebx,%ecx,8), %xmm5
-        	andnps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	andnps	69, %xmm5
-        	andnps	0x45,%xmm5
-
-// CHECK: 	andnps	32493, %xmm5
-        	andnps	0x7eed,%xmm5
-
-// CHECK: 	andnps	3133065982, %xmm5
-        	andnps	0xbabecafe,%xmm5
-
-// CHECK: 	andnps	305419896, %xmm5
-        	andnps	0x12345678,%xmm5
-
-// CHECK: 	andnps	%xmm5, %xmm5
-        	andnps	%xmm5,%xmm5
-
-// CHECK: 	andps	3735928559(%ebx,%ecx,8), %xmm5
-        	andps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	andps	69, %xmm5
-        	andps	0x45,%xmm5
-
-// CHECK: 	andps	32493, %xmm5
-        	andps	0x7eed,%xmm5
-
-// CHECK: 	andps	3133065982, %xmm5
-        	andps	0xbabecafe,%xmm5
-
-// CHECK: 	andps	305419896, %xmm5
-        	andps	0x12345678,%xmm5
-
-// CHECK: 	andps	%xmm5, %xmm5
-        	andps	%xmm5,%xmm5
-
-// CHECK: 	comiss	3735928559(%ebx,%ecx,8), %xmm5
-        	comiss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	comiss	69, %xmm5
-        	comiss	0x45,%xmm5
-
-// CHECK: 	comiss	32493, %xmm5
-        	comiss	0x7eed,%xmm5
-
-// CHECK: 	comiss	3133065982, %xmm5
-        	comiss	0xbabecafe,%xmm5
-
-// CHECK: 	comiss	305419896, %xmm5
-        	comiss	0x12345678,%xmm5
-
-// CHECK: 	comiss	%xmm5, %xmm5
-        	comiss	%xmm5,%xmm5
-
-// CHECK: 	cvtpi2ps	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtpi2ps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtpi2ps	69, %xmm5
-        	cvtpi2ps	0x45,%xmm5
-
-// CHECK: 	cvtpi2ps	32493, %xmm5
-        	cvtpi2ps	0x7eed,%xmm5
-
-// CHECK: 	cvtpi2ps	3133065982, %xmm5
-        	cvtpi2ps	0xbabecafe,%xmm5
-
-// CHECK: 	cvtpi2ps	305419896, %xmm5
-        	cvtpi2ps	0x12345678,%xmm5
-
-// CHECK: 	cvtpi2ps	%mm3, %xmm5
-        	cvtpi2ps	%mm3,%xmm5
-
-// CHECK: 	cvtps2pi	3735928559(%ebx,%ecx,8), %mm3
-        	cvtps2pi	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	cvtps2pi	69, %mm3
-        	cvtps2pi	0x45,%mm3
-
-// CHECK: 	cvtps2pi	32493, %mm3
-        	cvtps2pi	0x7eed,%mm3
-
-// CHECK: 	cvtps2pi	3133065982, %mm3
-        	cvtps2pi	0xbabecafe,%mm3
-
-// CHECK: 	cvtps2pi	305419896, %mm3
-        	cvtps2pi	0x12345678,%mm3
-
-// CHECK: 	cvtps2pi	%xmm5, %mm3
-        	cvtps2pi	%xmm5,%mm3
-
-// CHECK: 	cvtsi2ssl	%ecx, %xmm5
-        	cvtsi2ssl	%ecx,%xmm5
-
-// CHECK: 	cvtsi2ssl	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtsi2ssl	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtsi2ssl	69, %xmm5
-        	cvtsi2ssl	0x45,%xmm5
-
-// CHECK: 	cvtsi2ssl	32493, %xmm5
-        	cvtsi2ssl	0x7eed,%xmm5
-
-// CHECK: 	cvtsi2ssl	3133065982, %xmm5
-        	cvtsi2ssl	0xbabecafe,%xmm5
-
-// CHECK: 	cvtsi2ssl	305419896, %xmm5
-        	cvtsi2ssl	0x12345678,%xmm5
-
-// CHECK: 	cvttps2pi	3735928559(%ebx,%ecx,8), %mm3
-        	cvttps2pi	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	cvttps2pi	69, %mm3
-        	cvttps2pi	0x45,%mm3
-
-// CHECK: 	cvttps2pi	32493, %mm3
-        	cvttps2pi	0x7eed,%mm3
-
-// CHECK: 	cvttps2pi	3133065982, %mm3
-        	cvttps2pi	0xbabecafe,%mm3
-
-// CHECK: 	cvttps2pi	305419896, %mm3
-        	cvttps2pi	0x12345678,%mm3
-
-// CHECK: 	cvttps2pi	%xmm5, %mm3
-        	cvttps2pi	%xmm5,%mm3
-
-// CHECK: 	cvttss2si	3735928559(%ebx,%ecx,8), %ecx
-        	cvttss2si	0xdeadbeef(%ebx,%ecx,8),%ecx
-
-// CHECK: 	cvttss2si	69, %ecx
-        	cvttss2si	0x45,%ecx
-
-// CHECK: 	cvttss2si	32493, %ecx
-        	cvttss2si	0x7eed,%ecx
-
-// CHECK: 	cvttss2si	3133065982, %ecx
-        	cvttss2si	0xbabecafe,%ecx
-
-// CHECK: 	cvttss2si	305419896, %ecx
-        	cvttss2si	0x12345678,%ecx
-
-// CHECK: 	cvttss2si	%xmm5, %ecx
-        	cvttss2si	%xmm5,%ecx
-
-// CHECK: 	divps	3735928559(%ebx,%ecx,8), %xmm5
-        	divps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	divps	69, %xmm5
-        	divps	0x45,%xmm5
-
-// CHECK: 	divps	32493, %xmm5
-        	divps	0x7eed,%xmm5
-
-// CHECK: 	divps	3133065982, %xmm5
-        	divps	0xbabecafe,%xmm5
-
-// CHECK: 	divps	305419896, %xmm5
-        	divps	0x12345678,%xmm5
-
-// CHECK: 	divps	%xmm5, %xmm5
-        	divps	%xmm5,%xmm5
-
-// CHECK: 	divss	3735928559(%ebx,%ecx,8), %xmm5
-        	divss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	divss	69, %xmm5
-        	divss	0x45,%xmm5
-
-// CHECK: 	divss	32493, %xmm5
-        	divss	0x7eed,%xmm5
-
-// CHECK: 	divss	3133065982, %xmm5
-        	divss	0xbabecafe,%xmm5
-
-// CHECK: 	divss	305419896, %xmm5
-        	divss	0x12345678,%xmm5
-
-// CHECK: 	divss	%xmm5, %xmm5
-        	divss	%xmm5,%xmm5
-
-// CHECK: 	ldmxcsr	3735928559(%ebx,%ecx,8)
-        	ldmxcsr	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	ldmxcsr	32493
-        	ldmxcsr	0x7eed
-
-// CHECK: 	ldmxcsr	3133065982
-        	ldmxcsr	0xbabecafe
-
-// CHECK: 	ldmxcsr	305419896
-        	ldmxcsr	0x12345678
-
-// CHECK: 	maskmovq	%mm3, %mm3
-        	maskmovq	%mm3,%mm3
-
-// CHECK: 	maxps	3735928559(%ebx,%ecx,8), %xmm5
-        	maxps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	maxps	69, %xmm5
-        	maxps	0x45,%xmm5
-
-// CHECK: 	maxps	32493, %xmm5
-        	maxps	0x7eed,%xmm5
-
-// CHECK: 	maxps	3133065982, %xmm5
-        	maxps	0xbabecafe,%xmm5
-
-// CHECK: 	maxps	305419896, %xmm5
-        	maxps	0x12345678,%xmm5
-
-// CHECK: 	maxps	%xmm5, %xmm5
-        	maxps	%xmm5,%xmm5
-
-// CHECK: 	maxss	3735928559(%ebx,%ecx,8), %xmm5
-        	maxss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	maxss	69, %xmm5
-        	maxss	0x45,%xmm5
-
-// CHECK: 	maxss	32493, %xmm5
-        	maxss	0x7eed,%xmm5
-
-// CHECK: 	maxss	3133065982, %xmm5
-        	maxss	0xbabecafe,%xmm5
-
-// CHECK: 	maxss	305419896, %xmm5
-        	maxss	0x12345678,%xmm5
-
-// CHECK: 	maxss	%xmm5, %xmm5
-        	maxss	%xmm5,%xmm5
-
-// CHECK: 	minps	3735928559(%ebx,%ecx,8), %xmm5
-        	minps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	minps	69, %xmm5
-        	minps	0x45,%xmm5
-
-// CHECK: 	minps	32493, %xmm5
-        	minps	0x7eed,%xmm5
-
-// CHECK: 	minps	3133065982, %xmm5
-        	minps	0xbabecafe,%xmm5
-
-// CHECK: 	minps	305419896, %xmm5
-        	minps	0x12345678,%xmm5
-
-// CHECK: 	minps	%xmm5, %xmm5
-        	minps	%xmm5,%xmm5
-
-// CHECK: 	minss	3735928559(%ebx,%ecx,8), %xmm5
-        	minss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	minss	69, %xmm5
-        	minss	0x45,%xmm5
-
-// CHECK: 	minss	32493, %xmm5
-        	minss	0x7eed,%xmm5
-
-// CHECK: 	minss	3133065982, %xmm5
-        	minss	0xbabecafe,%xmm5
-
-// CHECK: 	minss	305419896, %xmm5
-        	minss	0x12345678,%xmm5
-
-// CHECK: 	minss	%xmm5, %xmm5
-        	minss	%xmm5,%xmm5
-
-// CHECK: 	movaps	3735928559(%ebx,%ecx,8), %xmm5
-        	movaps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movaps	69, %xmm5
-        	movaps	0x45,%xmm5
-
-// CHECK: 	movaps	32493, %xmm5
-        	movaps	0x7eed,%xmm5
-
-// CHECK: 	movaps	3133065982, %xmm5
-        	movaps	0xbabecafe,%xmm5
-
-// CHECK: 	movaps	305419896, %xmm5
-        	movaps	0x12345678,%xmm5
-
-// CHECK: 	movaps	%xmm5, %xmm5
-        	movaps	%xmm5,%xmm5
-
-// CHECK: 	movaps	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movaps	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movaps	%xmm5, 69
-        	movaps	%xmm5,0x45
-
-// CHECK: 	movaps	%xmm5, 32493
-        	movaps	%xmm5,0x7eed
-
-// CHECK: 	movaps	%xmm5, 3133065982
-        	movaps	%xmm5,0xbabecafe
-
-// CHECK: 	movaps	%xmm5, 305419896
-        	movaps	%xmm5,0x12345678
-
-// CHECK: 	movaps	%xmm5, %xmm5
-        	movaps	%xmm5,%xmm5
-
-// CHECK: 	movhlps	%xmm5, %xmm5
-        	movhlps	%xmm5,%xmm5
-
-// CHECK: 	movhps	3735928559(%ebx,%ecx,8), %xmm5
-        	movhps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movhps	69, %xmm5
-        	movhps	0x45,%xmm5
-
-// CHECK: 	movhps	32493, %xmm5
-        	movhps	0x7eed,%xmm5
-
-// CHECK: 	movhps	3133065982, %xmm5
-        	movhps	0xbabecafe,%xmm5
-
-// CHECK: 	movhps	305419896, %xmm5
-        	movhps	0x12345678,%xmm5
-
-// CHECK: 	movhps	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movhps	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movhps	%xmm5, 69
-        	movhps	%xmm5,0x45
-
-// CHECK: 	movhps	%xmm5, 32493
-        	movhps	%xmm5,0x7eed
-
-// CHECK: 	movhps	%xmm5, 3133065982
-        	movhps	%xmm5,0xbabecafe
-
-// CHECK: 	movhps	%xmm5, 305419896
-        	movhps	%xmm5,0x12345678
-
-// CHECK: 	movlhps	%xmm5, %xmm5
-        	movlhps	%xmm5,%xmm5
-
-// CHECK: 	movlps	3735928559(%ebx,%ecx,8), %xmm5
-        	movlps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movlps	69, %xmm5
-        	movlps	0x45,%xmm5
-
-// CHECK: 	movlps	32493, %xmm5
-        	movlps	0x7eed,%xmm5
-
-// CHECK: 	movlps	3133065982, %xmm5
-        	movlps	0xbabecafe,%xmm5
-
-// CHECK: 	movlps	305419896, %xmm5
-        	movlps	0x12345678,%xmm5
-
-// CHECK: 	movlps	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movlps	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movlps	%xmm5, 69
-        	movlps	%xmm5,0x45
-
-// CHECK: 	movlps	%xmm5, 32493
-        	movlps	%xmm5,0x7eed
-
-// CHECK: 	movlps	%xmm5, 3133065982
-        	movlps	%xmm5,0xbabecafe
-
-// CHECK: 	movlps	%xmm5, 305419896
-        	movlps	%xmm5,0x12345678
-
-// CHECK: 	movmskps	%xmm5, %ecx
-        	movmskps	%xmm5,%ecx
-
-// CHECK: 	movntps	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movntps	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movntps	%xmm5, 69
-        	movntps	%xmm5,0x45
-
-// CHECK: 	movntps	%xmm5, 32493
-        	movntps	%xmm5,0x7eed
-
-// CHECK: 	movntps	%xmm5, 3133065982
-        	movntps	%xmm5,0xbabecafe
-
-// CHECK: 	movntps	%xmm5, 305419896
-        	movntps	%xmm5,0x12345678
-
-// CHECK: 	movntq	%mm3, 3735928559(%ebx,%ecx,8)
-        	movntq	%mm3,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movntq	%mm3, 69
-        	movntq	%mm3,0x45
-
-// CHECK: 	movntq	%mm3, 32493
-        	movntq	%mm3,0x7eed
-
-// CHECK: 	movntq	%mm3, 3133065982
-        	movntq	%mm3,0xbabecafe
-
-// CHECK: 	movntq	%mm3, 305419896
-        	movntq	%mm3,0x12345678
-
-// CHECK: 	movntdq	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movntdq	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movntdq	%xmm5, 69
-        	movntdq	%xmm5,0x45
-
-// CHECK: 	movntdq	%xmm5, 32493
-        	movntdq	%xmm5,0x7eed
-
-// CHECK: 	movntdq	%xmm5, 3133065982
-        	movntdq	%xmm5,0xbabecafe
-
-// CHECK: 	movntdq	%xmm5, 305419896
-        	movntdq	%xmm5,0x12345678
-
-// CHECK: 	movss	3735928559(%ebx,%ecx,8), %xmm5
-        	movss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movss	69, %xmm5
-        	movss	0x45,%xmm5
-
-// CHECK: 	movss	32493, %xmm5
-        	movss	0x7eed,%xmm5
-
-// CHECK: 	movss	3133065982, %xmm5
-        	movss	0xbabecafe,%xmm5
-
-// CHECK: 	movss	305419896, %xmm5
-        	movss	0x12345678,%xmm5
-
-// CHECK: 	movss	%xmm5, %xmm5
-        	movss	%xmm5,%xmm5
-
-// CHECK: 	movss	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movss	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movss	%xmm5, 69
-        	movss	%xmm5,0x45
-
-// CHECK: 	movss	%xmm5, 32493
-        	movss	%xmm5,0x7eed
-
-// CHECK: 	movss	%xmm5, 3133065982
-        	movss	%xmm5,0xbabecafe
-
-// CHECK: 	movss	%xmm5, 305419896
-        	movss	%xmm5,0x12345678
-
-// CHECK: 	movss	%xmm5, %xmm5
-        	movss	%xmm5,%xmm5
-
-// CHECK: 	movups	3735928559(%ebx,%ecx,8), %xmm5
-        	movups	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movups	69, %xmm5
-        	movups	0x45,%xmm5
-
-// CHECK: 	movups	32493, %xmm5
-        	movups	0x7eed,%xmm5
-
-// CHECK: 	movups	3133065982, %xmm5
-        	movups	0xbabecafe,%xmm5
-
-// CHECK: 	movups	305419896, %xmm5
-        	movups	0x12345678,%xmm5
-
-// CHECK: 	movups	%xmm5, %xmm5
-        	movups	%xmm5,%xmm5
-
-// CHECK: 	movups	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movups	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movups	%xmm5, 69
-        	movups	%xmm5,0x45
-
-// CHECK: 	movups	%xmm5, 32493
-        	movups	%xmm5,0x7eed
-
-// CHECK: 	movups	%xmm5, 3133065982
-        	movups	%xmm5,0xbabecafe
-
-// CHECK: 	movups	%xmm5, 305419896
-        	movups	%xmm5,0x12345678
-
-// CHECK: 	movups	%xmm5, %xmm5
-        	movups	%xmm5,%xmm5
-
-// CHECK: 	mulps	3735928559(%ebx,%ecx,8), %xmm5
-        	mulps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	mulps	69, %xmm5
-        	mulps	0x45,%xmm5
-
-// CHECK: 	mulps	32493, %xmm5
-        	mulps	0x7eed,%xmm5
-
-// CHECK: 	mulps	3133065982, %xmm5
-        	mulps	0xbabecafe,%xmm5
-
-// CHECK: 	mulps	305419896, %xmm5
-        	mulps	0x12345678,%xmm5
-
-// CHECK: 	mulps	%xmm5, %xmm5
-        	mulps	%xmm5,%xmm5
-
-// CHECK: 	mulss	3735928559(%ebx,%ecx,8), %xmm5
-        	mulss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	mulss	69, %xmm5
-        	mulss	0x45,%xmm5
-
-// CHECK: 	mulss	32493, %xmm5
-        	mulss	0x7eed,%xmm5
-
-// CHECK: 	mulss	3133065982, %xmm5
-        	mulss	0xbabecafe,%xmm5
-
-// CHECK: 	mulss	305419896, %xmm5
-        	mulss	0x12345678,%xmm5
-
-// CHECK: 	mulss	%xmm5, %xmm5
-        	mulss	%xmm5,%xmm5
-
-// CHECK: 	orps	3735928559(%ebx,%ecx,8), %xmm5
-        	orps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	orps	69, %xmm5
-        	orps	0x45,%xmm5
-
-// CHECK: 	orps	32493, %xmm5
-        	orps	0x7eed,%xmm5
-
-// CHECK: 	orps	3133065982, %xmm5
-        	orps	0xbabecafe,%xmm5
-
-// CHECK: 	orps	305419896, %xmm5
-        	orps	0x12345678,%xmm5
-
-// CHECK: 	orps	%xmm5, %xmm5
-        	orps	%xmm5,%xmm5
-
-// CHECK: 	pavgb	3735928559(%ebx,%ecx,8), %mm3
-        	pavgb	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pavgb	69, %mm3
-        	pavgb	0x45,%mm3
-
-// CHECK: 	pavgb	32493, %mm3
-        	pavgb	0x7eed,%mm3
-
-// CHECK: 	pavgb	3133065982, %mm3
-        	pavgb	0xbabecafe,%mm3
-
-// CHECK: 	pavgb	305419896, %mm3
-        	pavgb	0x12345678,%mm3
-
-// CHECK: 	pavgb	%mm3, %mm3
-        	pavgb	%mm3,%mm3
-
-// CHECK: 	pavgb	3735928559(%ebx,%ecx,8), %xmm5
-        	pavgb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pavgb	69, %xmm5
-        	pavgb	0x45,%xmm5
-
-// CHECK: 	pavgb	32493, %xmm5
-        	pavgb	0x7eed,%xmm5
-
-// CHECK: 	pavgb	3133065982, %xmm5
-        	pavgb	0xbabecafe,%xmm5
-
-// CHECK: 	pavgb	305419896, %xmm5
-        	pavgb	0x12345678,%xmm5
-
-// CHECK: 	pavgb	%xmm5, %xmm5
-        	pavgb	%xmm5,%xmm5
-
-// CHECK: 	pavgw	3735928559(%ebx,%ecx,8), %mm3
-        	pavgw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pavgw	69, %mm3
-        	pavgw	0x45,%mm3
-
-// CHECK: 	pavgw	32493, %mm3
-        	pavgw	0x7eed,%mm3
-
-// CHECK: 	pavgw	3133065982, %mm3
-        	pavgw	0xbabecafe,%mm3
-
-// CHECK: 	pavgw	305419896, %mm3
-        	pavgw	0x12345678,%mm3
-
-// CHECK: 	pavgw	%mm3, %mm3
-        	pavgw	%mm3,%mm3
-
-// CHECK: 	pavgw	3735928559(%ebx,%ecx,8), %xmm5
-        	pavgw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pavgw	69, %xmm5
-        	pavgw	0x45,%xmm5
-
-// CHECK: 	pavgw	32493, %xmm5
-        	pavgw	0x7eed,%xmm5
-
-// CHECK: 	pavgw	3133065982, %xmm5
-        	pavgw	0xbabecafe,%xmm5
-
-// CHECK: 	pavgw	305419896, %xmm5
-        	pavgw	0x12345678,%xmm5
-
-// CHECK: 	pavgw	%xmm5, %xmm5
-        	pavgw	%xmm5,%xmm5
-
-// CHECK: 	pmaxsw	3735928559(%ebx,%ecx,8), %mm3
-        	pmaxsw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pmaxsw	69, %mm3
-        	pmaxsw	0x45,%mm3
-
-// CHECK: 	pmaxsw	32493, %mm3
-        	pmaxsw	0x7eed,%mm3
-
-// CHECK: 	pmaxsw	3133065982, %mm3
-        	pmaxsw	0xbabecafe,%mm3
-
-// CHECK: 	pmaxsw	305419896, %mm3
-        	pmaxsw	0x12345678,%mm3
-
-// CHECK: 	pmaxsw	%mm3, %mm3
-        	pmaxsw	%mm3,%mm3
-
-// CHECK: 	pmaxsw	3735928559(%ebx,%ecx,8), %xmm5
-        	pmaxsw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmaxsw	69, %xmm5
-        	pmaxsw	0x45,%xmm5
-
-// CHECK: 	pmaxsw	32493, %xmm5
-        	pmaxsw	0x7eed,%xmm5
-
-// CHECK: 	pmaxsw	3133065982, %xmm5
-        	pmaxsw	0xbabecafe,%xmm5
-
-// CHECK: 	pmaxsw	305419896, %xmm5
-        	pmaxsw	0x12345678,%xmm5
-
-// CHECK: 	pmaxsw	%xmm5, %xmm5
-        	pmaxsw	%xmm5,%xmm5
-
-// CHECK: 	pmaxub	3735928559(%ebx,%ecx,8), %mm3
-        	pmaxub	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pmaxub	69, %mm3
-        	pmaxub	0x45,%mm3
-
-// CHECK: 	pmaxub	32493, %mm3
-        	pmaxub	0x7eed,%mm3
-
-// CHECK: 	pmaxub	3133065982, %mm3
-        	pmaxub	0xbabecafe,%mm3
-
-// CHECK: 	pmaxub	305419896, %mm3
-        	pmaxub	0x12345678,%mm3
-
-// CHECK: 	pmaxub	%mm3, %mm3
-        	pmaxub	%mm3,%mm3
-
-// CHECK: 	pmaxub	3735928559(%ebx,%ecx,8), %xmm5
-        	pmaxub	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmaxub	69, %xmm5
-        	pmaxub	0x45,%xmm5
-
-// CHECK: 	pmaxub	32493, %xmm5
-        	pmaxub	0x7eed,%xmm5
-
-// CHECK: 	pmaxub	3133065982, %xmm5
-        	pmaxub	0xbabecafe,%xmm5
-
-// CHECK: 	pmaxub	305419896, %xmm5
-        	pmaxub	0x12345678,%xmm5
-
-// CHECK: 	pmaxub	%xmm5, %xmm5
-        	pmaxub	%xmm5,%xmm5
-
-// CHECK: 	pminsw	3735928559(%ebx,%ecx,8), %mm3
-        	pminsw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pminsw	69, %mm3
-        	pminsw	0x45,%mm3
-
-// CHECK: 	pminsw	32493, %mm3
-        	pminsw	0x7eed,%mm3
-
-// CHECK: 	pminsw	3133065982, %mm3
-        	pminsw	0xbabecafe,%mm3
-
-// CHECK: 	pminsw	305419896, %mm3
-        	pminsw	0x12345678,%mm3
-
-// CHECK: 	pminsw	%mm3, %mm3
-        	pminsw	%mm3,%mm3
-
-// CHECK: 	pminsw	3735928559(%ebx,%ecx,8), %xmm5
-        	pminsw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pminsw	69, %xmm5
-        	pminsw	0x45,%xmm5
-
-// CHECK: 	pminsw	32493, %xmm5
-        	pminsw	0x7eed,%xmm5
-
-// CHECK: 	pminsw	3133065982, %xmm5
-        	pminsw	0xbabecafe,%xmm5
-
-// CHECK: 	pminsw	305419896, %xmm5
-        	pminsw	0x12345678,%xmm5
-
-// CHECK: 	pminsw	%xmm5, %xmm5
-        	pminsw	%xmm5,%xmm5
-
-// CHECK: 	pminub	3735928559(%ebx,%ecx,8), %mm3
-        	pminub	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pminub	69, %mm3
-        	pminub	0x45,%mm3
-
-// CHECK: 	pminub	32493, %mm3
-        	pminub	0x7eed,%mm3
-
-// CHECK: 	pminub	3133065982, %mm3
-        	pminub	0xbabecafe,%mm3
-
-// CHECK: 	pminub	305419896, %mm3
-        	pminub	0x12345678,%mm3
-
-// CHECK: 	pminub	%mm3, %mm3
-        	pminub	%mm3,%mm3
-
-// CHECK: 	pminub	3735928559(%ebx,%ecx,8), %xmm5
-        	pminub	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pminub	69, %xmm5
-        	pminub	0x45,%xmm5
-
-// CHECK: 	pminub	32493, %xmm5
-        	pminub	0x7eed,%xmm5
-
-// CHECK: 	pminub	3133065982, %xmm5
-        	pminub	0xbabecafe,%xmm5
-
-// CHECK: 	pminub	305419896, %xmm5
-        	pminub	0x12345678,%xmm5
-
-// CHECK: 	pminub	%xmm5, %xmm5
-        	pminub	%xmm5,%xmm5
-
-// CHECK: 	pmovmskb	%mm3, %ecx
-        	pmovmskb	%mm3,%ecx
-
-// CHECK: 	pmovmskb	%xmm5, %ecx
-        	pmovmskb	%xmm5,%ecx
-
-// CHECK: 	pmulhuw	3735928559(%ebx,%ecx,8), %mm3
-        	pmulhuw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pmulhuw	69, %mm3
-        	pmulhuw	0x45,%mm3
-
-// CHECK: 	pmulhuw	32493, %mm3
-        	pmulhuw	0x7eed,%mm3
-
-// CHECK: 	pmulhuw	3133065982, %mm3
-        	pmulhuw	0xbabecafe,%mm3
-
-// CHECK: 	pmulhuw	305419896, %mm3
-        	pmulhuw	0x12345678,%mm3
-
-// CHECK: 	pmulhuw	%mm3, %mm3
-        	pmulhuw	%mm3,%mm3
-
-// CHECK: 	pmulhuw	3735928559(%ebx,%ecx,8), %xmm5
-        	pmulhuw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmulhuw	69, %xmm5
-        	pmulhuw	0x45,%xmm5
-
-// CHECK: 	pmulhuw	32493, %xmm5
-        	pmulhuw	0x7eed,%xmm5
-
-// CHECK: 	pmulhuw	3133065982, %xmm5
-        	pmulhuw	0xbabecafe,%xmm5
-
-// CHECK: 	pmulhuw	305419896, %xmm5
-        	pmulhuw	0x12345678,%xmm5
-
-// CHECK: 	pmulhuw	%xmm5, %xmm5
-        	pmulhuw	%xmm5,%xmm5
-
-// CHECK: 	prefetchnta	3735928559(%ebx,%ecx,8)
-        	prefetchnta	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	prefetchnta	32493
-        	prefetchnta	0x7eed
-
-// CHECK: 	prefetchnta	3133065982
-        	prefetchnta	0xbabecafe
-
-// CHECK: 	prefetchnta	305419896
-        	prefetchnta	0x12345678
-
-// CHECK: 	prefetcht0	3735928559(%ebx,%ecx,8)
-        	prefetcht0	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	prefetcht0	32493
-        	prefetcht0	0x7eed
-
-// CHECK: 	prefetcht0	3133065982
-        	prefetcht0	0xbabecafe
-
-// CHECK: 	prefetcht0	305419896
-        	prefetcht0	0x12345678
-
-// CHECK: 	prefetcht1	3735928559(%ebx,%ecx,8)
-        	prefetcht1	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	prefetcht1	32493
-        	prefetcht1	0x7eed
-
-// CHECK: 	prefetcht1	3133065982
-        	prefetcht1	0xbabecafe
-
-// CHECK: 	prefetcht1	305419896
-        	prefetcht1	0x12345678
-
-// CHECK: 	prefetcht2	3735928559(%ebx,%ecx,8)
-        	prefetcht2	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	prefetcht2	32493
-        	prefetcht2	0x7eed
-
-// CHECK: 	prefetcht2	3133065982
-        	prefetcht2	0xbabecafe
-
-// CHECK: 	prefetcht2	305419896
-        	prefetcht2	0x12345678
-
-// CHECK: 	psadbw	3735928559(%ebx,%ecx,8), %mm3
-        	psadbw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psadbw	69, %mm3
-        	psadbw	0x45,%mm3
-
-// CHECK: 	psadbw	32493, %mm3
-        	psadbw	0x7eed,%mm3
-
-// CHECK: 	psadbw	3133065982, %mm3
-        	psadbw	0xbabecafe,%mm3
-
-// CHECK: 	psadbw	305419896, %mm3
-        	psadbw	0x12345678,%mm3
-
-// CHECK: 	psadbw	%mm3, %mm3
-        	psadbw	%mm3,%mm3
-
-// CHECK: 	psadbw	3735928559(%ebx,%ecx,8), %xmm5
-        	psadbw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psadbw	69, %xmm5
-        	psadbw	0x45,%xmm5
-
-// CHECK: 	psadbw	32493, %xmm5
-        	psadbw	0x7eed,%xmm5
-
-// CHECK: 	psadbw	3133065982, %xmm5
-        	psadbw	0xbabecafe,%xmm5
-
-// CHECK: 	psadbw	305419896, %xmm5
-        	psadbw	0x12345678,%xmm5
-
-// CHECK: 	psadbw	%xmm5, %xmm5
-        	psadbw	%xmm5,%xmm5
-
-// CHECK: 	rcpps	3735928559(%ebx,%ecx,8), %xmm5
-        	rcpps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	rcpps	69, %xmm5
-        	rcpps	0x45,%xmm5
-
-// CHECK: 	rcpps	32493, %xmm5
-        	rcpps	0x7eed,%xmm5
-
-// CHECK: 	rcpps	3133065982, %xmm5
-        	rcpps	0xbabecafe,%xmm5
-
-// CHECK: 	rcpps	305419896, %xmm5
-        	rcpps	0x12345678,%xmm5
-
-// CHECK: 	rcpps	%xmm5, %xmm5
-        	rcpps	%xmm5,%xmm5
-
-// CHECK: 	rcpss	3735928559(%ebx,%ecx,8), %xmm5
-        	rcpss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	rcpss	69, %xmm5
-        	rcpss	0x45,%xmm5
-
-// CHECK: 	rcpss	32493, %xmm5
-        	rcpss	0x7eed,%xmm5
-
-// CHECK: 	rcpss	3133065982, %xmm5
-        	rcpss	0xbabecafe,%xmm5
-
-// CHECK: 	rcpss	305419896, %xmm5
-        	rcpss	0x12345678,%xmm5
-
-// CHECK: 	rcpss	%xmm5, %xmm5
-        	rcpss	%xmm5,%xmm5
-
-// CHECK: 	rsqrtps	3735928559(%ebx,%ecx,8), %xmm5
-        	rsqrtps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	rsqrtps	69, %xmm5
-        	rsqrtps	0x45,%xmm5
-
-// CHECK: 	rsqrtps	32493, %xmm5
-        	rsqrtps	0x7eed,%xmm5
-
-// CHECK: 	rsqrtps	3133065982, %xmm5
-        	rsqrtps	0xbabecafe,%xmm5
-
-// CHECK: 	rsqrtps	305419896, %xmm5
-        	rsqrtps	0x12345678,%xmm5
-
-// CHECK: 	rsqrtps	%xmm5, %xmm5
-        	rsqrtps	%xmm5,%xmm5
-
-// CHECK: 	rsqrtss	3735928559(%ebx,%ecx,8), %xmm5
-        	rsqrtss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	rsqrtss	69, %xmm5
-        	rsqrtss	0x45,%xmm5
-
-// CHECK: 	rsqrtss	32493, %xmm5
-        	rsqrtss	0x7eed,%xmm5
-
-// CHECK: 	rsqrtss	3133065982, %xmm5
-        	rsqrtss	0xbabecafe,%xmm5
-
-// CHECK: 	rsqrtss	305419896, %xmm5
-        	rsqrtss	0x12345678,%xmm5
-
-// CHECK: 	rsqrtss	%xmm5, %xmm5
-        	rsqrtss	%xmm5,%xmm5
-
-// CHECK: 	sfence
-        	sfence
-
-// CHECK: 	sqrtps	3735928559(%ebx,%ecx,8), %xmm5
-        	sqrtps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	sqrtps	69, %xmm5
-        	sqrtps	0x45,%xmm5
-
-// CHECK: 	sqrtps	32493, %xmm5
-        	sqrtps	0x7eed,%xmm5
-
-// CHECK: 	sqrtps	3133065982, %xmm5
-        	sqrtps	0xbabecafe,%xmm5
-
-// CHECK: 	sqrtps	305419896, %xmm5
-        	sqrtps	0x12345678,%xmm5
-
-// CHECK: 	sqrtps	%xmm5, %xmm5
-        	sqrtps	%xmm5,%xmm5
-
-// CHECK: 	sqrtss	3735928559(%ebx,%ecx,8), %xmm5
-        	sqrtss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	sqrtss	69, %xmm5
-        	sqrtss	0x45,%xmm5
-
-// CHECK: 	sqrtss	32493, %xmm5
-        	sqrtss	0x7eed,%xmm5
-
-// CHECK: 	sqrtss	3133065982, %xmm5
-        	sqrtss	0xbabecafe,%xmm5
-
-// CHECK: 	sqrtss	305419896, %xmm5
-        	sqrtss	0x12345678,%xmm5
-
-// CHECK: 	sqrtss	%xmm5, %xmm5
-        	sqrtss	%xmm5,%xmm5
-
-// CHECK: 	stmxcsr	3735928559(%ebx,%ecx,8)
-        	stmxcsr	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	stmxcsr	32493
-        	stmxcsr	0x7eed
-
-// CHECK: 	stmxcsr	3133065982
-        	stmxcsr	0xbabecafe
-
-// CHECK: 	stmxcsr	305419896
-        	stmxcsr	0x12345678
-
-// CHECK: 	subps	3735928559(%ebx,%ecx,8), %xmm5
-        	subps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	subps	69, %xmm5
-        	subps	0x45,%xmm5
-
-// CHECK: 	subps	32493, %xmm5
-        	subps	0x7eed,%xmm5
-
-// CHECK: 	subps	3133065982, %xmm5
-        	subps	0xbabecafe,%xmm5
-
-// CHECK: 	subps	305419896, %xmm5
-        	subps	0x12345678,%xmm5
-
-// CHECK: 	subps	%xmm5, %xmm5
-        	subps	%xmm5,%xmm5
-
-// CHECK: 	subss	3735928559(%ebx,%ecx,8), %xmm5
-        	subss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	subss	69, %xmm5
-        	subss	0x45,%xmm5
-
-// CHECK: 	subss	32493, %xmm5
-        	subss	0x7eed,%xmm5
-
-// CHECK: 	subss	3133065982, %xmm5
-        	subss	0xbabecafe,%xmm5
-
-// CHECK: 	subss	305419896, %xmm5
-        	subss	0x12345678,%xmm5
-
-// CHECK: 	subss	%xmm5, %xmm5
-        	subss	%xmm5,%xmm5
-
-// CHECK: 	ucomiss	3735928559(%ebx,%ecx,8), %xmm5
-        	ucomiss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	ucomiss	69, %xmm5
-        	ucomiss	0x45,%xmm5
-
-// CHECK: 	ucomiss	32493, %xmm5
-        	ucomiss	0x7eed,%xmm5
-
-// CHECK: 	ucomiss	3133065982, %xmm5
-        	ucomiss	0xbabecafe,%xmm5
-
-// CHECK: 	ucomiss	305419896, %xmm5
-        	ucomiss	0x12345678,%xmm5
-
-// CHECK: 	ucomiss	%xmm5, %xmm5
-        	ucomiss	%xmm5,%xmm5
-
-// CHECK: 	unpckhps	3735928559(%ebx,%ecx,8), %xmm5
-        	unpckhps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	unpckhps	69, %xmm5
-        	unpckhps	0x45,%xmm5
-
-// CHECK: 	unpckhps	32493, %xmm5
-        	unpckhps	0x7eed,%xmm5
-
-// CHECK: 	unpckhps	3133065982, %xmm5
-        	unpckhps	0xbabecafe,%xmm5
-
-// CHECK: 	unpckhps	305419896, %xmm5
-        	unpckhps	0x12345678,%xmm5
-
-// CHECK: 	unpckhps	%xmm5, %xmm5
-        	unpckhps	%xmm5,%xmm5
-
-// CHECK: 	unpcklps	3735928559(%ebx,%ecx,8), %xmm5
-        	unpcklps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	unpcklps	69, %xmm5
-        	unpcklps	0x45,%xmm5
-
-// CHECK: 	unpcklps	32493, %xmm5
-        	unpcklps	0x7eed,%xmm5
-
-// CHECK: 	unpcklps	3133065982, %xmm5
-        	unpcklps	0xbabecafe,%xmm5
-
-// CHECK: 	unpcklps	305419896, %xmm5
-        	unpcklps	0x12345678,%xmm5
-
-// CHECK: 	unpcklps	%xmm5, %xmm5
-        	unpcklps	%xmm5,%xmm5
-
-// CHECK: 	xorps	3735928559(%ebx,%ecx,8), %xmm5
-        	xorps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	xorps	69, %xmm5
-        	xorps	0x45,%xmm5
-
-// CHECK: 	xorps	32493, %xmm5
-        	xorps	0x7eed,%xmm5
-
-// CHECK: 	xorps	3133065982, %xmm5
-        	xorps	0xbabecafe,%xmm5
-
-// CHECK: 	xorps	305419896, %xmm5
-        	xorps	0x12345678,%xmm5
-
-// CHECK: 	xorps	%xmm5, %xmm5
-        	xorps	%xmm5,%xmm5
-
-// CHECK: 	addpd	3735928559(%ebx,%ecx,8), %xmm5
-        	addpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	addpd	69, %xmm5
-        	addpd	0x45,%xmm5
-
-// CHECK: 	addpd	32493, %xmm5
-        	addpd	0x7eed,%xmm5
-
-// CHECK: 	addpd	3133065982, %xmm5
-        	addpd	0xbabecafe,%xmm5
-
-// CHECK: 	addpd	305419896, %xmm5
-        	addpd	0x12345678,%xmm5
-
-// CHECK: 	addpd	%xmm5, %xmm5
-        	addpd	%xmm5,%xmm5
-
-// CHECK: 	addsd	3735928559(%ebx,%ecx,8), %xmm5
-        	addsd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	addsd	69, %xmm5
-        	addsd	0x45,%xmm5
-
-// CHECK: 	addsd	32493, %xmm5
-        	addsd	0x7eed,%xmm5
-
-// CHECK: 	addsd	3133065982, %xmm5
-        	addsd	0xbabecafe,%xmm5
-
-// CHECK: 	addsd	305419896, %xmm5
-        	addsd	0x12345678,%xmm5
-
-// CHECK: 	addsd	%xmm5, %xmm5
-        	addsd	%xmm5,%xmm5
-
-// CHECK: 	andnpd	3735928559(%ebx,%ecx,8), %xmm5
-        	andnpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	andnpd	69, %xmm5
-        	andnpd	0x45,%xmm5
-
-// CHECK: 	andnpd	32493, %xmm5
-        	andnpd	0x7eed,%xmm5
-
-// CHECK: 	andnpd	3133065982, %xmm5
-        	andnpd	0xbabecafe,%xmm5
-
-// CHECK: 	andnpd	305419896, %xmm5
-        	andnpd	0x12345678,%xmm5
-
-// CHECK: 	andnpd	%xmm5, %xmm5
-        	andnpd	%xmm5,%xmm5
-
-// CHECK: 	andpd	3735928559(%ebx,%ecx,8), %xmm5
-        	andpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	andpd	69, %xmm5
-        	andpd	0x45,%xmm5
-
-// CHECK: 	andpd	32493, %xmm5
-        	andpd	0x7eed,%xmm5
-
-// CHECK: 	andpd	3133065982, %xmm5
-        	andpd	0xbabecafe,%xmm5
-
-// CHECK: 	andpd	305419896, %xmm5
-        	andpd	0x12345678,%xmm5
-
-// CHECK: 	andpd	%xmm5, %xmm5
-        	andpd	%xmm5,%xmm5
-
-// CHECK: 	comisd	3735928559(%ebx,%ecx,8), %xmm5
-        	comisd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	comisd	69, %xmm5
-        	comisd	0x45,%xmm5
-
-// CHECK: 	comisd	32493, %xmm5
-        	comisd	0x7eed,%xmm5
-
-// CHECK: 	comisd	3133065982, %xmm5
-        	comisd	0xbabecafe,%xmm5
-
-// CHECK: 	comisd	305419896, %xmm5
-        	comisd	0x12345678,%xmm5
-
-// CHECK: 	comisd	%xmm5, %xmm5
-        	comisd	%xmm5,%xmm5
-
-// CHECK: 	cvtpi2pd	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtpi2pd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtpi2pd	69, %xmm5
-        	cvtpi2pd	0x45,%xmm5
-
-// CHECK: 	cvtpi2pd	32493, %xmm5
-        	cvtpi2pd	0x7eed,%xmm5
-
-// CHECK: 	cvtpi2pd	3133065982, %xmm5
-        	cvtpi2pd	0xbabecafe,%xmm5
-
-// CHECK: 	cvtpi2pd	305419896, %xmm5
-        	cvtpi2pd	0x12345678,%xmm5
-
-// CHECK: 	cvtpi2pd	%mm3, %xmm5
-        	cvtpi2pd	%mm3,%xmm5
-
-// CHECK: 	cvtsi2sdl	%ecx, %xmm5
-        	cvtsi2sdl	%ecx,%xmm5
-
-// CHECK: 	cvtsi2sdl	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtsi2sdl	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtsi2sdl	69, %xmm5
-        	cvtsi2sdl	0x45,%xmm5
-
-// CHECK: 	cvtsi2sdl	32493, %xmm5
-        	cvtsi2sdl	0x7eed,%xmm5
-
-// CHECK: 	cvtsi2sdl	3133065982, %xmm5
-        	cvtsi2sdl	0xbabecafe,%xmm5
-
-// CHECK: 	cvtsi2sdl	305419896, %xmm5
-        	cvtsi2sdl	0x12345678,%xmm5
-
-// CHECK: 	divpd	3735928559(%ebx,%ecx,8), %xmm5
-        	divpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	divpd	69, %xmm5
-        	divpd	0x45,%xmm5
-
-// CHECK: 	divpd	32493, %xmm5
-        	divpd	0x7eed,%xmm5
-
-// CHECK: 	divpd	3133065982, %xmm5
-        	divpd	0xbabecafe,%xmm5
-
-// CHECK: 	divpd	305419896, %xmm5
-        	divpd	0x12345678,%xmm5
-
-// CHECK: 	divpd	%xmm5, %xmm5
-        	divpd	%xmm5,%xmm5
-
-// CHECK: 	divsd	3735928559(%ebx,%ecx,8), %xmm5
-        	divsd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	divsd	69, %xmm5
-        	divsd	0x45,%xmm5
-
-// CHECK: 	divsd	32493, %xmm5
-        	divsd	0x7eed,%xmm5
-
-// CHECK: 	divsd	3133065982, %xmm5
-        	divsd	0xbabecafe,%xmm5
-
-// CHECK: 	divsd	305419896, %xmm5
-        	divsd	0x12345678,%xmm5
-
-// CHECK: 	divsd	%xmm5, %xmm5
-        	divsd	%xmm5,%xmm5
-
-// CHECK: 	maxpd	3735928559(%ebx,%ecx,8), %xmm5
-        	maxpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	maxpd	69, %xmm5
-        	maxpd	0x45,%xmm5
-
-// CHECK: 	maxpd	32493, %xmm5
-        	maxpd	0x7eed,%xmm5
-
-// CHECK: 	maxpd	3133065982, %xmm5
-        	maxpd	0xbabecafe,%xmm5
-
-// CHECK: 	maxpd	305419896, %xmm5
-        	maxpd	0x12345678,%xmm5
-
-// CHECK: 	maxpd	%xmm5, %xmm5
-        	maxpd	%xmm5,%xmm5
-
-// CHECK: 	maxsd	3735928559(%ebx,%ecx,8), %xmm5
-        	maxsd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	maxsd	69, %xmm5
-        	maxsd	0x45,%xmm5
-
-// CHECK: 	maxsd	32493, %xmm5
-        	maxsd	0x7eed,%xmm5
-
-// CHECK: 	maxsd	3133065982, %xmm5
-        	maxsd	0xbabecafe,%xmm5
-
-// CHECK: 	maxsd	305419896, %xmm5
-        	maxsd	0x12345678,%xmm5
-
-// CHECK: 	maxsd	%xmm5, %xmm5
-        	maxsd	%xmm5,%xmm5
-
-// CHECK: 	minpd	3735928559(%ebx,%ecx,8), %xmm5
-        	minpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	minpd	69, %xmm5
-        	minpd	0x45,%xmm5
-
-// CHECK: 	minpd	32493, %xmm5
-        	minpd	0x7eed,%xmm5
-
-// CHECK: 	minpd	3133065982, %xmm5
-        	minpd	0xbabecafe,%xmm5
-
-// CHECK: 	minpd	305419896, %xmm5
-        	minpd	0x12345678,%xmm5
-
-// CHECK: 	minpd	%xmm5, %xmm5
-        	minpd	%xmm5,%xmm5
-
-// CHECK: 	minsd	3735928559(%ebx,%ecx,8), %xmm5
-        	minsd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	minsd	69, %xmm5
-        	minsd	0x45,%xmm5
-
-// CHECK: 	minsd	32493, %xmm5
-        	minsd	0x7eed,%xmm5
-
-// CHECK: 	minsd	3133065982, %xmm5
-        	minsd	0xbabecafe,%xmm5
-
-// CHECK: 	minsd	305419896, %xmm5
-        	minsd	0x12345678,%xmm5
-
-// CHECK: 	minsd	%xmm5, %xmm5
-        	minsd	%xmm5,%xmm5
-
-// CHECK: 	movapd	3735928559(%ebx,%ecx,8), %xmm5
-        	movapd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movapd	69, %xmm5
-        	movapd	0x45,%xmm5
-
-// CHECK: 	movapd	32493, %xmm5
-        	movapd	0x7eed,%xmm5
-
-// CHECK: 	movapd	3133065982, %xmm5
-        	movapd	0xbabecafe,%xmm5
-
-// CHECK: 	movapd	305419896, %xmm5
-        	movapd	0x12345678,%xmm5
-
-// CHECK: 	movapd	%xmm5, %xmm5
-        	movapd	%xmm5,%xmm5
-
-// CHECK: 	movapd	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movapd	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movapd	%xmm5, 69
-        	movapd	%xmm5,0x45
-
-// CHECK: 	movapd	%xmm5, 32493
-        	movapd	%xmm5,0x7eed
-
-// CHECK: 	movapd	%xmm5, 3133065982
-        	movapd	%xmm5,0xbabecafe
-
-// CHECK: 	movapd	%xmm5, 305419896
-        	movapd	%xmm5,0x12345678
-
-// CHECK: 	movapd	%xmm5, %xmm5
-        	movapd	%xmm5,%xmm5
-
-// CHECK: 	movhpd	3735928559(%ebx,%ecx,8), %xmm5
-        	movhpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movhpd	69, %xmm5
-        	movhpd	0x45,%xmm5
-
-// CHECK: 	movhpd	32493, %xmm5
-        	movhpd	0x7eed,%xmm5
-
-// CHECK: 	movhpd	3133065982, %xmm5
-        	movhpd	0xbabecafe,%xmm5
-
-// CHECK: 	movhpd	305419896, %xmm5
-        	movhpd	0x12345678,%xmm5
-
-// CHECK: 	movhpd	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movhpd	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movhpd	%xmm5, 69
-        	movhpd	%xmm5,0x45
-
-// CHECK: 	movhpd	%xmm5, 32493
-        	movhpd	%xmm5,0x7eed
-
-// CHECK: 	movhpd	%xmm5, 3133065982
-        	movhpd	%xmm5,0xbabecafe
-
-// CHECK: 	movhpd	%xmm5, 305419896
-        	movhpd	%xmm5,0x12345678
-
-// CHECK: 	movlpd	3735928559(%ebx,%ecx,8), %xmm5
-        	movlpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movlpd	69, %xmm5
-        	movlpd	0x45,%xmm5
-
-// CHECK: 	movlpd	32493, %xmm5
-        	movlpd	0x7eed,%xmm5
-
-// CHECK: 	movlpd	3133065982, %xmm5
-        	movlpd	0xbabecafe,%xmm5
-
-// CHECK: 	movlpd	305419896, %xmm5
-        	movlpd	0x12345678,%xmm5
-
-// CHECK: 	movlpd	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movlpd	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movlpd	%xmm5, 69
-        	movlpd	%xmm5,0x45
-
-// CHECK: 	movlpd	%xmm5, 32493
-        	movlpd	%xmm5,0x7eed
-
-// CHECK: 	movlpd	%xmm5, 3133065982
-        	movlpd	%xmm5,0xbabecafe
-
-// CHECK: 	movlpd	%xmm5, 305419896
-        	movlpd	%xmm5,0x12345678
-
-// CHECK: 	movmskpd	%xmm5, %ecx
-        	movmskpd	%xmm5,%ecx
-
-// CHECK: 	movntpd	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movntpd	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movntpd	%xmm5, 69
-        	movntpd	%xmm5,0x45
-
-// CHECK: 	movntpd	%xmm5, 32493
-        	movntpd	%xmm5,0x7eed
-
-// CHECK: 	movntpd	%xmm5, 3133065982
-        	movntpd	%xmm5,0xbabecafe
-
-// CHECK: 	movntpd	%xmm5, 305419896
-        	movntpd	%xmm5,0x12345678
-
-// CHECK: 	movsd	3735928559(%ebx,%ecx,8), %xmm5
-        	movsd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movsd	69, %xmm5
-        	movsd	0x45,%xmm5
-
-// CHECK: 	movsd	32493, %xmm5
-        	movsd	0x7eed,%xmm5
-
-// CHECK: 	movsd	3133065982, %xmm5
-        	movsd	0xbabecafe,%xmm5
-
-// CHECK: 	movsd	305419896, %xmm5
-        	movsd	0x12345678,%xmm5
-
-// CHECK: 	movsd	%xmm5, %xmm5
-        	movsd	%xmm5,%xmm5
-
-// CHECK: 	movsd	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movsd	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movsd	%xmm5, 69
-        	movsd	%xmm5,0x45
-
-// CHECK: 	movsd	%xmm5, 32493
-        	movsd	%xmm5,0x7eed
-
-// CHECK: 	movsd	%xmm5, 3133065982
-        	movsd	%xmm5,0xbabecafe
-
-// CHECK: 	movsd	%xmm5, 305419896
-        	movsd	%xmm5,0x12345678
-
-// CHECK: 	movsd	%xmm5, %xmm5
-        	movsd	%xmm5,%xmm5
-
-// CHECK: 	movupd	3735928559(%ebx,%ecx,8), %xmm5
-        	movupd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movupd	69, %xmm5
-        	movupd	0x45,%xmm5
-
-// CHECK: 	movupd	32493, %xmm5
-        	movupd	0x7eed,%xmm5
-
-// CHECK: 	movupd	3133065982, %xmm5
-        	movupd	0xbabecafe,%xmm5
-
-// CHECK: 	movupd	305419896, %xmm5
-        	movupd	0x12345678,%xmm5
-
-// CHECK: 	movupd	%xmm5, %xmm5
-        	movupd	%xmm5,%xmm5
-
-// CHECK: 	movupd	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movupd	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movupd	%xmm5, 69
-        	movupd	%xmm5,0x45
-
-// CHECK: 	movupd	%xmm5, 32493
-        	movupd	%xmm5,0x7eed
-
-// CHECK: 	movupd	%xmm5, 3133065982
-        	movupd	%xmm5,0xbabecafe
-
-// CHECK: 	movupd	%xmm5, 305419896
-        	movupd	%xmm5,0x12345678
-
-// CHECK: 	movupd	%xmm5, %xmm5
-        	movupd	%xmm5,%xmm5
-
-// CHECK: 	mulpd	3735928559(%ebx,%ecx,8), %xmm5
-        	mulpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	mulpd	69, %xmm5
-        	mulpd	0x45,%xmm5
-
-// CHECK: 	mulpd	32493, %xmm5
-        	mulpd	0x7eed,%xmm5
-
-// CHECK: 	mulpd	3133065982, %xmm5
-        	mulpd	0xbabecafe,%xmm5
-
-// CHECK: 	mulpd	305419896, %xmm5
-        	mulpd	0x12345678,%xmm5
-
-// CHECK: 	mulpd	%xmm5, %xmm5
-        	mulpd	%xmm5,%xmm5
-
-// CHECK: 	mulsd	3735928559(%ebx,%ecx,8), %xmm5
-        	mulsd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	mulsd	69, %xmm5
-        	mulsd	0x45,%xmm5
-
-// CHECK: 	mulsd	32493, %xmm5
-        	mulsd	0x7eed,%xmm5
-
-// CHECK: 	mulsd	3133065982, %xmm5
-        	mulsd	0xbabecafe,%xmm5
-
-// CHECK: 	mulsd	305419896, %xmm5
-        	mulsd	0x12345678,%xmm5
-
-// CHECK: 	mulsd	%xmm5, %xmm5
-        	mulsd	%xmm5,%xmm5
-
-// CHECK: 	orpd	3735928559(%ebx,%ecx,8), %xmm5
-        	orpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	orpd	69, %xmm5
-        	orpd	0x45,%xmm5
-
-// CHECK: 	orpd	32493, %xmm5
-        	orpd	0x7eed,%xmm5
-
-// CHECK: 	orpd	3133065982, %xmm5
-        	orpd	0xbabecafe,%xmm5
-
-// CHECK: 	orpd	305419896, %xmm5
-        	orpd	0x12345678,%xmm5
-
-// CHECK: 	orpd	%xmm5, %xmm5
-        	orpd	%xmm5,%xmm5
-
-// CHECK: 	sqrtpd	3735928559(%ebx,%ecx,8), %xmm5
-        	sqrtpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	sqrtpd	69, %xmm5
-        	sqrtpd	0x45,%xmm5
-
-// CHECK: 	sqrtpd	32493, %xmm5
-        	sqrtpd	0x7eed,%xmm5
-
-// CHECK: 	sqrtpd	3133065982, %xmm5
-        	sqrtpd	0xbabecafe,%xmm5
-
-// CHECK: 	sqrtpd	305419896, %xmm5
-        	sqrtpd	0x12345678,%xmm5
-
-// CHECK: 	sqrtpd	%xmm5, %xmm5
-        	sqrtpd	%xmm5,%xmm5
-
-// CHECK: 	sqrtsd	3735928559(%ebx,%ecx,8), %xmm5
-        	sqrtsd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	sqrtsd	69, %xmm5
-        	sqrtsd	0x45,%xmm5
-
-// CHECK: 	sqrtsd	32493, %xmm5
-        	sqrtsd	0x7eed,%xmm5
-
-// CHECK: 	sqrtsd	3133065982, %xmm5
-        	sqrtsd	0xbabecafe,%xmm5
-
-// CHECK: 	sqrtsd	305419896, %xmm5
-        	sqrtsd	0x12345678,%xmm5
-
-// CHECK: 	sqrtsd	%xmm5, %xmm5
-        	sqrtsd	%xmm5,%xmm5
-
-// CHECK: 	subpd	3735928559(%ebx,%ecx,8), %xmm5
-        	subpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	subpd	69, %xmm5
-        	subpd	0x45,%xmm5
-
-// CHECK: 	subpd	32493, %xmm5
-        	subpd	0x7eed,%xmm5
-
-// CHECK: 	subpd	3133065982, %xmm5
-        	subpd	0xbabecafe,%xmm5
-
-// CHECK: 	subpd	305419896, %xmm5
-        	subpd	0x12345678,%xmm5
-
-// CHECK: 	subpd	%xmm5, %xmm5
-        	subpd	%xmm5,%xmm5
-
-// CHECK: 	subsd	3735928559(%ebx,%ecx,8), %xmm5
-        	subsd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	subsd	69, %xmm5
-        	subsd	0x45,%xmm5
-
-// CHECK: 	subsd	32493, %xmm5
-        	subsd	0x7eed,%xmm5
-
-// CHECK: 	subsd	3133065982, %xmm5
-        	subsd	0xbabecafe,%xmm5
-
-// CHECK: 	subsd	305419896, %xmm5
-        	subsd	0x12345678,%xmm5
-
-// CHECK: 	subsd	%xmm5, %xmm5
-        	subsd	%xmm5,%xmm5
-
-// CHECK: 	ucomisd	3735928559(%ebx,%ecx,8), %xmm5
-        	ucomisd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	ucomisd	69, %xmm5
-        	ucomisd	0x45,%xmm5
-
-// CHECK: 	ucomisd	32493, %xmm5
-        	ucomisd	0x7eed,%xmm5
-
-// CHECK: 	ucomisd	3133065982, %xmm5
-        	ucomisd	0xbabecafe,%xmm5
-
-// CHECK: 	ucomisd	305419896, %xmm5
-        	ucomisd	0x12345678,%xmm5
-
-// CHECK: 	ucomisd	%xmm5, %xmm5
-        	ucomisd	%xmm5,%xmm5
-
-// CHECK: 	unpckhpd	3735928559(%ebx,%ecx,8), %xmm5
-        	unpckhpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	unpckhpd	69, %xmm5
-        	unpckhpd	0x45,%xmm5
-
-// CHECK: 	unpckhpd	32493, %xmm5
-        	unpckhpd	0x7eed,%xmm5
-
-// CHECK: 	unpckhpd	3133065982, %xmm5
-        	unpckhpd	0xbabecafe,%xmm5
-
-// CHECK: 	unpckhpd	305419896, %xmm5
-        	unpckhpd	0x12345678,%xmm5
-
-// CHECK: 	unpckhpd	%xmm5, %xmm5
-        	unpckhpd	%xmm5,%xmm5
-
-// CHECK: 	unpcklpd	3735928559(%ebx,%ecx,8), %xmm5
-        	unpcklpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	unpcklpd	69, %xmm5
-        	unpcklpd	0x45,%xmm5
-
-// CHECK: 	unpcklpd	32493, %xmm5
-        	unpcklpd	0x7eed,%xmm5
-
-// CHECK: 	unpcklpd	3133065982, %xmm5
-        	unpcklpd	0xbabecafe,%xmm5
-
-// CHECK: 	unpcklpd	305419896, %xmm5
-        	unpcklpd	0x12345678,%xmm5
-
-// CHECK: 	unpcklpd	%xmm5, %xmm5
-        	unpcklpd	%xmm5,%xmm5
-
-// CHECK: 	xorpd	3735928559(%ebx,%ecx,8), %xmm5
-        	xorpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	xorpd	69, %xmm5
-        	xorpd	0x45,%xmm5
-
-// CHECK: 	xorpd	32493, %xmm5
-        	xorpd	0x7eed,%xmm5
-
-// CHECK: 	xorpd	3133065982, %xmm5
-        	xorpd	0xbabecafe,%xmm5
-
-// CHECK: 	xorpd	305419896, %xmm5
-        	xorpd	0x12345678,%xmm5
-
-// CHECK: 	xorpd	%xmm5, %xmm5
-        	xorpd	%xmm5,%xmm5
-
-// CHECK: 	cvtdq2pd	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtdq2pd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtdq2pd	69, %xmm5
-        	cvtdq2pd	0x45,%xmm5
-
-// CHECK: 	cvtdq2pd	32493, %xmm5
-        	cvtdq2pd	0x7eed,%xmm5
-
-// CHECK: 	cvtdq2pd	3133065982, %xmm5
-        	cvtdq2pd	0xbabecafe,%xmm5
-
-// CHECK: 	cvtdq2pd	305419896, %xmm5
-        	cvtdq2pd	0x12345678,%xmm5
-
-// CHECK: 	cvtdq2pd	%xmm5, %xmm5
-        	cvtdq2pd	%xmm5,%xmm5
-
-// CHECK: 	cvtpd2dq	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtpd2dq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtpd2dq	69, %xmm5
-        	cvtpd2dq	0x45,%xmm5
-
-// CHECK: 	cvtpd2dq	32493, %xmm5
-        	cvtpd2dq	0x7eed,%xmm5
-
-// CHECK: 	cvtpd2dq	3133065982, %xmm5
-        	cvtpd2dq	0xbabecafe,%xmm5
-
-// CHECK: 	cvtpd2dq	305419896, %xmm5
-        	cvtpd2dq	0x12345678,%xmm5
-
-// CHECK: 	cvtpd2dq	%xmm5, %xmm5
-        	cvtpd2dq	%xmm5,%xmm5
-
-// CHECK: 	cvtdq2ps	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtdq2ps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtdq2ps	69, %xmm5
-        	cvtdq2ps	0x45,%xmm5
-
-// CHECK: 	cvtdq2ps	32493, %xmm5
-        	cvtdq2ps	0x7eed,%xmm5
-
-// CHECK: 	cvtdq2ps	3133065982, %xmm5
-        	cvtdq2ps	0xbabecafe,%xmm5
-
-// CHECK: 	cvtdq2ps	305419896, %xmm5
-        	cvtdq2ps	0x12345678,%xmm5
-
-// CHECK: 	cvtdq2ps	%xmm5, %xmm5
-        	cvtdq2ps	%xmm5,%xmm5
-
-// CHECK: 	cvtpd2pi	3735928559(%ebx,%ecx,8), %mm3
-        	cvtpd2pi	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	cvtpd2pi	69, %mm3
-        	cvtpd2pi	0x45,%mm3
-
-// CHECK: 	cvtpd2pi	32493, %mm3
-        	cvtpd2pi	0x7eed,%mm3
-
-// CHECK: 	cvtpd2pi	3133065982, %mm3
-        	cvtpd2pi	0xbabecafe,%mm3
-
-// CHECK: 	cvtpd2pi	305419896, %mm3
-        	cvtpd2pi	0x12345678,%mm3
-
-// CHECK: 	cvtpd2pi	%xmm5, %mm3
-        	cvtpd2pi	%xmm5,%mm3
-
-// CHECK: 	cvtpd2ps	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtpd2ps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtpd2ps	69, %xmm5
-        	cvtpd2ps	0x45,%xmm5
-
-// CHECK: 	cvtpd2ps	32493, %xmm5
-        	cvtpd2ps	0x7eed,%xmm5
-
-// CHECK: 	cvtpd2ps	3133065982, %xmm5
-        	cvtpd2ps	0xbabecafe,%xmm5
-
-// CHECK: 	cvtpd2ps	305419896, %xmm5
-        	cvtpd2ps	0x12345678,%xmm5
-
-// CHECK: 	cvtpd2ps	%xmm5, %xmm5
-        	cvtpd2ps	%xmm5,%xmm5
-
-// CHECK: 	cvtps2pd	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtps2pd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtps2pd	69, %xmm5
-        	cvtps2pd	0x45,%xmm5
-
-// CHECK: 	cvtps2pd	32493, %xmm5
-        	cvtps2pd	0x7eed,%xmm5
-
-// CHECK: 	cvtps2pd	3133065982, %xmm5
-        	cvtps2pd	0xbabecafe,%xmm5
-
-// CHECK: 	cvtps2pd	305419896, %xmm5
-        	cvtps2pd	0x12345678,%xmm5
-
-// CHECK: 	cvtps2pd	%xmm5, %xmm5
-        	cvtps2pd	%xmm5,%xmm5
-
-// CHECK: 	cvtps2dq	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtps2dq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtps2dq	69, %xmm5
-        	cvtps2dq	0x45,%xmm5
-
-// CHECK: 	cvtps2dq	32493, %xmm5
-        	cvtps2dq	0x7eed,%xmm5
-
-// CHECK: 	cvtps2dq	3133065982, %xmm5
-        	cvtps2dq	0xbabecafe,%xmm5
-
-// CHECK: 	cvtps2dq	305419896, %xmm5
-        	cvtps2dq	0x12345678,%xmm5
-
-// CHECK: 	cvtps2dq	%xmm5, %xmm5
-        	cvtps2dq	%xmm5,%xmm5
-
-// CHECK: 	cvtsd2ss	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtsd2ss	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtsd2ss	69, %xmm5
-        	cvtsd2ss	0x45,%xmm5
-
-// CHECK: 	cvtsd2ss	32493, %xmm5
-        	cvtsd2ss	0x7eed,%xmm5
-
-// CHECK: 	cvtsd2ss	3133065982, %xmm5
-        	cvtsd2ss	0xbabecafe,%xmm5
-
-// CHECK: 	cvtsd2ss	305419896, %xmm5
-        	cvtsd2ss	0x12345678,%xmm5
-
-// CHECK: 	cvtsd2ss	%xmm5, %xmm5
-        	cvtsd2ss	%xmm5,%xmm5
-
-// CHECK: 	cvtss2sd	3735928559(%ebx,%ecx,8), %xmm5
-        	cvtss2sd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvtss2sd	69, %xmm5
-        	cvtss2sd	0x45,%xmm5
-
-// CHECK: 	cvtss2sd	32493, %xmm5
-        	cvtss2sd	0x7eed,%xmm5
-
-// CHECK: 	cvtss2sd	3133065982, %xmm5
-        	cvtss2sd	0xbabecafe,%xmm5
-
-// CHECK: 	cvtss2sd	305419896, %xmm5
-        	cvtss2sd	0x12345678,%xmm5
-
-// CHECK: 	cvtss2sd	%xmm5, %xmm5
-        	cvtss2sd	%xmm5,%xmm5
-
-// CHECK: 	cvttpd2pi	3735928559(%ebx,%ecx,8), %mm3
-        	cvttpd2pi	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	cvttpd2pi	69, %mm3
-        	cvttpd2pi	0x45,%mm3
-
-// CHECK: 	cvttpd2pi	32493, %mm3
-        	cvttpd2pi	0x7eed,%mm3
-
-// CHECK: 	cvttpd2pi	3133065982, %mm3
-        	cvttpd2pi	0xbabecafe,%mm3
-
-// CHECK: 	cvttpd2pi	305419896, %mm3
-        	cvttpd2pi	0x12345678,%mm3
-
-// CHECK: 	cvttpd2pi	%xmm5, %mm3
-        	cvttpd2pi	%xmm5,%mm3
-
-// CHECK: 	cvttsd2si	3735928559(%ebx,%ecx,8), %ecx
-        	cvttsd2si	0xdeadbeef(%ebx,%ecx,8),%ecx
-
-// CHECK: 	cvttsd2si	69, %ecx
-        	cvttsd2si	0x45,%ecx
-
-// CHECK: 	cvttsd2si	32493, %ecx
-        	cvttsd2si	0x7eed,%ecx
-
-// CHECK: 	cvttsd2si	3133065982, %ecx
-        	cvttsd2si	0xbabecafe,%ecx
-
-// CHECK: 	cvttsd2si	305419896, %ecx
-        	cvttsd2si	0x12345678,%ecx
-
-// CHECK: 	cvttsd2si	%xmm5, %ecx
-        	cvttsd2si	%xmm5,%ecx
-
-// CHECK: 	cvttps2dq	3735928559(%ebx,%ecx,8), %xmm5
-        	cvttps2dq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	cvttps2dq	69, %xmm5
-        	cvttps2dq	0x45,%xmm5
-
-// CHECK: 	cvttps2dq	32493, %xmm5
-        	cvttps2dq	0x7eed,%xmm5
-
-// CHECK: 	cvttps2dq	3133065982, %xmm5
-        	cvttps2dq	0xbabecafe,%xmm5
-
-// CHECK: 	cvttps2dq	305419896, %xmm5
-        	cvttps2dq	0x12345678,%xmm5
-
-// CHECK: 	cvttps2dq	%xmm5, %xmm5
-        	cvttps2dq	%xmm5,%xmm5
-
-// CHECK: 	maskmovdqu	%xmm5, %xmm5
-        	maskmovdqu	%xmm5,%xmm5
-
-// CHECK: 	movdqa	3735928559(%ebx,%ecx,8), %xmm5
-        	movdqa	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movdqa	69, %xmm5
-        	movdqa	0x45,%xmm5
-
-// CHECK: 	movdqa	32493, %xmm5
-        	movdqa	0x7eed,%xmm5
-
-// CHECK: 	movdqa	3133065982, %xmm5
-        	movdqa	0xbabecafe,%xmm5
-
-// CHECK: 	movdqa	305419896, %xmm5
-        	movdqa	0x12345678,%xmm5
-
-// CHECK: 	movdqa	%xmm5, %xmm5
-        	movdqa	%xmm5,%xmm5
-
-// CHECK: 	movdqa	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movdqa	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movdqa	%xmm5, 69
-        	movdqa	%xmm5,0x45
-
-// CHECK: 	movdqa	%xmm5, 32493
-        	movdqa	%xmm5,0x7eed
-
-// CHECK: 	movdqa	%xmm5, 3133065982
-        	movdqa	%xmm5,0xbabecafe
-
-// CHECK: 	movdqa	%xmm5, 305419896
-        	movdqa	%xmm5,0x12345678
-
-// CHECK: 	movdqa	%xmm5, %xmm5
-        	movdqa	%xmm5,%xmm5
-
-// CHECK: 	movdqu	3735928559(%ebx,%ecx,8), %xmm5
-        	movdqu	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movdqu	69, %xmm5
-        	movdqu	0x45,%xmm5
-
-// CHECK: 	movdqu	32493, %xmm5
-        	movdqu	0x7eed,%xmm5
-
-// CHECK: 	movdqu	3133065982, %xmm5
-        	movdqu	0xbabecafe,%xmm5
-
-// CHECK: 	movdqu	305419896, %xmm5
-        	movdqu	0x12345678,%xmm5
-
-// CHECK: 	movdqu	%xmm5, 3735928559(%ebx,%ecx,8)
-        	movdqu	%xmm5,0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	movdqu	%xmm5, 69
-        	movdqu	%xmm5,0x45
-
-// CHECK: 	movdqu	%xmm5, 32493
-        	movdqu	%xmm5,0x7eed
-
-// CHECK: 	movdqu	%xmm5, 3133065982
-        	movdqu	%xmm5,0xbabecafe
-
-// CHECK: 	movdqu	%xmm5, 305419896
-        	movdqu	%xmm5,0x12345678
-
-// CHECK: 	movdq2q	%xmm5, %mm3
-        	movdq2q	%xmm5,%mm3
-
-// CHECK: 	movq2dq	%mm3, %xmm5
-        	movq2dq	%mm3,%xmm5
-
-// CHECK: 	pmuludq	3735928559(%ebx,%ecx,8), %mm3
-        	pmuludq	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pmuludq	69, %mm3
-        	pmuludq	0x45,%mm3
-
-// CHECK: 	pmuludq	32493, %mm3
-        	pmuludq	0x7eed,%mm3
-
-// CHECK: 	pmuludq	3133065982, %mm3
-        	pmuludq	0xbabecafe,%mm3
-
-// CHECK: 	pmuludq	305419896, %mm3
-        	pmuludq	0x12345678,%mm3
-
-// CHECK: 	pmuludq	%mm3, %mm3
-        	pmuludq	%mm3,%mm3
-
-// CHECK: 	pmuludq	3735928559(%ebx,%ecx,8), %xmm5
-        	pmuludq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmuludq	69, %xmm5
-        	pmuludq	0x45,%xmm5
-
-// CHECK: 	pmuludq	32493, %xmm5
-        	pmuludq	0x7eed,%xmm5
-
-// CHECK: 	pmuludq	3133065982, %xmm5
-        	pmuludq	0xbabecafe,%xmm5
-
-// CHECK: 	pmuludq	305419896, %xmm5
-        	pmuludq	0x12345678,%xmm5
-
-// CHECK: 	pmuludq	%xmm5, %xmm5
-        	pmuludq	%xmm5,%xmm5
-
-// CHECK: 	pslldq	$127, %xmm5
-        	pslldq	$0x7f,%xmm5
-
-// CHECK: 	psrldq	$127, %xmm5
-        	psrldq	$0x7f,%xmm5
-
-// CHECK: 	punpckhqdq	3735928559(%ebx,%ecx,8), %xmm5
-        	punpckhqdq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	punpckhqdq	69, %xmm5
-        	punpckhqdq	0x45,%xmm5
-
-// CHECK: 	punpckhqdq	32493, %xmm5
-        	punpckhqdq	0x7eed,%xmm5
-
-// CHECK: 	punpckhqdq	3133065982, %xmm5
-        	punpckhqdq	0xbabecafe,%xmm5
-
-// CHECK: 	punpckhqdq	305419896, %xmm5
-        	punpckhqdq	0x12345678,%xmm5
-
-// CHECK: 	punpckhqdq	%xmm5, %xmm5
-        	punpckhqdq	%xmm5,%xmm5
-
-// CHECK: 	punpcklqdq	3735928559(%ebx,%ecx,8), %xmm5
-        	punpcklqdq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	punpcklqdq	69, %xmm5
-        	punpcklqdq	0x45,%xmm5
-
-// CHECK: 	punpcklqdq	32493, %xmm5
-        	punpcklqdq	0x7eed,%xmm5
-
-// CHECK: 	punpcklqdq	3133065982, %xmm5
-        	punpcklqdq	0xbabecafe,%xmm5
-
-// CHECK: 	punpcklqdq	305419896, %xmm5
-        	punpcklqdq	0x12345678,%xmm5
-
-// CHECK: 	punpcklqdq	%xmm5, %xmm5
-        	punpcklqdq	%xmm5,%xmm5
-
-// CHECK: 	addsubpd	3735928559(%ebx,%ecx,8), %xmm5
-        	addsubpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	addsubpd	69, %xmm5
-        	addsubpd	0x45,%xmm5
-
-// CHECK: 	addsubpd	32493, %xmm5
-        	addsubpd	0x7eed,%xmm5
-
-// CHECK: 	addsubpd	3133065982, %xmm5
-        	addsubpd	0xbabecafe,%xmm5
-
-// CHECK: 	addsubpd	305419896, %xmm5
-        	addsubpd	0x12345678,%xmm5
-
-// CHECK: 	addsubpd	%xmm5, %xmm5
-        	addsubpd	%xmm5,%xmm5
-
-// CHECK: 	addsubps	3735928559(%ebx,%ecx,8), %xmm5
-        	addsubps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	addsubps	69, %xmm5
-        	addsubps	0x45,%xmm5
-
-// CHECK: 	addsubps	32493, %xmm5
-        	addsubps	0x7eed,%xmm5
-
-// CHECK: 	addsubps	3133065982, %xmm5
-        	addsubps	0xbabecafe,%xmm5
-
-// CHECK: 	addsubps	305419896, %xmm5
-        	addsubps	0x12345678,%xmm5
-
-// CHECK: 	addsubps	%xmm5, %xmm5
-        	addsubps	%xmm5,%xmm5
-
-// CHECK: 	fisttpl	3735928559(%ebx,%ecx,8)
-        	fisttpl	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	fisttpl	3133065982
-        	fisttpl	0xbabecafe
-
-// CHECK: 	fisttpl	305419896
-        	fisttpl	0x12345678
-
-// CHECK: 	haddpd	3735928559(%ebx,%ecx,8), %xmm5
-        	haddpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	haddpd	69, %xmm5
-        	haddpd	0x45,%xmm5
-
-// CHECK: 	haddpd	32493, %xmm5
-        	haddpd	0x7eed,%xmm5
-
-// CHECK: 	haddpd	3133065982, %xmm5
-        	haddpd	0xbabecafe,%xmm5
-
-// CHECK: 	haddpd	305419896, %xmm5
-        	haddpd	0x12345678,%xmm5
-
-// CHECK: 	haddpd	%xmm5, %xmm5
-        	haddpd	%xmm5,%xmm5
-
-// CHECK: 	haddps	3735928559(%ebx,%ecx,8), %xmm5
-        	haddps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	haddps	69, %xmm5
-        	haddps	0x45,%xmm5
-
-// CHECK: 	haddps	32493, %xmm5
-        	haddps	0x7eed,%xmm5
-
-// CHECK: 	haddps	3133065982, %xmm5
-        	haddps	0xbabecafe,%xmm5
-
-// CHECK: 	haddps	305419896, %xmm5
-        	haddps	0x12345678,%xmm5
-
-// CHECK: 	haddps	%xmm5, %xmm5
-        	haddps	%xmm5,%xmm5
-
-// CHECK: 	hsubpd	3735928559(%ebx,%ecx,8), %xmm5
-        	hsubpd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	hsubpd	69, %xmm5
-        	hsubpd	0x45,%xmm5
-
-// CHECK: 	hsubpd	32493, %xmm5
-        	hsubpd	0x7eed,%xmm5
-
-// CHECK: 	hsubpd	3133065982, %xmm5
-        	hsubpd	0xbabecafe,%xmm5
-
-// CHECK: 	hsubpd	305419896, %xmm5
-        	hsubpd	0x12345678,%xmm5
-
-// CHECK: 	hsubpd	%xmm5, %xmm5
-        	hsubpd	%xmm5,%xmm5
-
-// CHECK: 	hsubps	3735928559(%ebx,%ecx,8), %xmm5
-        	hsubps	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	hsubps	69, %xmm5
-        	hsubps	0x45,%xmm5
-
-// CHECK: 	hsubps	32493, %xmm5
-        	hsubps	0x7eed,%xmm5
-
-// CHECK: 	hsubps	3133065982, %xmm5
-        	hsubps	0xbabecafe,%xmm5
-
-// CHECK: 	hsubps	305419896, %xmm5
-        	hsubps	0x12345678,%xmm5
-
-// CHECK: 	hsubps	%xmm5, %xmm5
-        	hsubps	%xmm5,%xmm5
-
-// CHECK: 	lddqu	3735928559(%ebx,%ecx,8), %xmm5
-        	lddqu	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	lddqu	69, %xmm5
-        	lddqu	0x45,%xmm5
-
-// CHECK: 	lddqu	32493, %xmm5
-        	lddqu	0x7eed,%xmm5
-
-// CHECK: 	lddqu	3133065982, %xmm5
-        	lddqu	0xbabecafe,%xmm5
-
-// CHECK: 	lddqu	305419896, %xmm5
-        	lddqu	0x12345678,%xmm5
-
 // CHECK: 	monitor
         	monitor
 
-// CHECK: 	movddup	3735928559(%ebx,%ecx,8), %xmm5
-        	movddup	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movddup	69, %xmm5
-        	movddup	0x45,%xmm5
-
-// CHECK: 	movddup	32493, %xmm5
-        	movddup	0x7eed,%xmm5
-
-// CHECK: 	movddup	3133065982, %xmm5
-        	movddup	0xbabecafe,%xmm5
-
-// CHECK: 	movddup	305419896, %xmm5
-        	movddup	0x12345678,%xmm5
-
-// CHECK: 	movddup	%xmm5, %xmm5
-        	movddup	%xmm5,%xmm5
-
-// CHECK: 	movshdup	3735928559(%ebx,%ecx,8), %xmm5
-        	movshdup	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movshdup	69, %xmm5
-        	movshdup	0x45,%xmm5
-
-// CHECK: 	movshdup	32493, %xmm5
-        	movshdup	0x7eed,%xmm5
-
-// CHECK: 	movshdup	3133065982, %xmm5
-        	movshdup	0xbabecafe,%xmm5
-
-// CHECK: 	movshdup	305419896, %xmm5
-        	movshdup	0x12345678,%xmm5
-
-// CHECK: 	movshdup	%xmm5, %xmm5
-        	movshdup	%xmm5,%xmm5
-
-// CHECK: 	movsldup	3735928559(%ebx,%ecx,8), %xmm5
-        	movsldup	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movsldup	69, %xmm5
-        	movsldup	0x45,%xmm5
-
-// CHECK: 	movsldup	32493, %xmm5
-        	movsldup	0x7eed,%xmm5
-
-// CHECK: 	movsldup	3133065982, %xmm5
-        	movsldup	0xbabecafe,%xmm5
-
-// CHECK: 	movsldup	305419896, %xmm5
-        	movsldup	0x12345678,%xmm5
-
-// CHECK: 	movsldup	%xmm5, %xmm5
-        	movsldup	%xmm5,%xmm5
-
 // CHECK: 	mwait
         	mwait
 
@@ -18419,48 +10466,12 @@
 // CHECK: 	vmfunc
         	vmfunc
 
-// CHECK: 	vmclear	3735928559(%ebx,%ecx,8)
-        	vmclear	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	vmclear	32493
-        	vmclear	0x7eed
-
-// CHECK: 	vmclear	3133065982
-        	vmclear	0xbabecafe
-
-// CHECK: 	vmclear	305419896
-        	vmclear	0x12345678
-
 // CHECK: 	vmlaunch
         	vmlaunch
 
 // CHECK: 	vmresume
         	vmresume
 
-// CHECK: 	vmptrld	3735928559(%ebx,%ecx,8)
-        	vmptrld	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	vmptrld	32493
-        	vmptrld	0x7eed
-
-// CHECK: 	vmptrld	3133065982
-        	vmptrld	0xbabecafe
-
-// CHECK: 	vmptrld	305419896
-        	vmptrld	0x12345678
-
-// CHECK: 	vmptrst	3735928559(%ebx,%ecx,8)
-        	vmptrst	0xdeadbeef(%ebx,%ecx,8)
-
-// CHECK: 	vmptrst	32493
-        	vmptrst	0x7eed
-
-// CHECK: 	vmptrst	3133065982
-        	vmptrst	0xbabecafe
-
-// CHECK: 	vmptrst	305419896
-        	vmptrst	0x12345678
-
 // CHECK: 	vmxoff
         	vmxoff
 
@@ -18500,1119 +10511,6 @@
 // CHECK: 	invlpga %ecx, %eax
         	invlpga %ecx, %eax
 
-// CHECK: 	phaddw	3735928559(%ebx,%ecx,8), %mm3
-        	phaddw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	phaddw	69, %mm3
-        	phaddw	0x45,%mm3
-
-// CHECK: 	phaddw	32493, %mm3
-        	phaddw	0x7eed,%mm3
-
-// CHECK: 	phaddw	3133065982, %mm3
-        	phaddw	0xbabecafe,%mm3
-
-// CHECK: 	phaddw	305419896, %mm3
-        	phaddw	0x12345678,%mm3
-
-// CHECK: 	phaddw	%mm3, %mm3
-        	phaddw	%mm3,%mm3
-
-// CHECK: 	phaddw	3735928559(%ebx,%ecx,8), %xmm5
-        	phaddw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	phaddw	69, %xmm5
-        	phaddw	0x45,%xmm5
-
-// CHECK: 	phaddw	32493, %xmm5
-        	phaddw	0x7eed,%xmm5
-
-// CHECK: 	phaddw	3133065982, %xmm5
-        	phaddw	0xbabecafe,%xmm5
-
-// CHECK: 	phaddw	305419896, %xmm5
-        	phaddw	0x12345678,%xmm5
-
-// CHECK: 	phaddw	%xmm5, %xmm5
-        	phaddw	%xmm5,%xmm5
-
-// CHECK: 	phaddd	3735928559(%ebx,%ecx,8), %mm3
-        	phaddd	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	phaddd	69, %mm3
-        	phaddd	0x45,%mm3
-
-// CHECK: 	phaddd	32493, %mm3
-        	phaddd	0x7eed,%mm3
-
-// CHECK: 	phaddd	3133065982, %mm3
-        	phaddd	0xbabecafe,%mm3
-
-// CHECK: 	phaddd	305419896, %mm3
-        	phaddd	0x12345678,%mm3
-
-// CHECK: 	phaddd	%mm3, %mm3
-        	phaddd	%mm3,%mm3
-
-// CHECK: 	phaddd	3735928559(%ebx,%ecx,8), %xmm5
-        	phaddd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	phaddd	69, %xmm5
-        	phaddd	0x45,%xmm5
-
-// CHECK: 	phaddd	32493, %xmm5
-        	phaddd	0x7eed,%xmm5
-
-// CHECK: 	phaddd	3133065982, %xmm5
-        	phaddd	0xbabecafe,%xmm5
-
-// CHECK: 	phaddd	305419896, %xmm5
-        	phaddd	0x12345678,%xmm5
-
-// CHECK: 	phaddd	%xmm5, %xmm5
-        	phaddd	%xmm5,%xmm5
-
-// CHECK: 	phaddsw	3735928559(%ebx,%ecx,8), %mm3
-        	phaddsw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	phaddsw	69, %mm3
-        	phaddsw	0x45,%mm3
-
-// CHECK: 	phaddsw	32493, %mm3
-        	phaddsw	0x7eed,%mm3
-
-// CHECK: 	phaddsw	3133065982, %mm3
-        	phaddsw	0xbabecafe,%mm3
-
-// CHECK: 	phaddsw	305419896, %mm3
-        	phaddsw	0x12345678,%mm3
-
-// CHECK: 	phaddsw	%mm3, %mm3
-        	phaddsw	%mm3,%mm3
-
-// CHECK: 	phaddsw	3735928559(%ebx,%ecx,8), %xmm5
-        	phaddsw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	phaddsw	69, %xmm5
-        	phaddsw	0x45,%xmm5
-
-// CHECK: 	phaddsw	32493, %xmm5
-        	phaddsw	0x7eed,%xmm5
-
-// CHECK: 	phaddsw	3133065982, %xmm5
-        	phaddsw	0xbabecafe,%xmm5
-
-// CHECK: 	phaddsw	305419896, %xmm5
-        	phaddsw	0x12345678,%xmm5
-
-// CHECK: 	phaddsw	%xmm5, %xmm5
-        	phaddsw	%xmm5,%xmm5
-
-// CHECK: 	phsubw	3735928559(%ebx,%ecx,8), %mm3
-        	phsubw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	phsubw	69, %mm3
-        	phsubw	0x45,%mm3
-
-// CHECK: 	phsubw	32493, %mm3
-        	phsubw	0x7eed,%mm3
-
-// CHECK: 	phsubw	3133065982, %mm3
-        	phsubw	0xbabecafe,%mm3
-
-// CHECK: 	phsubw	305419896, %mm3
-        	phsubw	0x12345678,%mm3
-
-// CHECK: 	phsubw	%mm3, %mm3
-        	phsubw	%mm3,%mm3
-
-// CHECK: 	phsubw	3735928559(%ebx,%ecx,8), %xmm5
-        	phsubw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	phsubw	69, %xmm5
-        	phsubw	0x45,%xmm5
-
-// CHECK: 	phsubw	32493, %xmm5
-        	phsubw	0x7eed,%xmm5
-
-// CHECK: 	phsubw	3133065982, %xmm5
-        	phsubw	0xbabecafe,%xmm5
-
-// CHECK: 	phsubw	305419896, %xmm5
-        	phsubw	0x12345678,%xmm5
-
-// CHECK: 	phsubw	%xmm5, %xmm5
-        	phsubw	%xmm5,%xmm5
-
-// CHECK: 	phsubd	3735928559(%ebx,%ecx,8), %mm3
-        	phsubd	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	phsubd	69, %mm3
-        	phsubd	0x45,%mm3
-
-// CHECK: 	phsubd	32493, %mm3
-        	phsubd	0x7eed,%mm3
-
-// CHECK: 	phsubd	3133065982, %mm3
-        	phsubd	0xbabecafe,%mm3
-
-// CHECK: 	phsubd	305419896, %mm3
-        	phsubd	0x12345678,%mm3
-
-// CHECK: 	phsubd	%mm3, %mm3
-        	phsubd	%mm3,%mm3
-
-// CHECK: 	phsubd	3735928559(%ebx,%ecx,8), %xmm5
-        	phsubd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	phsubd	69, %xmm5
-        	phsubd	0x45,%xmm5
-
-// CHECK: 	phsubd	32493, %xmm5
-        	phsubd	0x7eed,%xmm5
-
-// CHECK: 	phsubd	3133065982, %xmm5
-        	phsubd	0xbabecafe,%xmm5
-
-// CHECK: 	phsubd	305419896, %xmm5
-        	phsubd	0x12345678,%xmm5
-
-// CHECK: 	phsubd	%xmm5, %xmm5
-        	phsubd	%xmm5,%xmm5
-
-// CHECK: 	phsubsw	3735928559(%ebx,%ecx,8), %mm3
-        	phsubsw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	phsubsw	69, %mm3
-        	phsubsw	0x45,%mm3
-
-// CHECK: 	phsubsw	32493, %mm3
-        	phsubsw	0x7eed,%mm3
-
-// CHECK: 	phsubsw	3133065982, %mm3
-        	phsubsw	0xbabecafe,%mm3
-
-// CHECK: 	phsubsw	305419896, %mm3
-        	phsubsw	0x12345678,%mm3
-
-// CHECK: 	phsubsw	%mm3, %mm3
-        	phsubsw	%mm3,%mm3
-
-// CHECK: 	phsubsw	3735928559(%ebx,%ecx,8), %xmm5
-        	phsubsw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	phsubsw	69, %xmm5
-        	phsubsw	0x45,%xmm5
-
-// CHECK: 	phsubsw	32493, %xmm5
-        	phsubsw	0x7eed,%xmm5
-
-// CHECK: 	phsubsw	3133065982, %xmm5
-        	phsubsw	0xbabecafe,%xmm5
-
-// CHECK: 	phsubsw	305419896, %xmm5
-        	phsubsw	0x12345678,%xmm5
-
-// CHECK: 	phsubsw	%xmm5, %xmm5
-        	phsubsw	%xmm5,%xmm5
-
-// CHECK: 	pmaddubsw	3735928559(%ebx,%ecx,8), %mm3
-        	pmaddubsw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pmaddubsw	69, %mm3
-        	pmaddubsw	0x45,%mm3
-
-// CHECK: 	pmaddubsw	32493, %mm3
-        	pmaddubsw	0x7eed,%mm3
-
-// CHECK: 	pmaddubsw	3133065982, %mm3
-        	pmaddubsw	0xbabecafe,%mm3
-
-// CHECK: 	pmaddubsw	305419896, %mm3
-        	pmaddubsw	0x12345678,%mm3
-
-// CHECK: 	pmaddubsw	%mm3, %mm3
-        	pmaddubsw	%mm3,%mm3
-
-// CHECK: 	pmaddubsw	3735928559(%ebx,%ecx,8), %xmm5
-        	pmaddubsw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmaddubsw	69, %xmm5
-        	pmaddubsw	0x45,%xmm5
-
-// CHECK: 	pmaddubsw	32493, %xmm5
-        	pmaddubsw	0x7eed,%xmm5
-
-// CHECK: 	pmaddubsw	3133065982, %xmm5
-        	pmaddubsw	0xbabecafe,%xmm5
-
-// CHECK: 	pmaddubsw	305419896, %xmm5
-        	pmaddubsw	0x12345678,%xmm5
-
-// CHECK: 	pmaddubsw	%xmm5, %xmm5
-        	pmaddubsw	%xmm5,%xmm5
-
-// CHECK: 	pmulhrsw	3735928559(%ebx,%ecx,8), %mm3
-        	pmulhrsw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pmulhrsw	69, %mm3
-        	pmulhrsw	0x45,%mm3
-
-// CHECK: 	pmulhrsw	32493, %mm3
-        	pmulhrsw	0x7eed,%mm3
-
-// CHECK: 	pmulhrsw	3133065982, %mm3
-        	pmulhrsw	0xbabecafe,%mm3
-
-// CHECK: 	pmulhrsw	305419896, %mm3
-        	pmulhrsw	0x12345678,%mm3
-
-// CHECK: 	pmulhrsw	%mm3, %mm3
-        	pmulhrsw	%mm3,%mm3
-
-// CHECK: 	pmulhrsw	3735928559(%ebx,%ecx,8), %xmm5
-        	pmulhrsw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmulhrsw	69, %xmm5
-        	pmulhrsw	0x45,%xmm5
-
-// CHECK: 	pmulhrsw	32493, %xmm5
-        	pmulhrsw	0x7eed,%xmm5
-
-// CHECK: 	pmulhrsw	3133065982, %xmm5
-        	pmulhrsw	0xbabecafe,%xmm5
-
-// CHECK: 	pmulhrsw	305419896, %xmm5
-        	pmulhrsw	0x12345678,%xmm5
-
-// CHECK: 	pmulhrsw	%xmm5, %xmm5
-        	pmulhrsw	%xmm5,%xmm5
-
-// CHECK: 	pshufb	3735928559(%ebx,%ecx,8), %mm3
-        	pshufb	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pshufb	69, %mm3
-        	pshufb	0x45,%mm3
-
-// CHECK: 	pshufb	32493, %mm3
-        	pshufb	0x7eed,%mm3
-
-// CHECK: 	pshufb	3133065982, %mm3
-        	pshufb	0xbabecafe,%mm3
-
-// CHECK: 	pshufb	305419896, %mm3
-        	pshufb	0x12345678,%mm3
-
-// CHECK: 	pshufb	%mm3, %mm3
-        	pshufb	%mm3,%mm3
-
-// CHECK: 	pshufb	3735928559(%ebx,%ecx,8), %xmm5
-        	pshufb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pshufb	69, %xmm5
-        	pshufb	0x45,%xmm5
-
-// CHECK: 	pshufb	32493, %xmm5
-        	pshufb	0x7eed,%xmm5
-
-// CHECK: 	pshufb	3133065982, %xmm5
-        	pshufb	0xbabecafe,%xmm5
-
-// CHECK: 	pshufb	305419896, %xmm5
-        	pshufb	0x12345678,%xmm5
-
-// CHECK: 	pshufb	%xmm5, %xmm5
-        	pshufb	%xmm5,%xmm5
-
-// CHECK: 	psignb	3735928559(%ebx,%ecx,8), %mm3
-        	psignb	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psignb	69, %mm3
-        	psignb	0x45,%mm3
-
-// CHECK: 	psignb	32493, %mm3
-        	psignb	0x7eed,%mm3
-
-// CHECK: 	psignb	3133065982, %mm3
-        	psignb	0xbabecafe,%mm3
-
-// CHECK: 	psignb	305419896, %mm3
-        	psignb	0x12345678,%mm3
-
-// CHECK: 	psignb	%mm3, %mm3
-        	psignb	%mm3,%mm3
-
-// CHECK: 	psignb	3735928559(%ebx,%ecx,8), %xmm5
-        	psignb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psignb	69, %xmm5
-        	psignb	0x45,%xmm5
-
-// CHECK: 	psignb	32493, %xmm5
-        	psignb	0x7eed,%xmm5
-
-// CHECK: 	psignb	3133065982, %xmm5
-        	psignb	0xbabecafe,%xmm5
-
-// CHECK: 	psignb	305419896, %xmm5
-        	psignb	0x12345678,%xmm5
-
-// CHECK: 	psignb	%xmm5, %xmm5
-        	psignb	%xmm5,%xmm5
-
-// CHECK: 	psignw	3735928559(%ebx,%ecx,8), %mm3
-        	psignw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psignw	69, %mm3
-        	psignw	0x45,%mm3
-
-// CHECK: 	psignw	32493, %mm3
-        	psignw	0x7eed,%mm3
-
-// CHECK: 	psignw	3133065982, %mm3
-        	psignw	0xbabecafe,%mm3
-
-// CHECK: 	psignw	305419896, %mm3
-        	psignw	0x12345678,%mm3
-
-// CHECK: 	psignw	%mm3, %mm3
-        	psignw	%mm3,%mm3
-
-// CHECK: 	psignw	3735928559(%ebx,%ecx,8), %xmm5
-        	psignw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psignw	69, %xmm5
-        	psignw	0x45,%xmm5
-
-// CHECK: 	psignw	32493, %xmm5
-        	psignw	0x7eed,%xmm5
-
-// CHECK: 	psignw	3133065982, %xmm5
-        	psignw	0xbabecafe,%xmm5
-
-// CHECK: 	psignw	305419896, %xmm5
-        	psignw	0x12345678,%xmm5
-
-// CHECK: 	psignw	%xmm5, %xmm5
-        	psignw	%xmm5,%xmm5
-
-// CHECK: 	psignd	3735928559(%ebx,%ecx,8), %mm3
-        	psignd	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	psignd	69, %mm3
-        	psignd	0x45,%mm3
-
-// CHECK: 	psignd	32493, %mm3
-        	psignd	0x7eed,%mm3
-
-// CHECK: 	psignd	3133065982, %mm3
-        	psignd	0xbabecafe,%mm3
-
-// CHECK: 	psignd	305419896, %mm3
-        	psignd	0x12345678,%mm3
-
-// CHECK: 	psignd	%mm3, %mm3
-        	psignd	%mm3,%mm3
-
-// CHECK: 	psignd	3735928559(%ebx,%ecx,8), %xmm5
-        	psignd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	psignd	69, %xmm5
-        	psignd	0x45,%xmm5
-
-// CHECK: 	psignd	32493, %xmm5
-        	psignd	0x7eed,%xmm5
-
-// CHECK: 	psignd	3133065982, %xmm5
-        	psignd	0xbabecafe,%xmm5
-
-// CHECK: 	psignd	305419896, %xmm5
-        	psignd	0x12345678,%xmm5
-
-// CHECK: 	psignd	%xmm5, %xmm5
-        	psignd	%xmm5,%xmm5
-
-// CHECK: 	pabsb	3735928559(%ebx,%ecx,8), %mm3
-        	pabsb	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pabsb	69, %mm3
-        	pabsb	0x45,%mm3
-
-// CHECK: 	pabsb	32493, %mm3
-        	pabsb	0x7eed,%mm3
-
-// CHECK: 	pabsb	3133065982, %mm3
-        	pabsb	0xbabecafe,%mm3
-
-// CHECK: 	pabsb	305419896, %mm3
-        	pabsb	0x12345678,%mm3
-
-// CHECK: 	pabsb	%mm3, %mm3
-        	pabsb	%mm3,%mm3
-
-// CHECK: 	pabsb	3735928559(%ebx,%ecx,8), %xmm5
-        	pabsb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pabsb	69, %xmm5
-        	pabsb	0x45,%xmm5
-
-// CHECK: 	pabsb	32493, %xmm5
-        	pabsb	0x7eed,%xmm5
-
-// CHECK: 	pabsb	3133065982, %xmm5
-        	pabsb	0xbabecafe,%xmm5
-
-// CHECK: 	pabsb	305419896, %xmm5
-        	pabsb	0x12345678,%xmm5
-
-// CHECK: 	pabsb	%xmm5, %xmm5
-        	pabsb	%xmm5,%xmm5
-
-// CHECK: 	pabsw	3735928559(%ebx,%ecx,8), %mm3
-        	pabsw	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pabsw	69, %mm3
-        	pabsw	0x45,%mm3
-
-// CHECK: 	pabsw	32493, %mm3
-        	pabsw	0x7eed,%mm3
-
-// CHECK: 	pabsw	3133065982, %mm3
-        	pabsw	0xbabecafe,%mm3
-
-// CHECK: 	pabsw	305419896, %mm3
-        	pabsw	0x12345678,%mm3
-
-// CHECK: 	pabsw	%mm3, %mm3
-        	pabsw	%mm3,%mm3
-
-// CHECK: 	pabsw	3735928559(%ebx,%ecx,8), %xmm5
-        	pabsw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pabsw	69, %xmm5
-        	pabsw	0x45,%xmm5
-
-// CHECK: 	pabsw	32493, %xmm5
-        	pabsw	0x7eed,%xmm5
-
-// CHECK: 	pabsw	3133065982, %xmm5
-        	pabsw	0xbabecafe,%xmm5
-
-// CHECK: 	pabsw	305419896, %xmm5
-        	pabsw	0x12345678,%xmm5
-
-// CHECK: 	pabsw	%xmm5, %xmm5
-        	pabsw	%xmm5,%xmm5
-
-// CHECK: 	pabsd	3735928559(%ebx,%ecx,8), %mm3
-        	pabsd	0xdeadbeef(%ebx,%ecx,8),%mm3
-
-// CHECK: 	pabsd	69, %mm3
-        	pabsd	0x45,%mm3
-
-// CHECK: 	pabsd	32493, %mm3
-        	pabsd	0x7eed,%mm3
-
-// CHECK: 	pabsd	3133065982, %mm3
-        	pabsd	0xbabecafe,%mm3
-
-// CHECK: 	pabsd	305419896, %mm3
-        	pabsd	0x12345678,%mm3
-
-// CHECK: 	pabsd	%mm3, %mm3
-        	pabsd	%mm3,%mm3
-
-// CHECK: 	pabsd	3735928559(%ebx,%ecx,8), %xmm5
-        	pabsd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pabsd	69, %xmm5
-        	pabsd	0x45,%xmm5
-
-// CHECK: 	pabsd	32493, %xmm5
-        	pabsd	0x7eed,%xmm5
-
-// CHECK: 	pabsd	3133065982, %xmm5
-        	pabsd	0xbabecafe,%xmm5
-
-// CHECK: 	pabsd	305419896, %xmm5
-        	pabsd	0x12345678,%xmm5
-
-// CHECK: 	pabsd	%xmm5, %xmm5
-        	pabsd	%xmm5,%xmm5
-
-// CHECK: 	femms
-        	femms
-
-// CHECK: 	movntdqa	3735928559(%ebx,%ecx,8), %xmm5
-        	movntdqa	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	movntdqa	69, %xmm5
-        	movntdqa	0x45,%xmm5
-
-// CHECK: 	movntdqa	32493, %xmm5
-        	movntdqa	0x7eed,%xmm5
-
-// CHECK: 	movntdqa	3133065982, %xmm5
-        	movntdqa	0xbabecafe,%xmm5
-
-// CHECK: 	movntdqa	305419896, %xmm5
-        	movntdqa	0x12345678,%xmm5
-
-// CHECK: 	packusdw	3735928559(%ebx,%ecx,8), %xmm5
-        	packusdw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	packusdw	69, %xmm5
-        	packusdw	0x45,%xmm5
-
-// CHECK: 	packusdw	32493, %xmm5
-        	packusdw	0x7eed,%xmm5
-
-// CHECK: 	packusdw	3133065982, %xmm5
-        	packusdw	0xbabecafe,%xmm5
-
-// CHECK: 	packusdw	305419896, %xmm5
-        	packusdw	0x12345678,%xmm5
-
-// CHECK: 	packusdw	%xmm5, %xmm5
-        	packusdw	%xmm5,%xmm5
-
-// CHECK: 	pcmpeqq	3735928559(%ebx,%ecx,8), %xmm5
-        	pcmpeqq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pcmpeqq	69, %xmm5
-        	pcmpeqq	0x45,%xmm5
-
-// CHECK: 	pcmpeqq	32493, %xmm5
-        	pcmpeqq	0x7eed,%xmm5
-
-// CHECK: 	pcmpeqq	3133065982, %xmm5
-        	pcmpeqq	0xbabecafe,%xmm5
-
-// CHECK: 	pcmpeqq	305419896, %xmm5
-        	pcmpeqq	0x12345678,%xmm5
-
-// CHECK: 	pcmpeqq	%xmm5, %xmm5
-        	pcmpeqq	%xmm5,%xmm5
-
-// CHECK: 	phminposuw	3735928559(%ebx,%ecx,8), %xmm5
-        	phminposuw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	phminposuw	69, %xmm5
-        	phminposuw	0x45,%xmm5
-
-// CHECK: 	phminposuw	32493, %xmm5
-        	phminposuw	0x7eed,%xmm5
-
-// CHECK: 	phminposuw	3133065982, %xmm5
-        	phminposuw	0xbabecafe,%xmm5
-
-// CHECK: 	phminposuw	305419896, %xmm5
-        	phminposuw	0x12345678,%xmm5
-
-// CHECK: 	phminposuw	%xmm5, %xmm5
-        	phminposuw	%xmm5,%xmm5
-
-// CHECK: 	pmaxsb	3735928559(%ebx,%ecx,8), %xmm5
-        	pmaxsb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmaxsb	69, %xmm5
-        	pmaxsb	0x45,%xmm5
-
-// CHECK: 	pmaxsb	32493, %xmm5
-        	pmaxsb	0x7eed,%xmm5
-
-// CHECK: 	pmaxsb	3133065982, %xmm5
-        	pmaxsb	0xbabecafe,%xmm5
-
-// CHECK: 	pmaxsb	305419896, %xmm5
-        	pmaxsb	0x12345678,%xmm5
-
-// CHECK: 	pmaxsb	%xmm5, %xmm5
-        	pmaxsb	%xmm5,%xmm5
-
-// CHECK: 	pmaxsd	3735928559(%ebx,%ecx,8), %xmm5
-        	pmaxsd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmaxsd	69, %xmm5
-        	pmaxsd	0x45,%xmm5
-
-// CHECK: 	pmaxsd	32493, %xmm5
-        	pmaxsd	0x7eed,%xmm5
-
-// CHECK: 	pmaxsd	3133065982, %xmm5
-        	pmaxsd	0xbabecafe,%xmm5
-
-// CHECK: 	pmaxsd	305419896, %xmm5
-        	pmaxsd	0x12345678,%xmm5
-
-// CHECK: 	pmaxsd	%xmm5, %xmm5
-        	pmaxsd	%xmm5,%xmm5
-
-// CHECK: 	pmaxud	3735928559(%ebx,%ecx,8), %xmm5
-        	pmaxud	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmaxud	69, %xmm5
-        	pmaxud	0x45,%xmm5
-
-// CHECK: 	pmaxud	32493, %xmm5
-        	pmaxud	0x7eed,%xmm5
-
-// CHECK: 	pmaxud	3133065982, %xmm5
-        	pmaxud	0xbabecafe,%xmm5
-
-// CHECK: 	pmaxud	305419896, %xmm5
-        	pmaxud	0x12345678,%xmm5
-
-// CHECK: 	pmaxud	%xmm5, %xmm5
-        	pmaxud	%xmm5,%xmm5
-
-// CHECK: 	pmaxuw	3735928559(%ebx,%ecx,8), %xmm5
-        	pmaxuw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmaxuw	69, %xmm5
-        	pmaxuw	0x45,%xmm5
-
-// CHECK: 	pmaxuw	32493, %xmm5
-        	pmaxuw	0x7eed,%xmm5
-
-// CHECK: 	pmaxuw	3133065982, %xmm5
-        	pmaxuw	0xbabecafe,%xmm5
-
-// CHECK: 	pmaxuw	305419896, %xmm5
-        	pmaxuw	0x12345678,%xmm5
-
-// CHECK: 	pmaxuw	%xmm5, %xmm5
-        	pmaxuw	%xmm5,%xmm5
-
-// CHECK: 	pminsb	3735928559(%ebx,%ecx,8), %xmm5
-        	pminsb	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pminsb	69, %xmm5
-        	pminsb	0x45,%xmm5
-
-// CHECK: 	pminsb	32493, %xmm5
-        	pminsb	0x7eed,%xmm5
-
-// CHECK: 	pminsb	3133065982, %xmm5
-        	pminsb	0xbabecafe,%xmm5
-
-// CHECK: 	pminsb	305419896, %xmm5
-        	pminsb	0x12345678,%xmm5
-
-// CHECK: 	pminsb	%xmm5, %xmm5
-        	pminsb	%xmm5,%xmm5
-
-// CHECK: 	pminsd	3735928559(%ebx,%ecx,8), %xmm5
-        	pminsd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pminsd	69, %xmm5
-        	pminsd	0x45,%xmm5
-
-// CHECK: 	pminsd	32493, %xmm5
-        	pminsd	0x7eed,%xmm5
-
-// CHECK: 	pminsd	3133065982, %xmm5
-        	pminsd	0xbabecafe,%xmm5
-
-// CHECK: 	pminsd	305419896, %xmm5
-        	pminsd	0x12345678,%xmm5
-
-// CHECK: 	pminsd	%xmm5, %xmm5
-        	pminsd	%xmm5,%xmm5
-
-// CHECK: 	pminud	3735928559(%ebx,%ecx,8), %xmm5
-        	pminud	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pminud	69, %xmm5
-        	pminud	0x45,%xmm5
-
-// CHECK: 	pminud	32493, %xmm5
-        	pminud	0x7eed,%xmm5
-
-// CHECK: 	pminud	3133065982, %xmm5
-        	pminud	0xbabecafe,%xmm5
-
-// CHECK: 	pminud	305419896, %xmm5
-        	pminud	0x12345678,%xmm5
-
-// CHECK: 	pminud	%xmm5, %xmm5
-        	pminud	%xmm5,%xmm5
-
-// CHECK: 	pminuw	3735928559(%ebx,%ecx,8), %xmm5
-        	pminuw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pminuw	69, %xmm5
-        	pminuw	0x45,%xmm5
-
-// CHECK: 	pminuw	32493, %xmm5
-        	pminuw	0x7eed,%xmm5
-
-// CHECK: 	pminuw	3133065982, %xmm5
-        	pminuw	0xbabecafe,%xmm5
-
-// CHECK: 	pminuw	305419896, %xmm5
-        	pminuw	0x12345678,%xmm5
-
-// CHECK: 	pminuw	%xmm5, %xmm5
-        	pminuw	%xmm5,%xmm5
-
-// CHECK: 	pmovsxbw	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovsxbw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovsxbw	69, %xmm5
-        	pmovsxbw	0x45,%xmm5
-
-// CHECK: 	pmovsxbw	32493, %xmm5
-        	pmovsxbw	0x7eed,%xmm5
-
-// CHECK: 	pmovsxbw	3133065982, %xmm5
-        	pmovsxbw	0xbabecafe,%xmm5
-
-// CHECK: 	pmovsxbw	305419896, %xmm5
-        	pmovsxbw	0x12345678,%xmm5
-
-// CHECK: 	pmovsxbw	%xmm5, %xmm5
-        	pmovsxbw	%xmm5,%xmm5
-
-// CHECK: 	pmovsxbd	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovsxbd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovsxbd	69, %xmm5
-        	pmovsxbd	0x45,%xmm5
-
-// CHECK: 	pmovsxbd	32493, %xmm5
-        	pmovsxbd	0x7eed,%xmm5
-
-// CHECK: 	pmovsxbd	3133065982, %xmm5
-        	pmovsxbd	0xbabecafe,%xmm5
-
-// CHECK: 	pmovsxbd	305419896, %xmm5
-        	pmovsxbd	0x12345678,%xmm5
-
-// CHECK: 	pmovsxbd	%xmm5, %xmm5
-        	pmovsxbd	%xmm5,%xmm5
-
-// CHECK: 	pmovsxbq	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovsxbq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovsxbq	69, %xmm5
-        	pmovsxbq	0x45,%xmm5
-
-// CHECK: 	pmovsxbq	32493, %xmm5
-        	pmovsxbq	0x7eed,%xmm5
-
-// CHECK: 	pmovsxbq	3133065982, %xmm5
-        	pmovsxbq	0xbabecafe,%xmm5
-
-// CHECK: 	pmovsxbq	305419896, %xmm5
-        	pmovsxbq	0x12345678,%xmm5
-
-// CHECK: 	pmovsxbq	%xmm5, %xmm5
-        	pmovsxbq	%xmm5,%xmm5
-
-// CHECK: 	pmovsxwd	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovsxwd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovsxwd	69, %xmm5
-        	pmovsxwd	0x45,%xmm5
-
-// CHECK: 	pmovsxwd	32493, %xmm5
-        	pmovsxwd	0x7eed,%xmm5
-
-// CHECK: 	pmovsxwd	3133065982, %xmm5
-        	pmovsxwd	0xbabecafe,%xmm5
-
-// CHECK: 	pmovsxwd	305419896, %xmm5
-        	pmovsxwd	0x12345678,%xmm5
-
-// CHECK: 	pmovsxwd	%xmm5, %xmm5
-        	pmovsxwd	%xmm5,%xmm5
-
-// CHECK: 	pmovsxwq	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovsxwq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovsxwq	69, %xmm5
-        	pmovsxwq	0x45,%xmm5
-
-// CHECK: 	pmovsxwq	32493, %xmm5
-        	pmovsxwq	0x7eed,%xmm5
-
-// CHECK: 	pmovsxwq	3133065982, %xmm5
-        	pmovsxwq	0xbabecafe,%xmm5
-
-// CHECK: 	pmovsxwq	305419896, %xmm5
-        	pmovsxwq	0x12345678,%xmm5
-
-// CHECK: 	pmovsxwq	%xmm5, %xmm5
-        	pmovsxwq	%xmm5,%xmm5
-
-// CHECK: 	pmovsxdq	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovsxdq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovsxdq	69, %xmm5
-        	pmovsxdq	0x45,%xmm5
-
-// CHECK: 	pmovsxdq	32493, %xmm5
-        	pmovsxdq	0x7eed,%xmm5
-
-// CHECK: 	pmovsxdq	3133065982, %xmm5
-        	pmovsxdq	0xbabecafe,%xmm5
-
-// CHECK: 	pmovsxdq	305419896, %xmm5
-        	pmovsxdq	0x12345678,%xmm5
-
-// CHECK: 	pmovsxdq	%xmm5, %xmm5
-        	pmovsxdq	%xmm5,%xmm5
-
-// CHECK: 	pmovzxbw	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovzxbw	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovzxbw	69, %xmm5
-        	pmovzxbw	0x45,%xmm5
-
-// CHECK: 	pmovzxbw	32493, %xmm5
-        	pmovzxbw	0x7eed,%xmm5
-
-// CHECK: 	pmovzxbw	3133065982, %xmm5
-        	pmovzxbw	0xbabecafe,%xmm5
-
-// CHECK: 	pmovzxbw	305419896, %xmm5
-        	pmovzxbw	0x12345678,%xmm5
-
-// CHECK: 	pmovzxbw	%xmm5, %xmm5
-        	pmovzxbw	%xmm5,%xmm5
-
-// CHECK: 	pmovzxbd	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovzxbd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovzxbd	69, %xmm5
-        	pmovzxbd	0x45,%xmm5
-
-// CHECK: 	pmovzxbd	32493, %xmm5
-        	pmovzxbd	0x7eed,%xmm5
-
-// CHECK: 	pmovzxbd	3133065982, %xmm5
-        	pmovzxbd	0xbabecafe,%xmm5
-
-// CHECK: 	pmovzxbd	305419896, %xmm5
-        	pmovzxbd	0x12345678,%xmm5
-
-// CHECK: 	pmovzxbd	%xmm5, %xmm5
-        	pmovzxbd	%xmm5,%xmm5
-
-// CHECK: 	pmovzxbq	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovzxbq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovzxbq	69, %xmm5
-        	pmovzxbq	0x45,%xmm5
-
-// CHECK: 	pmovzxbq	32493, %xmm5
-        	pmovzxbq	0x7eed,%xmm5
-
-// CHECK: 	pmovzxbq	3133065982, %xmm5
-        	pmovzxbq	0xbabecafe,%xmm5
-
-// CHECK: 	pmovzxbq	305419896, %xmm5
-        	pmovzxbq	0x12345678,%xmm5
-
-// CHECK: 	pmovzxbq	%xmm5, %xmm5
-        	pmovzxbq	%xmm5,%xmm5
-
-// CHECK: 	pmovzxwd	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovzxwd	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovzxwd	69, %xmm5
-        	pmovzxwd	0x45,%xmm5
-
-// CHECK: 	pmovzxwd	32493, %xmm5
-        	pmovzxwd	0x7eed,%xmm5
-
-// CHECK: 	pmovzxwd	3133065982, %xmm5
-        	pmovzxwd	0xbabecafe,%xmm5
-
-// CHECK: 	pmovzxwd	305419896, %xmm5
-        	pmovzxwd	0x12345678,%xmm5
-
-// CHECK: 	pmovzxwd	%xmm5, %xmm5
-        	pmovzxwd	%xmm5,%xmm5
-
-// CHECK: 	pmovzxwq	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovzxwq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovzxwq	69, %xmm5
-        	pmovzxwq	0x45,%xmm5
-
-// CHECK: 	pmovzxwq	32493, %xmm5
-        	pmovzxwq	0x7eed,%xmm5
-
-// CHECK: 	pmovzxwq	3133065982, %xmm5
-        	pmovzxwq	0xbabecafe,%xmm5
-
-// CHECK: 	pmovzxwq	305419896, %xmm5
-        	pmovzxwq	0x12345678,%xmm5
-
-// CHECK: 	pmovzxwq	%xmm5, %xmm5
-        	pmovzxwq	%xmm5,%xmm5
-
-// CHECK: 	pmovzxdq	3735928559(%ebx,%ecx,8), %xmm5
-        	pmovzxdq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmovzxdq	69, %xmm5
-        	pmovzxdq	0x45,%xmm5
-
-// CHECK: 	pmovzxdq	32493, %xmm5
-        	pmovzxdq	0x7eed,%xmm5
-
-// CHECK: 	pmovzxdq	3133065982, %xmm5
-        	pmovzxdq	0xbabecafe,%xmm5
-
-// CHECK: 	pmovzxdq	305419896, %xmm5
-        	pmovzxdq	0x12345678,%xmm5
-
-// CHECK: 	pmovzxdq	%xmm5, %xmm5
-        	pmovzxdq	%xmm5,%xmm5
-
-// CHECK: 	pmuldq	3735928559(%ebx,%ecx,8), %xmm5
-        	pmuldq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmuldq	69, %xmm5
-        	pmuldq	0x45,%xmm5
-
-// CHECK: 	pmuldq	32493, %xmm5
-        	pmuldq	0x7eed,%xmm5
-
-// CHECK: 	pmuldq	3133065982, %xmm5
-        	pmuldq	0xbabecafe,%xmm5
-
-// CHECK: 	pmuldq	305419896, %xmm5
-        	pmuldq	0x12345678,%xmm5
-
-// CHECK: 	pmuldq	%xmm5, %xmm5
-        	pmuldq	%xmm5,%xmm5
-
-// CHECK: 	pmulld	3735928559(%ebx,%ecx,8), %xmm5
-        	pmulld	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pmulld	69, %xmm5
-        	pmulld	0x45,%xmm5
-
-// CHECK: 	pmulld	32493, %xmm5
-        	pmulld	0x7eed,%xmm5
-
-// CHECK: 	pmulld	3133065982, %xmm5
-        	pmulld	0xbabecafe,%xmm5
-
-// CHECK: 	pmulld	305419896, %xmm5
-        	pmulld	0x12345678,%xmm5
-
-// CHECK: 	pmulld	%xmm5, %xmm5
-        	pmulld	%xmm5,%xmm5
-
-// CHECK: 	ptest 	3735928559(%ebx,%ecx,8), %xmm5
-        	ptest	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	ptest 	69, %xmm5
-        	ptest	0x45,%xmm5
-
-// CHECK: 	ptest 	32493, %xmm5
-        	ptest	0x7eed,%xmm5
-
-// CHECK: 	ptest 	3133065982, %xmm5
-        	ptest	0xbabecafe,%xmm5
-
-// CHECK: 	ptest 	305419896, %xmm5
-        	ptest	0x12345678,%xmm5
-
-// CHECK: 	ptest 	%xmm5, %xmm5
-        	ptest	%xmm5,%xmm5
-
-// CHECK: 	crc32b 	%bl, %eax
-                crc32b %bl, %eax
-
-// CHECK: 	crc32b 	4(%ebx), %eax
-                crc32b 4(%ebx), %eax
-
-// CHECK: 	crc32w 	%bx, %eax
-                crc32w %bx, %eax
-
-// CHECK: 	crc32w 	4(%ebx), %eax
-                crc32w 4(%ebx), %eax
-
-// CHECK: 	crc32l 	%ebx, %eax
-                crc32l %ebx, %eax
-
-// CHECK: 	crc32l 	4(%ebx), %eax
-                crc32l 4(%ebx), %eax
-
-// CHECK: 	crc32l 	3735928559(%ebx,%ecx,8), %ecx
-                crc32l 0xdeadbeef(%ebx,%ecx,8),%ecx
-
-// CHECK: 	crc32l 	69, %ecx
-                crc32l 0x45,%ecx
-
-// CHECK: 	crc32l 	32493, %ecx
-                crc32l 0x7eed,%ecx
-
-// CHECK: 	crc32l 	3133065982, %ecx
-                crc32l 0xbabecafe,%ecx
-
-// CHECK: 	crc32l 	%ecx, %ecx
-                crc32l %ecx,%ecx
-
-// CHECK: 	pcmpgtq	3735928559(%ebx,%ecx,8), %xmm5
-        	pcmpgtq	0xdeadbeef(%ebx,%ecx,8),%xmm5
-
-// CHECK: 	pcmpgtq	69, %xmm5
-        	pcmpgtq	0x45,%xmm5
-
-// CHECK: 	pcmpgtq	32493, %xmm5
-        	pcmpgtq	0x7eed,%xmm5
-
-// CHECK: 	pcmpgtq	3133065982, %xmm5
-        	pcmpgtq	0xbabecafe,%xmm5
-
-// CHECK: 	pcmpgtq	305419896, %xmm5
-        	pcmpgtq	0x12345678,%xmm5
-
-// CHECK: 	pcmpgtq	%xmm5, %xmm5
-        	pcmpgtq	%xmm5,%xmm5
-
-// CHECK: 	aesimc	%xmm0, %xmm1
-                aesimc %xmm0,%xmm1
-
-// CHECK: 	aesimc	(%eax), %xmm1
-                aesimc (%eax),%xmm1
-
-// CHECK: 	aesenc	%xmm1, %xmm2
-                aesenc %xmm1,%xmm2
-
-// CHECK: 	aesenc	4(%ebx), %xmm2
-                aesenc 4(%ebx),%xmm2
-
-// CHECK: 	aesenclast	%xmm3, %xmm4
-                aesenclast %xmm3,%xmm4
-
-// CHECK: 	aesenclast	4(%edx,%edi), %xmm4
-                aesenclast 4(%edx,%edi),%xmm4
-
-// CHECK: 	aesdec	%xmm5, %xmm6
-                aesdec %xmm5,%xmm6
-
-// CHECK: 	aesdec	4(%ecx,%eax,8), %xmm6
-                aesdec 4(%ecx,%eax,8),%xmm6
-
-// CHECK: 	aesdeclast	%xmm7, %xmm0
-                aesdeclast %xmm7,%xmm0
-
-// CHECK: 	aesdeclast	3405691582, %xmm0
-                aesdeclast 0xcafebabe,%xmm0
-
-// CHECK: 	aeskeygenassist	$125, %xmm1, %xmm2
-                aeskeygenassist $125, %xmm1, %xmm2
-
-// CHECK: 	aeskeygenassist	$125, (%edx,%eax,4), %xmm2
-                aeskeygenassist $125, (%edx,%eax,4), %xmm2
-
 // CHECK:   blendvps	(%eax), %xmm1   # encoding: [0x66,0x0f,0x38,0x14,0x08]
             blendvps (%eax), %xmm1
 // CHECK:   blendvps	%xmm2, %xmm1    # encoding: [0x66,0x0f,0x38,0x14,0xca]
@@ -19622,31 +10520,31 @@
 // immediate. Check both forms here.
 // CHECK: blendps $129, %xmm2, %xmm1
           blendps $0x81, %xmm2, %xmm1
-// CHECK: blendps $-64, %xmm2, %xmm1
+// CHECK: blendps $192, %xmm2, %xmm1
           blendps $-64, %xmm2, %xmm1
 // CHECK: blendpd $129, %xmm2, %xmm1
           blendpd $0x81, %xmm2, %xmm1
-// CHECK: blendpd $-64, %xmm2, %xmm1
+// CHECK: blendpd $192, %xmm2, %xmm1
           blendpd $-64, %xmm2, %xmm1
 // CHECK: pblendw $129, %xmm2, %xmm1
           pblendw $0x81, %xmm2, %xmm1
-// CHECK: pblendw $-64, %xmm2, %xmm1
+// CHECK: pblendw $192, %xmm2, %xmm1
           pblendw $-64, %xmm2, %xmm1
 // CHECK: mpsadbw $129, %xmm2, %xmm1
           mpsadbw $0x81, %xmm2, %xmm1
-// CHECK: mpsadbw $-64, %xmm2, %xmm1
+// CHECK: mpsadbw $192, %xmm2, %xmm1
           mpsadbw $-64, %xmm2, %xmm1
 // CHECK: dpps $129, %xmm2, %xmm1
           dpps $0x81, %xmm2, %xmm1
-// CHECK: dpps $-64, %xmm2, %xmm1
+// CHECK: dpps $192, %xmm2, %xmm1
           dpps $-64, %xmm2, %xmm1
 // CHECK: dppd $129, %xmm2, %xmm1
           dppd $0x81, %xmm2, %xmm1
-// CHECK: dppd $-64, %xmm2, %xmm1
+// CHECK: dppd $192, %xmm2, %xmm1
           dppd $-64, %xmm2, %xmm1
 // CHECK: insertps $129, %xmm2, %xmm1
           insertps $0x81, %xmm2, %xmm1
-// CHECK: insertps $-64, %xmm2, %xmm1
+// CHECK: insertps $192, %xmm2, %xmm1
           insertps $-64, %xmm2, %xmm1
 
 // PR13253 handle implicit optional third argument that must always be xmm0
@@ -19708,3 +10606,139 @@ btc $4, (%eax)
 btcw $4, (%eax)
 btcl $4, (%eax)
 btcq $4, (%eax)
+
+// CHECK: clflushopt	3735928559(%ebx,%ecx,8)
+// CHECK:  encoding: [0x66,0x0f,0xae,0xbc,0xcb,0xef,0xbe,0xad,0xde]
+        	clflushopt	0xdeadbeef(%ebx,%ecx,8)
+
+// CHECK: clflushopt	32493
+// CHECK:  encoding: [0x66,0x0f,0xae,0x3d,0xed,0x7e,0x00,0x00]
+        	clflushopt	0x7eed
+
+// CHECK: clflushopt	3133065982
+// CHECK:  encoding: [0x66,0x0f,0xae,0x3d,0xfe,0xca,0xbe,0xba]
+        	clflushopt	0xbabecafe
+
+// CHECK: clflushopt	305419896
+// CHECK:  encoding: [0x66,0x0f,0xae,0x3d,0x78,0x56,0x34,0x12]
+        	clflushopt	0x12345678
+
+// CHECK: clwb	3735928559(%ebx,%ecx,8)
+// CHECK:  encoding: [0x66,0x0f,0xae,0xb4,0xcb,0xef,0xbe,0xad,0xde]
+        	clwb	0xdeadbeef(%ebx,%ecx,8)
+
+// CHECK: clwb	32493
+// CHECK:  encoding: [0x66,0x0f,0xae,0x35,0xed,0x7e,0x00,0x00]
+        	clwb	0x7eed
+
+// CHECK: clwb	3133065982
+// CHECK:  encoding: [0x66,0x0f,0xae,0x35,0xfe,0xca,0xbe,0xba]
+        	clwb	0xbabecafe
+
+// CHECK: clwb	305419896
+// CHECK:  encoding: [0x66,0x0f,0xae,0x35,0x78,0x56,0x34,0x12]
+        	clwb	0x12345678
+
+// CHECK: pcommit
+// CHECK:  encoding: [0x66,0x0f,0xae,0xf8]
+        	pcommit
+
+// CHECK: xsave	3735928559(%ebx,%ecx,8)
+// CHECK:  encoding: [0x0f,0xae,0xa4,0xcb,0xef,0xbe,0xad,0xde]
+        	xsave	0xdeadbeef(%ebx,%ecx,8)
+
+// CHECK: xsave	32493
+// CHECK:  encoding: [0x0f,0xae,0x25,0xed,0x7e,0x00,0x00]
+        	xsave	0x7eed
+
+// CHECK: xsave	3133065982
+// CHECK:  encoding: [0x0f,0xae,0x25,0xfe,0xca,0xbe,0xba]
+        	xsave	0xbabecafe
+
+// CHECK: xsave	305419896
+// CHECK:  encoding: [0x0f,0xae,0x25,0x78,0x56,0x34,0x12]
+        	xsave	0x12345678
+
+// CHECK: xrstor	3735928559(%ebx,%ecx,8)
+// CHECK:  encoding: [0x0f,0xae,0xac,0xcb,0xef,0xbe,0xad,0xde]
+        	xrstor	0xdeadbeef(%ebx,%ecx,8)
+
+// CHECK: xrstor	32493
+// CHECK:  encoding: [0x0f,0xae,0x2d,0xed,0x7e,0x00,0x00]
+        	xrstor	0x7eed
+
+// CHECK: xrstor	3133065982
+// CHECK:  encoding: [0x0f,0xae,0x2d,0xfe,0xca,0xbe,0xba]
+        	xrstor	0xbabecafe
+
+// CHECK: xrstor	305419896
+// CHECK:  encoding: [0x0f,0xae,0x2d,0x78,0x56,0x34,0x12]
+        	xrstor	0x12345678
+
+// CHECK: xsaveopt	3735928559(%ebx,%ecx,8)
+// CHECK:  encoding: [0x0f,0xae,0xb4,0xcb,0xef,0xbe,0xad,0xde]
+        	xsaveopt	0xdeadbeef(%ebx,%ecx,8)
+
+// CHECK: xsaveopt	32493
+// CHECK:  encoding: [0x0f,0xae,0x35,0xed,0x7e,0x00,0x00]
+        	xsaveopt	0x7eed
+
+// CHECK: xsaveopt	3133065982
+// CHECK:  encoding: [0x0f,0xae,0x35,0xfe,0xca,0xbe,0xba]
+        	xsaveopt	0xbabecafe
+
+// CHECK: xsaveopt	305419896
+// CHECK:  encoding: [0x0f,0xae,0x35,0x78,0x56,0x34,0x12]
+        	xsaveopt	0x12345678
+
+// CHECK: xsaves	3735928559(%ebx,%ecx,8)
+// CHECK:  encoding: [0x0f,0xc7,0xac,0xcb,0xef,0xbe,0xad,0xde]
+        	xsaves	0xdeadbeef(%ebx,%ecx,8)
+
+// CHECK: xsaves	32493
+// CHECK:  encoding: [0x0f,0xc7,0x2d,0xed,0x7e,0x00,0x00]
+        	xsaves	0x7eed
+
+// CHECK: xsaves	3133065982
+// CHECK:  encoding: [0x0f,0xc7,0x2d,0xfe,0xca,0xbe,0xba]
+        	xsaves	0xbabecafe
+
+// CHECK: xsaves	305419896
+// CHECK:  encoding: [0x0f,0xc7,0x2d,0x78,0x56,0x34,0x12]
+        	xsaves	0x12345678
+
+// CHECK: xsavec	3735928559(%ebx,%ecx,8)
+// CHECK:  encoding: [0x0f,0xc7,0xa4,0xcb,0xef,0xbe,0xad,0xde]
+        	xsavec	0xdeadbeef(%ebx,%ecx,8)
+
+// CHECK: xsavec	32493
+// CHECK:  encoding: [0x0f,0xc7,0x25,0xed,0x7e,0x00,0x00]
+        	xsavec	0x7eed
+
+// CHECK: xsavec	3133065982
+// CHECK:  encoding: [0x0f,0xc7,0x25,0xfe,0xca,0xbe,0xba]
+        	xsavec	0xbabecafe
+
+// CHECK: xsavec	305419896
+// CHECK:  encoding: [0x0f,0xc7,0x25,0x78,0x56,0x34,0x12]
+        	xsavec	0x12345678
+
+// CHECK: xrstors	3735928559(%ebx,%ecx,8)
+// CHECK:  encoding: [0x0f,0xc7,0x9c,0xcb,0xef,0xbe,0xad,0xde]
+        	xrstors	0xdeadbeef(%ebx,%ecx,8)
+
+// CHECK: xrstors	32493
+// CHECK:  encoding: [0x0f,0xc7,0x1d,0xed,0x7e,0x00,0x00]
+        	xrstors	0x7eed
+
+// CHECK: xrstors	3133065982
+// CHECK:  encoding: [0x0f,0xc7,0x1d,0xfe,0xca,0xbe,0xba]
+        	xrstors	0xbabecafe
+
+// CHECK: xrstors	305419896
+// CHECK:  encoding: [0x0f,0xc7,0x1d,0x78,0x56,0x34,0x12]
+        	xrstors	0x12345678
+
+// CHECK: getsec
+// CHECK:  encoding: [0x0f,0x37]
+        	getsec
diff --git a/test/MC/X86/x86-32.s b/test/MC/X86/x86-32.s
index bebaa65227f1..56fd658a76ee 100644
--- a/test/MC/X86/x86-32.s
+++ b/test/MC/X86/x86-32.s
@@ -79,7 +79,7 @@
 // CHECK: movl	%eax, -16(%ebp)          # encoding: [0x89,0x45,0xf0]
 	movl	%eax, -16(%ebp)
 
-// CHECK: testb	%bl, %cl                # encoding: [0x84,0xcb]
+// CHECK: testb	%bl, %cl                # encoding: [0x84,0xd9]
         testb %bl, %cl
 
 // CHECK: cmpl	%eax, %ebx              # encoding: [0x39,0xc3]
@@ -289,35 +289,35 @@ cmovnae	%bx,%bx
 
 // Check matching of instructions which embed the SSE comparison code.
 
-// CHECK: cmpps $0, %xmm0, %xmm1
+// CHECK: cmpeqps %xmm0, %xmm1
 // CHECK: encoding: [0x0f,0xc2,0xc8,0x00]
         cmpeqps %xmm0, %xmm1
 
-// CHECK: cmppd $1, %xmm0, %xmm1
+// CHECK: cmpltpd %xmm0, %xmm1
 // CHECK: encoding: [0x66,0x0f,0xc2,0xc8,0x01]
         cmpltpd %xmm0, %xmm1
 
-// CHECK: cmpss $2, %xmm0, %xmm1
+// CHECK: cmpless %xmm0, %xmm1
 // CHECK: encoding: [0xf3,0x0f,0xc2,0xc8,0x02]
         cmpless %xmm0, %xmm1
 
-// CHECK: cmppd $3, %xmm0, %xmm1
+// CHECK: cmpunordpd %xmm0, %xmm1
 // CHECK: encoding: [0x66,0x0f,0xc2,0xc8,0x03]
         cmpunordpd %xmm0, %xmm1
 
-// CHECK: cmpps $4, %xmm0, %xmm1
+// CHECK: cmpneqps %xmm0, %xmm1
 // CHECK: encoding: [0x0f,0xc2,0xc8,0x04]
         cmpneqps %xmm0, %xmm1
 
-// CHECK: cmppd $5, %xmm0, %xmm1
+// CHECK: cmpnltpd %xmm0, %xmm1
 // CHECK: encoding: [0x66,0x0f,0xc2,0xc8,0x05]
         cmpnltpd %xmm0, %xmm1
 
-// CHECK: cmpss $6, %xmm0, %xmm1
+// CHECK: cmpnless %xmm0, %xmm1
 // CHECK: encoding: [0xf3,0x0f,0xc2,0xc8,0x06]
         cmpnless %xmm0, %xmm1
 
-// CHECK: cmpsd $7, %xmm0, %xmm1
+// CHECK: cmpordsd %xmm0, %xmm1
 // CHECK: encoding: [0xf2,0x0f,0xc2,0xc8,0x07]
         cmpordsd %xmm0, %xmm1
 
diff --git a/test/MC/X86/x86-64-avx512bw.s b/test/MC/X86/x86-64-avx512bw.s
index 1abe7776f0c2..ba043da66329 100644
--- a/test/MC/X86/x86-64-avx512bw.s
+++ b/test/MC/X86/x86-64-avx512bw.s
@@ -511,6 +511,78 @@
 // CHECK:  encoding: [0x62,0xe2,0x15,0x40,0x3a,0x9a,0xc0,0xdf,0xff,0xff]
           vpminuw -8256(%rdx), %zmm29, %zmm19
 
+// CHECK: vpmovsxbw %ymm18, %zmm22
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x48,0x20,0xf2]
+          vpmovsxbw %ymm18, %zmm22
+
+// CHECK: vpmovsxbw %ymm18, %zmm22 {%k5}
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x4d,0x20,0xf2]
+          vpmovsxbw %ymm18, %zmm22 {%k5}
+
+// CHECK: vpmovsxbw %ymm18, %zmm22 {%k5} {z}
+// CHECK:  encoding: [0x62,0xa2,0x7d,0xcd,0x20,0xf2]
+          vpmovsxbw %ymm18, %zmm22 {%k5} {z}
+
+// CHECK: vpmovsxbw (%rcx), %zmm22
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x48,0x20,0x31]
+          vpmovsxbw (%rcx), %zmm22
+
+// CHECK: vpmovsxbw 291(%rax,%r14,8), %zmm22
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x48,0x20,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpmovsxbw 291(%rax,%r14,8), %zmm22
+
+// CHECK: vpmovsxbw 4064(%rdx), %zmm22
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x48,0x20,0x72,0x7f]
+          vpmovsxbw 4064(%rdx), %zmm22
+
+// CHECK: vpmovsxbw 4096(%rdx), %zmm22
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x48,0x20,0xb2,0x00,0x10,0x00,0x00]
+          vpmovsxbw 4096(%rdx), %zmm22
+
+// CHECK: vpmovsxbw -4096(%rdx), %zmm22
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x48,0x20,0x72,0x80]
+          vpmovsxbw -4096(%rdx), %zmm22
+
+// CHECK: vpmovsxbw -4128(%rdx), %zmm22
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x48,0x20,0xb2,0xe0,0xef,0xff,0xff]
+          vpmovsxbw -4128(%rdx), %zmm22
+
+// CHECK: vpmovzxbw %ymm26, %zmm24
+// CHECK:  encoding: [0x62,0x02,0x7d,0x48,0x30,0xc2]
+          vpmovzxbw %ymm26, %zmm24
+
+// CHECK: vpmovzxbw %ymm26, %zmm24 {%k4}
+// CHECK:  encoding: [0x62,0x02,0x7d,0x4c,0x30,0xc2]
+          vpmovzxbw %ymm26, %zmm24 {%k4}
+
+// CHECK: vpmovzxbw %ymm26, %zmm24 {%k4} {z}
+// CHECK:  encoding: [0x62,0x02,0x7d,0xcc,0x30,0xc2]
+          vpmovzxbw %ymm26, %zmm24 {%k4} {z}
+
+// CHECK: vpmovzxbw (%rcx), %zmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x30,0x01]
+          vpmovzxbw (%rcx), %zmm24
+
+// CHECK: vpmovzxbw 291(%rax,%r14,8), %zmm24
+// CHECK:  encoding: [0x62,0x22,0x7d,0x48,0x30,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vpmovzxbw 291(%rax,%r14,8), %zmm24
+
+// CHECK: vpmovzxbw 4064(%rdx), %zmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x30,0x42,0x7f]
+          vpmovzxbw 4064(%rdx), %zmm24
+
+// CHECK: vpmovzxbw 4096(%rdx), %zmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x30,0x82,0x00,0x10,0x00,0x00]
+          vpmovzxbw 4096(%rdx), %zmm24
+
+// CHECK: vpmovzxbw -4096(%rdx), %zmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x30,0x42,0x80]
+          vpmovzxbw -4096(%rdx), %zmm24
+
+// CHECK: vpmovzxbw -4128(%rdx), %zmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x30,0x82,0xe0,0xef,0xff,0xff]
+          vpmovzxbw -4128(%rdx), %zmm24
+
 // CHECK: vpmullw %zmm19, %zmm28, %zmm19
 // CHECK:  encoding: [0x62,0xa1,0x1d,0x40,0xd5,0xdb]
           vpmullw %zmm19, %zmm28, %zmm19
@@ -912,6 +984,166 @@
 // CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x9a,0xc0,0xdf,0xff,0xff,0x7b]
           vpcmpb $123, -8256(%rdx), %zmm26, %k3
 
+// CHECK: vpcmpltb %zmm25, %zmm26, %k3
+// CHECK:  encoding: [0x62,0x93,0x2d,0x40,0x3f,0xd9,0x01]
+          vpcmpltb %zmm25, %zmm26, %k3
+
+// CHECK: vpcmpltb %zmm25, %zmm26, %k3 {%k7}
+// CHECK:  encoding: [0x62,0x93,0x2d,0x47,0x3f,0xd9,0x01]
+          vpcmpltb %zmm25, %zmm26, %k3 {%k7}
+
+// CHECK: vpcmpltb (%rcx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x19,0x01]
+          vpcmpltb (%rcx), %zmm26, %k3
+
+// CHECK: vpcmpltb 291(%rax,%r14,8), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xb3,0x2d,0x40,0x3f,0x9c,0xf0,0x23,0x01,0x00,0x00,0x01]
+          vpcmpltb 291(%rax,%r14,8), %zmm26, %k3
+
+// CHECK: vpcmpltb 8128(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x5a,0x7f,0x01]
+          vpcmpltb 8128(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpltb 8192(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x9a,0x00,0x20,0x00,0x00,0x01]
+          vpcmpltb 8192(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpltb -8192(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x5a,0x80,0x01]
+          vpcmpltb -8192(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpltb -8256(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x9a,0xc0,0xdf,0xff,0xff,0x01]
+          vpcmpltb -8256(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpleb %zmm25, %zmm26, %k3
+// CHECK:  encoding: [0x62,0x93,0x2d,0x40,0x3f,0xd9,0x02]
+          vpcmpleb %zmm25, %zmm26, %k3
+
+// CHECK: vpcmpleb %zmm25, %zmm26, %k3 {%k7}
+// CHECK:  encoding: [0x62,0x93,0x2d,0x47,0x3f,0xd9,0x02]
+          vpcmpleb %zmm25, %zmm26, %k3 {%k7}
+
+// CHECK: vpcmpleb (%rcx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x19,0x02]
+          vpcmpleb (%rcx), %zmm26, %k3
+
+// CHECK: vpcmpleb 291(%rax,%r14,8), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xb3,0x2d,0x40,0x3f,0x9c,0xf0,0x23,0x01,0x00,0x00,0x02]
+          vpcmpleb 291(%rax,%r14,8), %zmm26, %k3
+
+// CHECK: vpcmpleb 8128(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x5a,0x7f,0x02]
+          vpcmpleb 8128(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpleb 8192(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x9a,0x00,0x20,0x00,0x00,0x02]
+          vpcmpleb 8192(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpleb -8192(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x5a,0x80,0x02]
+          vpcmpleb -8192(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpleb -8256(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x9a,0xc0,0xdf,0xff,0xff,0x02]
+          vpcmpleb -8256(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpneqb %zmm25, %zmm26, %k3
+// CHECK:  encoding: [0x62,0x93,0x2d,0x40,0x3f,0xd9,0x04]
+          vpcmpneqb %zmm25, %zmm26, %k3
+
+// CHECK: vpcmpneqb %zmm25, %zmm26, %k3 {%k7}
+// CHECK:  encoding: [0x62,0x93,0x2d,0x47,0x3f,0xd9,0x04]
+          vpcmpneqb %zmm25, %zmm26, %k3 {%k7}
+
+// CHECK: vpcmpneqb (%rcx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x19,0x04]
+          vpcmpneqb (%rcx), %zmm26, %k3
+
+// CHECK: vpcmpneqb 291(%rax,%r14,8), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xb3,0x2d,0x40,0x3f,0x9c,0xf0,0x23,0x01,0x00,0x00,0x04]
+          vpcmpneqb 291(%rax,%r14,8), %zmm26, %k3
+
+// CHECK: vpcmpneqb 8128(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x5a,0x7f,0x04]
+          vpcmpneqb 8128(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpneqb 8192(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x9a,0x00,0x20,0x00,0x00,0x04]
+          vpcmpneqb 8192(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpneqb -8192(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x5a,0x80,0x04]
+          vpcmpneqb -8192(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpneqb -8256(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x9a,0xc0,0xdf,0xff,0xff,0x04]
+          vpcmpneqb -8256(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpnltb %zmm25, %zmm26, %k3
+// CHECK:  encoding: [0x62,0x93,0x2d,0x40,0x3f,0xd9,0x05]
+          vpcmpnltb %zmm25, %zmm26, %k3
+
+// CHECK: vpcmpnltb %zmm25, %zmm26, %k3 {%k7}
+// CHECK:  encoding: [0x62,0x93,0x2d,0x47,0x3f,0xd9,0x05]
+          vpcmpnltb %zmm25, %zmm26, %k3 {%k7}
+
+// CHECK: vpcmpnltb (%rcx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x19,0x05]
+          vpcmpnltb (%rcx), %zmm26, %k3
+
+// CHECK: vpcmpnltb 291(%rax,%r14,8), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xb3,0x2d,0x40,0x3f,0x9c,0xf0,0x23,0x01,0x00,0x00,0x05]
+          vpcmpnltb 291(%rax,%r14,8), %zmm26, %k3
+
+// CHECK: vpcmpnltb 8128(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x5a,0x7f,0x05]
+          vpcmpnltb 8128(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpnltb 8192(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x9a,0x00,0x20,0x00,0x00,0x05]
+          vpcmpnltb 8192(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpnltb -8192(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x5a,0x80,0x05]
+          vpcmpnltb -8192(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpnltb -8256(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x9a,0xc0,0xdf,0xff,0xff,0x05]
+          vpcmpnltb -8256(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpnleb %zmm25, %zmm26, %k3
+// CHECK:  encoding: [0x62,0x93,0x2d,0x40,0x3f,0xd9,0x06]
+          vpcmpnleb %zmm25, %zmm26, %k3
+
+// CHECK: vpcmpnleb %zmm25, %zmm26, %k3 {%k7}
+// CHECK:  encoding: [0x62,0x93,0x2d,0x47,0x3f,0xd9,0x06]
+          vpcmpnleb %zmm25, %zmm26, %k3 {%k7}
+
+// CHECK: vpcmpnleb (%rcx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x19,0x06]
+          vpcmpnleb (%rcx), %zmm26, %k3
+
+// CHECK: vpcmpnleb 291(%rax,%r14,8), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xb3,0x2d,0x40,0x3f,0x9c,0xf0,0x23,0x01,0x00,0x00,0x06]
+          vpcmpnleb 291(%rax,%r14,8), %zmm26, %k3
+
+// CHECK: vpcmpnleb 8128(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x5a,0x7f,0x06]
+          vpcmpnleb 8128(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpnleb 8192(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x9a,0x00,0x20,0x00,0x00,0x06]
+          vpcmpnleb 8192(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpnleb -8192(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x5a,0x80,0x06]
+          vpcmpnleb -8192(%rdx), %zmm26, %k3
+
+// CHECK: vpcmpnleb -8256(%rdx), %zmm26, %k3
+// CHECK:  encoding: [0x62,0xf3,0x2d,0x40,0x3f,0x9a,0xc0,0xdf,0xff,0xff,0x06]
+          vpcmpnleb -8256(%rdx), %zmm26, %k3
+
 // CHECK: vpcmpw $171, %zmm25, %zmm29, %k3
 // CHECK:  encoding: [0x62,0x93,0x95,0x40,0x3f,0xd9,0xab]
           vpcmpw $171, %zmm25, %zmm29, %k3
@@ -948,6 +1180,166 @@
 // CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x9a,0xc0,0xdf,0xff,0xff,0x7b]
           vpcmpw $123, -8256(%rdx), %zmm29, %k3
 
+// CHECK: vpcmpltw %zmm25, %zmm29, %k3
+// CHECK:  encoding: [0x62,0x93,0x95,0x40,0x3f,0xd9,0x01]
+          vpcmpltw %zmm25, %zmm29, %k3
+
+// CHECK: vpcmpltw %zmm25, %zmm29, %k3 {%k6}
+// CHECK:  encoding: [0x62,0x93,0x95,0x46,0x3f,0xd9,0x01]
+          vpcmpltw %zmm25, %zmm29, %k3 {%k6}
+
+// CHECK: vpcmpltw (%rcx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x19,0x01]
+          vpcmpltw (%rcx), %zmm29, %k3
+
+// CHECK: vpcmpltw 291(%rax,%r14,8), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xb3,0x95,0x40,0x3f,0x9c,0xf0,0x23,0x01,0x00,0x00,0x01]
+          vpcmpltw 291(%rax,%r14,8), %zmm29, %k3
+
+// CHECK: vpcmpltw 8128(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x5a,0x7f,0x01]
+          vpcmpltw 8128(%rdx), %zmm29, %k3
+
+// CHECK: vpcmpltw 8192(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x9a,0x00,0x20,0x00,0x00,0x01]
+          vpcmpltw 8192(%rdx), %zmm29, %k3
+
+// CHECK: vpcmpltw -8192(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x5a,0x80,0x01]
+          vpcmpltw -8192(%rdx), %zmm29, %k3
+
+// CHECK: vpcmpltw -8256(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x9a,0xc0,0xdf,0xff,0xff,0x01]
+          vpcmpltw -8256(%rdx), %zmm29, %k3
+
+// CHECK: vpcmplew %zmm25, %zmm29, %k3
+// CHECK:  encoding: [0x62,0x93,0x95,0x40,0x3f,0xd9,0x02]
+          vpcmplew %zmm25, %zmm29, %k3
+
+// CHECK: vpcmplew %zmm25, %zmm29, %k3 {%k6}
+// CHECK:  encoding: [0x62,0x93,0x95,0x46,0x3f,0xd9,0x02]
+          vpcmplew %zmm25, %zmm29, %k3 {%k6}
+
+// CHECK: vpcmplew (%rcx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x19,0x02]
+          vpcmplew (%rcx), %zmm29, %k3
+
+// CHECK: vpcmplew 291(%rax,%r14,8), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xb3,0x95,0x40,0x3f,0x9c,0xf0,0x23,0x01,0x00,0x00,0x02]
+          vpcmplew 291(%rax,%r14,8), %zmm29, %k3
+
+// CHECK: vpcmplew 8128(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x5a,0x7f,0x02]
+          vpcmplew 8128(%rdx), %zmm29, %k3
+
+// CHECK: vpcmplew 8192(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x9a,0x00,0x20,0x00,0x00,0x02]
+          vpcmplew 8192(%rdx), %zmm29, %k3
+
+// CHECK: vpcmplew -8192(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x5a,0x80,0x02]
+          vpcmplew -8192(%rdx), %zmm29, %k3
+
+// CHECK: vpcmplew -8256(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x9a,0xc0,0xdf,0xff,0xff,0x02]
+          vpcmplew -8256(%rdx), %zmm29, %k3
+
+// CHECK: vpcmpneqw %zmm25, %zmm29, %k3
+// CHECK:  encoding: [0x62,0x93,0x95,0x40,0x3f,0xd9,0x04]
+          vpcmpneqw %zmm25, %zmm29, %k3
+
+// CHECK: vpcmpneqw %zmm25, %zmm29, %k3 {%k6}
+// CHECK:  encoding: [0x62,0x93,0x95,0x46,0x3f,0xd9,0x04]
+          vpcmpneqw %zmm25, %zmm29, %k3 {%k6}
+
+// CHECK: vpcmpneqw (%rcx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x19,0x04]
+          vpcmpneqw (%rcx), %zmm29, %k3
+
+// CHECK: vpcmpneqw 291(%rax,%r14,8), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xb3,0x95,0x40,0x3f,0x9c,0xf0,0x23,0x01,0x00,0x00,0x04]
+          vpcmpneqw 291(%rax,%r14,8), %zmm29, %k3
+
+// CHECK: vpcmpneqw 8128(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x5a,0x7f,0x04]
+          vpcmpneqw 8128(%rdx), %zmm29, %k3
+
+// CHECK: vpcmpneqw 8192(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x9a,0x00,0x20,0x00,0x00,0x04]
+          vpcmpneqw 8192(%rdx), %zmm29, %k3
+
+// CHECK: vpcmpneqw -8192(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x5a,0x80,0x04]
+          vpcmpneqw -8192(%rdx), %zmm29, %k3
+
+// CHECK: vpcmpneqw -8256(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x9a,0xc0,0xdf,0xff,0xff,0x04]
+          vpcmpneqw -8256(%rdx), %zmm29, %k3
+
+// CHECK: vpcmpnltw %zmm25, %zmm29, %k3
+// CHECK:  encoding: [0x62,0x93,0x95,0x40,0x3f,0xd9,0x05]
+          vpcmpnltw %zmm25, %zmm29, %k3
+
+// CHECK: vpcmpnltw %zmm25, %zmm29, %k3 {%k6}
+// CHECK:  encoding: [0x62,0x93,0x95,0x46,0x3f,0xd9,0x05]
+          vpcmpnltw %zmm25, %zmm29, %k3 {%k6}
+
+// CHECK: vpcmpnltw (%rcx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x19,0x05]
+          vpcmpnltw (%rcx), %zmm29, %k3
+
+// CHECK: vpcmpnltw 291(%rax,%r14,8), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xb3,0x95,0x40,0x3f,0x9c,0xf0,0x23,0x01,0x00,0x00,0x05]
+          vpcmpnltw 291(%rax,%r14,8), %zmm29, %k3
+
+// CHECK: vpcmpnltw 8128(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x5a,0x7f,0x05]
+          vpcmpnltw 8128(%rdx), %zmm29, %k3
+
+// CHECK: vpcmpnltw 8192(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x9a,0x00,0x20,0x00,0x00,0x05]
+          vpcmpnltw 8192(%rdx), %zmm29, %k3
+
+// CHECK: vpcmpnltw -8192(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x5a,0x80,0x05]
+          vpcmpnltw -8192(%rdx), %zmm29, %k3
+
+// CHECK: vpcmpnltw -8256(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x9a,0xc0,0xdf,0xff,0xff,0x05]
+          vpcmpnltw -8256(%rdx), %zmm29, %k3
+
+// CHECK: vpcmpnlew %zmm25, %zmm29, %k3
+// CHECK:  encoding: [0x62,0x93,0x95,0x40,0x3f,0xd9,0x06]
+          vpcmpnlew %zmm25, %zmm29, %k3
+
+// CHECK: vpcmpnlew %zmm25, %zmm29, %k3 {%k6}
+// CHECK:  encoding: [0x62,0x93,0x95,0x46,0x3f,0xd9,0x06]
+          vpcmpnlew %zmm25, %zmm29, %k3 {%k6}
+
+// CHECK: vpcmpnlew (%rcx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x19,0x06]
+          vpcmpnlew (%rcx), %zmm29, %k3
+
+// CHECK: vpcmpnlew 291(%rax,%r14,8), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xb3,0x95,0x40,0x3f,0x9c,0xf0,0x23,0x01,0x00,0x00,0x06]
+          vpcmpnlew 291(%rax,%r14,8), %zmm29, %k3
+
+// CHECK: vpcmpnlew 8128(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x5a,0x7f,0x06]
+          vpcmpnlew 8128(%rdx), %zmm29, %k3
+
+// CHECK: vpcmpnlew 8192(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x9a,0x00,0x20,0x00,0x00,0x06]
+          vpcmpnlew 8192(%rdx), %zmm29, %k3
+
+// CHECK: vpcmpnlew -8192(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x5a,0x80,0x06]
+          vpcmpnlew -8192(%rdx), %zmm29, %k3
+
+// CHECK: vpcmpnlew -8256(%rdx), %zmm29, %k3
+// CHECK:  encoding: [0x62,0xf3,0x95,0x40,0x3f,0x9a,0xc0,0xdf,0xff,0xff,0x06]
+          vpcmpnlew -8256(%rdx), %zmm29, %k3
+
 // CHECK: vpcmpub $171, %zmm22, %zmm29, %k4
 // CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xe6,0xab]
           vpcmpub $171, %zmm22, %zmm29, %k4
@@ -984,6 +1376,222 @@
 // CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0xa2,0xc0,0xdf,0xff,0xff,0x7b]
           vpcmpub $123, -8256(%rdx), %zmm29, %k4
 
+// CHECK: vpcmpequb %zmm22, %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xe6,0x00]
+          vpcmpequb %zmm22, %zmm29, %k4
+
+// CHECK: vpcmpequb %zmm22, %zmm29, %k4 {%k7}
+// CHECK:  encoding: [0x62,0xb3,0x15,0x47,0x3e,0xe6,0x00]
+          vpcmpequb %zmm22, %zmm29, %k4 {%k7}
+
+// CHECK: vpcmpequb %zmm22, %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xe6,0x00]
+          vpcmpequb %zmm22, %zmm29, %k4
+
+// CHECK: vpcmpequb (%rcx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x21,0x00]
+          vpcmpequb (%rcx), %zmm29, %k4
+
+// CHECK: vpcmpequb 291(%rax,%r14,8), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xa4,0xf0,0x23,0x01,0x00,0x00,0x00]
+          vpcmpequb 291(%rax,%r14,8), %zmm29, %k4
+
+// CHECK: vpcmpequb 8128(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x62,0x7f,0x00]
+          vpcmpequb 8128(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpequb 8192(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0xa2,0x00,0x20,0x00,0x00,0x00]
+          vpcmpequb 8192(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpequb -8192(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x62,0x80,0x00]
+          vpcmpequb -8192(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpequb -8256(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0xa2,0xc0,0xdf,0xff,0xff,0x00]
+          vpcmpequb -8256(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpltub %zmm22, %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xe6,0x01]
+          vpcmpltub %zmm22, %zmm29, %k4
+
+// CHECK: vpcmpltub %zmm22, %zmm29, %k4 {%k7}
+// CHECK:  encoding: [0x62,0xb3,0x15,0x47,0x3e,0xe6,0x01]
+          vpcmpltub %zmm22, %zmm29, %k4 {%k7}
+
+// CHECK: vpcmpltub %zmm22, %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xe6,0x01]
+          vpcmpltub %zmm22, %zmm29, %k4
+
+// CHECK: vpcmpltub (%rcx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x21,0x01]
+          vpcmpltub (%rcx), %zmm29, %k4
+
+// CHECK: vpcmpltub 291(%rax,%r14,8), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xa4,0xf0,0x23,0x01,0x00,0x00,0x01]
+          vpcmpltub 291(%rax,%r14,8), %zmm29, %k4
+
+// CHECK: vpcmpltub 8128(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x62,0x7f,0x01]
+          vpcmpltub 8128(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpltub 8192(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0xa2,0x00,0x20,0x00,0x00,0x01]
+          vpcmpltub 8192(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpltub -8192(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x62,0x80,0x01]
+          vpcmpltub -8192(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpltub -8256(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0xa2,0xc0,0xdf,0xff,0xff,0x01]
+          vpcmpltub -8256(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpleub %zmm22, %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xe6,0x02]
+          vpcmpleub %zmm22, %zmm29, %k4
+
+// CHECK: vpcmpleub %zmm22, %zmm29, %k4 {%k7}
+// CHECK:  encoding: [0x62,0xb3,0x15,0x47,0x3e,0xe6,0x02]
+          vpcmpleub %zmm22, %zmm29, %k4 {%k7}
+
+// CHECK: vpcmpleub %zmm22, %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xe6,0x02]
+          vpcmpleub %zmm22, %zmm29, %k4
+
+// CHECK: vpcmpleub (%rcx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x21,0x02]
+          vpcmpleub (%rcx), %zmm29, %k4
+
+// CHECK: vpcmpleub 291(%rax,%r14,8), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xa4,0xf0,0x23,0x01,0x00,0x00,0x02]
+          vpcmpleub 291(%rax,%r14,8), %zmm29, %k4
+
+// CHECK: vpcmpleub 8128(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x62,0x7f,0x02]
+          vpcmpleub 8128(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpleub 8192(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0xa2,0x00,0x20,0x00,0x00,0x02]
+          vpcmpleub 8192(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpleub -8192(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x62,0x80,0x02]
+          vpcmpleub -8192(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpleub -8256(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0xa2,0xc0,0xdf,0xff,0xff,0x02]
+          vpcmpleub -8256(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpnequb %zmm22, %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xe6,0x04]
+          vpcmpnequb %zmm22, %zmm29, %k4
+
+// CHECK: vpcmpnequb %zmm22, %zmm29, %k4 {%k7}
+// CHECK:  encoding: [0x62,0xb3,0x15,0x47,0x3e,0xe6,0x04]
+          vpcmpnequb %zmm22, %zmm29, %k4 {%k7}
+
+// CHECK: vpcmpnequb %zmm22, %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xe6,0x04]
+          vpcmpnequb %zmm22, %zmm29, %k4
+
+// CHECK: vpcmpnequb (%rcx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x21,0x04]
+          vpcmpnequb (%rcx), %zmm29, %k4
+
+// CHECK: vpcmpnequb 291(%rax,%r14,8), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xa4,0xf0,0x23,0x01,0x00,0x00,0x04]
+          vpcmpnequb 291(%rax,%r14,8), %zmm29, %k4
+
+// CHECK: vpcmpnequb 8128(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x62,0x7f,0x04]
+          vpcmpnequb 8128(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpnequb 8192(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0xa2,0x00,0x20,0x00,0x00,0x04]
+          vpcmpnequb 8192(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpnequb -8192(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x62,0x80,0x04]
+          vpcmpnequb -8192(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpnequb -8256(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0xa2,0xc0,0xdf,0xff,0xff,0x04]
+          vpcmpnequb -8256(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpnltub %zmm22, %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xe6,0x05]
+          vpcmpnltub %zmm22, %zmm29, %k4
+
+// CHECK: vpcmpnltub %zmm22, %zmm29, %k4 {%k7}
+// CHECK:  encoding: [0x62,0xb3,0x15,0x47,0x3e,0xe6,0x05]
+          vpcmpnltub %zmm22, %zmm29, %k4 {%k7}
+
+// CHECK: vpcmpnltub %zmm22, %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xe6,0x05]
+          vpcmpnltub %zmm22, %zmm29, %k4
+
+// CHECK: vpcmpnltub (%rcx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x21,0x05]
+          vpcmpnltub (%rcx), %zmm29, %k4
+
+// CHECK: vpcmpnltub 291(%rax,%r14,8), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xa4,0xf0,0x23,0x01,0x00,0x00,0x05]
+          vpcmpnltub 291(%rax,%r14,8), %zmm29, %k4
+
+// CHECK: vpcmpnltub 8128(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x62,0x7f,0x05]
+          vpcmpnltub 8128(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpnltub 8192(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0xa2,0x00,0x20,0x00,0x00,0x05]
+          vpcmpnltub 8192(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpnltub -8192(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x62,0x80,0x05]
+          vpcmpnltub -8192(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpnltub -8256(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0xa2,0xc0,0xdf,0xff,0xff,0x05]
+          vpcmpnltub -8256(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpnleub %zmm22, %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xe6,0x06]
+          vpcmpnleub %zmm22, %zmm29, %k4
+
+// CHECK: vpcmpnleub %zmm22, %zmm29, %k4 {%k7}
+// CHECK:  encoding: [0x62,0xb3,0x15,0x47,0x3e,0xe6,0x06]
+          vpcmpnleub %zmm22, %zmm29, %k4 {%k7}
+
+// CHECK: vpcmpnleub %zmm22, %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xe6,0x06]
+          vpcmpnleub %zmm22, %zmm29, %k4
+
+// CHECK: vpcmpnleub (%rcx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x21,0x06]
+          vpcmpnleub (%rcx), %zmm29, %k4
+
+// CHECK: vpcmpnleub 291(%rax,%r14,8), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xb3,0x15,0x40,0x3e,0xa4,0xf0,0x23,0x01,0x00,0x00,0x06]
+          vpcmpnleub 291(%rax,%r14,8), %zmm29, %k4
+
+// CHECK: vpcmpnleub 8128(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x62,0x7f,0x06]
+          vpcmpnleub 8128(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpnleub 8192(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0xa2,0x00,0x20,0x00,0x00,0x06]
+          vpcmpnleub 8192(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpnleub -8192(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0x62,0x80,0x06]
+          vpcmpnleub -8192(%rdx), %zmm29, %k4
+
+// CHECK: vpcmpnleub -8256(%rdx), %zmm29, %k4
+// CHECK:  encoding: [0x62,0xf3,0x15,0x40,0x3e,0xa2,0xc0,0xdf,0xff,0xff,0x06]
+          vpcmpnleub -8256(%rdx), %zmm29, %k4
+
 // CHECK: vpcmpuw $171, %zmm22, %zmm22, %k4
 // CHECK:  encoding: [0x62,0xb3,0xcd,0x40,0x3e,0xe6,0xab]
           vpcmpuw $171, %zmm22, %zmm22, %k4
@@ -1019,3 +1627,1684 @@
 // CHECK: vpcmpuw $123, -8256(%rdx), %zmm22, %k4
 // CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0xa2,0xc0,0xdf,0xff,0xff,0x7b]
           vpcmpuw $123, -8256(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpequw %zmm22, %zmm22, %k4
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x40,0x3e,0xe6,0x00]
+          vpcmpequw %zmm22, %zmm22, %k4
+
+// CHECK: vpcmpequw %zmm22, %zmm22, %k4 {%k7}
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x47,0x3e,0xe6,0x00]
+          vpcmpequw %zmm22, %zmm22, %k4 {%k7}
+
+// CHECK: vpcmpequw (%rcx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x21,0x00]
+          vpcmpequw (%rcx), %zmm22, %k4
+
+// CHECK: vpcmpequw 291(%rax,%r14,8), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x40,0x3e,0xa4,0xf0,0x23,0x01,0x00,0x00,0x00]
+          vpcmpequw 291(%rax,%r14,8), %zmm22, %k4
+
+// CHECK: vpcmpequw 8128(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x62,0x7f,0x00]
+          vpcmpequw 8128(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpequw 8192(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0xa2,0x00,0x20,0x00,0x00,0x00]
+          vpcmpequw 8192(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpequw -8192(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x62,0x80,0x00]
+          vpcmpequw -8192(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpequw -8256(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0xa2,0xc0,0xdf,0xff,0xff,0x00]
+          vpcmpequw -8256(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpltuw %zmm22, %zmm22, %k4
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x40,0x3e,0xe6,0x01]
+          vpcmpltuw %zmm22, %zmm22, %k4
+
+// CHECK: vpcmpltuw %zmm22, %zmm22, %k4 {%k7}
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x47,0x3e,0xe6,0x01]
+          vpcmpltuw %zmm22, %zmm22, %k4 {%k7}
+
+// CHECK: vpcmpltuw (%rcx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x21,0x01]
+          vpcmpltuw (%rcx), %zmm22, %k4
+
+// CHECK: vpcmpltuw 291(%rax,%r14,8), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x40,0x3e,0xa4,0xf0,0x23,0x01,0x00,0x00,0x01]
+          vpcmpltuw 291(%rax,%r14,8), %zmm22, %k4
+
+// CHECK: vpcmpltuw 8128(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x62,0x7f,0x01]
+          vpcmpltuw 8128(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpltuw 8192(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0xa2,0x00,0x20,0x00,0x00,0x01]
+          vpcmpltuw 8192(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpltuw -8192(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x62,0x80,0x01]
+          vpcmpltuw -8192(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpltuw -8256(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0xa2,0xc0,0xdf,0xff,0xff,0x01]
+          vpcmpltuw -8256(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpleuw %zmm22, %zmm22, %k4
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x40,0x3e,0xe6,0x02]
+          vpcmpleuw %zmm22, %zmm22, %k4
+
+// CHECK: vpcmpleuw %zmm22, %zmm22, %k4 {%k7}
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x47,0x3e,0xe6,0x02]
+          vpcmpleuw %zmm22, %zmm22, %k4 {%k7}
+
+// CHECK: vpcmpleuw (%rcx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x21,0x02]
+          vpcmpleuw (%rcx), %zmm22, %k4
+
+// CHECK: vpcmpleuw 291(%rax,%r14,8), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x40,0x3e,0xa4,0xf0,0x23,0x01,0x00,0x00,0x02]
+          vpcmpleuw 291(%rax,%r14,8), %zmm22, %k4
+
+// CHECK: vpcmpleuw 8128(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x62,0x7f,0x02]
+          vpcmpleuw 8128(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpleuw 8192(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0xa2,0x00,0x20,0x00,0x00,0x02]
+          vpcmpleuw 8192(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpleuw -8192(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x62,0x80,0x02]
+          vpcmpleuw -8192(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpleuw -8256(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0xa2,0xc0,0xdf,0xff,0xff,0x02]
+          vpcmpleuw -8256(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpnequw %zmm22, %zmm22, %k4
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x40,0x3e,0xe6,0x04]
+          vpcmpnequw %zmm22, %zmm22, %k4
+
+// CHECK: vpcmpnequw %zmm22, %zmm22, %k4 {%k7}
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x47,0x3e,0xe6,0x04]
+          vpcmpnequw %zmm22, %zmm22, %k4 {%k7}
+
+// CHECK: vpcmpnequw (%rcx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x21,0x04]
+          vpcmpnequw (%rcx), %zmm22, %k4
+
+// CHECK: vpcmpnequw 291(%rax,%r14,8), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x40,0x3e,0xa4,0xf0,0x23,0x01,0x00,0x00,0x04]
+          vpcmpnequw 291(%rax,%r14,8), %zmm22, %k4
+
+// CHECK: vpcmpnequw 8128(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x62,0x7f,0x04]
+          vpcmpnequw 8128(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpnequw 8192(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0xa2,0x00,0x20,0x00,0x00,0x04]
+          vpcmpnequw 8192(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpnequw -8192(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x62,0x80,0x04]
+          vpcmpnequw -8192(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpnequw -8256(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0xa2,0xc0,0xdf,0xff,0xff,0x04]
+          vpcmpnequw -8256(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpnltuw %zmm22, %zmm22, %k4
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x40,0x3e,0xe6,0x05]
+          vpcmpnltuw %zmm22, %zmm22, %k4
+
+// CHECK: vpcmpnltuw %zmm22, %zmm22, %k4 {%k7}
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x47,0x3e,0xe6,0x05]
+          vpcmpnltuw %zmm22, %zmm22, %k4 {%k7}
+
+// CHECK: vpcmpnltuw (%rcx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x21,0x05]
+          vpcmpnltuw (%rcx), %zmm22, %k4
+
+// CHECK: vpcmpnltuw 291(%rax,%r14,8), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x40,0x3e,0xa4,0xf0,0x23,0x01,0x00,0x00,0x05]
+          vpcmpnltuw 291(%rax,%r14,8), %zmm22, %k4
+
+// CHECK: vpcmpnltuw 8128(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x62,0x7f,0x05]
+          vpcmpnltuw 8128(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpnltuw 8192(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0xa2,0x00,0x20,0x00,0x00,0x05]
+          vpcmpnltuw 8192(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpnltuw -8192(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x62,0x80,0x05]
+          vpcmpnltuw -8192(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpnltuw -8256(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0xa2,0xc0,0xdf,0xff,0xff,0x05]
+          vpcmpnltuw -8256(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpnleuw %zmm22, %zmm22, %k4
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x40,0x3e,0xe6,0x06]
+          vpcmpnleuw %zmm22, %zmm22, %k4
+
+// CHECK: vpcmpnleuw %zmm22, %zmm22, %k4 {%k7}
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x47,0x3e,0xe6,0x06]
+          vpcmpnleuw %zmm22, %zmm22, %k4 {%k7}
+
+// CHECK: vpcmpnleuw (%rcx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x21,0x06]
+          vpcmpnleuw (%rcx), %zmm22, %k4
+
+// CHECK: vpcmpnleuw 291(%rax,%r14,8), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xb3,0xcd,0x40,0x3e,0xa4,0xf0,0x23,0x01,0x00,0x00,0x06]
+          vpcmpnleuw 291(%rax,%r14,8), %zmm22, %k4
+
+// CHECK: vpcmpnleuw 8128(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x62,0x7f,0x06]
+          vpcmpnleuw 8128(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpnleuw 8192(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0xa2,0x00,0x20,0x00,0x00,0x06]
+          vpcmpnleuw 8192(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpnleuw -8192(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0x62,0x80,0x06]
+          vpcmpnleuw -8192(%rdx), %zmm22, %k4
+
+// CHECK: vpcmpnleuw -8256(%rdx), %zmm22, %k4
+// CHECK:  encoding: [0x62,0xf3,0xcd,0x40,0x3e,0xa2,0xc0,0xdf,0xff,0xff,0x06]
+          vpcmpnleuw -8256(%rdx), %zmm22, %k4
+
+// CHECK: vpsllw %xmm24, %zmm21, %zmm24
+// CHECK:  encoding: [0x62,0x01,0x55,0x40,0xf1,0xc0]
+          vpsllw %xmm24, %zmm21, %zmm24
+
+// CHECK: vpsllw %xmm24, %zmm21, %zmm24 {%k2}
+// CHECK:  encoding: [0x62,0x01,0x55,0x42,0xf1,0xc0]
+          vpsllw %xmm24, %zmm21, %zmm24 {%k2}
+
+// CHECK: vpsllw %xmm24, %zmm21, %zmm24 {%k2} {z}
+// CHECK:  encoding: [0x62,0x01,0x55,0xc2,0xf1,0xc0]
+          vpsllw %xmm24, %zmm21, %zmm24 {%k2} {z}
+
+// CHECK: vpsllw (%rcx), %zmm21, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x55,0x40,0xf1,0x01]
+          vpsllw (%rcx), %zmm21, %zmm24
+
+// CHECK: vpsllw 291(%rax,%r14,8), %zmm21, %zmm24
+// CHECK:  encoding: [0x62,0x21,0x55,0x40,0xf1,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vpsllw 291(%rax,%r14,8), %zmm21, %zmm24
+
+// CHECK: vpsllw 2032(%rdx), %zmm21, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x55,0x40,0xf1,0x42,0x7f]
+          vpsllw 2032(%rdx), %zmm21, %zmm24
+
+// CHECK: vpsllw 2048(%rdx), %zmm21, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x55,0x40,0xf1,0x82,0x00,0x08,0x00,0x00]
+          vpsllw 2048(%rdx), %zmm21, %zmm24
+
+// CHECK: vpsllw -2048(%rdx), %zmm21, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x55,0x40,0xf1,0x42,0x80]
+          vpsllw -2048(%rdx), %zmm21, %zmm24
+
+// CHECK: vpsllw -2064(%rdx), %zmm21, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x55,0x40,0xf1,0x82,0xf0,0xf7,0xff,0xff]
+          vpsllw -2064(%rdx), %zmm21, %zmm24
+
+// CHECK: vpsraw %xmm21, %zmm27, %zmm28
+// CHECK:  encoding: [0x62,0x21,0x25,0x40,0xe1,0xe5]
+          vpsraw %xmm21, %zmm27, %zmm28
+
+// CHECK: vpsraw %xmm21, %zmm27, %zmm28 {%k4}
+// CHECK:  encoding: [0x62,0x21,0x25,0x44,0xe1,0xe5]
+          vpsraw %xmm21, %zmm27, %zmm28 {%k4}
+
+// CHECK: vpsraw %xmm21, %zmm27, %zmm28 {%k4} {z}
+// CHECK:  encoding: [0x62,0x21,0x25,0xc4,0xe1,0xe5]
+          vpsraw %xmm21, %zmm27, %zmm28 {%k4} {z}
+
+// CHECK: vpsraw (%rcx), %zmm27, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x25,0x40,0xe1,0x21]
+          vpsraw (%rcx), %zmm27, %zmm28
+
+// CHECK: vpsraw 291(%rax,%r14,8), %zmm27, %zmm28
+// CHECK:  encoding: [0x62,0x21,0x25,0x40,0xe1,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsraw 291(%rax,%r14,8), %zmm27, %zmm28
+
+// CHECK: vpsraw 2032(%rdx), %zmm27, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x25,0x40,0xe1,0x62,0x7f]
+          vpsraw 2032(%rdx), %zmm27, %zmm28
+
+// CHECK: vpsraw 2048(%rdx), %zmm27, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x25,0x40,0xe1,0xa2,0x00,0x08,0x00,0x00]
+          vpsraw 2048(%rdx), %zmm27, %zmm28
+
+// CHECK: vpsraw -2048(%rdx), %zmm27, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x25,0x40,0xe1,0x62,0x80]
+          vpsraw -2048(%rdx), %zmm27, %zmm28
+
+// CHECK: vpsraw -2064(%rdx), %zmm27, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x25,0x40,0xe1,0xa2,0xf0,0xf7,0xff,0xff]
+          vpsraw -2064(%rdx), %zmm27, %zmm28
+
+// CHECK: vpsrlw %xmm22, %zmm20, %zmm23
+// CHECK:  encoding: [0x62,0xa1,0x5d,0x40,0xd1,0xfe]
+          vpsrlw %xmm22, %zmm20, %zmm23
+
+// CHECK: vpsrlw %xmm22, %zmm20, %zmm23 {%k6}
+// CHECK:  encoding: [0x62,0xa1,0x5d,0x46,0xd1,0xfe]
+          vpsrlw %xmm22, %zmm20, %zmm23 {%k6}
+
+// CHECK: vpsrlw %xmm22, %zmm20, %zmm23 {%k6} {z}
+// CHECK:  encoding: [0x62,0xa1,0x5d,0xc6,0xd1,0xfe]
+          vpsrlw %xmm22, %zmm20, %zmm23 {%k6} {z}
+
+// CHECK: vpsrlw (%rcx), %zmm20, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x40,0xd1,0x39]
+          vpsrlw (%rcx), %zmm20, %zmm23
+
+// CHECK: vpsrlw 291(%rax,%r14,8), %zmm20, %zmm23
+// CHECK:  encoding: [0x62,0xa1,0x5d,0x40,0xd1,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vpsrlw 291(%rax,%r14,8), %zmm20, %zmm23
+
+// CHECK: vpsrlw 2032(%rdx), %zmm20, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x40,0xd1,0x7a,0x7f]
+          vpsrlw 2032(%rdx), %zmm20, %zmm23
+
+// CHECK: vpsrlw 2048(%rdx), %zmm20, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x40,0xd1,0xba,0x00,0x08,0x00,0x00]
+          vpsrlw 2048(%rdx), %zmm20, %zmm23
+
+// CHECK: vpsrlw -2048(%rdx), %zmm20, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x40,0xd1,0x7a,0x80]
+          vpsrlw -2048(%rdx), %zmm20, %zmm23
+
+// CHECK: vpsrlw -2064(%rdx), %zmm20, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x40,0xd1,0xba,0xf0,0xf7,0xff,0xff]
+          vpsrlw -2064(%rdx), %zmm20, %zmm23
+
+// CHECK: vpsrlw $171, %zmm26, %zmm25
+// CHECK:  encoding: [0x62,0x91,0x35,0x40,0x71,0xd2,0xab]
+          vpsrlw $171, %zmm26, %zmm25
+
+// CHECK: vpsrlw $171, %zmm26, %zmm25 {%k6}
+// CHECK:  encoding: [0x62,0x91,0x35,0x46,0x71,0xd2,0xab]
+          vpsrlw $171, %zmm26, %zmm25 {%k6}
+
+// CHECK: vpsrlw $171, %zmm26, %zmm25 {%k6} {z}
+// CHECK:  encoding: [0x62,0x91,0x35,0xc6,0x71,0xd2,0xab]
+          vpsrlw $171, %zmm26, %zmm25 {%k6} {z}
+
+// CHECK: vpsrlw $123, %zmm26, %zmm25
+// CHECK:  encoding: [0x62,0x91,0x35,0x40,0x71,0xd2,0x7b]
+          vpsrlw $123, %zmm26, %zmm25
+
+// CHECK: vpsrlw $123, (%rcx), %zmm25
+// CHECK:  encoding: [0x62,0xf1,0x35,0x40,0x71,0x11,0x7b]
+          vpsrlw $123, (%rcx), %zmm25
+
+// CHECK: vpsrlw $123, 291(%rax,%r14,8), %zmm25
+// CHECK:  encoding: [0x62,0xb1,0x35,0x40,0x71,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpsrlw $123, 291(%rax,%r14,8), %zmm25
+
+// CHECK: vpsrlw $123, 8128(%rdx), %zmm25
+// CHECK:  encoding: [0x62,0xf1,0x35,0x40,0x71,0x52,0x7f,0x7b]
+          vpsrlw $123, 8128(%rdx), %zmm25
+
+// CHECK: vpsrlw $123, 8192(%rdx), %zmm25
+// CHECK:  encoding: [0x62,0xf1,0x35,0x40,0x71,0x92,0x00,0x20,0x00,0x00,0x7b]
+          vpsrlw $123, 8192(%rdx), %zmm25
+
+// CHECK: vpsrlw $123, -8192(%rdx), %zmm25
+// CHECK:  encoding: [0x62,0xf1,0x35,0x40,0x71,0x52,0x80,0x7b]
+          vpsrlw $123, -8192(%rdx), %zmm25
+
+// CHECK: vpsrlw $123, -8256(%rdx), %zmm25
+// CHECK:  encoding: [0x62,0xf1,0x35,0x40,0x71,0x92,0xc0,0xdf,0xff,0xff,0x7b]
+          vpsrlw $123, -8256(%rdx), %zmm25
+
+// CHECK: vpsraw $171, %zmm29, %zmm28
+// CHECK:  encoding: [0x62,0x91,0x1d,0x40,0x71,0xe5,0xab]
+          vpsraw $171, %zmm29, %zmm28
+
+// CHECK: vpsraw $171, %zmm29, %zmm28 {%k4}
+// CHECK:  encoding: [0x62,0x91,0x1d,0x44,0x71,0xe5,0xab]
+          vpsraw $171, %zmm29, %zmm28 {%k4}
+
+// CHECK: vpsraw $171, %zmm29, %zmm28 {%k4} {z}
+// CHECK:  encoding: [0x62,0x91,0x1d,0xc4,0x71,0xe5,0xab]
+          vpsraw $171, %zmm29, %zmm28 {%k4} {z}
+
+// CHECK: vpsraw $123, %zmm29, %zmm28
+// CHECK:  encoding: [0x62,0x91,0x1d,0x40,0x71,0xe5,0x7b]
+          vpsraw $123, %zmm29, %zmm28
+
+// CHECK: vpsraw $123, (%rcx), %zmm28
+// CHECK:  encoding: [0x62,0xf1,0x1d,0x40,0x71,0x21,0x7b]
+          vpsraw $123, (%rcx), %zmm28
+
+// CHECK: vpsraw $123, 291(%rax,%r14,8), %zmm28
+// CHECK:  encoding: [0x62,0xb1,0x1d,0x40,0x71,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpsraw $123, 291(%rax,%r14,8), %zmm28
+
+// CHECK: vpsraw $123, 8128(%rdx), %zmm28
+// CHECK:  encoding: [0x62,0xf1,0x1d,0x40,0x71,0x62,0x7f,0x7b]
+          vpsraw $123, 8128(%rdx), %zmm28
+
+// CHECK: vpsraw $123, 8192(%rdx), %zmm28
+// CHECK:  encoding: [0x62,0xf1,0x1d,0x40,0x71,0xa2,0x00,0x20,0x00,0x00,0x7b]
+          vpsraw $123, 8192(%rdx), %zmm28
+
+// CHECK: vpsraw $123, -8192(%rdx), %zmm28
+// CHECK:  encoding: [0x62,0xf1,0x1d,0x40,0x71,0x62,0x80,0x7b]
+          vpsraw $123, -8192(%rdx), %zmm28
+
+// CHECK: vpsraw $123, -8256(%rdx), %zmm28
+// CHECK:  encoding: [0x62,0xf1,0x1d,0x40,0x71,0xa2,0xc0,0xdf,0xff,0xff,0x7b]
+          vpsraw $123, -8256(%rdx), %zmm28
+
+// CHECK: vpsrlvw %zmm21, %zmm18, %zmm17
+// CHECK:  encoding: [0x62,0xa2,0xed,0x40,0x10,0xcd]
+          vpsrlvw %zmm21, %zmm18, %zmm17
+
+// CHECK: vpsrlvw %zmm21, %zmm18, %zmm17 {%k6}
+// CHECK:  encoding: [0x62,0xa2,0xed,0x46,0x10,0xcd]
+          vpsrlvw %zmm21, %zmm18, %zmm17 {%k6}
+
+// CHECK: vpsrlvw %zmm21, %zmm18, %zmm17 {%k6} {z}
+// CHECK:  encoding: [0x62,0xa2,0xed,0xc6,0x10,0xcd]
+          vpsrlvw %zmm21, %zmm18, %zmm17 {%k6} {z}
+
+// CHECK: vpsrlvw (%rcx), %zmm18, %zmm17
+// CHECK:  encoding: [0x62,0xe2,0xed,0x40,0x10,0x09]
+          vpsrlvw (%rcx), %zmm18, %zmm17
+
+// CHECK: vpsrlvw 291(%rax,%r14,8), %zmm18, %zmm17
+// CHECK:  encoding: [0x62,0xa2,0xed,0x40,0x10,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpsrlvw 291(%rax,%r14,8), %zmm18, %zmm17
+
+// CHECK: vpsrlvw 8128(%rdx), %zmm18, %zmm17
+// CHECK:  encoding: [0x62,0xe2,0xed,0x40,0x10,0x4a,0x7f]
+          vpsrlvw 8128(%rdx), %zmm18, %zmm17
+
+// CHECK: vpsrlvw 8192(%rdx), %zmm18, %zmm17
+// CHECK:  encoding: [0x62,0xe2,0xed,0x40,0x10,0x8a,0x00,0x20,0x00,0x00]
+          vpsrlvw 8192(%rdx), %zmm18, %zmm17
+
+// CHECK: vpsrlvw -8192(%rdx), %zmm18, %zmm17
+// CHECK:  encoding: [0x62,0xe2,0xed,0x40,0x10,0x4a,0x80]
+          vpsrlvw -8192(%rdx), %zmm18, %zmm17
+
+// CHECK: vpsrlvw -8256(%rdx), %zmm18, %zmm17
+// CHECK:  encoding: [0x62,0xe2,0xed,0x40,0x10,0x8a,0xc0,0xdf,0xff,0xff]
+          vpsrlvw -8256(%rdx), %zmm18, %zmm17
+
+// CHECK: vpsravw %zmm20, %zmm29, %zmm19
+// CHECK:  encoding: [0x62,0xa2,0x95,0x40,0x11,0xdc]
+          vpsravw %zmm20, %zmm29, %zmm19
+
+// CHECK: vpsravw %zmm20, %zmm29, %zmm19 {%k7}
+// CHECK:  encoding: [0x62,0xa2,0x95,0x47,0x11,0xdc]
+          vpsravw %zmm20, %zmm29, %zmm19 {%k7}
+
+// CHECK: vpsravw %zmm20, %zmm29, %zmm19 {%k7} {z}
+// CHECK:  encoding: [0x62,0xa2,0x95,0xc7,0x11,0xdc]
+          vpsravw %zmm20, %zmm29, %zmm19 {%k7} {z}
+
+// CHECK: vpsravw (%rcx), %zmm29, %zmm19
+// CHECK:  encoding: [0x62,0xe2,0x95,0x40,0x11,0x19]
+          vpsravw (%rcx), %zmm29, %zmm19
+
+// CHECK: vpsravw 291(%rax,%r14,8), %zmm29, %zmm19
+// CHECK:  encoding: [0x62,0xa2,0x95,0x40,0x11,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpsravw 291(%rax,%r14,8), %zmm29, %zmm19
+
+// CHECK: vpsravw 8128(%rdx), %zmm29, %zmm19
+// CHECK:  encoding: [0x62,0xe2,0x95,0x40,0x11,0x5a,0x7f]
+          vpsravw 8128(%rdx), %zmm29, %zmm19
+
+// CHECK: vpsravw 8192(%rdx), %zmm29, %zmm19
+// CHECK:  encoding: [0x62,0xe2,0x95,0x40,0x11,0x9a,0x00,0x20,0x00,0x00]
+          vpsravw 8192(%rdx), %zmm29, %zmm19
+
+// CHECK: vpsravw -8192(%rdx), %zmm29, %zmm19
+// CHECK:  encoding: [0x62,0xe2,0x95,0x40,0x11,0x5a,0x80]
+          vpsravw -8192(%rdx), %zmm29, %zmm19
+
+// CHECK: vpsravw -8256(%rdx), %zmm29, %zmm19
+// CHECK:  encoding: [0x62,0xe2,0x95,0x40,0x11,0x9a,0xc0,0xdf,0xff,0xff]
+          vpsravw -8256(%rdx), %zmm29, %zmm19
+
+// CHECK: vpacksswb %zmm18, %zmm29, %zmm21
+// CHECK:  encoding: [0x62,0xa1,0x95,0x40,0x63,0xea]
+          vpacksswb %zmm18, %zmm29, %zmm21
+
+// CHECK: vpacksswb %zmm18, %zmm29, %zmm21 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0x95,0x41,0x63,0xea]
+          vpacksswb %zmm18, %zmm29, %zmm21 {%k1}
+
+// CHECK: vpacksswb %zmm18, %zmm29, %zmm21 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0x95,0xc1,0x63,0xea]
+          vpacksswb %zmm18, %zmm29, %zmm21 {%k1} {z}
+
+// CHECK: vpacksswb (%rcx), %zmm29, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x95,0x40,0x63,0x29]
+          vpacksswb (%rcx), %zmm29, %zmm21
+
+// CHECK: vpacksswb 291(%rax,%r14,8), %zmm29, %zmm21
+// CHECK:  encoding: [0x62,0xa1,0x95,0x40,0x63,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpacksswb 291(%rax,%r14,8), %zmm29, %zmm21
+
+// CHECK: vpacksswb 8128(%rdx), %zmm29, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x95,0x40,0x63,0x6a,0x7f]
+          vpacksswb 8128(%rdx), %zmm29, %zmm21
+
+// CHECK: vpacksswb 8192(%rdx), %zmm29, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x95,0x40,0x63,0xaa,0x00,0x20,0x00,0x00]
+          vpacksswb 8192(%rdx), %zmm29, %zmm21
+
+// CHECK: vpacksswb -8192(%rdx), %zmm29, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x95,0x40,0x63,0x6a,0x80]
+          vpacksswb -8192(%rdx), %zmm29, %zmm21
+
+// CHECK: vpacksswb -8256(%rdx), %zmm29, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x95,0x40,0x63,0xaa,0xc0,0xdf,0xff,0xff]
+          vpacksswb -8256(%rdx), %zmm29, %zmm21
+
+// CHECK: vpackuswb %zmm28, %zmm24, %zmm28
+// CHECK:  encoding: [0x62,0x01,0xbd,0x40,0x67,0xe4]
+          vpackuswb %zmm28, %zmm24, %zmm28
+
+// CHECK: vpackuswb %zmm28, %zmm24, %zmm28 {%k6}
+// CHECK:  encoding: [0x62,0x01,0xbd,0x46,0x67,0xe4]
+          vpackuswb %zmm28, %zmm24, %zmm28 {%k6}
+
+// CHECK: vpackuswb %zmm28, %zmm24, %zmm28 {%k6} {z}
+// CHECK:  encoding: [0x62,0x01,0xbd,0xc6,0x67,0xe4]
+          vpackuswb %zmm28, %zmm24, %zmm28 {%k6} {z}
+
+// CHECK: vpackuswb (%rcx), %zmm24, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xbd,0x40,0x67,0x21]
+          vpackuswb (%rcx), %zmm24, %zmm28
+
+// CHECK: vpackuswb 291(%rax,%r14,8), %zmm24, %zmm28
+// CHECK:  encoding: [0x62,0x21,0xbd,0x40,0x67,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpackuswb 291(%rax,%r14,8), %zmm24, %zmm28
+
+// CHECK: vpackuswb 8128(%rdx), %zmm24, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xbd,0x40,0x67,0x62,0x7f]
+          vpackuswb 8128(%rdx), %zmm24, %zmm28
+
+// CHECK: vpackuswb 8192(%rdx), %zmm24, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xbd,0x40,0x67,0xa2,0x00,0x20,0x00,0x00]
+          vpackuswb 8192(%rdx), %zmm24, %zmm28
+
+// CHECK: vpackuswb -8192(%rdx), %zmm24, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xbd,0x40,0x67,0x62,0x80]
+          vpackuswb -8192(%rdx), %zmm24, %zmm28
+
+// CHECK: vpackuswb -8256(%rdx), %zmm24, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xbd,0x40,0x67,0xa2,0xc0,0xdf,0xff,0xff]
+          vpackuswb -8256(%rdx), %zmm24, %zmm28
+
+// CHECK: vpacksswb %zmm24, %zmm29, %zmm26
+// CHECK:  encoding: [0x62,0x01,0x95,0x40,0x63,0xd0]
+          vpacksswb %zmm24, %zmm29, %zmm26
+
+// CHECK: vpacksswb %zmm24, %zmm29, %zmm26 {%k6}
+// CHECK:  encoding: [0x62,0x01,0x95,0x46,0x63,0xd0]
+          vpacksswb %zmm24, %zmm29, %zmm26 {%k6}
+
+// CHECK: vpacksswb %zmm24, %zmm29, %zmm26 {%k6} {z}
+// CHECK:  encoding: [0x62,0x01,0x95,0xc6,0x63,0xd0]
+          vpacksswb %zmm24, %zmm29, %zmm26 {%k6} {z}
+
+// CHECK: vpacksswb (%rcx), %zmm29, %zmm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x40,0x63,0x11]
+          vpacksswb (%rcx), %zmm29, %zmm26
+
+// CHECK: vpacksswb 4660(%rax,%r14,8), %zmm29, %zmm26
+// CHECK:  encoding: [0x62,0x21,0x95,0x40,0x63,0x94,0xf0,0x34,0x12,0x00,0x00]
+          vpacksswb 4660(%rax,%r14,8), %zmm29, %zmm26
+
+// CHECK: vpacksswb 8128(%rdx), %zmm29, %zmm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x40,0x63,0x52,0x7f]
+          vpacksswb 8128(%rdx), %zmm29, %zmm26
+
+// CHECK: vpacksswb 8192(%rdx), %zmm29, %zmm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x40,0x63,0x92,0x00,0x20,0x00,0x00]
+          vpacksswb 8192(%rdx), %zmm29, %zmm26
+
+// CHECK: vpacksswb -8192(%rdx), %zmm29, %zmm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x40,0x63,0x52,0x80]
+          vpacksswb -8192(%rdx), %zmm29, %zmm26
+
+// CHECK: vpacksswb -8256(%rdx), %zmm29, %zmm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x40,0x63,0x92,0xc0,0xdf,0xff,0xff]
+          vpacksswb -8256(%rdx), %zmm29, %zmm26
+
+// CHECK: vpackuswb %zmm23, %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x40,0x67,0xd7]
+          vpackuswb %zmm23, %zmm28, %zmm18
+
+// CHECK: vpackuswb %zmm23, %zmm28, %zmm18 {%k4}
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x44,0x67,0xd7]
+          vpackuswb %zmm23, %zmm28, %zmm18 {%k4}
+
+// CHECK: vpackuswb %zmm23, %zmm28, %zmm18 {%k4} {z}
+// CHECK:  encoding: [0x62,0xa1,0x9d,0xc4,0x67,0xd7]
+          vpackuswb %zmm23, %zmm28, %zmm18 {%k4} {z}
+
+// CHECK: vpackuswb (%rcx), %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x40,0x67,0x11]
+          vpackuswb (%rcx), %zmm28, %zmm18
+
+// CHECK: vpackuswb 4660(%rax,%r14,8), %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x40,0x67,0x94,0xf0,0x34,0x12,0x00,0x00]
+          vpackuswb 4660(%rax,%r14,8), %zmm28, %zmm18
+
+// CHECK: vpackuswb 8128(%rdx), %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x40,0x67,0x52,0x7f]
+          vpackuswb 8128(%rdx), %zmm28, %zmm18
+
+// CHECK: vpackuswb 8192(%rdx), %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x40,0x67,0x92,0x00,0x20,0x00,0x00]
+          vpackuswb 8192(%rdx), %zmm28, %zmm18
+
+// CHECK: vpackuswb -8192(%rdx), %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x40,0x67,0x52,0x80]
+          vpackuswb -8192(%rdx), %zmm28, %zmm18
+
+// CHECK: vpackuswb -8256(%rdx), %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x40,0x67,0x92,0xc0,0xdf,0xff,0xff]
+          vpackuswb -8256(%rdx), %zmm28, %zmm18
+
+// CHECK: vpackssdw %zmm22, %zmm27, %zmm24
+// CHECK:  encoding: [0x62,0x21,0x25,0x40,0x6b,0xc6]
+          vpackssdw %zmm22, %zmm27, %zmm24
+
+// CHECK: vpackssdw %zmm22, %zmm27, %zmm24 {%k2}
+// CHECK:  encoding: [0x62,0x21,0x25,0x42,0x6b,0xc6]
+          vpackssdw %zmm22, %zmm27, %zmm24 {%k2}
+
+// CHECK: vpackssdw %zmm22, %zmm27, %zmm24 {%k2} {z}
+// CHECK:  encoding: [0x62,0x21,0x25,0xc2,0x6b,0xc6]
+          vpackssdw %zmm22, %zmm27, %zmm24 {%k2} {z}
+
+// CHECK: vpackssdw (%rcx), %zmm27, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x25,0x40,0x6b,0x01]
+          vpackssdw (%rcx), %zmm27, %zmm24
+
+// CHECK: vpackssdw 291(%rax,%r14,8), %zmm27, %zmm24
+// CHECK:  encoding: [0x62,0x21,0x25,0x40,0x6b,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vpackssdw 291(%rax,%r14,8), %zmm27, %zmm24
+
+// CHECK: vpackssdw (%rcx){1to16}, %zmm27, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x25,0x50,0x6b,0x01]
+          vpackssdw (%rcx){1to16}, %zmm27, %zmm24
+
+// CHECK: vpackssdw 8128(%rdx), %zmm27, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x25,0x40,0x6b,0x42,0x7f]
+          vpackssdw 8128(%rdx), %zmm27, %zmm24
+
+// CHECK: vpackssdw 8192(%rdx), %zmm27, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x25,0x40,0x6b,0x82,0x00,0x20,0x00,0x00]
+          vpackssdw 8192(%rdx), %zmm27, %zmm24
+
+// CHECK: vpackssdw -8192(%rdx), %zmm27, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x25,0x40,0x6b,0x42,0x80]
+          vpackssdw -8192(%rdx), %zmm27, %zmm24
+
+// CHECK: vpackssdw -8256(%rdx), %zmm27, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x25,0x40,0x6b,0x82,0xc0,0xdf,0xff,0xff]
+          vpackssdw -8256(%rdx), %zmm27, %zmm24
+
+// CHECK: vpackssdw 508(%rdx){1to16}, %zmm27, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x25,0x50,0x6b,0x42,0x7f]
+          vpackssdw 508(%rdx){1to16}, %zmm27, %zmm24
+
+// CHECK: vpackssdw 512(%rdx){1to16}, %zmm27, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x25,0x50,0x6b,0x82,0x00,0x02,0x00,0x00]
+          vpackssdw 512(%rdx){1to16}, %zmm27, %zmm24
+
+// CHECK: vpackssdw -512(%rdx){1to16}, %zmm27, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x25,0x50,0x6b,0x42,0x80]
+          vpackssdw -512(%rdx){1to16}, %zmm27, %zmm24
+
+// CHECK: vpackssdw -516(%rdx){1to16}, %zmm27, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x25,0x50,0x6b,0x82,0xfc,0xfd,0xff,0xff]
+          vpackssdw -516(%rdx){1to16}, %zmm27, %zmm24
+
+// CHECK: vpacksswb %zmm23, %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x21,0xed,0x40,0x63,0xe7]
+          vpacksswb %zmm23, %zmm18, %zmm28
+
+// CHECK: vpacksswb %zmm23, %zmm18, %zmm28 {%k3}
+// CHECK:  encoding: [0x62,0x21,0xed,0x43,0x63,0xe7]
+          vpacksswb %zmm23, %zmm18, %zmm28 {%k3}
+
+// CHECK: vpacksswb %zmm23, %zmm18, %zmm28 {%k3} {z}
+// CHECK:  encoding: [0x62,0x21,0xed,0xc3,0x63,0xe7]
+          vpacksswb %zmm23, %zmm18, %zmm28 {%k3} {z}
+
+// CHECK: vpacksswb (%rcx), %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xed,0x40,0x63,0x21]
+          vpacksswb (%rcx), %zmm18, %zmm28
+
+// CHECK: vpacksswb 291(%rax,%r14,8), %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x21,0xed,0x40,0x63,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpacksswb 291(%rax,%r14,8), %zmm18, %zmm28
+
+// CHECK: vpacksswb 8128(%rdx), %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xed,0x40,0x63,0x62,0x7f]
+          vpacksswb 8128(%rdx), %zmm18, %zmm28
+
+// CHECK: vpacksswb 8192(%rdx), %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xed,0x40,0x63,0xa2,0x00,0x20,0x00,0x00]
+          vpacksswb 8192(%rdx), %zmm18, %zmm28
+
+// CHECK: vpacksswb -8192(%rdx), %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xed,0x40,0x63,0x62,0x80]
+          vpacksswb -8192(%rdx), %zmm18, %zmm28
+
+// CHECK: vpacksswb -8256(%rdx), %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xed,0x40,0x63,0xa2,0xc0,0xdf,0xff,0xff]
+          vpacksswb -8256(%rdx), %zmm18, %zmm28
+
+// CHECK: vpackusdw %zmm21, %zmm29, %zmm18
+// CHECK:  encoding: [0x62,0xa2,0x15,0x40,0x2b,0xd5]
+          vpackusdw %zmm21, %zmm29, %zmm18
+
+// CHECK: vpackusdw %zmm21, %zmm29, %zmm18 {%k2}
+// CHECK:  encoding: [0x62,0xa2,0x15,0x42,0x2b,0xd5]
+          vpackusdw %zmm21, %zmm29, %zmm18 {%k2}
+
+// CHECK: vpackusdw %zmm21, %zmm29, %zmm18 {%k2} {z}
+// CHECK:  encoding: [0x62,0xa2,0x15,0xc2,0x2b,0xd5]
+          vpackusdw %zmm21, %zmm29, %zmm18 {%k2} {z}
+
+// CHECK: vpackusdw (%rcx), %zmm29, %zmm18
+// CHECK:  encoding: [0x62,0xe2,0x15,0x40,0x2b,0x11]
+          vpackusdw (%rcx), %zmm29, %zmm18
+
+// CHECK: vpackusdw 291(%rax,%r14,8), %zmm29, %zmm18
+// CHECK:  encoding: [0x62,0xa2,0x15,0x40,0x2b,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vpackusdw 291(%rax,%r14,8), %zmm29, %zmm18
+
+// CHECK: vpackusdw (%rcx){1to16}, %zmm29, %zmm18
+// CHECK:  encoding: [0x62,0xe2,0x15,0x50,0x2b,0x11]
+          vpackusdw (%rcx){1to16}, %zmm29, %zmm18
+
+// CHECK: vpackusdw 8128(%rdx), %zmm29, %zmm18
+// CHECK:  encoding: [0x62,0xe2,0x15,0x40,0x2b,0x52,0x7f]
+          vpackusdw 8128(%rdx), %zmm29, %zmm18
+
+// CHECK: vpackusdw 8192(%rdx), %zmm29, %zmm18
+// CHECK:  encoding: [0x62,0xe2,0x15,0x40,0x2b,0x92,0x00,0x20,0x00,0x00]
+          vpackusdw 8192(%rdx), %zmm29, %zmm18
+
+// CHECK: vpackusdw -8192(%rdx), %zmm29, %zmm18
+// CHECK:  encoding: [0x62,0xe2,0x15,0x40,0x2b,0x52,0x80]
+          vpackusdw -8192(%rdx), %zmm29, %zmm18
+
+// CHECK: vpackusdw -8256(%rdx), %zmm29, %zmm18
+// CHECK:  encoding: [0x62,0xe2,0x15,0x40,0x2b,0x92,0xc0,0xdf,0xff,0xff]
+          vpackusdw -8256(%rdx), %zmm29, %zmm18
+
+// CHECK: vpackusdw 508(%rdx){1to16}, %zmm29, %zmm18
+// CHECK:  encoding: [0x62,0xe2,0x15,0x50,0x2b,0x52,0x7f]
+          vpackusdw 508(%rdx){1to16}, %zmm29, %zmm18
+
+// CHECK: vpackusdw 512(%rdx){1to16}, %zmm29, %zmm18
+// CHECK:  encoding: [0x62,0xe2,0x15,0x50,0x2b,0x92,0x00,0x02,0x00,0x00]
+          vpackusdw 512(%rdx){1to16}, %zmm29, %zmm18
+
+// CHECK: vpackusdw -512(%rdx){1to16}, %zmm29, %zmm18
+// CHECK:  encoding: [0x62,0xe2,0x15,0x50,0x2b,0x52,0x80]
+          vpackusdw -512(%rdx){1to16}, %zmm29, %zmm18
+
+// CHECK: vpackusdw -516(%rdx){1to16}, %zmm29, %zmm18
+// CHECK:  encoding: [0x62,0xe2,0x15,0x50,0x2b,0x92,0xfc,0xfd,0xff,0xff]
+          vpackusdw -516(%rdx){1to16}, %zmm29, %zmm18
+
+// CHECK: vpackuswb %zmm27, %zmm18, %zmm23
+// CHECK:  encoding: [0x62,0x81,0xed,0x40,0x67,0xfb]
+          vpackuswb %zmm27, %zmm18, %zmm23
+
+// CHECK: vpackuswb %zmm27, %zmm18, %zmm23 {%k5}
+// CHECK:  encoding: [0x62,0x81,0xed,0x45,0x67,0xfb]
+          vpackuswb %zmm27, %zmm18, %zmm23 {%k5}
+
+// CHECK: vpackuswb %zmm27, %zmm18, %zmm23 {%k5} {z}
+// CHECK:  encoding: [0x62,0x81,0xed,0xc5,0x67,0xfb]
+          vpackuswb %zmm27, %zmm18, %zmm23 {%k5} {z}
+
+// CHECK: vpackuswb (%rcx), %zmm18, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0xed,0x40,0x67,0x39]
+          vpackuswb (%rcx), %zmm18, %zmm23
+
+// CHECK: vpackuswb 291(%rax,%r14,8), %zmm18, %zmm23
+// CHECK:  encoding: [0x62,0xa1,0xed,0x40,0x67,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vpackuswb 291(%rax,%r14,8), %zmm18, %zmm23
+
+// CHECK: vpackuswb 8128(%rdx), %zmm18, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0xed,0x40,0x67,0x7a,0x7f]
+          vpackuswb 8128(%rdx), %zmm18, %zmm23
+
+// CHECK: vpackuswb 8192(%rdx), %zmm18, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0xed,0x40,0x67,0xba,0x00,0x20,0x00,0x00]
+          vpackuswb 8192(%rdx), %zmm18, %zmm23
+
+// CHECK: vpackuswb -8192(%rdx), %zmm18, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0xed,0x40,0x67,0x7a,0x80]
+          vpackuswb -8192(%rdx), %zmm18, %zmm23
+
+// CHECK: vpackuswb -8256(%rdx), %zmm18, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0xed,0x40,0x67,0xba,0xc0,0xdf,0xff,0xff]
+          vpackuswb -8256(%rdx), %zmm18, %zmm23
+
+// CHECK: vpaddsb %zmm20, %zmm19, %zmm19
+// CHECK:  encoding: [0x62,0xa1,0x65,0x40,0xec,0xdc]
+          vpaddsb %zmm20, %zmm19, %zmm19
+
+// CHECK: vpaddsb %zmm20, %zmm19, %zmm19 {%k6}
+// CHECK:  encoding: [0x62,0xa1,0x65,0x46,0xec,0xdc]
+          vpaddsb %zmm20, %zmm19, %zmm19 {%k6}
+
+// CHECK: vpaddsb %zmm20, %zmm19, %zmm19 {%k6} {z}
+// CHECK:  encoding: [0x62,0xa1,0x65,0xc6,0xec,0xdc]
+          vpaddsb %zmm20, %zmm19, %zmm19 {%k6} {z}
+
+// CHECK: vpaddsb (%rcx), %zmm19, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x65,0x40,0xec,0x19]
+          vpaddsb (%rcx), %zmm19, %zmm19
+
+// CHECK: vpaddsb 291(%rax,%r14,8), %zmm19, %zmm19
+// CHECK:  encoding: [0x62,0xa1,0x65,0x40,0xec,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpaddsb 291(%rax,%r14,8), %zmm19, %zmm19
+
+// CHECK: vpaddsb 8128(%rdx), %zmm19, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x65,0x40,0xec,0x5a,0x7f]
+          vpaddsb 8128(%rdx), %zmm19, %zmm19
+
+// CHECK: vpaddsb 8192(%rdx), %zmm19, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x65,0x40,0xec,0x9a,0x00,0x20,0x00,0x00]
+          vpaddsb 8192(%rdx), %zmm19, %zmm19
+
+// CHECK: vpaddsb -8192(%rdx), %zmm19, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x65,0x40,0xec,0x5a,0x80]
+          vpaddsb -8192(%rdx), %zmm19, %zmm19
+
+// CHECK: vpaddsb -8256(%rdx), %zmm19, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x65,0x40,0xec,0x9a,0xc0,0xdf,0xff,0xff]
+          vpaddsb -8256(%rdx), %zmm19, %zmm19
+
+// CHECK: vpaddsw %zmm22, %zmm19, %zmm20
+// CHECK:  encoding: [0x62,0xa1,0x65,0x40,0xed,0xe6]
+          vpaddsw %zmm22, %zmm19, %zmm20
+
+// CHECK: vpaddsw %zmm22, %zmm19, %zmm20 {%k2}
+// CHECK:  encoding: [0x62,0xa1,0x65,0x42,0xed,0xe6]
+          vpaddsw %zmm22, %zmm19, %zmm20 {%k2}
+
+// CHECK: vpaddsw %zmm22, %zmm19, %zmm20 {%k2} {z}
+// CHECK:  encoding: [0x62,0xa1,0x65,0xc2,0xed,0xe6]
+          vpaddsw %zmm22, %zmm19, %zmm20 {%k2} {z}
+
+// CHECK: vpaddsw (%rcx), %zmm19, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x65,0x40,0xed,0x21]
+          vpaddsw (%rcx), %zmm19, %zmm20
+
+// CHECK: vpaddsw 291(%rax,%r14,8), %zmm19, %zmm20
+// CHECK:  encoding: [0x62,0xa1,0x65,0x40,0xed,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpaddsw 291(%rax,%r14,8), %zmm19, %zmm20
+
+// CHECK: vpaddsw 8128(%rdx), %zmm19, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x65,0x40,0xed,0x62,0x7f]
+          vpaddsw 8128(%rdx), %zmm19, %zmm20
+
+// CHECK: vpaddsw 8192(%rdx), %zmm19, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x65,0x40,0xed,0xa2,0x00,0x20,0x00,0x00]
+          vpaddsw 8192(%rdx), %zmm19, %zmm20
+
+// CHECK: vpaddsw -8192(%rdx), %zmm19, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x65,0x40,0xed,0x62,0x80]
+          vpaddsw -8192(%rdx), %zmm19, %zmm20
+
+// CHECK: vpaddsw -8256(%rdx), %zmm19, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x65,0x40,0xed,0xa2,0xc0,0xdf,0xff,0xff]
+          vpaddsw -8256(%rdx), %zmm19, %zmm20
+
+// CHECK: vpaddusb %zmm25, %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x01,0x15,0x40,0xdc,0xe9]
+          vpaddusb %zmm25, %zmm29, %zmm29
+
+// CHECK: vpaddusb %zmm25, %zmm29, %zmm29 {%k1}
+// CHECK:  encoding: [0x62,0x01,0x15,0x41,0xdc,0xe9]
+          vpaddusb %zmm25, %zmm29, %zmm29 {%k1}
+
+// CHECK: vpaddusb %zmm25, %zmm29, %zmm29 {%k1} {z}
+// CHECK:  encoding: [0x62,0x01,0x15,0xc1,0xdc,0xe9]
+          vpaddusb %zmm25, %zmm29, %zmm29 {%k1} {z}
+
+// CHECK: vpaddusb (%rcx), %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x61,0x15,0x40,0xdc,0x29]
+          vpaddusb (%rcx), %zmm29, %zmm29
+
+// CHECK: vpaddusb 291(%rax,%r14,8), %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x21,0x15,0x40,0xdc,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpaddusb 291(%rax,%r14,8), %zmm29, %zmm29
+
+// CHECK: vpaddusb 8128(%rdx), %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x61,0x15,0x40,0xdc,0x6a,0x7f]
+          vpaddusb 8128(%rdx), %zmm29, %zmm29
+
+// CHECK: vpaddusb 8192(%rdx), %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x61,0x15,0x40,0xdc,0xaa,0x00,0x20,0x00,0x00]
+          vpaddusb 8192(%rdx), %zmm29, %zmm29
+
+// CHECK: vpaddusb -8192(%rdx), %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x61,0x15,0x40,0xdc,0x6a,0x80]
+          vpaddusb -8192(%rdx), %zmm29, %zmm29
+
+// CHECK: vpaddusb -8256(%rdx), %zmm29, %zmm29
+// CHECK:  encoding: [0x62,0x61,0x15,0x40,0xdc,0xaa,0xc0,0xdf,0xff,0xff]
+          vpaddusb -8256(%rdx), %zmm29, %zmm29
+
+// CHECK: vpaddusw %zmm17, %zmm25, %zmm21
+// CHECK:  encoding: [0x62,0xa1,0x35,0x40,0xdd,0xe9]
+          vpaddusw %zmm17, %zmm25, %zmm21
+
+// CHECK: vpaddusw %zmm17, %zmm25, %zmm21 {%k4}
+// CHECK:  encoding: [0x62,0xa1,0x35,0x44,0xdd,0xe9]
+          vpaddusw %zmm17, %zmm25, %zmm21 {%k4}
+
+// CHECK: vpaddusw %zmm17, %zmm25, %zmm21 {%k4} {z}
+// CHECK:  encoding: [0x62,0xa1,0x35,0xc4,0xdd,0xe9]
+          vpaddusw %zmm17, %zmm25, %zmm21 {%k4} {z}
+
+// CHECK: vpaddusw (%rcx), %zmm25, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x35,0x40,0xdd,0x29]
+          vpaddusw (%rcx), %zmm25, %zmm21
+
+// CHECK: vpaddusw 291(%rax,%r14,8), %zmm25, %zmm21
+// CHECK:  encoding: [0x62,0xa1,0x35,0x40,0xdd,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpaddusw 291(%rax,%r14,8), %zmm25, %zmm21
+
+// CHECK: vpaddusw 8128(%rdx), %zmm25, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x35,0x40,0xdd,0x6a,0x7f]
+          vpaddusw 8128(%rdx), %zmm25, %zmm21
+
+// CHECK: vpaddusw 8192(%rdx), %zmm25, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x35,0x40,0xdd,0xaa,0x00,0x20,0x00,0x00]
+          vpaddusw 8192(%rdx), %zmm25, %zmm21
+
+// CHECK: vpaddusw -8192(%rdx), %zmm25, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x35,0x40,0xdd,0x6a,0x80]
+          vpaddusw -8192(%rdx), %zmm25, %zmm21
+
+// CHECK: vpaddusw -8256(%rdx), %zmm25, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x35,0x40,0xdd,0xaa,0xc0,0xdf,0xff,0xff]
+          vpaddusw -8256(%rdx), %zmm25, %zmm21
+
+// CHECK: vpsubsb %zmm20, %zmm24, %zmm25
+// CHECK:  encoding: [0x62,0x21,0x3d,0x40,0xe8,0xcc]
+          vpsubsb %zmm20, %zmm24, %zmm25
+
+// CHECK: vpsubsb %zmm20, %zmm24, %zmm25 {%k2}
+// CHECK:  encoding: [0x62,0x21,0x3d,0x42,0xe8,0xcc]
+          vpsubsb %zmm20, %zmm24, %zmm25 {%k2}
+
+// CHECK: vpsubsb %zmm20, %zmm24, %zmm25 {%k2} {z}
+// CHECK:  encoding: [0x62,0x21,0x3d,0xc2,0xe8,0xcc]
+          vpsubsb %zmm20, %zmm24, %zmm25 {%k2} {z}
+
+// CHECK: vpsubsb (%rcx), %zmm24, %zmm25
+// CHECK:  encoding: [0x62,0x61,0x3d,0x40,0xe8,0x09]
+          vpsubsb (%rcx), %zmm24, %zmm25
+
+// CHECK: vpsubsb 291(%rax,%r14,8), %zmm24, %zmm25
+// CHECK:  encoding: [0x62,0x21,0x3d,0x40,0xe8,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpsubsb 291(%rax,%r14,8), %zmm24, %zmm25
+
+// CHECK: vpsubsb 8128(%rdx), %zmm24, %zmm25
+// CHECK:  encoding: [0x62,0x61,0x3d,0x40,0xe8,0x4a,0x7f]
+          vpsubsb 8128(%rdx), %zmm24, %zmm25
+
+// CHECK: vpsubsb 8192(%rdx), %zmm24, %zmm25
+// CHECK:  encoding: [0x62,0x61,0x3d,0x40,0xe8,0x8a,0x00,0x20,0x00,0x00]
+          vpsubsb 8192(%rdx), %zmm24, %zmm25
+
+// CHECK: vpsubsb -8192(%rdx), %zmm24, %zmm25
+// CHECK:  encoding: [0x62,0x61,0x3d,0x40,0xe8,0x4a,0x80]
+          vpsubsb -8192(%rdx), %zmm24, %zmm25
+
+// CHECK: vpsubsb -8256(%rdx), %zmm24, %zmm25
+// CHECK:  encoding: [0x62,0x61,0x3d,0x40,0xe8,0x8a,0xc0,0xdf,0xff,0xff]
+          vpsubsb -8256(%rdx), %zmm24, %zmm25
+
+// CHECK: vpsubsw %zmm23, %zmm22, %zmm23
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x40,0xe9,0xff]
+          vpsubsw %zmm23, %zmm22, %zmm23
+
+// CHECK: vpsubsw %zmm23, %zmm22, %zmm23 {%k3}
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x43,0xe9,0xff]
+          vpsubsw %zmm23, %zmm22, %zmm23 {%k3}
+
+// CHECK: vpsubsw %zmm23, %zmm22, %zmm23 {%k3} {z}
+// CHECK:  encoding: [0x62,0xa1,0x4d,0xc3,0xe9,0xff]
+          vpsubsw %zmm23, %zmm22, %zmm23 {%k3} {z}
+
+// CHECK: vpsubsw (%rcx), %zmm22, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x40,0xe9,0x39]
+          vpsubsw (%rcx), %zmm22, %zmm23
+
+// CHECK: vpsubsw 291(%rax,%r14,8), %zmm22, %zmm23
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x40,0xe9,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vpsubsw 291(%rax,%r14,8), %zmm22, %zmm23
+
+// CHECK: vpsubsw 8128(%rdx), %zmm22, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x40,0xe9,0x7a,0x7f]
+          vpsubsw 8128(%rdx), %zmm22, %zmm23
+
+// CHECK: vpsubsw 8192(%rdx), %zmm22, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x40,0xe9,0xba,0x00,0x20,0x00,0x00]
+          vpsubsw 8192(%rdx), %zmm22, %zmm23
+
+// CHECK: vpsubsw -8192(%rdx), %zmm22, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x40,0xe9,0x7a,0x80]
+          vpsubsw -8192(%rdx), %zmm22, %zmm23
+
+// CHECK: vpsubsw -8256(%rdx), %zmm22, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x40,0xe9,0xba,0xc0,0xdf,0xff,0xff]
+          vpsubsw -8256(%rdx), %zmm22, %zmm23
+
+// CHECK: vpsubusb %zmm22, %zmm21, %zmm24
+// CHECK:  encoding: [0x62,0x21,0x55,0x40,0xd8,0xc6]
+          vpsubusb %zmm22, %zmm21, %zmm24
+
+// CHECK: vpsubusb %zmm22, %zmm21, %zmm24 {%k4}
+// CHECK:  encoding: [0x62,0x21,0x55,0x44,0xd8,0xc6]
+          vpsubusb %zmm22, %zmm21, %zmm24 {%k4}
+
+// CHECK: vpsubusb %zmm22, %zmm21, %zmm24 {%k4} {z}
+// CHECK:  encoding: [0x62,0x21,0x55,0xc4,0xd8,0xc6]
+          vpsubusb %zmm22, %zmm21, %zmm24 {%k4} {z}
+
+// CHECK: vpsubusb (%rcx), %zmm21, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x55,0x40,0xd8,0x01]
+          vpsubusb (%rcx), %zmm21, %zmm24
+
+// CHECK: vpsubusb 291(%rax,%r14,8), %zmm21, %zmm24
+// CHECK:  encoding: [0x62,0x21,0x55,0x40,0xd8,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vpsubusb 291(%rax,%r14,8), %zmm21, %zmm24
+
+// CHECK: vpsubusb 8128(%rdx), %zmm21, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x55,0x40,0xd8,0x42,0x7f]
+          vpsubusb 8128(%rdx), %zmm21, %zmm24
+
+// CHECK: vpsubusb 8192(%rdx), %zmm21, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x55,0x40,0xd8,0x82,0x00,0x20,0x00,0x00]
+          vpsubusb 8192(%rdx), %zmm21, %zmm24
+
+// CHECK: vpsubusb -8192(%rdx), %zmm21, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x55,0x40,0xd8,0x42,0x80]
+          vpsubusb -8192(%rdx), %zmm21, %zmm24
+
+// CHECK: vpsubusb -8256(%rdx), %zmm21, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x55,0x40,0xd8,0x82,0xc0,0xdf,0xff,0xff]
+          vpsubusb -8256(%rdx), %zmm21, %zmm24
+
+// CHECK: vpsubusw %zmm23, %zmm17, %zmm25
+// CHECK:  encoding: [0x62,0x21,0x75,0x40,0xd9,0xcf]
+          vpsubusw %zmm23, %zmm17, %zmm25
+
+// CHECK: vpsubusw %zmm23, %zmm17, %zmm25 {%k1}
+// CHECK:  encoding: [0x62,0x21,0x75,0x41,0xd9,0xcf]
+          vpsubusw %zmm23, %zmm17, %zmm25 {%k1}
+
+// CHECK: vpsubusw %zmm23, %zmm17, %zmm25 {%k1} {z}
+// CHECK:  encoding: [0x62,0x21,0x75,0xc1,0xd9,0xcf]
+          vpsubusw %zmm23, %zmm17, %zmm25 {%k1} {z}
+
+// CHECK: vpsubusw (%rcx), %zmm17, %zmm25
+// CHECK:  encoding: [0x62,0x61,0x75,0x40,0xd9,0x09]
+          vpsubusw (%rcx), %zmm17, %zmm25
+
+// CHECK: vpsubusw 291(%rax,%r14,8), %zmm17, %zmm25
+// CHECK:  encoding: [0x62,0x21,0x75,0x40,0xd9,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpsubusw 291(%rax,%r14,8), %zmm17, %zmm25
+
+// CHECK: vpsubusw 8128(%rdx), %zmm17, %zmm25
+// CHECK:  encoding: [0x62,0x61,0x75,0x40,0xd9,0x4a,0x7f]
+          vpsubusw 8128(%rdx), %zmm17, %zmm25
+
+// CHECK: vpsubusw 8192(%rdx), %zmm17, %zmm25
+// CHECK:  encoding: [0x62,0x61,0x75,0x40,0xd9,0x8a,0x00,0x20,0x00,0x00]
+          vpsubusw 8192(%rdx), %zmm17, %zmm25
+
+// CHECK: vpsubusw -8192(%rdx), %zmm17, %zmm25
+// CHECK:  encoding: [0x62,0x61,0x75,0x40,0xd9,0x4a,0x80]
+          vpsubusw -8192(%rdx), %zmm17, %zmm25
+
+// CHECK: vpsubusw -8256(%rdx), %zmm17, %zmm25
+// CHECK:  encoding: [0x62,0x61,0x75,0x40,0xd9,0x8a,0xc0,0xdf,0xff,0xff]
+          vpsubusw -8256(%rdx), %zmm17, %zmm25
+
+// CHECK: vpaddb %zmm26, %zmm29, %zmm21
+// CHECK:  encoding: [0x62,0x81,0x15,0x40,0xfc,0xea]
+          vpaddb %zmm26, %zmm29, %zmm21
+
+// CHECK: vpaddb %zmm26, %zmm29, %zmm21 {%k5}
+// CHECK:  encoding: [0x62,0x81,0x15,0x45,0xfc,0xea]
+          vpaddb %zmm26, %zmm29, %zmm21 {%k5}
+
+// CHECK: vpaddb %zmm26, %zmm29, %zmm21 {%k5} {z}
+// CHECK:  encoding: [0x62,0x81,0x15,0xc5,0xfc,0xea]
+          vpaddb %zmm26, %zmm29, %zmm21 {%k5} {z}
+
+// CHECK: vpaddb (%rcx), %zmm29, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x15,0x40,0xfc,0x29]
+          vpaddb (%rcx), %zmm29, %zmm21
+
+// CHECK: vpaddb 4660(%rax,%r14,8), %zmm29, %zmm21
+// CHECK:  encoding: [0x62,0xa1,0x15,0x40,0xfc,0xac,0xf0,0x34,0x12,0x00,0x00]
+          vpaddb 4660(%rax,%r14,8), %zmm29, %zmm21
+
+// CHECK: vpaddb 8128(%rdx), %zmm29, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x15,0x40,0xfc,0x6a,0x7f]
+          vpaddb 8128(%rdx), %zmm29, %zmm21
+
+// CHECK: vpaddb 8192(%rdx), %zmm29, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x15,0x40,0xfc,0xaa,0x00,0x20,0x00,0x00]
+          vpaddb 8192(%rdx), %zmm29, %zmm21
+
+// CHECK: vpaddb -8192(%rdx), %zmm29, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x15,0x40,0xfc,0x6a,0x80]
+          vpaddb -8192(%rdx), %zmm29, %zmm21
+
+// CHECK: vpaddb -8256(%rdx), %zmm29, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x15,0x40,0xfc,0xaa,0xc0,0xdf,0xff,0xff]
+          vpaddb -8256(%rdx), %zmm29, %zmm21
+
+// CHECK: vpaddsb %zmm19, %zmm24, %zmm18
+// CHECK:  encoding: [0x62,0xa1,0x3d,0x40,0xec,0xd3]
+          vpaddsb %zmm19, %zmm24, %zmm18
+
+// CHECK: vpaddsb %zmm19, %zmm24, %zmm18 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0x3d,0x41,0xec,0xd3]
+          vpaddsb %zmm19, %zmm24, %zmm18 {%k1}
+
+// CHECK: vpaddsb %zmm19, %zmm24, %zmm18 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0x3d,0xc1,0xec,0xd3]
+          vpaddsb %zmm19, %zmm24, %zmm18 {%k1} {z}
+
+// CHECK: vpaddsb (%rcx), %zmm24, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x3d,0x40,0xec,0x11]
+          vpaddsb (%rcx), %zmm24, %zmm18
+
+// CHECK: vpaddsb 4660(%rax,%r14,8), %zmm24, %zmm18
+// CHECK:  encoding: [0x62,0xa1,0x3d,0x40,0xec,0x94,0xf0,0x34,0x12,0x00,0x00]
+          vpaddsb 4660(%rax,%r14,8), %zmm24, %zmm18
+
+// CHECK: vpaddsb 8128(%rdx), %zmm24, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x3d,0x40,0xec,0x52,0x7f]
+          vpaddsb 8128(%rdx), %zmm24, %zmm18
+
+// CHECK: vpaddsb 8192(%rdx), %zmm24, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x3d,0x40,0xec,0x92,0x00,0x20,0x00,0x00]
+          vpaddsb 8192(%rdx), %zmm24, %zmm18
+
+// CHECK: vpaddsb -8192(%rdx), %zmm24, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x3d,0x40,0xec,0x52,0x80]
+          vpaddsb -8192(%rdx), %zmm24, %zmm18
+
+// CHECK: vpaddsb -8256(%rdx), %zmm24, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x3d,0x40,0xec,0x92,0xc0,0xdf,0xff,0xff]
+          vpaddsb -8256(%rdx), %zmm24, %zmm18
+
+// CHECK: vpaddsw %zmm28, %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0x81,0x75,0x40,0xed,0xe4]
+          vpaddsw %zmm28, %zmm17, %zmm20
+
+// CHECK: vpaddsw %zmm28, %zmm17, %zmm20 {%k2}
+// CHECK:  encoding: [0x62,0x81,0x75,0x42,0xed,0xe4]
+          vpaddsw %zmm28, %zmm17, %zmm20 {%k2}
+
+// CHECK: vpaddsw %zmm28, %zmm17, %zmm20 {%k2} {z}
+// CHECK:  encoding: [0x62,0x81,0x75,0xc2,0xed,0xe4]
+          vpaddsw %zmm28, %zmm17, %zmm20 {%k2} {z}
+
+// CHECK: vpaddsw (%rcx), %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x75,0x40,0xed,0x21]
+          vpaddsw (%rcx), %zmm17, %zmm20
+
+// CHECK: vpaddsw 4660(%rax,%r14,8), %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xa1,0x75,0x40,0xed,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vpaddsw 4660(%rax,%r14,8), %zmm17, %zmm20
+
+// CHECK: vpaddsw 8128(%rdx), %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x75,0x40,0xed,0x62,0x7f]
+          vpaddsw 8128(%rdx), %zmm17, %zmm20
+
+// CHECK: vpaddsw 8192(%rdx), %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x75,0x40,0xed,0xa2,0x00,0x20,0x00,0x00]
+          vpaddsw 8192(%rdx), %zmm17, %zmm20
+
+// CHECK: vpaddsw -8192(%rdx), %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x75,0x40,0xed,0x62,0x80]
+          vpaddsw -8192(%rdx), %zmm17, %zmm20
+
+// CHECK: vpaddsw -8256(%rdx), %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x75,0x40,0xed,0xa2,0xc0,0xdf,0xff,0xff]
+          vpaddsw -8256(%rdx), %zmm17, %zmm20
+
+// CHECK: vpaddusb %zmm22, %zmm27, %zmm19
+// CHECK:  encoding: [0x62,0xa1,0x25,0x40,0xdc,0xde]
+          vpaddusb %zmm22, %zmm27, %zmm19
+
+// CHECK: vpaddusb %zmm22, %zmm27, %zmm19 {%k7}
+// CHECK:  encoding: [0x62,0xa1,0x25,0x47,0xdc,0xde]
+          vpaddusb %zmm22, %zmm27, %zmm19 {%k7}
+
+// CHECK: vpaddusb %zmm22, %zmm27, %zmm19 {%k7} {z}
+// CHECK:  encoding: [0x62,0xa1,0x25,0xc7,0xdc,0xde]
+          vpaddusb %zmm22, %zmm27, %zmm19 {%k7} {z}
+
+// CHECK: vpaddusb (%rcx), %zmm27, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x25,0x40,0xdc,0x19]
+          vpaddusb (%rcx), %zmm27, %zmm19
+
+// CHECK: vpaddusb 4660(%rax,%r14,8), %zmm27, %zmm19
+// CHECK:  encoding: [0x62,0xa1,0x25,0x40,0xdc,0x9c,0xf0,0x34,0x12,0x00,0x00]
+          vpaddusb 4660(%rax,%r14,8), %zmm27, %zmm19
+
+// CHECK: vpaddusb 8128(%rdx), %zmm27, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x25,0x40,0xdc,0x5a,0x7f]
+          vpaddusb 8128(%rdx), %zmm27, %zmm19
+
+// CHECK: vpaddusb 8192(%rdx), %zmm27, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x25,0x40,0xdc,0x9a,0x00,0x20,0x00,0x00]
+          vpaddusb 8192(%rdx), %zmm27, %zmm19
+
+// CHECK: vpaddusb -8192(%rdx), %zmm27, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x25,0x40,0xdc,0x5a,0x80]
+          vpaddusb -8192(%rdx), %zmm27, %zmm19
+
+// CHECK: vpaddusb -8256(%rdx), %zmm27, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x25,0x40,0xdc,0x9a,0xc0,0xdf,0xff,0xff]
+          vpaddusb -8256(%rdx), %zmm27, %zmm19
+
+// CHECK: vpaddusw %zmm23, %zmm23, %zmm27
+// CHECK:  encoding: [0x62,0x21,0x45,0x40,0xdd,0xdf]
+          vpaddusw %zmm23, %zmm23, %zmm27
+
+// CHECK: vpaddusw %zmm23, %zmm23, %zmm27 {%k7}
+// CHECK:  encoding: [0x62,0x21,0x45,0x47,0xdd,0xdf]
+          vpaddusw %zmm23, %zmm23, %zmm27 {%k7}
+
+// CHECK: vpaddusw %zmm23, %zmm23, %zmm27 {%k7} {z}
+// CHECK:  encoding: [0x62,0x21,0x45,0xc7,0xdd,0xdf]
+          vpaddusw %zmm23, %zmm23, %zmm27 {%k7} {z}
+
+// CHECK: vpaddusw (%rcx), %zmm23, %zmm27
+// CHECK:  encoding: [0x62,0x61,0x45,0x40,0xdd,0x19]
+          vpaddusw (%rcx), %zmm23, %zmm27
+
+// CHECK: vpaddusw 4660(%rax,%r14,8), %zmm23, %zmm27
+// CHECK:  encoding: [0x62,0x21,0x45,0x40,0xdd,0x9c,0xf0,0x34,0x12,0x00,0x00]
+          vpaddusw 4660(%rax,%r14,8), %zmm23, %zmm27
+
+// CHECK: vpaddusw 8128(%rdx), %zmm23, %zmm27
+// CHECK:  encoding: [0x62,0x61,0x45,0x40,0xdd,0x5a,0x7f]
+          vpaddusw 8128(%rdx), %zmm23, %zmm27
+
+// CHECK: vpaddusw 8192(%rdx), %zmm23, %zmm27
+// CHECK:  encoding: [0x62,0x61,0x45,0x40,0xdd,0x9a,0x00,0x20,0x00,0x00]
+          vpaddusw 8192(%rdx), %zmm23, %zmm27
+
+// CHECK: vpaddusw -8192(%rdx), %zmm23, %zmm27
+// CHECK:  encoding: [0x62,0x61,0x45,0x40,0xdd,0x5a,0x80]
+          vpaddusw -8192(%rdx), %zmm23, %zmm27
+
+// CHECK: vpaddusw -8256(%rdx), %zmm23, %zmm27
+// CHECK:  encoding: [0x62,0x61,0x45,0x40,0xdd,0x9a,0xc0,0xdf,0xff,0xff]
+          vpaddusw -8256(%rdx), %zmm23, %zmm27
+
+// CHECK: vpsubsb %zmm18, %zmm28, %zmm17
+// CHECK:  encoding: [0x62,0xa1,0x1d,0x40,0xe8,0xca]
+          vpsubsb %zmm18, %zmm28, %zmm17
+
+// CHECK: vpsubsb %zmm18, %zmm28, %zmm17 {%k5}
+// CHECK:  encoding: [0x62,0xa1,0x1d,0x45,0xe8,0xca]
+          vpsubsb %zmm18, %zmm28, %zmm17 {%k5}
+
+// CHECK: vpsubsb %zmm18, %zmm28, %zmm17 {%k5} {z}
+// CHECK:  encoding: [0x62,0xa1,0x1d,0xc5,0xe8,0xca]
+          vpsubsb %zmm18, %zmm28, %zmm17 {%k5} {z}
+
+// CHECK: vpsubsb (%rcx), %zmm28, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x40,0xe8,0x09]
+          vpsubsb (%rcx), %zmm28, %zmm17
+
+// CHECK: vpsubsb 4660(%rax,%r14,8), %zmm28, %zmm17
+// CHECK:  encoding: [0x62,0xa1,0x1d,0x40,0xe8,0x8c,0xf0,0x34,0x12,0x00,0x00]
+          vpsubsb 4660(%rax,%r14,8), %zmm28, %zmm17
+
+// CHECK: vpsubsb 8128(%rdx), %zmm28, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x40,0xe8,0x4a,0x7f]
+          vpsubsb 8128(%rdx), %zmm28, %zmm17
+
+// CHECK: vpsubsb 8192(%rdx), %zmm28, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x40,0xe8,0x8a,0x00,0x20,0x00,0x00]
+          vpsubsb 8192(%rdx), %zmm28, %zmm17
+
+// CHECK: vpsubsb -8192(%rdx), %zmm28, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x40,0xe8,0x4a,0x80]
+          vpsubsb -8192(%rdx), %zmm28, %zmm17
+
+// CHECK: vpsubsb -8256(%rdx), %zmm28, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x40,0xe8,0x8a,0xc0,0xdf,0xff,0xff]
+          vpsubsb -8256(%rdx), %zmm28, %zmm17
+
+// CHECK: vpsubsw %zmm26, %zmm24, %zmm30
+// CHECK:  encoding: [0x62,0x01,0x3d,0x40,0xe9,0xf2]
+          vpsubsw %zmm26, %zmm24, %zmm30
+
+// CHECK: vpsubsw %zmm26, %zmm24, %zmm30 {%k3}
+// CHECK:  encoding: [0x62,0x01,0x3d,0x43,0xe9,0xf2]
+          vpsubsw %zmm26, %zmm24, %zmm30 {%k3}
+
+// CHECK: vpsubsw %zmm26, %zmm24, %zmm30 {%k3} {z}
+// CHECK:  encoding: [0x62,0x01,0x3d,0xc3,0xe9,0xf2]
+          vpsubsw %zmm26, %zmm24, %zmm30 {%k3} {z}
+
+// CHECK: vpsubsw (%rcx), %zmm24, %zmm30
+// CHECK:  encoding: [0x62,0x61,0x3d,0x40,0xe9,0x31]
+          vpsubsw (%rcx), %zmm24, %zmm30
+
+// CHECK: vpsubsw 4660(%rax,%r14,8), %zmm24, %zmm30
+// CHECK:  encoding: [0x62,0x21,0x3d,0x40,0xe9,0xb4,0xf0,0x34,0x12,0x00,0x00]
+          vpsubsw 4660(%rax,%r14,8), %zmm24, %zmm30
+
+// CHECK: vpsubsw 8128(%rdx), %zmm24, %zmm30
+// CHECK:  encoding: [0x62,0x61,0x3d,0x40,0xe9,0x72,0x7f]
+          vpsubsw 8128(%rdx), %zmm24, %zmm30
+
+// CHECK: vpsubsw 8192(%rdx), %zmm24, %zmm30
+// CHECK:  encoding: [0x62,0x61,0x3d,0x40,0xe9,0xb2,0x00,0x20,0x00,0x00]
+          vpsubsw 8192(%rdx), %zmm24, %zmm30
+
+// CHECK: vpsubsw -8192(%rdx), %zmm24, %zmm30
+// CHECK:  encoding: [0x62,0x61,0x3d,0x40,0xe9,0x72,0x80]
+          vpsubsw -8192(%rdx), %zmm24, %zmm30
+
+// CHECK: vpsubsw -8256(%rdx), %zmm24, %zmm30
+// CHECK:  encoding: [0x62,0x61,0x3d,0x40,0xe9,0xb2,0xc0,0xdf,0xff,0xff]
+          vpsubsw -8256(%rdx), %zmm24, %zmm30
+
+// CHECK: vpsubusb %zmm28, %zmm29, %zmm28
+// CHECK:  encoding: [0x62,0x01,0x15,0x40,0xd8,0xe4]
+          vpsubusb %zmm28, %zmm29, %zmm28
+
+// CHECK: vpsubusb %zmm28, %zmm29, %zmm28 {%k2}
+// CHECK:  encoding: [0x62,0x01,0x15,0x42,0xd8,0xe4]
+          vpsubusb %zmm28, %zmm29, %zmm28 {%k2}
+
+// CHECK: vpsubusb %zmm28, %zmm29, %zmm28 {%k2} {z}
+// CHECK:  encoding: [0x62,0x01,0x15,0xc2,0xd8,0xe4]
+          vpsubusb %zmm28, %zmm29, %zmm28 {%k2} {z}
+
+// CHECK: vpsubusb (%rcx), %zmm29, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x15,0x40,0xd8,0x21]
+          vpsubusb (%rcx), %zmm29, %zmm28
+
+// CHECK: vpsubusb 4660(%rax,%r14,8), %zmm29, %zmm28
+// CHECK:  encoding: [0x62,0x21,0x15,0x40,0xd8,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vpsubusb 4660(%rax,%r14,8), %zmm29, %zmm28
+
+// CHECK: vpsubusb 8128(%rdx), %zmm29, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x15,0x40,0xd8,0x62,0x7f]
+          vpsubusb 8128(%rdx), %zmm29, %zmm28
+
+// CHECK: vpsubusb 8192(%rdx), %zmm29, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x15,0x40,0xd8,0xa2,0x00,0x20,0x00,0x00]
+          vpsubusb 8192(%rdx), %zmm29, %zmm28
+
+// CHECK: vpsubusb -8192(%rdx), %zmm29, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x15,0x40,0xd8,0x62,0x80]
+          vpsubusb -8192(%rdx), %zmm29, %zmm28
+
+// CHECK: vpsubusb -8256(%rdx), %zmm29, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x15,0x40,0xd8,0xa2,0xc0,0xdf,0xff,0xff]
+          vpsubusb -8256(%rdx), %zmm29, %zmm28
+
+// CHECK: vpsubusw %zmm19, %zmm28, %zmm22
+// CHECK:  encoding: [0x62,0xa1,0x1d,0x40,0xd9,0xf3]
+          vpsubusw %zmm19, %zmm28, %zmm22
+
+// CHECK: vpsubusw %zmm19, %zmm28, %zmm22 {%k5}
+// CHECK:  encoding: [0x62,0xa1,0x1d,0x45,0xd9,0xf3]
+          vpsubusw %zmm19, %zmm28, %zmm22 {%k5}
+
+// CHECK: vpsubusw %zmm19, %zmm28, %zmm22 {%k5} {z}
+// CHECK:  encoding: [0x62,0xa1,0x1d,0xc5,0xd9,0xf3]
+          vpsubusw %zmm19, %zmm28, %zmm22 {%k5} {z}
+
+// CHECK: vpsubusw (%rcx), %zmm28, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x40,0xd9,0x31]
+          vpsubusw (%rcx), %zmm28, %zmm22
+
+// CHECK: vpsubusw 4660(%rax,%r14,8), %zmm28, %zmm22
+// CHECK:  encoding: [0x62,0xa1,0x1d,0x40,0xd9,0xb4,0xf0,0x34,0x12,0x00,0x00]
+          vpsubusw 4660(%rax,%r14,8), %zmm28, %zmm22
+
+// CHECK: vpsubusw 8128(%rdx), %zmm28, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x40,0xd9,0x72,0x7f]
+          vpsubusw 8128(%rdx), %zmm28, %zmm22
+
+// CHECK: vpsubusw 8192(%rdx), %zmm28, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x40,0xd9,0xb2,0x00,0x20,0x00,0x00]
+          vpsubusw 8192(%rdx), %zmm28, %zmm22
+
+// CHECK: vpsubusw -8192(%rdx), %zmm28, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x40,0xd9,0x72,0x80]
+          vpsubusw -8192(%rdx), %zmm28, %zmm22
+
+// CHECK: vpsubusw -8256(%rdx), %zmm28, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x40,0xd9,0xb2,0xc0,0xdf,0xff,0xff]
+          vpsubusw -8256(%rdx), %zmm28, %zmm22
+
+// CHECK: vpaddsb %zmm25, %zmm19, %zmm28
+// CHECK:  encoding: [0x62,0x01,0x65,0x40,0xec,0xe1]
+          vpaddsb %zmm25, %zmm19, %zmm28
+
+// CHECK: vpaddsb %zmm25, %zmm19, %zmm28 {%k4}
+// CHECK:  encoding: [0x62,0x01,0x65,0x44,0xec,0xe1]
+          vpaddsb %zmm25, %zmm19, %zmm28 {%k4}
+
+// CHECK: vpaddsb %zmm25, %zmm19, %zmm28 {%k4} {z}
+// CHECK:  encoding: [0x62,0x01,0x65,0xc4,0xec,0xe1]
+          vpaddsb %zmm25, %zmm19, %zmm28 {%k4} {z}
+
+// CHECK: vpaddsb (%rcx), %zmm19, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x65,0x40,0xec,0x21]
+          vpaddsb (%rcx), %zmm19, %zmm28
+
+// CHECK: vpaddsb 291(%rax,%r14,8), %zmm19, %zmm28
+// CHECK:  encoding: [0x62,0x21,0x65,0x40,0xec,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpaddsb 291(%rax,%r14,8), %zmm19, %zmm28
+
+// CHECK: vpaddsb 8128(%rdx), %zmm19, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x65,0x40,0xec,0x62,0x7f]
+          vpaddsb 8128(%rdx), %zmm19, %zmm28
+
+// CHECK: vpaddsb 8192(%rdx), %zmm19, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x65,0x40,0xec,0xa2,0x00,0x20,0x00,0x00]
+          vpaddsb 8192(%rdx), %zmm19, %zmm28
+
+// CHECK: vpaddsb -8192(%rdx), %zmm19, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x65,0x40,0xec,0x62,0x80]
+          vpaddsb -8192(%rdx), %zmm19, %zmm28
+
+// CHECK: vpaddsb -8256(%rdx), %zmm19, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x65,0x40,0xec,0xa2,0xc0,0xdf,0xff,0xff]
+          vpaddsb -8256(%rdx), %zmm19, %zmm28
+
+// CHECK: vpaddsw %zmm20, %zmm22, %zmm20
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x40,0xed,0xe4]
+          vpaddsw %zmm20, %zmm22, %zmm20
+
+// CHECK: vpaddsw %zmm20, %zmm22, %zmm20 {%k7}
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x47,0xed,0xe4]
+          vpaddsw %zmm20, %zmm22, %zmm20 {%k7}
+
+// CHECK: vpaddsw %zmm20, %zmm22, %zmm20 {%k7} {z}
+// CHECK:  encoding: [0x62,0xa1,0x4d,0xc7,0xed,0xe4]
+          vpaddsw %zmm20, %zmm22, %zmm20 {%k7} {z}
+
+// CHECK: vpaddsw (%rcx), %zmm22, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x40,0xed,0x21]
+          vpaddsw (%rcx), %zmm22, %zmm20
+
+// CHECK: vpaddsw 291(%rax,%r14,8), %zmm22, %zmm20
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x40,0xed,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpaddsw 291(%rax,%r14,8), %zmm22, %zmm20
+
+// CHECK: vpaddsw 8128(%rdx), %zmm22, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x40,0xed,0x62,0x7f]
+          vpaddsw 8128(%rdx), %zmm22, %zmm20
+
+// CHECK: vpaddsw 8192(%rdx), %zmm22, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x40,0xed,0xa2,0x00,0x20,0x00,0x00]
+          vpaddsw 8192(%rdx), %zmm22, %zmm20
+
+// CHECK: vpaddsw -8192(%rdx), %zmm22, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x40,0xed,0x62,0x80]
+          vpaddsw -8192(%rdx), %zmm22, %zmm20
+
+// CHECK: vpaddsw -8256(%rdx), %zmm22, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x40,0xed,0xa2,0xc0,0xdf,0xff,0xff]
+          vpaddsw -8256(%rdx), %zmm22, %zmm20
+
+// CHECK: vpaddusb %zmm17, %zmm27, %zmm26
+// CHECK:  encoding: [0x62,0x21,0x25,0x40,0xdc,0xd1]
+          vpaddusb %zmm17, %zmm27, %zmm26
+
+// CHECK: vpaddusb %zmm17, %zmm27, %zmm26 {%k3}
+// CHECK:  encoding: [0x62,0x21,0x25,0x43,0xdc,0xd1]
+          vpaddusb %zmm17, %zmm27, %zmm26 {%k3}
+
+// CHECK: vpaddusb %zmm17, %zmm27, %zmm26 {%k3} {z}
+// CHECK:  encoding: [0x62,0x21,0x25,0xc3,0xdc,0xd1]
+          vpaddusb %zmm17, %zmm27, %zmm26 {%k3} {z}
+
+// CHECK: vpaddusb (%rcx), %zmm27, %zmm26
+// CHECK:  encoding: [0x62,0x61,0x25,0x40,0xdc,0x11]
+          vpaddusb (%rcx), %zmm27, %zmm26
+
+// CHECK: vpaddusb 291(%rax,%r14,8), %zmm27, %zmm26
+// CHECK:  encoding: [0x62,0x21,0x25,0x40,0xdc,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vpaddusb 291(%rax,%r14,8), %zmm27, %zmm26
+
+// CHECK: vpaddusb 8128(%rdx), %zmm27, %zmm26
+// CHECK:  encoding: [0x62,0x61,0x25,0x40,0xdc,0x52,0x7f]
+          vpaddusb 8128(%rdx), %zmm27, %zmm26
+
+// CHECK: vpaddusb 8192(%rdx), %zmm27, %zmm26
+// CHECK:  encoding: [0x62,0x61,0x25,0x40,0xdc,0x92,0x00,0x20,0x00,0x00]
+          vpaddusb 8192(%rdx), %zmm27, %zmm26
+
+// CHECK: vpaddusb -8192(%rdx), %zmm27, %zmm26
+// CHECK:  encoding: [0x62,0x61,0x25,0x40,0xdc,0x52,0x80]
+          vpaddusb -8192(%rdx), %zmm27, %zmm26
+
+// CHECK: vpaddusb -8256(%rdx), %zmm27, %zmm26
+// CHECK:  encoding: [0x62,0x61,0x25,0x40,0xdc,0x92,0xc0,0xdf,0xff,0xff]
+          vpaddusb -8256(%rdx), %zmm27, %zmm26
+
+// CHECK: vpaddusw %zmm20, %zmm22, %zmm21
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x40,0xdd,0xec]
+          vpaddusw %zmm20, %zmm22, %zmm21
+
+// CHECK: vpaddusw %zmm20, %zmm22, %zmm21 {%k7}
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x47,0xdd,0xec]
+          vpaddusw %zmm20, %zmm22, %zmm21 {%k7}
+
+// CHECK: vpaddusw %zmm20, %zmm22, %zmm21 {%k7} {z}
+// CHECK:  encoding: [0x62,0xa1,0x4d,0xc7,0xdd,0xec]
+          vpaddusw %zmm20, %zmm22, %zmm21 {%k7} {z}
+
+// CHECK: vpaddusw (%rcx), %zmm22, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x40,0xdd,0x29]
+          vpaddusw (%rcx), %zmm22, %zmm21
+
+// CHECK: vpaddusw 291(%rax,%r14,8), %zmm22, %zmm21
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x40,0xdd,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpaddusw 291(%rax,%r14,8), %zmm22, %zmm21
+
+// CHECK: vpaddusw 8128(%rdx), %zmm22, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x40,0xdd,0x6a,0x7f]
+          vpaddusw 8128(%rdx), %zmm22, %zmm21
+
+// CHECK: vpaddusw 8192(%rdx), %zmm22, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x40,0xdd,0xaa,0x00,0x20,0x00,0x00]
+          vpaddusw 8192(%rdx), %zmm22, %zmm21
+
+// CHECK: vpaddusw -8192(%rdx), %zmm22, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x40,0xdd,0x6a,0x80]
+          vpaddusw -8192(%rdx), %zmm22, %zmm21
+
+// CHECK: vpaddusw -8256(%rdx), %zmm22, %zmm21
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x40,0xdd,0xaa,0xc0,0xdf,0xff,0xff]
+          vpaddusw -8256(%rdx), %zmm22, %zmm21
+
+// CHECK: vpsubsb %zmm28, %zmm21, %zmm19
+// CHECK:  encoding: [0x62,0x81,0x55,0x40,0xe8,0xdc]
+          vpsubsb %zmm28, %zmm21, %zmm19
+
+// CHECK: vpsubsb %zmm28, %zmm21, %zmm19 {%k2}
+// CHECK:  encoding: [0x62,0x81,0x55,0x42,0xe8,0xdc]
+          vpsubsb %zmm28, %zmm21, %zmm19 {%k2}
+
+// CHECK: vpsubsb %zmm28, %zmm21, %zmm19 {%k2} {z}
+// CHECK:  encoding: [0x62,0x81,0x55,0xc2,0xe8,0xdc]
+          vpsubsb %zmm28, %zmm21, %zmm19 {%k2} {z}
+
+// CHECK: vpsubsb (%rcx), %zmm21, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x55,0x40,0xe8,0x19]
+          vpsubsb (%rcx), %zmm21, %zmm19
+
+// CHECK: vpsubsb 291(%rax,%r14,8), %zmm21, %zmm19
+// CHECK:  encoding: [0x62,0xa1,0x55,0x40,0xe8,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpsubsb 291(%rax,%r14,8), %zmm21, %zmm19
+
+// CHECK: vpsubsb 8128(%rdx), %zmm21, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x55,0x40,0xe8,0x5a,0x7f]
+          vpsubsb 8128(%rdx), %zmm21, %zmm19
+
+// CHECK: vpsubsb 8192(%rdx), %zmm21, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x55,0x40,0xe8,0x9a,0x00,0x20,0x00,0x00]
+          vpsubsb 8192(%rdx), %zmm21, %zmm19
+
+// CHECK: vpsubsb -8192(%rdx), %zmm21, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x55,0x40,0xe8,0x5a,0x80]
+          vpsubsb -8192(%rdx), %zmm21, %zmm19
+
+// CHECK: vpsubsb -8256(%rdx), %zmm21, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x55,0x40,0xe8,0x9a,0xc0,0xdf,0xff,0xff]
+          vpsubsb -8256(%rdx), %zmm21, %zmm19
+
+// CHECK: vpsubsw %zmm23, %zmm23, %zmm23
+// CHECK:  encoding: [0x62,0xa1,0x45,0x40,0xe9,0xff]
+          vpsubsw %zmm23, %zmm23, %zmm23
+
+// CHECK: vpsubsw %zmm23, %zmm23, %zmm23 {%k6}
+// CHECK:  encoding: [0x62,0xa1,0x45,0x46,0xe9,0xff]
+          vpsubsw %zmm23, %zmm23, %zmm23 {%k6}
+
+// CHECK: vpsubsw %zmm23, %zmm23, %zmm23 {%k6} {z}
+// CHECK:  encoding: [0x62,0xa1,0x45,0xc6,0xe9,0xff]
+          vpsubsw %zmm23, %zmm23, %zmm23 {%k6} {z}
+
+// CHECK: vpsubsw (%rcx), %zmm23, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0x45,0x40,0xe9,0x39]
+          vpsubsw (%rcx), %zmm23, %zmm23
+
+// CHECK: vpsubsw 291(%rax,%r14,8), %zmm23, %zmm23
+// CHECK:  encoding: [0x62,0xa1,0x45,0x40,0xe9,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vpsubsw 291(%rax,%r14,8), %zmm23, %zmm23
+
+// CHECK: vpsubsw 8128(%rdx), %zmm23, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0x45,0x40,0xe9,0x7a,0x7f]
+          vpsubsw 8128(%rdx), %zmm23, %zmm23
+
+// CHECK: vpsubsw 8192(%rdx), %zmm23, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0x45,0x40,0xe9,0xba,0x00,0x20,0x00,0x00]
+          vpsubsw 8192(%rdx), %zmm23, %zmm23
+
+// CHECK: vpsubsw -8192(%rdx), %zmm23, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0x45,0x40,0xe9,0x7a,0x80]
+          vpsubsw -8192(%rdx), %zmm23, %zmm23
+
+// CHECK: vpsubsw -8256(%rdx), %zmm23, %zmm23
+// CHECK:  encoding: [0x62,0xe1,0x45,0x40,0xe9,0xba,0xc0,0xdf,0xff,0xff]
+          vpsubsw -8256(%rdx), %zmm23, %zmm23
+
+// CHECK: vpsubusb %zmm25, %zmm29, %zmm27
+// CHECK:  encoding: [0x62,0x01,0x15,0x40,0xd8,0xd9]
+          vpsubusb %zmm25, %zmm29, %zmm27
+
+// CHECK: vpsubusb %zmm25, %zmm29, %zmm27 {%k4}
+// CHECK:  encoding: [0x62,0x01,0x15,0x44,0xd8,0xd9]
+          vpsubusb %zmm25, %zmm29, %zmm27 {%k4}
+
+// CHECK: vpsubusb %zmm25, %zmm29, %zmm27 {%k4} {z}
+// CHECK:  encoding: [0x62,0x01,0x15,0xc4,0xd8,0xd9]
+          vpsubusb %zmm25, %zmm29, %zmm27 {%k4} {z}
+
+// CHECK: vpsubusb (%rcx), %zmm29, %zmm27
+// CHECK:  encoding: [0x62,0x61,0x15,0x40,0xd8,0x19]
+          vpsubusb (%rcx), %zmm29, %zmm27
+
+// CHECK: vpsubusb 291(%rax,%r14,8), %zmm29, %zmm27
+// CHECK:  encoding: [0x62,0x21,0x15,0x40,0xd8,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpsubusb 291(%rax,%r14,8), %zmm29, %zmm27
+
+// CHECK: vpsubusb 8128(%rdx), %zmm29, %zmm27
+// CHECK:  encoding: [0x62,0x61,0x15,0x40,0xd8,0x5a,0x7f]
+          vpsubusb 8128(%rdx), %zmm29, %zmm27
+
+// CHECK: vpsubusb 8192(%rdx), %zmm29, %zmm27
+// CHECK:  encoding: [0x62,0x61,0x15,0x40,0xd8,0x9a,0x00,0x20,0x00,0x00]
+          vpsubusb 8192(%rdx), %zmm29, %zmm27
+
+// CHECK: vpsubusb -8192(%rdx), %zmm29, %zmm27
+// CHECK:  encoding: [0x62,0x61,0x15,0x40,0xd8,0x5a,0x80]
+          vpsubusb -8192(%rdx), %zmm29, %zmm27
+
+// CHECK: vpsubusb -8256(%rdx), %zmm29, %zmm27
+// CHECK:  encoding: [0x62,0x61,0x15,0x40,0xd8,0x9a,0xc0,0xdf,0xff,0xff]
+          vpsubusb -8256(%rdx), %zmm29, %zmm27
+
+// CHECK: vpsubusw %zmm25, %zmm20, %zmm20
+// CHECK:  encoding: [0x62,0x81,0x5d,0x40,0xd9,0xe1]
+          vpsubusw %zmm25, %zmm20, %zmm20
+
+// CHECK: vpsubusw %zmm25, %zmm20, %zmm20 {%k6}
+// CHECK:  encoding: [0x62,0x81,0x5d,0x46,0xd9,0xe1]
+          vpsubusw %zmm25, %zmm20, %zmm20 {%k6}
+
+// CHECK: vpsubusw %zmm25, %zmm20, %zmm20 {%k6} {z}
+// CHECK:  encoding: [0x62,0x81,0x5d,0xc6,0xd9,0xe1]
+          vpsubusw %zmm25, %zmm20, %zmm20 {%k6} {z}
+
+// CHECK: vpsubusw (%rcx), %zmm20, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x40,0xd9,0x21]
+          vpsubusw (%rcx), %zmm20, %zmm20
+
+// CHECK: vpsubusw 291(%rax,%r14,8), %zmm20, %zmm20
+// CHECK:  encoding: [0x62,0xa1,0x5d,0x40,0xd9,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsubusw 291(%rax,%r14,8), %zmm20, %zmm20
+
+// CHECK: vpsubusw 8128(%rdx), %zmm20, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x40,0xd9,0x62,0x7f]
+          vpsubusw 8128(%rdx), %zmm20, %zmm20
+
+// CHECK: vpsubusw 8192(%rdx), %zmm20, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x40,0xd9,0xa2,0x00,0x20,0x00,0x00]
+          vpsubusw 8192(%rdx), %zmm20, %zmm20
+
+// CHECK: vpsubusw -8192(%rdx), %zmm20, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x40,0xd9,0x62,0x80]
+          vpsubusw -8192(%rdx), %zmm20, %zmm20
+
+// CHECK: vpsubusw -8256(%rdx), %zmm20, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x40,0xd9,0xa2,0xc0,0xdf,0xff,0xff]
+          vpsubusw -8256(%rdx), %zmm20, %zmm20
+
diff --git a/test/MC/X86/x86-64-avx512bw_vl.s b/test/MC/X86/x86-64-avx512bw_vl.s
index e84755022eb6..bd16b0ed95c7 100644
--- a/test/MC/X86/x86-64-avx512bw_vl.s
+++ b/test/MC/X86/x86-64-avx512bw_vl.s
@@ -1312,6 +1312,150 @@
 // CHECK:  encoding: [0x62,0xe2,0x25,0x20,0x3a,0xa2,0xe0,0xef,0xff,0xff]
           vpminuw -4128(%rdx), %ymm27, %ymm20
 
+// CHECK: vpmovsxbw %xmm23, %xmm27
+// CHECK:  encoding: [0x62,0x22,0x7d,0x08,0x20,0xdf]
+          vpmovsxbw %xmm23, %xmm27
+
+// CHECK: vpmovsxbw %xmm23, %xmm27 {%k7}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x0f,0x20,0xdf]
+          vpmovsxbw %xmm23, %xmm27 {%k7}
+
+// CHECK: vpmovsxbw %xmm23, %xmm27 {%k7} {z}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x8f,0x20,0xdf]
+          vpmovsxbw %xmm23, %xmm27 {%k7} {z}
+
+// CHECK: vpmovsxbw (%rcx), %xmm27
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x20,0x19]
+          vpmovsxbw (%rcx), %xmm27
+
+// CHECK: vpmovsxbw 291(%rax,%r14,8), %xmm27
+// CHECK:  encoding: [0x62,0x22,0x7d,0x08,0x20,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpmovsxbw 291(%rax,%r14,8), %xmm27
+
+// CHECK: vpmovsxbw 1016(%rdx), %xmm27
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x20,0x5a,0x7f]
+          vpmovsxbw 1016(%rdx), %xmm27
+
+// CHECK: vpmovsxbw 1024(%rdx), %xmm27
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x20,0x9a,0x00,0x04,0x00,0x00]
+          vpmovsxbw 1024(%rdx), %xmm27
+
+// CHECK: vpmovsxbw -1024(%rdx), %xmm27
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x20,0x5a,0x80]
+          vpmovsxbw -1024(%rdx), %xmm27
+
+// CHECK: vpmovsxbw -1032(%rdx), %xmm27
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x20,0x9a,0xf8,0xfb,0xff,0xff]
+          vpmovsxbw -1032(%rdx), %xmm27
+
+// CHECK: vpmovsxbw %xmm23, %ymm21
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x28,0x20,0xef]
+          vpmovsxbw %xmm23, %ymm21
+
+// CHECK: vpmovsxbw %xmm23, %ymm21 {%k7}
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x2f,0x20,0xef]
+          vpmovsxbw %xmm23, %ymm21 {%k7}
+
+// CHECK: vpmovsxbw %xmm23, %ymm21 {%k7} {z}
+// CHECK:  encoding: [0x62,0xa2,0x7d,0xaf,0x20,0xef]
+          vpmovsxbw %xmm23, %ymm21 {%k7} {z}
+
+// CHECK: vpmovsxbw (%rcx), %ymm21
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x20,0x29]
+          vpmovsxbw (%rcx), %ymm21
+
+// CHECK: vpmovsxbw 291(%rax,%r14,8), %ymm21
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x28,0x20,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpmovsxbw 291(%rax,%r14,8), %ymm21
+
+// CHECK: vpmovsxbw 2032(%rdx), %ymm21
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x20,0x6a,0x7f]
+          vpmovsxbw 2032(%rdx), %ymm21
+
+// CHECK: vpmovsxbw 2048(%rdx), %ymm21
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x20,0xaa,0x00,0x08,0x00,0x00]
+          vpmovsxbw 2048(%rdx), %ymm21
+
+// CHECK: vpmovsxbw -2048(%rdx), %ymm21
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x20,0x6a,0x80]
+          vpmovsxbw -2048(%rdx), %ymm21
+
+// CHECK: vpmovsxbw -2064(%rdx), %ymm21
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x20,0xaa,0xf0,0xf7,0xff,0xff]
+          vpmovsxbw -2064(%rdx), %ymm21
+
+// CHECK: vpmovzxbw %xmm29, %xmm30
+// CHECK:  encoding: [0x62,0x02,0x7d,0x08,0x30,0xf5]
+          vpmovzxbw %xmm29, %xmm30
+
+// CHECK: vpmovzxbw %xmm29, %xmm30 {%k7}
+// CHECK:  encoding: [0x62,0x02,0x7d,0x0f,0x30,0xf5]
+          vpmovzxbw %xmm29, %xmm30 {%k7}
+
+// CHECK: vpmovzxbw %xmm29, %xmm30 {%k7} {z}
+// CHECK:  encoding: [0x62,0x02,0x7d,0x8f,0x30,0xf5]
+          vpmovzxbw %xmm29, %xmm30 {%k7} {z}
+
+// CHECK: vpmovzxbw (%rcx), %xmm30
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x30,0x31]
+          vpmovzxbw (%rcx), %xmm30
+
+// CHECK: vpmovzxbw 291(%rax,%r14,8), %xmm30
+// CHECK:  encoding: [0x62,0x22,0x7d,0x08,0x30,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpmovzxbw 291(%rax,%r14,8), %xmm30
+
+// CHECK: vpmovzxbw 1016(%rdx), %xmm30
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x30,0x72,0x7f]
+          vpmovzxbw 1016(%rdx), %xmm30
+
+// CHECK: vpmovzxbw 1024(%rdx), %xmm30
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x30,0xb2,0x00,0x04,0x00,0x00]
+          vpmovzxbw 1024(%rdx), %xmm30
+
+// CHECK: vpmovzxbw -1024(%rdx), %xmm30
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x30,0x72,0x80]
+          vpmovzxbw -1024(%rdx), %xmm30
+
+// CHECK: vpmovzxbw -1032(%rdx), %xmm30
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x30,0xb2,0xf8,0xfb,0xff,0xff]
+          vpmovzxbw -1032(%rdx), %xmm30
+
+// CHECK: vpmovzxbw %xmm29, %ymm22
+// CHECK:  encoding: [0x62,0x82,0x7d,0x28,0x30,0xf5]
+          vpmovzxbw %xmm29, %ymm22
+
+// CHECK: vpmovzxbw %xmm29, %ymm22 {%k2}
+// CHECK:  encoding: [0x62,0x82,0x7d,0x2a,0x30,0xf5]
+          vpmovzxbw %xmm29, %ymm22 {%k2}
+
+// CHECK: vpmovzxbw %xmm29, %ymm22 {%k2} {z}
+// CHECK:  encoding: [0x62,0x82,0x7d,0xaa,0x30,0xf5]
+          vpmovzxbw %xmm29, %ymm22 {%k2} {z}
+
+// CHECK: vpmovzxbw (%rcx), %ymm22
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x30,0x31]
+          vpmovzxbw (%rcx), %ymm22
+
+// CHECK: vpmovzxbw 291(%rax,%r14,8), %ymm22
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x28,0x30,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpmovzxbw 291(%rax,%r14,8), %ymm22
+
+// CHECK: vpmovzxbw 2032(%rdx), %ymm22
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x30,0x72,0x7f]
+          vpmovzxbw 2032(%rdx), %ymm22
+
+// CHECK: vpmovzxbw 2048(%rdx), %ymm22
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x30,0xb2,0x00,0x08,0x00,0x00]
+          vpmovzxbw 2048(%rdx), %ymm22
+
+// CHECK: vpmovzxbw -2048(%rdx), %ymm22
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x30,0x72,0x80]
+          vpmovzxbw -2048(%rdx), %ymm22
+
+// CHECK: vpmovzxbw -2064(%rdx), %ymm22
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x30,0xb2,0xf0,0xf7,0xff,0xff]
+          vpmovzxbw -2064(%rdx), %ymm22
+
 // CHECK: vpmullw %xmm26, %xmm19, %xmm29
 // CHECK:  encoding: [0x62,0x01,0x65,0x00,0xd5,0xea]
           vpmullw %xmm26, %xmm19, %xmm29
@@ -1783,3 +1927,3851 @@
 // CHECK: vmovdqu16 %ymm29, -4128(%rdx)
 // CHECK:  encoding: [0x62,0x61,0xff,0x28,0x7f,0xaa,0xe0,0xef,0xff,0xff]
           vmovdqu16 %ymm29, -4128(%rdx)
+
+// CHECK: vpsllw %xmm26, %xmm23, %xmm19
+// CHECK:  encoding: [0x62,0x81,0x45,0x00,0xf1,0xda]
+          vpsllw %xmm26, %xmm23, %xmm19
+
+// CHECK: vpsllw %xmm26, %xmm23, %xmm19 {%k7}
+// CHECK:  encoding: [0x62,0x81,0x45,0x07,0xf1,0xda]
+          vpsllw %xmm26, %xmm23, %xmm19 {%k7}
+
+// CHECK: vpsllw %xmm26, %xmm23, %xmm19 {%k7} {z}
+// CHECK:  encoding: [0x62,0x81,0x45,0x87,0xf1,0xda]
+          vpsllw %xmm26, %xmm23, %xmm19 {%k7} {z}
+
+// CHECK: vpsllw (%rcx), %xmm23, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x45,0x00,0xf1,0x19]
+          vpsllw (%rcx), %xmm23, %xmm19
+
+// CHECK: vpsllw 291(%rax,%r14,8), %xmm23, %xmm19
+// CHECK:  encoding: [0x62,0xa1,0x45,0x00,0xf1,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpsllw 291(%rax,%r14,8), %xmm23, %xmm19
+
+// CHECK: vpsllw 2032(%rdx), %xmm23, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x45,0x00,0xf1,0x5a,0x7f]
+          vpsllw 2032(%rdx), %xmm23, %xmm19
+
+// CHECK: vpsllw 2048(%rdx), %xmm23, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x45,0x00,0xf1,0x9a,0x00,0x08,0x00,0x00]
+          vpsllw 2048(%rdx), %xmm23, %xmm19
+
+// CHECK: vpsllw -2048(%rdx), %xmm23, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x45,0x00,0xf1,0x5a,0x80]
+          vpsllw -2048(%rdx), %xmm23, %xmm19
+
+// CHECK: vpsllw -2064(%rdx), %xmm23, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x45,0x00,0xf1,0x9a,0xf0,0xf7,0xff,0xff]
+          vpsllw -2064(%rdx), %xmm23, %xmm19
+
+// CHECK: vpsllw %xmm26, %ymm21, %ymm20
+// CHECK:  encoding: [0x62,0x81,0x55,0x20,0xf1,0xe2]
+          vpsllw %xmm26, %ymm21, %ymm20
+
+// CHECK: vpsllw %xmm26, %ymm21, %ymm20 {%k7}
+// CHECK:  encoding: [0x62,0x81,0x55,0x27,0xf1,0xe2]
+          vpsllw %xmm26, %ymm21, %ymm20 {%k7}
+
+// CHECK: vpsllw %xmm26, %ymm21, %ymm20 {%k7} {z}
+// CHECK:  encoding: [0x62,0x81,0x55,0xa7,0xf1,0xe2]
+          vpsllw %xmm26, %ymm21, %ymm20 {%k7} {z}
+
+// CHECK: vpsllw (%rcx), %ymm21, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xf1,0x21]
+          vpsllw (%rcx), %ymm21, %ymm20
+
+// CHECK: vpsllw 291(%rax,%r14,8), %ymm21, %ymm20
+// CHECK:  encoding: [0x62,0xa1,0x55,0x20,0xf1,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsllw 291(%rax,%r14,8), %ymm21, %ymm20
+
+// CHECK: vpsllw 2032(%rdx), %ymm21, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xf1,0x62,0x7f]
+          vpsllw 2032(%rdx), %ymm21, %ymm20
+
+// CHECK: vpsllw 2048(%rdx), %ymm21, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xf1,0xa2,0x00,0x08,0x00,0x00]
+          vpsllw 2048(%rdx), %ymm21, %ymm20
+
+// CHECK: vpsllw -2048(%rdx), %ymm21, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xf1,0x62,0x80]
+          vpsllw -2048(%rdx), %ymm21, %ymm20
+
+// CHECK: vpsllw -2064(%rdx), %ymm21, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xf1,0xa2,0xf0,0xf7,0xff,0xff]
+          vpsllw -2064(%rdx), %ymm21, %ymm20
+
+// CHECK: vpsraw %xmm28, %xmm28, %xmm17
+// CHECK:  encoding: [0x62,0x81,0x1d,0x00,0xe1,0xcc]
+          vpsraw %xmm28, %xmm28, %xmm17
+
+// CHECK: vpsraw %xmm28, %xmm28, %xmm17 {%k1}
+// CHECK:  encoding: [0x62,0x81,0x1d,0x01,0xe1,0xcc]
+          vpsraw %xmm28, %xmm28, %xmm17 {%k1}
+
+// CHECK: vpsraw %xmm28, %xmm28, %xmm17 {%k1} {z}
+// CHECK:  encoding: [0x62,0x81,0x1d,0x81,0xe1,0xcc]
+          vpsraw %xmm28, %xmm28, %xmm17 {%k1} {z}
+
+// CHECK: vpsraw (%rcx), %xmm28, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x00,0xe1,0x09]
+          vpsraw (%rcx), %xmm28, %xmm17
+
+// CHECK: vpsraw 291(%rax,%r14,8), %xmm28, %xmm17
+// CHECK:  encoding: [0x62,0xa1,0x1d,0x00,0xe1,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpsraw 291(%rax,%r14,8), %xmm28, %xmm17
+
+// CHECK: vpsraw 2032(%rdx), %xmm28, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x00,0xe1,0x4a,0x7f]
+          vpsraw 2032(%rdx), %xmm28, %xmm17
+
+// CHECK: vpsraw 2048(%rdx), %xmm28, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x00,0xe1,0x8a,0x00,0x08,0x00,0x00]
+          vpsraw 2048(%rdx), %xmm28, %xmm17
+
+// CHECK: vpsraw -2048(%rdx), %xmm28, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x00,0xe1,0x4a,0x80]
+          vpsraw -2048(%rdx), %xmm28, %xmm17
+
+// CHECK: vpsraw -2064(%rdx), %xmm28, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x00,0xe1,0x8a,0xf0,0xf7,0xff,0xff]
+          vpsraw -2064(%rdx), %xmm28, %xmm17
+
+// CHECK: vpsraw %xmm19, %ymm26, %ymm18
+// CHECK:  encoding: [0x62,0xa1,0x2d,0x20,0xe1,0xd3]
+          vpsraw %xmm19, %ymm26, %ymm18
+
+// CHECK: vpsraw %xmm19, %ymm26, %ymm18 {%k7}
+// CHECK:  encoding: [0x62,0xa1,0x2d,0x27,0xe1,0xd3]
+          vpsraw %xmm19, %ymm26, %ymm18 {%k7}
+
+// CHECK: vpsraw %xmm19, %ymm26, %ymm18 {%k7} {z}
+// CHECK:  encoding: [0x62,0xa1,0x2d,0xa7,0xe1,0xd3]
+          vpsraw %xmm19, %ymm26, %ymm18 {%k7} {z}
+
+// CHECK: vpsraw (%rcx), %ymm26, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x20,0xe1,0x11]
+          vpsraw (%rcx), %ymm26, %ymm18
+
+// CHECK: vpsraw 291(%rax,%r14,8), %ymm26, %ymm18
+// CHECK:  encoding: [0x62,0xa1,0x2d,0x20,0xe1,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vpsraw 291(%rax,%r14,8), %ymm26, %ymm18
+
+// CHECK: vpsraw 2032(%rdx), %ymm26, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x20,0xe1,0x52,0x7f]
+          vpsraw 2032(%rdx), %ymm26, %ymm18
+
+// CHECK: vpsraw 2048(%rdx), %ymm26, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x20,0xe1,0x92,0x00,0x08,0x00,0x00]
+          vpsraw 2048(%rdx), %ymm26, %ymm18
+
+// CHECK: vpsraw -2048(%rdx), %ymm26, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x20,0xe1,0x52,0x80]
+          vpsraw -2048(%rdx), %ymm26, %ymm18
+
+// CHECK: vpsraw -2064(%rdx), %ymm26, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x20,0xe1,0x92,0xf0,0xf7,0xff,0xff]
+          vpsraw -2064(%rdx), %ymm26, %ymm18
+
+// CHECK: vpsrlw %xmm27, %xmm29, %xmm30
+// CHECK:  encoding: [0x62,0x01,0x15,0x00,0xd1,0xf3]
+          vpsrlw %xmm27, %xmm29, %xmm30
+
+// CHECK: vpsrlw %xmm27, %xmm29, %xmm30 {%k1}
+// CHECK:  encoding: [0x62,0x01,0x15,0x01,0xd1,0xf3]
+          vpsrlw %xmm27, %xmm29, %xmm30 {%k1}
+
+// CHECK: vpsrlw %xmm27, %xmm29, %xmm30 {%k1} {z}
+// CHECK:  encoding: [0x62,0x01,0x15,0x81,0xd1,0xf3]
+          vpsrlw %xmm27, %xmm29, %xmm30 {%k1} {z}
+
+// CHECK: vpsrlw (%rcx), %xmm29, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x15,0x00,0xd1,0x31]
+          vpsrlw (%rcx), %xmm29, %xmm30
+
+// CHECK: vpsrlw 291(%rax,%r14,8), %xmm29, %xmm30
+// CHECK:  encoding: [0x62,0x21,0x15,0x00,0xd1,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpsrlw 291(%rax,%r14,8), %xmm29, %xmm30
+
+// CHECK: vpsrlw 2032(%rdx), %xmm29, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x15,0x00,0xd1,0x72,0x7f]
+          vpsrlw 2032(%rdx), %xmm29, %xmm30
+
+// CHECK: vpsrlw 2048(%rdx), %xmm29, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x15,0x00,0xd1,0xb2,0x00,0x08,0x00,0x00]
+          vpsrlw 2048(%rdx), %xmm29, %xmm30
+
+// CHECK: vpsrlw -2048(%rdx), %xmm29, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x15,0x00,0xd1,0x72,0x80]
+          vpsrlw -2048(%rdx), %xmm29, %xmm30
+
+// CHECK: vpsrlw -2064(%rdx), %xmm29, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x15,0x00,0xd1,0xb2,0xf0,0xf7,0xff,0xff]
+          vpsrlw -2064(%rdx), %xmm29, %xmm30
+
+// CHECK: vpsrlw %xmm27, %ymm18, %ymm28
+// CHECK:  encoding: [0x62,0x01,0x6d,0x20,0xd1,0xe3]
+          vpsrlw %xmm27, %ymm18, %ymm28
+
+// CHECK: vpsrlw %xmm27, %ymm18, %ymm28 {%k2}
+// CHECK:  encoding: [0x62,0x01,0x6d,0x22,0xd1,0xe3]
+          vpsrlw %xmm27, %ymm18, %ymm28 {%k2}
+
+// CHECK: vpsrlw %xmm27, %ymm18, %ymm28 {%k2} {z}
+// CHECK:  encoding: [0x62,0x01,0x6d,0xa2,0xd1,0xe3]
+          vpsrlw %xmm27, %ymm18, %ymm28 {%k2} {z}
+
+// CHECK: vpsrlw (%rcx), %ymm18, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x6d,0x20,0xd1,0x21]
+          vpsrlw (%rcx), %ymm18, %ymm28
+
+// CHECK: vpsrlw 291(%rax,%r14,8), %ymm18, %ymm28
+// CHECK:  encoding: [0x62,0x21,0x6d,0x20,0xd1,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsrlw 291(%rax,%r14,8), %ymm18, %ymm28
+
+// CHECK: vpsrlw 2032(%rdx), %ymm18, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x6d,0x20,0xd1,0x62,0x7f]
+          vpsrlw 2032(%rdx), %ymm18, %ymm28
+
+// CHECK: vpsrlw 2048(%rdx), %ymm18, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x6d,0x20,0xd1,0xa2,0x00,0x08,0x00,0x00]
+          vpsrlw 2048(%rdx), %ymm18, %ymm28
+
+// CHECK: vpsrlw -2048(%rdx), %ymm18, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x6d,0x20,0xd1,0x62,0x80]
+          vpsrlw -2048(%rdx), %ymm18, %ymm28
+
+// CHECK: vpsrlw -2064(%rdx), %ymm18, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x6d,0x20,0xd1,0xa2,0xf0,0xf7,0xff,0xff]
+          vpsrlw -2064(%rdx), %ymm18, %ymm28
+
+// CHECK: vpsrlw $171, %xmm21, %xmm22
+// CHECK:  encoding: [0x62,0xb1,0x4d,0x00,0x71,0xd5,0xab]
+          vpsrlw $171, %xmm21, %xmm22
+
+// CHECK: vpsrlw $171, %xmm21, %xmm22 {%k7}
+// CHECK:  encoding: [0x62,0xb1,0x4d,0x07,0x71,0xd5,0xab]
+          vpsrlw $171, %xmm21, %xmm22 {%k7}
+
+// CHECK: vpsrlw $171, %xmm21, %xmm22 {%k7} {z}
+// CHECK:  encoding: [0x62,0xb1,0x4d,0x87,0x71,0xd5,0xab]
+          vpsrlw $171, %xmm21, %xmm22 {%k7} {z}
+
+// CHECK: vpsrlw $123, %xmm21, %xmm22
+// CHECK:  encoding: [0x62,0xb1,0x4d,0x00,0x71,0xd5,0x7b]
+          vpsrlw $123, %xmm21, %xmm22
+
+// CHECK: vpsrlw $123, (%rcx), %xmm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x00,0x71,0x11,0x7b]
+          vpsrlw $123, (%rcx), %xmm22
+
+// CHECK: vpsrlw $123, 291(%rax,%r14,8), %xmm22
+// CHECK:  encoding: [0x62,0xb1,0x4d,0x00,0x71,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpsrlw $123, 291(%rax,%r14,8), %xmm22
+
+// CHECK: vpsrlw $123, 2032(%rdx), %xmm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x00,0x71,0x52,0x7f,0x7b]
+          vpsrlw $123, 2032(%rdx), %xmm22
+
+// CHECK: vpsrlw $123, 2048(%rdx), %xmm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x00,0x71,0x92,0x00,0x08,0x00,0x00,0x7b]
+          vpsrlw $123, 2048(%rdx), %xmm22
+
+// CHECK: vpsrlw $123, -2048(%rdx), %xmm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x00,0x71,0x52,0x80,0x7b]
+          vpsrlw $123, -2048(%rdx), %xmm22
+
+// CHECK: vpsrlw $123, -2064(%rdx), %xmm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x00,0x71,0x92,0xf0,0xf7,0xff,0xff,0x7b]
+          vpsrlw $123, -2064(%rdx), %xmm22
+
+// CHECK: vpsrlw $171, %ymm19, %ymm27
+// CHECK:  encoding: [0x62,0xb1,0x25,0x20,0x71,0xd3,0xab]
+          vpsrlw $171, %ymm19, %ymm27
+
+// CHECK: vpsrlw $171, %ymm19, %ymm27 {%k3}
+// CHECK:  encoding: [0x62,0xb1,0x25,0x23,0x71,0xd3,0xab]
+          vpsrlw $171, %ymm19, %ymm27 {%k3}
+
+// CHECK: vpsrlw $171, %ymm19, %ymm27 {%k3} {z}
+// CHECK:  encoding: [0x62,0xb1,0x25,0xa3,0x71,0xd3,0xab]
+          vpsrlw $171, %ymm19, %ymm27 {%k3} {z}
+
+// CHECK: vpsrlw $123, %ymm19, %ymm27
+// CHECK:  encoding: [0x62,0xb1,0x25,0x20,0x71,0xd3,0x7b]
+          vpsrlw $123, %ymm19, %ymm27
+
+// CHECK: vpsrlw $123, (%rcx), %ymm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x20,0x71,0x11,0x7b]
+          vpsrlw $123, (%rcx), %ymm27
+
+// CHECK: vpsrlw $123, 291(%rax,%r14,8), %ymm27
+// CHECK:  encoding: [0x62,0xb1,0x25,0x20,0x71,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpsrlw $123, 291(%rax,%r14,8), %ymm27
+
+// CHECK: vpsrlw $123, 4064(%rdx), %ymm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x20,0x71,0x52,0x7f,0x7b]
+          vpsrlw $123, 4064(%rdx), %ymm27
+
+// CHECK: vpsrlw $123, 4096(%rdx), %ymm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x20,0x71,0x92,0x00,0x10,0x00,0x00,0x7b]
+          vpsrlw $123, 4096(%rdx), %ymm27
+
+// CHECK: vpsrlw $123, -4096(%rdx), %ymm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x20,0x71,0x52,0x80,0x7b]
+          vpsrlw $123, -4096(%rdx), %ymm27
+
+// CHECK: vpsrlw $123, -4128(%rdx), %ymm27
+// CHECK:  encoding: [0x62,0xf1,0x25,0x20,0x71,0x92,0xe0,0xef,0xff,0xff,0x7b]
+          vpsrlw $123, -4128(%rdx), %ymm27
+
+// CHECK: vpsraw $171, %xmm22, %xmm22
+// CHECK:  encoding: [0x62,0xb1,0x4d,0x00,0x71,0xe6,0xab]
+          vpsraw $171, %xmm22, %xmm22
+
+// CHECK: vpsraw $171, %xmm22, %xmm22 {%k4}
+// CHECK:  encoding: [0x62,0xb1,0x4d,0x04,0x71,0xe6,0xab]
+          vpsraw $171, %xmm22, %xmm22 {%k4}
+
+// CHECK: vpsraw $171, %xmm22, %xmm22 {%k4} {z}
+// CHECK:  encoding: [0x62,0xb1,0x4d,0x84,0x71,0xe6,0xab]
+          vpsraw $171, %xmm22, %xmm22 {%k4} {z}
+
+// CHECK: vpsraw $123, %xmm22, %xmm22
+// CHECK:  encoding: [0x62,0xb1,0x4d,0x00,0x71,0xe6,0x7b]
+          vpsraw $123, %xmm22, %xmm22
+
+// CHECK: vpsraw $123, (%rcx), %xmm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x00,0x71,0x21,0x7b]
+          vpsraw $123, (%rcx), %xmm22
+
+// CHECK: vpsraw $123, 291(%rax,%r14,8), %xmm22
+// CHECK:  encoding: [0x62,0xb1,0x4d,0x00,0x71,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpsraw $123, 291(%rax,%r14,8), %xmm22
+
+// CHECK: vpsraw $123, 2032(%rdx), %xmm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x00,0x71,0x62,0x7f,0x7b]
+          vpsraw $123, 2032(%rdx), %xmm22
+
+// CHECK: vpsraw $123, 2048(%rdx), %xmm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x00,0x71,0xa2,0x00,0x08,0x00,0x00,0x7b]
+          vpsraw $123, 2048(%rdx), %xmm22
+
+// CHECK: vpsraw $123, -2048(%rdx), %xmm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x00,0x71,0x62,0x80,0x7b]
+          vpsraw $123, -2048(%rdx), %xmm22
+
+// CHECK: vpsraw $123, -2064(%rdx), %xmm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x00,0x71,0xa2,0xf0,0xf7,0xff,0xff,0x7b]
+          vpsraw $123, -2064(%rdx), %xmm22
+
+// CHECK: vpsraw $171, %ymm22, %ymm19
+// CHECK:  encoding: [0x62,0xb1,0x65,0x20,0x71,0xe6,0xab]
+          vpsraw $171, %ymm22, %ymm19
+
+// CHECK: vpsraw $171, %ymm22, %ymm19 {%k7}
+// CHECK:  encoding: [0x62,0xb1,0x65,0x27,0x71,0xe6,0xab]
+          vpsraw $171, %ymm22, %ymm19 {%k7}
+
+// CHECK: vpsraw $171, %ymm22, %ymm19 {%k7} {z}
+// CHECK:  encoding: [0x62,0xb1,0x65,0xa7,0x71,0xe6,0xab]
+          vpsraw $171, %ymm22, %ymm19 {%k7} {z}
+
+// CHECK: vpsraw $123, %ymm22, %ymm19
+// CHECK:  encoding: [0x62,0xb1,0x65,0x20,0x71,0xe6,0x7b]
+          vpsraw $123, %ymm22, %ymm19
+
+// CHECK: vpsraw $123, (%rcx), %ymm19
+// CHECK:  encoding: [0x62,0xf1,0x65,0x20,0x71,0x21,0x7b]
+          vpsraw $123, (%rcx), %ymm19
+
+// CHECK: vpsraw $123, 291(%rax,%r14,8), %ymm19
+// CHECK:  encoding: [0x62,0xb1,0x65,0x20,0x71,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpsraw $123, 291(%rax,%r14,8), %ymm19
+
+// CHECK: vpsraw $123, 4064(%rdx), %ymm19
+// CHECK:  encoding: [0x62,0xf1,0x65,0x20,0x71,0x62,0x7f,0x7b]
+          vpsraw $123, 4064(%rdx), %ymm19
+
+// CHECK: vpsraw $123, 4096(%rdx), %ymm19
+// CHECK:  encoding: [0x62,0xf1,0x65,0x20,0x71,0xa2,0x00,0x10,0x00,0x00,0x7b]
+          vpsraw $123, 4096(%rdx), %ymm19
+
+// CHECK: vpsraw $123, -4096(%rdx), %ymm19
+// CHECK:  encoding: [0x62,0xf1,0x65,0x20,0x71,0x62,0x80,0x7b]
+          vpsraw $123, -4096(%rdx), %ymm19
+
+// CHECK: vpsraw $123, -4128(%rdx), %ymm19
+// CHECK:  encoding: [0x62,0xf1,0x65,0x20,0x71,0xa2,0xe0,0xef,0xff,0xff,0x7b]
+          vpsraw $123, -4128(%rdx), %ymm19
+
+// CHECK: vpsrlvw %xmm19, %xmm22, %xmm30
+// CHECK:  encoding: [0x62,0x22,0xcd,0x00,0x10,0xf3]
+          vpsrlvw %xmm19, %xmm22, %xmm30
+
+// CHECK: vpsrlvw %xmm19, %xmm22, %xmm30 {%k7}
+// CHECK:  encoding: [0x62,0x22,0xcd,0x07,0x10,0xf3]
+          vpsrlvw %xmm19, %xmm22, %xmm30 {%k7}
+
+// CHECK: vpsrlvw %xmm19, %xmm22, %xmm30 {%k7} {z}
+// CHECK:  encoding: [0x62,0x22,0xcd,0x87,0x10,0xf3]
+          vpsrlvw %xmm19, %xmm22, %xmm30 {%k7} {z}
+
+// CHECK: vpsrlvw (%rcx), %xmm22, %xmm30
+// CHECK:  encoding: [0x62,0x62,0xcd,0x00,0x10,0x31]
+          vpsrlvw (%rcx), %xmm22, %xmm30
+
+// CHECK: vpsrlvw 291(%rax,%r14,8), %xmm22, %xmm30
+// CHECK:  encoding: [0x62,0x22,0xcd,0x00,0x10,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpsrlvw 291(%rax,%r14,8), %xmm22, %xmm30
+
+// CHECK: vpsrlvw 2032(%rdx), %xmm22, %xmm30
+// CHECK:  encoding: [0x62,0x62,0xcd,0x00,0x10,0x72,0x7f]
+          vpsrlvw 2032(%rdx), %xmm22, %xmm30
+
+// CHECK: vpsrlvw 2048(%rdx), %xmm22, %xmm30
+// CHECK:  encoding: [0x62,0x62,0xcd,0x00,0x10,0xb2,0x00,0x08,0x00,0x00]
+          vpsrlvw 2048(%rdx), %xmm22, %xmm30
+
+// CHECK: vpsrlvw -2048(%rdx), %xmm22, %xmm30
+// CHECK:  encoding: [0x62,0x62,0xcd,0x00,0x10,0x72,0x80]
+          vpsrlvw -2048(%rdx), %xmm22, %xmm30
+
+// CHECK: vpsrlvw -2064(%rdx), %xmm22, %xmm30
+// CHECK:  encoding: [0x62,0x62,0xcd,0x00,0x10,0xb2,0xf0,0xf7,0xff,0xff]
+          vpsrlvw -2064(%rdx), %xmm22, %xmm30
+
+// CHECK: vpsrlvw %ymm27, %ymm25, %ymm30
+// CHECK:  encoding: [0x62,0x02,0xb5,0x20,0x10,0xf3]
+          vpsrlvw %ymm27, %ymm25, %ymm30
+
+// CHECK: vpsrlvw %ymm27, %ymm25, %ymm30 {%k1}
+// CHECK:  encoding: [0x62,0x02,0xb5,0x21,0x10,0xf3]
+          vpsrlvw %ymm27, %ymm25, %ymm30 {%k1}
+
+// CHECK: vpsrlvw %ymm27, %ymm25, %ymm30 {%k1} {z}
+// CHECK:  encoding: [0x62,0x02,0xb5,0xa1,0x10,0xf3]
+          vpsrlvw %ymm27, %ymm25, %ymm30 {%k1} {z}
+
+// CHECK: vpsrlvw (%rcx), %ymm25, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xb5,0x20,0x10,0x31]
+          vpsrlvw (%rcx), %ymm25, %ymm30
+
+// CHECK: vpsrlvw 291(%rax,%r14,8), %ymm25, %ymm30
+// CHECK:  encoding: [0x62,0x22,0xb5,0x20,0x10,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpsrlvw 291(%rax,%r14,8), %ymm25, %ymm30
+
+// CHECK: vpsrlvw 4064(%rdx), %ymm25, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xb5,0x20,0x10,0x72,0x7f]
+          vpsrlvw 4064(%rdx), %ymm25, %ymm30
+
+// CHECK: vpsrlvw 4096(%rdx), %ymm25, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xb5,0x20,0x10,0xb2,0x00,0x10,0x00,0x00]
+          vpsrlvw 4096(%rdx), %ymm25, %ymm30
+
+// CHECK: vpsrlvw -4096(%rdx), %ymm25, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xb5,0x20,0x10,0x72,0x80]
+          vpsrlvw -4096(%rdx), %ymm25, %ymm30
+
+// CHECK: vpsrlvw -4128(%rdx), %ymm25, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xb5,0x20,0x10,0xb2,0xe0,0xef,0xff,0xff]
+          vpsrlvw -4128(%rdx), %ymm25, %ymm30
+
+// CHECK: vpsravw %xmm27, %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x02,0x9d,0x00,0x11,0xe3]
+          vpsravw %xmm27, %xmm28, %xmm28
+
+// CHECK: vpsravw %xmm27, %xmm28, %xmm28 {%k3}
+// CHECK:  encoding: [0x62,0x02,0x9d,0x03,0x11,0xe3]
+          vpsravw %xmm27, %xmm28, %xmm28 {%k3}
+
+// CHECK: vpsravw %xmm27, %xmm28, %xmm28 {%k3} {z}
+// CHECK:  encoding: [0x62,0x02,0x9d,0x83,0x11,0xe3]
+          vpsravw %xmm27, %xmm28, %xmm28 {%k3} {z}
+
+// CHECK: vpsravw (%rcx), %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x9d,0x00,0x11,0x21]
+          vpsravw (%rcx), %xmm28, %xmm28
+
+// CHECK: vpsravw 291(%rax,%r14,8), %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x22,0x9d,0x00,0x11,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsravw 291(%rax,%r14,8), %xmm28, %xmm28
+
+// CHECK: vpsravw 2032(%rdx), %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x9d,0x00,0x11,0x62,0x7f]
+          vpsravw 2032(%rdx), %xmm28, %xmm28
+
+// CHECK: vpsravw 2048(%rdx), %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x9d,0x00,0x11,0xa2,0x00,0x08,0x00,0x00]
+          vpsravw 2048(%rdx), %xmm28, %xmm28
+
+// CHECK: vpsravw -2048(%rdx), %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x9d,0x00,0x11,0x62,0x80]
+          vpsravw -2048(%rdx), %xmm28, %xmm28
+
+// CHECK: vpsravw -2064(%rdx), %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x9d,0x00,0x11,0xa2,0xf0,0xf7,0xff,0xff]
+          vpsravw -2064(%rdx), %xmm28, %xmm28
+
+// CHECK: vpsravw %ymm17, %ymm28, %ymm20
+// CHECK:  encoding: [0x62,0xa2,0x9d,0x20,0x11,0xe1]
+          vpsravw %ymm17, %ymm28, %ymm20
+
+// CHECK: vpsravw %ymm17, %ymm28, %ymm20 {%k5}
+// CHECK:  encoding: [0x62,0xa2,0x9d,0x25,0x11,0xe1]
+          vpsravw %ymm17, %ymm28, %ymm20 {%k5}
+
+// CHECK: vpsravw %ymm17, %ymm28, %ymm20 {%k5} {z}
+// CHECK:  encoding: [0x62,0xa2,0x9d,0xa5,0x11,0xe1]
+          vpsravw %ymm17, %ymm28, %ymm20 {%k5} {z}
+
+// CHECK: vpsravw (%rcx), %ymm28, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0x9d,0x20,0x11,0x21]
+          vpsravw (%rcx), %ymm28, %ymm20
+
+// CHECK: vpsravw 291(%rax,%r14,8), %ymm28, %ymm20
+// CHECK:  encoding: [0x62,0xa2,0x9d,0x20,0x11,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsravw 291(%rax,%r14,8), %ymm28, %ymm20
+
+// CHECK: vpsravw 4064(%rdx), %ymm28, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0x9d,0x20,0x11,0x62,0x7f]
+          vpsravw 4064(%rdx), %ymm28, %ymm20
+
+// CHECK: vpsravw 4096(%rdx), %ymm28, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0x9d,0x20,0x11,0xa2,0x00,0x10,0x00,0x00]
+          vpsravw 4096(%rdx), %ymm28, %ymm20
+
+// CHECK: vpsravw -4096(%rdx), %ymm28, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0x9d,0x20,0x11,0x62,0x80]
+          vpsravw -4096(%rdx), %ymm28, %ymm20
+
+// CHECK: vpsravw -4128(%rdx), %ymm28, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0x9d,0x20,0x11,0xa2,0xe0,0xef,0xff,0xff]
+          vpsravw -4128(%rdx), %ymm28, %ymm20
+
+// CHECK: vpacksswb %xmm20, %xmm29, %xmm17
+// CHECK:  encoding: [0x62,0xa1,0x95,0x00,0x63,0xcc]
+          vpacksswb %xmm20, %xmm29, %xmm17
+
+// CHECK: vpacksswb %xmm20, %xmm29, %xmm17 {%k3}
+// CHECK:  encoding: [0x62,0xa1,0x95,0x03,0x63,0xcc]
+          vpacksswb %xmm20, %xmm29, %xmm17 {%k3}
+
+// CHECK: vpacksswb %xmm20, %xmm29, %xmm17 {%k3} {z}
+// CHECK:  encoding: [0x62,0xa1,0x95,0x83,0x63,0xcc]
+          vpacksswb %xmm20, %xmm29, %xmm17 {%k3} {z}
+
+// CHECK: vpacksswb (%rcx), %xmm29, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x95,0x00,0x63,0x09]
+          vpacksswb (%rcx), %xmm29, %xmm17
+
+// CHECK: vpacksswb 291(%rax,%r14,8), %xmm29, %xmm17
+// CHECK:  encoding: [0x62,0xa1,0x95,0x00,0x63,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpacksswb 291(%rax,%r14,8), %xmm29, %xmm17
+
+// CHECK: vpacksswb 2032(%rdx), %xmm29, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x95,0x00,0x63,0x4a,0x7f]
+          vpacksswb 2032(%rdx), %xmm29, %xmm17
+
+// CHECK: vpacksswb 2048(%rdx), %xmm29, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x95,0x00,0x63,0x8a,0x00,0x08,0x00,0x00]
+          vpacksswb 2048(%rdx), %xmm29, %xmm17
+
+// CHECK: vpacksswb -2048(%rdx), %xmm29, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x95,0x00,0x63,0x4a,0x80]
+          vpacksswb -2048(%rdx), %xmm29, %xmm17
+
+// CHECK: vpacksswb -2064(%rdx), %xmm29, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x95,0x00,0x63,0x8a,0xf0,0xf7,0xff,0xff]
+          vpacksswb -2064(%rdx), %xmm29, %xmm17
+
+// CHECK: vpacksswb %ymm21, %ymm26, %ymm29
+// CHECK:  encoding: [0x62,0x21,0xad,0x20,0x63,0xed]
+          vpacksswb %ymm21, %ymm26, %ymm29
+
+// CHECK: vpacksswb %ymm21, %ymm26, %ymm29 {%k2}
+// CHECK:  encoding: [0x62,0x21,0xad,0x22,0x63,0xed]
+          vpacksswb %ymm21, %ymm26, %ymm29 {%k2}
+
+// CHECK: vpacksswb %ymm21, %ymm26, %ymm29 {%k2} {z}
+// CHECK:  encoding: [0x62,0x21,0xad,0xa2,0x63,0xed]
+          vpacksswb %ymm21, %ymm26, %ymm29 {%k2} {z}
+
+// CHECK: vpacksswb (%rcx), %ymm26, %ymm29
+// CHECK:  encoding: [0x62,0x61,0xad,0x20,0x63,0x29]
+          vpacksswb (%rcx), %ymm26, %ymm29
+
+// CHECK: vpacksswb 291(%rax,%r14,8), %ymm26, %ymm29
+// CHECK:  encoding: [0x62,0x21,0xad,0x20,0x63,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpacksswb 291(%rax,%r14,8), %ymm26, %ymm29
+
+// CHECK: vpacksswb 4064(%rdx), %ymm26, %ymm29
+// CHECK:  encoding: [0x62,0x61,0xad,0x20,0x63,0x6a,0x7f]
+          vpacksswb 4064(%rdx), %ymm26, %ymm29
+
+// CHECK: vpacksswb 4096(%rdx), %ymm26, %ymm29
+// CHECK:  encoding: [0x62,0x61,0xad,0x20,0x63,0xaa,0x00,0x10,0x00,0x00]
+          vpacksswb 4096(%rdx), %ymm26, %ymm29
+
+// CHECK: vpacksswb -4096(%rdx), %ymm26, %ymm29
+// CHECK:  encoding: [0x62,0x61,0xad,0x20,0x63,0x6a,0x80]
+          vpacksswb -4096(%rdx), %ymm26, %ymm29
+
+// CHECK: vpacksswb -4128(%rdx), %ymm26, %ymm29
+// CHECK:  encoding: [0x62,0x61,0xad,0x20,0x63,0xaa,0xe0,0xef,0xff,0xff]
+          vpacksswb -4128(%rdx), %ymm26, %ymm29
+
+// CHECK: vpackuswb %xmm24, %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0x81,0xad,0x00,0x67,0xe0]
+          vpackuswb %xmm24, %xmm26, %xmm20
+
+// CHECK: vpackuswb %xmm24, %xmm26, %xmm20 {%k4}
+// CHECK:  encoding: [0x62,0x81,0xad,0x04,0x67,0xe0]
+          vpackuswb %xmm24, %xmm26, %xmm20 {%k4}
+
+// CHECK: vpackuswb %xmm24, %xmm26, %xmm20 {%k4} {z}
+// CHECK:  encoding: [0x62,0x81,0xad,0x84,0x67,0xe0]
+          vpackuswb %xmm24, %xmm26, %xmm20 {%k4} {z}
+
+// CHECK: vpackuswb (%rcx), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0xad,0x00,0x67,0x21]
+          vpackuswb (%rcx), %xmm26, %xmm20
+
+// CHECK: vpackuswb 291(%rax,%r14,8), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0xad,0x00,0x67,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpackuswb 291(%rax,%r14,8), %xmm26, %xmm20
+
+// CHECK: vpackuswb 2032(%rdx), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0xad,0x00,0x67,0x62,0x7f]
+          vpackuswb 2032(%rdx), %xmm26, %xmm20
+
+// CHECK: vpackuswb 2048(%rdx), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0xad,0x00,0x67,0xa2,0x00,0x08,0x00,0x00]
+          vpackuswb 2048(%rdx), %xmm26, %xmm20
+
+// CHECK: vpackuswb -2048(%rdx), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0xad,0x00,0x67,0x62,0x80]
+          vpackuswb -2048(%rdx), %xmm26, %xmm20
+
+// CHECK: vpackuswb -2064(%rdx), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0xad,0x00,0x67,0xa2,0xf0,0xf7,0xff,0xff]
+          vpackuswb -2064(%rdx), %xmm26, %xmm20
+
+// CHECK: vpackuswb %ymm20, %ymm28, %ymm19
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x20,0x67,0xdc]
+          vpackuswb %ymm20, %ymm28, %ymm19
+
+// CHECK: vpackuswb %ymm20, %ymm28, %ymm19 {%k2}
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x22,0x67,0xdc]
+          vpackuswb %ymm20, %ymm28, %ymm19 {%k2}
+
+// CHECK: vpackuswb %ymm20, %ymm28, %ymm19 {%k2} {z}
+// CHECK:  encoding: [0x62,0xa1,0x9d,0xa2,0x67,0xdc]
+          vpackuswb %ymm20, %ymm28, %ymm19 {%k2} {z}
+
+// CHECK: vpackuswb (%rcx), %ymm28, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x20,0x67,0x19]
+          vpackuswb (%rcx), %ymm28, %ymm19
+
+// CHECK: vpackuswb 291(%rax,%r14,8), %ymm28, %ymm19
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x20,0x67,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpackuswb 291(%rax,%r14,8), %ymm28, %ymm19
+
+// CHECK: vpackuswb 4064(%rdx), %ymm28, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x20,0x67,0x5a,0x7f]
+          vpackuswb 4064(%rdx), %ymm28, %ymm19
+
+// CHECK: vpackuswb 4096(%rdx), %ymm28, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x20,0x67,0x9a,0x00,0x10,0x00,0x00]
+          vpackuswb 4096(%rdx), %ymm28, %ymm19
+
+// CHECK: vpackuswb -4096(%rdx), %ymm28, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x20,0x67,0x5a,0x80]
+          vpackuswb -4096(%rdx), %ymm28, %ymm19
+
+// CHECK: vpackuswb -4128(%rdx), %ymm28, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x20,0x67,0x9a,0xe0,0xef,0xff,0xff]
+          vpackuswb -4128(%rdx), %ymm28, %ymm19
+
+// CHECK: vpacksswb %xmm25, %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0x81,0xed,0x00,0x63,0xd9]
+          vpacksswb %xmm25, %xmm18, %xmm19
+
+// CHECK: vpacksswb %xmm25, %xmm18, %xmm19 {%k4}
+// CHECK:  encoding: [0x62,0x81,0xed,0x04,0x63,0xd9]
+          vpacksswb %xmm25, %xmm18, %xmm19 {%k4}
+
+// CHECK: vpacksswb %xmm25, %xmm18, %xmm19 {%k4} {z}
+// CHECK:  encoding: [0x62,0x81,0xed,0x84,0x63,0xd9]
+          vpacksswb %xmm25, %xmm18, %xmm19 {%k4} {z}
+
+// CHECK: vpacksswb (%rcx), %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xed,0x00,0x63,0x19]
+          vpacksswb (%rcx), %xmm18, %xmm19
+
+// CHECK: vpacksswb 4660(%rax,%r14,8), %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xa1,0xed,0x00,0x63,0x9c,0xf0,0x34,0x12,0x00,0x00]
+          vpacksswb 4660(%rax,%r14,8), %xmm18, %xmm19
+
+// CHECK: vpacksswb 2032(%rdx), %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xed,0x00,0x63,0x5a,0x7f]
+          vpacksswb 2032(%rdx), %xmm18, %xmm19
+
+// CHECK: vpacksswb 2048(%rdx), %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xed,0x00,0x63,0x9a,0x00,0x08,0x00,0x00]
+          vpacksswb 2048(%rdx), %xmm18, %xmm19
+
+// CHECK: vpacksswb -2048(%rdx), %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xed,0x00,0x63,0x5a,0x80]
+          vpacksswb -2048(%rdx), %xmm18, %xmm19
+
+// CHECK: vpacksswb -2064(%rdx), %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xed,0x00,0x63,0x9a,0xf0,0xf7,0xff,0xff]
+          vpacksswb -2064(%rdx), %xmm18, %xmm19
+
+// CHECK: vpacksswb %ymm19, %ymm22, %ymm22
+// CHECK:  encoding: [0x62,0xa1,0xcd,0x20,0x63,0xf3]
+          vpacksswb %ymm19, %ymm22, %ymm22
+
+// CHECK: vpacksswb %ymm19, %ymm22, %ymm22 {%k7}
+// CHECK:  encoding: [0x62,0xa1,0xcd,0x27,0x63,0xf3]
+          vpacksswb %ymm19, %ymm22, %ymm22 {%k7}
+
+// CHECK: vpacksswb %ymm19, %ymm22, %ymm22 {%k7} {z}
+// CHECK:  encoding: [0x62,0xa1,0xcd,0xa7,0x63,0xf3]
+          vpacksswb %ymm19, %ymm22, %ymm22 {%k7} {z}
+
+// CHECK: vpacksswb (%rcx), %ymm22, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xcd,0x20,0x63,0x31]
+          vpacksswb (%rcx), %ymm22, %ymm22
+
+// CHECK: vpacksswb 4660(%rax,%r14,8), %ymm22, %ymm22
+// CHECK:  encoding: [0x62,0xa1,0xcd,0x20,0x63,0xb4,0xf0,0x34,0x12,0x00,0x00]
+          vpacksswb 4660(%rax,%r14,8), %ymm22, %ymm22
+
+// CHECK: vpacksswb 4064(%rdx), %ymm22, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xcd,0x20,0x63,0x72,0x7f]
+          vpacksswb 4064(%rdx), %ymm22, %ymm22
+
+// CHECK: vpacksswb 4096(%rdx), %ymm22, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xcd,0x20,0x63,0xb2,0x00,0x10,0x00,0x00]
+          vpacksswb 4096(%rdx), %ymm22, %ymm22
+
+// CHECK: vpacksswb -4096(%rdx), %ymm22, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xcd,0x20,0x63,0x72,0x80]
+          vpacksswb -4096(%rdx), %ymm22, %ymm22
+
+// CHECK: vpacksswb -4128(%rdx), %ymm22, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xcd,0x20,0x63,0xb2,0xe0,0xef,0xff,0xff]
+          vpacksswb -4128(%rdx), %ymm22, %ymm22
+
+// CHECK: vpackuswb %xmm23, %xmm28, %xmm23
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x00,0x67,0xff]
+          vpackuswb %xmm23, %xmm28, %xmm23
+
+// CHECK: vpackuswb %xmm23, %xmm28, %xmm23 {%k3}
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x03,0x67,0xff]
+          vpackuswb %xmm23, %xmm28, %xmm23 {%k3}
+
+// CHECK: vpackuswb %xmm23, %xmm28, %xmm23 {%k3} {z}
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x83,0x67,0xff]
+          vpackuswb %xmm23, %xmm28, %xmm23 {%k3} {z}
+
+// CHECK: vpackuswb (%rcx), %xmm28, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x00,0x67,0x39]
+          vpackuswb (%rcx), %xmm28, %xmm23
+
+// CHECK: vpackuswb 4660(%rax,%r14,8), %xmm28, %xmm23
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x00,0x67,0xbc,0xf0,0x34,0x12,0x00,0x00]
+          vpackuswb 4660(%rax,%r14,8), %xmm28, %xmm23
+
+// CHECK: vpackuswb 2032(%rdx), %xmm28, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x00,0x67,0x7a,0x7f]
+          vpackuswb 2032(%rdx), %xmm28, %xmm23
+
+// CHECK: vpackuswb 2048(%rdx), %xmm28, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x00,0x67,0xba,0x00,0x08,0x00,0x00]
+          vpackuswb 2048(%rdx), %xmm28, %xmm23
+
+// CHECK: vpackuswb -2048(%rdx), %xmm28, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x00,0x67,0x7a,0x80]
+          vpackuswb -2048(%rdx), %xmm28, %xmm23
+
+// CHECK: vpackuswb -2064(%rdx), %xmm28, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x00,0x67,0xba,0xf0,0xf7,0xff,0xff]
+          vpackuswb -2064(%rdx), %xmm28, %xmm23
+
+// CHECK: vpackuswb %ymm27, %ymm26, %ymm20
+// CHECK:  encoding: [0x62,0x81,0xad,0x20,0x67,0xe3]
+          vpackuswb %ymm27, %ymm26, %ymm20
+
+// CHECK: vpackuswb %ymm27, %ymm26, %ymm20 {%k6}
+// CHECK:  encoding: [0x62,0x81,0xad,0x26,0x67,0xe3]
+          vpackuswb %ymm27, %ymm26, %ymm20 {%k6}
+
+// CHECK: vpackuswb %ymm27, %ymm26, %ymm20 {%k6} {z}
+// CHECK:  encoding: [0x62,0x81,0xad,0xa6,0x67,0xe3]
+          vpackuswb %ymm27, %ymm26, %ymm20 {%k6} {z}
+
+// CHECK: vpackuswb (%rcx), %ymm26, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0xad,0x20,0x67,0x21]
+          vpackuswb (%rcx), %ymm26, %ymm20
+
+// CHECK: vpackuswb 4660(%rax,%r14,8), %ymm26, %ymm20
+// CHECK:  encoding: [0x62,0xa1,0xad,0x20,0x67,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vpackuswb 4660(%rax,%r14,8), %ymm26, %ymm20
+
+// CHECK: vpackuswb 4064(%rdx), %ymm26, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0xad,0x20,0x67,0x62,0x7f]
+          vpackuswb 4064(%rdx), %ymm26, %ymm20
+
+// CHECK: vpackuswb 4096(%rdx), %ymm26, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0xad,0x20,0x67,0xa2,0x00,0x10,0x00,0x00]
+          vpackuswb 4096(%rdx), %ymm26, %ymm20
+
+// CHECK: vpackuswb -4096(%rdx), %ymm26, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0xad,0x20,0x67,0x62,0x80]
+          vpackuswb -4096(%rdx), %ymm26, %ymm20
+
+// CHECK: vpackuswb -4128(%rdx), %ymm26, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0xad,0x20,0x67,0xa2,0xe0,0xef,0xff,0xff]
+          vpackuswb -4128(%rdx), %ymm26, %ymm20
+
+// CHECK: vpackssdw %xmm26, %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x01,0x2d,0x00,0x6b,0xf2]
+          vpackssdw %xmm26, %xmm26, %xmm30
+
+// CHECK: vpackssdw %xmm26, %xmm26, %xmm30 {%k2}
+// CHECK:  encoding: [0x62,0x01,0x2d,0x02,0x6b,0xf2]
+          vpackssdw %xmm26, %xmm26, %xmm30 {%k2}
+
+// CHECK: vpackssdw %xmm26, %xmm26, %xmm30 {%k2} {z}
+// CHECK:  encoding: [0x62,0x01,0x2d,0x82,0x6b,0xf2]
+          vpackssdw %xmm26, %xmm26, %xmm30 {%k2} {z}
+
+// CHECK: vpackssdw (%rcx), %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x2d,0x00,0x6b,0x31]
+          vpackssdw (%rcx), %xmm26, %xmm30
+
+// CHECK: vpackssdw 291(%rax,%r14,8), %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x21,0x2d,0x00,0x6b,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpackssdw 291(%rax,%r14,8), %xmm26, %xmm30
+
+// CHECK: vpackssdw (%rcx){1to4}, %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x2d,0x10,0x6b,0x31]
+          vpackssdw (%rcx){1to4}, %xmm26, %xmm30
+
+// CHECK: vpackssdw 2032(%rdx), %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x2d,0x00,0x6b,0x72,0x7f]
+          vpackssdw 2032(%rdx), %xmm26, %xmm30
+
+// CHECK: vpackssdw 2048(%rdx), %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x2d,0x00,0x6b,0xb2,0x00,0x08,0x00,0x00]
+          vpackssdw 2048(%rdx), %xmm26, %xmm30
+
+// CHECK: vpackssdw -2048(%rdx), %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x2d,0x00,0x6b,0x72,0x80]
+          vpackssdw -2048(%rdx), %xmm26, %xmm30
+
+// CHECK: vpackssdw -2064(%rdx), %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x2d,0x00,0x6b,0xb2,0xf0,0xf7,0xff,0xff]
+          vpackssdw -2064(%rdx), %xmm26, %xmm30
+
+// CHECK: vpackssdw 508(%rdx){1to4}, %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x2d,0x10,0x6b,0x72,0x7f]
+          vpackssdw 508(%rdx){1to4}, %xmm26, %xmm30
+
+// CHECK: vpackssdw 512(%rdx){1to4}, %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x2d,0x10,0x6b,0xb2,0x00,0x02,0x00,0x00]
+          vpackssdw 512(%rdx){1to4}, %xmm26, %xmm30
+
+// CHECK: vpackssdw -512(%rdx){1to4}, %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x2d,0x10,0x6b,0x72,0x80]
+          vpackssdw -512(%rdx){1to4}, %xmm26, %xmm30
+
+// CHECK: vpackssdw -516(%rdx){1to4}, %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x2d,0x10,0x6b,0xb2,0xfc,0xfd,0xff,0xff]
+          vpackssdw -516(%rdx){1to4}, %xmm26, %xmm30
+
+// CHECK: vpackssdw %ymm26, %ymm22, %ymm28
+// CHECK:  encoding: [0x62,0x01,0x4d,0x20,0x6b,0xe2]
+          vpackssdw %ymm26, %ymm22, %ymm28
+
+// CHECK: vpackssdw %ymm26, %ymm22, %ymm28 {%k7}
+// CHECK:  encoding: [0x62,0x01,0x4d,0x27,0x6b,0xe2]
+          vpackssdw %ymm26, %ymm22, %ymm28 {%k7}
+
+// CHECK: vpackssdw %ymm26, %ymm22, %ymm28 {%k7} {z}
+// CHECK:  encoding: [0x62,0x01,0x4d,0xa7,0x6b,0xe2]
+          vpackssdw %ymm26, %ymm22, %ymm28 {%k7} {z}
+
+// CHECK: vpackssdw (%rcx), %ymm22, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x4d,0x20,0x6b,0x21]
+          vpackssdw (%rcx), %ymm22, %ymm28
+
+// CHECK: vpackssdw 291(%rax,%r14,8), %ymm22, %ymm28
+// CHECK:  encoding: [0x62,0x21,0x4d,0x20,0x6b,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpackssdw 291(%rax,%r14,8), %ymm22, %ymm28
+
+// CHECK: vpackssdw (%rcx){1to8}, %ymm22, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x4d,0x30,0x6b,0x21]
+          vpackssdw (%rcx){1to8}, %ymm22, %ymm28
+
+// CHECK: vpackssdw 4064(%rdx), %ymm22, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x4d,0x20,0x6b,0x62,0x7f]
+          vpackssdw 4064(%rdx), %ymm22, %ymm28
+
+// CHECK: vpackssdw 4096(%rdx), %ymm22, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x4d,0x20,0x6b,0xa2,0x00,0x10,0x00,0x00]
+          vpackssdw 4096(%rdx), %ymm22, %ymm28
+
+// CHECK: vpackssdw -4096(%rdx), %ymm22, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x4d,0x20,0x6b,0x62,0x80]
+          vpackssdw -4096(%rdx), %ymm22, %ymm28
+
+// CHECK: vpackssdw -4128(%rdx), %ymm22, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x4d,0x20,0x6b,0xa2,0xe0,0xef,0xff,0xff]
+          vpackssdw -4128(%rdx), %ymm22, %ymm28
+
+// CHECK: vpackssdw 508(%rdx){1to8}, %ymm22, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x4d,0x30,0x6b,0x62,0x7f]
+          vpackssdw 508(%rdx){1to8}, %ymm22, %ymm28
+
+// CHECK: vpackssdw 512(%rdx){1to8}, %ymm22, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x4d,0x30,0x6b,0xa2,0x00,0x02,0x00,0x00]
+          vpackssdw 512(%rdx){1to8}, %ymm22, %ymm28
+
+// CHECK: vpackssdw -512(%rdx){1to8}, %ymm22, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x4d,0x30,0x6b,0x62,0x80]
+          vpackssdw -512(%rdx){1to8}, %ymm22, %ymm28
+
+// CHECK: vpackssdw -516(%rdx){1to8}, %ymm22, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x4d,0x30,0x6b,0xa2,0xfc,0xfd,0xff,0xff]
+          vpackssdw -516(%rdx){1to8}, %ymm22, %ymm28
+
+// CHECK: vpacksswb %xmm21, %xmm28, %xmm25
+// CHECK:  encoding: [0x62,0x21,0x9d,0x00,0x63,0xcd]
+          vpacksswb %xmm21, %xmm28, %xmm25
+
+// CHECK: vpacksswb %xmm21, %xmm28, %xmm25 {%k5}
+// CHECK:  encoding: [0x62,0x21,0x9d,0x05,0x63,0xcd]
+          vpacksswb %xmm21, %xmm28, %xmm25 {%k5}
+
+// CHECK: vpacksswb %xmm21, %xmm28, %xmm25 {%k5} {z}
+// CHECK:  encoding: [0x62,0x21,0x9d,0x85,0x63,0xcd]
+          vpacksswb %xmm21, %xmm28, %xmm25 {%k5} {z}
+
+// CHECK: vpacksswb (%rcx), %xmm28, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x9d,0x00,0x63,0x09]
+          vpacksswb (%rcx), %xmm28, %xmm25
+
+// CHECK: vpacksswb 291(%rax,%r14,8), %xmm28, %xmm25
+// CHECK:  encoding: [0x62,0x21,0x9d,0x00,0x63,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpacksswb 291(%rax,%r14,8), %xmm28, %xmm25
+
+// CHECK: vpacksswb 2032(%rdx), %xmm28, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x9d,0x00,0x63,0x4a,0x7f]
+          vpacksswb 2032(%rdx), %xmm28, %xmm25
+
+// CHECK: vpacksswb 2048(%rdx), %xmm28, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x9d,0x00,0x63,0x8a,0x00,0x08,0x00,0x00]
+          vpacksswb 2048(%rdx), %xmm28, %xmm25
+
+// CHECK: vpacksswb -2048(%rdx), %xmm28, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x9d,0x00,0x63,0x4a,0x80]
+          vpacksswb -2048(%rdx), %xmm28, %xmm25
+
+// CHECK: vpacksswb -2064(%rdx), %xmm28, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x9d,0x00,0x63,0x8a,0xf0,0xf7,0xff,0xff]
+          vpacksswb -2064(%rdx), %xmm28, %xmm25
+
+// CHECK: vpacksswb %ymm22, %ymm28, %ymm21
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x20,0x63,0xee]
+          vpacksswb %ymm22, %ymm28, %ymm21
+
+// CHECK: vpacksswb %ymm22, %ymm28, %ymm21 {%k5}
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x25,0x63,0xee]
+          vpacksswb %ymm22, %ymm28, %ymm21 {%k5}
+
+// CHECK: vpacksswb %ymm22, %ymm28, %ymm21 {%k5} {z}
+// CHECK:  encoding: [0x62,0xa1,0x9d,0xa5,0x63,0xee]
+          vpacksswb %ymm22, %ymm28, %ymm21 {%k5} {z}
+
+// CHECK: vpacksswb (%rcx), %ymm28, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x20,0x63,0x29]
+          vpacksswb (%rcx), %ymm28, %ymm21
+
+// CHECK: vpacksswb 291(%rax,%r14,8), %ymm28, %ymm21
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x20,0x63,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpacksswb 291(%rax,%r14,8), %ymm28, %ymm21
+
+// CHECK: vpacksswb 4064(%rdx), %ymm28, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x20,0x63,0x6a,0x7f]
+          vpacksswb 4064(%rdx), %ymm28, %ymm21
+
+// CHECK: vpacksswb 4096(%rdx), %ymm28, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x20,0x63,0xaa,0x00,0x10,0x00,0x00]
+          vpacksswb 4096(%rdx), %ymm28, %ymm21
+
+// CHECK: vpacksswb -4096(%rdx), %ymm28, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x20,0x63,0x6a,0x80]
+          vpacksswb -4096(%rdx), %ymm28, %ymm21
+
+// CHECK: vpacksswb -4128(%rdx), %ymm28, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x20,0x63,0xaa,0xe0,0xef,0xff,0xff]
+          vpacksswb -4128(%rdx), %ymm28, %ymm21
+
+// CHECK: vpackusdw %xmm20, %xmm24, %xmm24
+// CHECK:  encoding: [0x62,0x22,0x3d,0x00,0x2b,0xc4]
+          vpackusdw %xmm20, %xmm24, %xmm24
+
+// CHECK: vpackusdw %xmm20, %xmm24, %xmm24 {%k5}
+// CHECK:  encoding: [0x62,0x22,0x3d,0x05,0x2b,0xc4]
+          vpackusdw %xmm20, %xmm24, %xmm24 {%k5}
+
+// CHECK: vpackusdw %xmm20, %xmm24, %xmm24 {%k5} {z}
+// CHECK:  encoding: [0x62,0x22,0x3d,0x85,0x2b,0xc4]
+          vpackusdw %xmm20, %xmm24, %xmm24 {%k5} {z}
+
+// CHECK: vpackusdw (%rcx), %xmm24, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x3d,0x00,0x2b,0x01]
+          vpackusdw (%rcx), %xmm24, %xmm24
+
+// CHECK: vpackusdw 291(%rax,%r14,8), %xmm24, %xmm24
+// CHECK:  encoding: [0x62,0x22,0x3d,0x00,0x2b,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vpackusdw 291(%rax,%r14,8), %xmm24, %xmm24
+
+// CHECK: vpackusdw (%rcx){1to4}, %xmm24, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x3d,0x10,0x2b,0x01]
+          vpackusdw (%rcx){1to4}, %xmm24, %xmm24
+
+// CHECK: vpackusdw 2032(%rdx), %xmm24, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x3d,0x00,0x2b,0x42,0x7f]
+          vpackusdw 2032(%rdx), %xmm24, %xmm24
+
+// CHECK: vpackusdw 2048(%rdx), %xmm24, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x3d,0x00,0x2b,0x82,0x00,0x08,0x00,0x00]
+          vpackusdw 2048(%rdx), %xmm24, %xmm24
+
+// CHECK: vpackusdw -2048(%rdx), %xmm24, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x3d,0x00,0x2b,0x42,0x80]
+          vpackusdw -2048(%rdx), %xmm24, %xmm24
+
+// CHECK: vpackusdw -2064(%rdx), %xmm24, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x3d,0x00,0x2b,0x82,0xf0,0xf7,0xff,0xff]
+          vpackusdw -2064(%rdx), %xmm24, %xmm24
+
+// CHECK: vpackusdw 508(%rdx){1to4}, %xmm24, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x3d,0x10,0x2b,0x42,0x7f]
+          vpackusdw 508(%rdx){1to4}, %xmm24, %xmm24
+
+// CHECK: vpackusdw 512(%rdx){1to4}, %xmm24, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x3d,0x10,0x2b,0x82,0x00,0x02,0x00,0x00]
+          vpackusdw 512(%rdx){1to4}, %xmm24, %xmm24
+
+// CHECK: vpackusdw -512(%rdx){1to4}, %xmm24, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x3d,0x10,0x2b,0x42,0x80]
+          vpackusdw -512(%rdx){1to4}, %xmm24, %xmm24
+
+// CHECK: vpackusdw -516(%rdx){1to4}, %xmm24, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x3d,0x10,0x2b,0x82,0xfc,0xfd,0xff,0xff]
+          vpackusdw -516(%rdx){1to4}, %xmm24, %xmm24
+
+// CHECK: vpackusdw %ymm21, %ymm26, %ymm19
+// CHECK:  encoding: [0x62,0xa2,0x2d,0x20,0x2b,0xdd]
+          vpackusdw %ymm21, %ymm26, %ymm19
+
+// CHECK: vpackusdw %ymm21, %ymm26, %ymm19 {%k1}
+// CHECK:  encoding: [0x62,0xa2,0x2d,0x21,0x2b,0xdd]
+          vpackusdw %ymm21, %ymm26, %ymm19 {%k1}
+
+// CHECK: vpackusdw %ymm21, %ymm26, %ymm19 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa2,0x2d,0xa1,0x2b,0xdd]
+          vpackusdw %ymm21, %ymm26, %ymm19 {%k1} {z}
+
+// CHECK: vpackusdw (%rcx), %ymm26, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x20,0x2b,0x19]
+          vpackusdw (%rcx), %ymm26, %ymm19
+
+// CHECK: vpackusdw 291(%rax,%r14,8), %ymm26, %ymm19
+// CHECK:  encoding: [0x62,0xa2,0x2d,0x20,0x2b,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpackusdw 291(%rax,%r14,8), %ymm26, %ymm19
+
+// CHECK: vpackusdw (%rcx){1to8}, %ymm26, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x30,0x2b,0x19]
+          vpackusdw (%rcx){1to8}, %ymm26, %ymm19
+
+// CHECK: vpackusdw 4064(%rdx), %ymm26, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x20,0x2b,0x5a,0x7f]
+          vpackusdw 4064(%rdx), %ymm26, %ymm19
+
+// CHECK: vpackusdw 4096(%rdx), %ymm26, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x20,0x2b,0x9a,0x00,0x10,0x00,0x00]
+          vpackusdw 4096(%rdx), %ymm26, %ymm19
+
+// CHECK: vpackusdw -4096(%rdx), %ymm26, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x20,0x2b,0x5a,0x80]
+          vpackusdw -4096(%rdx), %ymm26, %ymm19
+
+// CHECK: vpackusdw -4128(%rdx), %ymm26, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x20,0x2b,0x9a,0xe0,0xef,0xff,0xff]
+          vpackusdw -4128(%rdx), %ymm26, %ymm19
+
+// CHECK: vpackusdw 508(%rdx){1to8}, %ymm26, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x30,0x2b,0x5a,0x7f]
+          vpackusdw 508(%rdx){1to8}, %ymm26, %ymm19
+
+// CHECK: vpackusdw 512(%rdx){1to8}, %ymm26, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x30,0x2b,0x9a,0x00,0x02,0x00,0x00]
+          vpackusdw 512(%rdx){1to8}, %ymm26, %ymm19
+
+// CHECK: vpackusdw -512(%rdx){1to8}, %ymm26, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x30,0x2b,0x5a,0x80]
+          vpackusdw -512(%rdx){1to8}, %ymm26, %ymm19
+
+// CHECK: vpackusdw -516(%rdx){1to8}, %ymm26, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x30,0x2b,0x9a,0xfc,0xfd,0xff,0xff]
+          vpackusdw -516(%rdx){1to8}, %ymm26, %ymm19
+
+// CHECK: vpackuswb %xmm17, %xmm27, %xmm21
+// CHECK:  encoding: [0x62,0xa1,0xa5,0x00,0x67,0xe9]
+          vpackuswb %xmm17, %xmm27, %xmm21
+
+// CHECK: vpackuswb %xmm17, %xmm27, %xmm21 {%k4}
+// CHECK:  encoding: [0x62,0xa1,0xa5,0x04,0x67,0xe9]
+          vpackuswb %xmm17, %xmm27, %xmm21 {%k4}
+
+// CHECK: vpackuswb %xmm17, %xmm27, %xmm21 {%k4} {z}
+// CHECK:  encoding: [0x62,0xa1,0xa5,0x84,0x67,0xe9]
+          vpackuswb %xmm17, %xmm27, %xmm21 {%k4} {z}
+
+// CHECK: vpackuswb (%rcx), %xmm27, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0xa5,0x00,0x67,0x29]
+          vpackuswb (%rcx), %xmm27, %xmm21
+
+// CHECK: vpackuswb 291(%rax,%r14,8), %xmm27, %xmm21
+// CHECK:  encoding: [0x62,0xa1,0xa5,0x00,0x67,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpackuswb 291(%rax,%r14,8), %xmm27, %xmm21
+
+// CHECK: vpackuswb 2032(%rdx), %xmm27, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0xa5,0x00,0x67,0x6a,0x7f]
+          vpackuswb 2032(%rdx), %xmm27, %xmm21
+
+// CHECK: vpackuswb 2048(%rdx), %xmm27, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0xa5,0x00,0x67,0xaa,0x00,0x08,0x00,0x00]
+          vpackuswb 2048(%rdx), %xmm27, %xmm21
+
+// CHECK: vpackuswb -2048(%rdx), %xmm27, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0xa5,0x00,0x67,0x6a,0x80]
+          vpackuswb -2048(%rdx), %xmm27, %xmm21
+
+// CHECK: vpackuswb -2064(%rdx), %xmm27, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0xa5,0x00,0x67,0xaa,0xf0,0xf7,0xff,0xff]
+          vpackuswb -2064(%rdx), %xmm27, %xmm21
+
+// CHECK: vpackuswb %ymm20, %ymm28, %ymm19
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x20,0x67,0xdc]
+          vpackuswb %ymm20, %ymm28, %ymm19
+
+// CHECK: vpackuswb %ymm20, %ymm28, %ymm19 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x21,0x67,0xdc]
+          vpackuswb %ymm20, %ymm28, %ymm19 {%k1}
+
+// CHECK: vpackuswb %ymm20, %ymm28, %ymm19 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0x9d,0xa1,0x67,0xdc]
+          vpackuswb %ymm20, %ymm28, %ymm19 {%k1} {z}
+
+// CHECK: vpackuswb (%rcx), %ymm28, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x20,0x67,0x19]
+          vpackuswb (%rcx), %ymm28, %ymm19
+
+// CHECK: vpackuswb 291(%rax,%r14,8), %ymm28, %ymm19
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x20,0x67,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpackuswb 291(%rax,%r14,8), %ymm28, %ymm19
+
+// CHECK: vpackuswb 4064(%rdx), %ymm28, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x20,0x67,0x5a,0x7f]
+          vpackuswb 4064(%rdx), %ymm28, %ymm19
+
+// CHECK: vpackuswb 4096(%rdx), %ymm28, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x20,0x67,0x9a,0x00,0x10,0x00,0x00]
+          vpackuswb 4096(%rdx), %ymm28, %ymm19
+
+// CHECK: vpackuswb -4096(%rdx), %ymm28, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x20,0x67,0x5a,0x80]
+          vpackuswb -4096(%rdx), %ymm28, %ymm19
+
+// CHECK: vpackuswb -4128(%rdx), %ymm28, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x20,0x67,0x9a,0xe0,0xef,0xff,0xff]
+          vpackuswb -4128(%rdx), %ymm28, %ymm19
+
+// CHECK: vpackssdw %xmm19, %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x21,0x75,0x00,0x6b,0xc3]
+          vpackssdw %xmm19, %xmm17, %xmm24
+
+// CHECK: vpackssdw %xmm19, %xmm17, %xmm24 {%k7}
+// CHECK:  encoding: [0x62,0x21,0x75,0x07,0x6b,0xc3]
+          vpackssdw %xmm19, %xmm17, %xmm24 {%k7}
+
+// CHECK: vpackssdw %xmm19, %xmm17, %xmm24 {%k7} {z}
+// CHECK:  encoding: [0x62,0x21,0x75,0x87,0x6b,0xc3]
+          vpackssdw %xmm19, %xmm17, %xmm24 {%k7} {z}
+
+// CHECK: vpackssdw (%rcx), %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x61,0x75,0x00,0x6b,0x01]
+          vpackssdw (%rcx), %xmm17, %xmm24
+
+// CHECK: vpackssdw 4660(%rax,%r14,8), %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x21,0x75,0x00,0x6b,0x84,0xf0,0x34,0x12,0x00,0x00]
+          vpackssdw 4660(%rax,%r14,8), %xmm17, %xmm24
+
+// CHECK: vpackssdw (%rcx){1to4}, %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x61,0x75,0x10,0x6b,0x01]
+          vpackssdw (%rcx){1to4}, %xmm17, %xmm24
+
+// CHECK: vpackssdw 2032(%rdx), %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x61,0x75,0x00,0x6b,0x42,0x7f]
+          vpackssdw 2032(%rdx), %xmm17, %xmm24
+
+// CHECK: vpackssdw 2048(%rdx), %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x61,0x75,0x00,0x6b,0x82,0x00,0x08,0x00,0x00]
+          vpackssdw 2048(%rdx), %xmm17, %xmm24
+
+// CHECK: vpackssdw -2048(%rdx), %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x61,0x75,0x00,0x6b,0x42,0x80]
+          vpackssdw -2048(%rdx), %xmm17, %xmm24
+
+// CHECK: vpackssdw -2064(%rdx), %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x61,0x75,0x00,0x6b,0x82,0xf0,0xf7,0xff,0xff]
+          vpackssdw -2064(%rdx), %xmm17, %xmm24
+
+// CHECK: vpackssdw 508(%rdx){1to4}, %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x61,0x75,0x10,0x6b,0x42,0x7f]
+          vpackssdw 508(%rdx){1to4}, %xmm17, %xmm24
+
+// CHECK: vpackssdw 512(%rdx){1to4}, %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x61,0x75,0x10,0x6b,0x82,0x00,0x02,0x00,0x00]
+          vpackssdw 512(%rdx){1to4}, %xmm17, %xmm24
+
+// CHECK: vpackssdw -512(%rdx){1to4}, %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x61,0x75,0x10,0x6b,0x42,0x80]
+          vpackssdw -512(%rdx){1to4}, %xmm17, %xmm24
+
+// CHECK: vpackssdw -516(%rdx){1to4}, %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x61,0x75,0x10,0x6b,0x82,0xfc,0xfd,0xff,0xff]
+          vpackssdw -516(%rdx){1to4}, %xmm17, %xmm24
+
+// CHECK: vpackssdw %ymm19, %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x21,0x65,0x20,0x6b,0xcb]
+          vpackssdw %ymm19, %ymm19, %ymm25
+
+// CHECK: vpackssdw %ymm19, %ymm19, %ymm25 {%k2}
+// CHECK:  encoding: [0x62,0x21,0x65,0x22,0x6b,0xcb]
+          vpackssdw %ymm19, %ymm19, %ymm25 {%k2}
+
+// CHECK: vpackssdw %ymm19, %ymm19, %ymm25 {%k2} {z}
+// CHECK:  encoding: [0x62,0x21,0x65,0xa2,0x6b,0xcb]
+          vpackssdw %ymm19, %ymm19, %ymm25 {%k2} {z}
+
+// CHECK: vpackssdw (%rcx), %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x65,0x20,0x6b,0x09]
+          vpackssdw (%rcx), %ymm19, %ymm25
+
+// CHECK: vpackssdw 4660(%rax,%r14,8), %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x21,0x65,0x20,0x6b,0x8c,0xf0,0x34,0x12,0x00,0x00]
+          vpackssdw 4660(%rax,%r14,8), %ymm19, %ymm25
+
+// CHECK: vpackssdw (%rcx){1to8}, %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x65,0x30,0x6b,0x09]
+          vpackssdw (%rcx){1to8}, %ymm19, %ymm25
+
+// CHECK: vpackssdw 4064(%rdx), %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x65,0x20,0x6b,0x4a,0x7f]
+          vpackssdw 4064(%rdx), %ymm19, %ymm25
+
+// CHECK: vpackssdw 4096(%rdx), %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x65,0x20,0x6b,0x8a,0x00,0x10,0x00,0x00]
+          vpackssdw 4096(%rdx), %ymm19, %ymm25
+
+// CHECK: vpackssdw -4096(%rdx), %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x65,0x20,0x6b,0x4a,0x80]
+          vpackssdw -4096(%rdx), %ymm19, %ymm25
+
+// CHECK: vpackssdw -4128(%rdx), %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x65,0x20,0x6b,0x8a,0xe0,0xef,0xff,0xff]
+          vpackssdw -4128(%rdx), %ymm19, %ymm25
+
+// CHECK: vpackssdw 508(%rdx){1to8}, %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x65,0x30,0x6b,0x4a,0x7f]
+          vpackssdw 508(%rdx){1to8}, %ymm19, %ymm25
+
+// CHECK: vpackssdw 512(%rdx){1to8}, %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x65,0x30,0x6b,0x8a,0x00,0x02,0x00,0x00]
+          vpackssdw 512(%rdx){1to8}, %ymm19, %ymm25
+
+// CHECK: vpackssdw -512(%rdx){1to8}, %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x65,0x30,0x6b,0x4a,0x80]
+          vpackssdw -512(%rdx){1to8}, %ymm19, %ymm25
+
+// CHECK: vpackssdw -516(%rdx){1to8}, %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x65,0x30,0x6b,0x8a,0xfc,0xfd,0xff,0xff]
+          vpackssdw -516(%rdx){1to8}, %ymm19, %ymm25
+
+// CHECK: vpacksswb %xmm22, %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x21,0xb5,0x00,0x63,0xee]
+          vpacksswb %xmm22, %xmm25, %xmm29
+
+// CHECK: vpacksswb %xmm22, %xmm25, %xmm29 {%k5}
+// CHECK:  encoding: [0x62,0x21,0xb5,0x05,0x63,0xee]
+          vpacksswb %xmm22, %xmm25, %xmm29 {%k5}
+
+// CHECK: vpacksswb %xmm22, %xmm25, %xmm29 {%k5} {z}
+// CHECK:  encoding: [0x62,0x21,0xb5,0x85,0x63,0xee]
+          vpacksswb %xmm22, %xmm25, %xmm29 {%k5} {z}
+
+// CHECK: vpacksswb (%rcx), %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x61,0xb5,0x00,0x63,0x29]
+          vpacksswb (%rcx), %xmm25, %xmm29
+
+// CHECK: vpacksswb 4660(%rax,%r14,8), %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x21,0xb5,0x00,0x63,0xac,0xf0,0x34,0x12,0x00,0x00]
+          vpacksswb 4660(%rax,%r14,8), %xmm25, %xmm29
+
+// CHECK: vpacksswb 2032(%rdx), %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x61,0xb5,0x00,0x63,0x6a,0x7f]
+          vpacksswb 2032(%rdx), %xmm25, %xmm29
+
+// CHECK: vpacksswb 2048(%rdx), %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x61,0xb5,0x00,0x63,0xaa,0x00,0x08,0x00,0x00]
+          vpacksswb 2048(%rdx), %xmm25, %xmm29
+
+// CHECK: vpacksswb -2048(%rdx), %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x61,0xb5,0x00,0x63,0x6a,0x80]
+          vpacksswb -2048(%rdx), %xmm25, %xmm29
+
+// CHECK: vpacksswb -2064(%rdx), %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x61,0xb5,0x00,0x63,0xaa,0xf0,0xf7,0xff,0xff]
+          vpacksswb -2064(%rdx), %xmm25, %xmm29
+
+// CHECK: vpacksswb %ymm27, %ymm20, %ymm26
+// CHECK:  encoding: [0x62,0x01,0xdd,0x20,0x63,0xd3]
+          vpacksswb %ymm27, %ymm20, %ymm26
+
+// CHECK: vpacksswb %ymm27, %ymm20, %ymm26 {%k6}
+// CHECK:  encoding: [0x62,0x01,0xdd,0x26,0x63,0xd3]
+          vpacksswb %ymm27, %ymm20, %ymm26 {%k6}
+
+// CHECK: vpacksswb %ymm27, %ymm20, %ymm26 {%k6} {z}
+// CHECK:  encoding: [0x62,0x01,0xdd,0xa6,0x63,0xd3]
+          vpacksswb %ymm27, %ymm20, %ymm26 {%k6} {z}
+
+// CHECK: vpacksswb (%rcx), %ymm20, %ymm26
+// CHECK:  encoding: [0x62,0x61,0xdd,0x20,0x63,0x11]
+          vpacksswb (%rcx), %ymm20, %ymm26
+
+// CHECK: vpacksswb 4660(%rax,%r14,8), %ymm20, %ymm26
+// CHECK:  encoding: [0x62,0x21,0xdd,0x20,0x63,0x94,0xf0,0x34,0x12,0x00,0x00]
+          vpacksswb 4660(%rax,%r14,8), %ymm20, %ymm26
+
+// CHECK: vpacksswb 4064(%rdx), %ymm20, %ymm26
+// CHECK:  encoding: [0x62,0x61,0xdd,0x20,0x63,0x52,0x7f]
+          vpacksswb 4064(%rdx), %ymm20, %ymm26
+
+// CHECK: vpacksswb 4096(%rdx), %ymm20, %ymm26
+// CHECK:  encoding: [0x62,0x61,0xdd,0x20,0x63,0x92,0x00,0x10,0x00,0x00]
+          vpacksswb 4096(%rdx), %ymm20, %ymm26
+
+// CHECK: vpacksswb -4096(%rdx), %ymm20, %ymm26
+// CHECK:  encoding: [0x62,0x61,0xdd,0x20,0x63,0x52,0x80]
+          vpacksswb -4096(%rdx), %ymm20, %ymm26
+
+// CHECK: vpacksswb -4128(%rdx), %ymm20, %ymm26
+// CHECK:  encoding: [0x62,0x61,0xdd,0x20,0x63,0x92,0xe0,0xef,0xff,0xff]
+          vpacksswb -4128(%rdx), %ymm20, %ymm26
+
+// CHECK: vpackusdw %xmm18, %xmm27, %xmm28
+// CHECK:  encoding: [0x62,0x22,0x25,0x00,0x2b,0xe2]
+          vpackusdw %xmm18, %xmm27, %xmm28
+
+// CHECK: vpackusdw %xmm18, %xmm27, %xmm28 {%k4}
+// CHECK:  encoding: [0x62,0x22,0x25,0x04,0x2b,0xe2]
+          vpackusdw %xmm18, %xmm27, %xmm28 {%k4}
+
+// CHECK: vpackusdw %xmm18, %xmm27, %xmm28 {%k4} {z}
+// CHECK:  encoding: [0x62,0x22,0x25,0x84,0x2b,0xe2]
+          vpackusdw %xmm18, %xmm27, %xmm28 {%k4} {z}
+
+// CHECK: vpackusdw (%rcx), %xmm27, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x25,0x00,0x2b,0x21]
+          vpackusdw (%rcx), %xmm27, %xmm28
+
+// CHECK: vpackusdw 4660(%rax,%r14,8), %xmm27, %xmm28
+// CHECK:  encoding: [0x62,0x22,0x25,0x00,0x2b,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vpackusdw 4660(%rax,%r14,8), %xmm27, %xmm28
+
+// CHECK: vpackusdw (%rcx){1to4}, %xmm27, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x25,0x10,0x2b,0x21]
+          vpackusdw (%rcx){1to4}, %xmm27, %xmm28
+
+// CHECK: vpackusdw 2032(%rdx), %xmm27, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x25,0x00,0x2b,0x62,0x7f]
+          vpackusdw 2032(%rdx), %xmm27, %xmm28
+
+// CHECK: vpackusdw 2048(%rdx), %xmm27, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x25,0x00,0x2b,0xa2,0x00,0x08,0x00,0x00]
+          vpackusdw 2048(%rdx), %xmm27, %xmm28
+
+// CHECK: vpackusdw -2048(%rdx), %xmm27, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x25,0x00,0x2b,0x62,0x80]
+          vpackusdw -2048(%rdx), %xmm27, %xmm28
+
+// CHECK: vpackusdw -2064(%rdx), %xmm27, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x25,0x00,0x2b,0xa2,0xf0,0xf7,0xff,0xff]
+          vpackusdw -2064(%rdx), %xmm27, %xmm28
+
+// CHECK: vpackusdw 508(%rdx){1to4}, %xmm27, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x25,0x10,0x2b,0x62,0x7f]
+          vpackusdw 508(%rdx){1to4}, %xmm27, %xmm28
+
+// CHECK: vpackusdw 512(%rdx){1to4}, %xmm27, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x25,0x10,0x2b,0xa2,0x00,0x02,0x00,0x00]
+          vpackusdw 512(%rdx){1to4}, %xmm27, %xmm28
+
+// CHECK: vpackusdw -512(%rdx){1to4}, %xmm27, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x25,0x10,0x2b,0x62,0x80]
+          vpackusdw -512(%rdx){1to4}, %xmm27, %xmm28
+
+// CHECK: vpackusdw -516(%rdx){1to4}, %xmm27, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x25,0x10,0x2b,0xa2,0xfc,0xfd,0xff,0xff]
+          vpackusdw -516(%rdx){1to4}, %xmm27, %xmm28
+
+// CHECK: vpackusdw %ymm17, %ymm26, %ymm23
+// CHECK:  encoding: [0x62,0xa2,0x2d,0x20,0x2b,0xf9]
+          vpackusdw %ymm17, %ymm26, %ymm23
+
+// CHECK: vpackusdw %ymm17, %ymm26, %ymm23 {%k4}
+// CHECK:  encoding: [0x62,0xa2,0x2d,0x24,0x2b,0xf9]
+          vpackusdw %ymm17, %ymm26, %ymm23 {%k4}
+
+// CHECK: vpackusdw %ymm17, %ymm26, %ymm23 {%k4} {z}
+// CHECK:  encoding: [0x62,0xa2,0x2d,0xa4,0x2b,0xf9]
+          vpackusdw %ymm17, %ymm26, %ymm23 {%k4} {z}
+
+// CHECK: vpackusdw (%rcx), %ymm26, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x20,0x2b,0x39]
+          vpackusdw (%rcx), %ymm26, %ymm23
+
+// CHECK: vpackusdw 4660(%rax,%r14,8), %ymm26, %ymm23
+// CHECK:  encoding: [0x62,0xa2,0x2d,0x20,0x2b,0xbc,0xf0,0x34,0x12,0x00,0x00]
+          vpackusdw 4660(%rax,%r14,8), %ymm26, %ymm23
+
+// CHECK: vpackusdw (%rcx){1to8}, %ymm26, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x30,0x2b,0x39]
+          vpackusdw (%rcx){1to8}, %ymm26, %ymm23
+
+// CHECK: vpackusdw 4064(%rdx), %ymm26, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x20,0x2b,0x7a,0x7f]
+          vpackusdw 4064(%rdx), %ymm26, %ymm23
+
+// CHECK: vpackusdw 4096(%rdx), %ymm26, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x20,0x2b,0xba,0x00,0x10,0x00,0x00]
+          vpackusdw 4096(%rdx), %ymm26, %ymm23
+
+// CHECK: vpackusdw -4096(%rdx), %ymm26, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x20,0x2b,0x7a,0x80]
+          vpackusdw -4096(%rdx), %ymm26, %ymm23
+
+// CHECK: vpackusdw -4128(%rdx), %ymm26, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x20,0x2b,0xba,0xe0,0xef,0xff,0xff]
+          vpackusdw -4128(%rdx), %ymm26, %ymm23
+
+// CHECK: vpackusdw 508(%rdx){1to8}, %ymm26, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x30,0x2b,0x7a,0x7f]
+          vpackusdw 508(%rdx){1to8}, %ymm26, %ymm23
+
+// CHECK: vpackusdw 512(%rdx){1to8}, %ymm26, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x30,0x2b,0xba,0x00,0x02,0x00,0x00]
+          vpackusdw 512(%rdx){1to8}, %ymm26, %ymm23
+
+// CHECK: vpackusdw -512(%rdx){1to8}, %ymm26, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x30,0x2b,0x7a,0x80]
+          vpackusdw -512(%rdx){1to8}, %ymm26, %ymm23
+
+// CHECK: vpackusdw -516(%rdx){1to8}, %ymm26, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0x2d,0x30,0x2b,0xba,0xfc,0xfd,0xff,0xff]
+          vpackusdw -516(%rdx){1to8}, %ymm26, %ymm23
+
+// CHECK: vpackuswb %xmm23, %xmm20, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0xdd,0x00,0x67,0xe7]
+          vpackuswb %xmm23, %xmm20, %xmm20
+
+// CHECK: vpackuswb %xmm23, %xmm20, %xmm20 {%k2}
+// CHECK:  encoding: [0x62,0xa1,0xdd,0x02,0x67,0xe7]
+          vpackuswb %xmm23, %xmm20, %xmm20 {%k2}
+
+// CHECK: vpackuswb %xmm23, %xmm20, %xmm20 {%k2} {z}
+// CHECK:  encoding: [0x62,0xa1,0xdd,0x82,0x67,0xe7]
+          vpackuswb %xmm23, %xmm20, %xmm20 {%k2} {z}
+
+// CHECK: vpackuswb (%rcx), %xmm20, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0xdd,0x00,0x67,0x21]
+          vpackuswb (%rcx), %xmm20, %xmm20
+
+// CHECK: vpackuswb 4660(%rax,%r14,8), %xmm20, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0xdd,0x00,0x67,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vpackuswb 4660(%rax,%r14,8), %xmm20, %xmm20
+
+// CHECK: vpackuswb 2032(%rdx), %xmm20, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0xdd,0x00,0x67,0x62,0x7f]
+          vpackuswb 2032(%rdx), %xmm20, %xmm20
+
+// CHECK: vpackuswb 2048(%rdx), %xmm20, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0xdd,0x00,0x67,0xa2,0x00,0x08,0x00,0x00]
+          vpackuswb 2048(%rdx), %xmm20, %xmm20
+
+// CHECK: vpackuswb -2048(%rdx), %xmm20, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0xdd,0x00,0x67,0x62,0x80]
+          vpackuswb -2048(%rdx), %xmm20, %xmm20
+
+// CHECK: vpackuswb -2064(%rdx), %xmm20, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0xdd,0x00,0x67,0xa2,0xf0,0xf7,0xff,0xff]
+          vpackuswb -2064(%rdx), %xmm20, %xmm20
+
+// CHECK: vpackuswb %ymm27, %ymm19, %ymm20
+// CHECK:  encoding: [0x62,0x81,0xe5,0x20,0x67,0xe3]
+          vpackuswb %ymm27, %ymm19, %ymm20
+
+// CHECK: vpackuswb %ymm27, %ymm19, %ymm20 {%k5}
+// CHECK:  encoding: [0x62,0x81,0xe5,0x25,0x67,0xe3]
+          vpackuswb %ymm27, %ymm19, %ymm20 {%k5}
+
+// CHECK: vpackuswb %ymm27, %ymm19, %ymm20 {%k5} {z}
+// CHECK:  encoding: [0x62,0x81,0xe5,0xa5,0x67,0xe3]
+          vpackuswb %ymm27, %ymm19, %ymm20 {%k5} {z}
+
+// CHECK: vpackuswb (%rcx), %ymm19, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0xe5,0x20,0x67,0x21]
+          vpackuswb (%rcx), %ymm19, %ymm20
+
+// CHECK: vpackuswb 4660(%rax,%r14,8), %ymm19, %ymm20
+// CHECK:  encoding: [0x62,0xa1,0xe5,0x20,0x67,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vpackuswb 4660(%rax,%r14,8), %ymm19, %ymm20
+
+// CHECK: vpackuswb 4064(%rdx), %ymm19, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0xe5,0x20,0x67,0x62,0x7f]
+          vpackuswb 4064(%rdx), %ymm19, %ymm20
+
+// CHECK: vpackuswb 4096(%rdx), %ymm19, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0xe5,0x20,0x67,0xa2,0x00,0x10,0x00,0x00]
+          vpackuswb 4096(%rdx), %ymm19, %ymm20
+
+// CHECK: vpackuswb -4096(%rdx), %ymm19, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0xe5,0x20,0x67,0x62,0x80]
+          vpackuswb -4096(%rdx), %ymm19, %ymm20
+
+// CHECK: vpackuswb -4128(%rdx), %ymm19, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0xe5,0x20,0x67,0xa2,0xe0,0xef,0xff,0xff]
+          vpackuswb -4128(%rdx), %ymm19, %ymm20
+
+// CHECK: vpaddsb %xmm27, %xmm19, %xmm19
+// CHECK:  encoding: [0x62,0x81,0x65,0x00,0xec,0xdb]
+          vpaddsb %xmm27, %xmm19, %xmm19
+
+// CHECK: vpaddsb %xmm27, %xmm19, %xmm19 {%k2}
+// CHECK:  encoding: [0x62,0x81,0x65,0x02,0xec,0xdb]
+          vpaddsb %xmm27, %xmm19, %xmm19 {%k2}
+
+// CHECK: vpaddsb %xmm27, %xmm19, %xmm19 {%k2} {z}
+// CHECK:  encoding: [0x62,0x81,0x65,0x82,0xec,0xdb]
+          vpaddsb %xmm27, %xmm19, %xmm19 {%k2} {z}
+
+// CHECK: vpaddsb (%rcx), %xmm19, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x65,0x00,0xec,0x19]
+          vpaddsb (%rcx), %xmm19, %xmm19
+
+// CHECK: vpaddsb 291(%rax,%r14,8), %xmm19, %xmm19
+// CHECK:  encoding: [0x62,0xa1,0x65,0x00,0xec,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpaddsb 291(%rax,%r14,8), %xmm19, %xmm19
+
+// CHECK: vpaddsb 2032(%rdx), %xmm19, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x65,0x00,0xec,0x5a,0x7f]
+          vpaddsb 2032(%rdx), %xmm19, %xmm19
+
+// CHECK: vpaddsb 2048(%rdx), %xmm19, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x65,0x00,0xec,0x9a,0x00,0x08,0x00,0x00]
+          vpaddsb 2048(%rdx), %xmm19, %xmm19
+
+// CHECK: vpaddsb -2048(%rdx), %xmm19, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x65,0x00,0xec,0x5a,0x80]
+          vpaddsb -2048(%rdx), %xmm19, %xmm19
+
+// CHECK: vpaddsb -2064(%rdx), %xmm19, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x65,0x00,0xec,0x9a,0xf0,0xf7,0xff,0xff]
+          vpaddsb -2064(%rdx), %xmm19, %xmm19
+
+// CHECK: vpaddsb %ymm27, %ymm21, %ymm19
+// CHECK:  encoding: [0x62,0x81,0x55,0x20,0xec,0xdb]
+          vpaddsb %ymm27, %ymm21, %ymm19
+
+// CHECK: vpaddsb %ymm27, %ymm21, %ymm19 {%k4}
+// CHECK:  encoding: [0x62,0x81,0x55,0x24,0xec,0xdb]
+          vpaddsb %ymm27, %ymm21, %ymm19 {%k4}
+
+// CHECK: vpaddsb %ymm27, %ymm21, %ymm19 {%k4} {z}
+// CHECK:  encoding: [0x62,0x81,0x55,0xa4,0xec,0xdb]
+          vpaddsb %ymm27, %ymm21, %ymm19 {%k4} {z}
+
+// CHECK: vpaddsb (%rcx), %ymm21, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xec,0x19]
+          vpaddsb (%rcx), %ymm21, %ymm19
+
+// CHECK: vpaddsb 291(%rax,%r14,8), %ymm21, %ymm19
+// CHECK:  encoding: [0x62,0xa1,0x55,0x20,0xec,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpaddsb 291(%rax,%r14,8), %ymm21, %ymm19
+
+// CHECK: vpaddsb 4064(%rdx), %ymm21, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xec,0x5a,0x7f]
+          vpaddsb 4064(%rdx), %ymm21, %ymm19
+
+// CHECK: vpaddsb 4096(%rdx), %ymm21, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xec,0x9a,0x00,0x10,0x00,0x00]
+          vpaddsb 4096(%rdx), %ymm21, %ymm19
+
+// CHECK: vpaddsb -4096(%rdx), %ymm21, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xec,0x5a,0x80]
+          vpaddsb -4096(%rdx), %ymm21, %ymm19
+
+// CHECK: vpaddsb -4128(%rdx), %ymm21, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xec,0x9a,0xe0,0xef,0xff,0xff]
+          vpaddsb -4128(%rdx), %ymm21, %ymm19
+
+// CHECK: vpaddsw %xmm21, %xmm27, %xmm29
+// CHECK:  encoding: [0x62,0x21,0x25,0x00,0xed,0xed]
+          vpaddsw %xmm21, %xmm27, %xmm29
+
+// CHECK: vpaddsw %xmm21, %xmm27, %xmm29 {%k1}
+// CHECK:  encoding: [0x62,0x21,0x25,0x01,0xed,0xed]
+          vpaddsw %xmm21, %xmm27, %xmm29 {%k1}
+
+// CHECK: vpaddsw %xmm21, %xmm27, %xmm29 {%k1} {z}
+// CHECK:  encoding: [0x62,0x21,0x25,0x81,0xed,0xed]
+          vpaddsw %xmm21, %xmm27, %xmm29 {%k1} {z}
+
+// CHECK: vpaddsw (%rcx), %xmm27, %xmm29
+// CHECK:  encoding: [0x62,0x61,0x25,0x00,0xed,0x29]
+          vpaddsw (%rcx), %xmm27, %xmm29
+
+// CHECK: vpaddsw 291(%rax,%r14,8), %xmm27, %xmm29
+// CHECK:  encoding: [0x62,0x21,0x25,0x00,0xed,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpaddsw 291(%rax,%r14,8), %xmm27, %xmm29
+
+// CHECK: vpaddsw 2032(%rdx), %xmm27, %xmm29
+// CHECK:  encoding: [0x62,0x61,0x25,0x00,0xed,0x6a,0x7f]
+          vpaddsw 2032(%rdx), %xmm27, %xmm29
+
+// CHECK: vpaddsw 2048(%rdx), %xmm27, %xmm29
+// CHECK:  encoding: [0x62,0x61,0x25,0x00,0xed,0xaa,0x00,0x08,0x00,0x00]
+          vpaddsw 2048(%rdx), %xmm27, %xmm29
+
+// CHECK: vpaddsw -2048(%rdx), %xmm27, %xmm29
+// CHECK:  encoding: [0x62,0x61,0x25,0x00,0xed,0x6a,0x80]
+          vpaddsw -2048(%rdx), %xmm27, %xmm29
+
+// CHECK: vpaddsw -2064(%rdx), %xmm27, %xmm29
+// CHECK:  encoding: [0x62,0x61,0x25,0x00,0xed,0xaa,0xf0,0xf7,0xff,0xff]
+          vpaddsw -2064(%rdx), %xmm27, %xmm29
+
+// CHECK: vpaddsw %ymm26, %ymm17, %ymm22
+// CHECK:  encoding: [0x62,0x81,0x75,0x20,0xed,0xf2]
+          vpaddsw %ymm26, %ymm17, %ymm22
+
+// CHECK: vpaddsw %ymm26, %ymm17, %ymm22 {%k3}
+// CHECK:  encoding: [0x62,0x81,0x75,0x23,0xed,0xf2]
+          vpaddsw %ymm26, %ymm17, %ymm22 {%k3}
+
+// CHECK: vpaddsw %ymm26, %ymm17, %ymm22 {%k3} {z}
+// CHECK:  encoding: [0x62,0x81,0x75,0xa3,0xed,0xf2]
+          vpaddsw %ymm26, %ymm17, %ymm22 {%k3} {z}
+
+// CHECK: vpaddsw (%rcx), %ymm17, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x75,0x20,0xed,0x31]
+          vpaddsw (%rcx), %ymm17, %ymm22
+
+// CHECK: vpaddsw 291(%rax,%r14,8), %ymm17, %ymm22
+// CHECK:  encoding: [0x62,0xa1,0x75,0x20,0xed,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpaddsw 291(%rax,%r14,8), %ymm17, %ymm22
+
+// CHECK: vpaddsw 4064(%rdx), %ymm17, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x75,0x20,0xed,0x72,0x7f]
+          vpaddsw 4064(%rdx), %ymm17, %ymm22
+
+// CHECK: vpaddsw 4096(%rdx), %ymm17, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x75,0x20,0xed,0xb2,0x00,0x10,0x00,0x00]
+          vpaddsw 4096(%rdx), %ymm17, %ymm22
+
+// CHECK: vpaddsw -4096(%rdx), %ymm17, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x75,0x20,0xed,0x72,0x80]
+          vpaddsw -4096(%rdx), %ymm17, %ymm22
+
+// CHECK: vpaddsw -4128(%rdx), %ymm17, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x75,0x20,0xed,0xb2,0xe0,0xef,0xff,0xff]
+          vpaddsw -4128(%rdx), %ymm17, %ymm22
+
+// CHECK: vpaddusb %xmm26, %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0x81,0x1d,0x00,0xdc,0xea]
+          vpaddusb %xmm26, %xmm28, %xmm21
+
+// CHECK: vpaddusb %xmm26, %xmm28, %xmm21 {%k5}
+// CHECK:  encoding: [0x62,0x81,0x1d,0x05,0xdc,0xea]
+          vpaddusb %xmm26, %xmm28, %xmm21 {%k5}
+
+// CHECK: vpaddusb %xmm26, %xmm28, %xmm21 {%k5} {z}
+// CHECK:  encoding: [0x62,0x81,0x1d,0x85,0xdc,0xea]
+          vpaddusb %xmm26, %xmm28, %xmm21 {%k5} {z}
+
+// CHECK: vpaddusb (%rcx), %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x00,0xdc,0x29]
+          vpaddusb (%rcx), %xmm28, %xmm21
+
+// CHECK: vpaddusb 291(%rax,%r14,8), %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xa1,0x1d,0x00,0xdc,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpaddusb 291(%rax,%r14,8), %xmm28, %xmm21
+
+// CHECK: vpaddusb 2032(%rdx), %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x00,0xdc,0x6a,0x7f]
+          vpaddusb 2032(%rdx), %xmm28, %xmm21
+
+// CHECK: vpaddusb 2048(%rdx), %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x00,0xdc,0xaa,0x00,0x08,0x00,0x00]
+          vpaddusb 2048(%rdx), %xmm28, %xmm21
+
+// CHECK: vpaddusb -2048(%rdx), %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x00,0xdc,0x6a,0x80]
+          vpaddusb -2048(%rdx), %xmm28, %xmm21
+
+// CHECK: vpaddusb -2064(%rdx), %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x1d,0x00,0xdc,0xaa,0xf0,0xf7,0xff,0xff]
+          vpaddusb -2064(%rdx), %xmm28, %xmm21
+
+// CHECK: vpaddusb %ymm17, %ymm23, %ymm20
+// CHECK:  encoding: [0x62,0xa1,0x45,0x20,0xdc,0xe1]
+          vpaddusb %ymm17, %ymm23, %ymm20
+
+// CHECK: vpaddusb %ymm17, %ymm23, %ymm20 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0x45,0x21,0xdc,0xe1]
+          vpaddusb %ymm17, %ymm23, %ymm20 {%k1}
+
+// CHECK: vpaddusb %ymm17, %ymm23, %ymm20 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0x45,0xa1,0xdc,0xe1]
+          vpaddusb %ymm17, %ymm23, %ymm20 {%k1} {z}
+
+// CHECK: vpaddusb (%rcx), %ymm23, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x45,0x20,0xdc,0x21]
+          vpaddusb (%rcx), %ymm23, %ymm20
+
+// CHECK: vpaddusb 291(%rax,%r14,8), %ymm23, %ymm20
+// CHECK:  encoding: [0x62,0xa1,0x45,0x20,0xdc,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpaddusb 291(%rax,%r14,8), %ymm23, %ymm20
+
+// CHECK: vpaddusb 4064(%rdx), %ymm23, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x45,0x20,0xdc,0x62,0x7f]
+          vpaddusb 4064(%rdx), %ymm23, %ymm20
+
+// CHECK: vpaddusb 4096(%rdx), %ymm23, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x45,0x20,0xdc,0xa2,0x00,0x10,0x00,0x00]
+          vpaddusb 4096(%rdx), %ymm23, %ymm20
+
+// CHECK: vpaddusb -4096(%rdx), %ymm23, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x45,0x20,0xdc,0x62,0x80]
+          vpaddusb -4096(%rdx), %ymm23, %ymm20
+
+// CHECK: vpaddusb -4128(%rdx), %ymm23, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x45,0x20,0xdc,0xa2,0xe0,0xef,0xff,0xff]
+          vpaddusb -4128(%rdx), %ymm23, %ymm20
+
+// CHECK: vpaddusw %xmm24, %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0x81,0x25,0x00,0xdd,0xf8]
+          vpaddusw %xmm24, %xmm27, %xmm23
+
+// CHECK: vpaddusw %xmm24, %xmm27, %xmm23 {%k2}
+// CHECK:  encoding: [0x62,0x81,0x25,0x02,0xdd,0xf8]
+          vpaddusw %xmm24, %xmm27, %xmm23 {%k2}
+
+// CHECK: vpaddusw %xmm24, %xmm27, %xmm23 {%k2} {z}
+// CHECK:  encoding: [0x62,0x81,0x25,0x82,0xdd,0xf8]
+          vpaddusw %xmm24, %xmm27, %xmm23 {%k2} {z}
+
+// CHECK: vpaddusw (%rcx), %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xdd,0x39]
+          vpaddusw (%rcx), %xmm27, %xmm23
+
+// CHECK: vpaddusw 291(%rax,%r14,8), %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xa1,0x25,0x00,0xdd,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vpaddusw 291(%rax,%r14,8), %xmm27, %xmm23
+
+// CHECK: vpaddusw 2032(%rdx), %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xdd,0x7a,0x7f]
+          vpaddusw 2032(%rdx), %xmm27, %xmm23
+
+// CHECK: vpaddusw 2048(%rdx), %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xdd,0xba,0x00,0x08,0x00,0x00]
+          vpaddusw 2048(%rdx), %xmm27, %xmm23
+
+// CHECK: vpaddusw -2048(%rdx), %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xdd,0x7a,0x80]
+          vpaddusw -2048(%rdx), %xmm27, %xmm23
+
+// CHECK: vpaddusw -2064(%rdx), %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xdd,0xba,0xf0,0xf7,0xff,0xff]
+          vpaddusw -2064(%rdx), %xmm27, %xmm23
+
+// CHECK: vpaddusw %ymm17, %ymm22, %ymm23
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x20,0xdd,0xf9]
+          vpaddusw %ymm17, %ymm22, %ymm23
+
+// CHECK: vpaddusw %ymm17, %ymm22, %ymm23 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x21,0xdd,0xf9]
+          vpaddusw %ymm17, %ymm22, %ymm23 {%k1}
+
+// CHECK: vpaddusw %ymm17, %ymm22, %ymm23 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0x4d,0xa1,0xdd,0xf9]
+          vpaddusw %ymm17, %ymm22, %ymm23 {%k1} {z}
+
+// CHECK: vpaddusw (%rcx), %ymm22, %ymm23
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x20,0xdd,0x39]
+          vpaddusw (%rcx), %ymm22, %ymm23
+
+// CHECK: vpaddusw 291(%rax,%r14,8), %ymm22, %ymm23
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x20,0xdd,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vpaddusw 291(%rax,%r14,8), %ymm22, %ymm23
+
+// CHECK: vpaddusw 4064(%rdx), %ymm22, %ymm23
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x20,0xdd,0x7a,0x7f]
+          vpaddusw 4064(%rdx), %ymm22, %ymm23
+
+// CHECK: vpaddusw 4096(%rdx), %ymm22, %ymm23
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x20,0xdd,0xba,0x00,0x10,0x00,0x00]
+          vpaddusw 4096(%rdx), %ymm22, %ymm23
+
+// CHECK: vpaddusw -4096(%rdx), %ymm22, %ymm23
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x20,0xdd,0x7a,0x80]
+          vpaddusw -4096(%rdx), %ymm22, %ymm23
+
+// CHECK: vpaddusw -4128(%rdx), %ymm22, %ymm23
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x20,0xdd,0xba,0xe0,0xef,0xff,0xff]
+          vpaddusw -4128(%rdx), %ymm22, %ymm23
+
+// CHECK: vpsubsb %xmm27, %xmm17, %xmm17
+// CHECK:  encoding: [0x62,0x81,0x75,0x00,0xe8,0xcb]
+          vpsubsb %xmm27, %xmm17, %xmm17
+
+// CHECK: vpsubsb %xmm27, %xmm17, %xmm17 {%k7}
+// CHECK:  encoding: [0x62,0x81,0x75,0x07,0xe8,0xcb]
+          vpsubsb %xmm27, %xmm17, %xmm17 {%k7}
+
+// CHECK: vpsubsb %xmm27, %xmm17, %xmm17 {%k7} {z}
+// CHECK:  encoding: [0x62,0x81,0x75,0x87,0xe8,0xcb]
+          vpsubsb %xmm27, %xmm17, %xmm17 {%k7} {z}
+
+// CHECK: vpsubsb (%rcx), %xmm17, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x75,0x00,0xe8,0x09]
+          vpsubsb (%rcx), %xmm17, %xmm17
+
+// CHECK: vpsubsb 291(%rax,%r14,8), %xmm17, %xmm17
+// CHECK:  encoding: [0x62,0xa1,0x75,0x00,0xe8,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpsubsb 291(%rax,%r14,8), %xmm17, %xmm17
+
+// CHECK: vpsubsb 2032(%rdx), %xmm17, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x75,0x00,0xe8,0x4a,0x7f]
+          vpsubsb 2032(%rdx), %xmm17, %xmm17
+
+// CHECK: vpsubsb 2048(%rdx), %xmm17, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x75,0x00,0xe8,0x8a,0x00,0x08,0x00,0x00]
+          vpsubsb 2048(%rdx), %xmm17, %xmm17
+
+// CHECK: vpsubsb -2048(%rdx), %xmm17, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x75,0x00,0xe8,0x4a,0x80]
+          vpsubsb -2048(%rdx), %xmm17, %xmm17
+
+// CHECK: vpsubsb -2064(%rdx), %xmm17, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x75,0x00,0xe8,0x8a,0xf0,0xf7,0xff,0xff]
+          vpsubsb -2064(%rdx), %xmm17, %xmm17
+
+// CHECK: vpsubsb %ymm27, %ymm25, %ymm17
+// CHECK:  encoding: [0x62,0x81,0x35,0x20,0xe8,0xcb]
+          vpsubsb %ymm27, %ymm25, %ymm17
+
+// CHECK: vpsubsb %ymm27, %ymm25, %ymm17 {%k2}
+// CHECK:  encoding: [0x62,0x81,0x35,0x22,0xe8,0xcb]
+          vpsubsb %ymm27, %ymm25, %ymm17 {%k2}
+
+// CHECK: vpsubsb %ymm27, %ymm25, %ymm17 {%k2} {z}
+// CHECK:  encoding: [0x62,0x81,0x35,0xa2,0xe8,0xcb]
+          vpsubsb %ymm27, %ymm25, %ymm17 {%k2} {z}
+
+// CHECK: vpsubsb (%rcx), %ymm25, %ymm17
+// CHECK:  encoding: [0x62,0xe1,0x35,0x20,0xe8,0x09]
+          vpsubsb (%rcx), %ymm25, %ymm17
+
+// CHECK: vpsubsb 291(%rax,%r14,8), %ymm25, %ymm17
+// CHECK:  encoding: [0x62,0xa1,0x35,0x20,0xe8,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpsubsb 291(%rax,%r14,8), %ymm25, %ymm17
+
+// CHECK: vpsubsb 4064(%rdx), %ymm25, %ymm17
+// CHECK:  encoding: [0x62,0xe1,0x35,0x20,0xe8,0x4a,0x7f]
+          vpsubsb 4064(%rdx), %ymm25, %ymm17
+
+// CHECK: vpsubsb 4096(%rdx), %ymm25, %ymm17
+// CHECK:  encoding: [0x62,0xe1,0x35,0x20,0xe8,0x8a,0x00,0x10,0x00,0x00]
+          vpsubsb 4096(%rdx), %ymm25, %ymm17
+
+// CHECK: vpsubsb -4096(%rdx), %ymm25, %ymm17
+// CHECK:  encoding: [0x62,0xe1,0x35,0x20,0xe8,0x4a,0x80]
+          vpsubsb -4096(%rdx), %ymm25, %ymm17
+
+// CHECK: vpsubsb -4128(%rdx), %ymm25, %ymm17
+// CHECK:  encoding: [0x62,0xe1,0x35,0x20,0xe8,0x8a,0xe0,0xef,0xff,0xff]
+          vpsubsb -4128(%rdx), %ymm25, %ymm17
+
+// CHECK: vpsubsw %xmm23, %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x21,0x2d,0x00,0xe9,0xf7]
+          vpsubsw %xmm23, %xmm26, %xmm30
+
+// CHECK: vpsubsw %xmm23, %xmm26, %xmm30 {%k7}
+// CHECK:  encoding: [0x62,0x21,0x2d,0x07,0xe9,0xf7]
+          vpsubsw %xmm23, %xmm26, %xmm30 {%k7}
+
+// CHECK: vpsubsw %xmm23, %xmm26, %xmm30 {%k7} {z}
+// CHECK:  encoding: [0x62,0x21,0x2d,0x87,0xe9,0xf7]
+          vpsubsw %xmm23, %xmm26, %xmm30 {%k7} {z}
+
+// CHECK: vpsubsw (%rcx), %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x2d,0x00,0xe9,0x31]
+          vpsubsw (%rcx), %xmm26, %xmm30
+
+// CHECK: vpsubsw 291(%rax,%r14,8), %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x21,0x2d,0x00,0xe9,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpsubsw 291(%rax,%r14,8), %xmm26, %xmm30
+
+// CHECK: vpsubsw 2032(%rdx), %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x2d,0x00,0xe9,0x72,0x7f]
+          vpsubsw 2032(%rdx), %xmm26, %xmm30
+
+// CHECK: vpsubsw 2048(%rdx), %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x2d,0x00,0xe9,0xb2,0x00,0x08,0x00,0x00]
+          vpsubsw 2048(%rdx), %xmm26, %xmm30
+
+// CHECK: vpsubsw -2048(%rdx), %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x2d,0x00,0xe9,0x72,0x80]
+          vpsubsw -2048(%rdx), %xmm26, %xmm30
+
+// CHECK: vpsubsw -2064(%rdx), %xmm26, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x2d,0x00,0xe9,0xb2,0xf0,0xf7,0xff,0xff]
+          vpsubsw -2064(%rdx), %xmm26, %xmm30
+
+// CHECK: vpsubsw %ymm17, %ymm29, %ymm19
+// CHECK:  encoding: [0x62,0xa1,0x15,0x20,0xe9,0xd9]
+          vpsubsw %ymm17, %ymm29, %ymm19
+
+// CHECK: vpsubsw %ymm17, %ymm29, %ymm19 {%k2}
+// CHECK:  encoding: [0x62,0xa1,0x15,0x22,0xe9,0xd9]
+          vpsubsw %ymm17, %ymm29, %ymm19 {%k2}
+
+// CHECK: vpsubsw %ymm17, %ymm29, %ymm19 {%k2} {z}
+// CHECK:  encoding: [0x62,0xa1,0x15,0xa2,0xe9,0xd9]
+          vpsubsw %ymm17, %ymm29, %ymm19 {%k2} {z}
+
+// CHECK: vpsubsw (%rcx), %ymm29, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x15,0x20,0xe9,0x19]
+          vpsubsw (%rcx), %ymm29, %ymm19
+
+// CHECK: vpsubsw 291(%rax,%r14,8), %ymm29, %ymm19
+// CHECK:  encoding: [0x62,0xa1,0x15,0x20,0xe9,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpsubsw 291(%rax,%r14,8), %ymm29, %ymm19
+
+// CHECK: vpsubsw 4064(%rdx), %ymm29, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x15,0x20,0xe9,0x5a,0x7f]
+          vpsubsw 4064(%rdx), %ymm29, %ymm19
+
+// CHECK: vpsubsw 4096(%rdx), %ymm29, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x15,0x20,0xe9,0x9a,0x00,0x10,0x00,0x00]
+          vpsubsw 4096(%rdx), %ymm29, %ymm19
+
+// CHECK: vpsubsw -4096(%rdx), %ymm29, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x15,0x20,0xe9,0x5a,0x80]
+          vpsubsw -4096(%rdx), %ymm29, %ymm19
+
+// CHECK: vpsubsw -4128(%rdx), %ymm29, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x15,0x20,0xe9,0x9a,0xe0,0xef,0xff,0xff]
+          vpsubsw -4128(%rdx), %ymm29, %ymm19
+
+// CHECK: vpsubusb %xmm23, %xmm27, %xmm17
+// CHECK:  encoding: [0x62,0xa1,0x25,0x00,0xd8,0xcf]
+          vpsubusb %xmm23, %xmm27, %xmm17
+
+// CHECK: vpsubusb %xmm23, %xmm27, %xmm17 {%k6}
+// CHECK:  encoding: [0x62,0xa1,0x25,0x06,0xd8,0xcf]
+          vpsubusb %xmm23, %xmm27, %xmm17 {%k6}
+
+// CHECK: vpsubusb %xmm23, %xmm27, %xmm17 {%k6} {z}
+// CHECK:  encoding: [0x62,0xa1,0x25,0x86,0xd8,0xcf]
+          vpsubusb %xmm23, %xmm27, %xmm17 {%k6} {z}
+
+// CHECK: vpsubusb (%rcx), %xmm27, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xd8,0x09]
+          vpsubusb (%rcx), %xmm27, %xmm17
+
+// CHECK: vpsubusb 291(%rax,%r14,8), %xmm27, %xmm17
+// CHECK:  encoding: [0x62,0xa1,0x25,0x00,0xd8,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpsubusb 291(%rax,%r14,8), %xmm27, %xmm17
+
+// CHECK: vpsubusb 2032(%rdx), %xmm27, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xd8,0x4a,0x7f]
+          vpsubusb 2032(%rdx), %xmm27, %xmm17
+
+// CHECK: vpsubusb 2048(%rdx), %xmm27, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xd8,0x8a,0x00,0x08,0x00,0x00]
+          vpsubusb 2048(%rdx), %xmm27, %xmm17
+
+// CHECK: vpsubusb -2048(%rdx), %xmm27, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xd8,0x4a,0x80]
+          vpsubusb -2048(%rdx), %xmm27, %xmm17
+
+// CHECK: vpsubusb -2064(%rdx), %xmm27, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xd8,0x8a,0xf0,0xf7,0xff,0xff]
+          vpsubusb -2064(%rdx), %xmm27, %xmm17
+
+// CHECK: vpsubusb %ymm18, %ymm21, %ymm17
+// CHECK:  encoding: [0x62,0xa1,0x55,0x20,0xd8,0xca]
+          vpsubusb %ymm18, %ymm21, %ymm17
+
+// CHECK: vpsubusb %ymm18, %ymm21, %ymm17 {%k5}
+// CHECK:  encoding: [0x62,0xa1,0x55,0x25,0xd8,0xca]
+          vpsubusb %ymm18, %ymm21, %ymm17 {%k5}
+
+// CHECK: vpsubusb %ymm18, %ymm21, %ymm17 {%k5} {z}
+// CHECK:  encoding: [0x62,0xa1,0x55,0xa5,0xd8,0xca]
+          vpsubusb %ymm18, %ymm21, %ymm17 {%k5} {z}
+
+// CHECK: vpsubusb (%rcx), %ymm21, %ymm17
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xd8,0x09]
+          vpsubusb (%rcx), %ymm21, %ymm17
+
+// CHECK: vpsubusb 291(%rax,%r14,8), %ymm21, %ymm17
+// CHECK:  encoding: [0x62,0xa1,0x55,0x20,0xd8,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpsubusb 291(%rax,%r14,8), %ymm21, %ymm17
+
+// CHECK: vpsubusb 4064(%rdx), %ymm21, %ymm17
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xd8,0x4a,0x7f]
+          vpsubusb 4064(%rdx), %ymm21, %ymm17
+
+// CHECK: vpsubusb 4096(%rdx), %ymm21, %ymm17
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xd8,0x8a,0x00,0x10,0x00,0x00]
+          vpsubusb 4096(%rdx), %ymm21, %ymm17
+
+// CHECK: vpsubusb -4096(%rdx), %ymm21, %ymm17
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xd8,0x4a,0x80]
+          vpsubusb -4096(%rdx), %ymm21, %ymm17
+
+// CHECK: vpsubusb -4128(%rdx), %ymm21, %ymm17
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xd8,0x8a,0xe0,0xef,0xff,0xff]
+          vpsubusb -4128(%rdx), %ymm21, %ymm17
+
+// CHECK: vpsubusw %xmm19, %xmm21, %xmm25
+// CHECK:  encoding: [0x62,0x21,0x55,0x00,0xd9,0xcb]
+          vpsubusw %xmm19, %xmm21, %xmm25
+
+// CHECK: vpsubusw %xmm19, %xmm21, %xmm25 {%k6}
+// CHECK:  encoding: [0x62,0x21,0x55,0x06,0xd9,0xcb]
+          vpsubusw %xmm19, %xmm21, %xmm25 {%k6}
+
+// CHECK: vpsubusw %xmm19, %xmm21, %xmm25 {%k6} {z}
+// CHECK:  encoding: [0x62,0x21,0x55,0x86,0xd9,0xcb]
+          vpsubusw %xmm19, %xmm21, %xmm25 {%k6} {z}
+
+// CHECK: vpsubusw (%rcx), %xmm21, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x55,0x00,0xd9,0x09]
+          vpsubusw (%rcx), %xmm21, %xmm25
+
+// CHECK: vpsubusw 291(%rax,%r14,8), %xmm21, %xmm25
+// CHECK:  encoding: [0x62,0x21,0x55,0x00,0xd9,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpsubusw 291(%rax,%r14,8), %xmm21, %xmm25
+
+// CHECK: vpsubusw 2032(%rdx), %xmm21, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x55,0x00,0xd9,0x4a,0x7f]
+          vpsubusw 2032(%rdx), %xmm21, %xmm25
+
+// CHECK: vpsubusw 2048(%rdx), %xmm21, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x55,0x00,0xd9,0x8a,0x00,0x08,0x00,0x00]
+          vpsubusw 2048(%rdx), %xmm21, %xmm25
+
+// CHECK: vpsubusw -2048(%rdx), %xmm21, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x55,0x00,0xd9,0x4a,0x80]
+          vpsubusw -2048(%rdx), %xmm21, %xmm25
+
+// CHECK: vpsubusw -2064(%rdx), %xmm21, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x55,0x00,0xd9,0x8a,0xf0,0xf7,0xff,0xff]
+          vpsubusw -2064(%rdx), %xmm21, %xmm25
+
+// CHECK: vpsubusw %ymm17, %ymm17, %ymm26
+// CHECK:  encoding: [0x62,0x21,0x75,0x20,0xd9,0xd1]
+          vpsubusw %ymm17, %ymm17, %ymm26
+
+// CHECK: vpsubusw %ymm17, %ymm17, %ymm26 {%k4}
+// CHECK:  encoding: [0x62,0x21,0x75,0x24,0xd9,0xd1]
+          vpsubusw %ymm17, %ymm17, %ymm26 {%k4}
+
+// CHECK: vpsubusw %ymm17, %ymm17, %ymm26 {%k4} {z}
+// CHECK:  encoding: [0x62,0x21,0x75,0xa4,0xd9,0xd1]
+          vpsubusw %ymm17, %ymm17, %ymm26 {%k4} {z}
+
+// CHECK: vpsubusw (%rcx), %ymm17, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x75,0x20,0xd9,0x11]
+          vpsubusw (%rcx), %ymm17, %ymm26
+
+// CHECK: vpsubusw 291(%rax,%r14,8), %ymm17, %ymm26
+// CHECK:  encoding: [0x62,0x21,0x75,0x20,0xd9,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vpsubusw 291(%rax,%r14,8), %ymm17, %ymm26
+
+// CHECK: vpsubusw 4064(%rdx), %ymm17, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x75,0x20,0xd9,0x52,0x7f]
+          vpsubusw 4064(%rdx), %ymm17, %ymm26
+
+// CHECK: vpsubusw 4096(%rdx), %ymm17, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x75,0x20,0xd9,0x92,0x00,0x10,0x00,0x00]
+          vpsubusw 4096(%rdx), %ymm17, %ymm26
+
+// CHECK: vpsubusw -4096(%rdx), %ymm17, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x75,0x20,0xd9,0x52,0x80]
+          vpsubusw -4096(%rdx), %ymm17, %ymm26
+
+// CHECK: vpsubusw -4128(%rdx), %ymm17, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x75,0x20,0xd9,0x92,0xe0,0xef,0xff,0xff]
+          vpsubusw -4128(%rdx), %ymm17, %ymm26
+
+// CHECK: vpaddsb %xmm23, %xmm24, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0x3d,0x00,0xec,0xe7]
+          vpaddsb %xmm23, %xmm24, %xmm20
+
+// CHECK: vpaddsb %xmm23, %xmm24, %xmm20 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0x3d,0x01,0xec,0xe7]
+          vpaddsb %xmm23, %xmm24, %xmm20 {%k1}
+
+// CHECK: vpaddsb %xmm23, %xmm24, %xmm20 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0x3d,0x81,0xec,0xe7]
+          vpaddsb %xmm23, %xmm24, %xmm20 {%k1} {z}
+
+// CHECK: vpaddsb (%rcx), %xmm24, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x3d,0x00,0xec,0x21]
+          vpaddsb (%rcx), %xmm24, %xmm20
+
+// CHECK: vpaddsb 4660(%rax,%r14,8), %xmm24, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0x3d,0x00,0xec,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vpaddsb 4660(%rax,%r14,8), %xmm24, %xmm20
+
+// CHECK: vpaddsb 2032(%rdx), %xmm24, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x3d,0x00,0xec,0x62,0x7f]
+          vpaddsb 2032(%rdx), %xmm24, %xmm20
+
+// CHECK: vpaddsb 2048(%rdx), %xmm24, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x3d,0x00,0xec,0xa2,0x00,0x08,0x00,0x00]
+          vpaddsb 2048(%rdx), %xmm24, %xmm20
+
+// CHECK: vpaddsb -2048(%rdx), %xmm24, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x3d,0x00,0xec,0x62,0x80]
+          vpaddsb -2048(%rdx), %xmm24, %xmm20
+
+// CHECK: vpaddsb -2064(%rdx), %xmm24, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x3d,0x00,0xec,0xa2,0xf0,0xf7,0xff,0xff]
+          vpaddsb -2064(%rdx), %xmm24, %xmm20
+
+// CHECK: vpaddsb %ymm19, %ymm20, %ymm18
+// CHECK:  encoding: [0x62,0xa1,0x5d,0x20,0xec,0xd3]
+          vpaddsb %ymm19, %ymm20, %ymm18
+
+// CHECK: vpaddsb %ymm19, %ymm20, %ymm18 {%k7}
+// CHECK:  encoding: [0x62,0xa1,0x5d,0x27,0xec,0xd3]
+          vpaddsb %ymm19, %ymm20, %ymm18 {%k7}
+
+// CHECK: vpaddsb %ymm19, %ymm20, %ymm18 {%k7} {z}
+// CHECK:  encoding: [0x62,0xa1,0x5d,0xa7,0xec,0xd3]
+          vpaddsb %ymm19, %ymm20, %ymm18 {%k7} {z}
+
+// CHECK: vpaddsb (%rcx), %ymm20, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x20,0xec,0x11]
+          vpaddsb (%rcx), %ymm20, %ymm18
+
+// CHECK: vpaddsb 4660(%rax,%r14,8), %ymm20, %ymm18
+// CHECK:  encoding: [0x62,0xa1,0x5d,0x20,0xec,0x94,0xf0,0x34,0x12,0x00,0x00]
+          vpaddsb 4660(%rax,%r14,8), %ymm20, %ymm18
+
+// CHECK: vpaddsb 4064(%rdx), %ymm20, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x20,0xec,0x52,0x7f]
+          vpaddsb 4064(%rdx), %ymm20, %ymm18
+
+// CHECK: vpaddsb 4096(%rdx), %ymm20, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x20,0xec,0x92,0x00,0x10,0x00,0x00]
+          vpaddsb 4096(%rdx), %ymm20, %ymm18
+
+// CHECK: vpaddsb -4096(%rdx), %ymm20, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x20,0xec,0x52,0x80]
+          vpaddsb -4096(%rdx), %ymm20, %ymm18
+
+// CHECK: vpaddsb -4128(%rdx), %ymm20, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x20,0xec,0x92,0xe0,0xef,0xff,0xff]
+          vpaddsb -4128(%rdx), %ymm20, %ymm18
+
+// CHECK: vpaddsw %xmm24, %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0x81,0x45,0x00,0xed,0xf8]
+          vpaddsw %xmm24, %xmm23, %xmm23
+
+// CHECK: vpaddsw %xmm24, %xmm23, %xmm23 {%k5}
+// CHECK:  encoding: [0x62,0x81,0x45,0x05,0xed,0xf8]
+          vpaddsw %xmm24, %xmm23, %xmm23 {%k5}
+
+// CHECK: vpaddsw %xmm24, %xmm23, %xmm23 {%k5} {z}
+// CHECK:  encoding: [0x62,0x81,0x45,0x85,0xed,0xf8]
+          vpaddsw %xmm24, %xmm23, %xmm23 {%k5} {z}
+
+// CHECK: vpaddsw (%rcx), %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x45,0x00,0xed,0x39]
+          vpaddsw (%rcx), %xmm23, %xmm23
+
+// CHECK: vpaddsw 4660(%rax,%r14,8), %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xa1,0x45,0x00,0xed,0xbc,0xf0,0x34,0x12,0x00,0x00]
+          vpaddsw 4660(%rax,%r14,8), %xmm23, %xmm23
+
+// CHECK: vpaddsw 2032(%rdx), %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x45,0x00,0xed,0x7a,0x7f]
+          vpaddsw 2032(%rdx), %xmm23, %xmm23
+
+// CHECK: vpaddsw 2048(%rdx), %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x45,0x00,0xed,0xba,0x00,0x08,0x00,0x00]
+          vpaddsw 2048(%rdx), %xmm23, %xmm23
+
+// CHECK: vpaddsw -2048(%rdx), %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x45,0x00,0xed,0x7a,0x80]
+          vpaddsw -2048(%rdx), %xmm23, %xmm23
+
+// CHECK: vpaddsw -2064(%rdx), %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x45,0x00,0xed,0xba,0xf0,0xf7,0xff,0xff]
+          vpaddsw -2064(%rdx), %xmm23, %xmm23
+
+// CHECK: vpaddsw %ymm19, %ymm22, %ymm29
+// CHECK:  encoding: [0x62,0x21,0x4d,0x20,0xed,0xeb]
+          vpaddsw %ymm19, %ymm22, %ymm29
+
+// CHECK: vpaddsw %ymm19, %ymm22, %ymm29 {%k6}
+// CHECK:  encoding: [0x62,0x21,0x4d,0x26,0xed,0xeb]
+          vpaddsw %ymm19, %ymm22, %ymm29 {%k6}
+
+// CHECK: vpaddsw %ymm19, %ymm22, %ymm29 {%k6} {z}
+// CHECK:  encoding: [0x62,0x21,0x4d,0xa6,0xed,0xeb]
+          vpaddsw %ymm19, %ymm22, %ymm29 {%k6} {z}
+
+// CHECK: vpaddsw (%rcx), %ymm22, %ymm29
+// CHECK:  encoding: [0x62,0x61,0x4d,0x20,0xed,0x29]
+          vpaddsw (%rcx), %ymm22, %ymm29
+
+// CHECK: vpaddsw 4660(%rax,%r14,8), %ymm22, %ymm29
+// CHECK:  encoding: [0x62,0x21,0x4d,0x20,0xed,0xac,0xf0,0x34,0x12,0x00,0x00]
+          vpaddsw 4660(%rax,%r14,8), %ymm22, %ymm29
+
+// CHECK: vpaddsw 4064(%rdx), %ymm22, %ymm29
+// CHECK:  encoding: [0x62,0x61,0x4d,0x20,0xed,0x6a,0x7f]
+          vpaddsw 4064(%rdx), %ymm22, %ymm29
+
+// CHECK: vpaddsw 4096(%rdx), %ymm22, %ymm29
+// CHECK:  encoding: [0x62,0x61,0x4d,0x20,0xed,0xaa,0x00,0x10,0x00,0x00]
+          vpaddsw 4096(%rdx), %ymm22, %ymm29
+
+// CHECK: vpaddsw -4096(%rdx), %ymm22, %ymm29
+// CHECK:  encoding: [0x62,0x61,0x4d,0x20,0xed,0x6a,0x80]
+          vpaddsw -4096(%rdx), %ymm22, %ymm29
+
+// CHECK: vpaddsw -4128(%rdx), %ymm22, %ymm29
+// CHECK:  encoding: [0x62,0x61,0x4d,0x20,0xed,0xaa,0xe0,0xef,0xff,0xff]
+          vpaddsw -4128(%rdx), %ymm22, %ymm29
+
+// CHECK: vpaddusb %xmm26, %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0x81,0x6d,0x00,0xdc,0xe2]
+          vpaddusb %xmm26, %xmm18, %xmm20
+
+// CHECK: vpaddusb %xmm26, %xmm18, %xmm20 {%k6}
+// CHECK:  encoding: [0x62,0x81,0x6d,0x06,0xdc,0xe2]
+          vpaddusb %xmm26, %xmm18, %xmm20 {%k6}
+
+// CHECK: vpaddusb %xmm26, %xmm18, %xmm20 {%k6} {z}
+// CHECK:  encoding: [0x62,0x81,0x6d,0x86,0xdc,0xe2]
+          vpaddusb %xmm26, %xmm18, %xmm20 {%k6} {z}
+
+// CHECK: vpaddusb (%rcx), %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x6d,0x00,0xdc,0x21]
+          vpaddusb (%rcx), %xmm18, %xmm20
+
+// CHECK: vpaddusb 4660(%rax,%r14,8), %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0x6d,0x00,0xdc,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vpaddusb 4660(%rax,%r14,8), %xmm18, %xmm20
+
+// CHECK: vpaddusb 2032(%rdx), %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x6d,0x00,0xdc,0x62,0x7f]
+          vpaddusb 2032(%rdx), %xmm18, %xmm20
+
+// CHECK: vpaddusb 2048(%rdx), %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x6d,0x00,0xdc,0xa2,0x00,0x08,0x00,0x00]
+          vpaddusb 2048(%rdx), %xmm18, %xmm20
+
+// CHECK: vpaddusb -2048(%rdx), %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x6d,0x00,0xdc,0x62,0x80]
+          vpaddusb -2048(%rdx), %xmm18, %xmm20
+
+// CHECK: vpaddusb -2064(%rdx), %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x6d,0x00,0xdc,0xa2,0xf0,0xf7,0xff,0xff]
+          vpaddusb -2064(%rdx), %xmm18, %xmm20
+
+// CHECK: vpaddusb %ymm24, %ymm26, %ymm25
+// CHECK:  encoding: [0x62,0x01,0x2d,0x20,0xdc,0xc8]
+          vpaddusb %ymm24, %ymm26, %ymm25
+
+// CHECK: vpaddusb %ymm24, %ymm26, %ymm25 {%k3}
+// CHECK:  encoding: [0x62,0x01,0x2d,0x23,0xdc,0xc8]
+          vpaddusb %ymm24, %ymm26, %ymm25 {%k3}
+
+// CHECK: vpaddusb %ymm24, %ymm26, %ymm25 {%k3} {z}
+// CHECK:  encoding: [0x62,0x01,0x2d,0xa3,0xdc,0xc8]
+          vpaddusb %ymm24, %ymm26, %ymm25 {%k3} {z}
+
+// CHECK: vpaddusb (%rcx), %ymm26, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x2d,0x20,0xdc,0x09]
+          vpaddusb (%rcx), %ymm26, %ymm25
+
+// CHECK: vpaddusb 4660(%rax,%r14,8), %ymm26, %ymm25
+// CHECK:  encoding: [0x62,0x21,0x2d,0x20,0xdc,0x8c,0xf0,0x34,0x12,0x00,0x00]
+          vpaddusb 4660(%rax,%r14,8), %ymm26, %ymm25
+
+// CHECK: vpaddusb 4064(%rdx), %ymm26, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x2d,0x20,0xdc,0x4a,0x7f]
+          vpaddusb 4064(%rdx), %ymm26, %ymm25
+
+// CHECK: vpaddusb 4096(%rdx), %ymm26, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x2d,0x20,0xdc,0x8a,0x00,0x10,0x00,0x00]
+          vpaddusb 4096(%rdx), %ymm26, %ymm25
+
+// CHECK: vpaddusb -4096(%rdx), %ymm26, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x2d,0x20,0xdc,0x4a,0x80]
+          vpaddusb -4096(%rdx), %ymm26, %ymm25
+
+// CHECK: vpaddusb -4128(%rdx), %ymm26, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x2d,0x20,0xdc,0x8a,0xe0,0xef,0xff,0xff]
+          vpaddusb -4128(%rdx), %ymm26, %ymm25
+
+// CHECK: vpaddusw %xmm24, %xmm29, %xmm28
+// CHECK:  encoding: [0x62,0x01,0x15,0x00,0xdd,0xe0]
+          vpaddusw %xmm24, %xmm29, %xmm28
+
+// CHECK: vpaddusw %xmm24, %xmm29, %xmm28 {%k4}
+// CHECK:  encoding: [0x62,0x01,0x15,0x04,0xdd,0xe0]
+          vpaddusw %xmm24, %xmm29, %xmm28 {%k4}
+
+// CHECK: vpaddusw %xmm24, %xmm29, %xmm28 {%k4} {z}
+// CHECK:  encoding: [0x62,0x01,0x15,0x84,0xdd,0xe0]
+          vpaddusw %xmm24, %xmm29, %xmm28 {%k4} {z}
+
+// CHECK: vpaddusw (%rcx), %xmm29, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x15,0x00,0xdd,0x21]
+          vpaddusw (%rcx), %xmm29, %xmm28
+
+// CHECK: vpaddusw 4660(%rax,%r14,8), %xmm29, %xmm28
+// CHECK:  encoding: [0x62,0x21,0x15,0x00,0xdd,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vpaddusw 4660(%rax,%r14,8), %xmm29, %xmm28
+
+// CHECK: vpaddusw 2032(%rdx), %xmm29, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x15,0x00,0xdd,0x62,0x7f]
+          vpaddusw 2032(%rdx), %xmm29, %xmm28
+
+// CHECK: vpaddusw 2048(%rdx), %xmm29, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x15,0x00,0xdd,0xa2,0x00,0x08,0x00,0x00]
+          vpaddusw 2048(%rdx), %xmm29, %xmm28
+
+// CHECK: vpaddusw -2048(%rdx), %xmm29, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x15,0x00,0xdd,0x62,0x80]
+          vpaddusw -2048(%rdx), %xmm29, %xmm28
+
+// CHECK: vpaddusw -2064(%rdx), %xmm29, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x15,0x00,0xdd,0xa2,0xf0,0xf7,0xff,0xff]
+          vpaddusw -2064(%rdx), %xmm29, %xmm28
+
+// CHECK: vpaddusw %ymm22, %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x21,0x2d,0x20,0xdd,0xde]
+          vpaddusw %ymm22, %ymm26, %ymm27
+
+// CHECK: vpaddusw %ymm22, %ymm26, %ymm27 {%k3}
+// CHECK:  encoding: [0x62,0x21,0x2d,0x23,0xdd,0xde]
+          vpaddusw %ymm22, %ymm26, %ymm27 {%k3}
+
+// CHECK: vpaddusw %ymm22, %ymm26, %ymm27 {%k3} {z}
+// CHECK:  encoding: [0x62,0x21,0x2d,0xa3,0xdd,0xde]
+          vpaddusw %ymm22, %ymm26, %ymm27 {%k3} {z}
+
+// CHECK: vpaddusw (%rcx), %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x2d,0x20,0xdd,0x19]
+          vpaddusw (%rcx), %ymm26, %ymm27
+
+// CHECK: vpaddusw 4660(%rax,%r14,8), %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x21,0x2d,0x20,0xdd,0x9c,0xf0,0x34,0x12,0x00,0x00]
+          vpaddusw 4660(%rax,%r14,8), %ymm26, %ymm27
+
+// CHECK: vpaddusw 4064(%rdx), %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x2d,0x20,0xdd,0x5a,0x7f]
+          vpaddusw 4064(%rdx), %ymm26, %ymm27
+
+// CHECK: vpaddusw 4096(%rdx), %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x2d,0x20,0xdd,0x9a,0x00,0x10,0x00,0x00]
+          vpaddusw 4096(%rdx), %ymm26, %ymm27
+
+// CHECK: vpaddusw -4096(%rdx), %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x2d,0x20,0xdd,0x5a,0x80]
+          vpaddusw -4096(%rdx), %ymm26, %ymm27
+
+// CHECK: vpaddusw -4128(%rdx), %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x2d,0x20,0xdd,0x9a,0xe0,0xef,0xff,0xff]
+          vpaddusw -4128(%rdx), %ymm26, %ymm27
+
+// CHECK: vpsubsb %xmm18, %xmm22, %xmm23
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x00,0xe8,0xfa]
+          vpsubsb %xmm18, %xmm22, %xmm23
+
+// CHECK: vpsubsb %xmm18, %xmm22, %xmm23 {%k5}
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x05,0xe8,0xfa]
+          vpsubsb %xmm18, %xmm22, %xmm23 {%k5}
+
+// CHECK: vpsubsb %xmm18, %xmm22, %xmm23 {%k5} {z}
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x85,0xe8,0xfa]
+          vpsubsb %xmm18, %xmm22, %xmm23 {%k5} {z}
+
+// CHECK: vpsubsb (%rcx), %xmm22, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x00,0xe8,0x39]
+          vpsubsb (%rcx), %xmm22, %xmm23
+
+// CHECK: vpsubsb 4660(%rax,%r14,8), %xmm22, %xmm23
+// CHECK:  encoding: [0x62,0xa1,0x4d,0x00,0xe8,0xbc,0xf0,0x34,0x12,0x00,0x00]
+          vpsubsb 4660(%rax,%r14,8), %xmm22, %xmm23
+
+// CHECK: vpsubsb 2032(%rdx), %xmm22, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x00,0xe8,0x7a,0x7f]
+          vpsubsb 2032(%rdx), %xmm22, %xmm23
+
+// CHECK: vpsubsb 2048(%rdx), %xmm22, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x00,0xe8,0xba,0x00,0x08,0x00,0x00]
+          vpsubsb 2048(%rdx), %xmm22, %xmm23
+
+// CHECK: vpsubsb -2048(%rdx), %xmm22, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x00,0xe8,0x7a,0x80]
+          vpsubsb -2048(%rdx), %xmm22, %xmm23
+
+// CHECK: vpsubsb -2064(%rdx), %xmm22, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x4d,0x00,0xe8,0xba,0xf0,0xf7,0xff,0xff]
+          vpsubsb -2064(%rdx), %xmm22, %xmm23
+
+// CHECK: vpsubsb %ymm24, %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x01,0x55,0x20,0xe8,0xe0]
+          vpsubsb %ymm24, %ymm21, %ymm28
+
+// CHECK: vpsubsb %ymm24, %ymm21, %ymm28 {%k5}
+// CHECK:  encoding: [0x62,0x01,0x55,0x25,0xe8,0xe0]
+          vpsubsb %ymm24, %ymm21, %ymm28 {%k5}
+
+// CHECK: vpsubsb %ymm24, %ymm21, %ymm28 {%k5} {z}
+// CHECK:  encoding: [0x62,0x01,0x55,0xa5,0xe8,0xe0]
+          vpsubsb %ymm24, %ymm21, %ymm28 {%k5} {z}
+
+// CHECK: vpsubsb (%rcx), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x55,0x20,0xe8,0x21]
+          vpsubsb (%rcx), %ymm21, %ymm28
+
+// CHECK: vpsubsb 4660(%rax,%r14,8), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x21,0x55,0x20,0xe8,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vpsubsb 4660(%rax,%r14,8), %ymm21, %ymm28
+
+// CHECK: vpsubsb 4064(%rdx), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x55,0x20,0xe8,0x62,0x7f]
+          vpsubsb 4064(%rdx), %ymm21, %ymm28
+
+// CHECK: vpsubsb 4096(%rdx), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x55,0x20,0xe8,0xa2,0x00,0x10,0x00,0x00]
+          vpsubsb 4096(%rdx), %ymm21, %ymm28
+
+// CHECK: vpsubsb -4096(%rdx), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x55,0x20,0xe8,0x62,0x80]
+          vpsubsb -4096(%rdx), %ymm21, %ymm28
+
+// CHECK: vpsubsb -4128(%rdx), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x55,0x20,0xe8,0xa2,0xe0,0xef,0xff,0xff]
+          vpsubsb -4128(%rdx), %ymm21, %ymm28
+
+// CHECK: vpsubsw %xmm18, %xmm27, %xmm19
+// CHECK:  encoding: [0x62,0xa1,0x25,0x00,0xe9,0xda]
+          vpsubsw %xmm18, %xmm27, %xmm19
+
+// CHECK: vpsubsw %xmm18, %xmm27, %xmm19 {%k4}
+// CHECK:  encoding: [0x62,0xa1,0x25,0x04,0xe9,0xda]
+          vpsubsw %xmm18, %xmm27, %xmm19 {%k4}
+
+// CHECK: vpsubsw %xmm18, %xmm27, %xmm19 {%k4} {z}
+// CHECK:  encoding: [0x62,0xa1,0x25,0x84,0xe9,0xda]
+          vpsubsw %xmm18, %xmm27, %xmm19 {%k4} {z}
+
+// CHECK: vpsubsw (%rcx), %xmm27, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xe9,0x19]
+          vpsubsw (%rcx), %xmm27, %xmm19
+
+// CHECK: vpsubsw 4660(%rax,%r14,8), %xmm27, %xmm19
+// CHECK:  encoding: [0x62,0xa1,0x25,0x00,0xe9,0x9c,0xf0,0x34,0x12,0x00,0x00]
+          vpsubsw 4660(%rax,%r14,8), %xmm27, %xmm19
+
+// CHECK: vpsubsw 2032(%rdx), %xmm27, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xe9,0x5a,0x7f]
+          vpsubsw 2032(%rdx), %xmm27, %xmm19
+
+// CHECK: vpsubsw 2048(%rdx), %xmm27, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xe9,0x9a,0x00,0x08,0x00,0x00]
+          vpsubsw 2048(%rdx), %xmm27, %xmm19
+
+// CHECK: vpsubsw -2048(%rdx), %xmm27, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xe9,0x5a,0x80]
+          vpsubsw -2048(%rdx), %xmm27, %xmm19
+
+// CHECK: vpsubsw -2064(%rdx), %xmm27, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xe9,0x9a,0xf0,0xf7,0xff,0xff]
+          vpsubsw -2064(%rdx), %xmm27, %xmm19
+
+// CHECK: vpsubsw %ymm25, %ymm29, %ymm18
+// CHECK:  encoding: [0x62,0x81,0x15,0x20,0xe9,0xd1]
+          vpsubsw %ymm25, %ymm29, %ymm18
+
+// CHECK: vpsubsw %ymm25, %ymm29, %ymm18 {%k5}
+// CHECK:  encoding: [0x62,0x81,0x15,0x25,0xe9,0xd1]
+          vpsubsw %ymm25, %ymm29, %ymm18 {%k5}
+
+// CHECK: vpsubsw %ymm25, %ymm29, %ymm18 {%k5} {z}
+// CHECK:  encoding: [0x62,0x81,0x15,0xa5,0xe9,0xd1]
+          vpsubsw %ymm25, %ymm29, %ymm18 {%k5} {z}
+
+// CHECK: vpsubsw (%rcx), %ymm29, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x15,0x20,0xe9,0x11]
+          vpsubsw (%rcx), %ymm29, %ymm18
+
+// CHECK: vpsubsw 4660(%rax,%r14,8), %ymm29, %ymm18
+// CHECK:  encoding: [0x62,0xa1,0x15,0x20,0xe9,0x94,0xf0,0x34,0x12,0x00,0x00]
+          vpsubsw 4660(%rax,%r14,8), %ymm29, %ymm18
+
+// CHECK: vpsubsw 4064(%rdx), %ymm29, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x15,0x20,0xe9,0x52,0x7f]
+          vpsubsw 4064(%rdx), %ymm29, %ymm18
+
+// CHECK: vpsubsw 4096(%rdx), %ymm29, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x15,0x20,0xe9,0x92,0x00,0x10,0x00,0x00]
+          vpsubsw 4096(%rdx), %ymm29, %ymm18
+
+// CHECK: vpsubsw -4096(%rdx), %ymm29, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x15,0x20,0xe9,0x52,0x80]
+          vpsubsw -4096(%rdx), %ymm29, %ymm18
+
+// CHECK: vpsubsw -4128(%rdx), %ymm29, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x15,0x20,0xe9,0x92,0xe0,0xef,0xff,0xff]
+          vpsubsw -4128(%rdx), %ymm29, %ymm18
+
+// CHECK: vpsubusb %xmm23, %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0x2d,0x00,0xd8,0xe7]
+          vpsubusb %xmm23, %xmm26, %xmm20
+
+// CHECK: vpsubusb %xmm23, %xmm26, %xmm20 {%k5}
+// CHECK:  encoding: [0x62,0xa1,0x2d,0x05,0xd8,0xe7]
+          vpsubusb %xmm23, %xmm26, %xmm20 {%k5}
+
+// CHECK: vpsubusb %xmm23, %xmm26, %xmm20 {%k5} {z}
+// CHECK:  encoding: [0x62,0xa1,0x2d,0x85,0xd8,0xe7]
+          vpsubusb %xmm23, %xmm26, %xmm20 {%k5} {z}
+
+// CHECK: vpsubusb (%rcx), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x00,0xd8,0x21]
+          vpsubusb (%rcx), %xmm26, %xmm20
+
+// CHECK: vpsubusb 4660(%rax,%r14,8), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0x2d,0x00,0xd8,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vpsubusb 4660(%rax,%r14,8), %xmm26, %xmm20
+
+// CHECK: vpsubusb 2032(%rdx), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x00,0xd8,0x62,0x7f]
+          vpsubusb 2032(%rdx), %xmm26, %xmm20
+
+// CHECK: vpsubusb 2048(%rdx), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x00,0xd8,0xa2,0x00,0x08,0x00,0x00]
+          vpsubusb 2048(%rdx), %xmm26, %xmm20
+
+// CHECK: vpsubusb -2048(%rdx), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x00,0xd8,0x62,0x80]
+          vpsubusb -2048(%rdx), %xmm26, %xmm20
+
+// CHECK: vpsubusb -2064(%rdx), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x00,0xd8,0xa2,0xf0,0xf7,0xff,0xff]
+          vpsubusb -2064(%rdx), %xmm26, %xmm20
+
+// CHECK: vpsubusb %ymm19, %ymm28, %ymm30
+// CHECK:  encoding: [0x62,0x21,0x1d,0x20,0xd8,0xf3]
+          vpsubusb %ymm19, %ymm28, %ymm30
+
+// CHECK: vpsubusb %ymm19, %ymm28, %ymm30 {%k3}
+// CHECK:  encoding: [0x62,0x21,0x1d,0x23,0xd8,0xf3]
+          vpsubusb %ymm19, %ymm28, %ymm30 {%k3}
+
+// CHECK: vpsubusb %ymm19, %ymm28, %ymm30 {%k3} {z}
+// CHECK:  encoding: [0x62,0x21,0x1d,0xa3,0xd8,0xf3]
+          vpsubusb %ymm19, %ymm28, %ymm30 {%k3} {z}
+
+// CHECK: vpsubusb (%rcx), %ymm28, %ymm30
+// CHECK:  encoding: [0x62,0x61,0x1d,0x20,0xd8,0x31]
+          vpsubusb (%rcx), %ymm28, %ymm30
+
+// CHECK: vpsubusb 4660(%rax,%r14,8), %ymm28, %ymm30
+// CHECK:  encoding: [0x62,0x21,0x1d,0x20,0xd8,0xb4,0xf0,0x34,0x12,0x00,0x00]
+          vpsubusb 4660(%rax,%r14,8), %ymm28, %ymm30
+
+// CHECK: vpsubusb 4064(%rdx), %ymm28, %ymm30
+// CHECK:  encoding: [0x62,0x61,0x1d,0x20,0xd8,0x72,0x7f]
+          vpsubusb 4064(%rdx), %ymm28, %ymm30
+
+// CHECK: vpsubusb 4096(%rdx), %ymm28, %ymm30
+// CHECK:  encoding: [0x62,0x61,0x1d,0x20,0xd8,0xb2,0x00,0x10,0x00,0x00]
+          vpsubusb 4096(%rdx), %ymm28, %ymm30
+
+// CHECK: vpsubusb -4096(%rdx), %ymm28, %ymm30
+// CHECK:  encoding: [0x62,0x61,0x1d,0x20,0xd8,0x72,0x80]
+          vpsubusb -4096(%rdx), %ymm28, %ymm30
+
+// CHECK: vpsubusb -4128(%rdx), %ymm28, %ymm30
+// CHECK:  encoding: [0x62,0x61,0x1d,0x20,0xd8,0xb2,0xe0,0xef,0xff,0xff]
+          vpsubusb -4128(%rdx), %ymm28, %ymm30
+
+// CHECK: vpsubusw %xmm21, %xmm23, %xmm26
+// CHECK:  encoding: [0x62,0x21,0x45,0x00,0xd9,0xd5]
+          vpsubusw %xmm21, %xmm23, %xmm26
+
+// CHECK: vpsubusw %xmm21, %xmm23, %xmm26 {%k6}
+// CHECK:  encoding: [0x62,0x21,0x45,0x06,0xd9,0xd5]
+          vpsubusw %xmm21, %xmm23, %xmm26 {%k6}
+
+// CHECK: vpsubusw %xmm21, %xmm23, %xmm26 {%k6} {z}
+// CHECK:  encoding: [0x62,0x21,0x45,0x86,0xd9,0xd5]
+          vpsubusw %xmm21, %xmm23, %xmm26 {%k6} {z}
+
+// CHECK: vpsubusw (%rcx), %xmm23, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x45,0x00,0xd9,0x11]
+          vpsubusw (%rcx), %xmm23, %xmm26
+
+// CHECK: vpsubusw 4660(%rax,%r14,8), %xmm23, %xmm26
+// CHECK:  encoding: [0x62,0x21,0x45,0x00,0xd9,0x94,0xf0,0x34,0x12,0x00,0x00]
+          vpsubusw 4660(%rax,%r14,8), %xmm23, %xmm26
+
+// CHECK: vpsubusw 2032(%rdx), %xmm23, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x45,0x00,0xd9,0x52,0x7f]
+          vpsubusw 2032(%rdx), %xmm23, %xmm26
+
+// CHECK: vpsubusw 2048(%rdx), %xmm23, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x45,0x00,0xd9,0x92,0x00,0x08,0x00,0x00]
+          vpsubusw 2048(%rdx), %xmm23, %xmm26
+
+// CHECK: vpsubusw -2048(%rdx), %xmm23, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x45,0x00,0xd9,0x52,0x80]
+          vpsubusw -2048(%rdx), %xmm23, %xmm26
+
+// CHECK: vpsubusw -2064(%rdx), %xmm23, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x45,0x00,0xd9,0x92,0xf0,0xf7,0xff,0xff]
+          vpsubusw -2064(%rdx), %xmm23, %xmm26
+
+// CHECK: vpsubusw %ymm24, %ymm20, %ymm25
+// CHECK:  encoding: [0x62,0x01,0x5d,0x20,0xd9,0xc8]
+          vpsubusw %ymm24, %ymm20, %ymm25
+
+// CHECK: vpsubusw %ymm24, %ymm20, %ymm25 {%k1}
+// CHECK:  encoding: [0x62,0x01,0x5d,0x21,0xd9,0xc8]
+          vpsubusw %ymm24, %ymm20, %ymm25 {%k1}
+
+// CHECK: vpsubusw %ymm24, %ymm20, %ymm25 {%k1} {z}
+// CHECK:  encoding: [0x62,0x01,0x5d,0xa1,0xd9,0xc8]
+          vpsubusw %ymm24, %ymm20, %ymm25 {%k1} {z}
+
+// CHECK: vpsubusw (%rcx), %ymm20, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x5d,0x20,0xd9,0x09]
+          vpsubusw (%rcx), %ymm20, %ymm25
+
+// CHECK: vpsubusw 4660(%rax,%r14,8), %ymm20, %ymm25
+// CHECK:  encoding: [0x62,0x21,0x5d,0x20,0xd9,0x8c,0xf0,0x34,0x12,0x00,0x00]
+          vpsubusw 4660(%rax,%r14,8), %ymm20, %ymm25
+
+// CHECK: vpsubusw 4064(%rdx), %ymm20, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x5d,0x20,0xd9,0x4a,0x7f]
+          vpsubusw 4064(%rdx), %ymm20, %ymm25
+
+// CHECK: vpsubusw 4096(%rdx), %ymm20, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x5d,0x20,0xd9,0x8a,0x00,0x10,0x00,0x00]
+          vpsubusw 4096(%rdx), %ymm20, %ymm25
+
+// CHECK: vpsubusw -4096(%rdx), %ymm20, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x5d,0x20,0xd9,0x4a,0x80]
+          vpsubusw -4096(%rdx), %ymm20, %ymm25
+
+// CHECK: vpsubusw -4128(%rdx), %ymm20, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x5d,0x20,0xd9,0x8a,0xe0,0xef,0xff,0xff]
+          vpsubusw -4128(%rdx), %ymm20, %ymm25
+
+// CHECK: vpaddsb %xmm25, %xmm19, %xmm30
+// CHECK:  encoding: [0x62,0x01,0x65,0x00,0xec,0xf1]
+          vpaddsb %xmm25, %xmm19, %xmm30
+
+// CHECK: vpaddsb %xmm25, %xmm19, %xmm30 {%k6}
+// CHECK:  encoding: [0x62,0x01,0x65,0x06,0xec,0xf1]
+          vpaddsb %xmm25, %xmm19, %xmm30 {%k6}
+
+// CHECK: vpaddsb %xmm25, %xmm19, %xmm30 {%k6} {z}
+// CHECK:  encoding: [0x62,0x01,0x65,0x86,0xec,0xf1]
+          vpaddsb %xmm25, %xmm19, %xmm30 {%k6} {z}
+
+// CHECK: vpaddsb (%rcx), %xmm19, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x65,0x00,0xec,0x31]
+          vpaddsb (%rcx), %xmm19, %xmm30
+
+// CHECK: vpaddsb 291(%rax,%r14,8), %xmm19, %xmm30
+// CHECK:  encoding: [0x62,0x21,0x65,0x00,0xec,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpaddsb 291(%rax,%r14,8), %xmm19, %xmm30
+
+// CHECK: vpaddsb 2032(%rdx), %xmm19, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x65,0x00,0xec,0x72,0x7f]
+          vpaddsb 2032(%rdx), %xmm19, %xmm30
+
+// CHECK: vpaddsb 2048(%rdx), %xmm19, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x65,0x00,0xec,0xb2,0x00,0x08,0x00,0x00]
+          vpaddsb 2048(%rdx), %xmm19, %xmm30
+
+// CHECK: vpaddsb -2048(%rdx), %xmm19, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x65,0x00,0xec,0x72,0x80]
+          vpaddsb -2048(%rdx), %xmm19, %xmm30
+
+// CHECK: vpaddsb -2064(%rdx), %xmm19, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x65,0x00,0xec,0xb2,0xf0,0xf7,0xff,0xff]
+          vpaddsb -2064(%rdx), %xmm19, %xmm30
+
+// CHECK: vpaddsb %ymm28, %ymm29, %ymm22
+// CHECK:  encoding: [0x62,0x81,0x15,0x20,0xec,0xf4]
+          vpaddsb %ymm28, %ymm29, %ymm22
+
+// CHECK: vpaddsb %ymm28, %ymm29, %ymm22 {%k4}
+// CHECK:  encoding: [0x62,0x81,0x15,0x24,0xec,0xf4]
+          vpaddsb %ymm28, %ymm29, %ymm22 {%k4}
+
+// CHECK: vpaddsb %ymm28, %ymm29, %ymm22 {%k4} {z}
+// CHECK:  encoding: [0x62,0x81,0x15,0xa4,0xec,0xf4]
+          vpaddsb %ymm28, %ymm29, %ymm22 {%k4} {z}
+
+// CHECK: vpaddsb (%rcx), %ymm29, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x15,0x20,0xec,0x31]
+          vpaddsb (%rcx), %ymm29, %ymm22
+
+// CHECK: vpaddsb 291(%rax,%r14,8), %ymm29, %ymm22
+// CHECK:  encoding: [0x62,0xa1,0x15,0x20,0xec,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpaddsb 291(%rax,%r14,8), %ymm29, %ymm22
+
+// CHECK: vpaddsb 4064(%rdx), %ymm29, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x15,0x20,0xec,0x72,0x7f]
+          vpaddsb 4064(%rdx), %ymm29, %ymm22
+
+// CHECK: vpaddsb 4096(%rdx), %ymm29, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x15,0x20,0xec,0xb2,0x00,0x10,0x00,0x00]
+          vpaddsb 4096(%rdx), %ymm29, %ymm22
+
+// CHECK: vpaddsb -4096(%rdx), %ymm29, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x15,0x20,0xec,0x72,0x80]
+          vpaddsb -4096(%rdx), %ymm29, %ymm22
+
+// CHECK: vpaddsb -4128(%rdx), %ymm29, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x15,0x20,0xec,0xb2,0xe0,0xef,0xff,0xff]
+          vpaddsb -4128(%rdx), %ymm29, %ymm22
+
+// CHECK: vpaddsw %xmm19, %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0x65,0x00,0xed,0xe3]
+          vpaddsw %xmm19, %xmm19, %xmm20
+
+// CHECK: vpaddsw %xmm19, %xmm19, %xmm20 {%k7}
+// CHECK:  encoding: [0x62,0xa1,0x65,0x07,0xed,0xe3]
+          vpaddsw %xmm19, %xmm19, %xmm20 {%k7}
+
+// CHECK: vpaddsw %xmm19, %xmm19, %xmm20 {%k7} {z}
+// CHECK:  encoding: [0x62,0xa1,0x65,0x87,0xed,0xe3]
+          vpaddsw %xmm19, %xmm19, %xmm20 {%k7} {z}
+
+// CHECK: vpaddsw (%rcx), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x65,0x00,0xed,0x21]
+          vpaddsw (%rcx), %xmm19, %xmm20
+
+// CHECK: vpaddsw 291(%rax,%r14,8), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0x65,0x00,0xed,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpaddsw 291(%rax,%r14,8), %xmm19, %xmm20
+
+// CHECK: vpaddsw 2032(%rdx), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x65,0x00,0xed,0x62,0x7f]
+          vpaddsw 2032(%rdx), %xmm19, %xmm20
+
+// CHECK: vpaddsw 2048(%rdx), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x65,0x00,0xed,0xa2,0x00,0x08,0x00,0x00]
+          vpaddsw 2048(%rdx), %xmm19, %xmm20
+
+// CHECK: vpaddsw -2048(%rdx), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x65,0x00,0xed,0x62,0x80]
+          vpaddsw -2048(%rdx), %xmm19, %xmm20
+
+// CHECK: vpaddsw -2064(%rdx), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x65,0x00,0xed,0xa2,0xf0,0xf7,0xff,0xff]
+          vpaddsw -2064(%rdx), %xmm19, %xmm20
+
+// CHECK: vpaddsw %ymm19, %ymm27, %ymm20
+// CHECK:  encoding: [0x62,0xa1,0x25,0x20,0xed,0xe3]
+          vpaddsw %ymm19, %ymm27, %ymm20
+
+// CHECK: vpaddsw %ymm19, %ymm27, %ymm20 {%k3}
+// CHECK:  encoding: [0x62,0xa1,0x25,0x23,0xed,0xe3]
+          vpaddsw %ymm19, %ymm27, %ymm20 {%k3}
+
+// CHECK: vpaddsw %ymm19, %ymm27, %ymm20 {%k3} {z}
+// CHECK:  encoding: [0x62,0xa1,0x25,0xa3,0xed,0xe3]
+          vpaddsw %ymm19, %ymm27, %ymm20 {%k3} {z}
+
+// CHECK: vpaddsw (%rcx), %ymm27, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x25,0x20,0xed,0x21]
+          vpaddsw (%rcx), %ymm27, %ymm20
+
+// CHECK: vpaddsw 291(%rax,%r14,8), %ymm27, %ymm20
+// CHECK:  encoding: [0x62,0xa1,0x25,0x20,0xed,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpaddsw 291(%rax,%r14,8), %ymm27, %ymm20
+
+// CHECK: vpaddsw 4064(%rdx), %ymm27, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x25,0x20,0xed,0x62,0x7f]
+          vpaddsw 4064(%rdx), %ymm27, %ymm20
+
+// CHECK: vpaddsw 4096(%rdx), %ymm27, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x25,0x20,0xed,0xa2,0x00,0x10,0x00,0x00]
+          vpaddsw 4096(%rdx), %ymm27, %ymm20
+
+// CHECK: vpaddsw -4096(%rdx), %ymm27, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x25,0x20,0xed,0x62,0x80]
+          vpaddsw -4096(%rdx), %ymm27, %ymm20
+
+// CHECK: vpaddsw -4128(%rdx), %ymm27, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x25,0x20,0xed,0xa2,0xe0,0xef,0xff,0xff]
+          vpaddsw -4128(%rdx), %ymm27, %ymm20
+
+// CHECK: vpaddusb %xmm19, %xmm21, %xmm25
+// CHECK:  encoding: [0x62,0x21,0x55,0x00,0xdc,0xcb]
+          vpaddusb %xmm19, %xmm21, %xmm25
+
+// CHECK: vpaddusb %xmm19, %xmm21, %xmm25 {%k7}
+// CHECK:  encoding: [0x62,0x21,0x55,0x07,0xdc,0xcb]
+          vpaddusb %xmm19, %xmm21, %xmm25 {%k7}
+
+// CHECK: vpaddusb %xmm19, %xmm21, %xmm25 {%k7} {z}
+// CHECK:  encoding: [0x62,0x21,0x55,0x87,0xdc,0xcb]
+          vpaddusb %xmm19, %xmm21, %xmm25 {%k7} {z}
+
+// CHECK: vpaddusb (%rcx), %xmm21, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x55,0x00,0xdc,0x09]
+          vpaddusb (%rcx), %xmm21, %xmm25
+
+// CHECK: vpaddusb 291(%rax,%r14,8), %xmm21, %xmm25
+// CHECK:  encoding: [0x62,0x21,0x55,0x00,0xdc,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpaddusb 291(%rax,%r14,8), %xmm21, %xmm25
+
+// CHECK: vpaddusb 2032(%rdx), %xmm21, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x55,0x00,0xdc,0x4a,0x7f]
+          vpaddusb 2032(%rdx), %xmm21, %xmm25
+
+// CHECK: vpaddusb 2048(%rdx), %xmm21, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x55,0x00,0xdc,0x8a,0x00,0x08,0x00,0x00]
+          vpaddusb 2048(%rdx), %xmm21, %xmm25
+
+// CHECK: vpaddusb -2048(%rdx), %xmm21, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x55,0x00,0xdc,0x4a,0x80]
+          vpaddusb -2048(%rdx), %xmm21, %xmm25
+
+// CHECK: vpaddusb -2064(%rdx), %xmm21, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x55,0x00,0xdc,0x8a,0xf0,0xf7,0xff,0xff]
+          vpaddusb -2064(%rdx), %xmm21, %xmm25
+
+// CHECK: vpaddusb %ymm25, %ymm21, %ymm21
+// CHECK:  encoding: [0x62,0x81,0x55,0x20,0xdc,0xe9]
+          vpaddusb %ymm25, %ymm21, %ymm21
+
+// CHECK: vpaddusb %ymm25, %ymm21, %ymm21 {%k1}
+// CHECK:  encoding: [0x62,0x81,0x55,0x21,0xdc,0xe9]
+          vpaddusb %ymm25, %ymm21, %ymm21 {%k1}
+
+// CHECK: vpaddusb %ymm25, %ymm21, %ymm21 {%k1} {z}
+// CHECK:  encoding: [0x62,0x81,0x55,0xa1,0xdc,0xe9]
+          vpaddusb %ymm25, %ymm21, %ymm21 {%k1} {z}
+
+// CHECK: vpaddusb (%rcx), %ymm21, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xdc,0x29]
+          vpaddusb (%rcx), %ymm21, %ymm21
+
+// CHECK: vpaddusb 291(%rax,%r14,8), %ymm21, %ymm21
+// CHECK:  encoding: [0x62,0xa1,0x55,0x20,0xdc,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpaddusb 291(%rax,%r14,8), %ymm21, %ymm21
+
+// CHECK: vpaddusb 4064(%rdx), %ymm21, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xdc,0x6a,0x7f]
+          vpaddusb 4064(%rdx), %ymm21, %ymm21
+
+// CHECK: vpaddusb 4096(%rdx), %ymm21, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xdc,0xaa,0x00,0x10,0x00,0x00]
+          vpaddusb 4096(%rdx), %ymm21, %ymm21
+
+// CHECK: vpaddusb -4096(%rdx), %ymm21, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xdc,0x6a,0x80]
+          vpaddusb -4096(%rdx), %ymm21, %ymm21
+
+// CHECK: vpaddusb -4128(%rdx), %ymm21, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x55,0x20,0xdc,0xaa,0xe0,0xef,0xff,0xff]
+          vpaddusb -4128(%rdx), %ymm21, %ymm21
+
+// CHECK: vpaddusw %xmm26, %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x01,0x75,0x00,0xdd,0xc2]
+          vpaddusw %xmm26, %xmm17, %xmm24
+
+// CHECK: vpaddusw %xmm26, %xmm17, %xmm24 {%k6}
+// CHECK:  encoding: [0x62,0x01,0x75,0x06,0xdd,0xc2]
+          vpaddusw %xmm26, %xmm17, %xmm24 {%k6}
+
+// CHECK: vpaddusw %xmm26, %xmm17, %xmm24 {%k6} {z}
+// CHECK:  encoding: [0x62,0x01,0x75,0x86,0xdd,0xc2]
+          vpaddusw %xmm26, %xmm17, %xmm24 {%k6} {z}
+
+// CHECK: vpaddusw (%rcx), %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x61,0x75,0x00,0xdd,0x01]
+          vpaddusw (%rcx), %xmm17, %xmm24
+
+// CHECK: vpaddusw 291(%rax,%r14,8), %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x21,0x75,0x00,0xdd,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vpaddusw 291(%rax,%r14,8), %xmm17, %xmm24
+
+// CHECK: vpaddusw 2032(%rdx), %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x61,0x75,0x00,0xdd,0x42,0x7f]
+          vpaddusw 2032(%rdx), %xmm17, %xmm24
+
+// CHECK: vpaddusw 2048(%rdx), %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x61,0x75,0x00,0xdd,0x82,0x00,0x08,0x00,0x00]
+          vpaddusw 2048(%rdx), %xmm17, %xmm24
+
+// CHECK: vpaddusw -2048(%rdx), %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x61,0x75,0x00,0xdd,0x42,0x80]
+          vpaddusw -2048(%rdx), %xmm17, %xmm24
+
+// CHECK: vpaddusw -2064(%rdx), %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x61,0x75,0x00,0xdd,0x82,0xf0,0xf7,0xff,0xff]
+          vpaddusw -2064(%rdx), %xmm17, %xmm24
+
+// CHECK: vpaddusw %ymm22, %ymm27, %ymm22
+// CHECK:  encoding: [0x62,0xa1,0x25,0x20,0xdd,0xf6]
+          vpaddusw %ymm22, %ymm27, %ymm22
+
+// CHECK: vpaddusw %ymm22, %ymm27, %ymm22 {%k5}
+// CHECK:  encoding: [0x62,0xa1,0x25,0x25,0xdd,0xf6]
+          vpaddusw %ymm22, %ymm27, %ymm22 {%k5}
+
+// CHECK: vpaddusw %ymm22, %ymm27, %ymm22 {%k5} {z}
+// CHECK:  encoding: [0x62,0xa1,0x25,0xa5,0xdd,0xf6]
+          vpaddusw %ymm22, %ymm27, %ymm22 {%k5} {z}
+
+// CHECK: vpaddusw (%rcx), %ymm27, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x25,0x20,0xdd,0x31]
+          vpaddusw (%rcx), %ymm27, %ymm22
+
+// CHECK: vpaddusw 291(%rax,%r14,8), %ymm27, %ymm22
+// CHECK:  encoding: [0x62,0xa1,0x25,0x20,0xdd,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpaddusw 291(%rax,%r14,8), %ymm27, %ymm22
+
+// CHECK: vpaddusw 4064(%rdx), %ymm27, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x25,0x20,0xdd,0x72,0x7f]
+          vpaddusw 4064(%rdx), %ymm27, %ymm22
+
+// CHECK: vpaddusw 4096(%rdx), %ymm27, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x25,0x20,0xdd,0xb2,0x00,0x10,0x00,0x00]
+          vpaddusw 4096(%rdx), %ymm27, %ymm22
+
+// CHECK: vpaddusw -4096(%rdx), %ymm27, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x25,0x20,0xdd,0x72,0x80]
+          vpaddusw -4096(%rdx), %ymm27, %ymm22
+
+// CHECK: vpaddusw -4128(%rdx), %ymm27, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x25,0x20,0xdd,0xb2,0xe0,0xef,0xff,0xff]
+          vpaddusw -4128(%rdx), %ymm27, %ymm22
+
+// CHECK: vpsubsb %xmm19, %xmm19, %xmm28
+// CHECK:  encoding: [0x62,0x21,0x65,0x00,0xe8,0xe3]
+          vpsubsb %xmm19, %xmm19, %xmm28
+
+// CHECK: vpsubsb %xmm19, %xmm19, %xmm28 {%k4}
+// CHECK:  encoding: [0x62,0x21,0x65,0x04,0xe8,0xe3]
+          vpsubsb %xmm19, %xmm19, %xmm28 {%k4}
+
+// CHECK: vpsubsb %xmm19, %xmm19, %xmm28 {%k4} {z}
+// CHECK:  encoding: [0x62,0x21,0x65,0x84,0xe8,0xe3]
+          vpsubsb %xmm19, %xmm19, %xmm28 {%k4} {z}
+
+// CHECK: vpsubsb (%rcx), %xmm19, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x65,0x00,0xe8,0x21]
+          vpsubsb (%rcx), %xmm19, %xmm28
+
+// CHECK: vpsubsb 291(%rax,%r14,8), %xmm19, %xmm28
+// CHECK:  encoding: [0x62,0x21,0x65,0x00,0xe8,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsubsb 291(%rax,%r14,8), %xmm19, %xmm28
+
+// CHECK: vpsubsb 2032(%rdx), %xmm19, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x65,0x00,0xe8,0x62,0x7f]
+          vpsubsb 2032(%rdx), %xmm19, %xmm28
+
+// CHECK: vpsubsb 2048(%rdx), %xmm19, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x65,0x00,0xe8,0xa2,0x00,0x08,0x00,0x00]
+          vpsubsb 2048(%rdx), %xmm19, %xmm28
+
+// CHECK: vpsubsb -2048(%rdx), %xmm19, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x65,0x00,0xe8,0x62,0x80]
+          vpsubsb -2048(%rdx), %xmm19, %xmm28
+
+// CHECK: vpsubsb -2064(%rdx), %xmm19, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x65,0x00,0xe8,0xa2,0xf0,0xf7,0xff,0xff]
+          vpsubsb -2064(%rdx), %xmm19, %xmm28
+
+// CHECK: vpsubsb %ymm18, %ymm23, %ymm18
+// CHECK:  encoding: [0x62,0xa1,0x45,0x20,0xe8,0xd2]
+          vpsubsb %ymm18, %ymm23, %ymm18
+
+// CHECK: vpsubsb %ymm18, %ymm23, %ymm18 {%k6}
+// CHECK:  encoding: [0x62,0xa1,0x45,0x26,0xe8,0xd2]
+          vpsubsb %ymm18, %ymm23, %ymm18 {%k6}
+
+// CHECK: vpsubsb %ymm18, %ymm23, %ymm18 {%k6} {z}
+// CHECK:  encoding: [0x62,0xa1,0x45,0xa6,0xe8,0xd2]
+          vpsubsb %ymm18, %ymm23, %ymm18 {%k6} {z}
+
+// CHECK: vpsubsb (%rcx), %ymm23, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x45,0x20,0xe8,0x11]
+          vpsubsb (%rcx), %ymm23, %ymm18
+
+// CHECK: vpsubsb 291(%rax,%r14,8), %ymm23, %ymm18
+// CHECK:  encoding: [0x62,0xa1,0x45,0x20,0xe8,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vpsubsb 291(%rax,%r14,8), %ymm23, %ymm18
+
+// CHECK: vpsubsb 4064(%rdx), %ymm23, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x45,0x20,0xe8,0x52,0x7f]
+          vpsubsb 4064(%rdx), %ymm23, %ymm18
+
+// CHECK: vpsubsb 4096(%rdx), %ymm23, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x45,0x20,0xe8,0x92,0x00,0x10,0x00,0x00]
+          vpsubsb 4096(%rdx), %ymm23, %ymm18
+
+// CHECK: vpsubsb -4096(%rdx), %ymm23, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x45,0x20,0xe8,0x52,0x80]
+          vpsubsb -4096(%rdx), %ymm23, %ymm18
+
+// CHECK: vpsubsb -4128(%rdx), %ymm23, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x45,0x20,0xe8,0x92,0xe0,0xef,0xff,0xff]
+          vpsubsb -4128(%rdx), %ymm23, %ymm18
+
+// CHECK: vpsubsw %xmm19, %xmm24, %xmm26
+// CHECK:  encoding: [0x62,0x21,0x3d,0x00,0xe9,0xd3]
+          vpsubsw %xmm19, %xmm24, %xmm26
+
+// CHECK: vpsubsw %xmm19, %xmm24, %xmm26 {%k7}
+// CHECK:  encoding: [0x62,0x21,0x3d,0x07,0xe9,0xd3]
+          vpsubsw %xmm19, %xmm24, %xmm26 {%k7}
+
+// CHECK: vpsubsw %xmm19, %xmm24, %xmm26 {%k7} {z}
+// CHECK:  encoding: [0x62,0x21,0x3d,0x87,0xe9,0xd3]
+          vpsubsw %xmm19, %xmm24, %xmm26 {%k7} {z}
+
+// CHECK: vpsubsw (%rcx), %xmm24, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x3d,0x00,0xe9,0x11]
+          vpsubsw (%rcx), %xmm24, %xmm26
+
+// CHECK: vpsubsw 291(%rax,%r14,8), %xmm24, %xmm26
+// CHECK:  encoding: [0x62,0x21,0x3d,0x00,0xe9,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vpsubsw 291(%rax,%r14,8), %xmm24, %xmm26
+
+// CHECK: vpsubsw 2032(%rdx), %xmm24, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x3d,0x00,0xe9,0x52,0x7f]
+          vpsubsw 2032(%rdx), %xmm24, %xmm26
+
+// CHECK: vpsubsw 2048(%rdx), %xmm24, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x3d,0x00,0xe9,0x92,0x00,0x08,0x00,0x00]
+          vpsubsw 2048(%rdx), %xmm24, %xmm26
+
+// CHECK: vpsubsw -2048(%rdx), %xmm24, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x3d,0x00,0xe9,0x52,0x80]
+          vpsubsw -2048(%rdx), %xmm24, %xmm26
+
+// CHECK: vpsubsw -2064(%rdx), %xmm24, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x3d,0x00,0xe9,0x92,0xf0,0xf7,0xff,0xff]
+          vpsubsw -2064(%rdx), %xmm24, %xmm26
+
+// CHECK: vpsubsw %ymm19, %ymm27, %ymm20
+// CHECK:  encoding: [0x62,0xa1,0x25,0x20,0xe9,0xe3]
+          vpsubsw %ymm19, %ymm27, %ymm20
+
+// CHECK: vpsubsw %ymm19, %ymm27, %ymm20 {%k3}
+// CHECK:  encoding: [0x62,0xa1,0x25,0x23,0xe9,0xe3]
+          vpsubsw %ymm19, %ymm27, %ymm20 {%k3}
+
+// CHECK: vpsubsw %ymm19, %ymm27, %ymm20 {%k3} {z}
+// CHECK:  encoding: [0x62,0xa1,0x25,0xa3,0xe9,0xe3]
+          vpsubsw %ymm19, %ymm27, %ymm20 {%k3} {z}
+
+// CHECK: vpsubsw (%rcx), %ymm27, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x25,0x20,0xe9,0x21]
+          vpsubsw (%rcx), %ymm27, %ymm20
+
+// CHECK: vpsubsw 291(%rax,%r14,8), %ymm27, %ymm20
+// CHECK:  encoding: [0x62,0xa1,0x25,0x20,0xe9,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsubsw 291(%rax,%r14,8), %ymm27, %ymm20
+
+// CHECK: vpsubsw 4064(%rdx), %ymm27, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x25,0x20,0xe9,0x62,0x7f]
+          vpsubsw 4064(%rdx), %ymm27, %ymm20
+
+// CHECK: vpsubsw 4096(%rdx), %ymm27, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x25,0x20,0xe9,0xa2,0x00,0x10,0x00,0x00]
+          vpsubsw 4096(%rdx), %ymm27, %ymm20
+
+// CHECK: vpsubsw -4096(%rdx), %ymm27, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x25,0x20,0xe9,0x62,0x80]
+          vpsubsw -4096(%rdx), %ymm27, %ymm20
+
+// CHECK: vpsubsw -4128(%rdx), %ymm27, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x25,0x20,0xe9,0xa2,0xe0,0xef,0xff,0xff]
+          vpsubsw -4128(%rdx), %ymm27, %ymm20
+
+// CHECK: vpsubusb %xmm25, %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0x81,0x65,0x00,0xd8,0xe1]
+          vpsubusb %xmm25, %xmm19, %xmm20
+
+// CHECK: vpsubusb %xmm25, %xmm19, %xmm20 {%k6}
+// CHECK:  encoding: [0x62,0x81,0x65,0x06,0xd8,0xe1]
+          vpsubusb %xmm25, %xmm19, %xmm20 {%k6}
+
+// CHECK: vpsubusb %xmm25, %xmm19, %xmm20 {%k6} {z}
+// CHECK:  encoding: [0x62,0x81,0x65,0x86,0xd8,0xe1]
+          vpsubusb %xmm25, %xmm19, %xmm20 {%k6} {z}
+
+// CHECK: vpsubusb (%rcx), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x65,0x00,0xd8,0x21]
+          vpsubusb (%rcx), %xmm19, %xmm20
+
+// CHECK: vpsubusb 291(%rax,%r14,8), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0x65,0x00,0xd8,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsubusb 291(%rax,%r14,8), %xmm19, %xmm20
+
+// CHECK: vpsubusb 2032(%rdx), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x65,0x00,0xd8,0x62,0x7f]
+          vpsubusb 2032(%rdx), %xmm19, %xmm20
+
+// CHECK: vpsubusb 2048(%rdx), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x65,0x00,0xd8,0xa2,0x00,0x08,0x00,0x00]
+          vpsubusb 2048(%rdx), %xmm19, %xmm20
+
+// CHECK: vpsubusb -2048(%rdx), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x65,0x00,0xd8,0x62,0x80]
+          vpsubusb -2048(%rdx), %xmm19, %xmm20
+
+// CHECK: vpsubusb -2064(%rdx), %xmm19, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x65,0x00,0xd8,0xa2,0xf0,0xf7,0xff,0xff]
+          vpsubusb -2064(%rdx), %xmm19, %xmm20
+
+// CHECK: vpsubusb %ymm19, %ymm19, %ymm21
+// CHECK:  encoding: [0x62,0xa1,0x65,0x20,0xd8,0xeb]
+          vpsubusb %ymm19, %ymm19, %ymm21
+
+// CHECK: vpsubusb %ymm19, %ymm19, %ymm21 {%k3}
+// CHECK:  encoding: [0x62,0xa1,0x65,0x23,0xd8,0xeb]
+          vpsubusb %ymm19, %ymm19, %ymm21 {%k3}
+
+// CHECK: vpsubusb %ymm19, %ymm19, %ymm21 {%k3} {z}
+// CHECK:  encoding: [0x62,0xa1,0x65,0xa3,0xd8,0xeb]
+          vpsubusb %ymm19, %ymm19, %ymm21 {%k3} {z}
+
+// CHECK: vpsubusb (%rcx), %ymm19, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x65,0x20,0xd8,0x29]
+          vpsubusb (%rcx), %ymm19, %ymm21
+
+// CHECK: vpsubusb 291(%rax,%r14,8), %ymm19, %ymm21
+// CHECK:  encoding: [0x62,0xa1,0x65,0x20,0xd8,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpsubusb 291(%rax,%r14,8), %ymm19, %ymm21
+
+// CHECK: vpsubusb 4064(%rdx), %ymm19, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x65,0x20,0xd8,0x6a,0x7f]
+          vpsubusb 4064(%rdx), %ymm19, %ymm21
+
+// CHECK: vpsubusb 4096(%rdx), %ymm19, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x65,0x20,0xd8,0xaa,0x00,0x10,0x00,0x00]
+          vpsubusb 4096(%rdx), %ymm19, %ymm21
+
+// CHECK: vpsubusb -4096(%rdx), %ymm19, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x65,0x20,0xd8,0x6a,0x80]
+          vpsubusb -4096(%rdx), %ymm19, %ymm21
+
+// CHECK: vpsubusb -4128(%rdx), %ymm19, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x65,0x20,0xd8,0xaa,0xe0,0xef,0xff,0xff]
+          vpsubusb -4128(%rdx), %ymm19, %ymm21
+
+// CHECK: vpsubusw %xmm22, %xmm20, %xmm23
+// CHECK:  encoding: [0x62,0xa1,0x5d,0x00,0xd9,0xfe]
+          vpsubusw %xmm22, %xmm20, %xmm23
+
+// CHECK: vpsubusw %xmm22, %xmm20, %xmm23 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0x5d,0x01,0xd9,0xfe]
+          vpsubusw %xmm22, %xmm20, %xmm23 {%k1}
+
+// CHECK: vpsubusw %xmm22, %xmm20, %xmm23 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0x5d,0x81,0xd9,0xfe]
+          vpsubusw %xmm22, %xmm20, %xmm23 {%k1} {z}
+
+// CHECK: vpsubusw (%rcx), %xmm20, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x00,0xd9,0x39]
+          vpsubusw (%rcx), %xmm20, %xmm23
+
+// CHECK: vpsubusw 291(%rax,%r14,8), %xmm20, %xmm23
+// CHECK:  encoding: [0x62,0xa1,0x5d,0x00,0xd9,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vpsubusw 291(%rax,%r14,8), %xmm20, %xmm23
+
+// CHECK: vpsubusw 2032(%rdx), %xmm20, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x00,0xd9,0x7a,0x7f]
+          vpsubusw 2032(%rdx), %xmm20, %xmm23
+
+// CHECK: vpsubusw 2048(%rdx), %xmm20, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x00,0xd9,0xba,0x00,0x08,0x00,0x00]
+          vpsubusw 2048(%rdx), %xmm20, %xmm23
+
+// CHECK: vpsubusw -2048(%rdx), %xmm20, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x00,0xd9,0x7a,0x80]
+          vpsubusw -2048(%rdx), %xmm20, %xmm23
+
+// CHECK: vpsubusw -2064(%rdx), %xmm20, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x00,0xd9,0xba,0xf0,0xf7,0xff,0xff]
+          vpsubusw -2064(%rdx), %xmm20, %xmm23
+
+// CHECK: vpsubusw %ymm28, %ymm17, %ymm27
+// CHECK:  encoding: [0x62,0x01,0x75,0x20,0xd9,0xdc]
+          vpsubusw %ymm28, %ymm17, %ymm27
+
+// CHECK: vpsubusw %ymm28, %ymm17, %ymm27 {%k3}
+// CHECK:  encoding: [0x62,0x01,0x75,0x23,0xd9,0xdc]
+          vpsubusw %ymm28, %ymm17, %ymm27 {%k3}
+
+// CHECK: vpsubusw %ymm28, %ymm17, %ymm27 {%k3} {z}
+// CHECK:  encoding: [0x62,0x01,0x75,0xa3,0xd9,0xdc]
+          vpsubusw %ymm28, %ymm17, %ymm27 {%k3} {z}
+
+// CHECK: vpsubusw (%rcx), %ymm17, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x75,0x20,0xd9,0x19]
+          vpsubusw (%rcx), %ymm17, %ymm27
+
+// CHECK: vpsubusw 291(%rax,%r14,8), %ymm17, %ymm27
+// CHECK:  encoding: [0x62,0x21,0x75,0x20,0xd9,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpsubusw 291(%rax,%r14,8), %ymm17, %ymm27
+
+// CHECK: vpsubusw 4064(%rdx), %ymm17, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x75,0x20,0xd9,0x5a,0x7f]
+          vpsubusw 4064(%rdx), %ymm17, %ymm27
+
+// CHECK: vpsubusw 4096(%rdx), %ymm17, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x75,0x20,0xd9,0x9a,0x00,0x10,0x00,0x00]
+          vpsubusw 4096(%rdx), %ymm17, %ymm27
+
+// CHECK: vpsubusw -4096(%rdx), %ymm17, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x75,0x20,0xd9,0x5a,0x80]
+          vpsubusw -4096(%rdx), %ymm17, %ymm27
+
+// CHECK: vpsubusw -4128(%rdx), %ymm17, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x75,0x20,0xd9,0x9a,0xe0,0xef,0xff,0xff]
+          vpsubusw -4128(%rdx), %ymm17, %ymm27
+
+// CHECK: vpaddsb %xmm18, %xmm23, %xmm17
+// CHECK:  encoding: [0x62,0xa1,0x45,0x00,0xec,0xca]
+          vpaddsb %xmm18, %xmm23, %xmm17
+
+// CHECK: vpaddsb %xmm18, %xmm23, %xmm17 {%k2}
+// CHECK:  encoding: [0x62,0xa1,0x45,0x02,0xec,0xca]
+          vpaddsb %xmm18, %xmm23, %xmm17 {%k2}
+
+// CHECK: vpaddsb %xmm18, %xmm23, %xmm17 {%k2} {z}
+// CHECK:  encoding: [0x62,0xa1,0x45,0x82,0xec,0xca]
+          vpaddsb %xmm18, %xmm23, %xmm17 {%k2} {z}
+
+// CHECK: vpaddsb (%rcx), %xmm23, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x45,0x00,0xec,0x09]
+          vpaddsb (%rcx), %xmm23, %xmm17
+
+// CHECK: vpaddsb 4660(%rax,%r14,8), %xmm23, %xmm17
+// CHECK:  encoding: [0x62,0xa1,0x45,0x00,0xec,0x8c,0xf0,0x34,0x12,0x00,0x00]
+          vpaddsb 4660(%rax,%r14,8), %xmm23, %xmm17
+
+// CHECK: vpaddsb 2032(%rdx), %xmm23, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x45,0x00,0xec,0x4a,0x7f]
+          vpaddsb 2032(%rdx), %xmm23, %xmm17
+
+// CHECK: vpaddsb 2048(%rdx), %xmm23, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x45,0x00,0xec,0x8a,0x00,0x08,0x00,0x00]
+          vpaddsb 2048(%rdx), %xmm23, %xmm17
+
+// CHECK: vpaddsb -2048(%rdx), %xmm23, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x45,0x00,0xec,0x4a,0x80]
+          vpaddsb -2048(%rdx), %xmm23, %xmm17
+
+// CHECK: vpaddsb -2064(%rdx), %xmm23, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x45,0x00,0xec,0x8a,0xf0,0xf7,0xff,0xff]
+          vpaddsb -2064(%rdx), %xmm23, %xmm17
+
+// CHECK: vpaddsb %ymm19, %ymm26, %ymm20
+// CHECK:  encoding: [0x62,0xa1,0x2d,0x20,0xec,0xe3]
+          vpaddsb %ymm19, %ymm26, %ymm20
+
+// CHECK: vpaddsb %ymm19, %ymm26, %ymm20 {%k2}
+// CHECK:  encoding: [0x62,0xa1,0x2d,0x22,0xec,0xe3]
+          vpaddsb %ymm19, %ymm26, %ymm20 {%k2}
+
+// CHECK: vpaddsb %ymm19, %ymm26, %ymm20 {%k2} {z}
+// CHECK:  encoding: [0x62,0xa1,0x2d,0xa2,0xec,0xe3]
+          vpaddsb %ymm19, %ymm26, %ymm20 {%k2} {z}
+
+// CHECK: vpaddsb (%rcx), %ymm26, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x20,0xec,0x21]
+          vpaddsb (%rcx), %ymm26, %ymm20
+
+// CHECK: vpaddsb 4660(%rax,%r14,8), %ymm26, %ymm20
+// CHECK:  encoding: [0x62,0xa1,0x2d,0x20,0xec,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vpaddsb 4660(%rax,%r14,8), %ymm26, %ymm20
+
+// CHECK: vpaddsb 4064(%rdx), %ymm26, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x20,0xec,0x62,0x7f]
+          vpaddsb 4064(%rdx), %ymm26, %ymm20
+
+// CHECK: vpaddsb 4096(%rdx), %ymm26, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x20,0xec,0xa2,0x00,0x10,0x00,0x00]
+          vpaddsb 4096(%rdx), %ymm26, %ymm20
+
+// CHECK: vpaddsb -4096(%rdx), %ymm26, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x20,0xec,0x62,0x80]
+          vpaddsb -4096(%rdx), %ymm26, %ymm20
+
+// CHECK: vpaddsb -4128(%rdx), %ymm26, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x20,0xec,0xa2,0xe0,0xef,0xff,0xff]
+          vpaddsb -4128(%rdx), %ymm26, %ymm20
+
+// CHECK: vpaddsw %xmm26, %xmm17, %xmm26
+// CHECK:  encoding: [0x62,0x01,0x75,0x00,0xed,0xd2]
+          vpaddsw %xmm26, %xmm17, %xmm26
+
+// CHECK: vpaddsw %xmm26, %xmm17, %xmm26 {%k6}
+// CHECK:  encoding: [0x62,0x01,0x75,0x06,0xed,0xd2]
+          vpaddsw %xmm26, %xmm17, %xmm26 {%k6}
+
+// CHECK: vpaddsw %xmm26, %xmm17, %xmm26 {%k6} {z}
+// CHECK:  encoding: [0x62,0x01,0x75,0x86,0xed,0xd2]
+          vpaddsw %xmm26, %xmm17, %xmm26 {%k6} {z}
+
+// CHECK: vpaddsw (%rcx), %xmm17, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x75,0x00,0xed,0x11]
+          vpaddsw (%rcx), %xmm17, %xmm26
+
+// CHECK: vpaddsw 4660(%rax,%r14,8), %xmm17, %xmm26
+// CHECK:  encoding: [0x62,0x21,0x75,0x00,0xed,0x94,0xf0,0x34,0x12,0x00,0x00]
+          vpaddsw 4660(%rax,%r14,8), %xmm17, %xmm26
+
+// CHECK: vpaddsw 2032(%rdx), %xmm17, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x75,0x00,0xed,0x52,0x7f]
+          vpaddsw 2032(%rdx), %xmm17, %xmm26
+
+// CHECK: vpaddsw 2048(%rdx), %xmm17, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x75,0x00,0xed,0x92,0x00,0x08,0x00,0x00]
+          vpaddsw 2048(%rdx), %xmm17, %xmm26
+
+// CHECK: vpaddsw -2048(%rdx), %xmm17, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x75,0x00,0xed,0x52,0x80]
+          vpaddsw -2048(%rdx), %xmm17, %xmm26
+
+// CHECK: vpaddsw -2064(%rdx), %xmm17, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x75,0x00,0xed,0x92,0xf0,0xf7,0xff,0xff]
+          vpaddsw -2064(%rdx), %xmm17, %xmm26
+
+// CHECK: vpaddsw %ymm23, %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x21,0x25,0x20,0xed,0xe7]
+          vpaddsw %ymm23, %ymm27, %ymm28
+
+// CHECK: vpaddsw %ymm23, %ymm27, %ymm28 {%k4}
+// CHECK:  encoding: [0x62,0x21,0x25,0x24,0xed,0xe7]
+          vpaddsw %ymm23, %ymm27, %ymm28 {%k4}
+
+// CHECK: vpaddsw %ymm23, %ymm27, %ymm28 {%k4} {z}
+// CHECK:  encoding: [0x62,0x21,0x25,0xa4,0xed,0xe7]
+          vpaddsw %ymm23, %ymm27, %ymm28 {%k4} {z}
+
+// CHECK: vpaddsw (%rcx), %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x25,0x20,0xed,0x21]
+          vpaddsw (%rcx), %ymm27, %ymm28
+
+// CHECK: vpaddsw 4660(%rax,%r14,8), %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x21,0x25,0x20,0xed,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vpaddsw 4660(%rax,%r14,8), %ymm27, %ymm28
+
+// CHECK: vpaddsw 4064(%rdx), %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x25,0x20,0xed,0x62,0x7f]
+          vpaddsw 4064(%rdx), %ymm27, %ymm28
+
+// CHECK: vpaddsw 4096(%rdx), %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x25,0x20,0xed,0xa2,0x00,0x10,0x00,0x00]
+          vpaddsw 4096(%rdx), %ymm27, %ymm28
+
+// CHECK: vpaddsw -4096(%rdx), %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x25,0x20,0xed,0x62,0x80]
+          vpaddsw -4096(%rdx), %ymm27, %ymm28
+
+// CHECK: vpaddsw -4128(%rdx), %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x25,0x20,0xed,0xa2,0xe0,0xef,0xff,0xff]
+          vpaddsw -4128(%rdx), %ymm27, %ymm28
+
+// CHECK: vpaddusb %xmm18, %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xa1,0x55,0x00,0xdc,0xca]
+          vpaddusb %xmm18, %xmm21, %xmm17
+
+// CHECK: vpaddusb %xmm18, %xmm21, %xmm17 {%k4}
+// CHECK:  encoding: [0x62,0xa1,0x55,0x04,0xdc,0xca]
+          vpaddusb %xmm18, %xmm21, %xmm17 {%k4}
+
+// CHECK: vpaddusb %xmm18, %xmm21, %xmm17 {%k4} {z}
+// CHECK:  encoding: [0x62,0xa1,0x55,0x84,0xdc,0xca]
+          vpaddusb %xmm18, %xmm21, %xmm17 {%k4} {z}
+
+// CHECK: vpaddusb (%rcx), %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x55,0x00,0xdc,0x09]
+          vpaddusb (%rcx), %xmm21, %xmm17
+
+// CHECK: vpaddusb 4660(%rax,%r14,8), %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xa1,0x55,0x00,0xdc,0x8c,0xf0,0x34,0x12,0x00,0x00]
+          vpaddusb 4660(%rax,%r14,8), %xmm21, %xmm17
+
+// CHECK: vpaddusb 2032(%rdx), %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x55,0x00,0xdc,0x4a,0x7f]
+          vpaddusb 2032(%rdx), %xmm21, %xmm17
+
+// CHECK: vpaddusb 2048(%rdx), %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x55,0x00,0xdc,0x8a,0x00,0x08,0x00,0x00]
+          vpaddusb 2048(%rdx), %xmm21, %xmm17
+
+// CHECK: vpaddusb -2048(%rdx), %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x55,0x00,0xdc,0x4a,0x80]
+          vpaddusb -2048(%rdx), %xmm21, %xmm17
+
+// CHECK: vpaddusb -2064(%rdx), %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x55,0x00,0xdc,0x8a,0xf0,0xf7,0xff,0xff]
+          vpaddusb -2064(%rdx), %xmm21, %xmm17
+
+// CHECK: vpaddusb %ymm24, %ymm20, %ymm21
+// CHECK:  encoding: [0x62,0x81,0x5d,0x20,0xdc,0xe8]
+          vpaddusb %ymm24, %ymm20, %ymm21
+
+// CHECK: vpaddusb %ymm24, %ymm20, %ymm21 {%k2}
+// CHECK:  encoding: [0x62,0x81,0x5d,0x22,0xdc,0xe8]
+          vpaddusb %ymm24, %ymm20, %ymm21 {%k2}
+
+// CHECK: vpaddusb %ymm24, %ymm20, %ymm21 {%k2} {z}
+// CHECK:  encoding: [0x62,0x81,0x5d,0xa2,0xdc,0xe8]
+          vpaddusb %ymm24, %ymm20, %ymm21 {%k2} {z}
+
+// CHECK: vpaddusb (%rcx), %ymm20, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x20,0xdc,0x29]
+          vpaddusb (%rcx), %ymm20, %ymm21
+
+// CHECK: vpaddusb 4660(%rax,%r14,8), %ymm20, %ymm21
+// CHECK:  encoding: [0x62,0xa1,0x5d,0x20,0xdc,0xac,0xf0,0x34,0x12,0x00,0x00]
+          vpaddusb 4660(%rax,%r14,8), %ymm20, %ymm21
+
+// CHECK: vpaddusb 4064(%rdx), %ymm20, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x20,0xdc,0x6a,0x7f]
+          vpaddusb 4064(%rdx), %ymm20, %ymm21
+
+// CHECK: vpaddusb 4096(%rdx), %ymm20, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x20,0xdc,0xaa,0x00,0x10,0x00,0x00]
+          vpaddusb 4096(%rdx), %ymm20, %ymm21
+
+// CHECK: vpaddusb -4096(%rdx), %ymm20, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x20,0xdc,0x6a,0x80]
+          vpaddusb -4096(%rdx), %ymm20, %ymm21
+
+// CHECK: vpaddusb -4128(%rdx), %ymm20, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x5d,0x20,0xdc,0xaa,0xe0,0xef,0xff,0xff]
+          vpaddusb -4128(%rdx), %ymm20, %ymm21
+
+// CHECK: vpaddusw %xmm28, %xmm24, %xmm22
+// CHECK:  encoding: [0x62,0x81,0x3d,0x00,0xdd,0xf4]
+          vpaddusw %xmm28, %xmm24, %xmm22
+
+// CHECK: vpaddusw %xmm28, %xmm24, %xmm22 {%k6}
+// CHECK:  encoding: [0x62,0x81,0x3d,0x06,0xdd,0xf4]
+          vpaddusw %xmm28, %xmm24, %xmm22 {%k6}
+
+// CHECK: vpaddusw %xmm28, %xmm24, %xmm22 {%k6} {z}
+// CHECK:  encoding: [0x62,0x81,0x3d,0x86,0xdd,0xf4]
+          vpaddusw %xmm28, %xmm24, %xmm22 {%k6} {z}
+
+// CHECK: vpaddusw (%rcx), %xmm24, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x3d,0x00,0xdd,0x31]
+          vpaddusw (%rcx), %xmm24, %xmm22
+
+// CHECK: vpaddusw 4660(%rax,%r14,8), %xmm24, %xmm22
+// CHECK:  encoding: [0x62,0xa1,0x3d,0x00,0xdd,0xb4,0xf0,0x34,0x12,0x00,0x00]
+          vpaddusw 4660(%rax,%r14,8), %xmm24, %xmm22
+
+// CHECK: vpaddusw 2032(%rdx), %xmm24, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x3d,0x00,0xdd,0x72,0x7f]
+          vpaddusw 2032(%rdx), %xmm24, %xmm22
+
+// CHECK: vpaddusw 2048(%rdx), %xmm24, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x3d,0x00,0xdd,0xb2,0x00,0x08,0x00,0x00]
+          vpaddusw 2048(%rdx), %xmm24, %xmm22
+
+// CHECK: vpaddusw -2048(%rdx), %xmm24, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x3d,0x00,0xdd,0x72,0x80]
+          vpaddusw -2048(%rdx), %xmm24, %xmm22
+
+// CHECK: vpaddusw -2064(%rdx), %xmm24, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x3d,0x00,0xdd,0xb2,0xf0,0xf7,0xff,0xff]
+          vpaddusw -2064(%rdx), %xmm24, %xmm22
+
+// CHECK: vpaddusw %ymm25, %ymm19, %ymm21
+// CHECK:  encoding: [0x62,0x81,0x65,0x20,0xdd,0xe9]
+          vpaddusw %ymm25, %ymm19, %ymm21
+
+// CHECK: vpaddusw %ymm25, %ymm19, %ymm21 {%k2}
+// CHECK:  encoding: [0x62,0x81,0x65,0x22,0xdd,0xe9]
+          vpaddusw %ymm25, %ymm19, %ymm21 {%k2}
+
+// CHECK: vpaddusw %ymm25, %ymm19, %ymm21 {%k2} {z}
+// CHECK:  encoding: [0x62,0x81,0x65,0xa2,0xdd,0xe9]
+          vpaddusw %ymm25, %ymm19, %ymm21 {%k2} {z}
+
+// CHECK: vpaddusw (%rcx), %ymm19, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x65,0x20,0xdd,0x29]
+          vpaddusw (%rcx), %ymm19, %ymm21
+
+// CHECK: vpaddusw 4660(%rax,%r14,8), %ymm19, %ymm21
+// CHECK:  encoding: [0x62,0xa1,0x65,0x20,0xdd,0xac,0xf0,0x34,0x12,0x00,0x00]
+          vpaddusw 4660(%rax,%r14,8), %ymm19, %ymm21
+
+// CHECK: vpaddusw 4064(%rdx), %ymm19, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x65,0x20,0xdd,0x6a,0x7f]
+          vpaddusw 4064(%rdx), %ymm19, %ymm21
+
+// CHECK: vpaddusw 4096(%rdx), %ymm19, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x65,0x20,0xdd,0xaa,0x00,0x10,0x00,0x00]
+          vpaddusw 4096(%rdx), %ymm19, %ymm21
+
+// CHECK: vpaddusw -4096(%rdx), %ymm19, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x65,0x20,0xdd,0x6a,0x80]
+          vpaddusw -4096(%rdx), %ymm19, %ymm21
+
+// CHECK: vpaddusw -4128(%rdx), %ymm19, %ymm21
+// CHECK:  encoding: [0x62,0xe1,0x65,0x20,0xdd,0xaa,0xe0,0xef,0xff,0xff]
+          vpaddusw -4128(%rdx), %ymm19, %ymm21
+
+// CHECK: vpsubsb %xmm22, %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0x2d,0x00,0xe8,0xe6]
+          vpsubsb %xmm22, %xmm26, %xmm20
+
+// CHECK: vpsubsb %xmm22, %xmm26, %xmm20 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0x2d,0x01,0xe8,0xe6]
+          vpsubsb %xmm22, %xmm26, %xmm20 {%k1}
+
+// CHECK: vpsubsb %xmm22, %xmm26, %xmm20 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0x2d,0x81,0xe8,0xe6]
+          vpsubsb %xmm22, %xmm26, %xmm20 {%k1} {z}
+
+// CHECK: vpsubsb (%rcx), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x00,0xe8,0x21]
+          vpsubsb (%rcx), %xmm26, %xmm20
+
+// CHECK: vpsubsb 4660(%rax,%r14,8), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0x2d,0x00,0xe8,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vpsubsb 4660(%rax,%r14,8), %xmm26, %xmm20
+
+// CHECK: vpsubsb 2032(%rdx), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x00,0xe8,0x62,0x7f]
+          vpsubsb 2032(%rdx), %xmm26, %xmm20
+
+// CHECK: vpsubsb 2048(%rdx), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x00,0xe8,0xa2,0x00,0x08,0x00,0x00]
+          vpsubsb 2048(%rdx), %xmm26, %xmm20
+
+// CHECK: vpsubsb -2048(%rdx), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x00,0xe8,0x62,0x80]
+          vpsubsb -2048(%rdx), %xmm26, %xmm20
+
+// CHECK: vpsubsb -2064(%rdx), %xmm26, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x2d,0x00,0xe8,0xa2,0xf0,0xf7,0xff,0xff]
+          vpsubsb -2064(%rdx), %xmm26, %xmm20
+
+// CHECK: vpsubsb %ymm26, %ymm18, %ymm25
+// CHECK:  encoding: [0x62,0x01,0x6d,0x20,0xe8,0xca]
+          vpsubsb %ymm26, %ymm18, %ymm25
+
+// CHECK: vpsubsb %ymm26, %ymm18, %ymm25 {%k6}
+// CHECK:  encoding: [0x62,0x01,0x6d,0x26,0xe8,0xca]
+          vpsubsb %ymm26, %ymm18, %ymm25 {%k6}
+
+// CHECK: vpsubsb %ymm26, %ymm18, %ymm25 {%k6} {z}
+// CHECK:  encoding: [0x62,0x01,0x6d,0xa6,0xe8,0xca]
+          vpsubsb %ymm26, %ymm18, %ymm25 {%k6} {z}
+
+// CHECK: vpsubsb (%rcx), %ymm18, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x6d,0x20,0xe8,0x09]
+          vpsubsb (%rcx), %ymm18, %ymm25
+
+// CHECK: vpsubsb 4660(%rax,%r14,8), %ymm18, %ymm25
+// CHECK:  encoding: [0x62,0x21,0x6d,0x20,0xe8,0x8c,0xf0,0x34,0x12,0x00,0x00]
+          vpsubsb 4660(%rax,%r14,8), %ymm18, %ymm25
+
+// CHECK: vpsubsb 4064(%rdx), %ymm18, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x6d,0x20,0xe8,0x4a,0x7f]
+          vpsubsb 4064(%rdx), %ymm18, %ymm25
+
+// CHECK: vpsubsb 4096(%rdx), %ymm18, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x6d,0x20,0xe8,0x8a,0x00,0x10,0x00,0x00]
+          vpsubsb 4096(%rdx), %ymm18, %ymm25
+
+// CHECK: vpsubsb -4096(%rdx), %ymm18, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x6d,0x20,0xe8,0x4a,0x80]
+          vpsubsb -4096(%rdx), %ymm18, %ymm25
+
+// CHECK: vpsubsb -4128(%rdx), %ymm18, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x6d,0x20,0xe8,0x8a,0xe0,0xef,0xff,0xff]
+          vpsubsb -4128(%rdx), %ymm18, %ymm25
+
+// CHECK: vpsubsw %xmm28, %xmm27, %xmm26
+// CHECK:  encoding: [0x62,0x01,0x25,0x00,0xe9,0xd4]
+          vpsubsw %xmm28, %xmm27, %xmm26
+
+// CHECK: vpsubsw %xmm28, %xmm27, %xmm26 {%k5}
+// CHECK:  encoding: [0x62,0x01,0x25,0x05,0xe9,0xd4]
+          vpsubsw %xmm28, %xmm27, %xmm26 {%k5}
+
+// CHECK: vpsubsw %xmm28, %xmm27, %xmm26 {%k5} {z}
+// CHECK:  encoding: [0x62,0x01,0x25,0x85,0xe9,0xd4]
+          vpsubsw %xmm28, %xmm27, %xmm26 {%k5} {z}
+
+// CHECK: vpsubsw (%rcx), %xmm27, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x25,0x00,0xe9,0x11]
+          vpsubsw (%rcx), %xmm27, %xmm26
+
+// CHECK: vpsubsw 4660(%rax,%r14,8), %xmm27, %xmm26
+// CHECK:  encoding: [0x62,0x21,0x25,0x00,0xe9,0x94,0xf0,0x34,0x12,0x00,0x00]
+          vpsubsw 4660(%rax,%r14,8), %xmm27, %xmm26
+
+// CHECK: vpsubsw 2032(%rdx), %xmm27, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x25,0x00,0xe9,0x52,0x7f]
+          vpsubsw 2032(%rdx), %xmm27, %xmm26
+
+// CHECK: vpsubsw 2048(%rdx), %xmm27, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x25,0x00,0xe9,0x92,0x00,0x08,0x00,0x00]
+          vpsubsw 2048(%rdx), %xmm27, %xmm26
+
+// CHECK: vpsubsw -2048(%rdx), %xmm27, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x25,0x00,0xe9,0x52,0x80]
+          vpsubsw -2048(%rdx), %xmm27, %xmm26
+
+// CHECK: vpsubsw -2064(%rdx), %xmm27, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x25,0x00,0xe9,0x92,0xf0,0xf7,0xff,0xff]
+          vpsubsw -2064(%rdx), %xmm27, %xmm26
+
+// CHECK: vpsubsw %ymm21, %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xa1,0x35,0x20,0xe9,0xf5]
+          vpsubsw %ymm21, %ymm25, %ymm22
+
+// CHECK: vpsubsw %ymm21, %ymm25, %ymm22 {%k3}
+// CHECK:  encoding: [0x62,0xa1,0x35,0x23,0xe9,0xf5]
+          vpsubsw %ymm21, %ymm25, %ymm22 {%k3}
+
+// CHECK: vpsubsw %ymm21, %ymm25, %ymm22 {%k3} {z}
+// CHECK:  encoding: [0x62,0xa1,0x35,0xa3,0xe9,0xf5]
+          vpsubsw %ymm21, %ymm25, %ymm22 {%k3} {z}
+
+// CHECK: vpsubsw (%rcx), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x35,0x20,0xe9,0x31]
+          vpsubsw (%rcx), %ymm25, %ymm22
+
+// CHECK: vpsubsw 4660(%rax,%r14,8), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xa1,0x35,0x20,0xe9,0xb4,0xf0,0x34,0x12,0x00,0x00]
+          vpsubsw 4660(%rax,%r14,8), %ymm25, %ymm22
+
+// CHECK: vpsubsw 4064(%rdx), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x35,0x20,0xe9,0x72,0x7f]
+          vpsubsw 4064(%rdx), %ymm25, %ymm22
+
+// CHECK: vpsubsw 4096(%rdx), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x35,0x20,0xe9,0xb2,0x00,0x10,0x00,0x00]
+          vpsubsw 4096(%rdx), %ymm25, %ymm22
+
+// CHECK: vpsubsw -4096(%rdx), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x35,0x20,0xe9,0x72,0x80]
+          vpsubsw -4096(%rdx), %ymm25, %ymm22
+
+// CHECK: vpsubsw -4128(%rdx), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x35,0x20,0xe9,0xb2,0xe0,0xef,0xff,0xff]
+          vpsubsw -4128(%rdx), %ymm25, %ymm22
+
+// CHECK: vpsubusb %xmm26, %xmm27, %xmm18
+// CHECK:  encoding: [0x62,0x81,0x25,0x00,0xd8,0xd2]
+          vpsubusb %xmm26, %xmm27, %xmm18
+
+// CHECK: vpsubusb %xmm26, %xmm27, %xmm18 {%k2}
+// CHECK:  encoding: [0x62,0x81,0x25,0x02,0xd8,0xd2]
+          vpsubusb %xmm26, %xmm27, %xmm18 {%k2}
+
+// CHECK: vpsubusb %xmm26, %xmm27, %xmm18 {%k2} {z}
+// CHECK:  encoding: [0x62,0x81,0x25,0x82,0xd8,0xd2]
+          vpsubusb %xmm26, %xmm27, %xmm18 {%k2} {z}
+
+// CHECK: vpsubusb (%rcx), %xmm27, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xd8,0x11]
+          vpsubusb (%rcx), %xmm27, %xmm18
+
+// CHECK: vpsubusb 4660(%rax,%r14,8), %xmm27, %xmm18
+// CHECK:  encoding: [0x62,0xa1,0x25,0x00,0xd8,0x94,0xf0,0x34,0x12,0x00,0x00]
+          vpsubusb 4660(%rax,%r14,8), %xmm27, %xmm18
+
+// CHECK: vpsubusb 2032(%rdx), %xmm27, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xd8,0x52,0x7f]
+          vpsubusb 2032(%rdx), %xmm27, %xmm18
+
+// CHECK: vpsubusb 2048(%rdx), %xmm27, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xd8,0x92,0x00,0x08,0x00,0x00]
+          vpsubusb 2048(%rdx), %xmm27, %xmm18
+
+// CHECK: vpsubusb -2048(%rdx), %xmm27, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xd8,0x52,0x80]
+          vpsubusb -2048(%rdx), %xmm27, %xmm18
+
+// CHECK: vpsubusb -2064(%rdx), %xmm27, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xd8,0x92,0xf0,0xf7,0xff,0xff]
+          vpsubusb -2064(%rdx), %xmm27, %xmm18
+
+// CHECK: vpsubusb %ymm19, %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x21,0x65,0x20,0xd8,0xcb]
+          vpsubusb %ymm19, %ymm19, %ymm25
+
+// CHECK: vpsubusb %ymm19, %ymm19, %ymm25 {%k6}
+// CHECK:  encoding: [0x62,0x21,0x65,0x26,0xd8,0xcb]
+          vpsubusb %ymm19, %ymm19, %ymm25 {%k6}
+
+// CHECK: vpsubusb %ymm19, %ymm19, %ymm25 {%k6} {z}
+// CHECK:  encoding: [0x62,0x21,0x65,0xa6,0xd8,0xcb]
+          vpsubusb %ymm19, %ymm19, %ymm25 {%k6} {z}
+
+// CHECK: vpsubusb (%rcx), %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x65,0x20,0xd8,0x09]
+          vpsubusb (%rcx), %ymm19, %ymm25
+
+// CHECK: vpsubusb 4660(%rax,%r14,8), %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x21,0x65,0x20,0xd8,0x8c,0xf0,0x34,0x12,0x00,0x00]
+          vpsubusb 4660(%rax,%r14,8), %ymm19, %ymm25
+
+// CHECK: vpsubusb 4064(%rdx), %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x65,0x20,0xd8,0x4a,0x7f]
+          vpsubusb 4064(%rdx), %ymm19, %ymm25
+
+// CHECK: vpsubusb 4096(%rdx), %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x65,0x20,0xd8,0x8a,0x00,0x10,0x00,0x00]
+          vpsubusb 4096(%rdx), %ymm19, %ymm25
+
+// CHECK: vpsubusb -4096(%rdx), %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x65,0x20,0xd8,0x4a,0x80]
+          vpsubusb -4096(%rdx), %ymm19, %ymm25
+
+// CHECK: vpsubusb -4128(%rdx), %ymm19, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x65,0x20,0xd8,0x8a,0xe0,0xef,0xff,0xff]
+          vpsubusb -4128(%rdx), %ymm19, %ymm25
+
+// CHECK: vpsubusw %xmm25, %xmm27, %xmm21
+// CHECK:  encoding: [0x62,0x81,0x25,0x00,0xd9,0xe9]
+          vpsubusw %xmm25, %xmm27, %xmm21
+
+// CHECK: vpsubusw %xmm25, %xmm27, %xmm21 {%k5}
+// CHECK:  encoding: [0x62,0x81,0x25,0x05,0xd9,0xe9]
+          vpsubusw %xmm25, %xmm27, %xmm21 {%k5}
+
+// CHECK: vpsubusw %xmm25, %xmm27, %xmm21 {%k5} {z}
+// CHECK:  encoding: [0x62,0x81,0x25,0x85,0xd9,0xe9]
+          vpsubusw %xmm25, %xmm27, %xmm21 {%k5} {z}
+
+// CHECK: vpsubusw (%rcx), %xmm27, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xd9,0x29]
+          vpsubusw (%rcx), %xmm27, %xmm21
+
+// CHECK: vpsubusw 4660(%rax,%r14,8), %xmm27, %xmm21
+// CHECK:  encoding: [0x62,0xa1,0x25,0x00,0xd9,0xac,0xf0,0x34,0x12,0x00,0x00]
+          vpsubusw 4660(%rax,%r14,8), %xmm27, %xmm21
+
+// CHECK: vpsubusw 2032(%rdx), %xmm27, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xd9,0x6a,0x7f]
+          vpsubusw 2032(%rdx), %xmm27, %xmm21
+
+// CHECK: vpsubusw 2048(%rdx), %xmm27, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xd9,0xaa,0x00,0x08,0x00,0x00]
+          vpsubusw 2048(%rdx), %xmm27, %xmm21
+
+// CHECK: vpsubusw -2048(%rdx), %xmm27, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xd9,0x6a,0x80]
+          vpsubusw -2048(%rdx), %xmm27, %xmm21
+
+// CHECK: vpsubusw -2064(%rdx), %xmm27, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x25,0x00,0xd9,0xaa,0xf0,0xf7,0xff,0xff]
+          vpsubusw -2064(%rdx), %xmm27, %xmm21
+
+// CHECK: vpsubusw %ymm17, %ymm25, %ymm27
+// CHECK:  encoding: [0x62,0x21,0x35,0x20,0xd9,0xd9]
+          vpsubusw %ymm17, %ymm25, %ymm27
+
+// CHECK: vpsubusw %ymm17, %ymm25, %ymm27 {%k4}
+// CHECK:  encoding: [0x62,0x21,0x35,0x24,0xd9,0xd9]
+          vpsubusw %ymm17, %ymm25, %ymm27 {%k4}
+
+// CHECK: vpsubusw %ymm17, %ymm25, %ymm27 {%k4} {z}
+// CHECK:  encoding: [0x62,0x21,0x35,0xa4,0xd9,0xd9]
+          vpsubusw %ymm17, %ymm25, %ymm27 {%k4} {z}
+
+// CHECK: vpsubusw (%rcx), %ymm25, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x35,0x20,0xd9,0x19]
+          vpsubusw (%rcx), %ymm25, %ymm27
+
+// CHECK: vpsubusw 4660(%rax,%r14,8), %ymm25, %ymm27
+// CHECK:  encoding: [0x62,0x21,0x35,0x20,0xd9,0x9c,0xf0,0x34,0x12,0x00,0x00]
+          vpsubusw 4660(%rax,%r14,8), %ymm25, %ymm27
+
+// CHECK: vpsubusw 4064(%rdx), %ymm25, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x35,0x20,0xd9,0x5a,0x7f]
+          vpsubusw 4064(%rdx), %ymm25, %ymm27
+
+// CHECK: vpsubusw 4096(%rdx), %ymm25, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x35,0x20,0xd9,0x9a,0x00,0x10,0x00,0x00]
+          vpsubusw 4096(%rdx), %ymm25, %ymm27
+
+// CHECK: vpsubusw -4096(%rdx), %ymm25, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x35,0x20,0xd9,0x5a,0x80]
+          vpsubusw -4096(%rdx), %ymm25, %ymm27
+
+// CHECK: vpsubusw -4128(%rdx), %ymm25, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x35,0x20,0xd9,0x9a,0xe0,0xef,0xff,0xff]
+          vpsubusw -4128(%rdx), %ymm25, %ymm27
diff --git a/test/MC/X86/x86-64-avx512dq.s b/test/MC/X86/x86-64-avx512dq.s
index aac176517bf6..7d33abd7deb1 100644
--- a/test/MC/X86/x86-64-avx512dq.s
+++ b/test/MC/X86/x86-64-avx512dq.s
@@ -127,3 +127,1034 @@
 // CHECK: kmovb  %k3, %r13d
 // CHECK:  encoding: [0xc5,0x79,0x93,0xeb]
           kmovb  %k3, %r13d
+
+// CHECK: vandpd %zmm27, %zmm28, %zmm19
+// CHECK:  encoding: [0x62,0x81,0x9d,0x40,0x54,0xdb]
+          vandpd %zmm27, %zmm28, %zmm19
+
+// CHECK: vandpd %zmm27, %zmm28, %zmm19 {%k5}
+// CHECK:  encoding: [0x62,0x81,0x9d,0x45,0x54,0xdb]
+          vandpd %zmm27, %zmm28, %zmm19 {%k5}
+
+// CHECK: vandpd %zmm27, %zmm28, %zmm19 {%k5} {z}
+// CHECK:  encoding: [0x62,0x81,0x9d,0xc5,0x54,0xdb]
+          vandpd %zmm27, %zmm28, %zmm19 {%k5} {z}
+
+// CHECK: vandpd (%rcx), %zmm28, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x40,0x54,0x19]
+          vandpd (%rcx), %zmm28, %zmm19
+
+// CHECK: vandpd 291(%rax,%r14,8), %zmm28, %zmm19
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x40,0x54,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vandpd 291(%rax,%r14,8), %zmm28, %zmm19
+
+// CHECK: vandpd (%rcx){1to8}, %zmm28, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x50,0x54,0x19]
+          vandpd (%rcx){1to8}, %zmm28, %zmm19
+
+// CHECK: vandpd 8128(%rdx), %zmm28, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x40,0x54,0x5a,0x7f]
+          vandpd 8128(%rdx), %zmm28, %zmm19
+
+// CHECK: vandpd 8192(%rdx), %zmm28, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x40,0x54,0x9a,0x00,0x20,0x00,0x00]
+          vandpd 8192(%rdx), %zmm28, %zmm19
+
+// CHECK: vandpd -8192(%rdx), %zmm28, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x40,0x54,0x5a,0x80]
+          vandpd -8192(%rdx), %zmm28, %zmm19
+
+// CHECK: vandpd -8256(%rdx), %zmm28, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x40,0x54,0x9a,0xc0,0xdf,0xff,0xff]
+          vandpd -8256(%rdx), %zmm28, %zmm19
+
+// CHECK: vandpd 1016(%rdx){1to8}, %zmm28, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x50,0x54,0x5a,0x7f]
+          vandpd 1016(%rdx){1to8}, %zmm28, %zmm19
+
+// CHECK: vandpd 1024(%rdx){1to8}, %zmm28, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x50,0x54,0x9a,0x00,0x04,0x00,0x00]
+          vandpd 1024(%rdx){1to8}, %zmm28, %zmm19
+
+// CHECK: vandpd -1024(%rdx){1to8}, %zmm28, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x50,0x54,0x5a,0x80]
+          vandpd -1024(%rdx){1to8}, %zmm28, %zmm19
+
+// CHECK: vandpd -1032(%rdx){1to8}, %zmm28, %zmm19
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x50,0x54,0x9a,0xf8,0xfb,0xff,0xff]
+          vandpd -1032(%rdx){1to8}, %zmm28, %zmm19
+
+// CHECK: vandps %zmm25, %zmm22, %zmm17
+// CHECK:  encoding: [0x62,0x81,0x4c,0x40,0x54,0xc9]
+          vandps %zmm25, %zmm22, %zmm17
+
+// CHECK: vandps %zmm25, %zmm22, %zmm17 {%k4}
+// CHECK:  encoding: [0x62,0x81,0x4c,0x44,0x54,0xc9]
+          vandps %zmm25, %zmm22, %zmm17 {%k4}
+
+// CHECK: vandps %zmm25, %zmm22, %zmm17 {%k4} {z}
+// CHECK:  encoding: [0x62,0x81,0x4c,0xc4,0x54,0xc9]
+          vandps %zmm25, %zmm22, %zmm17 {%k4} {z}
+
+// CHECK: vandps (%rcx), %zmm22, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4c,0x40,0x54,0x09]
+          vandps (%rcx), %zmm22, %zmm17
+
+// CHECK: vandps 291(%rax,%r14,8), %zmm22, %zmm17
+// CHECK:  encoding: [0x62,0xa1,0x4c,0x40,0x54,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vandps 291(%rax,%r14,8), %zmm22, %zmm17
+
+// CHECK: vandps (%rcx){1to16}, %zmm22, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4c,0x50,0x54,0x09]
+          vandps (%rcx){1to16}, %zmm22, %zmm17
+
+// CHECK: vandps 8128(%rdx), %zmm22, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4c,0x40,0x54,0x4a,0x7f]
+          vandps 8128(%rdx), %zmm22, %zmm17
+
+// CHECK: vandps 8192(%rdx), %zmm22, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4c,0x40,0x54,0x8a,0x00,0x20,0x00,0x00]
+          vandps 8192(%rdx), %zmm22, %zmm17
+
+// CHECK: vandps -8192(%rdx), %zmm22, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4c,0x40,0x54,0x4a,0x80]
+          vandps -8192(%rdx), %zmm22, %zmm17
+
+// CHECK: vandps -8256(%rdx), %zmm22, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4c,0x40,0x54,0x8a,0xc0,0xdf,0xff,0xff]
+          vandps -8256(%rdx), %zmm22, %zmm17
+
+// CHECK: vandps 508(%rdx){1to16}, %zmm22, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4c,0x50,0x54,0x4a,0x7f]
+          vandps 508(%rdx){1to16}, %zmm22, %zmm17
+
+// CHECK: vandps 512(%rdx){1to16}, %zmm22, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4c,0x50,0x54,0x8a,0x00,0x02,0x00,0x00]
+          vandps 512(%rdx){1to16}, %zmm22, %zmm17
+
+// CHECK: vandps -512(%rdx){1to16}, %zmm22, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4c,0x50,0x54,0x4a,0x80]
+          vandps -512(%rdx){1to16}, %zmm22, %zmm17
+
+// CHECK: vandps -516(%rdx){1to16}, %zmm22, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x4c,0x50,0x54,0x8a,0xfc,0xfd,0xff,0xff]
+          vandps -516(%rdx){1to16}, %zmm22, %zmm17
+
+// CHECK: vandnpd %zmm22, %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xa1,0xf5,0x40,0x55,0xe6]
+          vandnpd %zmm22, %zmm17, %zmm20
+
+// CHECK: vandnpd %zmm22, %zmm17, %zmm20 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0xf5,0x41,0x55,0xe6]
+          vandnpd %zmm22, %zmm17, %zmm20 {%k1}
+
+// CHECK: vandnpd %zmm22, %zmm17, %zmm20 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0xf5,0xc1,0x55,0xe6]
+          vandnpd %zmm22, %zmm17, %zmm20 {%k1} {z}
+
+// CHECK: vandnpd (%rcx), %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0xf5,0x40,0x55,0x21]
+          vandnpd (%rcx), %zmm17, %zmm20
+
+// CHECK: vandnpd 291(%rax,%r14,8), %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xa1,0xf5,0x40,0x55,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vandnpd 291(%rax,%r14,8), %zmm17, %zmm20
+
+// CHECK: vandnpd (%rcx){1to8}, %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0xf5,0x50,0x55,0x21]
+          vandnpd (%rcx){1to8}, %zmm17, %zmm20
+
+// CHECK: vandnpd 8128(%rdx), %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0xf5,0x40,0x55,0x62,0x7f]
+          vandnpd 8128(%rdx), %zmm17, %zmm20
+
+// CHECK: vandnpd 8192(%rdx), %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0xf5,0x40,0x55,0xa2,0x00,0x20,0x00,0x00]
+          vandnpd 8192(%rdx), %zmm17, %zmm20
+
+// CHECK: vandnpd -8192(%rdx), %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0xf5,0x40,0x55,0x62,0x80]
+          vandnpd -8192(%rdx), %zmm17, %zmm20
+
+// CHECK: vandnpd -8256(%rdx), %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0xf5,0x40,0x55,0xa2,0xc0,0xdf,0xff,0xff]
+          vandnpd -8256(%rdx), %zmm17, %zmm20
+
+// CHECK: vandnpd 1016(%rdx){1to8}, %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0xf5,0x50,0x55,0x62,0x7f]
+          vandnpd 1016(%rdx){1to8}, %zmm17, %zmm20
+
+// CHECK: vandnpd 1024(%rdx){1to8}, %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0xf5,0x50,0x55,0xa2,0x00,0x04,0x00,0x00]
+          vandnpd 1024(%rdx){1to8}, %zmm17, %zmm20
+
+// CHECK: vandnpd -1024(%rdx){1to8}, %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0xf5,0x50,0x55,0x62,0x80]
+          vandnpd -1024(%rdx){1to8}, %zmm17, %zmm20
+
+// CHECK: vandnpd -1032(%rdx){1to8}, %zmm17, %zmm20
+// CHECK:  encoding: [0x62,0xe1,0xf5,0x50,0x55,0xa2,0xf8,0xfb,0xff,0xff]
+          vandnpd -1032(%rdx){1to8}, %zmm17, %zmm20
+
+// CHECK: vandnps %zmm19, %zmm17, %zmm22
+// CHECK:  encoding: [0x62,0xa1,0x74,0x40,0x55,0xf3]
+          vandnps %zmm19, %zmm17, %zmm22
+
+// CHECK: vandnps %zmm19, %zmm17, %zmm22 {%k2}
+// CHECK:  encoding: [0x62,0xa1,0x74,0x42,0x55,0xf3]
+          vandnps %zmm19, %zmm17, %zmm22 {%k2}
+
+// CHECK: vandnps %zmm19, %zmm17, %zmm22 {%k2} {z}
+// CHECK:  encoding: [0x62,0xa1,0x74,0xc2,0x55,0xf3]
+          vandnps %zmm19, %zmm17, %zmm22 {%k2} {z}
+
+// CHECK: vandnps (%rcx), %zmm17, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x74,0x40,0x55,0x31]
+          vandnps (%rcx), %zmm17, %zmm22
+
+// CHECK: vandnps 291(%rax,%r14,8), %zmm17, %zmm22
+// CHECK:  encoding: [0x62,0xa1,0x74,0x40,0x55,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vandnps 291(%rax,%r14,8), %zmm17, %zmm22
+
+// CHECK: vandnps (%rcx){1to16}, %zmm17, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x74,0x50,0x55,0x31]
+          vandnps (%rcx){1to16}, %zmm17, %zmm22
+
+// CHECK: vandnps 8128(%rdx), %zmm17, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x74,0x40,0x55,0x72,0x7f]
+          vandnps 8128(%rdx), %zmm17, %zmm22
+
+// CHECK: vandnps 8192(%rdx), %zmm17, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x74,0x40,0x55,0xb2,0x00,0x20,0x00,0x00]
+          vandnps 8192(%rdx), %zmm17, %zmm22
+
+// CHECK: vandnps -8192(%rdx), %zmm17, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x74,0x40,0x55,0x72,0x80]
+          vandnps -8192(%rdx), %zmm17, %zmm22
+
+// CHECK: vandnps -8256(%rdx), %zmm17, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x74,0x40,0x55,0xb2,0xc0,0xdf,0xff,0xff]
+          vandnps -8256(%rdx), %zmm17, %zmm22
+
+// CHECK: vandnps 508(%rdx){1to16}, %zmm17, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x74,0x50,0x55,0x72,0x7f]
+          vandnps 508(%rdx){1to16}, %zmm17, %zmm22
+
+// CHECK: vandnps 512(%rdx){1to16}, %zmm17, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x74,0x50,0x55,0xb2,0x00,0x02,0x00,0x00]
+          vandnps 512(%rdx){1to16}, %zmm17, %zmm22
+
+// CHECK: vandnps -512(%rdx){1to16}, %zmm17, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x74,0x50,0x55,0x72,0x80]
+          vandnps -512(%rdx){1to16}, %zmm17, %zmm22
+
+// CHECK: vandnps -516(%rdx){1to16}, %zmm17, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x74,0x50,0x55,0xb2,0xfc,0xfd,0xff,0xff]
+          vandnps -516(%rdx){1to16}, %zmm17, %zmm22
+
+// CHECK: vorpd  %zmm21, %zmm22, %zmm30
+// CHECK:  encoding: [0x62,0x21,0xcd,0x40,0x56,0xf5]
+          vorpd  %zmm21, %zmm22, %zmm30
+
+// CHECK: vorpd  %zmm21, %zmm22, %zmm30 {%k6}
+// CHECK:  encoding: [0x62,0x21,0xcd,0x46,0x56,0xf5]
+          vorpd  %zmm21, %zmm22, %zmm30 {%k6}
+
+// CHECK: vorpd  %zmm21, %zmm22, %zmm30 {%k6} {z}
+// CHECK:  encoding: [0x62,0x21,0xcd,0xc6,0x56,0xf5]
+          vorpd  %zmm21, %zmm22, %zmm30 {%k6} {z}
+
+// CHECK: vorpd  (%rcx), %zmm22, %zmm30
+// CHECK:  encoding: [0x62,0x61,0xcd,0x40,0x56,0x31]
+          vorpd  (%rcx), %zmm22, %zmm30
+
+// CHECK: vorpd  291(%rax,%r14,8), %zmm22, %zmm30
+// CHECK:  encoding: [0x62,0x21,0xcd,0x40,0x56,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vorpd  291(%rax,%r14,8), %zmm22, %zmm30
+
+// CHECK: vorpd  (%rcx){1to8}, %zmm22, %zmm30
+// CHECK:  encoding: [0x62,0x61,0xcd,0x50,0x56,0x31]
+          vorpd  (%rcx){1to8}, %zmm22, %zmm30
+
+// CHECK: vorpd  8128(%rdx), %zmm22, %zmm30
+// CHECK:  encoding: [0x62,0x61,0xcd,0x40,0x56,0x72,0x7f]
+          vorpd  8128(%rdx), %zmm22, %zmm30
+
+// CHECK: vorpd  8192(%rdx), %zmm22, %zmm30
+// CHECK:  encoding: [0x62,0x61,0xcd,0x40,0x56,0xb2,0x00,0x20,0x00,0x00]
+          vorpd  8192(%rdx), %zmm22, %zmm30
+
+// CHECK: vorpd  -8192(%rdx), %zmm22, %zmm30
+// CHECK:  encoding: [0x62,0x61,0xcd,0x40,0x56,0x72,0x80]
+          vorpd  -8192(%rdx), %zmm22, %zmm30
+
+// CHECK: vorpd  -8256(%rdx), %zmm22, %zmm30
+// CHECK:  encoding: [0x62,0x61,0xcd,0x40,0x56,0xb2,0xc0,0xdf,0xff,0xff]
+          vorpd  -8256(%rdx), %zmm22, %zmm30
+
+// CHECK: vorpd  1016(%rdx){1to8}, %zmm22, %zmm30
+// CHECK:  encoding: [0x62,0x61,0xcd,0x50,0x56,0x72,0x7f]
+          vorpd  1016(%rdx){1to8}, %zmm22, %zmm30
+
+// CHECK: vorpd  1024(%rdx){1to8}, %zmm22, %zmm30
+// CHECK:  encoding: [0x62,0x61,0xcd,0x50,0x56,0xb2,0x00,0x04,0x00,0x00]
+          vorpd  1024(%rdx){1to8}, %zmm22, %zmm30
+
+// CHECK: vorpd  -1024(%rdx){1to8}, %zmm22, %zmm30
+// CHECK:  encoding: [0x62,0x61,0xcd,0x50,0x56,0x72,0x80]
+          vorpd  -1024(%rdx){1to8}, %zmm22, %zmm30
+
+// CHECK: vorpd  -1032(%rdx){1to8}, %zmm22, %zmm30
+// CHECK:  encoding: [0x62,0x61,0xcd,0x50,0x56,0xb2,0xf8,0xfb,0xff,0xff]
+          vorpd  -1032(%rdx){1to8}, %zmm22, %zmm30
+
+// CHECK: vorps  %zmm26, %zmm21, %zmm22
+// CHECK:  encoding: [0x62,0x81,0x54,0x40,0x56,0xf2]
+          vorps  %zmm26, %zmm21, %zmm22
+
+// CHECK: vorps  %zmm26, %zmm21, %zmm22 {%k7}
+// CHECK:  encoding: [0x62,0x81,0x54,0x47,0x56,0xf2]
+          vorps  %zmm26, %zmm21, %zmm22 {%k7}
+
+// CHECK: vorps  %zmm26, %zmm21, %zmm22 {%k7} {z}
+// CHECK:  encoding: [0x62,0x81,0x54,0xc7,0x56,0xf2]
+          vorps  %zmm26, %zmm21, %zmm22 {%k7} {z}
+
+// CHECK: vorps  (%rcx), %zmm21, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x54,0x40,0x56,0x31]
+          vorps  (%rcx), %zmm21, %zmm22
+
+// CHECK: vorps  291(%rax,%r14,8), %zmm21, %zmm22
+// CHECK:  encoding: [0x62,0xa1,0x54,0x40,0x56,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vorps  291(%rax,%r14,8), %zmm21, %zmm22
+
+// CHECK: vorps  (%rcx){1to16}, %zmm21, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x54,0x50,0x56,0x31]
+          vorps  (%rcx){1to16}, %zmm21, %zmm22
+
+// CHECK: vorps  8128(%rdx), %zmm21, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x54,0x40,0x56,0x72,0x7f]
+          vorps  8128(%rdx), %zmm21, %zmm22
+
+// CHECK: vorps  8192(%rdx), %zmm21, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x54,0x40,0x56,0xb2,0x00,0x20,0x00,0x00]
+          vorps  8192(%rdx), %zmm21, %zmm22
+
+// CHECK: vorps  -8192(%rdx), %zmm21, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x54,0x40,0x56,0x72,0x80]
+          vorps  -8192(%rdx), %zmm21, %zmm22
+
+// CHECK: vorps  -8256(%rdx), %zmm21, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x54,0x40,0x56,0xb2,0xc0,0xdf,0xff,0xff]
+          vorps  -8256(%rdx), %zmm21, %zmm22
+
+// CHECK: vorps  508(%rdx){1to16}, %zmm21, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x54,0x50,0x56,0x72,0x7f]
+          vorps  508(%rdx){1to16}, %zmm21, %zmm22
+
+// CHECK: vorps  512(%rdx){1to16}, %zmm21, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x54,0x50,0x56,0xb2,0x00,0x02,0x00,0x00]
+          vorps  512(%rdx){1to16}, %zmm21, %zmm22
+
+// CHECK: vorps  -512(%rdx){1to16}, %zmm21, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x54,0x50,0x56,0x72,0x80]
+          vorps  -512(%rdx){1to16}, %zmm21, %zmm22
+
+// CHECK: vorps  -516(%rdx){1to16}, %zmm21, %zmm22
+// CHECK:  encoding: [0x62,0xe1,0x54,0x50,0x56,0xb2,0xfc,0xfd,0xff,0xff]
+          vorps  -516(%rdx){1to16}, %zmm21, %zmm22
+
+// CHECK: vxorpd %zmm24, %zmm24, %zmm27
+// CHECK:  encoding: [0x62,0x01,0xbd,0x40,0x57,0xd8]
+          vxorpd %zmm24, %zmm24, %zmm27
+
+// CHECK: vxorpd %zmm24, %zmm24, %zmm27 {%k5}
+// CHECK:  encoding: [0x62,0x01,0xbd,0x45,0x57,0xd8]
+          vxorpd %zmm24, %zmm24, %zmm27 {%k5}
+
+// CHECK: vxorpd %zmm24, %zmm24, %zmm27 {%k5} {z}
+// CHECK:  encoding: [0x62,0x01,0xbd,0xc5,0x57,0xd8]
+          vxorpd %zmm24, %zmm24, %zmm27 {%k5} {z}
+
+// CHECK: vxorpd (%rcx), %zmm24, %zmm27
+// CHECK:  encoding: [0x62,0x61,0xbd,0x40,0x57,0x19]
+          vxorpd (%rcx), %zmm24, %zmm27
+
+// CHECK: vxorpd 291(%rax,%r14,8), %zmm24, %zmm27
+// CHECK:  encoding: [0x62,0x21,0xbd,0x40,0x57,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vxorpd 291(%rax,%r14,8), %zmm24, %zmm27
+
+// CHECK: vxorpd (%rcx){1to8}, %zmm24, %zmm27
+// CHECK:  encoding: [0x62,0x61,0xbd,0x50,0x57,0x19]
+          vxorpd (%rcx){1to8}, %zmm24, %zmm27
+
+// CHECK: vxorpd 8128(%rdx), %zmm24, %zmm27
+// CHECK:  encoding: [0x62,0x61,0xbd,0x40,0x57,0x5a,0x7f]
+          vxorpd 8128(%rdx), %zmm24, %zmm27
+
+// CHECK: vxorpd 8192(%rdx), %zmm24, %zmm27
+// CHECK:  encoding: [0x62,0x61,0xbd,0x40,0x57,0x9a,0x00,0x20,0x00,0x00]
+          vxorpd 8192(%rdx), %zmm24, %zmm27
+
+// CHECK: vxorpd -8192(%rdx), %zmm24, %zmm27
+// CHECK:  encoding: [0x62,0x61,0xbd,0x40,0x57,0x5a,0x80]
+          vxorpd -8192(%rdx), %zmm24, %zmm27
+
+// CHECK: vxorpd -8256(%rdx), %zmm24, %zmm27
+// CHECK:  encoding: [0x62,0x61,0xbd,0x40,0x57,0x9a,0xc0,0xdf,0xff,0xff]
+          vxorpd -8256(%rdx), %zmm24, %zmm27
+
+// CHECK: vxorpd 1016(%rdx){1to8}, %zmm24, %zmm27
+// CHECK:  encoding: [0x62,0x61,0xbd,0x50,0x57,0x5a,0x7f]
+          vxorpd 1016(%rdx){1to8}, %zmm24, %zmm27
+
+// CHECK: vxorpd 1024(%rdx){1to8}, %zmm24, %zmm27
+// CHECK:  encoding: [0x62,0x61,0xbd,0x50,0x57,0x9a,0x00,0x04,0x00,0x00]
+          vxorpd 1024(%rdx){1to8}, %zmm24, %zmm27
+
+// CHECK: vxorpd -1024(%rdx){1to8}, %zmm24, %zmm27
+// CHECK:  encoding: [0x62,0x61,0xbd,0x50,0x57,0x5a,0x80]
+          vxorpd -1024(%rdx){1to8}, %zmm24, %zmm27
+
+// CHECK: vxorpd -1032(%rdx){1to8}, %zmm24, %zmm27
+// CHECK:  encoding: [0x62,0x61,0xbd,0x50,0x57,0x9a,0xf8,0xfb,0xff,0xff]
+          vxorpd -1032(%rdx){1to8}, %zmm24, %zmm27
+
+// CHECK: vxorps %zmm19, %zmm18, %zmm18
+// CHECK:  encoding: [0x62,0xa1,0x6c,0x40,0x57,0xd3]
+          vxorps %zmm19, %zmm18, %zmm18
+
+// CHECK: vxorps %zmm19, %zmm18, %zmm18 {%k2}
+// CHECK:  encoding: [0x62,0xa1,0x6c,0x42,0x57,0xd3]
+          vxorps %zmm19, %zmm18, %zmm18 {%k2}
+
+// CHECK: vxorps %zmm19, %zmm18, %zmm18 {%k2} {z}
+// CHECK:  encoding: [0x62,0xa1,0x6c,0xc2,0x57,0xd3]
+          vxorps %zmm19, %zmm18, %zmm18 {%k2} {z}
+
+// CHECK: vxorps (%rcx), %zmm18, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x40,0x57,0x11]
+          vxorps (%rcx), %zmm18, %zmm18
+
+// CHECK: vxorps 291(%rax,%r14,8), %zmm18, %zmm18
+// CHECK:  encoding: [0x62,0xa1,0x6c,0x40,0x57,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vxorps 291(%rax,%r14,8), %zmm18, %zmm18
+
+// CHECK: vxorps (%rcx){1to16}, %zmm18, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x50,0x57,0x11]
+          vxorps (%rcx){1to16}, %zmm18, %zmm18
+
+// CHECK: vxorps 8128(%rdx), %zmm18, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x40,0x57,0x52,0x7f]
+          vxorps 8128(%rdx), %zmm18, %zmm18
+
+// CHECK: vxorps 8192(%rdx), %zmm18, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x40,0x57,0x92,0x00,0x20,0x00,0x00]
+          vxorps 8192(%rdx), %zmm18, %zmm18
+
+// CHECK: vxorps -8192(%rdx), %zmm18, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x40,0x57,0x52,0x80]
+          vxorps -8192(%rdx), %zmm18, %zmm18
+
+// CHECK: vxorps -8256(%rdx), %zmm18, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x40,0x57,0x92,0xc0,0xdf,0xff,0xff]
+          vxorps -8256(%rdx), %zmm18, %zmm18
+
+// CHECK: vxorps 508(%rdx){1to16}, %zmm18, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x50,0x57,0x52,0x7f]
+          vxorps 508(%rdx){1to16}, %zmm18, %zmm18
+
+// CHECK: vxorps 512(%rdx){1to16}, %zmm18, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x50,0x57,0x92,0x00,0x02,0x00,0x00]
+          vxorps 512(%rdx){1to16}, %zmm18, %zmm18
+
+// CHECK: vxorps -512(%rdx){1to16}, %zmm18, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x50,0x57,0x52,0x80]
+          vxorps -512(%rdx){1to16}, %zmm18, %zmm18
+
+// CHECK: vxorps -516(%rdx){1to16}, %zmm18, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x50,0x57,0x92,0xfc,0xfd,0xff,0xff]
+          vxorps -516(%rdx){1to16}, %zmm18, %zmm18
+// CHECK: vandpd %zmm22, %zmm22, %zmm24
+// CHECK:  encoding: [0x62,0x21,0xcd,0x40,0x54,0xc6]
+          vandpd %zmm22, %zmm22, %zmm24
+
+// CHECK: vandpd %zmm22, %zmm22, %zmm24 {%k4}
+// CHECK:  encoding: [0x62,0x21,0xcd,0x44,0x54,0xc6]
+          vandpd %zmm22, %zmm22, %zmm24 {%k4}
+
+// CHECK: vandpd %zmm22, %zmm22, %zmm24 {%k4} {z}
+// CHECK:  encoding: [0x62,0x21,0xcd,0xc4,0x54,0xc6]
+          vandpd %zmm22, %zmm22, %zmm24 {%k4} {z}
+
+// CHECK: vandpd (%rcx), %zmm22, %zmm24
+// CHECK:  encoding: [0x62,0x61,0xcd,0x40,0x54,0x01]
+          vandpd (%rcx), %zmm22, %zmm24
+
+// CHECK: vandpd 4660(%rax,%r14,8), %zmm22, %zmm24
+// CHECK:  encoding: [0x62,0x21,0xcd,0x40,0x54,0x84,0xf0,0x34,0x12,0x00,0x00]
+          vandpd 4660(%rax,%r14,8), %zmm22, %zmm24
+
+// CHECK: vandpd (%rcx){1to8}, %zmm22, %zmm24
+// CHECK:  encoding: [0x62,0x61,0xcd,0x50,0x54,0x01]
+          vandpd (%rcx){1to8}, %zmm22, %zmm24
+
+// CHECK: vandpd 8128(%rdx), %zmm22, %zmm24
+// CHECK:  encoding: [0x62,0x61,0xcd,0x40,0x54,0x42,0x7f]
+          vandpd 8128(%rdx), %zmm22, %zmm24
+
+// CHECK: vandpd 8192(%rdx), %zmm22, %zmm24
+// CHECK:  encoding: [0x62,0x61,0xcd,0x40,0x54,0x82,0x00,0x20,0x00,0x00]
+          vandpd 8192(%rdx), %zmm22, %zmm24
+
+// CHECK: vandpd -8192(%rdx), %zmm22, %zmm24
+// CHECK:  encoding: [0x62,0x61,0xcd,0x40,0x54,0x42,0x80]
+          vandpd -8192(%rdx), %zmm22, %zmm24
+
+// CHECK: vandpd -8256(%rdx), %zmm22, %zmm24
+// CHECK:  encoding: [0x62,0x61,0xcd,0x40,0x54,0x82,0xc0,0xdf,0xff,0xff]
+          vandpd -8256(%rdx), %zmm22, %zmm24
+
+// CHECK: vandpd 1016(%rdx){1to8}, %zmm22, %zmm24
+// CHECK:  encoding: [0x62,0x61,0xcd,0x50,0x54,0x42,0x7f]
+          vandpd 1016(%rdx){1to8}, %zmm22, %zmm24
+
+// CHECK: vandpd 1024(%rdx){1to8}, %zmm22, %zmm24
+// CHECK:  encoding: [0x62,0x61,0xcd,0x50,0x54,0x82,0x00,0x04,0x00,0x00]
+          vandpd 1024(%rdx){1to8}, %zmm22, %zmm24
+
+// CHECK: vandpd -1024(%rdx){1to8}, %zmm22, %zmm24
+// CHECK:  encoding: [0x62,0x61,0xcd,0x50,0x54,0x42,0x80]
+          vandpd -1024(%rdx){1to8}, %zmm22, %zmm24
+
+// CHECK: vandpd -1032(%rdx){1to8}, %zmm22, %zmm24
+// CHECK:  encoding: [0x62,0x61,0xcd,0x50,0x54,0x82,0xf8,0xfb,0xff,0xff]
+          vandpd -1032(%rdx){1to8}, %zmm22, %zmm24
+
+// CHECK: vandps %zmm23, %zmm23, %zmm30
+// CHECK:  encoding: [0x62,0x21,0x44,0x40,0x54,0xf7]
+          vandps %zmm23, %zmm23, %zmm30
+
+// CHECK: vandps %zmm23, %zmm23, %zmm30 {%k5}
+// CHECK:  encoding: [0x62,0x21,0x44,0x45,0x54,0xf7]
+          vandps %zmm23, %zmm23, %zmm30 {%k5}
+
+// CHECK: vandps %zmm23, %zmm23, %zmm30 {%k5} {z}
+// CHECK:  encoding: [0x62,0x21,0x44,0xc5,0x54,0xf7]
+          vandps %zmm23, %zmm23, %zmm30 {%k5} {z}
+
+// CHECK: vandps (%rcx), %zmm23, %zmm30
+// CHECK:  encoding: [0x62,0x61,0x44,0x40,0x54,0x31]
+          vandps (%rcx), %zmm23, %zmm30
+
+// CHECK: vandps 4660(%rax,%r14,8), %zmm23, %zmm30
+// CHECK:  encoding: [0x62,0x21,0x44,0x40,0x54,0xb4,0xf0,0x34,0x12,0x00,0x00]
+          vandps 4660(%rax,%r14,8), %zmm23, %zmm30
+
+// CHECK: vandps (%rcx){1to16}, %zmm23, %zmm30
+// CHECK:  encoding: [0x62,0x61,0x44,0x50,0x54,0x31]
+          vandps (%rcx){1to16}, %zmm23, %zmm30
+
+// CHECK: vandps 8128(%rdx), %zmm23, %zmm30
+// CHECK:  encoding: [0x62,0x61,0x44,0x40,0x54,0x72,0x7f]
+          vandps 8128(%rdx), %zmm23, %zmm30
+
+// CHECK: vandps 8192(%rdx), %zmm23, %zmm30
+// CHECK:  encoding: [0x62,0x61,0x44,0x40,0x54,0xb2,0x00,0x20,0x00,0x00]
+          vandps 8192(%rdx), %zmm23, %zmm30
+
+// CHECK: vandps -8192(%rdx), %zmm23, %zmm30
+// CHECK:  encoding: [0x62,0x61,0x44,0x40,0x54,0x72,0x80]
+          vandps -8192(%rdx), %zmm23, %zmm30
+
+// CHECK: vandps -8256(%rdx), %zmm23, %zmm30
+// CHECK:  encoding: [0x62,0x61,0x44,0x40,0x54,0xb2,0xc0,0xdf,0xff,0xff]
+          vandps -8256(%rdx), %zmm23, %zmm30
+
+// CHECK: vandps 508(%rdx){1to16}, %zmm23, %zmm30
+// CHECK:  encoding: [0x62,0x61,0x44,0x50,0x54,0x72,0x7f]
+          vandps 508(%rdx){1to16}, %zmm23, %zmm30
+
+// CHECK: vandps 512(%rdx){1to16}, %zmm23, %zmm30
+// CHECK:  encoding: [0x62,0x61,0x44,0x50,0x54,0xb2,0x00,0x02,0x00,0x00]
+          vandps 512(%rdx){1to16}, %zmm23, %zmm30
+
+// CHECK: vandps -512(%rdx){1to16}, %zmm23, %zmm30
+// CHECK:  encoding: [0x62,0x61,0x44,0x50,0x54,0x72,0x80]
+          vandps -512(%rdx){1to16}, %zmm23, %zmm30
+
+// CHECK: vandps -516(%rdx){1to16}, %zmm23, %zmm30
+// CHECK:  encoding: [0x62,0x61,0x44,0x50,0x54,0xb2,0xfc,0xfd,0xff,0xff]
+          vandps -516(%rdx){1to16}, %zmm23, %zmm30
+
+// CHECK: vandnpd %zmm21, %zmm21, %zmm25
+// CHECK:  encoding: [0x62,0x21,0xd5,0x40,0x55,0xcd]
+          vandnpd %zmm21, %zmm21, %zmm25
+
+// CHECK: vandnpd %zmm21, %zmm21, %zmm25 {%k2}
+// CHECK:  encoding: [0x62,0x21,0xd5,0x42,0x55,0xcd]
+          vandnpd %zmm21, %zmm21, %zmm25 {%k2}
+
+// CHECK: vandnpd %zmm21, %zmm21, %zmm25 {%k2} {z}
+// CHECK:  encoding: [0x62,0x21,0xd5,0xc2,0x55,0xcd]
+          vandnpd %zmm21, %zmm21, %zmm25 {%k2} {z}
+
+// CHECK: vandnpd (%rcx), %zmm21, %zmm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x40,0x55,0x09]
+          vandnpd (%rcx), %zmm21, %zmm25
+
+// CHECK: vandnpd 4660(%rax,%r14,8), %zmm21, %zmm25
+// CHECK:  encoding: [0x62,0x21,0xd5,0x40,0x55,0x8c,0xf0,0x34,0x12,0x00,0x00]
+          vandnpd 4660(%rax,%r14,8), %zmm21, %zmm25
+
+// CHECK: vandnpd (%rcx){1to8}, %zmm21, %zmm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x50,0x55,0x09]
+          vandnpd (%rcx){1to8}, %zmm21, %zmm25
+
+// CHECK: vandnpd 8128(%rdx), %zmm21, %zmm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x40,0x55,0x4a,0x7f]
+          vandnpd 8128(%rdx), %zmm21, %zmm25
+
+// CHECK: vandnpd 8192(%rdx), %zmm21, %zmm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x40,0x55,0x8a,0x00,0x20,0x00,0x00]
+          vandnpd 8192(%rdx), %zmm21, %zmm25
+
+// CHECK: vandnpd -8192(%rdx), %zmm21, %zmm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x40,0x55,0x4a,0x80]
+          vandnpd -8192(%rdx), %zmm21, %zmm25
+
+// CHECK: vandnpd -8256(%rdx), %zmm21, %zmm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x40,0x55,0x8a,0xc0,0xdf,0xff,0xff]
+          vandnpd -8256(%rdx), %zmm21, %zmm25
+
+// CHECK: vandnpd 1016(%rdx){1to8}, %zmm21, %zmm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x50,0x55,0x4a,0x7f]
+          vandnpd 1016(%rdx){1to8}, %zmm21, %zmm25
+
+// CHECK: vandnpd 1024(%rdx){1to8}, %zmm21, %zmm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x50,0x55,0x8a,0x00,0x04,0x00,0x00]
+          vandnpd 1024(%rdx){1to8}, %zmm21, %zmm25
+
+// CHECK: vandnpd -1024(%rdx){1to8}, %zmm21, %zmm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x50,0x55,0x4a,0x80]
+          vandnpd -1024(%rdx){1to8}, %zmm21, %zmm25
+
+// CHECK: vandnpd -1032(%rdx){1to8}, %zmm21, %zmm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x50,0x55,0x8a,0xf8,0xfb,0xff,0xff]
+          vandnpd -1032(%rdx){1to8}, %zmm21, %zmm25
+
+// CHECK: vandnps %zmm18, %zmm21, %zmm17
+// CHECK:  encoding: [0x62,0xa1,0x54,0x40,0x55,0xca]
+          vandnps %zmm18, %zmm21, %zmm17
+
+// CHECK: vandnps %zmm18, %zmm21, %zmm17 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0x54,0x41,0x55,0xca]
+          vandnps %zmm18, %zmm21, %zmm17 {%k1}
+
+// CHECK: vandnps %zmm18, %zmm21, %zmm17 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0x54,0xc1,0x55,0xca]
+          vandnps %zmm18, %zmm21, %zmm17 {%k1} {z}
+
+// CHECK: vandnps (%rcx), %zmm21, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x40,0x55,0x09]
+          vandnps (%rcx), %zmm21, %zmm17
+
+// CHECK: vandnps 4660(%rax,%r14,8), %zmm21, %zmm17
+// CHECK:  encoding: [0x62,0xa1,0x54,0x40,0x55,0x8c,0xf0,0x34,0x12,0x00,0x00]
+          vandnps 4660(%rax,%r14,8), %zmm21, %zmm17
+
+// CHECK: vandnps (%rcx){1to16}, %zmm21, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x50,0x55,0x09]
+          vandnps (%rcx){1to16}, %zmm21, %zmm17
+
+// CHECK: vandnps 8128(%rdx), %zmm21, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x40,0x55,0x4a,0x7f]
+          vandnps 8128(%rdx), %zmm21, %zmm17
+
+// CHECK: vandnps 8192(%rdx), %zmm21, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x40,0x55,0x8a,0x00,0x20,0x00,0x00]
+          vandnps 8192(%rdx), %zmm21, %zmm17
+
+// CHECK: vandnps -8192(%rdx), %zmm21, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x40,0x55,0x4a,0x80]
+          vandnps -8192(%rdx), %zmm21, %zmm17
+
+// CHECK: vandnps -8256(%rdx), %zmm21, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x40,0x55,0x8a,0xc0,0xdf,0xff,0xff]
+          vandnps -8256(%rdx), %zmm21, %zmm17
+
+// CHECK: vandnps 508(%rdx){1to16}, %zmm21, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x50,0x55,0x4a,0x7f]
+          vandnps 508(%rdx){1to16}, %zmm21, %zmm17
+
+// CHECK: vandnps 512(%rdx){1to16}, %zmm21, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x50,0x55,0x8a,0x00,0x02,0x00,0x00]
+          vandnps 512(%rdx){1to16}, %zmm21, %zmm17
+
+// CHECK: vandnps -512(%rdx){1to16}, %zmm21, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x50,0x55,0x4a,0x80]
+          vandnps -512(%rdx){1to16}, %zmm21, %zmm17
+
+// CHECK: vandnps -516(%rdx){1to16}, %zmm21, %zmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x50,0x55,0x8a,0xfc,0xfd,0xff,0xff]
+          vandnps -516(%rdx){1to16}, %zmm21, %zmm17
+
+// CHECK: vorpd  %zmm24, %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0x81,0x9d,0x40,0x56,0xd0]
+          vorpd  %zmm24, %zmm28, %zmm18
+
+// CHECK: vorpd  %zmm24, %zmm28, %zmm18 {%k1}
+// CHECK:  encoding: [0x62,0x81,0x9d,0x41,0x56,0xd0]
+          vorpd  %zmm24, %zmm28, %zmm18 {%k1}
+
+// CHECK: vorpd  %zmm24, %zmm28, %zmm18 {%k1} {z}
+// CHECK:  encoding: [0x62,0x81,0x9d,0xc1,0x56,0xd0]
+          vorpd  %zmm24, %zmm28, %zmm18 {%k1} {z}
+
+// CHECK: vorpd  (%rcx), %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x40,0x56,0x11]
+          vorpd  (%rcx), %zmm28, %zmm18
+
+// CHECK: vorpd  4660(%rax,%r14,8), %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x40,0x56,0x94,0xf0,0x34,0x12,0x00,0x00]
+          vorpd  4660(%rax,%r14,8), %zmm28, %zmm18
+
+// CHECK: vorpd  (%rcx){1to8}, %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x50,0x56,0x11]
+          vorpd  (%rcx){1to8}, %zmm28, %zmm18
+
+// CHECK: vorpd  8128(%rdx), %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x40,0x56,0x52,0x7f]
+          vorpd  8128(%rdx), %zmm28, %zmm18
+
+// CHECK: vorpd  8192(%rdx), %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x40,0x56,0x92,0x00,0x20,0x00,0x00]
+          vorpd  8192(%rdx), %zmm28, %zmm18
+
+// CHECK: vorpd  -8192(%rdx), %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x40,0x56,0x52,0x80]
+          vorpd  -8192(%rdx), %zmm28, %zmm18
+
+// CHECK: vorpd  -8256(%rdx), %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x40,0x56,0x92,0xc0,0xdf,0xff,0xff]
+          vorpd  -8256(%rdx), %zmm28, %zmm18
+
+// CHECK: vorpd  1016(%rdx){1to8}, %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x50,0x56,0x52,0x7f]
+          vorpd  1016(%rdx){1to8}, %zmm28, %zmm18
+
+// CHECK: vorpd  1024(%rdx){1to8}, %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x50,0x56,0x92,0x00,0x04,0x00,0x00]
+          vorpd  1024(%rdx){1to8}, %zmm28, %zmm18
+
+// CHECK: vorpd  -1024(%rdx){1to8}, %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x50,0x56,0x52,0x80]
+          vorpd  -1024(%rdx){1to8}, %zmm28, %zmm18
+
+// CHECK: vorpd  -1032(%rdx){1to8}, %zmm28, %zmm18
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x50,0x56,0x92,0xf8,0xfb,0xff,0xff]
+          vorpd  -1032(%rdx){1to8}, %zmm28, %zmm18
+
+// CHECK: vorps  %zmm23, %zmm17, %zmm28
+// CHECK:  encoding: [0x62,0x21,0x74,0x40,0x56,0xe7]
+          vorps  %zmm23, %zmm17, %zmm28
+
+// CHECK: vorps  %zmm23, %zmm17, %zmm28 {%k7}
+// CHECK:  encoding: [0x62,0x21,0x74,0x47,0x56,0xe7]
+          vorps  %zmm23, %zmm17, %zmm28 {%k7}
+
+// CHECK: vorps  %zmm23, %zmm17, %zmm28 {%k7} {z}
+// CHECK:  encoding: [0x62,0x21,0x74,0xc7,0x56,0xe7]
+          vorps  %zmm23, %zmm17, %zmm28 {%k7} {z}
+
+// CHECK: vorps  (%rcx), %zmm17, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x74,0x40,0x56,0x21]
+          vorps  (%rcx), %zmm17, %zmm28
+
+// CHECK: vorps  4660(%rax,%r14,8), %zmm17, %zmm28
+// CHECK:  encoding: [0x62,0x21,0x74,0x40,0x56,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vorps  4660(%rax,%r14,8), %zmm17, %zmm28
+
+// CHECK: vorps  (%rcx){1to16}, %zmm17, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x74,0x50,0x56,0x21]
+          vorps  (%rcx){1to16}, %zmm17, %zmm28
+
+// CHECK: vorps  8128(%rdx), %zmm17, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x74,0x40,0x56,0x62,0x7f]
+          vorps  8128(%rdx), %zmm17, %zmm28
+
+// CHECK: vorps  8192(%rdx), %zmm17, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x74,0x40,0x56,0xa2,0x00,0x20,0x00,0x00]
+          vorps  8192(%rdx), %zmm17, %zmm28
+
+// CHECK: vorps  -8192(%rdx), %zmm17, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x74,0x40,0x56,0x62,0x80]
+          vorps  -8192(%rdx), %zmm17, %zmm28
+
+// CHECK: vorps  -8256(%rdx), %zmm17, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x74,0x40,0x56,0xa2,0xc0,0xdf,0xff,0xff]
+          vorps  -8256(%rdx), %zmm17, %zmm28
+
+// CHECK: vorps  508(%rdx){1to16}, %zmm17, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x74,0x50,0x56,0x62,0x7f]
+          vorps  508(%rdx){1to16}, %zmm17, %zmm28
+
+// CHECK: vorps  512(%rdx){1to16}, %zmm17, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x74,0x50,0x56,0xa2,0x00,0x02,0x00,0x00]
+          vorps  512(%rdx){1to16}, %zmm17, %zmm28
+
+// CHECK: vorps  -512(%rdx){1to16}, %zmm17, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x74,0x50,0x56,0x62,0x80]
+          vorps  -512(%rdx){1to16}, %zmm17, %zmm28
+
+// CHECK: vorps  -516(%rdx){1to16}, %zmm17, %zmm28
+// CHECK:  encoding: [0x62,0x61,0x74,0x50,0x56,0xa2,0xfc,0xfd,0xff,0xff]
+          vorps  -516(%rdx){1to16}, %zmm17, %zmm28
+
+// CHECK: vxorpd %zmm27, %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x01,0xed,0x40,0x57,0xe3]
+          vxorpd %zmm27, %zmm18, %zmm28
+
+// CHECK: vxorpd %zmm27, %zmm18, %zmm28 {%k4}
+// CHECK:  encoding: [0x62,0x01,0xed,0x44,0x57,0xe3]
+          vxorpd %zmm27, %zmm18, %zmm28 {%k4}
+
+// CHECK: vxorpd %zmm27, %zmm18, %zmm28 {%k4} {z}
+// CHECK:  encoding: [0x62,0x01,0xed,0xc4,0x57,0xe3]
+          vxorpd %zmm27, %zmm18, %zmm28 {%k4} {z}
+
+// CHECK: vxorpd (%rcx), %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xed,0x40,0x57,0x21]
+          vxorpd (%rcx), %zmm18, %zmm28
+
+// CHECK: vxorpd 4660(%rax,%r14,8), %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x21,0xed,0x40,0x57,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vxorpd 4660(%rax,%r14,8), %zmm18, %zmm28
+
+// CHECK: vxorpd (%rcx){1to8}, %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xed,0x50,0x57,0x21]
+          vxorpd (%rcx){1to8}, %zmm18, %zmm28
+
+// CHECK: vxorpd 8128(%rdx), %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xed,0x40,0x57,0x62,0x7f]
+          vxorpd 8128(%rdx), %zmm18, %zmm28
+
+// CHECK: vxorpd 8192(%rdx), %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xed,0x40,0x57,0xa2,0x00,0x20,0x00,0x00]
+          vxorpd 8192(%rdx), %zmm18, %zmm28
+
+// CHECK: vxorpd -8192(%rdx), %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xed,0x40,0x57,0x62,0x80]
+          vxorpd -8192(%rdx), %zmm18, %zmm28
+
+// CHECK: vxorpd -8256(%rdx), %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xed,0x40,0x57,0xa2,0xc0,0xdf,0xff,0xff]
+          vxorpd -8256(%rdx), %zmm18, %zmm28
+
+// CHECK: vxorpd 1016(%rdx){1to8}, %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xed,0x50,0x57,0x62,0x7f]
+          vxorpd 1016(%rdx){1to8}, %zmm18, %zmm28
+
+// CHECK: vxorpd 1024(%rdx){1to8}, %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xed,0x50,0x57,0xa2,0x00,0x04,0x00,0x00]
+          vxorpd 1024(%rdx){1to8}, %zmm18, %zmm28
+
+// CHECK: vxorpd -1024(%rdx){1to8}, %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xed,0x50,0x57,0x62,0x80]
+          vxorpd -1024(%rdx){1to8}, %zmm18, %zmm28
+
+// CHECK: vxorpd -1032(%rdx){1to8}, %zmm18, %zmm28
+// CHECK:  encoding: [0x62,0x61,0xed,0x50,0x57,0xa2,0xf8,0xfb,0xff,0xff]
+          vxorpd -1032(%rdx){1to8}, %zmm18, %zmm28
+
+// CHECK: vxorps %zmm18, %zmm28, %zmm24
+// CHECK:  encoding: [0x62,0x21,0x1c,0x40,0x57,0xc2]
+          vxorps %zmm18, %zmm28, %zmm24
+
+// CHECK: vxorps %zmm18, %zmm28, %zmm24 {%k4}
+// CHECK:  encoding: [0x62,0x21,0x1c,0x44,0x57,0xc2]
+          vxorps %zmm18, %zmm28, %zmm24 {%k4}
+
+// CHECK: vxorps %zmm18, %zmm28, %zmm24 {%k4} {z}
+// CHECK:  encoding: [0x62,0x21,0x1c,0xc4,0x57,0xc2]
+          vxorps %zmm18, %zmm28, %zmm24 {%k4} {z}
+
+// CHECK: vxorps (%rcx), %zmm28, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x1c,0x40,0x57,0x01]
+          vxorps (%rcx), %zmm28, %zmm24
+
+// CHECK: vxorps 4660(%rax,%r14,8), %zmm28, %zmm24
+// CHECK:  encoding: [0x62,0x21,0x1c,0x40,0x57,0x84,0xf0,0x34,0x12,0x00,0x00]
+          vxorps 4660(%rax,%r14,8), %zmm28, %zmm24
+
+// CHECK: vxorps (%rcx){1to16}, %zmm28, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x1c,0x50,0x57,0x01]
+          vxorps (%rcx){1to16}, %zmm28, %zmm24
+
+// CHECK: vxorps 8128(%rdx), %zmm28, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x1c,0x40,0x57,0x42,0x7f]
+          vxorps 8128(%rdx), %zmm28, %zmm24
+
+// CHECK: vxorps 8192(%rdx), %zmm28, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x1c,0x40,0x57,0x82,0x00,0x20,0x00,0x00]
+          vxorps 8192(%rdx), %zmm28, %zmm24
+
+// CHECK: vxorps -8192(%rdx), %zmm28, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x1c,0x40,0x57,0x42,0x80]
+          vxorps -8192(%rdx), %zmm28, %zmm24
+
+// CHECK: vxorps -8256(%rdx), %zmm28, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x1c,0x40,0x57,0x82,0xc0,0xdf,0xff,0xff]
+          vxorps -8256(%rdx), %zmm28, %zmm24
+
+// CHECK: vxorps 508(%rdx){1to16}, %zmm28, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x1c,0x50,0x57,0x42,0x7f]
+          vxorps 508(%rdx){1to16}, %zmm28, %zmm24
+
+// CHECK: vxorps 512(%rdx){1to16}, %zmm28, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x1c,0x50,0x57,0x82,0x00,0x02,0x00,0x00]
+          vxorps 512(%rdx){1to16}, %zmm28, %zmm24
+
+// CHECK: vxorps -512(%rdx){1to16}, %zmm28, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x1c,0x50,0x57,0x42,0x80]
+          vxorps -512(%rdx){1to16}, %zmm28, %zmm24
+
+// CHECK: vxorps -516(%rdx){1to16}, %zmm28, %zmm24
+// CHECK:  encoding: [0x62,0x61,0x1c,0x50,0x57,0x82,0xfc,0xfd,0xff,0xff]
+          vxorps -516(%rdx){1to16}, %zmm28, %zmm24
+
+// CHECK: vinserti32x8
+// CHECK: encoding: [0x62,0xd3,0x4d,0x40,0x3a,0xdb,0x01]
+          vinserti32x8  $1, %ymm11, %zmm22, %zmm3
+
+// CHECK: vinsertf64x2
+// CHECK: encoding: [0x62,0xf3,0xed,0x48,0x18,0x4f,0x10,0x01]
+          vinsertf64x2  $1, 256(%rdi), %zmm2, %zmm1
+
+// CHECK: vbroadcastf32x8 (%rcx), %zmm30
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x1b,0x31]
+          vbroadcastf32x8 (%rcx), %zmm30
+
+// CHECK: vbroadcastf32x8 (%rcx), %zmm30 {%k3}
+// CHECK:  encoding: [0x62,0x62,0x7d,0x4b,0x1b,0x31]
+          vbroadcastf32x8 (%rcx), %zmm30 {%k3}
+
+// CHECK: vbroadcastf32x8 (%rcx), %zmm30 {%k3} {z}
+// CHECK:  encoding: [0x62,0x62,0x7d,0xcb,0x1b,0x31]
+          vbroadcastf32x8 (%rcx), %zmm30 {%k3} {z}
+
+// CHECK: vbroadcastf32x8 291(%rax,%r14,8), %zmm30
+// CHECK:  encoding: [0x62,0x22,0x7d,0x48,0x1b,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vbroadcastf32x8 291(%rax,%r14,8), %zmm30
+
+// CHECK: vbroadcastf32x8 4064(%rdx), %zmm30
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x1b,0x72,0x7f]
+          vbroadcastf32x8 4064(%rdx), %zmm30
+
+// CHECK: vbroadcastf32x8 4096(%rdx), %zmm30
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x1b,0xb2,0x00,0x10,0x00,0x00]
+          vbroadcastf32x8 4096(%rdx), %zmm30
+
+// CHECK: vbroadcastf32x8 -4096(%rdx), %zmm30
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x1b,0x72,0x80]
+          vbroadcastf32x8 -4096(%rdx), %zmm30
+
+// CHECK: vbroadcastf32x8 -4128(%rdx), %zmm30
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x1b,0xb2,0xe0,0xef,0xff,0xff]
+          vbroadcastf32x8 -4128(%rdx), %zmm30
+
+// CHECK: vbroadcastf64x2 (%rcx), %zmm28
+// CHECK:  encoding: [0x62,0x62,0xfd,0x48,0x1a,0x21]
+          vbroadcastf64x2 (%rcx), %zmm28
+
+// CHECK: vbroadcastf64x2 (%rcx), %zmm28 {%k4}
+// CHECK:  encoding: [0x62,0x62,0xfd,0x4c,0x1a,0x21]
+          vbroadcastf64x2 (%rcx), %zmm28 {%k4}
+
+// CHECK: vbroadcastf64x2 (%rcx), %zmm28 {%k4} {z}
+// CHECK:  encoding: [0x62,0x62,0xfd,0xcc,0x1a,0x21]
+          vbroadcastf64x2 (%rcx), %zmm28 {%k4} {z}
+
+// CHECK: vbroadcastf64x2 291(%rax,%r14,8), %zmm28
+// CHECK:  encoding: [0x62,0x22,0xfd,0x48,0x1a,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vbroadcastf64x2 291(%rax,%r14,8), %zmm28
+
+// CHECK: vbroadcastf64x2 2032(%rdx), %zmm28
+// CHECK:  encoding: [0x62,0x62,0xfd,0x48,0x1a,0x62,0x7f]
+          vbroadcastf64x2 2032(%rdx), %zmm28
+
+// CHECK: vbroadcastf64x2 2048(%rdx), %zmm28
+// CHECK:  encoding: [0x62,0x62,0xfd,0x48,0x1a,0xa2,0x00,0x08,0x00,0x00]
+          vbroadcastf64x2 2048(%rdx), %zmm28
+
+// CHECK: vbroadcastf64x2 -2048(%rdx), %zmm28
+// CHECK:  encoding: [0x62,0x62,0xfd,0x48,0x1a,0x62,0x80]
+          vbroadcastf64x2 -2048(%rdx), %zmm28
+
+// CHECK: vbroadcastf64x2 -2064(%rdx), %zmm28
+// CHECK:  encoding: [0x62,0x62,0xfd,0x48,0x1a,0xa2,0xf0,0xf7,0xff,0xff]
+          vbroadcastf64x2 -2064(%rdx), %zmm28
+
+// CHECK: vbroadcasti32x8 (%rcx), %zmm29
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x5b,0x29]
+          vbroadcasti32x8 (%rcx), %zmm29
+
+// CHECK: vbroadcasti32x8 (%rcx), %zmm29 {%k5}
+// CHECK:  encoding: [0x62,0x62,0x7d,0x4d,0x5b,0x29]
+          vbroadcasti32x8 (%rcx), %zmm29 {%k5}
+
+// CHECK: vbroadcasti32x8 (%rcx), %zmm29 {%k5} {z}
+// CHECK:  encoding: [0x62,0x62,0x7d,0xcd,0x5b,0x29]
+          vbroadcasti32x8 (%rcx), %zmm29 {%k5} {z}
+
+// CHECK: vbroadcasti32x8 291(%rax,%r14,8), %zmm29
+// CHECK:  encoding: [0x62,0x22,0x7d,0x48,0x5b,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vbroadcasti32x8 291(%rax,%r14,8), %zmm29
+
+// CHECK: vbroadcasti32x8 4064(%rdx), %zmm29
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x5b,0x6a,0x7f]
+          vbroadcasti32x8 4064(%rdx), %zmm29
+
+// CHECK: vbroadcasti32x8 4096(%rdx), %zmm29
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x5b,0xaa,0x00,0x10,0x00,0x00]
+          vbroadcasti32x8 4096(%rdx), %zmm29
+
+// CHECK: vbroadcasti32x8 -4096(%rdx), %zmm29
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x5b,0x6a,0x80]
+          vbroadcasti32x8 -4096(%rdx), %zmm29
+
+// CHECK: vbroadcasti32x8 -4128(%rdx), %zmm29
+// CHECK:  encoding: [0x62,0x62,0x7d,0x48,0x5b,0xaa,0xe0,0xef,0xff,0xff]
+          vbroadcasti32x8 -4128(%rdx), %zmm29
+
+// CHECK: vbroadcasti64x2 (%rcx), %zmm20
+// CHECK:  encoding: [0x62,0xe2,0xfd,0x48,0x5a,0x21]
+          vbroadcasti64x2 (%rcx), %zmm20
+
+// CHECK: vbroadcasti64x2 (%rcx), %zmm20 {%k3}
+// CHECK:  encoding: [0x62,0xe2,0xfd,0x4b,0x5a,0x21]
+          vbroadcasti64x2 (%rcx), %zmm20 {%k3}
+
+// CHECK: vbroadcasti64x2 (%rcx), %zmm20 {%k3} {z}
+// CHECK:  encoding: [0x62,0xe2,0xfd,0xcb,0x5a,0x21]
+          vbroadcasti64x2 (%rcx), %zmm20 {%k3} {z}
+
+// CHECK: vbroadcasti64x2 291(%rax,%r14,8), %zmm20
+// CHECK:  encoding: [0x62,0xa2,0xfd,0x48,0x5a,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vbroadcasti64x2 291(%rax,%r14,8), %zmm20
+
+// CHECK: vbroadcasti64x2 2032(%rdx), %zmm20
+// CHECK:  encoding: [0x62,0xe2,0xfd,0x48,0x5a,0x62,0x7f]
+          vbroadcasti64x2 2032(%rdx), %zmm20
+
+// CHECK: vbroadcasti64x2 2048(%rdx), %zmm20
+// CHECK:  encoding: [0x62,0xe2,0xfd,0x48,0x5a,0xa2,0x00,0x08,0x00,0x00]
+          vbroadcasti64x2 2048(%rdx), %zmm20
+
+// CHECK: vbroadcasti64x2 -2048(%rdx), %zmm20
+// CHECK:  encoding: [0x62,0xe2,0xfd,0x48,0x5a,0x62,0x80]
+          vbroadcasti64x2 -2048(%rdx), %zmm20
+
+// CHECK: vbroadcasti64x2 -2064(%rdx), %zmm20
+// CHECK:  encoding: [0x62,0xe2,0xfd,0x48,0x5a,0xa2,0xf0,0xf7,0xff,0xff]
+          vbroadcasti64x2 -2064(%rdx), %zmm20
diff --git a/test/MC/X86/x86-64-avx512dq_vl.s b/test/MC/X86/x86-64-avx512dq_vl.s
index 38aab78be2c3..2de4564b5f51 100644
--- a/test/MC/X86/x86-64-avx512dq_vl.s
+++ b/test/MC/X86/x86-64-avx512dq_vl.s
@@ -111,3 +111,1860 @@
 // CHECK: vpmullq -1032(%rdx){1to4}, %ymm25, %ymm25
 // CHECK:  encoding: [0x62,0x62,0xb5,0x30,0x40,0x8a,0xf8,0xfb,0xff,0xff]
           vpmullq -1032(%rdx){1to4}, %ymm25, %ymm25
+
+// CHECK: vandpd %xmm20, %xmm29, %xmm21
+// CHECK:  encoding: [0x62,0xa1,0x95,0x00,0x54,0xec]
+          vandpd %xmm20, %xmm29, %xmm21
+
+// CHECK: vandpd %xmm20, %xmm29, %xmm21 {%k6}
+// CHECK:  encoding: [0x62,0xa1,0x95,0x06,0x54,0xec]
+          vandpd %xmm20, %xmm29, %xmm21 {%k6}
+
+// CHECK: vandpd %xmm20, %xmm29, %xmm21 {%k6} {z}
+// CHECK:  encoding: [0x62,0xa1,0x95,0x86,0x54,0xec]
+          vandpd %xmm20, %xmm29, %xmm21 {%k6} {z}
+
+// CHECK: vandpd (%rcx), %xmm29, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x95,0x00,0x54,0x29]
+          vandpd (%rcx), %xmm29, %xmm21
+
+// CHECK: vandpd 291(%rax,%r14,8), %xmm29, %xmm21
+// CHECK:  encoding: [0x62,0xa1,0x95,0x00,0x54,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vandpd 291(%rax,%r14,8), %xmm29, %xmm21
+
+// CHECK: vandpd (%rcx){1to2}, %xmm29, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x95,0x10,0x54,0x29]
+          vandpd (%rcx){1to2}, %xmm29, %xmm21
+
+// CHECK: vandpd 2032(%rdx), %xmm29, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x95,0x00,0x54,0x6a,0x7f]
+          vandpd 2032(%rdx), %xmm29, %xmm21
+
+// CHECK: vandpd 2048(%rdx), %xmm29, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x95,0x00,0x54,0xaa,0x00,0x08,0x00,0x00]
+          vandpd 2048(%rdx), %xmm29, %xmm21
+
+// CHECK: vandpd -2048(%rdx), %xmm29, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x95,0x00,0x54,0x6a,0x80]
+          vandpd -2048(%rdx), %xmm29, %xmm21
+
+// CHECK: vandpd -2064(%rdx), %xmm29, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x95,0x00,0x54,0xaa,0xf0,0xf7,0xff,0xff]
+          vandpd -2064(%rdx), %xmm29, %xmm21
+
+// CHECK: vandpd 1016(%rdx){1to2}, %xmm29, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x95,0x10,0x54,0x6a,0x7f]
+          vandpd 1016(%rdx){1to2}, %xmm29, %xmm21
+
+// CHECK: vandpd 1024(%rdx){1to2}, %xmm29, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x95,0x10,0x54,0xaa,0x00,0x04,0x00,0x00]
+          vandpd 1024(%rdx){1to2}, %xmm29, %xmm21
+
+// CHECK: vandpd -1024(%rdx){1to2}, %xmm29, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x95,0x10,0x54,0x6a,0x80]
+          vandpd -1024(%rdx){1to2}, %xmm29, %xmm21
+
+// CHECK: vandpd -1032(%rdx){1to2}, %xmm29, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x95,0x10,0x54,0xaa,0xf8,0xfb,0xff,0xff]
+          vandpd -1032(%rdx){1to2}, %xmm29, %xmm21
+
+// CHECK: vandpd %ymm28, %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x01,0xd5,0x20,0x54,0xe4]
+          vandpd %ymm28, %ymm21, %ymm28
+
+// CHECK: vandpd %ymm28, %ymm21, %ymm28 {%k4}
+// CHECK:  encoding: [0x62,0x01,0xd5,0x24,0x54,0xe4]
+          vandpd %ymm28, %ymm21, %ymm28 {%k4}
+
+// CHECK: vandpd %ymm28, %ymm21, %ymm28 {%k4} {z}
+// CHECK:  encoding: [0x62,0x01,0xd5,0xa4,0x54,0xe4]
+          vandpd %ymm28, %ymm21, %ymm28 {%k4} {z}
+
+// CHECK: vandpd (%rcx), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xd5,0x20,0x54,0x21]
+          vandpd (%rcx), %ymm21, %ymm28
+
+// CHECK: vandpd 291(%rax,%r14,8), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x21,0xd5,0x20,0x54,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vandpd 291(%rax,%r14,8), %ymm21, %ymm28
+
+// CHECK: vandpd (%rcx){1to4}, %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xd5,0x30,0x54,0x21]
+          vandpd (%rcx){1to4}, %ymm21, %ymm28
+
+// CHECK: vandpd 4064(%rdx), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xd5,0x20,0x54,0x62,0x7f]
+          vandpd 4064(%rdx), %ymm21, %ymm28
+
+// CHECK: vandpd 4096(%rdx), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xd5,0x20,0x54,0xa2,0x00,0x10,0x00,0x00]
+          vandpd 4096(%rdx), %ymm21, %ymm28
+
+// CHECK: vandpd -4096(%rdx), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xd5,0x20,0x54,0x62,0x80]
+          vandpd -4096(%rdx), %ymm21, %ymm28
+
+// CHECK: vandpd -4128(%rdx), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xd5,0x20,0x54,0xa2,0xe0,0xef,0xff,0xff]
+          vandpd -4128(%rdx), %ymm21, %ymm28
+
+// CHECK: vandpd 1016(%rdx){1to4}, %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xd5,0x30,0x54,0x62,0x7f]
+          vandpd 1016(%rdx){1to4}, %ymm21, %ymm28
+
+// CHECK: vandpd 1024(%rdx){1to4}, %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xd5,0x30,0x54,0xa2,0x00,0x04,0x00,0x00]
+          vandpd 1024(%rdx){1to4}, %ymm21, %ymm28
+
+// CHECK: vandpd -1024(%rdx){1to4}, %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xd5,0x30,0x54,0x62,0x80]
+          vandpd -1024(%rdx){1to4}, %ymm21, %ymm28
+
+// CHECK: vandpd -1032(%rdx){1to4}, %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xd5,0x30,0x54,0xa2,0xf8,0xfb,0xff,0xff]
+          vandpd -1032(%rdx){1to4}, %ymm21, %ymm28
+
+// CHECK: vandps %xmm24, %xmm21, %xmm23
+// CHECK:  encoding: [0x62,0x81,0x54,0x00,0x54,0xf8]
+          vandps %xmm24, %xmm21, %xmm23
+
+// CHECK: vandps %xmm24, %xmm21, %xmm23 {%k5}
+// CHECK:  encoding: [0x62,0x81,0x54,0x05,0x54,0xf8]
+          vandps %xmm24, %xmm21, %xmm23 {%k5}
+
+// CHECK: vandps %xmm24, %xmm21, %xmm23 {%k5} {z}
+// CHECK:  encoding: [0x62,0x81,0x54,0x85,0x54,0xf8]
+          vandps %xmm24, %xmm21, %xmm23 {%k5} {z}
+
+// CHECK: vandps (%rcx), %xmm21, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x54,0x00,0x54,0x39]
+          vandps (%rcx), %xmm21, %xmm23
+
+// CHECK: vandps 291(%rax,%r14,8), %xmm21, %xmm23
+// CHECK:  encoding: [0x62,0xa1,0x54,0x00,0x54,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vandps 291(%rax,%r14,8), %xmm21, %xmm23
+
+// CHECK: vandps (%rcx){1to4}, %xmm21, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x54,0x10,0x54,0x39]
+          vandps (%rcx){1to4}, %xmm21, %xmm23
+
+// CHECK: vandps 2032(%rdx), %xmm21, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x54,0x00,0x54,0x7a,0x7f]
+          vandps 2032(%rdx), %xmm21, %xmm23
+
+// CHECK: vandps 2048(%rdx), %xmm21, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x54,0x00,0x54,0xba,0x00,0x08,0x00,0x00]
+          vandps 2048(%rdx), %xmm21, %xmm23
+
+// CHECK: vandps -2048(%rdx), %xmm21, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x54,0x00,0x54,0x7a,0x80]
+          vandps -2048(%rdx), %xmm21, %xmm23
+
+// CHECK: vandps -2064(%rdx), %xmm21, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x54,0x00,0x54,0xba,0xf0,0xf7,0xff,0xff]
+          vandps -2064(%rdx), %xmm21, %xmm23
+
+// CHECK: vandps 508(%rdx){1to4}, %xmm21, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x54,0x10,0x54,0x7a,0x7f]
+          vandps 508(%rdx){1to4}, %xmm21, %xmm23
+
+// CHECK: vandps 512(%rdx){1to4}, %xmm21, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x54,0x10,0x54,0xba,0x00,0x02,0x00,0x00]
+          vandps 512(%rdx){1to4}, %xmm21, %xmm23
+
+// CHECK: vandps -512(%rdx){1to4}, %xmm21, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x54,0x10,0x54,0x7a,0x80]
+          vandps -512(%rdx){1to4}, %xmm21, %xmm23
+
+// CHECK: vandps -516(%rdx){1to4}, %xmm21, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0x54,0x10,0x54,0xba,0xfc,0xfd,0xff,0xff]
+          vandps -516(%rdx){1to4}, %xmm21, %xmm23
+
+// CHECK: vandps %ymm23, %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x21,0x6c,0x20,0x54,0xd7]
+          vandps %ymm23, %ymm18, %ymm26
+
+// CHECK: vandps %ymm23, %ymm18, %ymm26 {%k6}
+// CHECK:  encoding: [0x62,0x21,0x6c,0x26,0x54,0xd7]
+          vandps %ymm23, %ymm18, %ymm26 {%k6}
+
+// CHECK: vandps %ymm23, %ymm18, %ymm26 {%k6} {z}
+// CHECK:  encoding: [0x62,0x21,0x6c,0xa6,0x54,0xd7]
+          vandps %ymm23, %ymm18, %ymm26 {%k6} {z}
+
+// CHECK: vandps (%rcx), %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x6c,0x20,0x54,0x11]
+          vandps (%rcx), %ymm18, %ymm26
+
+// CHECK: vandps 291(%rax,%r14,8), %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x21,0x6c,0x20,0x54,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vandps 291(%rax,%r14,8), %ymm18, %ymm26
+
+// CHECK: vandps (%rcx){1to8}, %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x6c,0x30,0x54,0x11]
+          vandps (%rcx){1to8}, %ymm18, %ymm26
+
+// CHECK: vandps 4064(%rdx), %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x6c,0x20,0x54,0x52,0x7f]
+          vandps 4064(%rdx), %ymm18, %ymm26
+
+// CHECK: vandps 4096(%rdx), %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x6c,0x20,0x54,0x92,0x00,0x10,0x00,0x00]
+          vandps 4096(%rdx), %ymm18, %ymm26
+
+// CHECK: vandps -4096(%rdx), %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x6c,0x20,0x54,0x52,0x80]
+          vandps -4096(%rdx), %ymm18, %ymm26
+
+// CHECK: vandps -4128(%rdx), %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x6c,0x20,0x54,0x92,0xe0,0xef,0xff,0xff]
+          vandps -4128(%rdx), %ymm18, %ymm26
+
+// CHECK: vandps 508(%rdx){1to8}, %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x6c,0x30,0x54,0x52,0x7f]
+          vandps 508(%rdx){1to8}, %ymm18, %ymm26
+
+// CHECK: vandps 512(%rdx){1to8}, %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x6c,0x30,0x54,0x92,0x00,0x02,0x00,0x00]
+          vandps 512(%rdx){1to8}, %ymm18, %ymm26
+
+// CHECK: vandps -512(%rdx){1to8}, %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x6c,0x30,0x54,0x52,0x80]
+          vandps -512(%rdx){1to8}, %ymm18, %ymm26
+
+// CHECK: vandps -516(%rdx){1to8}, %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x6c,0x30,0x54,0x92,0xfc,0xfd,0xff,0xff]
+          vandps -516(%rdx){1to8}, %ymm18, %ymm26
+
+// CHECK: vandnpd %xmm25, %xmm27, %xmm25
+// CHECK:  encoding: [0x62,0x01,0xa5,0x00,0x55,0xc9]
+          vandnpd %xmm25, %xmm27, %xmm25
+
+// CHECK: vandnpd %xmm25, %xmm27, %xmm25 {%k5}
+// CHECK:  encoding: [0x62,0x01,0xa5,0x05,0x55,0xc9]
+          vandnpd %xmm25, %xmm27, %xmm25 {%k5}
+
+// CHECK: vandnpd %xmm25, %xmm27, %xmm25 {%k5} {z}
+// CHECK:  encoding: [0x62,0x01,0xa5,0x85,0x55,0xc9]
+          vandnpd %xmm25, %xmm27, %xmm25 {%k5} {z}
+
+// CHECK: vandnpd (%rcx), %xmm27, %xmm25
+// CHECK:  encoding: [0x62,0x61,0xa5,0x00,0x55,0x09]
+          vandnpd (%rcx), %xmm27, %xmm25
+
+// CHECK: vandnpd 291(%rax,%r14,8), %xmm27, %xmm25
+// CHECK:  encoding: [0x62,0x21,0xa5,0x00,0x55,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vandnpd 291(%rax,%r14,8), %xmm27, %xmm25
+
+// CHECK: vandnpd (%rcx){1to2}, %xmm27, %xmm25
+// CHECK:  encoding: [0x62,0x61,0xa5,0x10,0x55,0x09]
+          vandnpd (%rcx){1to2}, %xmm27, %xmm25
+
+// CHECK: vandnpd 2032(%rdx), %xmm27, %xmm25
+// CHECK:  encoding: [0x62,0x61,0xa5,0x00,0x55,0x4a,0x7f]
+          vandnpd 2032(%rdx), %xmm27, %xmm25
+
+// CHECK: vandnpd 2048(%rdx), %xmm27, %xmm25
+// CHECK:  encoding: [0x62,0x61,0xa5,0x00,0x55,0x8a,0x00,0x08,0x00,0x00]
+          vandnpd 2048(%rdx), %xmm27, %xmm25
+
+// CHECK: vandnpd -2048(%rdx), %xmm27, %xmm25
+// CHECK:  encoding: [0x62,0x61,0xa5,0x00,0x55,0x4a,0x80]
+          vandnpd -2048(%rdx), %xmm27, %xmm25
+
+// CHECK: vandnpd -2064(%rdx), %xmm27, %xmm25
+// CHECK:  encoding: [0x62,0x61,0xa5,0x00,0x55,0x8a,0xf0,0xf7,0xff,0xff]
+          vandnpd -2064(%rdx), %xmm27, %xmm25
+
+// CHECK: vandnpd 1016(%rdx){1to2}, %xmm27, %xmm25
+// CHECK:  encoding: [0x62,0x61,0xa5,0x10,0x55,0x4a,0x7f]
+          vandnpd 1016(%rdx){1to2}, %xmm27, %xmm25
+
+// CHECK: vandnpd 1024(%rdx){1to2}, %xmm27, %xmm25
+// CHECK:  encoding: [0x62,0x61,0xa5,0x10,0x55,0x8a,0x00,0x04,0x00,0x00]
+          vandnpd 1024(%rdx){1to2}, %xmm27, %xmm25
+
+// CHECK: vandnpd -1024(%rdx){1to2}, %xmm27, %xmm25
+// CHECK:  encoding: [0x62,0x61,0xa5,0x10,0x55,0x4a,0x80]
+          vandnpd -1024(%rdx){1to2}, %xmm27, %xmm25
+
+// CHECK: vandnpd -1032(%rdx){1to2}, %xmm27, %xmm25
+// CHECK:  encoding: [0x62,0x61,0xa5,0x10,0x55,0x8a,0xf8,0xfb,0xff,0xff]
+          vandnpd -1032(%rdx){1to2}, %xmm27, %xmm25
+
+// CHECK: vandnpd %ymm22, %ymm18, %ymm22
+// CHECK:  encoding: [0x62,0xa1,0xed,0x20,0x55,0xf6]
+          vandnpd %ymm22, %ymm18, %ymm22
+
+// CHECK: vandnpd %ymm22, %ymm18, %ymm22 {%k7}
+// CHECK:  encoding: [0x62,0xa1,0xed,0x27,0x55,0xf6]
+          vandnpd %ymm22, %ymm18, %ymm22 {%k7}
+
+// CHECK: vandnpd %ymm22, %ymm18, %ymm22 {%k7} {z}
+// CHECK:  encoding: [0x62,0xa1,0xed,0xa7,0x55,0xf6]
+          vandnpd %ymm22, %ymm18, %ymm22 {%k7} {z}
+
+// CHECK: vandnpd (%rcx), %ymm18, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xed,0x20,0x55,0x31]
+          vandnpd (%rcx), %ymm18, %ymm22
+
+// CHECK: vandnpd 291(%rax,%r14,8), %ymm18, %ymm22
+// CHECK:  encoding: [0x62,0xa1,0xed,0x20,0x55,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vandnpd 291(%rax,%r14,8), %ymm18, %ymm22
+
+// CHECK: vandnpd (%rcx){1to4}, %ymm18, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xed,0x30,0x55,0x31]
+          vandnpd (%rcx){1to4}, %ymm18, %ymm22
+
+// CHECK: vandnpd 4064(%rdx), %ymm18, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xed,0x20,0x55,0x72,0x7f]
+          vandnpd 4064(%rdx), %ymm18, %ymm22
+
+// CHECK: vandnpd 4096(%rdx), %ymm18, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xed,0x20,0x55,0xb2,0x00,0x10,0x00,0x00]
+          vandnpd 4096(%rdx), %ymm18, %ymm22
+
+// CHECK: vandnpd -4096(%rdx), %ymm18, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xed,0x20,0x55,0x72,0x80]
+          vandnpd -4096(%rdx), %ymm18, %ymm22
+
+// CHECK: vandnpd -4128(%rdx), %ymm18, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xed,0x20,0x55,0xb2,0xe0,0xef,0xff,0xff]
+          vandnpd -4128(%rdx), %ymm18, %ymm22
+
+// CHECK: vandnpd 1016(%rdx){1to4}, %ymm18, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xed,0x30,0x55,0x72,0x7f]
+          vandnpd 1016(%rdx){1to4}, %ymm18, %ymm22
+
+// CHECK: vandnpd 1024(%rdx){1to4}, %ymm18, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xed,0x30,0x55,0xb2,0x00,0x04,0x00,0x00]
+          vandnpd 1024(%rdx){1to4}, %ymm18, %ymm22
+
+// CHECK: vandnpd -1024(%rdx){1to4}, %ymm18, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xed,0x30,0x55,0x72,0x80]
+          vandnpd -1024(%rdx){1to4}, %ymm18, %ymm22
+
+// CHECK: vandnpd -1032(%rdx){1to4}, %ymm18, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xed,0x30,0x55,0xb2,0xf8,0xfb,0xff,0xff]
+          vandnpd -1032(%rdx){1to4}, %ymm18, %ymm22
+
+// CHECK: vandnps %xmm27, %xmm21, %xmm21
+// CHECK:  encoding: [0x62,0x81,0x54,0x00,0x55,0xeb]
+          vandnps %xmm27, %xmm21, %xmm21
+
+// CHECK: vandnps %xmm27, %xmm21, %xmm21 {%k2}
+// CHECK:  encoding: [0x62,0x81,0x54,0x02,0x55,0xeb]
+          vandnps %xmm27, %xmm21, %xmm21 {%k2}
+
+// CHECK: vandnps %xmm27, %xmm21, %xmm21 {%k2} {z}
+// CHECK:  encoding: [0x62,0x81,0x54,0x82,0x55,0xeb]
+          vandnps %xmm27, %xmm21, %xmm21 {%k2} {z}
+
+// CHECK: vandnps (%rcx), %xmm21, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x54,0x00,0x55,0x29]
+          vandnps (%rcx), %xmm21, %xmm21
+
+// CHECK: vandnps 291(%rax,%r14,8), %xmm21, %xmm21
+// CHECK:  encoding: [0x62,0xa1,0x54,0x00,0x55,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vandnps 291(%rax,%r14,8), %xmm21, %xmm21
+
+// CHECK: vandnps (%rcx){1to4}, %xmm21, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x54,0x10,0x55,0x29]
+          vandnps (%rcx){1to4}, %xmm21, %xmm21
+
+// CHECK: vandnps 2032(%rdx), %xmm21, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x54,0x00,0x55,0x6a,0x7f]
+          vandnps 2032(%rdx), %xmm21, %xmm21
+
+// CHECK: vandnps 2048(%rdx), %xmm21, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x54,0x00,0x55,0xaa,0x00,0x08,0x00,0x00]
+          vandnps 2048(%rdx), %xmm21, %xmm21
+
+// CHECK: vandnps -2048(%rdx), %xmm21, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x54,0x00,0x55,0x6a,0x80]
+          vandnps -2048(%rdx), %xmm21, %xmm21
+
+// CHECK: vandnps -2064(%rdx), %xmm21, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x54,0x00,0x55,0xaa,0xf0,0xf7,0xff,0xff]
+          vandnps -2064(%rdx), %xmm21, %xmm21
+
+// CHECK: vandnps 508(%rdx){1to4}, %xmm21, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x54,0x10,0x55,0x6a,0x7f]
+          vandnps 508(%rdx){1to4}, %xmm21, %xmm21
+
+// CHECK: vandnps 512(%rdx){1to4}, %xmm21, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x54,0x10,0x55,0xaa,0x00,0x02,0x00,0x00]
+          vandnps 512(%rdx){1to4}, %xmm21, %xmm21
+
+// CHECK: vandnps -512(%rdx){1to4}, %xmm21, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x54,0x10,0x55,0x6a,0x80]
+          vandnps -512(%rdx){1to4}, %xmm21, %xmm21
+
+// CHECK: vandnps -516(%rdx){1to4}, %xmm21, %xmm21
+// CHECK:  encoding: [0x62,0xe1,0x54,0x10,0x55,0xaa,0xfc,0xfd,0xff,0xff]
+          vandnps -516(%rdx){1to4}, %xmm21, %xmm21
+
+// CHECK: vandnps %ymm25, %ymm23, %ymm19
+// CHECK:  encoding: [0x62,0x81,0x44,0x20,0x55,0xd9]
+          vandnps %ymm25, %ymm23, %ymm19
+
+// CHECK: vandnps %ymm25, %ymm23, %ymm19 {%k1}
+// CHECK:  encoding: [0x62,0x81,0x44,0x21,0x55,0xd9]
+          vandnps %ymm25, %ymm23, %ymm19 {%k1}
+
+// CHECK: vandnps %ymm25, %ymm23, %ymm19 {%k1} {z}
+// CHECK:  encoding: [0x62,0x81,0x44,0xa1,0x55,0xd9]
+          vandnps %ymm25, %ymm23, %ymm19 {%k1} {z}
+
+// CHECK: vandnps (%rcx), %ymm23, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x44,0x20,0x55,0x19]
+          vandnps (%rcx), %ymm23, %ymm19
+
+// CHECK: vandnps 291(%rax,%r14,8), %ymm23, %ymm19
+// CHECK:  encoding: [0x62,0xa1,0x44,0x20,0x55,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vandnps 291(%rax,%r14,8), %ymm23, %ymm19
+
+// CHECK: vandnps (%rcx){1to8}, %ymm23, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x44,0x30,0x55,0x19]
+          vandnps (%rcx){1to8}, %ymm23, %ymm19
+
+// CHECK: vandnps 4064(%rdx), %ymm23, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x44,0x20,0x55,0x5a,0x7f]
+          vandnps 4064(%rdx), %ymm23, %ymm19
+
+// CHECK: vandnps 4096(%rdx), %ymm23, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x44,0x20,0x55,0x9a,0x00,0x10,0x00,0x00]
+          vandnps 4096(%rdx), %ymm23, %ymm19
+
+// CHECK: vandnps -4096(%rdx), %ymm23, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x44,0x20,0x55,0x5a,0x80]
+          vandnps -4096(%rdx), %ymm23, %ymm19
+
+// CHECK: vandnps -4128(%rdx), %ymm23, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x44,0x20,0x55,0x9a,0xe0,0xef,0xff,0xff]
+          vandnps -4128(%rdx), %ymm23, %ymm19
+
+// CHECK: vandnps 508(%rdx){1to8}, %ymm23, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x44,0x30,0x55,0x5a,0x7f]
+          vandnps 508(%rdx){1to8}, %ymm23, %ymm19
+
+// CHECK: vandnps 512(%rdx){1to8}, %ymm23, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x44,0x30,0x55,0x9a,0x00,0x02,0x00,0x00]
+          vandnps 512(%rdx){1to8}, %ymm23, %ymm19
+
+// CHECK: vandnps -512(%rdx){1to8}, %ymm23, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x44,0x30,0x55,0x5a,0x80]
+          vandnps -512(%rdx){1to8}, %ymm23, %ymm19
+
+// CHECK: vandnps -516(%rdx){1to8}, %ymm23, %ymm19
+// CHECK:  encoding: [0x62,0xe1,0x44,0x30,0x55,0x9a,0xfc,0xfd,0xff,0xff]
+          vandnps -516(%rdx){1to8}, %ymm23, %ymm19
+
+// CHECK: vorpd  %xmm18, %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xa1,0xa5,0x00,0x56,0xfa]
+          vorpd  %xmm18, %xmm27, %xmm23
+
+// CHECK: vorpd  %xmm18, %xmm27, %xmm23 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0xa5,0x01,0x56,0xfa]
+          vorpd  %xmm18, %xmm27, %xmm23 {%k1}
+
+// CHECK: vorpd  %xmm18, %xmm27, %xmm23 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0xa5,0x81,0x56,0xfa]
+          vorpd  %xmm18, %xmm27, %xmm23 {%k1} {z}
+
+// CHECK: vorpd  (%rcx), %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0xa5,0x00,0x56,0x39]
+          vorpd  (%rcx), %xmm27, %xmm23
+
+// CHECK: vorpd  291(%rax,%r14,8), %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xa1,0xa5,0x00,0x56,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vorpd  291(%rax,%r14,8), %xmm27, %xmm23
+
+// CHECK: vorpd  (%rcx){1to2}, %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0xa5,0x10,0x56,0x39]
+          vorpd  (%rcx){1to2}, %xmm27, %xmm23
+
+// CHECK: vorpd  2032(%rdx), %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0xa5,0x00,0x56,0x7a,0x7f]
+          vorpd  2032(%rdx), %xmm27, %xmm23
+
+// CHECK: vorpd  2048(%rdx), %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0xa5,0x00,0x56,0xba,0x00,0x08,0x00,0x00]
+          vorpd  2048(%rdx), %xmm27, %xmm23
+
+// CHECK: vorpd  -2048(%rdx), %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0xa5,0x00,0x56,0x7a,0x80]
+          vorpd  -2048(%rdx), %xmm27, %xmm23
+
+// CHECK: vorpd  -2064(%rdx), %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0xa5,0x00,0x56,0xba,0xf0,0xf7,0xff,0xff]
+          vorpd  -2064(%rdx), %xmm27, %xmm23
+
+// CHECK: vorpd  1016(%rdx){1to2}, %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0xa5,0x10,0x56,0x7a,0x7f]
+          vorpd  1016(%rdx){1to2}, %xmm27, %xmm23
+
+// CHECK: vorpd  1024(%rdx){1to2}, %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0xa5,0x10,0x56,0xba,0x00,0x04,0x00,0x00]
+          vorpd  1024(%rdx){1to2}, %xmm27, %xmm23
+
+// CHECK: vorpd  -1024(%rdx){1to2}, %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0xa5,0x10,0x56,0x7a,0x80]
+          vorpd  -1024(%rdx){1to2}, %xmm27, %xmm23
+
+// CHECK: vorpd  -1032(%rdx){1to2}, %xmm27, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0xa5,0x10,0x56,0xba,0xf8,0xfb,0xff,0xff]
+          vorpd  -1032(%rdx){1to2}, %xmm27, %xmm23
+
+// CHECK: vorpd  %ymm20, %ymm29, %ymm26
+// CHECK:  encoding: [0x62,0x21,0x95,0x20,0x56,0xd4]
+          vorpd  %ymm20, %ymm29, %ymm26
+
+// CHECK: vorpd  %ymm20, %ymm29, %ymm26 {%k5}
+// CHECK:  encoding: [0x62,0x21,0x95,0x25,0x56,0xd4]
+          vorpd  %ymm20, %ymm29, %ymm26 {%k5}
+
+// CHECK: vorpd  %ymm20, %ymm29, %ymm26 {%k5} {z}
+// CHECK:  encoding: [0x62,0x21,0x95,0xa5,0x56,0xd4]
+          vorpd  %ymm20, %ymm29, %ymm26 {%k5} {z}
+
+// CHECK: vorpd  (%rcx), %ymm29, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x56,0x11]
+          vorpd  (%rcx), %ymm29, %ymm26
+
+// CHECK: vorpd  291(%rax,%r14,8), %ymm29, %ymm26
+// CHECK:  encoding: [0x62,0x21,0x95,0x20,0x56,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vorpd  291(%rax,%r14,8), %ymm29, %ymm26
+
+// CHECK: vorpd  (%rcx){1to4}, %ymm29, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x56,0x11]
+          vorpd  (%rcx){1to4}, %ymm29, %ymm26
+
+// CHECK: vorpd  4064(%rdx), %ymm29, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x56,0x52,0x7f]
+          vorpd  4064(%rdx), %ymm29, %ymm26
+
+// CHECK: vorpd  4096(%rdx), %ymm29, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x56,0x92,0x00,0x10,0x00,0x00]
+          vorpd  4096(%rdx), %ymm29, %ymm26
+
+// CHECK: vorpd  -4096(%rdx), %ymm29, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x56,0x52,0x80]
+          vorpd  -4096(%rdx), %ymm29, %ymm26
+
+// CHECK: vorpd  -4128(%rdx), %ymm29, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x56,0x92,0xe0,0xef,0xff,0xff]
+          vorpd  -4128(%rdx), %ymm29, %ymm26
+
+// CHECK: vorpd  1016(%rdx){1to4}, %ymm29, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x56,0x52,0x7f]
+          vorpd  1016(%rdx){1to4}, %ymm29, %ymm26
+
+// CHECK: vorpd  1024(%rdx){1to4}, %ymm29, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x56,0x92,0x00,0x04,0x00,0x00]
+          vorpd  1024(%rdx){1to4}, %ymm29, %ymm26
+
+// CHECK: vorpd  -1024(%rdx){1to4}, %ymm29, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x56,0x52,0x80]
+          vorpd  -1024(%rdx){1to4}, %ymm29, %ymm26
+
+// CHECK: vorpd  -1032(%rdx){1to4}, %ymm29, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x56,0x92,0xf8,0xfb,0xff,0xff]
+          vorpd  -1032(%rdx){1to4}, %ymm29, %ymm26
+
+// CHECK: vorps  %xmm27, %xmm28, %xmm19
+// CHECK:  encoding: [0x62,0x81,0x1c,0x00,0x56,0xdb]
+          vorps  %xmm27, %xmm28, %xmm19
+
+// CHECK: vorps  %xmm27, %xmm28, %xmm19 {%k4}
+// CHECK:  encoding: [0x62,0x81,0x1c,0x04,0x56,0xdb]
+          vorps  %xmm27, %xmm28, %xmm19 {%k4}
+
+// CHECK: vorps  %xmm27, %xmm28, %xmm19 {%k4} {z}
+// CHECK:  encoding: [0x62,0x81,0x1c,0x84,0x56,0xdb]
+          vorps  %xmm27, %xmm28, %xmm19 {%k4} {z}
+
+// CHECK: vorps  (%rcx), %xmm28, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x1c,0x00,0x56,0x19]
+          vorps  (%rcx), %xmm28, %xmm19
+
+// CHECK: vorps  291(%rax,%r14,8), %xmm28, %xmm19
+// CHECK:  encoding: [0x62,0xa1,0x1c,0x00,0x56,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vorps  291(%rax,%r14,8), %xmm28, %xmm19
+
+// CHECK: vorps  (%rcx){1to4}, %xmm28, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x1c,0x10,0x56,0x19]
+          vorps  (%rcx){1to4}, %xmm28, %xmm19
+
+// CHECK: vorps  2032(%rdx), %xmm28, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x1c,0x00,0x56,0x5a,0x7f]
+          vorps  2032(%rdx), %xmm28, %xmm19
+
+// CHECK: vorps  2048(%rdx), %xmm28, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x1c,0x00,0x56,0x9a,0x00,0x08,0x00,0x00]
+          vorps  2048(%rdx), %xmm28, %xmm19
+
+// CHECK: vorps  -2048(%rdx), %xmm28, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x1c,0x00,0x56,0x5a,0x80]
+          vorps  -2048(%rdx), %xmm28, %xmm19
+
+// CHECK: vorps  -2064(%rdx), %xmm28, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x1c,0x00,0x56,0x9a,0xf0,0xf7,0xff,0xff]
+          vorps  -2064(%rdx), %xmm28, %xmm19
+
+// CHECK: vorps  508(%rdx){1to4}, %xmm28, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x1c,0x10,0x56,0x5a,0x7f]
+          vorps  508(%rdx){1to4}, %xmm28, %xmm19
+
+// CHECK: vorps  512(%rdx){1to4}, %xmm28, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x1c,0x10,0x56,0x9a,0x00,0x02,0x00,0x00]
+          vorps  512(%rdx){1to4}, %xmm28, %xmm19
+
+// CHECK: vorps  -512(%rdx){1to4}, %xmm28, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x1c,0x10,0x56,0x5a,0x80]
+          vorps  -512(%rdx){1to4}, %xmm28, %xmm19
+
+// CHECK: vorps  -516(%rdx){1to4}, %xmm28, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0x1c,0x10,0x56,0x9a,0xfc,0xfd,0xff,0xff]
+          vorps  -516(%rdx){1to4}, %xmm28, %xmm19
+
+// CHECK: vorps  %ymm26, %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x01,0x2c,0x20,0x56,0xda]
+          vorps  %ymm26, %ymm26, %ymm27
+
+// CHECK: vorps  %ymm26, %ymm26, %ymm27 {%k1}
+// CHECK:  encoding: [0x62,0x01,0x2c,0x21,0x56,0xda]
+          vorps  %ymm26, %ymm26, %ymm27 {%k1}
+
+// CHECK: vorps  %ymm26, %ymm26, %ymm27 {%k1} {z}
+// CHECK:  encoding: [0x62,0x01,0x2c,0xa1,0x56,0xda]
+          vorps  %ymm26, %ymm26, %ymm27 {%k1} {z}
+
+// CHECK: vorps  (%rcx), %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x2c,0x20,0x56,0x19]
+          vorps  (%rcx), %ymm26, %ymm27
+
+// CHECK: vorps  291(%rax,%r14,8), %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x21,0x2c,0x20,0x56,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vorps  291(%rax,%r14,8), %ymm26, %ymm27
+
+// CHECK: vorps  (%rcx){1to8}, %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x2c,0x30,0x56,0x19]
+          vorps  (%rcx){1to8}, %ymm26, %ymm27
+
+// CHECK: vorps  4064(%rdx), %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x2c,0x20,0x56,0x5a,0x7f]
+          vorps  4064(%rdx), %ymm26, %ymm27
+
+// CHECK: vorps  4096(%rdx), %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x2c,0x20,0x56,0x9a,0x00,0x10,0x00,0x00]
+          vorps  4096(%rdx), %ymm26, %ymm27
+
+// CHECK: vorps  -4096(%rdx), %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x2c,0x20,0x56,0x5a,0x80]
+          vorps  -4096(%rdx), %ymm26, %ymm27
+
+// CHECK: vorps  -4128(%rdx), %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x2c,0x20,0x56,0x9a,0xe0,0xef,0xff,0xff]
+          vorps  -4128(%rdx), %ymm26, %ymm27
+
+// CHECK: vorps  508(%rdx){1to8}, %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x2c,0x30,0x56,0x5a,0x7f]
+          vorps  508(%rdx){1to8}, %ymm26, %ymm27
+
+// CHECK: vorps  512(%rdx){1to8}, %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x2c,0x30,0x56,0x9a,0x00,0x02,0x00,0x00]
+          vorps  512(%rdx){1to8}, %ymm26, %ymm27
+
+// CHECK: vorps  -512(%rdx){1to8}, %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x2c,0x30,0x56,0x5a,0x80]
+          vorps  -512(%rdx){1to8}, %ymm26, %ymm27
+
+// CHECK: vorps  -516(%rdx){1to8}, %ymm26, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x2c,0x30,0x56,0x9a,0xfc,0xfd,0xff,0xff]
+          vorps  -516(%rdx){1to8}, %ymm26, %ymm27
+
+// CHECK: vxorpd %xmm23, %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xa1,0xd5,0x00,0x57,0xd7]
+          vxorpd %xmm23, %xmm21, %xmm18
+
+// CHECK: vxorpd %xmm23, %xmm21, %xmm18 {%k2}
+// CHECK:  encoding: [0x62,0xa1,0xd5,0x02,0x57,0xd7]
+          vxorpd %xmm23, %xmm21, %xmm18 {%k2}
+
+// CHECK: vxorpd %xmm23, %xmm21, %xmm18 {%k2} {z}
+// CHECK:  encoding: [0x62,0xa1,0xd5,0x82,0x57,0xd7]
+          vxorpd %xmm23, %xmm21, %xmm18 {%k2} {z}
+
+// CHECK: vxorpd (%rcx), %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x00,0x57,0x11]
+          vxorpd (%rcx), %xmm21, %xmm18
+
+// CHECK: vxorpd 291(%rax,%r14,8), %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xa1,0xd5,0x00,0x57,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vxorpd 291(%rax,%r14,8), %xmm21, %xmm18
+
+// CHECK: vxorpd (%rcx){1to2}, %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x10,0x57,0x11]
+          vxorpd (%rcx){1to2}, %xmm21, %xmm18
+
+// CHECK: vxorpd 2032(%rdx), %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x00,0x57,0x52,0x7f]
+          vxorpd 2032(%rdx), %xmm21, %xmm18
+
+// CHECK: vxorpd 2048(%rdx), %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x00,0x57,0x92,0x00,0x08,0x00,0x00]
+          vxorpd 2048(%rdx), %xmm21, %xmm18
+
+// CHECK: vxorpd -2048(%rdx), %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x00,0x57,0x52,0x80]
+          vxorpd -2048(%rdx), %xmm21, %xmm18
+
+// CHECK: vxorpd -2064(%rdx), %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x00,0x57,0x92,0xf0,0xf7,0xff,0xff]
+          vxorpd -2064(%rdx), %xmm21, %xmm18
+
+// CHECK: vxorpd 1016(%rdx){1to2}, %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x10,0x57,0x52,0x7f]
+          vxorpd 1016(%rdx){1to2}, %xmm21, %xmm18
+
+// CHECK: vxorpd 1024(%rdx){1to2}, %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x10,0x57,0x92,0x00,0x04,0x00,0x00]
+          vxorpd 1024(%rdx){1to2}, %xmm21, %xmm18
+
+// CHECK: vxorpd -1024(%rdx){1to2}, %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x10,0x57,0x52,0x80]
+          vxorpd -1024(%rdx){1to2}, %xmm21, %xmm18
+
+// CHECK: vxorpd -1032(%rdx){1to2}, %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x10,0x57,0x92,0xf8,0xfb,0xff,0xff]
+          vxorpd -1032(%rdx){1to2}, %xmm21, %xmm18
+
+// CHECK: vxorpd %ymm19, %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x21,0x95,0x20,0x57,0xc3]
+          vxorpd %ymm19, %ymm29, %ymm24
+
+// CHECK: vxorpd %ymm19, %ymm29, %ymm24 {%k7}
+// CHECK:  encoding: [0x62,0x21,0x95,0x27,0x57,0xc3]
+          vxorpd %ymm19, %ymm29, %ymm24 {%k7}
+
+// CHECK: vxorpd %ymm19, %ymm29, %ymm24 {%k7} {z}
+// CHECK:  encoding: [0x62,0x21,0x95,0xa7,0x57,0xc3]
+          vxorpd %ymm19, %ymm29, %ymm24 {%k7} {z}
+
+// CHECK: vxorpd (%rcx), %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x57,0x01]
+          vxorpd (%rcx), %ymm29, %ymm24
+
+// CHECK: vxorpd 291(%rax,%r14,8), %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x21,0x95,0x20,0x57,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vxorpd 291(%rax,%r14,8), %ymm29, %ymm24
+
+// CHECK: vxorpd (%rcx){1to4}, %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x57,0x01]
+          vxorpd (%rcx){1to4}, %ymm29, %ymm24
+
+// CHECK: vxorpd 4064(%rdx), %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x57,0x42,0x7f]
+          vxorpd 4064(%rdx), %ymm29, %ymm24
+
+// CHECK: vxorpd 4096(%rdx), %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x57,0x82,0x00,0x10,0x00,0x00]
+          vxorpd 4096(%rdx), %ymm29, %ymm24
+
+// CHECK: vxorpd -4096(%rdx), %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x57,0x42,0x80]
+          vxorpd -4096(%rdx), %ymm29, %ymm24
+
+// CHECK: vxorpd -4128(%rdx), %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x57,0x82,0xe0,0xef,0xff,0xff]
+          vxorpd -4128(%rdx), %ymm29, %ymm24
+
+// CHECK: vxorpd 1016(%rdx){1to4}, %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x57,0x42,0x7f]
+          vxorpd 1016(%rdx){1to4}, %ymm29, %ymm24
+
+// CHECK: vxorpd 1024(%rdx){1to4}, %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x57,0x82,0x00,0x04,0x00,0x00]
+          vxorpd 1024(%rdx){1to4}, %ymm29, %ymm24
+
+// CHECK: vxorpd -1024(%rdx){1to4}, %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x57,0x42,0x80]
+          vxorpd -1024(%rdx){1to4}, %ymm29, %ymm24
+
+// CHECK: vxorpd -1032(%rdx){1to4}, %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x57,0x82,0xf8,0xfb,0xff,0xff]
+          vxorpd -1032(%rdx){1to4}, %ymm29, %ymm24
+
+// CHECK: vxorps %xmm19, %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0x6c,0x00,0x57,0xe3]
+          vxorps %xmm19, %xmm18, %xmm20
+
+// CHECK: vxorps %xmm19, %xmm18, %xmm20 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0x6c,0x01,0x57,0xe3]
+          vxorps %xmm19, %xmm18, %xmm20 {%k1}
+
+// CHECK: vxorps %xmm19, %xmm18, %xmm20 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0x6c,0x81,0x57,0xe3]
+          vxorps %xmm19, %xmm18, %xmm20 {%k1} {z}
+
+// CHECK: vxorps (%rcx), %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x00,0x57,0x21]
+          vxorps (%rcx), %xmm18, %xmm20
+
+// CHECK: vxorps 291(%rax,%r14,8), %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0x6c,0x00,0x57,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vxorps 291(%rax,%r14,8), %xmm18, %xmm20
+
+// CHECK: vxorps (%rcx){1to4}, %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x10,0x57,0x21]
+          vxorps (%rcx){1to4}, %xmm18, %xmm20
+
+// CHECK: vxorps 2032(%rdx), %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x00,0x57,0x62,0x7f]
+          vxorps 2032(%rdx), %xmm18, %xmm20
+
+// CHECK: vxorps 2048(%rdx), %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x00,0x57,0xa2,0x00,0x08,0x00,0x00]
+          vxorps 2048(%rdx), %xmm18, %xmm20
+
+// CHECK: vxorps -2048(%rdx), %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x00,0x57,0x62,0x80]
+          vxorps -2048(%rdx), %xmm18, %xmm20
+
+// CHECK: vxorps -2064(%rdx), %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x00,0x57,0xa2,0xf0,0xf7,0xff,0xff]
+          vxorps -2064(%rdx), %xmm18, %xmm20
+
+// CHECK: vxorps 508(%rdx){1to4}, %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x10,0x57,0x62,0x7f]
+          vxorps 508(%rdx){1to4}, %xmm18, %xmm20
+
+// CHECK: vxorps 512(%rdx){1to4}, %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x10,0x57,0xa2,0x00,0x02,0x00,0x00]
+          vxorps 512(%rdx){1to4}, %xmm18, %xmm20
+
+// CHECK: vxorps -512(%rdx){1to4}, %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x10,0x57,0x62,0x80]
+          vxorps -512(%rdx){1to4}, %xmm18, %xmm20
+
+// CHECK: vxorps -516(%rdx){1to4}, %xmm18, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x6c,0x10,0x57,0xa2,0xfc,0xfd,0xff,0xff]
+          vxorps -516(%rdx){1to4}, %xmm18, %xmm20
+
+// CHECK: vxorps %ymm24, %ymm20, %ymm27
+// CHECK:  encoding: [0x62,0x01,0x5c,0x20,0x57,0xd8]
+          vxorps %ymm24, %ymm20, %ymm27
+
+// CHECK: vxorps %ymm24, %ymm20, %ymm27 {%k2}
+// CHECK:  encoding: [0x62,0x01,0x5c,0x22,0x57,0xd8]
+          vxorps %ymm24, %ymm20, %ymm27 {%k2}
+
+// CHECK: vxorps %ymm24, %ymm20, %ymm27 {%k2} {z}
+// CHECK:  encoding: [0x62,0x01,0x5c,0xa2,0x57,0xd8]
+          vxorps %ymm24, %ymm20, %ymm27 {%k2} {z}
+
+// CHECK: vxorps (%rcx), %ymm20, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x5c,0x20,0x57,0x19]
+          vxorps (%rcx), %ymm20, %ymm27
+
+// CHECK: vxorps 291(%rax,%r14,8), %ymm20, %ymm27
+// CHECK:  encoding: [0x62,0x21,0x5c,0x20,0x57,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vxorps 291(%rax,%r14,8), %ymm20, %ymm27
+
+// CHECK: vxorps (%rcx){1to8}, %ymm20, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x5c,0x30,0x57,0x19]
+          vxorps (%rcx){1to8}, %ymm20, %ymm27
+
+// CHECK: vxorps 4064(%rdx), %ymm20, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x5c,0x20,0x57,0x5a,0x7f]
+          vxorps 4064(%rdx), %ymm20, %ymm27
+
+// CHECK: vxorps 4096(%rdx), %ymm20, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x5c,0x20,0x57,0x9a,0x00,0x10,0x00,0x00]
+          vxorps 4096(%rdx), %ymm20, %ymm27
+
+// CHECK: vxorps -4096(%rdx), %ymm20, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x5c,0x20,0x57,0x5a,0x80]
+          vxorps -4096(%rdx), %ymm20, %ymm27
+
+// CHECK: vxorps -4128(%rdx), %ymm20, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x5c,0x20,0x57,0x9a,0xe0,0xef,0xff,0xff]
+          vxorps -4128(%rdx), %ymm20, %ymm27
+
+// CHECK: vxorps 508(%rdx){1to8}, %ymm20, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x5c,0x30,0x57,0x5a,0x7f]
+          vxorps 508(%rdx){1to8}, %ymm20, %ymm27
+
+// CHECK: vxorps 512(%rdx){1to8}, %ymm20, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x5c,0x30,0x57,0x9a,0x00,0x02,0x00,0x00]
+          vxorps 512(%rdx){1to8}, %ymm20, %ymm27
+
+// CHECK: vxorps -512(%rdx){1to8}, %ymm20, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x5c,0x30,0x57,0x5a,0x80]
+          vxorps -512(%rdx){1to8}, %ymm20, %ymm27
+
+// CHECK: vxorps -516(%rdx){1to8}, %ymm20, %ymm27
+// CHECK:  encoding: [0x62,0x61,0x5c,0x30,0x57,0x9a,0xfc,0xfd,0xff,0xff]
+          vxorps -516(%rdx){1to8}, %ymm20, %ymm27
+
+// CHECK: vandpd %xmm27, %xmm25, %xmm19
+// CHECK:  encoding: [0x62,0x81,0xb5,0x00,0x54,0xdb]
+          vandpd %xmm27, %xmm25, %xmm19
+
+// CHECK: vandpd %xmm27, %xmm25, %xmm19 {%k6}
+// CHECK:  encoding: [0x62,0x81,0xb5,0x06,0x54,0xdb]
+          vandpd %xmm27, %xmm25, %xmm19 {%k6}
+
+// CHECK: vandpd %xmm27, %xmm25, %xmm19 {%k6} {z}
+// CHECK:  encoding: [0x62,0x81,0xb5,0x86,0x54,0xdb]
+          vandpd %xmm27, %xmm25, %xmm19 {%k6} {z}
+
+// CHECK: vandpd (%rcx), %xmm25, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xb5,0x00,0x54,0x19]
+          vandpd (%rcx), %xmm25, %xmm19
+
+// CHECK: vandpd 4660(%rax,%r14,8), %xmm25, %xmm19
+// CHECK:  encoding: [0x62,0xa1,0xb5,0x00,0x54,0x9c,0xf0,0x34,0x12,0x00,0x00]
+          vandpd 4660(%rax,%r14,8), %xmm25, %xmm19
+
+// CHECK: vandpd (%rcx){1to2}, %xmm25, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xb5,0x10,0x54,0x19]
+          vandpd (%rcx){1to2}, %xmm25, %xmm19
+
+// CHECK: vandpd 2032(%rdx), %xmm25, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xb5,0x00,0x54,0x5a,0x7f]
+          vandpd 2032(%rdx), %xmm25, %xmm19
+
+// CHECK: vandpd 2048(%rdx), %xmm25, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xb5,0x00,0x54,0x9a,0x00,0x08,0x00,0x00]
+          vandpd 2048(%rdx), %xmm25, %xmm19
+
+// CHECK: vandpd -2048(%rdx), %xmm25, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xb5,0x00,0x54,0x5a,0x80]
+          vandpd -2048(%rdx), %xmm25, %xmm19
+
+// CHECK: vandpd -2064(%rdx), %xmm25, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xb5,0x00,0x54,0x9a,0xf0,0xf7,0xff,0xff]
+          vandpd -2064(%rdx), %xmm25, %xmm19
+
+// CHECK: vandpd 1016(%rdx){1to2}, %xmm25, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xb5,0x10,0x54,0x5a,0x7f]
+          vandpd 1016(%rdx){1to2}, %xmm25, %xmm19
+
+// CHECK: vandpd 1024(%rdx){1to2}, %xmm25, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xb5,0x10,0x54,0x9a,0x00,0x04,0x00,0x00]
+          vandpd 1024(%rdx){1to2}, %xmm25, %xmm19
+
+// CHECK: vandpd -1024(%rdx){1to2}, %xmm25, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xb5,0x10,0x54,0x5a,0x80]
+          vandpd -1024(%rdx){1to2}, %xmm25, %xmm19
+
+// CHECK: vandpd -1032(%rdx){1to2}, %xmm25, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xb5,0x10,0x54,0x9a,0xf8,0xfb,0xff,0xff]
+          vandpd -1032(%rdx){1to2}, %xmm25, %xmm19
+
+// CHECK: vandpd %ymm21, %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x21,0x95,0x20,0x54,0xc5]
+          vandpd %ymm21, %ymm29, %ymm24
+
+// CHECK: vandpd %ymm21, %ymm29, %ymm24 {%k2}
+// CHECK:  encoding: [0x62,0x21,0x95,0x22,0x54,0xc5]
+          vandpd %ymm21, %ymm29, %ymm24 {%k2}
+
+// CHECK: vandpd %ymm21, %ymm29, %ymm24 {%k2} {z}
+// CHECK:  encoding: [0x62,0x21,0x95,0xa2,0x54,0xc5]
+          vandpd %ymm21, %ymm29, %ymm24 {%k2} {z}
+
+// CHECK: vandpd (%rcx), %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x54,0x01]
+          vandpd (%rcx), %ymm29, %ymm24
+
+// CHECK: vandpd 4660(%rax,%r14,8), %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x21,0x95,0x20,0x54,0x84,0xf0,0x34,0x12,0x00,0x00]
+          vandpd 4660(%rax,%r14,8), %ymm29, %ymm24
+
+// CHECK: vandpd (%rcx){1to4}, %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x54,0x01]
+          vandpd (%rcx){1to4}, %ymm29, %ymm24
+
+// CHECK: vandpd 4064(%rdx), %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x54,0x42,0x7f]
+          vandpd 4064(%rdx), %ymm29, %ymm24
+
+// CHECK: vandpd 4096(%rdx), %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x54,0x82,0x00,0x10,0x00,0x00]
+          vandpd 4096(%rdx), %ymm29, %ymm24
+
+// CHECK: vandpd -4096(%rdx), %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x54,0x42,0x80]
+          vandpd -4096(%rdx), %ymm29, %ymm24
+
+// CHECK: vandpd -4128(%rdx), %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x54,0x82,0xe0,0xef,0xff,0xff]
+          vandpd -4128(%rdx), %ymm29, %ymm24
+
+// CHECK: vandpd 1016(%rdx){1to4}, %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x54,0x42,0x7f]
+          vandpd 1016(%rdx){1to4}, %ymm29, %ymm24
+
+// CHECK: vandpd 1024(%rdx){1to4}, %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x54,0x82,0x00,0x04,0x00,0x00]
+          vandpd 1024(%rdx){1to4}, %ymm29, %ymm24
+
+// CHECK: vandpd -1024(%rdx){1to4}, %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x54,0x42,0x80]
+          vandpd -1024(%rdx){1to4}, %ymm29, %ymm24
+
+// CHECK: vandpd -1032(%rdx){1to4}, %ymm29, %ymm24
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x54,0x82,0xf8,0xfb,0xff,0xff]
+          vandpd -1032(%rdx){1to4}, %ymm29, %ymm24
+
+// CHECK: vandps %xmm17, %xmm25, %xmm22
+// CHECK:  encoding: [0x62,0xa1,0x34,0x00,0x54,0xf1]
+          vandps %xmm17, %xmm25, %xmm22
+
+// CHECK: vandps %xmm17, %xmm25, %xmm22 {%k3}
+// CHECK:  encoding: [0x62,0xa1,0x34,0x03,0x54,0xf1]
+          vandps %xmm17, %xmm25, %xmm22 {%k3}
+
+// CHECK: vandps %xmm17, %xmm25, %xmm22 {%k3} {z}
+// CHECK:  encoding: [0x62,0xa1,0x34,0x83,0x54,0xf1]
+          vandps %xmm17, %xmm25, %xmm22 {%k3} {z}
+
+// CHECK: vandps (%rcx), %xmm25, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x00,0x54,0x31]
+          vandps (%rcx), %xmm25, %xmm22
+
+// CHECK: vandps 4660(%rax,%r14,8), %xmm25, %xmm22
+// CHECK:  encoding: [0x62,0xa1,0x34,0x00,0x54,0xb4,0xf0,0x34,0x12,0x00,0x00]
+          vandps 4660(%rax,%r14,8), %xmm25, %xmm22
+
+// CHECK: vandps (%rcx){1to4}, %xmm25, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x10,0x54,0x31]
+          vandps (%rcx){1to4}, %xmm25, %xmm22
+
+// CHECK: vandps 2032(%rdx), %xmm25, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x00,0x54,0x72,0x7f]
+          vandps 2032(%rdx), %xmm25, %xmm22
+
+// CHECK: vandps 2048(%rdx), %xmm25, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x00,0x54,0xb2,0x00,0x08,0x00,0x00]
+          vandps 2048(%rdx), %xmm25, %xmm22
+
+// CHECK: vandps -2048(%rdx), %xmm25, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x00,0x54,0x72,0x80]
+          vandps -2048(%rdx), %xmm25, %xmm22
+
+// CHECK: vandps -2064(%rdx), %xmm25, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x00,0x54,0xb2,0xf0,0xf7,0xff,0xff]
+          vandps -2064(%rdx), %xmm25, %xmm22
+
+// CHECK: vandps 508(%rdx){1to4}, %xmm25, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x10,0x54,0x72,0x7f]
+          vandps 508(%rdx){1to4}, %xmm25, %xmm22
+
+// CHECK: vandps 512(%rdx){1to4}, %xmm25, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x10,0x54,0xb2,0x00,0x02,0x00,0x00]
+          vandps 512(%rdx){1to4}, %xmm25, %xmm22
+
+// CHECK: vandps -512(%rdx){1to4}, %xmm25, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x10,0x54,0x72,0x80]
+          vandps -512(%rdx){1to4}, %xmm25, %xmm22
+
+// CHECK: vandps -516(%rdx){1to4}, %xmm25, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x10,0x54,0xb2,0xfc,0xfd,0xff,0xff]
+          vandps -516(%rdx){1to4}, %xmm25, %xmm22
+
+// CHECK: vandps %ymm18, %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xa1,0x34,0x20,0x54,0xf2]
+          vandps %ymm18, %ymm25, %ymm22
+
+// CHECK: vandps %ymm18, %ymm25, %ymm22 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0x34,0x21,0x54,0xf2]
+          vandps %ymm18, %ymm25, %ymm22 {%k1}
+
+// CHECK: vandps %ymm18, %ymm25, %ymm22 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0x34,0xa1,0x54,0xf2]
+          vandps %ymm18, %ymm25, %ymm22 {%k1} {z}
+
+// CHECK: vandps (%rcx), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x20,0x54,0x31]
+          vandps (%rcx), %ymm25, %ymm22
+
+// CHECK: vandps 4660(%rax,%r14,8), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xa1,0x34,0x20,0x54,0xb4,0xf0,0x34,0x12,0x00,0x00]
+          vandps 4660(%rax,%r14,8), %ymm25, %ymm22
+
+// CHECK: vandps (%rcx){1to8}, %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x30,0x54,0x31]
+          vandps (%rcx){1to8}, %ymm25, %ymm22
+
+// CHECK: vandps 4064(%rdx), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x20,0x54,0x72,0x7f]
+          vandps 4064(%rdx), %ymm25, %ymm22
+
+// CHECK: vandps 4096(%rdx), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x20,0x54,0xb2,0x00,0x10,0x00,0x00]
+          vandps 4096(%rdx), %ymm25, %ymm22
+
+// CHECK: vandps -4096(%rdx), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x20,0x54,0x72,0x80]
+          vandps -4096(%rdx), %ymm25, %ymm22
+
+// CHECK: vandps -4128(%rdx), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x20,0x54,0xb2,0xe0,0xef,0xff,0xff]
+          vandps -4128(%rdx), %ymm25, %ymm22
+
+// CHECK: vandps 508(%rdx){1to8}, %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x30,0x54,0x72,0x7f]
+          vandps 508(%rdx){1to8}, %ymm25, %ymm22
+
+// CHECK: vandps 512(%rdx){1to8}, %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x30,0x54,0xb2,0x00,0x02,0x00,0x00]
+          vandps 512(%rdx){1to8}, %ymm25, %ymm22
+
+// CHECK: vandps -512(%rdx){1to8}, %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x30,0x54,0x72,0x80]
+          vandps -512(%rdx){1to8}, %ymm25, %ymm22
+
+// CHECK: vandps -516(%rdx){1to8}, %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0x34,0x30,0x54,0xb2,0xfc,0xfd,0xff,0xff]
+          vandps -516(%rdx){1to8}, %ymm25, %ymm22
+
+// CHECK: vandnpd %xmm23, %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xa1,0xed,0x00,0x55,0xdf]
+          vandnpd %xmm23, %xmm18, %xmm19
+
+// CHECK: vandnpd %xmm23, %xmm18, %xmm19 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0xed,0x01,0x55,0xdf]
+          vandnpd %xmm23, %xmm18, %xmm19 {%k1}
+
+// CHECK: vandnpd %xmm23, %xmm18, %xmm19 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0xed,0x81,0x55,0xdf]
+          vandnpd %xmm23, %xmm18, %xmm19 {%k1} {z}
+
+// CHECK: vandnpd (%rcx), %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xed,0x00,0x55,0x19]
+          vandnpd (%rcx), %xmm18, %xmm19
+
+// CHECK: vandnpd 4660(%rax,%r14,8), %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xa1,0xed,0x00,0x55,0x9c,0xf0,0x34,0x12,0x00,0x00]
+          vandnpd 4660(%rax,%r14,8), %xmm18, %xmm19
+
+// CHECK: vandnpd (%rcx){1to2}, %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xed,0x10,0x55,0x19]
+          vandnpd (%rcx){1to2}, %xmm18, %xmm19
+
+// CHECK: vandnpd 2032(%rdx), %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xed,0x00,0x55,0x5a,0x7f]
+          vandnpd 2032(%rdx), %xmm18, %xmm19
+
+// CHECK: vandnpd 2048(%rdx), %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xed,0x00,0x55,0x9a,0x00,0x08,0x00,0x00]
+          vandnpd 2048(%rdx), %xmm18, %xmm19
+
+// CHECK: vandnpd -2048(%rdx), %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xed,0x00,0x55,0x5a,0x80]
+          vandnpd -2048(%rdx), %xmm18, %xmm19
+
+// CHECK: vandnpd -2064(%rdx), %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xed,0x00,0x55,0x9a,0xf0,0xf7,0xff,0xff]
+          vandnpd -2064(%rdx), %xmm18, %xmm19
+
+// CHECK: vandnpd 1016(%rdx){1to2}, %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xed,0x10,0x55,0x5a,0x7f]
+          vandnpd 1016(%rdx){1to2}, %xmm18, %xmm19
+
+// CHECK: vandnpd 1024(%rdx){1to2}, %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xed,0x10,0x55,0x9a,0x00,0x04,0x00,0x00]
+          vandnpd 1024(%rdx){1to2}, %xmm18, %xmm19
+
+// CHECK: vandnpd -1024(%rdx){1to2}, %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xed,0x10,0x55,0x5a,0x80]
+          vandnpd -1024(%rdx){1to2}, %xmm18, %xmm19
+
+// CHECK: vandnpd -1032(%rdx){1to2}, %xmm18, %xmm19
+// CHECK:  encoding: [0x62,0xe1,0xed,0x10,0x55,0x9a,0xf8,0xfb,0xff,0xff]
+          vandnpd -1032(%rdx){1to2}, %xmm18, %xmm19
+
+// CHECK: vandnpd %ymm28, %ymm29, %ymm25
+// CHECK:  encoding: [0x62,0x01,0x95,0x20,0x55,0xcc]
+          vandnpd %ymm28, %ymm29, %ymm25
+
+// CHECK: vandnpd %ymm28, %ymm29, %ymm25 {%k7}
+// CHECK:  encoding: [0x62,0x01,0x95,0x27,0x55,0xcc]
+          vandnpd %ymm28, %ymm29, %ymm25 {%k7}
+
+// CHECK: vandnpd %ymm28, %ymm29, %ymm25 {%k7} {z}
+// CHECK:  encoding: [0x62,0x01,0x95,0xa7,0x55,0xcc]
+          vandnpd %ymm28, %ymm29, %ymm25 {%k7} {z}
+
+// CHECK: vandnpd (%rcx), %ymm29, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x55,0x09]
+          vandnpd (%rcx), %ymm29, %ymm25
+
+// CHECK: vandnpd 4660(%rax,%r14,8), %ymm29, %ymm25
+// CHECK:  encoding: [0x62,0x21,0x95,0x20,0x55,0x8c,0xf0,0x34,0x12,0x00,0x00]
+          vandnpd 4660(%rax,%r14,8), %ymm29, %ymm25
+
+// CHECK: vandnpd (%rcx){1to4}, %ymm29, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x55,0x09]
+          vandnpd (%rcx){1to4}, %ymm29, %ymm25
+
+// CHECK: vandnpd 4064(%rdx), %ymm29, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x55,0x4a,0x7f]
+          vandnpd 4064(%rdx), %ymm29, %ymm25
+
+// CHECK: vandnpd 4096(%rdx), %ymm29, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x55,0x8a,0x00,0x10,0x00,0x00]
+          vandnpd 4096(%rdx), %ymm29, %ymm25
+
+// CHECK: vandnpd -4096(%rdx), %ymm29, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x55,0x4a,0x80]
+          vandnpd -4096(%rdx), %ymm29, %ymm25
+
+// CHECK: vandnpd -4128(%rdx), %ymm29, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x95,0x20,0x55,0x8a,0xe0,0xef,0xff,0xff]
+          vandnpd -4128(%rdx), %ymm29, %ymm25
+
+// CHECK: vandnpd 1016(%rdx){1to4}, %ymm29, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x55,0x4a,0x7f]
+          vandnpd 1016(%rdx){1to4}, %ymm29, %ymm25
+
+// CHECK: vandnpd 1024(%rdx){1to4}, %ymm29, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x55,0x8a,0x00,0x04,0x00,0x00]
+          vandnpd 1024(%rdx){1to4}, %ymm29, %ymm25
+
+// CHECK: vandnpd -1024(%rdx){1to4}, %ymm29, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x55,0x4a,0x80]
+          vandnpd -1024(%rdx){1to4}, %ymm29, %ymm25
+
+// CHECK: vandnpd -1032(%rdx){1to4}, %ymm29, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x95,0x30,0x55,0x8a,0xf8,0xfb,0xff,0xff]
+          vandnpd -1032(%rdx){1to4}, %ymm29, %ymm25
+
+// CHECK: vandnps %xmm23, %xmm17, %xmm25
+// CHECK:  encoding: [0x62,0x21,0x74,0x00,0x55,0xcf]
+          vandnps %xmm23, %xmm17, %xmm25
+
+// CHECK: vandnps %xmm23, %xmm17, %xmm25 {%k5}
+// CHECK:  encoding: [0x62,0x21,0x74,0x05,0x55,0xcf]
+          vandnps %xmm23, %xmm17, %xmm25 {%k5}
+
+// CHECK: vandnps %xmm23, %xmm17, %xmm25 {%k5} {z}
+// CHECK:  encoding: [0x62,0x21,0x74,0x85,0x55,0xcf]
+          vandnps %xmm23, %xmm17, %xmm25 {%k5} {z}
+
+// CHECK: vandnps (%rcx), %xmm17, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x74,0x00,0x55,0x09]
+          vandnps (%rcx), %xmm17, %xmm25
+
+// CHECK: vandnps 4660(%rax,%r14,8), %xmm17, %xmm25
+// CHECK:  encoding: [0x62,0x21,0x74,0x00,0x55,0x8c,0xf0,0x34,0x12,0x00,0x00]
+          vandnps 4660(%rax,%r14,8), %xmm17, %xmm25
+
+// CHECK: vandnps (%rcx){1to4}, %xmm17, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x74,0x10,0x55,0x09]
+          vandnps (%rcx){1to4}, %xmm17, %xmm25
+
+// CHECK: vandnps 2032(%rdx), %xmm17, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x74,0x00,0x55,0x4a,0x7f]
+          vandnps 2032(%rdx), %xmm17, %xmm25
+
+// CHECK: vandnps 2048(%rdx), %xmm17, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x74,0x00,0x55,0x8a,0x00,0x08,0x00,0x00]
+          vandnps 2048(%rdx), %xmm17, %xmm25
+
+// CHECK: vandnps -2048(%rdx), %xmm17, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x74,0x00,0x55,0x4a,0x80]
+          vandnps -2048(%rdx), %xmm17, %xmm25
+
+// CHECK: vandnps -2064(%rdx), %xmm17, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x74,0x00,0x55,0x8a,0xf0,0xf7,0xff,0xff]
+          vandnps -2064(%rdx), %xmm17, %xmm25
+
+// CHECK: vandnps 508(%rdx){1to4}, %xmm17, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x74,0x10,0x55,0x4a,0x7f]
+          vandnps 508(%rdx){1to4}, %xmm17, %xmm25
+
+// CHECK: vandnps 512(%rdx){1to4}, %xmm17, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x74,0x10,0x55,0x8a,0x00,0x02,0x00,0x00]
+          vandnps 512(%rdx){1to4}, %xmm17, %xmm25
+
+// CHECK: vandnps -512(%rdx){1to4}, %xmm17, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x74,0x10,0x55,0x4a,0x80]
+          vandnps -512(%rdx){1to4}, %xmm17, %xmm25
+
+// CHECK: vandnps -516(%rdx){1to4}, %xmm17, %xmm25
+// CHECK:  encoding: [0x62,0x61,0x74,0x10,0x55,0x8a,0xfc,0xfd,0xff,0xff]
+          vandnps -516(%rdx){1to4}, %xmm17, %xmm25
+
+// CHECK: vandnps %ymm23, %ymm19, %ymm18
+// CHECK:  encoding: [0x62,0xa1,0x64,0x20,0x55,0xd7]
+          vandnps %ymm23, %ymm19, %ymm18
+
+// CHECK: vandnps %ymm23, %ymm19, %ymm18 {%k6}
+// CHECK:  encoding: [0x62,0xa1,0x64,0x26,0x55,0xd7]
+          vandnps %ymm23, %ymm19, %ymm18 {%k6}
+
+// CHECK: vandnps %ymm23, %ymm19, %ymm18 {%k6} {z}
+// CHECK:  encoding: [0x62,0xa1,0x64,0xa6,0x55,0xd7]
+          vandnps %ymm23, %ymm19, %ymm18 {%k6} {z}
+
+// CHECK: vandnps (%rcx), %ymm19, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x64,0x20,0x55,0x11]
+          vandnps (%rcx), %ymm19, %ymm18
+
+// CHECK: vandnps 4660(%rax,%r14,8), %ymm19, %ymm18
+// CHECK:  encoding: [0x62,0xa1,0x64,0x20,0x55,0x94,0xf0,0x34,0x12,0x00,0x00]
+          vandnps 4660(%rax,%r14,8), %ymm19, %ymm18
+
+// CHECK: vandnps (%rcx){1to8}, %ymm19, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x64,0x30,0x55,0x11]
+          vandnps (%rcx){1to8}, %ymm19, %ymm18
+
+// CHECK: vandnps 4064(%rdx), %ymm19, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x64,0x20,0x55,0x52,0x7f]
+          vandnps 4064(%rdx), %ymm19, %ymm18
+
+// CHECK: vandnps 4096(%rdx), %ymm19, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x64,0x20,0x55,0x92,0x00,0x10,0x00,0x00]
+          vandnps 4096(%rdx), %ymm19, %ymm18
+
+// CHECK: vandnps -4096(%rdx), %ymm19, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x64,0x20,0x55,0x52,0x80]
+          vandnps -4096(%rdx), %ymm19, %ymm18
+
+// CHECK: vandnps -4128(%rdx), %ymm19, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x64,0x20,0x55,0x92,0xe0,0xef,0xff,0xff]
+          vandnps -4128(%rdx), %ymm19, %ymm18
+
+// CHECK: vandnps 508(%rdx){1to8}, %ymm19, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x64,0x30,0x55,0x52,0x7f]
+          vandnps 508(%rdx){1to8}, %ymm19, %ymm18
+
+// CHECK: vandnps 512(%rdx){1to8}, %ymm19, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x64,0x30,0x55,0x92,0x00,0x02,0x00,0x00]
+          vandnps 512(%rdx){1to8}, %ymm19, %ymm18
+
+// CHECK: vandnps -512(%rdx){1to8}, %ymm19, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x64,0x30,0x55,0x52,0x80]
+          vandnps -512(%rdx){1to8}, %ymm19, %ymm18
+
+// CHECK: vandnps -516(%rdx){1to8}, %ymm19, %ymm18
+// CHECK:  encoding: [0x62,0xe1,0x64,0x30,0x55,0x92,0xfc,0xfd,0xff,0xff]
+          vandnps -516(%rdx){1to8}, %ymm19, %ymm18
+
+// CHECK: vorpd  %xmm18, %xmm29, %xmm26
+// CHECK:  encoding: [0x62,0x21,0x95,0x00,0x56,0xd2]
+          vorpd  %xmm18, %xmm29, %xmm26
+
+// CHECK: vorpd  %xmm18, %xmm29, %xmm26 {%k2}
+// CHECK:  encoding: [0x62,0x21,0x95,0x02,0x56,0xd2]
+          vorpd  %xmm18, %xmm29, %xmm26 {%k2}
+
+// CHECK: vorpd  %xmm18, %xmm29, %xmm26 {%k2} {z}
+// CHECK:  encoding: [0x62,0x21,0x95,0x82,0x56,0xd2]
+          vorpd  %xmm18, %xmm29, %xmm26 {%k2} {z}
+
+// CHECK: vorpd  (%rcx), %xmm29, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x00,0x56,0x11]
+          vorpd  (%rcx), %xmm29, %xmm26
+
+// CHECK: vorpd  4660(%rax,%r14,8), %xmm29, %xmm26
+// CHECK:  encoding: [0x62,0x21,0x95,0x00,0x56,0x94,0xf0,0x34,0x12,0x00,0x00]
+          vorpd  4660(%rax,%r14,8), %xmm29, %xmm26
+
+// CHECK: vorpd  (%rcx){1to2}, %xmm29, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x10,0x56,0x11]
+          vorpd  (%rcx){1to2}, %xmm29, %xmm26
+
+// CHECK: vorpd  2032(%rdx), %xmm29, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x00,0x56,0x52,0x7f]
+          vorpd  2032(%rdx), %xmm29, %xmm26
+
+// CHECK: vorpd  2048(%rdx), %xmm29, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x00,0x56,0x92,0x00,0x08,0x00,0x00]
+          vorpd  2048(%rdx), %xmm29, %xmm26
+
+// CHECK: vorpd  -2048(%rdx), %xmm29, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x00,0x56,0x52,0x80]
+          vorpd  -2048(%rdx), %xmm29, %xmm26
+
+// CHECK: vorpd  -2064(%rdx), %xmm29, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x00,0x56,0x92,0xf0,0xf7,0xff,0xff]
+          vorpd  -2064(%rdx), %xmm29, %xmm26
+
+// CHECK: vorpd  1016(%rdx){1to2}, %xmm29, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x10,0x56,0x52,0x7f]
+          vorpd  1016(%rdx){1to2}, %xmm29, %xmm26
+
+// CHECK: vorpd  1024(%rdx){1to2}, %xmm29, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x10,0x56,0x92,0x00,0x04,0x00,0x00]
+          vorpd  1024(%rdx){1to2}, %xmm29, %xmm26
+
+// CHECK: vorpd  -1024(%rdx){1to2}, %xmm29, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x10,0x56,0x52,0x80]
+          vorpd  -1024(%rdx){1to2}, %xmm29, %xmm26
+
+// CHECK: vorpd  -1032(%rdx){1to2}, %xmm29, %xmm26
+// CHECK:  encoding: [0x62,0x61,0x95,0x10,0x56,0x92,0xf8,0xfb,0xff,0xff]
+          vorpd  -1032(%rdx){1to2}, %xmm29, %xmm26
+
+// CHECK: vorpd  %ymm22, %ymm19, %ymm28
+// CHECK:  encoding: [0x62,0x21,0xe5,0x20,0x56,0xe6]
+          vorpd  %ymm22, %ymm19, %ymm28
+
+// CHECK: vorpd  %ymm22, %ymm19, %ymm28 {%k1}
+// CHECK:  encoding: [0x62,0x21,0xe5,0x21,0x56,0xe6]
+          vorpd  %ymm22, %ymm19, %ymm28 {%k1}
+
+// CHECK: vorpd  %ymm22, %ymm19, %ymm28 {%k1} {z}
+// CHECK:  encoding: [0x62,0x21,0xe5,0xa1,0x56,0xe6]
+          vorpd  %ymm22, %ymm19, %ymm28 {%k1} {z}
+
+// CHECK: vorpd  (%rcx), %ymm19, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xe5,0x20,0x56,0x21]
+          vorpd  (%rcx), %ymm19, %ymm28
+
+// CHECK: vorpd  4660(%rax,%r14,8), %ymm19, %ymm28
+// CHECK:  encoding: [0x62,0x21,0xe5,0x20,0x56,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vorpd  4660(%rax,%r14,8), %ymm19, %ymm28
+
+// CHECK: vorpd  (%rcx){1to4}, %ymm19, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xe5,0x30,0x56,0x21]
+          vorpd  (%rcx){1to4}, %ymm19, %ymm28
+
+// CHECK: vorpd  4064(%rdx), %ymm19, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xe5,0x20,0x56,0x62,0x7f]
+          vorpd  4064(%rdx), %ymm19, %ymm28
+
+// CHECK: vorpd  4096(%rdx), %ymm19, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xe5,0x20,0x56,0xa2,0x00,0x10,0x00,0x00]
+          vorpd  4096(%rdx), %ymm19, %ymm28
+
+// CHECK: vorpd  -4096(%rdx), %ymm19, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xe5,0x20,0x56,0x62,0x80]
+          vorpd  -4096(%rdx), %ymm19, %ymm28
+
+// CHECK: vorpd  -4128(%rdx), %ymm19, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xe5,0x20,0x56,0xa2,0xe0,0xef,0xff,0xff]
+          vorpd  -4128(%rdx), %ymm19, %ymm28
+
+// CHECK: vorpd  1016(%rdx){1to4}, %ymm19, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xe5,0x30,0x56,0x62,0x7f]
+          vorpd  1016(%rdx){1to4}, %ymm19, %ymm28
+
+// CHECK: vorpd  1024(%rdx){1to4}, %ymm19, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xe5,0x30,0x56,0xa2,0x00,0x04,0x00,0x00]
+          vorpd  1024(%rdx){1to4}, %ymm19, %ymm28
+
+// CHECK: vorpd  -1024(%rdx){1to4}, %ymm19, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xe5,0x30,0x56,0x62,0x80]
+          vorpd  -1024(%rdx){1to4}, %ymm19, %ymm28
+
+// CHECK: vorpd  -1032(%rdx){1to4}, %ymm19, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xe5,0x30,0x56,0xa2,0xf8,0xfb,0xff,0xff]
+          vorpd  -1032(%rdx){1to4}, %ymm19, %ymm28
+
+// CHECK: vorps  %xmm24, %xmm22, %xmm28
+// CHECK:  encoding: [0x62,0x01,0x4c,0x00,0x56,0xe0]
+          vorps  %xmm24, %xmm22, %xmm28
+
+// CHECK: vorps  %xmm24, %xmm22, %xmm28 {%k6}
+// CHECK:  encoding: [0x62,0x01,0x4c,0x06,0x56,0xe0]
+          vorps  %xmm24, %xmm22, %xmm28 {%k6}
+
+// CHECK: vorps  %xmm24, %xmm22, %xmm28 {%k6} {z}
+// CHECK:  encoding: [0x62,0x01,0x4c,0x86,0x56,0xe0]
+          vorps  %xmm24, %xmm22, %xmm28 {%k6} {z}
+
+// CHECK: vorps  (%rcx), %xmm22, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x4c,0x00,0x56,0x21]
+          vorps  (%rcx), %xmm22, %xmm28
+
+// CHECK: vorps  4660(%rax,%r14,8), %xmm22, %xmm28
+// CHECK:  encoding: [0x62,0x21,0x4c,0x00,0x56,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vorps  4660(%rax,%r14,8), %xmm22, %xmm28
+
+// CHECK: vorps  (%rcx){1to4}, %xmm22, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x4c,0x10,0x56,0x21]
+          vorps  (%rcx){1to4}, %xmm22, %xmm28
+
+// CHECK: vorps  2032(%rdx), %xmm22, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x4c,0x00,0x56,0x62,0x7f]
+          vorps  2032(%rdx), %xmm22, %xmm28
+
+// CHECK: vorps  2048(%rdx), %xmm22, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x4c,0x00,0x56,0xa2,0x00,0x08,0x00,0x00]
+          vorps  2048(%rdx), %xmm22, %xmm28
+
+// CHECK: vorps  -2048(%rdx), %xmm22, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x4c,0x00,0x56,0x62,0x80]
+          vorps  -2048(%rdx), %xmm22, %xmm28
+
+// CHECK: vorps  -2064(%rdx), %xmm22, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x4c,0x00,0x56,0xa2,0xf0,0xf7,0xff,0xff]
+          vorps  -2064(%rdx), %xmm22, %xmm28
+
+// CHECK: vorps  508(%rdx){1to4}, %xmm22, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x4c,0x10,0x56,0x62,0x7f]
+          vorps  508(%rdx){1to4}, %xmm22, %xmm28
+
+// CHECK: vorps  512(%rdx){1to4}, %xmm22, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x4c,0x10,0x56,0xa2,0x00,0x02,0x00,0x00]
+          vorps  512(%rdx){1to4}, %xmm22, %xmm28
+
+// CHECK: vorps  -512(%rdx){1to4}, %xmm22, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x4c,0x10,0x56,0x62,0x80]
+          vorps  -512(%rdx){1to4}, %xmm22, %xmm28
+
+// CHECK: vorps  -516(%rdx){1to4}, %xmm22, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x4c,0x10,0x56,0xa2,0xfc,0xfd,0xff,0xff]
+          vorps  -516(%rdx){1to4}, %xmm22, %xmm28
+
+// CHECK: vorps  %ymm25, %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0x81,0x3c,0x20,0x56,0xe1]
+          vorps  %ymm25, %ymm24, %ymm20
+
+// CHECK: vorps  %ymm25, %ymm24, %ymm20 {%k1}
+// CHECK:  encoding: [0x62,0x81,0x3c,0x21,0x56,0xe1]
+          vorps  %ymm25, %ymm24, %ymm20 {%k1}
+
+// CHECK: vorps  %ymm25, %ymm24, %ymm20 {%k1} {z}
+// CHECK:  encoding: [0x62,0x81,0x3c,0xa1,0x56,0xe1]
+          vorps  %ymm25, %ymm24, %ymm20 {%k1} {z}
+
+// CHECK: vorps  (%rcx), %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x3c,0x20,0x56,0x21]
+          vorps  (%rcx), %ymm24, %ymm20
+
+// CHECK: vorps  4660(%rax,%r14,8), %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xa1,0x3c,0x20,0x56,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vorps  4660(%rax,%r14,8), %ymm24, %ymm20
+
+// CHECK: vorps  (%rcx){1to8}, %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x3c,0x30,0x56,0x21]
+          vorps  (%rcx){1to8}, %ymm24, %ymm20
+
+// CHECK: vorps  4064(%rdx), %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x3c,0x20,0x56,0x62,0x7f]
+          vorps  4064(%rdx), %ymm24, %ymm20
+
+// CHECK: vorps  4096(%rdx), %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x3c,0x20,0x56,0xa2,0x00,0x10,0x00,0x00]
+          vorps  4096(%rdx), %ymm24, %ymm20
+
+// CHECK: vorps  -4096(%rdx), %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x3c,0x20,0x56,0x62,0x80]
+          vorps  -4096(%rdx), %ymm24, %ymm20
+
+// CHECK: vorps  -4128(%rdx), %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x3c,0x20,0x56,0xa2,0xe0,0xef,0xff,0xff]
+          vorps  -4128(%rdx), %ymm24, %ymm20
+
+// CHECK: vorps  508(%rdx){1to8}, %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x3c,0x30,0x56,0x62,0x7f]
+          vorps  508(%rdx){1to8}, %ymm24, %ymm20
+
+// CHECK: vorps  512(%rdx){1to8}, %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x3c,0x30,0x56,0xa2,0x00,0x02,0x00,0x00]
+          vorps  512(%rdx){1to8}, %ymm24, %ymm20
+
+// CHECK: vorps  -512(%rdx){1to8}, %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x3c,0x30,0x56,0x62,0x80]
+          vorps  -512(%rdx){1to8}, %ymm24, %ymm20
+
+// CHECK: vorps  -516(%rdx){1to8}, %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe1,0x3c,0x30,0x56,0xa2,0xfc,0xfd,0xff,0xff]
+          vorps  -516(%rdx){1to8}, %ymm24, %ymm20
+
+// CHECK: vxorpd %xmm18, %xmm21, %xmm22
+// CHECK:  encoding: [0x62,0xa1,0xd5,0x00,0x57,0xf2]
+          vxorpd %xmm18, %xmm21, %xmm22
+
+// CHECK: vxorpd %xmm18, %xmm21, %xmm22 {%k3}
+// CHECK:  encoding: [0x62,0xa1,0xd5,0x03,0x57,0xf2]
+          vxorpd %xmm18, %xmm21, %xmm22 {%k3}
+
+// CHECK: vxorpd %xmm18, %xmm21, %xmm22 {%k3} {z}
+// CHECK:  encoding: [0x62,0xa1,0xd5,0x83,0x57,0xf2]
+          vxorpd %xmm18, %xmm21, %xmm22 {%k3} {z}
+
+// CHECK: vxorpd (%rcx), %xmm21, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x00,0x57,0x31]
+          vxorpd (%rcx), %xmm21, %xmm22
+
+// CHECK: vxorpd 4660(%rax,%r14,8), %xmm21, %xmm22
+// CHECK:  encoding: [0x62,0xa1,0xd5,0x00,0x57,0xb4,0xf0,0x34,0x12,0x00,0x00]
+          vxorpd 4660(%rax,%r14,8), %xmm21, %xmm22
+
+// CHECK: vxorpd (%rcx){1to2}, %xmm21, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x10,0x57,0x31]
+          vxorpd (%rcx){1to2}, %xmm21, %xmm22
+
+// CHECK: vxorpd 2032(%rdx), %xmm21, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x00,0x57,0x72,0x7f]
+          vxorpd 2032(%rdx), %xmm21, %xmm22
+
+// CHECK: vxorpd 2048(%rdx), %xmm21, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x00,0x57,0xb2,0x00,0x08,0x00,0x00]
+          vxorpd 2048(%rdx), %xmm21, %xmm22
+
+// CHECK: vxorpd -2048(%rdx), %xmm21, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x00,0x57,0x72,0x80]
+          vxorpd -2048(%rdx), %xmm21, %xmm22
+
+// CHECK: vxorpd -2064(%rdx), %xmm21, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x00,0x57,0xb2,0xf0,0xf7,0xff,0xff]
+          vxorpd -2064(%rdx), %xmm21, %xmm22
+
+// CHECK: vxorpd 1016(%rdx){1to2}, %xmm21, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x10,0x57,0x72,0x7f]
+          vxorpd 1016(%rdx){1to2}, %xmm21, %xmm22
+
+// CHECK: vxorpd 1024(%rdx){1to2}, %xmm21, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x10,0x57,0xb2,0x00,0x04,0x00,0x00]
+          vxorpd 1024(%rdx){1to2}, %xmm21, %xmm22
+
+// CHECK: vxorpd -1024(%rdx){1to2}, %xmm21, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x10,0x57,0x72,0x80]
+          vxorpd -1024(%rdx){1to2}, %xmm21, %xmm22
+
+// CHECK: vxorpd -1032(%rdx){1to2}, %xmm21, %xmm22
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x10,0x57,0xb2,0xf8,0xfb,0xff,0xff]
+          vxorpd -1032(%rdx){1to2}, %xmm21, %xmm22
+
+// CHECK: vxorpd %ymm27, %ymm21, %ymm25
+// CHECK:  encoding: [0x62,0x01,0xd5,0x20,0x57,0xcb]
+          vxorpd %ymm27, %ymm21, %ymm25
+
+// CHECK: vxorpd %ymm27, %ymm21, %ymm25 {%k7}
+// CHECK:  encoding: [0x62,0x01,0xd5,0x27,0x57,0xcb]
+          vxorpd %ymm27, %ymm21, %ymm25 {%k7}
+
+// CHECK: vxorpd %ymm27, %ymm21, %ymm25 {%k7} {z}
+// CHECK:  encoding: [0x62,0x01,0xd5,0xa7,0x57,0xcb]
+          vxorpd %ymm27, %ymm21, %ymm25 {%k7} {z}
+
+// CHECK: vxorpd (%rcx), %ymm21, %ymm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x20,0x57,0x09]
+          vxorpd (%rcx), %ymm21, %ymm25
+
+// CHECK: vxorpd 4660(%rax,%r14,8), %ymm21, %ymm25
+// CHECK:  encoding: [0x62,0x21,0xd5,0x20,0x57,0x8c,0xf0,0x34,0x12,0x00,0x00]
+          vxorpd 4660(%rax,%r14,8), %ymm21, %ymm25
+
+// CHECK: vxorpd (%rcx){1to4}, %ymm21, %ymm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x30,0x57,0x09]
+          vxorpd (%rcx){1to4}, %ymm21, %ymm25
+
+// CHECK: vxorpd 4064(%rdx), %ymm21, %ymm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x20,0x57,0x4a,0x7f]
+          vxorpd 4064(%rdx), %ymm21, %ymm25
+
+// CHECK: vxorpd 4096(%rdx), %ymm21, %ymm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x20,0x57,0x8a,0x00,0x10,0x00,0x00]
+          vxorpd 4096(%rdx), %ymm21, %ymm25
+
+// CHECK: vxorpd -4096(%rdx), %ymm21, %ymm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x20,0x57,0x4a,0x80]
+          vxorpd -4096(%rdx), %ymm21, %ymm25
+
+// CHECK: vxorpd -4128(%rdx), %ymm21, %ymm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x20,0x57,0x8a,0xe0,0xef,0xff,0xff]
+          vxorpd -4128(%rdx), %ymm21, %ymm25
+
+// CHECK: vxorpd 1016(%rdx){1to4}, %ymm21, %ymm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x30,0x57,0x4a,0x7f]
+          vxorpd 1016(%rdx){1to4}, %ymm21, %ymm25
+
+// CHECK: vxorpd 1024(%rdx){1to4}, %ymm21, %ymm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x30,0x57,0x8a,0x00,0x04,0x00,0x00]
+          vxorpd 1024(%rdx){1to4}, %ymm21, %ymm25
+
+// CHECK: vxorpd -1024(%rdx){1to4}, %ymm21, %ymm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x30,0x57,0x4a,0x80]
+          vxorpd -1024(%rdx){1to4}, %ymm21, %ymm25
+
+// CHECK: vxorpd -1032(%rdx){1to4}, %ymm21, %ymm25
+// CHECK:  encoding: [0x62,0x61,0xd5,0x30,0x57,0x8a,0xf8,0xfb,0xff,0xff]
+          vxorpd -1032(%rdx){1to4}, %ymm21, %ymm25
+
+// CHECK: vxorps %xmm21, %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xa1,0x54,0x00,0x57,0xcd]
+          vxorps %xmm21, %xmm21, %xmm17
+
+// CHECK: vxorps %xmm21, %xmm21, %xmm17 {%k5}
+// CHECK:  encoding: [0x62,0xa1,0x54,0x05,0x57,0xcd]
+          vxorps %xmm21, %xmm21, %xmm17 {%k5}
+
+// CHECK: vxorps %xmm21, %xmm21, %xmm17 {%k5} {z}
+// CHECK:  encoding: [0x62,0xa1,0x54,0x85,0x57,0xcd]
+          vxorps %xmm21, %xmm21, %xmm17 {%k5} {z}
+
+// CHECK: vxorps (%rcx), %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x00,0x57,0x09]
+          vxorps (%rcx), %xmm21, %xmm17
+
+// CHECK: vxorps 4660(%rax,%r14,8), %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xa1,0x54,0x00,0x57,0x8c,0xf0,0x34,0x12,0x00,0x00]
+          vxorps 4660(%rax,%r14,8), %xmm21, %xmm17
+
+// CHECK: vxorps (%rcx){1to4}, %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x10,0x57,0x09]
+          vxorps (%rcx){1to4}, %xmm21, %xmm17
+
+// CHECK: vxorps 2032(%rdx), %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x00,0x57,0x4a,0x7f]
+          vxorps 2032(%rdx), %xmm21, %xmm17
+
+// CHECK: vxorps 2048(%rdx), %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x00,0x57,0x8a,0x00,0x08,0x00,0x00]
+          vxorps 2048(%rdx), %xmm21, %xmm17
+
+// CHECK: vxorps -2048(%rdx), %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x00,0x57,0x4a,0x80]
+          vxorps -2048(%rdx), %xmm21, %xmm17
+
+// CHECK: vxorps -2064(%rdx), %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x00,0x57,0x8a,0xf0,0xf7,0xff,0xff]
+          vxorps -2064(%rdx), %xmm21, %xmm17
+
+// CHECK: vxorps 508(%rdx){1to4}, %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x10,0x57,0x4a,0x7f]
+          vxorps 508(%rdx){1to4}, %xmm21, %xmm17
+
+// CHECK: vxorps 512(%rdx){1to4}, %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x10,0x57,0x8a,0x00,0x02,0x00,0x00]
+          vxorps 512(%rdx){1to4}, %xmm21, %xmm17
+
+// CHECK: vxorps -512(%rdx){1to4}, %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x10,0x57,0x4a,0x80]
+          vxorps -512(%rdx){1to4}, %xmm21, %xmm17
+
+// CHECK: vxorps -516(%rdx){1to4}, %xmm21, %xmm17
+// CHECK:  encoding: [0x62,0xe1,0x54,0x10,0x57,0x8a,0xfc,0xfd,0xff,0xff]
+          vxorps -516(%rdx){1to4}, %xmm21, %xmm17
+
+// CHECK: vxorps %ymm22, %ymm25, %ymm28
+// CHECK:  encoding: [0x62,0x21,0x34,0x20,0x57,0xe6]
+          vxorps %ymm22, %ymm25, %ymm28
+
+// CHECK: vxorps %ymm22, %ymm25, %ymm28 {%k3}
+// CHECK:  encoding: [0x62,0x21,0x34,0x23,0x57,0xe6]
+          vxorps %ymm22, %ymm25, %ymm28 {%k3}
+
+// CHECK: vxorps %ymm22, %ymm25, %ymm28 {%k3} {z}
+// CHECK:  encoding: [0x62,0x21,0x34,0xa3,0x57,0xe6]
+          vxorps %ymm22, %ymm25, %ymm28 {%k3} {z}
+
+// CHECK: vxorps (%rcx), %ymm25, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x34,0x20,0x57,0x21]
+          vxorps (%rcx), %ymm25, %ymm28
+
+// CHECK: vxorps 4660(%rax,%r14,8), %ymm25, %ymm28
+// CHECK:  encoding: [0x62,0x21,0x34,0x20,0x57,0xa4,0xf0,0x34,0x12,0x00,0x00]
+          vxorps 4660(%rax,%r14,8), %ymm25, %ymm28
+
+// CHECK: vxorps (%rcx){1to8}, %ymm25, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x34,0x30,0x57,0x21]
+          vxorps (%rcx){1to8}, %ymm25, %ymm28
+
+// CHECK: vxorps 4064(%rdx), %ymm25, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x34,0x20,0x57,0x62,0x7f]
+          vxorps 4064(%rdx), %ymm25, %ymm28
+
+// CHECK: vxorps 4096(%rdx), %ymm25, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x34,0x20,0x57,0xa2,0x00,0x10,0x00,0x00]
+          vxorps 4096(%rdx), %ymm25, %ymm28
+
+// CHECK: vxorps -4096(%rdx), %ymm25, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x34,0x20,0x57,0x62,0x80]
+          vxorps -4096(%rdx), %ymm25, %ymm28
+
+// CHECK: vxorps -4128(%rdx), %ymm25, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x34,0x20,0x57,0xa2,0xe0,0xef,0xff,0xff]
+          vxorps -4128(%rdx), %ymm25, %ymm28
+
+// CHECK: vxorps 508(%rdx){1to8}, %ymm25, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x34,0x30,0x57,0x62,0x7f]
+          vxorps 508(%rdx){1to8}, %ymm25, %ymm28
+
+// CHECK: vxorps 512(%rdx){1to8}, %ymm25, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x34,0x30,0x57,0xa2,0x00,0x02,0x00,0x00]
+          vxorps 512(%rdx){1to8}, %ymm25, %ymm28
+
+// CHECK: vxorps -512(%rdx){1to8}, %ymm25, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x34,0x30,0x57,0x62,0x80]
+          vxorps -512(%rdx){1to8}, %ymm25, %ymm28
+
+// CHECK: vxorps -516(%rdx){1to8}, %ymm25, %ymm28
+// CHECK:  encoding: [0x62,0x61,0x34,0x30,0x57,0xa2,0xfc,0xfd,0xff,0xff]
+          vxorps -516(%rdx){1to8}, %ymm25, %ymm28
+
+// CHECK: vbroadcastf64x2 (%rcx), %ymm27
+// CHECK:  encoding: [0x62,0x62,0xfd,0x28,0x1a,0x19]
+          vbroadcastf64x2 (%rcx), %ymm27
+
+// CHECK: vbroadcastf64x2 (%rcx), %ymm27 {%k5}
+// CHECK:  encoding: [0x62,0x62,0xfd,0x2d,0x1a,0x19]
+          vbroadcastf64x2 (%rcx), %ymm27 {%k5}
+
+// CHECK: vbroadcastf64x2 (%rcx), %ymm27 {%k5} {z}
+// CHECK:  encoding: [0x62,0x62,0xfd,0xad,0x1a,0x19]
+          vbroadcastf64x2 (%rcx), %ymm27 {%k5} {z}
+
+// CHECK: vbroadcastf64x2 291(%rax,%r14,8), %ymm27
+// CHECK:  encoding: [0x62,0x22,0xfd,0x28,0x1a,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vbroadcastf64x2 291(%rax,%r14,8), %ymm27
+
+// CHECK: vbroadcastf64x2 2032(%rdx), %ymm27
+// CHECK:  encoding: [0x62,0x62,0xfd,0x28,0x1a,0x5a,0x7f]
+          vbroadcastf64x2 2032(%rdx), %ymm27
+
+// CHECK: vbroadcastf64x2 2048(%rdx), %ymm27
+// CHECK:  encoding: [0x62,0x62,0xfd,0x28,0x1a,0x9a,0x00,0x08,0x00,0x00]
+          vbroadcastf64x2 2048(%rdx), %ymm27
+
+// CHECK: vbroadcastf64x2 -2048(%rdx), %ymm27
+// CHECK:  encoding: [0x62,0x62,0xfd,0x28,0x1a,0x5a,0x80]
+          vbroadcastf64x2 -2048(%rdx), %ymm27
+
+// CHECK: vbroadcastf64x2 -2064(%rdx), %ymm27
+// CHECK:  encoding: [0x62,0x62,0xfd,0x28,0x1a,0x9a,0xf0,0xf7,0xff,0xff]
+          vbroadcastf64x2 -2064(%rdx), %ymm27
+
+// CHECK: vbroadcasti64x2 (%rcx), %ymm18
+// CHECK:  encoding: [0x62,0xe2,0xfd,0x28,0x5a,0x11]
+          vbroadcasti64x2 (%rcx), %ymm18
+
+// CHECK: vbroadcasti64x2 (%rcx), %ymm18 {%k1}
+// CHECK:  encoding: [0x62,0xe2,0xfd,0x29,0x5a,0x11]
+          vbroadcasti64x2 (%rcx), %ymm18 {%k1}
+
+// CHECK: vbroadcasti64x2 (%rcx), %ymm18 {%k1} {z}
+// CHECK:  encoding: [0x62,0xe2,0xfd,0xa9,0x5a,0x11]
+          vbroadcasti64x2 (%rcx), %ymm18 {%k1} {z}
+
+// CHECK: vbroadcasti64x2 291(%rax,%r14,8), %ymm18
+// CHECK:  encoding: [0x62,0xa2,0xfd,0x28,0x5a,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vbroadcasti64x2 291(%rax,%r14,8), %ymm18
+
+// CHECK: vbroadcasti64x2 2032(%rdx), %ymm18
+// CHECK:  encoding: [0x62,0xe2,0xfd,0x28,0x5a,0x52,0x7f]
+          vbroadcasti64x2 2032(%rdx), %ymm18
+
+// CHECK: vbroadcasti64x2 2048(%rdx), %ymm18
+// CHECK:  encoding: [0x62,0xe2,0xfd,0x28,0x5a,0x92,0x00,0x08,0x00,0x00]
+          vbroadcasti64x2 2048(%rdx), %ymm18
+
+// CHECK: vbroadcasti64x2 -2048(%rdx), %ymm18
+// CHECK:  encoding: [0x62,0xe2,0xfd,0x28,0x5a,0x52,0x80]
+          vbroadcasti64x2 -2048(%rdx), %ymm18
+
+// CHECK: vbroadcasti64x2 -2064(%rdx), %ymm18
+// CHECK:  encoding: [0x62,0xe2,0xfd,0x28,0x5a,0x92,0xf0,0xf7,0xff,0xff]
+          vbroadcasti64x2 -2064(%rdx), %ymm18
+
diff --git a/test/MC/X86/x86-64-avx512f_vl.s b/test/MC/X86/x86-64-avx512f_vl.s
index ad121dc7d0da..500772681707 100644
--- a/test/MC/X86/x86-64-avx512f_vl.s
+++ b/test/MC/X86/x86-64-avx512f_vl.s
@@ -4524,6 +4524,726 @@
 // CHECK:  encoding: [0x62,0x62,0xd5,0x30,0x3b,0xaa,0xf8,0xfb,0xff,0xff]
           vpminuq -1032(%rdx){1to4}, %ymm21, %ymm29
 
+// CHECK: vpmovsxbd %xmm28, %xmm24
+// CHECK:  encoding: [0x62,0x02,0x7d,0x08,0x21,0xc4]
+          vpmovsxbd %xmm28, %xmm24
+
+// CHECK: vpmovsxbd %xmm28, %xmm24 {%k1}
+// CHECK:  encoding: [0x62,0x02,0x7d,0x09,0x21,0xc4]
+          vpmovsxbd %xmm28, %xmm24 {%k1}
+
+// CHECK: vpmovsxbd %xmm28, %xmm24 {%k1} {z}
+// CHECK:  encoding: [0x62,0x02,0x7d,0x89,0x21,0xc4]
+          vpmovsxbd %xmm28, %xmm24 {%k1} {z}
+
+// CHECK: vpmovsxbd (%rcx), %xmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x21,0x01]
+          vpmovsxbd (%rcx), %xmm24
+
+// CHECK: vpmovsxbd 291(%rax,%r14,8), %xmm24
+// CHECK:  encoding: [0x62,0x22,0x7d,0x08,0x21,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vpmovsxbd 291(%rax,%r14,8), %xmm24
+
+// CHECK: vpmovsxbd 508(%rdx), %xmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x21,0x42,0x7f]
+          vpmovsxbd 508(%rdx), %xmm24
+
+// CHECK: vpmovsxbd 512(%rdx), %xmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x21,0x82,0x00,0x02,0x00,0x00]
+          vpmovsxbd 512(%rdx), %xmm24
+
+// CHECK: vpmovsxbd -512(%rdx), %xmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x21,0x42,0x80]
+          vpmovsxbd -512(%rdx), %xmm24
+
+// CHECK: vpmovsxbd -516(%rdx), %xmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x21,0x82,0xfc,0xfd,0xff,0xff]
+          vpmovsxbd -516(%rdx), %xmm24
+
+// CHECK: vpmovsxbd %xmm20, %ymm24
+// CHECK:  encoding: [0x62,0x22,0x7d,0x28,0x21,0xc4]
+          vpmovsxbd %xmm20, %ymm24
+
+// CHECK: vpmovsxbd %xmm20, %ymm24 {%k3}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x2b,0x21,0xc4]
+          vpmovsxbd %xmm20, %ymm24 {%k3}
+
+// CHECK: vpmovsxbd %xmm20, %ymm24 {%k3} {z}
+// CHECK:  encoding: [0x62,0x22,0x7d,0xab,0x21,0xc4]
+          vpmovsxbd %xmm20, %ymm24 {%k3} {z}
+
+// CHECK: vpmovsxbd (%rcx), %ymm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x21,0x01]
+          vpmovsxbd (%rcx), %ymm24
+
+// CHECK: vpmovsxbd 291(%rax,%r14,8), %ymm24
+// CHECK:  encoding: [0x62,0x22,0x7d,0x28,0x21,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vpmovsxbd 291(%rax,%r14,8), %ymm24
+
+// CHECK: vpmovsxbd 1016(%rdx), %ymm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x21,0x42,0x7f]
+          vpmovsxbd 1016(%rdx), %ymm24
+
+// CHECK: vpmovsxbd 1024(%rdx), %ymm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x21,0x82,0x00,0x04,0x00,0x00]
+          vpmovsxbd 1024(%rdx), %ymm24
+
+// CHECK: vpmovsxbd -1024(%rdx), %ymm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x21,0x42,0x80]
+          vpmovsxbd -1024(%rdx), %ymm24
+
+// CHECK: vpmovsxbd -1032(%rdx), %ymm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x21,0x82,0xf8,0xfb,0xff,0xff]
+          vpmovsxbd -1032(%rdx), %ymm24
+
+// CHECK: vpmovsxbq %xmm22, %xmm17
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x08,0x22,0xce]
+          vpmovsxbq %xmm22, %xmm17
+
+// CHECK: vpmovsxbq %xmm22, %xmm17 {%k5}
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x0d,0x22,0xce]
+          vpmovsxbq %xmm22, %xmm17 {%k5}
+
+// CHECK: vpmovsxbq %xmm22, %xmm17 {%k5} {z}
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x8d,0x22,0xce]
+          vpmovsxbq %xmm22, %xmm17 {%k5} {z}
+
+// CHECK: vpmovsxbq (%rcx), %xmm17
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x22,0x09]
+          vpmovsxbq (%rcx), %xmm17
+
+// CHECK: vpmovsxbq 291(%rax,%r14,8), %xmm17
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x08,0x22,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpmovsxbq 291(%rax,%r14,8), %xmm17
+
+// CHECK: vpmovsxbq 254(%rdx), %xmm17
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x22,0x4a,0x7f]
+          vpmovsxbq 254(%rdx), %xmm17
+
+// CHECK: vpmovsxbq 256(%rdx), %xmm17
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x22,0x8a,0x00,0x01,0x00,0x00]
+          vpmovsxbq 256(%rdx), %xmm17
+
+// CHECK: vpmovsxbq -256(%rdx), %xmm17
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x22,0x4a,0x80]
+          vpmovsxbq -256(%rdx), %xmm17
+
+// CHECK: vpmovsxbq -258(%rdx), %xmm17
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x22,0x8a,0xfe,0xfe,0xff,0xff]
+          vpmovsxbq -258(%rdx), %xmm17
+
+// CHECK: vpmovsxbq %xmm26, %ymm28
+// CHECK:  encoding: [0x62,0x02,0x7d,0x28,0x22,0xe2]
+          vpmovsxbq %xmm26, %ymm28
+
+// CHECK: vpmovsxbq %xmm26, %ymm28 {%k5}
+// CHECK:  encoding: [0x62,0x02,0x7d,0x2d,0x22,0xe2]
+          vpmovsxbq %xmm26, %ymm28 {%k5}
+
+// CHECK: vpmovsxbq %xmm26, %ymm28 {%k5} {z}
+// CHECK:  encoding: [0x62,0x02,0x7d,0xad,0x22,0xe2]
+          vpmovsxbq %xmm26, %ymm28 {%k5} {z}
+
+// CHECK: vpmovsxbq (%rcx), %ymm28
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x22,0x21]
+          vpmovsxbq (%rcx), %ymm28
+
+// CHECK: vpmovsxbq 291(%rax,%r14,8), %ymm28
+// CHECK:  encoding: [0x62,0x22,0x7d,0x28,0x22,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpmovsxbq 291(%rax,%r14,8), %ymm28
+
+// CHECK: vpmovsxbq 508(%rdx), %ymm28
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x22,0x62,0x7f]
+          vpmovsxbq 508(%rdx), %ymm28
+
+// CHECK: vpmovsxbq 512(%rdx), %ymm28
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x22,0xa2,0x00,0x02,0x00,0x00]
+          vpmovsxbq 512(%rdx), %ymm28
+
+// CHECK: vpmovsxbq -512(%rdx), %ymm28
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x22,0x62,0x80]
+          vpmovsxbq -512(%rdx), %ymm28
+
+// CHECK: vpmovsxbq -516(%rdx), %ymm28
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x22,0xa2,0xfc,0xfd,0xff,0xff]
+          vpmovsxbq -516(%rdx), %ymm28
+
+// CHECK: vpmovsxdq %xmm26, %xmm23
+// CHECK:  encoding: [0x62,0x82,0x7d,0x08,0x25,0xfa]
+          vpmovsxdq %xmm26, %xmm23
+
+// CHECK: vpmovsxdq %xmm26, %xmm23 {%k7}
+// CHECK:  encoding: [0x62,0x82,0x7d,0x0f,0x25,0xfa]
+          vpmovsxdq %xmm26, %xmm23 {%k7}
+
+// CHECK: vpmovsxdq %xmm26, %xmm23 {%k7} {z}
+// CHECK:  encoding: [0x62,0x82,0x7d,0x8f,0x25,0xfa]
+          vpmovsxdq %xmm26, %xmm23 {%k7} {z}
+
+// CHECK: vpmovsxdq (%rcx), %xmm23
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x25,0x39]
+          vpmovsxdq (%rcx), %xmm23
+
+// CHECK: vpmovsxdq 291(%rax,%r14,8), %xmm23
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x08,0x25,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vpmovsxdq 291(%rax,%r14,8), %xmm23
+
+// CHECK: vpmovsxdq 1016(%rdx), %xmm23
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x25,0x7a,0x7f]
+          vpmovsxdq 1016(%rdx), %xmm23
+
+// CHECK: vpmovsxdq 1024(%rdx), %xmm23
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x25,0xba,0x00,0x04,0x00,0x00]
+          vpmovsxdq 1024(%rdx), %xmm23
+
+// CHECK: vpmovsxdq -1024(%rdx), %xmm23
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x25,0x7a,0x80]
+          vpmovsxdq -1024(%rdx), %xmm23
+
+// CHECK: vpmovsxdq -1032(%rdx), %xmm23
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x25,0xba,0xf8,0xfb,0xff,0xff]
+          vpmovsxdq -1032(%rdx), %xmm23
+
+// CHECK: vpmovsxdq %xmm28, %ymm18
+// CHECK:  encoding: [0x62,0x82,0x7d,0x28,0x25,0xd4]
+          vpmovsxdq %xmm28, %ymm18
+
+// CHECK: vpmovsxdq %xmm28, %ymm18 {%k7}
+// CHECK:  encoding: [0x62,0x82,0x7d,0x2f,0x25,0xd4]
+          vpmovsxdq %xmm28, %ymm18 {%k7}
+
+// CHECK: vpmovsxdq %xmm28, %ymm18 {%k7} {z}
+// CHECK:  encoding: [0x62,0x82,0x7d,0xaf,0x25,0xd4]
+          vpmovsxdq %xmm28, %ymm18 {%k7} {z}
+
+// CHECK: vpmovsxdq (%rcx), %ymm18
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x25,0x11]
+          vpmovsxdq (%rcx), %ymm18
+
+// CHECK: vpmovsxdq 291(%rax,%r14,8), %ymm18
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x28,0x25,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vpmovsxdq 291(%rax,%r14,8), %ymm18
+
+// CHECK: vpmovsxdq 2032(%rdx), %ymm18
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x25,0x52,0x7f]
+          vpmovsxdq 2032(%rdx), %ymm18
+
+// CHECK: vpmovsxdq 2048(%rdx), %ymm18
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x25,0x92,0x00,0x08,0x00,0x00]
+          vpmovsxdq 2048(%rdx), %ymm18
+
+// CHECK: vpmovsxdq -2048(%rdx), %ymm18
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x25,0x52,0x80]
+          vpmovsxdq -2048(%rdx), %ymm18
+
+// CHECK: vpmovsxdq -2064(%rdx), %ymm18
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x25,0x92,0xf0,0xf7,0xff,0xff]
+          vpmovsxdq -2064(%rdx), %ymm18
+
+// CHECK: vpmovsxwd %xmm18, %xmm17
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x08,0x23,0xca]
+          vpmovsxwd %xmm18, %xmm17
+
+// CHECK: vpmovsxwd %xmm18, %xmm17 {%k4}
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x0c,0x23,0xca]
+          vpmovsxwd %xmm18, %xmm17 {%k4}
+
+// CHECK: vpmovsxwd %xmm18, %xmm17 {%k4} {z}
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x8c,0x23,0xca]
+          vpmovsxwd %xmm18, %xmm17 {%k4} {z}
+
+// CHECK: vpmovsxwd (%rcx), %xmm17
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x23,0x09]
+          vpmovsxwd (%rcx), %xmm17
+
+// CHECK: vpmovsxwd 291(%rax,%r14,8), %xmm17
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x08,0x23,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpmovsxwd 291(%rax,%r14,8), %xmm17
+
+// CHECK: vpmovsxwd 1016(%rdx), %xmm17
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x23,0x4a,0x7f]
+          vpmovsxwd 1016(%rdx), %xmm17
+
+// CHECK: vpmovsxwd 1024(%rdx), %xmm17
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x23,0x8a,0x00,0x04,0x00,0x00]
+          vpmovsxwd 1024(%rdx), %xmm17
+
+// CHECK: vpmovsxwd -1024(%rdx), %xmm17
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x23,0x4a,0x80]
+          vpmovsxwd -1024(%rdx), %xmm17
+
+// CHECK: vpmovsxwd -1032(%rdx), %xmm17
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x23,0x8a,0xf8,0xfb,0xff,0xff]
+          vpmovsxwd -1032(%rdx), %xmm17
+
+// CHECK: vpmovsxwd %xmm25, %ymm21
+// CHECK:  encoding: [0x62,0x82,0x7d,0x28,0x23,0xe9]
+          vpmovsxwd %xmm25, %ymm21
+
+// CHECK: vpmovsxwd %xmm25, %ymm21 {%k5}
+// CHECK:  encoding: [0x62,0x82,0x7d,0x2d,0x23,0xe9]
+          vpmovsxwd %xmm25, %ymm21 {%k5}
+
+// CHECK: vpmovsxwd %xmm25, %ymm21 {%k5} {z}
+// CHECK:  encoding: [0x62,0x82,0x7d,0xad,0x23,0xe9]
+          vpmovsxwd %xmm25, %ymm21 {%k5} {z}
+
+// CHECK: vpmovsxwd (%rcx), %ymm21
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x23,0x29]
+          vpmovsxwd (%rcx), %ymm21
+
+// CHECK: vpmovsxwd 291(%rax,%r14,8), %ymm21
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x28,0x23,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpmovsxwd 291(%rax,%r14,8), %ymm21
+
+// CHECK: vpmovsxwd 2032(%rdx), %ymm21
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x23,0x6a,0x7f]
+          vpmovsxwd 2032(%rdx), %ymm21
+
+// CHECK: vpmovsxwd 2048(%rdx), %ymm21
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x23,0xaa,0x00,0x08,0x00,0x00]
+          vpmovsxwd 2048(%rdx), %ymm21
+
+// CHECK: vpmovsxwd -2048(%rdx), %ymm21
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x23,0x6a,0x80]
+          vpmovsxwd -2048(%rdx), %ymm21
+
+// CHECK: vpmovsxwd -2064(%rdx), %ymm21
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x23,0xaa,0xf0,0xf7,0xff,0xff]
+          vpmovsxwd -2064(%rdx), %ymm21
+
+// CHECK: vpmovsxwq %xmm20, %xmm29
+// CHECK:  encoding: [0x62,0x22,0x7d,0x08,0x24,0xec]
+          vpmovsxwq %xmm20, %xmm29
+
+// CHECK: vpmovsxwq %xmm20, %xmm29 {%k6}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x0e,0x24,0xec]
+          vpmovsxwq %xmm20, %xmm29 {%k6}
+
+// CHECK: vpmovsxwq %xmm20, %xmm29 {%k6} {z}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x8e,0x24,0xec]
+          vpmovsxwq %xmm20, %xmm29 {%k6} {z}
+
+// CHECK: vpmovsxwq (%rcx), %xmm29
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x24,0x29]
+          vpmovsxwq (%rcx), %xmm29
+
+// CHECK: vpmovsxwq 291(%rax,%r14,8), %xmm29
+// CHECK:  encoding: [0x62,0x22,0x7d,0x08,0x24,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpmovsxwq 291(%rax,%r14,8), %xmm29
+
+// CHECK: vpmovsxwq 508(%rdx), %xmm29
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x24,0x6a,0x7f]
+          vpmovsxwq 508(%rdx), %xmm29
+
+// CHECK: vpmovsxwq 512(%rdx), %xmm29
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x24,0xaa,0x00,0x02,0x00,0x00]
+          vpmovsxwq 512(%rdx), %xmm29
+
+// CHECK: vpmovsxwq -512(%rdx), %xmm29
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x24,0x6a,0x80]
+          vpmovsxwq -512(%rdx), %xmm29
+
+// CHECK: vpmovsxwq -516(%rdx), %xmm29
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x24,0xaa,0xfc,0xfd,0xff,0xff]
+          vpmovsxwq -516(%rdx), %xmm29
+
+// CHECK: vpmovsxwq %xmm17, %ymm23
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x28,0x24,0xf9]
+          vpmovsxwq %xmm17, %ymm23
+
+// CHECK: vpmovsxwq %xmm17, %ymm23 {%k5}
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x2d,0x24,0xf9]
+          vpmovsxwq %xmm17, %ymm23 {%k5}
+
+// CHECK: vpmovsxwq %xmm17, %ymm23 {%k5} {z}
+// CHECK:  encoding: [0x62,0xa2,0x7d,0xad,0x24,0xf9]
+          vpmovsxwq %xmm17, %ymm23 {%k5} {z}
+
+// CHECK: vpmovsxwq (%rcx), %ymm23
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x24,0x39]
+          vpmovsxwq (%rcx), %ymm23
+
+// CHECK: vpmovsxwq 291(%rax,%r14,8), %ymm23
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x28,0x24,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vpmovsxwq 291(%rax,%r14,8), %ymm23
+
+// CHECK: vpmovsxwq 1016(%rdx), %ymm23
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x24,0x7a,0x7f]
+          vpmovsxwq 1016(%rdx), %ymm23
+
+// CHECK: vpmovsxwq 1024(%rdx), %ymm23
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x24,0xba,0x00,0x04,0x00,0x00]
+          vpmovsxwq 1024(%rdx), %ymm23
+
+// CHECK: vpmovsxwq -1024(%rdx), %ymm23
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x24,0x7a,0x80]
+          vpmovsxwq -1024(%rdx), %ymm23
+
+// CHECK: vpmovsxwq -1032(%rdx), %ymm23
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x24,0xba,0xf8,0xfb,0xff,0xff]
+          vpmovsxwq -1032(%rdx), %ymm23
+
+// CHECK: vpmovzxbd %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x22,0x7d,0x08,0x31,0xc1]
+          vpmovzxbd %xmm17, %xmm24
+
+// CHECK: vpmovzxbd %xmm17, %xmm24 {%k6}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x0e,0x31,0xc1]
+          vpmovzxbd %xmm17, %xmm24 {%k6}
+
+// CHECK: vpmovzxbd %xmm17, %xmm24 {%k6} {z}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x8e,0x31,0xc1]
+          vpmovzxbd %xmm17, %xmm24 {%k6} {z}
+
+// CHECK: vpmovzxbd (%rcx), %xmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x31,0x01]
+          vpmovzxbd (%rcx), %xmm24
+
+// CHECK: vpmovzxbd 291(%rax,%r14,8), %xmm24
+// CHECK:  encoding: [0x62,0x22,0x7d,0x08,0x31,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vpmovzxbd 291(%rax,%r14,8), %xmm24
+
+// CHECK: vpmovzxbd 508(%rdx), %xmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x31,0x42,0x7f]
+          vpmovzxbd 508(%rdx), %xmm24
+
+// CHECK: vpmovzxbd 512(%rdx), %xmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x31,0x82,0x00,0x02,0x00,0x00]
+          vpmovzxbd 512(%rdx), %xmm24
+
+// CHECK: vpmovzxbd -512(%rdx), %xmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x31,0x42,0x80]
+          vpmovzxbd -512(%rdx), %xmm24
+
+// CHECK: vpmovzxbd -516(%rdx), %xmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x31,0x82,0xfc,0xfd,0xff,0xff]
+          vpmovzxbd -516(%rdx), %xmm24
+
+// CHECK: vpmovzxbd %xmm17, %ymm27
+// CHECK:  encoding: [0x62,0x22,0x7d,0x28,0x31,0xd9]
+          vpmovzxbd %xmm17, %ymm27
+
+// CHECK: vpmovzxbd %xmm17, %ymm27 {%k1}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x29,0x31,0xd9]
+          vpmovzxbd %xmm17, %ymm27 {%k1}
+
+// CHECK: vpmovzxbd %xmm17, %ymm27 {%k1} {z}
+// CHECK:  encoding: [0x62,0x22,0x7d,0xa9,0x31,0xd9]
+          vpmovzxbd %xmm17, %ymm27 {%k1} {z}
+
+// CHECK: vpmovzxbd (%rcx), %ymm27
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x31,0x19]
+          vpmovzxbd (%rcx), %ymm27
+
+// CHECK: vpmovzxbd 291(%rax,%r14,8), %ymm27
+// CHECK:  encoding: [0x62,0x22,0x7d,0x28,0x31,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpmovzxbd 291(%rax,%r14,8), %ymm27
+
+// CHECK: vpmovzxbd 1016(%rdx), %ymm27
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x31,0x5a,0x7f]
+          vpmovzxbd 1016(%rdx), %ymm27
+
+// CHECK: vpmovzxbd 1024(%rdx), %ymm27
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x31,0x9a,0x00,0x04,0x00,0x00]
+          vpmovzxbd 1024(%rdx), %ymm27
+
+// CHECK: vpmovzxbd -1024(%rdx), %ymm27
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x31,0x5a,0x80]
+          vpmovzxbd -1024(%rdx), %ymm27
+
+// CHECK: vpmovzxbd -1032(%rdx), %ymm27
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x31,0x9a,0xf8,0xfb,0xff,0xff]
+          vpmovzxbd -1032(%rdx), %ymm27
+
+// CHECK: vpmovzxbq %xmm19, %xmm19
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x08,0x32,0xdb]
+          vpmovzxbq %xmm19, %xmm19
+
+// CHECK: vpmovzxbq %xmm19, %xmm19 {%k1}
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x09,0x32,0xdb]
+          vpmovzxbq %xmm19, %xmm19 {%k1}
+
+// CHECK: vpmovzxbq %xmm19, %xmm19 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x89,0x32,0xdb]
+          vpmovzxbq %xmm19, %xmm19 {%k1} {z}
+
+// CHECK: vpmovzxbq (%rcx), %xmm19
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x32,0x19]
+          vpmovzxbq (%rcx), %xmm19
+
+// CHECK: vpmovzxbq 291(%rax,%r14,8), %xmm19
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x08,0x32,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpmovzxbq 291(%rax,%r14,8), %xmm19
+
+// CHECK: vpmovzxbq 254(%rdx), %xmm19
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x32,0x5a,0x7f]
+          vpmovzxbq 254(%rdx), %xmm19
+
+// CHECK: vpmovzxbq 256(%rdx), %xmm19
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x32,0x9a,0x00,0x01,0x00,0x00]
+          vpmovzxbq 256(%rdx), %xmm19
+
+// CHECK: vpmovzxbq -256(%rdx), %xmm19
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x32,0x5a,0x80]
+          vpmovzxbq -256(%rdx), %xmm19
+
+// CHECK: vpmovzxbq -258(%rdx), %xmm19
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x08,0x32,0x9a,0xfe,0xfe,0xff,0xff]
+          vpmovzxbq -258(%rdx), %xmm19
+
+// CHECK: vpmovzxbq %xmm19, %ymm24
+// CHECK:  encoding: [0x62,0x22,0x7d,0x28,0x32,0xc3]
+          vpmovzxbq %xmm19, %ymm24
+
+// CHECK: vpmovzxbq %xmm19, %ymm24 {%k2}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x2a,0x32,0xc3]
+          vpmovzxbq %xmm19, %ymm24 {%k2}
+
+// CHECK: vpmovzxbq %xmm19, %ymm24 {%k2} {z}
+// CHECK:  encoding: [0x62,0x22,0x7d,0xaa,0x32,0xc3]
+          vpmovzxbq %xmm19, %ymm24 {%k2} {z}
+
+// CHECK: vpmovzxbq (%rcx), %ymm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x32,0x01]
+          vpmovzxbq (%rcx), %ymm24
+
+// CHECK: vpmovzxbq 291(%rax,%r14,8), %ymm24
+// CHECK:  encoding: [0x62,0x22,0x7d,0x28,0x32,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vpmovzxbq 291(%rax,%r14,8), %ymm24
+
+// CHECK: vpmovzxbq 508(%rdx), %ymm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x32,0x42,0x7f]
+          vpmovzxbq 508(%rdx), %ymm24
+
+// CHECK: vpmovzxbq 512(%rdx), %ymm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x32,0x82,0x00,0x02,0x00,0x00]
+          vpmovzxbq 512(%rdx), %ymm24
+
+// CHECK: vpmovzxbq -512(%rdx), %ymm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x32,0x42,0x80]
+          vpmovzxbq -512(%rdx), %ymm24
+
+// CHECK: vpmovzxbq -516(%rdx), %ymm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x32,0x82,0xfc,0xfd,0xff,0xff]
+          vpmovzxbq -516(%rdx), %ymm24
+
+// CHECK: vpmovzxdq %xmm21, %xmm25
+// CHECK:  encoding: [0x62,0x22,0x7d,0x08,0x35,0xcd]
+          vpmovzxdq %xmm21, %xmm25
+
+// CHECK: vpmovzxdq %xmm21, %xmm25 {%k7}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x0f,0x35,0xcd]
+          vpmovzxdq %xmm21, %xmm25 {%k7}
+
+// CHECK: vpmovzxdq %xmm21, %xmm25 {%k7} {z}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x8f,0x35,0xcd]
+          vpmovzxdq %xmm21, %xmm25 {%k7} {z}
+
+// CHECK: vpmovzxdq (%rcx), %xmm25
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x35,0x09]
+          vpmovzxdq (%rcx), %xmm25
+
+// CHECK: vpmovzxdq 291(%rax,%r14,8), %xmm25
+// CHECK:  encoding: [0x62,0x22,0x7d,0x08,0x35,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpmovzxdq 291(%rax,%r14,8), %xmm25
+
+// CHECK: vpmovzxdq 1016(%rdx), %xmm25
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x35,0x4a,0x7f]
+          vpmovzxdq 1016(%rdx), %xmm25
+
+// CHECK: vpmovzxdq 1024(%rdx), %xmm25
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x35,0x8a,0x00,0x04,0x00,0x00]
+          vpmovzxdq 1024(%rdx), %xmm25
+
+// CHECK: vpmovzxdq -1024(%rdx), %xmm25
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x35,0x4a,0x80]
+          vpmovzxdq -1024(%rdx), %xmm25
+
+// CHECK: vpmovzxdq -1032(%rdx), %xmm25
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x35,0x8a,0xf8,0xfb,0xff,0xff]
+          vpmovzxdq -1032(%rdx), %xmm25
+
+// CHECK: vpmovzxdq %xmm22, %ymm28
+// CHECK:  encoding: [0x62,0x22,0x7d,0x28,0x35,0xe6]
+          vpmovzxdq %xmm22, %ymm28
+
+// CHECK: vpmovzxdq %xmm22, %ymm28 {%k7}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x2f,0x35,0xe6]
+          vpmovzxdq %xmm22, %ymm28 {%k7}
+
+// CHECK: vpmovzxdq %xmm22, %ymm28 {%k7} {z}
+// CHECK:  encoding: [0x62,0x22,0x7d,0xaf,0x35,0xe6]
+          vpmovzxdq %xmm22, %ymm28 {%k7} {z}
+
+// CHECK: vpmovzxdq (%rcx), %ymm28
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x35,0x21]
+          vpmovzxdq (%rcx), %ymm28
+
+// CHECK: vpmovzxdq 291(%rax,%r14,8), %ymm28
+// CHECK:  encoding: [0x62,0x22,0x7d,0x28,0x35,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpmovzxdq 291(%rax,%r14,8), %ymm28
+
+// CHECK: vpmovzxdq 2032(%rdx), %ymm28
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x35,0x62,0x7f]
+          vpmovzxdq 2032(%rdx), %ymm28
+
+// CHECK: vpmovzxdq 2048(%rdx), %ymm28
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x35,0xa2,0x00,0x08,0x00,0x00]
+          vpmovzxdq 2048(%rdx), %ymm28
+
+// CHECK: vpmovzxdq -2048(%rdx), %ymm28
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x35,0x62,0x80]
+          vpmovzxdq -2048(%rdx), %ymm28
+
+// CHECK: vpmovzxdq -2064(%rdx), %ymm28
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x35,0xa2,0xf0,0xf7,0xff,0xff]
+          vpmovzxdq -2064(%rdx), %ymm28
+
+// CHECK: vpmovzxwd %xmm17, %xmm24
+// CHECK:  encoding: [0x62,0x22,0x7d,0x08,0x33,0xc1]
+          vpmovzxwd %xmm17, %xmm24
+
+// CHECK: vpmovzxwd %xmm17, %xmm24 {%k4}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x0c,0x33,0xc1]
+          vpmovzxwd %xmm17, %xmm24 {%k4}
+
+// CHECK: vpmovzxwd %xmm17, %xmm24 {%k4} {z}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x8c,0x33,0xc1]
+          vpmovzxwd %xmm17, %xmm24 {%k4} {z}
+
+// CHECK: vpmovzxwd (%rcx), %xmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x33,0x01]
+          vpmovzxwd (%rcx), %xmm24
+
+// CHECK: vpmovzxwd 291(%rax,%r14,8), %xmm24
+// CHECK:  encoding: [0x62,0x22,0x7d,0x08,0x33,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vpmovzxwd 291(%rax,%r14,8), %xmm24
+
+// CHECK: vpmovzxwd 1016(%rdx), %xmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x33,0x42,0x7f]
+          vpmovzxwd 1016(%rdx), %xmm24
+
+// CHECK: vpmovzxwd 1024(%rdx), %xmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x33,0x82,0x00,0x04,0x00,0x00]
+          vpmovzxwd 1024(%rdx), %xmm24
+
+// CHECK: vpmovzxwd -1024(%rdx), %xmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x33,0x42,0x80]
+          vpmovzxwd -1024(%rdx), %xmm24
+
+// CHECK: vpmovzxwd -1032(%rdx), %xmm24
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x33,0x82,0xf8,0xfb,0xff,0xff]
+          vpmovzxwd -1032(%rdx), %xmm24
+
+// CHECK: vpmovzxwd %xmm29, %ymm26
+// CHECK:  encoding: [0x62,0x02,0x7d,0x28,0x33,0xd5]
+          vpmovzxwd %xmm29, %ymm26
+
+// CHECK: vpmovzxwd %xmm29, %ymm26 {%k5}
+// CHECK:  encoding: [0x62,0x02,0x7d,0x2d,0x33,0xd5]
+          vpmovzxwd %xmm29, %ymm26 {%k5}
+
+// CHECK: vpmovzxwd %xmm29, %ymm26 {%k5} {z}
+// CHECK:  encoding: [0x62,0x02,0x7d,0xad,0x33,0xd5]
+          vpmovzxwd %xmm29, %ymm26 {%k5} {z}
+
+// CHECK: vpmovzxwd (%rcx), %ymm26
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x33,0x11]
+          vpmovzxwd (%rcx), %ymm26
+
+// CHECK: vpmovzxwd 291(%rax,%r14,8), %ymm26
+// CHECK:  encoding: [0x62,0x22,0x7d,0x28,0x33,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vpmovzxwd 291(%rax,%r14,8), %ymm26
+
+// CHECK: vpmovzxwd 2032(%rdx), %ymm26
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x33,0x52,0x7f]
+          vpmovzxwd 2032(%rdx), %ymm26
+
+// CHECK: vpmovzxwd 2048(%rdx), %ymm26
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x33,0x92,0x00,0x08,0x00,0x00]
+          vpmovzxwd 2048(%rdx), %ymm26
+
+// CHECK: vpmovzxwd -2048(%rdx), %ymm26
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x33,0x52,0x80]
+          vpmovzxwd -2048(%rdx), %ymm26
+
+// CHECK: vpmovzxwd -2064(%rdx), %ymm26
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x33,0x92,0xf0,0xf7,0xff,0xff]
+          vpmovzxwd -2064(%rdx), %ymm26
+
+// CHECK: vpmovzxwq %xmm20, %xmm29
+// CHECK:  encoding: [0x62,0x22,0x7d,0x08,0x34,0xec]
+          vpmovzxwq %xmm20, %xmm29
+
+// CHECK: vpmovzxwq %xmm20, %xmm29 {%k2}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x0a,0x34,0xec]
+          vpmovzxwq %xmm20, %xmm29 {%k2}
+
+// CHECK: vpmovzxwq %xmm20, %xmm29 {%k2} {z}
+// CHECK:  encoding: [0x62,0x22,0x7d,0x8a,0x34,0xec]
+          vpmovzxwq %xmm20, %xmm29 {%k2} {z}
+
+// CHECK: vpmovzxwq (%rcx), %xmm29
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x34,0x29]
+          vpmovzxwq (%rcx), %xmm29
+
+// CHECK: vpmovzxwq 291(%rax,%r14,8), %xmm29
+// CHECK:  encoding: [0x62,0x22,0x7d,0x08,0x34,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpmovzxwq 291(%rax,%r14,8), %xmm29
+
+// CHECK: vpmovzxwq 508(%rdx), %xmm29
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x34,0x6a,0x7f]
+          vpmovzxwq 508(%rdx), %xmm29
+
+// CHECK: vpmovzxwq 512(%rdx), %xmm29
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x34,0xaa,0x00,0x02,0x00,0x00]
+          vpmovzxwq 512(%rdx), %xmm29
+
+// CHECK: vpmovzxwq -512(%rdx), %xmm29
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x34,0x6a,0x80]
+          vpmovzxwq -512(%rdx), %xmm29
+
+// CHECK: vpmovzxwq -516(%rdx), %xmm29
+// CHECK:  encoding: [0x62,0x62,0x7d,0x08,0x34,0xaa,0xfc,0xfd,0xff,0xff]
+          vpmovzxwq -516(%rdx), %xmm29
+
+// CHECK: vpmovzxwq %xmm25, %ymm18
+// CHECK:  encoding: [0x62,0x82,0x7d,0x28,0x34,0xd1]
+          vpmovzxwq %xmm25, %ymm18
+
+// CHECK: vpmovzxwq %xmm25, %ymm18 {%k1}
+// CHECK:  encoding: [0x62,0x82,0x7d,0x29,0x34,0xd1]
+          vpmovzxwq %xmm25, %ymm18 {%k1}
+
+// CHECK: vpmovzxwq %xmm25, %ymm18 {%k1} {z}
+// CHECK:  encoding: [0x62,0x82,0x7d,0xa9,0x34,0xd1]
+          vpmovzxwq %xmm25, %ymm18 {%k1} {z}
+
+// CHECK: vpmovzxwq (%rcx), %ymm18
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x34,0x11]
+          vpmovzxwq (%rcx), %ymm18
+
+// CHECK: vpmovzxwq 291(%rax,%r14,8), %ymm18
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x28,0x34,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vpmovzxwq 291(%rax,%r14,8), %ymm18
+
+// CHECK: vpmovzxwq 1016(%rdx), %ymm18
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x34,0x52,0x7f]
+          vpmovzxwq 1016(%rdx), %ymm18
+
+// CHECK: vpmovzxwq 1024(%rdx), %ymm18
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x34,0x92,0x00,0x04,0x00,0x00]
+          vpmovzxwq 1024(%rdx), %ymm18
+
+// CHECK: vpmovzxwq -1024(%rdx), %ymm18
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x34,0x52,0x80]
+          vpmovzxwq -1024(%rdx), %ymm18
+
+// CHECK: vpmovzxwq -1032(%rdx), %ymm18
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x34,0x92,0xf8,0xfb,0xff,0xff]
+          vpmovzxwq -1032(%rdx), %ymm18
+
 // CHECK: vpmulld %xmm24, %xmm19, %xmm25
 // CHECK:  encoding: [0x62,0x02,0x65,0x00,0x40,0xc8]
           vpmulld %xmm24, %xmm19, %xmm25
@@ -6651,3 +7371,2829 @@
 // CHECK: vmovups %ymm23, -4128(%rdx)
 // CHECK:  encoding: [0x62,0xe1,0x7c,0x28,0x11,0xba,0xe0,0xef,0xff,0xff]
           vmovups %ymm23, -4128(%rdx)
+
+// CHECK: vaddpd  %zmm2, %zmm1, %zmm1
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x48,0x58,0xca]
+vaddpd  %zmm2, %zmm1, %zmm1
+
+// CHECK: vaddpd  %zmm2, %zmm1, %zmm1 {%k5}
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x4d,0x58,0xca]
+vaddpd  %zmm2, %zmm1, %zmm1 {%k5}
+
+// CHECK: vaddpd  %zmm2, %zmm1, %zmm1 {%k5} {z}
+// CHECK:  encoding: [0x62,0xf1,0xf5,0xcd,0x58,0xca]
+vaddpd  %zmm2, %zmm1, %zmm1 {%k5} {z}
+
+// CHECK: vaddpd  {rn-sae}, %zmm2, %zmm1, %zmm1 {%k5} {z}
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x9d,0x58,0xca]
+vaddpd  {rn-sae}, %zmm2, %zmm1, %zmm1 {%k5} {z}
+
+// CHECK: vaddpd  {rn-sae}, %zmm2, %zmm1, %zmm1
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x18,0x58,0xca]
+vaddpd  {rn-sae}, %zmm2, %zmm1, %zmm1
+
+// CHECK: vaddpd  {ru-sae}, %zmm2, %zmm1, %zmm1
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x58,0x58,0xca]
+vaddpd  {ru-sae}, %zmm2, %zmm1, %zmm1
+
+// CHECK:  vaddpd  {rd-sae}, %zmm2, %zmm1, %zmm1
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x38,0x58,0xca]
+vaddpd  {rd-sae}, %zmm2, %zmm1, %zmm1
+
+// CHECK: vaddpd  {rz-sae}, %zmm2, %zmm1, %zmm1
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x78,0x58,0xca]
+vaddpd  {rz-sae}, %zmm2, %zmm1, %zmm1
+
+// CHECK: vpslld %xmm22, %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xa1,0x55,0x00,0xf2,0xd6]
+          vpslld %xmm22, %xmm21, %xmm18
+
+// CHECK: vpslld %xmm22, %xmm21, %xmm18 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0x55,0x01,0xf2,0xd6]
+          vpslld %xmm22, %xmm21, %xmm18 {%k1}
+
+// CHECK: vpslld %xmm22, %xmm21, %xmm18 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0x55,0x81,0xf2,0xd6]
+          vpslld %xmm22, %xmm21, %xmm18 {%k1} {z}
+
+// CHECK: vpslld (%rcx), %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0x55,0x00,0xf2,0x11]
+          vpslld (%rcx), %xmm21, %xmm18
+
+// CHECK: vpslld 291(%rax,%r14,8), %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xa1,0x55,0x00,0xf2,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vpslld 291(%rax,%r14,8), %xmm21, %xmm18
+
+// CHECK: vpslld 2032(%rdx), %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0x55,0x00,0xf2,0x52,0x7f]
+          vpslld 2032(%rdx), %xmm21, %xmm18
+
+// CHECK: vpslld 2048(%rdx), %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0x55,0x00,0xf2,0x92,0x00,0x08,0x00,0x00]
+          vpslld 2048(%rdx), %xmm21, %xmm18
+
+// CHECK: vpslld -2048(%rdx), %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0x55,0x00,0xf2,0x52,0x80]
+          vpslld -2048(%rdx), %xmm21, %xmm18
+
+// CHECK: vpslld -2064(%rdx), %xmm21, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0x55,0x00,0xf2,0x92,0xf0,0xf7,0xff,0xff]
+          vpslld -2064(%rdx), %xmm21, %xmm18
+
+// CHECK: vpslld %xmm25, %ymm26, %ymm29
+// CHECK:  encoding: [0x62,0x01,0x2d,0x20,0xf2,0xe9]
+          vpslld %xmm25, %ymm26, %ymm29
+
+// CHECK: vpslld %xmm25, %ymm26, %ymm29 {%k7}
+// CHECK:  encoding: [0x62,0x01,0x2d,0x27,0xf2,0xe9]
+          vpslld %xmm25, %ymm26, %ymm29 {%k7}
+
+// CHECK: vpslld %xmm25, %ymm26, %ymm29 {%k7} {z}
+// CHECK:  encoding: [0x62,0x01,0x2d,0xa7,0xf2,0xe9]
+          vpslld %xmm25, %ymm26, %ymm29 {%k7} {z}
+
+// CHECK: vpslld (%rcx), %ymm26, %ymm29
+// CHECK:  encoding: [0x62,0x61,0x2d,0x20,0xf2,0x29]
+          vpslld (%rcx), %ymm26, %ymm29
+
+// CHECK: vpslld 291(%rax,%r14,8), %ymm26, %ymm29
+// CHECK:  encoding: [0x62,0x21,0x2d,0x20,0xf2,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpslld 291(%rax,%r14,8), %ymm26, %ymm29
+
+// CHECK: vpslld 2032(%rdx), %ymm26, %ymm29
+// CHECK:  encoding: [0x62,0x61,0x2d,0x20,0xf2,0x6a,0x7f]
+          vpslld 2032(%rdx), %ymm26, %ymm29
+
+// CHECK: vpslld 2048(%rdx), %ymm26, %ymm29
+// CHECK:  encoding: [0x62,0x61,0x2d,0x20,0xf2,0xaa,0x00,0x08,0x00,0x00]
+          vpslld 2048(%rdx), %ymm26, %ymm29
+
+// CHECK: vpslld -2048(%rdx), %ymm26, %ymm29
+// CHECK:  encoding: [0x62,0x61,0x2d,0x20,0xf2,0x6a,0x80]
+          vpslld -2048(%rdx), %ymm26, %ymm29
+
+// CHECK: vpslld -2064(%rdx), %ymm26, %ymm29
+// CHECK:  encoding: [0x62,0x61,0x2d,0x20,0xf2,0xaa,0xf0,0xf7,0xff,0xff]
+          vpslld -2064(%rdx), %ymm26, %ymm29
+
+// CHECK: vpsllq %xmm24, %xmm28, %xmm20
+// CHECK:  encoding: [0x62,0x81,0x9d,0x00,0xf3,0xe0]
+          vpsllq %xmm24, %xmm28, %xmm20
+
+// CHECK: vpsllq %xmm24, %xmm28, %xmm20 {%k1}
+// CHECK:  encoding: [0x62,0x81,0x9d,0x01,0xf3,0xe0]
+          vpsllq %xmm24, %xmm28, %xmm20 {%k1}
+
+// CHECK: vpsllq %xmm24, %xmm28, %xmm20 {%k1} {z}
+// CHECK:  encoding: [0x62,0x81,0x9d,0x81,0xf3,0xe0]
+          vpsllq %xmm24, %xmm28, %xmm20 {%k1} {z}
+
+// CHECK: vpsllq (%rcx), %xmm28, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x00,0xf3,0x21]
+          vpsllq (%rcx), %xmm28, %xmm20
+
+// CHECK: vpsllq 291(%rax,%r14,8), %xmm28, %xmm20
+// CHECK:  encoding: [0x62,0xa1,0x9d,0x00,0xf3,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsllq 291(%rax,%r14,8), %xmm28, %xmm20
+
+// CHECK: vpsllq 2032(%rdx), %xmm28, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x00,0xf3,0x62,0x7f]
+          vpsllq 2032(%rdx), %xmm28, %xmm20
+
+// CHECK: vpsllq 2048(%rdx), %xmm28, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x00,0xf3,0xa2,0x00,0x08,0x00,0x00]
+          vpsllq 2048(%rdx), %xmm28, %xmm20
+
+// CHECK: vpsllq -2048(%rdx), %xmm28, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x00,0xf3,0x62,0x80]
+          vpsllq -2048(%rdx), %xmm28, %xmm20
+
+// CHECK: vpsllq -2064(%rdx), %xmm28, %xmm20
+// CHECK:  encoding: [0x62,0xe1,0x9d,0x00,0xf3,0xa2,0xf0,0xf7,0xff,0xff]
+          vpsllq -2064(%rdx), %xmm28, %xmm20
+
+// CHECK: vpsllq %xmm20, %ymm21, %ymm23
+// CHECK:  encoding: [0x62,0xa1,0xd5,0x20,0xf3,0xfc]
+          vpsllq %xmm20, %ymm21, %ymm23
+
+// CHECK: vpsllq %xmm20, %ymm21, %ymm23 {%k1}
+// CHECK:  encoding: [0x62,0xa1,0xd5,0x21,0xf3,0xfc]
+          vpsllq %xmm20, %ymm21, %ymm23 {%k1}
+
+// CHECK: vpsllq %xmm20, %ymm21, %ymm23 {%k1} {z}
+// CHECK:  encoding: [0x62,0xa1,0xd5,0xa1,0xf3,0xfc]
+          vpsllq %xmm20, %ymm21, %ymm23 {%k1} {z}
+
+// CHECK: vpsllq (%rcx), %ymm21, %ymm23
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x20,0xf3,0x39]
+          vpsllq (%rcx), %ymm21, %ymm23
+
+// CHECK: vpsllq 291(%rax,%r14,8), %ymm21, %ymm23
+// CHECK:  encoding: [0x62,0xa1,0xd5,0x20,0xf3,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vpsllq 291(%rax,%r14,8), %ymm21, %ymm23
+
+// CHECK: vpsllq 2032(%rdx), %ymm21, %ymm23
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x20,0xf3,0x7a,0x7f]
+          vpsllq 2032(%rdx), %ymm21, %ymm23
+
+// CHECK: vpsllq 2048(%rdx), %ymm21, %ymm23
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x20,0xf3,0xba,0x00,0x08,0x00,0x00]
+          vpsllq 2048(%rdx), %ymm21, %ymm23
+
+// CHECK: vpsllq -2048(%rdx), %ymm21, %ymm23
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x20,0xf3,0x7a,0x80]
+          vpsllq -2048(%rdx), %ymm21, %ymm23
+
+// CHECK: vpsllq -2064(%rdx), %ymm21, %ymm23
+// CHECK:  encoding: [0x62,0xe1,0xd5,0x20,0xf3,0xba,0xf0,0xf7,0xff,0xff]
+          vpsllq -2064(%rdx), %ymm21, %ymm23
+
+// CHECK: vpsllvd %xmm24, %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0x82,0x45,0x00,0x47,0xf8]
+          vpsllvd %xmm24, %xmm23, %xmm23
+
+// CHECK: vpsllvd %xmm24, %xmm23, %xmm23 {%k6}
+// CHECK:  encoding: [0x62,0x82,0x45,0x06,0x47,0xf8]
+          vpsllvd %xmm24, %xmm23, %xmm23 {%k6}
+
+// CHECK: vpsllvd %xmm24, %xmm23, %xmm23 {%k6} {z}
+// CHECK:  encoding: [0x62,0x82,0x45,0x86,0x47,0xf8]
+          vpsllvd %xmm24, %xmm23, %xmm23 {%k6} {z}
+
+// CHECK: vpsllvd (%rcx), %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xe2,0x45,0x00,0x47,0x39]
+          vpsllvd (%rcx), %xmm23, %xmm23
+
+// CHECK: vpsllvd 291(%rax,%r14,8), %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xa2,0x45,0x00,0x47,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vpsllvd 291(%rax,%r14,8), %xmm23, %xmm23
+
+// CHECK: vpsllvd (%rcx){1to4}, %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xe2,0x45,0x10,0x47,0x39]
+          vpsllvd (%rcx){1to4}, %xmm23, %xmm23
+
+// CHECK: vpsllvd 2032(%rdx), %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xe2,0x45,0x00,0x47,0x7a,0x7f]
+          vpsllvd 2032(%rdx), %xmm23, %xmm23
+
+// CHECK: vpsllvd 2048(%rdx), %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xe2,0x45,0x00,0x47,0xba,0x00,0x08,0x00,0x00]
+          vpsllvd 2048(%rdx), %xmm23, %xmm23
+
+// CHECK: vpsllvd -2048(%rdx), %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xe2,0x45,0x00,0x47,0x7a,0x80]
+          vpsllvd -2048(%rdx), %xmm23, %xmm23
+
+// CHECK: vpsllvd -2064(%rdx), %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xe2,0x45,0x00,0x47,0xba,0xf0,0xf7,0xff,0xff]
+          vpsllvd -2064(%rdx), %xmm23, %xmm23
+
+// CHECK: vpsllvd 508(%rdx){1to4}, %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xe2,0x45,0x10,0x47,0x7a,0x7f]
+          vpsllvd 508(%rdx){1to4}, %xmm23, %xmm23
+
+// CHECK: vpsllvd 512(%rdx){1to4}, %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xe2,0x45,0x10,0x47,0xba,0x00,0x02,0x00,0x00]
+          vpsllvd 512(%rdx){1to4}, %xmm23, %xmm23
+
+// CHECK: vpsllvd -512(%rdx){1to4}, %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xe2,0x45,0x10,0x47,0x7a,0x80]
+          vpsllvd -512(%rdx){1to4}, %xmm23, %xmm23
+
+// CHECK: vpsllvd -516(%rdx){1to4}, %xmm23, %xmm23
+// CHECK:  encoding: [0x62,0xe2,0x45,0x10,0x47,0xba,0xfc,0xfd,0xff,0xff]
+          vpsllvd -516(%rdx){1to4}, %xmm23, %xmm23
+
+// CHECK: vpsllvd %ymm19, %ymm22, %ymm17
+// CHECK:  encoding: [0x62,0xa2,0x4d,0x20,0x47,0xcb]
+          vpsllvd %ymm19, %ymm22, %ymm17
+
+// CHECK: vpsllvd %ymm19, %ymm22, %ymm17 {%k5}
+// CHECK:  encoding: [0x62,0xa2,0x4d,0x25,0x47,0xcb]
+          vpsllvd %ymm19, %ymm22, %ymm17 {%k5}
+
+// CHECK: vpsllvd %ymm19, %ymm22, %ymm17 {%k5} {z}
+// CHECK:  encoding: [0x62,0xa2,0x4d,0xa5,0x47,0xcb]
+          vpsllvd %ymm19, %ymm22, %ymm17 {%k5} {z}
+
+// CHECK: vpsllvd (%rcx), %ymm22, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0x4d,0x20,0x47,0x09]
+          vpsllvd (%rcx), %ymm22, %ymm17
+
+// CHECK: vpsllvd 291(%rax,%r14,8), %ymm22, %ymm17
+// CHECK:  encoding: [0x62,0xa2,0x4d,0x20,0x47,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpsllvd 291(%rax,%r14,8), %ymm22, %ymm17
+
+// CHECK: vpsllvd (%rcx){1to8}, %ymm22, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0x4d,0x30,0x47,0x09]
+          vpsllvd (%rcx){1to8}, %ymm22, %ymm17
+
+// CHECK: vpsllvd 4064(%rdx), %ymm22, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0x4d,0x20,0x47,0x4a,0x7f]
+          vpsllvd 4064(%rdx), %ymm22, %ymm17
+
+// CHECK: vpsllvd 4096(%rdx), %ymm22, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0x4d,0x20,0x47,0x8a,0x00,0x10,0x00,0x00]
+          vpsllvd 4096(%rdx), %ymm22, %ymm17
+
+// CHECK: vpsllvd -4096(%rdx), %ymm22, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0x4d,0x20,0x47,0x4a,0x80]
+          vpsllvd -4096(%rdx), %ymm22, %ymm17
+
+// CHECK: vpsllvd -4128(%rdx), %ymm22, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0x4d,0x20,0x47,0x8a,0xe0,0xef,0xff,0xff]
+          vpsllvd -4128(%rdx), %ymm22, %ymm17
+
+// CHECK: vpsllvd 508(%rdx){1to8}, %ymm22, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0x4d,0x30,0x47,0x4a,0x7f]
+          vpsllvd 508(%rdx){1to8}, %ymm22, %ymm17
+
+// CHECK: vpsllvd 512(%rdx){1to8}, %ymm22, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0x4d,0x30,0x47,0x8a,0x00,0x02,0x00,0x00]
+          vpsllvd 512(%rdx){1to8}, %ymm22, %ymm17
+
+// CHECK: vpsllvd -512(%rdx){1to8}, %ymm22, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0x4d,0x30,0x47,0x4a,0x80]
+          vpsllvd -512(%rdx){1to8}, %ymm22, %ymm17
+
+// CHECK: vpsllvd -516(%rdx){1to8}, %ymm22, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0x4d,0x30,0x47,0x8a,0xfc,0xfd,0xff,0xff]
+          vpsllvd -516(%rdx){1to8}, %ymm22, %ymm17
+
+// CHECK: vpsllvq %xmm18, %xmm21, %xmm19
+// CHECK:  encoding: [0x62,0xa2,0xd5,0x00,0x47,0xda]
+          vpsllvq %xmm18, %xmm21, %xmm19
+
+// CHECK: vpsllvq %xmm18, %xmm21, %xmm19 {%k2}
+// CHECK:  encoding: [0x62,0xa2,0xd5,0x02,0x47,0xda]
+          vpsllvq %xmm18, %xmm21, %xmm19 {%k2}
+
+// CHECK: vpsllvq %xmm18, %xmm21, %xmm19 {%k2} {z}
+// CHECK:  encoding: [0x62,0xa2,0xd5,0x82,0x47,0xda]
+          vpsllvq %xmm18, %xmm21, %xmm19 {%k2} {z}
+
+// CHECK: vpsllvq (%rcx), %xmm21, %xmm19
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x00,0x47,0x19]
+          vpsllvq (%rcx), %xmm21, %xmm19
+
+// CHECK: vpsllvq 291(%rax,%r14,8), %xmm21, %xmm19
+// CHECK:  encoding: [0x62,0xa2,0xd5,0x00,0x47,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpsllvq 291(%rax,%r14,8), %xmm21, %xmm19
+
+// CHECK: vpsllvq (%rcx){1to2}, %xmm21, %xmm19
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x10,0x47,0x19]
+          vpsllvq (%rcx){1to2}, %xmm21, %xmm19
+
+// CHECK: vpsllvq 2032(%rdx), %xmm21, %xmm19
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x00,0x47,0x5a,0x7f]
+          vpsllvq 2032(%rdx), %xmm21, %xmm19
+
+// CHECK: vpsllvq 2048(%rdx), %xmm21, %xmm19
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x00,0x47,0x9a,0x00,0x08,0x00,0x00]
+          vpsllvq 2048(%rdx), %xmm21, %xmm19
+
+// CHECK: vpsllvq -2048(%rdx), %xmm21, %xmm19
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x00,0x47,0x5a,0x80]
+          vpsllvq -2048(%rdx), %xmm21, %xmm19
+
+// CHECK: vpsllvq -2064(%rdx), %xmm21, %xmm19
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x00,0x47,0x9a,0xf0,0xf7,0xff,0xff]
+          vpsllvq -2064(%rdx), %xmm21, %xmm19
+
+// CHECK: vpsllvq 1016(%rdx){1to2}, %xmm21, %xmm19
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x10,0x47,0x5a,0x7f]
+          vpsllvq 1016(%rdx){1to2}, %xmm21, %xmm19
+
+// CHECK: vpsllvq 1024(%rdx){1to2}, %xmm21, %xmm19
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x10,0x47,0x9a,0x00,0x04,0x00,0x00]
+          vpsllvq 1024(%rdx){1to2}, %xmm21, %xmm19
+
+// CHECK: vpsllvq -1024(%rdx){1to2}, %xmm21, %xmm19
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x10,0x47,0x5a,0x80]
+          vpsllvq -1024(%rdx){1to2}, %xmm21, %xmm19
+
+// CHECK: vpsllvq -1032(%rdx){1to2}, %xmm21, %xmm19
+// CHECK:  encoding: [0x62,0xe2,0xd5,0x10,0x47,0x9a,0xf8,0xfb,0xff,0xff]
+          vpsllvq -1032(%rdx){1to2}, %xmm21, %xmm19
+
+// CHECK: vpsllvq %ymm18, %ymm25, %ymm23
+// CHECK:  encoding: [0x62,0xa2,0xb5,0x20,0x47,0xfa]
+          vpsllvq %ymm18, %ymm25, %ymm23
+
+// CHECK: vpsllvq %ymm18, %ymm25, %ymm23 {%k2}
+// CHECK:  encoding: [0x62,0xa2,0xb5,0x22,0x47,0xfa]
+          vpsllvq %ymm18, %ymm25, %ymm23 {%k2}
+
+// CHECK: vpsllvq %ymm18, %ymm25, %ymm23 {%k2} {z}
+// CHECK:  encoding: [0x62,0xa2,0xb5,0xa2,0x47,0xfa]
+          vpsllvq %ymm18, %ymm25, %ymm23 {%k2} {z}
+
+// CHECK: vpsllvq (%rcx), %ymm25, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0xb5,0x20,0x47,0x39]
+          vpsllvq (%rcx), %ymm25, %ymm23
+
+// CHECK: vpsllvq 291(%rax,%r14,8), %ymm25, %ymm23
+// CHECK:  encoding: [0x62,0xa2,0xb5,0x20,0x47,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vpsllvq 291(%rax,%r14,8), %ymm25, %ymm23
+
+// CHECK: vpsllvq (%rcx){1to4}, %ymm25, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0xb5,0x30,0x47,0x39]
+          vpsllvq (%rcx){1to4}, %ymm25, %ymm23
+
+// CHECK: vpsllvq 4064(%rdx), %ymm25, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0xb5,0x20,0x47,0x7a,0x7f]
+          vpsllvq 4064(%rdx), %ymm25, %ymm23
+
+// CHECK: vpsllvq 4096(%rdx), %ymm25, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0xb5,0x20,0x47,0xba,0x00,0x10,0x00,0x00]
+          vpsllvq 4096(%rdx), %ymm25, %ymm23
+
+// CHECK: vpsllvq -4096(%rdx), %ymm25, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0xb5,0x20,0x47,0x7a,0x80]
+          vpsllvq -4096(%rdx), %ymm25, %ymm23
+
+// CHECK: vpsllvq -4128(%rdx), %ymm25, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0xb5,0x20,0x47,0xba,0xe0,0xef,0xff,0xff]
+          vpsllvq -4128(%rdx), %ymm25, %ymm23
+
+// CHECK: vpsllvq 1016(%rdx){1to4}, %ymm25, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0xb5,0x30,0x47,0x7a,0x7f]
+          vpsllvq 1016(%rdx){1to4}, %ymm25, %ymm23
+
+// CHECK: vpsllvq 1024(%rdx){1to4}, %ymm25, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0xb5,0x30,0x47,0xba,0x00,0x04,0x00,0x00]
+          vpsllvq 1024(%rdx){1to4}, %ymm25, %ymm23
+
+// CHECK: vpsllvq -1024(%rdx){1to4}, %ymm25, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0xb5,0x30,0x47,0x7a,0x80]
+          vpsllvq -1024(%rdx){1to4}, %ymm25, %ymm23
+
+// CHECK: vpsllvq -1032(%rdx){1to4}, %ymm25, %ymm23
+// CHECK:  encoding: [0x62,0xe2,0xb5,0x30,0x47,0xba,0xf8,0xfb,0xff,0xff]
+          vpsllvq -1032(%rdx){1to4}, %ymm25, %ymm23
+
+// CHECK: vpsrad %xmm20, %xmm23, %xmm28
+// CHECK:  encoding: [0x62,0x21,0x45,0x00,0xe2,0xe4]
+          vpsrad %xmm20, %xmm23, %xmm28
+
+// CHECK: vpsrad %xmm20, %xmm23, %xmm28 {%k3}
+// CHECK:  encoding: [0x62,0x21,0x45,0x03,0xe2,0xe4]
+          vpsrad %xmm20, %xmm23, %xmm28 {%k3}
+
+// CHECK: vpsrad %xmm20, %xmm23, %xmm28 {%k3} {z}
+// CHECK:  encoding: [0x62,0x21,0x45,0x83,0xe2,0xe4]
+          vpsrad %xmm20, %xmm23, %xmm28 {%k3} {z}
+
+// CHECK: vpsrad (%rcx), %xmm23, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x45,0x00,0xe2,0x21]
+          vpsrad (%rcx), %xmm23, %xmm28
+
+// CHECK: vpsrad 291(%rax,%r14,8), %xmm23, %xmm28
+// CHECK:  encoding: [0x62,0x21,0x45,0x00,0xe2,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsrad 291(%rax,%r14,8), %xmm23, %xmm28
+
+// CHECK: vpsrad 2032(%rdx), %xmm23, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x45,0x00,0xe2,0x62,0x7f]
+          vpsrad 2032(%rdx), %xmm23, %xmm28
+
+// CHECK: vpsrad 2048(%rdx), %xmm23, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x45,0x00,0xe2,0xa2,0x00,0x08,0x00,0x00]
+          vpsrad 2048(%rdx), %xmm23, %xmm28
+
+// CHECK: vpsrad -2048(%rdx), %xmm23, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x45,0x00,0xe2,0x62,0x80]
+          vpsrad -2048(%rdx), %xmm23, %xmm28
+
+// CHECK: vpsrad -2064(%rdx), %xmm23, %xmm28
+// CHECK:  encoding: [0x62,0x61,0x45,0x00,0xe2,0xa2,0xf0,0xf7,0xff,0xff]
+          vpsrad -2064(%rdx), %xmm23, %xmm28
+
+// CHECK: vpsrad %xmm24, %ymm27, %ymm25
+// CHECK:  encoding: [0x62,0x01,0x25,0x20,0xe2,0xc8]
+          vpsrad %xmm24, %ymm27, %ymm25
+
+// CHECK: vpsrad %xmm24, %ymm27, %ymm25 {%k4}
+// CHECK:  encoding: [0x62,0x01,0x25,0x24,0xe2,0xc8]
+          vpsrad %xmm24, %ymm27, %ymm25 {%k4}
+
+// CHECK: vpsrad %xmm24, %ymm27, %ymm25 {%k4} {z}
+// CHECK:  encoding: [0x62,0x01,0x25,0xa4,0xe2,0xc8]
+          vpsrad %xmm24, %ymm27, %ymm25 {%k4} {z}
+
+// CHECK: vpsrad (%rcx), %ymm27, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x25,0x20,0xe2,0x09]
+          vpsrad (%rcx), %ymm27, %ymm25
+
+// CHECK: vpsrad 291(%rax,%r14,8), %ymm27, %ymm25
+// CHECK:  encoding: [0x62,0x21,0x25,0x20,0xe2,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpsrad 291(%rax,%r14,8), %ymm27, %ymm25
+
+// CHECK: vpsrad 2032(%rdx), %ymm27, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x25,0x20,0xe2,0x4a,0x7f]
+          vpsrad 2032(%rdx), %ymm27, %ymm25
+
+// CHECK: vpsrad 2048(%rdx), %ymm27, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x25,0x20,0xe2,0x8a,0x00,0x08,0x00,0x00]
+          vpsrad 2048(%rdx), %ymm27, %ymm25
+
+// CHECK: vpsrad -2048(%rdx), %ymm27, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x25,0x20,0xe2,0x4a,0x80]
+          vpsrad -2048(%rdx), %ymm27, %ymm25
+
+// CHECK: vpsrad -2064(%rdx), %ymm27, %ymm25
+// CHECK:  encoding: [0x62,0x61,0x25,0x20,0xe2,0x8a,0xf0,0xf7,0xff,0xff]
+          vpsrad -2064(%rdx), %ymm27, %ymm25
+
+// CHECK: vpsraq %xmm24, %xmm24, %xmm29
+// CHECK:  encoding: [0x62,0x01,0xbd,0x00,0xe2,0xe8]
+          vpsraq %xmm24, %xmm24, %xmm29
+
+// CHECK: vpsraq %xmm24, %xmm24, %xmm29 {%k3}
+// CHECK:  encoding: [0x62,0x01,0xbd,0x03,0xe2,0xe8]
+          vpsraq %xmm24, %xmm24, %xmm29 {%k3}
+
+// CHECK: vpsraq %xmm24, %xmm24, %xmm29 {%k3} {z}
+// CHECK:  encoding: [0x62,0x01,0xbd,0x83,0xe2,0xe8]
+          vpsraq %xmm24, %xmm24, %xmm29 {%k3} {z}
+
+// CHECK: vpsraq (%rcx), %xmm24, %xmm29
+// CHECK:  encoding: [0x62,0x61,0xbd,0x00,0xe2,0x29]
+          vpsraq (%rcx), %xmm24, %xmm29
+
+// CHECK: vpsraq 291(%rax,%r14,8), %xmm24, %xmm29
+// CHECK:  encoding: [0x62,0x21,0xbd,0x00,0xe2,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpsraq 291(%rax,%r14,8), %xmm24, %xmm29
+
+// CHECK: vpsraq 2032(%rdx), %xmm24, %xmm29
+// CHECK:  encoding: [0x62,0x61,0xbd,0x00,0xe2,0x6a,0x7f]
+          vpsraq 2032(%rdx), %xmm24, %xmm29
+
+// CHECK: vpsraq 2048(%rdx), %xmm24, %xmm29
+// CHECK:  encoding: [0x62,0x61,0xbd,0x00,0xe2,0xaa,0x00,0x08,0x00,0x00]
+          vpsraq 2048(%rdx), %xmm24, %xmm29
+
+// CHECK: vpsraq -2048(%rdx), %xmm24, %xmm29
+// CHECK:  encoding: [0x62,0x61,0xbd,0x00,0xe2,0x6a,0x80]
+          vpsraq -2048(%rdx), %xmm24, %xmm29
+
+// CHECK: vpsraq -2064(%rdx), %xmm24, %xmm29
+// CHECK:  encoding: [0x62,0x61,0xbd,0x00,0xe2,0xaa,0xf0,0xf7,0xff,0xff]
+          vpsraq -2064(%rdx), %xmm24, %xmm29
+
+// CHECK: vpsraq %xmm26, %ymm26, %ymm28
+// CHECK:  encoding: [0x62,0x01,0xad,0x20,0xe2,0xe2]
+          vpsraq %xmm26, %ymm26, %ymm28
+
+// CHECK: vpsraq %xmm26, %ymm26, %ymm28 {%k4}
+// CHECK:  encoding: [0x62,0x01,0xad,0x24,0xe2,0xe2]
+          vpsraq %xmm26, %ymm26, %ymm28 {%k4}
+
+// CHECK: vpsraq %xmm26, %ymm26, %ymm28 {%k4} {z}
+// CHECK:  encoding: [0x62,0x01,0xad,0xa4,0xe2,0xe2]
+          vpsraq %xmm26, %ymm26, %ymm28 {%k4} {z}
+
+// CHECK: vpsraq (%rcx), %ymm26, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xad,0x20,0xe2,0x21]
+          vpsraq (%rcx), %ymm26, %ymm28
+
+// CHECK: vpsraq 291(%rax,%r14,8), %ymm26, %ymm28
+// CHECK:  encoding: [0x62,0x21,0xad,0x20,0xe2,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsraq 291(%rax,%r14,8), %ymm26, %ymm28
+
+// CHECK: vpsraq 2032(%rdx), %ymm26, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xad,0x20,0xe2,0x62,0x7f]
+          vpsraq 2032(%rdx), %ymm26, %ymm28
+
+// CHECK: vpsraq 2048(%rdx), %ymm26, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xad,0x20,0xe2,0xa2,0x00,0x08,0x00,0x00]
+          vpsraq 2048(%rdx), %ymm26, %ymm28
+
+// CHECK: vpsraq -2048(%rdx), %ymm26, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xad,0x20,0xe2,0x62,0x80]
+          vpsraq -2048(%rdx), %ymm26, %ymm28
+
+// CHECK: vpsraq -2064(%rdx), %ymm26, %ymm28
+// CHECK:  encoding: [0x62,0x61,0xad,0x20,0xe2,0xa2,0xf0,0xf7,0xff,0xff]
+          vpsraq -2064(%rdx), %ymm26, %ymm28
+
+// CHECK: vpsravd %xmm18, %xmm26, %xmm24
+// CHECK:  encoding: [0x62,0x22,0x2d,0x00,0x46,0xc2]
+          vpsravd %xmm18, %xmm26, %xmm24
+
+// CHECK: vpsravd %xmm18, %xmm26, %xmm24 {%k5}
+// CHECK:  encoding: [0x62,0x22,0x2d,0x05,0x46,0xc2]
+          vpsravd %xmm18, %xmm26, %xmm24 {%k5}
+
+// CHECK: vpsravd %xmm18, %xmm26, %xmm24 {%k5} {z}
+// CHECK:  encoding: [0x62,0x22,0x2d,0x85,0x46,0xc2]
+          vpsravd %xmm18, %xmm26, %xmm24 {%k5} {z}
+
+// CHECK: vpsravd (%rcx), %xmm26, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x2d,0x00,0x46,0x01]
+          vpsravd (%rcx), %xmm26, %xmm24
+
+// CHECK: vpsravd 291(%rax,%r14,8), %xmm26, %xmm24
+// CHECK:  encoding: [0x62,0x22,0x2d,0x00,0x46,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vpsravd 291(%rax,%r14,8), %xmm26, %xmm24
+
+// CHECK: vpsravd (%rcx){1to4}, %xmm26, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x2d,0x10,0x46,0x01]
+          vpsravd (%rcx){1to4}, %xmm26, %xmm24
+
+// CHECK: vpsravd 2032(%rdx), %xmm26, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x2d,0x00,0x46,0x42,0x7f]
+          vpsravd 2032(%rdx), %xmm26, %xmm24
+
+// CHECK: vpsravd 2048(%rdx), %xmm26, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x2d,0x00,0x46,0x82,0x00,0x08,0x00,0x00]
+          vpsravd 2048(%rdx), %xmm26, %xmm24
+
+// CHECK: vpsravd -2048(%rdx), %xmm26, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x2d,0x00,0x46,0x42,0x80]
+          vpsravd -2048(%rdx), %xmm26, %xmm24
+
+// CHECK: vpsravd -2064(%rdx), %xmm26, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x2d,0x00,0x46,0x82,0xf0,0xf7,0xff,0xff]
+          vpsravd -2064(%rdx), %xmm26, %xmm24
+
+// CHECK: vpsravd 508(%rdx){1to4}, %xmm26, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x2d,0x10,0x46,0x42,0x7f]
+          vpsravd 508(%rdx){1to4}, %xmm26, %xmm24
+
+// CHECK: vpsravd 512(%rdx){1to4}, %xmm26, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x2d,0x10,0x46,0x82,0x00,0x02,0x00,0x00]
+          vpsravd 512(%rdx){1to4}, %xmm26, %xmm24
+
+// CHECK: vpsravd -512(%rdx){1to4}, %xmm26, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x2d,0x10,0x46,0x42,0x80]
+          vpsravd -512(%rdx){1to4}, %xmm26, %xmm24
+
+// CHECK: vpsravd -516(%rdx){1to4}, %xmm26, %xmm24
+// CHECK:  encoding: [0x62,0x62,0x2d,0x10,0x46,0x82,0xfc,0xfd,0xff,0xff]
+          vpsravd -516(%rdx){1to4}, %xmm26, %xmm24
+
+// CHECK: vpsravd %ymm23, %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xa2,0x35,0x20,0x46,0xf7]
+          vpsravd %ymm23, %ymm25, %ymm22
+
+// CHECK: vpsravd %ymm23, %ymm25, %ymm22 {%k7}
+// CHECK:  encoding: [0x62,0xa2,0x35,0x27,0x46,0xf7]
+          vpsravd %ymm23, %ymm25, %ymm22 {%k7}
+
+// CHECK: vpsravd %ymm23, %ymm25, %ymm22 {%k7} {z}
+// CHECK:  encoding: [0x62,0xa2,0x35,0xa7,0x46,0xf7]
+          vpsravd %ymm23, %ymm25, %ymm22 {%k7} {z}
+
+// CHECK: vpsravd (%rcx), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe2,0x35,0x20,0x46,0x31]
+          vpsravd (%rcx), %ymm25, %ymm22
+
+// CHECK: vpsravd 291(%rax,%r14,8), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xa2,0x35,0x20,0x46,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpsravd 291(%rax,%r14,8), %ymm25, %ymm22
+
+// CHECK: vpsravd (%rcx){1to8}, %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe2,0x35,0x30,0x46,0x31]
+          vpsravd (%rcx){1to8}, %ymm25, %ymm22
+
+// CHECK: vpsravd 4064(%rdx), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe2,0x35,0x20,0x46,0x72,0x7f]
+          vpsravd 4064(%rdx), %ymm25, %ymm22
+
+// CHECK: vpsravd 4096(%rdx), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe2,0x35,0x20,0x46,0xb2,0x00,0x10,0x00,0x00]
+          vpsravd 4096(%rdx), %ymm25, %ymm22
+
+// CHECK: vpsravd -4096(%rdx), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe2,0x35,0x20,0x46,0x72,0x80]
+          vpsravd -4096(%rdx), %ymm25, %ymm22
+
+// CHECK: vpsravd -4128(%rdx), %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe2,0x35,0x20,0x46,0xb2,0xe0,0xef,0xff,0xff]
+          vpsravd -4128(%rdx), %ymm25, %ymm22
+
+// CHECK: vpsravd 508(%rdx){1to8}, %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe2,0x35,0x30,0x46,0x72,0x7f]
+          vpsravd 508(%rdx){1to8}, %ymm25, %ymm22
+
+// CHECK: vpsravd 512(%rdx){1to8}, %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe2,0x35,0x30,0x46,0xb2,0x00,0x02,0x00,0x00]
+          vpsravd 512(%rdx){1to8}, %ymm25, %ymm22
+
+// CHECK: vpsravd -512(%rdx){1to8}, %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe2,0x35,0x30,0x46,0x72,0x80]
+          vpsravd -512(%rdx){1to8}, %ymm25, %ymm22
+
+// CHECK: vpsravd -516(%rdx){1to8}, %ymm25, %ymm22
+// CHECK:  encoding: [0x62,0xe2,0x35,0x30,0x46,0xb2,0xfc,0xfd,0xff,0xff]
+          vpsravd -516(%rdx){1to8}, %ymm25, %ymm22
+
+// CHECK: vpsravq %xmm17, %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x22,0x9d,0x00,0x46,0xe1]
+          vpsravq %xmm17, %xmm28, %xmm28
+
+// CHECK: vpsravq %xmm17, %xmm28, %xmm28 {%k1}
+// CHECK:  encoding: [0x62,0x22,0x9d,0x01,0x46,0xe1]
+          vpsravq %xmm17, %xmm28, %xmm28 {%k1}
+
+// CHECK: vpsravq %xmm17, %xmm28, %xmm28 {%k1} {z}
+// CHECK:  encoding: [0x62,0x22,0x9d,0x81,0x46,0xe1]
+          vpsravq %xmm17, %xmm28, %xmm28 {%k1} {z}
+
+// CHECK: vpsravq (%rcx), %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x9d,0x00,0x46,0x21]
+          vpsravq (%rcx), %xmm28, %xmm28
+
+// CHECK: vpsravq 291(%rax,%r14,8), %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x22,0x9d,0x00,0x46,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsravq 291(%rax,%r14,8), %xmm28, %xmm28
+
+// CHECK: vpsravq (%rcx){1to2}, %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x9d,0x10,0x46,0x21]
+          vpsravq (%rcx){1to2}, %xmm28, %xmm28
+
+// CHECK: vpsravq 2032(%rdx), %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x9d,0x00,0x46,0x62,0x7f]
+          vpsravq 2032(%rdx), %xmm28, %xmm28
+
+// CHECK: vpsravq 2048(%rdx), %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x9d,0x00,0x46,0xa2,0x00,0x08,0x00,0x00]
+          vpsravq 2048(%rdx), %xmm28, %xmm28
+
+// CHECK: vpsravq -2048(%rdx), %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x9d,0x00,0x46,0x62,0x80]
+          vpsravq -2048(%rdx), %xmm28, %xmm28
+
+// CHECK: vpsravq -2064(%rdx), %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x9d,0x00,0x46,0xa2,0xf0,0xf7,0xff,0xff]
+          vpsravq -2064(%rdx), %xmm28, %xmm28
+
+// CHECK: vpsravq 1016(%rdx){1to2}, %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x9d,0x10,0x46,0x62,0x7f]
+          vpsravq 1016(%rdx){1to2}, %xmm28, %xmm28
+
+// CHECK: vpsravq 1024(%rdx){1to2}, %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x9d,0x10,0x46,0xa2,0x00,0x04,0x00,0x00]
+          vpsravq 1024(%rdx){1to2}, %xmm28, %xmm28
+
+// CHECK: vpsravq -1024(%rdx){1to2}, %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x9d,0x10,0x46,0x62,0x80]
+          vpsravq -1024(%rdx){1to2}, %xmm28, %xmm28
+
+// CHECK: vpsravq -1032(%rdx){1to2}, %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x62,0x9d,0x10,0x46,0xa2,0xf8,0xfb,0xff,0xff]
+          vpsravq -1032(%rdx){1to2}, %xmm28, %xmm28
+
+// CHECK: vpsravq %ymm21, %ymm24, %ymm30
+// CHECK:  encoding: [0x62,0x22,0xbd,0x20,0x46,0xf5]
+          vpsravq %ymm21, %ymm24, %ymm30
+
+// CHECK: vpsravq %ymm21, %ymm24, %ymm30 {%k7}
+// CHECK:  encoding: [0x62,0x22,0xbd,0x27,0x46,0xf5]
+          vpsravq %ymm21, %ymm24, %ymm30 {%k7}
+
+// CHECK: vpsravq %ymm21, %ymm24, %ymm30 {%k7} {z}
+// CHECK:  encoding: [0x62,0x22,0xbd,0xa7,0x46,0xf5]
+          vpsravq %ymm21, %ymm24, %ymm30 {%k7} {z}
+
+// CHECK: vpsravq (%rcx), %ymm24, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xbd,0x20,0x46,0x31]
+          vpsravq (%rcx), %ymm24, %ymm30
+
+// CHECK: vpsravq 291(%rax,%r14,8), %ymm24, %ymm30
+// CHECK:  encoding: [0x62,0x22,0xbd,0x20,0x46,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpsravq 291(%rax,%r14,8), %ymm24, %ymm30
+
+// CHECK: vpsravq (%rcx){1to4}, %ymm24, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xbd,0x30,0x46,0x31]
+          vpsravq (%rcx){1to4}, %ymm24, %ymm30
+
+// CHECK: vpsravq 4064(%rdx), %ymm24, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xbd,0x20,0x46,0x72,0x7f]
+          vpsravq 4064(%rdx), %ymm24, %ymm30
+
+// CHECK: vpsravq 4096(%rdx), %ymm24, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xbd,0x20,0x46,0xb2,0x00,0x10,0x00,0x00]
+          vpsravq 4096(%rdx), %ymm24, %ymm30
+
+// CHECK: vpsravq -4096(%rdx), %ymm24, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xbd,0x20,0x46,0x72,0x80]
+          vpsravq -4096(%rdx), %ymm24, %ymm30
+
+// CHECK: vpsravq -4128(%rdx), %ymm24, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xbd,0x20,0x46,0xb2,0xe0,0xef,0xff,0xff]
+          vpsravq -4128(%rdx), %ymm24, %ymm30
+
+// CHECK: vpsravq 1016(%rdx){1to4}, %ymm24, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xbd,0x30,0x46,0x72,0x7f]
+          vpsravq 1016(%rdx){1to4}, %ymm24, %ymm30
+
+// CHECK: vpsravq 1024(%rdx){1to4}, %ymm24, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xbd,0x30,0x46,0xb2,0x00,0x04,0x00,0x00]
+          vpsravq 1024(%rdx){1to4}, %ymm24, %ymm30
+
+// CHECK: vpsravq -1024(%rdx){1to4}, %ymm24, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xbd,0x30,0x46,0x72,0x80]
+          vpsravq -1024(%rdx){1to4}, %ymm24, %ymm30
+
+// CHECK: vpsravq -1032(%rdx){1to4}, %ymm24, %ymm30
+// CHECK:  encoding: [0x62,0x62,0xbd,0x30,0x46,0xb2,0xf8,0xfb,0xff,0xff]
+          vpsravq -1032(%rdx){1to4}, %ymm24, %ymm30
+
+// CHECK: vpsrld %xmm20, %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x21,0x5d,0x00,0xd2,0xf4]
+          vpsrld %xmm20, %xmm20, %xmm30
+
+// CHECK: vpsrld %xmm20, %xmm20, %xmm30 {%k3}
+// CHECK:  encoding: [0x62,0x21,0x5d,0x03,0xd2,0xf4]
+          vpsrld %xmm20, %xmm20, %xmm30 {%k3}
+
+// CHECK: vpsrld %xmm20, %xmm20, %xmm30 {%k3} {z}
+// CHECK:  encoding: [0x62,0x21,0x5d,0x83,0xd2,0xf4]
+          vpsrld %xmm20, %xmm20, %xmm30 {%k3} {z}
+
+// CHECK: vpsrld (%rcx), %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x5d,0x00,0xd2,0x31]
+          vpsrld (%rcx), %xmm20, %xmm30
+
+// CHECK: vpsrld 291(%rax,%r14,8), %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x21,0x5d,0x00,0xd2,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpsrld 291(%rax,%r14,8), %xmm20, %xmm30
+
+// CHECK: vpsrld 2032(%rdx), %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x5d,0x00,0xd2,0x72,0x7f]
+          vpsrld 2032(%rdx), %xmm20, %xmm30
+
+// CHECK: vpsrld 2048(%rdx), %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x5d,0x00,0xd2,0xb2,0x00,0x08,0x00,0x00]
+          vpsrld 2048(%rdx), %xmm20, %xmm30
+
+// CHECK: vpsrld -2048(%rdx), %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x5d,0x00,0xd2,0x72,0x80]
+          vpsrld -2048(%rdx), %xmm20, %xmm30
+
+// CHECK: vpsrld -2064(%rdx), %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x61,0x5d,0x00,0xd2,0xb2,0xf0,0xf7,0xff,0xff]
+          vpsrld -2064(%rdx), %xmm20, %xmm30
+
+// CHECK: vpsrld %xmm25, %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x01,0x6d,0x20,0xd2,0xd1]
+          vpsrld %xmm25, %ymm18, %ymm26
+
+// CHECK: vpsrld %xmm25, %ymm18, %ymm26 {%k1}
+// CHECK:  encoding: [0x62,0x01,0x6d,0x21,0xd2,0xd1]
+          vpsrld %xmm25, %ymm18, %ymm26 {%k1}
+
+// CHECK: vpsrld %xmm25, %ymm18, %ymm26 {%k1} {z}
+// CHECK:  encoding: [0x62,0x01,0x6d,0xa1,0xd2,0xd1]
+          vpsrld %xmm25, %ymm18, %ymm26 {%k1} {z}
+
+// CHECK: vpsrld (%rcx), %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x6d,0x20,0xd2,0x11]
+          vpsrld (%rcx), %ymm18, %ymm26
+
+// CHECK: vpsrld 291(%rax,%r14,8), %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x21,0x6d,0x20,0xd2,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vpsrld 291(%rax,%r14,8), %ymm18, %ymm26
+
+// CHECK: vpsrld 2032(%rdx), %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x6d,0x20,0xd2,0x52,0x7f]
+          vpsrld 2032(%rdx), %ymm18, %ymm26
+
+// CHECK: vpsrld 2048(%rdx), %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x6d,0x20,0xd2,0x92,0x00,0x08,0x00,0x00]
+          vpsrld 2048(%rdx), %ymm18, %ymm26
+
+// CHECK: vpsrld -2048(%rdx), %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x6d,0x20,0xd2,0x52,0x80]
+          vpsrld -2048(%rdx), %ymm18, %ymm26
+
+// CHECK: vpsrld -2064(%rdx), %ymm18, %ymm26
+// CHECK:  encoding: [0x62,0x61,0x6d,0x20,0xd2,0x92,0xf0,0xf7,0xff,0xff]
+          vpsrld -2064(%rdx), %ymm18, %ymm26
+
+// CHECK: vpsrlq %xmm17, %xmm21, %xmm28
+// CHECK:  encoding: [0x62,0x21,0xd5,0x00,0xd3,0xe1]
+          vpsrlq %xmm17, %xmm21, %xmm28
+
+// CHECK: vpsrlq %xmm17, %xmm21, %xmm28 {%k2}
+// CHECK:  encoding: [0x62,0x21,0xd5,0x02,0xd3,0xe1]
+          vpsrlq %xmm17, %xmm21, %xmm28 {%k2}
+
+// CHECK: vpsrlq %xmm17, %xmm21, %xmm28 {%k2} {z}
+// CHECK:  encoding: [0x62,0x21,0xd5,0x82,0xd3,0xe1]
+          vpsrlq %xmm17, %xmm21, %xmm28 {%k2} {z}
+
+// CHECK: vpsrlq (%rcx), %xmm21, %xmm28
+// CHECK:  encoding: [0x62,0x61,0xd5,0x00,0xd3,0x21]
+          vpsrlq (%rcx), %xmm21, %xmm28
+
+// CHECK: vpsrlq 291(%rax,%r14,8), %xmm21, %xmm28
+// CHECK:  encoding: [0x62,0x21,0xd5,0x00,0xd3,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsrlq 291(%rax,%r14,8), %xmm21, %xmm28
+
+// CHECK: vpsrlq 2032(%rdx), %xmm21, %xmm28
+// CHECK:  encoding: [0x62,0x61,0xd5,0x00,0xd3,0x62,0x7f]
+          vpsrlq 2032(%rdx), %xmm21, %xmm28
+
+// CHECK: vpsrlq 2048(%rdx), %xmm21, %xmm28
+// CHECK:  encoding: [0x62,0x61,0xd5,0x00,0xd3,0xa2,0x00,0x08,0x00,0x00]
+          vpsrlq 2048(%rdx), %xmm21, %xmm28
+
+// CHECK: vpsrlq -2048(%rdx), %xmm21, %xmm28
+// CHECK:  encoding: [0x62,0x61,0xd5,0x00,0xd3,0x62,0x80]
+          vpsrlq -2048(%rdx), %xmm21, %xmm28
+
+// CHECK: vpsrlq -2064(%rdx), %xmm21, %xmm28
+// CHECK:  encoding: [0x62,0x61,0xd5,0x00,0xd3,0xa2,0xf0,0xf7,0xff,0xff]
+          vpsrlq -2064(%rdx), %xmm21, %xmm28
+
+// CHECK: vpsrlq %xmm18, %ymm26, %ymm22
+// CHECK:  encoding: [0x62,0xa1,0xad,0x20,0xd3,0xf2]
+          vpsrlq %xmm18, %ymm26, %ymm22
+
+// CHECK: vpsrlq %xmm18, %ymm26, %ymm22 {%k2}
+// CHECK:  encoding: [0x62,0xa1,0xad,0x22,0xd3,0xf2]
+          vpsrlq %xmm18, %ymm26, %ymm22 {%k2}
+
+// CHECK: vpsrlq %xmm18, %ymm26, %ymm22 {%k2} {z}
+// CHECK:  encoding: [0x62,0xa1,0xad,0xa2,0xd3,0xf2]
+          vpsrlq %xmm18, %ymm26, %ymm22 {%k2} {z}
+
+// CHECK: vpsrlq (%rcx), %ymm26, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xad,0x20,0xd3,0x31]
+          vpsrlq (%rcx), %ymm26, %ymm22
+
+// CHECK: vpsrlq 291(%rax,%r14,8), %ymm26, %ymm22
+// CHECK:  encoding: [0x62,0xa1,0xad,0x20,0xd3,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpsrlq 291(%rax,%r14,8), %ymm26, %ymm22
+
+// CHECK: vpsrlq 2032(%rdx), %ymm26, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xad,0x20,0xd3,0x72,0x7f]
+          vpsrlq 2032(%rdx), %ymm26, %ymm22
+
+// CHECK: vpsrlq 2048(%rdx), %ymm26, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xad,0x20,0xd3,0xb2,0x00,0x08,0x00,0x00]
+          vpsrlq 2048(%rdx), %ymm26, %ymm22
+
+// CHECK: vpsrlq -2048(%rdx), %ymm26, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xad,0x20,0xd3,0x72,0x80]
+          vpsrlq -2048(%rdx), %ymm26, %ymm22
+
+// CHECK: vpsrlq -2064(%rdx), %ymm26, %ymm22
+// CHECK:  encoding: [0x62,0xe1,0xad,0x20,0xd3,0xb2,0xf0,0xf7,0xff,0xff]
+          vpsrlq -2064(%rdx), %ymm26, %ymm22
+
+// CHECK: vpsrlvd %xmm18, %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x22,0x35,0x00,0x45,0xea]
+          vpsrlvd %xmm18, %xmm25, %xmm29
+
+// CHECK: vpsrlvd %xmm18, %xmm25, %xmm29 {%k3}
+// CHECK:  encoding: [0x62,0x22,0x35,0x03,0x45,0xea]
+          vpsrlvd %xmm18, %xmm25, %xmm29 {%k3}
+
+// CHECK: vpsrlvd %xmm18, %xmm25, %xmm29 {%k3} {z}
+// CHECK:  encoding: [0x62,0x22,0x35,0x83,0x45,0xea]
+          vpsrlvd %xmm18, %xmm25, %xmm29 {%k3} {z}
+
+// CHECK: vpsrlvd (%rcx), %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x62,0x35,0x00,0x45,0x29]
+          vpsrlvd (%rcx), %xmm25, %xmm29
+
+// CHECK: vpsrlvd 291(%rax,%r14,8), %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x22,0x35,0x00,0x45,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpsrlvd 291(%rax,%r14,8), %xmm25, %xmm29
+
+// CHECK: vpsrlvd (%rcx){1to4}, %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x62,0x35,0x10,0x45,0x29]
+          vpsrlvd (%rcx){1to4}, %xmm25, %xmm29
+
+// CHECK: vpsrlvd 2032(%rdx), %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x62,0x35,0x00,0x45,0x6a,0x7f]
+          vpsrlvd 2032(%rdx), %xmm25, %xmm29
+
+// CHECK: vpsrlvd 2048(%rdx), %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x62,0x35,0x00,0x45,0xaa,0x00,0x08,0x00,0x00]
+          vpsrlvd 2048(%rdx), %xmm25, %xmm29
+
+// CHECK: vpsrlvd -2048(%rdx), %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x62,0x35,0x00,0x45,0x6a,0x80]
+          vpsrlvd -2048(%rdx), %xmm25, %xmm29
+
+// CHECK: vpsrlvd -2064(%rdx), %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x62,0x35,0x00,0x45,0xaa,0xf0,0xf7,0xff,0xff]
+          vpsrlvd -2064(%rdx), %xmm25, %xmm29
+
+// CHECK: vpsrlvd 508(%rdx){1to4}, %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x62,0x35,0x10,0x45,0x6a,0x7f]
+          vpsrlvd 508(%rdx){1to4}, %xmm25, %xmm29
+
+// CHECK: vpsrlvd 512(%rdx){1to4}, %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x62,0x35,0x10,0x45,0xaa,0x00,0x02,0x00,0x00]
+          vpsrlvd 512(%rdx){1to4}, %xmm25, %xmm29
+
+// CHECK: vpsrlvd -512(%rdx){1to4}, %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x62,0x35,0x10,0x45,0x6a,0x80]
+          vpsrlvd -512(%rdx){1to4}, %xmm25, %xmm29
+
+// CHECK: vpsrlvd -516(%rdx){1to4}, %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x62,0x35,0x10,0x45,0xaa,0xfc,0xfd,0xff,0xff]
+          vpsrlvd -516(%rdx){1to4}, %xmm25, %xmm29
+
+// CHECK: vpsrlvd %ymm20, %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x22,0x55,0x20,0x45,0xe4]
+          vpsrlvd %ymm20, %ymm21, %ymm28
+
+// CHECK: vpsrlvd %ymm20, %ymm21, %ymm28 {%k5}
+// CHECK:  encoding: [0x62,0x22,0x55,0x25,0x45,0xe4]
+          vpsrlvd %ymm20, %ymm21, %ymm28 {%k5}
+
+// CHECK: vpsrlvd %ymm20, %ymm21, %ymm28 {%k5} {z}
+// CHECK:  encoding: [0x62,0x22,0x55,0xa5,0x45,0xe4]
+          vpsrlvd %ymm20, %ymm21, %ymm28 {%k5} {z}
+
+// CHECK: vpsrlvd (%rcx), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x62,0x55,0x20,0x45,0x21]
+          vpsrlvd (%rcx), %ymm21, %ymm28
+
+// CHECK: vpsrlvd 291(%rax,%r14,8), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x22,0x55,0x20,0x45,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsrlvd 291(%rax,%r14,8), %ymm21, %ymm28
+
+// CHECK: vpsrlvd (%rcx){1to8}, %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x62,0x55,0x30,0x45,0x21]
+          vpsrlvd (%rcx){1to8}, %ymm21, %ymm28
+
+// CHECK: vpsrlvd 4064(%rdx), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x62,0x55,0x20,0x45,0x62,0x7f]
+          vpsrlvd 4064(%rdx), %ymm21, %ymm28
+
+// CHECK: vpsrlvd 4096(%rdx), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x62,0x55,0x20,0x45,0xa2,0x00,0x10,0x00,0x00]
+          vpsrlvd 4096(%rdx), %ymm21, %ymm28
+
+// CHECK: vpsrlvd -4096(%rdx), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x62,0x55,0x20,0x45,0x62,0x80]
+          vpsrlvd -4096(%rdx), %ymm21, %ymm28
+
+// CHECK: vpsrlvd -4128(%rdx), %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x62,0x55,0x20,0x45,0xa2,0xe0,0xef,0xff,0xff]
+          vpsrlvd -4128(%rdx), %ymm21, %ymm28
+
+// CHECK: vpsrlvd 508(%rdx){1to8}, %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x62,0x55,0x30,0x45,0x62,0x7f]
+          vpsrlvd 508(%rdx){1to8}, %ymm21, %ymm28
+
+// CHECK: vpsrlvd 512(%rdx){1to8}, %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x62,0x55,0x30,0x45,0xa2,0x00,0x02,0x00,0x00]
+          vpsrlvd 512(%rdx){1to8}, %ymm21, %ymm28
+
+// CHECK: vpsrlvd -512(%rdx){1to8}, %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x62,0x55,0x30,0x45,0x62,0x80]
+          vpsrlvd -512(%rdx){1to8}, %ymm21, %ymm28
+
+// CHECK: vpsrlvd -516(%rdx){1to8}, %ymm21, %ymm28
+// CHECK:  encoding: [0x62,0x62,0x55,0x30,0x45,0xa2,0xfc,0xfd,0xff,0xff]
+          vpsrlvd -516(%rdx){1to8}, %ymm21, %ymm28
+
+// CHECK: vpsrlvq %xmm27, %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0x82,0x9d,0x00,0x45,0xeb]
+          vpsrlvq %xmm27, %xmm28, %xmm21
+
+// CHECK: vpsrlvq %xmm27, %xmm28, %xmm21 {%k1}
+// CHECK:  encoding: [0x62,0x82,0x9d,0x01,0x45,0xeb]
+          vpsrlvq %xmm27, %xmm28, %xmm21 {%k1}
+
+// CHECK: vpsrlvq %xmm27, %xmm28, %xmm21 {%k1} {z}
+// CHECK:  encoding: [0x62,0x82,0x9d,0x81,0x45,0xeb]
+          vpsrlvq %xmm27, %xmm28, %xmm21 {%k1} {z}
+
+// CHECK: vpsrlvq (%rcx), %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xe2,0x9d,0x00,0x45,0x29]
+          vpsrlvq (%rcx), %xmm28, %xmm21
+
+// CHECK: vpsrlvq 291(%rax,%r14,8), %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xa2,0x9d,0x00,0x45,0xac,0xf0,0x23,0x01,0x00,0x00]
+          vpsrlvq 291(%rax,%r14,8), %xmm28, %xmm21
+
+// CHECK: vpsrlvq (%rcx){1to2}, %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xe2,0x9d,0x10,0x45,0x29]
+          vpsrlvq (%rcx){1to2}, %xmm28, %xmm21
+
+// CHECK: vpsrlvq 2032(%rdx), %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xe2,0x9d,0x00,0x45,0x6a,0x7f]
+          vpsrlvq 2032(%rdx), %xmm28, %xmm21
+
+// CHECK: vpsrlvq 2048(%rdx), %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xe2,0x9d,0x00,0x45,0xaa,0x00,0x08,0x00,0x00]
+          vpsrlvq 2048(%rdx), %xmm28, %xmm21
+
+// CHECK: vpsrlvq -2048(%rdx), %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xe2,0x9d,0x00,0x45,0x6a,0x80]
+          vpsrlvq -2048(%rdx), %xmm28, %xmm21
+
+// CHECK: vpsrlvq -2064(%rdx), %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xe2,0x9d,0x00,0x45,0xaa,0xf0,0xf7,0xff,0xff]
+          vpsrlvq -2064(%rdx), %xmm28, %xmm21
+
+// CHECK: vpsrlvq 1016(%rdx){1to2}, %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xe2,0x9d,0x10,0x45,0x6a,0x7f]
+          vpsrlvq 1016(%rdx){1to2}, %xmm28, %xmm21
+
+// CHECK: vpsrlvq 1024(%rdx){1to2}, %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xe2,0x9d,0x10,0x45,0xaa,0x00,0x04,0x00,0x00]
+          vpsrlvq 1024(%rdx){1to2}, %xmm28, %xmm21
+
+// CHECK: vpsrlvq -1024(%rdx){1to2}, %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xe2,0x9d,0x10,0x45,0x6a,0x80]
+          vpsrlvq -1024(%rdx){1to2}, %xmm28, %xmm21
+
+// CHECK: vpsrlvq -1032(%rdx){1to2}, %xmm28, %xmm21
+// CHECK:  encoding: [0x62,0xe2,0x9d,0x10,0x45,0xaa,0xf8,0xfb,0xff,0xff]
+          vpsrlvq -1032(%rdx){1to2}, %xmm28, %xmm21
+
+// CHECK: vpsrlvq %ymm26, %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x02,0xa5,0x20,0x45,0xe2]
+          vpsrlvq %ymm26, %ymm27, %ymm28
+
+// CHECK: vpsrlvq %ymm26, %ymm27, %ymm28 {%k7}
+// CHECK:  encoding: [0x62,0x02,0xa5,0x27,0x45,0xe2]
+          vpsrlvq %ymm26, %ymm27, %ymm28 {%k7}
+
+// CHECK: vpsrlvq %ymm26, %ymm27, %ymm28 {%k7} {z}
+// CHECK:  encoding: [0x62,0x02,0xa5,0xa7,0x45,0xe2]
+          vpsrlvq %ymm26, %ymm27, %ymm28 {%k7} {z}
+
+// CHECK: vpsrlvq (%rcx), %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x62,0xa5,0x20,0x45,0x21]
+          vpsrlvq (%rcx), %ymm27, %ymm28
+
+// CHECK: vpsrlvq 291(%rax,%r14,8), %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x22,0xa5,0x20,0x45,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vpsrlvq 291(%rax,%r14,8), %ymm27, %ymm28
+
+// CHECK: vpsrlvq (%rcx){1to4}, %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x62,0xa5,0x30,0x45,0x21]
+          vpsrlvq (%rcx){1to4}, %ymm27, %ymm28
+
+// CHECK: vpsrlvq 4064(%rdx), %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x62,0xa5,0x20,0x45,0x62,0x7f]
+          vpsrlvq 4064(%rdx), %ymm27, %ymm28
+
+// CHECK: vpsrlvq 4096(%rdx), %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x62,0xa5,0x20,0x45,0xa2,0x00,0x10,0x00,0x00]
+          vpsrlvq 4096(%rdx), %ymm27, %ymm28
+
+// CHECK: vpsrlvq -4096(%rdx), %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x62,0xa5,0x20,0x45,0x62,0x80]
+          vpsrlvq -4096(%rdx), %ymm27, %ymm28
+
+// CHECK: vpsrlvq -4128(%rdx), %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x62,0xa5,0x20,0x45,0xa2,0xe0,0xef,0xff,0xff]
+          vpsrlvq -4128(%rdx), %ymm27, %ymm28
+
+// CHECK: vpsrlvq 1016(%rdx){1to4}, %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x62,0xa5,0x30,0x45,0x62,0x7f]
+          vpsrlvq 1016(%rdx){1to4}, %ymm27, %ymm28
+
+// CHECK: vpsrlvq 1024(%rdx){1to4}, %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x62,0xa5,0x30,0x45,0xa2,0x00,0x04,0x00,0x00]
+          vpsrlvq 1024(%rdx){1to4}, %ymm27, %ymm28
+
+// CHECK: vpsrlvq -1024(%rdx){1to4}, %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x62,0xa5,0x30,0x45,0x62,0x80]
+          vpsrlvq -1024(%rdx){1to4}, %ymm27, %ymm28
+
+// CHECK: vpsrlvq -1032(%rdx){1to4}, %ymm27, %ymm28
+// CHECK:  encoding: [0x62,0x62,0xa5,0x30,0x45,0xa2,0xf8,0xfb,0xff,0xff]
+          vpsrlvq -1032(%rdx){1to4}, %ymm27, %ymm28
+
+// CHECK: vpsrld $171, %xmm23, %xmm30
+// CHECK:  encoding: [0x62,0xb1,0x0d,0x00,0x72,0xd7,0xab]
+          vpsrld $171, %xmm23, %xmm30
+
+// CHECK: vpsrld $171, %xmm23, %xmm30 {%k3}
+// CHECK:  encoding: [0x62,0xb1,0x0d,0x03,0x72,0xd7,0xab]
+          vpsrld $171, %xmm23, %xmm30 {%k3}
+
+// CHECK: vpsrld $171, %xmm23, %xmm30 {%k3} {z}
+// CHECK:  encoding: [0x62,0xb1,0x0d,0x83,0x72,0xd7,0xab]
+          vpsrld $171, %xmm23, %xmm30 {%k3} {z}
+
+// CHECK: vpsrld $123, %xmm23, %xmm30
+// CHECK:  encoding: [0x62,0xb1,0x0d,0x00,0x72,0xd7,0x7b]
+          vpsrld $123, %xmm23, %xmm30
+
+// CHECK: vpsrld $123, (%rcx), %xmm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x00,0x72,0x11,0x7b]
+          vpsrld $123, (%rcx), %xmm30
+
+// CHECK: vpsrld $123, 291(%rax,%r14,8), %xmm30
+// CHECK:  encoding: [0x62,0xb1,0x0d,0x00,0x72,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpsrld $123, 291(%rax,%r14,8), %xmm30
+
+// CHECK: vpsrld $123, (%rcx){1to4}, %xmm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x10,0x72,0x11,0x7b]
+          vpsrld $123, (%rcx){1to4}, %xmm30
+
+// CHECK: vpsrld $123, 2032(%rdx), %xmm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x00,0x72,0x52,0x7f,0x7b]
+          vpsrld $123, 2032(%rdx), %xmm30
+
+// CHECK: vpsrld $123, 2048(%rdx), %xmm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x00,0x72,0x92,0x00,0x08,0x00,0x00,0x7b]
+          vpsrld $123, 2048(%rdx), %xmm30
+
+// CHECK: vpsrld $123, -2048(%rdx), %xmm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x00,0x72,0x52,0x80,0x7b]
+          vpsrld $123, -2048(%rdx), %xmm30
+
+// CHECK: vpsrld $123, -2064(%rdx), %xmm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x00,0x72,0x92,0xf0,0xf7,0xff,0xff,0x7b]
+          vpsrld $123, -2064(%rdx), %xmm30
+
+// CHECK: vpsrld $123, 508(%rdx){1to4}, %xmm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x10,0x72,0x52,0x7f,0x7b]
+          vpsrld $123, 508(%rdx){1to4}, %xmm30
+
+// CHECK: vpsrld $123, 512(%rdx){1to4}, %xmm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x10,0x72,0x92,0x00,0x02,0x00,0x00,0x7b]
+          vpsrld $123, 512(%rdx){1to4}, %xmm30
+
+// CHECK: vpsrld $123, -512(%rdx){1to4}, %xmm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x10,0x72,0x52,0x80,0x7b]
+          vpsrld $123, -512(%rdx){1to4}, %xmm30
+
+// CHECK: vpsrld $123, -516(%rdx){1to4}, %xmm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x10,0x72,0x92,0xfc,0xfd,0xff,0xff,0x7b]
+          vpsrld $123, -516(%rdx){1to4}, %xmm30
+
+// CHECK: vpsrld $171, %ymm24, %ymm22
+// CHECK:  encoding: [0x62,0x91,0x4d,0x20,0x72,0xd0,0xab]
+          vpsrld $171, %ymm24, %ymm22
+
+// CHECK: vpsrld $171, %ymm24, %ymm22 {%k2}
+// CHECK:  encoding: [0x62,0x91,0x4d,0x22,0x72,0xd0,0xab]
+          vpsrld $171, %ymm24, %ymm22 {%k2}
+
+// CHECK: vpsrld $171, %ymm24, %ymm22 {%k2} {z}
+// CHECK:  encoding: [0x62,0x91,0x4d,0xa2,0x72,0xd0,0xab]
+          vpsrld $171, %ymm24, %ymm22 {%k2} {z}
+
+// CHECK: vpsrld $123, %ymm24, %ymm22
+// CHECK:  encoding: [0x62,0x91,0x4d,0x20,0x72,0xd0,0x7b]
+          vpsrld $123, %ymm24, %ymm22
+
+// CHECK: vpsrld $123, (%rcx), %ymm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x20,0x72,0x11,0x7b]
+          vpsrld $123, (%rcx), %ymm22
+
+// CHECK: vpsrld $123, 291(%rax,%r14,8), %ymm22
+// CHECK:  encoding: [0x62,0xb1,0x4d,0x20,0x72,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpsrld $123, 291(%rax,%r14,8), %ymm22
+
+// CHECK: vpsrld $123, (%rcx){1to8}, %ymm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x30,0x72,0x11,0x7b]
+          vpsrld $123, (%rcx){1to8}, %ymm22
+
+// CHECK: vpsrld $123, 4064(%rdx), %ymm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x20,0x72,0x52,0x7f,0x7b]
+          vpsrld $123, 4064(%rdx), %ymm22
+
+// CHECK: vpsrld $123, 4096(%rdx), %ymm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x20,0x72,0x92,0x00,0x10,0x00,0x00,0x7b]
+          vpsrld $123, 4096(%rdx), %ymm22
+
+// CHECK: vpsrld $123, -4096(%rdx), %ymm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x20,0x72,0x52,0x80,0x7b]
+          vpsrld $123, -4096(%rdx), %ymm22
+
+// CHECK: vpsrld $123, -4128(%rdx), %ymm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x20,0x72,0x92,0xe0,0xef,0xff,0xff,0x7b]
+          vpsrld $123, -4128(%rdx), %ymm22
+
+// CHECK: vpsrld $123, 508(%rdx){1to8}, %ymm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x30,0x72,0x52,0x7f,0x7b]
+          vpsrld $123, 508(%rdx){1to8}, %ymm22
+
+// CHECK: vpsrld $123, 512(%rdx){1to8}, %ymm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x30,0x72,0x92,0x00,0x02,0x00,0x00,0x7b]
+          vpsrld $123, 512(%rdx){1to8}, %ymm22
+
+// CHECK: vpsrld $123, -512(%rdx){1to8}, %ymm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x30,0x72,0x52,0x80,0x7b]
+          vpsrld $123, -512(%rdx){1to8}, %ymm22
+
+// CHECK: vpsrld $123, -516(%rdx){1to8}, %ymm22
+// CHECK:  encoding: [0x62,0xf1,0x4d,0x30,0x72,0x92,0xfc,0xfd,0xff,0xff,0x7b]
+          vpsrld $123, -516(%rdx){1to8}, %ymm22
+
+// CHECK: vpsrlq $171, %xmm24, %xmm17
+// CHECK:  encoding: [0x62,0x91,0xf5,0x00,0x73,0xd0,0xab]
+          vpsrlq $171, %xmm24, %xmm17
+
+// CHECK: vpsrlq $171, %xmm24, %xmm17 {%k6}
+// CHECK:  encoding: [0x62,0x91,0xf5,0x06,0x73,0xd0,0xab]
+          vpsrlq $171, %xmm24, %xmm17 {%k6}
+
+// CHECK: vpsrlq $171, %xmm24, %xmm17 {%k6} {z}
+// CHECK:  encoding: [0x62,0x91,0xf5,0x86,0x73,0xd0,0xab]
+          vpsrlq $171, %xmm24, %xmm17 {%k6} {z}
+
+// CHECK: vpsrlq $123, %xmm24, %xmm17
+// CHECK:  encoding: [0x62,0x91,0xf5,0x00,0x73,0xd0,0x7b]
+          vpsrlq $123, %xmm24, %xmm17
+
+// CHECK: vpsrlq $123, (%rcx), %xmm17
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x00,0x73,0x11,0x7b]
+          vpsrlq $123, (%rcx), %xmm17
+
+// CHECK: vpsrlq $123, 291(%rax,%r14,8), %xmm17
+// CHECK:  encoding: [0x62,0xb1,0xf5,0x00,0x73,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpsrlq $123, 291(%rax,%r14,8), %xmm17
+
+// CHECK: vpsrlq $123, (%rcx){1to2}, %xmm17
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x10,0x73,0x11,0x7b]
+          vpsrlq $123, (%rcx){1to2}, %xmm17
+
+// CHECK: vpsrlq $123, 2032(%rdx), %xmm17
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x00,0x73,0x52,0x7f,0x7b]
+          vpsrlq $123, 2032(%rdx), %xmm17
+
+// CHECK: vpsrlq $123, 2048(%rdx), %xmm17
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x00,0x73,0x92,0x00,0x08,0x00,0x00,0x7b]
+          vpsrlq $123, 2048(%rdx), %xmm17
+
+// CHECK: vpsrlq $123, -2048(%rdx), %xmm17
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x00,0x73,0x52,0x80,0x7b]
+          vpsrlq $123, -2048(%rdx), %xmm17
+
+// CHECK: vpsrlq $123, -2064(%rdx), %xmm17
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x00,0x73,0x92,0xf0,0xf7,0xff,0xff,0x7b]
+          vpsrlq $123, -2064(%rdx), %xmm17
+
+// CHECK: vpsrlq $123, 1016(%rdx){1to2}, %xmm17
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x10,0x73,0x52,0x7f,0x7b]
+          vpsrlq $123, 1016(%rdx){1to2}, %xmm17
+
+// CHECK: vpsrlq $123, 1024(%rdx){1to2}, %xmm17
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x10,0x73,0x92,0x00,0x04,0x00,0x00,0x7b]
+          vpsrlq $123, 1024(%rdx){1to2}, %xmm17
+
+// CHECK: vpsrlq $123, -1024(%rdx){1to2}, %xmm17
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x10,0x73,0x52,0x80,0x7b]
+          vpsrlq $123, -1024(%rdx){1to2}, %xmm17
+
+// CHECK: vpsrlq $123, -1032(%rdx){1to2}, %xmm17
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x10,0x73,0x92,0xf8,0xfb,0xff,0xff,0x7b]
+          vpsrlq $123, -1032(%rdx){1to2}, %xmm17
+
+// CHECK: vpsrlq $171, %ymm27, %ymm29
+// CHECK:  encoding: [0x62,0x91,0x95,0x20,0x73,0xd3,0xab]
+          vpsrlq $171, %ymm27, %ymm29
+
+// CHECK: vpsrlq $171, %ymm27, %ymm29 {%k3}
+// CHECK:  encoding: [0x62,0x91,0x95,0x23,0x73,0xd3,0xab]
+          vpsrlq $171, %ymm27, %ymm29 {%k3}
+
+// CHECK: vpsrlq $171, %ymm27, %ymm29 {%k3} {z}
+// CHECK:  encoding: [0x62,0x91,0x95,0xa3,0x73,0xd3,0xab]
+          vpsrlq $171, %ymm27, %ymm29 {%k3} {z}
+
+// CHECK: vpsrlq $123, %ymm27, %ymm29
+// CHECK:  encoding: [0x62,0x91,0x95,0x20,0x73,0xd3,0x7b]
+          vpsrlq $123, %ymm27, %ymm29
+
+// CHECK: vpsrlq $123, (%rcx), %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x20,0x73,0x11,0x7b]
+          vpsrlq $123, (%rcx), %ymm29
+
+// CHECK: vpsrlq $123, 291(%rax,%r14,8), %ymm29
+// CHECK:  encoding: [0x62,0xb1,0x95,0x20,0x73,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vpsrlq $123, 291(%rax,%r14,8), %ymm29
+
+// CHECK: vpsrlq $123, (%rcx){1to4}, %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x30,0x73,0x11,0x7b]
+          vpsrlq $123, (%rcx){1to4}, %ymm29
+
+// CHECK: vpsrlq $123, 4064(%rdx), %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x20,0x73,0x52,0x7f,0x7b]
+          vpsrlq $123, 4064(%rdx), %ymm29
+
+// CHECK: vpsrlq $123, 4096(%rdx), %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x20,0x73,0x92,0x00,0x10,0x00,0x00,0x7b]
+          vpsrlq $123, 4096(%rdx), %ymm29
+
+// CHECK: vpsrlq $123, -4096(%rdx), %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x20,0x73,0x52,0x80,0x7b]
+          vpsrlq $123, -4096(%rdx), %ymm29
+
+// CHECK: vpsrlq $123, -4128(%rdx), %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x20,0x73,0x92,0xe0,0xef,0xff,0xff,0x7b]
+          vpsrlq $123, -4128(%rdx), %ymm29
+
+// CHECK: vpsrlq $123, 1016(%rdx){1to4}, %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x30,0x73,0x52,0x7f,0x7b]
+          vpsrlq $123, 1016(%rdx){1to4}, %ymm29
+
+// CHECK: vpsrlq $123, 1024(%rdx){1to4}, %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x30,0x73,0x92,0x00,0x04,0x00,0x00,0x7b]
+          vpsrlq $123, 1024(%rdx){1to4}, %ymm29
+
+// CHECK: vpsrlq $123, -1024(%rdx){1to4}, %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x30,0x73,0x52,0x80,0x7b]
+          vpsrlq $123, -1024(%rdx){1to4}, %ymm29
+
+// CHECK: vpsrlq $123, -1032(%rdx){1to4}, %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x95,0x30,0x73,0x92,0xf8,0xfb,0xff,0xff,0x7b]
+          vpsrlq $123, -1032(%rdx){1to4}, %ymm29
+
+// CHECK: vprolvd %xmm20, %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x22,0x5d,0x00,0x15,0xf4]
+          vprolvd %xmm20, %xmm20, %xmm30
+
+// CHECK: vprolvd %xmm20, %xmm20, %xmm30 {%k2}
+// CHECK:  encoding: [0x62,0x22,0x5d,0x02,0x15,0xf4]
+          vprolvd %xmm20, %xmm20, %xmm30 {%k2}
+
+// CHECK: vprolvd %xmm20, %xmm20, %xmm30 {%k2} {z}
+// CHECK:  encoding: [0x62,0x22,0x5d,0x82,0x15,0xf4]
+          vprolvd %xmm20, %xmm20, %xmm30 {%k2} {z}
+
+// CHECK: vprolvd (%rcx), %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x62,0x5d,0x00,0x15,0x31]
+          vprolvd (%rcx), %xmm20, %xmm30
+
+// CHECK: vprolvd 291(%rax,%r14,8), %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x22,0x5d,0x00,0x15,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vprolvd 291(%rax,%r14,8), %xmm20, %xmm30
+
+// CHECK: vprolvd (%rcx){1to4}, %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x62,0x5d,0x10,0x15,0x31]
+          vprolvd (%rcx){1to4}, %xmm20, %xmm30
+
+// CHECK: vprolvd 2032(%rdx), %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x62,0x5d,0x00,0x15,0x72,0x7f]
+          vprolvd 2032(%rdx), %xmm20, %xmm30
+
+// CHECK: vprolvd 2048(%rdx), %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x62,0x5d,0x00,0x15,0xb2,0x00,0x08,0x00,0x00]
+          vprolvd 2048(%rdx), %xmm20, %xmm30
+
+// CHECK: vprolvd -2048(%rdx), %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x62,0x5d,0x00,0x15,0x72,0x80]
+          vprolvd -2048(%rdx), %xmm20, %xmm30
+
+// CHECK: vprolvd -2064(%rdx), %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x62,0x5d,0x00,0x15,0xb2,0xf0,0xf7,0xff,0xff]
+          vprolvd -2064(%rdx), %xmm20, %xmm30
+
+// CHECK: vprolvd 508(%rdx){1to4}, %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x62,0x5d,0x10,0x15,0x72,0x7f]
+          vprolvd 508(%rdx){1to4}, %xmm20, %xmm30
+
+// CHECK: vprolvd 512(%rdx){1to4}, %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x62,0x5d,0x10,0x15,0xb2,0x00,0x02,0x00,0x00]
+          vprolvd 512(%rdx){1to4}, %xmm20, %xmm30
+
+// CHECK: vprolvd -512(%rdx){1to4}, %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x62,0x5d,0x10,0x15,0x72,0x80]
+          vprolvd -512(%rdx){1to4}, %xmm20, %xmm30
+
+// CHECK: vprolvd -516(%rdx){1to4}, %xmm20, %xmm30
+// CHECK:  encoding: [0x62,0x62,0x5d,0x10,0x15,0xb2,0xfc,0xfd,0xff,0xff]
+          vprolvd -516(%rdx){1to4}, %xmm20, %xmm30
+
+// CHECK: vprolvd %ymm19, %ymm23, %ymm26
+// CHECK:  encoding: [0x62,0x22,0x45,0x20,0x15,0xd3]
+          vprolvd %ymm19, %ymm23, %ymm26
+
+// CHECK: vprolvd %ymm19, %ymm23, %ymm26 {%k1}
+// CHECK:  encoding: [0x62,0x22,0x45,0x21,0x15,0xd3]
+          vprolvd %ymm19, %ymm23, %ymm26 {%k1}
+
+// CHECK: vprolvd %ymm19, %ymm23, %ymm26 {%k1} {z}
+// CHECK:  encoding: [0x62,0x22,0x45,0xa1,0x15,0xd3]
+          vprolvd %ymm19, %ymm23, %ymm26 {%k1} {z}
+
+// CHECK: vprolvd (%rcx), %ymm23, %ymm26
+// CHECK:  encoding: [0x62,0x62,0x45,0x20,0x15,0x11]
+          vprolvd (%rcx), %ymm23, %ymm26
+
+// CHECK: vprolvd 291(%rax,%r14,8), %ymm23, %ymm26
+// CHECK:  encoding: [0x62,0x22,0x45,0x20,0x15,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vprolvd 291(%rax,%r14,8), %ymm23, %ymm26
+
+// CHECK: vprolvd (%rcx){1to8}, %ymm23, %ymm26
+// CHECK:  encoding: [0x62,0x62,0x45,0x30,0x15,0x11]
+          vprolvd (%rcx){1to8}, %ymm23, %ymm26
+
+// CHECK: vprolvd 4064(%rdx), %ymm23, %ymm26
+// CHECK:  encoding: [0x62,0x62,0x45,0x20,0x15,0x52,0x7f]
+          vprolvd 4064(%rdx), %ymm23, %ymm26
+
+// CHECK: vprolvd 4096(%rdx), %ymm23, %ymm26
+// CHECK:  encoding: [0x62,0x62,0x45,0x20,0x15,0x92,0x00,0x10,0x00,0x00]
+          vprolvd 4096(%rdx), %ymm23, %ymm26
+
+// CHECK: vprolvd -4096(%rdx), %ymm23, %ymm26
+// CHECK:  encoding: [0x62,0x62,0x45,0x20,0x15,0x52,0x80]
+          vprolvd -4096(%rdx), %ymm23, %ymm26
+
+// CHECK: vprolvd -4128(%rdx), %ymm23, %ymm26
+// CHECK:  encoding: [0x62,0x62,0x45,0x20,0x15,0x92,0xe0,0xef,0xff,0xff]
+          vprolvd -4128(%rdx), %ymm23, %ymm26
+
+// CHECK: vprolvd 508(%rdx){1to8}, %ymm23, %ymm26
+// CHECK:  encoding: [0x62,0x62,0x45,0x30,0x15,0x52,0x7f]
+          vprolvd 508(%rdx){1to8}, %ymm23, %ymm26
+
+// CHECK: vprolvd 512(%rdx){1to8}, %ymm23, %ymm26
+// CHECK:  encoding: [0x62,0x62,0x45,0x30,0x15,0x92,0x00,0x02,0x00,0x00]
+          vprolvd 512(%rdx){1to8}, %ymm23, %ymm26
+
+// CHECK: vprolvd -512(%rdx){1to8}, %ymm23, %ymm26
+// CHECK:  encoding: [0x62,0x62,0x45,0x30,0x15,0x52,0x80]
+          vprolvd -512(%rdx){1to8}, %ymm23, %ymm26
+
+// CHECK: vprolvd -516(%rdx){1to8}, %ymm23, %ymm26
+// CHECK:  encoding: [0x62,0x62,0x45,0x30,0x15,0x92,0xfc,0xfd,0xff,0xff]
+          vprolvd -516(%rdx){1to8}, %ymm23, %ymm26
+
+// CHECK: vprold $171, %xmm23, %xmm18
+// CHECK:  encoding: [0x62,0xb1,0x6d,0x00,0x72,0xcf,0xab]
+          vprold $171, %xmm23, %xmm18
+
+// CHECK: vprold $171, %xmm23, %xmm18 {%k3}
+// CHECK:  encoding: [0x62,0xb1,0x6d,0x03,0x72,0xcf,0xab]
+          vprold $171, %xmm23, %xmm18 {%k3}
+
+// CHECK: vprold $171, %xmm23, %xmm18 {%k3} {z}
+// CHECK:  encoding: [0x62,0xb1,0x6d,0x83,0x72,0xcf,0xab]
+          vprold $171, %xmm23, %xmm18 {%k3} {z}
+
+// CHECK: vprold $123, %xmm23, %xmm18
+// CHECK:  encoding: [0x62,0xb1,0x6d,0x00,0x72,0xcf,0x7b]
+          vprold $123, %xmm23, %xmm18
+
+// CHECK: vprold $123, (%rcx), %xmm18
+// CHECK:  encoding: [0x62,0xf1,0x6d,0x00,0x72,0x09,0x7b]
+          vprold $123, (%rcx), %xmm18
+
+// CHECK: vprold $123, 291(%rax,%r14,8), %xmm18
+// CHECK:  encoding: [0x62,0xb1,0x6d,0x00,0x72,0x8c,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vprold $123, 291(%rax,%r14,8), %xmm18
+
+// CHECK: vprold $123, (%rcx){1to4}, %xmm18
+// CHECK:  encoding: [0x62,0xf1,0x6d,0x10,0x72,0x09,0x7b]
+          vprold $123, (%rcx){1to4}, %xmm18
+
+// CHECK: vprold $123, 2032(%rdx), %xmm18
+// CHECK:  encoding: [0x62,0xf1,0x6d,0x00,0x72,0x4a,0x7f,0x7b]
+          vprold $123, 2032(%rdx), %xmm18
+
+// CHECK: vprold $123, 2048(%rdx), %xmm18
+// CHECK:  encoding: [0x62,0xf1,0x6d,0x00,0x72,0x8a,0x00,0x08,0x00,0x00,0x7b]
+          vprold $123, 2048(%rdx), %xmm18
+
+// CHECK: vprold $123, -2048(%rdx), %xmm18
+// CHECK:  encoding: [0x62,0xf1,0x6d,0x00,0x72,0x4a,0x80,0x7b]
+          vprold $123, -2048(%rdx), %xmm18
+
+// CHECK: vprold $123, -2064(%rdx), %xmm18
+// CHECK:  encoding: [0x62,0xf1,0x6d,0x00,0x72,0x8a,0xf0,0xf7,0xff,0xff,0x7b]
+          vprold $123, -2064(%rdx), %xmm18
+
+// CHECK: vprold $123, 508(%rdx){1to4}, %xmm18
+// CHECK:  encoding: [0x62,0xf1,0x6d,0x10,0x72,0x4a,0x7f,0x7b]
+          vprold $123, 508(%rdx){1to4}, %xmm18
+
+// CHECK: vprold $123, 512(%rdx){1to4}, %xmm18
+// CHECK:  encoding: [0x62,0xf1,0x6d,0x10,0x72,0x8a,0x00,0x02,0x00,0x00,0x7b]
+          vprold $123, 512(%rdx){1to4}, %xmm18
+
+// CHECK: vprold $123, -512(%rdx){1to4}, %xmm18
+// CHECK:  encoding: [0x62,0xf1,0x6d,0x10,0x72,0x4a,0x80,0x7b]
+          vprold $123, -512(%rdx){1to4}, %xmm18
+
+// CHECK: vprold $123, -516(%rdx){1to4}, %xmm18
+// CHECK:  encoding: [0x62,0xf1,0x6d,0x10,0x72,0x8a,0xfc,0xfd,0xff,0xff,0x7b]
+          vprold $123, -516(%rdx){1to4}, %xmm18
+
+// CHECK: vprold $171, %ymm19, %ymm29
+// CHECK:  encoding: [0x62,0xb1,0x15,0x20,0x72,0xcb,0xab]
+          vprold $171, %ymm19, %ymm29
+
+// CHECK: vprold $171, %ymm19, %ymm29 {%k1}
+// CHECK:  encoding: [0x62,0xb1,0x15,0x21,0x72,0xcb,0xab]
+          vprold $171, %ymm19, %ymm29 {%k1}
+
+// CHECK: vprold $171, %ymm19, %ymm29 {%k1} {z}
+// CHECK:  encoding: [0x62,0xb1,0x15,0xa1,0x72,0xcb,0xab]
+          vprold $171, %ymm19, %ymm29 {%k1} {z}
+
+// CHECK: vprold $123, %ymm19, %ymm29
+// CHECK:  encoding: [0x62,0xb1,0x15,0x20,0x72,0xcb,0x7b]
+          vprold $123, %ymm19, %ymm29
+
+// CHECK: vprold $123, (%rcx), %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x20,0x72,0x09,0x7b]
+          vprold $123, (%rcx), %ymm29
+
+// CHECK: vprold $123, 291(%rax,%r14,8), %ymm29
+// CHECK:  encoding: [0x62,0xb1,0x15,0x20,0x72,0x8c,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vprold $123, 291(%rax,%r14,8), %ymm29
+
+// CHECK: vprold $123, (%rcx){1to8}, %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x30,0x72,0x09,0x7b]
+          vprold $123, (%rcx){1to8}, %ymm29
+
+// CHECK: vprold $123, 4064(%rdx), %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x20,0x72,0x4a,0x7f,0x7b]
+          vprold $123, 4064(%rdx), %ymm29
+
+// CHECK: vprold $123, 4096(%rdx), %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x20,0x72,0x8a,0x00,0x10,0x00,0x00,0x7b]
+          vprold $123, 4096(%rdx), %ymm29
+
+// CHECK: vprold $123, -4096(%rdx), %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x20,0x72,0x4a,0x80,0x7b]
+          vprold $123, -4096(%rdx), %ymm29
+
+// CHECK: vprold $123, -4128(%rdx), %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x20,0x72,0x8a,0xe0,0xef,0xff,0xff,0x7b]
+          vprold $123, -4128(%rdx), %ymm29
+
+// CHECK: vprold $123, 508(%rdx){1to8}, %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x30,0x72,0x4a,0x7f,0x7b]
+          vprold $123, 508(%rdx){1to8}, %ymm29
+
+// CHECK: vprold $123, 512(%rdx){1to8}, %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x30,0x72,0x8a,0x00,0x02,0x00,0x00,0x7b]
+          vprold $123, 512(%rdx){1to8}, %ymm29
+
+// CHECK: vprold $123, -512(%rdx){1to8}, %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x30,0x72,0x4a,0x80,0x7b]
+          vprold $123, -512(%rdx){1to8}, %ymm29
+
+// CHECK: vprold $123, -516(%rdx){1to8}, %ymm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x30,0x72,0x8a,0xfc,0xfd,0xff,0xff,0x7b]
+          vprold $123, -516(%rdx){1to8}, %ymm29
+
+// CHECK: vprolvq %xmm17, %xmm22, %xmm25
+// CHECK:  encoding: [0x62,0x22,0xcd,0x00,0x15,0xc9]
+          vprolvq %xmm17, %xmm22, %xmm25
+
+// CHECK: vprolvq %xmm17, %xmm22, %xmm25 {%k5}
+// CHECK:  encoding: [0x62,0x22,0xcd,0x05,0x15,0xc9]
+          vprolvq %xmm17, %xmm22, %xmm25 {%k5}
+
+// CHECK: vprolvq %xmm17, %xmm22, %xmm25 {%k5} {z}
+// CHECK:  encoding: [0x62,0x22,0xcd,0x85,0x15,0xc9]
+          vprolvq %xmm17, %xmm22, %xmm25 {%k5} {z}
+
+// CHECK: vprolvq (%rcx), %xmm22, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xcd,0x00,0x15,0x09]
+          vprolvq (%rcx), %xmm22, %xmm25
+
+// CHECK: vprolvq 291(%rax,%r14,8), %xmm22, %xmm25
+// CHECK:  encoding: [0x62,0x22,0xcd,0x00,0x15,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vprolvq 291(%rax,%r14,8), %xmm22, %xmm25
+
+// CHECK: vprolvq (%rcx){1to2}, %xmm22, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xcd,0x10,0x15,0x09]
+          vprolvq (%rcx){1to2}, %xmm22, %xmm25
+
+// CHECK: vprolvq 2032(%rdx), %xmm22, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xcd,0x00,0x15,0x4a,0x7f]
+          vprolvq 2032(%rdx), %xmm22, %xmm25
+
+// CHECK: vprolvq 2048(%rdx), %xmm22, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xcd,0x00,0x15,0x8a,0x00,0x08,0x00,0x00]
+          vprolvq 2048(%rdx), %xmm22, %xmm25
+
+// CHECK: vprolvq -2048(%rdx), %xmm22, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xcd,0x00,0x15,0x4a,0x80]
+          vprolvq -2048(%rdx), %xmm22, %xmm25
+
+// CHECK: vprolvq -2064(%rdx), %xmm22, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xcd,0x00,0x15,0x8a,0xf0,0xf7,0xff,0xff]
+          vprolvq -2064(%rdx), %xmm22, %xmm25
+
+// CHECK: vprolvq 1016(%rdx){1to2}, %xmm22, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xcd,0x10,0x15,0x4a,0x7f]
+          vprolvq 1016(%rdx){1to2}, %xmm22, %xmm25
+
+// CHECK: vprolvq 1024(%rdx){1to2}, %xmm22, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xcd,0x10,0x15,0x8a,0x00,0x04,0x00,0x00]
+          vprolvq 1024(%rdx){1to2}, %xmm22, %xmm25
+
+// CHECK: vprolvq -1024(%rdx){1to2}, %xmm22, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xcd,0x10,0x15,0x4a,0x80]
+          vprolvq -1024(%rdx){1to2}, %xmm22, %xmm25
+
+// CHECK: vprolvq -1032(%rdx){1to2}, %xmm22, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xcd,0x10,0x15,0x8a,0xf8,0xfb,0xff,0xff]
+          vprolvq -1032(%rdx){1to2}, %xmm22, %xmm25
+
+// CHECK: vprolvq %ymm28, %ymm17, %ymm17
+// CHECK:  encoding: [0x62,0x82,0xf5,0x20,0x15,0xcc]
+          vprolvq %ymm28, %ymm17, %ymm17
+
+// CHECK: vprolvq %ymm28, %ymm17, %ymm17 {%k3}
+// CHECK:  encoding: [0x62,0x82,0xf5,0x23,0x15,0xcc]
+          vprolvq %ymm28, %ymm17, %ymm17 {%k3}
+
+// CHECK: vprolvq %ymm28, %ymm17, %ymm17 {%k3} {z}
+// CHECK:  encoding: [0x62,0x82,0xf5,0xa3,0x15,0xcc]
+          vprolvq %ymm28, %ymm17, %ymm17 {%k3} {z}
+
+// CHECK: vprolvq (%rcx), %ymm17, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0xf5,0x20,0x15,0x09]
+          vprolvq (%rcx), %ymm17, %ymm17
+
+// CHECK: vprolvq 291(%rax,%r14,8), %ymm17, %ymm17
+// CHECK:  encoding: [0x62,0xa2,0xf5,0x20,0x15,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vprolvq 291(%rax,%r14,8), %ymm17, %ymm17
+
+// CHECK: vprolvq (%rcx){1to4}, %ymm17, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0xf5,0x30,0x15,0x09]
+          vprolvq (%rcx){1to4}, %ymm17, %ymm17
+
+// CHECK: vprolvq 4064(%rdx), %ymm17, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0xf5,0x20,0x15,0x4a,0x7f]
+          vprolvq 4064(%rdx), %ymm17, %ymm17
+
+// CHECK: vprolvq 4096(%rdx), %ymm17, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0xf5,0x20,0x15,0x8a,0x00,0x10,0x00,0x00]
+          vprolvq 4096(%rdx), %ymm17, %ymm17
+
+// CHECK: vprolvq -4096(%rdx), %ymm17, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0xf5,0x20,0x15,0x4a,0x80]
+          vprolvq -4096(%rdx), %ymm17, %ymm17
+
+// CHECK: vprolvq -4128(%rdx), %ymm17, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0xf5,0x20,0x15,0x8a,0xe0,0xef,0xff,0xff]
+          vprolvq -4128(%rdx), %ymm17, %ymm17
+
+// CHECK: vprolvq 1016(%rdx){1to4}, %ymm17, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0xf5,0x30,0x15,0x4a,0x7f]
+          vprolvq 1016(%rdx){1to4}, %ymm17, %ymm17
+
+// CHECK: vprolvq 1024(%rdx){1to4}, %ymm17, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0xf5,0x30,0x15,0x8a,0x00,0x04,0x00,0x00]
+          vprolvq 1024(%rdx){1to4}, %ymm17, %ymm17
+
+// CHECK: vprolvq -1024(%rdx){1to4}, %ymm17, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0xf5,0x30,0x15,0x4a,0x80]
+          vprolvq -1024(%rdx){1to4}, %ymm17, %ymm17
+
+// CHECK: vprolvq -1032(%rdx){1to4}, %ymm17, %ymm17
+// CHECK:  encoding: [0x62,0xe2,0xf5,0x30,0x15,0x8a,0xf8,0xfb,0xff,0xff]
+          vprolvq -1032(%rdx){1to4}, %ymm17, %ymm17
+
+// CHECK: vprolq $171, %xmm19, %xmm28
+// CHECK:  encoding: [0x62,0xb1,0x9d,0x00,0x72,0xcb,0xab]
+          vprolq $171, %xmm19, %xmm28
+
+// CHECK: vprolq $171, %xmm19, %xmm28 {%k2}
+// CHECK:  encoding: [0x62,0xb1,0x9d,0x02,0x72,0xcb,0xab]
+          vprolq $171, %xmm19, %xmm28 {%k2}
+
+// CHECK: vprolq $171, %xmm19, %xmm28 {%k2} {z}
+// CHECK:  encoding: [0x62,0xb1,0x9d,0x82,0x72,0xcb,0xab]
+          vprolq $171, %xmm19, %xmm28 {%k2} {z}
+
+// CHECK: vprolq $123, %xmm19, %xmm28
+// CHECK:  encoding: [0x62,0xb1,0x9d,0x00,0x72,0xcb,0x7b]
+          vprolq $123, %xmm19, %xmm28
+
+// CHECK: vprolq $123, (%rcx), %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x00,0x72,0x09,0x7b]
+          vprolq $123, (%rcx), %xmm28
+
+// CHECK: vprolq $123, 291(%rax,%r14,8), %xmm28
+// CHECK:  encoding: [0x62,0xb1,0x9d,0x00,0x72,0x8c,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vprolq $123, 291(%rax,%r14,8), %xmm28
+
+// CHECK: vprolq $123, (%rcx){1to2}, %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x10,0x72,0x09,0x7b]
+          vprolq $123, (%rcx){1to2}, %xmm28
+
+// CHECK: vprolq $123, 2032(%rdx), %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x00,0x72,0x4a,0x7f,0x7b]
+          vprolq $123, 2032(%rdx), %xmm28
+
+// CHECK: vprolq $123, 2048(%rdx), %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x00,0x72,0x8a,0x00,0x08,0x00,0x00,0x7b]
+          vprolq $123, 2048(%rdx), %xmm28
+
+// CHECK: vprolq $123, -2048(%rdx), %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x00,0x72,0x4a,0x80,0x7b]
+          vprolq $123, -2048(%rdx), %xmm28
+
+// CHECK: vprolq $123, -2064(%rdx), %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x00,0x72,0x8a,0xf0,0xf7,0xff,0xff,0x7b]
+          vprolq $123, -2064(%rdx), %xmm28
+
+// CHECK: vprolq $123, 1016(%rdx){1to2}, %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x10,0x72,0x4a,0x7f,0x7b]
+          vprolq $123, 1016(%rdx){1to2}, %xmm28
+
+// CHECK: vprolq $123, 1024(%rdx){1to2}, %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x10,0x72,0x8a,0x00,0x04,0x00,0x00,0x7b]
+          vprolq $123, 1024(%rdx){1to2}, %xmm28
+
+// CHECK: vprolq $123, -1024(%rdx){1to2}, %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x10,0x72,0x4a,0x80,0x7b]
+          vprolq $123, -1024(%rdx){1to2}, %xmm28
+
+// CHECK: vprolq $123, -1032(%rdx){1to2}, %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x10,0x72,0x8a,0xf8,0xfb,0xff,0xff,0x7b]
+          vprolq $123, -1032(%rdx){1to2}, %xmm28
+
+// CHECK: vprolq $171, %ymm24, %ymm25
+// CHECK:  encoding: [0x62,0x91,0xb5,0x20,0x72,0xc8,0xab]
+          vprolq $171, %ymm24, %ymm25
+
+// CHECK: vprolq $171, %ymm24, %ymm25 {%k5}
+// CHECK:  encoding: [0x62,0x91,0xb5,0x25,0x72,0xc8,0xab]
+          vprolq $171, %ymm24, %ymm25 {%k5}
+
+// CHECK: vprolq $171, %ymm24, %ymm25 {%k5} {z}
+// CHECK:  encoding: [0x62,0x91,0xb5,0xa5,0x72,0xc8,0xab]
+          vprolq $171, %ymm24, %ymm25 {%k5} {z}
+
+// CHECK: vprolq $123, %ymm24, %ymm25
+// CHECK:  encoding: [0x62,0x91,0xb5,0x20,0x72,0xc8,0x7b]
+          vprolq $123, %ymm24, %ymm25
+
+// CHECK: vprolq $123, (%rcx), %ymm25
+// CHECK:  encoding: [0x62,0xf1,0xb5,0x20,0x72,0x09,0x7b]
+          vprolq $123, (%rcx), %ymm25
+
+// CHECK: vprolq $123, 291(%rax,%r14,8), %ymm25
+// CHECK:  encoding: [0x62,0xb1,0xb5,0x20,0x72,0x8c,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vprolq $123, 291(%rax,%r14,8), %ymm25
+
+// CHECK: vprolq $123, (%rcx){1to4}, %ymm25
+// CHECK:  encoding: [0x62,0xf1,0xb5,0x30,0x72,0x09,0x7b]
+          vprolq $123, (%rcx){1to4}, %ymm25
+
+// CHECK: vprolq $123, 4064(%rdx), %ymm25
+// CHECK:  encoding: [0x62,0xf1,0xb5,0x20,0x72,0x4a,0x7f,0x7b]
+          vprolq $123, 4064(%rdx), %ymm25
+
+// CHECK: vprolq $123, 4096(%rdx), %ymm25
+// CHECK:  encoding: [0x62,0xf1,0xb5,0x20,0x72,0x8a,0x00,0x10,0x00,0x00,0x7b]
+          vprolq $123, 4096(%rdx), %ymm25
+
+// CHECK: vprolq $123, -4096(%rdx), %ymm25
+// CHECK:  encoding: [0x62,0xf1,0xb5,0x20,0x72,0x4a,0x80,0x7b]
+          vprolq $123, -4096(%rdx), %ymm25
+
+// CHECK: vprolq $123, -4128(%rdx), %ymm25
+// CHECK:  encoding: [0x62,0xf1,0xb5,0x20,0x72,0x8a,0xe0,0xef,0xff,0xff,0x7b]
+          vprolq $123, -4128(%rdx), %ymm25
+
+// CHECK: vprolq $123, 1016(%rdx){1to4}, %ymm25
+// CHECK:  encoding: [0x62,0xf1,0xb5,0x30,0x72,0x4a,0x7f,0x7b]
+          vprolq $123, 1016(%rdx){1to4}, %ymm25
+
+// CHECK: vprolq $123, 1024(%rdx){1to4}, %ymm25
+// CHECK:  encoding: [0x62,0xf1,0xb5,0x30,0x72,0x8a,0x00,0x04,0x00,0x00,0x7b]
+          vprolq $123, 1024(%rdx){1to4}, %ymm25
+
+// CHECK: vprolq $123, -1024(%rdx){1to4}, %ymm25
+// CHECK:  encoding: [0x62,0xf1,0xb5,0x30,0x72,0x4a,0x80,0x7b]
+          vprolq $123, -1024(%rdx){1to4}, %ymm25
+
+// CHECK: vprolq $123, -1032(%rdx){1to4}, %ymm25
+// CHECK:  encoding: [0x62,0xf1,0xb5,0x30,0x72,0x8a,0xf8,0xfb,0xff,0xff,0x7b]
+          vprolq $123, -1032(%rdx){1to4}, %ymm25
+
+// CHECK: vprorvd %xmm22, %xmm26, %xmm25
+// CHECK:  encoding: [0x62,0x22,0x2d,0x00,0x14,0xce]
+          vprorvd %xmm22, %xmm26, %xmm25
+
+// CHECK: vprorvd %xmm22, %xmm26, %xmm25 {%k4}
+// CHECK:  encoding: [0x62,0x22,0x2d,0x04,0x14,0xce]
+          vprorvd %xmm22, %xmm26, %xmm25 {%k4}
+
+// CHECK: vprorvd %xmm22, %xmm26, %xmm25 {%k4} {z}
+// CHECK:  encoding: [0x62,0x22,0x2d,0x84,0x14,0xce]
+          vprorvd %xmm22, %xmm26, %xmm25 {%k4} {z}
+
+// CHECK: vprorvd (%rcx), %xmm26, %xmm25
+// CHECK:  encoding: [0x62,0x62,0x2d,0x00,0x14,0x09]
+          vprorvd (%rcx), %xmm26, %xmm25
+
+// CHECK: vprorvd 291(%rax,%r14,8), %xmm26, %xmm25
+// CHECK:  encoding: [0x62,0x22,0x2d,0x00,0x14,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vprorvd 291(%rax,%r14,8), %xmm26, %xmm25
+
+// CHECK: vprorvd (%rcx){1to4}, %xmm26, %xmm25
+// CHECK:  encoding: [0x62,0x62,0x2d,0x10,0x14,0x09]
+          vprorvd (%rcx){1to4}, %xmm26, %xmm25
+
+// CHECK: vprorvd 2032(%rdx), %xmm26, %xmm25
+// CHECK:  encoding: [0x62,0x62,0x2d,0x00,0x14,0x4a,0x7f]
+          vprorvd 2032(%rdx), %xmm26, %xmm25
+
+// CHECK: vprorvd 2048(%rdx), %xmm26, %xmm25
+// CHECK:  encoding: [0x62,0x62,0x2d,0x00,0x14,0x8a,0x00,0x08,0x00,0x00]
+          vprorvd 2048(%rdx), %xmm26, %xmm25
+
+// CHECK: vprorvd -2048(%rdx), %xmm26, %xmm25
+// CHECK:  encoding: [0x62,0x62,0x2d,0x00,0x14,0x4a,0x80]
+          vprorvd -2048(%rdx), %xmm26, %xmm25
+
+// CHECK: vprorvd -2064(%rdx), %xmm26, %xmm25
+// CHECK:  encoding: [0x62,0x62,0x2d,0x00,0x14,0x8a,0xf0,0xf7,0xff,0xff]
+          vprorvd -2064(%rdx), %xmm26, %xmm25
+
+// CHECK: vprorvd 508(%rdx){1to4}, %xmm26, %xmm25
+// CHECK:  encoding: [0x62,0x62,0x2d,0x10,0x14,0x4a,0x7f]
+          vprorvd 508(%rdx){1to4}, %xmm26, %xmm25
+
+// CHECK: vprorvd 512(%rdx){1to4}, %xmm26, %xmm25
+// CHECK:  encoding: [0x62,0x62,0x2d,0x10,0x14,0x8a,0x00,0x02,0x00,0x00]
+          vprorvd 512(%rdx){1to4}, %xmm26, %xmm25
+
+// CHECK: vprorvd -512(%rdx){1to4}, %xmm26, %xmm25
+// CHECK:  encoding: [0x62,0x62,0x2d,0x10,0x14,0x4a,0x80]
+          vprorvd -512(%rdx){1to4}, %xmm26, %xmm25
+
+// CHECK: vprorvd -516(%rdx){1to4}, %xmm26, %xmm25
+// CHECK:  encoding: [0x62,0x62,0x2d,0x10,0x14,0x8a,0xfc,0xfd,0xff,0xff]
+          vprorvd -516(%rdx){1to4}, %xmm26, %xmm25
+
+// CHECK: vprorvd %ymm25, %ymm28, %ymm24
+// CHECK:  encoding: [0x62,0x02,0x1d,0x20,0x14,0xc1]
+          vprorvd %ymm25, %ymm28, %ymm24
+
+// CHECK: vprorvd %ymm25, %ymm28, %ymm24 {%k4}
+// CHECK:  encoding: [0x62,0x02,0x1d,0x24,0x14,0xc1]
+          vprorvd %ymm25, %ymm28, %ymm24 {%k4}
+
+// CHECK: vprorvd %ymm25, %ymm28, %ymm24 {%k4} {z}
+// CHECK:  encoding: [0x62,0x02,0x1d,0xa4,0x14,0xc1]
+          vprorvd %ymm25, %ymm28, %ymm24 {%k4} {z}
+
+// CHECK: vprorvd (%rcx), %ymm28, %ymm24
+// CHECK:  encoding: [0x62,0x62,0x1d,0x20,0x14,0x01]
+          vprorvd (%rcx), %ymm28, %ymm24
+
+// CHECK: vprorvd 291(%rax,%r14,8), %ymm28, %ymm24
+// CHECK:  encoding: [0x62,0x22,0x1d,0x20,0x14,0x84,0xf0,0x23,0x01,0x00,0x00]
+          vprorvd 291(%rax,%r14,8), %ymm28, %ymm24
+
+// CHECK: vprorvd (%rcx){1to8}, %ymm28, %ymm24
+// CHECK:  encoding: [0x62,0x62,0x1d,0x30,0x14,0x01]
+          vprorvd (%rcx){1to8}, %ymm28, %ymm24
+
+// CHECK: vprorvd 4064(%rdx), %ymm28, %ymm24
+// CHECK:  encoding: [0x62,0x62,0x1d,0x20,0x14,0x42,0x7f]
+          vprorvd 4064(%rdx), %ymm28, %ymm24
+
+// CHECK: vprorvd 4096(%rdx), %ymm28, %ymm24
+// CHECK:  encoding: [0x62,0x62,0x1d,0x20,0x14,0x82,0x00,0x10,0x00,0x00]
+          vprorvd 4096(%rdx), %ymm28, %ymm24
+
+// CHECK: vprorvd -4096(%rdx), %ymm28, %ymm24
+// CHECK:  encoding: [0x62,0x62,0x1d,0x20,0x14,0x42,0x80]
+          vprorvd -4096(%rdx), %ymm28, %ymm24
+
+// CHECK: vprorvd -4128(%rdx), %ymm28, %ymm24
+// CHECK:  encoding: [0x62,0x62,0x1d,0x20,0x14,0x82,0xe0,0xef,0xff,0xff]
+          vprorvd -4128(%rdx), %ymm28, %ymm24
+
+// CHECK: vprorvd 508(%rdx){1to8}, %ymm28, %ymm24
+// CHECK:  encoding: [0x62,0x62,0x1d,0x30,0x14,0x42,0x7f]
+          vprorvd 508(%rdx){1to8}, %ymm28, %ymm24
+
+// CHECK: vprorvd 512(%rdx){1to8}, %ymm28, %ymm24
+// CHECK:  encoding: [0x62,0x62,0x1d,0x30,0x14,0x82,0x00,0x02,0x00,0x00]
+          vprorvd 512(%rdx){1to8}, %ymm28, %ymm24
+
+// CHECK: vprorvd -512(%rdx){1to8}, %ymm28, %ymm24
+// CHECK:  encoding: [0x62,0x62,0x1d,0x30,0x14,0x42,0x80]
+          vprorvd -512(%rdx){1to8}, %ymm28, %ymm24
+
+// CHECK: vprorvd -516(%rdx){1to8}, %ymm28, %ymm24
+// CHECK:  encoding: [0x62,0x62,0x1d,0x30,0x14,0x82,0xfc,0xfd,0xff,0xff]
+          vprorvd -516(%rdx){1to8}, %ymm28, %ymm24
+
+// CHECK: vprord $171, %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x91,0x15,0x00,0x72,0xc1,0xab]
+          vprord $171, %xmm25, %xmm29
+
+// CHECK: vprord $171, %xmm25, %xmm29 {%k3}
+// CHECK:  encoding: [0x62,0x91,0x15,0x03,0x72,0xc1,0xab]
+          vprord $171, %xmm25, %xmm29 {%k3}
+
+// CHECK: vprord $171, %xmm25, %xmm29 {%k3} {z}
+// CHECK:  encoding: [0x62,0x91,0x15,0x83,0x72,0xc1,0xab]
+          vprord $171, %xmm25, %xmm29 {%k3} {z}
+
+// CHECK: vprord $123, %xmm25, %xmm29
+// CHECK:  encoding: [0x62,0x91,0x15,0x00,0x72,0xc1,0x7b]
+          vprord $123, %xmm25, %xmm29
+
+// CHECK: vprord $123, (%rcx), %xmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x00,0x72,0x01,0x7b]
+          vprord $123, (%rcx), %xmm29
+
+// CHECK: vprord $123, 291(%rax,%r14,8), %xmm29
+// CHECK:  encoding: [0x62,0xb1,0x15,0x00,0x72,0x84,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vprord $123, 291(%rax,%r14,8), %xmm29
+
+// CHECK: vprord $123, (%rcx){1to4}, %xmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x10,0x72,0x01,0x7b]
+          vprord $123, (%rcx){1to4}, %xmm29
+
+// CHECK: vprord $123, 2032(%rdx), %xmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x00,0x72,0x42,0x7f,0x7b]
+          vprord $123, 2032(%rdx), %xmm29
+
+// CHECK: vprord $123, 2048(%rdx), %xmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x00,0x72,0x82,0x00,0x08,0x00,0x00,0x7b]
+          vprord $123, 2048(%rdx), %xmm29
+
+// CHECK: vprord $123, -2048(%rdx), %xmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x00,0x72,0x42,0x80,0x7b]
+          vprord $123, -2048(%rdx), %xmm29
+
+// CHECK: vprord $123, -2064(%rdx), %xmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x00,0x72,0x82,0xf0,0xf7,0xff,0xff,0x7b]
+          vprord $123, -2064(%rdx), %xmm29
+
+// CHECK: vprord $123, 508(%rdx){1to4}, %xmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x10,0x72,0x42,0x7f,0x7b]
+          vprord $123, 508(%rdx){1to4}, %xmm29
+
+// CHECK: vprord $123, 512(%rdx){1to4}, %xmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x10,0x72,0x82,0x00,0x02,0x00,0x00,0x7b]
+          vprord $123, 512(%rdx){1to4}, %xmm29
+
+// CHECK: vprord $123, -512(%rdx){1to4}, %xmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x10,0x72,0x42,0x80,0x7b]
+          vprord $123, -512(%rdx){1to4}, %xmm29
+
+// CHECK: vprord $123, -516(%rdx){1to4}, %xmm29
+// CHECK:  encoding: [0x62,0xf1,0x15,0x10,0x72,0x82,0xfc,0xfd,0xff,0xff,0x7b]
+          vprord $123, -516(%rdx){1to4}, %xmm29
+
+// CHECK: vprord $171, %ymm29, %ymm30
+// CHECK:  encoding: [0x62,0x91,0x0d,0x20,0x72,0xc5,0xab]
+          vprord $171, %ymm29, %ymm30
+
+// CHECK: vprord $171, %ymm29, %ymm30 {%k6}
+// CHECK:  encoding: [0x62,0x91,0x0d,0x26,0x72,0xc5,0xab]
+          vprord $171, %ymm29, %ymm30 {%k6}
+
+// CHECK: vprord $171, %ymm29, %ymm30 {%k6} {z}
+// CHECK:  encoding: [0x62,0x91,0x0d,0xa6,0x72,0xc5,0xab]
+          vprord $171, %ymm29, %ymm30 {%k6} {z}
+
+// CHECK: vprord $123, %ymm29, %ymm30
+// CHECK:  encoding: [0x62,0x91,0x0d,0x20,0x72,0xc5,0x7b]
+          vprord $123, %ymm29, %ymm30
+
+// CHECK: vprord $123, (%rcx), %ymm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x20,0x72,0x01,0x7b]
+          vprord $123, (%rcx), %ymm30
+
+// CHECK: vprord $123, 291(%rax,%r14,8), %ymm30
+// CHECK:  encoding: [0x62,0xb1,0x0d,0x20,0x72,0x84,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vprord $123, 291(%rax,%r14,8), %ymm30
+
+// CHECK: vprord $123, (%rcx){1to8}, %ymm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x30,0x72,0x01,0x7b]
+          vprord $123, (%rcx){1to8}, %ymm30
+
+// CHECK: vprord $123, 4064(%rdx), %ymm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x20,0x72,0x42,0x7f,0x7b]
+          vprord $123, 4064(%rdx), %ymm30
+
+// CHECK: vprord $123, 4096(%rdx), %ymm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x20,0x72,0x82,0x00,0x10,0x00,0x00,0x7b]
+          vprord $123, 4096(%rdx), %ymm30
+
+// CHECK: vprord $123, -4096(%rdx), %ymm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x20,0x72,0x42,0x80,0x7b]
+          vprord $123, -4096(%rdx), %ymm30
+
+// CHECK: vprord $123, -4128(%rdx), %ymm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x20,0x72,0x82,0xe0,0xef,0xff,0xff,0x7b]
+          vprord $123, -4128(%rdx), %ymm30
+
+// CHECK: vprord $123, 508(%rdx){1to8}, %ymm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x30,0x72,0x42,0x7f,0x7b]
+          vprord $123, 508(%rdx){1to8}, %ymm30
+
+// CHECK: vprord $123, 512(%rdx){1to8}, %ymm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x30,0x72,0x82,0x00,0x02,0x00,0x00,0x7b]
+          vprord $123, 512(%rdx){1to8}, %ymm30
+
+// CHECK: vprord $123, -512(%rdx){1to8}, %ymm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x30,0x72,0x42,0x80,0x7b]
+          vprord $123, -512(%rdx){1to8}, %ymm30
+
+// CHECK: vprord $123, -516(%rdx){1to8}, %ymm30
+// CHECK:  encoding: [0x62,0xf1,0x0d,0x30,0x72,0x82,0xfc,0xfd,0xff,0xff,0x7b]
+          vprord $123, -516(%rdx){1to8}, %ymm30
+
+// CHECK: vprorvq %xmm24, %xmm21, %xmm26
+// CHECK:  encoding: [0x62,0x02,0xd5,0x00,0x14,0xd0]
+          vprorvq %xmm24, %xmm21, %xmm26
+
+// CHECK: vprorvq %xmm24, %xmm21, %xmm26 {%k4}
+// CHECK:  encoding: [0x62,0x02,0xd5,0x04,0x14,0xd0]
+          vprorvq %xmm24, %xmm21, %xmm26 {%k4}
+
+// CHECK: vprorvq %xmm24, %xmm21, %xmm26 {%k4} {z}
+// CHECK:  encoding: [0x62,0x02,0xd5,0x84,0x14,0xd0]
+          vprorvq %xmm24, %xmm21, %xmm26 {%k4} {z}
+
+// CHECK: vprorvq (%rcx), %xmm21, %xmm26
+// CHECK:  encoding: [0x62,0x62,0xd5,0x00,0x14,0x11]
+          vprorvq (%rcx), %xmm21, %xmm26
+
+// CHECK: vprorvq 291(%rax,%r14,8), %xmm21, %xmm26
+// CHECK:  encoding: [0x62,0x22,0xd5,0x00,0x14,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vprorvq 291(%rax,%r14,8), %xmm21, %xmm26
+
+// CHECK: vprorvq (%rcx){1to2}, %xmm21, %xmm26
+// CHECK:  encoding: [0x62,0x62,0xd5,0x10,0x14,0x11]
+          vprorvq (%rcx){1to2}, %xmm21, %xmm26
+
+// CHECK: vprorvq 2032(%rdx), %xmm21, %xmm26
+// CHECK:  encoding: [0x62,0x62,0xd5,0x00,0x14,0x52,0x7f]
+          vprorvq 2032(%rdx), %xmm21, %xmm26
+
+// CHECK: vprorvq 2048(%rdx), %xmm21, %xmm26
+// CHECK:  encoding: [0x62,0x62,0xd5,0x00,0x14,0x92,0x00,0x08,0x00,0x00]
+          vprorvq 2048(%rdx), %xmm21, %xmm26
+
+// CHECK: vprorvq -2048(%rdx), %xmm21, %xmm26
+// CHECK:  encoding: [0x62,0x62,0xd5,0x00,0x14,0x52,0x80]
+          vprorvq -2048(%rdx), %xmm21, %xmm26
+
+// CHECK: vprorvq -2064(%rdx), %xmm21, %xmm26
+// CHECK:  encoding: [0x62,0x62,0xd5,0x00,0x14,0x92,0xf0,0xf7,0xff,0xff]
+          vprorvq -2064(%rdx), %xmm21, %xmm26
+
+// CHECK: vprorvq 1016(%rdx){1to2}, %xmm21, %xmm26
+// CHECK:  encoding: [0x62,0x62,0xd5,0x10,0x14,0x52,0x7f]
+          vprorvq 1016(%rdx){1to2}, %xmm21, %xmm26
+
+// CHECK: vprorvq 1024(%rdx){1to2}, %xmm21, %xmm26
+// CHECK:  encoding: [0x62,0x62,0xd5,0x10,0x14,0x92,0x00,0x04,0x00,0x00]
+          vprorvq 1024(%rdx){1to2}, %xmm21, %xmm26
+
+// CHECK: vprorvq -1024(%rdx){1to2}, %xmm21, %xmm26
+// CHECK:  encoding: [0x62,0x62,0xd5,0x10,0x14,0x52,0x80]
+          vprorvq -1024(%rdx){1to2}, %xmm21, %xmm26
+
+// CHECK: vprorvq -1032(%rdx){1to2}, %xmm21, %xmm26
+// CHECK:  encoding: [0x62,0x62,0xd5,0x10,0x14,0x92,0xf8,0xfb,0xff,0xff]
+          vprorvq -1032(%rdx){1to2}, %xmm21, %xmm26
+
+// CHECK: vprorvq %ymm28, %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0x82,0xbd,0x20,0x14,0xe4]
+          vprorvq %ymm28, %ymm24, %ymm20
+
+// CHECK: vprorvq %ymm28, %ymm24, %ymm20 {%k7}
+// CHECK:  encoding: [0x62,0x82,0xbd,0x27,0x14,0xe4]
+          vprorvq %ymm28, %ymm24, %ymm20 {%k7}
+
+// CHECK: vprorvq %ymm28, %ymm24, %ymm20 {%k7} {z}
+// CHECK:  encoding: [0x62,0x82,0xbd,0xa7,0x14,0xe4]
+          vprorvq %ymm28, %ymm24, %ymm20 {%k7} {z}
+
+// CHECK: vprorvq (%rcx), %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0xbd,0x20,0x14,0x21]
+          vprorvq (%rcx), %ymm24, %ymm20
+
+// CHECK: vprorvq 291(%rax,%r14,8), %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xa2,0xbd,0x20,0x14,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vprorvq 291(%rax,%r14,8), %ymm24, %ymm20
+
+// CHECK: vprorvq (%rcx){1to4}, %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0xbd,0x30,0x14,0x21]
+          vprorvq (%rcx){1to4}, %ymm24, %ymm20
+
+// CHECK: vprorvq 4064(%rdx), %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0xbd,0x20,0x14,0x62,0x7f]
+          vprorvq 4064(%rdx), %ymm24, %ymm20
+
+// CHECK: vprorvq 4096(%rdx), %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0xbd,0x20,0x14,0xa2,0x00,0x10,0x00,0x00]
+          vprorvq 4096(%rdx), %ymm24, %ymm20
+
+// CHECK: vprorvq -4096(%rdx), %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0xbd,0x20,0x14,0x62,0x80]
+          vprorvq -4096(%rdx), %ymm24, %ymm20
+
+// CHECK: vprorvq -4128(%rdx), %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0xbd,0x20,0x14,0xa2,0xe0,0xef,0xff,0xff]
+          vprorvq -4128(%rdx), %ymm24, %ymm20
+
+// CHECK: vprorvq 1016(%rdx){1to4}, %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0xbd,0x30,0x14,0x62,0x7f]
+          vprorvq 1016(%rdx){1to4}, %ymm24, %ymm20
+
+// CHECK: vprorvq 1024(%rdx){1to4}, %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0xbd,0x30,0x14,0xa2,0x00,0x04,0x00,0x00]
+          vprorvq 1024(%rdx){1to4}, %ymm24, %ymm20
+
+// CHECK: vprorvq -1024(%rdx){1to4}, %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0xbd,0x30,0x14,0x62,0x80]
+          vprorvq -1024(%rdx){1to4}, %ymm24, %ymm20
+
+// CHECK: vprorvq -1032(%rdx){1to4}, %ymm24, %ymm20
+// CHECK:  encoding: [0x62,0xe2,0xbd,0x30,0x14,0xa2,0xf8,0xfb,0xff,0xff]
+          vprorvq -1032(%rdx){1to4}, %ymm24, %ymm20
+
+// CHECK: vprorq $171, %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x91,0x9d,0x00,0x72,0xc4,0xab]
+          vprorq $171, %xmm28, %xmm28
+
+// CHECK: vprorq $171, %xmm28, %xmm28 {%k1}
+// CHECK:  encoding: [0x62,0x91,0x9d,0x01,0x72,0xc4,0xab]
+          vprorq $171, %xmm28, %xmm28 {%k1}
+
+// CHECK: vprorq $171, %xmm28, %xmm28 {%k1} {z}
+// CHECK:  encoding: [0x62,0x91,0x9d,0x81,0x72,0xc4,0xab]
+          vprorq $171, %xmm28, %xmm28 {%k1} {z}
+
+// CHECK: vprorq $123, %xmm28, %xmm28
+// CHECK:  encoding: [0x62,0x91,0x9d,0x00,0x72,0xc4,0x7b]
+          vprorq $123, %xmm28, %xmm28
+
+// CHECK: vprorq $123, (%rcx), %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x00,0x72,0x01,0x7b]
+          vprorq $123, (%rcx), %xmm28
+
+// CHECK: vprorq $123, 291(%rax,%r14,8), %xmm28
+// CHECK:  encoding: [0x62,0xb1,0x9d,0x00,0x72,0x84,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vprorq $123, 291(%rax,%r14,8), %xmm28
+
+// CHECK: vprorq $123, (%rcx){1to2}, %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x10,0x72,0x01,0x7b]
+          vprorq $123, (%rcx){1to2}, %xmm28
+
+// CHECK: vprorq $123, 2032(%rdx), %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x00,0x72,0x42,0x7f,0x7b]
+          vprorq $123, 2032(%rdx), %xmm28
+
+// CHECK: vprorq $123, 2048(%rdx), %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x00,0x72,0x82,0x00,0x08,0x00,0x00,0x7b]
+          vprorq $123, 2048(%rdx), %xmm28
+
+// CHECK: vprorq $123, -2048(%rdx), %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x00,0x72,0x42,0x80,0x7b]
+          vprorq $123, -2048(%rdx), %xmm28
+
+// CHECK: vprorq $123, -2064(%rdx), %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x00,0x72,0x82,0xf0,0xf7,0xff,0xff,0x7b]
+          vprorq $123, -2064(%rdx), %xmm28
+
+// CHECK: vprorq $123, 1016(%rdx){1to2}, %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x10,0x72,0x42,0x7f,0x7b]
+          vprorq $123, 1016(%rdx){1to2}, %xmm28
+
+// CHECK: vprorq $123, 1024(%rdx){1to2}, %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x10,0x72,0x82,0x00,0x04,0x00,0x00,0x7b]
+          vprorq $123, 1024(%rdx){1to2}, %xmm28
+
+// CHECK: vprorq $123, -1024(%rdx){1to2}, %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x10,0x72,0x42,0x80,0x7b]
+          vprorq $123, -1024(%rdx){1to2}, %xmm28
+
+// CHECK: vprorq $123, -1032(%rdx){1to2}, %xmm28
+// CHECK:  encoding: [0x62,0xf1,0x9d,0x10,0x72,0x82,0xf8,0xfb,0xff,0xff,0x7b]
+          vprorq $123, -1032(%rdx){1to2}, %xmm28
+
+// CHECK: vprorq $171, %ymm17, %ymm21
+// CHECK:  encoding: [0x62,0xb1,0xd5,0x20,0x72,0xc1,0xab]
+          vprorq $171, %ymm17, %ymm21
+
+// CHECK: vprorq $171, %ymm17, %ymm21 {%k1}
+// CHECK:  encoding: [0x62,0xb1,0xd5,0x21,0x72,0xc1,0xab]
+          vprorq $171, %ymm17, %ymm21 {%k1}
+
+// CHECK: vprorq $171, %ymm17, %ymm21 {%k1} {z}
+// CHECK:  encoding: [0x62,0xb1,0xd5,0xa1,0x72,0xc1,0xab]
+          vprorq $171, %ymm17, %ymm21 {%k1} {z}
+
+// CHECK: vprorq $123, %ymm17, %ymm21
+// CHECK:  encoding: [0x62,0xb1,0xd5,0x20,0x72,0xc1,0x7b]
+          vprorq $123, %ymm17, %ymm21
+
+// CHECK: vprorq $123, (%rcx), %ymm21
+// CHECK:  encoding: [0x62,0xf1,0xd5,0x20,0x72,0x01,0x7b]
+          vprorq $123, (%rcx), %ymm21
+
+// CHECK: vprorq $123, 291(%rax,%r14,8), %ymm21
+// CHECK:  encoding: [0x62,0xb1,0xd5,0x20,0x72,0x84,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vprorq $123, 291(%rax,%r14,8), %ymm21
+
+// CHECK: vprorq $123, (%rcx){1to4}, %ymm21
+// CHECK:  encoding: [0x62,0xf1,0xd5,0x30,0x72,0x01,0x7b]
+          vprorq $123, (%rcx){1to4}, %ymm21
+
+// CHECK: vprorq $123, 4064(%rdx), %ymm21
+// CHECK:  encoding: [0x62,0xf1,0xd5,0x20,0x72,0x42,0x7f,0x7b]
+          vprorq $123, 4064(%rdx), %ymm21
+
+// CHECK: vprorq $123, 4096(%rdx), %ymm21
+// CHECK:  encoding: [0x62,0xf1,0xd5,0x20,0x72,0x82,0x00,0x10,0x00,0x00,0x7b]
+          vprorq $123, 4096(%rdx), %ymm21
+
+// CHECK: vprorq $123, -4096(%rdx), %ymm21
+// CHECK:  encoding: [0x62,0xf1,0xd5,0x20,0x72,0x42,0x80,0x7b]
+          vprorq $123, -4096(%rdx), %ymm21
+
+// CHECK: vprorq $123, -4128(%rdx), %ymm21
+// CHECK:  encoding: [0x62,0xf1,0xd5,0x20,0x72,0x82,0xe0,0xef,0xff,0xff,0x7b]
+          vprorq $123, -4128(%rdx), %ymm21
+
+// CHECK: vprorq $123, 1016(%rdx){1to4}, %ymm21
+// CHECK:  encoding: [0x62,0xf1,0xd5,0x30,0x72,0x42,0x7f,0x7b]
+          vprorq $123, 1016(%rdx){1to4}, %ymm21
+
+// CHECK: vprorq $123, 1024(%rdx){1to4}, %ymm21
+// CHECK:  encoding: [0x62,0xf1,0xd5,0x30,0x72,0x82,0x00,0x04,0x00,0x00,0x7b]
+          vprorq $123, 1024(%rdx){1to4}, %ymm21
+
+// CHECK: vprorq $123, -1024(%rdx){1to4}, %ymm21
+// CHECK:  encoding: [0x62,0xf1,0xd5,0x30,0x72,0x42,0x80,0x7b]
+          vprorq $123, -1024(%rdx){1to4}, %ymm21
+
+// CHECK: vprorq $123, -1032(%rdx){1to4}, %ymm21
+// CHECK:  encoding: [0x62,0xf1,0xd5,0x30,0x72,0x82,0xf8,0xfb,0xff,0xff,0x7b]
+          vprorq $123, -1032(%rdx){1to4}, %ymm21
+
+// CHECK: vpmuludq %xmm18, %xmm22, %xmm27
+// CHECK:  encoding: [0x62,0x21,0xcd,0x00,0xf4,0xda]
+          vpmuludq %xmm18, %xmm22, %xmm27
+
+// CHECK: vpmuludq %xmm18, %xmm22, %xmm27 {%k5}
+// CHECK:  encoding: [0x62,0x21,0xcd,0x05,0xf4,0xda]
+          vpmuludq %xmm18, %xmm22, %xmm27 {%k5}
+
+// CHECK: vpmuludq %xmm18, %xmm22, %xmm27 {%k5} {z}
+// CHECK:  encoding: [0x62,0x21,0xcd,0x85,0xf4,0xda]
+          vpmuludq %xmm18, %xmm22, %xmm27 {%k5} {z}
+
+// CHECK: vpmuludq (%rcx), %xmm22, %xmm27
+// CHECK:  encoding: [0x62,0x61,0xcd,0x00,0xf4,0x19]
+          vpmuludq (%rcx), %xmm22, %xmm27
+
+// CHECK: vpmuludq 291(%rax,%r14,8), %xmm22, %xmm27
+// CHECK:  encoding: [0x62,0x21,0xcd,0x00,0xf4,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpmuludq 291(%rax,%r14,8), %xmm22, %xmm27
+
+// CHECK: vpmuludq (%rcx){1to2}, %xmm22, %xmm27
+// CHECK:  encoding: [0x62,0x61,0xcd,0x10,0xf4,0x19]
+          vpmuludq (%rcx){1to2}, %xmm22, %xmm27
+
+// CHECK: vpmuludq 2032(%rdx), %xmm22, %xmm27
+// CHECK:  encoding: [0x62,0x61,0xcd,0x00,0xf4,0x5a,0x7f]
+          vpmuludq 2032(%rdx), %xmm22, %xmm27
+
+// CHECK: vpmuludq 2048(%rdx), %xmm22, %xmm27
+// CHECK:  encoding: [0x62,0x61,0xcd,0x00,0xf4,0x9a,0x00,0x08,0x00,0x00]
+          vpmuludq 2048(%rdx), %xmm22, %xmm27
+
+// CHECK: vpmuludq -2048(%rdx), %xmm22, %xmm27
+// CHECK:  encoding: [0x62,0x61,0xcd,0x00,0xf4,0x5a,0x80]
+          vpmuludq -2048(%rdx), %xmm22, %xmm27
+
+// CHECK: vpmuludq -2064(%rdx), %xmm22, %xmm27
+// CHECK:  encoding: [0x62,0x61,0xcd,0x00,0xf4,0x9a,0xf0,0xf7,0xff,0xff]
+          vpmuludq -2064(%rdx), %xmm22, %xmm27
+
+// CHECK: vpmuludq 1016(%rdx){1to2}, %xmm22, %xmm27
+// CHECK:  encoding: [0x62,0x61,0xcd,0x10,0xf4,0x5a,0x7f]
+          vpmuludq 1016(%rdx){1to2}, %xmm22, %xmm27
+
+// CHECK: vpmuludq 1024(%rdx){1to2}, %xmm22, %xmm27
+// CHECK:  encoding: [0x62,0x61,0xcd,0x10,0xf4,0x9a,0x00,0x04,0x00,0x00]
+          vpmuludq 1024(%rdx){1to2}, %xmm22, %xmm27
+
+// CHECK: vpmuludq -1024(%rdx){1to2}, %xmm22, %xmm27
+// CHECK:  encoding: [0x62,0x61,0xcd,0x10,0xf4,0x5a,0x80]
+          vpmuludq -1024(%rdx){1to2}, %xmm22, %xmm27
+
+// CHECK: vpmuludq -1032(%rdx){1to2}, %xmm22, %xmm27
+// CHECK:  encoding: [0x62,0x61,0xcd,0x10,0xf4,0x9a,0xf8,0xfb,0xff,0xff]
+          vpmuludq -1032(%rdx){1to2}, %xmm22, %xmm27
+
+// CHECK: vpmuludq %ymm18, %ymm27, %ymm30
+// CHECK:  encoding: [0x62,0x21,0xa5,0x20,0xf4,0xf2]
+          vpmuludq %ymm18, %ymm27, %ymm30
+
+// CHECK: vpmuludq %ymm18, %ymm27, %ymm30 {%k7}
+// CHECK:  encoding: [0x62,0x21,0xa5,0x27,0xf4,0xf2]
+          vpmuludq %ymm18, %ymm27, %ymm30 {%k7}
+
+// CHECK: vpmuludq %ymm18, %ymm27, %ymm30 {%k7} {z}
+// CHECK:  encoding: [0x62,0x21,0xa5,0xa7,0xf4,0xf2]
+          vpmuludq %ymm18, %ymm27, %ymm30 {%k7} {z}
+
+// CHECK: vpmuludq (%rcx), %ymm27, %ymm30
+// CHECK:  encoding: [0x62,0x61,0xa5,0x20,0xf4,0x31]
+          vpmuludq (%rcx), %ymm27, %ymm30
+
+// CHECK: vpmuludq 291(%rax,%r14,8), %ymm27, %ymm30
+// CHECK:  encoding: [0x62,0x21,0xa5,0x20,0xf4,0xb4,0xf0,0x23,0x01,0x00,0x00]
+          vpmuludq 291(%rax,%r14,8), %ymm27, %ymm30
+
+// CHECK: vpmuludq (%rcx){1to4}, %ymm27, %ymm30
+// CHECK:  encoding: [0x62,0x61,0xa5,0x30,0xf4,0x31]
+          vpmuludq (%rcx){1to4}, %ymm27, %ymm30
+
+// CHECK: vpmuludq 4064(%rdx), %ymm27, %ymm30
+// CHECK:  encoding: [0x62,0x61,0xa5,0x20,0xf4,0x72,0x7f]
+          vpmuludq 4064(%rdx), %ymm27, %ymm30
+
+// CHECK: vpmuludq 4096(%rdx), %ymm27, %ymm30
+// CHECK:  encoding: [0x62,0x61,0xa5,0x20,0xf4,0xb2,0x00,0x10,0x00,0x00]
+          vpmuludq 4096(%rdx), %ymm27, %ymm30
+
+// CHECK: vpmuludq -4096(%rdx), %ymm27, %ymm30
+// CHECK:  encoding: [0x62,0x61,0xa5,0x20,0xf4,0x72,0x80]
+          vpmuludq -4096(%rdx), %ymm27, %ymm30
+
+// CHECK: vpmuludq -4128(%rdx), %ymm27, %ymm30
+// CHECK:  encoding: [0x62,0x61,0xa5,0x20,0xf4,0xb2,0xe0,0xef,0xff,0xff]
+          vpmuludq -4128(%rdx), %ymm27, %ymm30
+
+// CHECK: vpmuludq 1016(%rdx){1to4}, %ymm27, %ymm30
+// CHECK:  encoding: [0x62,0x61,0xa5,0x30,0xf4,0x72,0x7f]
+          vpmuludq 1016(%rdx){1to4}, %ymm27, %ymm30
+
+// CHECK: vpmuludq 1024(%rdx){1to4}, %ymm27, %ymm30
+// CHECK:  encoding: [0x62,0x61,0xa5,0x30,0xf4,0xb2,0x00,0x04,0x00,0x00]
+          vpmuludq 1024(%rdx){1to4}, %ymm27, %ymm30
+
+// CHECK: vpmuludq -1024(%rdx){1to4}, %ymm27, %ymm30
+// CHECK:  encoding: [0x62,0x61,0xa5,0x30,0xf4,0x72,0x80]
+          vpmuludq -1024(%rdx){1to4}, %ymm27, %ymm30
+
+// CHECK: vpmuludq -1032(%rdx){1to4}, %ymm27, %ymm30
+// CHECK:  encoding: [0x62,0x61,0xa5,0x30,0xf4,0xb2,0xf8,0xfb,0xff,0xff]
+          vpmuludq -1032(%rdx){1to4}, %ymm27, %ymm30
+          
+// CHECK: vpmuldq %xmm26, %xmm24, %xmm25
+// CHECK:  encoding: [0x62,0x02,0xbd,0x00,0x28,0xca]
+          vpmuldq %xmm26, %xmm24, %xmm25
+
+// CHECK: vpmuldq %xmm26, %xmm24, %xmm25 {%k3}
+// CHECK:  encoding: [0x62,0x02,0xbd,0x03,0x28,0xca]
+          vpmuldq %xmm26, %xmm24, %xmm25 {%k3}
+
+// CHECK: vpmuldq %xmm26, %xmm24, %xmm25 {%k3} {z}
+// CHECK:  encoding: [0x62,0x02,0xbd,0x83,0x28,0xca]
+          vpmuldq %xmm26, %xmm24, %xmm25 {%k3} {z}
+
+// CHECK: vpmuldq (%rcx), %xmm24, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xbd,0x00,0x28,0x09]
+          vpmuldq (%rcx), %xmm24, %xmm25
+
+// CHECK: vpmuldq 291(%rax,%r14,8), %xmm24, %xmm25
+// CHECK:  encoding: [0x62,0x22,0xbd,0x00,0x28,0x8c,0xf0,0x23,0x01,0x00,0x00]
+          vpmuldq 291(%rax,%r14,8), %xmm24, %xmm25
+
+// CHECK: vpmuldq (%rcx){1to2}, %xmm24, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xbd,0x10,0x28,0x09]
+          vpmuldq (%rcx){1to2}, %xmm24, %xmm25
+
+// CHECK: vpmuldq 2032(%rdx), %xmm24, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xbd,0x00,0x28,0x4a,0x7f]
+          vpmuldq 2032(%rdx), %xmm24, %xmm25
+
+// CHECK: vpmuldq 2048(%rdx), %xmm24, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xbd,0x00,0x28,0x8a,0x00,0x08,0x00,0x00]
+          vpmuldq 2048(%rdx), %xmm24, %xmm25
+
+// CHECK: vpmuldq -2048(%rdx), %xmm24, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xbd,0x00,0x28,0x4a,0x80]
+          vpmuldq -2048(%rdx), %xmm24, %xmm25
+
+// CHECK: vpmuldq -2064(%rdx), %xmm24, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xbd,0x00,0x28,0x8a,0xf0,0xf7,0xff,0xff]
+          vpmuldq -2064(%rdx), %xmm24, %xmm25
+
+// CHECK: vpmuldq 1016(%rdx){1to2}, %xmm24, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xbd,0x10,0x28,0x4a,0x7f]
+          vpmuldq 1016(%rdx){1to2}, %xmm24, %xmm25
+
+// CHECK: vpmuldq 1024(%rdx){1to2}, %xmm24, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xbd,0x10,0x28,0x8a,0x00,0x04,0x00,0x00]
+          vpmuldq 1024(%rdx){1to2}, %xmm24, %xmm25
+
+// CHECK: vpmuldq -1024(%rdx){1to2}, %xmm24, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xbd,0x10,0x28,0x4a,0x80]
+          vpmuldq -1024(%rdx){1to2}, %xmm24, %xmm25
+
+// CHECK: vpmuldq -1032(%rdx){1to2}, %xmm24, %xmm25
+// CHECK:  encoding: [0x62,0x62,0xbd,0x10,0x28,0x8a,0xf8,0xfb,0xff,0xff]
+          vpmuldq -1032(%rdx){1to2}, %xmm24, %xmm25
+
+// CHECK: vpmuldq %ymm26, %ymm18, %ymm19
+// CHECK:  encoding: [0x62,0x82,0xed,0x20,0x28,0xda]
+          vpmuldq %ymm26, %ymm18, %ymm19
+
+// CHECK: vpmuldq %ymm26, %ymm18, %ymm19 {%k6}
+// CHECK:  encoding: [0x62,0x82,0xed,0x26,0x28,0xda]
+          vpmuldq %ymm26, %ymm18, %ymm19 {%k6}
+
+// CHECK: vpmuldq %ymm26, %ymm18, %ymm19 {%k6} {z}
+// CHECK:  encoding: [0x62,0x82,0xed,0xa6,0x28,0xda]
+          vpmuldq %ymm26, %ymm18, %ymm19 {%k6} {z}
+
+// CHECK: vpmuldq (%rcx), %ymm18, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0xed,0x20,0x28,0x19]
+          vpmuldq (%rcx), %ymm18, %ymm19
+
+// CHECK: vpmuldq 291(%rax,%r14,8), %ymm18, %ymm19
+// CHECK:  encoding: [0x62,0xa2,0xed,0x20,0x28,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vpmuldq 291(%rax,%r14,8), %ymm18, %ymm19
+
+// CHECK: vpmuldq (%rcx){1to4}, %ymm18, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0xed,0x30,0x28,0x19]
+          vpmuldq (%rcx){1to4}, %ymm18, %ymm19
+
+// CHECK: vpmuldq 4064(%rdx), %ymm18, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0xed,0x20,0x28,0x5a,0x7f]
+          vpmuldq 4064(%rdx), %ymm18, %ymm19
+
+// CHECK: vpmuldq 4096(%rdx), %ymm18, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0xed,0x20,0x28,0x9a,0x00,0x10,0x00,0x00]
+          vpmuldq 4096(%rdx), %ymm18, %ymm19
+
+// CHECK: vpmuldq -4096(%rdx), %ymm18, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0xed,0x20,0x28,0x5a,0x80]
+          vpmuldq -4096(%rdx), %ymm18, %ymm19
+
+// CHECK: vpmuldq -4128(%rdx), %ymm18, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0xed,0x20,0x28,0x9a,0xe0,0xef,0xff,0xff]
+          vpmuldq -4128(%rdx), %ymm18, %ymm19
+
+// CHECK: vpmuldq 1016(%rdx){1to4}, %ymm18, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0xed,0x30,0x28,0x5a,0x7f]
+          vpmuldq 1016(%rdx){1to4}, %ymm18, %ymm19
+
+// CHECK: vpmuldq 1024(%rdx){1to4}, %ymm18, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0xed,0x30,0x28,0x9a,0x00,0x04,0x00,0x00]
+          vpmuldq 1024(%rdx){1to4}, %ymm18, %ymm19
+
+// CHECK: vpmuldq -1024(%rdx){1to4}, %ymm18, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0xed,0x30,0x28,0x5a,0x80]
+          vpmuldq -1024(%rdx){1to4}, %ymm18, %ymm19
+
+// CHECK: vpmuldq -1032(%rdx){1to4}, %ymm18, %ymm19
+// CHECK:  encoding: [0x62,0xe2,0xed,0x30,0x28,0x9a,0xf8,0xfb,0xff,0xff]
+          vpmuldq -1032(%rdx){1to4}, %ymm18, %ymm19
+
+// CHECK: vcmppd $171, %xmm23, %xmm27, %k3
+// CHECK:  encoding: [0x62,0xb1,0xa5,0x00,0xc2,0xdf,0xab]
+          vcmppd $0xab, %xmm23, %xmm27, %k3
+
+// CHECK: vcmppd $171, %xmm23, %xmm27, %k3 {%k5}
+// CHECK:  encoding: [0x62,0xb1,0xa5,0x05,0xc2,0xdf,0xab]
+          vcmppd $0xab, %xmm23, %xmm27, %k3 {%k5}
+
+// CHECK: vcmppd $123, %xmm23, %xmm27, %k3
+// CHECK:  encoding: [0x62,0xb1,0xa5,0x00,0xc2,0xdf,0x7b]
+          vcmppd $0x7b, %xmm23, %xmm27, %k3
+
+// CHECK: vcmppd $123, (%rcx), %xmm27, %k3
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x00,0xc2,0x19,0x7b]
+          vcmppd $0x7b, (%rcx), %xmm27, %k3
+
+// CHECK: vcmppd $123, 291(%rax,%r14,8), %xmm27, %k3
+// CHECK:  encoding: [0x62,0xb1,0xa5,0x00,0xc2,0x9c,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vcmppd $0x7b, 291(%rax,%r14,8), %xmm27, %k3
+
+// CHECK: vcmppd $123, (%rcx){1to2}, %xmm27, %k3
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x10,0xc2,0x19,0x7b]
+          vcmppd $0x7b, (%rcx){1to2}, %xmm27, %k3
+
+// CHECK: vcmppd $123, 2032(%rdx), %xmm27, %k3
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x00,0xc2,0x5a,0x7f,0x7b]
+          vcmppd $0x7b, 2032(%rdx), %xmm27, %k3
+
+// CHECK: vcmppd $123, 2048(%rdx), %xmm27, %k3
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x00,0xc2,0x9a,0x00,0x08,0x00,0x00,0x7b]
+          vcmppd $0x7b, 2048(%rdx), %xmm27, %k3
+
+// CHECK: vcmppd $123, -2048(%rdx), %xmm27, %k3
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x00,0xc2,0x5a,0x80,0x7b]
+          vcmppd $0x7b, -2048(%rdx), %xmm27, %k3
+
+// CHECK: vcmppd $123, -2064(%rdx), %xmm27, %k3
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x00,0xc2,0x9a,0xf0,0xf7,0xff,0xff,0x7b]
+          vcmppd $0x7b, -2064(%rdx), %xmm27, %k3
+
+// CHECK: vcmppd $123, 1016(%rdx){1to2}, %xmm27, %k3
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x10,0xc2,0x5a,0x7f,0x7b]
+          vcmppd $0x7b, 1016(%rdx){1to2}, %xmm27, %k3
+
+// CHECK: vcmppd $123, 1024(%rdx){1to2}, %xmm27, %k3
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x10,0xc2,0x9a,0x00,0x04,0x00,0x00,0x7b]
+          vcmppd $0x7b, 1024(%rdx){1to2}, %xmm27, %k3
+
+// CHECK: vcmppd $123, -1024(%rdx){1to2}, %xmm27, %k3
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x10,0xc2,0x5a,0x80,0x7b]
+          vcmppd $0x7b, -1024(%rdx){1to2}, %xmm27, %k3
+
+// CHECK: vcmppd $123, -1032(%rdx){1to2}, %xmm27, %k3
+// CHECK:  encoding: [0x62,0xf1,0xa5,0x10,0xc2,0x9a,0xf8,0xfb,0xff,0xff,0x7b]
+          vcmppd $0x7b, -1032(%rdx){1to2}, %xmm27, %k3
+
+// CHECK: vcmppd $171, %ymm27, %ymm17, %k4
+// CHECK:  encoding: [0x62,0x91,0xf5,0x20,0xc2,0xe3,0xab]
+          vcmppd $0xab, %ymm27, %ymm17, %k4
+
+// CHECK: vcmppd $171, %ymm27, %ymm17, %k4 {%k7}
+// CHECK:  encoding: [0x62,0x91,0xf5,0x27,0xc2,0xe3,0xab]
+          vcmppd $0xab, %ymm27, %ymm17, %k4 {%k7}
+
+// CHECK: vcmppd $123, %ymm27, %ymm17, %k4
+// CHECK:  encoding: [0x62,0x91,0xf5,0x20,0xc2,0xe3,0x7b]
+          vcmppd $0x7b, %ymm27, %ymm17, %k4
+
+// CHECK: vcmppd $123, (%rcx), %ymm17, %k4
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x20,0xc2,0x21,0x7b]
+          vcmppd $0x7b, (%rcx), %ymm17, %k4
+
+// CHECK: vcmppd $123, 291(%rax,%r14,8), %ymm17, %k4
+// CHECK:  encoding: [0x62,0xb1,0xf5,0x20,0xc2,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vcmppd $0x7b, 291(%rax,%r14,8), %ymm17, %k4
+
+// CHECK: vcmppd $123, (%rcx){1to4}, %ymm17, %k4
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x30,0xc2,0x21,0x7b]
+          vcmppd $0x7b, (%rcx){1to4}, %ymm17, %k4
+
+// CHECK: vcmppd $123, 4064(%rdx), %ymm17, %k4
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x20,0xc2,0x62,0x7f,0x7b]
+          vcmppd $123, 4064(%rdx), %ymm17, %k4
+
+// CHECK: vcmppd $123, 4096(%rdx), %ymm17, %k4
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x20,0xc2,0xa2,0x00,0x10,0x00,0x00,0x7b]
+          vcmppd $0x7b, 4096(%rdx), %ymm17, %k4
+
+// CHECK: vcmppd $123, -4096(%rdx), %ymm17, %k4
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x20,0xc2,0x62,0x80,0x7b]
+          vcmppd $0x7b, -4096(%rdx), %ymm17, %k4
+
+// CHECK: vcmppd $123, -4128(%rdx), %ymm17, %k4
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x20,0xc2,0xa2,0xe0,0xef,0xff,0xff,0x7b]
+          vcmppd $0x7b, -4128(%rdx), %ymm17, %k4
+
+// CHECK: vcmppd $123, 1016(%rdx){1to4}, %ymm17, %k4
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x30,0xc2,0x62,0x7f,0x7b]
+          vcmppd $0x7b, 1016(%rdx){1to4}, %ymm17, %k4
+
+// CHECK: vcmppd $123, 1024(%rdx){1to4}, %ymm17, %k4
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x30,0xc2,0xa2,0x00,0x04,0x00,0x00,0x7b]
+          vcmppd $0x7b, 1024(%rdx){1to4}, %ymm17, %k4
+
+// CHECK: vcmppd $123, -1024(%rdx){1to4}, %ymm17, %k4
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x30,0xc2,0x62,0x80,0x7b]
+          vcmppd $0x7b, -1024(%rdx){1to4}, %ymm17, %k4
+
+// CHECK: vcmppd $123, -1032(%rdx){1to4}, %ymm17, %k4
+// CHECK:  encoding: [0x62,0xf1,0xf5,0x30,0xc2,0xa2,0xf8,0xfb,0xff,0xff,0x7b]
+          vcmppd $0x7b, -1032(%rdx){1to4}, %ymm17, %k4
+
+// CHECK: vcmpps $171, %xmm28, %xmm29, %k4
+// CHECK:  encoding: [0x62,0x91,0x14,0x00,0xc2,0xe4,0xab]
+          vcmpps $0xab, %xmm28, %xmm29, %k4
+
+// CHECK: vcmpps $171, %xmm28, %xmm29, %k4 {%k2}
+// CHECK:  encoding: [0x62,0x91,0x14,0x02,0xc2,0xe4,0xab]
+          vcmpps $0xab, %xmm28, %xmm29, %k4 {%k2}
+
+// CHECK: vcmpps $123, %xmm28, %xmm29, %k4
+// CHECK:  encoding: [0x62,0x91,0x14,0x00,0xc2,0xe4,0x7b]
+          vcmpps $0x7b, %xmm28, %xmm29, %k4
+
+// CHECK: vcmpps $123, (%rcx), %xmm29, %k4
+// CHECK:  encoding: [0x62,0xf1,0x14,0x00,0xc2,0x21,0x7b]
+          vcmpps $0x7b, (%rcx), %xmm29, %k4
+
+// CHECK: vcmpps $123, 291(%rax,%r14,8), %xmm29, %k4
+// CHECK:  encoding: [0x62,0xb1,0x14,0x00,0xc2,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vcmpps $0x7b, 291(%rax,%r14,8), %xmm29, %k4
+
+// CHECK: vcmpps $123, (%rcx){1to4}, %xmm29, %k4
+// CHECK:  encoding: [0x62,0xf1,0x14,0x10,0xc2,0x21,0x7b]
+          vcmpps $0x7b, (%rcx){1to4}, %xmm29, %k4
+
+// CHECK: vcmpps $123, 2032(%rdx), %xmm29, %k4
+// CHECK:  encoding: [0x62,0xf1,0x14,0x00,0xc2,0x62,0x7f,0x7b]
+          vcmpps $0x7b, 2032(%rdx), %xmm29, %k4
+
+// CHECK: vcmpps $123, 2048(%rdx), %xmm29, %k4
+// CHECK:  encoding: [0x62,0xf1,0x14,0x00,0xc2,0xa2,0x00,0x08,0x00,0x00,0x7b]
+          vcmpps $0x7b, 2048(%rdx), %xmm29, %k4
+
+// CHECK: vcmpps $123, -2048(%rdx), %xmm29, %k4
+// CHECK:  encoding: [0x62,0xf1,0x14,0x00,0xc2,0x62,0x80,0x7b]
+          vcmpps $0x7b, -2048(%rdx), %xmm29, %k4
+
+// CHECK: vcmpps $123, -2064(%rdx), %xmm29, %k4
+// CHECK:  encoding: [0x62,0xf1,0x14,0x00,0xc2,0xa2,0xf0,0xf7,0xff,0xff,0x7b]
+          vcmpps $0x7b, -2064(%rdx), %xmm29, %k4
+
+// CHECK: vcmpps $123, 508(%rdx){1to4}, %xmm29, %k4
+// CHECK:  encoding: [0x62,0xf1,0x14,0x10,0xc2,0x62,0x7f,0x7b]
+          vcmpps $123, 508(%rdx){1to4}, %xmm29, %k4
+
+// CHECK: vcmpps $123, 512(%rdx){1to4}, %xmm29, %k4
+// CHECK:  encoding: [0x62,0xf1,0x14,0x10,0xc2,0xa2,0x00,0x02,0x00,0x00,0x7b]
+          vcmpps $123, 512(%rdx){1to4}, %xmm29, %k4
+
+// CHECK: vcmpps $123, -512(%rdx){1to4}, %xmm29, %k4
+// CHECK:  encoding: [0x62,0xf1,0x14,0x10,0xc2,0x62,0x80,0x7b]
+          vcmpps $0x7b, -512(%rdx){1to4}, %xmm29, %k4
+
+// CHECK: vcmpps $123, -516(%rdx){1to4}, %xmm29, %k4
+// CHECK:  encoding: [0x62,0xf1,0x14,0x10,0xc2,0xa2,0xfc,0xfd,0xff,0xff,0x7b]
+          vcmpps $0x7b, -516(%rdx){1to4}, %xmm29, %k4
+
+// CHECK: vcmpps $171, %ymm18, %ymm19, %k4
+// CHECK:  encoding: [0x62,0xb1,0x64,0x20,0xc2,0xe2,0xab]
+          vcmpps $0xab, %ymm18, %ymm19, %k4
+
+// CHECK: vcmpps $171, %ymm18, %ymm19, %k4 {%k1}
+// CHECK:  encoding: [0x62,0xb1,0x64,0x21,0xc2,0xe2,0xab]
+          vcmpps $0xab, %ymm18, %ymm19, %k4 {%k1}
+
+// CHECK: vcmpps $123, %ymm18, %ymm19, %k4
+// CHECK:  encoding: [0x62,0xb1,0x64,0x20,0xc2,0xe2,0x7b]
+          vcmpps $0x7b, %ymm18, %ymm19, %k4
+
+// CHECK: vcmpps $123, (%rcx), %ymm19, %k4
+// CHECK:  encoding: [0x62,0xf1,0x64,0x20,0xc2,0x21,0x7b]
+          vcmpps $0x7b, (%rcx), %ymm19, %k4
+
+// CHECK: vcmpps $123, 291(%rax,%r14,8), %ymm19, %k4
+// CHECK:  encoding: [0x62,0xb1,0x64,0x20,0xc2,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vcmpps $0x7b, 291(%rax,%r14,8), %ymm19, %k4
+
+// CHECK: vcmpps $123, (%rcx){1to8}, %ymm19, %k4
+// CHECK:  encoding: [0x62,0xf1,0x64,0x30,0xc2,0x21,0x7b]
+          vcmpps $0x7b, (%rcx){1to8}, %ymm19, %k4
+
+// CHECK: vcmpps $123, 4064(%rdx), %ymm19, %k4
+// CHECK:  encoding: [0x62,0xf1,0x64,0x20,0xc2,0x62,0x7f,0x7b]
+          vcmpps $0x7b, 4064(%rdx), %ymm19, %k4
+
+// CHECK: vcmpps $123, 4096(%rdx), %ymm19, %k4
+// CHECK:  encoding: [0x62,0xf1,0x64,0x20,0xc2,0xa2,0x00,0x10,0x00,0x00,0x7b]
+          vcmpps $0x7b, 4096(%rdx), %ymm19, %k4
+
+// CHECK: vcmpps $123, -4096(%rdx), %ymm19, %k4
+// CHECK:  encoding: [0x62,0xf1,0x64,0x20,0xc2,0x62,0x80,0x7b]
+          vcmpps $0x7b, -4096(%rdx), %ymm19, %k4
+
+// CHECK: vcmpps $123, -4128(%rdx), %ymm19, %k4
+// CHECK:  encoding: [0x62,0xf1,0x64,0x20,0xc2,0xa2,0xe0,0xef,0xff,0xff,0x7b]
+          vcmpps $0x7b, -4128(%rdx), %ymm19, %k4
+
+// CHECK: vcmpps $123, 508(%rdx){1to8}, %ymm19, %k4
+// CHECK:  encoding: [0x62,0xf1,0x64,0x30,0xc2,0x62,0x7f,0x7b]
+          vcmpps $0x7b, 508(%rdx){1to8}, %ymm19, %k4
+
+// CHECK: vcmpps $123, 512(%rdx){1to8}, %ymm19, %k4
+// CHECK:  encoding: [0x62,0xf1,0x64,0x30,0xc2,0xa2,0x00,0x02,0x00,0x00,0x7b]
+          vcmpps $0x7b, 512(%rdx){1to8}, %ymm19, %k4
+
+// CHECK: vcmpps $123, -512(%rdx){1to8}, %ymm19, %k4
+// CHECK:  encoding: [0x62,0xf1,0x64,0x30,0xc2,0x62,0x80,0x7b]
+          vcmpps $0x7b, -512(%rdx){1to8}, %ymm19, %k4
+
+// CHECK: vcmpps $123, -516(%rdx){1to8}, %ymm19, %k4
+// CHECK:  encoding: [0x62,0xf1,0x64,0x30,0xc2,0xa2,0xfc,0xfd,0xff,0xff,0x7b]
+          vcmpps $0x7b, -516(%rdx){1to8}, %ymm19, %k4
+
+// CHECK: vbroadcastf32x4 (%rcx), %ymm28
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x1a,0x21]
+          vbroadcastf32x4 (%rcx), %ymm28
+
+// CHECK: vbroadcastf32x4 (%rcx), %ymm28 {%k4}
+// CHECK:  encoding: [0x62,0x62,0x7d,0x2c,0x1a,0x21]
+          vbroadcastf32x4 (%rcx), %ymm28 {%k4}
+
+// CHECK: vbroadcastf32x4 (%rcx), %ymm28 {%k4} {z}
+// CHECK:  encoding: [0x62,0x62,0x7d,0xac,0x1a,0x21]
+          vbroadcastf32x4 (%rcx), %ymm28 {%k4} {z}
+
+// CHECK: vbroadcastf32x4 291(%rax,%r14,8), %ymm28
+// CHECK:  encoding: [0x62,0x22,0x7d,0x28,0x1a,0xa4,0xf0,0x23,0x01,0x00,0x00]
+          vbroadcastf32x4 291(%rax,%r14,8), %ymm28
+
+// CHECK: vbroadcastf32x4 2032(%rdx), %ymm28
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x1a,0x62,0x7f]
+          vbroadcastf32x4 2032(%rdx), %ymm28
+
+// CHECK: vbroadcastf32x4 2048(%rdx), %ymm28
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x1a,0xa2,0x00,0x08,0x00,0x00]
+          vbroadcastf32x4 2048(%rdx), %ymm28
+
+// CHECK: vbroadcastf32x4 -2048(%rdx), %ymm28
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x1a,0x62,0x80]
+          vbroadcastf32x4 -2048(%rdx), %ymm28
+
+// CHECK: vbroadcastf32x4 -2064(%rdx), %ymm28
+// CHECK:  encoding: [0x62,0x62,0x7d,0x28,0x1a,0xa2,0xf0,0xf7,0xff,0xff]
+          vbroadcastf32x4 -2064(%rdx), %ymm28
+
+// CHECK: vbroadcasti32x4 (%rcx), %ymm19
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x5a,0x19]
+          vbroadcasti32x4 (%rcx), %ymm19
+
+// CHECK: vbroadcasti32x4 (%rcx), %ymm19 {%k5}
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x2d,0x5a,0x19]
+          vbroadcasti32x4 (%rcx), %ymm19 {%k5}
+
+// CHECK: vbroadcasti32x4 (%rcx), %ymm19 {%k5} {z}
+// CHECK:  encoding: [0x62,0xe2,0x7d,0xad,0x5a,0x19]
+          vbroadcasti32x4 (%rcx), %ymm19 {%k5} {z}
+
+// CHECK: vbroadcasti32x4 291(%rax,%r14,8), %ymm19
+// CHECK:  encoding: [0x62,0xa2,0x7d,0x28,0x5a,0x9c,0xf0,0x23,0x01,0x00,0x00]
+          vbroadcasti32x4 291(%rax,%r14,8), %ymm19
+
+// CHECK: vbroadcasti32x4 2032(%rdx), %ymm19
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x5a,0x5a,0x7f]
+          vbroadcasti32x4 2032(%rdx), %ymm19
+
+// CHECK: vbroadcasti32x4 2048(%rdx), %ymm19
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x5a,0x9a,0x00,0x08,0x00,0x00]
+          vbroadcasti32x4 2048(%rdx), %ymm19
+
+// CHECK: vbroadcasti32x4 -2048(%rdx), %ymm19
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x5a,0x5a,0x80]
+          vbroadcasti32x4 -2048(%rdx), %ymm19
+
+// CHECK: vbroadcasti32x4 -2064(%rdx), %ymm19
+// CHECK:  encoding: [0x62,0xe2,0x7d,0x28,0x5a,0x9a,0xf0,0xf7,0xff,0xff]
+          vbroadcasti32x4 -2064(%rdx), %ymm19
+
+
+
+
+
+
+
+
+
+
diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s
index 10d420aa447b..096e90039abd 100644
--- a/test/MC/X86/x86-64.s
+++ b/test/MC/X86/x86-64.s
@@ -613,7 +613,7 @@ movq _foo@GOTPCREL(%rip), %r14
 movq 0x00(%r13,%rax,8),%r13
 
 // CHECK: testq	%rax, %rbx
-// CHECK:  encoding: [0x48,0x85,0xd8]
+// CHECK:  encoding: [0x48,0x85,0xc3]
 testq %rax, %rbx
 
 // CHECK: cmpq	%rbx, %r14
diff --git a/test/MC/X86/x86_64-avx-encoding.s b/test/MC/X86/x86_64-avx-encoding.s
index 1704b94a7298..1440d080ee80 100644
--- a/test/MC/X86/x86_64-avx-encoding.s
+++ b/test/MC/X86/x86_64-avx-encoding.s
@@ -344,1027 +344,1027 @@ vdivpd  -4(%rcx,%rbx,8), %xmm10, %xmm11
 // CHECK: encoding: [0xc5,0x19,0xc6,0x6c,0xcb,0xfc,0x08]
           vshufpd  $8, -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $0, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x00]
           vcmpeqps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $2, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpleps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x02]
           vcmpleps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $1, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpltps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x01]
           vcmpltps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $4, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x04]
           vcmpneqps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $6, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnleps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x06]
           vcmpnleps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $5, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnltps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x05]
           vcmpnltps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $7, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpordps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x07]
           vcmpordps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $3, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpunordps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x03]
           vcmpunordps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $0, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeqps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x00]
           vcmpeqps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $2, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpleps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x02]
           vcmpleps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $1, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpltps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x01]
           vcmpltps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $4, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneqps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x04]
           vcmpneqps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $6, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnleps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x06]
           vcmpnleps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $5, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnltps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x05]
           vcmpnltps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $7, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpordps  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x07]
           vcmpordps   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmpps  $3, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpunordps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x03]
           vcmpunordps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $0, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeqpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x00]
           vcmpeqpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $2, %xmm11, %xmm12, %xmm13
+// CHECK: vcmplepd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x02]
           vcmplepd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $1, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpltpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x01]
           vcmpltpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $4, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneqpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x04]
           vcmpneqpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $6, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnlepd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x06]
           vcmpnlepd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $5, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnltpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x05]
           vcmpnltpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $7, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpordpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x07]
           vcmpordpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $3, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpunordpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x03]
           vcmpunordpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $0, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeqpd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x00]
           vcmpeqpd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $2, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmplepd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x02]
           vcmplepd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $1, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpltpd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x01]
           vcmpltpd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $4, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneqpd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x04]
           vcmpneqpd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $6, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnlepd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x06]
           vcmpnlepd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $5, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnltpd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x05]
           vcmpnltpd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $7, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpordpd  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x07]
           vcmpordpd   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmppd  $3, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpunordpd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x03]
           vcmpunordpd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $0, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeqss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x00]
           vcmpeqss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $2, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpless  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x02]
           vcmpless   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $1, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpltss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x01]
           vcmpltss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $4, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneqss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x04]
           vcmpneqss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $6, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnless  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x06]
           vcmpnless   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $5, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnltss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x05]
           vcmpnltss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $7, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpordss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x07]
           vcmpordss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $3, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpunordss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x03]
           vcmpunordss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $0, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeqss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x00]
           vcmpeqss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $2, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpless  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x02]
           vcmpless   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $1, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpltss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x01]
           vcmpltss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $4, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneqss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x04]
           vcmpneqss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $6, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnless  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x06]
           vcmpnless   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $5, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnltss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x05]
           vcmpnltss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $7, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpordss  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x07]
           vcmpordss   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmpss  $3, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpunordss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x03]
           vcmpunordss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $0, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeqsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x00]
           vcmpeqsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $2, %xmm11, %xmm12, %xmm13
+// CHECK: vcmplesd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x02]
           vcmplesd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $1, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpltsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x01]
           vcmpltsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $4, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneqsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x04]
           vcmpneqsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $6, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnlesd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x06]
           vcmpnlesd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $5, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnltsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x05]
           vcmpnltsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $7, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpordsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x07]
           vcmpordsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $3, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpunordsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x03]
           vcmpunordsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $0, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeqsd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x00]
           vcmpeqsd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $2, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmplesd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x02]
           vcmplesd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $1, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpltsd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x01]
           vcmpltsd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $4, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneqsd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x04]
           vcmpneqsd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $6, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnlesd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x06]
           vcmpnlesd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $5, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnltsd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x05]
           vcmpnltsd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $7, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpordsd  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x07]
           vcmpordsd   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmpsd  $3, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpunordsd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x03]
           vcmpunordsd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $8, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeq_uqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x08]
           vcmpeq_uqps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $9, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpngeps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x09]
           vcmpngeps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $10, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpngtps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0a]
           vcmpngtps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $11, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpfalseps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0b]
           vcmpfalseps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $12, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneq_oqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0c]
           vcmpneq_oqps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $13, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpgeps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0d]
           vcmpgeps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $14, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpgtps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0e]
           vcmpgtps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $15, %xmm11, %xmm12, %xmm13
+// CHECK: vcmptrueps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0f]
           vcmptrueps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $16, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeq_osps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x10]
           vcmpeq_osps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $17, %xmm11, %xmm12, %xmm13
+// CHECK: vcmplt_oqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x11]
           vcmplt_oqps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $18, %xmm11, %xmm12, %xmm13
+// CHECK: vcmple_oqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x12]
           vcmple_oqps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $19, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpunord_sps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x13]
           vcmpunord_sps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $20, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneq_usps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x14]
           vcmpneq_usps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $21, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnlt_uqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x15]
           vcmpnlt_uqps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $22, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnle_uqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x16]
           vcmpnle_uqps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $23, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpord_sps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x17]
           vcmpord_sps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $24, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeq_usps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x18]
           vcmpeq_usps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $25, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnge_uqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x19]
           vcmpnge_uqps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $26, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpngt_uqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1a]
           vcmpngt_uqps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $27, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpfalse_osps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1b]
           vcmpfalse_osps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $28, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneq_osps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1c]
           vcmpneq_osps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $29, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpge_oqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1d]
           vcmpge_oqps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $30, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpgt_oqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1e]
           vcmpgt_oqps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $31, %xmm11, %xmm12, %xmm13
+// CHECK: vcmptrue_usps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1f]
           vcmptrue_usps   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $8, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeq_uqps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x08]
           vcmpeq_uqps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $9, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpngeps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x09]
           vcmpngeps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $10, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpngtps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0a]
           vcmpngtps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $11, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpfalseps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0b]
           vcmpfalseps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $12, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneq_oqps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0c]
           vcmpneq_oqps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $13, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpgeps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0d]
           vcmpgeps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $14, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpgtps  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x0e]
           vcmpgtps   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmpps  $15, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmptrueps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0f]
           vcmptrueps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $16, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeq_osps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x10]
           vcmpeq_osps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $17, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmplt_oqps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x11]
           vcmplt_oqps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $18, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmple_oqps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x12]
           vcmple_oqps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $19, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpunord_sps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x13]
           vcmpunord_sps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $20, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneq_usps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x14]
           vcmpneq_usps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $21, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnlt_uqps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x15]
           vcmpnlt_uqps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $22, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpnle_uqps  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x16]
           vcmpnle_uqps   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmpps  $23, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpord_sps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x17]
           vcmpord_sps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $24, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeq_usps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x18]
           vcmpeq_usps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $25, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnge_uqps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x19]
           vcmpnge_uqps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $26, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpngt_uqps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1a]
           vcmpngt_uqps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $27, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpfalse_osps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1b]
           vcmpfalse_osps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $28, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneq_osps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1c]
           vcmpneq_osps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $29, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpge_oqps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1d]
           vcmpge_oqps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpps  $30, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpgt_oqps  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x1e]
           vcmpgt_oqps   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmpps  $31, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmptrue_usps  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1f]
           vcmptrue_usps   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $8, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeq_uqpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x08]
           vcmpeq_uqpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $9, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpngepd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x09]
           vcmpngepd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $10, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpngtpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0a]
           vcmpngtpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $11, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpfalsepd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0b]
           vcmpfalsepd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $12, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneq_oqpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0c]
           vcmpneq_oqpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $13, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpgepd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0d]
           vcmpgepd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $14, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpgtpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0e]
           vcmpgtpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $15, %xmm11, %xmm12, %xmm13
+// CHECK: vcmptruepd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0f]
           vcmptruepd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $16, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeq_ospd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x10]
           vcmpeq_ospd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $17, %xmm11, %xmm12, %xmm13
+// CHECK: vcmplt_oqpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x11]
           vcmplt_oqpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $18, %xmm11, %xmm12, %xmm13
+// CHECK: vcmple_oqpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x12]
           vcmple_oqpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $19, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpunord_spd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x13]
           vcmpunord_spd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $20, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneq_uspd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x14]
           vcmpneq_uspd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $21, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnlt_uqpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x15]
           vcmpnlt_uqpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $22, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnle_uqpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x16]
           vcmpnle_uqpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $23, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpord_spd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x17]
           vcmpord_spd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $24, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeq_uspd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x18]
           vcmpeq_uspd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $25, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnge_uqpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x19]
           vcmpnge_uqpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $26, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpngt_uqpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1a]
           vcmpngt_uqpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $27, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpfalse_ospd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1b]
           vcmpfalse_ospd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $28, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneq_ospd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1c]
           vcmpneq_ospd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $29, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpge_oqpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1d]
           vcmpge_oqpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $30, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpgt_oqpd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1e]
           vcmpgt_oqpd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $31, %xmm11, %xmm12, %xmm13
+// CHECK: vcmptrue_uspd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1f]
           vcmptrue_uspd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmppd  $8, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeq_uqpd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x08]
           vcmpeq_uqpd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $9, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpngepd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x09]
           vcmpngepd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $10, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpngtpd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0a]
           vcmpngtpd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $11, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpfalsepd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0b]
           vcmpfalsepd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $12, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneq_oqpd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0c]
           vcmpneq_oqpd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $13, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpgepd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0d]
           vcmpgepd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $14, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpgtpd  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x0e]
           vcmpgtpd   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmppd  $15, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmptruepd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0f]
           vcmptruepd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $16, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeq_ospd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x10]
           vcmpeq_ospd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $17, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmplt_oqpd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x11]
           vcmplt_oqpd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $18, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmple_oqpd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x12]
           vcmple_oqpd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $19, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpunord_spd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x13]
           vcmpunord_spd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $20, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneq_uspd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x14]
           vcmpneq_uspd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $21, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnlt_uqpd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x15]
           vcmpnlt_uqpd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $22, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpnle_uqpd  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x16]
           vcmpnle_uqpd   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmppd  $23, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpord_spd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x17]
           vcmpord_spd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $24, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeq_uspd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x18]
           vcmpeq_uspd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $25, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnge_uqpd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x19]
           vcmpnge_uqpd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $26, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpngt_uqpd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1a]
           vcmpngt_uqpd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $27, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpfalse_ospd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1b]
           vcmpfalse_ospd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $28, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneq_ospd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1c]
           vcmpneq_ospd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $29, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpge_oqpd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1d]
           vcmpge_oqpd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmppd  $30, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpgt_oqpd  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x1e]
           vcmpgt_oqpd   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmppd  $31, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmptrue_uspd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1f]
           vcmptrue_uspd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $8, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeq_uqss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x08]
           vcmpeq_uqss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $9, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpngess  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x09]
           vcmpngess   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $10, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpngtss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0a]
           vcmpngtss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $11, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpfalsess  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0b]
           vcmpfalsess   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $12, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneq_oqss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0c]
           vcmpneq_oqss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $13, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpgess  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0d]
           vcmpgess   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $14, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpgtss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0e]
           vcmpgtss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $15, %xmm11, %xmm12, %xmm13
+// CHECK: vcmptruess  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0f]
           vcmptruess   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $16, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeq_osss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x10]
           vcmpeq_osss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $17, %xmm11, %xmm12, %xmm13
+// CHECK: vcmplt_oqss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x11]
           vcmplt_oqss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $18, %xmm11, %xmm12, %xmm13
+// CHECK: vcmple_oqss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x12]
           vcmple_oqss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $19, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpunord_sss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x13]
           vcmpunord_sss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $20, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneq_usss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x14]
           vcmpneq_usss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $21, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnlt_uqss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x15]
           vcmpnlt_uqss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $22, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnle_uqss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x16]
           vcmpnle_uqss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $23, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpord_sss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x17]
           vcmpord_sss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $24, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeq_usss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x18]
           vcmpeq_usss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $25, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnge_uqss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x19]
           vcmpnge_uqss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $26, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpngt_uqss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1a]
           vcmpngt_uqss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $27, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpfalse_osss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1b]
           vcmpfalse_osss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $28, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneq_osss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1c]
           vcmpneq_osss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $29, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpge_oqss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1d]
           vcmpge_oqss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $30, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpgt_oqss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1e]
           vcmpgt_oqss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $31, %xmm11, %xmm12, %xmm13
+// CHECK: vcmptrue_usss  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1f]
           vcmptrue_usss   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpss  $8, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeq_uqss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x08]
           vcmpeq_uqss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $9, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpngess  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x09]
           vcmpngess   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $10, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpngtss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0a]
           vcmpngtss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $11, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpfalsess  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0b]
           vcmpfalsess   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $12, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneq_oqss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0c]
           vcmpneq_oqss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $13, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpgess  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0d]
           vcmpgess   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $14, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpgtss  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x0e]
           vcmpgtss   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmpss  $15, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmptruess  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0f]
           vcmptruess   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $16, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeq_osss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x10]
           vcmpeq_osss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $17, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmplt_oqss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x11]
           vcmplt_oqss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $18, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmple_oqss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x12]
           vcmple_oqss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $19, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpunord_sss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x13]
           vcmpunord_sss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $20, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneq_usss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x14]
           vcmpneq_usss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $21, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnlt_uqss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x15]
           vcmpnlt_uqss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $22, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpnle_uqss  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x16]
           vcmpnle_uqss   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmpss  $23, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpord_sss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x17]
           vcmpord_sss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $24, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeq_usss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x18]
           vcmpeq_usss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $25, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnge_uqss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x19]
           vcmpnge_uqss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $26, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpngt_uqss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1a]
           vcmpngt_uqss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $27, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpfalse_osss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1b]
           vcmpfalse_osss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $28, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneq_osss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1c]
           vcmpneq_osss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $29, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpge_oqss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1d]
           vcmpge_oqss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpss  $30, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpgt_oqss  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x1e]
           vcmpgt_oqss   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmpss  $31, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmptrue_usss  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1f]
           vcmptrue_usss   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $8, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeq_uqsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x08]
           vcmpeq_uqsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $9, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpngesd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x09]
           vcmpngesd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $10, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpngtsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0a]
           vcmpngtsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $11, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpfalsesd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0b]
           vcmpfalsesd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $12, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneq_oqsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0c]
           vcmpneq_oqsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $13, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpgesd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0d]
           vcmpgesd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $14, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpgtsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0e]
           vcmpgtsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $15, %xmm11, %xmm12, %xmm13
+// CHECK: vcmptruesd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0f]
           vcmptruesd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $16, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeq_ossd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x10]
           vcmpeq_ossd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $17, %xmm11, %xmm12, %xmm13
+// CHECK: vcmplt_oqsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x11]
           vcmplt_oqsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $18, %xmm11, %xmm12, %xmm13
+// CHECK: vcmple_oqsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x12]
           vcmple_oqsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $19, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpunord_ssd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x13]
           vcmpunord_ssd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $20, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneq_ussd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x14]
           vcmpneq_ussd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $21, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnlt_uqsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x15]
           vcmpnlt_uqsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $22, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnle_uqsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x16]
           vcmpnle_uqsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $23, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpord_ssd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x17]
           vcmpord_ssd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $24, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeq_ussd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x18]
           vcmpeq_ussd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $25, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnge_uqsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x19]
           vcmpnge_uqsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $26, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpngt_uqsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1a]
           vcmpngt_uqsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $27, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpfalse_ossd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1b]
           vcmpfalse_ossd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $28, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneq_ossd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1c]
           vcmpneq_ossd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $29, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpge_oqsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1d]
           vcmpge_oqsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $30, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpgt_oqsd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1e]
           vcmpgt_oqsd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $31, %xmm11, %xmm12, %xmm13
+// CHECK: vcmptrue_ussd  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1f]
           vcmptrue_ussd   %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpsd  $8, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeq_uqsd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x08]
           vcmpeq_uqsd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $9, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpngesd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x09]
           vcmpngesd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $10, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpngtsd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0a]
           vcmpngtsd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $11, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpfalsesd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0b]
           vcmpfalsesd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $12, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneq_oqsd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0c]
           vcmpneq_oqsd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $13, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpgesd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0d]
           vcmpgesd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $14, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpgtsd  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x0e]
           vcmpgtsd   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmpsd  $15, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmptruesd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0f]
           vcmptruesd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $16, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeq_ossd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x10]
           vcmpeq_ossd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $17, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmplt_oqsd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x11]
           vcmplt_oqsd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $18, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmple_oqsd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x12]
           vcmple_oqsd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $19, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpunord_ssd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x13]
           vcmpunord_ssd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $20, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneq_ussd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x14]
           vcmpneq_ussd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $21, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnlt_uqsd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x15]
           vcmpnlt_uqsd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $22, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpnle_uqsd  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x16]
           vcmpnle_uqsd   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmpsd  $23, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpord_ssd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x17]
           vcmpord_ssd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $24, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpeq_ussd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x18]
           vcmpeq_ussd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $25, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpnge_uqsd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x19]
           vcmpnge_uqsd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $26, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpngt_uqsd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1a]
           vcmpngt_uqsd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $27, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpfalse_ossd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1b]
           vcmpfalse_ossd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $28, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpneq_ossd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1c]
           vcmpneq_ossd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $29, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmpge_oqsd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1d]
           vcmpge_oqsd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
-// CHECK: vcmpsd  $30, -4(%rbx,%rcx,8), %xmm6, %xmm2
+// CHECK: vcmpgt_oqsd  -4(%rbx,%rcx,8), %xmm6, %xmm2
 // CHECK: encoding: [0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x1e]
           vcmpgt_oqsd   -4(%rbx,%rcx,8), %xmm6, %xmm2
 
-// CHECK: vcmpsd  $31, -4(%rbx,%rcx,8), %xmm12, %xmm13
+// CHECK: vcmptrue_ussd  -4(%rbx,%rcx,8), %xmm12, %xmm13
 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1f]
           vcmptrue_ussd   -4(%rbx,%rcx,8), %xmm12, %xmm13
 
@@ -2936,99 +2936,99 @@ vdivpd  -4(%rcx,%rbx,8), %xmm10, %xmm11
 // CHECK: encoding: [0xc4,0x63,0x79,0xdf,0x10,0x07]
           vaeskeygenassist  $7, (%rax), %xmm10
 
-// CHECK: vcmpps  $8, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeq_uqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x08]
           vcmpeq_uqps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $9, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpngeps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x09]
           vcmpngeps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $10, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpngtps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0a]
           vcmpngtps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $11, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpfalseps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0b]
           vcmpfalseps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $12, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneq_oqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0c]
           vcmpneq_oqps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $13, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpgeps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0d]
           vcmpgeps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $14, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpgtps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0e]
           vcmpgtps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $15, %xmm11, %xmm12, %xmm13
+// CHECK: vcmptrueps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0f]
           vcmptrueps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $16, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeq_osps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x10]
           vcmpeq_osps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $17, %xmm11, %xmm12, %xmm13
+// CHECK: vcmplt_oqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x11]
           vcmplt_oqps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $18, %xmm11, %xmm12, %xmm13
+// CHECK: vcmple_oqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x12]
           vcmple_oqps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $19, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpunord_sps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x13]
           vcmpunord_sps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $20, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneq_usps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x14]
           vcmpneq_usps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $21, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnlt_uqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x15]
           vcmpnlt_uqps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $22, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnle_uqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x16]
           vcmpnle_uqps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $23, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpord_sps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x17]
           vcmpord_sps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $24, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpeq_usps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x18]
           vcmpeq_usps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $25, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpnge_uqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x19]
           vcmpnge_uqps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $26, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpngt_uqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1a]
           vcmpngt_uqps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $27, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpfalse_osps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1b]
           vcmpfalse_osps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $28, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpneq_osps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1c]
           vcmpneq_osps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $29, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpge_oqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1d]
           vcmpge_oqps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $30, %xmm11, %xmm12, %xmm13
+// CHECK: vcmpgt_oqps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1e]
           vcmpgt_oqps %xmm11, %xmm12, %xmm13
 
-// CHECK: vcmpps  $31, %xmm11, %xmm12, %xmm13
+// CHECK: vcmptrue_usps  %xmm11, %xmm12, %xmm13
 // CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1f]
           vcmptrue_usps %xmm11, %xmm12, %xmm13
 
@@ -3428,227 +3428,227 @@ vdivpd  -4(%rcx,%rbx,8), %xmm10, %xmm11
 // CHECK: encoding: [0xc5,0x7b,0xe6,0x18]
           vcvtpd2dqx  (%rax), %xmm11
 
-// CHECK: vcmpps  $0, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpeqps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x00]
           vcmpeqps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $2, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpleps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x02]
           vcmpleps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $1, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpltps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x01]
           vcmpltps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $4, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpneqps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x04]
           vcmpneqps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $6, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpnleps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x06]
           vcmpnleps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $5, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpnltps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x05]
           vcmpnltps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $7, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpordps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x07]
           vcmpordps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $3, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpunordps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x03]
           vcmpunordps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $0, -4(%rbx,%rcx,8), %ymm12, %ymm13
+// CHECK: vcmpeqps  -4(%rbx,%rcx,8), %ymm12, %ymm13
 // CHECK: encoding: [0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x00]
           vcmpeqps -4(%rbx,%rcx,8), %ymm12, %ymm13
 
-// CHECK: vcmpps  $2, -4(%rbx,%rcx,8), %ymm12, %ymm13
+// CHECK: vcmpleps  -4(%rbx,%rcx,8), %ymm12, %ymm13
 // CHECK: encoding: [0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x02]
           vcmpleps -4(%rbx,%rcx,8), %ymm12, %ymm13
 
-// CHECK: vcmpps  $1, -4(%rbx,%rcx,8), %ymm12, %ymm13
+// CHECK: vcmpltps  -4(%rbx,%rcx,8), %ymm12, %ymm13
 // CHECK: encoding: [0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x01]
           vcmpltps -4(%rbx,%rcx,8), %ymm12, %ymm13
 
-// CHECK: vcmpps  $4, -4(%rbx,%rcx,8), %ymm12, %ymm13
+// CHECK: vcmpneqps  -4(%rbx,%rcx,8), %ymm12, %ymm13
 // CHECK: encoding: [0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x04]
           vcmpneqps -4(%rbx,%rcx,8), %ymm12, %ymm13
 
-// CHECK: vcmpps  $6, -4(%rbx,%rcx,8), %ymm12, %ymm13
+// CHECK: vcmpnleps  -4(%rbx,%rcx,8), %ymm12, %ymm13
 // CHECK: encoding: [0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x06]
           vcmpnleps -4(%rbx,%rcx,8), %ymm12, %ymm13
 
-// CHECK: vcmpps  $5, -4(%rbx,%rcx,8), %ymm12, %ymm13
+// CHECK: vcmpnltps  -4(%rbx,%rcx,8), %ymm12, %ymm13
 // CHECK: encoding: [0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x05]
           vcmpnltps -4(%rbx,%rcx,8), %ymm12, %ymm13
 
-// CHECK: vcmpps  $7, -4(%rbx,%rcx,8), %ymm6, %ymm12
+// CHECK: vcmpordps  -4(%rbx,%rcx,8), %ymm6, %ymm12
 // CHECK: encoding: [0xc5,0x4c,0xc2,0x64,0xcb,0xfc,0x07]
           vcmpordps -4(%rbx,%rcx,8), %ymm6, %ymm12
 
-// CHECK: vcmpps  $3, -4(%rbx,%rcx,8), %ymm12, %ymm13
+// CHECK: vcmpunordps  -4(%rbx,%rcx,8), %ymm12, %ymm13
 // CHECK: encoding: [0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x03]
           vcmpunordps -4(%rbx,%rcx,8), %ymm12, %ymm13
 
-// CHECK: vcmppd  $0, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpeqpd  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x00]
           vcmpeqpd %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmppd  $2, %ymm11, %ymm12, %ymm13
+// CHECK: vcmplepd  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x02]
           vcmplepd %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmppd  $1, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpltpd  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x01]
           vcmpltpd %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmppd  $4, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpneqpd  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x04]
           vcmpneqpd %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmppd  $6, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpnlepd  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x06]
           vcmpnlepd %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmppd  $5, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpnltpd  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x05]
           vcmpnltpd %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmppd  $7, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpordpd  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x07]
           vcmpordpd %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmppd  $3, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpunordpd  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x03]
           vcmpunordpd %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmppd  $0, -4(%rbx,%rcx,8), %ymm12, %ymm13
+// CHECK: vcmpeqpd  -4(%rbx,%rcx,8), %ymm12, %ymm13
 // CHECK: encoding: [0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x00]
           vcmpeqpd -4(%rbx,%rcx,8), %ymm12, %ymm13
 
-// CHECK: vcmppd  $2, -4(%rbx,%rcx,8), %ymm12, %ymm13
+// CHECK: vcmplepd  -4(%rbx,%rcx,8), %ymm12, %ymm13
 // CHECK: encoding: [0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x02]
           vcmplepd -4(%rbx,%rcx,8), %ymm12, %ymm13
 
-// CHECK: vcmppd  $1, -4(%rbx,%rcx,8), %ymm12, %ymm13
+// CHECK: vcmpltpd  -4(%rbx,%rcx,8), %ymm12, %ymm13
 // CHECK: encoding: [0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x01]
           vcmpltpd -4(%rbx,%rcx,8), %ymm12, %ymm13
 
-// CHECK: vcmppd  $4, -4(%rbx,%rcx,8), %ymm12, %ymm13
+// CHECK: vcmpneqpd  -4(%rbx,%rcx,8), %ymm12, %ymm13
 // CHECK: encoding: [0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x04]
           vcmpneqpd -4(%rbx,%rcx,8), %ymm12, %ymm13
 
-// CHECK: vcmppd  $6, -4(%rbx,%rcx,8), %ymm12, %ymm13
+// CHECK: vcmpnlepd  -4(%rbx,%rcx,8), %ymm12, %ymm13
 // CHECK: encoding: [0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x06]
           vcmpnlepd -4(%rbx,%rcx,8), %ymm12, %ymm13
 
-// CHECK: vcmppd  $5, -4(%rbx,%rcx,8), %ymm12, %ymm13
+// CHECK: vcmpnltpd  -4(%rbx,%rcx,8), %ymm12, %ymm13
 // CHECK: encoding: [0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x05]
           vcmpnltpd -4(%rbx,%rcx,8), %ymm12, %ymm13
 
-// CHECK: vcmppd  $7, -4(%rbx,%rcx,8), %ymm6, %ymm12
+// CHECK: vcmpordpd  -4(%rbx,%rcx,8), %ymm6, %ymm12
 // CHECK: encoding: [0xc5,0x4d,0xc2,0x64,0xcb,0xfc,0x07]
           vcmpordpd -4(%rbx,%rcx,8), %ymm6, %ymm12
 
-// CHECK: vcmppd  $3, -4(%rbx,%rcx,8), %ymm12, %ymm13
+// CHECK: vcmpunordpd  -4(%rbx,%rcx,8), %ymm12, %ymm13
 // CHECK: encoding: [0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x03]
           vcmpunordpd -4(%rbx,%rcx,8), %ymm12, %ymm13
 
-// CHECK: vcmpps  $8, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpeq_uqps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x08]
           vcmpeq_uqps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $9, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpngeps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x09]
           vcmpngeps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $10, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpngtps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x0a]
           vcmpngtps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $11, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpfalseps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x0b]
           vcmpfalseps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $12, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpneq_oqps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x0c]
           vcmpneq_oqps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $13, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpgeps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x0d]
           vcmpgeps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $14, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpgtps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x0e]
           vcmpgtps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $15, %ymm11, %ymm12, %ymm13
+// CHECK: vcmptrueps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x0f]
           vcmptrueps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $16, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpeq_osps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x10]
           vcmpeq_osps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $17, %ymm11, %ymm12, %ymm13
+// CHECK: vcmplt_oqps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x11]
           vcmplt_oqps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $18, %ymm11, %ymm12, %ymm13
+// CHECK: vcmple_oqps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x12]
           vcmple_oqps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $19, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpunord_sps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x13]
           vcmpunord_sps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $20, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpneq_usps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x14]
           vcmpneq_usps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $21, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpnlt_uqps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x15]
           vcmpnlt_uqps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $22, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpnle_uqps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x16]
           vcmpnle_uqps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $23, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpord_sps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x17]
           vcmpord_sps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $24, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpeq_usps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x18]
           vcmpeq_usps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $25, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpnge_uqps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x19]
           vcmpnge_uqps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $26, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpngt_uqps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x1a]
           vcmpngt_uqps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $27, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpfalse_osps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x1b]
           vcmpfalse_osps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $28, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpneq_osps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x1c]
           vcmpneq_osps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $29, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpge_oqps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x1d]
           vcmpge_oqps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $30, %ymm11, %ymm12, %ymm13
+// CHECK: vcmpgt_oqps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x1e]
           vcmpgt_oqps %ymm11, %ymm12, %ymm13
 
-// CHECK: vcmpps  $31, %ymm11, %ymm12, %ymm13
+// CHECK: vcmptrue_usps  %ymm11, %ymm12, %ymm13
 // CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x1f]
           vcmptrue_usps %ymm11, %ymm12, %ymm13
 
@@ -3724,6 +3724,10 @@ vdivpd  -4(%rcx,%rbx,8), %xmm10, %xmm11
 // CHECK: encoding: [0xc4,0x63,0x2d,0x40,0x18,0x03]
           vdpps  $3, (%rax), %ymm10, %ymm11
 
+// CHECK: vbroadcasti128  (%rax), %ymm12
+// CHECK: encoding: [0xc4,0x62,0x7d,0x5a,0x20]
+          vbroadcasti128  (%rax), %ymm12
+
 // CHECK: vbroadcastf128  (%rax), %ymm12
 // CHECK: encoding: [0xc4,0x62,0x7d,0x1a,0x20]
           vbroadcastf128  (%rax), %ymm12
diff --git a/test/MC/X86/x86_64-encoding.s b/test/MC/X86/x86_64-encoding.s
index 40b93f0a7d05..62af1bdb2357 100644
--- a/test/MC/X86/x86_64-encoding.s
+++ b/test/MC/X86/x86_64-encoding.s
@@ -200,14 +200,22 @@ sha256msg2 (%rax), %xmm2
 // CHECK: encoding: [0x48,0x8b,0x04,0xe1]
           movq  (%rcx,%riz,8), %rax
 
-// CHECK: fxsaveq (%rax)
+// CHECK: fxsave64 (%rax)
 // CHECK: encoding: [0x48,0x0f,0xae,0x00]
           fxsaveq (%rax)
 
-// CHECK: fxrstorq (%rax)
+// CHECK: fxsave64 (%rax)
+// CHECK: encoding: [0x48,0x0f,0xae,0x00]
+          fxsave64 (%rax)
+
+// CHECK: fxrstor64 (%rax)
 // CHECK: encoding: [0x48,0x0f,0xae,0x08]
           fxrstorq (%rax)
 
+// CHECK: fxrstor64 (%rax)
+// CHECK: encoding: [0x48,0x0f,0xae,0x08]
+          fxrstor64 (%rax)
+
 // CHECK: leave
 // CHECK:  encoding: [0xc9]
         	leave
diff --git a/test/MC/X86/x86_64-xop-encoding.s b/test/MC/X86/x86_64-xop-encoding.s
index 1137b71df04b..48f30ec9e36b 100644
--- a/test/MC/X86/x86_64-xop-encoding.s
+++ b/test/MC/X86/x86_64-xop-encoding.s
@@ -506,6 +506,70 @@
 // CHECK: encoding: [0x8f,0xe8,0x60,0xcc,0x50,0x08,0x38]
           vpcomb $56, 8(%rax), %xmm3, %xmm2
 
+// CHECK: vpcomltw %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xcd,0xe2,0x00]
+          vpcomltw %xmm2, %xmm3, %xmm4
+
+// CHECK: vpcomlew %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xcd,0xe2,0x01]
+          vpcomlew %xmm2, %xmm3, %xmm4
+
+// CHECK: vpcomgtw %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xcd,0xe2,0x02]
+          vpcomgtw %xmm2, %xmm3, %xmm4
+
+// CHECK: vpcomgew %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xcd,0xe2,0x03]
+          vpcomgew %xmm2, %xmm3, %xmm4
+
+// CHECK: vpcomeqw %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xcd,0xe2,0x04]
+          vpcomeqw %xmm2, %xmm3, %xmm4
+
+// CHECK: vpcomneqw %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xcd,0xe2,0x05]
+          vpcomneqw %xmm2, %xmm3, %xmm4
+
+// CHECK: vpcomfalsew %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xcd,0xe2,0x06]
+          vpcomfalsew %xmm2, %xmm3, %xmm4
+
+// CHECK: vpcomtruew %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xcd,0xe2,0x07]
+          vpcomtruew %xmm2, %xmm3, %xmm4
+
+
+// CHECK: vpcomltuw %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xed,0xe2,0x00]
+          vpcomltuw %xmm2, %xmm3, %xmm4
+
+// CHECK: vpcomleuw %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xed,0xe2,0x01]
+          vpcomleuw %xmm2, %xmm3, %xmm4
+
+// CHECK: vpcomgtuw %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xed,0xe2,0x02]
+          vpcomgtuw %xmm2, %xmm3, %xmm4
+
+// CHECK: vpcomgeuw %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xed,0xe2,0x03]
+          vpcomgeuw %xmm2, %xmm3, %xmm4
+
+// CHECK: vpcomequw %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xed,0xe2,0x04]
+          vpcomequw %xmm2, %xmm3, %xmm4
+
+// CHECK: vpcomnequw %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xed,0xe2,0x05]
+          vpcomnequw %xmm2, %xmm3, %xmm4
+
+// CHECK: vpcomfalseuw %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xed,0xe2,0x06]
+          vpcomfalseuw %xmm2, %xmm3, %xmm4
+
+// CHECK: vpcomtrueuw %xmm2, %xmm3, %xmm4
+// CHECK: encoding: [0x8f,0xe8,0x60,0xed,0xe2,0x07]
+          vpcomtrueuw %xmm2, %xmm3, %xmm4
 
 // vpperm
 // CHECK: vpperm %xmm1, %xmm2, %xmm3, %xmm4
diff --git a/test/MC/X86/x86_errors.s b/test/MC/X86/x86_errors.s
index 0b3bc7f43502..fa87ef676f3e 100644
--- a/test/MC/X86/x86_errors.s
+++ b/test/MC/X86/x86_errors.s
@@ -50,3 +50,11 @@ outb al, 4
 // 32: error: invalid segment register
 // 64: error: invalid segment register
 movl %eax:0x00, %ebx
+
+// 32: error: invalid operand for instruction
+// 64: error: invalid operand for instruction
+cmpps $-129, %xmm0, %xmm0
+
+// 32: error: invalid operand for instruction
+// 64: error: invalid operand for instruction
+cmppd $256, %xmm0, %xmm0
diff --git a/test/Makefile b/test/Makefile
index 7f253b066256..558762e39dc2 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -85,13 +85,13 @@ endif
 # just removing them here won't work.
 # Solaris does not have the -m flag for ulimit
 ifeq ($(HOST_OS),SunOS)
-ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; ulimit -v 512000 ;
+ULIMIT=ulimit -t 1200 ; ulimit -d 512000 ; ulimit -v 512000 ;
 else # !SunOS
 # Newer versions of python try to allocate an insane amount of address space for
 # its thread-local storage, don't set a limit here.
 # When -v is not used, then -s has to be used to limit the stack size.
 # FIXME: Those limits should be enforced by lit instead of globally.
-ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; ulimit -m 512000 ; ulimit -s 8192 ;
+ULIMIT=ulimit -t 1200 ; ulimit -d 512000 ; ulimit -m 512000 ; ulimit -s 8192 ;
 endif # SunOS
 
 check-local:: lit.site.cfg Unit/lit.site.cfg
@@ -128,6 +128,8 @@ lit.site.cfg: FORCE
 	@$(ECHOPATH) s=@SHLIBEXT@=$(SHLIBEXT)=g >> lit.tmp
 	@$(ECHOPATH) s=@EXEEXT@=$(EXEEXT)=g >> lit.tmp
 	@$(ECHOPATH) s=@PYTHON_EXECUTABLE@=$(PYTHON)=g >> lit.tmp
+	@$(ECHOPATH) s=@GOLD_EXECUTABLE@=ld=g >> lit.tmp
+	@$(ECHOPATH) s=@LD64_EXECUTABLE@=ld=g >> lit.tmp
 	@$(ECHOPATH) s=@OCAMLFIND@=$(OCAMLFIND)=g >> lit.tmp
 	@$(ECHOPATH) s!@OCAMLFLAGS@!$(addprefix -cclib ,$(LDFLAGS))!g >> lit.tmp
 	@$(ECHOPATH) s=@HAVE_OCAMLOPT@=$(HAVE_OCAMLOPT)=g >> lit.tmp
@@ -143,6 +145,7 @@ lit.site.cfg: FORCE
 	@$(ECHOPATH) s=@HOST_OS@=$(HOST_OS)=g >> lit.tmp
 	@$(ECHOPATH) s=@HOST_ARCH@=$(HOST_ARCH)=g >> lit.tmp
 	@$(ECHOPATH) s=@HAVE_LIBZ@=$(HAVE_LIBZ)=g >> lit.tmp
+	@$(ECHOPATH) s=@HAVE_DIA_SDK@=0=g >> lit.tmp
 	@sed -f lit.tmp $(PROJ_SRC_DIR)/lit.site.cfg.in > $@
 	@-rm -f lit.tmp
 
diff --git a/test/Object/AArch64/yaml2obj-elf-aarch64-rel.yaml b/test/Object/AArch64/yaml2obj-elf-aarch64-rel.yaml
index b8fb68113c76..c27e888a47c0 100644
--- a/test/Object/AArch64/yaml2obj-elf-aarch64-rel.yaml
+++ b/test/Object/AArch64/yaml2obj-elf-aarch64-rel.yaml
@@ -10,11 +10,9 @@
 # CHECK-NEXT:      - Offset:          0x0000000000000000
 # CHECK-NEXT:        Symbol:          main
 # CHECK-NEXT:        Type:            R_AARCH64_ABS64
-# CHECK-NEXT:        Addend:          0
 # CHECK-NEXT:      - Offset:          0x0000000000000008
 # CHECK-NEXT:        Symbol:          main
 # CHECK-NEXT:        Type:            R_AARCH64_TLSGD_ADR_PREL21
-# CHECK-NEXT:        Addend:          0
 
 FileHeader:
   Class:           ELFCLASS64
diff --git a/test/Object/Inputs/archive-test.a-irix6-mips64el b/test/Object/Inputs/archive-test.a-irix6-mips64el
new file mode 100644
index 000000000000..ccc2634be7a2
--- /dev/null
+++ b/test/Object/Inputs/archive-test.a-irix6-mips64el
diff --git a/test/Object/Inputs/macho-empty-kext-bundle-x86-64 b/test/Object/Inputs/macho-empty-kext-bundle-x86-64
new file mode 100755
index 000000000000..bf75d3041ce0
--- /dev/null
+++ b/test/Object/Inputs/macho-empty-kext-bundle-x86-64
diff --git a/test/Object/Inputs/macho-invalid-bad-symbol-index b/test/Object/Inputs/macho-invalid-bad-symbol-index
new file mode 100644
index 000000000000..294bbde3ddff
--- /dev/null
+++ b/test/Object/Inputs/macho-invalid-bad-symbol-index
diff --git a/test/Object/Inputs/macho-invalid-no-size-for-sections b/test/Object/Inputs/macho-invalid-no-size-for-sections
new file mode 100644
index 000000000000..89fa95acbcf8
--- /dev/null
+++ b/test/Object/Inputs/macho-invalid-no-size-for-sections
diff --git a/test/Object/Inputs/macho-invalid-section-index-getSectionRawName b/test/Object/Inputs/macho-invalid-section-index-getSectionRawName
new file mode 100644
index 000000000000..9cd3e1cace8c
--- /dev/null
+++ b/test/Object/Inputs/macho-invalid-section-index-getSectionRawName
diff --git a/test/Object/Inputs/macho-invalid-symbol-name-past-eof b/test/Object/Inputs/macho-invalid-symbol-name-past-eof
new file mode 100644
index 000000000000..874788407879
--- /dev/null
+++ b/test/Object/Inputs/macho-invalid-symbol-name-past-eof
diff --git a/test/Object/Inputs/macho-invalid-too-small-load-command b/test/Object/Inputs/macho-invalid-too-small-load-command
new file mode 100644
index 000000000000..36021692ee55
--- /dev/null
+++ b/test/Object/Inputs/macho-invalid-too-small-load-command
diff --git a/test/Object/Inputs/macho-invalid-too-small-segment-load-command b/test/Object/Inputs/macho-invalid-too-small-segment-load-command
new file mode 100644
index 000000000000..8cbfbf965785
--- /dev/null
+++ b/test/Object/Inputs/macho-invalid-too-small-segment-load-command
diff --git a/test/Object/Inputs/macho-zero-ncmds b/test/Object/Inputs/macho-invalid-zero-ncmds
index 0505419195e9..0505419195e9 100644
--- a/test/Object/Inputs/macho-zero-ncmds
+++ b/test/Object/Inputs/macho-invalid-zero-ncmds
diff --git a/test/Object/Inputs/macho64-invalid-incomplete-load-command b/test/Object/Inputs/macho64-invalid-incomplete-load-command
new file mode 100644
index 000000000000..a569c9e14b3a
--- /dev/null
+++ b/test/Object/Inputs/macho64-invalid-incomplete-load-command
diff --git a/test/Object/Inputs/macho64-invalid-no-size-for-sections b/test/Object/Inputs/macho64-invalid-no-size-for-sections
new file mode 100644
index 000000000000..5aae5ffed3ae
--- /dev/null
+++ b/test/Object/Inputs/macho64-invalid-no-size-for-sections
diff --git a/test/Object/Inputs/macho64-invalid-too-small-load-command b/test/Object/Inputs/macho64-invalid-too-small-load-command
new file mode 100644
index 000000000000..0028451d1905
--- /dev/null
+++ b/test/Object/Inputs/macho64-invalid-too-small-load-command
diff --git a/test/Object/Inputs/macho64-invalid-too-small-segment-load-command b/test/Object/Inputs/macho64-invalid-too-small-segment-load-command
new file mode 100644
index 000000000000..ce6a20134a99
--- /dev/null
+++ b/test/Object/Inputs/macho64-invalid-too-small-segment-load-command
diff --git a/test/Object/Inputs/program-headers.mips b/test/Object/Inputs/program-headers.mips
index 54ebfea31f0c..e3485b223747 100755
--- a/test/Object/Inputs/program-headers.mips
+++ b/test/Object/Inputs/program-headers.mips
diff --git a/test/Object/Inputs/sectionGroup.elf.x86-64 b/test/Object/Inputs/sectionGroup.elf.x86-64
new file mode 100644
index 000000000000..b88ad0c596e6
--- /dev/null
+++ b/test/Object/Inputs/sectionGroup.elf.x86-64
diff --git a/test/Object/Inputs/trivial.ll b/test/Object/Inputs/trivial.ll
index 463442eb90ac..37a6bc20a8c2 100644
--- a/test/Object/Inputs/trivial.ll
+++ b/test/Object/Inputs/trivial.ll
@@ -2,7 +2,7 @@
 
 define i32 @main() nounwind {
 entry:
-  %call = tail call i32 @puts(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0)) nounwind
+  %call = tail call i32 @puts(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0)) nounwind
   tail call void bitcast (void (...)* @SomeOtherFunction to void ()*)() nounwind
   ret i32 0
 }
diff --git a/test/Object/Mips/abi-flags.yaml b/test/Object/Mips/abi-flags.yaml
new file mode 100644
index 000000000000..8a11fc4124c3
--- /dev/null
+++ b/test/Object/Mips/abi-flags.yaml
@@ -0,0 +1,63 @@
+# RUN: yaml2obj -format=elf %s > %t
+# RUN: llvm-readobj -mips-abi-flags %t | FileCheck -check-prefix=OBJ %s
+# RUN: obj2yaml %t | FileCheck -check-prefix=YAML %s
+
+# OBJ:      MIPS ABI Flags {
+# OBJ-NEXT:   Version: 0
+# OBJ-NEXT:   ISA: MIPS64r5
+# OBJ-NEXT:   ISA Extension: Cavium Networks Octeon3 (0x13)
+# OBJ-NEXT:   ASEs [ (0x103)
+# OBJ-NEXT:     DSP (0x1)
+# OBJ-NEXT:     DSPR2 (0x2)
+# OBJ-NEXT:     VZ (0x100)
+# OBJ-NEXT:   ]
+# OBJ-NEXT:   FP ABI: Hard float (double precision) (0x1)
+# OBJ-NEXT:   GPR size: 64
+# OBJ-NEXT:   CPR1 size: 64
+# OBJ-NEXT:   CPR2 size: 0
+# OBJ-NEXT:   Flags 1 [ (0x1)
+# OBJ-NEXT:     ODDSPREG (0x1)
+# OBJ-NEXT:   ]
+# OBJ-NEXT:   Flags 2: 0x0
+# OBJ-NEXT: }
+
+# YAML:      Sections:
+# YAML-NEXT: - Name:            .MIPS.abiflags
+# YAML-NEXT:   Type:            SHT_MIPS_ABIFLAGS
+# YAML-NEXT:   AddressAlign:    0x0000000000000008
+# YAML-NEXT:   ISA:             MIPS64
+# YAML-NEXT:   ISARevision:     0x05
+# YAML-NEXT:   ISAExtension:    EXT_OCTEON3
+# YAML-NEXT:   ASEs:            [ DSP, DSPR2, VIRT ]
+# YAML-NEXT:   FpABI:           FP_DOUBLE
+# YAML-NEXT:   GPRSize:         REG_64
+# YAML-NEXT:   CPR1Size:        REG_64
+# YAML-NEXT:   Flags1:          [ ODDSPREG ]
+
+FileHeader:
+  Class:   ELFCLASS64
+  Data:    ELFDATA2MSB
+  Type:    ET_REL
+  Machine: EM_MIPS
+
+Sections:
+- Name: .MIPS.abiflags
+  Type: SHT_MIPS_ABIFLAGS
+  AddressAlign: 8
+  Version:      0
+  ISA:          MIPS64
+  ISARevision:  5
+  ISAExtension: EXT_OCTEON3
+  ASEs:         [ DSP, DSPR2, VIRT ]
+  FpABI:        FP_DOUBLE
+  GPRSize:      REG_64
+  CPR1Size:     REG_64
+  CPR2Size:     REG_NONE
+  Flags1:       [ ODDSPREG ]
+  Flags2:       0x0
+
+Symbols:
+  Local:
+    - Name:    .MIPS.abiflags
+      Type:    STT_SECTION
+      Section: .MIPS.abiflags
diff --git a/test/Object/Mips/elf-abi.yaml b/test/Object/Mips/elf-abi.yaml
new file mode 100644
index 000000000000..5f11b14da596
--- /dev/null
+++ b/test/Object/Mips/elf-abi.yaml
@@ -0,0 +1,136 @@
+# RUN: yaml2obj -format=elf -docnum=1 %s > %t.o32
+# RUN: llvm-readobj -file-headers %t.o32 | FileCheck -check-prefix=O32OBJ %s
+# RUN: obj2yaml %t.o32 | FileCheck -check-prefix=O32YAML %s
+
+# O32OBJ:      Flags [ (0x50001002)
+# O32OBJ-NEXT:   EF_MIPS_ABI_O32 (0x1000)
+# O32OBJ-NEXT:   EF_MIPS_ARCH_32 (0x50000000)
+# O32OBJ-NEXT:   EF_MIPS_PIC (0x2)
+# O32OBJ-NEXT: ]
+
+# O32YAML:  Flags:  [ EF_MIPS_PIC, EF_MIPS_ABI_O32, EF_MIPS_ARCH_32 ]
+
+# RUN: yaml2obj -format=elf -docnum=2 %s > %t.o64
+# RUN: llvm-readobj -file-headers %t.o64 | FileCheck -check-prefix=O64OBJ %s
+# RUN: obj2yaml %t.o64 | FileCheck -check-prefix=O64YAML %s
+
+# O64OBJ:      Flags [ (0x60002002)
+# O64OBJ-NEXT:   EF_MIPS_ABI_O64 (0x2000)
+# O64OBJ-NEXT:   EF_MIPS_ARCH_64 (0x60000000)
+# O64OBJ-NEXT:   EF_MIPS_PIC (0x2)
+# O64OBJ-NEXT: ]
+
+# O64YAML:  Flags:  [ EF_MIPS_PIC, EF_MIPS_ABI_O64, EF_MIPS_ARCH_64 ]
+
+# RUN: yaml2obj -format=elf -docnum=3 %s > %t.eabi32
+# RUN: llvm-readobj -file-headers %t.eabi32 | FileCheck -check-prefix=E32OBJ %s
+# RUN: obj2yaml %t.eabi32 | FileCheck -check-prefix=E32YAML %s
+
+# E32OBJ:      Flags [ (0x50003002)
+# E32OBJ-NEXT:   EF_MIPS_ABI_EABI32 (0x3000)
+# E32OBJ-NEXT:   EF_MIPS_ARCH_32 (0x50000000)
+# E32OBJ-NEXT:   EF_MIPS_PIC (0x2)
+# E32OBJ-NEXT: ]
+
+# E32YAML:  Flags:  [ EF_MIPS_PIC, EF_MIPS_ABI_EABI32, EF_MIPS_ARCH_32 ]
+
+# RUN: yaml2obj -format=elf -docnum=4 %s > %t.eabi64
+# RUN: llvm-readobj -file-headers %t.eabi64 | FileCheck -check-prefix=E64OBJ %s
+# RUN: obj2yaml %t.eabi64 | FileCheck -check-prefix=E64YAML %s
+
+# E64OBJ:      Flags [ (0x60004002)
+# E64OBJ-NEXT:   EF_MIPS_ABI_EABI64 (0x4000)
+# E64OBJ-NEXT:   EF_MIPS_ARCH_64 (0x60000000)
+# E64OBJ-NEXT:   EF_MIPS_PIC (0x2)
+# E64OBJ-NEXT: ]
+
+# E64YAML:  Flags:  [ EF_MIPS_PIC, EF_MIPS_ABI_EABI64, EF_MIPS_ARCH_64 ]
+
+# o32
+---
+FileHeader:
+  Class:           ELFCLASS32
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_MIPS
+  Flags:           [ EF_MIPS_PIC, EF_MIPS_ABI_O32, EF_MIPS_ARCH_32 ]
+Sections:
+  - Name:            .text
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    16
+    Size:            4
+
+Symbols:
+  Global:
+    - Name:    T1
+      Section: .text
+      Value:   0
+      Size:    4
+
+# o64
+---
+FileHeader:
+  Class:           ELFCLASS64
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_MIPS
+  Flags:           [ EF_MIPS_PIC, EF_MIPS_ABI_O64, EF_MIPS_ARCH_64 ]
+Sections:
+  - Name:            .text
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    16
+    Size:            4
+
+Symbols:
+  Global:
+    - Name:    T1
+      Section: .text
+      Value:   0
+      Size:    4
+
+# eabio32
+---
+FileHeader:
+  Class:           ELFCLASS32
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_MIPS
+  Flags:           [ EF_MIPS_PIC, EF_MIPS_ABI_EABI32, EF_MIPS_ARCH_32 ]
+Sections:
+  - Name:            .text
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    16
+    Size:            4
+
+Symbols:
+  Global:
+    - Name:    T1
+      Section: .text
+      Value:   0
+      Size:    4
+
+# eabi64
+---
+FileHeader:
+  Class:           ELFCLASS64
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_MIPS
+  Flags:           [ EF_MIPS_PIC, EF_MIPS_ABI_EABI64, EF_MIPS_ARCH_64 ]
+Sections:
+  - Name:            .text
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    16
+    Size:            4
+
+Symbols:
+  Global:
+    - Name:    T1
+      Section: .text
+      Value:   0
+      Size:    4
+...
diff --git a/test/Object/Mips/elf-flags.yaml b/test/Object/Mips/elf-flags.yaml
new file mode 100644
index 000000000000..f79be9d4e078
--- /dev/null
+++ b/test/Object/Mips/elf-flags.yaml
@@ -0,0 +1,52 @@
+# RUN: yaml2obj -format=elf %s > %t
+# RUN: llvm-readobj -file-headers %t | FileCheck -check-prefix=OBJ %s
+# RUN: obj2yaml %t | FileCheck -check-prefix=YAML %s
+
+# OBJ:      Flags [ (0x9E8B1727)
+# OBJ-NEXT:   EF_MIPS_32BITMODE (0x100)
+# OBJ-NEXT:   EF_MIPS_ABI2 (0x20)
+# OBJ-NEXT:   EF_MIPS_ABI_O32 (0x1000)
+# OBJ-NEXT:   EF_MIPS_ARCH_32R6 (0x90000000)
+# OBJ-NEXT:   EF_MIPS_ARCH_ASE_M16 (0x4000000)
+# OBJ-NEXT:   EF_MIPS_ARCH_ASE_MDMX (0x8000000)
+# OBJ-NEXT:   EF_MIPS_CPIC (0x4)
+# OBJ-NEXT:   EF_MIPS_FP64 (0x200)
+# OBJ-NEXT:   EF_MIPS_MACH_OCTEON (0x8B0000)
+# OBJ-NEXT:   EF_MIPS_MICROMIPS (0x2000000)
+# OBJ-NEXT:   EF_MIPS_NAN2008 (0x400)
+# OBJ-NEXT:   EF_MIPS_NOREORDER (0x1)
+# OBJ-NEXT:   EF_MIPS_PIC (0x2)
+# OBJ-NEXT: ]
+
+# YAML:      FileHeader:
+# YAML-NEXT:   Class:           ELFCLASS32
+# YAML-NEXT:   Data:            ELFDATA2LSB
+# YAML-NEXT:   Type:            ET_REL
+# YAML-NEXT:   Machine:         EM_MIPS
+# YAML-NEXT:   Flags:           [ EF_MIPS_NOREORDER, EF_MIPS_PIC, EF_MIPS_CPIC, EF_MIPS_ABI2, EF_MIPS_32BITMODE, EF_MIPS_FP64, EF_MIPS_NAN2008, EF_MIPS_MICROMIPS, EF_MIPS_ARCH_ASE_M16, EF_MIPS_ARCH_ASE_MDMX, EF_MIPS_ABI_O32, EF_MIPS_MACH_OCTEON, EF_MIPS_ARCH_32R6 ]
+
+---
+FileHeader:
+  Class:    ELFCLASS32
+  Data:     ELFDATA2LSB
+  Type:     ET_REL
+  Machine:  EM_MIPS
+  Flags:    [ EF_MIPS_NOREORDER, EF_MIPS_PIC, EF_MIPS_CPIC, EF_MIPS_ABI2,
+              EF_MIPS_32BITMODE, EF_MIPS_FP64, EF_MIPS_NAN2008,
+              EF_MIPS_ABI_O32, EF_MIPS_ARCH_32R6,
+              EF_MIPS_MICROMIPS, EF_MIPS_ARCH_ASE_M16,
+              EF_MIPS_ARCH_ASE_MDMX, EF_MIPS_MACH_OCTEON ]
+Sections:
+  - Name:          .text
+    Type:          SHT_PROGBITS
+    Flags:         [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:  16
+    Size:          4
+
+Symbols:
+  Global:
+    - Name:    T1
+      Section: .text
+      Value:   0
+      Size:    4
+...
diff --git a/test/Object/Mips/elf-mips64-rel.yaml b/test/Object/Mips/elf-mips64-rel.yaml
new file mode 100644
index 000000000000..8b595099b9e5
--- /dev/null
+++ b/test/Object/Mips/elf-mips64-rel.yaml
@@ -0,0 +1,113 @@
+# RUN: yaml2obj -format=elf %s > %t
+# RUN: llvm-readobj -r %t | FileCheck -check-prefix=OBJ %s
+# RUN: obj2yaml %t | FileCheck -check-prefix=YAML %s
+
+# OBJ:      Relocations [
+# OBJ-NEXT:   Section (2) .rela.text {
+# OBJ-NEXT:     0x14 R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 main 0x4
+# OBJ-NEXT:     0x1C R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 main 0x8
+# OBJ-NEXT:     0x20 R_MIPS_GOT_PAGE/R_MIPS_NONE/R_MIPS_NONE .rodata 0x0
+# OBJ-NEXT:     0x24 R_MIPS_GOT_OFST/R_MIPS_NONE/R_MIPS_NONE .rodata 0x0
+# OBJ-NEXT:     0x28 R_MIPS_CALL16/R_MIPS_NONE/R_MIPS_NONE printf 0x0
+# OBJ-NEXT:     0x30 R_MIPS_GPREL16/R_MIPS_LO16/R_MIPS_NONE printf 0x0
+# OBJ-NEXT:   }
+# OBJ-NEXT: ]
+
+# YAML:      Relocations:
+# YAML-NEXT:   - Offset:      0x0000000000000014
+# YAML-NEXT:     Symbol:      main
+# YAML-NEXT:     Type:        R_MIPS_GPREL16
+# YAML-NEXT:     Type2:       R_MIPS_SUB
+# YAML-NEXT:     Type3:       R_MIPS_HI16
+# YAML-NEXT:     Addend:      4
+# YAML-NEXT:   - Offset:      0x000000000000001C
+# YAML-NEXT:     Symbol:      main
+# YAML-NEXT:     Type:        R_MIPS_GPREL16
+# YAML-NEXT:     Type2:       R_MIPS_SUB
+# YAML-NEXT:     Type3:       R_MIPS_LO16
+# YAML-NEXT:     Addend:      8
+# YAML-NEXT:   - Offset:      0x0000000000000020
+# YAML-NEXT:     Symbol:      .rodata
+# YAML-NEXT:     Type:        R_MIPS_GOT_PAGE
+# YAML-NEXT:   - Offset:      0x0000000000000024
+# YAML-NEXT:     Symbol:      .rodata
+# YAML-NEXT:     Type:        R_MIPS_GOT_OFST
+# YAML-NEXT:   - Offset:      0x0000000000000028
+# YAML-NEXT:     Symbol:      printf
+# YAML-NEXT:     Type:        R_MIPS_CALL16
+# YAML-NEXT:   - Offset:      0x0000000000000030
+# YAML-NEXT:     Symbol:      printf
+# YAML-NEXT:     Type:        R_MIPS_GPREL16
+# YAML-NEXT:     Type2:       R_MIPS_LO16
+# YAML-NEXT:     SpecSym:     RSS_GP0
+
+---
+FileHeader:
+  Class:           ELFCLASS64
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_MIPS
+  Flags:           [ EF_MIPS_PIC, EF_MIPS_CPIC,
+                     EF_MIPS_NOREORDER, EF_MIPS_ARCH_64R2 ]
+Sections:
+  - Name:            .text
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x10
+    Size:            0x60
+  - Name:            .rela.text
+    Type:            SHT_RELA
+    Flags:           [ SHF_INFO_LINK ]
+    Info:            .text
+    Relocations:
+      - Offset:      0x14
+        Symbol:      main
+        Type:        R_MIPS_GPREL16
+        Type2:       R_MIPS_SUB
+        Type3:       R_MIPS_HI16
+        Addend:      4
+      - Offset:      0x1C
+        Symbol:      main
+        Type:        R_MIPS_GPREL16
+        Type2:       R_MIPS_SUB
+        Type3:       R_MIPS_LO16
+        Addend:      8
+      - Offset:      0x20
+        Symbol:      .rodata
+        Type:        R_MIPS_GOT_PAGE
+        Addend:      0
+      - Offset:      0x24
+        Symbol:      .rodata
+        Type:        R_MIPS_GOT_OFST
+        Addend:      0
+      - Offset:      0x28
+        Symbol:      printf
+        Type:        R_MIPS_CALL16
+        Addend:      0
+      - Offset:      0x30
+        Symbol:      printf
+        Type:        R_MIPS_GPREL16
+        Type2:       R_MIPS_LO16
+        SpecSym:     RSS_GP0
+        Addend:      0
+  - Name:            .rodata
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC ]
+    AddressAlign:    0x10
+    Size:            0x0F
+
+Symbols:
+  Local:
+    - Name:            .text
+      Type:            STT_SECTION
+      Section:         .text
+    - Name:            .rodata
+      Type:            STT_SECTION
+      Section:         .rodata
+  Global:
+    - Name:            main
+      Type:            STT_FUNC
+      Section:         .text
+      Size:            0x58
+    - Name:            printf
+...
diff --git a/test/Object/archive-delete.test b/test/Object/archive-delete.test
index 552b0e709f61..c8530beafce4 100644
--- a/test/Object/archive-delete.test
+++ b/test/Object/archive-delete.test
@@ -1,7 +1,5 @@
 Test the 'd' operation in llvm-ar
 
-REQUIRES: shell
-
 RUN: cd %T
 
 RUN: rm -f %t.a
diff --git a/test/Object/archive-extract-dir.test b/test/Object/archive-extract-dir.test
index c718f90275b6..5182a2f91411 100644
--- a/test/Object/archive-extract-dir.test
+++ b/test/Object/archive-extract-dir.test
@@ -1,5 +1,3 @@
-REQUIRES: shell
-
 RUN: mkdir -p %t
 RUN: cd %t
 RUN: rm -rf foo
@@ -10,4 +8,4 @@ RUN: rm foo
 RUN: mkdir foo
 RUN: not llvm-ar x test.a foo 2>&1 | FileCheck %s
 
-CHECK: foo: Is a directory
+CHECK: foo: {{[Ii]}}s a directory
diff --git a/test/Object/archive-format.test b/test/Object/archive-format.test
index 20ac1a0d78fb..f076123d2ea1 100644
--- a/test/Object/archive-format.test
+++ b/test/Object/archive-format.test
@@ -1,13 +1,11 @@
 Test the exact archive format. In particular, test which file names use the
 string table or not.
 
-REQUIRES: shell
-
 RUN: mkdir -p %t
 RUN: cd %t
 
-RUN: echo bar > 0123456789abcde
-RUN: echo zed > 0123456789abcdef
+RUN: echo -n bar. > 0123456789abcde
+RUN: echo -n zed. > 0123456789abcdef
 
 RUN: rm -f test.a
 RUN: llvm-ar rc test.a 0123456789abcde 0123456789abcdef
@@ -17,6 +15,5 @@ CHECK:      !<arch>
 CHECK-NEXT: //                                              18        `
 CHECK-NEXT: 0123456789abcdef/
 CHECK-NEXT: 0123456789abcde/{{................................}}4         `
-CHECK-NEXT: bar
-CHECK-NEXT: /0              {{................................}}4         `
-CHECK-NEXT: zed
+CHECK-NEXT: bar./0              {{................................}}4         `
+CHECK-NEXT: zed.
diff --git a/test/Object/archive-move.test b/test/Object/archive-move.test
index 0378e9111a96..adc114994d28 100644
--- a/test/Object/archive-move.test
+++ b/test/Object/archive-move.test
@@ -1,7 +1,5 @@
 Test the 'm' operation in llvm-ar
 
-REQUIRES: shell
-
 RUN: cd %T
 
 RUN: rm -f %t.a
diff --git a/test/Object/archive-update.test b/test/Object/archive-update.test
index 20286d2669ad..91ca8102c7e1 100644
--- a/test/Object/archive-update.test
+++ b/test/Object/archive-update.test
@@ -1,7 +1,5 @@
 Test the 'u' option of llvm-ar
 
-REQUIRES: shell
-
 RUN: cd %T
 RUN: rm -f %t.a
 
diff --git a/test/Object/elf-unknown-type.test b/test/Object/elf-unknown-type.test
new file mode 100644
index 000000000000..9993c096376c
--- /dev/null
+++ b/test/Object/elf-unknown-type.test
@@ -0,0 +1,10 @@
+# RUN: yaml2obj -format=elf %s | llvm-readobj -file-headers - | FileCheck %s
+
+!ELF
+FileHeader: !FileHeader
+  Class: ELFCLASS64
+  Data: ELFDATA2LSB
+  Type: 42
+  Machine: EM_X86_64
+
+# CHECK: Type: 0x2A
diff --git a/test/Object/extract.ll b/test/Object/extract.ll
index a4e76499ca6c..8d77f09fe88c 100644
--- a/test/Object/extract.ll
+++ b/test/Object/extract.ll
@@ -3,8 +3,6 @@
 ; This test just makes sure that llvm-ar can extract bytecode members
 ; from various style archives.
 
-; REQUIRES: shell
-
 ; RUN: cd %T
 
 ; RUN: rm -f very_long_bytecode_file_name.bc
diff --git a/test/Object/kext.test b/test/Object/kext.test
new file mode 100644
index 000000000000..8e7c3d148719
--- /dev/null
+++ b/test/Object/kext.test
@@ -0,0 +1,7 @@
+// Check that we understand kext bundles.
+// Test input generated by "clang -x c++ -fapple-kext -Wl,-kext /dev/null"
+
+RUN: llvm-readobj %p/Inputs/macho-empty-kext-bundle-x86-64 | FileCheck %s
+CHECK: Format: Mach-O 64-bit x86-64
+CHECK: Arch: x86_64
+CHECK: AddressSize: 64bit
diff --git a/test/Object/macho-invalid.test b/test/Object/macho-invalid.test
new file mode 100644
index 000000000000..e2c9b6b7360e
--- /dev/null
+++ b/test/Object/macho-invalid.test
@@ -0,0 +1,38 @@
+// No crash, might not be totally invalid
+RUN: llvm-objdump -private-headers %p/Inputs/macho-invalid-zero-ncmds
+
+RUN: not llvm-objdump -private-headers %p/Inputs/macho64-invalid-incomplete-load-command 2>&1 \
+RUN:      | FileCheck -check-prefix INCOMPLETE-LOADC %s
+
+RUN: not llvm-objdump -private-headers %p/Inputs/macho-invalid-too-small-load-command 2>&1 \
+RUN:      | FileCheck -check-prefix SMALL-LOADC-SIZE %s
+RUN: not llvm-objdump -private-headers %p/Inputs/macho64-invalid-too-small-load-command 2>&1 \
+RUN:      | FileCheck -check-prefix SMALL-LOADC-SIZE %s
+
+RUN: not llvm-objdump -private-headers %p/Inputs/macho-invalid-too-small-segment-load-command 2>&1 \
+RUN:      | FileCheck -check-prefix SMALL-SEGLOADC-SIZE %s
+RUN: not llvm-objdump -private-headers %p/Inputs/macho64-invalid-too-small-segment-load-command 2>&1 \
+RUN:      | FileCheck -check-prefix SMALL-SEGLOADC-SIZE %s
+
+RUN: not llvm-objdump -private-headers %p/Inputs/macho-invalid-no-size-for-sections 2>&1 \
+RUN:      | FileCheck -check-prefix TOO-MANY-SECTS %s
+RUN: not llvm-objdump -private-headers %p/Inputs/macho64-invalid-no-size-for-sections 2>&1 \
+RUN:      | FileCheck -check-prefix TOO-MANY-SECTS %s
+
+RUN: not llvm-objdump -t %p/Inputs/macho-invalid-bad-symbol-index 2>&1 \
+RUN:      | FileCheck -check-prefix BAD-SYMBOL %s
+
+RUN: not llvm-objdump -t %p/Inputs/macho-invalid-symbol-name-past-eof 2>&1 \
+RUN:      | FileCheck -check-prefix NAME-PAST-EOF %s
+
+RUN: not llvm-nm %p/Inputs/macho-invalid-section-index-getSectionRawName 2>&1 \
+RUN:      | FileCheck -check-prefix INVALID-SECTION-IDX-SYMBOL-SEC %s
+
+SMALL-LOADC-SIZE: Load command with size < 8 bytes
+SMALL-SEGLOADC-SIZE: Segment load command size is too small
+INCOMPLETE-LOADC: Malformed MachO file
+TOO-MANY-SECTS: Number of sections too large for size of load command
+BAD-SYMBOL: Requested symbol index is out of range
+NAME-PAST-EOF: Symbol name entry points before beginning or past end of file
+
+INVALID-SECTION-IDX-SYMBOL-SEC: getSymbolSection: Invalid section index
diff --git a/test/Object/nm-irix6.test b/test/Object/nm-irix6.test
new file mode 100644
index 000000000000..047665cbf32b
--- /dev/null
+++ b/test/Object/nm-irix6.test
@@ -0,0 +1,27 @@
+# Check reading IRIX 6.0 64-bit archive file.
+RUN: llvm-nm %p/Inputs/archive-test.a-irix6-mips64el | FileCheck %s
+
+CHECK:      f1.o:
+CHECK-NEXT: 00000028 T f1
+CHECK-NEXT: 00000000 d s_d
+CHECK-NEXT: 00000000 t s_foo
+
+CHECK:      f2.o:
+CHECK-NEXT: 00000028 T f2
+CHECK-NEXT: 00000000 d s_d
+CHECK-NEXT: 00000000 t s_foo
+
+CHECK:      f3.o:
+CHECK-NEXT: 00000028 T f3
+CHECK-NEXT: 00000000 d s_d
+CHECK-NEXT: 00000000 t s_foo
+
+CHECK:      f4.o:
+CHECK-NEXT: 00000028 T f4
+CHECK-NEXT: 00000000 d s_d
+CHECK-NEXT: 00000000 t s_foo
+
+CHECK:      f5.o:
+CHECK-NEXT: 00000028 T f5
+CHECK-NEXT: 00000000 d s_d
+CHECK-NEXT: 00000000 t s_foo
diff --git a/test/Object/nm-trivial-object.test b/test/Object/nm-trivial-object.test
index 0135f2df3cb0..def6549d6563 100644
--- a/test/Object/nm-trivial-object.test
+++ b/test/Object/nm-trivial-object.test
@@ -1,9 +1,11 @@
 RUN: yaml2obj %p/Inputs/COFF/i386.yaml | llvm-nm -a -S - \
-RUN:         | FileCheck %s -check-prefix COFF
+RUN:         | FileCheck %s -check-prefix COFF32
 RUN: yaml2obj %p/Inputs/COFF/x86-64.yaml | llvm-nm -a -S - \
-RUN:         | FileCheck %s -check-prefix COFF
+RUN:         | FileCheck %s -check-prefix COFF64
 RUN: llvm-nm %p/Inputs/trivial-object-test.elf-i386 \
 RUN:         | FileCheck %s -check-prefix ELF
+RUN: llvm-nm %p/Inputs/trivial-object-test.elf-i386 -S \
+RUN:         | FileCheck %s -check-prefix ELF-SIZE
 RUN: llvm-nm -o %p/Inputs/trivial-object-test.elf-i386 \
 RUN:         | FileCheck %s -check-prefix ELF-o
 RUN: llvm-nm -u %p/Inputs/trivial-object-test.elf-i386 \
@@ -46,23 +48,30 @@ RUN: mkdir -p %t
 RUN: cd %t
 RUN: cp %p/Inputs/trivial-object-test.macho-i386 a.out
 RUN: llvm-nm | FileCheck %s -check-prefix A-OUT
-REQUIRES: shell
 
 
-COFF: 00000000 {{.*}} d .data
-COFF: 00000000 {{.*}} t .text
-COFF: 00000000 0000000d d L{{_?}}.str
-COFF:          U {{_?}}SomeOtherFunction
-COFF: 00000000 {{.*}} T {{_?}}main
-COFF:          U {{_?}}puts
+COFF32: 00000000 d .data
+COFF32-NEXT: 00000000 t .text
+COFF32-NEXT: 00000000 d L_.str
+COFF32-NEXT:          U _SomeOtherFunction
+COFF32-NEXT: 00000000 T _main
+COFF32-NEXT:          U _puts
 
-COFF-COMMON: 00000000 00000000 b .bss
-COFF-COMMON-NEXT: 00000000 00000000 d .data
-COFF-COMMON-NEXT: 00000000 00000014 d .drectve
-COFF-COMMON-NEXT: 00000000 00000000 n .file
-COFF-COMMON-NEXT: 00000000 00000014 r .rdata$zzz
-COFF-COMMON-NEXT: 00000000 00000000 t .text
-COFF-COMMON-NEXT:          00000004 C _a
+COFF64: 00000000 d .data
+COFF64-NEXT: 00000000 t .text
+COFF64-NEXT: 00000000 r ??__Ex@@YAXXZ
+COFF64-NEXT: 00000000 d L.str
+COFF64-NEXT:          U SomeOtherFunction
+COFF64-NEXT: 00000000 T main
+COFF64-NEXT:          U puts
+
+COFF-COMMON: 00000000 b .bss
+COFF-COMMON-NEXT: 00000000 d .data
+COFF-COMMON-NEXT: 00000000 d .drectve
+COFF-COMMON-NEXT: 00000000 n .file
+COFF-COMMON-NEXT: 00000000 r .rdata$zzz
+COFF-COMMON-NEXT: 00000000 t .text
+COFF-COMMON-NEXT:          C _a
 
 
 ELF-NOT:      U
@@ -70,6 +79,11 @@ ELF:          U SomeOtherFunction
 ELF: 00000000 T main
 ELF:          U puts
 
+FIXME: we should not print the size of undefined symbols.
+ELF-SIZE:               00000000 U SomeOtherFunction
+ELF-SIZE-NEXT: 00000000 00000024 T main
+ELF-SIZE-NEXT:          00000000 U puts
+
 ELF-o: {{.*}}/trivial-object-test.elf-i386:          U SomeOtherFunction
 ELF-o: {{.*}}/trivial-object-test.elf-i386: 00000000 T main
 ELF-o: {{.*}}/trivial-object-test.elf-i386:          U puts
diff --git a/test/Object/obj2yaml-sectiongroup.test b/test/Object/obj2yaml-sectiongroup.test
new file mode 100644
index 000000000000..66e8e3875be2
--- /dev/null
+++ b/test/Object/obj2yaml-sectiongroup.test
@@ -0,0 +1,26 @@
+# Checks that the tool is able to read section groups with ELF.
+RUN: obj2yaml %p/Inputs/sectionGroup.elf.x86-64 > %t1.sectiongroup.yaml
+RUN: FileCheck %s --check-prefix ELF-GROUP < %t1.sectiongroup.yaml
+RUN: yaml2obj -format=elf %t1.sectiongroup.yaml -o %t2.o.elf
+RUN: llvm-readobj -sections %t2.o.elf | FileCheck %s -check-prefix=SECTIONS
+#ELF-GROUP:  - Name:            .group
+#ELF-GROUP:    Type:            SHT_GROUP
+#ELF-GROUP:    Link:            .symtab
+#ELF-GROUP:    Info:            a
+#ELF-GROUP:    Members:
+#ELF-GROUP:      - SectionOrType:   GRP_COMDAT
+#ELF-GROUP:      - SectionOrType:   .rodata.a
+#SECTIONS: Format: ELF64-x86-64
+#SECTIONS: Arch: x86_64
+#SECTIONS: AddressSize: 64bit
+#SECTIONS:   Section {
+#SECTIONS:     Index: 1
+#SECTIONS:     Name: .group (21)
+#SECTIONS:     Type: SHT_GROUP (0x11)
+#SECTIONS:     Flags [ (0x0)
+#SECTIONS:     ]
+#SECTIONS:     Address: 0x0
+#SECTIONS:     Size: 8
+#SECTIONS:     AddressAlignment: 4
+#SECTIONS:     EntrySize: 4
+#SECTIONS:   }
diff --git a/test/Object/obj2yaml.test b/test/Object/obj2yaml.test
index 1c79e98fdc3b..2a3f7c841dd1 100644
--- a/test/Object/obj2yaml.test
+++ b/test/Object/obj2yaml.test
@@ -210,27 +210,21 @@ ELF-MIPSEL-NEXT:     Relocations:
 ELF-MIPSEL-NEXT:       - Offset:          0x0000000000000000
 ELF-MIPSEL-NEXT:         Symbol:          _gp_disp
 ELF-MIPSEL-NEXT:         Type:            R_MIPS_HI16
-ELF-MIPSEL-NEXT:         Addend:          0
 ELF-MIPSEL-NEXT:       - Offset:          0x0000000000000004
 ELF-MIPSEL-NEXT:         Symbol:          _gp_disp
 ELF-MIPSEL-NEXT:         Type:            R_MIPS_LO16
-ELF-MIPSEL-NEXT:         Addend:          0
 ELF-MIPSEL-NEXT:       - Offset:          0x0000000000000018
 ELF-MIPSEL-NEXT:         Symbol:          '$.str'
 ELF-MIPSEL-NEXT:         Type:            R_MIPS_GOT16
-ELF-MIPSEL-NEXT:         Addend:          0
 ELF-MIPSEL-NEXT:       - Offset:          0x000000000000001C
 ELF-MIPSEL-NEXT:         Symbol:          '$.str'
 ELF-MIPSEL-NEXT:         Type:            R_MIPS_LO16
-ELF-MIPSEL-NEXT:         Addend:          0
 ELF-MIPSEL-NEXT:       - Offset:          0x0000000000000020
 ELF-MIPSEL-NEXT:         Symbol:          puts
 ELF-MIPSEL-NEXT:         Type:            R_MIPS_CALL16
-ELF-MIPSEL-NEXT:         Addend:          0
 ELF-MIPSEL-NEXT:       - Offset:          0x000000000000002C
 ELF-MIPSEL-NEXT:         Symbol:          SomeOtherFunction
 ELF-MIPSEL-NEXT:         Type:            R_MIPS_CALL16
-ELF-MIPSEL-NEXT:         Addend:          0
 ELF-MIPSEL-NEXT:   - Name:            .data
 ELF-MIPSEL-NEXT:     Type:            SHT_PROGBITS
 ELF-MIPSEL-NEXT:     Flags:           [ SHF_WRITE, SHF_ALLOC ]
@@ -259,7 +253,12 @@ ELF-MIPSEL-NEXT:   - Name:            .MIPS.abiflags
 ELF-MIPSEL-NEXT:     Type:            SHT_MIPS_ABIFLAGS
 ELF-MIPSEL-NEXT:     Flags:           [ SHF_ALLOC ]
 ELF-MIPSEL-NEXT:     AddressAlign:    0x0000000000000008
-ELF-MIPSEL-NEXT:     Content:         '000020010101000100000000000000000100000000000000'
+ELF-MIPSEL-NEXT:     ISA:             MIPS32
+ELF-MIPSEL-NEXT:     ISARevision:     0x01
+ELF-MIPSEL-NEXT:     FpABI:           FP_DOUBLE
+ELF-MIPSEL-NEXT:     GPRSize:         REG_32
+ELF-MIPSEL-NEXT:     CPR1Size:        REG_32
+ELF-MIPSEL-NEXT:     Flags1:          [ ODDSPREG ]
 ELF-MIPSEL-NEXT: Symbols:
 ELF-MIPSEL-NEXT:   Local:
 ELF-MIPSEL-NEXT:     - Name:            trivial.ll
@@ -328,7 +327,6 @@ ELF-MIPS64EL-NEXT:     Relocations:
 ELF-MIPS64EL-NEXT:       - Offset:          0
 ELF-MIPS64EL-NEXT:         Symbol:          zed
 ELF-MIPS64EL-NEXT:         Type:            R_MIPS_64
-ELF-MIPS64EL-NEXT:         Addend:          0
 ELF-MIPS64EL-NEXT:   - Name:            .bss
 ELF-MIPS64EL-NEXT:     Type:            SHT_NOBITS
 ELF-MIPS64EL-NEXT:     Flags:           [ SHF_WRITE, SHF_ALLOC ]
@@ -398,7 +396,6 @@ ELF-X86-64-NEXT:     Relocations:
 ELF-X86-64-NEXT:       - Offset:          0x000000000000000D
 ELF-X86-64-NEXT:         Symbol:          .rodata.str1.1
 ELF-X86-64-NEXT:         Type:            R_X86_64_32S
-ELF-X86-64-NEXT:         Addend:          0
 ELF-X86-64-NEXT:       - Offset:          0x0000000000000012
 ELF-X86-64-NEXT:         Symbol:          puts
 ELF-X86-64-NEXT:         Type:            R_X86_64_PC32
diff --git a/test/Object/objdump-macho-quirks.test b/test/Object/objdump-macho-quirks.test
deleted file mode 100644
index eeee1537def7..000000000000
--- a/test/Object/objdump-macho-quirks.test
+++ /dev/null
@@ -1,9 +0,0 @@
-RUN: llvm-objdump -private-headers %p/Inputs/macho-zero-ncmds \
-RUN:         | FileCheck %s -check-prefix A
-
-// Check that we don't get an infinite loop if ncmds = 0
-A: file format Mach-O 64-bit unknown
-A: Mach header
-A:      magic cputype cpusubtype  caps    filetype ncmds sizeofcmds      flags
-A: MH_MAGIC_64  0x00      OBJECT     0          0 0x00000000
-
diff --git a/test/Object/objdump-symbol-table.test b/test/Object/objdump-symbol-table.test
index c94b07773550..3d09e1a45f39 100644
--- a/test/Object/objdump-symbol-table.test
+++ b/test/Object/objdump-symbol-table.test
@@ -30,12 +30,14 @@ ELF-i386: 00000000         *UND*  00000000 puts
 
 macho-i386: trivial-object-test.macho-i386:        file format Mach-O 32-bit i386
 macho-i386: SYMBOL TABLE:
-macho-i386: 00000000 g     F __TEXT,__text  00000024 _main
+macho-i386: 00000000 g     F __TEXT,__text  00000000 _main
 macho-i386: 00000000         *UND*  00000000 _SomeOtherFunction
 macho-i386: 00000000         *UND*  00000000 _puts
 
 ELF-shared: shared-object-test.elf-i386:     file format
 ELF-shared: SYMBOL TABLE:
 ELF-shared: 00000200 l     F .text 00000003 local_func
+ELF-shared: 000012b8 l       *ABS* 00000000 .hidden _GLOBAL_OFFSET_TABLE_
+ELF-shared: 00001248 l       *ABS* 00000000 .hidden _DYNAMIC
 ELF-shared: 000012c4 g       .data 00000004 defined_sym
 ELF-shared: 000001f0 g     F .text 00000003 global_func
diff --git a/test/Object/yaml2obj-elf-rel-noref.yaml b/test/Object/yaml2obj-elf-rel-noref.yaml
new file mode 100644
index 000000000000..69fcf0854434
--- /dev/null
+++ b/test/Object/yaml2obj-elf-rel-noref.yaml
@@ -0,0 +1,77 @@
+# RUN: yaml2obj -format=elf %s | llvm-readobj -sections -relocations - | FileCheck %s
+
+!ELF
+FileHeader:        !FielHeader
+  Class:           ELFCLASS32
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_ARM
+  Flags:           [ EF_ARM_EABI_VER5 ]
+Sections:        
+  - Name:            .text
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000004
+    Content:         03308FE0022093E7000052E31EFF2F01
+  - Name:            .rel.text
+    Type:            SHT_REL
+    Flags:           [ SHF_INFO_LINK ]
+    Link:            .symtab
+    AddressAlign:    0x0000000000000004
+    Info:            .text
+    Relocations:     
+      - Offset:          0x000000000000000C
+        Symbol:          ''
+        Type:            R_ARM_V4BX
+  - Name:            .data
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_WRITE, SHF_ALLOC ]
+    AddressAlign:    0x0000000000000001
+    Content:         ''
+  - Name:            .bss
+    Type:            SHT_NOBITS
+    Flags:           [ SHF_WRITE, SHF_ALLOC ]
+    AddressAlign:    0x0000000000000001
+    Content:         ''
+  - Name:            .ARM.attributes
+    Type:            SHT_ARM_ATTRIBUTES
+    AddressAlign:    0x0000000000000001
+    Content:         4115000000616561626900010B000000060208010901
+Symbols:         
+  Local:           
+    - Name:            .text
+      Type:            STT_SECTION
+      Section:         .text
+    - Name:            .data
+      Type:            STT_SECTION
+      Section:         .data
+    - Name:            .bss
+      Type:            STT_SECTION
+      Section:         .bss
+    - Name:            '$a'
+      Section:         .text
+    - Name:            call_weak_fn
+      Type:            STT_FUNC
+      Section:         .text
+    - Name:            .ARM.attributes
+      Type:            STT_SECTION
+      Section:         .ARM.attributes
+
+# CHECK:        Section {
+# CHECK-NEXT:     Index: 0
+# CHECK:        }
+# CHECK:        Section {
+# CHECK-NEXT:     Index: 1
+# CHECK-NEXT:     Name: .text (5)
+# CHECK:        }
+# CHECK-NEXT:   Section {
+# CHECK-NEXT:     Index: 2
+# CHECK-NEXT:     Name: .rel.text (1)
+# CHECK-NEXT:     Type: SHT_REL (0x9)
+# CHECK-NEXT:     Flags [ (0x40)
+# CHECK:	}
+# CHECK:        Relocations [
+# CHECK-NEXT:     Section (2) .rel.text {
+# CHECK-NEXT:       0xC R_ARM_V4BX - 0x0
+# CHECK-NEXT:     }
+# CHECK-NEXT:   ]
diff --git a/test/Other/2004-08-16-PackedGlobalConstant.ll b/test/Other/2004-08-16-PackedGlobalConstant.ll
index 9130ccba1736..4f15c9ef4273 100644
--- a/test/Other/2004-08-16-PackedGlobalConstant.ll
+++ b/test/Other/2004-08-16-PackedGlobalConstant.ll
@@ -4,7 +4,7 @@
 @bar = external global <2 x i32>                ; <<2 x i32>*> [#uses=1]
 
 define void @main() {
-        %t0 = load <2 x i32>* @foo              ; <<2 x i32>> [#uses=1]
+        %t0 = load <2 x i32>, <2 x i32>* @foo              ; <<2 x i32>> [#uses=1]
         store <2 x i32> %t0, <2 x i32>* @bar
         ret void
 }
diff --git a/test/Other/2004-08-16-PackedSelect.ll b/test/Other/2004-08-16-PackedSelect.ll
index c1d6214dc63d..1d0e7aab3009 100644
--- a/test/Other/2004-08-16-PackedSelect.ll
+++ b/test/Other/2004-08-16-PackedSelect.ll
@@ -4,7 +4,7 @@
 @bar = external global <4 x float>              ; <<4 x float>*> [#uses=1]
 
 define void @main() {
-        %t0 = load <4 x float>* @foo            ; <<4 x float>> [#uses=3]
+        %t0 = load <4 x float>, <4 x float>* @foo            ; <<4 x float>> [#uses=3]
         %t1 = fadd <4 x float> %t0, %t0          ; <<4 x float>> [#uses=1]
         %t2 = select i1 true, <4 x float> %t0, <4 x float> %t1          ; <<4 x float>> [#uses=1]
         store <4 x float> %t2, <4 x float>* @bar
diff --git a/test/Other/2004-08-16-PackedSimple.ll b/test/Other/2004-08-16-PackedSimple.ll
index 81cecd4235fc..3923c9648ecf 100644
--- a/test/Other/2004-08-16-PackedSimple.ll
+++ b/test/Other/2004-08-16-PackedSimple.ll
@@ -4,7 +4,7 @@
 @bar = external global <4 x float>              ; <<4 x float>*> [#uses=1]
 
 define void @main() {
-        %t0 = load <4 x float>* @foo            ; <<4 x float>> [#uses=3]
+        %t0 = load <4 x float>, <4 x float>* @foo            ; <<4 x float>> [#uses=3]
         %t2 = fadd <4 x float> %t0, %t0          ; <<4 x float>> [#uses=1]
         %t3 = select i1 false, <4 x float> %t0, <4 x float> %t2         ; <<4 x float>> [#uses=1]
         store <4 x float> %t3, <4 x float>* @bar
diff --git a/test/Other/2004-08-20-PackedControlFlow.ll b/test/Other/2004-08-20-PackedControlFlow.ll
index 39435706934f..64da59d13b2b 100644
--- a/test/Other/2004-08-20-PackedControlFlow.ll
+++ b/test/Other/2004-08-20-PackedControlFlow.ll
@@ -16,7 +16,7 @@ B:              ; preds = %A
         br label %C
 
 A:              ; preds = %0
-        %t0 = load %v4f* @foo           ; <%v4f> [#uses=2]
+        %t0 = load %v4f, %v4f* @foo           ; <%v4f> [#uses=2]
         br label %B
 }
 
diff --git a/test/Other/2007-09-10-PassManager.ll b/test/Other/2007-09-10-PassManager.ll
index ded15e569511..39af0d046aef 100644
--- a/test/Other/2007-09-10-PassManager.ll
+++ b/test/Other/2007-09-10-PassManager.ll
@@ -8,15 +8,15 @@ entry:
 	br label %bb3
 
 bb:		; preds = %bb3
-	%tmp = load i32* %i, align 4		; <i32> [#uses=1]
+	%tmp = load i32, i32* %i, align 4		; <i32> [#uses=1]
 	call void @bar( i32 %tmp )
-	%tmp1 = load i32* %i, align 4		; <i32> [#uses=1]
+	%tmp1 = load i32, i32* %i, align 4		; <i32> [#uses=1]
 	%tmp2 = add i32 %tmp1, 1		; <i32> [#uses=1]
 	store i32 %tmp2, i32* %i, align 4
 	br label %bb3
 
 bb3:		; preds = %bb, %entry
-	%tmp4 = load i32* %i, align 4		; <i32> [#uses=1]
+	%tmp4 = load i32, i32* %i, align 4		; <i32> [#uses=1]
 	%tmp5 = icmp sle i32 %tmp4, 9		; <i1> [#uses=1]
 	%tmp56 = zext i1 %tmp5 to i8		; <i8> [#uses=1]
 	%toBool = icmp ne i8 %tmp56, 0		; <i1> [#uses=1]
diff --git a/test/Other/2008-06-04-FieldSizeInPacked.ll b/test/Other/2008-06-04-FieldSizeInPacked.ll
index d90209f6af36..d2532553752b 100644
--- a/test/Other/2008-06-04-FieldSizeInPacked.ll
+++ b/test/Other/2008-06-04-FieldSizeInPacked.ll
@@ -7,8 +7,8 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define i1 @q() nounwind  {
 entry:
-	%char_p = getelementptr %packed* null, i32 0, i32 1		; <i8*> [#uses=1]
-	%char_u = getelementptr %unpacked* null, i32 0, i32 1		; <i8*> [#uses=1]
+	%char_p = getelementptr %packed, %packed* null, i32 0, i32 1		; <i8*> [#uses=1]
+	%char_u = getelementptr %unpacked, %unpacked* null, i32 0, i32 1		; <i8*> [#uses=1]
 	%res = icmp eq i8* %char_p, %char_u		; <i1> [#uses=1]
 	ret i1 %res
 }
diff --git a/test/Other/2009-03-31-CallGraph.ll b/test/Other/2009-03-31-CallGraph.ll
index 864903cffba2..1e1783084649 100644
--- a/test/Other/2009-03-31-CallGraph.ll
+++ b/test/Other/2009-03-31-CallGraph.ll
@@ -7,6 +7,8 @@ ok1:
     ret void
 
 lpad1:
+    landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
+            cleanup
     invoke void @f4()
         to label %ok2 unwind label %lpad2
 
diff --git a/test/Other/Inputs/utf8-bom-response b/test/Other/Inputs/utf8-bom-response
new file mode 100644
index 000000000000..9dae3158ecdb
--- /dev/null
+++ b/test/Other/Inputs/utf8-bom-response
@@ -0,0 +1 @@
+-help
diff --git a/test/Other/Inputs/utf8-response b/test/Other/Inputs/utf8-response
new file mode 100644
index 000000000000..97f455ac44e7
--- /dev/null
+++ b/test/Other/Inputs/utf8-response
@@ -0,0 +1 @@
+-help
diff --git a/test/Other/ResponseFile.ll b/test/Other/ResponseFile.ll
index 914e5480f203..92648b86f5fb 100644
--- a/test/Other/ResponseFile.ll
+++ b/test/Other/ResponseFile.ll
@@ -6,6 +6,11 @@
 ; RUN: llvm-as @%t.list2 -o %t.bc
 ; RUN: llvm-nm %t.bc 2>&1 | FileCheck %s
 
+; When the response file begins with UTF8 BOM sequence, we shall remove them.
+; Neither command below should return a "Could not open input file" error.
+; RUN: llvm-as @%S/Inputs/utf8-response > /dev/null
+; RUN: llvm-as @%S/Inputs/utf8-bom-response > /dev/null
+
 ; CHECK: T foobar
 
 define void @foobar() {
diff --git a/test/Other/constant-fold-gep-address-spaces.ll b/test/Other/constant-fold-gep-address-spaces.ll
index f6abe7468bba..ee2f48b64a33 100644
--- a/test/Other/constant-fold-gep-address-spaces.ll
+++ b/test/Other/constant-fold-gep-address-spaces.ll
@@ -7,140 +7,140 @@ target datalayout = "e-p:128:128:128-p1:32:32:32-p2:8:8:8-p3:16:16:16-p4:64:64:6
 ; The automatic constant folder in opt does not have targetdata access, so
 ; it can't fold gep arithmetic, in general. However, the constant folder run
 ; from instcombine and global opt can use targetdata.
-; PLAIN: @G8 = global i8 addrspace(1)* getelementptr (i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -1)
-@G8 = global i8 addrspace(1)* getelementptr (i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -1)
-; PLAIN: @G1 = global i1 addrspace(2)* getelementptr (i1 addrspace(2)* inttoptr (i8 1 to i1 addrspace(2)*), i8 -1)
-@G1 = global i1 addrspace(2)* getelementptr (i1 addrspace(2)* inttoptr (i8 1 to i1 addrspace(2)*), i8 -1)
-; PLAIN: @F8 = global i8 addrspace(1)* getelementptr (i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -2)
-@F8 = global i8 addrspace(1)* getelementptr (i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -2)
-; PLAIN: @F1 = global i1 addrspace(2)* getelementptr (i1 addrspace(2)* inttoptr (i8 1 to i1 addrspace(2)*), i8 -2)
-@F1 = global i1 addrspace(2)* getelementptr (i1 addrspace(2)* inttoptr (i8 1 to i1 addrspace(2)*), i8 -2)
-; PLAIN: @H8 = global i8 addrspace(1)* getelementptr (i8 addrspace(1)* null, i32 -1)
-@H8 = global i8 addrspace(1)* getelementptr (i8 addrspace(1)* inttoptr (i32 0 to i8 addrspace(1)*), i32 -1)
-; PLAIN: @H1 = global i1 addrspace(2)* getelementptr (i1 addrspace(2)* null, i8 -1)
-@H1 = global i1 addrspace(2)* getelementptr (i1 addrspace(2)* inttoptr (i8 0 to i1 addrspace(2)*), i8 -1)
+; PLAIN: @G8 = global i8 addrspace(1)* getelementptr (i8, i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -1)
+@G8 = global i8 addrspace(1)* getelementptr (i8, i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -1)
+; PLAIN: @G1 = global i1 addrspace(2)* getelementptr (i1, i1 addrspace(2)* inttoptr (i8 1 to i1 addrspace(2)*), i8 -1)
+@G1 = global i1 addrspace(2)* getelementptr (i1, i1 addrspace(2)* inttoptr (i8 1 to i1 addrspace(2)*), i8 -1)
+; PLAIN: @F8 = global i8 addrspace(1)* getelementptr (i8, i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -2)
+@F8 = global i8 addrspace(1)* getelementptr (i8, i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -2)
+; PLAIN: @F1 = global i1 addrspace(2)* getelementptr (i1, i1 addrspace(2)* inttoptr (i8 1 to i1 addrspace(2)*), i8 -2)
+@F1 = global i1 addrspace(2)* getelementptr (i1, i1 addrspace(2)* inttoptr (i8 1 to i1 addrspace(2)*), i8 -2)
+; PLAIN: @H8 = global i8 addrspace(1)* getelementptr (i8, i8 addrspace(1)* null, i32 -1)
+@H8 = global i8 addrspace(1)* getelementptr (i8, i8 addrspace(1)* inttoptr (i32 0 to i8 addrspace(1)*), i32 -1)
+; PLAIN: @H1 = global i1 addrspace(2)* getelementptr (i1, i1 addrspace(2)* null, i8 -1)
+@H1 = global i1 addrspace(2)* getelementptr (i1, i1 addrspace(2)* inttoptr (i8 0 to i1 addrspace(2)*), i8 -1)
 
 
 ; The target-independent folder should be able to do some clever
 ; simplifications on sizeof, alignof, and offsetof expressions. The
 ; target-dependent folder should fold these down to constants.
-; PLAIN-X: @a = constant i64 mul (i64 ptrtoint (double addrspace(4)* getelementptr (double addrspace(4)* null, i32 1) to i64), i64 2310)
-@a = constant i64 mul (i64 3, i64 mul (i64 ptrtoint ({[7 x double], [7 x double]} addrspace(4)* getelementptr ({[7 x double], [7 x double]} addrspace(4)* null, i64 11) to i64), i64 5))
+; PLAIN-X: @a = constant i64 mul (i64 ptrtoint (double addrspace(4)* getelementptr (double, double addrspace(4)* null, i32 1) to i64), i64 2310)
+@a = constant i64 mul (i64 3, i64 mul (i64 ptrtoint ({[7 x double], [7 x double]} addrspace(4)* getelementptr ({[7 x double], [7 x double]}, {[7 x double], [7 x double]} addrspace(4)* null, i64 11) to i64), i64 5))
 
-; PLAIN-X: @b = constant i64 ptrtoint (double addrspace(4)* getelementptr ({ i1, double }* null, i64 0, i32 1) to i64)
-@b = constant i64 ptrtoint ([13 x double] addrspace(4)* getelementptr ({i1, [13 x double]} addrspace(4)* null, i64 0, i32 1) to i64)
+; PLAIN-X: @b = constant i64 ptrtoint (double addrspace(4)* getelementptr ({ i1, double }, { i1, double }* null, i64 0, i32 1) to i64)
+@b = constant i64 ptrtoint ([13 x double] addrspace(4)* getelementptr ({i1, [13 x double]}, {i1, [13 x double]} addrspace(4)* null, i64 0, i32 1) to i64)
 
-; PLAIN-X: @c = constant i64 mul nuw (i64 ptrtoint (double addrspace(4)* getelementptr (double addrspace(4)* null, i32 1) to i64), i64 2)
-@c = constant i64 ptrtoint (double addrspace(4)* getelementptr ({double, double, double, double} addrspace(4)* null, i64 0, i32 2) to i64)
+; PLAIN-X: @c = constant i64 mul nuw (i64 ptrtoint (double addrspace(4)* getelementptr (double, double addrspace(4)* null, i32 1) to i64), i64 2)
+@c = constant i64 ptrtoint (double addrspace(4)* getelementptr ({double, double, double, double}, {double, double, double, double} addrspace(4)* null, i64 0, i32 2) to i64)
 
-; PLAIN-X: @d = constant i64 mul nuw (i64 ptrtoint (double addrspace(4)* getelementptr (double addrspace(4)* null, i32 1) to i64), i64 11)
-@d = constant i64 ptrtoint (double addrspace(4)* getelementptr ([13 x double] addrspace(4)* null, i64 0, i32 11) to i64)
+; PLAIN-X: @d = constant i64 mul nuw (i64 ptrtoint (double addrspace(4)* getelementptr (double, double addrspace(4)* null, i32 1) to i64), i64 11)
+@d = constant i64 ptrtoint (double addrspace(4)* getelementptr ([13 x double], [13 x double] addrspace(4)* null, i64 0, i32 11) to i64)
 
-; PLAIN-X: @e = constant i64 ptrtoint (double addrspace(4)* getelementptr ({ double, float, double, double }* null, i64 0, i32 2) to i64)
-@e = constant i64 ptrtoint (double addrspace(4)* getelementptr ({double, float, double, double} addrspace(4)* null, i64 0, i32 2) to i64)
+; PLAIN-X: @e = constant i64 ptrtoint (double addrspace(4)* getelementptr ({ double, float, double, double }, { double, float, double, double }* null, i64 0, i32 2) to i64)
+@e = constant i64 ptrtoint (double addrspace(4)* getelementptr ({double, float, double, double}, {double, float, double, double} addrspace(4)* null, i64 0, i32 2) to i64)
 
 ; PLAIN-X: @f = constant i64 1
-@f = constant i64 ptrtoint (<{ i16, i128 }> addrspace(4)* getelementptr ({i1, <{ i16, i128 }>} addrspace(4)* null, i64 0, i32 1) to i64)
+@f = constant i64 ptrtoint (<{ i16, i128 }> addrspace(4)* getelementptr ({i1, <{ i16, i128 }>}, {i1, <{ i16, i128 }>} addrspace(4)* null, i64 0, i32 1) to i64)
 
-; PLAIN-X: @g = constant i64 ptrtoint (double addrspace(4)* getelementptr ({ i1, double }* null, i64 0, i32 1) to i64)
-@g = constant i64 ptrtoint ({double, double} addrspace(4)* getelementptr ({i1, {double, double}} addrspace(4)* null, i64 0, i32 1) to i64)
+; PLAIN-X: @g = constant i64 ptrtoint (double addrspace(4)* getelementptr ({ i1, double }, { i1, double }* null, i64 0, i32 1) to i64)
+@g = constant i64 ptrtoint ({double, double} addrspace(4)* getelementptr ({i1, {double, double}}, {i1, {double, double}} addrspace(4)* null, i64 0, i32 1) to i64)
 
-; PLAIN-X: @h = constant i64 ptrtoint (i1 addrspace(2)* getelementptr (i1 addrspace(2)* null, i32 1) to i64)
-@h = constant i64 ptrtoint (double addrspace(4)* getelementptr (double addrspace(4)* null, i64 1) to i64)
+; PLAIN-X: @h = constant i64 ptrtoint (i1 addrspace(2)* getelementptr (i1, i1 addrspace(2)* null, i32 1) to i64)
+@h = constant i64 ptrtoint (double addrspace(4)* getelementptr (double, double addrspace(4)* null, i64 1) to i64)
 
-; PLAIN-X: @i = constant i64 ptrtoint (i1 addrspace(2)* getelementptr ({ i1, i1 addrspace(2)* }* null, i64 0, i32 1) to i64)
-@i = constant i64 ptrtoint (double addrspace(4)* getelementptr ({i1, double} addrspace(4)* null, i64 0, i32 1) to i64)
+; PLAIN-X: @i = constant i64 ptrtoint (i1 addrspace(2)* getelementptr ({ i1, i1 addrspace(2)* }, { i1, i1 addrspace(2)* }* null, i64 0, i32 1) to i64)
+@i = constant i64 ptrtoint (double addrspace(4)* getelementptr ({i1, double}, {i1, double} addrspace(4)* null, i64 0, i32 1) to i64)
 
 ; The target-dependent folder should cast GEP indices to integer-sized pointers.
 
-; PLAIN: @M = constant i64 addrspace(4)* getelementptr (i64 addrspace(4)* null, i32 1)
-; PLAIN: @N = constant i64 addrspace(4)* getelementptr ({ i64, i64 } addrspace(4)* null, i32 0, i32 1)
-; PLAIN: @O = constant i64 addrspace(4)* getelementptr ([2 x i64] addrspace(4)* null, i32 0, i32 1)
+; PLAIN: @M = constant i64 addrspace(4)* getelementptr (i64, i64 addrspace(4)* null, i32 1)
+; PLAIN: @N = constant i64 addrspace(4)* getelementptr ({ i64, i64 }, { i64, i64 } addrspace(4)* null, i32 0, i32 1)
+; PLAIN: @O = constant i64 addrspace(4)* getelementptr ([2 x i64], [2 x i64] addrspace(4)* null, i32 0, i32 1)
 
-@M = constant i64 addrspace(4)* getelementptr (i64 addrspace(4)* null, i32 1)
-@N = constant i64 addrspace(4)* getelementptr ({ i64, i64 } addrspace(4)* null, i32 0, i32 1)
-@O = constant i64 addrspace(4)* getelementptr ([2 x i64] addrspace(4)* null, i32 0, i32 1)
+@M = constant i64 addrspace(4)* getelementptr (i64, i64 addrspace(4)* null, i32 1)
+@N = constant i64 addrspace(4)* getelementptr ({ i64, i64 }, { i64, i64 } addrspace(4)* null, i32 0, i32 1)
+@O = constant i64 addrspace(4)* getelementptr ([2 x i64], [2 x i64] addrspace(4)* null, i32 0, i32 1)
 
 ; Fold GEP of a GEP. Very simple cases are folded.
 
-; PLAIN-X: @Y = global [3 x { i32, i32 }]addrspace(3)* getelementptr inbounds ([3 x { i32, i32 }]addrspace(3)* @ext, i64 2)
+; PLAIN-X: @Y = global [3 x { i32, i32 }]addrspace(3)* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]addrspace(3)* @ext, i64 2)
 @ext = external addrspace(3) global [3 x { i32, i32 }]
-@Y = global [3 x { i32, i32 }]addrspace(3)* getelementptr inbounds ([3 x { i32, i32 }]addrspace(3)* getelementptr inbounds ([3 x { i32, i32 }]addrspace(3)* @ext, i64 1), i64 1)
+@Y = global [3 x { i32, i32 }]addrspace(3)* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]addrspace(3)* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]addrspace(3)* @ext, i64 1), i64 1)
 
-; PLAIN-X: @Z = global i32addrspace(3)* getelementptr inbounds (i32addrspace(3)* getelementptr inbounds ([3 x { i32, i32 }]addrspace(3)* @ext, i64 0, i64 1, i32 0), i64 1)
-@Z = global i32addrspace(3)* getelementptr inbounds (i32addrspace(3)* getelementptr inbounds ([3 x { i32, i32 }]addrspace(3)* @ext, i64 0, i64 1, i32 0), i64 1)
+; PLAIN-X: @Z = global i32addrspace(3)* getelementptr inbounds (i32, i32addrspace(3)* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]addrspace(3)* @ext, i64 0, i64 1, i32 0), i64 1)
+@Z = global i32addrspace(3)* getelementptr inbounds (i32, i32addrspace(3)* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]addrspace(3)* @ext, i64 0, i64 1, i32 0), i64 1)
 
 
 ; Duplicate all of the above as function return values rather than
 ; global initializers.
 
 ; PLAIN: define i8 addrspace(1)* @goo8() #0 {
-; PLAIN:   %t = bitcast i8 addrspace(1)* getelementptr (i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -1) to i8 addrspace(1)*
+; PLAIN:   %t = bitcast i8 addrspace(1)* getelementptr (i8, i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -1) to i8 addrspace(1)*
 ; PLAIN:   ret i8 addrspace(1)* %t
 ; PLAIN: }
 ; PLAIN: define i1 addrspace(2)* @goo1() #0 {
-; PLAIN:   %t = bitcast i1 addrspace(2)* getelementptr (i1 addrspace(2)* inttoptr (i32 1 to i1 addrspace(2)*), i32 -1) to i1 addrspace(2)*
+; PLAIN:   %t = bitcast i1 addrspace(2)* getelementptr (i1, i1 addrspace(2)* inttoptr (i32 1 to i1 addrspace(2)*), i32 -1) to i1 addrspace(2)*
 ; PLAIN:   ret i1 addrspace(2)* %t
 ; PLAIN: }
 ; PLAIN: define i8 addrspace(1)* @foo8() #0 {
-; PLAIN:   %t = bitcast i8 addrspace(1)* getelementptr (i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -2) to i8 addrspace(1)*
+; PLAIN:   %t = bitcast i8 addrspace(1)* getelementptr (i8, i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -2) to i8 addrspace(1)*
 ; PLAIN:   ret i8 addrspace(1)* %t
 ; PLAIN: }
 ; PLAIN: define i1 addrspace(2)* @foo1() #0 {
-; PLAIN:   %t = bitcast i1 addrspace(2)* getelementptr (i1 addrspace(2)* inttoptr (i32 1 to i1 addrspace(2)*), i32 -2) to i1 addrspace(2)*
+; PLAIN:   %t = bitcast i1 addrspace(2)* getelementptr (i1, i1 addrspace(2)* inttoptr (i32 1 to i1 addrspace(2)*), i32 -2) to i1 addrspace(2)*
 ; PLAIN:   ret i1 addrspace(2)* %t
 ; PLAIN: }
 ; PLAIN: define i8 addrspace(1)* @hoo8() #0 {
-; PLAIN:   %t = bitcast i8 addrspace(1)* getelementptr (i8 addrspace(1)* null, i32 -1) to i8 addrspace(1)*
+; PLAIN:   %t = bitcast i8 addrspace(1)* getelementptr (i8, i8 addrspace(1)* null, i32 -1) to i8 addrspace(1)*
 ; PLAIN:   ret i8 addrspace(1)* %t
 ; PLAIN: }
 ; PLAIN: define i1 addrspace(2)* @hoo1() #0 {
-; PLAIN:   %t = bitcast i1 addrspace(2)* getelementptr (i1 addrspace(2)* null, i32 -1) to i1 addrspace(2)*
+; PLAIN:   %t = bitcast i1 addrspace(2)* getelementptr (i1, i1 addrspace(2)* null, i32 -1) to i1 addrspace(2)*
 ; PLAIN:   ret i1 addrspace(2)* %t
 ; PLAIN: }
 define i8 addrspace(1)* @goo8() #0 {
-  %t = bitcast i8 addrspace(1)* getelementptr (i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -1) to i8 addrspace(1)*
+  %t = bitcast i8 addrspace(1)* getelementptr (i8, i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -1) to i8 addrspace(1)*
   ret i8 addrspace(1)* %t
 }
 define i1 addrspace(2)* @goo1() #0 {
-  %t = bitcast i1 addrspace(2)* getelementptr (i1 addrspace(2)* inttoptr (i32 1 to i1 addrspace(2)*), i32 -1) to i1 addrspace(2)*
+  %t = bitcast i1 addrspace(2)* getelementptr (i1, i1 addrspace(2)* inttoptr (i32 1 to i1 addrspace(2)*), i32 -1) to i1 addrspace(2)*
   ret i1 addrspace(2)* %t
 }
 define i8 addrspace(1)* @foo8() #0 {
-  %t = bitcast i8 addrspace(1)* getelementptr (i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -2) to i8 addrspace(1)*
+  %t = bitcast i8 addrspace(1)* getelementptr (i8, i8 addrspace(1)* inttoptr (i32 1 to i8 addrspace(1)*), i32 -2) to i8 addrspace(1)*
   ret i8 addrspace(1)* %t
 }
 define i1 addrspace(2)* @foo1() #0 {
-  %t = bitcast i1 addrspace(2)* getelementptr (i1 addrspace(2)* inttoptr (i32 1 to i1 addrspace(2)*), i32 -2) to i1 addrspace(2)*
+  %t = bitcast i1 addrspace(2)* getelementptr (i1, i1 addrspace(2)* inttoptr (i32 1 to i1 addrspace(2)*), i32 -2) to i1 addrspace(2)*
   ret i1 addrspace(2)* %t
 }
 define i8 addrspace(1)* @hoo8() #0 {
-  %t = bitcast i8 addrspace(1)* getelementptr (i8 addrspace(1)* inttoptr (i32 0 to i8 addrspace(1)*), i32 -1) to i8 addrspace(1)*
+  %t = bitcast i8 addrspace(1)* getelementptr (i8, i8 addrspace(1)* inttoptr (i32 0 to i8 addrspace(1)*), i32 -1) to i8 addrspace(1)*
   ret i8 addrspace(1)* %t
 }
 define i1 addrspace(2)* @hoo1() #0 {
-  %t = bitcast i1 addrspace(2)* getelementptr (i1 addrspace(2)* inttoptr (i32 0 to i1 addrspace(2)*), i32 -1) to i1 addrspace(2)*
+  %t = bitcast i1 addrspace(2)* getelementptr (i1, i1 addrspace(2)* inttoptr (i32 0 to i1 addrspace(2)*), i32 -1) to i1 addrspace(2)*
   ret i1 addrspace(2)* %t
 }
 
 ; PLAIN-X: define i64 @fa() #0 {
-; PLAIN-X:   %t = bitcast i64 mul (i64 ptrtoint (double addrspace(4)* getelementptr (double addrspace(4)* null, i32 1) to i64), i64 2310) to i64
+; PLAIN-X:   %t = bitcast i64 mul (i64 ptrtoint (double addrspace(4)* getelementptr (double, double addrspace(4)* null, i32 1) to i64), i64 2310) to i64
 ; PLAIN-X:   ret i64 %t
 ; PLAIN-X: }
 ; PLAIN-X: define i64 @fb() #0 {
-; PLAIN-X:   %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr ({ i1, double }* null, i64 0, i32 1) to i64) to i64
+; PLAIN-X:   %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr ({ i1, double }, { i1, double }* null, i64 0, i32 1) to i64) to i64
 ; PLAIN-X:   ret i64 %t
 ; PLAIN-X: }
 ; PLAIN-X: define i64 @fc() #0 {
-; PLAIN-X:   %t = bitcast i64 mul nuw (i64 ptrtoint (double addrspace(4)* getelementptr (double addrspace(4)* null, i32 1) to i64), i64 2) to i64
+; PLAIN-X:   %t = bitcast i64 mul nuw (i64 ptrtoint (double addrspace(4)* getelementptr (double, double addrspace(4)* null, i32 1) to i64), i64 2) to i64
 ; PLAIN-X:   ret i64 %t
 ; PLAIN-X: }
 ; PLAIN-X: define i64 @fd() #0 {
-; PLAIN-X:   %t = bitcast i64 mul nuw (i64 ptrtoint (double addrspace(4)* getelementptr (double addrspace(4)* null, i32 1) to i64), i64 11) to i64
+; PLAIN-X:   %t = bitcast i64 mul nuw (i64 ptrtoint (double addrspace(4)* getelementptr (double, double addrspace(4)* null, i32 1) to i64), i64 11) to i64
 ; PLAIN-X:   ret i64 %t
 ; PLAIN-X: }
 ; PLAIN-X: define i64 @fe() #0 {
-; PLAIN-X:   %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr ({ double, float, double, double }* null, i64 0, i32 2) to i64) to i64
+; PLAIN-X:   %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr ({ double, float, double, double }, { double, float, double, double }* null, i64 0, i32 2) to i64) to i64
 ; PLAIN-X:   ret i64 %t
 ; PLAIN-X: }
 ; PLAIN-X: define i64 @ff() #0 {
@@ -148,87 +148,87 @@ define i1 addrspace(2)* @hoo1() #0 {
 ; PLAIN-X:   ret i64 %t
 ; PLAIN-X: }
 ; PLAIN-X: define i64 @fg() #0 {
-; PLAIN-X:   %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr ({ i1, double }* null, i64 0, i32 1) to i64) to i64
+; PLAIN-X:   %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr ({ i1, double }, { i1, double }* null, i64 0, i32 1) to i64) to i64
 ; PLAIN-X:   ret i64 %t
 ; PLAIN-X: }
 ; PLAIN-X: define i64 @fh() #0 {
-; PLAIN-X:   %t = bitcast i64 ptrtoint (i1 addrspace(2)* getelementptr (i1 addrspace(2)* null, i32 1) to i64) to i64
+; PLAIN-X:   %t = bitcast i64 ptrtoint (i1 addrspace(2)* getelementptr (i1, i1 addrspace(2)* null, i32 1) to i64) to i64
 ; PLAIN-X:   ret i64 %t
 ; PLAIN-X: }
 ; PLAIN-X: define i64 @fi() #0 {
-; PLAIN-X:   %t = bitcast i64 ptrtoint (i1 addrspace(2)* getelementptr ({ i1, i1 addrspace(2)* }* null, i64 0, i32 1) to i64) to i64
+; PLAIN-X:   %t = bitcast i64 ptrtoint (i1 addrspace(2)* getelementptr ({ i1, i1 addrspace(2)* }, { i1, i1 addrspace(2)* }* null, i64 0, i32 1) to i64) to i64
 ; PLAIN-X:   ret i64 %t
 ; PLAIN-X: }
 define i64 @fa() #0 {
-  %t = bitcast i64 mul (i64 3, i64 mul (i64 ptrtoint ({[7 x double], [7 x double]}* getelementptr ({[7 x double], [7 x double]}* null, i64 11) to i64), i64 5)) to i64
+  %t = bitcast i64 mul (i64 3, i64 mul (i64 ptrtoint ({[7 x double], [7 x double]}* getelementptr ({[7 x double], [7 x double]}, {[7 x double], [7 x double]}* null, i64 11) to i64), i64 5)) to i64
   ret i64 %t
 }
 define i64 @fb() #0 {
-  %t = bitcast i64 ptrtoint ([13 x double] addrspace(4)* getelementptr ({i1, [13 x double]} addrspace(4)* null, i64 0, i32 1) to i64) to i64
+  %t = bitcast i64 ptrtoint ([13 x double] addrspace(4)* getelementptr ({i1, [13 x double]}, {i1, [13 x double]} addrspace(4)* null, i64 0, i32 1) to i64) to i64
   ret i64 %t
 }
 define i64 @fc() #0 {
-  %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr ({double, double, double, double} addrspace(4)* null, i64 0, i32 2) to i64) to i64
+  %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr ({double, double, double, double}, {double, double, double, double} addrspace(4)* null, i64 0, i32 2) to i64) to i64
   ret i64 %t
 }
 define i64 @fd() #0 {
-  %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr ([13 x double] addrspace(4)* null, i64 0, i32 11) to i64) to i64
+  %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr ([13 x double], [13 x double] addrspace(4)* null, i64 0, i32 11) to i64) to i64
   ret i64 %t
 }
 define i64 @fe() #0 {
-  %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr ({double, float, double, double} addrspace(4)* null, i64 0, i32 2) to i64) to i64
+  %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr ({double, float, double, double}, {double, float, double, double} addrspace(4)* null, i64 0, i32 2) to i64) to i64
   ret i64 %t
 }
 define i64 @ff() #0 {
-  %t = bitcast i64 ptrtoint (<{ i16, i128 }> addrspace(4)* getelementptr ({i1, <{ i16, i128 }>} addrspace(4)* null, i64 0, i32 1) to i64) to i64
+  %t = bitcast i64 ptrtoint (<{ i16, i128 }> addrspace(4)* getelementptr ({i1, <{ i16, i128 }>}, {i1, <{ i16, i128 }>} addrspace(4)* null, i64 0, i32 1) to i64) to i64
   ret i64 %t
 }
 define i64 @fg() #0 {
-  %t = bitcast i64 ptrtoint ({double, double} addrspace(4)* getelementptr ({i1, {double, double}} addrspace(4)* null, i64 0, i32 1) to i64) to i64
+  %t = bitcast i64 ptrtoint ({double, double} addrspace(4)* getelementptr ({i1, {double, double}}, {i1, {double, double}} addrspace(4)* null, i64 0, i32 1) to i64) to i64
   ret i64 %t
 }
 define i64 @fh() #0 {
-  %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr (double addrspace(4)* null, i32 1) to i64) to i64
+  %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr (double, double addrspace(4)* null, i32 1) to i64) to i64
   ret i64 %t
 }
 define i64 @fi() #0 {
-  %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr ({i1, double}addrspace(4)* null, i64 0, i32 1) to i64) to i64
+  %t = bitcast i64 ptrtoint (double addrspace(4)* getelementptr ({i1, double}, {i1, double}addrspace(4)* null, i64 0, i32 1) to i64) to i64
   ret i64 %t
 }
 
 ; PLAIN: define i64* @fM() #0 {
-; PLAIN:   %t = bitcast i64* getelementptr (i64* null, i32 1) to i64*
+; PLAIN:   %t = bitcast i64* getelementptr (i64, i64* null, i32 1) to i64*
 ; PLAIN:   ret i64* %t
 ; PLAIN: }
 ; PLAIN: define i64* @fN() #0 {
-; PLAIN:   %t = bitcast i64* getelementptr ({ i64, i64 }* null, i32 0, i32 1) to i64*
+; PLAIN:   %t = bitcast i64* getelementptr ({ i64, i64 }, { i64, i64 }* null, i32 0, i32 1) to i64*
 ; PLAIN:   ret i64* %t
 ; PLAIN: }
 ; PLAIN: define i64* @fO() #0 {
-; PLAIN:   %t = bitcast i64* getelementptr ([2 x i64]* null, i32 0, i32 1) to i64*
+; PLAIN:   %t = bitcast i64* getelementptr ([2 x i64], [2 x i64]* null, i32 0, i32 1) to i64*
 ; PLAIN:   ret i64* %t
 ; PLAIN: }
 
 define i64* @fM() #0 {
-  %t = bitcast i64* getelementptr (i64* null, i32 1) to i64*
+  %t = bitcast i64* getelementptr (i64, i64* null, i32 1) to i64*
   ret i64* %t
 }
 define i64* @fN() #0 {
-  %t = bitcast i64* getelementptr ({ i64, i64 }* null, i32 0, i32 1) to i64*
+  %t = bitcast i64* getelementptr ({ i64, i64 }, { i64, i64 }* null, i32 0, i32 1) to i64*
   ret i64* %t
 }
 define i64* @fO() #0 {
-  %t = bitcast i64* getelementptr ([2 x i64]* null, i32 0, i32 1) to i64*
+  %t = bitcast i64* getelementptr ([2 x i64], [2 x i64]* null, i32 0, i32 1) to i64*
   ret i64* %t
 }
 
 ; PLAIN: define i32 addrspace(1)* @fZ() #0 {
-; PLAIN:   %t = bitcast i32 addrspace(1)* getelementptr inbounds (i32 addrspace(1)* getelementptr inbounds ([3 x { i32, i32 }] addrspace(1)* @ext2, i64 0, i64 1, i32 0), i64 1) to i32 addrspace(1)*
+; PLAIN:   %t = bitcast i32 addrspace(1)* getelementptr inbounds (i32, i32 addrspace(1)* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }] addrspace(1)* @ext2, i64 0, i64 1, i32 0), i64 1) to i32 addrspace(1)*
 ; PLAIN:   ret i32 addrspace(1)* %t
 ; PLAIN: }
 @ext2 = external addrspace(1) global [3 x { i32, i32 }]
 define i32 addrspace(1)* @fZ() #0 {
-  %t = bitcast i32 addrspace(1)* getelementptr inbounds (i32 addrspace(1)* getelementptr inbounds ([3 x { i32, i32 }] addrspace(1)* @ext2, i64 0, i64 1, i32 0), i64 1) to i32 addrspace(1)*
+  %t = bitcast i32 addrspace(1)* getelementptr inbounds (i32, i32 addrspace(1)* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }] addrspace(1)* @ext2, i64 0, i64 1, i32 0), i64 1) to i32 addrspace(1)*
   ret i32 addrspace(1)* %t
 }
 
diff --git a/test/Other/constant-fold-gep.ll b/test/Other/constant-fold-gep.ll
index 387489820b26..6923aadeb44a 100644
--- a/test/Other/constant-fold-gep.ll
+++ b/test/Other/constant-fold-gep.ll
@@ -1,8 +1,8 @@
-; "PLAIN" - No optimizations. This tests the target-independent
+; "PLAIN" - No optimizations. This tests the default target layout
 ; constant folder.
 ; RUN: opt -S -o - < %s | FileCheck --check-prefix=PLAIN %s
 
-; "OPT" - Optimizations but no targetdata. This tests target-independent
+; "OPT" - Optimizations but no targetdata. This tests default target layout
 ; folding in the optimizers.
 ; RUN: opt -S -o - -instcombine -globalopt < %s | FileCheck --check-prefix=OPT %s
 
@@ -10,7 +10,7 @@
 ; folding in the optimizers.
 ; RUN: opt -S -o - -instcombine -globalopt -default-data-layout="e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64" < %s | FileCheck --check-prefix=TO %s
 
-; "SCEV" - ScalarEvolution but no targetdata.
+; "SCEV" - ScalarEvolution with default target layout
 ; RUN: opt -analyze -scalar-evolution < %s | FileCheck --check-prefix=SCEV %s
 
 
@@ -18,18 +18,18 @@
 ; it can't fold gep arithmetic, in general. However, the constant folder run
 ; from instcombine and global opt can use targetdata.
 
-; PLAIN: @G8 = global i8* getelementptr (i8* inttoptr (i32 1 to i8*), i32 -1)
-; PLAIN: @G1 = global i1* getelementptr (i1* inttoptr (i32 1 to i1*), i32 -1)
-; PLAIN: @F8 = global i8* getelementptr (i8* inttoptr (i32 1 to i8*), i32 -2)
-; PLAIN: @F1 = global i1* getelementptr (i1* inttoptr (i32 1 to i1*), i32 -2)
-; PLAIN: @H8 = global i8* getelementptr (i8* null, i32 -1)
-; PLAIN: @H1 = global i1* getelementptr (i1* null, i32 -1)
-; OPT: @G8 = global i8* getelementptr (i8* inttoptr (i32 1 to i8*), i32 -1)
-; OPT: @G1 = global i1* getelementptr (i1* inttoptr (i32 1 to i1*), i32 -1)
-; OPT: @F8 = global i8* getelementptr (i8* inttoptr (i32 1 to i8*), i32 -2)
-; OPT: @F1 = global i1* getelementptr (i1* inttoptr (i32 1 to i1*), i32 -2)
-; OPT: @H8 = global i8* getelementptr (i8* null, i32 -1)
-; OPT: @H1 = global i1* getelementptr (i1* null, i32 -1)
+; PLAIN: @G8 = global i8* getelementptr (i8, i8* inttoptr (i32 1 to i8*), i32 -1)
+; PLAIN: @G1 = global i1* getelementptr (i1, i1* inttoptr (i32 1 to i1*), i32 -1)
+; PLAIN: @F8 = global i8* getelementptr (i8, i8* inttoptr (i32 1 to i8*), i32 -2)
+; PLAIN: @F1 = global i1* getelementptr (i1, i1* inttoptr (i32 1 to i1*), i32 -2)
+; PLAIN: @H8 = global i8* getelementptr (i8, i8* null, i32 -1)
+; PLAIN: @H1 = global i1* getelementptr (i1, i1* null, i32 -1)
+; OPT: @G8 = global i8* null
+; OPT: @G1 = global i1* null
+; OPT: @F8 = global i8* inttoptr (i64 -1 to i8*)
+; OPT: @F1 = global i1* inttoptr (i64 -1 to i1*)
+; OPT: @H8 = global i8* inttoptr (i64 -1 to i8*)
+; OPT: @H1 = global i1* inttoptr (i64 -1 to i1*)
 ; TO: @G8 = global i8* null
 ; TO: @G1 = global i1* null
 ; TO: @F8 = global i8* inttoptr (i64 -1 to i8*)
@@ -37,35 +37,35 @@
 ; TO: @H8 = global i8* inttoptr (i64 -1 to i8*)
 ; TO: @H1 = global i1* inttoptr (i64 -1 to i1*)
 
-@G8 = global i8* getelementptr (i8* inttoptr (i32 1 to i8*), i32 -1)
-@G1 = global i1* getelementptr (i1* inttoptr (i32 1 to i1*), i32 -1)
-@F8 = global i8* getelementptr (i8* inttoptr (i32 1 to i8*), i32 -2)
-@F1 = global i1* getelementptr (i1* inttoptr (i32 1 to i1*), i32 -2)
-@H8 = global i8* getelementptr (i8* inttoptr (i32 0 to i8*), i32 -1)
-@H1 = global i1* getelementptr (i1* inttoptr (i32 0 to i1*), i32 -1)
+@G8 = global i8* getelementptr (i8, i8* inttoptr (i32 1 to i8*), i32 -1)
+@G1 = global i1* getelementptr (i1, i1* inttoptr (i32 1 to i1*), i32 -1)
+@F8 = global i8* getelementptr (i8, i8* inttoptr (i32 1 to i8*), i32 -2)
+@F1 = global i1* getelementptr (i1, i1* inttoptr (i32 1 to i1*), i32 -2)
+@H8 = global i8* getelementptr (i8, i8* inttoptr (i32 0 to i8*), i32 -1)
+@H1 = global i1* getelementptr (i1, i1* inttoptr (i32 0 to i1*), i32 -1)
 
 ; The target-independent folder should be able to do some clever
 ; simplifications on sizeof, alignof, and offsetof expressions. The
 ; target-dependent folder should fold these down to constants.
 
-; PLAIN: @a = constant i64 mul (i64 ptrtoint (double* getelementptr (double* null, i32 1) to i64), i64 2310)
-; PLAIN: @b = constant i64 ptrtoint (double* getelementptr ({ i1, double }* null, i64 0, i32 1) to i64)
-; PLAIN: @c = constant i64 mul nuw (i64 ptrtoint (double* getelementptr (double* null, i32 1) to i64), i64 2)
-; PLAIN: @d = constant i64 mul nuw (i64 ptrtoint (double* getelementptr (double* null, i32 1) to i64), i64 11)
-; PLAIN: @e = constant i64 ptrtoint (double* getelementptr ({ double, float, double, double }* null, i64 0, i32 2) to i64)
+; PLAIN: @a = constant i64 mul (i64 ptrtoint (double* getelementptr (double, double* null, i32 1) to i64), i64 2310)
+; PLAIN: @b = constant i64 ptrtoint (double* getelementptr ({ i1, double }, { i1, double }* null, i64 0, i32 1) to i64)
+; PLAIN: @c = constant i64 mul nuw (i64 ptrtoint (double* getelementptr (double, double* null, i32 1) to i64), i64 2)
+; PLAIN: @d = constant i64 mul nuw (i64 ptrtoint (double* getelementptr (double, double* null, i32 1) to i64), i64 11)
+; PLAIN: @e = constant i64 ptrtoint (double* getelementptr ({ double, float, double, double }, { double, float, double, double }* null, i64 0, i32 2) to i64)
 ; PLAIN: @f = constant i64 1
-; PLAIN: @g = constant i64 ptrtoint (double* getelementptr ({ i1, double }* null, i64 0, i32 1) to i64)
-; PLAIN: @h = constant i64 ptrtoint (i1** getelementptr (i1** null, i32 1) to i64)
-; PLAIN: @i = constant i64 ptrtoint (i1** getelementptr ({ i1, i1* }* null, i64 0, i32 1) to i64)
-; OPT: @a = constant i64 mul (i64 ptrtoint (double* getelementptr (double* null, i32 1) to i64), i64 2310)
-; OPT: @b = constant i64 ptrtoint (double* getelementptr ({ i1, double }* null, i64 0, i32 1) to i64)
-; OPT: @c = constant i64 mul (i64 ptrtoint (double* getelementptr (double* null, i32 1) to i64), i64 2)
-; OPT: @d = constant i64 mul (i64 ptrtoint (double* getelementptr (double* null, i32 1) to i64), i64 11)
-; OPT: @e = constant i64 ptrtoint (double* getelementptr ({ double, float, double, double }* null, i64 0, i32 2) to i64)
+; PLAIN: @g = constant i64 ptrtoint (double* getelementptr ({ i1, double }, { i1, double }* null, i64 0, i32 1) to i64)
+; PLAIN: @h = constant i64 ptrtoint (i1** getelementptr (i1*, i1** null, i32 1) to i64)
+; PLAIN: @i = constant i64 ptrtoint (i1** getelementptr ({ i1, i1* }, { i1, i1* }* null, i64 0, i32 1) to i64)
+; OPT: @a = constant i64 18480
+; OPT: @b = constant i64 8
+; OPT: @c = constant i64 16
+; OPT: @d = constant i64 88
+; OPT: @e = constant i64 16
 ; OPT: @f = constant i64 1
-; OPT: @g = constant i64 ptrtoint (double* getelementptr ({ i1, double }* null, i64 0, i32 1) to i64)
-; OPT: @h = constant i64 ptrtoint (i1** getelementptr (i1** null, i32 1) to i64)
-; OPT: @i = constant i64 ptrtoint (i1** getelementptr ({ i1, i1* }* null, i64 0, i32 1) to i64)
+; OPT: @g = constant i64 8
+; OPT: @h = constant i64 8
+; OPT: @i = constant i64 8
 ; TO: @a = constant i64 18480
 ; TO: @b = constant i64 8
 ; TO: @c = constant i64 16
@@ -76,89 +76,89 @@
 ; TO: @h = constant i64 8
 ; TO: @i = constant i64 8
 
-@a = constant i64 mul (i64 3, i64 mul (i64 ptrtoint ({[7 x double], [7 x double]}* getelementptr ({[7 x double], [7 x double]}* null, i64 11) to i64), i64 5))
-@b = constant i64 ptrtoint ([13 x double]* getelementptr ({i1, [13 x double]}* null, i64 0, i32 1) to i64)
-@c = constant i64 ptrtoint (double* getelementptr ({double, double, double, double}* null, i64 0, i32 2) to i64)
-@d = constant i64 ptrtoint (double* getelementptr ([13 x double]* null, i64 0, i32 11) to i64)
-@e = constant i64 ptrtoint (double* getelementptr ({double, float, double, double}* null, i64 0, i32 2) to i64)
-@f = constant i64 ptrtoint (<{ i16, i128 }>* getelementptr ({i1, <{ i16, i128 }>}* null, i64 0, i32 1) to i64)
-@g = constant i64 ptrtoint ({double, double}* getelementptr ({i1, {double, double}}* null, i64 0, i32 1) to i64)
-@h = constant i64 ptrtoint (double** getelementptr (double** null, i64 1) to i64)
-@i = constant i64 ptrtoint (double** getelementptr ({i1, double*}* null, i64 0, i32 1) to i64)
+@a = constant i64 mul (i64 3, i64 mul (i64 ptrtoint ({[7 x double], [7 x double]}* getelementptr ({[7 x double], [7 x double]}, {[7 x double], [7 x double]}* null, i64 11) to i64), i64 5))
+@b = constant i64 ptrtoint ([13 x double]* getelementptr ({i1, [13 x double]}, {i1, [13 x double]}* null, i64 0, i32 1) to i64)
+@c = constant i64 ptrtoint (double* getelementptr ({double, double, double, double}, {double, double, double, double}* null, i64 0, i32 2) to i64)
+@d = constant i64 ptrtoint (double* getelementptr ([13 x double], [13 x double]* null, i64 0, i32 11) to i64)
+@e = constant i64 ptrtoint (double* getelementptr ({double, float, double, double}, {double, float, double, double}* null, i64 0, i32 2) to i64)
+@f = constant i64 ptrtoint (<{ i16, i128 }>* getelementptr ({i1, <{ i16, i128 }>}, {i1, <{ i16, i128 }>}* null, i64 0, i32 1) to i64)
+@g = constant i64 ptrtoint ({double, double}* getelementptr ({i1, {double, double}}, {i1, {double, double}}* null, i64 0, i32 1) to i64)
+@h = constant i64 ptrtoint (double** getelementptr (double*, double** null, i64 1) to i64)
+@i = constant i64 ptrtoint (double** getelementptr ({i1, double*}, {i1, double*}* null, i64 0, i32 1) to i64)
 
 ; The target-dependent folder should cast GEP indices to integer-sized pointers.
 
-; PLAIN: @M = constant i64* getelementptr (i64* null, i32 1)
-; PLAIN: @N = constant i64* getelementptr ({ i64, i64 }* null, i32 0, i32 1)
-; PLAIN: @O = constant i64* getelementptr ([2 x i64]* null, i32 0, i32 1)
-; OPT: @M = constant i64* getelementptr (i64* null, i32 1)
-; OPT: @N = constant i64* getelementptr ({ i64, i64 }* null, i32 0, i32 1)
-; OPT: @O = constant i64* getelementptr ([2 x i64]* null, i32 0, i32 1)
+; PLAIN: @M = constant i64* getelementptr (i64, i64* null, i32 1)
+; PLAIN: @N = constant i64* getelementptr ({ i64, i64 }, { i64, i64 }* null, i32 0, i32 1)
+; PLAIN: @O = constant i64* getelementptr ([2 x i64], [2 x i64]* null, i32 0, i32 1)
+; OPT: @M = constant i64* inttoptr (i64 8 to i64*)
+; OPT: @N = constant i64* inttoptr (i64 8 to i64*)
+; OPT: @O = constant i64* inttoptr (i64 8 to i64*)
 ; TO: @M = constant i64* inttoptr (i64 8 to i64*)
 ; TO: @N = constant i64* inttoptr (i64 8 to i64*)
 ; TO: @O = constant i64* inttoptr (i64 8 to i64*)
 
-@M = constant i64* getelementptr (i64* null, i32 1)
-@N = constant i64* getelementptr ({ i64, i64 }* null, i32 0, i32 1)
-@O = constant i64* getelementptr ([2 x i64]* null, i32 0, i32 1)
+@M = constant i64* getelementptr (i64, i64* null, i32 1)
+@N = constant i64* getelementptr ({ i64, i64 }, { i64, i64 }* null, i32 0, i32 1)
+@O = constant i64* getelementptr ([2 x i64], [2 x i64]* null, i32 0, i32 1)
 
 ; Fold GEP of a GEP. Very simple cases are folded without targetdata.
 
-; PLAIN: @Y = global [3 x { i32, i32 }]* getelementptr inbounds ([3 x { i32, i32 }]* @ext, i64 2)
-; PLAIN: @Z = global i32* getelementptr inbounds (i32* getelementptr inbounds ([3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 0), i64 1)
-; OPT: @Y = global [3 x { i32, i32 }]* getelementptr ([3 x { i32, i32 }]* @ext, i64 2)
-; OPT: @Z = global i32* getelementptr (i32* getelementptr inbounds ([3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 0), i64 1)
-; TO: @Y = global [3 x { i32, i32 }]* getelementptr ([3 x { i32, i32 }]* @ext, i64 2)
-; TO: @Z = global i32* getelementptr inbounds ([3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 1)
+; PLAIN: @Y = global [3 x { i32, i32 }]* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]* @ext, i64 2)
+; PLAIN: @Z = global i32* getelementptr inbounds (i32, i32* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 0), i64 1)
+; OPT: @Y = global [3 x { i32, i32 }]* getelementptr ([3 x { i32, i32 }], [3 x { i32, i32 }]* @ext, i64 2)
+; OPT: @Z = global i32* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 1)
+; TO: @Y = global [3 x { i32, i32 }]* getelementptr ([3 x { i32, i32 }], [3 x { i32, i32 }]* @ext, i64 2)
+; TO: @Z = global i32* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 1)
 
 @ext = external global [3 x { i32, i32 }]
-@Y = global [3 x { i32, i32 }]* getelementptr inbounds ([3 x { i32, i32 }]* getelementptr inbounds ([3 x { i32, i32 }]* @ext, i64 1), i64 1)
-@Z = global i32* getelementptr inbounds (i32* getelementptr inbounds ([3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 0), i64 1)
+@Y = global [3 x { i32, i32 }]* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]* @ext, i64 1), i64 1)
+@Z = global i32* getelementptr inbounds (i32, i32* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 0), i64 1)
 
 ; Duplicate all of the above as function return values rather than
 ; global initializers.
 
 ; PLAIN: define i8* @goo8() #0 {
-; PLAIN:   %t = bitcast i8* getelementptr (i8* inttoptr (i32 1 to i8*), i32 -1) to i8*
+; PLAIN:   %t = bitcast i8* getelementptr (i8, i8* inttoptr (i32 1 to i8*), i32 -1) to i8*
 ; PLAIN:   ret i8* %t
 ; PLAIN: }
 ; PLAIN: define i1* @goo1() #0 {
-; PLAIN:   %t = bitcast i1* getelementptr (i1* inttoptr (i32 1 to i1*), i32 -1) to i1*
+; PLAIN:   %t = bitcast i1* getelementptr (i1, i1* inttoptr (i32 1 to i1*), i32 -1) to i1*
 ; PLAIN:   ret i1* %t
 ; PLAIN: }
 ; PLAIN: define i8* @foo8() #0 {
-; PLAIN:   %t = bitcast i8* getelementptr (i8* inttoptr (i32 1 to i8*), i32 -2) to i8*
+; PLAIN:   %t = bitcast i8* getelementptr (i8, i8* inttoptr (i32 1 to i8*), i32 -2) to i8*
 ; PLAIN:   ret i8* %t
 ; PLAIN: }
 ; PLAIN: define i1* @foo1() #0 {
-; PLAIN:   %t = bitcast i1* getelementptr (i1* inttoptr (i32 1 to i1*), i32 -2) to i1*
+; PLAIN:   %t = bitcast i1* getelementptr (i1, i1* inttoptr (i32 1 to i1*), i32 -2) to i1*
 ; PLAIN:   ret i1* %t
 ; PLAIN: }
 ; PLAIN: define i8* @hoo8() #0 {
-; PLAIN:   %t = bitcast i8* getelementptr (i8* null, i32 -1) to i8*
+; PLAIN:   %t = bitcast i8* getelementptr (i8, i8* null, i32 -1) to i8*
 ; PLAIN:   ret i8* %t
 ; PLAIN: }
 ; PLAIN: define i1* @hoo1() #0 {
-; PLAIN:   %t = bitcast i1* getelementptr (i1* null, i32 -1) to i1*
+; PLAIN:   %t = bitcast i1* getelementptr (i1, i1* null, i32 -1) to i1*
 ; PLAIN:   ret i1* %t
 ; PLAIN: }
 ; OPT: define i8* @goo8() #0 {
-; OPT:   ret i8* getelementptr (i8* inttoptr (i32 1 to i8*), i32 -1)
+; OPT:   ret i8* null
 ; OPT: }
 ; OPT: define i1* @goo1() #0 {
-; OPT:   ret i1* getelementptr (i1* inttoptr (i32 1 to i1*), i32 -1)
+; OPT:   ret i1* null
 ; OPT: }
 ; OPT: define i8* @foo8() #0 {
-; OPT:   ret i8* getelementptr (i8* inttoptr (i32 1 to i8*), i32 -2)
+; OPT:   ret i8* inttoptr (i64 -1 to i8*)
 ; OPT: }
 ; OPT: define i1* @foo1() #0 {
-; OPT:   ret i1* getelementptr (i1* inttoptr (i32 1 to i1*), i32 -2)
+; OPT:   ret i1* inttoptr (i64 -1 to i1*)
 ; OPT: }
 ; OPT: define i8* @hoo8() #0 {
-; OPT:   ret i8* getelementptr (i8* null, i32 -1)
+; OPT:   ret i8* inttoptr (i64 -1 to i8*)
 ; OPT: }
 ; OPT: define i1* @hoo1() #0 {
-; OPT:   ret i1* getelementptr (i1* null, i32 -1)
+; OPT:   ret i1* inttoptr (i64 -1 to i1*)
 ; OPT: }
 ; TO: define i8* @goo8() #0 {
 ; TO:   ret i8* null
@@ -179,65 +179,65 @@
 ; TO:   ret i1* inttoptr (i64 -1 to i1*)
 ; TO: }
 ; SCEV: Classifying expressions for: @goo8
-; SCEV:   %t = bitcast i8* getelementptr (i8* inttoptr (i32 1 to i8*), i32 -1) to i8*
-; SCEV:   -->  ((-1 * sizeof(i8)) + inttoptr (i32 1 to i8*))
+; SCEV:   %t = bitcast i8* getelementptr (i8, i8* inttoptr (i32 1 to i8*), i32 -1) to i8*
+; SCEV:   -->  (-1 + inttoptr (i32 1 to i8*))
 ; SCEV: Classifying expressions for: @goo1
-; SCEV:   %t = bitcast i1* getelementptr (i1* inttoptr (i32 1 to i1*), i32 -1) to i1*
-; SCEV:   -->  ((-1 * sizeof(i1)) + inttoptr (i32 1 to i1*))
+; SCEV:   %t = bitcast i1* getelementptr (i1, i1* inttoptr (i32 1 to i1*), i32 -1) to i1*
+; SCEV:   -->  (-1 + inttoptr (i32 1 to i1*))
 ; SCEV: Classifying expressions for: @foo8
-; SCEV:   %t = bitcast i8* getelementptr (i8* inttoptr (i32 1 to i8*), i32 -2) to i8*
-; SCEV:   -->  ((-2 * sizeof(i8)) + inttoptr (i32 1 to i8*))
+; SCEV:   %t = bitcast i8* getelementptr (i8, i8* inttoptr (i32 1 to i8*), i32 -2) to i8*
+; SCEV:   -->  (-2 + inttoptr (i32 1 to i8*))
 ; SCEV: Classifying expressions for: @foo1
-; SCEV:   %t = bitcast i1* getelementptr (i1* inttoptr (i32 1 to i1*), i32 -2) to i1*
-; SCEV:   -->  ((-2 * sizeof(i1)) + inttoptr (i32 1 to i1*))
+; SCEV:   %t = bitcast i1* getelementptr (i1, i1* inttoptr (i32 1 to i1*), i32 -2) to i1*
+; SCEV:   -->  (-2 + inttoptr (i32 1 to i1*))
 ; SCEV: Classifying expressions for: @hoo8
-; SCEV:   -->  (-1 * sizeof(i8))
+; SCEV:   -->  -1
 ; SCEV: Classifying expressions for: @hoo1
-; SCEV:   -->  (-1 * sizeof(i1))
+; SCEV:   -->  -1
 
 define i8* @goo8() nounwind {
-  %t = bitcast i8* getelementptr (i8* inttoptr (i32 1 to i8*), i32 -1) to i8*
+  %t = bitcast i8* getelementptr (i8, i8* inttoptr (i32 1 to i8*), i32 -1) to i8*
   ret i8* %t
 }
 define i1* @goo1() nounwind {
-  %t = bitcast i1* getelementptr (i1* inttoptr (i32 1 to i1*), i32 -1) to i1*
+  %t = bitcast i1* getelementptr (i1, i1* inttoptr (i32 1 to i1*), i32 -1) to i1*
   ret i1* %t
 }
 define i8* @foo8() nounwind {
-  %t = bitcast i8* getelementptr (i8* inttoptr (i32 1 to i8*), i32 -2) to i8*
+  %t = bitcast i8* getelementptr (i8, i8* inttoptr (i32 1 to i8*), i32 -2) to i8*
   ret i8* %t
 }
 define i1* @foo1() nounwind {
-  %t = bitcast i1* getelementptr (i1* inttoptr (i32 1 to i1*), i32 -2) to i1*
+  %t = bitcast i1* getelementptr (i1, i1* inttoptr (i32 1 to i1*), i32 -2) to i1*
   ret i1* %t
 }
 define i8* @hoo8() nounwind {
-  %t = bitcast i8* getelementptr (i8* inttoptr (i32 0 to i8*), i32 -1) to i8*
+  %t = bitcast i8* getelementptr (i8, i8* inttoptr (i32 0 to i8*), i32 -1) to i8*
   ret i8* %t
 }
 define i1* @hoo1() nounwind {
-  %t = bitcast i1* getelementptr (i1* inttoptr (i32 0 to i1*), i32 -1) to i1*
+  %t = bitcast i1* getelementptr (i1, i1* inttoptr (i32 0 to i1*), i32 -1) to i1*
   ret i1* %t
 }
 
 ; PLAIN: define i64 @fa() #0 {
-; PLAIN:   %t = bitcast i64 mul (i64 ptrtoint (double* getelementptr (double* null, i32 1) to i64), i64 2310) to i64
+; PLAIN:   %t = bitcast i64 mul (i64 ptrtoint (double* getelementptr (double, double* null, i32 1) to i64), i64 2310) to i64
 ; PLAIN:   ret i64 %t
 ; PLAIN: }
 ; PLAIN: define i64 @fb() #0 {
-; PLAIN:   %t = bitcast i64 ptrtoint (double* getelementptr ({ i1, double }* null, i64 0, i32 1) to i64) to i64
+; PLAIN:   %t = bitcast i64 ptrtoint (double* getelementptr ({ i1, double }, { i1, double }* null, i64 0, i32 1) to i64) to i64
 ; PLAIN:   ret i64 %t
 ; PLAIN: }
 ; PLAIN: define i64 @fc() #0 {
-; PLAIN:   %t = bitcast i64 mul nuw (i64 ptrtoint (double* getelementptr (double* null, i32 1) to i64), i64 2) to i64
+; PLAIN:   %t = bitcast i64 mul nuw (i64 ptrtoint (double* getelementptr (double, double* null, i32 1) to i64), i64 2) to i64
 ; PLAIN:   ret i64 %t
 ; PLAIN: }
 ; PLAIN: define i64 @fd() #0 {
-; PLAIN:   %t = bitcast i64 mul nuw (i64 ptrtoint (double* getelementptr (double* null, i32 1) to i64), i64 11) to i64
+; PLAIN:   %t = bitcast i64 mul nuw (i64 ptrtoint (double* getelementptr (double, double* null, i32 1) to i64), i64 11) to i64
 ; PLAIN:   ret i64 %t
 ; PLAIN: }
 ; PLAIN: define i64 @fe() #0 {
-; PLAIN:   %t = bitcast i64 ptrtoint (double* getelementptr ({ double, float, double, double }* null, i64 0, i32 2) to i64) to i64
+; PLAIN:   %t = bitcast i64 ptrtoint (double* getelementptr ({ double, float, double, double }, { double, float, double, double }* null, i64 0, i32 2) to i64) to i64
 ; PLAIN:   ret i64 %t
 ; PLAIN: }
 ; PLAIN: define i64 @ff() #0 {
@@ -245,43 +245,43 @@ define i1* @hoo1() nounwind {
 ; PLAIN:   ret i64 %t
 ; PLAIN: }
 ; PLAIN: define i64 @fg() #0 {
-; PLAIN:   %t = bitcast i64 ptrtoint (double* getelementptr ({ i1, double }* null, i64 0, i32 1) to i64) to i64
+; PLAIN:   %t = bitcast i64 ptrtoint (double* getelementptr ({ i1, double }, { i1, double }* null, i64 0, i32 1) to i64) to i64
 ; PLAIN:   ret i64 %t
 ; PLAIN: }
 ; PLAIN: define i64 @fh() #0 {
-; PLAIN:   %t = bitcast i64 ptrtoint (i1** getelementptr (i1** null, i32 1) to i64) to i64
+; PLAIN:   %t = bitcast i64 ptrtoint (i1** getelementptr (i1*, i1** null, i32 1) to i64) to i64
 ; PLAIN:   ret i64 %t
 ; PLAIN: }
 ; PLAIN: define i64 @fi() #0 {
-; PLAIN:   %t = bitcast i64 ptrtoint (i1** getelementptr ({ i1, i1* }* null, i64 0, i32 1) to i64) to i64
+; PLAIN:   %t = bitcast i64 ptrtoint (i1** getelementptr ({ i1, i1* }, { i1, i1* }* null, i64 0, i32 1) to i64) to i64
 ; PLAIN:   ret i64 %t
 ; PLAIN: }
 ; OPT: define i64 @fa() #0 {
-; OPT:   ret i64 mul (i64 ptrtoint (double* getelementptr (double* null, i32 1) to i64), i64 2310)
+; OPT:   ret i64 18480
 ; OPT: }
 ; OPT: define i64 @fb() #0 {
-; OPT:   ret i64 ptrtoint (double* getelementptr ({ i1, double }* null, i64 0, i32 1) to i64)
+; OPT:   ret i64 8
 ; OPT: }
 ; OPT: define i64 @fc() #0 {
-; OPT:   ret i64 mul (i64 ptrtoint (double* getelementptr (double* null, i32 1) to i64), i64 2)
+; OPT:   ret i64 16
 ; OPT: }
 ; OPT: define i64 @fd() #0 {
-; OPT:   ret i64 mul (i64 ptrtoint (double* getelementptr (double* null, i32 1) to i64), i64 11)
+; OPT:   ret i64 88
 ; OPT: }
 ; OPT: define i64 @fe() #0 {
-; OPT:   ret i64 ptrtoint (double* getelementptr ({ double, float, double, double }* null, i64 0, i32 2) to i64)
+; OPT:   ret i64 16
 ; OPT: }
 ; OPT: define i64 @ff() #0 {
 ; OPT:   ret i64 1
 ; OPT: }
 ; OPT: define i64 @fg() #0 {
-; OPT:   ret i64 ptrtoint (double* getelementptr ({ i1, double }* null, i64 0, i32 1) to i64)
+; OPT:   ret i64 8
 ; OPT: }
 ; OPT: define i64 @fh() #0 {
-; OPT:   ret i64 ptrtoint (i1** getelementptr (i1** null, i32 1) to i64)
+; OPT:   ret i64 8
 ; OPT: }
 ; OPT: define i64 @fi() #0 {
-; OPT:   ret i64 ptrtoint (i1** getelementptr ({ i1, i1* }* null, i64 0, i32 1) to i64)
+; OPT:   ret i64 8
 ; OPT: }
 ; TO: define i64 @fa() #0 {
 ; TO:   ret i64 18480
@@ -311,90 +311,90 @@ define i1* @hoo1() nounwind {
 ; TO:   ret i64 8
 ; TO: }
 ; SCEV: Classifying expressions for: @fa
-; SCEV:   %t = bitcast i64 mul (i64 ptrtoint (double* getelementptr (double* null, i32 1) to i64), i64 2310) to i64 
+; SCEV:   %t = bitcast i64 mul (i64 ptrtoint (double* getelementptr (double, double* null, i32 1) to i64), i64 2310) to i64
 ; SCEV:   -->  (2310 * sizeof(double))
 ; SCEV: Classifying expressions for: @fb
-; SCEV:   %t = bitcast i64 ptrtoint (double* getelementptr ({ i1, double }* null, i64 0, i32 1) to i64) to i64 
+; SCEV:   %t = bitcast i64 ptrtoint (double* getelementptr ({ i1, double }, { i1, double }* null, i64 0, i32 1) to i64) to i64
 ; SCEV:   -->  alignof(double)
 ; SCEV: Classifying expressions for: @fc
-; SCEV:   %t = bitcast i64 mul nuw (i64 ptrtoint (double* getelementptr (double* null, i32 1) to i64), i64 2) to i64 
+; SCEV:   %t = bitcast i64 mul nuw (i64 ptrtoint (double* getelementptr (double, double* null, i32 1) to i64), i64 2) to i64
 ; SCEV:   -->  (2 * sizeof(double))
 ; SCEV: Classifying expressions for: @fd
-; SCEV:   %t = bitcast i64 mul nuw (i64 ptrtoint (double* getelementptr (double* null, i32 1) to i64), i64 11) to i64 
+; SCEV:   %t = bitcast i64 mul nuw (i64 ptrtoint (double* getelementptr (double, double* null, i32 1) to i64), i64 11) to i64
 ; SCEV:   -->  (11 * sizeof(double))
 ; SCEV: Classifying expressions for: @fe
-; SCEV:   %t = bitcast i64 ptrtoint (double* getelementptr ({ double, float, double, double }* null, i64 0, i32 2) to i64) to i64 
+; SCEV:   %t = bitcast i64 ptrtoint (double* getelementptr ({ double, float, double, double }, { double, float, double, double }* null, i64 0, i32 2) to i64) to i64
 ; SCEV:   -->  offsetof({ double, float, double, double }, 2)
 ; SCEV: Classifying expressions for: @ff
-; SCEV:   %t = bitcast i64 1 to i64 
+; SCEV:   %t = bitcast i64 1 to i64
 ; SCEV:   -->  1
 ; SCEV: Classifying expressions for: @fg
-; SCEV:   %t = bitcast i64 ptrtoint (double* getelementptr ({ i1, double }* null, i64 0, i32 1) to i64) to i64
+; SCEV:   %t = bitcast i64 ptrtoint (double* getelementptr ({ i1, double }, { i1, double }* null, i64 0, i32 1) to i64) to i64
 ; SCEV:   -->  alignof(double)
 ; SCEV: Classifying expressions for: @fh
-; SCEV:   %t = bitcast i64 ptrtoint (i1** getelementptr (i1** null, i32 1) to i64) to i64
+; SCEV:   %t = bitcast i64 ptrtoint (i1** getelementptr (i1*, i1** null, i32 1) to i64) to i64
 ; SCEV:   -->  sizeof(i1*)
 ; SCEV: Classifying expressions for: @fi
-; SCEV:   %t = bitcast i64 ptrtoint (i1** getelementptr ({ i1, i1* }* null, i64 0, i32 1) to i64) to i64
+; SCEV:   %t = bitcast i64 ptrtoint (i1** getelementptr ({ i1, i1* }, { i1, i1* }* null, i64 0, i32 1) to i64) to i64
 ; SCEV:   -->  alignof(i1*)
 
 define i64 @fa() nounwind {
-  %t = bitcast i64 mul (i64 3, i64 mul (i64 ptrtoint ({[7 x double], [7 x double]}* getelementptr ({[7 x double], [7 x double]}* null, i64 11) to i64), i64 5)) to i64
+  %t = bitcast i64 mul (i64 3, i64 mul (i64 ptrtoint ({[7 x double], [7 x double]}* getelementptr ({[7 x double], [7 x double]}, {[7 x double], [7 x double]}* null, i64 11) to i64), i64 5)) to i64
   ret i64 %t
 }
 define i64 @fb() nounwind {
-  %t = bitcast i64 ptrtoint ([13 x double]* getelementptr ({i1, [13 x double]}* null, i64 0, i32 1) to i64) to i64
+  %t = bitcast i64 ptrtoint ([13 x double]* getelementptr ({i1, [13 x double]}, {i1, [13 x double]}* null, i64 0, i32 1) to i64) to i64
   ret i64 %t
 }
 define i64 @fc() nounwind {
-  %t = bitcast i64 ptrtoint (double* getelementptr ({double, double, double, double}* null, i64 0, i32 2) to i64) to i64
+  %t = bitcast i64 ptrtoint (double* getelementptr ({double, double, double, double}, {double, double, double, double}* null, i64 0, i32 2) to i64) to i64
   ret i64 %t
 }
 define i64 @fd() nounwind {
-  %t = bitcast i64 ptrtoint (double* getelementptr ([13 x double]* null, i64 0, i32 11) to i64) to i64
+  %t = bitcast i64 ptrtoint (double* getelementptr ([13 x double], [13 x double]* null, i64 0, i32 11) to i64) to i64
   ret i64 %t
 }
 define i64 @fe() nounwind {
-  %t = bitcast i64 ptrtoint (double* getelementptr ({double, float, double, double}* null, i64 0, i32 2) to i64) to i64
+  %t = bitcast i64 ptrtoint (double* getelementptr ({double, float, double, double}, {double, float, double, double}* null, i64 0, i32 2) to i64) to i64
   ret i64 %t
 }
 define i64 @ff() nounwind {
-  %t = bitcast i64 ptrtoint (<{ i16, i128 }>* getelementptr ({i1, <{ i16, i128 }>}* null, i64 0, i32 1) to i64) to i64
+  %t = bitcast i64 ptrtoint (<{ i16, i128 }>* getelementptr ({i1, <{ i16, i128 }>}, {i1, <{ i16, i128 }>}* null, i64 0, i32 1) to i64) to i64
   ret i64 %t
 }
 define i64 @fg() nounwind {
-  %t = bitcast i64 ptrtoint ({double, double}* getelementptr ({i1, {double, double}}* null, i64 0, i32 1) to i64) to i64
+  %t = bitcast i64 ptrtoint ({double, double}* getelementptr ({i1, {double, double}}, {i1, {double, double}}* null, i64 0, i32 1) to i64) to i64
   ret i64 %t
 }
 define i64 @fh() nounwind {
-  %t = bitcast i64 ptrtoint (double** getelementptr (double** null, i32 1) to i64) to i64
+  %t = bitcast i64 ptrtoint (double** getelementptr (double*, double** null, i32 1) to i64) to i64
   ret i64 %t
 }
 define i64 @fi() nounwind {
-  %t = bitcast i64 ptrtoint (double** getelementptr ({i1, double*}* null, i64 0, i32 1) to i64) to i64
+  %t = bitcast i64 ptrtoint (double** getelementptr ({i1, double*}, {i1, double*}* null, i64 0, i32 1) to i64) to i64
   ret i64 %t
 }
 
 ; PLAIN: define i64* @fM() #0 {
-; PLAIN:   %t = bitcast i64* getelementptr (i64* null, i32 1) to i64*
+; PLAIN:   %t = bitcast i64* getelementptr (i64, i64* null, i32 1) to i64*
 ; PLAIN:   ret i64* %t
 ; PLAIN: }
 ; PLAIN: define i64* @fN() #0 {
-; PLAIN:   %t = bitcast i64* getelementptr ({ i64, i64 }* null, i32 0, i32 1) to i64*
+; PLAIN:   %t = bitcast i64* getelementptr ({ i64, i64 }, { i64, i64 }* null, i32 0, i32 1) to i64*
 ; PLAIN:   ret i64* %t
 ; PLAIN: }
 ; PLAIN: define i64* @fO() #0 {
-; PLAIN:   %t = bitcast i64* getelementptr ([2 x i64]* null, i32 0, i32 1) to i64*
+; PLAIN:   %t = bitcast i64* getelementptr ([2 x i64], [2 x i64]* null, i32 0, i32 1) to i64*
 ; PLAIN:   ret i64* %t
 ; PLAIN: }
 ; OPT: define i64* @fM() #0 {
-; OPT:   ret i64* getelementptr (i64* null, i32 1)
+; OPT:   ret i64* inttoptr (i64 8 to i64*)
 ; OPT: }
 ; OPT: define i64* @fN() #0 {
-; OPT:   ret i64* getelementptr ({ i64, i64 }* null, i32 0, i32 1)
+; OPT:   ret i64* inttoptr (i64 8 to i64*)
 ; OPT: }
 ; OPT: define i64* @fO() #0 {
-; OPT:   ret i64* getelementptr ([2 x i64]* null, i32 0, i32 1)
+; OPT:   ret i64* inttoptr (i64 8 to i64*)
 ; OPT: }
 ; TO: define i64* @fM() #0 {
 ; TO:   ret i64* inttoptr (i64 8 to i64*)
@@ -406,44 +406,44 @@ define i64 @fi() nounwind {
 ; TO:   ret i64* inttoptr (i64 8 to i64*)
 ; TO: }
 ; SCEV: Classifying expressions for: @fM
-; SCEV:   %t = bitcast i64* getelementptr (i64* null, i32 1) to i64* 
-; SCEV:   -->  sizeof(i64)
+; SCEV:   %t = bitcast i64* getelementptr (i64, i64* null, i32 1) to i64*
+; SCEV:   -->  8
 ; SCEV: Classifying expressions for: @fN
-; SCEV:   %t = bitcast i64* getelementptr ({ i64, i64 }* null, i32 0, i32 1) to i64* 
-; SCEV:   -->  sizeof(i64)
+; SCEV:   %t = bitcast i64* getelementptr ({ i64, i64 }, { i64, i64 }* null, i32 0, i32 1) to i64*
+; SCEV:   -->  8
 ; SCEV: Classifying expressions for: @fO
-; SCEV:   %t = bitcast i64* getelementptr ([2 x i64]* null, i32 0, i32 1) to i64* 
-; SCEV:   -->  sizeof(i64)
+; SCEV:   %t = bitcast i64* getelementptr ([2 x i64], [2 x i64]* null, i32 0, i32 1) to i64*
+; SCEV:   -->  8
 
 define i64* @fM() nounwind {
-  %t = bitcast i64* getelementptr (i64* null, i32 1) to i64*
+  %t = bitcast i64* getelementptr (i64, i64* null, i32 1) to i64*
   ret i64* %t
 }
 define i64* @fN() nounwind {
-  %t = bitcast i64* getelementptr ({ i64, i64 }* null, i32 0, i32 1) to i64*
+  %t = bitcast i64* getelementptr ({ i64, i64 }, { i64, i64 }* null, i32 0, i32 1) to i64*
   ret i64* %t
 }
 define i64* @fO() nounwind {
-  %t = bitcast i64* getelementptr ([2 x i64]* null, i32 0, i32 1) to i64*
+  %t = bitcast i64* getelementptr ([2 x i64], [2 x i64]* null, i32 0, i32 1) to i64*
   ret i64* %t
 }
 
 ; PLAIN: define i32* @fZ() #0 {
-; PLAIN:   %t = bitcast i32* getelementptr inbounds (i32* getelementptr inbounds ([3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 0), i64 1) to i32*
+; PLAIN:   %t = bitcast i32* getelementptr inbounds (i32, i32* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 0), i64 1) to i32*
 ; PLAIN:   ret i32* %t
 ; PLAIN: }
 ; OPT: define i32* @fZ() #0 {
-; OPT:   ret i32* getelementptr (i32* getelementptr inbounds ([3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 0), i64 1)
+; OPT:   ret i32* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 1)
 ; OPT: }
 ; TO: define i32* @fZ() #0 {
-; TO:   ret i32* getelementptr inbounds ([3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 1)
+; TO:   ret i32* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 1)
 ; TO: }
 ; SCEV: Classifying expressions for: @fZ
-; SCEV:   %t = bitcast i32* getelementptr inbounds (i32* getelementptr inbounds ([3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 0), i64 1) to i32*
-; SCEV:   -->  ((3 * sizeof(i32)) + @ext)
+; SCEV:   %t = bitcast i32* getelementptr inbounds (i32, i32* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 0), i64 1) to i32*
+; SCEV:   -->  (12 + @ext)
 
 define i32* @fZ() nounwind {
-  %t = bitcast i32* getelementptr inbounds (i32* getelementptr inbounds ([3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 0), i64 1) to i32*
+  %t = bitcast i32* getelementptr inbounds (i32, i32* getelementptr inbounds ([3 x { i32, i32 }], [3 x { i32, i32 }]* @ext, i64 0, i64 1, i32 0), i64 1) to i32*
   ret i32* %t
 }
 
@@ -454,17 +454,17 @@ define i32* @fZ() nounwind {
 
 define i8* @different_addrspace() nounwind noinline {
 ; OPT: different_addrspace
-  %p = getelementptr inbounds i8* addrspacecast ([4 x i8] addrspace(12)* @p12 to i8*),
+  %p = getelementptr inbounds i8, i8* addrspacecast ([4 x i8] addrspace(12)* @p12 to i8*),
                                   i32 2
   ret i8* %p
-; OPT: ret i8* getelementptr (i8* addrspacecast (i8 addrspace(12)* getelementptr inbounds ([4 x i8] addrspace(12)* @p12, i32 0, i32 0) to i8*), i32 2)
+; OPT: ret i8* getelementptr ([4 x i8], [4 x i8]* addrspacecast ([4 x i8] addrspace(12)* @p12 to [4 x i8]*), i64 0, i64 2)
 }
 
 define i8* @same_addrspace() nounwind noinline {
 ; OPT: same_addrspace
-  %p = getelementptr inbounds i8* bitcast ([4 x i8] * @p0 to i8*), i32 2
+  %p = getelementptr inbounds i8, i8* bitcast ([4 x i8] * @p0 to i8*), i32 2
   ret i8* %p
-; OPT: ret i8* getelementptr inbounds ([4 x i8]* @p0, i32 0, i32 2)
+; OPT: ret i8* getelementptr inbounds ([4 x i8], [4 x i8]* @p0, i64 0, i64 2)
 }
 
 @gv1 = internal global i32 1
@@ -473,13 +473,13 @@ define i8* @same_addrspace() nounwind noinline {
 
 ; Handled by TI-independent constant folder
 define i1 @gv_gep_vs_gv() {
-  ret i1 icmp eq (i32* getelementptr inbounds ([1 x i32]* @gv2, i32 0, i32 0), i32* @gv1)
+  ret i1 icmp eq (i32* getelementptr inbounds ([1 x i32], [1 x i32]* @gv2, i32 0, i32 0), i32* @gv1)
 }
 ; PLAIN: gv_gep_vs_gv
 ; PLAIN: ret i1 false
 
 define i1 @gv_gep_vs_gv_gep() {
-  ret i1 icmp eq (i32* getelementptr inbounds ([1 x i32]* @gv2, i32 0, i32 0), i32* getelementptr inbounds ([1 x i32]* @gv3, i32 0, i32 0))
+  ret i1 icmp eq (i32* getelementptr inbounds ([1 x i32], [1 x i32]* @gv2, i32 0, i32 0), i32* getelementptr inbounds ([1 x i32], [1 x i32]* @gv3, i32 0, i32 0))
 }
 ; PLAIN: gv_gep_vs_gv_gep
 ; PLAIN: ret i1 false
diff --git a/test/Other/lint.ll b/test/Other/lint.ll
index 78bbbe9e6fa6..8a93fa117a03 100644
--- a/test/Other/lint.ll
+++ b/test/Other/lint.ll
@@ -19,11 +19,11 @@ define i32 @foo() noreturn {
 ; CHECK: Null pointer dereference
   store i32 0, i32* null
 ; CHECK: Null pointer dereference
-  %t = load i32* null
+  %t = load i32, i32* null
 ; CHECK: Undef pointer dereference
   store i32 0, i32* undef
 ; CHECK: Undef pointer dereference
-  %u = load i32* undef
+  %u = load i32, i32* undef
 ; CHECK: All-ones pointer dereference
   store i32 0, i32* inttoptr (i64 -1 to i32*)
 ; CHECK: Address one pointer dereference
@@ -31,7 +31,7 @@ define i32 @foo() noreturn {
 ; CHECK: Memory reference address is misaligned
   store i8 0, i8* %buf, align 2
 ; CHECK: Memory reference address is misaligned
-  %gep = getelementptr {i8, i8}* %buf2, i32 0, i32 1
+  %gep = getelementptr {i8, i8}, {i8, i8}* %buf2, i32 0, i32 1
   store i8 0, i8* %gep, align 2
 ; CHECK: Division by zero
   %sd = sdiv i32 2, 0
@@ -61,9 +61,9 @@ define i32 @foo() noreturn {
 ; CHECK: Write to text section
   store i32 8, i32* bitcast (i32()* @foo to i32*)
 ; CHECK: Load from block address
-  %lb = load i32* bitcast (i8* blockaddress(@foo, %next) to i32*)
+  %lb = load i32, i32* bitcast (i8* blockaddress(@foo, %next) to i32*)
 ; CHECK: Call to block address
-  call void()* bitcast (i8* blockaddress(@foo, %next) to void()*)()
+  call void() bitcast (i8* blockaddress(@foo, %next) to void()*)()
 ; CHECK: Undefined behavior: Null pointer dereference
   call void @llvm.stackrestore(i8* null)
 ; CHECK: Undefined behavior: Null pointer dereference
@@ -71,11 +71,11 @@ define i32 @foo() noreturn {
 ; CHECK: Unusual: noalias argument aliases another argument
   call void @has_noaliases(i32* @CG, i32* @CG)
 ; CHECK: Call argument count mismatches callee argument count
-  call void (i32, i32)* bitcast (void (i32)* @one_arg to void (i32, i32)*)(i32 0, i32 0)
+  call void (i32, i32) bitcast (void (i32)* @one_arg to void (i32, i32)*)(i32 0, i32 0)
 ; CHECK: Call argument count mismatches callee argument count
-  call void ()* bitcast (void (i32)* @one_arg to void ()*)()
+  call void () bitcast (void (i32)* @one_arg to void ()*)()
 ; CHECK: Call argument type mismatches callee parameter type
-  call void (float)* bitcast (void (i32)* @one_arg to void (float)*)(float 0.0)
+  call void (float) bitcast (void (i32)* @one_arg to void (float)*)(float 0.0)
 
 ; CHECK: Write to read-only memory
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (i32* @CG to i8*), i8* bitcast (i32* @CG to i8*), i64 1, i32 1, i1 0)
@@ -84,11 +84,11 @@ define i32 @foo() noreturn {
   %wider = bitcast i8* %buf to i16*
   store i16 0, i16* %wider
 ; CHECK: Undefined behavior: Buffer overflow
-  %inner = getelementptr {i8, i8}* %buf2, i32 0, i32 1
+  %inner = getelementptr {i8, i8}, {i8, i8}* %buf2, i32 0, i32 1
   %wider2 = bitcast i8* %inner to i16*
   store i16 0, i16* %wider2
 ; CHECK: Undefined behavior: Buffer overflow
-  %before = getelementptr i8* %buf, i32 -1
+  %before = getelementptr i8, i8* %buf, i32 -1
   %wider3 = bitcast i8* %before to i16*
   store i16 0, i16* %wider3
 
@@ -140,7 +140,7 @@ define void @use_tail(i8* %valist) {
 ; CHECK: Unusual: Returning alloca value
 define i8* @return_local(i32 %n, i32 %m) {
   %t = alloca i8, i32 %n
-  %s = getelementptr i8* %t, i32 %m
+  %s = getelementptr i8, i8* %t, i32 %m
   ret i8* %s
 }
 
@@ -152,7 +152,7 @@ entry:
   store i32* %x, i32** %retval
   br label %next
 next:
-  %t0 = load i32** %retval
+  %t0 = load i32*, i32** %retval
   %t1 = insertvalue { i32, i32, i32* } zeroinitializer, i32* %t0, 2
   %t2 = extractvalue { i32, i32, i32* } %t1, 2
   br label %exit
@@ -172,7 +172,7 @@ entry:
 exit:
   %t3 = phi i32* [ %t4, %exit ]
   %t4 = bitcast i32* %t3 to i32*
-  %x = load volatile i32* %t3
+  %x = load volatile i32, i32* %t3
   br label %exit
 }
 
diff --git a/test/Other/new-pass-manager.ll b/test/Other/new-pass-manager.ll
index 6454ffc1fb09..fb84e787a0ab 100644
--- a/test/Other/new-pass-manager.ll
+++ b/test/Other/new-pass-manager.ll
@@ -266,6 +266,40 @@
 ; CHECK-INVALIDATE-ALL-CG-NOT: Running analysis: NoOpModuleAnalysis
 ; CHECK-INVALIDATE-ALL-CG: Finished pass manager
 
+; RUN: opt -disable-output -disable-verify -debug-pass-manager %s 2>&1 \
+; RUN:     -passes='require<targetlibinfo>,invalidate<all>,require<targetlibinfo>' \
+; RUN:     | FileCheck %s --check-prefix=CHECK-TLI
+; CHECK-TLI: Starting pass manager
+; CHECK-TLI: Running pass: RequireAnalysisPass
+; CHECK-TLI: Running analysis: TargetLibraryAnalysis
+; CHECK-TLI: Running pass: InvalidateAllAnalysesPass
+; CHECK-TLI-NOT: Invalidating analysis: TargetLibraryAnalysis
+; CHECK-TLI: Running pass: RequireAnalysisPass
+; CHECK-TLI-NOT: Running analysis: TargetLibraryAnalysis
+; CHECK-TLI: Finished pass manager
+
+; RUN: opt -disable-output -disable-verify -debug-pass-manager %s 2>&1 \
+; RUN:     -passes='require<targetir>,invalidate<all>,require<targetir>' \
+; RUN:     | FileCheck %s --check-prefix=CHECK-TIRA
+; CHECK-TIRA: Starting pass manager
+; CHECK-TIRA: Running pass: RequireAnalysisPass
+; CHECK-TIRA: Running analysis: TargetIRAnalysis
+; CHECK-TIRA: Running pass: InvalidateAllAnalysesPass
+; CHECK-TIRA-NOT: Invalidating analysis: TargetIRAnalysis
+; CHECK-TIRA: Running pass: RequireAnalysisPass
+; CHECK-TIRA-NOT: Running analysis: TargetIRAnalysis
+; CHECK-TIRA: Finished pass manager
+
+; RUN: opt -disable-output -disable-verify -debug-pass-manager %s 2>&1 \
+; RUN:     -passes='require<domtree>' \
+; RUN:     | FileCheck %s --check-prefix=CHECK-DT
+; CHECK-DT: Starting pass manager
+; CHECK-DT: Running pass: RequireAnalysisPass
+; CHECK-DT: Running analysis: DominatorTreeAnalysis
+; CHECK-DT: Finished pass manager
+
 define void @foo() {
   ret void
 }
+
+declare void @bar()
diff --git a/test/Other/opt-override-mcpu-mattr.ll b/test/Other/opt-override-mcpu-mattr.ll
new file mode 100644
index 000000000000..84d4209a996a
--- /dev/null
+++ b/test/Other/opt-override-mcpu-mattr.ll
@@ -0,0 +1,13 @@
+; RUN: opt < %s -mtriple=x86_64-apple-darwin -mcpu=broadwell -mattr=+avx2 -S | FileCheck %s
+
+; Check that opt can rewrite function attributes target-cpu and target-features
+; using command line options -mcpu and -mattr.
+
+; CHECK: attributes #0 = { nounwind readnone ssp uwtable "target-cpu"="broadwell" "target-features"="+avx2" "use-soft-float"="false" }
+
+define i32 @foo1() #0 {
+entry:
+  ret i32 0
+}
+
+attributes #0 = { nounwind readnone ssp uwtable "target-cpu"="core2" "target-features"="+ssse3,+cx16,+sse,+sse2,+sse3" "use-soft-float"="false" }
diff --git a/test/Other/optimization-remarks-inline.ll b/test/Other/optimization-remarks-inline.ll
index 566b206919e1..bcd90bc28d32 100644
--- a/test/Other/optimization-remarks-inline.ll
+++ b/test/Other/optimization-remarks-inline.ll
@@ -18,8 +18,8 @@ entry:
   %y.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
   store i32 %y, i32* %y.addr, align 4
-  %0 = load i32* %x.addr, align 4
-  %1 = load i32* %y.addr, align 4
+  %0 = load i32, i32* %x.addr, align 4
+  %1 = load i32, i32* %y.addr, align 4
   %add = add nsw i32 %0, %1
   ret i32 %add
 }
@@ -28,8 +28,8 @@ define i32 @bar(i32 %j) #0 {
 entry:
   %j.addr = alloca i32, align 4
   store i32 %j, i32* %j.addr, align 4
-  %0 = load i32* %j.addr, align 4
-  %1 = load i32* %j.addr, align 4
+  %0 = load i32, i32* %j.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
   %sub = sub nsw i32 %1, 2
   %call = call i32 @foo(i32 %0, i32 %sub)
 ; CHECK: foo inlined into bar
diff --git a/test/TableGen/AsmPredicateCondsEmission.td b/test/TableGen/AsmPredicateCondsEmission.td
new file mode 100644
index 000000000000..c1fe0d2aba21
--- /dev/null
+++ b/test/TableGen/AsmPredicateCondsEmission.td
@@ -0,0 +1,31 @@
+// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
+
+// Check that we don't generate invalid code of the form "( && Cond2)" when
+// emitting AssemblerPredicate conditions. In the example below, the invalid
+// code would be: "return ( && (Bits & arch::AssemblerCondition2));".
+
+include "llvm/Target/Target.td"
+
+def archInstrInfo : InstrInfo { }
+
+def arch : Target {
+  let InstructionSet = archInstrInfo;
+}
+
+def Pred1 : Predicate<"Condition1">;
+def Pred2 : Predicate<"Condition2">,
+            AssemblerPredicate<"AssemblerCondition2">;
+
+def foo : Instruction {
+  let Size = 2;
+  let OutOperandList = (outs);
+  let InOperandList = (ins);
+  field bits<16> Inst;
+  let Inst = 0xAAAA;
+  let AsmString = "foo";
+  field bits<16> SoftFail = 0;
+  // This is the important bit:
+  let Predicates = [Pred1, Pred2];
+}
+
+// CHECK: return (Bits[arch::AssemblerCondition2]);
diff --git a/test/TableGen/MultiClassDefName.td b/test/TableGen/MultiClassDefName.td
index 811d92667eb2..fafa1ad3081b 100644
--- a/test/TableGen/MultiClassDefName.td
+++ b/test/TableGen/MultiClassDefName.td
@@ -39,3 +39,45 @@ multiclass MC2<string name> {
 
 defm : MC2<"bar">;
 
+multiclass MC3<string s> {
+  def ZFizz#s : C<s>;
+}
+
+defm : MC3<"Buzz">;
+
+// CHECK: def ZFizzBuzz
+// CHECK: string name = "Buzz";
+// CHECK-NOT: MC3::s
+
+multiclass MC4<string s> {
+  def NAME#s : C<s>;
+}
+
+defm ZTagazok : MC4<"AToi">;
+
+// CHECK: def ZTagazokAToi
+// CHECK: string name = "AToi";
+// CHECK-NOT: MC4::s
+
+multiclass MC5<C c> {
+  def NAME#c.name : C<c.name>;
+}
+
+def CTiger : C<"Tiger">;
+defm Zebra : MC5<CTiger>;
+
+// CHECK: def ZebraTiger
+// CHECK: string name = "Tiger";
+// CHECK-NOT: MC5::c
+
+multiclass MC6<C c> {
+  def NAME#Tiger#c.name : C<c.name>;
+}
+
+def CAligator : C<"Aligator">;
+defm Zebra : MC6<CAligator>;
+
+// CHECK: def ZebraTigerAligator
+// CHECK: string name = "Aligator";
+// CHECK-NOT: MC6::c
+
diff --git a/test/TableGen/intrinsic-varargs.td b/test/TableGen/intrinsic-varargs.td
index 935a62503803..380d79d4a22a 100644
--- a/test/TableGen/intrinsic-varargs.td
+++ b/test/TableGen/intrinsic-varargs.td
@@ -23,7 +23,7 @@ class Intrinsic<string name, list<LLVMType> param_types = []> {
 }
 
 // isVoid needs to match the definition in ValueTypes.td
-def isVoid : ValueType<0, 56>;   // Produces no value
+def isVoid : ValueType<0, 57>;   // Produces no value
 def llvm_vararg_ty : LLVMType<isVoid>;   // this means vararg here
 
 // CHECK: /* 0 */ 0, 28, 0,
diff --git a/test/Transforms/ADCE/2002-05-23-ZeroArgPHITest.ll b/test/Transforms/ADCE/2002-05-23-ZeroArgPHITest.ll
index 9407b5a68d69..8d1beec8ed35 100644
--- a/test/Transforms/ADCE/2002-05-23-ZeroArgPHITest.ll
+++ b/test/Transforms/ADCE/2002-05-23-ZeroArgPHITest.ll
@@ -15,14 +15,14 @@ bb0:
         br label %bb1
 
 bb1:            ; preds = %bb0
-        %reg107 = load %node_t** %nodelist.upgrd.1              ; <%node_t*> [#uses=2]
+        %reg107 = load %node_t*, %node_t** %nodelist.upgrd.1              ; <%node_t*> [#uses=2]
         %cond211 = icmp eq %node_t* %reg107, null               ; <i1> [#uses=1]
         br i1 %cond211, label %bb3, label %bb2
 
 bb2:            ; preds = %bb2, %bb1
         %reg109 = phi %node_t* [ %reg110, %bb2 ], [ %reg107, %bb1 ]             ; <%node_t*> [#uses=1]
-        %reg212 = getelementptr %node_t* %reg109, i64 0, i32 1          ; <%node_t**> [#uses=1]
-        %reg110 = load %node_t** %reg212                ; <%node_t*> [#uses=2]
+        %reg212 = getelementptr %node_t, %node_t* %reg109, i64 0, i32 1          ; <%node_t**> [#uses=1]
+        %reg110 = load %node_t*, %node_t** %reg212                ; <%node_t*> [#uses=2]
         %cond213 = icmp ne %node_t* %reg110, null               ; <i1> [#uses=1]
         br i1 %cond213, label %bb2, label %bb3
 
diff --git a/test/Transforms/ADCE/2002-05-28-Crash.ll b/test/Transforms/ADCE/2002-05-28-Crash.ll
index 9bbbd055ff96..d88580afad0a 100644
--- a/test/Transforms/ADCE/2002-05-28-Crash.ll
+++ b/test/Transforms/ADCE/2002-05-28-Crash.ll
@@ -15,7 +15,7 @@
 
 define i32 @rx_bitset_empty(i32 %size, i32* %set) {
 bb1:
-        %reg110 = load i32* %set                ; <i32> [#uses=2]
+        %reg110 = load i32, i32* %set                ; <i32> [#uses=2]
         store i32 1, i32* %set
         %cast112 = sext i32 %size to i64                ; <i64> [#uses=1]
         %reg113 = add i64 %cast112, 31          ; <i64> [#uses=1]
@@ -25,8 +25,8 @@ bb1:
         %reg114-idxcast = trunc i64 %reg114 to i32              ; <i32> [#uses=1]
         %reg114-idxcast-offset = add i32 %reg114-idxcast, 1073741823            ; <i32> [#uses=1]
         %reg114-idxcast-offset.upgrd.1 = zext i32 %reg114-idxcast-offset to i64         ; <i64> [#uses=1]
-        %reg124 = getelementptr i32* %set, i64 %reg114-idxcast-offset.upgrd.1           ; <i32*> [#uses=1]
-        %reg125 = load i32* %reg124             ; <i32> [#uses=1]
+        %reg124 = getelementptr i32, i32* %set, i64 %reg114-idxcast-offset.upgrd.1           ; <i32*> [#uses=1]
+        %reg125 = load i32, i32* %reg124             ; <i32> [#uses=1]
         %cond232 = icmp ne i32 %reg125, 0               ; <i1> [#uses=1]
         br i1 %cond232, label %bb3, label %bb2
 
@@ -38,8 +38,8 @@ bb2:            ; preds = %bb2, %bb1
         %reg130-idxcast = bitcast i32 %reg130 to i32            ; <i32> [#uses=1]
         %reg130-idxcast-offset = add i32 %reg130-idxcast, 1073741823            ; <i32> [#uses=1]
         %reg130-idxcast-offset.upgrd.2 = zext i32 %reg130-idxcast-offset to i64         ; <i64> [#uses=1]
-        %reg118 = getelementptr i32* %set, i64 %reg130-idxcast-offset.upgrd.2           ; <i32*> [#uses=1]
-        %reg119 = load i32* %reg118             ; <i32> [#uses=1]
+        %reg118 = getelementptr i32, i32* %set, i64 %reg130-idxcast-offset.upgrd.2           ; <i32*> [#uses=1]
+        %reg119 = load i32, i32* %reg118             ; <i32> [#uses=1]
         %cond233 = icmp eq i32 %reg119, 0               ; <i1> [#uses=1]
         br i1 %cond233, label %bb2, label %bb3
 
diff --git a/test/Transforms/ADCE/2002-07-17-AssertionFailure.ll b/test/Transforms/ADCE/2002-07-17-AssertionFailure.ll
index 8f8dadf7332f..ff8bdb3fd3b3 100644
--- a/test/Transforms/ADCE/2002-07-17-AssertionFailure.ll
+++ b/test/Transforms/ADCE/2002-07-17-AssertionFailure.ll
@@ -7,7 +7,7 @@
 
 define void @foo(i8* %reg5481) {
         %cast611 = bitcast i8* %reg5481 to i8**         ; <i8**> [#uses=1]
-        %reg162 = load i8** %cast611            ; <i8*> [#uses=1]
+        %reg162 = load i8*, i8** %cast611            ; <i8*> [#uses=1]
         ptrtoint i8* %reg162 to i32             ; <i32>:1 [#uses=0]
         ret void
 }
diff --git a/test/Transforms/ADCE/2002-07-17-PHIAssertion.ll b/test/Transforms/ADCE/2002-07-17-PHIAssertion.ll
index 2f0df670d6ac..1bf79e8ec6c7 100644
--- a/test/Transforms/ADCE/2002-07-17-PHIAssertion.ll
+++ b/test/Transforms/ADCE/2002-07-17-PHIAssertion.ll
@@ -17,7 +17,7 @@ bb3:            ; preds = %bb2
         br label %UnifiedExitNode
 
 bb4:            ; preds = %bb2
-        %reg117 = load i32* @hufts              ; <i32> [#uses=2]
+        %reg117 = load i32, i32* @hufts              ; <i32> [#uses=2]
         %cond241 = icmp ule i32 %reg117, %reg128                ; <i1> [#uses=1]
         br i1 %cond241, label %bb6, label %bb5
 
@@ -29,12 +29,12 @@ bb6:            ; preds = %bb5, %bb4
         br i1 false, label %bb2, label %bb7
 
 bb7:            ; preds = %bb6
-        %reg126 = load i32* @bk         ; <i32> [#uses=1]
+        %reg126 = load i32, i32* @bk         ; <i32> [#uses=1]
         %cond247 = icmp ule i32 %reg126, 7              ; <i1> [#uses=1]
         br i1 %cond247, label %bb9, label %bb8
 
 bb8:            ; preds = %bb8, %bb7
-        %reg119 = load i32* @bk         ; <i32> [#uses=1]
+        %reg119 = load i32, i32* @bk         ; <i32> [#uses=1]
         %cond256 = icmp ugt i32 %reg119, 7              ; <i1> [#uses=1]
         br i1 %cond256, label %bb8, label %bb9
 
diff --git a/test/Transforms/ADCE/2003-06-11-InvalidCFG.ll b/test/Transforms/ADCE/2003-06-11-InvalidCFG.ll
index 5206b243e372..7c7e238f9d99 100644
--- a/test/Transforms/ADCE/2003-06-11-InvalidCFG.ll
+++ b/test/Transforms/ADCE/2003-06-11-InvalidCFG.ll
@@ -16,7 +16,7 @@ then.66:                ; preds = %shortcirc_done.12
         br label %endif.42
 
 endif.65:               ; preds = %endif.42
-        %tmp.2846 = load i32** @G               ; <i32*> [#uses=1]
+        %tmp.2846 = load i32*, i32** @G               ; <i32*> [#uses=1]
         br i1 false, label %shortcirc_next.12, label %shortcirc_done.12
 
 shortcirc_next.12:              ; preds = %endif.65
diff --git a/test/Transforms/ADCE/2003-06-24-BadSuccessor.ll b/test/Transforms/ADCE/2003-06-24-BadSuccessor.ll
index eb3ef1e7913f..707e14aad0dd 100644
--- a/test/Transforms/ADCE/2003-06-24-BadSuccessor.ll
+++ b/test/Transforms/ADCE/2003-06-24-BadSuccessor.ll
@@ -48,8 +48,8 @@ shortcirc_next.4:		; preds = %then.44
 	br i1 false, label %no_exit.2, label %loopexit.2
 
 no_exit.2:		; preds = %shortcirc_next.4
-	%tmp.897 = getelementptr i32* %SubArrays.10, i64 0		; <i32*> [#uses=1]
-	%tmp.899 = load i32* %tmp.897		; <i32> [#uses=1]
+	%tmp.897 = getelementptr i32, i32* %SubArrays.10, i64 0		; <i32*> [#uses=1]
+	%tmp.899 = load i32, i32* %tmp.897		; <i32> [#uses=1]
 	store i32 %tmp.899, i32* null
 	ret i32 0
 
@@ -79,7 +79,7 @@ shortcirc_next.8:		; preds = %shortcirc_next.7
 
 then.53:		; preds = %shortcirc_next.7, %label.17
 	%SubArrays.8 = phi i32* [ %SubArrays.10, %shortcirc_next.7 ], [ %SubArrays.10, %label.17 ]		; <i32*> [#uses=1]
-	%tmp.1023 = load i32* null		; <i32> [#uses=1]
+	%tmp.1023 = load i32, i32* null		; <i32> [#uses=1]
 	switch i32 %tmp.1023, label %loopentry.1 [
 	]
 
diff --git a/test/Transforms/ADCE/2003-06-24-BasicFunctionality.ll b/test/Transforms/ADCE/2003-06-24-BasicFunctionality.ll
index 82fa5b2a40e1..f0de43164365 100644
--- a/test/Transforms/ADCE/2003-06-24-BasicFunctionality.ll
+++ b/test/Transforms/ADCE/2003-06-24-BasicFunctionality.ll
@@ -2,20 +2,20 @@
 
 define void @dead_test8(i32* %data.1, i32 %idx.1) {
 entry:
-        %tmp.1 = load i32* %data.1              ; <i32> [#uses=2]
+        %tmp.1 = load i32, i32* %data.1              ; <i32> [#uses=2]
         %tmp.41 = icmp sgt i32 %tmp.1, 0                ; <i1> [#uses=1]
         br i1 %tmp.41, label %no_exit.preheader, label %return
 
 no_exit.preheader:              ; preds = %entry
-        %tmp.11 = getelementptr i32* %data.1, i64 1             ; <i32*> [#uses=1]
+        %tmp.11 = getelementptr i32, i32* %data.1, i64 1             ; <i32*> [#uses=1]
         %tmp.22-idxcast = sext i32 %idx.1 to i64                ; <i64> [#uses=1]
-        %tmp.28 = getelementptr i32* %data.1, i64 %tmp.22-idxcast               ; <i32*> [#uses=1]
+        %tmp.28 = getelementptr i32, i32* %data.1, i64 %tmp.22-idxcast               ; <i32*> [#uses=1]
         br label %no_exit
 
 no_exit:                ; preds = %endif, %no_exit.preheader
         %k.1 = phi i32 [ %k.0, %endif ], [ 0, %no_exit.preheader ]              ; <i32> [#uses=3]
         %i.0 = phi i32 [ %inc.1, %endif ], [ 0, %no_exit.preheader ]            ; <i32> [#uses=1]
-        %tmp.12 = load i32* %tmp.11             ; <i32> [#uses=1]
+        %tmp.12 = load i32, i32* %tmp.11             ; <i32> [#uses=1]
         %tmp.14 = sub i32 0, %tmp.12            ; <i32> [#uses=1]
         %tmp.161 = icmp ne i32 %k.1, %tmp.14            ; <i1> [#uses=1]
         br i1 %tmp.161, label %then, label %else
diff --git a/test/Transforms/ADCE/basictest1.ll b/test/Transforms/ADCE/basictest1.ll
index bbb88783deb2..4d0d386384b9 100644
--- a/test/Transforms/ADCE/basictest1.ll
+++ b/test/Transforms/ADCE/basictest1.ll
@@ -22,12 +22,12 @@ declare i32 @fwrite(i8*, i32, i32, %FILE*)
 declare void @perror(i8*)
 
 define i32 @spec_getc(i32 %fd) {
-	%reg109 = load i32* @dbglvl		; <i32> [#uses=1]
+	%reg109 = load i32, i32* @dbglvl		; <i32> [#uses=1]
 	%cond266 = icmp sle i32 %reg109, 4		; <i1> [#uses=1]
 	br i1 %cond266, label %bb3, label %bb2
 
 bb2:		; preds = %0
-	%cast273 = getelementptr [17 x i8]* @.LC12, i64 0, i64 0		; <i8*> [#uses=0]
+	%cast273 = getelementptr [17 x i8], [17 x i8]* @.LC12, i64 0, i64 0		; <i8*> [#uses=0]
 	br label %bb3
 
 bb3:		; preds = %bb2, %0
@@ -35,8 +35,8 @@ bb3:		; preds = %bb2, %0
 	br i1 %cond267, label %bb5, label %bb4
 
 bb4:		; preds = %bb3
-	%reg111 = getelementptr [20 x %FILE]* @__iob, i64 0, i64 1, i32 3		; <i8*> [#uses=1]
-	%cast274 = getelementptr [34 x i8]* @.LC9, i64 0, i64 0		; <i8*> [#uses=0]
+	%reg111 = getelementptr [20 x %FILE], [20 x %FILE]* @__iob, i64 0, i64 1, i32 3		; <i8*> [#uses=1]
+	%cast274 = getelementptr [34 x i8], [34 x i8]* @.LC9, i64 0, i64 0		; <i8*> [#uses=0]
 	%cast282 = bitcast i8* %reg111 to %FILE*		; <%FILE*> [#uses=0]
 	call void @exit( i32 1 )
 	br label %UnifiedExitNode
@@ -44,21 +44,21 @@ bb4:		; preds = %bb3
 bb5:		; preds = %bb3
 	%reg107-idxcast1 = sext i32 %fd to i64		; <i64> [#uses=2]
 	%reg107-idxcast2 = sext i32 %fd to i64		; <i64> [#uses=1]
-	%reg1311 = getelementptr [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast2		; <%spec_fd_t*> [#uses=1]
-	%idx1 = getelementptr [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast1, i32 2		; <i32*> [#uses=1]
-	%reg1321 = load i32* %idx1		; <i32> [#uses=3]
-	%idx2 = getelementptr %spec_fd_t* %reg1311, i64 0, i32 1		; <i32*> [#uses=1]
-	%reg1331 = load i32* %idx2		; <i32> [#uses=1]
+	%reg1311 = getelementptr [3 x %spec_fd_t], [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast2		; <%spec_fd_t*> [#uses=1]
+	%idx1 = getelementptr [3 x %spec_fd_t], [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast1, i32 2		; <i32*> [#uses=1]
+	%reg1321 = load i32, i32* %idx1		; <i32> [#uses=3]
+	%idx2 = getelementptr %spec_fd_t, %spec_fd_t* %reg1311, i64 0, i32 1		; <i32*> [#uses=1]
+	%reg1331 = load i32, i32* %idx2		; <i32> [#uses=1]
 	%cond270 = icmp slt i32 %reg1321, %reg1331		; <i1> [#uses=1]
 	br i1 %cond270, label %bb9, label %bb6
 
 bb6:		; preds = %bb5
-	%reg134 = load i32* @dbglvl		; <i32> [#uses=1]
+	%reg134 = load i32, i32* @dbglvl		; <i32> [#uses=1]
 	%cond271 = icmp sle i32 %reg134, 4		; <i1> [#uses=1]
 	br i1 %cond271, label %bb8, label %bb7
 
 bb7:		; preds = %bb6
-	%cast277 = getelementptr [4 x i8]* @.LC10, i64 0, i64 0		; <i8*> [#uses=0]
+	%cast277 = getelementptr [4 x i8], [4 x i8]* @.LC10, i64 0, i64 0		; <i8*> [#uses=0]
 	br label %bb8
 
 bb8:		; preds = %bb7, %bb6
@@ -66,21 +66,21 @@ bb8:		; preds = %bb7, %bb6
 
 bb9:		; preds = %bb5
 	%reg107-idxcast3 = sext i32 %fd to i64		; <i64> [#uses=1]
-	%idx3 = getelementptr [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast3, i32 3		; <i8**> [#uses=1]
-	%reg1601 = load i8** %idx3		; <i8*> [#uses=1]
+	%idx3 = getelementptr [3 x %spec_fd_t], [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast3, i32 3		; <i8**> [#uses=1]
+	%reg1601 = load i8*, i8** %idx3		; <i8*> [#uses=1]
 	%reg132-idxcast1 = sext i32 %reg1321 to i64		; <i64> [#uses=1]
-	%idx4 = getelementptr i8* %reg1601, i64 %reg132-idxcast1		; <i8*> [#uses=1]
-	%reg1621 = load i8* %idx4		; <i8> [#uses=2]
+	%idx4 = getelementptr i8, i8* %reg1601, i64 %reg132-idxcast1		; <i8*> [#uses=1]
+	%reg1621 = load i8, i8* %idx4		; <i8> [#uses=2]
 	%cast108 = zext i8 %reg1621 to i64		; <i64> [#uses=0]
 	%reg157 = add i32 %reg1321, 1		; <i32> [#uses=1]
-	%idx5 = getelementptr [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast1, i32 2		; <i32*> [#uses=1]
+	%idx5 = getelementptr [3 x %spec_fd_t], [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast1, i32 2		; <i32*> [#uses=1]
 	store i32 %reg157, i32* %idx5
-	%reg163 = load i32* @dbglvl		; <i32> [#uses=1]
+	%reg163 = load i32, i32* @dbglvl		; <i32> [#uses=1]
 	%cond272 = icmp sle i32 %reg163, 4		; <i1> [#uses=1]
 	br i1 %cond272, label %bb11, label %bb10
 
 bb10:		; preds = %bb9
-	%cast279 = getelementptr [4 x i8]* @.LC11, i64 0, i64 0		; <i8*> [#uses=0]
+	%cast279 = getelementptr [4 x i8], [4 x i8]* @.LC11, i64 0, i64 0		; <i8*> [#uses=0]
 	br label %bb11
 
 bb11:		; preds = %bb10, %bb9
diff --git a/test/Transforms/ADCE/basictest2.ll b/test/Transforms/ADCE/basictest2.ll
index a17795f14246..26b2e85cccba 100644
--- a/test/Transforms/ADCE/basictest2.ll
+++ b/test/Transforms/ADCE/basictest2.ll
@@ -22,12 +22,12 @@ declare i32 @fwrite(i8*, i32, i32, %FILE*)
 declare void @perror(i8*)
 
 define i32 @spec_getc(i32 %fd) {
-	%reg109 = load i32* @dbglvl		; <i32> [#uses=1]
+	%reg109 = load i32, i32* @dbglvl		; <i32> [#uses=1]
 	%cond266 = icmp sle i32 %reg109, 4		; <i1> [#uses=1]
 	br i1 %cond266, label %bb3, label %bb2
 
 bb2:		; preds = %0
-	%cast273 = getelementptr [17 x i8]* @.LC12, i64 0, i64 0		; <i8*> [#uses=0]
+	%cast273 = getelementptr [17 x i8], [17 x i8]* @.LC12, i64 0, i64 0		; <i8*> [#uses=0]
 	br label %bb3
 
 bb3:		; preds = %bb2, %0
@@ -35,8 +35,8 @@ bb3:		; preds = %bb2, %0
 	br label %bb5
 
 bb4:		; No predecessors!
-	%reg111 = getelementptr [20 x %FILE]* @__iob, i64 0, i64 1, i32 3		; <i8*> [#uses=1]
-	%cast274 = getelementptr [34 x i8]* @.LC9, i64 0, i64 0		; <i8*> [#uses=0]
+	%reg111 = getelementptr [20 x %FILE], [20 x %FILE]* @__iob, i64 0, i64 1, i32 3		; <i8*> [#uses=1]
+	%cast274 = getelementptr [34 x i8], [34 x i8]* @.LC9, i64 0, i64 0		; <i8*> [#uses=0]
 	%cast282 = bitcast i8* %reg111 to %FILE*		; <%FILE*> [#uses=0]
 	call void @exit( i32 1 )
 	br label %UnifiedExitNode
@@ -44,21 +44,21 @@ bb4:		; No predecessors!
 bb5:		; preds = %bb3
 	%reg107-idxcast1 = sext i32 %fd to i64		; <i64> [#uses=2]
 	%reg107-idxcast2 = sext i32 %fd to i64		; <i64> [#uses=1]
-	%reg1311 = getelementptr [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast2		; <%spec_fd_t*> [#uses=1]
-	%idx1 = getelementptr [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast1, i32 2		; <i32*> [#uses=1]
-	%reg1321 = load i32* %idx1		; <i32> [#uses=3]
-	%idx2 = getelementptr %spec_fd_t* %reg1311, i64 0, i32 1		; <i32*> [#uses=1]
-	%reg1331 = load i32* %idx2		; <i32> [#uses=1]
+	%reg1311 = getelementptr [3 x %spec_fd_t], [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast2		; <%spec_fd_t*> [#uses=1]
+	%idx1 = getelementptr [3 x %spec_fd_t], [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast1, i32 2		; <i32*> [#uses=1]
+	%reg1321 = load i32, i32* %idx1		; <i32> [#uses=3]
+	%idx2 = getelementptr %spec_fd_t, %spec_fd_t* %reg1311, i64 0, i32 1		; <i32*> [#uses=1]
+	%reg1331 = load i32, i32* %idx2		; <i32> [#uses=1]
 	%cond270 = icmp slt i32 %reg1321, %reg1331		; <i1> [#uses=1]
 	br i1 %cond270, label %bb9, label %bb6
 
 bb6:		; preds = %bb5
-	%reg134 = load i32* @dbglvl		; <i32> [#uses=1]
+	%reg134 = load i32, i32* @dbglvl		; <i32> [#uses=1]
 	%cond271 = icmp sle i32 %reg134, 4		; <i1> [#uses=1]
 	br i1 %cond271, label %bb8, label %bb7
 
 bb7:		; preds = %bb6
-	%cast277 = getelementptr [4 x i8]* @.LC10, i64 0, i64 0		; <i8*> [#uses=0]
+	%cast277 = getelementptr [4 x i8], [4 x i8]* @.LC10, i64 0, i64 0		; <i8*> [#uses=0]
 	br label %bb8
 
 bb8:		; preds = %bb7, %bb6
@@ -66,21 +66,21 @@ bb8:		; preds = %bb7, %bb6
 
 bb9:		; preds = %bb5
 	%reg107-idxcast3 = sext i32 %fd to i64		; <i64> [#uses=1]
-	%idx3 = getelementptr [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast3, i32 3		; <i8**> [#uses=1]
-	%reg1601 = load i8** %idx3		; <i8*> [#uses=1]
+	%idx3 = getelementptr [3 x %spec_fd_t], [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast3, i32 3		; <i8**> [#uses=1]
+	%reg1601 = load i8*, i8** %idx3		; <i8*> [#uses=1]
 	%reg132-idxcast1 = sext i32 %reg1321 to i64		; <i64> [#uses=1]
-	%idx4 = getelementptr i8* %reg1601, i64 %reg132-idxcast1		; <i8*> [#uses=1]
-	%reg1621 = load i8* %idx4		; <i8> [#uses=2]
+	%idx4 = getelementptr i8, i8* %reg1601, i64 %reg132-idxcast1		; <i8*> [#uses=1]
+	%reg1621 = load i8, i8* %idx4		; <i8> [#uses=2]
 	%cast108 = zext i8 %reg1621 to i64		; <i64> [#uses=0]
 	%reg157 = add i32 %reg1321, 1		; <i32> [#uses=1]
-	%idx5 = getelementptr [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast1, i32 2		; <i32*> [#uses=1]
+	%idx5 = getelementptr [3 x %spec_fd_t], [3 x %spec_fd_t]* @spec_fd, i64 0, i64 %reg107-idxcast1, i32 2		; <i32*> [#uses=1]
 	store i32 %reg157, i32* %idx5
-	%reg163 = load i32* @dbglvl		; <i32> [#uses=1]
+	%reg163 = load i32, i32* @dbglvl		; <i32> [#uses=1]
 	%cond272 = icmp sle i32 %reg163, 4		; <i1> [#uses=1]
 	br i1 %cond272, label %bb11, label %bb10
 
 bb10:		; preds = %bb9
-	%cast279 = getelementptr [4 x i8]* @.LC11, i64 0, i64 0		; <i8*> [#uses=0]
+	%cast279 = getelementptr [4 x i8], [4 x i8]* @.LC11, i64 0, i64 0		; <i8*> [#uses=0]
 	br label %bb11
 
 bb11:		; preds = %bb10, %bb9
diff --git a/test/Transforms/AddDiscriminators/basic.ll b/test/Transforms/AddDiscriminators/basic.ll
index 7c8b3d3a7ce8..cabf707fe5d6 100644
--- a/test/Transforms/AddDiscriminators/basic.ll
+++ b/test/Transforms/AddDiscriminators/basic.ll
@@ -16,22 +16,23 @@ entry:
   %i.addr = alloca i32, align 4
   %x = alloca i32, align 4
   store i32 %i, i32* %i.addr, align 4
-  %0 = load i32* %i.addr, align 4, !dbg !10
+  %0 = load i32, i32* %i.addr, align 4, !dbg !10
   %cmp = icmp slt i32 %0, 10, !dbg !10
   br i1 %cmp, label %if.then, label %if.end, !dbg !10
 
 if.then:                                          ; preds = %entry
-  %1 = load i32* %i.addr, align 4, !dbg !10
-; CHECK:  %1 = load i32* %i.addr, align 4, !dbg !12
+  %1 = load i32, i32* %i.addr, align 4, !dbg !10
+; CHECK:  %1 = load i32, i32* %i.addr, align 4, !dbg ![[THEN:[0-9]+]]
 
   store i32 %1, i32* %x, align 4, !dbg !10
-; CHECK:  store i32 %1, i32* %x, align 4, !dbg !12
+; CHECK:  store i32 %1, i32* %x, align 4, !dbg ![[THEN]]
 
   br label %if.end, !dbg !10
-; CHECK:   br label %if.end, !dbg !12
+; CHECK:   br label %if.end, !dbg ![[THEN]]
 
 if.end:                                           ; preds = %if.then, %entry
   ret void, !dbg !12
+; CHECK:   ret void, !dbg ![[END:[0-9]+]]
 }
 
 attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
@@ -40,20 +41,22 @@ attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointe
 !llvm.module.flags = !{!7, !8}
 !llvm.ident = !{!9}
 
-!0 = !{!"0x11\0012\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [basic.c] [DW_LANG_C99]
-!1 = !{!"basic.c", !"."}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "basic.c", directory: ".")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, void (i32)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [basic.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void (i32)* @foo, variables: !2)
+!5 = !DIFile(filename: "basic.c", directory: ".")
+!6 = !DISubroutineType(types: !2)
 !7 = !{i32 2, !"Dwarf Version", i32 4}
-!8 = !{i32 1, !"Debug Info Version", i32 2}
+!8 = !{i32 1, !"Debug Info Version", i32 3}
 !9 = !{!"clang version 3.5 "}
-!10 = !MDLocation(line: 3, scope: !11)
-!11 = !{!"0xb\003\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [basic.c]
-!12 = !MDLocation(line: 4, scope: !4)
-
-; CHECK: !12 = !MDLocation(line: 3, scope: !13)
-; CHECK: !13 = !{!"0xb\001", !1, !11} ; [ DW_TAG_lexical_block ] [./basic.c]
-; CHECK: !14 = !MDLocation(line: 4, scope: !4)
+!10 = !DILocation(line: 3, scope: !11)
+!11 = distinct !DILexicalBlock(line: 3, column: 0, file: !1, scope: !4)
+!12 = !DILocation(line: 4, scope: !4)
+
+; CHECK: ![[FOO:[0-9]+]] = !DISubprogram(name: "foo"
+; CHECK: ![[BLOCK:[0-9]+]] = distinct !DILexicalBlock(scope: ![[FOO]],{{.*}} line: 3)
+; CHECK: ![[THEN]] = !DILocation(line: 3, scope: ![[BLOCKFILE:[0-9]+]])
+; CHECK: ![[BLOCKFILE]] = !DILexicalBlockFile(scope: ![[BLOCK]],{{.*}} discriminator: 1)
+; CHECK: ![[END]] = !DILocation(line: 4, scope: ![[FOO]])
diff --git a/test/Transforms/AddDiscriminators/first-only.ll b/test/Transforms/AddDiscriminators/first-only.ll
index 153cfc8a44cc..7f1ea2b15cf6 100644
--- a/test/Transforms/AddDiscriminators/first-only.ll
+++ b/test/Transforms/AddDiscriminators/first-only.ll
@@ -19,29 +19,29 @@ entry:
   %x = alloca i32, align 4
   %y = alloca i32, align 4
   store i32 %i, i32* %i.addr, align 4
-  %0 = load i32* %i.addr, align 4, !dbg !10
+  %0 = load i32, i32* %i.addr, align 4, !dbg !10
   %cmp = icmp slt i32 %0, 10, !dbg !10
   br i1 %cmp, label %if.then, label %if.end, !dbg !10
 
 if.then:                                          ; preds = %entry
-  %1 = load i32* %i.addr, align 4, !dbg !12
+  %1 = load i32, i32* %i.addr, align 4, !dbg !12
   store i32 %1, i32* %x, align 4, !dbg !12
 
-  %2 = load i32* %i.addr, align 4, !dbg !14
-; CHECK:  %2 = load i32* %i.addr, align 4, !dbg !15
+  %2 = load i32, i32* %i.addr, align 4, !dbg !14
+; CHECK:  %2 = load i32, i32* %i.addr, align 4, !dbg ![[THEN:[0-9]+]]
 
   %sub = sub nsw i32 0, %2, !dbg !14
-; CHECK:  %sub = sub nsw i32 0, %2, !dbg !15
+; CHECK:  %sub = sub nsw i32 0, %2, !dbg ![[THEN]]
 
   store i32 %sub, i32* %y, align 4, !dbg !14
-; CHECK:  store i32 %sub, i32* %y, align 4, !dbg !15
+; CHECK:  store i32 %sub, i32* %y, align 4, !dbg ![[THEN]]
 
   br label %if.end, !dbg !15
-; CHECK:  br label %if.end, !dbg !16
+; CHECK:  br label %if.end, !dbg ![[BR:[0-9]+]]
 
 if.end:                                           ; preds = %if.then, %entry
   ret void, !dbg !16
-; CHECK:  ret void, !dbg !17
+; CHECK:  ret void, !dbg ![[END:[0-9]+]]
 }
 
 attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
@@ -50,33 +50,34 @@ attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointe
 !llvm.module.flags = !{!7, !8}
 !llvm.ident = !{!9}
 
-!0 = !{!"0x11\0012\00clang version 3.5 (trunk 199750) (llvm/trunk 199751)\000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [first-only.c] [DW_LANG_C99]
-!1 = !{!"first-only.c", !"."}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 (trunk 199750) (llvm/trunk 199751)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "first-only.c", directory: ".")
+!2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, void (i32)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [first-only.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void (i32)* @foo, variables: !2)
+!5 = !DIFile(filename: "first-only.c", directory: ".")
+!6 = !DISubroutineType(types: !{null})
 !7 = !{i32 2, !"Dwarf Version", i32 4}
-!8 = !{i32 1, !"Debug Info Version", i32 2}
+!8 = !{i32 1, !"Debug Info Version", i32 3}
 !9 = !{!"clang version 3.5 (trunk 199750) (llvm/trunk 199751)"}
-!10 = !MDLocation(line: 3, scope: !11)
+!10 = !DILocation(line: 3, scope: !11)
 
-!11 = !{!"0xb\003\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [first-only.c]
-; CHECK: !11 = !{!"0xb\003\000\000", !1, !4}
+!11 = distinct !DILexicalBlock(line: 3, column: 0, file: !1, scope: !4)
+; CHECK: ![[FOO:[0-9]+]] = !DISubprogram(name: "foo"
+; CHECK: ![[BLOCK1:[0-9]+]] = distinct !DILexicalBlock(scope: ![[FOO]],{{.*}} line: 3)
 
-!12 = !MDLocation(line: 3, scope: !13)
+!12 = !DILocation(line: 3, scope: !13)
 
-!13 = !{!"0xb\003\000\001", !1, !11} ; [ DW_TAG_lexical_block ] [first-only.c]
-; CHECK: !13 = !{!"0xb\001", !1, !14} ; [ DW_TAG_lexical_block ] [./first-only.c]
+!13 = distinct !DILexicalBlock(line: 3, column: 0, file: !1, scope: !11)
+; CHECK: !DILexicalBlockFile(scope: ![[BLOCK2:[0-9]+]],{{.*}} discriminator: 1)
 
-!14 = !MDLocation(line: 4, scope: !13)
-; CHECK: !14 = !{!"0xb\003\000\001", !1, !11}
+!14 = !DILocation(line: 4, scope: !13)
+; CHECK: ![[BLOCK2]] = distinct !DILexicalBlock(scope: ![[BLOCK1]],{{.*}} line: 3)
 
-!15 = !MDLocation(line: 5, scope: !13)
-; CHECK: !15 = !MDLocation(line: 4, scope: !14)
+!15 = !DILocation(line: 5, scope: !13)
+; CHECK: ![[THEN]] = !DILocation(line: 4, scope: ![[BLOCK2]])
 
-!16 = !MDLocation(line: 6, scope: !4)
-; CHECK: !16 = !MDLocation(line: 5, scope: !14)
-; CHECK: !17 = !MDLocation(line: 6, scope: !4)
+!16 = !DILocation(line: 6, scope: !4)
+; CHECK: ![[BR]] = !DILocation(line: 5, scope: ![[BLOCK2]])
+; CHECK: ![[END]] = !DILocation(line: 6, scope: ![[FOO]])
 
diff --git a/test/Transforms/AddDiscriminators/multiple.ll b/test/Transforms/AddDiscriminators/multiple.ll
index 5e552a87bbb2..621a7117571c 100644
--- a/test/Transforms/AddDiscriminators/multiple.ll
+++ b/test/Transforms/AddDiscriminators/multiple.ll
@@ -15,29 +15,29 @@ entry:
   %i.addr = alloca i32, align 4
   %x = alloca i32, align 4
   store i32 %i, i32* %i.addr, align 4
-  %0 = load i32* %i.addr, align 4, !dbg !10
+  %0 = load i32, i32* %i.addr, align 4, !dbg !10
   %cmp = icmp slt i32 %0, 10, !dbg !10
   br i1 %cmp, label %if.then, label %if.else, !dbg !10
 
 if.then:                                          ; preds = %entry
-  %1 = load i32* %i.addr, align 4, !dbg !10
-; CHECK:  %1 = load i32* %i.addr, align 4, !dbg !12
+  %1 = load i32, i32* %i.addr, align 4, !dbg !10
+; CHECK:  %1 = load i32, i32* %i.addr, align 4, !dbg ![[THEN:[0-9]+]]
 
   store i32 %1, i32* %x, align 4, !dbg !10
-; CHECK:  store i32 %1, i32* %x, align 4, !dbg !12
+; CHECK:  store i32 %1, i32* %x, align 4, !dbg ![[THEN]]
 
   br label %if.end, !dbg !10
-; CHECK:  br label %if.end, !dbg !12
+; CHECK:  br label %if.end, !dbg ![[THEN]]
 
 if.else:                                          ; preds = %entry
-  %2 = load i32* %i.addr, align 4, !dbg !10
-; CHECK:  %2 = load i32* %i.addr, align 4, !dbg !14
+  %2 = load i32, i32* %i.addr, align 4, !dbg !10
+; CHECK:  %2 = load i32, i32* %i.addr, align 4, !dbg ![[ELSE:[0-9]+]]
 
   %sub = sub nsw i32 0, %2, !dbg !10
-; CHECK:  %sub = sub nsw i32 0, %2, !dbg !14
+; CHECK:  %sub = sub nsw i32 0, %2, !dbg ![[ELSE]]
 
   store i32 %sub, i32* %x, align 4, !dbg !10
-; CHECK:  store i32 %sub, i32* %x, align 4, !dbg !14
+; CHECK:  store i32 %sub, i32* %x, align 4, !dbg ![[ELSE]]
 
   br label %if.end
 
@@ -51,21 +51,22 @@ attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointe
 !llvm.module.flags = !{!7, !8}
 !llvm.ident = !{!9}
 
-!0 = !{!"0x11\0012\00clang version 3.5 (trunk 199750) (llvm/trunk 199751)\000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [multiple.c] [DW_LANG_C99]
-!1 = !{!"multiple.c", !"."}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 (trunk 199750) (llvm/trunk 199751)", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "multiple.c", directory: ".")
+!2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, void (i32)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [multiple.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void (i32)* @foo, variables: !2)
+!5 = !DIFile(filename: "multiple.c", directory: ".")
+!6 = !DISubroutineType(types: !{null, !13})
+!13 = !DIBasicType(encoding: DW_ATE_signed, name: "int", size: 32, align: 32)
 !7 = !{i32 2, !"Dwarf Version", i32 4}
-!8 = !{i32 1, !"Debug Info Version", i32 2}
+!8 = !{i32 1, !"Debug Info Version", i32 3}
 !9 = !{!"clang version 3.5 (trunk 199750) (llvm/trunk 199751)"}
-!10 = !MDLocation(line: 3, scope: !11)
-!11 = !{!"0xb\003\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [multiple.c]
-!12 = !MDLocation(line: 4, scope: !4)
+!10 = !DILocation(line: 3, scope: !11)
+!11 = distinct !DILexicalBlock(line: 3, column: 0, file: !1, scope: !4)
+!12 = !DILocation(line: 4, scope: !4)
 
-; CHECK: !12 = !MDLocation(line: 3, scope: !13)
-; CHECK: !13 = !{!"0xb\001", !1, !11} ; [ DW_TAG_lexical_block ] [./multiple.c]
-; CHECK: !14 = !MDLocation(line: 3, scope: !15)
-; CHECK: !15 = !{!"0xb\002", !1, !11} ; [ DW_TAG_lexical_block ] [./multiple.c]
+; CHECK: ![[THEN]] = !DILocation(line: 3, scope: ![[THENBLOCK:[0-9]+]])
+; CHECK: ![[THENBLOCK]] = !DILexicalBlockFile(scope: ![[SCOPE:[0-9]+]],{{.*}} discriminator: 1)
+; CHECK: ![[ELSE]] = !DILocation(line: 3, scope: ![[ELSEBLOCK:[0-9]+]])
+; CHECK: ![[ELSEBLOCK]] = !DILexicalBlockFile(scope: ![[SCOPE]],{{.*}} discriminator: 2)
diff --git a/test/Transforms/AddDiscriminators/no-discriminators.ll b/test/Transforms/AddDiscriminators/no-discriminators.ll
index dd7faf0a71e3..895967e73b4d 100644
--- a/test/Transforms/AddDiscriminators/no-discriminators.ll
+++ b/test/Transforms/AddDiscriminators/no-discriminators.ll
@@ -17,13 +17,13 @@ entry:
   %retval = alloca i32, align 4
   %i.addr = alloca i64, align 8
   store i64 %i, i64* %i.addr, align 8
-  call void @llvm.dbg.declare(metadata i64* %i.addr, metadata !13, metadata !{}), !dbg !14
-  %0 = load i64* %i.addr, align 8, !dbg !15
-; CHECK:  %0 = load i64* %i.addr, align 8, !dbg !15
+  call void @llvm.dbg.declare(metadata i64* %i.addr, metadata !13, metadata !DIExpression()), !dbg !14
+  %0 = load i64, i64* %i.addr, align 8, !dbg !15
+; CHECK:  %0 = load i64, i64* %i.addr, align 8, !dbg ![[ENTRY:[0-9]+]]
   %cmp = icmp slt i64 %0, 5, !dbg !15
-; CHECK:  %cmp = icmp slt i64 %0, 5, !dbg !15
+; CHECK:  %cmp = icmp slt i64 %0, 5, !dbg ![[ENTRY:[0-9]+]]
   br i1 %cmp, label %if.then, label %if.else, !dbg !15
-; CHECK:  br i1 %cmp, label %if.then, label %if.else, !dbg !15
+; CHECK:  br i1 %cmp, label %if.then, label %if.else, !dbg ![[ENTRY:[0-9]+]]
 
 if.then:                                          ; preds = %entry
   store i32 2, i32* %retval, !dbg !15
@@ -34,7 +34,7 @@ if.else:                                          ; preds = %entry
   br label %return, !dbg !15
 
 return:                                           ; preds = %if.else, %if.then
-  %1 = load i32* %retval, !dbg !17
+  %1 = load i32, i32* %retval, !dbg !17
   ret i32 %1, !dbg !17
 }
 
@@ -48,24 +48,25 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!10, !11}
 !llvm.ident = !{!12}
 
-!0 = !{!"0x11\0012\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [./no-discriminators] [DW_LANG_C99]
-!1 = !{!"no-discriminators", !"."}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "no-discriminators", directory: ".")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, i32 (i64)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [./no-discriminators]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 (i64)* @foo, variables: !2)
+; CHECK: ![[FOO:[0-9]+]] = !DISubprogram(name: "foo"
+!5 = !DIFile(filename: "no-discriminators", directory: ".")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !9}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0x24\00long int\000\0064\0064\000\000\005", null, null} ; [ DW_TAG_base_type ] [long int] [line 0, size 64, align 64, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "long int", size: 64, align: 64, encoding: DW_ATE_signed)
 !10 = !{i32 2, !"Dwarf Version", i32 2}
-; CHECK: !10 = !{i32 2, !"Dwarf Version", i32 2}
-!11 = !{i32 1, !"Debug Info Version", i32 2}
+; CHECK: !{i32 2, !"Dwarf Version", i32 2}
+!11 = !{i32 1, !"Debug Info Version", i32 3}
 !12 = !{!"clang version 3.5.0 "}
-!13 = !{!"0x101\00i\0016777217\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [i] [line 1]
-!14 = !MDLocation(line: 1, scope: !4)
-!15 = !MDLocation(line: 2, scope: !16)
-; CHECK: !15 = !MDLocation(line: 2, scope: !16)
-!16 = !{!"0xb\002\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [./no-discriminators]
-; CHECK: !16 = !{!"0xb\002\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [./no-discriminators]
-!17 = !MDLocation(line: 3, scope: !4)
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 1, arg: 1, scope: !4, file: !5, type: !9)
+!14 = !DILocation(line: 1, scope: !4)
+!15 = !DILocation(line: 2, scope: !16)
+; CHECK: ![[ENTRY]] = !DILocation(line: 2, scope: ![[BLOCK:[0-9]+]])
+!16 = distinct !DILexicalBlock(line: 2, column: 0, file: !1, scope: !4)
+; CHECK: ![[BLOCK]] = distinct !DILexicalBlock(scope: ![[FOO]],{{.*}} line: 2)
+!17 = !DILocation(line: 3, scope: !4)
diff --git a/test/Transforms/AlignmentFromAssumptions/simple.ll b/test/Transforms/AlignmentFromAssumptions/simple.ll
index 884c8bad02f5..851e6dc3ccc6 100644
--- a/test/Transforms/AlignmentFromAssumptions/simple.ll
+++ b/test/Transforms/AlignmentFromAssumptions/simple.ll
@@ -7,11 +7,11 @@ entry:
   %maskedptr = and i64 %ptrint, 31
   %maskcond = icmp eq i64 %maskedptr, 0
   tail call void @llvm.assume(i1 %maskcond)
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   ret i32 %0
 
 ; CHECK-LABEL: @foo
-; CHECK: load i32* {{[^,]+}}, align 32
+; CHECK: load i32, i32* {{[^,]+}}, align 32
 ; CHECK: ret i32
 }
 
@@ -22,12 +22,12 @@ entry:
   %maskedptr = and i64 %offsetptr, 31
   %maskcond = icmp eq i64 %maskedptr, 0
   tail call void @llvm.assume(i1 %maskcond)
-  %arrayidx = getelementptr inbounds i32* %a, i64 2
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 2
+  %0 = load i32, i32* %arrayidx, align 4
   ret i32 %0
 
 ; CHECK-LABEL: @foo2
-; CHECK: load i32* {{[^,]+}}, align 16
+; CHECK: load i32, i32* {{[^,]+}}, align 16
 ; CHECK: ret i32
 }
 
@@ -38,12 +38,12 @@ entry:
   %maskedptr = and i64 %offsetptr, 31
   %maskcond = icmp eq i64 %maskedptr, 0
   tail call void @llvm.assume(i1 %maskcond)
-  %arrayidx = getelementptr inbounds i32* %a, i64 -1
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 -1
+  %0 = load i32, i32* %arrayidx, align 4
   ret i32 %0
 
 ; CHECK-LABEL: @foo2a
-; CHECK: load i32* {{[^,]+}}, align 32
+; CHECK: load i32, i32* {{[^,]+}}, align 32
 ; CHECK: ret i32
 }
 
@@ -53,11 +53,11 @@ entry:
   %maskedptr = and i64 %ptrint, 31
   %maskcond = icmp eq i64 %maskedptr, 0
   tail call void @llvm.assume(i1 %maskcond)
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   ret i32 %0
 
 ; CHECK-LABEL: @goo
-; CHECK: load i32* {{[^,]+}}, align 32
+; CHECK: load i32, i32* {{[^,]+}}, align 32
 ; CHECK: ret i32
 }
 
@@ -72,8 +72,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %r.06 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %r.06
   %indvars.iv.next = add i64 %indvars.iv, 8
   %1 = trunc i64 %indvars.iv.next to i32
@@ -85,7 +85,7 @@ for.end:                                          ; preds = %for.body
   ret i32 %add.lcssa
 
 ; CHECK-LABEL: @hoo
-; CHECK: load i32* %arrayidx, align 32
+; CHECK: load i32, i32* %arrayidx, align 32
 ; CHECK: ret i32 %add.lcssa
 }
 
@@ -100,8 +100,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ 4, %entry ], [ %indvars.iv.next, %for.body ]
   %r.06 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %r.06
   %indvars.iv.next = add i64 %indvars.iv, 8
   %1 = trunc i64 %indvars.iv.next to i32
@@ -113,7 +113,7 @@ for.end:                                          ; preds = %for.body
   ret i32 %add.lcssa
 
 ; CHECK-LABEL: @joo
-; CHECK: load i32* %arrayidx, align 16
+; CHECK: load i32, i32* %arrayidx, align 16
 ; CHECK: ret i32 %add.lcssa
 }
 
@@ -128,8 +128,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %r.06 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %r.06
   %indvars.iv.next = add i64 %indvars.iv, 4
   %1 = trunc i64 %indvars.iv.next to i32
@@ -141,7 +141,7 @@ for.end:                                          ; preds = %for.body
   ret i32 %add.lcssa
 
 ; CHECK-LABEL: @koo
-; CHECK: load i32* %arrayidx, align 16
+; CHECK: load i32, i32* %arrayidx, align 16
 ; CHECK: ret i32 %add.lcssa
 }
 
@@ -156,8 +156,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ -4, %entry ], [ %indvars.iv.next, %for.body ]
   %r.06 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %r.06
   %indvars.iv.next = add i64 %indvars.iv, 4
   %1 = trunc i64 %indvars.iv.next to i32
@@ -169,7 +169,7 @@ for.end:                                          ; preds = %for.body
   ret i32 %add.lcssa
 
 ; CHECK-LABEL: @koo2
-; CHECK: load i32* %arrayidx, align 16
+; CHECK: load i32, i32* %arrayidx, align 16
 ; CHECK: ret i32 %add.lcssa
 }
 
diff --git a/test/Transforms/AlignmentFromAssumptions/simple32.ll b/test/Transforms/AlignmentFromAssumptions/simple32.ll
index 166e7ef38936..2edc2e95f41a 100644
--- a/test/Transforms/AlignmentFromAssumptions/simple32.ll
+++ b/test/Transforms/AlignmentFromAssumptions/simple32.ll
@@ -7,11 +7,11 @@ entry:
   %maskedptr = and i64 %ptrint, 31
   %maskcond = icmp eq i64 %maskedptr, 0
   tail call void @llvm.assume(i1 %maskcond)
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   ret i32 %0
 
 ; CHECK-LABEL: @foo
-; CHECK: load i32* {{[^,]+}}, align 32
+; CHECK: load i32, i32* {{[^,]+}}, align 32
 ; CHECK: ret i32
 }
 
@@ -22,12 +22,12 @@ entry:
   %maskedptr = and i64 %offsetptr, 31
   %maskcond = icmp eq i64 %maskedptr, 0
   tail call void @llvm.assume(i1 %maskcond)
-  %arrayidx = getelementptr inbounds i32* %a, i64 2
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 2
+  %0 = load i32, i32* %arrayidx, align 4
   ret i32 %0
 
 ; CHECK-LABEL: @foo2
-; CHECK: load i32* {{[^,]+}}, align 16
+; CHECK: load i32, i32* {{[^,]+}}, align 16
 ; CHECK: ret i32
 }
 
@@ -38,12 +38,12 @@ entry:
   %maskedptr = and i64 %offsetptr, 31
   %maskcond = icmp eq i64 %maskedptr, 0
   tail call void @llvm.assume(i1 %maskcond)
-  %arrayidx = getelementptr inbounds i32* %a, i64 -1
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 -1
+  %0 = load i32, i32* %arrayidx, align 4
   ret i32 %0
 
 ; CHECK-LABEL: @foo2a
-; CHECK: load i32* {{[^,]+}}, align 32
+; CHECK: load i32, i32* {{[^,]+}}, align 32
 ; CHECK: ret i32
 }
 
@@ -53,11 +53,11 @@ entry:
   %maskedptr = and i64 %ptrint, 31
   %maskcond = icmp eq i64 %maskedptr, 0
   tail call void @llvm.assume(i1 %maskcond)
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   ret i32 %0
 
 ; CHECK-LABEL: @goo
-; CHECK: load i32* {{[^,]+}}, align 32
+; CHECK: load i32, i32* {{[^,]+}}, align 32
 ; CHECK: ret i32
 }
 
@@ -72,8 +72,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %r.06 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %r.06
   %indvars.iv.next = add i64 %indvars.iv, 8
   %1 = trunc i64 %indvars.iv.next to i32
@@ -85,7 +85,7 @@ for.end:                                          ; preds = %for.body
   ret i32 %add.lcssa
 
 ; CHECK-LABEL: @hoo
-; CHECK: load i32* %arrayidx, align 32
+; CHECK: load i32, i32* %arrayidx, align 32
 ; CHECK: ret i32 %add.lcssa
 }
 
@@ -100,8 +100,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ 4, %entry ], [ %indvars.iv.next, %for.body ]
   %r.06 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %r.06
   %indvars.iv.next = add i64 %indvars.iv, 8
   %1 = trunc i64 %indvars.iv.next to i32
@@ -113,7 +113,7 @@ for.end:                                          ; preds = %for.body
   ret i32 %add.lcssa
 
 ; CHECK-LABEL: @joo
-; CHECK: load i32* %arrayidx, align 16
+; CHECK: load i32, i32* %arrayidx, align 16
 ; CHECK: ret i32 %add.lcssa
 }
 
@@ -128,8 +128,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %r.06 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %r.06
   %indvars.iv.next = add i64 %indvars.iv, 4
   %1 = trunc i64 %indvars.iv.next to i32
@@ -141,7 +141,7 @@ for.end:                                          ; preds = %for.body
   ret i32 %add.lcssa
 
 ; CHECK-LABEL: @koo
-; CHECK: load i32* %arrayidx, align 16
+; CHECK: load i32, i32* %arrayidx, align 16
 ; CHECK: ret i32 %add.lcssa
 }
 
@@ -156,8 +156,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ -4, %entry ], [ %indvars.iv.next, %for.body ]
   %r.06 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %r.06
   %indvars.iv.next = add i64 %indvars.iv, 4
   %1 = trunc i64 %indvars.iv.next to i32
@@ -169,7 +169,7 @@ for.end:                                          ; preds = %for.body
   ret i32 %add.lcssa
 
 ; CHECK-LABEL: @koo2
-; CHECK: load i32* %arrayidx, align 16
+; CHECK: load i32, i32* %arrayidx, align 16
 ; CHECK: ret i32 %add.lcssa
 }
 
diff --git a/test/Transforms/AlignmentFromAssumptions/start-unk.ll b/test/Transforms/AlignmentFromAssumptions/start-unk.ll
index b7fe24947cb5..99533cf6ccb9 100644
--- a/test/Transforms/AlignmentFromAssumptions/start-unk.ll
+++ b/test/Transforms/AlignmentFromAssumptions/start-unk.ll
@@ -79,13 +79,13 @@ if.then126:                                       ; preds = %if.end123
   %maskcond.i.i187 = icmp eq i64 %maskedptr.i.i186, 0
   tail call void @llvm.assume(i1 %maskcond.i.i187) #0
   %ret.0..sroa_cast.i.i188 = bitcast %type1* undef to i32*
-  %ret.0.copyload.i.i189 = load i32* %ret.0..sroa_cast.i.i188, align 2
+  %ret.0.copyload.i.i189 = load i32, i32* %ret.0..sroa_cast.i.i188, align 2
 
 ; CHECK: load {{.*}} align 2
 
   %0 = tail call i32 @llvm.bswap.i32(i32 %ret.0.copyload.i.i189) #0
   %conv131 = zext i32 %0 to i64
-  %add.ptr132 = getelementptr inbounds i8* undef, i64 %conv131
+  %add.ptr132 = getelementptr inbounds i8, i8* undef, i64 %conv131
   %1 = bitcast i8* %add.ptr132 to %type1*
   br i1 undef, label %if.end150, label %if.end.i173
 
@@ -113,11 +113,11 @@ for.body137:                                      ; preds = %test1b.exit, %for.b
   br i1 undef, label %for.body137.if.end146_crit_edge, label %if.then140
 
 for.body137.if.end146_crit_edge:                  ; preds = %for.body137
-  %incdec.ptr = getelementptr inbounds %type1* %ShndxTable.0309, i64 1
+  %incdec.ptr = getelementptr inbounds %type1, %type1* %ShndxTable.0309, i64 1
   br i1 undef, label %cond.false.i70, label %cond.end.i
 
 if.then140:                                       ; preds = %for.body137
-  %ret.0.copyload.i.i102 = load i32* %ret.0..sroa_cast.i.i106, align 2
+  %ret.0.copyload.i.i102 = load i32, i32* %ret.0..sroa_cast.i.i106, align 2
 
 ; CHECK: load {{.*}} align 2
 
diff --git a/test/Transforms/ArgumentPromotion/2008-02-01-ReturnAttrs.ll b/test/Transforms/ArgumentPromotion/2008-02-01-ReturnAttrs.ll
index 1226b98a998e..c988774da8a7 100644
--- a/test/Transforms/ArgumentPromotion/2008-02-01-ReturnAttrs.ll
+++ b/test/Transforms/ArgumentPromotion/2008-02-01-ReturnAttrs.ll
@@ -3,7 +3,7 @@
 ; CHECK: define internal i32 @deref(i32 %x.val) #0 {
 define internal i32 @deref(i32* %x) nounwind {
 entry:
-  %tmp2 = load i32* %x, align 4
+  %tmp2 = load i32, i32* %x, align 4
   ret i32 %tmp2
 }
 
diff --git a/test/Transforms/ArgumentPromotion/2008-07-02-array-indexing.ll b/test/Transforms/ArgumentPromotion/2008-07-02-array-indexing.ll
index 210eb97bc1dc..267a6c045974 100644
--- a/test/Transforms/ArgumentPromotion/2008-07-02-array-indexing.ll
+++ b/test/Transforms/ArgumentPromotion/2008-07-02-array-indexing.ll
@@ -7,14 +7,14 @@
 define internal i32 @callee(i1 %C, i32* %A) {
 entry:
         ; Unconditonally load the element at %A
-        %A.0 = load i32* %A
+        %A.0 = load i32, i32* %A
         br i1 %C, label %T, label %F
 T:
         ret i32 %A.0
 F:
         ; Load the element at offset two from %A. This should not be promoted!
-        %A.2 = getelementptr i32* %A, i32 2
-        %R = load i32* %A.2
+        %A.2 = getelementptr i32, i32* %A, i32 2
+        %R = load i32, i32* %A.2
         ret i32 %R
 }
 
diff --git a/test/Transforms/ArgumentPromotion/aggregate-promote.ll b/test/Transforms/ArgumentPromotion/aggregate-promote.ll
index 12de51172739..3f521bace7f3 100644
--- a/test/Transforms/ArgumentPromotion/aggregate-promote.ll
+++ b/test/Transforms/ArgumentPromotion/aggregate-promote.ll
@@ -9,10 +9,10 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1
     i32 25 }            ; <%QuadTy*> [#uses=1]
 
 define internal i32 @test(%QuadTy* %P) {
-        %A = getelementptr %QuadTy* %P, i64 0, i32 3            ; <i32*> [#uses=1]
-        %B = getelementptr %QuadTy* %P, i64 0, i32 2            ; <i32*> [#uses=1]
-        %a = load i32* %A               ; <i32> [#uses=1]
-        %b = load i32* %B               ; <i32> [#uses=1]
+        %A = getelementptr %QuadTy, %QuadTy* %P, i64 0, i32 3            ; <i32*> [#uses=1]
+        %B = getelementptr %QuadTy, %QuadTy* %P, i64 0, i32 2            ; <i32*> [#uses=1]
+        %a = load i32, i32* %A               ; <i32> [#uses=1]
+        %b = load i32, i32* %B               ; <i32> [#uses=1]
         %V = add i32 %a, %b             ; <i32> [#uses=1]
         ret i32 %V
 }
diff --git a/test/Transforms/ArgumentPromotion/attrs.ll b/test/Transforms/ArgumentPromotion/attrs.ll
index 49c075029951..46128f93c240 100644
--- a/test/Transforms/ArgumentPromotion/attrs.ll
+++ b/test/Transforms/ArgumentPromotion/attrs.ll
@@ -4,8 +4,8 @@
 
 define internal void @f(%struct.ss* byval  %b, i32* byval %X, i32 %i) nounwind  {
 entry:
-	%tmp = getelementptr %struct.ss* %b, i32 0, i32 0
-	%tmp1 = load i32* %tmp, align 4
+	%tmp = getelementptr %struct.ss, %struct.ss* %b, i32 0, i32 0
+	%tmp1 = load i32, i32* %tmp, align 4
 	%tmp2 = add i32 %tmp1, 1	
 	store i32 %tmp2, i32* %tmp, align 4
 
@@ -16,9 +16,9 @@ entry:
 define i32 @test(i32* %X) {
 entry:
 	%S = alloca %struct.ss		; <%struct.ss*> [#uses=4]
-	%tmp1 = getelementptr %struct.ss* %S, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp1 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 1, i32* %tmp1, align 8
-	%tmp4 = getelementptr %struct.ss* %S, i32 0, i32 1		; <i64*> [#uses=1]
+	%tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1		; <i64*> [#uses=1]
 	store i64 2, i64* %tmp4, align 4
 	call void @f( %struct.ss* byval %S, i32* byval %X, i32 zeroext 0) 
 	ret i32 0
diff --git a/test/Transforms/ArgumentPromotion/basictest.ll b/test/Transforms/ArgumentPromotion/basictest.ll
index 8f78b98437bc..89888bbc98a7 100644
--- a/test/Transforms/ArgumentPromotion/basictest.ll
+++ b/test/Transforms/ArgumentPromotion/basictest.ll
@@ -3,8 +3,8 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1
 
 define internal i32 @test(i32* %X, i32* %Y) {
 ; CHECK-LABEL: define internal i32 @test(i32 %X.val, i32 %Y.val)
-  %A = load i32* %X
-  %B = load i32* %Y
+  %A = load i32, i32* %X
+  %B = load i32, i32* %Y
   %C = add i32 %A, %B
   ret i32 %C
 }
diff --git a/test/Transforms/ArgumentPromotion/byval-2.ll b/test/Transforms/ArgumentPromotion/byval-2.ll
index b412f5ef0856..6c0288f5f989 100644
--- a/test/Transforms/ArgumentPromotion/byval-2.ll
+++ b/test/Transforms/ArgumentPromotion/byval-2.ll
@@ -8,8 +8,8 @@
 define internal void @f(%struct.ss* byval  %b, i32* byval %X) nounwind  {
 ; CHECK-LABEL: define internal void @f(i32 %b.0, i64 %b.1, i32* byval %X)
 entry:
-  %tmp = getelementptr %struct.ss* %b, i32 0, i32 0
-  %tmp1 = load i32* %tmp, align 4
+  %tmp = getelementptr %struct.ss, %struct.ss* %b, i32 0, i32 0
+  %tmp1 = load i32, i32* %tmp, align 4
   %tmp2 = add i32 %tmp1, 1
   store i32 %tmp2, i32* %tmp, align 4
 
@@ -21,9 +21,9 @@ define i32 @test(i32* %X) {
 ; CHECK-LABEL: define i32 @test
 entry:
   %S = alloca %struct.ss
-  %tmp1 = getelementptr %struct.ss* %S, i32 0, i32 0
+  %tmp1 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 0
   store i32 1, i32* %tmp1, align 8
-  %tmp4 = getelementptr %struct.ss* %S, i32 0, i32 1
+  %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1
   store i64 2, i64* %tmp4, align 4
   call void @f( %struct.ss* byval %S, i32* byval %X)
 ; CHECK: call void @f(i32 %{{.*}}, i64 %{{.*}}, i32* byval %{{.*}})
diff --git a/test/Transforms/ArgumentPromotion/byval.ll b/test/Transforms/ArgumentPromotion/byval.ll
index 27305e92068d..b091b09a3597 100644
--- a/test/Transforms/ArgumentPromotion/byval.ll
+++ b/test/Transforms/ArgumentPromotion/byval.ll
@@ -7,8 +7,8 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1
 define internal void @f(%struct.ss* byval  %b) nounwind  {
 ; CHECK-LABEL: define internal void @f(i32 %b.0, i64 %b.1)
 entry:
-  %tmp = getelementptr %struct.ss* %b, i32 0, i32 0		; <i32*> [#uses=2]
-  %tmp1 = load i32* %tmp, align 4		; <i32> [#uses=1]
+  %tmp = getelementptr %struct.ss, %struct.ss* %b, i32 0, i32 0		; <i32*> [#uses=2]
+  %tmp1 = load i32, i32* %tmp, align 4		; <i32> [#uses=1]
   %tmp2 = add i32 %tmp1, 1		; <i32> [#uses=1]
   store i32 %tmp2, i32* %tmp, align 4
   ret void
@@ -18,9 +18,9 @@ define i32 @main() nounwind  {
 ; CHECK-LABEL: define i32 @main
 entry:
   %S = alloca %struct.ss		; <%struct.ss*> [#uses=4]
-  %tmp1 = getelementptr %struct.ss* %S, i32 0, i32 0		; <i32*> [#uses=1]
+  %tmp1 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 0		; <i32*> [#uses=1]
   store i32 1, i32* %tmp1, align 8
-  %tmp4 = getelementptr %struct.ss* %S, i32 0, i32 1		; <i64*> [#uses=1]
+  %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1		; <i64*> [#uses=1]
   store i64 2, i64* %tmp4, align 4
   call void @f( %struct.ss* byval  %S ) nounwind 
 ; CHECK: call void @f(i32 %{{.*}}, i64 %{{.*}})
diff --git a/test/Transforms/ArgumentPromotion/chained.ll b/test/Transforms/ArgumentPromotion/chained.ll
index c9a453899d7a..6ba2e8d48694 100644
--- a/test/Transforms/ArgumentPromotion/chained.ll
+++ b/test/Transforms/ArgumentPromotion/chained.ll
@@ -5,8 +5,8 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1
 @G2 = constant i32* @G1         ; <i32**> [#uses=1]
 
 define internal i32 @test(i32** %X) {
-        %Y = load i32** %X              ; <i32*> [#uses=1]
-        %X.upgrd.1 = load i32* %Y               ; <i32> [#uses=1]
+        %Y = load i32*, i32** %X              ; <i32*> [#uses=1]
+        %X.upgrd.1 = load i32, i32* %Y               ; <i32> [#uses=1]
         ret i32 %X.upgrd.1
 }
 
diff --git a/test/Transforms/ArgumentPromotion/control-flow.ll b/test/Transforms/ArgumentPromotion/control-flow.ll
index e4a61da45cf3..cdff36eb83c0 100644
--- a/test/Transforms/ArgumentPromotion/control-flow.ll
+++ b/test/Transforms/ArgumentPromotion/control-flow.ll
@@ -8,7 +8,7 @@ T:              ; preds = %0
         ret i32 17
 
 F:              ; preds = %0
-        %X = load i32* %P               ; <i32> [#uses=1]
+        %X = load i32, i32* %P               ; <i32> [#uses=1]
         ret i32 %X
 }
 
diff --git a/test/Transforms/ArgumentPromotion/control-flow2.ll b/test/Transforms/ArgumentPromotion/control-flow2.ll
index 2543218bafe8..7413f46a860f 100644
--- a/test/Transforms/ArgumentPromotion/control-flow2.ll
+++ b/test/Transforms/ArgumentPromotion/control-flow2.ll
@@ -1,5 +1,6 @@
-; RUN: opt < %s -argpromotion -S | \
-; RUN:   grep "load i32\* %A"
+; RUN: opt < %s -argpromotion -S | FileCheck %s
+
+; CHECK: load i32, i32* %A
 target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
 
 define internal i32 @callee(i1 %C, i32* %P) {
@@ -9,7 +10,7 @@ T:              ; preds = %0
         ret i32 17
 
 F:              ; preds = %0
-        %X = load i32* %P               ; <i32> [#uses=1]
+        %X = load i32, i32* %P               ; <i32> [#uses=1]
         ret i32 %X
 }
 
diff --git a/test/Transforms/ArgumentPromotion/crash.ll b/test/Transforms/ArgumentPromotion/crash.ll
index 5e1a0370dbb1..dbd343ae920e 100644
--- a/test/Transforms/ArgumentPromotion/crash.ll
+++ b/test/Transforms/ArgumentPromotion/crash.ll
@@ -50,10 +50,10 @@ init:
 
 define internal i32 @"clay_assign(Chain, Chain)"(%0* %c, %0* %d) {
 init:
-  %0 = getelementptr %0* %d, i32 0, i32 0
-  %1 = load %0** %0
-  %2 = getelementptr %0* %c, i32 0, i32 0
-  %3 = load %0** %2
+  %0 = getelementptr %0, %0* %d, i32 0, i32 0
+  %1 = load %0*, %0** %0
+  %2 = getelementptr %0, %0* %c, i32 0, i32 0
+  %3 = load %0*, %0** %2
   %4 = call i32 @"clay_assign(Chain, Chain)"(%0* %3, %0* %1)
   ret i32 0
 }
diff --git a/test/Transforms/ArgumentPromotion/dbg.ll b/test/Transforms/ArgumentPromotion/dbg.ll
index 65cf3678bd99..17a34cb62239 100644
--- a/test/Transforms/ArgumentPromotion/dbg.ll
+++ b/test/Transforms/ArgumentPromotion/dbg.ll
@@ -1,12 +1,12 @@
 ; RUN: opt < %s -argpromotion -S | FileCheck %s
 ; CHECK: call void @test(i32 %
-; CHECK: void (i32)* @test, {{.*}} ; [ DW_TAG_subprogram ] {{.*}} [test]
+; CHECK: !DISubprogram(name: "test",{{.*}} function: void (i32)* @test
 
 declare void @sink(i32)
 
 define internal void @test(i32** %X) {
-  %1 = load i32** %X, align 8
-  %2 = load i32* %1, align 8
+  %1 = load i32*, i32** %X, align 8
+  %2 = load i32, i32* %1, align 8
   call void @sink(i32 %2)
   ret void
 }
@@ -19,8 +19,9 @@ define void @caller(i32** %Y) {
 !llvm.module.flags = !{!0}
 !llvm.dbg.cu = !{!3}
 
-!0 = !{i32 2, !"Debug Info Version", i32 2}
-!1 = !MDLocation(line: 8, scope: !2)
-!2 = !{!"0x2e\00test\00test\00\003\001\001\000\006\00256\000\003", null, null, null, null, void (i32**)* @test, null, null, null} ; [ DW_TAG_subprogram ]
-!3 = !{!"0x11\004\00clang version 3.5.0 \000\00\000\00\002", null, null, null, !4, null, null} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/blaikie/dev/scratch/pr20038/reduce/<stdin>] [DW_LANG_C_plus_plus]
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !DILocation(line: 8, scope: !2)
+!2 = !DISubprogram(name: "test", line: 3, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, scope: null, function: void (i32**)* @test)
+!3 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 2, file: !5, subprograms: !4)
 !4 = !{!2}
+!5 = !DIFile(filename: "test.c", directory: "")
diff --git a/test/Transforms/ArgumentPromotion/fp80.ll b/test/Transforms/ArgumentPromotion/fp80.ll
index a770d6013d6b..84ef603de82c 100644
--- a/test/Transforms/ArgumentPromotion/fp80.ll
+++ b/test/Transforms/ArgumentPromotion/fp80.ll
@@ -24,22 +24,22 @@ entry:
 define internal i8 @UseLongDoubleUnsafely(%union.u* byval align 16 %arg) {
 entry:
   %bitcast = bitcast %union.u* %arg to %struct.s*
-  %gep = getelementptr inbounds %struct.s* %bitcast, i64 0, i32 2
-  %result = load i8* %gep
+  %gep = getelementptr inbounds %struct.s, %struct.s* %bitcast, i64 0, i32 2
+  %result = load i8, i8* %gep
   ret i8 %result
 }
 
 ; CHECK: internal x86_fp80 @UseLongDoubleSafely(x86_fp80 {{%.*}}) {
 define internal x86_fp80 @UseLongDoubleSafely(%union.u* byval align 16 %arg) {
-  %gep = getelementptr inbounds %union.u* %arg, i64 0, i32 0
-  %fp80 = load x86_fp80* %gep
+  %gep = getelementptr inbounds %union.u, %union.u* %arg, i64 0, i32 0
+  %fp80 = load x86_fp80, x86_fp80* %gep
   ret x86_fp80 %fp80
 }
 
 ; CHECK: define internal i64 @AccessPaddingOfStruct(%struct.Foo* byval %a) {
 define internal i64 @AccessPaddingOfStruct(%struct.Foo* byval %a) {
   %p = bitcast %struct.Foo* %a to i64*
-  %v = load i64* %p
+  %v = load i64, i64* %p
   ret i64 %v
 }
 
@@ -53,6 +53,6 @@ loop:
   %phi = phi %struct.Foo* [ null, %entry ], [ %gep, %loop ]
   %0   = phi %struct.Foo* [ %a, %entry ],   [ %0, %loop ]
   store %struct.Foo* %phi, %struct.Foo** %a_ptr
-  %gep = getelementptr %struct.Foo* %a, i64 0
+  %gep = getelementptr %struct.Foo, %struct.Foo* %a, i64 0
   br label %loop
 }
diff --git a/test/Transforms/ArgumentPromotion/inalloca.ll b/test/Transforms/ArgumentPromotion/inalloca.ll
index 089a78f6b319..80bd6fdbc406 100644
--- a/test/Transforms/ArgumentPromotion/inalloca.ll
+++ b/test/Transforms/ArgumentPromotion/inalloca.ll
@@ -7,10 +7,10 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1
 ; Argpromote + scalarrepl should change this to passing the two integers by value.
 define internal i32 @f(%struct.ss* inalloca  %s) {
 entry:
-  %f0 = getelementptr %struct.ss* %s, i32 0, i32 0
-  %f1 = getelementptr %struct.ss* %s, i32 0, i32 1
-  %a = load i32* %f0, align 4
-  %b = load i32* %f1, align 4
+  %f0 = getelementptr %struct.ss, %struct.ss* %s, i32 0, i32 0
+  %f1 = getelementptr %struct.ss, %struct.ss* %s, i32 0, i32 1
+  %a = load i32, i32* %f0, align 4
+  %b = load i32, i32* %f1, align 4
   %r = add i32 %a, %b
   ret i32 %r
 }
@@ -21,8 +21,8 @@ entry:
 define i32 @main() {
 entry:
   %S = alloca inalloca %struct.ss
-  %f0 = getelementptr %struct.ss* %S, i32 0, i32 0
-  %f1 = getelementptr %struct.ss* %S, i32 0, i32 1
+  %f0 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 0
+  %f1 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1
   store i32 1, i32* %f0, align 4
   store i32 2, i32* %f1, align 4
   %r = call i32 @f(%struct.ss* inalloca %S)
diff --git a/test/Transforms/ArgumentPromotion/reserve-tbaa.ll b/test/Transforms/ArgumentPromotion/reserve-tbaa.ll
index db9d70d337a1..3c8ed79eeb29 100644
--- a/test/Transforms/ArgumentPromotion/reserve-tbaa.ll
+++ b/test/Transforms/ArgumentPromotion/reserve-tbaa.ll
@@ -14,9 +14,9 @@
 
 define internal fastcc void @fn(i32* nocapture readonly %p1, i64* nocapture readonly %p2) {
 entry:
-  %0 = load i64* %p2, align 8, !tbaa !1
+  %0 = load i64, i64* %p2, align 8, !tbaa !1
   %conv = trunc i64 %0 to i32
-  %1 = load i32* %p1, align 4, !tbaa !5
+  %1 = load i32, i32* %p1, align 4, !tbaa !5
   %conv1 = trunc i32 %1 to i8
   store i8 %conv1, i8* @d, align 1, !tbaa !7
   ret void
@@ -26,11 +26,11 @@ define i32 @main() {
 entry:
 ; CHECK-LABEL: main
 ; CHECK: store i32 1, i32* %{{.*}}, align 4, !tbaa ![[I32:[0-9]+]]
-; CHECK: %g.val = load i32* @g, align 4, !tbaa ![[I32]]
-; CHECK: %c.val = load i64* @c, align 8, !tbaa ![[LONG:[0-9]+]]
-  %0 = load i32*** @e, align 8, !tbaa !8
+; CHECK: %g.val = load i32, i32* @g, align 4, !tbaa ![[I32]]
+; CHECK: %c.val = load i64, i64* @c, align 8, !tbaa ![[LONG:[0-9]+]]
+  %0 = load i32**, i32*** @e, align 8, !tbaa !8
   store i32* @g, i32** %0, align 8, !tbaa !8
-  %1 = load i32** @a, align 8, !tbaa !8
+  %1 = load i32*, i32** @a, align 8, !tbaa !8
   store i32 1, i32* %1, align 4, !tbaa !5
   call fastcc void @fn(i32* @g, i64* @c)
 
diff --git a/test/Transforms/ArgumentPromotion/variadic.ll b/test/Transforms/ArgumentPromotion/variadic.ll
index 0ae52b3bbbd1..0e03882d3b20 100644
--- a/test/Transforms/ArgumentPromotion/variadic.ll
+++ b/test/Transforms/ArgumentPromotion/variadic.ll
@@ -15,7 +15,7 @@ target triple = "x86_64-unknown-linux-gnu"
 ; Function Attrs: nounwind uwtable
 define i32 @main(i32 %argc, i8** nocapture readnone %argv) #0 {
 entry:
-  tail call void (i8*, i8*, i8*, i8*, i8*, ...)* @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* byval align 8 @t45)
+  tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* byval align 8 @t45)
   ret i32 0
 }
 
diff --git a/test/Transforms/BBVectorize/X86/loop1.ll b/test/Transforms/BBVectorize/X86/loop1.ll
index 401808441c26..c3c30454ce33 100644
--- a/test/Transforms/BBVectorize/X86/loop1.ll
+++ b/test/Transforms/BBVectorize/X86/loop1.ll
@@ -12,10 +12,10 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds double* %in1, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
-  %arrayidx2 = getelementptr inbounds double* %in2, i64 %indvars.iv
-  %1 = load double* %arrayidx2, align 8
+  %arrayidx = getelementptr inbounds double, double* %in1, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %in2, i64 %indvars.iv
+  %1 = load double, double* %arrayidx2, align 8
   %mul = fmul double %0, %0
   %mul3 = fmul double %0, %1
   %add = fadd double %mul, %mul3
@@ -28,7 +28,7 @@ for.body:                                         ; preds = %for.body, %entry
   %add10 = fadd double %add9, %0
   %mul11 = fmul double %mul8, %add10
   %add12 = fadd double %add7, %mul11
-  %arrayidx14 = getelementptr inbounds double* %out, i64 %indvars.iv
+  %arrayidx14 = getelementptr inbounds double, double* %out, i64 %indvars.iv
   store double %add12, double* %arrayidx14, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/BBVectorize/X86/pr15289.ll b/test/Transforms/BBVectorize/X86/pr15289.ll
index 42bd0ff14032..a383a260fafd 100644
--- a/test/Transforms/BBVectorize/X86/pr15289.ll
+++ b/test/Transforms/BBVectorize/X86/pr15289.ll
@@ -44,43 +44,43 @@ entry:
   %12 = fsub double undef, %7
   %13 = fmul double %3, %12
   %14 = fmul double %3, undef
-  %15 = getelementptr inbounds [5 x { double, double }]* %c2ten, i64 0, i64 0, i32 0
+  %15 = getelementptr inbounds [5 x { double, double }], [5 x { double, double }]* %c2ten, i64 0, i64 0, i32 0
   store double %13, double* %15, align 8
-  %16 = getelementptr inbounds [5 x { double, double }]* %c2ten, i64 0, i64 0, i32 1
+  %16 = getelementptr inbounds [5 x { double, double }], [5 x { double, double }]* %c2ten, i64 0, i64 0, i32 1
   %17 = fmul double undef, %8
   %18 = fmul double %17, undef
   %19 = fmul double undef, %18
   %20 = fadd double undef, undef
   %21 = fmul double %3, %19
   %22 = fsub double -0.000000e+00, %21
-  %23 = getelementptr inbounds [5 x { double, double }]* %c2ten, i64 0, i64 1, i32 0
+  %23 = getelementptr inbounds [5 x { double, double }], [5 x { double, double }]* %c2ten, i64 0, i64 1, i32 0
   store double %22, double* %23, align 8
-  %24 = getelementptr inbounds [5 x { double, double }]* %c2ten, i64 0, i64 1, i32 1
+  %24 = getelementptr inbounds [5 x { double, double }], [5 x { double, double }]* %c2ten, i64 0, i64 1, i32 1
   %25 = fmul double undef, 0x3FE42F601A8C6794
   %26 = fmul double undef, 2.000000e+00
   %27 = fsub double %26, %0
   %28 = fmul double %6, undef
   %29 = fsub double undef, %28
-  %30 = getelementptr inbounds [5 x { double, double }]* %c2ten, i64 0, i64 2, i32 0
+  %30 = getelementptr inbounds [5 x { double, double }], [5 x { double, double }]* %c2ten, i64 0, i64 2, i32 0
   store double undef, double* %30, align 8
-  %31 = getelementptr inbounds [5 x { double, double }]* %c2ten, i64 0, i64 2, i32 1
+  %31 = getelementptr inbounds [5 x { double, double }], [5 x { double, double }]* %c2ten, i64 0, i64 2, i32 1
   %32 = fmul double undef, %17
   %33 = fmul double undef, %17
   %34 = fmul double undef, %32
   %35 = fmul double undef, %33
   %36 = fsub double undef, %35
   %37 = fmul double %3, %34
-  %38 = getelementptr inbounds [5 x { double, double }]* %c2ten, i64 0, i64 3, i32 0
+  %38 = getelementptr inbounds [5 x { double, double }], [5 x { double, double }]* %c2ten, i64 0, i64 3, i32 0
   store double %37, double* %38, align 8
-  %39 = getelementptr inbounds [5 x { double, double }]* %c2ten, i64 0, i64 3, i32 1
+  %39 = getelementptr inbounds [5 x { double, double }], [5 x { double, double }]* %c2ten, i64 0, i64 3, i32 1
   %40 = fmul double undef, %8
   %41 = fmul double undef, %40
   %42 = fmul double undef, %41
   %43 = fsub double undef, %42
   %44 = fmul double %3, %43
-  %45 = getelementptr inbounds [5 x { double, double }]* %c2ten, i64 0, i64 4, i32 0
+  %45 = getelementptr inbounds [5 x { double, double }], [5 x { double, double }]* %c2ten, i64 0, i64 4, i32 0
   store double %13, double* %45, align 8
-  %46 = getelementptr inbounds [5 x { double, double }]* %c2ten, i64 0, i64 4, i32 1
+  %46 = getelementptr inbounds [5 x { double, double }], [5 x { double, double }]* %c2ten, i64 0, i64 4, i32 1
   %47 = fsub double -0.000000e+00, %14
   store double %47, double* %16, align 8
   store double undef, double* %24, align 8
diff --git a/test/Transforms/BBVectorize/X86/sh-rec.ll b/test/Transforms/BBVectorize/X86/sh-rec.ll
index ad75fc96d9f2..2cb9dbded224 100644
--- a/test/Transforms/BBVectorize/X86/sh-rec.ll
+++ b/test/Transforms/BBVectorize/X86/sh-rec.ll
@@ -8,39 +8,39 @@ entry:
   br i1 undef, label %return, label %if.end10
 
 if.end10:                                         ; preds = %entry
-  %incdec.ptr = getelementptr inbounds i8* %call, i64 undef
+  %incdec.ptr = getelementptr inbounds i8, i8* %call, i64 undef
   %call17 = call i32 @ptou() nounwind
-  %incdec.ptr26.1 = getelementptr inbounds i8* %incdec.ptr, i64 -2
+  %incdec.ptr26.1 = getelementptr inbounds i8, i8* %incdec.ptr, i64 -2
   store i8 undef, i8* %incdec.ptr26.1, align 1
   %div27.1 = udiv i32 %call17, 100
   %rem.2 = urem i32 %div27.1, 10
   %add2230.2 = or i32 %rem.2, 48
   %conv25.2 = trunc i32 %add2230.2 to i8
-  %incdec.ptr26.2 = getelementptr inbounds i8* %incdec.ptr, i64 -3
+  %incdec.ptr26.2 = getelementptr inbounds i8, i8* %incdec.ptr, i64 -3
   store i8 %conv25.2, i8* %incdec.ptr26.2, align 1
-  %incdec.ptr26.3 = getelementptr inbounds i8* %incdec.ptr, i64 -4
+  %incdec.ptr26.3 = getelementptr inbounds i8, i8* %incdec.ptr, i64 -4
   store i8 undef, i8* %incdec.ptr26.3, align 1
   %div27.3 = udiv i32 %call17, 10000
   %rem.4 = urem i32 %div27.3, 10
   %add2230.4 = or i32 %rem.4, 48
   %conv25.4 = trunc i32 %add2230.4 to i8
-  %incdec.ptr26.4 = getelementptr inbounds i8* %incdec.ptr, i64 -5
+  %incdec.ptr26.4 = getelementptr inbounds i8, i8* %incdec.ptr, i64 -5
   store i8 %conv25.4, i8* %incdec.ptr26.4, align 1
   %div27.4 = udiv i32 %call17, 100000
   %rem.5 = urem i32 %div27.4, 10
   %add2230.5 = or i32 %rem.5, 48
   %conv25.5 = trunc i32 %add2230.5 to i8
-  %incdec.ptr26.5 = getelementptr inbounds i8* %incdec.ptr, i64 -6
+  %incdec.ptr26.5 = getelementptr inbounds i8, i8* %incdec.ptr, i64 -6
   store i8 %conv25.5, i8* %incdec.ptr26.5, align 1
-  %incdec.ptr26.6 = getelementptr inbounds i8* %incdec.ptr, i64 -7
+  %incdec.ptr26.6 = getelementptr inbounds i8, i8* %incdec.ptr, i64 -7
   store i8 0, i8* %incdec.ptr26.6, align 1
-  %incdec.ptr26.7 = getelementptr inbounds i8* %incdec.ptr, i64 -8
+  %incdec.ptr26.7 = getelementptr inbounds i8, i8* %incdec.ptr, i64 -8
   store i8 undef, i8* %incdec.ptr26.7, align 1
   %div27.7 = udiv i32 %call17, 100000000
   %rem.8 = urem i32 %div27.7, 10
   %add2230.8 = or i32 %rem.8, 48
   %conv25.8 = trunc i32 %add2230.8 to i8
-  %incdec.ptr26.8 = getelementptr inbounds i8* %incdec.ptr, i64 -9
+  %incdec.ptr26.8 = getelementptr inbounds i8, i8* %incdec.ptr, i64 -9
   store i8 %conv25.8, i8* %incdec.ptr26.8, align 1
   unreachable
 
diff --git a/test/Transforms/BBVectorize/X86/sh-rec2.ll b/test/Transforms/BBVectorize/X86/sh-rec2.ll
index d65ac1cc12f1..d7a004c21384 100644
--- a/test/Transforms/BBVectorize/X86/sh-rec2.ll
+++ b/test/Transforms/BBVectorize/X86/sh-rec2.ll
@@ -7,72 +7,72 @@ target triple = "x86_64-unknown-linux-gnu"
 define void @gsm_encode(%struct.gsm_state.2.8.14.15.16.17.19.22.23.25.26.28.29.31.32.33.35.36.37.38.40.41.42.44.45.47.48.50.52.53.54.56.57.58.59.60.61.62.63.66.73.83.84.89.90.91.92.93.94.95.96.99.100.101.102.103.104.106.107.114.116.121.122.129.130.135.136.137.138.139.140.141.142.143.144.147.148.149.158.159.160.161.164.165.166.167.168.169.172.179.181.182.183.188.195.200.201.202.203.204.205.208.209.210.212.213.214.215.222.223.225.226.230.231.232.233.234.235.236.237.238.239.240.241.242.243.244.352* %s, i16* %source, i8* %c) nounwind uwtable {
 entry:
   %xmc = alloca [52 x i16], align 16
-  %arraydecay5 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 0
+  %arraydecay5 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 0
   call void @Gsm_Coder(%struct.gsm_state.2.8.14.15.16.17.19.22.23.25.26.28.29.31.32.33.35.36.37.38.40.41.42.44.45.47.48.50.52.53.54.56.57.58.59.60.61.62.63.66.73.83.84.89.90.91.92.93.94.95.96.99.100.101.102.103.104.106.107.114.116.121.122.129.130.135.136.137.138.139.140.141.142.143.144.147.148.149.158.159.160.161.164.165.166.167.168.169.172.179.181.182.183.188.195.200.201.202.203.204.205.208.209.210.212.213.214.215.222.223.225.226.230.231.232.233.234.235.236.237.238.239.240.241.242.243.244.352* %s, i16* %source, i16* undef, i16* null, i16* undef, i16* undef, i16* undef, i16* %arraydecay5) nounwind
-  %incdec.ptr136 = getelementptr inbounds i8* %c, i64 10
-  %incdec.ptr157 = getelementptr inbounds i8* %c, i64 11
+  %incdec.ptr136 = getelementptr inbounds i8, i8* %c, i64 10
+  %incdec.ptr157 = getelementptr inbounds i8, i8* %c, i64 11
   store i8 0, i8* %incdec.ptr136, align 1
-  %arrayidx162 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 11
-  %0 = load i16* %arrayidx162, align 2
+  %arrayidx162 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 11
+  %0 = load i16, i16* %arrayidx162, align 2
   %conv1631 = trunc i16 %0 to i8
   %and164 = shl i8 %conv1631, 3
   %shl165 = and i8 %and164, 56
-  %incdec.ptr172 = getelementptr inbounds i8* %c, i64 12
+  %incdec.ptr172 = getelementptr inbounds i8, i8* %c, i64 12
   store i8 %shl165, i8* %incdec.ptr157, align 1
-  %1 = load i16* inttoptr (i64 2 to i16*), align 2
+  %1 = load i16, i16* inttoptr (i64 2 to i16*), align 2
   %conv1742 = trunc i16 %1 to i8
   %and175 = shl i8 %conv1742, 1
-  %incdec.ptr183 = getelementptr inbounds i8* %c, i64 13
+  %incdec.ptr183 = getelementptr inbounds i8, i8* %c, i64 13
   store i8 %and175, i8* %incdec.ptr172, align 1
-  %incdec.ptr199 = getelementptr inbounds i8* %c, i64 14
+  %incdec.ptr199 = getelementptr inbounds i8, i8* %c, i64 14
   store i8 0, i8* %incdec.ptr183, align 1
-  %arrayidx214 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 15
-  %incdec.ptr220 = getelementptr inbounds i8* %c, i64 15
+  %arrayidx214 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 15
+  %incdec.ptr220 = getelementptr inbounds i8, i8* %c, i64 15
   store i8 0, i8* %incdec.ptr199, align 1
-  %2 = load i16* %arrayidx214, align 2
+  %2 = load i16, i16* %arrayidx214, align 2
   %conv2223 = trunc i16 %2 to i8
   %and223 = shl i8 %conv2223, 6
-  %incdec.ptr235 = getelementptr inbounds i8* %c, i64 16
+  %incdec.ptr235 = getelementptr inbounds i8, i8* %c, i64 16
   store i8 %and223, i8* %incdec.ptr220, align 1
-  %arrayidx240 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 19
-  %3 = load i16* %arrayidx240, align 2
+  %arrayidx240 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 19
+  %3 = load i16, i16* %arrayidx240, align 2
   %conv2414 = trunc i16 %3 to i8
   %and242 = shl i8 %conv2414, 2
   %shl243 = and i8 %and242, 28
-  %incdec.ptr251 = getelementptr inbounds i8* %c, i64 17
+  %incdec.ptr251 = getelementptr inbounds i8, i8* %c, i64 17
   store i8 %shl243, i8* %incdec.ptr235, align 1
-  %incdec.ptr272 = getelementptr inbounds i8* %c, i64 18
+  %incdec.ptr272 = getelementptr inbounds i8, i8* %c, i64 18
   store i8 0, i8* %incdec.ptr251, align 1
-  %arrayidx282 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 25
-  %4 = load i16* %arrayidx282, align 2
+  %arrayidx282 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 25
+  %4 = load i16, i16* %arrayidx282, align 2
   %conv2835 = trunc i16 %4 to i8
   %and284 = and i8 %conv2835, 7
-  %incdec.ptr287 = getelementptr inbounds i8* %c, i64 19
+  %incdec.ptr287 = getelementptr inbounds i8, i8* %c, i64 19
   store i8 %and284, i8* %incdec.ptr272, align 1
-  %incdec.ptr298 = getelementptr inbounds i8* %c, i64 20
+  %incdec.ptr298 = getelementptr inbounds i8, i8* %c, i64 20
   store i8 0, i8* %incdec.ptr287, align 1
-  %incdec.ptr314 = getelementptr inbounds i8* %c, i64 21
+  %incdec.ptr314 = getelementptr inbounds i8, i8* %c, i64 21
   store i8 0, i8* %incdec.ptr298, align 1
-  %arrayidx319 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 26
-  %5 = load i16* %arrayidx319, align 4
+  %arrayidx319 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 26
+  %5 = load i16, i16* %arrayidx319, align 4
   %conv3206 = trunc i16 %5 to i8
   %and321 = shl i8 %conv3206, 4
   %shl322 = and i8 %and321, 112
-  %incdec.ptr335 = getelementptr inbounds i8* %c, i64 22
+  %incdec.ptr335 = getelementptr inbounds i8, i8* %c, i64 22
   store i8 %shl322, i8* %incdec.ptr314, align 1
-  %arrayidx340 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 29
-  %6 = load i16* %arrayidx340, align 2
+  %arrayidx340 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 29
+  %6 = load i16, i16* %arrayidx340, align 2
   %conv3417 = trunc i16 %6 to i8
   %and342 = shl i8 %conv3417, 3
   %shl343 = and i8 %and342, 56
-  %incdec.ptr350 = getelementptr inbounds i8* %c, i64 23
+  %incdec.ptr350 = getelementptr inbounds i8, i8* %c, i64 23
   store i8 %shl343, i8* %incdec.ptr335, align 1
-  %incdec.ptr366 = getelementptr inbounds i8* %c, i64 24
+  %incdec.ptr366 = getelementptr inbounds i8, i8* %c, i64 24
   store i8 0, i8* %incdec.ptr350, align 1
-  %arrayidx381 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 36
-  %incdec.ptr387 = getelementptr inbounds i8* %c, i64 25
+  %arrayidx381 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 36
+  %incdec.ptr387 = getelementptr inbounds i8, i8* %c, i64 25
   store i8 0, i8* %incdec.ptr366, align 1
-  %7 = load i16* %arrayidx381, align 8
+  %7 = load i16, i16* %arrayidx381, align 8
   %conv3898 = trunc i16 %7 to i8
   %and390 = shl i8 %conv3898, 6
   store i8 %and390, i8* %incdec.ptr387, align 1
diff --git a/test/Transforms/BBVectorize/X86/sh-rec3.ll b/test/Transforms/BBVectorize/X86/sh-rec3.ll
index ad880ed8895a..2096deb08a90 100644
--- a/test/Transforms/BBVectorize/X86/sh-rec3.ll
+++ b/test/Transforms/BBVectorize/X86/sh-rec3.ll
@@ -7,153 +7,153 @@ target triple = "x86_64-unknown-linux-gnu"
 define void @gsm_encode(%struct.gsm_state.2.8.39.44.45.55.56.57.58.59.62.63.64.65.74.75.76.77.80.87.92.93.94.95.96.97.110.111.112.113.114.128.130.135.136.137.138.139.140.141.142.143.144.145.148.149.150.151.152.169.170.177.178.179.184.185.186.187.188.201.208.209.219.220.221.223.224.225.230.231.232.233.235.236.237.238.245.246.248.249.272.274.279.280.281.282.283.286.293.298.299.314.315.316.317.318.319.320.321.322.323.324.325.326.327.328.329.330.331.332.333.334.335.336.337.338.339.340.341.342.343.344.345.346.347.348.349.350.351.352.353.565* %s, i16* %source, i8* %c) nounwind uwtable {
 entry:
   %LARc28 = alloca [2 x i64], align 16
-  %LARc28.sub = getelementptr inbounds [2 x i64]* %LARc28, i64 0, i64 0
+  %LARc28.sub = getelementptr inbounds [2 x i64], [2 x i64]* %LARc28, i64 0, i64 0
   %tmpcast = bitcast [2 x i64]* %LARc28 to [8 x i16]*
   %Nc = alloca [4 x i16], align 2
   %Mc = alloca [4 x i16], align 2
   %bc = alloca [4 x i16], align 2
   %xmc = alloca [52 x i16], align 16
   %arraydecay = bitcast [2 x i64]* %LARc28 to i16*
-  %arraydecay1 = getelementptr inbounds [4 x i16]* %Nc, i64 0, i64 0
-  %arraydecay2 = getelementptr inbounds [4 x i16]* %bc, i64 0, i64 0
-  %arraydecay3 = getelementptr inbounds [4 x i16]* %Mc, i64 0, i64 0
-  %arraydecay5 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 0
+  %arraydecay1 = getelementptr inbounds [4 x i16], [4 x i16]* %Nc, i64 0, i64 0
+  %arraydecay2 = getelementptr inbounds [4 x i16], [4 x i16]* %bc, i64 0, i64 0
+  %arraydecay3 = getelementptr inbounds [4 x i16], [4 x i16]* %Mc, i64 0, i64 0
+  %arraydecay5 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 0
   call void @Gsm_Coder(%struct.gsm_state.2.8.39.44.45.55.56.57.58.59.62.63.64.65.74.75.76.77.80.87.92.93.94.95.96.97.110.111.112.113.114.128.130.135.136.137.138.139.140.141.142.143.144.145.148.149.150.151.152.169.170.177.178.179.184.185.186.187.188.201.208.209.219.220.221.223.224.225.230.231.232.233.235.236.237.238.245.246.248.249.272.274.279.280.281.282.283.286.293.298.299.314.315.316.317.318.319.320.321.322.323.324.325.326.327.328.329.330.331.332.333.334.335.336.337.338.339.340.341.342.343.344.345.346.347.348.349.350.351.352.353.565* %s, i16* %source, i16* %arraydecay, i16* %arraydecay1, i16* %arraydecay2, i16* %arraydecay3, i16* undef, i16* %arraydecay5) nounwind
-  %0 = load i64* %LARc28.sub, align 16
+  %0 = load i64, i64* %LARc28.sub, align 16
   %1 = trunc i64 %0 to i32
   %conv1 = lshr i32 %1, 2
   %and = and i32 %conv1, 15
   %or = or i32 %and, 208
   %conv6 = trunc i32 %or to i8
-  %incdec.ptr = getelementptr inbounds i8* %c, i64 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %c, i64 1
   store i8 %conv6, i8* %c, align 1
   %conv84 = trunc i64 %0 to i8
   %and9 = shl i8 %conv84, 6
-  %incdec.ptr15 = getelementptr inbounds i8* %c, i64 2
+  %incdec.ptr15 = getelementptr inbounds i8, i8* %c, i64 2
   store i8 %and9, i8* %incdec.ptr, align 1
   %2 = lshr i64 %0, 50
   %shr226.tr = trunc i64 %2 to i8
   %conv25 = and i8 %shr226.tr, 7
-  %incdec.ptr26 = getelementptr inbounds i8* %c, i64 3
+  %incdec.ptr26 = getelementptr inbounds i8, i8* %c, i64 3
   store i8 %conv25, i8* %incdec.ptr15, align 1
-  %incdec.ptr42 = getelementptr inbounds i8* %c, i64 4
+  %incdec.ptr42 = getelementptr inbounds i8, i8* %c, i64 4
   store i8 0, i8* %incdec.ptr26, align 1
-  %arrayidx52 = getelementptr inbounds [8 x i16]* %tmpcast, i64 0, i64 7
-  %3 = load i16* %arrayidx52, align 2
+  %arrayidx52 = getelementptr inbounds [8 x i16], [8 x i16]* %tmpcast, i64 0, i64 7
+  %3 = load i16, i16* %arrayidx52, align 2
   %conv537 = trunc i16 %3 to i8
   %and54 = and i8 %conv537, 7
-  %incdec.ptr57 = getelementptr inbounds i8* %c, i64 5
+  %incdec.ptr57 = getelementptr inbounds i8, i8* %c, i64 5
   store i8 %and54, i8* %incdec.ptr42, align 1
-  %incdec.ptr68 = getelementptr inbounds i8* %c, i64 6
+  %incdec.ptr68 = getelementptr inbounds i8, i8* %c, i64 6
   store i8 0, i8* %incdec.ptr57, align 1
-  %4 = load i16* %arraydecay3, align 2
+  %4 = load i16, i16* %arraydecay3, align 2
   %conv748 = trunc i16 %4 to i8
   %and75 = shl i8 %conv748, 5
   %shl76 = and i8 %and75, 96
-  %incdec.ptr84 = getelementptr inbounds i8* %c, i64 7
+  %incdec.ptr84 = getelementptr inbounds i8, i8* %c, i64 7
   store i8 %shl76, i8* %incdec.ptr68, align 1
-  %arrayidx94 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 1
-  %5 = load i16* %arrayidx94, align 2
+  %arrayidx94 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 1
+  %5 = load i16, i16* %arrayidx94, align 2
   %conv959 = trunc i16 %5 to i8
   %and96 = shl i8 %conv959, 1
   %shl97 = and i8 %and96, 14
   %or103 = or i8 %shl97, 1
-  %incdec.ptr105 = getelementptr inbounds i8* %c, i64 8
+  %incdec.ptr105 = getelementptr inbounds i8, i8* %c, i64 8
   store i8 %or103, i8* %incdec.ptr84, align 1
-  %arrayidx115 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 4
+  %arrayidx115 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 4
   %6 = bitcast i16* %arrayidx115 to i32*
-  %7 = load i32* %6, align 8
+  %7 = load i32, i32* %6, align 8
   %conv11610 = trunc i32 %7 to i8
   %and117 = and i8 %conv11610, 7
-  %incdec.ptr120 = getelementptr inbounds i8* %c, i64 9
+  %incdec.ptr120 = getelementptr inbounds i8, i8* %c, i64 9
   store i8 %and117, i8* %incdec.ptr105, align 1
   %8 = lshr i32 %7, 16
   %and12330 = shl nuw nsw i32 %8, 5
   %and123 = trunc i32 %and12330 to i8
-  %incdec.ptr136 = getelementptr inbounds i8* %c, i64 10
+  %incdec.ptr136 = getelementptr inbounds i8, i8* %c, i64 10
   store i8 %and123, i8* %incdec.ptr120, align 1
-  %incdec.ptr157 = getelementptr inbounds i8* %c, i64 11
+  %incdec.ptr157 = getelementptr inbounds i8, i8* %c, i64 11
   store i8 0, i8* %incdec.ptr136, align 1
-  %incdec.ptr172 = getelementptr inbounds i8* %c, i64 12
+  %incdec.ptr172 = getelementptr inbounds i8, i8* %c, i64 12
   store i8 0, i8* %incdec.ptr157, align 1
-  %arrayidx173 = getelementptr inbounds [4 x i16]* %Nc, i64 0, i64 1
-  %9 = load i16* %arrayidx173, align 2
+  %arrayidx173 = getelementptr inbounds [4 x i16], [4 x i16]* %Nc, i64 0, i64 1
+  %9 = load i16, i16* %arrayidx173, align 2
   %conv17412 = zext i16 %9 to i32
   %and175 = shl nuw nsw i32 %conv17412, 1
-  %arrayidx177 = getelementptr inbounds [4 x i16]* %bc, i64 0, i64 1
-  %10 = load i16* %arrayidx177, align 2
+  %arrayidx177 = getelementptr inbounds [4 x i16], [4 x i16]* %bc, i64 0, i64 1
+  %10 = load i16, i16* %arrayidx177, align 2
   %conv17826 = zext i16 %10 to i32
   %shr17913 = lshr i32 %conv17826, 1
   %and180 = and i32 %shr17913, 1
   %or181 = or i32 %and175, %and180
   %conv182 = trunc i32 %or181 to i8
-  %incdec.ptr183 = getelementptr inbounds i8* %c, i64 13
+  %incdec.ptr183 = getelementptr inbounds i8, i8* %c, i64 13
   store i8 %conv182, i8* %incdec.ptr172, align 1
-  %arrayidx188 = getelementptr inbounds [4 x i16]* %Mc, i64 0, i64 1
-  %11 = load i16* %arrayidx188, align 2
+  %arrayidx188 = getelementptr inbounds [4 x i16], [4 x i16]* %Mc, i64 0, i64 1
+  %11 = load i16, i16* %arrayidx188, align 2
   %conv18914 = trunc i16 %11 to i8
   %and190 = shl i8 %conv18914, 5
   %shl191 = and i8 %and190, 96
-  %incdec.ptr199 = getelementptr inbounds i8* %c, i64 14
+  %incdec.ptr199 = getelementptr inbounds i8, i8* %c, i64 14
   store i8 %shl191, i8* %incdec.ptr183, align 1
-  %arrayidx209 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 14
-  %12 = load i16* %arrayidx209, align 4
+  %arrayidx209 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 14
+  %12 = load i16, i16* %arrayidx209, align 4
   %conv21015 = trunc i16 %12 to i8
   %and211 = shl i8 %conv21015, 1
   %shl212 = and i8 %and211, 14
   %or218 = or i8 %shl212, 1
-  %incdec.ptr220 = getelementptr inbounds i8* %c, i64 15
+  %incdec.ptr220 = getelementptr inbounds i8, i8* %c, i64 15
   store i8 %or218, i8* %incdec.ptr199, align 1
-  %arrayidx225 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 16
+  %arrayidx225 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 16
   %13 = bitcast i16* %arrayidx225 to i64*
-  %14 = load i64* %13, align 16
+  %14 = load i64, i64* %13, align 16
   %conv22616 = trunc i64 %14 to i8
   %and227 = shl i8 %conv22616, 3
   %shl228 = and i8 %and227, 56
-  %incdec.ptr235 = getelementptr inbounds i8* %c, i64 16
+  %incdec.ptr235 = getelementptr inbounds i8, i8* %c, i64 16
   store i8 %shl228, i8* %incdec.ptr220, align 1
   %15 = lshr i64 %14, 32
   %and23832 = shl nuw nsw i64 %15, 5
   %and238 = trunc i64 %and23832 to i8
-  %incdec.ptr251 = getelementptr inbounds i8* %c, i64 17
+  %incdec.ptr251 = getelementptr inbounds i8, i8* %c, i64 17
   store i8 %and238, i8* %incdec.ptr235, align 1
-  %arrayidx266 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 23
-  %incdec.ptr272 = getelementptr inbounds i8* %c, i64 18
+  %arrayidx266 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 23
+  %incdec.ptr272 = getelementptr inbounds i8, i8* %c, i64 18
   store i8 0, i8* %incdec.ptr251, align 1
-  %16 = load i16* %arrayidx266, align 2
+  %16 = load i16, i16* %arrayidx266, align 2
   %conv27418 = trunc i16 %16 to i8
   %and275 = shl i8 %conv27418, 6
-  %incdec.ptr287 = getelementptr inbounds i8* %c, i64 19
+  %incdec.ptr287 = getelementptr inbounds i8, i8* %c, i64 19
   store i8 %and275, i8* %incdec.ptr272, align 1
-  %arrayidx288 = getelementptr inbounds [4 x i16]* %Nc, i64 0, i64 2
-  %17 = load i16* %arrayidx288, align 2
+  %arrayidx288 = getelementptr inbounds [4 x i16], [4 x i16]* %Nc, i64 0, i64 2
+  %17 = load i16, i16* %arrayidx288, align 2
   %conv28919 = zext i16 %17 to i32
   %and290 = shl nuw nsw i32 %conv28919, 1
-  %arrayidx292 = getelementptr inbounds [4 x i16]* %bc, i64 0, i64 2
-  %18 = load i16* %arrayidx292, align 2
+  %arrayidx292 = getelementptr inbounds [4 x i16], [4 x i16]* %bc, i64 0, i64 2
+  %18 = load i16, i16* %arrayidx292, align 2
   %conv29327 = zext i16 %18 to i32
   %shr29420 = lshr i32 %conv29327, 1
   %and295 = and i32 %shr29420, 1
   %or296 = or i32 %and290, %and295
   %conv297 = trunc i32 %or296 to i8
-  %incdec.ptr298 = getelementptr inbounds i8* %c, i64 20
+  %incdec.ptr298 = getelementptr inbounds i8, i8* %c, i64 20
   store i8 %conv297, i8* %incdec.ptr287, align 1
   %conv30021 = trunc i16 %18 to i8
   %and301 = shl i8 %conv30021, 7
-  %incdec.ptr314 = getelementptr inbounds i8* %c, i64 21
+  %incdec.ptr314 = getelementptr inbounds i8, i8* %c, i64 21
   store i8 %and301, i8* %incdec.ptr298, align 1
-  %incdec.ptr335 = getelementptr inbounds i8* %c, i64 22
+  %incdec.ptr335 = getelementptr inbounds i8, i8* %c, i64 22
   store i8 0, i8* %incdec.ptr314, align 1
-  %arrayidx340 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 29
-  %19 = load i16* %arrayidx340, align 2
+  %arrayidx340 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 29
+  %19 = load i16, i16* %arrayidx340, align 2
   %conv34122 = trunc i16 %19 to i8
   %and342 = shl i8 %conv34122, 3
   %shl343 = and i8 %and342, 56
-  %incdec.ptr350 = getelementptr inbounds i8* %c, i64 23
+  %incdec.ptr350 = getelementptr inbounds i8, i8* %c, i64 23
   store i8 %shl343, i8* %incdec.ptr335, align 1
-  %arrayidx355 = getelementptr inbounds [52 x i16]* %xmc, i64 0, i64 32
+  %arrayidx355 = getelementptr inbounds [52 x i16], [52 x i16]* %xmc, i64 0, i64 32
   %20 = bitcast i16* %arrayidx355 to i32*
-  %21 = load i32* %20, align 16
+  %21 = load i32, i32* %20, align 16
   %conv35623 = shl i32 %21, 2
   %shl358 = and i32 %conv35623, 28
   %22 = lshr i32 %21, 17
diff --git a/test/Transforms/BBVectorize/X86/simple-ldstr.ll b/test/Transforms/BBVectorize/X86/simple-ldstr.ll
index 1abbc34b68ec..2c05f30d0818 100644
--- a/test/Transforms/BBVectorize/X86/simple-ldstr.ll
+++ b/test/Transforms/BBVectorize/X86/simple-ldstr.ll
@@ -4,23 +4,23 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; Simple 3-pair chain with loads and stores
 define void @test1(double* %a, double* %b, double* %c) nounwind uwtable readonly {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   store double %mul, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   ret void
 ; CHECK-LABEL: @test1(
 ; CHECK: %i0.v.i0 = bitcast double* %a to <2 x double>*
 ; CHECK: %i1.v.i0 = bitcast double* %b to <2 x double>*
-; CHECK: %i0 = load <2 x double>* %i0.v.i0, align 8
-; CHECK: %i1 = load <2 x double>* %i1.v.i0, align 8
+; CHECK: %i0 = load <2 x double>, <2 x double>* %i0.v.i0, align 8
+; CHECK: %i1 = load <2 x double>, <2 x double>* %i1.v.i0, align 8
 ; CHECK: %mul = fmul <2 x double> %i0, %i1
 ; CHECK: %0 = bitcast double* %c to <2 x double>*
 ; CHECK: store <2 x double> %mul, <2 x double>* %0, align 8
diff --git a/test/Transforms/BBVectorize/X86/wr-aliases.ll b/test/Transforms/BBVectorize/X86/wr-aliases.ll
index 34b1d4e9cae3..56448c0e5471 100644
--- a/test/Transforms/BBVectorize/X86/wr-aliases.ll
+++ b/test/Transforms/BBVectorize/X86/wr-aliases.ll
@@ -27,27 +27,27 @@ arrayctor.cont.ret.exitStub:                      ; preds = %arrayctor.cont
 ; CHECK: <2 x double>
 ; CHECK: @_ZL12printQBezier7QBezier
 ; CHECK: store double %mul8.i, double* %x3.i, align 16
-; CHECK: load double* %x3.i, align 16
+; CHECK: load double, double* %x3.i, align 16
 ; CHECK: ret
 
 arrayctor.cont:                                   ; preds = %newFuncRoot
-  %ref.tmp.sroa.0.0.idx = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 0
+  %ref.tmp.sroa.0.0.idx = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 0
   store double 1.000000e+01, double* %ref.tmp.sroa.0.0.idx, align 16
-  %ref.tmp.sroa.2.0.idx1 = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 1
+  %ref.tmp.sroa.2.0.idx1 = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 1
   store double 2.000000e+01, double* %ref.tmp.sroa.2.0.idx1, align 8
-  %ref.tmp.sroa.3.0.idx2 = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 2
+  %ref.tmp.sroa.3.0.idx2 = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 2
   store double 3.000000e+01, double* %ref.tmp.sroa.3.0.idx2, align 16
-  %ref.tmp.sroa.4.0.idx3 = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 3
+  %ref.tmp.sroa.4.0.idx3 = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 3
   store double 4.000000e+01, double* %ref.tmp.sroa.4.0.idx3, align 8
-  %ref.tmp.sroa.5.0.idx4 = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 4
+  %ref.tmp.sroa.5.0.idx4 = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 4
   store double 5.000000e+01, double* %ref.tmp.sroa.5.0.idx4, align 16
-  %ref.tmp.sroa.6.0.idx5 = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 5
+  %ref.tmp.sroa.6.0.idx5 = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 5
   store double 6.000000e+01, double* %ref.tmp.sroa.6.0.idx5, align 8
-  %ref.tmp.sroa.7.0.idx6 = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 6
+  %ref.tmp.sroa.7.0.idx6 = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 6
   store double 7.000000e+01, double* %ref.tmp.sroa.7.0.idx6, align 16
-  %ref.tmp.sroa.8.0.idx7 = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 7
+  %ref.tmp.sroa.8.0.idx7 = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 7
   store double 8.000000e+01, double* %ref.tmp.sroa.8.0.idx7, align 8
-  %add.ptr = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 1
+  %add.ptr = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 1
   %v0 = bitcast %class.QBezier.15* %agg.tmp.i to i8*
   call void @llvm.lifetime.start(i64 64, i8* %v0)
   %v1 = bitcast %class.QBezier.15* %agg.tmp55.i to i8*
@@ -57,77 +57,77 @@ arrayctor.cont:                                   ; preds = %newFuncRoot
   %v3 = bitcast [10 x %class.QBezier.15]* %beziers to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %v0, i8* %v3, i64 64, i32 8, i1 false)
   call fastcc void @_ZL12printQBezier7QBezier(%class.QBezier.15* byval align 8 %agg.tmp.i)
-  %x2.i = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 2
-  %v4 = load double* %x2.i, align 16
-  %x3.i = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 4
-  %v5 = load double* %x3.i, align 16
+  %x2.i = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 2
+  %v4 = load double, double* %x2.i, align 16
+  %x3.i = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 4
+  %v5 = load double, double* %x3.i, align 16
   %add.i = fadd double %v4, %v5
   %mul.i = fmul double 5.000000e-01, %add.i
-  %x1.i = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 0
-  %v6 = load double* %x1.i, align 16
+  %x1.i = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 0
+  %v6 = load double, double* %x1.i, align 16
   %add3.i = fadd double %v4, %v6
   %mul4.i = fmul double 5.000000e-01, %add3.i
-  %x25.i = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 1, i32 2
+  %x25.i = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 1, i32 2
   store double %mul4.i, double* %x25.i, align 16
-  %v7 = load double* %x3.i, align 16
-  %x4.i = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 6
-  %v8 = load double* %x4.i, align 16
+  %v7 = load double, double* %x3.i, align 16
+  %x4.i = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 6
+  %v8 = load double, double* %x4.i, align 16
   %add7.i = fadd double %v7, %v8
   %mul8.i = fmul double 5.000000e-01, %add7.i
   store double %mul8.i, double* %x3.i, align 16
-  %v9 = load double* %x1.i, align 16
-  %x111.i = getelementptr inbounds %class.QBezier.15* %add.ptr, i64 0, i32 0
+  %v9 = load double, double* %x1.i, align 16
+  %x111.i = getelementptr inbounds %class.QBezier.15, %class.QBezier.15* %add.ptr, i64 0, i32 0
   store double %v9, double* %x111.i, align 16
-  %v10 = load double* %x25.i, align 16
+  %v10 = load double, double* %x25.i, align 16
   %add15.i = fadd double %mul.i, %v10
   %mul16.i = fmul double 5.000000e-01, %add15.i
-  %x317.i = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 1, i32 4
+  %x317.i = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 1, i32 4
   store double %mul16.i, double* %x317.i, align 16
-  %v11 = load double* %x3.i, align 16
+  %v11 = load double, double* %x3.i, align 16
   %add19.i = fadd double %mul.i, %v11
   %mul20.i = fmul double 5.000000e-01, %add19.i
   store double %mul20.i, double* %x2.i, align 16
-  %v12 = load double* %x317.i, align 16
+  %v12 = load double, double* %x317.i, align 16
   %add24.i = fadd double %v12, %mul20.i
   %mul25.i = fmul double 5.000000e-01, %add24.i
   store double %mul25.i, double* %x1.i, align 16
-  %x427.i = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 1, i32 6
+  %x427.i = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 1, i32 6
   store double %mul25.i, double* %x427.i, align 16
-  %y2.i = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 3
-  %v13 = load double* %y2.i, align 8
-  %y3.i = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 5
-  %v14 = load double* %y3.i, align 8
+  %y2.i = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 3
+  %v13 = load double, double* %y2.i, align 8
+  %y3.i = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 5
+  %v14 = load double, double* %y3.i, align 8
   %add28.i = fadd double %v13, %v14
   %div.i = fmul double 5.000000e-01, %add28.i
-  %y1.i = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 1
-  %v15 = load double* %y1.i, align 8
+  %y1.i = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 1
+  %v15 = load double, double* %y1.i, align 8
   %add30.i = fadd double %v13, %v15
   %mul31.i = fmul double 5.000000e-01, %add30.i
-  %y232.i = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 1, i32 3
+  %y232.i = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 1, i32 3
   store double %mul31.i, double* %y232.i, align 8
-  %v16 = load double* %y3.i, align 8
-  %y4.i = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 7
-  %v17 = load double* %y4.i, align 8
+  %v16 = load double, double* %y3.i, align 8
+  %y4.i = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 0, i32 7
+  %v17 = load double, double* %y4.i, align 8
   %add34.i = fadd double %v16, %v17
   %mul35.i = fmul double 5.000000e-01, %add34.i
   store double %mul35.i, double* %y3.i, align 8
-  %v18 = load double* %y1.i, align 8
-  %y138.i = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 1, i32 1
+  %v18 = load double, double* %y1.i, align 8
+  %y138.i = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 1, i32 1
   store double %v18, double* %y138.i, align 8
-  %v19 = load double* %y232.i, align 8
+  %v19 = load double, double* %y232.i, align 8
   %add42.i = fadd double %div.i, %v19
   %mul43.i = fmul double 5.000000e-01, %add42.i
-  %y344.i = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 1, i32 5
+  %y344.i = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 1, i32 5
   store double %mul43.i, double* %y344.i, align 8
-  %v20 = load double* %y3.i, align 8
+  %v20 = load double, double* %y3.i, align 8
   %add46.i = fadd double %div.i, %v20
   %mul47.i = fmul double 5.000000e-01, %add46.i
   store double %mul47.i, double* %y2.i, align 8
-  %v21 = load double* %y344.i, align 8
+  %v21 = load double, double* %y344.i, align 8
   %add51.i = fadd double %v21, %mul47.i
   %mul52.i = fmul double 5.000000e-01, %add51.i
   store double %mul52.i, double* %y1.i, align 8
-  %y454.i = getelementptr inbounds [10 x %class.QBezier.15]* %beziers, i64 0, i64 1, i32 7
+  %y454.i = getelementptr inbounds [10 x %class.QBezier.15], [10 x %class.QBezier.15]* %beziers, i64 0, i64 1, i32 7
   store double %mul52.i, double* %y454.i, align 8
   %v22 = bitcast %class.QBezier.15* %add.ptr to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %v1, i8* %v22, i64 64, i32 8, i1 false)
diff --git a/test/Transforms/BBVectorize/func-alias.ll b/test/Transforms/BBVectorize/func-alias.ll
index 9d0cc07c1593..ab72ec0e1991 100644
--- a/test/Transforms/BBVectorize/func-alias.ll
+++ b/test/Transforms/BBVectorize/func-alias.ll
@@ -47,99 +47,99 @@ codeRepl80.exitStub:                              ; preds = %"<bb 34>"
   ret i1 false
 
 "<bb 34>":                                        ; preds = %newFuncRoot
-  %tmp128 = getelementptr inbounds %struct.__st_parameter_dt* %memtmp3, i32 0, i32 0
-  %tmp129 = getelementptr inbounds %struct.__st_parameter_common* %tmp128, i32 0, i32 2
-  store i8* getelementptr inbounds ([11 x i8]* @.cst4, i64 0, i64 0), i8** %tmp129, align 8
-  %tmp130 = getelementptr inbounds %struct.__st_parameter_dt* %memtmp3, i32 0, i32 0
-  %tmp131 = getelementptr inbounds %struct.__st_parameter_common* %tmp130, i32 0, i32 3
+  %tmp128 = getelementptr inbounds %struct.__st_parameter_dt, %struct.__st_parameter_dt* %memtmp3, i32 0, i32 0
+  %tmp129 = getelementptr inbounds %struct.__st_parameter_common, %struct.__st_parameter_common* %tmp128, i32 0, i32 2
+  store i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.cst4, i64 0, i64 0), i8** %tmp129, align 8
+  %tmp130 = getelementptr inbounds %struct.__st_parameter_dt, %struct.__st_parameter_dt* %memtmp3, i32 0, i32 0
+  %tmp131 = getelementptr inbounds %struct.__st_parameter_common, %struct.__st_parameter_common* %tmp130, i32 0, i32 3
   store i32 31495, i32* %tmp131, align 4
-  %tmp132 = getelementptr inbounds %struct.__st_parameter_dt* %memtmp3, i32 0, i32 5
-  store i8* getelementptr inbounds ([214 x i8]* @.cst823, i64 0, i64 0), i8** %tmp132, align 8
-  %tmp133 = getelementptr inbounds %struct.__st_parameter_dt* %memtmp3, i32 0, i32 6
+  %tmp132 = getelementptr inbounds %struct.__st_parameter_dt, %struct.__st_parameter_dt* %memtmp3, i32 0, i32 5
+  store i8* getelementptr inbounds ([214 x i8], [214 x i8]* @.cst823, i64 0, i64 0), i8** %tmp132, align 8
+  %tmp133 = getelementptr inbounds %struct.__st_parameter_dt, %struct.__st_parameter_dt* %memtmp3, i32 0, i32 6
   store i32 214, i32* %tmp133, align 4
-  %tmp134 = getelementptr inbounds %struct.__st_parameter_dt* %memtmp3, i32 0, i32 0
-  %tmp135 = getelementptr inbounds %struct.__st_parameter_common* %tmp134, i32 0, i32 0
+  %tmp134 = getelementptr inbounds %struct.__st_parameter_dt, %struct.__st_parameter_dt* %memtmp3, i32 0, i32 0
+  %tmp135 = getelementptr inbounds %struct.__st_parameter_common, %struct.__st_parameter_common* %tmp134, i32 0, i32 0
   store i32 4096, i32* %tmp135, align 4
-  %iounit.8748_288 = load i32* @__main1_MOD_iounit, align 4
-  %tmp136 = getelementptr inbounds %struct.__st_parameter_dt* %memtmp3, i32 0, i32 0
-  %tmp137 = getelementptr inbounds %struct.__st_parameter_common* %tmp136, i32 0, i32 1
+  %iounit.8748_288 = load i32, i32* @__main1_MOD_iounit, align 4
+  %tmp136 = getelementptr inbounds %struct.__st_parameter_dt, %struct.__st_parameter_dt* %memtmp3, i32 0, i32 0
+  %tmp137 = getelementptr inbounds %struct.__st_parameter_common, %struct.__st_parameter_common* %tmp136, i32 0, i32 1
   store i32 %iounit.8748_288, i32* %tmp137, align 4
   call void @_gfortran_st_write(%struct.__st_parameter_dt* %memtmp3) nounwind
   call void bitcast (void (%struct.__st_parameter_dt*, i8*, i32)* @_gfortran_transfer_integer_write to void (%struct.__st_parameter_dt*, i32*, i32)*)(%struct.__st_parameter_dt* %memtmp3, i32* @j.4580, i32 4) nounwind
 ; CHECK: @_gfortran_transfer_integer_write
-  %D.75807_289 = load i8** getelementptr inbounds (%"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 0), align 8
-  %j.8758_290 = load i32* @j.4580, align 4
+  %D.75807_289 = load i8*, i8** getelementptr inbounds (%"struct.array4_real(kind=4)", %"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 0), align 8
+  %j.8758_290 = load i32, i32* @j.4580, align 4
   %D.75760_291 = sext i32 %j.8758_290 to i64
-  %iave.8736_292 = load i32* @__main1_MOD_iave, align 4
+  %iave.8736_292 = load i32, i32* @__main1_MOD_iave, align 4
   %D.75620_293 = sext i32 %iave.8736_292 to i64
-  %D.75808_294 = load i64* getelementptr inbounds (%"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 3, i64 2, i32 0), align 8
+  %D.75808_294 = load i64, i64* getelementptr inbounds (%"struct.array4_real(kind=4)", %"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 3, i64 2, i32 0), align 8
   %D.75809_295 = mul nsw i64 %D.75620_293, %D.75808_294
-  %igrp.8737_296 = load i32* @__main1_MOD_igrp, align 4
+  %igrp.8737_296 = load i32, i32* @__main1_MOD_igrp, align 4
   %D.75635_297 = sext i32 %igrp.8737_296 to i64
-  %D.75810_298 = load i64* getelementptr inbounds (%"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 3, i64 1, i32 0), align 8
+  %D.75810_298 = load i64, i64* getelementptr inbounds (%"struct.array4_real(kind=4)", %"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 3, i64 1, i32 0), align 8
   %D.75811_299 = mul nsw i64 %D.75635_297, %D.75810_298
   %D.75812_300 = add nsw i64 %D.75809_295, %D.75811_299
   %D.75813_301 = add nsw i64 %D.75760_291, %D.75812_300
-  %ityp.8750_302 = load i32* @__main1_MOD_ityp, align 4
+  %ityp.8750_302 = load i32, i32* @__main1_MOD_ityp, align 4
   %D.75704_303 = sext i32 %ityp.8750_302 to i64
-  %D.75814_304 = load i64* getelementptr inbounds (%"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 3, i64 3, i32 0), align 8
+  %D.75814_304 = load i64, i64* getelementptr inbounds (%"struct.array4_real(kind=4)", %"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 3, i64 3, i32 0), align 8
   %D.75815_305 = mul nsw i64 %D.75704_303, %D.75814_304
   %D.75816_306 = add nsw i64 %D.75813_301, %D.75815_305
-  %D.75817_307 = load i64* getelementptr inbounds (%"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 1), align 8
+  %D.75817_307 = load i64, i64* getelementptr inbounds (%"struct.array4_real(kind=4)", %"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 1), align 8
   %D.75818_308 = add nsw i64 %D.75816_306, %D.75817_307
   %tmp138 = bitcast i8* %D.75807_289 to [0 x float]*
   %tmp139 = bitcast [0 x float]* %tmp138 to float*
-  %D.75819_309 = getelementptr inbounds float* %tmp139, i64 %D.75818_308
+  %D.75819_309 = getelementptr inbounds float, float* %tmp139, i64 %D.75818_308
   call void bitcast (void (%struct.__st_parameter_dt*, i8*, i32)* @_gfortran_transfer_real_write to void (%struct.__st_parameter_dt*, float*, i32)*)(%struct.__st_parameter_dt* %memtmp3, float* %D.75819_309, i32 4) nounwind
 ; CHECK: @_gfortran_transfer_real_write
-  %D.75820_310 = load i8** getelementptr inbounds (%struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 0), align 8
-  %j.8758_311 = load i32* @j.4580, align 4
+  %D.75820_310 = load i8*, i8** getelementptr inbounds (%struct.array4_unknown, %struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 0), align 8
+  %j.8758_311 = load i32, i32* @j.4580, align 4
   %D.75760_312 = sext i32 %j.8758_311 to i64
-  %iave.8736_313 = load i32* @__main1_MOD_iave, align 4
+  %iave.8736_313 = load i32, i32* @__main1_MOD_iave, align 4
   %D.75620_314 = sext i32 %iave.8736_313 to i64
-  %D.75821_315 = load i64* getelementptr inbounds (%struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 3, i64 2, i32 0), align 8
+  %D.75821_315 = load i64, i64* getelementptr inbounds (%struct.array4_unknown, %struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 3, i64 2, i32 0), align 8
   %D.75822_316 = mul nsw i64 %D.75620_314, %D.75821_315
-  %igrp.8737_317 = load i32* @__main1_MOD_igrp, align 4
+  %igrp.8737_317 = load i32, i32* @__main1_MOD_igrp, align 4
   %D.75635_318 = sext i32 %igrp.8737_317 to i64
-  %D.75823_319 = load i64* getelementptr inbounds (%struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 3, i64 1, i32 0), align 8
+  %D.75823_319 = load i64, i64* getelementptr inbounds (%struct.array4_unknown, %struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 3, i64 1, i32 0), align 8
   %D.75824_320 = mul nsw i64 %D.75635_318, %D.75823_319
   %D.75825_321 = add nsw i64 %D.75822_316, %D.75824_320
   %D.75826_322 = add nsw i64 %D.75760_312, %D.75825_321
-  %ityp.8750_323 = load i32* @__main1_MOD_ityp, align 4
+  %ityp.8750_323 = load i32, i32* @__main1_MOD_ityp, align 4
   %D.75704_324 = sext i32 %ityp.8750_323 to i64
-  %D.75827_325 = load i64* getelementptr inbounds (%struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 3, i64 3, i32 0), align 8
+  %D.75827_325 = load i64, i64* getelementptr inbounds (%struct.array4_unknown, %struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 3, i64 3, i32 0), align 8
   %D.75828_326 = mul nsw i64 %D.75704_324, %D.75827_325
   %D.75829_327 = add nsw i64 %D.75826_322, %D.75828_326
-  %D.75830_328 = load i64* getelementptr inbounds (%struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 1), align 8
+  %D.75830_328 = load i64, i64* getelementptr inbounds (%struct.array4_unknown, %struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 1), align 8
   %D.75831_329 = add nsw i64 %D.75829_327, %D.75830_328
   %tmp140 = bitcast i8* %D.75820_310 to [0 x [1 x i8]]*
   %tmp141 = bitcast [0 x [1 x i8]]* %tmp140 to [1 x i8]*
-  %D.75832_330 = getelementptr inbounds [1 x i8]* %tmp141, i64 %D.75831_329
+  %D.75832_330 = getelementptr inbounds [1 x i8], [1 x i8]* %tmp141, i64 %D.75831_329
   call void bitcast (void (%struct.__st_parameter_dt*, i8*, i32)* @_gfortran_transfer_character_write to void (%struct.__st_parameter_dt*, [1 x i8]*, i32)*)(%struct.__st_parameter_dt* %memtmp3, [1 x i8]* %D.75832_330, i32 1) nounwind
 ; CHECK: @_gfortran_transfer_character_write
-  %D.75833_331 = load i8** getelementptr inbounds (%"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 0), align 8
-  %j.8758_332 = load i32* @j.4580, align 4
+  %D.75833_331 = load i8*, i8** getelementptr inbounds (%"struct.array4_integer(kind=4).73", %"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 0), align 8
+  %j.8758_332 = load i32, i32* @j.4580, align 4
   %D.75760_333 = sext i32 %j.8758_332 to i64
-  %iave.8736_334 = load i32* @__main1_MOD_iave, align 4
+  %iave.8736_334 = load i32, i32* @__main1_MOD_iave, align 4
   %D.75620_335 = sext i32 %iave.8736_334 to i64
-  %D.75834_336 = load i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 3, i64 2, i32 0), align 8
+  %D.75834_336 = load i64, i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73", %"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 3, i64 2, i32 0), align 8
   %D.75835_337 = mul nsw i64 %D.75620_335, %D.75834_336
-  %igrp.8737_338 = load i32* @__main1_MOD_igrp, align 4
+  %igrp.8737_338 = load i32, i32* @__main1_MOD_igrp, align 4
   %D.75635_339 = sext i32 %igrp.8737_338 to i64
-  %D.75836_340 = load i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 3, i64 1, i32 0), align 8
+  %D.75836_340 = load i64, i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73", %"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 3, i64 1, i32 0), align 8
   %D.75837_341 = mul nsw i64 %D.75635_339, %D.75836_340
   %D.75838_342 = add nsw i64 %D.75835_337, %D.75837_341
   %D.75839_343 = add nsw i64 %D.75760_333, %D.75838_342
-  %ityp.8750_344 = load i32* @__main1_MOD_ityp, align 4
+  %ityp.8750_344 = load i32, i32* @__main1_MOD_ityp, align 4
   %D.75704_345 = sext i32 %ityp.8750_344 to i64
-  %D.75840_346 = load i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 3, i64 3, i32 0), align 8
+  %D.75840_346 = load i64, i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73", %"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 3, i64 3, i32 0), align 8
   %D.75841_347 = mul nsw i64 %D.75704_345, %D.75840_346
   %D.75842_348 = add nsw i64 %D.75839_343, %D.75841_347
-  %D.75843_349 = load i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 1), align 8
+  %D.75843_349 = load i64, i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73", %"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 1), align 8
   %D.75844_350 = add nsw i64 %D.75842_348, %D.75843_349
   %tmp142 = bitcast i8* %D.75833_331 to [0 x i32]*
   %tmp143 = bitcast [0 x i32]* %tmp142 to i32*
-  %D.75845_351 = getelementptr inbounds i32* %tmp143, i64 %D.75844_350
+  %D.75845_351 = getelementptr inbounds i32, i32* %tmp143, i64 %D.75844_350
   call void bitcast (void (%struct.__st_parameter_dt*, i8*, i32)* @_gfortran_transfer_integer_write to void (%struct.__st_parameter_dt*, i32*, i32)*)(%struct.__st_parameter_dt* %memtmp3, i32* %D.75845_351, i32 4) nounwind
 ; CHECK: @_gfortran_transfer_integer_write
   call void bitcast (void (%struct.__st_parameter_dt*, i8*, i32)* @_gfortran_transfer_real_write to void (%struct.__st_parameter_dt*, float*, i32)*)(%struct.__st_parameter_dt* %memtmp3, float* @xr1.4592, i32 4) nounwind
@@ -150,79 +150,79 @@ codeRepl80.exitStub:                              ; preds = %"<bb 34>"
 ; CHECK: @_gfortran_transfer_character_write
   call void bitcast (void (%struct.__st_parameter_dt*, i8*, i32)* @_gfortran_transfer_integer_write to void (%struct.__st_parameter_dt*, i32*, i32)*)(%struct.__st_parameter_dt* %memtmp3, i32* @j1.4581, i32 4) nounwind
 ; CHECK: @_gfortran_transfer_integer_write
-  %D.75807_352 = load i8** getelementptr inbounds (%"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 0), align 8
-  %j1.8760_353 = load i32* @j1.4581, align 4
+  %D.75807_352 = load i8*, i8** getelementptr inbounds (%"struct.array4_real(kind=4)", %"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 0), align 8
+  %j1.8760_353 = load i32, i32* @j1.4581, align 4
   %D.75773_354 = sext i32 %j1.8760_353 to i64
-  %iave.8736_355 = load i32* @__main1_MOD_iave, align 4
+  %iave.8736_355 = load i32, i32* @__main1_MOD_iave, align 4
   %D.75620_356 = sext i32 %iave.8736_355 to i64
-  %D.75808_357 = load i64* getelementptr inbounds (%"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 3, i64 2, i32 0), align 8
+  %D.75808_357 = load i64, i64* getelementptr inbounds (%"struct.array4_real(kind=4)", %"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 3, i64 2, i32 0), align 8
   %D.75809_358 = mul nsw i64 %D.75620_356, %D.75808_357
-  %igrp.8737_359 = load i32* @__main1_MOD_igrp, align 4
+  %igrp.8737_359 = load i32, i32* @__main1_MOD_igrp, align 4
   %D.75635_360 = sext i32 %igrp.8737_359 to i64
-  %D.75810_361 = load i64* getelementptr inbounds (%"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 3, i64 1, i32 0), align 8
+  %D.75810_361 = load i64, i64* getelementptr inbounds (%"struct.array4_real(kind=4)", %"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 3, i64 1, i32 0), align 8
   %D.75811_362 = mul nsw i64 %D.75635_360, %D.75810_361
   %D.75812_363 = add nsw i64 %D.75809_358, %D.75811_362
   %D.75846_364 = add nsw i64 %D.75773_354, %D.75812_363
-  %ityp.8750_365 = load i32* @__main1_MOD_ityp, align 4
+  %ityp.8750_365 = load i32, i32* @__main1_MOD_ityp, align 4
   %D.75704_366 = sext i32 %ityp.8750_365 to i64
-  %D.75814_367 = load i64* getelementptr inbounds (%"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 3, i64 3, i32 0), align 8
+  %D.75814_367 = load i64, i64* getelementptr inbounds (%"struct.array4_real(kind=4)", %"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 3, i64 3, i32 0), align 8
   %D.75815_368 = mul nsw i64 %D.75704_366, %D.75814_367
   %D.75847_369 = add nsw i64 %D.75846_364, %D.75815_368
-  %D.75817_370 = load i64* getelementptr inbounds (%"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 1), align 8
+  %D.75817_370 = load i64, i64* getelementptr inbounds (%"struct.array4_real(kind=4)", %"struct.array4_real(kind=4)"* @__main1_MOD_rmxval, i64 0, i32 1), align 8
   %D.75848_371 = add nsw i64 %D.75847_369, %D.75817_370
   %tmp144 = bitcast i8* %D.75807_352 to [0 x float]*
   %tmp145 = bitcast [0 x float]* %tmp144 to float*
-  %D.75849_372 = getelementptr inbounds float* %tmp145, i64 %D.75848_371
+  %D.75849_372 = getelementptr inbounds float, float* %tmp145, i64 %D.75848_371
   call void bitcast (void (%struct.__st_parameter_dt*, i8*, i32)* @_gfortran_transfer_real_write to void (%struct.__st_parameter_dt*, float*, i32)*)(%struct.__st_parameter_dt* %memtmp3, float* %D.75849_372, i32 4) nounwind
 ; CHECK: @_gfortran_transfer_real_write
-  %D.75820_373 = load i8** getelementptr inbounds (%struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 0), align 8
-  %j1.8760_374 = load i32* @j1.4581, align 4
+  %D.75820_373 = load i8*, i8** getelementptr inbounds (%struct.array4_unknown, %struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 0), align 8
+  %j1.8760_374 = load i32, i32* @j1.4581, align 4
   %D.75773_375 = sext i32 %j1.8760_374 to i64
-  %iave.8736_376 = load i32* @__main1_MOD_iave, align 4
+  %iave.8736_376 = load i32, i32* @__main1_MOD_iave, align 4
   %D.75620_377 = sext i32 %iave.8736_376 to i64
-  %D.75821_378 = load i64* getelementptr inbounds (%struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 3, i64 2, i32 0), align 8
+  %D.75821_378 = load i64, i64* getelementptr inbounds (%struct.array4_unknown, %struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 3, i64 2, i32 0), align 8
   %D.75822_379 = mul nsw i64 %D.75620_377, %D.75821_378
-  %igrp.8737_380 = load i32* @__main1_MOD_igrp, align 4
+  %igrp.8737_380 = load i32, i32* @__main1_MOD_igrp, align 4
   %D.75635_381 = sext i32 %igrp.8737_380 to i64
-  %D.75823_382 = load i64* getelementptr inbounds (%struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 3, i64 1, i32 0), align 8
+  %D.75823_382 = load i64, i64* getelementptr inbounds (%struct.array4_unknown, %struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 3, i64 1, i32 0), align 8
   %D.75824_383 = mul nsw i64 %D.75635_381, %D.75823_382
   %D.75825_384 = add nsw i64 %D.75822_379, %D.75824_383
   %D.75850_385 = add nsw i64 %D.75773_375, %D.75825_384
-  %ityp.8750_386 = load i32* @__main1_MOD_ityp, align 4
+  %ityp.8750_386 = load i32, i32* @__main1_MOD_ityp, align 4
   %D.75704_387 = sext i32 %ityp.8750_386 to i64
-  %D.75827_388 = load i64* getelementptr inbounds (%struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 3, i64 3, i32 0), align 8
+  %D.75827_388 = load i64, i64* getelementptr inbounds (%struct.array4_unknown, %struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 3, i64 3, i32 0), align 8
   %D.75828_389 = mul nsw i64 %D.75704_387, %D.75827_388
   %D.75851_390 = add nsw i64 %D.75850_385, %D.75828_389
-  %D.75830_391 = load i64* getelementptr inbounds (%struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 1), align 8
+  %D.75830_391 = load i64, i64* getelementptr inbounds (%struct.array4_unknown, %struct.array4_unknown* @__main1_MOD_mclmsg, i64 0, i32 1), align 8
   %D.75852_392 = add nsw i64 %D.75851_390, %D.75830_391
   %tmp146 = bitcast i8* %D.75820_373 to [0 x [1 x i8]]*
   %tmp147 = bitcast [0 x [1 x i8]]* %tmp146 to [1 x i8]*
-  %D.75853_393 = getelementptr inbounds [1 x i8]* %tmp147, i64 %D.75852_392
+  %D.75853_393 = getelementptr inbounds [1 x i8], [1 x i8]* %tmp147, i64 %D.75852_392
   call void bitcast (void (%struct.__st_parameter_dt*, i8*, i32)* @_gfortran_transfer_character_write to void (%struct.__st_parameter_dt*, [1 x i8]*, i32)*)(%struct.__st_parameter_dt* %memtmp3, [1 x i8]* %D.75853_393, i32 1) nounwind
 ; CHECK: @_gfortran_transfer_character_write
-  %D.75833_394 = load i8** getelementptr inbounds (%"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 0), align 8
-  %j1.8760_395 = load i32* @j1.4581, align 4
+  %D.75833_394 = load i8*, i8** getelementptr inbounds (%"struct.array4_integer(kind=4).73", %"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 0), align 8
+  %j1.8760_395 = load i32, i32* @j1.4581, align 4
   %D.75773_396 = sext i32 %j1.8760_395 to i64
-  %iave.8736_397 = load i32* @__main1_MOD_iave, align 4
+  %iave.8736_397 = load i32, i32* @__main1_MOD_iave, align 4
   %D.75620_398 = sext i32 %iave.8736_397 to i64
-  %D.75834_399 = load i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 3, i64 2, i32 0), align 8
+  %D.75834_399 = load i64, i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73", %"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 3, i64 2, i32 0), align 8
   %D.75835_400 = mul nsw i64 %D.75620_398, %D.75834_399
-  %igrp.8737_401 = load i32* @__main1_MOD_igrp, align 4
+  %igrp.8737_401 = load i32, i32* @__main1_MOD_igrp, align 4
   %D.75635_402 = sext i32 %igrp.8737_401 to i64
-  %D.75836_403 = load i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 3, i64 1, i32 0), align 8
+  %D.75836_403 = load i64, i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73", %"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 3, i64 1, i32 0), align 8
   %D.75837_404 = mul nsw i64 %D.75635_402, %D.75836_403
   %D.75838_405 = add nsw i64 %D.75835_400, %D.75837_404
   %D.75854_406 = add nsw i64 %D.75773_396, %D.75838_405
-  %ityp.8750_407 = load i32* @__main1_MOD_ityp, align 4
+  %ityp.8750_407 = load i32, i32* @__main1_MOD_ityp, align 4
   %D.75704_408 = sext i32 %ityp.8750_407 to i64
-  %D.75840_409 = load i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 3, i64 3, i32 0), align 8
+  %D.75840_409 = load i64, i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73", %"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 3, i64 3, i32 0), align 8
   %D.75841_410 = mul nsw i64 %D.75704_408, %D.75840_409
   %D.75855_411 = add nsw i64 %D.75854_406, %D.75841_410
-  %D.75843_412 = load i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 1), align 8
+  %D.75843_412 = load i64, i64* getelementptr inbounds (%"struct.array4_integer(kind=4).73", %"struct.array4_integer(kind=4).73"* @__main1_MOD_mxdate, i64 0, i32 1), align 8
   %D.75856_413 = add nsw i64 %D.75855_411, %D.75843_412
   %tmp148 = bitcast i8* %D.75833_394 to [0 x i32]*
   %tmp149 = bitcast [0 x i32]* %tmp148 to i32*
-  %D.75857_414 = getelementptr inbounds i32* %tmp149, i64 %D.75856_413
+  %D.75857_414 = getelementptr inbounds i32, i32* %tmp149, i64 %D.75856_413
   call void bitcast (void (%struct.__st_parameter_dt*, i8*, i32)* @_gfortran_transfer_integer_write to void (%struct.__st_parameter_dt*, i32*, i32)*)(%struct.__st_parameter_dt* %memtmp3, i32* %D.75857_414, i32 4) nounwind
 ; CHECK: @_gfortran_transfer_integer_write
   call void bitcast (void (%struct.__st_parameter_dt*, i8*, i32)* @_gfortran_transfer_real_write to void (%struct.__st_parameter_dt*, float*, i32)*)(%struct.__st_parameter_dt* %memtmp3, float* @xr2.4593, i32 4) nounwind
@@ -233,9 +233,9 @@ codeRepl80.exitStub:                              ; preds = %"<bb 34>"
 ; CHECK: @_gfortran_transfer_character_write
   call void @_gfortran_st_write_done(%struct.__st_parameter_dt* %memtmp3) nounwind
 ; CHECK: @_gfortran_st_write_done
-  %j.8758_415 = load i32* @j.4580, align 4
+  %j.8758_415 = load i32, i32* @j.4580, align 4
   %D.4634_416 = icmp eq i32 %j.8758_415, %D.4627_188.reload
-  %j.8758_417 = load i32* @j.4580, align 4
+  %j.8758_417 = load i32, i32* @j.4580, align 4
   %j.8770_418 = add nsw i32 %j.8758_417, 1
   store i32 %j.8770_418, i32* @j.4580, align 4
   %tmp150 = icmp ne i1 %D.4634_416, false
diff --git a/test/Transforms/BBVectorize/ld1.ll b/test/Transforms/BBVectorize/ld1.ll
index 9c79eef05f7b..368c38aa5ce7 100644
--- a/test/Transforms/BBVectorize/ld1.ll
+++ b/test/Transforms/BBVectorize/ld1.ll
@@ -3,18 +3,18 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 define double @test1(double* %a, double* %b, double* %c) nounwind uwtable readonly {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
-  %i2 = load double* %c, align 8
+  %i2 = load double, double* %c, align 8
   %add = fadd double %mul, %i2
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
-  %arrayidx6 = getelementptr inbounds double* %c, i64 1
-  %i5 = load double* %arrayidx6, align 8
+  %arrayidx6 = getelementptr inbounds double, double* %c, i64 1
+  %i5 = load double, double* %arrayidx6, align 8
   %add7 = fadd double %mul5, %i5
   %mul9 = fmul double %add, %i1
   %add11 = fadd double %mul9, %i2
@@ -26,10 +26,10 @@ entry:
 ; CHECK: %i0.v.i0 = bitcast double* %a to <2 x double>*
 ; CHECK: %i1.v.i0 = bitcast double* %b to <2 x double>*
 ; CHECK: %i2.v.i0 = bitcast double* %c to <2 x double>*
-; CHECK: %i0 = load <2 x double>* %i0.v.i0, align 8
-; CHECK: %i1 = load <2 x double>* %i1.v.i0, align 8
+; CHECK: %i0 = load <2 x double>, <2 x double>* %i0.v.i0, align 8
+; CHECK: %i1 = load <2 x double>, <2 x double>* %i1.v.i0, align 8
 ; CHECK: %mul = fmul <2 x double> %i0, %i1
-; CHECK: %i2 = load <2 x double>* %i2.v.i0, align 8
+; CHECK: %i2 = load <2 x double>, <2 x double>* %i2.v.i0, align 8
 ; CHECK: %add = fadd <2 x double> %mul, %i2
 ; CHECK: %mul9 = fmul <2 x double> %add, %i1
 ; CHECK: %add11 = fadd <2 x double> %mul9, %i2
diff --git a/test/Transforms/BBVectorize/loop1.ll b/test/Transforms/BBVectorize/loop1.ll
index ca361703adcb..70a5def42228 100644
--- a/test/Transforms/BBVectorize/loop1.ll
+++ b/test/Transforms/BBVectorize/loop1.ll
@@ -12,10 +12,10 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds double* %in1, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
-  %arrayidx2 = getelementptr inbounds double* %in2, i64 %indvars.iv
-  %1 = load double* %arrayidx2, align 8
+  %arrayidx = getelementptr inbounds double, double* %in1, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %in2, i64 %indvars.iv
+  %1 = load double, double* %arrayidx2, align 8
   %mul = fmul double %0, %0
   %mul3 = fmul double %0, %1
   %add = fadd double %mul, %mul3
@@ -28,17 +28,17 @@ for.body:                                         ; preds = %for.body, %entry
   %add10 = fadd double %add9, %0
   %mul11 = fmul double %mul8, %add10
   %add12 = fadd double %add7, %mul11
-  %arrayidx14 = getelementptr inbounds double* %out, i64 %indvars.iv
+  %arrayidx14 = getelementptr inbounds double, double* %out, i64 %indvars.iv
   store double %add12, double* %arrayidx14, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
   %exitcond = icmp eq i32 %lftr.wideiv, 10
   br i1 %exitcond, label %for.end, label %for.body
 ; CHECK: %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-; CHECK: %arrayidx = getelementptr inbounds double* %in1, i64 %indvars.iv
-; CHECK: %0 = load double* %arrayidx, align 8
-; CHECK: %arrayidx2 = getelementptr inbounds double* %in2, i64 %indvars.iv
-; CHECK: %1 = load double* %arrayidx2, align 8
+; CHECK: %arrayidx = getelementptr inbounds double, double* %in1, i64 %indvars.iv
+; CHECK: %0 = load double, double* %arrayidx, align 8
+; CHECK: %arrayidx2 = getelementptr inbounds double, double* %in2, i64 %indvars.iv
+; CHECK: %1 = load double, double* %arrayidx2, align 8
 ; CHECK: %mul = fmul double %0, %0
 ; CHECK: %mul3 = fmul double %0, %1
 ; CHECK: %add = fadd double %mul, %mul3
@@ -55,20 +55,20 @@ for.body:                                         ; preds = %for.body, %entry
 ; CHECK: %mul6.v.r2 = extractelement <2 x double> %mul6, i32 1
 ; CHECK: %add7 = fadd double %add, %mul6.v.r1
 ; CHECK: %add12 = fadd double %add7, %mul6.v.r2
-; CHECK: %arrayidx14 = getelementptr inbounds double* %out, i64 %indvars.iv
+; CHECK: %arrayidx14 = getelementptr inbounds double, double* %out, i64 %indvars.iv
 ; CHECK: store double %add12, double* %arrayidx14, align 8
 ; CHECK: %indvars.iv.next = add i64 %indvars.iv, 1
 ; CHECK: %lftr.wideiv = trunc i64 %indvars.iv.next to i32
 ; CHECK: %exitcond = icmp eq i32 %lftr.wideiv, 10
 ; CHECK: br i1 %exitcond, label %for.end, label %for.body
 ; CHECK-UNRL: %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next.1, %for.body ]
-; CHECK-UNRL: %arrayidx = getelementptr inbounds double* %in1, i64 %indvars.iv
+; CHECK-UNRL: %arrayidx = getelementptr inbounds double, double* %in1, i64 %indvars.iv
 ; CHECK-UNRL: %0 = bitcast double* %arrayidx to <2 x double>*
-; CHECK-UNRL: %arrayidx2 = getelementptr inbounds double* %in2, i64 %indvars.iv
+; CHECK-UNRL: %arrayidx2 = getelementptr inbounds double, double* %in2, i64 %indvars.iv
 ; CHECK-UNRL: %1 = bitcast double* %arrayidx2 to <2 x double>*
-; CHECK-UNRL: %arrayidx14 = getelementptr inbounds double* %out, i64 %indvars.iv
-; CHECK-UNRL: %2 = load <2 x double>* %0, align 8
-; CHECK-UNRL: %3 = load <2 x double>* %1, align 8
+; CHECK-UNRL: %arrayidx14 = getelementptr inbounds double, double* %out, i64 %indvars.iv
+; CHECK-UNRL: %2 = load <2 x double>, <2 x double>* %0, align 8
+; CHECK-UNRL: %3 = load <2 x double>, <2 x double>* %1, align 8
 ; CHECK-UNRL: %mul = fmul <2 x double> %2, %2
 ; CHECK-UNRL: %mul3 = fmul <2 x double> %2, %3
 ; CHECK-UNRL: %add = fadd <2 x double> %mul, %mul3
diff --git a/test/Transforms/BBVectorize/mem-op-depth.ll b/test/Transforms/BBVectorize/mem-op-depth.ll
index c31d4521183f..732043b7f8ec 100644
--- a/test/Transforms/BBVectorize/mem-op-depth.ll
+++ b/test/Transforms/BBVectorize/mem-op-depth.ll
@@ -7,15 +7,15 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @test1() nounwind {
 ; CHECK-LABEL: @test1(
-  %V1 = load float* getelementptr inbounds ([1024 x float]* @A, i64 0, i64 0), align 16
-  %V2 = load float* getelementptr inbounds ([1024 x float]* @A, i64 0, i64 1), align 4
-  %V3= load float* getelementptr inbounds ([1024 x float]* @A, i64 0, i64 2), align 8
-  %V4 = load float* getelementptr inbounds ([1024 x float]* @A, i64 0, i64 3), align 4
-; CHECK:   %V1 = load <4 x float>* bitcast ([1024 x float]* @A to <4 x float>*), align 16
-  store float %V1, float* getelementptr inbounds ([1024 x float]* @B, i64 0, i64 0), align 16
-  store float %V2, float* getelementptr inbounds ([1024 x float]* @B, i64 0, i64 1), align 4
-  store float %V3, float* getelementptr inbounds ([1024 x float]* @B, i64 0, i64 2), align 8
-  store float %V4, float* getelementptr inbounds ([1024 x float]* @B, i64 0, i64 3), align 4
+  %V1 = load float, float* getelementptr inbounds ([1024 x float], [1024 x float]* @A, i64 0, i64 0), align 16
+  %V2 = load float, float* getelementptr inbounds ([1024 x float], [1024 x float]* @A, i64 0, i64 1), align 4
+  %V3= load float, float* getelementptr inbounds ([1024 x float], [1024 x float]* @A, i64 0, i64 2), align 8
+  %V4 = load float, float* getelementptr inbounds ([1024 x float], [1024 x float]* @A, i64 0, i64 3), align 4
+; CHECK:   %V1 = load <4 x float>, <4 x float>* bitcast ([1024 x float]* @A to <4 x float>*), align 16
+  store float %V1, float* getelementptr inbounds ([1024 x float], [1024 x float]* @B, i64 0, i64 0), align 16
+  store float %V2, float* getelementptr inbounds ([1024 x float], [1024 x float]* @B, i64 0, i64 1), align 4
+  store float %V3, float* getelementptr inbounds ([1024 x float], [1024 x float]* @B, i64 0, i64 2), align 8
+  store float %V4, float* getelementptr inbounds ([1024 x float], [1024 x float]* @B, i64 0, i64 3), align 4
 ; CHECK-NEXT: store <4 x float> %V1, <4 x float>* bitcast ([1024 x float]* @B to <4 x float>*), align 16
   ret i32 0
 ; CHECK-NEXT: ret i32 0
diff --git a/test/Transforms/BBVectorize/metadata.ll b/test/Transforms/BBVectorize/metadata.ll
index 874fbb87967c..f5580a888616 100644
--- a/test/Transforms/BBVectorize/metadata.ll
+++ b/test/Transforms/BBVectorize/metadata.ll
@@ -4,16 +4,16 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; Simple 3-pair chain with loads and stores (with fpmath)
 define void @test1(double* %a, double* %b, double* %c) nounwind uwtable readonly {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1, !fpmath !2
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4, !fpmath !3
   store double %mul, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   ret void
 ; CHECK-LABEL: @test1(
@@ -24,16 +24,16 @@ entry:
 ; Simple 3-pair chain with loads and stores (ints with range)
 define void @test2(i64* %a, i64* %b, i64* %c) nounwind uwtable readonly {
 entry:
-  %i0 = load i64* %a, align 8, !range !0
-  %i1 = load i64* %b, align 8
+  %i0 = load i64, i64* %a, align 8, !range !0
+  %i1 = load i64, i64* %b, align 8
   %mul = mul i64 %i0, %i1
-  %arrayidx3 = getelementptr inbounds i64* %a, i64 1
-  %i3 = load i64* %arrayidx3, align 8, !range !1
-  %arrayidx4 = getelementptr inbounds i64* %b, i64 1
-  %i4 = load i64* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds i64, i64* %a, i64 1
+  %i3 = load i64, i64* %arrayidx3, align 8, !range !1
+  %arrayidx4 = getelementptr inbounds i64, i64* %b, i64 1
+  %i4 = load i64, i64* %arrayidx4, align 8
   %mul5 = mul i64 %i3, %i4
   store i64 %mul, i64* %c, align 8
-  %arrayidx5 = getelementptr inbounds i64* %c, i64 1
+  %arrayidx5 = getelementptr inbounds i64, i64* %c, i64 1
   store i64 %mul5, i64* %arrayidx5, align 8
   ret void
 ; CHECK-LABEL: @test2(
diff --git a/test/Transforms/BBVectorize/no-ldstr-conn.ll b/test/Transforms/BBVectorize/no-ldstr-conn.ll
index bcc5ce7531bd..a84cd6585602 100644
--- a/test/Transforms/BBVectorize/no-ldstr-conn.ll
+++ b/test/Transforms/BBVectorize/no-ldstr-conn.ll
@@ -7,10 +7,10 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 define i64 @test2(i64 %a) nounwind uwtable readonly {
 entry:
   %a1 = inttoptr i64 %a to i64*
-  %a2 = getelementptr i64* %a1, i64 1
-  %a3 = getelementptr i64* %a1, i64 2
-  %v2 = load i64* %a2, align 8
-  %v3 = load i64* %a3, align 8
+  %a2 = getelementptr i64, i64* %a1, i64 1
+  %a3 = getelementptr i64, i64* %a1, i64 2
+  %v2 = load i64, i64* %a2, align 8
+  %v3 = load i64, i64* %a3, align 8
   %v2a = add i64 %v2, 5
   %v3a = add i64 %v3, 7
   store i64 %v2a, i64* %a2, align 8
@@ -18,6 +18,6 @@ entry:
   %r = add i64 %v2, %v3
   ret i64 %r
 ; CHECK-LABEL: @test2(
-; CHECK-NOT: getelementptr <2 x i64*>
+; CHECK-NOT: getelementptr i64, <2 x i64*>
 }
 
diff --git a/test/Transforms/BBVectorize/simple-ldstr-ptrs.ll b/test/Transforms/BBVectorize/simple-ldstr-ptrs.ll
index 4d2298c1a11d..fcc0236bae9d 100644
--- a/test/Transforms/BBVectorize/simple-ldstr-ptrs.ll
+++ b/test/Transforms/BBVectorize/simple-ldstr-ptrs.ll
@@ -8,37 +8,37 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; Simple 3-pair chain also with loads and stores (using ptrs and gep)
 define double @test1(i64* %a, i64* %b, i64* %c) nounwind uwtable readonly {
 entry:
-  %i0 = load i64* %a, align 8
-  %i1 = load i64* %b, align 8
+  %i0 = load i64, i64* %a, align 8
+  %i1 = load i64, i64* %b, align 8
   %mul = mul i64 %i0, %i1
-  %arrayidx3 = getelementptr inbounds i64* %a, i64 1
-  %i3 = load i64* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds i64* %b, i64 1
-  %i4 = load i64* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds i64, i64* %a, i64 1
+  %i3 = load i64, i64* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds i64, i64* %b, i64 1
+  %i4 = load i64, i64* %arrayidx4, align 8
   %mul5 = mul i64 %i3, %i4
   %ptr = inttoptr i64 %mul to double*
   %ptr5 = inttoptr i64 %mul5 to double*
-  %aptr = getelementptr inbounds double* %ptr, i64 2
-  %aptr5 = getelementptr inbounds double* %ptr5, i64 3
-  %av = load double* %aptr, align 16
-  %av5 = load double* %aptr5, align 16
+  %aptr = getelementptr inbounds double, double* %ptr, i64 2
+  %aptr5 = getelementptr inbounds double, double* %ptr5, i64 3
+  %av = load double, double* %aptr, align 16
+  %av5 = load double, double* %aptr5, align 16
   %r = fmul double %av, %av5
   store i64 %mul, i64* %c, align 8
-  %arrayidx5 = getelementptr inbounds i64* %c, i64 1
+  %arrayidx5 = getelementptr inbounds i64, i64* %c, i64 1
   store i64 %mul5, i64* %arrayidx5, align 8
   ret double %r
 ; CHECK-LABEL: @test1(
 ; CHECK: %i0.v.i0 = bitcast i64* %a to <2 x i64>*
 ; CHECK: %i1.v.i0 = bitcast i64* %b to <2 x i64>*
-; CHECK: %i0 = load <2 x i64>* %i0.v.i0, align 8
-; CHECK: %i1 = load <2 x i64>* %i1.v.i0, align 8
+; CHECK: %i0 = load <2 x i64>, <2 x i64>* %i0.v.i0, align 8
+; CHECK: %i1 = load <2 x i64>, <2 x i64>* %i1.v.i0, align 8
 ; CHECK: %mul = mul <2 x i64> %i0, %i1
 ; CHECK: %ptr = inttoptr <2 x i64> %mul to <2 x double*>
-; CHECK: %aptr = getelementptr inbounds <2 x double*> %ptr, <2 x i64> <i64 2, i64 3>
+; CHECK: %aptr = getelementptr inbounds double, <2 x double*> %ptr, <2 x i64> <i64 2, i64 3>
 ; CHECK: %aptr.v.r1 = extractelement <2 x double*> %aptr, i32 0
 ; CHECK: %aptr.v.r2 = extractelement <2 x double*> %aptr, i32 1
-; CHECK: %av = load double* %aptr.v.r1, align 16
-; CHECK: %av5 = load double* %aptr.v.r2, align 16
+; CHECK: %av = load double, double* %aptr.v.r1, align 16
+; CHECK: %av5 = load double, double* %aptr.v.r2, align 16
 ; CHECK: %r = fmul double %av, %av5
 ; CHECK: %0 = bitcast i64* %c to <2 x i64>*
 ; CHECK: store <2 x i64> %mul, <2 x i64>* %0, align 8
@@ -50,31 +50,31 @@ entry:
 ; Simple 3-pair chain with loads and stores (using ptrs and gep)
 define void @test2(i64** %a, i64** %b, i64** %c) nounwind uwtable readonly {
 entry:
-  %i0 = load i64** %a, align 8
-  %i1 = load i64** %b, align 8
-  %arrayidx3 = getelementptr inbounds i64** %a, i64 1
-  %i3 = load i64** %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds i64** %b, i64 1
-  %i4 = load i64** %arrayidx4, align 8
-  %o1 = load i64* %i1, align 8
-  %o4 = load i64* %i4, align 8
-  %ptr0 = getelementptr inbounds i64* %i0, i64 %o1
-  %ptr3 = getelementptr inbounds i64* %i3, i64 %o4
+  %i0 = load i64*, i64** %a, align 8
+  %i1 = load i64*, i64** %b, align 8
+  %arrayidx3 = getelementptr inbounds i64*, i64** %a, i64 1
+  %i3 = load i64*, i64** %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds i64*, i64** %b, i64 1
+  %i4 = load i64*, i64** %arrayidx4, align 8
+  %o1 = load i64, i64* %i1, align 8
+  %o4 = load i64, i64* %i4, align 8
+  %ptr0 = getelementptr inbounds i64, i64* %i0, i64 %o1
+  %ptr3 = getelementptr inbounds i64, i64* %i3, i64 %o4
   store i64* %ptr0, i64** %c, align 8
-  %arrayidx5 = getelementptr inbounds i64** %c, i64 1
+  %arrayidx5 = getelementptr inbounds i64*, i64** %c, i64 1
   store i64* %ptr3, i64** %arrayidx5, align 8
   ret void
 ; CHECK-LABEL: @test2(
 ; CHECK: %i0.v.i0 = bitcast i64** %a to <2 x i64*>*
-; CHECK: %i1 = load i64** %b, align 8
-; CHECK: %i0 = load <2 x i64*>* %i0.v.i0, align 8
-; CHECK: %arrayidx4 = getelementptr inbounds i64** %b, i64 1
-; CHECK: %i4 = load i64** %arrayidx4, align 8
-; CHECK: %o1 = load i64* %i1, align 8
-; CHECK: %o4 = load i64* %i4, align 8
+; CHECK: %i1 = load i64*, i64** %b, align 8
+; CHECK: %i0 = load <2 x i64*>, <2 x i64*>* %i0.v.i0, align 8
+; CHECK: %arrayidx4 = getelementptr inbounds i64*, i64** %b, i64 1
+; CHECK: %i4 = load i64*, i64** %arrayidx4, align 8
+; CHECK: %o1 = load i64, i64* %i1, align 8
+; CHECK: %o4 = load i64, i64* %i4, align 8
 ; CHECK: %ptr0.v.i1.1 = insertelement <2 x i64> undef, i64 %o1, i32 0
 ; CHECK: %ptr0.v.i1.2 = insertelement <2 x i64> %ptr0.v.i1.1, i64 %o4, i32 1
-; CHECK: %ptr0 = getelementptr inbounds <2 x i64*> %i0, <2 x i64> %ptr0.v.i1.2
+; CHECK: %ptr0 = getelementptr inbounds i64, <2 x i64*> %i0, <2 x i64> %ptr0.v.i1.2
 ; CHECK: %0 = bitcast i64** %c to <2 x i64*>*
 ; CHECK: store <2 x i64*> %ptr0, <2 x i64*>* %0, align 8
 ; CHECK: ret void
@@ -86,42 +86,42 @@ entry:
 ; using pointer vectors.
 define void @test3(<2 x i64*>* %a, <2 x i64*>* %b, <2 x i64*>* %c) nounwind uwtable readonly {
 entry:
-  %i0 = load <2 x i64*>* %a, align 8
-  %i1 = load <2 x i64*>* %b, align 8
-  %arrayidx3 = getelementptr inbounds <2 x i64*>* %a, i64 1
-  %i3 = load <2 x i64*>* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds <2 x i64*>* %b, i64 1
-  %i4 = load <2 x i64*>* %arrayidx4, align 8
+  %i0 = load <2 x i64*>, <2 x i64*>* %a, align 8
+  %i1 = load <2 x i64*>, <2 x i64*>* %b, align 8
+  %arrayidx3 = getelementptr inbounds <2 x i64*>, <2 x i64*>* %a, i64 1
+  %i3 = load <2 x i64*>, <2 x i64*>* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds <2 x i64*>, <2 x i64*>* %b, i64 1
+  %i4 = load <2 x i64*>, <2 x i64*>* %arrayidx4, align 8
   %j1 = extractelement <2 x i64*> %i1, i32 0
   %j4 = extractelement <2 x i64*> %i4, i32 0
-  %o1 = load i64* %j1, align 8
-  %o4 = load i64* %j4, align 8
+  %o1 = load i64, i64* %j1, align 8
+  %o4 = load i64, i64* %j4, align 8
   %j0 = extractelement <2 x i64*> %i0, i32 0
   %j3 = extractelement <2 x i64*> %i3, i32 0
-  %ptr0 = getelementptr inbounds i64* %j0, i64 %o1
-  %ptr3 = getelementptr inbounds i64* %j3, i64 %o4
+  %ptr0 = getelementptr inbounds i64, i64* %j0, i64 %o1
+  %ptr3 = getelementptr inbounds i64, i64* %j3, i64 %o4
   %qtr0 = insertelement <2 x i64*> undef, i64* %ptr0, i32 0
   %rtr0 = insertelement <2 x i64*> %qtr0, i64* %ptr0, i32 1
   %qtr3 = insertelement <2 x i64*> undef, i64* %ptr3, i32 0
   %rtr3 = insertelement <2 x i64*> %qtr3, i64* %ptr3, i32 1
   store <2 x i64*> %rtr0, <2 x i64*>* %c, align 8
-  %arrayidx5 = getelementptr inbounds <2 x i64*>* %c, i64 1
+  %arrayidx5 = getelementptr inbounds <2 x i64*>, <2 x i64*>* %c, i64 1
   store <2 x i64*> %rtr3, <2 x i64*>* %arrayidx5, align 8
   ret void
 ; CHECK-LABEL: @test3(
 ; CHECK: %i0.v.i0 = bitcast <2 x i64*>* %a to <4 x i64*>*
-; CHECK: %i1 = load <2 x i64*>* %b, align 8
-; CHECK: %i0 = load <4 x i64*>* %i0.v.i0, align 8
-; CHECK: %arrayidx4 = getelementptr inbounds <2 x i64*>* %b, i64 1
-; CHECK: %i4 = load <2 x i64*>* %arrayidx4, align 8
+; CHECK: %i1 = load <2 x i64*>, <2 x i64*>* %b, align 8
+; CHECK: %i0 = load <4 x i64*>, <4 x i64*>* %i0.v.i0, align 8
+; CHECK: %arrayidx4 = getelementptr inbounds <2 x i64*>, <2 x i64*>* %b, i64 1
+; CHECK: %i4 = load <2 x i64*>, <2 x i64*>* %arrayidx4, align 8
 ; CHECK: %j1 = extractelement <2 x i64*> %i1, i32 0
 ; CHECK: %j4 = extractelement <2 x i64*> %i4, i32 0
-; CHECK: %o1 = load i64* %j1, align 8
-; CHECK: %o4 = load i64* %j4, align 8
+; CHECK: %o1 = load i64, i64* %j1, align 8
+; CHECK: %o4 = load i64, i64* %j4, align 8
 ; CHECK: %ptr0.v.i1.1 = insertelement <2 x i64> undef, i64 %o1, i32 0
 ; CHECK: %ptr0.v.i1.2 = insertelement <2 x i64> %ptr0.v.i1.1, i64 %o4, i32 1
 ; CHECK: %ptr0.v.i0 = shufflevector <4 x i64*> %i0, <4 x i64*> undef, <2 x i32> <i32 0, i32 2>
-; CHECK: %ptr0 = getelementptr inbounds <2 x i64*> %ptr0.v.i0, <2 x i64> %ptr0.v.i1.2
+; CHECK: %ptr0 = getelementptr inbounds i64, <2 x i64*> %ptr0.v.i0, <2 x i64> %ptr0.v.i1.2
 ; CHECK: %rtr0 = shufflevector <2 x i64*> %ptr0, <2 x i64*> undef, <2 x i32> zeroinitializer
 ; CHECK: %rtr3 = shufflevector <2 x i64*> %ptr0, <2 x i64*> undef, <2 x i32> <i32 1, i32 1>
 ; CHECK: %0 = bitcast <2 x i64*>* %c to <4 x i64*>*
diff --git a/test/Transforms/BBVectorize/simple-ldstr.ll b/test/Transforms/BBVectorize/simple-ldstr.ll
index 558f8b38d794..56c1a06b42ea 100644
--- a/test/Transforms/BBVectorize/simple-ldstr.ll
+++ b/test/Transforms/BBVectorize/simple-ldstr.ll
@@ -5,23 +5,23 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; Simple 3-pair chain with loads and stores
 define void @test1(double* %a, double* %b, double* %c) nounwind uwtable readonly {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   store double %mul, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   ret void
 ; CHECK-LABEL: @test1(
 ; CHECK: %i0.v.i0 = bitcast double* %a to <2 x double>*
 ; CHECK: %i1.v.i0 = bitcast double* %b to <2 x double>*
-; CHECK: %i0 = load <2 x double>* %i0.v.i0, align 8
-; CHECK: %i1 = load <2 x double>* %i1.v.i0, align 8
+; CHECK: %i0 = load <2 x double>, <2 x double>* %i0.v.i0, align 8
+; CHECK: %i1 = load <2 x double>, <2 x double>* %i1.v.i0, align 8
 ; CHECK: %mul = fmul <2 x double> %i0, %i1
 ; CHECK: %0 = bitcast double* %c to <2 x double>*
 ; CHECK: store <2 x double> %mul, <2 x double>* %0, align 8
@@ -33,28 +33,28 @@ entry:
 ; Simple chain with extending loads and stores
 define void @test2(float* %a, float* %b, double* %c) nounwind uwtable readonly {
 entry:
-  %i0f = load float* %a, align 4
+  %i0f = load float, float* %a, align 4
   %i0 = fpext float %i0f to double
-  %i1f = load float* %b, align 4
+  %i1f = load float, float* %b, align 4
   %i1 = fpext float %i1f to double
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds float* %a, i64 1
-  %i3f = load float* %arrayidx3, align 4
+  %arrayidx3 = getelementptr inbounds float, float* %a, i64 1
+  %i3f = load float, float* %arrayidx3, align 4
   %i3 = fpext float %i3f to double
-  %arrayidx4 = getelementptr inbounds float* %b, i64 1
-  %i4f = load float* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds float, float* %b, i64 1
+  %i4f = load float, float* %arrayidx4, align 4
   %i4 = fpext float %i4f to double
   %mul5 = fmul double %i3, %i4
   store double %mul, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   ret void
 ; CHECK-LABEL: @test2(
 ; CHECK: %i0f.v.i0 = bitcast float* %a to <2 x float>*
 ; CHECK: %i1f.v.i0 = bitcast float* %b to <2 x float>*
-; CHECK: %i0f = load <2 x float>* %i0f.v.i0, align 4
+; CHECK: %i0f = load <2 x float>, <2 x float>* %i0f.v.i0, align 4
 ; CHECK: %i0 = fpext <2 x float> %i0f to <2 x double>
-; CHECK: %i1f = load <2 x float>* %i1f.v.i0, align 4
+; CHECK: %i1f = load <2 x float>, <2 x float>* %i1f.v.i0, align 4
 ; CHECK: %i1 = fpext <2 x float> %i1f to <2 x double>
 ; CHECK: %mul = fmul <2 x double> %i0, %i1
 ; CHECK: %0 = bitcast double* %c to <2 x double>*
@@ -67,37 +67,37 @@ entry:
 ; Simple chain with loads and truncating stores
 define void @test3(double* %a, double* %b, float* %c) nounwind uwtable readonly {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
   %mulf = fptrunc double %mul to float
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   %mul5f = fptrunc double %mul5 to float
   store float %mulf, float* %c, align 8
-  %arrayidx5 = getelementptr inbounds float* %c, i64 1
+  %arrayidx5 = getelementptr inbounds float, float* %c, i64 1
   store float %mul5f, float* %arrayidx5, align 4
   ret void
 ; CHECK-LABEL: @test3(
 ; CHECK: %i0.v.i0 = bitcast double* %a to <2 x double>*
 ; CHECK: %i1.v.i0 = bitcast double* %b to <2 x double>*
-; CHECK: %i0 = load <2 x double>* %i0.v.i0, align 8
-; CHECK: %i1 = load <2 x double>* %i1.v.i0, align 8
+; CHECK: %i0 = load <2 x double>, <2 x double>* %i0.v.i0, align 8
+; CHECK: %i1 = load <2 x double>, <2 x double>* %i1.v.i0, align 8
 ; CHECK: %mul = fmul <2 x double> %i0, %i1
 ; CHECK: %mulf = fptrunc <2 x double> %mul to <2 x float>
 ; CHECK: %0 = bitcast float* %c to <2 x float>*
 ; CHECK: store <2 x float> %mulf, <2 x float>* %0, align 8
 ; CHECK: ret void
 ; CHECK-AO-LABEL: @test3(
-; CHECK-AO: %i0 = load double* %a, align 8
-; CHECK-AO: %i1 = load double* %b, align 8
-; CHECK-AO: %arrayidx3 = getelementptr inbounds double* %a, i64 1
-; CHECK-AO: %i3 = load double* %arrayidx3, align 8
-; CHECK-AO: %arrayidx4 = getelementptr inbounds double* %b, i64 1
-; CHECK-AO: %i4 = load double* %arrayidx4, align 8
+; CHECK-AO: %i0 = load double, double* %a, align 8
+; CHECK-AO: %i1 = load double, double* %b, align 8
+; CHECK-AO: %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+; CHECK-AO: %i3 = load double, double* %arrayidx3, align 8
+; CHECK-AO: %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+; CHECK-AO: %i4 = load double, double* %arrayidx4, align 8
 ; CHECK-AO: %mul.v.i1.1 = insertelement <2 x double> undef, double %i1, i32 0
 ; CHECK-AO: %mul.v.i1.2 = insertelement <2 x double> %mul.v.i1.1, double %i4, i32 1
 ; CHECK-AO: %mul.v.i0.1 = insertelement <2 x double> undef, double %i0, i32 0
@@ -119,16 +119,16 @@ if.then1:
   br label %if.then
 
 if.then:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   store double %mul, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   br label %if.end
 
@@ -143,23 +143,23 @@ if.end:
 ; Simple 3-pair chain with loads and stores
 define void @test5(double* %a, double* %b, double* %c) nounwind uwtable readonly {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   store double %mul, double* %c, align 4
   ret void
 ; CHECK-LABEL: @test5(
 ; CHECK: %i0.v.i0 = bitcast double* %a to <2 x double>*
 ; CHECK: %i1.v.i0 = bitcast double* %b to <2 x double>*
-; CHECK: %i0 = load <2 x double>* %i0.v.i0, align 8
-; CHECK: %i1 = load <2 x double>* %i1.v.i0, align 8
+; CHECK: %i0 = load <2 x double>, <2 x double>* %i0.v.i0, align 8
+; CHECK: %i1 = load <2 x double>, <2 x double>* %i1.v.i0, align 8
 ; CHECK: %mul = fmul <2 x double> %i0, %i1
 ; CHECK: %0 = bitcast double* %c to <2 x double>*
 ; CHECK: store <2 x double> %mul, <2 x double>* %0, align 4
diff --git a/test/Transforms/BBVectorize/simple3.ll b/test/Transforms/BBVectorize/simple3.ll
index 6edf7f07ac1d..da7f94149414 100644
--- a/test/Transforms/BBVectorize/simple3.ll
+++ b/test/Transforms/BBVectorize/simple3.ll
@@ -4,12 +4,12 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; Basic depth-3 chain
 define double @test1(double %A1, double %A2, double %A3, double %B1, double %B2, double %B3) {
 ; CHECK-LABEL: @test1(
-; CHECK: %X1.v.i1.11 = insertelement <3 x double> undef, double %B1, i32 0
-; CHECK: %X1.v.i1.22 = insertelement <3 x double> %X1.v.i1.11, double %B2, i32 1
-; CHECK: %X1.v.i1 = insertelement <3 x double> %X1.v.i1.22, double %B3, i32 2
-; CHECK: %X1.v.i0.13 = insertelement <3 x double> undef, double %A1, i32 0
-; CHECK: %X1.v.i0.24 = insertelement <3 x double> %X1.v.i0.13, double %A2, i32 1
-; CHECK: %X1.v.i0 = insertelement <3 x double> %X1.v.i0.24, double %A3, i32 2
+; CHECK: %X1.v.i1.1.1 = insertelement <3 x double> undef, double %B1, i32 0
+; CHECK: %X1.v.i1.2.2 = insertelement <3 x double> %X1.v.i1.1.1, double %B2, i32 1
+; CHECK: %X1.v.i1 = insertelement <3 x double> %X1.v.i1.2.2, double %B3, i32 2
+; CHECK: %X1.v.i0.1.3 = insertelement <3 x double> undef, double %A1, i32 0
+; CHECK: %X1.v.i0.2.4 = insertelement <3 x double> %X1.v.i0.1.3, double %A2, i32 1
+; CHECK: %X1.v.i0 = insertelement <3 x double> %X1.v.i0.2.4, double %A3, i32 2
 	%X1 = fsub double %A1, %B1
 	%X2 = fsub double %A2, %B2
 	%X3 = fsub double %A3, %B3
@@ -24,11 +24,11 @@ define double @test1(double %A1, double %A2, double %A3, double %B1, double %B2,
 ; CHECK: %Z1 = fadd <3 x double> %Y1, %X1.v.i1
         %R1 = fmul double %Z1, %Z2
 	%R  = fmul double %R1, %Z3
-; CHECK: %Z1.v.r210 = extractelement <3 x double> %Z1, i32 2
+; CHECK: %Z1.v.r2.10 = extractelement <3 x double> %Z1, i32 2
 ; CHECK: %Z1.v.r1 = extractelement <3 x double> %Z1, i32 0
 ; CHECK: %Z1.v.r2 = extractelement <3 x double> %Z1, i32 1
 ; CHECK: %R1 = fmul double %Z1.v.r1, %Z1.v.r2
-; CHECK: %R = fmul double %R1, %Z1.v.r210
+; CHECK: %R = fmul double %R1, %Z1.v.r2.10
 	ret double %R
 ; CHECK: ret double %R
 }
diff --git a/test/Transforms/BDCE/basic.ll b/test/Transforms/BDCE/basic.ll
new file mode 100644
index 000000000000..6e748c69a16e
--- /dev/null
+++ b/test/Transforms/BDCE/basic.ll
@@ -0,0 +1,348 @@
+; RUN: opt -S -bdce -instsimplify < %s | FileCheck %s
+; RUN: opt -S -instsimplify < %s | FileCheck %s -check-prefix=CHECK-IO
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind readnone
+define signext i32 @bar(i32 signext %x) #0 {
+entry:
+  %call = tail call signext i32 @foo(i32 signext 5) #0
+  %and = and i32 %call, 4
+  %or = or i32 %and, %x
+  %call1 = tail call signext i32 @foo(i32 signext 3) #0
+  %and2 = and i32 %call1, 8
+  %or3 = or i32 %or, %and2
+  %call4 = tail call signext i32 @foo(i32 signext 2) #0
+  %and5 = and i32 %call4, 16
+  %or6 = or i32 %or3, %and5
+  %call7 = tail call signext i32 @foo(i32 signext 1) #0
+  %and8 = and i32 %call7, 32
+  %or9 = or i32 %or6, %and8
+  %call10 = tail call signext i32 @foo(i32 signext 0) #0
+  %and11 = and i32 %call10, 64
+  %or12 = or i32 %or9, %and11
+  %call13 = tail call signext i32 @foo(i32 signext 4) #0
+  %and14 = and i32 %call13, 128
+  %or15 = or i32 %or12, %and14
+  %shr = ashr i32 %or15, 4
+  ret i32 %shr
+
+; CHECK-LABEL: @bar
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 5)
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 3)
+; CHECK: tail call signext i32 @foo(i32 signext 2)
+; CHECK: tail call signext i32 @foo(i32 signext 1)
+; CHECK: tail call signext i32 @foo(i32 signext 0)
+; CHECK: tail call signext i32 @foo(i32 signext 4)
+; CHECK: ret i32
+
+; Check that instsimplify is not doing this all on its own.
+; CHECK-IO-LABEL: @bar
+; CHECK-IO: tail call signext i32 @foo(i32 signext 5)
+; CHECK-IO: tail call signext i32 @foo(i32 signext 3)
+; CHECK-IO: tail call signext i32 @foo(i32 signext 2)
+; CHECK-IO: tail call signext i32 @foo(i32 signext 1)
+; CHECK-IO: tail call signext i32 @foo(i32 signext 0)
+; CHECK-IO: tail call signext i32 @foo(i32 signext 4)
+; CHECK-IO: ret i32
+}
+
+; Function Attrs: nounwind readnone
+declare signext i32 @foo(i32 signext) #0
+
+; Function Attrs: nounwind readnone
+define signext i32 @far(i32 signext %x) #1 {
+entry:
+  %call = tail call signext i32 @goo(i32 signext 5) #1
+  %and = and i32 %call, 4
+  %or = or i32 %and, %x
+  %call1 = tail call signext i32 @goo(i32 signext 3) #1
+  %and2 = and i32 %call1, 8
+  %or3 = or i32 %or, %and2
+  %call4 = tail call signext i32 @goo(i32 signext 2) #1
+  %and5 = and i32 %call4, 16
+  %or6 = or i32 %or3, %and5
+  %call7 = tail call signext i32 @goo(i32 signext 1) #1
+  %and8 = and i32 %call7, 32
+  %or9 = or i32 %or6, %and8
+  %call10 = tail call signext i32 @goo(i32 signext 0) #1
+  %and11 = and i32 %call10, 64
+  %or12 = or i32 %or9, %and11
+  %call13 = tail call signext i32 @goo(i32 signext 4) #1
+  %and14 = and i32 %call13, 128
+  %or15 = or i32 %or12, %and14
+  %shr = ashr i32 %or15, 4
+  ret i32 %shr
+
+; CHECK-LABEL: @far
+; Calls to foo(5) and foo(3) are still there, but their results are not used.
+; CHECK: tail call signext i32 @goo(i32 signext 5)
+; CHECK-NEXT: tail call signext i32 @goo(i32 signext 3)
+; CHECK-NEXT: tail call signext i32 @goo(i32 signext 2)
+; CHECK: tail call signext i32 @goo(i32 signext 1)
+; CHECK: tail call signext i32 @goo(i32 signext 0)
+; CHECK: tail call signext i32 @goo(i32 signext 4)
+; CHECK: ret i32
+
+; Check that instsimplify is not doing this all on its own.
+; CHECK-IO-LABEL: @far
+; CHECK-IO: tail call signext i32 @goo(i32 signext 5)
+; CHECK-IO: tail call signext i32 @goo(i32 signext 3)
+; CHECK-IO: tail call signext i32 @goo(i32 signext 2)
+; CHECK-IO: tail call signext i32 @goo(i32 signext 1)
+; CHECK-IO: tail call signext i32 @goo(i32 signext 0)
+; CHECK-IO: tail call signext i32 @goo(i32 signext 4)
+; CHECK-IO: ret i32
+}
+
+declare signext i32 @goo(i32 signext) #1
+
+; Function Attrs: nounwind readnone
+define signext i32 @tar1(i32 signext %x) #0 {
+entry:
+  %call = tail call signext i32 @foo(i32 signext 5) #0
+  %and = and i32 %call, 33554432
+  %or = or i32 %and, %x
+  %call1 = tail call signext i32 @foo(i32 signext 3) #0
+  %and2 = and i32 %call1, 67108864
+  %or3 = or i32 %or, %and2
+  %call4 = tail call signext i32 @foo(i32 signext 2) #0
+  %and5 = and i32 %call4, 16
+  %or6 = or i32 %or3, %and5
+  %call7 = tail call signext i32 @foo(i32 signext 1) #0
+  %and8 = and i32 %call7, 32
+  %or9 = or i32 %or6, %and8
+  %call10 = tail call signext i32 @foo(i32 signext 0) #0
+  %and11 = and i32 %call10, 64
+  %or12 = or i32 %or9, %and11
+  %call13 = tail call signext i32 @foo(i32 signext 4) #0
+  %and14 = and i32 %call13, 128
+  %or15 = or i32 %or12, %and14
+  %bs = tail call i32 @llvm.bswap.i32(i32 %or15) #0
+  %shr = ashr i32 %bs, 4
+  ret i32 %shr
+
+; CHECK-LABEL: @tar1
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 5)
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 3)
+; CHECK: tail call signext i32 @foo(i32 signext 2)
+; CHECK: tail call signext i32 @foo(i32 signext 1)
+; CHECK: tail call signext i32 @foo(i32 signext 0)
+; CHECK: tail call signext i32 @foo(i32 signext 4)
+; CHECK: ret i32
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.bswap.i32(i32) #0
+
+; Function Attrs: nounwind readnone
+define signext i32 @tar2(i32 signext %x) #0 {
+entry:
+  %call = tail call signext i32 @foo(i32 signext 5) #0
+  %and = and i32 %call, 33554432
+  %or = or i32 %and, %x
+  %call1 = tail call signext i32 @foo(i32 signext 3) #0
+  %and2 = and i32 %call1, 67108864
+  %or3 = or i32 %or, %and2
+  %call4 = tail call signext i32 @foo(i32 signext 2) #0
+  %and5 = and i32 %call4, 16
+  %or6 = or i32 %or3, %and5
+  %call7 = tail call signext i32 @foo(i32 signext 1) #0
+  %and8 = and i32 %call7, 32
+  %or9 = or i32 %or6, %and8
+  %call10 = tail call signext i32 @foo(i32 signext 0) #0
+  %and11 = and i32 %call10, 64
+  %or12 = or i32 %or9, %and11
+  %call13 = tail call signext i32 @foo(i32 signext 4) #0
+  %and14 = and i32 %call13, 128
+  %or15 = or i32 %or12, %and14
+  %shl = shl i32 %or15, 10
+  ret i32 %shl
+
+; CHECK-LABEL: @tar2
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 5)
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 3)
+; CHECK: tail call signext i32 @foo(i32 signext 2)
+; CHECK: tail call signext i32 @foo(i32 signext 1)
+; CHECK: tail call signext i32 @foo(i32 signext 0)
+; CHECK: tail call signext i32 @foo(i32 signext 4)
+; CHECK: ret i32
+}
+
+; Function Attrs: nounwind readnone
+define signext i32 @tar3(i32 signext %x) #0 {
+entry:
+  %call = tail call signext i32 @foo(i32 signext 5) #0
+  %and = and i32 %call, 33554432
+  %or = or i32 %and, %x
+  %call1 = tail call signext i32 @foo(i32 signext 3) #0
+  %and2 = and i32 %call1, 67108864
+  %or3 = or i32 %or, %and2
+  %call4 = tail call signext i32 @foo(i32 signext 2) #0
+  %and5 = and i32 %call4, 16
+  %or6 = or i32 %or3, %and5
+  %call7 = tail call signext i32 @foo(i32 signext 1) #0
+  %and8 = and i32 %call7, 32
+  %or9 = or i32 %or6, %and8
+  %call10 = tail call signext i32 @foo(i32 signext 0) #0
+  %and11 = and i32 %call10, 64
+  %or12 = or i32 %or9, %and11
+  %call13 = tail call signext i32 @foo(i32 signext 4) #0
+  %and14 = and i32 %call13, 128
+  %or15 = or i32 %or12, %and14
+  %add = add i32 %or15, 5
+  %shl = shl i32 %add, 10
+  ret i32 %shl
+
+; CHECK-LABEL: @tar3
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 5)
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 3)
+; CHECK: tail call signext i32 @foo(i32 signext 2)
+; CHECK: tail call signext i32 @foo(i32 signext 1)
+; CHECK: tail call signext i32 @foo(i32 signext 0)
+; CHECK: tail call signext i32 @foo(i32 signext 4)
+; CHECK: ret i32
+}
+
+; Function Attrs: nounwind readnone
+define signext i32 @tar4(i32 signext %x) #0 {
+entry:
+  %call = tail call signext i32 @foo(i32 signext 5) #0
+  %and = and i32 %call, 33554432
+  %or = or i32 %and, %x
+  %call1 = tail call signext i32 @foo(i32 signext 3) #0
+  %and2 = and i32 %call1, 67108864
+  %or3 = or i32 %or, %and2
+  %call4 = tail call signext i32 @foo(i32 signext 2) #0
+  %and5 = and i32 %call4, 16
+  %or6 = or i32 %or3, %and5
+  %call7 = tail call signext i32 @foo(i32 signext 1) #0
+  %and8 = and i32 %call7, 32
+  %or9 = or i32 %or6, %and8
+  %call10 = tail call signext i32 @foo(i32 signext 0) #0
+  %and11 = and i32 %call10, 64
+  %or12 = or i32 %or9, %and11
+  %call13 = tail call signext i32 @foo(i32 signext 4) #0
+  %and14 = and i32 %call13, 128
+  %or15 = or i32 %or12, %and14
+  %sub = sub i32 %or15, 5
+  %shl = shl i32 %sub, 10
+  ret i32 %shl
+
+; CHECK-LABEL: @tar4
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 5)
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 3)
+; CHECK: tail call signext i32 @foo(i32 signext 2)
+; CHECK: tail call signext i32 @foo(i32 signext 1)
+; CHECK: tail call signext i32 @foo(i32 signext 0)
+; CHECK: tail call signext i32 @foo(i32 signext 4)
+; CHECK: ret i32
+}
+
+; Function Attrs: nounwind readnone
+define signext i32 @tar5(i32 signext %x) #0 {
+entry:
+  %call = tail call signext i32 @foo(i32 signext 5) #0
+  %and = and i32 %call, 33554432
+  %or = or i32 %and, %x
+  %call1 = tail call signext i32 @foo(i32 signext 3) #0
+  %and2 = and i32 %call1, 67108864
+  %or3 = or i32 %or, %and2
+  %call4 = tail call signext i32 @foo(i32 signext 2) #0
+  %and5 = and i32 %call4, 16
+  %or6 = or i32 %or3, %and5
+  %call7 = tail call signext i32 @foo(i32 signext 1) #0
+  %and8 = and i32 %call7, 32
+  %or9 = or i32 %or6, %and8
+  %call10 = tail call signext i32 @foo(i32 signext 0) #0
+  %and11 = and i32 %call10, 64
+  %or12 = or i32 %or9, %and11
+  %call13 = tail call signext i32 @foo(i32 signext 4) #0
+  %and14 = and i32 %call13, 128
+  %or15 = or i32 %or12, %and14
+  %xor = xor i32 %or15, 5
+  %shl = shl i32 %xor, 10
+  ret i32 %shl
+
+; CHECK-LABEL: @tar5
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 5)
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 3)
+; CHECK: tail call signext i32 @foo(i32 signext 2)
+; CHECK: tail call signext i32 @foo(i32 signext 1)
+; CHECK: tail call signext i32 @foo(i32 signext 0)
+; CHECK: tail call signext i32 @foo(i32 signext 4)
+; CHECK: ret i32
+}
+
+; Function Attrs: nounwind readnone
+define signext i32 @tar7(i32 signext %x, i1 %b) #0 {
+entry:
+  %call = tail call signext i32 @foo(i32 signext 5) #0
+  %and = and i32 %call, 33554432
+  %or = or i32 %and, %x
+  %call1 = tail call signext i32 @foo(i32 signext 3) #0
+  %and2 = and i32 %call1, 67108864
+  %or3 = or i32 %or, %and2
+  %call4 = tail call signext i32 @foo(i32 signext 2) #0
+  %and5 = and i32 %call4, 16
+  %or6 = or i32 %or3, %and5
+  %call7 = tail call signext i32 @foo(i32 signext 1) #0
+  %and8 = and i32 %call7, 32
+  %or9 = or i32 %or6, %and8
+  %call10 = tail call signext i32 @foo(i32 signext 0) #0
+  %and11 = and i32 %call10, 64
+  %or12 = or i32 %or9, %and11
+  %call13 = tail call signext i32 @foo(i32 signext 4) #0
+  %and14 = and i32 %call13, 128
+  %or15 = or i32 %or12, %and14
+  %v = select i1 %b, i32 %or15, i32 5
+  %shl = shl i32 %v, 10
+  ret i32 %shl
+
+; CHECK-LABEL: @tar7
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 5)
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 3)
+; CHECK: tail call signext i32 @foo(i32 signext 2)
+; CHECK: tail call signext i32 @foo(i32 signext 1)
+; CHECK: tail call signext i32 @foo(i32 signext 0)
+; CHECK: tail call signext i32 @foo(i32 signext 4)
+; CHECK: ret i32
+}
+
+; Function Attrs: nounwind readnone
+define signext i16 @tar8(i32 signext %x) #0 {
+entry:
+  %call = tail call signext i32 @foo(i32 signext 5) #0
+  %and = and i32 %call, 33554432
+  %or = or i32 %and, %x
+  %call1 = tail call signext i32 @foo(i32 signext 3) #0
+  %and2 = and i32 %call1, 67108864
+  %or3 = or i32 %or, %and2
+  %call4 = tail call signext i32 @foo(i32 signext 2) #0
+  %and5 = and i32 %call4, 16
+  %or6 = or i32 %or3, %and5
+  %call7 = tail call signext i32 @foo(i32 signext 1) #0
+  %and8 = and i32 %call7, 32
+  %or9 = or i32 %or6, %and8
+  %call10 = tail call signext i32 @foo(i32 signext 0) #0
+  %and11 = and i32 %call10, 64
+  %or12 = or i32 %or9, %and11
+  %call13 = tail call signext i32 @foo(i32 signext 4) #0
+  %and14 = and i32 %call13, 128
+  %or15 = or i32 %or12, %and14
+  %tr = trunc i32 %or15 to i16
+  ret i16 %tr
+
+; CHECK-LABEL: @tar8
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 5)
+; CHECK-NOT: tail call signext i32 @foo(i32 signext 3)
+; CHECK: tail call signext i32 @foo(i32 signext 2)
+; CHECK: tail call signext i32 @foo(i32 signext 1)
+; CHECK: tail call signext i32 @foo(i32 signext 0)
+; CHECK: tail call signext i32 @foo(i32 signext 4)
+; CHECK: ret i16
+}
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }
+
diff --git a/test/Transforms/BDCE/dce-pure.ll b/test/Transforms/BDCE/dce-pure.ll
new file mode 100644
index 000000000000..6a432fcc42d7
--- /dev/null
+++ b/test/Transforms/BDCE/dce-pure.ll
@@ -0,0 +1,33 @@
+; RUN: opt -bdce -S < %s | FileCheck %s
+
+declare i32 @strlen(i8*) readonly nounwind
+
+define void @test1() {
+  call i32 @strlen( i8* null )
+  ret void
+
+; CHECK-LABEL: @test1
+; CHECK-NOT: call
+; CHECK: ret void
+}
+
+define i32 @test2() {
+  ; invoke of pure function should not be deleted!
+  invoke i32 @strlen( i8* null ) readnone
+                  to label %Cont unwind label %Other
+
+Cont:           ; preds = %0
+  ret i32 0
+
+Other:          ; preds = %0
+   %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
+            cleanup
+  ret i32 1
+
+; CHECK-LABEL: @test2
+; CHECK: invoke
+; CHECK: ret i32 1
+}
+
+declare i32 @__gxx_personality_v0(...)
+
diff --git a/test/Transforms/BDCE/order.ll b/test/Transforms/BDCE/order.ll
new file mode 100644
index 000000000000..301f4476ab5b
--- /dev/null
+++ b/test/Transforms/BDCE/order.ll
@@ -0,0 +1,37 @@
+; RUN: opt -bdce -S < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+declare i32 @__gxx_personality_v0(...)
+
+define fastcc void @_ZN11__sanitizerL12TestRegistryEPNS_14ThreadRegistryEb() #0 {
+entry:
+  br i1 undef, label %if.else, label %entry.if.end_crit_edge
+
+if.else:
+  ret void
+
+invoke.cont70:
+  store i32 %call71, i32* undef, align 4
+  br label %if.else
+
+; CHECK-LABEL: @_ZN11__sanitizerL12TestRegistryEPNS_14ThreadRegistryEb
+; CHECK: store i32 %call71
+
+lpad65.loopexit.split-lp.loopexit.split-lp:
+  br label %if.else
+
+lpad65.loopexit.split-lp.loopexit.split-lp.loopexit:
+  %lpad.loopexit1121 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  br label %lpad65.loopexit.split-lp.loopexit.split-lp
+
+entry.if.end_crit_edge:
+  %call71 = invoke i32 @_ZN11__sanitizer14ThreadRegistry12CreateThreadEmbjPv()
+          to label %invoke.cont70 unwind label %lpad65.loopexit.split-lp.loopexit.split-lp.loopexit
+}
+
+declare i32 @_ZN11__sanitizer14ThreadRegistry12CreateThreadEmbjPv()
+
+attributes #0 = { uwtable }
+
diff --git a/test/Transforms/CodeExtractor/2004-03-14-DominanceProblem.ll b/test/Transforms/CodeExtractor/2004-03-14-DominanceProblem.ll
index a6ee63ec45ae..2f9c0c7371c5 100644
--- a/test/Transforms/CodeExtractor/2004-03-14-DominanceProblem.ll
+++ b/test/Transforms/CodeExtractor/2004-03-14-DominanceProblem.ll
@@ -13,7 +13,7 @@ loopentry.1:            ; preds = %no_exit.1, %loopentry.1.preheader
         br i1 false, label %no_exit.1, label %loopexit.0.loopexit1
 
 no_exit.1:              ; preds = %loopentry.1
-        %tmp.53 = load i32* null                ; <i32> [#uses=1]
+        %tmp.53 = load i32, i32* null                ; <i32> [#uses=1]
         br i1 false, label %shortcirc_next.2, label %loopentry.1
 
 shortcirc_next.2:               ; preds = %no_exit.1
diff --git a/test/Transforms/CodeGenPrepare/R600/lit.local.cfg b/test/Transforms/CodeGenPrepare/R600/lit.local.cfg
new file mode 100644
index 000000000000..4086e8d681c3
--- /dev/null
+++ b/test/Transforms/CodeGenPrepare/R600/lit.local.cfg
@@ -0,0 +1,3 @@
+if not 'R600' in config.root.targets:
+    config.unsupported = True
+
diff --git a/test/Transforms/CodeGenPrepare/R600/no-sink-addrspacecast.ll b/test/Transforms/CodeGenPrepare/R600/no-sink-addrspacecast.ll
new file mode 100644
index 000000000000..f6f898fae21b
--- /dev/null
+++ b/test/Transforms/CodeGenPrepare/R600/no-sink-addrspacecast.ll
@@ -0,0 +1,49 @@
+; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown < %s | FileCheck -check-prefix=ASC -check-prefix=COMMON %s
+
+; COMMON-LABEL: @test_sink_ptrtoint_asc(
+; ASC: addrspacecast
+; ASC-NOT: ptrtoint
+; ASC-NOT: inttoptr
+
+define void @test_sink_ptrtoint_asc(float addrspace(1)* nocapture %arg, float addrspace(1)* nocapture readonly %arg1, float addrspace(3)* %arg2) #0 {
+bb:
+  %tmp = getelementptr inbounds float, float addrspace(3)* %arg2, i32 16
+  %tmp2 = tail call i32 @llvm.r600.read.tidig.x() #1
+  %tmp3 = sext i32 %tmp2 to i64
+  %tmp4 = getelementptr inbounds float, float addrspace(1)* %arg1, i64 %tmp3
+  %tmp5 = load float, float addrspace(1)* %tmp4, align 4
+  %tmp6 = addrspacecast float addrspace(3)* %tmp to float addrspace(4)*
+  %tmp7 = fcmp olt float %tmp5, 8.388608e+06
+  br i1 %tmp7, label %bb8, label %bb14
+
+bb8:                                              ; preds = %bb
+  %tmp9 = tail call float @llvm.fma.f32(float %tmp5, float 0x3FE45F3060000000, float 5.000000e-01) #1
+  %tmp10 = fmul float %tmp9, 0x3E74442D00000000
+  %tmp11 = fsub float -0.000000e+00, %tmp10
+  %tmp12 = tail call float @llvm.fma.f32(float %tmp9, float 0x3E74442D00000000, float %tmp11) #1
+  store float %tmp12, float addrspace(4)* %tmp6, align 4
+  %tmp13 = fsub float -0.000000e+00, %tmp12
+  br label %bb15
+
+bb14:                                             ; preds = %bb
+  store float 2.000000e+00, float addrspace(4)* %tmp6, align 4
+  br label %bb15
+
+bb15:                                             ; preds = %bb14, %bb8
+  %tmp16 = phi float [ 0.000000e+00, %bb14 ], [ %tmp13, %bb8 ]
+  %tmp17 = fsub float -0.000000e+00, %tmp16
+  %tmp18 = tail call float @llvm.fma.f32(float 1.000000e+00, float 0x3FF0AAAAA0000000, float %tmp17) #1
+  %tmp19 = fsub float 2.187500e-01, %tmp18
+  %tmp20 = fsub float 7.187500e-01, %tmp19
+  %tmp21 = fcmp ogt float %tmp5, 1.600000e+01
+  %tmp22 = select i1 %tmp21, float 0x7FF8000000000000, float %tmp20
+  %tmp23 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp3
+  store float %tmp22, float addrspace(1)* %tmp23, align 4
+  ret void
+}
+
+declare float @llvm.fma.f32(float, float, float) #1
+declare i32 @llvm.r600.read.tidig.x() #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
diff --git a/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll b/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll
index 430b99299d82..519e1ee2ce6f 100644
--- a/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll
+++ b/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll
@@ -9,7 +9,7 @@ define i128 @sink(i64* %mem1, i64* %mem2) {
 ; CHECK-LABEL: block1:
 ; CHECK-NEXT: load
 block1:
-  %l1 = load i64* %mem1
+  %l1 = load i64, i64* %mem1
   %s1 = sext i64 %l1 to i128
   br label %block2
 
@@ -18,7 +18,7 @@ block1:
 ; CHECK-NEXT: load
 ; CHECK-NEXT: sext
 block2:
-  %l2 = load i64* %mem2
+  %l2 = load i64, i64* %mem2
   %s2 = sext i64 %l2 to i128
   %res = mul i128 %s1, %s2
   ret i128 %res
@@ -31,7 +31,7 @@ define i64 @hoist(i32* %mem1, i32* %mem2) {
 ; CHECK-NEXT: load
 ; CHECK-NEXT: sext
 block1:
-  %l1 = load i32* %mem1
+  %l1 = load i32, i32* %mem1
   br label %block2
 
 ; CHECK-LABEL: block2:
@@ -39,7 +39,7 @@ block1:
 ; CHECK-NEXT: sext
 block2:
   %s1 = sext i32 %l1 to i64
-  %l2 = load i32* %mem2
+  %l2 = load i32, i32* %mem2
   %s2 = sext i32 %l2 to i64
   %res = mul i64 %s1, %s2
   ret i64 %res
diff --git a/test/Transforms/CodeGenPrepare/X86/memset_chk-simplify-nobuiltin.ll b/test/Transforms/CodeGenPrepare/X86/memset_chk-simplify-nobuiltin.ll
new file mode 100644
index 000000000000..1e12c0192a95
--- /dev/null
+++ b/test/Transforms/CodeGenPrepare/X86/memset_chk-simplify-nobuiltin.ll
@@ -0,0 +1,18 @@
+; RUN: opt -S -disable-simplify-libcalls -codegenprepare < %s | FileCheck %s
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+
+; This is a workaround for PR23093: when building with -mkernel/-fno-builtin,
+; we still generate fortified library calls.
+
+; Check that we ignore two things:
+; - attribute nobuiltin
+; - TLI::has (always returns false thanks to -disable-simplify-libcalls)
+
+; CHECK-NOT: _chk
+; CHECK: call void @llvm.memset.p0i8.i64(i8* %dst, i8 0, i64 %len, i32 1, i1 false)
+define void @test_nobuiltin(i8* %dst, i64 %len) {
+  call i8* @__memset_chk(i8* %dst, i32 0, i64 %len, i64 -1) nobuiltin
+  ret void
+}
+
+declare i8* @__memset_chk(i8*, i32, i64, i64)
diff --git a/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll b/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll
index a985c36707a9..c9f49b5d4f86 100644
--- a/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll
+++ b/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll
@@ -8,12 +8,12 @@ target triple = "x86_64-unknown-linux-gnu"
 ; CHECK: add i64 %sunkaddr, 40
 define void @load_cast_gep(i1 %cond, i64* %base) {
 entry:
-  %addr = getelementptr inbounds i64* %base, i64 5
+  %addr = getelementptr inbounds i64, i64* %base, i64 5
   %casted = addrspacecast i64* %addr to i32 addrspace(1)*
   br i1 %cond, label %if.then, label %fallthrough
 
 if.then:
-  %v = load i32 addrspace(1)* %casted, align 4
+  %v = load i32, i32 addrspace(1)* %casted, align 4
   br label %fallthrough
 
 fallthrough:
@@ -25,7 +25,7 @@ fallthrough:
 define void @store_gep_cast(i1 %cond, i64* %base) {
 entry:
   %casted = addrspacecast i64* %base to i32 addrspace(1)*
-  %addr = getelementptr inbounds i32 addrspace(1)* %casted, i64 5
+  %addr = getelementptr inbounds i32, i32 addrspace(1)* %casted, i64 5
   br i1 %cond, label %if.then, label %fallthrough
 
 if.then:
diff --git a/test/Transforms/CodeGenPrepare/overflow-intrinsics.ll b/test/Transforms/CodeGenPrepare/overflow-intrinsics.ll
new file mode 100644
index 000000000000..1e413191e064
--- /dev/null
+++ b/test/Transforms/CodeGenPrepare/overflow-intrinsics.ll
@@ -0,0 +1,74 @@
+; RUN: opt -codegenprepare -S < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-darwin10.0.0"
+
+; CHECK-LABEL: @test1(
+; CHECK: llvm.uadd.with.overflow
+; CHECK: ret i64
+define i64 @test1(i64 %a, i64 %b) nounwind ssp {
+entry:
+  %add = add i64 %b, %a
+  %cmp = icmp ult i64 %add, %a
+  %Q = select i1 %cmp, i64 %b, i64 42
+  ret i64 %Q
+}
+
+; CHECK-LABEL: @test2(
+; CHECK: llvm.uadd.with.overflow
+; CHECK: ret i64
+define i64 @test2(i64 %a, i64 %b) nounwind ssp {
+entry:
+  %add = add i64 %b, %a
+  %cmp = icmp ult i64 %add, %b
+  %Q = select i1 %cmp, i64 %b, i64 42
+  ret i64 %Q
+}
+
+; CHECK-LABEL: @test3(
+; CHECK: llvm.uadd.with.overflow
+; CHECK: ret i64
+define i64 @test3(i64 %a, i64 %b) nounwind ssp {
+entry:
+  %add = add i64 %b, %a
+  %cmp = icmp ugt i64 %b, %add
+  %Q = select i1 %cmp, i64 %b, i64 42
+  ret i64 %Q
+}
+
+; CHECK-LABEL: @test4(
+; CHECK: llvm.uadd.with.overflow
+; CHECK: extractvalue
+; CHECK: extractvalue
+; CHECK: select
+define i64 @test4(i64 %a, i64 %b, i1 %c) nounwind ssp {
+entry:
+  %add = add i64 %b, %a
+  %cmp = icmp ugt i64 %b, %add
+  br i1 %c, label %next, label %exit
+
+ next:
+  %Q = select i1 %cmp, i64 %b, i64 42
+  ret i64 %Q
+
+ exit:
+  ret i64 0
+}
+
+; CHECK-LABEL: @test5(
+; CHECK-NOT: llvm.uadd.with.overflow
+; CHECK: next
+define i64 @test5(i64 %a, i64 %b, i64* %ptr, i1 %c) nounwind ssp {
+entry:
+  %add = add i64 %b, %a
+  store i64 %add, i64* %ptr
+  %cmp = icmp ugt i64 %b, %add
+  br i1 %c, label %next, label %exit
+
+ next:
+  %Q = select i1 %cmp, i64 %b, i64 42
+  ret i64 %Q
+
+ exit:
+  ret i64 0
+}
diff --git a/test/Transforms/CodeGenPrepare/statepoint-relocate.ll b/test/Transforms/CodeGenPrepare/statepoint-relocate.ll
new file mode 100644
index 000000000000..b6898b373113
--- /dev/null
+++ b/test/Transforms/CodeGenPrepare/statepoint-relocate.ll
@@ -0,0 +1,88 @@
+; RUN: opt -codegenprepare -S < %s | FileCheck %s
+
+target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnu"
+
+declare zeroext i1 @return_i1()
+
+define i32 @test_sor_basic(i32* %base) gc "statepoint-example" {
+; CHECK: getelementptr i32, i32* %base, i32 15
+; CHECK: getelementptr i32, i32* %base-new, i32 15
+entry:
+       %ptr = getelementptr i32, i32* %base, i32 15
+       %tok = call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, i32* %base, i32* %ptr)
+       %base-new = call i32* @llvm.experimental.gc.relocate.p0i32(i32 %tok,  i32 7, i32 7)
+       %ptr-new = call i32* @llvm.experimental.gc.relocate.p0i32(i32 %tok, i32 7, i32 8)
+       %ret = load i32, i32* %ptr-new
+       ret i32 %ret
+}
+
+define i32 @test_sor_two_derived(i32* %base) gc "statepoint-example" {
+; CHECK: getelementptr i32, i32* %base, i32 15
+; CHECK: getelementptr i32, i32* %base, i32 12
+; CHECK: getelementptr i32, i32* %base-new, i32 12
+; CHECK: getelementptr i32, i32* %base-new, i32 15
+entry:
+       %ptr = getelementptr i32, i32* %base, i32 15
+       %ptr2 = getelementptr i32, i32* %base, i32 12
+       %tok = call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, i32* %base, i32* %ptr, i32* %ptr2)
+       %base-new = call i32* @llvm.experimental.gc.relocate.p0i32(i32 %tok,  i32 7, i32 7)
+       %ptr-new = call i32* @llvm.experimental.gc.relocate.p0i32(i32 %tok, i32 7, i32 8)
+       %ptr2-new = call i32* @llvm.experimental.gc.relocate.p0i32(i32 %tok, i32 7, i32 9)
+       %ret = load i32, i32* %ptr-new
+       ret i32 %ret
+}
+
+define i32 @test_sor_ooo(i32* %base) gc "statepoint-example" {
+; CHECK: getelementptr i32, i32* %base, i32 15
+; CHECK: getelementptr i32, i32* %base-new, i32 15
+entry:
+       %ptr = getelementptr i32, i32* %base, i32 15
+       %tok = call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, i32* %base, i32* %ptr)
+       %ptr-new = call i32* @llvm.experimental.gc.relocate.p0i32(i32 %tok, i32 7, i32 8)
+       %base-new = call i32* @llvm.experimental.gc.relocate.p0i32(i32 %tok,  i32 7, i32 7)
+       %ret = load i32, i32* %ptr-new
+       ret i32 %ret
+}
+
+define i32 @test_sor_gep_smallint([3 x i32]* %base) gc "statepoint-example" {
+; CHECK: getelementptr [3 x i32], [3 x i32]* %base, i32 0, i32 2
+; CHECK: getelementptr [3 x i32], [3 x i32]* %base-new, i32 0, i32 2
+entry:
+       %ptr = getelementptr [3 x i32], [3 x i32]* %base, i32 0, i32 2
+       %tok = call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, [3 x i32]* %base, i32* %ptr)
+       %base-new = call [3 x i32]* @llvm.experimental.gc.relocate.p0a3i32(i32 %tok,  i32 7, i32 7)
+       %ptr-new = call i32* @llvm.experimental.gc.relocate.p0i32(i32 %tok, i32 7, i32 8)
+       %ret = load i32, i32* %ptr-new
+       ret i32 %ret
+}
+
+define i32 @test_sor_gep_largeint([3 x i32]* %base) gc "statepoint-example" {
+; CHECK: getelementptr [3 x i32], [3 x i32]* %base, i32 0, i32 21
+; CHECK-NOT: getelementptr [3 x i32], [3 x i32]* %base-new, i32 0, i32 21
+entry:
+       %ptr = getelementptr [3 x i32], [3 x i32]* %base, i32 0, i32 21
+       %tok = call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, [3 x i32]* %base, i32* %ptr)
+       %base-new = call [3 x i32]* @llvm.experimental.gc.relocate.p0a3i32(i32 %tok,  i32 7, i32 7)
+       %ptr-new = call i32* @llvm.experimental.gc.relocate.p0i32(i32 %tok, i32 7, i32 8)
+       %ret = load i32, i32* %ptr-new
+       ret i32 %ret
+}
+
+define i32 @test_sor_noop(i32* %base) gc "statepoint-example" {
+; CHECK: getelementptr i32, i32* %base, i32 15
+; CHECK: call i32* @llvm.experimental.gc.relocate.p0i32(i32 %tok, i32 7, i32 8)
+; CHECK: call i32* @llvm.experimental.gc.relocate.p0i32(i32 %tok, i32 7, i32 9)
+entry:
+       %ptr = getelementptr i32, i32* %base, i32 15
+       %ptr2 = getelementptr i32, i32* %base, i32 12
+       %tok = call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, i32* %base, i32* %ptr, i32* %ptr2)
+       %ptr-new = call i32* @llvm.experimental.gc.relocate.p0i32(i32 %tok, i32 7, i32 8)
+       %ptr2-new = call i32* @llvm.experimental.gc.relocate.p0i32(i32 %tok, i32 7, i32 9)
+       %ret = load i32, i32* %ptr-new
+       ret i32 %ret
+}
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i32, ...)
+declare i32* @llvm.experimental.gc.relocate.p0i32(i32, i32, i32)
+declare [3 x i32]* @llvm.experimental.gc.relocate.p0a3i32(i32, i32, i32)
diff --git a/test/Transforms/ConstProp/2005-01-28-SetCCGEP.ll b/test/Transforms/ConstProp/2005-01-28-SetCCGEP.ll
index d68cb26da348..af7e8be4fcd8 100644
--- a/test/Transforms/ConstProp/2005-01-28-SetCCGEP.ll
+++ b/test/Transforms/ConstProp/2005-01-28-SetCCGEP.ll
@@ -4,7 +4,7 @@
 @b = external global [2 x {  }]         ; <[2 x {  }]*> [#uses=2]
 
 define i1 @f() {
-        %tmp.2 = icmp eq {  }* getelementptr ([2 x {  }]* @b, i32 0, i32 0), getelementptr ([2 x {  }]* @b, i32 0, i32 1)                ; <i1> [#uses=1]
+        %tmp.2 = icmp eq {  }* getelementptr ([2 x {  }], [2 x {  }]* @b, i32 0, i32 0), getelementptr ([2 x {  }], [2 x {  }]* @b, i32 0, i32 1)                ; <i1> [#uses=1]
         ret i1 %tmp.2
 }
 
diff --git a/test/Transforms/ConstProp/2009-09-01-GEP-Crash.ll b/test/Transforms/ConstProp/2009-09-01-GEP-Crash.ll
index fc7ff905ecb0..e93a2c066bd2 100644
--- a/test/Transforms/ConstProp/2009-09-01-GEP-Crash.ll
+++ b/test/Transforms/ConstProp/2009-09-01-GEP-Crash.ll
@@ -18,7 +18,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define void @init_hrtimers_cpu(i32 %cpu) nounwind noredzone section ".cpuinit.text" {
 entry:
-  %tmp3 = getelementptr %struct.hrtimer_cpu_base* bitcast (%1* @per_cpu__hrtimer_bases to %struct.hrtimer_cpu_base*), i32 0, i32 0 ; <%0*> [#uses=1]
+  %tmp3 = getelementptr %struct.hrtimer_cpu_base, %struct.hrtimer_cpu_base* bitcast (%1* @per_cpu__hrtimer_bases to %struct.hrtimer_cpu_base*), i32 0, i32 0 ; <%0*> [#uses=1]
   %tmp5 = bitcast %0* %tmp3 to i8*                ; <i8*> [#uses=0]
   unreachable
 }
diff --git a/test/Transforms/ConstProp/InsertElement.ll b/test/Transforms/ConstProp/InsertElement.ll
new file mode 100644
index 000000000000..011ad3f57f46
--- /dev/null
+++ b/test/Transforms/ConstProp/InsertElement.ll
@@ -0,0 +1,32 @@
+; RUN: opt < %s -constprop -S | FileCheck %s
+
+; CHECK-LABEL: @test1
+define i32 @test1() {
+  %A = bitcast i32 2139171423 to float
+  %B = insertelement <1 x float> undef, float %A, i32 0
+  %C = extractelement <1 x float> %B, i32 0
+  %D = bitcast float %C to i32
+  ret i32 %D
+; CHECK: ret i32 2139171423
+}
+
+; CHECK-LABEL: @insertelement
+define <4 x i64> @insertelement() {
+  %vec1 = insertelement <4 x i64> undef, i64 -1, i32 0
+  %vec2 = insertelement <4 x i64> %vec1, i64 -2, i32 1
+  %vec3 = insertelement <4 x i64> %vec2, i64 -3, i32 2
+  %vec4 = insertelement <4 x i64> %vec3, i64 -4, i32 3
+  ; CHECK: ret <4 x i64> <i64 -1, i64 -2, i64 -3, i64 -4>
+  ret <4 x i64> %vec4
+}
+
+; CHECK-LABEL: @insertelement_undef
+define <4 x i64> @insertelement_undef() {
+  %vec1 = insertelement <4 x i64> undef, i64 -1, i32 0
+  %vec2 = insertelement <4 x i64> %vec1, i64 -2, i32 1
+  %vec3 = insertelement <4 x i64> %vec2, i64 -3, i32 2
+  %vec4 = insertelement <4 x i64> %vec3, i64 -4, i32 3
+  %vec5 = insertelement <4 x i64> %vec3, i64 -5, i32 4
+  ; CHECK: ret <4 x i64> undef
+  ret <4 x i64> %vec5
+}
diff --git a/test/Transforms/ConstProp/convert-from-fp16.ll b/test/Transforms/ConstProp/convert-from-fp16.ll
new file mode 100644
index 000000000000..bb9032313179
--- /dev/null
+++ b/test/Transforms/ConstProp/convert-from-fp16.ll
@@ -0,0 +1,97 @@
+; RUN: opt -constprop -S < %s | FileCheck %s
+
+; Verify that we don't crash with an assertion failure when constant folding
+; a call to intrinsic 'convert.from.fp16' if the return type is not 'float'.
+
+define float @fold_from_fp16_to_fp32() {
+; CHECK-LABEL: @fold_from_fp16_to_fp32
+; CHECK: ret float 0.000000e+00
+entry:
+  %0 = call float @llvm.convert.from.fp16.f32(i16 0)
+  ret float %0
+}
+
+define double @fold_from_fp16_to_fp64() {
+; CHECK-LABEL: @fold_from_fp16_to_fp64
+; CHECK: ret double 0.000000e+00
+entry:
+  %0 = call double @llvm.convert.from.fp16.f64(i16 0)
+  ret double %0
+}
+
+define x86_fp80 @fold_from_fp16_to_fp80() {
+; CHECK-LABEL: @fold_from_fp16_to_fp80
+; CHECK: ret x86_fp80 0xK00000000000000000000
+entry:
+  %0 = call x86_fp80 @llvm.convert.from.fp16.f80(i16 0)
+  ret x86_fp80 %0
+}
+
+define fp128 @fold_from_fp16_to_fp128() {
+; CHECK-LABEL: @fold_from_fp16_to_fp128
+; CHECK: ret fp128 0xL00000000000000000000000000000000
+entry:
+  %0 = call fp128 @llvm.convert.from.fp16.f128(i16 0)
+  ret fp128 %0
+}
+
+define ppc_fp128 @fold_from_fp16_to_ppcfp128() {
+; CHECK-LABEL: @fold_from_fp16_to_ppcfp128
+; CHECK: ret ppc_fp128 0xM00000000000000000000000000000000
+entry:
+  %0 = call ppc_fp128 @llvm.convert.from.fp16.ppcf128(i16 0)
+  ret ppc_fp128 %0
+}
+
+define float @fold_from_fp16_to_fp32_b() {
+; CHECK-LABEL: @fold_from_fp16_to_fp32_b
+; CHECK: ret float 4.000000e+00
+entry:
+  %0 = call i16 @llvm.convert.to.fp16.f64(double 4.0)
+  %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
+  ret float %1
+}
+
+define double @fold_from_fp16_to_fp64_b() {
+; CHECK-LABEL: @fold_from_fp16_to_fp64_b
+; CHECK: ret double 4.000000e+00
+entry:
+  %0 = call i16 @llvm.convert.to.fp16.f64(double 4.0)
+  %1 = call double @llvm.convert.from.fp16.f64(i16 %0)
+  ret double %1
+}
+
+define x86_fp80 @fold_from_fp16_to_fp80_b() {
+; CHECK-LABEL: @fold_from_fp16_to_fp80_b
+; CHECK: ret x86_fp80 0xK40018000000000000000
+entry:
+  %0 = call i16 @llvm.convert.to.fp16.f64(double 4.0)
+  %1 = call x86_fp80 @llvm.convert.from.fp16.f80(i16 %0)
+  ret x86_fp80 %1
+}
+
+define fp128 @fold_from_fp16_to_fp128_b() {
+; CHECK-LABEL: @fold_from_fp16_to_fp128_b
+; CHECK: ret fp128 0xL00000000000000004001000000000000
+entry:
+  %0 = call i16 @llvm.convert.to.fp16.f64(double 4.0)
+  %1 = call fp128 @llvm.convert.from.fp16.f128(i16 %0)
+  ret fp128 %1
+}
+
+define ppc_fp128 @fold_from_fp16_to_ppcfp128_b() {
+; CHECK-LABEL: @fold_from_fp16_to_ppcfp128_b
+; CHECK: ret ppc_fp128 0xM40100000000000000000000000000000
+entry:
+  %0 = call i16 @llvm.convert.to.fp16.f64(double 4.0)
+  %1 = call ppc_fp128 @llvm.convert.from.fp16.ppcf128(i16 %0)
+  ret ppc_fp128 %1
+}
+
+
+declare i16 @llvm.convert.to.fp16.f64(double)
+declare float @llvm.convert.from.fp16.f32(i16)
+declare double @llvm.convert.from.fp16.f64(i16)
+declare x86_fp80 @llvm.convert.from.fp16.f80(i16)
+declare fp128 @llvm.convert.from.fp16.f128(i16)
+declare ppc_fp128 @llvm.convert.from.fp16.ppcf128(i16)
diff --git a/test/Transforms/ConstProp/div-zero.ll b/test/Transforms/ConstProp/div-zero.ll
index a2c59d3c002a..f4049a9615a8 100644
--- a/test/Transforms/ConstProp/div-zero.ll
+++ b/test/Transforms/ConstProp/div-zero.ll
@@ -5,7 +5,7 @@ declare void @ext()
 define i32 @foo(i32 %ptr) {
 entry:
         %zero = sub i32 %ptr, %ptr              ; <i32> [#uses=1]
-        %div_zero = sdiv i32 %zero, ptrtoint (i32* getelementptr (i32* null,
+        %div_zero = sdiv i32 %zero, ptrtoint (i32* getelementptr (i32, i32* null,
 i32 1) to i32)             ; <i32> [#uses=1]
         ret i32 %div_zero
 }
diff --git a/test/Transforms/ConstProp/insertvalue.ll b/test/Transforms/ConstProp/insertvalue.ll
index 0d288b3841df..dce2b728b93b 100644
--- a/test/Transforms/ConstProp/insertvalue.ll
+++ b/test/Transforms/ConstProp/insertvalue.ll
@@ -65,3 +65,12 @@ define [3 x %struct] @undef-test3() {
 ; CHECK: ret [3 x %struct] [%struct undef, %struct { i32 0, [4 x i8] undef }, %struct undef]
 }
 
+define i32 @test-float-Nan() {
+  %A = bitcast i32 2139171423 to float
+  %B = insertvalue [1 x float] undef, float %A, 0
+  %C = extractvalue [1 x float] %B, 0
+  %D = bitcast float %C to i32
+  ret i32 %D
+; CHECK: @test-float-Nan
+; CHECK: ret i32 2139171423
+}
diff --git a/test/Transforms/ConstProp/loads.ll b/test/Transforms/ConstProp/loads.ll
index 5a23dad87f3a..5426ad0f8adb 100644
--- a/test/Transforms/ConstProp/loads.ll
+++ b/test/Transforms/ConstProp/loads.ll
@@ -9,7 +9,7 @@
 
 ; Simple load
 define i32 @test1() {
-  %r = load i32* getelementptr ({{i32,i8},i32}* @g1, i32 0, i32 0, i32 0)
+  %r = load i32, i32* getelementptr ({{i32,i8},i32}, {{i32,i8},i32}* @g1, i32 0, i32 0, i32 0)
   ret i32 %r
 
 ; 0xDEADBEEF
@@ -24,7 +24,7 @@ define i32 @test1() {
 ; PR3152
 ; Load of first 16 bits of 32-bit value.
 define i16 @test2() {
-  %r = load i16* bitcast(i32* getelementptr ({{i32,i8},i32}* @g1, i32 0, i32 0, i32 0) to i16*)
+  %r = load i16, i16* bitcast(i32* getelementptr ({{i32,i8},i32}, {{i32,i8},i32}* @g1, i32 0, i32 0, i32 0) to i16*)
   ret i16 %r
 
 ; 0xBEEF
@@ -37,7 +37,7 @@ define i16 @test2() {
 }
 
 define i16 @test2_addrspacecast() {
-  %r = load i16 addrspace(1)* addrspacecast(i32* getelementptr ({{i32,i8},i32}* @g1, i32 0, i32 0, i32 0) to i16 addrspace(1)*)
+  %r = load i16, i16 addrspace(1)* addrspacecast(i32* getelementptr ({{i32,i8},i32}, {{i32,i8},i32}* @g1, i32 0, i32 0, i32 0) to i16 addrspace(1)*)
   ret i16 %r
 
 ; 0xBEEF
@@ -51,7 +51,7 @@ define i16 @test2_addrspacecast() {
 
 ; Load of second 16 bits of 32-bit value.
 define i16 @test3() {
-  %r = load i16* getelementptr(i16* bitcast(i32* getelementptr ({{i32,i8},i32}* @g1, i32 0, i32 0, i32 0) to i16*), i32 1)
+  %r = load i16, i16* getelementptr(i16, i16* bitcast(i32* getelementptr ({{i32,i8},i32}, {{i32,i8},i32}* @g1, i32 0, i32 0, i32 0) to i16*), i32 1)
   ret i16 %r
 
 ; 0xDEAD
@@ -65,7 +65,7 @@ define i16 @test3() {
 
 ; Load of 8 bit field + tail padding.
 define i16 @test4() {
-  %r = load i16* getelementptr(i16* bitcast(i32* getelementptr ({{i32,i8},i32}* @g1, i32 0, i32 0, i32 0) to i16*), i32 2)
+  %r = load i16, i16* getelementptr(i16, i16* bitcast(i32* getelementptr ({{i32,i8},i32}, {{i32,i8},i32}* @g1, i32 0, i32 0, i32 0) to i16*), i32 2)
   ret i16 %r
 
 ; 0x00BA
@@ -79,7 +79,7 @@ define i16 @test4() {
 
 ; Load of double bits.
 define i64 @test6() {
-  %r = load i64* bitcast(double* @g2 to i64*)
+  %r = load i64, i64* bitcast(double* @g2 to i64*)
   ret i64 %r
 
 ; 0x3FF_0000000000000
@@ -93,7 +93,7 @@ define i64 @test6() {
 
 ; Load of double bits.
 define i16 @test7() {
-  %r = load i16* bitcast(double* @g2 to i16*)
+  %r = load i16, i16* bitcast(double* @g2 to i16*)
   ret i16 %r
 
 ; 0x0000
@@ -107,7 +107,7 @@ define i16 @test7() {
 
 ; Double load.
 define double @test8() {
-  %r = load double* bitcast({{i32,i8},i32}* @g1 to double*)
+  %r = load double, double* bitcast({{i32,i8},i32}* @g1 to double*)
   ret double %r
 
 ; LE-LABEL: @test8(
@@ -120,7 +120,7 @@ define double @test8() {
 
 ; i128 load.
 define i128 @test9() {
-  %r = load i128* bitcast({i64, i64}* @g3 to i128*)
+  %r = load i128, i128* bitcast({i64, i64}* @g3 to i128*)
   ret i128 %r
 
 ; 0x00000000_06B1BFF8_00000000_0000007B
@@ -134,7 +134,7 @@ define i128 @test9() {
 
 ; vector load.
 define <2 x i64> @test10() {
-  %r = load <2 x i64>* bitcast({i64, i64}* @g3 to <2 x i64>*)
+  %r = load <2 x i64>, <2 x i64>* bitcast({i64, i64}* @g3 to <2 x i64>*)
   ret <2 x i64> %r
 
 ; LE-LABEL: @test10(
@@ -151,7 +151,7 @@ define <2 x i64> @test10() {
 
 define i16 @test11() nounwind {
 entry:
-  %a = load i16* bitcast ({ i8, i8 }* @g4 to i16*)
+  %a = load i16, i16* bitcast ({ i8, i8 }* @g4 to i16*)
   ret i16 %a
 
 ; 0x08A1
@@ -168,7 +168,7 @@ entry:
 @test12g = private constant [6 x i8] c"a\00b\00\00\00"
 
 define i16 @test12() {
-  %a = load i16* getelementptr inbounds ([3 x i16]* bitcast ([6 x i8]* @test12g to [3 x i16]*), i32 0, i64 1)
+  %a = load i16, i16* getelementptr inbounds ([3 x i16], [3 x i16]* bitcast ([6 x i8]* @test12g to [3 x i16]*), i32 0, i64 1)
   ret i16 %a
 
 ; 0x0062
@@ -184,7 +184,7 @@ define i16 @test12() {
 ; PR5978
 @g5 = constant i8 4
 define i1 @test13() {
-  %A = load i1* bitcast (i8* @g5 to i1*)
+  %A = load i1, i1* bitcast (i8* @g5 to i1*)
   ret i1 %A
 
 ; LE-LABEL: @test13(
@@ -197,7 +197,7 @@ define i1 @test13() {
 @g6 = constant [2 x i8*] [i8* inttoptr (i64 1 to i8*), i8* inttoptr (i64 2 to i8*)]
 define i64 @test14() nounwind {
 entry:
-  %tmp = load i64* bitcast ([2 x i8*]* @g6 to i64*)
+  %tmp = load i64, i64* bitcast ([2 x i8*]* @g6 to i64*)
   ret i64 %tmp
 
 ; LE-LABEL: @test14(
@@ -211,7 +211,7 @@ entry:
 @g6_as1 = constant [2 x i8 addrspace(1)*] [i8 addrspace(1)* inttoptr (i16 1 to i8 addrspace(1)*), i8 addrspace(1)* inttoptr (i16 2 to i8 addrspace(1)*)]
 define i16 @test14_as1() nounwind {
 entry:
-  %tmp = load i16* bitcast ([2 x i8 addrspace(1)*]* @g6_as1 to i16*)
+  %tmp = load i16, i16* bitcast ([2 x i8 addrspace(1)*]* @g6_as1 to i16*)
   ret i16 %tmp
 
 ; LE: @test14_as1
@@ -223,7 +223,7 @@ entry:
 
 define i64 @test15() nounwind {
 entry:
-  %tmp = load i64* bitcast (i8** getelementptr inbounds ([2 x i8*]* @g6, i32 0, i64 1) to i64*)
+  %tmp = load i64, i64* bitcast (i8** getelementptr inbounds ([2 x i8*], [2 x i8*]* @g6, i32 0, i64 1) to i64*)
   ret i64 %tmp
 
 ; LE-LABEL: @test15(
@@ -235,7 +235,7 @@ entry:
 
 @gv7 = constant [4 x i8*] [i8* null, i8* inttoptr (i64 -14 to i8*), i8* null, i8* null]
 define i64 @test16.1() {
-  %v = load i64* bitcast ([4 x i8*]* @gv7 to i64*), align 8
+  %v = load i64, i64* bitcast ([4 x i8*]* @gv7 to i64*), align 8
   ret i64 %v
 
 ; LE-LABEL: @test16.1(
@@ -246,7 +246,7 @@ define i64 @test16.1() {
 }
 
 define i64 @test16.2() {
-  %v = load i64* bitcast (i8** getelementptr inbounds ([4 x i8*]* @gv7, i64 0, i64 1) to i64*), align 8
+  %v = load i64, i64* bitcast (i8** getelementptr inbounds ([4 x i8*], [4 x i8*]* @gv7, i64 0, i64 1) to i64*), align 8
   ret i64 %v
 
 ; LE-LABEL: @test16.2(
@@ -257,7 +257,7 @@ define i64 @test16.2() {
 }
 
 define i64 @test16.3() {
-  %v = load i64* bitcast (i8** getelementptr inbounds ([4 x i8*]* @gv7, i64 0, i64 2) to i64*), align 8
+  %v = load i64, i64* bitcast (i8** getelementptr inbounds ([4 x i8*], [4 x i8*]* @gv7, i64 0, i64 2) to i64*), align 8
   ret i64 %v
 
 ; LE-LABEL: @test16.3(
diff --git a/test/Transforms/ConstantHoisting/AArch64/const-addr.ll b/test/Transforms/ConstantHoisting/AArch64/const-addr.ll
index 89d596055c44..4c36d20dc6b0 100644
--- a/test/Transforms/ConstantHoisting/AArch64/const-addr.ll
+++ b/test/Transforms/ConstantHoisting/AArch64/const-addr.ll
@@ -6,17 +6,17 @@ define i32 @test1() nounwind {
 ; CHECK-LABEL: test1
 ; CHECK: %const = bitcast i64 68141056 to i64
 ; CHECK: %1 = inttoptr i64 %const to %T*
-; CHECK: %o1 = getelementptr %T* %1, i32 0, i32 1
-; CHECK: %o2 = getelementptr %T* %1, i32 0, i32 2
-; CHECK: %o3 = getelementptr %T* %1, i32 0, i32 3
+; CHECK: %o1 = getelementptr %T, %T* %1, i32 0, i32 1
+; CHECK: %o2 = getelementptr %T, %T* %1, i32 0, i32 2
+; CHECK: %o3 = getelementptr %T, %T* %1, i32 0, i32 3
   %at = inttoptr i64 68141056 to %T*
-  %o1 = getelementptr %T* %at, i32 0, i32 1
-  %t1 = load i32* %o1
-  %o2 = getelementptr %T* %at, i32 0, i32 2
-  %t2 = load i32* %o2
+  %o1 = getelementptr %T, %T* %at, i32 0, i32 1
+  %t1 = load i32, i32* %o1
+  %o2 = getelementptr %T, %T* %at, i32 0, i32 2
+  %t2 = load i32, i32* %o2
   %a1 = add i32 %t1, %t2
-  %o3 = getelementptr %T* %at, i32 0, i32 3
-  %t3 = load i32* %o3
+  %o3 = getelementptr %T, %T* %at, i32 0, i32 3
+  %t3 = load i32, i32* %o3
   %a2 = add i32 %a1, %t3
   ret i32 %a2
 }
diff --git a/test/Transforms/ConstantHoisting/PowerPC/const-base-addr.ll b/test/Transforms/ConstantHoisting/PowerPC/const-base-addr.ll
index b4337eeda653..69b13cf9c9a4 100644
--- a/test/Transforms/ConstantHoisting/PowerPC/const-base-addr.ll
+++ b/test/Transforms/ConstantHoisting/PowerPC/const-base-addr.ll
@@ -9,13 +9,13 @@ define i32 @test1() nounwind {
 ; CHECK-LABEL:  @test1
 ; CHECK:        %const = bitcast i32 12345678 to i32
 ; CHECK:        %1 = inttoptr i32 %const to %T*
-; CHECK:        %addr1 = getelementptr %T* %1, i32 0, i32 1
-  %addr1 = getelementptr %T* inttoptr (i32 12345678 to %T*), i32 0, i32 1
-  %tmp1 = load i32* %addr1
-  %addr2 = getelementptr %T* inttoptr (i32 12345678 to %T*), i32 0, i32 2
-  %tmp2 = load i32* %addr2
-  %addr3 = getelementptr %T* inttoptr (i32 12345678 to %T*), i32 0, i32 3
-  %tmp3 = load i32* %addr3
+; CHECK:        %addr1 = getelementptr %T, %T* %1, i32 0, i32 1
+  %addr1 = getelementptr %T, %T* inttoptr (i32 12345678 to %T*), i32 0, i32 1
+  %tmp1 = load i32, i32* %addr1
+  %addr2 = getelementptr %T, %T* inttoptr (i32 12345678 to %T*), i32 0, i32 2
+  %tmp2 = load i32, i32* %addr2
+  %addr3 = getelementptr %T, %T* inttoptr (i32 12345678 to %T*), i32 0, i32 3
+  %tmp3 = load i32, i32* %addr3
   %tmp4 = add i32 %tmp1, %tmp2
   %tmp5 = add i32 %tmp3, %tmp4
   ret i32 %tmp5
diff --git a/test/Transforms/ConstantHoisting/PowerPC/masks.ll b/test/Transforms/ConstantHoisting/PowerPC/masks.ll
index d55318201136..4cc504f11bd9 100644
--- a/test/Transforms/ConstantHoisting/PowerPC/masks.ll
+++ b/test/Transforms/ConstantHoisting/PowerPC/masks.ll
@@ -19,7 +19,7 @@ if.then152:
 if.end167:
 ; CHECK: and i32 {{.*}}, 32768
   %shl161 = shl nuw nsw i32 %conv121, 15
-  %0 = load i8* undef, align 1
+  %0 = load i8, i8* undef, align 1
   %conv169 = zext i8 %0 to i32
   %shl170 = shl nuw nsw i32 %conv169, 7
   %shl161.masked = and i32 %shl161, 32768
@@ -49,7 +49,7 @@ if.then152:
 if.end167:
 ; CHECK: add i32 {{.*}}, -32758
   %shl161 = shl nuw nsw i32 %conv121, 15
-  %0 = load i8* undef, align 1
+  %0 = load i8, i8* undef, align 1
   %conv169 = zext i8 %0 to i32
   %shl170 = shl nuw nsw i32 %conv169, 7
   %shl161.masked = and i32 %shl161, 32773
diff --git a/test/Transforms/ConstantHoisting/X86/cast-inst.ll b/test/Transforms/ConstantHoisting/X86/cast-inst.ll
index f490f4a37236..bd1e196b6445 100644
--- a/test/Transforms/ConstantHoisting/X86/cast-inst.ll
+++ b/test/Transforms/ConstantHoisting/X86/cast-inst.ll
@@ -9,19 +9,19 @@ define i32 @cast_inst_test() {
 ; CHECK-LABEL:  @cast_inst_test
 ; CHECK:        %const = bitcast i64 4646526064 to i64
 ; CHECK:        %1 = inttoptr i64 %const to i32*
-; CHECK:        %v0 = load i32* %1, align 16
+; CHECK:        %v0 = load i32, i32* %1, align 16
 ; CHECK:        %const_mat = add i64 %const, 16
 ; CHECK-NEXT:   %2 = inttoptr i64 %const_mat to i32*
-; CHECK-NEXT:   %v1 = load i32* %2, align 16
+; CHECK-NEXT:   %v1 = load i32, i32* %2, align 16
 ; CHECK:        %const_mat1 = add i64 %const, 32
 ; CHECK-NEXT:   %3 = inttoptr i64 %const_mat1 to i32*
-; CHECK-NEXT:   %v2 = load i32* %3, align 16
+; CHECK-NEXT:   %v2 = load i32, i32* %3, align 16
   %a0 = inttoptr i64 4646526064 to i32*
-  %v0 = load i32* %a0, align 16
+  %v0 = load i32, i32* %a0, align 16
   %a1 = inttoptr i64 4646526080 to i32*
-  %v1 = load i32* %a1, align 16
+  %v1 = load i32, i32* %a1, align 16
   %a2 = inttoptr i64 4646526096 to i32*
-  %v2 = load i32* %a2, align 16
+  %v2 = load i32, i32* %a2, align 16
   %r0 = add i32 %v0, %v1
   %r1 = add i32 %r0, %v2
   ret i32 %r1
diff --git a/test/Transforms/ConstantHoisting/X86/const-base-addr.ll b/test/Transforms/ConstantHoisting/X86/const-base-addr.ll
index 01e6cdfd2a5b..db5dfdd1538a 100644
--- a/test/Transforms/ConstantHoisting/X86/const-base-addr.ll
+++ b/test/Transforms/ConstantHoisting/X86/const-base-addr.ll
@@ -10,13 +10,13 @@ define i32 @test1() nounwind {
 ; CHECK-LABEL:  @test1
 ; CHECK:        %const = bitcast i32 12345678 to i32
 ; CHECK:        %1 = inttoptr i32 %const to %T*
-; CHECK:        %addr1 = getelementptr %T* %1, i32 0, i32 1
-  %addr1 = getelementptr %T* inttoptr (i32 12345678 to %T*), i32 0, i32 1
-  %tmp1 = load i32* %addr1
-  %addr2 = getelementptr %T* inttoptr (i32 12345678 to %T*), i32 0, i32 2
-  %tmp2 = load i32* %addr2
-  %addr3 = getelementptr %T* inttoptr (i32 12345678 to %T*), i32 0, i32 3
-  %tmp3 = load i32* %addr3
+; CHECK:        %addr1 = getelementptr %T, %T* %1, i32 0, i32 1
+  %addr1 = getelementptr %T, %T* inttoptr (i32 12345678 to %T*), i32 0, i32 1
+  %tmp1 = load i32, i32* %addr1
+  %addr2 = getelementptr %T, %T* inttoptr (i32 12345678 to %T*), i32 0, i32 2
+  %tmp2 = load i32, i32* %addr2
+  %addr3 = getelementptr %T, %T* inttoptr (i32 12345678 to %T*), i32 0, i32 3
+  %tmp3 = load i32, i32* %addr3
   %tmp4 = add i32 %tmp1, %tmp2
   %tmp5 = add i32 %tmp3, %tmp4
   ret i32 %tmp5
diff --git a/test/Transforms/ConstantHoisting/X86/delete-dead-cast-inst.ll b/test/Transforms/ConstantHoisting/X86/delete-dead-cast-inst.ll
index d35238692078..5df4c1a376e5 100644
--- a/test/Transforms/ConstantHoisting/X86/delete-dead-cast-inst.ll
+++ b/test/Transforms/ConstantHoisting/X86/delete-dead-cast-inst.ll
@@ -10,13 +10,13 @@ define i32 @test1() nounwind {
 ; CHECK:        %const = bitcast i32 12345678 to i32
 ; CHECK-NOT:    %base = inttoptr i32 12345678 to %T*
 ; CHECK-NEXT:   %1 = inttoptr i32 %const to %T*
-; CHECK-NEXT:   %addr1 = getelementptr %T* %1, i32 0, i32 1
-; CHECK-NEXT:   %addr2 = getelementptr %T* %1, i32 0, i32 2
-; CHECK-NEXT:   %addr3 = getelementptr %T* %1, i32 0, i32 3
+; CHECK-NEXT:   %addr1 = getelementptr %T, %T* %1, i32 0, i32 1
+; CHECK-NEXT:   %addr2 = getelementptr %T, %T* %1, i32 0, i32 2
+; CHECK-NEXT:   %addr3 = getelementptr %T, %T* %1, i32 0, i32 3
   %base = inttoptr i32 12345678 to %T*
-  %addr1 = getelementptr %T* %base, i32 0, i32 1
-  %addr2 = getelementptr %T* %base, i32 0, i32 2
-  %addr3 = getelementptr %T* %base, i32 0, i32 3
+  %addr1 = getelementptr %T, %T* %base, i32 0, i32 1
+  %addr2 = getelementptr %T, %T* %base, i32 0, i32 2
+  %addr3 = getelementptr %T, %T* %base, i32 0, i32 3
   ret i32 12345678
 }
 
diff --git a/test/Transforms/ConstantHoisting/X86/stackmap.ll b/test/Transforms/ConstantHoisting/X86/stackmap.ll
index 9df44177820e..b9aee6b38fb0 100644
--- a/test/Transforms/ConstantHoisting/X86/stackmap.ll
+++ b/test/Transforms/ConstantHoisting/X86/stackmap.ll
@@ -7,10 +7,10 @@ target triple = "x86_64-apple-macosx10.9.0"
 define i128 @test1(i128 %a) {
 ; CHECK-LABEL:  @test1
 ; CHECK:        %const = bitcast i128 134646182756734033220 to i128
-; CHECK:        tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 1, i32 24, i128 %const)
+; CHECK:        tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 1, i32 24, i128 %const)
 entry:
   %0 = add i128 %a, 134646182756734033220
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 1, i32 24, i128 134646182756734033220)
+  tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 1, i32 24, i128 134646182756734033220)
   ret i128 %0
 }
 
diff --git a/test/Transforms/ConstantMerge/2002-09-23-CPR-Update.ll b/test/Transforms/ConstantMerge/2002-09-23-CPR-Update.ll
index b7b05cf1c370..2e83503af815 100644
--- a/test/Transforms/ConstantMerge/2002-09-23-CPR-Update.ll
+++ b/test/Transforms/ConstantMerge/2002-09-23-CPR-Update.ll
@@ -6,8 +6,8 @@
 declare i32 @test(i32*)
 
 define void @foo() {
-        call i32 @test( i32* getelementptr ({ i32 }* @foo.upgrd.1, i64 0, i32 0) )              ; <i32>:1 [#uses=0]
-        call i32 @test( i32* getelementptr ({ i32 }* @bar, i64 0, i32 0) )              ; <i32>:2 [#uses=0]
+        call i32 @test( i32* getelementptr ({ i32 }, { i32 }* @foo.upgrd.1, i64 0, i32 0) )              ; <i32>:1 [#uses=0]
+        call i32 @test( i32* getelementptr ({ i32 }, { i32 }* @bar, i64 0, i32 0) )              ; <i32>:2 [#uses=0]
         ret void
 }
 
diff --git a/test/Transforms/ConstantMerge/merge-both.ll b/test/Transforms/ConstantMerge/merge-both.ll
index 316267648f1f..11b0621d42d7 100644
--- a/test/Transforms/ConstantMerge/merge-both.ll
+++ b/test/Transforms/ConstantMerge/merge-both.ll
@@ -1,7 +1,6 @@
 ; RUN: opt -constmerge -S < %s | FileCheck %s
 ; Test that in one run var3 is merged into var2 and var1 into var4.
-; Test that we merge @var5 and @var6 into one with the higher alignment, and
-; don't merge var7/var8 into var5/var6.
+; Test that we merge @var5 and @var6 into one with the higher alignment
 
 declare void @zed(%struct.foobar*, %struct.foobar*)
 
@@ -23,8 +22,8 @@ declare void @helper([16 x i8]*)
 @var7 = internal constant [16 x i8] c"foo1bar2foo3bar\00"
 @var8 = private unnamed_addr constant [16 x i8] c"foo1bar2foo3bar\00"
 
-; CHECK-NEXT: @var6 = private constant [16 x i8] c"foo1bar2foo3bar\00", align 16
-; CHECK-NEXT: @var8 = private constant [16 x i8] c"foo1bar2foo3bar\00"
+; CHECK-NEXT: @var7 = internal constant [16 x i8] c"foo1bar2foo3bar\00"
+; CHECK-NEXT: @var8 = private constant [16 x i8] c"foo1bar2foo3bar\00", align 16
 
 @var4a = alias %struct.foobar* @var4
 @llvm.used = appending global [1 x %struct.foobar*] [%struct.foobar* @var4a], section "llvm.metadata"
diff --git a/test/Transforms/CorrelatedValuePropagation/basic.ll b/test/Transforms/CorrelatedValuePropagation/basic.ll
index 9a2264793c50..9d1253a1888e 100644
--- a/test/Transforms/CorrelatedValuePropagation/basic.ll
+++ b/test/Transforms/CorrelatedValuePropagation/basic.ll
@@ -52,8 +52,8 @@ bb:             ; preds = %entry
         ret i8 0
 
 bb2:            ; preds = %entry
-; CHECK: %should_be_const = load i8* @gv
-        %should_be_const = load i8* %a
+; CHECK: %should_be_const = load i8, i8* @gv
+        %should_be_const = load i8, i8* %a
         ret i8 %should_be_const
 }
 
diff --git a/test/Transforms/CorrelatedValuePropagation/non-null.ll b/test/Transforms/CorrelatedValuePropagation/non-null.ll
index b14abd83694a..6bb8bb07c45f 100644
--- a/test/Transforms/CorrelatedValuePropagation/non-null.ll
+++ b/test/Transforms/CorrelatedValuePropagation/non-null.ll
@@ -2,7 +2,7 @@
 
 define void @test1(i8* %ptr) {
 ; CHECK: test1
-  %A = load i8* %ptr
+  %A = load i8, i8* %ptr
   br label %bb
 bb:
   icmp ne i8* %ptr, null
diff --git a/test/Transforms/CorrelatedValuePropagation/select.ll b/test/Transforms/CorrelatedValuePropagation/select.ll
new file mode 100644
index 000000000000..5501438f690f
--- /dev/null
+++ b/test/Transforms/CorrelatedValuePropagation/select.ll
@@ -0,0 +1,53 @@
+; RUN: opt < %s -correlated-propagation -S | FileCheck %s
+
+; CHECK-LABEL: @simple(
+define i8 @simple(i1) {
+entry:
+  %s = select i1 %0, i8 0, i8 1
+  br i1 %0, label %then, label %else
+
+then:
+; CHECK: ret i8 0
+  %a = phi i8 [ %s, %entry ]
+  ret i8 %a
+
+else:
+; CHECK: ret i8 1
+  %b = phi i8 [ %s, %entry ]
+  ret i8 %b
+}
+
+; CHECK-LABEL: @loop(
+define void @loop(i32) {
+entry:
+  br label %loop
+
+loop:
+  %idx = phi i32 [ %0, %entry ], [ %sel, %loop ]
+; CHECK: %idx = phi i32 [ %0, %entry ], [ %2, %loop ]
+  %1 = icmp eq i32 %idx, 0
+  %2 = add i32 %idx, -1
+  %sel = select i1 %1, i32 0, i32 %2
+  br i1 %1, label %out, label %loop
+
+out:
+  ret void
+}
+
+; CHECK-LABEL: @not_correlated(
+define i8 @not_correlated(i1, i1) {
+entry:
+  %s = select i1 %0, i8 0, i8 1
+  br i1 %1, label %then, label %else
+
+then:
+; CHECK: ret i8 %s
+  %a = phi i8 [ %s, %entry ]
+  ret i8 %a
+
+else:
+; CHECK: ret i8 %s
+  %b = phi i8 [ %s, %entry ]
+  ret i8 %b
+}
+
diff --git a/test/Transforms/DeadArgElim/2007-10-18-VarargsReturn.ll b/test/Transforms/DeadArgElim/2007-10-18-VarargsReturn.ll
index cdd893faba26..9bbc275ae7d7 100644
--- a/test/Transforms/DeadArgElim/2007-10-18-VarargsReturn.ll
+++ b/test/Transforms/DeadArgElim/2007-10-18-VarargsReturn.ll
@@ -6,7 +6,7 @@ define internal i32 @test(i32 %A, ...) {
 }
 
 define i32 @foo() {
-	%A = call i32(i32, ...)* @test(i32 1)
+	%A = call i32(i32, ...) @test(i32 1)
 	ret i32 %A
 }
 
diff --git a/test/Transforms/DeadArgElim/2007-12-20-ParamAttrs.ll b/test/Transforms/DeadArgElim/2007-12-20-ParamAttrs.ll
index f049265ce4ea..ab378e9df1ee 100644
--- a/test/Transforms/DeadArgElim/2007-12-20-ParamAttrs.ll
+++ b/test/Transforms/DeadArgElim/2007-12-20-ParamAttrs.ll
@@ -13,7 +13,7 @@ define internal zeroext i8 @foo(i8* inreg %p, i8 signext %y, ... )  nounwind {
 
 define i32 @bar() {
 ; CHECK: call void @foo(i8 signext 1) [[NUW]]
-  %A = call zeroext i8(i8*, i8, ...)* @foo(i8* inreg null, i8 signext 1, %struct* byval null ) nounwind
+  %A = call zeroext i8(i8*, i8, ...) @foo(i8* inreg null, i8 signext 1, %struct* byval null ) nounwind
   ret i32 0
 }
 
diff --git a/test/Transforms/DeadArgElim/2008-01-16-VarargsParamAttrs.ll b/test/Transforms/DeadArgElim/2008-01-16-VarargsParamAttrs.ll
index 93282f7f8f2b..48e43961e7a1 100644
--- a/test/Transforms/DeadArgElim/2008-01-16-VarargsParamAttrs.ll
+++ b/test/Transforms/DeadArgElim/2008-01-16-VarargsParamAttrs.ll
@@ -22,8 +22,8 @@ declare void @llvm.va_end(i8*) nounwind
 define i32 @main() {
 entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
-	%tmp = getelementptr [4 x %struct.point]* @pts, i32 0, i32 0		; <%struct.point*> [#uses=1]
-	%tmp1 = call i32 (i32, ...)* @va1( i32 1, %struct.point* byval  %tmp ) nounwind 		; <i32> [#uses=0]
+	%tmp = getelementptr [4 x %struct.point], [4 x %struct.point]* @pts, i32 0, i32 0		; <%struct.point*> [#uses=1]
+	%tmp1 = call i32 (i32, ...) @va1( i32 1, %struct.point* byval  %tmp ) nounwind 		; <i32> [#uses=0]
 	call void @exit( i32 0 ) noreturn nounwind 
 	unreachable
 }
diff --git a/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll b/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll
index dd283aebc1d4..5ff05f0d6858 100644
--- a/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll
+++ b/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll
@@ -4,10 +4,10 @@
 
 define i8* @vfs_addname(i8* %name, i32 %len, i32 %hash, i32 %flags) nounwind ssp {
 entry:
-  call void @llvm.dbg.value(metadata i8* %name, i64 0, metadata !0, metadata !{})
-  call void @llvm.dbg.value(metadata i32 %len, i64 0, metadata !10, metadata !{})
-  call void @llvm.dbg.value(metadata i32 %hash, i64 0, metadata !11, metadata !{})
-  call void @llvm.dbg.value(metadata i32 %flags, i64 0, metadata !12, metadata !{})
+  call void @llvm.dbg.value(metadata i8* %name, i64 0, metadata !0, metadata !DIExpression()), !dbg !DILocation(scope: !1)
+  call void @llvm.dbg.value(metadata i32 %len, i64 0, metadata !10, metadata !DIExpression()), !dbg !DILocation(scope: !1)
+  call void @llvm.dbg.value(metadata i32 %hash, i64 0, metadata !11, metadata !DIExpression()), !dbg !DILocation(scope: !1)
+  call void @llvm.dbg.value(metadata i32 %flags, i64 0, metadata !12, metadata !DIExpression()), !dbg !DILocation(scope: !1)
 ; CHECK:  call fastcc i8* @add_name_internal(i8* %name, i32 %hash) [[NUW:#[0-9]+]], !dbg !{{[0-9]+}}
   %0 = call fastcc i8* @add_name_internal(i8* %name, i32 %len, i32 %hash, i8 zeroext 0, i32 %flags) nounwind, !dbg !13 ; <i8*> [#uses=1]
   ret i8* %0, !dbg !13
@@ -17,11 +17,11 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 
 define internal fastcc i8* @add_name_internal(i8* %name, i32 %len, i32 %hash, i8 zeroext %extra, i32 %flags) noinline nounwind ssp {
 entry:
-  call void @llvm.dbg.value(metadata i8* %name, i64 0, metadata !15, metadata !{})
-  call void @llvm.dbg.value(metadata i32 %len, i64 0, metadata !20, metadata !{})
-  call void @llvm.dbg.value(metadata i32 %hash, i64 0, metadata !21, metadata !{})
-  call void @llvm.dbg.value(metadata i8 %extra, i64 0, metadata !22, metadata !{})
-  call void @llvm.dbg.value(metadata i32 %flags, i64 0, metadata !23, metadata !{})
+  call void @llvm.dbg.value(metadata i8* %name, i64 0, metadata !15, metadata !DIExpression()), !dbg !DILocation(scope: !16)
+  call void @llvm.dbg.value(metadata i32 %len, i64 0, metadata !20, metadata !DIExpression()), !dbg !DILocation(scope: !16)
+  call void @llvm.dbg.value(metadata i32 %hash, i64 0, metadata !21, metadata !DIExpression()), !dbg !DILocation(scope: !16)
+  call void @llvm.dbg.value(metadata i8 %extra, i64 0, metadata !22, metadata !DIExpression()), !dbg !DILocation(scope: !16)
+  call void @llvm.dbg.value(metadata i32 %flags, i64 0, metadata !23, metadata !DIExpression()), !dbg !DILocation(scope: !16)
   %0 = icmp eq i32 %hash, 0, !dbg !24             ; <i1> [#uses=1]
   br i1 %0, label %bb, label %bb1, !dbg !24
 
@@ -32,7 +32,7 @@ bb1:                                              ; preds = %entry
   br label %bb2, !dbg !27
 
 bb2:                                              ; preds = %bb1, %bb
-  %.0 = phi i8* [ getelementptr inbounds ([1 x i8]* @.str, i64 0, i64 0), %bb ], [ %name, %bb1 ] ; <i8*> [#uses=1]
+  %.0 = phi i8* [ getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i64 0, i64 0), %bb ], [ %name, %bb1 ] ; <i8*> [#uses=1]
   ret i8* %.0, !dbg !27
 }
 
@@ -45,34 +45,34 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 
 !llvm.dbg.cu = !{!3}
 !llvm.module.flags = !{!30}
-!0 = !{!"0x101\00name\008\000", !1, !2, !6} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00vfs_addname\00vfs_addname\00vfs_addname\0012\000\001\000\006\000\000\000", !28, !2, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !28} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)\001\00\000\00\000", !28, !29, !29, null, null, null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !28, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "name", line: 8, arg: 0, scope: !1, file: !2, type: !6)
+!1 = !DISubprogram(name: "vfs_addname", linkageName: "vfs_addname", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !28, scope: !2, type: !4)
+!2 = !DIFile(filename: "tail.c", directory: "/Users/echeng/LLVM/radars/r7927803/")
+!3 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)", isOptimized: true, emissionKind: 0, file: !28, enums: !29, retainedTypes: !29)
+!4 = !DISubroutineType(types: !5)
 !5 = !{!6, !6, !9, !9, !9}
-!6 = !{!"0xf\00\000\0064\0064\000\000", !28, !2, !7} ; [ DW_TAG_pointer_type ]
-!7 = !{!"0x26\00\000\008\008\000\000", !28, !2, !8} ; [ DW_TAG_const_type ]
-!8 = !{!"0x24\00char\000\008\008\000\000\006", !28, !2} ; [ DW_TAG_base_type ]
-!9 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", !28, !2} ; [ DW_TAG_base_type ]
-!10 = !{!"0x101\00len\009\000", !1, !2, !9} ; [ DW_TAG_arg_variable ]
-!11 = !{!"0x101\00hash\0010\000", !1, !2, !9} ; [ DW_TAG_arg_variable ]
-!12 = !{!"0x101\00flags\0011\000", !1, !2, !9} ; [ DW_TAG_arg_variable ]
-!13 = !MDLocation(line: 13, scope: !14)
-!14 = !{!"0xb\0012\000\000", !28, !1} ; [ DW_TAG_lexical_block ]
-!15 = !{!"0x101\00name\0017\000", !16, !2, !6} ; [ DW_TAG_arg_variable ]
-!16 = !{!"0x2e\00add_name_internal\00add_name_internal\00add_name_internal\0022\001\001\000\006\000\000\000", !28, !2, !17, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!17 = !{!"0x15\00\000\000\000\000\000\000", !28, !2, null, !18, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !28, scope: !2, baseType: !7)
+!7 = !DIDerivedType(tag: DW_TAG_const_type, size: 8, align: 8, file: !28, scope: !2, baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "len", line: 9, arg: 0, scope: !1, file: !2, type: !9)
+!11 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "hash", line: 10, arg: 0, scope: !1, file: !2, type: !9)
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "flags", line: 11, arg: 0, scope: !1, file: !2, type: !9)
+!13 = !DILocation(line: 13, scope: !14)
+!14 = distinct !DILexicalBlock(line: 12, column: 0, file: !28, scope: !1)
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "name", line: 17, arg: 0, scope: !16, file: !2, type: !6)
+!16 = !DISubprogram(name: "add_name_internal", linkageName: "add_name_internal", line: 22, isLocal: true, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !28, scope: !2, type: !17)
+!17 = !DISubroutineType(types: !18)
 !18 = !{!6, !6, !9, !9, !19, !9}
-!19 = !{!"0x24\00unsigned char\000\008\008\000\000\008", !28, !2} ; [ DW_TAG_base_type ]
-!20 = !{!"0x101\00len\0018\000", !16, !2, !9} ; [ DW_TAG_arg_variable ]
-!21 = !{!"0x101\00hash\0019\000", !16, !2, !9} ; [ DW_TAG_arg_variable ]
-!22 = !{!"0x101\00extra\0020\000", !16, !2, !19} ; [ DW_TAG_arg_variable ]
-!23 = !{!"0x101\00flags\0021\000", !16, !2, !9} ; [ DW_TAG_arg_variable ]
-!24 = !MDLocation(line: 23, scope: !25)
-!25 = !{!"0xb\0022\000\000", !28, !16} ; [ DW_TAG_lexical_block ]
-!26 = !MDLocation(line: 24, scope: !25)
-!27 = !MDLocation(line: 26, scope: !25)
-!28 = !{!"tail.c", !"/Users/echeng/LLVM/radars/r7927803/"}
-!29 = !{i32 0}
-!30 = !{i32 1, !"Debug Info Version", i32 2}
+!19 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char)
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "len", line: 18, arg: 0, scope: !16, file: !2, type: !9)
+!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "hash", line: 19, arg: 0, scope: !16, file: !2, type: !9)
+!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "extra", line: 20, arg: 0, scope: !16, file: !2, type: !19)
+!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "flags", line: 21, arg: 0, scope: !16, file: !2, type: !9)
+!24 = !DILocation(line: 23, scope: !25)
+!25 = distinct !DILexicalBlock(line: 22, column: 0, file: !28, scope: !16)
+!26 = !DILocation(line: 24, scope: !25)
+!27 = !DILocation(line: 26, scope: !25)
+!28 = !DIFile(filename: "tail.c", directory: "/Users/echeng/LLVM/radars/r7927803/")
+!29 = !{}
+!30 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/DeadArgElim/2013-05-17-VarargsAndBlockAddress.ll b/test/Transforms/DeadArgElim/2013-05-17-VarargsAndBlockAddress.ll
index 23216031b58a..7552a12142b5 100644
--- a/test/Transforms/DeadArgElim/2013-05-17-VarargsAndBlockAddress.ll
+++ b/test/Transforms/DeadArgElim/2013-05-17-VarargsAndBlockAddress.ll
@@ -19,7 +19,7 @@ l2:
 ; CHECK: define internal i32 @varargs_func(i8* %addr) {
 
 define i32 @caller(i8* %addr) {
-  %r = call i32 (i8*, ...)* @varargs_func(i8* %addr)
+  %r = call i32 (i8*, ...) @varargs_func(i8* %addr)
   ret i32 %r
 }
 ; CHECK: %r = call i32 @varargs_func(i8* %addr)
diff --git a/test/Transforms/DeadArgElim/aggregates.ll b/test/Transforms/DeadArgElim/aggregates.ll
new file mode 100644
index 000000000000..68d253425587
--- /dev/null
+++ b/test/Transforms/DeadArgElim/aggregates.ll
@@ -0,0 +1,162 @@
+; RUN: opt -S -deadargelim %s | FileCheck %s
+
+; Case 0: the basic example: an entire aggregate use is returned, but it's
+; actually only used in ways we can eliminate. We gain benefit from analysing
+; the "use" and applying its results to all sub-values.
+
+; CHECK-LABEL: define internal void @agguse_dead()
+
+define internal { i32, i32 } @agguse_dead() {
+  ret { i32, i32 } { i32 0, i32 1 }
+}
+
+define internal { i32, i32 } @test_agguse_dead() {
+  %val = call { i32, i32 } @agguse_dead()
+  ret { i32, i32 } %val
+}
+
+
+
+; Case 1: an opaque use of the aggregate exists (in this case dead). Otherwise
+; only one value is used, so function can be simplified.
+
+; CHECK-LABEL: define internal i32 @rets_independent_if_agguse_dead()
+; CHECK: [[RET:%.*]] = extractvalue { i32, i32 } { i32 0, i32 1 }, 1
+; CHECK: ret i32 [[RET]]
+
+define internal { i32, i32 } @rets_independent_if_agguse_dead() {
+  ret { i32, i32 } { i32 0, i32 1 }
+}
+
+define internal { i32, i32 } @test_rets_independent_if_agguse_dead(i1 %tst) {
+  %val = call { i32, i32 } @rets_independent_if_agguse_dead()
+  br i1 %tst, label %use_1, label %use_aggregate
+
+use_1:
+  ; This use can be classified as applying only to ret 1.
+  %val0 = extractvalue { i32, i32 } %val, 1
+  call void @callee(i32 %val0)
+  ret { i32, i32 } undef
+
+use_aggregate:
+  ; This use is assumed to apply to both 0 and 1.
+  ret { i32, i32 } %val
+}
+
+; Case 2: an opaque use of the aggregate exists (in this case *live*). Other
+; uses shouldn't matter.
+
+; CHECK-LABEL: define internal { i32, i32 } @rets_live_agguse()
+; CHECK: ret { i32, i32 } { i32 0, i32 1 }
+
+define internal { i32, i32 } @rets_live_agguse() {
+  ret { i32, i32} { i32 0, i32 1 }
+}
+
+define { i32, i32 } @test_rets_live_aggues(i1 %tst) {
+  %val = call { i32, i32 } @rets_live_agguse()
+  br i1 %tst, label %use_1, label %use_aggregate
+
+use_1:
+  ; This use can be classified as applying only to ret 1.
+  %val0 = extractvalue { i32, i32 } %val, 1
+  call void @callee(i32 %val0)
+  ret { i32, i32 } undef
+
+use_aggregate:
+  ; This use is assumed to apply to both 0 and 1.
+  ret { i32, i32 } %val
+}
+
+declare void @callee(i32)
+
+; Case 3: the insertvalue meant %in was live if ret-slot-1 was, but we were only
+; tracking multiple ret-slots for struct types. So %in was eliminated
+; incorrectly.
+
+; CHECK-LABEL: define internal [2 x i32] @array_rets_have_multiple_slots(i32 %in)
+
+define internal [2 x i32] @array_rets_have_multiple_slots(i32 %in) {
+  %ret = insertvalue [2 x i32] undef, i32 %in, 1
+  ret [2 x i32] %ret
+}
+
+define [2 x i32] @test_array_rets_have_multiple_slots() {
+  %res = call [2 x i32] @array_rets_have_multiple_slots(i32 42)
+  ret [2 x i32] %res
+}
+
+; Case 4: we can remove some retvals from the array. It's nice to produce an
+; array again having done so (rather than converting it to a struct).
+
+; CHECK-LABEL: define internal [2 x i32] @can_shrink_arrays()
+; CHECK: [[VAL0:%.*]] = extractvalue [3 x i32] [i32 42, i32 43, i32 44], 0
+; CHECK: [[RESTMP:%.*]] = insertvalue [2 x i32] undef, i32 [[VAL0]], 0
+; CHECK: [[VAL2:%.*]] = extractvalue [3 x i32] [i32 42, i32 43, i32 44], 2
+; CHECK: [[RES:%.*]] = insertvalue [2 x i32] [[RESTMP]], i32 [[VAL2]], 1
+; CHECK: ret [2 x i32] [[RES]]
+
+; CHECK-LABEL: define void @test_can_shrink_arrays()
+
+define internal [3 x i32] @can_shrink_arrays() {
+  ret [3 x i32] [i32 42, i32 43, i32 44]
+}
+
+define void @test_can_shrink_arrays() {
+  %res = call [3 x i32] @can_shrink_arrays()
+
+  %res.0 = extractvalue [3 x i32] %res, 0
+  call void @callee(i32 %res.0)
+
+  %res.2 = extractvalue [3 x i32] %res, 2
+  call void @callee(i32 %res.2)
+
+  ret void
+}
+
+; Case 5: %in gets passed directly to the return. It should mark be marked as
+; used if *any* of the return values are, not just if value 0 is.
+
+; CHECK-LABEL: define internal i32 @ret_applies_to_all({ i32, i32 } %in)
+; CHECK: [[RET:%.*]] = extractvalue { i32, i32 } %in, 1
+; CHECK: ret i32 [[RET]]
+
+define internal {i32, i32} @ret_applies_to_all({i32, i32} %in) {
+  ret {i32, i32} %in
+}
+
+define i32 @test_ret_applies_to_all() {
+  %val = call {i32, i32} @ret_applies_to_all({i32, i32} {i32 42, i32 43})
+  %ret = extractvalue {i32, i32} %val, 1
+  ret i32 %ret
+}
+
+; Case 6: When considering @mid, the return instruciton has sub-value 0
+; unconditionally live, but 1 only conditionally live. Since at that level we're
+; applying the results to the whole of %res, this means %res is live and cannot
+; be reduced. There is scope for further optimisation here (though not visible
+; in this test-case).
+
+; CHECK-LABEL: define internal { i8*, i32 } @inner()
+
+define internal {i8*, i32} @mid() {
+  %res = call {i8*, i32} @inner()
+  %intval = extractvalue {i8*, i32} %res, 1
+  %tst = icmp eq i32 %intval, 42
+  br i1 %tst, label %true, label %true
+
+true:
+  ret {i8*, i32} %res
+}
+
+define internal {i8*, i32} @inner() {
+  ret {i8*, i32} {i8* null, i32 42}
+}
+
+define internal i8 @outer() {
+  %res = call {i8*, i32} @mid()
+  %resptr = extractvalue {i8*, i32} %res, 0
+
+  %val = load i8, i8* %resptr
+  ret i8 %val
+}
\ No newline at end of file
diff --git a/test/Transforms/DeadArgElim/dbginfo.ll b/test/Transforms/DeadArgElim/dbginfo.ll
index 5bbf821ef213..efafd9bbc9e2 100644
--- a/test/Transforms/DeadArgElim/dbginfo.ll
+++ b/test/Transforms/DeadArgElim/dbginfo.ll
@@ -14,7 +14,7 @@
 ; the function->debug info mapping on update to ensure it's accurate when used
 ; again for the next removal.
 
-; CHECK: void ()* @_ZL2f1iz, {{.*}} ; [ DW_TAG_subprogram ] {{.*}} [f1]
+; CHECK: !DISubprogram(name: "f1",{{.*}} function: void ()* @_ZL2f1iz
 
 ; Check that debug info metadata for subprograms stores pointers to
 ; updated LLVM functions.
@@ -22,7 +22,7 @@
 ; Function Attrs: uwtable
 define void @_Z2f2v() #0 {
 entry:
-  call void (i32, ...)* @_ZL2f1iz(i32 1), !dbg !15
+  call void (i32, ...) @_ZL2f1iz(i32 1), !dbg !15
   ret void, !dbg !16
 }
 
@@ -47,24 +47,24 @@ attributes #2 = { nounwind readnone }
 !llvm.module.flags = !{!12, !13}
 !llvm.ident = !{!14}
 
-!0 = !{!"0x11\004\00clang version 3.6.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/dbginfo/dbg.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"dbg.cpp", !"/tmp/dbginfo"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.6.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "dbg.cpp", directory: "/tmp/dbginfo")
 !2 = !{}
 !3 = !{!4, !8}
-!4 = !{!"0x2e\00f2\00f2\00_Z2f2v\004\000\001\000\000\00256\000\004", !1, !5, !6, null, void ()* @_Z2f2v, null, null, !2} ; [ DW_TAG_subprogram ] [line 4] [def] [f2]
-!5 = !{!"0x29", !1}    ; [ DW_TAG_file_type ] [/tmp/dbginfo/dbg.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "f2", linkageName: "_Z2f2v", line: 4, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !1, scope: !5, type: !6, function: void ()* @_Z2f2v, variables: !2)
+!5 = !DIFile(filename: "dbg.cpp", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
-!8 = !{!"0x2e\00f1\00f1\00_ZL2f1iz\001\001\001\000\000\00256\000\001", !1, !5, !9, null, void (i32, ...)* @_ZL2f1iz, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [local] [def] [f1]
-!9 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = !DISubprogram(name: "f1", linkageName: "_ZL2f1iz", line: 1, isLocal: true, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !9, function: void (i32, ...)* @_ZL2f1iz, variables: !2)
+!9 = !DISubroutineType(types: !10)
 !10 = !{null, !11, null}
-!11 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !12 = !{i32 2, !"Dwarf Version", i32 4}
-!13 = !{i32 2, !"Debug Info Version", i32 2}
+!13 = !{i32 2, !"Debug Info Version", i32 3}
 !14 = !{!"clang version 3.6.0 "}
-!15 = !MDLocation(line: 5, column: 3, scope: !4)
-!16 = !MDLocation(line: 6, column: 1, scope: !4)
-!17 = !{!"0x101\00\0016777217\000", !8, !5, !11} ; [ DW_TAG_arg_variable ] [line 1]
-!18 = !{!"0x102"}               ; [ DW_TAG_expression ]
-!19 = !MDLocation(line: 1, column: 19, scope: !8)
-!20 = !MDLocation(line: 2, column: 1, scope: !8)
+!15 = !DILocation(line: 5, column: 3, scope: !4)
+!16 = !DILocation(line: 6, column: 1, scope: !4)
+!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "", line: 1, arg: 1, scope: !8, file: !5, type: !11)
+!18 = !DIExpression()
+!19 = !DILocation(line: 1, column: 19, scope: !8)
+!20 = !DILocation(line: 2, column: 1, scope: !8)
diff --git a/test/Transforms/DeadArgElim/dead_vaargs.ll b/test/Transforms/DeadArgElim/dead_vaargs.ll
index c8189c66b48c..375415948af1 100644
--- a/test/Transforms/DeadArgElim/dead_vaargs.ll
+++ b/test/Transforms/DeadArgElim/dead_vaargs.ll
@@ -1,25 +1,25 @@
 ; RUN: opt < %s -deadargelim -S | FileCheck %s
 
 define i32 @bar(i32 %A) {
-  call void (i32, ...)* @thunk(i32 %A, i64 47, double 1.000000e+00)
-  %a = call i32 (i32, ...)* @has_vastart(i32 %A, i64 47, double 1.000000e+00)
-  %b = call i32 (i32, ...)* @no_vastart( i32 %A, i32 %A, i32 %A, i32 %A, i64 47, double 1.000000e+00 )
+  call void (i32, ...) @thunk(i32 %A, i64 47, double 1.000000e+00)
+  %a = call i32 (i32, ...) @has_vastart(i32 %A, i64 47, double 1.000000e+00)
+  %b = call i32 (i32, ...) @no_vastart( i32 %A, i32 %A, i32 %A, i32 %A, i64 47, double 1.000000e+00 )
   %c = add i32 %a, %b
   ret i32 %c
 }
 ; CHECK-LABEL: define i32 @bar
-; CHECK: call void (i32, ...)* @thunk(i32 %A, i64 47, double 1.000000e+00)
-; CHECK: call i32 (i32, ...)* @has_vastart(i32 %A, i64 47, double 1.000000e+00)
+; CHECK: call void (i32, ...) @thunk(i32 %A, i64 47, double 1.000000e+00)
+; CHECK: call i32 (i32, ...) @has_vastart(i32 %A, i64 47, double 1.000000e+00)
 ; CHECK: call i32 @no_vastart(i32 %A)
 
 declare void @thunk_target(i32 %X, ...)
 
 define internal void @thunk(i32 %X, ...) {
-  musttail call void(i32, ...)* @thunk_target(i32 %X, ...)
+  musttail call void(i32, ...) @thunk_target(i32 %X, ...)
   ret void
 }
 ; CHECK-LABEL: define internal void @thunk(i32 %X, ...)
-; CHECK: musttail call void (i32, ...)* @thunk_target(i32 %X, ...)
+; CHECK: musttail call void (i32, ...) @thunk_target(i32 %X, ...)
 
 define internal i32 @has_vastart(i32 %X, ...) {
   %valist = alloca i8
diff --git a/test/Transforms/DeadArgElim/deadexternal.ll b/test/Transforms/DeadArgElim/deadexternal.ll
index 665d7dbf4937..21cbc37a3f00 100644
--- a/test/Transforms/DeadArgElim/deadexternal.ll
+++ b/test/Transforms/DeadArgElim/deadexternal.ll
@@ -31,9 +31,9 @@ define void @h() {
 entry:
   %i = alloca i32, align 4
   store volatile i32 10, i32* %i, align 4
-; CHECK: %tmp = load volatile i32* %i, align 4
+; CHECK: %tmp = load volatile i32, i32* %i, align 4
 ; CHECK-NEXT: call void @f(i32 undef)
-  %tmp = load volatile i32* %i, align 4
+  %tmp = load volatile i32, i32* %i, align 4
   call void @f(i32 %tmp)
   ret void
 }
diff --git a/test/Transforms/DeadArgElim/deadretval2.ll b/test/Transforms/DeadArgElim/deadretval2.ll
index dcdc36e319a3..b0d2428fbdc0 100644
--- a/test/Transforms/DeadArgElim/deadretval2.ll
+++ b/test/Transforms/DeadArgElim/deadretval2.ll
@@ -20,7 +20,7 @@ define void @test3(i32 %X) {
 }
 
 define internal i32 @foo() {
-        %DEAD = load i32* @P            ; <i32> [#uses=1]
+        %DEAD = load i32, i32* @P            ; <i32> [#uses=1]
         ret i32 %DEAD
 }
 
diff --git a/test/Transforms/DeadArgElim/keepalive.ll b/test/Transforms/DeadArgElim/keepalive.ll
index 16569db4d38f..d8a09933dcf9 100644
--- a/test/Transforms/DeadArgElim/keepalive.ll
+++ b/test/Transforms/DeadArgElim/keepalive.ll
@@ -31,7 +31,7 @@ define void @caller() {
 ; We can't remove 'this' here, as that would put argmem in ecx instead of
 ; memory.
 define internal x86_thiscallcc i32 @unused_this(i32* %this, i32* inalloca %argmem) {
-	%v = load i32* %argmem
+	%v = load i32, i32* %argmem
 	ret i32 %v
 }
 ; CHECK-LABEL: define internal x86_thiscallcc i32 @unused_this(i32* %this, i32* inalloca %argmem)
diff --git a/test/Transforms/DeadArgElim/variadic_safety.ll b/test/Transforms/DeadArgElim/variadic_safety.ll
index 15f57bcfdcb8..2dac2f9180ed 100644
--- a/test/Transforms/DeadArgElim/variadic_safety.ll
+++ b/test/Transforms/DeadArgElim/variadic_safety.ll
@@ -17,9 +17,9 @@ define internal i32 @va_func(i32 %a, i32 %b, ...) {
 define i32 @call_va(i32 %in) {
   %stacked = alloca i32
   store i32 42, i32* %stacked
-  %res = call i32(i32, i32, ...)* @va_func(i32 %in, i32 %in, [6 x i32] undef, i32* byval %stacked)
+  %res = call i32(i32, i32, ...) @va_func(i32 %in, i32 %in, [6 x i32] undef, i32* byval %stacked)
   ret i32 %res
-; CHECK: call i32 (i32, i32, ...)* @va_func(i32 undef, i32 %in, [6 x i32] undef, i32* byval %stacked)
+; CHECK: call i32 (i32, i32, ...) @va_func(i32 undef, i32 %in, [6 x i32] undef, i32* byval %stacked)
 }
 
 define internal i32 @va_deadret_func(i32 %a, i32 %b, ...) {
@@ -32,7 +32,7 @@ define internal i32 @va_deadret_func(i32 %a, i32 %b, ...) {
 define void @call_deadret(i32 %in) {
   %stacked = alloca i32
   store i32 42, i32* %stacked
-  call i32 (i32, i32, ...)* @va_deadret_func(i32 undef, i32 %in, [6 x i32] undef, i32* byval %stacked)
+  call i32 (i32, i32, ...) @va_deadret_func(i32 undef, i32 %in, [6 x i32] undef, i32* byval %stacked)
   ret void
-; CHECK: call void (i32, i32, ...)* @va_deadret_func(i32 undef, i32 undef, [6 x i32] undef, i32* byval %stacked)
+; CHECK: call void (i32, i32, ...) @va_deadret_func(i32 undef, i32 undef, [6 x i32] undef, i32* byval %stacked)
 }
diff --git a/test/Transforms/DeadStoreElimination/2011-03-25-DSEMiscompile.ll b/test/Transforms/DeadStoreElimination/2011-03-25-DSEMiscompile.ll
index 39d53584dc37..7746ccee5218 100644
--- a/test/Transforms/DeadStoreElimination/2011-03-25-DSEMiscompile.ll
+++ b/test/Transforms/DeadStoreElimination/2011-03-25-DSEMiscompile.ll
@@ -11,10 +11,10 @@ define ghccc void @Func1(i32* noalias %Arg1, i32* noalias %Arg2, i32* %Arg3, i32
 entry:
   store i32 add (i32 ptrtoint ([0 x i32]* @A to i32), i32 1), i32* %Arg2
 ; CHECK: store i32 add (i32 ptrtoint ([0 x i32]* @A to i32), i32 1), i32* %Arg2
-  %ln2gz = getelementptr i32* %Arg1, i32 14
+  %ln2gz = getelementptr i32, i32* %Arg1, i32 14
   %ln2gA = bitcast i32* %ln2gz to double*
-  %ln2gB = load double* %ln2gA
-  %ln2gD = getelementptr i32* %Arg2, i32 -3
+  %ln2gB = load double, double* %ln2gA
+  %ln2gD = getelementptr i32, i32* %Arg2, i32 -3
   %ln2gE = bitcast i32* %ln2gD to double*
   store double %ln2gB, double* %ln2gE
 ; CHECK: store double %ln2gB, double* %ln2gE
diff --git a/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll b/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll
index 95253f6570b5..7e46d28a9c47 100644
--- a/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll
+++ b/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll
@@ -10,11 +10,11 @@ define void @_Z3foov(%"class.std::auto_ptr"* noalias nocapture sret %agg.result)
 _ZNSt8auto_ptrIiED1Ev.exit:
   %temp.lvalue = alloca %"class.std::auto_ptr", align 8
   call void @_Z3barv(%"class.std::auto_ptr"* sret %temp.lvalue)
-  %_M_ptr.i.i = getelementptr inbounds %"class.std::auto_ptr"* %temp.lvalue, i64 0, i32 0
-  %tmp.i.i = load i32** %_M_ptr.i.i, align 8
+  %_M_ptr.i.i = getelementptr inbounds %"class.std::auto_ptr", %"class.std::auto_ptr"* %temp.lvalue, i64 0, i32 0
+  %tmp.i.i = load i32*, i32** %_M_ptr.i.i, align 8
 ; CHECK-NOT: store i32* null
   store i32* null, i32** %_M_ptr.i.i, align 8
-  %_M_ptr.i.i4 = getelementptr inbounds %"class.std::auto_ptr"* %agg.result, i64 0, i32 0
+  %_M_ptr.i.i4 = getelementptr inbounds %"class.std::auto_ptr", %"class.std::auto_ptr"* %agg.result, i64 0, i32 0
   store i32* %tmp.i.i, i32** %_M_ptr.i.i4, align 8
 ; CHECK: ret void
   ret void
diff --git a/test/Transforms/DeadStoreElimination/2011-09-06-MemCpy.ll b/test/Transforms/DeadStoreElimination/2011-09-06-MemCpy.ll
index 22b87864c063..d30e9a2e6c1f 100644
--- a/test/Transforms/DeadStoreElimination/2011-09-06-MemCpy.ll
+++ b/test/Transforms/DeadStoreElimination/2011-09-06-MemCpy.ll
@@ -68,13 +68,13 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
 define void @_ZSt9iter_swapIPSt4pairIPN4llvm10BasicBlockEjES5_EvT_T0_(%struct.pair.162* %__a, %struct.pair.162* %__b) nounwind uwtable inlinehint {
 entry:
   %memtmp = alloca %struct.pair.162, align 8
-  %0 = getelementptr inbounds %struct.pair.162* %memtmp, i64 0, i32 0
-  %1 = getelementptr inbounds %struct.pair.162* %__a, i64 0, i32 0
-  %2 = load %struct.BasicBlock** %1, align 8
+  %0 = getelementptr inbounds %struct.pair.162, %struct.pair.162* %memtmp, i64 0, i32 0
+  %1 = getelementptr inbounds %struct.pair.162, %struct.pair.162* %__a, i64 0, i32 0
+  %2 = load %struct.BasicBlock*, %struct.BasicBlock** %1, align 8
   store %struct.BasicBlock* %2, %struct.BasicBlock** %0, align 8
-  %3 = getelementptr inbounds %struct.pair.162* %memtmp, i64 0, i32 1
-  %4 = getelementptr inbounds %struct.pair.162* %__a, i64 0, i32 1
-  %5 = load i32* %4, align 4
+  %3 = getelementptr inbounds %struct.pair.162, %struct.pair.162* %memtmp, i64 0, i32 1
+  %4 = getelementptr inbounds %struct.pair.162, %struct.pair.162* %__a, i64 0, i32 1
+  %5 = load i32, i32* %4, align 4
   store i32 %5, i32* %3, align 8
   %6 = bitcast %struct.pair.162* %__a to i8*
   %7 = bitcast %struct.pair.162* %__b to i8*
diff --git a/test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll b/test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll
index 968d608c67ed..de7a4ccd867c 100644
--- a/test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll
+++ b/test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll
@@ -10,11 +10,11 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 define void @write24to28(i32* nocapture %p) nounwind uwtable ssp {
 ; CHECK-LABEL: @write24to28(
 entry:
-  %arrayidx0 = getelementptr inbounds i32* %p, i64 1
+  %arrayidx0 = getelementptr inbounds i32, i32* %p, i64 1
   %p3 = bitcast i32* %arrayidx0 to i8*
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %p3, i8 0, i64 24, i32 4, i1 false)
   call void @llvm.memset.p0i8.i64(i8* %p3, i8 0, i64 28, i32 4, i1 false)
-  %arrayidx1 = getelementptr inbounds i32* %p, i64 7
+  %arrayidx1 = getelementptr inbounds i32, i32* %p, i64 7
   store i32 1, i32* %arrayidx1, align 4
   ret void
 }
@@ -25,7 +25,7 @@ entry:
   %p3 = bitcast i32* %p to i8*
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %p3, i8 0, i64 28, i32 4, i1 false)
   call void @llvm.memset.p0i8.i64(i8* %p3, i8 0, i64 32, i32 4, i1 false)
-  %arrayidx1 = getelementptr inbounds i32* %p, i64 7
+  %arrayidx1 = getelementptr inbounds i32, i32* %p, i64 7
   store i32 1, i32* %arrayidx1, align 4
   ret void
 }
@@ -36,7 +36,7 @@ entry:
   %p3 = bitcast i32* %p to i8*
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %p3, i8 0, i64 32, i32 16, i1 false)
   call void @llvm.memset.p0i8.i64(i8* %p3, i8 0, i64 32, i32 16, i1 false)
-  %arrayidx1 = getelementptr inbounds i32* %p, i64 7
+  %arrayidx1 = getelementptr inbounds i32, i32* %p, i64 7
   store i32 1, i32* %arrayidx1, align 4
   ret void
 }
@@ -47,7 +47,7 @@ entry:
   %0 = bitcast %struct.vec2plusi* %p to i8*
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.vec2plusi* @glob2 to i8*), i64 32, i32 16, i1 false)
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.vec2plusi* @glob2 to i8*), i64 36, i32 16, i1 false)
-  %c = getelementptr inbounds %struct.vec2plusi* %p, i64 0, i32 2
+  %c = getelementptr inbounds %struct.vec2plusi, %struct.vec2plusi* %p, i64 0, i32 2
   store i32 1, i32* %c, align 4
   ret void
 }
@@ -58,7 +58,7 @@ entry:
   %0 = bitcast %struct.vec2* %p to i8*
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.vec2* @glob1 to i8*), i64 16, i32 16, i1 false)
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.vec2* @glob1 to i8*), i64 32, i32 16, i1 false)
-  %c = getelementptr inbounds %struct.vec2* %p, i64 0, i32 1
+  %c = getelementptr inbounds %struct.vec2, %struct.vec2* %p, i64 0, i32 1
   store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32>* %c, align 4
   ret void
 }
@@ -69,7 +69,7 @@ entry:
   %0 = bitcast %struct.vec2* %p to i8*
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.vec2* @glob1 to i8*), i64 32, i32 16, i1 false)
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.vec2* @glob1 to i8*), i64 32, i32 16, i1 false)
-  %arrayidx1 = getelementptr inbounds %struct.vec2* %p, i64 0, i32 0, i64 7
+  %arrayidx1 = getelementptr inbounds %struct.vec2, %struct.vec2* %p, i64 0, i32 0, i64 7
   store i32 1, i32* %arrayidx1, align 4
   ret void
 }
@@ -84,12 +84,12 @@ declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
 define void @cpu_lwp_fork(%struct.trapframe* %md_regs, i64 %pcb_rsp0) nounwind uwtable noinline ssp {
 entry:
   %0 = inttoptr i64 %pcb_rsp0 to %struct.trapframe*
-  %add.ptr = getelementptr inbounds %struct.trapframe* %0, i64 -1
+  %add.ptr = getelementptr inbounds %struct.trapframe, %struct.trapframe* %0, i64 -1
   %1 = bitcast %struct.trapframe* %add.ptr to i8*
   %2 = bitcast %struct.trapframe* %md_regs to i8*
 ; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 24, i32 1, i1 false)
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 24, i32 1, i1 false)
-  %tf_trapno = getelementptr inbounds %struct.trapframe* %0, i64 -1, i32 1
+  %tf_trapno = getelementptr inbounds %struct.trapframe, %struct.trapframe* %0, i64 -1, i32 1
   store i64 3, i64* %tf_trapno, align 8
   ret void
 }
diff --git a/test/Transforms/DeadStoreElimination/PartialStore.ll b/test/Transforms/DeadStoreElimination/PartialStore.ll
index 80c2bfae846e..d85b4de0ab98 100644
--- a/test/Transforms/DeadStoreElimination/PartialStore.ll
+++ b/test/Transforms/DeadStoreElimination/PartialStore.ll
@@ -30,8 +30,8 @@ define i32 @test3(double %__x) {
   %__u = alloca { [3 x i32] }
   %tmp.1 = bitcast { [3 x i32] }* %__u to double*
   store double %__x, double* %tmp.1
-  %tmp.4 = getelementptr { [3 x i32] }* %__u, i32 0, i32 0, i32 1
-  %tmp.5 = load i32* %tmp.4
+  %tmp.4 = getelementptr { [3 x i32] }, { [3 x i32] }* %__u, i32 0, i32 0, i32 1
+  %tmp.5 = load i32, i32* %tmp.4
   %tmp.6 = icmp slt i32 %tmp.5, 0
   %tmp.7 = zext i1 %tmp.6 to i32
   ret i32 %tmp.7
@@ -44,7 +44,7 @@ define void @test4(i8* %P) {
 ; CHECK-NEXT: store double
 
   store i8 19, i8* %P  ;; dead
-  %A = getelementptr i8* %P, i32 3
+  %A = getelementptr i8, i8* %P, i32 3
 
   store i8 42, i8* %A  ;; dead
 
@@ -58,7 +58,7 @@ declare void @test5a(i32*)
 define void @test5(i32 %i) nounwind ssp {
   %A = alloca i32
   %B = bitcast i32* %A to i8*
-  %C = getelementptr i8* %B, i32 %i
+  %C = getelementptr i8, i8* %B, i32 %i
   store i8 10, i8* %C        ;; Dead store to variable index.
   store i32 20, i32* %A
 
@@ -74,7 +74,7 @@ declare void @test5a_as1(i32*)
 define void @test5_addrspacecast(i32 %i) nounwind ssp {
   %A = alloca i32
   %B = addrspacecast i32* %A to i8 addrspace(1)*
-  %C = getelementptr i8 addrspace(1)* %B, i32 %i
+  %C = getelementptr i8, i8 addrspace(1)* %B, i32 %i
   store i8 10, i8 addrspace(1)* %C        ;; Dead store to variable index.
   store i32 20, i32* %A
 
diff --git a/test/Transforms/DeadStoreElimination/atomic.ll b/test/Transforms/DeadStoreElimination/atomic.ll
index af303fa983ee..79beee803e4e 100644
--- a/test/Transforms/DeadStoreElimination/atomic.ll
+++ b/test/Transforms/DeadStoreElimination/atomic.ll
@@ -23,28 +23,6 @@ define void @test1() {
   ret void
 }
 
-; DSE across seq_cst load (allowed)
-define i32 @test2() {
-; CHECK-LABEL: test2
-; CHECK-NOT: store i32 0
-; CHECK: store i32 1
-  store i32 0, i32* @x
-  %x = load atomic i32* @y seq_cst, align 4
-  store i32 1, i32* @x
-  ret i32 %x
-}
-
-; DSE across seq_cst store (allowed)
-define void @test3() {
-; CHECK-LABEL: test3
-; CHECK-NOT: store i32 0
-; CHECK: store atomic i32 2
-  store i32 0, i32* @x
-  store atomic i32 2, i32* @y seq_cst, align 4
-  store i32 1, i32* @x
-  ret void
-}
-
 ; DSE remove unordered store (allowed)
 define void @test4() {
 ; CHECK-LABEL: test4
@@ -69,7 +47,7 @@ define void @test6() {
 ; CHECK-LABEL: test6
 ; CHECK-NOT: store
 ; CHECK: ret void
-  %x = load atomic i32* @x unordered, align 4
+  %x = load atomic i32, i32* @x unordered, align 4
   store atomic i32 %x, i32* @x unordered, align 4
   ret void
 }
@@ -93,7 +71,7 @@ define i32 @test8() {
   %a = alloca i32
   call void @randomop(i32* %a)
   store i32 0, i32* %a, align 4
-  %x = load atomic i32* @x seq_cst, align 4
+  %x = load atomic i32, i32* @x seq_cst, align 4
   ret i32 %x
 }
 
@@ -103,7 +81,7 @@ define i32 @test9() {
 ; CHECK-NOT: store i32 0
 ; CHECK: store i32 1
   store i32 0, i32* @x
-  %x = load atomic i32* @y monotonic, align 4
+  %x = load atomic i32, i32* @y monotonic, align 4
   store i32 1, i32* @x
   ret i32 %x
 }
@@ -125,7 +103,7 @@ define i32 @test11() {
 ; CHECK: store atomic i32 0
 ; CHECK: store atomic i32 1
   store atomic i32 0, i32* @x monotonic, align 4
-  %x = load atomic i32* @y monotonic, align 4
+  %x = load atomic i32, i32* @y monotonic, align 4
   store atomic i32 1, i32* @x monotonic, align 4
   ret i32 %x
 }
@@ -141,30 +119,6 @@ define void @test12() {
   ret void
 }
 
-; DSE is allowed across a pair of an atomic read and then write.
-define i32 @test13() {
-; CHECK-LABEL: test13
-; CHECK-NOT: store i32 0
-; CHECK: store i32 1
-  store i32 0, i32* @x
-  %x = load atomic i32* @y seq_cst, align 4
-  store atomic i32 %x, i32* @y seq_cst, align 4
-  store i32 1, i32* @x
-  ret i32 %x
-}
-
-; Same if it is acquire-release instead of seq_cst/seq_cst
-define i32 @test14() {
-; CHECK-LABEL: test14
-; CHECK-NOT: store i32 0
-; CHECK: store i32 1
-  store i32 0, i32* @x
-  %x = load atomic i32* @y acquire, align 4
-  store atomic i32 %x, i32* @y release, align 4
-  store i32 1, i32* @x
-  ret i32 %x
-}
-
 ; But DSE is not allowed across a release-acquire pair.
 define i32 @test15() {
 ; CHECK-LABEL: test15
@@ -172,7 +126,7 @@ define i32 @test15() {
 ; CHECK: store i32 1
   store i32 0, i32* @x
   store atomic i32 0, i32* @y release, align 4
-  %x = load atomic i32* @y acquire, align 4
+  %x = load atomic i32, i32* @y acquire, align 4
   store i32 1, i32* @x
   ret i32 %x
 }
diff --git a/test/Transforms/DeadStoreElimination/const-pointers.ll b/test/Transforms/DeadStoreElimination/const-pointers.ll
index 3e772d79c70a..e4403edbed20 100644
--- a/test/Transforms/DeadStoreElimination/const-pointers.ll
+++ b/test/Transforms/DeadStoreElimination/const-pointers.ll
@@ -6,10 +6,10 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 @g = global i32 42
 
 define void @test1(%t* noalias %pp) {
-  %p = getelementptr inbounds %t* %pp, i32 0, i32 0
+  %p = getelementptr inbounds %t, %t* %pp, i32 0, i32 0
 
   store i32 1, i32* %p; <-- This is dead
-  %x = load i32* inttoptr (i32 12345 to i32*)
+  %x = load i32, i32* inttoptr (i32 12345 to i32*)
   store i32 %x, i32* %p
   ret void
 ; CHECK-LABEL: define void @test1(
@@ -30,7 +30,7 @@ define void @test3() {
 
 define void @test4(i32* %p) {
   store i32 1, i32* %p
-  %x = load i32* @g; <-- %p and @g could alias
+  %x = load i32, i32* @g; <-- %p and @g could alias
   store i32 %x, i32* %p
   ret void
 ; CHECK-LABEL: define void @test4(
diff --git a/test/Transforms/DeadStoreElimination/crash.ll b/test/Transforms/DeadStoreElimination/crash.ll
index 148695fcedbd..78cb842e60ed 100644
--- a/test/Transforms/DeadStoreElimination/crash.ll
+++ b/test/Transforms/DeadStoreElimination/crash.ll
@@ -28,14 +28,14 @@ bb:                                               ; preds = %bb, %entry
 define fastcc i32 @test2() nounwind ssp {
 bb14:                                             ; preds = %bb4
   %0 = bitcast i8* undef to i8**                  ; <i8**> [#uses=1]
-  %1 = getelementptr inbounds i8** %0, i64 undef  ; <i8**> [#uses=1]
+  %1 = getelementptr inbounds i8*, i8** %0, i64 undef  ; <i8**> [#uses=1]
   %2 = bitcast i8** %1 to i16*                    ; <i16*> [#uses=2]
-  %3 = getelementptr inbounds i16* %2, i64 undef  ; <i16*> [#uses=1]
+  %3 = getelementptr inbounds i16, i16* %2, i64 undef  ; <i16*> [#uses=1]
   %4 = bitcast i16* %3 to i8*                     ; <i8*> [#uses=1]
-  %5 = getelementptr inbounds i8* %4, i64 undef   ; <i8*> [#uses=1]
-  %6 = getelementptr inbounds i16* %2, i64 undef  ; <i16*> [#uses=1]
+  %5 = getelementptr inbounds i8, i8* %4, i64 undef   ; <i8*> [#uses=1]
+  %6 = getelementptr inbounds i16, i16* %2, i64 undef  ; <i16*> [#uses=1]
   store i16 undef, i16* %6, align 2
-  %7 = getelementptr inbounds i8* %5, i64 undef   ; <i8*> [#uses=1]
+  %7 = getelementptr inbounds i8, i8* %5, i64 undef   ; <i8*> [#uses=1]
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %7, i8* undef, i64 undef, i32 1, i1 false)
   unreachable
 }
@@ -49,8 +49,8 @@ entry:
   ret i32 0
   
 dead:
-  %P2 = getelementptr i32 *%P2, i32 52
-  %Q2 = getelementptr i32 *%Q2, i32 52
+  %P2 = getelementptr i32, i32 *%P2, i32 52
+  %Q2 = getelementptr i32, i32 *%Q2, i32 52
   store i32 4, i32* %P2
   store i32 4, i32* %Q2
   br label %dead
@@ -65,9 +65,9 @@ dead:
 define void @test4(%struct.f393a00_2__windmill* %a, %struct.f393a00_2__windmill* %b) {
 entry:
 	%t = alloca %struct.f393a00_2__windmill		; <%struct.f393a00_2__windmill*> [#uses=1]
-	%0 = getelementptr %struct.f393a00_2__windmill* %t, i32 0, i32 0, i32 0		; <%struct.ada__tags__dispatch_table**> [#uses=1]
-	%1 = load %struct.ada__tags__dispatch_table** null, align 4		; <%struct.ada__tags__dispatch_table*> [#uses=1]
-	%2 = load %struct.ada__tags__dispatch_table** %0, align 8		; <%struct.ada__tags__dispatch_table*> [#uses=1]
+	%0 = getelementptr %struct.f393a00_2__windmill, %struct.f393a00_2__windmill* %t, i32 0, i32 0, i32 0		; <%struct.ada__tags__dispatch_table**> [#uses=1]
+	%1 = load %struct.ada__tags__dispatch_table*, %struct.ada__tags__dispatch_table** null, align 4		; <%struct.ada__tags__dispatch_table*> [#uses=1]
+	%2 = load %struct.ada__tags__dispatch_table*, %struct.ada__tags__dispatch_table** %0, align 8		; <%struct.ada__tags__dispatch_table*> [#uses=1]
 	store %struct.ada__tags__dispatch_table* %2, %struct.ada__tags__dispatch_table** null, align 4
 	store %struct.ada__tags__dispatch_table* %1, %struct.ada__tags__dispatch_table** null, align 4
 	ret void
diff --git a/test/Transforms/DeadStoreElimination/cs-cs-aliasing.ll b/test/Transforms/DeadStoreElimination/cs-cs-aliasing.ll
index 8953f9ce0834..30bb96fa2b4a 100644
--- a/test/Transforms/DeadStoreElimination/cs-cs-aliasing.ll
+++ b/test/Transforms/DeadStoreElimination/cs-cs-aliasing.ll
@@ -22,18 +22,18 @@ define weak_odr zeroext i1 @test() #2 align 2 {
 bb:
   %tmp = alloca %class.basic_string, align 8
   %tmp1 = alloca %class.basic_string, align 8
-  %tmp3 = getelementptr inbounds %class.basic_string* %tmp, i64 0, i32 0, i32 0, i32 2
+  %tmp3 = getelementptr inbounds %class.basic_string, %class.basic_string* %tmp, i64 0, i32 0, i32 0, i32 2
   %tmp4 = bitcast %union.anon* %tmp3 to i8*
-  %tmp5 = getelementptr inbounds %class.basic_string* %tmp, i64 0, i32 0, i32 0, i32 0, i32 0
-  %tmp6 = getelementptr inbounds %class.basic_string* %tmp, i64 0, i32 0, i32 0, i32 1
-  %tmp7 = getelementptr inbounds i8* %tmp4, i64 1
+  %tmp5 = getelementptr inbounds %class.basic_string, %class.basic_string* %tmp, i64 0, i32 0, i32 0, i32 0, i32 0
+  %tmp6 = getelementptr inbounds %class.basic_string, %class.basic_string* %tmp, i64 0, i32 0, i32 0, i32 1
+  %tmp7 = getelementptr inbounds i8, i8* %tmp4, i64 1
   %tmp8 = bitcast %class.basic_string* %tmp to i8*
   %tmp9 = bitcast i64 0 to i64
-  %tmp10 = getelementptr inbounds %class.basic_string* %tmp1, i64 0, i32 0, i32 0, i32 2
+  %tmp10 = getelementptr inbounds %class.basic_string, %class.basic_string* %tmp1, i64 0, i32 0, i32 0, i32 2
   %tmp11 = bitcast %union.anon* %tmp10 to i8*
-  %tmp12 = getelementptr inbounds %class.basic_string* %tmp1, i64 0, i32 0, i32 0, i32 0, i32 0
-  %tmp13 = getelementptr inbounds %class.basic_string* %tmp1, i64 0, i32 0, i32 0, i32 1
-  %tmp14 = getelementptr inbounds i8* %tmp11, i64 1
+  %tmp12 = getelementptr inbounds %class.basic_string, %class.basic_string* %tmp1, i64 0, i32 0, i32 0, i32 0, i32 0
+  %tmp13 = getelementptr inbounds %class.basic_string, %class.basic_string* %tmp1, i64 0, i32 0, i32 0, i32 1
+  %tmp14 = getelementptr inbounds i8, i8* %tmp11, i64 1
   %tmp15 = bitcast %class.basic_string* %tmp1 to i8*
   br label %_ZN12basic_stringIcSt11char_traitsIcESaIcEEC2EPKcRKS2_.exit
 
diff --git a/test/Transforms/DeadStoreElimination/dominate.ll b/test/Transforms/DeadStoreElimination/dominate.ll
index 38cf1a066dae..638992bae729 100644
--- a/test/Transforms/DeadStoreElimination/dominate.ll
+++ b/test/Transforms/DeadStoreElimination/dominate.ll
@@ -5,7 +5,7 @@ declare void @bar()
 define void @foo() {
 bb1:
   %memtmp3.i = alloca [21 x i8], align 1
-  %0 = getelementptr inbounds [21 x i8]* %memtmp3.i, i64 0, i64 0
+  %0 = getelementptr inbounds [21 x i8], [21 x i8]* %memtmp3.i, i64 0, i64 0
   br label %bb3
 
 bb2:
diff --git a/test/Transforms/DeadStoreElimination/free.ll b/test/Transforms/DeadStoreElimination/free.ll
index 1d273d67a501..6b69ec860202 100644
--- a/test/Transforms/DeadStoreElimination/free.ll
+++ b/test/Transforms/DeadStoreElimination/free.ll
@@ -10,7 +10,7 @@ declare noalias i8* @malloc(i64)
 ; CHECK-NEXT: @free
 ; CHECK-NEXT: ret void
 define void @test(i32* %Q, i32* %P) {
-        %DEAD = load i32* %Q            ; <i32> [#uses=1]
+        %DEAD = load i32, i32* %Q            ; <i32> [#uses=1]
         store i32 %DEAD, i32* %P
         %1 = bitcast i32* %P to i8*
         tail call void @free(i8* %1)
@@ -22,7 +22,7 @@ define void @test(i32* %Q, i32* %P) {
 ; CHECK-NEXT: @free
 ; CHECK-NEXT: ret void
 define void @test2({i32, i32}* %P) {
-	%Q = getelementptr {i32, i32} *%P, i32 0, i32 1
+	%Q = getelementptr {i32, i32}, {i32, i32} *%P, i32 0, i32 1
 	store i32 4, i32* %Q
         %1 = bitcast {i32, i32}* %P to i8*
         tail call void @free(i8* %1)
@@ -35,7 +35,7 @@ define void @test2({i32, i32}* %P) {
 define void @test3() {
   %m = call i8* @malloc(i64 24)
   store i8 0, i8* %m
-  %m1 = getelementptr i8* %m, i64 1
+  %m1 = getelementptr i8, i8* %m, i64 1
   store i8 1, i8* %m1
   call void @free(i8* %m)
   ret void
diff --git a/test/Transforms/DeadStoreElimination/inst-limits.ll b/test/Transforms/DeadStoreElimination/inst-limits.ll
index 3ef560723387..54e41c8b413b 100644
--- a/test/Transforms/DeadStoreElimination/inst-limits.ll
+++ b/test/Transforms/DeadStoreElimination/inst-limits.ll
@@ -118,7 +118,7 @@ entry:
 
   ; Insert a meaningless dbg.value intrinsic; it should have no
   ; effect on the working of DSE in any way.
-  call void @llvm.dbg.value(metadata i32* undef, i64 0, metadata !10, metadata !{})
+  call void @llvm.dbg.value(metadata i32* undef, i64 0, metadata !10, metadata !DIExpression()), !dbg !DILocation(scope: !4)
 
   ; CHECK:  store i32 -1, i32* @x, align 4
   store i32 -1, i32* @x, align 4
@@ -245,18 +245,18 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!11, !13}
 
-!0 = !{!"0x11\004\00clang version 3.4\001\00\000\00\000", !1, !2, !2, !3, !9, !2} ; [ DW_TAG_compile_unit ] [/home/tmp/test.c] [DW_LANG_C99]
-!1 = !{!"test.c", !"/home/tmp"}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.c", directory: "/home/tmp")
+!2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00test_within_limit\00test_within_limit\00\003\000\001\000\006\00256\000\004", !1, !5, !6, null, i32 ()* @test_within_limit, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 4] [test]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/home/tmp/test.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "test_within_limit", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !1, scope: !5, type: !6, function: i32 ()* @test_within_limit, variables: !2)
+!5 = !DIFile(filename: "test.c", directory: "/home/tmp")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !9 = !{!10}
-!10 = !{!"0x34\00x\00x\00\001\000\001", null, !5, !8, i32* @x, null} ; [ DW_TAG_variable ] [x] [line 1] [def]
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", scope: !4, type: !8)
 !11 = !{i32 2, !"Dwarf Version", i32 4}
 !12 = !{i32* undef}
 
-!13 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/DeadStoreElimination/libcalls.ll b/test/Transforms/DeadStoreElimination/libcalls.ll
index 65396945bf65..8afa148a58b7 100644
--- a/test/Transforms/DeadStoreElimination/libcalls.ll
+++ b/test/Transforms/DeadStoreElimination/libcalls.ll
@@ -4,7 +4,7 @@ declare i8* @strcpy(i8* %dest, i8* %src) nounwind
 define void @test1(i8* %src) {
 ; CHECK-LABEL: @test1(
   %B = alloca [16 x i8]
-  %dest = getelementptr inbounds [16 x i8]* %B, i64 0, i64 0
+  %dest = getelementptr inbounds [16 x i8], [16 x i8]* %B, i64 0, i64 0
 ; CHECK-NOT: @strcpy
   %call = call i8* @strcpy(i8* %dest, i8* %src)
 ; CHECK: ret void
@@ -15,7 +15,7 @@ declare i8* @strncpy(i8* %dest, i8* %src, i32 %n) nounwind
 define void @test2(i8* %src) {
 ; CHECK-LABEL: @test2(
   %B = alloca [16 x i8]
-  %dest = getelementptr inbounds [16 x i8]* %B, i64 0, i64 0
+  %dest = getelementptr inbounds [16 x i8], [16 x i8]* %B, i64 0, i64 0
 ; CHECK-NOT: @strncpy
   %call = call i8* @strncpy(i8* %dest, i8* %src, i32 12)
 ; CHECK: ret void
@@ -26,7 +26,7 @@ declare i8* @strcat(i8* %dest, i8* %src) nounwind
 define void @test3(i8* %src) {
 ; CHECK-LABEL: @test3(
   %B = alloca [16 x i8]
-  %dest = getelementptr inbounds [16 x i8]* %B, i64 0, i64 0
+  %dest = getelementptr inbounds [16 x i8], [16 x i8]* %B, i64 0, i64 0
 ; CHECK-NOT: @strcat
   %call = call i8* @strcat(i8* %dest, i8* %src)
 ; CHECK: ret void
@@ -37,7 +37,7 @@ declare i8* @strncat(i8* %dest, i8* %src, i32 %n) nounwind
 define void @test4(i8* %src) {
 ; CHECK-LABEL: @test4(
   %B = alloca [16 x i8]
-  %dest = getelementptr inbounds [16 x i8]* %B, i64 0, i64 0
+  %dest = getelementptr inbounds [16 x i8], [16 x i8]* %B, i64 0, i64 0
 ; CHECK-NOT: @strncat
   %call = call i8* @strncat(i8* %dest, i8* %src, i32 12)
 ; CHECK: ret void
@@ -47,10 +47,10 @@ define void @test4(i8* %src) {
 define void @test5(i8* nocapture %src) {
 ; CHECK-LABEL: @test5(
   %dest = alloca [100 x i8], align 16
-  %arraydecay = getelementptr inbounds [100 x i8]* %dest, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [100 x i8], [100 x i8]* %dest, i64 0, i64 0
   %call = call i8* @strcpy(i8* %arraydecay, i8* %src)
 ; CHECK: %call = call i8* @strcpy
-  %arrayidx = getelementptr inbounds i8* %call, i64 10
+  %arrayidx = getelementptr inbounds i8, i8* %call, i64 10
   store i8 97, i8* %arrayidx, align 1
   ret void
 }
@@ -59,7 +59,7 @@ declare void @user(i8* %p)
 define void @test6(i8* %src) {
 ; CHECK-LABEL: @test6(
   %B = alloca [16 x i8]
-  %dest = getelementptr inbounds [16 x i8]* %B, i64 0, i64 0
+  %dest = getelementptr inbounds [16 x i8], [16 x i8]* %B, i64 0, i64 0
 ; CHECK: @strcpy
   %call = call i8* @strcpy(i8* %dest, i8* %src)
 ; CHECK: @user
diff --git a/test/Transforms/DeadStoreElimination/lifetime.ll b/test/Transforms/DeadStoreElimination/lifetime.ll
index 7fe7fbfa7478..305c916dc02b 100644
--- a/test/Transforms/DeadStoreElimination/lifetime.ll
+++ b/test/Transforms/DeadStoreElimination/lifetime.ll
@@ -23,7 +23,7 @@ define void @test1() {
 
 define void @test2(i32* %P) {
 ; CHECK: test2
-  %Q = getelementptr i32* %P, i32 1
+  %Q = getelementptr i32, i32* %P, i32 1
   %R = bitcast i32* %Q to i8*
   call void @llvm.lifetime.start(i64 4, i8* %R)
 ; CHECK: lifetime.start
diff --git a/test/Transforms/DeadStoreElimination/no-targetdata.ll b/test/Transforms/DeadStoreElimination/no-targetdata.ll
index 25395330bf37..f9262ed54b3f 100644
--- a/test/Transforms/DeadStoreElimination/no-targetdata.ll
+++ b/test/Transforms/DeadStoreElimination/no-targetdata.ll
@@ -12,7 +12,7 @@ entry:
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64
 ; CHECK: ret void
 
-  %arrayidx = getelementptr i8* %buf, i64 18
+  %arrayidx = getelementptr i8, i8* %buf, i64 18
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %arrayidx, i8* %buf, i64 18, i32 1, i1 false)
   store i8 1, i8* %arrayidx, align 1
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %buf, i8* %arrayidx, i64 18, i32 1, i1 false)
diff --git a/test/Transforms/DeadStoreElimination/pr11390.ll b/test/Transforms/DeadStoreElimination/pr11390.ll
index f63aa1eb8aae..faf3b8b47a92 100644
--- a/test/Transforms/DeadStoreElimination/pr11390.ll
+++ b/test/Transforms/DeadStoreElimination/pr11390.ll
@@ -18,12 +18,12 @@ entry:
 
 if.end:                                           ; preds = %entry
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %call4, i8* %name, i64 %call, i32 1, i1 false)
-  %arrayidx = getelementptr inbounds i8* %call4, i64 %call
+  %arrayidx = getelementptr inbounds i8, i8* %call4, i64 %call
   store i8 46, i8* %arrayidx, align 1
 ; CHECK: store i8 46
-  %add.ptr5 = getelementptr inbounds i8* %call4, i64 %add
+  %add.ptr5 = getelementptr inbounds i8, i8* %call4, i64 %add
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %add.ptr5, i8* %domain, i64 %call1, i32 1, i1 false)
-  %arrayidx8 = getelementptr inbounds i8* %call4, i64 %add2
+  %arrayidx8 = getelementptr inbounds i8, i8* %call4, i64 %add2
   store i8 0, i8* %arrayidx8, align 1
   br label %return
 
diff --git a/test/Transforms/DeadStoreElimination/simple.ll b/test/Transforms/DeadStoreElimination/simple.ll
index 1e813852b04c..2ffe0539098e 100644
--- a/test/Transforms/DeadStoreElimination/simple.ll
+++ b/test/Transforms/DeadStoreElimination/simple.ll
@@ -3,10 +3,10 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1
 
 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
-declare i8* @llvm.init.trampoline(i8*, i8*, i8*)
+declare void @llvm.init.trampoline(i8*, i8*, i8*)
 
 define void @test1(i32* %Q, i32* %P) {
-        %DEAD = load i32* %Q
+        %DEAD = load i32, i32* %Q
         store i32 %DEAD, i32* %P
         store i32 0, i32* %P
         ret void
@@ -31,17 +31,17 @@ define void @test2(i32 *%p, i32 *%q) {
 
 define i32 @test3(i32* %g_addr) nounwind {
 ; CHECK-LABEL: @test3(
-; CHECK: load i32* %g_addr
-  %g_value = load i32* %g_addr, align 4
+; CHECK: load i32, i32* %g_addr
+  %g_value = load i32, i32* %g_addr, align 4
   store i32 -1, i32* @g, align 4
   store i32 %g_value, i32* %g_addr, align 4
-  %tmp3 = load i32* @g, align 4
+  %tmp3 = load i32, i32* @g, align 4
   ret i32 %tmp3
 }
 
 
 define void @test4(i32* %Q) {
-        %a = load i32* %Q
+        %a = load i32, i32* %Q
         store volatile i32 %a, i32* %Q
         ret void
 ; CHECK-LABEL: @test4(
@@ -51,7 +51,7 @@ define void @test4(i32* %Q) {
 }
 
 define void @test5(i32* %Q) {
-        %a = load volatile i32* %Q
+        %a = load volatile i32, i32* %Q
         store i32 %a, i32* %Q
         ret void
 ; CHECK-LABEL: @test5(
@@ -87,7 +87,7 @@ define i32 @test8() {
         store i32 1234567, i32* %V
         %V2 = bitcast i32* %V to i8*
         store i8 0, i8* %V2
-        %X = load i32* %V
+        %X = load i32, i32* %V
         ret i32 %X
         
 ; CHECK-LABEL: @test8(
@@ -98,7 +98,7 @@ define i32 @test8() {
 ; Test for byval handling.
 %struct.x = type { i32, i32, i32, i32 }
 define void @test9(%struct.x* byval  %a) nounwind  {
-	%tmp2 = getelementptr %struct.x* %a, i32 0, i32 0
+	%tmp2 = getelementptr %struct.x, %struct.x* %a, i32 0, i32 0
 	store i32 1, i32* %tmp2, align 4
 	ret void
 ; CHECK-LABEL: @test9(
@@ -107,7 +107,7 @@ define void @test9(%struct.x* byval  %a) nounwind  {
 
 ; Test for inalloca handling.
 define void @test9_2(%struct.x* inalloca  %a) nounwind  {
-	%tmp2 = getelementptr %struct.x* %a, i32 0, i32 0
+	%tmp2 = getelementptr %struct.x, %struct.x* %a, i32 0, i32 0
 	store i32 1, i32* %tmp2, align 4
 	ret void
 ; CHECK-LABEL: @test9_2(
@@ -131,8 +131,8 @@ define void @test11() {
 ; CHECK-LABEL: @test11(
 	%storage = alloca [10 x i8], align 16		; <[10 x i8]*> [#uses=1]
 ; CHECK-NOT: alloca
-	%cast = getelementptr [10 x i8]* %storage, i32 0, i32 0		; <i8*> [#uses=1]
-	%tramp = call i8* @llvm.init.trampoline( i8* %cast, i8* bitcast (void ()* @test11f to i8*), i8* null )		; <i8*> [#uses=1]
+	%cast = getelementptr [10 x i8], [10 x i8]* %storage, i32 0, i32 0		; <i8*> [#uses=1]
+	call void @llvm.init.trampoline( i8* %cast, i8* bitcast (void ()* @test11f to i8*), i8* null )		; <i8*> [#uses=1]
 ; CHECK-NOT: trampoline
 	ret void
 ; CHECK: ret void
@@ -141,10 +141,10 @@ define void @test11() {
 
 ; PR2599 - load -> store to same address.
 define void @test12({ i32, i32 }* %x) nounwind  {
-	%tmp4 = getelementptr { i32, i32 }* %x, i32 0, i32 0
-	%tmp5 = load i32* %tmp4, align 4
-	%tmp7 = getelementptr { i32, i32 }* %x, i32 0, i32 1
-	%tmp8 = load i32* %tmp7, align 4
+	%tmp4 = getelementptr { i32, i32 }, { i32, i32 }* %x, i32 0, i32 0
+	%tmp5 = load i32, i32* %tmp4, align 4
+	%tmp7 = getelementptr { i32, i32 }, { i32, i32 }* %x, i32 0, i32 1
+	%tmp8 = load i32, i32* %tmp7, align 4
 	%tmp17 = sub i32 0, %tmp8
 	store i32 %tmp5, i32* %tmp4, align 4
 	store i32 %tmp17, i32* %tmp7, align 4
@@ -160,7 +160,7 @@ declare void @test13f()
 define i32* @test13() {
         %p = tail call i8* @malloc(i32 4)
         %P = bitcast i8* %p to i32*
-        %DEAD = load i32* %P
+        %DEAD = load i32, i32* %P
         %DEAD2 = add i32 %DEAD, 1
         store i32 %DEAD2, i32* %P
         call void @test13f( )
@@ -176,7 +176,7 @@ define i32 addrspace(1)* @test13_addrspacecast() {
   %p = tail call i8* @malloc(i32 4)
   %p.bc = bitcast i8* %p to i32*
   %P = addrspacecast i32* %p.bc to i32 addrspace(1)*
-  %DEAD = load i32 addrspace(1)* %P
+  %DEAD = load i32, i32 addrspace(1)* %P
   %DEAD2 = add i32 %DEAD, 1
   store i32 %DEAD2, i32 addrspace(1)* %P
   call void @test13f( )
@@ -195,7 +195,7 @@ declare noalias i8* @calloc(i32, i32)
 
 define void @test14(i32* %Q) {
         %P = alloca i32
-        %DEAD = load i32* %Q
+        %DEAD = load i32, i32* %Q
         store i32 %DEAD, i32* %P
         ret void
 
@@ -267,7 +267,7 @@ declare void @test19f({i32}* byval align 4 %P)
 
 define void @test19({i32} * nocapture byval align 4 %arg5) nounwind ssp {
 bb:
-  %tmp7 = getelementptr inbounds {i32}* %arg5, i32 0, i32 0
+  %tmp7 = getelementptr inbounds {i32}, {i32}* %arg5, i32 0, i32 0
   store i32 912, i32* %tmp7
   call void @test19f({i32}* byval align 4 %arg5)
   ret void
@@ -310,9 +310,9 @@ define void @test22(i1 %i, i32 %k, i32 %m) nounwind {
 declare noalias i8* @strdup(i8* nocapture) nounwind
 define noalias i8* @test23() nounwind uwtable ssp {
   %x = alloca [2 x i8], align 1
-  %arrayidx = getelementptr inbounds [2 x i8]* %x, i64 0, i64 0
+  %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* %x, i64 0, i64 0
   store i8 97, i8* %arrayidx, align 1
-  %arrayidx1 = getelementptr inbounds [2 x i8]* %x, i64 0, i64 1
+  %arrayidx1 = getelementptr inbounds [2 x i8], [2 x i8]* %x, i64 0, i64 1
   store i8 0, i8* %arrayidx1, align 1
   %call = call i8* @strdup(i8* %arrayidx) nounwind
   ret i8* %call
@@ -326,13 +326,13 @@ define noalias i8* @test23() nounwind uwtable ssp {
 ; CHECK: store i32 %c
 ; CHECK: ret void
 define void @test24([2 x i32]* %a, i32 %b, i32 %c) nounwind {
-  %1 = getelementptr inbounds [2 x i32]* %a, i64 0, i64 0
+  %1 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 0, i64 0
   store i32 0, i32* %1, align 4
-  %2 = getelementptr inbounds [2 x i32]* %a, i64 0, i64 1
+  %2 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 0, i64 1
   store i32 0, i32* %2, align 4
-  %3 = getelementptr inbounds [2 x i32]* %a, i64 0, i64 0
+  %3 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 0, i64 0
   store i32 %b, i32* %3, align 4
-  %4 = getelementptr inbounds [2 x i32]* %a, i64 0, i64 1
+  %4 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 0, i64 1
   store i32 %c, i32* %4, align 4
   ret void
 }
@@ -343,8 +343,8 @@ define void @test24([2 x i32]* %a, i32 %b, i32 %c) nounwind {
 ; CHECK: store i8 0
 ; CHECK: store i8 %tmp
 define i8* @test25(i8* %p) nounwind {
-  %p.4 = getelementptr i8* %p, i64 4
-  %tmp = load i8* %p.4, align 1
+  %p.4 = getelementptr i8, i8* %p, i64 4
+  %tmp = load i8, i8* %p.4, align 1
   store i8 0, i8* %p.4, align 1
   %q = call i8* @strdup(i8* %p) nounwind optsize
   store i8 %tmp, i8* %p.4, align 1
diff --git a/test/Transforms/EarlyCSE/AArch64/intrinsics.ll b/test/Transforms/EarlyCSE/AArch64/intrinsics.ll
new file mode 100644
index 000000000000..d166ff1e1092
--- /dev/null
+++ b/test/Transforms/EarlyCSE/AArch64/intrinsics.ll
@@ -0,0 +1,232 @@
+; RUN: opt < %s -S -mtriple=aarch64-none-linux-gnu -mattr=+neon -early-cse | FileCheck %s
+; RUN: opt < %s -S -mtriple=aarch64-none-linux-gnu -mattr=+neon -passes=early-cse | FileCheck %s
+
+define <4 x i32> @test_cse(i32* %a, [2 x <4 x i32>] %s.coerce, i32 %n) {
+entry:
+; Check that @llvm.aarch64.neon.ld2 is optimized away by Early CSE.
+; CHECK-LABEL: @test_cse
+; CHECK-NOT: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8
+  %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
+  %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.body, %entry
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]
+  %cmp = icmp slt i32 %i.0, %n
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %0 = bitcast i32* %a to i8*
+  %1 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
+  %2 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>
+  %3 = bitcast <16 x i8> %1 to <4 x i32>
+  %4 = bitcast <16 x i8> %2 to <4 x i32>
+  call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %4, i8* %0)
+  %5 = bitcast i32* %a to i8*
+  %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8* %5)
+  %vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0
+  %vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 1
+  %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)
+  %inc = add nsw i32 %i.0, 1
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  ret <4 x i32> %res.0
+}
+
+define <4 x i32> @test_cse2(i32* %a, [2 x <4 x i32>] %s.coerce, i32 %n) {
+entry:
+; Check that the first @llvm.aarch64.neon.st2 is optimized away by Early CSE.
+; CHECK-LABEL: @test_cse2
+; CHECK-NOT: call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %3, i8* %0)
+; CHECK: call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %4, i8* %0)
+  %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
+  %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.body, %entry
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]
+  %cmp = icmp slt i32 %i.0, %n
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %0 = bitcast i32* %a to i8*
+  %1 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
+  %2 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>
+  %3 = bitcast <16 x i8> %1 to <4 x i32>
+  %4 = bitcast <16 x i8> %2 to <4 x i32>
+  call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %3, i8* %0)
+  call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %4, i8* %0)
+  %5 = bitcast i32* %a to i8*
+  %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8* %5)
+  %vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0
+  %vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 1
+  %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)
+  %inc = add nsw i32 %i.0, 1
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  ret <4 x i32> %res.0
+}
+
+define <4 x i32> @test_cse3(i32* %a, [2 x <4 x i32>] %s.coerce, i32 %n) #0 {
+entry:
+; Check that the first @llvm.aarch64.neon.ld2 is optimized away by Early CSE.
+; CHECK-LABEL: @test_cse3
+; CHECK: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8
+; CHECK-NOT: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8
+  %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
+  %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.body, %entry
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]
+  %cmp = icmp slt i32 %i.0, %n
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %0 = bitcast i32* %a to i8*
+  %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8* %0)
+  %vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0
+  %vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 1
+  %1 = bitcast i32* %a to i8*
+  %vld22 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8* %1)
+  %vld22.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld22, 0
+  %vld22.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld22, 1
+  %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld22.fca.0.extract)
+  %inc = add nsw i32 %i.0, 1
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  ret <4 x i32> %res.0
+}
+
+
+define <4 x i32> @test_nocse(i32* %a, i32* %b, [2 x <4 x i32>] %s.coerce, i32 %n) {
+entry:
+; Check that the store prevents @llvm.aarch64.neon.ld2 from being optimized
+; away by Early CSE.
+; CHECK-LABEL: @test_nocse
+; CHECK: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8
+  %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
+  %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.body, %entry
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]
+  %cmp = icmp slt i32 %i.0, %n
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %0 = bitcast i32* %a to i8*
+  %1 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
+  %2 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>
+  %3 = bitcast <16 x i8> %1 to <4 x i32>
+  %4 = bitcast <16 x i8> %2 to <4 x i32>
+  call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %4, i8* %0)
+  store i32 0, i32* %b, align 4
+  %5 = bitcast i32* %a to i8*
+  %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8* %5)
+  %vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0
+  %vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 1
+  %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)
+  %inc = add nsw i32 %i.0, 1
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  ret <4 x i32> %res.0
+}
+
+define <4 x i32> @test_nocse2(i32* %a, [2 x <4 x i32>] %s.coerce, i32 %n) {
+entry:
+; Check that @llvm.aarch64.neon.ld3 is not optimized away by Early CSE due
+; to mismatch between st2 and ld3.
+; CHECK-LABEL: @test_nocse2
+; CHECK: call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i8
+  %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
+  %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.body, %entry
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]
+  %cmp = icmp slt i32 %i.0, %n
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %0 = bitcast i32* %a to i8*
+  %1 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
+  %2 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>
+  %3 = bitcast <16 x i8> %1 to <4 x i32>
+  %4 = bitcast <16 x i8> %2 to <4 x i32>
+  call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %4, i8* %0)
+  %5 = bitcast i32* %a to i8*
+  %vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i8(i8* %5)
+  %vld3.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 0
+  %vld3.fca.2.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 2
+  %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld3.fca.0.extract, <4 x i32> %vld3.fca.2.extract)
+  %inc = add nsw i32 %i.0, 1
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  ret <4 x i32> %res.0
+}
+
+define <4 x i32> @test_nocse3(i32* %a, [2 x <4 x i32>] %s.coerce, i32 %n) {
+entry:
+; Check that @llvm.aarch64.neon.st3 is not optimized away by Early CSE due to
+; mismatch between st2 and st3.
+; CHECK-LABEL: @test_nocse3
+; CHECK: call void @llvm.aarch64.neon.st3.v4i32.p0i8
+; CHECK: call void @llvm.aarch64.neon.st2.v4i32.p0i8
+  %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
+  %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.body, %entry
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]
+  %cmp = icmp slt i32 %i.0, %n
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %0 = bitcast i32* %a to i8*
+  %1 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
+  %2 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>
+  %3 = bitcast <16 x i8> %1 to <4 x i32>
+  %4 = bitcast <16 x i8> %2 to <4 x i32>
+  call void @llvm.aarch64.neon.st3.v4i32.p0i8(<4 x i32> %4, <4 x i32> %3, <4 x i32> %3, i8* %0)
+  call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %3, i8* %0)
+  %5 = bitcast i32* %a to i8*
+  %vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i8(i8* %5)
+  %vld3.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 0
+  %vld3.fca.1.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 1
+  %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld3.fca.0.extract, <4 x i32> %vld3.fca.0.extract)
+  %inc = add nsw i32 %i.0, 1
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  ret <4 x i32> %res.0
+}
+
+; Function Attrs: nounwind
+declare void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32>, <4 x i32>, i8* nocapture)
+
+; Function Attrs: nounwind
+declare void @llvm.aarch64.neon.st3.v4i32.p0i8(<4 x i32>, <4 x i32>, <4 x i32>, i8* nocapture)
+
+; Function Attrs: nounwind readonly
+declare { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8*)
+
+; Function Attrs: nounwind readonly
+declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i8(i8*)
+
+define internal fastcc <4 x i32> @vaddq_s32(<4 x i32> %__p0, <4 x i32> %__p1) {
+entry:
+  %add = add <4 x i32> %__p0, %__p1
+  ret <4 x i32> %add
+}
diff --git a/test/Transforms/EarlyCSE/AArch64/lit.local.cfg b/test/Transforms/EarlyCSE/AArch64/lit.local.cfg
new file mode 100644
index 000000000000..6642d2870680
--- /dev/null
+++ b/test/Transforms/EarlyCSE/AArch64/lit.local.cfg
@@ -0,0 +1,5 @@
+config.suffixes = ['.ll']
+
+targets = set(config.root.targets_to_build.split())
+if not 'AArch64' in targets:
+    config.unsupported = True
diff --git a/test/Transforms/EarlyCSE/basic.ll b/test/Transforms/EarlyCSE/basic.ll
index 3ec8831def18..43b5e6098f6a 100644
--- a/test/Transforms/EarlyCSE/basic.ll
+++ b/test/Transforms/EarlyCSE/basic.ll
@@ -1,4 +1,5 @@
 ; RUN: opt < %s -S -early-cse | FileCheck %s
+; RUN: opt < %s -S -passes=early-cse | FileCheck %s
 
 declare void @llvm.assume(i1) nounwind
 
@@ -36,8 +37,8 @@ define void @test1(i8 %V, i32 *%P) {
 ;; Simple load value numbering.
 ; CHECK-LABEL: @test2(
 define i32 @test2(i32 *%P) {
-  %V1 = load i32* %P
-  %V2 = load i32* %P
+  %V1 = load i32, i32* %P
+  %V2 = load i32, i32* %P
   %Diff = sub i32 %V1, %V2
   ret i32 %Diff
   ; CHECK: ret i32 0
@@ -45,9 +46,9 @@ define i32 @test2(i32 *%P) {
 
 ; CHECK-LABEL: @test2a(
 define i32 @test2a(i32 *%P, i1 %b) {
-  %V1 = load i32* %P
+  %V1 = load i32, i32* %P
   tail call void @llvm.assume(i1 %b)
-  %V2 = load i32* %P
+  %V2 = load i32, i32* %P
   %Diff = sub i32 %V1, %V2
   ret i32 %Diff
   ; CHECK: ret i32 0
@@ -56,13 +57,13 @@ define i32 @test2a(i32 *%P, i1 %b) {
 ;; Cross block load value numbering.
 ; CHECK-LABEL: @test3(
 define i32 @test3(i32 *%P, i1 %Cond) {
-  %V1 = load i32* %P
+  %V1 = load i32, i32* %P
   br i1 %Cond, label %T, label %F
 T:
   store i32 4, i32* %P
   ret i32 42
 F:
-  %V2 = load i32* %P
+  %V2 = load i32, i32* %P
   %Diff = sub i32 %V1, %V2
   ret i32 %Diff
   ; CHECK: F:
@@ -71,14 +72,14 @@ F:
 
 ; CHECK-LABEL: @test3a(
 define i32 @test3a(i32 *%P, i1 %Cond, i1 %b) {
-  %V1 = load i32* %P
+  %V1 = load i32, i32* %P
   br i1 %Cond, label %T, label %F
 T:
   store i32 4, i32* %P
   ret i32 42
 F:
   tail call void @llvm.assume(i1 %b)
-  %V2 = load i32* %P
+  %V2 = load i32, i32* %P
   %Diff = sub i32 %V1, %V2
   ret i32 %Diff
   ; CHECK: F:
@@ -88,7 +89,7 @@ F:
 ;; Cross block load value numbering stops when stores happen.
 ; CHECK-LABEL: @test4(
 define i32 @test4(i32 *%P, i1 %Cond) {
-  %V1 = load i32* %P
+  %V1 = load i32, i32* %P
   br i1 %Cond, label %T, label %F
 T:
   ret i32 42
@@ -96,7 +97,7 @@ F:
   ; Clobbers V1
   store i32 42, i32* %P
   
-  %V2 = load i32* %P
+  %V2 = load i32, i32* %P
   %Diff = sub i32 %V1, %V2
   ret i32 %Diff
   ; CHECK: F:
@@ -119,7 +120,7 @@ define i32 @test5(i32 *%P) {
 ; CHECK-LABEL: @test6(
 define i32 @test6(i32 *%P) {
   store i32 42, i32* %P
-  %V1 = load i32* %P
+  %V1 = load i32, i32* %P
   ret i32 %V1
   ; CHECK: ret i32 42
 }
@@ -128,7 +129,7 @@ define i32 @test6(i32 *%P) {
 define i32 @test6a(i32 *%P, i1 %b) {
   store i32 42, i32* %P
   tail call void @llvm.assume(i1 %b)
-  %V1 = load i32* %P
+  %V1 = load i32, i32* %P
   ret i32 %V1
   ; CHECK: ret i32 42
 }
@@ -194,11 +195,11 @@ define void @test11(i32 *%P) {
 
 ; CHECK-LABEL: @test12(
 define i32 @test12(i1 %B, i32* %P1, i32* %P2) {
-  %load0 = load i32* %P1
-  %1 = load atomic i32* %P2 seq_cst, align 4
-  %load1 = load i32* %P1
+  %load0 = load i32, i32* %P1
+  %1 = load atomic i32, i32* %P2 seq_cst, align 4
+  %load1 = load i32, i32* %P1
   %sel = select i1 %B, i32 %load0, i32 %load1
   ret i32 %sel
-  ; CHECK: load i32* %P1
-  ; CHECK: load i32* %P1
+  ; CHECK: load i32, i32* %P1
+  ; CHECK: load i32, i32* %P1
 }
diff --git a/test/Transforms/EarlyCSE/conditional.ll b/test/Transforms/EarlyCSE/conditional.ll
new file mode 100644
index 000000000000..5b5a74f112b5
--- /dev/null
+++ b/test/Transforms/EarlyCSE/conditional.ll
@@ -0,0 +1,107 @@
+; RUN: opt -early-cse -S < %s | FileCheck %s
+
+; Can we CSE a known condition to a constant?
+define i1 @test(i8* %p) {
+; CHECK-LABEL: @test
+entry:
+  %cnd1 = icmp eq i8* %p, null
+  br i1 %cnd1, label %taken, label %untaken
+
+taken:
+; CHECK-LABEL: taken:
+; CHECK-NEXT: ret i1 true
+  %cnd2 = icmp eq i8* %p, null
+  ret i1 %cnd2
+
+untaken:
+; CHECK-LABEL: untaken:
+; CHECK-NEXT: ret i1 false
+  %cnd3 = icmp eq i8* %p, null
+  ret i1 %cnd3
+}
+
+; We can CSE the condition, but we *don't* know it's value after the merge
+define i1 @test_neg1(i8* %p) {
+; CHECK-LABEL: @test_neg1
+entry:
+  %cnd1 = icmp eq i8* %p, null
+  br i1 %cnd1, label %taken, label %untaken
+
+taken:
+  br label %merge
+
+untaken:
+  br label %merge
+
+merge:
+; CHECK-LABEL: merge:
+; CHECK-NEXT: ret i1 %cnd1
+  %cnd3 = icmp eq i8* %p, null
+  ret i1 %cnd3
+}
+
+; Check specifically for a case where we have a unique predecessor, but
+; not a single predecessor.  We can not know the value of the condition here.
+define i1 @test_neg2(i8* %p) {
+; CHECK-LABEL: @test_neg2
+entry:
+  %cnd1 = icmp eq i8* %p, null
+  br i1 %cnd1, label %merge, label %merge
+
+merge:
+; CHECK-LABEL: merge:
+; CHECK-NEXT: ret i1 %cnd1
+  %cnd3 = icmp eq i8* %p, null
+  ret i1 %cnd3
+}
+
+; Replace a use rather than CSE
+define i1 @test2(i8* %p) {
+; CHECK-LABEL: @test2
+entry:
+  %cnd = icmp eq i8* %p, null
+  br i1 %cnd, label %taken, label %untaken
+
+taken:
+; CHECK-LABEL: taken:
+; CHECK-NEXT: ret i1 true
+  ret i1 %cnd
+
+untaken:
+; CHECK-LABEL: untaken:
+; CHECK-NEXT: ret i1 false
+  ret i1 %cnd
+}
+
+; Not legal to replace use given it's not dominated by edge
+define i1 @test2_neg1(i8* %p) {
+; CHECK-LABEL: @test2_neg1
+entry:
+  %cnd1 = icmp eq i8* %p, null
+  br i1 %cnd1, label %taken, label %untaken
+
+taken:
+  br label %merge
+
+untaken:
+  br label %merge
+
+merge:
+; CHECK-LABEL: merge:
+; CHECK-NEXT: ret i1 %cnd1
+  ret i1 %cnd1
+}
+
+; Another single predecessor test, but for dominated use
+define i1 @test2_neg2(i8* %p) {
+; CHECK-LABEL: @test2_neg2
+entry:
+  %cnd1 = icmp eq i8* %p, null
+  br i1 %cnd1, label %merge, label %merge
+
+merge:
+; CHECK-LABEL: merge:
+; CHECK-NEXT: ret i1 %cnd1
+  ret i1 %cnd1
+}
+
diff --git a/test/Transforms/EarlyCSE/edge.ll b/test/Transforms/EarlyCSE/edge.ll
new file mode 100644
index 000000000000..267db679967b
--- /dev/null
+++ b/test/Transforms/EarlyCSE/edge.ll
@@ -0,0 +1,173 @@
+; RUN: opt -early-cse -S < %s | FileCheck %s
+; Same as GVN/edge.ll, but updated to reflect EarlyCSE's less powerful
+; implementation.  EarlyCSE currently doesn't exploit equality comparisons
+; against constants.
+
+define i32 @f1(i32 %x) {
+  ; CHECK-LABEL: define i32 @f1(
+bb0:
+  %cmp = icmp eq i32 %x, 0
+  br i1 %cmp, label %bb2, label %bb1
+bb1:
+  br label %bb2
+bb2:
+  %cond = phi i32 [ %x, %bb0 ], [ 0, %bb1 ]
+  %foo = add i32 %cond, %x
+  ret i32 %foo
+  ; CHECK: bb2:
+  ; CHECK: %cond = phi i32 [ %x, %bb0 ], [ 0, %bb1 ]
+}
+
+define i32 @f2(i32 %x) {
+  ; CHECK-LABEL: define i32 @f2(
+bb0:
+  %cmp = icmp ne i32 %x, 0
+  br i1 %cmp, label %bb1, label %bb2
+bb1:
+  br label %bb2
+bb2:
+  %cond = phi i32 [ %x, %bb0 ], [ 0, %bb1 ]
+  %foo = add i32 %cond, %x
+  ret i32 %foo
+  ; CHECK: bb2:
+  ; CHECK: %cond = phi i32 [ %x, %bb0 ], [ 0, %bb1 ]
+}
+
+define i32 @f3(i32 %x) {
+  ; CHECK-LABEL: define i32 @f3(
+bb0:
+  switch i32 %x, label %bb1 [ i32 0, label %bb2]
+bb1:
+  br label %bb2
+bb2:
+  %cond = phi i32 [ %x, %bb0 ], [ 0, %bb1 ]
+  %foo = add i32 %cond, %x
+  ret i32 %foo
+  ; CHECK: bb2:
+  ; CHECK: %cond = phi i32 [ %x, %bb0 ], [ 0, %bb1 ]
+}
+
+declare void @g(i1)
+define void @f4(i8 * %x)  {
+; CHECK-LABEL: define void @f4(
+bb0:
+  %y = icmp eq i8* null, %x
+  br i1 %y, label %bb2, label %bb1
+bb1:
+  br label %bb2
+bb2:
+  %zed = icmp eq i8* null, %x
+  call void @g(i1 %zed)
+; CHECK: call void @g(i1 %y)
+  ret void
+}
+
+define double @fcmp_oeq_not_zero(double %x, double %y) {
+entry:
+  %cmp = fcmp oeq double %y, 2.0
+  br i1 %cmp, label %if, label %return
+
+if:
+  %div = fdiv double %x, %y
+  br label %return
+
+return:
+  %retval = phi double [ %div, %if ], [ %x, %entry ]
+  ret double %retval
+
+; CHECK-LABEL: define double @fcmp_oeq_not_zero(
+; CHECK: %div = fdiv double %x, %y
+}
+
+define double @fcmp_une_not_zero(double %x, double %y) {
+entry:
+  %cmp = fcmp une double %y, 2.0
+  br i1 %cmp, label %return, label %else
+
+else:
+  %div = fdiv double %x, %y
+  br label %return
+
+return:
+  %retval = phi double [ %div, %else ], [ %x, %entry ]
+  ret double %retval
+
+; CHECK-LABEL: define double @fcmp_une_not_zero(
+; CHECK: %div = fdiv double %x, %y
+}
+
+; PR22376 - We can't propagate zero constants because -0.0 
+; compares equal to 0.0. If %y is -0.0 in this test case,
+; we would produce the wrong sign on the infinity return value.
+define double @fcmp_oeq_zero(double %x, double %y) {
+entry:
+  %cmp = fcmp oeq double %y, 0.0
+  br i1 %cmp, label %if, label %return
+
+if:
+  %div = fdiv double %x, %y
+  br label %return
+
+return:
+  %retval = phi double [ %div, %if ], [ %x, %entry ]
+  ret double %retval
+
+; CHECK-LABEL: define double @fcmp_oeq_zero(
+; CHECK: %div = fdiv double %x, %y
+}
+
+define double @fcmp_une_zero(double %x, double %y) {
+entry:
+  %cmp = fcmp une double %y, -0.0
+  br i1 %cmp, label %return, label %else
+
+else:
+  %div = fdiv double %x, %y
+  br label %return
+
+return:
+  %retval = phi double [ %div, %else ], [ %x, %entry ]
+  ret double %retval
+
+; CHECK-LABEL: define double @fcmp_une_zero(
+; CHECK: %div = fdiv double %x, %y
+}
+
+; We also cannot propagate a value if it's not a constant.
+; This is because the value could be 0.0 or -0.0.
+
+define double @fcmp_oeq_maybe_zero(double %x, double %y, double %z1, double %z2) {
+entry:
+ %z = fadd double %z1, %z2
+ %cmp = fcmp oeq double %y, %z
+ br i1 %cmp, label %if, label %return
+
+if:
+ %div = fdiv double %x, %z
+ br label %return
+
+return:
+ %retval = phi double [ %div, %if ], [ %x, %entry ]
+ ret double %retval
+
+; CHECK-LABEL: define double @fcmp_oeq_maybe_zero(
+; CHECK: %div = fdiv double %x, %z
+}
+
+define double @fcmp_une_maybe_zero(double %x, double %y, double %z1, double %z2) {
+entry:
+ %z = fadd double %z1, %z2
+ %cmp = fcmp une double %y, %z
+ br i1 %cmp, label %return, label %else
+
+else:
+ %div = fdiv double %x, %z
+ br label %return
+
+return:
+ %retval = phi double [ %div, %else ], [ %x, %entry ]
+ ret double %retval
+
+; CHECK-LABEL: define double @fcmp_une_maybe_zero(
+; CHECK: %div = fdiv double %x, %z
+}
diff --git a/test/Transforms/EarlyCSE/read-reg.ll b/test/Transforms/EarlyCSE/read-reg.ll
new file mode 100644
index 000000000000..83a299912c77
--- /dev/null
+++ b/test/Transforms/EarlyCSE/read-reg.ll
@@ -0,0 +1,34 @@
+; RUN: opt -S -early-cse < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define i64 @f(i64 %x) #0 {
+entry:
+  %0 = call i64 @llvm.read_register.i64(metadata !0)
+  call void bitcast (void (...)* @foo to void ()*)()
+  %1 = call i64 @llvm.read_register.i64(metadata !0)
+  %add = add nsw i64 %0, %1
+  ret i64 %add
+}
+
+; CHECK-LABEL: @f
+; CHECK: call i64 @llvm.read_register.i64
+; CHECK: call i64 @llvm.read_register.i64
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.read_register.i64(metadata) #1
+
+; Function Attrs: nounwind
+declare void @llvm.write_register.i64(metadata, i64) #2
+
+declare void @foo(...)
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind }
+
+!llvm.named.register.r1 = !{!0}
+
+!0 = !{!"r1"}
+
diff --git a/test/Transforms/Float2Int/basic.ll b/test/Transforms/Float2Int/basic.ll
new file mode 100644
index 000000000000..f4d946914cd4
--- /dev/null
+++ b/test/Transforms/Float2Int/basic.ll
@@ -0,0 +1,256 @@
+; RUN: opt < %s -float2int -S | FileCheck %s
+
+;
+; Positive tests
+;
+
+; CHECK-LABEL: @simple1
+; CHECK:  %1 = zext i8 %a to i32
+; CHECK:  %2 = add i32 %1, 1
+; CHECK:  %3 = trunc i32 %2 to i16
+; CHECK:  ret i16 %3
+define i16 @simple1(i8 %a) {
+  %1 = uitofp i8 %a to float
+  %2 = fadd float %1, 1.0
+  %3 = fptoui float %2 to i16
+  ret i16 %3
+}
+
+; CHECK-LABEL: @simple2
+; CHECK:  %1 = zext i8 %a to i32
+; CHECK:  %2 = sub i32 %1, 1
+; CHECK:  %3 = trunc i32 %2 to i8
+; CHECK:  ret i8 %3
+define i8 @simple2(i8 %a) {
+  %1 = uitofp i8 %a to float
+  %2 = fsub float %1, 1.0
+  %3 = fptoui float %2 to i8
+  ret i8 %3
+}
+
+; CHECK-LABEL: @simple3
+; CHECK:  %1 = zext i8 %a to i32
+; CHECK:  %2 = sub i32 %1, 1
+; CHECK:  ret i32 %2
+define i32 @simple3(i8 %a) {
+  %1 = uitofp i8 %a to float
+  %2 = fsub float %1, 1.0
+  %3 = fptoui float %2 to i32
+  ret i32 %3
+}
+
+; CHECK-LABEL: @cmp
+; CHECK:  %1 = zext i8 %a to i32
+; CHECK:  %2 = zext i8 %b to i32
+; CHECK:  %3 = icmp slt i32 %1, %2
+; CHECK:  ret i1 %3
+define i1 @cmp(i8 %a, i8 %b) {
+  %1 = uitofp i8 %a to float
+  %2 = uitofp i8 %b to float
+  %3 = fcmp ult float %1, %2
+  ret i1 %3
+}
+
+; CHECK-LABEL: @simple4
+; CHECK:  %1 = zext i32 %a to i64
+; CHECK:  %2 = add i64 %1, 1
+; CHECK:  %3 = trunc i64 %2 to i32
+; CHECK:  ret i32 %3
+define i32 @simple4(i32 %a) {
+  %1 = uitofp i32 %a to double
+  %2 = fadd double %1, 1.0
+  %3 = fptoui double %2 to i32
+  ret i32 %3
+}
+
+; CHECK-LABEL: @simple5
+; CHECK:  %1 = zext i8 %a to i32
+; CHECK:  %2 = zext i8 %b to i32
+; CHECK:  %3 = add i32 %1, 1
+; CHECK:  %4 = mul i32 %3, %2
+; CHECK:  ret i32 %4
+define i32 @simple5(i8 %a, i8 %b) {
+  %1 = uitofp i8 %a to float
+  %2 = uitofp i8 %b to float
+  %3 = fadd float %1, 1.0
+  %4 = fmul float %3, %2
+  %5 = fptoui float %4 to i32
+  ret i32 %5
+}
+
+; The two chains don't interact - failure of one shouldn't
+; cause failure of the other.
+
+; CHECK-LABEL: @multi1
+; CHECK:  %1 = zext i8 %a to i32
+; CHECK:  %2 = zext i8 %b to i32
+; CHECK:  %fc = uitofp i8 %c to float
+; CHECK:  %x1 = add i32 %1, %2
+; CHECK:  %z = fadd float %fc, %d
+; CHECK:  %w = fptoui float %z to i32
+; CHECK:  %r = add i32 %x1, %w
+; CHECK:  ret i32 %r
+define i32 @multi1(i8 %a, i8 %b, i8 %c, float %d) {
+  %fa = uitofp i8 %a to float
+  %fb = uitofp i8 %b to float
+  %fc = uitofp i8 %c to float
+  %x = fadd float %fa, %fb
+  %y = fptoui float %x to i32
+  %z = fadd float %fc, %d
+  %w = fptoui float %z to i32
+  %r = add i32 %y, %w
+  ret i32 %r
+}
+
+; CHECK-LABEL: @simple_negzero
+; CHECK:  %1 = zext i8 %a to i32
+; CHECK:  %2 = add i32 %1, 0
+; CHECK:  %3 = trunc i32 %2 to i16
+; CHECK:  ret i16 %3
+define i16 @simple_negzero(i8 %a) {
+  %1 = uitofp i8 %a to float
+  %2 = fadd fast float %1, -0.0
+  %3 = fptoui float %2 to i16
+  ret i16 %3
+}
+
+; CHECK-LABEL: @simple_negative
+; CHECK: %1 = sext i8 %call to i32
+; CHECK: %mul1 = mul i32 %1, -3
+; CHECK: %2 = trunc i32 %mul1 to i8
+; CHECK: %conv3 = sext i8 %2 to i32
+; CHECK: ret i32 %conv3
+define i32 @simple_negative(i8 %call) {
+  %conv1 = sitofp i8 %call to float
+  %mul = fmul float %conv1, -3.000000e+00
+  %conv2 = fptosi float %mul to i8
+  %conv3 = sext i8 %conv2 to i32
+  ret i32 %conv3
+}
+
+;
+; Negative tests
+;
+
+; CHECK-LABEL: @neg_multi1
+; CHECK:  %fa = uitofp i8 %a to float
+; CHECK:  %fc = uitofp i8 %c to float
+; CHECK:  %x = fadd float %fa, %fc
+; CHECK:  %y = fptoui float %x to i32
+; CHECK:  %z = fadd float %fc, %d
+; CHECK:  %w = fptoui float %z to i32
+; CHECK:  %r = add i32 %y, %w
+; CHECK:  ret i32 %r
+; The two chains intersect, which means because one fails, no
+; transform can occur.
+define i32 @neg_multi1(i8 %a, i8 %b, i8 %c, float %d) {
+  %fa = uitofp i8 %a to float
+  %fc = uitofp i8 %c to float
+  %x = fadd float %fa, %fc
+  %y = fptoui float %x to i32
+  %z = fadd float %fc, %d
+  %w = fptoui float %z to i32
+  %r = add i32 %y, %w
+  ret i32 %r
+}
+
+; CHECK-LABEL: @neg_muld
+; CHECK:  %fa = uitofp i32 %a to double
+; CHECK:  %fb = uitofp i32 %b to double
+; CHECK:  %mul = fmul double %fa, %fb
+; CHECK:  %r = fptoui double %mul to i64
+; CHECK:  ret i64 %r
+; The i32 * i32 = i64, which has 64 bits, which is greater than the 52 bits
+; that can be exactly represented in a double.
+define i64 @neg_muld(i32 %a, i32 %b) {
+  %fa = uitofp i32 %a to double
+  %fb = uitofp i32 %b to double
+  %mul = fmul double %fa, %fb
+  %r = fptoui double %mul to i64
+  ret i64 %r
+}
+
+; CHECK-LABEL: @neg_mulf
+; CHECK:  %fa = uitofp i16 %a to float
+; CHECK:  %fb = uitofp i16 %b to float
+; CHECK:  %mul = fmul float %fa, %fb
+; CHECK:  %r = fptoui float %mul to i32
+; CHECK:  ret i32 %r
+; The i16 * i16 = i32, which can't be represented in a float, but can in a
+; double. This should fail, as the written code uses floats, not doubles so
+; the original result may be inaccurate.
+define i32 @neg_mulf(i16 %a, i16 %b) {
+  %fa = uitofp i16 %a to float
+  %fb = uitofp i16 %b to float
+  %mul = fmul float %fa, %fb
+  %r = fptoui float %mul to i32
+  ret i32 %r
+}
+
+; CHECK-LABEL: @neg_cmp
+; CHECK:  %1 = uitofp i8 %a to float
+; CHECK:  %2 = uitofp i8 %b to float
+; CHECK:  %3 = fcmp false float %1, %2
+; CHECK:  ret i1 %3
+; "false" doesn't have an icmp equivalent.
+define i1 @neg_cmp(i8 %a, i8 %b) {
+  %1 = uitofp i8 %a to float
+  %2 = uitofp i8 %b to float
+  %3 = fcmp false float %1, %2
+  ret i1 %3
+}
+
+; CHECK-LABEL: @neg_div
+; CHECK:  %1 = uitofp i8 %a to float
+; CHECK:  %2 = fdiv float %1, 1.0
+; CHECK:  %3 = fptoui float %2 to i16
+; CHECK:  ret i16 %3
+; Division isn't a supported operator.
+define i16 @neg_div(i8 %a) {
+  %1 = uitofp i8 %a to float
+  %2 = fdiv float %1, 1.0
+  %3 = fptoui float %2 to i16
+  ret i16 %3
+}
+
+; CHECK-LABEL: @neg_remainder
+; CHECK:  %1 = uitofp i8 %a to float
+; CHECK:  %2 = fadd float %1, 1.2
+; CHECK:  %3 = fptoui float %2 to i16
+; CHECK:  ret i16 %3
+; 1.2 is not an integer.
+define i16 @neg_remainder(i8 %a) {
+  %1 = uitofp i8 %a to float
+  %2 = fadd float %1, 1.25
+  %3 = fptoui float %2 to i16
+  ret i16 %3
+}
+
+; CHECK-LABEL: @neg_toolarge
+; CHECK:  %1 = uitofp i80 %a to fp128
+; CHECK:  %2 = fadd fp128 %1, %1
+; CHECK:  %3 = fptoui fp128 %2 to i80
+; CHECK:  ret i80 %3
+; i80 > i64, which is the largest bitwidth handleable by default.
+define i80 @neg_toolarge(i80 %a) {
+  %1 = uitofp i80 %a to fp128
+  %2 = fadd fp128 %1, %1
+  %3 = fptoui fp128 %2 to i80
+  ret i80 %3
+}
+
+; CHECK-LABEL: @neg_calluser
+; CHECK: sitofp
+; CHECK: fcmp
+; The sequence %1..%3 cannot be converted because %4 uses %2.
+define i32 @neg_calluser(i32 %value) {
+  %1 = sitofp i32 %value to double
+  %2 = fadd double %1, 1.0
+  %3 = fcmp olt double %2, 0.000000e+00
+  %4 = tail call double @g(double %2)
+  %5 = fptosi double %4 to i32
+  %6 = zext i1 %3 to i32
+  %7 = add i32 %6, %5
+  ret i32 %7
+}
+declare double @g(double)
diff --git a/test/Transforms/Float2Int/float2int-optnone.ll b/test/Transforms/Float2Int/float2int-optnone.ll
new file mode 100644
index 000000000000..c1eeea7a82e5
--- /dev/null
+++ b/test/Transforms/Float2Int/float2int-optnone.ll
@@ -0,0 +1,17 @@
+; RUN: opt < %s -float2int -S | FileCheck %s
+;
+; Verify that pass float2int is not run on optnone functions.
+
+define i16 @simple1(i8 %a) #0 {
+; CHECK-LABEL: @simple1
+; CHECK:  %1 = uitofp i8 %a to float
+; CHECK-NEXT:  %2 = fadd float %1, 1.0
+; CHECK-NEXT:  %3 = fptoui float %2 to i16
+; CHECK-NEXT:  ret i16 %3
+  %1 = uitofp i8 %a to float
+  %2 = fadd float %1, 1.0
+  %3 = fptoui float %2 to i16
+  ret i16 %3
+}
+
+attributes #0 = { noinline optnone }
diff --git a/test/Transforms/Float2Int/toolarge.ll b/test/Transforms/Float2Int/toolarge.ll
new file mode 100644
index 000000000000..b5d778157685
--- /dev/null
+++ b/test/Transforms/Float2Int/toolarge.ll
@@ -0,0 +1,16 @@
+; RUN: opt < %s -float2int -float2int-max-integer-bw=256 -S | FileCheck %s
+
+; CHECK-LABEL: @neg_toolarge
+; CHECK:  %1 = uitofp i80 %a to fp128
+; CHECK:  %2 = fadd fp128 %1, %1
+; CHECK:  %3 = fptoui fp128 %2 to i80
+; CHECK:  ret i80 %3
+; fp128 has a 112-bit mantissa, which can hold an i80. But we only support
+; up to i64, so it should fail (even though the max integer bitwidth is 256).
+define i80 @neg_toolarge(i80 %a) {
+  %1 = uitofp i80 %a to fp128
+  %2 = fadd fp128 %1, %1
+  %3 = fptoui fp128 %2 to i80
+  ret i80 %3
+}
+
diff --git a/test/Transforms/FunctionAttrs/2008-09-03-ReadNone.ll b/test/Transforms/FunctionAttrs/2008-09-03-ReadNone.ll
index 36a765873487..ca05d63743b5 100644
--- a/test/Transforms/FunctionAttrs/2008-09-03-ReadNone.ll
+++ b/test/Transforms/FunctionAttrs/2008-09-03-ReadNone.ll
@@ -17,7 +17,7 @@ define i32 @g() readonly {
 
 ; CHECK: define i32 @h() #0
 define i32 @h() readnone {
-	%tmp = load i32* @x		; <i32> [#uses=1]
+	%tmp = load i32, i32* @x		; <i32> [#uses=1]
 	ret i32 %tmp
 }
 
diff --git a/test/Transforms/FunctionAttrs/2008-09-13-VolatileRead.ll b/test/Transforms/FunctionAttrs/2008-09-13-VolatileRead.ll
index b7e4d1f87261..fef872c794ae 100644
--- a/test/Transforms/FunctionAttrs/2008-09-13-VolatileRead.ll
+++ b/test/Transforms/FunctionAttrs/2008-09-13-VolatileRead.ll
@@ -4,6 +4,6 @@
 @g = global i32 0		; <i32*> [#uses=1]
 
 define i32 @f() {
-	%t = load volatile i32* @g		; <i32> [#uses=1]
+	%t = load volatile i32, i32* @g		; <i32> [#uses=1]
 	ret i32 %t
 }
diff --git a/test/Transforms/FunctionAttrs/2008-12-29-Constant.ll b/test/Transforms/FunctionAttrs/2008-12-29-Constant.ll
index 9655da45c646..e3a8f0161b86 100644
--- a/test/Transforms/FunctionAttrs/2008-12-29-Constant.ll
+++ b/test/Transforms/FunctionAttrs/2008-12-29-Constant.ll
@@ -3,6 +3,6 @@
 @s = external constant i8		; <i8*> [#uses=1]
 
 define i8 @f() {
-	%tmp = load i8* @s		; <i8> [#uses=1]
+	%tmp = load i8, i8* @s		; <i8> [#uses=1]
 	ret i8 %tmp
 }
diff --git a/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll b/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll
index 0cf1cb7c638d..ec1db0957283 100644
--- a/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll
+++ b/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll
@@ -2,7 +2,7 @@
 
 ; CHECK: define i32* @a(i32** nocapture readonly %p)
 define i32* @a(i32** %p) {
-	%tmp = load i32** %p
+	%tmp = load i32*, i32** %p
 	ret i32* %tmp
 }
 
diff --git a/test/Transforms/FunctionAttrs/2010-10-30-volatile.ll b/test/Transforms/FunctionAttrs/2010-10-30-volatile.ll
index 93991d21a1fa..1a64a8393804 100644
--- a/test/Transforms/FunctionAttrs/2010-10-30-volatile.ll
+++ b/test/Transforms/FunctionAttrs/2010-10-30-volatile.ll
@@ -5,6 +5,6 @@
 
 define void @foo() {
 ; CHECK: void @foo() {
-  %tmp = load volatile i32* @g
+  %tmp = load volatile i32, i32* @g
   ret void
 }
diff --git a/test/Transforms/FunctionAttrs/atomic.ll b/test/Transforms/FunctionAttrs/atomic.ll
index d5a8db7d53b9..bb867011cc2a 100644
--- a/test/Transforms/FunctionAttrs/atomic.ll
+++ b/test/Transforms/FunctionAttrs/atomic.ll
@@ -7,7 +7,7 @@ define i32 @test1(i32 %x) uwtable ssp {
 entry:
   %x.addr = alloca i32, align 4
   store atomic i32 %x, i32* %x.addr seq_cst, align 4
-  %r = load atomic i32* %x.addr seq_cst, align 4
+  %r = load atomic i32, i32* %x.addr seq_cst, align 4
   ret i32 %r
 }
 
@@ -15,7 +15,7 @@ entry:
 define i32 @test2(i32* %x) uwtable ssp {
 ; CHECK: define i32 @test2(i32* nocapture readonly %x) #1 {
 entry:
-  %r = load atomic i32* %x seq_cst, align 4
+  %r = load atomic i32, i32* %x seq_cst, align 4
   ret i32 %r
 }
 
diff --git a/test/Transforms/FunctionAttrs/nocapture.ll b/test/Transforms/FunctionAttrs/nocapture.ll
index d3842c8415ca..55a3dc4aa35b 100644
--- a/test/Transforms/FunctionAttrs/nocapture.ll
+++ b/test/Transforms/FunctionAttrs/nocapture.ll
@@ -39,8 +39,8 @@ define i1 @c5(i32* %q, i32 %bitno) {
 	%tmp2 = lshr i32 %tmp, %bitno
 	%bit = and i32 %tmp2, 1
         ; subtle escape mechanism follows
-	%lookup = getelementptr [2 x i1]* @lookup_table, i32 0, i32 %bit
-	%val = load i1* %lookup
+	%lookup = getelementptr [2 x i1], [2 x i1]* @lookup_table, i32 0, i32 %bit
+	%val = load i1, i1* %lookup
 	ret i1 %val
 }
 
@@ -64,14 +64,14 @@ define i1* @lookup_bit(i32* %q, i32 %bitno) readnone nounwind {
 	%tmp = ptrtoint i32* %q to i32
 	%tmp2 = lshr i32 %tmp, %bitno
 	%bit = and i32 %tmp2, 1
-	%lookup = getelementptr [2 x i1]* @lookup_table, i32 0, i32 %bit
+	%lookup = getelementptr [2 x i1], [2 x i1]* @lookup_table, i32 0, i32 %bit
 	ret i1* %lookup
 }
 
 ; CHECK: define i1 @c7(i32* readonly %q, i32 %bitno)
 define i1 @c7(i32* %q, i32 %bitno) {
 	%ptr = call i1* @lookup_bit(i32* %q, i32 %bitno)
-	%val = load i1* %ptr
+	%val = load i1, i1* %ptr
 	ret i1 %val
 }
 
@@ -85,7 +85,7 @@ l:
 	%y = phi i32* [ %q, %e ]
 	%tmp = bitcast i32* %x to i32*		; <i32*> [#uses=2]
 	%tmp2 = select i1 %b, i32* %tmp, i32* %y
-	%val = load i32* %tmp2		; <i32> [#uses=1]
+	%val = load i32, i32* %tmp2		; <i32> [#uses=1]
 	store i32 0, i32* %tmp
 	store i32* %y, i32** @g
 	ret i32 %val
@@ -100,7 +100,7 @@ l:
 	%y = phi i32* [ %q, %e ]
 	%tmp = addrspacecast i32 addrspace(1)* %x to i32*		; <i32*> [#uses=2]
 	%tmp2 = select i1 %b, i32* %tmp, i32* %y
-	%val = load i32* %tmp2		; <i32> [#uses=1]
+	%val = load i32, i32* %tmp2		; <i32> [#uses=1]
 	store i32 0, i32* %tmp
 	store i32* %y, i32** @g
 	ret i32 %val
@@ -188,7 +188,7 @@ declare void @test6_1(i8* %x6_1, i8* nocapture %y6_1, ...)
 
 ; CHECK: define void @test6_2(i8* %x6_2, i8* nocapture %y6_2, i8* %z6_2)
 define void @test6_2(i8* %x6_2, i8* %y6_2, i8* %z6_2) {
-  call void (i8*, i8*, ...)* @test6_1(i8* %x6_2, i8* %y6_2, i8* %z6_2)
+  call void (i8*, i8*, ...) @test6_1(i8* %x6_2, i8* %y6_2, i8* %z6_2)
   store i32* null, i32** @g
   ret void
 }
diff --git a/test/Transforms/FunctionAttrs/optnone-simple.ll b/test/Transforms/FunctionAttrs/optnone-simple.ll
index 9d0f8e3710a6..beaa588da503 100644
--- a/test/Transforms/FunctionAttrs/optnone-simple.ll
+++ b/test/Transforms/FunctionAttrs/optnone-simple.ll
@@ -15,8 +15,8 @@ entry:
   %b.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
   store i32 %b, i32* %b.addr, align 4
-  %0 = load i32* %a.addr, align 4
-  %1 = load i32* %b.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4
+  %1 = load i32, i32* %b.addr, align 4
   %add = add nsw i32 %0, %1
   ret i32 %add
 }
@@ -33,8 +33,8 @@ entry:
   %b.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
   store i32 %b, i32* %b.addr, align 4
-  %0 = load i32* %a.addr, align 4
-  %1 = load i32* %b.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4
+  %1 = load i32, i32* %b.addr, align 4
   %add = add nsw i32 %0, %1
   ret i32 %add
 }
@@ -57,8 +57,8 @@ entry:
   %b.addr = alloca float, align 4
   store float %a, float* %a.addr, align 4
   store float %b, float* %b.addr, align 4
-  %0 = load float* %a.addr, align 4
-  %1 = load float* %b.addr, align 4
+  %0 = load float, float* %a.addr, align 4
+  %1 = load float, float* %b.addr, align 4
   %sub = fsub float %0, %1
   ret float %sub
 }
@@ -75,8 +75,8 @@ entry:
   %b.addr = alloca float, align 4
   store float %a, float* %a.addr, align 4
   store float %b, float* %b.addr, align 4
-  %0 = load float* %a.addr, align 4
-  %1 = load float* %b.addr, align 4
+  %0 = load float, float* %a.addr, align 4
+  %1 = load float, float* %b.addr, align 4
   %sub = fsub float %0, %1
   ret float %sub
 }
@@ -100,8 +100,8 @@ entry:
   %b.addr = alloca <4 x float>, align 16
   store <4 x float> %a, <4 x float>* %a.addr, align 16
   store <4 x float> %b, <4 x float>* %b.addr, align 16
-  %0 = load <4 x float>* %a.addr, align 16
-  %1 = load <4 x float>* %b.addr, align 16
+  %0 = load <4 x float>, <4 x float>* %a.addr, align 16
+  %1 = load <4 x float>, <4 x float>* %b.addr, align 16
   %mul = fmul <4 x float> %0, %1
   ret <4 x float> %mul
 }
@@ -118,8 +118,8 @@ entry:
   %b.addr = alloca <4 x float>, align 16
   store <4 x float> %a, <4 x float>* %a.addr, align 16
   store <4 x float> %b, <4 x float>* %b.addr, align 16
-  %0 = load <4 x float>* %a.addr, align 16
-  %1 = load <4 x float>* %b.addr, align 16
+  %0 = load <4 x float>, <4 x float>* %a.addr, align 16
+  %1 = load <4 x float>, <4 x float>* %b.addr, align 16
   %mul = fmul <4 x float> %0, %1
   ret <4 x float> %mul
 }
diff --git a/test/Transforms/FunctionAttrs/readattrs.ll b/test/Transforms/FunctionAttrs/readattrs.ll
index b4e904cf9b04..7f22e6f2a2c5 100644
--- a/test/Transforms/FunctionAttrs/readattrs.ll
+++ b/test/Transforms/FunctionAttrs/readattrs.ll
@@ -5,7 +5,7 @@ declare void @test1_1(i8* %x1_1, i8* readonly %y1_1, ...)
 
 ; CHECK: define void @test1_2(i8* %x1_2, i8* readonly %y1_2, i8* %z1_2)
 define void @test1_2(i8* %x1_2, i8* %y1_2, i8* %z1_2) {
-  call void (i8*, i8*, ...)* @test1_1(i8* %x1_2, i8* %y1_2, i8* %z1_2)
+  call void (i8*, i8*, ...) @test1_1(i8* %x1_2, i8* %y1_2, i8* %z1_2)
   store i32 0, i32* @x
   ret void
 }
diff --git a/test/Transforms/FunctionAttrs/readnone.ll b/test/Transforms/FunctionAttrs/readnone.ll
new file mode 100644
index 000000000000..eddcdd2641d5
--- /dev/null
+++ b/test/Transforms/FunctionAttrs/readnone.ll
@@ -0,0 +1,13 @@
+; RUN: opt < %s -functionattrs -S | FileCheck %s
+
+; CHECK: define void @bar(i8* nocapture readnone)
+define void @bar(i8* readonly) {
+  call void @foo(i8* %0)
+    ret void
+}
+
+; CHECK: define void @foo(i8* nocapture readnone)
+define void @foo(i8* readonly) {
+  call void @bar(i8* %0)
+  ret void
+}
diff --git a/test/Transforms/GCOVProfiling/function-numbering.ll b/test/Transforms/GCOVProfiling/function-numbering.ll
index 487f4ca01a6b..5a704e4d047b 100644
--- a/test/Transforms/GCOVProfiling/function-numbering.ll
+++ b/test/Transforms/GCOVProfiling/function-numbering.ll
@@ -6,7 +6,7 @@
 ; RUN: cat %s %t1 > %t2
 
 ; RUN: opt -insert-gcov-profiling -S < %t2 | FileCheck --check-prefix GCDA %s
-; RUN: llvm-cov -n -dump %T/function-numbering.gcno 2>&1 | FileCheck --check-prefix GCNO %s
+; RUN: llvm-cov gcov -n -dump %T/function-numbering.gcno 2>&1 | FileCheck --check-prefix GCNO %s
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.10.0"
@@ -15,8 +15,8 @@ target triple = "x86_64-apple-macosx10.10.0"
 ; GCDA-NOT: @{{[0-9]+}} = private unnamed_addr constant .* c"bar\00"
 ; GCDA: @[[BAZ:[0-9]+]] = private unnamed_addr constant [4 x i8] c"baz\00"
 ; GCDA: define internal void @__llvm_gcov_writeout()
-; GCDA: call void @llvm_gcda_emit_function(i32 0, i8* getelementptr inbounds ([4 x i8]* @[[FOO]]
-; GCDA: call void @llvm_gcda_emit_function(i32 1, i8* getelementptr inbounds ([4 x i8]* @[[BAZ]]
+; GCDA: call void @llvm_gcda_emit_function(i32 0, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @[[FOO]]
+; GCDA: call void @llvm_gcda_emit_function(i32 1, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @[[BAZ]]
 
 ; GCNO: == foo (0) @
 ; GCNO-NOT: == bar ({{[0-9]+}}) @
@@ -40,17 +40,17 @@ define void @baz() {
 !llvm.module.flags = !{!9, !10}
 !llvm.ident = !{!11}
 
-!0 = !{!"0x11\0012\00clang version 3.6.0 \000\00\000\00\002", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [function-numbering.ll] [DW_LANG_C99]
-!1 = !{!".../llvm/test/Transforms/GCOVProfiling/function-numbering.ll", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.6.0 ", isOptimized: false, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: ".../llvm/test/Transforms/GCOVProfiling/function-numbering.ll", directory: "")
 !2 = !{}
 !3 = !{!4, !7, !8}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\000\000\000\001", !1, !5, !6, null, void ()* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}    ; [ DW_TAG_file_type ] [/Users/bogner/build/llvm-debug//tmp/foo.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!7 = !{!"0x2e\00bar\00bar\00\002\000\001\000\000\000\000\002", !1, !5, !6, null, void ()* @bar, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [def] [bar]
-!8 = !{!"0x2e\00baz\00baz\00\003\000\001\000\000\000\000\003", !1, !5, !6, null, void ()* @baz, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [baz]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void ()* @foo, variables: !2)
+!5 = !DIFile(filename: ".../llvm/test/Transforms/GCOVProfiling/function-numbering.ll", directory: "")
+!6 = !DISubroutineType(types: !2)
+!7 = !DISubprogram(name: "bar", line: 2, isLocal: false, isDefinition: true, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !6, function: void ()* @bar, variables: !2)
+!8 = !DISubprogram(name: "baz", line: 3, isLocal: false, isDefinition: true, isOptimized: false, scopeLine: 3, file: !1, scope: !5, type: !6, function: void ()* @baz, variables: !2)
 !9 = !{i32 2, !"Dwarf Version", i32 2}
-!10 = !{i32 2, !"Debug Info Version", i32 2}
+!10 = !{i32 2, !"Debug Info Version", i32 3}
 !11 = !{!"clang version 3.6.0 "}
-!12 = !MDLocation(line: 1, column: 13, scope: !4)
-!13 = !MDLocation(line: 3, column: 13, scope: !8)
+!12 = !DILocation(line: 1, column: 13, scope: !4)
+!13 = !DILocation(line: 3, column: 13, scope: !8)
diff --git a/test/Transforms/GCOVProfiling/global-ctor.ll b/test/Transforms/GCOVProfiling/global-ctor.ll
index 9a9b7cecce7a..29c46d6c2107 100644
--- a/test/Transforms/GCOVProfiling/global-ctor.ll
+++ b/test/Transforms/GCOVProfiling/global-ctor.ll
@@ -38,19 +38,19 @@ attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "
 !llvm.gcov = !{!16}
 !llvm.ident = !{!12}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 (trunk 210217)\000\00\000\00\002", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/home/nlewycky/<stdin>] [DW_LANG_C_plus_plus]
-!1 = !{!"<stdin>", !"/home/nlewycky"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 (trunk 210217)", isOptimized: false, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<stdin>", directory: "/home/nlewycky")
 !2 = !{}
 !3 = !{!4, !8}
-!4 = !{!"0x2e\00__cxx_global_var_init\00__cxx_global_var_init\00\002\001\001\000\006\00256\000\002", !5, !6, !7, null, void ()* @__cxx_global_var_init, null, null, !2} ; [ DW_TAG_subprogram ] [line 2] [local] [def] [__cxx_global_var_init]
-!5 = !{!"global-ctor.ll", !"/home/nlewycky"}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [/home/nlewycky/global-ctor.ll]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!8 = !{!"0x2e\00\00\00_GLOBAL__sub_I_global-ctor.ll\000\001\001\000\006\0064\000\000", !1, !9, !7, null, void ()* @_GLOBAL__sub_I_global-ctor.ll, null, null, !2} ; [ DW_TAG_subprogram ] [line 0] [local] [def]
-!9 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/home/nlewycky/<stdin>]
+!4 = !DISubprogram(name: "__cxx_global_var_init", line: 2, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !5, scope: !6, type: !7, function: void ()* @__cxx_global_var_init, variables: !2)
+!5 = !DIFile(filename: "global-ctor.ll", directory: "/home/nlewycky")
+!6 = !DIFile(filename: "global-ctor.ll", directory: "/home/nlewycky")
+!7 = !DISubroutineType(types: !2)
+!8 = !DISubprogram(name: "", linkageName: "_GLOBAL__sub_I_global-ctor.ll", isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagArtificial, isOptimized: false, file: !1, scope: !9, type: !7, function: void ()* @_GLOBAL__sub_I_global-ctor.ll, variables: !2)
+!9 = !DIFile(filename: "<stdin>", directory: "/home/nlewycky")
 !10 = !{i32 2, !"Dwarf Version", i32 4}
-!11 = !{i32 2, !"Debug Info Version", i32 2}
+!11 = !{i32 2, !"Debug Info Version", i32 3}
 !12 = !{!"clang version 3.5.0 (trunk 210217)"}
-!13 = !MDLocation(line: 2, scope: !4)
-!14 = !MDLocation(line: 0, scope: !15)
-!15 = !{!"0xb\000", !5, !8} ; [ DW_TAG_lexical_block ] [/home/nlewycky/global-ctor.ll]
+!13 = !DILocation(line: 2, scope: !4)
+!14 = !DILocation(line: 0, scope: !15)
+!15 = !DILexicalBlockFile(discriminator: 0, file: !5, scope: !8)
diff --git a/test/Transforms/GCOVProfiling/linezero.ll b/test/Transforms/GCOVProfiling/linezero.ll
index cf0fcd2cc820..9e172b752d78 100644
--- a/test/Transforms/GCOVProfiling/linezero.ll
+++ b/test/Transforms/GCOVProfiling/linezero.ll
@@ -1,6 +1,5 @@
-; RUN: sed -e 's|PATTERN|%/T|g' < %s > %t1
-; RUN: opt -insert-gcov-profiling -disable-output < %t1
-; RUN: rm %T/linezero.gcno %t1
+; RUN: sed -e 's|PATTERN|%/T|g' %s | opt -insert-gcov-profiling -disable-output
+; RUN: rm %T/linezero.gcno
 
 ; This is a crash test.
 
@@ -19,38 +18,38 @@ entry:
   %__begin = alloca i8*, align 8
   %__end = alloca i8*, align 8
   %spec = alloca i8, align 1
-  call void @llvm.dbg.declare(metadata %struct.vector** %__range, metadata !27, metadata !{}), !dbg !30
+  call void @llvm.dbg.declare(metadata %struct.vector** %__range, metadata !27, metadata !DIExpression()), !dbg !30
   br label %0
 
 ; <label>:0                                       ; preds = %entry
   call void @_Z13TagFieldSpecsv(), !dbg !31
   store %struct.vector* %ref.tmp, %struct.vector** %__range, align 8, !dbg !31
-  call void @llvm.dbg.declare(metadata i8** %__begin, metadata !32, metadata !{}), !dbg !30
-  %1 = load %struct.vector** %__range, align 8, !dbg !31
+  call void @llvm.dbg.declare(metadata i8** %__begin, metadata !32, metadata !DIExpression()), !dbg !30
+  %1 = load %struct.vector*, %struct.vector** %__range, align 8, !dbg !31
   %call = call i8* @_ZN6vector5beginEv(%struct.vector* %1), !dbg !31
   store i8* %call, i8** %__begin, align 8, !dbg !31
-  call void @llvm.dbg.declare(metadata i8** %__end, metadata !33, metadata !{}), !dbg !30
-  %2 = load %struct.vector** %__range, align 8, !dbg !31
+  call void @llvm.dbg.declare(metadata i8** %__end, metadata !33, metadata !DIExpression()), !dbg !30
+  %2 = load %struct.vector*, %struct.vector** %__range, align 8, !dbg !31
   %call1 = call i8* @_ZN6vector3endEv(%struct.vector* %2), !dbg !31
   store i8* %call1, i8** %__end, align 8, !dbg !31
   br label %for.cond, !dbg !31
 
 for.cond:                                         ; preds = %for.inc, %0
-  %3 = load i8** %__begin, align 8, !dbg !34
-  %4 = load i8** %__end, align 8, !dbg !34
+  %3 = load i8*, i8** %__begin, align 8, !dbg !34
+  %4 = load i8*, i8** %__end, align 8, !dbg !34
   %cmp = icmp ne i8* %3, %4, !dbg !34
   br i1 %cmp, label %for.body, label %for.end, !dbg !34
 
 for.body:                                         ; preds = %for.cond
-  call void @llvm.dbg.declare(metadata i8* %spec, metadata !37, metadata !{}), !dbg !31
-  %5 = load i8** %__begin, align 8, !dbg !38
-  %6 = load i8* %5, align 1, !dbg !38
+  call void @llvm.dbg.declare(metadata i8* %spec, metadata !37, metadata !DIExpression()), !dbg !31
+  %5 = load i8*, i8** %__begin, align 8, !dbg !38
+  %6 = load i8, i8* %5, align 1, !dbg !38
   store i8 %6, i8* %spec, align 1, !dbg !38
   br label %for.inc, !dbg !38
 
 for.inc:                                          ; preds = %for.body
-  %7 = load i8** %__begin, align 8, !dbg !40
-  %incdec.ptr = getelementptr inbounds i8* %7, i32 1, !dbg !40
+  %7 = load i8*, i8** %__begin, align 8, !dbg !40
+  %incdec.ptr = getelementptr inbounds i8, i8* %7, i32 1, !dbg !40
   store i8* %incdec.ptr, i8** %__begin, align 8, !dbg !40
   br label %for.cond, !dbg !40
 
@@ -59,7 +58,7 @@ for.end:                                          ; preds = %for.cond
   unreachable, !dbg !42
 
 return:                                           ; No predecessors!
-  %8 = load i32* %retval, !dbg !44
+  %8 = load i32, i32* %retval, !dbg !44
   ret i32 %8, !dbg !44
 }
 
@@ -94,49 +93,49 @@ attributes #3 = { noreturn nounwind }
 !llvm.gcov = !{!25}
 !llvm.ident = !{!26}
 
-!0 = !{!"0x11\004\00clang version 3.5.0 (trunk 209871)\000\00\000\00\001", !1, !2, !3, !14, !2, !2} ; [ DW_TAG_compile_unit ] [<stdin>] [DW_LANG_C_plus_plus]
-!1 = !{!"<stdin>", !"PATTERN"}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 (trunk 209871)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !14, globals: !2, imports: !2)
+!1 = !DIFile(filename: "<stdin>", directory: "PATTERN")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x13\00vector\0021\008\008\000\000\000", !5, null, null, !6, null, null, !"_ZTS6vector"} ; [ DW_TAG_structure_type ] [vector] [line 21, size 8, align 8, offset 0] [def] [from ]
-!5 = !{!"linezero.cc", !"PATTERN"}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "vector", line: 21, size: 8, align: 8, file: !5, elements: !6, identifier: "_ZTS6vector")
+!5 = !DIFile(filename: "linezero.cc", directory: "PATTERN")
 !6 = !{!7, !13}
-!7 = !{!"0x2e\00begin\00begin\00_ZN6vector5beginEv\0025\000\000\000\006\00256\000\0025", !5, !"_ZTS6vector", !8, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 25] [begin]
-!8 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !9, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = !DISubprogram(name: "begin", linkageName: "_ZN6vector5beginEv", line: 25, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 25, file: !5, scope: !"_ZTS6vector", type: !8)
+!8 = !DISubroutineType(types: !9)
 !9 = !{!10, !12}
-!10 = !{!"0xf\00\000\0064\0064\000\000", null, null, !11} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char]
-!11 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
-!12 = !{!"0xf\00\000\0064\0064\000\001088", null, null, !"_ZTS6vector"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS6vector]
-!13 = !{!"0x2e\00end\00end\00_ZN6vector3endEv\0026\000\000\000\006\00256\000\0026", !5, !"_ZTS6vector", !8, null, null, null, i32 0, null} ; [ DW_TAG_subprogram ] [line 26] [end]
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !11)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial | DIFlagObjectPointer, baseType: !"_ZTS6vector")
+!13 = !DISubprogram(name: "end", linkageName: "_ZN6vector3endEv", line: 26, isLocal: false, isDefinition: false, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 26, file: !5, scope: !"_ZTS6vector", type: !8)
 !14 = !{!15, !20}
-!15 = !{!"0x2e\00test\00test\00_Z4testv\0050\000\001\000\006\00256\000\0050", !5, !16, !17, null, i32 ()* @_Z4testv, null, null, !2} ; [ DW_TAG_subprogram ] [line 50] [def] [test]
-!16 = !{!"0x29", !5}         ; [ DW_TAG_file_type ] [./linezero.cc]
-!17 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !18, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!15 = !DISubprogram(name: "test", linkageName: "_Z4testv", line: 50, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 50, file: !5, scope: !16, type: !17, function: i32 ()* @_Z4testv, variables: !2)
+!16 = !DIFile(filename: "linezero.cc", directory: "PATTERN")
+!17 = !DISubroutineType(types: !18)
 !18 = !{!19}
-!19 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!20 = !{!"0x2e\00f1\00f1\00_Z2f1v\0054\000\001\000\006\00256\000\0054", !5, !16, !21, null, void ()* @_Z2f1v, null, null, !2} ; [ DW_TAG_subprogram ] [line 54] [def] [f1]
-!21 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !22, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!19 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!20 = !DISubprogram(name: "f1", linkageName: "_Z2f1v", line: 54, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 54, file: !5, scope: !16, type: !21, function: void ()* @_Z2f1v, variables: !2)
+!21 = !DISubroutineType(types: !22)
 !22 = !{null}
 !23 = !{i32 2, !"Dwarf Version", i32 4}
-!24 = !{i32 2, !"Debug Info Version", i32 2}
+!24 = !{i32 2, !"Debug Info Version", i32 3}
 !25 = !{!"PATTERN/linezero.o", !0}
 !26 = !{!"clang version 3.5.0 (trunk 209871)"}
-!27 = !{!"0x100\00__range\000\0064", !28, null, !29} ; [ DW_TAG_auto_variable ] [__range] [line 0]
-!28 = !{!"0xb\0051\000\000", !5, !15} ; [ DW_TAG_lexical_block ] [./linezero.cc]
-!29 = !{!"0x42\00\000\000\000\000\000", null, null, !"_ZTS6vector"} ; [ DW_TAG_rvalue_reference_type ] [line 0, size 0, align 0, offset 0] [from _ZTS6vector]
-!30 = !MDLocation(line: 0, scope: !28)
-!31 = !MDLocation(line: 51, scope: !28)
-!32 = !{!"0x100\00__begin\000\0064", !28, null, !10} ; [ DW_TAG_auto_variable ] [__begin] [line 0]
-!33 = !{!"0x100\00__end\000\0064", !28, null, !10} ; [ DW_TAG_auto_variable ] [__end] [line 0]
-!34 = !MDLocation(line: 51, scope: !35)
-!35 = !{!"0xb\0051\000\005", !5, !36} ; [ DW_TAG_lexical_block ] [./linezero.cc]
-!36 = !{!"0xb\0051\000\001", !5, !28} ; [ DW_TAG_lexical_block ] [./linezero.cc]
-!37 = !{!"0x100\00spec\0051\000", !28, !16, !11} ; [ DW_TAG_auto_variable ] [spec] [line 51]
-!38 = !MDLocation(line: 51, scope: !39)
-!39 = !{!"0xb\0051\000\002", !5, !28} ; [ DW_TAG_lexical_block ] [./linezero.cc]
-!40 = !MDLocation(line: 51, scope: !41)
-!41 = !{!"0xb\0051\000\004", !5, !28} ; [ DW_TAG_lexical_block ] [./linezero.cc]
-!42 = !MDLocation(line: 51, scope: !43)
-!43 = !{!"0xb\0051\000\003", !5, !28} ; [ DW_TAG_lexical_block ] [./linezero.cc]
-!44 = !MDLocation(line: 52, scope: !15)
-!45 = !MDLocation(line: 54, scope: !20)
+!27 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "__range", flags: DIFlagArtificial, scope: !28, type: !29)
+!28 = distinct !DILexicalBlock(line: 51, column: 0, file: !5, scope: !15)
+!29 = !DIDerivedType(tag: DW_TAG_rvalue_reference_type, baseType: !"_ZTS6vector")
+!30 = !DILocation(line: 0, scope: !28)
+!31 = !DILocation(line: 51, scope: !28)
+!32 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "__begin", flags: DIFlagArtificial, scope: !28, type: !10)
+!33 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "__end", flags: DIFlagArtificial, scope: !28, type: !10)
+!34 = !DILocation(line: 51, scope: !35)
+!35 = distinct !DILexicalBlock(line: 51, column: 0, file: !5, scope: !36)
+!36 = distinct !DILexicalBlock(line: 51, column: 0, file: !5, scope: !28)
+!37 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "spec", line: 51, scope: !28, file: !16, type: !11)
+!38 = !DILocation(line: 51, scope: !39)
+!39 = distinct !DILexicalBlock(line: 51, column: 0, file: !5, scope: !28)
+!40 = !DILocation(line: 51, scope: !41)
+!41 = distinct !DILexicalBlock(line: 51, column: 0, file: !5, scope: !28)
+!42 = !DILocation(line: 51, scope: !43)
+!43 = distinct !DILexicalBlock(line: 51, column: 0, file: !5, scope: !28)
+!44 = !DILocation(line: 52, scope: !15)
+!45 = !DILocation(line: 54, scope: !20)
diff --git a/test/Transforms/GCOVProfiling/linkagename.ll b/test/Transforms/GCOVProfiling/linkagename.ll
index c30d4a61ced4..7a4119802c9a 100644
--- a/test/Transforms/GCOVProfiling/linkagename.ll
+++ b/test/Transforms/GCOVProfiling/linkagename.ll
@@ -13,15 +13,15 @@ entry:
 !llvm.module.flags = !{!10}
 !llvm.gcov = !{!9}
 
-!0 = !{!"0x11\004\00clang version 3.3 (trunk 177323)\000\00\000\00\000", !2, !3, !3, !4, !3,  !3} ; [ DW_TAG_compile_unit ] [/home/nlewycky/hello.cc] [DW_LANG_C_plus_plus]
-!1 = !{!"0x29", !2}          ; [ DW_TAG_file_type ] [/home/nlewycky/hello.cc]
-!2 = !{!"hello.cc", !"/home/nlewycky"}
-!3 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 (trunk 177323)", isOptimized: false, emissionKind: 0, file: !2, enums: !3, retainedTypes: !3, subprograms: !4, globals: !3, imports:  !3)
+!1 = !DIFile(filename: "hello.cc", directory: "/home/nlewycky")
+!2 = !DIFile(filename: "hello.cc", directory: "/home/nlewycky")
+!3 = !{}
 !4 = !{!5}
-!5 = !{!"0x2e\00foo\00foo\00_Z3foov\001\000\001\000\006\00256\000\001", !1, !1, !6, null, void ()* @_Z3foov, null, null, !3} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "foo", linkageName: "_Z3foov", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !1, type: !6, function: void ()* @_Z3foov, variables: !3)
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
-!8 = !MDLocation(line: 1, scope: !5)
+!8 = !DILocation(line: 1, scope: !5)
 
 
-!10 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/GCOVProfiling/return-block.ll b/test/Transforms/GCOVProfiling/return-block.ll
index fce374a0a18b..38b5b75e3c2d 100644
--- a/test/Transforms/GCOVProfiling/return-block.ll
+++ b/test/Transforms/GCOVProfiling/return-block.ll
@@ -18,13 +18,13 @@ target triple = "x86_64-unknown-linux-gnu"
 ; Function Attrs: nounwind uwtable
 define void @test() #0 {
 entry:
-  tail call void (...)* @f() #2, !dbg !14
-  %0 = load i32* @A, align 4, !dbg !15
+  tail call void (...) @f() #2, !dbg !14
+  %0 = load i32, i32* @A, align 4, !dbg !15
   %tobool = icmp eq i32 %0, 0, !dbg !15
   br i1 %tobool, label %if.end, label %if.then, !dbg !15
 
 if.then:                                          ; preds = %entry
-  tail call void (...)* @g() #2, !dbg !16
+  tail call void (...) @g() #2, !dbg !16
   br label %if.end, !dbg !16
 
 if.end:                                           ; preds = %entry, %if.then
@@ -44,25 +44,25 @@ attributes #2 = { nounwind }
 !llvm.module.flags = !{!11, !12}
 !llvm.ident = !{!13}
 
-!0 = !{!"0x11\0012\00clang version 3.6.0 (trunk 223182)\001\00\000\00\001", !1, !2, !2, !3, !8, !2} ; [ DW_TAG_compile_unit ] [return-block.c] [DW_LANG_C99]
-!1 = !{!".../llvm/test/Transforms/GCOVProfiling/return-block.ll", !""}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.6.0 (trunk 223182)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !8, imports: !2)
+!1 = !DIFile(filename: ".../llvm/test/Transforms/GCOVProfiling/return-block.ll", directory: "")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00test\00test\00\005\000\001\000\000\000\001\005", !1, !5, !6, null, void ()* @test, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [test]
-!5 = !{!"0x29", !1}    ; [ DW_TAG_file_type ] [return-block.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "test", line: 5, isLocal: false, isDefinition: true, isOptimized: true, scopeLine: 5, file: !1, scope: !5, type: !6, function: void ()* @test, variables: !2)
+!5 = !DIFile(filename: ".../llvm/test/Transforms/GCOVProfiling/return-block.ll", directory: "")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null}
 !8 = !{!9}
-!9 = !{!"0x34\00A\00A\00\003\000\001", null, !5, !10, i32* @A, null} ; [ DW_TAG_variable ] [A] [line 3] [def]
-!10 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = !DIGlobalVariable(name: "A", line: 3, isLocal: false, isDefinition: true, scope: null, file: !5, type: !10, variable: i32* @A)
+!10 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !11 = !{i32 2, !"Dwarf Version", i32 4}
-!12 = !{i32 2, !"Debug Info Version", i32 2}
+!12 = !{i32 2, !"Debug Info Version", i32 3}
 !13 = !{!"clang version 3.6.0 (trunk 223182)"}
-!14 = !MDLocation(line: 6, column: 3, scope: !4)
-!15 = !MDLocation(line: 7, column: 7, scope: !4)
-!16 = !MDLocation(line: 8, column: 5, scope: !17)
-!17 = !{!"0xb\007\007\000", !1, !4} ; [ DW_TAG_lexical_block ] [return-block.c]
-!18 = !MDLocation(line: 9, column: 1, scope: !4)
+!14 = !DILocation(line: 6, column: 3, scope: !4)
+!15 = !DILocation(line: 7, column: 7, scope: !4)
+!16 = !DILocation(line: 8, column: 5, scope: !17)
+!17 = distinct !DILexicalBlock(line: 7, column: 7, file: !1, scope: !4)
+!18 = !DILocation(line: 9, column: 1, scope: !4)
 
 ; There should be no destination edges for the exit block.
 ; CHECK: Block : 1 Counter : 0
diff --git a/test/Transforms/GCOVProfiling/version.ll b/test/Transforms/GCOVProfiling/version.ll
index 9436bd657da3..487e72123cb0 100644
--- a/test/Transforms/GCOVProfiling/version.ll
+++ b/test/Transforms/GCOVProfiling/version.ll
@@ -16,15 +16,15 @@ define void @test() {
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!12}
 
-!0 = !{!"0x11\004\00clang version 3.3 (trunk 176994)\000\00\000\00\000", !11, !3, !3, !4, !3, null} ; [ DW_TAG_compile_unit ] [./version] [DW_LANG_C_plus_plus]
-!2 = !{!"0x29", !11} ; [ DW_TAG_file_type ]
-!3 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.3 (trunk 176994)", isOptimized: false, emissionKind: 0, file: !11, enums: !3, retainedTypes: !3, subprograms: !4, globals: !3)
+!2 = !DIFile(filename: "version", directory: "/usr/local/google/home/nlewycky")
+!3 = !{}
 !4 = !{!5}
-!5 = !{!"0x2e\00test\00test\00\001\000\001\000\006\00256\000\001", !10, !6, !7, null, void ()* @test, null, null, !3} ; [ DW_TAG_subprogram ] [line 1] [def] [test]
-!6 = !{!"0x29", !10} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !3, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!8 = !MDLocation(line: 1, scope: !5)
+!5 = !DISubprogram(name: "test", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !10, scope: !6, type: !7, function: void ()* @test, variables: !3)
+!6 = !DIFile(filename: "<stdin>", directory: ".")
+!7 = !DISubroutineType(types: !{null})
+!8 = !DILocation(line: 1, scope: !5)
 ;; !9 is added through the echo line at the top.
-!10 = !{!"<stdin>", !"."}
-!11 = !{!"version", !"/usr/local/google/home/nlewycky"}
-!12 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !DIFile(filename: "<stdin>", directory: ".")
+!11 = !DIFile(filename: "version", directory: "/usr/local/google/home/nlewycky")
+!12 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/GVN/2007-07-25-DominatedLoop.ll b/test/Transforms/GVN/2007-07-25-DominatedLoop.ll
index ad580ce1677d..10d1e229b12a 100644
--- a/test/Transforms/GVN/2007-07-25-DominatedLoop.ll
+++ b/test/Transforms/GVN/2007-07-25-DominatedLoop.ll
@@ -71,11 +71,11 @@ cond_true23.i:		; preds = %Perl_safefree.exit68
 	ret void
 
 cond_next150:		; preds = %Perl_safefree.exit68
-	%tmp16092 = load i32* @PL_sv_count, align 4		; <i32> [#uses=0]
+	%tmp16092 = load i32, i32* @PL_sv_count, align 4		; <i32> [#uses=0]
 	br label %cond_next165
 
 bb157:		; preds = %cond_next165
-	%tmp158 = load i32* @PL_sv_count, align 4		; <i32> [#uses=0]
+	%tmp158 = load i32, i32* @PL_sv_count, align 4		; <i32> [#uses=0]
 	br label %cond_next165
 
 cond_next165:		; preds = %bb157, %cond_next150
diff --git a/test/Transforms/GVN/2007-07-25-InfiniteLoop.ll b/test/Transforms/GVN/2007-07-25-InfiniteLoop.ll
index 7e9c982de51c..0ffb34c39b4f 100644
--- a/test/Transforms/GVN/2007-07-25-InfiniteLoop.ll
+++ b/test/Transforms/GVN/2007-07-25-InfiniteLoop.ll
@@ -9,6 +9,6 @@ entry:
 	br label %bb
 
 bb:		; preds = %bb, %entry
-	%tmp10 = load %struct.INT2** @blkshifts, align 4		; <%struct.INT2*> [#uses=0]
+	%tmp10 = load %struct.INT2*, %struct.INT2** @blkshifts, align 4		; <%struct.INT2*> [#uses=0]
 	br label %bb
 }
diff --git a/test/Transforms/GVN/2007-07-25-Loop.ll b/test/Transforms/GVN/2007-07-25-Loop.ll
index 6a9f58e02f65..54c0d982de4d 100644
--- a/test/Transforms/GVN/2007-07-25-Loop.ll
+++ b/test/Transforms/GVN/2007-07-25-Loop.ll
@@ -10,6 +10,6 @@ bb278:		; preds = %bb278, %entry
 	br i1 false, label %bb278, label %bb344
 
 bb344:		; preds = %bb278, %entry
-	%tmp38758 = load i16* null, align 2		; <i16> [#uses=0]
+	%tmp38758 = load i16, i16* null, align 2		; <i16> [#uses=0]
 	ret void
 }
diff --git a/test/Transforms/GVN/2007-07-25-NestedLoop.ll b/test/Transforms/GVN/2007-07-25-NestedLoop.ll
index c6d7750d6272..8f2c182faa89 100644
--- a/test/Transforms/GVN/2007-07-25-NestedLoop.ll
+++ b/test/Transforms/GVN/2007-07-25-NestedLoop.ll
@@ -10,27 +10,27 @@ bb534.preheader:		; preds = %entry
 	ret %struct.TypHeader* null
 
 bb556.preheader:		; preds = %entry
-	%tmp56119 = getelementptr %struct.TypHeader* %hdR, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp56220 = load i32* %tmp56119		; <i32> [#uses=0]
+	%tmp56119 = getelementptr %struct.TypHeader, %struct.TypHeader* %hdR, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp56220 = load i32, i32* %tmp56119		; <i32> [#uses=0]
 	br i1 false, label %bb.nph23, label %bb675.preheader
 
 bb.nph23:		; preds = %bb556.preheader
 	ret %struct.TypHeader* null
 
 bb656:		; preds = %bb675.outer, %bb656
-	%tmp678 = load i32* %tmp677		; <i32> [#uses=0]
+	%tmp678 = load i32, i32* %tmp677		; <i32> [#uses=0]
 	br i1 false, label %bb684, label %bb656
 
 bb684:		; preds = %bb675.outer, %bb656
 	br i1 false, label %bb924.preheader, label %bb675.outer
 
 bb675.outer:		; preds = %bb675.preheader, %bb684
-	%tmp67812 = load i32* %tmp67711		; <i32> [#uses=0]
+	%tmp67812 = load i32, i32* %tmp67711		; <i32> [#uses=0]
 	br i1 false, label %bb684, label %bb656
 
 bb675.preheader:		; preds = %bb556.preheader
-	%tmp67711 = getelementptr %struct.TypHeader* %hdR, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp677 = getelementptr %struct.TypHeader* %hdR, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp67711 = getelementptr %struct.TypHeader, %struct.TypHeader* %hdR, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp677 = getelementptr %struct.TypHeader, %struct.TypHeader* %hdR, i32 0, i32 0		; <i32*> [#uses=1]
 	br label %bb675.outer
 
 bb924.preheader:		; preds = %bb684
diff --git a/test/Transforms/GVN/2007-07-25-SinglePredecessor.ll b/test/Transforms/GVN/2007-07-25-SinglePredecessor.ll
index ecff657ed389..d7e6c20324f1 100644
--- a/test/Transforms/GVN/2007-07-25-SinglePredecessor.ll
+++ b/test/Transforms/GVN/2007-07-25-SinglePredecessor.ll
@@ -12,7 +12,7 @@
 
 define i32 @_ZNK21mrZEllipticalCylinder10viewingHitERK6ggRay3dddR18mrViewingHitRecordR16ggMaterialRecord(%struct.mrXEllipticalCylinder* %this, %struct.ggBox3* %ray, double %unnamed_arg, double %tmin, double %tmax, %struct.mrViewingHitRecord* %VHR, %struct.ggMaterialRecord* %unnamed_arg2) {
 entry:
-	%tmp80.i = getelementptr %struct.mrViewingHitRecord* %VHR, i32 0, i32 1, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp80.i = getelementptr %struct.mrViewingHitRecord, %struct.mrViewingHitRecord* %VHR, i32 0, i32 1, i32 0, i32 0		; <double*> [#uses=1]
 	store double 0.000000e+00, double* %tmp80.i
 	br i1 false, label %return, label %cond_next.i
 
@@ -20,8 +20,8 @@ cond_next.i:		; preds = %entry
 	br i1 false, label %return, label %cond_true
 
 cond_true:		; preds = %cond_next.i
-	%tmp3.i8 = getelementptr %struct.mrViewingHitRecord* %VHR, i32 0, i32 1, i32 0, i32 0		; <double*> [#uses=1]
-	%tmp46 = load double* %tmp3.i8		; <double> [#uses=0]
+	%tmp3.i8 = getelementptr %struct.mrViewingHitRecord, %struct.mrViewingHitRecord* %VHR, i32 0, i32 1, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp46 = load double, double* %tmp3.i8		; <double> [#uses=0]
 	ret i32 1
 
 return:		; preds = %cond_next.i, %entry
diff --git a/test/Transforms/GVN/2007-07-26-InterlockingLoops.ll b/test/Transforms/GVN/2007-07-26-InterlockingLoops.ll
index 5a15f0e43aaf..98e0024adf5b 100644
--- a/test/Transforms/GVN/2007-07-26-InterlockingLoops.ll
+++ b/test/Transforms/GVN/2007-07-26-InterlockingLoops.ll
@@ -5,7 +5,7 @@
 define i32 @NextRootMove(i32 %wtm, i32 %x, i32 %y, i32 %z) {
 entry:
         %A = alloca i32*
-	%tmp17618 = load i32** getelementptr ([65 x i32*]* @last, i32 0, i32 1), align 4
+	%tmp17618 = load i32*, i32** getelementptr ([65 x i32*], [65 x i32*]* @last, i32 0, i32 1), align 4
         store i32* %tmp17618, i32** %A
 ; CHECK: entry:
 ; CHECK-NEXT: alloca i32
@@ -19,7 +19,7 @@ cond_true116:
 	br i1 %cmp, label %cond_true128, label %cond_true145
 
 cond_true128:
-	%tmp17625 = load i32** getelementptr ([65 x i32*]* @last, i32 0, i32 1), align 4
+	%tmp17625 = load i32*, i32** getelementptr ([65 x i32*], [65 x i32*]* @last, i32 0, i32 1), align 4
         store i32* %tmp17625, i32** %A
    %cmp1 = icmp eq i32 %x, %z
 	br i1 %cmp1 , label %bb98.backedge, label %return.loopexit
@@ -28,7 +28,7 @@ bb98.backedge:
 	br label %cond_true116
 
 cond_true145:
-	%tmp17631 = load i32** getelementptr ([65 x i32*]* @last, i32 0, i32 1), align 4
+	%tmp17631 = load i32*, i32** getelementptr ([65 x i32*], [65 x i32*]* @last, i32 0, i32 1), align 4
         store i32* %tmp17631, i32** %A
 	br i1 false, label %bb98.backedge, label %return.loopexit
 
diff --git a/test/Transforms/GVN/2007-07-26-NonRedundant.ll b/test/Transforms/GVN/2007-07-26-NonRedundant.ll
index 7579e8aff08b..211830a39af3 100644
--- a/test/Transforms/GVN/2007-07-26-NonRedundant.ll
+++ b/test/Transforms/GVN/2007-07-26-NonRedundant.ll
@@ -11,6 +11,6 @@ cond_next:		; preds = %entry
 	br label %bb19
 
 bb19:		; preds = %cond_next, %entry
-	%tmp29 = load i32* @bsLive, align 4		; <i32> [#uses=0]
+	%tmp29 = load i32, i32* @bsLive, align 4		; <i32> [#uses=0]
 	ret i32 0
 }
diff --git a/test/Transforms/GVN/2007-07-26-PhiErasure.ll b/test/Transforms/GVN/2007-07-26-PhiErasure.ll
index d898ab8e2fa2..82af521ab3d6 100644
--- a/test/Transforms/GVN/2007-07-26-PhiErasure.ll
+++ b/test/Transforms/GVN/2007-07-26-PhiErasure.ll
@@ -9,7 +9,7 @@
 
 define i32 @reload(%struct.rtx_def* %first, i32 %global, %struct.FILE* %dumpfile) {
 cond_next2835.1:		; preds = %cond_next2861
-	%tmp2922 = load i32* @n_spills, align 4		; <i32> [#uses=0]
+	%tmp2922 = load i32, i32* @n_spills, align 4		; <i32> [#uses=0]
 	br label %bb2928
 
 bb2928:		; preds = %cond_next2835.1, %cond_next2943
@@ -22,7 +22,7 @@ cond_next2943:		; preds = %cond_true2935, %bb2928
 	br i1 false, label %bb2982.preheader, label %bb2928
 
 bb2982.preheader:		; preds = %cond_next2943
-	%tmp298316 = load i32* @n_spills, align 4		; <i32> [#uses=0]
+	%tmp298316 = load i32, i32* @n_spills, align 4		; <i32> [#uses=0]
 	ret i32 %tmp298316
 
 }
diff --git a/test/Transforms/GVN/2007-07-30-PredIDom.ll b/test/Transforms/GVN/2007-07-30-PredIDom.ll
index 5cb6bb3ecffb..3a7eec7d1424 100644
--- a/test/Transforms/GVN/2007-07-30-PredIDom.ll
+++ b/test/Transforms/GVN/2007-07-30-PredIDom.ll
@@ -269,6 +269,6 @@ bb970:		; preds = %entry
 	br label %return
 
 return:		; preds = %0, %cond_next967, %cond_next922, %cond_next879, %cond_next807, %cond_next630, %cond_next415, %cond_next267, %cond_next191, %bb
-	%retval980 = load i8** null		; <i8*> [#uses=1]
+	%retval980 = load i8*, i8** null		; <i8*> [#uses=1]
 	ret i8* %retval980
 }
diff --git a/test/Transforms/GVN/2007-07-31-NoDomInherit.ll b/test/Transforms/GVN/2007-07-31-NoDomInherit.ll
index 5018a0747aff..b2e4c64ee770 100644
--- a/test/Transforms/GVN/2007-07-31-NoDomInherit.ll
+++ b/test/Transforms/GVN/2007-07-31-NoDomInherit.ll
@@ -149,27 +149,27 @@ entry:
 	br label %bb91
 
 bb:		; preds = %cond_next97
-	%tmp1 = load i32* @numi		; <i32> [#uses=1]
-	%tmp2 = getelementptr [44 x i8]* @.str43, i32 0, i32 0		; <i8*> [#uses=1]
-	%tmp3 = call i32 (i8*, ...)* @printf( i8* %tmp2, i32 %tmp1 )		; <i32> [#uses=0]
+	%tmp1 = load i32, i32* @numi		; <i32> [#uses=1]
+	%tmp2 = getelementptr [44 x i8], [44 x i8]* @.str43, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp3 = call i32 (i8*, ...) @printf( i8* %tmp2, i32 %tmp1 )		; <i32> [#uses=0]
 	store i32 0, i32* %i
 	br label %bb13
 
 bb4:		; preds = %bb13
-	%tmp5 = load i32* %i		; <i32> [#uses=1]
-	%tmp6 = load i32* %i		; <i32> [#uses=1]
-	%tmp7 = getelementptr [17 x i32]* @trialx, i32 0, i32 %tmp6		; <i32*> [#uses=1]
-	%tmp8 = load i32* %tmp7		; <i32> [#uses=1]
+	%tmp5 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp6 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp7 = getelementptr [17 x i32], [17 x i32]* @trialx, i32 0, i32 %tmp6		; <i32*> [#uses=1]
+	%tmp8 = load i32, i32* %tmp7		; <i32> [#uses=1]
 	%tmp9 = call i32 @userfun( i32 %tmp8 )		; <i32> [#uses=1]
-	%tmp10 = getelementptr [17 x i32]* @correct_result, i32 0, i32 %tmp5		; <i32*> [#uses=1]
+	%tmp10 = getelementptr [17 x i32], [17 x i32]* @correct_result, i32 0, i32 %tmp5		; <i32*> [#uses=1]
 	store i32 %tmp9, i32* %tmp10
-	%tmp11 = load i32* %i		; <i32> [#uses=1]
+	%tmp11 = load i32, i32* %i		; <i32> [#uses=1]
 	%tmp12 = add i32 %tmp11, 1		; <i32> [#uses=1]
 	store i32 %tmp12, i32* %i
 	br label %bb13
 
 bb13:		; preds = %bb4, %bb
-	%tmp14 = load i32* %i		; <i32> [#uses=1]
+	%tmp14 = load i32, i32* %i		; <i32> [#uses=1]
 	%tmp15 = icmp sle i32 %tmp14, 16		; <i1> [#uses=1]
 	%tmp1516 = zext i1 %tmp15 to i32		; <i32> [#uses=1]
 	%toBool = icmp ne i32 %tmp1516, 0		; <i1> [#uses=1]
@@ -180,47 +180,47 @@ bb17:		; preds = %bb13
 	br label %bb49
 
 bb18:		; preds = %bb49
-	%tmp19 = load i32* %i		; <i32> [#uses=1]
-	%tmp20 = getelementptr [5 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %tmp19		; <{ i32, [3 x i32] }*> [#uses=1]
-	%tmp21 = getelementptr { i32, [3 x i32] }* %tmp20, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp19 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp20 = getelementptr [5 x { i32, [3 x i32] }], [5 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %tmp19		; <{ i32, [3 x i32] }*> [#uses=1]
+	%tmp21 = getelementptr { i32, [3 x i32] }, { i32, [3 x i32] }* %tmp20, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp21
-	%tmp22 = load i32* %i		; <i32> [#uses=1]
-	%tmp23 = getelementptr [13 x %struct.anon]* @isa, i32 0, i32 0		; <%struct.anon*> [#uses=1]
-	%tmp24 = getelementptr %struct.anon* %tmp23, i32 0, i32 3		; <[3 x i32]*> [#uses=1]
-	%tmp25 = getelementptr [3 x i32]* %tmp24, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp26 = load i32* %tmp25		; <i32> [#uses=1]
-	%tmp27 = getelementptr [5 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %tmp22		; <{ i32, [3 x i32] }*> [#uses=1]
-	%tmp28 = getelementptr { i32, [3 x i32] }* %tmp27, i32 0, i32 1		; <[3 x i32]*> [#uses=1]
-	%tmp29 = getelementptr [3 x i32]* %tmp28, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp22 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp23 = getelementptr [13 x %struct.anon], [13 x %struct.anon]* @isa, i32 0, i32 0		; <%struct.anon*> [#uses=1]
+	%tmp24 = getelementptr %struct.anon, %struct.anon* %tmp23, i32 0, i32 3		; <[3 x i32]*> [#uses=1]
+	%tmp25 = getelementptr [3 x i32], [3 x i32]* %tmp24, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp26 = load i32, i32* %tmp25		; <i32> [#uses=1]
+	%tmp27 = getelementptr [5 x { i32, [3 x i32] }], [5 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %tmp22		; <{ i32, [3 x i32] }*> [#uses=1]
+	%tmp28 = getelementptr { i32, [3 x i32] }, { i32, [3 x i32] }* %tmp27, i32 0, i32 1		; <[3 x i32]*> [#uses=1]
+	%tmp29 = getelementptr [3 x i32], [3 x i32]* %tmp28, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 %tmp26, i32* %tmp29
-	%tmp30 = load i32* %i		; <i32> [#uses=1]
-	%tmp31 = getelementptr [13 x %struct.anon]* @isa, i32 0, i32 0		; <%struct.anon*> [#uses=1]
-	%tmp32 = getelementptr %struct.anon* %tmp31, i32 0, i32 3		; <[3 x i32]*> [#uses=1]
-	%tmp33 = getelementptr [3 x i32]* %tmp32, i32 0, i32 1		; <i32*> [#uses=1]
-	%tmp34 = load i32* %tmp33		; <i32> [#uses=1]
-	%tmp35 = getelementptr [5 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %tmp30		; <{ i32, [3 x i32] }*> [#uses=1]
-	%tmp36 = getelementptr { i32, [3 x i32] }* %tmp35, i32 0, i32 1		; <[3 x i32]*> [#uses=1]
-	%tmp37 = getelementptr [3 x i32]* %tmp36, i32 0, i32 1		; <i32*> [#uses=1]
+	%tmp30 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp31 = getelementptr [13 x %struct.anon], [13 x %struct.anon]* @isa, i32 0, i32 0		; <%struct.anon*> [#uses=1]
+	%tmp32 = getelementptr %struct.anon, %struct.anon* %tmp31, i32 0, i32 3		; <[3 x i32]*> [#uses=1]
+	%tmp33 = getelementptr [3 x i32], [3 x i32]* %tmp32, i32 0, i32 1		; <i32*> [#uses=1]
+	%tmp34 = load i32, i32* %tmp33		; <i32> [#uses=1]
+	%tmp35 = getelementptr [5 x { i32, [3 x i32] }], [5 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %tmp30		; <{ i32, [3 x i32] }*> [#uses=1]
+	%tmp36 = getelementptr { i32, [3 x i32] }, { i32, [3 x i32] }* %tmp35, i32 0, i32 1		; <[3 x i32]*> [#uses=1]
+	%tmp37 = getelementptr [3 x i32], [3 x i32]* %tmp36, i32 0, i32 1		; <i32*> [#uses=1]
 	store i32 %tmp34, i32* %tmp37
-	%tmp38 = load i32* %i		; <i32> [#uses=1]
-	%tmp39 = getelementptr [13 x %struct.anon]* @isa, i32 0, i32 0		; <%struct.anon*> [#uses=1]
-	%tmp40 = getelementptr %struct.anon* %tmp39, i32 0, i32 3		; <[3 x i32]*> [#uses=1]
-	%tmp41 = getelementptr [3 x i32]* %tmp40, i32 0, i32 2		; <i32*> [#uses=1]
-	%tmp42 = load i32* %tmp41		; <i32> [#uses=1]
-	%tmp43 = getelementptr [5 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %tmp38		; <{ i32, [3 x i32] }*> [#uses=1]
-	%tmp44 = getelementptr { i32, [3 x i32] }* %tmp43, i32 0, i32 1		; <[3 x i32]*> [#uses=1]
-	%tmp45 = getelementptr [3 x i32]* %tmp44, i32 0, i32 2		; <i32*> [#uses=1]
+	%tmp38 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp39 = getelementptr [13 x %struct.anon], [13 x %struct.anon]* @isa, i32 0, i32 0		; <%struct.anon*> [#uses=1]
+	%tmp40 = getelementptr %struct.anon, %struct.anon* %tmp39, i32 0, i32 3		; <[3 x i32]*> [#uses=1]
+	%tmp41 = getelementptr [3 x i32], [3 x i32]* %tmp40, i32 0, i32 2		; <i32*> [#uses=1]
+	%tmp42 = load i32, i32* %tmp41		; <i32> [#uses=1]
+	%tmp43 = getelementptr [5 x { i32, [3 x i32] }], [5 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %tmp38		; <{ i32, [3 x i32] }*> [#uses=1]
+	%tmp44 = getelementptr { i32, [3 x i32] }, { i32, [3 x i32] }* %tmp43, i32 0, i32 1		; <[3 x i32]*> [#uses=1]
+	%tmp45 = getelementptr [3 x i32], [3 x i32]* %tmp44, i32 0, i32 2		; <i32*> [#uses=1]
 	store i32 %tmp42, i32* %tmp45
-	%tmp46 = load i32* %i		; <i32> [#uses=1]
+	%tmp46 = load i32, i32* %i		; <i32> [#uses=1]
 	call void @fix_operands( i32 %tmp46 )
-	%tmp47 = load i32* %i		; <i32> [#uses=1]
+	%tmp47 = load i32, i32* %i		; <i32> [#uses=1]
 	%tmp48 = add i32 %tmp47, 1		; <i32> [#uses=1]
 	store i32 %tmp48, i32* %i
 	br label %bb49
 
 bb49:		; preds = %bb18, %bb17
-	%tmp50 = load i32* @numi		; <i32> [#uses=1]
-	%tmp51 = load i32* %i		; <i32> [#uses=1]
+	%tmp50 = load i32, i32* @numi		; <i32> [#uses=1]
+	%tmp51 = load i32, i32* %i		; <i32> [#uses=1]
 	%tmp52 = icmp slt i32 %tmp51, %tmp50		; <i1> [#uses=1]
 	%tmp5253 = zext i1 %tmp52 to i32		; <i32> [#uses=1]
 	%toBool54 = icmp ne i32 %tmp5253, 0		; <i1> [#uses=1]
@@ -229,10 +229,10 @@ bb49:		; preds = %bb18, %bb17
 bb55:		; preds = %bb49
 	%tmp56 = call i32 @search( )		; <i32> [#uses=1]
 	store i32 %tmp56, i32* %num_sol
-	%tmp57 = getelementptr [21 x i8]* @.str44, i32 0, i32 0		; <i8*> [#uses=1]
-	%tmp58 = load i32* %num_sol		; <i32> [#uses=1]
-	%tmp59 = call i32 (i8*, ...)* @printf( i8* %tmp57, i32 %tmp58 )		; <i32> [#uses=0]
-	%tmp60 = load i32* @counters		; <i32> [#uses=1]
+	%tmp57 = getelementptr [21 x i8], [21 x i8]* @.str44, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp58 = load i32, i32* %num_sol		; <i32> [#uses=1]
+	%tmp59 = call i32 (i8*, ...) @printf( i8* %tmp57, i32 %tmp58 )		; <i32> [#uses=0]
+	%tmp60 = load i32, i32* @counters		; <i32> [#uses=1]
 	%tmp61 = icmp ne i32 %tmp60, 0		; <i1> [#uses=1]
 	%tmp6162 = zext i1 %tmp61 to i32		; <i32> [#uses=1]
 	%toBool63 = icmp ne i32 %tmp6162, 0		; <i1> [#uses=1]
@@ -240,50 +240,50 @@ bb55:		; preds = %bb49
 
 cond_true:		; preds = %bb55
 	store i32 0, i32* %total
-	%tmp64 = getelementptr [12 x i8]* @.str45, i32 0, i32 0		; <i8*> [#uses=1]
-	%tmp65 = call i32 (i8*, ...)* @printf( i8* %tmp64 )		; <i32> [#uses=0]
+	%tmp64 = getelementptr [12 x i8], [12 x i8]* @.str45, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp65 = call i32 (i8*, ...) @printf( i8* %tmp64 )		; <i32> [#uses=0]
 	store i32 0, i32* %i
 	br label %bb79
 
 bb66:		; preds = %bb79
-	%tmp67 = load i32* %i		; <i32> [#uses=1]
-	%tmp68 = getelementptr [5 x i32]* @counter, i32 0, i32 %tmp67		; <i32*> [#uses=1]
-	%tmp69 = load i32* %tmp68		; <i32> [#uses=1]
-	%tmp70 = getelementptr [5 x i8]* @.str46, i32 0, i32 0		; <i8*> [#uses=1]
-	%tmp71 = call i32 (i8*, ...)* @printf( i8* %tmp70, i32 %tmp69 )		; <i32> [#uses=0]
-	%tmp72 = load i32* %i		; <i32> [#uses=1]
-	%tmp73 = getelementptr [5 x i32]* @counter, i32 0, i32 %tmp72		; <i32*> [#uses=1]
-	%tmp74 = load i32* %tmp73		; <i32> [#uses=1]
-	%tmp75 = load i32* %total		; <i32> [#uses=1]
+	%tmp67 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp68 = getelementptr [5 x i32], [5 x i32]* @counter, i32 0, i32 %tmp67		; <i32*> [#uses=1]
+	%tmp69 = load i32, i32* %tmp68		; <i32> [#uses=1]
+	%tmp70 = getelementptr [5 x i8], [5 x i8]* @.str46, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp71 = call i32 (i8*, ...) @printf( i8* %tmp70, i32 %tmp69 )		; <i32> [#uses=0]
+	%tmp72 = load i32, i32* %i		; <i32> [#uses=1]
+	%tmp73 = getelementptr [5 x i32], [5 x i32]* @counter, i32 0, i32 %tmp72		; <i32*> [#uses=1]
+	%tmp74 = load i32, i32* %tmp73		; <i32> [#uses=1]
+	%tmp75 = load i32, i32* %total		; <i32> [#uses=1]
 	%tmp76 = add i32 %tmp74, %tmp75		; <i32> [#uses=1]
 	store i32 %tmp76, i32* %total
-	%tmp77 = load i32* %i		; <i32> [#uses=1]
+	%tmp77 = load i32, i32* %i		; <i32> [#uses=1]
 	%tmp78 = add i32 %tmp77, 1		; <i32> [#uses=1]
 	store i32 %tmp78, i32* %i
 	br label %bb79
 
 bb79:		; preds = %bb66, %cond_true
-	%tmp80 = load i32* @numi		; <i32> [#uses=1]
-	%tmp81 = load i32* %i		; <i32> [#uses=1]
+	%tmp80 = load i32, i32* @numi		; <i32> [#uses=1]
+	%tmp81 = load i32, i32* %i		; <i32> [#uses=1]
 	%tmp82 = icmp slt i32 %tmp81, %tmp80		; <i1> [#uses=1]
 	%tmp8283 = zext i1 %tmp82 to i32		; <i32> [#uses=1]
 	%toBool84 = icmp ne i32 %tmp8283, 0		; <i1> [#uses=1]
 	br i1 %toBool84, label %bb66, label %bb85
 
 bb85:		; preds = %bb79
-	%tmp86 = getelementptr [12 x i8]* @.str47, i32 0, i32 0		; <i8*> [#uses=1]
-	%tmp87 = load i32* %total		; <i32> [#uses=1]
-	%tmp88 = call i32 (i8*, ...)* @printf( i8* %tmp86, i32 %tmp87 )		; <i32> [#uses=0]
+	%tmp86 = getelementptr [12 x i8], [12 x i8]* @.str47, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp87 = load i32, i32* %total		; <i32> [#uses=1]
+	%tmp88 = call i32 (i8*, ...) @printf( i8* %tmp86, i32 %tmp87 )		; <i32> [#uses=0]
 	br label %cond_next
 
 cond_next:		; preds = %bb85, %bb55
-	%tmp89 = load i32* @numi		; <i32> [#uses=1]
+	%tmp89 = load i32, i32* @numi		; <i32> [#uses=1]
 	%tmp90 = add i32 %tmp89, 1		; <i32> [#uses=1]
 	store i32 %tmp90, i32* @numi
 	br label %bb91
 
 bb91:		; preds = %cond_next, %entry
-	%tmp92 = load i32* @numi		; <i32> [#uses=1]
+	%tmp92 = load i32, i32* @numi		; <i32> [#uses=1]
 	%tmp93 = icmp sgt i32 %tmp92, 5		; <i1> [#uses=1]
 	%tmp9394 = zext i1 %tmp93 to i32		; <i32> [#uses=1]
 	%toBool95 = icmp ne i32 %tmp9394, 0		; <i1> [#uses=1]
@@ -293,7 +293,7 @@ cond_true96:		; preds = %bb91
 	br label %bb102
 
 cond_next97:		; preds = %bb91
-	%tmp98 = load i32* %num_sol		; <i32> [#uses=1]
+	%tmp98 = load i32, i32* %num_sol		; <i32> [#uses=1]
 	%tmp99 = icmp eq i32 %tmp98, 0		; <i1> [#uses=1]
 	%tmp99100 = zext i1 %tmp99 to i32		; <i32> [#uses=1]
 	%toBool101 = icmp ne i32 %tmp99100, 0		; <i1> [#uses=1]
@@ -301,12 +301,12 @@ cond_next97:		; preds = %bb91
 
 bb102:		; preds = %cond_next97, %cond_true96
 	store i32 0, i32* %tmp
-	%tmp103 = load i32* %tmp		; <i32> [#uses=1]
+	%tmp103 = load i32, i32* %tmp		; <i32> [#uses=1]
 	store i32 %tmp103, i32* %retval
 	br label %return
 
 return:		; preds = %bb102
-	%retval104 = load i32* %retval		; <i32> [#uses=1]
+	%retval104 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval104
 }
 
diff --git a/test/Transforms/GVN/2007-07-31-RedundantPhi.ll b/test/Transforms/GVN/2007-07-31-RedundantPhi.ll
index 13419d19e1d5..b285560e6a99 100644
--- a/test/Transforms/GVN/2007-07-31-RedundantPhi.ll
+++ b/test/Transforms/GVN/2007-07-31-RedundantPhi.ll
@@ -17,6 +17,6 @@ cond_false470:		; preds = %cond_next449
 	br label %cond_next698
 
 cond_next698:		; preds = %cond_true492
-	%tmp701 = load i16* @img_width, align 2		; <i16> [#uses=0]
+	%tmp701 = load i16, i16* @img_width, align 2		; <i16> [#uses=0]
 	ret i32 0
 }
diff --git a/test/Transforms/GVN/2008-02-12-UndefLoad.ll b/test/Transforms/GVN/2008-02-12-UndefLoad.ll
index de2aa614ff5d..a1aed867ec63 100644
--- a/test/Transforms/GVN/2008-02-12-UndefLoad.ll
+++ b/test/Transforms/GVN/2008-02-12-UndefLoad.ll
@@ -6,13 +6,13 @@
 define i32 @a() {
 entry:
         %c = alloca %struct.anon                ; <%struct.anon*> [#uses=2]
-        %tmp = getelementptr %struct.anon* %c, i32 0, i32 0             ; <i32*> [#uses=1]
-        %tmp1 = getelementptr i32* %tmp, i32 1          ; <i32*> [#uses=2]
-        %tmp2 = load i32* %tmp1, align 4                ; <i32> [#uses=1]
+        %tmp = getelementptr %struct.anon, %struct.anon* %c, i32 0, i32 0             ; <i32*> [#uses=1]
+        %tmp1 = getelementptr i32, i32* %tmp, i32 1          ; <i32*> [#uses=2]
+        %tmp2 = load i32, i32* %tmp1, align 4                ; <i32> [#uses=1]
         %tmp3 = or i32 %tmp2, 11                ; <i32> [#uses=1]
         %tmp4 = and i32 %tmp3, -21              ; <i32> [#uses=1]
         store i32 %tmp4, i32* %tmp1, align 4
-        %call = call i32 (...)* @x( %struct.anon* %c )          ; <i32> [#uses=0]
+        %call = call i32 (...) @x( %struct.anon* %c )          ; <i32> [#uses=0]
         ret i32 undef
 }
 
diff --git a/test/Transforms/GVN/2008-02-13-NewPHI.ll b/test/Transforms/GVN/2008-02-13-NewPHI.ll
index 80b519d14e9a..638939b15343 100644
--- a/test/Transforms/GVN/2008-02-13-NewPHI.ll
+++ b/test/Transforms/GVN/2008-02-13-NewPHI.ll
@@ -8,7 +8,7 @@ entry:
 	br label %bb33
 
 bb:		; preds = %bb33
-	%tmp27 = load float** %sx_addr, align 4		; <float*> [#uses=1]
+	%tmp27 = load float*, float** %sx_addr, align 4		; <float*> [#uses=1]
 	store float 0.000000e+00, float* %tmp27, align 4
 	store float* null, float** %sx_addr, align 4
 	br label %bb33
@@ -17,6 +17,6 @@ bb33:		; preds = %bb, %entry
 	br i1 false, label %bb, label %return
 
 return:		; preds = %bb33
-	%retval59 = load i32* null, align 4		; <i32> [#uses=1]
+	%retval59 = load i32, i32* null, align 4		; <i32> [#uses=1]
 	ret i32 %retval59
 }
diff --git a/test/Transforms/GVN/2008-07-02-Unreachable.ll b/test/Transforms/GVN/2008-07-02-Unreachable.ll
index ce83fa4e4be9..d9932644da3e 100644
--- a/test/Transforms/GVN/2008-07-02-Unreachable.ll
+++ b/test/Transforms/GVN/2008-07-02-Unreachable.ll
@@ -13,7 +13,7 @@ ifthen:		; preds = %entry
 	br label %ifend
 
 ifelse:		; preds = %entry
-	%tmp3 = load i8* @g_3		; <i8> [#uses=0]
+	%tmp3 = load i8, i8* @g_3		; <i8> [#uses=0]
         store i8 %tmp3, i8* %A
 	br label %afterfor
 
@@ -27,7 +27,7 @@ forinc:		; preds = %forbody
 	br label %forcond
 
 afterfor:		; preds = %forcond, %forcond.thread
-	%tmp10 = load i8* @g_3		; <i8> [#uses=0]
+	%tmp10 = load i8, i8* @g_3		; <i8> [#uses=0]
 	ret i8 %tmp10
 
 ifend:		; preds = %afterfor, %ifthen
diff --git a/test/Transforms/GVN/2008-12-09-SelfRemove.ll b/test/Transforms/GVN/2008-12-09-SelfRemove.ll
index c6833e373d06..d8ab1bae48e9 100644
--- a/test/Transforms/GVN/2008-12-09-SelfRemove.ll
+++ b/test/Transforms/GVN/2008-12-09-SelfRemove.ll
@@ -10,12 +10,12 @@ target triple = "i386-apple-darwin9.5"
 
 define void @d_print_mod_list(%struct.d_print_info* %dpi, %struct.d_print_mod* %mods, i32 %suffix) nounwind {
 entry:
-	%0 = getelementptr %struct.d_print_info* %dpi, i32 0, i32 1		; <i8**> [#uses=1]
+	%0 = getelementptr %struct.d_print_info, %struct.d_print_info* %dpi, i32 0, i32 1		; <i8**> [#uses=1]
 	br i1 false, label %return, label %bb
 
 bb:		; preds = %entry
-	%1 = load i8** %0, align 4		; <i8*> [#uses=0]
-	%2 = getelementptr %struct.d_print_info* %dpi, i32 0, i32 1		; <i8**> [#uses=0]
+	%1 = load i8*, i8** %0, align 4		; <i8*> [#uses=0]
+	%2 = getelementptr %struct.d_print_info, %struct.d_print_info* %dpi, i32 0, i32 1		; <i8**> [#uses=0]
 	br label %bb21
 
 bb21:		; preds = %bb21, %bb
diff --git a/test/Transforms/GVN/2008-12-12-RLE-Crash.ll b/test/Transforms/GVN/2008-12-12-RLE-Crash.ll
index da67ee776696..dabf7fa7aeb2 100644
--- a/test/Transforms/GVN/2008-12-12-RLE-Crash.ll
+++ b/test/Transforms/GVN/2008-12-12-RLE-Crash.ll
@@ -7,8 +7,8 @@ entry:
 	br label %bb84
 
 bb41:		; preds = %bb82
-	%tmp = load i8* %opt.0, align 1		; <i8> [#uses=0]
-	%tmp1 = getelementptr i8* %opt.0, i32 1		; <i8*> [#uses=2]
+	%tmp = load i8, i8* %opt.0, align 1		; <i8> [#uses=0]
+	%tmp1 = getelementptr i8, i8* %opt.0, i32 1		; <i8*> [#uses=2]
 	switch i32 0, label %bb81 [
 		i32 102, label %bb82
 		i32 110, label %bb79
@@ -26,10 +26,10 @@ bb81:		; preds = %bb41
 
 bb82:		; preds = %bb84, %bb79, %bb41
 	%opt.0 = phi i8* [ %tmp3, %bb84 ], [ %tmp1, %bb79 ], [ %tmp1, %bb41 ]		; <i8*> [#uses=3]
-	%tmp2 = load i8* %opt.0, align 1		; <i8> [#uses=0]
+	%tmp2 = load i8, i8* %opt.0, align 1		; <i8> [#uses=0]
 	br i1 false, label %bb84, label %bb41
 
 bb84:		; preds = %bb82, %entry
-	%tmp3 = getelementptr i8* null, i32 1		; <i8*> [#uses=1]
+	%tmp3 = getelementptr i8, i8* null, i32 1		; <i8*> [#uses=1]
 	br label %bb82
 }
diff --git a/test/Transforms/GVN/2008-12-14-rle-reanalyze.ll b/test/Transforms/GVN/2008-12-14-rle-reanalyze.ll
index 41f76c8167e5..207a2519f433 100644
--- a/test/Transforms/GVN/2008-12-14-rle-reanalyze.ll
+++ b/test/Transforms/GVN/2008-12-14-rle-reanalyze.ll
@@ -11,8 +11,8 @@ bb22:		; preds = %bb23, %bb22, %entry
 	br i1 false, label %bb23, label %bb22
 
 bb23:		; preds = %bb23, %bb22
-	%sortv.233 = phi i32* [ getelementptr ([256 x i32]* @sort_value, i32 0, i32 0), %bb22 ], [ %sortv.2, %bb23 ]		; <i32*> [#uses=1]
-	%0 = load i32* %sortv.233, align 4		; <i32> [#uses=0]
-	%sortv.2 = getelementptr [256 x i32]* @sort_value, i32 0, i32 0		; <i32*> [#uses=1]
+	%sortv.233 = phi i32* [ getelementptr ([256 x i32], [256 x i32]* @sort_value, i32 0, i32 0), %bb22 ], [ %sortv.2, %bb23 ]		; <i32*> [#uses=1]
+	%0 = load i32, i32* %sortv.233, align 4		; <i32> [#uses=0]
+	%sortv.2 = getelementptr [256 x i32], [256 x i32]* @sort_value, i32 0, i32 0		; <i32*> [#uses=1]
 	br i1 false, label %bb23, label %bb22
 }
diff --git a/test/Transforms/GVN/2008-12-15-CacheVisited.ll b/test/Transforms/GVN/2008-12-15-CacheVisited.ll
index 0a63f3f4626c..73adacd3cfaf 100644
--- a/test/Transforms/GVN/2008-12-15-CacheVisited.ll
+++ b/test/Transforms/GVN/2008-12-15-CacheVisited.ll
@@ -10,12 +10,12 @@ bb202:		; preds = %entry
 	unreachable
 
 bb203:		; preds = %entry
-	%tmp = getelementptr i32* %decl, i32 1		; <i32*> [#uses=1]
-	%tmp1 = load i32* %tmp, align 4		; <i32> [#uses=0]
+	%tmp = getelementptr i32, i32* %decl, i32 1		; <i32*> [#uses=1]
+	%tmp1 = load i32, i32* %tmp, align 4		; <i32> [#uses=0]
 	br i1 false, label %bb207, label %bb204
 
 bb204:		; preds = %bb203
-	%tmp2 = getelementptr i32* %decl, i32 1		; <i32*> [#uses=1]
+	%tmp2 = getelementptr i32, i32* %decl, i32 1		; <i32*> [#uses=1]
 	br label %bb208
 
 bb207:		; preds = %bb203
@@ -23,6 +23,6 @@ bb207:		; preds = %bb203
 
 bb208:		; preds = %bb207, %bb204
 	%iftmp.1374.0.in = phi i32* [ null, %bb207 ], [ %tmp2, %bb204 ]		; <i32*> [#uses=1]
-	%iftmp.1374.0 = load i32* %iftmp.1374.0.in		; <i32> [#uses=0]
+	%iftmp.1374.0 = load i32, i32* %iftmp.1374.0.in		; <i32> [#uses=0]
 	unreachable
 }
diff --git a/test/Transforms/GVN/2009-01-21-SortInvalidation.ll b/test/Transforms/GVN/2009-01-21-SortInvalidation.ll
index 36775936c8b7..6144697bb5b6 100644
--- a/test/Transforms/GVN/2009-01-21-SortInvalidation.ll
+++ b/test/Transforms/GVN/2009-01-21-SortInvalidation.ll
@@ -37,7 +37,7 @@ bb550:		; preds = %bb543
 	br i1 false, label %bb554, label %bb552
 
 bb552:		; preds = %bb550
-	%0 = load i8* %d.0, align 8		; <i8> [#uses=0]
+	%0 = load i8, i8* %d.0, align 8		; <i8> [#uses=0]
 	br label %bb554
 
 bb554:		; preds = %bb552, %bb550, %bb549
diff --git a/test/Transforms/GVN/2009-01-22-SortInvalidation.ll b/test/Transforms/GVN/2009-01-22-SortInvalidation.ll
index 95690a5a2571..89b058a235b4 100644
--- a/test/Transforms/GVN/2009-01-22-SortInvalidation.ll
+++ b/test/Transforms/GVN/2009-01-22-SortInvalidation.ll
@@ -79,20 +79,20 @@ bb54:		; preds = %entry
 	br label %bb69.loopexit
 
 bb59:		; preds = %bb63.preheader
-	%0 = load %struct..4sPragmaType** %3, align 4		; <%struct..4sPragmaType*> [#uses=0]
+	%0 = load %struct..4sPragmaType*, %struct..4sPragmaType** %3, align 4		; <%struct..4sPragmaType*> [#uses=0]
 	br label %bb65
 
 bb65:		; preds = %bb63.preheader, %bb59
-	%1 = load %struct..4sPragmaType** %4, align 4		; <%struct..4sPragmaType*> [#uses=0]
+	%1 = load %struct..4sPragmaType*, %struct..4sPragmaType** %4, align 4		; <%struct..4sPragmaType*> [#uses=0]
 	br i1 false, label %bb67, label %bb63.preheader
 
 bb67:		; preds = %bb65
-	%2 = getelementptr %struct.IdList* %pColumn, i32 0, i32 0		; <%struct..4sPragmaType**> [#uses=0]
+	%2 = getelementptr %struct.IdList, %struct.IdList* %pColumn, i32 0, i32 0		; <%struct..4sPragmaType**> [#uses=0]
 	unreachable
 
 bb69.loopexit:		; preds = %bb54, %entry
-	%3 = getelementptr %struct.IdList* %pColumn, i32 0, i32 0		; <%struct..4sPragmaType**> [#uses=1]
-	%4 = getelementptr %struct.IdList* %pColumn, i32 0, i32 0		; <%struct..4sPragmaType**> [#uses=1]
+	%3 = getelementptr %struct.IdList, %struct.IdList* %pColumn, i32 0, i32 0		; <%struct..4sPragmaType**> [#uses=1]
+	%4 = getelementptr %struct.IdList, %struct.IdList* %pColumn, i32 0, i32 0		; <%struct..4sPragmaType**> [#uses=1]
 	br label %bb63.preheader
 
 bb63.preheader:		; preds = %bb69.loopexit, %bb65
diff --git a/test/Transforms/GVN/2009-02-17-LoadPRECrash.ll b/test/Transforms/GVN/2009-02-17-LoadPRECrash.ll
index c2d57a105fc9..808f28c674c5 100644
--- a/test/Transforms/GVN/2009-02-17-LoadPRECrash.ll
+++ b/test/Transforms/GVN/2009-02-17-LoadPRECrash.ll
@@ -24,11 +24,11 @@ entry:
 	%addr = alloca %struct.rtx_def*		; <%struct.rtx_def**> [#uses=5]
 	%iftmp.1532 = alloca %struct.rtx_def*		; <%struct.rtx_def**> [#uses=3]
 	store %struct.rtx_def* %orig, %struct.rtx_def** null
-	%0 = load %struct.rtx_def** null, align 4		; <%struct.rtx_def*> [#uses=0]
+	%0 = load %struct.rtx_def*, %struct.rtx_def** null, align 4		; <%struct.rtx_def*> [#uses=0]
 	br i1 false, label %bb96, label %bb59
 
 bb59:		; preds = %entry
-	%1 = load %struct.rtx_def** %addr, align 4		; <%struct.rtx_def*> [#uses=1]
+	%1 = load %struct.rtx_def*, %struct.rtx_def** %addr, align 4		; <%struct.rtx_def*> [#uses=1]
 	%2 = call i32 @local_symbolic_operand(%struct.rtx_def* %1, i32 0) nounwind		; <i32> [#uses=0]
 	br i1 false, label %bb96, label %bb63
 
@@ -54,7 +54,7 @@ bb76:		; preds = %bb75, %bb74
 	br i1 false, label %bb77, label %bb84
 
 bb77:		; preds = %bb76
-	%3 = getelementptr [1 x %struct.cgraph_rtl_info]* null, i32 0, i32 0		; <%struct.cgraph_rtl_info*> [#uses=0]
+	%3 = getelementptr [1 x %struct.cgraph_rtl_info], [1 x %struct.cgraph_rtl_info]* null, i32 0, i32 0		; <%struct.cgraph_rtl_info*> [#uses=0]
 	unreachable
 
 bb84:		; preds = %bb76
@@ -89,22 +89,22 @@ bb94:		; preds = %bb93, %bb92
 	unreachable
 
 bb96:		; preds = %bb59, %entry
-	%5 = load %struct.rtx_def** %addr, align 4		; <%struct.rtx_def*> [#uses=1]
-	%6 = getelementptr %struct.rtx_def* %5, i32 0, i32 0		; <i16*> [#uses=1]
-	%7 = load i16* %6, align 2		; <i16> [#uses=0]
+	%5 = load %struct.rtx_def*, %struct.rtx_def** %addr, align 4		; <%struct.rtx_def*> [#uses=1]
+	%6 = getelementptr %struct.rtx_def, %struct.rtx_def* %5, i32 0, i32 0		; <i16*> [#uses=1]
+	%7 = load i16, i16* %6, align 2		; <i16> [#uses=0]
 	br i1 false, label %bb147, label %bb97
 
 bb97:		; preds = %bb96
-	%8 = load %struct.rtx_def** %addr, align 4		; <%struct.rtx_def*> [#uses=0]
+	%8 = load %struct.rtx_def*, %struct.rtx_def** %addr, align 4		; <%struct.rtx_def*> [#uses=0]
 	br i1 false, label %bb147, label %bb99
 
 bb99:		; preds = %bb97
 	unreachable
 
 bb147:		; preds = %bb97, %bb96
-	%9 = load %struct.rtx_def** %addr, align 4		; <%struct.rtx_def*> [#uses=1]
-	%10 = getelementptr %struct.rtx_def* %9, i32 0, i32 0		; <i16*> [#uses=1]
-	%11 = load i16* %10, align 2		; <i16> [#uses=0]
+	%9 = load %struct.rtx_def*, %struct.rtx_def** %addr, align 4		; <%struct.rtx_def*> [#uses=1]
+	%10 = getelementptr %struct.rtx_def, %struct.rtx_def* %9, i32 0, i32 0		; <i16*> [#uses=1]
+	%11 = load i16, i16* %10, align 2		; <i16> [#uses=0]
 	br i1 false, label %bb164, label %bb148
 
 bb148:		; preds = %bb147
@@ -120,7 +120,7 @@ bb152:		; preds = %bb149
 	br label %bb164
 
 bb164:		; preds = %bb152, %bb148, %bb147
-	%12 = getelementptr [1 x %struct.cgraph_rtl_info]* null, i32 0, i32 1		; <%struct.cgraph_rtl_info*> [#uses=0]
+	%12 = getelementptr [1 x %struct.cgraph_rtl_info], [1 x %struct.cgraph_rtl_info]* null, i32 0, i32 1		; <%struct.cgraph_rtl_info*> [#uses=0]
 	br i1 false, label %bb165, label %bb166
 
 bb165:		; preds = %bb164
@@ -163,12 +163,12 @@ bb180:		; preds = %bb179, %bb178
 	br label %bb181
 
 bb181:		; preds = %bb180, %bb170
-	%13 = call %struct.rtvec_def* (i32, ...)* @gen_rtvec(i32 1, %struct.rtx_def* null) nounwind		; <%struct.rtvec_def*> [#uses=0]
+	%13 = call %struct.rtvec_def* (i32, ...) @gen_rtvec(i32 1, %struct.rtx_def* null) nounwind		; <%struct.rtvec_def*> [#uses=0]
 	unreachable
 
 bb211:		; preds = %bb168, %bb167
-	%14 = load %struct.rtx_def** %addr, align 4		; <%struct.rtx_def*> [#uses=0]
-	%15 = getelementptr [1 x %struct.cgraph_rtl_info]* null, i32 0, i32 0		; <%struct.cgraph_rtl_info*> [#uses=0]
+	%14 = load %struct.rtx_def*, %struct.rtx_def** %addr, align 4		; <%struct.rtx_def*> [#uses=0]
+	%15 = getelementptr [1 x %struct.cgraph_rtl_info], [1 x %struct.cgraph_rtl_info]* null, i32 0, i32 0		; <%struct.cgraph_rtl_info*> [#uses=0]
 	store %struct.rtx_def* null, %struct.rtx_def** null, align 4
 	br i1 false, label %bb212, label %bb213
 
@@ -182,12 +182,12 @@ bb213:		; preds = %bb211
 
 bb214:		; preds = %bb213, %bb212
 	%16 = bitcast %struct.block_symbol* null to [1 x %struct.cgraph_rtl_info]*		; <[1 x %struct.cgraph_rtl_info]*> [#uses=1]
-	%17 = getelementptr [1 x %struct.cgraph_rtl_info]* %16, i32 0, i32 1		; <%struct.cgraph_rtl_info*> [#uses=0]
-	%18 = load %struct.rtx_def** %iftmp.1532, align 4		; <%struct.rtx_def*> [#uses=0]
-	%19 = getelementptr %struct.rtx_def* null, i32 0, i32 3		; <%struct.u*> [#uses=1]
-	%20 = getelementptr %struct.u* %19, i32 0, i32 0		; <%struct.block_symbol*> [#uses=1]
+	%17 = getelementptr [1 x %struct.cgraph_rtl_info], [1 x %struct.cgraph_rtl_info]* %16, i32 0, i32 1		; <%struct.cgraph_rtl_info*> [#uses=0]
+	%18 = load %struct.rtx_def*, %struct.rtx_def** %iftmp.1532, align 4		; <%struct.rtx_def*> [#uses=0]
+	%19 = getelementptr %struct.rtx_def, %struct.rtx_def* null, i32 0, i32 3		; <%struct.u*> [#uses=1]
+	%20 = getelementptr %struct.u, %struct.u* %19, i32 0, i32 0		; <%struct.block_symbol*> [#uses=1]
 	%21 = bitcast %struct.block_symbol* %20 to [1 x i64]*		; <[1 x i64]*> [#uses=1]
-	%22 = getelementptr [1 x i64]* %21, i32 0, i32 0		; <i64*> [#uses=0]
+	%22 = getelementptr [1 x i64], [1 x i64]* %21, i32 0, i32 0		; <i64*> [#uses=0]
 	%23 = call %struct.rtx_def* @plus_constant(%struct.rtx_def* null, i64 0) nounwind		; <%struct.rtx_def*> [#uses=0]
 	unreachable
 }
diff --git a/test/Transforms/GVN/2009-06-17-InvalidPRE.ll b/test/Transforms/GVN/2009-06-17-InvalidPRE.ll
index 6ac6072a9273..bf0a234da4ac 100644
--- a/test/Transforms/GVN/2009-06-17-InvalidPRE.ll
+++ b/test/Transforms/GVN/2009-06-17-InvalidPRE.ll
@@ -18,20 +18,20 @@ bb4.preheader:    ; preds = %entry
 
 bb2:    ; preds = %bb1
   %2 = sub i32 %len.0, %13   ; <i32> [#uses=1]
-  %3 = getelementptr %struct.mbuf* %m.0.ph, i32 0, i32 2    ; <i32*> [#uses=1]
+  %3 = getelementptr %struct.mbuf, %struct.mbuf* %m.0.ph, i32 0, i32 2    ; <i32*> [#uses=1]
   store i32 0, i32* %3, align 4
-  %4 = getelementptr %struct.mbuf* %m.0.ph, i32 0, i32 0    ; <%struct.mbuf**> [#uses=1]
-  %5 = load %struct.mbuf** %4, align 4    ; <%struct.mbuf*> [#uses=1]
+  %4 = getelementptr %struct.mbuf, %struct.mbuf* %m.0.ph, i32 0, i32 0    ; <%struct.mbuf**> [#uses=1]
+  %5 = load %struct.mbuf*, %struct.mbuf** %4, align 4    ; <%struct.mbuf*> [#uses=1]
   br label %bb4.outer
 
 bb4.outer:    ; preds = %bb4.preheader, %bb2
   %m.0.ph = phi %struct.mbuf* [ %5, %bb2 ], [ %mp, %bb4.preheader ]   ; <%struct.mbuf*> [#uses=7]
   %len.0.ph = phi i32 [ %2, %bb2 ], [ %req_len, %bb4.preheader ]    ; <i32> [#uses=1]
   %6 = icmp ne %struct.mbuf* %m.0.ph, null    ; <i1> [#uses=1]
-  %7 = getelementptr %struct.mbuf* %m.0.ph, i32 0, i32 2    ; <i32*> [#uses=1]
-  %8 = getelementptr %struct.mbuf* %m.0.ph, i32 0, i32 2   ; <i32*> [#uses=1]
-  %9 = getelementptr %struct.mbuf* %m.0.ph, i32 0, i32 3   ; <i8**> [#uses=1]
-  %10 = getelementptr %struct.mbuf* %m.0.ph, i32 0, i32 3   ; <i8**> [#uses=1]
+  %7 = getelementptr %struct.mbuf, %struct.mbuf* %m.0.ph, i32 0, i32 2    ; <i32*> [#uses=1]
+  %8 = getelementptr %struct.mbuf, %struct.mbuf* %m.0.ph, i32 0, i32 2   ; <i32*> [#uses=1]
+  %9 = getelementptr %struct.mbuf, %struct.mbuf* %m.0.ph, i32 0, i32 3   ; <i8**> [#uses=1]
+  %10 = getelementptr %struct.mbuf, %struct.mbuf* %m.0.ph, i32 0, i32 3   ; <i8**> [#uses=1]
   br label %bb4
 
 bb4:    ; preds = %bb4.outer, %bb3
@@ -41,21 +41,21 @@ bb4:    ; preds = %bb4.outer, %bb3
   br i1 %12, label %bb1, label %bb7
 
 bb1:    ; preds = %bb4
-  %13 = load i32* %7, align 4    ; <i32> [#uses=3]
+  %13 = load i32, i32* %7, align 4    ; <i32> [#uses=3]
   %14 = icmp sgt i32 %13, %len.0    ; <i1> [#uses=1]
   br i1 %14, label %bb3, label %bb2
 
 bb3:    ; preds = %bb1
   %15 = sub i32 %13, %len.0    ; <i32> [#uses=1]
   store i32 %15, i32* %8, align 4
-  %16 = load i8** %9, align 4    ; <i8*> [#uses=1]
-  %17 = getelementptr i8* %16, i32 %len.0   ; <i8*> [#uses=1]
+  %16 = load i8*, i8** %9, align 4    ; <i8*> [#uses=1]
+  %17 = getelementptr i8, i8* %16, i32 %len.0   ; <i8*> [#uses=1]
   store i8* %17, i8** %10, align 4
   br label %bb4
 
 bb7:    ; preds = %bb4
-  %18 = getelementptr %struct.mbuf* %mp, i32 0, i32 5   ; <i16*> [#uses=1]
-  %19 = load i16* %18, align 2    ; <i16> [#uses=1]
+  %18 = getelementptr %struct.mbuf, %struct.mbuf* %mp, i32 0, i32 5   ; <i16*> [#uses=1]
+  %19 = load i16, i16* %18, align 2    ; <i16> [#uses=1]
   %20 = zext i16 %19 to i32   ; <i32> [#uses=1]
   %21 = and i32 %20, 2    ; <i32> [#uses=1]
   %22 = icmp eq i32 %21, 0    ; <i1> [#uses=1]
@@ -63,7 +63,7 @@ bb7:    ; preds = %bb4
 
 bb8:    ; preds = %bb7
   %23 = sub i32 %req_len, %len.0    ; <i32> [#uses=1]
-  %24 = getelementptr %struct.mbuf* %mp, i32 0, i32 6   ; <i32*> [#uses=1]
+  %24 = getelementptr %struct.mbuf, %struct.mbuf* %mp, i32 0, i32 6   ; <i32*> [#uses=1]
   store i32 %23, i32* %24, align 4
   ret void
 
diff --git a/test/Transforms/GVN/2009-07-13-MemDepSortFail.ll b/test/Transforms/GVN/2009-07-13-MemDepSortFail.ll
index f079108b9bda..0ed52370f80d 100644
--- a/test/Transforms/GVN/2009-07-13-MemDepSortFail.ll
+++ b/test/Transforms/GVN/2009-07-13-MemDepSortFail.ll
@@ -22,11 +22,11 @@ bb2:		; preds = %bb
 	br label %bb62
 
 bb9:		; preds = %bb
-	%0 = load i8* %sp.1, align 1		; <i8> [#uses=0]
+	%0 = load i8, i8* %sp.1, align 1		; <i8> [#uses=0]
 	br label %bb62
 
 bb51:		; preds = %bb
-	%1 = load i8* %sp.1, align 1		; <i8> [#uses=0]
+	%1 = load i8, i8* %sp.1, align 1		; <i8> [#uses=0]
 	ret i8* null
 
 bb62:		; preds = %bb9, %bb2, %bb
diff --git a/test/Transforms/GVN/2009-11-12-MemDepMallocBitCast.ll b/test/Transforms/GVN/2009-11-12-MemDepMallocBitCast.ll
index b433297bba6f..a12fbddbda5a 100644
--- a/test/Transforms/GVN/2009-11-12-MemDepMallocBitCast.ll
+++ b/test/Transforms/GVN/2009-11-12-MemDepMallocBitCast.ll
@@ -3,12 +3,12 @@
 ; RUN: opt < %s -gvn -S | FileCheck %s
 
 define i64 @test() {
-  %1 = tail call i8* @malloc(i64 mul (i64 4, i64 ptrtoint (i64* getelementptr (i64* null, i64 1) to i64))) ; <i8*> [#uses=2]
+  %1 = tail call i8* @malloc(i64 mul (i64 4, i64 ptrtoint (i64* getelementptr (i64, i64* null, i64 1) to i64))) ; <i8*> [#uses=2]
   store i8 42, i8* %1
   %X = bitcast i8* %1 to i64*                     ; <i64*> [#uses=1]
-  %Y = load i64* %X                               ; <i64> [#uses=1]
+  %Y = load i64, i64* %X                               ; <i64> [#uses=1]
   ret i64 %Y
-; CHECK: %Y = load i64* %X
+; CHECK: %Y = load i64, i64* %X
 ; CHECK: ret i64 %Y
 }
 
diff --git a/test/Transforms/GVN/2010-03-31-RedundantPHIs.ll b/test/Transforms/GVN/2010-03-31-RedundantPHIs.ll
index d6e1c6b76d0b..9d9ad5424075 100644
--- a/test/Transforms/GVN/2010-03-31-RedundantPHIs.ll
+++ b/test/Transforms/GVN/2010-03-31-RedundantPHIs.ll
@@ -24,8 +24,8 @@ bb8:                                              ; preds = %bb12
   br i1 undef, label %bb9, label %bb10
 
 bb9:                                              ; preds = %bb8
-  %0 = load i8** undef, align 4                   ; <i8*> [#uses=0]
-  %1 = load i8** undef, align 4                   ; <i8*> [#uses=0]
+  %0 = load i8*, i8** undef, align 4                   ; <i8*> [#uses=0]
+  %1 = load i8*, i8** undef, align 4                   ; <i8*> [#uses=0]
   br label %bb11
 
 bb10:                                             ; preds = %bb8
diff --git a/test/Transforms/GVN/2010-05-08-OneBit.ll b/test/Transforms/GVN/2010-05-08-OneBit.ll
index 480ce8ba0ae1..0e3fa4b8a490 100644
--- a/test/Transforms/GVN/2010-05-08-OneBit.ll
+++ b/test/Transforms/GVN/2010-05-08-OneBit.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @main(i32 %argc, i8** nocapture %argv) {
 entry:
-  %0 = getelementptr inbounds i8* undef, i64 5    ; <i8*> [#uses=1]
+  %0 = getelementptr inbounds i8, i8* undef, i64 5    ; <i8*> [#uses=1]
   %1 = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
   store i32 undef, i32* %1, align 1
   br i1 undef, label %k121.i.i, label %l117.i.i
@@ -29,9 +29,9 @@ l129.i.i:                                         ; preds = %k121.i.i
   unreachable
 
 k133.i.i:                                         ; preds = %k121.i.i
-  %2 = getelementptr i8* undef, i64 5             ; <i8*> [#uses=1]
+  %2 = getelementptr i8, i8* undef, i64 5             ; <i8*> [#uses=1]
   %3 = bitcast i8* %2 to i1*                      ; <i1*> [#uses=1]
-  %4 = load i1* %3                                ; <i1> [#uses=1]
+  %4 = load i1, i1* %3                                ; <i1> [#uses=1]
   br i1 %4, label %k151.i.i, label %l147.i.i
 
 l147.i.i:                                         ; preds = %k133.i.i
diff --git a/test/Transforms/GVN/2011-04-27-phioperands.ll b/test/Transforms/GVN/2011-04-27-phioperands.ll
index 42c46500c483..e964120a8b05 100644
--- a/test/Transforms/GVN/2011-04-27-phioperands.ll
+++ b/test/Transforms/GVN/2011-04-27-phioperands.ll
@@ -27,7 +27,7 @@ doemit.exit76.i:
   br label %"<bb 53>.i"
 
 "<L98>.i":
-  store i8* getelementptr inbounds ([10 x i8]* @nuls, i64 0, i64 0), i8** undef, align 8
+  store i8* getelementptr inbounds ([10 x i8], [10 x i8]* @nuls, i64 0, i64 0), i8** undef, align 8
   br label %"<bb 53>.i"
 
 "<L99>.i":
@@ -50,7 +50,7 @@ doemit.exit76.i:
 
 "<bb 53>.i":
   %wascaret_2.i = phi i32 [ 0, %"<L39>.i" ], [ 0, %"<L29>.i" ], [ 0, %"<L28>.i" ], [ 0, %"<bb 35>.i" ], [ 0, %"<L99>.i" ], [ 0, %"<L98>.i" ], [ 0, %doemit.exit76.i ], [ 1, %doemit.exit51.i ], [ 0, %"<L24>.i" ]
-  %D.5496_84.i = load i8** undef, align 8
+  %D.5496_84.i = load i8*, i8** undef, align 8
   br i1 undef, label %"<bb 54>.i", label %"<bb 5>"
 
 "<bb 54>.i":
diff --git a/test/Transforms/GVN/2011-06-01-NonLocalMemdepMiscompile.ll b/test/Transforms/GVN/2011-06-01-NonLocalMemdepMiscompile.ll
index 298f27401aaf..0769575759ba 100644
--- a/test/Transforms/GVN/2011-06-01-NonLocalMemdepMiscompile.ll
+++ b/test/Transforms/GVN/2011-06-01-NonLocalMemdepMiscompile.ll
@@ -19,10 +19,10 @@ bb1:
   br i1 undef, label %bb3, label %bb15
 
 ; CHECK: bb1:
-; CHECK: [[TMP:%.*]] = phi i8* [ getelementptr (i8* null, i64 undef), %bb10 ], [ null, %bb ]
+; CHECK: [[TMP:%.*]] = phi i8* [ getelementptr (i8, i8* null, i64 undef), %bb10 ], [ null, %bb ]
 
 ; CHECK: bb1.bb15_crit_edge:
-; CHECK: %tmp17.pre = load i8* [[TMP]], align 1
+; CHECK: %tmp17.pre = load i8, i8* [[TMP]], align 1
 
 bb3:
   call void @isalnum()
@@ -32,22 +32,22 @@ bb5:
   br i1 undef, label %bb10, label %bb6
 
 bb6:
-  %tmp7 = load i8** %tmp, align 8
-  %tmp8 = load i8* %tmp7, align 1
+  %tmp7 = load i8*, i8** %tmp, align 8
+  %tmp8 = load i8, i8* %tmp7, align 1
   %tmp9 = zext i8 %tmp8 to i64
   br i1 undef, label %bb15, label %bb10
 
 bb10:
-  %tmp11 = load i8** %tmp, align 8
-  %tmp12 = load i8* %tmp11, align 1
+  %tmp11 = load i8*, i8** %tmp, align 8
+  %tmp12 = load i8, i8* %tmp11, align 1
   %tmp13 = zext i8 %tmp12 to i64
-  %tmp14 = getelementptr inbounds i8* null, i64 undef
+  %tmp14 = getelementptr inbounds i8, i8* null, i64 undef
   store i8* %tmp14, i8** %tmp, align 8
   br label %bb1
 
 bb15:
-  %tmp16 = load i8** %tmp, align 8
-  %tmp17 = load i8* %tmp16, align 1
+  %tmp16 = load i8*, i8** %tmp, align 8
+  %tmp17 = load i8, i8* %tmp16, align 1
   %tmp18 = icmp eq i8 %tmp17, 0
   br label %bb19
 
diff --git a/test/Transforms/GVN/MemdepMiscompile.ll b/test/Transforms/GVN/MemdepMiscompile.ll
index d42016961575..0652304b3d7d 100644
--- a/test/Transforms/GVN/MemdepMiscompile.ll
+++ b/test/Transforms/GVN/MemdepMiscompile.ll
@@ -13,14 +13,14 @@ entry:
 ; CHECK: call void @RunInMode
 ; CHECK: br i1 %tobool, label %while.cond.backedge, label %if.then
 ; CHECK: while.cond.backedge:
-; CHECK: load i32* %shouldExit
+; CHECK: load i32, i32* %shouldExit
 ; CHECK: br i1 %cmp, label %while.body
   %shouldExit = alloca i32, align 4
   %tasksIdle = alloca i32, align 4
   store i32 0, i32* %shouldExit, align 4
   store i32 0, i32* %tasksIdle, align 4
   call void @CTestInitialize(i32* %tasksIdle) nounwind
-  %0 = load i32* %shouldExit, align 4
+  %0 = load i32, i32* %shouldExit, align 4
   %cmp1 = icmp eq i32 %0, 0
   br i1 %cmp1, label %while.body.lr.ph, label %while.end
 
@@ -29,7 +29,7 @@ while.body.lr.ph:
 
 while.body:
   call void @RunInMode(i32 100) nounwind
-  %1 = load i32* %tasksIdle, align 4
+  %1 = load i32, i32* %tasksIdle, align 4
   %tobool = icmp eq i32 %1, 0
   br i1 %tobool, label %while.cond.backedge, label %if.then
 
@@ -39,7 +39,7 @@ if.then:
   br label %while.cond.backedge
 
 while.cond.backedge:
-  %2 = load i32* %shouldExit, align 4
+  %2 = load i32, i32* %shouldExit, align 4
   %cmp = icmp eq i32 %2, 0
   br i1 %cmp, label %while.body, label %while.cond.while.end_crit_edge
 
diff --git a/test/Transforms/GVN/atomic.ll b/test/Transforms/GVN/atomic.ll
index 8c13d209c53a..11b54f39756b 100644
--- a/test/Transforms/GVN/atomic.ll
+++ b/test/Transforms/GVN/atomic.ll
@@ -11,21 +11,9 @@ define i32 @test1() nounwind uwtable ssp {
 ; CHECK-LABEL: test1
 ; CHECK: add i32 %x, %x
 entry:
-  %x = load i32* @y
+  %x = load i32, i32* @y
   store atomic i32 %x, i32* @x unordered, align 4
-  %y = load i32* @y
-  %z = add i32 %x, %y
-  ret i32 %z
-}
-
-; GVN across seq_cst store (allowed)
-define i32 @test2() nounwind uwtable ssp {
-; CHECK-LABEL: test2
-; CHECK: add i32 %x, %x
-entry:
-  %x = load i32* @y
-  store atomic i32 %x, i32* @x seq_cst, align 4
-  %y = load i32* @y
+  %y = load i32, i32* @y
   %z = add i32 %x, %y
   ret i32 %z
 }
@@ -35,35 +23,21 @@ define i32 @test3() nounwind uwtable ssp {
 ; CHECK-LABEL: test3
 ; CHECK: add i32 %x, %x
 entry:
-  %x = load i32* @y
-  %y = load atomic i32* @x unordered, align 4
-  %z = load i32* @y
+  %x = load i32, i32* @y
+  %y = load atomic i32, i32* @x unordered, align 4
+  %z = load i32, i32* @y
   %a = add i32 %x, %z
   %b = add i32 %y, %a
   ret i32 %b
 }
 
-; GVN across acquire load (allowed as the original load was not atomic)
-define i32 @test4() nounwind uwtable ssp {
-; CHECK-LABEL: test4
-; CHECK: load atomic i32* @x
-; CHECK-NOT: load i32* @y
-entry:
-  %x = load i32* @y
-  %y = load atomic i32* @x seq_cst, align 4
-  %x2 = load i32* @y
-  %x3 = add i32 %x, %x2
-  %y2 = add i32 %y, %x3
-  ret i32 %y2
-}
-
 ; GVN load to unordered load (allowed)
 define i32 @test5() nounwind uwtable ssp {
 ; CHECK-LABEL: test5
 ; CHECK: add i32 %x, %x
 entry:
-  %x = load atomic i32* @x unordered, align 4
-  %y = load i32* @x
+  %x = load atomic i32, i32* @x unordered, align 4
+  %y = load i32, i32* @x
   %z = add i32 %x, %y
   ret i32 %z
 }
@@ -71,10 +45,10 @@ entry:
 ; GVN unordered load to load (unordered load must not be removed)
 define i32 @test6() nounwind uwtable ssp {
 ; CHECK-LABEL: test6
-; CHECK: load atomic i32* @x unordered
+; CHECK: load atomic i32, i32* @x unordered
 entry:
-  %x = load i32* @x
-  %x2 = load atomic i32* @x unordered, align 4
+  %x = load i32, i32* @x
+  %x2 = load atomic i32, i32* @x unordered, align 4
   %x3 = add i32 %x, %x2
   ret i32 %x3
 }
@@ -84,23 +58,10 @@ define i32 @test7() nounwind uwtable ssp {
 ; CHECK-LABEL: test7
 ; CHECK: add i32 %x, %y
 entry:
-  %x = load i32* @y
+  %x = load i32, i32* @y
   store atomic i32 %x, i32* @x release, align 4
-  %w = load atomic i32* @x acquire, align 4
-  %y = load i32* @y
-  %z = add i32 %x, %y
-  ret i32 %z
-}
-
-; GVN across acquire-release pair (allowed)
-define i32 @test8() nounwind uwtable ssp {
-; CHECK-LABEL: test8
-; CHECK: add i32 %x, %x
-entry:
-  %x = load i32* @y
-  %w = load atomic i32* @x acquire, align 4
-  store atomic i32 %x, i32* @x release, align 4
-  %y = load i32* @y
+  %w = load atomic i32, i32* @x acquire, align 4
+  %y = load i32, i32* @y
   %z = add i32 %x, %y
   ret i32 %z
 }
@@ -110,9 +71,9 @@ define i32 @test9() nounwind uwtable ssp {
 ; CHECK-LABEL: test9
 ; CHECK: add i32 %x, %x
 entry:
-  %x = load i32* @y
+  %x = load i32, i32* @y
   store atomic i32 %x, i32* @x monotonic, align 4
-  %y = load i32* @y
+  %y = load i32, i32* @y
   %z = add i32 %x, %y
   ret i32 %z
 }
@@ -122,10 +83,27 @@ define i32 @test10() nounwind uwtable ssp {
 ; CHECK-LABEL: test10
 ; CHECK: add i32 %x, %y
 entry:
-  %x = load atomic i32* @y unordered, align 4
-  %clobber = load atomic i32* @x monotonic, align 4
-  %y = load atomic i32* @y monotonic, align 4
+  %x = load atomic i32, i32* @y unordered, align 4
+  %clobber = load atomic i32, i32* @x monotonic, align 4
+  %y = load atomic i32, i32* @y monotonic, align 4
   %z = add i32 %x, %y
   ret i32 %z
 }
 
+define i32 @PR22708(i1 %flag) {
+; CHECK-LABEL: PR22708
+entry:
+  br i1 %flag, label %if.then, label %if.end
+
+if.then:
+  store i32 43, i32* @y, align 4
+; CHECK: store i32 43, i32* @y, align 4
+  br label %if.end
+
+if.end:
+  load atomic i32, i32* @x acquire, align 4
+  %load = load i32, i32* @y, align 4
+; CHECK: load atomic i32, i32* @x acquire, align 4
+; CHECK: load i32, i32* @y, align 4
+  ret i32 %load
+}
diff --git a/test/Transforms/GVN/basic-undef-test.ll b/test/Transforms/GVN/basic-undef-test.ll
new file mode 100644
index 000000000000..4f9409567806
--- /dev/null
+++ b/test/Transforms/GVN/basic-undef-test.ll
@@ -0,0 +1,15 @@
+; RUN: opt -basicaa -gvn -S < %s | FileCheck %s
+; ModuleID = 'test3.ll'
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+
+define i32 @main(i32 *%foo)  {
+entry:
+; CHECK: load i32, i32* %foo, align 4
+  %0 = load i32, i32* %foo, align 4
+  store i32 5, i32* undef, align 4
+; CHECK-NOT: load i32, i32* %foo, align 4
+  %1 = load i32, i32* %foo, align 4
+; CHECK: add i32 %0, %0
+  %2 = add i32 %0, %1
+  ret i32 %2
+}
diff --git a/test/Transforms/GVN/calloc-load-removal.ll b/test/Transforms/GVN/calloc-load-removal.ll
index 2dde5b7b4146..a51f71fd77a1 100644
--- a/test/Transforms/GVN/calloc-load-removal.ll
+++ b/test/Transforms/GVN/calloc-load-removal.ll
@@ -9,11 +9,11 @@ define i32 @test1() {
   %1 = tail call noalias i8* @calloc(i64 1, i64 4)
   %2 = bitcast i8* %1 to i32*
   ; This load is trivially constant zero
-  %3 = load i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
   ret i32 %3
 
 ; CHECK-LABEL: @test1(
-; CHECK-NOT: %3 = load i32* %2, align 4
+; CHECK-NOT: %3 = load i32, i32* %2, align 4
 ; CHECK: ret i32 0
 
 ; CHECK_NO_LIBCALLS-LABEL: @test1(
diff --git a/test/Transforms/GVN/calls-readonly.ll b/test/Transforms/GVN/calls-readonly.ll
index a4777401b190..ba8ad661eabf 100644
--- a/test/Transforms/GVN/calls-readonly.ll
+++ b/test/Transforms/GVN/calls-readonly.ll
@@ -20,7 +20,7 @@ bb1:                                              ; preds = %bb, %entry
   %4 = tail call i32 @strlen(i8* %P)              ; <i32> [#uses=1]
   %5 = add i32 %x_addr.0, %0                      ; <i32> [#uses=1]
   %.sum = sub i32 %5, %4                          ; <i32> [#uses=1]
-  %6 = getelementptr i8* %3, i32 %.sum            ; <i8*> [#uses=1]
+  %6 = getelementptr i8, i8* %3, i32 %.sum            ; <i8*> [#uses=1]
   ret i8* %6
 }
 
diff --git a/test/Transforms/GVN/cond_br.ll b/test/Transforms/GVN/cond_br.ll
index 918e7d41f12c..aeb1a6e6bf70 100644
--- a/test/Transforms/GVN/cond_br.ll
+++ b/test/Transforms/GVN/cond_br.ll
@@ -5,11 +5,11 @@
 ; Function Attrs: nounwind ssp uwtable
 define void @foo(i32 %x) {
 ; CHECK: @foo(i32 %x)
-; CHECK: %.pre = load i32* @y
+; CHECK: %.pre = load i32, i32* @y
 ; CHECK: call void @bar(i32 %.pre)
 
   %t = sub i32 %x, %x
-  %.pre = load i32* @y, align 4
+  %.pre = load i32, i32* @y, align 4
   %cmp = icmp sgt i32 %t, 2
   br i1 %cmp, label %if.then, label %entry.if.end_crit_edge
 
@@ -29,11 +29,11 @@ if.end:                                           ; preds = %entry.if.end_crit_e
 
 define void @foo2(i32 %x) {
 ; CHECK: @foo2(i32 %x)
-; CHECK: %.pre = load i32* @y
+; CHECK: %.pre = load i32, i32* @y
 ; CHECK: tail call void @bar(i32 %.pre)
 entry:
   %t = sub i32 %x, %x
-  %.pre = load i32* @y, align 4
+  %.pre = load i32, i32* @y, align 4
   %cmp = icmp sgt i32 %t, 2
   br i1 %cmp, label %if.then, label %if.else
 
diff --git a/test/Transforms/GVN/cond_br2.ll b/test/Transforms/GVN/cond_br2.ll
index a7ca2190563b..02154a783912 100644
--- a/test/Transforms/GVN/cond_br2.ll
+++ b/test/Transforms/GVN/cond_br2.ll
@@ -19,19 +19,19 @@ entry:
   %sv = alloca %"class.llvm::SmallVector", align 16
   %0 = bitcast %"class.llvm::SmallVector"* %sv to i8*
   call void @llvm.lifetime.start(i64 64, i8* %0) #1
-  %BeginX.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
-  %FirstEl.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0, i32 3
+  %BeginX.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SmallVector", %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
+  %FirstEl.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SmallVector", %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0, i32 3
   %1 = bitcast %"union.llvm::SmallVectorBase::U"* %FirstEl.i.i.i.i.i.i to i8*
   store i8* %1, i8** %BeginX.i.i.i.i.i.i, align 16, !tbaa !4
-  %EndX.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0, i32 1
+  %EndX.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SmallVector", %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0, i32 1
   store i8* %1, i8** %EndX.i.i.i.i.i.i, align 8, !tbaa !4
-  %CapacityX.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0, i32 2
-  %add.ptr.i.i.i.i2.i.i = getelementptr inbounds %"union.llvm::SmallVectorBase::U"* %FirstEl.i.i.i.i.i.i, i64 2
+  %CapacityX.i.i.i.i.i.i = getelementptr inbounds %"class.llvm::SmallVector", %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0, i32 2
+  %add.ptr.i.i.i.i2.i.i = getelementptr inbounds %"union.llvm::SmallVectorBase::U", %"union.llvm::SmallVectorBase::U"* %FirstEl.i.i.i.i.i.i, i64 2
   %add.ptr.i.i.i.i.i.i = bitcast %"union.llvm::SmallVectorBase::U"* %add.ptr.i.i.i.i2.i.i to i8*
   store i8* %add.ptr.i.i.i.i.i.i, i8** %CapacityX.i.i.i.i.i.i, align 16, !tbaa !4
-  %EndX.i = getelementptr inbounds %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0, i32 1
-  %2 = load i8** %EndX.i, align 8, !tbaa !4
-  %CapacityX.i = getelementptr inbounds %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0, i32 2
+  %EndX.i = getelementptr inbounds %"class.llvm::SmallVector", %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0, i32 1
+  %2 = load i8*, i8** %EndX.i, align 8, !tbaa !4
+  %CapacityX.i = getelementptr inbounds %"class.llvm::SmallVector", %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0, i32 2
   %cmp.i = icmp ult i8* %2, %add.ptr.i.i.i.i.i.i
   br i1 %cmp.i, label %Retry.i, label %if.end.i
 
@@ -46,23 +46,23 @@ new.notnull.i:                                    ; preds = %Retry.i
   br label %invoke.cont
 
 if.end.i:                                         ; preds = %entry
-  %5 = getelementptr inbounds %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0
+  %5 = getelementptr inbounds %"class.llvm::SmallVector", %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0
   invoke void @_ZN4llvm15SmallVectorBase8grow_podEmm(%"class.llvm::SmallVectorBase"* %5, i64 0, i64 4)
           to label %.noexc unwind label %lpad
 
 .noexc:                                           ; preds = %if.end.i
-  %.pre.i = load i8** %EndX.i, align 8, !tbaa !4
+  %.pre.i = load i8*, i8** %EndX.i, align 8, !tbaa !4
   br label %Retry.i
 
 invoke.cont:                                      ; preds = %new.notnull.i, %Retry.i
-  %add.ptr.i = getelementptr inbounds i8* %3, i64 4
+  %add.ptr.i = getelementptr inbounds i8, i8* %3, i64 4
   store i8* %add.ptr.i, i8** %EndX.i, align 8, !tbaa !4
-  %6 = load i8** %CapacityX.i, align 16, !tbaa !4
+  %6 = load i8*, i8** %CapacityX.i, align 16, !tbaa !4
   %cmp.i8 = icmp ult i8* %add.ptr.i, %6
   br i1 %cmp.i8, label %new.notnull.i11, label %if.end.i14
 
 Retry.i10:                                        ; preds = %if.end.i14
-  %.pre.i13 = load i8** %EndX.i, align 8, !tbaa !4
+  %.pre.i13 = load i8*, i8** %EndX.i, align 8, !tbaa !4
   %new.isnull.i9 = icmp eq i8* %.pre.i13, null
   br i1 %new.isnull.i9, label %invoke.cont2, label %new.notnull.i11
 
@@ -73,19 +73,19 @@ new.notnull.i11:                                  ; preds = %invoke.cont, %Retry
   br label %invoke.cont2
 
 if.end.i14:                                       ; preds = %invoke.cont
-  %9 = getelementptr inbounds %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0
+  %9 = getelementptr inbounds %"class.llvm::SmallVector", %"class.llvm::SmallVector"* %sv, i64 0, i32 0, i32 0, i32 0, i32 0
   invoke void @_ZN4llvm15SmallVectorBase8grow_podEmm(%"class.llvm::SmallVectorBase"* %9, i64 0, i64 4)
           to label %Retry.i10 unwind label %lpad
 
 invoke.cont2:                                     ; preds = %new.notnull.i11, %Retry.i10
   %10 = phi i8* [ null, %Retry.i10 ], [ %7, %new.notnull.i11 ]
-  %add.ptr.i12 = getelementptr inbounds i8* %10, i64 4
+  %add.ptr.i12 = getelementptr inbounds i8, i8* %10, i64 4
   store i8* %add.ptr.i12, i8** %EndX.i, align 8, !tbaa !4
   invoke void @_Z1gRN4llvm11SmallVectorIiLj8EEE(%"class.llvm::SmallVector"* %sv)
           to label %invoke.cont3 unwind label %lpad
 
 invoke.cont3:                                     ; preds = %invoke.cont2
-  %11 = load i8** %BeginX.i.i.i.i.i.i, align 16, !tbaa !4
+  %11 = load i8*, i8** %BeginX.i.i.i.i.i.i, align 16, !tbaa !4
   %cmp.i.i.i.i19 = icmp eq i8* %11, %1
   br i1 %cmp.i.i.i.i19, label %_ZN4llvm11SmallVectorIiLj8EED1Ev.exit21, label %if.then.i.i.i20
 
@@ -100,7 +100,7 @@ _ZN4llvm11SmallVectorIiLj8EED1Ev.exit21:          ; preds = %invoke.cont3, %if.t
 lpad:                                             ; preds = %if.end.i14, %if.end.i, %invoke.cont2
   %12 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
           cleanup
-  %13 = load i8** %BeginX.i.i.i.i.i.i, align 16, !tbaa !4
+  %13 = load i8*, i8** %BeginX.i.i.i.i.i.i, align 16, !tbaa !4
   %cmp.i.i.i.i = icmp eq i8* %13, %1
   br i1 %cmp.i.i.i.i, label %eh.resume, label %if.then.i.i.i
 
diff --git a/test/Transforms/GVN/condprop.ll b/test/Transforms/GVN/condprop.ll
index 845f88e15895..6aa3cb862509 100644
--- a/test/Transforms/GVN/condprop.ll
+++ b/test/Transforms/GVN/condprop.ll
@@ -5,7 +5,7 @@
 ; CHECK-LABEL: @test1(
 define i32 @test1() nounwind {
 entry:
-	%0 = load i32* @a, align 4
+	%0 = load i32, i32* @a, align 4
 	%1 = icmp eq i32 %0, 4
 	br i1 %1, label %bb, label %bb1
 
@@ -13,7 +13,7 @@ bb:		; preds = %entry
 	br label %bb8
 
 bb1:		; preds = %entry
-	%2 = load i32* @a, align 4
+	%2 = load i32, i32* @a, align 4
 	%3 = icmp eq i32 %2, 5
 	br i1 %3, label %bb2, label %bb3
 
@@ -21,29 +21,29 @@ bb2:		; preds = %bb1
 	br label %bb8
 
 bb3:		; preds = %bb1
-	%4 = load i32* @a, align 4
+	%4 = load i32, i32* @a, align 4
 	%5 = icmp eq i32 %4, 4
 ; CHECK: br i1 false, label %bb4, label %bb5
 	br i1 %5, label %bb4, label %bb5
 
 bb4:		; preds = %bb3
-	%6 = load i32* @a, align 4
+	%6 = load i32, i32* @a, align 4
 	%7 = add i32 %6, 5
 	br label %bb8
 
 bb5:		; preds = %bb3
-	%8 = load i32* @a, align 4
+	%8 = load i32, i32* @a, align 4
 	%9 = icmp eq i32 %8, 5
 ; CHECK: br i1 false, label %bb6, label %bb7
 	br i1 %9, label %bb6, label %bb7
 
 bb6:		; preds = %bb5
-	%10 = load i32* @a, align 4
+	%10 = load i32, i32* @a, align 4
 	%11 = add i32 %10, 4
 	br label %bb8
 
 bb7:		; preds = %bb5
-	%12 = load i32* @a, align 4
+	%12 = load i32, i32* @a, align 4
 	br label %bb8
 
 bb8:		; preds = %bb7, %bb6, %bb4, %bb2, %bb
diff --git a/test/Transforms/GVN/crash-no-aa.ll b/test/Transforms/GVN/crash-no-aa.ll
index 9ad63a7350c2..f076a8d81ace 100644
--- a/test/Transforms/GVN/crash-no-aa.ll
+++ b/test/Transforms/GVN/crash-no-aa.ll
@@ -5,11 +5,11 @@ target triple = "x86_64-unknown-freebsd8.0"
 
 ; PR5744
 define i32 @test1({i16, i32} *%P) {
-  %P2 = getelementptr {i16, i32} *%P, i32 0, i32 0
+  %P2 = getelementptr {i16, i32}, {i16, i32} *%P, i32 0, i32 0
   store i16 42, i16* %P2
 
-  %P3 = getelementptr {i16, i32} *%P, i32 0, i32 1
-  %V = load i32* %P3
+  %P3 = getelementptr {i16, i32}, {i16, i32} *%P, i32 0, i32 1
+  %V = load i32, i32* %P3
   ret i32 %V
 }
 
diff --git a/test/Transforms/GVN/crash.ll b/test/Transforms/GVN/crash.ll
index 9fb612fcae13..2abb4194f159 100644
--- a/test/Transforms/GVN/crash.ll
+++ b/test/Transforms/GVN/crash.ll
@@ -22,7 +22,7 @@ while.body:                                       ; preds = %while.body.backedge
 
 lor.lhs.false:                                    ; preds = %while.body
   %tmp20 = bitcast i32* %o.addr.0 to i32*         ; <i32*> [#uses=1]
-  %tmp22 = load i32* %tmp20                       ; <i32> [#uses=0]
+  %tmp22 = load i32, i32* %tmp20                       ; <i32> [#uses=0]
   br i1 undef, label %land.lhs.true24, label %if.end31
 
 land.lhs.true24:                                  ; preds = %lor.lhs.false
@@ -34,11 +34,11 @@ if.end31:                                         ; preds = %land.lhs.true24, %l
 
 if.end41:                                         ; preds = %if.end31
   %tmp43 = bitcast i32* %o.addr.0 to i32*         ; <i32*> [#uses=1]
-  %tmp45 = load i32* %tmp43                       ; <i32> [#uses=0]
+  %tmp45 = load i32, i32* %tmp43                       ; <i32> [#uses=0]
   br i1 undef, label %if.then50, label %if.else
 
 if.then50:                                        ; preds = %if.end41
-  %tmp53 = load i32** undef                       ; <i32*> [#uses=1]
+  %tmp53 = load i32*, i32** undef                       ; <i32*> [#uses=1]
   br label %while.body.backedge
 
 if.else:                                          ; preds = %if.end41
@@ -74,16 +74,16 @@ entry:
   br label %bb69.i
 
 bb69.i:                                           ; preds = %bb57.i.preheader
-  %tmp4 = getelementptr inbounds [4 x %struct.attribute_spec*]* @attribute_tables, i32 0, i32 undef ; <%struct.attribute_spec**> [#uses=1]
-  %tmp3 = load %struct.attribute_spec** %tmp4, align 4 ; <%struct.attribute_spec*> [#uses=1]
+  %tmp4 = getelementptr inbounds [4 x %struct.attribute_spec*], [4 x %struct.attribute_spec*]* @attribute_tables, i32 0, i32 undef ; <%struct.attribute_spec**> [#uses=1]
+  %tmp3 = load %struct.attribute_spec*, %struct.attribute_spec** %tmp4, align 4 ; <%struct.attribute_spec*> [#uses=1]
   br label %bb65.i
 
 bb65.i:                                           ; preds = %bb65.i.preheader, %bb64.i
   %storemerge6.i = phi i32 [ 1, %bb64.i ], [ 0, %bb69.i ] ; <i32> [#uses=3]
-  %scevgep14 = getelementptr inbounds %struct.attribute_spec* %tmp3, i32 %storemerge6.i, i32 0 ; <i8**> [#uses=1]
-  %tmp2 = load i8** %scevgep14, align 4           ; <i8*> [#uses=0]
-  %tmp = load %struct.attribute_spec** %tmp4, align 4 ; <%struct.attribute_spec*> [#uses=1]
-  %scevgep1516 = getelementptr inbounds %struct.attribute_spec* %tmp, i32 %storemerge6.i, i32 0 ; <i8**> [#uses=0]
+  %scevgep14 = getelementptr inbounds %struct.attribute_spec, %struct.attribute_spec* %tmp3, i32 %storemerge6.i, i32 0 ; <i8**> [#uses=1]
+  %tmp2 = load i8*, i8** %scevgep14, align 4           ; <i8*> [#uses=0]
+  %tmp = load %struct.attribute_spec*, %struct.attribute_spec** %tmp4, align 4 ; <%struct.attribute_spec*> [#uses=1]
+  %scevgep1516 = getelementptr inbounds %struct.attribute_spec, %struct.attribute_spec* %tmp, i32 %storemerge6.i, i32 0 ; <i8**> [#uses=0]
   unreachable
 
 bb64.i:                                           ; Unreachable
@@ -101,7 +101,7 @@ bb66.i:                                           ; Unreachable
 
 define i32* @test3() {
 do.end17.i:
-  %tmp18.i = load i7** undef
+  %tmp18.i = load i7*, i7** undef
   %tmp1 = bitcast i7* %tmp18.i to i8*
   br i1 undef, label %do.body36.i, label %if.then21.i
 
@@ -110,12 +110,12 @@ if.then21.i:
   ret i32* undef
 
 do.body36.i:
-  %ivar38.i = load i64* @g 
+  %ivar38.i = load i64, i64* @g 
   %tmp3 = bitcast i7* %tmp18.i to i8*
   %add.ptr39.sum.i = add i64 %ivar38.i, 8
-  %tmp40.i = getelementptr inbounds i8* %tmp3, i64 %add.ptr39.sum.i
+  %tmp40.i = getelementptr inbounds i8, i8* %tmp3, i64 %add.ptr39.sum.i
   %tmp4 = bitcast i8* %tmp40.i to i64*
-  %tmp41.i = load i64* %tmp4
+  %tmp41.i = load i64, i64* %tmp4
   br i1 undef, label %if.then48.i, label %do.body57.i
 
 if.then48.i:
@@ -123,13 +123,13 @@ if.then48.i:
   br label %do.body57.i
 
 do.body57.i:
-  %tmp58.i = load i7** undef
-  %ivar59.i = load i64* @g
+  %tmp58.i = load i7*, i7** undef
+  %ivar59.i = load i64, i64* @g
   %tmp5 = bitcast i7* %tmp58.i to i8*
   %add.ptr65.sum.i = add i64 %ivar59.i, 8
-  %tmp66.i = getelementptr inbounds i8* %tmp5, i64 %add.ptr65.sum.i
+  %tmp66.i = getelementptr inbounds i8, i8* %tmp5, i64 %add.ptr65.sum.i
   %tmp6 = bitcast i8* %tmp66.i to i64*
-  %tmp67.i = load i64* %tmp6
+  %tmp67.i = load i64, i64* %tmp6
   ret i32* undef
 }
 
@@ -142,10 +142,10 @@ entry:
   ret i32 0
   
 dead:
-  %P2 = getelementptr i32 *%P2, i32 52
-  %Q2 = getelementptr i32 *%Q2, i32 52
+  %P2 = getelementptr i32, i32 *%P2, i32 52
+  %Q2 = getelementptr i32, i32 *%Q2, i32 52
   store i32 4, i32* %P2
-  %A = load i32* %Q2
+  %A = load i32, i32* %Q2
   br i1 true, label %dead, label %dead2
   
 dead2:
@@ -156,10 +156,10 @@ dead2:
 ; PR9841
 define fastcc i8 @test5(i8* %P) nounwind {
 entry:
-  %0 = load i8* %P, align 2
+  %0 = load i8, i8* %P, align 2
 
-  %Q = getelementptr i8* %P, i32 1
-  %1 = load i8* %Q, align 1
+  %Q = getelementptr i8, i8* %P, i32 1
+  %1 = load i8, i8* %Q, align 1
   ret i8 %1
 }
 
@@ -178,16 +178,16 @@ entry:
 ;; Unreachable code.
 
 unreachable.bb:
-  %gep.val = getelementptr inbounds %struct.type* %gep.val, i64 1
+  %gep.val = getelementptr inbounds %struct.type, %struct.type* %gep.val, i64 1
   br i1 undef, label %u2.bb, label %u1.bb
 
 u1.bb:
-  %tmp1 = getelementptr inbounds %struct.type* %gep.val, i64 0, i32 0
+  %tmp1 = getelementptr inbounds %struct.type, %struct.type* %gep.val, i64 0, i32 0
   store i64 -1, i64* %tmp1, align 8
   br label %unreachable.bb
 
 u2.bb:
-  %0 = load i32* undef, align 4
+  %0 = load i32, i32* undef, align 4
   %conv.i.i.i.i.i = zext i32 %0 to i64
   br label %u2.bb
 
diff --git a/test/Transforms/GVN/invariant-load.ll b/test/Transforms/GVN/invariant-load.ll
index 2f9f2a6100fb..982da8cfe486 100644
--- a/test/Transforms/GVN/invariant-load.ll
+++ b/test/Transforms/GVN/invariant-load.ll
@@ -3,13 +3,13 @@
 
 define i32 @test1(i32* nocapture %p, i8* nocapture %q) {
 ; CHECK-LABEL: test1
-; CHECK: %x = load i32* %p, align 4, !invariant.load !0
+; CHECK: %x = load i32, i32* %p, align 4, !invariant.load !0
 ; CHECK-NOT: %y = load
 entry:
-  %x = load i32* %p, align 4, !invariant.load !0
+  %x = load i32, i32* %p, align 4, !invariant.load !0
   %conv = trunc i32 %x to i8
   store i8 %conv, i8* %q, align 1
-  %y = load i32* %p, align 4, !invariant.load !0
+  %y = load i32, i32* %p, align 4, !invariant.load !0
   %add = add i32 %y, 1
   ret i32 %add
 }
@@ -19,13 +19,101 @@ define i32 @test2(i32* nocapture %p, i8* nocapture %q) {
 ; CHECK-NOT: !invariant.load
 ; CHECK-NOT: %y = load
 entry:
-  %x = load i32* %p, align 4
+  %x = load i32, i32* %p, align 4
   %conv = trunc i32 %x to i8
   store i8 %conv, i8* %q, align 1
-  %y = load i32* %p, align 4, !invariant.load !0
+  %y = load i32, i32* %p, align 4, !invariant.load !0
   %add = add i32 %y, 1
   ret i32 %add
 }
 
+; With the invariant.load metadata, what would otherwise
+; be a case for PRE becomes a full redundancy.
+define i32 @test3(i1 %cnd, i32* %p, i32* %q) {
+; CHECK-LABEL: test3
+; CHECK-NOT: load
+entry:
+  %v1 = load i32, i32* %p
+  br i1 %cnd, label %bb1, label %bb2
+
+bb1:
+  store i32 5, i32* %q
+  br label %bb2
+
+bb2:
+  %v2 = load i32, i32* %p, !invariant.load !0
+  %res = sub i32 %v1, %v2
+  ret i32 %res
+}
+
+; This test is here to document a case which doesn't optimize
+; as well as it could.  
+define i32 @test4(i1 %cnd, i32* %p, i32* %q) {
+; CHECK-LABEL: test4
+; %v2 is redundant, but GVN currently doesn't catch that
+entry:
+  %v1 = load i32, i32* %p, !invariant.load !0
+  br i1 %cnd, label %bb1, label %bb2
+
+bb1:
+  store i32 5, i32* %q
+  br label %bb2
+
+bb2:
+  %v2 = load i32, i32* %p
+  %res = sub i32 %v1, %v2
+  ret i32 %res
+}
+
+; Checks that we return the mustalias store as a def
+; so that it contributes to value forwarding.  Note
+; that we could and should remove the store too.
+define i32 @test5(i1 %cnd, i32* %p) {
+; CHECK-LABEL: test5
+; CHECK-LABEL: entry:
+; CHECK-NEXT: store i32 5, i32* %p
+; CHECK-NEXT: ret i32 5
+entry:
+  %v1 = load i32, i32* %p, !invariant.load !0
+  store i32 5, i32* %p ;; must alias store, want to exploit
+  %v2 = load i32, i32* %p, !invariant.load !0
+  ret i32 %v2
+}
+
+
+declare void @foo()
+
+; Clobbering (mayalias) stores, even in function calls, can be ignored
+define i32 @test6(i1 %cnd, i32* %p) {
+; CHECK-LABEL: test6
+; CHECK-LABEL: entry:
+; CHECK-NEXT: @foo
+; CHECK-NEXT: ret i32 0
+entry:
+  %v1 = load i32, i32* %p, !invariant.load !0
+  call void @foo()
+  %v2 = load i32, i32* %p, !invariant.load !0
+  %res = sub i32 %v1, %v2
+  ret i32 %res
+}
+
+declare noalias i32* @bar(...) 
+
+; Same as previous, but a function with a noalias result (since they're handled
+; differently in MDA)
+define i32 @test7(i1 %cnd, i32* %p) {
+; CHECK-LABEL: test7
+; CHECK-LABEL: entry:
+; CHECK-NEXT: @bar
+; CHECK-NEXT: ret i32 0
+entry:
+  %v1 = load i32, i32* %p, !invariant.load !0
+  call i32* (...) @bar(i32* %p)
+  %v2 = load i32, i32* %p, !invariant.load !0
+  %res = sub i32 %v1, %v2
+  ret i32 %res
+}
+
+
 !0 = !{ }
 
diff --git a/test/Transforms/GVN/lifetime-simple.ll b/test/Transforms/GVN/lifetime-simple.ll
index 02f7bcc9e857..d03b62c8158a 100644
--- a/test/Transforms/GVN/lifetime-simple.ll
+++ b/test/Transforms/GVN/lifetime-simple.ll
@@ -9,10 +9,10 @@ define i8 @test(i8* %P) nounwind {
 ; CHECK: lifetime.end
 entry:
   call void @llvm.lifetime.start(i64 32, i8* %P)
-  %0 = load i8* %P
+  %0 = load i8, i8* %P
   store i8 1, i8* %P
   call void @llvm.lifetime.end(i64 32, i8* %P)
-  %1 = load i8* %P
+  %1 = load i8, i8* %P
   ret i8 %1
 }
 
diff --git a/test/Transforms/GVN/load-constant-mem.ll b/test/Transforms/GVN/load-constant-mem.ll
index a7dacea6b5da..f870485630fa 100644
--- a/test/Transforms/GVN/load-constant-mem.ll
+++ b/test/Transforms/GVN/load-constant-mem.ll
@@ -4,10 +4,10 @@
 
 define i32 @test(i8* %p, i32 %i) nounwind {
 entry:
-	%P = getelementptr [4 x i32]* @G, i32 0, i32 %i
-	%A = load i32* %P
+	%P = getelementptr [4 x i32], [4 x i32]* @G, i32 0, i32 %i
+	%A = load i32, i32* %P
 	store i8 4, i8* %p
-	%B = load i32* %P
+	%B = load i32, i32* %P
 	%C = sub i32 %A, %B
 	ret i32 %C
 }
diff --git a/test/Transforms/GVN/load-from-unreachable-predecessor.ll b/test/Transforms/GVN/load-from-unreachable-predecessor.ll
index b676d958aa4a..29ea14d62b40 100644
--- a/test/Transforms/GVN/load-from-unreachable-predecessor.ll
+++ b/test/Transforms/GVN/load-from-unreachable-predecessor.ll
@@ -8,13 +8,13 @@ define i32 @f(i32** %f) {
 ; Load should be removed, since it's ignored.
 ; CHECK-NEXT: br label
 bb0:
-  %bar = load i32** %f
+  %bar = load i32*, i32** %f
   br label %bb2
 bb1:
-  %zed = load i32** %f
+  %zed = load i32*, i32** %f
   br i1 false, label %bb1, label %bb2
 bb2:
   %foo = phi i32* [ null, %bb0 ], [ %zed, %bb1 ]
-  %storemerge = load i32* %foo
+  %storemerge = load i32, i32* %foo
   ret i32 %storemerge
 }
diff --git a/test/Transforms/GVN/load-pre-align.ll b/test/Transforms/GVN/load-pre-align.ll
index 4816af2f441b..1198cafaeed9 100644
--- a/test/Transforms/GVN/load-pre-align.ll
+++ b/test/Transforms/GVN/load-pre-align.ll
@@ -25,7 +25,7 @@ for.cond.for.end_crit_edge:
   br label %for.end
 
 for.body:
-  %tmp3 = load i32* @p, align 8
+  %tmp3 = load i32, i32* @p, align 8
   %dec = add i32 %tmp3, -1
   store i32 %dec, i32* @p
   %cmp6 = icmp slt i32 %dec, 0
@@ -39,6 +39,6 @@ for.inc:
   br label %for.cond
 
 for.end:
-  %tmp9 = load i32* @p, align 8
+  %tmp9 = load i32, i32* @p, align 8
   ret i32 %tmp9
 }
diff --git a/test/Transforms/GVN/load-pre-licm.ll b/test/Transforms/GVN/load-pre-licm.ll
index 63541ad181d1..d14b01caf779 100644
--- a/test/Transforms/GVN/load-pre-licm.ll
+++ b/test/Transforms/GVN/load-pre-licm.ll
@@ -16,11 +16,11 @@ entry:
 while.body5:
   %indvar = phi i32 [ 0, %entry ], [ %tmp6, %if.end ]
   %tmp5 = add i32 %indvar, 2
-  %arrayidx9 = getelementptr [5001 x i32]* @sortlist, i32 0, i32 %tmp5
+  %arrayidx9 = getelementptr [5001 x i32], [5001 x i32]* @sortlist, i32 0, i32 %tmp5
   %tmp6 = add i32 %indvar, 1
-  %arrayidx = getelementptr [5001 x i32]* @sortlist, i32 0, i32 %tmp6
-  %tmp7 = load i32* %arrayidx, align 4
-  %tmp10 = load i32* %arrayidx9, align 4
+  %arrayidx = getelementptr [5001 x i32], [5001 x i32]* @sortlist, i32 0, i32 %tmp6
+  %tmp7 = load i32, i32* %arrayidx, align 4
+  %tmp10 = load i32, i32* %arrayidx9, align 4
   %cmp11 = icmp sgt i32 %tmp7, %tmp10
   br i1 %cmp11, label %if.then, label %if.end
 
diff --git a/test/Transforms/GVN/load-pre-nonlocal.ll b/test/Transforms/GVN/load-pre-nonlocal.ll
index ae508b96cf59..c75e54db6287 100644
--- a/test/Transforms/GVN/load-pre-nonlocal.ll
+++ b/test/Transforms/GVN/load-pre-nonlocal.ll
@@ -12,8 +12,8 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 
 ; CHECK-LABEL: define i32 @volatile_load
 ; CHECK: for.body:
-; CHECK: %2 = load i32*
-; CHECK: %3 = load volatile i32*
+; CHECK: %2 = load i32, i32*
+; CHECK: %3 = load volatile i32, i32*
 ; CHECK: for.cond.for.end_crit_edge:
 
 define i32 @volatile_load(i32 %n) {
@@ -22,21 +22,21 @@ entry:
   br i1 %cmp6, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:
-  %0 = load i32** @a2, align 8, !tbaa !1
-  %1 = load i32** @a, align 8, !tbaa !1
+  %0 = load i32*, i32** @a2, align 8, !tbaa !1
+  %1 = load i32*, i32** @a, align 8, !tbaa !1
   br label %for.body
 
 for.body:
   %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]
   %s.09 = phi i32 [ 0, %for.body.lr.ph ], [ %add, %for.body ]
   %p.08 = phi i32* [ %0, %for.body.lr.ph ], [ %incdec.ptr, %for.body ]
-  %2 = load i32* %p.08, align 4, !tbaa !5
-  %arrayidx = getelementptr inbounds i32* %1, i64 %indvars.iv
+  %2 = load i32, i32* %p.08, align 4, !tbaa !5
+  %arrayidx = getelementptr inbounds i32, i32* %1, i64 %indvars.iv
   store i32 %2, i32* %arrayidx, align 4, !tbaa !5
-  %3 = load volatile i32* %p.08, align 4, !tbaa !5
+  %3 = load volatile i32, i32* %p.08, align 4, !tbaa !5
   %add = add nsw i32 %3, %s.09
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
-  %incdec.ptr = getelementptr inbounds i32* %p.08, i64 1
+  %incdec.ptr = getelementptr inbounds i32, i32* %p.08, i64 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
   %exitcond = icmp ne i32 %lftr.wideiv, %n
   br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge
@@ -54,7 +54,7 @@ for.end:
 
 ; CHECK-LABEL: define i32 @overaligned_load
 ; CHECK: if.end:
-; CHECK-NOT: %1 = load i32*
+; CHECK-NOT: %1 = load i32, i32*
 
 define i32 @overaligned_load(i32 %a, i32* nocapture %b) {
 entry:
@@ -62,19 +62,19 @@ entry:
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:
-  %0 = load i32* getelementptr inbounds (%struct.S1* @s1, i64 0, i32 0), align 8, !tbaa !5
+  %0 = load i32, i32* getelementptr inbounds (%struct.S1, %struct.S1* @s1, i64 0, i32 0), align 8, !tbaa !5
   br label %if.end
 
 if.else:
-  %arrayidx = getelementptr inbounds i32* %b, i64 2
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 2
   store i32 10, i32* %arrayidx, align 4, !tbaa !5
   br label %if.end
 
 if.end:
   %i.0 = phi i32 [ %0, %if.then ], [ 0, %if.else ]
-  %p.0 = phi i32* [ getelementptr inbounds (%struct.S1* @s1, i64 0, i32 0), %if.then ], [ %b, %if.else ]
-  %add.ptr = getelementptr inbounds i32* %p.0, i64 1
-  %1 = load i32* %add.ptr, align 4, !tbaa !5
+  %p.0 = phi i32* [ getelementptr inbounds (%struct.S1, %struct.S1* @s1, i64 0, i32 0), %if.then ], [ %b, %if.else ]
+  %add.ptr = getelementptr inbounds i32, i32* %p.0, i64 1
+  %1 = load i32, i32* %add.ptr, align 4, !tbaa !5
   %add1 = add nsw i32 %1, %i.0
   ret i32 %add1
 }
diff --git a/test/Transforms/GVN/lpre-call-wrap-2.ll b/test/Transforms/GVN/lpre-call-wrap-2.ll
index 35e3534a9c89..5dc779ef40d1 100644
--- a/test/Transforms/GVN/lpre-call-wrap-2.ll
+++ b/test/Transforms/GVN/lpre-call-wrap-2.ll
@@ -16,10 +16,10 @@ target triple = "i386-apple-darwin7"
 define void @bi_windup(i8* %outbuf, i8 zeroext %bi_buf) nounwind {
 entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
-	%0 = load i32* @outcnt, align 4		; <i32> [#uses=1]
-	%1 = getelementptr i8* %outbuf, i32 %0		; <i8*> [#uses=1]
+	%0 = load i32, i32* @outcnt, align 4		; <i32> [#uses=1]
+	%1 = getelementptr i8, i8* %outbuf, i32 %0		; <i8*> [#uses=1]
 	store i8 %bi_buf, i8* %1, align 1
-	%2 = load i32* @outcnt, align 4		; <i32> [#uses=1]
+	%2 = load i32, i32* @outcnt, align 4		; <i32> [#uses=1]
 	%3 = icmp eq i32 %2, 16384		; <i1> [#uses=1]
 	br i1 %3, label %bb, label %bb1
 
@@ -31,8 +31,8 @@ bb1:		; preds = %bb, %entry
 ; CHECK: bb1:
 ; CHECK-NEXT: phi
 ; CHECK-NEXT: getelementptr
-	%4 = load i32* @outcnt, align 4		; <i32> [#uses=1]
-	%5 = getelementptr i8* %outbuf, i32 %4		; <i8*> [#uses=1]
+	%4 = load i32, i32* @outcnt, align 4		; <i32> [#uses=1]
+	%5 = getelementptr i8, i8* %outbuf, i32 %4		; <i8*> [#uses=1]
 	store i8 %bi_buf, i8* %5, align 1
 	ret void
 }
diff --git a/test/Transforms/GVN/lpre-call-wrap.ll b/test/Transforms/GVN/lpre-call-wrap.ll
index 0646f3fe0aad..274830549394 100644
--- a/test/Transforms/GVN/lpre-call-wrap.ll
+++ b/test/Transforms/GVN/lpre-call-wrap.ll
@@ -19,20 +19,20 @@ target triple = "i386-apple-darwin7"
 
 define void @_Z12testfunctionR1A(%struct.A* %iter) {
 entry:
-	%0 = getelementptr %struct.A* %iter, i32 0, i32 0		; <i32*> [#uses=3]
-	%1 = load i32* %0, align 4		; <i32> [#uses=2]
+	%0 = getelementptr %struct.A, %struct.A* %iter, i32 0, i32 0		; <i32*> [#uses=3]
+	%1 = load i32, i32* %0, align 4		; <i32> [#uses=2]
 	%2 = icmp eq i32 %1, 0		; <i1> [#uses=1]
 	br i1 %2, label %return, label %bb.nph
 
 bb.nph:		; preds = %entry
-	%3 = getelementptr %struct.A* %iter, i32 0, i32 1		; <i32*> [#uses=1]
+	%3 = getelementptr %struct.A, %struct.A* %iter, i32 0, i32 1		; <i32*> [#uses=1]
 	br label %bb
 
 bb:		; preds = %bb3.backedge, %bb.nph
 	%.rle = phi i32 [ %1, %bb.nph ], [ %7, %bb3.backedge ]		; <i32> [#uses=1]
 	%4 = add i32 %.rle, 1		; <i32> [#uses=2]
 	store i32 %4, i32* %0, align 4
-	%5 = load i32* %3, align 4		; <i32> [#uses=1]
+	%5 = load i32, i32* %3, align 4		; <i32> [#uses=1]
 	%6 = icmp eq i32 %4, %5		; <i1> [#uses=1]
 	br i1 %6, label %bb1, label %bb3.backedge
 
@@ -44,7 +44,7 @@ bb3.backedge:		; preds = %bb, %bb1
 ; CHECK: bb3.backedge:
 ; CHECK-NEXT: phi
 ; CHECK-NEXT: icmp
-	%7 = load i32* %0, align 4		; <i32> [#uses=2]
+	%7 = load i32, i32* %0, align 4		; <i32> [#uses=2]
 	%8 = icmp eq i32 %7, 0		; <i1> [#uses=1]
 	br i1 %8, label %return, label %bb
 
diff --git a/test/Transforms/GVN/malloc-load-removal.ll b/test/Transforms/GVN/malloc-load-removal.ll
index d2d2fd77afec..1d7a2ddc4c2d 100644
--- a/test/Transforms/GVN/malloc-load-removal.ll
+++ b/test/Transforms/GVN/malloc-load-removal.ll
@@ -10,7 +10,7 @@ declare i8* @malloc(i64) nounwind
 define noalias i8* @test1() nounwind uwtable ssp {
 entry:
   %call = tail call i8* @malloc(i64 100) nounwind
-  %0 = load i8* %call, align 1
+  %0 = load i8, i8* %call, align 1
   %tobool = icmp eq i8 %0, 0
   br i1 %tobool, label %if.end, label %if.then
 
@@ -35,7 +35,7 @@ declare i8* @_Znwm(i64) nounwind
 define noalias i8* @test2() nounwind uwtable ssp {
 entry:
   %call = tail call i8* @_Znwm(i64 100) nounwind
-  %0 = load i8* %call, align 1
+  %0 = load i8, i8* %call, align 1
   %tobool = icmp eq i8 %0, 0
   br i1 %tobool, label %if.end, label %if.then
 
diff --git a/test/Transforms/GVN/noalias.ll b/test/Transforms/GVN/noalias.ll
index 6c310fad7ec6..cfff096b6952 100644
--- a/test/Transforms/GVN/noalias.ll
+++ b/test/Transforms/GVN/noalias.ll
@@ -2,21 +2,21 @@
 
 define i32 @test1(i32* %p, i32* %q) {
 ; CHECK-LABEL: @test1(i32* %p, i32* %q)
-; CHECK: load i32* %p
+; CHECK: load i32, i32* %p
 ; CHECK-NOT: noalias
 ; CHECK: %c = add i32 %a, %a
-  %a = load i32* %p, !noalias !0
-  %b = load i32* %p
+  %a = load i32, i32* %p, !noalias !0
+  %b = load i32, i32* %p
   %c = add i32 %a, %b
   ret i32 %c
 }
 
 define i32 @test2(i32* %p, i32* %q) {
 ; CHECK-LABEL: @test2(i32* %p, i32* %q)
-; CHECK: load i32* %p, !alias.scope !0
+; CHECK: load i32, i32* %p, !alias.scope !0
 ; CHECK: %c = add i32 %a, %a
-  %a = load i32* %p, !alias.scope !0
-  %b = load i32* %p, !alias.scope !0
+  %a = load i32, i32* %p, !alias.scope !0
+  %b = load i32, i32* %p, !alias.scope !0
   %c = add i32 %a, %b
   ret i32 %c
 }
@@ -27,10 +27,10 @@ define i32 @test2(i32* %p, i32* %q) {
 ; throw in between.
 define i32 @test3(i32* %p, i32* %q) {
 ; CHECK-LABEL: @test3(i32* %p, i32* %q)
-; CHECK: load i32* %p, !alias.scope !1
+; CHECK: load i32, i32* %p, !alias.scope !1
 ; CHECK: %c = add i32 %a, %a
-  %a = load i32* %p, !alias.scope !1
-  %b = load i32* %p, !alias.scope !2
+  %a = load i32, i32* %p, !alias.scope !1
+  %b = load i32, i32* %p, !alias.scope !2
   %c = add i32 %a, %b
   ret i32 %c
 }
diff --git a/test/Transforms/GVN/non-local-offset.ll b/test/Transforms/GVN/non-local-offset.ll
index 0b9edcb8e430..2373ef5888b9 100644
--- a/test/Transforms/GVN/non-local-offset.ll
+++ b/test/Transforms/GVN/non-local-offset.ll
@@ -13,12 +13,12 @@ target datalayout = "e-p:64:64:64"
 define void @yes(i1 %c, i32* %p, i32* %q) nounwind {
 entry:
   store i32 0, i32* %p
-  %p1 = getelementptr inbounds i32* %p, i64 1
+  %p1 = getelementptr inbounds i32, i32* %p, i64 1
   store i32 1, i32* %p1
   br i1 %c, label %if.else, label %if.then
 
 if.then:
-  %t = load i32* %p
+  %t = load i32, i32* %p
   store i32 %t, i32* %q
   ret void
 
@@ -35,25 +35,25 @@ if.else:
 ; CHECK-NEXT: store i32 0, i32* %q
 ; CHECK-NEXT: ret void
 ; CHECK: if.else:
-; CHECK: load i64* %pc
+; CHECK: load i64, i64* %pc
 ; CHECK: store i64
 
 define void @watch_out_for_size_change(i1 %c, i32* %p, i32* %q) nounwind {
 entry:
   store i32 0, i32* %p
-  %p1 = getelementptr inbounds i32* %p, i64 1
+  %p1 = getelementptr inbounds i32, i32* %p, i64 1
   store i32 1, i32* %p1
   br i1 %c, label %if.else, label %if.then
 
 if.then:
-  %t = load i32* %p
+  %t = load i32, i32* %p
   store i32 %t, i32* %q
   ret void
 
 if.else:
   %pc = bitcast i32* %p to i64*
   %qc = bitcast i32* %q to i64*
-  %t64 = load i64* %pc
+  %t64 = load i64, i64* %pc
   store i64 %t64, i64* %qc
   ret void
 }
diff --git a/test/Transforms/GVN/nonescaping-malloc.ll b/test/Transforms/GVN/nonescaping-malloc.ll
index c2eeed56ffc1..f83b317fade4 100644
--- a/test/Transforms/GVN/nonescaping-malloc.ll
+++ b/test/Transforms/GVN/nonescaping-malloc.ll
@@ -22,10 +22,10 @@ target triple = "x86_64-apple-darwin10.0"
 define %"struct.llvm::StringMapEntry<void*>"* @_Z3fooRN4llvm9StringMapIPvNS_15MallocAllocatorEEEPKc(%"struct.llvm::StringMap<void*,llvm::MallocAllocator>"* %X, i8* %P) ssp {
 entry:
   %tmp = alloca %"struct.llvm::StringRef", align 8
-  %tmp.i = getelementptr inbounds %"struct.llvm::StringRef"* %tmp, i64 0, i32 0
+  %tmp.i = getelementptr inbounds %"struct.llvm::StringRef", %"struct.llvm::StringRef"* %tmp, i64 0, i32 0
   store i8* %P, i8** %tmp.i, align 8
   %tmp1.i = call i64 @strlen(i8* %P) nounwind readonly
-  %tmp2.i = getelementptr inbounds %"struct.llvm::StringRef"* %tmp, i64 0, i32 1
+  %tmp2.i = getelementptr inbounds %"struct.llvm::StringRef", %"struct.llvm::StringRef"* %tmp, i64 0, i32 1
   store i64 %tmp1.i, i64* %tmp2.i, align 8
   %tmp1 = call %"struct.llvm::StringMapEntry<void*>"* @_ZN4llvm9StringMapIPvNS_15MallocAllocatorEE16GetOrCreateValueERKNS_9StringRefE(%"struct.llvm::StringMap<void*,llvm::MallocAllocator>"* %X, %"struct.llvm::StringRef"* %tmp) ssp
   ret %"struct.llvm::StringMapEntry<void*>"* %tmp1
@@ -40,16 +40,16 @@ declare i32 @_ZN4llvm13StringMapImpl15LookupBucketForENS_9StringRefE(%"struct.ll
 define linkonce_odr %"struct.llvm::StringMapEntry<void*>"* @_ZN4llvm9StringMapIPvNS_15MallocAllocatorEE16GetOrCreateValueERKNS_9StringRefE(%"struct.llvm::StringMap<void*,llvm::MallocAllocator>"* %this, %"struct.llvm::StringRef"* nocapture %Key) ssp align 2 {
 entry:
   %elt = bitcast %"struct.llvm::StringRef"* %Key to i64*
-  %val = load i64* %elt
-  %tmp = getelementptr inbounds %"struct.llvm::StringRef"* %Key, i64 0, i32 1
-  %val2 = load i64* %tmp
-  %tmp2.i = getelementptr inbounds %"struct.llvm::StringMap<void*,llvm::MallocAllocator>"* %this, i64 0, i32 0
+  %val = load i64, i64* %elt
+  %tmp = getelementptr inbounds %"struct.llvm::StringRef", %"struct.llvm::StringRef"* %Key, i64 0, i32 1
+  %val2 = load i64, i64* %tmp
+  %tmp2.i = getelementptr inbounds %"struct.llvm::StringMap<void*,llvm::MallocAllocator>", %"struct.llvm::StringMap<void*,llvm::MallocAllocator>"* %this, i64 0, i32 0
   %tmp3.i = tail call i32 @_ZN4llvm13StringMapImpl15LookupBucketForENS_9StringRefE(%"struct.llvm::StringMapImpl"* %tmp2.i, i64 %val, i64 %val2)
-  %tmp4.i = getelementptr inbounds %"struct.llvm::StringMap<void*,llvm::MallocAllocator>"* %this, i64 0, i32 0, i32 0
-  %tmp5.i = load %"struct.llvm::StringMapImpl::ItemBucket"** %tmp4.i, align 8
+  %tmp4.i = getelementptr inbounds %"struct.llvm::StringMap<void*,llvm::MallocAllocator>", %"struct.llvm::StringMap<void*,llvm::MallocAllocator>"* %this, i64 0, i32 0, i32 0
+  %tmp5.i = load %"struct.llvm::StringMapImpl::ItemBucket"*, %"struct.llvm::StringMapImpl::ItemBucket"** %tmp4.i, align 8
   %tmp6.i = zext i32 %tmp3.i to i64
-  %tmp7.i = getelementptr inbounds %"struct.llvm::StringMapImpl::ItemBucket"* %tmp5.i, i64 %tmp6.i, i32 1
-  %tmp8.i = load %"struct.llvm::StringMapEntryBase"** %tmp7.i, align 8
+  %tmp7.i = getelementptr inbounds %"struct.llvm::StringMapImpl::ItemBucket", %"struct.llvm::StringMapImpl::ItemBucket"* %tmp5.i, i64 %tmp6.i, i32 1
+  %tmp8.i = load %"struct.llvm::StringMapEntryBase"*, %"struct.llvm::StringMapEntryBase"** %tmp7.i, align 8
   %tmp9.i = icmp eq %"struct.llvm::StringMapEntryBase"* %tmp8.i, null
   %tmp13.i = icmp eq %"struct.llvm::StringMapEntryBase"* %tmp8.i, inttoptr (i64 -1 to %"struct.llvm::StringMapEntryBase"*)
   %or.cond.i = or i1 %tmp9.i, %tmp13.i
@@ -57,7 +57,7 @@ entry:
 
 bb4.i:                                            ; preds = %entry
   %tmp41.i = inttoptr i64 %val to i8*
-  %tmp4.i35.i = getelementptr inbounds i8* %tmp41.i, i64 %val2
+  %tmp4.i35.i = getelementptr inbounds i8, i8* %tmp41.i, i64 %val2
   %tmp.i.i = ptrtoint i8* %tmp4.i35.i to i64
   %tmp1.i.i = trunc i64 %tmp.i.i to i32
   %tmp3.i.i = trunc i64 %val to i32
@@ -72,22 +72,22 @@ bb4.i:                                            ; preds = %entry
 bb.i.i:                                           ; preds = %bb4.i
   %tmp.i.i.i.i = bitcast i8* %tmp.i20.i.i to i32*
   store i32 %tmp4.i.i, i32* %tmp.i.i.i.i, align 4
-  %tmp1.i19.i.i = getelementptr inbounds i8* %tmp.i20.i.i, i64 8
+  %tmp1.i19.i.i = getelementptr inbounds i8, i8* %tmp.i20.i.i, i64 8
   %0 = bitcast i8* %tmp1.i19.i.i to i8**
   store i8* null, i8** %0, align 8
   br label %_ZN4llvm14StringMapEntryIPvE6CreateINS_15MallocAllocatorES1_EEPS2_PKcS7_RT_T0_.exit.i
 
 _ZN4llvm14StringMapEntryIPvE6CreateINS_15MallocAllocatorES1_EEPS2_PKcS7_RT_T0_.exit.i: ; preds = %bb.i.i, %bb4.i
-  %tmp.i18.i.i = getelementptr inbounds i8* %tmp.i20.i.i, i64 16
+  %tmp.i18.i.i = getelementptr inbounds i8, i8* %tmp.i20.i.i, i64 16
   %tmp15.i.i = zext i32 %tmp4.i.i to i64
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp.i18.i.i, i8* %tmp41.i, i64 %tmp15.i.i, i32 1, i1 false)
   %tmp.i18.sum.i.i = add i64 %tmp15.i.i, 16
-  %tmp17.i.i = getelementptr inbounds i8* %tmp.i20.i.i, i64 %tmp.i18.sum.i.i
+  %tmp17.i.i = getelementptr inbounds i8, i8* %tmp.i20.i.i, i64 %tmp.i18.sum.i.i
   store i8 0, i8* %tmp17.i.i, align 1
-  %tmp.i.i.i = getelementptr inbounds i8* %tmp.i20.i.i, i64 8
+  %tmp.i.i.i = getelementptr inbounds i8, i8* %tmp.i20.i.i, i64 8
   %1 = bitcast i8* %tmp.i.i.i to i8**
   store i8* null, i8** %1, align 8
-  %tmp22.i = load %"struct.llvm::StringMapEntryBase"** %tmp7.i, align 8
+  %tmp22.i = load %"struct.llvm::StringMapEntryBase"*, %"struct.llvm::StringMapEntryBase"** %tmp7.i, align 8
   %tmp24.i = icmp eq %"struct.llvm::StringMapEntryBase"* %tmp22.i, inttoptr (i64 -1 to %"struct.llvm::StringMapEntryBase"*)
   br i1 %tmp24.i, label %bb9.i, label %_ZN4llvm9StringMapIPvNS_15MallocAllocatorEE16GetOrCreateValueIS1_EERNS_14StringMapEntryIS1_EENS_9StringRefET_.exit
 
@@ -96,8 +96,8 @@ bb6.i:                                            ; preds = %entry
   ret %"struct.llvm::StringMapEntry<void*>"* %tmp16.i
 
 bb9.i:                                            ; preds = %_ZN4llvm14StringMapEntryIPvE6CreateINS_15MallocAllocatorES1_EEPS2_PKcS7_RT_T0_.exit.i
-  %tmp25.i = getelementptr inbounds %"struct.llvm::StringMap<void*,llvm::MallocAllocator>"* %this, i64 0, i32 0, i32 3
-  %tmp26.i = load i32* %tmp25.i, align 8
+  %tmp25.i = getelementptr inbounds %"struct.llvm::StringMap<void*,llvm::MallocAllocator>", %"struct.llvm::StringMap<void*,llvm::MallocAllocator>"* %this, i64 0, i32 0, i32 3
+  %tmp26.i = load i32, i32* %tmp25.i, align 8
   %tmp27.i = add i32 %tmp26.i, -1
   store i32 %tmp27.i, i32* %tmp25.i, align 8
   ret %"struct.llvm::StringMapEntry<void*>"* %tmp10.i.i
diff --git a/test/Transforms/GVN/null-aliases-nothing.ll b/test/Transforms/GVN/null-aliases-nothing.ll
index 37bf09d7f3ff..0b7c5eb5bf95 100644
--- a/test/Transforms/GVN/null-aliases-nothing.ll
+++ b/test/Transforms/GVN/null-aliases-nothing.ll
@@ -4,12 +4,12 @@
 declare void @test1f(i8*)
 
 define void @test1(%t* noalias %stuff ) {
-    %p = getelementptr inbounds %t* %stuff, i32 0, i32 0
-    %before = load i32* %p
+    %p = getelementptr inbounds %t, %t* %stuff, i32 0, i32 0
+    %before = load i32, i32* %p
 
     call void @test1f(i8* null)
 
-    %after = load i32* %p ; <--- This should be a dead load
+    %after = load i32, i32* %p ; <--- This should be a dead load
     %sum = add i32 %before, %after
 
     store i32 %sum, i32* %p
diff --git a/test/Transforms/GVN/phi-translate-partial-alias.ll b/test/Transforms/GVN/phi-translate-partial-alias.ll
index 47bec41fb163..f1cf53e45dec 100644
--- a/test/Transforms/GVN/phi-translate-partial-alias.ll
+++ b/test/Transforms/GVN/phi-translate-partial-alias.ll
@@ -8,19 +8,19 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 ; CHECK: define void @test0(i8* %begin)
 ; CHECK: loop:
-; CHECK:   %l0 = load i8* %phi
+; CHECK:   %l0 = load i8, i8* %phi
 ; CHECK:   call void @bar(i8 %l0)
-; CHECK:   %l1 = load i8* %phi
+; CHECK:   %l1 = load i8, i8* %phi
 define void @test0(i8* %begin) {
 entry:
   br label %loop
 
 loop:
   %phi = phi i8* [ %begin, %entry ], [ %next, %loop ]
-  %l0 = load i8* %phi
+  %l0 = load i8, i8* %phi
   call void @bar(i8 %l0)
-  %l1 = load i8* %phi
-  %next = getelementptr inbounds i8* %phi, i8 %l1
+  %l1 = load i8, i8* %phi
+  %next = getelementptr inbounds i8, i8* %phi, i8 %l1
   br label %loop
 }
 
diff --git a/test/Transforms/GVN/phi-translate.ll b/test/Transforms/GVN/phi-translate.ll
index 50d6178c5cc2..6068b05aadf5 100644
--- a/test/Transforms/GVN/phi-translate.ll
+++ b/test/Transforms/GVN/phi-translate.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64"
 
 ; CHECK-LABEL: @foo(
 ; CHECK: entry.end_crit_edge:
-; CHECK:   %n.pre = load i32* %q.phi.trans.insert
+; CHECK:   %n.pre = load i32, i32* %q.phi.trans.insert
 ; CHECK: then:
 ; CHECK:   store i32 %z
 ; CHECK: end:
@@ -19,13 +19,13 @@ entry:
 
 then:
   %i = sext i32 %x to i64
-  %p = getelementptr [100 x i32]* @G, i64 0, i64 %i
+  %p = getelementptr [100 x i32], [100 x i32]* @G, i64 0, i64 %i
   store i32 %z, i32* %p
   br label %end
 
 end:
   %j = sext i32 %x to i64
-  %q = getelementptr [100 x i32]* @G, i64 0, i64 %j
-  %n = load i32* %q
+  %q = getelementptr [100 x i32], [100 x i32]* @G, i64 0, i64 %j
+  %n = load i32, i32* %q
   ret i32 %n
 }
diff --git a/test/Transforms/GVN/pr10820.ll b/test/Transforms/GVN/pr10820.ll
index 12c1e70fc387..c6a9a931df02 100644
--- a/test/Transforms/GVN/pr10820.ll
+++ b/test/Transforms/GVN/pr10820.ll
@@ -11,7 +11,7 @@ entry:
 ; CHECK: store i32
   store i32 402662078, i32* bitcast (i31* @g to i32*), align 8
 ; CHECK-NOT: load i31
-  %0 = load i31* @g, align 8
+  %0 = load i31, i31* @g, align 8
 ; CHECK: store i31
   store i31 %0, i31* undef, align 1
   unreachable
diff --git a/test/Transforms/GVN/pr14166.ll b/test/Transforms/GVN/pr14166.ll
index 4d6820506879..eafe418dbdc6 100644
--- a/test/Transforms/GVN/pr14166.ll
+++ b/test/Transforms/GVN/pr14166.ll
@@ -4,16 +4,16 @@ target triple = "i386-pc-linux-gnu"
 define <2 x i32> @test1() {
   %v1 = alloca <2 x i32>
   call void @anything(<2 x i32>* %v1)
-  %v2 = load <2 x i32>* %v1
+  %v2 = load <2 x i32>, <2 x i32>* %v1
   %v3 = inttoptr <2 x i32> %v2 to <2 x i8*>
   %v4 = bitcast <2 x i32>* %v1 to <2 x i8*>*
   store <2 x i8*> %v3, <2 x i8*>* %v4
-  %v5 = load <2 x i32>* %v1
+  %v5 = load <2 x i32>, <2 x i32>* %v1
   ret <2 x i32> %v5
 ; CHECK-LABEL: @test1(
 ; CHECK: %v1 = alloca <2 x i32>
 ; CHECK: call void @anything(<2 x i32>* %v1)
-; CHECK: %v2 = load <2 x i32>* %v1
+; CHECK: %v2 = load <2 x i32>, <2 x i32>* %v1
 ; CHECK: %v3 = inttoptr <2 x i32> %v2 to <2 x i8*>
 ; CHECK: %v4 = bitcast <2 x i32>* %v1 to <2 x i8*>*
 ; CHECK: store <2 x i8*> %v3, <2 x i8*>* %v4
diff --git a/test/Transforms/GVN/pr17732.ll b/test/Transforms/GVN/pr17732.ll
index 606a195b8538..6c40ccf45019 100644
--- a/test/Transforms/GVN/pr17732.ll
+++ b/test/Transforms/GVN/pr17732.ll
@@ -14,11 +14,11 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @main() {
 entry:
-  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds (%struct.with_array* @array_with_zeroinit, i64 0, i32 0, i64 0), i8* getelementptr inbounds ({ [2 x i8], i32, i8, [3 x i8] }* @main.obj_with_array, i64 0, i32 0, i64 0), i64 12, i32 4, i1 false)
-  %0 = load i8* getelementptr inbounds (%struct.with_array* @array_with_zeroinit, i64 0, i32 2), align 4
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds (%struct.with_array, %struct.with_array* @array_with_zeroinit, i64 0, i32 0, i64 0), i8* getelementptr inbounds ({ [2 x i8], i32, i8, [3 x i8] }, { [2 x i8], i32, i8, [3 x i8] }* @main.obj_with_array, i64 0, i32 0, i64 0), i64 12, i32 4, i1 false)
+  %0 = load i8, i8* getelementptr inbounds (%struct.with_array, %struct.with_array* @array_with_zeroinit, i64 0, i32 2), align 4
 
-  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds (%struct.with_vector* @vector_with_zeroinit, i64 0, i32 0, i64 0), i8* getelementptr inbounds ({ <2 x i8>, i32, i8, [3 x i8] }* @main.obj_with_vector, i64 0, i32 0, i64 0), i64 12, i32 4, i1 false)
-  %1 = load i8* getelementptr inbounds (%struct.with_vector* @vector_with_zeroinit, i64 0, i32 2), align 4
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds (%struct.with_vector, %struct.with_vector* @vector_with_zeroinit, i64 0, i32 0, i64 0), i8* getelementptr inbounds ({ <2 x i8>, i32, i8, [3 x i8] }, { <2 x i8>, i32, i8, [3 x i8] }* @main.obj_with_vector, i64 0, i32 0, i64 0), i64 12, i32 4, i1 false)
+  %1 = load i8, i8* getelementptr inbounds (%struct.with_vector, %struct.with_vector* @vector_with_zeroinit, i64 0, i32 2), align 4
   %conv0 = sext i8 %0 to i32
   %conv1 = sext i8 %1 to i32
   %and = and i32 %conv0, %conv1
diff --git a/test/Transforms/GVN/pr17852.ll b/test/Transforms/GVN/pr17852.ll
index e95ff7f5c106..9a8a709ba6a5 100644
--- a/test/Transforms/GVN/pr17852.ll
+++ b/test/Transforms/GVN/pr17852.ll
@@ -5,60 +5,60 @@ define void @fn1(%struct.S0* byval align 8 %p1) {
   br label %for.cond
 for.cond:                                         ; preds = %1, %0
   br label %for.end
-  %f2 = getelementptr inbounds %struct.S0* %p1, i64 0, i32 2
-  %f9 = getelementptr inbounds %struct.S0* %p1, i64 0, i32 7
+  %f2 = getelementptr inbounds %struct.S0, %struct.S0* %p1, i64 0, i32 2
+  %f9 = getelementptr inbounds %struct.S0, %struct.S0* %p1, i64 0, i32 7
   br label %for.cond
 for.end:                                          ; preds = %for.cond
   br i1 true, label %if.else, label %if.then
 if.then:                                          ; preds = %for.end
-  %f22 = getelementptr inbounds %struct.S0* %p1, i64 0, i32 2
-  %f7 = getelementptr inbounds %struct.S0* %p1, i64 0, i32 5
-  %tmp7 = load i32* %f7, align 8
+  %f22 = getelementptr inbounds %struct.S0, %struct.S0* %p1, i64 0, i32 2
+  %f7 = getelementptr inbounds %struct.S0, %struct.S0* %p1, i64 0, i32 5
+  %tmp7 = load i32, i32* %f7, align 8
   br label %if.end40
 if.else:                                          ; preds = %for.end
   br i1 false, label %for.cond18, label %if.then6
 if.then6:                                         ; preds = %if.else
-  %f3 = getelementptr inbounds %struct.S0* %p1, i64 0, i32 2
+  %f3 = getelementptr inbounds %struct.S0, %struct.S0* %p1, i64 0, i32 2
   %tmp10 = bitcast %struct.S0* %p1 to i16*
-  %f5 = getelementptr inbounds %struct.S0* %p1, i64 0, i32 3
+  %f5 = getelementptr inbounds %struct.S0, %struct.S0* %p1, i64 0, i32 3
   %tmp11 = bitcast [2 x i8]* %f5 to i16*
-  %bf.load13 = load i16* %tmp11, align 8
+  %bf.load13 = load i16, i16* %tmp11, align 8
   br label %if.end36
 for.cond18:                                       ; preds = %if.else
   call void @fn4()
   br i1 true, label %if.end, label %if.end36
 if.end:                                           ; preds = %for.cond18
-  %f321 = getelementptr inbounds %struct.S0* %p1, i64 0, i32 2
-  %f925 = getelementptr inbounds %struct.S0* %p1, i64 0, i32 7
-  %f526 = getelementptr inbounds %struct.S0* %p1, i64 0, i32 3
+  %f321 = getelementptr inbounds %struct.S0, %struct.S0* %p1, i64 0, i32 2
+  %f925 = getelementptr inbounds %struct.S0, %struct.S0* %p1, i64 0, i32 7
+  %f526 = getelementptr inbounds %struct.S0, %struct.S0* %p1, i64 0, i32 3
   %tmp15 = bitcast [2 x i8]* %f526 to i16*
-  %bf.load27 = load i16* %tmp15, align 8
+  %bf.load27 = load i16, i16* %tmp15, align 8
   %tmp16 = bitcast %struct.S0* %p1 to i16*
   br label %if.end36
 if.end36:                                         ; preds = %if.end, %for.cond18, %if.then6
-  %f537 = getelementptr inbounds %struct.S0* %p1, i64 0, i32 3
+  %f537 = getelementptr inbounds %struct.S0, %struct.S0* %p1, i64 0, i32 3
   %tmp17 = bitcast [2 x i8]* %f537 to i16*
-  %bf.load38 = load i16* %tmp17, align 8
+  %bf.load38 = load i16, i16* %tmp17, align 8
   %bf.clear39 = and i16 %bf.load38, -16384
   br label %if.end40
 if.end40:                                         ; preds = %if.end36, %if.then
-  %f6 = getelementptr inbounds %struct.S0* %p1, i64 0, i32 4
-  %tmp18 = load i32* %f6, align 4
+  %f6 = getelementptr inbounds %struct.S0, %struct.S0* %p1, i64 0, i32 4
+  %tmp18 = load i32, i32* %f6, align 4
   call void @fn2(i32 %tmp18)
-  %f8 = getelementptr inbounds %struct.S0* %p1, i64 0, i32 6
-  %tmp19 = load i32* %f8, align 4
+  %f8 = getelementptr inbounds %struct.S0, %struct.S0* %p1, i64 0, i32 6
+  %tmp19 = load i32, i32* %f8, align 4
   %tobool41 = icmp eq i32 %tmp19, 0
   br i1 true, label %if.end50, label %if.then42
 if.then42:                                        ; preds = %if.end40
   %tmp20 = bitcast %struct.S0* %p1 to i16*
-  %f547 = getelementptr inbounds %struct.S0* %p1, i64 0, i32 3
+  %f547 = getelementptr inbounds %struct.S0, %struct.S0* %p1, i64 0, i32 3
   %tmp21 = bitcast [2 x i8]* %f547 to i16*
-  %bf.load48 = load i16* %tmp21, align 8
+  %bf.load48 = load i16, i16* %tmp21, align 8
   br label %if.end50
 if.end50:                                         ; preds = %if.then42, %if.end40
-  %f551 = getelementptr inbounds %struct.S0* %p1, i64 0, i32 3
+  %f551 = getelementptr inbounds %struct.S0, %struct.S0* %p1, i64 0, i32 3
   %tmp22 = bitcast [2 x i8]* %f551 to i16*
-  %bf.load52 = load i16* %tmp22, align 8
+  %bf.load52 = load i16, i16* %tmp22, align 8
   %bf.clear53 = and i16 %bf.load52, -16384
   ret void
 }
diff --git a/test/Transforms/GVN/pre-basic-add.ll b/test/Transforms/GVN/pre-basic-add.ll
index 4bde05c3387f..fa4e2e3abded 100644
--- a/test/Transforms/GVN/pre-basic-add.ll
+++ b/test/Transforms/GVN/pre-basic-add.ll
@@ -5,8 +5,8 @@
 
 define i32 @test() nounwind {
 entry:
-	%0 = load i32* @H, align 4		; <i32> [#uses=2]
-	%1 = call i32 (...)* @foo() nounwind		; <i32> [#uses=1]
+	%0 = load i32, i32* @H, align 4		; <i32> [#uses=2]
+	%1 = call i32 (...) @foo() nounwind		; <i32> [#uses=1]
 	%2 = icmp ne i32 %1, 0		; <i1> [#uses=1]
 	br i1 %2, label %bb, label %bb1
 
diff --git a/test/Transforms/GVN/pre-compare.ll b/test/Transforms/GVN/pre-compare.ll
index 18d0c2e1085c..a77684a9831e 100644
--- a/test/Transforms/GVN/pre-compare.ll
+++ b/test/Transforms/GVN/pre-compare.ll
@@ -43,7 +43,7 @@ entry:
 
 if.then:                                          ; preds = %entry
   %cmp1 = icmp eq i32 %x, 2
-  %cond = select i1 %cmp1, i8* getelementptr inbounds ([2 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds ([2 x i8]* @.str1, i64 0, i64 0)
+  %cond = select i1 %cmp1, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str1, i64 0, i64 0)
   %call = tail call i32 @puts(i8* %cond) nounwind
   br label %for.cond.preheader
 
@@ -52,11 +52,11 @@ for.cond.preheader:                               ; preds = %entry, %if.then
   br label %for.cond
 
 for.cond:                                         ; preds = %for.cond.backedge, %for.cond.preheader
-  %call2 = tail call i32 @puts(i8* getelementptr inbounds ([7 x i8]* @.str2, i64 0, i64 0)) nounwind
+  %call2 = tail call i32 @puts(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str2, i64 0, i64 0)) nounwind
   br i1 %cmp3, label %for.cond.backedge, label %if.end5
 
 if.end5:                                          ; preds = %for.cond
-  %call6 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str3, i64 0, i64 0), i32 %x) nounwind
+  %call6 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str3, i64 0, i64 0), i32 %x) nounwind
   br label %for.cond.backedge
 
 for.cond.backedge:                                ; preds = %if.end5, %for.cond
diff --git a/test/Transforms/GVN/pre-gep-load.ll b/test/Transforms/GVN/pre-gep-load.ll
index 3ee3a37b81ad..291af359a7a1 100644
--- a/test/Transforms/GVN/pre-gep-load.ll
+++ b/test/Transforms/GVN/pre-gep-load.ll
@@ -13,10 +13,10 @@ entry:
 
 sw.bb:                                            ; preds = %entry, %entry
   %idxprom = sext i32 %i to i64
-  %arrayidx = getelementptr inbounds double** %p, i64 0
-  %0 = load double** %arrayidx, align 8
-  %arrayidx1 = getelementptr inbounds double* %0, i64 %idxprom
-  %1 = load double* %arrayidx1, align 8
+  %arrayidx = getelementptr inbounds double*, double** %p, i64 0
+  %0 = load double*, double** %arrayidx, align 8
+  %arrayidx1 = getelementptr inbounds double, double* %0, i64 %idxprom
+  %1 = load double, double* %arrayidx1, align 8
   %sub = fsub double %1, 1.000000e+00
   %cmp = fcmp olt double %sub, 0.000000e+00
   br i1 %cmp, label %if.then, label %if.end
@@ -29,10 +29,10 @@ if.end:                                           ; preds = %sw.bb
 
 sw.bb2:                                           ; preds = %if.end, %entry
   %idxprom3 = sext i32 %i to i64
-  %arrayidx4 = getelementptr inbounds double** %p, i64 0
-  %2 = load double** %arrayidx4, align 8
-  %arrayidx5 = getelementptr inbounds double* %2, i64 %idxprom3
-  %3 = load double* %arrayidx5, align 8
+  %arrayidx4 = getelementptr inbounds double*, double** %p, i64 0
+  %2 = load double*, double** %arrayidx4, align 8
+  %arrayidx5 = getelementptr inbounds double, double* %2, i64 %idxprom3
+  %3 = load double, double* %arrayidx5, align 8
 ; CHECK: sw.bb2:
 ; CHECK-NEXT-NOT: sext
 ; CHECK-NEXT: phi double [
diff --git a/test/Transforms/GVN/pre-load.ll b/test/Transforms/GVN/pre-load.ll
index 9842886fe3ab..24221d540f22 100644
--- a/test/Transforms/GVN/pre-load.ll
+++ b/test/Transforms/GVN/pre-load.ll
@@ -9,14 +9,14 @@ block1:
 block2:
  br label %block4
 ; CHECK: block2:
-; CHECK-NEXT: load i32* %p
+; CHECK-NEXT: load i32, i32* %p
 
 block3:
   store i32 0, i32* %p
   br label %block4
 
 block4:
-  %PRE = load i32* %p
+  %PRE = load i32, i32* %p
   ret i32 %PRE
 ; CHECK: block4:
 ; CHECK-NEXT: phi i32
@@ -32,7 +32,7 @@ block1:
 block2:
  br label %block4
 ; CHECK: block2:
-; CHECK-NEXT: load i32* %q
+; CHECK-NEXT: load i32, i32* %q
 
 block3:
   store i32 0, i32* %p
@@ -40,7 +40,7 @@ block3:
 
 block4:
   %P2 = phi i32* [%p, %block3], [%q, %block2]
-  %PRE = load i32* %P2
+  %PRE = load i32, i32* %P2
   ret i32 %PRE
 ; CHECK: block4:
 ; CHECK-NEXT: phi i32 [
@@ -52,24 +52,24 @@ block4:
 define i32 @test3(i32* %p, i32* %q, i32** %Hack, i1 %C) {
 ; CHECK-LABEL: @test3(
 block1:
-  %B = getelementptr i32* %q, i32 1
+  %B = getelementptr i32, i32* %q, i32 1
   store i32* %B, i32** %Hack
 	br i1 %C, label %block2, label %block3
 
 block2:
  br label %block4
 ; CHECK: block2:
-; CHECK-NEXT: load i32* %B
+; CHECK-NEXT: load i32, i32* %B
 
 block3:
-  %A = getelementptr i32* %p, i32 1
+  %A = getelementptr i32, i32* %p, i32 1
   store i32 0, i32* %A
   br label %block4
 
 block4:
   %P2 = phi i32* [%p, %block3], [%q, %block2]
-  %P3 = getelementptr i32* %P2, i32 1
-  %PRE = load i32* %P3
+  %P3 = getelementptr i32, i32* %P2, i32 1
+  %PRE = load i32, i32* %P3
   ret i32 %PRE
 ; CHECK: block4:
 ; CHECK-NEXT: phi i32 [
@@ -87,21 +87,21 @@ block1:
 block2:
  br label %block4
 ; CHECK: block2:
-; CHECK:   load i32*
+; CHECK:   load i32, i32*
 ; CHECK:   br label %block4
 
 block3:
-  %B = getelementptr i32* %q, i32 1
+  %B = getelementptr i32, i32* %q, i32 1
   store i32* %B, i32** %Hack
 
-  %A = getelementptr i32* %p, i32 1
+  %A = getelementptr i32, i32* %p, i32 1
   store i32 0, i32* %A
   br label %block4
 
 block4:
   %P2 = phi i32* [%p, %block3], [%q, %block2]
-  %P3 = getelementptr i32* %P2, i32 1
-  %PRE = load i32* %P3
+  %P3 = getelementptr i32, i32* %P2, i32 1
+  %PRE = load i32, i32* %P3
   ret i32 %PRE
 ; CHECK: block4:
 ; CHECK-NEXT: phi i32 [
@@ -127,16 +127,16 @@ bb.nph:
   br label %bb
 
 ; CHECK: bb.nph:
-; CHECK: load double*
+; CHECK: load double, double*
 ; CHECK: br label %bb
 
 bb:             
   %indvar = phi i64 [ 0, %bb.nph ], [ %tmp6, %bb ]
   %tmp6 = add i64 %indvar, 1                    
-  %scevgep = getelementptr double* %G, i64 %tmp6
-  %scevgep7 = getelementptr double* %G, i64 %indvar
-  %2 = load double* %scevgep7, align 8
-  %3 = load double* %scevgep, align 8 
+  %scevgep = getelementptr double, double* %G, i64 %tmp6
+  %scevgep7 = getelementptr double, double* %G, i64 %indvar
+  %2 = load double, double* %scevgep7, align 8
+  %3 = load double, double* %scevgep, align 8 
   %4 = fadd double %2, %3             
   store double %4, double* %scevgep7, align 8
   %exitcond = icmp eq i64 %tmp6, %tmp 
@@ -144,8 +144,8 @@ bb:
 
 ; Should only be one load in the loop.
 ; CHECK: bb:
-; CHECK: load double*
-; CHECK-NOT: load double*
+; CHECK: load double, double*
+; CHECK-NOT: load double, double*
 ; CHECK: br i1 %exitcond
 
 return:                               
@@ -170,16 +170,16 @@ bb.nph:
   br label %bb
 
 ; CHECK: bb.nph:
-; CHECK: load double*
+; CHECK: load double, double*
 ; CHECK: br label %bb
 
 bb:             
   %indvar = phi i64 [ 0, %bb.nph ], [ %tmp6, %bb ]
   %tmp6 = add i64 %indvar, 1                    
-  %scevgep = getelementptr double* %G, i64 %tmp6
-  %scevgep7 = getelementptr double* %G, i64 %indvar
-  %2 = load double* %scevgep7, align 8
-  %3 = load double* %scevgep, align 8 
+  %scevgep = getelementptr double, double* %G, i64 %tmp6
+  %scevgep7 = getelementptr double, double* %G, i64 %indvar
+  %2 = load double, double* %scevgep7, align 8
+  %3 = load double, double* %scevgep, align 8 
   %4 = fadd double %2, %3             
   store double %4, double* %scevgep, align 8
   %exitcond = icmp eq i64 %tmp6, %tmp 
@@ -187,8 +187,8 @@ bb:
 
 ; Should only be one load in the loop.
 ; CHECK: bb:
-; CHECK: load double*
-; CHECK-NOT: load double*
+; CHECK: load double, double*
+; CHECK-NOT: load double, double*
 ; CHECK: br i1 %exitcond
 
 return:                               
@@ -205,7 +205,7 @@ return:
 ; This requires phi translation of the adds.
 define void @test7(i32 %N, double* nocapture %G) nounwind ssp {
 entry:
-  %0 = getelementptr inbounds double* %G, i64 1   
+  %0 = getelementptr inbounds double, double* %G, i64 1   
   store double 1.000000e+00, double* %0, align 8
   %1 = add i32 %N, -1                             
   %2 = icmp sgt i32 %1, 1                         
@@ -219,11 +219,11 @@ bb.nph:
 bb:                                               
   %indvar = phi i64 [ 0, %bb.nph ], [ %tmp9, %bb ] 
   %tmp8 = add i64 %indvar, 2                      
-  %scevgep = getelementptr double* %G, i64 %tmp8  
+  %scevgep = getelementptr double, double* %G, i64 %tmp8  
   %tmp9 = add i64 %indvar, 1                      
-  %scevgep10 = getelementptr double* %G, i64 %tmp9 
-  %3 = load double* %scevgep10, align 8           
-  %4 = load double* %scevgep, align 8             
+  %scevgep10 = getelementptr double, double* %G, i64 %tmp9 
+  %3 = load double, double* %scevgep10, align 8           
+  %4 = load double, double* %scevgep, align 8             
   %5 = fadd double %3, %4                         
   store double %5, double* %scevgep, align 8
   %exitcond = icmp eq i64 %tmp9, %tmp7            
@@ -231,8 +231,8 @@ bb:
 
 ; Should only be one load in the loop.
 ; CHECK: bb:
-; CHECK: load double*
-; CHECK-NOT: load double*
+; CHECK: load double, double*
+; CHECK-NOT: load double, double*
 ; CHECK: br i1 %exitcond
 
 return:                                           
@@ -249,18 +249,18 @@ block1:
 block2:
  br label %block4
 ; CHECK: block2:
-; CHECK:   load i32*
+; CHECK:   load i32, i32*
 ; CHECK:   br label %block4
 
 block3:
-  %A = getelementptr i32* %p, i32 1
+  %A = getelementptr i32, i32* %p, i32 1
   store i32 0, i32* %A
   br label %block4
 
 block4:
   %P2 = phi i32* [%p, %block3], [%q, %block2]
-  %P3 = getelementptr i32* %P2, i32 1
-  %PRE = load i32* %P3
+  %P3 = getelementptr i32, i32* %P2, i32 1
+  %PRE = load i32, i32* %P3
   ret i32 %PRE
 ; CHECK: block4:
 ; CHECK-NEXT: phi i32 [
@@ -288,17 +288,17 @@ bb.nph:
   br label %bb
 
 ; CHECK: bb.nph:
-; CHECK:   load double*
+; CHECK:   load double, double*
 ; CHECK:   br label %bb
 
 bb:                                               
   %indvar = phi i64 [ 0, %bb.nph ], [ %tmp9, %bb ] 
   %tmp8 = add i64 %indvar, 2                      
-  %scevgep = getelementptr double* %G, i64 %tmp8  
+  %scevgep = getelementptr double, double* %G, i64 %tmp8  
   %tmp9 = add i64 %indvar, 1                      
-  %scevgep10 = getelementptr double* %G, i64 %tmp9 
-  %3 = load double* %scevgep10, align 8           
-  %4 = load double* %scevgep, align 8             
+  %scevgep10 = getelementptr double, double* %G, i64 %tmp9 
+  %3 = load double, double* %scevgep10, align 8           
+  %4 = load double, double* %scevgep, align 8             
   %5 = fadd double %3, %4                         
   store double %5, double* %scevgep, align 8
   %exitcond = icmp eq i64 %tmp9, %tmp7            
@@ -306,8 +306,8 @@ bb:
 
 ; Should only be one load in the loop.
 ; CHECK: bb:
-; CHECK: load double*
-; CHECK-NOT: load double*
+; CHECK: load double, double*
+; CHECK-NOT: load double, double*
 ; CHECK: br i1 %exitcond
 
 return:                                           
@@ -332,22 +332,22 @@ bb.nph:
   %tmp8 = add i64 %tmp, -1
   br label %bb
 ; CHECK: bb.nph:
-; CHECK:   load double*
-; CHECK:   load double*
+; CHECK:   load double, double*
+; CHECK:   load double, double*
 ; CHECK:   br label %bb
 
 
 bb:
   %indvar = phi i64 [ 0, %bb.nph ], [ %tmp11, %bb ]
-  %scevgep = getelementptr double* %G, i64 %indvar
+  %scevgep = getelementptr double, double* %G, i64 %indvar
   %tmp9 = add i64 %indvar, 2
-  %scevgep10 = getelementptr double* %G, i64 %tmp9
+  %scevgep10 = getelementptr double, double* %G, i64 %tmp9
   %tmp11 = add i64 %indvar, 1
-  %scevgep12 = getelementptr double* %G, i64 %tmp11
-  %2 = load double* %scevgep12, align 8
-  %3 = load double* %scevgep10, align 8
+  %scevgep12 = getelementptr double, double* %G, i64 %tmp11
+  %2 = load double, double* %scevgep12, align 8
+  %3 = load double, double* %scevgep10, align 8
   %4 = fadd double %2, %3
-  %5 = load double* %scevgep, align 8
+  %5 = load double, double* %scevgep, align 8
   %6 = fadd double %4, %5
   store double %6, double* %scevgep12, align 8
   %exitcond = icmp eq i64 %tmp11, %tmp8
@@ -355,8 +355,8 @@ bb:
 
 ; Should only be one load in the loop.
 ; CHECK: bb:
-; CHECK: load double*
-; CHECK-NOT: load double*
+; CHECK: load double, double*
+; CHECK-NOT: load double, double*
 ; CHECK: br i1 %exitcond
 
 return:
@@ -372,7 +372,7 @@ block1:
 block2:
  %cond = icmp sgt i32 %N, 1
  br i1 %cond, label %block4, label %block5
-; CHECK: load i32* %p
+; CHECK: load i32, i32* %p
 ; CHECK-NEXT: br label %block4
 
 block3:
@@ -380,7 +380,7 @@ block3:
   br label %block4
 
 block4:
-  %PRE = load i32* %p
+  %PRE = load i32, i32* %p
   br label %block5
 
 block5:
diff --git a/test/Transforms/GVN/pre-no-cost-phi.ll b/test/Transforms/GVN/pre-no-cost-phi.ll
new file mode 100644
index 000000000000..4c5afa12ddc1
--- /dev/null
+++ b/test/Transforms/GVN/pre-no-cost-phi.ll
@@ -0,0 +1,31 @@
+; RUN: opt < %s -gvn -S | FileCheck %s
+; This testcase tests insertion of no-cost phis.  That is,
+; when the value is already available in every predecessor,
+; and we just need to insert a phi node to merge the available values.
+
+@c = global i32 0, align 4
+@d = global i32 0, align 4
+
+
+define i32 @mai(i32 %foo, i32 %a, i32 %b) {
+  %1 = icmp ne i32 %foo, 0
+  br i1 %1, label %bb1, label %bb2
+
+bb1:
+  %2 = add nsw i32 %a, %b
+  store i32 %2, i32* @c, align 4
+  br label %mergeblock
+
+bb2:
+  %3 = add nsw i32 %a, %b
+  store i32 %3, i32* @d, align 4
+  br label %mergeblock
+
+mergeblock:
+; CHECK: pre-phi = phi i32 [ %3, %bb2 ], [ %2, %bb1 ]
+; CHECK-NEXT: ret i32 %.pre-phi
+  %4 = add nsw i32 %a, %b
+  ret i32 %4
+}
+
+
diff --git a/test/Transforms/GVN/pre-single-pred.ll b/test/Transforms/GVN/pre-single-pred.ll
index f1f5c71a93ab..0df45cf5c1c0 100644
--- a/test/Transforms/GVN/pre-single-pred.ll
+++ b/test/Transforms/GVN/pre-single-pred.ll
@@ -23,9 +23,9 @@ for.cond.for.end_crit_edge:		; preds = %for.cond
 	br label %for.end
 
 ; CHECK: for.body:
-; CHECK-NEXT: %tmp3 = load i32* @p
+; CHECK-NEXT: %tmp3 = load i32, i32* @p
 for.body:		; preds = %for.cond
-	%tmp3 = load i32* @p		; <i32> [#uses=1]
+	%tmp3 = load i32, i32* @p		; <i32> [#uses=1]
 	%dec = add i32 %tmp3, -1		; <i32> [#uses=2]
 	store i32 %dec, i32* @p
 	%cmp6 = icmp slt i32 %dec, 0		; <i1> [#uses=1]
@@ -40,6 +40,6 @@ for.inc:		; preds = %for.body
 	br label %for.cond
 
 for.end:		; preds = %for.body.for.end_crit_edge, %for.cond.for.end_crit_edge
-	%tmp9 = load i32* @p		; <i32> [#uses=1]
+	%tmp9 = load i32, i32* @p		; <i32> [#uses=1]
 	ret i32 %tmp9
 }
diff --git a/test/Transforms/GVN/preserve-tbaa.ll b/test/Transforms/GVN/preserve-tbaa.ll
index 587d463eef27..19467eeff404 100644
--- a/test/Transforms/GVN/preserve-tbaa.ll
+++ b/test/Transforms/GVN/preserve-tbaa.ll
@@ -5,7 +5,7 @@ target datalayout = "e-p:64:64:64"
 ; GVN should preserve the TBAA tag on loads when doing PRE.
 
 ; CHECK-LABEL: @test(
-; CHECK: %tmp33.pre = load i16* %P, align 2, !tbaa !0
+; CHECK: %tmp33.pre = load i16, i16* %P, align 2, !tbaa !0
 ; CHECK: br label %for.body
 define void @test(i16 *%P, i16* %Q) nounwind {
 entry:
@@ -15,7 +15,7 @@ bb.nph:                                           ; preds = %entry
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %bb.nph
-  %tmp33 = load i16* %P, align 2, !tbaa !0
+  %tmp33 = load i16, i16* %P, align 2, !tbaa !0
   store i16 %tmp33, i16* %Q
 
   store i16 0, i16* %P, align 2, !tbaa !0
diff --git a/test/Transforms/GVN/range.ll b/test/Transforms/GVN/range.ll
index 37202321a6dc..297c6aac88dd 100644
--- a/test/Transforms/GVN/range.ll
+++ b/test/Transforms/GVN/range.ll
@@ -2,82 +2,82 @@
 
 define i32 @test1(i32* %p) {
 ; CHECK: @test1(i32* %p)
-; CHECK: %a = load i32* %p, !range !0
+; CHECK: %a = load i32, i32* %p, !range !0
 ; CHECK: %c = add i32 %a, %a
-  %a = load i32* %p, !range !0
-  %b = load i32* %p, !range !0
+  %a = load i32, i32* %p, !range !0
+  %b = load i32, i32* %p, !range !0
   %c = add i32 %a, %b
   ret i32 %c
 }
 
 define i32 @test2(i32* %p) {
 ; CHECK: @test2(i32* %p)
-; CHECK: %a = load i32* %p
+; CHECK: %a = load i32, i32* %p
 ; CHECK-NOT: range
 ; CHECK: %c = add i32 %a, %a
-  %a = load i32* %p, !range !0
-  %b = load i32* %p
+  %a = load i32, i32* %p, !range !0
+  %b = load i32, i32* %p
   %c = add i32 %a, %b
   ret i32 %c
 }
 
 define i32 @test3(i32* %p) {
 ; CHECK: @test3(i32* %p)
-; CHECK: %a = load i32* %p, !range ![[DISJOINT_RANGE:[0-9]+]]
+; CHECK: %a = load i32, i32* %p, !range ![[DISJOINT_RANGE:[0-9]+]]
 ; CHECK: %c = add i32 %a, %a
-  %a = load i32* %p, !range !0
-  %b = load i32* %p, !range !1
+  %a = load i32, i32* %p, !range !0
+  %b = load i32, i32* %p, !range !1
   %c = add i32 %a, %b
   ret i32 %c
 }
 
 define i32 @test4(i32* %p) {
 ; CHECK: @test4(i32* %p)
-; CHECK: %a = load i32* %p, !range ![[MERGED_RANGE:[0-9]+]]
+; CHECK: %a = load i32, i32* %p, !range ![[MERGED_RANGE:[0-9]+]]
 ; CHECK: %c = add i32 %a, %a
-  %a = load i32* %p, !range !0
-  %b = load i32* %p, !range !2
+  %a = load i32, i32* %p, !range !0
+  %b = load i32, i32* %p, !range !2
   %c = add i32 %a, %b
   ret i32 %c
 }
 
 define i32 @test5(i32* %p) {
 ; CHECK: @test5(i32* %p)
-; CHECK: %a = load i32* %p, !range ![[MERGED_SIGNED_RANGE:[0-9]+]]
+; CHECK: %a = load i32, i32* %p, !range ![[MERGED_SIGNED_RANGE:[0-9]+]]
 ; CHECK: %c = add i32 %a, %a
-  %a = load i32* %p, !range !3
-  %b = load i32* %p, !range !4
+  %a = load i32, i32* %p, !range !3
+  %b = load i32, i32* %p, !range !4
   %c = add i32 %a, %b
   ret i32 %c
 }
 
 define i32 @test6(i32* %p) {
 ; CHECK: @test6(i32* %p)
-; CHECK: %a = load i32* %p, !range ![[MERGED_TEST6:[0-9]+]]
+; CHECK: %a = load i32, i32* %p, !range ![[MERGED_TEST6:[0-9]+]]
 ; CHECK: %c = add i32 %a, %a
-  %a = load i32* %p, !range !5
-  %b = load i32* %p, !range !6
+  %a = load i32, i32* %p, !range !5
+  %b = load i32, i32* %p, !range !6
   %c = add i32 %a, %b
   ret i32 %c
 }
 
 define i32 @test7(i32* %p) {
 ; CHECK: @test7(i32* %p)
-; CHECK: %a = load i32* %p, !range ![[MERGED_TEST7:[0-9]+]]
+; CHECK: %a = load i32, i32* %p, !range ![[MERGED_TEST7:[0-9]+]]
 ; CHECK: %c = add i32 %a, %a
-  %a = load i32* %p, !range !7
-  %b = load i32* %p, !range !8
+  %a = load i32, i32* %p, !range !7
+  %b = load i32, i32* %p, !range !8
   %c = add i32 %a, %b
   ret i32 %c
 }
 
 define i32 @test8(i32* %p) {
 ; CHECK: @test8(i32* %p)
-; CHECK: %a = load i32* %p
+; CHECK: %a = load i32, i32* %p
 ; CHECK-NOT: range
 ; CHECK: %c = add i32 %a, %a
-  %a = load i32* %p, !range !9
-  %b = load i32* %p, !range !10
+  %a = load i32, i32* %p, !range !9
+  %b = load i32, i32* %p, !range !10
   %c = add i32 %a, %b
   ret i32 %c
 }
diff --git a/test/Transforms/GVN/readattrs.ll b/test/Transforms/GVN/readattrs.ll
index ba624a71f9b6..fb36d07c86e6 100644
--- a/test/Transforms/GVN/readattrs.ll
+++ b/test/Transforms/GVN/readattrs.ll
@@ -9,7 +9,7 @@ define i8 @test() {
   %a = alloca i8
   store i8 1, i8* %a
   call void @use(i8* %a)
-  %b = load i8* %a
+  %b = load i8, i8* %a
   ret i8 %b
 ; CHECK-LABEL: define i8 @test(
 ; CHECK: call void @use(i8* %a)
diff --git a/test/Transforms/GVN/rle-must-alias.ll b/test/Transforms/GVN/rle-must-alias.ll
index e7dc9c423fcb..bf8b139a2e86 100644
--- a/test/Transforms/GVN/rle-must-alias.ll
+++ b/test/Transforms/GVN/rle-must-alias.ll
@@ -11,28 +11,28 @@ target triple = "i386-apple-darwin7"
 
 define i32 @test(i32 %i) nounwind {
 entry:
-	%0 = tail call i32 (...)* @foo() nounwind		; <i32> [#uses=1]
+	%0 = tail call i32 (...) @foo() nounwind		; <i32> [#uses=1]
 	%1 = icmp eq i32 %0, 0		; <i1> [#uses=1]
 	br i1 %1, label %bb1, label %bb
 
 bb:		; preds = %entry
-	%2 = tail call i32 (...)* @bar() nounwind		; <i32> [#uses=0]
-	%3 = getelementptr [100 x i32]* @H, i32 0, i32 %i		; <i32*> [#uses=1]
-	%4 = load i32* %3, align 4		; <i32> [#uses=1]
+	%2 = tail call i32 (...) @bar() nounwind		; <i32> [#uses=0]
+	%3 = getelementptr [100 x i32], [100 x i32]* @H, i32 0, i32 %i		; <i32*> [#uses=1]
+	%4 = load i32, i32* %3, align 4		; <i32> [#uses=1]
 	store i32 %4, i32* @G, align 4
 	br label %bb3
 
 bb1:		; preds = %entry
-	%5 = tail call i32 (...)* @baz() nounwind		; <i32> [#uses=0]
-	%6 = getelementptr [100 x i32]* @H, i32 0, i32 %i		; <i32*> [#uses=1]
-	%7 = load i32* %6, align 4		; <i32> [#uses=2]
+	%5 = tail call i32 (...) @baz() nounwind		; <i32> [#uses=0]
+	%6 = getelementptr [100 x i32], [100 x i32]* @H, i32 0, i32 %i		; <i32*> [#uses=1]
+	%7 = load i32, i32* %6, align 4		; <i32> [#uses=2]
 	store i32 %7, i32* @G, align 4
 	%8 = icmp eq i32 %7, 0		; <i1> [#uses=1]
 	br i1 %8, label %bb3, label %bb4
 
 bb3:		; preds = %bb1, %bb
-	%9 = getelementptr [100 x i32]* @H, i32 0, i32 %i		; <i32*> [#uses=1]
-	%DEAD = load i32* %9, align 4		; <i32> [#uses=1]
+	%9 = getelementptr [100 x i32], [100 x i32]* @H, i32 0, i32 %i		; <i32*> [#uses=1]
+	%DEAD = load i32, i32* %9, align 4		; <i32> [#uses=1]
 	ret i32 %DEAD
 
 bb4:		; preds = %bb1
diff --git a/test/Transforms/GVN/rle-no-phi-translate.ll b/test/Transforms/GVN/rle-no-phi-translate.ll
index 96dbf481899c..c1fd20115379 100644
--- a/test/Transforms/GVN/rle-no-phi-translate.ll
+++ b/test/Transforms/GVN/rle-no-phi-translate.ll
@@ -19,7 +19,7 @@ bb:		; preds = %entry
 
 bb2:		; preds = %bb1, %bb
 	%c_addr.0 = phi i32* [ %b, %entry ], [ %c, %bb ]		; <i32*> [#uses=1]
-	%cv = load i32* %c_addr.0, align 4		; <i32> [#uses=1]
+	%cv = load i32, i32* %c_addr.0, align 4		; <i32> [#uses=1]
 	ret i32 %cv
 ; CHECK: bb2:
 ; CHECK-NOT: load i32
diff --git a/test/Transforms/GVN/rle-nonlocal.ll b/test/Transforms/GVN/rle-nonlocal.ll
index 8229aaa14247..7975462313c0 100644
--- a/test/Transforms/GVN/rle-nonlocal.ll
+++ b/test/Transforms/GVN/rle-nonlocal.ll
@@ -6,20 +6,20 @@ block1:
 	br i1 %cmp , label %block2, label %block3
 
 block2:
- %a = load i32** %p
+ %a = load i32*, i32** %p
  br label %block4
 
 block3:
-  %b = load i32** %p
+  %b = load i32*, i32** %p
   br label %block4
 
 block4:
 ; CHECK-NOT: %existingPHI = phi
 ; CHECK: %DEAD = phi
   %existingPHI = phi i32* [ %a, %block2 ], [ %b, %block3 ] 
-  %DEAD = load i32** %p
-  %c = load i32* %DEAD
-  %d = load i32* %existingPHI
+  %DEAD = load i32*, i32** %p
+  %c = load i32, i32* %DEAD
+  %d = load i32, i32* %existingPHI
   %e = add i32 %c, %d
   ret i32 %e
 }
diff --git a/test/Transforms/GVN/rle-phi-translate.ll b/test/Transforms/GVN/rle-phi-translate.ll
index 1ce7e0b93797..7402e1a1fc00 100644
--- a/test/Transforms/GVN/rle-phi-translate.ll
+++ b/test/Transforms/GVN/rle-phi-translate.ll
@@ -11,13 +11,13 @@ entry:
 	br i1 %t1, label %bb, label %bb1
 
 bb:
-	%t2 = load i32* %c, align 4
+	%t2 = load i32, i32* %c, align 4
 	%t3 = add i32 %t2, 1
 	store i32 %t3, i32* %g, align 4
 	br label %bb2
 
 bb1:		; preds = %entry
-	%t5 = load i32* %b, align 4
+	%t5 = load i32, i32* %b, align 4
 	%t6 = add i32 %t5, 1
 	store i32 %t6, i32* %g, align 4
 	br label %bb2
@@ -25,8 +25,8 @@ bb1:		; preds = %entry
 bb2:		; preds = %bb1, %bb
 	%c_addr.0 = phi i32* [ %g, %bb1 ], [ %c, %bb ]
 	%b_addr.0 = phi i32* [ %b, %bb1 ], [ %g, %bb ]
-	%cv = load i32* %c_addr.0, align 4
-	%bv = load i32* %b_addr.0, align 4
+	%cv = load i32, i32* %c_addr.0, align 4
+	%bv = load i32, i32* %b_addr.0, align 4
 ; CHECK: %bv = phi i32
 ; CHECK: %cv = phi i32
 ; CHECK-NOT: load
@@ -53,7 +53,7 @@ bb1:
 bb2:
   %d = phi i32* [ %c, %bb1 ], [ %b, %bb ]
   %d1 = bitcast i32* %d to i8*
-  %dv = load i8* %d1
+  %dv = load i8, i8* %d1
 ; CHECK: %dv = phi i8 [ 92, %bb1 ], [ 4, %bb ]
 ; CHECK-NOT: load
 ; CHECK: ret i8 %dv
@@ -66,20 +66,20 @@ entry:
   br i1 %cond, label %bb, label %bb1
 
 bb:
-  %b1 = getelementptr i32* %b, i32 17
+  %b1 = getelementptr i32, i32* %b, i32 17
   store i32 4, i32* %b1
   br label %bb2
 
 bb1:
-  %c1 = getelementptr i32* %c, i32 7
+  %c1 = getelementptr i32, i32* %c, i32 7
   store i32 82, i32* %c1
   br label %bb2
 
 bb2:
   %d = phi i32* [ %c, %bb1 ], [ %b, %bb ]
   %i = phi i32 [ 7, %bb1 ], [ 17, %bb ]
-  %d1 = getelementptr i32* %d, i32 %i
-  %dv = load i32* %d1
+  %d1 = getelementptr i32, i32* %d, i32 %i
+  %dv = load i32, i32* %d1
 ; CHECK: %dv = phi i32 [ 82, %bb1 ], [ 4, %bb ]
 ; CHECK-NOT: load
 ; CHECK: ret i32 %dv
@@ -97,15 +97,15 @@ bb:
   br label %bb2
 
 bb1:
-  %c1 = getelementptr i32* %c, i32 7
+  %c1 = getelementptr i32, i32* %c, i32 7
   store i32 82, i32* %c1
   br label %bb2
 
 bb2:
   %d = phi i32* [ %c, %bb1 ], [ %b, %bb ]
   %i = phi i32 [ 7, %bb1 ], [ 0, %bb ]
-  %d1 = getelementptr i32* %d, i32 %i
-  %dv = load i32* %d1
+  %d1 = getelementptr i32, i32* %d, i32 %i
+  %dv = load i32, i32* %d1
 ; CHECK: %dv = phi i32 [ 82, %bb1 ], [ 4, %bb ]
 ; CHECK-NOT: load
 ; CHECK: ret i32 %dv
@@ -127,11 +127,11 @@ bb.nph:
 
 for.body:
   %indvar = phi i64 [ 0, %bb.nph ], [ %tmp, %for.body ]
-  %arrayidx6 = getelementptr double* %G, i64 %indvar
+  %arrayidx6 = getelementptr double, double* %G, i64 %indvar
   %tmp = add i64 %indvar, 1
-  %arrayidx = getelementptr double* %G, i64 %tmp
-  %tmp3 = load double* %arrayidx
-  %tmp7 = load double* %arrayidx6
+  %arrayidx = getelementptr double, double* %G, i64 %tmp
+  %tmp3 = load double, double* %arrayidx
+  %tmp7 = load double, double* %arrayidx6
   %add = fadd double %tmp3, %tmp7
   store double %add, double* %arrayidx
   %exitcond = icmp eq i64 %tmp, 999
diff --git a/test/Transforms/GVN/rle-semidominated.ll b/test/Transforms/GVN/rle-semidominated.ll
index 923cd03ecdb7..f80d040c93eb 100644
--- a/test/Transforms/GVN/rle-semidominated.ll
+++ b/test/Transforms/GVN/rle-semidominated.ll
@@ -2,7 +2,7 @@
 
 define i32 @main(i32* %p, i32 %x, i32 %y) {
 block1:
-  %z = load i32* %p
+  %z = load i32, i32* %p
   %cmp = icmp eq i32 %x, %y
 	br i1 %cmp, label %block2, label %block3
 
@@ -15,6 +15,6 @@ block3:
   br label %block4
 
 block4:
-  %DEAD = load i32* %p
+  %DEAD = load i32, i32* %p
   ret i32 %DEAD
 }
diff --git a/test/Transforms/GVN/rle.ll b/test/Transforms/GVN/rle.ll
index 6aac93e75a78..3f42135b4092 100644
--- a/test/Transforms/GVN/rle.ll
+++ b/test/Transforms/GVN/rle.ll
@@ -5,7 +5,7 @@
 define i32 @test0(i32 %V, i32* %P) {
   store i32 %V, i32* %P
 
-  %A = load i32* %P
+  %A = load i32, i32* %P
   ret i32 %A
 ; CHECK-LABEL: @test0(
 ; CHECK: ret i32 %V
@@ -20,7 +20,7 @@ define i32 @test0(i32 %V, i32* %P) {
 define i8 @crash0({i32, i32} %A, {i32, i32}* %P) {
   store {i32, i32} %A, {i32, i32}* %P
   %X = bitcast {i32, i32}* %P to i8*
-  %Y = load i8* %X
+  %Y = load i8, i8* %X
   ret i8 %Y
 }
 
@@ -28,7 +28,7 @@ define i8 @crash0({i32, i32} %A, {i32, i32}* %P) {
 declare void @helper()
 define void @crash1() {
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* undef, i64 undef, i32 1, i1 false) nounwind
-  %tmp = load i8* bitcast (void ()* @helper to i8*)
+  %tmp = load i8, i8* bitcast (void ()* @helper to i8*)
   %x = icmp eq i8 %tmp, 15
   ret void
 }
@@ -45,7 +45,7 @@ define float @coerce_mustalias1(i32 %V, i32* %P) {
    
   %P2 = bitcast i32* %P to float*
 
-  %A = load float* %P2
+  %A = load float, float* %P2
   ret float %A
 ; CHECK-LABEL: @coerce_mustalias1(
 ; CHECK-NOT: load
@@ -58,7 +58,7 @@ define float @coerce_mustalias2(i32* %V, i32** %P) {
    
   %P2 = bitcast i32** %P to float*
 
-  %A = load float* %P2
+  %A = load float, float* %P2
   ret float %A
 ; CHECK-LABEL: @coerce_mustalias2(
 ; CHECK-NOT: load
@@ -71,7 +71,7 @@ define i32* @coerce_mustalias3(float %V, float* %P) {
    
   %P2 = bitcast float* %P to i32**
 
-  %A = load i32** %P2
+  %A = load i32*, i32** %P2
   ret i32* %A
 ; CHECK-LABEL: @coerce_mustalias3(
 ; CHECK-NOT: load
@@ -80,10 +80,10 @@ define i32* @coerce_mustalias3(float %V, float* %P) {
 
 ;; i32 -> f32 load forwarding.
 define float @coerce_mustalias4(i32* %P, i1 %cond) {
-  %A = load i32* %P
+  %A = load i32, i32* %P
   
   %P2 = bitcast i32* %P to float*
-  %B = load float* %P2
+  %B = load float, float* %P2
   br i1 %cond, label %T, label %F
 T:
   ret float %B
@@ -93,7 +93,7 @@ F:
   ret float %X
 
 ; CHECK-LABEL: @coerce_mustalias4(
-; CHECK: %A = load i32* %P
+; CHECK: %A = load i32, i32* %P
 ; CHECK-NOT: load
 ; CHECK: ret float
 ; CHECK: F:
@@ -105,7 +105,7 @@ define i8 @coerce_mustalias5(i32 %V, i32* %P) {
    
   %P2 = bitcast i32* %P to i8*
 
-  %A = load i8* %P2
+  %A = load i8, i8* %P2
   ret i8 %A
 ; CHECK-LABEL: @coerce_mustalias5(
 ; CHECK-NOT: load
@@ -118,7 +118,7 @@ define float @coerce_mustalias6(i64 %V, i64* %P) {
    
   %P2 = bitcast i64* %P to float*
 
-  %A = load float* %P2
+  %A = load float, float* %P2
   ret float %A
 ; CHECK-LABEL: @coerce_mustalias6(
 ; CHECK-NOT: load
@@ -131,7 +131,7 @@ define i8* @coerce_mustalias7(i64 %V, i64* %P) {
    
   %P2 = bitcast i64* %P to i8**
 
-  %A = load i8** %P2
+  %A = load i8*, i8** %P2
   ret i8* %A
 ; CHECK-LABEL: @coerce_mustalias7(
 ; CHECK-NOT: load
@@ -143,8 +143,8 @@ define signext i16 @memset_to_i16_local(i16* %A) nounwind ssp {
 entry:
   %conv = bitcast i16* %A to i8* 
   tail call void @llvm.memset.p0i8.i64(i8* %conv, i8 1, i64 200, i32 1, i1 false)
-  %arrayidx = getelementptr inbounds i16* %A, i64 42
-  %tmp2 = load i16* %arrayidx
+  %arrayidx = getelementptr inbounds i16, i16* %A, i64 42
+  %tmp2 = load i16, i16* %arrayidx
   ret i16 %tmp2
 ; CHECK-LABEL: @memset_to_i16_local(
 ; CHECK-NOT: load
@@ -156,8 +156,8 @@ define float @memset_to_float_local(float* %A, i8 %Val) nounwind ssp {
 entry:
   %conv = bitcast float* %A to i8*                ; <i8*> [#uses=1]
   tail call void @llvm.memset.p0i8.i64(i8* %conv, i8 %Val, i64 400, i32 1, i1 false)
-  %arrayidx = getelementptr inbounds float* %A, i64 42 ; <float*> [#uses=1]
-  %tmp2 = load float* %arrayidx                   ; <float> [#uses=1]
+  %arrayidx = getelementptr inbounds float, float* %A, i64 42 ; <float*> [#uses=1]
+  %tmp2 = load float, float* %arrayidx                   ; <float> [#uses=1]
   ret float %tmp2
 ; CHECK-LABEL: @memset_to_float_local(
 ; CHECK-NOT: load
@@ -183,8 +183,8 @@ F:
   br label %Cont
 
 Cont:
-  %P2 = getelementptr i16* %P, i32 4
-  %A = load i16* %P2
+  %P2 = getelementptr i16, i16* %P, i32 4
+  %A = load i16, i16* %P2
   ret i16 %A
 
 ; CHECK-LABEL: @memset_to_i16_nonlocal0(
@@ -202,8 +202,8 @@ define float @memcpy_to_float_local(float* %A) nounwind ssp {
 entry:
   %conv = bitcast float* %A to i8*                ; <i8*> [#uses=1]
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %conv, i8* bitcast ({i32, float, i32 }* @GCst to i8*), i64 12, i32 1, i1 false)
-  %arrayidx = getelementptr inbounds float* %A, i64 1 ; <float*> [#uses=1]
-  %tmp2 = load float* %arrayidx                   ; <float> [#uses=1]
+  %arrayidx = getelementptr inbounds float, float* %A, i64 1 ; <float*> [#uses=1]
+  %tmp2 = load float, float* %arrayidx                   ; <float> [#uses=1]
   ret float %tmp2
 ; CHECK-LABEL: @memcpy_to_float_local(
 ; CHECK-NOT: load
@@ -215,8 +215,8 @@ define float @memcpy_to_float_local_as1(float* %A) nounwind ssp {
 entry:
   %conv = bitcast float* %A to i8*                ; <i8*> [#uses=1]
   tail call void @llvm.memcpy.p0i8.p1i8.i64(i8* %conv, i8 addrspace(1)* bitcast ({i32, float, i32 } addrspace(1)* @GCst_as1 to i8 addrspace(1)*), i64 12, i32 1, i1 false)
-  %arrayidx = getelementptr inbounds float* %A, i64 1 ; <float*> [#uses=1]
-  %tmp2 = load float* %arrayidx                   ; <float> [#uses=1]
+  %arrayidx = getelementptr inbounds float, float* %A, i64 1 ; <float*> [#uses=1]
+  %tmp2 = load float, float* %arrayidx                   ; <float> [#uses=1]
   ret float %tmp2
 ; CHECK-LABEL: @memcpy_to_float_local_as1(
 ; CHECK-NOT: load
@@ -237,7 +237,7 @@ F:
   br label %Cont
 
 Cont:
-  %A = load i8* %P3
+  %A = load i8, i8* %P3
   ret i8 %A
 
 ; CHECK-LABEL: @coerce_mustalias_nonlocal0(
@@ -263,7 +263,7 @@ F:
 
 Cont:
   %P3 = bitcast i32* %P to i8*
-  %A = load i8* %P3
+  %A = load i8, i8* %P3
   ret i8 %A
 
 ; CHECK-LABEL: @coerce_mustalias_nonlocal1(
@@ -286,12 +286,12 @@ F:
   br label %Cont
 
 Cont:
-  %A = load i8* %P3
+  %A = load i8, i8* %P3
   ret i8 %A
 
 ; CHECK-LABEL: @coerce_mustalias_pre0(
 ; CHECK: F:
-; CHECK:   load i8* %P3
+; CHECK:   load i8, i8* %P3
 ; CHECK: Cont:
 ; CHECK:   %A = phi i8 [
 ; CHECK-NOT: load
@@ -309,9 +309,9 @@ define i8 @coerce_offset0(i32 %V, i32* %P) {
   store i32 %V, i32* %P
    
   %P2 = bitcast i32* %P to i8*
-  %P3 = getelementptr i8* %P2, i32 2
+  %P3 = getelementptr i8, i8* %P2, i32 2
 
-  %A = load i8* %P3
+  %A = load i8, i8* %P3
   ret i8 %A
 ; CHECK-LABEL: @coerce_offset0(
 ; CHECK-NOT: load
@@ -322,9 +322,9 @@ define i8 @coerce_offset0_addrspacecast(i32 %V, i32* %P) {
   store i32 %V, i32* %P
 
   %P2 = addrspacecast i32* %P to i8 addrspace(1)*
-  %P3 = getelementptr i8 addrspace(1)* %P2, i32 2
+  %P3 = getelementptr i8, i8 addrspace(1)* %P2, i32 2
 
-  %A = load i8 addrspace(1)* %P3
+  %A = load i8, i8 addrspace(1)* %P3
   ret i8 %A
 ; CHECK-LABEL: @coerce_offset0_addrspacecast(
 ; CHECK-NOT: load
@@ -335,7 +335,7 @@ define i8 @coerce_offset0_addrspacecast(i32 %V, i32* %P) {
 define i8 @coerce_offset_nonlocal0(i32* %P, i1 %cond) {
   %P2 = bitcast i32* %P to float*
   %P3 = bitcast i32* %P to i8*
-  %P4 = getelementptr i8* %P3, i32 2
+  %P4 = getelementptr i8, i8* %P3, i32 2
   br i1 %cond, label %T, label %F
 T:
   store i32 57005, i32* %P
@@ -346,7 +346,7 @@ F:
   br label %Cont
 
 Cont:
-  %A = load i8* %P4
+  %A = load i8, i8* %P4
   ret i8 %A
 
 ; CHECK-LABEL: @coerce_offset_nonlocal0(
@@ -360,7 +360,7 @@ Cont:
 ;; non-local i32 -> i8 partial redundancy load forwarding.
 define i8 @coerce_offset_pre0(i32* %P, i1 %cond) {
   %P3 = bitcast i32* %P to i8*
-  %P4 = getelementptr i8* %P3, i32 2
+  %P4 = getelementptr i8, i8* %P3, i32 2
   br i1 %cond, label %T, label %F
 T:
   store i32 42, i32* %P
@@ -370,12 +370,12 @@ F:
   br label %Cont
 
 Cont:
-  %A = load i8* %P4
+  %A = load i8, i8* %P4
   ret i8 %A
 
 ; CHECK-LABEL: @coerce_offset_pre0(
 ; CHECK: F:
-; CHECK:   load i8* %P4
+; CHECK:   load i8, i8* %P4
 ; CHECK: Cont:
 ; CHECK:   %A = phi i8 [
 ; CHECK-NOT: load
@@ -386,28 +386,28 @@ define i32 @chained_load(i32** %p, i32 %x, i32 %y) {
 block1:
   %A = alloca i32*
 
-  %z = load i32** %p
+  %z = load i32*, i32** %p
   store i32* %z, i32** %A
   %cmp = icmp eq i32 %x, %y
   br i1 %cmp, label %block2, label %block3
 
 block2:
- %a = load i32** %p
+ %a = load i32*, i32** %p
  br label %block4
 
 block3:
-  %b = load i32** %p
+  %b = load i32*, i32** %p
   br label %block4
 
 block4:
-  %c = load i32** %p
-  %d = load i32* %c
+  %c = load i32*, i32** %p
+  %d = load i32, i32* %c
   ret i32 %d
   
 ; CHECK-LABEL: @chained_load(
-; CHECK: %z = load i32** %p
+; CHECK: %z = load i32*, i32** %p
 ; CHECK-NOT: load
-; CHECK: %d = load i32* %z
+; CHECK: %d = load i32, i32* %z
 ; CHECK-NEXT: ret i32 %d
 }
 
@@ -427,13 +427,13 @@ F1:
   br i1 %cond2, label %T1, label %TY
   
 T1:
-  %P2 = getelementptr i32* %P, i32 %A
-  %x = load i32* %P2
+  %P2 = getelementptr i32, i32* %P, i32 %A
+  %x = load i32, i32* %P2
   %cond = call i1 @cond2()
   br i1 %cond, label %TX, label %F
   
 F:
-  %P3 = getelementptr i32* %P, i32 2
+  %P3 = getelementptr i32, i32* %P, i32 2
   store i32 17, i32* %P3
   
   store i32 42, i32* %P2  ; Provides "P[A]".
@@ -464,7 +464,7 @@ block2:
  br label %block4
 
 block3:
-  %p2 = getelementptr i32* %p, i32 43
+  %p2 = getelementptr i32, i32* %p, i32 43
   store i32 97, i32* %p2
   br label %block4
 
@@ -481,11 +481,11 @@ block5:
   br i1 %cmpxy, label %block6, label %exit
   
 block6:
-  %C = getelementptr i32* %p, i32 %B
+  %C = getelementptr i32, i32* %p, i32 %B
   br i1 %cmpxy, label %block7, label %exit
   
 block7:
-  %D = load i32* %C
+  %D = load i32, i32* %C
   ret i32 %D
   
 ; CHECK: block7:
@@ -498,17 +498,17 @@ exit:
 define i8 @phi_trans4(i8* %p) {
 ; CHECK-LABEL: @phi_trans4(
 entry:
-  %X3 = getelementptr i8* %p, i32 192
+  %X3 = getelementptr i8, i8* %p, i32 192
   store i8 192, i8* %X3
   
-  %X = getelementptr i8* %p, i32 4
-  %Y = load i8* %X
+  %X = getelementptr i8, i8* %p, i32 4
+  %Y = load i8, i8* %X
   br label %loop
 
 loop:
   %i = phi i32 [4, %entry], [192, %loop]
-  %X2 = getelementptr i8* %p, i32 %i
-  %Y2 = load i8* %X2
+  %X2 = getelementptr i8, i8* %p, i32 %i
+  %Y2 = load i8, i8* %X2
   
 ; CHECK: loop:
 ; CHECK-NEXT: %Y2 = phi i8 [ %Y, %entry ], [ 0, %loop ]
@@ -529,29 +529,29 @@ define i8 @phi_trans5(i8* %p) {
 ; CHECK-LABEL: @phi_trans5(
 entry:
   
-  %X4 = getelementptr i8* %p, i32 2
+  %X4 = getelementptr i8, i8* %p, i32 2
   store i8 19, i8* %X4
   
-  %X = getelementptr i8* %p, i32 4
-  %Y = load i8* %X
+  %X = getelementptr i8, i8* %p, i32 4
+  %Y = load i8, i8* %X
   br label %loop
 
 loop:
   %i = phi i32 [4, %entry], [3, %cont]
-  %X2 = getelementptr i8* %p, i32 %i
-  %Y2 = load i8* %X2  ; Ensure this load is not being incorrectly replaced.
+  %X2 = getelementptr i8, i8* %p, i32 %i
+  %Y2 = load i8, i8* %X2  ; Ensure this load is not being incorrectly replaced.
   %cond = call i1 @cond2()
   br i1 %cond, label %cont, label %out
 
 cont:
-  %Z = getelementptr i8* %X2, i32 -1
+  %Z = getelementptr i8, i8* %X2, i32 -1
   %Z2 = bitcast i8 *%Z to i32*
   store i32 50462976, i32* %Z2  ;; (1 << 8) | (2 << 16) | (3 << 24)
 
 
 ; CHECK: store i32
-; CHECK-NEXT: getelementptr i8* %p, i32 3
-; CHECK-NEXT: load i8*
+; CHECK-NEXT: getelementptr i8, i8* %p, i32 3
+; CHECK-NEXT: load i8, i8*
   br label %loop
   
 out:
@@ -566,8 +566,8 @@ entry:
   %x = alloca [256 x i32], align 4                ; <[256 x i32]*> [#uses=2]
   %tmp = bitcast [256 x i32]* %x to i8*           ; <i8*> [#uses=1]
   call void @llvm.memset.p0i8.i64(i8* %tmp, i8 0, i64 1024, i32 4, i1 false)
-  %arraydecay = getelementptr inbounds [256 x i32]* %x, i32 0, i32 0 ; <i32*>
-  %tmp1 = load i32* %arraydecay                   ; <i32> [#uses=1]
+  %arraydecay = getelementptr inbounds [256 x i32], [256 x i32]* %x, i32 0, i32 0 ; <i32*>
+  %tmp1 = load i32, i32* %arraydecay                   ; <i32> [#uses=1]
   ret i32 %tmp1
 ; CHECK-LABEL: @memset_to_load(
 ; CHECK: ret i32 0
@@ -581,15 +581,15 @@ entry:
 define i32 @load_load_partial_alias(i8* %P) nounwind ssp {
 entry:
   %0 = bitcast i8* %P to i32*
-  %tmp2 = load i32* %0
-  %add.ptr = getelementptr inbounds i8* %P, i64 1
-  %tmp5 = load i8* %add.ptr
+  %tmp2 = load i32, i32* %0
+  %add.ptr = getelementptr inbounds i8, i8* %P, i64 1
+  %tmp5 = load i8, i8* %add.ptr
   %conv = zext i8 %tmp5 to i32
   %add = add nsw i32 %tmp2, %conv
   ret i32 %add
 
 ; TEMPORARILYDISABLED-LABEL: @load_load_partial_alias(
-; TEMPORARILYDISABLED: load i32*
+; TEMPORARILYDISABLED: load i32, i32*
 ; TEMPORARILYDISABLED-NOT: load
 ; TEMPORARILYDISABLED: lshr i32 {{.*}}, 8
 ; TEMPORARILYDISABLED-NOT: load
@@ -603,13 +603,13 @@ entry:
 define i32 @load_load_partial_alias_cross_block(i8* %P) nounwind ssp {
 entry:
   %xx = bitcast i8* %P to i32*
-  %x1 = load i32* %xx, align 4
+  %x1 = load i32, i32* %xx, align 4
   %cmp = icmp eq i32 %x1, 127
   br i1 %cmp, label %land.lhs.true, label %if.end
 
 land.lhs.true:                                    ; preds = %entry
-  %arrayidx4 = getelementptr inbounds i8* %P, i64 1
-  %tmp5 = load i8* %arrayidx4, align 1
+  %arrayidx4 = getelementptr inbounds i8, i8* %P, i64 1
+  %tmp5 = load i8, i8* %arrayidx4, align 1
   %conv6 = zext i8 %tmp5 to i32
   ret i32 %conv6
 
@@ -632,39 +632,39 @@ if.end:
 
 define i32 @test_widening1(i8* %P) nounwind ssp noredzone {
 entry:
-  %tmp = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 1), align 4
+  %tmp = load i8, i8* getelementptr inbounds (%widening1, %widening1* @f, i64 0, i32 1), align 4
   %conv = zext i8 %tmp to i32
-  %tmp1 = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 2), align 1
+  %tmp1 = load i8, i8* getelementptr inbounds (%widening1, %widening1* @f, i64 0, i32 2), align 1
   %conv2 = zext i8 %tmp1 to i32
   %add = add nsw i32 %conv, %conv2
   ret i32 %add
 ; CHECK-LABEL: @test_widening1(
 ; CHECK-NOT: load
-; CHECK: load i16*
+; CHECK: load i16, i16*
 ; CHECK-NOT: load
 ; CHECK: ret i32
 }
 
 define i32 @test_widening2() nounwind ssp noredzone {
 entry:
-  %tmp = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 1), align 4
+  %tmp = load i8, i8* getelementptr inbounds (%widening1, %widening1* @f, i64 0, i32 1), align 4
   %conv = zext i8 %tmp to i32
-  %tmp1 = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 2), align 1
+  %tmp1 = load i8, i8* getelementptr inbounds (%widening1, %widening1* @f, i64 0, i32 2), align 1
   %conv2 = zext i8 %tmp1 to i32
   %add = add nsw i32 %conv, %conv2
 
-  %tmp2 = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 3), align 2
+  %tmp2 = load i8, i8* getelementptr inbounds (%widening1, %widening1* @f, i64 0, i32 3), align 2
   %conv3 = zext i8 %tmp2 to i32
   %add2 = add nsw i32 %add, %conv3
 
-  %tmp3 = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 4), align 1
+  %tmp3 = load i8, i8* getelementptr inbounds (%widening1, %widening1* @f, i64 0, i32 4), align 1
   %conv4 = zext i8 %tmp3 to i32
   %add3 = add nsw i32 %add2, %conv3
 
   ret i32 %add3
 ; CHECK-LABEL: @test_widening2(
 ; CHECK-NOT: load
-; CHECK: load i32*
+; CHECK: load i32, i32*
 ; CHECK-NOT: load
 ; CHECK: ret i32
 }
@@ -691,9 +691,9 @@ declare void @use3(i8***, i8**)
 ; PR8908
 define void @test_escape1() nounwind {
   %x = alloca i8**, align 8
-  store i8** getelementptr inbounds ([5 x i8*]* @_ZTV1X, i64 0, i64 2), i8*** %x, align 8
+  store i8** getelementptr inbounds ([5 x i8*], [5 x i8*]* @_ZTV1X, i64 0, i64 2), i8*** %x, align 8
   call void @use() nounwind
-  %DEAD = load i8*** %x, align 8
+  %DEAD = load i8**, i8*** %x, align 8
   call void @use3(i8*** %x, i8** %DEAD) nounwind
   ret void
 ; CHECK: test_escape1
diff --git a/test/Transforms/GVN/tbaa.ll b/test/Transforms/GVN/tbaa.ll
index 1b3494ca4be3..b5a717b0984a 100644
--- a/test/Transforms/GVN/tbaa.ll
+++ b/test/Transforms/GVN/tbaa.ll
@@ -1,4 +1,4 @@
-; RUN: opt -basicaa -gvn -S < %s | FileCheck %s
+; RUN: opt -tbaa -basicaa -gvn -S < %s | FileCheck %s
 
 define i32 @test1(i8* %p, i8* %q) {
 ; CHECK: @test1(i8* %p, i8* %q)
@@ -72,6 +72,37 @@ define i32 @test7(i8* %p, i8* %q) {
   ret i32 %c
 }
 
+
+
+define i32 @test8(i32* %p, i32* %q) {
+; CHECK-LABEL: test8
+; CHECK-NEXT: store i32 15, i32* %p
+; CHECK-NEXT: ret i32 0
+; Since we know the location is invariant, we can forward the
+; load across the potentially aliasing store.
+
+  %a = load i32, i32* %q, !tbaa !10
+  store i32 15, i32* %p
+  %b = load i32, i32* %q, !tbaa !10
+  %c = sub i32 %a, %b
+  ret i32 %c
+}
+define i32 @test9(i32* %p, i32* %q) {
+; CHECK-LABEL: test9
+; CHECK-NEXT: call void @clobber()
+; CHECK-NEXT: ret i32 0
+; Since we know the location is invariant, we can forward the
+; load across the potentially aliasing store (within the call).
+
+  %a = load i32, i32* %q, !tbaa !10
+  call void @clobber()
+  %b = load i32, i32* %q, !tbaa !10
+  %c = sub i32 %a, %b
+  ret i32 %c
+}
+
+
+declare void @clobber()
 declare i32 @foo(i8*) readonly
 
 ; CHECK: [[TAGC]] = !{[[TYPEC:!.*]], [[TYPEC]], i64 0}
@@ -89,3 +120,9 @@ declare i32 @foo(i8*) readonly
 !6 = !{!"A", !2}
 !7 = !{!"B", !6}
 !8 = !{!"another root", null}
+
+
+;; A TBAA structure who's only point is to have a constant location
+!9 = !{!"yet another root"}
+!10 = !{!"node", !9, i64 1}
+
diff --git a/test/Transforms/GVN/volatile.ll b/test/Transforms/GVN/volatile.ll
new file mode 100644
index 000000000000..b31058db4ea8
--- /dev/null
+++ b/test/Transforms/GVN/volatile.ll
@@ -0,0 +1,157 @@
+; Tests that check our handling of volatile instructions encountered
+; when scanning for dependencies
+; RUN: opt -basicaa -gvn -S < %s | FileCheck %s
+
+; Check that we can bypass a volatile load when searching
+; for dependencies of a non-volatile load
+define i32 @test1(i32* nocapture %p, i32* nocapture %q) {
+; CHECK-LABEL: test1
+; CHECK:      %0 = load volatile i32, i32* %q
+; CHECK-NEXT: ret i32 0
+entry:
+  %x = load i32, i32* %p
+  load volatile i32, i32* %q
+  %y = load i32, i32* %p
+  %add = sub i32 %y, %x
+  ret i32 %add
+}
+
+; We can not value forward if the query instruction is 
+; volatile, this would be (in effect) removing the volatile load
+define i32 @test2(i32* nocapture %p, i32* nocapture %q) {
+; CHECK-LABEL: test2
+; CHECK:      %x = load i32, i32* %p
+; CHECK-NEXT: %y = load volatile i32, i32* %p
+; CHECK-NEXT: %add = sub i32 %y, %x
+entry:
+  %x = load i32, i32* %p
+  %y = load volatile i32, i32* %p
+  %add = sub i32 %y, %x
+  ret i32 %add
+}
+
+; If the query instruction is itself volatile, we *cannot*
+; reorder it even if p and q are noalias
+define i32 @test3(i32* noalias nocapture %p, i32* noalias nocapture %q) {
+; CHECK-LABEL: test3
+; CHECK:      %x = load i32, i32* %p
+; CHECK-NEXT: %0 = load volatile i32, i32* %q
+; CHECK-NEXT: %y = load volatile i32, i32* %p
+entry:
+  %x = load i32, i32* %p
+  load volatile i32, i32* %q
+  %y = load volatile i32, i32* %p
+  %add = sub i32 %y, %x
+  ret i32 %add
+}
+
+; If an encountered instruction is both volatile and ordered, 
+; we need to use the strictest ordering of either.  In this 
+; case, the ordering prevents forwarding.
+define i32 @test4(i32* noalias nocapture %p, i32* noalias nocapture %q) {
+; CHECK-LABEL: test4
+; CHECK:      %x = load i32, i32* %p
+; CHECK-NEXT: %0 = load atomic volatile i32, i32* %q seq_cst 
+; CHECK-NEXT: %y = load atomic i32, i32* %p seq_cst
+entry:
+  %x = load i32, i32* %p
+  load atomic volatile i32, i32* %q seq_cst, align 4
+  %y = load atomic i32, i32* %p seq_cst, align 4
+  %add = sub i32 %y, %x
+  ret i32 %add
+}
+
+; Value forwarding from a volatile load is perfectly legal
+define i32 @test5(i32* nocapture %p, i32* nocapture %q) {
+; CHECK-LABEL: test5
+; CHECK:      %x = load volatile i32, i32* %p
+; CHECK-NEXT: ret i32 0
+entry:
+  %x = load volatile i32, i32* %p
+  %y = load i32, i32* %p
+  %add = sub i32 %y, %x
+  ret i32 %add
+}
+
+; Does cross block redundancy elimination work with volatiles?
+define i32 @test6(i32* noalias nocapture %p, i32* noalias nocapture %q) {
+; CHECK-LABEL: test6
+; CHECK:      %y1 = load i32, i32* %p
+; CHECK-LABEL: header
+; CHECK:      %x = load volatile i32, i32* %q
+; CHECK-NEXT: %add = sub i32 %y1, %x
+entry:
+  %y1 = load i32, i32* %p
+  call void @use(i32 %y1)
+  br label %header
+header:
+  %x = load volatile i32, i32* %q
+  %y = load i32, i32* %p
+  %add = sub i32 %y, %x
+  %cnd = icmp eq i32 %add, 0
+  br i1 %cnd, label %exit, label %header
+exit:
+  ret i32 %add
+}
+
+; Does cross block PRE work with volatiles?
+define i32 @test7(i1 %c, i32* noalias nocapture %p, i32* noalias nocapture %q) {
+; CHECK-LABEL: test7
+; CHECK-LABEL: entry.header_crit_edge:
+; CHECK:       %y.pre = load i32, i32* %p
+; CHECK-LABEL: skip:
+; CHECK:       %y1 = load i32, i32* %p
+; CHECK-LABEL: header:
+; CHECK:      %y = phi i32
+; CHECK-NEXT: %x = load volatile i32, i32* %q
+; CHECK-NEXT: %add = sub i32 %y, %x
+entry:
+  br i1 %c, label %header, label %skip
+skip:
+  %y1 = load i32, i32* %p
+  call void @use(i32 %y1)
+  br label %header
+header:
+  %x = load volatile i32, i32* %q
+  %y = load i32, i32* %p
+  %add = sub i32 %y, %x
+  %cnd = icmp eq i32 %add, 0
+  br i1 %cnd, label %exit, label %header
+exit:
+  ret i32 %add
+}
+
+; Another volatile PRE case - two paths through a loop
+; load in preheader, one path read only, one not
+define i32 @test8(i1 %b, i1 %c, i32* noalias %p, i32* noalias %q) {
+; CHECK-LABEL: test8
+; CHECK-LABEL: entry
+; CHECK:       %y1 = load i32, i32* %p
+; CHECK-LABEL: header:
+; CHECK:      %y = phi i32
+; CHECK-NEXT: %x = load volatile i32, i32* %q
+; CHECK-NOT:  load
+; CHECK-LABEL: skip.header_crit_edge:
+; CHECK:       %y.pre = load i32, i32* %p
+entry:
+  %y1 = load i32, i32* %p
+  call void @use(i32 %y1)
+  br label %header
+header:
+  %x = load volatile i32, i32* %q
+  %y = load i32, i32* %p
+  call void @use(i32 %y)
+  br i1 %b, label %skip, label %header
+skip:
+  ; escaping the arguments is explicitly required since we marked 
+  ; them noalias
+  call void @clobber(i32* %p, i32* %q)
+  br i1 %c, label %header, label %exit
+exit:
+  %add = sub i32 %y, %x
+  ret i32 %add
+}
+
+declare void @use(i32) readonly
+declare void @clobber(i32* %p, i32* %q)
+
diff --git a/test/Transforms/GlobalDCE/2002-08-17-FunctionDGE.ll b/test/Transforms/GlobalDCE/2002-08-17-FunctionDGE.ll
index 766c227460e6..49a87d902305 100644
--- a/test/Transforms/GlobalDCE/2002-08-17-FunctionDGE.ll
+++ b/test/Transforms/GlobalDCE/2002-08-17-FunctionDGE.ll
@@ -11,7 +11,7 @@
 
  ;; dies when %b dies.
 define internal i32 @foo() {
-        %ret = load i32* @foo.upgrd.1           ; <i32> [#uses=1]
+        %ret = load i32, i32* @foo.upgrd.1           ; <i32> [#uses=1]
         ret i32 %ret
 }
 
diff --git a/test/Transforms/GlobalDCE/2002-08-17-WorkListTest.ll b/test/Transforms/GlobalDCE/2002-08-17-WorkListTest.ll
index 42fcb1e004a6..58d3f4c7d840 100644
--- a/test/Transforms/GlobalDCE/2002-08-17-WorkListTest.ll
+++ b/test/Transforms/GlobalDCE/2002-08-17-WorkListTest.ll
@@ -5,8 +5,8 @@
 
 @t0 = internal global [4 x i8] c"foo\00"                ; <[4 x i8]*> [#uses=1]
 @t1 = internal global [4 x i8] c"bar\00"                ; <[4 x i8]*> [#uses=1]
-@s1 = internal global [1 x i8*] [ i8* getelementptr ([4 x i8]* @t0, i32 0, i32 0) ]             ; <[1 x i8*]*> [#uses=0]
-@s2 = internal global [1 x i8*] [ i8* getelementptr ([4 x i8]* @t1, i64 0, i64 0) ]             ; <[1 x i8*]*> [#uses=0]
+@s1 = internal global [1 x i8*] [ i8* getelementptr ([4 x i8], [4 x i8]* @t0, i32 0, i32 0) ]             ; <[1 x i8*]*> [#uses=0]
+@s2 = internal global [1 x i8*] [ i8* getelementptr ([4 x i8], [4 x i8]* @t1, i64 0, i64 0) ]             ; <[1 x i8*]*> [#uses=0]
 @b = internal global i32* @a            ; <i32**> [#uses=0]
 @a = internal global i32 7              ; <i32*> [#uses=1]
 
diff --git a/test/Transforms/GlobalDCE/2002-09-12-Redeletion.ll b/test/Transforms/GlobalDCE/2002-09-12-Redeletion.ll
index 6221fa3a62fe..afa2629f8f6b 100644
--- a/test/Transforms/GlobalDCE/2002-09-12-Redeletion.ll
+++ b/test/Transforms/GlobalDCE/2002-09-12-Redeletion.ll
@@ -5,7 +5,7 @@
 @bar = internal global [2 x { i32*, i32 }] [ { i32*, i32 } { i32* @foo.upgrd.1, i32 7 }, { i32*, i32 } { i32* @foo.upgrd.1, i32 1 } ]            ; <[2 x { i32*, i32 }]*> [#uses=0]
 
 define internal i32 @foo() {
-        %ret = load i32* @foo.upgrd.1           ; <i32> [#uses=1]
+        %ret = load i32, i32* @foo.upgrd.1           ; <i32> [#uses=1]
         ret i32 %ret
 }
 
diff --git a/test/Transforms/GlobalDCE/2003-07-01-SelfReference.ll b/test/Transforms/GlobalDCE/2003-07-01-SelfReference.ll
index 738ec43aaeb1..781c57e4ad47 100644
--- a/test/Transforms/GlobalDCE/2003-07-01-SelfReference.ll
+++ b/test/Transforms/GlobalDCE/2003-07-01-SelfReference.ll
@@ -4,7 +4,7 @@
 declare i1 ()* @getfunc()
 
 define internal i1 @testfunc() {
-        %F = call i1 ()* ()* @getfunc( )                ; <i1 ()*> [#uses=1]
+        %F = call i1 ()* () @getfunc( )                ; <i1 ()*> [#uses=1]
         %c = icmp eq i1 ()* %F, @testfunc               ; <i1> [#uses=1]
         ret i1 %c
 }
diff --git a/test/Transforms/GlobalDCE/complex-constantexpr.ll b/test/Transforms/GlobalDCE/complex-constantexpr.ll
index 4bf1aeee709b..b4eed02eff23 100644
--- a/test/Transforms/GlobalDCE/complex-constantexpr.ll
+++ b/test/Transforms/GlobalDCE/complex-constantexpr.ll
@@ -19,7 +19,7 @@ bb:
   br label %bb2
 
 bb1:                                              ; preds = %bb11
-  %tmp = load i32* @global5, align 4
+  %tmp = load i32, i32* @global5, align 4
   br label %bb2
 
 bb2:                                              ; preds = %bb1, %bb
@@ -34,12 +34,12 @@ bb6:                                              ; preds = %bb2
   br label %bb8
 
 bb8:                                              ; preds = %bb6, %bb2
-  %tmp9 = load i32* @global7, align 4
+  %tmp9 = load i32, i32* @global7, align 4
   %tmp10 = icmp eq i32 %tmp9, 0
   br i1 %tmp10, label %bb11, label %bb15
 
 bb11:                                             ; preds = %bb8
-  %tmp12 = load i32* @global6, align 4
+  %tmp12 = load i32, i32* @global6, align 4
   %tmp13 = add nsw i32 %tmp12, 1
   store i32 %tmp13, i32* @global6, align 4
   %tmp14 = icmp slt i32 %tmp13, 42
@@ -69,9 +69,9 @@ bb:
 
 define void @blam() {
 bb:
-  store i32 ptrtoint (i32* @global to i32), i32* getelementptr inbounds (%struct.ham* @global8, i64 0, i32 0), align 4
+  store i32 ptrtoint (i32* @global to i32), i32* getelementptr inbounds (%struct.ham, %struct.ham* @global8, i64 0, i32 0), align 4
   store i32 0, i32* @global9, align 4
-  %tmp = load i32* getelementptr inbounds (%struct.ham* @global8, i64 0, i32 0), align 4
+  %tmp = load i32, i32* getelementptr inbounds (%struct.ham, %struct.ham* @global8, i64 0, i32 0), align 4
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb
@@ -89,7 +89,7 @@ bb1:                                              ; preds = %bb1, %bb
   br i1 %tmp12, label %bb13, label %bb1
 
 bb13:                                             ; preds = %bb1
-  store i32 %tmp10, i32* getelementptr inbounds (%struct.ham* @global8, i64 0, i32 0), align 4
+  store i32 %tmp10, i32* getelementptr inbounds (%struct.ham, %struct.ham* @global8, i64 0, i32 0), align 4
   store i32 0, i32* @global10, align 4
   store i32 %tmp6, i32* @global11, align 4
   store i32 20, i32* @global9, align 4
diff --git a/test/Transforms/GlobalDCE/global_ctors_integration.ll b/test/Transforms/GlobalDCE/global_ctors_integration.ll
index 5e6cc79f103c..f7f702a980d7 100644
--- a/test/Transforms/GlobalDCE/global_ctors_integration.ll
+++ b/test/Transforms/GlobalDCE/global_ctors_integration.ll
@@ -12,7 +12,7 @@
 @llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }]
 
 define internal void @__cxx_global_var_init() section "__TEXT,__StaticInit,regular,pure_instructions" {
-  %1 = load i32* @_ZN3Bar18LINKER_INITIALIZEDE, align 4
+  %1 = load i32, i32* @_ZN3Bar18LINKER_INITIALIZEDE, align 4
   call void @_ZN3FooC1E17LinkerInitialized(%class.Foo* @foo, i32 %1)
   ret void
 }
@@ -23,8 +23,8 @@ define linkonce_odr void @_ZN3FooC1E17LinkerInitialized(%class.Foo* %this, i32)
   %3 = alloca i32, align 4
   store %class.Foo* %this, %class.Foo** %2, align 8
   store i32 %0, i32* %3, align 4
-  %4 = load %class.Foo** %2
-  %5 = load i32* %3, align 4
+  %4 = load %class.Foo*, %class.Foo** %2
+  %5 = load i32, i32* %3, align 4
   call void @_ZN3FooC2E17LinkerInitialized(%class.Foo* %4, i32 %5)
   ret void
 }
@@ -35,7 +35,7 @@ define linkonce_odr void @_ZN3FooC2E17LinkerInitialized(%class.Foo* %this, i32)
   %3 = alloca i32, align 4
   store %class.Foo* %this, %class.Foo** %2, align 8
   store i32 %0, i32* %3, align 4
-  %4 = load %class.Foo** %2
+  %4 = load %class.Foo*, %class.Foo** %2
   ret void
 }
 
diff --git a/test/Transforms/GlobalDCE/indirectbr.ll b/test/Transforms/GlobalDCE/indirectbr.ll
index 90f1ae44b1ac..5671aea943f4 100644
--- a/test/Transforms/GlobalDCE/indirectbr.ll
+++ b/test/Transforms/GlobalDCE/indirectbr.ll
@@ -9,8 +9,8 @@ entry:
   br label %L1
 
 L1:
-  %arrayidx = getelementptr inbounds [3 x i8*]* @L, i32 0, i32 %idx
-  %l = load i8** %arrayidx
+  %arrayidx = getelementptr inbounds [3 x i8*], [3 x i8*]* @L, i32 0, i32 %idx
+  %l = load i8*, i8** %arrayidx
   indirectbr i8* %l, [label %L1, label %L2]
 
 L2:
diff --git a/test/Transforms/GlobalOpt/2004-10-10-CastStoreOnce.ll b/test/Transforms/GlobalOpt/2004-10-10-CastStoreOnce.ll
index bdcf1fa4778b..061b9b0670f0 100644
--- a/test/Transforms/GlobalOpt/2004-10-10-CastStoreOnce.ll
+++ b/test/Transforms/GlobalOpt/2004-10-10-CastStoreOnce.ll
@@ -4,8 +4,8 @@
 @G = internal global i32* null          ; <i32**> [#uses=2]
 
 define i32 @user() {
-        %P = load i32** @G              ; <i32*> [#uses=1]
-        %Q = load i32* %P               ; <i32> [#uses=1]
+        %P = load i32*, i32** @G              ; <i32*> [#uses=1]
+        %Q = load i32, i32* %P               ; <i32> [#uses=1]
         ret i32 %Q
 }
 
diff --git a/test/Transforms/GlobalOpt/2005-06-15-LocalizeConstExprCrash.ll b/test/Transforms/GlobalOpt/2005-06-15-LocalizeConstExprCrash.ll
index 7bcb1d430918..3efbde423416 100644
--- a/test/Transforms/GlobalOpt/2005-06-15-LocalizeConstExprCrash.ll
+++ b/test/Transforms/GlobalOpt/2005-06-15-LocalizeConstExprCrash.ll
@@ -4,7 +4,7 @@
 @g_40507551 = internal global i16 31038         ; <i16*> [#uses=1]
 
 define void @main() {
-        %tmp.4.i.1 = load i8* getelementptr (i8* bitcast (i16* @g_40507551 to i8*), i32 1)              ; <i8> [#uses=0]
+        %tmp.4.i.1 = load i8, i8* getelementptr (i8, i8* bitcast (i16* @g_40507551 to i8*), i32 1)              ; <i8> [#uses=0]
         ret void
 }
 
diff --git a/test/Transforms/GlobalOpt/2005-09-27-Crash.ll b/test/Transforms/GlobalOpt/2005-09-27-Crash.ll
index 43597bfd3685..061c88159dd3 100644
--- a/test/Transforms/GlobalOpt/2005-09-27-Crash.ll
+++ b/test/Transforms/GlobalOpt/2005-09-27-Crash.ll
@@ -8,7 +8,7 @@
 
 define fastcc void @pypy_array_constant() {
 block0:
-        %tmp.9 = getelementptr %structtype.test* bitcast ({ i32, { i32, [2 x i32] } }* @structinstance.test to %structtype.test*), i32 0, i32 0          ; <i32*> [#uses=0]
+        %tmp.9 = getelementptr %structtype.test, %structtype.test* bitcast ({ i32, { i32, [2 x i32] } }* @structinstance.test to %structtype.test*), i32 0, i32 0          ; <i32*> [#uses=0]
         ret void
 }
 
diff --git a/test/Transforms/GlobalOpt/2006-07-07-InlineAsmCrash.ll b/test/Transforms/GlobalOpt/2006-07-07-InlineAsmCrash.ll
index c9712198ce71..419ae101966a 100644
--- a/test/Transforms/GlobalOpt/2006-07-07-InlineAsmCrash.ll
+++ b/test/Transforms/GlobalOpt/2006-07-07-InlineAsmCrash.ll
@@ -106,12 +106,12 @@ entry:
 	%__priority_addr = alloca i32		; <i32*> [#uses=2]
 	store i32 %__initialize_p, i32* %__initialize_p_addr
 	store i32 %__priority, i32* %__priority_addr
-	%tmp = load i32* %__priority_addr		; <i32> [#uses=1]
+	%tmp = load i32, i32* %__priority_addr		; <i32> [#uses=1]
 	%tmp.upgrd.1 = icmp eq i32 %tmp, 65535		; <i1> [#uses=1]
 	br i1 %tmp.upgrd.1, label %cond_true, label %cond_next14
 
 cond_true:		; preds = %entry
-	%tmp8 = load i32* %__initialize_p_addr		; <i32> [#uses=1]
+	%tmp8 = load i32, i32* %__initialize_p_addr		; <i32> [#uses=1]
 	%tmp9 = icmp eq i32 %tmp8, 1		; <i1> [#uses=1]
 	br i1 %tmp9, label %cond_true10, label %cond_next14
 
diff --git a/test/Transforms/GlobalOpt/2006-11-01-ShrinkGlobalPhiCrash.ll b/test/Transforms/GlobalOpt/2006-11-01-ShrinkGlobalPhiCrash.ll
index 352639ac067c..7b62cf08a4b1 100644
--- a/test/Transforms/GlobalOpt/2006-11-01-ShrinkGlobalPhiCrash.ll
+++ b/test/Transforms/GlobalOpt/2006-11-01-ShrinkGlobalPhiCrash.ll
@@ -10,7 +10,7 @@ entry:
 
 cond_true16.i:          ; preds = %cond_true16.i, %entry
         %low.0.in.i.0 = phi i32* [ @nrow, %entry ], [ null, %cond_true16.i ]            ; <i32*> [#uses=1]
-        %low.0.i = load i32* %low.0.in.i.0              ; <i32> [#uses=0]
+        %low.0.i = load i32, i32* %low.0.in.i.0              ; <i32> [#uses=0]
         br label %cond_true16.i
 }
 
diff --git a/test/Transforms/GlobalOpt/2007-04-05-Crash.ll b/test/Transforms/GlobalOpt/2007-04-05-Crash.ll
index c7aca62895fa..f312fbbc9f93 100644
--- a/test/Transforms/GlobalOpt/2007-04-05-Crash.ll
+++ b/test/Transforms/GlobalOpt/2007-04-05-Crash.ll
@@ -9,7 +9,7 @@ target triple = "thumb-apple-darwin8"
 define zeroext i16 @__NSCharToUnicharCFWrapper(i8 zeroext  %ch)   {
 entry:
 	%iftmp.0.0.in.in = select i1 false, i16* @replacementUnichar, i16* null		; <i16*> [#uses=1]
-	%iftmp.0.0.in = load i16* %iftmp.0.0.in.in		; <i16> [#uses=1]
+	%iftmp.0.0.in = load i16, i16* %iftmp.0.0.in.in		; <i16> [#uses=1]
 	ret i16 %iftmp.0.0.in
 }
 
diff --git a/test/Transforms/GlobalOpt/2007-05-13-Crash.ll b/test/Transforms/GlobalOpt/2007-05-13-Crash.ll
index 57039093d1e4..90ba15c37074 100644
--- a/test/Transforms/GlobalOpt/2007-05-13-Crash.ll
+++ b/test/Transforms/GlobalOpt/2007-05-13-Crash.ll
@@ -9,9 +9,9 @@ target triple = "i686-apple-darwin8"
 @_ZZ19SFLGetVisibilityKeyvE19_kSFLLVisibilityKey = internal global %struct.__CFString* null             ; <%struct.__CFString**> [#uses=2]
 @_ZZ22SFLGetAlwaysVisibleKeyvE22_kSFLLAlwaysVisibleKey = internal global %struct.__CFString* null               ; <%struct.__CFString**> [#uses=7]
 internal constant %struct.__builtin_CFString {
-    i32* getelementptr ([0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), 
+    i32* getelementptr ([0 x i32], [0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), 
     i32 1992, 
-    i8* getelementptr ([14 x i8]* @.str, i32 0, i32 0), 
+    i8* getelementptr ([14 x i8], [14 x i8]* @.str, i32 0, i32 0), 
     i32 13 }, section "__DATA,__cfstring"               ; <%struct.__builtin_CFString*>:0 [#uses=1]
 @__CFConstantStringClassReference = external global [0 x i32]           ; <[0 x i32]*> [#uses=1]
 @.str = internal constant [14 x i8] c"AlwaysVisible\00"         ; <[14 x i8]*> [#uses=1]
@@ -19,13 +19,13 @@ internal constant %struct.__builtin_CFString {
 
 define %struct.__CFString* @_Z19SFLGetVisibilityKeyv() {
 entry:
-        %tmp1 = load %struct.__CFString** @_ZZ19SFLGetVisibilityKeyvE19_kSFLLVisibilityKey              ; <%struct.__CFString*> [#uses=1]
+        %tmp1 = load %struct.__CFString*, %struct.__CFString** @_ZZ19SFLGetVisibilityKeyvE19_kSFLLVisibilityKey              ; <%struct.__CFString*> [#uses=1]
         ret %struct.__CFString* %tmp1
 }
 
 define %struct.__CFString* @_Z22SFLGetAlwaysVisibleKeyv() {
 entry:
-        %tmp1 = load %struct.__CFString** @_ZZ22SFLGetAlwaysVisibleKeyvE22_kSFLLAlwaysVisibleKey                ; <%struct.__CFString*> [#uses=1]
+        %tmp1 = load %struct.__CFString*, %struct.__CFString** @_ZZ22SFLGetAlwaysVisibleKeyvE22_kSFLLAlwaysVisibleKey                ; <%struct.__CFString*> [#uses=1]
         %tmp2 = icmp eq %struct.__CFString* %tmp1, null         ; <i1> [#uses=1]
         br i1 %tmp2, label %cond_true, label %cond_next
 
@@ -34,25 +34,25 @@ cond_true:              ; preds = %entry
         br label %cond_next
 
 cond_next:              ; preds = %entry, %cond_true
-        %tmp4 = load %struct.__CFString** @_ZZ22SFLGetAlwaysVisibleKeyvE22_kSFLLAlwaysVisibleKey                ; <%struct.__CFString*> [#uses=1]
+        %tmp4 = load %struct.__CFString*, %struct.__CFString** @_ZZ22SFLGetAlwaysVisibleKeyvE22_kSFLLAlwaysVisibleKey                ; <%struct.__CFString*> [#uses=1]
         ret %struct.__CFString* %tmp4
 }
 
 define %struct.__CFString* @_Z21SFLGetNeverVisibleKeyv() {
 entry:
-        %tmp1 = load %struct.__CFString** @_ZZ21SFLGetNeverVisibleKeyvE21_kSFLLNeverVisibleKey          ; <%struct.__CFString*> [#uses=1]
+        %tmp1 = load %struct.__CFString*, %struct.__CFString** @_ZZ21SFLGetNeverVisibleKeyvE21_kSFLLNeverVisibleKey          ; <%struct.__CFString*> [#uses=1]
         ret %struct.__CFString* %tmp1
 }
 
 define %struct.__CFDictionary* @_ZN18SFLMutableListItem18GetPrefsDictionaryEv(%struct.SFLMutableListItem* %this) {
 entry:
-        %tmp4 = getelementptr %struct.SFLMutableListItem* %this, i32 0, i32 0  ; <i16*> [#uses=1]
-        %tmp5 = load i16* %tmp4         ; <i16> [#uses=1]
+        %tmp4 = getelementptr %struct.SFLMutableListItem, %struct.SFLMutableListItem* %this, i32 0, i32 0  ; <i16*> [#uses=1]
+        %tmp5 = load i16, i16* %tmp4         ; <i16> [#uses=1]
         %tmp6 = icmp eq i16 %tmp5, 0            ; <i1> [#uses=1]
         br i1 %tmp6, label %cond_next22, label %cond_true
 
 cond_true:              ; preds = %entry
-        %tmp9 = load %struct.__CFString** @_ZZ22SFLGetAlwaysVisibleKeyvE22_kSFLLAlwaysVisibleKey                ; <%struct.__CFString*> [#uses=1]
+        %tmp9 = load %struct.__CFString*, %struct.__CFString** @_ZZ22SFLGetAlwaysVisibleKeyvE22_kSFLLAlwaysVisibleKey                ; <%struct.__CFString*> [#uses=1]
         %tmp10 = icmp eq %struct.__CFString* %tmp9, null                ; <i1> [#uses=1]
         br i1 %tmp10, label %cond_true13, label %cond_next22
 
@@ -62,8 +62,8 @@ cond_true13:            ; preds = %cond_true
 
 cond_next22:            ; preds = %entry, %cond_true13, %cond_true
         %iftmp.1.0.in = phi %struct.__CFString** [ @_ZZ22SFLGetAlwaysVisibleKeyvE22_kSFLLAlwaysVisibleKey, %cond_true ], [ @_ZZ22SFLGetAlwaysVisibleKeyvE22_kSFLLAlwaysVisibleKey, %cond_true13 ], [ @_ZZ21SFLGetNeverVisibleKeyvE21_kSFLLNeverVisibleKey, %entry ]             ; <%struct.__CFString**> [#uses=1]
-        %iftmp.1.0 = load %struct.__CFString** %iftmp.1.0.in            ; <%struct.__CFString*> [#uses=1]
-        %tmp24 = load %struct.__CFString** @_ZZ19SFLGetVisibilityKeyvE19_kSFLLVisibilityKey             ; <%struct.__CFString*> [#uses=1]
+        %iftmp.1.0 = load %struct.__CFString*, %struct.__CFString** %iftmp.1.0.in            ; <%struct.__CFString*> [#uses=1]
+        %tmp24 = load %struct.__CFString*, %struct.__CFString** @_ZZ19SFLGetVisibilityKeyvE19_kSFLLVisibilityKey             ; <%struct.__CFString*> [#uses=1]
         %tmp2728 = bitcast %struct.__CFString* %tmp24 to i8*            ; <i8*> [#uses=1]
         %tmp2930 = bitcast %struct.__CFString* %iftmp.1.0 to i8*               ; <i8*> [#uses=1]
         call void @_Z20CFDictionaryAddValuePKvS0_( i8* %tmp2728, i8* %tmp2930 )
diff --git a/test/Transforms/GlobalOpt/2007-06-04-PackedStruct.ll b/test/Transforms/GlobalOpt/2007-06-04-PackedStruct.ll
index 7036c158ba67..f6e0bb70d63f 100644
--- a/test/Transforms/GlobalOpt/2007-06-04-PackedStruct.ll
+++ b/test/Transforms/GlobalOpt/2007-06-04-PackedStruct.ll
@@ -28,7 +28,7 @@ entry:
 	br i1 %tmp7, label %cond_true, label %cond_next
 
 cond_true:		; preds = %entry
-	store i8 0, i8* getelementptr (%"struct.std::map<int,int,std::less<int>,std::allocator<std::pair<const int, int> > >"* @someMap, i32 0, i32 0, i32 0, i32 0, i32 0)
+	store i8 0, i8* getelementptr (%"struct.std::map<int,int,std::less<int>,std::allocator<std::pair<const int, int> > >", %"struct.std::map<int,int,std::less<int>,std::allocator<std::pair<const int, int> > >"* @someMap, i32 0, i32 0, i32 0, i32 0, i32 0)
 	ret void
 
 cond_next:		; preds = %entry
diff --git a/test/Transforms/GlobalOpt/2007-11-09-GEP-GEP-Crash.ll b/test/Transforms/GlobalOpt/2007-11-09-GEP-GEP-Crash.ll
index 442cb921d8a3..7a2de55771b2 100644
--- a/test/Transforms/GlobalOpt/2007-11-09-GEP-GEP-Crash.ll
+++ b/test/Transforms/GlobalOpt/2007-11-09-GEP-GEP-Crash.ll
@@ -9,9 +9,9 @@ target triple = "powerpc-apple-darwin8"
 
 define i8 @func() {
 entry:
-        %tmp10 = getelementptr [2 x i32]* getelementptr ([6 x [2 x i32]]* @aaui1, i32 0, i32 0), i32 5, i32 1           ; <i32*> [#uses=1]
-        %tmp11 = load i32* %tmp10, align 4              ; <i32> [#uses=1]
-        %tmp12 = call i32 (...)* @func3( i32* null, i32 0, i32 %tmp11 )         ; <i32> [#uses=0]
+        %tmp10 = getelementptr [2 x i32], [2 x i32]* getelementptr ([6 x [2 x i32]], [6 x [2 x i32]]* @aaui1, i32 0, i32 0), i32 5, i32 1           ; <i32*> [#uses=1]
+        %tmp11 = load i32, i32* %tmp10, align 4              ; <i32> [#uses=1]
+        %tmp12 = call i32 (...) @func3( i32* null, i32 0, i32 %tmp11 )         ; <i32> [#uses=0]
         ret i8 undef
 }
 
diff --git a/test/Transforms/GlobalOpt/2008-01-03-Crash.ll b/test/Transforms/GlobalOpt/2008-01-03-Crash.ll
index 4105ab1ed5b9..dc41fdb8de46 100644
--- a/test/Transforms/GlobalOpt/2008-01-03-Crash.ll
+++ b/test/Transforms/GlobalOpt/2008-01-03-Crash.ll
@@ -20,7 +20,7 @@ stack_restore:		; preds = %cond_next20.i
 	ret i32 0
 
 cond_next21.i.i23.i:		; preds = %cond_next20.i
-	%tmp6.i4.i = load i32* bitcast (void (i32)** @indirect1 to i32*), align 4		; <i32> [#uses=0]
+	%tmp6.i4.i = load i32, i32* bitcast (void (i32)** @indirect1 to i32*), align 4		; <i32> [#uses=0]
 	ret i32 0
 }
 
diff --git a/test/Transforms/GlobalOpt/2008-01-13-OutOfRangeSROA.ll b/test/Transforms/GlobalOpt/2008-01-13-OutOfRangeSROA.ll
index 7c07d5d9a23a..8df7050b38a7 100644
--- a/test/Transforms/GlobalOpt/2008-01-13-OutOfRangeSROA.ll
+++ b/test/Transforms/GlobalOpt/2008-01-13-OutOfRangeSROA.ll
@@ -4,13 +4,13 @@
 @mm = internal global [16 x [31 x double]] zeroinitializer, align 32
 
 define void @test(i32 %X) {
-	%P = getelementptr [16 x [31 x double]]* @mm, i32 0, i32 0, i32 %X
+	%P = getelementptr [16 x [31 x double]], [16 x [31 x double]]* @mm, i32 0, i32 0, i32 %X
 	store double 1.0, double* %P
 	ret void
 }
 
 define double @get(i32 %X) {
-	%P = getelementptr [16 x [31 x double]]* @mm, i32 0, i32 0, i32 %X
-	%V = load double* %P
+	%P = getelementptr [16 x [31 x double]], [16 x [31 x double]]* @mm, i32 0, i32 0, i32 %X
+	%V = load double, double* %P
 	ret double %V
 }
diff --git a/test/Transforms/GlobalOpt/2008-01-29-VolatileGlobal.ll b/test/Transforms/GlobalOpt/2008-01-29-VolatileGlobal.ll
index 08b2cb1eb6f2..ac663604854d 100644
--- a/test/Transforms/GlobalOpt/2008-01-29-VolatileGlobal.ll
+++ b/test/Transforms/GlobalOpt/2008-01-29-VolatileGlobal.ll
@@ -3,7 +3,7 @@
 
 define double @foo() nounwind  {
 entry:
-	%tmp1 = load volatile double* @t0.1441, align 8		; <double> [#uses=2]
+	%tmp1 = load volatile double, double* @t0.1441, align 8		; <double> [#uses=2]
 	%tmp4 = fmul double %tmp1, %tmp1		; <double> [#uses=1]
 	ret double %tmp4
 }
diff --git a/test/Transforms/GlobalOpt/2008-04-26-SROA-Global-Align.ll b/test/Transforms/GlobalOpt/2008-04-26-SROA-Global-Align.ll
index d58becd53078..934d928aa88e 100644
--- a/test/Transforms/GlobalOpt/2008-04-26-SROA-Global-Align.ll
+++ b/test/Transforms/GlobalOpt/2008-04-26-SROA-Global-Align.ll
@@ -16,16 +16,16 @@ target triple = "x86_64-apple-darwin8"
 
 
 define void @test() {
-  store double 1.0, double* getelementptr (%T* @G, i32 0, i32 0), align 16
-  store double 2.0, double* getelementptr (%T* @G, i32 0, i32 1), align 8
-  store double 3.0, double* getelementptr (%T* @G, i32 0, i32 2), align 16
+  store double 1.0, double* getelementptr (%T, %T* @G, i32 0, i32 0), align 16
+  store double 2.0, double* getelementptr (%T, %T* @G, i32 0, i32 1), align 8
+  store double 3.0, double* getelementptr (%T, %T* @G, i32 0, i32 2), align 16
   ret void
 }
 
 define double @test2() {
-  %V1 = load double* getelementptr (%T* @G, i32 0, i32 0), align 16
-  %V2 = load double* getelementptr (%T* @G, i32 0, i32 1), align 8
-  %V3 = load double* getelementptr (%T* @G, i32 0, i32 2), align 16
+  %V1 = load double, double* getelementptr (%T, %T* @G, i32 0, i32 0), align 16
+  %V2 = load double, double* getelementptr (%T, %T* @G, i32 0, i32 1), align 8
+  %V3 = load double, double* getelementptr (%T, %T* @G, i32 0, i32 2), align 16
   %R = fadd double %V1, %V2
   %R2 = fadd double %R, %V3
   ret double %R2
diff --git a/test/Transforms/GlobalOpt/2008-07-17-addrspace.ll b/test/Transforms/GlobalOpt/2008-07-17-addrspace.ll
index 0867ca9c5431..d602df1e701c 100644
--- a/test/Transforms/GlobalOpt/2008-07-17-addrspace.ll
+++ b/test/Transforms/GlobalOpt/2008-07-17-addrspace.ll
@@ -10,8 +10,8 @@
 @array = internal addrspace(1) global [ 2 x i32 ] zeroinitializer 
 
 define i32 @foo() {
-  %A = load i32 addrspace(1) * getelementptr ({ i32, i32 } addrspace(1) * @struct, i32 0, i32 0)
-  %B = load i32 addrspace(1) * getelementptr ([ 2 x i32 ] addrspace(1) * @array, i32 0, i32 0)
+  %A = load i32, i32 addrspace(1) * getelementptr ({ i32, i32 }, { i32, i32 } addrspace(1) * @struct, i32 0, i32 0)
+  %B = load i32, i32 addrspace(1) * getelementptr ([ 2 x i32 ], [ 2 x i32 ] addrspace(1) * @array, i32 0, i32 0)
   ; Use the loaded values, so they won't get removed completely
   %R = add i32 %A, %B
   ret i32 %R
@@ -20,8 +20,8 @@ define i32 @foo() {
 ; We put stores in a different function, so that the global variables won't get
 ; optimized away completely.
 define void @bar(i32 %R) {
-  store i32 %R, i32 addrspace(1) * getelementptr ([ 2 x i32 ] addrspace(1) * @array, i32 0, i32 0)
-  store i32 %R, i32 addrspace(1) * getelementptr ({ i32, i32 } addrspace(1) * @struct, i32 0, i32 0)
+  store i32 %R, i32 addrspace(1) * getelementptr ([ 2 x i32 ], [ 2 x i32 ] addrspace(1) * @array, i32 0, i32 0)
+  store i32 %R, i32 addrspace(1) * getelementptr ({ i32, i32 }, { i32, i32 } addrspace(1) * @struct, i32 0, i32 0)
   ret void
 }
 
diff --git a/test/Transforms/GlobalOpt/2008-12-16-HeapSRACrash-2.ll b/test/Transforms/GlobalOpt/2008-12-16-HeapSRACrash-2.ll
index b74e4fcd1ef0..bd32163e5f9f 100644
--- a/test/Transforms/GlobalOpt/2008-12-16-HeapSRACrash-2.ll
+++ b/test/Transforms/GlobalOpt/2008-12-16-HeapSRACrash-2.ll
@@ -6,9 +6,9 @@ target triple = "i386-apple-darwin7"
 
 define void @bar(i32 %Size) nounwind noinline {
 entry:
-        %malloccall = tail call i8* @malloc(i32 trunc (i64 mul (i64 ptrtoint (i32* getelementptr (i32* null, i32 1) to i64), i64 2000000) to i32))
+        %malloccall = tail call i8* @malloc(i32 trunc (i64 mul (i64 ptrtoint (i32* getelementptr (i32, i32* null, i32 1) to i64), i64 2000000) to i32))
         %tmp = bitcast i8* %malloccall to [1000000 x %struct.foo]*
-	%.sub = getelementptr [1000000 x %struct.foo]* %tmp, i32 0, i32 0		; <%struct.foo*> [#uses=1]
+	%.sub = getelementptr [1000000 x %struct.foo], [1000000 x %struct.foo]* %tmp, i32 0, i32 0		; <%struct.foo*> [#uses=1]
 	store %struct.foo* %.sub, %struct.foo** @X, align 4
 	ret void
 }
@@ -18,11 +18,11 @@ declare noalias i8* @malloc(i32)
 
 define i32 @baz() nounwind readonly noinline {
 bb1.thread:
-	%tmpLD1 = load %struct.foo** @X, align 4		; <%struct.foo*> [#uses=2]
+	%tmpLD1 = load %struct.foo*, %struct.foo** @X, align 4		; <%struct.foo*> [#uses=2]
 	br label %bb1
 
 bb1:		; preds = %bb1, %bb1.thread
 	%tmp = phi %struct.foo* [ %tmpLD1, %bb1.thread ], [ %tmpLD1, %bb1 ]		; <%struct.foo*> [#uses=1]
-	%0 = getelementptr %struct.foo* %tmp, i32 1		; <%struct.foo*> [#uses=0]
+	%0 = getelementptr %struct.foo, %struct.foo* %tmp, i32 1		; <%struct.foo*> [#uses=0]
 	br label %bb1
 }
diff --git a/test/Transforms/GlobalOpt/2008-12-16-HeapSRACrash.ll b/test/Transforms/GlobalOpt/2008-12-16-HeapSRACrash.ll
index 613cb7bcef02..e9c16785afae 100644
--- a/test/Transforms/GlobalOpt/2008-12-16-HeapSRACrash.ll
+++ b/test/Transforms/GlobalOpt/2008-12-16-HeapSRACrash.ll
@@ -6,9 +6,9 @@ target triple = "i386-apple-darwin7"
 
 define void @bar(i32 %Size) nounwind noinline {
 entry:
-        %malloccall = tail call i8* @malloc(i32 trunc (i64 mul (i64 ptrtoint (i32* getelementptr (i32* null, i32 1) to i64), i64 2000000) to i32))
+        %malloccall = tail call i8* @malloc(i32 trunc (i64 mul (i64 ptrtoint (i32* getelementptr (i32, i32* null, i32 1) to i64), i64 2000000) to i32))
         %tmp = bitcast i8* %malloccall to [1000000 x %struct.foo]*
-	%.sub = getelementptr [1000000 x %struct.foo]* %tmp, i32 0, i32 0		; <%struct.foo*> [#uses=1]
+	%.sub = getelementptr [1000000 x %struct.foo], [1000000 x %struct.foo]* %tmp, i32 0, i32 0		; <%struct.foo*> [#uses=1]
 	store %struct.foo* %.sub, %struct.foo** @X, align 4
 	ret void
 }
@@ -17,7 +17,7 @@ declare noalias i8* @malloc(i32)
 
 define i32 @baz() nounwind readonly noinline {
 bb1.thread:
-	%tmpLD1 = load %struct.foo** @X, align 4		; <%struct.foo*> [#uses=3]
+	%tmpLD1 = load %struct.foo*, %struct.foo** @X, align 4		; <%struct.foo*> [#uses=3]
 	store %struct.foo* %tmpLD1, %struct.foo** null
 	br label %bb1
 
diff --git a/test/Transforms/GlobalOpt/2009-01-13-phi-user.ll b/test/Transforms/GlobalOpt/2009-01-13-phi-user.ll
index e76c44dbd044..21ec5267b973 100644
--- a/test/Transforms/GlobalOpt/2009-01-13-phi-user.ll
+++ b/test/Transforms/GlobalOpt/2009-01-13-phi-user.ll
@@ -12,15 +12,15 @@ entry:
 	br label %bb1
 
 bb:		; preds = %bb1
-	%0 = getelementptr %struct.node* %t.0, i64 0, i32 1		; <i32*> [#uses=1]
-	%1 = load i32* %0, align 4		; <i32> [#uses=1]
-	%2 = getelementptr %struct.node* %t.0, i64 0, i32 0		; <%struct.node**> [#uses=1]
+	%0 = getelementptr %struct.node, %struct.node* %t.0, i64 0, i32 1		; <i32*> [#uses=1]
+	%1 = load i32, i32* %0, align 4		; <i32> [#uses=1]
+	%2 = getelementptr %struct.node, %struct.node* %t.0, i64 0, i32 0		; <%struct.node**> [#uses=1]
 	br label %bb1
 
 bb1:		; preds = %bb, %entry
 	%value.0 = phi i32 [ undef, %entry ], [ %1, %bb ]		; <i32> [#uses=1]
 	%t.0.in = phi %struct.node** [ @head, %entry ], [ %2, %bb ]		; <%struct.node**> [#uses=1]
-	%t.0 = load %struct.node** %t.0.in		; <%struct.node*> [#uses=3]
+	%t.0 = load %struct.node*, %struct.node** %t.0.in		; <%struct.node*> [#uses=3]
 	%3 = icmp eq %struct.node* %t.0, null		; <i1> [#uses=1]
 	br i1 %3, label %bb2, label %bb
 
diff --git a/test/Transforms/GlobalOpt/2009-02-15-BitcastAlias.ll b/test/Transforms/GlobalOpt/2009-02-15-BitcastAlias.ll
index d6a565ad10a8..a3e90045d64b 100644
--- a/test/Transforms/GlobalOpt/2009-02-15-BitcastAlias.ll
+++ b/test/Transforms/GlobalOpt/2009-02-15-BitcastAlias.ll
@@ -5,6 +5,6 @@
 @a = alias bitcast (i32* @g to i8*)
 
 define void @f() {
-	%tmp = load i8* @a
+	%tmp = load i8, i8* @a
 	ret void
 }
diff --git a/test/Transforms/GlobalOpt/2009-02-15-ResolveAlias.ll b/test/Transforms/GlobalOpt/2009-02-15-ResolveAlias.ll
index 8efd01807fdb..6933d4a8d96c 100644
--- a/test/Transforms/GlobalOpt/2009-02-15-ResolveAlias.ll
+++ b/test/Transforms/GlobalOpt/2009-02-15-ResolveAlias.ll
@@ -9,7 +9,7 @@ define internal void @f() {
 @a = alias void ()* @f
 
 define void @g() {
-	call void()* @a()
+	call void() @a()
 	ret void
 }
 
@@ -17,7 +17,7 @@ define void @g() {
 ; CHECK-NOT: @b
 
 define void @h() {
-	call void()* @b()
+	call void() @b()
 ; CHECK: call void @g
 	ret void
 }
diff --git a/test/Transforms/GlobalOpt/2009-03-05-dbg.ll b/test/Transforms/GlobalOpt/2009-03-05-dbg.ll
index 049eef10eb7a..a8d618ae522d 100644
--- a/test/Transforms/GlobalOpt/2009-03-05-dbg.ll
+++ b/test/Transforms/GlobalOpt/2009-03-05-dbg.ll
@@ -33,7 +33,7 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 define i32 @bar() nounwind ssp {
 entry:
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  %0 = load i32* @Stop, align 4, !dbg !13         ; <i32> [#uses=1]
+  %0 = load i32, i32* @Stop, align 4, !dbg !13         ; <i32> [#uses=1]
   %1 = icmp eq i32 %0, 1, !dbg !13                ; <i1> [#uses=1]
   br i1 %1, label %bb, label %bb1, !dbg !13
 
@@ -55,25 +55,25 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 
 !llvm.dbg.gv = !{!0}
 
-!0 = !{!"0x34\00Stop\00Stop\00\002\001\001", !1, !1, !2, i32* @Stop} ; [ DW_TAG_variable ]
-!1 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\001\00\000\00\000", !20, !21, !21, null, null, null} ; [ DW_TAG_compile_unit ]
-!2 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !1} ; [ DW_TAG_base_type ]
-!3 = !{!"0x101\00i\004\000", !4, !1, !2} ; [ DW_TAG_arg_variable ]
-!4 = !{!"0x2e\00foo\00foo\00foo\004\000\001\000\006\000\000\000", i32 0, !1, !5, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!5 = !{!"0x15\00\000\000\000\000\000\000", !1, null, null, !6, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DIGlobalVariable(name: "Stop", line: 2, isLocal: true, isDefinition: true, scope: !1, file: !1, type: !2, variable: i32* @Stop)
+!1 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 0, file: !20, enums: !21, retainedTypes: !21)
+!2 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!3 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 4, arg: 0, scope: !4, file: !1, type: !2)
+!4 = !DISubprogram(name: "foo", linkageName: "foo", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !1, type: !5)
+!5 = !DISubroutineType(types: !6)
 !6 = !{!2, !2}
-!7 = !MDLocation(line: 5, scope: !8)
-!8 = !{!"0xb\000\000\000", !20, !4} ; [ DW_TAG_lexical_block ]
-!9 = !MDLocation(line: 6, scope: !8)
-!10 = !MDLocation(line: 7, scope: !8)
-!11 = !MDLocation(line: 9, scope: !8)
-!12 = !MDLocation(line: 11, scope: !8)
-!13 = !MDLocation(line: 14, scope: !14)
-!14 = !{!"0xb\000\000\000", !20, !15} ; [ DW_TAG_lexical_block ]
-!15 = !{!"0x2e\00bar\00bar\00bar\0013\000\001\000\006\000\000\000", i32 0, !1, !16, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!16 = !{!"0x15\00\000\000\000\000\000\000", !1, null, null, !17, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = !DILocation(line: 5, scope: !8)
+!8 = distinct !DILexicalBlock(line: 0, column: 0, file: !20, scope: !4)
+!9 = !DILocation(line: 6, scope: !8)
+!10 = !DILocation(line: 7, scope: !8)
+!11 = !DILocation(line: 9, scope: !8)
+!12 = !DILocation(line: 11, scope: !8)
+!13 = !DILocation(line: 14, scope: !14)
+!14 = distinct !DILexicalBlock(line: 0, column: 0, file: !20, scope: !15)
+!15 = !DISubprogram(name: "bar", linkageName: "bar", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !1, type: !16)
+!16 = !DISubroutineType(types: !17)
 !17 = !{!2}
-!18 = !MDLocation(line: 15, scope: !14)
-!19 = !MDLocation(line: 16, scope: !14)
-!20 = !{!"g.c", !"/tmp"}
+!18 = !DILocation(line: 15, scope: !14)
+!19 = !DILocation(line: 16, scope: !14)
+!20 = !DIFile(filename: "g.c", directory: "/tmp")
 !21 = !{i32 0}
diff --git a/test/Transforms/GlobalOpt/2009-03-07-PromotePtrToBool.ll b/test/Transforms/GlobalOpt/2009-03-07-PromotePtrToBool.ll
index 059af1cfeac8..469fa765c7af 100644
--- a/test/Transforms/GlobalOpt/2009-03-07-PromotePtrToBool.ll
+++ b/test/Transforms/GlobalOpt/2009-03-07-PromotePtrToBool.ll
@@ -12,6 +12,6 @@ entry:
 
 define i32* @get() nounwind {
 entry:
-	%0 = load i32** @X, align 4		; <i32*> [#uses=1]
+	%0 = load i32*, i32** @X, align 4		; <i32*> [#uses=1]
 	ret i32* %0
 }
diff --git a/test/Transforms/GlobalOpt/2009-06-01-RecursivePHI.ll b/test/Transforms/GlobalOpt/2009-06-01-RecursivePHI.ll
index d3c3ff59fea1..30e4d4226215 100644
--- a/test/Transforms/GlobalOpt/2009-06-01-RecursivePHI.ll
+++ b/test/Transforms/GlobalOpt/2009-06-01-RecursivePHI.ll
@@ -33,7 +33,7 @@ bb.i4.i:		; preds = %my_calloc.exit.i
 	unreachable
 
 my_calloc.exit5.i:		; preds = %my_calloc.exit.i
-	%.pre.i58 = load %struct.s_net** @net, align 4		; <%struct.s_net*> [#uses=1]
+	%.pre.i58 = load %struct.s_net*, %struct.s_net** @net, align 4		; <%struct.s_net*> [#uses=1]
 	br label %bb17.i78
 
 bb1.i61:		; preds = %bb4.preheader.i, %bb1.i61
@@ -58,11 +58,11 @@ bb.i1.i68:		; preds = %bb8.i67
 	unreachable
 
 my_malloc.exit.i70:		; preds = %bb8.i67
-	%0 = load %struct.s_net** @net, align 4		; <%struct.s_net*> [#uses=1]
+	%0 = load %struct.s_net*, %struct.s_net** @net, align 4		; <%struct.s_net*> [#uses=1]
 	br i1 undef, label %bb9.i71, label %bb16.i77
 
 bb9.i71:		; preds = %bb9.i71, %my_malloc.exit.i70
-	%1 = load %struct.s_net** @net, align 4		; <%struct.s_net*> [#uses=1]
+	%1 = load %struct.s_net*, %struct.s_net** @net, align 4		; <%struct.s_net*> [#uses=1]
 	br i1 undef, label %bb9.i71, label %bb16.i77
 
 bb16.i77:		; preds = %bb9.i71, %my_malloc.exit.i70, %bb15.preheader.i
diff --git a/test/Transforms/GlobalOpt/2009-11-16-BrokenPerformHeapAllocSRoA.ll b/test/Transforms/GlobalOpt/2009-11-16-BrokenPerformHeapAllocSRoA.ll
index 40862bd038e1..461c25316e91 100644
--- a/test/Transforms/GlobalOpt/2009-11-16-BrokenPerformHeapAllocSRoA.ll
+++ b/test/Transforms/GlobalOpt/2009-11-16-BrokenPerformHeapAllocSRoA.ll
@@ -13,9 +13,9 @@ target triple = "x86_64-apple-darwin10.0"
 
 ; based on linit in office-ispell
 define void @test() nounwind ssp {
-  %1 = load i32* getelementptr inbounds (%struct.hashheader* @hashheader, i64 0, i32 13), align 8 ; <i32> [#uses=1]
+  %1 = load i32, i32* getelementptr inbounds (%struct.hashheader, %struct.hashheader* @hashheader, i64 0, i32 13), align 8 ; <i32> [#uses=1]
   %2 = sext i32 %1 to i64                         ; <i64> [#uses=1]
-  %3 = mul i64 %2, ptrtoint (%struct.strchartype* getelementptr (%struct.strchartype* null, i64 1) to i64) ; <i64> [#uses=1]
+  %3 = mul i64 %2, ptrtoint (%struct.strchartype* getelementptr (%struct.strchartype, %struct.strchartype* null, i64 1) to i64) ; <i64> [#uses=1]
   %4 = tail call i8* @malloc(i64 %3)              ; <i8*> [#uses=1]
 ; CHECK-NOT: call i8* @malloc(i64
   %5 = bitcast i8* %4 to %struct.strchartype*     ; <%struct.strchartype*> [#uses=1]
diff --git a/test/Transforms/GlobalOpt/2009-11-16-MallocSingleStoreToGlobalVar.ll b/test/Transforms/GlobalOpt/2009-11-16-MallocSingleStoreToGlobalVar.ll
index b73f62ba148b..25bb9769f49e 100644
--- a/test/Transforms/GlobalOpt/2009-11-16-MallocSingleStoreToGlobalVar.ll
+++ b/test/Transforms/GlobalOpt/2009-11-16-MallocSingleStoreToGlobalVar.ll
@@ -14,15 +14,15 @@ target triple = "x86_64-apple-darwin10.0"
 ; Derived from @DescribeChannel() in yacr2
 define void @test() nounwind ssp {
   store i64 2335, i64* @channelColumns, align 8
-  %1 = load i64* @channelColumns, align 8         ; <i64> [#uses=1]
+  %1 = load i64, i64* @channelColumns, align 8         ; <i64> [#uses=1]
   %2 = shl i64 %1, 3                              ; <i64> [#uses=1]
   %3 = add i64 %2, 8                              ; <i64> [#uses=1]
   %4 = call noalias i8* @malloc(i64 %3) nounwind  ; <i8*> [#uses=1]
 ; CHECK: call noalias i8* @malloc
   %5 = bitcast i8* %4 to i64*                     ; <i64*> [#uses=1]
   store i64* %5, i64** @TOP, align 8
-  %6 = load i64** @TOP, align 8                   ; <i64*> [#uses=1]
-  %7 = getelementptr inbounds i64* %6, i64 13     ; <i64*> [#uses=1]
+  %6 = load i64*, i64** @TOP, align 8                   ; <i64*> [#uses=1]
+  %7 = getelementptr inbounds i64, i64* %6, i64 13     ; <i64*> [#uses=1]
   store i64 0, i64* %7, align 8
   ret void
 }
diff --git a/test/Transforms/GlobalOpt/2010-02-25-MallocPromote.ll b/test/Transforms/GlobalOpt/2010-02-25-MallocPromote.ll
index 629d57c88424..9f53ce402fd4 100644
--- a/test/Transforms/GlobalOpt/2010-02-25-MallocPromote.ll
+++ b/test/Transforms/GlobalOpt/2010-02-25-MallocPromote.ll
@@ -12,7 +12,7 @@ bb918:
   %malloccall.i10 = call i8* @malloc(i32 16) nounwind ; <i8*> [#uses=1]
   %0 = bitcast i8* %malloccall.i10 to i32*        ; <i32*> [#uses=1]
   store i32* %0, i32** @fixLRBT, align 8
-  %1 = load i32** @fixLRBT, align 8               ; <i32*> [#uses=0]
-  %A = load i32* %1
+  %1 = load i32*, i32** @fixLRBT, align 8               ; <i32*> [#uses=0]
+  %A = load i32, i32* %1
   ret i32 %A
 }
diff --git a/test/Transforms/GlobalOpt/2010-02-26-MallocSROA.ll b/test/Transforms/GlobalOpt/2010-02-26-MallocSROA.ll
index ab7721fd9720..12fa34191926 100644
--- a/test/Transforms/GlobalOpt/2010-02-26-MallocSROA.ll
+++ b/test/Transforms/GlobalOpt/2010-02-26-MallocSROA.ll
@@ -10,7 +10,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define fastcc void @init_net() nounwind {
 entry:
-  %0 = load i32* @numf2s, align 4                 ; <i32> [#uses=1]
+  %0 = load i32, i32* @numf2s, align 4                 ; <i32> [#uses=1]
   %mallocsize2 = shl i32 %0, 4                    ; <i32> [#uses=1]
   %malloccall3 = tail call i8* @malloc(i32 %mallocsize2) nounwind ; <i8*> [#uses=1]
   %1 = bitcast i8* %malloccall3 to %struct.xyz*   ; <%struct.xyz*> [#uses=1]
@@ -20,7 +20,7 @@ entry:
 
 define fastcc void @load_train(i8* %trainfile, i32 %mode, i32 %objects) nounwind {
 entry:
-  %0 = load %struct.xyz** @Y, align 8             ; <%struct.xyz*> [#uses=0]
+  %0 = load %struct.xyz*, %struct.xyz** @Y, align 8             ; <%struct.xyz*> [#uses=0]
   ret void
 }
 
diff --git a/test/Transforms/GlobalOpt/alias-resolve.ll b/test/Transforms/GlobalOpt/alias-resolve.ll
index ebc20c66cf61..090d78455226 100644
--- a/test/Transforms/GlobalOpt/alias-resolve.ll
+++ b/test/Transforms/GlobalOpt/alias-resolve.ll
@@ -13,8 +13,8 @@
 ; CHECK: @weak1 = weak alias void ()* @bar2
 
 @bar4 = private unnamed_addr constant [2 x i8*] zeroinitializer
-@foo4 = linkonce_odr unnamed_addr alias getelementptr inbounds ([2 x i8*]* @bar4, i32 0, i32 1)
-; CHECK: @foo4 = linkonce_odr unnamed_addr alias getelementptr inbounds ([2 x i8*]* @bar4, i32 0, i32 1)
+@foo4 = linkonce_odr unnamed_addr alias getelementptr inbounds ([2 x i8*], [2 x i8*]* @bar4, i32 0, i32 1)
+; CHECK: @foo4 = linkonce_odr unnamed_addr alias getelementptr inbounds ([2 x i8*], [2 x i8*]* @bar4, i32 0, i32 1)
 
 define void @bar2() {
   ret void
diff --git a/test/Transforms/GlobalOpt/array-elem-refs.ll b/test/Transforms/GlobalOpt/array-elem-refs.ll
index ec472b0e99f2..c31965b656d3 100644
--- a/test/Transforms/GlobalOpt/array-elem-refs.ll
+++ b/test/Transforms/GlobalOpt/array-elem-refs.ll
@@ -4,16 +4,16 @@ target triple = "x86_64-unknown-linux-gnu"
 
 %struct.S = type { i8, i8 }
 
-@c = internal global i8** bitcast (i8* getelementptr (i8* bitcast ([8 x i8*]* @b to i8*), i64 48) to i8**), align 8
-@b = internal global [8 x i8*] [i8* null, i8* null, i8* null, i8* null, i8* null, i8* null, i8* getelementptr inbounds (%struct.S* @a, i32 0, i32 0), i8* getelementptr (i8* getelementptr inbounds (%struct.S* @a, i32 0, i32 0), i64 1)], align 16
+@c = internal global i8** bitcast (i8* getelementptr (i8, i8* bitcast ([8 x i8*]* @b to i8*), i64 48) to i8**), align 8
+@b = internal global [8 x i8*] [i8* null, i8* null, i8* null, i8* null, i8* null, i8* null, i8* getelementptr inbounds (%struct.S, %struct.S* @a, i32 0, i32 0), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S, %struct.S* @a, i32 0, i32 0), i64 1)], align 16
 @a = internal global %struct.S zeroinitializer, align 1
 
 ; Function Attrs: nounwind uwtable
 define signext i8 @foo() #0 {
 entry:
-  %0 = load i8*** @c, align 8
-  %1 = load i8** %0, align 8
-  %2 = load i8* %1, align 1
+  %0 = load i8**, i8*** @c, align 8
+  %1 = load i8*, i8** %0, align 8
+  %2 = load i8, i8* %1, align 1
   ret i8 %2
 
 ; CHECK-LABEL: @foo
diff --git a/test/Transforms/GlobalOpt/atomic.ll b/test/Transforms/GlobalOpt/atomic.ll
index ac05bfd68d9d..563c1fec7d27 100644
--- a/test/Transforms/GlobalOpt/atomic.ll
+++ b/test/Transforms/GlobalOpt/atomic.ll
@@ -8,7 +8,7 @@
 
 define void @test1() {
 entry:
-  %0 = load atomic i8* bitcast (i64* @GV1 to i8*) acquire, align 8
+  %0 = load atomic i8, i8* bitcast (i64* @GV1 to i8*) acquire, align 8
   ret void
 }
 
@@ -20,6 +20,6 @@ entry:
 }
 define i32 @test2b() {
 entry:
-  %atomic-load = load atomic i32* @GV2 seq_cst, align 4
+  %atomic-load = load atomic i32, i32* @GV2 seq_cst, align 4
   ret i32 %atomic-load
 }
diff --git a/test/Transforms/GlobalOpt/basictest.ll b/test/Transforms/GlobalOpt/basictest.ll
index 4332d3dd38c2..4c25e4f9f407 100644
--- a/test/Transforms/GlobalOpt/basictest.ll
+++ b/test/Transforms/GlobalOpt/basictest.ll
@@ -3,7 +3,7 @@
 @X = internal global i32 4              ; <i32*> [#uses=1]
 
 define i32 @foo() {
-        %V = load i32* @X               ; <i32> [#uses=1]
+        %V = load i32, i32* @X               ; <i32> [#uses=1]
         ret i32 %V
 }
 
diff --git a/test/Transforms/GlobalOpt/blockaddress.ll b/test/Transforms/GlobalOpt/blockaddress.ll
index f7f830869b84..12e09fcd4815 100644
--- a/test/Transforms/GlobalOpt/blockaddress.ll
+++ b/test/Transforms/GlobalOpt/blockaddress.ll
@@ -13,6 +13,9 @@ define void @f() {
 }
 
 define void @g() {
+entry:
+  br label %here
+
 ; CHECK-LABEL: @g(
 
 here:
diff --git a/test/Transforms/GlobalOpt/constantexpr-dangle.ll b/test/Transforms/GlobalOpt/constantexpr-dangle.ll
index be13a9811898..fbbfe69c15ab 100644
--- a/test/Transforms/GlobalOpt/constantexpr-dangle.ll
+++ b/test/Transforms/GlobalOpt/constantexpr-dangle.ll
@@ -6,7 +6,7 @@ define internal float @foo() {
 }
 
 define float @bar() {
-        %tmp1 = call float (...)* bitcast (float ()* @foo to float (...)*)( )
+        %tmp1 = call float (...) bitcast (float ()* @foo to float (...)*)( )
         %tmp2 = fmul float %tmp1, 1.000000e+01           ; <float> [#uses=1]
         ret float %tmp2
 }
diff --git a/test/Transforms/GlobalOpt/constantfold-initializers.ll b/test/Transforms/GlobalOpt/constantfold-initializers.ll
index 36de19c1cd84..d0c18812cd94 100644
--- a/test/Transforms/GlobalOpt/constantfold-initializers.ll
+++ b/test/Transforms/GlobalOpt/constantfold-initializers.ll
@@ -5,7 +5,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 @.str91250 = global [3 x i8] zeroinitializer
 
 ; CHECK: @A = global i1 false
-@A = global i1 icmp ne (i64 sub nsw (i64 ptrtoint (i8* getelementptr inbounds ([3 x i8]* @.str91250, i64 0, i64 1) to i64), i64 ptrtoint ([3 x i8]* @.str91250 to i64)), i64 1)
+@A = global i1 icmp ne (i64 sub nsw (i64 ptrtoint (i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str91250, i64 0, i64 1) to i64), i64 ptrtoint ([3 x i8]* @.str91250 to i64)), i64 1)
 
 ; PR11352
 
@@ -15,13 +15,13 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; PR12642
 %PR12642.struct = type { i8 }
 @PR12642.s = global <{}> zeroinitializer, align 1
-@PR12642.p = constant %PR12642.struct* bitcast (i8* getelementptr (i8* bitcast (<{}>* @PR12642.s to i8*), i64 1) to %PR12642.struct*), align 8
+@PR12642.p = constant %PR12642.struct* bitcast (i8* getelementptr (i8, i8* bitcast (<{}>* @PR12642.s to i8*), i64 1) to %PR12642.struct*), align 8
 
 define internal void @test1() {
 entry:
-  store i32 1, i32* getelementptr inbounds ([2 x i32]* @xs, i64 0, i64 0)
-  %0 = load i32* getelementptr inbounds ([2 x i32]* @xs, i32 0, i64 0), align 4
-  store i32 %0, i32* getelementptr inbounds ([2 x i32]* @xs, i64 0, i64 1)
+  store i32 1, i32* getelementptr inbounds ([2 x i32], [2 x i32]* @xs, i64 0, i64 0)
+  %0 = load i32, i32* getelementptr inbounds ([2 x i32], [2 x i32]* @xs, i32 0, i64 0), align 4
+  store i32 %0, i32* getelementptr inbounds ([2 x i32], [2 x i32]* @xs, i64 0, i64 1)
   ret void
 }
 
@@ -36,15 +36,15 @@ entry:
 
 define internal i32 @test2_helper(%closure* %this, i32 %b) {
 entry:
-  %0 = getelementptr inbounds %closure* %this, i32 0, i32 0
-  %1 = load i32* %0, align 4
+  %0 = getelementptr inbounds %closure, %closure* %this, i32 0, i32 0
+  %1 = load i32, i32* %0, align 4
   %add = add nsw i32 %1, %b
   ret i32 %add
 }
 
 define internal void @test2() {
 entry:
-  store i32 4, i32* getelementptr inbounds (%closure* @f, i32 0, i32 0)
+  store i32 4, i32* getelementptr inbounds (%closure, %closure* @f, i32 0, i32 0)
   %call = call i32 @test2_helper(%closure* @f, i32 9)
   store i32 %call, i32* @m, align 4
   ret void
@@ -85,7 +85,7 @@ entry:
 @test6_v2 = global i32 0, align 4
 ; CHECK: @test6_v2 = global i32 42, align 4
 define internal void @test6() {
-  %load = load { i32, i32 }* @test6_v1, align 8
+  %load = load { i32, i32 }, { i32, i32 }* @test6_v1, align 8
   %xv0 = extractvalue { i32, i32 } %load, 0
   %iv = insertvalue { i32, i32 } %load, i32 %xv0, 1
   %xv1 = extractvalue { i32, i32 } %iv, 1
diff --git a/test/Transforms/GlobalOpt/crash-2.ll b/test/Transforms/GlobalOpt/crash-2.ll
index 684f6cee180b..748fb027c7d7 100644
--- a/test/Transforms/GlobalOpt/crash-2.ll
+++ b/test/Transforms/GlobalOpt/crash-2.ll
@@ -11,9 +11,9 @@
 @g_71 = internal global %struct.S0.1.7.13 { i8 1, i8 -93, i8 58, i8 -1, i16 -5, [2 x i8] undef }, align 4
 @g_114 = external global i8, align 1
 @g_30 = external global { i32, i8, i32, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }, align 4
-@g_271 = internal global [7 x [6 x [5 x i8*]]] [[6 x [5 x i8*]] [[5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* null], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114, i8* @g_114, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* null, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* null, i8* null], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* null, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25, i8* @g_114, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0)]], [6 x [5 x i8*]] [[5 x i8*] [i8* @g_25, i8* null, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* @g_25, i8* @g_114, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25], [5 x i8*] [i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* @g_25, i8* @g_25, i8* @g_25], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0)]], [6 x [5 x i8*]] [[5 x i8*] [i8* null, i8* @g_25, i8* @g_25, i8* @g_25, i8* null], [5 x i8*] [i8* @g_25, i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1)], [5 x i8*] [i8* null, i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* null, i8* @g_25], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1)], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* null, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* null], [5 x i8*] [i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0)]], [6 x [5 x i8*]] [[5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* null, i8* @g_25], [5 x i8*] [i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* @g_25, i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* @g_25], [5 x i8*] [i8* @g_114, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* @g_114, i8* @g_25, i8* @g_25, i8* @g_114, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0)]], [6 x [5 x i8*]] [[5 x i8*] [i8* @g_25, i8* null, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* @g_25], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1)], [5 x i8*] [i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25, i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1)], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_114], [5 x i8*] [i8* @g_25, i8* null, i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* null], [5 x i8*] [i8* @g_114, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114, i8* @g_25]], [6 x [5 x i8*]] [[5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* null, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* null, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1)], [5 x i8*] [i8* @g_114, i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25]], [6 x [5 x i8*]] [[5 x i8*] [i8* @g_25, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* null], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114, i8* @g_25, i8* @g_25, i8* @g_114], [5 x i8*] [i8* null, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* null, i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1)], [5 x i8*] [i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_114, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114, i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1)], [5 x i8*] [i8* @g_25, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25], [5 x i8*] [i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25, i8* @g_25, i8* getelementptr (i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25]]], align 4
+@g_271 = internal global [7 x [6 x [5 x i8*]]] [[6 x [5 x i8*]] [[5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* null], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114, i8* @g_114, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* null, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* null, i8* null], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* null, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25, i8* @g_114, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0)]], [6 x [5 x i8*]] [[5 x i8*] [i8* @g_25, i8* null, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* @g_25, i8* @g_114, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25], [5 x i8*] [i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* @g_25, i8* @g_25, i8* @g_25], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0)]], [6 x [5 x i8*]] [[5 x i8*] [i8* null, i8* @g_25, i8* @g_25, i8* @g_25, i8* null], [5 x i8*] [i8* @g_25, i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1)], [5 x i8*] [i8* null, i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* null, i8* @g_25], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1)], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* null, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* null], [5 x i8*] [i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0)]], [6 x [5 x i8*]] [[5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* null, i8* @g_25], [5 x i8*] [i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* @g_25, i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* @g_25], [5 x i8*] [i8* @g_114, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* @g_114, i8* @g_25, i8* @g_25, i8* @g_114, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0)]], [6 x [5 x i8*]] [[5 x i8*] [i8* @g_25, i8* null, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* @g_25], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1)], [5 x i8*] [i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25, i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1)], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_114], [5 x i8*] [i8* @g_25, i8* null, i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* null], [5 x i8*] [i8* @g_114, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114, i8* @g_25]], [6 x [5 x i8*]] [[5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* null, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* null, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1)], [5 x i8*] [i8* @g_114, i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0)], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25]], [6 x [5 x i8*]] [[5 x i8*] [i8* @g_25, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* null], [5 x i8*] [i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114, i8* @g_25, i8* @g_25, i8* @g_114], [5 x i8*] [i8* null, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_25, i8* null, i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1)], [5 x i8*] [i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_114, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* @g_114, i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1)], [5 x i8*] [i8* @g_25, i8* @g_25, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25], [5 x i8*] [i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25, i8* @g_25, i8* getelementptr (i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i64 1), i8* @g_25]]], align 4
 
 define i32 @func() {
-  %tmp = load i8* getelementptr inbounds (%struct.S0.1.7.13* @g_71, i32 0, i32 0), align 1
+  %tmp = load i8, i8* getelementptr inbounds (%struct.S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), align 1
   ret i32 0
 }
diff --git a/test/Transforms/GlobalOpt/crash.ll b/test/Transforms/GlobalOpt/crash.ll
index 80c777ccabc1..8e39931c8525 100644
--- a/test/Transforms/GlobalOpt/crash.ll
+++ b/test/Transforms/GlobalOpt/crash.ll
@@ -11,7 +11,7 @@ target triple = "i386-apple-darwin9.8"
 
 define internal void @_GLOBAL__I__ZN21btConeTwistConstraintC2Ev() nounwind section "__TEXT,__StaticInit,regular,pure_instructions" {
 entry:
-  store float 1.0, float* getelementptr inbounds (%struct.btSimdScalar* @_ZL6vTwist, i32 0, i32 0, i32 0, i32 3), align 4
+  store float 1.0, float* getelementptr inbounds (%struct.btSimdScalar, %struct.btSimdScalar* @_ZL6vTwist, i32 0, i32 0, i32 0, i32 3), align 4
   ret void
 }
 
@@ -31,11 +31,11 @@ entry:
   unreachable
 
 bb.nph.i: 
-  %scevgep.i539 = getelementptr i8* %C, i64 4
+  %scevgep.i539 = getelementptr i8, i8* %C, i64 4
   unreachable
 
 xx:
-  %E = load %T** @switch_inf, align 8 
+  %E = load %T*, %T** @switch_inf, align 8 
   unreachable
 }
 
@@ -46,7 +46,7 @@ declare noalias i8* @malloc(i64) nounwind
 @permute_bitrev.bitrev = internal global i32* null, align 8
 define void @permute_bitrev() nounwind {
 entry:
-  %tmp = load i32** @permute_bitrev.bitrev, align 8
+  %tmp = load i32*, i32** @permute_bitrev.bitrev, align 8
   %conv = sext i32 0 to i64
   %mul = mul i64 %conv, 4
   %call = call i8* @malloc(i64 %mul)
@@ -60,7 +60,7 @@ entry:
 
 @data8 = internal global [8000 x i8] zeroinitializer, align 16
 define void @memset_with_strange_user() ssp {
-  call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds ([8000 x i8]* @data8, i64 0, i64 0), i8 undef, i64 ptrtoint (i8* getelementptr ([8000 x i8]* @data8, i64 1, i64 sub (i64 0, i64 ptrtoint ([8000 x i8]* @data8 to i64))) to i64), i32 16, i1 false)
+  call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds ([8000 x i8], [8000 x i8]* @data8, i64 0, i64 0), i8 undef, i64 ptrtoint (i8* getelementptr ([8000 x i8], [8000 x i8]* @data8, i64 1, i64 sub (i64 0, i64 ptrtoint ([8000 x i8]* @data8 to i64))) to i64), i32 16, i1 false)
   ret void
 }
 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
@@ -72,7 +72,7 @@ declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
 
 define void @icmp_user_of_stored_once() nounwind ssp {
 entry:
-  %tmp4 = load i32*** @g_52, align 8
+  %tmp4 = load i32**, i32*** @g_52, align 8
   store i32** @g_90, i32*** @g_52
   %cmp17 = icmp ne i32*** undef, @g_52
   ret void
diff --git a/test/Transforms/GlobalOpt/ctor-list-opt-constexpr.ll b/test/Transforms/GlobalOpt/ctor-list-opt-constexpr.ll
index dd86f01924a5..0c3ff68a437e 100644
--- a/test/Transforms/GlobalOpt/ctor-list-opt-constexpr.ll
+++ b/test/Transforms/GlobalOpt/ctor-list-opt-constexpr.ll
@@ -16,7 +16,7 @@ target triple = "x86_64-apple-darwin10.0.0"
 ; arbitrary constant expression, the code generator can't handle it.
 define internal void @init1() {
 entry:
-  %tmp = getelementptr inbounds %struct.foo* @X, i32 0, i32 0
+  %tmp = getelementptr inbounds %struct.foo, %struct.foo* @X, i32 0, i32 0
   store i32* inttoptr (i64 sdiv (i64 ptrtoint (i32* @G to i64), i64 ptrtoint (i32* @H to i64)) to i32*), i32** %tmp, align 8
   ret void
 }
@@ -26,7 +26,7 @@ entry:
 ; PR11705 - ptrtoint isn't safe in general in global initializers.
 define internal void @init2() {
 entry:
-  %tmp = getelementptr inbounds %struct.bar* @X2, i32 0, i32 0
+  %tmp = getelementptr inbounds %struct.bar, %struct.bar* @X2, i32 0, i32 0
   store i128 ptrtoint (i32* @G to i128), i128* %tmp, align 16
   ret void
 }
diff --git a/test/Transforms/GlobalOpt/ctor-list-opt-inbounds.ll b/test/Transforms/GlobalOpt/ctor-list-opt-inbounds.ll
index 9b11985693a1..63dc783ae196 100644
--- a/test/Transforms/GlobalOpt/ctor-list-opt-inbounds.ll
+++ b/test/Transforms/GlobalOpt/ctor-list-opt-inbounds.ll
@@ -13,11 +13,11 @@
 @I = global i32 90
 
 define internal void @CTOR() {
-  store i32 1, i32* getelementptr ([6 x [5 x i32]]* @G, i64 0, i64 0, i64 0)
-  store i32 2, i32* getelementptr inbounds ([6 x [5 x i32]]* @G, i64 0, i64 0, i64 0)
-  %t = load i32* getelementptr ([6 x [5 x i32]]* @G, i64 0, i64 0, i64 0)
+  store i32 1, i32* getelementptr ([6 x [5 x i32]], [6 x [5 x i32]]* @G, i64 0, i64 0, i64 0)
+  store i32 2, i32* getelementptr inbounds ([6 x [5 x i32]], [6 x [5 x i32]]* @G, i64 0, i64 0, i64 0)
+  %t = load i32, i32* getelementptr ([6 x [5 x i32]], [6 x [5 x i32]]* @G, i64 0, i64 0, i64 0)
   store i32 %t, i32* @H
-  %s = load i32* getelementptr inbounds ([6 x [5 x i32]]* @G, i64 0, i64 0, i64 0)
+  %s = load i32, i32* getelementptr inbounds ([6 x [5 x i32]], [6 x [5 x i32]]* @G, i64 0, i64 0, i64 0)
   store i32 %s, i32* @I
   ret void
 }
diff --git a/test/Transforms/GlobalOpt/ctor-list-opt.ll b/test/Transforms/GlobalOpt/ctor-list-opt.ll
index 450bdb830284..95e7d4d1ab5b 100644
--- a/test/Transforms/GlobalOpt/ctor-list-opt.ll
+++ b/test/Transforms/GlobalOpt/ctor-list-opt.ll
@@ -51,16 +51,16 @@ T:		; preds = %Cont
 }
 
 define internal void @CTOR4() {
-	%X = load i32* @G3		; <i32> [#uses=1]
+	%X = load i32, i32* @G3		; <i32> [#uses=1]
 	%Y = add i32 %X, 123		; <i32> [#uses=1]
 	store i32 %Y, i32* @G3
 	ret void
 }
 
 define internal void @CTOR5() {
-	%X.2p = getelementptr inbounds { i32, [2 x i32] }* @X, i32 0, i32 1, i32 0		; <i32*> [#uses=2]
-	%X.2 = load i32* %X.2p		; <i32> [#uses=1]
-	%X.1p = getelementptr inbounds { i32, [2 x i32] }* @X, i32 0, i32 0		; <i32*> [#uses=1]
+	%X.2p = getelementptr inbounds { i32, [2 x i32] }, { i32, [2 x i32] }* @X, i32 0, i32 1, i32 0		; <i32*> [#uses=2]
+	%X.2 = load i32, i32* %X.2p		; <i32> [#uses=1]
+	%X.1p = getelementptr inbounds { i32, [2 x i32] }, { i32, [2 x i32] }* @X, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 %X.2, i32* %X.1p
 	store i32 42, i32* %X.2p
 	ret void
@@ -68,9 +68,9 @@ define internal void @CTOR5() {
 
 define internal void @CTOR6() {
 	%A = alloca i32		; <i32*> [#uses=2]
-	%y = load i32* @Y		; <i32> [#uses=1]
+	%y = load i32, i32* @Y		; <i32> [#uses=1]
 	store i32 %y, i32* %A
-	%Av = load i32* %A		; <i32> [#uses=1]
+	%Av = load i32, i32* %A		; <i32> [#uses=1]
 	%Av1 = add i32 %Av, 1		; <i32> [#uses=1]
 	store i32 %Av1, i32* @Y
 	ret void
@@ -95,7 +95,7 @@ define internal void @CTOR8() {
 }
 
 define i1 @accessor() {
-	%V = load i1* @CTORGV		; <i1> [#uses=1]
+	%V = load i1, i1* @CTORGV		; <i1> [#uses=1]
 	ret i1 %V
 }
 
@@ -107,9 +107,9 @@ define i1 @accessor() {
 define internal void @CTOR9() {
 entry:
   %0 = bitcast %struct.B* @GV1 to i8*
-  %1 = getelementptr inbounds i8* %0, i64 16
+  %1 = getelementptr inbounds i8, i8* %0, i64 16
   %2 = bitcast i8* %1 to %struct.A*
   %3 = bitcast %struct.B* @GV1 to i8***
-  store i8** getelementptr inbounds ([3 x i8*]* @GV2, i64 1, i64 0), i8*** %3
+  store i8** getelementptr inbounds ([3 x i8*], [3 x i8*]* @GV2, i64 1, i64 0), i8*** %3
   ret void
 }
diff --git a/test/Transforms/GlobalOpt/cxx-dtor.ll b/test/Transforms/GlobalOpt/cxx-dtor.ll
index 7c6ae78d1bc0..c94c26b53485 100644
--- a/test/Transforms/GlobalOpt/cxx-dtor.ll
+++ b/test/Transforms/GlobalOpt/cxx-dtor.ll
@@ -11,7 +11,7 @@
 ; CHECK-NOT: call i32 @__cxa_atexit
 
 define internal void @__cxx_global_var_init() nounwind section "__TEXT,__StaticInit,regular,pure_instructions" {
-  %1 = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.A*)* @_ZN1AD1Ev to void (i8*)*), i8* getelementptr inbounds (%struct.A* @a, i32 0, i32 0), i8* bitcast (i8** @__dso_handle to i8*))
+  %1 = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.A*)* @_ZN1AD1Ev to void (i8*)*), i8* getelementptr inbounds (%struct.A, %struct.A* @a, i32 0, i32 0), i8* bitcast (i8** @__dso_handle to i8*))
   ret void
 }
 
diff --git a/test/Transforms/GlobalOpt/deadfunction.ll b/test/Transforms/GlobalOpt/deadfunction.ll
index 5e003c63f77d..5771c4ccfb75 100644
--- a/test/Transforms/GlobalOpt/deadfunction.ll
+++ b/test/Transforms/GlobalOpt/deadfunction.ll
@@ -10,8 +10,8 @@ declare void @bb()
 define internal void @test(i32 %n) nounwind noinline {
 entry:
   %idxprom = sext i32 %n to i64
-  %arrayidx = getelementptr inbounds [3 x i8*]* @test.x, i64 0, i64 %idxprom
-  %0 = load i8** %arrayidx, align 8
+  %arrayidx = getelementptr inbounds [3 x i8*], [3 x i8*]* @test.x, i64 0, i64 %idxprom
+  %0 = load i8*, i8** %arrayidx, align 8
   indirectbr i8* %0, [label %a, label %b, label %c]
 
 a:
diff --git a/test/Transforms/GlobalOpt/deadglobal-2.ll b/test/Transforms/GlobalOpt/deadglobal-2.ll
index 4f8181983094..6b8717ee1831 100644
--- a/test/Transforms/GlobalOpt/deadglobal-2.ll
+++ b/test/Transforms/GlobalOpt/deadglobal-2.ll
@@ -5,7 +5,7 @@
 @G = internal global [4 x i32] zeroinitializer
 
 define void @foo(i32 %X) {
-	%Ptr = getelementptr [4 x i32]* @G, i32 0, i32 %X
+	%Ptr = getelementptr [4 x i32], [4 x i32]* @G, i32 0, i32 %X
 	store i32 1, i32* %Ptr
 	ret void
 }
diff --git a/test/Transforms/GlobalOpt/externally-initialized-global-ctr.ll b/test/Transforms/GlobalOpt/externally-initialized-global-ctr.ll
index 675211b64b46..2e22ff064444 100644
--- a/test/Transforms/GlobalOpt/externally-initialized-global-ctr.ll
+++ b/test/Transforms/GlobalOpt/externally-initialized-global-ctr.ll
@@ -7,14 +7,14 @@
 @_ZL14buttonInitData = internal global [1 x %struct.ButtonInitData] zeroinitializer, align 4
 
 @"\01L_OBJC_METH_VAR_NAME_40" = internal global [7 x i8] c"print:\00", section "__TEXT,__objc_methname,cstring_literals", align 1
-@"\01L_OBJC_SELECTOR_REFERENCES_41" = internal externally_initialized  global i8* getelementptr inbounds ([7 x i8]* @"\01L_OBJC_METH_VAR_NAME_40", i32 0, i32 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
+@"\01L_OBJC_SELECTOR_REFERENCES_41" = internal externally_initialized  global i8* getelementptr inbounds ([7 x i8], [7 x i8]* @"\01L_OBJC_METH_VAR_NAME_40", i32 0, i32 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
 
 @llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }]
-@llvm.used = appending global [2 x i8*] [i8* getelementptr inbounds ([7 x i8]* @"\01L_OBJC_METH_VAR_NAME_40", i32 0, i32 0),  i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_41" to i8*)]
+@llvm.used = appending global [2 x i8*] [i8* getelementptr inbounds ([7 x i8], [7 x i8]* @"\01L_OBJC_METH_VAR_NAME_40", i32 0, i32 0),  i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_41" to i8*)]
 
 define internal void @__cxx_global_var_init() section "__TEXT,__StaticInit,regular,pure_instructions" {
-  %1 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_41", !invariant.load !2009
-  store i8* %1, i8** getelementptr inbounds ([1 x %struct.ButtonInitData]* @_ZL14buttonInitData, i32 0, i32 0, i32 0), align 4
+  %1 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_41", !invariant.load !2009
+  store i8* %1, i8** getelementptr inbounds ([1 x %struct.ButtonInitData], [1 x %struct.ButtonInitData]* @_ZL14buttonInitData, i32 0, i32 0, i32 0), align 4
   ret void
 }
 
@@ -26,8 +26,8 @@ define internal void @_GLOBAL__I_a() section "__TEXT,__StaticInit,regular,pure_i
 declare void @test(i8*)
 
 define void @print() {
-; CHECK: %1 = load i8** getelementptr inbounds ([1 x %struct.ButtonInitData]* @_ZL14buttonInitData, i32 0, i32 0, i32 0), align 4
-  %1 = load i8** getelementptr inbounds ([1 x %struct.ButtonInitData]* @_ZL14buttonInitData, i32 0, i32 0, i32 0), align 4
+; CHECK: %1 = load i8*, i8** @_ZL14buttonInitData.0.0, align 4
+  %1 = load i8*, i8** getelementptr inbounds ([1 x %struct.ButtonInitData], [1 x %struct.ButtonInitData]* @_ZL14buttonInitData, i32 0, i32 0, i32 0), align 4
   call void @test(i8* %1)
   ret void
 }
diff --git a/test/Transforms/GlobalOpt/fastcc.ll b/test/Transforms/GlobalOpt/fastcc.ll
index 76122b203d79..26398d2bb900 100644
--- a/test/Transforms/GlobalOpt/fastcc.ll
+++ b/test/Transforms/GlobalOpt/fastcc.ll
@@ -2,13 +2,13 @@
 
 define internal i32 @f(i32* %m) {
 ; CHECK-LABEL: define internal fastcc i32 @f
-  %v = load i32* %m
+  %v = load i32, i32* %m
   ret i32 %v
 }
 
 define internal x86_thiscallcc i32 @g(i32* %m) {
 ; CHECK-LABEL: define internal fastcc i32 @g
-  %v = load i32* %m
+  %v = load i32, i32* %m
   ret i32 %v
 }
 
@@ -16,13 +16,13 @@ define internal x86_thiscallcc i32 @g(i32* %m) {
 ; convention.
 define internal coldcc i32 @h(i32* %m) {
 ; CHECK-LABEL: define internal coldcc i32 @h
-  %v = load i32* %m
+  %v = load i32, i32* %m
   ret i32 %v
 }
 
 define internal i32 @j(i32* %m) {
 ; CHECK-LABEL: define internal i32 @j
-  %v = load i32* %m
+  %v = load i32, i32* %m
   ret i32 %v
 }
 
diff --git a/test/Transforms/GlobalOpt/globalsra-partial.ll b/test/Transforms/GlobalOpt/globalsra-partial.ll
index 06485b53e0eb..9abcce6f4931 100644
--- a/test/Transforms/GlobalOpt/globalsra-partial.ll
+++ b/test/Transforms/GlobalOpt/globalsra-partial.ll
@@ -6,19 +6,19 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1
 @G = internal global { i32, [4 x float] } zeroinitializer               ; <{ i32, [4 x float] }*> [#uses=3]
 
 define void @onlystore() {
-        store i32 12345, i32* getelementptr ({ i32, [4 x float] }* @G, i32 0, i32 0)
+        store i32 12345, i32* getelementptr ({ i32, [4 x float] }, { i32, [4 x float] }* @G, i32 0, i32 0)
         ret void
 }
 
 define void @storeinit(i32 %i) {
-        %Ptr = getelementptr { i32, [4 x float] }* @G, i32 0, i32 1, i32 %i             ; <float*> [#uses=1]
+        %Ptr = getelementptr { i32, [4 x float] }, { i32, [4 x float] }* @G, i32 0, i32 1, i32 %i             ; <float*> [#uses=1]
         store float 1.000000e+00, float* %Ptr
         ret void
 }
 
 define float @readval(i32 %i) {
-        %Ptr = getelementptr { i32, [4 x float] }* @G, i32 0, i32 1, i32 %i             ; <float*> [#uses=1]
-        %V = load float* %Ptr           ; <float> [#uses=1]
+        %Ptr = getelementptr { i32, [4 x float] }, { i32, [4 x float] }* @G, i32 0, i32 1, i32 %i             ; <float*> [#uses=1]
+        %V = load float, float* %Ptr           ; <float> [#uses=1]
         ret float %V
 }
 
diff --git a/test/Transforms/GlobalOpt/globalsra-unknown-index.ll b/test/Transforms/GlobalOpt/globalsra-unknown-index.ll
index cc655e9a2d1d..5194b2ca7413 100644
--- a/test/Transforms/GlobalOpt/globalsra-unknown-index.ll
+++ b/test/Transforms/GlobalOpt/globalsra-unknown-index.ll
@@ -12,30 +12,30 @@
 @addr = external global i8
 
 define void @frob() {
-  store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 ptrtoint (i8* @addr to i64)), align 4
+  store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 ptrtoint (i8* @addr to i64)), align 4
   ret void
 }
 define i32 @borf(i64 %i, i64 %j) {
-  %p = getelementptr inbounds [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 0
-  %a = load i32* %p
-  %q = getelementptr inbounds [3 x %struct.X]* @Y, i64 0, i64 0, i32 1, i64 0
-  %b = load i32* %q
+  %p = getelementptr inbounds [3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 0
+  %a = load i32, i32* %p
+  %q = getelementptr inbounds [3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 1, i64 0
+  %b = load i32, i32* %q
   %c = add i32 %a, %b
   ret i32 %c
 }
 define i32 @borg(i64 %i, i64 %j) {
-  %p = getelementptr inbounds [3 x %struct.X]* @Y, i64 0, i64 1, i32 0, i64 1
-  %a = load i32* %p
-  %q = getelementptr inbounds [3 x %struct.X]* @Y, i64 0, i64 1, i32 1, i64 1
-  %b = load i32* %q
+  %p = getelementptr inbounds [3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 1, i32 0, i64 1
+  %a = load i32, i32* %p
+  %q = getelementptr inbounds [3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 1, i32 1, i64 1
+  %b = load i32, i32* %q
   %c = add i32 %a, %b
   ret i32 %c
 }
 define i32 @borh(i64 %i, i64 %j) {
-  %p = getelementptr inbounds [3 x %struct.X]* @Y, i64 0, i64 2, i32 0, i64 2
-  %a = load i32* %p
-  %q = getelementptr inbounds [3 x %struct.X]* @Y, i64 0, i64 2, i32 1, i64 2
-  %b = load i32* %q
+  %p = getelementptr inbounds [3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 2, i32 0, i64 2
+  %a = load i32, i32* %p
+  %q = getelementptr inbounds [3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 2, i32 1, i64 2
+  %b = load i32, i32* %q
   %c = add i32 %a, %b
   ret i32 %c
 }
diff --git a/test/Transforms/GlobalOpt/globalsra.ll b/test/Transforms/GlobalOpt/globalsra.ll
index 6d8f220d12b1..d593fcd9e15e 100644
--- a/test/Transforms/GlobalOpt/globalsra.ll
+++ b/test/Transforms/GlobalOpt/globalsra.ll
@@ -7,18 +7,18 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1
     { double } { double 1.727000e+01 } }                ; <{ i32, float, { double } }*> [#uses=3]
 
 define void @onlystore() {
-        store i32 123, i32* getelementptr ({ i32, float, { double } }* @G, i32 0, i32 0)
+        store i32 123, i32* getelementptr ({ i32, float, { double } }, { i32, float, { double } }* @G, i32 0, i32 0)
         ret void
 }
 
 define float @storeinit() {
-        store float 1.000000e+00, float* getelementptr ({ i32, float, { double } }* @G, i32 0, i32 1)
-        %X = load float* getelementptr ({ i32, float, { double } }* @G, i32 0, i32 1)           ; <float> [#uses=1]
+        store float 1.000000e+00, float* getelementptr ({ i32, float, { double } }, { i32, float, { double } }* @G, i32 0, i32 1)
+        %X = load float, float* getelementptr ({ i32, float, { double } }, { i32, float, { double } }* @G, i32 0, i32 1)           ; <float> [#uses=1]
         ret float %X
 }
 
 define double @constantize() {
-        %X = load double* getelementptr ({ i32, float, { double } }* @G, i32 0, i32 2, i32 0)           ; <double> [#uses=1]
+        %X = load double, double* getelementptr ({ i32, float, { double } }, { i32, float, { double } }* @G, i32 0, i32 2, i32 0)           ; <double> [#uses=1]
         ret double %X
 }
 
diff --git a/test/Transforms/GlobalOpt/heap-sra-1.ll b/test/Transforms/GlobalOpt/heap-sra-1.ll
index 9d5148f9be6f..6035eaaefccd 100644
--- a/test/Transforms/GlobalOpt/heap-sra-1.ll
+++ b/test/Transforms/GlobalOpt/heap-sra-1.ll
@@ -19,14 +19,14 @@ declare noalias i8* @malloc(i64)
 
 define i32 @baz() nounwind readonly noinline {
 bb1.thread:
-	%0 = load %struct.foo** @X, align 4		
+	%0 = load %struct.foo*, %struct.foo** @X, align 4		
 	br label %bb1
 
 bb1:		; preds = %bb1, %bb1.thread
 	%i.0.reg2mem.0 = phi i32 [ 0, %bb1.thread ], [ %indvar.next, %bb1 ]
 	%sum.0.reg2mem.0 = phi i32 [ 0, %bb1.thread ], [ %3, %bb1 ]
-	%1 = getelementptr %struct.foo* %0, i32 %i.0.reg2mem.0, i32 0
-	%2 = load i32* %1, align 4
+	%1 = getelementptr %struct.foo, %struct.foo* %0, i32 %i.0.reg2mem.0, i32 0
+	%2 = load i32, i32* %1, align 4
 	%3 = add i32 %2, %sum.0.reg2mem.0	
 	%indvar.next = add i32 %i.0.reg2mem.0, 1	
 	%exitcond = icmp eq i32 %indvar.next, 1200		
diff --git a/test/Transforms/GlobalOpt/heap-sra-2.ll b/test/Transforms/GlobalOpt/heap-sra-2.ll
index fa8c36281ee9..d66c627b184c 100644
--- a/test/Transforms/GlobalOpt/heap-sra-2.ll
+++ b/test/Transforms/GlobalOpt/heap-sra-2.ll
@@ -10,7 +10,7 @@ define void @bar(i32 %Size) nounwind noinline {
 entry:
 	%malloccall = tail call i8* @malloc(i64 8000000) ; <i8*> [#uses=1]
 	%0 = bitcast i8* %malloccall to [1000000 x %struct.foo]* ; <[1000000 x %struct.foo]*> [#uses=1]
-	%.sub = getelementptr [1000000 x %struct.foo]* %0, i32 0, i32 0		; <%struct.foo*> [#uses=1]
+	%.sub = getelementptr [1000000 x %struct.foo], [1000000 x %struct.foo]* %0, i32 0, i32 0		; <%struct.foo*> [#uses=1]
 	store %struct.foo* %.sub, %struct.foo** @X, align 4
 	ret void
 }
@@ -19,14 +19,14 @@ declare noalias i8* @malloc(i64)
 
 define i32 @baz() nounwind readonly noinline {
 bb1.thread:
-	%0 = load %struct.foo** @X, align 4		; <%struct.foo*> [#uses=1]
+	%0 = load %struct.foo*, %struct.foo** @X, align 4		; <%struct.foo*> [#uses=1]
 	br label %bb1
 
 bb1:		; preds = %bb1, %bb1.thread
 	%i.0.reg2mem.0 = phi i32 [ 0, %bb1.thread ], [ %indvar.next, %bb1 ]		; <i32> [#uses=2]
 	%sum.0.reg2mem.0 = phi i32 [ 0, %bb1.thread ], [ %3, %bb1 ]		; <i32> [#uses=1]
-	%1 = getelementptr %struct.foo* %0, i32 %i.0.reg2mem.0, i32 0		; <i32*> [#uses=1]
-	%2 = load i32* %1, align 4		; <i32> [#uses=1]
+	%1 = getelementptr %struct.foo, %struct.foo* %0, i32 %i.0.reg2mem.0, i32 0		; <i32*> [#uses=1]
+	%2 = load i32, i32* %1, align 4		; <i32> [#uses=1]
 	%3 = add i32 %2, %sum.0.reg2mem.0		; <i32> [#uses=2]
 	%indvar.next = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=2]
 	%exitcond = icmp eq i32 %indvar.next, 1200		; <i1> [#uses=1]
diff --git a/test/Transforms/GlobalOpt/heap-sra-3.ll b/test/Transforms/GlobalOpt/heap-sra-3.ll
index e7a877cda446..6a34364b49fe 100644
--- a/test/Transforms/GlobalOpt/heap-sra-3.ll
+++ b/test/Transforms/GlobalOpt/heap-sra-3.ll
@@ -20,14 +20,14 @@ declare noalias i8* @malloc(i64)
 
 define i32 @baz() nounwind readonly noinline {
 bb1.thread:
-	%0 = load %struct.foo** @X, align 4		
+	%0 = load %struct.foo*, %struct.foo** @X, align 4		
 	br label %bb1
 
 bb1:		; preds = %bb1, %bb1.thread
 	%i.0.reg2mem.0 = phi i32 [ 0, %bb1.thread ], [ %indvar.next, %bb1 ]
 	%sum.0.reg2mem.0 = phi i32 [ 0, %bb1.thread ], [ %3, %bb1 ]
-	%1 = getelementptr %struct.foo* %0, i32 %i.0.reg2mem.0, i32 0
-	%2 = load i32* %1, align 4
+	%1 = getelementptr %struct.foo, %struct.foo* %0, i32 %i.0.reg2mem.0, i32 0
+	%2 = load i32, i32* %1, align 4
 	%3 = add i32 %2, %sum.0.reg2mem.0	
 	%indvar.next = add i32 %i.0.reg2mem.0, 1	
 	%exitcond = icmp eq i32 %indvar.next, 1200		
diff --git a/test/Transforms/GlobalOpt/heap-sra-4.ll b/test/Transforms/GlobalOpt/heap-sra-4.ll
index d5a58288e1a2..2176b9fcbee2 100644
--- a/test/Transforms/GlobalOpt/heap-sra-4.ll
+++ b/test/Transforms/GlobalOpt/heap-sra-4.ll
@@ -20,14 +20,14 @@ declare noalias i8* @malloc(i64)
 
 define i32 @baz() nounwind readonly noinline {
 bb1.thread:
-	%0 = load %struct.foo** @X, align 4		
+	%0 = load %struct.foo*, %struct.foo** @X, align 4		
 	br label %bb1
 
 bb1:		; preds = %bb1, %bb1.thread
 	%i.0.reg2mem.0 = phi i32 [ 0, %bb1.thread ], [ %indvar.next, %bb1 ]
 	%sum.0.reg2mem.0 = phi i32 [ 0, %bb1.thread ], [ %3, %bb1 ]
-	%1 = getelementptr %struct.foo* %0, i32 %i.0.reg2mem.0, i32 0
-	%2 = load i32* %1, align 4
+	%1 = getelementptr %struct.foo, %struct.foo* %0, i32 %i.0.reg2mem.0, i32 0
+	%2 = load i32, i32* %1, align 4
 	%3 = add i32 %2, %sum.0.reg2mem.0	
 	%indvar.next = add i32 %i.0.reg2mem.0, 1	
 	%exitcond = icmp eq i32 %indvar.next, 1200		
diff --git a/test/Transforms/GlobalOpt/heap-sra-phi.ll b/test/Transforms/GlobalOpt/heap-sra-phi.ll
index 123ad851f717..bf9ca7b5311e 100644
--- a/test/Transforms/GlobalOpt/heap-sra-phi.ll
+++ b/test/Transforms/GlobalOpt/heap-sra-phi.ll
@@ -9,7 +9,7 @@ define void @bar(i32 %Size) nounwind noinline {
 entry:
 	%malloccall = tail call i8* @malloc(i64 8000000) ; <i8*> [#uses=1]
 	%tmp = bitcast i8* %malloccall to [1000000 x %struct.foo]* ; <[1000000 x %struct.foo]*> [#uses=1]
-	%.sub = getelementptr [1000000 x %struct.foo]* %tmp, i32 0, i32 0		; <%struct.foo*> [#uses=1]
+	%.sub = getelementptr [1000000 x %struct.foo], [1000000 x %struct.foo]* %tmp, i32 0, i32 0		; <%struct.foo*> [#uses=1]
 	store %struct.foo* %.sub, %struct.foo** @X, align 4
 	ret void
 }
@@ -18,22 +18,22 @@ declare noalias i8* @malloc(i64)
 
 define i32 @baz() nounwind readonly noinline {
 bb1.thread:
-	%tmpLD1 = load %struct.foo** @X, align 4		; <%struct.foo*> [#uses=1]
+	%tmpLD1 = load %struct.foo*, %struct.foo** @X, align 4		; <%struct.foo*> [#uses=1]
 	br label %bb1
 
 bb1:		; preds = %bb1, %bb1.thread
         %tmp = phi %struct.foo* [%tmpLD1, %bb1.thread ], [ %tmpLD2, %bb1 ]		; <i32> [#uses=2]
 	%i.0.reg2mem.0 = phi i32 [ 0, %bb1.thread ], [ %indvar.next, %bb1 ]		; <i32> [#uses=2]
 	%sum.0.reg2mem.0 = phi i32 [ 0, %bb1.thread ], [ %tmp3, %bb1 ]		; <i32> [#uses=1]
-	%tmp1 = getelementptr %struct.foo* %tmp, i32 %i.0.reg2mem.0, i32 0		; <i32*> [#uses=1]
-	%tmp2 = load i32* %tmp1, align 4		; <i32> [#uses=1]
+	%tmp1 = getelementptr %struct.foo, %struct.foo* %tmp, i32 %i.0.reg2mem.0, i32 0		; <i32*> [#uses=1]
+	%tmp2 = load i32, i32* %tmp1, align 4		; <i32> [#uses=1]
 	%tmp6 = add i32 %tmp2, %sum.0.reg2mem.0		; <i32> [#uses=2]
-	%tmp4 = getelementptr %struct.foo* %tmp, i32 %i.0.reg2mem.0, i32 1		; <i32*> [#uses=1]
-        %tmp5 = load i32 * %tmp4
+	%tmp4 = getelementptr %struct.foo, %struct.foo* %tmp, i32 %i.0.reg2mem.0, i32 1		; <i32*> [#uses=1]
+        %tmp5 = load i32 , i32 * %tmp4
         %tmp3 = add i32 %tmp5, %tmp6
 	%indvar.next = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=2]
         
-      	%tmpLD2 = load %struct.foo** @X, align 4		; <%struct.foo*> [#uses=1]
+      	%tmpLD2 = load %struct.foo*, %struct.foo** @X, align 4		; <%struct.foo*> [#uses=1]
 
 	%exitcond = icmp eq i32 %indvar.next, 1200		; <i1> [#uses=1]
 	br i1 %exitcond, label %bb2, label %bb1
diff --git a/test/Transforms/GlobalOpt/integer-bool.ll b/test/Transforms/GlobalOpt/integer-bool.ll
index abf5fdd2ef3c..617febdc0166 100644
--- a/test/Transforms/GlobalOpt/integer-bool.ll
+++ b/test/Transforms/GlobalOpt/integer-bool.ll
@@ -20,7 +20,7 @@ define void @set2() {
 
 define i1 @get() {
 ; CHECK-LABEL: @get(
-  %A = load i32 addrspace(1) * @G
+  %A = load i32, i32 addrspace(1) * @G
   %C = icmp slt i32 %A, 2
   ret i1 %C
 ; CHECK: ret i1 true
diff --git a/test/Transforms/GlobalOpt/iterate.ll b/test/Transforms/GlobalOpt/iterate.ll
index 746687427590..f7f34fc39d9a 100644
--- a/test/Transforms/GlobalOpt/iterate.ll
+++ b/test/Transforms/GlobalOpt/iterate.ll
@@ -4,8 +4,8 @@
 @H = internal global { i32* } { i32* @G }               ; <{ i32* }*> [#uses=1]
 
 define i32 @loadg() {
-        %G = load i32** getelementptr ({ i32* }* @H, i32 0, i32 0)              ; <i32*> [#uses=1]
-        %GV = load i32* %G              ; <i32> [#uses=1]
+        %G = load i32*, i32** getelementptr ({ i32* }, { i32* }* @H, i32 0, i32 0)              ; <i32*> [#uses=1]
+        %GV = load i32, i32* %G              ; <i32> [#uses=1]
         ret i32 %GV
 }
 
diff --git a/test/Transforms/GlobalOpt/load-store-global.ll b/test/Transforms/GlobalOpt/load-store-global.ll
index ad7326dc682c..e01358e8ed38 100644
--- a/test/Transforms/GlobalOpt/load-store-global.ll
+++ b/test/Transforms/GlobalOpt/load-store-global.ll
@@ -4,7 +4,7 @@
 ; CHECK-NOT: @G
 
 define void @foo() {
-        %V = load i32* @G               ; <i32> [#uses=1]
+        %V = load i32, i32* @G               ; <i32> [#uses=1]
         store i32 %V, i32* @G
         ret void
 ; CHECK-LABEL: @foo(
@@ -12,7 +12,7 @@ define void @foo() {
 }
 
 define i32 @bar() {
-        %X = load i32* @G               ; <i32> [#uses=1]
+        %X = load i32, i32* @G               ; <i32> [#uses=1]
         ret i32 %X
 ; CHECK-LABEL: @bar(
 ; CHECK-NEXT: ret i32 17
@@ -24,12 +24,12 @@ define i32 @bar() {
 ; PR13968
 define void @qux() nounwind {
   %b = bitcast i64** @a to i8*
-  %g = getelementptr i64** @a, i32 1
+  %g = getelementptr i64*, i64** @a, i32 1
   %cmp = icmp ne i8* null, %b
   %cmp2 = icmp eq i8* null, %b
   %cmp3 = icmp eq i64** null, %g
   store i64* inttoptr (i64 1 to i64*), i64** @a, align 8
-  %l = load i64** @a, align 8
+  %l = load i64*, i64** @a, align 8
   ret void
 ; CHECK-LABEL: @qux(
 ; CHECK-NOT: store
diff --git a/test/Transforms/GlobalOpt/malloc-promote-1.ll b/test/Transforms/GlobalOpt/malloc-promote-1.ll
index 51ccbbd43ca8..d5087dea3443 100644
--- a/test/Transforms/GlobalOpt/malloc-promote-1.ll
+++ b/test/Transforms/GlobalOpt/malloc-promote-1.ll
@@ -8,7 +8,7 @@ define void @init() {
         %malloccall = tail call i8* @malloc(i64 4)      ; <i8*> [#uses=1]
         %P = bitcast i8* %malloccall to i32*            ; <i32*> [#uses=1]
         store i32* %P, i32** @G
-        %GV = load i32** @G             ; <i32*> [#uses=1]
+        %GV = load i32*, i32** @G             ; <i32*> [#uses=1]
         store i32 0, i32* %GV
         ret void
 }
@@ -16,8 +16,8 @@ define void @init() {
 declare noalias i8* @malloc(i64)
 
 define i32 @get() {
-        %GV = load i32** @G             ; <i32*> [#uses=1]
-        %V = load i32* %GV              ; <i32> [#uses=1]
+        %GV = load i32*, i32** @G             ; <i32*> [#uses=1]
+        %V = load i32, i32* %GV              ; <i32> [#uses=1]
         ret i32 %V
 ; CHECK: ret i32 0
 }
diff --git a/test/Transforms/GlobalOpt/malloc-promote-2.ll b/test/Transforms/GlobalOpt/malloc-promote-2.ll
index 6cb44812d2b6..335ed82a8cf5 100644
--- a/test/Transforms/GlobalOpt/malloc-promote-2.ll
+++ b/test/Transforms/GlobalOpt/malloc-promote-2.ll
@@ -10,8 +10,8 @@ define void @t() {
   %malloccall = tail call i8* @malloc(i64 mul (i64 100, i64 4))
   %P = bitcast i8* %malloccall to i32*
   store i32* %P, i32** @G
-  %GV = load i32** @G
-  %GVe = getelementptr i32* %GV, i32 40
+  %GV = load i32*, i32** @G
+  %GVe = getelementptr i32, i32* %GV, i32 40
   store i32 20, i32* %GVe
   ret void
 }
diff --git a/test/Transforms/GlobalOpt/malloc-promote-3.ll b/test/Transforms/GlobalOpt/malloc-promote-3.ll
index d44ee6460950..1e42c3b89a60 100644
--- a/test/Transforms/GlobalOpt/malloc-promote-3.ll
+++ b/test/Transforms/GlobalOpt/malloc-promote-3.ll
@@ -9,8 +9,8 @@ define void @t() {
   %malloccall = tail call i8* @malloc(i64 mul (i64 100, i64 4)) nobuiltin
   %P = bitcast i8* %malloccall to i32*
   store i32* %P, i32** @G
-  %GV = load i32** @G
-  %GVe = getelementptr i32* %GV, i32 40
+  %GV = load i32*, i32** @G
+  %GVe = getelementptr i32, i32* %GV, i32 40
   store i32 20, i32* %GVe
   ret void
 }
diff --git a/test/Transforms/GlobalOpt/memcpy.ll b/test/Transforms/GlobalOpt/memcpy.ll
index dcfe009e330c..437142e8c6e1 100644
--- a/test/Transforms/GlobalOpt/memcpy.ll
+++ b/test/Transforms/GlobalOpt/memcpy.ll
@@ -5,8 +5,8 @@
 
 define void @foo() {
   %Blah = alloca [58 x i8]
-  %tmp.0 = getelementptr [58 x i8]* %Blah, i32 0, i32 0
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp.0, i8* getelementptr inbounds ([58 x i8]* @G1, i32 0, i32 0), i32 58, i32 1, i1 false)
+  %tmp.0 = getelementptr [58 x i8], [58 x i8]* %Blah, i32 0, i32 0
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp.0, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @G1, i32 0, i32 0), i32 58, i32 1, i1 false)
   ret void
 }
 
diff --git a/test/Transforms/GlobalOpt/memset-null.ll b/test/Transforms/GlobalOpt/memset-null.ll
index 53ec7551130e..838ac0979e30 100644
--- a/test/Transforms/GlobalOpt/memset-null.ll
+++ b/test/Transforms/GlobalOpt/memset-null.ll
@@ -23,7 +23,7 @@ entry:
 
 define internal void @_GLOBAL__I_b() nounwind {
 entry:
-  %tmp.i.i.i = load i8** @y, align 8
+  %tmp.i.i.i = load i8*, i8** @y, align 8
   tail call void @llvm.memset.p0i8.i64(i8* %tmp.i.i.i, i8 0, i64 10, i32 1, i1 false) nounwind
   ret void
 }
diff --git a/test/Transforms/GlobalOpt/memset.ll b/test/Transforms/GlobalOpt/memset.ll
index 85320b7f2461..1dfdd6422334 100644
--- a/test/Transforms/GlobalOpt/memset.ll
+++ b/test/Transforms/GlobalOpt/memset.ll
@@ -11,7 +11,7 @@ define void @foo() {
   %Blah = alloca [58 x i8]
   %tmp3 = bitcast [58 x i8]* %Blah to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* bitcast ([4 x i32]* @G1 to i8*), i8* %tmp3, i32 16, i32 1, i1 false)
-  call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([58 x i8]* @G0, i32 0, i32 0), i8 17, i32 58, i32 1, i1 false)
+  call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([58 x i8], [58 x i8]* @G0, i32 0, i32 0), i8 17, i32 58, i32 1, i1 false)
   ret void
 }
 
@@ -22,7 +22,7 @@ define void @foo_as1() {
   %Blah = alloca [58 x i8]
   %tmp3 = bitcast [58 x i8]* %Blah to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* addrspacecast ([4 x i32] addrspace(1)* @G1_as1 to i8*), i8* %tmp3, i32 16, i32 1, i1 false)
-  call void @llvm.memset.p1i8.i32(i8 addrspace(1)* getelementptr inbounds ([58 x i8] addrspace(1)* @G0_as1, i32 0, i32 0), i8 17, i32 58, i32 1, i1 false)
+  call void @llvm.memset.p1i8.i32(i8 addrspace(1)* getelementptr inbounds ([58 x i8], [58 x i8] addrspace(1)* @G0_as1, i32 0, i32 0), i8 17, i32 58, i32 1, i1 false)
   ret void
 }
 
diff --git a/test/Transforms/GlobalOpt/phi-select.ll b/test/Transforms/GlobalOpt/phi-select.ll
index cd8a7dc990ff..e5cb9819ca0a 100644
--- a/test/Transforms/GlobalOpt/phi-select.ll
+++ b/test/Transforms/GlobalOpt/phi-select.ll
@@ -8,7 +8,7 @@
 
 define i32 @test1(i1 %C) {
         %P = select i1 %C, i32* @X, i32* @Y             ; <i32*> [#uses=1]
-        %V = load i32* %P               ; <i32> [#uses=1]
+        %V = load i32, i32* %P               ; <i32> [#uses=1]
         ret i32 %V
 }
 
@@ -21,7 +21,7 @@ T:              ; preds = %0
 
 Cont:           ; preds = %T, %0
         %P = phi i32* [ @X, %0 ], [ @Y, %T ]            ; <i32*> [#uses=1]
-        %V = load i32* %P               ; <i32> [#uses=1]
+        %V = load i32, i32* %P               ; <i32> [#uses=1]
         ret i32 %V
 }
 
diff --git a/test/Transforms/GlobalOpt/storepointer-compare.ll b/test/Transforms/GlobalOpt/storepointer-compare.ll
index 09e20a8adb26..bcf7cafd831c 100644
--- a/test/Transforms/GlobalOpt/storepointer-compare.ll
+++ b/test/Transforms/GlobalOpt/storepointer-compare.ll
@@ -16,7 +16,7 @@ define void @init() {
 }
 
 define void @doit() {
-        %FP = load void ()** @G         ; <void ()*> [#uses=2]
+        %FP = load void ()*, void ()** @G         ; <void ()*> [#uses=2]
         %CC = icmp eq void ()* %FP, null                ; <i1> [#uses=1]
         br i1 %CC, label %isNull, label %DoCall
 
diff --git a/test/Transforms/GlobalOpt/storepointer.ll b/test/Transforms/GlobalOpt/storepointer.ll
index 8019076f9463..9003004d431d 100644
--- a/test/Transforms/GlobalOpt/storepointer.ll
+++ b/test/Transforms/GlobalOpt/storepointer.ll
@@ -12,7 +12,7 @@ define void @init() {
 }
 
 define void @doit() {
-        %FP = load void ()** @G         ; <void ()*> [#uses=1]
+        %FP = load void ()*, void ()** @G         ; <void ()*> [#uses=1]
         call void %FP( )
         ret void
 }
diff --git a/test/Transforms/GlobalOpt/tls.ll b/test/Transforms/GlobalOpt/tls.ll
index 59ae23a4f6a8..f3cb4a65704d 100644
--- a/test/Transforms/GlobalOpt/tls.ll
+++ b/test/Transforms/GlobalOpt/tls.ll
@@ -14,34 +14,34 @@ declare void @start_thread(void ()*)
 define i32 @f() {
 entry:
   ; Set @ip to point to x[1] for thread 1.
-  store i32* getelementptr inbounds ([100 x i32]* @x, i64 0, i64 1), i32** @ip, align 8
+  store i32* getelementptr inbounds ([100 x i32], [100 x i32]* @x, i64 0, i64 1), i32** @ip, align 8
 
   ; Run g on a new thread.
   tail call void @start_thread(void ()* @g) nounwind
   tail call void @wait() nounwind
 
   ; Reset x[1] for thread 1.
-  store i32 0, i32* getelementptr inbounds ([100 x i32]* @x, i64 0, i64 1), align 4
+  store i32 0, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @x, i64 0, i64 1), align 4
 
   ; Read the value of @ip, which now points at x[1] for thread 2.
-  %0 = load i32** @ip, align 8
+  %0 = load i32*, i32** @ip, align 8
 
-  %1 = load i32* %0, align 4
+  %1 = load i32, i32* %0, align 4
   ret i32 %1
 
 ; CHECK-LABEL: @f(
 ; Make sure that the load from @ip hasn't been removed.
-; CHECK: load i32** @ip
+; CHECK: load i32*, i32** @ip
 ; CHECK: ret
 }
 
 define internal void @g() nounwind uwtable {
 entry:
   ; Set @ip to point to x[1] for thread 2.
-  store i32* getelementptr inbounds ([100 x i32]* @x, i64 0, i64 1), i32** @ip, align 8
+  store i32* getelementptr inbounds ([100 x i32], [100 x i32]* @x, i64 0, i64 1), i32** @ip, align 8
 
   ; Store 50 in x[1] for thread 2.
-  store i32 50, i32* getelementptr inbounds ([100 x i32]* @x, i64 0, i64 1), align 4
+  store i32 50, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @x, i64 0, i64 1), align 4
 
   tail call void @signal() nounwind
   ret void
diff --git a/test/Transforms/GlobalOpt/trivialstore.ll b/test/Transforms/GlobalOpt/trivialstore.ll
index 21437f33b26d..f907d8382d57 100644
--- a/test/Transforms/GlobalOpt/trivialstore.ll
+++ b/test/Transforms/GlobalOpt/trivialstore.ll
@@ -8,7 +8,7 @@ define void @foo() {
 }
 
 define i32 @bar() {
-        %X = load i32* @G               ; <i32> [#uses=1]
+        %X = load i32, i32* @G               ; <i32> [#uses=1]
         ret i32 %X
 }
 
diff --git a/test/Transforms/GlobalOpt/undef-init.ll b/test/Transforms/GlobalOpt/undef-init.ll
index c14949739508..d304821225ea 100644
--- a/test/Transforms/GlobalOpt/undef-init.ll
+++ b/test/Transforms/GlobalOpt/undef-init.ll
@@ -5,7 +5,7 @@
 
 define i32 @_Z3foov() {
 entry:
-        %tmp.1 = load i32* @X.0         ; <i32> [#uses=1]
+        %tmp.1 = load i32, i32* @X.0         ; <i32> [#uses=1]
         ret i32 %tmp.1
 }
 
diff --git a/test/Transforms/GlobalOpt/unnamed-addr.ll b/test/Transforms/GlobalOpt/unnamed-addr.ll
index 2ca91e50da2a..85ed829c7112 100644
--- a/test/Transforms/GlobalOpt/unnamed-addr.ll
+++ b/test/Transforms/GlobalOpt/unnamed-addr.ll
@@ -13,7 +13,7 @@
 ; CHECK: @e = linkonce_odr global i32 0
 
 define i32 @get_e() {
-       %t = load i32* @e
+       %t = load i32, i32* @e
        ret i32 %t
 }
 
@@ -24,10 +24,10 @@ define void @set_e(i32 %x) {
 
 define i1 @bah(i64 %i) nounwind readonly optsize ssp {
 entry:
-  %arrayidx4 = getelementptr inbounds [4 x i8]* @d, i64 0, i64 %i
-  %tmp5 = load i8* %arrayidx4, align 1
+  %arrayidx4 = getelementptr inbounds [4 x i8], [4 x i8]* @d, i64 0, i64 %i
+  %tmp5 = load i8, i8* %arrayidx4, align 1
   %array0 = bitcast [4 x i8]* @d to i8*
-  %tmp6 = load i8* %array0, align 1
+  %tmp6 = load i8, i8* %array0, align 1
   %cmp = icmp eq i8 %tmp5, %tmp6
   ret i1 %cmp
 }
@@ -63,6 +63,6 @@ return:
 
 define i32 @zed() {
 entry:
-  %tmp1 = load i32* @c, align 4
+  %tmp1 = load i32, i32* @c, align 4
   ret i32 %tmp1
 }
diff --git a/test/Transforms/GlobalOpt/zeroinitializer-gep-load.ll b/test/Transforms/GlobalOpt/zeroinitializer-gep-load.ll
index d9787232d971..51feb480e3bf 100644
--- a/test/Transforms/GlobalOpt/zeroinitializer-gep-load.ll
+++ b/test/Transforms/GlobalOpt/zeroinitializer-gep-load.ll
@@ -3,8 +3,8 @@
 @zero = internal global [10 x i32] zeroinitializer
 
 define i32 @test1(i64 %idx) nounwind {
-  %arrayidx = getelementptr inbounds [10 x i32]* @zero, i64 0, i64 %idx
-  %l = load i32* %arrayidx
+  %arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* @zero, i64 0, i64 %idx
+  %l = load i32, i32* %arrayidx
   ret i32 %l
 ; CHECK-LABEL: @test1(
 ; CHECK: ret i32 0
diff --git a/test/Transforms/IPConstantProp/2009-09-24-byval-ptr.ll b/test/Transforms/IPConstantProp/2009-09-24-byval-ptr.ll
index 4ea0b88fd0de..61f4bf6d9f7f 100644
--- a/test/Transforms/IPConstantProp/2009-09-24-byval-ptr.ll
+++ b/test/Transforms/IPConstantProp/2009-09-24-byval-ptr.ll
@@ -5,10 +5,10 @@
 @mystr = internal global %struct.MYstr zeroinitializer ; <%struct.MYstr*> [#uses=3]
 define internal void @vfu1(%struct.MYstr* byval align 4 %u) nounwind {
 entry:
-  %0 = getelementptr %struct.MYstr* %u, i32 0, i32 1 ; <i32*> [#uses=1]
+  %0 = getelementptr %struct.MYstr, %struct.MYstr* %u, i32 0, i32 1 ; <i32*> [#uses=1]
   store i32 99, i32* %0, align 4
 ; CHECK: %struct.MYstr* %u
-  %1 = getelementptr %struct.MYstr* %u, i32 0, i32 0 ; <i8*> [#uses=1]
+  %1 = getelementptr %struct.MYstr, %struct.MYstr* %u, i32 0, i32 0 ; <i8*> [#uses=1]
   store i8 97, i8* %1, align 4
 ; CHECK: %struct.MYstr* %u
   br label %return
@@ -19,12 +19,12 @@ return:                                           ; preds = %entry
 
 define internal i32 @vfu2(%struct.MYstr* byval align 4 %u) nounwind readonly {
 entry:
-  %0 = getelementptr %struct.MYstr* %u, i32 0, i32 1 ; <i32*> [#uses=1]
-  %1 = load i32* %0
-; CHECK: load i32* getelementptr inbounds (%struct.MYstr* @mystr, i32 0, i32 1)
-  %2 = getelementptr %struct.MYstr* %u, i32 0, i32 0 ; <i8*> [#uses=1]
-  %3 = load i8* %2
-; CHECK: load i8* getelementptr inbounds (%struct.MYstr* @mystr, i32 0, i32 0)
+  %0 = getelementptr %struct.MYstr, %struct.MYstr* %u, i32 0, i32 1 ; <i32*> [#uses=1]
+  %1 = load i32, i32* %0
+; CHECK: load i32, i32* getelementptr inbounds (%struct.MYstr, %struct.MYstr* @mystr, i32 0, i32 1)
+  %2 = getelementptr %struct.MYstr, %struct.MYstr* %u, i32 0, i32 0 ; <i8*> [#uses=1]
+  %3 = load i8, i8* %2
+; CHECK: load i8, i8* getelementptr inbounds (%struct.MYstr, %struct.MYstr* @mystr, i32 0, i32 0)
   %4 = zext i8 %3 to i32
   %5 = add i32 %4, %1
   ret i32 %5
diff --git a/test/Transforms/IPConstantProp/dangling-block-address.ll b/test/Transforms/IPConstantProp/dangling-block-address.ll
index bb101333f801..abd0b0fc3136 100644
--- a/test/Transforms/IPConstantProp/dangling-block-address.ll
+++ b/test/Transforms/IPConstantProp/dangling-block-address.ll
@@ -29,10 +29,10 @@ end:                                              ; preds = %indirectgoto
 
 indirectgoto:                                     ; preds = %lab0, %entry
   %indvar = phi i32 [ %indvar.next, %lab0 ], [ 0, %entry ] ; <i32> [#uses=2]
-  %pc.addr.0 = getelementptr i32* %pc, i32 %indvar ; <i32*> [#uses=1]
-  %tmp1.pn = load i32* %pc.addr.0                 ; <i32> [#uses=1]
-  %indirect.goto.dest.in = getelementptr inbounds [2 x i8*]* @bar.l, i32 0, i32 %tmp1.pn ; <i8**> [#uses=1]
-  %indirect.goto.dest = load i8** %indirect.goto.dest.in ; <i8*> [#uses=1]
+  %pc.addr.0 = getelementptr i32, i32* %pc, i32 %indvar ; <i32*> [#uses=1]
+  %tmp1.pn = load i32, i32* %pc.addr.0                 ; <i32> [#uses=1]
+  %indirect.goto.dest.in = getelementptr inbounds [2 x i8*], [2 x i8*]* @bar.l, i32 0, i32 %tmp1.pn ; <i8**> [#uses=1]
+  %indirect.goto.dest = load i8*, i8** %indirect.goto.dest.in ; <i8*> [#uses=1]
   indirectbr i8* %indirect.goto.dest, [label %lab0, label %end]
 }
 
diff --git a/test/Transforms/IPConstantProp/global.ll b/test/Transforms/IPConstantProp/global.ll
index 67152937beec..d3ba14658f6e 100644
--- a/test/Transforms/IPConstantProp/global.ll
+++ b/test/Transforms/IPConstantProp/global.ll
@@ -4,7 +4,7 @@
 
 define void @_Z7test1f1v() nounwind {
 entry:
-  %tmp = load i32* @_ZL6test1g, align 4
+  %tmp = load i32, i32* @_ZL6test1g, align 4
   %cmp = icmp eq i32 %tmp, 0
   br i1 %cmp, label %if.then, label %if.end
 
@@ -21,6 +21,6 @@ if.end:                                           ; preds = %if.then, %entry
 ; CHECK-NEXT: ret i32 42
 define i32 @_Z7test1f2v() nounwind {
 entry:
-  %tmp = load i32* @_ZL6test1g, align 4
+  %tmp = load i32, i32* @_ZL6test1g, align 4
   ret i32 %tmp
 }
diff --git a/test/Transforms/IPConstantProp/return-argument.ll b/test/Transforms/IPConstantProp/return-argument.ll
index 2a14f05985d0..927531b996ea 100644
--- a/test/Transforms/IPConstantProp/return-argument.ll
+++ b/test/Transforms/IPConstantProp/return-argument.ll
@@ -4,7 +4,7 @@
 
 ;; This function returns its second argument on all return statements
 define internal i32* @incdec(i1 %C, i32* %V) {
-        %X = load i32* %V
+        %X = load i32, i32* %V
         br i1 %C, label %T, label %F
 
 T:              ; preds = %0
diff --git a/test/Transforms/IPConstantProp/return-constant.ll b/test/Transforms/IPConstantProp/return-constant.ll
index 499d38329522..d89579532e71 100644
--- a/test/Transforms/IPConstantProp/return-constant.ll
+++ b/test/Transforms/IPConstantProp/return-constant.ll
@@ -1,5 +1,4 @@
-; RUN: opt < %s -ipconstprop -instcombine | \
-; RUN:    llvm-dis | grep "ret i1 true" | count 2
+; RUN: opt < %s -ipconstprop -instcombine -S | grep "ret i1 true" | count 2
 define internal i32 @foo(i1 %C) {
         br i1 %C, label %T, label %F
 
diff --git a/test/Transforms/IRCE/bug-loop-varying-upper-limit.ll b/test/Transforms/IRCE/bug-loop-varying-upper-limit.ll
new file mode 100644
index 000000000000..4635bb4381ea
--- /dev/null
+++ b/test/Transforms/IRCE/bug-loop-varying-upper-limit.ll
@@ -0,0 +1,31 @@
+; RUN: opt -irce-print-changed-loops -S -irce -verify < %s 2>&1 | FileCheck %s
+
+; CHECK-NOT: constrained loop
+
+define void @single_access_no_preloop_no_offset(i32 *%arr, i32 *%a_len_ptr, i32 %n) {
+ entry:
+  %first.itr.check = icmp sgt i32 %n, 0
+  br i1 %first.itr.check, label %loop, label %exit
+
+ loop:
+  %idx = phi i32 [ 0, %entry ] , [ %idx.next, %in.bounds ]
+  %idx.next = add i32 %idx, 1
+  %len = load i32, i32* %a_len_ptr, !range !0
+  %abc = icmp slt i32 %idx, %len
+  br i1 %abc, label %in.bounds, label %out.of.bounds, !prof !1
+
+ in.bounds:
+  %addr = getelementptr i32, i32* %arr, i32 %idx
+  store i32 0, i32* %addr
+  %next = icmp slt i32 %idx.next, %n
+  br i1 %next, label %loop, label %exit
+
+ out.of.bounds:
+  ret void
+
+ exit:
+  ret void
+}
+
+!0 = !{i32 0, i32 2147483647}
+!1 = !{!"branch_weights", i32 64, i32 4}
diff --git a/test/Transforms/IRCE/bug-mismatched-types.ll b/test/Transforms/IRCE/bug-mismatched-types.ll
new file mode 100644
index 000000000000..9ff72493393e
--- /dev/null
+++ b/test/Transforms/IRCE/bug-mismatched-types.ll
@@ -0,0 +1,66 @@
+; RUN: opt -irce -S < %s
+
+; These test cases don't check the correctness of the transform, but
+; that the -irce does not crash in the presence of certain things in
+; the IR:
+
+define void @mismatched_types_1() {
+; In this test case, the safe range for the only range check in the
+; loop is of type [i32, i32) while the backedge taken count is of type
+; i64.
+
+; CHECK-LABEL: mismatched_types_1
+entry:
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ]
+  %0 = trunc i64 %indvars.iv to i32
+  %1 = icmp ult i32 %0, 7
+  br i1 %1, label %switch.lookup, label %for.inc
+
+switch.lookup:
+  br label %for.inc
+
+for.inc:
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %cmp55 = icmp slt i64 %indvars.iv.next, 11
+  br i1 %cmp55, label %for.body, label %for.end
+
+for.end:
+  unreachable
+}
+
+define void @mismatched_types_2() {
+; In this test case, there are two range check in the loop, one with a
+; safe range of type [i32, i32) and one with a safe range of type
+; [i64, i64).
+
+; CHECK-LABEL: mismatched_types_2
+entry:
+  br label %for.body.a
+
+for.body.a:
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ]
+  %cond.a = icmp ult i64 %indvars.iv, 7
+  br i1 %cond.a, label %switch.lookup.a, label %for.body.b
+
+switch.lookup.a:
+  br label %for.body.b
+
+for.body.b:
+  %truncated = trunc i64 %indvars.iv to i32
+  %cond.b = icmp ult i32 %truncated, 7
+  br i1 %cond.b, label %switch.lookup.b, label %for.inc
+
+switch.lookup.b:
+  br label %for.inc
+
+for.inc:
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %cmp55 = icmp slt i64 %indvars.iv.next, 11
+  br i1 %cmp55, label %for.body.a, label %for.end
+
+for.end:
+  unreachable
+}
diff --git a/test/Transforms/IRCE/decrementing-loop.ll b/test/Transforms/IRCE/decrementing-loop.ll
new file mode 100644
index 000000000000..6ff3e76c7546
--- /dev/null
+++ b/test/Transforms/IRCE/decrementing-loop.ll
@@ -0,0 +1,43 @@
+; RUN: opt -irce -S < %s | FileCheck %s
+
+define void @decrementing_loop(i32 *%arr, i32 *%a_len_ptr, i32 %n) {
+ entry:
+  %len = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check = icmp sgt i32 %n, 0
+  %start = sub i32 %n, 1
+  br i1 %first.itr.check, label %loop, label %exit
+
+ loop:
+  %idx = phi i32 [ %start, %entry ] , [ %idx.dec, %in.bounds ]
+  %idx.dec = sub i32 %idx, 1
+  %abc.high = icmp slt i32 %idx, %len
+  %abc.low = icmp sge i32 %idx, 0
+  %abc = and i1 %abc.low, %abc.high
+  br i1 %abc, label %in.bounds, label %out.of.bounds, !prof !1
+
+ in.bounds:
+  %addr = getelementptr i32, i32* %arr, i32 %idx
+  store i32 0, i32* %addr
+  %next = icmp sgt i32 %idx.dec, -1
+  br i1 %next, label %loop, label %exit
+
+ out.of.bounds:
+  ret void
+
+ exit:
+  ret void
+
+; CHECK: loop.preheader:
+; CHECK:   [[indvar_start:[^ ]+]] = add i32 %n, -1
+; CHECK:   [[not_len:[^ ]+]] = sub i32 -1, %len
+; CHECK:   [[not_n:[^ ]+]] = sub i32 -1, %n
+; CHECK:   [[not_len_hiclamp_cmp:[^ ]+]] = icmp sgt i32 [[not_len]], [[not_n]]
+; CHECK:   [[not_len_hiclamp:[^ ]+]] = select i1 [[not_len_hiclamp_cmp]], i32 [[not_len]], i32 [[not_n]]
+; CHECK:   [[len_hiclamp:[^ ]+]] = sub i32 -1, [[not_len_hiclamp]]
+; CHECK:   [[not_exit_preloop_at_cmp:[^ ]+]] = icmp sgt i32 [[len_hiclamp]], 0
+; CHECK:   [[not_exit_preloop_at:[^ ]+]] = select i1 [[not_exit_preloop_at_cmp]], i32 [[len_hiclamp]], i32 0
+; CHECK:   %exit.preloop.at = add i32 [[not_exit_preloop_at]], -1
+}
+
+!0 = !{i32 0, i32 2147483647}
+!1 = !{!"branch_weights", i32 64, i32 4}
diff --git a/test/Transforms/IRCE/low-becount.ll b/test/Transforms/IRCE/low-becount.ll
new file mode 100644
index 000000000000..89b91d6496a8
--- /dev/null
+++ b/test/Transforms/IRCE/low-becount.ll
@@ -0,0 +1,32 @@
+; RUN: opt -irce-print-changed-loops -irce -S < %s 2>&1 | FileCheck %s
+
+; CHECK-NOT: constrained Loop
+
+define void @low_profiled_be_count(i32 *%arr, i32 *%a_len_ptr, i32 %n) {
+ entry:
+  %len = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check = icmp sgt i32 %n, 0
+  br i1 %first.itr.check, label %loop, label %exit
+
+ loop:
+  %idx = phi i32 [ 0, %entry ] , [ %idx.next, %in.bounds ]
+  %idx.next = add i32 %idx, 1
+  %abc = icmp slt i32 %idx, %len
+  br i1 %abc, label %in.bounds, label %out.of.bounds, !prof !1
+
+ in.bounds:
+  %addr = getelementptr i32, i32* %arr, i32 %idx
+  store i32 0, i32* %addr
+  %next = icmp slt i32 %idx.next, %n
+  br i1 %next, label %loop, label %exit, !prof !2
+
+ out.of.bounds:
+  ret void
+
+ exit:
+  ret void
+}
+
+!0 = !{i32 0, i32 2147483647}
+!1 = !{!"branch_weights", i32 64, i32 4}
+!2 = !{!"branch_weights", i32 4, i32 64}
diff --git a/test/Transforms/IRCE/multiple-access-no-preloop.ll b/test/Transforms/IRCE/multiple-access-no-preloop.ll
new file mode 100644
index 000000000000..9963a57185bf
--- /dev/null
+++ b/test/Transforms/IRCE/multiple-access-no-preloop.ll
@@ -0,0 +1,66 @@
+; RUN: opt -irce -S < %s | FileCheck %s
+
+define void @multiple_access_no_preloop(
+    i32* %arr_a, i32* %a_len_ptr, i32* %arr_b, i32* %b_len_ptr, i32 %n) {
+
+ entry:
+  %len.a = load i32, i32* %a_len_ptr, !range !0
+  %len.b = load i32, i32* %b_len_ptr, !range !0
+  %first.itr.check = icmp sgt i32 %n, 0
+  br i1 %first.itr.check, label %loop, label %exit
+
+ loop:
+  %idx = phi i32 [ 0, %entry ] , [ %idx.next, %in.bounds.b ]
+  %idx.next = add i32 %idx, 1
+  %abc.a = icmp slt i32 %idx, %len.a
+  br i1 %abc.a, label %in.bounds.a, label %out.of.bounds, !prof !1
+
+ in.bounds.a:
+  %addr.a = getelementptr i32, i32* %arr_a, i32 %idx
+  store i32 0, i32* %addr.a
+  %abc.b = icmp slt i32 %idx, %len.b
+  br i1 %abc.b, label %in.bounds.b, label %out.of.bounds, !prof !1
+
+ in.bounds.b:
+  %addr.b = getelementptr i32, i32* %arr_b, i32 %idx
+  store i32 -1, i32* %addr.b
+  %next = icmp slt i32 %idx.next, %n
+  br i1 %next, label %loop, label %exit
+
+ out.of.bounds:
+  ret void
+
+ exit:
+  ret void
+}
+
+; CHECK-LABEL: multiple_access_no_preloop
+
+; CHECK-LABEL: loop.preheader:
+; CHECK: [[not_len_b:[^ ]+]] = sub i32 -1, %len.b
+; CHECK: [[not_len_a:[^ ]+]] = sub i32 -1, %len.a
+; CHECK: [[smax_not_len_cond:[^ ]+]] = icmp sgt i32 [[not_len_b]], [[not_len_a]]
+; CHECK: [[smax_not_len:[^ ]+]] = select i1 [[smax_not_len_cond]], i32 [[not_len_b]], i32 [[not_len_a]]
+; CHECK: [[not_n:[^ ]+]] = sub i32 -1, %n
+; CHECK: [[not_upper_limit_cond_loclamp:[^ ]+]] = icmp sgt i32 [[smax_not_len]], [[not_n]]
+; CHECK: [[not_upper_limit_loclamp:[^ ]+]] = select i1 [[not_upper_limit_cond_loclamp]], i32 [[smax_not_len]], i32 [[not_n]]
+; CHECK: [[upper_limit_loclamp:[^ ]+]] = sub i32 -1, [[not_upper_limit_loclamp]]
+; CHECK: [[upper_limit_cmp:[^ ]+]] = icmp sgt i32 [[upper_limit_loclamp]], 0
+; CHECK: [[upper_limit:[^ ]+]] = select i1 [[upper_limit_cmp]], i32 [[upper_limit_loclamp]], i32 0
+
+; CHECK-LABEL: loop:
+; CHECK: br i1 true, label %in.bounds.a, label %out.of.bounds
+
+; CHECK-LABEL: in.bounds.a:
+; CHECK: br i1 true, label %in.bounds.b, label %out.of.bounds
+
+; CHECK-LABEL: in.bounds.b:
+; CHECK: [[main_loop_cond:[^ ]+]] = icmp slt i32 %idx.next, [[upper_limit]]
+; CHECK: br i1 [[main_loop_cond]], label %loop, label %main.exit.selector
+
+; CHECK-LABEL: in.bounds.b.postloop:
+; CHECK: %next.postloop = icmp slt i32 %idx.next.postloop, %n
+; CHECK: br i1 %next.postloop, label %loop.postloop, label %exit.loopexit
+
+!0 = !{i32 0, i32 2147483647}
+!1 = !{!"branch_weights", i32 64, i32 4}
diff --git a/test/Transforms/IRCE/not-likely-taken.ll b/test/Transforms/IRCE/not-likely-taken.ll
new file mode 100644
index 000000000000..50a64a286320
--- /dev/null
+++ b/test/Transforms/IRCE/not-likely-taken.ll
@@ -0,0 +1,40 @@
+; RUN: opt -verify-loop-info -irce-print-changed-loops -irce < %s 2>&1 | FileCheck %s
+
+; CHECK-NOT: constrained Loop
+
+define void @multiple_access_no_preloop(
+    i32* %arr_a, i32* %a_len_ptr, i32* %arr_b, i32* %b_len_ptr, i32 %n) {
+
+ entry:
+  %len.a = load i32, i32* %a_len_ptr, !range !0
+  %len.b = load i32, i32* %b_len_ptr, !range !0
+  %first.itr.check = icmp sgt i32 %n, 0
+  br i1 %first.itr.check, label %loop, label %exit
+
+ loop:
+  %idx = phi i32 [ 0, %entry ] , [ %idx.next, %in.bounds.b ]
+  %idx.next = add i32 %idx, 1
+  %abc.a = icmp slt i32 %idx, %len.a
+  br i1 %abc.a, label %in.bounds.a, label %out.of.bounds, !prof !1
+
+ in.bounds.a:
+  %addr.a = getelementptr i32, i32* %arr_a, i32 %idx
+  store i32 0, i32* %addr.a
+  %abc.b = icmp slt i32 %idx, %len.b
+  br i1 %abc.b, label %in.bounds.b, label %out.of.bounds, !prof !1
+
+ in.bounds.b:
+  %addr.b = getelementptr i32, i32* %arr_b, i32 %idx
+  store i32 -1, i32* %addr.b
+  %next = icmp slt i32 %idx.next, %n
+  br i1 %next, label %loop, label %exit
+
+ out.of.bounds:
+  ret void
+
+ exit:
+  ret void
+}
+
+!0 = !{i32 0, i32 2147483647}
+!1 = !{!"branch_weights", i32 1, i32 1}
\ No newline at end of file
diff --git a/test/Transforms/IRCE/only-lower-check.ll b/test/Transforms/IRCE/only-lower-check.ll
new file mode 100644
index 000000000000..69abc89c1a66
--- /dev/null
+++ b/test/Transforms/IRCE/only-lower-check.ll
@@ -0,0 +1,37 @@
+; RUN: opt -irce-print-range-checks -irce-print-changed-loops -irce < %s 2>&1 | FileCheck %s
+
+; CHECK: irce: loop has 1 inductive range checks:
+; CHECK-NEXT: InductiveRangeCheck:
+; CHECK-NEXT:   Kind: RANGE_CHECK_LOWER
+; CHECK-NEXT:   Offset: (-1 + %n)  Scale: -1  Length: (null)
+; CHECK-NEXT:   Branch:   br i1 %abc, label %in.bounds, label %out.of.bounds
+; CHECK-NEXT: irce: in function only_lower_check: constrained Loop at depth 1 containing: %loop<header><exiting>,%in.bounds<latch><exiting>
+
+define void @only_lower_check(i32 *%arr, i32 *%a_len_ptr, i32 %n) {
+ entry:
+  %len = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check = icmp sgt i32 %n, 0
+  %start = sub i32 %n, 1
+  br i1 %first.itr.check, label %loop, label %exit
+
+ loop:
+  %idx = phi i32 [ %start, %entry ] , [ %idx.dec, %in.bounds ]
+  %idx.dec = sub i32 %idx, 1
+  %abc = icmp sge i32 %idx, 0
+  br i1 %abc, label %in.bounds, label %out.of.bounds, !prof !1
+
+ in.bounds:
+  %addr = getelementptr i32, i32* %arr, i32 %idx
+  store i32 0, i32* %addr
+  %next = icmp sgt i32 %idx.dec, -1
+  br i1 %next, label %loop, label %exit
+
+ out.of.bounds:
+  ret void
+
+ exit:
+  ret void
+}
+
+!0 = !{i32 0, i32 2147483647}
+!1 = !{!"branch_weights", i32 64, i32 4}
diff --git a/test/Transforms/IRCE/only-upper-check.ll b/test/Transforms/IRCE/only-upper-check.ll
new file mode 100644
index 000000000000..dda3f3f6dd87
--- /dev/null
+++ b/test/Transforms/IRCE/only-upper-check.ll
@@ -0,0 +1,37 @@
+; RUN: opt -irce -irce-print-range-checks -irce-print-changed-loops %s -S 2>&1 | FileCheck %s
+
+; CHECK: irce: loop has 1 inductive range checks:
+; CHECK-NEXT:InductiveRangeCheck:
+; CHECK-NEXT:  Kind: RANGE_CHECK_UPPER
+; CHECK-NEXT:  Offset: %offset  Scale: 1  Length:   %len = load i32, i32* %a_len_ptr, !range !0
+; CHECK-NEXT:  Branch:   br i1 %abc, label %in.bounds, label %out.of.bounds, !prof !1
+; CHECK-NEXT: irce: in function incrementing: constrained Loop at depth 1 containing: %loop<header><exiting>,%in.bounds<latch><exiting>
+
+define void @incrementing(i32 *%arr, i32 *%a_len_ptr, i32 %n, i32 %offset) {
+ entry:
+  %len = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check = icmp sgt i32 %n, 0
+  br i1 %first.itr.check, label %loop, label %exit
+
+ loop:
+  %idx = phi i32 [ 0, %entry ] , [ %idx.next, %in.bounds ]
+  %idx.next = add i32 %idx, 1
+  %array.idx = add i32 %idx, %offset
+  %abc = icmp slt i32 %array.idx, %len
+  br i1 %abc, label %in.bounds, label %out.of.bounds, !prof !1
+
+ in.bounds:
+  %addr = getelementptr i32, i32* %arr, i32 %array.idx
+  store i32 0, i32* %addr
+  %next = icmp slt i32 %idx.next, %n
+  br i1 %next, label %loop, label %exit
+
+ out.of.bounds:
+  ret void
+
+ exit:
+  ret void
+}
+
+!0 = !{i32 0, i32 2147483647}
+!1 = !{!"branch_weights", i32 64, i32 4}
diff --git a/test/Transforms/IRCE/single-access-no-preloop.ll b/test/Transforms/IRCE/single-access-no-preloop.ll
new file mode 100644
index 000000000000..4824d9560c69
--- /dev/null
+++ b/test/Transforms/IRCE/single-access-no-preloop.ll
@@ -0,0 +1,116 @@
+; RUN: opt -irce -S < %s | FileCheck %s
+
+define void @single_access_no_preloop_no_offset(i32 *%arr, i32 *%a_len_ptr, i32 %n) {
+ entry:
+  %len = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check = icmp sgt i32 %n, 0
+  br i1 %first.itr.check, label %loop, label %exit
+
+ loop:
+  %idx = phi i32 [ 0, %entry ] , [ %idx.next, %in.bounds ]
+  %idx.next = add i32 %idx, 1
+  %abc = icmp slt i32 %idx, %len
+  br i1 %abc, label %in.bounds, label %out.of.bounds, !prof !1
+
+ in.bounds:
+  %addr = getelementptr i32, i32* %arr, i32 %idx
+  store i32 0, i32* %addr
+  %next = icmp slt i32 %idx.next, %n
+  br i1 %next, label %loop, label %exit
+
+ out.of.bounds:
+  ret void
+
+ exit:
+  ret void
+}
+
+; CHECK-LABEL: single_access_no_preloop
+
+; CHECK-LABEL: loop:
+; CHECK: br i1 true, label %in.bounds, label %out.of.bounds
+
+; CHECK-LABEL: main.exit.selector:
+; CHECK-NEXT: [[continue:%[^ ]+]] = icmp slt i32 %idx.next, %n
+; CHECK-NEXT: br i1 [[continue]], label %main.pseudo.exit, label %exit.loopexit
+
+; CHECK-LABEL: main.pseudo.exit:
+; CHECK-NEXT: %idx.copy = phi i32 [ 0, %loop.preheader ], [ %idx.next, %main.exit.selector ]
+; CHECK-NEXT: %indvar.end = phi i32 [ 0, %loop.preheader ], [ %idx.next, %main.exit.selector ]
+; CHECK-NEXT: br label %postloop
+
+; CHECK-LABEL: postloop:
+; CHECK-NEXT: br label %loop.postloop
+
+; CHECK-LABEL: loop.postloop:
+; CHECK-NEXT: %idx.postloop = phi i32 [ %idx.next.postloop, %in.bounds.postloop ], [ %idx.copy, %postloop ]
+; CHECK-NEXT: %idx.next.postloop = add i32 %idx.postloop, 1
+; CHECK-NEXT: %abc.postloop = icmp slt i32 %idx.postloop, %len
+; CHECK-NEXT: br i1 %abc.postloop, label %in.bounds.postloop, label %out.of.bounds
+
+; CHECK-LABEL: in.bounds.postloop:
+; CHECK-NEXT: %addr.postloop = getelementptr i32, i32* %arr, i32 %idx.postloop
+; CHECK-NEXT: store i32 0, i32* %addr.postloop
+; CHECK-NEXT: %next.postloop = icmp slt i32 %idx.next.postloop, %n
+; CHECK-NEXT: br i1 %next.postloop, label %loop.postloop, label %exit.loopexit
+
+
+define void @single_access_no_preloop_with_offset(i32 *%arr, i32 *%a_len_ptr, i32 %n) {
+ entry:
+  %len = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check = icmp sgt i32 %n, 0
+  br i1 %first.itr.check, label %loop, label %exit
+
+ loop:
+  %idx = phi i32 [ 0, %entry ] , [ %idx.next, %in.bounds ]
+  %idx.next = add i32 %idx, 1
+  %idx.for.abc = add i32 %idx, 4
+  %abc = icmp slt i32 %idx.for.abc, %len
+  br i1 %abc, label %in.bounds, label %out.of.bounds, !prof !1
+
+ in.bounds:
+  %addr = getelementptr i32, i32* %arr, i32 %idx.for.abc
+  store i32 0, i32* %addr
+  %next = icmp slt i32 %idx.next, %n
+  br i1 %next, label %loop, label %exit
+
+ out.of.bounds:
+  ret void
+
+ exit:
+  ret void
+}
+
+; CHECK-LABEL: single_access_no_preloop_with_offset
+
+; CHECK-LABEL: loop.preheader:
+; CHECK: [[not_n:[^ ]+]] = sub i32 -1, %n
+; CHECK: [[not_safe_range_end:[^ ]+]] = sub i32 3, %len
+; CHECK: [[not_exit_main_loop_at_hiclamp_cmp:[^ ]+]] = icmp sgt i32 [[not_n]], [[not_safe_range_end]]
+; CHECK: [[not_exit_main_loop_at_hiclamp:[^ ]+]] = select i1 [[not_exit_main_loop_at_hiclamp_cmp]], i32 [[not_n]], i32 [[not_safe_range_end]]
+; CHECK: [[exit_main_loop_at_hiclamp:[^ ]+]] = sub i32 -1, [[not_exit_main_loop_at_hiclamp]]
+; CHECK: [[exit_main_loop_at_loclamp_cmp:[^ ]+]] = icmp sgt i32 [[exit_main_loop_at_hiclamp]], 0
+; CHECK: [[exit_main_loop_at_loclamp:[^ ]+]] = select i1 [[exit_main_loop_at_loclamp_cmp]], i32 [[exit_main_loop_at_hiclamp]], i32 0
+; CHECK: [[enter_main_loop:[^ ]+]] = icmp slt i32 0, [[exit_main_loop_at_loclamp]]
+; CHECK: br i1 [[enter_main_loop]], label %loop, label %main.pseudo.exit
+
+; CHECK-LABEL: loop:
+; CHECK: br i1 true, label %in.bounds, label %out.of.bounds
+
+; CHECK-LABEL: in.bounds:
+; CHECK: [[continue_main_loop:[^ ]+]] = icmp slt i32 %idx.next, [[exit_main_loop_at_loclamp]]
+; CHECK: br i1 [[continue_main_loop]], label %loop, label %main.exit.selector
+
+; CHECK-LABEL: main.pseudo.exit:
+; CHECK:  %idx.copy = phi i32 [ 0, %loop.preheader ], [ %idx.next, %main.exit.selector ]
+; CHECK:  br label %postloop
+
+; CHECK-LABEL: loop.postloop:
+; CHECK: %idx.postloop = phi i32 [ %idx.next.postloop, %in.bounds.postloop ], [ %idx.copy, %postloop ]
+
+; CHECK-LABEL: in.bounds.postloop:
+; CHECK: %next.postloop = icmp slt i32 %idx.next.postloop, %n
+; CHECK: br i1 %next.postloop, label %loop.postloop, label %exit.loopexit
+
+!0 = !{i32 0, i32 2147483647}
+!1 = !{!"branch_weights", i32 64, i32 4}
diff --git a/test/Transforms/IRCE/single-access-with-preloop.ll b/test/Transforms/IRCE/single-access-with-preloop.ll
new file mode 100644
index 000000000000..e581014ad188
--- /dev/null
+++ b/test/Transforms/IRCE/single-access-with-preloop.ll
@@ -0,0 +1,71 @@
+; RUN: opt -irce -S < %s | FileCheck %s
+
+define void @single_access_with_preloop(i32 *%arr, i32 *%a_len_ptr, i32 %n, i32 %offset) {
+ entry:
+  %len = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check = icmp sgt i32 %n, 0
+  br i1 %first.itr.check, label %loop, label %exit
+
+ loop:
+  %idx = phi i32 [ 0, %entry ] , [ %idx.next, %in.bounds ]
+  %idx.next = add i32 %idx, 1
+  %array.idx = add i32 %idx, %offset
+  %abc.high = icmp slt i32 %array.idx, %len
+  %abc.low = icmp sge i32 %array.idx, 0
+  %abc = and i1 %abc.low, %abc.high
+  br i1 %abc, label %in.bounds, label %out.of.bounds, !prof !1
+
+ in.bounds:
+  %addr = getelementptr i32, i32* %arr, i32 %array.idx
+  store i32 0, i32* %addr
+  %next = icmp slt i32 %idx.next, %n
+  br i1 %next, label %loop, label %exit
+
+ out.of.bounds:
+  ret void
+
+ exit:
+  ret void
+}
+
+; CHECK-LABEL: loop.preheader:
+; CHECK: [[not_safe_start:[^ ]+]] = add i32 %offset, -1
+; CHECK: [[not_n:[^ ]+]] = sub i32 -1, %n
+; CHECK: [[not_exit_preloop_at_cond_loclamp:[^ ]+]] = icmp sgt i32 [[not_safe_start]], [[not_n]]
+; CHECK: [[not_exit_preloop_at_loclamp:[^ ]+]] = select i1 [[not_exit_preloop_at_cond_loclamp]], i32 [[not_safe_start]], i32 [[not_n]]
+; CHECK: [[exit_preloop_at_loclamp:[^ ]+]] = sub i32 -1, [[not_exit_preloop_at_loclamp]]
+; CHECK: [[exit_preloop_at_cond:[^ ]+]] = icmp sgt i32 [[exit_preloop_at_loclamp]], 0
+; CHECK: [[exit_preloop_at:[^ ]+]] = select i1 [[exit_preloop_at_cond]], i32 [[exit_preloop_at_loclamp]], i32 0
+
+
+; CHECK: [[not_safe_start_2:[^ ]+]] = add i32 %offset, -1
+; CHECK: [[not_safe_end:[^ ]+]] = sub i32 [[not_safe_start_2]], %len
+; CHECK: [[not_exit_mainloop_at_cond_loclamp:[^ ]+]] = icmp sgt i32 [[not_safe_end]], [[not_n]]
+; CHECK: [[not_exit_mainloop_at_loclamp:[^ ]+]] = select i1 [[not_exit_mainloop_at_cond_loclamp]], i32 [[not_safe_end]], i32 [[not_n]]
+; CHECK: [[exit_mainloop_at_loclamp:[^ ]+]] = sub i32 -1, [[not_exit_mainloop_at_loclamp]]
+; CHECK: [[exit_mainloop_at_cmp:[^ ]+]] = icmp sgt i32 [[exit_mainloop_at_loclamp]], 0
+; CHECK: [[exit_mainloop_at:[^ ]+]] = select i1 [[exit_mainloop_at_cmp]], i32 [[exit_mainloop_at_loclamp]], i32 0
+
+
+; CHECK-LABEL: in.bounds:
+; CHECK: [[continue_mainloop_cond:[^ ]+]] = icmp slt i32 %idx.next, [[exit_mainloop_at]]
+; CHECK: br i1 [[continue_mainloop_cond]], label %loop, label %main.exit.selector
+
+; CHECK-LABEL: main.exit.selector:
+; CHECK: [[mainloop_its_left:[^ ]+]] = icmp slt i32 %idx.next, %n
+; CHECK: br i1 [[mainloop_its_left]], label %main.pseudo.exit, label %exit.loopexit
+
+; CHECK-LABEL: in.bounds.preloop:
+; CHECK: [[continue_preloop_cond:[^ ]+]] = icmp slt i32 %idx.next.preloop, [[exit_preloop_at]]
+; CHECK: br i1 [[continue_preloop_cond]], label %loop.preloop, label %preloop.exit.selector
+
+; CHECK-LABEL: preloop.exit.selector:
+; CHECK: [[preloop_its_left:[^ ]+]] = icmp slt i32 %idx.next.preloop, %n
+; CHECK: br i1 [[preloop_its_left]], label %preloop.pseudo.exit, label %exit.loopexit
+
+; CHECK-LABEL: in.bounds.postloop:
+; CHECK: %next.postloop = icmp slt i32 %idx.next.postloop, %n
+; CHECK: br i1 %next.postloop, label %loop.postloop, label %exit.loopexit
+
+!0 = !{i32 0, i32 2147483647}
+!1 = !{!"branch_weights", i32 64, i32 4}
diff --git a/test/Transforms/IRCE/unhandled.ll b/test/Transforms/IRCE/unhandled.ll
new file mode 100644
index 000000000000..0d5ff953aa3b
--- /dev/null
+++ b/test/Transforms/IRCE/unhandled.ll
@@ -0,0 +1,37 @@
+; RUN: opt -irce-print-changed-loops -irce -S < %s 2>&1 | FileCheck %s
+
+; Demonstrates that we don't currently handle the general expression
+; `A * I + B'.
+
+define void @general_affine_expressions(i32 *%arr, i32 *%a_len_ptr, i32 %n,
+                                        i32 %scale, i32 %offset) {
+; CHECK-NOT: constrained Loop at depth
+ entry:
+  %len = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check = icmp sgt i32 %n, 0
+  br i1 %first.itr.check, label %loop, label %exit
+
+ loop:
+  %idx = phi i32 [ 0, %entry ] , [ %idx.next, %in.bounds ]
+  %idx.next = add i32 %idx, 1
+  %idx.mul = mul i32 %idx, %scale
+  %array.idx = add i32 %idx.mul, %offset
+  %abc.high = icmp slt i32 %array.idx, %len
+  %abc.low = icmp sge i32 %array.idx, 0
+  %abc = and i1 %abc.low, %abc.high
+  br i1 %abc, label %in.bounds, label %out.of.bounds
+
+ in.bounds:
+  %addr = getelementptr i32, i32* %arr, i32 %array.idx
+  store i32 0, i32* %addr
+  %next = icmp slt i32 %idx.next, %n
+  br i1 %next, label %loop, label %exit
+
+ out.of.bounds:
+  ret void
+
+ exit:
+  ret void
+}
+
+!0 = !{i32 0, i32 2147483647}
diff --git a/test/Transforms/IRCE/with-parent-loops.ll b/test/Transforms/IRCE/with-parent-loops.ll
new file mode 100644
index 000000000000..00af20b964f8
--- /dev/null
+++ b/test/Transforms/IRCE/with-parent-loops.ll
@@ -0,0 +1,345 @@
+; RUN: opt -verify-loop-info -irce-print-changed-loops -irce < %s 2>&1 | FileCheck %s
+
+; This test checks if we update the LoopInfo correctly in the presence
+; of parents, uncles and cousins.
+
+; Function Attrs: alwaysinline
+define void @inner_loop(i32* %arr, i32* %a_len_ptr, i32 %n) #0 {
+; CHECK: irce: in function inner_loop: constrained Loop at depth 1 containing: %loop<header><exiting>,%in.bounds<latch><exiting>
+
+entry:
+  %len = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check = icmp sgt i32 %n, 0
+  br i1 %first.itr.check, label %loop, label %exit
+
+loop:                                             ; preds = %in.bounds, %entry
+  %idx = phi i32 [ 0, %entry ], [ %idx.next, %in.bounds ]
+  %idx.next = add i32 %idx, 1
+  %abc = icmp slt i32 %idx, %len
+  br i1 %abc, label %in.bounds, label %out.of.bounds, !prof !1
+
+in.bounds:                                        ; preds = %loop
+  %addr = getelementptr i32, i32* %arr, i32 %idx
+  store i32 0, i32* %addr
+  %next = icmp slt i32 %idx.next, %n
+  br i1 %next, label %loop, label %exit
+
+out.of.bounds:                                    ; preds = %loop
+  ret void
+
+exit:                                             ; preds = %in.bounds, %entry
+  ret void
+}
+
+; Function Attrs: alwaysinline
+define void @with_parent(i32* %arr, i32* %a_len_ptr, i32 %n, i32 %parent.count) #0 {
+; CHECK: irce: in function with_parent: constrained Loop at depth 2 containing: %loop.i<header><exiting>,%in.bounds.i<latch><exiting>
+
+entry:
+  br label %loop
+
+loop:                                             ; preds = %inner_loop.exit, %entry
+  %idx = phi i32 [ 0, %entry ], [ %idx.next, %inner_loop.exit ]
+  %idx.next = add i32 %idx, 1
+  %next = icmp ult i32 %idx.next, %parent.count
+  %len.i = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check.i = icmp sgt i32 %n, 0
+  br i1 %first.itr.check.i, label %loop.i, label %exit.i
+
+loop.i:                                           ; preds = %in.bounds.i, %loop
+  %idx.i = phi i32 [ 0, %loop ], [ %idx.next.i, %in.bounds.i ]
+  %idx.next.i = add i32 %idx.i, 1
+  %abc.i = icmp slt i32 %idx.i, %len.i
+  br i1 %abc.i, label %in.bounds.i, label %out.of.bounds.i, !prof !1
+
+in.bounds.i:                                      ; preds = %loop.i
+  %addr.i = getelementptr i32, i32* %arr, i32 %idx.i
+  store i32 0, i32* %addr.i
+  %next.i = icmp slt i32 %idx.next.i, %n
+  br i1 %next.i, label %loop.i, label %exit.i
+
+out.of.bounds.i:                                  ; preds = %loop.i
+  br label %inner_loop.exit
+
+exit.i:                                           ; preds = %in.bounds.i, %loop
+  br label %inner_loop.exit
+
+inner_loop.exit:                                  ; preds = %exit.i, %out.of.bounds.i
+  br i1 %next, label %loop, label %exit
+
+exit:                                             ; preds = %inner_loop.exit
+  ret void
+}
+
+; Function Attrs: alwaysinline
+define void @with_grandparent(i32* %arr, i32* %a_len_ptr, i32 %n, i32 %parent.count, i32 %grandparent.count) #0 {
+; CHECK: irce: in function with_grandparent: constrained Loop at depth 3 containing: %loop.i.i<header><exiting>,%in.bounds.i.i<latch><exiting>
+
+entry:
+  br label %loop
+
+loop:                                             ; preds = %with_parent.exit, %entry
+  %idx = phi i32 [ 0, %entry ], [ %idx.next, %with_parent.exit ]
+  %idx.next = add i32 %idx, 1
+  %next = icmp ult i32 %idx.next, %grandparent.count
+  br label %loop.i
+
+loop.i:                                           ; preds = %inner_loop.exit.i, %loop
+  %idx.i = phi i32 [ 0, %loop ], [ %idx.next.i, %inner_loop.exit.i ]
+  %idx.next.i = add i32 %idx.i, 1
+  %next.i = icmp ult i32 %idx.next.i, %parent.count
+  %len.i.i = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check.i.i = icmp sgt i32 %n, 0
+  br i1 %first.itr.check.i.i, label %loop.i.i, label %exit.i.i
+
+loop.i.i:                                         ; preds = %in.bounds.i.i, %loop.i
+  %idx.i.i = phi i32 [ 0, %loop.i ], [ %idx.next.i.i, %in.bounds.i.i ]
+  %idx.next.i.i = add i32 %idx.i.i, 1
+  %abc.i.i = icmp slt i32 %idx.i.i, %len.i.i
+  br i1 %abc.i.i, label %in.bounds.i.i, label %out.of.bounds.i.i, !prof !1
+
+in.bounds.i.i:                                    ; preds = %loop.i.i
+  %addr.i.i = getelementptr i32, i32* %arr, i32 %idx.i.i
+  store i32 0, i32* %addr.i.i
+  %next.i.i = icmp slt i32 %idx.next.i.i, %n
+  br i1 %next.i.i, label %loop.i.i, label %exit.i.i
+
+out.of.bounds.i.i:                                ; preds = %loop.i.i
+  br label %inner_loop.exit.i
+
+exit.i.i:                                         ; preds = %in.bounds.i.i, %loop.i
+  br label %inner_loop.exit.i
+
+inner_loop.exit.i:                                ; preds = %exit.i.i, %out.of.bounds.i.i
+  br i1 %next.i, label %loop.i, label %with_parent.exit
+
+with_parent.exit:                                 ; preds = %inner_loop.exit.i
+  br i1 %next, label %loop, label %exit
+
+exit:                                             ; preds = %with_parent.exit
+  ret void
+}
+
+; Function Attrs: alwaysinline
+define void @with_sibling(i32* %arr, i32* %a_len_ptr, i32 %n, i32 %parent.count) #0 {
+; CHECK: irce: in function with_sibling: constrained Loop at depth 2 containing: %loop.i<header><exiting>,%in.bounds.i<latch><exiting>
+; CHECK: irce: in function with_sibling: constrained Loop at depth 2 containing: %loop.i6<header><exiting>,%in.bounds.i9<latch><exiting>
+
+entry:
+  br label %loop
+
+loop:                                             ; preds = %inner_loop.exit12, %entry
+  %idx = phi i32 [ 0, %entry ], [ %idx.next, %inner_loop.exit12 ]
+  %idx.next = add i32 %idx, 1
+  %next = icmp ult i32 %idx.next, %parent.count
+  %len.i = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check.i = icmp sgt i32 %n, 0
+  br i1 %first.itr.check.i, label %loop.i, label %exit.i
+
+loop.i:                                           ; preds = %in.bounds.i, %loop
+  %idx.i = phi i32 [ 0, %loop ], [ %idx.next.i, %in.bounds.i ]
+  %idx.next.i = add i32 %idx.i, 1
+  %abc.i = icmp slt i32 %idx.i, %len.i
+  br i1 %abc.i, label %in.bounds.i, label %out.of.bounds.i, !prof !1
+
+in.bounds.i:                                      ; preds = %loop.i
+  %addr.i = getelementptr i32, i32* %arr, i32 %idx.i
+  store i32 0, i32* %addr.i
+  %next.i = icmp slt i32 %idx.next.i, %n
+  br i1 %next.i, label %loop.i, label %exit.i
+
+out.of.bounds.i:                                  ; preds = %loop.i
+  br label %inner_loop.exit
+
+exit.i:                                           ; preds = %in.bounds.i, %loop
+  br label %inner_loop.exit
+
+inner_loop.exit:                                  ; preds = %exit.i, %out.of.bounds.i
+  %len.i1 = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check.i2 = icmp sgt i32 %n, 0
+  br i1 %first.itr.check.i2, label %loop.i6, label %exit.i11
+
+loop.i6:                                          ; preds = %in.bounds.i9, %inner_loop.exit
+  %idx.i3 = phi i32 [ 0, %inner_loop.exit ], [ %idx.next.i4, %in.bounds.i9 ]
+  %idx.next.i4 = add i32 %idx.i3, 1
+  %abc.i5 = icmp slt i32 %idx.i3, %len.i1
+  br i1 %abc.i5, label %in.bounds.i9, label %out.of.bounds.i10, !prof !1
+
+in.bounds.i9:                                     ; preds = %loop.i6
+  %addr.i7 = getelementptr i32, i32* %arr, i32 %idx.i3
+  store i32 0, i32* %addr.i7
+  %next.i8 = icmp slt i32 %idx.next.i4, %n
+  br i1 %next.i8, label %loop.i6, label %exit.i11
+
+out.of.bounds.i10:                                ; preds = %loop.i6
+  br label %inner_loop.exit12
+
+exit.i11:                                         ; preds = %in.bounds.i9, %inner_loop.exit
+  br label %inner_loop.exit12
+
+inner_loop.exit12:                                ; preds = %exit.i11, %out.of.bounds.i10
+  br i1 %next, label %loop, label %exit
+
+exit:                                             ; preds = %inner_loop.exit12
+  ret void
+}
+
+; Function Attrs: alwaysinline
+define void @with_cousin(i32* %arr, i32* %a_len_ptr, i32 %n, i32 %parent.count, i32 %grandparent.count) #0 {
+; CHECK: irce: in function with_cousin: constrained Loop at depth 3 containing: %loop.i.i<header><exiting>,%in.bounds.i.i<latch><exiting>
+; CHECK: irce: in function with_cousin: constrained Loop at depth 3 containing: %loop.i.i10<header><exiting>,%in.bounds.i.i13<latch><exiting>
+
+entry:
+  br label %loop
+
+loop:                                             ; preds = %with_parent.exit17, %entry
+  %idx = phi i32 [ 0, %entry ], [ %idx.next, %with_parent.exit17 ]
+  %idx.next = add i32 %idx, 1
+  %next = icmp ult i32 %idx.next, %grandparent.count
+  br label %loop.i
+
+loop.i:                                           ; preds = %inner_loop.exit.i, %loop
+  %idx.i = phi i32 [ 0, %loop ], [ %idx.next.i, %inner_loop.exit.i ]
+  %idx.next.i = add i32 %idx.i, 1
+  %next.i = icmp ult i32 %idx.next.i, %parent.count
+  %len.i.i = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check.i.i = icmp sgt i32 %n, 0
+  br i1 %first.itr.check.i.i, label %loop.i.i, label %exit.i.i
+
+loop.i.i:                                         ; preds = %in.bounds.i.i, %loop.i
+  %idx.i.i = phi i32 [ 0, %loop.i ], [ %idx.next.i.i, %in.bounds.i.i ]
+  %idx.next.i.i = add i32 %idx.i.i, 1
+  %abc.i.i = icmp slt i32 %idx.i.i, %len.i.i
+  br i1 %abc.i.i, label %in.bounds.i.i, label %out.of.bounds.i.i, !prof !1
+
+in.bounds.i.i:                                    ; preds = %loop.i.i
+  %addr.i.i = getelementptr i32, i32* %arr, i32 %idx.i.i
+  store i32 0, i32* %addr.i.i
+  %next.i.i = icmp slt i32 %idx.next.i.i, %n
+  br i1 %next.i.i, label %loop.i.i, label %exit.i.i
+
+out.of.bounds.i.i:                                ; preds = %loop.i.i
+  br label %inner_loop.exit.i
+
+exit.i.i:                                         ; preds = %in.bounds.i.i, %loop.i
+  br label %inner_loop.exit.i
+
+inner_loop.exit.i:                                ; preds = %exit.i.i, %out.of.bounds.i.i
+  br i1 %next.i, label %loop.i, label %with_parent.exit
+
+with_parent.exit:                                 ; preds = %inner_loop.exit.i
+  br label %loop.i6
+
+loop.i6:                                          ; preds = %inner_loop.exit.i16, %with_parent.exit
+  %idx.i1 = phi i32 [ 0, %with_parent.exit ], [ %idx.next.i2, %inner_loop.exit.i16 ]
+  %idx.next.i2 = add i32 %idx.i1, 1
+  %next.i3 = icmp ult i32 %idx.next.i2, %parent.count
+  %len.i.i4 = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check.i.i5 = icmp sgt i32 %n, 0
+  br i1 %first.itr.check.i.i5, label %loop.i.i10, label %exit.i.i15
+
+loop.i.i10:                                       ; preds = %in.bounds.i.i13, %loop.i6
+  %idx.i.i7 = phi i32 [ 0, %loop.i6 ], [ %idx.next.i.i8, %in.bounds.i.i13 ]
+  %idx.next.i.i8 = add i32 %idx.i.i7, 1
+  %abc.i.i9 = icmp slt i32 %idx.i.i7, %len.i.i4
+  br i1 %abc.i.i9, label %in.bounds.i.i13, label %out.of.bounds.i.i14, !prof !1
+
+in.bounds.i.i13:                                  ; preds = %loop.i.i10
+  %addr.i.i11 = getelementptr i32, i32* %arr, i32 %idx.i.i7
+  store i32 0, i32* %addr.i.i11
+  %next.i.i12 = icmp slt i32 %idx.next.i.i8, %n
+  br i1 %next.i.i12, label %loop.i.i10, label %exit.i.i15
+
+out.of.bounds.i.i14:                              ; preds = %loop.i.i10
+  br label %inner_loop.exit.i16
+
+exit.i.i15:                                       ; preds = %in.bounds.i.i13, %loop.i6
+  br label %inner_loop.exit.i16
+
+inner_loop.exit.i16:                              ; preds = %exit.i.i15, %out.of.bounds.i.i14
+  br i1 %next.i3, label %loop.i6, label %with_parent.exit17
+
+with_parent.exit17:                               ; preds = %inner_loop.exit.i16
+  br i1 %next, label %loop, label %exit
+
+exit:                                             ; preds = %with_parent.exit17
+  ret void
+}
+
+; Function Attrs: alwaysinline
+define void @with_uncle(i32* %arr, i32* %a_len_ptr, i32 %n, i32 %parent.count, i32 %grandparent.count) #0 {
+; CHECK: irce: in function with_uncle: constrained Loop at depth 2 containing: %loop.i<header><exiting>,%in.bounds.i<latch><exiting>
+; CHECK: irce: in function with_uncle: constrained Loop at depth 3 containing: %loop.i.i<header><exiting>,%in.bounds.i.i<latch><exiting>
+
+entry:
+  br label %loop
+
+loop:                                             ; preds = %with_parent.exit, %entry
+  %idx = phi i32 [ 0, %entry ], [ %idx.next, %with_parent.exit ]
+  %idx.next = add i32 %idx, 1
+  %next = icmp ult i32 %idx.next, %grandparent.count
+  %len.i = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check.i = icmp sgt i32 %n, 0
+  br i1 %first.itr.check.i, label %loop.i, label %exit.i
+
+loop.i:                                           ; preds = %in.bounds.i, %loop
+  %idx.i = phi i32 [ 0, %loop ], [ %idx.next.i, %in.bounds.i ]
+  %idx.next.i = add i32 %idx.i, 1
+  %abc.i = icmp slt i32 %idx.i, %len.i
+  br i1 %abc.i, label %in.bounds.i, label %out.of.bounds.i, !prof !1
+
+in.bounds.i:                                      ; preds = %loop.i
+  %addr.i = getelementptr i32, i32* %arr, i32 %idx.i
+  store i32 0, i32* %addr.i
+  %next.i = icmp slt i32 %idx.next.i, %n
+  br i1 %next.i, label %loop.i, label %exit.i
+
+out.of.bounds.i:                                  ; preds = %loop.i
+  br label %inner_loop.exit
+
+exit.i:                                           ; preds = %in.bounds.i, %loop
+  br label %inner_loop.exit
+
+inner_loop.exit:                                  ; preds = %exit.i, %out.of.bounds.i
+  br label %loop.i4
+
+loop.i4:                                          ; preds = %inner_loop.exit.i, %inner_loop.exit
+  %idx.i1 = phi i32 [ 0, %inner_loop.exit ], [ %idx.next.i2, %inner_loop.exit.i ]
+  %idx.next.i2 = add i32 %idx.i1, 1
+  %next.i3 = icmp ult i32 %idx.next.i2, %parent.count
+  %len.i.i = load i32, i32* %a_len_ptr, !range !0
+  %first.itr.check.i.i = icmp sgt i32 %n, 0
+  br i1 %first.itr.check.i.i, label %loop.i.i, label %exit.i.i
+
+loop.i.i:                                         ; preds = %in.bounds.i.i, %loop.i4
+  %idx.i.i = phi i32 [ 0, %loop.i4 ], [ %idx.next.i.i, %in.bounds.i.i ]
+  %idx.next.i.i = add i32 %idx.i.i, 1
+  %abc.i.i = icmp slt i32 %idx.i.i, %len.i.i
+  br i1 %abc.i.i, label %in.bounds.i.i, label %out.of.bounds.i.i, !prof !1
+
+in.bounds.i.i:                                    ; preds = %loop.i.i
+  %addr.i.i = getelementptr i32, i32* %arr, i32 %idx.i.i
+  store i32 0, i32* %addr.i.i
+  %next.i.i = icmp slt i32 %idx.next.i.i, %n
+  br i1 %next.i.i, label %loop.i.i, label %exit.i.i
+
+out.of.bounds.i.i:                                ; preds = %loop.i.i
+  br label %inner_loop.exit.i
+
+exit.i.i:                                         ; preds = %in.bounds.i.i, %loop.i4
+  br label %inner_loop.exit.i
+
+inner_loop.exit.i:                                ; preds = %exit.i.i, %out.of.bounds.i.i
+  br i1 %next.i3, label %loop.i4, label %with_parent.exit
+
+with_parent.exit:                                 ; preds = %inner_loop.exit.i
+  br i1 %next, label %loop, label %exit
+
+exit:                                             ; preds = %with_parent.exit
+  ret void
+}
+
+attributes #0 = { alwaysinline }
+
+!0 = !{i32 0, i32 2147483647}
+!1 = !{!"branch_weights", i32 64, i32 4}
diff --git a/test/Transforms/IndVarSimplify/2005-02-17-TruncateExprCrash.ll b/test/Transforms/IndVarSimplify/2005-02-17-TruncateExprCrash.ll
index ce043beb7fd9..16ad635a9205 100644
--- a/test/Transforms/IndVarSimplify/2005-02-17-TruncateExprCrash.ll
+++ b/test/Transforms/IndVarSimplify/2005-02-17-TruncateExprCrash.ll
@@ -45,7 +45,7 @@ then.4:		; preds = %_ZNK7QString2atEi.exit
 	ret void
 
 endif.4:		; preds = %_ZNK7QString2atEi.exit
-	%tmp.115 = load i8* null		; <i8> [#uses=1]
+	%tmp.115 = load i8, i8* null		; <i8> [#uses=1]
 	br i1 false, label %loopexit.1, label %no_exit.0
 
 no_exit.0:		; preds = %no_exit.0, %endif.4
diff --git a/test/Transforms/IndVarSimplify/2005-11-18-Crash.ll b/test/Transforms/IndVarSimplify/2005-11-18-Crash.ll
index 7202c7ae9d8d..7ef351d4a456 100644
--- a/test/Transforms/IndVarSimplify/2005-11-18-Crash.ll
+++ b/test/Transforms/IndVarSimplify/2005-11-18-Crash.ll
@@ -7,8 +7,8 @@ entry:
         br label %no_exit.0
 
 no_exit.0:              ; preds = %no_exit.0, %entry
-        %p.0.0 = phi i32* [ getelementptr ([29 x [29 x [2 x i32]]]* @fixtab, i32 0, i32 0, i32 0, i32 0), %entry ], [ %inc.0, %no_exit.0 ]               ; <i32*> [#uses=1]
-        %inc.0 = getelementptr i32* %p.0.0, i32 1               ; <i32*> [#uses=1]
+        %p.0.0 = phi i32* [ getelementptr ([29 x [29 x [2 x i32]]], [29 x [29 x [2 x i32]]]* @fixtab, i32 0, i32 0, i32 0, i32 0), %entry ], [ %inc.0, %no_exit.0 ]               ; <i32*> [#uses=1]
+        %inc.0 = getelementptr i32, i32* %p.0.0, i32 1               ; <i32*> [#uses=1]
         br i1 undef, label %no_exit.0, label %no_exit.1
 
 no_exit.1:              ; preds = %no_exit.0
diff --git a/test/Transforms/IndVarSimplify/2006-06-16-Indvar-LCSSA-Crash.ll b/test/Transforms/IndVarSimplify/2006-06-16-Indvar-LCSSA-Crash.ll
index 36ec2b81ba73..2d40f88d0d0b 100644
--- a/test/Transforms/IndVarSimplify/2006-06-16-Indvar-LCSSA-Crash.ll
+++ b/test/Transforms/IndVarSimplify/2006-06-16-Indvar-LCSSA-Crash.ll
@@ -6,9 +6,9 @@ endif.0:
 
 no_exit.30:             ; preds = %no_exit.30, %endif.0
         %x.12.0 = phi i32 [ %inc.28, %no_exit.30 ], [ -2, %endif.0 ]            ; <i32> [#uses=1]
-        %tmp.583 = load i16* null               ; <i16> [#uses=1]
+        %tmp.583 = load i16, i16* null               ; <i16> [#uses=1]
         %tmp.584 = zext i16 %tmp.583 to i32             ; <i32> [#uses=1]
-        %tmp.588 = load i32* null               ; <i32> [#uses=1]
+        %tmp.588 = load i32, i32* null               ; <i32> [#uses=1]
         %tmp.589 = mul i32 %tmp.584, %tmp.588           ; <i32> [#uses=1]
         %tmp.591 = add i32 %tmp.589, 0          ; <i32> [#uses=1]
         %inc.28 = add i32 %x.12.0, 1            ; <i32> [#uses=2]
diff --git a/test/Transforms/IndVarSimplify/2007-01-06-TripCount.ll b/test/Transforms/IndVarSimplify/2007-01-06-TripCount.ll
index 6366c8c0516c..3dda657a6d70 100644
--- a/test/Transforms/IndVarSimplify/2007-01-06-TripCount.ll
+++ b/test/Transforms/IndVarSimplify/2007-01-06-TripCount.ll
@@ -24,8 +24,8 @@ cond_true:		; preds = %bb2
 	br label %bb
 
 cond_next:		; preds = %bb2
-	%tmp2 = getelementptr [5 x i8]* @foo, i32 0, i32 %i.0		; <i8*> [#uses=1]
-	%tmp3 = load i8* %tmp2		; <i8> [#uses=1]
+	%tmp2 = getelementptr [5 x i8], [5 x i8]* @foo, i32 0, i32 %i.0		; <i8*> [#uses=1]
+	%tmp3 = load i8, i8* %tmp2		; <i8> [#uses=1]
 	%tmp5 = icmp eq i8 %tmp3, 0		; <i1> [#uses=1]
 	br i1 %tmp5, label %bb6, label %bb
 
diff --git a/test/Transforms/IndVarSimplify/2008-09-02-IVType.ll b/test/Transforms/IndVarSimplify/2008-09-02-IVType.ll
index a00483164fb1..58934f5ef84b 100644
--- a/test/Transforms/IndVarSimplify/2008-09-02-IVType.ll
+++ b/test/Transforms/IndVarSimplify/2008-09-02-IVType.ll
@@ -1,6 +1,10 @@
 ; RUN: opt < %s -indvars -S | grep sext | count 1
 ; ModuleID = '<stdin>'
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+
 	%struct.App1Marker = type <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }>
 	%struct.ComponentInstanceRecord = type <{ [1 x i32] }>
 	%struct.DCPredictors = type { [5 x i16] }
@@ -18,18 +22,18 @@
 
 define signext i16 @ExtractBufferedBlocksIgnored(%struct.JPEGGlobals* %globp)  nounwind {
 entry:
-	%tmp4311 = getelementptr %struct.JPEGGlobals* %globp, i32 0, i32 70		; <i32*> [#uses=1]
-	%tmp4412 = load i32* %tmp4311, align 16		; <i32> [#uses=2]
+	%tmp4311 = getelementptr %struct.JPEGGlobals, %struct.JPEGGlobals* %globp, i32 0, i32 70		; <i32*> [#uses=1]
+	%tmp4412 = load i32, i32* %tmp4311, align 16		; <i32> [#uses=2]
 	%tmp4613 = icmp sgt i32 %tmp4412, 0		; <i1> [#uses=1]
 	br i1 %tmp4613, label %bb, label %bb49
 
 bb:		; preds = %bb28, %entry
 	%component.09 = phi i16 [ 0, %entry ], [ %tmp37, %bb28 ]		; <i16> [#uses=2]
 	%tmp12 = sext i16 %component.09 to i32		; <i32> [#uses=2]
-	%tmp6 = getelementptr %struct.JPEGGlobals* %globp, i32 0, i32 77, i32 %tmp12		; <i16**> [#uses=2]
-	%tmp7 = load i16** %tmp6, align 4		; <i16*> [#uses=2]
-	%tmp235 = getelementptr %struct.JPEGGlobals* %globp, i32 0, i32 71, i32 %tmp12		; <i32*> [#uses=1]
-	%tmp246 = load i32* %tmp235, align 4		; <i32> [#uses=2]
+	%tmp6 = getelementptr %struct.JPEGGlobals, %struct.JPEGGlobals* %globp, i32 0, i32 77, i32 %tmp12		; <i16**> [#uses=2]
+	%tmp7 = load i16*, i16** %tmp6, align 4		; <i16*> [#uses=2]
+	%tmp235 = getelementptr %struct.JPEGGlobals, %struct.JPEGGlobals* %globp, i32 0, i32 71, i32 %tmp12		; <i32*> [#uses=1]
+	%tmp246 = load i32, i32* %tmp235, align 4		; <i32> [#uses=2]
 	%tmp267 = icmp sgt i32 %tmp246, 0		; <i1> [#uses=1]
 	br i1 %tmp267, label %bb8, label %bb28
 
@@ -37,7 +41,7 @@ bb8:		; preds = %bb8, %bb
 	%indvar = phi i32 [ 0, %bb ], [ %indvar.next2, %bb8 ]		; <i32> [#uses=3]
 	%theDCTBufferIter.01.rec = shl i32 %indvar, 6		; <i32> [#uses=1]
 	%tmp10.rec = add i32 %theDCTBufferIter.01.rec, 64		; <i32> [#uses=1]
-	%tmp10 = getelementptr i16* %tmp7, i32 %tmp10.rec		; <i16*> [#uses=1]
+	%tmp10 = getelementptr i16, i16* %tmp7, i32 %tmp10.rec		; <i16*> [#uses=1]
 	%i.02 = trunc i32 %indvar to i16		; <i16> [#uses=1]
 	%tmp13 = add i16 %i.02, 1		; <i16> [#uses=1]
 	%phitmp = sext i16 %tmp13 to i32		; <i32> [#uses=1]
diff --git a/test/Transforms/IndVarSimplify/2008-10-03-CouldNotCompute.ll b/test/Transforms/IndVarSimplify/2008-10-03-CouldNotCompute.ll
index 23e788496138..1248154c1551 100644
--- a/test/Transforms/IndVarSimplify/2008-10-03-CouldNotCompute.ll
+++ b/test/Transforms/IndVarSimplify/2008-10-03-CouldNotCompute.ll
@@ -8,7 +8,7 @@ entry:
 	br i1 false, label %bb.nph, label %return
 
 bb.nph:		; preds = %entry
-	%0 = load i32* @foo, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* @foo, align 4		; <i32> [#uses=1]
 	%1 = sext i32 %0 to i64		; <i64> [#uses=1]
 	br label %bb
 
diff --git a/test/Transforms/IndVarSimplify/2009-04-14-shorten_iv_vars.ll b/test/Transforms/IndVarSimplify/2009-04-14-shorten_iv_vars.ll
index b4615668136b..ab2af329f4d5 100644
--- a/test/Transforms/IndVarSimplify/2009-04-14-shorten_iv_vars.ll
+++ b/test/Transforms/IndVarSimplify/2009-04-14-shorten_iv_vars.ll
@@ -15,95 +15,95 @@ bb1.thread:
 
 bb1:		; preds = %bb1, %bb1.thread
 	%i.0.reg2mem.0 = phi i32 [ 0, %bb1.thread ], [ %84, %bb1 ]		; <i32> [#uses=19]
-	%0 = load i32** @a, align 8		; <i32*> [#uses=1]
-	%1 = load i32** @b, align 8		; <i32*> [#uses=1]
+	%0 = load i32*, i32** @a, align 8		; <i32*> [#uses=1]
+	%1 = load i32*, i32** @b, align 8		; <i32*> [#uses=1]
 	%2 = sext i32 %i.0.reg2mem.0 to i64		; <i64> [#uses=1]
-	%3 = getelementptr i32* %1, i64 %2		; <i32*> [#uses=1]
-	%4 = load i32* %3, align 1		; <i32> [#uses=1]
-	%5 = load i32** @c, align 8		; <i32*> [#uses=1]
+	%3 = getelementptr i32, i32* %1, i64 %2		; <i32*> [#uses=1]
+	%4 = load i32, i32* %3, align 1		; <i32> [#uses=1]
+	%5 = load i32*, i32** @c, align 8		; <i32*> [#uses=1]
 	%6 = sext i32 %i.0.reg2mem.0 to i64		; <i64> [#uses=1]
-	%7 = getelementptr i32* %5, i64 %6		; <i32*> [#uses=1]
-	%8 = load i32* %7, align 1		; <i32> [#uses=1]
+	%7 = getelementptr i32, i32* %5, i64 %6		; <i32*> [#uses=1]
+	%8 = load i32, i32* %7, align 1		; <i32> [#uses=1]
 	%9 = add i32 %8, %4		; <i32> [#uses=1]
 	%10 = sext i32 %i.0.reg2mem.0 to i64		; <i64> [#uses=1]
-	%11 = getelementptr i32* %0, i64 %10		; <i32*> [#uses=1]
+	%11 = getelementptr i32, i32* %0, i64 %10		; <i32*> [#uses=1]
 	store i32 %9, i32* %11, align 1
-	%12 = load i32** @a, align 8		; <i32*> [#uses=1]
+	%12 = load i32*, i32** @a, align 8		; <i32*> [#uses=1]
 	%13 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=1]
-	%14 = load i32** @b, align 8		; <i32*> [#uses=1]
+	%14 = load i32*, i32** @b, align 8		; <i32*> [#uses=1]
 	%15 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=1]
 	%16 = sext i32 %15 to i64		; <i64> [#uses=1]
-	%17 = getelementptr i32* %14, i64 %16		; <i32*> [#uses=1]
-	%18 = load i32* %17, align 1		; <i32> [#uses=1]
-	%19 = load i32** @c, align 8		; <i32*> [#uses=1]
+	%17 = getelementptr i32, i32* %14, i64 %16		; <i32*> [#uses=1]
+	%18 = load i32, i32* %17, align 1		; <i32> [#uses=1]
+	%19 = load i32*, i32** @c, align 8		; <i32*> [#uses=1]
 	%20 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=1]
 	%21 = sext i32 %20 to i64		; <i64> [#uses=1]
-	%22 = getelementptr i32* %19, i64 %21		; <i32*> [#uses=1]
-	%23 = load i32* %22, align 1		; <i32> [#uses=1]
+	%22 = getelementptr i32, i32* %19, i64 %21		; <i32*> [#uses=1]
+	%23 = load i32, i32* %22, align 1		; <i32> [#uses=1]
 	%24 = add i32 %23, %18		; <i32> [#uses=1]
 	%25 = sext i32 %13 to i64		; <i64> [#uses=1]
-	%26 = getelementptr i32* %12, i64 %25		; <i32*> [#uses=1]
+	%26 = getelementptr i32, i32* %12, i64 %25		; <i32*> [#uses=1]
 	store i32 %24, i32* %26, align 1
-	%27 = load i32** @a, align 8		; <i32*> [#uses=1]
+	%27 = load i32*, i32** @a, align 8		; <i32*> [#uses=1]
 	%28 = add i32 %i.0.reg2mem.0, 2		; <i32> [#uses=1]
-	%29 = load i32** @b, align 8		; <i32*> [#uses=1]
+	%29 = load i32*, i32** @b, align 8		; <i32*> [#uses=1]
 	%30 = add i32 %i.0.reg2mem.0, 2		; <i32> [#uses=1]
 	%31 = sext i32 %30 to i64		; <i64> [#uses=1]
-	%32 = getelementptr i32* %29, i64 %31		; <i32*> [#uses=1]
-	%33 = load i32* %32, align 1		; <i32> [#uses=1]
-	%34 = load i32** @c, align 8		; <i32*> [#uses=1]
+	%32 = getelementptr i32, i32* %29, i64 %31		; <i32*> [#uses=1]
+	%33 = load i32, i32* %32, align 1		; <i32> [#uses=1]
+	%34 = load i32*, i32** @c, align 8		; <i32*> [#uses=1]
 	%35 = add i32 %i.0.reg2mem.0, 2		; <i32> [#uses=1]
 	%36 = sext i32 %35 to i64		; <i64> [#uses=1]
-	%37 = getelementptr i32* %34, i64 %36		; <i32*> [#uses=1]
-	%38 = load i32* %37, align 1		; <i32> [#uses=1]
+	%37 = getelementptr i32, i32* %34, i64 %36		; <i32*> [#uses=1]
+	%38 = load i32, i32* %37, align 1		; <i32> [#uses=1]
 	%39 = add i32 %38, %33		; <i32> [#uses=1]
 	%40 = sext i32 %28 to i64		; <i64> [#uses=1]
-	%41 = getelementptr i32* %27, i64 %40		; <i32*> [#uses=1]
+	%41 = getelementptr i32, i32* %27, i64 %40		; <i32*> [#uses=1]
 	store i32 %39, i32* %41, align 1
-	%42 = load i32** @d, align 8		; <i32*> [#uses=1]
-	%43 = load i32** @e, align 8		; <i32*> [#uses=1]
+	%42 = load i32*, i32** @d, align 8		; <i32*> [#uses=1]
+	%43 = load i32*, i32** @e, align 8		; <i32*> [#uses=1]
 	%44 = sext i32 %i.0.reg2mem.0 to i64		; <i64> [#uses=1]
-	%45 = getelementptr i32* %43, i64 %44		; <i32*> [#uses=1]
-	%46 = load i32* %45, align 1		; <i32> [#uses=1]
-	%47 = load i32** @f, align 8		; <i32*> [#uses=1]
+	%45 = getelementptr i32, i32* %43, i64 %44		; <i32*> [#uses=1]
+	%46 = load i32, i32* %45, align 1		; <i32> [#uses=1]
+	%47 = load i32*, i32** @f, align 8		; <i32*> [#uses=1]
 	%48 = sext i32 %i.0.reg2mem.0 to i64		; <i64> [#uses=1]
-	%49 = getelementptr i32* %47, i64 %48		; <i32*> [#uses=1]
-	%50 = load i32* %49, align 1		; <i32> [#uses=1]
+	%49 = getelementptr i32, i32* %47, i64 %48		; <i32*> [#uses=1]
+	%50 = load i32, i32* %49, align 1		; <i32> [#uses=1]
 	%51 = add i32 %50, %46		; <i32> [#uses=1]
 	%52 = sext i32 %i.0.reg2mem.0 to i64		; <i64> [#uses=1]
-	%53 = getelementptr i32* %42, i64 %52		; <i32*> [#uses=1]
+	%53 = getelementptr i32, i32* %42, i64 %52		; <i32*> [#uses=1]
 	store i32 %51, i32* %53, align 1
-	%54 = load i32** @d, align 8		; <i32*> [#uses=1]
+	%54 = load i32*, i32** @d, align 8		; <i32*> [#uses=1]
 	%55 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=1]
-	%56 = load i32** @e, align 8		; <i32*> [#uses=1]
+	%56 = load i32*, i32** @e, align 8		; <i32*> [#uses=1]
 	%57 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=1]
 	%58 = sext i32 %57 to i64		; <i64> [#uses=1]
-	%59 = getelementptr i32* %56, i64 %58		; <i32*> [#uses=1]
-	%60 = load i32* %59, align 1		; <i32> [#uses=1]
-	%61 = load i32** @f, align 8		; <i32*> [#uses=1]
+	%59 = getelementptr i32, i32* %56, i64 %58		; <i32*> [#uses=1]
+	%60 = load i32, i32* %59, align 1		; <i32> [#uses=1]
+	%61 = load i32*, i32** @f, align 8		; <i32*> [#uses=1]
 	%62 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=1]
 	%63 = sext i32 %62 to i64		; <i64> [#uses=1]
-	%64 = getelementptr i32* %61, i64 %63		; <i32*> [#uses=1]
-	%65 = load i32* %64, align 1		; <i32> [#uses=1]
+	%64 = getelementptr i32, i32* %61, i64 %63		; <i32*> [#uses=1]
+	%65 = load i32, i32* %64, align 1		; <i32> [#uses=1]
 	%66 = add i32 %65, %60		; <i32> [#uses=1]
 	%67 = sext i32 %55 to i64		; <i64> [#uses=1]
-	%68 = getelementptr i32* %54, i64 %67		; <i32*> [#uses=1]
+	%68 = getelementptr i32, i32* %54, i64 %67		; <i32*> [#uses=1]
 	store i32 %66, i32* %68, align 1
-	%69 = load i32** @d, align 8		; <i32*> [#uses=1]
+	%69 = load i32*, i32** @d, align 8		; <i32*> [#uses=1]
 	%70 = add i32 %i.0.reg2mem.0, 2		; <i32> [#uses=1]
-	%71 = load i32** @e, align 8		; <i32*> [#uses=1]
+	%71 = load i32*, i32** @e, align 8		; <i32*> [#uses=1]
 	%72 = add i32 %i.0.reg2mem.0, 2		; <i32> [#uses=1]
 	%73 = sext i32 %72 to i64		; <i64> [#uses=1]
-	%74 = getelementptr i32* %71, i64 %73		; <i32*> [#uses=1]
-	%75 = load i32* %74, align 1		; <i32> [#uses=1]
-	%76 = load i32** @f, align 8		; <i32*> [#uses=1]
+	%74 = getelementptr i32, i32* %71, i64 %73		; <i32*> [#uses=1]
+	%75 = load i32, i32* %74, align 1		; <i32> [#uses=1]
+	%76 = load i32*, i32** @f, align 8		; <i32*> [#uses=1]
 	%77 = add i32 %i.0.reg2mem.0, 2		; <i32> [#uses=1]
 	%78 = sext i32 %77 to i64		; <i64> [#uses=1]
-	%79 = getelementptr i32* %76, i64 %78		; <i32*> [#uses=1]
-	%80 = load i32* %79, align 1		; <i32> [#uses=1]
+	%79 = getelementptr i32, i32* %76, i64 %78		; <i32*> [#uses=1]
+	%80 = load i32, i32* %79, align 1		; <i32> [#uses=1]
 	%81 = add i32 %80, %75		; <i32> [#uses=1]
 	%82 = sext i32 %70 to i64		; <i64> [#uses=1]
-	%83 = getelementptr i32* %69, i64 %82		; <i32*> [#uses=1]
+	%83 = getelementptr i32, i32* %69, i64 %82		; <i32*> [#uses=1]
 	store i32 %81, i32* %83, align 1
 	%84 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=2]
 	%85 = icmp sgt i32 %84, 23646		; <i1> [#uses=1]
diff --git a/test/Transforms/IndVarSimplify/2009-04-15-shorten-iv-vars-2.ll b/test/Transforms/IndVarSimplify/2009-04-15-shorten-iv-vars-2.ll
index 0722d8958517..921a3937aa52 100644
--- a/test/Transforms/IndVarSimplify/2009-04-15-shorten-iv-vars-2.ll
+++ b/test/Transforms/IndVarSimplify/2009-04-15-shorten-iv-vars-2.ll
@@ -29,127 +29,127 @@ bb1.thread:
 
 bb1:		; preds = %bb1, %bb1.thread
 	%i.0.reg2mem.0 = phi i32 [ 0, %bb1.thread ], [ %116, %bb1 ]		; <i32> [#uses=22]
-	%0 = load i32** @a, align 8		; <i32*> [#uses=1]
+	%0 = load i32*, i32** @a, align 8		; <i32*> [#uses=1]
 	%1 = and i32 %i.0.reg2mem.0, 15		; <i32> [#uses=1]
-	%2 = load i32** @b, align 8		; <i32*> [#uses=1]
+	%2 = load i32*, i32** @b, align 8		; <i32*> [#uses=1]
 	%3 = and i32 %i.0.reg2mem.0, 15		; <i32> [#uses=1]
 	%4 = zext i32 %3 to i64		; <i64> [#uses=1]
-	%5 = getelementptr i32* %2, i64 %4		; <i32*> [#uses=1]
-	%6 = load i32* %5, align 1		; <i32> [#uses=1]
-	%7 = load i32** @c, align 8		; <i32*> [#uses=1]
+	%5 = getelementptr i32, i32* %2, i64 %4		; <i32*> [#uses=1]
+	%6 = load i32, i32* %5, align 1		; <i32> [#uses=1]
+	%7 = load i32*, i32** @c, align 8		; <i32*> [#uses=1]
 	%8 = and i32 %i.0.reg2mem.0, 15		; <i32> [#uses=1]
 	%9 = zext i32 %8 to i64		; <i64> [#uses=1]
-	%10 = getelementptr i32* %7, i64 %9		; <i32*> [#uses=1]
-	%11 = load i32* %10, align 1		; <i32> [#uses=1]
+	%10 = getelementptr i32, i32* %7, i64 %9		; <i32*> [#uses=1]
+	%11 = load i32, i32* %10, align 1		; <i32> [#uses=1]
 	%12 = add i32 %11, %6		; <i32> [#uses=1]
 	%13 = zext i32 %1 to i64		; <i64> [#uses=1]
-	%14 = getelementptr i32* %0, i64 %13		; <i32*> [#uses=1]
+	%14 = getelementptr i32, i32* %0, i64 %13		; <i32*> [#uses=1]
 	store i32 %12, i32* %14, align 1
-	%15 = load i32** @a, align 8		; <i32*> [#uses=1]
+	%15 = load i32*, i32** @a, align 8		; <i32*> [#uses=1]
 	%16 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=1]
 	%17 = and i32 %16, 15		; <i32> [#uses=1]
-	%18 = load i32** @b, align 8		; <i32*> [#uses=1]
+	%18 = load i32*, i32** @b, align 8		; <i32*> [#uses=1]
 	%19 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=1]
 	%20 = and i32 %19, 15		; <i32> [#uses=1]
 	%21 = zext i32 %20 to i64		; <i64> [#uses=1]
-	%22 = getelementptr i32* %18, i64 %21		; <i32*> [#uses=1]
-	%23 = load i32* %22, align 1		; <i32> [#uses=1]
-	%24 = load i32** @c, align 8		; <i32*> [#uses=1]
+	%22 = getelementptr i32, i32* %18, i64 %21		; <i32*> [#uses=1]
+	%23 = load i32, i32* %22, align 1		; <i32> [#uses=1]
+	%24 = load i32*, i32** @c, align 8		; <i32*> [#uses=1]
 	%25 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=1]
 	%26 = and i32 %25, 15		; <i32> [#uses=1]
 	%27 = zext i32 %26 to i64		; <i64> [#uses=1]
-	%28 = getelementptr i32* %24, i64 %27		; <i32*> [#uses=1]
-	%29 = load i32* %28, align 1		; <i32> [#uses=1]
+	%28 = getelementptr i32, i32* %24, i64 %27		; <i32*> [#uses=1]
+	%29 = load i32, i32* %28, align 1		; <i32> [#uses=1]
 	%30 = add i32 %29, %23		; <i32> [#uses=1]
 	%31 = zext i32 %17 to i64		; <i64> [#uses=1]
-	%32 = getelementptr i32* %15, i64 %31		; <i32*> [#uses=1]
+	%32 = getelementptr i32, i32* %15, i64 %31		; <i32*> [#uses=1]
 	store i32 %30, i32* %32, align 1
-	%33 = load i32** @a, align 8		; <i32*> [#uses=1]
+	%33 = load i32*, i32** @a, align 8		; <i32*> [#uses=1]
 	%34 = add i32 %i.0.reg2mem.0, 2		; <i32> [#uses=1]
 	%35 = and i32 %34, 15		; <i32> [#uses=1]
-	%36 = load i32** @b, align 8		; <i32*> [#uses=1]
+	%36 = load i32*, i32** @b, align 8		; <i32*> [#uses=1]
 	%37 = add i32 %i.0.reg2mem.0, 2		; <i32> [#uses=1]
 	%38 = and i32 %37, 15		; <i32> [#uses=1]
 	%39 = zext i32 %38 to i64		; <i64> [#uses=1]
-	%40 = getelementptr i32* %36, i64 %39		; <i32*> [#uses=1]
-	%41 = load i32* %40, align 1		; <i32> [#uses=1]
-	%42 = load i32** @c, align 8		; <i32*> [#uses=1]
+	%40 = getelementptr i32, i32* %36, i64 %39		; <i32*> [#uses=1]
+	%41 = load i32, i32* %40, align 1		; <i32> [#uses=1]
+	%42 = load i32*, i32** @c, align 8		; <i32*> [#uses=1]
 	%43 = add i32 %i.0.reg2mem.0, 2		; <i32> [#uses=1]
 	%44 = and i32 %43, 15		; <i32> [#uses=1]
 	%45 = zext i32 %44 to i64		; <i64> [#uses=1]
-	%46 = getelementptr i32* %42, i64 %45		; <i32*> [#uses=1]
-	%47 = load i32* %46, align 1		; <i32> [#uses=1]
+	%46 = getelementptr i32, i32* %42, i64 %45		; <i32*> [#uses=1]
+	%47 = load i32, i32* %46, align 1		; <i32> [#uses=1]
 	%48 = add i32 %47, %41		; <i32> [#uses=1]
 	%49 = zext i32 %35 to i64		; <i64> [#uses=1]
-	%50 = getelementptr i32* %33, i64 %49		; <i32*> [#uses=1]
+	%50 = getelementptr i32, i32* %33, i64 %49		; <i32*> [#uses=1]
 	store i32 %48, i32* %50, align 1
-	%51 = load i32** @d, align 8		; <i32*> [#uses=1]
+	%51 = load i32*, i32** @d, align 8		; <i32*> [#uses=1]
 	%52 = and i32 %i.0.reg2mem.0, 15		; <i32> [#uses=1]
-	%53 = load i32** @e, align 8		; <i32*> [#uses=1]
+	%53 = load i32*, i32** @e, align 8		; <i32*> [#uses=1]
 	%54 = and i32 %i.0.reg2mem.0, 15		; <i32> [#uses=1]
 	%55 = zext i32 %54 to i64		; <i64> [#uses=1]
-	%56 = getelementptr i32* %53, i64 %55		; <i32*> [#uses=1]
-	%57 = load i32* %56, align 1		; <i32> [#uses=1]
-	%58 = load i32** @f, align 8		; <i32*> [#uses=1]
+	%56 = getelementptr i32, i32* %53, i64 %55		; <i32*> [#uses=1]
+	%57 = load i32, i32* %56, align 1		; <i32> [#uses=1]
+	%58 = load i32*, i32** @f, align 8		; <i32*> [#uses=1]
 	%59 = and i32 %i.0.reg2mem.0, 15		; <i32> [#uses=1]
 	%60 = zext i32 %59 to i64		; <i64> [#uses=1]
-	%61 = getelementptr i32* %58, i64 %60		; <i32*> [#uses=1]
-	%62 = load i32* %61, align 1		; <i32> [#uses=1]
+	%61 = getelementptr i32, i32* %58, i64 %60		; <i32*> [#uses=1]
+	%62 = load i32, i32* %61, align 1		; <i32> [#uses=1]
 	%63 = sext i32 %i.0.reg2mem.0 to i64		; <i64> [#uses=1]
-	%64 = getelementptr [256 x i32]* @K, i64 0, i64 %63		; <i32*> [#uses=1]
-	%65 = load i32* %64, align 4		; <i32> [#uses=1]
+	%64 = getelementptr [256 x i32], [256 x i32]* @K, i64 0, i64 %63		; <i32*> [#uses=1]
+	%65 = load i32, i32* %64, align 4		; <i32> [#uses=1]
 	%66 = add i32 %62, %57		; <i32> [#uses=1]
 	%67 = add i32 %66, %65		; <i32> [#uses=1]
 	%68 = zext i32 %52 to i64		; <i64> [#uses=1]
-	%69 = getelementptr i32* %51, i64 %68		; <i32*> [#uses=1]
+	%69 = getelementptr i32, i32* %51, i64 %68		; <i32*> [#uses=1]
 	store i32 %67, i32* %69, align 1
-	%70 = load i32** @d, align 8		; <i32*> [#uses=1]
+	%70 = load i32*, i32** @d, align 8		; <i32*> [#uses=1]
 	%71 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=1]
 	%72 = and i32 %71, 15		; <i32> [#uses=1]
-	%73 = load i32** @e, align 8		; <i32*> [#uses=1]
+	%73 = load i32*, i32** @e, align 8		; <i32*> [#uses=1]
 	%74 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=1]
 	%75 = and i32 %74, 15		; <i32> [#uses=1]
 	%76 = zext i32 %75 to i64		; <i64> [#uses=1]
-	%77 = getelementptr i32* %73, i64 %76		; <i32*> [#uses=1]
-	%78 = load i32* %77, align 1		; <i32> [#uses=1]
-	%79 = load i32** @f, align 8		; <i32*> [#uses=1]
+	%77 = getelementptr i32, i32* %73, i64 %76		; <i32*> [#uses=1]
+	%78 = load i32, i32* %77, align 1		; <i32> [#uses=1]
+	%79 = load i32*, i32** @f, align 8		; <i32*> [#uses=1]
 	%80 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=1]
 	%81 = and i32 %80, 15		; <i32> [#uses=1]
 	%82 = zext i32 %81 to i64		; <i64> [#uses=1]
-	%83 = getelementptr i32* %79, i64 %82		; <i32*> [#uses=1]
-	%84 = load i32* %83, align 1		; <i32> [#uses=1]
+	%83 = getelementptr i32, i32* %79, i64 %82		; <i32*> [#uses=1]
+	%84 = load i32, i32* %83, align 1		; <i32> [#uses=1]
 	%85 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=1]
 	%86 = sext i32 %85 to i64		; <i64> [#uses=1]
-	%87 = getelementptr [256 x i32]* @K, i64 0, i64 %86		; <i32*> [#uses=1]
-	%88 = load i32* %87, align 4		; <i32> [#uses=1]
+	%87 = getelementptr [256 x i32], [256 x i32]* @K, i64 0, i64 %86		; <i32*> [#uses=1]
+	%88 = load i32, i32* %87, align 4		; <i32> [#uses=1]
 	%89 = add i32 %84, %78		; <i32> [#uses=1]
 	%90 = add i32 %89, %88		; <i32> [#uses=1]
 	%91 = zext i32 %72 to i64		; <i64> [#uses=1]
-	%92 = getelementptr i32* %70, i64 %91		; <i32*> [#uses=1]
+	%92 = getelementptr i32, i32* %70, i64 %91		; <i32*> [#uses=1]
 	store i32 %90, i32* %92, align 1
-	%93 = load i32** @d, align 8		; <i32*> [#uses=1]
+	%93 = load i32*, i32** @d, align 8		; <i32*> [#uses=1]
 	%94 = add i32 %i.0.reg2mem.0, 2		; <i32> [#uses=1]
 	%95 = and i32 %94, 15		; <i32> [#uses=1]
-	%96 = load i32** @e, align 8		; <i32*> [#uses=1]
+	%96 = load i32*, i32** @e, align 8		; <i32*> [#uses=1]
 	%97 = add i32 %i.0.reg2mem.0, 2		; <i32> [#uses=1]
 	%98 = and i32 %97, 15		; <i32> [#uses=1]
 	%99 = zext i32 %98 to i64		; <i64> [#uses=1]
-	%100 = getelementptr i32* %96, i64 %99		; <i32*> [#uses=1]
-	%101 = load i32* %100, align 1		; <i32> [#uses=1]
-	%102 = load i32** @f, align 8		; <i32*> [#uses=1]
+	%100 = getelementptr i32, i32* %96, i64 %99		; <i32*> [#uses=1]
+	%101 = load i32, i32* %100, align 1		; <i32> [#uses=1]
+	%102 = load i32*, i32** @f, align 8		; <i32*> [#uses=1]
 	%103 = add i32 %i.0.reg2mem.0, 2		; <i32> [#uses=1]
 	%104 = and i32 %103, 15		; <i32> [#uses=1]
 	%105 = zext i32 %104 to i64		; <i64> [#uses=1]
-	%106 = getelementptr i32* %102, i64 %105		; <i32*> [#uses=1]
-	%107 = load i32* %106, align 1		; <i32> [#uses=1]
+	%106 = getelementptr i32, i32* %102, i64 %105		; <i32*> [#uses=1]
+	%107 = load i32, i32* %106, align 1		; <i32> [#uses=1]
 	%108 = add i32 %i.0.reg2mem.0, 2		; <i32> [#uses=1]
 	%109 = sext i32 %108 to i64		; <i64> [#uses=1]
-	%110 = getelementptr [256 x i32]* @K, i64 0, i64 %109		; <i32*> [#uses=1]
-	%111 = load i32* %110, align 4		; <i32> [#uses=1]
+	%110 = getelementptr [256 x i32], [256 x i32]* @K, i64 0, i64 %109		; <i32*> [#uses=1]
+	%111 = load i32, i32* %110, align 4		; <i32> [#uses=1]
 	%112 = add i32 %107, %101		; <i32> [#uses=1]
 	%113 = add i32 %112, %111		; <i32> [#uses=1]
 	%114 = zext i32 %95 to i64		; <i64> [#uses=1]
-	%115 = getelementptr i32* %93, i64 %114		; <i32*> [#uses=1]
+	%115 = getelementptr i32, i32* %93, i64 %114		; <i32*> [#uses=1]
 	store i32 %113, i32* %115, align 1
 	%116 = add i32 %i.0.reg2mem.0, 1		; <i32> [#uses=2]
 	%117 = icmp sgt i32 %116, 23646		; <i1> [#uses=1]
diff --git a/test/Transforms/IndVarSimplify/2009-04-27-Floating.ll b/test/Transforms/IndVarSimplify/2009-04-27-Floating.ll
index 47164d86047e..44c43a3a0435 100644
--- a/test/Transforms/IndVarSimplify/2009-04-27-Floating.ll
+++ b/test/Transforms/IndVarSimplify/2009-04-27-Floating.ll
@@ -1,5 +1,9 @@
 ; RUN: opt < %s -indvars -S | FileCheck %s
 ; PR4086
+
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
 declare void @foo()
 
 define void @test() {
diff --git a/test/Transforms/IndVarSimplify/2011-09-27-hoistsext.ll b/test/Transforms/IndVarSimplify/2011-09-27-hoistsext.ll
index 0737489aad5b..f0765e7d4c69 100644
--- a/test/Transforms/IndVarSimplify/2011-09-27-hoistsext.ll
+++ b/test/Transforms/IndVarSimplify/2011-09-27-hoistsext.ll
@@ -17,8 +17,8 @@ for.body:
   %i2.115 = phi i32 [ 0, %entry ], [ %add249, %for.body ]
   %add174 = add nsw i32 %i2.115, %x
   %idxprom177 = sext i32 %add174 to i64
-  %arrayidx179 = getelementptr inbounds double* %data, i64 %idxprom177
-  %tmp180 = load double* %arrayidx179, align 8
+  %arrayidx179 = getelementptr inbounds double, double* %data, i64 %idxprom177
+  %tmp180 = load double, double* %arrayidx179, align 8
   %add249 = add nsw i32 %i2.115, %y
   %cmp168 = icmp sgt i32 %add249, %n
   br i1 %cmp168, label %exit, label %for.body
diff --git a/test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll b/test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll
index e462712fe7a5..3d77a364f96f 100644
--- a/test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll
+++ b/test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll
@@ -6,7 +6,7 @@ target triple = "thumbv7-apple-darwin"
 
 ; CHECK-LABEL: @test(
 ; CHECK: if.end.i126:
-; CHECK: %exitcond = icmp ne i8* %destYPixelPtr.010.i, getelementptr (i8* null, i32 undef)
+; CHECK: %exitcond = icmp ne i8* %incdec.ptr.i, getelementptr (i8, i8* null, i32 undef)
 define void @test() nounwind {
 entry:
   br label %while.cond
@@ -40,7 +40,7 @@ if.else.i124:                                     ; preds = %for.body21.i
   br label %if.end.i126
 
 if.end.i126:                                      ; preds = %if.else.i124, %for.body21.i
-  %incdec.ptr.i = getelementptr inbounds i8* %destYPixelPtr.010.i, i32 1
+  %incdec.ptr.i = getelementptr inbounds i8, i8* %destYPixelPtr.010.i, i32 1
   %inc.i125 = add i32 %x.09.i, 1
   %cmp19.i = icmp ult i32 %inc.i125, undef
   br i1 %cmp19.i, label %for.body21.i, label %for.end.i129
diff --git a/test/Transforms/IndVarSimplify/2011-11-01-lftrptr.ll b/test/Transforms/IndVarSimplify/2011-11-01-lftrptr.ll
index 8247886e66d9..402ae8cc05d0 100644
--- a/test/Transforms/IndVarSimplify/2011-11-01-lftrptr.ll
+++ b/test/Transforms/IndVarSimplify/2011-11-01-lftrptr.ll
@@ -25,13 +25,14 @@ preheader:
 loop:
   %p.01.us.us = phi i8* [ null, %preheader ], [ %gep, %loop ]
   %s = phi i8 [0, %preheader], [%snext, %loop]
-  %gep = getelementptr inbounds i8* %p.01.us.us, i64 1
-  %snext = load i8* %gep
+  %gep = getelementptr inbounds i8, i8* %p.01.us.us, i64 1
+  %snext = load i8, i8* %gep
   %cmp = icmp ult i8* %gep, %end
   br i1 %cmp, label %loop, label %exit
 
 exit:
-  ret i8 %snext
+  %ret = phi i8 [0, %loopguard], [%snext, %loop]
+  ret i8 %ret
 }
 
 ; CHECK-LABEL: @testptrptr(
@@ -50,13 +51,14 @@ preheader:
 loop:
   %p.01.us.us = phi i8* [ %buf, %preheader ], [ %gep, %loop ]
   %s = phi i8 [0, %preheader], [%snext, %loop]
-  %gep = getelementptr inbounds i8* %p.01.us.us, i64 1
-  %snext = load i8* %gep
+  %gep = getelementptr inbounds i8, i8* %p.01.us.us, i64 1
+  %snext = load i8, i8* %gep
   %cmp = icmp ult i8* %gep, %end
   br i1 %cmp, label %loop, label %exit
 
 exit:
-  ret i8 %snext
+  %ret = phi i8 [0, %loopguard], [%snext, %loop]
+  ret i8 %ret
 }
 
 ; CHECK-LABEL: @testnullptrint(
@@ -79,14 +81,15 @@ loop:
   %p.01.us.us = phi i8* [ null, %preheader ], [ %gep, %loop ]
   %iv = phi i32 [ 0, %preheader ], [ %ivnext, %loop ]
   %s = phi i8 [0, %preheader], [%snext, %loop]
-  %gep = getelementptr inbounds i8* %p.01.us.us, i64 1
-  %snext = load i8* %gep
+  %gep = getelementptr inbounds i8, i8* %p.01.us.us, i64 1
+  %snext = load i8, i8* %gep
   %ivnext = add i32 %iv, 1
   %cmp = icmp ult i32 %ivnext, %cnt
   br i1 %cmp, label %loop, label %exit
 
 exit:
-  ret i8 %snext
+  %ret = phi i8 [0, %loopguard], [%snext, %loop]
+  ret i8 %ret
 }
 
 ; CHECK-LABEL: @testptrint(
@@ -109,20 +112,21 @@ loop:
   %p.01.us.us = phi i8* [ %buf, %preheader ], [ %gep, %loop ]
   %iv = phi i32 [ %bi, %preheader ], [ %ivnext, %loop ]
   %s = phi i8 [0, %preheader], [%snext, %loop]
-  %gep = getelementptr inbounds i8* %p.01.us.us, i64 1
-  %snext = load i8* %gep
+  %gep = getelementptr inbounds i8, i8* %p.01.us.us, i64 1
+  %snext = load i8, i8* %gep
   %ivnext = add i32 %iv, 1
   %cmp = icmp ult i32 %ivnext, %cnt
   br i1 %cmp, label %loop, label %exit
 
 exit:
-  ret i8 %snext
+  %ret = phi i8 [0, %loopguard], [%snext, %loop]
+  ret i8 %ret
 }
 
 ; IV and BECount have two different pointer types here.
 define void @testnullptr([512 x i8]* %base) nounwind {
 entry:
-  %add.ptr1603 = getelementptr [512 x i8]* %base, i64 0, i64 512
+  %add.ptr1603 = getelementptr [512 x i8], [512 x i8]* %base, i64 0, i64 512
   br label %preheader
 
 preheader:
@@ -131,7 +135,7 @@ preheader:
 
 for.body:
   %r.17193 = phi i8* [ %incdec.ptr1608, %for.body ], [ null, %preheader ]
-  %incdec.ptr1608 = getelementptr i8* %r.17193, i64 1
+  %incdec.ptr1608 = getelementptr i8, i8* %r.17193, i64 1
   %cmp1604 = icmp ult i8* %incdec.ptr1608, %add.ptr1603
   br i1 %cmp1604, label %for.body, label %for.end1609
 
diff --git a/test/Transforms/IndVarSimplify/2011-11-15-multiexit.ll b/test/Transforms/IndVarSimplify/2011-11-15-multiexit.ll
index c74d04e6a5d8..65b2cf684580 100644
--- a/test/Transforms/IndVarSimplify/2011-11-15-multiexit.ll
+++ b/test/Transforms/IndVarSimplify/2011-11-15-multiexit.ll
@@ -20,12 +20,12 @@ if.then:                                          ; preds = %entry
 
 do.body:                                          ; preds = %if.else, %if.then
   %firstIV = phi i32* [ %incdec.ptr2, %if.else ], [ %first, %if.then ]
-  %incdec.ptr1 = getelementptr inbounds i32* %firstIV, i64 1
+  %incdec.ptr1 = getelementptr inbounds i32, i32* %firstIV, i64 1
   %cmp1 = icmp eq i32* %incdec.ptr1, %last
   br i1 %cmp1, label %early.exit, label %if.else
 
 if.else:                                        ; preds = %do.body
-  %incdec.ptr2 = getelementptr inbounds i32* %firstIV, i64 2
+  %incdec.ptr2 = getelementptr inbounds i32, i32* %firstIV, i64 2
   %cmp2 = icmp eq i32* %incdec.ptr2, %last
   br i1 %cmp2, label %if.end, label %do.body
 
@@ -35,6 +35,6 @@ early.exit:
 
 if.end:
   %tmp = phi i32* [ %first.lcssa, %early.exit ], [ %first, %if.then ], [ %first, %entry ], [ undef, %if.else ]
-  %val = load i32* %tmp
+  %val = load i32, i32* %tmp
   ret i32 %val
 }
diff --git a/test/Transforms/IndVarSimplify/2012-07-17-lftr-undef.ll b/test/Transforms/IndVarSimplify/2012-07-17-lftr-undef.ll
index 643d3cb333ee..faecbfbe07ab 100644
--- a/test/Transforms/IndVarSimplify/2012-07-17-lftr-undef.ll
+++ b/test/Transforms/IndVarSimplify/2012-07-17-lftr-undef.ll
@@ -13,7 +13,7 @@ block9:                                           ; preds = %block9,%func_start
   %undef = phi i64 [ %next_undef, %block9 ], [ undef, %func_start ]
   %iter = phi i64 [ %next_iter, %block9 ], [ 1, %func_start ]
   %next_iter = add nsw i64 %iter, 1
-  %0 = tail call i32 (i8*, ...)* @printf(i8* noalias nocapture getelementptr inbounds ([6 x i8]* @.str3, i64 0, i64 0), i64 %next_iter, i64 %undef)
+  %0 = tail call i32 (i8*, ...) @printf(i8* noalias nocapture getelementptr inbounds ([6 x i8], [6 x i8]* @.str3, i64 0, i64 0), i64 %next_iter, i64 %undef)
   %next_undef = add nsw i64 %undef, 1
   %_tmp_3 = icmp slt i64 %next_iter, 100
   br i1 %_tmp_3, label %block9, label %exit
diff --git a/test/Transforms/IndVarSimplify/2014-06-21-congruent-constant.ll b/test/Transforms/IndVarSimplify/2014-06-21-congruent-constant.ll
index 2c738de32e0a..1d80e751dcab 100644
--- a/test/Transforms/IndVarSimplify/2014-06-21-congruent-constant.ll
+++ b/test/Transforms/IndVarSimplify/2014-06-21-congruent-constant.ll
@@ -13,9 +13,9 @@ entry:
   br i1 undef, label %for.end12, label %for.cond.preheader
 
 for.cond.preheader:                               ; preds = %entry
-  %0 = load i32*** @c, align 8
-  %1 = load i32** %0, align 8
-  %2 = load i32* %1, align 4
+  %0 = load i32**, i32*** @c, align 8
+  %1 = load i32*, i32** %0, align 8
+  %2 = load i32, i32* %1, align 4
   br label %for.body
 
 for.body:                                         ; preds = %for.cond.backedge, %for.body9.us, %for.cond.preheader
@@ -26,7 +26,7 @@ for.body:                                         ; preds = %for.cond.backedge,
   br i1 %tobool1, label %if.end, label %for.cond.backedge
 
 if.end:                                           ; preds = %for.body
-  %5 = load i32* %3, align 4
+  %5 = load i32, i32* %3, align 4
   %tobool4 = icmp eq i32 %5, 0
   br i1 %tobool4, label %for.cond3, label %for.body9.preheader
 
@@ -35,8 +35,8 @@ for.body9.preheader:                              ; preds = %if.end
   br i1 %tobool8, label %for.body9.us, label %for.body9
 
 for.body9.us:                                     ; preds = %for.body9.preheader
-  %6 = load i32** undef, align 8
-  %7 = load i32* %6, align 4
+  %6 = load i32*, i32** undef, align 8
+  %7 = load i32, i32* %6, align 4
   br label %for.body
 
 for.cond3:                                        ; preds = %for.cond3, %if.end
diff --git a/test/Transforms/IndVarSimplify/NVPTX/no-widen-expensive.ll b/test/Transforms/IndVarSimplify/NVPTX/no-widen-expensive.ll
index 8744b19d5e28..ae2cb7ffee8f 100644
--- a/test/Transforms/IndVarSimplify/NVPTX/no-widen-expensive.ll
+++ b/test/Transforms/IndVarSimplify/NVPTX/no-widen-expensive.ll
@@ -23,7 +23,7 @@ for.body:                                         ; preds = %for.body.preheader,
 ; CHECK: phi i32
   %mul = mul nsw i32 %i.06, %i.06
   %0 = sext i32 %i.06 to i64
-  %arrayidx = getelementptr inbounds i32* %output, i64 %0
+  %arrayidx = getelementptr inbounds i32, i32* %output, i64 %0
   store i32 %mul, i32* %arrayidx, align 4
   %add = add nsw i32 %i.06, 3
   %cmp = icmp slt i32 %add, %n
diff --git a/test/Transforms/IndVarSimplify/ada-loops.ll b/test/Transforms/IndVarSimplify/ada-loops.ll
index c0932982ee5e..e452f03bed92 100644
--- a/test/Transforms/IndVarSimplify/ada-loops.ll
+++ b/test/Transforms/IndVarSimplify/ada-loops.ll
@@ -18,7 +18,7 @@ target triple = "i686-pc-linux-gnu"
 
 define void @kinds__sbytezero([256 x i32]* nocapture %a) nounwind {
 bb.thread:
-	%tmp46 = getelementptr [256 x i32]* %a, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp46 = getelementptr [256 x i32], [256 x i32]* %a, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp46
 	br label %bb
 
@@ -27,7 +27,7 @@ bb:		; preds = %bb, %bb.thread
 	%tmp8 = add i8 %i.0.reg2mem.0, 1		; <i8> [#uses=3]
 	%tmp1 = sext i8 %tmp8 to i32		; <i32> [#uses=1]
 	%tmp3 = add i32 %tmp1, 128		; <i32> [#uses=1]
-	%tmp4 = getelementptr [256 x i32]* %a, i32 0, i32 %tmp3		; <i32*> [#uses=1]
+	%tmp4 = getelementptr [256 x i32], [256 x i32]* %a, i32 0, i32 %tmp3		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp4
 	%0 = icmp eq i8 %tmp8, 127		; <i1> [#uses=1]
 	br i1 %0, label %return, label %bb
@@ -38,7 +38,7 @@ return:		; preds = %bb
 
 define void @kinds__ubytezero([256 x i32]* nocapture %a) nounwind {
 bb.thread:
-	%tmp35 = getelementptr [256 x i32]* %a, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp35 = getelementptr [256 x i32], [256 x i32]* %a, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp35
 	br label %bb
 
@@ -46,7 +46,7 @@ bb:		; preds = %bb, %bb.thread
 	%i.0.reg2mem.0 = phi i8 [ 0, %bb.thread ], [ %tmp7, %bb ]		; <i8> [#uses=1]
 	%tmp7 = add i8 %i.0.reg2mem.0, 1		; <i8> [#uses=3]
 	%tmp1 = zext i8 %tmp7 to i32		; <i32> [#uses=1]
-	%tmp3 = getelementptr [256 x i32]* %a, i32 0, i32 %tmp1		; <i32*> [#uses=1]
+	%tmp3 = getelementptr [256 x i32], [256 x i32]* %a, i32 0, i32 %tmp1		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp3
 	%0 = icmp eq i8 %tmp7, -1		; <i1> [#uses=1]
 	br i1 %0, label %return, label %bb
@@ -63,7 +63,7 @@ bb:		; preds = %bb, %bb.thread
 	%i.0.reg2mem.0 = phi i8 [ -10, %bb.thread ], [ %tmp7, %bb ]		; <i8> [#uses=2]
 	%tmp12 = sext i8 %i.0.reg2mem.0 to i32		; <i32> [#uses=1]
 	%tmp4 = add i32 %tmp12, 10		; <i32> [#uses=1]
-	%tmp5 = getelementptr [21 x i32]* %a, i32 0, i32 %tmp4		; <i32*> [#uses=1]
+	%tmp5 = getelementptr [21 x i32], [21 x i32]* %a, i32 0, i32 %tmp4		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp5
 	%tmp7 = add i8 %i.0.reg2mem.0, 1		; <i8> [#uses=2]
 	%0 = icmp sgt i8 %tmp7, 10		; <i1> [#uses=1]
@@ -81,7 +81,7 @@ bb:		; preds = %bb, %bb.thread
 	%i.0.reg2mem.0 = phi i8 [ 10, %bb.thread ], [ %tmp7, %bb ]		; <i8> [#uses=2]
 	%tmp12 = sext i8 %i.0.reg2mem.0 to i32		; <i32> [#uses=1]
 	%tmp4 = add i32 %tmp12, -10		; <i32> [#uses=1]
-	%tmp5 = getelementptr [21 x i32]* %a, i32 0, i32 %tmp4		; <i32*> [#uses=1]
+	%tmp5 = getelementptr [21 x i32], [21 x i32]* %a, i32 0, i32 %tmp4		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp5
 	%tmp7 = add i8 %i.0.reg2mem.0, 1		; <i8> [#uses=2]
 	%0 = icmp sgt i8 %tmp7, 30		; <i1> [#uses=1]
diff --git a/test/Transforms/IndVarSimplify/ashr-tripcount.ll b/test/Transforms/IndVarSimplify/ashr-tripcount.ll
index b47c8ad47184..5f337301b404 100644
--- a/test/Transforms/IndVarSimplify/ashr-tripcount.ll
+++ b/test/Transforms/IndVarSimplify/ashr-tripcount.ll
@@ -29,10 +29,10 @@ bb2:		; preds = %bb1, %entry
 	%.pn2.in = and i32 %.pn2.in.in, 3		; <i32> [#uses=1]
 	%.pn3 = sext i32 %.pn3.in to i64		; <i64> [#uses=1]
 	%.pn2 = zext i32 %.pn2.in to i64		; <i64> [#uses=1]
-	%.pn.in = getelementptr [0 x float]* %pow_2_tab.pn, i64 0, i64 %.pn3		; <float*> [#uses=1]
-	%.pn1.in = getelementptr [0 x float]* %pow_2_025_tab.pn, i64 0, i64 %.pn2		; <float*> [#uses=1]
-	%.pn = load float* %.pn.in		; <float> [#uses=1]
-	%.pn1 = load float* %.pn1.in		; <float> [#uses=1]
+	%.pn.in = getelementptr [0 x float], [0 x float]* %pow_2_tab.pn, i64 0, i64 %.pn3		; <float*> [#uses=1]
+	%.pn1.in = getelementptr [0 x float], [0 x float]* %pow_2_025_tab.pn, i64 0, i64 %.pn2		; <float*> [#uses=1]
+	%.pn = load float, float* %.pn.in		; <float> [#uses=1]
+	%.pn1 = load float, float* %.pn1.in		; <float> [#uses=1]
 	%invQuantizer.0 = fmul float %.pn, %.pn1		; <float> [#uses=4]
 	%t3 = ashr i32 %noOfLines, 2		; <i32> [#uses=1]
 	%t4 = icmp sgt i32 %t3, 0		; <i1> [#uses=1]
@@ -46,50 +46,50 @@ bb3:		; preds = %bb4, %bb.nph
 	%i.05 = phi i32 [ %t49, %bb4 ], [ 0, %bb.nph ]		; <i32> [#uses=9]
 	%k.04 = phi i32 [ %t48, %bb4 ], [ 0, %bb.nph ]		; <i32> [#uses=1]
 	%t6 = sext i32 %i.05 to i64		; <i64> [#uses=1]
-	%t7 = getelementptr i32* %quaSpectrum, i64 %t6		; <i32*> [#uses=1]
-	%t8 = load i32* %t7, align 4		; <i32> [#uses=1]
+	%t7 = getelementptr i32, i32* %quaSpectrum, i64 %t6		; <i32*> [#uses=1]
+	%t8 = load i32, i32* %t7, align 4		; <i32> [#uses=1]
 	%t9 = zext i32 %t8 to i64		; <i64> [#uses=1]
-	%t10 = getelementptr float* %pow4_3_tab_ptr, i64 %t9		; <float*> [#uses=1]
-	%t11 = load float* %t10, align 4		; <float> [#uses=1]
+	%t10 = getelementptr float, float* %pow4_3_tab_ptr, i64 %t9		; <float*> [#uses=1]
+	%t11 = load float, float* %t10, align 4		; <float> [#uses=1]
 	%t12 = or i32 %i.05, 1		; <i32> [#uses=1]
 	%t13 = sext i32 %t12 to i64		; <i64> [#uses=1]
-	%t14 = getelementptr i32* %quaSpectrum, i64 %t13		; <i32*> [#uses=1]
-	%t15 = load i32* %t14, align 4		; <i32> [#uses=1]
+	%t14 = getelementptr i32, i32* %quaSpectrum, i64 %t13		; <i32*> [#uses=1]
+	%t15 = load i32, i32* %t14, align 4		; <i32> [#uses=1]
 	%t16 = zext i32 %t15 to i64		; <i64> [#uses=1]
-	%t17 = getelementptr float* %pow4_3_tab_ptr, i64 %t16		; <float*> [#uses=1]
-	%t18 = load float* %t17, align 4		; <float> [#uses=1]
+	%t17 = getelementptr float, float* %pow4_3_tab_ptr, i64 %t16		; <float*> [#uses=1]
+	%t18 = load float, float* %t17, align 4		; <float> [#uses=1]
 	%t19 = or i32 %i.05, 2		; <i32> [#uses=1]
 	%t20 = sext i32 %t19 to i64		; <i64> [#uses=1]
-	%t21 = getelementptr i32* %quaSpectrum, i64 %t20		; <i32*> [#uses=1]
-	%t22 = load i32* %t21, align 4		; <i32> [#uses=1]
+	%t21 = getelementptr i32, i32* %quaSpectrum, i64 %t20		; <i32*> [#uses=1]
+	%t22 = load i32, i32* %t21, align 4		; <i32> [#uses=1]
 	%t23 = zext i32 %t22 to i64		; <i64> [#uses=1]
-	%t24 = getelementptr float* %pow4_3_tab_ptr, i64 %t23		; <float*> [#uses=1]
-	%t25 = load float* %t24, align 4		; <float> [#uses=1]
+	%t24 = getelementptr float, float* %pow4_3_tab_ptr, i64 %t23		; <float*> [#uses=1]
+	%t25 = load float, float* %t24, align 4		; <float> [#uses=1]
 	%t26 = or i32 %i.05, 3		; <i32> [#uses=1]
 	%t27 = sext i32 %t26 to i64		; <i64> [#uses=1]
-	%t28 = getelementptr i32* %quaSpectrum, i64 %t27		; <i32*> [#uses=1]
-	%t29 = load i32* %t28, align 4		; <i32> [#uses=1]
+	%t28 = getelementptr i32, i32* %quaSpectrum, i64 %t27		; <i32*> [#uses=1]
+	%t29 = load i32, i32* %t28, align 4		; <i32> [#uses=1]
 	%t30 = zext i32 %t29 to i64		; <i64> [#uses=1]
-	%t31 = getelementptr float* %pow4_3_tab_ptr, i64 %t30		; <float*> [#uses=1]
-	%t32 = load float* %t31, align 4		; <float> [#uses=1]
+	%t31 = getelementptr float, float* %pow4_3_tab_ptr, i64 %t30		; <float*> [#uses=1]
+	%t32 = load float, float* %t31, align 4		; <float> [#uses=1]
 	%t33 = fmul float %t11, %invQuantizer.0		; <float> [#uses=1]
 	%t34 = sext i32 %i.05 to i64		; <i64> [#uses=1]
-	%t35 = getelementptr float* %iquaSpectrum, i64 %t34		; <float*> [#uses=1]
+	%t35 = getelementptr float, float* %iquaSpectrum, i64 %t34		; <float*> [#uses=1]
 	store float %t33, float* %t35, align 4
 	%t36 = or i32 %i.05, 1		; <i32> [#uses=1]
 	%t37 = fmul float %t18, %invQuantizer.0		; <float> [#uses=1]
 	%t38 = sext i32 %t36 to i64		; <i64> [#uses=1]
-	%t39 = getelementptr float* %iquaSpectrum, i64 %t38		; <float*> [#uses=1]
+	%t39 = getelementptr float, float* %iquaSpectrum, i64 %t38		; <float*> [#uses=1]
 	store float %t37, float* %t39, align 4
 	%t40 = or i32 %i.05, 2		; <i32> [#uses=1]
 	%t41 = fmul float %t25, %invQuantizer.0		; <float> [#uses=1]
 	%t42 = sext i32 %t40 to i64		; <i64> [#uses=1]
-	%t43 = getelementptr float* %iquaSpectrum, i64 %t42		; <float*> [#uses=1]
+	%t43 = getelementptr float, float* %iquaSpectrum, i64 %t42		; <float*> [#uses=1]
 	store float %t41, float* %t43, align 4
 	%t44 = or i32 %i.05, 3		; <i32> [#uses=1]
 	%t45 = fmul float %t32, %invQuantizer.0		; <float> [#uses=1]
 	%t46 = sext i32 %t44 to i64		; <i64> [#uses=1]
-	%t47 = getelementptr float* %iquaSpectrum, i64 %t46		; <float*> [#uses=1]
+	%t47 = getelementptr float, float* %iquaSpectrum, i64 %t46		; <float*> [#uses=1]
 	store float %t45, float* %t47, align 4
 	%t48 = add i32 %k.04, 1		; <i32> [#uses=2]
 	%t49 = add i32 %i.05, 4		; <i32> [#uses=1]
diff --git a/test/Transforms/IndVarSimplify/avoid-i0.ll b/test/Transforms/IndVarSimplify/avoid-i0.ll
index 22f2e4b718c2..cc38590c0998 100644
--- a/test/Transforms/IndVarSimplify/avoid-i0.ll
+++ b/test/Transforms/IndVarSimplify/avoid-i0.ll
@@ -34,25 +34,25 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store i32 %_si1, i32* %_si1_addr
 	store i8 %_si2, i8* %_si2_addr
-	%1 = load i8* %_si2_addr, align 1		; <i8> [#uses=1]
+	%1 = load i8, i8* %_si2_addr, align 1		; <i8> [#uses=1]
 	%2 = sext i8 %1 to i32		; <i32> [#uses=1]
-	%3 = load i32* %_si1_addr, align 4		; <i32> [#uses=1]
+	%3 = load i32, i32* %_si1_addr, align 4		; <i32> [#uses=1]
 	%4 = xor i32 %2, %3		; <i32> [#uses=1]
-	%5 = load i8* %_si2_addr, align 1		; <i8> [#uses=1]
+	%5 = load i8, i8* %_si2_addr, align 1		; <i8> [#uses=1]
 	%6 = sext i8 %5 to i32		; <i32> [#uses=1]
 	%7 = sub i32 7, %6		; <i32> [#uses=1]
-	%8 = load i32* %_si1_addr, align 4		; <i32> [#uses=1]
+	%8 = load i32, i32* %_si1_addr, align 4		; <i32> [#uses=1]
 	%9 = shl i32 %8, %7		; <i32> [#uses=1]
 	%10 = and i32 %4, %9		; <i32> [#uses=1]
 	%11 = icmp slt i32 %10, 0		; <i1> [#uses=1]
 	%12 = zext i1 %11 to i32		; <i32> [#uses=1]
 	store i32 %12, i32* %0, align 4
-	%13 = load i32* %0, align 4		; <i32> [#uses=1]
+	%13 = load i32, i32* %0, align 4		; <i32> [#uses=1]
 	store i32 %13, i32* %retval, align 4
 	br label %return
 
 return:		; preds = %entry
-	%retval1 = load i32* %retval		; <i32> [#uses=1]
+	%retval1 = load i32, i32* %retval		; <i32> [#uses=1]
 	%retval12 = trunc i32 %retval1 to i8		; <i8> [#uses=1]
 	ret i8 %retval12
 }
@@ -66,15 +66,15 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store i32 %_ui1, i32* %_ui1_addr
 	store i32 %_ui2, i32* %_ui2_addr
-	%1 = load i32* %_ui1_addr, align 4		; <i32> [#uses=1]
+	%1 = load i32, i32* %_ui1_addr, align 4		; <i32> [#uses=1]
 	%2 = sub i32 %1, 1		; <i32> [#uses=1]
 	store i32 %2, i32* %0, align 4
-	%3 = load i32* %0, align 4		; <i32> [#uses=1]
+	%3 = load i32, i32* %0, align 4		; <i32> [#uses=1]
 	store i32 %3, i32* %retval, align 4
 	br label %return
 
 return:		; preds = %entry
-	%retval1 = load i32* %retval		; <i32> [#uses=1]
+	%retval1 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval1
 }
 
@@ -90,31 +90,31 @@ entry:
 	br label %bb4
 
 bb:		; preds = %bb4
-	%0 = load volatile i32* @x, align 4		; <i32> [#uses=1]
+	%0 = load volatile i32, i32* @x, align 4		; <i32> [#uses=1]
 	store i32 %0, i32* %vol.0, align 4
 	store i32 0, i32* %l_52, align 4
 	br label %bb2
 
 bb1:		; preds = %bb2
-	%1 = load i32* %l_52, align 4		; <i32> [#uses=1]
+	%1 = load i32, i32* %l_52, align 4		; <i32> [#uses=1]
 	%2 = call i32 @safe_sub_func_uint64_t_u_u(i32 %1, i32 1) nounwind		; <i32> [#uses=1]
 	store i32 %2, i32* %l_52, align 4
 	br label %bb2
 
 bb2:		; preds = %bb1, %bb
-	%3 = load i32* %l_52, align 4		; <i32> [#uses=1]
+	%3 = load i32, i32* %l_52, align 4		; <i32> [#uses=1]
 	%4 = icmp eq i32 %3, 0		; <i1> [#uses=1]
 	br i1 %4, label %bb1, label %bb3
 
 bb3:		; preds = %bb2
-	%5 = load i32* %l_52, align 4		; <i32> [#uses=1]
+	%5 = load i32, i32* %l_52, align 4		; <i32> [#uses=1]
 	%6 = call signext i8 @safe_sub_func_int32_t_s_s(i32 %5, i8 signext 1) nounwind		; <i8> [#uses=1]
 	%7 = sext i8 %6 to i32		; <i32> [#uses=1]
 	store i32 %7, i32* %l_52, align 4
 	br label %bb4
 
 bb4:		; preds = %bb3, %entry
-	%8 = load i32* %l_52, align 4		; <i32> [#uses=1]
+	%8 = load i32, i32* %l_52, align 4		; <i32> [#uses=1]
 	%9 = icmp ne i32 %8, 0		; <i1> [#uses=1]
 	br i1 %9, label %bb, label %bb5
 
diff --git a/test/Transforms/IndVarSimplify/backedge-on-min-max.ll b/test/Transforms/IndVarSimplify/backedge-on-min-max.ll
index 250ff9a2eca6..bb26ca5bafb0 100644
--- a/test/Transforms/IndVarSimplify/backedge-on-min-max.ll
+++ b/test/Transforms/IndVarSimplify/backedge-on-min-max.ll
@@ -18,7 +18,7 @@ define void @min.signed.1(i32* %a, i32 %a_len, i32 %n) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
@@ -46,7 +46,7 @@ define void @min.signed.2(i32* %a, i32 %a_len, i32 %n) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
@@ -74,7 +74,7 @@ define void @min.signed.3(i32* %a, i32 %n) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
@@ -102,7 +102,7 @@ define void @min.signed.4(i32* %a, i32 %n) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
@@ -130,7 +130,7 @@ define void @max.signed.1(i32* %a, i32 %a_len, i32 %n) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
@@ -158,7 +158,7 @@ define void @max.signed.2(i32* %a, i32 %a_len, i32 %n) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
@@ -186,7 +186,7 @@ define void @max.signed.3(i32* %a, i32 %n, i32 %init) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
@@ -214,7 +214,7 @@ define void @max.signed.4(i32* %a, i32 %n, i32 %init) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
@@ -244,7 +244,7 @@ define void @min.unsigned.1(i32* %a, i32 %a_len, i32 %n) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
@@ -272,7 +272,7 @@ define void @min.unsigned.2(i32* %a, i32 %a_len, i32 %n) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
@@ -300,7 +300,7 @@ define void @min.unsigned.3(i32* %a, i32 %n) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
@@ -328,7 +328,7 @@ define void @min.unsigned.4(i32* %a, i32 %n) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
@@ -356,7 +356,7 @@ define void @max.unsigned.1(i32* %a, i32 %a_len, i32 %n) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
@@ -384,7 +384,7 @@ define void @max.unsigned.2(i32* %a, i32 %a_len, i32 %n) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
@@ -412,7 +412,7 @@ define void @max.unsigned.3(i32* %a, i32 %n, i32 %init) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
@@ -440,7 +440,7 @@ define void @max.unsigned.4(i32* %a, i32 %n, i32 %init) {
 ; CHECK: br i1 true, label %ok, label %latch
 
  ok:
-  %addr = getelementptr i32* %a, i32 %idx
+  %addr = getelementptr i32, i32* %a, i32 %idx
   store i32 %idx, i32* %addr
   br label %latch
 
diff --git a/test/Transforms/IndVarSimplify/casted-argument.ll b/test/Transforms/IndVarSimplify/casted-argument.ll
index a5e002b4578f..9d868e800e98 100644
--- a/test/Transforms/IndVarSimplify/casted-argument.ll
+++ b/test/Transforms/IndVarSimplify/casted-argument.ll
@@ -17,7 +17,7 @@ loop:		; preds = %loop, %if.else
 	%pn = phi i8* [ %ge, %loop ], [ null, %entry ]		; <i8*> [#uses=1]
 	%cp = ptrtoint i8* %to to i32		; <i32> [#uses=1]
 	%su = sub i32 0, %cp		; <i32> [#uses=1]
-	%ge = getelementptr i8* %pn, i32 %su		; <i8*> [#uses=2]
+	%ge = getelementptr i8, i8* %pn, i32 %su		; <i8*> [#uses=2]
 	tail call void @bcopy(i8* %ge) nounwind
 	br label %loop
 }
@@ -39,9 +39,9 @@ if.end54:		; preds = %if.end54, %if.else
 	%sub.ptr.rhs.cast46.pn = ptrtoint i8* %from to i32		; <i32> [#uses=1]
 	%sub.ptr.lhs.cast45.pn = ptrtoint i8* %to to i32		; <i32> [#uses=1]
 	%sub.ptr.sub47.pn = sub i32 %sub.ptr.rhs.cast46.pn, %sub.ptr.lhs.cast45.pn		; <i32> [#uses=1]
-	%sub.ptr4912 = getelementptr i8* %sub.ptr4912.pn, i32 %sub.ptr.sub47.pn		; <i8*> [#uses=2]
+	%sub.ptr4912 = getelementptr i8, i8* %sub.ptr4912.pn, i32 %sub.ptr.sub47.pn		; <i8*> [#uses=2]
 	tail call void @bcopy_4038(i8* %sub.ptr4912, i8* %sub.ptr7, i32 0) nounwind
-	%sub.ptr = getelementptr i8* %sub.ptr7, i32 %sub.ptr.rhs.cast40		; <i8*> [#uses=1]
+	%sub.ptr = getelementptr i8, i8* %sub.ptr7, i32 %sub.ptr.rhs.cast40		; <i8*> [#uses=1]
 	br label %if.end54
 }
 
diff --git a/test/Transforms/IndVarSimplify/dangling-use.ll b/test/Transforms/IndVarSimplify/dangling-use.ll
index 51c31204c6df..24a68a9e82c8 100644
--- a/test/Transforms/IndVarSimplify/dangling-use.ll
+++ b/test/Transforms/IndVarSimplify/dangling-use.ll
@@ -15,7 +15,7 @@ bb49:                                             ; preds = %bb48, %entry
 
 bb10:                                             ; preds = %bb49
   %tmp326 = mul nsw i32 %tmp1, %tmp2              ; <i32> [#uses=1]
-  %tmp351 = getelementptr inbounds i8* %x_addr.0, i32 %tmp326 ; <i8*> [#uses=1]
+  %tmp351 = getelementptr inbounds i8, i8* %x_addr.0, i32 %tmp326 ; <i8*> [#uses=1]
   br i1 false, label %bb.nph, label %bb48
 
 bb.nph:                                           ; preds = %bb10
@@ -25,7 +25,7 @@ bb23:                                             ; preds = %bb28, %bb.nph
   %pOriginHi.01 = phi i8* [ %tmp351, %bb.nph ], [ %pOriginHi.0, %bb28 ] ; <i8*> [#uses=2]
   %tmp378 = bitcast i8* %pOriginHi.01 to i8*      ; <i8*> [#uses=1]
   store i8* %tmp378, i8** null
-  %tmp385 = getelementptr inbounds i8* %pOriginHi.01, i32 %tmp2 ; <i8*> [#uses=1]
+  %tmp385 = getelementptr inbounds i8, i8* %pOriginHi.01, i32 %tmp2 ; <i8*> [#uses=1]
   br label %bb28
 
 bb28:                                             ; preds = %bb23
@@ -36,6 +36,6 @@ bb28.bb48_crit_edge:                              ; preds = %bb28
   br label %bb48
 
 bb48:                                             ; preds = %bb28.bb48_crit_edge, %bb10
-  %tmp481 = getelementptr inbounds i8* %x_addr.0, i32 1 ; <i8*> [#uses=1]
+  %tmp481 = getelementptr inbounds i8, i8* %x_addr.0, i32 1 ; <i8*> [#uses=1]
   br label %bb49
 }
diff --git a/test/Transforms/IndVarSimplify/elim-extend.ll b/test/Transforms/IndVarSimplify/elim-extend.ll
index ad5679f3e7a4..98701c338520 100644
--- a/test/Transforms/IndVarSimplify/elim-extend.ll
+++ b/test/Transforms/IndVarSimplify/elim-extend.ll
@@ -14,15 +14,15 @@ loop:
   %iv = phi i32 [ %postiv, %loop ], [ 0, %entry ]
   %ivnsw = phi i32 [ %postivnsw, %loop ], [ 0, %entry ]
   %preofs = sext i32 %iv to i64
-  %preadr = getelementptr i8* %base, i64 %preofs
+  %preadr = getelementptr i8, i8* %base, i64 %preofs
   store i8 0, i8* %preadr
   %postiv = add i32 %iv, 1
   %postofs = sext i32 %postiv to i64
-  %postadr = getelementptr i8* %base, i64 %postofs
+  %postadr = getelementptr i8, i8* %base, i64 %postofs
   store i8 0, i8* %postadr
   %postivnsw = add nsw i32 %ivnsw, 1
   %postofsnsw = sext i32 %postivnsw to i64
-  %postadrnsw = getelementptr i8* %base, i64 %postofsnsw
+  %postadrnsw = getelementptr i8, i8* %base, i64 %postofsnsw
   store i8 0, i8* %postadrnsw
   %cond = icmp sgt i32 %limit, %iv
   br i1 %cond, label %loop, label %exit
@@ -46,15 +46,15 @@ loop:
   %iv = phi i32 [ %postiv, %loop ], [ %init, %entry ]
   %ivnsw = phi i32 [ %postivnsw, %loop ], [ %init, %entry ]
   %preofs = sext i32 %iv to i64
-  %preadr = getelementptr i8* %base, i64 %preofs
+  %preadr = getelementptr i8, i8* %base, i64 %preofs
   store i8 0, i8* %preadr
   %postiv = add i32 %iv, 1
   %postofs = sext i32 %postiv to i64
-  %postadr = getelementptr i8* %base, i64 %postofs
+  %postadr = getelementptr i8, i8* %base, i64 %postofs
   store i8 0, i8* %postadr
   %postivnsw = add nsw i32 %ivnsw, 1
   %postofsnsw = sext i32 %postivnsw to i64
-  %postadrnsw = getelementptr i8* %base, i64 %postofsnsw
+  %postadrnsw = getelementptr i8, i8* %base, i64 %postofsnsw
   store i8 0, i8* %postadrnsw
   %cond = icmp sgt i32 %limit, %postiv
   br i1 %cond, label %loop, label %exit
@@ -88,7 +88,7 @@ outerloop:
 
   %outercountdec = add i32 %outercount, -1
   %ofs1 = sext i32 %outercountdec to i64
-  %adr1 = getelementptr i8* %address, i64 %ofs1
+  %adr1 = getelementptr i8, i8* %address, i64 %ofs1
   store i8 0, i8* %adr1
 
   br label %innerpreheader
@@ -112,11 +112,11 @@ innerloop:
   %innerpostiv = add i32 %inneriv, 1
 
   %ofs2 = sext i32 %inneriv to i64
-  %adr2 = getelementptr i8* %address, i64 %ofs2
+  %adr2 = getelementptr i8, i8* %address, i64 %ofs2
   store i8 0, i8* %adr2
 
   %ofs3 = sext i32 %innerpostiv to i64
-  %adr3 = getelementptr i8* %address, i64 %ofs3
+  %adr3 = getelementptr i8, i8* %address, i64 %ofs3
   store i8 0, i8* %adr3
 
   %innercmp = icmp sgt i32 %limitdec, %innerpostiv
@@ -137,11 +137,11 @@ outermerge:
   %innercount.merge = phi i32 [ %innercount.lcssa, %innerexit ], [ %innercount, %innerpreheader ]
 
   %ofs4 = sext i32 %outercount to i64
-  %adr4 = getelementptr i8* %address, i64 %ofs4
+  %adr4 = getelementptr i8, i8* %address, i64 %ofs4
   store i8 0, i8* %adr4
 
   %ofs5 = sext i32 %innercount.merge to i64
-  %adr5 = getelementptr i8* %address, i64 %ofs5
+  %adr5 = getelementptr i8, i8* %address, i64 %ofs5
   store i8 0, i8* %adr5
 
   %outerpostcount = add i32 %outercount, 1
diff --git a/test/Transforms/IndVarSimplify/eliminate-comparison.ll b/test/Transforms/IndVarSimplify/eliminate-comparison.ll
index b48403e9a23b..4d14b3681c5d 100644
--- a/test/Transforms/IndVarSimplify/eliminate-comparison.ll
+++ b/test/Transforms/IndVarSimplify/eliminate-comparison.ll
@@ -16,7 +16,7 @@ entry:
   br i1 %cmp9, label %pre, label %return
 
 pre:
-  %t3 = load i32* %p
+  %t3 = load i32, i32* %p
   %tobool.not = icmp ne i32 %t3, 0
   br label %loop
 
@@ -27,7 +27,7 @@ loop:
   br i1 %cond, label %if.then, label %for.inc
 
 if.then:
-  %arrayidx = getelementptr [0 x double]* @X, i64 0, i64 %i
+  %arrayidx = getelementptr [0 x double], [0 x double]* @X, i64 0, i64 %i
   store double 3.200000e+00, double* %arrayidx
   br label %for.inc
 
@@ -50,22 +50,22 @@ entry:
   br label %bb18
 
 bb13:
-  %tmp66 = load i64** %tmp65, align 4
-  %tmp68 = getelementptr inbounds i64* %tmp66, i32 %i
-  %tmp69 = load i64* %tmp68, align 4
-  %tmp74 = load i64** %tmp73, align 4
-  %tmp76 = getelementptr inbounds i64* %tmp74, i32 %i
-  %tmp77 = load i64* %tmp76, align 4
+  %tmp66 = load i64*, i64** %tmp65, align 4
+  %tmp68 = getelementptr inbounds i64, i64* %tmp66, i32 %i
+  %tmp69 = load i64, i64* %tmp68, align 4
+  %tmp74 = load i64*, i64** %tmp73, align 4
+  %tmp76 = getelementptr inbounds i64, i64* %tmp74, i32 %i
+  %tmp77 = load i64, i64* %tmp76, align 4
   %tmp78 = icmp ugt i64 %tmp69, %tmp77
   br i1 %tmp78, label %bb20.loopexit, label %bb15
 
 bb15:
-  %tmp83 = load i64** %tmp82, align 4
-  %tmp85 = getelementptr inbounds i64* %tmp83, i32 %i
-  %tmp86 = load i64* %tmp85, align 4
-  %tmp91 = load i64** %tmp90, align 4
-  %tmp93 = getelementptr inbounds i64* %tmp91, i32 %i
-  %tmp94 = load i64* %tmp93, align 4
+  %tmp83 = load i64*, i64** %tmp82, align 4
+  %tmp85 = getelementptr inbounds i64, i64* %tmp83, i32 %i
+  %tmp86 = load i64, i64* %tmp85, align 4
+  %tmp91 = load i64*, i64** %tmp90, align 4
+  %tmp93 = getelementptr inbounds i64, i64* %tmp91, i32 %i
+  %tmp94 = load i64, i64* %tmp93, align 4
   %tmp95 = icmp ult i64 %tmp86, %tmp94
   br i1 %tmp95, label %bb20.loopexit, label %bb17
 
diff --git a/test/Transforms/IndVarSimplify/eliminate-max.ll b/test/Transforms/IndVarSimplify/eliminate-max.ll
index 98510eaed3f4..5831b9378a9a 100644
--- a/test/Transforms/IndVarSimplify/eliminate-max.ll
+++ b/test/Transforms/IndVarSimplify/eliminate-max.ll
@@ -45,7 +45,7 @@ bb14:                                             ; preds = %bb11, %bb7
   br i1 %t20, label %bb1, label %bb21
 
 bb21:                                             ; preds = %bb14
-  %t22 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([4 x i8]* @0, i32 0, i32 0), i32 %t18) nounwind
+  %t22 = call i32 (i8*, ...) @printf(i8* noalias getelementptr inbounds ([4 x i8], [4 x i8]* @0, i32 0, i32 0), i32 %t18) nounwind
   ret i32 0
 }
 
diff --git a/test/Transforms/IndVarSimplify/eliminate-rem.ll b/test/Transforms/IndVarSimplify/eliminate-rem.ll
index 64fe7107b633..6f8e6bbac775 100644
--- a/test/Transforms/IndVarSimplify/eliminate-rem.ll
+++ b/test/Transforms/IndVarSimplify/eliminate-rem.ll
@@ -18,7 +18,7 @@ bb4:                                              ; preds = %bb
 bb5:                                              ; preds = %bb4, %bb5
   %t6 = phi i64 [ %t9, %bb5 ], [ 0, %bb4 ]    ; <i64> [#uses=2]
   %t7 = srem i64 %t6, %arg                    ; <i64> [#uses=1]
-  %t8 = getelementptr inbounds double* %arg3, i64 %t7 ; <double*> [#uses=1]
+  %t8 = getelementptr inbounds double, double* %arg3, i64 %t7 ; <double*> [#uses=1]
   store double 0.000000e+00, double* %t8
   %t9 = add nsw i64 %t6, 1                    ; <i64> [#uses=2]
   %t10 = icmp slt i64 %t9, %arg               ; <i1> [#uses=1]
@@ -78,16 +78,16 @@ bb21:                                             ; preds = %bb21, %bb20
   %t26 = add nsw i64 %t24, %t22                   ; <i64> [#uses=1]
   %t27 = mul i64 %t11, %arg1                      ; <i64> [#uses=1]
   %t28 = add nsw i64 %t25, %t22                   ; <i64> [#uses=1]
-  %t29 = getelementptr inbounds i64* %arg, i64 %t26 ; <i64*> [#uses=1]
+  %t29 = getelementptr inbounds i64, i64* %arg, i64 %t26 ; <i64*> [#uses=1]
   %t30 = add nsw i64 %t27, %t22                   ; <i64> [#uses=1]
-  %t31 = getelementptr inbounds i64* %arg, i64 %t28 ; <i64*> [#uses=1]
+  %t31 = getelementptr inbounds i64, i64* %arg, i64 %t28 ; <i64*> [#uses=1]
   %t32 = zext i32 %t23 to i64                     ; <i64> [#uses=1]
-  %t33 = load i64* %t29                           ; <i64> [#uses=1]
-  %t34 = getelementptr inbounds i64* %arg, i64 %t30 ; <i64*> [#uses=1]
-  %t35 = load i64* %t31                           ; <i64> [#uses=1]
+  %t33 = load i64, i64* %t29                           ; <i64> [#uses=1]
+  %t34 = getelementptr inbounds i64, i64* %arg, i64 %t30 ; <i64*> [#uses=1]
+  %t35 = load i64, i64* %t31                           ; <i64> [#uses=1]
   %t36 = add nsw i64 %t32, %t33                   ; <i64> [#uses=1]
   %t37 = add nsw i64 %t36, %t35                   ; <i64> [#uses=1]
-  %t38 = load i64* %t34                           ; <i64> [#uses=1]
+  %t38 = load i64, i64* %t34                           ; <i64> [#uses=1]
   %t39 = add nsw i64 %t37, %t38                   ; <i64> [#uses=1]
   %t40 = trunc i64 %t39 to i32                    ; <i32> [#uses=2]
   %t41 = add nsw i64 %t22, 1                      ; <i64> [#uses=2]
diff --git a/test/Transforms/IndVarSimplify/indirectbr.ll b/test/Transforms/IndVarSimplify/indirectbr.ll
index a208ded22ed1..d5801690d5e0 100644
--- a/test/Transforms/IndVarSimplify/indirectbr.ll
+++ b/test/Transforms/IndVarSimplify/indirectbr.ll
@@ -32,8 +32,8 @@ bb14:                                             ; preds = %bb14, %bb7.preheade
 bb16:                                             ; preds = %bb16, %bb14, %bb7.preheader
   %S.31.0 = phi i64 [ %3, %bb16 ], [ 1, %bb7.preheader ], [ 1, %bb14 ] ; <i64> [#uses=2]
   %0 = add nsw i64 %S.31.0, -1                    ; <i64> [#uses=1]
-  %1 = getelementptr inbounds [3 x double]* undef, i64 0, i64 %0 ; <double*> [#uses=1]
-  %2 = load double* %1, align 8                   ; <double> [#uses=0]
+  %1 = getelementptr inbounds [3 x double], [3 x double]* undef, i64 0, i64 %0 ; <double*> [#uses=1]
+  %2 = load double, double* %1, align 8                   ; <double> [#uses=0]
   %3 = add nsw i64 %S.31.0, 1                     ; <i64> [#uses=1]
   br label %bb16
 }
diff --git a/test/Transforms/IndVarSimplify/iv-fold.ll b/test/Transforms/IndVarSimplify/iv-fold.ll
index 41a1f5ff91a2..af8a33b30ea9 100644
--- a/test/Transforms/IndVarSimplify/iv-fold.ll
+++ b/test/Transforms/IndVarSimplify/iv-fold.ll
@@ -13,12 +13,12 @@ entry:
 while.body:
   %0 = phi i32 [ 0, %entry ], [ %inc.2, %while.body ]
   %shr = lshr i32 %0, 5
-  %arrayidx = getelementptr inbounds i32* %bitmap, i32 %shr
-  %tmp6 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %bitmap, i32 %shr
+  %tmp6 = load i32, i32* %arrayidx, align 4
   %inc.1 = add i32 %0, 1
   %shr.1 = lshr i32 %inc.1, 5
-  %arrayidx.1 = getelementptr inbounds i32* %bitmap, i32 %shr.1
-  %tmp6.1 = load i32* %arrayidx.1, align 4
+  %arrayidx.1 = getelementptr inbounds i32, i32* %bitmap, i32 %shr.1
+  %tmp6.1 = load i32, i32* %arrayidx.1, align 4
   %inc.2 = add i32 %inc.1, 1
   %exitcond.3 = icmp eq i32 %inc.2, 128
   br i1 %exitcond.3, label %while.end, label %while.body
@@ -40,12 +40,12 @@ entry:
 while.body:
   %0 = phi i32 [ 0, %entry ], [ %inc.3, %while.body ]
   %shr = lshr i32 %0, 5
-  %arrayidx = getelementptr inbounds i32* %bitmap, i32 %shr
-  %tmp6 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %bitmap, i32 %shr
+  %tmp6 = load i32, i32* %arrayidx, align 4
   %inc.1 = add i32 %0, 1
   %shr.1 = lshr i32 %inc.1, 5
-  %arrayidx.1 = getelementptr inbounds i32* %bitmap, i32 %shr.1
-  %tmp6.1 = load i32* %arrayidx.1, align 4
+  %arrayidx.1 = getelementptr inbounds i32, i32* %bitmap, i32 %shr.1
+  %tmp6.1 = load i32, i32* %arrayidx.1, align 4
   %inc.3 = add i32 %inc.1, 2
   %exitcond.3 = icmp eq i32 %inc.3, 96
   br i1 %exitcond.3, label %while.end, label %while.body
diff --git a/test/Transforms/IndVarSimplify/iv-sext.ll b/test/Transforms/IndVarSimplify/iv-sext.ll
index 04df0f9aa5fa..89e21e1b2690 100644
--- a/test/Transforms/IndVarSimplify/iv-sext.ll
+++ b/test/Transforms/IndVarSimplify/iv-sext.ll
@@ -8,7 +8,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 define void @t(float* %pTmp1, float* %peakWeight, float* %nrgReducePeakrate, i32 %bandEdgeIndex, float %tmp1) nounwind {
 entry:
-	%tmp = load float* %peakWeight, align 4		; <float> [#uses=1]
+	%tmp = load float, float* %peakWeight, align 4		; <float> [#uses=1]
 	%tmp2 = icmp sgt i32 %bandEdgeIndex, 0		; <i1> [#uses=1]
 	br i1 %tmp2, label %bb.nph22, label %return
 
@@ -33,13 +33,13 @@ bb:		; preds = %bb8, %bb.nph22
 bb1:		; preds = %bb
 	%tmp5 = add i32 %part.016, -1		; <i32> [#uses=1]
 	%tmp6 = sext i32 %tmp5 to i64		; <i64> [#uses=1]
-	%tmp7 = getelementptr float* %pTmp1, i64 %tmp6		; <float*> [#uses=1]
-	%tmp8 = load float* %tmp7, align 4		; <float> [#uses=1]
+	%tmp7 = getelementptr float, float* %pTmp1, i64 %tmp6		; <float*> [#uses=1]
+	%tmp8 = load float, float* %tmp7, align 4		; <float> [#uses=1]
 	%tmp9 = fadd float %tmp8, %distERBlo.120		; <float> [#uses=1]
 	%tmp10 = add i32 %part.016, -1		; <i32> [#uses=1]
 	%tmp11 = sext i32 %tmp10 to i64		; <i64> [#uses=1]
-	%tmp12 = getelementptr float* %pTmp1, i64 %tmp11		; <float*> [#uses=1]
-	%tmp13 = load float* %tmp12, align 4		; <float> [#uses=1]
+	%tmp12 = getelementptr float, float* %pTmp1, i64 %tmp11		; <float*> [#uses=1]
+	%tmp13 = load float, float* %tmp12, align 4		; <float> [#uses=1]
 	%tmp14 = fsub float %distERBhi.121, %tmp13		; <float> [#uses=1]
 	br label %bb3.preheader
 
@@ -57,12 +57,12 @@ bb2:		; preds = %bb3, %bb.nph
 	%loPart.02 = phi i32 [ %tmp24, %bb3 ], [ %loPart.118, %bb.nph ]		; <i32> [#uses=3]
 	%peakCount.01 = phi float [ %tmp23, %bb3 ], [ %peakCount.117, %bb.nph ]		; <float> [#uses=1]
 	%tmp16 = sext i32 %loPart.02 to i64		; <i64> [#uses=1]
-	%tmp17 = getelementptr float* %pTmp1, i64 %tmp16		; <float*> [#uses=1]
-	%tmp18 = load float* %tmp17, align 4		; <float> [#uses=1]
+	%tmp17 = getelementptr float, float* %pTmp1, i64 %tmp16		; <float*> [#uses=1]
+	%tmp18 = load float, float* %tmp17, align 4		; <float> [#uses=1]
 	%tmp19 = fsub float %distERBlo.03, %tmp18		; <float> [#uses=3]
 	%tmp20 = sext i32 %loPart.02 to i64		; <i64> [#uses=1]
-	%tmp21 = getelementptr float* %peakWeight, i64 %tmp20		; <float*> [#uses=1]
-	%tmp22 = load float* %tmp21, align 4		; <float> [#uses=1]
+	%tmp21 = getelementptr float, float* %peakWeight, i64 %tmp20		; <float*> [#uses=1]
+	%tmp22 = load float, float* %tmp21, align 4		; <float> [#uses=1]
 	%tmp23 = fsub float %peakCount.01, %tmp22		; <float> [#uses=2]
 	%tmp24 = add i32 %loPart.02, 1		; <i32> [#uses=2]
 	br label %bb3
@@ -97,13 +97,13 @@ bb4:		; preds = %bb5, %bb.nph12
 	%hiPart.08 = phi i32 [ %tmp31, %bb5 ], [ %hiPart.119, %bb.nph12 ]		; <i32> [#uses=2]
 	%peakCount.27 = phi float [ %tmp35, %bb5 ], [ %peakCount.0.lcssa, %bb.nph12 ]		; <float> [#uses=1]
 	%tmp27 = sext i32 %hiPart.08 to i64		; <i64> [#uses=1]
-	%tmp28 = getelementptr float* %pTmp1, i64 %tmp27		; <float*> [#uses=1]
-	%tmp29 = load float* %tmp28, align 4		; <float> [#uses=1]
+	%tmp28 = getelementptr float, float* %pTmp1, i64 %tmp27		; <float*> [#uses=1]
+	%tmp29 = load float, float* %tmp28, align 4		; <float> [#uses=1]
 	%tmp30 = fadd float %tmp29, %distERBhi.29		; <float> [#uses=3]
 	%tmp31 = add i32 %hiPart.08, 1		; <i32> [#uses=4]
 	%tmp32 = sext i32 %tmp31 to i64		; <i64> [#uses=1]
-	%tmp33 = getelementptr float* %peakWeight, i64 %tmp32		; <float*> [#uses=1]
-	%tmp34 = load float* %tmp33, align 4		; <float> [#uses=1]
+	%tmp33 = getelementptr float, float* %peakWeight, i64 %tmp32		; <float*> [#uses=1]
+	%tmp34 = load float, float* %tmp33, align 4		; <float> [#uses=1]
 	%tmp35 = fadd float %tmp34, %peakCount.27		; <float> [#uses=2]
 	br label %bb5
 
@@ -132,7 +132,7 @@ bb7:		; preds = %bb5.bb7_crit_edge, %bb5.preheader
 	%tmp42 = fadd float %tmp41, 1.000000e+00		; <float> [#uses=1]
 	%tmp43 = fdiv float 1.000000e+00, %tmp42		; <float> [#uses=1]
 	%tmp44 = sext i32 %part.016 to i64		; <i64> [#uses=1]
-	%tmp45 = getelementptr float* %nrgReducePeakrate, i64 %tmp44		; <float*> [#uses=1]
+	%tmp45 = getelementptr float, float* %nrgReducePeakrate, i64 %tmp44		; <float*> [#uses=1]
 	store float %tmp43, float* %tmp45, align 4
 	%tmp46 = add i32 %part.016, 1		; <i32> [#uses=2]
 	br label %bb8
diff --git a/test/Transforms/IndVarSimplify/iv-widen.ll b/test/Transforms/IndVarSimplify/iv-widen.ll
index c899e2f0a580..464b03ce5595 100644
--- a/test/Transforms/IndVarSimplify/iv-widen.ll
+++ b/test/Transforms/IndVarSimplify/iv-widen.ll
@@ -1,5 +1,9 @@
 ; RUN: opt < %s -indvars -S | FileCheck %s
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+
 target triple = "x86_64-apple-darwin"
 
 ; CHECK-LABEL: @sloop
@@ -20,8 +24,8 @@ B18:                                        ; preds = %B24, %Prologue
   %.02 = phi i32 [ 0, %Prologue ], [ %tmp33, %B24 ]
   %tmp23 = zext i32 %.02 to i64
   %tmp33 = add i32 %.02, 1
-  %o = getelementptr i32* %a, i32 %.02
-  %v = load i32* %o
+  %o = getelementptr i32, i32* %a, i32 %.02
+  %v = load i32, i32* %o
   %t = icmp eq i32 %v, 0
   br i1 %t, label %exit24, label %B24
 
diff --git a/test/Transforms/IndVarSimplify/iv-zext.ll b/test/Transforms/IndVarSimplify/iv-zext.ll
index ed0514b08e33..629a85efe8e1 100644
--- a/test/Transforms/IndVarSimplify/iv-zext.ll
+++ b/test/Transforms/IndVarSimplify/iv-zext.ll
@@ -11,17 +11,17 @@ entry:
 loop:
 	%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
 	%indvar.i8 = and i64 %indvar, 255
-	%t0 = getelementptr double* %d, i64 %indvar.i8
-	%t1 = load double* %t0
+	%t0 = getelementptr double, double* %d, i64 %indvar.i8
+	%t1 = load double, double* %t0
 	%t2 = fmul double %t1, 0.1
 	store double %t2, double* %t0
 	%indvar.i24 = and i64 %indvar, 16777215
-	%t3 = getelementptr double* %d, i64 %indvar.i24
-	%t4 = load double* %t3
+	%t3 = getelementptr double, double* %d, i64 %indvar.i24
+	%t4 = load double, double* %t3
 	%t5 = fmul double %t4, 2.3
 	store double %t5, double* %t3
-	%t6 = getelementptr double* %d, i64 %indvar
-	%t7 = load double* %t6
+	%t6 = getelementptr double, double* %d, i64 %indvar
+	%t7 = load double, double* %t6
 	%t8 = fmul double %t7, 4.5
 	store double %t8, double* %t6
 	%indvar.next = add i64 %indvar, 1
diff --git a/test/Transforms/IndVarSimplify/lftr-address-space-pointers.ll b/test/Transforms/IndVarSimplify/lftr-address-space-pointers.ll
index 9e55a1791341..feb4b35a20a7 100644
--- a/test/Transforms/IndVarSimplify/lftr-address-space-pointers.ll
+++ b/test/Transforms/IndVarSimplify/lftr-address-space-pointers.ll
@@ -6,12 +6,12 @@ define void @ptriv_as2(i8 addrspace(2)* %base, i32 %n) nounwind {
 ; CHECK-LABEL: @ptriv_as2(
 entry:
   %idx.trunc = trunc i32 %n to i8
-  %add.ptr = getelementptr inbounds i8 addrspace(2)* %base, i8 %idx.trunc
+  %add.ptr = getelementptr inbounds i8, i8 addrspace(2)* %base, i8 %idx.trunc
   %cmp1 = icmp ult i8 addrspace(2)* %base, %add.ptr
   br i1 %cmp1, label %for.body, label %for.end
 
 ; Make sure the added GEP has the right index type
-; CHECK: %lftr.limit = getelementptr i8 addrspace(2)* %base, i8
+; CHECK: %lftr.limit = getelementptr i8, i8 addrspace(2)* %base, i8 %0
 
 ; CHECK: for.body:
 ; CHECK: phi i8 addrspace(2)*
@@ -26,7 +26,7 @@ for.body:
   %sub.ptr.rhs.cast = ptrtoint i8 addrspace(2)* %base to i8
   %sub.ptr.sub = sub i8 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast
   store i8 %sub.ptr.sub, i8 addrspace(2)* %p.02
-  %incdec.ptr = getelementptr inbounds i8 addrspace(2)* %p.02, i32 1
+  %incdec.ptr = getelementptr inbounds i8, i8 addrspace(2)* %p.02, i32 1
   %cmp = icmp ult i8 addrspace(2)* %incdec.ptr, %add.ptr
   br i1 %cmp, label %for.body, label %for.end
 
@@ -38,12 +38,12 @@ define void @ptriv_as3(i8 addrspace(3)* %base, i32 %n) nounwind {
 ; CHECK-LABEL: @ptriv_as3(
 entry:
   %idx.trunc = trunc i32 %n to i16
-  %add.ptr = getelementptr inbounds i8 addrspace(3)* %base, i16 %idx.trunc
+  %add.ptr = getelementptr inbounds i8, i8 addrspace(3)* %base, i16 %idx.trunc
   %cmp1 = icmp ult i8 addrspace(3)* %base, %add.ptr
   br i1 %cmp1, label %for.body, label %for.end
 
 ; Make sure the added GEP has the right index type
-; CHECK: %lftr.limit = getelementptr i8 addrspace(3)* %base, i16
+; CHECK: %lftr.limit = getelementptr i8, i8 addrspace(3)* %base, i16 %0
 
 ; CHECK: for.body:
 ; CHECK: phi i8 addrspace(3)*
@@ -59,7 +59,7 @@ for.body:
   %sub.ptr.sub = sub i16 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast
   %conv = trunc i16 %sub.ptr.sub to i8
   store i8 %conv, i8 addrspace(3)* %p.02
-  %incdec.ptr = getelementptr inbounds i8 addrspace(3)* %p.02, i32 1
+  %incdec.ptr = getelementptr inbounds i8, i8 addrspace(3)* %p.02, i32 1
   %cmp = icmp ult i8 addrspace(3)* %incdec.ptr, %add.ptr
   br i1 %cmp, label %for.body, label %for.end
 
diff --git a/test/Transforms/IndVarSimplify/lftr-extend-const.ll b/test/Transforms/IndVarSimplify/lftr-extend-const.ll
index f12c68cacb66..fa3166d4a3e2 100644
--- a/test/Transforms/IndVarSimplify/lftr-extend-const.ll
+++ b/test/Transforms/IndVarSimplify/lftr-extend-const.ll
@@ -1,5 +1,9 @@
 ;RUN: opt -S %s -indvars | FileCheck %s
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+
 ; CHECK-LABEL: @foo(
 ; CHECK-NOT: %lftr.wideiv = trunc i32 %indvars.iv.next to i16
 ; CHECK: %exitcond = icmp ne i32 %indvars.iv.next, 512
diff --git a/test/Transforms/IndVarSimplify/lftr-promote.ll b/test/Transforms/IndVarSimplify/lftr-promote.ll
index c4ecc845562b..4fe3191391b0 100644
--- a/test/Transforms/IndVarSimplify/lftr-promote.ll
+++ b/test/Transforms/IndVarSimplify/lftr-promote.ll
@@ -17,11 +17,11 @@ bb.nph:		; preds = %entry
 bb2:		; preds = %bb3, %bb.nph
 	%i.01 = phi i32 [ %7, %bb3 ], [ 0, %bb.nph ]		; <i32> [#uses=3]
 	%1 = sext i32 %i.01 to i64		; <i64> [#uses=1]
-	%2 = getelementptr double* %p, i64 %1		; <double*> [#uses=1]
-	%3 = load double* %2, align 8		; <double> [#uses=1]
+	%2 = getelementptr double, double* %p, i64 %1		; <double*> [#uses=1]
+	%3 = load double, double* %2, align 8		; <double> [#uses=1]
 	%4 = fmul double %3, 1.100000e+00		; <double> [#uses=1]
 	%5 = sext i32 %i.01 to i64		; <i64> [#uses=1]
-	%6 = getelementptr double* %p, i64 %5		; <double*> [#uses=1]
+	%6 = getelementptr double, double* %p, i64 %5		; <double*> [#uses=1]
 	store double %4, double* %6, align 8
 	%7 = add i32 %i.01, 1		; <i32> [#uses=2]
 	br label %bb3
diff --git a/test/Transforms/IndVarSimplify/lftr-reuse.ll b/test/Transforms/IndVarSimplify/lftr-reuse.ll
index efb96bdbe6b5..b4e1fdef4885 100644
--- a/test/Transforms/IndVarSimplify/lftr-reuse.ll
+++ b/test/Transforms/IndVarSimplify/lftr-reuse.ll
@@ -12,7 +12,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 define void @ptriv(i8* %base, i32 %n) nounwind {
 entry:
   %idx.ext = sext i32 %n to i64
-  %add.ptr = getelementptr inbounds i8* %base, i64 %idx.ext
+  %add.ptr = getelementptr inbounds i8, i8* %base, i64 %idx.ext
   %cmp1 = icmp ult i8* %base, %add.ptr
   br i1 %cmp1, label %for.body, label %for.end
 
@@ -30,7 +30,7 @@ for.body:
   %sub.ptr.sub = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast
   %conv = trunc i64 %sub.ptr.sub to i8
   store i8 %conv, i8* %p.02
-  %incdec.ptr = getelementptr inbounds i8* %p.02, i32 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %p.02, i32 1
   %cmp = icmp ult i8* %incdec.ptr, %add.ptr
   br i1 %cmp, label %for.body, label %for.end
 
@@ -82,23 +82,15 @@ exit:
 ; Perform LFTR without generating extra preheader code.
 define void @guardedloop([0 x double]* %matrix, [0 x double]* %vector,
                          i32 %irow, i32 %ilead) nounwind {
-; CHECK-LABEL: @guardedloop(
-; CHECK-LABEL: entry:
-; CHECK-NEXT: %[[cmp:.*]] = icmp slt i32 1, %irow
-; CHECK-NEXT: br i1 %[[cmp]], label %[[loop_preheader:.*]], label %[[return:.*]]
-
-; CHECK: [[loop_preheader]]:
-; CHECK-NEXT: %[[sext:.*]] = sext i32 %ilead to i64
-; CHECK-NEXT: %[[add:.*]] = add i32 %irow, -1
-; CHECK-NEXT: br label %[[loop:.*]]
-
-; CHECK: [[loop]]:
-; CHECK-NEXT: %[[indvars_iv2:.*]] = phi i64
-; CHECK-NEXT: phi i64
+; CHECK: entry:
+; CHECK-NOT: zext
+; CHECK-NOT: add
+; CHECK: loop:
+; CHECK: phi i64
+; CHECK: phi i64
 ; CHECK-NOT: phi
-; CHECK: %[[lftr_wideiv:.*]] = trunc i64 %[[indvars_iv2]] to i32
-; CHECK-NEXT: %[[exitcond:.*]] = icmp ne i32 %[[lftr_wideiv]], %[[add]]
-; CHECK-NEXT: br i1 %[[exitcond]], label %[[loop]], label
+; CHECK: icmp ne
+; CHECK: br i1
 entry:
   %cmp = icmp slt i32 1, %irow
   br i1 %cmp, label %loop, label %return
@@ -108,11 +100,11 @@ loop:
   %i = phi i32 [ 0, %entry ], [ %i.inc, %loop ]
   %diagidx = add nsw i32 %rowidx, %i
   %diagidxw = sext i32 %diagidx to i64
-  %matrixp = getelementptr inbounds [0 x double]* %matrix, i32 0, i64 %diagidxw
-  %v1 = load double* %matrixp
+  %matrixp = getelementptr inbounds [0 x double], [0 x double]* %matrix, i32 0, i64 %diagidxw
+  %v1 = load double, double* %matrixp
   %iw = sext i32 %i to i64
-  %vectorp = getelementptr inbounds [0 x double]* %vector, i32 0, i64 %iw
-  %v2 = load double* %vectorp
+  %vectorp = getelementptr inbounds [0 x double], [0 x double]* %vector, i32 0, i64 %iw
+  %v2 = load double, double* %vectorp
   %row.inc = add nsw i32 %rowidx, %ilead
   %i.inc = add nsw i32 %i, 1
   %cmp196 = icmp slt i32 %i.inc, %irow
@@ -142,11 +134,11 @@ loop:
   %i = phi i32 [ 0, %entry ], [ %i.inc, %loop ]
   %diagidx = add nsw i32 %rowidx, %i
   %diagidxw = sext i32 %diagidx to i64
-  %matrixp = getelementptr inbounds [0 x double]* %matrix, i32 0, i64 %diagidxw
-  %v1 = load double* %matrixp
+  %matrixp = getelementptr inbounds [0 x double], [0 x double]* %matrix, i32 0, i64 %diagidxw
+  %v1 = load double, double* %matrixp
   %iw = sext i32 %i to i64
-  %vectorp = getelementptr inbounds [0 x double]* %vector, i32 0, i64 %iw
-  %v2 = load double* %vectorp
+  %vectorp = getelementptr inbounds [0 x double], [0 x double]* %vector, i32 0, i64 %iw
+  %v2 = load double, double* %vectorp
   %row.inc = add nsw i32 %rowidx, %ilead
   %i.inc = add nsw i32 %i, 1
   %cmp196 = icmp slt i32 %i.inc, %irow
@@ -165,9 +157,9 @@ return:
 define void @geplftr(i8* %base, i32 %x, i32 %y, i32 %n) nounwind {
 entry:
   %x.ext = sext i32 %x to i64
-  %add.ptr = getelementptr inbounds i8* %base, i64 %x.ext
+  %add.ptr = getelementptr inbounds i8, i8* %base, i64 %x.ext
   %y.ext = sext i32 %y to i64
-  %add.ptr10 = getelementptr inbounds i8* %add.ptr, i64 %y.ext
+  %add.ptr10 = getelementptr inbounds i8, i8* %add.ptr, i64 %y.ext
   %lim = add i32 %x, %n
   %cmp.ph = icmp ult i32 %x, %lim
   br i1 %cmp.ph, label %loop, label %exit
@@ -182,7 +174,7 @@ entry:
 loop:
   %i = phi i32 [ %x, %entry ], [ %inc, %loop ]
   %aptr = phi i8* [ %add.ptr10, %entry ], [ %incdec.ptr, %loop ]
-  %incdec.ptr = getelementptr inbounds i8* %aptr, i32 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %aptr, i32 1
   store i8 3, i8* %aptr
   %inc = add i32 %i, 1
   %cmp = icmp ult i32 %inc, %lim
@@ -215,8 +207,8 @@ exit:
 ; Test LFTR on an IV whose recurrence start is a non-unit pointer type.
 define void @aryptriv([256 x i8]* %base, i32 %n) nounwind {
 entry:
-  %ivstart = getelementptr inbounds [256 x i8]* %base, i32 0, i32 0
-  %ivend = getelementptr inbounds [256 x i8]* %base, i32 0, i32 %n
+  %ivstart = getelementptr inbounds [256 x i8], [256 x i8]* %base, i32 0, i32 0
+  %ivend = getelementptr inbounds [256 x i8], [256 x i8]* %base, i32 0, i32 %n
   %cmp.ph = icmp ult i8* %ivstart, %ivend
   br i1 %cmp.ph, label %loop, label %exit
 
@@ -229,7 +221,7 @@ entry:
 ; CHECK: br i1
 loop:
   %aptr = phi i8* [ %ivstart, %entry ], [ %incdec.ptr, %loop ]
-  %incdec.ptr = getelementptr inbounds i8* %aptr, i32 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %aptr, i32 1
   store i8 3, i8* %aptr
   %cmp = icmp ult i8* %incdec.ptr, %ivend
   br i1 %cmp, label %loop, label %exit
diff --git a/test/Transforms/IndVarSimplify/lftr-udiv-tripcount.ll b/test/Transforms/IndVarSimplify/lftr-udiv-tripcount.ll
new file mode 100644
index 000000000000..8a1bb07bb0c2
--- /dev/null
+++ b/test/Transforms/IndVarSimplify/lftr-udiv-tripcount.ll
@@ -0,0 +1,29 @@
+; RUN: opt < %s -indvars -S | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+; It is okay to do LFTR on this loop even though the trip count is a
+; division because in this case the division can be optimized to a
+; shift.
+
+define void @foo(i8* %a, i8 %n) nounwind uwtable ssp {
+; CHECK-LABEL: @foo(
+ entry:
+  %e = icmp sgt i8 %n, 3
+  br i1 %e, label %loop, label %exit
+
+ loop:
+; CHECK-LABEL: loop:
+  %i = phi i8 [ 0, %entry ], [ %i.inc, %loop ]
+  %i1 = phi i8 [ 0, %entry ], [ %i1.inc, %loop ]
+  %i.inc = add nsw i8 %i, 4
+  %i1.inc = add i8 %i1, 1
+  store volatile i8 0, i8* %a
+  %c = icmp slt i8 %i, %n
+; CHECK-LABEL:  %exitcond = icmp ne i8 %i1.inc
+  br i1 %c, label %loop, label %exit
+
+ exit:
+; CHECK-LABEL: exit:
+  ret void
+}
diff --git a/test/Transforms/IndVarSimplify/lftr-zext.ll b/test/Transforms/IndVarSimplify/lftr-zext.ll
index 32fa61af1801..e654e143cee3 100644
--- a/test/Transforms/IndVarSimplify/lftr-zext.ll
+++ b/test/Transforms/IndVarSimplify/lftr-zext.ll
@@ -11,11 +11,11 @@ define void @foo(i8* %a) nounwind uwtable ssp {
 
 ; <label>:1                                       ; preds = %0, %1
   %i.0 = phi i8 [ 0, %0 ], [ %5, %1 ]
-  %p.0 = phi i8* [ getelementptr inbounds ([240 x i8]* @data, i64 0, i64 0), %0 ], [ %4, %1 ]
+  %p.0 = phi i8* [ getelementptr inbounds ([240 x i8], [240 x i8]* @data, i64 0, i64 0), %0 ], [ %4, %1 ]
   %.0 = phi i8* [ %a, %0 ], [ %2, %1 ]
-  %2 = getelementptr inbounds i8* %.0, i64 1
-  %3 = load i8* %.0, align 1
-  %4 = getelementptr inbounds i8* %p.0, i64 1
+  %2 = getelementptr inbounds i8, i8* %.0, i64 1
+  %3 = load i8, i8* %.0, align 1
+  %4 = getelementptr inbounds i8, i8* %p.0, i64 1
   store i8 %3, i8* %p.0, align 1
   %5 = add i8 %i.0, 1
   %6 = icmp ult i8 %5, -16
diff --git a/test/Transforms/IndVarSimplify/lftr_simple.ll b/test/Transforms/IndVarSimplify/lftr_simple.ll
index e373013609be..6a8d93721835 100644
--- a/test/Transforms/IndVarSimplify/lftr_simple.ll
+++ b/test/Transforms/IndVarSimplify/lftr_simple.ll
@@ -1,7 +1,11 @@
-; LFTR should eliminate the need for the computation of i*i completely.  It 
+; LFTR should eliminate the need for the computation of i*i completely.  It
 ; is only used to compute the exit value.
 ; RUN: opt < %s -indvars -dce -S | not grep mul
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+
 @A = external global i32                ; <i32*> [#uses=1]
 
 define i32 @quadratic_setlt() {
diff --git a/test/Transforms/IndVarSimplify/loop_evaluate7.ll b/test/Transforms/IndVarSimplify/loop_evaluate7.ll
index b9c0b12f2d97..333ab7a4967b 100644
--- a/test/Transforms/IndVarSimplify/loop_evaluate7.ll
+++ b/test/Transforms/IndVarSimplify/loop_evaluate7.ll
@@ -21,7 +21,7 @@ bb19:		; preds = %bb30
 	br i1 undef, label %bb20, label %bb29
 
 bb20:		; preds = %bb19
-	%0 = load i32* undef, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* undef, align 4		; <i32> [#uses=1]
 	%1 = sub i32 %0, %n		; <i32> [#uses=1]
 	br label %bb23
 
@@ -30,7 +30,7 @@ bb21:		; preds = %bb23
 	br i1 %2, label %bb22, label %overflow2
 
 bb22:		; preds = %bb21
-	%3 = getelementptr i8* %q.0, i32 1		; <i8*> [#uses=1]
+	%3 = getelementptr i8, i8* %q.0, i32 1		; <i8*> [#uses=1]
 	br label %bb23
 
 bb23:		; preds = %bb22, %bb20
diff --git a/test/Transforms/IndVarSimplify/loop_evaluate8.ll b/test/Transforms/IndVarSimplify/loop_evaluate8.ll
index 2a9d20596233..28d05dff2ff8 100644
--- a/test/Transforms/IndVarSimplify/loop_evaluate8.ll
+++ b/test/Transforms/IndVarSimplify/loop_evaluate8.ll
@@ -23,7 +23,7 @@ bb19:		; preds = %bb30
 	br i1 undef, label %bb20, label %bb29
 
 bb20:		; preds = %bb19
-	%0 = load i32* undef, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* undef, align 4		; <i32> [#uses=1]
 	%1 = sub i32 %0, undef		; <i32> [#uses=1]
 	br label %bb23
 
@@ -32,7 +32,7 @@ bb21:		; preds = %bb23
 	br i1 %2, label %bb22, label %overflow2
 
 bb22:		; preds = %bb21
-	%3 = getelementptr i8* %q.0, i32 1		; <i8*> [#uses=1]
+	%3 = getelementptr i8, i8* %q.0, i32 1		; <i8*> [#uses=1]
 	br label %bb23
 
 bb23:		; preds = %bb22, %bb20
diff --git a/test/Transforms/IndVarSimplify/loop_evaluate9.ll b/test/Transforms/IndVarSimplify/loop_evaluate9.ll
index 21fb7ef93167..7a69bd2e131f 100644
--- a/test/Transforms/IndVarSimplify/loop_evaluate9.ll
+++ b/test/Transforms/IndVarSimplify/loop_evaluate9.ll
@@ -28,7 +28,7 @@ bb1.i:		; preds = %bb2.i, %entry
 	br i1 %tmp1, label %bb.i.i, label %bb1.i.i
 
 bb.i.i:		; preds = %bb1.i
-	tail call void @__gnat_rcheck_12(i8* getelementptr ([13 x i8]* @.str, i32 0, i32 0), i32 24) noreturn
+	tail call void @__gnat_rcheck_12(i8* getelementptr ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 24) noreturn
 	unreachable
 
 bb1.i.i:		; preds = %bb1.i
@@ -39,7 +39,7 @@ bb1.i.i:		; preds = %bb1.i
 	br i1 %tmp3, label %bb2.i.i, label %cc70a02__complex_integers__Oadd.153.exit.i
 
 bb2.i.i:		; preds = %bb1.i.i
-	tail call void @__gnat_rcheck_12(i8* getelementptr ([13 x i8]* @.str, i32 0, i32 0), i32 24) noreturn
+	tail call void @__gnat_rcheck_12(i8* getelementptr ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 24) noreturn
 	unreachable
 
 cc70a02__complex_integers__Oadd.153.exit.i:		; preds = %bb1.i.i
diff --git a/test/Transforms/IndVarSimplify/masked-iv.ll b/test/Transforms/IndVarSimplify/masked-iv.ll
index f1f5af96eb96..24fe33d4369f 100644
--- a/test/Transforms/IndVarSimplify/masked-iv.ll
+++ b/test/Transforms/IndVarSimplify/masked-iv.ll
@@ -16,7 +16,7 @@ bb.preheader:		; preds = %entry
 bb:		; preds = %bb, %bb.preheader
 	%i.01 = phi i64 [ %t6, %bb ], [ %a, %bb.preheader ]		; <i64> [#uses=3]
 	%t1 = and i64 %i.01, 255		; <i64> [#uses=1]
-	%t2 = getelementptr i64* %A, i64 %t1		; <i64*> [#uses=1]
+	%t2 = getelementptr i64, i64* %A, i64 %t1		; <i64*> [#uses=1]
 	store i64 %i.01, i64* %t2, align 8
 	%t6 = add i64 %i.01, %s		; <i64> [#uses=1]
 	br label %bb
diff --git a/test/Transforms/IndVarSimplify/no-iv-rewrite.ll b/test/Transforms/IndVarSimplify/no-iv-rewrite.ll
index a7023f24314a..ca7b89911662 100644
--- a/test/Transforms/IndVarSimplify/no-iv-rewrite.ll
+++ b/test/Transforms/IndVarSimplify/no-iv-rewrite.ll
@@ -28,8 +28,8 @@ loop:
   %i.02 = phi i32 [ 0, %ph ], [ %iinc, %loop ]
   %s.01 = phi i32 [ 0, %ph ], [ %sinc, %loop ]
   %ofs = sext i32 %i.02 to i64
-  %adr = getelementptr inbounds i32* %arr, i64 %ofs
-  %val = load i32* %adr
+  %adr = getelementptr inbounds i32, i32* %arr, i64 %ofs
+  %val = load i32, i32* %adr
   %sinc = add nsw i32 %s.01, %val
   %iinc = add nsw i32 %i.02, 1
   %cond = icmp slt i32 %iinc, %n
@@ -69,8 +69,8 @@ loop:
   %i.02 = phi i32 [ 0, %ph ], [ %iinc, %loop ]
   %s.01 = phi i64 [ 0, %ph ], [ %sinc, %loop ]
   %ofs = sext i32 %i.02 to i64
-  %adr = getelementptr inbounds i32* %arr, i64 %ofs
-  %val = load i32* %adr
+  %adr = getelementptr inbounds i32, i32* %arr, i64 %ofs
+  %val = load i32, i32* %adr
   %vall = sext i32 %val to i64
   %sinc = add nsw i64 %s.01, %vall
   %iinc = add nsw i32 %i.02, 1
@@ -106,15 +106,15 @@ ph:
 ; CHECK-NOT: add
 ;
 ; Preserve gep inboundsness, and don't factor it.
-; CHECK: getelementptr inbounds i32* %ptriv, i32 1
+; CHECK: getelementptr inbounds i32, i32* %ptriv, i32 1
 ; CHECK-NOT: add
 ; CHECK: exit:
 loop:
   %ptriv = phi i32* [ %first, %ph ], [ %ptrpost, %loop ]
   %ofs = sext i32 %idx to i64
-  %adr = getelementptr inbounds i32* %ptriv, i64 %ofs
+  %adr = getelementptr inbounds i32, i32* %ptriv, i64 %ofs
   store i32 3, i32* %adr
-  %ptrpost = getelementptr inbounds i32* %ptriv, i32 1
+  %ptrpost = getelementptr inbounds i32, i32* %ptriv, i32 1
   %cond = icmp ne i32* %ptrpost, %last
   br i1 %cond, label %loop, label %exit
 
@@ -143,11 +143,11 @@ entry:
 loop:
   %iv = phi i32 [%start, %entry], [%next, %loop]
   %p = phi %structI* [%base, %entry], [%pinc, %loop]
-  %adr = getelementptr %structI* %p, i32 0, i32 0
+  %adr = getelementptr %structI, %structI* %p, i32 0, i32 0
   store i32 3, i32* %adr
   %pp = bitcast %structI* %p to i32*
   store i32 4, i32* %pp
-  %pinc = getelementptr %structI* %p, i32 1
+  %pinc = getelementptr %structI, %structI* %p, i32 1
   %next = add i32 %iv, 1
   %cond = icmp ne i32 %next, %limit
   br i1 %cond, label %loop, label %exit
@@ -170,8 +170,8 @@ loop:
   %idx = phi i32 [ 0, %entry ], [ %idx.next, %loop.inc ]
   %max = phi i32 [ 0, %entry ], [ %max.next, %loop.inc ]
   %idxprom = sext i32 %idx to i64
-  %adr = getelementptr inbounds i32* %base, i64 %idxprom
-  %val = load i32* %adr
+  %adr = getelementptr inbounds i32, i32* %base, i64 %idxprom
+  %val = load i32, i32* %adr
   %cmp19 = icmp sgt i32 %val, %max
   br i1 %cmp19, label %if.then, label %if.else
 
@@ -239,8 +239,8 @@ entry:
 loop:
   %iv = phi i32 [ 0, %entry], [ %iv.next, %loop ]
   %t1 = sext i32 %iv to i64
-  %adr = getelementptr i64* %base, i64 %t1
-  %val = load i64* %adr
+  %adr = getelementptr i64, i64* %base, i64 %t1
+  %val = load i64, i64* %adr
   %t2 = or i32 %iv, 1
   %t3 = sext i32 %t2 to i64
   %iv.next = add i32 %iv, 2
@@ -333,7 +333,7 @@ return:
 
 define void @congruentgepiv(%structIF* %base) nounwind uwtable ssp {
 entry:
-  %first = getelementptr inbounds %structIF* %base, i64 0, i32 0
+  %first = getelementptr inbounds %structIF, %structIF* %base, i64 0, i32 0
   br label %loop
 
 ; CHECK: loop:
@@ -349,8 +349,8 @@ loop:
   br i1 undef, label %latch, label %exit
 
 latch:                         ; preds = %for.inc50.i
-  %ptr.inc = getelementptr inbounds %structIF* %ptr.iv, i64 1
-  %next.inc = getelementptr inbounds %structIF* %ptr.inc, i64 0, i32 0
+  %ptr.inc = getelementptr inbounds %structIF, %structIF* %ptr.iv, i64 1
+  %next.inc = getelementptr inbounds %structIF, %structIF* %ptr.inc, i64 0, i32 0
   br label %loop
 
 exit:
diff --git a/test/Transforms/IndVarSimplify/overflowcheck.ll b/test/Transforms/IndVarSimplify/overflowcheck.ll
index 2603f363ab60..c3c033dfaece 100644
--- a/test/Transforms/IndVarSimplify/overflowcheck.ll
+++ b/test/Transforms/IndVarSimplify/overflowcheck.ll
@@ -9,7 +9,7 @@ target triple = "x86_64-apple-macosx"
 ; CHECK: @llvm.sadd.with.overflow
 ; CHECK-LABEL: loop2:
 ; CHECK-NOT: extractvalue
-; CHECK: add nuw nsw
+; CHECK: add nuw
 ; CHECK: @llvm.sadd.with.overflow
 ; CHECK-LABEL: loop3:
 ; CHECK-NOT: extractvalue
@@ -27,8 +27,8 @@ loop0:
 loop1:
   %zxt = zext i32 %i to i64
   %ofs = shl nuw nsw i64 %zxt, 3
-  %gep = getelementptr i64* %a, i64 %zxt
-  %v = load i64* %gep, align 8
+  %gep = getelementptr i64, i64* %a, i64 %zxt
+  %v = load i64, i64* %gep, align 8
   %truncv = trunc i64 %v to i32
   %adds = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %s, i32 %truncv)
   %ovflows = extractvalue { i32, i1 } %adds, 1
diff --git a/test/Transforms/IndVarSimplify/phi-uses-value-multiple-times.ll b/test/Transforms/IndVarSimplify/phi-uses-value-multiple-times.ll
index dc36b9948254..519d34d76cbd 100644
--- a/test/Transforms/IndVarSimplify/phi-uses-value-multiple-times.ll
+++ b/test/Transforms/IndVarSimplify/phi-uses-value-multiple-times.ll
@@ -13,7 +13,7 @@ entry:
 	br label %bb38.i
 
 bb14.i27:
-	%t0 = load i64* @ue, align 8
+	%t0 = load i64, i64* @ue, align 8
 	%t1 = sub i64 %t0, %i.0.i35
 	%t2 = add i64 %t1, 1
 	br i1 undef, label %bb15.i28, label %bb19.i31
diff --git a/test/Transforms/IndVarSimplify/polynomial-expand.ll b/test/Transforms/IndVarSimplify/polynomial-expand.ll
index 2087f6a6966b..5708c64d6c8e 100644
--- a/test/Transforms/IndVarSimplify/polynomial-expand.ll
+++ b/test/Transforms/IndVarSimplify/polynomial-expand.ll
@@ -20,8 +20,8 @@ bb30:                                             ; preds = %bb30, %bb24
   %tmp31 = phi i32 [ %tmp39, %bb30 ], [ %tmp28, %bb24 ] ; <i32> [#uses=2]
   %tmp32 = phi i32 [ %tmp37, %bb30 ], [ %tmp27, %bb24 ] ; <i32> [#uses=2]
   %tmp33 = sext i32 %tmp32 to i64                 ; <i64> [#uses=1]
-  %tmp35 = getelementptr float* %tmp4, i64 %tmp33 ; <%0*> [#uses=1]
-  %tmp36 = load float* %tmp35, align 4               ; <%0> [#uses=0]
+  %tmp35 = getelementptr float, float* %tmp4, i64 %tmp33 ; <%0*> [#uses=1]
+  %tmp36 = load float, float* %tmp35, align 4               ; <%0> [#uses=0]
   %tmp37 = add nsw i32 %tmp32, -1                 ; <i32> [#uses=1]
   %tmp39 = add nsw i32 %tmp31, -1                 ; <i32> [#uses=1]
   %tmp38 = icmp eq i32 %tmp31, 1                  ; <i1> [#uses=1]
diff --git a/test/Transforms/IndVarSimplify/pr18223.ll b/test/Transforms/IndVarSimplify/pr18223.ll
index 738f75c0fe03..f922aa424a17 100644
--- a/test/Transforms/IndVarSimplify/pr18223.ll
+++ b/test/Transforms/IndVarSimplify/pr18223.ll
@@ -8,7 +8,7 @@
 
 define i32 @main() #0 {
 entry:
-  %0 = load i32* @c, align 4
+  %0 = load i32, i32* @c, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %for.body, label %exit
 
diff --git a/test/Transforms/IndVarSimplify/pr20680.ll b/test/Transforms/IndVarSimplify/pr20680.ll
index 88a7fd765d0b..2c9eb54a789c 100644
--- a/test/Transforms/IndVarSimplify/pr20680.ll
+++ b/test/Transforms/IndVarSimplify/pr20680.ll
@@ -1,5 +1,9 @@
 ; RUN: opt < %s -indvars -S | FileCheck %s
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+
 @a = common global i32 0, align 4
 @c = common global i32 0, align 4
 @b = common global i32 0, align 4
@@ -13,9 +17,9 @@ define void @f() {
 ; CHECK-NEXT: %[[indvars_iv:.*]] = phi i32 [ %[[indvars_iv_next:.*]], %[[for_inc13:.*]] ], [ -14, %entry ]
 ; br i1 {{.*}}, label %[[for_inc13]], label %
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %tobool2 = icmp eq i32 %0, 0
-  %1 = load i32* @a, align 4
+  %1 = load i32, i32* @a, align 4
   %tobool = icmp eq i32 %1, 0
   br label %for.cond2.preheader
 
@@ -51,7 +55,7 @@ cond.false.us.us:                                 ; preds = %for.body3.us.us
 
 cond.end.us.us:                                   ; preds = %cond.false.us.us, %for.body3.us.us
   %cond.us.us = phi i32 [ %div, %cond.false.us.us ], [ %conv7, %for.body3.us.us ]
-  %4 = load i32* @b, align 4
+  %4 = load i32, i32* @b, align 4
   %cmp91.us.us = icmp slt i32 %4, 1
   br i1 %cmp91.us.us, label %for.inc.lr.ph.us.us, label %for.cond2.loopexit.us.us
 
@@ -87,7 +91,7 @@ cond.false.us:                                    ; preds = %for.body3.us
 
 cond.end.us:                                      ; preds = %cond.false.us, %for.body3.us
   %cond.us = phi i32 [ %div, %cond.false.us ], [ %conv7, %for.body3.us ]
-  %6 = load i32* @b, align 4
+  %6 = load i32, i32* @b, align 4
   %cmp91.us = icmp slt i32 %6, 1
   br i1 %cmp91.us, label %for.inc.lr.ph.us, label %for.cond2.loopexit.us
 
@@ -133,7 +137,7 @@ cond.false.us4:                                   ; preds = %for.body3.us3
 
 cond.end.us5:                                     ; preds = %cond.false.us4, %for.body3.us3
   %cond.us6 = phi i32 [ %div, %cond.false.us4 ], [ %conv7, %for.body3.us3 ]
-  %8 = load i32* @b, align 4
+  %8 = load i32, i32* @b, align 4
   %cmp91.us7 = icmp slt i32 %8, 1
   br i1 %cmp91.us7, label %for.inc.lr.ph.us12, label %for.cond2.loopexit.us11
 
@@ -177,7 +181,7 @@ cond.false:                                       ; preds = %for.body3
 
 cond.end:                                         ; preds = %cond.false, %for.body3
   %cond = phi i32 [ %div, %cond.false ], [ %conv7, %for.body3 ]
-  %10 = load i32* @b, align 4
+  %10 = load i32, i32* @b, align 4
   %cmp91 = icmp slt i32 %10, 1
   br i1 %cmp91, label %for.inc.lr.ph, label %for.cond2.loopexit
 
@@ -204,8 +208,8 @@ for.cond2.for.inc13_crit_edge:                    ; preds = %for.cond2.for.inc13
   br label %for.inc13
 
 ; CHECK: [[for_inc13]]:
-; CHECK-NEXT: %[[indvars_iv_next]] = add nuw nsw i32 %[[indvars_iv]], 1
-; CHECK-NEXT: %[[exitcond4:.*]] = icmp ne i32 %[[indvars_iv]], -1
+; CHECK-NEXT: %[[indvars_iv_next]] = add nsw i32 %[[indvars_iv]], 1
+; CHECK-NEXT: %[[exitcond4:.*]] = icmp ne i32 %[[indvars_iv_next]], 0
 ; CHECK-NEXT: br i1 %[[exitcond4]], label %[[for_cond2_preheader]], label %[[for_end15:.*]]
 for.inc13:                                        ; preds = %for.cond2.for.inc13_crit_edge, %for.cond2.preheader
   %inc14 = add i8 %storemerge15, 1
diff --git a/test/Transforms/IndVarSimplify/pr22222.ll b/test/Transforms/IndVarSimplify/pr22222.ll
index ccdfe538dfa5..d1f04906ae4a 100644
--- a/test/Transforms/IndVarSimplify/pr22222.ll
+++ b/test/Transforms/IndVarSimplify/pr22222.ll
@@ -9,7 +9,7 @@ declare void @abort() #1
 ; Function Attrs: nounwind ssp uwtable
 define i32 @main() {
 entry:
-  %a.promoted13 = load i32* @a, align 4
+  %a.promoted13 = load i32, i32* @a, align 4
   br label %for.cond1.preheader
 
 for.cond1.preheader:                              ; preds = %entry, %for.end
diff --git a/test/Transforms/IndVarSimplify/preserve-signed-wrap.ll b/test/Transforms/IndVarSimplify/preserve-signed-wrap.ll
index f619e8d127ec..c8d34acb24ae 100644
--- a/test/Transforms/IndVarSimplify/preserve-signed-wrap.ll
+++ b/test/Transforms/IndVarSimplify/preserve-signed-wrap.ll
@@ -4,6 +4,10 @@
 ; sext for the addressing, however it shouldn't eliminate the sext
 ; on the other phi, since that value undergoes signed wrapping.
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+
 define void @foo(i32* nocapture %d, i32 %n) nounwind {
 entry:
 	%0 = icmp sgt i32 %n, 0		; <i1> [#uses=1]
@@ -21,7 +25,7 @@ bb:		; preds = %bb1, %bb.nph
 	%p.01 = phi i8 [ %4, %bb1 ], [ -1, %bb.nph ]		; <i8> [#uses=2]
 	%1 = sext i8 %p.01 to i32		; <i32> [#uses=1]
 	%2 = sext i32 %i.02 to i64		; <i64> [#uses=1]
-	%3 = getelementptr i32* %d, i64 %2		; <i32*> [#uses=1]
+	%3 = getelementptr i32, i32* %d, i64 %2		; <i32*> [#uses=1]
 	store i32 %1, i32* %3, align 4
 	%4 = add i8 %p.01, 1		; <i8> [#uses=1]
 	%5 = add i32 %i.02, 1		; <i32> [#uses=2]
diff --git a/test/Transforms/IndVarSimplify/promote-iv-to-eliminate-casts.ll b/test/Transforms/IndVarSimplify/promote-iv-to-eliminate-casts.ll
index a007ca60b08f..f2afaf42bc92 100644
--- a/test/Transforms/IndVarSimplify/promote-iv-to-eliminate-casts.ll
+++ b/test/Transforms/IndVarSimplify/promote-iv-to-eliminate-casts.ll
@@ -1,5 +1,8 @@
-; RUN: opt < %s -indvars -S > %t
-; RUN: not grep sext %t
+; RUN: opt < %s -indvars -S | not grep sext
+
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
 
 define i64 @test(i64* nocapture %first, i32 %count) nounwind readonly {
 entry:
@@ -13,8 +16,8 @@ bb:		; preds = %bb1, %bb.nph
 	%result.02 = phi i64 [ %t5, %bb1 ], [ 0, %bb.nph ]		; <i64> [#uses=1]
 	%n.01 = phi i32 [ %t6, %bb1 ], [ 0, %bb.nph ]		; <i32> [#uses=2]
 	%t1 = sext i32 %n.01 to i64		; <i64> [#uses=1]
-	%t2 = getelementptr i64* %first, i64 %t1		; <i64*> [#uses=1]
-	%t3 = load i64* %t2, align 8		; <i64> [#uses=1]
+	%t2 = getelementptr i64, i64* %first, i64 %t1		; <i64*> [#uses=1]
+	%t3 = load i64, i64* %t2, align 8		; <i64> [#uses=1]
 	%t4 = lshr i64 %t3, 4		; <i64> [#uses=1]
 	%t5 = add i64 %t4, %result.02		; <i64> [#uses=2]
 	%t6 = add i32 %n.01, 1		; <i32> [#uses=2]
@@ -44,7 +47,7 @@ bb.nph:		; preds = %entry
 bb:		; preds = %bb1, %bb.nph
 	%i.01 = phi i16 [ %t3, %bb1 ], [ 0, %bb.nph ]		; <i16> [#uses=2]
 	%t1 = sext i16 %i.01 to i64		; <i64> [#uses=1]
-	%t2 = getelementptr i32* %P, i64 %t1		; <i32*> [#uses=1]
+	%t2 = getelementptr i32, i32* %P, i64 %t1		; <i32*> [#uses=1]
 	store i32 123, i32* %t2, align 4
 	%t3 = add i16 %i.01, 1		; <i16> [#uses=2]
 	br label %bb1
@@ -70,7 +73,7 @@ bb:             ; preds = %bb, %bb.thread
   %i.0.reg2mem.0 = phi i8 [ -10, %bb.thread ], [ %tmp7, %bb ]           ; <i8> [#uses=2]
   %tmp12 = sext i8 %i.0.reg2mem.0 to i32                ; <i32> [#uses=1]
   %tmp4 = add i32 %tmp12, 10            ; <i32> [#uses=1]
-  %tmp5 = getelementptr [21 x i32]* %a, i32 0, i32 %tmp4                ; <i32*> [#uses=1]
+  %tmp5 = getelementptr [21 x i32], [21 x i32]* %a, i32 0, i32 %tmp4                ; <i32*> [#uses=1]
   store i32 0, i32* %tmp5
   %tmp7 = add i8 %i.0.reg2mem.0, 1              ; <i8> [#uses=2]
   %0 = icmp sgt i8 %tmp7, 10            ; <i1> [#uses=1]
@@ -88,7 +91,7 @@ bb:             ; preds = %bb, %bb.thread
   %i.0.reg2mem.0 = phi i8 [ 10, %bb.thread ], [ %tmp7, %bb ]            ; <i8> [#uses=2]
   %tmp12 = sext i8 %i.0.reg2mem.0 to i32                ; <i32> [#uses=1]
   %tmp4 = add i32 %tmp12, -10           ; <i32> [#uses=1]
-  %tmp5 = getelementptr [21 x i32]* %a, i32 0, i32 %tmp4                ; <i32*> [#uses=1]
+  %tmp5 = getelementptr [21 x i32], [21 x i32]* %a, i32 0, i32 %tmp4                ; <i32*> [#uses=1]
   store i32 0, i32* %tmp5
   %tmp7 = add i8 %i.0.reg2mem.0, 1              ; <i8> [#uses=2]
   %0 = icmp sgt i8 %tmp7, 30            ; <i1> [#uses=1]
diff --git a/test/Transforms/IndVarSimplify/sharpen-range.ll b/test/Transforms/IndVarSimplify/sharpen-range.ll
index 5392dbc5fc04..c103da9cec70 100644
--- a/test/Transforms/IndVarSimplify/sharpen-range.ll
+++ b/test/Transforms/IndVarSimplify/sharpen-range.ll
@@ -8,7 +8,7 @@ declare void @abort()
 define i1 @bounded_below_slt(i32* nocapture readonly %buffer) {
 ; CHECK-LABEL: bounded_below_slt
 entry:
-  %length = load i32* %buffer, !range !0
+  %length = load i32, i32* %buffer, !range !0
   %entry.pred = icmp eq i32 %length, 0
   br i1 %entry.pred, label %abort, label %loop.preheader
 
@@ -42,7 +42,7 @@ oob:
 define i1 @bounded_below_sle(i32* nocapture readonly %buffer) {
 ; CHECK-LABEL: bounded_below_sle
 entry:
-  %length = load i32* %buffer, !range !0
+  %length = load i32, i32* %buffer, !range !0
   %entry.pred = icmp eq i32 %length, 0
   br i1 %entry.pred, label %abort, label %loop.preheader
 
@@ -92,7 +92,7 @@ loop.begin:
 loop:
 ; CHECK: loop
   %.sum = add i64 %i.01, -2
-  %v = getelementptr inbounds i8* null, i64 %.sum
+  %v = getelementptr inbounds i8, i8* null, i64 %.sum
   %r = tail call i32 @check(i8* %v)
   %c = icmp eq i32 %r, 0
   br i1 %c, label %loop.end, label %abort.now
diff --git a/test/Transforms/IndVarSimplify/signed-trip-count.ll b/test/Transforms/IndVarSimplify/signed-trip-count.ll
index 1a5e64ddc1b9..992e22e2a969 100644
--- a/test/Transforms/IndVarSimplify/signed-trip-count.ll
+++ b/test/Transforms/IndVarSimplify/signed-trip-count.ll
@@ -2,6 +2,10 @@
 ; RUN: not grep sext %t
 ; RUN: grep phi %t | count 1
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+
 define void @foo(i64* nocapture %x, i32 %n) nounwind {
 entry:
 	%tmp102 = icmp sgt i32 %n, 0		; <i1> [#uses=1]
@@ -13,7 +17,7 @@ bb.nph:		; preds = %entry
 bb:		; preds = %bb7, %bb.nph
 	%i.01 = phi i32 [ %tmp6, %bb7 ], [ 0, %bb.nph ]		; <i32> [#uses=3]
 	%tmp1 = sext i32 %i.01 to i64		; <i64> [#uses=1]
-	%tmp4 = getelementptr i64* %x, i32 %i.01		; <i64*> [#uses=1]
+	%tmp4 = getelementptr i64, i64* %x, i32 %i.01		; <i64*> [#uses=1]
 	store i64 %tmp1, i64* %tmp4, align 8
 	%tmp6 = add i32 %i.01, 1		; <i32> [#uses=2]
 	br label %bb7
diff --git a/test/Transforms/IndVarSimplify/single-element-range.ll b/test/Transforms/IndVarSimplify/single-element-range.ll
index 4b035eea1491..e047a0b254e1 100644
--- a/test/Transforms/IndVarSimplify/single-element-range.ll
+++ b/test/Transforms/IndVarSimplify/single-element-range.ll
@@ -8,7 +8,7 @@ entry:
 	br i1 undef, label %return, label %bb
 
 bb:		; preds = %entry
-	%0 = load i8** undef, align 4		; <i8*> [#uses=2]
+	%0 = load i8*, i8** undef, align 4		; <i8*> [#uses=2]
 	%1 = ptrtoint i8* %0 to i32		; <i32> [#uses=1]
 	%2 = icmp sgt i8* %0, inttoptr (i32 1 to i8*)		; <i1> [#uses=1]
 	br i1 %2, label %bb1, label %bb5
diff --git a/test/Transforms/IndVarSimplify/sink-alloca.ll b/test/Transforms/IndVarSimplify/sink-alloca.ll
index 64207d823d2c..38c2d3140de6 100644
--- a/test/Transforms/IndVarSimplify/sink-alloca.ll
+++ b/test/Transforms/IndVarSimplify/sink-alloca.ll
@@ -19,7 +19,7 @@ while.cond:                                       ; preds = %while.cond, %entry
 
 while.end:                                        ; preds = %while.cond
   store volatile i32 0, i32* %result.i
-  %tmp.i = load volatile i32* %result.i           ; <i32> [#uses=0]
+  %tmp.i = load volatile i32, i32* %result.i           ; <i32> [#uses=0]
   ret i32 0
 }
 declare i32 @bar()
@@ -42,8 +42,8 @@ entry:
 
 for.body.i:
   %indvars.iv37.i = phi i64 [ %indvars.iv.next38.i, %for.body.i ], [ 0, %entry ]
-  %call.i = call i8* (...)* @a() nounwind
-  %arrayidx.i = getelementptr inbounds i8** %vla.i, i64 %indvars.iv37.i
+  %call.i = call i8* (...) @a() nounwind
+  %arrayidx.i = getelementptr inbounds i8*, i8** %vla.i, i64 %indvars.iv37.i
   store i8* %call.i, i8** %arrayidx.i, align 8
   %indvars.iv.next38.i = add i64 %indvars.iv37.i, 1
   %exitcond5 = icmp eq i64 %indvars.iv.next38.i, %n
@@ -51,6 +51,6 @@ for.body.i:
 
 g.exit:
   call void @llvm.stackrestore(i8* %savedstack) nounwind
-  %call1 = call i8* (...)* @a(i8** %vla) nounwind
+  %call1 = call i8* (...) @a(i8** %vla) nounwind
   ret void
 }
diff --git a/test/Transforms/IndVarSimplify/udiv.ll b/test/Transforms/IndVarSimplify/udiv.ll
index aee455d08c80..45c703c99dde 100644
--- a/test/Transforms/IndVarSimplify/udiv.ll
+++ b/test/Transforms/IndVarSimplify/udiv.ll
@@ -17,8 +17,8 @@ entry:
   br i1 %cmp, label %cond.true, label %while.cond.preheader
 
 cond.true:                                        ; preds = %entry
-  %arrayidx = getelementptr inbounds i8** %argv, i64 1 ; <i8**> [#uses=1]
-  %tmp2 = load i8** %arrayidx                     ; <i8*> [#uses=1]
+  %arrayidx = getelementptr inbounds i8*, i8** %argv, i64 1 ; <i8**> [#uses=1]
+  %tmp2 = load i8*, i8** %arrayidx                     ; <i8*> [#uses=1]
   %call = tail call i32 @atoi(i8* %tmp2) nounwind readonly ; <i32> [#uses=1]
   br label %while.cond.preheader
 
@@ -59,7 +59,7 @@ bb.nph:                                           ; preds = %for.cond.preheader
 
 for.body:                                         ; preds = %bb.nph, %for.cond
   %i.02 = phi i64 [ 2, %bb.nph ], [ %inc, %for.cond ] ; <i64> [#uses=2]
-  %arrayidx10 = getelementptr inbounds [8193 x i8]* @main.flags, i64 0, i64 %i.02 ; <i8*> [#uses=1]
+  %arrayidx10 = getelementptr inbounds [8193 x i8], [8193 x i8]* @main.flags, i64 0, i64 %i.02 ; <i8*> [#uses=1]
   store i8 1, i8* %arrayidx10
   %inc = add nsw i64 %i.02, 1                     ; <i64> [#uses=2]
   br label %for.cond
@@ -81,8 +81,8 @@ bb.nph16:                                         ; preds = %for.cond12.loopexit
 for.body15:                                       ; preds = %bb.nph16, %for.cond12
   %count.212 = phi i32 [ 0, %bb.nph16 ], [ %count.1, %for.cond12 ] ; <i32> [#uses=2]
   %i.17 = phi i64 [ 2, %bb.nph16 ], [ %inc37, %for.cond12 ] ; <i64> [#uses=4]
-  %arrayidx17 = getelementptr inbounds [8193 x i8]* @main.flags, i64 0, i64 %i.17 ; <i8*> [#uses=1]
-  %tmp18 = load i8* %arrayidx17                   ; <i8> [#uses=1]
+  %arrayidx17 = getelementptr inbounds [8193 x i8], [8193 x i8]* @main.flags, i64 0, i64 %i.17 ; <i8*> [#uses=1]
+  %tmp18 = load i8, i8* %arrayidx17                   ; <i8> [#uses=1]
   %tobool19 = icmp eq i8 %tmp18, 0                ; <i1> [#uses=1]
   br i1 %tobool19, label %for.inc35, label %if.then
 
@@ -103,7 +103,7 @@ bb.nph5:                                          ; preds = %if.then
 
 for.body25:                                       ; preds = %bb.nph5, %for.cond22
   %k.04 = phi i64 [ %add, %bb.nph5 ], [ %add31, %for.cond22 ] ; <i64> [#uses=2]
-  %arrayidx27 = getelementptr inbounds [8193 x i8]* @main.flags, i64 0, i64 %k.04 ; <i8*> [#uses=1]
+  %arrayidx27 = getelementptr inbounds [8193 x i8], [8193 x i8]* @main.flags, i64 0, i64 %k.04 ; <i8*> [#uses=1]
   store i8 0, i8* %arrayidx27
   %add31 = add nsw i64 %k.04, %i.17               ; <i64> [#uses=2]
   br label %for.cond22
@@ -119,7 +119,7 @@ for.inc35:                                        ; preds = %for.body15, %for.en
 
 while.end:                                        ; preds = %while.cond.while.end_crit_edge, %while.cond.preheader
   %count.0.lcssa = phi i32 [ %count.2.lcssa.lcssa, %while.cond.while.end_crit_edge ], [ 0, %while.cond.preheader ] ; <i32> [#uses=1]
-  %call40 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i64 0, i64 0), i32 %count.0.lcssa) nounwind ; <i32> [#uses=0]
+  %call40 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i64 0, i64 0), i32 %count.0.lcssa) nounwind ; <i32> [#uses=0]
   ret i32 0
 }
 
@@ -146,7 +146,7 @@ for.body.preheader:                               ; preds = %entry
 
 for.body:                                         ; preds = %for.body.preheader, %for.body
   %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] ; <i64> [#uses=2]
-  %arrayidx = getelementptr inbounds double* %p, i64 %i.03 ; <double*> [#uses=1]
+  %arrayidx = getelementptr inbounds double, double* %p, i64 %i.03 ; <double*> [#uses=1]
   store double 0.000000e+00, double* %arrayidx
   %inc = add i64 %i.03, 1                         ; <i64> [#uses=2]
   %divx = udiv i64 %n, 7                           ; <i64> [#uses=1]
diff --git a/test/Transforms/IndVarSimplify/uglygep.ll b/test/Transforms/IndVarSimplify/uglygep.ll
index 0014b683db4b..e4343891be65 100644
--- a/test/Transforms/IndVarSimplify/uglygep.ll
+++ b/test/Transforms/IndVarSimplify/uglygep.ll
@@ -27,10 +27,10 @@ bb2:                                              ; preds = %bb1, %bb
   br i1 %tmp8, label %bb1, label %bb3
 
 bb1:                                              ; preds = %bb2
-  %tmp = load double*** @tds, align 8             ; <double**> [#uses=1]
+  %tmp = load double**, double*** @tds, align 8             ; <double**> [#uses=1]
   %tmp1 = sext i32 %i.0 to i64                    ; <i64> [#uses=1]
-  %tmp2 = getelementptr inbounds double** %tmp, i64 %tmp1 ; <double**> [#uses=1]
-  %tmp3 = load double** %tmp2, align 1            ; <double*> [#uses=1]
+  %tmp2 = getelementptr inbounds double*, double** %tmp, i64 %tmp1 ; <double**> [#uses=1]
+  %tmp3 = load double*, double** %tmp2, align 1            ; <double*> [#uses=1]
   %tmp6 = add nsw i32 %j.0, 1                     ; <i32> [#uses=1]
   br label %bb2
 
diff --git a/test/Transforms/IndVarSimplify/ult-sub-to-eq.ll b/test/Transforms/IndVarSimplify/ult-sub-to-eq.ll
index a421003aa30d..7272ef1ec135 100644
--- a/test/Transforms/IndVarSimplify/ult-sub-to-eq.ll
+++ b/test/Transforms/IndVarSimplify/ult-sub-to-eq.ll
@@ -1,5 +1,9 @@
 ; RUN: opt -S -indvars < %s | FileCheck %s
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+
 define void @test1(float* nocapture %autoc, float* nocapture %data, float %d, i32 %data_len, i32 %sample) nounwind {
 entry:
   %sub = sub i32 %data_len, %sample
@@ -11,11 +15,11 @@ for.body:                                         ; preds = %entry, %for.body
   %0 = trunc i64 %indvars.iv to i32
   %add = add i32 %0, %sample
   %idxprom = zext i32 %add to i64
-  %arrayidx = getelementptr inbounds float* %data, i64 %idxprom
-  %1 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %data, i64 %idxprom
+  %1 = load float, float* %arrayidx, align 4
   %mul = fmul float %1, %d
-  %arrayidx2 = getelementptr inbounds float* %autoc, i64 %indvars.iv
-  %2 = load float* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %autoc, i64 %indvars.iv
+  %2 = load float, float* %arrayidx2, align 4
   %add3 = fadd float %2, %mul
   store float %add3, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/IndVarSimplify/use-range-metadata.ll b/test/Transforms/IndVarSimplify/use-range-metadata.ll
index ea3b12dac391..1f0142608b5d 100644
--- a/test/Transforms/IndVarSimplify/use-range-metadata.ll
+++ b/test/Transforms/IndVarSimplify/use-range-metadata.ll
@@ -6,7 +6,7 @@ declare void @abort()
 
 define i1 @iterate(i32* nocapture readonly %buffer) {
 entry:
-  %length = load i32* %buffer, !range !0
+  %length = load i32, i32* %buffer, !range !0
   br label %loop.preheader
 
 loop.preheader:
diff --git a/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll b/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll
index fb9ef22549c0..5fa4a17b9159 100644
--- a/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll
+++ b/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll
@@ -6,17 +6,17 @@
 
 define void @vnum_test8(i32* %data) {
 entry:
-        %tmp.1 = getelementptr i32* %data, i32 3                ; <i32*> [#uses=1]
-        %tmp.2 = load i32* %tmp.1               ; <i32> [#uses=2]
-        %tmp.4 = getelementptr i32* %data, i32 4                ; <i32*> [#uses=1]
-        %tmp.5 = load i32* %tmp.4               ; <i32> [#uses=2]
-        %tmp.8 = getelementptr i32* %data, i32 2                ; <i32*> [#uses=1]
-        %tmp.9 = load i32* %tmp.8               ; <i32> [#uses=3]
+        %tmp.1 = getelementptr i32, i32* %data, i32 3                ; <i32*> [#uses=1]
+        %tmp.2 = load i32, i32* %tmp.1               ; <i32> [#uses=2]
+        %tmp.4 = getelementptr i32, i32* %data, i32 4                ; <i32*> [#uses=1]
+        %tmp.5 = load i32, i32* %tmp.4               ; <i32> [#uses=2]
+        %tmp.8 = getelementptr i32, i32* %data, i32 2                ; <i32*> [#uses=1]
+        %tmp.9 = load i32, i32* %tmp.8               ; <i32> [#uses=3]
         %tmp.125 = icmp sgt i32 %tmp.2, 0               ; <i1> [#uses=1]
         br i1 %tmp.125, label %no_exit.preheader, label %return
 
 no_exit.preheader:              ; preds = %entry
-        %tmp.16 = getelementptr i32* %data, i32 %tmp.9          ; <i32*> [#uses=1]
+        %tmp.16 = getelementptr i32, i32* %data, i32 %tmp.9          ; <i32*> [#uses=1]
         br label %no_exit
 
 ; CHECK: store i32 0
diff --git a/test/Transforms/IndVarSimplify/verify-scev.ll b/test/Transforms/IndVarSimplify/verify-scev.ll
index b9ce3d63ec99..ddf2e7f1e144 100644
--- a/test/Transforms/IndVarSimplify/verify-scev.ll
+++ b/test/Transforms/IndVarSimplify/verify-scev.ll
@@ -175,7 +175,7 @@ if.end250:                                        ; preds = %for.cond246
   br i1 undef, label %if.end256, label %for.end562
 
 if.end256:                                        ; preds = %if.end250
-  %0 = load i32* undef, align 4
+  %0 = load i32, i32* undef, align 4
   br i1 undef, label %if.then274, label %for.cond404.preheader
 
 for.cond404.preheader:                            ; preds = %if.end256
@@ -379,7 +379,7 @@ for.body48:                                       ; preds = %for.inc221, %for.bo
   br i1 undef, label %for.inc221, label %for.body65.lr.ph
 
 for.body65.lr.ph:                                 ; preds = %for.body48
-  %0 = load i32* undef, align 4
+  %0 = load i32, i32* undef, align 4
   %1 = sext i32 %0 to i64
   br label %for.body65.us
 
diff --git a/test/Transforms/IndVarSimplify/widen-loop-comp.ll b/test/Transforms/IndVarSimplify/widen-loop-comp.ll
index 0930a0c41390..eb81ceb700b0 100644
--- a/test/Transforms/IndVarSimplify/widen-loop-comp.ll
+++ b/test/Transforms/IndVarSimplify/widen-loop-comp.ll
@@ -1,6 +1,10 @@
 ; RUN: opt < %s -indvars -S | FileCheck %s
 target triple = "aarch64--linux-gnu"
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+
 ; Check the loop exit i32 compare instruction and operand are widened to i64
 ; instead of truncating IV before its use in the i32 compare instruction.
 
@@ -19,13 +23,13 @@ target triple = "aarch64--linux-gnu"
 define i32 @test1() {
 entry:
   store i32 -1, i32* @idx, align 4
-  %0 = load i32* @e, align 4
+  %0 = load i32, i32* @e, align 4
   %cmp4 = icmp slt i32 %0, 0
   br i1 %cmp4, label %for.end.loopexit, label %for.body.lr.ph
 
 for.body.lr.ph:
-  %1 = load i32** @ptr, align 8
-  %2 = load i32* @e, align 4
+  %1 = load i32*, i32** @ptr, align 8
+  %2 = load i32, i32* @e, align 4
   br label %for.body
 
 for.cond:
@@ -36,8 +40,8 @@ for.cond:
 for.body:
   %i.05 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.cond ]
   %idxprom = sext i32 %i.05 to i64
-  %arrayidx = getelementptr inbounds i32* %1, i64 %idxprom
-  %3 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %1, i64 %idxprom
+  %3 = load i32, i32* %arrayidx, align 4
   %tobool = icmp eq i32 %3, 0
   br i1 %tobool, label %if.then, label %for.cond
 
@@ -53,7 +57,7 @@ for.end.loopexit:
   br label %for.end
 
 for.end:
-  %4 = load i32* @idx, align 4
+  %4 = load i32, i32* @idx, align 4
   ret i32 %4
 }
 
@@ -81,11 +85,11 @@ for.inc13.us:
 for.body4.us:
   %storemerge14.us = phi i32 [ 0, %for.body4.lr.ph.us ], [ %inc.us, %for.body4.us ]
   %idxprom.us = sext i32 %storemerge14.us to i64
-  %arrayidx6.us = getelementptr inbounds [8 x i8]* %a, i64 %idxprom5.us, i64 %idxprom.us
-  %0 = load i8* %arrayidx6.us, align 1
+  %arrayidx6.us = getelementptr inbounds [8 x i8], [8 x i8]* %a, i64 %idxprom5.us, i64 %idxprom.us
+  %0 = load i8, i8* %arrayidx6.us, align 1
   %idxprom7.us = zext i8 %0 to i64
-  %arrayidx8.us = getelementptr inbounds i8* %b, i64 %idxprom7.us
-  %1 = load i8* %arrayidx8.us, align 1
+  %arrayidx8.us = getelementptr inbounds i8, i8* %b, i64 %idxprom7.us
+  %1 = load i8, i8* %arrayidx8.us, align 1
   store i8 %1, i8* %arrayidx6.us, align 1
   %inc.us = add nsw i32 %storemerge14.us, 1
   %cmp2.us = icmp slt i32 %inc.us, %conv
@@ -126,8 +130,8 @@ for.cond:
 
 for.body:
   %idxprom = sext i32 %i.0 to i64
-  %arrayidx = getelementptr inbounds i32* %a, i64 %idxprom
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %idxprom
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %sum.0, %0
   %inc = add nsw i32 %i.0, 1
   br label %for.cond
@@ -180,8 +184,8 @@ for.cond:
 
 for.body:
   %idxprom = zext i32 %i.0 to i64
-  %arrayidx = getelementptr inbounds i32* %a, i64 %idxprom
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %idxprom
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %sum.0, %0
   %inc = add nsw i32 %i.0, 1
   br label %for.cond
diff --git a/test/Transforms/IndVarSimplify/widen-nsw.ll b/test/Transforms/IndVarSimplify/widen-nsw.ll
index 56c3c0d9f128..8dbbb51ee51d 100644
--- a/test/Transforms/IndVarSimplify/widen-nsw.ll
+++ b/test/Transforms/IndVarSimplify/widen-nsw.ll
@@ -16,8 +16,8 @@ for.cond:                                         ; preds = %for.body, %entry
 
 for.body:                                         ; preds = %for.cond
   %idxprom = sext i32 %i.0 to i64
-  %arrayidx = getelementptr inbounds i32* %a, i64 %idxprom
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %idxprom
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %sum.0, %0
   %inc = add nsw i32 %i.0, 1
   br label %for.cond
diff --git a/test/Transforms/Inline/2003-09-22-PHINodeInlineFail.ll b/test/Transforms/Inline/2003-09-22-PHINodeInlineFail.ll
index b8ca56050dca..df0b472bb2a5 100644
--- a/test/Transforms/Inline/2003-09-22-PHINodeInlineFail.ll
+++ b/test/Transforms/Inline/2003-09-22-PHINodeInlineFail.ll
@@ -9,7 +9,7 @@ LongJmpBlkPost:
         ret i32 0
 
 LongJmpBlkPre:
-        %i.3 = phi i32 [ 0, %entry ], [ 0, %entry ]             ; <i32> [#uses=0]
+        %i.3 = phi i32 [ 0, %entry ]
         %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
                  cleanup
         ret i32 0
diff --git a/test/Transforms/Inline/2003-09-22-PHINodesInExceptionDest.ll b/test/Transforms/Inline/2003-09-22-PHINodesInExceptionDest.ll
index 9af93325f142..d5416a205979 100644
--- a/test/Transforms/Inline/2003-09-22-PHINodesInExceptionDest.ll
+++ b/test/Transforms/Inline/2003-09-22-PHINodesInExceptionDest.ll
@@ -9,7 +9,7 @@ Call2Invoke:            ; preds = %entry
         br label %exit
 
 LongJmpBlkPre:          ; preds = %Call2Invoke, %entry
-        %i.3 = phi i32 [ 0, %entry ], [ 0, %Call2Invoke ]               ; <i32> [#uses=0]
+        %i.3 = phi i32 [ 0, %entry ]
         %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
                  cleanup
         br label %exit
diff --git a/test/Transforms/Inline/2006-07-12-InlinePruneCGUpdate.ll b/test/Transforms/Inline/2006-07-12-InlinePruneCGUpdate.ll
index 69345627221b..a0ddacdbd5b1 100644
--- a/test/Transforms/Inline/2006-07-12-InlinePruneCGUpdate.ll
+++ b/test/Transforms/Inline/2006-07-12-InlinePruneCGUpdate.ll
@@ -214,7 +214,7 @@ bb:		; preds = %cond_true
 	br label %bb3
 
 bb3:		; preds = %bb, %entry
-	%tmp5 = load i8** null		; <i8*> [#uses=1]
+	%tmp5 = load i8*, i8** null		; <i8*> [#uses=1]
 	%tmp = icmp ne i8* null, %tmp5		; <i1> [#uses=1]
 	br i1 %tmp, label %cond_true, label %cond_false
 
diff --git a/test/Transforms/Inline/2009-01-08-NoInlineDynamicAlloca.ll b/test/Transforms/Inline/2009-01-08-NoInlineDynamicAlloca.ll
index db2a799225b9..1bfb55144f5f 100644
--- a/test/Transforms/Inline/2009-01-08-NoInlineDynamicAlloca.ll
+++ b/test/Transforms/Inline/2009-01-08-NoInlineDynamicAlloca.ll
@@ -10,15 +10,15 @@ entry:
 	%p = alloca i8*		; <i8**> [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store i32 %i, i32* %i_addr
-	%0 = load i32* %i_addr, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* %i_addr, align 4		; <i32> [#uses=1]
 	%1 = alloca i8, i32 %0		; <i8*> [#uses=1]
 	store i8* %1, i8** %p, align 4
-	%2 = load i8** %p, align 4		; <i8*> [#uses=1]
+	%2 = load i8*, i8** %p, align 4		; <i8*> [#uses=1]
 	store i8* %2, i8** @q, align 4
 	br label %return
 
 return:		; preds = %entry
-	%retval1 = load i8** %retval		; <i8*> [#uses=1]
+	%retval1 = load i8*, i8** %retval		; <i8*> [#uses=1]
 	ret i8* %retval1
 }
 
@@ -27,7 +27,7 @@ entry:
 	%i_addr = alloca i32		; <i32*> [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store i32 %i, i32* %i_addr
-	%0 = load i32* %i_addr, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* %i_addr, align 4		; <i32> [#uses=1]
 	%1 = call i8* @a(i32 %0) nounwind		; <i8*> [#uses=0]
 	br label %return
 
diff --git a/test/Transforms/Inline/2009-01-13-RecursiveInlineCrash.ll b/test/Transforms/Inline/2009-01-13-RecursiveInlineCrash.ll
index 7d8d16bacffe..8d8f20feb739 100644
--- a/test/Transforms/Inline/2009-01-13-RecursiveInlineCrash.ll
+++ b/test/Transforms/Inline/2009-01-13-RecursiveInlineCrash.ll
@@ -75,23 +75,23 @@ entry:
 	]
 
 bb:		; preds = %entry
-	%0 = getelementptr %struct.quad_struct* %tree, i32 0, i32 3		; <%struct.quad_struct**> [#uses=1]
-	%1 = load %struct.quad_struct** %0, align 4		; <%struct.quad_struct*> [#uses=1]
+	%0 = getelementptr %struct.quad_struct, %struct.quad_struct* %tree, i32 0, i32 3		; <%struct.quad_struct**> [#uses=1]
+	%1 = load %struct.quad_struct*, %struct.quad_struct** %0, align 4		; <%struct.quad_struct*> [#uses=1]
 	ret %struct.quad_struct* %1
 
 bb1:		; preds = %entry
-	%2 = getelementptr %struct.quad_struct* %tree, i32 0, i32 2		; <%struct.quad_struct**> [#uses=1]
-	%3 = load %struct.quad_struct** %2, align 4		; <%struct.quad_struct*> [#uses=1]
+	%2 = getelementptr %struct.quad_struct, %struct.quad_struct* %tree, i32 0, i32 2		; <%struct.quad_struct**> [#uses=1]
+	%3 = load %struct.quad_struct*, %struct.quad_struct** %2, align 4		; <%struct.quad_struct*> [#uses=1]
 	ret %struct.quad_struct* %3
 
 bb2:		; preds = %entry
-	%4 = getelementptr %struct.quad_struct* %tree, i32 0, i32 5		; <%struct.quad_struct**> [#uses=1]
-	%5 = load %struct.quad_struct** %4, align 4		; <%struct.quad_struct*> [#uses=1]
+	%4 = getelementptr %struct.quad_struct, %struct.quad_struct* %tree, i32 0, i32 5		; <%struct.quad_struct**> [#uses=1]
+	%5 = load %struct.quad_struct*, %struct.quad_struct** %4, align 4		; <%struct.quad_struct*> [#uses=1]
 	ret %struct.quad_struct* %5
 
 bb3:		; preds = %entry
-	%6 = getelementptr %struct.quad_struct* %tree, i32 0, i32 4		; <%struct.quad_struct**> [#uses=1]
-	%7 = load %struct.quad_struct** %6, align 4		; <%struct.quad_struct*> [#uses=1]
+	%6 = getelementptr %struct.quad_struct, %struct.quad_struct* %tree, i32 0, i32 4		; <%struct.quad_struct**> [#uses=1]
+	%7 = load %struct.quad_struct*, %struct.quad_struct** %6, align 4		; <%struct.quad_struct*> [#uses=1]
 	ret %struct.quad_struct* %7
 
 bb5:		; preds = %entry
@@ -100,10 +100,10 @@ bb5:		; preds = %entry
 
 define internal fastcc %struct.quad_struct* @gtequal_adj_neighbor(%struct.quad_struct* nocapture %tree, i32 %d) nounwind readonly {
 entry:
-	%0 = getelementptr %struct.quad_struct* %tree, i32 0, i32 6		; <%struct.quad_struct**> [#uses=1]
-	%1 = load %struct.quad_struct** %0, align 4		; <%struct.quad_struct*> [#uses=4]
-	%2 = getelementptr %struct.quad_struct* %tree, i32 0, i32 1		; <i32*> [#uses=1]
-	%3 = load i32* %2, align 4		; <i32> [#uses=2]
+	%0 = getelementptr %struct.quad_struct, %struct.quad_struct* %tree, i32 0, i32 6		; <%struct.quad_struct**> [#uses=1]
+	%1 = load %struct.quad_struct*, %struct.quad_struct** %0, align 4		; <%struct.quad_struct*> [#uses=4]
+	%2 = getelementptr %struct.quad_struct, %struct.quad_struct* %tree, i32 0, i32 1		; <i32*> [#uses=1]
+	%3 = load i32, i32* %2, align 4		; <i32> [#uses=2]
 	%4 = icmp eq %struct.quad_struct* %1, null		; <i1> [#uses=1]
 	br i1 %4, label %bb3, label %bb
 
@@ -122,8 +122,8 @@ bb3:		; preds = %bb1, %bb, %entry
 	br i1 %8, label %bb7, label %bb4
 
 bb4:		; preds = %bb3
-	%9 = getelementptr %struct.quad_struct* %q.0, i32 0, i32 0		; <i32*> [#uses=1]
-	%10 = load i32* %9, align 4		; <i32> [#uses=1]
+	%9 = getelementptr %struct.quad_struct, %struct.quad_struct* %q.0, i32 0, i32 0		; <i32*> [#uses=1]
+	%10 = load i32, i32* %9, align 4		; <i32> [#uses=1]
 	%11 = icmp eq i32 %10, 2		; <i1> [#uses=1]
 	br i1 %11, label %bb5, label %bb7
 
@@ -140,36 +140,36 @@ declare fastcc i32 @sum_adjacent(%struct.quad_struct* nocapture, i32, i32, i32)
 
 define i32 @perimeter(%struct.quad_struct* nocapture %tree, i32 %size) nounwind readonly {
 entry:
-	%0 = getelementptr %struct.quad_struct* %tree, i32 0, i32 0		; <i32*> [#uses=1]
-	%1 = load i32* %0, align 4		; <i32> [#uses=1]
+	%0 = getelementptr %struct.quad_struct, %struct.quad_struct* %tree, i32 0, i32 0		; <i32*> [#uses=1]
+	%1 = load i32, i32* %0, align 4		; <i32> [#uses=1]
 	%2 = icmp eq i32 %1, 2		; <i1> [#uses=1]
 	br i1 %2, label %bb, label %bb2
 
 bb:		; preds = %entry
-	%3 = getelementptr %struct.quad_struct* %tree, i32 0, i32 4		; <%struct.quad_struct**> [#uses=1]
-	%4 = load %struct.quad_struct** %3, align 4		; <%struct.quad_struct*> [#uses=1]
+	%3 = getelementptr %struct.quad_struct, %struct.quad_struct* %tree, i32 0, i32 4		; <%struct.quad_struct**> [#uses=1]
+	%4 = load %struct.quad_struct*, %struct.quad_struct** %3, align 4		; <%struct.quad_struct*> [#uses=1]
 	%5 = sdiv i32 %size, 2		; <i32> [#uses=1]
 	%6 = call i32 @perimeter(%struct.quad_struct* %4, i32 %5) nounwind		; <i32> [#uses=1]
-	%7 = getelementptr %struct.quad_struct* %tree, i32 0, i32 5		; <%struct.quad_struct**> [#uses=1]
-	%8 = load %struct.quad_struct** %7, align 4		; <%struct.quad_struct*> [#uses=1]
+	%7 = getelementptr %struct.quad_struct, %struct.quad_struct* %tree, i32 0, i32 5		; <%struct.quad_struct**> [#uses=1]
+	%8 = load %struct.quad_struct*, %struct.quad_struct** %7, align 4		; <%struct.quad_struct*> [#uses=1]
 	%9 = sdiv i32 %size, 2		; <i32> [#uses=1]
 	%10 = call i32 @perimeter(%struct.quad_struct* %8, i32 %9) nounwind		; <i32> [#uses=1]
 	%11 = add i32 %10, %6		; <i32> [#uses=1]
-	%12 = getelementptr %struct.quad_struct* %tree, i32 0, i32 3		; <%struct.quad_struct**> [#uses=1]
-	%13 = load %struct.quad_struct** %12, align 4		; <%struct.quad_struct*> [#uses=1]
+	%12 = getelementptr %struct.quad_struct, %struct.quad_struct* %tree, i32 0, i32 3		; <%struct.quad_struct**> [#uses=1]
+	%13 = load %struct.quad_struct*, %struct.quad_struct** %12, align 4		; <%struct.quad_struct*> [#uses=1]
 	%14 = sdiv i32 %size, 2		; <i32> [#uses=1]
 	%15 = call i32 @perimeter(%struct.quad_struct* %13, i32 %14) nounwind		; <i32> [#uses=1]
 	%16 = add i32 %15, %11		; <i32> [#uses=1]
-	%17 = getelementptr %struct.quad_struct* %tree, i32 0, i32 2		; <%struct.quad_struct**> [#uses=1]
-	%18 = load %struct.quad_struct** %17, align 4		; <%struct.quad_struct*> [#uses=1]
+	%17 = getelementptr %struct.quad_struct, %struct.quad_struct* %tree, i32 0, i32 2		; <%struct.quad_struct**> [#uses=1]
+	%18 = load %struct.quad_struct*, %struct.quad_struct** %17, align 4		; <%struct.quad_struct*> [#uses=1]
 	%19 = sdiv i32 %size, 2		; <i32> [#uses=1]
 	%20 = call i32 @perimeter(%struct.quad_struct* %18, i32 %19) nounwind		; <i32> [#uses=1]
 	%21 = add i32 %20, %16		; <i32> [#uses=1]
 	ret i32 %21
 
 bb2:		; preds = %entry
-	%22 = getelementptr %struct.quad_struct* %tree, i32 0, i32 0		; <i32*> [#uses=1]
-	%23 = load i32* %22, align 4		; <i32> [#uses=1]
+	%22 = getelementptr %struct.quad_struct, %struct.quad_struct* %tree, i32 0, i32 0		; <i32*> [#uses=1]
+	%23 = load i32, i32* %22, align 4		; <i32> [#uses=1]
 	%24 = icmp eq i32 %23, 0		; <i1> [#uses=1]
 	br i1 %24, label %bb3, label %bb23
 
@@ -179,14 +179,14 @@ bb3:		; preds = %bb2
 	br i1 %26, label %bb8, label %bb4
 
 bb4:		; preds = %bb3
-	%27 = getelementptr %struct.quad_struct* %25, i32 0, i32 0		; <i32*> [#uses=1]
-	%28 = load i32* %27, align 4		; <i32> [#uses=1]
+	%27 = getelementptr %struct.quad_struct, %struct.quad_struct* %25, i32 0, i32 0		; <i32*> [#uses=1]
+	%28 = load i32, i32* %27, align 4		; <i32> [#uses=1]
 	%29 = icmp eq i32 %28, 1		; <i1> [#uses=1]
 	br i1 %29, label %bb8, label %bb6
 
 bb6:		; preds = %bb4
-	%30 = getelementptr %struct.quad_struct* %25, i32 0, i32 0		; <i32*> [#uses=1]
-	%31 = load i32* %30, align 4		; <i32> [#uses=1]
+	%30 = getelementptr %struct.quad_struct, %struct.quad_struct* %25, i32 0, i32 0		; <i32*> [#uses=1]
+	%31 = load i32, i32* %30, align 4		; <i32> [#uses=1]
 	%32 = icmp eq i32 %31, 2		; <i1> [#uses=1]
 	br i1 %32, label %bb7, label %bb8
 
@@ -201,8 +201,8 @@ bb8:		; preds = %bb7, %bb6, %bb4, %bb3
 	br i1 %35, label %bb10, label %bb9
 
 bb9:		; preds = %bb8
-	%36 = getelementptr %struct.quad_struct* %34, i32 0, i32 0		; <i32*> [#uses=1]
-	%37 = load i32* %36, align 4		; <i32> [#uses=1]
+	%36 = getelementptr %struct.quad_struct, %struct.quad_struct* %34, i32 0, i32 0		; <i32*> [#uses=1]
+	%37 = load i32, i32* %36, align 4		; <i32> [#uses=1]
 	%38 = icmp eq i32 %37, 1		; <i1> [#uses=1]
 	br i1 %38, label %bb10, label %bb11
 
@@ -211,8 +211,8 @@ bb10:		; preds = %bb9, %bb8
 	br label %bb13
 
 bb11:		; preds = %bb9
-	%40 = getelementptr %struct.quad_struct* %34, i32 0, i32 0		; <i32*> [#uses=1]
-	%41 = load i32* %40, align 4		; <i32> [#uses=1]
+	%40 = getelementptr %struct.quad_struct, %struct.quad_struct* %34, i32 0, i32 0		; <i32*> [#uses=1]
+	%41 = load i32, i32* %40, align 4		; <i32> [#uses=1]
 	%42 = icmp eq i32 %41, 2		; <i1> [#uses=1]
 	br i1 %42, label %bb12, label %bb13
 
@@ -228,8 +228,8 @@ bb13:		; preds = %bb12, %bb11, %bb10
 	br i1 %46, label %bb15, label %bb14
 
 bb14:		; preds = %bb13
-	%47 = getelementptr %struct.quad_struct* %45, i32 0, i32 0		; <i32*> [#uses=1]
-	%48 = load i32* %47, align 4		; <i32> [#uses=1]
+	%47 = getelementptr %struct.quad_struct, %struct.quad_struct* %45, i32 0, i32 0		; <i32*> [#uses=1]
+	%48 = load i32, i32* %47, align 4		; <i32> [#uses=1]
 	%49 = icmp eq i32 %48, 1		; <i1> [#uses=1]
 	br i1 %49, label %bb15, label %bb16
 
@@ -238,8 +238,8 @@ bb15:		; preds = %bb14, %bb13
 	br label %bb18
 
 bb16:		; preds = %bb14
-	%51 = getelementptr %struct.quad_struct* %45, i32 0, i32 0		; <i32*> [#uses=1]
-	%52 = load i32* %51, align 4		; <i32> [#uses=1]
+	%51 = getelementptr %struct.quad_struct, %struct.quad_struct* %45, i32 0, i32 0		; <i32*> [#uses=1]
+	%52 = load i32, i32* %51, align 4		; <i32> [#uses=1]
 	%53 = icmp eq i32 %52, 2		; <i1> [#uses=1]
 	br i1 %53, label %bb17, label %bb18
 
@@ -255,8 +255,8 @@ bb18:		; preds = %bb17, %bb16, %bb15
 	br i1 %57, label %bb20, label %bb19
 
 bb19:		; preds = %bb18
-	%58 = getelementptr %struct.quad_struct* %56, i32 0, i32 0		; <i32*> [#uses=1]
-	%59 = load i32* %58, align 4		; <i32> [#uses=1]
+	%58 = getelementptr %struct.quad_struct, %struct.quad_struct* %56, i32 0, i32 0		; <i32*> [#uses=1]
+	%59 = load i32, i32* %58, align 4		; <i32> [#uses=1]
 	%60 = icmp eq i32 %59, 1		; <i1> [#uses=1]
 	br i1 %60, label %bb20, label %bb21
 
@@ -265,8 +265,8 @@ bb20:		; preds = %bb19, %bb18
 	ret i32 %61
 
 bb21:		; preds = %bb19
-	%62 = getelementptr %struct.quad_struct* %56, i32 0, i32 0		; <i32*> [#uses=1]
-	%63 = load i32* %62, align 4		; <i32> [#uses=1]
+	%62 = getelementptr %struct.quad_struct, %struct.quad_struct* %56, i32 0, i32 0		; <i32*> [#uses=1]
+	%63 = load i32, i32* %62, align 4		; <i32> [#uses=1]
 	%64 = icmp eq i32 %63, 2		; <i1> [#uses=1]
 	br i1 %64, label %bb22, label %bb23
 
diff --git a/test/Transforms/Inline/align.ll b/test/Transforms/Inline/align.ll
index 9ac6d54bfba9..c91fe8046174 100644
--- a/test/Transforms/Inline/align.ll
+++ b/test/Transforms/Inline/align.ll
@@ -4,8 +4,8 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define void @hello(float* align 128 nocapture %a, float* nocapture readonly %c) #0 {
 entry:
-  %0 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 5
+  %0 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 5
   store float %0, float* %arrayidx, align 4
   ret void
 }
@@ -13,8 +13,8 @@ entry:
 define void @foo(float* nocapture %a, float* nocapture readonly %c) #0 {
 entry:
   tail call void @hello(float* %a, float* %c)
-  %0 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 7
+  %0 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 7
   store float %0, float* %arrayidx, align 4
   ret void
 }
@@ -25,11 +25,11 @@ entry:
 ; CHECK:   %maskedptr = and i64 %ptrint, 127
 ; CHECK:   %maskcond = icmp eq i64 %maskedptr, 0
 ; CHECK:   call void @llvm.assume(i1 %maskcond)
-; CHECK:   %0 = load float* %c, align 4
-; CHECK:   %arrayidx.i = getelementptr inbounds float* %a, i64 5
+; CHECK:   %0 = load float, float* %c, align 4
+; CHECK:   %arrayidx.i = getelementptr inbounds float, float* %a, i64 5
 ; CHECK:   store float %0, float* %arrayidx.i, align 4
-; CHECK:   %1 = load float* %c, align 4
-; CHECK:   %arrayidx = getelementptr inbounds float* %a, i64 7
+; CHECK:   %1 = load float, float* %c, align 4
+; CHECK:   %arrayidx = getelementptr inbounds float, float* %a, i64 7
 ; CHECK:   store float %1, float* %arrayidx, align 4
 ; CHECK:   ret void
 ; CHECK: }
@@ -37,29 +37,29 @@ entry:
 define void @fooa(float* nocapture align 128 %a, float* nocapture readonly %c) #0 {
 entry:
   tail call void @hello(float* %a, float* %c)
-  %0 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 7
+  %0 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 7
   store float %0, float* %arrayidx, align 4
   ret void
 }
 
 ; CHECK: define void @fooa(float* nocapture align 128 %a, float* nocapture readonly %c) #0 {
 ; CHECK: entry:
-; CHECK:   %0 = load float* %c, align 4
-; CHECK:   %arrayidx.i = getelementptr inbounds float* %a, i64 5
+; CHECK:   %0 = load float, float* %c, align 4
+; CHECK:   %arrayidx.i = getelementptr inbounds float, float* %a, i64 5
 ; CHECK:   store float %0, float* %arrayidx.i, align 4
-; CHECK:   %1 = load float* %c, align 4
-; CHECK:   %arrayidx = getelementptr inbounds float* %a, i64 7
+; CHECK:   %1 = load float, float* %c, align 4
+; CHECK:   %arrayidx = getelementptr inbounds float, float* %a, i64 7
 ; CHECK:   store float %1, float* %arrayidx, align 4
 ; CHECK:   ret void
 ; CHECK: }
 
 define void @hello2(float* align 128 nocapture %a, float* align 128 nocapture %b, float* nocapture readonly %c) #0 {
 entry:
-  %0 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 5
+  %0 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 5
   store float %0, float* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds float* %b, i64 8
+  %arrayidx1 = getelementptr inbounds float, float* %b, i64 8
   store float %0, float* %arrayidx1, align 4
   ret void
 }
@@ -67,8 +67,8 @@ entry:
 define void @foo2(float* nocapture %a, float* nocapture %b, float* nocapture readonly %c) #0 {
 entry:
   tail call void @hello2(float* %a, float* %b, float* %c)
-  %0 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 7
+  %0 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 7
   store float %0, float* %arrayidx, align 4
   ret void
 }
@@ -83,13 +83,13 @@ entry:
 ; CHECK:   %maskedptr2 = and i64 %ptrint1, 127
 ; CHECK:   %maskcond3 = icmp eq i64 %maskedptr2, 0
 ; CHECK:   call void @llvm.assume(i1 %maskcond3)
-; CHECK:   %0 = load float* %c, align 4
-; CHECK:   %arrayidx.i = getelementptr inbounds float* %a, i64 5
+; CHECK:   %0 = load float, float* %c, align 4
+; CHECK:   %arrayidx.i = getelementptr inbounds float, float* %a, i64 5
 ; CHECK:   store float %0, float* %arrayidx.i, align 4
-; CHECK:   %arrayidx1.i = getelementptr inbounds float* %b, i64 8
+; CHECK:   %arrayidx1.i = getelementptr inbounds float, float* %b, i64 8
 ; CHECK:   store float %0, float* %arrayidx1.i, align 4
-; CHECK:   %1 = load float* %c, align 4
-; CHECK:   %arrayidx = getelementptr inbounds float* %a, i64 7
+; CHECK:   %1 = load float, float* %c, align 4
+; CHECK:   %arrayidx = getelementptr inbounds float, float* %a, i64 7
 ; CHECK:   store float %1, float* %arrayidx, align 4
 ; CHECK:   ret void
 ; CHECK: }
diff --git a/test/Transforms/Inline/alloca-bonus.ll b/test/Transforms/Inline/alloca-bonus.ll
index 3c5052b883b2..649fac909fba 100644
--- a/test/Transforms/Inline/alloca-bonus.ll
+++ b/test/Transforms/Inline/alloca-bonus.ll
@@ -15,10 +15,10 @@ define void @outer1() {
 }
 
 define void @inner1(i32 *%ptr) {
-  %A = load i32* %ptr
+  %A = load i32, i32* %ptr
   store i32 0, i32* %ptr
-  %C = getelementptr inbounds i32* %ptr, i32 0
-  %D = getelementptr inbounds i32* %ptr, i32 1
+  %C = getelementptr inbounds i32, i32* %ptr, i32 0
+  %D = getelementptr inbounds i32, i32* %ptr, i32 1
   %E = bitcast i32* %ptr to i8*
   %F = select i1 false, i32* %ptr, i32* @glbl
   call void @llvm.lifetime.start(i64 0, i8* %E)
@@ -35,10 +35,10 @@ define void @outer2() {
 
 ; %D poisons this call, scalar-repl can't handle that instruction.
 define void @inner2(i32 *%ptr) {
-  %A = load i32* %ptr
+  %A = load i32, i32* %ptr
   store i32 0, i32* %ptr
-  %C = getelementptr inbounds i32* %ptr, i32 0
-  %D = getelementptr inbounds i32* %ptr, i32 %A
+  %C = getelementptr inbounds i32, i32* %ptr, i32 0
+  %D = getelementptr inbounds i32, i32* %ptr, i32 %A
   %E = bitcast i32* %ptr to i8*
   %F = select i1 false, i32* %ptr, i32* @glbl
   call void @llvm.lifetime.start(i64 0, i8* %E)
@@ -59,7 +59,7 @@ define void @inner3(i32 *%ptr, i1 %x) {
   br i1 %A, label %bb.true, label %bb.false
 bb.true:
   ; This block musn't be counted in the inline cost.
-  %t1 = load i32* %ptr
+  %t1 = load i32, i32* %ptr
   %t2 = add i32 %t1, 1
   %t3 = add i32 %t2, 1
   %t4 = add i32 %t3, 1
@@ -95,12 +95,12 @@ define void @outer4(i32 %A) {
 ; %B poisons this call, scalar-repl can't handle that instruction. However, we
 ; still want to detect that the icmp and branch *can* be handled.
 define void @inner4(i32 *%ptr, i32 %A) {
-  %B = getelementptr inbounds i32* %ptr, i32 %A
+  %B = getelementptr inbounds i32, i32* %ptr, i32 %A
   %C = icmp eq i32* %ptr, null
   br i1 %C, label %bb.true, label %bb.false
 bb.true:
   ; This block musn't be counted in the inline cost.
-  %t1 = load i32* %ptr
+  %t1 = load i32, i32* %ptr
   %t2 = add i32 %t1, 1
   %t3 = add i32 %t2, 1
   %t4 = add i32 %t3, 1
@@ -137,13 +137,13 @@ define void @outer5() {
 ; the flag is set appropriately, the poisoning instruction is inside of dead
 ; code, and so shouldn't be counted.
 define void @inner5(i1 %flag, i32 *%ptr) {
-  %A = load i32* %ptr
+  %A = load i32, i32* %ptr
   store i32 0, i32* %ptr
-  %C = getelementptr inbounds i32* %ptr, i32 0
+  %C = getelementptr inbounds i32, i32* %ptr, i32 0
   br i1 %flag, label %if.then, label %exit
 
 if.then:
-  %D = getelementptr inbounds i32* %ptr, i32 %A
+  %D = getelementptr inbounds i32, i32* %ptr, i32 %A
   %E = bitcast i32* %ptr to i8*
   %F = select i1 false, i32* %ptr, i32* @glbl
   call void @llvm.lifetime.start(i64 0, i8* %E)
diff --git a/test/Transforms/Inline/alloca-dbgdeclare.ll b/test/Transforms/Inline/alloca-dbgdeclare.ll
new file mode 100644
index 000000000000..286f2931ff22
--- /dev/null
+++ b/test/Transforms/Inline/alloca-dbgdeclare.ll
@@ -0,0 +1,141 @@
+; RUN: opt -inline -S < %s | FileCheck %s
+; struct A {
+;   int arg0;
+;   double arg1[2];
+; } a, b;
+;  
+; void fn3(A p1) {
+;   if (p1.arg0)
+;     a = p1;
+; }
+;  
+; void fn4() { fn3(b); }
+;  
+; void fn5() {
+;   while (1)
+;     fn4();
+; }
+; ModuleID = 'test.cpp'
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-apple-darwin"
+
+%struct.A = type { i32, [2 x double] }
+
+@a = global %struct.A zeroinitializer, align 8
+@b = global %struct.A zeroinitializer, align 8
+
+; Function Attrs: nounwind
+declare void @_Z3fn31A(%struct.A* nocapture readonly %p1) #0
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+; Function Attrs: nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #2
+
+; Function Attrs: nounwind
+define void @_Z3fn4v() #0 {
+entry:
+; Test that the dbg.declare is moved together with the alloca.
+; CHECK: define void @_Z3fn5v()
+; CHECK-NEXT: entry:
+; CHECK-NEXT:   %agg.tmp.sroa.3.i = alloca [20 x i8], align 4
+; CHECK-NEXT:   call void @llvm.dbg.declare(metadata [20 x i8]* %agg.tmp.sroa.3.i,
+  %agg.tmp.sroa.3 = alloca [20 x i8], align 4
+  tail call void @llvm.dbg.declare(metadata [20 x i8]* %agg.tmp.sroa.3, metadata !46, metadata !48), !dbg !49
+  %agg.tmp.sroa.0.0.copyload = load i32, i32* getelementptr inbounds (%struct.A, %struct.A* @b, i64 0, i32 0), align 8, !dbg !50
+  tail call void @llvm.dbg.value(metadata i32 %agg.tmp.sroa.0.0.copyload, i64 0, metadata !46, metadata !51), !dbg !49
+  %agg.tmp.sroa.3.0..sroa_idx = getelementptr inbounds [20 x i8], [20 x i8]* %agg.tmp.sroa.3, i64 0, i64 0, !dbg !50
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %agg.tmp.sroa.3.0..sroa_idx, i8* getelementptr (i8, i8* bitcast (%struct.A* @b to i8*), i64 4), i64 20, i32 4, i1 false), !dbg !50
+  tail call void @llvm.dbg.declare(metadata %struct.A* undef, metadata !46, metadata !31) #2, !dbg !49
+  %tobool.i = icmp eq i32 %agg.tmp.sroa.0.0.copyload, 0, !dbg !52
+  br i1 %tobool.i, label %_Z3fn31A.exit, label %if.then.i, !dbg !53
+
+if.then.i:                                        ; preds = %entry
+  store i32 %agg.tmp.sroa.0.0.copyload, i32* getelementptr inbounds (%struct.A, %struct.A* @a, i64 0, i32 0), align 8, !dbg !54
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr (i8, i8* bitcast (%struct.A* @a to i8*), i64 4), i8* %agg.tmp.sroa.3.0..sroa_idx, i64 20, i32 4, i1 false), !dbg !54
+  br label %_Z3fn31A.exit, !dbg !54
+
+_Z3fn31A.exit:                                    ; preds = %entry, %if.then.i
+  ret void, !dbg !50
+}
+
+; Function Attrs: noreturn nounwind
+define void @_Z3fn5v() #3 {
+entry:
+  br label %while.body, !dbg !55
+
+while.body:                                       ; preds = %entry, %while.body
+  call void @_Z3fn4v(), !dbg !56
+  br label %while.body, !dbg !55
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind }
+attributes #3 = { noreturn nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!28, !29}
+!llvm.ident = !{!30}
+
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.7.0 (trunk 227480) (llvm/trunk 227517)", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !3, subprograms: !14, globals: !25, imports: !2)
+!1 = !DIFile(filename: "<stdin>", directory: "")
+!2 = !{}
+!3 = !{!4}
+!4 = !DICompositeType(tag: DW_TAG_structure_type, name: "A", line: 1, size: 192, align: 64, file: !5, elements: !6, identifier: "_ZTS1A")
+!5 = !DIFile(filename: "test.cpp", directory: "")
+!6 = !{!7, !9}
+!7 = !DIDerivedType(tag: DW_TAG_member, name: "arg0", line: 2, size: 32, align: 32, file: !5, scope: !"_ZTS1A", baseType: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_member, name: "arg1", line: 3, size: 128, align: 64, offset: 64, file: !5, scope: !"_ZTS1A", baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_array_type, size: 128, align: 64, baseType: !11, elements: !12)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 64, encoding: DW_ATE_float)
+!12 = !{!13}
+!13 = !DISubrange(count: 2)
+!14 = !{!15, !21, !24}
+!15 = !DISubprogram(name: "fn3", linkageName: "_Z3fn31A", line: 6, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 6, file: !5, scope: !16, type: !17, function: void (%struct.A*)* @_Z3fn31A, variables: !19)
+!16 = !DIFile(filename: "test.cpp", directory: "")
+!17 = !DISubroutineType(types: !18)
+!18 = !{null, !"_ZTS1A"}
+!19 = !{!20}
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p1", line: 6, arg: 1, scope: !15, file: !16, type: !"_ZTS1A")
+!21 = !DISubprogram(name: "fn4", linkageName: "_Z3fn4v", line: 11, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !5, scope: !16, type: !22, function: void ()* @_Z3fn4v, variables: !2)
+!22 = !DISubroutineType(types: !23)
+!23 = !{null}
+!24 = !DISubprogram(name: "fn5", linkageName: "_Z3fn5v", line: 13, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 13, file: !5, scope: !16, type: !22, function: void ()* @_Z3fn5v, variables: !2)
+!25 = !{!26, !27}
+!26 = !DIGlobalVariable(name: "a", line: 4, isLocal: false, isDefinition: true, scope: null, file: !16, type: !"_ZTS1A", variable: %struct.A* @a)
+!27 = !DIGlobalVariable(name: "b", line: 4, isLocal: false, isDefinition: true, scope: null, file: !16, type: !"_ZTS1A", variable: %struct.A* @b)
+!28 = !{i32 2, !"Dwarf Version", i32 4}
+!29 = !{i32 2, !"Debug Info Version", i32 3}
+!30 = !{!"clang version 3.7.0 (trunk 227480) (llvm/trunk 227517)"}
+!31 = !DIExpression(DW_OP_deref)
+!32 = !DILocation(line: 6, scope: !15)
+!33 = !DILocation(line: 7, scope: !34)
+!34 = distinct !DILexicalBlock(line: 7, column: 0, file: !5, scope: !15)
+!35 = !{!36, !37, i64 0}
+!36 = !{!"_ZTS1A", !37, i64 0, !38, i64 8}
+!37 = !{!"int", !38, i64 0}
+!38 = !{!"omnipotent char", !39, i64 0}
+!39 = !{!"Simple C/C++ TBAA"}
+!40 = !DILocation(line: 7, scope: !15)
+!41 = !DILocation(line: 8, scope: !34)
+!42 = !{i64 0, i64 4, !43, i64 8, i64 16, !44}
+!43 = !{!37, !37, i64 0}
+!44 = !{!38, !38, i64 0}
+!45 = !DILocation(line: 9, scope: !15)
+!46 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p1", line: 6, arg: 1, scope: !15, file: !16, type: !"_ZTS1A")
+!47 = distinct !DILocation(line: 11, scope: !21)
+!48 = !DIExpression(DW_OP_bit_piece, 32, 160)
+!49 = !DILocation(line: 6, scope: !15, inlinedAt: !47)
+!50 = !DILocation(line: 11, scope: !21)
+!51 = !DIExpression(DW_OP_bit_piece, 0, 32)
+!52 = !DILocation(line: 7, scope: !34, inlinedAt: !47)
+!53 = !DILocation(line: 7, scope: !15, inlinedAt: !47)
+!54 = !DILocation(line: 8, scope: !34, inlinedAt: !47)
+!55 = !DILocation(line: 14, scope: !24)
+!56 = !DILocation(line: 15, scope: !24)
diff --git a/test/Transforms/Inline/alloca-in-scc.ll b/test/Transforms/Inline/alloca-in-scc.ll
index d539255e6e0a..92649a6e0734 100644
--- a/test/Transforms/Inline/alloca-in-scc.ll
+++ b/test/Transforms/Inline/alloca-in-scc.ll
@@ -12,7 +12,7 @@ entry:
 define internal fastcc void @a() nounwind ssp {
 entry:
   %al = alloca [3 x i32], align 4
-  %0 = getelementptr inbounds [3 x i32]* %al, i32 0, i32 2 
+  %0 = getelementptr inbounds [3 x i32], [3 x i32]* %al, i32 0, i32 2 
   
   call fastcc void @c() nounwind
   unreachable
diff --git a/test/Transforms/Inline/alloca-merge-align-nodl.ll b/test/Transforms/Inline/alloca-merge-align-nodl.ll
deleted file mode 100644
index 301505ff7910..000000000000
--- a/test/Transforms/Inline/alloca-merge-align-nodl.ll
+++ /dev/null
@@ -1,88 +0,0 @@
-; RUN: opt < %s -inline -S | FileCheck %s
-; This variant of the test has no data layout information.
-target triple = "powerpc64-unknown-linux-gnu"
-
-%struct.s = type { i32, i32 }
-
-define void @foo(%struct.s* byval nocapture readonly %a) {
-entry:
-  %x = alloca [2 x i32], align 4
-  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
-  %0 = load i32* %a1, align 4
-  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
-  store i32 %0, i32* %arrayidx, align 4
-  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
-  %1 = load i32* %b, align 4
-  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
-  store i32 %1, i32* %arrayidx2, align 4
-  call void @bar(i32* %arrayidx) #2
-  ret void
-}
-
-define void @foo0(%struct.s* byval nocapture readonly %a) {
-entry:
-  %x = alloca [2 x i32]
-  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
-  %0 = load i32* %a1, align 4
-  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
-  store i32 %0, i32* %arrayidx, align 4
-  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
-  %1 = load i32* %b, align 4
-  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
-  store i32 %1, i32* %arrayidx2, align 4
-  call void @bar(i32* %arrayidx) #2
-  ret void
-}
-
-declare void @bar(i32*) #1
-
-define void @goo(%struct.s* byval nocapture readonly %a) {
-entry:
-  %x = alloca [2 x i32], align 32
-  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
-  %0 = load i32* %a1, align 4
-  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
-  store i32 %0, i32* %arrayidx, align 32
-  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
-  %1 = load i32* %b, align 4
-  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
-  store i32 %1, i32* %arrayidx2, align 4
-  call void @bar(i32* %arrayidx) #2
-  ret void
-}
-
-; CHECK-LABEL: @main
-; CHECK: alloca [2 x i32], align 32
-; CHECK-NOT: alloca [2 x i32]
-; CHECK: ret i32 0
-
-define signext i32 @main() {
-entry:
-  %a = alloca i64, align 8
-  %tmpcast = bitcast i64* %a to %struct.s*
-  store i64 0, i64* %a, align 8
-  %a1 = bitcast i64* %a to i32*
-  store i32 1, i32* %a1, align 8
-  call void @foo(%struct.s* byval %tmpcast)
-  store i32 2, i32* %a1, align 8
-  call void @goo(%struct.s* byval %tmpcast)
-  ret i32 0
-}
-
-; CHECK-LABEL: @test0
-; CHECK: alloca [2 x i32], align 32
-; CHECK: alloca [2 x i32]
-; CHECK: ret i32 0
-
-define signext i32 @test0() {
-entry:
-  %a = alloca i64, align 8
-  %tmpcast = bitcast i64* %a to %struct.s*
-  store i64 0, i64* %a, align 8
-  %a1 = bitcast i64* %a to i32*
-  store i32 1, i32* %a1, align 8
-  call void @foo0(%struct.s* byval %tmpcast)
-  store i32 2, i32* %a1, align 8
-  call void @goo(%struct.s* byval %tmpcast)
-  ret i32 0
-}
diff --git a/test/Transforms/Inline/alloca-merge-align.ll b/test/Transforms/Inline/alloca-merge-align.ll
index d357b3cd61a4..70b94f7b69a0 100644
--- a/test/Transforms/Inline/alloca-merge-align.ll
+++ b/test/Transforms/Inline/alloca-merge-align.ll
@@ -8,13 +8,13 @@ target triple = "powerpc64-unknown-linux-gnu"
 define void @foo(%struct.s* byval nocapture readonly %a) {
 entry:
   %x = alloca [2 x i32], align 4
-  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
-  %0 = load i32* %a1, align 4
-  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
+  %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0
+  %0 = load i32, i32* %a1, align 4
+  %arrayidx = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 0
   store i32 %0, i32* %arrayidx, align 4
-  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
-  %1 = load i32* %b, align 4
-  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
+  %b = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 1
+  %1 = load i32, i32* %b, align 4
+  %arrayidx2 = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 1
   store i32 %1, i32* %arrayidx2, align 4
   call void @bar(i32* %arrayidx) #2
   ret void
@@ -23,13 +23,13 @@ entry:
 define void @foo0(%struct.s* byval nocapture readonly %a) {
 entry:
   %x = alloca [2 x i32]
-  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
-  %0 = load i32* %a1, align 4
-  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
+  %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0
+  %0 = load i32, i32* %a1, align 4
+  %arrayidx = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 0
   store i32 %0, i32* %arrayidx, align 4
-  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
-  %1 = load i32* %b, align 4
-  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
+  %b = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 1
+  %1 = load i32, i32* %b, align 4
+  %arrayidx2 = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 1
   store i32 %1, i32* %arrayidx2, align 4
   call void @bar(i32* %arrayidx) #2
   ret void
@@ -38,13 +38,13 @@ entry:
 define void @foo1(%struct.s* byval nocapture readonly %a) {
 entry:
   %x = alloca [2 x i32], align 1
-  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
-  %0 = load i32* %a1, align 4
-  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
+  %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0
+  %0 = load i32, i32* %a1, align 4
+  %arrayidx = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 0
   store i32 %0, i32* %arrayidx, align 4
-  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
-  %1 = load i32* %b, align 4
-  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
+  %b = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 1
+  %1 = load i32, i32* %b, align 4
+  %arrayidx2 = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 1
   store i32 %1, i32* %arrayidx2, align 4
   call void @bar(i32* %arrayidx) #2
   ret void
@@ -55,13 +55,13 @@ declare void @bar(i32*) #1
 define void @goo(%struct.s* byval nocapture readonly %a) {
 entry:
   %x = alloca [2 x i32], align 32
-  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
-  %0 = load i32* %a1, align 4
-  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
+  %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0
+  %0 = load i32, i32* %a1, align 4
+  %arrayidx = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 0
   store i32 %0, i32* %arrayidx, align 32
-  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
-  %1 = load i32* %b, align 4
-  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
+  %b = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 1
+  %1 = load i32, i32* %b, align 4
+  %arrayidx2 = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 1
   store i32 %1, i32* %arrayidx2, align 4
   call void @bar(i32* %arrayidx) #2
   ret void
@@ -102,21 +102,3 @@ entry:
   call void @goo(%struct.s* byval %tmpcast)
   ret i32 0
 }
-
-; CHECK-LABEL: @test1
-; CHECK: {{alloca \[2 x i32\]$}}
-; CHECK-NOT: alloca [2 x i32]
-; CHECK: ret i32 0
-
-define signext i32 @test1() {
-entry:
-  %a = alloca i64, align 8
-  %tmpcast = bitcast i64* %a to %struct.s*
-  store i64 0, i64* %a, align 8
-  %a1 = bitcast i64* %a to i32*
-  store i32 1, i32* %a1, align 8
-  call void @foo0(%struct.s* byval %tmpcast)
-  store i32 2, i32* %a1, align 8
-  call void @foo1(%struct.s* byval %tmpcast)
-  ret i32 0
-}
diff --git a/test/Transforms/Inline/attributes.ll b/test/Transforms/Inline/attributes.ll
index 53fb13f2baf5..a97e6a60de75 100644
--- a/test/Transforms/Inline/attributes.ll
+++ b/test/Transforms/Inline/attributes.ll
@@ -110,3 +110,53 @@ define i32 @test_sanitize_thread(i32 %arg) sanitize_thread {
 ; CHECK-NEXT: @noattr_callee
 ; CHECK-NEXT: ret i32
 }
+
+; Check that a function doesn't get inlined if target-cpu strings don't match
+; exactly.
+define i32 @test_target_cpu_callee0(i32 %i) "target-cpu"="corei7" {
+  ret i32 %i
+}
+
+define i32 @test_target_cpu0(i32 %i) "target-cpu"="corei7" {
+  %1 = call i32 @test_target_cpu_callee0(i32 %i)
+  ret i32 %1
+; CHECK-LABEL: @test_target_cpu0(
+; CHECK-NOT: @test_target_cpu_callee0
+}
+
+define i32 @test_target_cpu_callee1(i32 %i) "target-cpu"="x86-64" {
+  ret i32 %i
+}
+
+define i32 @test_target_cpu1(i32 %i) "target-cpu"="corei7" {
+  %1 = call i32 @test_target_cpu_callee1(i32 %i)
+  ret i32 %1
+; CHECK-LABEL: @test_target_cpu1(
+; CHECK-NEXT: @test_target_cpu_callee1
+; CHECK-NEXT: ret i32
+}
+
+; Check that a function doesn't get inlined if target-features strings don't
+; match exactly.
+define i32 @test_target_features_callee0(i32 %i)  "target-features"="+sse4.2" {
+  ret i32 %i
+}
+
+define i32 @test_target_features0(i32 %i) "target-features"="+sse4.2" {
+  %1 = call i32 @test_target_features_callee0(i32 %i)
+  ret i32 %1
+; CHECK-LABEL: @test_target_features0(
+; CHECK-NOT: @test_target_features_callee0
+}
+
+define i32 @test_target_features_callee1(i32 %i) "target-features"="+avx2" {
+  ret i32 %i
+}
+
+define i32 @test_target_features1(i32 %i) "target-features"="+sse4.2" {
+  %1 = call i32 @test_target_features_callee1(i32 %i)
+  ret i32 %1
+; CHECK-LABEL: @test_target_features1(
+; CHECK-NEXT: @test_target_features_callee1
+; CHECK-NEXT: ret i32
+}
diff --git a/test/Transforms/Inline/basictest.ll b/test/Transforms/Inline/basictest.ll
index 085694febc6a..8f0b3eafaecb 100644
--- a/test/Transforms/Inline/basictest.ll
+++ b/test/Transforms/Inline/basictest.ll
@@ -25,7 +25,7 @@ define internal %T* @test2f(i1 %cond, %T* %P) {
   br i1 %cond, label %T, label %F
   
 T:
-  %A = getelementptr %T* %P, i32 0, i32 0
+  %A = getelementptr %T, %T* %P, i32 0, i32 0
   store i32 42, i32* %A
   ret %T* %P
   
@@ -37,8 +37,8 @@ define i32 @test2(i1 %cond) {
   %A = alloca %T
   
   %B = call %T* @test2f(i1 %cond, %T* %A)
-  %C = getelementptr %T* %B, i32 0, i32 0
-  %D = load i32* %C
+  %C = getelementptr %T, %T* %B, i32 0, i32 0
+  %D = load i32, i32* %C
   ret i32 %D
   
 ; CHECK-LABEL: @test2(
diff --git a/test/Transforms/Inline/byval-tail-call.ll b/test/Transforms/Inline/byval-tail-call.ll
index 154f3974b58d..1e50463ed80c 100644
--- a/test/Transforms/Inline/byval-tail-call.ll
+++ b/test/Transforms/Inline/byval-tail-call.ll
@@ -31,7 +31,7 @@ define internal void @qux(i32* byval %x) {
 define void @frob(i32* %x) {
 ; CHECK-LABEL: define void @frob(
 ; CHECK: %[[POS:.*]] = alloca i32
-; CHECK: %[[VAL:.*]] = load i32* %x
+; CHECK: %[[VAL:.*]] = load i32, i32* %x
 ; CHECK: store i32 %[[VAL]], i32* %[[POS]]
 ; CHECK: {{^ *}}call void @ext(i32* %[[POS]]
 ; CHECK: tail call void @ext(i32* null)
diff --git a/test/Transforms/Inline/byval.ll b/test/Transforms/Inline/byval.ll
index d7597adaf84f..d4edf2503cf6 100644
--- a/test/Transforms/Inline/byval.ll
+++ b/test/Transforms/Inline/byval.ll
@@ -7,8 +7,8 @@
 
 define internal void @f(%struct.ss* byval  %b) nounwind  {
 entry:
-	%tmp = getelementptr %struct.ss* %b, i32 0, i32 0		; <i32*> [#uses=2]
-	%tmp1 = load i32* %tmp, align 4		; <i32> [#uses=1]
+	%tmp = getelementptr %struct.ss, %struct.ss* %b, i32 0, i32 0		; <i32*> [#uses=2]
+	%tmp1 = load i32, i32* %tmp, align 4		; <i32> [#uses=1]
 	%tmp2 = add i32 %tmp1, 1		; <i32> [#uses=1]
 	store i32 %tmp2, i32* %tmp, align 4
 	ret void
@@ -19,9 +19,9 @@ declare i32 @printf(i8*, ...) nounwind
 define i32 @test1() nounwind  {
 entry:
 	%S = alloca %struct.ss		; <%struct.ss*> [#uses=4]
-	%tmp1 = getelementptr %struct.ss* %S, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp1 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 1, i32* %tmp1, align 8
-	%tmp4 = getelementptr %struct.ss* %S, i32 0, i32 1		; <i64*> [#uses=1]
+	%tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1		; <i64*> [#uses=1]
 	store i64 2, i64* %tmp4, align 4
 	call void @f( %struct.ss* byval  %S ) nounwind 
 	ret i32 0
@@ -37,8 +37,8 @@ entry:
 
 define internal i32 @f2(%struct.ss* byval  %b) nounwind readonly {
 entry:
-	%tmp = getelementptr %struct.ss* %b, i32 0, i32 0		; <i32*> [#uses=2]
-	%tmp1 = load i32* %tmp, align 4		; <i32> [#uses=1]
+	%tmp = getelementptr %struct.ss, %struct.ss* %b, i32 0, i32 0		; <i32*> [#uses=2]
+	%tmp1 = load i32, i32* %tmp, align 4		; <i32> [#uses=1]
 	%tmp2 = add i32 %tmp1, 1		; <i32> [#uses=1]
 	ret i32 %tmp2
 }
@@ -46,9 +46,9 @@ entry:
 define i32 @test2() nounwind  {
 entry:
 	%S = alloca %struct.ss		; <%struct.ss*> [#uses=4]
-	%tmp1 = getelementptr %struct.ss* %S, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp1 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 1, i32* %tmp1, align 8
-	%tmp4 = getelementptr %struct.ss* %S, i32 0, i32 1		; <i64*> [#uses=1]
+	%tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1		; <i64*> [#uses=1]
 	store i64 2, i64* %tmp4, align 4
 	%X = call i32 @f2( %struct.ss* byval  %S ) nounwind 
 	ret i32 %X
@@ -111,9 +111,9 @@ entry:
 
 define internal void @f5(%struct.S0* byval nocapture readonly align 4 %p) {
 entry:
-	store i32 0, i32* getelementptr inbounds (%struct.S0* @b, i64 0, i32 0), align 4
-	%f2 = getelementptr inbounds %struct.S0* %p, i64 0, i32 0
-	%0 = load i32* %f2, align 4
+	store i32 0, i32* getelementptr inbounds (%struct.S0, %struct.S0* @b, i64 0, i32 0), align 4
+	%f2 = getelementptr inbounds %struct.S0, %struct.S0* %p, i64 0, i32 0
+	%0 = load i32, i32* %f2, align 4
 	store i32 %0, i32* @a, align 4
 	ret void
 }
@@ -121,9 +121,9 @@ entry:
 define i32 @test5() {
 entry:
 	tail call void @f5(%struct.S0* byval align 4 @b)
-	%0 = load i32* @a, align 4
+	%0 = load i32, i32* @a, align 4
 	ret i32 %0
 ; CHECK: @test5()
-; CHECK: store i32 0, i32* getelementptr inbounds (%struct.S0* @b, i64 0, i32 0), align 4
-; CHECK-NOT: load i32* getelementptr inbounds (%struct.S0* @b, i64 0, i32 0), align 4
+; CHECK: store i32 0, i32* getelementptr inbounds (%struct.S0, %struct.S0* @b, i64 0, i32 0), align 4
+; CHECK-NOT: load i32, i32* getelementptr inbounds (%struct.S0, %struct.S0* @b, i64 0, i32 0), align 4
 }
diff --git a/test/Transforms/Inline/byval_lifetime.ll b/test/Transforms/Inline/byval_lifetime.ll
index e8dff2aa711d..b500eaea3317 100644
--- a/test/Transforms/Inline/byval_lifetime.ll
+++ b/test/Transforms/Inline/byval_lifetime.ll
@@ -10,9 +10,9 @@
 
 define i32 @foo(%struct.foo* byval align 8 %f, i32 %a) {
 entry:
-  %a1 = getelementptr inbounds %struct.foo* %f, i32 0, i32 1
-  %arrayidx = getelementptr inbounds [16 x i32]* %a1, i32 0, i32 %a
-  %tmp2 = load i32* %arrayidx, align 1
+  %a1 = getelementptr inbounds %struct.foo, %struct.foo* %f, i32 0, i32 1
+  %arrayidx = getelementptr inbounds [16 x i32], [16 x i32]* %a1, i32 0, i32 %a
+  %tmp2 = load i32, i32* %arrayidx, align 1
   ret i32 %tmp2
 }
 
diff --git a/test/Transforms/Inline/crash-lifetime-marker.ll b/test/Transforms/Inline/crash-lifetime-marker.ll
new file mode 100644
index 000000000000..42e926b1f63d
--- /dev/null
+++ b/test/Transforms/Inline/crash-lifetime-marker.ll
@@ -0,0 +1,24 @@
+; RUN: opt < %s -inline -S | FileCheck %s
+
+; InlineFunction would assert inside the loop that leaves lifetime markers if
+; there was an zero-sized AllocaInst. Check that it doesn't assert and doesn't
+; leave lifetime markers in that case.
+
+declare i32 @callee2(i8*)
+
+define i32 @callee1(i32 %count) {
+  %a0 = alloca i8, i32 %count, align 4
+  %call0 = call i32 @callee2(i8* %a0)
+  ret i32 %call0
+}
+
+; CHECK-LABEL: define i32 @caller1(
+; CHECK: [[ALLOCA:%[a-z0-9\.]+]] = alloca i8
+; CHECK-NOT: call void @llvm.lifetime.start(
+; CHECK: call i32 @callee2(i8* [[ALLOCA]])
+; CHECK-NOT: call void @llvm.lifetime.end(
+
+define i32 @caller1(i32 %count) {
+  %call0 = call i32 @callee1(i32 0)
+  ret i32 %call0
+}
diff --git a/test/Transforms/Inline/crash2.ll b/test/Transforms/Inline/crash2.ll
index be634f625633..4c0dfaea0364 100644
--- a/test/Transforms/Inline/crash2.ll
+++ b/test/Transforms/Inline/crash2.ll
@@ -14,7 +14,7 @@ entry:
   %__f_addr = alloca void (i8*)*, align 8
   store void (i8*)* %__f, void (i8*)** %__f_addr
 
-  %0 = load void (i8*)** %__f_addr, align 8
+  %0 = load void (i8*)*, void (i8*)** %__f_addr, align 8
   call void %0(i8* undef)
   call i8* @f1(i8* undef) ssp
   unreachable
diff --git a/test/Transforms/Inline/debug-info-duplicate-calls.ll b/test/Transforms/Inline/debug-info-duplicate-calls.ll
new file mode 100644
index 000000000000..4e3d9d92fdb3
--- /dev/null
+++ b/test/Transforms/Inline/debug-info-duplicate-calls.ll
@@ -0,0 +1,121 @@
+; RUN: opt < %s -always-inline -S | FileCheck %s
+
+; Original input generated from clang -emit-llvm -S -c -mllvm -disable-llvm-optzns
+;
+; #define CALLS1 f2(); f2();
+; #define CALLS2 f4(); f4();
+; void f1();
+; inline __attribute__((always_inline)) void f2() {
+;   f1();
+; }
+; inline __attribute__((always_inline)) void f3() {
+;   CALLS1
+; }
+; inline __attribute__((always_inline)) void f4() {
+;   f3();
+; }
+; void f() {
+;   CALLS2
+; }
+
+; There should be unique locations for all 4 of these instructions, correctly
+; describing the inlining that has occurred, even in the face of duplicate call
+; site locations.
+
+; The nomenclature used for the tags here is <function name>[cs<number>] where
+; 'cs' is an abbreviation for 'call site' and the number indicates which call
+; site from within the named function this is. (so, given the above inlining, we
+; should have 4 calls to 'f1', two from the first call to f4 and two from the
+; second call to f4)
+
+; CHECK: call void @_Z2f1v(), !dbg [[fcs1_f4_f3cs1_f2:![0-9]+]]
+; CHECK: call void @_Z2f1v(), !dbg [[fcs1_f4_f3cs2_f2:![0-9]+]]
+; CHECK: call void @_Z2f1v(), !dbg [[fcs2_f4_f3cs1_f2:![0-9]+]]
+; CHECK: call void @_Z2f1v(), !dbg [[fcs2_f4_f3cs2_f2:![0-9]+]]
+
+; CHECK-DAG: [[F:![0-9]+]]  = !DISubprogram(name: "f"
+; CHECK-DAG: [[F2:![0-9]+]] = !DISubprogram(name: "f2"
+; CHECK-DAG: [[F3:![0-9]+]] = !DISubprogram(name: "f3"
+; CHECK-DAG: [[F4:![0-9]+]] = !DISubprogram(name: "f4"
+
+; CHECK: [[fcs1_f4_f3cs1_f2]] = {{.*}}, scope: [[F2]], inlinedAt: [[fcs1_f4_f3cs1:![0-9]+]])
+; CHECK: [[fcs1_f4_f3cs1]] = {{.*}}, scope: [[F3]], inlinedAt: [[fcs1_f4:![0-9]+]])
+; CHECK: [[fcs1_f4]] = {{.*}}, scope: [[F4]], inlinedAt: [[fcs1:![0-9]+]])
+; CHECK: [[fcs1]] = {{.*}}, scope: [[F]])
+; CHECK: [[fcs1_f4_f3cs2_f2]] = {{.*}}, scope: [[F2]], inlinedAt: [[fcs1_f4_f3cs2:![0-9]+]])
+; CHECK: [[fcs1_f4_f3cs2]] = {{.*}}, scope: [[F3]], inlinedAt: [[fcs1_f4]])
+
+; CHECK: [[fcs2_f4_f3cs1_f2]] = {{.*}}, scope: [[F2]], inlinedAt: [[fcs2_f4_f3cs1:![0-9]+]])
+; CHECK: [[fcs2_f4_f3cs1]] = {{.*}}, scope: [[F3]], inlinedAt: [[fcs2_f4:![0-9]+]])
+; CHECK: [[fcs2_f4]] = {{.*}}, scope: [[F4]], inlinedAt: [[fcs2:![0-9]+]])
+; CHECK: [[fcs2]] = {{.*}}, scope: [[F]])
+; CHECK: [[fcs2_f4_f3cs2_f2]] = {{.*}}, scope: [[F2]], inlinedAt: [[fcs2_f4_f3cs2:![0-9]+]])
+; CHECK: [[fcs2_f4_f3cs2]] = {{.*}}, scope: [[F3]], inlinedAt: [[fcs2_f4]])
+
+$_Z2f4v = comdat any
+
+$_Z2f3v = comdat any
+
+$_Z2f2v = comdat any
+
+; Function Attrs: uwtable
+define void @_Z1fv() #0 {
+entry:
+  call void @_Z2f4v(), !dbg !13
+  call void @_Z2f4v(), !dbg !13
+  ret void, !dbg !14
+}
+
+; Function Attrs: alwaysinline inlinehint uwtable
+define linkonce_odr void @_Z2f4v() #1 comdat {
+entry:
+  call void @_Z2f3v(), !dbg !15
+  ret void, !dbg !16
+}
+
+; Function Attrs: alwaysinline inlinehint uwtable
+define linkonce_odr void @_Z2f3v() #1 comdat {
+entry:
+  call void @_Z2f2v(), !dbg !17
+  call void @_Z2f2v(), !dbg !17
+  ret void, !dbg !18
+}
+
+; Function Attrs: alwaysinline inlinehint uwtable
+define linkonce_odr void @_Z2f2v() #1 comdat {
+entry:
+  call void @_Z2f1v(), !dbg !19
+  ret void, !dbg !20
+}
+
+declare void @_Z2f1v() #2
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { alwaysinline inlinehint uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!10, !11}
+!llvm.ident = !{!12}
+
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.7.0 (trunk 226474) (llvm/trunk 226478)", isOptimized: false, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "debug-info-duplicate-calls.cpp", directory: "/tmp/dbginfo")
+!2 = !{}
+!3 = !{!4, !7, !8, !9}
+!4 = !DISubprogram(name: "f", line: 13, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 13, file: !1, scope: !5, type: !6, function: void ()* @_Z1fv, variables: !2)
+!5 = !DIFile(filename: "debug-info-duplicate-calls.cpp", directory: "/tmp/dbginfo")
+!6 = !DISubroutineType(types: !2)
+!7 = !DISubprogram(name: "f4", line: 10, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 10, file: !1, scope: !5, type: !6, function: void ()* @_Z2f4v, variables: !2)
+!8 = !DISubprogram(name: "f3", line: 7, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !1, scope: !5, type: !6, function: void ()* @_Z2f3v, variables: !2)
+!9 = !DISubprogram(name: "f2", line: 4, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 4, file: !1, scope: !5, type: !6, function: void ()* @_Z2f2v, variables: !2)
+!10 = !{i32 2, !"Dwarf Version", i32 4}
+!11 = !{i32 2, !"Debug Info Version", i32 3}
+!12 = !{!"clang version 3.7.0 (trunk 226474) (llvm/trunk 226478)"}
+!13 = !DILocation(line: 14, column: 3, scope: !4)
+!14 = !DILocation(line: 15, column: 1, scope: !4)
+!15 = !DILocation(line: 11, column: 3, scope: !7)
+!16 = !DILocation(line: 12, column: 1, scope: !7)
+!17 = !DILocation(line: 8, column: 3, scope: !8)
+!18 = !DILocation(line: 9, column: 1, scope: !8)
+!19 = !DILocation(line: 5, column: 3, scope: !9)
+!20 = !DILocation(line: 6, column: 1, scope: !9)
diff --git a/test/Transforms/Inline/debug-invoke.ll b/test/Transforms/Inline/debug-invoke.ll
index 4815e689b8a5..bb40091014cf 100644
--- a/test/Transforms/Inline/debug-invoke.ll
+++ b/test/Transforms/Inline/debug-invoke.ll
@@ -4,9 +4,9 @@
 
 ; CHECK: invoke void @test()
 ; CHECK-NEXT: to label {{.*}} unwind label {{.*}}, !dbg [[INL_LOC:!.*]]
-; CHECK: [[EMPTY:.*]] = !{}
-; CHECK: [[INL_LOC]] = !MDLocation(line: 1, scope: [[EMPTY]], inlinedAt: [[INL_AT:.*]])
-; CHECK: [[INL_AT]] = !MDLocation(line: 2, scope: [[EMPTY]])
+; CHECK: [[SP:.*]] = !DISubprogram(
+; CHECK: [[INL_LOC]] = !DILocation(line: 1, scope: [[SP]], inlinedAt: [[INL_AT:.*]])
+; CHECK: [[INL_AT]] = distinct !DILocation(line: 2, scope: [[SP]])
 
 declare void @test()
 declare i32 @__gxx_personality_v0(...)
@@ -31,7 +31,7 @@ lpad:
 }
 
 !llvm.module.flags = !{!1}
-!1 = !{i32 2, !"Debug Info Version", i32 2}
-!2 = !{}
-!3 = !MDLocation(line: 1, scope: !2)
-!4 = !MDLocation(line: 2, scope: !2)
+!1 = !{i32 2, !"Debug Info Version", i32 3}
+!2 = !DISubprogram()
+!3 = !DILocation(line: 1, scope: !2)
+!4 = !DILocation(line: 2, scope: !2)
diff --git a/test/Transforms/Inline/devirtualize-2.ll b/test/Transforms/Inline/devirtualize-2.ll
index b7eb1be19db2..cca4e7582b5f 100644
--- a/test/Transforms/Inline/devirtualize-2.ll
+++ b/test/Transforms/Inline/devirtualize-2.ll
@@ -2,7 +2,7 @@
 ; PR4834
 
 define i32 @test1() {
-  %funcall1_ = call fastcc i32 ()* ()* @f1()
+  %funcall1_ = call fastcc i32 ()* () @f1()
   %executecommandptr1_ = call i32 %funcall1_()
   ret i32 %executecommandptr1_
 }
diff --git a/test/Transforms/Inline/devirtualize-3.ll b/test/Transforms/Inline/devirtualize-3.ll
index 3f019676e4a4..76c8150de01f 100644
--- a/test/Transforms/Inline/devirtualize-3.ll
+++ b/test/Transforms/Inline/devirtualize-3.ll
@@ -14,12 +14,12 @@ target triple = "x86_64-apple-darwin10.0.0"
 define i32 @main() nounwind ssp {
 entry:
   %cont = alloca %struct.cont_t, align 8          ; <%struct.cont_t*> [#uses=4]
-  %tmp = getelementptr inbounds %struct.cont_t* %cont, i32 0, i32 0 ; <void (i8*, i32)**> [#uses=1]
-  %tmp1 = getelementptr inbounds %struct.cont_t* %cont, i32 0, i32 0 ; <void (i8*, i32)**> [#uses=2]
+  %tmp = getelementptr inbounds %struct.cont_t, %struct.cont_t* %cont, i32 0, i32 0 ; <void (i8*, i32)**> [#uses=1]
+  %tmp1 = getelementptr inbounds %struct.cont_t, %struct.cont_t* %cont, i32 0, i32 0 ; <void (i8*, i32)**> [#uses=2]
   store void (i8*, i32)* bitcast (void (%struct.cont_t*, i32)* @quit to void (i8*, i32)*), void (i8*, i32)** %tmp1
-  %tmp2 = load void (i8*, i32)** %tmp1            ; <void (i8*, i32)*> [#uses=1]
+  %tmp2 = load void (i8*, i32)*, void (i8*, i32)** %tmp1            ; <void (i8*, i32)*> [#uses=1]
   store void (i8*, i32)* %tmp2, void (i8*, i32)** %tmp
-  %tmp3 = getelementptr inbounds %struct.cont_t* %cont, i32 0, i32 1 ; <i8**> [#uses=1]
+  %tmp3 = getelementptr inbounds %struct.cont_t, %struct.cont_t* %cont, i32 0, i32 1 ; <i8**> [#uses=1]
   store i8* null, i8** %tmp3
   call void @foo(%struct.cont_t* %cont)
   ret i32 0
@@ -35,13 +35,13 @@ define internal void @foo(%struct.cont_t* %c) nounwind ssp {
 entry:
   %sf = alloca %struct.foo_sf_t, align 8          ; <%struct.foo_sf_t*> [#uses=3]
   %next = alloca %struct.cont_t, align 8          ; <%struct.cont_t*> [#uses=3]
-  %tmp = getelementptr inbounds %struct.foo_sf_t* %sf, i32 0, i32 0 ; <%struct.cont_t**> [#uses=1]
+  %tmp = getelementptr inbounds %struct.foo_sf_t, %struct.foo_sf_t* %sf, i32 0, i32 0 ; <%struct.cont_t**> [#uses=1]
   store %struct.cont_t* %c, %struct.cont_t** %tmp
-  %tmp2 = getelementptr inbounds %struct.foo_sf_t* %sf, i32 0, i32 1 ; <i32*> [#uses=1]
+  %tmp2 = getelementptr inbounds %struct.foo_sf_t, %struct.foo_sf_t* %sf, i32 0, i32 1 ; <i32*> [#uses=1]
   store i32 2, i32* %tmp2
-  %tmp4 = getelementptr inbounds %struct.cont_t* %next, i32 0, i32 0 ; <void (i8*, i32)**> [#uses=1]
+  %tmp4 = getelementptr inbounds %struct.cont_t, %struct.cont_t* %next, i32 0, i32 0 ; <void (i8*, i32)**> [#uses=1]
   store void (i8*, i32)* bitcast (void (%struct.foo_sf_t*, i32)* @foo2 to void (i8*, i32)*), void (i8*, i32)** %tmp4
-  %tmp5 = getelementptr inbounds %struct.cont_t* %next, i32 0, i32 1 ; <i8**> [#uses=1]
+  %tmp5 = getelementptr inbounds %struct.cont_t, %struct.cont_t* %next, i32 0, i32 1 ; <i8**> [#uses=1]
   %conv = bitcast %struct.foo_sf_t* %sf to i8*    ; <i8*> [#uses=1]
   store i8* %conv, i8** %tmp5
   call void @bar(%struct.cont_t* %next, i32 14)
@@ -50,15 +50,15 @@ entry:
 
 define internal void @foo2(%struct.foo_sf_t* %sf, i32 %y) nounwind ssp {
 entry:
-  %tmp1 = getelementptr inbounds %struct.foo_sf_t* %sf, i32 0, i32 0 ; <%struct.cont_t**> [#uses=1]
-  %tmp2 = load %struct.cont_t** %tmp1             ; <%struct.cont_t*> [#uses=1]
-  %tmp3 = getelementptr inbounds %struct.cont_t* %tmp2, i32 0, i32 0 ; <void (i8*, i32)**> [#uses=1]
-  %tmp4 = load void (i8*, i32)** %tmp3            ; <void (i8*, i32)*> [#uses=1]
-  %tmp6 = getelementptr inbounds %struct.foo_sf_t* %sf, i32 0, i32 0 ; <%struct.cont_t**> [#uses=1]
-  %tmp7 = load %struct.cont_t** %tmp6             ; <%struct.cont_t*> [#uses=1]
+  %tmp1 = getelementptr inbounds %struct.foo_sf_t, %struct.foo_sf_t* %sf, i32 0, i32 0 ; <%struct.cont_t**> [#uses=1]
+  %tmp2 = load %struct.cont_t*, %struct.cont_t** %tmp1             ; <%struct.cont_t*> [#uses=1]
+  %tmp3 = getelementptr inbounds %struct.cont_t, %struct.cont_t* %tmp2, i32 0, i32 0 ; <void (i8*, i32)**> [#uses=1]
+  %tmp4 = load void (i8*, i32)*, void (i8*, i32)** %tmp3            ; <void (i8*, i32)*> [#uses=1]
+  %tmp6 = getelementptr inbounds %struct.foo_sf_t, %struct.foo_sf_t* %sf, i32 0, i32 0 ; <%struct.cont_t**> [#uses=1]
+  %tmp7 = load %struct.cont_t*, %struct.cont_t** %tmp6             ; <%struct.cont_t*> [#uses=1]
   %conv = bitcast %struct.cont_t* %tmp7 to i8*    ; <i8*> [#uses=1]
-  %tmp9 = getelementptr inbounds %struct.foo_sf_t* %sf, i32 0, i32 1 ; <i32*> [#uses=1]
-  %tmp10 = load i32* %tmp9                        ; <i32> [#uses=1]
+  %tmp9 = getelementptr inbounds %struct.foo_sf_t, %struct.foo_sf_t* %sf, i32 0, i32 1 ; <i32*> [#uses=1]
+  %tmp10 = load i32, i32* %tmp9                        ; <i32> [#uses=1]
   %mul = mul i32 %tmp10, %y                       ; <i32> [#uses=1]
   call void %tmp4(i8* %conv, i32 %mul)
   ret void
@@ -66,10 +66,10 @@ entry:
 
 define internal void @bar(%struct.cont_t* %c, i32 %y) nounwind ssp {
 entry:
-  %tmp1 = getelementptr inbounds %struct.cont_t* %c, i32 0, i32 0 ; <void (i8*, i32)**> [#uses=1]
-  %tmp2 = load void (i8*, i32)** %tmp1            ; <void (i8*, i32)*> [#uses=1]
-  %tmp4 = getelementptr inbounds %struct.cont_t* %c, i32 0, i32 1 ; <i8**> [#uses=1]
-  %tmp5 = load i8** %tmp4                         ; <i8*> [#uses=1]
+  %tmp1 = getelementptr inbounds %struct.cont_t, %struct.cont_t* %c, i32 0, i32 0 ; <void (i8*, i32)**> [#uses=1]
+  %tmp2 = load void (i8*, i32)*, void (i8*, i32)** %tmp1            ; <void (i8*, i32)*> [#uses=1]
+  %tmp4 = getelementptr inbounds %struct.cont_t, %struct.cont_t* %c, i32 0, i32 1 ; <i8**> [#uses=1]
+  %tmp5 = load i8*, i8** %tmp4                         ; <i8*> [#uses=1]
   %add = add nsw i32 %y, 5                        ; <i32> [#uses=1]
   call void %tmp2(i8* %tmp5, i32 %add)
   ret void
diff --git a/test/Transforms/Inline/devirtualize.ll b/test/Transforms/Inline/devirtualize.ll
index 89482941267c..561bb62ae644 100644
--- a/test/Transforms/Inline/devirtualize.ll
+++ b/test/Transforms/Inline/devirtualize.ll
@@ -9,7 +9,7 @@ define i32 @foo(i32 ()** noalias %p, i64* noalias %q) nounwind ssp {
 entry:
   store i32 ()* @bar, i32 ()** %p
   store i64 0, i64* %q
-  %tmp3 = load i32 ()** %p                        ; <i32 ()*> [#uses=1]
+  %tmp3 = load i32 ()*, i32 ()** %p                        ; <i32 ()*> [#uses=1]
   %call = call i32 %tmp3()                        ; <i32> [#uses=1]
   %X = add i32 %call, 4
   ret i32 %X
@@ -47,11 +47,11 @@ entry:
 @_ZTS1C = linkonce_odr constant [3 x i8] c"1C\00"     ; <[3 x i8]*> [#uses=1]
 @_ZTVN10__cxxabiv117__class_type_infoE = external global i8* ; <i8**> [#uses=1]
 @_ZTS1A = linkonce_odr constant [3 x i8] c"1A\00"     ; <[3 x i8]*> [#uses=1]
-@_ZTI1A = linkonce_odr constant %0 { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8]* @_ZTS1A, i32 0, i32 0) } ; <%0*> [#uses=1]
+@_ZTI1A = linkonce_odr constant %0 { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @_ZTS1A, i32 0, i32 0) } ; <%0*> [#uses=1]
 @_ZTS1B = linkonce_odr constant [3 x i8] c"1B\00"     ; <[3 x i8]*> [#uses=1]
-@_ZTI1B = linkonce_odr constant %0 { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8]* @_ZTS1B, i32 0, i32 0) } ; <%0*> [#uses=1]
-@_ZTI1C = linkonce_odr constant %1 { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv121__vmi_class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8]* @_ZTS1C, i32 0, i32 0), i32 0, i32 2, i8* bitcast (%0* @_ZTI1A to i8*), i64 2, i8* bitcast (%0* @_ZTI1B to i8*), i64 2050 } ; <%1*> [#uses=1]
-@_ZTI1D = linkonce_odr constant %2 { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv120__si_class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8]* @_ZTS1D, i32 0, i32 0), i8* bitcast (%1* @_ZTI1C to i8*) } ; <%2*> [#uses=1]
+@_ZTI1B = linkonce_odr constant %0 { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @_ZTS1B, i32 0, i32 0) } ; <%0*> [#uses=1]
+@_ZTI1C = linkonce_odr constant %1 { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv121__vmi_class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @_ZTS1C, i32 0, i32 0), i32 0, i32 2, i8* bitcast (%0* @_ZTI1A to i8*), i64 2, i8* bitcast (%0* @_ZTI1B to i8*), i64 2050 } ; <%1*> [#uses=1]
+@_ZTI1D = linkonce_odr constant %2 { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv120__si_class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @_ZTS1D, i32 0, i32 0), i8* bitcast (%1* @_ZTI1C to i8*) } ; <%2*> [#uses=1]
 @_ZTV1C = linkonce_odr constant [6 x i8*] [i8* null, i8* bitcast (%1* @_ZTI1C to i8*), i8* bitcast (i32 (%struct.C*)* @_ZN1C1fEv to i8*), i8* inttoptr (i64 -8 to i8*), i8* bitcast (%1* @_ZTI1C to i8*), i8* bitcast (i32 (%struct.C*)* @_ZThn8_N1C1fEv to i8*)] ; <[6 x i8*]*> [#uses=2]
 @_ZTV1B = linkonce_odr constant [3 x i8*] [i8* null, i8* bitcast (%0* @_ZTI1B to i8*), i8* bitcast (i32 (%struct.A*)* @_ZN1B1fEv to i8*)] ; <[3 x i8*]*> [#uses=1]
 @_ZTV1A = linkonce_odr constant [3 x i8*] [i8* null, i8* bitcast (%0* @_ZTI1A to i8*), i8* bitcast (i32 (%struct.A*)* @_ZN1A1fEv to i8*)] ; <[3 x i8*]*> [#uses=1]
@@ -78,16 +78,16 @@ entry:
 
 cast.notnull:                                     ; preds = %entry
   %1 = bitcast %struct.C* %d to i8*               ; <i8*> [#uses=1]
-  %add.ptr = getelementptr i8* %1, i64 8          ; <i8*> [#uses=1]
+  %add.ptr = getelementptr i8, i8* %1, i64 8          ; <i8*> [#uses=1]
   %2 = bitcast i8* %add.ptr to %struct.A*         ; <%struct.A*> [#uses=1]
   br label %cast.end
 
 cast.end:                                         ; preds = %entry, %cast.notnull
   %3 = phi %struct.A* [ %2, %cast.notnull ], [ null, %entry ] ; <%struct.A*> [#uses=2]
   %4 = bitcast %struct.A* %3 to i32 (%struct.A*)*** ; <i32 (%struct.A*)***> [#uses=1]
-  %5 = load i32 (%struct.A*)*** %4                ; <i32 (%struct.A*)**> [#uses=1]
-  %vfn = getelementptr inbounds i32 (%struct.A*)** %5, i64 0 ; <i32 (%struct.A*)**> [#uses=1]
-  %6 = load i32 (%struct.A*)** %vfn               ; <i32 (%struct.A*)*> [#uses=1]
+  %5 = load i32 (%struct.A*)**, i32 (%struct.A*)*** %4                ; <i32 (%struct.A*)**> [#uses=1]
+  %vfn = getelementptr inbounds i32 (%struct.A*)*, i32 (%struct.A*)** %5, i64 0 ; <i32 (%struct.A*)**> [#uses=1]
+  %6 = load i32 (%struct.A*)*, i32 (%struct.A*)** %vfn               ; <i32 (%struct.A*)*> [#uses=1]
   %call = call i32 %6(%struct.A* %3)              ; <i32> [#uses=1]
   ret i32 %call
 }
@@ -100,7 +100,7 @@ entry:
 define linkonce_odr i32 @_ZThn8_N1D1fEv(%struct.C* %this) {
 entry:
   %0 = bitcast %struct.C* %this to i8*            ; <i8*> [#uses=1]
-  %1 = getelementptr inbounds i8* %0, i64 -8      ; <i8*> [#uses=1]
+  %1 = getelementptr inbounds i8, i8* %0, i64 -8      ; <i8*> [#uses=1]
   %2 = bitcast i8* %1 to %struct.C*               ; <%struct.C*> [#uses=1]
   %call = call i32 @_ZN1D1fEv(%struct.C* %2)      ; <i32> [#uses=1]
   ret i32 %call
@@ -110,13 +110,13 @@ define linkonce_odr void @_ZN1DC2Ev(%struct.C* %this) inlinehint ssp align 2 {
 entry:
   call void @_ZN1CC2Ev(%struct.C* %this)
   %0 = bitcast %struct.C* %this to i8*            ; <i8*> [#uses=1]
-  %1 = getelementptr inbounds i8* %0, i64 0       ; <i8*> [#uses=1]
+  %1 = getelementptr inbounds i8, i8* %0, i64 0       ; <i8*> [#uses=1]
   %2 = bitcast i8* %1 to i8***                    ; <i8***> [#uses=1]
-  store i8** getelementptr inbounds ([6 x i8*]* @_ZTV1D, i64 0, i64 2), i8*** %2
+  store i8** getelementptr inbounds ([6 x i8*], [6 x i8*]* @_ZTV1D, i64 0, i64 2), i8*** %2
   %3 = bitcast %struct.C* %this to i8*            ; <i8*> [#uses=1]
-  %4 = getelementptr inbounds i8* %3, i64 8       ; <i8*> [#uses=1]
+  %4 = getelementptr inbounds i8, i8* %3, i64 8       ; <i8*> [#uses=1]
   %5 = bitcast i8* %4 to i8***                    ; <i8***> [#uses=1]
-  store i8** getelementptr inbounds ([6 x i8*]* @_ZTV1D, i64 0, i64 5), i8*** %5
+  store i8** getelementptr inbounds ([6 x i8*], [6 x i8*]* @_ZTV1D, i64 0, i64 5), i8*** %5
   ret void
 }
 
@@ -125,17 +125,17 @@ entry:
   %0 = bitcast %struct.C* %this to %struct.A*     ; <%struct.A*> [#uses=1]
   call void @_ZN1AC2Ev(%struct.A* %0)
   %1 = bitcast %struct.C* %this to i8*            ; <i8*> [#uses=1]
-  %2 = getelementptr inbounds i8* %1, i64 8       ; <i8*> [#uses=1]
+  %2 = getelementptr inbounds i8, i8* %1, i64 8       ; <i8*> [#uses=1]
   %3 = bitcast i8* %2 to %struct.A*               ; <%struct.A*> [#uses=1]
   call void @_ZN1BC2Ev(%struct.A* %3)
   %4 = bitcast %struct.C* %this to i8*            ; <i8*> [#uses=1]
-  %5 = getelementptr inbounds i8* %4, i64 0       ; <i8*> [#uses=1]
+  %5 = getelementptr inbounds i8, i8* %4, i64 0       ; <i8*> [#uses=1]
   %6 = bitcast i8* %5 to i8***                    ; <i8***> [#uses=1]
-  store i8** getelementptr inbounds ([6 x i8*]* @_ZTV1C, i64 0, i64 2), i8*** %6
+  store i8** getelementptr inbounds ([6 x i8*], [6 x i8*]* @_ZTV1C, i64 0, i64 2), i8*** %6
   %7 = bitcast %struct.C* %this to i8*            ; <i8*> [#uses=1]
-  %8 = getelementptr inbounds i8* %7, i64 8       ; <i8*> [#uses=1]
+  %8 = getelementptr inbounds i8, i8* %7, i64 8       ; <i8*> [#uses=1]
   %9 = bitcast i8* %8 to i8***                    ; <i8***> [#uses=1]
-  store i8** getelementptr inbounds ([6 x i8*]* @_ZTV1C, i64 0, i64 5), i8*** %9
+  store i8** getelementptr inbounds ([6 x i8*], [6 x i8*]* @_ZTV1C, i64 0, i64 5), i8*** %9
   ret void
 }
 
@@ -147,7 +147,7 @@ entry:
 define linkonce_odr i32 @_ZThn8_N1C1fEv(%struct.C* %this) {
 entry:
   %0 = bitcast %struct.C* %this to i8*            ; <i8*> [#uses=1]
-  %1 = getelementptr inbounds i8* %0, i64 -8      ; <i8*> [#uses=1]
+  %1 = getelementptr inbounds i8, i8* %0, i64 -8      ; <i8*> [#uses=1]
   %2 = bitcast i8* %1 to %struct.C*               ; <%struct.C*> [#uses=1]
   %call = call i32 @_ZN1C1fEv(%struct.C* %2)      ; <i32> [#uses=1]
   ret i32 %call
@@ -156,18 +156,18 @@ entry:
 define linkonce_odr void @_ZN1AC2Ev(%struct.A* %this) inlinehint ssp align 2 {
 entry:
   %0 = bitcast %struct.A* %this to i8*            ; <i8*> [#uses=1]
-  %1 = getelementptr inbounds i8* %0, i64 0       ; <i8*> [#uses=1]
+  %1 = getelementptr inbounds i8, i8* %0, i64 0       ; <i8*> [#uses=1]
   %2 = bitcast i8* %1 to i8***                    ; <i8***> [#uses=1]
-  store i8** getelementptr inbounds ([3 x i8*]* @_ZTV1A, i64 0, i64 2), i8*** %2
+  store i8** getelementptr inbounds ([3 x i8*], [3 x i8*]* @_ZTV1A, i64 0, i64 2), i8*** %2
   ret void
 }
 
 define linkonce_odr void @_ZN1BC2Ev(%struct.A* %this) inlinehint ssp align 2 {
 entry:
   %0 = bitcast %struct.A* %this to i8*            ; <i8*> [#uses=1]
-  %1 = getelementptr inbounds i8* %0, i64 0       ; <i8*> [#uses=1]
+  %1 = getelementptr inbounds i8, i8* %0, i64 0       ; <i8*> [#uses=1]
   %2 = bitcast i8* %1 to i8***                    ; <i8***> [#uses=1]
-  store i8** getelementptr inbounds ([3 x i8*]* @_ZTV1B, i64 0, i64 2), i8*** %2
+  store i8** getelementptr inbounds ([3 x i8*], [3 x i8*]* @_ZTV1B, i64 0, i64 2), i8*** %2
   ret void
 }
 
diff --git a/test/Transforms/Inline/ephemeral.ll b/test/Transforms/Inline/ephemeral.ll
index d1135c6f0c3e..7e5ae034af35 100644
--- a/test/Transforms/Inline/ephemeral.ll
+++ b/test/Transforms/Inline/ephemeral.ll
@@ -3,7 +3,7 @@
 @a = global i32 4
 
 define i1 @inner() {
-  %a1 = load volatile i32* @a
+  %a1 = load volatile i32, i32* @a
   %x1 = add i32 %a1, %a1
   %c = icmp eq i32 %x1, 0
 
diff --git a/test/Transforms/Inline/frameescape.ll b/test/Transforms/Inline/frameescape.ll
new file mode 100644
index 000000000000..fb336024f937
--- /dev/null
+++ b/test/Transforms/Inline/frameescape.ll
@@ -0,0 +1,44 @@
+; RUN: opt -inline -S < %s | FileCheck %s
+
+; PR23216: We can't inline functions using llvm.frameescape.
+
+declare void @llvm.frameescape(...)
+declare i8* @llvm.frameaddress(i32)
+declare i8* @llvm.framerecover(i8*, i8*, i32)
+
+define internal void @foo(i8* %fp) {
+  %a.i8 = call i8* @llvm.framerecover(i8* bitcast (i32 ()* @bar to i8*), i8* %fp, i32 0)
+  %a = bitcast i8* %a.i8 to i32*
+  store i32 42, i32* %a
+  ret void
+}
+
+define internal i32 @bar() {
+entry:
+  %a = alloca i32
+  call void (...) @llvm.frameescape(i32* %a)
+  %fp = call i8* @llvm.frameaddress(i32 0)
+  tail call void @foo(i8* %fp)
+  %r = load i32, i32* %a
+  ret i32 %r
+}
+
+; We even bail when someone marks it alwaysinline.
+define internal i32 @bar_alwaysinline() alwaysinline {
+entry:
+  %a = alloca i32
+  call void (...) @llvm.frameescape(i32* %a)
+  tail call void @foo(i8* null)
+  ret i32 0
+}
+
+define i32 @bazz() {
+entry:
+  %r = tail call i32 @bar()
+  %r1 = tail call i32 @bar_alwaysinline()
+  ret i32 %r
+}
+
+; CHECK: define i32 @bazz()
+; CHECK: call i32 @bar()
+; CHECK: call i32 @bar_alwaysinline()
diff --git a/test/Transforms/Inline/gvn-inline-iteration.ll b/test/Transforms/Inline/gvn-inline-iteration.ll
index 7916a13df995..b87c0609ea2b 100644
--- a/test/Transforms/Inline/gvn-inline-iteration.ll
+++ b/test/Transforms/Inline/gvn-inline-iteration.ll
@@ -8,7 +8,7 @@ define i32 @foo(i32 ()** noalias nocapture %p, i64* noalias nocapture %q) nounwi
 entry:
   store i32 ()* @bar, i32 ()** %p
   store i64 0, i64* %q
-  %tmp3 = load i32 ()** %p                        ; <i32 ()*> [#uses=1]
+  %tmp3 = load i32 ()*, i32 ()** %p                        ; <i32 ()*> [#uses=1]
   %call = tail call i32 %tmp3() nounwind          ; <i32> [#uses=1]
   ret i32 %call
 }
diff --git a/test/Transforms/Inline/ignore-debug-info.ll b/test/Transforms/Inline/ignore-debug-info.ll
index 8bd6e7c4287b..eb92bc52cc94 100644
--- a/test/Transforms/Inline/ignore-debug-info.ll
+++ b/test/Transforms/Inline/ignore-debug-info.ll
@@ -12,11 +12,11 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
 
 define <4 x float> @inner_vectors(<4 x float> %a, <4 x float> %b) {
 entry:
-  call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}, metadata !{})
+  call void @llvm.dbg.value(metadata i32 undef, i64 0, metadata !DILocalVariable(tag: DW_TAG_auto_variable, scope: !6), metadata !DIExpression()), !dbg !DILocation(scope: !6)
   %mul = fmul <4 x float> %a, <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00>
-  call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}, metadata !{})
+  call void @llvm.dbg.value(metadata i32 undef, i64 0, metadata !DILocalVariable(tag: DW_TAG_auto_variable, scope: !6), metadata !DIExpression()), !dbg !DILocation(scope: !6)
   %mul1 = fmul <4 x float> %b, <float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00>
-  call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}, metadata !{})
+  call void @llvm.dbg.value(metadata i32 undef, i64 0, metadata !DILocalVariable(tag: DW_TAG_auto_variable, scope: !6), metadata !DIExpression()), !dbg !DILocation(scope: !6)
   %add = fadd <4 x float> %mul, %mul1
   ret <4 x float> %add
 }
@@ -27,10 +27,10 @@ define float @outer_vectors(<4 x float> %a, <4 x float> %b) {
 ; CHECK: ret float
 
 entry:
-  call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}, metadata !{})
-  call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}, metadata !{})
+  call void @llvm.dbg.value(metadata i32 undef, i64 0, metadata !DILocalVariable(tag: DW_TAG_auto_variable, scope: !6), metadata !DIExpression()), !dbg !DILocation(scope: !6)
+  call void @llvm.dbg.value(metadata i32 undef, i64 0, metadata !DILocalVariable(tag: DW_TAG_auto_variable, scope: !6), metadata !DIExpression()), !dbg !DILocation(scope: !6)
   %call = call <4 x float> @inner_vectors(<4 x float> %a, <4 x float> %b)
-  call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}, metadata !{})
+  call void @llvm.dbg.value(metadata i32 undef, i64 0, metadata !DILocalVariable(tag: DW_TAG_auto_variable, scope: !6), metadata !DIExpression()), !dbg !DILocation(scope: !6)
   %vecext = extractelement <4 x float> %call, i32 0
   %vecext1 = extractelement <4 x float> %call, i32 1
   %add = fadd float %vecext, %vecext1
@@ -47,9 +47,10 @@ attributes #0 = { nounwind readnone }
 !llvm.module.flags = !{!3, !4}
 !llvm.ident = !{!5}
 
-!0 = !{!"0x11\004\00\000\00\000\00\000", !1, !2, !2, !{}, !2, !2} ; [ DW_TAG_compile_unit ]
-!1 = !{!"", !""}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !{!6}, globals: !2, imports: !2)
+!1 = !DIFile(filename: "test.c", directory: "")
+!2 = !{}
 !3 = !{i32 2, !"Dwarf Version", i32 4}
-!4 = !{i32 1, !"Debug Info Version", i32 2}
+!4 = !{i32 1, !"Debug Info Version", i32 3}
 !5 = !{!""}
+!6 = !DISubprogram()
diff --git a/test/Transforms/Inline/inline-byval-bonus.ll b/test/Transforms/Inline/inline-byval-bonus.ll
index 052a5f12a191..7f0c0e1fcbaa 100644
--- a/test/Transforms/Inline/inline-byval-bonus.ll
+++ b/test/Transforms/Inline/inline-byval-bonus.ll
@@ -29,37 +29,37 @@ define i32 @caller(%struct.sphere* %i) {
 declare void @fix(%struct.ray*)
 
 define i32 @ray_sphere(%struct.sphere* nocapture %sph, %struct.ray* nocapture byval align 8 %ray, %struct.spoint* %sp) nounwind uwtable ssp {
-  %1 = getelementptr inbounds %struct.ray* %ray, i64 0, i32 1, i32 0
-  %2 = load double* %1, align 8
+  %1 = getelementptr inbounds %struct.ray, %struct.ray* %ray, i64 0, i32 1, i32 0
+  %2 = load double, double* %1, align 8
   %3 = fmul double %2, %2
-  %4 = getelementptr inbounds %struct.ray* %ray, i64 0, i32 1, i32 1
-  %5 = load double* %4, align 8
+  %4 = getelementptr inbounds %struct.ray, %struct.ray* %ray, i64 0, i32 1, i32 1
+  %5 = load double, double* %4, align 8
   %6 = fmul double %5, %5
   %7 = fadd double %3, %6
-  %8 = getelementptr inbounds %struct.ray* %ray, i64 0, i32 1, i32 2
-  %9 = load double* %8, align 8
+  %8 = getelementptr inbounds %struct.ray, %struct.ray* %ray, i64 0, i32 1, i32 2
+  %9 = load double, double* %8, align 8
   %10 = fmul double %9, %9
   %11 = fadd double %7, %10
   %12 = fmul double %2, 2.000000e+00
-  %13 = getelementptr inbounds %struct.ray* %ray, i64 0, i32 0, i32 0
-  %14 = load double* %13, align 8
-  %15 = getelementptr inbounds %struct.sphere* %sph, i64 0, i32 0, i32 0
-  %16 = load double* %15, align 8
+  %13 = getelementptr inbounds %struct.ray, %struct.ray* %ray, i64 0, i32 0, i32 0
+  %14 = load double, double* %13, align 8
+  %15 = getelementptr inbounds %struct.sphere, %struct.sphere* %sph, i64 0, i32 0, i32 0
+  %16 = load double, double* %15, align 8
   %17 = fsub double %14, %16
   %18 = fmul double %12, %17
   %19 = fmul double %5, 2.000000e+00
-  %20 = getelementptr inbounds %struct.ray* %ray, i64 0, i32 0, i32 1
-  %21 = load double* %20, align 8
-  %22 = getelementptr inbounds %struct.sphere* %sph, i64 0, i32 0, i32 1
-  %23 = load double* %22, align 8
+  %20 = getelementptr inbounds %struct.ray, %struct.ray* %ray, i64 0, i32 0, i32 1
+  %21 = load double, double* %20, align 8
+  %22 = getelementptr inbounds %struct.sphere, %struct.sphere* %sph, i64 0, i32 0, i32 1
+  %23 = load double, double* %22, align 8
   %24 = fsub double %21, %23
   %25 = fmul double %19, %24
   %26 = fadd double %18, %25
   %27 = fmul double %9, 2.000000e+00
-  %28 = getelementptr inbounds %struct.ray* %ray, i64 0, i32 0, i32 2
-  %29 = load double* %28, align 8
-  %30 = getelementptr inbounds %struct.sphere* %sph, i64 0, i32 0, i32 2
-  %31 = load double* %30, align 8
+  %28 = getelementptr inbounds %struct.ray, %struct.ray* %ray, i64 0, i32 0, i32 2
+  %29 = load double, double* %28, align 8
+  %30 = getelementptr inbounds %struct.sphere, %struct.sphere* %sph, i64 0, i32 0, i32 2
+  %31 = load double, double* %30, align 8
   %32 = fsub double %29, %31
   %33 = fmul double %27, %32
   %34 = fadd double %26, %33
@@ -82,8 +82,8 @@ define i32 @ray_sphere(%struct.sphere* nocapture %sph, %struct.ray* nocapture by
   %51 = fsub double %49, %50
   %52 = fmul double %51, 2.000000e+00
   %53 = fadd double %52, %45
-  %54 = getelementptr inbounds %struct.sphere* %sph, i64 0, i32 1
-  %55 = load double* %54, align 8
+  %54 = getelementptr inbounds %struct.sphere, %struct.sphere* %sph, i64 0, i32 1
+  %55 = load double, double* %54, align 8
   %56 = fmul double %55, %55
   %57 = fsub double %53, %56
   %58 = fmul double %34, %34
@@ -121,37 +121,37 @@ define i32 @ray_sphere(%struct.sphere* nocapture %sph, %struct.ray* nocapture by
   %t2.0 = select i1 %72, double %t1.0, double %70
   %79 = fcmp olt double %t1.0, %t2.0
   %80 = select i1 %79, double %t1.0, double %t2.0
-  %81 = getelementptr inbounds %struct.spoint* %sp, i64 0, i32 3
+  %81 = getelementptr inbounds %struct.spoint, %struct.spoint* %sp, i64 0, i32 3
   store double %80, double* %81, align 8
   %82 = fmul double %80, %2
   %83 = fadd double %14, %82
-  %84 = getelementptr inbounds %struct.spoint* %sp, i64 0, i32 0, i32 0
+  %84 = getelementptr inbounds %struct.spoint, %struct.spoint* %sp, i64 0, i32 0, i32 0
   store double %83, double* %84, align 8
   %85 = fmul double %5, %80
   %86 = fadd double %21, %85
-  %87 = getelementptr inbounds %struct.spoint* %sp, i64 0, i32 0, i32 1
+  %87 = getelementptr inbounds %struct.spoint, %struct.spoint* %sp, i64 0, i32 0, i32 1
   store double %86, double* %87, align 8
   %88 = fmul double %9, %80
   %89 = fadd double %29, %88
-  %90 = getelementptr inbounds %struct.spoint* %sp, i64 0, i32 0, i32 2
+  %90 = getelementptr inbounds %struct.spoint, %struct.spoint* %sp, i64 0, i32 0, i32 2
   store double %89, double* %90, align 8
-  %91 = load double* %15, align 8
+  %91 = load double, double* %15, align 8
   %92 = fsub double %83, %91
-  %93 = load double* %54, align 8
+  %93 = load double, double* %54, align 8
   %94 = fdiv double %92, %93
-  %95 = getelementptr inbounds %struct.spoint* %sp, i64 0, i32 1, i32 0
+  %95 = getelementptr inbounds %struct.spoint, %struct.spoint* %sp, i64 0, i32 1, i32 0
   store double %94, double* %95, align 8
-  %96 = load double* %22, align 8
+  %96 = load double, double* %22, align 8
   %97 = fsub double %86, %96
-  %98 = load double* %54, align 8
+  %98 = load double, double* %54, align 8
   %99 = fdiv double %97, %98
-  %100 = getelementptr inbounds %struct.spoint* %sp, i64 0, i32 1, i32 1
+  %100 = getelementptr inbounds %struct.spoint, %struct.spoint* %sp, i64 0, i32 1, i32 1
   store double %99, double* %100, align 8
-  %101 = load double* %30, align 8
+  %101 = load double, double* %30, align 8
   %102 = fsub double %89, %101
-  %103 = load double* %54, align 8
+  %103 = load double, double* %54, align 8
   %104 = fdiv double %102, %103
-  %105 = getelementptr inbounds %struct.spoint* %sp, i64 0, i32 1, i32 2
+  %105 = getelementptr inbounds %struct.spoint, %struct.spoint* %sp, i64 0, i32 1, i32 2
   store double %104, double* %105, align 8
   %106 = fmul double %2, %94
   %107 = fmul double %5, %99
@@ -168,9 +168,9 @@ define i32 @ray_sphere(%struct.sphere* nocapture %sph, %struct.ray* nocapture by
   %118 = fmul double %104, %111
   %119 = fsub double %118, %9
   %120 = fsub double -0.000000e+00, %119
-  %.06 = getelementptr inbounds %struct.spoint* %sp, i64 0, i32 2, i32 0
-  %.18 = getelementptr inbounds %struct.spoint* %sp, i64 0, i32 2, i32 1
-  %.210 = getelementptr inbounds %struct.spoint* %sp, i64 0, i32 2, i32 2
+  %.06 = getelementptr inbounds %struct.spoint, %struct.spoint* %sp, i64 0, i32 2, i32 0
+  %.18 = getelementptr inbounds %struct.spoint, %struct.spoint* %sp, i64 0, i32 2, i32 1
+  %.210 = getelementptr inbounds %struct.spoint, %struct.spoint* %sp, i64 0, i32 2, i32 2
   %121 = fmul double %113, %113
   %122 = fmul double %116, %116
   %123 = fadd double %121, %122
diff --git a/test/Transforms/Inline/inline-cold.ll b/test/Transforms/Inline/inline-cold.ll
index 57433771961e..b3c134538a45 100644
--- a/test/Transforms/Inline/inline-cold.ll
+++ b/test/Transforms/Inline/inline-cold.ll
@@ -17,29 +17,29 @@
 ; Function Attrs: nounwind readnone uwtable
 define i32 @simpleFunction(i32 %a) #0 {
 entry:
-  %a1 = load volatile i32* @a
+  %a1 = load volatile i32, i32* @a
   %x1 = add i32 %a1,  %a1
-  %a2 = load volatile i32* @a
+  %a2 = load volatile i32, i32* @a
   %x2 = add i32 %x1, %a2
-  %a3 = load volatile i32* @a
+  %a3 = load volatile i32, i32* @a
   %x3 = add i32 %x2, %a3
-  %a4 = load volatile i32* @a
+  %a4 = load volatile i32, i32* @a
   %x4 = add i32 %x3, %a4
-  %a5 = load volatile i32* @a
+  %a5 = load volatile i32, i32* @a
   %x5 = add i32 %x4, %a5
-  %a6 = load volatile i32* @a
+  %a6 = load volatile i32, i32* @a
   %x6 = add i32 %x5, %a6
-  %a7 = load volatile i32* @a
+  %a7 = load volatile i32, i32* @a
   %x7 = add i32 %x6, %a6
-  %a8 = load volatile i32* @a
+  %a8 = load volatile i32, i32* @a
   %x8 = add i32 %x7, %a8
-  %a9 = load volatile i32* @a
+  %a9 = load volatile i32, i32* @a
   %x9 = add i32 %x8, %a9
-  %a10 = load volatile i32* @a
+  %a10 = load volatile i32, i32* @a
   %x10 = add i32 %x9, %a10
-  %a11 = load volatile i32* @a
+  %a11 = load volatile i32, i32* @a
   %x11 = add i32 %x10, %a11
-  %a12 = load volatile i32* @a
+  %a12 = load volatile i32, i32* @a
   %x12 = add i32 %x11, %a12
   %add = add i32 %x12, %a
   ret i32 %add
@@ -54,29 +54,29 @@ define i32 @ColdFunction(i32 %a) #1 {
 ; DEFAULT-LABEL: @ColdFunction
 ; DEFAULT: ret
 entry:
-  %a1 = load volatile i32* @a
+  %a1 = load volatile i32, i32* @a
   %x1 = add i32 %a1,  %a1
-  %a2 = load volatile i32* @a
+  %a2 = load volatile i32, i32* @a
   %x2 = add i32 %x1, %a2
-  %a3 = load volatile i32* @a
+  %a3 = load volatile i32, i32* @a
   %x3 = add i32 %x2, %a3
-  %a4 = load volatile i32* @a
+  %a4 = load volatile i32, i32* @a
   %x4 = add i32 %x3, %a4
-  %a5 = load volatile i32* @a
+  %a5 = load volatile i32, i32* @a
   %x5 = add i32 %x4, %a5
-  %a6 = load volatile i32* @a
+  %a6 = load volatile i32, i32* @a
   %x6 = add i32 %x5, %a6
-  %a7 = load volatile i32* @a
+  %a7 = load volatile i32, i32* @a
   %x7 = add i32 %x6, %a6
-  %a8 = load volatile i32* @a
+  %a8 = load volatile i32, i32* @a
   %x8 = add i32 %x7, %a8
-  %a9 = load volatile i32* @a
+  %a9 = load volatile i32, i32* @a
   %x9 = add i32 %x8, %a9
-  %a10 = load volatile i32* @a
+  %a10 = load volatile i32, i32* @a
   %x10 = add i32 %x9, %a10
-  %a11 = load volatile i32* @a
+  %a11 = load volatile i32, i32* @a
   %x11 = add i32 %x10, %a11
-  %a12 = load volatile i32* @a
+  %a12 = load volatile i32, i32* @a
   %x12 = add i32 %x11, %a12
   %add = add i32 %x12, %a
   ret i32 %add
@@ -91,79 +91,79 @@ define i32 @ColdFunction2(i32 %a) #1 {
 ; DEFAULT-LABEL: @ColdFunction2
 ; DEFAULT: ret
 entry:
-  %a1 = load volatile i32* @a
+  %a1 = load volatile i32, i32* @a
   %x1 = add i32 %a1,  %a1
-  %a2 = load volatile i32* @a
+  %a2 = load volatile i32, i32* @a
   %x2 = add i32 %x1, %a2
-  %a3 = load volatile i32* @a
+  %a3 = load volatile i32, i32* @a
   %x3 = add i32 %x2, %a3
-  %a4 = load volatile i32* @a
+  %a4 = load volatile i32, i32* @a
   %x4 = add i32 %x3, %a4
-  %a5 = load volatile i32* @a
+  %a5 = load volatile i32, i32* @a
   %x5 = add i32 %x4, %a5
-  %a6 = load volatile i32* @a
+  %a6 = load volatile i32, i32* @a
   %x6 = add i32 %x5, %a6
-  %a7 = load volatile i32* @a
+  %a7 = load volatile i32, i32* @a
   %x7 = add i32 %x6, %a7
-  %a8 = load volatile i32* @a
+  %a8 = load volatile i32, i32* @a
   %x8 = add i32 %x7, %a8
-  %a9 = load volatile i32* @a
+  %a9 = load volatile i32, i32* @a
   %x9 = add i32 %x8, %a9
-  %a10 = load volatile i32* @a
+  %a10 = load volatile i32, i32* @a
   %x10 = add i32 %x9, %a10
-  %a11 = load volatile i32* @a
+  %a11 = load volatile i32, i32* @a
   %x11 = add i32 %x10, %a11
-  %a12 = load volatile i32* @a
+  %a12 = load volatile i32, i32* @a
   %x12 = add i32 %x11, %a12
 
-  %a21 = load volatile i32* @a
+  %a21 = load volatile i32, i32* @a
   %x21 = add i32 %x12, %a21
-  %a22 = load volatile i32* @a
+  %a22 = load volatile i32, i32* @a
   %x22 = add i32 %x21, %a22
-  %a23 = load volatile i32* @a
+  %a23 = load volatile i32, i32* @a
   %x23 = add i32 %x22, %a23
-  %a24 = load volatile i32* @a
+  %a24 = load volatile i32, i32* @a
   %x24 = add i32 %x23, %a24
-  %a25 = load volatile i32* @a
+  %a25 = load volatile i32, i32* @a
   %x25 = add i32 %x24, %a25
-  %a26 = load volatile i32* @a
+  %a26 = load volatile i32, i32* @a
   %x26 = add i32 %x25, %a26
-  %a27 = load volatile i32* @a
+  %a27 = load volatile i32, i32* @a
   %x27 = add i32 %x26, %a27
-  %a28 = load volatile i32* @a
+  %a28 = load volatile i32, i32* @a
   %x28 = add i32 %x27, %a28
-  %a29 = load volatile i32* @a
+  %a29 = load volatile i32, i32* @a
   %x29 = add i32 %x28, %a29
-  %a30 = load volatile i32* @a
+  %a30 = load volatile i32, i32* @a
   %x30 = add i32 %x29, %a30
-  %a31 = load volatile i32* @a
+  %a31 = load volatile i32, i32* @a
   %x31 = add i32 %x30, %a31
-  %a32 = load volatile i32* @a
+  %a32 = load volatile i32, i32* @a
   %x32 = add i32 %x31, %a32
 
-  %a41 = load volatile i32* @a
+  %a41 = load volatile i32, i32* @a
   %x41 = add i32 %x32, %a41
-  %a42 = load volatile i32* @a
+  %a42 = load volatile i32, i32* @a
   %x42 = add i32 %x41, %a42
-  %a43 = load volatile i32* @a
+  %a43 = load volatile i32, i32* @a
   %x43 = add i32 %x42, %a43
-  %a44 = load volatile i32* @a
+  %a44 = load volatile i32, i32* @a
   %x44 = add i32 %x43, %a44
-  %a45 = load volatile i32* @a
+  %a45 = load volatile i32, i32* @a
   %x45 = add i32 %x44, %a45
-  %a46 = load volatile i32* @a
+  %a46 = load volatile i32, i32* @a
   %x46 = add i32 %x45, %a46
-  %a47 = load volatile i32* @a
+  %a47 = load volatile i32, i32* @a
   %x47 = add i32 %x46, %a47
-  %a48 = load volatile i32* @a
+  %a48 = load volatile i32, i32* @a
   %x48 = add i32 %x47, %a48
-  %a49 = load volatile i32* @a
+  %a49 = load volatile i32, i32* @a
   %x49 = add i32 %x48, %a49
-  %a50 = load volatile i32* @a
+  %a50 = load volatile i32, i32* @a
   %x50 = add i32 %x49, %a50
-  %a51 = load volatile i32* @a
+  %a51 = load volatile i32, i32* @a
   %x51 = add i32 %x50, %a51
-  %a52 = load volatile i32* @a
+  %a52 = load volatile i32, i32* @a
   %x52 = add i32 %x51, %a52
 
   %add = add i32 %x52, %a
diff --git a/test/Transforms/Inline/inline-fast-math-flags.ll b/test/Transforms/Inline/inline-fast-math-flags.ll
new file mode 100644
index 000000000000..e5ff8f7bfe2b
--- /dev/null
+++ b/test/Transforms/Inline/inline-fast-math-flags.ll
@@ -0,0 +1,34 @@
+; RUN: opt < %s -S -inline -inline-threshold=20 | FileCheck %s
+; Check that we don't drop FastMathFlag when estimating inlining profitability.
+;
+; In this test we should inline 'foo'  to 'boo', because it'll fold to a
+; constant.
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+
+define float @foo(float* %a, float %b) {
+entry:
+  %a0 = load float, float* %a, align 4
+  %mul = fmul fast float %a0, %b
+  %tobool = fcmp une float %mul, 0.000000e+00
+  br i1 %tobool, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %a1 = load float, float* %a, align 8
+  %arrayidx1 = getelementptr inbounds float, float* %a, i64 1
+  %a2 = load float, float* %arrayidx1, align 4
+  %add = fadd fast float %a1, %a2
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  %storemerge = phi float [ %add, %if.then ], [ 1.000000e+00, %entry ]
+  ret float %storemerge
+}
+
+; CHECK-LABEL: @boo
+; CHECK-NOT: call float @foo
+define float @boo(float* %a) {
+entry:
+  %call = call float @foo(float* %a, float 0.000000e+00)
+  ret float %call
+}
diff --git a/test/Transforms/Inline/inline-fp.ll b/test/Transforms/Inline/inline-fp.ll
new file mode 100644
index 000000000000..cf42d82379a2
--- /dev/null
+++ b/test/Transforms/Inline/inline-fp.ll
@@ -0,0 +1,136 @@
+; RUN: opt -S -inline < %s | FileCheck %s
+; Make sure that soft float implementations are calculated as being more expensive
+; to the inliner.
+
+define i32 @test_nofp() #0 {
+; f_nofp() has the "use-soft-float" attribute, so it should never get inlined.
+; CHECK-LABEL: test_nofp
+; CHECK: call float @f_nofp 
+entry:
+  %responseX = alloca i32, align 4
+  %responseY = alloca i32, align 4
+  %responseZ = alloca i32, align 4
+  %valueX = alloca i8, align 1
+  %valueY = alloca i8, align 1
+  %valueZ = alloca i8, align 1
+
+  call void @getX(i32* %responseX, i8* %valueX)
+  call void @getY(i32* %responseY, i8* %valueY)
+  call void @getZ(i32* %responseZ, i8* %valueZ)
+
+  %0 = load i32, i32* %responseX
+  %1 = load i8, i8* %valueX
+  %call = call float @f_nofp(i32 %0, i8 zeroext %1)
+  %2 = load i32, i32* %responseZ
+  %3 = load i8, i8* %valueZ
+  %call2 = call float @f_nofp(i32 %2, i8 zeroext %3)
+  %call3 = call float @fabsf(float %call)
+  %cmp = fcmp ogt float %call3, 0x3FC1EB8520000000
+  br i1 %cmp, label %if.end12, label %if.else
+
+if.else:                                          ; preds = %entry
+  %4 = load i32, i32* %responseY
+  %5 = load i8, i8* %valueY
+  %call1 = call float @f_nofp(i32 %4, i8 zeroext %5)
+  %call4 = call float @fabsf(float %call1)
+  %cmp5 = fcmp ogt float %call4, 0x3FC1EB8520000000
+  br i1 %cmp5, label %if.end12, label %if.else7
+
+if.else7:                                         ; preds = %if.else
+  %call8 = call float @fabsf(float %call2)
+  %cmp9 = fcmp ogt float %call8, 0x3FC1EB8520000000
+  br i1 %cmp9, label %if.then10, label %if.end12
+
+if.then10:                                        ; preds = %if.else7
+  br label %if.end12
+
+if.end12:                                         ; preds = %if.else, %entry, %if.then10, %if.else7
+  %success.0 = phi i32 [ 0, %if.then10 ], [ 1, %if.else7 ], [ 0, %entry ], [ 0, %if.else ]
+  ret i32 %success.0
+}
+
+define i32 @test_hasfp() #0 {
+; f_hasfp()  does not have the "use-soft-float" attribute, so it should get inlined.
+; CHECK-LABEL: test_hasfp
+; CHECK-NOT: call float @f_hasfp 
+entry:
+  %responseX = alloca i32, align 4
+  %responseY = alloca i32, align 4
+  %responseZ = alloca i32, align 4
+  %valueX = alloca i8, align 1
+  %valueY = alloca i8, align 1
+  %valueZ = alloca i8, align 1
+
+  call void @getX(i32* %responseX, i8* %valueX)
+  call void @getY(i32* %responseY, i8* %valueY)
+  call void @getZ(i32* %responseZ, i8* %valueZ)
+
+  %0 = load i32, i32* %responseX
+  %1 = load i8, i8* %valueX
+  %call = call float @f_hasfp(i32 %0, i8 zeroext %1)
+  %2 = load i32, i32* %responseZ
+  %3 = load i8, i8* %valueZ
+  %call2 = call float @f_hasfp(i32 %2, i8 zeroext %3)
+  %call3 = call float @fabsf(float %call)
+  %cmp = fcmp ogt float %call3, 0x3FC1EB8520000000
+  br i1 %cmp, label %if.end12, label %if.else
+
+if.else:                                          ; preds = %entry
+  %4 = load i32, i32* %responseY
+  %5 = load i8, i8* %valueY
+  %call1 = call float @f_hasfp(i32 %4, i8 zeroext %5)
+  %call4 = call float @fabsf(float %call1)
+  %cmp5 = fcmp ogt float %call4, 0x3FC1EB8520000000
+  br i1 %cmp5, label %if.end12, label %if.else7
+
+if.else7:                                         ; preds = %if.else
+  %call8 = call float @fabsf(float %call2)
+  %cmp9 = fcmp ogt float %call8, 0x3FC1EB8520000000
+  br i1 %cmp9, label %if.then10, label %if.end12
+
+if.then10:                                        ; preds = %if.else7
+  br label %if.end12
+
+if.end12:                                         ; preds = %if.else, %entry, %if.then10, %if.else7
+  %success.0 = phi i32 [ 0, %if.then10 ], [ 1, %if.else7 ], [ 0, %entry ], [ 0, %if.else ]
+  ret i32 %success.0
+}
+
+declare void @getX(i32*, i8*) #0
+
+declare void @getY(i32*, i8*) #0
+
+declare void @getZ(i32*, i8*) #0
+
+define internal float @f_hasfp(i32 %response, i8 zeroext %value1) #0 {
+entry:
+  %conv = zext i8 %value1 to i32
+  %sub = add nsw i32 %conv, -1
+  %conv1 = sitofp i32 %sub to float
+  %0 = tail call float @llvm.pow.f32(float 0x3FF028F5C0000000, float %conv1)
+  %mul = fmul float %0, 2.620000e+03
+  %conv2 = sitofp i32 %response to float
+  %sub3 = fsub float %conv2, %mul
+  %div = fdiv float %sub3, %mul
+  ret float %div
+}
+
+define internal float @f_nofp(i32 %response, i8 zeroext %value1) #1 {
+entry:
+  %conv = zext i8 %value1 to i32
+  %sub = add nsw i32 %conv, -1
+  %conv1 = sitofp i32 %sub to float
+  %0 = tail call float @llvm.pow.f32(float 0x3FF028F5C0000000, float %conv1)
+  %mul = fmul float %0, 2.620000e+03
+  %conv2 = sitofp i32 %response to float
+  %sub3 = fsub float %conv2, %mul
+  %div = fdiv float %sub3, %mul
+  ret float %div
+}
+
+declare float @fabsf(float) optsize minsize
+
+declare float @llvm.pow.f32(float, float) optsize minsize
+
+attributes #0 = { minsize optsize }
+attributes #1 = { minsize optsize "use-soft-float"="true" }
diff --git a/test/Transforms/Inline/inline-invoke-tail.ll b/test/Transforms/Inline/inline-invoke-tail.ll
index e07752396a30..5fef4baee9e6 100644
--- a/test/Transforms/Inline/inline-invoke-tail.ll
+++ b/test/Transforms/Inline/inline-invoke-tail.ll
@@ -19,7 +19,7 @@ define i32 @main() {
 			to label %invcont unwind label %lpad
 
 invcont:
-	%retval = load i32* %a, align 4
+	%retval = load i32, i32* %a, align 4
 	ret i32 %retval
 
 lpad:
diff --git a/test/Transforms/Inline/inline-musttail-varargs.ll b/test/Transforms/Inline/inline-musttail-varargs.ll
index 7a8957488e1c..e93ef763aeff 100644
--- a/test/Transforms/Inline/inline-musttail-varargs.ll
+++ b/test/Transforms/Inline/inline-musttail-varargs.ll
@@ -6,17 +6,17 @@
 declare void @ext_method(i8*, i32)
 
 define linkonce_odr void @thunk(i8* %this, ...) {
-  %this_adj = getelementptr i8* %this, i32 4
-  musttail call void (i8*, ...)* bitcast (void (i8*, i32)* @ext_method to void (i8*, ...)*)(i8* %this_adj, ...)
+  %this_adj = getelementptr i8, i8* %this, i32 4
+  musttail call void (i8*, ...) bitcast (void (i8*, i32)* @ext_method to void (i8*, ...)*)(i8* %this_adj, ...)
   ret void
 }
 
 define void @thunk_caller(i8* %p) {
-  call void (i8*, ...)* @thunk(i8* %p, i32 42)
+  call void (i8*, ...) @thunk(i8* %p, i32 42)
   ret void
 }
 ; CHECK-LABEL: define void @thunk_caller(i8* %p)
-; CHECK: call void (i8*, ...)* @thunk(i8* %p, i32 42)
+; CHECK: call void (i8*, ...) @thunk(i8* %p, i32 42)
 
 ; FIXME: Inline the thunk. This should be significantly easier than inlining
 ; general varargs functions.
diff --git a/test/Transforms/Inline/inline-optsize.ll b/test/Transforms/Inline/inline-optsize.ll
index 3ad573a04e42..820e56f7f8ef 100644
--- a/test/Transforms/Inline/inline-optsize.ll
+++ b/test/Transforms/Inline/inline-optsize.ll
@@ -11,15 +11,15 @@
 ; This function should be larger than the inline threshold for -Oz (25), but
 ; smaller than the inline threshold for optsize (75).
 define i32 @inner() {
-  %a1 = load volatile i32* @a
+  %a1 = load volatile i32, i32* @a
   %x1 = add i32 %a1,  %a1
-  %a2 = load volatile i32* @a
+  %a2 = load volatile i32, i32* @a
   %x2 = add i32 %x1, %a2
-  %a3 = load volatile i32* @a
+  %a3 = load volatile i32, i32* @a
   %x3 = add i32 %x2, %a3
-  %a4 = load volatile i32* @a
+  %a4 = load volatile i32, i32* @a
   %x4 = add i32 %x3, %a4
-  %a5 = load volatile i32* @a
+  %a5 = load volatile i32, i32* @a
   %x5 = add i32 %x3, %a5
   ret i32 %x5
 }
diff --git a/test/Transforms/Inline/inline-vla.ll b/test/Transforms/Inline/inline-vla.ll
index 7da448b83f3a..df21b3f30cff 100644
--- a/test/Transforms/Inline/inline-vla.ll
+++ b/test/Transforms/Inline/inline-vla.ll
@@ -10,9 +10,9 @@
 define i32 @main(i32 %argc, i8** nocapture readnone %argv) #0 {
 entry:
   %data = alloca [2 x i8], align 1
-  %arraydecay = getelementptr inbounds [2 x i8]* %data, i64 0, i64 0
-  call fastcc void @memcpy2(i8* %arraydecay, i8* getelementptr inbounds ([2 x i8]* @.str, i64 0, i64 0), i64 1)
-  call fastcc void @memcpy2(i8* %arraydecay, i8* getelementptr inbounds ([3 x i8]* @.str1, i64 0, i64 0), i64 2)
+  %arraydecay = getelementptr inbounds [2 x i8], [2 x i8]* %data, i64 0, i64 0
+  call fastcc void @memcpy2(i8* %arraydecay, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i64 0, i64 0), i64 1)
+  call fastcc void @memcpy2(i8* %arraydecay, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str1, i64 0, i64 0), i64 2)
   ret i32 0
 }
 
diff --git a/test/Transforms/Inline/inline_constprop.ll b/test/Transforms/Inline/inline_constprop.ll
index b59a270468e0..de23b6157a71 100644
--- a/test/Transforms/Inline/inline_constprop.ll
+++ b/test/Transforms/Inline/inline_constprop.ll
@@ -267,8 +267,8 @@ entry:
   br i1 %cmp, label %if.then, label %if.end3
 
 if.then:
-  %0 = load i32* %a
-  %1 = load i32* %b
+  %0 = load i32, i32* %a
+  %1 = load i32, i32* %b
   %cmp1 = icmp eq i32 %0, %1
   br i1 %cmp1, label %return, label %if.end3
 
diff --git a/test/Transforms/Inline/inline_dbg_declare.ll b/test/Transforms/Inline/inline_dbg_declare.ll
index 563cde314160..f3ad7ef8b8fc 100644
--- a/test/Transforms/Inline/inline_dbg_declare.ll
+++ b/test/Transforms/Inline/inline_dbg_declare.ll
@@ -1,96 +1,99 @@
-; RUN: opt < %s -S -inline | FileCheck %s

-;

-; The purpose of this test is to check that inline pass preserves debug info

-; for variable using the dbg.declare intrinsic.

-;

-;; This test was generated by running this command:

-;; clang.exe -S -O0 -emit-llvm -g foo.c

-;;

-;; foo.c

-;; ==========================

-;; float foo(float x)

-;; {

-;;    return x;

-;; }

-;;

-;; void bar(float *dst)

-;; {

-;;    dst[0] = foo(dst[0]);

-;; }

-;; ==========================

-

-target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"

-target triple = "i686-pc-windows-msvc"

-

-; Function Attrs: nounwind

-define float @foo(float %x) #0 {

-entry:

-  %x.addr = alloca float, align 4

-  store float %x, float* %x.addr, align 4

-  call void @llvm.dbg.declare(metadata float* %x.addr, metadata !16, metadata !17), !dbg !18

-  %0 = load float* %x.addr, align 4, !dbg !19

-  ret float %0, !dbg !19

-}

-

-; Function Attrs: nounwind readnone

-declare void @llvm.dbg.declare(metadata, metadata, metadata) #1

-

-; CHECK: define void @bar

-

-; Function Attrs: nounwind

-define void @bar(float* %dst) #0 {

-entry:

-

-; CHECK: [[x_addr_i:%[a-zA-Z0-9.]+]] = alloca float, align 4

-

-  %dst.addr = alloca float*, align 4

-  store float* %dst, float** %dst.addr, align 4

-  call void @llvm.dbg.declare(metadata float** %dst.addr, metadata !20, metadata !17), !dbg !21

-  %0 = load float** %dst.addr, align 4, !dbg !22

-  %arrayidx = getelementptr inbounds float* %0, i32 0, !dbg !22

-  %1 = load float* %arrayidx, align 4, !dbg !22

-  %call = call float @foo(float %1), !dbg !22

-

-; CHECK-NOT: call float @foo

-; CHECK: void @llvm.dbg.declare(metadata float* [[x_addr_i]], metadata [[m23:![0-9]+]], metadata !17), !dbg [[m24:![0-9]+]]

-

-  %2 = load float** %dst.addr, align 4, !dbg !22

-  %arrayidx1 = getelementptr inbounds float* %2, i32 0, !dbg !22

-  store float %call, float* %arrayidx1, align 4, !dbg !22

-  ret void, !dbg !23

-}

-

-attributes #0 = { nounwind }

-attributes #1 = { nounwind readnone }

-

-!llvm.dbg.cu = !{!0}

-!llvm.module.flags = !{!13, !14}

-!llvm.ident = !{!15}

-

-!0 = !{!"0x11\0012\00clang version 3.6.0 (trunk)\000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [foo.c] [DW_LANG_C99]

-!1 = !{!"foo.c", !""}

-!2 = !{}

-!3 = !{!4, !9}

-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\000\00256\000\002", !1, !5, !6, null, float (float)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [scope 2] [foo]

-!5 = !{!"0x29", !1}    ; [ DW_TAG_file_type ] [foo.c]

-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]

-!7 = !{!8, !8}

-!8 = !{!"0x24\00float\000\0032\0032\000\000\004", null, null} ; [ DW_TAG_base_type ] [float] [line 0, size 32, align 32, offset 0, enc DW_ATE_float]

-!9 = !{!"0x2e\00bar\00bar\00\006\000\001\000\000\00256\000\007", !1, !5, !10, null, void (float*)* @bar, null, null, !2} ; [ DW_TAG_subprogram ] [line 6] [def] [scope 7] [bar]

-!10 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]

-!11 = !{null, !12}

-!12 = !{!"0xf\00\000\0032\0032\000\000", null, null, !8} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from float]

-!13 = !{i32 2, !"Dwarf Version", i32 4}

-!14 = !{i32 2, !"Debug Info Version", i32 2}

-!15 = !{!"clang version 3.6.0 (trunk)"}

-!16 = !{!"0x101\00x\0016777217\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [x] [line 1]

-!17 = !{!"0x102"}               ; [ DW_TAG_expression ]

-!18 = !MDLocation(line: 1, column: 17, scope: !4)

-!19 = !MDLocation(line: 3, column: 5, scope: !4)

-!20 = !{!"0x101\00dst\0016777222\000", !9, !5, !12} ; [ DW_TAG_arg_variable ] [dst] [line 6]

-!21 = !MDLocation(line: 6, column: 17, scope: !9)

-!22 = !MDLocation(line: 8, column: 14, scope: !9)

-!23 = !MDLocation(line: 9, column: 1, scope: !9)

-

-; CHECK: [[m23]] = !{!"0x101\00x\0016777217\000", !4, !5, !8, !22} ; [ DW_TAG_arg_variable ] [x] [line 1]

-; CHECK: [[m24]] = !MDLocation(line: 1, column: 17, scope: !4, inlinedAt: !22)

+; RUN: opt < %s -S -inline | FileCheck %s
+;
+; The purpose of this test is to check that inline pass preserves debug info
+; for variable using the dbg.declare intrinsic.
+;
+;; This test was generated by running this command:
+;; clang.exe -S -O0 -emit-llvm -g foo.c
+;;
+;; foo.c
+;; ==========================
+;; float foo(float x)
+;; {
+;;    return x;
+;; }
+;;
+;; void bar(float *dst)
+;; {
+;;    dst[0] = foo(dst[0]);
+;; }
+;; ==========================
+
+target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"
+target triple = "i686-pc-windows-msvc"
+
+; Function Attrs: nounwind
+define float @foo(float %x) #0 {
+entry:
+  %x.addr = alloca float, align 4
+  store float %x, float* %x.addr, align 4
+  call void @llvm.dbg.declare(metadata float* %x.addr, metadata !16, metadata !17), !dbg !18
+  %0 = load float, float* %x.addr, align 4, !dbg !19
+  ret float %0, !dbg !19
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+; CHECK: define void @bar
+
+; Function Attrs: nounwind
+define void @bar(float* %dst) #0 {
+entry:
+
+; CHECK: [[x_addr_i:%[a-zA-Z0-9.]+]] = alloca float, align 4
+
+  %dst.addr = alloca float*, align 4
+  store float* %dst, float** %dst.addr, align 4
+  call void @llvm.dbg.declare(metadata float** %dst.addr, metadata !20, metadata !17), !dbg !21
+  %0 = load float*, float** %dst.addr, align 4, !dbg !22
+  %arrayidx = getelementptr inbounds float, float* %0, i32 0, !dbg !22
+  %1 = load float, float* %arrayidx, align 4, !dbg !22
+  %call = call float @foo(float %1), !dbg !22
+
+; CHECK-NOT: call float @foo
+; CHECK: void @llvm.dbg.declare(metadata float* [[x_addr_i]], metadata [[m23:![0-9]+]], metadata !{{[0-9]+}}), !dbg [[m24:![0-9]+]]
+
+  %2 = load float*, float** %dst.addr, align 4, !dbg !22
+  %arrayidx1 = getelementptr inbounds float, float* %2, i32 0, !dbg !22
+  store float %call, float* %arrayidx1, align 4, !dbg !22
+  ret void, !dbg !23
+}
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!13, !14}
+!llvm.ident = !{!15}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.6.0 (trunk)", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "foo.c", directory: "")
+!2 = !{}
+!3 = !{!4, !9}
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 2, file: !1, scope: !5, type: !6, function: float (float)* @foo, variables: !2)
+!5 = !DIFile(filename: "foo.c", directory: "")
+!6 = !DISubroutineType(types: !7)
+!7 = !{!8, !8}
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float)
+!9 = !DISubprogram(name: "bar", line: 6, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !1, scope: !5, type: !10, function: void (float*)* @bar, variables: !2)
+!10 = !DISubroutineType(types: !11)
+!11 = !{null, !12}
+!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !8)
+!13 = !{i32 2, !"Dwarf Version", i32 4}
+!14 = !{i32 2, !"Debug Info Version", i32 3}
+!15 = !{!"clang version 3.6.0 (trunk)"}
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 1, arg: 1, scope: !4, file: !5, type: !8)
+!17 = !DIExpression()
+!18 = !DILocation(line: 1, column: 17, scope: !4)
+!19 = !DILocation(line: 3, column: 5, scope: !4)
+!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "dst", line: 6, arg: 1, scope: !9, file: !5, type: !12)
+!21 = !DILocation(line: 6, column: 17, scope: !9)
+!22 = !DILocation(line: 8, column: 14, scope: !9)
+!23 = !DILocation(line: 9, column: 1, scope: !9)
+
+; CHECK: [[FOO:![0-9]+]] = !DISubprogram(name: "foo",
+; CHECK: [[BAR:![0-9]+]] = !DISubprogram(name: "bar",
+; CHECK: [[m23]] = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", arg: 1, scope: [[FOO]]
+; CHECK: [[CALL_SITE:![0-9]+]] = distinct !DILocation(line: 8, column: 14, scope: [[BAR]])
+; CHECK: [[m24]] = !DILocation(line: 1, column: 17, scope: [[FOO]], inlinedAt: [[CALL_SITE]])
diff --git a/test/Transforms/Inline/inline_minisize.ll b/test/Transforms/Inline/inline_minisize.ll
index b9aad6083399..0bf75d72bd13 100644
--- a/test/Transforms/Inline/inline_minisize.ll
+++ b/test/Transforms/Inline/inline_minisize.ll
@@ -8,17 +8,17 @@ entry:
   %res = alloca i32, align 4
   %i = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
-  %tmp = load i32* %a.addr, align 4
+  %tmp = load i32, i32* %a.addr, align 4
   %idxprom = sext i32 %tmp to i64
-  %tmp1 = load i32** @data, align 8
-  %arrayidx = getelementptr inbounds i32* %tmp1, i64 %idxprom
-  %tmp2 = load i32* %arrayidx, align 4
-  %tmp3 = load i32* %a.addr, align 4
+  %tmp1 = load i32*, i32** @data, align 8
+  %arrayidx = getelementptr inbounds i32, i32* %tmp1, i64 %idxprom
+  %tmp2 = load i32, i32* %arrayidx, align 4
+  %tmp3 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %tmp3, 1
   %idxprom1 = sext i32 %add to i64
-  %tmp4 = load i32** @data, align 8
-  %arrayidx2 = getelementptr inbounds i32* %tmp4, i64 %idxprom1
-  %tmp5 = load i32* %arrayidx2, align 4
+  %tmp4 = load i32*, i32** @data, align 8
+  %arrayidx2 = getelementptr inbounds i32, i32* %tmp4, i64 %idxprom1
+  %tmp5 = load i32, i32* %arrayidx2, align 4
   %mul = mul nsw i32 %tmp2, %tmp5
   store i32 %mul, i32* %res, align 4
   store i32 0, i32* %i, align 4
@@ -26,21 +26,21 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %tmp6 = load i32* %i, align 4
-  %tmp7 = load i32* %res, align 4
+  %tmp6 = load i32, i32* %i, align 4
+  %tmp7 = load i32, i32* %res, align 4
   %cmp = icmp slt i32 %tmp6, %tmp7
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %tmp8 = load i32* %i, align 4
+  %tmp8 = load i32, i32* %i, align 4
   %idxprom3 = sext i32 %tmp8 to i64
-  %tmp9 = load i32** @data, align 8
-  %arrayidx4 = getelementptr inbounds i32* %tmp9, i64 %idxprom3
+  %tmp9 = load i32*, i32** @data, align 8
+  %arrayidx4 = getelementptr inbounds i32, i32* %tmp9, i64 %idxprom3
   call void @fct0(i32* %arrayidx4)
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %tmp10 = load i32* %i, align 4
+  %tmp10 = load i32, i32* %i, align 4
   %inc = add nsw i32 %tmp10, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
@@ -50,21 +50,21 @@ for.end:                                          ; preds = %for.cond
   br label %for.cond5
 
 for.cond5:                                        ; preds = %for.inc10, %for.end
-  %tmp11 = load i32* %i, align 4
-  %tmp12 = load i32* %res, align 4
+  %tmp11 = load i32, i32* %i, align 4
+  %tmp12 = load i32, i32* %res, align 4
   %cmp6 = icmp slt i32 %tmp11, %tmp12
   br i1 %cmp6, label %for.body7, label %for.end12
 
 for.body7:                                        ; preds = %for.cond5
-  %tmp13 = load i32* %i, align 4
+  %tmp13 = load i32, i32* %i, align 4
   %idxprom8 = sext i32 %tmp13 to i64
-  %tmp14 = load i32** @data, align 8
-  %arrayidx9 = getelementptr inbounds i32* %tmp14, i64 %idxprom8
+  %tmp14 = load i32*, i32** @data, align 8
+  %arrayidx9 = getelementptr inbounds i32, i32* %tmp14, i64 %idxprom8
   call void @fct0(i32* %arrayidx9)
   br label %for.inc10
 
 for.inc10:                                        ; preds = %for.body7
-  %tmp15 = load i32* %i, align 4
+  %tmp15 = load i32, i32* %i, align 4
   %inc11 = add nsw i32 %tmp15, 1
   store i32 %inc11, i32* %i, align 4
   br label %for.cond5
@@ -74,27 +74,27 @@ for.end12:                                        ; preds = %for.cond5
   br label %for.cond13
 
 for.cond13:                                       ; preds = %for.inc18, %for.end12
-  %tmp16 = load i32* %i, align 4
-  %tmp17 = load i32* %res, align 4
+  %tmp16 = load i32, i32* %i, align 4
+  %tmp17 = load i32, i32* %res, align 4
   %cmp14 = icmp slt i32 %tmp16, %tmp17
   br i1 %cmp14, label %for.body15, label %for.end20
 
 for.body15:                                       ; preds = %for.cond13
-  %tmp18 = load i32* %i, align 4
+  %tmp18 = load i32, i32* %i, align 4
   %idxprom16 = sext i32 %tmp18 to i64
-  %tmp19 = load i32** @data, align 8
-  %arrayidx17 = getelementptr inbounds i32* %tmp19, i64 %idxprom16
+  %tmp19 = load i32*, i32** @data, align 8
+  %arrayidx17 = getelementptr inbounds i32, i32* %tmp19, i64 %idxprom16
   call void @fct0(i32* %arrayidx17)
   br label %for.inc18
 
 for.inc18:                                        ; preds = %for.body15
-  %tmp20 = load i32* %i, align 4
+  %tmp20 = load i32, i32* %i, align 4
   %inc19 = add nsw i32 %tmp20, 1
   store i32 %inc19, i32* %i, align 4
   br label %for.cond13
 
 for.end20:                                        ; preds = %for.cond13
-  %tmp21 = load i32* %res, align 4
+  %tmp21 = load i32, i32* %res, align 4
   ret i32 %tmp21
 }
 
@@ -106,19 +106,19 @@ entry:
   %res = alloca i32, align 4
   %i = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
-  %tmp = load i32* %a.addr, align 4
+  %tmp = load i32, i32* %a.addr, align 4
   %shl = shl i32 %tmp, 1
   %idxprom = sext i32 %shl to i64
-  %tmp1 = load i32** @data, align 8
-  %arrayidx = getelementptr inbounds i32* %tmp1, i64 %idxprom
-  %tmp2 = load i32* %arrayidx, align 4
-  %tmp3 = load i32* %a.addr, align 4
+  %tmp1 = load i32*, i32** @data, align 8
+  %arrayidx = getelementptr inbounds i32, i32* %tmp1, i64 %idxprom
+  %tmp2 = load i32, i32* %arrayidx, align 4
+  %tmp3 = load i32, i32* %a.addr, align 4
   %shl1 = shl i32 %tmp3, 1
   %add = add nsw i32 %shl1, 13
   %idxprom2 = sext i32 %add to i64
-  %tmp4 = load i32** @data, align 8
-  %arrayidx3 = getelementptr inbounds i32* %tmp4, i64 %idxprom2
-  %tmp5 = load i32* %arrayidx3, align 4
+  %tmp4 = load i32*, i32** @data, align 8
+  %arrayidx3 = getelementptr inbounds i32, i32* %tmp4, i64 %idxprom2
+  %tmp5 = load i32, i32* %arrayidx3, align 4
   %mul = mul nsw i32 %tmp2, %tmp5
   store i32 %mul, i32* %res, align 4
   store i32 0, i32* %i, align 4
@@ -126,21 +126,21 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %tmp6 = load i32* %i, align 4
-  %tmp7 = load i32* %res, align 4
+  %tmp6 = load i32, i32* %i, align 4
+  %tmp7 = load i32, i32* %res, align 4
   %cmp = icmp slt i32 %tmp6, %tmp7
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %tmp8 = load i32* %i, align 4
+  %tmp8 = load i32, i32* %i, align 4
   %idxprom4 = sext i32 %tmp8 to i64
-  %tmp9 = load i32** @data, align 8
-  %arrayidx5 = getelementptr inbounds i32* %tmp9, i64 %idxprom4
+  %tmp9 = load i32*, i32** @data, align 8
+  %arrayidx5 = getelementptr inbounds i32, i32* %tmp9, i64 %idxprom4
   call void @fct0(i32* %arrayidx5)
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %tmp10 = load i32* %i, align 4
+  %tmp10 = load i32, i32* %i, align 4
   %inc = add nsw i32 %tmp10, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
@@ -150,21 +150,21 @@ for.end:                                          ; preds = %for.cond
   br label %for.cond6
 
 for.cond6:                                        ; preds = %for.inc11, %for.end
-  %tmp11 = load i32* %i, align 4
-  %tmp12 = load i32* %res, align 4
+  %tmp11 = load i32, i32* %i, align 4
+  %tmp12 = load i32, i32* %res, align 4
   %cmp7 = icmp slt i32 %tmp11, %tmp12
   br i1 %cmp7, label %for.body8, label %for.end13
 
 for.body8:                                        ; preds = %for.cond6
-  %tmp13 = load i32* %i, align 4
+  %tmp13 = load i32, i32* %i, align 4
   %idxprom9 = sext i32 %tmp13 to i64
-  %tmp14 = load i32** @data, align 8
-  %arrayidx10 = getelementptr inbounds i32* %tmp14, i64 %idxprom9
+  %tmp14 = load i32*, i32** @data, align 8
+  %arrayidx10 = getelementptr inbounds i32, i32* %tmp14, i64 %idxprom9
   call void @fct0(i32* %arrayidx10)
   br label %for.inc11
 
 for.inc11:                                        ; preds = %for.body8
-  %tmp15 = load i32* %i, align 4
+  %tmp15 = load i32, i32* %i, align 4
   %inc12 = add nsw i32 %tmp15, 1
   store i32 %inc12, i32* %i, align 4
   br label %for.cond6
@@ -174,27 +174,27 @@ for.end13:                                        ; preds = %for.cond6
   br label %for.cond14
 
 for.cond14:                                       ; preds = %for.inc19, %for.end13
-  %tmp16 = load i32* %i, align 4
-  %tmp17 = load i32* %res, align 4
+  %tmp16 = load i32, i32* %i, align 4
+  %tmp17 = load i32, i32* %res, align 4
   %cmp15 = icmp slt i32 %tmp16, %tmp17
   br i1 %cmp15, label %for.body16, label %for.end21
 
 for.body16:                                       ; preds = %for.cond14
-  %tmp18 = load i32* %i, align 4
+  %tmp18 = load i32, i32* %i, align 4
   %idxprom17 = sext i32 %tmp18 to i64
-  %tmp19 = load i32** @data, align 8
-  %arrayidx18 = getelementptr inbounds i32* %tmp19, i64 %idxprom17
+  %tmp19 = load i32*, i32** @data, align 8
+  %arrayidx18 = getelementptr inbounds i32, i32* %tmp19, i64 %idxprom17
   call void @fct0(i32* %arrayidx18)
   br label %for.inc19
 
 for.inc19:                                        ; preds = %for.body16
-  %tmp20 = load i32* %i, align 4
+  %tmp20 = load i32, i32* %i, align 4
   %inc20 = add nsw i32 %tmp20, 1
   store i32 %inc20, i32* %i, align 4
   br label %for.cond14
 
 for.end21:                                        ; preds = %for.cond14
-  %tmp21 = load i32* %res, align 4
+  %tmp21 = load i32, i32* %res, align 4
   ret i32 %tmp21
 }
 
@@ -206,9 +206,9 @@ entry:
   ;CHECK-NOT: call i32 @fct2
   %c.addr = alloca i32, align 4
   store i32 %c, i32* %c.addr, align 4
-  %tmp = load i32* %c.addr, align 4
+  %tmp = load i32, i32* %c.addr, align 4
   %call = call i32 @fct1(i32 %tmp)
-  %tmp1 = load i32* %c.addr, align 4
+  %tmp1 = load i32, i32* %c.addr, align 4
   %call1 = call i32 @fct2(i32 %tmp1)
   %add = add nsw i32 %call, %call1
   ret i32 %add
@@ -223,9 +223,9 @@ entry:
   ;CHECK: call i32 @fct2
   %c.addr = alloca i32, align 4
   store i32 %c, i32* %c.addr, align 4
-  %tmp = load i32* %c.addr, align 4
+  %tmp = load i32, i32* %c.addr, align 4
   %call = call i32 @fct1(i32 %tmp)
-  %tmp1 = load i32* %c.addr, align 4
+  %tmp1 = load i32, i32* %c.addr, align 4
   %call1 = call i32 @fct2(i32 %tmp1)
   %add = add nsw i32 %call, %call1
   ret i32 %add
diff --git a/test/Transforms/Inline/inline_ssp.ll b/test/Transforms/Inline/inline_ssp.ll
index a4b43a77bad2..1a077230da09 100644
--- a/test/Transforms/Inline/inline_ssp.ll
+++ b/test/Transforms/Inline/inline_ssp.ll
@@ -13,25 +13,25 @@
 ;  sspreq > sspstrong > ssp > [no ssp]
 define internal void @fun_sspreq() nounwind sspreq uwtable {
 entry:
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str3, i32 0, i32 0))
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str3, i32 0, i32 0))
   ret void
 }
 
 define internal void @fun_sspstrong() nounwind sspstrong uwtable {
 entry:
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([15 x i8]* @.str2, i32 0, i32 0))
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @.str2, i32 0, i32 0))
   ret void
 }
 
 define internal void @fun_ssp() nounwind ssp uwtable {
 entry:
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str1, i32 0, i32 0))
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str1, i32 0, i32 0))
   ret void
 }
 
 define internal void @fun_nossp() nounwind uwtable {
 entry:
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0))
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0))
   ret void
 }
 
diff --git a/test/Transforms/Inline/invoke-combine-clauses.ll b/test/Transforms/Inline/invoke-combine-clauses.ll
index 5f06039b9edc..89a4cc951c7a 100644
--- a/test/Transforms/Inline/invoke-combine-clauses.ll
+++ b/test/Transforms/Inline/invoke-combine-clauses.ll
@@ -20,7 +20,7 @@ cont:
 lpad:
   %lp = landingpad i32 personality i8* null
       catch i8* @exception_inner
-  %cond = load i1* @condition
+  %cond = load i1, i1* @condition
   br i1 %cond, label %resume1, label %resume2
 resume1:
   resume i32 1
diff --git a/test/Transforms/Inline/lifetime-no-datalayout.ll b/test/Transforms/Inline/lifetime-no-datalayout.ll
index 5abb77f2c3fc..4307064e1946 100644
--- a/test/Transforms/Inline/lifetime-no-datalayout.ll
+++ b/test/Transforms/Inline/lifetime-no-datalayout.ll
@@ -8,13 +8,13 @@ define void @helper() {
   ret void
 }
 
-; Size in llvm.lifetime.X should be -1 (unknown).
+; Size in llvm.lifetime.X should be 1 (default for i8).
 define void @test() {
 ; CHECK-LABEL: @test(
 ; CHECK-NOT: lifetime
-; CHECK: llvm.lifetime.start(i64 -1
+; CHECK: llvm.lifetime.start(i64 1
 ; CHECK-NOT: lifetime
-; CHECK: llvm.lifetime.end(i64 -1
+; CHECK: llvm.lifetime.end(i64 1
   call void @helper()
 ; CHECK-NOT: lifetime
 ; CHECK: ret void
diff --git a/test/Transforms/Inline/noalias-cs.ll b/test/Transforms/Inline/noalias-cs.ll
index da5ddd64ed06..0bff1882e832 100644
--- a/test/Transforms/Inline/noalias-cs.ll
+++ b/test/Transforms/Inline/noalias-cs.ll
@@ -5,13 +5,13 @@ target triple = "x86_64-unknown-linux-gnu"
 ; Function Attrs: nounwind uwtable
 define void @foo2(float* nocapture %a, float* nocapture %b, float* nocapture readonly %c) #0 {
 entry:
-  %0 = load float* %c, align 4, !noalias !3
-  %arrayidx.i = getelementptr inbounds float* %a, i64 5
+  %0 = load float, float* %c, align 4, !noalias !3
+  %arrayidx.i = getelementptr inbounds float, float* %a, i64 5
   store float %0, float* %arrayidx.i, align 4, !alias.scope !7, !noalias !8
-  %arrayidx1.i = getelementptr inbounds float* %b, i64 8
+  %arrayidx1.i = getelementptr inbounds float, float* %b, i64 8
   store float %0, float* %arrayidx1.i, align 4, !alias.scope !8, !noalias !7
-  %1 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 7
+  %1 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 7
   store float %1, float* %arrayidx, align 4
   ret void
 }
@@ -25,22 +25,22 @@ entry:
 
 ; CHECK: define void @foo(float* nocapture %a, float* nocapture %b, float* nocapture readonly %c) #0 {
 ; CHECK: entry:
-; CHECK:   %0 = load float* %c, align 4, !noalias !6
-; CHECK:   %arrayidx.i.i = getelementptr inbounds float* %a, i64 5
+; CHECK:   %0 = load float, float* %c, align 4, !noalias !6
+; CHECK:   %arrayidx.i.i = getelementptr inbounds float, float* %a, i64 5
 ; CHECK:   store float %0, float* %arrayidx.i.i, align 4, !alias.scope !12, !noalias !13
-; CHECK:   %arrayidx1.i.i = getelementptr inbounds float* %b, i64 8
+; CHECK:   %arrayidx1.i.i = getelementptr inbounds float, float* %b, i64 8
 ; CHECK:   store float %0, float* %arrayidx1.i.i, align 4, !alias.scope !14, !noalias !15
-; CHECK:   %1 = load float* %c, align 4, !noalias !16
-; CHECK:   %arrayidx.i = getelementptr inbounds float* %a, i64 7
+; CHECK:   %1 = load float, float* %c, align 4, !noalias !16
+; CHECK:   %arrayidx.i = getelementptr inbounds float, float* %a, i64 7
 ; CHECK:   store float %1, float* %arrayidx.i, align 4, !noalias !16
-; CHECK:   %2 = load float* %a, align 4, !alias.scope !16, !noalias !17
-; CHECK:   %arrayidx.i.i1 = getelementptr inbounds float* %b, i64 5
-; CHECK:   store float %2, float* %arrayidx.i.i1, align 4, !alias.scope !21, !noalias !22
-; CHECK:   %arrayidx1.i.i2 = getelementptr inbounds float* %b, i64 8
-; CHECK:   store float %2, float* %arrayidx1.i.i2, align 4, !alias.scope !23, !noalias !24
-; CHECK:   %3 = load float* %a, align 4, !alias.scope !16
-; CHECK:   %arrayidx.i3 = getelementptr inbounds float* %b, i64 7
-; CHECK:   store float %3, float* %arrayidx.i3, align 4, !alias.scope !16
+; CHECK:   %2 = load float, float* %a, align 4, !alias.scope !16, !noalias !17
+; CHECK:   %arrayidx.i.i.1 = getelementptr inbounds float, float* %b, i64 5
+; CHECK:   store float %2, float* %arrayidx.i.i.1, align 4, !alias.scope !21, !noalias !22
+; CHECK:   %arrayidx1.i.i.2 = getelementptr inbounds float, float* %b, i64 8
+; CHECK:   store float %2, float* %arrayidx1.i.i.2, align 4, !alias.scope !23, !noalias !24
+; CHECK:   %3 = load float, float* %a, align 4, !alias.scope !16
+; CHECK:   %arrayidx.i.3 = getelementptr inbounds float, float* %b, i64 7
+; CHECK:   store float %3, float* %arrayidx.i.3, align 4, !alias.scope !16
 ; CHECK:   ret void
 ; CHECK: }
 
diff --git a/test/Transforms/Inline/noalias.ll b/test/Transforms/Inline/noalias.ll
index 674da1e2efbb..27e53afc2a75 100644
--- a/test/Transforms/Inline/noalias.ll
+++ b/test/Transforms/Inline/noalias.ll
@@ -4,8 +4,8 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define void @hello(float* noalias nocapture %a, float* nocapture readonly %c) #0 {
 entry:
-  %0 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 5
+  %0 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 5
   store float %0, float* %arrayidx, align 4
   ret void
 }
@@ -13,29 +13,29 @@ entry:
 define void @foo(float* nocapture %a, float* nocapture readonly %c) #0 {
 entry:
   tail call void @hello(float* %a, float* %c)
-  %0 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 7
+  %0 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 7
   store float %0, float* %arrayidx, align 4
   ret void
 }
 
 ; CHECK: define void @foo(float* nocapture %a, float* nocapture readonly %c) #0 {
 ; CHECK: entry:
-; CHECK:   %0 = load float* %c, align 4, !noalias !0
-; CHECK:   %arrayidx.i = getelementptr inbounds float* %a, i64 5
+; CHECK:   %0 = load float, float* %c, align 4, !noalias !0
+; CHECK:   %arrayidx.i = getelementptr inbounds float, float* %a, i64 5
 ; CHECK:   store float %0, float* %arrayidx.i, align 4, !alias.scope !0
-; CHECK:   %1 = load float* %c, align 4
-; CHECK:   %arrayidx = getelementptr inbounds float* %a, i64 7
+; CHECK:   %1 = load float, float* %c, align 4
+; CHECK:   %arrayidx = getelementptr inbounds float, float* %a, i64 7
 ; CHECK:   store float %1, float* %arrayidx, align 4
 ; CHECK:   ret void
 ; CHECK: }
 
 define void @hello2(float* noalias nocapture %a, float* noalias nocapture %b, float* nocapture readonly %c) #0 {
 entry:
-  %0 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 5
+  %0 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 5
   store float %0, float* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds float* %b, i64 8
+  %arrayidx1 = getelementptr inbounds float, float* %b, i64 8
   store float %0, float* %arrayidx1, align 4
   ret void
 }
@@ -43,21 +43,21 @@ entry:
 define void @foo2(float* nocapture %a, float* nocapture %b, float* nocapture readonly %c) #0 {
 entry:
   tail call void @hello2(float* %a, float* %b, float* %c)
-  %0 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 7
+  %0 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 7
   store float %0, float* %arrayidx, align 4
   ret void
 }
 
 ; CHECK: define void @foo2(float* nocapture %a, float* nocapture %b, float* nocapture readonly %c) #0 {
 ; CHECK: entry:
-; CHECK:   %0 = load float* %c, align 4, !noalias !3
-; CHECK:   %arrayidx.i = getelementptr inbounds float* %a, i64 5
+; CHECK:   %0 = load float, float* %c, align 4, !noalias !3
+; CHECK:   %arrayidx.i = getelementptr inbounds float, float* %a, i64 5
 ; CHECK:   store float %0, float* %arrayidx.i, align 4, !alias.scope !7, !noalias !8
-; CHECK:   %arrayidx1.i = getelementptr inbounds float* %b, i64 8
+; CHECK:   %arrayidx1.i = getelementptr inbounds float, float* %b, i64 8
 ; CHECK:   store float %0, float* %arrayidx1.i, align 4, !alias.scope !8, !noalias !7
-; CHECK:   %1 = load float* %c, align 4
-; CHECK:   %arrayidx = getelementptr inbounds float* %a, i64 7
+; CHECK:   %1 = load float, float* %c, align 4
+; CHECK:   %arrayidx = getelementptr inbounds float, float* %a, i64 7
 ; CHECK:   store float %1, float* %arrayidx, align 4
 ; CHECK:   ret void
 ; CHECK: }
diff --git a/test/Transforms/Inline/noalias2.ll b/test/Transforms/Inline/noalias2.ll
index 9c8f8e22d388..df135b0a318a 100644
--- a/test/Transforms/Inline/noalias2.ll
+++ b/test/Transforms/Inline/noalias2.ll
@@ -4,8 +4,8 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define void @hello(float* noalias nocapture %a, float* noalias nocapture readonly %c) #0 {
 entry:
-  %0 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 5
+  %0 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 5
   store float %0, float* %arrayidx, align 4
   ret void
 }
@@ -13,29 +13,29 @@ entry:
 define void @foo(float* noalias nocapture %a, float* noalias nocapture readonly %c) #0 {
 entry:
   tail call void @hello(float* %a, float* %c)
-  %0 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 7
+  %0 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 7
   store float %0, float* %arrayidx, align 4
   ret void
 }
 
 ; CHECK: define void @foo(float* noalias nocapture %a, float* noalias nocapture readonly %c) #0 {
 ; CHECK: entry:
-; CHECK:   %0 = load float* %c, align 4, !alias.scope !0, !noalias !3
-; CHECK:   %arrayidx.i = getelementptr inbounds float* %a, i64 5
+; CHECK:   %0 = load float, float* %c, align 4, !alias.scope !0, !noalias !3
+; CHECK:   %arrayidx.i = getelementptr inbounds float, float* %a, i64 5
 ; CHECK:   store float %0, float* %arrayidx.i, align 4, !alias.scope !3, !noalias !0
-; CHECK:   %1 = load float* %c, align 4
-; CHECK:   %arrayidx = getelementptr inbounds float* %a, i64 7
+; CHECK:   %1 = load float, float* %c, align 4
+; CHECK:   %arrayidx = getelementptr inbounds float, float* %a, i64 7
 ; CHECK:   store float %1, float* %arrayidx, align 4
 ; CHECK:   ret void
 ; CHECK: }
 
 define void @hello2(float* noalias nocapture %a, float* noalias nocapture %b, float* nocapture readonly %c) #0 {
 entry:
-  %0 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 6
+  %0 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 6
   store float %0, float* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds float* %b, i64 8
+  %arrayidx1 = getelementptr inbounds float, float* %b, i64 8
   store float %0, float* %arrayidx1, align 4
   ret void
 }
@@ -46,27 +46,27 @@ define void @foo2(float* nocapture %a, float* nocapture %b, float* nocapture rea
 entry:
   tail call void @foo(float* %a, float* %c)
   tail call void @hello2(float* %a, float* %b, float* %c)
-  %0 = load float* %c, align 4
-  %arrayidx = getelementptr inbounds float* %a, i64 7
+  %0 = load float, float* %c, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 7
   store float %0, float* %arrayidx, align 4
   ret void
 }
 
 ; CHECK: define void @foo2(float* nocapture %a, float* nocapture %b, float* nocapture readonly %c) #0 {
 ; CHECK: entry:
-; CHECK:   %0 = load float* %c, align 4, !alias.scope !5, !noalias !10
-; CHECK:   %arrayidx.i.i = getelementptr inbounds float* %a, i64 5
+; CHECK:   %0 = load float, float* %c, align 4, !alias.scope !5, !noalias !10
+; CHECK:   %arrayidx.i.i = getelementptr inbounds float, float* %a, i64 5
 ; CHECK:   store float %0, float* %arrayidx.i.i, align 4, !alias.scope !10, !noalias !5
-; CHECK:   %1 = load float* %c, align 4, !alias.scope !13, !noalias !14
-; CHECK:   %arrayidx.i = getelementptr inbounds float* %a, i64 7
+; CHECK:   %1 = load float, float* %c, align 4, !alias.scope !13, !noalias !14
+; CHECK:   %arrayidx.i = getelementptr inbounds float, float* %a, i64 7
 ; CHECK:   store float %1, float* %arrayidx.i, align 4, !alias.scope !14, !noalias !13
-; CHECK:   %2 = load float* %c, align 4, !noalias !15
-; CHECK:   %arrayidx.i1 = getelementptr inbounds float* %a, i64 6
-; CHECK:   store float %2, float* %arrayidx.i1, align 4, !alias.scope !19, !noalias !20
-; CHECK:   %arrayidx1.i = getelementptr inbounds float* %b, i64 8
+; CHECK:   %2 = load float, float* %c, align 4, !noalias !15
+; CHECK:   %arrayidx.i.1 = getelementptr inbounds float, float* %a, i64 6
+; CHECK:   store float %2, float* %arrayidx.i.1, align 4, !alias.scope !19, !noalias !20
+; CHECK:   %arrayidx1.i = getelementptr inbounds float, float* %b, i64 8
 ; CHECK:   store float %2, float* %arrayidx1.i, align 4, !alias.scope !20, !noalias !19
-; CHECK:   %3 = load float* %c, align 4
-; CHECK:   %arrayidx = getelementptr inbounds float* %a, i64 7
+; CHECK:   %3 = load float, float* %c, align 4
+; CHECK:   %arrayidx = getelementptr inbounds float, float* %a, i64 7
 ; CHECK:   store float %3, float* %arrayidx, align 4
 ; CHECK:   ret void
 ; CHECK: }
diff --git a/test/Transforms/Inline/optimization-remarks.ll b/test/Transforms/Inline/optimization-remarks.ll
index fb1b04788885..8a3e4d1b1fe4 100644
--- a/test/Transforms/Inline/optimization-remarks.ll
+++ b/test/Transforms/Inline/optimization-remarks.ll
@@ -12,8 +12,8 @@ entry:
   %y.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
   store i32 %y, i32* %y.addr, align 4
-  %0 = load i32* %x.addr, align 4
-  %1 = load i32* %y.addr, align 4
+  %0 = load i32, i32* %x.addr, align 4
+  %1 = load i32, i32* %y.addr, align 4
   %add = add nsw i32 %0, %1
   ret i32 %add
 }
@@ -25,8 +25,8 @@ entry:
   %y.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
   store i32 %y, i32* %y.addr, align 4
-  %0 = load i32* %x.addr, align 4
-  %1 = load i32* %y.addr, align 4
+  %0 = load i32, i32* %x.addr, align 4
+  %1 = load i32, i32* %y.addr, align 4
   %mul = mul nsw i32 %0, %1
   %conv = sitofp i32 %mul to float
   ret float %conv
@@ -37,14 +37,14 @@ define i32 @bar(i32 %j) #2 {
 entry:
   %j.addr = alloca i32, align 4
   store i32 %j, i32* %j.addr, align 4
-  %0 = load i32* %j.addr, align 4
-  %1 = load i32* %j.addr, align 4
+  %0 = load i32, i32* %j.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
   %sub = sub nsw i32 %1, 2
   %call = call i32 @foo(i32 %0, i32 %sub)
   %conv = sitofp i32 %call to float
-  %2 = load i32* %j.addr, align 4
+  %2 = load i32, i32* %j.addr, align 4
   %sub1 = sub nsw i32 %2, 2
-  %3 = load i32* %j.addr, align 4
+  %3 = load i32, i32* %j.addr, align 4
   %call2 = call float @foz(i32 %sub1, i32 %3)
   %mul = fmul float %conv, %call2
   %conv3 = fptosi float %mul to i32
diff --git a/test/Transforms/Inline/pr22285.ll b/test/Transforms/Inline/pr22285.ll
new file mode 100644
index 000000000000..1deae1860f08
--- /dev/null
+++ b/test/Transforms/Inline/pr22285.ll
@@ -0,0 +1,15 @@
+; RUN: opt < %s -inline -S | FileCheck %s
+
+$f1 = comdat any
+; CHECK-NOT: $f1 = comdat any
+
+define void @f2() {
+  call void @f1()
+  ret void
+}
+; CHECK-LABEL: define void @f2
+
+define linkonce_odr void @f1() comdat {
+  ret void
+}
+; CHECK-NOT: define linkonce_odr void @f1() comdat
diff --git a/test/Transforms/Inline/ptr-diff.ll b/test/Transforms/Inline/ptr-diff.ll
index 46c3bcd4dc53..728f3793ee2d 100644
--- a/test/Transforms/Inline/ptr-diff.ll
+++ b/test/Transforms/Inline/ptr-diff.ll
@@ -8,8 +8,8 @@ define i32 @outer1() {
 ; CHECK: ret i32
 
   %ptr = alloca i32
-  %ptr1 = getelementptr inbounds i32* %ptr, i32 0
-  %ptr2 = getelementptr inbounds i32* %ptr, i32 42
+  %ptr1 = getelementptr inbounds i32, i32* %ptr, i32 0
+  %ptr2 = getelementptr inbounds i32, i32* %ptr, i32 42
   %result = call i32 @inner1(i32* %ptr1, i32* %ptr2)
   ret i32 %result
 }
@@ -25,7 +25,7 @@ then:
   ret i32 3
 
 else:
-  %t = load i32* %begin
+  %t = load i32, i32* %begin
   ret i32 %t
 }
 
@@ -36,8 +36,8 @@ define i32 @outer2(i32* %ptr) {
 ; CHECK: call i32 @inner2
 ; CHECK: ret i32
 
-  %ptr1 = getelementptr i32* %ptr, i32 0
-  %ptr2 = getelementptr i32* %ptr, i32 42
+  %ptr1 = getelementptr i32, i32* %ptr, i32 0
+  %ptr2 = getelementptr i32, i32* %ptr, i32 42
   %result = call i32 @inner2(i32* %ptr1, i32* %ptr2)
   ret i32 %result
 }
@@ -53,7 +53,7 @@ then:
   ret i32 3
 
 else:
-  %t = load i32* %begin
+  %t = load i32, i32* %begin
   ret i32 %t
 }
 
@@ -63,9 +63,9 @@ define i32 @inttoptr_free_cost(i32 %a, i32 %b, i32 %c) {
   %p1 = inttoptr i32 %a to i32 addrspace(1)*
   %p2 = inttoptr i32 %b to i32 addrspace(1)*
   %p3 = inttoptr i32 %c to i32 addrspace(1)*
-  %t1 = load i32 addrspace(1)* %p1
-  %t2 = load i32 addrspace(1)* %p2
-  %t3 = load i32 addrspace(1)* %p3
+  %t1 = load i32, i32 addrspace(1)* %p1
+  %t2 = load i32, i32 addrspace(1)* %p2
+  %t3 = load i32, i32 addrspace(1)* %p3
   %s = add i32 %t1, %t2
   %s1 = add i32 %s, %t3
   ret i32 %s1
@@ -84,9 +84,9 @@ define i32 @inttoptr_cost_smaller_ptr(i32 %a, i32 %b, i32 %c) {
   %p1 = inttoptr i32 %a to i32 addrspace(2)*
   %p2 = inttoptr i32 %b to i32 addrspace(2)*
   %p3 = inttoptr i32 %c to i32 addrspace(2)*
-  %t1 = load i32 addrspace(2)* %p1
-  %t2 = load i32 addrspace(2)* %p2
-  %t3 = load i32 addrspace(2)* %p3
+  %t1 = load i32, i32 addrspace(2)* %p1
+  %t2 = load i32, i32 addrspace(2)* %p2
+  %t3 = load i32, i32 addrspace(2)* %p3
   %s = add i32 %t1, %t2
   %s1 = add i32 %s, %t3
   ret i32 %s1
diff --git a/test/Transforms/Inline/store-sroa.ll b/test/Transforms/Inline/store-sroa.ll
new file mode 100644
index 000000000000..6b1ca964d330
--- /dev/null
+++ b/test/Transforms/Inline/store-sroa.ll
@@ -0,0 +1,22 @@
+; RUN: opt -S -O2 -inline-threshold=1 < %s | FileCheck %s
+
+%class.A = type { i32 }
+
+define void @_Z3barP1A(%class.A* %a) #0 {
+entry:
+  %a1 = getelementptr inbounds %class.A, %class.A* %a, i64 0, i32 0
+  %0 = load i32, i32* %a1, align 4
+  %add = add nsw i32 %0, 10
+  store i32 %add, i32* %a1, align 4
+  ret void
+}
+
+define void @_Z3foov() #0 {
+; CHECK-LABEL: @_Z3foov(
+; CHECK-NOT: call void @_Z3barP1A
+; CHECK: ret
+entry:
+  %a = alloca %class.A, align 4
+  call void @_Z3barP1A(%class.A* %a)
+  ret void
+}
diff --git a/test/Transforms/Inline/vector-bonus.ll b/test/Transforms/Inline/vector-bonus.ll
new file mode 100644
index 000000000000..c6745d59e5e0
--- /dev/null
+++ b/test/Transforms/Inline/vector-bonus.ll
@@ -0,0 +1,37 @@
+; RUN: opt < %s -inline -inline-threshold=35  -S | FileCheck %s
+
+define i32 @bar(<4 x i32> %v, i32 %i) #0 {
+entry:
+  %cmp = icmp sgt i32 %i, 4
+  br i1 %cmp, label %if.then, label %if.else
+
+if.then:                                          ; preds = %entry
+  %mul1 = mul nsw i32 %i, %i
+  br label %return
+
+if.else:                                          ; preds = %entry
+  %add1 = add nsw i32 %i, %i
+  %add2 = add nsw i32 %i, %i
+  %add3 = add nsw i32 %i, %i
+  %add4 = add nsw i32 %i, %i
+  %add5 = add nsw i32 %i, %i
+  %add6 = add nsw i32 %i, %i
+  %vecext = extractelement <4 x i32> %v, i32 0
+  %vecext7 = extractelement <4 x i32> %v, i32 1
+  %add7 = add nsw i32 %vecext, %vecext7
+  br label %return
+
+return:                                           ; preds = %if.else, %if.then
+  %retval.0 = phi i32 [ %mul1, %if.then ], [ %add7, %if.else ]
+  ret i32 %retval.0
+}
+
+define i32 @foo(<4 x i32> %v, i32 %a) #1 {
+; CHECK-LABEL: @foo(
+; CHECK-NOT: call i32 @bar
+; CHECK: ret
+entry:
+  %call = call i32 @bar(<4 x i32> %v, i32 %a)
+  ret i32 %call
+}
+
diff --git a/test/Transforms/InstCombine/2003-07-21-ExternalConstant.ll b/test/Transforms/InstCombine/2003-07-21-ExternalConstant.ll
index f550c8349f84..b38154580893 100644
--- a/test/Transforms/InstCombine/2003-07-21-ExternalConstant.ll
+++ b/test/Transforms/InstCombine/2003-07-21-ExternalConstant.ll
@@ -31,14 +31,14 @@ entry:
         %a.0 = alloca i32               ; <i32*> [#uses=2]
         %result = alloca i32            ; <i32*> [#uses=2]
         store i32 %a.1, i32* %a.0
-        %tmp.0 = load i32* %a.0         ; <i32> [#uses=1]
-        %tmp.1 = load i32* @silly               ; <i32> [#uses=1]
+        %tmp.0 = load i32, i32* %a.0         ; <i32> [#uses=1]
+        %tmp.1 = load i32, i32* @silly               ; <i32> [#uses=1]
         %tmp.2 = add i32 %tmp.0, %tmp.1         ; <i32> [#uses=1]
         store i32 %tmp.2, i32* %result
         br label %return
 
 return:         ; preds = %entry
-        %tmp.3 = load i32* %result              ; <i32> [#uses=1]
+        %tmp.3 = load i32, i32* %result              ; <i32> [#uses=1]
         ret i32 %tmp.3
 }
 
diff --git a/test/Transforms/InstCombine/2003-08-12-AllocaNonNull.ll b/test/Transforms/InstCombine/2003-08-12-AllocaNonNull.ll
index bb9a8181ccd4..50b9fdb16458 100644
--- a/test/Transforms/InstCombine/2003-08-12-AllocaNonNull.ll
+++ b/test/Transforms/InstCombine/2003-08-12-AllocaNonNull.ll
@@ -12,7 +12,7 @@ entry:
         br i1 %tmp.1, label %then, label %UnifiedExitNode
 
 then:           ; preds = %entry
-        %tmp.4 = call i32 (...)* @bitmap_clear( i32* %live_head )               ; <i32> [#uses=0]
+        %tmp.4 = call i32 (...) @bitmap_clear( i32* %live_head )               ; <i32> [#uses=0]
         br label %UnifiedExitNode
 
 UnifiedExitNode:                ; preds = %then, %entry
diff --git a/test/Transforms/InstCombine/2003-09-09-VolatileLoadElim.ll b/test/Transforms/InstCombine/2003-09-09-VolatileLoadElim.ll
index 7f7390809c77..3e0cf1247d90 100644
--- a/test/Transforms/InstCombine/2003-09-09-VolatileLoadElim.ll
+++ b/test/Transforms/InstCombine/2003-09-09-VolatileLoadElim.ll
@@ -2,6 +2,6 @@
 
 define void @test(i32* %P) {
         ; Dead but not deletable!
-        %X = load volatile i32* %P              ; <i32> [#uses=0]
+        %X = load volatile i32, i32* %P              ; <i32> [#uses=0]
         ret void
 }
diff --git a/test/Transforms/InstCombine/2003-11-03-VarargsCallBug.ll b/test/Transforms/InstCombine/2003-11-03-VarargsCallBug.ll
index c1692f77abb2..aff39f8bf979 100644
--- a/test/Transforms/InstCombine/2003-11-03-VarargsCallBug.ll
+++ b/test/Transforms/InstCombine/2003-11-03-VarargsCallBug.ll
@@ -7,7 +7,7 @@ declare void @foo(...)
 
 define void @test(i64 %X) {
         %Y = inttoptr i64 %X to i32*            ; <i32*> [#uses=1]
-        call void (...)* @foo( i32* %Y )
+        call void (...) @foo( i32* %Y )
         ret void
 }
 
diff --git a/test/Transforms/InstCombine/2004-01-13-InstCombineInvokePHI.ll b/test/Transforms/InstCombine/2004-01-13-InstCombineInvokePHI.ll
index 6df30c7e7fd1..a086c0156504 100644
--- a/test/Transforms/InstCombine/2004-01-13-InstCombineInvokePHI.ll
+++ b/test/Transforms/InstCombine/2004-01-13-InstCombineInvokePHI.ll
@@ -19,7 +19,7 @@ call:           ; preds = %entry
 
 cont:           ; preds = %call, %entry
         %P2 = phi i32* [ %P, %call ], [ null, %entry ]          ; <i32*> [#uses=1]
-        %V = load i32* %P2              ; <i32> [#uses=1]
+        %V = load i32, i32* %P2              ; <i32> [#uses=1]
         ret i32 %V
 
 N:              ; preds = %call
diff --git a/test/Transforms/InstCombine/2004-05-07-UnsizedCastLoad.ll b/test/Transforms/InstCombine/2004-05-07-UnsizedCastLoad.ll
index 8b549374a70c..ff855dc13e5b 100644
--- a/test/Transforms/InstCombine/2004-05-07-UnsizedCastLoad.ll
+++ b/test/Transforms/InstCombine/2004-05-07-UnsizedCastLoad.ll
@@ -4,7 +4,7 @@
 
 define i32 @test(%Ty* %X) {
         %Y = bitcast %Ty* %X to i32*            ; <i32*> [#uses=1]
-        %Z = load i32* %Y               ; <i32> [#uses=1]
+        %Z = load i32, i32* %Y               ; <i32> [#uses=1]
         ret i32 %Z
 }
 
diff --git a/test/Transforms/InstCombine/2004-09-20-BadLoadCombine.ll b/test/Transforms/InstCombine/2004-09-20-BadLoadCombine.ll
index d17db8d7eac2..10122e48ab66 100644
--- a/test/Transforms/InstCombine/2004-09-20-BadLoadCombine.ll
+++ b/test/Transforms/InstCombine/2004-09-20-BadLoadCombine.ll
@@ -12,7 +12,7 @@ define i32 @test(i1 %C) {
         store i32 2, i32* %X2
         %Y = select i1 %C, i32* %X, i32* %X2            ; <i32*> [#uses=1]
         store i32 3, i32* %X
-        %Z = load i32* %Y               ; <i32> [#uses=1]
+        %Z = load i32, i32* %Y               ; <i32> [#uses=1]
         ret i32 %Z
 }
 
diff --git a/test/Transforms/InstCombine/2004-09-20-BadLoadCombine2.ll b/test/Transforms/InstCombine/2004-09-20-BadLoadCombine2.ll
index 0d5fc810a8ae..981a4f301a99 100644
--- a/test/Transforms/InstCombine/2004-09-20-BadLoadCombine2.ll
+++ b/test/Transforms/InstCombine/2004-09-20-BadLoadCombine2.ll
@@ -18,7 +18,7 @@ cond_true.i:            ; preds = %entry
 cond_continue.i:                ; preds = %cond_true.i, %entry
         %mem_tmp.i.0 = phi i32* [ %X, %cond_true.i ], [ %X2, %entry ]           ; <i32*> [#uses=1]
         store i32 3, i32* %X
-        %tmp.3 = load i32* %mem_tmp.i.0         ; <i32> [#uses=1]
+        %tmp.3 = load i32, i32* %mem_tmp.i.0         ; <i32> [#uses=1]
         ret i32 %tmp.3
 }
 
diff --git a/test/Transforms/InstCombine/2005-06-16-SetCCOrSetCCMiscompile.ll b/test/Transforms/InstCombine/2005-06-16-SetCCOrSetCCMiscompile.ll
index 0a513c647c12..9c989b9ecf8a 100644
--- a/test/Transforms/InstCombine/2005-06-16-SetCCOrSetCCMiscompile.ll
+++ b/test/Transforms/InstCombine/2005-06-16-SetCCOrSetCCMiscompile.ll
@@ -5,7 +5,7 @@
 @g_07918478 = external global i32               ; <i32*> [#uses=1]
 
 define i1 @test() {
-        %tmp.0 = load i32* @g_07918478          ; <i32> [#uses=2]
+        %tmp.0 = load i32, i32* @g_07918478          ; <i32> [#uses=2]
         %tmp.1 = icmp ne i32 %tmp.0, 0          ; <i1> [#uses=1]
         %tmp.4 = icmp ult i32 %tmp.0, 4111              ; <i1> [#uses=1]
         %bothcond = or i1 %tmp.1, %tmp.4                ; <i1> [#uses=1]
diff --git a/test/Transforms/InstCombine/2006-09-15-CastToBool.ll b/test/Transforms/InstCombine/2006-09-15-CastToBool.ll
index ee261ced5869..2eb28a3f6bb8 100644
--- a/test/Transforms/InstCombine/2006-09-15-CastToBool.ll
+++ b/test/Transforms/InstCombine/2006-09-15-CastToBool.ll
@@ -2,7 +2,7 @@
 ; PR913
 
 define i32 @test(i32* %tmp1) {
-        %tmp.i = load i32* %tmp1                ; <i32> [#uses=1]
+        %tmp.i = load i32, i32* %tmp1                ; <i32> [#uses=1]
         %tmp = bitcast i32 %tmp.i to i32                ; <i32> [#uses=1]
         %tmp2.ui = lshr i32 %tmp, 5             ; <i32> [#uses=1]
         %tmp2 = bitcast i32 %tmp2.ui to i32             ; <i32> [#uses=1]
diff --git a/test/Transforms/InstCombine/2006-12-08-Phi-ICmp-Op-Fold.ll b/test/Transforms/InstCombine/2006-12-08-Phi-ICmp-Op-Fold.ll
index 295006ca2318..60113fb56206 100644
--- a/test/Transforms/InstCombine/2006-12-08-Phi-ICmp-Op-Fold.ll
+++ b/test/Transforms/InstCombine/2006-12-08-Phi-ICmp-Op-Fold.ll
@@ -12,24 +12,24 @@ entry:
 	%p3_addr = alloca %struct.point		; <%struct.point*> [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	%tmp = bitcast %struct.point* %p1_addr to { i64 }*		; <{ i64 }*> [#uses=1]
-	%tmp.upgrd.1 = getelementptr { i64 }* %tmp, i64 0, i32 0		; <i64*> [#uses=1]
+	%tmp.upgrd.1 = getelementptr { i64 }, { i64 }* %tmp, i64 0, i32 0		; <i64*> [#uses=1]
 	store i64 %p1.0, i64* %tmp.upgrd.1
 	%tmp1 = bitcast %struct.point* %p2_addr to { i64 }*		; <{ i64 }*> [#uses=1]
-	%tmp2 = getelementptr { i64 }* %tmp1, i64 0, i32 0		; <i64*> [#uses=1]
+	%tmp2 = getelementptr { i64 }, { i64 }* %tmp1, i64 0, i32 0		; <i64*> [#uses=1]
 	store i64 %p2.0, i64* %tmp2
 	%tmp3 = bitcast %struct.point* %p3_addr to { i64 }*		; <{ i64 }*> [#uses=1]
-	%tmp4 = getelementptr { i64 }* %tmp3, i64 0, i32 0		; <i64*> [#uses=1]
+	%tmp4 = getelementptr { i64 }, { i64 }* %tmp3, i64 0, i32 0		; <i64*> [#uses=1]
 	store i64 %p3.0, i64* %tmp4
 	%tmp.upgrd.2 = icmp eq i32 %direction, 0		; <i1> [#uses=1]
 	%tmp5 = bitcast %struct.point* %p1_addr to { i64 }*		; <{ i64 }*> [#uses=1]
-	%tmp6 = getelementptr { i64 }* %tmp5, i64 0, i32 0		; <i64*> [#uses=1]
-	%tmp.upgrd.3 = load i64* %tmp6		; <i64> [#uses=1]
+	%tmp6 = getelementptr { i64 }, { i64 }* %tmp5, i64 0, i32 0		; <i64*> [#uses=1]
+	%tmp.upgrd.3 = load i64, i64* %tmp6		; <i64> [#uses=1]
 	%tmp7 = bitcast %struct.point* %p2_addr to { i64 }*		; <{ i64 }*> [#uses=1]
-	%tmp8 = getelementptr { i64 }* %tmp7, i64 0, i32 0		; <i64*> [#uses=1]
-	%tmp9 = load i64* %tmp8		; <i64> [#uses=1]
+	%tmp8 = getelementptr { i64 }, { i64 }* %tmp7, i64 0, i32 0		; <i64*> [#uses=1]
+	%tmp9 = load i64, i64* %tmp8		; <i64> [#uses=1]
 	%tmp10 = bitcast %struct.point* %p3_addr to { i64 }*		; <{ i64 }*> [#uses=1]
-	%tmp11 = getelementptr { i64 }* %tmp10, i64 0, i32 0		; <i64*> [#uses=1]
-	%tmp12 = load i64* %tmp11		; <i64> [#uses=1]
+	%tmp11 = getelementptr { i64 }, { i64 }* %tmp10, i64 0, i32 0		; <i64*> [#uses=1]
+	%tmp12 = load i64, i64* %tmp11		; <i64> [#uses=1]
 	%tmp13 = call i32 @determinant( i64 %tmp.upgrd.3, i64 %tmp9, i64 %tmp12 )		; <i32> [#uses=2]
 	br i1 %tmp.upgrd.2, label %cond_true, label %cond_false
 
diff --git a/test/Transforms/InstCombine/2006-12-08-Select-ICmp.ll b/test/Transforms/InstCombine/2006-12-08-Select-ICmp.ll
index 272753cc98d6..f54416d14254 100644
--- a/test/Transforms/InstCombine/2006-12-08-Select-ICmp.ll
+++ b/test/Transforms/InstCombine/2006-12-08-Select-ICmp.ll
@@ -12,24 +12,24 @@ entry:
         %p2_addr = alloca %struct.point         ; <%struct.point*> [#uses=2]
         %p3_addr = alloca %struct.point         ; <%struct.point*> [#uses=2]
         %tmp = bitcast %struct.point* %p1_addr to { i64 }*              ; <{ i64 }*> [#uses=1]
-        %tmp.upgrd.1 = getelementptr { i64 }* %tmp, i32 0, i32 0                ; <i64*> [#uses=1]
+        %tmp.upgrd.1 = getelementptr { i64 }, { i64 }* %tmp, i32 0, i32 0                ; <i64*> [#uses=1]
         store i64 %p1.0, i64* %tmp.upgrd.1
         %tmp1 = bitcast %struct.point* %p2_addr to { i64 }*             ; <{ i64 }*> [#uses=1]
-        %tmp2 = getelementptr { i64 }* %tmp1, i32 0, i32 0              ; <i64*> [#uses=1]
+        %tmp2 = getelementptr { i64 }, { i64 }* %tmp1, i32 0, i32 0              ; <i64*> [#uses=1]
         store i64 %p2.0, i64* %tmp2
         %tmp3 = bitcast %struct.point* %p3_addr to { i64 }*             ; <{ i64 }*> [#uses=1]
-        %tmp4 = getelementptr { i64 }* %tmp3, i32 0, i32 0              ; <i64*> [#uses=1]
+        %tmp4 = getelementptr { i64 }, { i64 }* %tmp3, i32 0, i32 0              ; <i64*> [#uses=1]
         store i64 %p3.0, i64* %tmp4
         %tmp.upgrd.2 = icmp eq i32 %direction, 0                ; <i1> [#uses=1]
         %tmp5 = bitcast %struct.point* %p1_addr to { i64 }*             ; <{ i64 }*> [#uses=1]
-        %tmp6 = getelementptr { i64 }* %tmp5, i32 0, i32 0              ; <i64*> [#uses=1]
-        %tmp.upgrd.3 = load i64* %tmp6          ; <i64> [#uses=1]
+        %tmp6 = getelementptr { i64 }, { i64 }* %tmp5, i32 0, i32 0              ; <i64*> [#uses=1]
+        %tmp.upgrd.3 = load i64, i64* %tmp6          ; <i64> [#uses=1]
         %tmp7 = bitcast %struct.point* %p2_addr to { i64 }*             ; <{ i64 }*> [#uses=1]
-        %tmp8 = getelementptr { i64 }* %tmp7, i32 0, i32 0              ; <i64*> [#uses=1]
-        %tmp9 = load i64* %tmp8         ; <i64> [#uses=1]
+        %tmp8 = getelementptr { i64 }, { i64 }* %tmp7, i32 0, i32 0              ; <i64*> [#uses=1]
+        %tmp9 = load i64, i64* %tmp8         ; <i64> [#uses=1]
         %tmp10 = bitcast %struct.point* %p3_addr to { i64 }*            ; <{ i64 }*> [#uses=1]
-        %tmp11 = getelementptr { i64 }* %tmp10, i32 0, i32 0            ; <i64*> [#uses=1]
-        %tmp12 = load i64* %tmp11               ; <i64> [#uses=1]
+        %tmp11 = getelementptr { i64 }, { i64 }* %tmp10, i32 0, i32 0            ; <i64*> [#uses=1]
+        %tmp12 = load i64, i64* %tmp11               ; <i64> [#uses=1]
         %tmp13 = call i32 @determinant( i64 %tmp.upgrd.3, i64 %tmp9, i64 %tmp12 )         ; <i32> [#uses=2]
         %tmp14 = icmp slt i32 %tmp13, 0         ; <i1> [#uses=1]
         %tmp26 = icmp sgt i32 %tmp13, 0         ; <i1> [#uses=1]
diff --git a/test/Transforms/InstCombine/2006-12-15-Range-Test.ll b/test/Transforms/InstCombine/2006-12-15-Range-Test.ll
index 0c8eeceec81c..784b3e4fe687 100644
--- a/test/Transforms/InstCombine/2006-12-15-Range-Test.ll
+++ b/test/Transforms/InstCombine/2006-12-15-Range-Test.ll
@@ -21,8 +21,8 @@ cond_next23.exitStub:           ; preds = %cond_true
         ret i1 false
 
 cond_true:              ; preds = %newFuncRoot
-        %tmp15 = getelementptr [17 x i32]* @r, i32 0, i32 %tmp12.reload         ; <i32*> [#uses=1]
-        %tmp16 = load i32* %tmp15               ; <i32> [#uses=4]
+        %tmp15 = getelementptr [17 x i32], [17 x i32]* @r, i32 0, i32 %tmp12.reload         ; <i32*> [#uses=1]
+        %tmp16 = load i32, i32* %tmp15               ; <i32> [#uses=4]
         %tmp18 = icmp slt i32 %tmp16, -31               ; <i1> [#uses=1]
         %tmp21 = icmp sgt i32 %tmp16, 31                ; <i1> [#uses=1]
         %bothcond = or i1 %tmp18, %tmp21                ; <i1> [#uses=1]
diff --git a/test/Transforms/InstCombine/2006-12-23-Select-Cmp-Cmp.ll b/test/Transforms/InstCombine/2006-12-23-Select-Cmp-Cmp.ll
index eba1ac1298ce..9251e9b455d6 100644
--- a/test/Transforms/InstCombine/2006-12-23-Select-Cmp-Cmp.ll
+++ b/test/Transforms/InstCombine/2006-12-23-Select-Cmp-Cmp.ll
@@ -14,9 +14,9 @@ target triple = "i686-pc-linux-gnu"
 
 define void @mng_write_basi() {
 entry:
-	%tmp = load i8* null		; <i8> [#uses=1]
+	%tmp = load i8, i8* null		; <i8> [#uses=1]
 	%tmp.upgrd.1 = icmp ugt i8 %tmp, 8		; <i1> [#uses=1]
-	%tmp.upgrd.2 = load i16* null		; <i16> [#uses=2]
+	%tmp.upgrd.2 = load i16, i16* null		; <i16> [#uses=2]
 	%tmp3 = icmp eq i16 %tmp.upgrd.2, 255		; <i1> [#uses=1]
 	%tmp7 = icmp eq i16 %tmp.upgrd.2, -1		; <i1> [#uses=1]
 	%bOpaque.0.in = select i1 %tmp.upgrd.1, i1 %tmp7, i1 %tmp3		; <i1> [#uses=1]
diff --git a/test/Transforms/InstCombine/2007-02-01-LoadSinkAlloca.ll b/test/Transforms/InstCombine/2007-02-01-LoadSinkAlloca.ll
index e2bebecded52..113ada3df9d9 100644
--- a/test/Transforms/InstCombine/2007-02-01-LoadSinkAlloca.ll
+++ b/test/Transforms/InstCombine/2007-02-01-LoadSinkAlloca.ll
@@ -10,33 +10,33 @@ define i32 @test2(i32 %C) {
 entry:
 	%A = alloca i32
 	%B = alloca i32
-	%tmp = call i32 (...)* @bar( i32* %A )		; <i32> [#uses=0]
-	%T = load i32* %A		; <i32> [#uses=1]
+	%tmp = call i32 (...) @bar( i32* %A )		; <i32> [#uses=0]
+	%T = load i32, i32* %A		; <i32> [#uses=1]
 	%tmp2 = icmp eq i32 %C, 0		; <i1> [#uses=1]
 	br i1 %tmp2, label %cond_next, label %cond_true
 
 cond_true:		; preds = %entry
 	store i32 123, i32* %B
 	call i32 @test2( i32 123 )		; <i32>:0 [#uses=0]
-	%T1 = load i32* %B		; <i32> [#uses=1]
+	%T1 = load i32, i32* %B		; <i32> [#uses=1]
 	br label %cond_next
 
 cond_next:		; preds = %cond_true, %entry
 	%tmp1.0 = phi i32 [ %T1, %cond_true ], [ %T, %entry ]		; <i32> [#uses=1]
-	%tmp7 = call i32 (...)* @baq( )		; <i32> [#uses=0]
-	%tmp8 = call i32 (...)* @baq( )		; <i32> [#uses=0]
-	%tmp9 = call i32 (...)* @baq( )		; <i32> [#uses=0]
-	%tmp10 = call i32 (...)* @baq( )		; <i32> [#uses=0]
-	%tmp11 = call i32 (...)* @baq( )		; <i32> [#uses=0]
-	%tmp12 = call i32 (...)* @baq( )		; <i32> [#uses=0]
-	%tmp13 = call i32 (...)* @baq( )		; <i32> [#uses=0]
-	%tmp14 = call i32 (...)* @baq( )		; <i32> [#uses=0]
-	%tmp15 = call i32 (...)* @baq( )		; <i32> [#uses=0]
-	%tmp16 = call i32 (...)* @baq( )		; <i32> [#uses=0]
-	%tmp17 = call i32 (...)* @baq( )		; <i32> [#uses=0]
-	%tmp18 = call i32 (...)* @baq( )		; <i32> [#uses=0]
-	%tmp19 = call i32 (...)* @baq( )		; <i32> [#uses=0]
-	%tmp20 = call i32 (...)* @baq( )		; <i32> [#uses=0]
+	%tmp7 = call i32 (...) @baq( )		; <i32> [#uses=0]
+	%tmp8 = call i32 (...) @baq( )		; <i32> [#uses=0]
+	%tmp9 = call i32 (...) @baq( )		; <i32> [#uses=0]
+	%tmp10 = call i32 (...) @baq( )		; <i32> [#uses=0]
+	%tmp11 = call i32 (...) @baq( )		; <i32> [#uses=0]
+	%tmp12 = call i32 (...) @baq( )		; <i32> [#uses=0]
+	%tmp13 = call i32 (...) @baq( )		; <i32> [#uses=0]
+	%tmp14 = call i32 (...) @baq( )		; <i32> [#uses=0]
+	%tmp15 = call i32 (...) @baq( )		; <i32> [#uses=0]
+	%tmp16 = call i32 (...) @baq( )		; <i32> [#uses=0]
+	%tmp17 = call i32 (...) @baq( )		; <i32> [#uses=0]
+	%tmp18 = call i32 (...) @baq( )		; <i32> [#uses=0]
+	%tmp19 = call i32 (...) @baq( )		; <i32> [#uses=0]
+	%tmp20 = call i32 (...) @baq( )		; <i32> [#uses=0]
 	ret i32 %tmp1.0
 }
 
diff --git a/test/Transforms/InstCombine/2007-02-07-PointerCast.ll b/test/Transforms/InstCombine/2007-02-07-PointerCast.ll
index bf60991f7dd9..ddc1e03ddd20 100644
--- a/test/Transforms/InstCombine/2007-02-07-PointerCast.ll
+++ b/test/Transforms/InstCombine/2007-02-07-PointerCast.ll
@@ -12,11 +12,11 @@ declare i32 @printf(i8*, ...)
 
 define i32 @main(i32 %x, i8** %a) {
 entry:
-        %tmp = getelementptr [6 x i8]* @str, i32 0, i64 0               ; <i8*> [#uses=1]
-        %tmp1 = load i8** %a            ; <i8*> [#uses=1]
+        %tmp = getelementptr [6 x i8], [6 x i8]* @str, i32 0, i64 0               ; <i8*> [#uses=1]
+        %tmp1 = load i8*, i8** %a            ; <i8*> [#uses=1]
         %tmp2 = ptrtoint i8* %tmp1 to i32               ; <i32> [#uses=1]
         %tmp3 = zext i32 %tmp2 to i64           ; <i64> [#uses=1]
-        %tmp.upgrd.1 = call i32 (i8*, ...)* @printf( i8* %tmp, i64 %tmp3 )              ; <i32> [#uses=0]
+        %tmp.upgrd.1 = call i32 (i8*, ...) @printf( i8* %tmp, i64 %tmp3 )              ; <i32> [#uses=0]
         ret i32 0
 }
 
diff --git a/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll b/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll
index 7e9c9e28c94b..adaaf784ab6c 100644
--- a/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll
+++ b/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll
@@ -7,12 +7,12 @@
 define i32 @main() {
 entry:
 	%u = alloca %struct..1anon, align 8		; <%struct..1anon*> [#uses=4]
-	%tmp1 = getelementptr %struct..1anon* %u, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp1 = getelementptr %struct..1anon, %struct..1anon* %u, i32 0, i32 0		; <double*> [#uses=1]
 	store double 0x7FF0000000000000, double* %tmp1
-	%tmp3 = getelementptr %struct..1anon* %u, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp3 = getelementptr %struct..1anon, %struct..1anon* %u, i32 0, i32 0		; <double*> [#uses=1]
 	%tmp34 = bitcast double* %tmp3 to %struct..0anon*		; <%struct..0anon*> [#uses=1]
-	%tmp5 = getelementptr %struct..0anon* %tmp34, i32 0, i32 1		; <i32*> [#uses=1]
-	%tmp6 = load i32* %tmp5		; <i32> [#uses=1]
+	%tmp5 = getelementptr %struct..0anon, %struct..0anon* %tmp34, i32 0, i32 1		; <i32*> [#uses=1]
+	%tmp6 = load i32, i32* %tmp5		; <i32> [#uses=1]
 	%tmp7 = shl i32 %tmp6, 1		; <i32> [#uses=1]
 	%tmp8 = lshr i32 %tmp7, 21		; <i32> [#uses=1]
 	%tmp89 = trunc i32 %tmp8 to i16		; <i16> [#uses=1]
diff --git a/test/Transforms/InstCombine/2007-05-14-Crash.ll b/test/Transforms/InstCombine/2007-05-14-Crash.ll
index a3c010d2c427..a3d216591439 100644
--- a/test/Transforms/InstCombine/2007-05-14-Crash.ll
+++ b/test/Transforms/InstCombine/2007-05-14-Crash.ll
@@ -10,7 +10,7 @@ target triple = "powerpc-apple-darwin8.8.0"
 define i8* @foo(%struct.anon* %deviceRef, %struct.abc* %pCap) {
 entry:
         %tmp1 = bitcast %struct.anon* %deviceRef to %struct.def*            
-        %tmp3 = getelementptr %struct.def* %tmp1, i32 0, i32 1               
+        %tmp3 = getelementptr %struct.def, %struct.def* %tmp1, i32 0, i32 1               
         %tmp35 = bitcast %struct.abc* %tmp3 to i8*           
         ret i8* %tmp35
 }
diff --git a/test/Transforms/InstCombine/2007-06-06-AshrSignBit.ll b/test/Transforms/InstCombine/2007-06-06-AshrSignBit.ll
index 082b2155a010..2b89a9d721fb 100644
--- a/test/Transforms/InstCombine/2007-06-06-AshrSignBit.ll
+++ b/test/Transforms/InstCombine/2007-06-06-AshrSignBit.ll
@@ -9,13 +9,13 @@ return.exitStub:		; preds = %cond_true
 	ret void
 
 cond_true:		; preds = %newFuncRoot
-	%tmp30 = load i64* %tmp10		; <i64> [#uses=1]
+	%tmp30 = load i64, i64* %tmp10		; <i64> [#uses=1]
 	%.cast = zext i32 63 to i64		; <i64> [#uses=1]
 	%tmp31 = ashr i64 %tmp30, %.cast		; <i64> [#uses=1]
 	%tmp3132 = trunc i64 %tmp31 to i32		; <i32> [#uses=1]
 	%tmp33 = or i32 %tmp3132, 1		; <i32> [#uses=1]
 	store i32 %tmp33, i32* %tmp9
-	%tmp34 = load i32* %tmp9		; <i32> [#uses=1]
+	%tmp34 = load i32, i32* %tmp9		; <i32> [#uses=1]
 	store i32 %tmp34, i32* %retval
 	br label %return.exitStub
 }
diff --git a/test/Transforms/InstCombine/2007-09-10-AliasConstFold.ll b/test/Transforms/InstCombine/2007-09-10-AliasConstFold.ll
index 625989384d70..7f06f009515f 100644
--- a/test/Transforms/InstCombine/2007-09-10-AliasConstFold.ll
+++ b/test/Transforms/InstCombine/2007-09-10-AliasConstFold.ll
@@ -9,7 +9,7 @@ define weak i32 @pthread_cancel(i32) {
 
 define i1 @__gthread_active_p() {
 entry:
-	%tmp1 = load i8** @__gthread_active_ptr.5335, align 4		; <i8*> [#uses=1]
+	%tmp1 = load i8*, i8** @__gthread_active_ptr.5335, align 4		; <i8*> [#uses=1]
 	%tmp2 = icmp ne i8* %tmp1, null		; <i1> [#uses=1]
 	ret i1 %tmp2
 }
diff --git a/test/Transforms/InstCombine/2007-10-10-EliminateMemCpy.ll b/test/Transforms/InstCombine/2007-10-10-EliminateMemCpy.ll
index 656fb34061d9..67a94e5c8ccd 100644
--- a/test/Transforms/InstCombine/2007-10-10-EliminateMemCpy.ll
+++ b/test/Transforms/InstCombine/2007-10-10-EliminateMemCpy.ll
@@ -8,8 +8,8 @@ define void @foo(i8* %P) {
 entry:
   %P_addr = alloca i8*
   store i8* %P, i8** %P_addr
-  %tmp = load i8** %P_addr, align 4
-  %tmp1 = getelementptr [4 x i8]* @.str, i32 0, i32 0
+  %tmp = load i8*, i8** %P_addr, align 4
+  %tmp1 = getelementptr [4 x i8], [4 x i8]* @.str, i32 0, i32 0
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp, i8* %tmp1, i32 4, i32 1, i1 false)
   br label %return
 
diff --git a/test/Transforms/InstCombine/2007-10-12-Crash.ll b/test/Transforms/InstCombine/2007-10-12-Crash.ll
index b3d9f02b68aa..33d55e7e9e02 100644
--- a/test/Transforms/InstCombine/2007-10-12-Crash.ll
+++ b/test/Transforms/InstCombine/2007-10-12-Crash.ll
@@ -14,7 +14,7 @@ entry:
 
 bb29:		; preds = %bb62
 	%tmp322 = bitcast %struct.Ray* %tmp3 to %struct.Vec*		; <%struct.Vec*> [#uses=1]
-	%tmp322.0 = getelementptr %struct.Vec* %tmp322, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp322.0 = getelementptr %struct.Vec, %struct.Vec* %tmp322, i32 0, i32 0		; <double*> [#uses=1]
 	store double 0.000000e+00, double* %tmp322.0
 	%tmp57 = call double @_Z9ray_traceRK3VecRK3RayRK5Scene( %struct.Vec* null, %struct.Ray* %tmp3, %struct.Scene* null )		; <double> [#uses=0]
 	br label %bb62
diff --git a/test/Transforms/InstCombine/2007-10-28-stacksave.ll b/test/Transforms/InstCombine/2007-10-28-stacksave.ll
index 95a445c54357..48e876510a9d 100644
--- a/test/Transforms/InstCombine/2007-10-28-stacksave.ll
+++ b/test/Transforms/InstCombine/2007-10-28-stacksave.ll
@@ -23,7 +23,7 @@ lab:		; preds = %cleanup31, %entry
 	%tmp17 = mul i32 %tmp5, 4		; <i32> [#uses=1]
 	%tmp18 = alloca i8, i32 %tmp17		; <i8*> [#uses=1]
 	%tmp1819 = bitcast i8* %tmp18 to i32*		; <i32*> [#uses=2]
-	%tmp21 = getelementptr i32* %tmp1819, i32 0		; <i32*> [#uses=1]
+	%tmp21 = getelementptr i32, i32* %tmp1819, i32 0		; <i32*> [#uses=1]
 	store i32 1, i32* %tmp21, align 4
 	%tmp2223 = bitcast i32* %tmp1819 to i8*		; <i8*> [#uses=1]
 	store volatile i8* %tmp2223, i8** @p, align 4
diff --git a/test/Transforms/InstCombine/2007-10-31-RangeCrash.ll b/test/Transforms/InstCombine/2007-10-31-RangeCrash.ll
index 8105b4ba5579..8c2cb07af224 100644
--- a/test/Transforms/InstCombine/2007-10-31-RangeCrash.ll
+++ b/test/Transforms/InstCombine/2007-10-31-RangeCrash.ll
@@ -11,7 +11,7 @@ bb.i:		; preds = %entry
 	br label %bb51.i.i
 
 bb27.i.i:		; preds = %bb51.i.i
-	%tmp31.i.i = load i16* null, align 2		; <i16> [#uses=2]
+	%tmp31.i.i = load i16, i16* null, align 2		; <i16> [#uses=2]
 	%tmp35.i.i = icmp ult i16 %tmp31.i.i, 1		; <i1> [#uses=1]
 	%tmp41.i.i = icmp ugt i16 %tmp31.i.i, -1		; <i1> [#uses=1]
 	%bothcond.i.i = or i1 %tmp35.i.i, %tmp41.i.i		; <i1> [#uses=1]
diff --git a/test/Transforms/InstCombine/2007-10-31-StringCrash.ll b/test/Transforms/InstCombine/2007-10-31-StringCrash.ll
index 220f3e22b991..876cdd53f524 100644
--- a/test/Transforms/InstCombine/2007-10-31-StringCrash.ll
+++ b/test/Transforms/InstCombine/2007-10-31-StringCrash.ll
@@ -7,7 +7,7 @@ declare void @__darwin_gcc3_preregister_frame_info()
 define void @_start(i32 %argc, i8** %argv, i8** %envp) {
 entry:
 	%tmp1 = bitcast void ()* @__darwin_gcc3_preregister_frame_info to i32*		; <i32*> [#uses=1]
-	%tmp2 = load i32* %tmp1, align 4		; <i32> [#uses=1]
+	%tmp2 = load i32, i32* %tmp1, align 4		; <i32> [#uses=1]
 	%tmp3 = icmp ne i32 %tmp2, 0		; <i1> [#uses=1]
 	%tmp34 = zext i1 %tmp3 to i8		; <i8> [#uses=1]
 	%toBool = icmp ne i8 %tmp34, 0		; <i1> [#uses=1]
diff --git a/test/Transforms/InstCombine/2007-11-07-OpaqueAlignCrash.ll b/test/Transforms/InstCombine/2007-11-07-OpaqueAlignCrash.ll
index e6c9bcd01e5c..ff3107297a12 100644
--- a/test/Transforms/InstCombine/2007-11-07-OpaqueAlignCrash.ll
+++ b/test/Transforms/InstCombine/2007-11-07-OpaqueAlignCrash.ll
@@ -13,8 +13,8 @@ target triple = "i686-pc-linux-gnu"
 
 define i32 @foo() {
 entry:
-        %x = load i8* bitcast (%opaque_t* @g to i8*)
-        %y = load i32* bitcast (%op_ts* @h to i32*)
+        %x = load i8, i8* bitcast (%opaque_t* @g to i8*)
+        %y = load i32, i32* bitcast (%op_ts* @h to i32*)
 	%z = zext i8 %x to i32
 	%r = add i32 %y, %z
         ret i32 %r
diff --git a/test/Transforms/InstCombine/2007-11-25-CompatibleAttributes.ll b/test/Transforms/InstCombine/2007-11-25-CompatibleAttributes.ll
index e3192a990ba0..1232005a5610 100644
--- a/test/Transforms/InstCombine/2007-11-25-CompatibleAttributes.ll
+++ b/test/Transforms/InstCombine/2007-11-25-CompatibleAttributes.ll
@@ -5,7 +5,7 @@
 
 define i32 @main(i32 %argc, i8** %argv) {
 entry:
-	%tmp32 = tail call i32 (i8*  , ...) * bitcast (i32 (i8*, ...)  * @printf to i32 (i8*  , ...)  *)( i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0)  , i32 0 ) nounwind 		; <i32> [#uses=0]
+	%tmp32 = tail call i32 (i8*  , ...) bitcast (i32 (i8*, ...)  * @printf to i32 (i8*  , ...)  *)( i8* getelementptr ([4 x i8], [4 x i8]* @.str, i32 0, i32 0)  , i32 0 ) nounwind 		; <i32> [#uses=0]
 	ret i32 undef
 }
 
diff --git a/test/Transforms/InstCombine/2007-12-12-GEPScale.ll b/test/Transforms/InstCombine/2007-12-12-GEPScale.ll
index cea87f2a4666..60f715e2ef7d 100644
--- a/test/Transforms/InstCombine/2007-12-12-GEPScale.ll
+++ b/test/Transforms/InstCombine/2007-12-12-GEPScale.ll
@@ -5,6 +5,6 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 define i8* @foo([100 x {i8,i8,i8}]* %x) {
 entry:
         %p = bitcast [100 x {i8,i8,i8}]* %x to i8*
-        %q = getelementptr i8* %p, i32 -4
+        %q = getelementptr i8, i8* %p, i32 -4
         ret i8* %q
 }
diff --git a/test/Transforms/InstCombine/2007-12-28-IcmpSub2.ll b/test/Transforms/InstCombine/2007-12-28-IcmpSub2.ll
index 8721c83521bf..7260c001b0db 100644
--- a/test/Transforms/InstCombine/2007-12-28-IcmpSub2.ll
+++ b/test/Transforms/InstCombine/2007-12-28-IcmpSub2.ll
@@ -4,7 +4,7 @@ define i32 @test1() {
 entry:
 	%z = alloca i32
 	store i32 0, i32* %z
-	%tmp = load i32* %z
+	%tmp = load i32, i32* %z
 	%sub = sub i32 %tmp, 1
 	%cmp = icmp ule i32 %sub, 0
 	%retval = select i1 %cmp, i32 0, i32 1
@@ -15,7 +15,7 @@ define i32 @test2() {
 entry:
 	%z = alloca i32
 	store i32 0, i32* %z
-	%tmp = load i32* %z
+	%tmp = load i32, i32* %z
 	%sub = sub i32 %tmp, 1
 	%cmp = icmp ugt i32 %sub, 0
 	%retval = select i1 %cmp, i32 1, i32 0
@@ -26,7 +26,7 @@ define i32 @test3() {
 entry:
 	%z = alloca i32
 	store i32 0, i32* %z
-	%tmp = load i32* %z
+	%tmp = load i32, i32* %z
 	%sub = sub i32 %tmp, 1
 	%cmp = icmp slt i32 %sub, 0
 	%retval = select i1 %cmp, i32 1, i32 0
@@ -37,7 +37,7 @@ define i32 @test4() {
 entry:
 	%z = alloca i32
 	store i32 0, i32* %z
-	%tmp = load i32* %z
+	%tmp = load i32, i32* %z
 	%sub = sub i32 %tmp, 1
 	%cmp = icmp sle i32 %sub, 0
 	%retval = select i1 %cmp, i32 1, i32 0
@@ -48,7 +48,7 @@ define i32 @test5() {
 entry:
 	%z = alloca i32
 	store i32 0, i32* %z
-	%tmp = load i32* %z
+	%tmp = load i32, i32* %z
 	%sub = sub i32 %tmp, 1
 	%cmp = icmp sge i32 %sub, 0
 	%retval = select i1 %cmp, i32 0, i32 1
@@ -59,7 +59,7 @@ define i32 @test6() {
 entry:
 	%z = alloca i32
 	store i32 0, i32* %z
-	%tmp = load i32* %z
+	%tmp = load i32, i32* %z
 	%sub = sub i32 %tmp, 1
 	%cmp = icmp sgt i32 %sub, 0
 	%retval = select i1 %cmp, i32 0, i32 1
@@ -70,7 +70,7 @@ define i32 @test7() {
 entry:
 	%z = alloca i32
 	store i32 0, i32* %z
-	%tmp = load i32* %z
+	%tmp = load i32, i32* %z
 	%sub = sub i32 %tmp, 1
 	%cmp = icmp eq i32 %sub, 0
 	%retval = select i1 %cmp, i32 0, i32 1
@@ -81,7 +81,7 @@ define i32 @test8() {
 entry:
 	%z = alloca i32
 	store i32 0, i32* %z
-	%tmp = load i32* %z
+	%tmp = load i32, i32* %z
 	%sub = sub i32 %tmp, 1
 	%cmp = icmp ne i32 %sub, 0
 	%retval = select i1 %cmp, i32 1, i32 0
diff --git a/test/Transforms/InstCombine/2008-01-14-VarArgTrampoline.ll b/test/Transforms/InstCombine/2008-01-14-VarArgTrampoline.ll
index aacea9df5b31..b111b85d59f0 100644
--- a/test/Transforms/InstCombine/2008-01-14-VarArgTrampoline.ll
+++ b/test/Transforms/InstCombine/2008-01-14-VarArgTrampoline.ll
@@ -12,15 +12,15 @@ define i32 @nest(i32 %n) {
 entry:
 	%FRAME.0 = alloca %struct.FRAME.nest, align 8		; <%struct.FRAME.nest*> [#uses=3]
 	%TRAMP.216 = alloca [10 x i8], align 16		; <[10 x i8]*> [#uses=1]
-	%TRAMP.216.sub = getelementptr [10 x i8]* %TRAMP.216, i32 0, i32 0		; <i8*> [#uses=1]
-	%tmp3 = getelementptr %struct.FRAME.nest* %FRAME.0, i32 0, i32 0		; <i32*> [#uses=1]
+	%TRAMP.216.sub = getelementptr [10 x i8], [10 x i8]* %TRAMP.216, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp3 = getelementptr %struct.FRAME.nest, %struct.FRAME.nest* %FRAME.0, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 %n, i32* %tmp3, align 8
 	%FRAME.06 = bitcast %struct.FRAME.nest* %FRAME.0 to i8*		; <i8*> [#uses=1]
 	call void @llvm.init.trampoline( i8* %TRAMP.216.sub, i8* bitcast (i32 (%struct.FRAME.nest*, ...)* @f to i8*), i8* %FRAME.06 )		; <i8*> [#uses=1]
         %tramp = call i8* @llvm.adjust.trampoline( i8* %TRAMP.216.sub)
-	%tmp7 = getelementptr %struct.FRAME.nest* %FRAME.0, i32 0, i32 1		; <i32 (...)**> [#uses=1]
+	%tmp7 = getelementptr %struct.FRAME.nest, %struct.FRAME.nest* %FRAME.0, i32 0, i32 1		; <i32 (...)**> [#uses=1]
 	%tmp89 = bitcast i8* %tramp to i32 (...)*		; <i32 (...)*> [#uses=2]
 	store i32 (...)* %tmp89, i32 (...)** %tmp7, align 8
-	%tmp2.i = call i32 (...)* %tmp89( i32 zeroext 0 )		; <i32> [#uses=1]
+	%tmp2.i = call i32 (...) %tmp89( i32 zeroext 0 )		; <i32> [#uses=1]
 	ret i32 %tmp2.i
 }
diff --git a/test/Transforms/InstCombine/2008-03-13-IntToPtr.ll b/test/Transforms/InstCombine/2008-03-13-IntToPtr.ll
index 0fa4d715f289..d086f4b63b71 100644
--- a/test/Transforms/InstCombine/2008-03-13-IntToPtr.ll
+++ b/test/Transforms/InstCombine/2008-03-13-IntToPtr.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -instcombine -S | grep "16" | count 1
 
 define i8* @bork(i8** %qux) {
-  %tmp275 = load i8** %qux, align 1
+  %tmp275 = load i8*, i8** %qux, align 1
   %tmp275276 = ptrtoint i8* %tmp275 to i32
   %tmp277 = add i32 %tmp275276, 16
   %tmp277278 = inttoptr i32 %tmp277 to i8*
diff --git a/test/Transforms/InstCombine/2008-04-22-ByValBitcast.ll b/test/Transforms/InstCombine/2008-04-22-ByValBitcast.ll
index aa38065a7149..1ea0998bf70e 100644
--- a/test/Transforms/InstCombine/2008-04-22-ByValBitcast.ll
+++ b/test/Transforms/InstCombine/2008-04-22-ByValBitcast.ll
@@ -8,7 +8,7 @@ target triple = "i386-apple-darwin9"
 define void @foo(i8* %context) nounwind  {
 entry:
 	%tmp1 = bitcast i8* %context to %struct.NSRect*		; <%struct.NSRect*> [#uses=1]
-	call void (i32, ...)* @bar( i32 3, %struct.NSRect* byval align 4  %tmp1 ) nounwind 
+	call void (i32, ...) @bar( i32 3, %struct.NSRect* byval align 4  %tmp1 ) nounwind 
 	ret void
 }
 
diff --git a/test/Transforms/InstCombine/2008-04-29-VolatileLoadDontMerge.ll b/test/Transforms/InstCombine/2008-04-29-VolatileLoadDontMerge.ll
index fd0217e9f4d7..af662bda1e6e 100644
--- a/test/Transforms/InstCombine/2008-04-29-VolatileLoadDontMerge.ll
+++ b/test/Transforms/InstCombine/2008-04-29-VolatileLoadDontMerge.ll
@@ -6,7 +6,7 @@ target triple = "i386-apple-darwin8"
 define i32 @main() nounwind  {
 entry:
 	%tmp93 = icmp slt i32 0, 10		; <i1> [#uses=0]
-	%tmp34 = load volatile i32* @g_1, align 4		; <i32> [#uses=1]
+	%tmp34 = load volatile i32, i32* @g_1, align 4		; <i32> [#uses=1]
 	br label %bb
 
 bb:		; preds = %bb, %entry
@@ -16,7 +16,7 @@ bb:		; preds = %bb, %entry
 	store volatile i32 %tmp4, i32* @g_1, align 4
 	%tmp6 = add i32 %b.0.reg2mem.0, 1		; <i32> [#uses=2]
 	%tmp9 = icmp slt i32 %tmp6, 10		; <i1> [#uses=1]
-	%tmp3 = load volatile i32* @g_1, align 4		; <i32> [#uses=1]
+	%tmp3 = load volatile i32, i32* @g_1, align 4		; <i32> [#uses=1]
 	br i1 %tmp9, label %bb, label %bb11
 
 bb11:		; preds = %bb
diff --git a/test/Transforms/InstCombine/2008-04-29-VolatileLoadMerge.ll b/test/Transforms/InstCombine/2008-04-29-VolatileLoadMerge.ll
index 8022414d6fc9..3c67e513bcc1 100644
--- a/test/Transforms/InstCombine/2008-04-29-VolatileLoadMerge.ll
+++ b/test/Transforms/InstCombine/2008-04-29-VolatileLoadMerge.ll
@@ -7,11 +7,11 @@ target triple = "i386-apple-darwin8"
 define i32 @main(i32 %i) nounwind  {
 entry:
 	%tmp93 = icmp slt i32 %i, 10		; <i1> [#uses=0]
-	%tmp34 = load volatile i32* @g_1, align 4		; <i32> [#uses=1]
+	%tmp34 = load volatile i32, i32* @g_1, align 4		; <i32> [#uses=1]
 	br i1 %tmp93, label %bb11, label %bb
 
 bb:		; preds = %bb, %entry
-	%tmp3 = load volatile i32* @g_1, align 4		; <i32> [#uses=1]
+	%tmp3 = load volatile i32, i32* @g_1, align 4		; <i32> [#uses=1]
 	br label %bb11
 
 bb11:		; preds = %bb
diff --git a/test/Transforms/InstCombine/2008-05-08-LiveStoreDelete.ll b/test/Transforms/InstCombine/2008-05-08-LiveStoreDelete.ll
index 7a1c84474153..907382093d11 100644
--- a/test/Transforms/InstCombine/2008-05-08-LiveStoreDelete.ll
+++ b/test/Transforms/InstCombine/2008-05-08-LiveStoreDelete.ll
@@ -7,14 +7,14 @@ define i32 @a() nounwind  {
 entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	%tmp1 = call i8* @malloc( i32 10 ) nounwind 		; <i8*> [#uses=5]
-	%tmp3 = getelementptr i8* %tmp1, i32 1		; <i8*> [#uses=1]
+	%tmp3 = getelementptr i8, i8* %tmp1, i32 1		; <i8*> [#uses=1]
 	store i8 0, i8* %tmp3, align 1
-	%tmp5 = getelementptr i8* %tmp1, i32 0		; <i8*> [#uses=1]
+	%tmp5 = getelementptr i8, i8* %tmp1, i32 0		; <i8*> [#uses=1]
 	store i8 1, i8* %tmp5, align 1
 	%tmp7 = call i32 @strlen( i8* %tmp1 ) nounwind readonly 		; <i32> [#uses=1]
-	%tmp9 = getelementptr i8* %tmp1, i32 0		; <i8*> [#uses=1]
+	%tmp9 = getelementptr i8, i8* %tmp1, i32 0		; <i8*> [#uses=1]
 	store i8 0, i8* %tmp9, align 1
-	%tmp11 = call i32 (...)* @b( i8* %tmp1 ) nounwind 		; <i32> [#uses=0]
+	%tmp11 = call i32 (...) @b( i8* %tmp1 ) nounwind 		; <i32> [#uses=0]
 	ret i32 %tmp7
 }
 
diff --git a/test/Transforms/InstCombine/2008-05-08-StrLenSink.ll b/test/Transforms/InstCombine/2008-05-08-StrLenSink.ll
index d266164fd870..ce1923338c6b 100644
--- a/test/Transforms/InstCombine/2008-05-08-StrLenSink.ll
+++ b/test/Transforms/InstCombine/2008-05-08-StrLenSink.ll
@@ -7,18 +7,18 @@ define i32 @a() nounwind  {
 entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	%tmp1 = call i8* @malloc( i32 10 ) nounwind 		; <i8*> [#uses=5]
-	%tmp3 = getelementptr i8* %tmp1, i32 1		; <i8*> [#uses=1]
+	%tmp3 = getelementptr i8, i8* %tmp1, i32 1		; <i8*> [#uses=1]
 	store i8 0, i8* %tmp3, align 1
-	%tmp5 = getelementptr i8* %tmp1, i32 0		; <i8*> [#uses=1]
+	%tmp5 = getelementptr i8, i8* %tmp1, i32 0		; <i8*> [#uses=1]
 	store i8 1, i8* %tmp5, align 1
 ; CHECK: store
 ; CHECK: store
 ; CHECK-NEXT: strlen
 ; CHECK-NEXT: store
 	%tmp7 = call i32 @strlen( i8* %tmp1 ) nounwind readonly 		; <i32> [#uses=1]
-	%tmp9 = getelementptr i8* %tmp1, i32 0		; <i8*> [#uses=1]
+	%tmp9 = getelementptr i8, i8* %tmp1, i32 0		; <i8*> [#uses=1]
 	store i8 0, i8* %tmp9, align 1
-	%tmp11 = call i32 (...)* @b( i8* %tmp1 ) nounwind 		; <i32> [#uses=0]
+	%tmp11 = call i32 (...) @b( i8* %tmp1 ) nounwind 		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
diff --git a/test/Transforms/InstCombine/2008-05-09-SinkOfInvoke.ll b/test/Transforms/InstCombine/2008-05-09-SinkOfInvoke.ll
index f6eb24843fb8..722f8f0fabbd 100644
--- a/test/Transforms/InstCombine/2008-05-09-SinkOfInvoke.ll
+++ b/test/Transforms/InstCombine/2008-05-09-SinkOfInvoke.ll
@@ -23,8 +23,8 @@ invcont31:		; preds = %invcont
 			to label %invcont37 unwind label %lpad		; <i32**> [#uses=1]
 
 invcont37:		; preds = %invcont31
-	%tmp39 = load i32** %tmp38, align 8		; <i32*> [#uses=1]
-	%tmp41 = getelementptr %"struct.std::ctype<char>"* %this, i32 0, i32 4		; <i32**> [#uses=1]
+	%tmp39 = load i32*, i32** %tmp38, align 8		; <i32*> [#uses=1]
+	%tmp41 = getelementptr %"struct.std::ctype<char>", %"struct.std::ctype<char>"* %this, i32 0, i32 4		; <i32**> [#uses=1]
 	store i32* %tmp39, i32** %tmp41, align 8
 	ret void
 
diff --git a/test/Transforms/InstCombine/2008-05-17-InfLoop.ll b/test/Transforms/InstCombine/2008-05-17-InfLoop.ll
index 2939a4821654..af0f2a45e7ec 100644
--- a/test/Transforms/InstCombine/2008-05-17-InfLoop.ll
+++ b/test/Transforms/InstCombine/2008-05-17-InfLoop.ll
@@ -10,11 +10,11 @@ entry:
 	%blockSize100k = alloca i32		; <i32*> [#uses=2]
 	store i32 %0, i32* %blockSize100k
 	%n = alloca i32		; <i32*> [#uses=2]
-	load i32* %blockSize100k		; <i32>:1 [#uses=1]
+	load i32, i32* %blockSize100k		; <i32>:1 [#uses=1]
 	store i32 %1, i32* %n
-	load i32* %n		; <i32>:2 [#uses=1]
+	load i32, i32* %n		; <i32>:2 [#uses=1]
 	add i32 %2, 2		; <i32>:3 [#uses=1]
-	mul i32 %3, ptrtoint (i32* getelementptr (i32* null, i32 1) to i32)		; <i32>:4 [#uses=1]
+	mul i32 %3, ptrtoint (i32* getelementptr (i32, i32* null, i32 1) to i32)		; <i32>:4 [#uses=1]
 	call void @BZALLOC( i32 %4 )
 	br label %return
 
diff --git a/test/Transforms/InstCombine/2008-05-23-CompareFold.ll b/test/Transforms/InstCombine/2008-05-23-CompareFold.ll
index b72967767558..b10aac96599f 100644
--- a/test/Transforms/InstCombine/2008-05-23-CompareFold.ll
+++ b/test/Transforms/InstCombine/2008-05-23-CompareFold.ll
@@ -5,7 +5,7 @@
 ; CHECK: ret i1 false
 define i1 @f(i8* %x) {
 entry:
-       %tmp462 = load i8* %x, align 1          ; <i8> [#uses=1]
+       %tmp462 = load i8, i8* %x, align 1          ; <i8> [#uses=1]
        %tmp462463 = sitofp i8 %tmp462 to float         ; <float> [#uses=1]
        %tmp464 = fcmp ugt float %tmp462463, 0x47EFFFFFE0000000         ; <i1>
        ret i1 %tmp464
diff --git a/test/Transforms/InstCombine/2008-06-08-ICmpPHI.ll b/test/Transforms/InstCombine/2008-06-08-ICmpPHI.ll
index ec946238d897..7e8341b99f78 100644
--- a/test/Transforms/InstCombine/2008-06-08-ICmpPHI.ll
+++ b/test/Transforms/InstCombine/2008-06-08-ICmpPHI.ll
@@ -7,28 +7,28 @@ entry:
 bb:		; preds = %bb16, %entry
 	%i.0 = phi i32 [ 0, %entry ], [ %indvar.next, %somebb ]		; <i32> [#uses=1]
 	%x.0 = phi i32 [ 37, %entry ], [ %tmp17, %somebb ]		; <i32> [#uses=1]
-	%tmp = tail call i32 (...)* @bork( ) nounwind 		; <i32> [#uses=0]
-	%tmp1 = tail call i32 (...)* @bork( ) nounwind 		; <i32> [#uses=0]
-	%tmp2 = tail call i32 (...)* @bork( ) nounwind 		; <i32> [#uses=1]
+	%tmp = tail call i32 (...) @bork( ) nounwind 		; <i32> [#uses=0]
+	%tmp1 = tail call i32 (...) @bork( ) nounwind 		; <i32> [#uses=0]
+	%tmp2 = tail call i32 (...) @bork( ) nounwind 		; <i32> [#uses=1]
 	%tmp3 = icmp eq i32 %tmp2, 0		; <i1> [#uses=1]
 	br i1 %tmp3, label %bb7, label %bb5
 
 bb5:		; preds = %bb
-	%tmp6 = tail call i32 (...)* @bork( ) nounwind 		; <i32> [#uses=0]
+	%tmp6 = tail call i32 (...) @bork( ) nounwind 		; <i32> [#uses=0]
 	br label %bb7
 
 bb7:		; preds = %bb5, %bb
-	%tmp8 = tail call i32 (...)* @bork( ) nounwind 		; <i32> [#uses=0]
-	%tmp9 = tail call i32 (...)* @bork( ) nounwind 		; <i32> [#uses=0]
+	%tmp8 = tail call i32 (...) @bork( ) nounwind 		; <i32> [#uses=0]
+	%tmp9 = tail call i32 (...) @bork( ) nounwind 		; <i32> [#uses=0]
 	%tmp11 = icmp eq i32 %x.0, 37		; <i1> [#uses=1]
 	br i1 %tmp11, label %bb14, label %bb16
 
 bb14:		; preds = %bb7
-	%tmp15 = tail call i32 (...)* @bar( ) nounwind 		; <i32> [#uses=0]
+	%tmp15 = tail call i32 (...) @bar( ) nounwind 		; <i32> [#uses=0]
 	br label %bb16
 
 bb16:		; preds = %bb14, %bb7
-	%tmp17 = tail call i32 (...)* @zap( ) nounwind 		; <i32> [#uses=1]
+	%tmp17 = tail call i32 (...) @zap( ) nounwind 		; <i32> [#uses=1]
 	%indvar.next = add i32 %i.0, 1		; <i32> [#uses=2]
 	%exitcond = icmp eq i32 %indvar.next, 42		; <i1> [#uses=1]
 	br i1 %exitcond, label %return, label %somebb
diff --git a/test/Transforms/InstCombine/2008-06-19-UncondLoad.ll b/test/Transforms/InstCombine/2008-06-19-UncondLoad.ll
index 05f1c5200081..c3aab464b87e 100644
--- a/test/Transforms/InstCombine/2008-06-19-UncondLoad.ll
+++ b/test/Transforms/InstCombine/2008-06-19-UncondLoad.ll
@@ -4,13 +4,13 @@
 declare i32 @x(i32*)
 define i32 @b(i32* %a, i32* %b) {
 entry:
-        %tmp1 = load i32* %a            
-        %tmp3 = load i32* %b           
+        %tmp1 = load i32, i32* %a            
+        %tmp3 = load i32, i32* %b           
         %add = add i32 %tmp1, %tmp3   
         %call = call i32 @x( i32* %a )
         %tobool = icmp ne i32 %add, 0
 	; not safe to turn into an uncond load
         %cond = select i1 %tobool, i32* %b, i32* %a             
-        %tmp8 = load i32* %cond       
+        %tmp8 = load i32, i32* %cond       
         ret i32 %tmp8
 }
diff --git a/test/Transforms/InstCombine/2008-06-24-StackRestore.ll b/test/Transforms/InstCombine/2008-06-24-StackRestore.ll
index 9c4c1b538c4b..f963b009671b 100644
--- a/test/Transforms/InstCombine/2008-06-24-StackRestore.ll
+++ b/test/Transforms/InstCombine/2008-06-24-StackRestore.ll
@@ -27,7 +27,7 @@ bb44:		; preds = %bb44, %entry
 	%tmp27 = alloca i32, i32 %tmp5		; <i32*> [#uses=3]
 	%tmpcast = bitcast i32* %tmp27 to i8*		; <i8*> [#uses=1]
 	store i32 1, i32* %tmp27, align 4
-	%tmp34 = getelementptr i32* %tmp27, i32 %tmp4		; <i32*> [#uses=1]
+	%tmp34 = getelementptr i32, i32* %tmp27, i32 %tmp4		; <i32*> [#uses=1]
 	store i32 2, i32* %tmp34, align 4
 	store volatile i8* %tmpcast, i8** @p, align 4
 	%exitcond = icmp eq i32 %tmp3857, 999999		; <i1> [#uses=1]
diff --git a/test/Transforms/InstCombine/2008-07-08-VolatileLoadMerge.ll b/test/Transforms/InstCombine/2008-07-08-VolatileLoadMerge.ll
index dcf4befa8605..17ec9cd1d82b 100644
--- a/test/Transforms/InstCombine/2008-07-08-VolatileLoadMerge.ll
+++ b/test/Transforms/InstCombine/2008-07-08-VolatileLoadMerge.ll
@@ -7,7 +7,7 @@ target triple = "i386-apple-darwin8"
 define i32 @main() nounwind  {
 entry:
 	%tmp93 = icmp slt i32 0, 10		; <i1> [#uses=0]
-	%tmp34 = load volatile i32* @g_1, align 4		; <i32> [#uses=1]
+	%tmp34 = load volatile i32, i32* @g_1, align 4		; <i32> [#uses=1]
 	br label %bb
 
 bb:		; preds = %bb, %entry
@@ -17,7 +17,7 @@ bb:		; preds = %bb, %entry
 	store volatile i32 %tmp4, i32* @g_1, align 4
 	%tmp6 = add i32 %b.0.reg2mem.0, 1		; <i32> [#uses=2]
 	%tmp9 = icmp slt i32 %tmp6, 10		; <i1> [#uses=1]
-	%tmp3 = load volatile i32* @g_1, align 4		; <i32> [#uses=1]
+	%tmp3 = load volatile i32, i32* @g_1, align 4		; <i32> [#uses=1]
 	br i1 %tmp9, label %bb, label %bb11
 
 bb11:		; preds = %bb
diff --git a/test/Transforms/InstCombine/2008-08-05-And.ll b/test/Transforms/InstCombine/2008-08-05-And.ll
index 9773c2d76249..91f1c0b0a986 100644
--- a/test/Transforms/InstCombine/2008-08-05-And.ll
+++ b/test/Transforms/InstCombine/2008-08-05-And.ll
@@ -6,8 +6,8 @@ entry:
         br label %bb
 
 bb:
-	%g1 = getelementptr i8* %x, i32 0
-        %l1 = load i8* %g1, align 1
+	%g1 = getelementptr i8, i8* %x, i32 0
+        %l1 = load i8, i8* %g1, align 1
 	%s1 = sub i8 %l1, 6
 	%c1 = icmp ugt i8 %s1, 2
 	%s2 = sub i8 %l1, 10
diff --git a/test/Transforms/InstCombine/2009-01-08-AlignAlloca.ll b/test/Transforms/InstCombine/2009-01-08-AlignAlloca.ll
index 50ea2f42b0ca..9994b588b21c 100644
--- a/test/Transforms/InstCombine/2009-01-08-AlignAlloca.ll
+++ b/test/Transforms/InstCombine/2009-01-08-AlignAlloca.ll
@@ -12,16 +12,16 @@ entry:
 	%iospec = alloca %struct.Key		; <%struct.Key*> [#uses=3]
 	%ret = alloca i32		; <i32*> [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
-	%0 = getelementptr %struct.Key* %iospec, i32 0, i32 0		; <{ i32, i32 }*> [#uses=2]
-	%1 = getelementptr { i32, i32 }* %0, i32 0, i32 0		; <i32*> [#uses=1]
+	%0 = getelementptr %struct.Key, %struct.Key* %iospec, i32 0, i32 0		; <{ i32, i32 }*> [#uses=2]
+	%1 = getelementptr { i32, i32 }, { i32, i32 }* %0, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 0, i32* %1, align 4
-	%2 = getelementptr { i32, i32 }* %0, i32 0, i32 1		; <i32*> [#uses=1]
+	%2 = getelementptr { i32, i32 }, { i32, i32 }* %0, i32 0, i32 1		; <i32*> [#uses=1]
 	store i32 0, i32* %2, align 4
-	%3 = getelementptr %struct.Key* %iospec, i32 0, i32 0		; <{ i32, i32 }*> [#uses=1]
+	%3 = getelementptr %struct.Key, %struct.Key* %iospec, i32 0, i32 0		; <{ i32, i32 }*> [#uses=1]
 	%4 = bitcast { i32, i32 }* %3 to i64*		; <i64*> [#uses=1]
 	store i64 %key_token2, i64* %4, align 4
-	%5 = call i32 (...)* @foo(%struct.Key* byval align 4 %iospec, i32* %ret) nounwind		; <i32> [#uses=0]
-	%6 = load i32* %ret, align 4		; <i32> [#uses=1]
+	%5 = call i32 (...) @foo(%struct.Key* byval align 4 %iospec, i32* %ret) nounwind		; <i32> [#uses=0]
+	%6 = load i32, i32* %ret, align 4		; <i32> [#uses=1]
 	ret i32 %6
 }
 
diff --git a/test/Transforms/InstCombine/2009-01-19-fmod-constant-float-specials.ll b/test/Transforms/InstCombine/2009-01-19-fmod-constant-float-specials.ll
index 68c51b43fc3a..b9aa0a254972 100644
--- a/test/Transforms/InstCombine/2009-01-19-fmod-constant-float-specials.ll
+++ b/test/Transforms/InstCombine/2009-01-19-fmod-constant-float-specials.ll
@@ -15,12 +15,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 0x7FF0000000000000, float* %x, align 4
 	store float 0x7FF8000000000000, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
@@ -36,12 +36,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 0x7FF0000000000000, float* %x, align 4
 	store float 0.000000e+00, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
@@ -55,12 +55,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 0x7FF0000000000000, float* %x, align 4
 	store float 3.500000e+00, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
@@ -74,12 +74,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 0x7FF0000000000000, float* %x, align 4
 	store float 0x7FF0000000000000, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
@@ -93,12 +93,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 0x7FF8000000000000, float* %x, align 4
 	store float 0x7FF0000000000000, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
@@ -112,12 +112,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 0x7FF8000000000000, float* %x, align 4
 	store float 0.000000e+00, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
@@ -131,12 +131,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 0x7FF8000000000000, float* %x, align 4
 	store float 3.500000e+00, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
@@ -150,12 +150,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 0x7FF8000000000000, float* %x, align 4
 	store float 0x7FF8000000000000, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
@@ -169,12 +169,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 0.000000e+00, float* %x, align 4
 	store float 0x7FF8000000000000, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
@@ -188,12 +188,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 0.000000e+00, float* %x, align 4
 	store float 0x7FF0000000000000, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
@@ -207,12 +207,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 0.000000e+00, float* %x, align 4
 	store float 0.000000e+00, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
@@ -226,12 +226,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 0.000000e+00, float* %x, align 4
 	store float 3.500000e+00, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
@@ -245,12 +245,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 3.500000e+00, float* %x, align 4
 	store float 0x7FF8000000000000, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
@@ -264,12 +264,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 3.500000e+00, float* %x, align 4
 	store float 0x7FF0000000000000, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
@@ -283,12 +283,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 3.500000e+00, float* %x, align 4
 	store float 0.000000e+00, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
@@ -302,12 +302,12 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store float 3.500000e+00, float* %x, align 4
 	store float 3.500000e+00, float* %y, align 4
-	%0 = load float* %y, align 4		; <float> [#uses=1]
+	%0 = load float, float* %y, align 4		; <float> [#uses=1]
 	%1 = fpext float %0 to double		; <double> [#uses=1]
-	%2 = load float* %x, align 4		; <float> [#uses=1]
+	%2 = load float, float* %x, align 4		; <float> [#uses=1]
 	%3 = fpext float %2 to double		; <double> [#uses=1]
 	%4 = frem double %3, %1		; <double> [#uses=1]
-	%5 = call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
+	%5 = call i32 (i8*, ...) @printf(i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), double %4) nounwind		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
diff --git a/test/Transforms/InstCombine/2009-01-19-fmod-constant-float.ll b/test/Transforms/InstCombine/2009-01-19-fmod-constant-float.ll
index 6bc7ce34d1c2..5adcb6bfa071 100644
--- a/test/Transforms/InstCombine/2009-01-19-fmod-constant-float.ll
+++ b/test/Transforms/InstCombine/2009-01-19-fmod-constant-float.ll
@@ -14,12 +14,12 @@ entry:
 	%1 = frem double 1.000000e-01, 1.000000e+00	; <double> [#uses=1]
 	%2 = fptrunc double %1 to float		; <float> [#uses=1]
 	store float %2, float* %0, align 4
-	%3 = load float* %0, align 4		; <float> [#uses=1]
+	%3 = load float, float* %0, align 4		; <float> [#uses=1]
 	store float %3, float* %retval, align 4
 	br label %return
 
 return:		; preds = %entry
-	%retval1 = load float* %retval		; <float> [#uses=1]
+	%retval1 = load float, float* %retval		; <float> [#uses=1]
 	ret float %retval1
 }
 
@@ -31,12 +31,12 @@ entry:
 	%1 = frem double -1.000000e-01, 1.000000e+00	; <double> [#uses=1]
 	%2 = fptrunc double %1 to float		; <float> [#uses=1]
 	store float %2, float* %0, align 4
-	%3 = load float* %0, align 4		; <float> [#uses=1]
+	%3 = load float, float* %0, align 4		; <float> [#uses=1]
 	store float %3, float* %retval, align 4
 	br label %return
 
 return:		; preds = %entry
-	%retval1 = load float* %retval		; <float> [#uses=1]
+	%retval1 = load float, float* %retval		; <float> [#uses=1]
 	ret float %retval1
 }
 
@@ -48,12 +48,12 @@ entry:
 	%1 = frem double 1.000000e-01, -1.000000e+00	; <double> [#uses=1]
 	%2 = fptrunc double %1 to float		; <float> [#uses=1]
 	store float %2, float* %0, align 4
-	%3 = load float* %0, align 4		; <float> [#uses=1]
+	%3 = load float, float* %0, align 4		; <float> [#uses=1]
 	store float %3, float* %retval, align 4
 	br label %return
 
 return:		; preds = %entry
-	%retval1 = load float* %retval		; <float> [#uses=1]
+	%retval1 = load float, float* %retval		; <float> [#uses=1]
 	ret float %retval1
 }
 
@@ -65,11 +65,11 @@ entry:
 	%1 = frem double -1.000000e-01, -1.000000e+00	; <double> [#uses=1]
 	%2 = fptrunc double %1 to float		; <float> [#uses=1]
 	store float %2, float* %0, align 4
-	%3 = load float* %0, align 4		; <float> [#uses=1]
+	%3 = load float, float* %0, align 4		; <float> [#uses=1]
 	store float %3, float* %retval, align 4
 	br label %return
 
 return:		; preds = %entry
-	%retval1 = load float* %retval		; <float> [#uses=1]
+	%retval1 = load float, float* %retval		; <float> [#uses=1]
 	ret float %retval1
 }
diff --git a/test/Transforms/InstCombine/2009-01-24-EmptyStruct.ll b/test/Transforms/InstCombine/2009-01-24-EmptyStruct.ll
index 4b64b4872918..3f3535b363d7 100644
--- a/test/Transforms/InstCombine/2009-01-24-EmptyStruct.ll
+++ b/test/Transforms/InstCombine/2009-01-24-EmptyStruct.ll
@@ -11,7 +11,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define void @handle_event(%struct.inode* %bar) nounwind {
 entry:
-	%0 = getelementptr %struct.inode* %bar, i64 -1, i32 1, i32 1		; <%struct.rwlock_t*> [#uses=1]
+	%0 = getelementptr %struct.inode, %struct.inode* %bar, i64 -1, i32 1, i32 1		; <%struct.rwlock_t*> [#uses=1]
 	%1 = bitcast %struct.rwlock_t* %0 to i32*		; <i32*> [#uses=1]
 	store i32 1, i32* %1, align 4
 	ret void
diff --git a/test/Transforms/InstCombine/2009-02-20-InstCombine-SROA.ll b/test/Transforms/InstCombine/2009-02-20-InstCombine-SROA.ll
index 9146a8ee0117..0f8b38c8e9c1 100644
--- a/test/Transforms/InstCombine/2009-02-20-InstCombine-SROA.ll
+++ b/test/Transforms/InstCombine/2009-02-20-InstCombine-SROA.ll
@@ -27,53 +27,53 @@ entry:
   %4 = alloca i32
   %"alloca point" = bitcast i32 0 to i32
   store i32 42, i32* %4, align 4
-  %5 = getelementptr %"struct.std::vector<int,std::allocator<int> >"* %X, i32 0, i32 0
-  %6 = getelementptr %"struct.std::_Vector_base<int,std::allocator<int> >"* %5, i32 0, i32 0
-  %7 = getelementptr %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl"* %6, i32 0, i32 1
-  %8 = load i32** %7, align 4
-  %9 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %3, i32 0, i32 0
+  %5 = getelementptr %"struct.std::vector<int,std::allocator<int> >", %"struct.std::vector<int,std::allocator<int> >"* %X, i32 0, i32 0
+  %6 = getelementptr %"struct.std::_Vector_base<int,std::allocator<int> >", %"struct.std::_Vector_base<int,std::allocator<int> >"* %5, i32 0, i32 0
+  %7 = getelementptr %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl", %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl"* %6, i32 0, i32 1
+  %8 = load i32*, i32** %7, align 4
+  %9 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %3, i32 0, i32 0
   store i32* %8, i32** %9, align 4
-  %10 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %3, i32 0, i32 0
-  %11 = load i32** %10, align 4
+  %10 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %3, i32 0, i32 0
+  %11 = load i32*, i32** %10, align 4
   %tmp2.i = ptrtoint i32* %11 to i32
   %tmp1.i = inttoptr i32 %tmp2.i to i32*
   %tmp3 = ptrtoint i32* %tmp1.i to i32
   %tmp2 = inttoptr i32 %tmp3 to i32*
-  %12 = getelementptr %"struct.std::vector<int,std::allocator<int> >"* %X, i32 0, i32 0
-  %13 = getelementptr %"struct.std::_Vector_base<int,std::allocator<int> >"* %12, i32 0, i32 0
-  %14 = getelementptr %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl"* %13, i32 0, i32 0
-  %15 = load i32** %14, align 4
-  %16 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %0, i32 0, i32 0
+  %12 = getelementptr %"struct.std::vector<int,std::allocator<int> >", %"struct.std::vector<int,std::allocator<int> >"* %X, i32 0, i32 0
+  %13 = getelementptr %"struct.std::_Vector_base<int,std::allocator<int> >", %"struct.std::_Vector_base<int,std::allocator<int> >"* %12, i32 0, i32 0
+  %14 = getelementptr %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl", %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl"* %13, i32 0, i32 0
+  %15 = load i32*, i32** %14, align 4
+  %16 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %0, i32 0, i32 0
   store i32* %15, i32** %16, align 4
-  %17 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %0, i32 0, i32 0
-  %18 = load i32** %17, align 4
+  %17 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %0, i32 0, i32 0
+  %18 = load i32*, i32** %17, align 4
   %tmp2.i17 = ptrtoint i32* %18 to i32
   %tmp1.i18 = inttoptr i32 %tmp2.i17 to i32*
   %tmp8 = ptrtoint i32* %tmp1.i18 to i32
   %tmp6 = inttoptr i32 %tmp8 to i32*
-  %19 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i, i32 0, i32 0
+  %19 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i, i32 0, i32 0
   store i32* %tmp6, i32** %19
-  %20 = getelementptr %"struct.std::bidirectional_iterator_tag"* %1, i32 0, i32 0
-  %21 = load i8* %20, align 1
+  %20 = getelementptr %"struct.std::bidirectional_iterator_tag", %"struct.std::bidirectional_iterator_tag"* %1, i32 0, i32 0
+  %21 = load i8, i8* %20, align 1
   %22 = or i8 %21, 0
   %23 = or i8 %22, 0
   %24 = or i8 %23, 0
-  %25 = getelementptr %"struct.std::bidirectional_iterator_tag"* %2, i32 0, i32 0
+  %25 = getelementptr %"struct.std::bidirectional_iterator_tag", %"struct.std::bidirectional_iterator_tag"* %2, i32 0, i32 0
   store i8 0, i8* %25, align 1
-  %elt.i = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i, i32 0, i32 0
-  %val.i = load i32** %elt.i
+  %elt.i = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i, i32 0, i32 0
+  %val.i = load i32*, i32** %elt.i
   %tmp.i = bitcast %"struct.std::bidirectional_iterator_tag"* %unnamed_arg.i to i8*
   %tmp9.i = bitcast %"struct.std::bidirectional_iterator_tag"* %2 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp.i, i8* %tmp9.i, i64 1, i32 1, i1 false)
-  %26 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %26 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
   store i32* %val.i, i32** %26
-  %27 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__last_addr.i.i, i32 0, i32 0
+  %27 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__last_addr.i.i, i32 0, i32 0
   store i32* %tmp2, i32** %27
-  %28 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__last_addr.i.i, i32 0, i32 0
-  %29 = load i32** %28, align 4
+  %28 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__last_addr.i.i, i32 0, i32 0
+  %29 = load i32*, i32** %28, align 4
   %30 = ptrtoint i32* %29 to i32
-  %31 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %32 = load i32** %31, align 4
+  %31 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %32 = load i32*, i32** %31, align 4
   %33 = ptrtoint i32* %32 to i32
   %34 = sub i32 %30, %33
   %35 = ashr i32 %34, 2
@@ -81,85 +81,85 @@ entry:
   br label %bb12.i.i
 
 bb.i.i:                                           ; preds = %bb12.i.i
-  %37 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %38 = load i32** %37, align 4
-  %39 = load i32* %38, align 4
-  %40 = load i32* %4, align 4
+  %37 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %38 = load i32*, i32** %37, align 4
+  %39 = load i32, i32* %38, align 4
+  %40 = load i32, i32* %4, align 4
   %41 = icmp eq i32 %39, %40
   %42 = zext i1 %41 to i8
   %toBool.i.i = icmp ne i8 %42, 0
   br i1 %toBool.i.i, label %bb1.i.i, label %bb2.i.i
 
 bb1.i.i:                                          ; preds = %bb.i.i
-  %43 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %44 = load i32** %43, align 4
+  %43 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %44 = load i32*, i32** %43, align 4
   br label %_ZSt4findIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEiET_S7_S7_RKT0_.exit
 
 bb2.i.i:                                          ; preds = %bb.i.i
-  %45 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %46 = load i32** %45, align 4
-  %47 = getelementptr i32* %46, i64 1
-  %48 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %45 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %46 = load i32*, i32** %45, align 4
+  %47 = getelementptr i32, i32* %46, i64 1
+  %48 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
   store i32* %47, i32** %48, align 4
-  %49 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %50 = load i32** %49, align 4
-  %51 = load i32* %50, align 4
-  %52 = load i32* %4, align 4
+  %49 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %50 = load i32*, i32** %49, align 4
+  %51 = load i32, i32* %50, align 4
+  %52 = load i32, i32* %4, align 4
   %53 = icmp eq i32 %51, %52
   %54 = zext i1 %53 to i8
   %toBool3.i.i = icmp ne i8 %54, 0
   br i1 %toBool3.i.i, label %bb4.i.i, label %bb5.i.i
 
 bb4.i.i:                                          ; preds = %bb2.i.i
-  %55 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %56 = load i32** %55, align 4
+  %55 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %56 = load i32*, i32** %55, align 4
   br label %_ZSt4findIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEiET_S7_S7_RKT0_.exit
 
 bb5.i.i:                                          ; preds = %bb2.i.i
-  %57 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %58 = load i32** %57, align 4
-  %59 = getelementptr i32* %58, i64 1
-  %60 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %57 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %58 = load i32*, i32** %57, align 4
+  %59 = getelementptr i32, i32* %58, i64 1
+  %60 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
   store i32* %59, i32** %60, align 4
-  %61 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %62 = load i32** %61, align 4
-  %63 = load i32* %62, align 4
-  %64 = load i32* %4, align 4
+  %61 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %62 = load i32*, i32** %61, align 4
+  %63 = load i32, i32* %62, align 4
+  %64 = load i32, i32* %4, align 4
   %65 = icmp eq i32 %63, %64
   %66 = zext i1 %65 to i8
   %toBool6.i.i = icmp ne i8 %66, 0
   br i1 %toBool6.i.i, label %bb7.i.i, label %bb8.i.i
 
 bb7.i.i:                                          ; preds = %bb5.i.i
-  %67 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %68 = load i32** %67, align 4
+  %67 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %68 = load i32*, i32** %67, align 4
   br label %_ZSt4findIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEiET_S7_S7_RKT0_.exit
 
 bb8.i.i:                                          ; preds = %bb5.i.i
-  %69 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %70 = load i32** %69, align 4
-  %71 = getelementptr i32* %70, i64 1
-  %72 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %69 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %70 = load i32*, i32** %69, align 4
+  %71 = getelementptr i32, i32* %70, i64 1
+  %72 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
   store i32* %71, i32** %72, align 4
-  %73 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %74 = load i32** %73, align 4
-  %75 = load i32* %74, align 4
-  %76 = load i32* %4, align 4
+  %73 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %74 = load i32*, i32** %73, align 4
+  %75 = load i32, i32* %74, align 4
+  %76 = load i32, i32* %4, align 4
   %77 = icmp eq i32 %75, %76
   %78 = zext i1 %77 to i8
   %toBool9.i.i = icmp ne i8 %78, 0
   br i1 %toBool9.i.i, label %bb10.i.i, label %bb11.i.i
 
 bb10.i.i:                                         ; preds = %bb8.i.i
-  %79 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %80 = load i32** %79, align 4
+  %79 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %80 = load i32*, i32** %79, align 4
   br label %_ZSt4findIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEiET_S7_S7_RKT0_.exit
 
 bb11.i.i:                                         ; preds = %bb8.i.i
-  %81 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %82 = load i32** %81, align 4
-  %83 = getelementptr i32* %82, i64 1
-  %84 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %81 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %82 = load i32*, i32** %81, align 4
+  %83 = getelementptr i32, i32* %82, i64 1
+  %84 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
   store i32* %83, i32** %84, align 4
   %85 = sub i32 %__trip_count.0.i.i, 1
   br label %bb12.i.i
@@ -170,11 +170,11 @@ bb12.i.i:                                         ; preds = %bb11.i.i, %entry
   br i1 %86, label %bb.i.i, label %bb13.i.i
 
 bb13.i.i:                                         ; preds = %bb12.i.i
-  %87 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__last_addr.i.i, i32 0, i32 0
-  %88 = load i32** %87, align 4
+  %87 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__last_addr.i.i, i32 0, i32 0
+  %88 = load i32*, i32** %87, align 4
   %89 = ptrtoint i32* %88 to i32
-  %90 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %91 = load i32** %90, align 4
+  %90 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %91 = load i32*, i32** %90, align 4
   %92 = ptrtoint i32* %91 to i32
   %93 = sub i32 %89, %92
   %94 = ashr i32 %93, 2
@@ -185,77 +185,77 @@ bb13.i.i:                                         ; preds = %bb12.i.i
   ]
 
 bb14.i.i:                                         ; preds = %bb13.i.i
-  %95 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %96 = load i32** %95, align 4
-  %97 = load i32* %96, align 4
-  %98 = load i32* %4, align 4
+  %95 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %96 = load i32*, i32** %95, align 4
+  %97 = load i32, i32* %96, align 4
+  %98 = load i32, i32* %4, align 4
   %99 = icmp eq i32 %97, %98
   %100 = zext i1 %99 to i8
   %toBool15.i.i = icmp ne i8 %100, 0
   br i1 %toBool15.i.i, label %bb16.i.i, label %bb17.i.i
 
 bb16.i.i:                                         ; preds = %bb14.i.i
-  %101 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %102 = load i32** %101, align 4
+  %101 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %102 = load i32*, i32** %101, align 4
   br label %_ZSt4findIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEiET_S7_S7_RKT0_.exit
 
 bb17.i.i:                                         ; preds = %bb14.i.i
-  %103 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %104 = load i32** %103, align 4
-  %105 = getelementptr i32* %104, i64 1
-  %106 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %103 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %104 = load i32*, i32** %103, align 4
+  %105 = getelementptr i32, i32* %104, i64 1
+  %106 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
   store i32* %105, i32** %106, align 4
   br label %bb18.i.i
 
 bb18.i.i:                                         ; preds = %bb17.i.i, %bb13.i.i
-  %107 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %108 = load i32** %107, align 4
-  %109 = load i32* %108, align 4
-  %110 = load i32* %4, align 4
+  %107 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %108 = load i32*, i32** %107, align 4
+  %109 = load i32, i32* %108, align 4
+  %110 = load i32, i32* %4, align 4
   %111 = icmp eq i32 %109, %110
   %112 = zext i1 %111 to i8
   %toBool19.i.i = icmp ne i8 %112, 0
   br i1 %toBool19.i.i, label %bb20.i.i, label %bb21.i.i
 
 bb20.i.i:                                         ; preds = %bb18.i.i
-  %113 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %114 = load i32** %113, align 4
+  %113 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %114 = load i32*, i32** %113, align 4
   br label %_ZSt4findIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEiET_S7_S7_RKT0_.exit
 
 bb21.i.i:                                         ; preds = %bb18.i.i
-  %115 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %116 = load i32** %115, align 4
-  %117 = getelementptr i32* %116, i64 1
-  %118 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %115 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %116 = load i32*, i32** %115, align 4
+  %117 = getelementptr i32, i32* %116, i64 1
+  %118 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
   store i32* %117, i32** %118, align 4
   br label %bb22.i.i
 
 bb22.i.i:                                         ; preds = %bb21.i.i, %bb13.i.i
-  %119 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %120 = load i32** %119, align 4
-  %121 = load i32* %120, align 4
-  %122 = load i32* %4, align 4
+  %119 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %120 = load i32*, i32** %119, align 4
+  %121 = load i32, i32* %120, align 4
+  %122 = load i32, i32* %4, align 4
   %123 = icmp eq i32 %121, %122
   %124 = zext i1 %123 to i8
   %toBool23.i.i = icmp ne i8 %124, 0
   br i1 %toBool23.i.i, label %bb24.i.i, label %bb25.i.i
 
 bb24.i.i:                                         ; preds = %bb22.i.i
-  %125 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %126 = load i32** %125, align 4
+  %125 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %126 = load i32*, i32** %125, align 4
   br label %_ZSt4findIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEiET_S7_S7_RKT0_.exit
 
 bb25.i.i:                                         ; preds = %bb22.i.i
-  %127 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
-  %128 = load i32** %127, align 4
-  %129 = getelementptr i32* %128, i64 1
-  %130 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %127 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
+  %128 = load i32*, i32** %127, align 4
+  %129 = getelementptr i32, i32* %128, i64 1
+  %130 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__first_addr.i.i, i32 0, i32 0
   store i32* %129, i32** %130, align 4
   br label %bb26.i.i
 
 bb26.i.i:                                         ; preds = %bb25.i.i, %bb13.i.i
-  %131 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__last_addr.i.i, i32 0, i32 0
-  %132 = load i32** %131, align 4
+  %131 = getelementptr %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >", %"struct.__gnu_cxx::__normal_iterator<int*,std::vector<int, std::allocator<int> > >"* %__last_addr.i.i, i32 0, i32 0
+  %132 = load i32*, i32** %131, align 4
   br label %_ZSt4findIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEiET_S7_S7_RKT0_.exit
 
 _ZSt4findIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEiET_S7_S7_RKT0_.exit: ; preds = %bb26.i.i, %bb24.i.i, %bb20.i.i, %bb16.i.i, %bb10.i.i, %bb7.i.i, %bb4.i.i, %bb1.i.i
diff --git a/test/Transforms/InstCombine/2009-02-21-LoadCST.ll b/test/Transforms/InstCombine/2009-02-21-LoadCST.ll
index cb8a77c23bac..90ec6d540e9c 100644
--- a/test/Transforms/InstCombine/2009-02-21-LoadCST.ll
+++ b/test/Transforms/InstCombine/2009-02-21-LoadCST.ll
@@ -7,6 +7,6 @@ target triple = "i386-pc-linux-gnu"
 @.str1 = internal constant [4 x i8] c"\B5%8\00"
 
 define i32 @test() {
-  %rhsv = load i32* bitcast ([4 x i8]* @.str1 to i32*), align 1
+  %rhsv = load i32, i32* bitcast ([4 x i8]* @.str1 to i32*), align 1
   ret i32 %rhsv
 }
diff --git a/test/Transforms/InstCombine/2009-02-25-CrashZeroSizeArray.ll b/test/Transforms/InstCombine/2009-02-25-CrashZeroSizeArray.ll
index a8349f042e42..ef1734ba7d17 100644
--- a/test/Transforms/InstCombine/2009-02-25-CrashZeroSizeArray.ll
+++ b/test/Transforms/InstCombine/2009-02-25-CrashZeroSizeArray.ll
@@ -9,18 +9,18 @@ entry:
 	%tmp6 = mul i32 %max289, 4		; <i32> [#uses=1]
 	%tmp7 = alloca i8, i32 0		; <i8*> [#uses=1]
 	%tmp8 = bitcast i8* %tmp7 to [0 x [0 x i32]]*		; <[0 x [0 x i32]]*> [#uses=1]
-	%tmp11 = load i32* null, align 1		; <i32> [#uses=1]
+	%tmp11 = load i32, i32* null, align 1		; <i32> [#uses=1]
 	%tmp12 = icmp eq i32 %tmp11, 3		; <i1> [#uses=1]
 	%tmp13 = zext i1 %tmp12 to i8		; <i8> [#uses=1]
 	%tmp14 = ashr i32 %tmp6, 2		; <i32> [#uses=1]
 	%tmp15 = bitcast [0 x [0 x i32]]* %tmp8 to i8*		; <i8*> [#uses=1]
 	%tmp16 = mul i32 %tmp14, 4		; <i32> [#uses=1]
 	%tmp17 = mul i32 1, %tmp16		; <i32> [#uses=1]
-	%tmp18 = getelementptr i8* %tmp15, i32 %tmp17		; <i8*> [#uses=1]
+	%tmp18 = getelementptr i8, i8* %tmp15, i32 %tmp17		; <i8*> [#uses=1]
 	%tmp19 = bitcast i8* %tmp18 to [0 x i32]*		; <[0 x i32]*> [#uses=1]
 	%tmp20 = bitcast [0 x i32]* %tmp19 to i32*		; <i32*> [#uses=1]
-	%tmp21 = getelementptr i32* %tmp20, i32 0		; <i32*> [#uses=1]
-	%tmp22 = load i32* %tmp21, align 1		; <i32> [#uses=1]
+	%tmp21 = getelementptr i32, i32* %tmp20, i32 0		; <i32*> [#uses=1]
+	%tmp22 = load i32, i32* %tmp21, align 1		; <i32> [#uses=1]
 	%tmp23 = icmp eq i32 %tmp22, 4		; <i1> [#uses=1]
 	%tmp24 = zext i1 %tmp23 to i8		; <i8> [#uses=1]
 	%toBool709 = icmp ne i8 %tmp13, 0		; <i1> [#uses=1]
diff --git a/test/Transforms/InstCombine/2009-03-18-vector-ashr-crash.ll b/test/Transforms/InstCombine/2009-03-18-vector-ashr-crash.ll
index c617ca4fcad3..3847abd30c80 100644
--- a/test/Transforms/InstCombine/2009-03-18-vector-ashr-crash.ll
+++ b/test/Transforms/InstCombine/2009-03-18-vector-ashr-crash.ll
@@ -3,9 +3,9 @@
 
 define void @0(<4 x i16>*, <4 x i16>*) {
 	%3 = alloca <4 x i16>*		; <<4 x i16>**> [#uses=1]
-	%4 = load <4 x i16>* null, align 1		; <<4 x i16>> [#uses=1]
+	%4 = load <4 x i16>, <4 x i16>* null, align 1		; <<4 x i16>> [#uses=1]
 	%5 = ashr <4 x i16> %4, <i16 5, i16 5, i16 5, i16 5>		; <<4 x i16>> [#uses=1]
-	%6 = load <4 x i16>** %3		; <<4 x i16>*> [#uses=1]
+	%6 = load <4 x i16>*, <4 x i16>** %3		; <<4 x i16>*> [#uses=1]
 	store <4 x i16> %5, <4 x i16>* %6, align 1
 	ret void
 }
diff --git a/test/Transforms/InstCombine/2009-05-23-FCmpToICmp.ll b/test/Transforms/InstCombine/2009-05-23-FCmpToICmp.ll
index dd14c6beec4c..ced317c4d43f 100644
--- a/test/Transforms/InstCombine/2009-05-23-FCmpToICmp.ll
+++ b/test/Transforms/InstCombine/2009-05-23-FCmpToICmp.ll
@@ -2,7 +2,7 @@
 ; rdar://6903175
 
 define i1 @f0(i32 *%a) nounwind {
-       %b = load i32* %a, align 4
+       %b = load i32, i32* %a, align 4
        %c = uitofp i32 %b to double
        %d = fcmp ogt double %c, 0x41EFFFFFFFE00000
        ret i1 %d
diff --git a/test/Transforms/InstCombine/2009-12-17-CmpSelectNull.ll b/test/Transforms/InstCombine/2009-12-17-CmpSelectNull.ll
index fb7497b395d4..c438ca5fd172 100644
--- a/test/Transforms/InstCombine/2009-12-17-CmpSelectNull.ll
+++ b/test/Transforms/InstCombine/2009-12-17-CmpSelectNull.ll
@@ -6,9 +6,9 @@
 define i8* @demangle_qualified(i32 %isfuncname) nounwind {
 entry:
   %tobool272 = icmp ne i32 %isfuncname, 0
-  %cond276 = select i1 %tobool272, i8* getelementptr inbounds ([2 x i8]* @.str254, i32 0, i32 0), i8* getelementptr inbounds ([3 x i8]* @.str557, i32 0, i32 0) ; <i8*> [#uses=4]
+  %cond276 = select i1 %tobool272, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str254, i32 0, i32 0), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str557, i32 0, i32 0) ; <i8*> [#uses=4]
   %cmp.i504 = icmp eq i8* %cond276, null
-  %rval = getelementptr i8* %cond276, i1 %cmp.i504
+  %rval = getelementptr i8, i8* %cond276, i1 %cmp.i504
   ret i8* %rval
 }
 
diff --git a/test/Transforms/InstCombine/2010-03-03-ExtElim.ll b/test/Transforms/InstCombine/2010-03-03-ExtElim.ll
index e0def997d974..ad0fe5a21783 100644
--- a/test/Transforms/InstCombine/2010-03-03-ExtElim.ll
+++ b/test/Transforms/InstCombine/2010-03-03-ExtElim.ll
@@ -4,11 +4,11 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 target triple = "i386-unknown-linux-gnu"
 
 @g_92 = common global [2 x i32*] zeroinitializer, align 4 ; <[2 x i32*]*> [#uses=1]
-@g_177 = constant i32** bitcast (i8* getelementptr (i8* bitcast ([2 x i32*]* @g_92 to i8*), i64 4) to i32**), align 4 ; <i32***> [#uses=1]
+@g_177 = constant i32** bitcast (i8* getelementptr (i8, i8* bitcast ([2 x i32*]* @g_92 to i8*), i64 4) to i32**), align 4 ; <i32***> [#uses=1]
 
 define i1 @PR6486() nounwind {
 ; CHECK-LABEL: @PR6486(
-  %tmp = load i32*** @g_177                       ; <i32**> [#uses=1]
+  %tmp = load i32**, i32*** @g_177                       ; <i32**> [#uses=1]
   %cmp = icmp ne i32** null, %tmp                 ; <i1> [#uses=1]
   %conv = zext i1 %cmp to i32                     ; <i32> [#uses=1]
   %cmp1 = icmp sle i32 0, %conv                   ; <i1> [#uses=1]
@@ -21,12 +21,12 @@ define i1 @PR6486() nounwind {
 
 define i1 @PR16462_1() nounwind {
 ; CHECK-LABEL: @PR16462_1(
-  ret i1 icmp sgt (i32 sext (i16 trunc (i32 select (i1 icmp eq (i32* getelementptr inbounds ([1 x i32]* @a, i32 0, i32 0), i32* @d), i32 0, i32 1) to i16) to i32), i32 65535)
+  ret i1 icmp sgt (i32 sext (i16 trunc (i32 select (i1 icmp eq (i32* getelementptr inbounds ([1 x i32], [1 x i32]* @a, i32 0, i32 0), i32* @d), i32 0, i32 1) to i16) to i32), i32 65535)
 ; CHECK: ret i1 false
 }
 
 define i1 @PR16462_2() nounwind {
 ; CHECK-LABEL: @PR16462_2(
-  ret i1 icmp sgt (i32 sext (i16 trunc (i32 select (i1 icmp eq (i32* getelementptr inbounds ([1 x i32]* @a, i32 0, i32 0), i32* @d), i32 0, i32 1) to i16) to i32), i32 42)
+  ret i1 icmp sgt (i32 sext (i16 trunc (i32 select (i1 icmp eq (i32* getelementptr inbounds ([1 x i32], [1 x i32]* @a, i32 0, i32 0), i32* @d), i32 0, i32 1) to i16) to i32), i32 42)
 ; CHECK: ret i1 false
 }
diff --git a/test/Transforms/InstCombine/2010-05-30-memcpy-Struct.ll b/test/Transforms/InstCombine/2010-05-30-memcpy-Struct.ll
index 09a96749f260..51610698c244 100644
--- a/test/Transforms/InstCombine/2010-05-30-memcpy-Struct.ll
+++ b/test/Transforms/InstCombine/2010-05-30-memcpy-Struct.ll
@@ -10,7 +10,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define void @CopyEventArg(%union.anon* %ev) nounwind {
 entry:
-  %call = call i32 (i8*, i8*, ...)* @sprintf(i8* undef, i8* getelementptr inbounds ([3 x i8]* @.str, i64 0, i64 0), %union.anon* %ev) nounwind
+  %call = call i32 (i8*, i8*, ...) @sprintf(i8* undef, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i64 0, i64 0), %union.anon* %ev) nounwind
 ; CHECK: bitcast %union.anon* %ev to i8*
 ; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64
   ret void
diff --git a/test/Transforms/InstCombine/2010-11-21-SizeZeroTypeGEP.ll b/test/Transforms/InstCombine/2010-11-21-SizeZeroTypeGEP.ll
index 80983ef27098..798c726e566f 100644
--- a/test/Transforms/InstCombine/2010-11-21-SizeZeroTypeGEP.ll
+++ b/test/Transforms/InstCombine/2010-11-21-SizeZeroTypeGEP.ll
@@ -5,13 +5,13 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 define {}* @foo({}* %x, i32 %n) {
 ; CHECK-LABEL: @foo(
 ; CHECK-NOT: getelementptr
-  %p = getelementptr {}* %x, i32 %n
+  %p = getelementptr {}, {}* %x, i32 %n
   ret {}* %p
 }
 
 define i8* @bar(i64 %n, {{}, [0 x {[0 x i8]}]}* %p) {
 ; CHECK-LABEL: @bar(
-  %g = getelementptr {{}, [0 x {[0 x i8]}]}* %p, i64 %n, i32 1, i64 %n, i32 0, i64 %n
+  %g = getelementptr {{}, [0 x {[0 x i8]}]}, {{}, [0 x {[0 x i8]}]}* %p, i64 %n, i32 1, i64 %n, i32 0, i64 %n
 ; CHECK: %p, i64 0, i32 1, i64 0, i32 0, i64 %n
   ret i8* %g
 }
diff --git a/test/Transforms/InstCombine/2011-05-02-VectorBoolean.ll b/test/Transforms/InstCombine/2011-05-02-VectorBoolean.ll
index 02b64e3bb8d3..116c9713d893 100644
--- a/test/Transforms/InstCombine/2011-05-02-VectorBoolean.ll
+++ b/test/Transforms/InstCombine/2011-05-02-VectorBoolean.ll
@@ -6,9 +6,9 @@ entry:
   %a.addr = alloca <2 x i16>, align 4
   %.compoundliteral = alloca <2 x i16>, align 4
   store <2 x i16> %a, <2 x i16>* %a.addr, align 4
-  %tmp = load <2 x i16>* %a.addr, align 4
+  %tmp = load <2 x i16>, <2 x i16>* %a.addr, align 4
   store <2 x i16> zeroinitializer, <2 x i16>* %.compoundliteral
-  %tmp1 = load <2 x i16>* %.compoundliteral
+  %tmp1 = load <2 x i16>, <2 x i16>* %.compoundliteral
   %cmp = icmp uge <2 x i16> %tmp, %tmp1
   %sext = sext <2 x i1> %cmp to <2 x i16>
   ret <2 x i16> %sext
diff --git a/test/Transforms/InstCombine/2011-05-13-InBoundsGEP.ll b/test/Transforms/InstCombine/2011-05-13-InBoundsGEP.ll
index fba7239e2d1e..69568705cfd5 100644
--- a/test/Transforms/InstCombine/2011-05-13-InBoundsGEP.ll
+++ b/test/Transforms/InstCombine/2011-05-13-InBoundsGEP.ll
@@ -9,9 +9,9 @@ entry:
     %tmp2 = add i32 %argc, 1879048192
     %p = alloca i8
 ; CHECK: getelementptr
-    %p1 = getelementptr i8* %p, i32 %tmp1
+    %p1 = getelementptr i8, i8* %p, i32 %tmp1
 ; CHECK: getelementptr
-    %p2 = getelementptr i8* %p, i32 %tmp2
+    %p2 = getelementptr i8, i8* %p, i32 %tmp2
     %cmp = icmp ult i8* %p1, %p2
     br i1 %cmp, label %bbtrue, label %bbfalse
 bbtrue:          ; preds = %entry
diff --git a/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll b/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll
index b096d1f952f9..639b64aacba0 100644
--- a/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll
+++ b/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll
@@ -7,14 +7,14 @@ entry:
   %on_off.addr = alloca i32, align 4
   %a = alloca i32, align 4
   store i32 %on_off, i32* %on_off.addr, align 4
-  %tmp = load i32* %on_off.addr, align 4
+  %tmp = load i32, i32* %on_off.addr, align 4
   %sub = sub i32 1, %tmp
 ; CHECK-NOT: mul i32
   %mul = mul i32 %sub, -2
 ; CHECK: shl
 ; CHECK-NEXT: add
   store i32 %mul, i32* %a, align 4
-  %tmp1 = load i32* %a, align 4
+  %tmp1 = load i32, i32* %a, align 4
   %conv = trunc i32 %tmp1 to i16
   ret i16 %conv
 }
@@ -26,15 +26,15 @@ entry:
   %a = alloca i32, align 4
   store i32 %on_off, i32* %on_off.addr, align 4
   store i32 %q, i32* %q.addr, align 4
-  %tmp = load i32* %q.addr, align 4
-  %tmp1 = load i32* %on_off.addr, align 4
+  %tmp = load i32, i32* %q.addr, align 4
+  %tmp1 = load i32, i32* %on_off.addr, align 4
   %sub = sub i32 %tmp, %tmp1
 ; CHECK-NOT: mul i32
   %mul = mul i32 %sub, -4
 ; CHECK: sub i32
 ; CHECK-NEXT: shl
   store i32 %mul, i32* %a, align 4
-  %tmp2 = load i32* %a, align 4
+  %tmp2 = load i32, i32* %a, align 4
   %conv = trunc i32 %tmp2 to i16
   ret i16 %conv
 }
@@ -44,14 +44,14 @@ entry:
   %on_off.addr = alloca i32, align 4
   %a = alloca i32, align 4
   store i32 %on_off, i32* %on_off.addr, align 4
-  %tmp = load i32* %on_off.addr, align 4
+  %tmp = load i32, i32* %on_off.addr, align 4
   %sub = sub i32 7, %tmp
 ; CHECK-NOT: mul i32
   %mul = mul i32 %sub, -4
 ; CHECK: shl
 ; CHECK-NEXT: add
   store i32 %mul, i32* %a, align 4
-  %tmp1 = load i32* %a, align 4
+  %tmp1 = load i32, i32* %a, align 4
   %conv = trunc i32 %tmp1 to i16
   ret i16 %conv
 }
diff --git a/test/Transforms/InstCombine/2011-06-13-nsw-alloca.ll b/test/Transforms/InstCombine/2011-06-13-nsw-alloca.ll
index c8f0351858ca..15c11db37f59 100644
--- a/test/Transforms/InstCombine/2011-06-13-nsw-alloca.ll
+++ b/test/Transforms/InstCombine/2011-06-13-nsw-alloca.ll
@@ -9,12 +9,12 @@ define void @fu1(i32 %parm) nounwind ssp {
   %ptr = alloca double*, align 4
   store i32 %parm, i32* %1, align 4
   store double* null, double** %ptr, align 4
-  %2 = load i32* %1, align 4
+  %2 = load i32, i32* %1, align 4
   %3 = icmp ne i32 %2, 0
   br i1 %3, label %4, label %10
 
 ; <label>:4                                       ; preds = %0
-  %5 = load i32* %1, align 4
+  %5 = load i32, i32* %1, align 4
   %6 = shl nsw i32 %5, 3
 ; With "nsw", the alloca and its bitcast can be fused:
   %7 = add nsw i32 %6, 2048
@@ -25,7 +25,7 @@ define void @fu1(i32 %parm) nounwind ssp {
   store double* %9, double** %ptr, align 4
   br label %10
 ; <label>:10                                      ; preds = %4, %0
-  %11 = load double** %ptr, align 4
+  %11 = load double*, double** %ptr, align 4
   call void @bar(double* %11)
 ; CHECK: ret
   ret void
@@ -39,12 +39,12 @@ define void @fu2(i32 %parm) nounwind ssp {
   %ptr = alloca double*, align 4
   store i32 %parm, i32* %1, align 4
   store double* null, double** %ptr, align 4
-  %2 = load i32* %1, align 4
+  %2 = load i32, i32* %1, align 4
   %3 = icmp ne i32 %2, 0
   br i1 %3, label %4, label %10
 
 ; <label>:4                                       ; preds = %0
-  %5 = load i32* %1, align 4
+  %5 = load i32, i32* %1, align 4
   %6 = mul nsw i32 %5, 8
 ; Without "nsw", the alloca and its bitcast cannot be fused:
   %7 = add  i32 %6, 2048
@@ -57,7 +57,7 @@ define void @fu2(i32 %parm) nounwind ssp {
   br label %10
 
 ; <label>:10                                      ; preds = %4, %0
-  %11 = load double** %ptr, align 4
+  %11 = load double*, double** %ptr, align 4
   call void @bar(double* %11)
   ret void
 }
diff --git a/test/Transforms/InstCombine/2011-09-03-Trampoline.ll b/test/Transforms/InstCombine/2011-09-03-Trampoline.ll
index 5456e0357393..1833558cbceb 100644
--- a/test/Transforms/InstCombine/2011-09-03-Trampoline.ll
+++ b/test/Transforms/InstCombine/2011-09-03-Trampoline.ll
@@ -7,7 +7,7 @@ declare i32 @f(i8 * nest, i32)
 ; Most common case
 define i32 @test0(i32 %n) {
   %alloca = alloca [10 x i8], align 16
-  %gep = getelementptr [10 x i8]* %alloca, i32 0, i32 0
+  %gep = getelementptr [10 x i8], [10 x i8]* %alloca, i32 0, i32 0
   call void @llvm.init.trampoline(i8* %gep, i8* bitcast (i32 (i8*, i32)* @f to i8*),
                                   i8* null)
   %tramp = call i8* @llvm.adjust.trampoline(i8* %gep)
@@ -62,7 +62,7 @@ define i32 @test3(i32 %n, i8* %trampmem) {
 
 define i32 @test4(i32 %n) {
   %alloca = alloca [10 x i8], align 16
-  %gep = getelementptr [10 x i8]* %alloca, i32 0, i32 0
+  %gep = getelementptr [10 x i8], [10 x i8]* %alloca, i32 0, i32 0
   call void @llvm.init.trampoline(i8* %gep, i8* bitcast (i32 (i8*, i32)* @f to i8*),
                                   i8* null)
 
diff --git a/test/Transforms/InstCombine/2011-10-07-AlignPromotion.ll b/test/Transforms/InstCombine/2011-10-07-AlignPromotion.ll
index 22061b272a85..122669ec04a7 100644
--- a/test/Transforms/InstCombine/2011-10-07-AlignPromotion.ll
+++ b/test/Transforms/InstCombine/2011-10-07-AlignPromotion.ll
@@ -10,7 +10,7 @@ define void @t(%struct.CGPoint* %a) nounwind {
   %Point = alloca %struct.CGPoint, align 4
   %1 = bitcast %struct.CGPoint* %a to i64*
   %2 = bitcast %struct.CGPoint* %Point to i64*
-  %3 = load i64* %1, align 4
+  %3 = load i64, i64* %1, align 4
   store i64 %3, i64* %2, align 4
   call void @foo(i64* %2) nounwind
   ret void
diff --git a/test/Transforms/InstCombine/2012-02-13-FCmp.ll b/test/Transforms/InstCombine/2012-02-13-FCmp.ll
index 39b05946515a..586f86de3c29 100644
--- a/test/Transforms/InstCombine/2012-02-13-FCmp.ll
+++ b/test/Transforms/InstCombine/2012-02-13-FCmp.ll
@@ -6,9 +6,9 @@
 declare i32 @printf(i8*, ...)
 define i64 @_Z8tempCastj(i32 %val) uwtable ssp {
 entry:
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([35 x i8]* @.str1, i64 0, i64 0), i32 %val)
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([35 x i8], [35 x i8]* @.str1, i64 0, i64 0), i32 %val)
   %conv = uitofp i32 %val to double
-  %call.i = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([35 x i8]* @.str, i64 0, i64 0), double %conv)
+  %call.i = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([35 x i8], [35 x i8]* @.str, i64 0, i64 0), double %conv)
   %cmp.i = fcmp oge double %conv, -1.000000e+00
   br i1 %cmp.i, label %land.rhs.i, label %if.end.critedge
 ; CHECK:  br i1 true, label %land.rhs.i, label %if.end.critedge
diff --git a/test/Transforms/InstCombine/2012-05-27-Negative-Shift-Crash.ll b/test/Transforms/InstCombine/2012-05-27-Negative-Shift-Crash.ll
index ba83fe9ec0ad..ba57baf23711 100644
--- a/test/Transforms/InstCombine/2012-05-27-Negative-Shift-Crash.ll
+++ b/test/Transforms/InstCombine/2012-05-27-Negative-Shift-Crash.ll
@@ -20,7 +20,7 @@ entry:
 
 define void @fn4() nounwind uwtable ssp {
 entry:
-  %0 = load i32* @d, align 4
+  %0 = load i32, i32* @d, align 4
   %cmp = icmp eq i32 %0, 0
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @c, align 4
@@ -34,12 +34,12 @@ entry:
   store i32 %and, i32* @e, align 4
   %sub = add nsw i32 %and, -1
   store i32 %sub, i32* @f, align 4
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %if.else, label %if.then
 
 if.then:                                          ; preds = %entry
-  %1 = load i32* @b, align 4
+  %1 = load i32, i32* @b, align 4
   %.lobit = lshr i32 %1, 31
   %2 = trunc i32 %.lobit to i8
   %.not = xor i8 %2, 1
diff --git a/test/Transforms/InstCombine/2012-05-28-select-hang.ll b/test/Transforms/InstCombine/2012-05-28-select-hang.ll
index db1dbd5b6e2f..c514dd1f5ec7 100644
--- a/test/Transforms/InstCombine/2012-05-28-select-hang.ll
+++ b/test/Transforms/InstCombine/2012-05-28-select-hang.ll
@@ -6,7 +6,7 @@
 
 define void @func() nounwind uwtable ssp {
 entry:
-  %0 = load i8* @c, align 1
+  %0 = load i8, i8* @c, align 1
   %conv = zext i8 %0 to i32
   %or = or i32 %conv, 1
   %conv1 = trunc i32 %or to i8
@@ -16,7 +16,7 @@ entry:
   %and = and i32 1, %neg
   %conv3 = trunc i32 %and to i8
   store i8 %conv3, i8* @b, align 1
-  %1 = load i8* @a, align 1
+  %1 = load i8, i8* @a, align 1
   %conv4 = zext i8 %1 to i32
   %conv5 = zext i8 %conv3 to i32
   %tobool = icmp ne i32 %conv4, 0
diff --git a/test/Transforms/InstCombine/2012-06-06-LoadOfPHIs.ll b/test/Transforms/InstCombine/2012-06-06-LoadOfPHIs.ll
index 22466a96b667..4af1ca842c59 100644
--- a/test/Transforms/InstCombine/2012-06-06-LoadOfPHIs.ll
+++ b/test/Transforms/InstCombine/2012-06-06-LoadOfPHIs.ll
@@ -34,16 +34,16 @@ bb11:                                             ; preds = %bb8
 
 bb12:                                             ; preds = %bb11, %bb10, %bb7, %bb6
   %max.0 = phi double* [ %tmp, %bb6 ], [ %tmp2, %bb7 ], [ %tmp1, %bb10 ], [ %tmp2, %bb11 ]
-; CHECK: %tmp13 = load double* %tmp, align 8
-; CHECK: %tmp14 = load double* %tmp1, align 8
+; CHECK: %tmp13 = load double, double* %tmp, align 8
+; CHECK: %tmp14 = load double, double* %tmp1, align 8
 ; CHECK: %tmp15 = fcmp olt double %tmp13, %tmp14
-  %tmp13 = load double* %tmp, align 8
-  %tmp14 = load double* %tmp1, align 8
+  %tmp13 = load double, double* %tmp, align 8
+  %tmp14 = load double, double* %tmp1, align 8
   %tmp15 = fcmp olt double %tmp13, %tmp14
   br i1 %tmp15, label %bb16, label %bb21
 
 bb16:                                             ; preds = %bb12
-  %tmp17 = load double* %tmp2, align 8
+  %tmp17 = load double, double* %tmp2, align 8
   %tmp18 = fcmp olt double %tmp13, %tmp17
   br i1 %tmp18, label %bb19, label %bb20
 
@@ -54,7 +54,7 @@ bb20:                                             ; preds = %bb16
   br label %bb26
 
 bb21:                                             ; preds = %bb12
-  %tmp22 = load double* %tmp2, align 8
+  %tmp22 = load double, double* %tmp2, align 8
   %tmp23 = fcmp olt double %tmp14, %tmp22
   br i1 %tmp23, label %bb24, label %bb25
 
@@ -66,16 +66,16 @@ bb25:                                             ; preds = %bb21
 
 bb26:                                             ; preds = %bb25, %bb24, %bb20, %bb19
   %min.0 = phi double* [ %tmp, %bb19 ], [ %tmp2, %bb20 ], [ %tmp1, %bb24 ], [ %tmp2, %bb25 ]
-; CHECK: %tmp27 = load double* %min.0, align 8
-; CHECK: %tmp28 = load double* %max.0
+; CHECK: %tmp27 = load double, double* %min.0, align 8
+; CHECK: %tmp28 = load double, double* %max.0
 ; CHECK: %tmp29 = fadd double %tmp27, %tmp28
-  %tmp27 = load double* %min.0, align 8
-  %tmp28 = load double* %max.0
+  %tmp27 = load double, double* %min.0, align 8
+  %tmp28 = load double, double* %max.0
   %tmp29 = fadd double %tmp27, %tmp28
   %tmp30 = fdiv double %tmp29, 2.000000e+00
   store double %tmp30, double* %outL
-  %tmp31 = load double* %min.0
-  %tmp32 = load double* %max.0
+  %tmp31 = load double, double* %min.0
+  %tmp32 = load double, double* %max.0
   %tmp33 = fcmp oeq double %tmp31, %tmp32
   br i1 %tmp33, label %bb34, label %bb35
 
@@ -107,11 +107,11 @@ bb45:                                             ; preds = %bb41, %bb38
   br i1 %tmp46, label %bb47, label %bb55
 
 bb47:                                             ; preds = %bb45
-  %tmp48 = load double* %tmp1, align 8
-  %tmp49 = load double* %tmp2, align 8
+  %tmp48 = load double, double* %tmp1, align 8
+  %tmp49 = load double, double* %tmp2, align 8
   %tmp50 = fsub double %tmp48, %tmp49
-  %tmp51 = load double* %max.0
-  %tmp52 = load double* %min.0
+  %tmp51 = load double, double* %max.0
+  %tmp52 = load double, double* %min.0
   %tmp53 = fsub double %tmp51, %tmp52
   %tmp54 = fdiv double %tmp50, %tmp53
   store double %tmp54, double* %outH
@@ -122,11 +122,11 @@ bb55:                                             ; preds = %bb45
   br i1 %tmp56, label %bb57, label %bb66
 
 bb57:                                             ; preds = %bb55
-  %tmp58 = load double* %tmp2, align 8
-  %tmp59 = load double* %tmp, align 8
+  %tmp58 = load double, double* %tmp2, align 8
+  %tmp59 = load double, double* %tmp, align 8
   %tmp60 = fsub double %tmp58, %tmp59
-  %tmp61 = load double* %max.0
-  %tmp62 = load double* %min.0
+  %tmp61 = load double, double* %max.0
+  %tmp62 = load double, double* %min.0
   %tmp63 = fsub double %tmp61, %tmp62
   %tmp64 = fdiv double %tmp60, %tmp63
   %tmp65 = fadd double 2.000000e+00, %tmp64
@@ -134,11 +134,11 @@ bb57:                                             ; preds = %bb55
   br label %bb75
 
 bb66:                                             ; preds = %bb55
-  %tmp67 = load double* %tmp, align 8
-  %tmp68 = load double* %tmp1, align 8
+  %tmp67 = load double, double* %tmp, align 8
+  %tmp68 = load double, double* %tmp1, align 8
   %tmp69 = fsub double %tmp67, %tmp68
-  %tmp70 = load double* %max.0
-  %tmp71 = load double* %min.0
+  %tmp70 = load double, double* %max.0
+  %tmp71 = load double, double* %min.0
   %tmp72 = fsub double %tmp70, %tmp71
   %tmp73 = fdiv double %tmp69, %tmp72
   %tmp74 = fadd double 4.000000e+00, %tmp73
@@ -146,7 +146,7 @@ bb66:                                             ; preds = %bb55
   br label %bb75
 
 bb75:                                             ; preds = %bb66, %bb57, %bb47
-  %tmp76 = load double* %outH
+  %tmp76 = load double, double* %outH
   %tmp77 = fdiv double %tmp76, 6.000000e+00
   store double %tmp77, double* %outH
   %tmp78 = fcmp olt double %tmp77, 0.000000e+00
diff --git a/test/Transforms/InstCombine/2012-07-25-LoadPart.ll b/test/Transforms/InstCombine/2012-07-25-LoadPart.ll
index 18aab7f27efd..14fcf52fe9a7 100644
--- a/test/Transforms/InstCombine/2012-07-25-LoadPart.ll
+++ b/test/Transforms/InstCombine/2012-07-25-LoadPart.ll
@@ -5,7 +5,7 @@
 @test = constant [4 x i32] [i32 1, i32 2, i32 3, i32 4]
 
 define i64 @foo() {
-  %ret = load i64* bitcast (i8* getelementptr (i8* bitcast ([4 x i32]* @test to i8*), i64 2) to i64*), align 1
+  %ret = load i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast ([4 x i32]* @test to i8*), i64 2) to i64*), align 1
   ret i64 %ret
   ; 0x00030000_00020000 in [01 00/00 00 02 00 00 00 03 00/00 00 04 00 00 00]
   ; LE: ret i64 844424930263040
diff --git a/test/Transforms/InstCombine/2012-07-30-addrsp-bitcast.ll b/test/Transforms/InstCombine/2012-07-30-addrsp-bitcast.ll
index ac9c555020d0..666538067884 100644
--- a/test/Transforms/InstCombine/2012-07-30-addrsp-bitcast.ll
+++ b/test/Transforms/InstCombine/2012-07-30-addrsp-bitcast.ll
@@ -5,6 +5,6 @@
 declare void @foo(i32*)
 
 define void @test() nounwind {
-  call void @foo(i32* getelementptr (i32* addrspacecast ([16 x i32] addrspace(3)* @base to i32*), i64 2147483647)) nounwind
+  call void @foo(i32* getelementptr (i32, i32* addrspacecast ([16 x i32] addrspace(3)* @base to i32*), i64 2147483647)) nounwind
   ret void
 }
diff --git a/test/Transforms/InstCombine/2012-09-17-ZeroSizedAlloca.ll b/test/Transforms/InstCombine/2012-09-17-ZeroSizedAlloca.ll
index 7015725feb16..1c5a9813e6b3 100644
--- a/test/Transforms/InstCombine/2012-09-17-ZeroSizedAlloca.ll
+++ b/test/Transforms/InstCombine/2012-09-17-ZeroSizedAlloca.ll
@@ -16,8 +16,8 @@ target triple = "x86_64-apple-macosx10.8.0"
 define void @f() {
   %1 = alloca [0 x i8], align 1
   %2 = alloca [0 x i8], align 1024
-  %3 = getelementptr inbounds [0 x i8]* %1, i64 0, i64 0
-  %4 = getelementptr inbounds [0 x i8]* %2, i64 0, i64 0
+  %3 = getelementptr inbounds [0 x i8], [0 x i8]* %1, i64 0, i64 0
+  %4 = getelementptr inbounds [0 x i8], [0 x i8]* %2, i64 0, i64 0
   store i8* %3, i8** @x, align 8
   store i8* %4, i8** @y, align 8
   ret void
diff --git a/test/Transforms/InstCombine/2012-09-24-MemcpyFromGlobalCrash.ll b/test/Transforms/InstCombine/2012-09-24-MemcpyFromGlobalCrash.ll
deleted file mode 100644
index 35b62850c626..000000000000
--- a/test/Transforms/InstCombine/2012-09-24-MemcpyFromGlobalCrash.ll
+++ /dev/null
@@ -1,19 +0,0 @@
-; RUN: opt < %s -instcombine -S | FileCheck %s
-
-; Check we don't crash due to lack of target data.
-
-@G = constant [100 x i8] zeroinitializer
-
-declare void @bar(i8*)
-declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
-
-define void @test() {
-; CHECK-LABEL: @test(
-; CHECK: llvm.memcpy
-; CHECK: ret void
-  %A = alloca [100 x i8]
-  %a = getelementptr inbounds [100 x i8]* %A, i64 0, i64 0
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* getelementptr inbounds ([100 x i8]* @G, i64 0, i32 0), i64 100, i32 4, i1 false)
-  call void @bar(i8* %a) readonly
-  ret void
-}
diff --git a/test/Transforms/InstCombine/2012-10-25-vector-of-pointers.ll b/test/Transforms/InstCombine/2012-10-25-vector-of-pointers.ll
index 20ea28268742..23210650e2f3 100644
--- a/test/Transforms/InstCombine/2012-10-25-vector-of-pointers.ll
+++ b/test/Transforms/InstCombine/2012-10-25-vector-of-pointers.ll
@@ -9,7 +9,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 define void @widget(%struct.hoge* nocapture %arg) nounwind uwtable ssp {
 bb:
-  %tmp = getelementptr inbounds %struct.hoge* %arg, i64 0, i32 0
+  %tmp = getelementptr inbounds %struct.hoge, %struct.hoge* %arg, i64 0, i32 0
   br i1 undef, label %bb1, label %bb17
 
 bb1:                                              ; preds = %bb
@@ -20,7 +20,7 @@ bb2:                                              ; preds = %bb1
 
 bb3:                                              ; preds = %bb1
   %tmp4 = bitcast double** %tmp to <2 x double*>*
-  %tmp5 = load <2 x double*>* %tmp4, align 8
+  %tmp5 = load <2 x double*>, <2 x double*>* %tmp4, align 8
   %tmp6 = ptrtoint <2 x double*> %tmp5 to <2 x i64>
   %tmp7 = sub <2 x i64> zeroinitializer, %tmp6
   %tmp8 = ashr exact <2 x i64> %tmp7, <i64 3, i64 3>
diff --git a/test/Transforms/InstCombine/2012-12-14-simp-vgep.ll b/test/Transforms/InstCombine/2012-12-14-simp-vgep.ll
index fc29b095e5ce..46702f80c0cc 100644
--- a/test/Transforms/InstCombine/2012-12-14-simp-vgep.ll
+++ b/test/Transforms/InstCombine/2012-12-14-simp-vgep.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 
 define <4 x i32> @foo(<4 x i32*>* %in) {
-  %t17 = load <4 x i32*>* %in, align 8
+  %t17 = load <4 x i32*>, <4 x i32*>* %in, align 8
   %t18 = icmp eq <4 x i32*> %t17, zeroinitializer
   %t19 = zext <4 x i1> %t18 to <4 x i32>
   ret <4 x i32> %t19
diff --git a/test/Transforms/InstCombine/2013-03-05-Combine-BitcastTy-Into-Alloca.ll b/test/Transforms/InstCombine/2013-03-05-Combine-BitcastTy-Into-Alloca.ll
index 789e3172e7c4..9425c29a427d 100644
--- a/test/Transforms/InstCombine/2013-03-05-Combine-BitcastTy-Into-Alloca.ll
+++ b/test/Transforms/InstCombine/2013-03-05-Combine-BitcastTy-Into-Alloca.ll
@@ -16,8 +16,8 @@ define { i64, i64 } @function(i32 %x, i32 %y, i32 %z) nounwind {
 ; CHECK-NOT: bitcast i96* %retval to %struct._my_struct*
 entry:
   %retval = alloca %struct._my_struct, align 8
-  %k.sroa.0.0.copyload = load i96* bitcast (%struct._my_struct* @initval to i96*), align 1
-  %k.sroa.1.12.copyload = load i32* bitcast ([4 x i8]* getelementptr inbounds (%struct._my_struct* @initval, i64 0, i32 1) to i32*), align 1
+  %k.sroa.0.0.copyload = load i96, i96* bitcast (%struct._my_struct* @initval to i96*), align 1
+  %k.sroa.1.12.copyload = load i32, i32* bitcast ([4 x i8]* getelementptr inbounds (%struct._my_struct, %struct._my_struct* @initval, i64 0, i32 1) to i32*), align 1
   %0 = zext i32 %x to i96
   %bf.value = shl nuw nsw i96 %0, 6
   %bf.clear = and i96 %k.sroa.0.0.copyload, -288230376151711744
@@ -32,14 +32,14 @@ entry:
   %bf.set10 = or i96 %bf.set5, %bf.clear
   %retval.0.cast7 = bitcast %struct._my_struct* %retval to i96*
   store i96 %bf.set10, i96* %retval.0.cast7, align 8
-  %retval.12.idx8 = getelementptr inbounds %struct._my_struct* %retval, i64 0, i32 1
+  %retval.12.idx8 = getelementptr inbounds %struct._my_struct, %struct._my_struct* %retval, i64 0, i32 1
   %retval.12.cast9 = bitcast [4 x i8]* %retval.12.idx8 to i32*
   store i32 %k.sroa.1.12.copyload, i32* %retval.12.cast9, align 4
   %trunc = trunc i96 %bf.set10 to i64
   %.fca.0.insert = insertvalue { i64, i64 } undef, i64 %trunc, 0
-  %retval.8.idx12 = getelementptr inbounds %struct._my_struct* %retval, i64 0, i32 0, i64 8
+  %retval.8.idx12 = getelementptr inbounds %struct._my_struct, %struct._my_struct* %retval, i64 0, i32 0, i64 8
   %retval.8.cast13 = bitcast i8* %retval.8.idx12 to i64*
-  %retval.8.load14 = load i64* %retval.8.cast13, align 8
+  %retval.8.load14 = load i64, i64* %retval.8.cast13, align 8
   %.fca.1.insert = insertvalue { i64, i64 } %.fca.0.insert, i64 %retval.8.load14, 1
   ret { i64, i64 } %.fca.1.insert
 }
diff --git a/test/Transforms/InstCombine/CPP_min_max.ll b/test/Transforms/InstCombine/CPP_min_max.ll
index b3d081b613a6..04bf0ceefea9 100644
--- a/test/Transforms/InstCombine/CPP_min_max.ll
+++ b/test/Transforms/InstCombine/CPP_min_max.ll
@@ -10,11 +10,11 @@
 
 define void @_Z5test1RiS_(i32* %x, i32* %y) {
 entry:
-        %tmp.1.i = load i32* %y         ; <i32> [#uses=1]
-        %tmp.3.i = load i32* %x         ; <i32> [#uses=1]
+        %tmp.1.i = load i32, i32* %y         ; <i32> [#uses=1]
+        %tmp.3.i = load i32, i32* %x         ; <i32> [#uses=1]
         %tmp.4.i = icmp slt i32 %tmp.1.i, %tmp.3.i              ; <i1> [#uses=1]
         %retval.i = select i1 %tmp.4.i, i32* %y, i32* %x                ; <i32*> [#uses=1]
-        %tmp.4 = load i32* %retval.i            ; <i32> [#uses=1]
+        %tmp.4 = load i32, i32* %retval.i            ; <i32> [#uses=1]
         store i32 %tmp.4, i32* %x
         ret void
 }
@@ -22,12 +22,12 @@ entry:
 define void @_Z5test2RiS_(i32* %x, i32* %y) {
 entry:
         %tmp.0 = alloca i32             ; <i32*> [#uses=2]
-        %tmp.2 = load i32* %x           ; <i32> [#uses=2]
+        %tmp.2 = load i32, i32* %x           ; <i32> [#uses=2]
         store i32 %tmp.2, i32* %tmp.0
-        %tmp.3.i = load i32* %y         ; <i32> [#uses=1]
+        %tmp.3.i = load i32, i32* %y         ; <i32> [#uses=1]
         %tmp.4.i = icmp slt i32 %tmp.2, %tmp.3.i                ; <i1> [#uses=1]
         %retval.i = select i1 %tmp.4.i, i32* %y, i32* %tmp.0            ; <i32*> [#uses=1]
-        %tmp.6 = load i32* %retval.i            ; <i32> [#uses=1]
+        %tmp.6 = load i32, i32* %retval.i            ; <i32> [#uses=1]
         store i32 %tmp.6, i32* %y
         ret void
 }
diff --git a/test/Transforms/InstCombine/LandingPadClauses.ll b/test/Transforms/InstCombine/LandingPadClauses.ll
index 10af4bcadf68..0d42f7c737f3 100644
--- a/test/Transforms/InstCombine/LandingPadClauses.ll
+++ b/test/Transforms/InstCombine/LandingPadClauses.ll
@@ -7,6 +7,7 @@
 declare i32 @generic_personality(i32, i64, i8*, i8*)
 declare i32 @__gxx_personality_v0(i32, i64, i8*, i8*)
 declare i32 @__objc_personality_v0(i32, i64, i8*, i8*)
+declare i32 @__C_specific_handler(...)
 
 declare void @bar()
 
@@ -231,3 +232,54 @@ lpad.d:
 ; CHECK-NEXT: null
 ; CHECK-NEXT: unreachable
 }
+
+define void @foo_seh() {
+; CHECK-LABEL: @foo_seh(
+  invoke void @bar()
+    to label %cont.a unwind label %lpad.a
+cont.a:
+  invoke void @bar()
+    to label %cont.b unwind label %lpad.b
+cont.b:
+  invoke void @bar()
+    to label %cont.c unwind label %lpad.c
+cont.c:
+  invoke void @bar()
+    to label %cont.d unwind label %lpad.d
+cont.d:
+  ret void
+
+lpad.a:
+  %a = landingpad { i8*, i32 } personality i32 (...)* @__C_specific_handler
+          catch i32* null
+          catch i32* @T1
+  unreachable
+; CHECK: %a = landingpad
+; CHECK-NEXT: null
+; CHECK-NEXT: unreachable
+
+lpad.b:
+  %b = landingpad { i8*, i32 } personality i32 (...)* @__C_specific_handler
+          filter [1 x i32*] zeroinitializer
+  unreachable
+; CHECK: %b = landingpad
+; CHECK-NEXT: cleanup
+; CHECK-NEXT: unreachable
+
+lpad.c:
+  %c = landingpad { i8*, i32 } personality i32 (...)* @__C_specific_handler
+          filter [2 x i32*] [i32* @T1, i32* null]
+  unreachable
+; CHECK: %c = landingpad
+; CHECK-NEXT: cleanup
+; CHECK-NEXT: unreachable
+
+lpad.d:
+  %d = landingpad { i8*, i32 } personality i32 (...)* @__C_specific_handler
+          cleanup
+          catch i32* null
+  unreachable
+; CHECK: %d = landingpad
+; CHECK-NEXT: null
+; CHECK-NEXT: unreachable
+}
diff --git a/test/Transforms/InstCombine/PR7357.ll b/test/Transforms/InstCombine/PR7357.ll
index c397c5ee05e3..616c8225b2ac 100644
--- a/test/Transforms/InstCombine/PR7357.ll
+++ b/test/Transforms/InstCombine/PR7357.ll
@@ -8,7 +8,7 @@
 ; CHECK: call arm_aapcscc  i8* @strchr
 define arm_aapcscc i32 @foo(i32 %argc) nounwind {
 bb.nph:
-  %c = call arm_aapcscc  i8* @strchr(i8* getelementptr ([11 x i8]* @.str1, i32 0,
+  %c = call arm_aapcscc  i8* @strchr(i8* getelementptr ([11 x i8], [11 x i8]* @.str1, i32 0,
 i32 0), i32 %argc) nounwind readonly
   %p = ptrtoint i8* %c to i32
   ret i32 %p
diff --git a/test/Transforms/InstCombine/add2.ll b/test/Transforms/InstCombine/add2.ll
index fbbba5954b32..1af2b0ffbf0a 100644
--- a/test/Transforms/InstCombine/add2.ll
+++ b/test/Transforms/InstCombine/add2.ll
@@ -273,6 +273,35 @@ define i32 @mul_add_to_mul_6(i32 %x, i32 %y) {
 ; CHECK-NEXT: ret i32 %add
 }
 
+define i16 @mul_add_to_mul_7(i16 %x) {
+  %mul1 = mul nsw i16 %x, 32767
+  %add2 = add nsw i16 %x, %mul1
+  ret i16 %add2
+; CHECK-LABEL: @mul_add_to_mul_7(
+; CHECK-NEXT: %add2 = shl i16 %x, 15
+; CHECK-NEXT: ret i16 %add2
+}
+
+define i16 @mul_add_to_mul_8(i16 %a) {
+  %mul1 = mul nsw i16 %a, 16383
+  %mul2 = mul nsw i16 %a, 16384
+  %add = add nsw i16 %mul1, %mul2
+  ret i16 %add
+; CHECK-LABEL: @mul_add_to_mul_8(
+; CHECK-NEXT: %add = mul nsw i16 %a, 32767
+; CHECK-NEXT: ret i16 %add
+}
+
+define i16 @mul_add_to_mul_9(i16 %a) {
+  %mul1 = mul nsw i16 %a, 16384
+  %mul2 = mul nsw i16 %a, 16384
+  %add = add nsw i16 %mul1, %mul2
+  ret i16 %add
+; CHECK-LABEL: @mul_add_to_mul_9(
+; CHECK-NEXT: %add = shl i16 %a, 15
+; CHECK-NEXT: ret i16 %add
+}
+
 ; This test and the next test verify that when a range metadata is attached to
 ; llvm.cttz, ValueTracking correctly intersects the range specified by the
 ; metadata and the range implied by the intrinsic.
@@ -353,3 +382,16 @@ define i32 @add_nuw_nsw_or_and(i32 %x, i32 %y) {
 ; CHECK-NEXT: add nuw nsw i32 %x, %y
 ; CHECK-NEXT: ret i32
 }
+
+; A *nsw B + A *nsw C != A *nsw (B + C)
+; e.g. A = -1, B = 1, C = INT_SMAX
+
+define i8 @add_of_mul(i8 %x, i8 %y, i8 %z) {
+; CHECK-LABEL: @add_of_mul(
+ entry:
+  %mA = mul nsw i8 %x, %y
+  %mB = mul nsw i8 %x, %z
+; CHECK: %sum = mul i8
+  %sum = add nsw i8 %mA, %mB
+  ret i8 %sum
+}
diff --git a/test/Transforms/InstCombine/add3.ll b/test/Transforms/InstCombine/add3.ll
index cde3e24215f8..9d3842f1a31a 100644
--- a/test/Transforms/InstCombine/add3.ll
+++ b/test/Transforms/InstCombine/add3.ll
@@ -12,8 +12,8 @@ EntryBlock:
         store i32 1, i32* %1
         add i32 %.val24, -16
         inttoptr i32 %2 to i32*
-        getelementptr i32* %3, i32 1
-        load i32* %4
+        getelementptr i32, i32* %3, i32 1
+        load i32, i32* %4
         tail call i32 @callee( i32 %5 )
         ret void
 }
diff --git a/test/Transforms/InstCombine/addrspacecast.ll b/test/Transforms/InstCombine/addrspacecast.ll
index c1684361f99f..27f6b720d667 100644
--- a/test/Transforms/InstCombine/addrspacecast.ll
+++ b/test/Transforms/InstCombine/addrspacecast.ll
@@ -104,12 +104,12 @@ define <4 x float addrspace(2)*> @combine_addrspacecast_types_vector(<4 x i32 ad
 
 define i32 @canonicalize_addrspacecast([16 x i32] addrspace(1)* %arr) {
 ; CHECK-LABEL: @canonicalize_addrspacecast(
-; CHECK-NEXT: getelementptr inbounds [16 x i32] addrspace(1)* %arr, i32 0, i32 0
+; CHECK-NEXT: getelementptr inbounds [16 x i32], [16 x i32] addrspace(1)* %arr, i32 0, i32 0
 ; CHECK-NEXT: addrspacecast i32 addrspace(1)* %{{[a-zA-Z0-9]+}} to i32*
-; CHECK-NEXT: load i32*
+; CHECK-NEXT: load i32, i32*
 ; CHECK-NEXT: ret i32
   %p = addrspacecast [16 x i32] addrspace(1)* %arr to i32*
-  %v = load i32* %p
+  %v = load i32, i32* %p
   ret i32 %v
 }
 
@@ -127,14 +127,14 @@ declare void @foo(i8*) nounwind
 define i32 @memcpy_addrspacecast() nounwind {
 entry:
   %alloca = alloca i8, i32 48
-  call void @llvm.memcpy.p0i8.p1i8.i32(i8* %alloca, i8 addrspace(1)* addrspacecast (i8 addrspace(2)* getelementptr inbounds ([60 x i8] addrspace(2)* @const_array, i16 0, i16 4) to i8 addrspace(1)*), i32 48, i32 4, i1 false) nounwind
+  call void @llvm.memcpy.p0i8.p1i8.i32(i8* %alloca, i8 addrspace(1)* addrspacecast (i8 addrspace(2)* getelementptr inbounds ([60 x i8], [60 x i8] addrspace(2)* @const_array, i16 0, i16 4) to i8 addrspace(1)*), i32 48, i32 4, i1 false) nounwind
   br label %loop.body
 
 loop.body:
   %i = phi i32 [ 0, %entry ], [ %i.inc, %loop.body ]
   %sum = phi i32 [ 0, %entry ], [ %sum.inc, %loop.body]
-  %ptr = getelementptr i8* %alloca, i32 %i
-  %load = load i8* %ptr
+  %ptr = getelementptr i8, i8* %alloca, i32 %i
+  %load = load i8, i8* %ptr
   %ext = zext i8 %load to i32
   %sum.inc = add i32 %sum, %ext
   %i.inc = add i32 %i, 1
diff --git a/test/Transforms/InstCombine/alias-recursion.ll b/test/Transforms/InstCombine/alias-recursion.ll
index fa63726d2d33..74254f3e8dff 100644
--- a/test/Transforms/InstCombine/alias-recursion.ll
+++ b/test/Transforms/InstCombine/alias-recursion.ll
@@ -7,7 +7,7 @@ target triple = "x86_64-pc-windows-msvc"
 
 @0 = constant [1 x i8*] zeroinitializer
 
-@vtbl = alias getelementptr inbounds ([1 x i8*]* @0, i32 0, i32 0)
+@vtbl = alias getelementptr inbounds ([1 x i8*], [1 x i8*]* @0, i32 0, i32 0)
 
 define i32 (%class.A*)* @test() {
 ; CHECK-LABEL: test
@@ -19,6 +19,6 @@ for.body:                                         ; preds = %for.body, %entry
 
 for.end:                                          ; preds = %for.body, %entry
   %A = phi i32 (%class.A*)** [ bitcast (i8** @vtbl to i32 (%class.A*)**), %for.body ], [ null, %entry ]
-  %B = load i32 (%class.A*)** %A
+  %B = load i32 (%class.A*)*, i32 (%class.A*)** %A
   ret i32 (%class.A*)* %B
 }
diff --git a/test/Transforms/InstCombine/align-2d-gep.ll b/test/Transforms/InstCombine/align-2d-gep.ll
index f6a877684ce4..bbdb3f94cb28 100644
--- a/test/Transforms/InstCombine/align-2d-gep.ll
+++ b/test/Transforms/InstCombine/align-2d-gep.ll
@@ -22,11 +22,11 @@ bb7.outer:
 bb1:
   %j = phi i64 [ 0, %bb7.outer ], [ %indvar.next, %bb1 ]
 
-  %t4 = getelementptr [1001 x [20000 x double]]* @Nice, i64 0, i64 %i, i64 %j
+  %t4 = getelementptr [1001 x [20000 x double]], [1001 x [20000 x double]]* @Nice, i64 0, i64 %i, i64 %j
   %q = bitcast double* %t4 to <2 x double>*
   store <2 x double><double 0.0, double 0.0>, <2 x double>* %q, align 8
 
-  %s4 = getelementptr [1001 x [20001 x double]]* @Awkward, i64 0, i64 %i, i64 %j
+  %s4 = getelementptr [1001 x [20001 x double]], [1001 x [20001 x double]]* @Awkward, i64 0, i64 %i, i64 %j
   %r = bitcast double* %s4 to <2 x double>*
   store <2 x double><double 0.0, double 0.0>, <2 x double>* %r, align 8
 
diff --git a/test/Transforms/InstCombine/align-addr.ll b/test/Transforms/InstCombine/align-addr.ll
index 4d22c2cd2ef2..ab0ae390b145 100644
--- a/test/Transforms/InstCombine/align-addr.ll
+++ b/test/Transforms/InstCombine/align-addr.ll
@@ -21,7 +21,7 @@ bb:
   %i = phi i64 [ %indvar.next, %bb ], [ 20, %entry ]
   %j = mul i64 %i, %v
   %h = add i64 %j, %z
-  %t8 = getelementptr double* %e, i64 %h
+  %t8 = getelementptr double, double* %e, i64 %h
   %p = bitcast double* %t8 to <2 x double>*
   store <2 x double><double 0.0, double 0.0>, <2 x double>* %p, align 8
   %indvar.next = add i64 %i, 1
@@ -43,7 +43,7 @@ return:
 
 define <16 x i8> @test1(<2 x i64> %x) {
 entry:
-	%tmp = load <16 x i8>* bitcast ([4 x i32]* @GLOBAL to <16 x i8>*), align 1
+	%tmp = load <16 x i8>, <16 x i8>* bitcast ([4 x i32]* @GLOBAL to <16 x i8>*), align 1
 	ret <16 x i8> %tmp
 }
 
@@ -53,7 +53,7 @@ define <16 x i8> @test1_as1(<2 x i64> %x) {
 ; CHECK-LABEL: @test1_as1(
 ; CHECK: tmp = load
 ; CHECK: GLOBAL_as1{{.*}}align 16
-  %tmp = load <16 x i8> addrspace(1)* bitcast ([4 x i32] addrspace(1)* @GLOBAL_as1 to <16 x i8> addrspace(1)*), align 1
+  %tmp = load <16 x i8>, <16 x i8> addrspace(1)* bitcast ([4 x i32] addrspace(1)* @GLOBAL_as1 to <16 x i8> addrspace(1)*), align 1
   ret <16 x i8> %tmp
 }
 
@@ -63,7 +63,7 @@ define <16 x i8> @test1_as1_gep(<2 x i64> %x) {
 ; CHECK-LABEL: @test1_as1_gep(
 ; CHECK: tmp = load
 ; CHECK: GLOBAL_as1_gep{{.*}}align 16
-  %tmp = load <16 x i8> addrspace(1)* bitcast (i32 addrspace(1)* getelementptr ([8 x i32] addrspace(1)* @GLOBAL_as1_gep, i16 0, i16 4) to <16 x i8> addrspace(1)*), align 1
+  %tmp = load <16 x i8>, <16 x i8> addrspace(1)* bitcast (i32 addrspace(1)* getelementptr ([8 x i32], [8 x i32] addrspace(1)* @GLOBAL_as1_gep, i16 0, i16 4) to <16 x i8> addrspace(1)*), align 1
   ret <16 x i8> %tmp
 }
 
@@ -71,11 +71,11 @@ define <16 x i8> @test1_as1_gep(<2 x i64> %x) {
 ; When a load or store lacks an explicit alignment, add one.
 
 ; CHECK-LABEL: @test2(
-; CHECK: load double* %p, align 8
+; CHECK: load double, double* %p, align 8
 ; CHECK: store double %n, double* %p, align 8
 
 define double @test2(double* %p, double %n) nounwind {
-  %t = load double* %p
+  %t = load double, double* %p
   store double %n, double* %p
   ret double %t
 }
diff --git a/test/Transforms/InstCombine/align-attr.ll b/test/Transforms/InstCombine/align-attr.ll
index 9f366bf8fab1..99a17db13c4c 100644
--- a/test/Transforms/InstCombine/align-attr.ll
+++ b/test/Transforms/InstCombine/align-attr.ll
@@ -5,11 +5,11 @@ target triple = "x86_64-unknown-linux-gnu"
 ; Function Attrs: nounwind uwtable
 define i32 @foo1(i32* align 32 %a) #0 {
 entry:
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   ret i32 %0
 
 ; CHECK-LABEL: @foo1
-; CHECK-DAG: load i32* %a, align 32
+; CHECK-DAG: load i32, i32* %a, align 32
 ; CHECK: ret i32
 }
 
diff --git a/test/Transforms/InstCombine/align-external.ll b/test/Transforms/InstCombine/align-external.ll
index 66ff9c16e424..ee98a0120179 100644
--- a/test/Transforms/InstCombine/align-external.ll
+++ b/test/Transforms/InstCombine/align-external.ll
@@ -23,7 +23,7 @@ define i64 @foo(i64 %a) {
 
 define i32 @bar() {
 ; CHECK-LABEL: @bar(
-  %r = load i32* @B, align 1
+  %r = load i32, i32* @B, align 1
 ; CHECK: align 1
   ret i32 %r
 }
diff --git a/test/Transforms/InstCombine/aligned-altivec.ll b/test/Transforms/InstCombine/aligned-altivec.ll
new file mode 100644
index 000000000000..10b4e4d62631
--- /dev/null
+++ b/test/Transforms/InstCombine/aligned-altivec.ll
@@ -0,0 +1,131 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+declare <4 x i32> @llvm.ppc.altivec.lvx(i8*) #1
+
+define <4 x i32> @test1(<4 x i32>* %h) #0 {
+entry:
+  %h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
+  %hv = bitcast <4 x i32>* %h1 to i8*
+  %vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
+
+; CHECK-LABEL: @test1
+; CHECK: @llvm.ppc.altivec.lvx
+; CHECK: ret <4 x i32>
+
+  %v0 = load <4 x i32>, <4 x i32>* %h, align 8
+  %a = add <4 x i32> %v0, %vl
+  ret <4 x i32> %a
+}
+
+define <4 x i32> @test1a(<4 x i32>* align 16 %h) #0 {
+entry:
+  %h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
+  %hv = bitcast <4 x i32>* %h1 to i8*
+  %vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
+
+; CHECK-LABEL: @test1a
+; CHECK-NOT: @llvm.ppc.altivec.lvx
+; CHECK: ret <4 x i32>
+
+  %v0 = load <4 x i32>, <4 x i32>* %h, align 8
+  %a = add <4 x i32> %v0, %vl
+  ret <4 x i32> %a
+}
+
+declare void @llvm.ppc.altivec.stvx(<4 x i32>, i8*) #0
+
+define <4 x i32> @test2(<4 x i32>* %h, <4 x i32> %d) #0 {
+entry:
+  %h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
+  %hv = bitcast <4 x i32>* %h1 to i8*
+  call void @llvm.ppc.altivec.stvx(<4 x i32> %d, i8* %hv)
+
+  %v0 = load <4 x i32>, <4 x i32>* %h, align 8
+  ret <4 x i32> %v0
+
+; CHECK-LABEL: @test2
+; CHECK: @llvm.ppc.altivec.stvx
+; CHECK: ret <4 x i32>
+}
+
+define <4 x i32> @test2a(<4 x i32>* align 16 %h, <4 x i32> %d) #0 {
+entry:
+  %h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
+  %hv = bitcast <4 x i32>* %h1 to i8*
+  call void @llvm.ppc.altivec.stvx(<4 x i32> %d, i8* %hv)
+
+  %v0 = load <4 x i32>, <4 x i32>* %h, align 8
+  ret <4 x i32> %v0
+
+; CHECK-LABEL: @test2
+; CHECK-NOT: @llvm.ppc.altivec.stvx
+; CHECK: ret <4 x i32>
+}
+
+declare <4 x i32> @llvm.ppc.altivec.lvxl(i8*) #1
+
+define <4 x i32> @test1l(<4 x i32>* %h) #0 {
+entry:
+  %h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
+  %hv = bitcast <4 x i32>* %h1 to i8*
+  %vl = call <4 x i32> @llvm.ppc.altivec.lvxl(i8* %hv)
+
+; CHECK-LABEL: @test1l
+; CHECK: @llvm.ppc.altivec.lvxl
+; CHECK: ret <4 x i32>
+
+  %v0 = load <4 x i32>, <4 x i32>* %h, align 8
+  %a = add <4 x i32> %v0, %vl
+  ret <4 x i32> %a
+}
+
+define <4 x i32> @test1la(<4 x i32>* align 16 %h) #0 {
+entry:
+  %h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
+  %hv = bitcast <4 x i32>* %h1 to i8*
+  %vl = call <4 x i32> @llvm.ppc.altivec.lvxl(i8* %hv)
+
+; CHECK-LABEL: @test1la
+; CHECK-NOT: @llvm.ppc.altivec.lvxl
+; CHECK: ret <4 x i32>
+
+  %v0 = load <4 x i32>, <4 x i32>* %h, align 8
+  %a = add <4 x i32> %v0, %vl
+  ret <4 x i32> %a
+}
+
+declare void @llvm.ppc.altivec.stvxl(<4 x i32>, i8*) #0
+
+define <4 x i32> @test2l(<4 x i32>* %h, <4 x i32> %d) #0 {
+entry:
+  %h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
+  %hv = bitcast <4 x i32>* %h1 to i8*
+  call void @llvm.ppc.altivec.stvxl(<4 x i32> %d, i8* %hv)
+
+  %v0 = load <4 x i32>, <4 x i32>* %h, align 8
+  ret <4 x i32> %v0
+
+; CHECK-LABEL: @test2l
+; CHECK: @llvm.ppc.altivec.stvxl
+; CHECK: ret <4 x i32>
+}
+
+define <4 x i32> @test2la(<4 x i32>* align 16 %h, <4 x i32> %d) #0 {
+entry:
+  %h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
+  %hv = bitcast <4 x i32>* %h1 to i8*
+  call void @llvm.ppc.altivec.stvxl(<4 x i32> %d, i8* %hv)
+
+  %v0 = load <4 x i32>, <4 x i32>* %h, align 8
+  ret <4 x i32> %v0
+
+; CHECK-LABEL: @test2l
+; CHECK-NOT: @llvm.ppc.altivec.stvxl
+; CHECK: ret <4 x i32>
+}
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readonly }
+
diff --git a/test/Transforms/InstCombine/aligned-qpx.ll b/test/Transforms/InstCombine/aligned-qpx.ll
new file mode 100644
index 000000000000..e9710df5670c
--- /dev/null
+++ b/test/Transforms/InstCombine/aligned-qpx.ll
@@ -0,0 +1,165 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+declare <4 x double> @llvm.ppc.qpx.qvlfs(i8*) #1
+
+define <4 x double> @test1(<4 x float>* %h) #0 {
+entry:
+  %h1 = getelementptr <4 x float>, <4 x float>* %h, i64 1
+  %hv = bitcast <4 x float>* %h1 to i8*
+  %vl = call <4 x double> @llvm.ppc.qpx.qvlfs(i8* %hv)
+
+; CHECK-LABEL: @test1
+; CHECK: @llvm.ppc.qpx.qvlfs
+; CHECK: ret <4 x double>
+
+  %v0 = load <4 x float>, <4 x float>* %h, align 8
+  %v0e = fpext <4 x float> %v0 to <4 x double>
+  %a = fadd <4 x double> %v0e, %vl
+  ret <4 x double> %a
+}
+
+define <4 x double> @test1a(<4 x float>* align 16 %h) #0 {
+entry:
+  %h1 = getelementptr <4 x float>, <4 x float>* %h, i64 1
+  %hv = bitcast <4 x float>* %h1 to i8*
+  %vl = call <4 x double> @llvm.ppc.qpx.qvlfs(i8* %hv)
+
+; CHECK-LABEL: @test1a
+; CHECK-NOT: @llvm.ppc.qpx.qvlfs
+; CHECK-NOT: load <4 x double>
+; CHECK: ret <4 x double>
+
+  %v0 = load <4 x float>, <4 x float>* %h, align 8
+  %v0e = fpext <4 x float> %v0 to <4 x double>
+  %a = fadd <4 x double> %v0e, %vl
+  ret <4 x double> %a
+}
+
+declare void @llvm.ppc.qpx.qvstfs(<4 x double>, i8*) #0
+
+define <4 x float> @test2(<4 x float>* %h, <4 x double> %d) #0 {
+entry:
+  %h1 = getelementptr <4 x float>, <4 x float>* %h, i64 1
+  %hv = bitcast <4 x float>* %h1 to i8*
+  call void @llvm.ppc.qpx.qvstfs(<4 x double> %d, i8* %hv)
+
+  %v0 = load <4 x float>, <4 x float>* %h, align 8
+  ret <4 x float> %v0
+
+; CHECK-LABEL: @test2
+; CHECK: @llvm.ppc.qpx.qvstfs
+; CHECK: ret <4 x float>
+}
+
+define <4 x float> @test2a(<4 x float>* align 16 %h, <4 x double> %d) #0 {
+entry:
+  %h1 = getelementptr <4 x float>, <4 x float>* %h, i64 1
+  %hv = bitcast <4 x float>* %h1 to i8*
+  call void @llvm.ppc.qpx.qvstfs(<4 x double> %d, i8* %hv)
+
+  %v0 = load <4 x float>, <4 x float>* %h, align 8
+  ret <4 x float> %v0
+
+; CHECK-LABEL: @test2
+; CHECK: fptrunc <4 x double> %d to <4 x float>
+; CHECK-NOT: @llvm.ppc.qpx.qvstfs
+; CHECK-NOT: store <4 x double>
+; CHECK: ret <4 x float>
+}
+
+declare <4 x double> @llvm.ppc.qpx.qvlfd(i8*) #1
+
+define <4 x double> @test1l(<4 x double>* %h) #0 {
+entry:
+  %h1 = getelementptr <4 x double>, <4 x double>* %h, i64 1
+  %hv = bitcast <4 x double>* %h1 to i8*
+  %vl = call <4 x double> @llvm.ppc.qpx.qvlfd(i8* %hv)
+
+; CHECK-LABEL: @test1l
+; CHECK: @llvm.ppc.qpx.qvlfd
+; CHECK: ret <4 x double>
+
+  %v0 = load <4 x double>, <4 x double>* %h, align 8
+  %a = fadd <4 x double> %v0, %vl
+  ret <4 x double> %a
+}
+
+define <4 x double> @test1ln(<4 x double>* align 16 %h) #0 {
+entry:
+  %h1 = getelementptr <4 x double>, <4 x double>* %h, i64 1
+  %hv = bitcast <4 x double>* %h1 to i8*
+  %vl = call <4 x double> @llvm.ppc.qpx.qvlfd(i8* %hv)
+
+; CHECK-LABEL: @test1ln
+; CHECK: @llvm.ppc.qpx.qvlfd
+; CHECK: ret <4 x double>
+
+  %v0 = load <4 x double>, <4 x double>* %h, align 8
+  %a = fadd <4 x double> %v0, %vl
+  ret <4 x double> %a
+}
+
+define <4 x double> @test1la(<4 x double>* align 32 %h) #0 {
+entry:
+  %h1 = getelementptr <4 x double>, <4 x double>* %h, i64 1
+  %hv = bitcast <4 x double>* %h1 to i8*
+  %vl = call <4 x double> @llvm.ppc.qpx.qvlfd(i8* %hv)
+
+; CHECK-LABEL: @test1la
+; CHECK-NOT: @llvm.ppc.qpx.qvlfd
+; CHECK: ret <4 x double>
+
+  %v0 = load <4 x double>, <4 x double>* %h, align 8
+  %a = fadd <4 x double> %v0, %vl
+  ret <4 x double> %a
+}
+
+declare void @llvm.ppc.qpx.qvstfd(<4 x double>, i8*) #0
+
+define <4 x double> @test2l(<4 x double>* %h, <4 x double> %d) #0 {
+entry:
+  %h1 = getelementptr <4 x double>, <4 x double>* %h, i64 1
+  %hv = bitcast <4 x double>* %h1 to i8*
+  call void @llvm.ppc.qpx.qvstfd(<4 x double> %d, i8* %hv)
+
+  %v0 = load <4 x double>, <4 x double>* %h, align 8
+  ret <4 x double> %v0
+
+; CHECK-LABEL: @test2l
+; CHECK: @llvm.ppc.qpx.qvstfd
+; CHECK: ret <4 x double>
+}
+
+define <4 x double> @test2ln(<4 x double>* align 16 %h, <4 x double> %d) #0 {
+entry:
+  %h1 = getelementptr <4 x double>, <4 x double>* %h, i64 1
+  %hv = bitcast <4 x double>* %h1 to i8*
+  call void @llvm.ppc.qpx.qvstfd(<4 x double> %d, i8* %hv)
+
+  %v0 = load <4 x double>, <4 x double>* %h, align 8
+  ret <4 x double> %v0
+
+; CHECK-LABEL: @test2ln
+; CHECK: @llvm.ppc.qpx.qvstfd
+; CHECK: ret <4 x double>
+}
+
+define <4 x double> @test2la(<4 x double>* align 32 %h, <4 x double> %d) #0 {
+entry:
+  %h1 = getelementptr <4 x double>, <4 x double>* %h, i64 1
+  %hv = bitcast <4 x double>* %h1 to i8*
+  call void @llvm.ppc.qpx.qvstfd(<4 x double> %d, i8* %hv)
+
+  %v0 = load <4 x double>, <4 x double>* %h, align 8
+  ret <4 x double> %v0
+
+; CHECK-LABEL: @test2l
+; CHECK-NOT: @llvm.ppc.qpx.qvstfd
+; CHECK: ret <4 x double>
+}
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readonly }
+
diff --git a/test/Transforms/InstCombine/alloca.ll b/test/Transforms/InstCombine/alloca.ll
index 6d0c131c51ed..b61b75e9f9f3 100644
--- a/test/Transforms/InstCombine/alloca.ll
+++ b/test/Transforms/InstCombine/alloca.ll
@@ -1,6 +1,6 @@
-; RUN: opt < %s -instcombine -S -default-data-layout="E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" | FileCheck %s
-; RUN: opt < %s -instcombine -S -default-data-layout="E-p:32:32:32-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" | FileCheck %s -check-prefix=P32
-; RUN: opt < %s -instcombine -S | FileCheck %s -check-prefix=NODL
+; RUN: opt < %s -instcombine -S -default-data-layout="E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" | FileCheck %s -check-prefix=CHECK -check-prefix=ALL
+; RUN: opt < %s -instcombine -S -default-data-layout="E-p:32:32:32-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" | FileCheck %s -check-prefix=P32 -check-prefix=ALL
+; RUN: opt < %s -instcombine -S | FileCheck %s -check-prefix=NODL -check-prefix=ALL
 
 
 declare void @use(...)
@@ -13,14 +13,14 @@ declare void @use(...)
 ; CHECK-NOT: alloca
 define void @test() {
         %X = alloca [0 x i32]           ; <[0 x i32]*> [#uses=1]
-        call void (...)* @use( [0 x i32]* %X )
+        call void (...) @use( [0 x i32]* %X )
         %Y = alloca i32, i32 0          ; <i32*> [#uses=1]
-        call void (...)* @use( i32* %Y )
+        call void (...) @use( i32* %Y )
         %Z = alloca {  }                ; <{  }*> [#uses=1]
-        call void (...)* @use( {  }* %Z )
-        %size = load i32* @int
+        call void (...) @use( {  }* %Z )
+        %size = load i32, i32* @int
         %A = alloca {{}}, i32 %size
-        call void (...)* @use( {{}}* %A )
+        call void (...) @use( {{}}* %A )
         ret void
 }
 
@@ -38,7 +38,7 @@ define void @test2() {
 ; CHECK-NOT: alloca
 define void @test3() {
         %A = alloca { i32 }             ; <{ i32 }*> [#uses=1]
-        %B = getelementptr { i32 }* %A, i32 0, i32 0            ; <i32*> [#uses=1]
+        %B = getelementptr { i32 }, { i32 }* %A, i32 0, i32 0            ; <i32*> [#uses=1]
         store i32 123, i32* %B
         ret void
 }
@@ -62,16 +62,16 @@ define void @test5() {
 entry:
   %a = alloca { i32 }
   %b = alloca i32*
-  %a.1 = getelementptr { i32 }* %a, i32 0, i32 0
+  %a.1 = getelementptr { i32 }, { i32 }* %a, i32 0, i32 0
   store i32 123, i32* %a.1
   store i32* %a.1, i32** %b
   %b.1 = bitcast i32** %b to i32*
   store i32 123, i32* %b.1
-  %a.2 = getelementptr { i32 }* %a, i32 0, i32 0
+  %a.2 = getelementptr { i32 }, { i32 }* %a, i32 0, i32 0
   store atomic i32 2, i32* %a.2 unordered, align 4
-  %a.3 = getelementptr { i32 }* %a, i32 0, i32 0
+  %a.3 = getelementptr { i32 }, { i32 }* %a, i32 0, i32 0
   store atomic i32 3, i32* %a.3 release, align 4
-  %a.4 = getelementptr { i32 }* %a, i32 0, i32 0
+  %a.4 = getelementptr { i32 }, { i32 }* %a, i32 0, i32 0
   store atomic i32 4, i32* %a.4 seq_cst, align 4
   ret void
 }
@@ -89,7 +89,7 @@ define void @test6() {
 entry:
   %a = alloca { i32 }
   %b = alloca i32
-  %a.1 = getelementptr { i32 }* %a, i32 0, i32 0
+  %a.1 = getelementptr { i32 }, { i32 }* %a, i32 0, i32 0
   store volatile i32 123, i32* %a.1
   tail call void @f(i32* %b)
   ret void
@@ -116,17 +116,17 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32,
 define void @test8() {
 ; CHECK-LABEL: @test8(
 ; CHECK: alloca [100 x i32]
-; CHECK: getelementptr inbounds [100 x i32]* %x1, i64 0, i64 0
+; CHECK: getelementptr inbounds [100 x i32], [100 x i32]* %x1, i64 0, i64 0
 
 ; P32-LABEL: @test8(
 ; P32: alloca [100 x i32]
-; P32: getelementptr inbounds [100 x i32]* %x1, i32 0, i32 0
+; P32: getelementptr inbounds [100 x i32], [100 x i32]* %x1, i32 0, i32 0
 
 ; NODL-LABEL: @test8(
 ; NODL: alloca [100 x i32]
-; NODL: getelementptr inbounds [100 x i32]* %x1, i64 0, i64 0
+; NODL: getelementptr inbounds [100 x i32], [100 x i32]* %x1, i64 0, i64 0
   %x = alloca i32, i32 100
-  call void (...)* @use(i32* %x)
+  call void (...) @use(i32* %x)
   ret void
 }
 
@@ -142,7 +142,7 @@ entry:
   %inalloca.save = call i8* @llvm.stacksave()
   %argmem = alloca inalloca <{ %struct_type }>
 ; CHECK: alloca inalloca i64, align 8
-  %0 = getelementptr inbounds <{ %struct_type }>* %argmem, i32 0, i32 0
+  %0 = getelementptr inbounds <{ %struct_type }>, <{ %struct_type }>* %argmem, i32 0, i32 0
   %1 = bitcast %struct_type* %0 to i8*
   %2 = bitcast %struct_type* %a to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %1, i8* %2, i32 8, i32 4, i1 false)
@@ -150,3 +150,16 @@ entry:
   call void @llvm.stackrestore(i8* %inalloca.save)
   ret void
 }
+
+define void @test10() {
+entry:
+; ALL-LABEL: @test10(
+; ALL: %v32 = alloca i1, align 8
+; ALL: %v64 = alloca i1, align 8
+; ALL: %v33 = alloca i1, align 8
+  %v32 = alloca i1, align 8
+  %v64 = alloca i1, i64 1, align 8
+  %v33 = alloca i1, i33 1, align 8
+  call void (...) @use(i1* %v32, i1* %v64, i1* %v33)
+  ret void
+}
diff --git a/test/Transforms/InstCombine/assume-loop-align.ll b/test/Transforms/InstCombine/assume-loop-align.ll
index 19190de2cddd..e803ba61774d 100644
--- a/test/Transforms/InstCombine/assume-loop-align.ll
+++ b/test/Transforms/InstCombine/assume-loop-align.ll
@@ -19,16 +19,16 @@ entry:
   br label %for.body
 
 ; CHECK-LABEL: @foo
-; CHECK: load i32* {{.*}} align 64
+; CHECK: load i32, i32* {{.*}} align 64
 ; CHECK: store i32 {{.*}}  align 64
 ; CHECK: ret
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, 1
-  %arrayidx5 = getelementptr inbounds i32* %a, i64 %indvars.iv
+  %arrayidx5 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
   store i32 %add, i32* %arrayidx5, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 16
   %1 = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/InstCombine/assume-redundant.ll b/test/Transforms/InstCombine/assume-redundant.ll
index 81fe0945949b..4b869ef2c50e 100644
--- a/test/Transforms/InstCombine/assume-redundant.ll
+++ b/test/Transforms/InstCombine/assume-redundant.ll
@@ -15,8 +15,8 @@ define void @_Z3fooR1s(%struct.s* nocapture readonly dereferenceable(8) %x) #0 {
 ; CHECK-NOT: call void @llvm.assume
 
 entry:
-  %a = getelementptr inbounds %struct.s* %x, i64 0, i32 0
-  %0 = load double** %a, align 8
+  %a = getelementptr inbounds %struct.s, %struct.s* %x, i64 0, i32 0
+  %0 = load double*, double** %a, align 8
   %ptrint = ptrtoint double* %0 to i64
   %maskedptr = and i64 %ptrint, 31
   %maskcond = icmp eq i64 %maskedptr, 0
@@ -25,16 +25,16 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next.1, %for.body ]
   tail call void @llvm.assume(i1 %maskcond)
-  %arrayidx = getelementptr inbounds double* %0, i64 %indvars.iv
-  %1 = load double* %arrayidx, align 16
+  %arrayidx = getelementptr inbounds double, double* %0, i64 %indvars.iv
+  %1 = load double, double* %arrayidx, align 16
   %add = fadd double %1, 1.000000e+00
   tail call void @llvm.assume(i1 %maskcond)
   %mul = fmul double %add, 2.000000e+00
   store double %mul, double* %arrayidx, align 16
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   tail call void @llvm.assume(i1 %maskcond)
-  %arrayidx.1 = getelementptr inbounds double* %0, i64 %indvars.iv.next
-  %2 = load double* %arrayidx.1, align 8
+  %arrayidx.1 = getelementptr inbounds double, double* %0, i64 %indvars.iv.next
+  %2 = load double, double* %arrayidx.1, align 8
   %add.1 = fadd double %2, 1.000000e+00
   tail call void @llvm.assume(i1 %maskcond)
   %mul.1 = fmul double %add.1, 2.000000e+00
diff --git a/test/Transforms/InstCombine/assume.ll b/test/Transforms/InstCombine/assume.ll
index 7e45c04622ac..2f9213820f2b 100644
--- a/test/Transforms/InstCombine/assume.ll
+++ b/test/Transforms/InstCombine/assume.ll
@@ -5,12 +5,12 @@ target triple = "x86_64-unknown-linux-gnu"
 ; Function Attrs: nounwind uwtable
 define i32 @foo1(i32* %a) #0 {
 entry:
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
 
 ; Check that the alignment has been upgraded and that the assume has not
 ; been removed:
 ; CHECK-LABEL: @foo1
-; CHECK-DAG: load i32* %a, align 32
+; CHECK-DAG: load i32, i32* %a, align 32
 ; CHECK-DAG: call void @llvm.assume
 ; CHECK: ret i32
 
@@ -27,7 +27,7 @@ define i32 @foo2(i32* %a) #0 {
 entry:
 ; Same check as in @foo1, but make sure it works if the assume is first too.
 ; CHECK-LABEL: @foo2
-; CHECK-DAG: load i32* %a, align 32
+; CHECK-DAG: load i32, i32* %a, align 32
 ; CHECK-DAG: call void @llvm.assume
 ; CHECK: ret i32
 
@@ -36,7 +36,7 @@ entry:
   %maskcond = icmp eq i64 %maskedptr, 0
   tail call void @llvm.assume(i1 %maskcond)
 
-  %0 = load i32* %a, align 4
+  %0 = load i32, i32* %a, align 4
   ret i32 %0
 }
 
@@ -192,7 +192,7 @@ declare void @escape(i32* %a)
 ; metadata form?
 define i1 @nonnull1(i32** %a) {
 entry:
-  %load = load i32** %a
+  %load = load i32*, i32** %a
   %cmp = icmp ne i32* %load, null
   tail call void @llvm.assume(i1 %cmp)
   tail call void @escape(i32* %load)
@@ -209,7 +209,7 @@ entry:
 ; to pointer types.  Doing otherwise would be illegal.
 define i1 @nonnull2(i32* %a) {
 entry:
-  %load = load i32* %a
+  %load = load i32, i32* %a
   %cmp = icmp ne i32 %load, 0
   tail call void @llvm.assume(i1 %cmp)
   %rval = icmp eq i32 %load, 0
@@ -224,7 +224,7 @@ entry:
 ; if the assume is control dependent on something else
 define i1 @nonnull3(i32** %a, i1 %control) {
 entry:
-  %load = load i32** %a
+  %load = load i32*, i32** %a
   %cmp = icmp ne i32* %load, null
   br i1 %control, label %taken, label %not_taken
 taken:
@@ -244,7 +244,7 @@ not_taken:
 ; interrupted by an exception being thrown
 define i1 @nonnull4(i32** %a) {
 entry:
-  %load = load i32** %a
+  %load = load i32*, i32** %a
   ;; This call may throw!
   tail call void @escape(i32* %load)
   %cmp = icmp ne i32* %load, null
diff --git a/test/Transforms/InstCombine/atomic.ll b/test/Transforms/InstCombine/atomic.ll
index 98cecefcc294..5754a5a4ba56 100644
--- a/test/Transforms/InstCombine/atomic.ll
+++ b/test/Transforms/InstCombine/atomic.ll
@@ -7,10 +7,10 @@ target triple = "x86_64-apple-macosx10.7.0"
 
 define i32 @test2(i32* %p) {
 ; CHECK-LABEL: define i32 @test2(
-; CHECK: %x = load atomic i32* %p seq_cst, align 4
+; CHECK: %x = load atomic i32, i32* %p seq_cst, align 4
 ; CHECK: shl i32 %x, 1
-  %x = load atomic i32* %p seq_cst, align 4
-  %y = load i32* %p, align 4
+  %x = load atomic i32, i32* %p seq_cst, align 4
+  %y = load i32, i32* %p, align 4
   %z = add i32 %x, %y
   ret i32 %z
 }
diff --git a/test/Transforms/InstCombine/bitcast-alias-function.ll b/test/Transforms/InstCombine/bitcast-alias-function.ll
index cfec09200dbc..1a598a5d4153 100644
--- a/test/Transforms/InstCombine/bitcast-alias-function.ll
+++ b/test/Transforms/InstCombine/bitcast-alias-function.ll
@@ -91,12 +91,12 @@ define void @bitcast_alias_scalar(float* noalias %source, float* noalias %dest)
 entry:
 ; CHECK-LABEL: @bitcast_alias_scalar
 ; CHECK: bitcast float* %source to i32*
-; CHECK: load i32*
+; CHECK: load i32, i32*
 ; CHECK-NOT: fptoui
 ; CHECK-NOT: uitofp
 ; CHECK: bitcast float* %dest to i32*
 ; CHECK: store i32
-  %tmp = load float* %source, align 8
+  %tmp = load float, float* %source, align 8
   %call = call float @alias_i32_to_f32(float %tmp) nounwind
   store float %call, float* %dest, align 8
   ret void
@@ -107,12 +107,12 @@ define void @bitcast_alias_vector(<2 x float>* noalias %source, <2 x float>* noa
 entry:
 ; CHECK-LABEL: @bitcast_alias_vector
 ; CHECK: bitcast <2 x float>* %source to <2 x i32>*
-; CHECK: load <2 x i32>*
+; CHECK: load <2 x i32>, <2 x i32>*
 ; CHECK-NOT: fptoui
 ; CHECK-NOT: uitofp
 ; CHECK: bitcast <2 x float>* %dest to <2 x i32>*
 ; CHECK: store <2 x i32>
-  %tmp = load <2 x float>* %source, align 8
+  %tmp = load <2 x float>, <2 x float>* %source, align 8
   %call = call <2 x float> @alias_v2i32_to_v2f32(<2 x float> %tmp) nounwind
   store <2 x float> %call, <2 x float>* %dest, align 8
   ret void
@@ -123,11 +123,11 @@ define void @bitcast_alias_vector_scalar_same_size(<2 x float>* noalias %source,
 entry:
 ; CHECK-LABEL: @bitcast_alias_vector_scalar_same_size
 ; CHECK: bitcast <2 x float>* %source to i64*
-; CHECK: load i64*
+; CHECK: load i64, i64*
 ; CHECK: %call = call i64 @func_i64
 ; CHECK: bitcast <2 x float>* %dest to i64*
 ; CHECK: store i64
-  %tmp = load <2 x float>* %source, align 8
+  %tmp = load <2 x float>, <2 x float>* %source, align 8
   %call = call <2 x float> @alias_v2f32_to_i64(<2 x float> %tmp) nounwind
   store <2 x float> %call, <2 x float>* %dest, align 8
   ret void
@@ -137,11 +137,11 @@ define void @bitcast_alias_scalar_vector_same_size(i64* noalias %source, i64* no
 entry:
 ; CHECK-LABEL: @bitcast_alias_scalar_vector_same_size
 ; CHECK: bitcast i64* %source to <2 x float>*
-; CHECK: load <2 x float>*
+; CHECK: load <2 x float>, <2 x float>*
 ; CHECK: call <2 x float> @func_v2f32
 ; CHECK: bitcast i64* %dest to <2 x float>*
 ; CHECK: store <2 x float>
-  %tmp = load i64* %source, align 8
+  %tmp = load i64, i64* %source, align 8
   %call = call i64 @alias_i64_to_v2f32(i64 %tmp) nounwind
   store i64 %call, i64* %dest, align 8
   ret void
@@ -151,11 +151,11 @@ define void @bitcast_alias_vector_ptrs_same_size(<2 x i64*>* noalias %source, <2
 entry:
 ; CHECK-LABEL: @bitcast_alias_vector_ptrs_same_size
 ; CHECK: bitcast <2 x i64*>* %source to <2 x i32*>*
-; CHECK: load <2 x i32*>*
+; CHECK: load <2 x i32*>, <2 x i32*>*
 ; CHECK: call <2 x i32*> @func_v2i32p
 ; CHECK: bitcast <2 x i64*>* %dest to <2 x i32*>*
 ; CHECK: store <2 x i32*>
-  %tmp = load <2 x i64*>* %source, align 8
+  %tmp = load <2 x i64*>, <2 x i64*>* %source, align 8
   %call = call <2 x i64*> @alias_v2i32p_to_v2i64p(<2 x i64*> %tmp) nounwind
   store <2 x i64*> %call, <2 x i64*>* %dest, align 8
   ret void
@@ -169,7 +169,7 @@ entry:
 ; CHECK-NOT: fptoui
 ; CHECK: @alias_i64_to_f32
 ; CHECK-NOT: uitofp
-  %tmp = load float* %source, align 8
+  %tmp = load float, float* %source, align 8
   %call = call float @alias_i64_to_f32(float %tmp) nounwind
   store float %call, float* %dest, align 8
   ret void
@@ -181,7 +181,7 @@ entry:
 ; CHECK-NOT: fptoui <2 x float> %tmp to <2 x i64>
 ; CHECK: @alias_v2i64_to_v2f32
 ; CHECK-NOT: uitofp <2 x i64> %call to <2 x float>
-  %tmp = load <2 x float>* %source, align 8
+  %tmp = load <2 x float>, <2 x float>* %source, align 8
   %call = call <2 x float> @alias_v2i64_to_v2f32(<2 x float> %tmp) nounwind
   store <2 x float> %call, <2 x float>* %dest, align 8
   ret void
@@ -191,7 +191,7 @@ define void @bitcast_alias_vector_mismatched_number_elements(<4 x float>* noalia
 entry:
 ; CHECK-LABEL: @bitcast_alias_vector_mismatched_number_elements
 ; CHECK:  %call = call <4 x float> @alias_v2i32_to_v4f32
-  %tmp = load <4 x float>* %source, align 8
+  %tmp = load <4 x float>, <4 x float>* %source, align 8
   %call = call <4 x float> @alias_v2i32_to_v4f32(<4 x float> %tmp) nounwind
   store <4 x float> %call, <4 x float>* %dest, align 8
   ret void
@@ -201,7 +201,7 @@ define void @bitcast_alias_vector_scalar_mismatched_bit_size(<4 x float>* noalia
 entry:
 ; CHECK-LABEL: @bitcast_alias_vector_scalar_mismatched_bit_size
 ; CHECK:  %call = call <4 x float> @alias_v4f32_to_i64
-  %tmp = load <4 x float>* %source, align 8
+  %tmp = load <4 x float>, <4 x float>* %source, align 8
   %call = call <4 x float> @alias_v4f32_to_i64(<4 x float> %tmp) nounwind
   store <4 x float> %call, <4 x float>* %dest, align 8
   ret void
@@ -211,7 +211,7 @@ define void @bitcast_alias_vector_ptrs_scalar_mismatched_bit_size(<4 x i32*>* no
 entry:
 ; CHECK-LABEL: @bitcast_alias_vector_ptrs_scalar_mismatched_bit_size
 ; CHECK: @alias_v4i32p_to_i64
-  %tmp = load <4 x i32*>* %source, align 8
+  %tmp = load <4 x i32*>, <4 x i32*>* %source, align 8
   %call = call <4 x i32*> @alias_v4i32p_to_i64(<4 x i32*> %tmp) nounwind
   store <4 x i32*> %call, <4 x i32*>* %dest, align 8
   ret void
@@ -221,7 +221,7 @@ define void @bitcast_alias_scalar_vector_ptrs_same_size(i64* noalias %source, i6
 entry:
 ; CHECK-LABEL: @bitcast_alias_scalar_vector_ptrs_same_size
 ; CHECK: @alias_i64_to_v2i32p
-  %tmp = load i64* %source, align 8
+  %tmp = load i64, i64* %source, align 8
   %call = call i64 @alias_i64_to_v2i32p(i64 %tmp) nounwind
   store i64 %call, i64* %dest, align 8
   ret void
@@ -231,7 +231,7 @@ define void @bitcast_alias_scalar_vector_mismatched_bit_size(i64* noalias %sourc
 entry:
 ; CHECK-LABEL: @bitcast_alias_scalar_vector_mismatched_bit_size
 ; CHECK: call i64 @alias_i64_to_v4f32
-  %tmp = load i64* %source, align 8
+  %tmp = load i64, i64* %source, align 8
   %call = call i64 @alias_i64_to_v4f32(i64 %tmp) nounwind
   store i64 %call, i64* %dest, align 8
   ret void
diff --git a/test/Transforms/InstCombine/bitcast.ll b/test/Transforms/InstCombine/bitcast.ll
index c7a520bcf360..579839e4245b 100644
--- a/test/Transforms/InstCombine/bitcast.ll
+++ b/test/Transforms/InstCombine/bitcast.ll
@@ -148,7 +148,7 @@ define <2 x i16> @BitcastInsert(i32 %a) {
 ; PR17293
 define <2 x i64> @test7(<2 x i8*>* %arg) nounwind {
   %cast = bitcast <2 x i8*>* %arg to <2 x i64>*
-  %load = load <2 x i64>* %cast, align 16
+  %load = load <2 x i64>, <2 x i64>* %cast, align 16
   ret <2 x i64> %load
 ; CHECK: @test7
 ; CHECK: bitcast
diff --git a/test/Transforms/InstCombine/bittest.ll b/test/Transforms/InstCombine/bittest.ll
index 84ee7dd602d5..edf65d5a87ba 100644
--- a/test/Transforms/InstCombine/bittest.ll
+++ b/test/Transforms/InstCombine/bittest.ll
@@ -5,7 +5,7 @@
 
 define void @_Z12h000007_testv(i32* %P) {
 entry:
-        %tmp.2 = load i32* @b_rec.0             ; <i32> [#uses=1]
+        %tmp.2 = load i32, i32* @b_rec.0             ; <i32> [#uses=1]
         %tmp.9 = or i32 %tmp.2, -989855744              ; <i32> [#uses=2]
         %tmp.16 = and i32 %tmp.9, -805306369            ; <i32> [#uses=2]
         %tmp.17 = and i32 %tmp.9, -973078529            ; <i32> [#uses=1]
diff --git a/test/Transforms/InstCombine/branch.ll b/test/Transforms/InstCombine/branch.ll
new file mode 100644
index 000000000000..5be93cc20234
--- /dev/null
+++ b/test/Transforms/InstCombine/branch.ll
@@ -0,0 +1,16 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+define i32 @test(i32 %x) {
+; CHECK-LABEL: @test
+entry:
+; CHECK-NOT: icmp
+; CHECK: br i1 undef, 
+  %cmp = icmp ult i32 %x, 7
+  br i1 %cmp, label %merge, label %merge
+merge:
+; CHECK-LABEL: merge:
+; CHECK: ret i32 %x
+  ret i32 %x
+}
+
+
diff --git a/test/Transforms/InstCombine/call-cast-target.ll b/test/Transforms/InstCombine/call-cast-target.ll
index 4a5c94961e29..881e80762ea6 100644
--- a/test/Transforms/InstCombine/call-cast-target.ll
+++ b/test/Transforms/InstCombine/call-cast-target.ll
@@ -72,3 +72,18 @@ entry:
   %call = tail call i32 bitcast (i32 (i32)* @fn4 to i32 (i32*)*)(i32* %a)
   ret i32 %call
 }
+
+declare i1 @fn5({ i32, i32 }* byval align 4 %r)
+
+define i1 @test5() {
+; CHECK-LABEL: @test5
+; CHECK:      %[[call:.*]] = call i1 bitcast (i1 ({ i32, i32 }*)* @fn5 to i1 (i32, i32)*)(i32 {{.*}}, i32 {{.*}})
+; CHECK-NEXT: ret i1 %[[call]]
+  %1 = alloca { i32, i32 }, align 4
+  %2 = getelementptr inbounds { i32, i32 }, { i32, i32 }* %1, i32 0, i32 0
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds { i32, i32 }, { i32, i32 }* %1, i32 0, i32 1
+  %5 = load i32, i32* %4, align 4
+  %6 = call i1 bitcast (i1 ({ i32, i32 }*)* @fn5 to i1 (i32, i32)*)(i32 %3, i32 %5)
+  ret i1 %6
+}
diff --git a/test/Transforms/InstCombine/call-intrinsics.ll b/test/Transforms/InstCombine/call-intrinsics.ll
index f9d108058063..3e37a71e1bf6 100644
--- a/test/Transforms/InstCombine/call-intrinsics.ll
+++ b/test/Transforms/InstCombine/call-intrinsics.ll
@@ -3,17 +3,17 @@
 @X = global i8 0                ; <i8*> [#uses=3]
 @Y = global i8 12               ; <i8*> [#uses=2]
 
-declare void @llvm.memmove.i32(i8*, i8*, i32, i32)
+declare void @llvm.memmove.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
 
-declare void @llvm.memcpy.i32(i8*, i8*, i32, i32)
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
 
-declare void @llvm.memset.i32(i8*, i8, i32, i32)
+declare void @llvm.memset.p0i8.i32(i8*, i8, i32, i32, i1)
 
 define void @zero_byte_test() {
         ; These process zero bytes, so they are a noop.
-        call void @llvm.memmove.i32( i8* @X, i8* @Y, i32 0, i32 100 )
-        call void @llvm.memcpy.i32( i8* @X, i8* @Y, i32 0, i32 100 )
-        call void @llvm.memset.i32( i8* @X, i8 123, i32 0, i32 100 )
+        call void @llvm.memmove.p0i8.p0i8.i32( i8* @X, i8* @Y, i32 0, i32 128, i1 false )
+        call void @llvm.memcpy.p0i8.p0i8.i32( i8* @X, i8* @Y, i32 0, i32 128, i1 false )
+        call void @llvm.memset.p0i8.i32( i8* @X, i8 123, i32 0, i32 128, i1 false )
         ret void
 }
 
diff --git a/test/Transforms/InstCombine/call.ll b/test/Transforms/InstCombine/call.ll
index e68c0ad9b208..47ae71f37fb2 100644
--- a/test/Transforms/InstCombine/call.ll
+++ b/test/Transforms/InstCombine/call.ll
@@ -61,7 +61,7 @@ define void @test3a(i8, ...) {unreachable }
 define void @test3(i8 %A, i8 %B) {
 ; CHECK-LABEL: @test3(
 ; CHECK: %1 = zext i8 %B to i32
-; CHECK: call void (i8, ...)* @test3a(i8 %A, i32 %1)
+; CHECK: call void (i8, ...) @test3a(i8 %A, i32 %1)
 ; CHECK: ret void
   call void bitcast (void (i8, ...)* @test3a to void (i8, i8)*)( i8 %A, i8 %B)
   ret void
diff --git a/test/Transforms/InstCombine/call2.ll b/test/Transforms/InstCombine/call2.ll
index 1f45c7ab75dd..70a5b3ce36e3 100644
--- a/test/Transforms/InstCombine/call2.ll
+++ b/test/Transforms/InstCombine/call2.ll
@@ -4,11 +4,11 @@
 define i32 @bar() {
 entry:
 	%retval = alloca i32, align 4		; <i32*> [#uses=1]
-	%tmp = call i32 (...)* bitcast (i32 (i8*)* @f to i32 (...)*)( double 3.000000e+00 )		; <i32> [#uses=0]
+	%tmp = call i32 (...) bitcast (i32 (i8*)* @f to i32 (...)*)( double 3.000000e+00 )		; <i32> [#uses=0]
 	br label %return
 
 return:		; preds = %entry
-	%retval1 = load i32* %retval		; <i32> [#uses=1]
+	%retval1 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval1
 }
 
@@ -20,6 +20,6 @@ entry:
 	br label %return
 
 return:		; preds = %entry
-	%retval1 = load i32* %retval		; <i32> [#uses=1]
+	%retval1 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval1
 }
diff --git a/test/Transforms/InstCombine/cast.ll b/test/Transforms/InstCombine/cast.ll
index aac7a531b356..68f86336580b 100644
--- a/test/Transforms/InstCombine/cast.ll
+++ b/test/Transforms/InstCombine/cast.ll
@@ -93,9 +93,9 @@ declare void @varargs(i32, ...)
 
 define void @test11(i32* %P) {
         %c = bitcast i32* %P to i16*            ; <i16*> [#uses=1]
-        call void (i32, ...)* @varargs( i32 5, i16* %c )
+        call void (i32, ...) @varargs( i32 5, i16* %c )
         ret void
-; CHECK: call void (i32, ...)* @varargs(i32 5, i32* %P)
+; CHECK: call void (i32, ...) @varargs(i32 5, i32* %P)
 ; CHECK: ret void
 }
 
@@ -104,7 +104,7 @@ define void @test_invoke_vararg_cast(i32* %a, i32* %b) {
 entry:
   %0 = bitcast i32* %b to i8*
   %1 = bitcast i32* %a to i64*
-  invoke void (i32, ...)* @varargs(i32 1, i8* %0, i64* %1)
+  invoke void (i32, ...) @varargs(i32 1, i8* %0, i64* %1)
           to label %invoke.cont unwind label %lpad
 
 invoke.cont:                                      ; preds = %entry
@@ -116,13 +116,13 @@ lpad:                                             ; preds = %entry
   ret void
 ; CHECK-LABEL: test_invoke_vararg_cast
 ; CHECK-LABEL: entry:
-; CHECK: invoke void (i32, ...)* @varargs(i32 1, i32* %b, i32* %a)
+; CHECK: invoke void (i32, ...) @varargs(i32 1, i32* %b, i32* %a)
 }
 
 define i8* @test13(i64 %A) {
-        %c = getelementptr [0 x i8]* bitcast ([32832 x i8]* @inbuf to [0 x i8]*), i64 0, i64 %A             ; <i8*> [#uses=1]
+        %c = getelementptr [0 x i8], [0 x i8]* bitcast ([32832 x i8]* @inbuf to [0 x i8]*), i64 0, i64 %A             ; <i8*> [#uses=1]
         ret i8* %c
-; CHECK: %c = getelementptr [32832 x i8]* @inbuf, i64 0, i64 %A
+; CHECK: %c = getelementptr [32832 x i8], [32832 x i8]* @inbuf, i64 0, i64 %A
 ; CHECK: ret i8* %c
 }
 
@@ -187,8 +187,8 @@ define i32 @test21(i32 %X) {
         %c2 = sext i8 %c1 to i32                ; <i32> [#uses=1]
         %RV = and i32 %c2, 255          ; <i32> [#uses=1]
         ret i32 %RV
-; CHECK: %c21 = and i32 %X, 255
-; CHECK: ret i32 %c21
+; CHECK: %c2.1 = and i32 %X, 255
+; CHECK: ret i32 %c2.1
 }
 
 define i32 @test22(i32 %X) {
@@ -231,14 +231,14 @@ define i32 @test26(float %F) {
 define [4 x float]* @test27([9 x [4 x float]]* %A) {
         %c = bitcast [9 x [4 x float]]* %A to [4 x float]*              ; <[4 x float]*> [#uses=1]
         ret [4 x float]* %c
-; CHECK: %c = getelementptr inbounds [9 x [4 x float]]* %A, i64 0, i64 0
+; CHECK: %c = getelementptr inbounds [9 x [4 x float]], [9 x [4 x float]]* %A, i64 0, i64 0
 ; CHECK: ret [4 x float]* %c
 }
 
 define float* @test28([4 x float]* %A) {
         %c = bitcast [4 x float]* %A to float*          ; <float*> [#uses=1]
         ret float* %c
-; CHECK: %c = getelementptr inbounds [4 x float]* %A, i64 0, i64 0
+; CHECK: %c = getelementptr inbounds [4 x float], [4 x float]* %A, i64 0, i64 0
 ; CHECK: ret float* %c
 }
 
@@ -359,7 +359,7 @@ define i16 @test40(i16 %a) {
 ; PR1263
 define i32* @test41(i32* %tmp1) {
         %tmp64 = bitcast i32* %tmp1 to { i32 }*
-        %tmp65 = getelementptr { i32 }* %tmp64, i32 0, i32 0
+        %tmp65 = getelementptr { i32 }, { i32 }* %tmp64, i32 0, i32 0
         ret i32* %tmp65
 ; CHECK-LABEL: @test41(
 ; CHECK: ret i32* %tmp1
@@ -367,7 +367,7 @@ define i32* @test41(i32* %tmp1) {
 
 define i32 addrspace(1)* @test41_addrspacecast_smaller(i32* %tmp1) {
   %tmp64 = addrspacecast i32* %tmp1 to { i32 } addrspace(1)*
-  %tmp65 = getelementptr { i32 } addrspace(1)* %tmp64, i32 0, i32 0
+  %tmp65 = getelementptr { i32 }, { i32 } addrspace(1)* %tmp64, i32 0, i32 0
   ret i32 addrspace(1)* %tmp65
 ; CHECK-LABEL: @test41_addrspacecast_smaller(
 ; CHECK: addrspacecast i32* %tmp1 to i32 addrspace(1)*
@@ -376,7 +376,7 @@ define i32 addrspace(1)* @test41_addrspacecast_smaller(i32* %tmp1) {
 
 define i32* @test41_addrspacecast_larger(i32 addrspace(1)* %tmp1) {
   %tmp64 = addrspacecast i32 addrspace(1)* %tmp1 to { i32 }*
-  %tmp65 = getelementptr { i32 }* %tmp64, i32 0, i32 0
+  %tmp65 = getelementptr { i32 }, { i32 }* %tmp64, i32 0, i32 0
   ret i32* %tmp65
 ; CHECK-LABEL: @test41_addrspacecast_larger(
 ; CHECK: addrspacecast i32 addrspace(1)* %tmp1 to i32*
@@ -728,11 +728,11 @@ define %s @test68(%s *%p, i64 %i) {
 ; CHECK-LABEL: @test68(
   %o = mul i64 %i, 12
   %q = bitcast %s* %p to i8*
-  %pp = getelementptr inbounds i8* %q, i64 %o
-; CHECK-NEXT: getelementptr %s*
+  %pp = getelementptr inbounds i8, i8* %q, i64 %o
+; CHECK-NEXT: getelementptr %s, %s*
   %r = bitcast i8* %pp to %s*
-  %l = load %s* %r
-; CHECK-NEXT: load %s*
+  %l = load %s, %s* %r
+; CHECK-NEXT: load %s, %s*
   ret %s %l
 ; CHECK-NEXT: ret %s
 }
@@ -740,28 +740,28 @@ define %s @test68(%s *%p, i64 %i) {
 ; addrspacecasts should be eliminated.
 define %s @test68_addrspacecast(%s* %p, i64 %i) {
 ; CHECK-LABEL: @test68_addrspacecast(
-; CHECK-NEXT: getelementptr %s*
-; CHECK-NEXT: load %s*
+; CHECK-NEXT: getelementptr %s, %s*
+; CHECK-NEXT: load %s, %s*
 ; CHECK-NEXT: ret %s
   %o = mul i64 %i, 12
   %q = addrspacecast %s* %p to i8 addrspace(2)*
-  %pp = getelementptr inbounds i8 addrspace(2)* %q, i64 %o
+  %pp = getelementptr inbounds i8, i8 addrspace(2)* %q, i64 %o
   %r = addrspacecast i8 addrspace(2)* %pp to %s*
-  %l = load %s* %r
+  %l = load %s, %s* %r
   ret %s %l
 }
 
 define %s @test68_addrspacecast_2(%s* %p, i64 %i) {
 ; CHECK-LABEL: @test68_addrspacecast_2(
-; CHECK-NEXT: getelementptr %s* %p
+; CHECK-NEXT: getelementptr %s, %s* %p
 ; CHECK-NEXT: addrspacecast
-; CHECK-NEXT: load %s addrspace(1)*
+; CHECK-NEXT: load %s, %s addrspace(1)*
 ; CHECK-NEXT: ret %s
   %o = mul i64 %i, 12
   %q = addrspacecast %s* %p to i8 addrspace(2)*
-  %pp = getelementptr inbounds i8 addrspace(2)* %q, i64 %o
+  %pp = getelementptr inbounds i8, i8 addrspace(2)* %q, i64 %o
   %r = addrspacecast i8 addrspace(2)* %pp to %s addrspace(1)*
-  %l = load %s addrspace(1)* %r
+  %l = load %s, %s addrspace(1)* %r
   ret %s %l
 }
 
@@ -769,11 +769,11 @@ define %s @test68_as1(%s addrspace(1)* %p, i32 %i) {
 ; CHECK-LABEL: @test68_as1(
   %o = mul i32 %i, 12
   %q = bitcast %s addrspace(1)* %p to i8 addrspace(1)*
-  %pp = getelementptr inbounds i8 addrspace(1)* %q, i32 %o
-; CHECK-NEXT: getelementptr %s addrspace(1)*
+  %pp = getelementptr inbounds i8, i8 addrspace(1)* %q, i32 %o
+; CHECK-NEXT: getelementptr %s, %s addrspace(1)*
   %r = bitcast i8 addrspace(1)* %pp to %s addrspace(1)*
-  %l = load %s addrspace(1)* %r
-; CHECK-NEXT: load %s addrspace(1)*
+  %l = load %s, %s addrspace(1)* %r
+; CHECK-NEXT: load %s, %s addrspace(1)*
   ret %s %l
 ; CHECK-NEXT: ret %s
 }
@@ -782,11 +782,11 @@ define double @test69(double *%p, i64 %i) {
 ; CHECK-LABEL: @test69(
   %o = shl nsw i64 %i, 3
   %q = bitcast double* %p to i8*
-  %pp = getelementptr inbounds i8* %q, i64 %o
-; CHECK-NEXT: getelementptr inbounds double*
+  %pp = getelementptr inbounds i8, i8* %q, i64 %o
+; CHECK-NEXT: getelementptr inbounds double, double*
   %r = bitcast i8* %pp to double*
-  %l = load double* %r
-; CHECK-NEXT: load double*
+  %l = load double, double* %r
+; CHECK-NEXT: load double, double*
   ret double %l
 ; CHECK-NEXT: ret double
 }
@@ -796,11 +796,11 @@ define %s @test70(%s *%p, i64 %i) {
   %o = mul nsw i64 %i, 36
 ; CHECK-NEXT: mul nsw i64 %i, 3
   %q = bitcast %s* %p to i8*
-  %pp = getelementptr inbounds i8* %q, i64 %o
-; CHECK-NEXT: getelementptr inbounds %s*
+  %pp = getelementptr inbounds i8, i8* %q, i64 %o
+; CHECK-NEXT: getelementptr inbounds %s, %s*
   %r = bitcast i8* %pp to %s*
-  %l = load %s* %r
-; CHECK-NEXT: load %s*
+  %l = load %s, %s* %r
+; CHECK-NEXT: load %s, %s*
   ret %s %l
 ; CHECK-NEXT: ret %s
 }
@@ -810,11 +810,11 @@ define double @test71(double *%p, i64 %i) {
   %o = shl i64 %i, 5
 ; CHECK-NEXT: shl i64 %i, 2
   %q = bitcast double* %p to i8*
-  %pp = getelementptr i8* %q, i64 %o
-; CHECK-NEXT: getelementptr double*
+  %pp = getelementptr i8, i8* %q, i64 %o
+; CHECK-NEXT: getelementptr double, double*
   %r = bitcast i8* %pp to double*
-  %l = load double* %r
-; CHECK-NEXT: load double*
+  %l = load double, double* %r
+; CHECK-NEXT: load double, double*
   ret double %l
 ; CHECK-NEXT: ret double
 }
@@ -825,11 +825,11 @@ define double @test72(double *%p, i32 %i) {
   %o = sext i32 %so to i64
 ; CHECK-NEXT: sext i32 %i to i64
   %q = bitcast double* %p to i8*
-  %pp = getelementptr inbounds i8* %q, i64 %o
-; CHECK-NEXT: getelementptr inbounds double*
+  %pp = getelementptr inbounds i8, i8* %q, i64 %o
+; CHECK-NEXT: getelementptr inbounds double, double*
   %r = bitcast i8* %pp to double*
-  %l = load double* %r
-; CHECK-NEXT: load double*
+  %l = load double, double* %r
+; CHECK-NEXT: load double, double*
   ret double %l
 ; CHECK-NEXT: ret double
 }
@@ -840,11 +840,11 @@ define double @test73(double *%p, i128 %i) {
   %o = trunc i128 %lo to i64
 ; CHECK-NEXT: trunc i128 %i to i64
   %q = bitcast double* %p to i8*
-  %pp = getelementptr inbounds i8* %q, i64 %o
-; CHECK-NEXT: getelementptr double*
+  %pp = getelementptr inbounds i8, i8* %q, i64 %o
+; CHECK-NEXT: getelementptr double, double*
   %r = bitcast i8* %pp to double*
-  %l = load double* %r
-; CHECK-NEXT: load double*
+  %l = load double, double* %r
+; CHECK-NEXT: load double, double*
   ret double %l
 ; CHECK-NEXT: ret double
 }
@@ -852,11 +852,11 @@ define double @test73(double *%p, i128 %i) {
 define double @test74(double *%p, i64 %i) {
 ; CHECK-LABEL: @test74(
   %q = bitcast double* %p to i64*
-  %pp = getelementptr inbounds i64* %q, i64 %i
-; CHECK-NEXT: getelementptr inbounds double*
+  %pp = getelementptr inbounds i64, i64* %q, i64 %i
+; CHECK-NEXT: getelementptr inbounds double, double*
   %r = bitcast i64* %pp to double*
-  %l = load double* %r
-; CHECK-NEXT: load double*
+  %l = load double, double* %r
+; CHECK-NEXT: load double, double*
   ret double %l
 ; CHECK-NEXT: ret double
 }
@@ -868,7 +868,7 @@ define i32* @test75(i32* %p, i32 %x) {
   %z = sext i32 %y to i64
 ; CHECK-NEXT: sext i32 %y to i64
   %q = bitcast i32* %p to i8*
-  %r = getelementptr i8* %q, i64 %z
+  %r = getelementptr i8, i8* %q, i64 %z
   %s = bitcast i8* %r to i32*
   ret i32* %s
 }
@@ -879,11 +879,11 @@ define %s @test76(%s *%p, i64 %i, i64 %j) {
   %o2 = mul nsw i64 %o, %j
 ; CHECK-NEXT: %o2 = mul i64 %i, %j
   %q = bitcast %s* %p to i8*
-  %pp = getelementptr inbounds i8* %q, i64 %o2
-; CHECK-NEXT: getelementptr %s* %p, i64 %o2
+  %pp = getelementptr inbounds i8, i8* %q, i64 %o2
+; CHECK-NEXT: getelementptr %s, %s* %p, i64 %o2
   %r = bitcast i8* %pp to %s*
-  %l = load %s* %r
-; CHECK-NEXT: load %s*
+  %l = load %s, %s* %r
+; CHECK-NEXT: load %s, %s*
   ret %s %l
 ; CHECK-NEXT: ret %s
 }
@@ -895,11 +895,11 @@ define %s @test77(%s *%p, i64 %i, i64 %j) {
 ; CHECK-NEXT: %o = mul nsw i64 %i, 3
 ; CHECK-NEXT: %o2 = mul nsw i64 %o, %j
   %q = bitcast %s* %p to i8*
-  %pp = getelementptr inbounds i8* %q, i64 %o2
-; CHECK-NEXT: getelementptr inbounds %s* %p, i64 %o2
+  %pp = getelementptr inbounds i8, i8* %q, i64 %o2
+; CHECK-NEXT: getelementptr inbounds %s, %s* %p, i64 %o2
   %r = bitcast i8* %pp to %s*
-  %l = load %s* %r
-; CHECK-NEXT: load %s*
+  %l = load %s, %s* %r
+; CHECK-NEXT: load %s, %s*
   ret %s %l
 ; CHECK-NEXT: ret %s
 }
@@ -923,11 +923,11 @@ define %s @test78(%s *%p, i64 %i, i64 %j, i32 %k, i32 %l, i128 %m, i128 %n) {
   %h = mul nsw i64 %g, %j
 ; CHECK-NEXT: mul i64 %g, %j
   %q = bitcast %s* %p to i8*
-  %pp = getelementptr inbounds i8* %q, i64 %h
-; CHECK-NEXT: getelementptr %s* %p, i64 %h
+  %pp = getelementptr inbounds i8, i8* %q, i64 %h
+; CHECK-NEXT: getelementptr %s, %s* %p, i64 %h
   %r = bitcast i8* %pp to %s*
-  %load = load %s* %r
-; CHECK-NEXT: load %s*
+  %load = load %s, %s* %r
+; CHECK-NEXT: load %s, %s*
   ret %s %load
 ; CHECK-NEXT: ret %s
 }
@@ -940,9 +940,9 @@ define %s @test79(%s *%p, i64 %i, i32 %j) {
   %c = mul i32 %b, %j
   %q = bitcast %s* %p to i8*
 ; CHECK: bitcast
-  %pp = getelementptr inbounds i8* %q, i32 %c
+  %pp = getelementptr inbounds i8, i8* %q, i32 %c
   %r = bitcast i8* %pp to %s*
-  %l = load %s* %r
+  %l = load %s, %s* %r
   ret %s %l
 }
 
@@ -951,39 +951,39 @@ define double @test80([100 x double]* %p, i32 %i) {
   %tmp = shl nsw i32 %i, 3
 ; CHECK-NEXT: sext i32 %i to i64
   %q = bitcast [100 x double]* %p to i8*
-  %pp = getelementptr i8* %q, i32 %tmp
-; CHECK-NEXT: getelementptr [100 x double]*
+  %pp = getelementptr i8, i8* %q, i32 %tmp
+; CHECK-NEXT: getelementptr [100 x double], [100 x double]*
   %r = bitcast i8* %pp to double*
-  %l = load double* %r
-; CHECK-NEXT: load double*
+  %l = load double, double* %r
+; CHECK-NEXT: load double, double*
   ret double %l
 ; CHECK-NEXT: ret double
 }
 
 define double @test80_addrspacecast([100 x double] addrspace(1)* %p, i32 %i) {
 ; CHECK-LABEL: @test80_addrspacecast(
-; CHECK-NEXT: getelementptr [100 x double] addrspace(1)* %p
-; CHECK-NEXT: load double addrspace(1)*
+; CHECK-NEXT: getelementptr [100 x double], [100 x double] addrspace(1)* %p
+; CHECK-NEXT: load double, double addrspace(1)*
 ; CHECK-NEXT: ret double
   %tmp = shl nsw i32 %i, 3
   %q = addrspacecast [100 x double] addrspace(1)* %p to i8 addrspace(2)*
-  %pp = getelementptr i8 addrspace(2)* %q, i32 %tmp
+  %pp = getelementptr i8, i8 addrspace(2)* %q, i32 %tmp
   %r = addrspacecast i8 addrspace(2)* %pp to double addrspace(1)*
-  %l = load double addrspace(1)* %r
+  %l = load double, double addrspace(1)* %r
   ret double %l
 }
 
 define double @test80_addrspacecast_2([100 x double] addrspace(1)* %p, i32 %i) {
 ; CHECK-LABEL: @test80_addrspacecast_2(
-; CHECK-NEXT: getelementptr [100 x double] addrspace(1)*
+; CHECK-NEXT: getelementptr [100 x double], [100 x double] addrspace(1)*
 ; CHECK-NEXT: addrspacecast double addrspace(1)*
-; CHECK-NEXT: load double addrspace(3)*
+; CHECK-NEXT: load double, double addrspace(3)*
 ; CHECK-NEXT: ret double
   %tmp = shl nsw i32 %i, 3
   %q = addrspacecast [100 x double] addrspace(1)* %p to i8 addrspace(2)*
-  %pp = getelementptr i8 addrspace(2)* %q, i32 %tmp
+  %pp = getelementptr i8, i8 addrspace(2)* %q, i32 %tmp
   %r = addrspacecast i8 addrspace(2)* %pp to double addrspace(3)*
-  %l = load double addrspace(3)* %r
+  %l = load double, double addrspace(3)* %r
   ret double %l
 }
 
@@ -992,11 +992,11 @@ define double @test80_as1([100 x double] addrspace(1)* %p, i16 %i) {
   %tmp = shl nsw i16 %i, 3
 ; CHECK-NEXT: sext i16 %i to i32
   %q = bitcast [100 x double] addrspace(1)* %p to i8 addrspace(1)*
-  %pp = getelementptr i8 addrspace(1)* %q, i16 %tmp
-; CHECK-NEXT: getelementptr [100 x double] addrspace(1)*
+  %pp = getelementptr i8, i8 addrspace(1)* %q, i16 %tmp
+; CHECK-NEXT: getelementptr [100 x double], [100 x double] addrspace(1)*
   %r = bitcast i8 addrspace(1)* %pp to double addrspace(1)*
-  %l = load double addrspace(1)* %r
-; CHECK-NEXT: load double addrspace(1)*
+  %l = load double, double addrspace(1)* %r
+; CHECK-NEXT: load double, double addrspace(1)*
   ret double %l
 ; CHECK-NEXT: ret double
 }
@@ -1004,9 +1004,9 @@ define double @test80_as1([100 x double] addrspace(1)* %p, i16 %i) {
 define double @test81(double *%p, float %f) {
   %i = fptosi float %f to i64
   %q = bitcast double* %p to i8*
-  %pp = getelementptr i8* %q, i64 %i
+  %pp = getelementptr i8, i8* %q, i64 %i
   %r = bitcast i8* %pp to double*
-  %l = load double* %r
+  %l = load double, double* %r
   ret double %l
 }
 
@@ -1104,3 +1104,36 @@ define i32 @PR21388(i32* %v) {
 ; CHECK-NEXT: %[[sext:.*]] = sext i1 %[[icmp]] to i32
 ; CHECK-NEXT: ret i32 %[[sext]]
 }
+
+define float @sitofp_zext(i16 %a) {
+; CHECK-LABEL: @sitofp_zext(
+; CHECK-NEXT: %[[sitofp:.*]] = uitofp i16 %a to float
+; CHECK-NEXT: ret float %[[sitofp]]
+  %zext = zext i16 %a to i32
+  %sitofp = sitofp i32 %zext to float
+  ret float %sitofp
+}
+
+define i1 @PR23309(i32 %A, i32 %B) {
+; CHECK-LABEL: @PR23309(
+; CHECK-NEXT: %[[sub:.*]] = sub i32 %A, %B
+; CHECK-NEXT: %[[and:.*]] = and i32 %[[sub]], 1
+; CHECK-NEXT: %[[cmp:.*]] = icmp ne i32 %[[and]], 0
+; CHECK-NEXT: ret i1 %[[cmp]]
+  %add = add i32 %A, -4
+  %sub = sub nsw i32 %add, %B
+  %trunc = trunc i32 %sub to i1
+  ret i1 %trunc
+}
+
+define i1 @PR23309v2(i32 %A, i32 %B) {
+; CHECK-LABEL: @PR23309v2(
+; CHECK-NEXT: %[[sub:.*]] = add i32 %A, %B
+; CHECK-NEXT: %[[and:.*]] = and i32 %[[sub]], 1
+; CHECK-NEXT: %[[cmp:.*]] = icmp ne i32 %[[and]], 0
+; CHECK-NEXT: ret i1 %[[cmp]]
+  %add = add i32 %A, -4
+  %sub = add nuw i32 %add, %B
+  %trunc = trunc i32 %sub to i1
+  ret i1 %trunc
+}
diff --git a/test/Transforms/InstCombine/cast_ptr.ll b/test/Transforms/InstCombine/cast_ptr.ll
index 23006a84604b..eaf946ef9259 100644
--- a/test/Transforms/InstCombine/cast_ptr.ll
+++ b/test/Transforms/InstCombine/cast_ptr.ll
@@ -3,6 +3,8 @@
 
 target datalayout = "p:32:32-p1:32:32-p2:16:16"
 
+@global = global i8 0
+
 ; This shouldn't convert to getelementptr because the relationship
 ; between the arithmetic and the layout of allocated memory is
 ; entirely unknown.
@@ -47,10 +49,29 @@ define i1 @test2_as2_larger(i8 addrspace(2)* %a, i8 addrspace(2)* %b) {
   ret i1 %r
 }
 
+; These casts should not be folded away.
+; CHECK-LABEL: @test2_diff_as
+; CHECK: icmp sge i32 %i0, %i1
+define i1 @test2_diff_as(i8* %p, i8 addrspace(1)* %q) {
+  %i0 = ptrtoint i8* %p to i32
+  %i1 = ptrtoint i8 addrspace(1)* %q to i32
+  %r0 = icmp sge i32 %i0, %i1
+  ret i1 %r0
+}
+
+; These casts should not be folded away.
+; CHECK-LABEL: @test2_diff_as_global
+; CHECK: icmp sge i32 %i1
+define i1 @test2_diff_as_global(i8 addrspace(1)* %q) {
+  %i0 = ptrtoint i8* @global to i32
+  %i1 = ptrtoint i8 addrspace(1)* %q to i32
+  %r0 = icmp sge i32 %i1, %i0
+  ret i1 %r0
+}
+
 ; These casts should also be folded away.
 ; CHECK-LABEL: @test3(
 ; CHECK: icmp eq i8* %a, @global
-@global = global i8 0
 define i1 @test3(i8* %a) {
         %tmpa = ptrtoint i8* %a to i32
         %r = icmp eq i32 %tmpa, ptrtoint (i8* @global to i32)
@@ -86,7 +107,7 @@ define i1 @test4_as2(i16 %A) {
 declare %op* @foo(%op* %X)
 
 define %unop* @test5(%op* %O) {
-        %tmp = load %unop* (%op*)** bitcast ([1 x %op* (%op*)*]* @Array to %unop* (%op*)**); <%unop* (%op*)*> [#uses=1]
+        %tmp = load %unop* (%op*)*, %unop* (%op*)** bitcast ([1 x %op* (%op*)*]* @Array to %unop* (%op*)**); <%unop* (%op*)*> [#uses=1]
         %tmp.2 = call %unop* %tmp( %op* %O )            ; <%unop*> [#uses=1]
         ret %unop* %tmp.2
 ; CHECK-LABEL: @test5(
@@ -101,8 +122,8 @@ define %unop* @test5(%op* %O) {
 define i8 @test6(i8 addrspace(1)* %source) {
 entry:
   %arrayidx223 = addrspacecast i8 addrspace(1)* %source to i8*
-  %tmp4 = load i8* %arrayidx223
+  %tmp4 = load i8, i8* %arrayidx223
   ret i8 %tmp4
 ; CHECK-LABEL: @test6(
-; CHECK: load i8* %arrayidx223
+; CHECK: load i8, i8* %arrayidx223
 }
diff --git a/test/Transforms/InstCombine/constant-expr-datalayout.ll b/test/Transforms/InstCombine/constant-expr-datalayout.ll
index 9a72c77afdb0..cdecfc91f592 100644
--- a/test/Transforms/InstCombine/constant-expr-datalayout.ll
+++ b/test/Transforms/InstCombine/constant-expr-datalayout.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-unknown-linux-gnu"
 %test1.struct = type { i32, i32 }
 @test1.aligned_glbl = global %test1.struct zeroinitializer, align 4
 define void @test1(i64 *%ptr) {
-  store i64 and (i64 ptrtoint (i32* getelementptr (%test1.struct* @test1.aligned_glbl, i32 0, i32 1) to i64), i64 3), i64* %ptr
+  store i64 and (i64 ptrtoint (i32* getelementptr (%test1.struct, %test1.struct* @test1.aligned_glbl, i32 0, i32 1) to i64), i64 3), i64* %ptr
 ; CHECK: store i64 0, i64* %ptr
   ret void
 }
diff --git a/test/Transforms/InstCombine/constant-fold-address-space-pointer.ll b/test/Transforms/InstCombine/constant-fold-address-space-pointer.ll
index bb61f02c8e23..0ab76be17cb3 100644
--- a/test/Transforms/InstCombine/constant-fold-address-space-pointer.ll
+++ b/test/Transforms/InstCombine/constant-fold-address-space-pointer.ll
@@ -149,22 +149,22 @@ define i1 @constant_fold_inttoptr() {
 
 define float @constant_fold_bitcast_ftoi_load() {
 ; CHECK-LABEL: @constant_fold_bitcast_ftoi_load(
-; CHECK: load float addrspace(3)* bitcast (i32 addrspace(3)* @g to float addrspace(3)*), align 4
-  %a = load float addrspace(3)* bitcast (i32 addrspace(3)* @g to float addrspace(3)*), align 4
+; CHECK: load float, float addrspace(3)* bitcast (i32 addrspace(3)* @g to float addrspace(3)*), align 4
+  %a = load float, float addrspace(3)* bitcast (i32 addrspace(3)* @g to float addrspace(3)*), align 4
   ret float %a
 }
 
 define i32 @constant_fold_bitcast_itof_load() {
 ; CHECK-LABEL: @constant_fold_bitcast_itof_load(
-; CHECK: load i32 addrspace(3)* bitcast (float addrspace(3)* @g_float_as3 to i32 addrspace(3)*), align 4
-  %a = load i32 addrspace(3)* bitcast (float addrspace(3)* @g_float_as3 to i32 addrspace(3)*), align 4
+; CHECK: load i32, i32 addrspace(3)* bitcast (float addrspace(3)* @g_float_as3 to i32 addrspace(3)*), align 4
+  %a = load i32, i32 addrspace(3)* bitcast (float addrspace(3)* @g_float_as3 to i32 addrspace(3)*), align 4
   ret i32 %a
 }
 
 define <4 x float> @constant_fold_bitcast_vector_as() {
 ; CHECK-LABEL: @constant_fold_bitcast_vector_as(
-; CHECK: load <4 x float> addrspace(3)* @g_v4f_as3, align 16
-  %a = load <4 x float> addrspace(3)* bitcast (<4 x i32> addrspace(3)* bitcast (<4 x float> addrspace(3)* @g_v4f_as3 to <4 x i32> addrspace(3)*) to <4 x float> addrspace(3)*), align 4
+; CHECK: load <4 x float>, <4 x float> addrspace(3)* @g_v4f_as3, align 16
+  %a = load <4 x float>, <4 x float> addrspace(3)* bitcast (<4 x i32> addrspace(3)* bitcast (<4 x float> addrspace(3)* @g_v4f_as3 to <4 x i32> addrspace(3)*) to <4 x float> addrspace(3)*), align 4
   ret <4 x float> %a
 }
 
@@ -172,9 +172,9 @@ define <4 x float> @constant_fold_bitcast_vector_as() {
 
 define i32 @test_cast_gep_small_indices_as() {
 ; CHECK-LABEL: @test_cast_gep_small_indices_as(
-; CHECK: load i32 addrspace(3)* getelementptr inbounds ([10 x i32] addrspace(3)* @i32_array_as3, i16 0, i16 0), align 16
-   %p = getelementptr [10 x i32] addrspace(3)* @i32_array_as3, i7 0, i7 0
-   %x = load i32 addrspace(3)* %p, align 4
+; CHECK: load i32, i32 addrspace(3)* getelementptr inbounds ([10 x i32], [10 x i32] addrspace(3)* @i32_array_as3, i16 0, i16 0), align 16
+   %p = getelementptr [10 x i32], [10 x i32] addrspace(3)* @i32_array_as3, i7 0, i7 0
+   %x = load i32, i32 addrspace(3)* %p, align 4
    ret i32 %x
 }
 
@@ -184,22 +184,22 @@ define i32 @test_cast_gep_small_indices_as() {
   float 0.0,
   float 0.0,
   [4 x i32] zeroinitializer,
-  i32 addrspace(3)* getelementptr ([10 x i32] addrspace(3)* @i32_array_as3, i64 0, i64 0)
+  i32 addrspace(3)* getelementptr ([10 x i32], [10 x i32] addrspace(3)* @i32_array_as3, i64 0, i64 0)
 }
 
 define i32 @test_cast_gep_large_indices_as() {
 ; CHECK-LABEL: @test_cast_gep_large_indices_as(
-; CHECK: load i32 addrspace(3)* getelementptr inbounds ([10 x i32] addrspace(3)* @i32_array_as3, i16 0, i16 0), align 16
-   %p = getelementptr [10 x i32] addrspace(3)* @i32_array_as3, i64 0, i64 0
-   %x = load i32 addrspace(3)* %p, align 4
+; CHECK: load i32, i32 addrspace(3)* getelementptr inbounds ([10 x i32], [10 x i32] addrspace(3)* @i32_array_as3, i16 0, i16 0), align 16
+   %p = getelementptr [10 x i32], [10 x i32] addrspace(3)* @i32_array_as3, i64 0, i64 0
+   %x = load i32, i32 addrspace(3)* %p, align 4
    ret i32 %x
 }
 
 define i32 @test_constant_cast_gep_struct_indices_as() {
 ; CHECK-LABEL: @test_constant_cast_gep_struct_indices_as(
-; CHECK: load i32 addrspace(3)* getelementptr inbounds (%struct.foo addrspace(3)* @constant_fold_global_ptr, i16 0, i32 2, i16 2), align 8
-  %x = getelementptr %struct.foo addrspace(3)* @constant_fold_global_ptr, i18 0, i32 2, i12 2
-  %y = load i32 addrspace(3)* %x, align 4
+; CHECK: load i32, i32 addrspace(3)* getelementptr inbounds (%struct.foo, %struct.foo addrspace(3)* @constant_fold_global_ptr, i16 0, i32 2, i16 2), align 8
+  %x = getelementptr %struct.foo, %struct.foo addrspace(3)* @constant_fold_global_ptr, i18 0, i32 2, i12 2
+  %y = load i32, i32 addrspace(3)* %x, align 4
   ret i32 %y
 }
 
@@ -208,8 +208,8 @@ define i32 @test_constant_cast_gep_struct_indices_as() {
 define i32 @test_read_data_from_global_as3() {
 ; CHECK-LABEL: @test_read_data_from_global_as3(
 ; CHECK-NEXT: ret i32 2
-  %x = getelementptr [5 x i32] addrspace(3)* @constant_data_as3, i32 0, i32 1
-  %y = load i32 addrspace(3)* %x, align 4
+  %x = getelementptr [5 x i32], [5 x i32] addrspace(3)* @constant_data_as3, i32 0, i32 1
+  %y = load i32, i32 addrspace(3)* %x, align 4
   ret i32 %y
 }
 
@@ -219,14 +219,14 @@ define i32 @test_read_data_from_global_as3() {
 @d = addrspace(1) constant i32 99
 
 @ptr_array = addrspace(2) constant [4 x i32 addrspace(1)*] [ i32 addrspace(1)* @a, i32 addrspace(1)* @b, i32 addrspace(1)* @c, i32 addrspace(1)* @d]
-@indirect = addrspace(0) constant i32 addrspace(1)* addrspace(2)* getelementptr inbounds ([4 x i32 addrspace(1)*] addrspace(2)* @ptr_array, i1 0, i32 2)
+@indirect = addrspace(0) constant i32 addrspace(1)* addrspace(2)* getelementptr inbounds ([4 x i32 addrspace(1)*], [4 x i32 addrspace(1)*] addrspace(2)* @ptr_array, i1 0, i32 2)
 
 define i32 @constant_through_array_as_ptrs() {
 ; CHECK-LABEL: @constant_through_array_as_ptrs(
 ; CHECK-NEXT: ret i32 34
-  %p = load i32 addrspace(1)* addrspace(2)* addrspace(0)* @indirect, align 4
-  %a = load i32 addrspace(1)* addrspace(2)* %p, align 4
-  %b = load i32 addrspace(1)* %a, align 4
+  %p = load i32 addrspace(1)* addrspace(2)*, i32 addrspace(1)* addrspace(2)* addrspace(0)* @indirect, align 4
+  %a = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(2)* %p, align 4
+  %b = load i32, i32 addrspace(1)* %a, align 4
   ret i32 %b
 }
 
@@ -234,8 +234,8 @@ define i32 @constant_through_array_as_ptrs() {
 
 define float @canonicalize_addrspacecast(i32 %i) {
 ; CHECK-LABEL: @canonicalize_addrspacecast
-; CHECK-NEXT: getelementptr inbounds float* addrspacecast (float addrspace(3)* bitcast ([0 x i8] addrspace(3)* @shared_mem to float addrspace(3)*) to float*), i32 %i
-  %p = getelementptr inbounds float* addrspacecast ([0 x i8] addrspace(3)* @shared_mem to float*), i32 %i
-  %v = load float* %p
+; CHECK-NEXT: getelementptr inbounds float, float* addrspacecast (float addrspace(3)* bitcast ([0 x i8] addrspace(3)* @shared_mem to float addrspace(3)*) to float*), i32 %i
+  %p = getelementptr inbounds float, float* addrspacecast ([0 x i8] addrspace(3)* @shared_mem to float*), i32 %i
+  %v = load float, float* %p
   ret float %v
 }
diff --git a/test/Transforms/InstCombine/constant-fold-alias.ll b/test/Transforms/InstCombine/constant-fold-alias.ll
index 13da0f445242..c872f57c37e1 100644
--- a/test/Transforms/InstCombine/constant-fold-alias.ll
+++ b/test/Transforms/InstCombine/constant-fold-alias.ll
@@ -6,8 +6,8 @@ target datalayout = "e-p1:16:16-p2:32:32-p3:64:64"
 @G2 = global i32 42
 @G3 = global [4 x i8] zeroinitializer, align 1
 
-@A1 = alias bitcast (i8* getelementptr inbounds ([4 x i8]* @G3, i32 0, i32 2) to i32*)
-@A2 = alias inttoptr (i64 and (i64 ptrtoint (i8* getelementptr inbounds ([4 x i8]* @G3, i32 0, i32 3) to i64), i64 -4) to i32*)
+@A1 = alias bitcast (i8* getelementptr inbounds ([4 x i8], [4 x i8]* @G3, i32 0, i32 2) to i32*)
+@A2 = alias inttoptr (i64 and (i64 ptrtoint (i8* getelementptr inbounds ([4 x i8], [4 x i8]* @G3, i32 0, i32 3) to i64), i64 -4) to i32*)
 
 define i64 @f1() {
 ; This cannot be constant folded because G1 is underaligned.
diff --git a/test/Transforms/InstCombine/constant-fold-gep.ll b/test/Transforms/InstCombine/constant-fold-gep.ll
index 5fb56023a4f6..77090529e130 100644
--- a/test/Transforms/InstCombine/constant-fold-gep.ll
+++ b/test/Transforms/InstCombine/constant-fold-gep.ll
@@ -9,48 +9,48 @@ target datalayout = "E-p:64:64:64-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-
 @Y = internal global [3 x %struct.X] zeroinitializer
 
 define void @frob() {
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 0), align 16
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 0), align 4
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 1), align 4
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 1), align 4
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 2), align 8
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 2), align 4
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 0, i32 1, i64 0), align 4
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 3), align 4
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 0, i32 1, i64 1), align 4
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 4), align 4
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 0, i32 1, i64 2), align 4
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 5), align 4
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 1, i32 0, i64 0), align 8
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 6), align 4
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 1, i32 0, i64 1), align 4
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 7), align 4
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 1, i32 0, i64 2), align 8
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 8), align 4
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 1, i32 1, i64 0), align 4
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 9), align 4
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 1, i32 1, i64 1), align 4
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 10), align 4
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 1, i32 1, i64 2), align 4
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 11), align 4
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 2, i32 0, i64 0), align 16
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 12), align 4
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 2, i32 0, i64 1), align 4
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 13), align 4
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 2, i32 0, i64 2), align 8
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 14), align 8
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 2, i32 1, i64 0), align 8
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 15), align 8
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 2, i32 1, i64 1), align 8
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 16), align 8
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 2, i32 1, i64 2), align 8
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 17), align 8
-; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 1, i64 0, i32 0, i64 0), align 8
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 18), align 8
-; CHECK: store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 2, i64 0, i32 0, i64 0), align 16
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 36), align 8
-; CHECK: store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 1, i64 0, i32 0, i64 1), align 8
-  store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 19), align 8
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 0), align 16
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 0), align 4
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 1), align 4
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 1), align 4
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 2), align 8
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 2), align 4
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 1, i64 0), align 4
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 3), align 4
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 1, i64 1), align 4
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 4), align 4
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 1, i64 2), align 4
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 5), align 4
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 1, i32 0, i64 0), align 8
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 6), align 4
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 1, i32 0, i64 1), align 4
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 7), align 4
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 1, i32 0, i64 2), align 8
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 8), align 4
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 1, i32 1, i64 0), align 4
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 9), align 4
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 1, i32 1, i64 1), align 4
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 10), align 4
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 1, i32 1, i64 2), align 4
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 11), align 4
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 2, i32 0, i64 0), align 16
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 12), align 4
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 2, i32 0, i64 1), align 4
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 13), align 4
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 2, i32 0, i64 2), align 8
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 14), align 8
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 2, i32 1, i64 0), align 8
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 15), align 8
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 2, i32 1, i64 1), align 8
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 16), align 8
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 2, i32 1, i64 2), align 8
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 17), align 8
+; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X], [3 x %struct.X]* @Y, i64 1, i64 0, i32 0, i64 0), align 8
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 18), align 8
+; CHECK: store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 2, i64 0, i32 0, i64 0), align 16
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 36), align 8
+; CHECK: store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 1, i64 0, i32 0, i64 1), align 8
+  store i32 1, i32* getelementptr ([3 x %struct.X], [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 19), align 8
   ret void
 }
 
@@ -61,12 +61,12 @@ define void @frob() {
 
 define i64 @test2() {
 entry:
-  %A = bitcast i8* getelementptr inbounds ([1000 x i8]* @X, i64 1, i64 0) to i8*
-  %B = bitcast i8* getelementptr inbounds ([1000 x i8]* @X, i64 0, i64 0) to i8*
+  %A = bitcast i8* getelementptr inbounds ([1000 x i8], [1000 x i8]* @X, i64 1, i64 0) to i8*
+  %B = bitcast i8* getelementptr inbounds ([1000 x i8], [1000 x i8]* @X, i64 0, i64 0) to i8*
 
   %B2 = ptrtoint i8* %B to i64
   %C = sub i64 0, %B2
-  %D = getelementptr i8* %A, i64 %C
+  %D = getelementptr i8, i8* %A, i64 %C
   %E = ptrtoint i8* %D to i64
 
   ret i64 %E
@@ -80,12 +80,12 @@ define i16 @test2_as1() {
   ; CHECK: ret i16 1000
 
 entry:
-  %A = bitcast i8 addrspace(1)* getelementptr inbounds ([1000 x i8] addrspace(1)* @X_as1, i64 1, i64 0) to i8 addrspace(1)*
-  %B = bitcast i8 addrspace(1)* getelementptr inbounds ([1000 x i8] addrspace(1)* @X_as1, i64 0, i64 0) to i8 addrspace(1)*
+  %A = bitcast i8 addrspace(1)* getelementptr inbounds ([1000 x i8], [1000 x i8] addrspace(1)* @X_as1, i64 1, i64 0) to i8 addrspace(1)*
+  %B = bitcast i8 addrspace(1)* getelementptr inbounds ([1000 x i8], [1000 x i8] addrspace(1)* @X_as1, i64 0, i64 0) to i8 addrspace(1)*
 
   %B2 = ptrtoint i8 addrspace(1)* %B to i16
   %C = sub i16 0, %B2
-  %D = getelementptr i8 addrspace(1)* %A, i16 %C
+  %D = getelementptr i8, i8 addrspace(1)* %A, i16 %C
   %E = ptrtoint i8 addrspace(1)* %D to i16
 
   ret i16 %E
diff --git a/test/Transforms/InstCombine/constant-fold-hang.ll b/test/Transforms/InstCombine/constant-fold-hang.ll
new file mode 100644
index 000000000000..2ca6b86ccc2f
--- /dev/null
+++ b/test/Transforms/InstCombine/constant-fold-hang.ll
@@ -0,0 +1,14 @@
+; RUN: opt -instcombine < %s
+
+; Function Attrs: nounwind readnone ssp
+define void @mulByZero(<4 x i16> %x) #0 {
+entry:
+  %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) #2
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) #1
+
+attributes #0 = { nounwind readnone ssp }
+attributes #1 = { nounwind readnone }
diff --git a/test/Transforms/InstCombine/crash.ll b/test/Transforms/InstCombine/crash.ll
index 2ef6ac64c7f3..2d93ecd59bf5 100644
--- a/test/Transforms/InstCombine/crash.ll
+++ b/test/Transforms/InstCombine/crash.ll
@@ -35,12 +35,12 @@ entry:
 ; PR4908
 define void @test2(<1 x i16>* nocapture %b, i32* nocapture %c) nounwind ssp {
 entry:
-  %arrayidx = getelementptr inbounds <1 x i16>* %b, i64 undef ; <<1 x i16>*>
-  %tmp2 = load <1 x i16>* %arrayidx               ; <<1 x i16>> [#uses=1]
+  %arrayidx = getelementptr inbounds <1 x i16>, <1 x i16>* %b, i64 undef ; <<1 x i16>*>
+  %tmp2 = load <1 x i16>, <1 x i16>* %arrayidx               ; <<1 x i16>> [#uses=1]
   %tmp6 = bitcast <1 x i16> %tmp2 to i16          ; <i16> [#uses=1]
   %tmp7 = zext i16 %tmp6 to i32                   ; <i32> [#uses=1]
   %ins = or i32 0, %tmp7                          ; <i32> [#uses=1]
-  %arrayidx20 = getelementptr inbounds i32* %c, i64 undef ; <i32*> [#uses=1]
+  %arrayidx20 = getelementptr inbounds i32, i32* %c, i64 undef ; <i32*> [#uses=1]
   store i32 %ins, i32* %arrayidx20
   ret void
 }
@@ -60,7 +60,7 @@ define void @foo(i1) nounwind align 2 {
 ; <label>:3                                       ; preds = %2, %1
   %4 = phi i8 [ 1, %2 ], [ 0, %1 ]                ; <i8> [#uses=1]
   %5 = icmp eq i8 %4, 0                           ; <i1> [#uses=1]
-  %6 = load i64* @tmp2, align 8                   ; <i64> [#uses=1]
+  %6 = load i64, i64* @tmp2, align 8                   ; <i64> [#uses=1]
   %7 = select i1 %5, i64 0, i64 %6                ; <i64> [#uses=1]
   br label %8
 
@@ -79,9 +79,9 @@ define void @bar3(i1, i1) nounwind align 2 {
   br i1 %1, label %10, label %3
 
 ; <label>:3                                       ; preds = %2
-  %4 = getelementptr inbounds %t0* null, i64 0, i32 1 ; <i32*> [#uses=0]
-  %5 = getelementptr inbounds %t1* null, i64 0, i32 4 ; <i32**> [#uses=1]
-  %6 = load i32** %5, align 8                     ; <i32*> [#uses=1]
+  %4 = getelementptr inbounds %t0, %t0* null, i64 0, i32 1 ; <i32*> [#uses=0]
+  %5 = getelementptr inbounds %t1, %t1* null, i64 0, i32 4 ; <i32**> [#uses=1]
+  %6 = load i32*, i32** %5, align 8                     ; <i32*> [#uses=1]
   %7 = icmp ne i32* %6, null                      ; <i1> [#uses=1]
   %8 = zext i1 %7 to i32                          ; <i32> [#uses=1]
   %9 = add i32 %8, 0                              ; <i32> [#uses=1]
@@ -115,7 +115,7 @@ BB1:
 
 BB2:
   %v5_ = phi i1 [ true, %BB0], [false, %BB1]
-  %v6 = load i64* %P
+  %v6 = load i64, i64* %P
   br label %l8
 
 l8:
@@ -149,7 +149,7 @@ exit:
 
 define arm_aapcs_vfpcc i32 @test6(i32 %argc, i8** %argv) nounwind {
 entry:
-  store i32* getelementptr (i32* bitcast (i32 (i32, i8**)* @test6 to i32*), i32 -2048), i32** @test6g, align 4
+  store i32* getelementptr (i32, i32* bitcast (i32 (i32, i8**)* @test6 to i32*), i32 -2048), i32** @test6g, align 4
   unreachable
 }
 
@@ -182,8 +182,8 @@ cont:                                             ; preds = %ehcleanup
   resume { i8*, i32 } %exc1
 
 cond.false:                                       ; preds = %entry
-  %tmp4 = getelementptr inbounds %class.RuleBasedBreakIterator* %this, i32 0, i32 0 ; <i64 ()**> [#uses=1]
-  %tmp5 = load i64 ()** %tmp4                     ; <i64 ()*> [#uses=1]
+  %tmp4 = getelementptr inbounds %class.RuleBasedBreakIterator, %class.RuleBasedBreakIterator* %this, i32 0, i32 0 ; <i64 ()**> [#uses=1]
+  %tmp5 = load i64 ()*, i64 ()** %tmp4                     ; <i64 ()*> [#uses=1]
   %call = invoke i64 %tmp5()
           to label %cond.end unwind label %ehcleanup ; <i64> [#uses=1]
 
@@ -242,10 +242,10 @@ entry:
 ; PR6503
 define void @test12(i32* %A) nounwind {
 entry:
-  %tmp1 = load i32* %A
+  %tmp1 = load i32, i32* %A
   %cmp = icmp ugt i32 1, %tmp1                    ; <i1> [#uses=1]
   %conv = zext i1 %cmp to i32                     ; <i32> [#uses=1]
-  %tmp2 = load i32* %A
+  %tmp2 = load i32, i32* %A
   %cmp3 = icmp ne i32 %tmp2, 0                    ; <i1> [#uses=1]
   %conv4 = zext i1 %cmp3 to i32                   ; <i32> [#uses=1]
   %or = or i32 %conv, %conv4                      ; <i32> [#uses=1]
@@ -258,10 +258,10 @@ entry:
 %s2 = type { i64 }
 define void @test13() nounwind ssp {
 entry:
-  %0 = getelementptr inbounds %s1* null, i64 0, i32 2, i64 0, i32 0
+  %0 = getelementptr inbounds %s1, %s1* null, i64 0, i32 2, i64 0, i32 0
   %1 = bitcast i64* %0 to i32*
-  %2 = getelementptr inbounds %s1* null, i64 0, i32 2, i64 1, i32 0
-  %.pre = load i32* %1, align 8
+  %2 = getelementptr inbounds %s1, %s1* null, i64 0, i32 2, i64 1, i32 0
+  %.pre = load i32, i32* %1, align 8
   %3 = lshr i32 %.pre, 19
   %brmerge = or i1 undef, undef
   %4 = and i32 %3, 3
@@ -269,7 +269,7 @@ entry:
   %6 = shl i32 %5, 19
   %7 = add i32 %6, 1572864
   %8 = and i32 %7, 1572864
-  %9 = load i64* %2, align 8
+  %9 = load i64, i64* %2, align 8
   %trunc156 = trunc i64 %9 to i32
   %10 = and i32 %trunc156, -1537
   %11 = and i32 %10, -6145
@@ -304,7 +304,7 @@ entry:
 
 define void @test15(i32* %p_92) nounwind {
 entry:
-%0 = load i32* %p_92, align 4
+%0 = load i32, i32* %p_92, align 4
 %1 = icmp ne i32 %0, 0
 %2 = zext i1 %1 to i32
 %3 = call i32 @func_14() nounwind
@@ -349,7 +349,7 @@ define double @test16(i32 %a) nounwind {
 
 define %struct.basic_ios *@test17() ssp {
 entry:
-  %add.ptr.i = getelementptr i8* null, i64 undef
+  %add.ptr.i = getelementptr i8, i8* null, i64 undef
   %0 = bitcast i8* %add.ptr.i to %struct.basic_ios*
   ret %struct.basic_ios* %0
 }
diff --git a/test/Transforms/InstCombine/debug-line.ll b/test/Transforms/InstCombine/debug-line.ll
index 1946576183c4..823ec98ebe2b 100644
--- a/test/Transforms/InstCombine/debug-line.ll
+++ b/test/Transforms/InstCombine/debug-line.ll
@@ -5,7 +5,7 @@
 
 define void @foo() nounwind ssp {
 ;CHECK: call i32 @putchar{{.+}} !dbg
-  %1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i32 97), !dbg !5
+  %1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i32 97), !dbg !5
   ret void, !dbg !7
 }
 
@@ -15,14 +15,14 @@ declare i32 @printf(i8*, ...)
 !llvm.module.flags = !{!10}
 !llvm.dbg.sp = !{!0}
 
-!0 = !{!"0x2e\00foo\00foo\00\004\000\001\000\006\000\000\000", !8, !1, !3, null, void ()* @foo, null, null, null} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !8} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang\001\00\000\00\000", !8, !4, !4, !9, null, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !8, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "foo", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !8, scope: !1, type: !3, function: void ()* @foo)
+!1 = !DIFile(filename: "m.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang", isOptimized: true, emissionKind: 0, file: !8, enums: !{}, retainedTypes: !{}, subprograms: !9)
+!3 = !DISubroutineType(types: !4)
 !4 = !{null}
-!5 = !MDLocation(line: 5, column: 2, scope: !6)
-!6 = !{!"0xb\004\0012\000", !8, !0} ; [ DW_TAG_lexical_block ]
-!7 = !MDLocation(line: 6, column: 1, scope: !6)
-!8 = !{!"m.c", !"/private/tmp"}
+!5 = !DILocation(line: 5, column: 2, scope: !6)
+!6 = distinct !DILexicalBlock(line: 4, column: 12, file: !8, scope: !0)
+!7 = !DILocation(line: 6, column: 1, scope: !6)
+!8 = !DIFile(filename: "m.c", directory: "/private/tmp")
 !9 = !{!0}
-!10 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/InstCombine/debuginfo.ll b/test/Transforms/InstCombine/debuginfo.ll
index ae72f700039e..3875bcc9b8c6 100644
--- a/test/Transforms/InstCombine/debuginfo.ll
+++ b/test/Transforms/InstCombine/debuginfo.ll
@@ -14,15 +14,15 @@ entry:
   store i8* %__dest, i8** %__dest.addr, align 8
 ; CHECK-NOT: call void @llvm.dbg.declare
 ; CHECK: call void @llvm.dbg.value
-  call void @llvm.dbg.declare(metadata i8** %__dest.addr, metadata !0, metadata !{}), !dbg !16
+  call void @llvm.dbg.declare(metadata i8** %__dest.addr, metadata !0, metadata !DIExpression()), !dbg !16
   store i32 %__val, i32* %__val.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %__val.addr, metadata !7, metadata !{}), !dbg !18
+  call void @llvm.dbg.declare(metadata i32* %__val.addr, metadata !7, metadata !DIExpression()), !dbg !18
   store i64 %__len, i64* %__len.addr, align 8
-  call void @llvm.dbg.declare(metadata i64* %__len.addr, metadata !9, metadata !{}), !dbg !20
-  %tmp = load i8** %__dest.addr, align 8, !dbg !21
-  %tmp1 = load i32* %__val.addr, align 4, !dbg !21
-  %tmp2 = load i64* %__len.addr, align 8, !dbg !21
-  %tmp3 = load i8** %__dest.addr, align 8, !dbg !21
+  call void @llvm.dbg.declare(metadata i64* %__len.addr, metadata !9, metadata !DIExpression()), !dbg !20
+  %tmp = load i8*, i8** %__dest.addr, align 8, !dbg !21
+  %tmp1 = load i32, i32* %__val.addr, align 4, !dbg !21
+  %tmp2 = load i64, i64* %__len.addr, align 8, !dbg !21
+  %tmp3 = load i8*, i8** %__dest.addr, align 8, !dbg !21
   %0 = call i64 @llvm.objectsize.i64.p0i8(i8* %tmp3, i1 false), !dbg !21
   %call = call i8* @foo(i8* %tmp, i32 %tmp1, i64 %tmp2, i64 %0), !dbg !21
   ret i8* %call, !dbg !21
@@ -31,29 +31,29 @@ entry:
 !llvm.dbg.cu = !{!3}
 !llvm.module.flags = !{!30}
 
-!0 = !{!"0x101\00__dest\0016777294\000", !1, !2, !6} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00foobar\00foobar\00\0079\001\001\000\006\00256\001\0079", !27, !2, !4, null, i8* (i8*, i32, i64)* @foobar, null, null, !25} ; [ DW_TAG_subprogram ] [line 79] [local] [def] [foobar]
-!2 = !{!"0x29", !27} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\0012\00clang version 3.0 (trunk 127710)\001\00\000\00\000", !28, !29, !29, !24, null, null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !27, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "__dest", line: 78, arg: 1, scope: !1, file: !2, type: !6)
+!1 = !DISubprogram(name: "foobar", line: 79, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 79, file: !27, scope: !2, type: !4, function: i8* (i8*, i32, i64)* @foobar, variables: !25)
+!2 = !DIFile(filename: "string.h", directory: "Game")
+!3 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 127710)", isOptimized: true, emissionKind: 0, file: !28, enums: !29, retainedTypes: !29, subprograms: !24)
+!4 = !DISubroutineType(types: !5)
 !5 = !{!6}
-!6 = !{!"0xf\00\000\0064\0064\000\000", null, !3, null} ; [ DW_TAG_pointer_type ]
-!7 = !{!"0x101\00__val\0033554510\000", !1, !2, !8} ; [ DW_TAG_arg_variable ]
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !3} ; [ DW_TAG_base_type ]
-!9 = !{!"0x101\00__len\0050331726\000", !1, !2, !10} ; [ DW_TAG_arg_variable ]
-!10 = !{!"0x16\00size_t\0080\000\000\000\000", !27, !3, !11} ; [ DW_TAG_typedef ]
-!11 = !{!"0x16\00__darwin_size_t\0090\000\000\000\000", !27, !3, !12} ; [ DW_TAG_typedef ]
-!12 = !{!"0x24\00long unsigned int\000\0064\0064\000\000\007", null, !3} ; [ DW_TAG_base_type ]
-!16 = !MDLocation(line: 78, column: 28, scope: !1)
-!18 = !MDLocation(line: 78, column: 40, scope: !1)
-!20 = !MDLocation(line: 78, column: 54, scope: !1)
-!21 = !MDLocation(line: 80, column: 3, scope: !22)
-!22 = !{!"0xb\0080\003\007", !27, !23} ; [ DW_TAG_lexical_block ]
-!23 = !{!"0xb\0079\001\006", !27, !1} ; [ DW_TAG_lexical_block ]
+!6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, scope: !3, baseType: null)
+!7 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "__val", line: 78, arg: 2, scope: !1, file: !2, type: !8)
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "__len", line: 78, arg: 3, scope: !1, file: !2, type: !10)
+!10 = !DIDerivedType(tag: DW_TAG_typedef, name: "size_t", line: 80, file: !27, scope: !3, baseType: !11)
+!11 = !DIDerivedType(tag: DW_TAG_typedef, name: "__darwin_size_t", line: 90, file: !27, scope: !3, baseType: !12)
+!12 = !DIBasicType(tag: DW_TAG_base_type, name: "long unsigned int", size: 64, align: 64, encoding: DW_ATE_unsigned)
+!16 = !DILocation(line: 78, column: 28, scope: !1)
+!18 = !DILocation(line: 78, column: 40, scope: !1)
+!20 = !DILocation(line: 78, column: 54, scope: !1)
+!21 = !DILocation(line: 80, column: 3, scope: !22)
+!22 = distinct !DILexicalBlock(line: 80, column: 3, file: !27, scope: !23)
+!23 = distinct !DILexicalBlock(line: 79, column: 1, file: !27, scope: !1)
 !24 = !{!1}
 !25 = !{!0, !7, !9}
-!26 = !{!"0x29", !28} ; [ DW_TAG_file_type ]
-!27 = !{!"string.h", !"Game"}
-!28 = !{!"bits.c", !"Game"}
-!29 = !{i32 0}
-!30 = !{i32 1, !"Debug Info Version", i32 2}
+!26 = !DIFile(filename: "bits.c", directory: "Game")
+!27 = !DIFile(filename: "string.h", directory: "Game")
+!28 = !DIFile(filename: "bits.c", directory: "Game")
+!29 = !{}
+!30 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/InstCombine/default-alignment.ll b/test/Transforms/InstCombine/default-alignment.ll
new file mode 100644
index 000000000000..718da2136717
--- /dev/null
+++ b/test/Transforms/InstCombine/default-alignment.ll
@@ -0,0 +1,10 @@
+; RUN: opt -verify -instcombine < %s
+%Foo = type <{ i8, x86_fp80 }>
+
+define i8 @t(%Foo* %arg) {
+entry:
+  %0 = getelementptr %Foo, %Foo* %arg, i32 0, i32 0
+  %1 = load i8, i8* %0, align 1
+  ret i8 %1
+}
+
diff --git a/test/Transforms/InstCombine/demand_shrink_nsw.ll b/test/Transforms/InstCombine/demand_shrink_nsw.ll
new file mode 100644
index 000000000000..f49174295167
--- /dev/null
+++ b/test/Transforms/InstCombine/demand_shrink_nsw.ll
@@ -0,0 +1,26 @@
+; RUN: opt -instcombine -o - -S %s | FileCheck %s
+
+; The constant at %v35 should be shrunk, but this must lead to the nsw flag of
+; %v43 getting removed so that %v44 is not illegally optimized away.
+; CHECK-LABEL: @foo
+; CHECK: %v35 = add nuw i32 %v34, 1362915575
+; ...
+; CHECK: add nuw i32 %v42, 1533579450
+; CHECK-NEXT: %v44 = or i32 %v43, -2147483648
+; CHECK-NEXT: %v45 = xor i32 %v44, 749011377
+; CHECK-NEXT: ret i32 %v45
+define i32 @foo(i32 %arg) {
+  %v33 = and i32 %arg, 223
+  %v34 = xor i32 %v33, 29
+  %v35 = add nuw i32 %v34, 3510399223
+  %v37 = or i32 %v34, 1874836915
+  %v38 = and i32 %v34, 221
+  %v39 = xor i32 %v38, 1874836915
+  %v40 = xor i32 %v37, %v39
+  %v41 = shl nsw nuw i32 %v40, 1
+  %v42 = sub i32 %v35, %v41
+  %v43 = add nsw i32 %v42, 1533579450
+  %v44 = or i32 %v43, -2147483648
+  %v45 = xor i32 %v44, 749011377
+  ret i32 %v45
+}
diff --git a/test/Transforms/InstCombine/descale-zero.ll b/test/Transforms/InstCombine/descale-zero.ll
deleted file mode 100644
index 4656837cc05e..000000000000
--- a/test/Transforms/InstCombine/descale-zero.ll
+++ /dev/null
@@ -1,20 +0,0 @@
-; RUN: opt < %s -instcombine -S | FileCheck %s
-
-target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
-target triple = "x86_64-apple-macosx10.10.0"
-
-define internal i8* @descale_zero() {
-entry:
-; CHECK: load i8** inttoptr (i64 48 to i8**), align 16
-; CHECK-NEXT: ret i8*
-  %i16_ptr = load i16** inttoptr (i64 48 to i16**), align 16
-  %num = load i64* inttoptr (i64 64 to i64*), align 64
-  %num_times_2 = shl i64 %num, 1
-  %num_times_2_plus_4 = add i64 %num_times_2, 4
-  %i8_ptr = bitcast i16* %i16_ptr to i8*
-  %i8_ptr_num_times_2_plus_4 = getelementptr i8* %i8_ptr, i64 %num_times_2_plus_4
-  %num_times_neg2 = mul i64 %num, -2
-  %num_times_neg2_minus_4 = add i64 %num_times_neg2, -4
-  %addr = getelementptr i8* %i8_ptr_num_times_2_plus_4, i64 %num_times_neg2_minus_4
-  ret i8* %addr
-}
diff --git a/test/Transforms/InstCombine/disable-simplify-libcalls.ll b/test/Transforms/InstCombine/disable-simplify-libcalls.ll
index 665278861791..e25ce31cbfbf 100644
--- a/test/Transforms/InstCombine/disable-simplify-libcalls.ll
+++ b/test/Transforms/InstCombine/disable-simplify-libcalls.ll
@@ -87,7 +87,7 @@ define double @t5(double %x) {
 
 define i8* @t6(i8* %x) {
 ; CHECK-LABEL: @t6(
-  %empty = getelementptr [1 x i8]* @empty, i32 0, i32 0
+  %empty = getelementptr [1 x i8], [1 x i8]* @empty, i32 0, i32 0
   %ret = call i8* @strcat(i8* %x, i8* %empty)
   ret i8* %ret
 ; CHECK: call i8* @strcat
@@ -95,7 +95,7 @@ define i8* @t6(i8* %x) {
 
 define i8* @t7(i8* %x) {
 ; CHECK-LABEL: @t7(
-  %empty = getelementptr [1 x i8]* @empty, i32 0, i32 0
+  %empty = getelementptr [1 x i8], [1 x i8]* @empty, i32 0, i32 0
   %ret = call i8* @strncat(i8* %x, i8* %empty, i32 1)
   ret i8* %ret
 ; CHECK: call i8* @strncat
@@ -103,7 +103,7 @@ define i8* @t7(i8* %x) {
 
 define i8* @t8() {
 ; CHECK-LABEL: @t8(
-  %x = getelementptr inbounds [13 x i8]* @.str1, i32 0, i32 0
+  %x = getelementptr inbounds [13 x i8], [13 x i8]* @.str1, i32 0, i32 0
   %ret = call i8* @strchr(i8* %x, i32 119)
   ret i8* %ret
 ; CHECK: call i8* @strchr
@@ -111,7 +111,7 @@ define i8* @t8() {
 
 define i8* @t9() {
 ; CHECK-LABEL: @t9(
-  %x = getelementptr inbounds [13 x i8]* @.str1, i32 0, i32 0
+  %x = getelementptr inbounds [13 x i8], [13 x i8]* @.str1, i32 0, i32 0
   %ret = call i8* @strrchr(i8* %x, i32 119)
   ret i8* %ret
 ; CHECK: call i8* @strrchr
@@ -119,8 +119,8 @@ define i8* @t9() {
 
 define i32 @t10() {
 ; CHECK-LABEL: @t10(
-  %x = getelementptr inbounds [4 x i8]* @.str2, i32 0, i32 0
-  %y = getelementptr inbounds [4 x i8]* @.str3, i32 0, i32 0
+  %x = getelementptr inbounds [4 x i8], [4 x i8]* @.str2, i32 0, i32 0
+  %y = getelementptr inbounds [4 x i8], [4 x i8]* @.str3, i32 0, i32 0
   %ret = call i32 @strcmp(i8* %x, i8* %y)
   ret i32 %ret
 ; CHECK: call i32 @strcmp
@@ -128,8 +128,8 @@ define i32 @t10() {
 
 define i32 @t11() {
 ; CHECK-LABEL: @t11(
-  %x = getelementptr inbounds [4 x i8]* @.str2, i32 0, i32 0
-  %y = getelementptr inbounds [4 x i8]* @.str3, i32 0, i32 0
+  %x = getelementptr inbounds [4 x i8], [4 x i8]* @.str2, i32 0, i32 0
+  %y = getelementptr inbounds [4 x i8], [4 x i8]* @.str3, i32 0, i32 0
   %ret = call i32 @strncmp(i8* %x, i8* %y, i64 3)
   ret i32 %ret
 ; CHECK: call i32 @strncmp
@@ -137,7 +137,7 @@ define i32 @t11() {
 
 define i8* @t12(i8* %x) {
 ; CHECK-LABEL: @t12(
-  %y = getelementptr inbounds [4 x i8]* @.str2, i32 0, i32 0
+  %y = getelementptr inbounds [4 x i8], [4 x i8]* @.str2, i32 0, i32 0
   %ret = call i8* @strcpy(i8* %x, i8* %y)
   ret i8* %ret
 ; CHECK: call i8* @strcpy
@@ -145,7 +145,7 @@ define i8* @t12(i8* %x) {
 
 define i8* @t13(i8* %x) {
 ; CHECK-LABEL: @t13(
-  %y = getelementptr inbounds [4 x i8]* @.str2, i32 0, i32 0
+  %y = getelementptr inbounds [4 x i8], [4 x i8]* @.str2, i32 0, i32 0
   %ret = call i8* @stpcpy(i8* %x, i8* %y)
   ret i8* %ret
 ; CHECK: call i8* @stpcpy
@@ -153,7 +153,7 @@ define i8* @t13(i8* %x) {
 
 define i8* @t14(i8* %x) {
 ; CHECK-LABEL: @t14(
-  %y = getelementptr inbounds [4 x i8]* @.str2, i32 0, i32 0
+  %y = getelementptr inbounds [4 x i8], [4 x i8]* @.str2, i32 0, i32 0
   %ret = call i8* @strncpy(i8* %x, i8* %y, i64 3)
   ret i8* %ret
 ; CHECK: call i8* @strncpy
@@ -161,7 +161,7 @@ define i8* @t14(i8* %x) {
 
 define i64 @t15() {
 ; CHECK-LABEL: @t15(
-  %x = getelementptr inbounds [4 x i8]* @.str2, i32 0, i32 0
+  %x = getelementptr inbounds [4 x i8], [4 x i8]* @.str2, i32 0, i32 0
   %ret = call i64 @strlen(i8* %x)
   ret i64 %ret
 ; CHECK: call i64 @strlen
@@ -169,7 +169,7 @@ define i64 @t15() {
 
 define i8* @t16(i8* %x) {
 ; CHECK-LABEL: @t16(
-  %y = getelementptr inbounds [1 x i8]* @.str, i32 0, i32 0
+  %y = getelementptr inbounds [1 x i8], [1 x i8]* @.str, i32 0, i32 0
   %ret = call i8* @strpbrk(i8* %x, i8* %y)
   ret i8* %ret
 ; CHECK: call i8* @strpbrk
@@ -177,7 +177,7 @@ define i8* @t16(i8* %x) {
 
 define i64 @t17(i8* %x) {
 ; CHECK-LABEL: @t17(
-  %y = getelementptr inbounds [1 x i8]* @.str, i32 0, i32 0
+  %y = getelementptr inbounds [1 x i8], [1 x i8]* @.str, i32 0, i32 0
   %ret = call i64 @strspn(i8* %x, i8* %y)
   ret i64 %ret
 ; CHECK: call i64 @strspn
@@ -185,7 +185,7 @@ define i64 @t17(i8* %x) {
 
 define double @t18(i8** %y) {
 ; CHECK-LABEL: @t18(
-  %x = getelementptr inbounds [6 x i8]* @.str4, i64 0, i64 0
+  %x = getelementptr inbounds [6 x i8], [6 x i8]* @.str4, i64 0, i64 0
   %ret = call double @strtod(i8* %x, i8** %y)
   ret double %ret
 ; CHECK: call double @strtod
@@ -193,7 +193,7 @@ define double @t18(i8** %y) {
 
 define float @t19(i8** %y) {
 ; CHECK-LABEL: @t19(
-  %x = getelementptr inbounds [6 x i8]* @.str4, i64 0, i64 0
+  %x = getelementptr inbounds [6 x i8], [6 x i8]* @.str4, i64 0, i64 0
   %ret = call float @strtof(i8* %x, i8** %y)
   ret float %ret
 ; CHECK: call float @strtof
@@ -201,7 +201,7 @@ define float @t19(i8** %y) {
 
 define x86_fp80 @t20(i8** %y) {
 ; CHECK-LABEL: @t20(
-  %x = getelementptr inbounds [6 x i8]* @.str4, i64 0, i64 0
+  %x = getelementptr inbounds [6 x i8], [6 x i8]* @.str4, i64 0, i64 0
   %ret = call x86_fp80 @strtold(i8* %x, i8** %y)
   ret x86_fp80 %ret
 ; CHECK: call x86_fp80 @strtold
@@ -209,7 +209,7 @@ define x86_fp80 @t20(i8** %y) {
 
 define i64 @t21(i8** %y) {
 ; CHECK-LABEL: @t21(
-  %x = getelementptr inbounds [5 x i8]* @.str5, i64 0, i64 0
+  %x = getelementptr inbounds [5 x i8], [5 x i8]* @.str5, i64 0, i64 0
   %ret = call i64 @strtol(i8* %x, i8** %y, i32 10)
   ret i64 %ret
 ; CHECK: call i64 @strtol
@@ -217,7 +217,7 @@ define i64 @t21(i8** %y) {
 
 define i64 @t22(i8** %y) {
 ; CHECK-LABEL: @t22(
-  %x = getelementptr inbounds [5 x i8]* @.str5, i64 0, i64 0
+  %x = getelementptr inbounds [5 x i8], [5 x i8]* @.str5, i64 0, i64 0
   %ret = call i64 @strtoll(i8* %x, i8** %y, i32 10)
   ret i64 %ret
 ; CHECK: call i64 @strtoll
@@ -225,7 +225,7 @@ define i64 @t22(i8** %y) {
 
 define i64 @t23(i8** %y) {
 ; CHECK-LABEL: @t23(
-  %x = getelementptr inbounds [5 x i8]* @.str5, i64 0, i64 0
+  %x = getelementptr inbounds [5 x i8], [5 x i8]* @.str5, i64 0, i64 0
   %ret = call i64 @strtoul(i8* %x, i8** %y, i32 10)
   ret i64 %ret
 ; CHECK: call i64 @strtoul
@@ -233,7 +233,7 @@ define i64 @t23(i8** %y) {
 
 define i64 @t24(i8** %y) {
 ; CHECK-LABEL: @t24(
-  %x = getelementptr inbounds [5 x i8]* @.str5, i64 0, i64 0
+  %x = getelementptr inbounds [5 x i8], [5 x i8]* @.str5, i64 0, i64 0
   %ret = call i64 @strtoull(i8* %x, i8** %y, i32 10)
   ret i64 %ret
 ; CHECK: call i64 @strtoull
@@ -241,7 +241,7 @@ define i64 @t24(i8** %y) {
 
 define i64 @t25(i8* %y) {
 ; CHECK-LABEL: @t25(
-  %x = getelementptr [1 x i8]* @empty, i32 0, i32 0
+  %x = getelementptr [1 x i8], [1 x i8]* @empty, i32 0, i32 0
   %ret = call i64 @strcspn(i8* %x, i8* %y)
   ret i64 %ret
 ; CHECK: call i64 @strcspn
@@ -277,7 +277,7 @@ define i32 @t29(i64 %y) {
 
 define void @t30() {
 ; CHECK-LABEL: @t30(
-  %x = getelementptr inbounds [13 x i8]* @.str1, i32 0, i32 0
+  %x = getelementptr inbounds [13 x i8], [13 x i8]* @.str1, i32 0, i32 0
   call i32 @fprintf(i8* null, i8* %x)
   ret void
 ; CHECK: call i32 @fprintf
@@ -320,7 +320,7 @@ define i64 @t35(i64 %y) {
 
 define void @t36() {
 ; CHECK-LABEL: @t36(
-  %x = getelementptr inbounds [1 x i8]* @empty, i32 0, i32 0
+  %x = getelementptr inbounds [1 x i8], [1 x i8]* @empty, i32 0, i32 0
   call i32 @printf(i8* %x)
   ret void
 ; CHECK: call i32 @printf
@@ -328,7 +328,7 @@ define void @t36() {
 
 define void @t37(i8* %x) {
 ; CHECK-LABEL: @t37(
-  %y = getelementptr inbounds [13 x i8]* @.str1, i32 0, i32 0
+  %y = getelementptr inbounds [13 x i8], [13 x i8]* @.str1, i32 0, i32 0
   call i32 @sprintf(i8* %x, i8* %y)
   ret void
 ; CHECK: call i32 @sprintf
diff --git a/test/Transforms/InstCombine/div-shift-crash.ll b/test/Transforms/InstCombine/div-shift-crash.ll
index a61972456403..936173cd6d48 100644
--- a/test/Transforms/InstCombine/div-shift-crash.ll
+++ b/test/Transforms/InstCombine/div-shift-crash.ll
@@ -14,7 +14,7 @@ land.lhs.true:                                    ; preds = %entry
   br label %for.cond.i
 
 for.cond.i:                                       ; preds = %land.lhs.true, %entry
-  %0 = getelementptr inbounds %struct.S0.0.1.2.3.4.13.22.31.44.48.53.54.55.56.58.59.60.66.68.70.74.77.106.107.108.109.110.113.117.118.128.129* %l_819.i.i, i64 0, i32 0
+  %0 = getelementptr inbounds %struct.S0.0.1.2.3.4.13.22.31.44.48.53.54.55.56.58.59.60.66.68.70.74.77.106.107.108.109.110.113.117.118.128.129, %struct.S0.0.1.2.3.4.13.22.31.44.48.53.54.55.56.58.59.60.66.68.70.74.77.106.107.108.109.110.113.117.118.128.129* %l_819.i.i, i64 0, i32 0
   br label %for.cond.i6.i.i
 
 for.cond.i6.i.i:                                  ; preds = %for.body.i8.i.i, %for.cond.i
@@ -39,7 +39,7 @@ for.body4.i.i.i.i:                                ; preds = %for.cond1.i.i.i.i
   br label %for.cond1.i.i.i.i
 
 func_39.exit.i.i:                                 ; preds = %for.cond1.i.i.i.i
-  %l_8191.sroa.0.0.copyload.i.i = load i64* %0, align 1
+  %l_8191.sroa.0.0.copyload.i.i = load i64, i64* %0, align 1
   br label %for.cond1.i.i.i
 
 for.cond1.i.i.i:                                  ; preds = %safe_div_func_uint32_t_u_u.exit.i.i.i, %func_39.exit.i.i
diff --git a/test/Transforms/InstCombine/dom-conditions.ll b/test/Transforms/InstCombine/dom-conditions.ll
new file mode 100644
index 000000000000..426404352681
--- /dev/null
+++ b/test/Transforms/InstCombine/dom-conditions.ll
@@ -0,0 +1,152 @@
+; RUN: opt -instcombine -value-tracking-dom-conditions=1 -S < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-p1:16:16:16-p2:32:32:32-p3:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+
+define i1 @test_cmp_ult(i64 %A) {
+; CHECK-LABEL: @test_cmp_ult
+entry:
+  %cmp = icmp ult i64 %A, 64
+  br i1 %cmp, label %taken, label %untaken
+
+taken:
+; CHECK-LABEL: taken:
+; CHECK-NEXT: ret i1 false
+  %cmp2 = icmp ugt i64 %A, 64
+  ret i1 %cmp2
+untaken:
+  ret i1 true
+}
+
+define i1 @test_cmp_ule(i64 %A) {
+; CHECK-LABEL: @test_cmp_ule
+entry:
+  %cmp = icmp ule i64 %A, 64
+  br i1 %cmp, label %taken, label %untaken
+
+taken:
+; CHECK-LABEL: taken:
+; CHECK-NEXT: ret i1 false
+  %cmp2 = icmp ugt i64 %A, 128
+  ret i1 %cmp2
+untaken:
+  ret i1 true
+}
+
+define i1 @test_cmp_sgt(i32 %A) {
+; CHECK-LABEL: @test_cmp_sgt
+entry:
+  %cmp = icmp sgt i32 %A, 10
+  br i1 %cmp, label %taken, label %untaken
+
+taken:
+; CHECK-LABEL: taken:
+; CHECK-NEXT: ret i1 true
+  %cmp2 = icmp sgt i32 %A, -1
+  ret i1 %cmp2
+untaken:
+  ret i1 true
+}
+
+define i64 @test_add_zero_bits(i64 %A) {
+; CHECK-LABEL: @test_add_zero_bits
+entry:
+  %cmp = icmp eq i64 %A, 2
+  br i1 %cmp, label %taken, label %untaken
+
+taken:
+; CHECK-LABEL: taken:
+; CHECK-NEXT: ret i64 3
+  %add = add i64 %A, 1
+  ret i64 %add
+untaken:
+  ret i64 %A
+}
+
+define i64 @test_add_nsw(i64 %A) {
+; CHECK-LABEL: @test_add_nsw
+entry:
+  %cmp = icmp ult i64 %A, 20
+  br i1 %cmp, label %taken, label %untaken
+
+taken:
+; CHECK-LABEL: taken:
+; CHECK-NEXT: %add = add nuw nsw i64 %A, 1
+; CHECK-NEXT: ret i64 %add
+  %add = add i64 %A, 1
+  ret i64 %add
+untaken:
+  ret i64 %A
+}
+
+; After sinking the instructions into the if block, check that we 
+; can simplify some of them using dominating conditions.
+define i32 @test_add_zero_bits_sink(i32 %x) nounwind ssp {
+; CHECK-LABEL: @test_add_zero_bits_sink(
+; CHECK-NOT: sdiv i32
+entry:
+  %a = add nsw i32 %x, 16
+  %b = sdiv i32 %a, %x
+  %cmp = icmp ult i32 %x, 7
+  br i1 %cmp, label %bb1, label %bb2
+
+bb1:
+; CHECK-LABEL: bb1:
+; CHECK-NEXT: or i32 %x, 16
+; CHECK-NEXT: udiv i32
+  ret i32 %b
+
+bb2:
+  ret i32 %x
+}
+
+; A condition in the same block gives no information
+define i32 @test_neg1(i32 %x) nounwind ssp {
+; CHECK-LABEL: @test_neg1
+; CHECK: add
+; CHECK: sdiv
+; CHECK: icmp
+; CHECK: select
+entry:
+  %a = add nsw i32 %x, 16
+  %b = sdiv i32 %a, %x
+  %cmp = icmp ult i32 %x, 7
+  %ret = select i1 %cmp, i32 %a, i32 %b
+  ret i32 %ret
+}
+
+; A non-dominating edge gives no information 
+define i32 @test_neg2(i32 %x) {
+; CHECK-LABEL: @test_neg2
+entry:
+  %cmp = icmp ult i32 %x, 7
+  br i1 %cmp, label %bb1, label %merge
+
+bb1:
+  br label %merge
+
+merge:
+; CHECK-LABEL: merge:
+; CHECK: icmp
+; CHECK: select
+  %cmp2 = icmp ult i32 %x, 7
+  %ret = select i1 %cmp2, i32 %x, i32 0
+  ret i32 %ret
+}
+
+; A unconditional branch expressed as a condition one gives no
+; information (and shouldn't trip any asserts.)
+define i32 @test_neg3(i32 %x) {
+; CHECK-LABEL: @test_neg3
+entry:
+  %cmp = icmp ult i32 %x, 7
+  br i1 %cmp, label %merge, label %merge
+merge:
+; CHECK-LABEL: merge:
+; CHECK: icmp
+; CHECK: select
+  %cmp2 = icmp ult i32 %x, 7
+  %ret = select i1 %cmp2, i32 %x, i32 0
+  ret i32 %ret
+}
+
+declare i32 @bar()
diff --git a/test/Transforms/InstCombine/enforce-known-alignment.ll b/test/Transforms/InstCombine/enforce-known-alignment.ll
index 46bb60569fe2..323a7ec2998c 100644
--- a/test/Transforms/InstCombine/enforce-known-alignment.ll
+++ b/test/Transforms/InstCombine/enforce-known-alignment.ll
@@ -8,12 +8,12 @@ define void @foo(i32) {
 ; CHECK: alloca
 ; CHECK: align 16
 	%2 = alloca [3 x <{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>], align 16		; <[3 x <{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>]*> [#uses=1]
-	%3 = getelementptr [3 x <{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>]* %2, i32 0, i32 0		; <<{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>*> [#uses=1]
-	%4 = getelementptr <{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>* %3, i32 0, i32 0		; <{ { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } }*> [#uses=1]
-	%5 = getelementptr { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } }* %4, i32 0, i32 0		; <{ [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 }*> [#uses=1]
+	%3 = getelementptr [3 x <{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>], [3 x <{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>]* %2, i32 0, i32 0		; <<{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>*> [#uses=1]
+	%4 = getelementptr <{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>, <{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>* %3, i32 0, i32 0		; <{ { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } }*> [#uses=1]
+	%5 = getelementptr { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } }, { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } }* %4, i32 0, i32 0		; <{ [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 }*> [#uses=1]
 	%6 = bitcast { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 }* %5 to { [8 x i16] }*		; <{ [8 x i16] }*> [#uses=1]
-	%7 = getelementptr { [8 x i16] }* %6, i32 0, i32 0		; <[8 x i16]*> [#uses=1]
-	%8 = getelementptr [8 x i16]* %7, i32 0, i32 0		; <i16*> [#uses=1]
+	%7 = getelementptr { [8 x i16] }, { [8 x i16] }* %6, i32 0, i32 0		; <[8 x i16]*> [#uses=1]
+	%8 = getelementptr [8 x i16], [8 x i16]* %7, i32 0, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %8, align 16
     call void @bar(i16* %8)
 	ret void
@@ -24,12 +24,12 @@ declare void @bar(i16*)
 define void @foo_as1(i32 %a, [3 x <{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>] addrspace(1)* %b) {
 ; CHECK-LABEL: @foo_as1(
 ; CHECK: align 16
-  %1 = getelementptr [3 x <{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>] addrspace(1)* %b, i32 0, i32 0        ; <<{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>*> [#uses=1]
-  %2 = getelementptr <{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }> addrspace(1)* %1, i32 0, i32 0      ; <{ { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } }*> [#uses=1]
-  %3 = getelementptr { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } addrspace(1)* %2, i32 0, i32 0        ; <{ [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 }*> [#uses=1]
+  %1 = getelementptr [3 x <{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>], [3 x <{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>] addrspace(1)* %b, i32 0, i32 0        ; <<{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>*> [#uses=1]
+  %2 = getelementptr <{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }>, <{ { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } }> addrspace(1)* %1, i32 0, i32 0      ; <{ { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } }*> [#uses=1]
+  %3 = getelementptr { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } }, { { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } } addrspace(1)* %2, i32 0, i32 0        ; <{ [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 }*> [#uses=1]
   %4 = bitcast { [2 x { { i32 } }], [2 x i8], { i16 }, [2 x i8], i8, i8 } addrspace(1)* %3 to { [8 x i16] } addrspace(1)*     ; <{ [8 x i16] }*> [#uses=1]
-  %5 = getelementptr { [8 x i16] } addrspace(1)* %4, i32 0, i32 0     ; <[8 x i16]*> [#uses=1]
-  %6 = getelementptr [8 x i16] addrspace(1)* %5, i32 0, i32 0     ; <i16*> [#uses=1]
+  %5 = getelementptr { [8 x i16] }, { [8 x i16] } addrspace(1)* %4, i32 0, i32 0     ; <[8 x i16]*> [#uses=1]
+  %6 = getelementptr [8 x i16], [8 x i16] addrspace(1)* %5, i32 0, i32 0     ; <i16*> [#uses=1]
   store i16 0, i16 addrspace(1)* %6, align 16
   call void @bar_as1(i16 addrspace(1)* %6)
   ret void
diff --git a/test/Transforms/InstCombine/err-rep-cold.ll b/test/Transforms/InstCombine/err-rep-cold.ll
index 0cbafc43e0f6..6c4e4e1ccb01 100644
--- a/test/Transforms/InstCombine/err-rep-cold.ll
+++ b/test/Transforms/InstCombine/err-rep-cold.ll
@@ -18,11 +18,11 @@ entry:
   br i1 %cmp, label %if.then, label %return
 
 if.then:                                          ; preds = %entry
-  %0 = load %struct._IO_FILE** @stderr, align 8
-  %call = tail call i32 (%struct._IO_FILE*, i8*, ...)* @fprintf(%struct._IO_FILE* %0, i8* getelementptr inbounds ([13 x i8]* @.str, i64 0, i64 0), i32 %a) #1
+  %0 = load %struct._IO_FILE*, %struct._IO_FILE** @stderr, align 8
+  %call = tail call i32 (%struct._IO_FILE*, i8*, ...) @fprintf(%struct._IO_FILE* %0, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i64 0, i64 0), i32 %a) #1
   br label %return
 
-; CHECK: %call = tail call i32 (%struct._IO_FILE*, i8*, ...)* @fprintf(%struct._IO_FILE* %0, i8* getelementptr inbounds ([13 x i8]* @.str, i64 0, i64 0), i32 %a) #[[AT1:[0-9]+]]
+; CHECK: %call = tail call i32 (%struct._IO_FILE*, i8*, ...) @fprintf(%struct._IO_FILE* %0, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i64 0, i64 0), i32 %a) #[[AT1:[0-9]+]]
 
 return:                                           ; preds = %entry, %if.then
   %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
@@ -38,11 +38,11 @@ entry:
   br i1 %cmp, label %if.then, label %return
 
 if.then:                                          ; preds = %entry
-  %0 = load %struct._IO_FILE** @stderr, align 8
-  %1 = tail call i64 @fwrite(i8* getelementptr inbounds ([9 x i8]* @.str1, i64 0, i64 0), i64 8, i64 1, %struct._IO_FILE* %0)
+  %0 = load %struct._IO_FILE*, %struct._IO_FILE** @stderr, align 8
+  %1 = tail call i64 @fwrite(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str1, i64 0, i64 0), i64 8, i64 1, %struct._IO_FILE* %0)
   br label %return
 
-; CHECK: tail call i64 @fwrite(i8* getelementptr inbounds ([9 x i8]* @.str1, i64 0, i64 0), i64 8, i64 1, %struct._IO_FILE* %0) #[[AT2:[0-9]+]]
+; CHECK: tail call i64 @fwrite(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str1, i64 0, i64 0), i64 8, i64 1, %struct._IO_FILE* %0) #[[AT2:[0-9]+]]
 
 return:                                           ; preds = %entry, %if.then
   %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
@@ -58,11 +58,11 @@ entry:
   br i1 %cmp, label %if.then, label %return
 
 if.then:                                          ; preds = %entry
-  %0 = load %struct._IO_FILE** @stdout, align 8
-  %1 = tail call i64 @fwrite(i8* getelementptr inbounds ([9 x i8]* @.str1, i64 0, i64 0), i64 8, i64 1, %struct._IO_FILE* %0)
+  %0 = load %struct._IO_FILE*, %struct._IO_FILE** @stdout, align 8
+  %1 = tail call i64 @fwrite(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str1, i64 0, i64 0), i64 8, i64 1, %struct._IO_FILE* %0)
   br label %return
 
-; CHECK-NOT: tail call i64 @fwrite(i8* getelementptr inbounds ([9 x i8]* @.str1, i64 0, i64 0), i64 8, i64 1, %struct._IO_FILE* %0) #[[AT2]]
+; CHECK-NOT: tail call i64 @fwrite(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str1, i64 0, i64 0), i64 8, i64 1, %struct._IO_FILE* %0) #[[AT2]]
 
 return:                                           ; preds = %entry, %if.then
   %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
diff --git a/test/Transforms/InstCombine/extractvalue.ll b/test/Transforms/InstCombine/extractvalue.ll
index 04c7ffa219da..6319590873a2 100644
--- a/test/Transforms/InstCombine/extractvalue.ll
+++ b/test/Transforms/InstCombine/extractvalue.ll
@@ -13,7 +13,7 @@ define i32 @foo(i32 %a, i32 %b) {
         %s1 = insertvalue {i32, i32} %s1.1, i32 %b, 1
         %v1 = extractvalue {i32, i32} %s1, 0
         %v2 = extractvalue {i32, i32} %s1, 1
-        
+
         ; Build a nested struct and pull a sub struct out of it
         ; This requires instcombine to insert a few insertvalue instructions
         %ns1.1 = insertvalue {i32, {i32, i32}} undef, i32 %v1, 0
@@ -40,8 +40,8 @@ define i32 @foo(i32 %a, i32 %b) {
 }
 
 ; CHECK-LABEL: define i32 @extract2gep(
-; CHECK-NEXT: [[GEP:%[a-z0-9]+]] = getelementptr inbounds {{.*}}* %pair, i32 0, i32 1
-; CHECK-NEXT: [[LOAD:%[A-Za-z0-9]+]] = load i32* [[GEP]]
+; CHECK-NEXT: [[GEP:%[a-z0-9]+]] = getelementptr inbounds {{.*}}, {{.*}}* %pair, i64 0, i32 1
+; CHECK-NEXT: [[LOAD:%[A-Za-z0-9]+]] = load i32, i32* [[GEP]]
 ; CHECK-NEXT: store
 ; CHECK-NEXT: br label %loop
 ; CHECK-NOT: extractvalue
@@ -52,7 +52,7 @@ define i32 @extract2gep({i32, i32}* %pair, i32* %P) {
         ; The load + extractvalue should be converted
         ; to an inbounds gep + smaller load.
         ; The new load should be in the same spot as the old load.
-        %L = load {i32, i32}* %pair
+        %L = load {i32, i32}, {i32, i32}* %pair
         store i32 0, i32* %P
         br label %loop
 
@@ -68,13 +68,13 @@ end:
 }
 
 ; CHECK-LABEL: define i32 @doubleextract2gep(
-; CHECK-NEXT: [[GEP:%[a-z0-9]+]] = getelementptr inbounds {{.*}}* %arg, i32 0, i32 1, i32 1
-; CHECK-NEXT: [[LOAD:%[A-Za-z0-9]+]] = load i32* [[GEP]]
+; CHECK-NEXT: [[GEP:%[a-z0-9]+]] = getelementptr inbounds {{.*}}, {{.*}}* %arg, i64 0, i32 1, i32 1
+; CHECK-NEXT: [[LOAD:%[A-Za-z0-9]+]] = load i32, i32* [[GEP]]
 ; CHECK-NEXT: ret i32 [[LOAD]]
 define i32 @doubleextract2gep({i32, {i32, i32}}* %arg) {
         ; The load + extractvalues should be converted
         ; to a 3-index inbounds gep + smaller load.
-        %L = load {i32, {i32, i32}}* %arg
+        %L = load {i32, {i32, i32}}, {i32, {i32, i32}}* %arg
         %E1 = extractvalue {i32, {i32, i32}} %L, 1
         %E2 = extractvalue {i32, i32} %E1, 1
         ret i32 %E2
@@ -88,7 +88,7 @@ define i32 @doubleextract2gep({i32, {i32, i32}}* %arg) {
 ; CHECK-NEXT: ret
 define i32 @nogep-multiuse({i32, i32}* %pair) {
         ; The load should be left unchanged since both parts are needed.
-        %L = load volatile {i32, i32}* %pair
+        %L = load volatile {i32, i32}, {i32, i32}* %pair
         %LHS = extractvalue {i32, i32} %L, 0
         %RHS = extractvalue {i32, i32} %L, 1
         %R = add i32 %LHS, %RHS
@@ -101,7 +101,7 @@ define i32 @nogep-multiuse({i32, i32}* %pair) {
 ; CHECK-NEXT: ret
 define i32 @nogep-volatile({i32, i32}* %pair) {
         ; The load volatile should be left unchanged.
-        %L = load volatile {i32, i32}* %pair
+        %L = load volatile {i32, i32}, {i32, i32}* %pair
         %E = extractvalue {i32, i32} %L, 1
         ret i32 %E
 }
diff --git a/test/Transforms/InstCombine/fast-math.ll b/test/Transforms/InstCombine/fast-math.ll
index c6081c399253..4eebdbdfacf1 100644
--- a/test/Transforms/InstCombine/fast-math.ll
+++ b/test/Transforms/InstCombine/fast-math.ll
@@ -267,6 +267,14 @@ define <4 x float> @fmul3_vec(<4 x float> %f1, <4 x float> %f2) {
 ; CHECK: fmul fast <4 x float> %f1, <float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00>
 }
 
+; Make sure fmul with constant expression doesn't assert.
+define <4 x float> @fmul3_vec_constexpr(<4 x float> %f1, <4 x float> %f2) {
+  %constExprMul = bitcast i128 trunc (i160 bitcast (<5 x float> <float 6.0e+3, float 6.0e+3, float 2.0e+3, float 1.0e+3, float undef> to i160) to i128) to <4 x float>  
+  %t1 = fdiv <4 x float> %f1, <float 2.0e+3, float 3.0e+3, float 2.0e+3, float 1.0e+3>
+  %t3 = fmul fast <4 x float> %t1, %constExprMul
+  ret <4 x float> %t3
+}
+
 ; Rule "X/C1 * C2 => X * (C2/C1) is not applicable if C2/C1 is either a special
 ; value of a denormal. The 0x3810000000000000 here take value FLT_MIN
 ;
diff --git a/test/Transforms/InstCombine/fcmp.ll b/test/Transforms/InstCombine/fcmp.ll
index ee39d1084ebc..7fd46f228183 100644
--- a/test/Transforms/InstCombine/fcmp.ll
+++ b/test/Transforms/InstCombine/fcmp.ll
@@ -240,3 +240,38 @@ define i32 @test17(double %a, double (double)* %p) nounwind {
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
+
+; Can fold fcmp with undef on one side by choosing NaN for the undef
+define i32 @test18_undef_unordered(float %a) nounwind {
+; CHECK-LABEL: @test18_undef_unordered
+; CHECK: ret i32 1
+  %cmp = fcmp ueq float %a, undef
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+; Can fold fcmp with undef on one side by choosing NaN for the undef
+define i32 @test18_undef_ordered(float %a) nounwind {
+; CHECK-LABEL: @test18_undef_ordered
+; CHECK: ret i32 0
+  %cmp = fcmp oeq float %a, undef
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Can fold fcmp with undef on both side
+;   fcmp u_pred undef, undef -> true
+;   fcmp o_pred undef, undef -> false
+; because whatever you choose for the first undef
+; you can choose NaN for the other undef
+define i1 @test19_undef_unordered() nounwind {
+; CHECK-LABEL: @test19_undef
+; CHECK: ret i1 true
+  %cmp = fcmp ueq float undef, undef
+  ret i1 %cmp
+}
+define i1 @test19_undef_ordered() nounwind {
+; CHECK-LABEL: @test19_undef
+; CHECK: ret i1 false
+  %cmp = fcmp oeq float undef, undef
+  ret i1 %cmp
+}
diff --git a/test/Transforms/InstCombine/fmul.ll b/test/Transforms/InstCombine/fmul.ll
index a776765ac2ca..ac3000fc0514 100644
--- a/test/Transforms/InstCombine/fmul.ll
+++ b/test/Transforms/InstCombine/fmul.ll
@@ -74,7 +74,7 @@ define float @test7(float %x, float %y) {
 ; Don't crash when attempting to cast a constant FMul to an instruction.
 define void @test8(i32* %inout) {
 entry:
-  %0 = load i32* %inout, align 4
+  %0 = load i32, i32* %inout, align 4
   %conv = uitofp i32 %0 to float
   %vecinit = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float undef>, float %conv, i32 3
   %sub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %vecinit
diff --git a/test/Transforms/InstCombine/fold-vector-zero.ll b/test/Transforms/InstCombine/fold-vector-zero.ll
index e1d86b6cd07c..bf661df7795d 100644
--- a/test/Transforms/InstCombine/fold-vector-zero.ll
+++ b/test/Transforms/InstCombine/fold-vector-zero.ll
@@ -9,7 +9,7 @@ bb30:
 	%l0 = phi i64 [ -2222, %bb8 ], [ %r23, %bb30 ]
 	%r2 = add i64 %s0, %B
 	%r3 = inttoptr i64 %r2 to <2 x double>*
-	%r4 = load <2 x double>* %r3, align 8
+	%r4 = load <2 x double>, <2 x double>* %r3, align 8
 	%r6 = bitcast <2 x double> %r4 to <2 x i64>
 	%r7 = bitcast <2 x double> zeroinitializer to <2 x i64>
 	%r8 = insertelement <2 x i64> undef, i64 9223372036854775807, i32 0
diff --git a/test/Transforms/InstCombine/fp-ret-bitcast.ll b/test/Transforms/InstCombine/fp-ret-bitcast.ll
index b2fbc0b882db..7106933d2bde 100644
--- a/test/Transforms/InstCombine/fp-ret-bitcast.ll
+++ b/test/Transforms/InstCombine/fp-ret-bitcast.ll
@@ -13,11 +13,11 @@ define void @bork() nounwind  {
 entry:
 	%color = alloca %struct.NSArray*
 	%color.466 = alloca %struct.NSObject*
-	%tmp103 = load %struct.NSArray** %color, align 4
-	%tmp103104 = getelementptr %struct.NSArray* %tmp103, i32 0, i32 0
+	%tmp103 = load %struct.NSArray*, %struct.NSArray** %color, align 4
+	%tmp103104 = getelementptr %struct.NSArray, %struct.NSArray* %tmp103, i32 0, i32 0
 	store %struct.NSObject* %tmp103104, %struct.NSObject** %color.466, align 4
-	%tmp105 = load %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_81", align 4
-	%tmp106 = load %struct.NSObject** %color.466, align 4
+	%tmp105 = load %struct.objc_selector*, %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_81", align 4
+	%tmp106 = load %struct.NSObject*, %struct.NSObject** %color.466, align 4
 	%tmp107 = call float bitcast (void (%struct.NSObject*, ...)* @objc_msgSend_fpret to float (%struct.NSObject*, %struct.objc_selector*)*)( %struct.NSObject* %tmp106, %struct.objc_selector* %tmp105 ) nounwind
 	br label %exit
 
diff --git a/test/Transforms/InstCombine/fpextend.ll b/test/Transforms/InstCombine/fpextend.ll
index 8640cd2b6f5c..775caadb45a4 100644
--- a/test/Transforms/InstCombine/fpextend.ll
+++ b/test/Transforms/InstCombine/fpextend.ll
@@ -5,7 +5,7 @@
 
 define void @test() nounwind  {
 entry:
-	%tmp = load float* @X, align 4		; <float> [#uses=1]
+	%tmp = load float, float* @X, align 4		; <float> [#uses=1]
 	%tmp1 = fpext float %tmp to double		; <double> [#uses=1]
 	%tmp3 = fadd double %tmp1, 0.000000e+00		; <double> [#uses=1]
 	%tmp34 = fptrunc double %tmp3 to float		; <float> [#uses=1]
@@ -15,9 +15,9 @@ entry:
 
 define void @test2() nounwind  {
 entry:
-	%tmp = load float* @X, align 4		; <float> [#uses=1]
+	%tmp = load float, float* @X, align 4		; <float> [#uses=1]
 	%tmp1 = fpext float %tmp to double		; <double> [#uses=1]
-	%tmp2 = load float* @Y, align 4		; <float> [#uses=1]
+	%tmp2 = load float, float* @Y, align 4		; <float> [#uses=1]
 	%tmp23 = fpext float %tmp2 to double		; <double> [#uses=1]
 	%tmp5 = fmul double %tmp1, %tmp23		; <double> [#uses=1]
 	%tmp56 = fptrunc double %tmp5 to float		; <float> [#uses=1]
@@ -27,9 +27,9 @@ entry:
 
 define void @test3() nounwind  {
 entry:
-	%tmp = load float* @X, align 4		; <float> [#uses=1]
+	%tmp = load float, float* @X, align 4		; <float> [#uses=1]
 	%tmp1 = fpext float %tmp to double		; <double> [#uses=1]
-	%tmp2 = load float* @Y, align 4		; <float> [#uses=1]
+	%tmp2 = load float, float* @Y, align 4		; <float> [#uses=1]
 	%tmp23 = fpext float %tmp2 to double		; <double> [#uses=1]
 	%tmp5 = fdiv double %tmp1, %tmp23		; <double> [#uses=1]
 	%tmp56 = fptrunc double %tmp5 to float		; <float> [#uses=1]
@@ -39,7 +39,7 @@ entry:
 
 define void @test4() nounwind  {
 entry:
-	%tmp = load float* @X, align 4		; <float> [#uses=1]
+	%tmp = load float, float* @X, align 4		; <float> [#uses=1]
 	%tmp1 = fpext float %tmp to double		; <double> [#uses=1]
 	%tmp2 = fsub double -0.000000e+00, %tmp1		; <double> [#uses=1]
 	%tmp34 = fptrunc double %tmp2 to float		; <float> [#uses=1]
diff --git a/test/Transforms/InstCombine/fprintf-1.ll b/test/Transforms/InstCombine/fprintf-1.ll
index 6741345839a0..6d21f39d4fd6 100644
--- a/test/Transforms/InstCombine/fprintf-1.ll
+++ b/test/Transforms/InstCombine/fprintf-1.ll
@@ -19,9 +19,9 @@ declare i32 @fprintf(%FILE*, i8*, ...)
 
 define void @test_simplify1(%FILE* %fp) {
 ; CHECK-LABEL: @test_simplify1(
-  %fmt = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
-  call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt)
-; CHECK-NEXT: call i32 @fwrite(i8* getelementptr inbounds ([13 x i8]* @hello_world, i32 0, i32 0), i32 12, i32 1, %FILE* %fp)
+  %fmt = getelementptr [13 x i8], [13 x i8]* @hello_world, i32 0, i32 0
+  call i32 (%FILE*, i8*, ...) @fprintf(%FILE* %fp, i8* %fmt)
+; CHECK-NEXT: call i32 @fwrite(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @hello_world, i32 0, i32 0), i32 12, i32 1, %FILE* %fp)
   ret void
 ; CHECK-NEXT: ret void
 }
@@ -30,8 +30,8 @@ define void @test_simplify1(%FILE* %fp) {
 
 define void @test_simplify2(%FILE* %fp) {
 ; CHECK-LABEL: @test_simplify2(
-  %fmt = getelementptr [3 x i8]* @percent_c, i32 0, i32 0
-  call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt, i8 104)
+  %fmt = getelementptr [3 x i8], [3 x i8]* @percent_c, i32 0, i32 0
+  call i32 (%FILE*, i8*, ...) @fprintf(%FILE* %fp, i8* %fmt, i8 104)
 ; CHECK-NEXT: call i32 @fputc(i32 104, %FILE* %fp)
   ret void
 ; CHECK-NEXT: ret void
@@ -42,10 +42,10 @@ define void @test_simplify2(%FILE* %fp) {
 
 define void @test_simplify3(%FILE* %fp) {
 ; CHECK-LABEL: @test_simplify3(
-  %fmt = getelementptr [3 x i8]* @percent_s, i32 0, i32 0
-  %str = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
-  call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt, i8* %str)
-; CHECK-NEXT: call i32 @fwrite(i8* getelementptr inbounds ([13 x i8]* @hello_world, i32 0, i32 0), i32 12, i32 1, %FILE* %fp)
+  %fmt = getelementptr [3 x i8], [3 x i8]* @percent_s, i32 0, i32 0
+  %str = getelementptr [13 x i8], [13 x i8]* @hello_world, i32 0, i32 0
+  call i32 (%FILE*, i8*, ...) @fprintf(%FILE* %fp, i8* %fmt, i8* %str)
+; CHECK-NEXT: call i32 @fwrite(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @hello_world, i32 0, i32 0), i32 12, i32 1, %FILE* %fp)
   ret void
 ; CHECK-NEXT: ret void
 }
@@ -54,36 +54,36 @@ define void @test_simplify3(%FILE* %fp) {
 
 define void @test_simplify4(%FILE* %fp) {
 ; CHECK-IPRINTF-LABEL: @test_simplify4(
-  %fmt = getelementptr [3 x i8]* @percent_d, i32 0, i32 0
-  call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt, i32 187)
-; CHECK-IPRINTF-NEXT: call i32 (%FILE*, i8*, ...)* @fiprintf(%FILE* %fp, i8* getelementptr inbounds ([3 x i8]* @percent_d, i32 0, i32 0), i32 187)
+  %fmt = getelementptr [3 x i8], [3 x i8]* @percent_d, i32 0, i32 0
+  call i32 (%FILE*, i8*, ...) @fprintf(%FILE* %fp, i8* %fmt, i32 187)
+; CHECK-IPRINTF-NEXT: call i32 (%FILE*, i8*, ...) @fiprintf(%FILE* %fp, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @percent_d, i32 0, i32 0), i32 187)
   ret void
 ; CHECK-IPRINTF-NEXT: ret void
 }
 
 define void @test_no_simplify1(%FILE* %fp) {
 ; CHECK-IPRINTF-LABEL: @test_no_simplify1(
-  %fmt = getelementptr [3 x i8]* @percent_f, i32 0, i32 0
-  call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt, double 1.87)
-; CHECK-IPRINTF-NEXT: call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* getelementptr inbounds ([3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00)
+  %fmt = getelementptr [3 x i8], [3 x i8]* @percent_f, i32 0, i32 0
+  call i32 (%FILE*, i8*, ...) @fprintf(%FILE* %fp, i8* %fmt, double 1.87)
+; CHECK-IPRINTF-NEXT: call i32 (%FILE*, i8*, ...) @fprintf(%FILE* %fp, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00)
   ret void
 ; CHECK-IPRINTF-NEXT: ret void
 }
 
 define void @test_no_simplify2(%FILE* %fp, double %d) {
 ; CHECK-LABEL: @test_no_simplify2(
-  %fmt = getelementptr [3 x i8]* @percent_f, i32 0, i32 0
-  call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt, double %d)
-; CHECK-NEXT: call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* getelementptr inbounds ([3 x i8]* @percent_f, i32 0, i32 0), double %d)
+  %fmt = getelementptr [3 x i8], [3 x i8]* @percent_f, i32 0, i32 0
+  call i32 (%FILE*, i8*, ...) @fprintf(%FILE* %fp, i8* %fmt, double %d)
+; CHECK-NEXT: call i32 (%FILE*, i8*, ...) @fprintf(%FILE* %fp, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @percent_f, i32 0, i32 0), double %d)
   ret void
 ; CHECK-NEXT: ret void
 }
 
 define i32 @test_no_simplify3(%FILE* %fp) {
 ; CHECK-LABEL: @test_no_simplify3(
-  %fmt = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
-  %1 = call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt)
-; CHECK-NEXT: call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* getelementptr inbounds ([13 x i8]* @hello_world, i32 0, i32 0))
+  %fmt = getelementptr [13 x i8], [13 x i8]* @hello_world, i32 0, i32 0
+  %1 = call i32 (%FILE*, i8*, ...) @fprintf(%FILE* %fp, i8* %fmt)
+; CHECK-NEXT: call i32 (%FILE*, i8*, ...) @fprintf(%FILE* %fp, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @hello_world, i32 0, i32 0))
   ret i32 %1
 ; CHECK-NEXT: ret i32 %1
 }
diff --git a/test/Transforms/InstCombine/fputs-1.ll b/test/Transforms/InstCombine/fputs-1.ll
index 473610e6120a..1c245753e61f 100644
--- a/test/Transforms/InstCombine/fputs-1.ll
+++ b/test/Transforms/InstCombine/fputs-1.ll
@@ -16,7 +16,7 @@ declare i32 @fputs(i8*, %FILE*)
 
 define void @test_simplify1(%FILE* %fp) {
 ; CHECK-LABEL: @test_simplify1(
-  %str = getelementptr [1 x i8]* @empty, i32 0, i32 0
+  %str = getelementptr [1 x i8], [1 x i8]* @empty, i32 0, i32 0
   call i32 @fputs(i8* %str, %FILE* %fp)
   ret void
 ; CHECK-NEXT: ret void
@@ -26,7 +26,7 @@ define void @test_simplify1(%FILE* %fp) {
 
 define void @test_simplify2(%FILE* %fp) {
 ; CHECK-LABEL: @test_simplify2(
-  %str = getelementptr [2 x i8]* @A, i32 0, i32 0
+  %str = getelementptr [2 x i8], [2 x i8]* @A, i32 0, i32 0
   call i32 @fputs(i8* %str, %FILE* %fp)
 ; CHECK-NEXT: call i32 @fputc(i32 65, %FILE* %fp)
   ret void
@@ -35,9 +35,9 @@ define void @test_simplify2(%FILE* %fp) {
 
 define void @test_simplify3(%FILE* %fp) {
 ; CHECK-LABEL: @test_simplify3(
-  %str = getelementptr [7 x i8]* @hello, i32 0, i32 0
+  %str = getelementptr [7 x i8], [7 x i8]* @hello, i32 0, i32 0
   call i32 @fputs(i8* %str, %FILE* %fp)
-; CHECK-NEXT: call i32 @fwrite(i8* getelementptr inbounds ([7 x i8]* @hello, i32 0, i32 0), i32 6, i32 1, %FILE* %fp)
+; CHECK-NEXT: call i32 @fwrite(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @hello, i32 0, i32 0), i32 6, i32 1, %FILE* %fp)
   ret void
 ; CHECK-NEXT: ret void
 }
diff --git a/test/Transforms/InstCombine/fwrite-1.ll b/test/Transforms/InstCombine/fwrite-1.ll
index 6f9a8e463a8c..10f0b23e1d8d 100644
--- a/test/Transforms/InstCombine/fwrite-1.ll
+++ b/test/Transforms/InstCombine/fwrite-1.ll
@@ -15,7 +15,7 @@ declare i64 @fwrite(i8*, i64, i64, %FILE *)
 
 define void @test_simplify1(%FILE* %fp) {
 ; CHECK-LABEL: @test_simplify1(
-  %str = getelementptr inbounds [1 x i8]* @str, i64 0, i64 0
+  %str = getelementptr inbounds [1 x i8], [1 x i8]* @str, i64 0, i64 0
   call i64 @fwrite(i8* %str, i64 1, i64 1, %FILE* %fp)
 ; CHECK-NEXT: call i32 @fputc(i32 0, %FILE* %fp)
   ret void
@@ -24,7 +24,7 @@ define void @test_simplify1(%FILE* %fp) {
 
 define void @test_simplify2(%FILE* %fp) {
 ; CHECK-LABEL: @test_simplify2(
-  %str = getelementptr inbounds [0 x i8]* @empty, i64 0, i64 0
+  %str = getelementptr inbounds [0 x i8], [0 x i8]* @empty, i64 0, i64 0
   call i64 @fwrite(i8* %str, i64 1, i64 0, %FILE* %fp)
   ret void
 ; CHECK-NEXT: ret void
@@ -32,7 +32,7 @@ define void @test_simplify2(%FILE* %fp) {
 
 define void @test_simplify3(%FILE* %fp) {
 ; CHECK-LABEL: @test_simplify3(
-  %str = getelementptr inbounds [0 x i8]* @empty, i64 0, i64 0
+  %str = getelementptr inbounds [0 x i8], [0 x i8]* @empty, i64 0, i64 0
   call i64 @fwrite(i8* %str, i64 0, i64 1, %FILE* %fp)
   ret void
 ; CHECK-NEXT: ret void
@@ -40,7 +40,7 @@ define void @test_simplify3(%FILE* %fp) {
 
 define i64 @test_no_simplify1(%FILE* %fp) {
 ; CHECK-LABEL: @test_no_simplify1(
-  %str = getelementptr inbounds [1 x i8]* @str, i64 0, i64 0
+  %str = getelementptr inbounds [1 x i8], [1 x i8]* @str, i64 0, i64 0
   %ret = call i64 @fwrite(i8* %str, i64 1, i64 1, %FILE* %fp)
 ; CHECK-NEXT: call i64 @fwrite
   ret i64 %ret
@@ -49,7 +49,7 @@ define i64 @test_no_simplify1(%FILE* %fp) {
 
 define void @test_no_simplify2(%FILE* %fp, i64 %size) {
 ; CHECK-LABEL: @test_no_simplify2(
-  %str = getelementptr inbounds [1 x i8]* @str, i64 0, i64 0
+  %str = getelementptr inbounds [1 x i8], [1 x i8]* @str, i64 0, i64 0
   call i64 @fwrite(i8* %str, i64 %size, i64 1, %FILE* %fp)
 ; CHECK-NEXT: call i64 @fwrite
   ret void
diff --git a/test/Transforms/InstCombine/gc.relocate.ll b/test/Transforms/InstCombine/gc.relocate.ll
new file mode 100644
index 000000000000..a51aac10eb57
--- /dev/null
+++ b/test/Transforms/InstCombine/gc.relocate.ll
@@ -0,0 +1,21 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+
+; Uses InstCombine with DataLayout to propagate dereferenceable
+; attribute via gc.relocate: if the derived ptr is dereferenceable(N),
+; then the return attribute of gc.relocate is dereferenceable(N).
+
+declare zeroext i1 @return_i1()
+declare i32 @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i32, ...)
+declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32, i32, i32)
+
+define i32 addrspace(1)* @deref(i32 addrspace(1)* dereferenceable(8) %dparam) gc "statepoint-example" {
+; Checks that a dereferenceabler pointer
+; CHECK-LABEL: @deref
+; CHECK: call dereferenceable(8)
+entry:
+    %load = load i32, i32 addrspace(1)* %dparam
+    %tok = tail call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, i32 addrspace(1)* %dparam)
+    %relocate = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %tok,  i32 7, i32 7)
+    ret i32 addrspace(1)* %relocate
+}
diff --git a/test/Transforms/InstCombine/gep-addrspace.ll b/test/Transforms/InstCombine/gep-addrspace.ll
index 29511a3c6677..aa46ea671302 100644
--- a/test/Transforms/InstCombine/gep-addrspace.ll
+++ b/test/Transforms/InstCombine/gep-addrspace.ll
@@ -8,11 +8,11 @@ target triple = "x86_64-pc-win32"
 ; make sure that we are not crashing when creating an illegal type
 define void @func(%myStruct addrspace(1)* nocapture %p) nounwind {
 ST:
-  %A = getelementptr inbounds %myStruct addrspace(1)* %p, i64 0
+  %A = getelementptr inbounds %myStruct, %myStruct addrspace(1)* %p, i64 0
   %B = addrspacecast %myStruct addrspace(1)* %A to %myStruct*
-  %C = getelementptr inbounds %myStruct* %B, i32 0, i32 1
-  %D = getelementptr inbounds [3 x float]* %C, i32 0, i32 2
-  %E = load float* %D, align 4
+  %C = getelementptr inbounds %myStruct, %myStruct* %B, i32 0, i32 1
+  %D = getelementptr inbounds [3 x float], [3 x float]* %C, i32 0, i32 2
+  %E = load float, float* %D, align 4
   %F = fsub float %E, undef
   ret void
 }
@@ -23,9 +23,9 @@ ST:
 define void @keep_necessary_addrspacecast(i64 %i, float** %out0, float** %out1) {
 entry:
 ; CHECK-LABEL: @keep_necessary_addrspacecast
-  %0 = getelementptr [256 x float]* addrspacecast ([256 x float] addrspace(3)* @array to [256 x float]*), i64 0, i64 %i
+  %0 = getelementptr [256 x float], [256 x float]* addrspacecast ([256 x float] addrspace(3)* @array to [256 x float]*), i64 0, i64 %i
 ; CHECK: addrspacecast float addrspace(3)* %{{[0-9]+}} to float*
-  %1 = getelementptr [0 x float]* addrspacecast (float addrspace(3)* @scalar to [0 x float]*), i64 0, i64 %i
+  %1 = getelementptr [0 x float], [0 x float]* addrspacecast (float addrspace(3)* @scalar to [0 x float]*), i64 0, i64 %i
 ; CHECK: addrspacecast float addrspace(3)* %{{[0-9]+}} to float*
   store float* %0, float** %out0, align 4
   store float* %1, float** %out1, align 4
diff --git a/test/Transforms/InstCombine/gep-sext.ll b/test/Transforms/InstCombine/gep-sext.ll
new file mode 100644
index 000000000000..36e2aeff02cf
--- /dev/null
+++ b/test/Transforms/InstCombine/gep-sext.ll
@@ -0,0 +1,61 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-pc-win32"
+
+declare void @use(i32) readonly
+
+; We prefer to canonicalize the machine width gep indices early
+define void @test(i32* %p, i32 %index) {
+; CHECK-LABEL: @test
+; CHECK-NEXT: %1 = sext i32 %index to i64
+; CHECK-NEXT: %addr = getelementptr i32, i32* %p, i64 %1
+  %addr = getelementptr i32, i32* %p, i32 %index
+  %val = load i32, i32* %addr
+  call void @use(i32 %val)
+  ret void
+}
+; If they've already been canonicalized via zext, that's fine
+define void @test2(i32* %p, i32 %index) {
+; CHECK-LABEL: @test2
+; CHECK-NEXT: %i = zext i32 %index to i64
+; CHECK-NEXT: %addr = getelementptr i32, i32* %p, i64 %i
+  %i = zext i32 %index to i64
+  %addr = getelementptr i32, i32* %p, i64 %i
+  %val = load i32, i32* %addr
+  call void @use(i32 %val)
+  ret void
+}
+; If we can use a zext, we prefer that.  This requires
+; knowing that the index is positive.
+define void @test3(i32* %p, i32 %index) {
+; CHECK-LABEL: @test3
+; CHECK:   zext
+; CHECK-NOT: sext
+  %addr_begin = getelementptr i32, i32* %p, i64 40
+  %addr_fixed = getelementptr i32, i32* %addr_begin, i64 48
+  %val_fixed = load i32, i32* %addr_fixed, !range !0
+  %addr = getelementptr i32, i32* %addr_begin, i32 %val_fixed
+  %val = load i32, i32* %addr
+  call void @use(i32 %val)
+  ret void
+}
+; Replace sext with zext where possible
+define void @test4(i32* %p, i32 %index) {
+; CHECK-LABEL: @test4
+; CHECK:   zext
+; CHECK-NOT: sext
+  %addr_begin = getelementptr i32, i32* %p, i64 40
+  %addr_fixed = getelementptr i32, i32* %addr_begin, i64 48
+  %val_fixed = load i32, i32* %addr_fixed, !range !0
+  %i = sext i32 %val_fixed to i64
+  %addr = getelementptr i32, i32* %addr_begin, i64 %i
+  %val = load i32, i32* %addr
+  call void @use(i32 %val)
+  ret void
+}
+
+;;  !range !0
+!0 = !{i32 0, i32 2147483647}
+
+
+
diff --git a/test/Transforms/InstCombine/gepgep.ll b/test/Transforms/InstCombine/gepgep.ll
index 9e681d28c424..24b81aaea3f1 100644
--- a/test/Transforms/InstCombine/gepgep.ll
+++ b/test/Transforms/InstCombine/gepgep.ll
@@ -8,6 +8,6 @@ target triple = "x86_64-unknown-linux-gnu"
 declare void @use(i8*)
 
 define void @f() {
-  call void @use(i8* getelementptr (i8* getelementptr (i8* bitcast ([64 x float]* @buffer to i8*), i64 and (i64 sub (i64 0, i64 ptrtoint ([64 x float]* @buffer to i64)), i64 63)), i64 64))
+  call void @use(i8* getelementptr (i8, i8* getelementptr (i8, i8* bitcast ([64 x float]* @buffer to i8*), i64 and (i64 sub (i64 0, i64 ptrtoint ([64 x float]* @buffer to i64)), i64 63)), i64 64))
   ret void
 }
diff --git a/test/Transforms/InstCombine/gepphigep.ll b/test/Transforms/InstCombine/gepphigep.ll
index 9aab609901e2..5ae3171b39f6 100644
--- a/test/Transforms/InstCombine/gepphigep.ll
+++ b/test/Transforms/InstCombine/gepphigep.ll
@@ -2,55 +2,135 @@
 
 %struct1 = type { %struct2*, i32, i32, i32 }
 %struct2 = type { i32, i32 }
+%struct3 = type { i32, %struct4, %struct4 }
+%struct4 = type { %struct2, %struct2 }
 
 define i32 @test1(%struct1* %dm, i1 %tmp4, i64 %tmp9, i64 %tmp19) {
 bb:
-  %tmp = getelementptr inbounds %struct1* %dm, i64 0, i32 0
-  %tmp1 = load %struct2** %tmp, align 8
+  %tmp = getelementptr inbounds %struct1, %struct1* %dm, i64 0, i32 0
+  %tmp1 = load %struct2*, %struct2** %tmp, align 8
   br i1 %tmp4, label %bb1, label %bb2
 
 bb1:
-  %tmp10 = getelementptr inbounds %struct2* %tmp1, i64 %tmp9
-  %tmp11 = getelementptr inbounds %struct2* %tmp10, i64 0, i32 0
+  %tmp10 = getelementptr inbounds %struct2, %struct2* %tmp1, i64 %tmp9
+  %tmp11 = getelementptr inbounds %struct2, %struct2* %tmp10, i64 0, i32 0
   store i32 0, i32* %tmp11, align 4
   br label %bb3
 
 bb2:
-  %tmp20 = getelementptr inbounds %struct2* %tmp1, i64 %tmp19
-  %tmp21 = getelementptr inbounds %struct2* %tmp20, i64 0, i32 0
+  %tmp20 = getelementptr inbounds %struct2, %struct2* %tmp1, i64 %tmp19
+  %tmp21 = getelementptr inbounds %struct2, %struct2* %tmp20, i64 0, i32 0
   store i32 0, i32* %tmp21, align 4
   br label %bb3
 
 bb3:
   %phi = phi %struct2* [ %tmp10, %bb1 ], [ %tmp20, %bb2 ]
-  %tmp24 = getelementptr inbounds %struct2* %phi, i64 0, i32 1
-  %tmp25 = load i32* %tmp24, align 4
+  %tmp24 = getelementptr inbounds %struct2, %struct2* %phi, i64 0, i32 1
+  %tmp25 = load i32, i32* %tmp24, align 4
   ret i32 %tmp25
 
 ; CHECK-LABEL: @test1(
-; CHECK: getelementptr inbounds %struct2* %tmp1, i64 %tmp9, i32 0
-; CHECK: getelementptr inbounds %struct2* %tmp1, i64 %tmp19, i32 0
+; CHECK: getelementptr inbounds %struct2, %struct2* %tmp1, i64 %tmp9, i32 0
+; CHECK: getelementptr inbounds %struct2, %struct2* %tmp1, i64 %tmp19, i32 0
 ; CHECK: %[[PHI:[0-9A-Za-z]+]] = phi i64 [ %tmp9, %bb1 ], [ %tmp19, %bb2 ]
-; CHECK: getelementptr inbounds %struct2* %tmp1, i64 %[[PHI]], i32 1
+; CHECK: getelementptr inbounds %struct2, %struct2* %tmp1, i64 %[[PHI]], i32 1
 
 }
 
 define i32 @test2(%struct1* %dm, i1 %tmp4, i64 %tmp9, i64 %tmp19) {
 bb:
-  %tmp = getelementptr inbounds %struct1* %dm, i64 0, i32 0
-  %tmp1 = load %struct2** %tmp, align 8
-  %tmp10 = getelementptr inbounds %struct2* %tmp1, i64 %tmp9
-  %tmp11 = getelementptr inbounds %struct2* %tmp10, i64 0, i32 0
+  %tmp = getelementptr inbounds %struct1, %struct1* %dm, i64 0, i32 0
+  %tmp1 = load %struct2*, %struct2** %tmp, align 8
+  %tmp10 = getelementptr inbounds %struct2, %struct2* %tmp1, i64 %tmp9
+  %tmp11 = getelementptr inbounds %struct2, %struct2* %tmp10, i64 0, i32 0
   store i32 0, i32* %tmp11, align 4
-  %tmp20 = getelementptr inbounds %struct2* %tmp1, i64 %tmp19
-  %tmp21 = getelementptr inbounds %struct2* %tmp20, i64 0, i32 0
+  %tmp20 = getelementptr inbounds %struct2, %struct2* %tmp1, i64 %tmp19
+  %tmp21 = getelementptr inbounds %struct2, %struct2* %tmp20, i64 0, i32 0
   store i32 0, i32* %tmp21, align 4
-  %tmp24 = getelementptr inbounds %struct2* %tmp10, i64 0, i32 1
-  %tmp25 = load i32* %tmp24, align 4
+  %tmp24 = getelementptr inbounds %struct2, %struct2* %tmp10, i64 0, i32 1
+  %tmp25 = load i32, i32* %tmp24, align 4
   ret i32 %tmp25
 
 ; CHECK-LABEL: @test2(
-; CHECK: getelementptr inbounds %struct2* %tmp1, i64 %tmp9, i32 0
-; CHECK: getelementptr inbounds %struct2* %tmp1, i64 %tmp19, i32 0
-; CHECK: getelementptr inbounds %struct2* %tmp1, i64 %tmp9, i32 1
+; CHECK: getelementptr inbounds %struct2, %struct2* %tmp1, i64 %tmp9, i32 0
+; CHECK: getelementptr inbounds %struct2, %struct2* %tmp1, i64 %tmp19, i32 0
+; CHECK: getelementptr inbounds %struct2, %struct2* %tmp1, i64 %tmp9, i32 1
+}
+
+; Check that instcombine doesn't insert GEPs before landingpad.
+
+define i32 @test3(%struct3* %dm, i1 %tmp4, i64 %tmp9, i64 %tmp19, i64 %tmp20, i64 %tmp21) {
+bb:
+  %tmp = getelementptr inbounds %struct3, %struct3* %dm, i64 0
+  br i1 %tmp4, label %bb1, label %bb2
+
+bb1:
+  %tmp1 = getelementptr inbounds %struct3, %struct3* %tmp, i64 %tmp19, i32 1
+  %tmp11 = getelementptr inbounds %struct4, %struct4* %tmp1, i64 0, i32 0, i32 0
+  store i32 0, i32* %tmp11, align 4
+  br label %bb3
+
+bb2:
+  %tmp2 = getelementptr inbounds %struct3, %struct3* %tmp, i64 %tmp20, i32 1
+  %tmp12 = getelementptr inbounds %struct4, %struct4* %tmp2, i64 0, i32 0, i32 1
+  store i32 0, i32* %tmp12, align 4
+  br label %bb3
+
+bb3:
+  %phi = phi %struct4* [ %tmp1, %bb1 ], [ %tmp2, %bb2 ]
+  %tmp22 = invoke i32 @foo1(i32 11) to label %bb4 unwind label %bb5
+
+bb4:
+  ret i32 0
+
+bb5:
+  %tmp27 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) catch i8* bitcast (i8** @_ZTIi to i8*)
+  %tmp34 = getelementptr inbounds %struct4, %struct4* %phi, i64 %tmp21, i32 1
+  %tmp35 = getelementptr inbounds %struct2, %struct2* %tmp34, i64 0, i32 1
+  %tmp25 = load i32, i32* %tmp35, align 4
+  ret i32 %tmp25
+
+; CHECK-LABEL: @test3(
+; CHECK: bb5:
+; CHECK-NEXT: {{.*}}landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+}
+
+@_ZTIi = external constant i8*
+declare i32 @__gxx_personality_v0(...)
+declare i32 @foo1(i32)
+
+
+; Check that instcombine doesn't fold GEPs into themselves through a loop
+; back-edge.
+
+define i8* @test4(i32 %value, i8* %buffer) {
+entry:
+  %incptr = getelementptr inbounds i8, i8* %buffer, i64 1
+  %cmp = icmp ugt i32 %value, 127
+  br i1 %cmp, label %loop.header, label %exit
+
+loop.header:
+  br label %loop.body
+
+loop.body:
+  %loopptr = phi i8* [ %incptr, %loop.header ], [ %incptr2, %loop.body ]
+  %newval = phi i32 [ %value, %loop.header ], [ %shr, %loop.body ]
+  %shr = lshr i32 %newval, 7
+  %incptr2 = getelementptr inbounds i8, i8* %loopptr, i64 1
+  %cmp2 = icmp ugt i32 %shr, 127
+  br i1 %cmp2, label %loop.body, label %loop.exit
+
+loop.exit:
+  %exitptr = phi i8* [ %incptr2, %loop.body ]
+  br label %exit
+
+exit:
+  %ptr2 = phi i8* [ %exitptr, %loop.exit ], [ %incptr, %entry ]
+  %incptr3 = getelementptr inbounds i8, i8* %ptr2, i64 1
+  ret i8* %incptr3
+
+; CHECK-LABEL: @test4(
+; CHECK: loop.body:
+; CHECK: getelementptr{{.*}}i64 1
+; CHECK: exit:
 }
diff --git a/test/Transforms/InstCombine/getelementptr.ll b/test/Transforms/InstCombine/getelementptr.ll
index 94cc1803073a..276ada91f3c6 100644
--- a/test/Transforms/InstCombine/getelementptr.ll
+++ b/test/Transforms/InstCombine/getelementptr.ll
@@ -14,14 +14,14 @@ target datalayout = "e-p:64:64-p1:16:16-p2:32:32:32-p3:64:64:64"
 
 ; Test noop elimination
 define i32* @test1(i32* %I) {
-        %A = getelementptr i32* %I, i64 0
+        %A = getelementptr i32, i32* %I, i64 0
         ret i32* %A
 ; CHECK-LABEL: @test1(
 ; CHECK: ret i32* %I
 }
 
 define i32 addrspace(1)* @test1_as1(i32 addrspace(1)* %I) {
-  %A = getelementptr i32 addrspace(1)* %I, i64 0
+  %A = getelementptr i32, i32 addrspace(1)* %I, i64 0
   ret i32 addrspace(1)* %A
 ; CHECK-LABEL: @test1_as1(
 ; CHECK: ret i32 addrspace(1)* %I
@@ -29,7 +29,7 @@ define i32 addrspace(1)* @test1_as1(i32 addrspace(1)* %I) {
 
 ; Test noop elimination
 define i32* @test2(i32* %I) {
-        %A = getelementptr i32* %I
+        %A = getelementptr i32, i32* %I
         ret i32* %A
 ; CHECK-LABEL: @test2(
 ; CHECK: ret i32* %I
@@ -37,38 +37,38 @@ define i32* @test2(i32* %I) {
 
 ; Test that two array indexing geps fold
 define i32* @test3(i32* %I) {
-        %A = getelementptr i32* %I, i64 17
-        %B = getelementptr i32* %A, i64 4
+        %A = getelementptr i32, i32* %I, i64 17
+        %B = getelementptr i32, i32* %A, i64 4
         ret i32* %B
 ; CHECK-LABEL: @test3(
-; CHECK: getelementptr i32* %I, i64 21
+; CHECK: getelementptr i32, i32* %I, i64 21
 }
 
 ; Test that two getelementptr insts fold
 define i32* @test4({ i32 }* %I) {
-        %A = getelementptr { i32 }* %I, i64 1
-        %B = getelementptr { i32 }* %A, i64 0, i32 0
+        %A = getelementptr { i32 }, { i32 }* %I, i64 1
+        %B = getelementptr { i32 }, { i32 }* %A, i64 0, i32 0
         ret i32* %B
 ; CHECK-LABEL: @test4(
-; CHECK: getelementptr { i32 }* %I, i64 1, i32 0
+; CHECK: getelementptr { i32 }, { i32 }* %I, i64 1, i32 0
 }
 
 define void @test5(i8 %B) {
         ; This should be turned into a constexpr instead of being an instruction
-        %A = getelementptr [10 x i8]* @Global, i64 0, i64 4
+        %A = getelementptr [10 x i8], [10 x i8]* @Global, i64 0, i64 4
         store i8 %B, i8* %A
         ret void
 ; CHECK-LABEL: @test5(
-; CHECK: store i8 %B, i8* getelementptr inbounds ([10 x i8]* @Global, i64 0, i64 4)
+; CHECK: store i8 %B, i8* getelementptr inbounds ([10 x i8], [10 x i8]* @Global, i64 0, i64 4)
 }
 
 define void @test5_as1(i8 %B) {
         ; This should be turned into a constexpr instead of being an instruction
-        %A = getelementptr [10 x i8] addrspace(1)* @Global_as1, i16 0, i16 4
+        %A = getelementptr [10 x i8], [10 x i8] addrspace(1)* @Global_as1, i16 0, i16 4
         store i8 %B, i8 addrspace(1)* %A
         ret void
 ; CHECK-LABEL: @test5_as1(
-; CHECK: store i8 %B, i8 addrspace(1)* getelementptr inbounds ([10 x i8] addrspace(1)* @Global_as1, i16 0, i16 4)
+; CHECK: store i8 %B, i8 addrspace(1)* getelementptr inbounds ([10 x i8], [10 x i8] addrspace(1)* @Global_as1, i16 0, i16 4)
 }
 
 %as1_ptr_struct = type { i32 addrspace(1)* }
@@ -80,9 +80,9 @@ define void @test5_as1(i8 %B) {
 ; This should be turned into a constexpr instead of being an instruction
 define void @test_evaluate_gep_nested_as_ptrs(i32 addrspace(2)* %B) {
 ; CHECK-LABEL: @test_evaluate_gep_nested_as_ptrs(
-; CHECK-NEXT: store i32 addrspace(2)* %B, i32 addrspace(2)* addrspace(1)* getelementptr inbounds (%as2_ptr_struct addrspace(1)* @global_as1_as2_ptr, i16 0, i32 0), align 8
+; CHECK-NEXT: store i32 addrspace(2)* %B, i32 addrspace(2)* addrspace(1)* getelementptr inbounds (%as2_ptr_struct, %as2_ptr_struct addrspace(1)* @global_as1_as2_ptr, i16 0, i32 0), align 8
 ; CHECK-NEXT: ret void
-  %A = getelementptr %as2_ptr_struct addrspace(1)* @global_as1_as2_ptr, i16 0, i32 0
+  %A = getelementptr %as2_ptr_struct, %as2_ptr_struct addrspace(1)* @global_as1_as2_ptr, i16 0, i32 0
   store i32 addrspace(2)* %B, i32 addrspace(2)* addrspace(1)* %A
   ret void
 }
@@ -91,26 +91,26 @@ define void @test_evaluate_gep_nested_as_ptrs(i32 addrspace(2)* %B) {
 
 define void @test_evaluate_gep_as_ptrs_array(i8 addrspace(2)* %B) {
 ; CHECK-LABEL: @test_evaluate_gep_as_ptrs_array(
-; CHECK-NEXT: store i8 addrspace(2)* %B, i8 addrspace(2)* addrspace(1)* getelementptr inbounds ([4 x i8 addrspace(2)*] addrspace(1)* @arst, i16 0, i16 2), align 4
+; CHECK-NEXT: store i8 addrspace(2)* %B, i8 addrspace(2)* addrspace(1)* getelementptr inbounds ([4 x i8 addrspace(2)*], [4 x i8 addrspace(2)*] addrspace(1)* @arst, i16 0, i16 2), align 4
 
 ; CHECK-NEXT: ret void
-  %A = getelementptr [4 x i8 addrspace(2)*] addrspace(1)* @arst, i16 0, i16 2
+  %A = getelementptr [4 x i8 addrspace(2)*], [4 x i8 addrspace(2)*] addrspace(1)* @arst, i16 0, i16 2
   store i8 addrspace(2)* %B, i8 addrspace(2)* addrspace(1)* %A
   ret void
 }
 
 define i32* @test7(i32* %I, i64 %C, i64 %D) {
-        %A = getelementptr i32* %I, i64 %C
-        %B = getelementptr i32* %A, i64 %D
+        %A = getelementptr i32, i32* %I, i64 %C
+        %B = getelementptr i32, i32* %A, i64 %D
         ret i32* %B
 ; CHECK-LABEL: @test7(
-; CHECK: %A.sum = add i64 %C, %D
-; CHECK: getelementptr i32* %I, i64 %A.sum
+; CHECK: %A = getelementptr i32, i32* %I, i64 %C
+; CHECK: %B = getelementptr i32, i32* %A, i64 %D
 }
 
 define i8* @test8([10 x i32]* %X) {
         ;; Fold into the cast.
-        %A = getelementptr [10 x i32]* %X, i64 0, i64 0
+        %A = getelementptr [10 x i32], [10 x i32]* %X, i64 0, i64 0
         %B = bitcast i32* %A to i8*
         ret i8* %B
 ; CHECK-LABEL: @test8(
@@ -118,7 +118,7 @@ define i8* @test8([10 x i32]* %X) {
 }
 
 define i32 @test9() {
-        %A = getelementptr { i32, double }* null, i32 0, i32 1
+        %A = getelementptr { i32, double }, { i32, double }* null, i32 0, i32 1
         %B = ptrtoint double* %A to i32
         ret i32 %B
 ; CHECK-LABEL: @test9(
@@ -126,8 +126,8 @@ define i32 @test9() {
 }
 
 define i1 @test10({ i32, i32 }* %x, { i32, i32 }* %y) {
-        %tmp.1 = getelementptr { i32, i32 }* %x, i32 0, i32 1
-        %tmp.3 = getelementptr { i32, i32 }* %y, i32 0, i32 1
+        %tmp.1 = getelementptr { i32, i32 }, { i32, i32 }* %x, i32 0, i32 1
+        %tmp.3 = getelementptr { i32, i32 }, { i32, i32 }* %y, i32 0, i32 1
         ;; seteq x, y
         %tmp.4 = icmp eq i32* %tmp.1, %tmp.3
         ret i1 %tmp.4
@@ -136,7 +136,7 @@ define i1 @test10({ i32, i32 }* %x, { i32, i32 }* %y) {
 }
 
 define i1 @test11({ i32, i32 }* %X) {
-        %P = getelementptr { i32, i32 }* %X, i32 0, i32 0
+        %P = getelementptr { i32, i32 }, { i32, i32 }* %X, i32 0, i32 0
         %Q = icmp eq i32* %P, null
         ret i1 %Q
 ; CHECK-LABEL: @test11(
@@ -147,18 +147,18 @@ define i1 @test11({ i32, i32 }* %X) {
 ; PR4748
 define i32 @test12(%struct.A* %a) {
 entry:
-  %g3 = getelementptr %struct.A* %a, i32 0, i32 1
+  %g3 = getelementptr %struct.A, %struct.A* %a, i32 0, i32 1
   store i32 10, i32* %g3, align 4
 
-  %g4 = getelementptr %struct.A* %a, i32 0, i32 0
+  %g4 = getelementptr %struct.A, %struct.A* %a, i32 0, i32 0
 
   %new_a = bitcast %struct.B* %g4 to %struct.A*
 
-  %g5 = getelementptr %struct.A* %new_a, i32 0, i32 1
-  %a_a = load i32* %g5, align 4
+  %g5 = getelementptr %struct.A, %struct.A* %new_a, i32 0, i32 1
+  %a_a = load i32, i32* %g5, align 4
   ret i32 %a_a
 ; CHECK-LABEL:      @test12(
-; CHECK:      getelementptr %struct.A* %a, i64 0, i32 1
+; CHECK:      getelementptr %struct.A, %struct.A* %a, i64 0, i32 1
 ; CHECK-NEXT: store i32 10, i32* %g3
 ; CHECK-NEXT: ret i32 10
 }
@@ -167,8 +167,8 @@ entry:
 ; PR2235
 %S = type { i32, [ 100 x i32] }
 define i1 @test13(i64 %X, %S* %P) {
-        %A = getelementptr inbounds %S* %P, i32 0, i32 1, i64 %X
-        %B = getelementptr inbounds %S* %P, i32 0, i32 0
+        %A = getelementptr inbounds %S, %S* %P, i32 0, i32 1, i64 %X
+        %B = getelementptr inbounds %S, %S* %P, i32 0, i32 0
 	%C = icmp eq i32* %A, %B
 	ret i1 %C
 ; CHECK-LABEL: @test13(
@@ -180,8 +180,8 @@ define <2 x i1> @test13_vector(<2 x i64> %X, <2 x %S*> %P) nounwind {
 ; CHECK-NEXT: shl nuw <2 x i64> %X, <i64 2, i64 2>
 ; CHECK-NEXT: add <2 x i64> %A.idx, <i64 4, i64 4>
 ; CHECK-NEXT: icmp eq <2 x i64> %A.offs, zeroinitializer
-  %A = getelementptr inbounds <2 x %S*> %P, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 1>, <2 x i64> %X
-  %B = getelementptr inbounds <2 x %S*> %P, <2 x i64> <i64 0, i64 0>, <2 x i32> <i32 0, i32 0>
+  %A = getelementptr inbounds %S, <2 x %S*> %P, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 1>, <2 x i64> %X
+  %B = getelementptr inbounds %S, <2 x %S*> %P, <2 x i64> <i64 0, i64 0>, <2 x i32> <i32 0, i32 0>
   %C = icmp eq <2 x i32*> %A, %B
   ret <2 x i1> %C
 }
@@ -190,8 +190,8 @@ define i1 @test13_as1(i16 %X, %S addrspace(1)* %P) {
 ; CHECK-LABEL: @test13_as1(
 ; CHECK-NEXT:  %C = icmp eq i16 %X, -1
 ; CHECK-NEXT: ret i1 %C
-  %A = getelementptr inbounds %S addrspace(1)* %P, i16 0, i32 1, i16 %X
-  %B = getelementptr inbounds %S addrspace(1)* %P, i16 0, i32 0
+  %A = getelementptr inbounds %S, %S addrspace(1)* %P, i16 0, i32 1, i16 %X
+  %B = getelementptr inbounds %S, %S addrspace(1)* %P, i16 0, i32 0
   %C = icmp eq i32 addrspace(1)* %A, %B
   ret i1 %C
 }
@@ -202,8 +202,8 @@ define <2 x i1> @test13_vector_as1(<2 x i16> %X, <2 x %S addrspace(1)*> %P) {
 ; CHECK-NEXT: add <2 x i16> %A.idx, <i16 4, i16 4>
 ; CHECK-NEXT: icmp eq <2 x i16> %A.offs, zeroinitializer
 ; CHECK-NEXT: ret <2 x i1>
-  %A = getelementptr inbounds <2 x %S addrspace(1)*> %P, <2 x i16> <i16 0, i16 0>, <2 x i32> <i32 1, i32 1>, <2 x i16> %X
-  %B = getelementptr inbounds <2 x %S addrspace(1)*> %P, <2 x i16> <i16 0, i16 0>, <2 x i32> <i32 0, i32 0>
+  %A = getelementptr inbounds %S, <2 x %S addrspace(1)*> %P, <2 x i16> <i16 0, i16 0>, <2 x i32> <i32 1, i32 1>, <2 x i16> %X
+  %B = getelementptr inbounds %S, <2 x %S addrspace(1)*> %P, <2 x i16> <i16 0, i16 0>, <2 x i32> <i32 0, i32 0>
   %C = icmp eq <2 x i32 addrspace(1)*> %A, %B
   ret <2 x i1> %C
 }
@@ -211,8 +211,8 @@ define <2 x i1> @test13_vector_as1(<2 x i16> %X, <2 x %S addrspace(1)*> %P) {
 define i1 @test13_i32(i32 %X, %S* %P) {
 ; CHECK-LABEL: @test13_i32(
 ; CHECK: %C = icmp eq i32 %X, -1
-  %A = getelementptr inbounds %S* %P, i32 0, i32 1, i32 %X
-  %B = getelementptr inbounds %S* %P, i32 0, i32 0
+  %A = getelementptr inbounds %S, %S* %P, i32 0, i32 1, i32 %X
+  %B = getelementptr inbounds %S, %S* %P, i32 0, i32 0
   %C = icmp eq i32* %A, %B
   ret i1 %C
 }
@@ -220,8 +220,8 @@ define i1 @test13_i32(i32 %X, %S* %P) {
 define i1 @test13_i16(i16 %X, %S* %P) {
 ; CHECK-LABEL: @test13_i16(
 ; CHECK: %C = icmp eq i16 %X, -1
-  %A = getelementptr inbounds %S* %P, i16 0, i32 1, i16 %X
-  %B = getelementptr inbounds %S* %P, i16 0, i32 0
+  %A = getelementptr inbounds %S, %S* %P, i16 0, i32 1, i16 %X
+  %B = getelementptr inbounds %S, %S* %P, i16 0, i32 0
   %C = icmp eq i32* %A, %B
   ret i1 %C
 }
@@ -229,8 +229,8 @@ define i1 @test13_i16(i16 %X, %S* %P) {
 define i1 @test13_i128(i128 %X, %S* %P) {
 ; CHECK-LABEL: @test13_i128(
 ; CHECK: %C = icmp eq i64 %1, -1
-  %A = getelementptr inbounds %S* %P, i128 0, i32 1, i128 %X
-  %B = getelementptr inbounds %S* %P, i128 0, i32 0
+  %A = getelementptr inbounds %S, %S* %P, i128 0, i32 1, i128 %X
+  %B = getelementptr inbounds %S, %S* %P, i128 0, i32 0
   %C = icmp eq i32* %A, %B
   ret i1 %C
 }
@@ -239,25 +239,25 @@ define i1 @test13_i128(i128 %X, %S* %P) {
 @G = external global [3 x i8]
 define i8* @test14(i32 %Idx) {
         %idx = zext i32 %Idx to i64
-        %tmp = getelementptr i8* getelementptr ([3 x i8]* @G, i32 0, i32 0), i64 %idx
+        %tmp = getelementptr i8, i8* getelementptr ([3 x i8], [3 x i8]* @G, i32 0, i32 0), i64 %idx
         ret i8* %tmp
 ; CHECK-LABEL: @test14(
-; CHECK: getelementptr [3 x i8]* @G, i64 0, i64 %idx
+; CHECK: getelementptr [3 x i8], [3 x i8]* @G, i64 0, i64 %idx
 }
 
 
 ; Test folding of constantexpr geps into normal geps.
 @Array = external global [40 x i32]
 define i32 *@test15(i64 %X) {
-        %A = getelementptr i32* getelementptr ([40 x i32]* @Array, i64 0, i64 0), i64 %X
+        %A = getelementptr i32, i32* getelementptr ([40 x i32], [40 x i32]* @Array, i64 0, i64 0), i64 %X
         ret i32* %A
 ; CHECK-LABEL: @test15(
-; CHECK: getelementptr [40 x i32]* @Array, i64 0, i64 %X
+; CHECK: getelementptr [40 x i32], [40 x i32]* @Array, i64 0, i64 %X
 }
 
 
 define i32* @test16(i32* %X, i32 %Idx) {
-        %R = getelementptr i32* %X, i32 %Idx
+        %R = getelementptr i32, i32* %X, i32 %Idx
         ret i32* %R
 ; CHECK-LABEL: @test16(
 ; CHECK: sext i32 %Idx to i64
@@ -265,8 +265,8 @@ define i32* @test16(i32* %X, i32 %Idx) {
 
 
 define i1 @test17(i16* %P, i32 %I, i32 %J) {
-        %X = getelementptr inbounds i16* %P, i32 %I
-        %Y = getelementptr inbounds i16* %P, i32 %J
+        %X = getelementptr inbounds i16, i16* %P, i32 %I
+        %Y = getelementptr inbounds i16, i16* %P, i32 %J
         %C = icmp ult i16* %X, %Y
         ret i1 %C
 ; CHECK-LABEL: @test17(
@@ -274,7 +274,7 @@ define i1 @test17(i16* %P, i32 %I, i32 %J) {
 }
 
 define i1 @test18(i16* %P, i32 %I) {
-        %X = getelementptr inbounds i16* %P, i32 %I
+        %X = getelementptr inbounds i16, i16* %P, i32 %I
         %C = icmp ult i16* %X, %P
         ret i1 %C
 ; CHECK-LABEL: @test18(
@@ -287,7 +287,7 @@ define i1 @test18_as1(i16 addrspace(1)* %P, i32 %I) {
 ; CHECK-NEXT: %1 = trunc i32 %I to i16
 ; CHECK-NEXT: %C = icmp slt i16 %1, 0
 ; CHECK-NEXT: ret i1 %C
-  %X = getelementptr inbounds i16 addrspace(1)* %P, i32 %I
+  %X = getelementptr inbounds i16, i16 addrspace(1)* %P, i32 %I
   %C = icmp ult i16 addrspace(1)* %X, %P
   ret i1 %C
 }
@@ -298,7 +298,7 @@ define i1 @test18_as1_i32(i16 addrspace(1)* %P, i32 %I) {
 ; CHECK-NEXT: %1 = trunc i32 %I to i16
 ; CHECK-NEXT: %C = icmp slt i16 %1, 0
 ; CHECK-NEXT: ret i1 %C
-  %X = getelementptr inbounds i16 addrspace(1)* %P, i32 %I
+  %X = getelementptr inbounds i16, i16 addrspace(1)* %P, i32 %I
   %C = icmp ult i16 addrspace(1)* %X, %P
   ret i1 %C
 }
@@ -307,7 +307,7 @@ define i1 @test18_as1_i32(i16 addrspace(1)* %P, i32 %I) {
 define i1 @test18_i16(i16* %P, i16 %I) {
 ; CHECK-LABEL: @test18_i16(
 ; CHECK: %C = icmp slt i16 %I, 0
-  %X = getelementptr inbounds i16* %P, i16 %I
+  %X = getelementptr inbounds i16, i16* %P, i16 %I
   %C = icmp ult i16* %X, %P
   ret i1 %C
 }
@@ -316,7 +316,7 @@ define i1 @test18_i16(i16* %P, i16 %I) {
 define i1 @test18_i64(i16* %P, i64 %I) {
 ; CHECK-LABEL: @test18_i64(
 ; CHECK: %C = icmp slt i64 %I, 0
-  %X = getelementptr inbounds i16* %P, i64 %I
+  %X = getelementptr inbounds i16, i16* %P, i64 %I
   %C = icmp ult i16* %X, %P
   ret i1 %C
 }
@@ -325,14 +325,14 @@ define i1 @test18_i64(i16* %P, i64 %I) {
 define i1 @test18_i128(i16* %P, i128 %I) {
 ; CHECK-LABEL: @test18_i128(
 ; CHECK: %C = icmp slt i64 %1, 0
-  %X = getelementptr inbounds i16* %P, i128 %I
+  %X = getelementptr inbounds i16, i16* %P, i128 %I
   %C = icmp ult i16* %X, %P
   ret i1 %C
 }
 
 define i32 @test19(i32* %P, i32 %A, i32 %B) {
-        %tmp.4 = getelementptr inbounds i32* %P, i32 %A
-        %tmp.9 = getelementptr inbounds i32* %P, i32 %B
+        %tmp.4 = getelementptr inbounds i32, i32* %P, i32 %A
+        %tmp.9 = getelementptr inbounds i32, i32* %P, i32 %B
         %tmp.10 = icmp eq i32* %tmp.4, %tmp.9
         %tmp.11 = zext i1 %tmp.10 to i32
         ret i32 %tmp.11
@@ -341,7 +341,7 @@ define i32 @test19(i32* %P, i32 %A, i32 %B) {
 }
 
 define i32 @test20(i32* %P, i32 %A, i32 %B) {
-        %tmp.4 = getelementptr inbounds i32* %P, i32 %A
+        %tmp.4 = getelementptr inbounds i32, i32* %P, i32 %A
         %tmp.6 = icmp eq i32* %tmp.4, %P
         %tmp.7 = zext i1 %tmp.6 to i32
         ret i32 %tmp.7
@@ -350,7 +350,7 @@ define i32 @test20(i32* %P, i32 %A, i32 %B) {
 }
 
 define i32 @test20_as1(i32 addrspace(1)* %P, i32 %A, i32 %B) {
-  %tmp.4 = getelementptr inbounds i32 addrspace(1)* %P, i32 %A
+  %tmp.4 = getelementptr inbounds i32, i32 addrspace(1)* %P, i32 %A
   %tmp.6 = icmp eq i32 addrspace(1)* %tmp.4, %P
   %tmp.7 = zext i1 %tmp.6 to i32
   ret i32 %tmp.7
@@ -361,12 +361,12 @@ define i32 @test20_as1(i32 addrspace(1)* %P, i32 %A, i32 %B) {
 
 define i32 @test21() {
         %pbob1 = alloca %intstruct
-        %pbob2 = getelementptr %intstruct* %pbob1
-        %pbobel = getelementptr %intstruct* %pbob2, i64 0, i32 0
-        %rval = load i32* %pbobel
+        %pbob2 = getelementptr %intstruct, %intstruct* %pbob1
+        %pbobel = getelementptr %intstruct, %intstruct* %pbob2, i64 0, i32 0
+        %rval = load i32, i32* %pbobel
         ret i32 %rval
 ; CHECK-LABEL: @test21(
-; CHECK: getelementptr %intstruct* %pbob1, i64 0, i32 0
+; CHECK: getelementptr %intstruct, %intstruct* %pbob1, i64 0, i32 0
 }
 
 
@@ -374,18 +374,18 @@ define i32 @test21() {
 @B = global i32 2               ; <i32*> [#uses=1]
 
 define i1 @test22() {
-        %C = icmp ult i32* getelementptr (i32* @A, i64 1),
-                           getelementptr (i32* @B, i64 2)
+        %C = icmp ult i32* getelementptr (i32, i32* @A, i64 1),
+                           getelementptr (i32, i32* @B, i64 2)
         ret i1 %C
 ; CHECK-LABEL: @test22(
-; CHECK: icmp ult (i32* getelementptr inbounds (i32* @A, i64 1), i32* getelementptr (i32* @B, i64 2))
+; CHECK: icmp ult (i32* getelementptr inbounds (i32, i32* @A, i64 1), i32* getelementptr (i32, i32* @B, i64 2))
 }
 
 
 %X = type { [10 x i32], float }
 
 define i1 @test23() {
-        %A = getelementptr %X* null, i64 0, i32 0, i64 0                ; <i32*> [#uses=1]
+        %A = getelementptr %X, %X* null, i64 0, i32 0, i64 0                ; <i32*> [#uses=1]
         %B = icmp ne i32* %A, null              ; <i1> [#uses=1]
         ret i1 %B
 ; CHECK-LABEL: @test23(
@@ -394,9 +394,9 @@ define i1 @test23() {
 
 define void @test25() {
 entry:
-        %tmp = getelementptr { i64, i64, i64, i64 }* null, i32 0, i32 3         ; <i64*> [#uses=1]
-        %tmp.upgrd.1 = load i64* %tmp           ; <i64> [#uses=1]
-        %tmp8.ui = load i64* null               ; <i64> [#uses=1]
+        %tmp = getelementptr { i64, i64, i64, i64 }, { i64, i64, i64, i64 }* null, i32 0, i32 3         ; <i64*> [#uses=1]
+        %tmp.upgrd.1 = load i64, i64* %tmp           ; <i64> [#uses=1]
+        %tmp8.ui = load i64, i64* null               ; <i64> [#uses=1]
         %tmp8 = bitcast i64 %tmp8.ui to i64             ; <i64> [#uses=1]
         %tmp9 = and i64 %tmp8, %tmp.upgrd.1             ; <i64> [#uses=1]
         %sext = trunc i64 %tmp9 to i32          ; <i32> [#uses=1]
@@ -411,8 +411,8 @@ declare void @foo25(i32, i64)
 
 ; PR1637
 define i1 @test26(i8* %arr) {
-        %X = getelementptr i8* %arr, i32 1
-        %Y = getelementptr i8* %arr, i32 1
+        %X = getelementptr i8, i8* %arr, i32 1
+        %Y = getelementptr i8, i8* %arr, i32 1
         %test = icmp uge i8* %X, %Y
         ret i1 %test
 ; CHECK-LABEL: @test26(
@@ -427,14 +427,14 @@ define i1 @test26(i8* %arr) {
 define i32 @test27(%struct.compat_siginfo* %to, %struct.siginfo_t* %from) {
 entry:
 	%from_addr = alloca %struct.siginfo_t*
-	%tmp344 = load %struct.siginfo_t** %from_addr, align 8
-	%tmp345 = getelementptr %struct.siginfo_t* %tmp344, i32 0, i32 3
-	%tmp346 = getelementptr { { i32, i32, [0 x i8], %struct.sigval_t, i32 }, [88 x i8] }* %tmp345, i32 0, i32 0
+	%tmp344 = load %struct.siginfo_t*, %struct.siginfo_t** %from_addr, align 8
+	%tmp345 = getelementptr %struct.siginfo_t, %struct.siginfo_t* %tmp344, i32 0, i32 3
+	%tmp346 = getelementptr { { i32, i32, [0 x i8], %struct.sigval_t, i32 }, [88 x i8] }, { { i32, i32, [0 x i8], %struct.sigval_t, i32 }, [88 x i8] }* %tmp345, i32 0, i32 0
 	%tmp346347 = bitcast { i32, i32, [0 x i8], %struct.sigval_t, i32 }* %tmp346 to { i32, i32, %struct.sigval_t }*
-	%tmp348 = getelementptr { i32, i32, %struct.sigval_t }* %tmp346347, i32 0, i32 2
-	%tmp349 = getelementptr %struct.sigval_t* %tmp348, i32 0, i32 0
+	%tmp348 = getelementptr { i32, i32, %struct.sigval_t }, { i32, i32, %struct.sigval_t }* %tmp346347, i32 0, i32 2
+	%tmp349 = getelementptr %struct.sigval_t, %struct.sigval_t* %tmp348, i32 0, i32 0
 	%tmp349350 = bitcast i8** %tmp349 to i32*
-	%tmp351 = load i32* %tmp349350, align 8
+	%tmp351 = load i32, i32* %tmp349350, align 8
 	%tmp360 = call i32 asm sideeffect "...",
         "=r,ir,*m,i,0,~{dirflag},~{fpsr},~{flags}"( i32 %tmp351,
          %struct.__large_struct* null, i32 -14, i32 0 )
@@ -450,17 +450,17 @@ entry:
 define i32 @test28() nounwind  {
 entry:
 	%orientations = alloca [1 x [1 x %struct.x]]
-	%tmp3 = call i32 @puts( i8* getelementptr ([6 x i8]* @.str, i32 0, i32 0) ) nounwind
-	%tmp45 = getelementptr inbounds [1 x [1 x %struct.x]]* %orientations, i32 1, i32 0, i32 0
-	%orientations62 = getelementptr [1 x [1 x %struct.x]]* %orientations, i32 0, i32 0, i32 0
+	%tmp3 = call i32 @puts( i8* getelementptr ([6 x i8], [6 x i8]* @.str, i32 0, i32 0) ) nounwind
+	%tmp45 = getelementptr inbounds [1 x [1 x %struct.x]], [1 x [1 x %struct.x]]* %orientations, i32 1, i32 0, i32 0
+	%orientations62 = getelementptr [1 x [1 x %struct.x]], [1 x [1 x %struct.x]]* %orientations, i32 0, i32 0, i32 0
 	br label %bb10
 
 bb10:
 	%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb10 ]
 	%tmp.0.reg2mem.0.rec = mul i32 %indvar, -1
 	%tmp12.rec = add i32 %tmp.0.reg2mem.0.rec, -1
-	%tmp12 = getelementptr inbounds %struct.x* %tmp45, i32 %tmp12.rec
-	%tmp16 = call i32 (i8*, ...)* @printf( i8* getelementptr ([12 x i8]* @.str1, i32 0, i32 0), %struct.x* %tmp12 ) nounwind
+	%tmp12 = getelementptr inbounds %struct.x, %struct.x* %tmp45, i32 %tmp12.rec
+	%tmp16 = call i32 (i8*, ...) @printf( i8* getelementptr ([12 x i8], [12 x i8]* @.str1, i32 0, i32 0), %struct.x* %tmp12 ) nounwind
 	%tmp84 = icmp eq %struct.x* %tmp12, %orientations62
 	%indvar.next = add i32 %indvar, 1
 	br i1 %tmp84, label %bb17, label %bb10
@@ -482,12 +482,12 @@ declare i32 @printf(i8*, ...)
 	%T = type <{ i64, i64, i64 }>
 define i32 @test29(i8* %start, i32 %X) nounwind {
 entry:
-	%tmp3 = load i64* null
-	%add.ptr = getelementptr i8* %start, i64 %tmp3
-	%tmp158 = load i32* null
-	%add.ptr159 = getelementptr %T* null, i32 %tmp158
-	%add.ptr209 = getelementptr i8* %start, i64 0
-	%add.ptr212 = getelementptr i8* %add.ptr209, i32 %X
+	%tmp3 = load i64, i64* null
+	%add.ptr = getelementptr i8, i8* %start, i64 %tmp3
+	%tmp158 = load i32, i32* null
+	%add.ptr159 = getelementptr %T, %T* null, i32 %tmp158
+	%add.ptr209 = getelementptr i8, i8* %start, i64 0
+	%add.ptr212 = getelementptr i8, i8* %add.ptr209, i32 %X
 	%cmp214 = icmp ugt i8* %add.ptr212, %add.ptr
 	br i1 %cmp214, label %if.then216, label %if.end363
 
@@ -506,8 +506,8 @@ entry:
 	%0 = alloca i32, i32 %n, align 4
 	%1 = bitcast i32* %0 to [0 x i32]*
 	call void @test30f(i32* %0) nounwind
-	%2 = getelementptr [0 x i32]* %1, i32 0, i32 %m
-	%3 = load i32* %2, align 4
+	%2 = getelementptr [0 x i32], [0 x i32]* %1, i32 0, i32 %m
+	%3 = load i32, i32* %2, align 4
 	ret i32 %3
 ; CHECK-LABEL: @test30(
 ; CHECK: getelementptr i32
@@ -518,8 +518,8 @@ declare void @test30f(i32*)
 
 
 define i1 @test31(i32* %A) {
-        %B = getelementptr i32* %A, i32 1
-        %C = getelementptr i32* %A, i64 1
+        %B = getelementptr i32, i32* %A, i32 1
+        %C = getelementptr i32, i32* %A, i64 1
         %V = icmp eq i32* %B, %C
         ret i1 %V
 ; CHECK-LABEL: @test31(
@@ -530,18 +530,18 @@ define i1 @test31(i32* %A) {
 ; PR1345
 define i8* @test32(i8* %v) {
 	%A = alloca [4 x i8*], align 16
-	%B = getelementptr [4 x i8*]* %A, i32 0, i32 0
+	%B = getelementptr [4 x i8*], [4 x i8*]* %A, i32 0, i32 0
 	store i8* null, i8** %B
 	%C = bitcast [4 x i8*]* %A to { [16 x i8] }*
-	%D = getelementptr { [16 x i8] }* %C, i32 0, i32 0, i32 8
+	%D = getelementptr { [16 x i8] }, { [16 x i8] }* %C, i32 0, i32 0, i32 8
 	%E = bitcast i8* %D to i8**
 	store i8* %v, i8** %E
-	%F = getelementptr [4 x i8*]* %A, i32 0, i32 2
-	%G = load i8** %F
+	%F = getelementptr [4 x i8*], [4 x i8*]* %A, i32 0, i32 2
+	%G = load i8*, i8** %F
 	ret i8* %G
 ; CHECK-LABEL: @test32(
-; CHECK: %D = getelementptr [4 x i8*]* %A, i64 0, i64 1
-; CHECK: %F = getelementptr [4 x i8*]* %A, i64 0, i64 2
+; CHECK: %D = getelementptr [4 x i8*], [4 x i8*]* %A, i64 0, i64 1
+; CHECK: %F = getelementptr [4 x i8*], [4 x i8*]* %A, i64 0, i64 2
 }
 
 ; PR3290
@@ -550,44 +550,44 @@ define i8* @test32(i8* %v) {
 
 define i32* @test33(%struct.Key* %A) {
 ; CHECK-LABEL: @test33(
-; CHECK: getelementptr %struct.Key* %A, i64 0, i32 0, i32 1
+; CHECK: getelementptr %struct.Key, %struct.Key* %A, i64 0, i32 0, i32 1
   %B = bitcast %struct.Key* %A to %struct.anon*
-  %C = getelementptr %struct.anon* %B, i32 0, i32 2
+  %C = getelementptr %struct.anon, %struct.anon* %B, i32 0, i32 2
   ret i32* %C
 }
 
 define i32 addrspace(1)* @test33_as1(%struct.Key addrspace(1)* %A) {
 ; CHECK-LABEL: @test33_as1(
-; CHECK: getelementptr %struct.Key addrspace(1)* %A, i16 0, i32 0, i32 1
+; CHECK: getelementptr %struct.Key, %struct.Key addrspace(1)* %A, i16 0, i32 0, i32 1
   %B = bitcast %struct.Key addrspace(1)* %A to %struct.anon addrspace(1)*
-  %C = getelementptr %struct.anon addrspace(1)* %B, i32 0, i32 2
+  %C = getelementptr %struct.anon, %struct.anon addrspace(1)* %B, i32 0, i32 2
   ret i32 addrspace(1)* %C
 }
 
 define i32 addrspace(1)* @test33_array_as1([10 x i32] addrspace(1)* %A) {
 ; CHECK-LABEL: @test33_array_as1(
-; CHECK: getelementptr [10 x i32] addrspace(1)* %A, i16 0, i16 2
+; CHECK: getelementptr [10 x i32], [10 x i32] addrspace(1)* %A, i16 0, i16 2
   %B = bitcast [10 x i32] addrspace(1)* %A to [5 x i32] addrspace(1)*
-  %C = getelementptr [5 x i32] addrspace(1)* %B, i32 0, i32 2
+  %C = getelementptr [5 x i32], [5 x i32] addrspace(1)* %B, i32 0, i32 2
   ret i32 addrspace(1)* %C
 }
 
 ; Make sure the GEP indices use the right pointer sized integer
 define i32 addrspace(1)* @test33_array_struct_as1([10 x %struct.Key] addrspace(1)* %A) {
 ; CHECK-LABEL: @test33_array_struct_as1(
-; CHECK: getelementptr [10 x %struct.Key] addrspace(1)* %A, i16 0, i16 1, i32 0, i32 0
+; CHECK: getelementptr [10 x %struct.Key], [10 x %struct.Key] addrspace(1)* %A, i16 0, i16 1, i32 0, i32 0
   %B = bitcast [10 x %struct.Key] addrspace(1)* %A to [20 x i32] addrspace(1)*
-  %C = getelementptr [20 x i32] addrspace(1)* %B, i32 0, i32 2
+  %C = getelementptr [20 x i32], [20 x i32] addrspace(1)* %B, i32 0, i32 2
   ret i32 addrspace(1)* %C
 }
 
 define i32 addrspace(1)* @test33_addrspacecast(%struct.Key* %A) {
 ; CHECK-LABEL: @test33_addrspacecast(
-; CHECK: %C = getelementptr %struct.Key* %A, i64 0, i32 0, i32 1
+; CHECK: %C = getelementptr %struct.Key, %struct.Key* %A, i64 0, i32 0, i32 1
 ; CHECK-NEXT: addrspacecast i32* %C to i32 addrspace(1)*
 ; CHECK-NEXT: ret
   %B = addrspacecast %struct.Key* %A to %struct.anon addrspace(1)*
-  %C = getelementptr %struct.anon addrspace(1)* %B, i32 0, i32 2
+  %C = getelementptr %struct.anon, %struct.anon addrspace(1)* %B, i32 0, i32 2
   ret i32 addrspace(1)* %C
 }
 
@@ -596,10 +596,10 @@ define i8* @test34(i8* %Val, i64 %V) nounwind {
 entry:
 	%A = alloca %T2, align 8
 	%mrv_gep = bitcast %T2* %A to i64*
-	%B = getelementptr %T2* %A, i64 0, i32 0
+	%B = getelementptr %T2, %T2* %A, i64 0, i32 0
 
       	store i64 %V, i64* %mrv_gep
-	%C = load i8** %B, align 8
+	%C = load i8*, i8** %B, align 8
 	ret i8* %C
 ; CHECK-LABEL: @test34(
 ; CHECK: %[[C:.*]] = inttoptr i64 %V to i8*
@@ -617,11 +617,11 @@ entry:
 ; Instcombine should be able to fold this getelementptr.
 
 define i32 @test35() nounwind {
-  call i32 (i8*, ...)* @printf(i8* getelementptr ([17 x i8]* @"\01LC8", i32 0, i32 0),
-             i8* getelementptr (%t1* bitcast (%t0* @s to %t1*), i32 0, i32 1, i32 0)) nounwind
+  call i32 (i8*, ...) @printf(i8* getelementptr ([17 x i8], [17 x i8]* @"\01LC8", i32 0, i32 0),
+             i8* getelementptr (%t1, %t1* bitcast (%t0* @s to %t1*), i32 0, i32 1, i32 0)) nounwind
   ret i32 0
 ; CHECK-LABEL: @test35(
-; CHECK: call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @"\01LC8", i64 0, i64 0), i8* getelementptr inbounds (%t0* @s, i64 0, i32 1, i64 0)) [[NUW:#[0-9]+]]
+; CHECK: call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @"\01LC8", i64 0, i64 0), i8* getelementptr inbounds (%t0, %t0* @s, i64 0, i32 1, i64 0)) [[NUW:#[0-9]+]]
 }
 
 ; Instcombine should constant-fold the GEP so that indices that have
@@ -630,9 +630,9 @@ define i32 @test35() nounwind {
 ; the same address is computed, but 3 is in the range of [0,11).
 
 define i8* @test36() nounwind {
-  ret i8* getelementptr ([11 x i8]* @array, i32 0, i64 -1)
+  ret i8* getelementptr ([11 x i8], [11 x i8]* @array, i32 0, i64 -1)
 ; CHECK-LABEL: @test36(
-; CHECK: ret i8* getelementptr ([11 x i8]* @array, i64 1676976733973595601, i64 4)
+; CHECK: ret i8* getelementptr ([11 x i8], [11 x i8]* @array, i64 1676976733973595601, i64 4)
 }
 
 ; Instcombine shouldn't assume that gep(A,0,1) != gep(A,1,0).
@@ -640,18 +640,18 @@ define i8* @test36() nounwind {
 define i1 @test37() nounwind {
 ; CHECK-LABEL: @test37(
 ; CHECK: ret i1 true
-  %t = icmp eq i8* getelementptr ([1 x i8]* @A37, i64 0, i64 1),
-                   getelementptr ([1 x i8]* @A37, i64 1, i64 0)
+  %t = icmp eq i8* getelementptr ([1 x i8], [1 x i8]* @A37, i64 0, i64 1),
+                   getelementptr ([1 x i8], [1 x i8]* @A37, i64 1, i64 0)
   ret i1 %t
 }
 
 ; Test index promotion
 define i32* @test38(i32* %I, i32 %n) {
-        %A = getelementptr i32* %I, i32 %n
+        %A = getelementptr i32, i32* %I, i32 %n
         ret i32* %A
 ; CHECK-LABEL: @test38(
 ; CHECK: = sext i32 %n to i64
-; CHECK: %A = getelementptr i32* %I, i64 %
+; CHECK: %A = getelementptr i32, i32* %I, i64 %
 }
 
 ; Test that we don't duplicate work when the second gep is a "bitcast".
@@ -660,14 +660,14 @@ declare void @pr10322_f2(%pr10322_t*)
 declare void @pr10322_f3(i8**)
 define void @pr10322_f1(%pr10322_t* %foo) {
 entry:
-  %arrayidx8 = getelementptr inbounds %pr10322_t* %foo, i64 2
+  %arrayidx8 = getelementptr inbounds %pr10322_t, %pr10322_t* %foo, i64 2
   call void @pr10322_f2(%pr10322_t* %arrayidx8) nounwind
-  %tmp2 = getelementptr inbounds %pr10322_t* %arrayidx8, i64 0, i32 0
+  %tmp2 = getelementptr inbounds %pr10322_t, %pr10322_t* %arrayidx8, i64 0, i32 0
   call void @pr10322_f3(i8** %tmp2) nounwind
   ret void
 
 ; CHECK-LABEL: @pr10322_f1(
-; CHECK: %tmp2 = getelementptr inbounds %pr10322_t* %arrayidx8, i64 0, i32 0
+; CHECK: %tmp2 = getelementptr inbounds %pr10322_t, %pr10322_t* %arrayidx8, i64 0, i32 0
 }
 
 ; Test that we combine the last two geps in this sequence, before we
@@ -676,14 +676,14 @@ entry:
 %three_gep_t2 = type {%three_gep_t}
 
 define void @three_gep_f(%three_gep_t2* %x) {
-  %gep1 = getelementptr %three_gep_t2* %x, i64 2
+  %gep1 = getelementptr %three_gep_t2, %three_gep_t2* %x, i64 2
   call void @three_gep_h(%three_gep_t2* %gep1)
-  %gep2 = getelementptr %three_gep_t2* %gep1, i64 0, i32 0
-  %gep3 = getelementptr %three_gep_t* %gep2, i64 0, i32 0
+  %gep2 = getelementptr %three_gep_t2, %three_gep_t2* %gep1, i64 0, i32 0
+  %gep3 = getelementptr %three_gep_t, %three_gep_t* %gep2, i64 0, i32 0
   call void @three_gep_g(i32* %gep3)
 
 ; CHECK-LABEL: @three_gep_f(
-; CHECK: %gep3 = getelementptr %three_gep_t2* %gep1, i64 0, i32 0, i32 0
+; CHECK: %gep3 = getelementptr %three_gep_t2, %three_gep_t2* %gep1, i64 0, i32 0, i32 0
   ret void
 }
 
@@ -694,21 +694,21 @@ declare void @three_gep_h(%three_gep_t2*)
 %struct.zot = type { i64, i8 }
 
 define void @test39(%struct.ham* %arg, i8 %arg1) nounwind {
-  %tmp = getelementptr inbounds %struct.ham* %arg, i64 0, i32 2
-  %tmp2 = load %struct.zot** %tmp, align 8
+  %tmp = getelementptr inbounds %struct.ham, %struct.ham* %arg, i64 0, i32 2
+  %tmp2 = load %struct.zot*, %struct.zot** %tmp, align 8
   %tmp3 = bitcast %struct.zot* %tmp2 to i8*
-  %tmp4 = getelementptr inbounds i8* %tmp3, i64 -8
+  %tmp4 = getelementptr inbounds i8, i8* %tmp3, i64 -8
   store i8 %arg1, i8* %tmp4, align 8
   ret void
 
 ; CHECK-LABEL: @test39(
-; CHECK: getelementptr inbounds %struct.ham* %arg, i64 0, i32 2
-; CHECK: getelementptr inbounds i8* %{{.+}}, i64 -8
+; CHECK: getelementptr inbounds %struct.ham, %struct.ham* %arg, i64 0, i32 2
+; CHECK: getelementptr inbounds i8, i8* %{{.+}}, i64 -8
 }
 
 define i1 @pr16483([1 x i8]* %a, [1 x i8]* %b) {
-  %c = getelementptr [1 x i8]* %a, i32 0, i32 0
-  %d = getelementptr [1 x i8]* %b, i32 0, i32 0
+  %c = getelementptr [1 x i8], [1 x i8]* %a, i32 0, i32 0
+  %d = getelementptr [1 x i8], [1 x i8]* %b, i32 0, i32 0
   %cmp = icmp ult i8* %c, %d
   ret i1 %cmp
 
@@ -718,82 +718,82 @@ define i1 @pr16483([1 x i8]* %a, [1 x i8]* %b) {
 
 define i8 @test_gep_bitcast_as1(i32 addrspace(1)* %arr, i16 %N) {
 ; CHECK-LABEL: @test_gep_bitcast_as1(
-; CHECK: getelementptr i32 addrspace(1)* %arr, i16 %N
+; CHECK: getelementptr i32, i32 addrspace(1)* %arr, i16 %N
 ; CHECK: bitcast
   %cast = bitcast i32 addrspace(1)* %arr to i8 addrspace(1)*
   %V = mul i16 %N, 4
-  %t = getelementptr i8 addrspace(1)* %cast, i16 %V
-  %x = load i8 addrspace(1)* %t
+  %t = getelementptr i8, i8 addrspace(1)* %cast, i16 %V
+  %x = load i8, i8 addrspace(1)* %t
   ret i8 %x
 }
 
 ; The element size of the array matches the element size of the pointer
 define i64 @test_gep_bitcast_array_same_size_element([100 x double]* %arr, i64 %N) {
 ; CHECK-LABEL: @test_gep_bitcast_array_same_size_element(
-; CHECK: getelementptr [100 x double]* %arr, i64 0, i64 %V
+; CHECK: getelementptr [100 x double], [100 x double]* %arr, i64 0, i64 %V
 ; CHECK: bitcast
   %cast = bitcast [100 x double]* %arr to i64*
   %V = mul i64 %N, 8
-  %t = getelementptr i64* %cast, i64 %V
-  %x = load i64* %t
+  %t = getelementptr i64, i64* %cast, i64 %V
+  %x = load i64, i64* %t
   ret i64 %x
 }
 
 ; gep should be done in the original address space.
 define i64 @test_gep_bitcast_array_same_size_element_addrspacecast([100 x double]* %arr, i64 %N) {
 ; CHECK-LABEL: @test_gep_bitcast_array_same_size_element_addrspacecast(
-; CHECK: getelementptr [100 x double]* %arr, i64 0, i64 %V
+; CHECK: getelementptr [100 x double], [100 x double]* %arr, i64 0, i64 %V
 ; CHECK-NEXT: bitcast double*
 ; CHECK-NEXT: %t = addrspacecast i64*
-; CHECK: load i64 addrspace(3)* %t
+; CHECK: load i64, i64 addrspace(3)* %t
   %cast = addrspacecast [100 x double]* %arr to i64 addrspace(3)*
   %V = mul i64 %N, 8
-  %t = getelementptr i64 addrspace(3)* %cast, i64 %V
-  %x = load i64 addrspace(3)* %t
+  %t = getelementptr i64, i64 addrspace(3)* %cast, i64 %V
+  %x = load i64, i64 addrspace(3)* %t
   ret i64 %x
 }
 
 ; The element size of the array is different the element size of the pointer
 define i8 @test_gep_bitcast_array_different_size_element([100 x double]* %arr, i64 %N) {
 ; CHECK-LABEL: @test_gep_bitcast_array_different_size_element(
-; CHECK: getelementptr [100 x double]* %arr, i64 0, i64 %N
+; CHECK: getelementptr [100 x double], [100 x double]* %arr, i64 0, i64 %N
 ; CHECK: bitcast
   %cast = bitcast [100 x double]* %arr to i8*
   %V = mul i64 %N, 8
-  %t = getelementptr i8* %cast, i64 %V
-  %x = load i8* %t
+  %t = getelementptr i8, i8* %cast, i64 %V
+  %x = load i8, i8* %t
   ret i8 %x
 }
 
 define i64 @test_gep_bitcast_array_same_size_element_as1([100 x double] addrspace(1)* %arr, i16 %N) {
 ; CHECK-LABEL: @test_gep_bitcast_array_same_size_element_as1(
-; CHECK: getelementptr [100 x double] addrspace(1)* %arr, i16 0, i16 %V
+; CHECK: getelementptr [100 x double], [100 x double] addrspace(1)* %arr, i16 0, i16 %V
 ; CHECK: bitcast
   %cast = bitcast [100 x double] addrspace(1)* %arr to i64 addrspace(1)*
   %V = mul i16 %N, 8
-  %t = getelementptr i64 addrspace(1)* %cast, i16 %V
-  %x = load i64 addrspace(1)* %t
+  %t = getelementptr i64, i64 addrspace(1)* %cast, i16 %V
+  %x = load i64, i64 addrspace(1)* %t
   ret i64 %x
 }
 
 define i8 @test_gep_bitcast_array_different_size_element_as1([100 x double] addrspace(1)* %arr, i16 %N) {
 ; CHECK-LABEL: @test_gep_bitcast_array_different_size_element_as1(
-; CHECK: getelementptr [100 x double] addrspace(1)* %arr, i16 0, i16 %N
+; CHECK: getelementptr [100 x double], [100 x double] addrspace(1)* %arr, i16 0, i16 %N
 ; CHECK: bitcast
   %cast = bitcast [100 x double] addrspace(1)* %arr to i8 addrspace(1)*
   %V = mul i16 %N, 8
-  %t = getelementptr i8 addrspace(1)* %cast, i16 %V
-  %x = load i8 addrspace(1)* %t
+  %t = getelementptr i8, i8 addrspace(1)* %cast, i16 %V
+  %x = load i8, i8 addrspace(1)* %t
   ret i8 %x
 }
 
 define i64 @test40() {
   %array = alloca [3 x i32], align 4
-  %gep = getelementptr inbounds [3 x i32]* %array, i64 0, i64 2
+  %gep = getelementptr inbounds [3 x i32], [3 x i32]* %array, i64 0, i64 2
   %gepi8 = bitcast i32* %gep to i8*
   %p = ptrtoint [3 x i32]* %array to i64
   %np = sub i64 0, %p
-  %gep2 = getelementptr i8* %gepi8, i64 %np
+  %gep2 = getelementptr i8, i8* %gepi8, i64 %np
   %ret = ptrtoint i8* %gep2 to i64
   ret i64 %ret
 
@@ -802,11 +802,11 @@ define i64 @test40() {
 }
 
 define i16 @test41([3 x i32] addrspace(1)* %array) {
-  %gep = getelementptr inbounds [3 x i32] addrspace(1)* %array, i16 0, i16 2
+  %gep = getelementptr inbounds [3 x i32], [3 x i32] addrspace(1)* %array, i16 0, i16 2
   %gepi8 = bitcast i32 addrspace(1)* %gep to i8 addrspace(1)*
   %p = ptrtoint [3 x i32] addrspace(1)* %array to i16
   %np = sub i16 0, %p
-  %gep2 = getelementptr i8 addrspace(1)* %gepi8, i16 %np
+  %gep2 = getelementptr i8, i8 addrspace(1)* %gepi8, i16 %np
   %ret = ptrtoint i8 addrspace(1)* %gep2 to i16
   ret i16 %ret
 
@@ -817,7 +817,7 @@ define i16 @test41([3 x i32] addrspace(1)* %array) {
 define i8* @test42(i8* %c1, i8* %c2) {
   %ptrtoint = ptrtoint i8* %c1 to i64
   %sub = sub i64 0, %ptrtoint
-  %gep = getelementptr inbounds i8* %c2, i64 %sub
+  %gep = getelementptr inbounds i8, i8* %c2, i64 %sub
   ret i8* %gep
 
 ; CHECK-LABEL: @test42(
@@ -832,7 +832,7 @@ define i16* @test43(i16* %c1, i16* %c2) {
   %ptrtoint = ptrtoint i16* %c1 to i64
   %sub = sub i64 0, %ptrtoint
   %shr = ashr i64 %sub, 1
-  %gep = getelementptr inbounds i16* %c2, i64 %shr
+  %gep = getelementptr inbounds i16, i16* %c2, i64 %shr
   ret i16* %gep
 
 ; CHECK-LABEL: @test43(
@@ -847,7 +847,7 @@ define %struct.C* @test44(%struct.C* %c1, %struct.C* %c2) {
   %ptrtoint = ptrtoint %struct.C* %c1 to i64
   %sub = sub i64 0, %ptrtoint
   %shr = sdiv i64 %sub, 7
-  %gep = getelementptr inbounds %struct.C* %c2, i64 %shr
+  %gep = getelementptr inbounds %struct.C, %struct.C* %c2, i64 %shr
   ret %struct.C* %gep
 
 ; CHECK-LABEL: @test44(
@@ -863,7 +863,7 @@ define %struct.C* @test45(%struct.C* %c1, %struct.C** %c2) {
   %ptrtoint2 = ptrtoint %struct.C** %c2 to i64
   %sub = sub i64 %ptrtoint2, %ptrtoint1 ; C2 - C1
   %shr = sdiv i64 %sub, 7
-  %gep = getelementptr inbounds %struct.C* %c1, i64 %shr ; C1 + (C2 - C1)
+  %gep = getelementptr inbounds %struct.C, %struct.C* %c1, i64 %shr ; C1 + (C2 - C1)
   ret %struct.C* %gep
 
 ; CHECK-LABEL: @test45(
@@ -875,14 +875,14 @@ define %struct.C* @test46(%struct.C* %c1, %struct.C* %c2, i64 %N) {
   %ptrtoint = ptrtoint %struct.C* %c1 to i64
   %sub = sub i64 0, %ptrtoint
   %sdiv = sdiv i64 %sub, %N
-  %gep = getelementptr inbounds %struct.C* %c2, i64 %sdiv
+  %gep = getelementptr inbounds %struct.C, %struct.C* %c2, i64 %sdiv
   ret %struct.C* %gep
 
 ; CHECK-LABEL: @test46(
 ; CHECK-NEXT:  [[PTRTOINT:%.*]] = ptrtoint %struct.C* %c1 to i64
 ; CHECK-NEXT:  [[SUB:%.*]] = sub i64 0, [[PTRTOINT]]
 ; CHECK-NEXT:  [[SDIV:%.*]] = sdiv i64 [[SUB]], %N
-; CHECK-NEXT:  [[GEP:%.*]] = getelementptr inbounds %struct.C* %c2, i64 %sdiv
+; CHECK-NEXT:  [[GEP:%.*]] = getelementptr inbounds %struct.C, %struct.C* %c2, i64 %sdiv
 ; CHECK-NEXT:  ret %struct.C* [[GEP]]
 }
 
@@ -890,7 +890,7 @@ define i32 addrspace(1)* @ascast_0_gep(i32* %p) nounwind {
 ; CHECK-LABEL: @ascast_0_gep(
 ; CHECK-NOT: getelementptr
 ; CHECK: ret
-  %gep = getelementptr i32* %p, i32 0
+  %gep = getelementptr i32, i32* %p, i32 0
   %x = addrspacecast i32* %gep to i32 addrspace(1)*
   ret i32 addrspace(1)* %x
 }
@@ -902,7 +902,7 @@ define i32 addrspace(1)* @ascast_0_0_gep([128 x i32]* %p) nounwind {
 ; CHECK-NEXT: getelementptr [128 x i32]
 ; CHECK-NEXT: addrspacecast i32*
 ; CHECK-NEXT: ret i32 addrspace(1)*
-  %gep = getelementptr [128 x i32]* %p, i32 0, i32 0
+  %gep = getelementptr [128 x i32], [128 x i32]* %p, i32 0, i32 0
   %x = addrspacecast i32* %gep to i32 addrspace(1)*
   ret i32 addrspace(1)* %x
 }
diff --git a/test/Transforms/InstCombine/icmp-range.ll b/test/Transforms/InstCombine/icmp-range.ll
index 0911ab03c601..041adf76b5e1 100644
--- a/test/Transforms/InstCombine/icmp-range.ll
+++ b/test/Transforms/InstCombine/icmp-range.ll
@@ -6,14 +6,14 @@
 define i1 @test_nonzero(i32* nocapture readonly %arg) {
 ; CHECK-LABEL:test_nonzero
 ; CHECK: ret i1 true
-  %val = load i32* %arg, !range !0
+  %val = load i32, i32* %arg, !range !0
   %rval = icmp ne i32 %val, 0
   ret i1 %rval
 }
 define i1 @test_nonzero2(i32* nocapture readonly %arg) {
 ; CHECK-LABEL:test_nonzero2
 ; CHECK: ret i1 false
-  %val = load i32* %arg, !range !0
+  %val = load i32, i32* %arg, !range !0
   %rval = icmp eq i32 %val, 0
   ret i1 %rval
 }
@@ -23,7 +23,7 @@ define i1 @test_nonzero3(i32* nocapture readonly %arg) {
 ; CHECK-LABEL: test_nonzero3
 ; Check that this does not trigger - it wouldn't be legal
 ; CHECK: icmp
-  %val = load i32* %arg, !range !1
+  %val = load i32, i32* %arg, !range !1
   %rval = icmp ne i32 %val, 0
   ret i1 %rval
 }
@@ -32,7 +32,7 @@ define i1 @test_nonzero3(i32* nocapture readonly %arg) {
 define i1 @test_nonzero4(i8* nocapture readonly %arg) {
 ; CHECK-LABEL: test_nonzero4
 ; CHECK: ret i1 false
-  %val = load i8* %arg, !range !2
+  %val = load i8, i8* %arg, !range !2
   %rval = icmp ne i8 %val, 0
   ret i1 %rval
 }
@@ -40,7 +40,7 @@ define i1 @test_nonzero4(i8* nocapture readonly %arg) {
 define i1 @test_nonzero5(i8* nocapture readonly %arg) {
 ; CHECK-LABEL: test_nonzero5
 ; CHECK: ret i1 false
-  %val = load i8* %arg, !range !2
+  %val = load i8, i8* %arg, !range !2
   %rval = icmp ugt i8 %val, 0
   ret i1 %rval
 }
@@ -49,7 +49,7 @@ define i1 @test_nonzero5(i8* nocapture readonly %arg) {
 define i1 @test_nonzero6(i8* %argw) {
 ; CHECK-LABEL: test_nonzero6
 ; CHECK: icmp ne i8 %val, 0
-  %val = load i8* %argw, !range !3
+  %val = load i8, i8* %argw, !range !3
   %rval = icmp sgt i8 %val, 0
   ret i1 %rval
 }
diff --git a/test/Transforms/InstCombine/icmp.ll b/test/Transforms/InstCombine/icmp.ll
index 64741c5712eb..edcf76d5a7d2 100644
--- a/test/Transforms/InstCombine/icmp.ll
+++ b/test/Transforms/InstCombine/icmp.ll
@@ -244,8 +244,8 @@ define i1 @test23(i32 %x) nounwind {
 ; CHECK:    %cmp = icmp eq i64 %i, 1000
 ; CHECK:   ret i1 %cmp
 define i1 @test24(i64 %i) {
-  %p1 = getelementptr inbounds i32* getelementptr inbounds ([1000 x i32]* @X, i64 0, i64 0), i64 %i
-  %cmp = icmp eq i32* %p1, getelementptr inbounds ([1000 x i32]* @X, i64 1, i64 0)
+  %p1 = getelementptr inbounds i32, i32* getelementptr inbounds ([1000 x i32], [1000 x i32]* @X, i64 0, i64 0), i64 %i
+  %cmp = icmp eq i32* %p1, getelementptr inbounds ([1000 x i32], [1000 x i32]* @X, i64 1, i64 0)
   ret i1 %cmp
 }
 
@@ -256,8 +256,8 @@ define i1 @test24(i64 %i) {
 ; CHECK: %cmp = icmp eq i16 %1, 1000
 ; CHECK: ret i1 %cmp
 define i1 @test24_as1(i64 %i) {
-  %p1 = getelementptr inbounds i32 addrspace(1)* getelementptr inbounds ([1000 x i32] addrspace(1)* @X_as1, i64 0, i64 0), i64 %i
-  %cmp = icmp eq i32 addrspace(1)* %p1, getelementptr inbounds ([1000 x i32] addrspace(1)* @X_as1, i64 1, i64 0)
+  %p1 = getelementptr inbounds i32, i32 addrspace(1)* getelementptr inbounds ([1000 x i32], [1000 x i32] addrspace(1)* @X_as1, i64 0, i64 0), i64 %i
+  %cmp = icmp eq i32 addrspace(1)* %p1, getelementptr inbounds ([1000 x i32], [1000 x i32] addrspace(1)* @X_as1, i64 1, i64 0)
   ret i1 %cmp
 }
 
@@ -619,8 +619,8 @@ declare i32 @test58_d(i64)
 
 define i1 @test59(i8* %foo) {
   %bit = bitcast i8* %foo to i32*
-  %gep1 = getelementptr inbounds i32* %bit, i64 2
-  %gep2 = getelementptr inbounds i8* %foo, i64 10
+  %gep1 = getelementptr inbounds i32, i32* %bit, i64 2
+  %gep2 = getelementptr inbounds i8, i8* %foo, i64 10
   %cast1 = bitcast i32* %gep1 to i8*
   %cmp = icmp ult i8* %cast1, %gep2
   %use = ptrtoint i8* %cast1 to i64
@@ -632,23 +632,23 @@ define i1 @test59(i8* %foo) {
 
 define i1 @test59_as1(i8 addrspace(1)* %foo) {
   %bit = bitcast i8 addrspace(1)* %foo to i32 addrspace(1)*
-  %gep1 = getelementptr inbounds i32 addrspace(1)* %bit, i64 2
-  %gep2 = getelementptr inbounds i8 addrspace(1)* %foo, i64 10
+  %gep1 = getelementptr inbounds i32, i32 addrspace(1)* %bit, i64 2
+  %gep2 = getelementptr inbounds i8, i8 addrspace(1)* %foo, i64 10
   %cast1 = bitcast i32 addrspace(1)* %gep1 to i8 addrspace(1)*
   %cmp = icmp ult i8 addrspace(1)* %cast1, %gep2
   %use = ptrtoint i8 addrspace(1)* %cast1 to i64
   %call = call i32 @test58_d(i64 %use) nounwind
   ret i1 %cmp
 ; CHECK: @test59_as1
-; CHECK: %[[GEP:.+]] = getelementptr inbounds i8 addrspace(1)* %foo, i16 8
+; CHECK: %[[GEP:.+]] = getelementptr inbounds i8, i8 addrspace(1)* %foo, i16 8
 ; CHECK: ptrtoint i8 addrspace(1)* %[[GEP]] to i16
 ; CHECK: ret i1 true
 }
 
 define i1 @test60(i8* %foo, i64 %i, i64 %j) {
   %bit = bitcast i8* %foo to i32*
-  %gep1 = getelementptr inbounds i32* %bit, i64 %i
-  %gep2 = getelementptr inbounds i8* %foo, i64 %j
+  %gep1 = getelementptr inbounds i32, i32* %bit, i64 %i
+  %gep2 = getelementptr inbounds i8, i8* %foo, i64 %j
   %cast1 = bitcast i32* %gep1 to i8*
   %cmp = icmp ult i8* %cast1, %gep2
   ret i1 %cmp
@@ -660,8 +660,8 @@ define i1 @test60(i8* %foo, i64 %i, i64 %j) {
 
 define i1 @test60_as1(i8 addrspace(1)* %foo, i64 %i, i64 %j) {
   %bit = bitcast i8 addrspace(1)* %foo to i32 addrspace(1)*
-  %gep1 = getelementptr inbounds i32 addrspace(1)* %bit, i64 %i
-  %gep2 = getelementptr inbounds i8 addrspace(1)* %foo, i64 %j
+  %gep1 = getelementptr inbounds i32, i32 addrspace(1)* %bit, i64 %i
+  %gep2 = getelementptr inbounds i8, i8 addrspace(1)* %foo, i64 %j
   %cast1 = bitcast i32 addrspace(1)* %gep1 to i8 addrspace(1)*
   %cmp = icmp ult i8 addrspace(1)* %cast1, %gep2
   ret i1 %cmp
@@ -677,8 +677,8 @@ define i1 @test60_as1(i8 addrspace(1)* %foo, i64 %i, i64 %j) {
 ; bitcast. This uses the same sized addrspace.
 define i1 @test60_addrspacecast(i8* %foo, i64 %i, i64 %j) {
   %bit = addrspacecast i8* %foo to i32 addrspace(3)*
-  %gep1 = getelementptr inbounds i32 addrspace(3)* %bit, i64 %i
-  %gep2 = getelementptr inbounds i8* %foo, i64 %j
+  %gep1 = getelementptr inbounds i32, i32 addrspace(3)* %bit, i64 %i
+  %gep2 = getelementptr inbounds i8, i8* %foo, i64 %j
   %cast1 = addrspacecast i32 addrspace(3)* %gep1 to i8*
   %cmp = icmp ult i8* %cast1, %gep2
   ret i1 %cmp
@@ -690,8 +690,8 @@ define i1 @test60_addrspacecast(i8* %foo, i64 %i, i64 %j) {
 
 define i1 @test60_addrspacecast_smaller(i8* %foo, i16 %i, i64 %j) {
   %bit = addrspacecast i8* %foo to i32 addrspace(1)*
-  %gep1 = getelementptr inbounds i32 addrspace(1)* %bit, i16 %i
-  %gep2 = getelementptr inbounds i8* %foo, i64 %j
+  %gep1 = getelementptr inbounds i32, i32 addrspace(1)* %bit, i16 %i
+  %gep2 = getelementptr inbounds i8, i8* %foo, i64 %j
   %cast1 = addrspacecast i32 addrspace(1)* %gep1 to i8*
   %cmp = icmp ult i8* %cast1, %gep2
   ret i1 %cmp
@@ -704,8 +704,8 @@ define i1 @test60_addrspacecast_smaller(i8* %foo, i16 %i, i64 %j) {
 
 define i1 @test60_addrspacecast_larger(i8 addrspace(1)* %foo, i32 %i, i16 %j) {
   %bit = addrspacecast i8 addrspace(1)* %foo to i32 addrspace(2)*
-  %gep1 = getelementptr inbounds i32 addrspace(2)* %bit, i32 %i
-  %gep2 = getelementptr inbounds i8 addrspace(1)* %foo, i16 %j
+  %gep1 = getelementptr inbounds i32, i32 addrspace(2)* %bit, i32 %i
+  %gep2 = getelementptr inbounds i8, i8 addrspace(1)* %foo, i16 %j
   %cast1 = addrspacecast i32 addrspace(2)* %gep1 to i8 addrspace(1)*
   %cmp = icmp ult i8 addrspace(1)* %cast1, %gep2
   ret i1 %cmp
@@ -718,8 +718,8 @@ define i1 @test60_addrspacecast_larger(i8 addrspace(1)* %foo, i32 %i, i16 %j) {
 
 define i1 @test61(i8* %foo, i64 %i, i64 %j) {
   %bit = bitcast i8* %foo to i32*
-  %gep1 = getelementptr i32* %bit, i64 %i
-  %gep2 = getelementptr  i8* %foo, i64 %j
+  %gep1 = getelementptr i32, i32* %bit, i64 %i
+  %gep2 = getelementptr  i8,  i8* %foo, i64 %j
   %cast1 = bitcast i32* %gep1 to i8*
   %cmp = icmp ult i8* %cast1, %gep2
   ret i1 %cmp
@@ -731,8 +731,8 @@ define i1 @test61(i8* %foo, i64 %i, i64 %j) {
 
 define i1 @test61_as1(i8 addrspace(1)* %foo, i16 %i, i16 %j) {
   %bit = bitcast i8 addrspace(1)* %foo to i32 addrspace(1)*
-  %gep1 = getelementptr i32 addrspace(1)* %bit, i16 %i
-  %gep2 = getelementptr i8 addrspace(1)* %foo, i16 %j
+  %gep1 = getelementptr i32, i32 addrspace(1)* %bit, i16 %i
+  %gep2 = getelementptr i8, i8 addrspace(1)* %foo, i16 %j
   %cast1 = bitcast i32 addrspace(1)* %gep1 to i8 addrspace(1)*
   %cmp = icmp ult i8 addrspace(1)* %cast1, %gep2
   ret i1 %cmp
@@ -743,8 +743,8 @@ define i1 @test61_as1(i8 addrspace(1)* %foo, i16 %i, i16 %j) {
 }
 
 define i1 @test62(i8* %a) {
-  %arrayidx1 = getelementptr inbounds i8* %a, i64 1
-  %arrayidx2 = getelementptr inbounds i8* %a, i64 10
+  %arrayidx1 = getelementptr inbounds i8, i8* %a, i64 1
+  %arrayidx2 = getelementptr inbounds i8, i8* %a, i64 10
   %cmp = icmp slt i8* %arrayidx1, %arrayidx2
   ret i1 %cmp
 ; CHECK-LABEL: @test62(
@@ -754,8 +754,8 @@ define i1 @test62(i8* %a) {
 define i1 @test62_as1(i8 addrspace(1)* %a) {
 ; CHECK-LABEL: @test62_as1(
 ; CHECK-NEXT: ret i1 true
-  %arrayidx1 = getelementptr inbounds i8 addrspace(1)* %a, i64 1
-  %arrayidx2 = getelementptr inbounds i8 addrspace(1)* %a, i64 10
+  %arrayidx1 = getelementptr inbounds i8, i8 addrspace(1)* %a, i64 1
+  %arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %a, i64 10
   %cmp = icmp slt i8 addrspace(1)* %arrayidx1, %arrayidx2
   ret i1 %cmp
 }
@@ -1115,8 +1115,8 @@ define i1 @icmp_add_and_shr_ne_0(i32 %X) {
 ; CHECK-LABEL: define i1 @test71(
 ; CHECK-NEXT: ret i1 false
 define i1 @test71(i8* %x) {
-  %a = getelementptr i8* %x, i64 8
-  %b = getelementptr inbounds i8* %x, i64 8
+  %a = getelementptr i8, i8* %x, i64 8
+  %b = getelementptr inbounds i8, i8* %x, i64 8
   %c = icmp ugt i8* %a, %b
   ret i1 %c
 }
@@ -1124,8 +1124,8 @@ define i1 @test71(i8* %x) {
 define i1 @test71_as1(i8 addrspace(1)* %x) {
 ; CHECK-LABEL: @test71_as1(
 ; CHECK-NEXT: ret i1 false
-  %a = getelementptr i8 addrspace(1)* %x, i64 8
-  %b = getelementptr inbounds i8 addrspace(1)* %x, i64 8
+  %a = getelementptr i8, i8 addrspace(1)* %x, i64 8
+  %b = getelementptr inbounds i8, i8 addrspace(1)* %x, i64 8
   %c = icmp ugt i8 addrspace(1)* %a, %b
   ret i1 %c
 }
@@ -1573,3 +1573,33 @@ define i32 @f5(i8 %a, i8 %b) {
   %sub7.sub = select i1 %cmp4, i32 %sub7, i32 %sub
   ret i32 %sub7.sub
 }
+
+; CHECK-LABEL: @f6
+; CHECK: %cmp.unshifted = xor i32 %a, %b
+; CHECK-NEXT: %cmp.mask = and i32 %cmp.unshifted, 255
+; CHECK-NEXT: %cmp = icmp eq i32 %cmp.mask, 0
+; CHECK-NEXT: %s = select i1 %cmp, i32 10000, i32 0
+; CHECK-NEXT: ret i32 %s
+define i32 @f6(i32 %a, i32 %b) {
+  %sext = shl i32 %a, 24
+  %conv = ashr i32 %sext, 24
+  %sext6 = shl i32 %b, 24
+  %conv4 = ashr i32 %sext6, 24
+  %cmp = icmp eq i32 %conv, %conv4
+  %s = select i1 %cmp, i32 10000, i32 0
+  ret i32 %s
+}
+
+; CHECK-LABEL: @f7
+; CHECK:   %cmp.unshifted = xor i32 %a, %b
+; CHECK-NEXT: %cmp.mask = and i32 %cmp.unshifted, 511
+; CHECK-NEXT: %cmp = icmp ne i32 %cmp.mask, 0
+; CHECK-NEXT: %s = select i1 %cmp, i32 10000, i32 0
+; CHECK-NEXT: ret i32 %s
+define i32 @f7(i32 %a, i32 %b) {
+  %sext = shl i32 %a, 23
+  %sext6 = shl i32 %b, 23
+  %cmp = icmp ne i32 %sext, %sext6
+  %s = select i1 %cmp, i32 10000, i32 0
+  ret i32 %s
+}
diff --git a/test/Transforms/InstCombine/inline-intrinsic-assert.ll b/test/Transforms/InstCombine/inline-intrinsic-assert.ll
new file mode 100644
index 000000000000..af34277563e0
--- /dev/null
+++ b/test/Transforms/InstCombine/inline-intrinsic-assert.ll
@@ -0,0 +1,30 @@
+; RUN: opt < %s -inline -instcombine -S | FileCheck %s
+
+; PR22857: http://llvm.org/bugs/show_bug.cgi?id=22857
+; The inliner should not add an edge to an intrinsic and
+; then assert that it did not add an edge to an intrinsic!
+
+define float @foo(float %f1) #0 {
+  %call = call float @bar(float %f1)
+  ret float %call
+
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: call float @llvm.fabs.f32
+; CHECK-NEXT: ret float
+}
+
+define float @bar(float %f1) #0 {
+  %call = call float @sqr(float %f1)
+  %call1 = call float @sqrtf(float %call) #0
+  ret float %call1
+}
+
+define float @sqr(float %f) #0 {
+  %mul = fmul fast float %f, %f
+  ret float %mul
+}
+
+declare float @sqrtf(float) #0
+
+attributes #0 = { "unsafe-fp-math"="true" }
+
diff --git a/test/Transforms/InstCombine/intrinsics.ll b/test/Transforms/InstCombine/intrinsics.ll
index 8e7742f8c34a..9767704c85cf 100644
--- a/test/Transforms/InstCombine/intrinsics.ll
+++ b/test/Transforms/InstCombine/intrinsics.ll
@@ -349,7 +349,8 @@ define i32 @ctlz_select(i32 %Value) nounwind {
   ret i32 %s
 
 ; CHECK-LABEL: @ctlz_select(
-; CHECK: select i1 %tobool, i32 %ctlz, i32 32
+; CHECK-NEXT: call i32 @llvm.ctlz.i32(i32 %Value, i1 false)
+; CHECK-NEXT: ret i32
 }
 
 define i32 @cttz_select(i32 %Value) nounwind {
@@ -359,5 +360,68 @@ define i32 @cttz_select(i32 %Value) nounwind {
   ret i32 %s
 
 ; CHECK-LABEL: @cttz_select(
-; CHECK: select i1 %tobool, i32 %cttz, i32 32
+; CHECK-NEXT: call i32 @llvm.cttz.i32(i32 %Value, i1 false)
+; CHECK-NEXT: ret i32
+}
+
+; CHECK-LABEL: @overflow_div_add(
+; CHECK: ret i1 false
+define i1 @overflow_div_add(i32 %v1, i32 %v2) nounwind {
+entry:
+  %div = sdiv i32 %v1, 2
+  %t = call %ov.result.32 @llvm.sadd.with.overflow.i32(i32 %div, i32 1)
+  %obit = extractvalue %ov.result.32 %t, 1
+  ret i1 %obit
+}
+
+; CHECK-LABEL: @overflow_div_sub(
+; CHECK: ret i1 false
+define i1 @overflow_div_sub(i32 %v1, i32 %v2) nounwind {
+entry:
+  ; Check cases where the known sign bits are larger than the word size.
+  %a = ashr i32 %v1, 18
+  %div = sdiv i32 %a, 65536
+  %t = call %ov.result.32 @llvm.ssub.with.overflow.i32(i32 %div, i32 1)
+  %obit = extractvalue %ov.result.32 %t, 1
+  ret i1 %obit
+}
+
+; CHECK-LABEL: @overflow_mod_mul(
+; CHECK: ret i1 false
+define i1 @overflow_mod_mul(i32 %v1, i32 %v2) nounwind {
+entry:
+  %rem = srem i32 %v1, 1000
+  %t = call %ov.result.32 @llvm.smul.with.overflow.i32(i32 %rem, i32 %rem)
+  %obit = extractvalue %ov.result.32 %t, 1
+  ret i1 %obit
+}
+
+; CHECK-LABEL: @overflow_mod_overflow_mul(
+; CHECK-NOT: ret i1 false
+define i1 @overflow_mod_overflow_mul(i32 %v1, i32 %v2) nounwind {
+entry:
+  %rem = srem i32 %v1, 65537
+  ; This may overflow because the result of the mul operands may be greater than 16bits
+  ; and the result greater than 32.
+  %t = call %ov.result.32 @llvm.smul.with.overflow.i32(i32 %rem, i32 %rem)
+  %obit = extractvalue %ov.result.32 %t, 1
+  ret i1 %obit
+}
+
+define %ov.result.32 @ssubtest_reorder(i8 %a) {
+  %A = sext i8 %a to i32
+  %x = call %ov.result.32 @llvm.ssub.with.overflow.i32(i32 0, i32 %A)
+  ret %ov.result.32 %x
+; CHECK-LABEL: @ssubtest_reorder
+; CHECK: %x = sub nsw i32 0, %A
+; CHECK-NEXT: %1 = insertvalue %ov.result.32 { i32 undef, i1 false }, i32 %x, 0
+; CHECK-NEXT:  ret %ov.result.32 %1
+}
+
+define %ov.result.32 @never_overflows_ssub_test0(i32 %a) {
+  %x = call %ov.result.32 @llvm.ssub.with.overflow.i32(i32 %a, i32 0)
+  ret %ov.result.32 %x
+; CHECK-LABEL: @never_overflows_ssub_test0
+; CHECK-NEXT: %[[x:.*]] = insertvalue %ov.result.32 { i32 undef, i1 false }, i32 %a, 0
+; CHECK-NEXT:  ret %ov.result.32 %[[x]]
 }
diff --git a/test/Transforms/InstCombine/invariant.ll b/test/Transforms/InstCombine/invariant.ll
index 383238022692..246f9e640417 100644
--- a/test/Transforms/InstCombine/invariant.ll
+++ b/test/Transforms/InstCombine/invariant.ll
@@ -11,6 +11,6 @@ define i8 @f() {
   %i = call {}* @llvm.invariant.start(i64 1, i8* %a) ; <{}*> [#uses=0]
   ; CHECK: call {}* @llvm.invariant.start
   call void @g(i8* %a)
-  %r = load i8* %a                                ; <i8> [#uses=1]
+  %r = load i8, i8* %a                                ; <i8> [#uses=1]
   ret i8 %r
 }
diff --git a/test/Transforms/InstCombine/known_align.ll b/test/Transforms/InstCombine/known_align.ll
index 0249951966dc..653c4c51e2da 100644
--- a/test/Transforms/InstCombine/known_align.ll
+++ b/test/Transforms/InstCombine/known_align.ll
@@ -11,17 +11,17 @@ entry:
 	%tmp = alloca i32, align 4		; <i32*> [#uses=2]
 	%tmp1 = alloca i32, align 4		; <i32*> [#uses=3]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
-	%tmp3 = load i32* getelementptr (%struct.p* @t, i32 0, i32 1), align 1		; <i32> [#uses=1]
+	%tmp3 = load i32, i32* getelementptr (%struct.p, %struct.p* @t, i32 0, i32 1), align 1		; <i32> [#uses=1]
 	store i32 %tmp3, i32* %tmp1, align 4
-	%tmp5 = load i32* %tmp1, align 4		; <i32> [#uses=1]
-	store i32 %tmp5, i32* getelementptr (%struct.p* @u, i32 0, i32 1), align 1
-	%tmp6 = load i32* %tmp1, align 4		; <i32> [#uses=1]
+	%tmp5 = load i32, i32* %tmp1, align 4		; <i32> [#uses=1]
+	store i32 %tmp5, i32* getelementptr (%struct.p, %struct.p* @u, i32 0, i32 1), align 1
+	%tmp6 = load i32, i32* %tmp1, align 4		; <i32> [#uses=1]
 	store i32 %tmp6, i32* %tmp, align 4
-	%tmp7 = load i32* %tmp, align 4		; <i32> [#uses=1]
+	%tmp7 = load i32, i32* %tmp, align 4		; <i32> [#uses=1]
 	store i32 %tmp7, i32* %retval, align 4
 	br label %return
 
 return:		; preds = %entry
-	%retval8 = load i32* %retval		; <i32> [#uses=1]
+	%retval8 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval8
 }
diff --git a/test/Transforms/InstCombine/load-cmp.ll b/test/Transforms/InstCombine/load-cmp.ll
index 98100263b48c..b0bfdc4c4c54 100644
--- a/test/Transforms/InstCombine/load-cmp.ll
+++ b/test/Transforms/InstCombine/load-cmp.ll
@@ -1,5 +1,4 @@
-; RUN: opt -instcombine -S < %s | FileCheck -check-prefix=NODL %s
-; RUN: opt -instcombine -S -default-data-layout="p:32:32:32-p1:16:16:16-n8:16:32:64" < %s | FileCheck -check-prefix=P32 %s
+; RUN: opt -instcombine -S -default-data-layout="p:32:32:32-p1:16:16:16-n8:16:32:64" < %s | FileCheck %s
 
 @G16 = internal constant [10 x i16] [i16 35, i16 82, i16 69, i16 81, i16 85,
                                      i16 73, i16 82, i16 69, i16 68, i16 0]
@@ -21,185 +20,137 @@
 
 
 define i1 @test1(i32 %X) {
-  %P = getelementptr inbounds [10 x i16]* @G16, i32 0, i32 %X
-  %Q = load i16* %P
+  %P = getelementptr inbounds [10 x i16], [10 x i16]* @G16, i32 0, i32 %X
+  %Q = load i16, i16* %P
   %R = icmp eq i16 %Q, 0
   ret i1 %R
-; NODL-LABEL: @test1(
-; NODL-NEXT: %R = icmp eq i32 %X, 9
-; NODL-NEXT: ret i1 %R
-
-; P32-LABEL: @test1(
-; P32-NEXT: %R = icmp eq i32 %X, 9
-; P32-NEXT: ret i1 %R
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: %R = icmp eq i32 %X, 9
+; CHECK-NEXT: ret i1 %R
 }
 
 define i1 @test1_noinbounds(i32 %X) {
-  %P = getelementptr [10 x i16]* @G16, i32 0, i32 %X
-  %Q = load i16* %P
+  %P = getelementptr [10 x i16], [10 x i16]* @G16, i32 0, i32 %X
+  %Q = load i16, i16* %P
   %R = icmp eq i16 %Q, 0
   ret i1 %R
-; NODL-LABEL: @test1_noinbounds(
-; NODL-NEXT: %P = getelementptr [10 x i16]* @G16, i32 0, i32 %X
-
-; P32-LABEL: @test1_noinbounds(
-; P32-NEXT: %R = icmp eq i32 %X, 9
-; P32-NEXT: ret i1 %R
+; CHECK-LABEL: @test1_noinbounds(
+; CHECK-NEXT: %R = icmp eq i32 %X, 9
+; CHECK-NEXT: ret i1 %R
 }
 
 define i1 @test1_noinbounds_i64(i64 %X) {
-  %P = getelementptr [10 x i16]* @G16, i64 0, i64 %X
-  %Q = load i16* %P
+  %P = getelementptr [10 x i16], [10 x i16]* @G16, i64 0, i64 %X
+  %Q = load i16, i16* %P
   %R = icmp eq i16 %Q, 0
   ret i1 %R
-; NODL-LABEL: @test1_noinbounds_i64(
-; NODL-NEXT: %P = getelementptr [10 x i16]* @G16, i64 0, i64 %X
-
-; P32-LABEL: @test1_noinbounds_i64(
-; P32: %R = icmp eq i32 %1, 9
-; P32-NEXT: ret i1 %R
+; CHECK-LABEL: @test1_noinbounds_i64(
+; CHECK: %R = icmp eq i32 %1, 9
+; CHECK-NEXT: ret i1 %R
 }
 
 define i1 @test1_noinbounds_as1(i32 %x) {
-  %p = getelementptr [10 x i16] addrspace(1)* @G16_as1, i16 0, i32 %x
-  %q = load i16 addrspace(1)* %p
+  %p = getelementptr [10 x i16], [10 x i16] addrspace(1)* @G16_as1, i16 0, i32 %x
+  %q = load i16, i16 addrspace(1)* %p
   %r = icmp eq i16 %q, 0
   ret i1 %r
 
-; P32-LABEL: @test1_noinbounds_as1(
-; P32-NEXT: trunc i32 %x to i16
-; P32-NEXT: %r = icmp eq i16 %1, 9
-; P32-NEXT: ret i1 %r
+; CHECK-LABEL: @test1_noinbounds_as1(
+; CHECK-NEXT: trunc i32 %x to i16
+; CHECK-NEXT: %r = icmp eq i16 %1, 9
+; CHECK-NEXT: ret i1 %r
 }
 
 define i1 @test2(i32 %X) {
-  %P = getelementptr inbounds [10 x i16]* @G16, i32 0, i32 %X
-  %Q = load i16* %P
+  %P = getelementptr inbounds [10 x i16], [10 x i16]* @G16, i32 0, i32 %X
+  %Q = load i16, i16* %P
   %R = icmp slt i16 %Q, 85
   ret i1 %R
-; NODL-LABEL: @test2(
-; NODL-NEXT: %R = icmp ne i32 %X, 4
-; NODL-NEXT: ret i1 %R
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:  %R = icmp ne i32 %X, 4
+; CHECK-NEXT:  ret i1 %R
 }
 
 define i1 @test3(i32 %X) {
-  %P = getelementptr inbounds [6 x double]* @GD, i32 0, i32 %X
-  %Q = load double* %P
+  %P = getelementptr inbounds [6 x double], [6 x double]* @GD, i32 0, i32 %X
+  %Q = load double, double* %P
   %R = fcmp oeq double %Q, 1.0
   ret i1 %R
-; NODL-LABEL: @test3(
-; NODL-NEXT: %R = icmp eq i32 %X, 1
-; NODL-NEXT: ret i1 %R
-
-; P32-LABEL: @test3(
-; P32-NEXT: %R = icmp eq i32 %X, 1
-; P32-NEXT: ret i1 %R
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: %R = icmp eq i32 %X, 1
+; CHECK-NEXT: ret i1 %R
 
 }
 
 define i1 @test4(i32 %X) {
-  %P = getelementptr inbounds [10 x i16]* @G16, i32 0, i32 %X
-  %Q = load i16* %P
+  %P = getelementptr inbounds [10 x i16], [10 x i16]* @G16, i32 0, i32 %X
+  %Q = load i16, i16* %P
   %R = icmp sle i16 %Q, 73
   ret i1 %R
-; NODL-LABEL: @test4(
-; NODL-NEXT: lshr i32 933, %X
-; NODL-NEXT: and i32 {{.*}}, 1
-; NODL-NEXT: %R = icmp ne i32 {{.*}}, 0
-; NODL-NEXT: ret i1 %R
-
-; P32-LABEL: @test4(
-; P32-NEXT: lshr i32 933, %X
-; P32-NEXT: and i32 {{.*}}, 1
-; P32-NEXT: %R = icmp ne i32 {{.*}}, 0
-; P32-NEXT: ret i1 %R
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: lshr i32 933, %X
+; CHECK-NEXT: and i32 {{.*}}, 1
+; CHECK-NEXT: %R = icmp ne i32 {{.*}}, 0
+; CHECK-NEXT: ret i1 %R
 }
 
 define i1 @test4_i16(i16 %X) {
-  %P = getelementptr inbounds [10 x i16]* @G16, i32 0, i16 %X
-  %Q = load i16* %P
+  %P = getelementptr inbounds [10 x i16], [10 x i16]* @G16, i32 0, i16 %X
+  %Q = load i16, i16* %P
   %R = icmp sle i16 %Q, 73
   ret i1 %R
-
-; NODL-LABEL: @test4_i16(
-; NODL-NEXT: lshr i16 933, %X
-; NODL-NEXT: and i16 {{.*}}, 1
-; NODL-NEXT: %R = icmp ne i16 {{.*}}, 0
-; NODL-NEXT: ret i1 %R
-
-; P32-LABEL: @test4_i16(
-; P32-NEXT: sext i16 %X to i32
-; P32-NEXT: lshr i32 933, %1
-; P32-NEXT: and i32 {{.*}}, 1
-; P32-NEXT: %R = icmp ne i32 {{.*}}, 0
-; P32-NEXT: ret i1 %R
+; CHECK-LABEL: @test4_i16(
+; CHECK-NEXT: sext i16 %X to i32
+; CHECK-NEXT: lshr i32 933, %1
+; CHECK-NEXT: and i32 {{.*}}, 1
+; CHECK-NEXT: %R = icmp ne i32 {{.*}}, 0
+; CHECK-NEXT: ret i1 %R
 }
 
 define i1 @test5(i32 %X) {
-  %P = getelementptr inbounds [10 x i16]* @G16, i32 0, i32 %X
-  %Q = load i16* %P
+  %P = getelementptr inbounds [10 x i16], [10 x i16]* @G16, i32 0, i32 %X
+  %Q = load i16, i16* %P
   %R = icmp eq i16 %Q, 69
   ret i1 %R
-; NODL-LABEL: @test5(
-; NODL-NEXT: icmp eq i32 %X, 2
-; NODL-NEXT: icmp eq i32 %X, 7
-; NODL-NEXT: %R = or i1
-; NODL-NEXT: ret i1 %R
-
-; P32-LABEL: @test5(
-; P32-NEXT: icmp eq i32 %X, 2
-; P32-NEXT: icmp eq i32 %X, 7
-; P32-NEXT: %R = or i1
-; P32-NEXT: ret i1 %R
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: icmp eq i32 %X, 2
+; CHECK-NEXT: icmp eq i32 %X, 7
+; CHECK-NEXT: %R = or i1
+; CHECK-NEXT: ret i1 %R
 }
 
 define i1 @test6(i32 %X) {
-  %P = getelementptr inbounds [6 x double]* @GD, i32 0, i32 %X
-  %Q = load double* %P
+  %P = getelementptr inbounds [6 x double], [6 x double]* @GD, i32 0, i32 %X
+  %Q = load double, double* %P
   %R = fcmp ogt double %Q, 0.0
   ret i1 %R
-; NODL-LABEL: @test6(
-; NODL-NEXT: add i32 %X, -1
-; NODL-NEXT: %R = icmp ult i32 {{.*}}, 3
-; NODL-NEXT: ret i1 %R
-
-; P32-LABEL: @test6(
-; P32-NEXT: add i32 %X, -1
-; P32-NEXT: %R = icmp ult i32 {{.*}}, 3
-; P32-NEXT: ret i1 %R
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: add i32 %X, -1
+; CHECK-NEXT: %R = icmp ult i32 {{.*}}, 3
+; CHECK-NEXT: ret i1 %R
 }
 
 define i1 @test7(i32 %X) {
-  %P = getelementptr inbounds [6 x double]* @GD, i32 0, i32 %X
-  %Q = load double* %P
+  %P = getelementptr inbounds [6 x double], [6 x double]* @GD, i32 0, i32 %X
+  %Q = load double, double* %P
   %R = fcmp olt double %Q, 0.0
   ret i1 %R
-; NODL-LABEL: @test7(
-; NODL-NEXT: add i32 %X, -1
-; NODL-NEXT: %R = icmp ugt i32 {{.*}}, 2
-; NODL-NEXT: ret i1 %R
-
-; P32-LABEL: @test7(
-; P32-NEXT: add i32 %X, -1
-; P32-NEXT: %R = icmp ugt i32 {{.*}}, 2
-; P32-NEXT: ret i1 %R
+; CHECK-LABEL: @test7(
+; CHECK-NEXT: add i32 %X, -1
+; CHECK-NEXT: %R = icmp ugt i32 {{.*}}, 2
+; CHECK-NEXT: ret i1 %R
 }
 
 define i1 @test8(i32 %X) {
-  %P = getelementptr inbounds [10 x i16]* @G16, i32 0, i32 %X
-  %Q = load i16* %P
+  %P = getelementptr inbounds [10 x i16], [10 x i16]* @G16, i32 0, i32 %X
+  %Q = load i16, i16* %P
   %R = and i16 %Q, 3
   %S = icmp eq i16 %R, 0
   ret i1 %S
-; NODL-LABEL: @test8(
-; NODL-NEXT: and i32 %X, -2
-; NODL-NEXT: icmp eq i32 {{.*}}, 8
-; NODL-NEXT: ret i1
-
-; P32-LABEL: @test8(
-; P32-NEXT: and i32 %X, -2
-; P32-NEXT: icmp eq i32 {{.*}}, 8
-; P32-NEXT: ret i1
+; CHECK-LABEL: @test8(
+; CHECK-NEXT: and i32 %X, -2
+; CHECK-NEXT: icmp eq i32 {{.*}}, 8
+; CHECK-NEXT: ret i1
 }
 
 @GA = internal constant [4 x { i32, i32 } ] [
@@ -210,41 +161,30 @@ define i1 @test8(i32 %X) {
 ]
 
 define i1 @test9(i32 %X) {
-  %P = getelementptr inbounds [4 x { i32, i32 } ]* @GA, i32 0, i32 %X, i32 1
-  %Q = load i32* %P
+  %P = getelementptr inbounds [4 x { i32, i32 } ], [4 x { i32, i32 } ]* @GA, i32 0, i32 %X, i32 1
+  %Q = load i32, i32* %P
   %R = icmp eq i32 %Q, 1
   ret i1 %R
-; NODL-LABEL: @test9(
-; NODL-NEXT: add i32 %X, -1
-; NODL-NEXT: icmp ult i32 {{.*}}, 2
-; NODL-NEXT: ret i1
-
-; P32-LABEL: @test9(
-; P32-NEXT: add i32 %X, -1
-; P32-NEXT: icmp ult i32 {{.*}}, 2
-; P32-NEXT: ret i1
+; CHECK-LABEL: @test9(
+; CHECK-NEXT: add i32 %X, -1
+; CHECK-NEXT: icmp ult i32 {{.*}}, 2
+; CHECK-NEXT: ret i1
 }
 
 define i1 @test10_struct(i32 %x) {
-; NODL-LABEL: @test10_struct(
-; NODL: getelementptr inbounds %Foo* @GS, i32 %x, i32 0
-
-; P32-LABEL: @test10_struct(
-; P32: getelementptr inbounds %Foo* @GS, i32 %x, i32 0
-  %p = getelementptr inbounds %Foo* @GS, i32 %x, i32 0
-  %q = load i32* %p
+; CHECK-LABEL: @test10_struct(
+; CHECK: ret i1 false
+  %p = getelementptr inbounds %Foo, %Foo* @GS, i32 %x, i32 0
+  %q = load i32, i32* %p
   %r = icmp eq i32 %q, 9
   ret i1 %r
 }
 
 define i1 @test10_struct_noinbounds(i32 %x) {
-; NODL-LABEL: @test10_struct_noinbounds(
-; NODL: getelementptr %Foo* @GS, i32 %x, i32 0
-
-; P32-LABEL: @test10_struct_noinbounds(
-; P32: getelementptr %Foo* @GS, i32 %x, i32 0
-  %p = getelementptr %Foo* @GS, i32 %x, i32 0
-  %q = load i32* %p
+; CHECK-LABEL: @test10_struct_noinbounds(
+; CHECK: getelementptr %Foo, %Foo* @GS, i32 %x, i32 0
+  %p = getelementptr %Foo, %Foo* @GS, i32 %x, i32 0
+  %q = load i32, i32* %p
   %r = icmp eq i32 %q, 9
   ret i1 %r
 }
@@ -252,14 +192,10 @@ define i1 @test10_struct_noinbounds(i32 %x) {
 ; Test that the GEP indices are converted before we ever get here
 ; Index < ptr size
 define i1 @test10_struct_i16(i16 %x){
-; NODL-LABEL: @test10_struct_i16(
-; NODL: getelementptr inbounds %Foo* @GS, i16 %x, i32 0
-
-; P32-LABEL: @test10_struct_i16(
-; P32: %1 = sext i16 %x to i32
-; P32: getelementptr inbounds %Foo* @GS, i32 %1, i32 0
-  %p = getelementptr inbounds %Foo* @GS, i16 %x, i32 0
-  %q = load i32* %p
+; CHECK-LABEL: @test10_struct_i16(
+; CHECK: ret i1 false
+  %p = getelementptr inbounds %Foo, %Foo* @GS, i16 %x, i32 0
+  %q = load i32, i32* %p
   %r = icmp eq i32 %q, 0
   ret i1 %r
 }
@@ -267,108 +203,79 @@ define i1 @test10_struct_i16(i16 %x){
 ; Test that the GEP indices are converted before we ever get here
 ; Index > ptr size
 define i1 @test10_struct_i64(i64 %x){
-; NODL-LABEL: @test10_struct_i64(
-; NODL: getelementptr inbounds %Foo* @GS, i64 %x, i32 0
-
-; P32-LABEL: @test10_struct_i64(
-; P32: %1 = trunc i64 %x to i32
-; P32: getelementptr inbounds %Foo* @GS, i32 %1, i32 0
-  %p = getelementptr inbounds %Foo* @GS, i64 %x, i32 0
-  %q = load i32* %p
+; CHECK-LABEL: @test10_struct_i64(
+; CHECK: ret i1 false
+  %p = getelementptr inbounds %Foo, %Foo* @GS, i64 %x, i32 0
+  %q = load i32, i32* %p
   %r = icmp eq i32 %q, 0
   ret i1 %r
 }
 
 define i1 @test10_struct_noinbounds_i16(i16 %x) {
-; NODL-LABEL: @test10_struct_noinbounds_i16(
-; NODL: getelementptr %Foo* @GS, i16 %x, i32 0
-
-; P32-LABEL: @test10_struct_noinbounds_i16(
-; P32: %1 = sext i16 %x to i32
-; P32: getelementptr %Foo* @GS, i32 %1, i32 0
-  %p = getelementptr %Foo* @GS, i16 %x, i32 0
-  %q = load i32* %p
+; CHECK-LABEL: @test10_struct_noinbounds_i16(
+; CHECK: %1 = sext i16 %x to i32
+; CHECK: getelementptr %Foo, %Foo* @GS, i32 %1, i32 0
+  %p = getelementptr %Foo, %Foo* @GS, i16 %x, i32 0
+  %q = load i32, i32* %p
   %r = icmp eq i32 %q, 0
   ret i1 %r
 }
 
 define i1 @test10_struct_arr(i32 %x) {
-; NODL-LABEL: @test10_struct_arr(
-; NODL-NEXT: %r = icmp ne i32 %x, 1
-; NODL-NEXT: ret i1 %r
-
-; P32-LABEL: @test10_struct_arr(
-; P32-NEXT: %r = icmp ne i32 %x, 1
-; P32-NEXT: ret i1 %r
-  %p = getelementptr inbounds [4 x %Foo]* @GStructArr, i32 0, i32 %x, i32 2
-  %q = load i32* %p
+; CHECK-LABEL: @test10_struct_arr(
+; CHECK-NEXT: %r = icmp ne i32 %x, 1
+; CHECK-NEXT: ret i1 %r
+  %p = getelementptr inbounds [4 x %Foo], [4 x %Foo]* @GStructArr, i32 0, i32 %x, i32 2
+  %q = load i32, i32* %p
   %r = icmp eq i32 %q, 9
   ret i1 %r
 }
 
 define i1 @test10_struct_arr_noinbounds(i32 %x) {
-; NODL-LABEL: @test10_struct_arr_noinbounds(
-; NODL-NEXT  %p = getelementptr [4 x %Foo]* @GStructArr, i32 0, i32 %x, i32 2
-
-; P32-LABEL: @test10_struct_arr_noinbounds(
-; P32-NEXT  %p = getelementptr [4 x %Foo]* @GStructArr, i32 0, i32 %x, i32 2
-  %p = getelementptr [4 x %Foo]* @GStructArr, i32 0, i32 %x, i32 2
-  %q = load i32* %p
+; CHECK-LABEL: @test10_struct_arr_noinbounds(
+; CHECK-NEXT  %p = getelementptr [4 x %Foo], [4 x %Foo]* @GStructArr, i32 0, i32 %x, i32 2
+  %p = getelementptr [4 x %Foo], [4 x %Foo]* @GStructArr, i32 0, i32 %x, i32 2
+  %q = load i32, i32* %p
   %r = icmp eq i32 %q, 9
   ret i1 %r
 }
 
 define i1 @test10_struct_arr_i16(i16 %x) {
-; NODL-LABEL: @test10_struct_arr_i16(
-; NODL-NEXT: %r = icmp ne i16 %x, 1
-; NODL-NEXT: ret i1 %r
-
-; P32-LABEL: @test10_struct_arr_i16(
-; P32-NEXT: %r = icmp ne i16 %x, 1
-; P32-NEXT: ret i1 %r
-  %p = getelementptr inbounds [4 x %Foo]* @GStructArr, i16 0, i16 %x, i32 2
-  %q = load i32* %p
+; CHECK-LABEL: @test10_struct_arr_i16(
+; CHECK-NEXT: %r = icmp ne i16 %x, 1
+; CHECK-NEXT: ret i1 %r
+  %p = getelementptr inbounds [4 x %Foo], [4 x %Foo]* @GStructArr, i16 0, i16 %x, i32 2
+  %q = load i32, i32* %p
   %r = icmp eq i32 %q, 9
   ret i1 %r
 }
 
 define i1 @test10_struct_arr_i64(i64 %x) {
-; NODL-LABEL: @test10_struct_arr_i64(
-; NODL-NEXT: %r = icmp ne i64 %x, 1
-; NODL-NEXT: ret i1 %r
-
-; P32-LABEL: @test10_struct_arr_i64(
-; P32-NEXT: trunc i64 %x to i32
-; P32-NEXT: %r = icmp ne i32 %1, 1
-; P32-NEXT: ret i1 %r
-  %p = getelementptr inbounds [4 x %Foo]* @GStructArr, i64 0, i64 %x, i32 2
-  %q = load i32* %p
+; CHECK-LABEL: @test10_struct_arr_i64(
+; CHECK-NEXT: trunc i64 %x to i32
+; CHECK-NEXT: %r = icmp ne i32 %1, 1
+; CHECK-NEXT: ret i1 %r
+  %p = getelementptr inbounds [4 x %Foo], [4 x %Foo]* @GStructArr, i64 0, i64 %x, i32 2
+  %q = load i32, i32* %p
   %r = icmp eq i32 %q, 9
   ret i1 %r
 }
 
 define i1 @test10_struct_arr_noinbounds_i16(i16 %x) {
-; NODL-LABEL: @test10_struct_arr_noinbounds_i16(
-; NODL-NEXT:  %p = getelementptr [4 x %Foo]* @GStructArr, i32 0, i16 %x, i32 2
-
-; P32-LABEL: @test10_struct_arr_noinbounds_i16(
-; P32-NEXT: %r = icmp ne i16 %x, 1
-  %p = getelementptr [4 x %Foo]* @GStructArr, i32 0, i16 %x, i32 2
-  %q = load i32* %p
+; CHECK-LABEL: @test10_struct_arr_noinbounds_i16(
+; CHECK-NEXT: %r = icmp ne i16 %x, 1
+  %p = getelementptr [4 x %Foo], [4 x %Foo]* @GStructArr, i32 0, i16 %x, i32 2
+  %q = load i32, i32* %p
   %r = icmp eq i32 %q, 9
   ret i1 %r
 }
 
 define i1 @test10_struct_arr_noinbounds_i64(i64 %x) {
-; FIXME: Should be no trunc?
-; NODL-LABEL: @test10_struct_arr_noinbounds_i64(
-; NODL-NEXT:  %p = getelementptr [4 x %Foo]* @GStructArr, i32 0, i64 %x, i32 2
-
-; P32-LABEL: @test10_struct_arr_noinbounds_i64(
-; P32: %r = icmp ne i32 %1, 1
-; P32-NEXT: ret i1 %r
-  %p = getelementptr [4 x %Foo]* @GStructArr, i32 0, i64 %x, i32 2
-  %q = load i32* %p
+; CHECK-LABEL: @test10_struct_arr_noinbounds_i64(
+; CHECK: %r = icmp ne i32 %1, 1
+; CHECK-NEXT: ret i1 %r
+  %p = getelementptr [4 x %Foo], [4 x %Foo]* @GStructArr, i32 0, i64 %x, i32 2
+  %q = load i32, i32* %p
   %r = icmp eq i32 %q, 9
   ret i1 %r
 }
diff --git a/test/Transforms/InstCombine/load-select.ll b/test/Transforms/InstCombine/load-select.ll
index e8cbad335dea..dfc07983eff4 100644
--- a/test/Transforms/InstCombine/load-select.ll
+++ b/test/Transforms/InstCombine/load-select.ll
@@ -10,7 +10,7 @@ define i32 @b(i32 %y) nounwind readonly {
 ; CHECK: ret i32
 entry:
   %0 = icmp eq i32 %y, 0                          ; <i1> [#uses=1]
-  %storemerge = select i1 %0, i32* getelementptr inbounds ([2 x i32]* @a, i32 0, i32 1), i32* getelementptr inbounds ([2 x i32]* @a, i32 0, i32 0) ; <i32*> [#uses=1]
-  %1 = load i32* %storemerge, align 4             ; <i32> [#uses=1]
+  %storemerge = select i1 %0, i32* getelementptr inbounds ([2 x i32], [2 x i32]* @a, i32 0, i32 1), i32* getelementptr inbounds ([2 x i32], [2 x i32]* @a, i32 0, i32 0) ; <i32*> [#uses=1]
+  %1 = load i32, i32* %storemerge, align 4             ; <i32> [#uses=1]
   ret i32 %1
 }
diff --git a/test/Transforms/InstCombine/load.ll b/test/Transforms/InstCombine/load.ll
index b4b7558a1a05..2cc55e99fd20 100644
--- a/test/Transforms/InstCombine/load.ll
+++ b/test/Transforms/InstCombine/load.ll
@@ -1,8 +1,9 @@
 ; RUN: opt -instcombine -S < %s | FileCheck %s
+; RUN: opt -passes=instcombine -S < %s | FileCheck %s
 
 ; This test makes sure that these instructions are properly eliminated.
 
-target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target datalayout = "e-m:e-p:64:64:64-i64:64-f80:128-n8:16:32:64-S128"
 
 @X = constant i32 42		; <i32*> [#uses=2]
 @X2 = constant i32 47		; <i32*> [#uses=1]
@@ -15,31 +16,31 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 ; CHECK-LABEL: @test1(
 ; CHECK-NOT: load
 define i32 @test1() {
-	%B = load i32* @X		; <i32> [#uses=1]
+	%B = load i32, i32* @X		; <i32> [#uses=1]
 	ret i32 %B
 }
 
 ; CHECK-LABEL: @test2(
 ; CHECK-NOT: load
 define float @test2() {
-	%A = getelementptr [2 x { i32, float }]* @Y, i64 0, i64 1, i32 1		; <float*> [#uses=1]
-	%B = load float* %A		; <float> [#uses=1]
+	%A = getelementptr [2 x { i32, float }], [2 x { i32, float }]* @Y, i64 0, i64 1, i32 1		; <float*> [#uses=1]
+	%B = load float, float* %A		; <float> [#uses=1]
 	ret float %B
 }
 
 ; CHECK-LABEL: @test3(
 ; CHECK-NOT: load
 define i32 @test3() {
-	%A = getelementptr [2 x { i32, float }]* @Y, i64 0, i64 0, i32 0		; <i32*> [#uses=1]
-	%B = load i32* %A		; <i32> [#uses=1]
+	%A = getelementptr [2 x { i32, float }], [2 x { i32, float }]* @Y, i64 0, i64 0, i32 0		; <i32*> [#uses=1]
+	%B = load i32, i32* %A		; <i32> [#uses=1]
 	ret i32 %B
 }
 
 ; CHECK-LABEL: @test4(
 ; CHECK-NOT: load
 define i32 @test4() {
-	%A = getelementptr [2 x { i32, float }]* @Z, i64 0, i64 1, i32 0		; <i32*> [#uses=1]
-	%B = load i32* %A		; <i32> [#uses=1]
+	%A = getelementptr [2 x { i32, float }], [2 x { i32, float }]* @Z, i64 0, i64 1, i32 0		; <i32*> [#uses=1]
+	%B = load i32, i32* %A		; <i32> [#uses=1]
 	ret i32 %B
 }
 
@@ -47,15 +48,15 @@ define i32 @test4() {
 ; CHECK-NOT: load
 define i32 @test5(i1 %C) {
 	%Y = select i1 %C, i32* @X, i32* @X2		; <i32*> [#uses=1]
-	%Z = load i32* %Y		; <i32> [#uses=1]
+	%Z = load i32, i32* %Y		; <i32> [#uses=1]
 	ret i32 %Z
 }
 
 ; CHECK-LABEL: @test7(
 ; CHECK-NOT: load
 define i32 @test7(i32 %X) {
-	%V = getelementptr i32* null, i32 %X		; <i32*> [#uses=1]
-	%R = load i32* %V		; <i32> [#uses=1]
+	%V = getelementptr i32, i32* null, i32 %X		; <i32*> [#uses=1]
+	%R = load i32, i32* %V		; <i32> [#uses=1]
 	ret i32 %R
 }
 
@@ -63,15 +64,15 @@ define i32 @test7(i32 %X) {
 ; CHECK-NOT: load
 define i32 @test8(i32* %P) {
 	store i32 1, i32* %P
-	%X = load i32* %P		; <i32> [#uses=1]
+	%X = load i32, i32* %P		; <i32> [#uses=1]
 	ret i32 %X
 }
 
 ; CHECK-LABEL: @test9(
 ; CHECK-NOT: load
 define i32 @test9(i32* %P) {
-	%X = load i32* %P		; <i32> [#uses=1]
-	%Y = load i32* %P		; <i32> [#uses=1]
+	%X = load i32, i32* %P		; <i32> [#uses=1]
+	%Y = load i32, i32* %P		; <i32> [#uses=1]
 	%Z = sub i32 %X, %Y		; <i32> [#uses=1]
 	ret i32 %Z
 }
@@ -88,17 +89,17 @@ F:		; preds = %0
 	store i32 0, i32* %P
 	br label %C
 C:		; preds = %F, %T
-	%V = load i32* %P		; <i32> [#uses=1]
+	%V = load i32, i32* %P		; <i32> [#uses=1]
 	ret i32 %V
 }
 
 ; CHECK-LABEL: @test11(
 ; CHECK-NOT: load
 define double @test11(double* %p) {
-  %t0 = getelementptr double* %p, i32 1
+  %t0 = getelementptr double, double* %p, i32 1
   store double 2.0, double* %t0
-  %t1 = getelementptr double* %p, i32 1
-  %x = load double* %t1
+  %t1 = getelementptr double, double* %p, i32 1
+  %x = load double, double* %t1
   ret double %x
 }
 
@@ -109,14 +110,14 @@ define i32 @test12(i32* %P) {
   store i32 123, i32* %A
   ; Cast the result of the load not the source
   %Q = bitcast i32* %A to i32*
-  %V = load i32* %Q
+  %V = load i32, i32* %Q
   ret i32 %V
 }
 
 ; CHECK-LABEL: @test13(
 ; CHECK-NOT: load
 define <16 x i8> @test13(<2 x i64> %x) {
-  %tmp = load <16 x i8>* bitcast ([4 x i32]* @GLOBAL to <16 x i8>*)
+  %tmp = load <16 x i8>, <16 x i8>* bitcast ([4 x i32]* @GLOBAL to <16 x i8>*)
   ret <16 x i8> %tmp
 }
 
@@ -127,13 +128,13 @@ define i8 @test14(i8 %x, i32 %y) {
 ; those confuse the analysis into thinking that the second store does not alias
 ; the first.
 ; CHECK-LABEL: @test14(
-; CHECK:         %[[R:.*]] = load i8*
+; CHECK:         %[[R:.*]] = load i8, i8*
 ; CHECK-NEXT:    ret i8 %[[R]]
   %a = alloca i32
   %a.i8 = bitcast i32* %a to i8*
   store i8 %x, i8* %a.i8
   store i32 %y, i32* %a
-  %r = load i8* %a.i8
+  %r = load i8, i8* %a.i8
   ret i8 %r
 }
 
@@ -142,11 +143,61 @@ define i8 @test14(i8 %x, i32 %y) {
 define i8 @test15(i8 %x, i32 %y) {
 ; Same test as @test14 essentially, but using a global instead of an alloca.
 ; CHECK-LABEL: @test15(
-; CHECK:         %[[R:.*]] = load i8*
+; CHECK:         %[[R:.*]] = load i8, i8*
 ; CHECK-NEXT:    ret i8 %[[R]]
   %g.i8 = bitcast i32* @test15_global to i8*
   store i8 %x, i8* %g.i8
   store i32 %y, i32* @test15_global
-  %r = load i8* %g.i8
+  %r = load i8, i8* %g.i8
   ret i8 %r
 }
+
+define void @test16(i8* %x, i8* %a, i8* %b, i8* %c) {
+; Check that we canonicalize loads which are only stored to use integer types
+; when there is a valid integer type.
+; CHECK-LABEL: @test16(
+; CHECK: %[[L1:.*]] = load i32, i32*
+; CHECK-NOT: load
+; CHECK: store i32 %[[L1]], i32*
+; CHECK: store i32 %[[L1]], i32*
+; CHECK-NOT: store
+; CHECK: %[[L1:.*]] = load i32, i32*
+; CHECK-NOT: load
+; CHECK: store i32 %[[L1]], i32*
+; CHECK: store i32 %[[L1]], i32*
+; CHECK-NOT: store
+; CHECK: ret
+
+entry:
+  %x.cast = bitcast i8* %x to float*
+  %a.cast = bitcast i8* %a to float*
+  %b.cast = bitcast i8* %b to float*
+  %c.cast = bitcast i8* %c to i32*
+
+  %x1 = load float, float* %x.cast
+  store float %x1, float* %a.cast
+  store float %x1, float* %b.cast
+
+  %x2 = load float, float* %x.cast
+  store float %x2, float* %b.cast
+  %x2.cast = bitcast float %x2 to i32
+  store i32 %x2.cast, i32* %c.cast
+
+  ret void
+}
+
+define void @test17(i8** %x, i8 %y) {
+; Check that in cases similar to @test16 we don't try to rewrite a load when
+; its only use is a store but it is used as the pointer to that store rather
+; than the value.
+;
+; CHECK-LABEL: @test17(
+; CHECK: %[[L:.*]] = load i8*, i8**
+; CHECK: store i8 %y, i8* %[[L]]
+
+entry:
+  %x.load = load i8*, i8** %x
+  store i8 %y, i8* %x.load
+
+  ret void
+}
diff --git a/test/Transforms/InstCombine/load3.ll b/test/Transforms/InstCombine/load3.ll
index f79ef9a695c2..6db8dd391fa1 100644
--- a/test/Transforms/InstCombine/load3.ll
+++ b/test/Transforms/InstCombine/load3.ll
@@ -5,10 +5,10 @@ target triple = "i386-apple-macosx10.0.0"
 ; Instcombine should be able to do trivial CSE of loads.
 
 define i32 @test1(i32* %p) {
-  %t0 = getelementptr i32* %p, i32 1
-  %y = load i32* %t0
-  %t1 = getelementptr i32* %p, i32 1
-  %x = load i32* %t1
+  %t0 = getelementptr i32, i32* %p, i32 1
+  %y = load i32, i32* %t0
+  %t1 = getelementptr i32, i32* %p, i32 1
+  %x = load i32, i32* %t1
   %a = sub i32 %y, %x
   ret i32 %a
 ; CHECK-LABEL: @test1(
@@ -19,7 +19,7 @@ define i32 @test1(i32* %p) {
 ; PR7429
 @.str = private constant [4 x i8] c"XYZ\00"
 define float @test2() {
-  %tmp = load float* bitcast ([4 x i8]* @.str to float*), align 1
+  %tmp = load float, float* bitcast ([4 x i8]* @.str to float*), align 1
   ret float %tmp
   
 ; CHECK-LABEL: @test2(
@@ -37,10 +37,10 @@ align 4
 ; PR14986
 define void @test3() nounwind {
 ; This is a weird way of computing zero.
-  %l = load i32* getelementptr ([36 x i32]* @expect32, i32 29826161, i32 28), align 4
-  store i32 %l, i32* getelementptr ([36 x i32]* @rslts32, i32 29826161, i32 28), align 4
+  %l = load i32, i32* getelementptr ([36 x i32], [36 x i32]* @expect32, i32 29826161, i32 28), align 4
+  store i32 %l, i32* getelementptr ([36 x i32], [36 x i32]* @rslts32, i32 29826161, i32 28), align 4
   ret void
 
 ; CHECK-LABEL: @test3(
-; CHECK: store i32 1, i32* getelementptr inbounds ([36 x i32]* @rslts32, i32 0, i32 0)
+; CHECK: store i32 1, i32* getelementptr inbounds ([36 x i32], [36 x i32]* @rslts32, i32 0, i32 0)
 }
diff --git a/test/Transforms/InstCombine/loadstore-alignment.ll b/test/Transforms/InstCombine/loadstore-alignment.ll
index e90bdb7cdd99..4afa82dcb4c5 100644
--- a/test/Transforms/InstCombine/loadstore-alignment.ll
+++ b/test/Transforms/InstCombine/loadstore-alignment.ll
@@ -9,58 +9,58 @@ target datalayout = "E-p:64:64:64-p1:64:64:64-p2:32:32:32-a0:0:8-f32:32:32-f64:6
 ; CHECK-LABEL: @static_hem(
 ; CHECK: , align 16
 define <2 x i64> @static_hem() {
-  %t = getelementptr <2 x i64>* @x, i32 7
-  %tmp1 = load <2 x i64>* %t, align 1
+  %t = getelementptr <2 x i64>, <2 x i64>* @x, i32 7
+  %tmp1 = load <2 x i64>, <2 x i64>* %t, align 1
   ret <2 x i64> %tmp1
 }
 
 ; CHECK-LABEL: @static_hem_addrspacecast(
 ; CHECK: , align 16
 define <2 x i64> @static_hem_addrspacecast() {
-  %t = getelementptr <2 x i64>* @x, i32 7
+  %t = getelementptr <2 x i64>, <2 x i64>* @x, i32 7
   %t.asc = addrspacecast <2 x i64>* %t to <2 x i64> addrspace(1)*
-  %tmp1 = load <2 x i64> addrspace(1)* %t.asc, align 1
+  %tmp1 = load <2 x i64>, <2 x i64> addrspace(1)* %t.asc, align 1
   ret <2 x i64> %tmp1
 }
 
 ; CHECK-LABEL: @static_hem_addrspacecast_smaller_ptr(
 ; CHECK: , align 16
 define <2 x i64> @static_hem_addrspacecast_smaller_ptr() {
-  %t = getelementptr <2 x i64>* @x, i32 7
+  %t = getelementptr <2 x i64>, <2 x i64>* @x, i32 7
   %t.asc = addrspacecast <2 x i64>* %t to <2 x i64> addrspace(2)*
-  %tmp1 = load <2 x i64> addrspace(2)* %t.asc, align 1
+  %tmp1 = load <2 x i64>, <2 x i64> addrspace(2)* %t.asc, align 1
   ret <2 x i64> %tmp1
 }
 
 ; CHECK-LABEL: @static_hem_addrspacecast_larger_ptr(
 ; CHECK: , align 16
 define <2 x i64> @static_hem_addrspacecast_larger_ptr() {
-  %t = getelementptr <2 x i64> addrspace(2)* @x.as2, i32 7
+  %t = getelementptr <2 x i64>, <2 x i64> addrspace(2)* @x.as2, i32 7
   %t.asc = addrspacecast <2 x i64> addrspace(2)* %t to <2 x i64> addrspace(1)*
-  %tmp1 = load <2 x i64> addrspace(1)* %t.asc, align 1
+  %tmp1 = load <2 x i64>, <2 x i64> addrspace(1)* %t.asc, align 1
   ret <2 x i64> %tmp1
 }
 
 ; CHECK-LABEL: @hem(
 ; CHECK: , align 16
 define <2 x i64> @hem(i32 %i) {
-  %t = getelementptr <2 x i64>* @x, i32 %i
-  %tmp1 = load <2 x i64>* %t, align 1
+  %t = getelementptr <2 x i64>, <2 x i64>* @x, i32 %i
+  %tmp1 = load <2 x i64>, <2 x i64>* %t, align 1
   ret <2 x i64> %tmp1
 }
 
 ; CHECK-LABEL: @hem_2d(
 ; CHECK: , align 16
 define <2 x i64> @hem_2d(i32 %i, i32 %j) {
-  %t = getelementptr [13 x <2 x i64>]* @xx, i32 %i, i32 %j
-  %tmp1 = load <2 x i64>* %t, align 1
+  %t = getelementptr [13 x <2 x i64>], [13 x <2 x i64>]* @xx, i32 %i, i32 %j
+  %tmp1 = load <2 x i64>, <2 x i64>* %t, align 1
   ret <2 x i64> %tmp1
 }
 
 ; CHECK-LABEL: @foo(
 ; CHECK: , align 16
 define <2 x i64> @foo() {
-  %tmp1 = load <2 x i64>* @x, align 1
+  %tmp1 = load <2 x i64>, <2 x i64>* @x, align 1
   ret <2 x i64> %tmp1
 }
 
@@ -70,14 +70,14 @@ define <2 x i64> @foo() {
 define <2 x i64> @bar() {
   %t = alloca <2 x i64>
   call void @kip(<2 x i64>* %t)
-  %tmp1 = load <2 x i64>* %t, align 1
+  %tmp1 = load <2 x i64>, <2 x i64>* %t, align 1
   ret <2 x i64> %tmp1
 }
 
 ; CHECK-LABEL: @static_hem_store(
 ; CHECK: , align 16
 define void @static_hem_store(<2 x i64> %y) {
-  %t = getelementptr <2 x i64>* @x, i32 7
+  %t = getelementptr <2 x i64>, <2 x i64>* @x, i32 7
   store <2 x i64> %y, <2 x i64>* %t, align 1
   ret void
 }
@@ -85,7 +85,7 @@ define void @static_hem_store(<2 x i64> %y) {
 ; CHECK-LABEL: @hem_store(
 ; CHECK: , align 16
 define void @hem_store(i32 %i, <2 x i64> %y) {
-  %t = getelementptr <2 x i64>* @x, i32 %i
+  %t = getelementptr <2 x i64>, <2 x i64>* @x, i32 %i
   store <2 x i64> %y, <2 x i64>* %t, align 1
   ret void
 }
@@ -93,7 +93,7 @@ define void @hem_store(i32 %i, <2 x i64> %y) {
 ; CHECK-LABEL: @hem_2d_store(
 ; CHECK: , align 16
 define void @hem_2d_store(i32 %i, i32 %j, <2 x i64> %y) {
-  %t = getelementptr [13 x <2 x i64>]* @xx, i32 %i, i32 %j
+  %t = getelementptr [13 x <2 x i64>], [13 x <2 x i64>]* @xx, i32 %i, i32 %j
   store <2 x i64> %y, <2 x i64>* %t, align 1
   ret void
 }
diff --git a/test/Transforms/InstCombine/loadstore-metadata.ll b/test/Transforms/InstCombine/loadstore-metadata.ll
index 3d18ac0e3344..a30c0bc852ea 100644
--- a/test/Transforms/InstCombine/loadstore-metadata.ll
+++ b/test/Transforms/InstCombine/loadstore-metadata.ll
@@ -5,9 +5,9 @@ target datalayout = "e-m:e-p:64:64:64-i64:64-f80:128-n8:16:32:64-S128"
 define i32 @test_load_cast_combine_tbaa(float* %ptr) {
 ; Ensure (cast (load (...))) -> (load (cast (...))) preserves TBAA.
 ; CHECK-LABEL: @test_load_cast_combine_tbaa(
-; CHECK: load i32* %{{.*}}, !tbaa !0
+; CHECK: load i32, i32* %{{.*}}, !tbaa !0
 entry:
-  %l = load float* %ptr, !tbaa !0
+  %l = load float, float* %ptr, !tbaa !0
   %c = bitcast float %l to i32
   ret i32 %c
 }
@@ -15,9 +15,9 @@ entry:
 define i32 @test_load_cast_combine_noalias(float* %ptr) {
 ; Ensure (cast (load (...))) -> (load (cast (...))) preserves no-alias metadata.
 ; CHECK-LABEL: @test_load_cast_combine_noalias(
-; CHECK: load i32* %{{.*}}, !alias.scope !2, !noalias !1
+; CHECK: load i32, i32* %{{.*}}, !alias.scope !2, !noalias !1
 entry:
-  %l = load float* %ptr, !alias.scope !2, !noalias !1
+  %l = load float, float* %ptr, !alias.scope !2, !noalias !1
   %c = bitcast float %l to i32
   ret i32 %c
 }
@@ -27,11 +27,11 @@ define float @test_load_cast_combine_range(i32* %ptr) {
 ; would be nice to preserve or update it somehow but this is hard when moving
 ; between types.
 ; CHECK-LABEL: @test_load_cast_combine_range(
-; CHECK: load float* %{{.*}}
+; CHECK: load float, float* %{{.*}}
 ; CHECK-NOT: !range
 ; CHECK: ret float
 entry:
-  %l = load i32* %ptr, !range !5
+  %l = load i32, i32* %ptr, !range !5
   %c = bitcast i32 %l to float
   ret float %c
 }
@@ -39,9 +39,9 @@ entry:
 define i32 @test_load_cast_combine_invariant(float* %ptr) {
 ; Ensure (cast (load (...))) -> (load (cast (...))) preserves invariant metadata.
 ; CHECK-LABEL: @test_load_cast_combine_invariant(
-; CHECK: load i32* %{{.*}}, !invariant.load !3
+; CHECK: load i32, i32* %{{.*}}, !invariant.load !3
 entry:
-  %l = load float* %ptr, !invariant.load !3
+  %l = load float, float* %ptr, !invariant.load !3
   %c = bitcast float %l to i32
   ret i32 %c
 }
@@ -50,9 +50,9 @@ define i32 @test_load_cast_combine_nontemporal(float* %ptr) {
 ; Ensure (cast (load (...))) -> (load (cast (...))) preserves nontemporal
 ; metadata.
 ; CHECK-LABEL: @test_load_cast_combine_nontemporal(
-; CHECK: load i32* %{{.*}}, !nontemporal !4
+; CHECK: load i32, i32* %{{.*}}, !nontemporal !4
 entry:
-  %l = load float* %ptr, !nontemporal !4
+  %l = load float, float* %ptr, !nontemporal !4
   %c = bitcast float %l to i32
   ret i32 %c
 }
@@ -61,15 +61,15 @@ define void @test_load_cast_combine_loop(float* %src, i32* %dst, i32 %n) {
 ; Ensure (cast (load (...))) -> (load (cast (...))) preserves loop access
 ; metadata.
 ; CHECK-LABEL: @test_load_cast_combine_loop(
-; CHECK: load i32* %{{.*}}, !llvm.mem.parallel_loop_access !1
+; CHECK: load i32, i32* %{{.*}}, !llvm.mem.parallel_loop_access !1
 entry:
   br label %loop
 
 loop:
   %i = phi i32 [ 0, %entry ], [ %i.next, %loop ]
-  %src.gep = getelementptr inbounds float* %src, i32 %i
-  %dst.gep = getelementptr inbounds i32* %dst, i32 %i
-  %l = load float* %src.gep, !llvm.mem.parallel_loop_access !1
+  %src.gep = getelementptr inbounds float, float* %src, i32 %i
+  %dst.gep = getelementptr inbounds i32, i32* %dst, i32 %i
+  %l = load float, float* %src.gep, !llvm.mem.parallel_loop_access !1
   %c = bitcast float %l to i32
   store i32 %c, i32* %dst.gep
   %i.next = add i32 %i, 1
@@ -80,6 +80,31 @@ exit:
   ret void
 }
 
+define void @test_load_cast_combine_nonnull(float** %ptr) {
+; We can't preserve nonnull metadata when converting a load of a pointer to
+; a load of an integer. Instead, we translate it to range metadata.
+; FIXME: We should also transform range metadata back into nonnull metadata.
+; FIXME: This test is very fragile. If any LABEL lines are added after
+; this point, the test will fail, because this test depends on a metadata tuple,
+; which is always emitted at the end of the file. At some point, we should
+; consider an option to the IR printer to emit MD tuples after the function
+; that first uses them--this will allow us to refer to them like this and not
+; have the tests break. For now, this function must always come last in this
+; file, and no LABEL lines are to be added after this point.
+;
+; CHECK-LABEL: @test_load_cast_combine_nonnull(
+; CHECK: %[[V:.*]] = load i64, i64* %{{.*}}, !range ![[MD:[0-9]+]]
+; CHECK-NOT: !nonnull
+; CHECK: store i64 %[[V]], i64*
+entry:
+  %p = load float*, float** %ptr, !nonnull !3
+  %gep = getelementptr float*, float** %ptr, i32 42
+  store float* %p, float** %gep
+  ret void
+}
+
+; This is the metadata tuple that we reference above:
+; CHECK: ![[MD]] = !{i64 1, i64 0}
 !0 = !{ !1, !1, i64 0 }
 !1 = !{ !1 }
 !2 = !{ !2, !1 }
diff --git a/test/Transforms/InstCombine/lshr-phi.ll b/test/Transforms/InstCombine/lshr-phi.ll
index 76a113face05..79dc8b33192d 100644
--- a/test/Transforms/InstCombine/lshr-phi.ll
+++ b/test/Transforms/InstCombine/lshr-phi.ll
@@ -8,24 +8,24 @@
 
 define i32 @hash_string(i8* nocapture %key) nounwind readonly {
 entry:
-	%t0 = load i8* %key, align 1		; <i8> [#uses=1]
+	%t0 = load i8, i8* %key, align 1		; <i8> [#uses=1]
 	%t1 = icmp eq i8 %t0, 0		; <i1> [#uses=1]
 	br i1 %t1, label %bb2, label %bb
 
 bb:		; preds = %bb, %entry
 	%indvar = phi i64 [ 0, %entry ], [ %tmp, %bb ]		; <i64> [#uses=2]
 	%k.04 = phi i32 [ 0, %entry ], [ %t8, %bb ]		; <i32> [#uses=2]
-	%cp.05 = getelementptr i8* %key, i64 %indvar		; <i8*> [#uses=1]
+	%cp.05 = getelementptr i8, i8* %key, i64 %indvar		; <i8*> [#uses=1]
 	%t2 = shl i32 %k.04, 1		; <i32> [#uses=1]
 	%t3 = lshr i32 %k.04, 14		; <i32> [#uses=1]
 	%t4 = add i32 %t2, %t3		; <i32> [#uses=1]
-	%t5 = load i8* %cp.05, align 1		; <i8> [#uses=1]
+	%t5 = load i8, i8* %cp.05, align 1		; <i8> [#uses=1]
 	%t6 = sext i8 %t5 to i32		; <i32> [#uses=1]
 	%t7 = xor i32 %t6, %t4		; <i32> [#uses=1]
 	%t8 = and i32 %t7, 16383		; <i32> [#uses=2]
 	%tmp = add i64 %indvar, 1		; <i64> [#uses=2]
-	%scevgep = getelementptr i8* %key, i64 %tmp		; <i8*> [#uses=1]
-	%t9 = load i8* %scevgep, align 1		; <i8> [#uses=1]
+	%scevgep = getelementptr i8, i8* %key, i64 %tmp		; <i8*> [#uses=1]
+	%t9 = load i8, i8* %scevgep, align 1		; <i8> [#uses=1]
 	%t10 = icmp eq i8 %t9, 0		; <i1> [#uses=1]
 	br i1 %t10, label %bb2, label %bb
 
diff --git a/test/Transforms/InstCombine/malloc-free-delete.ll b/test/Transforms/InstCombine/malloc-free-delete.ll
index ed25e4e49c84..dc04adb06966 100644
--- a/test/Transforms/InstCombine/malloc-free-delete.ll
+++ b/test/Transforms/InstCombine/malloc-free-delete.ll
@@ -3,9 +3,9 @@
 define i32 @main(i32 %argc, i8** %argv) {
 ; CHECK-LABEL: @main(
     %c_19 = alloca i8*
-    %malloc_206 = tail call i8* @malloc(i32 mul (i32 ptrtoint (i8* getelementptr (i8* null, i32 1) to i32), i32 10))
+    %malloc_206 = tail call i8* @malloc(i32 mul (i32 ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i32), i32 10))
     store i8* %malloc_206, i8** %c_19
-    %tmp_207 = load i8** %c_19
+    %tmp_207 = load i8*, i8** %c_19
     tail call void @free(i8* %tmp_207)
     ret i32 0
 ; CHECK-NEXT: ret i32 0
@@ -146,17 +146,36 @@ lpad.i:                                           ; preds = %entry
 }
 
 declare i8* @_Znwm(i64) nobuiltin
-declare void @_ZdlPvm(i8*, i64) nobuiltin
 declare i8* @_Znwj(i32) nobuiltin
-declare void @_ZdlPvj(i8*, i32) nobuiltin
 declare i8* @_Znam(i64) nobuiltin
-declare void @_ZdaPvm(i8*, i64) nobuiltin
 declare i8* @_Znaj(i32) nobuiltin
-declare void @_ZdaPvj(i8*, i32) nobuiltin
+declare void @_ZdlPv(i8*) nobuiltin
+declare void @_ZdaPv(i8*) nobuiltin
+
+define linkonce void @_ZdlPvm(i8* %p, i64) nobuiltin {
+  call void @_ZdlPv(i8* %p)
+  ret void
+}
+define linkonce void @_ZdlPvj(i8* %p, i32) nobuiltin {
+  call void @_ZdlPv(i8* %p)
+  ret void
+}
+define linkonce void @_ZdaPvm(i8* %p, i64) nobuiltin {
+  call void @_ZdaPv(i8* %p)
+  ret void
+}
+define linkonce void @_ZdaPvj(i8* %p, i32) nobuiltin {
+  call void @_ZdaPv(i8* %p)
+  ret void
+}
 
 ; CHECK-LABEL: @test8(
 define void @test8() {
   ; CHECK-NOT: call
+  %nw = call i8* @_Znwm(i64 32) builtin
+  call void @_ZdlPv(i8* %nw) builtin
+  %na = call i8* @_Znam(i64 32) builtin
+  call void @_ZdaPv(i8* %na) builtin
   %nwm = call i8* @_Znwm(i64 32) builtin
   call void @_ZdlPvm(i8* %nwm, i64 32) builtin
   %nwj = call i8* @_Znwj(i32 32) builtin
diff --git a/test/Transforms/InstCombine/max-of-nots.ll b/test/Transforms/InstCombine/max-of-nots.ll
new file mode 100644
index 000000000000..dd9c54b06739
--- /dev/null
+++ b/test/Transforms/InstCombine/max-of-nots.ll
@@ -0,0 +1,85 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+define i32 @compute_min_2(i32 %x, i32 %y) {
+; CHECK-LABEL: compute_min_2
+ entry:
+  %not_x = sub i32 -1, %x
+  %not_y = sub i32 -1, %y
+  %cmp = icmp sgt i32 %not_x, %not_y
+  %not_min = select i1 %cmp, i32 %not_x, i32 %not_y
+  %min = sub i32 -1, %not_min
+  ret i32 %min
+
+; CHECK: %0 = icmp slt i32 %x, %y
+; CHECK-NEXT: %1 = select i1 %0, i32 %x, i32 %y
+; CHECK-NEXT: ret i32 %1
+}
+
+define i32 @compute_min_3(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: compute_min_3
+ entry:
+  %not_x = sub i32 -1, %x
+  %not_y = sub i32 -1, %y
+  %not_z = sub i32 -1, %z
+  %cmp_1 = icmp sgt i32 %not_x, %not_y
+  %not_min_1 = select i1 %cmp_1, i32 %not_x, i32 %not_y
+  %cmp_2 = icmp sgt i32 %not_min_1, %not_z
+  %not_min_2 = select i1 %cmp_2, i32 %not_min_1, i32 %not_z
+  %min = sub i32 -1, %not_min_2
+  ret i32 %min
+
+; CHECK: %0 = icmp slt i32 %x, %y
+; CHECK-NEXT: %1 = select i1 %0, i32 %x, i32 %y
+; CHECK-NEXT: %2 = icmp slt i32 %1, %z
+; CHECK-NEXT: %3 = select i1 %2, i32 %1, i32 %z
+; CHECK-NEXT: ret i32 %3
+}
+
+define i32 @compute_min_arithmetic(i32 %x, i32 %y) {
+; CHECK-LABEL: compute_min_arithmetic
+ entry:
+  %not_value = sub i32 3, %x
+  %not_y = sub i32 -1, %y
+  %cmp = icmp sgt i32 %not_value, %not_y
+  %not_min = select i1 %cmp, i32 %not_value, i32 %not_y
+  ret i32 %not_min
+
+; CHECK: %0 = add i32 %x, -4
+; CHECK-NEXT: %1 = icmp slt i32 %0, %y
+; CHECK-NEXT: %2 = select i1 %1, i32 %0, i32 %y
+; CHECK-NEXT: %3 = xor i32 %2, -1
+; CHECK-NEXT: ret i32 %3
+}
+
+declare void @fake_use(i32)
+
+define i32 @compute_min_pessimization(i32 %x, i32 %y) {
+; CHECK-LABEL: compute_min_pessimization
+ entry:
+  %not_value = sub i32 3, %x
+  call void @fake_use(i32 %not_value)
+  %not_y = sub i32 -1, %y
+  %cmp = icmp sgt i32 %not_value, %not_y
+; CHECK: %not_value = sub i32 3, %x
+; CHECK: %cmp = icmp sgt i32 %not_value, %not_y
+  %not_min = select i1 %cmp, i32 %not_value, i32 %not_y
+  %min = sub i32 -1, %not_min
+  ret i32 %min
+}
+
+define i32 @max_of_nots(i32 %x, i32 %y) {
+; CHECK-LABEL: @max_of_nots(
+; CHECK-NEXT: icmp
+; CHECK-NEXT: select
+; CHECK-NEXT: icmp
+; CHECK-NEXT: select
+; CHECK-NEXT: xor
+; CHECK-NEXT: ret
+  %c0 = icmp sgt i32 %y, 0
+  %xor_y = xor i32 %y, -1
+  %s0 = select i1 %c0, i32 %xor_y, i32 -1
+  %xor_x = xor i32 %x, -1
+  %c1 = icmp slt i32 %s0, %xor_x
+  %smax96 = select i1 %c1, i32 %xor_x, i32 %s0
+  ret i32 %smax96
+}
diff --git a/test/Transforms/InstCombine/mem-gep-zidx.ll b/test/Transforms/InstCombine/mem-gep-zidx.ll
new file mode 100644
index 000000000000..cf021b133703
--- /dev/null
+++ b/test/Transforms/InstCombine/mem-gep-zidx.ll
@@ -0,0 +1,48 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+@f.a = private unnamed_addr constant [1 x i32] [i32 12], align 4
+@f.b = private unnamed_addr constant [1 x i32] [i32 55], align 4
+
+define signext i32 @test1(i32 signext %x) #0 {
+entry:
+  %idxprom = sext i32 %x to i64
+  %arrayidx = getelementptr inbounds [1 x i32], [1 x i32]* @f.a, i64 0, i64 %idxprom
+  %0 = load i32, i32* %arrayidx, align 4
+  ret i32 %0
+
+; CHECK-LABEL: @test1
+; CHECK: ret i32 12
+}
+
+declare void @foo(i64* %p)
+define void @test2(i32 signext %x, i64 %v) #0 {
+entry:
+  %p = alloca i64
+  %idxprom = sext i32 %x to i64
+  %arrayidx = getelementptr inbounds i64, i64* %p, i64 %idxprom
+  store i64 %v, i64* %arrayidx
+  call void @foo(i64* %p)
+  ret void
+
+; CHECK-LABEL: @test2
+; CHECK: %p = alloca i64
+; CHECK: store i64 %v, i64* %p
+; CHECK: ret void
+}
+
+define signext i32 @test3(i32 signext %x, i1 %y) #0 {
+entry:
+  %idxprom = sext i32 %x to i64
+  %p = select i1 %y, [1 x i32]* @f.a, [1 x i32]* @f.b
+  %arrayidx = getelementptr inbounds [1 x i32], [1 x i32]* %p, i64 0, i64 %idxprom
+  %0 = load i32, i32* %arrayidx, align 4
+  ret i32 %0
+
+; CHECK-LABEL: @test3
+; CHECK: getelementptr inbounds [1 x i32], [1 x i32]* %p, i64 0, i64 0
+}
+
+attributes #0 = { nounwind readnone }
+
diff --git a/test/Transforms/InstCombine/memchr.ll b/test/Transforms/InstCombine/memchr.ll
new file mode 100644
index 000000000000..216dba874ccb
--- /dev/null
+++ b/test/Transforms/InstCombine/memchr.ll
@@ -0,0 +1,200 @@
+; Test that the memchr library call simplifier works correctly.
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
+
+@hello = constant [14 x i8] c"hello world\5Cn\00"
+@hellonull = constant [14 x i8] c"hello\00world\5Cn\00"
+@null = constant [1 x i8] zeroinitializer
+@newlines = constant [3 x i8] c"\0D\0A\00"
+@single = constant [2 x i8] c"\1F\00"
+@spaces = constant [4 x i8] c" \0D\0A\00"
+@negative = constant [3 x i8] c"\FF\FE\00"
+@chp = global i8* zeroinitializer
+
+declare i8* @memchr(i8*, i32, i32)
+
+define void @test1() {
+; CHECK-LABEL: @test1
+; CHECK: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hello, i32 0, i32 6)
+; CHECK-NOT: call i8* @memchr
+; CHECK: ret void
+
+  %str = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
+  %dst = call i8* @memchr(i8* %str, i32 119, i32 14)
+  store i8* %dst, i8** @chp
+  ret void
+}
+
+define void @test2() {
+; CHECK-LABEL: @test2
+; CHECK: store i8* null, i8** @chp, align 4
+; CHECK-NOT: call i8* @memchr
+; CHECK: ret void
+
+  %str = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
+  %dst = call i8* @memchr(i8* %str, i32 119, i32 1)
+  store i8* %dst, i8** @chp
+  ret void
+}
+
+define void @test3() {
+; CHECK-LABEL: @test3
+; CHECK: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hello, i32 0, i32 13)
+; CHECK-NOT: call i8* @memchr
+; CHECK: ret void
+
+  %src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
+  %dst = call i8* @memchr(i8* %src, i32 0, i32 14)
+  store i8* %dst, i8** @chp
+  ret void
+}
+
+define void @test4(i32 %chr) {
+; CHECK-LABEL: @test4
+; CHECK: call i8* @memchr
+; CHECK-NOT: call i8* @memchr
+; CHECK: ret void
+
+  %src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
+  %dst = call i8* @memchr(i8* %src, i32 %chr, i32 14)
+  store i8* %dst, i8** @chp
+  ret void
+}
+
+define void @test5() {
+; CHECK-LABEL: @test5
+; CHECK: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hello, i32 0, i32 13)
+; CHECK-NOT: call i8* @memchr
+; CHECK: ret void
+
+  %src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
+  %dst = call i8* @memchr(i8* %src, i32 65280, i32 14)
+  store i8* %dst, i8** @chp
+  ret void
+}
+
+define void @test6() {
+; CHECK-LABEL: @test6
+; CHECK: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hello, i32 0, i32 6)
+; CHECK-NOT: call i8* @memchr
+; CHECK: ret void
+
+  %src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
+; Overflow, but we still find the right thing.
+  %dst = call i8* @memchr(i8* %src, i32 119, i32 100)
+  store i8* %dst, i8** @chp
+  ret void
+}
+
+define void @test7() {
+; CHECK-LABEL: @test7
+; CHECK: store i8* null, i8** @chp, align 4
+; CHECK-NOT: call i8* @memchr
+; CHECK: ret void
+
+  %src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
+; Overflow
+  %dst = call i8* @memchr(i8* %src, i32 120, i32 100)
+  store i8* %dst, i8** @chp
+  ret void
+}
+
+define void @test8() {
+; CHECK-LABEL: @test8
+; CHECK: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hellonull, i32 0, i32 6)
+; CHECK-NOT: call i8* @memchr
+; CHECK: ret void
+
+  %str = getelementptr [14 x i8], [14 x i8]* @hellonull, i32 0, i32 0
+  %dst = call i8* @memchr(i8* %str, i32 119, i32 14)
+  store i8* %dst, i8** @chp
+  ret void
+}
+
+define void @test9() {
+; CHECK-LABEL: @test9
+; CHECK: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hellonull, i32 0, i32 6)
+; CHECK-NOT: call i8* @memchr
+; CHECK: ret void
+
+  %str = getelementptr [14 x i8], [14 x i8]* @hellonull, i32 0, i32 2
+  %dst = call i8* @memchr(i8* %str, i32 119, i32 12)
+  store i8* %dst, i8** @chp
+  ret void
+}
+
+define void @test10() {
+; CHECK-LABEL: @test10
+; CHECK: store i8* null, i8** @chp, align 4
+; CHECK-NOT: call i8* @memchr
+; CHECK: ret void
+
+  %str = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
+  %dst = call i8* @memchr(i8* %str, i32 119, i32 6)
+  store i8* %dst, i8** @chp
+  ret void
+}
+
+; Check transformation memchr("\r\n", C, 2) != nullptr -> (C & 9216) != 0
+define i1 @test11(i32 %C) {
+; CHECK-LABEL: @test11
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 %C to i16
+; CHECK-NEXT: %memchr.bounds = icmp ult i16 [[TRUNC]], 16
+; CHECK-NEXT: [[SHL:%.*]] = shl i16 1, [[TRUNC]]
+; CHECK-NEXT: [[AND:%.*]] = and i16 [[SHL]], 9216
+; CHECK-NEXT: %memchr.bits = icmp ne i16 [[AND]], 0
+; CHECK-NEXT: %memchr = and i1 %memchr.bounds, %memchr.bits
+; CHECK-NEXT: ret i1 %memchr
+
+  %dst = call i8* @memchr(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @newlines, i64 0, i64 0), i32 %C, i32 2)
+  %cmp = icmp ne i8* %dst, null
+  ret i1 %cmp
+}
+
+; No 64 bits here
+define i1 @test12(i32 %C) {
+; CHECK-LABEL: @test12
+; CHECK-NEXT: %dst = call i8* @memchr(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @spaces, i32 0, i32 0), i32 %C, i32 3)
+; CHECK-NEXT: %cmp = icmp ne i8* %dst, null
+; CHECK-NEXT: ret i1 %cmp
+
+  %dst = call i8* @memchr(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @spaces, i64 0, i64 0), i32 %C, i32 3)
+  %cmp = icmp ne i8* %dst, null
+  ret i1 %cmp
+}
+
+define i1 @test13(i32 %C) {
+; CHECK-LABEL: @test13
+; CHECK-NEXT: %memchr.bounds = icmp ult i32 %C, 32
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, %C
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], -2147483647
+; CHECK-NEXT: %memchr.bits = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: %memchr = and i1 %memchr.bounds, %memchr.bits
+; CHECK-NEXT: ret i1 %memchr
+
+  %dst = call i8* @memchr(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @single, i64 0, i64 0), i32 %C, i32 2)
+  %cmp = icmp ne i8* %dst, null
+  ret i1 %cmp
+}
+
+define i1 @test14(i32 %C) {
+; CHECK-LABEL: @test14
+; CHECK-NEXT: icmp eq i32 %C, 31
+; CHECK-NEXT: ret
+
+  %dst = call i8* @memchr(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @single, i64 0, i64 0), i32 %C, i32 1)
+  %cmp = icmp ne i8* %dst, null
+  ret i1 %cmp
+}
+
+define i1 @test15(i32 %C) {
+; CHECK-LABEL: @test15
+; CHECK-NEXT: %dst = call i8* @memchr(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @negative, i32 0, i32 0), i32 %C, i32 3)
+; CHECK-NEXT: %cmp = icmp ne i8* %dst, null
+; CHECK-NEXT: ret i1 %cmp
+
+  %dst = call i8* @memchr(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @negative, i64 0, i64 0), i32 %C, i32 3)
+  %cmp = icmp ne i8* %dst, null
+  ret i1 %cmp
+}
diff --git a/test/Transforms/InstCombine/memcmp-1.ll b/test/Transforms/InstCombine/memcmp-1.ll
index d960693a05d4..db15bd66b715 100644
--- a/test/Transforms/InstCombine/memcmp-1.ll
+++ b/test/Transforms/InstCombine/memcmp-1.ll
@@ -33,9 +33,9 @@ define i32 @test_simplify2(i8* %mem1, i8* %mem2) {
 define i32 @test_simplify3(i8* %mem1, i8* %mem2) {
 ; CHECK-LABEL: @test_simplify3(
   %ret = call i32 @memcmp(i8* %mem1, i8* %mem2, i32 1)
-; CHECK: [[LOAD1:%[a-z]+]] = load i8* %mem1, align 1
+; CHECK: [[LOAD1:%[a-z]+]] = load i8, i8* %mem1, align 1
 ; CHECK: [[ZEXT1:%[a-z]+]] = zext i8 [[LOAD1]] to i32
-; CHECK: [[LOAD2:%[a-z]+]] = load i8* %mem2, align 1
+; CHECK: [[LOAD2:%[a-z]+]] = load i8, i8* %mem2, align 1
 ; CHECK: [[ZEXT2:%[a-z]+]] = zext i8 [[LOAD2]] to i32
 ; CHECK: [[RET:%[a-z]+]] = sub nsw i32 [[ZEXT1]], [[ZEXT2]]
   ret i32 %ret
@@ -46,8 +46,8 @@ define i32 @test_simplify3(i8* %mem1, i8* %mem2) {
 
 define i32 @test_simplify4() {
 ; CHECK-LABEL: @test_simplify4(
-  %mem1 = getelementptr [4 x i8]* @hel, i32 0, i32 0
-  %mem2 = getelementptr [8 x i8]* @hello_u, i32 0, i32 0
+  %mem1 = getelementptr [4 x i8], [4 x i8]* @hel, i32 0, i32 0
+  %mem2 = getelementptr [8 x i8], [8 x i8]* @hello_u, i32 0, i32 0
   %ret = call i32 @memcmp(i8* %mem1, i8* %mem2, i32 3)
   ret i32 %ret
 ; CHECK: ret i32 0
@@ -55,8 +55,8 @@ define i32 @test_simplify4() {
 
 define i32 @test_simplify5() {
 ; CHECK-LABEL: @test_simplify5(
-  %mem1 = getelementptr [4 x i8]* @hel, i32 0, i32 0
-  %mem2 = getelementptr [4 x i8]* @foo, i32 0, i32 0
+  %mem1 = getelementptr [4 x i8], [4 x i8]* @hel, i32 0, i32 0
+  %mem2 = getelementptr [4 x i8], [4 x i8]* @foo, i32 0, i32 0
   %ret = call i32 @memcmp(i8* %mem1, i8* %mem2, i32 3)
   ret i32 %ret
 ; CHECK: ret i32 1
@@ -64,8 +64,8 @@ define i32 @test_simplify5() {
 
 define i32 @test_simplify6() {
 ; CHECK-LABEL: @test_simplify6(
-  %mem1 = getelementptr [4 x i8]* @foo, i32 0, i32 0
-  %mem2 = getelementptr [4 x i8]* @hel, i32 0, i32 0
+  %mem1 = getelementptr [4 x i8], [4 x i8]* @foo, i32 0, i32 0
+  %mem2 = getelementptr [4 x i8], [4 x i8]* @hel, i32 0, i32 0
   %ret = call i32 @memcmp(i8* %mem1, i8* %mem2, i32 3)
   ret i32 %ret
 ; CHECK: ret i32 -1
diff --git a/test/Transforms/InstCombine/memcpy-from-global.ll b/test/Transforms/InstCombine/memcpy-from-global.ll
index 3bc1d36f486d..da38087d7397 100644
--- a/test/Transforms/InstCombine/memcpy-from-global.ll
+++ b/test/Transforms/InstCombine/memcpy-from-global.ll
@@ -14,23 +14,23 @@ entry:
 
 	%tmp3 = shl i32 %hash, 2		; <i32> [#uses=1]
 	%tmp5 = and i32 %tmp3, 124		; <i32> [#uses=4]
-	%tmp753 = getelementptr [128 x float]* %lookupTable, i32 0, i32 %tmp5		; <float*> [#uses=1]
-	%tmp9 = load float* %tmp753		; <float> [#uses=1]
+	%tmp753 = getelementptr [128 x float], [128 x float]* %lookupTable, i32 0, i32 %tmp5		; <float*> [#uses=1]
+	%tmp9 = load float, float* %tmp753		; <float> [#uses=1]
 	%tmp11 = fmul float %tmp9, %x		; <float> [#uses=1]
 	%tmp13 = fadd float %tmp11, 0.000000e+00		; <float> [#uses=1]
 	%tmp17.sum52 = or i32 %tmp5, 1		; <i32> [#uses=1]
-	%tmp1851 = getelementptr [128 x float]* %lookupTable, i32 0, i32 %tmp17.sum52		; <float*> [#uses=1]
-	%tmp19 = load float* %tmp1851		; <float> [#uses=1]
+	%tmp1851 = getelementptr [128 x float], [128 x float]* %lookupTable, i32 0, i32 %tmp17.sum52		; <float*> [#uses=1]
+	%tmp19 = load float, float* %tmp1851		; <float> [#uses=1]
 	%tmp21 = fmul float %tmp19, %y		; <float> [#uses=1]
 	%tmp23 = fadd float %tmp21, %tmp13		; <float> [#uses=1]
 	%tmp27.sum50 = or i32 %tmp5, 2		; <i32> [#uses=1]
-	%tmp2849 = getelementptr [128 x float]* %lookupTable, i32 0, i32 %tmp27.sum50		; <float*> [#uses=1]
-	%tmp29 = load float* %tmp2849		; <float> [#uses=1]
+	%tmp2849 = getelementptr [128 x float], [128 x float]* %lookupTable, i32 0, i32 %tmp27.sum50		; <float*> [#uses=1]
+	%tmp29 = load float, float* %tmp2849		; <float> [#uses=1]
 	%tmp31 = fmul float %tmp29, %z		; <float> [#uses=1]
 	%tmp33 = fadd float %tmp31, %tmp23		; <float> [#uses=1]
 	%tmp37.sum48 = or i32 %tmp5, 3		; <i32> [#uses=1]
-	%tmp3847 = getelementptr [128 x float]* %lookupTable, i32 0, i32 %tmp37.sum48		; <float*> [#uses=1]
-	%tmp39 = load float* %tmp3847		; <float> [#uses=1]
+	%tmp3847 = getelementptr [128 x float], [128 x float]* %lookupTable, i32 0, i32 %tmp37.sum48		; <float*> [#uses=1]
+	%tmp39 = load float, float* %tmp3847		; <float> [#uses=1]
 	%tmp41 = fmul float %tmp39, %w		; <float> [#uses=1]
 	%tmp43 = fadd float %tmp41, %tmp33		; <float> [#uses=1]
 	ret float %tmp43
@@ -57,10 +57,10 @@ define void @test2() {
 
 ; %A alloca is deleted
 ; CHECK-NEXT: alloca [124 x i8]
-; CHECK-NEXT: getelementptr inbounds [124 x i8]*
+; CHECK-NEXT: getelementptr inbounds [124 x i8], [124 x i8]*
 
 ; use @G instead of %A
-; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* getelementptr inbounds (%T* @G, i64 0, i32 0)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* getelementptr inbounds (%T, %T* @G, i64 0, i32 0)
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%T* @G to i8*), i64 124, i32 4, i1 false)
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %b, i8* %a, i64 124, i32 4, i1 false)
   call void @bar(i8* %b)
@@ -101,7 +101,7 @@ define void @test3() {
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%T* @G to i8*), i64 124, i32 4, i1 false)
   call void @bar(i8* %a) readonly
 ; CHECK-LABEL: @test3(
-; CHECK-NEXT: call void @bar(i8* getelementptr inbounds (%T* @G, i64 0, i32 0))
+; CHECK-NEXT: call void @bar(i8* getelementptr inbounds (%T, %T* @G, i64 0, i32 0))
   ret void
 }
 
@@ -111,7 +111,7 @@ define void @test3_addrspacecast() {
   call void @llvm.memcpy.p0i8.p1i8.i64(i8* %a, i8 addrspace(1)* addrspacecast (%T* @G to i8 addrspace(1)*), i64 124, i32 4, i1 false)
   call void @bar(i8* %a) readonly
 ; CHECK-LABEL: @test3_addrspacecast(
-; CHECK-NEXT: call void @bar(i8* getelementptr inbounds (%T* @G, i64 0, i32 0))
+; CHECK-NEXT: call void @bar(i8* getelementptr inbounds (%T, %T* @G, i64 0, i32 0))
   ret void
 }
 
@@ -122,7 +122,7 @@ define void @test4() {
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%T* @G to i8*), i64 124, i32 4, i1 false)
   call void @baz(i8* byval %a)
 ; CHECK-LABEL: @test4(
-; CHECK-NEXT: call void @baz(i8* byval getelementptr inbounds (%T* @G, i64 0, i32 0))
+; CHECK-NEXT: call void @baz(i8* byval getelementptr inbounds (%T, %T* @G, i64 0, i32 0))
   ret void
 }
 
@@ -134,7 +134,7 @@ define void @test5() {
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%T* @G to i8*), i64 124, i32 4, i1 false)
   call void @baz(i8* byval %a)
 ; CHECK-LABEL: @test5(
-; CHECK-NEXT: call void @baz(i8* byval getelementptr inbounds (%T* @G, i64 0, i32 0))
+; CHECK-NEXT: call void @baz(i8* byval getelementptr inbounds (%T, %T* @G, i64 0, i32 0))
   ret void
 }
 
@@ -155,7 +155,7 @@ define void @test6() {
 define void @test7() {
   %A = alloca %U, align 16
   %a = bitcast %U* %A to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%U* getelementptr ([2 x %U]* @H, i64 0, i32 0) to i8*), i64 20, i32 4, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%U* getelementptr ([2 x %U], [2 x %U]* @H, i64 0, i32 0) to i8*), i64 20, i32 4, i1 false)
   call void @bar(i8* %a) readonly
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT: call void @bar(i8* bitcast ([2 x %U]* @H to i8*))
@@ -165,7 +165,7 @@ define void @test7() {
 define void @test8() {
   %A = alloca %U, align 16
   %a = bitcast %U* %A to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%U* getelementptr ([2 x %U]* @H, i64 0, i32 1) to i8*), i64 20, i32 4, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%U* getelementptr ([2 x %U], [2 x %U]* @H, i64 0, i32 1) to i8*), i64 20, i32 4, i1 false)
   call void @bar(i8* %a) readonly
 ; CHECK-LABEL: @test8(
 ; CHECK: llvm.memcpy
@@ -177,7 +177,7 @@ define void @test8() {
 define void @test8_addrspacecast() {
   %A = alloca %U, align 16
   %a = bitcast %U* %A to i8*
-  call void @llvm.memcpy.p0i8.p1i8.i64(i8* %a, i8 addrspace(1)* addrspacecast (%U* getelementptr ([2 x %U]* @H, i64 0, i32 1) to i8 addrspace(1)*), i64 20, i32 4, i1 false)
+  call void @llvm.memcpy.p0i8.p1i8.i64(i8* %a, i8 addrspace(1)* addrspacecast (%U* getelementptr ([2 x %U], [2 x %U]* @H, i64 0, i32 1) to i8 addrspace(1)*), i64 20, i32 4, i1 false)
   call void @bar(i8* %a) readonly
 ; CHECK-LABEL: @test8_addrspacecast(
 ; CHECK: llvm.memcpy
@@ -188,19 +188,19 @@ define void @test8_addrspacecast() {
 define void @test9() {
   %A = alloca %U, align 4
   %a = bitcast %U* %A to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%U* getelementptr ([2 x %U]* @H, i64 0, i32 1) to i8*), i64 20, i32 4, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%U* getelementptr ([2 x %U], [2 x %U]* @H, i64 0, i32 1) to i8*), i64 20, i32 4, i1 false)
   call void @bar(i8* %a) readonly
 ; CHECK-LABEL: @test9(
-; CHECK-NEXT: call void @bar(i8* bitcast (%U* getelementptr inbounds ([2 x %U]* @H, i64 0, i64 1) to i8*))
+; CHECK-NEXT: call void @bar(i8* bitcast (%U* getelementptr inbounds ([2 x %U], [2 x %U]* @H, i64 0, i64 1) to i8*))
   ret void
 }
 
 define void @test9_addrspacecast() {
   %A = alloca %U, align 4
   %a = bitcast %U* %A to i8*
-  call void @llvm.memcpy.p0i8.p1i8.i64(i8* %a, i8 addrspace(1)* addrspacecast (%U* getelementptr ([2 x %U]* @H, i64 0, i32 1) to i8 addrspace(1)*), i64 20, i32 4, i1 false)
+  call void @llvm.memcpy.p0i8.p1i8.i64(i8* %a, i8 addrspace(1)* addrspacecast (%U* getelementptr ([2 x %U], [2 x %U]* @H, i64 0, i32 1) to i8 addrspace(1)*), i64 20, i32 4, i1 false)
   call void @bar(i8* %a) readonly
 ; CHECK-LABEL: @test9_addrspacecast(
-; CHECK-NEXT: call void @bar(i8* bitcast (%U* getelementptr inbounds ([2 x %U]* @H, i64 0, i64 1) to i8*))
+; CHECK-NEXT: call void @bar(i8* bitcast (%U* getelementptr inbounds ([2 x %U], [2 x %U]* @H, i64 0, i64 1) to i8*))
   ret void
 }
diff --git a/test/Transforms/InstCombine/memmove.ll b/test/Transforms/InstCombine/memmove.ll
index 9d51ea0e70bb..96f230eece06 100644
--- a/test/Transforms/InstCombine/memmove.ll
+++ b/test/Transforms/InstCombine/memmove.ll
@@ -14,16 +14,16 @@ define void @test1(i8* %A, i8* %B, i32 %N) {
 
 define void @test2(i8* %A, i32 %N) {
         ;; dest can't alias source since we can't write to source!
-	call void @llvm.memmove.p0i8.p0i8.i32(i8* %A, i8* getelementptr inbounds ([33 x i8]* @S, i32 0, i32 0), i32 %N, i32 1, i1 false)
+	call void @llvm.memmove.p0i8.p0i8.i32(i8* %A, i8* getelementptr inbounds ([33 x i8], [33 x i8]* @S, i32 0, i32 0), i32 %N, i32 1, i1 false)
 	ret void
 }
 
 define i32 @test3() {
-	%h_p = getelementptr [2 x i8]* @h, i32 0, i32 0		; <i8*> [#uses=1]
-	%hel_p = getelementptr [4 x i8]* @hel, i32 0, i32 0		; <i8*> [#uses=1]
-	%hello_u_p = getelementptr [8 x i8]* @hello_u, i32 0, i32 0		; <i8*> [#uses=1]
+	%h_p = getelementptr [2 x i8], [2 x i8]* @h, i32 0, i32 0		; <i8*> [#uses=1]
+	%hel_p = getelementptr [4 x i8], [4 x i8]* @hel, i32 0, i32 0		; <i8*> [#uses=1]
+	%hello_u_p = getelementptr [8 x i8], [8 x i8]* @hello_u, i32 0, i32 0		; <i8*> [#uses=1]
 	%target = alloca [1024 x i8]		; <[1024 x i8]*> [#uses=1]
-	%target_p = getelementptr [1024 x i8]* %target, i32 0, i32 0		; <i8*> [#uses=3]
+	%target_p = getelementptr [1024 x i8], [1024 x i8]* %target, i32 0, i32 0		; <i8*> [#uses=3]
         call void @llvm.memmove.p0i8.p0i8.i32(i8* %target_p, i8* %h_p, i32 2, i32 2, i1 false)
         call void @llvm.memmove.p0i8.p0i8.i32(i8* %target_p, i8* %hel_p, i32 4, i32 4, i1 false)
         call void @llvm.memmove.p0i8.p0i8.i32(i8* %target_p, i8* %hello_u_p, i32 8, i32 8, i1 false)
diff --git a/test/Transforms/InstCombine/memset.ll b/test/Transforms/InstCombine/memset.ll
index 7f02dad58a7a..dfafcf948d1c 100644
--- a/test/Transforms/InstCombine/memset.ll
+++ b/test/Transforms/InstCombine/memset.ll
@@ -2,7 +2,7 @@
 
 define i32 @main() {
   %target = alloca [1024 x i8]
-  %target_p = getelementptr [1024 x i8]* %target, i32 0, i32 0
+  %target_p = getelementptr [1024 x i8], [1024 x i8]* %target, i32 0, i32 0
   call void @llvm.memset.p0i8.i32(i8* %target_p, i8 1, i32 0, i32 1, i1 false)
   call void @llvm.memset.p0i8.i32(i8* %target_p, i8 1, i32 1, i32 1, i1 false)
   call void @llvm.memset.p0i8.i32(i8* %target_p, i8 1, i32 2, i32 2, i1 false)
diff --git a/test/Transforms/InstCombine/memset2.ll b/test/Transforms/InstCombine/memset2.ll
index 87639f0d6a22..ad4c225846bf 100644
--- a/test/Transforms/InstCombine/memset2.ll
+++ b/test/Transforms/InstCombine/memset2.ll
@@ -7,7 +7,7 @@
 define i32 @test(%struct.Moves addrspace(1)* nocapture %moves) {
 entry:
 ; CHECK: bitcast i8 addrspace(1)* %gep to i64 addrspace(1)*
-	%gep = getelementptr inbounds %struct.Moves addrspace(1)* %moves, i32 1, i32 0, i32 9
+	%gep = getelementptr inbounds %struct.Moves, %struct.Moves addrspace(1)* %moves, i32 1, i32 0, i32 9
 	 call void @llvm.memset.p1i8.i64(i8 addrspace(1)* %gep, i8 0, i64 8, i32 1, i1 false)                                                                     
 	ret i32 0
 }
diff --git a/test/Transforms/InstCombine/merge-icmp.ll b/test/Transforms/InstCombine/merge-icmp.ll
index b021fe0429a5..6a65b5befa38 100644
--- a/test/Transforms/InstCombine/merge-icmp.ll
+++ b/test/Transforms/InstCombine/merge-icmp.ll
@@ -1,7 +1,7 @@
 ; RUN: opt -S -instcombine < %s | FileCheck %s
 
 define i1 @test1(i16* %x) {
-  %load = load i16* %x, align 4
+  %load = load i16, i16* %x, align 4
   %trunc = trunc i16 %load to i8
   %cmp1 = icmp eq i8 %trunc, 127
   %and = and i16 %load, -256
@@ -15,7 +15,7 @@ define i1 @test1(i16* %x) {
 }
 
 define i1 @test2(i16* %x) {
-  %load = load i16* %x, align 4
+  %load = load i16, i16* %x, align 4
   %and = and i16 %load, -256
   %cmp1 = icmp eq i16 %and, 32512
   %trunc = trunc i16 %load to i8
diff --git a/test/Transforms/InstCombine/minmax-fold.ll b/test/Transforms/InstCombine/minmax-fold.ll
new file mode 100644
index 000000000000..4ed0c78216d6
--- /dev/null
+++ b/test/Transforms/InstCombine/minmax-fold.ll
@@ -0,0 +1,112 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+; CHECK-LABEL: @t1
+; CHECK-NEXT: icmp
+; CHECK-NEXT: select
+; CHECK-NEXT: sext
+define i64 @t1(i32 %a) {
+  ; This is the canonical form for a type-changing min/max.
+  %1 = icmp slt i32 %a, 5
+  %2 = select i1 %1, i32 %a, i32 5
+  %3 = sext i32 %2 to i64
+  ret i64 %3
+}
+
+; CHECK-LABEL: @t2
+; CHECK-NEXT: icmp
+; CHECK-NEXT: select
+; CHECK-NEXT: sext
+define i64 @t2(i32 %a) {
+  ; Check this is converted into canonical form, as above.
+  %1 = icmp slt i32 %a, 5
+  %2 = sext i32 %a to i64
+  %3 = select i1 %1, i64 %2, i64 5
+  ret i64 %3
+}
+
+; CHECK-LABEL: @t3
+; CHECK-NEXT: icmp
+; CHECK-NEXT: select
+; CHECK-NEXT: zext
+define i64 @t3(i32 %a) {
+  ; Same as @t2, with flipped operands and zext instead of sext.
+  %1 = icmp ult i32 %a, 5
+  %2 = zext i32 %a to i64
+  %3 = select i1 %1, i64 5, i64 %2
+  ret i64 %3
+}
+
+; CHECK-LABEL: @t4
+; CHECK-NEXT: icmp
+; CHECK-NEXT: select
+; CHECK-NEXT: trunc
+define i32 @t4(i64 %a) {
+  ; Same again, with trunc.
+  %1 = icmp slt i64 %a, 5
+  %2 = trunc i64 %a to i32
+  %3 = select i1 %1, i32 %2, i32 5
+  ret i32 %3
+}
+
+; CHECK-LABEL: @t5
+; CHECK-NEXT: icmp
+; CHECK-NEXT: zext
+; CHECK-NEXT: select
+define i64 @t5(i32 %a) {
+  ; Same as @t3, but with mismatched signedness between icmp and zext.
+  ; InstCombine should leave this alone.
+  %1 = icmp slt i32 %a, 5
+  %2 = zext i32 %a to i64
+  %3 = select i1 %1, i64 5, i64 %2
+  ret i64 %3
+}
+
+; CHECK-LABEL: @t6
+; CHECK-NEXT: icmp
+; CHECK-NEXT: select
+; CHECK-NEXT: sitofp
+define float @t6(i32 %a) {
+  %1 = icmp slt i32 %a, 0
+  %2 = select i1 %1, i32 %a, i32 0
+  %3 = sitofp i32 %2 to float
+  ret float %3
+}
+
+; CHECK-LABEL: @t7
+; CHECK-NEXT: icmp
+; CHECK-NEXT: select
+; CHECK-NEXT: trunc
+define i16 @t7(i32 %a) {
+  %1 = icmp slt i32 %a, -32768
+  %2 = trunc i32 %a to i16
+  %3 = select i1 %1, i16 %2, i16 -32768
+  ret i16 %3
+}
+
+; Just check for no infinite loop. InstSimplify liked to
+; "simplify" -32767 by removing all the sign bits,
+; which led to a canonicalization fight between different
+; parts of instcombine.
+define i32 @t8(i64 %a, i32 %b) {
+  %1 = icmp slt i64 %a, -32767
+  %2 = select i1 %1, i64 %a, i64 -32767
+  %3 = trunc i64 %2 to i32
+  %4 = icmp slt i32 %b, 42
+  %5 = select i1 %4, i32 42, i32 %3
+  %6 = icmp ne i32 %5, %b
+  %7 = zext i1 %6 to i32
+  ret i32 %7
+}
+
+; Ensure this doesn't get converted to a min/max.
+; CHECK-LABEL: @t9
+; CHECK-NEXT: icmp
+; CHECK-NEXT: sext
+; CHECK-NEXT: 4294967295
+; CHECK-NEXT: ret
+define i64 @t9(i32 %a) {
+  %1 = icmp sgt i32 %a, -1
+  %2 = sext i32 %a to i64
+  %3 = select i1 %1, i64 %2, i64 4294967295
+  ret i64 %3
+}
diff --git a/test/Transforms/InstCombine/mul.ll b/test/Transforms/InstCombine/mul.ll
index 4d1e6c700bda..6e67c7fa08a0 100644
--- a/test/Transforms/InstCombine/mul.ll
+++ b/test/Transforms/InstCombine/mul.ll
@@ -107,7 +107,7 @@ define i32 @test12(i32 %a, i32 %b) {
 ; PR2642
 define internal void @test13(<4 x float>*) {
 ; CHECK-LABEL: @test13(
-	load <4 x float>* %0, align 1
+	load <4 x float>, <4 x float>* %0, align 1
 	fmul <4 x float> %2, < float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 >
 	store <4 x float> %3, <4 x float>* %0, align 1
 	ret void
@@ -288,3 +288,19 @@ define i32 @test31(i32 %V) {
 ; CHECK:      %[[mul:.*]] = shl i32 %V, zext (i1 icmp ne (i32* inttoptr (i64 1 to i32*), i32* @PR22087) to i32)
 ; CHECK-NEXT: ret i32 %[[mul]]
 }
+
+define i32 @test32(i32 %X) {
+; CHECK-LABEL: @test32
+  %mul = mul nsw i32 %X, -2147483648
+  ret i32 %mul
+; CHECK:      %[[shl:.*]] = shl i32 %X, 31
+; CHECK-NEXT: ret i32 %[[shl]]
+}
+
+define i32 @test33(i32 %X) {
+; CHECK-LABEL: @test33
+  %mul = mul nsw i32 %X, 1073741824
+; CHECK:      %[[shl:.*]] = shl nsw i32 %X, 30
+; CHECK-NEXT: ret i32 %[[shl]]
+  ret i32 %mul
+}
diff --git a/test/Transforms/InstCombine/multi-size-address-space-pointer.ll b/test/Transforms/InstCombine/multi-size-address-space-pointer.ll
index 2d88bed4e7bf..4e5b2100f34a 100644
--- a/test/Transforms/InstCombine/multi-size-address-space-pointer.ll
+++ b/test/Transforms/InstCombine/multi-size-address-space-pointer.ll
@@ -4,43 +4,43 @@ target datalayout = "e-p:32:32:32-p1:64:64:64-p2:8:8:8-p3:16:16:16-p4:16:16:16-i
 
 define i32 @test_as0(i32 addrspace(0)* %a) {
 ; CHECK-LABEL: @test_as0(
-; CHECK: %arrayidx = getelementptr i32* %a, i32 1
-  %arrayidx = getelementptr i32 addrspace(0)* %a, i64 1
-  %y = load i32 addrspace(0)* %arrayidx, align 4
+; CHECK: %arrayidx = getelementptr i32, i32* %a, i32 1
+  %arrayidx = getelementptr i32, i32 addrspace(0)* %a, i64 1
+  %y = load i32, i32 addrspace(0)* %arrayidx, align 4
   ret i32 %y
 }
 
 define i32 @test_as1(i32 addrspace(1)* %a) {
 ; CHECK-LABEL: @test_as1(
-; CHECK: %arrayidx = getelementptr i32 addrspace(1)* %a, i64 1
-  %arrayidx = getelementptr i32 addrspace(1)* %a, i32 1
-  %y = load i32 addrspace(1)* %arrayidx, align 4
+; CHECK: %arrayidx = getelementptr i32, i32 addrspace(1)* %a, i64 1
+  %arrayidx = getelementptr i32, i32 addrspace(1)* %a, i32 1
+  %y = load i32, i32 addrspace(1)* %arrayidx, align 4
   ret i32 %y
 }
 
 define i32 @test_as2(i32 addrspace(2)* %a) {
 ; CHECK-LABEL: @test_as2(
-; CHECK: %arrayidx = getelementptr i32 addrspace(2)* %a, i8 1
-  %arrayidx = getelementptr i32 addrspace(2)* %a, i32 1
-  %y = load i32 addrspace(2)* %arrayidx, align 4
+; CHECK: %arrayidx = getelementptr i32, i32 addrspace(2)* %a, i8 1
+  %arrayidx = getelementptr i32, i32 addrspace(2)* %a, i32 1
+  %y = load i32, i32 addrspace(2)* %arrayidx, align 4
   ret i32 %y
 }
 
 define i32 @test_as3(i32 addrspace(3)* %a) {
 ; CHECK-LABEL: @test_as3(
-; CHECK: %arrayidx = getelementptr i32 addrspace(3)* %a, i16 1
-  %arrayidx = getelementptr i32 addrspace(3)* %a, i32 1
-  %y = load i32 addrspace(3)* %arrayidx, align 4
+; CHECK: %arrayidx = getelementptr i32, i32 addrspace(3)* %a, i16 1
+  %arrayidx = getelementptr i32, i32 addrspace(3)* %a, i32 1
+  %y = load i32, i32 addrspace(3)* %arrayidx, align 4
   ret i32 %y
 }
 
 define i32 @test_combine_ptrtoint(i32 addrspace(2)* %a) {
 ; CHECK-LABEL: @test_combine_ptrtoint(
-; CHECK-NEXT: %y = load i32 addrspace(2)* %a
+; CHECK-NEXT: %y = load i32, i32 addrspace(2)* %a
 ; CHECK-NEXT: ret i32 %y
   %cast = ptrtoint i32 addrspace(2)* %a to i8
   %castback = inttoptr i8 %cast to i32 addrspace(2)*
-  %y = load i32 addrspace(2)* %castback, align 4
+  %y = load i32, i32 addrspace(2)* %castback, align 4
   ret i32 %y
 }
 
@@ -55,12 +55,12 @@ define i8 @test_combine_inttoptr(i8 %a) {
 define i32 @test_combine_vector_ptrtoint(<2 x i32 addrspace(2)*> %a) {
 ; CHECK-LABEL: @test_combine_vector_ptrtoint(
 ; CHECK-NEXT: %p = extractelement <2 x i32 addrspace(2)*> %a, i32 0
-; CHECK-NEXT: %y = load i32 addrspace(2)* %p, align 4
+; CHECK-NEXT: %y = load i32, i32 addrspace(2)* %p, align 4
 ; CHECK-NEXT: ret i32 %y
   %cast = ptrtoint <2 x i32 addrspace(2)*> %a to <2 x i8>
   %castback = inttoptr <2 x i8> %cast to <2 x i32 addrspace(2)*>
   %p = extractelement <2 x i32 addrspace(2)*> %castback, i32 0
-  %y = load i32 addrspace(2)* %p, align 4
+  %y = load i32, i32 addrspace(2)* %p, align 4
   ret i32 %y
 }
 
@@ -75,38 +75,38 @@ define <2 x i8> @test_combine_vector_inttoptr(<2 x i8> %a) {
 ; Check that the GEP index is changed to the address space integer type (i64 -> i8)
 define i32 addrspace(2)* @shrink_gep_constant_index_64_as2(i32 addrspace(2)* %p) {
 ; CHECK-LABEL: @shrink_gep_constant_index_64_as2(
-; CHECK-NEXT: getelementptr i32 addrspace(2)* %p, i8 1
-  %ret = getelementptr i32 addrspace(2)* %p, i64 1
+; CHECK-NEXT: getelementptr i32, i32 addrspace(2)* %p, i8 1
+  %ret = getelementptr i32, i32 addrspace(2)* %p, i64 1
   ret i32 addrspace(2)* %ret
 }
 
 define i32 addrspace(2)* @shrink_gep_constant_index_32_as2(i32 addrspace(2)* %p) {
 ; CHECK-LABEL: @shrink_gep_constant_index_32_as2(
-; CHECK-NEXT: getelementptr i32 addrspace(2)* %p, i8 1
-  %ret = getelementptr i32 addrspace(2)* %p, i32 1
+; CHECK-NEXT: getelementptr i32, i32 addrspace(2)* %p, i8 1
+  %ret = getelementptr i32, i32 addrspace(2)* %p, i32 1
   ret i32 addrspace(2)* %ret
 }
 
 define i32 addrspace(3)* @shrink_gep_constant_index_64_as3(i32 addrspace(3)* %p) {
 ; CHECK-LABEL: @shrink_gep_constant_index_64_as3(
-; CHECK-NEXT: getelementptr i32 addrspace(3)* %p, i16 1
-  %ret = getelementptr i32 addrspace(3)* %p, i64 1
+; CHECK-NEXT: getelementptr i32, i32 addrspace(3)* %p, i16 1
+  %ret = getelementptr i32, i32 addrspace(3)* %p, i64 1
   ret i32 addrspace(3)* %ret
 }
 
 define i32 addrspace(2)* @shrink_gep_variable_index_64_as2(i32 addrspace(2)* %p, i64 %idx) {
 ; CHECK-LABEL: @shrink_gep_variable_index_64_as2(
 ; CHECK-NEXT: %1 = trunc i64 %idx to i8
-; CHECK-NEXT: getelementptr i32 addrspace(2)* %p, i8 %1
-  %ret = getelementptr i32 addrspace(2)* %p, i64 %idx
+; CHECK-NEXT: getelementptr i32, i32 addrspace(2)* %p, i8 %1
+  %ret = getelementptr i32, i32 addrspace(2)* %p, i64 %idx
   ret i32 addrspace(2)* %ret
 }
 
 define i32 addrspace(1)* @grow_gep_variable_index_8_as1(i32 addrspace(1)* %p, i8 %idx) {
 ; CHECK-LABEL: @grow_gep_variable_index_8_as1(
 ; CHECK-NEXT: %1 = sext i8 %idx to i64
-; CHECK-NEXT: getelementptr i32 addrspace(1)* %p, i64 %1
-  %ret = getelementptr i32 addrspace(1)* %p, i8 %idx
+; CHECK-NEXT: getelementptr i32, i32 addrspace(1)* %p, i64 %1
+  %ret = getelementptr i32, i32 addrspace(1)* %p, i8 %idx
   ret i32 addrspace(1)* %ret
 }
 
diff --git a/test/Transforms/InstCombine/no-negzero.ll b/test/Transforms/InstCombine/no-negzero.ll
index 4ed283603446..07e68251b5ae 100644
--- a/test/Transforms/InstCombine/no-negzero.ll
+++ b/test/Transforms/InstCombine/no-negzero.ll
@@ -14,17 +14,17 @@ entry:
   %0 = alloca double, align 8                     ; <double*> [#uses=2]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   store double %x, double* %x_addr
-  %1 = load double* %x_addr, align 8              ; <double> [#uses=1]
+  %1 = load double, double* %x_addr, align 8              ; <double> [#uses=1]
   %2 = call double @fabs(double %1) nounwind readnone ; <double> [#uses=1]
   %3 = call double @sqrt(double %2) nounwind readonly ; <double> [#uses=1]
   %4 = fadd double %3, 0.000000e+00               ; <double> [#uses=1]
   store double %4, double* %0, align 8
-  %5 = load double* %0, align 8                   ; <double> [#uses=1]
+  %5 = load double, double* %0, align 8                   ; <double> [#uses=1]
   store double %5, double* %retval, align 8
   br label %return
 
 return:                                           ; preds = %entry
-  %retval1 = load double* %retval                 ; <double> [#uses=1]
+  %retval1 = load double, double* %retval                 ; <double> [#uses=1]
   ret double %retval1
 }
 
diff --git a/test/Transforms/InstCombine/not.ll b/test/Transforms/InstCombine/not.ll
index 4012ce1ea4ba..9d59edd7934d 100644
--- a/test/Transforms/InstCombine/not.ll
+++ b/test/Transforms/InstCombine/not.ll
@@ -52,3 +52,9 @@ entry:
 	%retval67 = zext i1 %tmp3 to i8		; <i8> [#uses=1]
 	ret i8 %retval67
 }
+
+define <2 x i1> @test7(<2 x i32> %A, <2 x i32> %B) {
+        %cond = icmp sle <2 x i32> %A, %B
+        %Ret = xor <2 x i1> %cond, <i1 true, i1 true>
+        ret <2 x i1> %Ret
+}
diff --git a/test/Transforms/InstCombine/obfuscated_splat.ll b/test/Transforms/InstCombine/obfuscated_splat.ll
index fa9cb423d02c..c37456cc9cfa 100644
--- a/test/Transforms/InstCombine/obfuscated_splat.ll
+++ b/test/Transforms/InstCombine/obfuscated_splat.ll
@@ -1,7 +1,7 @@
 ; RUN: opt -instcombine -S < %s | FileCheck %s
 
 define void @test(<4 x float> *%in_ptr, <4 x float> *%out_ptr) {
-  %A = load <4 x float>* %in_ptr, align 16
+  %A = load <4 x float>, <4 x float>* %in_ptr, align 16
   %B = shufflevector <4 x float> %A, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef>
   %C = shufflevector <4 x float> %B, <4 x float> %A, <4 x i32> <i32 0, i32 1, i32 4, i32 undef>
   %D = shufflevector <4 x float> %C, <4 x float> %A, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
diff --git a/test/Transforms/InstCombine/objsize-address-space.ll b/test/Transforms/InstCombine/objsize-address-space.ll
index a971c913bd41..6046dad89790 100644
--- a/test/Transforms/InstCombine/objsize-address-space.ll
+++ b/test/Transforms/InstCombine/objsize-address-space.ll
@@ -21,20 +21,20 @@ declare i16 @llvm.objectsize.i16.p3i8(i8 addrspace(3)*, i1) nounwind readonly
 define i32 @foo_as3() nounwind {
 ; CHECK-LABEL: @foo_as3(
 ; CHECK-NEXT: ret i32 60
-  %1 = call i32 @llvm.objectsize.i32.p3i8(i8 addrspace(3)* getelementptr inbounds ([60 x i8] addrspace(3)* @a_as3, i32 0, i32 0), i1 false)
+  %1 = call i32 @llvm.objectsize.i32.p3i8(i8 addrspace(3)* getelementptr inbounds ([60 x i8], [60 x i8] addrspace(3)* @a_as3, i32 0, i32 0), i1 false)
   ret i32 %1
 }
 
 define i16 @foo_as3_i16() nounwind {
 ; CHECK-LABEL: @foo_as3_i16(
 ; CHECK-NEXT: ret i16 60
-  %1 = call i16 @llvm.objectsize.i16.p3i8(i8 addrspace(3)* getelementptr inbounds ([60 x i8] addrspace(3)* @a_as3, i32 0, i32 0), i1 false)
+  %1 = call i16 @llvm.objectsize.i16.p3i8(i8 addrspace(3)* getelementptr inbounds ([60 x i8], [60 x i8] addrspace(3)* @a_as3, i32 0, i32 0), i1 false)
   ret i16 %1
 }
 
 @a_alias = weak alias [60 x i8] addrspace(3)* @a_as3
 define i32 @foo_alias() nounwind {
-  %1 = call i32 @llvm.objectsize.i32.p3i8(i8 addrspace(3)* getelementptr inbounds ([60 x i8] addrspace(3)* @a_alias, i32 0, i32 0), i1 false)
+  %1 = call i32 @llvm.objectsize.i32.p3i8(i8 addrspace(3)* getelementptr inbounds ([60 x i8], [60 x i8] addrspace(3)* @a_alias, i32 0, i32 0), i1 false)
   ret i32 %1
 }
 
diff --git a/test/Transforms/InstCombine/objsize-noverify.ll b/test/Transforms/InstCombine/objsize-noverify.ll
new file mode 100644
index 000000000000..7e469bd25282
--- /dev/null
+++ b/test/Transforms/InstCombine/objsize-noverify.ll
@@ -0,0 +1,43 @@
+; Test objectsize bounds checking that won't verify until after -instcombine.
+; RUN: opt < %s -disable-verify -instcombine -S | opt -S | FileCheck %s
+; We need target data to get the sizes of the arrays and structures.
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+
+declare i32 @llvm.objectsize.i32.p0i8(i8*, i1) nounwind readonly
+
+; CHECK-LABEL: @PR13390(
+define i32 @PR13390(i1 %bool, i8* %a) {
+entry:
+  %cond = or i1 %bool, true
+  br i1 %cond, label %return, label %xpto
+
+xpto:
+  %select = select i1 %bool, i8* %select, i8* %a
+  %select2 = select i1 %bool, i8* %a, i8* %select2
+  %0 = tail call i32 @llvm.objectsize.i32.p0i8(i8* %select, i1 true)
+  %1 = tail call i32 @llvm.objectsize.i32.p0i8(i8* %select2, i1 true)
+  %2 = add i32 %0, %1
+; CHECK: ret i32 undef
+  ret i32 %2
+
+return:
+  ret i32 42
+}
+
+; CHECK-LABEL: @PR13621(
+define i32 @PR13621(i1 %bool) nounwind {
+entry:
+  %cond = or i1 %bool, true
+  br i1 %cond, label %return, label %xpto
+
+; technically reachable, but this malformed IR may appear as a result of constant propagation
+xpto:
+  %gep2 = getelementptr i8, i8* %gep, i32 1
+  %gep = getelementptr i8, i8* %gep2, i32 1
+  %o = call i32 @llvm.objectsize.i32.p0i8(i8* %gep, i1 true)
+; CHECK: ret i32 undef
+  ret i32 %o
+
+return:
+  ret i32 7
+}
diff --git a/test/Transforms/InstCombine/objsize.ll b/test/Transforms/InstCombine/objsize.ll
index 1285b1c3aa6a..335a816e9ece 100644
--- a/test/Transforms/InstCombine/objsize.ll
+++ b/test/Transforms/InstCombine/objsize.ll
@@ -8,7 +8,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 define i32 @foo() nounwind {
 ; CHECK-LABEL: @foo(
 ; CHECK-NEXT: ret i32 60
-  %1 = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i1 false)
+  %1 = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i1 false)
   ret i32 %1
 }
 
@@ -16,24 +16,24 @@ define i8* @bar() nounwind {
 ; CHECK-LABEL: @bar(
 entry:
   %retval = alloca i8*
-  %0 = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i1 false)
+  %0 = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i1 false)
   %cmp = icmp ne i32 %0, -1
 ; CHECK: br i1 true
   br i1 %cmp, label %cond.true, label %cond.false
 
 cond.true:
-  %1 = load i8** %retval
+  %1 = load i8*, i8** %retval
   ret i8* %1
 
 cond.false:
-  %2 = load i8** %retval
+  %2 = load i8*, i8** %retval
   ret i8* %2
 }
 
 define i32 @f() nounwind {
 ; CHECK-LABEL: @f(
 ; CHECK-NEXT: ret i32 0
-  %1 = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr ([60 x i8]* @a, i32 1, i32 0), i1 false)
+  %1 = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr ([60 x i8], [60 x i8]* @a, i32 1, i32 0), i1 false)
   ret i32 %1
 }
 
@@ -42,7 +42,7 @@ define i32 @f() nounwind {
 define i1 @baz() nounwind {
 ; CHECK-LABEL: @baz(
 ; CHECK-NEXT: objectsize
-  %1 = tail call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr inbounds ([0 x i8]* @window, i32 0, i32 0), i1 false)
+  %1 = tail call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr inbounds ([0 x i8], [0 x i8]* @window, i32 0, i32 0), i1 false)
   %2 = icmp eq i32 %1, -1
   ret i1 %2
 }
@@ -51,7 +51,7 @@ define void @test1(i8* %q, i32 %x) nounwind noinline {
 ; CHECK-LABEL: @test1(
 ; CHECK: objectsize.i32.p0i8
 entry:
-  %0 = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr inbounds ([0 x i8]* @window, i32 0, i32 10), i1 false) ; <i64> [#uses=1]
+  %0 = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr inbounds ([0 x i8], [0 x i8]* @window, i32 0, i32 10), i1 false) ; <i64> [#uses=1]
   %1 = icmp eq i32 %0, -1                         ; <i1> [#uses=1]
   br i1 %1, label %"47", label %"46"
 
@@ -67,7 +67,7 @@ entry:
 define i32 @test2() nounwind {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT: ret i32 34
-  %1 = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr (i8* bitcast ([9 x i32]* @.str5 to i8*), i32 2), i1 false)
+  %1 = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr (i8, i8* bitcast ([9 x i32]* @.str5 to i8*), i32 2), i1 false)
   ret i32 %1
 }
 
@@ -86,7 +86,7 @@ entry:
   br i1 undef, label %bb11, label %bb12
 
 bb11:
-  %0 = getelementptr inbounds float* getelementptr inbounds ([480 x float]* @array, i32 0, i32 128), i32 -127 ; <float*> [#uses=1]
+  %0 = getelementptr inbounds float, float* getelementptr inbounds ([480 x float], [480 x float]* @array, i32 0, i32 128), i32 -127 ; <float*> [#uses=1]
   %1 = bitcast float* %0 to i8*                   ; <i8*> [#uses=1]
   %2 = call i32 @llvm.objectsize.i32.p0i8(i8* %1, i1 false) ; <i32> [#uses=1]
   %3 = call i8* @__memcpy_chk(i8* undef, i8* undef, i32 512, i32 %2) nounwind ; <i8*> [#uses=0]
@@ -94,7 +94,7 @@ bb11:
   unreachable
 
 bb12:
-  %4 = getelementptr inbounds float* getelementptr inbounds ([480 x float]* @array, i32 0, i32 128), i32 -127 ; <float*> [#uses=1]
+  %4 = getelementptr inbounds float, float* getelementptr inbounds ([480 x float], [480 x float]* @array, i32 0, i32 128), i32 -127 ; <float*> [#uses=1]
   %5 = bitcast float* %4 to i8*                   ; <i8*> [#uses=1]
   %6 = call i8* @__inline_memcpy_chk(i8* %5, i8* undef, i32 512) nounwind inlinehint ; <i8*> [#uses=0]
 ; CHECK: @__inline_memcpy_chk
@@ -126,7 +126,7 @@ define i8* @test5(i32 %n) nounwind ssp {
 entry:
   %0 = tail call noalias i8* @malloc(i32 20) nounwind
   %1 = tail call i32 @llvm.objectsize.i32.p0i8(i8* %0, i1 false)
-  %2 = load i8** @s, align 8
+  %2 = load i8*, i8** @s, align 8
 ; CHECK-NOT: @llvm.objectsize
 ; CHECK: @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* %1, i32 10, i32 1, i1 false)
   %3 = tail call i8* @__memcpy_chk(i8* %0, i8* %2, i32 10, i32 %1) nounwind
@@ -138,7 +138,7 @@ define void @test6(i32 %n) nounwind ssp {
 entry:
   %0 = tail call noalias i8* @malloc(i32 20) nounwind
   %1 = tail call i32 @llvm.objectsize.i32.p0i8(i8* %0, i1 false)
-  %2 = load i8** @s, align 8
+  %2 = load i8*, i8** @s, align 8
 ; CHECK-NOT: @llvm.objectsize
 ; CHECK: @__memcpy_chk(i8* %0, i8* %1, i32 30, i32 20)
   %3 = tail call i8* @__memcpy_chk(i8* %0, i8* %2, i32 30, i32 %1) nounwind
@@ -153,7 +153,7 @@ define i32 @test7(i8** %esc) {
 ; CHECK-LABEL: @test7(
   %alloc = call noalias i8* @malloc(i32 48) nounwind
   store i8* %alloc, i8** %esc
-  %gep = getelementptr inbounds i8* %alloc, i32 16
+  %gep = getelementptr inbounds i8, i8* %alloc, i32 16
   %objsize = call i32 @llvm.objectsize.i32.p0i8(i8* %gep, i1 false) nounwind readonly
 ; CHECK: ret i32 32
   ret i32 %objsize
@@ -165,7 +165,7 @@ define i32 @test8(i8** %esc) {
 ; CHECK-LABEL: @test8(
   %alloc = call noalias i8* @calloc(i32 5, i32 7) nounwind
   store i8* %alloc, i8** %esc
-  %gep = getelementptr inbounds i8* %alloc, i32 5
+  %gep = getelementptr inbounds i8, i8* %alloc, i32 5
   %objsize = call i32 @llvm.objectsize.i32.p0i8(i8* %gep, i1 false) nounwind readonly
 ; CHECK: ret i32 30
   ret i32 %objsize
@@ -176,7 +176,7 @@ declare noalias i8* @strndup(i8* nocapture, i32) nounwind
 
 ; CHECK-LABEL: @test9(
 define i32 @test9(i8** %esc) {
-  %call = tail call i8* @strdup(i8* getelementptr inbounds ([8 x i8]* @.str, i64 0, i64 0)) nounwind
+  %call = tail call i8* @strdup(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0)) nounwind
   store i8* %call, i8** %esc, align 8
   %1 = tail call i32 @llvm.objectsize.i32.p0i8(i8* %call, i1 true)
 ; CHECK: ret i32 8
@@ -185,7 +185,7 @@ define i32 @test9(i8** %esc) {
 
 ; CHECK-LABEL: @test10(
 define i32 @test10(i8** %esc) {
-  %call = tail call i8* @strndup(i8* getelementptr inbounds ([8 x i8]* @.str, i64 0, i64 0), i32 3) nounwind
+  %call = tail call i8* @strndup(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i32 3) nounwind
   store i8* %call, i8** %esc, align 8
   %1 = tail call i32 @llvm.objectsize.i32.p0i8(i8* %call, i1 true)
 ; CHECK: ret i32 4
@@ -194,7 +194,7 @@ define i32 @test10(i8** %esc) {
 
 ; CHECK-LABEL: @test11(
 define i32 @test11(i8** %esc) {
-  %call = tail call i8* @strndup(i8* getelementptr inbounds ([8 x i8]* @.str, i64 0, i64 0), i32 7) nounwind
+  %call = tail call i8* @strndup(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i32 7) nounwind
   store i8* %call, i8** %esc, align 8
   %1 = tail call i32 @llvm.objectsize.i32.p0i8(i8* %call, i1 true)
 ; CHECK: ret i32 8
@@ -203,7 +203,7 @@ define i32 @test11(i8** %esc) {
 
 ; CHECK-LABEL: @test12(
 define i32 @test12(i8** %esc) {
-  %call = tail call i8* @strndup(i8* getelementptr inbounds ([8 x i8]* @.str, i64 0, i64 0), i32 8) nounwind
+  %call = tail call i8* @strndup(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i32 8) nounwind
   store i8* %call, i8** %esc, align 8
   %1 = tail call i32 @llvm.objectsize.i32.p0i8(i8* %call, i1 true)
 ; CHECK: ret i32 8
@@ -212,50 +212,13 @@ define i32 @test12(i8** %esc) {
 
 ; CHECK-LABEL: @test13(
 define i32 @test13(i8** %esc) {
-  %call = tail call i8* @strndup(i8* getelementptr inbounds ([8 x i8]* @.str, i64 0, i64 0), i32 57) nounwind
+  %call = tail call i8* @strndup(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i32 57) nounwind
   store i8* %call, i8** %esc, align 8
   %1 = tail call i32 @llvm.objectsize.i32.p0i8(i8* %call, i1 true)
 ; CHECK: ret i32 8
   ret i32 %1
 }
 
-; CHECK-LABEL: @PR13390(
-define i32 @PR13390(i1 %bool, i8* %a) {
-entry:
-  %cond = or i1 %bool, true
-  br i1 %cond, label %return, label %xpto
-
-xpto:
-  %select = select i1 %bool, i8* %select, i8* %a
-  %select2 = select i1 %bool, i8* %a, i8* %select2
-  %0 = tail call i32 @llvm.objectsize.i32.p0i8(i8* %select, i1 true)
-  %1 = tail call i32 @llvm.objectsize.i32.p0i8(i8* %select2, i1 true)
-  %2 = add i32 %0, %1
-; CHECK: ret i32 undef
-  ret i32 %2
-
-return:
-  ret i32 42
-}
-
-; CHECK-LABEL: @PR13621(
-define i32 @PR13621(i1 %bool) nounwind {
-entry:
-  %cond = or i1 %bool, true
-  br i1 %cond, label %return, label %xpto
-
-; technically reachable, but this malformed IR may appear as a result of constant propagation
-xpto:
-  %gep2 = getelementptr i8* %gep, i32 1
-  %gep = getelementptr i8* %gep2, i32 1
-  %o = call i32 @llvm.objectsize.i32.p0i8(i8* %gep, i1 true)
-; CHECK: ret i32 undef
-  ret i32 %o
-
-return:
-  ret i32 7
-}
-
 @globalalias = internal alias [60 x i8]* @a
 
 ; CHECK-LABEL: @test18(
diff --git a/test/Transforms/InstCombine/odr-linkage.ll b/test/Transforms/InstCombine/odr-linkage.ll
index 2ce62468dc77..73675efb08bb 100644
--- a/test/Transforms/InstCombine/odr-linkage.ll
+++ b/test/Transforms/InstCombine/odr-linkage.ll
@@ -6,10 +6,10 @@
 @g4 = internal constant i32 4
 
 define i32 @test() {
-  %A = load i32* @g1
-  %B = load i32* @g2
-  %C = load i32* @g3
-  %D = load i32* @g4
+  %A = load i32, i32* @g1
+  %B = load i32, i32* @g2
+  %C = load i32, i32* @g3
+  %D = load i32, i32* @g4
   
   %a = add i32 %A, %B
   %b = add i32 %a, %C
diff --git a/test/Transforms/InstCombine/or.ll b/test/Transforms/InstCombine/or.ll
index f604bafcc330..b91a5954d97e 100644
--- a/test/Transforms/InstCombine/or.ll
+++ b/test/Transforms/InstCombine/or.ll
@@ -394,7 +394,7 @@ define i32 @test37(i32* %xp, i32 %y) {
 ; CHECK: select i1 %tobool, i32 -1, i32 %x
   %tobool = icmp ne i32 %y, 0
   %sext = sext i1 %tobool to i32
-  %x = load i32* %xp
+  %x = load i32, i32* %xp
   %or = or i32 %sext, %x
   ret i32 %or
 }
@@ -404,7 +404,7 @@ define i32 @test38(i32* %xp, i32 %y) {
 ; CHECK: select i1 %tobool, i32 -1, i32 %x
   %tobool = icmp ne i32 %y, 0
   %sext = sext i1 %tobool to i32
-  %x = load i32* %xp
+  %x = load i32, i32* %xp
   %or = or i32 %x, %sext
   ret i32 %or
 }
diff --git a/test/Transforms/InstCombine/osx-names.ll b/test/Transforms/InstCombine/osx-names.ll
index 926caadc49d8..04d842d0ec28 100644
--- a/test/Transforms/InstCombine/osx-names.ll
+++ b/test/Transforms/InstCombine/osx-names.ll
@@ -16,14 +16,14 @@ target triple = "i386-apple-macosx10.7.2"
 define void @test1(%struct.__sFILE* %stream) nounwind {
 ; CHECK-LABEL: define void @test1(
 ; CHECK: call i32 @"fwrite$UNIX2003"
-  %call = tail call i32 (%struct.__sFILE*, i8*, ...)* @fprintf(%struct.__sFILE* %stream, i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0)) nounwind
+  %call = tail call i32 (%struct.__sFILE*, i8*, ...) @fprintf(%struct.__sFILE* %stream, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0)) nounwind
   ret void
 }
 
 define void @test2(%struct.__sFILE* %stream, i8* %str) nounwind ssp {
 ; CHECK-LABEL: define void @test2(
 ; CHECK: call i32 @"fputs$UNIX2003"
-  %call = tail call i32 (%struct.__sFILE*, i8*, ...)* @fprintf(%struct.__sFILE* %stream, i8* getelementptr inbounds ([3 x i8]* @.str2, i32 0, i32 0), i8* %str) nounwind
+  %call = tail call i32 (%struct.__sFILE*, i8*, ...) @fprintf(%struct.__sFILE* %stream, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str2, i32 0, i32 0), i8* %str) nounwind
   ret void
 }
 
diff --git a/test/Transforms/InstCombine/overflow-mul.ll b/test/Transforms/InstCombine/overflow-mul.ll
index 6d8d40bcac3e..bc0504b0a96d 100644
--- a/test/Transforms/InstCombine/overflow-mul.ll
+++ b/test/Transforms/InstCombine/overflow-mul.ll
@@ -174,6 +174,17 @@ define <4 x i32> @pr20113(<4 x i16> %a, <4 x i16> %b) {
   ret <4 x i32> %vcgez.i
 }
 
+
+; The last test needs this weird datalayout.
+target datalayout = "i32:8:8"
+; Without it, InstCombine will align the pointed on 4 Bytes
+; The KnownBitsZero that result from the alignment allows to
+; turn:
+;    and i32 %mul, 255
+; to:
+;    and i32 %mul, 252
+; The mask is no longer in the form 2^n-1  and this prevents the transformation.
+
 @pr21445_data = external global i32
 define i1 @pr21445(i8 %a) {
 ; CHECK-LABEL: @pr21445(
diff --git a/test/Transforms/InstCombine/overflow.ll b/test/Transforms/InstCombine/overflow.ll
index 3eddc80a7048..4c0a8a2c0df7 100644
--- a/test/Transforms/InstCombine/overflow.ll
+++ b/test/Transforms/InstCombine/overflow.ll
@@ -97,39 +97,6 @@ if.end:                                           ; preds = %entry
 ; CHECK: ret i8
 }
 
-; CHECK-LABEL: @test5(
-; CHECK: llvm.uadd.with.overflow
-; CHECK: ret i64
-define i64 @test5(i64 %a, i64 %b) nounwind ssp {
-entry:
-  %add = add i64 %b, %a
-  %cmp = icmp ult i64 %add, %a
-  %Q = select i1 %cmp, i64 %b, i64 42
-  ret i64 %Q
-}
-
-; CHECK-LABEL: @test6(
-; CHECK: llvm.uadd.with.overflow
-; CHECK: ret i64
-define i64 @test6(i64 %a, i64 %b) nounwind ssp {
-entry:
-  %add = add i64 %b, %a
-  %cmp = icmp ult i64 %add, %b
-  %Q = select i1 %cmp, i64 %b, i64 42
-  ret i64 %Q
-}
-
-; CHECK-LABEL: @test7(
-; CHECK: llvm.uadd.with.overflow
-; CHECK: ret i64
-define i64 @test7(i64 %a, i64 %b) nounwind ssp {
-entry:
-  %add = add i64 %b, %a
-  %cmp = icmp ugt i64 %b, %add
-  %Q = select i1 %cmp, i64 %b, i64 42
-  ret i64 %Q
-}
-
 ; CHECK-LABEL: @test8(
 ; PR11438
 ; This is @test1, but the operands are not sign-extended.  Make sure
diff --git a/test/Transforms/InstCombine/phi-merge-gep.ll b/test/Transforms/InstCombine/phi-merge-gep.ll
index 25c9cea9b770..b548e51a56a0 100644
--- a/test/Transforms/InstCombine/phi-merge-gep.ll
+++ b/test/Transforms/InstCombine/phi-merge-gep.ll
@@ -7,39 +7,39 @@
 
 define void @foo(float* %Ar, float* %Ai, i64 %As, float* %Cr, float* %Ci, i64 %Cs, i64 %n) nounwind {
 entry:
-  %0 = getelementptr inbounds float* %Ar, i64 0   ; <float*> [#uses=1]
-  %1 = getelementptr inbounds float* %Ai, i64 0   ; <float*> [#uses=1]
+  %0 = getelementptr inbounds float, float* %Ar, i64 0   ; <float*> [#uses=1]
+  %1 = getelementptr inbounds float, float* %Ai, i64 0   ; <float*> [#uses=1]
   %2 = mul i64 %n, %As                            ; <i64> [#uses=1]
-  %3 = getelementptr inbounds float* %Ar, i64 %2  ; <float*> [#uses=1]
+  %3 = getelementptr inbounds float, float* %Ar, i64 %2  ; <float*> [#uses=1]
   %4 = mul i64 %n, %As                            ; <i64> [#uses=1]
-  %5 = getelementptr inbounds float* %Ai, i64 %4  ; <float*> [#uses=1]
+  %5 = getelementptr inbounds float, float* %Ai, i64 %4  ; <float*> [#uses=1]
   %6 = mul i64 %n, 2                              ; <i64> [#uses=1]
   %7 = mul i64 %6, %As                            ; <i64> [#uses=1]
-  %8 = getelementptr inbounds float* %Ar, i64 %7  ; <float*> [#uses=1]
+  %8 = getelementptr inbounds float, float* %Ar, i64 %7  ; <float*> [#uses=1]
   %9 = mul i64 %n, 2                              ; <i64> [#uses=1]
   %10 = mul i64 %9, %As                           ; <i64> [#uses=1]
-  %11 = getelementptr inbounds float* %Ai, i64 %10 ; <float*> [#uses=1]
-  %12 = getelementptr inbounds float* %Cr, i64 0  ; <float*> [#uses=1]
-  %13 = getelementptr inbounds float* %Ci, i64 0  ; <float*> [#uses=1]
+  %11 = getelementptr inbounds float, float* %Ai, i64 %10 ; <float*> [#uses=1]
+  %12 = getelementptr inbounds float, float* %Cr, i64 0  ; <float*> [#uses=1]
+  %13 = getelementptr inbounds float, float* %Ci, i64 0  ; <float*> [#uses=1]
   %14 = mul i64 %n, %Cs                           ; <i64> [#uses=1]
-  %15 = getelementptr inbounds float* %Cr, i64 %14 ; <float*> [#uses=1]
+  %15 = getelementptr inbounds float, float* %Cr, i64 %14 ; <float*> [#uses=1]
   %16 = mul i64 %n, %Cs                           ; <i64> [#uses=1]
-  %17 = getelementptr inbounds float* %Ci, i64 %16 ; <float*> [#uses=1]
+  %17 = getelementptr inbounds float, float* %Ci, i64 %16 ; <float*> [#uses=1]
   %18 = mul i64 %n, 2                             ; <i64> [#uses=1]
   %19 = mul i64 %18, %Cs                          ; <i64> [#uses=1]
-  %20 = getelementptr inbounds float* %Cr, i64 %19 ; <float*> [#uses=1]
+  %20 = getelementptr inbounds float, float* %Cr, i64 %19 ; <float*> [#uses=1]
   %21 = mul i64 %n, 2                             ; <i64> [#uses=1]
   %22 = mul i64 %21, %Cs                          ; <i64> [#uses=1]
-  %23 = getelementptr inbounds float* %Ci, i64 %22 ; <float*> [#uses=1]
+  %23 = getelementptr inbounds float, float* %Ci, i64 %22 ; <float*> [#uses=1]
   br label %bb13
 
 bb:                                               ; preds = %bb13
-  %24 = load float* %A0r.0, align 4               ; <float> [#uses=1]
-  %25 = load float* %A0i.0, align 4               ; <float> [#uses=1]
-  %26 = load float* %A1r.0, align 4               ; <float> [#uses=2]
-  %27 = load float* %A1i.0, align 4               ; <float> [#uses=2]
-  %28 = load float* %A2r.0, align 4               ; <float> [#uses=2]
-  %29 = load float* %A2i.0, align 4               ; <float> [#uses=2]
+  %24 = load float, float* %A0r.0, align 4               ; <float> [#uses=1]
+  %25 = load float, float* %A0i.0, align 4               ; <float> [#uses=1]
+  %26 = load float, float* %A1r.0, align 4               ; <float> [#uses=2]
+  %27 = load float, float* %A1i.0, align 4               ; <float> [#uses=2]
+  %28 = load float, float* %A2r.0, align 4               ; <float> [#uses=2]
+  %29 = load float, float* %A2i.0, align 4               ; <float> [#uses=2]
   %30 = fadd float %26, %28                       ; <float> [#uses=2]
   %31 = fadd float %27, %29                       ; <float> [#uses=2]
   %32 = fsub float %26, %28                       ; <float> [#uses=1]
@@ -62,18 +62,18 @@ bb:                                               ; preds = %bb13
   store float %43, float* %C1i.0, align 4
   store float %44, float* %C2r.0, align 4
   store float %45, float* %C2i.0, align 4
-  %46 = getelementptr inbounds float* %A0r.0, i64 %As ; <float*> [#uses=1]
-  %47 = getelementptr inbounds float* %A0i.0, i64 %As ; <float*> [#uses=1]
-  %48 = getelementptr inbounds float* %A1r.0, i64 %As ; <float*> [#uses=1]
-  %49 = getelementptr inbounds float* %A1i.0, i64 %As ; <float*> [#uses=1]
-  %50 = getelementptr inbounds float* %A2r.0, i64 %As ; <float*> [#uses=1]
-  %51 = getelementptr inbounds float* %A2i.0, i64 %As ; <float*> [#uses=1]
-  %52 = getelementptr inbounds float* %C0r.0, i64 %Cs ; <float*> [#uses=1]
-  %53 = getelementptr inbounds float* %C0i.0, i64 %Cs ; <float*> [#uses=1]
-  %54 = getelementptr inbounds float* %C1r.0, i64 %Cs ; <float*> [#uses=1]
-  %55 = getelementptr inbounds float* %C1i.0, i64 %Cs ; <float*> [#uses=1]
-  %56 = getelementptr inbounds float* %C2r.0, i64 %Cs ; <float*> [#uses=1]
-  %57 = getelementptr inbounds float* %C2i.0, i64 %Cs ; <float*> [#uses=1]
+  %46 = getelementptr inbounds float, float* %A0r.0, i64 %As ; <float*> [#uses=1]
+  %47 = getelementptr inbounds float, float* %A0i.0, i64 %As ; <float*> [#uses=1]
+  %48 = getelementptr inbounds float, float* %A1r.0, i64 %As ; <float*> [#uses=1]
+  %49 = getelementptr inbounds float, float* %A1i.0, i64 %As ; <float*> [#uses=1]
+  %50 = getelementptr inbounds float, float* %A2r.0, i64 %As ; <float*> [#uses=1]
+  %51 = getelementptr inbounds float, float* %A2i.0, i64 %As ; <float*> [#uses=1]
+  %52 = getelementptr inbounds float, float* %C0r.0, i64 %Cs ; <float*> [#uses=1]
+  %53 = getelementptr inbounds float, float* %C0i.0, i64 %Cs ; <float*> [#uses=1]
+  %54 = getelementptr inbounds float, float* %C1r.0, i64 %Cs ; <float*> [#uses=1]
+  %55 = getelementptr inbounds float, float* %C1i.0, i64 %Cs ; <float*> [#uses=1]
+  %56 = getelementptr inbounds float, float* %C2r.0, i64 %Cs ; <float*> [#uses=1]
+  %57 = getelementptr inbounds float, float* %C2i.0, i64 %Cs ; <float*> [#uses=1]
   %58 = add nsw i64 %i.0, 1                       ; <i64> [#uses=1]
   br label %bb13
 
diff --git a/test/Transforms/InstCombine/phi.ll b/test/Transforms/InstCombine/phi.ll
index 6e314651383c..54cc4cfe4594 100644
--- a/test/Transforms/InstCombine/phi.ll
+++ b/test/Transforms/InstCombine/phi.ll
@@ -125,11 +125,11 @@ Exit:           ; preds = %Loop
 
 define i32* @test8({ i32, i32 } *%A, i1 %b) {
 BB0:
-        %X = getelementptr inbounds { i32, i32 } *%A, i32 0, i32 1
+        %X = getelementptr inbounds { i32, i32 }, { i32, i32 } *%A, i32 0, i32 1
         br i1 %b, label %BB1, label %BB2
 
 BB1:
-        %Y = getelementptr { i32, i32 } *%A, i32 0, i32 1
+        %Y = getelementptr { i32, i32 }, { i32, i32 } *%A, i32 0, i32 1
         br label %BB2
 
 BB2:
@@ -139,7 +139,7 @@ BB2:
 ; CHECK-LABEL: @test8(
 ; CHECK-NOT: phi
 ; CHECK: BB2:
-; CHECK-NEXT: %B = getelementptr { i32, i32 }* %A 
+; CHECK-NEXT: %B = getelementptr { i32, i32 }, { i32, i32 }* %A 
 ; CHECK-NEXT: ret i32* %B
 }
 
@@ -149,11 +149,11 @@ entry:
   br i1 %c, label %bb1, label %bb
 
 bb:
-  %C = load i32* %B, align 1
+  %C = load i32, i32* %B, align 1
   br label %bb2
 
 bb1:
-  %D = load i32* %A, align 1
+  %D = load i32, i32* %A, align 1
   br label %bb2
 
 bb2:
@@ -162,7 +162,7 @@ bb2:
 ; CHECK-LABEL: @test9(
 ; CHECK:       bb2:
 ; CHECK-NEXT:        phi i32* [ %B, %bb ], [ %A, %bb1 ]
-; CHECK-NEXT:   %E = load i32* %{{[^,]*}}, align 1
+; CHECK-NEXT:   %E = load i32, i32* %{{[^,]*}}, align 1
 ; CHECK-NEXT:   ret i32 %E
 
 }
@@ -173,11 +173,11 @@ entry:
   br i1 %c, label %bb1, label %bb
 
 bb:
-  %C = load i32* %B, align 16
+  %C = load i32, i32* %B, align 16
   br label %bb2
 
 bb1:
-  %D = load i32* %A, align 32
+  %D = load i32, i32* %A, align 32
   br label %bb2
 
 bb2:
@@ -186,7 +186,7 @@ bb2:
 ; CHECK-LABEL: @test10(
 ; CHECK:       bb2:
 ; CHECK-NEXT:        phi i32* [ %B, %bb ], [ %A, %bb1 ]
-; CHECK-NEXT:   %E = load i32* %{{[^,]*}}, align 16
+; CHECK-NEXT:   %E = load i32, i32* %{{[^,]*}}, align 16
 ; CHECK-NEXT:   ret i32 %E
 }
 
@@ -375,30 +375,30 @@ entry:
   store i32 %flag, i32* %flag.addr
   store i32* %pointer2, i32** %pointer2.addr
   store i32 10, i32* %res
-  %tmp = load i32* %flag.addr                     ; <i32> [#uses=1]
+  %tmp = load i32, i32* %flag.addr                     ; <i32> [#uses=1]
   %tobool = icmp ne i32 %tmp, 0                   ; <i1> [#uses=1]
   br i1 %tobool, label %if.then, label %if.else
 
 return:                                           ; preds = %if.end
-  %tmp7 = load i32* %retval                       ; <i32> [#uses=1]
+  %tmp7 = load i32, i32* %retval                       ; <i32> [#uses=1]
   ret i32 %tmp7
 
 if.end:                                           ; preds = %if.else, %if.then
-  %tmp6 = load i32* %res                          ; <i32> [#uses=1]
+  %tmp6 = load i32, i32* %res                          ; <i32> [#uses=1]
   store i32 %tmp6, i32* %retval
   br label %return
 
 if.then:                                          ; preds = %entry
-  %tmp1 = load i32 addrspace(1)** %pointer1.addr  ; <i32 addrspace(1)*>
-  %arrayidx = getelementptr i32 addrspace(1)* %tmp1, i32 0 ; <i32 addrspace(1)*> [#uses=1]
-  %tmp2 = load i32 addrspace(1)* %arrayidx        ; <i32> [#uses=1]
+  %tmp1 = load i32 addrspace(1)*, i32 addrspace(1)** %pointer1.addr  ; <i32 addrspace(1)*>
+  %arrayidx = getelementptr i32, i32 addrspace(1)* %tmp1, i32 0 ; <i32 addrspace(1)*> [#uses=1]
+  %tmp2 = load i32, i32 addrspace(1)* %arrayidx        ; <i32> [#uses=1]
   store i32 %tmp2, i32* %res
   br label %if.end
 
 if.else:                                          ; preds = %entry
-  %tmp3 = load i32** %pointer2.addr               ; <i32*> [#uses=1]
-  %arrayidx4 = getelementptr i32* %tmp3, i32 0    ; <i32*> [#uses=1]
-  %tmp5 = load i32* %arrayidx4                    ; <i32> [#uses=1]
+  %tmp3 = load i32*, i32** %pointer2.addr               ; <i32*> [#uses=1]
+  %arrayidx4 = getelementptr i32, i32* %tmp3, i32 0    ; <i32*> [#uses=1]
+  %tmp5 = load i32, i32* %arrayidx4                    ; <i32> [#uses=1]
   store i32 %tmp5, i32* %res
   br label %if.end
 }
diff --git a/test/Transforms/InstCombine/pr12251.ll b/test/Transforms/InstCombine/pr12251.ll
index 8c382bb104ac..7197bda2e542 100644
--- a/test/Transforms/InstCombine/pr12251.ll
+++ b/test/Transforms/InstCombine/pr12251.ll
@@ -2,13 +2,13 @@
 
 define zeroext i1 @_Z3fooPb(i8* nocapture %x) {
 entry:
-  %a = load i8* %x, align 1, !range !0
+  %a = load i8, i8* %x, align 1, !range !0
   %b = and i8 %a, 1
   %tobool = icmp ne i8 %b, 0
   ret i1 %tobool
 }
 
-; CHECK: %a = load i8* %x, align 1, !range !0
+; CHECK: %a = load i8, i8* %x, align 1, !range !0
 ; CHECK-NEXT: %tobool = icmp ne i8 %a, 0
 ; CHECK-NEXT: ret i1 %tobool
 
diff --git a/test/Transforms/InstCombine/pr21651.ll b/test/Transforms/InstCombine/pr21651.ll
index 914785f329af..d2b8d312d8c6 100644
--- a/test/Transforms/InstCombine/pr21651.ll
+++ b/test/Transforms/InstCombine/pr21651.ll
@@ -1,5 +1,9 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+
 define void @PR21651() {
   switch i2 0, label %out [
     i2 0, label %out
diff --git a/test/Transforms/InstCombine/pr2645-0.ll b/test/Transforms/InstCombine/pr2645-0.ll
index e8aeb2afb9cf..21bfa64a8604 100644
--- a/test/Transforms/InstCombine/pr2645-0.ll
+++ b/test/Transforms/InstCombine/pr2645-0.ll
@@ -6,10 +6,10 @@
 define internal void @""(i8*) {
 ; <label>:1
         bitcast i8* %0 to i32*          ; <i32*>:2 [#uses=1]
-        load i32* %2, align 1           ; <i32>:3 [#uses=1]
-        getelementptr i8* %0, i32 4             ; <i8*>:4 [#uses=1]
+        load i32, i32* %2, align 1           ; <i32>:3 [#uses=1]
+        getelementptr i8, i8* %0, i32 4             ; <i8*>:4 [#uses=1]
         bitcast i8* %4 to i32*          ; <i32*>:5 [#uses=1]
-        load i32* %5, align 1           ; <i32>:6 [#uses=1]
+        load i32, i32* %5, align 1           ; <i32>:6 [#uses=1]
         br label %7
 
 ; <label>:7             ; preds = %9, %1
@@ -22,7 +22,7 @@ define internal void @""(i8*) {
         sitofp i32 %.0 to float         ; <float>:10 [#uses=1]
         insertelement <4 x float> %.01, float %10, i32 0                ; <<4 x float>>:11 [#uses=1]
         shufflevector <4 x float> %11, <4 x float> undef, <4 x i32> zeroinitializer             ; <<4 x float>>:12 [#uses=2]
-        getelementptr i8* %0, i32 48            ; <i8*>:13 [#uses=1]
+        getelementptr i8, i8* %0, i32 48            ; <i8*>:13 [#uses=1]
         bitcast i8* %13 to <4 x float>*         ; <<4 x float>*>:14 [#uses=1]
         store <4 x float> %12, <4 x float>* %14, align 16
         add i32 %.0, 2          ; <i32>:15 [#uses=1]
diff --git a/test/Transforms/InstCombine/pr2645-1.ll b/test/Transforms/InstCombine/pr2645-1.ll
index d320dafcd252..2986d21866bf 100644
--- a/test/Transforms/InstCombine/pr2645-1.ll
+++ b/test/Transforms/InstCombine/pr2645-1.ll
@@ -13,9 +13,9 @@ define internal void @""(i8*, i32, i8*) {
         br i1 %5, label %6, label %20
 
 ; <label>:6             ; preds = %4
-        %7 = getelementptr i8* %2, i32 %.0              ; <i8*> [#uses=1]
+        %7 = getelementptr i8, i8* %2, i32 %.0              ; <i8*> [#uses=1]
         %8 = bitcast i8* %7 to <4 x i16>*               ; <<4 x i16>*> [#uses=1]
-        %9 = load <4 x i16>* %8, align 1                ; <<4 x i16>> [#uses=1]
+        %9 = load <4 x i16>, <4 x i16>* %8, align 1                ; <<4 x i16>> [#uses=1]
         %10 = bitcast <4 x i16> %9 to <1 x i64>         ; <<1 x i64>> [#uses=1]
         %11 = call <2 x i64> @foo(<1 x i64> %10)
 ; <<2 x i64>> [#uses=1]
@@ -24,7 +24,7 @@ define internal void @""(i8*, i32, i8*) {
         %14 = shufflevector <8 x i16> %13, <8 x i16> %13, <8 x i32> < i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3 >          ; <<8 x i16>> [#uses=1]
         %15 = bitcast <8 x i16> %14 to <4 x i32>                ; <<4 x i32>> [#uses=1]
         %16 = sitofp <4 x i32> %15 to <4 x float>               ; <<4 x float>> [#uses=1]
-        %17 = getelementptr i8* %0, i32 %.0             ; <i8*> [#uses=1]
+        %17 = getelementptr i8, i8* %0, i32 %.0             ; <i8*> [#uses=1]
         %18 = bitcast i8* %17 to <4 x float>*           ; <<4 x float>*> [#uses=1]
         store <4 x float> %16, <4 x float>* %18, align 1
         %19 = add i32 %.0, 1            ; <i32> [#uses=1]
diff --git a/test/Transforms/InstCombine/pr2996.ll b/test/Transforms/InstCombine/pr2996.ll
index ff3245d8668c..f5e1df4dd048 100644
--- a/test/Transforms/InstCombine/pr2996.ll
+++ b/test/Transforms/InstCombine/pr2996.ll
@@ -5,7 +5,7 @@ define void @func_53(i16 signext %p_56) nounwind {
 entry:
 	%0 = icmp sgt i16 %p_56, -1		; <i1> [#uses=1]
 	%iftmp.0.0 = select i1 %0, i32 -1, i32 0		; <i32> [#uses=1]
-	%1 = call i32 (...)* @func_4(i32 %iftmp.0.0) nounwind		; <i32> [#uses=0]
+	%1 = call i32 (...) @func_4(i32 %iftmp.0.0) nounwind		; <i32> [#uses=0]
 	ret void
 }
 
diff --git a/test/Transforms/InstCombine/pr8547.ll b/test/Transforms/InstCombine/pr8547.ll
index 7e9cbe17b68d..6d74b4002c11 100644
--- a/test/Transforms/InstCombine/pr8547.ll
+++ b/test/Transforms/InstCombine/pr8547.ll
@@ -21,6 +21,6 @@ for.cond:                                         ; preds = %for.cond, %codeRepl
   br i1 %tobool, label %for.cond, label %codeRepl2
 
 codeRepl2:                                        ; preds = %for.cond
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i64 0, i64 0), i32 %conv2) nounwind
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str, i64 0, i64 0), i32 %conv2) nounwind
   ret i32 0
 }
diff --git a/test/Transforms/InstCombine/printf-1.ll b/test/Transforms/InstCombine/printf-1.ll
index 483bc7a6b079..75e11ce7b7b4 100644
--- a/test/Transforms/InstCombine/printf-1.ll
+++ b/test/Transforms/InstCombine/printf-1.ll
@@ -21,8 +21,8 @@ declare i32 @printf(i8*, ...)
 
 define void @test_simplify1() {
 ; CHECK-LABEL: @test_simplify1(
-  %fmt = getelementptr [1 x i8]* @empty, i32 0, i32 0
-  call i32 (i8*, ...)* @printf(i8* %fmt)
+  %fmt = getelementptr [1 x i8], [1 x i8]* @empty, i32 0, i32 0
+  call i32 (i8*, ...) @printf(i8* %fmt)
   ret void
 ; CHECK-NEXT: ret void
 }
@@ -31,8 +31,8 @@ define void @test_simplify1() {
 
 define void @test_simplify2() {
 ; CHECK-LABEL: @test_simplify2(
-  %fmt = getelementptr [2 x i8]* @h, i32 0, i32 0
-  call i32 (i8*, ...)* @printf(i8* %fmt)
+  %fmt = getelementptr [2 x i8], [2 x i8]* @h, i32 0, i32 0
+  call i32 (i8*, ...) @printf(i8* %fmt)
 ; CHECK-NEXT: call i32 @putchar(i32 104)
   ret void
 ; CHECK-NEXT: ret void
@@ -40,8 +40,8 @@ define void @test_simplify2() {
 
 define void @test_simplify3() {
 ; CHECK-LABEL: @test_simplify3(
-  %fmt = getelementptr [2 x i8]* @percent, i32 0, i32 0
-  call i32 (i8*, ...)* @printf(i8* %fmt)
+  %fmt = getelementptr [2 x i8], [2 x i8]* @percent, i32 0, i32 0
+  call i32 (i8*, ...) @printf(i8* %fmt)
 ; CHECK-NEXT: call i32 @putchar(i32 37)
   ret void
 ; CHECK-NEXT: ret void
@@ -51,9 +51,9 @@ define void @test_simplify3() {
 
 define void @test_simplify4() {
 ; CHECK-LABEL: @test_simplify4(
-  %fmt = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
-  call i32 (i8*, ...)* @printf(i8* %fmt)
-; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([12 x i8]* [[STR]], i32 0, i32 0))
+  %fmt = getelementptr [13 x i8], [13 x i8]* @hello_world, i32 0, i32 0
+  call i32 (i8*, ...) @printf(i8* %fmt)
+; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([12 x i8], [12 x i8]* [[STR]], i32 0, i32 0))
   ret void
 ; CHECK-NEXT: ret void
 }
@@ -62,8 +62,8 @@ define void @test_simplify4() {
 
 define void @test_simplify5() {
 ; CHECK-LABEL: @test_simplify5(
-  %fmt = getelementptr [3 x i8]* @percent_c, i32 0, i32 0
-  call i32 (i8*, ...)* @printf(i8* %fmt, i8 104)
+  %fmt = getelementptr [3 x i8], [3 x i8]* @percent_c, i32 0, i32 0
+  call i32 (i8*, ...) @printf(i8* %fmt, i8 104)
 ; CHECK-NEXT: call i32 @putchar(i32 104)
   ret void
 ; CHECK-NEXT: ret void
@@ -73,10 +73,10 @@ define void @test_simplify5() {
 
 define void @test_simplify6() {
 ; CHECK-LABEL: @test_simplify6(
-  %fmt = getelementptr [4 x i8]* @percent_s, i32 0, i32 0
-  %str = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
-  call i32 (i8*, ...)* @printf(i8* %fmt, i8* %str)
-; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([13 x i8]* @hello_world, i32 0, i32 0))
+  %fmt = getelementptr [4 x i8], [4 x i8]* @percent_s, i32 0, i32 0
+  %str = getelementptr [13 x i8], [13 x i8]* @hello_world, i32 0, i32 0
+  call i32 (i8*, ...) @printf(i8* %fmt, i8* %str)
+; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @hello_world, i32 0, i32 0))
   ret void
 ; CHECK-NEXT: ret void
 }
@@ -85,35 +85,35 @@ define void @test_simplify6() {
 
 define void @test_simplify7() {
 ; CHECK-IPRINTF-LABEL: @test_simplify7(
-  %fmt = getelementptr [3 x i8]* @percent_d, i32 0, i32 0
-  call i32 (i8*, ...)* @printf(i8* %fmt, i32 187)
-; CHECK-IPRINTF-NEXT: call i32 (i8*, ...)* @iprintf(i8* getelementptr inbounds ([3 x i8]* @percent_d, i32 0, i32 0), i32 187)
+  %fmt = getelementptr [3 x i8], [3 x i8]* @percent_d, i32 0, i32 0
+  call i32 (i8*, ...) @printf(i8* %fmt, i32 187)
+; CHECK-IPRINTF-NEXT: call i32 (i8*, ...) @iprintf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @percent_d, i32 0, i32 0), i32 187)
   ret void
 ; CHECK-IPRINTF-NEXT: ret void
 }
 
 define void @test_no_simplify1() {
 ; CHECK-IPRINTF-LABEL: @test_no_simplify1(
-  %fmt = getelementptr [3 x i8]* @percent_f, i32 0, i32 0
-  call i32 (i8*, ...)* @printf(i8* %fmt, double 1.87)
-; CHECK-IPRINTF-NEXT: call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00)
+  %fmt = getelementptr [3 x i8], [3 x i8]* @percent_f, i32 0, i32 0
+  call i32 (i8*, ...) @printf(i8* %fmt, double 1.87)
+; CHECK-IPRINTF-NEXT: call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00)
   ret void
 ; CHECK-IPRINTF-NEXT: ret void
 }
 
 define void @test_no_simplify2(i8* %fmt, double %d) {
 ; CHECK-LABEL: @test_no_simplify2(
-  call i32 (i8*, ...)* @printf(i8* %fmt, double %d)
-; CHECK-NEXT: call i32 (i8*, ...)* @printf(i8* %fmt, double %d)
+  call i32 (i8*, ...) @printf(i8* %fmt, double %d)
+; CHECK-NEXT: call i32 (i8*, ...) @printf(i8* %fmt, double %d)
   ret void
 ; CHECK-NEXT: ret void
 }
 
 define i32 @test_no_simplify3() {
 ; CHECK-LABEL: @test_no_simplify3(
-  %fmt = getelementptr [2 x i8]* @h, i32 0, i32 0
-  %ret = call i32 (i8*, ...)* @printf(i8* %fmt)
-; CHECK-NEXT: call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([2 x i8]* @h, i32 0, i32 0))
+  %fmt = getelementptr [2 x i8], [2 x i8]* @h, i32 0, i32 0
+  %ret = call i32 (i8*, ...) @printf(i8* %fmt)
+; CHECK-NEXT: call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @h, i32 0, i32 0))
   ret i32 %ret
 ; CHECK-NEXT: ret i32 %ret
 }
diff --git a/test/Transforms/InstCombine/printf-2.ll b/test/Transforms/InstCombine/printf-2.ll
index 7e018ebba04d..d6769856e3d8 100644
--- a/test/Transforms/InstCombine/printf-2.ll
+++ b/test/Transforms/InstCombine/printf-2.ll
@@ -14,8 +14,8 @@ declare void @printf(i8*, ...)
 
 define void @test_simplify1() {
 ; CHECK-LABEL: @test_simplify1(
-  %fmt = getelementptr [2 x i8]* @h, i32 0, i32 0
-  call void (i8*, ...)* @printf(i8* %fmt)
+  %fmt = getelementptr [2 x i8], [2 x i8]* @h, i32 0, i32 0
+  call void (i8*, ...) @printf(i8* %fmt)
 ; CHECK-NEXT: call i32 @putchar(i32 104)
   ret void
 ; CHECK-NEXT: ret void
@@ -23,19 +23,19 @@ define void @test_simplify1() {
 
 define void @test_simplify2() {
 ; CHECK-LABEL: @test_simplify2(
-  %fmt = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
-  call void (i8*, ...)* @printf(i8* %fmt)
-; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([12 x i8]* @str, i32 0, i32 0))
+  %fmt = getelementptr [13 x i8], [13 x i8]* @hello_world, i32 0, i32 0
+  call void (i8*, ...) @printf(i8* %fmt)
+; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @str, i32 0, i32 0))
   ret void
 ; CHECK-NEXT: ret void
 }
 
 define void @test_simplify6() {
 ; CHECK-LABEL: @test_simplify6(
-  %fmt = getelementptr [4 x i8]* @percent_s, i32 0, i32 0
-  %str = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
-  call void (i8*, ...)* @printf(i8* %fmt, i8* %str)
-; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([13 x i8]* @hello_world, i32 0, i32 0))
+  %fmt = getelementptr [4 x i8], [4 x i8]* @percent_s, i32 0, i32 0
+  %str = getelementptr [13 x i8], [13 x i8]* @hello_world, i32 0, i32 0
+  call void (i8*, ...) @printf(i8* %fmt, i8* %str)
+; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @hello_world, i32 0, i32 0))
   ret void
 ; CHECK-NEXT: ret void
 }
diff --git a/test/Transforms/InstCombine/puts-1.ll b/test/Transforms/InstCombine/puts-1.ll
index bd7557ef650f..21028684851d 100644
--- a/test/Transforms/InstCombine/puts-1.ll
+++ b/test/Transforms/InstCombine/puts-1.ll
@@ -12,7 +12,7 @@ declare i32 @puts(i8*)
 
 define void @test_simplify1() {
 ; CHECK-LABEL: @test_simplify1(
-  %str = getelementptr [1 x i8]* @empty, i32 0, i32 0
+  %str = getelementptr [1 x i8], [1 x i8]* @empty, i32 0, i32 0
   call i32 @puts(i8* %str)
 ; CHECK-NEXT: call i32 @putchar(i32 10)
   ret void
@@ -23,9 +23,9 @@ define void @test_simplify1() {
 
 define i32 @test_no_simplify1() {
 ; CHECK-LABEL: @test_no_simplify1(
-  %str = getelementptr [1 x i8]* @empty, i32 0, i32 0
+  %str = getelementptr [1 x i8], [1 x i8]* @empty, i32 0, i32 0
   %ret = call i32 @puts(i8* %str)
-; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([1 x i8]* @empty, i32 0, i32 0))
+; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @empty, i32 0, i32 0))
   ret i32 %ret
 ; CHECK-NEXT: ret i32 %ret
 }
diff --git a/test/Transforms/InstCombine/select-cmp-br.ll b/test/Transforms/InstCombine/select-cmp-br.ll
index f10d58783a77..1dc7e153f5fb 100644
--- a/test/Transforms/InstCombine/select-cmp-br.ll
+++ b/test/Transforms/InstCombine/select-cmp-br.ll
@@ -9,13 +9,13 @@ declare void @foobar()
 
 define void @test1(%C*) {
 entry:
-  %1 = getelementptr inbounds %C* %0, i64 0, i32 0, i32 0
-  %m = load i64** %1, align 8
-  %2 = getelementptr inbounds %C* %0, i64 1, i32 0, i32 0
-  %n = load i64** %2, align 8
-  %3 = getelementptr inbounds i64* %m, i64 9
+  %1 = getelementptr inbounds %C, %C* %0, i64 0, i32 0, i32 0
+  %m = load i64*, i64** %1, align 8
+  %2 = getelementptr inbounds %C, %C* %0, i64 1, i32 0, i32 0
+  %n = load i64*, i64** %2, align 8
+  %3 = getelementptr inbounds i64, i64* %m, i64 9
   %4 = bitcast i64* %3 to i64 (%C*)**
-  %5 = load i64 (%C*)** %4, align 8
+  %5 = load i64 (%C*)*, i64 (%C*)** %4, align 8
   %6 = icmp eq i64* %m, %n
   %7 = select i1 %6, %C* %0, %C* null
   %8 = icmp eq %C* %7, null
@@ -25,7 +25,7 @@ entry:
   ret void
 
 ; <label>:10                                      ; preds = %entry
-  %11 = getelementptr inbounds %C* %7, i64 0, i32 0
+  %11 = getelementptr inbounds %C, %C* %7, i64 0, i32 0
   tail call void @bar(%struct.S* %11)
   br label %9
 
@@ -40,13 +40,13 @@ entry:
 
 define void @test2(%C*) {
 entry:
-  %1 = getelementptr inbounds %C* %0, i64 0, i32 0, i32 0
-  %m = load i64** %1, align 8
-  %2 = getelementptr inbounds %C* %0, i64 1, i32 0, i32 0
-  %n = load i64** %2, align 8
-  %3 = getelementptr inbounds i64* %m, i64 9
+  %1 = getelementptr inbounds %C, %C* %0, i64 0, i32 0, i32 0
+  %m = load i64*, i64** %1, align 8
+  %2 = getelementptr inbounds %C, %C* %0, i64 1, i32 0, i32 0
+  %n = load i64*, i64** %2, align 8
+  %3 = getelementptr inbounds i64, i64* %m, i64 9
   %4 = bitcast i64* %3 to i64 (%C*)**
-  %5 = load i64 (%C*)** %4, align 8
+  %5 = load i64 (%C*)*, i64 (%C*)** %4, align 8
   %6 = icmp eq i64* %m, %n
   %7 = select i1 %6, %C* null, %C* %0
   %8 = icmp eq %C* %7, null
@@ -56,7 +56,7 @@ entry:
   ret void
 
 ; <label>:10                                      ; preds = %entry
-  %11 = getelementptr inbounds %C* %7, i64 0, i32 0
+  %11 = getelementptr inbounds %C, %C* %7, i64 0, i32 0
   tail call void @bar(%struct.S* %11)
   br label %9
 
@@ -71,13 +71,13 @@ entry:
 
 define void @test3(%C*) {
 entry:
-  %1 = getelementptr inbounds %C* %0, i64 0, i32 0, i32 0
-  %m = load i64** %1, align 8
-  %2 = getelementptr inbounds %C* %0, i64 1, i32 0, i32 0
-  %n = load i64** %2, align 8
-  %3 = getelementptr inbounds i64* %m, i64 9
+  %1 = getelementptr inbounds %C, %C* %0, i64 0, i32 0, i32 0
+  %m = load i64*, i64** %1, align 8
+  %2 = getelementptr inbounds %C, %C* %0, i64 1, i32 0, i32 0
+  %n = load i64*, i64** %2, align 8
+  %3 = getelementptr inbounds i64, i64* %m, i64 9
   %4 = bitcast i64* %3 to i64 (%C*)**
-  %5 = load i64 (%C*)** %4, align 8
+  %5 = load i64 (%C*)*, i64 (%C*)** %4, align 8
   %6 = icmp eq i64* %m, %n
   %7 = select i1 %6, %C* %0, %C* null
   %8 = icmp ne %C* %7, null
@@ -87,7 +87,7 @@ entry:
   ret void
 
 ; <label>:10                                      ; preds = %entry
-  %11 = getelementptr inbounds %C* %7, i64 0, i32 0
+  %11 = getelementptr inbounds %C, %C* %7, i64 0, i32 0
   tail call void @bar(%struct.S* %11)
   br label %9
 
@@ -102,13 +102,13 @@ entry:
 
 define void @test4(%C*) {
 entry:
-  %1 = getelementptr inbounds %C* %0, i64 0, i32 0, i32 0
-  %m = load i64** %1, align 8
-  %2 = getelementptr inbounds %C* %0, i64 1, i32 0, i32 0
-  %n = load i64** %2, align 8
-  %3 = getelementptr inbounds i64* %m, i64 9
+  %1 = getelementptr inbounds %C, %C* %0, i64 0, i32 0, i32 0
+  %m = load i64*, i64** %1, align 8
+  %2 = getelementptr inbounds %C, %C* %0, i64 1, i32 0, i32 0
+  %n = load i64*, i64** %2, align 8
+  %3 = getelementptr inbounds i64, i64* %m, i64 9
   %4 = bitcast i64* %3 to i64 (%C*)**
-  %5 = load i64 (%C*)** %4, align 8
+  %5 = load i64 (%C*)*, i64 (%C*)** %4, align 8
   %6 = icmp eq i64* %m, %n
   %7 = select i1 %6, %C* null, %C* %0
   %8 = icmp ne %C* %7, null
@@ -118,7 +118,7 @@ entry:
   ret void
 
 ; <label>:10                                      ; preds = %entry
-  %11 = getelementptr inbounds %C* %7, i64 0, i32 0
+  %11 = getelementptr inbounds %C, %C* %7, i64 0, i32 0
   tail call void @bar(%struct.S* %11)
   br label %9
 
@@ -141,7 +141,7 @@ entry:
   ret void
 
 ; <label>:5                                      ; preds = %entry
-  %6 = getelementptr inbounds %C* %2, i64 0, i32 0
+  %6 = getelementptr inbounds %C, %C* %2, i64 0, i32 0
   tail call void @bar(%struct.S* %6)
   br label %4
 
diff --git a/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll b/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll
new file mode 100644
index 000000000000..894bf6db0a42
--- /dev/null
+++ b/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll
@@ -0,0 +1,327 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+; This test is to verify that the instruction combiner is able to fold
+; a cttz/ctlz followed by a icmp + select into a single cttz/ctlz with
+; the 'is_zero_undef' flag cleared.
+
+define i16 @test1(i16 %x) {
+; CHECK-LABEL: @test1(
+; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false)
+; CHECK-NEXT: ret i16 [[VAR]]
+entry:
+  %0 = tail call i16 @llvm.ctlz.i16(i16 %x, i1 true)
+  %tobool = icmp ne i16 %x, 0
+  %cond = select i1 %tobool, i16 %0, i16 16
+  ret i16 %cond
+}
+
+define i32 @test2(i32 %x) {
+; CHECK-LABEL: @test2(
+; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false)
+; CHECK-NEXT: ret i32 [[VAR]]
+entry:
+  %0 = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+  %tobool = icmp ne i32 %x, 0
+  %cond = select i1 %tobool, i32 %0, i32 32
+  ret i32 %cond
+}
+
+define i64 @test3(i64 %x) {
+; CHECK-LABEL: @test3(
+; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false)
+; CHECK-NEXT: ret i64 [[VAR]]
+entry:
+  %0 = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
+  %tobool = icmp ne i64 %x, 0
+  %cond = select i1 %tobool, i64 %0, i64 64
+  ret i64 %cond
+}
+
+define i16 @test4(i16 %x) {
+; CHECK-LABEL: @test4(
+; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false)
+; CHECK-NEXT: ret i16 [[VAR]]
+entry:
+  %0 = tail call i16 @llvm.ctlz.i16(i16 %x, i1 true)
+  %tobool = icmp eq i16 %x, 0
+  %cond = select i1 %tobool, i16 16, i16 %0
+  ret i16 %cond
+}
+
+define i32 @test5(i32 %x) {
+; CHECK-LABEL: @test5(
+; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false)
+; CHECK-NEXT: ret i32 [[VAR]]
+entry:
+  %0 = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+  %tobool = icmp eq i32 %x, 0
+  %cond = select i1 %tobool, i32 32, i32 %0
+  ret i32 %cond
+}
+
+define i64 @test6(i64 %x) {
+; CHECK-LABEL: @test6(
+; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false)
+; CHECK-NEXT: ret i64 [[VAR]]
+entry:
+  %0 = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
+  %tobool = icmp eq i64 %x, 0
+  %cond = select i1 %tobool, i64 64, i64 %0
+  ret i64 %cond
+}
+
+define i16 @test1b(i16 %x) {
+; CHECK-LABEL: @test1b(
+; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %x, i1 false)
+; CHECK-NEXT: ret i16 [[VAR]]
+entry:
+  %0 = tail call i16 @llvm.cttz.i16(i16 %x, i1 true)
+  %tobool = icmp ne i16 %x, 0
+  %cond = select i1 %tobool, i16 %0, i16 16
+  ret i16 %cond
+}
+
+define i32 @test2b(i32 %x) {
+; CHECK-LABEL: @test2b(
+; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
+; CHECK-NEXT: ret i32 [[VAR]]
+entry:
+  %0 = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
+  %tobool = icmp ne i32 %x, 0
+  %cond = select i1 %tobool, i32 %0, i32 32
+  ret i32 %cond
+}
+
+define i64 @test3b(i64 %x) {
+; CHECK-LABEL: @test3b(
+; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 false)
+; CHECK-NEXT: ret i64 [[VAR]]
+entry:
+  %0 = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
+  %tobool = icmp ne i64 %x, 0
+  %cond = select i1 %tobool, i64 %0, i64 64
+  ret i64 %cond
+}
+
+define i16 @test4b(i16 %x) {
+; CHECK-LABEL: @test4b(
+; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %x, i1 false)
+; CHECK-NEXT: ret i16 [[VAR]]
+entry:
+  %0 = tail call i16 @llvm.cttz.i16(i16 %x, i1 true)
+  %tobool = icmp eq i16 %x, 0
+  %cond = select i1 %tobool, i16 16, i16 %0
+  ret i16 %cond
+}
+
+define i32 @test5b(i32 %x) {
+; CHECK-LABEL: @test5b(
+; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
+; CHECK-NEXT: ret i32 [[VAR]]
+entry:
+  %0 = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
+  %tobool = icmp eq i32 %x, 0
+  %cond = select i1 %tobool, i32 32, i32 %0
+  ret i32 %cond
+}
+
+define i64 @test6b(i64 %x) {
+; CHECK-LABEL: @test6b(
+; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 false)
+; CHECK-NEXT: ret i64 [[VAR]]
+entry:
+  %0 = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
+  %tobool = icmp eq i64 %x, 0
+  %cond = select i1 %tobool, i64 64, i64 %0
+  ret i64 %cond
+}
+
+define i32 @test1c(i16 %x) {
+; CHECK-LABEL: @test1c(
+; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %x, i1 false)
+; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i16 [[VAR1]] to i32
+; CHECK-NEXT: ret i32 [[VAR2]]
+entry:
+  %0 = tail call i16 @llvm.cttz.i16(i16 %x, i1 true)
+  %cast2 = zext i16 %0 to i32
+  %tobool = icmp ne i16 %x, 0
+  %cond = select i1 %tobool, i32 %cast2, i32 16
+  ret i32 %cond
+}
+
+define i64 @test2c(i16 %x) {
+; CHECK-LABEL: @test2c(
+; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %x, i1 false)
+; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i16 [[VAR1]] to i64
+; CHECK-NEXT: ret i64 [[VAR2]]
+entry:
+  %0 = tail call i16 @llvm.cttz.i16(i16 %x, i1 true)
+  %conv = zext i16 %0 to i64
+  %tobool = icmp ne i16 %x, 0
+  %cond = select i1 %tobool, i64 %conv, i64 16
+  ret i64 %cond
+}
+
+define i64 @test3c(i32 %x) {
+; CHECK-LABEL: @test3c(
+; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
+; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i32 [[VAR1]] to i64
+; CHECK-NEXT: ret i64 [[VAR2]]
+entry:
+  %0 = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
+  %conv = zext i32 %0 to i64
+  %tobool = icmp ne i32 %x, 0
+  %cond = select i1 %tobool, i64 %conv, i64 32
+  ret i64 %cond
+}
+
+define i32 @test4c(i16 %x) {
+; CHECK-LABEL: @test4c(
+; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false)
+; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i16 [[VAR1]] to i32
+; CHECK-NEXT: ret i32 [[VAR2]]
+entry:
+  %0 = tail call i16 @llvm.ctlz.i16(i16 %x, i1 true)
+  %cast = zext i16 %0 to i32
+  %tobool = icmp ne i16 %x, 0
+  %cond = select i1 %tobool, i32 %cast, i32 16
+  ret i32 %cond
+}
+
+define i64 @test5c(i16 %x) {
+; CHECK-LABEL: @test5c(
+; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false)
+; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i16 [[VAR1]] to i64
+; CHECK-NEXT: ret i64 [[VAR2]]
+entry:
+  %0 = tail call i16 @llvm.ctlz.i16(i16 %x, i1 true)
+  %cast = zext i16 %0 to i64
+  %tobool = icmp ne i16 %x, 0
+  %cond = select i1 %tobool, i64 %cast, i64 16
+  ret i64 %cond
+}
+
+define i64 @test6c(i32 %x) {
+; CHECK-LABEL: @test6c(
+; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false)
+; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i32 [[VAR1]] to i64
+; CHECK-NEXT: ret i64 [[VAR2]]
+entry:
+  %0 = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+  %cast = zext i32 %0 to i64
+  %tobool = icmp ne i32 %x, 0
+  %cond = select i1 %tobool, i64 %cast, i64 32
+  ret i64 %cond
+}
+
+define i16 @test1d(i64 %x) {
+; CHECK-LABEL: @test1d(
+; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 false)
+; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = trunc i64 [[VAR1]] to i16
+; CHECK-NEXT: ret i16 [[VAR2]]
+entry:
+  %0 = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
+  %conv = trunc i64 %0 to i16
+  %tobool = icmp ne i64 %x, 0
+  %cond = select i1 %tobool, i16 %conv, i16 64
+  ret i16 %cond
+}
+
+define i32 @test2d(i64 %x) {
+; CHECK-LABEL: @test2d(
+; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 false)
+; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = trunc i64 [[VAR1]] to i32
+; CHECK-NEXT: ret i32 [[VAR2]]
+entry:
+  %0 = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
+  %cast = trunc i64 %0 to i32
+  %tobool = icmp ne i64 %x, 0
+  %cond = select i1 %tobool, i32 %cast, i32 64
+  ret i32 %cond
+}
+
+define i16 @test3d(i32 %x) {
+; CHECK-LABEL: @test3d(
+; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
+; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = trunc i32 [[VAR1]] to i16
+; CHECK-NEXT: ret i16 [[VAR2]]
+entry:
+  %0 = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
+  %cast = trunc i32 %0 to i16
+  %tobool = icmp ne i32 %x, 0
+  %cond = select i1 %tobool, i16 %cast, i16 32
+  ret i16 %cond
+}
+
+define i16 @test4d(i64 %x) {
+; CHECK-LABEL: @test4d(
+; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false)
+; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = trunc i64 [[VAR1]] to i16
+; CHECK-NEXT: ret i16 [[VAR2]]
+entry:
+  %0 = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
+  %cast = trunc i64 %0 to i16
+  %tobool = icmp ne i64 %x, 0
+  %cond = select i1 %tobool, i16 %cast, i16 64
+  ret i16 %cond
+}
+
+define i32 @test5d(i64 %x) {
+; CHECK-LABEL: @test5d(
+; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false)
+; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = trunc i64 [[VAR1]] to i32
+; CHECK-NEXT: ret i32 [[VAR2]]
+entry:
+  %0 = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
+  %cast = trunc i64 %0 to i32
+  %tobool = icmp ne i64 %x, 0
+  %cond = select i1 %tobool, i32 %cast, i32 64
+  ret i32 %cond
+}
+
+define i16 @test6d(i32 %x) {
+; CHECK-LABEL: @test6d(
+; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false)
+; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = trunc i32 [[VAR1]] to i16
+; CHECK-NEXT: ret i16 [[VAR2]]
+entry:
+  %0 = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+  %cast = trunc i32 %0 to i16
+  %tobool = icmp ne i32 %x, 0
+  %cond = select i1 %tobool, i16 %cast, i16 32
+  ret i16 %cond
+}
+
+define i64 @select_bug1(i32 %x) {
+; CHECK-LABEL: @select_bug1(
+; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
+; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i32 [[VAR1]] to i64
+; CHECK-NEXT: ret i64 [[VAR2]]
+entry:
+  %0 = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
+  %conv = zext i32 %0 to i64
+  %tobool = icmp ne i32 %x, 0
+  %cond = select i1 %tobool, i64 %conv, i64 32
+  ret i64 %cond
+}
+
+define i16 @select_bug2(i32 %x) {
+; CHECK-LABEL: @select_bug2(
+; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
+; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = trunc i32 [[VAR1]] to i16
+; CHECK-NEXT: ret i16 [[VAR2]]
+entry:
+  %0 = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
+  %conv = trunc i32 %0 to i16
+  %tobool = icmp ne i32 %x, 0
+  %cond = select i1 %tobool, i16 %conv, i16 32
+  ret i16 %cond
+}
+
+
+declare i16 @llvm.ctlz.i16(i16, i1)
+declare i32 @llvm.ctlz.i32(i32, i1)
+declare i64 @llvm.ctlz.i64(i64, i1)
+declare i16 @llvm.cttz.i16(i16, i1)
+declare i32 @llvm.cttz.i32(i32, i1)
+declare i64 @llvm.cttz.i64(i64, i1)
diff --git a/test/Transforms/InstCombine/select-crash-noverify.ll b/test/Transforms/InstCombine/select-crash-noverify.ll
new file mode 100644
index 000000000000..4a366aa8fb83
--- /dev/null
+++ b/test/Transforms/InstCombine/select-crash-noverify.ll
@@ -0,0 +1,19 @@
+; RUN: opt < %s -disable-verify -instcombine -S | opt -S | FileCheck %s
+; Formerly crashed, PR8490.
+
+; CHECK-LABEL: @test3(
+define i32 @test3(i1 %bool, i32 %a) {
+entry:
+  %cond = or i1 %bool, true
+  br i1 %cond, label %return, label %xpto
+
+; technically reachable, but this malformed IR may appear as a result of constant propagation
+xpto:
+  %select = select i1 %bool, i32 %a, i32 %select
+  %select2 = select i1 %bool, i32 %select2, i32 %a
+  %sum = add i32 %select, %select2
+  ret i32 %sum
+
+return:
+  ret i32 7
+}
diff --git a/test/Transforms/InstCombine/select-crash.ll b/test/Transforms/InstCombine/select-crash.ll
index 77446cd8ba02..991635b63aa8 100644
--- a/test/Transforms/InstCombine/select-crash.ll
+++ b/test/Transforms/InstCombine/select-crash.ll
@@ -30,20 +30,3 @@ define <4 x float> @foo(i1 %b, <4 x float> %x, <4 x float> %y, <4 x float> %z) {
   %sel = select i1 %b, <4 x float> %a, <4 x float> %sub 
   ret <4 x float> %sel
 }
-
-; CHECK-LABEL: @test3(
-define i32 @test3(i1 %bool, i32 %a) {
-entry:
-  %cond = or i1 %bool, true
-  br i1 %cond, label %return, label %xpto
-
-; technically reachable, but this malformed IR may appear as a result of constant propagation
-xpto:
-  %select = select i1 %bool, i32 %a, i32 %select
-  %select2 = select i1 %bool, i32 %select2, i32 %a
-  %sum = add i32 %select, %select2
-  ret i32 %sum
-
-return:
-  ret i32 7
-}
diff --git a/test/Transforms/InstCombine/select-load-call.ll b/test/Transforms/InstCombine/select-load-call.ll
index b63468de53e1..ad0ef4f85eb2 100644
--- a/test/Transforms/InstCombine/select-load-call.ll
+++ b/test/Transforms/InstCombine/select-load-call.ll
@@ -10,6 +10,6 @@ define i32 @test(i1 %cond, i32 *%P) {
   call void @test2() readonly
 
   %P2 = select i1 %cond, i32 *%P, i32* %A
-  %V = load i32* %P2
+  %V = load i32, i32* %P2
   ret i32 %V
 }
diff --git a/test/Transforms/InstCombine/select-select.ll b/test/Transforms/InstCombine/select-select.ll
index 65820acf07b8..768d1c47c209 100644
--- a/test/Transforms/InstCombine/select-select.ll
+++ b/test/Transforms/InstCombine/select-select.ll
@@ -21,4 +21,14 @@ define float @foo2(float %a) #0 {
   ret float %f
 }
 
+; CHECK-LABEL: @foo3
+define <2 x i32> @foo3(<2 x i1> %vec_bool, i1 %bool, <2 x i32> %V) {
+; CHECK: %[[sel0:.*]] = select <2 x i1> %vec_bool, <2 x i32> zeroinitializer, <2 x i32> %V
+; CHECK: %[[sel1:.*]] = select i1 %bool, <2 x i32> %[[sel0]], <2 x i32> %V
+; CHECK: ret <2 x i32> %[[sel1]]
+  %sel0 = select <2 x i1> %vec_bool, <2 x i32> zeroinitializer, <2 x i32> %V
+  %sel1 = select i1 %bool, <2 x i32> %sel0, <2 x i32> %V
+  ret <2 x i32> %sel1
+}
+
 attributes #0 = { nounwind readnone ssp uwtable }
diff --git a/test/Transforms/InstCombine/select.ll b/test/Transforms/InstCombine/select.ll
index 054f00a0de49..e4bc96cff176 100644
--- a/test/Transforms/InstCombine/select.ll
+++ b/test/Transforms/InstCombine/select.ll
@@ -301,30 +301,30 @@ define i32 @test15j(i32 %X) {
 
 define i32 @test16(i1 %C, i32* %P) {
         %P2 = select i1 %C, i32* %P, i32* null          
-        %V = load i32* %P2              
+        %V = load i32, i32* %P2              
         ret i32 %V
 ; CHECK-LABEL: @test16(
-; CHECK-NEXT: %V = load i32* %P
+; CHECK-NEXT: %V = load i32, i32* %P
 ; CHECK: ret i32 %V
 }
 
 ;; It may be legal to load from a null address in a non-zero address space
 define i32 @test16_neg(i1 %C, i32 addrspace(1)* %P) {
         %P2 = select i1 %C, i32 addrspace(1)* %P, i32 addrspace(1)* null
-        %V = load i32 addrspace(1)* %P2
+        %V = load i32, i32 addrspace(1)* %P2
         ret i32 %V
 ; CHECK-LABEL: @test16_neg
 ; CHECK-NEXT: %P2 = select i1 %C, i32 addrspace(1)* %P, i32 addrspace(1)* null
-; CHECK-NEXT: %V = load i32 addrspace(1)* %P2
+; CHECK-NEXT: %V = load i32, i32 addrspace(1)* %P2
 ; CHECK: ret i32 %V
 }
 define i32 @test16_neg2(i1 %C, i32 addrspace(1)* %P) {
         %P2 = select i1 %C, i32 addrspace(1)* null, i32 addrspace(1)* %P
-        %V = load i32 addrspace(1)* %P2
+        %V = load i32, i32 addrspace(1)* %P2
         ret i32 %V
 ; CHECK-LABEL: @test16_neg2
 ; CHECK-NEXT: %P2 = select i1 %C, i32 addrspace(1)* null, i32 addrspace(1)* %P
-; CHECK-NEXT: %V = load i32 addrspace(1)* %P2
+; CHECK-NEXT: %V = load i32, i32 addrspace(1)* %P2
 ; CHECK: ret i32 %V
 }
 
@@ -423,11 +423,11 @@ jump:
   %c = or i1 false, false
   br label %ret 
 ret:
-  %a = phi i1 [true, %jump], [%c, %entry]
-  %b = select i1 %a, i32 10, i32 20
+  %a = phi i1 [true, %entry], [%c, %jump]
+  %b = select i1 %a, i32 20, i32 10
   ret i32 %b
 ; CHECK-LABEL: @test26(
-; CHECK: %a = phi i32 [ 10, %jump ], [ 20, %entry ]
+; CHECK: %a = phi i32 [ 20, %entry ], [ 10, %jump ]
 ; CHECK-NEXT: ret i32 %a
 }
 
@@ -813,7 +813,7 @@ define i32 @test59(i32 %x, i32 %y) nounwind {
 
 define i1 @test60(i32 %x, i1* %y) nounwind {
   %cmp = icmp eq i32 %x, 0
-  %load = load i1* %y, align 1
+  %load = load i1, i1* %y, align 1
   %cmp1 = icmp slt i32 %x, 1
   %sel = select i1 %cmp, i1 %load, i1 %cmp1
   ret i1 %sel
@@ -823,7 +823,7 @@ define i1 @test60(i32 %x, i1* %y) nounwind {
 
 @glbl = constant i32 10
 define i32 @test61(i32* %ptr) {
-  %A = load i32* %ptr
+  %A = load i32, i32* %ptr
   %B = icmp eq i32* %ptr, @glbl
   %C = select i1 %B, i32 %A, i32 10
   ret i32 %C
@@ -1249,11 +1249,11 @@ define i32 @test76(i1 %flag, i32* %x) {
 ; CHECK-LABEL: @test76(
 ; CHECK: store i32 0, i32* %x
 ; CHECK: %[[P:.*]] = select i1 %flag, i32* @under_aligned, i32* %x
-; CHECK: load i32* %[[P]]
+; CHECK: load i32, i32* %[[P]]
 
   store i32 0, i32* %x
   %p = select i1 %flag, i32* @under_aligned, i32* %x
-  %v = load i32* %p
+  %v = load i32, i32* %p
   ret i32 %v
 }
 
@@ -1268,13 +1268,13 @@ define i32 @test77(i1 %flag, i32* %x) {
 ; CHECK: call void @scribble_on_i32(i32* %[[A]])
 ; CHECK: store i32 0, i32* %x
 ; CHECK: %[[P:.*]] = select i1 %flag, i32* %[[A]], i32* %x
-; CHECK: load i32* %[[P]]
+; CHECK: load i32, i32* %[[P]]
 
   %under_aligned = alloca i32, align 1
   call void @scribble_on_i32(i32* %under_aligned)
   store i32 0, i32* %x
   %p = select i1 %flag, i32* %under_aligned, i32* %x
-  %v = load i32* %p
+  %v = load i32, i32* %p
   ret i32 %v
 }
 
@@ -1282,8 +1282,8 @@ define i32 @test78(i1 %flag, i32* %x, i32* %y, i32* %z) {
 ; Test that we can speculate the loads around the select even when we can't
 ; fold the load completely away.
 ; CHECK-LABEL: @test78(
-; CHECK:         %[[V1:.*]] = load i32* %x
-; CHECK-NEXT:    %[[V2:.*]] = load i32* %y
+; CHECK:         %[[V1:.*]] = load i32, i32* %x
+; CHECK-NEXT:    %[[V2:.*]] = load i32, i32* %y
 ; CHECK-NEXT:    %[[S:.*]] = select i1 %flag, i32 %[[V1]], i32 %[[V2]]
 ; CHECK-NEXT:    ret i32 %[[S]]
 entry:
@@ -1292,7 +1292,7 @@ entry:
   ; Block forwarding by storing to %z which could alias either %x or %y.
   store i32 42, i32* %z
   %p = select i1 %flag, i32* %x, i32* %y
-  %v = load i32* %p
+  %v = load i32, i32* %p
   ret i32 %v
 }
 
@@ -1300,8 +1300,8 @@ define float @test79(i1 %flag, float* %x, i32* %y, i32* %z) {
 ; Test that we can speculate the loads around the select even when we can't
 ; fold the load completely away.
 ; CHECK-LABEL: @test79(
-; CHECK:         %[[V1:.*]] = load float* %x
-; CHECK-NEXT:    %[[V2:.*]] = load float* %y
+; CHECK:         %[[V1:.*]] = load float, float* %x
+; CHECK-NEXT:    %[[V2:.*]] = load float, float* %y
 ; CHECK-NEXT:    %[[S:.*]] = select i1 %flag, float %[[V1]], float %[[V2]]
 ; CHECK-NEXT:    ret float %[[S]]
 entry:
@@ -1312,7 +1312,7 @@ entry:
   ; Block forwarding by storing to %z which could alias either %x or %y.
   store i32 42, i32* %z
   %p = select i1 %flag, float* %x, float* %y1
-  %v = load float* %p
+  %v = load float, float* %p
   ret float %v
 }
 
@@ -1322,7 +1322,7 @@ define i32 @test80(i1 %flag) {
 ; CHECK-LABEL: @test80(
 ; CHECK:         %[[X:.*]] = alloca i32
 ; CHECK-NEXT:    %[[Y:.*]] = alloca i32
-; CHECK:         %[[V:.*]] = load i32* %[[X]]
+; CHECK:         %[[V:.*]] = load i32, i32* %[[X]]
 ; CHECK-NEXT:    store i32 %[[V]], i32* %[[Y]]
 ; CHECK-NEXT:    ret i32 %[[V]]
 entry:
@@ -1330,10 +1330,10 @@ entry:
   %y = alloca i32
   call void @scribble_on_i32(i32* %x)
   call void @scribble_on_i32(i32* %y)
-  %tmp = load i32* %x
+  %tmp = load i32, i32* %x
   store i32 %tmp, i32* %y
   %p = select i1 %flag, i32* %x, i32* %y
-  %v = load i32* %p
+  %v = load i32, i32* %p
   ret i32 %v
 }
 
@@ -1343,7 +1343,7 @@ define float @test81(i1 %flag) {
 ; CHECK-LABEL: @test81(
 ; CHECK:         %[[X:.*]] = alloca i32
 ; CHECK-NEXT:    %[[Y:.*]] = alloca i32
-; CHECK:         %[[V:.*]] = load i32* %[[X]]
+; CHECK:         %[[V:.*]] = load i32, i32* %[[X]]
 ; CHECK-NEXT:    store i32 %[[V]], i32* %[[Y]]
 ; CHECK-NEXT:    %[[C:.*]] = bitcast i32 %[[V]] to float
 ; CHECK-NEXT:    ret float %[[C]]
@@ -1354,10 +1354,10 @@ entry:
   %y1 = bitcast i32* %y to float*
   call void @scribble_on_i32(i32* %x1)
   call void @scribble_on_i32(i32* %y)
-  %tmp = load i32* %x1
+  %tmp = load i32, i32* %x1
   store i32 %tmp, i32* %y
   %p = select i1 %flag, float* %x, float* %y1
-  %v = load float* %p
+  %v = load float, float* %p
   ret float %v
 }
 
@@ -1369,7 +1369,7 @@ define i32 @test82(i1 %flag) {
 ; CHECK-NEXT:    %[[Y:.*]] = alloca i32
 ; CHECK-NEXT:    %[[X1:.*]] = bitcast float* %[[X]] to i32*
 ; CHECK-NEXT:    %[[Y1:.*]] = bitcast i32* %[[Y]] to float*
-; CHECK:         %[[V:.*]] = load float* %[[X]]
+; CHECK:         %[[V:.*]] = load float, float* %[[X]]
 ; CHECK-NEXT:    store float %[[V]], float* %[[Y1]]
 ; CHECK-NEXT:    %[[C:.*]] = bitcast float %[[V]] to i32
 ; CHECK-NEXT:    ret i32 %[[C]]
@@ -1380,10 +1380,10 @@ entry:
   %y1 = bitcast i32* %y to float*
   call void @scribble_on_i32(i32* %x1)
   call void @scribble_on_i32(i32* %y)
-  %tmp = load float* %x
+  %tmp = load float, float* %x
   store float %tmp, float* %y1
   %p = select i1 %flag, i32* %x1, i32* %y
-  %v = load i32* %p
+  %v = load i32, i32* %p
   ret i32 %v
 }
 
@@ -1398,7 +1398,7 @@ define i8* @test83(i1 %flag) {
 ; CHECK-NEXT:    %[[Y:.*]] = alloca i8*
 ; CHECK-DAG:     %[[X2:.*]] = bitcast i8** %[[X]] to i64*
 ; CHECK-DAG:     %[[Y2:.*]] = bitcast i8** %[[Y]] to i64*
-; CHECK:         %[[V:.*]] = load i64* %[[X2]]
+; CHECK:         %[[V:.*]] = load i64, i64* %[[X2]]
 ; CHECK-NEXT:    store i64 %[[V]], i64* %[[Y2]]
 ; CHECK-NEXT:    %[[C:.*]] = inttoptr i64 %[[V]] to i8*
 ; CHECK-NEXT:    ret i8* %[[S]]
@@ -1409,10 +1409,10 @@ entry:
   %y1 = bitcast i64* %y to i8**
   call void @scribble_on_i64(i64* %x1)
   call void @scribble_on_i64(i64* %y)
-  %tmp = load i64* %x1
+  %tmp = load i64, i64* %x1
   store i64 %tmp, i64* %y
   %p = select i1 %flag, i8** %x, i8** %y1
-  %v = load i8** %p
+  %v = load i8*, i8** %p
   ret i8* %v
 }
 
@@ -1422,7 +1422,7 @@ define i64 @test84(i1 %flag) {
 ; CHECK-LABEL: @test84(
 ; CHECK:         %[[X:.*]] = alloca i8*
 ; CHECK-NEXT:    %[[Y:.*]] = alloca i8*
-; CHECK:         %[[V:.*]] = load i8** %[[X]]
+; CHECK:         %[[V:.*]] = load i8*, i8** %[[X]]
 ; CHECK-NEXT:    store i8* %[[V]], i8** %[[Y]]
 ; CHECK-NEXT:    %[[C:.*]] = ptrtoint i8* %[[V]] to i64
 ; CHECK-NEXT:    ret i64 %[[C]]
@@ -1433,10 +1433,10 @@ entry:
   %y1 = bitcast i64* %y to i8**
   call void @scribble_on_i64(i64* %x1)
   call void @scribble_on_i64(i64* %y)
-  %tmp = load i8** %x
+  %tmp = load i8*, i8** %x
   store i8* %tmp, i8** %y1
   %p = select i1 %flag, i64* %x1, i64* %y
-  %v = load i64* %p
+  %v = load i64, i64* %p
   ret i64 %v
 }
 
@@ -1445,10 +1445,10 @@ define i8* @test85(i1 %flag) {
 ; pointer doesn't load all of the stored integer bits. We could fix this, but it
 ; would require endianness checks and other nastiness.
 ; CHECK-LABEL: @test85(
-; CHECK:         %[[T:.*]] = load i128*
+; CHECK:         %[[T:.*]] = load i128, i128*
 ; CHECK-NEXT:    store i128 %[[T]], i128*
-; CHECK-NEXT:    %[[X:.*]] = load i8**
-; CHECK-NEXT:    %[[Y:.*]] = load i8**
+; CHECK-NEXT:    %[[X:.*]] = load i8*, i8**
+; CHECK-NEXT:    %[[Y:.*]] = load i8*, i8**
 ; CHECK-NEXT:    %[[V:.*]] = select i1 %flag, i8* %[[X]], i8* %[[Y]]
 ; CHECK-NEXT:    ret i8* %[[V]]
 entry:
@@ -1459,10 +1459,10 @@ entry:
   %y1 = bitcast i128* %y to i8**
   call void @scribble_on_i128(i128* %x2)
   call void @scribble_on_i128(i128* %y)
-  %tmp = load i128* %x2
+  %tmp = load i128, i128* %x2
   store i128 %tmp, i128* %y
   %p = select i1 %flag, i8** %x1, i8** %y1
-  %v = load i8** %p
+  %v = load i8*, i8** %p
   ret i8* %v
 }
 
@@ -1472,10 +1472,10 @@ define i128 @test86(i1 %flag) {
 ; the bits of the integer.
 ;
 ; CHECK-LABEL: @test86(
-; CHECK:         %[[T:.*]] = load i8**
+; CHECK:         %[[T:.*]] = load i8*, i8**
 ; CHECK-NEXT:    store i8* %[[T]], i8**
-; CHECK-NEXT:    %[[X:.*]] = load i128*
-; CHECK-NEXT:    %[[Y:.*]] = load i128*
+; CHECK-NEXT:    %[[X:.*]] = load i128, i128*
+; CHECK-NEXT:    %[[Y:.*]] = load i128, i128*
 ; CHECK-NEXT:    %[[V:.*]] = select i1 %flag, i128 %[[X]], i128 %[[Y]]
 ; CHECK-NEXT:    ret i128 %[[V]]
 entry:
@@ -1486,9 +1486,49 @@ entry:
   %y1 = bitcast i128* %y to i8**
   call void @scribble_on_i128(i128* %x2)
   call void @scribble_on_i128(i128* %y)
-  %tmp = load i8** %x1
+  %tmp = load i8*, i8** %x1
   store i8* %tmp, i8** %y1
   %p = select i1 %flag, i128* %x2, i128* %y
-  %v = load i128* %p
+  %v = load i128, i128* %p
   ret i128 %v
 }
+
+define i32 @test_select_select0(i32 %a, i32 %r0, i32 %r1, i32 %v1, i32 %v2) {
+  ; CHECK-LABEL: @test_select_select0(
+  ; CHECK: %[[C0:.*]] = icmp sge i32 %a, %v1
+  ; CHECK-NEXT: %[[C1:.*]] = icmp slt i32 %a, %v2
+  ; CHECK-NEXT: %[[C:.*]] = and i1 %[[C1]], %[[C0]]
+  ; CHECK-NEXT: %[[SEL:.*]] = select i1 %[[C]], i32 %r0, i32 %r1
+  ; CHECK-NEXT: ret i32 %[[SEL]]
+  %c0 = icmp sge i32 %a, %v1
+  %s0 = select i1 %c0, i32 %r0, i32 %r1
+  %c1 = icmp slt i32 %a, %v2
+  %s1 = select i1 %c1, i32 %s0, i32 %r1
+  ret i32 %s1
+}
+
+define i32 @test_select_select1(i32 %a, i32 %r0, i32 %r1, i32 %v1, i32 %v2) {
+  ; CHECK-LABEL: @test_select_select1(
+  ; CHECK: %[[C0:.*]] = icmp sge i32 %a, %v1
+  ; CHECK-NEXT: %[[C1:.*]] = icmp slt i32 %a, %v2
+  ; CHECK-NEXT: %[[C:.*]] = or i1 %[[C1]], %[[C0]]
+  ; CHECK-NEXT: %[[SEL:.*]] = select i1 %[[C]], i32 %r0, i32 %r1
+  ; CHECK-NEXT: ret i32 %[[SEL]]
+  %c0 = icmp sge i32 %a, %v1
+  %s0 = select i1 %c0, i32 %r0, i32 %r1
+  %c1 = icmp slt i32 %a, %v2
+  %s1 = select i1 %c1, i32 %r0, i32 %s0
+  ret i32 %s1
+}
+
+define i32 @test_max_of_min(i32 %a) {
+; MAX(MIN(%a, -1), -1) == -1
+; CHECK-LABEL: @test_max_of_min(
+; CHECK: ret i32 -1
+  %not_a = xor i32 %a, -1
+  %c0 = icmp sgt i32 %a, 0
+  %s0 = select i1 %c0, i32 %not_a, i32 -1
+  %c1 = icmp sgt i32 %s0, -1
+  %s1 = select i1 %c1, i32 %s0, i32 -1
+  ret i32 %s1
+}
diff --git a/test/Transforms/InstCombine/shift.ll b/test/Transforms/InstCombine/shift.ll
index 0b5b5deb68c5..79c2ae28105e 100644
--- a/test/Transforms/InstCombine/shift.ll
+++ b/test/Transforms/InstCombine/shift.ll
@@ -575,7 +575,7 @@ entry:
 ; CHECK: %0 = shl i8 %tmp4, 2
 ; CHECK: %tmp54 = and i8 %0, 16
   %tmp55 = xor i8 %tmp54, %tmp51
-; CHECK: ret i8 %tmp551
+; CHECK: ret i8 %tmp55.1
   ret i8 %tmp55
 }
 
@@ -743,7 +743,7 @@ define i32 @test57(i32 %x) {
   %or = or i32 %shl, 7
   ret i32 %or
 ; CHECK-LABEL: @test57(
-; CHECK: %shl = shl i32 %shr1, 4
+; CHECK: %shl = shl i32 %shr.1, 4
 }
 
 
diff --git a/test/Transforms/InstCombine/shufflemask-undef.ll b/test/Transforms/InstCombine/shufflemask-undef.ll
index aa6baa989bfc..10509a92941b 100644
--- a/test/Transforms/InstCombine/shufflemask-undef.ll
+++ b/test/Transforms/InstCombine/shufflemask-undef.ll
@@ -69,8 +69,8 @@ target triple = "i386-apple-darwin9"
 
 define i32 @foo(%struct.State* %dst, <4 x float>* %prgrm, <4 x float>** %buffs, %struct._VMConstants* %cnstn, %struct.PPStreamToken* %pstrm, %struct.PluginBufferData* %gpctx, %struct.VMTextures* %txtrs, %struct.VMGPStack* %gpstk) nounwind {
 bb266.i:
-	getelementptr <4 x float>* null, i32 11		; <<4 x float>*>:0 [#uses=1]
-	load <4 x float>* %0, align 16		; <<4 x float>>:1 [#uses=1]
+	getelementptr <4 x float>, <4 x float>* null, i32 11		; <<4 x float>*>:0 [#uses=1]
+	load <4 x float>, <4 x float>* %0, align 16		; <<4 x float>>:1 [#uses=1]
 	shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> < i32 0, i32 1, i32 1, i32 1 >		; <<4 x float>>:2 [#uses=1]
 	shufflevector <4 x float> %2, <4 x float> undef, <4 x i32> < i32 0, i32 4, i32 1, i32 5 >		; <<4 x float>>:3 [#uses=1]
 	shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> < i32 0, i32 4, i32 1, i32 5 >		; <<4 x float>>:4 [#uses=1]
diff --git a/test/Transforms/InstCombine/signed-comparison.ll b/test/Transforms/InstCombine/signed-comparison.ll
index ab0e7e7ff9fe..922f4dcb2d42 100644
--- a/test/Transforms/InstCombine/signed-comparison.ll
+++ b/test/Transforms/InstCombine/signed-comparison.ll
@@ -12,8 +12,8 @@ entry:
 bb:
 	%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %bb ]
 	%t0 = and i64 %indvar, 65535
-	%t1 = getelementptr double* %p, i64 %t0
-	%t2 = load double* %t1, align 8
+	%t1 = getelementptr double, double* %p, i64 %t0
+	%t2 = load double, double* %t1, align 8
 	%t3 = fmul double %t2, 2.2
 	store double %t3, double* %t1, align 8
 	%i.04 = trunc i64 %indvar to i16
diff --git a/test/Transforms/InstCombine/simplify-demanded-bits-pointer.ll b/test/Transforms/InstCombine/simplify-demanded-bits-pointer.ll
index 6d2193fe448a..db8f17917d1e 100644
--- a/test/Transforms/InstCombine/simplify-demanded-bits-pointer.ll
+++ b/test/Transforms/InstCombine/simplify-demanded-bits-pointer.ll
@@ -29,7 +29,7 @@ bb95:		; preds = %bb88
 	unreachable
 
 bb107:		; preds = %bb88
-	%0 = load i16* undef, align 8		; <i16> [#uses=1]
+	%0 = load i16, i16* undef, align 8		; <i16> [#uses=1]
 	%1 = icmp eq i16 %0, 38		; <i1> [#uses=1]
 	%src_eqv_here.0 = select i1 %1, %struct.rtx_def* null, %struct.rtx_def* null		; <%struct.rtx_def*> [#uses=1]
 	br i1 undef, label %bb127, label %bb125
diff --git a/test/Transforms/InstCombine/simplify-libcalls.ll b/test/Transforms/InstCombine/simplify-libcalls.ll
index fae3e6e3d9be..7cc671061379 100644
--- a/test/Transforms/InstCombine/simplify-libcalls.ll
+++ b/test/Transforms/InstCombine/simplify-libcalls.ll
@@ -1,11 +1,12 @@
 ; RUN: opt -S < %s -instcombine | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"
 
 @G = constant [3 x i8] c"%s\00"		; <[3 x i8]*> [#uses=1]
 
 declare i32 @sprintf(i8*, i8*, ...)
 
 define void @foo(i8* %P, i32* %X) {
-	call i32 (i8*, i8*, ...)* @sprintf( i8* %P, i8* getelementptr ([3 x i8]* @G, i32 0, i32 0), i32* %X )		; <i32>:1 [#uses=0]
+	call i32 (i8*, i8*, ...) @sprintf( i8* %P, i8* getelementptr ([3 x i8], [3 x i8]* @G, i32 0, i32 0), i32* %X )		; <i32>:1 [#uses=0]
 	ret void
 }
 
@@ -15,26 +16,26 @@ define void @foo(i8* %P, i32* %X) {
 @str2 = internal constant [5 x i8] c"Ponk\00"
 
 define i8* @test1() {
-        %tmp3 = tail call i8* @strchr( i8* getelementptr ([5 x i8]* @str, i32 0, i32 2), i32 103 )              ; <i8*> [#uses=1]
+        %tmp3 = tail call i8* @strchr( i8* getelementptr ([5 x i8], [5 x i8]* @str, i32 0, i32 2), i32 103 )              ; <i8*> [#uses=1]
         ret i8* %tmp3
 
 ; CHECK-LABEL: @test1(
-; CHECK: ret i8* getelementptr inbounds ([5 x i8]* @str, i32 0, i64 3)
+; CHECK: ret i8* getelementptr inbounds ([5 x i8], [5 x i8]* @str, i32 0, i32 3)
 }
 
 declare i8* @strchr(i8*, i32)
 
 define i8* @test2() {
-        %tmp3 = tail call i8* @strchr( i8* getelementptr ([8 x i8]* @str1, i32 0, i32 2), i32 0 )               ; <i8*> [#uses=1]
+        %tmp3 = tail call i8* @strchr( i8* getelementptr ([8 x i8], [8 x i8]* @str1, i32 0, i32 2), i32 0 )               ; <i8*> [#uses=1]
         ret i8* %tmp3
 
 ; CHECK-LABEL: @test2(
-; CHECK: ret i8* getelementptr inbounds ([8 x i8]* @str1, i32 0, i64 7)
+; CHECK: ret i8* getelementptr inbounds ([8 x i8], [8 x i8]* @str1, i32 0, i32 7)
 }
 
 define i8* @test3() {
 entry:
-        %tmp3 = tail call i8* @strchr( i8* getelementptr ([5 x i8]* @str2, i32 0, i32 1), i32 80 )              ; <i8*> [#uses=1]
+        %tmp3 = tail call i8* @strchr( i8* getelementptr ([5 x i8], [5 x i8]* @str2, i32 0, i32 1), i32 80 )              ; <i8*> [#uses=1]
         ret i8* %tmp3
 
 ; CHECK-LABEL: @test3(
@@ -47,8 +48,8 @@ declare i32 @memcmp(i8*, i8*, i32) nounwind readonly
 
 define i1 @PR2341(i8** %start_addr) {
 entry:
-	%tmp4 = load i8** %start_addr, align 4		; <i8*> [#uses=1]
-	%tmp5 = call i32 @memcmp( i8* %tmp4, i8* getelementptr ([5 x i8]* @_2E_str, i32 0, i32 0), i32 4 ) nounwind readonly 		; <i32> [#uses=1]
+	%tmp4 = load i8*, i8** %start_addr, align 4		; <i8*> [#uses=1]
+	%tmp5 = call i32 @memcmp( i8* %tmp4, i8* getelementptr ([5 x i8], [5 x i8]* @_2E_str, i32 0, i32 0), i32 4 ) nounwind readonly 		; <i32> [#uses=1]
 	%tmp6 = icmp eq i32 %tmp5, 0		; <i1> [#uses=1]
 	ret i1 %tmp6
 
@@ -80,7 +81,7 @@ entry:
 define i32 @PR4641(i32 %argc, i8** %argv) nounwind {
 entry:
 	call void @exit(i32 0) nounwind
-	%cond392 = select i1 undef, i8* getelementptr ([2 x i8]* @.str13, i32 0, i32 0), i8* getelementptr ([2 x i8]* @.str14, i32 0, i32 0)		; <i8*> [#uses=1]
+	%cond392 = select i1 undef, i8* getelementptr ([2 x i8], [2 x i8]* @.str13, i32 0, i32 0), i8* getelementptr ([2 x i8], [2 x i8]* @.str14, i32 0, i32 0)		; <i8*> [#uses=1]
 	%call393 = call %struct.__sFILE* @fopen(i8* undef, i8* %cond392) nounwind		; <%struct.__sFILE*> [#uses=0]
 	unreachable
 }
@@ -114,11 +115,11 @@ for.end:		; preds = %for.cond20
 @hello_u = constant [8 x i8] c"hello_u\00"		; <[8 x i8]*> [#uses=1]
 
 define i32 @MemCpy() {
-  %h_p = getelementptr [2 x i8]* @h, i32 0, i32 0
-  %hel_p = getelementptr [4 x i8]* @hel, i32 0, i32 0
-  %hello_u_p = getelementptr [8 x i8]* @hello_u, i32 0, i32 0
+  %h_p = getelementptr [2 x i8], [2 x i8]* @h, i32 0, i32 0
+  %hel_p = getelementptr [4 x i8], [4 x i8]* @hel, i32 0, i32 0
+  %hello_u_p = getelementptr [8 x i8], [8 x i8]* @hello_u, i32 0, i32 0
   %target = alloca [1024 x i8]
-  %target_p = getelementptr [1024 x i8]* %target, i32 0, i32 0
+  %target_p = getelementptr [1024 x i8], [1024 x i8]* %target, i32 0, i32 0
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %target_p, i8* %h_p, i32 2, i32 2, i1 false)
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %target_p, i8* %hel_p, i32 4, i32 4, i1 false)
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %target_p, i8* %hello_u_p, i32 8, i32 8, i1 false)
diff --git a/test/Transforms/InstCombine/sincospi.ll b/test/Transforms/InstCombine/sincospi.ll
index 739827f1962a..f49fb35cb76a 100644
--- a/test/Transforms/InstCombine/sincospi.ll
+++ b/test/Transforms/InstCombine/sincospi.ll
@@ -18,17 +18,17 @@ declare double @__cospi(double %x) #0
 @var64 = global double 0.0
 
 define float @test_instbased_f32() {
-       %val = load float* @var32
+       %val = load float, float* @var32
        %sin = call float @__sinpif(float %val) #0
        %cos = call float @__cospif(float %val) #0
        %res = fadd float %sin, %cos
        ret float %res
-; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load float* @var32
+; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load float, float* @var32
 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float [[VAL]])
 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 0
 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 1
 
-; CHECK: [[VAL:%[a-z0-9]+]] = load float* @var32
+; CHECK: [[VAL:%[a-z0-9]+]] = load float, float* @var32
 ; CHECK: [[SINCOS:%[a-z0-9]+]] = call { float, float } @__sincospif_stret(float [[VAL]])
 ; CHECK: extractvalue { float, float } [[SINCOS]], 0
 ; CHECK: extractvalue { float, float } [[SINCOS]], 1
@@ -55,17 +55,17 @@ define float @test_constant_f32() {
 }
 
 define double @test_instbased_f64() {
-       %val = load double* @var64
+       %val = load double, double* @var64
        %sin = call double @__sinpi(double %val) #0
        %cos = call double @__cospi(double %val) #0
        %res = fadd double %sin, %cos
        ret double %res
-; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load double* @var64
+; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load double, double* @var64
 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call { double, double } @__sincospi_stret(double [[VAL]])
 ; CHECK-FLOAT-IN-VEC: extractvalue { double, double } [[SINCOS]], 0
 ; CHECK-FLOAT-IN-VEC: extractvalue { double, double } [[SINCOS]], 1
 
-; CHECK: [[VAL:%[a-z0-9]+]] = load double* @var64
+; CHECK: [[VAL:%[a-z0-9]+]] = load double, double* @var64
 ; CHECK: [[SINCOS:%[a-z0-9]+]] = call { double, double } @__sincospi_stret(double [[VAL]])
 ; CHECK: extractvalue { double, double } [[SINCOS]], 0
 ; CHECK: extractvalue { double, double } [[SINCOS]], 1
diff --git a/test/Transforms/InstCombine/sitofp.ll b/test/Transforms/InstCombine/sitofp.ll
index bd31b89f7879..820977838836 100644
--- a/test/Transforms/InstCombine/sitofp.ll
+++ b/test/Transforms/InstCombine/sitofp.ll
@@ -1,28 +1,40 @@
-; RUN: opt < %s -instcombine -S | not grep itofp
+; RUN: opt < %s -instcombine -S | FileCheck %s
 
+; CHECK-LABEL: test1
+; CHECK: ret i1 true
 define i1 @test1(i8 %A) {
   %B = sitofp i8 %A to double
   %C = fcmp ult double %B, 128.0
-  ret i1 %C  ;  True!
+  ret i1 %C
 }
+
+; CHECK-LABEL: test2
+; CHECK: ret i1 true
 define i1 @test2(i8 %A) {
   %B = sitofp i8 %A to double
   %C = fcmp ugt double %B, -128.1
-  ret i1 %C  ;  True!
+  ret i1 %C
 }
 
+; CHECK-LABEL: test3
+; CHECK: ret i1 true
 define i1 @test3(i8 %A) {
   %B = sitofp i8 %A to double
   %C = fcmp ule double %B, 127.0
-  ret i1 %C  ;  true!
+  ret i1 %C
 }
 
+; CHECK-LABEL: test4
+; CHECK: icmp ne i8 %A, 127
+; CHECK-NEXT: ret i1
 define i1 @test4(i8 %A) {
   %B = sitofp i8 %A to double
   %C = fcmp ult double %B, 127.0
-  ret i1 %C  ;  A != 127
+  ret i1 %C
 }
 
+; CHECK-LABEL: test5
+; CHECK: ret i32
 define i32 @test5(i32 %A) {
   %B = sitofp i32 %A to double
   %C = fptosi double %B to i32
@@ -31,25 +43,142 @@ define i32 @test5(i32 %A) {
   ret i32 %E
 }
 
+; CHECK-LABEL: test6
+; CHECK: and i32 %A, 39
+; CHECK-NEXT: ret i32
 define i32 @test6(i32 %A) {
-	%B = and i32 %A, 7		; <i32> [#uses=1]
-	%C = and i32 %A, 32		; <i32> [#uses=1]
-	%D = sitofp i32 %B to double		; <double> [#uses=1]
-	%E = sitofp i32 %C to double		; <double> [#uses=1]
-	%F = fadd double %D, %E		; <double> [#uses=1]
-	%G = fptosi double %F to i32		; <i32> [#uses=1]
-	ret i32 %G
+  %B = and i32 %A, 7
+  %C = and i32 %A, 32
+  %D = sitofp i32 %B to double
+  %E = sitofp i32 %C to double
+  %F = fadd double %D, %E
+  %G = fptosi double %F to i32
+  ret i32 %G
+}
+
+; CHECK-LABEL: test7
+; CHECK: ret i32
+define i32 @test7(i32 %A) nounwind {
+  %B = sitofp i32 %A to double
+  %C = fptoui double %B to i32
+  ret i32 %C
+}
+
+; CHECK-LABEL: test8
+; CHECK: ret i32
+define i32 @test8(i32 %A) nounwind {
+  %B = uitofp i32 %A to double
+  %C = fptosi double %B to i32
+  ret i32 %C
+}
+
+; CHECK-LABEL: test9
+; CHECK: zext i8
+; CHECK-NEXT: ret i32
+define i32 @test9(i8 %A) nounwind {
+  %B = sitofp i8 %A to float
+  %C = fptoui float %B to i32
+  ret i32 %C
+}
+
+; CHECK-LABEL: test10
+; CHECK: sext i8
+; CHECK-NEXT: ret i32
+define i32 @test10(i8 %A) nounwind {
+  %B = sitofp i8 %A to float
+  %C = fptosi float %B to i32
+  ret i32 %C
+}
+
+; If the input value is outside of the range of the output cast, it's
+; undefined behavior, so we can assume it fits.
+; CHECK-LABEL: test11
+; CHECK: trunc
+; CHECK-NEXT: ret i8
+define i8 @test11(i32 %A) nounwind {
+  %B = sitofp i32 %A to float
+  %C = fptosi float %B to i8
+  ret i8 %C
+}
+
+; If the input value is negative, it'll be outside the range of the
+; output cast, and thus undefined behavior.
+; CHECK-LABEL: test12
+; CHECK: zext i8
+; CHECK-NEXT: ret i32
+define i32 @test12(i8 %A) nounwind {
+  %B = sitofp i8 %A to float
+  %C = fptoui float %B to i32
+  ret i32 %C
+}
+
+; This can't fold because the 25-bit input doesn't fit in the mantissa.
+; CHECK-LABEL: test13
+; CHECK: uitofp
+; CHECK-NEXT: fptoui
+define i32 @test13(i25 %A) nounwind {
+  %B = uitofp i25 %A to float
+  %C = fptoui float %B to i32
+  ret i32 %C
+}
+
+; But this one can.
+; CHECK-LABEL: test14
+; CHECK: zext i24
+; CHECK-NEXT: ret i32
+define i32 @test14(i24 %A) nounwind {
+  %B = uitofp i24 %A to float
+  %C = fptoui float %B to i32
+  ret i32 %C
+}
+
+; And this one can too.
+; CHECK-LABEL: test15
+; CHECK: trunc i32
+; CHECK-NEXT: ret i24
+define i24 @test15(i32 %A) nounwind {
+  %B = uitofp i32 %A to float
+  %C = fptoui float %B to i24
+  ret i24 %C
+}
+
+; This can fold because the 25-bit input is signed and we disard the sign bit.
+; CHECK-LABEL: test16
+; CHECK: zext
+define i32 @test16(i25 %A) nounwind {
+ %B = sitofp i25 %A to float
+ %C = fptoui float %B to i32
+ ret i32 %C
+}
+
+; This can't fold because the 26-bit input won't fit the mantissa
+; even after disarding the signed bit.
+; CHECK-LABEL: test17
+; CHECK: sitofp
+; CHECK-NEXT: fptoui
+define i32 @test17(i26 %A) nounwind {
+ %B = sitofp i26 %A to float
+ %C = fptoui float %B to i32
+ ret i32 %C
 }
 
-define i32 @test7(i32 %a) nounwind {
-	%b = sitofp i32 %a to double		; <double> [#uses=1]
-	%c = fptoui double %b to i32		; <i32> [#uses=1]
-	ret i32 %c
+; This can fold because the 54-bit output is signed and we disard the sign bit.
+; CHECK-LABEL: test18
+; CHECK: trunc
+define i54 @test18(i64 %A) nounwind {
+ %B = sitofp i64 %A to double
+ %C = fptosi double %B to i54
+ ret i54 %C
 }
 
-define i32 @test8(i32 %a) nounwind {
-	%b = uitofp i32 %a to double		; <double> [#uses=1]
-	%c = fptosi double %b to i32		; <i32> [#uses=1]
-	ret i32 %c
+; This can't fold because the 55-bit output won't fit the mantissa
+; even after disarding the sign bit.
+; CHECK-LABEL: test19
+; CHECK: sitofp
+; CHECK-NEXT: fptosi
+define i55 @test19(i64 %A) nounwind {
+ %B = sitofp i64 %A to double
+ %C = fptosi double %B to i55
+ ret i55 %C
 }
 
diff --git a/test/Transforms/InstCombine/sprintf-1.ll b/test/Transforms/InstCombine/sprintf-1.ll
index afa38f35ae83..ddf2f2f88e73 100644
--- a/test/Transforms/InstCombine/sprintf-1.ll
+++ b/test/Transforms/InstCombine/sprintf-1.ll
@@ -20,17 +20,17 @@ declare i32 @sprintf(i8*, i8*, ...)
 
 define void @test_simplify1(i8* %dst) {
 ; CHECK-LABEL: @test_simplify1(
-  %fmt = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
-  call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt)
-; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* getelementptr inbounds ([13 x i8]* @hello_world, i32 0, i32 0), i32 13, i32 1, i1 false)
+  %fmt = getelementptr [13 x i8], [13 x i8]* @hello_world, i32 0, i32 0
+  call i32 (i8*, i8*, ...) @sprintf(i8* %dst, i8* %fmt)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @hello_world, i32 0, i32 0), i32 13, i32 1, i1 false)
   ret void
 ; CHECK-NEXT: ret void
 }
 
 define void @test_simplify2(i8* %dst) {
 ; CHECK-LABEL: @test_simplify2(
-  %fmt = getelementptr [1 x i8]* @null, i32 0, i32 0
-  call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt)
+  %fmt = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
+  call i32 (i8*, i8*, ...) @sprintf(i8* %dst, i8* %fmt)
 ; CHECK-NEXT: store i8 0, i8* %dst, align 1
   ret void
 ; CHECK-NEXT: ret void
@@ -38,8 +38,8 @@ define void @test_simplify2(i8* %dst) {
 
 define void @test_simplify3(i8* %dst) {
 ; CHECK-LABEL: @test_simplify3(
-  %fmt = getelementptr [7 x i8]* @null_hello, i32 0, i32 0
-  call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt)
+  %fmt = getelementptr [7 x i8], [7 x i8]* @null_hello, i32 0, i32 0
+  call i32 (i8*, i8*, ...) @sprintf(i8* %dst, i8* %fmt)
 ; CHECK-NEXT: store i8 0, i8* %dst, align 1
   ret void
 ; CHECK-NEXT: ret void
@@ -49,10 +49,10 @@ define void @test_simplify3(i8* %dst) {
 
 define void @test_simplify4(i8* %dst) {
 ; CHECK-LABEL: @test_simplify4(
-  %fmt = getelementptr [3 x i8]* @percent_c, i32 0, i32 0
-  call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt, i8 104)
+  %fmt = getelementptr [3 x i8], [3 x i8]* @percent_c, i32 0, i32 0
+  call i32 (i8*, i8*, ...) @sprintf(i8* %dst, i8* %fmt, i8 104)
 ; CHECK-NEXT: store i8 104, i8* %dst, align 1
-; CHECK-NEXT: [[NUL:%[a-z0-9]+]] = getelementptr i8* %dst, i32 1
+; CHECK-NEXT: [[NUL:%[a-z0-9]+]] = getelementptr i8, i8* %dst, i32 1
 ; CHECK-NEXT: store i8 0, i8* [[NUL]], align 1
   ret void
 ; CHECK-NEXT: ret void
@@ -62,8 +62,8 @@ define void @test_simplify4(i8* %dst) {
 
 define void @test_simplify5(i8* %dst, i8* %str) {
 ; CHECK-LABEL: @test_simplify5(
-  %fmt = getelementptr [3 x i8]* @percent_s, i32 0, i32 0
-  call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt, i8* %str)
+  %fmt = getelementptr [3 x i8], [3 x i8]* @percent_s, i32 0, i32 0
+  call i32 (i8*, i8*, ...) @sprintf(i8* %dst, i8* %fmt, i8* %str)
 ; CHECK-NEXT: [[STRLEN:%[a-z0-9]+]] = call i32 @strlen(i8* %str)
 ; CHECK-NEXT: [[LENINC:%[a-z0-9]+]] = add i32 [[STRLEN]], 1
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %str, i32 [[LENINC]], i32 1, i1 false)
@@ -75,26 +75,26 @@ define void @test_simplify5(i8* %dst, i8* %str) {
 
 define void @test_simplify6(i8* %dst) {
 ; CHECK-IPRINTF-LABEL: @test_simplify6(
-  %fmt = getelementptr [3 x i8]* @percent_d, i32 0, i32 0
-  call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt, i32 187)
-; CHECK-IPRINTF-NEXT: call i32 (i8*, i8*, ...)* @siprintf(i8* %dst, i8* getelementptr inbounds ([3 x i8]* @percent_d, i32 0, i32 0), i32 187)
+  %fmt = getelementptr [3 x i8], [3 x i8]* @percent_d, i32 0, i32 0
+  call i32 (i8*, i8*, ...) @sprintf(i8* %dst, i8* %fmt, i32 187)
+; CHECK-IPRINTF-NEXT: call i32 (i8*, i8*, ...) @siprintf(i8* %dst, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @percent_d, i32 0, i32 0), i32 187)
   ret void
 ; CHECK-IPRINTF-NEXT: ret void
 }
 
 define void @test_no_simplify1(i8* %dst) {
 ; CHECK-IPRINTF-LABEL: @test_no_simplify1(
-  %fmt = getelementptr [3 x i8]* @percent_f, i32 0, i32 0
-  call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt, double 1.87)
-; CHECK-IPRINTF-NEXT: call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* getelementptr inbounds ([3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00)
+  %fmt = getelementptr [3 x i8], [3 x i8]* @percent_f, i32 0, i32 0
+  call i32 (i8*, i8*, ...) @sprintf(i8* %dst, i8* %fmt, double 1.87)
+; CHECK-IPRINTF-NEXT: call i32 (i8*, i8*, ...) @sprintf(i8* %dst, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00)
   ret void
 ; CHECK-IPRINTF-NEXT: ret void
 }
 
 define void @test_no_simplify2(i8* %dst, i8* %fmt, double %d) {
 ; CHECK-LABEL: @test_no_simplify2(
-  call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt, double %d)
-; CHECK-NEXT: call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt, double %d)
+  call i32 (i8*, i8*, ...) @sprintf(i8* %dst, i8* %fmt, double %d)
+; CHECK-NEXT: call i32 (i8*, i8*, ...) @sprintf(i8* %dst, i8* %fmt, double %d)
   ret void
 ; CHECK-NEXT: ret void
 }
diff --git a/test/Transforms/InstCombine/sqrt.ll b/test/Transforms/InstCombine/sqrt.ll
index 650b10c6e966..bf44e4f841ce 100644
--- a/test/Transforms/InstCombine/sqrt.ll
+++ b/test/Transforms/InstCombine/sqrt.ll
@@ -38,13 +38,13 @@ entry:
 ; CHECK: sqrt(
 ; CHECK-NOT: sqrtf(
 ; CHECK: fptrunc
-  %arrayidx13 = getelementptr inbounds float* %v, i64 2
-  %tmp14 = load float* %arrayidx13
+  %arrayidx13 = getelementptr inbounds float, float* %v, i64 2
+  %tmp14 = load float, float* %arrayidx13
   %mul18 = fmul float %tmp14, %tmp14
   %add19 = fadd float undef, %mul18
   %conv = fpext float %add19 to double
   %call34 = call double @sqrt(double %conv) readnone
-  %call36 = call i32 (double)* @foo(double %call34) nounwind
+  %call36 = call i32 (double) @foo(double %call34) nounwind
   %conv38 = fptrunc double %call34 to float
   ret float %conv38
 }
diff --git a/test/Transforms/InstCombine/srem1.ll b/test/Transforms/InstCombine/srem1.ll
index f18690c3fff2..31452d8f208a 100644
--- a/test/Transforms/InstCombine/srem1.ll
+++ b/test/Transforms/InstCombine/srem1.ll
@@ -5,7 +5,7 @@
 
 define i32 @func_56(i32 %p_58, i32 %p_59, i32 %p_61, i16 signext %p_62) nounwind {
 entry:
-	%call = call i32 (...)* @rshift_s_s( i32 %p_61, i32 1 )		; <i32> [#uses=1]
+	%call = call i32 (...) @rshift_s_s( i32 %p_61, i32 1 )		; <i32> [#uses=1]
 	%conv = sext i32 %call to i64		; <i64> [#uses=1]
 	%or = or i64 -1734012817166602727, %conv		; <i64> [#uses=1]
 	%rem = srem i64 %or, 1		; <i64> [#uses=1]
diff --git a/test/Transforms/InstCombine/stack-overalign.ll b/test/Transforms/InstCombine/stack-overalign.ll
index 80c2ee88f340..a8f086e6cb93 100644
--- a/test/Transforms/InstCombine/stack-overalign.ll
+++ b/test/Transforms/InstCombine/stack-overalign.ll
@@ -18,8 +18,8 @@
 define void @foo() nounwind {
 entry:
   %src = alloca [1024 x i8], align 1
-  %src1 = getelementptr [1024 x i8]* %src, i32 0, i32 0
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([1024 x i8]* @dst, i32 0, i32 0), i8* %src1, i32 1024, i32 1, i1 false)
+  %src1 = getelementptr [1024 x i8], [1024 x i8]* %src, i32 0, i32 0
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dst, i32 0, i32 0), i8* %src1, i32 1024, i32 1, i1 false)
   call void @frob(i8* %src1) nounwind
   ret void
 }
diff --git a/test/Transforms/InstCombine/stacksaverestore.ll b/test/Transforms/InstCombine/stacksaverestore.ll
index f5c7a6f9f3f9..de400e91a751 100644
--- a/test/Transforms/InstCombine/stacksaverestore.ll
+++ b/test/Transforms/InstCombine/stacksaverestore.ll
@@ -31,7 +31,7 @@ bb:		; preds = %bb, %bb.preheader
 	%i.0.reg2mem.0 = phi i32 [ 0, %bb.preheader ], [ %indvar.next, %bb ]		; <i32> [#uses=2]
 	%tmp = call i8* @llvm.stacksave( )		; <i8*> [#uses=1]
 	%tmp23 = alloca i8, i32 %size		; <i8*> [#uses=2]
-	%tmp27 = getelementptr i8* %tmp23, i32 %tmp25		; <i8*> [#uses=1]
+	%tmp27 = getelementptr i8, i8* %tmp23, i32 %tmp25		; <i8*> [#uses=1]
 	store i8 0, i8* %tmp27, align 1
 	%tmp28 = call i8* @llvm.stacksave( )		; <i8*> [#uses=1]
 	%tmp52 = alloca i8, i32 %size		; <i8*> [#uses=1]
diff --git a/test/Transforms/InstCombine/statepoint.ll b/test/Transforms/InstCombine/statepoint.ll
index bee219db9c12..f904f207bfdc 100644
--- a/test/Transforms/InstCombine/statepoint.ll
+++ b/test/Transforms/InstCombine/statepoint.ll
@@ -5,10 +5,10 @@
 
 declare void @func()
 
-define i1 @test_negative(i32 addrspace(1)* %p) {
+define i1 @test_negative(i32 addrspace(1)* %p) gc "statepoint-example" {
 entry:
-  %safepoint_token = tail call i32 (void ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_isVoidf(void ()* @func, i32 0, i32 0, i32 0, i32 addrspace(1)* %p)
-  %pnew = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 4, i32 4)
+  %safepoint_token = tail call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @func, i32 0, i32 0, i32 0, i32 0, i32 addrspace(1)* %p)
+  %pnew = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token,  i32 7, i32 7)
   %cmp = icmp eq i32 addrspace(1)* %pnew, null
   ret i1 %cmp
 ; CHECK-LABEL: test_negative
@@ -16,20 +16,20 @@ entry:
 ; CHECK: ret i1 %cmp
 }
 
-define i1 @test_nonnull(i32 addrspace(1)* nonnull %p) {
+define i1 @test_nonnull(i32 addrspace(1)* nonnull %p) gc "statepoint-example" {
 entry:
-  %safepoint_token = tail call i32 (void ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_isVoidf(void ()* @func, i32 0, i32 0, i32 0, i32 addrspace(1)* %p)
-  %pnew = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 4, i32 4)
+  %safepoint_token = tail call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @func, i32 0, i32 0, i32 0, i32 0, i32 addrspace(1)* %p)
+  %pnew = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token,  i32 7, i32 7)
   %cmp = icmp eq i32 addrspace(1)* %pnew, null
   ret i1 %cmp
 ; CHECK-LABEL: test_nonnull
 ; CHECK: ret i1 false
 }
 
-define i1 @test_null() {
+define i1 @test_null() gc "statepoint-example" {
 entry:
-  %safepoint_token = tail call i32 (void ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_isVoidf(void ()* @func, i32 0, i32 0, i32 0, i32 addrspace(1)* null)
-  %pnew = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 4, i32 4)
+  %safepoint_token = tail call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @func, i32 0, i32 0, i32 0, i32 0, i32 addrspace(1)* null)
+  %pnew = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token,  i32 7, i32 7)
   %cmp = icmp eq i32 addrspace(1)* %pnew, null
   ret i1 %cmp
 ; CHECK-LABEL: test_null
@@ -37,10 +37,10 @@ entry:
 ; CHECK: ret i1 true
 }
 
-define i1 @test_undef() {
+define i1 @test_undef() gc "statepoint-example" {
 entry:
-  %safepoint_token = tail call i32 (void ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_isVoidf(void ()* @func, i32 0, i32 0, i32 0, i32 addrspace(1)* undef)
-  %pnew = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token, i32 4, i32 4)
+  %safepoint_token = tail call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @func, i32 0, i32 0, i32 0, i32 0, i32 addrspace(1)* undef)
+  %pnew = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %safepoint_token,  i32 7, i32 7)
   %cmp = icmp eq i32 addrspace(1)* %pnew, null
   ret i1 %cmp
 ; CHECK-LABEL: test_undef
@@ -48,5 +48,5 @@ entry:
 ; CHECK: ret i1 undef
 }
 
-declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(void ()*, i32, i32, ...)
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
 declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32, i32, i32) #3
diff --git a/test/Transforms/InstCombine/store.ll b/test/Transforms/InstCombine/store.ll
index 0bb175923e98..5dfbd7140901 100644
--- a/test/Transforms/InstCombine/store.ll
+++ b/test/Transforms/InstCombine/store.ll
@@ -12,7 +12,7 @@ define void @test1(i32* %P) {
 }
 
 define void @test2(i32* %P) {
-        %X = load i32* %P               ; <i32> [#uses=1]
+        %X = load i32, i32* %P               ; <i32> [#uses=1]
         %Y = add i32 %X, 0              ; <i32> [#uses=1]
         store i32 %Y, i32* %P
         ret void
@@ -36,12 +36,12 @@ Cond2:
 	br label %Cont
 
 Cont:
-	%V = load i32* %A
+	%V = load i32, i32* %A
 	ret i32 %V
 ; CHECK-LABEL: @test3(
 ; CHECK-NOT: alloca
 ; CHECK: Cont:
-; CHECK-NEXT:  %storemerge = phi i32 [ 47, %Cond2 ], [ -987654321, %Cond ]
+; CHECK-NEXT:  %storemerge = phi i32 [ -987654321, %Cond ], [ 47, %Cond2 ]
 ; CHECK-NEXT:  ret i32 %storemerge
 }
 
@@ -56,7 +56,7 @@ Cond:
         br label %Cont
 
 Cont:
-	%V = load i32* %A
+	%V = load i32, i32* %A
 	ret i32 %V
 ; CHECK-LABEL: @test4(
 ; CHECK-NOT: alloca
@@ -92,15 +92,15 @@ entry:
 
 for.cond:                                         ; preds = %for.body, %entry
   %storemerge = phi i32 [ 0, %entry ], [ %inc, %for.body ]
-  %0 = load i32* %gi, align 4, !tbaa !0
+  %0 = load i32, i32* %gi, align 4, !tbaa !0
   %cmp = icmp slt i32 %0, %n
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
   %idxprom = sext i32 %0 to i64
-  %arrayidx = getelementptr inbounds float* %a, i64 %idxprom
+  %arrayidx = getelementptr inbounds float, float* %a, i64 %idxprom
   store float 0.000000e+00, float* %arrayidx, align 4, !tbaa !3
-  %1 = load i32* %gi, align 4, !tbaa !0
+  %1 = load i32, i32* %gi, align 4, !tbaa !0
   %inc = add nsw i32 %1, 1
   store i32 %inc, i32* %gi, align 4, !tbaa !0
   br label %for.cond
diff --git a/test/Transforms/InstCombine/stpcpy-1.ll b/test/Transforms/InstCombine/stpcpy-1.ll
index b918c9e9e890..cc8289937078 100644
--- a/test/Transforms/InstCombine/stpcpy-1.ll
+++ b/test/Transforms/InstCombine/stpcpy-1.ll
@@ -14,31 +14,31 @@ declare i8* @stpcpy(i8*, i8*)
 define i8* @test_simplify1() {
 ; CHECK-LABEL: @test_simplify1(
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
 
   %ret = call i8* @stpcpy(i8* %dst, i8* %src)
 ; CHECK: @llvm.memcpy.p0i8.p0i8.i32
-; CHECK-NEXT: getelementptr inbounds ([32 x i8]* @a, i32 0, i32 5)
+; CHECK-NEXT: getelementptr inbounds ([32 x i8], [32 x i8]* @a, i32 0, i32 5)
   ret i8* %ret
 }
 
 define i8* @test_simplify2() {
 ; CHECK-LABEL: @test_simplify2(
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
 
   %ret = call i8* @stpcpy(i8* %dst, i8* %dst)
 ; CHECK: [[LEN:%[a-z]+]] = call i32 @strlen
-; CHECK-NEXT: getelementptr inbounds [32 x i8]* @a, i32 0, i32 [[LEN]]
+; CHECK-NEXT: getelementptr inbounds [32 x i8], [32 x i8]* @a, i32 0, i32 [[LEN]]
   ret i8* %ret
 }
 
 define i8* @test_no_simplify1() {
 ; CHECK-LABEL: @test_no_simplify1(
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [32 x i8]* @b, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [32 x i8], [32 x i8]* @b, i32 0, i32 0
 
   %ret = call i8* @stpcpy(i8* %dst, i8* %src)
 ; CHECK: call i8* @stpcpy
diff --git a/test/Transforms/InstCombine/stpcpy-2.ll b/test/Transforms/InstCombine/stpcpy-2.ll
index 6a0f7530d5a8..07e13a69e2d2 100644
--- a/test/Transforms/InstCombine/stpcpy-2.ll
+++ b/test/Transforms/InstCombine/stpcpy-2.ll
@@ -13,8 +13,8 @@ declare i16* @stpcpy(i8*, i8*)
 define void @test_no_simplify1() {
 ; CHECK-LABEL: @test_no_simplify1(
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
 
   call i16* @stpcpy(i8* %dst, i8* %src)
 ; CHECK: call i16* @stpcpy
diff --git a/test/Transforms/InstCombine/stpcpy_chk-1.ll b/test/Transforms/InstCombine/stpcpy_chk-1.ll
index 393c5d96d10b..2fcc34b05227 100644
--- a/test/Transforms/InstCombine/stpcpy_chk-1.ll
+++ b/test/Transforms/InstCombine/stpcpy_chk-1.ll
@@ -13,33 +13,33 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 
 define i8* @test_simplify1() {
 ; CHECK-LABEL: @test_simplify1(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [12 x i8], [12 x i8]* @.str, i32 0, i32 0
 
-; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
-; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 11)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
+; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 11)
   %ret = call i8* @__stpcpy_chk(i8* %dst, i8* %src, i32 60)
   ret i8* %ret
 }
 
 define i8* @test_simplify2() {
 ; CHECK-LABEL: @test_simplify2(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [12 x i8], [12 x i8]* @.str, i32 0, i32 0
 
-; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
-; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 11)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
+; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 11)
   %ret = call i8* @__stpcpy_chk(i8* %dst, i8* %src, i32 12)
   ret i8* %ret
 }
 
 define i8* @test_simplify3() {
 ; CHECK-LABEL: @test_simplify3(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [12 x i8], [12 x i8]* @.str, i32 0, i32 0
 
-; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
-; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 11)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
+; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 11)
   %ret = call i8* @__stpcpy_chk(i8* %dst, i8* %src, i32 -1)
   ret i8* %ret
 }
@@ -48,10 +48,10 @@ define i8* @test_simplify3() {
 
 define i8* @test_simplify4() {
 ; CHECK-LABEL: @test_simplify4(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [60 x i8]* @b, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [60 x i8], [60 x i8]* @b, i32 0, i32 0
 
-; CHECK-NEXT: %stpcpy = call i8* @stpcpy(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8]* @b, i32 0, i32 0))
+; CHECK-NEXT: %stpcpy = call i8* @stpcpy(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @b, i32 0, i32 0))
 ; CHECK-NEXT: ret i8* %stpcpy
   %ret = call i8* @__stpcpy_chk(i8* %dst, i8* %src, i32 -1)
   ret i8* %ret
@@ -61,12 +61,12 @@ define i8* @test_simplify4() {
 
 define i8* @test_simplify5() {
 ; CHECK-LABEL: @test_simplify5(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [12 x i8], [12 x i8]* @.str, i32 0, i32 0
 
-; CHECK-NEXT: %len = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i1 false)
-; CHECK-NEXT: %1 = call i8* @__memcpy_chk(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), i32 12, i32 %len)
-; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 11)
+; CHECK-NEXT: %len = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i1 false)
+; CHECK-NEXT: %1 = call i8* @__memcpy_chk(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), i32 12, i32 %len)
+; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 11)
   %len = call i32 @llvm.objectsize.i32.p0i8(i8* %dst, i1 false)
   %ret = call i8* @__stpcpy_chk(i8* %dst, i8* %src, i32 %len)
   ret i8* %ret
@@ -76,10 +76,10 @@ define i8* @test_simplify5() {
 
 define i8* @test_simplify6() {
 ; CHECK-LABEL: @test_simplify6(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
 
-; CHECK-NEXT: %strlen = call i32 @strlen(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0))
-; CHECK-NEXT: %1 = getelementptr inbounds [60 x i8]* @a, i32 0, i32 %strlen
+; CHECK-NEXT: %strlen = call i32 @strlen(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0))
+; CHECK-NEXT: %1 = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 %strlen
 ; CHECK-NEXT: ret i8* %1
   %len = call i32 @llvm.objectsize.i32.p0i8(i8* %dst, i1 false)
   %ret = call i8* @__stpcpy_chk(i8* %dst, i8* %dst, i32 %len)
@@ -90,10 +90,10 @@ define i8* @test_simplify6() {
 
 define i8* @test_no_simplify1() {
 ; CHECK-LABEL: @test_no_simplify1(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [60 x i8]* @b, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [60 x i8], [60 x i8]* @b, i32 0, i32 0
 
-; CHECK-NEXT: %ret = call i8* @__stpcpy_chk(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8]* @b, i32 0, i32 0), i32 8)
+; CHECK-NEXT: %ret = call i8* @__stpcpy_chk(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @b, i32 0, i32 0), i32 8)
 ; CHECK-NEXT: ret i8* %ret
   %ret = call i8* @__stpcpy_chk(i8* %dst, i8* %src, i32 8)
   ret i8* %ret
diff --git a/test/Transforms/InstCombine/stpcpy_chk-2.ll b/test/Transforms/InstCombine/stpcpy_chk-2.ll
index b503da9c191c..b4803f98b249 100644
--- a/test/Transforms/InstCombine/stpcpy_chk-2.ll
+++ b/test/Transforms/InstCombine/stpcpy_chk-2.ll
@@ -10,8 +10,8 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 
 define void @test_no_simplify() {
 ; CHECK-LABEL: @test_no_simplify(
-  %dst = getelementptr inbounds [60 x i16]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [8 x i8]* @.str, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i16], [60 x i16]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [8 x i8], [8 x i8]* @.str, i32 0, i32 0
 
 ; CHECK-NEXT: call i16* @__strcpy_chk
   call i16* @__strcpy_chk(i16* %dst, i8* %src, i32 8)
diff --git a/test/Transforms/InstCombine/strcat-1.ll b/test/Transforms/InstCombine/strcat-1.ll
index 131ad4834837..446a26e94ac4 100644
--- a/test/Transforms/InstCombine/strcat-1.ll
+++ b/test/Transforms/InstCombine/strcat-1.ll
@@ -18,19 +18,19 @@ define i32 @main() {
 ; CHECK: call i32 @puts
 
   %target = alloca [1024 x i8]
-  %arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0
+  %arg1 = getelementptr [1024 x i8], [1024 x i8]* %target, i32 0, i32 0
   store i8 0, i8* %arg1
 
   ; rslt1 = strcat(target, "hello\00")
-  %arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %arg2 = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   %rslt1 = call i8* @strcat(i8* %arg1, i8* %arg2)
 
   ; rslt2 = strcat(rslt1, "\00")
-  %arg3 = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %arg3 = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
   %rslt2 = call i8* @strcat(i8* %rslt1, i8* %arg3)
 
   ; rslt3 = strcat(rslt2, "\00hello\00")
-  %arg4 = getelementptr [7 x i8]* @null_hello, i32 0, i32 0
+  %arg4 = getelementptr [7 x i8], [7 x i8]* @null_hello, i32 0, i32 0
   %rslt3 = call i8* @strcat(i8* %rslt2, i8* %arg4)
 
   call i32 @puts( i8* %rslt3 )
diff --git a/test/Transforms/InstCombine/strcat-2.ll b/test/Transforms/InstCombine/strcat-2.ll
index 48f82670c325..287019770acf 100644
--- a/test/Transforms/InstCombine/strcat-2.ll
+++ b/test/Transforms/InstCombine/strcat-2.ll
@@ -15,8 +15,8 @@ define void @test_simplify1() {
 ; CHECK-NOT: call i8* @strcat
 ; CHECK: ret void
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   call i8* @strcat(i8* %dst, i8* %src)
   ret void
 }
@@ -25,8 +25,8 @@ define void @test_simplify2() {
 ; CHECK-LABEL: @test_simplify2(
 ; CHECK-NEXT: ret void
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [1 x i8]* @empty, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [1 x i8], [1 x i8]* @empty, i32 0, i32 0
   call i8* @strcat(i8* %dst, i8* %src)
   ret void
 }
diff --git a/test/Transforms/InstCombine/strcat-3.ll b/test/Transforms/InstCombine/strcat-3.ll
index e3396df73d37..88cd162d0cd5 100644
--- a/test/Transforms/InstCombine/strcat-3.ll
+++ b/test/Transforms/InstCombine/strcat-3.ll
@@ -15,8 +15,8 @@ define void @test_nosimplify1() {
 ; CHECK: call i16* @strcat
 ; CHECK: ret void
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   call i16* @strcat(i8* %dst, i8* %src)
   ret void
 }
diff --git a/test/Transforms/InstCombine/strchr-1.ll b/test/Transforms/InstCombine/strchr-1.ll
index 66b3e2e51c7a..6c10ebdfcc43 100644
--- a/test/Transforms/InstCombine/strchr-1.ll
+++ b/test/Transforms/InstCombine/strchr-1.ll
@@ -1,20 +1,21 @@
 ; Test that the strchr library call simplifier works correctly.
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
 
 @hello = constant [14 x i8] c"hello world\5Cn\00"
 @null = constant [1 x i8] zeroinitializer
+@newlines = constant [3 x i8] c"\0D\0A\00"
 @chp = global i8* zeroinitializer
 
 declare i8* @strchr(i8*, i32)
 
 define void @test_simplify1() {
-; CHECK: store i8* getelementptr inbounds ([14 x i8]* @hello, i32 0, i32 6)
+; CHECK: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hello, i32 0, i32 6)
 ; CHECK-NOT: call i8* @strchr
 ; CHECK: ret void
 
-  %str = getelementptr [14 x i8]* @hello, i32 0, i32 0
+  %str = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
   %dst = call i8* @strchr(i8* %str, i32 119)
   store i8* %dst, i8** @chp
   ret void
@@ -25,18 +26,18 @@ define void @test_simplify2() {
 ; CHECK-NOT: call i8* @strchr
 ; CHECK: ret void
 
-  %str = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %str = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
   %dst = call i8* @strchr(i8* %str, i32 119)
   store i8* %dst, i8** @chp
   ret void
 }
 
 define void @test_simplify3() {
-; CHECK: store i8* getelementptr inbounds ([14 x i8]* @hello, i32 0, i32 13)
+; CHECK: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hello, i32 0, i32 13)
 ; CHECK-NOT: call i8* @strchr
 ; CHECK: ret void
 
-  %src = getelementptr [14 x i8]* @hello, i32 0, i32 0
+  %src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
   %dst = call i8* @strchr(i8* %src, i32 0)
   store i8* %dst, i8** @chp
   ret void
@@ -47,18 +48,18 @@ define void @test_simplify4(i32 %chr) {
 ; CHECK-NOT: call i8* @strchr
 ; CHECK: ret void
 
-  %src = getelementptr [14 x i8]* @hello, i32 0, i32 0
+  %src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
   %dst = call i8* @strchr(i8* %src, i32 %chr)
   store i8* %dst, i8** @chp
   ret void
 }
 
 define void @test_simplify5() {
-; CHECK: store i8* getelementptr inbounds ([14 x i8]* @hello, i32 0, i32 13)
+; CHECK: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hello, i32 0, i32 13)
 ; CHECK-NOT: call i8* @strchr
 ; CHECK: ret void
 
-  %src = getelementptr [14 x i8]* @hello, i32 0, i32 0
+  %src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
   %dst = call i8* @strchr(i8* %src, i32 65280)
   store i8* %dst, i8** @chp
   ret void
@@ -68,7 +69,7 @@ define void @test_simplify5() {
 define void @test_simplify6(i8* %str) {
 ; CHECK: %strlen = call i32 @strlen(i8* %str)
 ; CHECK-NOT: call i8* @strchr
-; CHECK: %strchr = getelementptr i8* %str, i32 %strlen
+; CHECK: %strchr = getelementptr i8, i8* %str, i32 %strlen
 ; CHECK: store i8* %strchr, i8** @chp, align 4
 ; CHECK: ret void
 
@@ -76,3 +77,19 @@ define void @test_simplify6(i8* %str) {
   store i8* %dst, i8** @chp
   ret void
 }
+
+; Check transformation strchr("\r\n", C) != nullptr -> (C & 9217) != 0
+define i1 @test_simplify7(i32 %C) {
+; CHECK-LABEL: @test_simplify7
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 %C to i16
+; CHECK-NEXT: %memchr.bounds = icmp ult i16 [[TRUNC]], 16
+; CHECK-NEXT: [[SHL:%.*]] = shl i16 1, [[TRUNC]]
+; CHECK-NEXT: [[AND:%.*]] = and i16 [[SHL]], 9217
+; CHECK-NEXT: %memchr.bits = icmp ne i16 [[AND]], 0
+; CHECK-NEXT: %memchr1 = and i1 %memchr.bounds, %memchr.bits
+; CHECK-NEXT: ret i1 %memchr1
+
+  %dst = call i8* @strchr(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @newlines, i64 0, i64 0), i32 %C)
+  %cmp = icmp ne i8* %dst, null
+  ret i1 %cmp
+}
diff --git a/test/Transforms/InstCombine/strchr-2.ll b/test/Transforms/InstCombine/strchr-2.ll
index 35bbd23e6d4d..dd86a16f77bc 100644
--- a/test/Transforms/InstCombine/strchr-2.ll
+++ b/test/Transforms/InstCombine/strchr-2.ll
@@ -14,7 +14,7 @@ define void @test_nosimplify1() {
 ; CHECK: call i8 @strchr
 ; CHECK: ret void
 
-  %str = getelementptr [14 x i8]* @hello, i32 0, i32 0
+  %str = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
   %dst = call i8 @strchr(i8* %str, i32 119)
   store i8 %dst, i8* @chr
   ret void
diff --git a/test/Transforms/InstCombine/strcmp-1.ll b/test/Transforms/InstCombine/strcmp-1.ll
index 9bbd7dbe7da8..9bc1fc693557 100644
--- a/test/Transforms/InstCombine/strcmp-1.ll
+++ b/test/Transforms/InstCombine/strcmp-1.ll
@@ -13,12 +13,12 @@ declare i32 @strcmp(i8*, i8*)
 ; strcmp("", x) -> -*x
 define i32 @test1(i8* %str2) {
 ; CHECK-LABEL: @test1(
-; CHECK: %strcmpload = load i8* %str
+; CHECK: %strcmpload = load i8, i8* %str
 ; CHECK: %1 = zext i8 %strcmpload to i32
 ; CHECK: %2 = sub nsw i32 0, %1
 ; CHECK: ret i32 %2
 
-  %str1 = getelementptr inbounds [1 x i8]* @null, i32 0, i32 0
+  %str1 = getelementptr inbounds [1 x i8], [1 x i8]* @null, i32 0, i32 0
   %temp1 = call i32 @strcmp(i8* %str1, i8* %str2)
   ret i32 %temp1
 
@@ -27,11 +27,11 @@ define i32 @test1(i8* %str2) {
 ; strcmp(x, "") -> *x
 define i32 @test2(i8* %str1) {
 ; CHECK-LABEL: @test2(
-; CHECK: %strcmpload = load i8* %str
+; CHECK: %strcmpload = load i8, i8* %str
 ; CHECK: %1 = zext i8 %strcmpload to i32
 ; CHECK: ret i32 %1
 
-  %str2 = getelementptr inbounds [1 x i8]* @null, i32 0, i32 0
+  %str2 = getelementptr inbounds [1 x i8], [1 x i8]* @null, i32 0, i32 0
   %temp1 = call i32 @strcmp(i8* %str1, i8* %str2)
   ret i32 %temp1
 }
@@ -41,8 +41,8 @@ define i32 @test3() {
 ; CHECK-LABEL: @test3(
 ; CHECK: ret i32 -1
 
-  %str1 = getelementptr inbounds [5 x i8]* @hell, i32 0, i32 0
-  %str2 = getelementptr inbounds [6 x i8]* @hello, i32 0, i32 0
+  %str1 = getelementptr inbounds [5 x i8], [5 x i8]* @hell, i32 0, i32 0
+  %str2 = getelementptr inbounds [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   %temp1 = call i32 @strcmp(i8* %str1, i8* %str2)
   ret i32 %temp1
 }
@@ -51,8 +51,8 @@ define i32 @test4() {
 ; CHECK-LABEL: @test4(
 ; CHECK: ret i32 1
 
-  %str1 = getelementptr inbounds [5 x i8]* @hell, i32 0, i32 0
-  %str2 = getelementptr inbounds [1 x i8]* @null, i32 0, i32 0
+  %str1 = getelementptr inbounds [5 x i8], [5 x i8]* @hell, i32 0, i32 0
+  %str2 = getelementptr inbounds [1 x i8], [1 x i8]* @null, i32 0, i32 0
   %temp1 = call i32 @strcmp(i8* %str1, i8* %str2)
   ret i32 %temp1
 }
@@ -61,12 +61,12 @@ define i32 @test4() {
 ; (This transform is rather difficult to trigger in a useful manner)
 define i32 @test5(i1 %b) {
 ; CHECK-LABEL: @test5(
-; CHECK: %memcmp = call i32 @memcmp(i8* getelementptr inbounds ([6 x i8]* @hello, i32 0, i32 0), i8* %str2, i32 5)
+; CHECK: %memcmp = call i32 @memcmp(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @hello, i32 0, i32 0), i8* %str2, i32 5)
 ; CHECK: ret i32 %memcmp
 
-  %str1 = getelementptr inbounds [6 x i8]* @hello, i32 0, i32 0
-  %temp1 = getelementptr inbounds [5 x i8]* @hell, i32 0, i32 0
-  %temp2 = getelementptr inbounds [5 x i8]* @bell, i32 0, i32 0
+  %str1 = getelementptr inbounds [6 x i8], [6 x i8]* @hello, i32 0, i32 0
+  %temp1 = getelementptr inbounds [5 x i8], [5 x i8]* @hell, i32 0, i32 0
+  %temp2 = getelementptr inbounds [5 x i8], [5 x i8]* @bell, i32 0, i32 0
   %str2 = select i1 %b, i8* %temp1, i8* %temp2
   %temp3 = call i32 @strcmp(i8* %str1, i8* %str2)
   ret i32 %temp3
diff --git a/test/Transforms/InstCombine/strcmp-2.ll b/test/Transforms/InstCombine/strcmp-2.ll
index f0ef51652270..a537b10e0deb 100644
--- a/test/Transforms/InstCombine/strcmp-2.ll
+++ b/test/Transforms/InstCombine/strcmp-2.ll
@@ -13,8 +13,8 @@ define i16 @test_nosimplify() {
 ; CHECK: call i16 @strcmp
 ; CHECK: ret i16 %temp1
 
-  %str1 = getelementptr inbounds [5 x i8]* @hell, i32 0, i32 0
-  %str2 = getelementptr inbounds [6 x i8]* @hello, i32 0, i32 0
+  %str1 = getelementptr inbounds [5 x i8], [5 x i8]* @hell, i32 0, i32 0
+  %str2 = getelementptr inbounds [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   %temp1 = call i16 @strcmp(i8* %str1, i8* %str2)
   ret i16 %temp1
 }
diff --git a/test/Transforms/InstCombine/strcpy-1.ll b/test/Transforms/InstCombine/strcpy-1.ll
index 7c253f6f9fca..24c70c18fc05 100644
--- a/test/Transforms/InstCombine/strcpy-1.ll
+++ b/test/Transforms/InstCombine/strcpy-1.ll
@@ -15,8 +15,8 @@ declare i8* @strcpy(i8*, i8*)
 define void @test_simplify1() {
 ; CHECK-LABEL: @test_simplify1(
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
 
   call i8* @strcpy(i8* %dst, i8* %src)
 ; CHECK: @llvm.memcpy.p0i8.p0i8.i32
@@ -26,18 +26,18 @@ define void @test_simplify1() {
 define i8* @test_simplify2() {
 ; CHECK-LABEL: @test_simplify2(
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
 
   %ret = call i8* @strcpy(i8* %dst, i8* %dst)
-; CHECK: ret i8* getelementptr inbounds ([32 x i8]* @a, i32 0, i32 0)
+; CHECK: ret i8* getelementptr inbounds ([32 x i8], [32 x i8]* @a, i32 0, i32 0)
   ret i8* %ret
 }
 
 define i8* @test_no_simplify1() {
 ; CHECK-LABEL: @test_no_simplify1(
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [32 x i8]* @b, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [32 x i8], [32 x i8]* @b, i32 0, i32 0
 
   %ret = call i8* @strcpy(i8* %dst, i8* %src)
 ; CHECK: call i8* @strcpy
diff --git a/test/Transforms/InstCombine/strcpy-2.ll b/test/Transforms/InstCombine/strcpy-2.ll
index bad392d7c648..cfc8a410b7ee 100644
--- a/test/Transforms/InstCombine/strcpy-2.ll
+++ b/test/Transforms/InstCombine/strcpy-2.ll
@@ -13,8 +13,8 @@ declare i16* @strcpy(i8*, i8*)
 define void @test_no_simplify1() {
 ; CHECK-LABEL: @test_no_simplify1(
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
 
   call i16* @strcpy(i8* %dst, i8* %src)
 ; CHECK: call i16* @strcpy
diff --git a/test/Transforms/InstCombine/strcpy_chk-1.ll b/test/Transforms/InstCombine/strcpy_chk-1.ll
index e3f163fd087d..7a21a49c993c 100644
--- a/test/Transforms/InstCombine/strcpy_chk-1.ll
+++ b/test/Transforms/InstCombine/strcpy_chk-1.ll
@@ -13,33 +13,33 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 
 define i8* @test_simplify1() {
 ; CHECK-LABEL: @test_simplify1(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [12 x i8], [12 x i8]* @.str, i32 0, i32 0
 
-; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
-; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
+; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0)
   %ret = call i8* @__strcpy_chk(i8* %dst, i8* %src, i32 60)
   ret i8* %ret
 }
 
 define i8* @test_simplify2() {
 ; CHECK-LABEL: @test_simplify2(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [12 x i8], [12 x i8]* @.str, i32 0, i32 0
 
-; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
-; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
+; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0)
   %ret = call i8* @__strcpy_chk(i8* %dst, i8* %src, i32 12)
   ret i8* %ret
 }
 
 define i8* @test_simplify3() {
 ; CHECK-LABEL: @test_simplify3(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [12 x i8], [12 x i8]* @.str, i32 0, i32 0
 
-; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
-; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
+; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0)
   %ret = call i8* @__strcpy_chk(i8* %dst, i8* %src, i32 -1)
   ret i8* %ret
 }
@@ -48,10 +48,10 @@ define i8* @test_simplify3() {
 
 define i8* @test_simplify4() {
 ; CHECK-LABEL: @test_simplify4(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [60 x i8]* @b, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [60 x i8], [60 x i8]* @b, i32 0, i32 0
 
-; CHECK-NEXT: %strcpy = call i8* @strcpy(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8]* @b, i32 0, i32 0))
+; CHECK-NEXT: %strcpy = call i8* @strcpy(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @b, i32 0, i32 0))
 ; CHECK-NEXT: ret i8* %strcpy
   %ret = call i8* @__strcpy_chk(i8* %dst, i8* %src, i32 -1)
   ret i8* %ret
@@ -61,11 +61,11 @@ define i8* @test_simplify4() {
 
 define i8* @test_simplify5() {
 ; CHECK-LABEL: @test_simplify5(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [12 x i8], [12 x i8]* @.str, i32 0, i32 0
 
-; CHECK-NEXT: %len = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i1 false)
-; CHECK-NEXT: %1 = call i8* @__memcpy_chk(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), i32 12, i32 %len)
+; CHECK-NEXT: %len = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i1 false)
+; CHECK-NEXT: %1 = call i8* @__memcpy_chk(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), i32 12, i32 %len)
 ; CHECK-NEXT: ret i8* %1
   %len = call i32 @llvm.objectsize.i32.p0i8(i8* %dst, i1 false)
   %ret = call i8* @__strcpy_chk(i8* %dst, i8* %src, i32 %len)
@@ -76,10 +76,10 @@ define i8* @test_simplify5() {
 
 define i8* @test_simplify6() {
 ; CHECK-LABEL: @test_simplify6(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
 
-; CHECK-NEXT: %len = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i1 false)
-; CHECK-NEXT: %ret = call i8* @__strcpy_chk(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i32 %len)
+; CHECK-NEXT: %len = call i32 @llvm.objectsize.i32.p0i8(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i1 false)
+; CHECK-NEXT: %ret = call i8* @__strcpy_chk(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i32 %len)
 ; CHECK-NEXT: ret i8* %ret
   %len = call i32 @llvm.objectsize.i32.p0i8(i8* %dst, i1 false)
   %ret = call i8* @__strcpy_chk(i8* %dst, i8* %dst, i32 %len)
@@ -90,10 +90,10 @@ define i8* @test_simplify6() {
 
 define i8* @test_no_simplify1() {
 ; CHECK-LABEL: @test_no_simplify1(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [60 x i8]* @b, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [60 x i8], [60 x i8]* @b, i32 0, i32 0
 
-; CHECK-NEXT: %ret = call i8* @__strcpy_chk(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8]* @b, i32 0, i32 0), i32 8)
+; CHECK-NEXT: %ret = call i8* @__strcpy_chk(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @b, i32 0, i32 0), i32 8)
 ; CHECK-NEXT: ret i8* %ret
   %ret = call i8* @__strcpy_chk(i8* %dst, i8* %src, i32 8)
   ret i8* %ret
diff --git a/test/Transforms/InstCombine/strcpy_chk-2.ll b/test/Transforms/InstCombine/strcpy_chk-2.ll
index 1eff5a822e78..c2204a830bae 100644
--- a/test/Transforms/InstCombine/strcpy_chk-2.ll
+++ b/test/Transforms/InstCombine/strcpy_chk-2.ll
@@ -10,8 +10,8 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 
 define void @test_no_simplify() {
 ; CHECK-LABEL: @test_no_simplify(
-  %dst = getelementptr inbounds [60 x i16]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [8 x i8]* @.str, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i16], [60 x i16]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [8 x i8], [8 x i8]* @.str, i32 0, i32 0
 
 ; CHECK-NEXT: call i16* @__strcpy_chk
   call i16* @__strcpy_chk(i16* %dst, i8* %src, i32 8)
diff --git a/test/Transforms/InstCombine/strcpy_chk-64.ll b/test/Transforms/InstCombine/strcpy_chk-64.ll
index 31447d9569e1..8a2cdc2f2bb5 100644
--- a/test/Transforms/InstCombine/strcpy_chk-64.ll
+++ b/test/Transforms/InstCombine/strcpy_chk-64.ll
@@ -7,7 +7,7 @@ define void @func(i8* %i) nounwind ssp {
 ; CHECK: @__strcpy_chk(i8* %arraydecay, i8* %i, i64 32)
 entry:
   %s = alloca [32 x i8], align 16
-  %arraydecay = getelementptr inbounds [32 x i8]* %s, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [32 x i8], [32 x i8]* %s, i32 0, i32 0
   %call = call i8* @__strcpy_chk(i8* %arraydecay, i8* %i, i64 32)
   call void @func2(i8* %arraydecay)
   ret void
diff --git a/test/Transforms/InstCombine/strcspn-1.ll b/test/Transforms/InstCombine/strcspn-1.ll
index b3b52b5025a5..8d441a9eecd0 100644
--- a/test/Transforms/InstCombine/strcspn-1.ll
+++ b/test/Transforms/InstCombine/strcspn-1.ll
@@ -14,7 +14,7 @@ declare i64 @strcspn(i8*, i8*)
 
 define i64 @test_simplify1(i8* %str) {
 ; CHECK-LABEL: @test_simplify1(
-  %pat = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %pat = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
 
   %ret = call i64 @strcspn(i8* %str, i8* %pat)
 ; CHECK-NEXT: [[VAR:%[a-z]+]] = call i64 @strlen(i8* %str)
@@ -26,7 +26,7 @@ define i64 @test_simplify1(i8* %str) {
 
 define i64 @test_simplify2(i8* %pat) {
 ; CHECK-LABEL: @test_simplify2(
-  %str = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %str = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
 
   %ret = call i64 @strcspn(i8* %str, i8* %pat)
   ret i64 %ret
@@ -37,8 +37,8 @@ define i64 @test_simplify2(i8* %pat) {
 
 define i64 @test_simplify3() {
 ; CHECK-LABEL: @test_simplify3(
-  %str = getelementptr [6 x i8]* @abcba, i32 0, i32 0
-  %pat = getelementptr [4 x i8]* @abc, i32 0, i32 0
+  %str = getelementptr [6 x i8], [6 x i8]* @abcba, i32 0, i32 0
+  %pat = getelementptr [4 x i8], [4 x i8]* @abc, i32 0, i32 0
 
   %ret = call i64 @strcspn(i8* %str, i8* %pat)
   ret i64 %ret
diff --git a/test/Transforms/InstCombine/strcspn-2.ll b/test/Transforms/InstCombine/strcspn-2.ll
index ecfa27d3b6ba..749860afcd4e 100644
--- a/test/Transforms/InstCombine/strcspn-2.ll
+++ b/test/Transforms/InstCombine/strcspn-2.ll
@@ -12,7 +12,7 @@ declare double @strcspn(i8*, i8*)
 
 define double @test_no_simplify1(i8* %pat) {
 ; CHECK-LABEL: @test_no_simplify1(
-  %str = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %str = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
 
   %ret = call double @strcspn(i8* %str, i8* %pat)
 ; CHECK-NEXT: call double @strcspn
diff --git a/test/Transforms/InstCombine/strlen-1.ll b/test/Transforms/InstCombine/strlen-1.ll
index 4a3caf28a0fe..fe453699a60e 100644
--- a/test/Transforms/InstCombine/strlen-1.ll
+++ b/test/Transforms/InstCombine/strlen-1.ll
@@ -17,7 +17,7 @@ declare i32 @strlen(i8*)
 
 define i32 @test_simplify1() {
 ; CHECK-LABEL: @test_simplify1(
-  %hello_p = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %hello_p = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   %hello_l = call i32 @strlen(i8* %hello_p)
   ret i32 %hello_l
 ; CHECK-NEXT: ret i32 5
@@ -25,7 +25,7 @@ define i32 @test_simplify1() {
 
 define i32 @test_simplify2() {
 ; CHECK-LABEL: @test_simplify2(
-  %null_p = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %null_p = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
   %null_l = call i32 @strlen(i8* %null_p)
   ret i32 %null_l
 ; CHECK-NEXT: ret i32 0
@@ -33,7 +33,7 @@ define i32 @test_simplify2() {
 
 define i32 @test_simplify3() {
 ; CHECK-LABEL: @test_simplify3(
-  %null_hello_p = getelementptr [7 x i8]* @null_hello, i32 0, i32 0
+  %null_hello_p = getelementptr [7 x i8], [7 x i8]* @null_hello, i32 0, i32 0
   %null_hello_l = call i32 @strlen(i8* %null_hello_p)
   ret i32 %null_hello_l
 ; CHECK-NEXT: ret i32 0
@@ -50,7 +50,7 @@ define i32 @test_simplify4() {
 
 define i1 @test_simplify5() {
 ; CHECK-LABEL: @test_simplify5(
-  %hello_p = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %hello_p = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   %hello_l = call i32 @strlen(i8* %hello_p)
   %eq_hello = icmp eq i32 %hello_l, 0
   ret i1 %eq_hello
@@ -59,7 +59,7 @@ define i1 @test_simplify5() {
 
 define i1 @test_simplify6() {
 ; CHECK-LABEL: @test_simplify6(
-  %null_p = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %null_p = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
   %null_l = call i32 @strlen(i8* %null_p)
   %eq_null = icmp eq i32 %null_l, 0
   ret i1 %eq_null
@@ -70,7 +70,7 @@ define i1 @test_simplify6() {
 
 define i1 @test_simplify7() {
 ; CHECK-LABEL: @test_simplify7(
-  %hello_p = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %hello_p = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   %hello_l = call i32 @strlen(i8* %hello_p)
   %ne_hello = icmp ne i32 %hello_l, 0
   ret i1 %ne_hello
@@ -79,7 +79,7 @@ define i1 @test_simplify7() {
 
 define i1 @test_simplify8() {
 ; CHECK-LABEL: @test_simplify8(
-  %null_p = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %null_p = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
   %null_l = call i32 @strlen(i8* %null_p)
   %ne_null = icmp ne i32 %null_l, 0
   ret i1 %ne_null
@@ -88,8 +88,8 @@ define i1 @test_simplify8() {
 
 define i32 @test_simplify9(i1 %x) {
 ; CHECK-LABEL: @test_simplify9
-  %hello = getelementptr [6 x i8]* @hello, i32 0, i32 0
-  %longer = getelementptr [7 x i8]* @longer, i32 0, i32 0
+  %hello = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
+  %longer = getelementptr [7 x i8], [7 x i8]* @longer, i32 0, i32 0
   %s = select i1 %x, i8* %hello, i8* %longer
   %l = call i32 @strlen(i8* %s)
 ; CHECK-NEXT: select i1 %x, i32 5, i32 6
@@ -101,7 +101,7 @@ define i32 @test_simplify9(i1 %x) {
 
 define i32 @test_no_simplify1() {
 ; CHECK-LABEL: @test_no_simplify1(
-  %a_p = getelementptr [32 x i8]* @a, i32 0, i32 0
+  %a_p = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
   %a_l = call i32 @strlen(i8* %a_p)
 ; CHECK-NEXT: %a_l = call i32 @strlen
   ret i32 %a_l
diff --git a/test/Transforms/InstCombine/strlen-2.ll b/test/Transforms/InstCombine/strlen-2.ll
index 6652a310ba6a..df5eee0caef7 100644
--- a/test/Transforms/InstCombine/strlen-2.ll
+++ b/test/Transforms/InstCombine/strlen-2.ll
@@ -10,7 +10,7 @@ declare i32 @strlen(i8*, i32)
 
 define i32 @test_no_simplify1() {
 ; CHECK-LABEL: @test_no_simplify1(
-  %hello_p = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %hello_p = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   %hello_l = call i32 @strlen(i8* %hello_p, i32 187)
 ; CHECK-NEXT: %hello_l = call i32 @strlen
   ret i32 %hello_l
diff --git a/test/Transforms/InstCombine/strncat-1.ll b/test/Transforms/InstCombine/strncat-1.ll
index 8eae3dae2e23..4b8da81f6fb6 100644
--- a/test/Transforms/InstCombine/strncat-1.ll
+++ b/test/Transforms/InstCombine/strncat-1.ll
@@ -17,19 +17,19 @@ define i32 @main() {
 ; CHECK: call i32 @puts
 
   %target = alloca [1024 x i8]
-  %arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0
+  %arg1 = getelementptr [1024 x i8], [1024 x i8]* %target, i32 0, i32 0
   store i8 0, i8* %arg1
 
   ; rslt1 = strncat(target, "hello\00")
-  %arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %arg2 = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   %rslt1 = call i8* @strncat(i8* %arg1, i8* %arg2, i32 6)
 
   ; rslt2 = strncat(rslt1, "\00")
-  %arg3 = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %arg3 = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
   %rslt2 = call i8* @strncat(i8* %rslt1, i8* %arg3, i32 42)
 
   ; rslt3 = strncat(rslt2, "\00hello\00")
-  %arg4 = getelementptr [7 x i8]* @null_hello, i32 0, i32 0
+  %arg4 = getelementptr [7 x i8], [7 x i8]* @null_hello, i32 0, i32 0
   %rslt3 = call i8* @strncat(i8* %rslt2, i8* %arg4, i32 42)
 
   call i32 @puts(i8* %rslt3)
diff --git a/test/Transforms/InstCombine/strncat-2.ll b/test/Transforms/InstCombine/strncat-2.ll
index b09fa1260a03..3533e1eace70 100644
--- a/test/Transforms/InstCombine/strncat-2.ll
+++ b/test/Transforms/InstCombine/strncat-2.ll
@@ -15,8 +15,8 @@ define void @test_simplify1() {
 ; CHECK-NOT: call i8* @strncat
 ; CHECK: ret void
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   call i8* @strncat(i8* %dst, i8* %src, i32 13)
   ret void
 }
@@ -25,8 +25,8 @@ define void @test_simplify2() {
 ; CHECK-LABEL: @test_simplify2(
 ; CHECK-NEXT: ret void
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [1 x i8]* @empty, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [1 x i8], [1 x i8]* @empty, i32 0, i32 0
   call i8* @strncat(i8* %dst, i8* %src, i32 13)
   ret void
 }
@@ -35,8 +35,8 @@ define void @test_simplify3() {
 ; CHECK-LABEL: @test_simplify3(
 ; CHECK-NEXT: ret void
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   call i8* @strncat(i8* %dst, i8* %src, i32 0)
   ret void
 }
@@ -46,8 +46,8 @@ define void @test_nosimplify1() {
 ; CHECK: call i8* @strncat
 ; CHECK: ret void
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   call i8* @strncat(i8* %dst, i8* %src, i32 1)
   ret void
 }
diff --git a/test/Transforms/InstCombine/strncat-3.ll b/test/Transforms/InstCombine/strncat-3.ll
index 1b25b4aca1ae..0f6964df9154 100644
--- a/test/Transforms/InstCombine/strncat-3.ll
+++ b/test/Transforms/InstCombine/strncat-3.ll
@@ -15,8 +15,8 @@ define void @test_nosimplify1() {
 ; CHECK: call i16* @strncat
 ; CHECK: ret void
 
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   call i16* @strncat(i8* %dst, i8* %src, i32 13)
   ret void
 }
diff --git a/test/Transforms/InstCombine/strncmp-1.ll b/test/Transforms/InstCombine/strncmp-1.ll
index 49b095554c2c..a1121821fdf5 100644
--- a/test/Transforms/InstCombine/strncmp-1.ll
+++ b/test/Transforms/InstCombine/strncmp-1.ll
@@ -13,12 +13,12 @@ declare i32 @strncmp(i8*, i8*, i32)
 ; strncmp("", x, n) -> -*x
 define i32 @test1(i8* %str2) {
 ; CHECK-LABEL: @test1(
-; CHECK: %strcmpload = load i8* %str
+; CHECK: %strcmpload = load i8, i8* %str
 ; CHECK: %1 = zext i8 %strcmpload to i32
 ; CHECK: %2 = sub nsw i32 0, %1
 ; CHECK: ret i32 %2
 
-  %str1 = getelementptr inbounds [1 x i8]* @null, i32 0, i32 0
+  %str1 = getelementptr inbounds [1 x i8], [1 x i8]* @null, i32 0, i32 0
   %temp1 = call i32 @strncmp(i8* %str1, i8* %str2, i32 10)
   ret i32 %temp1
 }
@@ -26,11 +26,11 @@ define i32 @test1(i8* %str2) {
 ; strncmp(x, "", n) -> *x
 define i32 @test2(i8* %str1) {
 ; CHECK-LABEL: @test2(
-; CHECK: %strcmpload = load i8* %str1
+; CHECK: %strcmpload = load i8, i8* %str1
 ; CHECK: %1 = zext i8 %strcmpload to i32
 ; CHECK: ret i32 %1
 
-  %str2 = getelementptr inbounds [1 x i8]* @null, i32 0, i32 0
+  %str2 = getelementptr inbounds [1 x i8], [1 x i8]* @null, i32 0, i32 0
   %temp1 = call i32 @strncmp(i8* %str1, i8* %str2, i32 10)
   ret i32 %temp1
 }
@@ -40,8 +40,8 @@ define i32 @test3() {
 ; CHECK-LABEL: @test3(
 ; CHECK: ret i32 -1
 
-  %str1 = getelementptr inbounds [5 x i8]* @hell, i32 0, i32 0
-  %str2 = getelementptr inbounds [6 x i8]* @hello, i32 0, i32 0
+  %str1 = getelementptr inbounds [5 x i8], [5 x i8]* @hell, i32 0, i32 0
+  %str2 = getelementptr inbounds [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   %temp1 = call i32 @strncmp(i8* %str1, i8* %str2, i32 10)
   ret i32 %temp1
 }
@@ -50,8 +50,8 @@ define i32 @test4() {
 ; CHECK-LABEL: @test4(
 ; CHECK: ret i32 1
 
-  %str1 = getelementptr inbounds [5 x i8]* @hell, i32 0, i32 0
-  %str2 = getelementptr inbounds [1 x i8]* @null, i32 0, i32 0
+  %str1 = getelementptr inbounds [5 x i8], [5 x i8]* @hell, i32 0, i32 0
+  %str2 = getelementptr inbounds [1 x i8], [1 x i8]* @null, i32 0, i32 0
   %temp1 = call i32 @strncmp(i8* %str1, i8* %str2, i32 10)
   ret i32 %temp1
 }
@@ -60,8 +60,8 @@ define i32 @test5() {
 ; CHECK-LABEL: @test5(
 ; CHECK: ret i32 0
 
-  %str1 = getelementptr inbounds [5 x i8]* @hell, i32 0, i32 0
-  %str2 = getelementptr inbounds [6 x i8]* @hello, i32 0, i32 0
+  %str1 = getelementptr inbounds [5 x i8], [5 x i8]* @hell, i32 0, i32 0
+  %str2 = getelementptr inbounds [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   %temp1 = call i32 @strncmp(i8* %str1, i8* %str2, i32 4)
   ret i32 %temp1
 }
@@ -69,9 +69,9 @@ define i32 @test5() {
 ; strncmp(x,y,1) -> memcmp(x,y,1)
 define i32 @test6(i8* %str1, i8* %str2) {
 ; CHECK-LABEL: @test6(
-; CHECK: [[LOAD1:%[a-z]+]] = load i8* %str1, align 1
+; CHECK: [[LOAD1:%[a-z]+]] = load i8, i8* %str1, align 1
 ; CHECK: [[ZEXT1:%[a-z]+]] = zext i8 [[LOAD1]] to i32
-; CHECK: [[LOAD2:%[a-z]+]] = load i8* %str2, align 1
+; CHECK: [[LOAD2:%[a-z]+]] = load i8, i8* %str2, align 1
 ; CHECK: [[ZEXT2:%[a-z]+]] = zext i8 [[LOAD2]] to i32
 ; CHECK: [[RET:%[a-z]+]] = sub nsw i32 [[ZEXT1]], [[ZEXT2]]
 ; CHECK: ret i32 [[RET]]
diff --git a/test/Transforms/InstCombine/strncmp-2.ll b/test/Transforms/InstCombine/strncmp-2.ll
index 16ad8a4f62a7..9e19781e04c4 100644
--- a/test/Transforms/InstCombine/strncmp-2.ll
+++ b/test/Transforms/InstCombine/strncmp-2.ll
@@ -13,8 +13,8 @@ define i16 @test_nosimplify() {
 ; CHECK: call i16 @strncmp
 ; CHECK: ret i16 %temp1
 
-  %str1 = getelementptr inbounds [5 x i8]* @hell, i32 0, i32 0
-  %str2 = getelementptr inbounds [6 x i8]* @hello, i32 0, i32 0
+  %str1 = getelementptr inbounds [5 x i8], [5 x i8]* @hell, i32 0, i32 0
+  %str2 = getelementptr inbounds [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   %temp1 = call i16 @strncmp(i8* %str1, i8* %str2, i32 10)
   ret i16 %temp1
 }
diff --git a/test/Transforms/InstCombine/strncpy-1.ll b/test/Transforms/InstCombine/strncpy-1.ll
index c70197f12e28..28cb26b17047 100644
--- a/test/Transforms/InstCombine/strncpy-1.ll
+++ b/test/Transforms/InstCombine/strncpy-1.ll
@@ -20,16 +20,16 @@ define i32 @test_simplify1() {
 ; CHECK-NOT: call i8* @strncpy
 ; CHECK: call i32 @puts
   %target = alloca [1024 x i8]
-  %arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0
+  %arg1 = getelementptr [1024 x i8], [1024 x i8]* %target, i32 0, i32 0
   store i8 0, i8* %arg1
 
-  %arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %arg2 = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
   %rslt1 = call i8* @strncpy(i8* %arg1, i8* %arg2, i32 6)
 
-  %arg3 = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %arg3 = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
   %rslt2 = call i8* @strncpy(i8* %rslt1, i8* %arg3, i32 42)
 
-  %arg4 = getelementptr [7 x i8]* @null_hello, i32 0, i32 0
+  %arg4 = getelementptr [7 x i8], [7 x i8]* @null_hello, i32 0, i32 0
   %rslt3 = call i8* @strncpy(i8* %rslt2, i8* %arg4, i32 42)
 
   call i32 @puts( i8* %rslt3 )
@@ -40,8 +40,8 @@ define i32 @test_simplify1() {
 
 define void @test_simplify2() {
 ; CHECK-LABEL: @test_simplify2(
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
 
   call i8* @strncpy(i8* %dst, i8* %src, i32 32)
 ; CHECK: call void @llvm.memset.p0i8.i32
@@ -52,20 +52,20 @@ define void @test_simplify2() {
 
 define i8* @test_simplify3() {
 ; CHECK-LABEL: @test_simplify3(
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
 
   %ret = call i8* @strncpy(i8* %dst, i8* %src, i32 0)
   ret i8* %ret
-; CHECK: ret i8* getelementptr inbounds ([32 x i8]* @a, i32 0, i32 0)
+; CHECK: ret i8* getelementptr inbounds ([32 x i8], [32 x i8]* @a, i32 0, i32 0)
 }
 
 ; Check  strncpy(x, s, c) -> memcpy(x, s, c, 1) [s and c are constant].
 
 define void @test_simplify4() {
 ; CHECK-LABEL: @test_simplify4(
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
 
   call i8* @strncpy(i8* %dst, i8* %src, i32 6)
 ; CHECK: call void @llvm.memcpy.p0i8.p0i8.i32
@@ -76,8 +76,8 @@ define void @test_simplify4() {
 
 define void @test_no_simplify1() {
 ; CHECK-LABEL: @test_no_simplify1(
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [32 x i8]* @b, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [32 x i8], [32 x i8]* @b, i32 0, i32 0
 
   call i8* @strncpy(i8* %dst, i8* %src, i32 32)
 ; CHECK: call i8* @strncpy
@@ -86,8 +86,8 @@ define void @test_no_simplify1() {
 
 define void @test_no_simplify2() {
 ; CHECK-LABEL: @test_no_simplify2(
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
 
   call i8* @strncpy(i8* %dst, i8* %src, i32 8)
 ; CHECK: call i8* @strncpy
diff --git a/test/Transforms/InstCombine/strncpy-2.ll b/test/Transforms/InstCombine/strncpy-2.ll
index acc2878648fc..5c45f9f24aee 100644
--- a/test/Transforms/InstCombine/strncpy-2.ll
+++ b/test/Transforms/InstCombine/strncpy-2.ll
@@ -13,8 +13,8 @@ declare i16* @strncpy(i8*, i8*, i32)
 
 define void @test_no_simplify1() {
 ; CHECK-LABEL: @test_no_simplify1(
-  %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
-  %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %dst = getelementptr [32 x i8], [32 x i8]* @a, i32 0, i32 0
+  %src = getelementptr [6 x i8], [6 x i8]* @hello, i32 0, i32 0
 
   call i16* @strncpy(i8* %dst, i8* %src, i32 6)
 ; CHECK: call i16* @strncpy
diff --git a/test/Transforms/InstCombine/strncpy_chk-1.ll b/test/Transforms/InstCombine/strncpy_chk-1.ll
index 9242a8acdbbe..03690b9b1e01 100644
--- a/test/Transforms/InstCombine/strncpy_chk-1.ll
+++ b/test/Transforms/InstCombine/strncpy_chk-1.ll
@@ -13,32 +13,32 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 
 define i8* @test_simplify1() {
 ; CHECK-LABEL: @test_simplify1(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [12 x i8], [12 x i8]* @.str, i32 0, i32 0
 
-; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
-; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
+; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0)
   %ret = call i8* @__strncpy_chk(i8* %dst, i8* %src, i32 12, i32 60)
   ret i8* %ret
 }
 
 define i8* @test_simplify2() {
 ; CHECK-LABEL: @test_simplify2(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [12 x i8], [12 x i8]* @.str, i32 0, i32 0
 
-; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
-; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), i32 12, i32 1, i1 false)
+; CHECK-NEXT: ret i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0)
   %ret = call i8* @__strncpy_chk(i8* %dst, i8* %src, i32 12, i32 12)
   ret i8* %ret
 }
 
 define i8* @test_simplify3() {
 ; CHECK-LABEL: @test_simplify3(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [60 x i8]* @b, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [60 x i8], [60 x i8]* @b, i32 0, i32 0
 
-; CHECK-NEXT: %strncpy = call i8* @strncpy(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8]* @b, i32 0, i32 0), i32 12)
+; CHECK-NEXT: %strncpy = call i8* @strncpy(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @b, i32 0, i32 0), i32 12)
 ; CHECK-NEXT: ret i8* %strncpy
   %ret = call i8* @__strncpy_chk(i8* %dst, i8* %src, i32 12, i32 60)
   ret i8* %ret
@@ -48,10 +48,10 @@ define i8* @test_simplify3() {
 
 define i8* @test_no_simplify1() {
 ; CHECK-LABEL: @test_no_simplify1(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [12 x i8], [12 x i8]* @.str, i32 0, i32 0
 
-; CHECK-NEXT: %ret = call i8* @__strncpy_chk(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), i32 8, i32 4)
+; CHECK-NEXT: %ret = call i8* @__strncpy_chk(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), i32 8, i32 4)
 ; CHECK-NEXT: ret i8* %ret
   %ret = call i8* @__strncpy_chk(i8* %dst, i8* %src, i32 8, i32 4)
   ret i8* %ret
@@ -59,10 +59,10 @@ define i8* @test_no_simplify1() {
 
 define i8* @test_no_simplify2() {
 ; CHECK-LABEL: @test_no_simplify2(
-  %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [60 x i8]* @b, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [60 x i8], [60 x i8]* @b, i32 0, i32 0
 
-; CHECK-NEXT: %ret = call i8* @__strncpy_chk(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8]* @b, i32 0, i32 0), i32 8, i32 0)
+; CHECK-NEXT: %ret = call i8* @__strncpy_chk(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @b, i32 0, i32 0), i32 8, i32 0)
 ; CHECK-NEXT: ret i8* %ret
   %ret = call i8* @__strncpy_chk(i8* %dst, i8* %src, i32 8, i32 0)
   ret i8* %ret
diff --git a/test/Transforms/InstCombine/strncpy_chk-2.ll b/test/Transforms/InstCombine/strncpy_chk-2.ll
index 829a4798f09a..89ecd46c04a9 100644
--- a/test/Transforms/InstCombine/strncpy_chk-2.ll
+++ b/test/Transforms/InstCombine/strncpy_chk-2.ll
@@ -10,8 +10,8 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 
 define void @test_no_simplify() {
 ; CHECK-LABEL: @test_no_simplify(
-  %dst = getelementptr inbounds [60 x i16]* @a, i32 0, i32 0
-  %src = getelementptr inbounds [60 x i16]* @b, i32 0, i32 0
+  %dst = getelementptr inbounds [60 x i16], [60 x i16]* @a, i32 0, i32 0
+  %src = getelementptr inbounds [60 x i16], [60 x i16]* @b, i32 0, i32 0
 
 ; CHECK-NEXT: call i16* @__strncpy_chk
   call i16* @__strncpy_chk(i16* %dst, i16* %src, i32 60, i32 60)
diff --git a/test/Transforms/InstCombine/strpbrk-1.ll b/test/Transforms/InstCombine/strpbrk-1.ll
index 58b2d9e88d2c..a61100deb875 100644
--- a/test/Transforms/InstCombine/strpbrk-1.ll
+++ b/test/Transforms/InstCombine/strpbrk-1.ll
@@ -14,7 +14,7 @@ declare i8* @strpbrk(i8*, i8*)
 
 define i8* @test_simplify1(i8* %str) {
 ; CHECK-LABEL: @test_simplify1(
-  %pat = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %pat = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
 
   %ret = call i8* @strpbrk(i8* %str, i8* %pat)
   ret i8* %ret
@@ -25,7 +25,7 @@ define i8* @test_simplify1(i8* %str) {
 
 define i8* @test_simplify2(i8* %pat) {
 ; CHECK-LABEL: @test_simplify2(
-  %str = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %str = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
 
   %ret = call i8* @strpbrk(i8* %str, i8* %pat)
   ret i8* %ret
@@ -36,19 +36,19 @@ define i8* @test_simplify2(i8* %pat) {
 
 define i8* @test_simplify3() {
 ; CHECK-LABEL: @test_simplify3(
-  %str = getelementptr [12 x i8]* @hello, i32 0, i32 0
-  %pat = getelementptr [2 x i8]* @w, i32 0, i32 0
+  %str = getelementptr [12 x i8], [12 x i8]* @hello, i32 0, i32 0
+  %pat = getelementptr [2 x i8], [2 x i8]* @w, i32 0, i32 0
 
   %ret = call i8* @strpbrk(i8* %str, i8* %pat)
   ret i8* %ret
-; CHECK-NEXT: ret i8* getelementptr inbounds ([12 x i8]* @hello, i32 0, i32 6)
+; CHECK-NEXT: ret i8* getelementptr inbounds ([12 x i8], [12 x i8]* @hello, i32 0, i32 6)
 }
 
 ; Check strpbrk(s, "a") -> strchr(s, 'a').
 
 define i8* @test_simplify4(i8* %str) {
 ; CHECK-LABEL: @test_simplify4(
-  %pat = getelementptr [2 x i8]* @w, i32 0, i32 0
+  %pat = getelementptr [2 x i8], [2 x i8]* @w, i32 0, i32 0
 
   %ret = call i8* @strpbrk(i8* %str, i8* %pat)
 ; CHECK-NEXT: [[VAR:%[a-z]+]] = call i8* @strchr(i8* %str, i32 119)
diff --git a/test/Transforms/InstCombine/strpbrk-2.ll b/test/Transforms/InstCombine/strpbrk-2.ll
index b797d7a59527..0af6faf40bc2 100644
--- a/test/Transforms/InstCombine/strpbrk-2.ll
+++ b/test/Transforms/InstCombine/strpbrk-2.ll
@@ -13,8 +13,8 @@ declare i16* @strpbrk(i8*, i8*)
 
 define i16* @test_no_simplify1() {
 ; CHECK-LABEL: @test_no_simplify1(
-  %str = getelementptr [12 x i8]* @hello, i32 0, i32 0
-  %pat = getelementptr [2 x i8]* @w, i32 0, i32 0
+  %str = getelementptr [12 x i8], [12 x i8]* @hello, i32 0, i32 0
+  %pat = getelementptr [2 x i8], [2 x i8]* @w, i32 0, i32 0
 
   %ret = call i16* @strpbrk(i8* %str, i8* %pat)
 ; CHECK-NEXT: %ret = call i16* @strpbrk
diff --git a/test/Transforms/InstCombine/strrchr-1.ll b/test/Transforms/InstCombine/strrchr-1.ll
index 4615f5f2bd25..3ae68fba96df 100644
--- a/test/Transforms/InstCombine/strrchr-1.ll
+++ b/test/Transforms/InstCombine/strrchr-1.ll
@@ -10,11 +10,11 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 declare i8* @strrchr(i8*, i32)
 
 define void @test_simplify1() {
-; CHECK: store i8* getelementptr inbounds ([14 x i8]* @hello, i32 0, i32 6)
+; CHECK: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hello, i32 0, i32 6)
 ; CHECK-NOT: call i8* @strrchr
 ; CHECK: ret void
 
-  %str = getelementptr [14 x i8]* @hello, i32 0, i32 0
+  %str = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
   %dst = call i8* @strrchr(i8* %str, i32 119)
   store i8* %dst, i8** @chp
   ret void
@@ -25,29 +25,29 @@ define void @test_simplify2() {
 ; CHECK-NOT: call i8* @strrchr
 ; CHECK: ret void
 
-  %str = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %str = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
   %dst = call i8* @strrchr(i8* %str, i32 119)
   store i8* %dst, i8** @chp
   ret void
 }
 
 define void @test_simplify3() {
-; CHECK: store i8* getelementptr inbounds ([14 x i8]* @hello, i32 0, i32 13)
+; CHECK: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hello, i32 0, i32 13)
 ; CHECK-NOT: call i8* @strrchr
 ; CHECK: ret void
 
-  %src = getelementptr [14 x i8]* @hello, i32 0, i32 0
+  %src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
   %dst = call i8* @strrchr(i8* %src, i32 0)
   store i8* %dst, i8** @chp
   ret void
 }
 
 define void @test_simplify4() {
-; CHECK: store i8* getelementptr inbounds ([14 x i8]* @hello, i32 0, i32 13)
+; CHECK: store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @hello, i32 0, i32 13)
 ; CHECK-NOT: call i8* @strrchr
 ; CHECK: ret void
 
-  %src = getelementptr [14 x i8]* @hello, i32 0, i32 0
+  %src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
   %dst = call i8* @strrchr(i8* %src, i32 65280)
   store i8* %dst, i8** @chp
   ret void
@@ -58,7 +58,7 @@ define void @test_nosimplify1(i32 %chr) {
 ; CHECK: call i8* @strrchr
 ; CHECK: ret void
 
-  %src = getelementptr [14 x i8]* @hello, i32 0, i32 0
+  %src = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
   %dst = call i8* @strrchr(i8* %src, i32 %chr)
   store i8* %dst, i8** @chp
   ret void
diff --git a/test/Transforms/InstCombine/strrchr-2.ll b/test/Transforms/InstCombine/strrchr-2.ll
index 1974f6ca6033..4c203d0e8e79 100644
--- a/test/Transforms/InstCombine/strrchr-2.ll
+++ b/test/Transforms/InstCombine/strrchr-2.ll
@@ -14,7 +14,7 @@ define void @test_nosimplify1() {
 ; CHECK: call i8 @strrchr
 ; CHECK: ret void
 
-  %str = getelementptr [14 x i8]* @hello, i32 0, i32 0
+  %str = getelementptr [14 x i8], [14 x i8]* @hello, i32 0, i32 0
   %dst = call i8 @strrchr(i8* %str, i32 119)
   store i8 %dst, i8* @chr
   ret void
diff --git a/test/Transforms/InstCombine/strspn-1.ll b/test/Transforms/InstCombine/strspn-1.ll
index ac940cce9e56..3d9c573ac617 100644
--- a/test/Transforms/InstCombine/strspn-1.ll
+++ b/test/Transforms/InstCombine/strspn-1.ll
@@ -14,7 +14,7 @@ declare i64 @strspn(i8*, i8*)
 
 define i64 @test_simplify1(i8* %str) {
 ; CHECK-LABEL: @test_simplify1(
-  %pat = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %pat = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
 
   %ret = call i64 @strspn(i8* %str, i8* %pat)
   ret i64 %ret
@@ -25,7 +25,7 @@ define i64 @test_simplify1(i8* %str) {
 
 define i64 @test_simplify2(i8* %pat) {
 ; CHECK-LABEL: @test_simplify2(
-  %str = getelementptr [1 x i8]* @null, i32 0, i32 0
+  %str = getelementptr [1 x i8], [1 x i8]* @null, i32 0, i32 0
 
   %ret = call i64 @strspn(i8* %str, i8* %pat)
   ret i64 %ret
@@ -36,8 +36,8 @@ define i64 @test_simplify2(i8* %pat) {
 
 define i64 @test_simplify3() {
 ; CHECK-LABEL: @test_simplify3(
-  %str = getelementptr [6 x i8]* @abcba, i32 0, i32 0
-  %pat = getelementptr [4 x i8]* @abc, i32 0, i32 0
+  %str = getelementptr [6 x i8], [6 x i8]* @abcba, i32 0, i32 0
+  %pat = getelementptr [4 x i8], [4 x i8]* @abc, i32 0, i32 0
 
   %ret = call i64 @strspn(i8* %str, i8* %pat)
   ret i64 %ret
diff --git a/test/Transforms/InstCombine/strstr-1.ll b/test/Transforms/InstCombine/strstr-1.ll
index a946dd32779a..d57e56ccdaf3 100644
--- a/test/Transforms/InstCombine/strstr-1.ll
+++ b/test/Transforms/InstCombine/strstr-1.ll
@@ -15,7 +15,7 @@ declare i8* @strstr(i8*, i8*)
 
 define i8* @test_simplify1(i8* %str) {
 ; CHECK-LABEL: @test_simplify1(
-  %pat = getelementptr inbounds [1 x i8]* @.str, i32 0, i32 0
+  %pat = getelementptr inbounds [1 x i8], [1 x i8]* @.str, i32 0, i32 0
   %ret = call i8* @strstr(i8* %str, i8* %pat)
   ret i8* %ret
 ; CHECK-NEXT: ret i8* %str
@@ -25,7 +25,7 @@ define i8* @test_simplify1(i8* %str) {
 
 define i8* @test_simplify2(i8* %str) {
 ; CHECK-LABEL: @test_simplify2(
-  %pat = getelementptr inbounds [2 x i8]* @.str1, i32 0, i32 0
+  %pat = getelementptr inbounds [2 x i8], [2 x i8]* @.str1, i32 0, i32 0
   %ret = call i8* @strstr(i8* %str, i8* %pat)
   ret i8* %ret
 ; CHECK-NEXT: @strchr(i8* %str, i32 97)
@@ -35,11 +35,11 @@ define i8* @test_simplify2(i8* %str) {
 
 define i8* @test_simplify3() {
 ; CHECK-LABEL: @test_simplify3(
-  %str = getelementptr inbounds [6 x i8]* @.str2, i32 0, i32 0
-  %pat = getelementptr inbounds [4 x i8]* @.str3, i32 0, i32 0
+  %str = getelementptr inbounds [6 x i8], [6 x i8]* @.str2, i32 0, i32 0
+  %pat = getelementptr inbounds [4 x i8], [4 x i8]* @.str3, i32 0, i32 0
   %ret = call i8* @strstr(i8* %str, i8* %pat)
   ret i8* %ret
-; CHECK-NEXT: getelementptr inbounds ([6 x i8]* @.str2, i64 0, i64 1)
+; CHECK-NEXT: getelementptr inbounds ([6 x i8], [6 x i8]* @.str2, i64 0, i64 1)
 }
 
 ; Check strstr(str, str) -> str.
diff --git a/test/Transforms/InstCombine/strstr-2.ll b/test/Transforms/InstCombine/strstr-2.ll
index 7b28ed0e691e..9cb33115c2ee 100644
--- a/test/Transforms/InstCombine/strstr-2.ll
+++ b/test/Transforms/InstCombine/strstr-2.ll
@@ -10,7 +10,7 @@ declare i8 @strstr(i8*, i8*)
 
 define i8 @test_no_simplify1(i8* %str) {
 ; CHECK-LABEL: @test_no_simplify1(
-  %pat = getelementptr inbounds [1 x i8]* @null, i32 0, i32 0
+  %pat = getelementptr inbounds [1 x i8], [1 x i8]* @null, i32 0, i32 0
   %ret = call i8 @strstr(i8* %str, i8* %pat)
 ; CHECK-NEXT: call i8 @strstr
   ret i8 %ret
diff --git a/test/Transforms/InstCombine/struct-assign-tbaa.ll b/test/Transforms/InstCombine/struct-assign-tbaa.ll
index 4e4b3f2a1a88..c75a839f3fb6 100644
--- a/test/Transforms/InstCombine/struct-assign-tbaa.ll
+++ b/test/Transforms/InstCombine/struct-assign-tbaa.ll
@@ -10,8 +10,8 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
 %struct.test1 = type { float }
 
 ; CHECK: @test
-; CHECK: %2 = load float* %0, align 4, !tbaa !0
-; CHECK: store float %2, float* %1, align 4, !tbaa !0
+; CHECK: %[[LOAD:.*]] = load i32, i32* %{{.*}}, align 4, !tbaa !0
+; CHECK: store i32 %[[LOAD:.*]], i32* %{{.*}}, align 4, !tbaa !0
 ; CHECK: ret
 define void @test1(%struct.test1* nocapture %a, %struct.test1* nocapture %b) {
 entry:
@@ -30,8 +30,8 @@ define i32 (i8*, i32*, double*)*** @test2() {
   %tmp = alloca %struct.test2, align 8
   %tmp1 = bitcast %struct.test2* %tmp to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp1, i8* undef, i64 8, i32 8, i1 false), !tbaa.struct !4
-  %tmp2 = getelementptr %struct.test2* %tmp, i32 0, i32 0
-  %tmp3 = load i32 (i8*, i32*, double*)*** %tmp2
+  %tmp2 = getelementptr %struct.test2, %struct.test2* %tmp, i32 0, i32 0
+  %tmp3 = load i32 (i8*, i32*, double*)**, i32 (i8*, i32*, double*)*** %tmp2
   ret i32 (i8*, i32*, double*)*** %tmp2
 }
 
diff --git a/test/Transforms/InstCombine/sub.ll b/test/Transforms/InstCombine/sub.ll
index 0e421f75f139..c76d8d0e2205 100644
--- a/test/Transforms/InstCombine/sub.ll
+++ b/test/Transforms/InstCombine/sub.ll
@@ -216,7 +216,7 @@ define zeroext i1 @test22(i32 %a, i32 %b)  nounwind  {
 
 ; rdar://7362831
 define i32 @test23(i8* %P, i64 %A){
-  %B = getelementptr inbounds i8* %P, i64 %A
+  %B = getelementptr inbounds i8, i8* %P, i64 %A
   %C = ptrtoint i8* %B to i64
   %D = trunc i64 %C to i32
   %E = ptrtoint i8* %P to i64
@@ -232,7 +232,7 @@ define i8 @test23_as1(i8 addrspace(1)* %P, i16 %A) {
 ; CHECK: @test23_as1
 ; CHECK-NEXT: = trunc i16 %A to i8
 ; CHECK-NEXT: ret i8
-  %B = getelementptr inbounds i8 addrspace(1)* %P, i16 %A
+  %B = getelementptr inbounds i8, i8 addrspace(1)* %P, i16 %A
   %C = ptrtoint i8 addrspace(1)* %B to i16
   %D = trunc i16 %C to i8
   %E = ptrtoint i8 addrspace(1)* %P to i16
@@ -242,7 +242,7 @@ define i8 @test23_as1(i8 addrspace(1)* %P, i16 %A) {
 }
 
 define i64 @test24(i8* %P, i64 %A){
-  %B = getelementptr inbounds i8* %P, i64 %A
+  %B = getelementptr inbounds i8, i8* %P, i64 %A
   %C = ptrtoint i8* %B to i64
   %E = ptrtoint i8* %P to i64
   %G = sub i64 %C, %E
@@ -254,7 +254,7 @@ define i64 @test24(i8* %P, i64 %A){
 define i16 @test24_as1(i8 addrspace(1)* %P, i16 %A) {
 ; CHECK: @test24_as1
 ; CHECK-NEXT: ret i16 %A
-  %B = getelementptr inbounds i8 addrspace(1)* %P, i16 %A
+  %B = getelementptr inbounds i8, i8 addrspace(1)* %P, i16 %A
   %C = ptrtoint i8 addrspace(1)* %B to i16
   %E = ptrtoint i8 addrspace(1)* %P to i16
   %G = sub i16 %C, %E
@@ -262,7 +262,7 @@ define i16 @test24_as1(i8 addrspace(1)* %P, i16 %A) {
 }
 
 define i64 @test24a(i8* %P, i64 %A){
-  %B = getelementptr inbounds i8* %P, i64 %A
+  %B = getelementptr inbounds i8, i8* %P, i64 %A
   %C = ptrtoint i8* %B to i64
   %E = ptrtoint i8* %P to i64
   %G = sub i64 %E, %C
@@ -276,7 +276,7 @@ define i16 @test24a_as1(i8 addrspace(1)* %P, i16 %A) {
 ; CHECK: @test24a_as1
 ; CHECK-NEXT: sub i16 0, %A
 ; CHECK-NEXT: ret i16
-  %B = getelementptr inbounds i8 addrspace(1)* %P, i16 %A
+  %B = getelementptr inbounds i8, i8 addrspace(1)* %P, i16 %A
   %C = ptrtoint i8 addrspace(1)* %B to i16
   %E = ptrtoint i8 addrspace(1)* %P to i16
   %G = sub i16 %E, %C
@@ -287,7 +287,7 @@ define i16 @test24a_as1(i8 addrspace(1)* %P, i16 %A) {
 @Arr = external global [42 x i16]
 
 define i64 @test24b(i8* %P, i64 %A){
-  %B = getelementptr inbounds [42 x i16]* @Arr, i64 0, i64 %A
+  %B = getelementptr inbounds [42 x i16], [42 x i16]* @Arr, i64 0, i64 %A
   %C = ptrtoint i16* %B to i64
   %G = sub i64 %C, ptrtoint ([42 x i16]* @Arr to i64)
   ret i64 %G
@@ -298,9 +298,9 @@ define i64 @test24b(i8* %P, i64 %A){
 
 
 define i64 @test25(i8* %P, i64 %A){
-  %B = getelementptr inbounds [42 x i16]* @Arr, i64 0, i64 %A
+  %B = getelementptr inbounds [42 x i16], [42 x i16]* @Arr, i64 0, i64 %A
   %C = ptrtoint i16* %B to i64
-  %G = sub i64 %C, ptrtoint (i16* getelementptr ([42 x i16]* @Arr, i64 1, i64 0) to i64)
+  %G = sub i64 %C, ptrtoint (i16* getelementptr ([42 x i16], [42 x i16]* @Arr, i64 1, i64 0) to i64)
   ret i64 %G
 ; CHECK-LABEL: @test25(
 ; CHECK-NEXT: shl nuw i64 %A, 1
@@ -316,9 +316,9 @@ define i16 @test25_as1(i8 addrspace(1)* %P, i64 %A) {
 ; CHECK-NEXT: shl nuw i16 %1, 1
 ; CHECK-NEXT: add i16 {{.*}}, -84
 ; CHECK-NEXT: ret i16
-  %B = getelementptr inbounds [42 x i16] addrspace(1)* @Arr_as1, i64 0, i64 %A
+  %B = getelementptr inbounds [42 x i16], [42 x i16] addrspace(1)* @Arr_as1, i64 0, i64 %A
   %C = ptrtoint i16 addrspace(1)* %B to i16
-  %G = sub i16 %C, ptrtoint (i16 addrspace(1)* getelementptr ([42 x i16] addrspace(1)* @Arr_as1, i64 1, i64 0) to i16)
+  %G = sub i16 %C, ptrtoint (i16 addrspace(1)* getelementptr ([42 x i16], [42 x i16] addrspace(1)* @Arr_as1, i64 1, i64 0) to i16)
   ret i16 %G
 }
 
@@ -353,8 +353,8 @@ define i32 @test28(i32 %x, i32 %y, i32 %z) {
 }
 
 define i64 @test29(i8* %foo, i64 %i, i64 %j) {
-  %gep1 = getelementptr inbounds i8* %foo, i64 %i
-  %gep2 = getelementptr inbounds i8* %foo, i64 %j
+  %gep1 = getelementptr inbounds i8, i8* %foo, i64 %i
+  %gep2 = getelementptr inbounds i8, i8* %foo, i64 %j
   %cast1 = ptrtoint i8* %gep1 to i64
   %cast2 = ptrtoint i8* %gep2 to i64
   %sub = sub i64 %cast1, %cast2
@@ -366,8 +366,8 @@ define i64 @test29(i8* %foo, i64 %i, i64 %j) {
 
 define i64 @test30(i8* %foo, i64 %i, i64 %j) {
   %bit = bitcast i8* %foo to i32*
-  %gep1 = getelementptr inbounds i32* %bit, i64 %i
-  %gep2 = getelementptr inbounds i8* %foo, i64 %j
+  %gep1 = getelementptr inbounds i32, i32* %bit, i64 %i
+  %gep2 = getelementptr inbounds i8, i8* %foo, i64 %j
   %cast1 = ptrtoint i32* %gep1 to i64
   %cast2 = ptrtoint i8* %gep2 to i64
   %sub = sub i64 %cast1, %cast2
@@ -384,8 +384,8 @@ define i16 @test30_as1(i8 addrspace(1)* %foo, i16 %i, i16 %j) {
 ; CHECK-NEXT: sub i16 %gep1.idx, %j
 ; CHECK-NEXT: ret i16
   %bit = bitcast i8 addrspace(1)* %foo to i32 addrspace(1)*
-  %gep1 = getelementptr inbounds i32 addrspace(1)* %bit, i16 %i
-  %gep2 = getelementptr inbounds i8 addrspace(1)* %foo, i16 %j
+  %gep1 = getelementptr inbounds i32, i32 addrspace(1)* %bit, i16 %i
+  %gep2 = getelementptr inbounds i8, i8 addrspace(1)* %foo, i16 %j
   %cast1 = ptrtoint i32 addrspace(1)* %gep1 to i16
   %cast2 = ptrtoint i8 addrspace(1)* %gep2 to i16
   %sub = sub i16 %cast1, %cast2
diff --git a/test/Transforms/InstCombine/switch-truncate-crash.ll b/test/Transforms/InstCombine/switch-truncate-crash.ll
new file mode 100644
index 000000000000..cc3c1ff28ed2
--- /dev/null
+++ b/test/Transforms/InstCombine/switch-truncate-crash.ll
@@ -0,0 +1,7 @@
+; RUN: opt -instcombine < %s
+
+define void @test() {
+  switch i32 0, label %out [i32 0, label %out]
+out:
+  ret void
+}
diff --git a/test/Transforms/InstCombine/type_pun.ll b/test/Transforms/InstCombine/type_pun.ll
new file mode 100644
index 000000000000..098164cd029f
--- /dev/null
+++ b/test/Transforms/InstCombine/type_pun.ll
@@ -0,0 +1,141 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; Ensure that type punning using a union of vector and same-sized array
+; generates an extract instead of a shuffle with an uncommon vector size:
+;
+;   typedef uint32_t v4i32 __attribute__((vector_size(16)));
+;   union { v4i32 v; uint32_t a[4]; };
+;
+; This cleans up behind SROA, which inserts the uncommon vector size when
+; cleaning up the alloca/store/GEP/load.
+
+
+; Provide legal integer types.
+target datalayout = "p:32:32"
+
+
+; Extracting the zeroth element in an i32 array.
+define i32 @type_pun_zeroth(<16 x i8> %in) {
+; CHECK-LABEL: @type_pun_zeroth(
+; CHECK-NEXT: %[[BC:.*]] = bitcast <16 x i8> %in to <4 x i32>
+; CHECK-NEXT: %[[EXT:.*]] = extractelement <4 x i32> %[[BC]], i32 0
+; CHECK-NEXT: ret i32 %[[EXT]]
+  %sroa = shufflevector <16 x i8> %in, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %1 = bitcast <4 x i8> %sroa to i32
+  ret i32 %1
+}
+
+; Extracting the first element in an i32 array.
+define i32 @type_pun_first(<16 x i8> %in) {
+; CHECK-LABEL: @type_pun_first(
+; CHECK-NEXT: %[[BC:.*]] = bitcast <16 x i8> %in to <4 x i32>
+; CHECK-NEXT: %[[EXT:.*]] = extractelement <4 x i32> %[[BC]], i32 1
+; CHECK-NEXT: ret i32 %[[EXT]]
+  %sroa = shufflevector <16 x i8> %in, <16 x i8> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+  %1 = bitcast <4 x i8> %sroa to i32
+  ret i32 %1
+}
+
+; Extracting an i32 that isn't aligned to any natural boundary.
+define i32 @type_pun_misaligned(<16 x i8> %in) {
+; CHECK-LABEL: @type_pun_misaligned(
+; CHECK-NEXT: %[[SHUF:.*]] = shufflevector <16 x i8> %in, <16 x i8> undef, <16 x i32> <i32 6, i32 7, i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT: %[[BC:.*]] = bitcast <16 x i8> %[[SHUF]] to <4 x i32>
+; CHECK-NEXT: %[[EXT:.*]] = extractelement <4 x i32> %[[BC]], i32 0
+; CHECK-NEXT: ret i32 %[[EXT]]
+  %sroa = shufflevector <16 x i8> %in, <16 x i8> undef, <4 x i32> <i32 6, i32 7, i32 8, i32 9>
+  %1 = bitcast <4 x i8> %sroa to i32
+  ret i32 %1
+}
+
+; Type punning to an array of pointers.
+define i32* @type_pun_pointer(<16 x i8> %in) {
+; CHECK-LABEL: @type_pun_pointer(
+; CHECK-NEXT: %[[BC:.*]] = bitcast <16 x i8> %in to <4 x i32>
+; CHECK-NEXT: %[[EXT:.*]] = extractelement <4 x i32> %[[BC]], i32 0
+; CHECK-NEXT: %[[I2P:.*]] = inttoptr i32 %[[EXT]] to i32*
+; CHECK-NEXT: ret i32* %[[I2P]]
+  %sroa = shufflevector <16 x i8> %in, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %1 = bitcast <4 x i8> %sroa to i32
+  %2 = inttoptr i32 %1 to i32*
+  ret i32* %2
+}
+
+; Type punning to an array of 32-bit floating-point values.
+define float @type_pun_float(<16 x i8> %in) {
+; CHECK-LABEL: @type_pun_float(
+; CHECK-NEXT: %[[BC:.*]] = bitcast <16 x i8> %in to <4 x float>
+; CHECK-NEXT: %[[EXT:.*]] = extractelement <4 x float> %[[BC]], i32 0
+; CHECK-NEXT: ret float %[[EXT]]
+  %sroa = shufflevector <16 x i8> %in, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %1 = bitcast <4 x i8> %sroa to float
+  ret float %1
+}
+
+; Type punning to an array of 64-bit floating-point values.
+define double @type_pun_double(<16 x i8> %in) {
+; CHECK-LABEL: @type_pun_double(
+; CHECK-NEXT: %[[BC:.*]] = bitcast <16 x i8> %in to <2 x double>
+; CHECK-NEXT: %[[EXT:.*]] = extractelement <2 x double> %[[BC]], i32 0
+; CHECK-NEXT: ret double %[[EXT]]
+  %sroa = shufflevector <16 x i8> %in, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %1 = bitcast <8 x i8> %sroa to double
+  ret double %1
+}
+
+; Type punning to same-size floating-point and integer values.
+; Verify that multiple uses with different bitcast types are properly handled.
+define { float, i32 } @type_pun_float_i32(<16 x i8> %in) {
+; CHECK-LABEL: @type_pun_float_i32(
+; CHECK-NEXT: %[[BCI:.*]] = bitcast <16 x i8> %in to <4 x i32>
+; CHECK-NEXT: %[[EXTI:.*]] = extractelement <4 x i32> %[[BCI]], i32 0
+; CHECK-NEXT: %[[BCF:.*]] = bitcast <16 x i8> %in to <4 x float>
+; CHECK-NEXT: %[[EXTF:.*]] = extractelement <4 x float> %[[BCF]], i32 0
+; CHECK-NEXT: %1 = insertvalue { float, i32 } undef, float %[[EXTF]], 0
+; CHECK-NEXT: %2 = insertvalue { float, i32 } %1, i32 %[[EXTI]], 1
+; CHECK-NEXT: ret { float, i32 } %2
+  %sroa = shufflevector <16 x i8> %in, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %f = bitcast <4 x i8> %sroa to float
+  %i = bitcast <4 x i8> %sroa to i32
+  %1 = insertvalue { float, i32 } undef, float %f, 0
+  %2 = insertvalue { float, i32 } %1, i32 %i, 1
+  ret { float, i32 } %2
+}
+
+; Type punning two i32 values, with control flow.
+; Verify that the bitcast is shared and dominates usage.
+define i32 @type_pun_i32_ctrl(<16 x i8> %in) {
+; CHECK-LABEL: @type_pun_i32_ctrl(
+entry: ; CHECK-NEXT: entry:
+; CHECK-NEXT: %[[BC:.*]] = bitcast <16 x i8> %in to <4 x i32>
+; CHECK-NEXT: br
+  %sroa = shufflevector <16 x i8> %in, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  br i1 undef, label %left, label %right
+left: ; CHECK: left:
+; CHECK-NEXT: %[[EXTL:.*]] = extractelement <4 x i32> %[[BC]], i32 0
+; CHECK-NEXT: br
+  %lhs = bitcast <4 x i8> %sroa to i32
+  br label %tail
+right: ; CHECK: right:
+; CHECK-NEXT: %[[EXTR:.*]] = extractelement <4 x i32> %[[BC]], i32 0
+; CHECK-NEXT: br
+  %rhs = bitcast <4 x i8> %sroa to i32
+  br label %tail
+tail: ; CHECK: tail:
+; CHECK-NEXT: %i = phi i32 [ %[[EXTL]], %left ], [ %[[EXTR]], %right ]
+; CHECK-NEXT: ret i32 %i
+  %i = phi i32 [ %lhs, %left ], [ %rhs, %right ]
+  ret i32 %i
+}
+
+; Extracting a type that won't fit in a vector isn't handled. The function
+; should stay the same.
+define i40 @type_pun_unhandled(<16 x i8> %in) {
+; CHECK-LABEL: @type_pun_unhandled(
+; CHECK-NEXT: %sroa = shufflevector <16 x i8> %in, <16 x i8> undef, <5 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8>
+; CHECK-NEXT: %1 = bitcast <5 x i8> %sroa to i40
+; CHECK-NEXT: ret i40 %1
+  %sroa = shufflevector <16 x i8> %in, <16 x i8> undef, <5 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8>
+  %1 = bitcast <5 x i8> %sroa to i40
+  ret i40 %1
+}
diff --git a/test/Transforms/InstCombine/unpack-fca.ll b/test/Transforms/InstCombine/unpack-fca.ll
new file mode 100644
index 000000000000..48bb157956aa
--- /dev/null
+++ b/test/Transforms/InstCombine/unpack-fca.ll
@@ -0,0 +1,114 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+target datalayout = "e-i64:64-f80:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+%A__vtbl = type { i8*, i32 (%A*)* }
+%A = type { %A__vtbl* }
+
+@A__vtblZ = constant %A__vtbl { i8* null, i32 (%A*)* @A.foo }
+
+declare i32 @A.foo(%A* nocapture %this)
+
+declare i8* @allocmemory(i64)
+
+define void @storeA() {
+body:
+  %0 = tail call i8* @allocmemory(i64 32)
+  %1 = bitcast i8* %0 to %A*
+; CHECK-LABEL: storeA
+; CHECK: store %A__vtbl* @A__vtblZ
+  store %A { %A__vtbl* @A__vtblZ }, %A* %1, align 8
+  ret void
+}
+
+define void @storeStructOfA() {
+body:
+  %0 = tail call i8* @allocmemory(i64 32)
+  %1 = bitcast i8* %0 to { %A }*
+; CHECK-LABEL: storeStructOfA
+; CHECK: store %A__vtbl* @A__vtblZ
+  store { %A } { %A { %A__vtbl* @A__vtblZ } }, { %A }* %1, align 8
+  ret void
+}
+
+define void @storeArrayOfA() {
+body:
+  %0 = tail call i8* @allocmemory(i64 32)
+  %1 = bitcast i8* %0 to [1 x %A]*
+; CHECK-LABEL: storeArrayOfA
+; CHECK: store %A__vtbl* @A__vtblZ
+  store [1 x %A] [%A { %A__vtbl* @A__vtblZ }], [1 x %A]* %1, align 8
+  ret void
+}
+
+define void @storeStructOfArrayOfA() {
+body:
+  %0 = tail call i8* @allocmemory(i64 32)
+  %1 = bitcast i8* %0 to { [1 x %A] }*
+; CHECK-LABEL: storeStructOfArrayOfA
+; CHECK: store %A__vtbl* @A__vtblZ
+  store { [1 x %A] } { [1 x %A] [%A { %A__vtbl* @A__vtblZ }] }, { [1 x %A] }* %1, align 8
+  ret void
+}
+
+define %A @loadA() {
+body:
+  %0 = tail call i8* @allocmemory(i64 32)
+  %1 = bitcast i8* %0 to %A*
+; CHECK-LABEL: loadA
+; CHECK: load %A__vtbl*,
+; CHECK: insertvalue %A undef, %A__vtbl* {{.*}}, 0
+  %2 = load %A, %A* %1, align 8
+  ret %A %2
+}
+
+define { %A } @loadStructOfA() {
+body:
+  %0 = tail call i8* @allocmemory(i64 32)
+  %1 = bitcast i8* %0 to { %A }*
+; CHECK-LABEL: loadStructOfA
+; CHECK: load %A__vtbl*,
+; CHECK: insertvalue %A undef, %A__vtbl* {{.*}}, 0
+; CHECK: insertvalue { %A } undef, %A {{.*}}, 0
+  %2 = load { %A }, { %A }* %1, align 8
+  ret { %A } %2
+}
+
+define [1 x %A] @loadArrayOfA() {
+body:
+  %0 = tail call i8* @allocmemory(i64 32)
+  %1 = bitcast i8* %0 to [1 x %A]*
+; CHECK-LABEL: loadArrayOfA
+; CHECK: load %A__vtbl*,
+; CHECK: insertvalue %A undef, %A__vtbl* {{.*}}, 0
+; CHECK: insertvalue [1 x %A] undef, %A {{.*}}, 0
+  %2 = load [1 x %A], [1 x %A]* %1, align 8
+  ret [1 x %A] %2
+}
+
+define { [1 x %A] } @loadStructOfArrayOfA() {
+body:
+  %0 = tail call i8* @allocmemory(i64 32)
+  %1 = bitcast i8* %0 to { [1 x %A] }*
+; CHECK-LABEL: loadStructOfArrayOfA
+; CHECK: load %A__vtbl*,
+; CHECK: insertvalue %A undef, %A__vtbl* {{.*}}, 0
+; CHECK: insertvalue [1 x %A] undef, %A {{.*}}, 0
+; CHECK: insertvalue { [1 x %A] } undef, [1 x %A] {{.*}}, 0
+  %2 = load { [1 x %A] }, { [1 x %A] }* %1, align 8
+  ret { [1 x %A] } %2
+}
+
+define { %A } @structOfA() {
+body:
+  %0 = tail call i8* @allocmemory(i64 32)
+  %1 = bitcast i8* %0 to { %A }*
+; CHECK-LABEL: structOfA
+; CHECK: store %A__vtbl* @A__vtblZ
+  store { %A } { %A { %A__vtbl* @A__vtblZ } }, { %A }* %1, align 8
+  %2 = load { %A }, { %A }* %1, align 8
+; CHECK-NOT: load
+; CHECK: ret { %A } { %A { %A__vtbl* @A__vtblZ } }
+  ret { %A } %2
+}
diff --git a/test/Transforms/InstCombine/urem-simplify-bug.ll b/test/Transforms/InstCombine/urem-simplify-bug.ll
index 3e94ab5b2c33..1220dfdc77f0 100644
--- a/test/Transforms/InstCombine/urem-simplify-bug.ll
+++ b/test/Transforms/InstCombine/urem-simplify-bug.ll
@@ -22,8 +22,8 @@ bb14:		; preds = %entry
 	br label %bb15
 
 bb15:		; preds = %bb14, %bb
-	%iftmp.0.0 = phi i8* [ getelementptr ([5 x i8]* @.str1, i32 0, i32 0), %bb14 ], [ getelementptr ([5 x i8]* @.str, i32 0, i32 0), %bb ]		; <i8*> [#uses=1]
-	%tmp17 = call i32 (i8*, ...)* @printf( i8* %iftmp.0.0 ) nounwind 		; <i32> [#uses=0]
+	%iftmp.0.0 = phi i8* [ getelementptr ([5 x i8], [5 x i8]* @.str1, i32 0, i32 0), %bb14 ], [ getelementptr ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), %bb ]		; <i8*> [#uses=1]
+	%tmp17 = call i32 (i8*, ...) @printf( i8* %iftmp.0.0 ) nounwind 		; <i32> [#uses=0]
 	ret i32 0
 }
 
diff --git a/test/Transforms/InstCombine/vec_demanded_elts.ll b/test/Transforms/InstCombine/vec_demanded_elts.ll
index 00a029aeab78..4245c7a3c134 100644
--- a/test/Transforms/InstCombine/vec_demanded_elts.ll
+++ b/test/Transforms/InstCombine/vec_demanded_elts.ll
@@ -110,7 +110,7 @@ define void @vac(<4 x float>* nocapture %a) nounwind {
 ; CHECK-NOT: load
 ; CHECK: ret
 entry:
-	%tmp1 = load <4 x float>* %a		; <<4 x float>> [#uses=1]
+	%tmp1 = load <4 x float>, <4 x float>* %a		; <<4 x float>> [#uses=1]
 	%vecins = insertelement <4 x float> %tmp1, float 0.000000e+00, i32 0	; <<4 x float>> [#uses=1]
 	%vecins4 = insertelement <4 x float> %vecins, float 0.000000e+00, i32 1; <<4 x float>> [#uses=1]
 	%vecins6 = insertelement <4 x float> %vecins4, float 0.000000e+00, i32 2; <<4 x float>> [#uses=1]
@@ -141,8 +141,8 @@ declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>)
 ; <rdar://problem/6945110>
 define <4 x i32> @kernel3_vertical(<4 x i16> * %src, <8 x i16> * %foo) nounwind {
 entry:
-	%tmp = load <4 x i16>* %src
-	%tmp1 = load <8 x i16>* %foo
+	%tmp = load <4 x i16>, <4 x i16>* %src
+	%tmp1 = load <8 x i16>, <8 x i16>* %foo
 ; CHECK: %tmp2 = shufflevector
 	%tmp2 = shufflevector <4 x i16> %tmp, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
 ; pmovzxwd ignores the upper 64-bits of its input; -instcombine should remove this shuffle:
@@ -350,19 +350,19 @@ define <8 x float> @test_vpermilvar_ps_256(<8 x float> %v) {
   ret <8 x float> %a
 }
 
-declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i32>)
+declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i64>)
 define <2 x double> @test_vpermilvar_pd(<2 x double> %v) {
 ; CHECK-LABEL: @test_vpermilvar_pd(
 ; CHECK: shufflevector <2 x double> %v, <2 x double> undef, <2 x i32> <i32 1, i32 0>
-  %a = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %v, <2 x i32> <i32 2, i32 0>)
+  %a = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %v, <2 x i64> <i64 2, i64 0>)
   ret <2 x double> %a
 }
 
-declare <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double>, <4 x i32>)
+declare <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double>, <4 x i64>)
 define <4 x double> @test_vpermilvar_pd_256(<4 x double> %v) {
 ; CHECK-LABEL: @test_vpermilvar_pd_256(
 ; CHECK: shufflevector <4 x double> %v, <4 x double> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
-  %a = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %v, <4 x i32> <i32 3, i32 1, i32 2, i32 0>)
+  %a = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %v, <4 x i64> <i64 3, i64 1, i64 2, i64 0>)
   ret <4 x double> %a
 }
 
@@ -383,14 +383,14 @@ define <8 x float> @test_vpermilvar_ps_256_zero(<8 x float> %v) {
 define <2 x double> @test_vpermilvar_pd_zero(<2 x double> %v) {
 ; CHECK-LABEL: @test_vpermilvar_pd_zero(
 ; CHECK: shufflevector <2 x double> %v, <2 x double> undef, <2 x i32> zeroinitializer
-  %a = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %v, <2 x i32> zeroinitializer)
+  %a = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %v, <2 x i64> zeroinitializer)
   ret <2 x double> %a
 }
 
 define <4 x double> @test_vpermilvar_pd_256_zero(<4 x double> %v) {
 ; CHECK-LABEL: @test_vpermilvar_pd_256_zero(
 ; CHECK: shufflevector <4 x double> %v, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
-  %a = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %v, <4 x i32> zeroinitializer)
+  %a = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %v, <4 x i64> zeroinitializer)
   ret <4 x double> %a
 }
 
diff --git a/test/Transforms/InstCombine/vec_extract_var_elt.ll b/test/Transforms/InstCombine/vec_extract_var_elt.ll
index f6f9e0134a16..5c0610ff48bb 100644
--- a/test/Transforms/InstCombine/vec_extract_var_elt.ll
+++ b/test/Transforms/InstCombine/vec_extract_var_elt.ll
@@ -3,7 +3,7 @@
 define void @test (float %b, <8 x float> * %p)  {
 ; CHECK: extractelement
 ; CHECK: fptosi
-  %1 = load <8 x float> * %p
+  %1 = load <8 x float> , <8 x float> * %p
   %2 = bitcast <8 x float> %1 to <8 x i32>
   %3 = bitcast <8 x i32> %2 to <8 x float>
   %a = fptosi <8 x float> %3 to <8 x i32>
diff --git a/test/Transforms/InstCombine/vec_phi_extract.ll b/test/Transforms/InstCombine/vec_phi_extract.ll
index 1d778a000fb7..1079dc9e7198 100644
--- a/test/Transforms/InstCombine/vec_phi_extract.ll
+++ b/test/Transforms/InstCombine/vec_phi_extract.ll
@@ -16,7 +16,7 @@ loop:
   %end = icmp ult i32 %elt, %limit
   %3 = add i32 10, %elt
   %4 = sext i32 %elt to i64
-  %5 = getelementptr i32* %ptr, i64 %4
+  %5 = getelementptr i32, i32* %ptr, i64 %4
   store i32 %3, i32* %5
   %inc = add <16 x i32> %2, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
   br i1 %end, label %loop, label %ret
diff --git a/test/Transforms/InstCombine/vec_shuffle.ll b/test/Transforms/InstCombine/vec_shuffle.ll
index eb4e9d6f8c30..d4d7f167ef07 100644
--- a/test/Transforms/InstCombine/vec_shuffle.ll
+++ b/test/Transforms/InstCombine/vec_shuffle.ll
@@ -190,11 +190,11 @@ define void @test14(i16 %conv10) {
   %tmp = alloca <4 x i16>, align 8
   %vecinit6 = insertelement <4 x i16> undef, i16 23, i32 3
   store <4 x i16> %vecinit6, <4 x i16>* undef
-  %tmp1 = load <4 x i16>* undef
+  %tmp1 = load <4 x i16>, <4 x i16>* undef
   %vecinit11 = insertelement <4 x i16> undef, i16 %conv10, i32 3
   %div = udiv <4 x i16> %tmp1, %vecinit11
   store <4 x i16> %div, <4 x i16>* %tmp
-  %tmp4 = load <4 x i16>* %tmp
+  %tmp4 = load <4 x i16>, <4 x i16>* %tmp
   %tmp5 = shufflevector <4 x i16> %tmp4, <4 x i16> undef, <2 x i32> <i32 2, i32 0>
   %cmp = icmp ule <2 x i16> %tmp5, undef
   %sext = sext <2 x i1> %cmp to <2 x i16>
@@ -414,3 +414,11 @@ define <4 x i32> @pr20114(<4 x i32> %__mask) {
   %masked_new.i.i.i = and <4 x i32> bitcast (<2 x i64> <i64 ptrtoint (<4 x i32> (<4 x i32>)* @pr20114 to i64), i64 ptrtoint (<4 x i32> (<4 x i32>)* @pr20114 to i64)> to <4 x i32>), %mask01.i
   ret <4 x i32> %masked_new.i.i.i
 }
+
+define <2 x i32*> @pr23113(<4 x i32*> %A) {
+; CHECK-LABEL: @pr23113
+; CHECK: %[[V:.*]] = shufflevector <4 x i32*> %A, <4 x i32*> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: ret <2 x i32*> %[[V]]
+  %1 = shufflevector <4 x i32*> %A, <4 x i32*> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x i32*> %1
+}
diff --git a/test/Transforms/InstCombine/vector-casts.ll b/test/Transforms/InstCombine/vector-casts.ll
index ca97b3407da6..727eb4ebb4c8 100644
--- a/test/Transforms/InstCombine/vector-casts.ll
+++ b/test/Transforms/InstCombine/vector-casts.ll
@@ -133,7 +133,7 @@ entry:
   %dim31 = insertelement <4 x i32> %dim30, i32 %a, i32 2
   %dim32 = insertelement <4 x i32> %dim31, i32 %a, i32 3
 
-  %offset_ptr = getelementptr <4 x float>* null, i32 1
+  %offset_ptr = getelementptr <4 x float>, <4 x float>* null, i32 1
   %offset_int = ptrtoint <4 x float>* %offset_ptr to i64
   %sizeof32 = trunc i64 %offset_int to i32
 
diff --git a/test/Transforms/InstCombine/vector_gep1.ll b/test/Transforms/InstCombine/vector_gep1.ll
index 90ca26212f2a..0f4e407dd7fe 100644
--- a/test/Transforms/InstCombine/vector_gep1.ll
+++ b/test/Transforms/InstCombine/vector_gep1.ll
@@ -17,26 +17,26 @@ define <2 x i1> @test2(<2 x i8*> %a) {
 }
 
 define <2 x i1> @test3(<2 x i8*> %a) {
-  %g = getelementptr <2 x i8*> %a, <2 x i32> <i32 1, i32 0>
+  %g = getelementptr i8, <2 x i8*> %a, <2 x i32> <i32 1, i32 0>
   %B = icmp ult <2 x i8*> %g, zeroinitializer
   ret <2 x i1> %B
 }
 
 define <1 x i1> @test4(<1 x i8*> %a) {
-  %g = getelementptr <1 x i8*> %a, <1 x i32> <i32 1>
+  %g = getelementptr i8, <1 x i8*> %a, <1 x i32> <i32 1>
   %B = icmp ult <1 x i8*> %g, zeroinitializer
   ret <1 x i1> %B
 }
 
 define <2 x i1> @test5(<2 x i8*> %a) {
-  %w = getelementptr <2 x i8*> %a, <2 x i32> zeroinitializer
-  %e = getelementptr <2 x i8*> %w, <2 x i32> <i32 5, i32 9>
-  %g = getelementptr <2 x i8*> %e, <2 x i32> <i32 1, i32 0>
+  %w = getelementptr i8, <2 x i8*> %a, <2 x i32> zeroinitializer
+  %e = getelementptr i8, <2 x i8*> %w, <2 x i32> <i32 5, i32 9>
+  %g = getelementptr i8, <2 x i8*> %e, <2 x i32> <i32 1, i32 0>
   %B = icmp ult <2 x i8*> %g, zeroinitializer
   ret <2 x i1> %B
 }
 
 define <2 x i32*> @test7(<2 x {i32, i32}*> %a) {
-  %w = getelementptr <2 x {i32, i32}*> %a, <2 x i32> <i32 5, i32 9>, <2 x i32> zeroinitializer
+  %w = getelementptr {i32, i32}, <2 x {i32, i32}*> %a, <2 x i32> <i32 5, i32 9>, <2 x i32> zeroinitializer
   ret <2 x i32*> %w
 }
diff --git a/test/Transforms/InstCombine/vector_gep2.ll b/test/Transforms/InstCombine/vector_gep2.ll
index 42057d60b8c8..d76a7d56cc7a 100644
--- a/test/Transforms/InstCombine/vector_gep2.ll
+++ b/test/Transforms/InstCombine/vector_gep2.ll
@@ -5,7 +5,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define <2 x i8*> @testa(<2 x i8*> %a) {
 ; CHECK-LABEL: @testa(
-  %g = getelementptr <2 x i8*> %a, <2 x i32> <i32 0, i32 1>
-; CHECK: getelementptr <2 x i8*> %a, <2 x i64> <i64 0, i64 1>
+  %g = getelementptr i8, <2 x i8*> %a, <2 x i32> <i32 0, i32 1>
+; CHECK: getelementptr i8, <2 x i8*> %a, <2 x i64> <i64 0, i64 1>
   ret <2 x i8*> %g
 }
diff --git a/test/Transforms/InstCombine/volatile_store.ll b/test/Transforms/InstCombine/volatile_store.ll
index 7cab199a58f4..7377b6815e29 100644
--- a/test/Transforms/InstCombine/volatile_store.ll
+++ b/test/Transforms/InstCombine/volatile_store.ll
@@ -5,7 +5,7 @@
 
 define void @self_assign_1() {
 entry:
-	%tmp = load volatile i32* @x		; <i32> [#uses=1]
+	%tmp = load volatile i32, i32* @x		; <i32> [#uses=1]
 	store volatile i32 %tmp, i32* @x
 	br label %return
 
diff --git a/test/Transforms/InstCombine/vsx-unaligned.ll b/test/Transforms/InstCombine/vsx-unaligned.ll
index 26e04268f446..ad264fb15b31 100644
--- a/test/Transforms/InstCombine/vsx-unaligned.ll
+++ b/test/Transforms/InstCombine/vsx-unaligned.ll
@@ -14,28 +14,28 @@ entry:
   %t1 = alloca <4 x float>*, align 8
   %t2 = alloca <2 x double>*, align 8
   store <4 x float>* @vf, <4 x float>** %t1, align 8
-  %0 = load <4 x float>** %t1, align 8
+  %0 = load <4 x float>*, <4 x float>** %t1, align 8
   %1 = bitcast <4 x float>* %0 to i8*
   %2 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %1)
   store <4 x float>* @res_vf, <4 x float>** %t1, align 8
-  %3 = load <4 x float>** %t1, align 8
+  %3 = load <4 x float>*, <4 x float>** %t1, align 8
   %4 = bitcast <4 x float>* %3 to i8*
   call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %2, i8* %4)
   store <2 x double>* @vd, <2 x double>** %t2, align 8
-  %5 = load <2 x double>** %t2, align 8
+  %5 = load <2 x double>*, <2 x double>** %t2, align 8
   %6 = bitcast <2 x double>* %5 to i8*
   %7 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %6)
   store <2 x double>* @res_vd, <2 x double>** %t2, align 8
-  %8 = load <2 x double>** %t2, align 8
+  %8 = load <2 x double>*, <2 x double>** %t2, align 8
   %9 = bitcast <2 x double>* %8 to i8*
   call void @llvm.ppc.vsx.stxvd2x(<2 x double> %7, i8* %9)
   ret void
 }
 
 ; CHECK-LABEL: @test1
-; CHECK: %0 = load <4 x i32>* bitcast (<4 x float>* @vf to <4 x i32>*), align 1
+; CHECK: %0 = load <4 x i32>, <4 x i32>* bitcast (<4 x float>* @vf to <4 x i32>*), align 1
 ; CHECK: store <4 x i32> %0, <4 x i32>* bitcast (<4 x float>* @res_vf to <4 x i32>*), align 1
-; CHECK: %1 = load <2 x double>* @vd, align 1
+; CHECK: %1 = load <2 x double>, <2 x double>* @vd, align 1
 ; CHECK: store <2 x double> %1, <2 x double>* @res_vd, align 1
 
 declare <4 x i32> @llvm.ppc.vsx.lxvw4x(i8*)
diff --git a/test/Transforms/InstCombine/weak-symbols.ll b/test/Transforms/InstCombine/weak-symbols.ll
index ec946ead8602..3f92e64d2ec0 100644
--- a/test/Transforms/InstCombine/weak-symbols.ll
+++ b/test/Transforms/InstCombine/weak-symbols.ll
@@ -13,8 +13,8 @@ define i32 @foo() nounwind {
 ; CHECK: ret i32 %temp1
 
 entry:
-  %str1 = getelementptr inbounds [2 x i8]* @fake_init, i64 0, i64 0
-  %str2 = getelementptr inbounds [2 x i8]* @.str, i64 0, i64 0
+  %str1 = getelementptr inbounds [2 x i8], [2 x i8]* @fake_init, i64 0, i64 0
+  %str2 = getelementptr inbounds [2 x i8], [2 x i8]* @.str, i64 0, i64 0
   %temp1 = call i32 @strcmp(i8* %str1, i8* %str2) nounwind readonly
   ret i32 %temp1
 }
@@ -24,8 +24,8 @@ define i32 @bar() nounwind {
 ; CHECK: ret i32 0
 
 entry:
-  %str1 = getelementptr inbounds [2 x i8]* @real_init, i64 0, i64 0
-  %str2 = getelementptr inbounds [2 x i8]* @.str, i64 0, i64 0
+  %str1 = getelementptr inbounds [2 x i8], [2 x i8]* @real_init, i64 0, i64 0
+  %str2 = getelementptr inbounds [2 x i8], [2 x i8]* @.str, i64 0, i64 0
   %temp1 = call i32 @strcmp(i8* %str1, i8* %str2) nounwind readonly
   ret i32 %temp1
 }
diff --git a/test/Transforms/InstCombine/x86-insertps.ll b/test/Transforms/InstCombine/x86-insertps.ll
new file mode 100644
index 000000000000..092bf7c6c624
--- /dev/null
+++ b/test/Transforms/InstCombine/x86-insertps.ll
@@ -0,0 +1,150 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounwind readnone
+
+; This should never happen, but make sure we don't crash handling a non-constant immediate byte.
+
+define <4 x float> @insertps_non_const_imm(<4 x float> %v1, <4 x float> %v2, i8 %c) {
+  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 %c)
+  ret <4 x float> %res
+
+; CHECK-LABEL: @insertps_non_const_imm
+; CHECK-NEXT:  call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 %c)
+; CHECK-NEXT:  ret <4 x float>
+}
+
+; If all zero mask bits are set, return a zero regardless of the other control bits.
+
+define <4 x float> @insertps_0x0f(<4 x float> %v1, <4 x float> %v2) {
+  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 15)
+  ret <4 x float> %res
+
+; CHECK-LABEL: @insertps_0x0f
+; CHECK-NEXT:  ret <4 x float> zeroinitializer
+}
+define <4 x float> @insertps_0xff(<4 x float> %v1, <4 x float> %v2) {
+  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 255)
+  ret <4 x float> %res
+
+; CHECK-LABEL: @insertps_0xff
+; CHECK-NEXT:  ret <4 x float> zeroinitializer
+}
+
+; If some zero mask bits are set that do not override the insertion, we do not change anything.
+
+define <4 x float> @insertps_0x0c(<4 x float> %v1, <4 x float> %v2) {
+  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 12)
+  ret <4 x float> %res
+
+; CHECK-LABEL: @insertps_0x0c
+; CHECK-NEXT:  call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 12)
+; CHECK-NEXT:  ret <4 x float>
+}
+
+; ...unless both input vectors are the same operand.
+
+define <4 x float> @insertps_0x15_single_input(<4 x float> %v1) {
+  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v1, i8 21)
+  ret <4 x float> %res
+
+; CHECK-LABEL: @insertps_0x15_single_input
+; CHECK-NEXT:  shufflevector <4 x float> %v1, <4 x float> <float 0.000000e+00, float undef, float 0.000000e+00, float undef>, <4 x i32> <i32 4, i32 0, i32 6, i32 3>
+; CHECK-NEXT:  ret <4 x float>
+}
+
+; The zero mask overrides the insertion lane.
+
+define <4 x float> @insertps_0x1a_single_input(<4 x float> %v1) {
+  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v1, i8 26)
+  ret <4 x float> %res
+
+; CHECK-LABEL: @insertps_0x1a_single_input
+; CHECK-NEXT:  shufflevector <4 x float> %v1, <4 x float> <float undef, float 0.000000e+00, float undef, float 0.000000e+00>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; CHECK-NEXT:  ret <4 x float>
+}
+
+; The zero mask overrides the insertion lane, so the second input vector is not used.
+
+define <4 x float> @insertps_0xc1(<4 x float> %v1, <4 x float> %v2) {
+  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 193)
+  ret <4 x float> %res
+
+; CHECK-LABEL: @insertps_0xc1
+; CHECK-NEXT:  shufflevector <4 x float> %v1, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
+; CHECK-NEXT:  ret <4 x float>
+}
+
+; If no zero mask bits are set, convert to a shuffle.
+
+define <4 x float> @insertps_0x00(<4 x float> %v1, <4 x float> %v2) {
+  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 0)
+  ret <4 x float> %res
+
+; CHECK-LABEL: @insertps_0x00
+; CHECK-NEXT:  shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
+; CHECK-NEXT:  ret <4 x float>
+}
+
+define <4 x float> @insertps_0x10(<4 x float> %v1, <4 x float> %v2) {
+  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 16)
+  ret <4 x float> %res
+
+; CHECK-LABEL: @insertps_0x10
+; CHECK-NEXT:  shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
+; CHECK-NEXT:  ret <4 x float>
+}
+
+define <4 x float> @insertps_0x20(<4 x float> %v1, <4 x float> %v2) {
+  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 32)
+  ret <4 x float> %res
+
+; CHECK-LABEL: @insertps_0x20
+; CHECK-NEXT:  shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
+; CHECK-NEXT:  ret <4 x float>
+}
+
+define <4 x float> @insertps_0x30(<4 x float> %v1, <4 x float> %v2) {
+  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 48)
+  ret <4 x float> %res
+
+; CHECK-LABEL: @insertps_0x30
+; CHECK-NEXT:  shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
+; CHECK-NEXT:  ret <4 x float>
+}
+
+define <4 x float> @insertps_0xc0(<4 x float> %v1, <4 x float> %v2) {
+  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 192)
+  ret <4 x float> %res
+
+; CHECK-LABEL: @insertps_0xc0
+; CHECK-NEXT:  shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 7, i32 1, i32 2, i32 3>
+; CHECK-NEXT:  ret <4 x float>
+}
+
+define <4 x float> @insertps_0xd0(<4 x float> %v1, <4 x float> %v2) {
+  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 208)
+  ret <4 x float> %res
+
+; CHECK-LABEL: @insertps_0xd0
+; CHECK-NEXT:  shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
+; CHECK-NEXT:  ret <4 x float>
+}
+
+define <4 x float> @insertps_0xe0(<4 x float> %v1, <4 x float> %v2) {
+  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 224)
+  ret <4 x float> %res
+
+; CHECK-LABEL: @insertps_0xe0
+; CHECK-NEXT:  shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 0, i32 1, i32 7, i32 3>
+; CHECK-NEXT:  ret <4 x float>
+}
+
+define <4 x float> @insertps_0xf0(<4 x float> %v1, <4 x float> %v2) {
+  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 240)
+  ret <4 x float> %res
+
+; CHECK-LABEL: @insertps_0xf0
+; CHECK-NEXT:  shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+; CHECK-NEXT:  ret <4 x float>
+}
+
diff --git a/test/Transforms/InstCombine/x86-vperm2.ll b/test/Transforms/InstCombine/x86-vperm2.ll
new file mode 100644
index 000000000000..5c60852dddb6
--- /dev/null
+++ b/test/Transforms/InstCombine/x86-vperm2.ll
@@ -0,0 +1,283 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; This should never happen, but make sure we don't crash handling a non-constant immediate byte.
+
+define <4 x double> @perm2pd_non_const_imm(<4 x double> %a0, <4 x double> %a1, i8 %b) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 %b) 
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_non_const_imm
+; CHECK-NEXT:  call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 %b)
+; CHECK-NEXT:  ret <4 x double>
+}
+
+
+; In the following 4 tests, both zero mask bits of the immediate are set.
+
+define <4 x double> @perm2pd_0x88(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 136) 
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x88
+; CHECK-NEXT:  ret <4 x double> zeroinitializer
+}
+
+define <8 x float> @perm2ps_0x88(<8 x float> %a0, <8 x float> %a1) {
+  %res = call <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float> %a0, <8 x float> %a1, i8 136) 
+  ret <8 x float> %res
+
+; CHECK-LABEL: @perm2ps_0x88
+; CHECK-NEXT:  ret <8 x float> zeroinitializer
+}
+
+define <8 x i32> @perm2si_0x88(<8 x i32> %a0, <8 x i32> %a1) {
+  %res = call <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32> %a0, <8 x i32> %a1, i8 136) 
+  ret <8 x i32> %res
+
+; CHECK-LABEL: @perm2si_0x88
+; CHECK-NEXT:  ret <8 x i32> zeroinitializer
+}
+
+define <4 x i64> @perm2i_0x88(<4 x i64> %a0, <4 x i64> %a1) {
+  %res = call <4 x i64> @llvm.x86.avx2.vperm2i128(<4 x i64> %a0, <4 x i64> %a1, i8 136) 
+  ret <4 x i64> %res
+
+; CHECK-LABEL: @perm2i_0x88
+; CHECK-NEXT:  ret <4 x i64> zeroinitializer
+}
+
+
+; The other control bits are ignored when zero mask bits of the immediate are set.
+
+define <4 x double> @perm2pd_0xff(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 255) 
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0xff
+; CHECK-NEXT:  ret <4 x double> zeroinitializer
+}
+
+
+; The following 16 tests are simple shuffles, except for 2 cases where we can just return one of the
+; source vectors. Verify that we generate the right shuffle masks and undef source operand where possible..
+
+define <4 x double> @perm2pd_0x00(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 0)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x00
+; CHECK-NEXT:  %1 = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+; CHECK-NEXT:  ret <4 x double> %1
+}
+
+define <4 x double> @perm2pd_0x01(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 1)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x01
+; CHECK-NEXT:  %1 = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
+; CHECK-NEXT:  ret <4 x double> %1
+}
+
+define <4 x double> @perm2pd_0x02(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 2)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x02
+; CHECK-NEXT:  %1 = shufflevector <4 x double> %a1, <4 x double> %a0, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+; CHECK-NEXT:  ret <4 x double> %1
+}
+
+define <4 x double> @perm2pd_0x03(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 3)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x03
+; CHECK-NEXT:  %1 = shufflevector <4 x double> %a1, <4 x double> %a0, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
+; CHECK-NEXT:  ret <4 x double> %1
+}
+
+define <4 x double> @perm2pd_0x10(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 16)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x10
+; CHECK-NEXT:  ret <4 x double> %a0
+}
+
+define <4 x double> @perm2pd_0x11(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 17)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x11
+; CHECK-NEXT:  %1 = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
+; CHECK-NEXT:  ret <4 x double> %1
+}
+
+define <4 x double> @perm2pd_0x12(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 18)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x12
+; CHECK-NEXT:  %1 = shufflevector <4 x double> %a1, <4 x double> %a0, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT:  ret <4 x double> %1
+}
+
+define <4 x double> @perm2pd_0x13(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 19)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x13
+; CHECK-NEXT:  %1 = shufflevector <4 x double> %a1, <4 x double> %a0, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
+; CHECK-NEXT:  ret <4 x double> %1
+}
+
+define <4 x double> @perm2pd_0x20(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 32)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x20
+; CHECK-NEXT:  %1 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+; CHECK-NEXT:  ret <4 x double> %1
+}
+
+define <4 x double> @perm2pd_0x21(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 33)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x21
+; CHECK-NEXT:  %1 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
+; CHECK-NEXT:  ret <4 x double> %1
+}
+
+define <4 x double> @perm2pd_0x22(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 34)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x22
+; CHECK-NEXT:  %1 = shufflevector <4 x double> %a1, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+; CHECK-NEXT:  ret <4 x double> %1
+}
+
+define <4 x double> @perm2pd_0x23(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 35)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x23
+; CHECK-NEXT:  %1 = shufflevector <4 x double> %a1, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
+; CHECK-NEXT:  ret <4 x double> %1
+}
+
+define <4 x double> @perm2pd_0x30(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 48)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x30
+; CHECK-NEXT:  %1 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT:  ret <4 x double> %1
+}
+
+define <4 x double> @perm2pd_0x31(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 49)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x31
+; CHECK-NEXT:  %1 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
+; CHECK-NEXT:  ret <4 x double> %1
+}
+
+define <4 x double> @perm2pd_0x32(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 50)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x32
+; CHECK-NEXT:  ret <4 x double> %a1
+}
+
+define <4 x double> @perm2pd_0x33(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 51)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x33
+; CHECK-NEXT:  %1 = shufflevector <4 x double> %a1, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
+; CHECK-NEXT:  ret <4 x double> %1
+}
+
+; Confirm that a mask for 32-bit elements is also correct.
+
+define <8 x float> @perm2ps_0x31(<8 x float> %a0, <8 x float> %a1) {
+  %res = call <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float> %a0, <8 x float> %a1, i8 49)
+  ret <8 x float> %res
+
+; CHECK-LABEL: @perm2ps_0x31
+; CHECK-NEXT:  %1 = shufflevector <8 x float> %a0, <8 x float> %a1, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT:  ret <8 x float> %1
+}
+
+
+; Confirm that the AVX2 version works the same.
+
+define <4 x i64> @perm2i_0x33(<4 x i64> %a0, <4 x i64> %a1) {
+  %res = call <4 x i64> @llvm.x86.avx2.vperm2i128(<4 x i64> %a0, <4 x i64> %a1, i8 51)
+  ret <4 x i64> %res
+
+; CHECK-LABEL: @perm2i_0x33
+; CHECK-NEXT:  %1 = shufflevector <4 x i64> %a1, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
+; CHECK-NEXT:  ret <4 x i64> %1
+}
+
+
+; Confirm that when a single zero mask bit is set, we replace a source vector with zeros.
+
+define <4 x double> @perm2pd_0x81(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 129)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x81
+; CHECK-NEXT:  shufflevector <4 x double> %a0, <4 x double> <double 0.0{{.*}}<4 x i32> <i32 2, i32 3, i32 4, i32 5>
+; CHECK-NEXT:  ret <4 x double>
+}
+
+define <4 x double> @perm2pd_0x83(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 131)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x83
+; CHECK-NEXT:  shufflevector <4 x double> %a1, <4 x double> <double 0.0{{.*}}, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
+; CHECK-NEXT:  ret <4 x double>
+}
+
+define <4 x double> @perm2pd_0x28(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 40)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x28
+; CHECK-NEXT:  shufflevector <4 x double> <double 0.0{{.*}}, <4 x double> %a1, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+; CHECK-NEXT:  ret <4 x double>
+}
+
+define <4 x double> @perm2pd_0x08(<4 x double> %a0, <4 x double> %a1) {
+  %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 8)
+  ret <4 x double> %res
+
+; CHECK-LABEL: @perm2pd_0x08
+; CHECK-NEXT:  shufflevector <4 x double> <double 0.0{{.*}}, <4 x double> %a0, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+; CHECK-NEXT:  ret <4 x double>
+}
+
+; Check one more with the AVX2 version.
+
+define <4 x i64> @perm2i_0x28(<4 x i64> %a0, <4 x i64> %a1) {
+  %res = call <4 x i64> @llvm.x86.avx2.vperm2i128(<4 x i64> %a0, <4 x i64> %a1, i8 40)
+  ret <4 x i64> %res
+
+; CHECK-LABEL: @perm2i_0x28
+; CHECK-NEXT:  shufflevector <4 x i64> <i64 0{{.*}}, <4 x i64> %a1, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+; CHECK-NEXT:  ret <4 x i64>
+}
+
+declare <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone
+declare <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone
+declare <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32>, <8 x i32>, i8) nounwind readnone
+declare <4 x i64> @llvm.x86.avx2.vperm2i128(<4 x i64>, <4 x i64>, i8) nounwind readnone
+
diff --git a/test/Transforms/InstCombine/xor.ll b/test/Transforms/InstCombine/xor.ll
index c8debcbac226..33d5a2a9fda5 100644
--- a/test/Transforms/InstCombine/xor.ll
+++ b/test/Transforms/InstCombine/xor.ll
@@ -63,8 +63,8 @@ define i32 @test7(i32 %A, i32 %B) {
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT: %A1 = and i32 %A, 7
 ; CHECK-NEXT: %B1 = and i32 %B, 128
-; CHECK-NEXT: %C11 = or i32 %A1, %B1
-; CHECK-NEXT: ret i32 %C11
+; CHECK-NEXT: %C1.1 = or i32 %A1, %B1
+; CHECK-NEXT: ret i32 %C1.1
 	%A1 = and i32 %A, 7		; <i32> [#uses=1]
 	%B1 = and i32 %B, 128		; <i32> [#uses=1]
 	%C1 = xor i32 %A1, %B1		; <i32> [#uses=1]
@@ -96,8 +96,8 @@ define i1 @test9(i8 %A) {
 define i8 @test10(i8 %A) {
 ; CHECK-LABEL: @test10(
 ; CHECK-NEXT: %B = and i8 %A, 3
-; CHECK-NEXT: %C1 = or i8 %B, 4
-; CHECK-NEXT: ret i8 %C1
+; CHECK-NEXT: %C.1 = or i8 %B, 4
+; CHECK-NEXT: ret i8 %C.1
 	%B = and i8 %A, 3		; <i8> [#uses=1]
 	%C = xor i8 %B, 4		; <i8> [#uses=1]
 	ret i8 %C
diff --git a/test/Transforms/InstCombine/zext-or-icmp.ll b/test/Transforms/InstCombine/zext-or-icmp.ll
index ddc60834f586..3a27f9a124cb 100644
--- a/test/Transforms/InstCombine/zext-or-icmp.ll
+++ b/test/Transforms/InstCombine/zext-or-icmp.ll
@@ -10,19 +10,19 @@ entry:
 	%tmp3 = and i32 %tmp2, 2		; <i32> [#uses=1]
 	%tmp5 = and i32 %blk_i, 1		; <i32> [#uses=1]
 	%tmp6 = or i32 %tmp3, %tmp5		; <i32> [#uses=1]
-	%tmp8 = getelementptr %struct.FooBar* %up, i32 0, i32 7		; <i16*> [#uses=1]
-	%tmp9 = load i16* %tmp8, align 1		; <i16> [#uses=1]
+	%tmp8 = getelementptr %struct.FooBar, %struct.FooBar* %up, i32 0, i32 7		; <i16*> [#uses=1]
+	%tmp9 = load i16, i16* %tmp8, align 1		; <i16> [#uses=1]
 	%tmp910 = zext i16 %tmp9 to i32		; <i32> [#uses=1]
-	%tmp12 = getelementptr [4 x i8]* @some_idx, i32 0, i32 %tmp6		; <i8*> [#uses=1]
-	%tmp13 = load i8* %tmp12, align 1		; <i8> [#uses=1]
+	%tmp12 = getelementptr [4 x i8], [4 x i8]* @some_idx, i32 0, i32 %tmp6		; <i8*> [#uses=1]
+	%tmp13 = load i8, i8* %tmp12, align 1		; <i8> [#uses=1]
 	%tmp1314 = zext i8 %tmp13 to i32		; <i32> [#uses=1]
 	%tmp151 = lshr i32 %tmp910, %tmp1314		; <i32> [#uses=1]
 	%tmp1516 = trunc i32 %tmp151 to i8		; <i8> [#uses=1]
-	%tmp18 = getelementptr %struct.FooBar* %up, i32 0, i32 0		; <i8*> [#uses=1]
-	%tmp19 = load i8* %tmp18, align 1		; <i8> [#uses=1]
+	%tmp18 = getelementptr %struct.FooBar, %struct.FooBar* %up, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp19 = load i8, i8* %tmp18, align 1		; <i8> [#uses=1]
 	%tmp22 = and i8 %tmp1516, %tmp19		; <i8> [#uses=1]
-	%tmp24 = getelementptr %struct.FooBar* %up, i32 0, i32 0		; <i8*> [#uses=1]
-	%tmp25 = load i8* %tmp24, align 1		; <i8> [#uses=1]
+	%tmp24 = getelementptr %struct.FooBar, %struct.FooBar* %up, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp25 = load i8, i8* %tmp24, align 1		; <i8> [#uses=1]
 	%tmp26.mask = and i8 %tmp25, 1		; <i8> [#uses=1]
 	%toBool = icmp eq i8 %tmp26.mask, 0		; <i1> [#uses=1]
 	%toBool.not = xor i1 %toBool, true		; <i1> [#uses=1]
diff --git a/test/Transforms/InstMerge/ld_hoist1.ll b/test/Transforms/InstMerge/ld_hoist1.ll
index 715f1b824407..74c8900b8ab1 100644
--- a/test/Transforms/InstMerge/ld_hoist1.ll
+++ b/test/Transforms/InstMerge/ld_hoist1.ll
@@ -15,35 +15,35 @@ for.body.lr.ph:                                   ; preds = %entry
 
 ; CHECK-LABEL: for.body
 ; CHECK: load
-; CHECK:  %2 = getelementptr inbounds i32* %in, i64 %indvars.iv
-; CHECK:  %3 = load i32* %2, align 4
+; CHECK:  %2 = getelementptr inbounds i32, i32* %in, i64 %indvars.iv
+; CHECK:  %3 = load i32, i32* %2, align 4
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.inc
   %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.inc ]
-  %arrayidx = getelementptr inbounds i32* %trigger, i64 %indvars.iv
-  %1 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %trigger, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %1, 0
   br i1 %cmp1, label %if.then, label %if.else
 
 ; CHECK-LABEL: if.then
 if.then:                                          ; preds = %for.body
 ; This load should be hoisted
-  %arrayidx3 = getelementptr inbounds i32* %in, i64 %indvars.iv
-  %2 = load i32* %arrayidx3, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %in, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
   %conv = sitofp i32 %2 to float
   %add = fadd float %conv, 5.000000e-01
-  %arrayidx5 = getelementptr inbounds float* %out, i64 %indvars.iv
+  %arrayidx5 = getelementptr inbounds float, float* %out, i64 %indvars.iv
   store float %add, float* %arrayidx5, align 4
   br label %for.inc
 
 if.else:                                          ; preds = %for.body
-  %arrayidx7 = getelementptr inbounds float* %out, i64 %indvars.iv
-  %3 = load float* %arrayidx7, align 4
+  %arrayidx7 = getelementptr inbounds float, float* %out, i64 %indvars.iv
+  %3 = load float, float* %arrayidx7, align 4
   %div = fdiv float %3, 3.000000e+00
   store float %div, float* %arrayidx7, align 4
 ; This load should be hoisted in spite of store 
-  %arrayidx9 = getelementptr inbounds i32* %in, i64 %indvars.iv
-  %4 = load i32* %arrayidx9, align 4
+  %arrayidx9 = getelementptr inbounds i32, i32* %in, i64 %indvars.iv
+  %4 = load i32, i32* %arrayidx9, align 4
   %conv10 = sitofp i32 %4 to float
   %add13 = fadd float %div, %conv10
   store float %add13, float* %arrayidx7, align 4
diff --git a/test/Transforms/InstMerge/ld_hoist_st_sink.ll b/test/Transforms/InstMerge/ld_hoist_st_sink.ll
index 978160aa002e..1d3f941882e5 100644
--- a/test/Transforms/InstMerge/ld_hoist_st_sink.ll
+++ b/test/Transforms/InstMerge/ld_hoist_st_sink.ll
@@ -8,8 +8,8 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
 define i64 @foo(%struct.node* nocapture readonly %r) nounwind {
 entry:
-  %node.0.in16 = getelementptr inbounds %struct.node* %r, i64 0, i32 2
-  %node.017 = load %struct.node** %node.0.in16, align 8
+  %node.0.in16 = getelementptr inbounds %struct.node, %struct.node* %r, i64 0, i32 2
+  %node.017 = load %struct.node*, %struct.node** %node.0.in16, align 8
   %tobool18 = icmp eq %struct.node* %node.017, null
   br i1 %tobool18, label %while.end, label %while.body.preheader
 
@@ -21,46 +21,46 @@ while.body.preheader:                             ; preds = %entry
 while.body:                                       ; preds = %while.body.preheader, %if.end
   %node.020 = phi %struct.node* [ %node.0, %if.end ], [ %node.017, %while.body.preheader ]
   %sum.019 = phi i64 [ %inc, %if.end ], [ 0, %while.body.preheader ]
-  %orientation = getelementptr inbounds %struct.node* %node.020, i64 0, i32 4
-  %0 = load i64* %orientation, align 8
+  %orientation = getelementptr inbounds %struct.node, %struct.node* %node.020, i64 0, i32 4
+  %0 = load i64, i64* %orientation, align 8
   %cmp = icmp eq i64 %0, 1
   br i1 %cmp, label %if.then, label %if.else
 ; CHECK: if.then
 if.then:                                          ; preds = %while.body
-  %a = getelementptr inbounds %struct.node* %node.020, i64 0, i32 5
+  %a = getelementptr inbounds %struct.node, %struct.node* %node.020, i64 0, i32 5
 ; CHECK-NOT: load %struct.arc
-  %1 = load %struct.arc** %a, align 8
-  %cost = getelementptr inbounds %struct.arc* %1, i64 0, i32 0
-; CHECK-NOT: load i64*
-  %2 = load i64* %cost, align 8
-  %pred = getelementptr inbounds %struct.node* %node.020, i64 0, i32 1
-; CHECK-NOT: load %struct.node**
-  %3 = load %struct.node** %pred, align 8
-  %p = getelementptr inbounds %struct.node* %3, i64 0, i32 6
-; CHECK-NOT: load i64*
-  %4 = load i64* %p, align 8
+  %1 = load %struct.arc*, %struct.arc** %a, align 8
+  %cost = getelementptr inbounds %struct.arc, %struct.arc* %1, i64 0, i32 0
+; CHECK-NOT: load i64, i64*
+  %2 = load i64, i64* %cost, align 8
+  %pred = getelementptr inbounds %struct.node, %struct.node* %node.020, i64 0, i32 1
+; CHECK-NOT: load %struct.node*, %struct.node**
+  %3 = load %struct.node*, %struct.node** %pred, align 8
+  %p = getelementptr inbounds %struct.node, %struct.node* %3, i64 0, i32 6
+; CHECK-NOT: load i64, i64*
+  %4 = load i64, i64* %p, align 8
   %add = add nsw i64 %4, %2
-  %p1 = getelementptr inbounds %struct.node* %node.020, i64 0, i32 6
+  %p1 = getelementptr inbounds %struct.node, %struct.node* %node.020, i64 0, i32 6
 ; CHECK-NOT: store i64
   store i64 %add, i64* %p1, align 8
   br label %if.end
 
 ; CHECK: if.else
 if.else:                                          ; preds = %while.body
-  %pred2 = getelementptr inbounds %struct.node* %node.020, i64 0, i32 1
-; CHECK-NOT: load %struct.node**
-  %5 = load %struct.node** %pred2, align 8
-  %p3 = getelementptr inbounds %struct.node* %5, i64 0, i32 6
-; CHECK-NOT: load i64*
-  %6 = load i64* %p3, align 8
-  %a4 = getelementptr inbounds %struct.node* %node.020, i64 0, i32 5
-; CHECK-NOT: load %struct.arc**
-  %7 = load %struct.arc** %a4, align 8
-  %cost5 = getelementptr inbounds %struct.arc* %7, i64 0, i32 0
-; CHECK-NOT: load i64*
-  %8 = load i64* %cost5, align 8
+  %pred2 = getelementptr inbounds %struct.node, %struct.node* %node.020, i64 0, i32 1
+; CHECK-NOT: load %struct.node*, %struct.node**
+  %5 = load %struct.node*, %struct.node** %pred2, align 8
+  %p3 = getelementptr inbounds %struct.node, %struct.node* %5, i64 0, i32 6
+; CHECK-NOT: load i64, i64*
+  %6 = load i64, i64* %p3, align 8
+  %a4 = getelementptr inbounds %struct.node, %struct.node* %node.020, i64 0, i32 5
+; CHECK-NOT: load %struct.arc*, %struct.arc**
+  %7 = load %struct.arc*, %struct.arc** %a4, align 8
+  %cost5 = getelementptr inbounds %struct.arc, %struct.arc* %7, i64 0, i32 0
+; CHECK-NOT: load i64, i64*
+  %8 = load i64, i64* %cost5, align 8
   %sub = sub nsw i64 %6, %8
-  %p6 = getelementptr inbounds %struct.node* %node.020, i64 0, i32 6
+  %p6 = getelementptr inbounds %struct.node, %struct.node* %node.020, i64 0, i32 6
 ; CHECK-NOT: store i64
   store i64 %sub, i64* %p6, align 8
   br label %if.end
@@ -69,8 +69,8 @@ if.else:                                          ; preds = %while.body
 if.end:                                           ; preds = %if.else, %if.then
 ; CHECK: store
   %inc = add nsw i64 %sum.019, 1
-  %node.0.in = getelementptr inbounds %struct.node* %node.020, i64 0, i32 2
-  %node.0 = load %struct.node** %node.0.in, align 8
+  %node.0.in = getelementptr inbounds %struct.node, %struct.node* %node.020, i64 0, i32 2
+  %node.0 = load %struct.node*, %struct.node** %node.0.in, align 8
   %tobool = icmp eq %struct.node* %node.0, null
   br i1 %tobool, label %while.end.loopexit, label %while.body
 
diff --git a/test/Transforms/InstMerge/st_sink_barrier_call.ll b/test/Transforms/InstMerge/st_sink_barrier_call.ll
index c158b006bee0..cdcc34624d5c 100644
--- a/test/Transforms/InstMerge/st_sink_barrier_call.ll
+++ b/test/Transforms/InstMerge/st_sink_barrier_call.ll
@@ -10,27 +10,27 @@ declare i32 @foo(i32 %x)
 ; Function Attrs: nounwind uwtable
 define void @sink_store(%struct.node* nocapture %r, i32 %index) {
 entry:
-  %node.0.in16 = getelementptr inbounds %struct.node* %r, i64 0, i32 2
-  %node.017 = load %struct.node** %node.0.in16, align 8
+  %node.0.in16 = getelementptr inbounds %struct.node, %struct.node* %r, i64 0, i32 2
+  %node.017 = load %struct.node*, %struct.node** %node.0.in16, align 8
   %index.addr = alloca i32, align 4
   store i32 %index, i32* %index.addr, align 4
-  %0 = load i32* %index.addr, align 4
+  %0 = load i32, i32* %index.addr, align 4
   %cmp = icmp slt i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
 ; CHECK: if.then
 if.then:                                          ; preds = %entry
-  %1 = load i32* %index.addr, align 4
-  %p1 = getelementptr inbounds %struct.node* %node.017, i32 0, i32 6
+  %1 = load i32, i32* %index.addr, align 4
+  %p1 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 0, i32 6
   ; CHECK: store i32
   store i32 %1, i32* %p1, align 4
   br label %if.end
   
 ; CHECK: if.else
 if.else:                                          ; preds = %entry
-  %2 = load i32* %index.addr, align 4
+  %2 = load i32, i32* %index.addr, align 4
   %add = add nsw i32 %2, 1
-  %p3 = getelementptr inbounds %struct.node* %node.017, i32 0, i32 6
+  %p3 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 0, i32 6
   ; CHECK: store i32
   store i32 %add, i32* %p3, align 4
   call i32 @foo(i32 5)				  ;barrier
diff --git a/test/Transforms/InstMerge/st_sink_bugfix_22613.ll b/test/Transforms/InstMerge/st_sink_bugfix_22613.ll
index 6b817f20d16b..575f239efb23 100644
--- a/test/Transforms/InstMerge/st_sink_bugfix_22613.ll
+++ b/test/Transforms/InstMerge/st_sink_bugfix_22613.ll
@@ -20,52 +20,52 @@ target triple = "x86_64-unknown-linux-gnu"
 @a = common global i32 0, align 4
 
 ; Function Attrs: nounwind uwtable
-define void @fn1() #0 {
+define void @fn1() {
 entry:
   store i32 0, i32* @d, align 4
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc8, %entry
-  %0 = load i32* @d, align 4
+  %0 = load i32, i32* @d, align 4
   %cmp = icmp slt i32 %0, 2
   br i1 %cmp, label %for.body, label %for.end10
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* @d, align 4
+  %1 = load i32, i32* @d, align 4
   %idxprom = sext i32 %1 to i64
-  %2 = load i32* @b, align 4
+  %2 = load i32, i32* @b, align 4
   %idxprom1 = sext i32 %2 to i64
-  %arrayidx = getelementptr inbounds [1 x [3 x i8]]* @f, i32 0, i64 %idxprom1
-  %arrayidx2 = getelementptr inbounds [3 x i8]* %arrayidx, i32 0, i64 %idxprom
+  %arrayidx = getelementptr inbounds [1 x [3 x i8]], [1 x [3 x i8]]* @f, i32 0, i64 %idxprom1
+  %arrayidx2 = getelementptr inbounds [3 x i8], [3 x i8]* %arrayidx, i32 0, i64 %idxprom
   store i8 0, i8* %arrayidx2, align 1
   store i32 0, i32* @e, align 4
   br label %for.cond3
 
 for.cond3:                                        ; preds = %for.inc, %for.body
-  %3 = load i32* @e, align 4
+  %3 = load i32, i32* @e, align 4
   %cmp4 = icmp slt i32 %3, 3
   br i1 %cmp4, label %for.body5, label %for.end
 
 for.body5:                                        ; preds = %for.cond3
-  %4 = load i32* @c, align 4
+  %4 = load i32, i32* @c, align 4
   %tobool = icmp ne i32 %4, 0
   br i1 %tobool, label %if.then, label %if.end
 
 if.then:                                          ; preds = %for.body5
-  %5 = load i32* @a, align 4
+  %5 = load i32, i32* @a, align 4
   %dec = add nsw i32 %5, -1
   store i32 %dec, i32* @a, align 4
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %for.body5
-  %6 = load i32* @e, align 4
+  %6 = load i32, i32* @e, align 4
   %idxprom6 = sext i32 %6 to i64
-  %arrayidx7 = getelementptr inbounds [3 x i8]* getelementptr inbounds ([1 x [3 x i8]]* @f, i32 0, i64 0), i32 0, i64 %idxprom6
+  %arrayidx7 = getelementptr inbounds [3 x i8], [3 x i8]* getelementptr inbounds ([1 x [3 x i8]], [1 x [3 x i8]]* @f, i32 0, i64 0), i32 0, i64 %idxprom6
   store i8 1, i8* %arrayidx7, align 1
   br label %for.inc
 
 for.inc:                                          ; preds = %if.end
-  %7 = load i32* @e, align 4
+  %7 = load i32, i32* @e, align 4
   %inc = add nsw i32 %7, 1
   store i32 %inc, i32* @e, align 4
   br label %for.cond3
@@ -74,7 +74,7 @@ for.end:                                          ; preds = %for.cond3
   br label %for.inc8
 
 for.inc8:                                         ; preds = %for.end
-  %8 = load i32* @d, align 4
+  %8 = load i32, i32* @d, align 4
   %inc9 = add nsw i32 %8, 1
   store i32 %inc9, i32* @d, align 4
   br label %for.cond
@@ -84,18 +84,18 @@ for.end10:                                        ; preds = %for.cond
 }
 
 ; Function Attrs: nounwind uwtable
-define i32 @main() #0 {
+define i32 @main() {
 entry:
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
   call void @fn1()
-  %0 = load i8* getelementptr inbounds ([1 x [3 x i8]]* @f, i32 0, i64 0, i64 1), align 1
+  %0 = load i8, i8* getelementptr inbounds ([1 x [3 x i8]], [1 x [3 x i8]]* @f, i32 0, i64 0, i64 1), align 1
   %conv = sext i8 %0 to i32
   %cmp = icmp ne i32 %conv, 1
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  call void @abort() #2
+  call void @abort()
   unreachable
 
 if.end:                                           ; preds = %entry
@@ -103,12 +103,4 @@ if.end:                                           ; preds = %entry
 }
 
 ; Function Attrs: noreturn nounwind
-declare void @abort() #1
-
-attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
-attributes #1 = { noreturn nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
-attributes #2 = { noreturn nounwind }
-
-!llvm.ident = !{!0}
-
-!0 = !{!"clang version 3.7.0 (trunk 229288) (llvm/trunk 229286:229290M)"}
+declare void @abort()
diff --git a/test/Transforms/InstMerge/st_sink_no_barrier_call.ll b/test/Transforms/InstMerge/st_sink_no_barrier_call.ll
index 72f1fdf77371..0ad90f8581eb 100644
--- a/test/Transforms/InstMerge/st_sink_no_barrier_call.ll
+++ b/test/Transforms/InstMerge/st_sink_no_barrier_call.ll
@@ -10,27 +10,27 @@ declare i32 @foo(i32 %x) #0
 ; Function Attrs: nounwind uwtable
 define void @sink_store(%struct.node* nocapture %r, i32 %index) {
 entry:
-  %node.0.in16 = getelementptr inbounds %struct.node* %r, i64 0, i32 2
-  %node.017 = load %struct.node** %node.0.in16, align 8
+  %node.0.in16 = getelementptr inbounds %struct.node, %struct.node* %r, i64 0, i32 2
+  %node.017 = load %struct.node*, %struct.node** %node.0.in16, align 8
   %index.addr = alloca i32, align 4
   store i32 %index, i32* %index.addr, align 4
-  %0 = load i32* %index.addr, align 4
+  %0 = load i32, i32* %index.addr, align 4
   %cmp = icmp slt i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
 ; CHECK: if.then
 if.then:                                          ; preds = %entry
-  %1 = load i32* %index.addr, align 4
-  %p1 = getelementptr inbounds %struct.node* %node.017, i32 0, i32 6
+  %1 = load i32, i32* %index.addr, align 4
+  %p1 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 0, i32 6
   ; CHECK-NOT: store i32
   store i32 %1, i32* %p1, align 4
   br label %if.end
   
 ; CHECK: if.else
 if.else:                                          ; preds = %entry
-  %2 = load i32* %index.addr, align 4
+  %2 = load i32, i32* %index.addr, align 4
   %add = add nsw i32 %2, 1
-  %p3 = getelementptr inbounds %struct.node* %node.017, i32 0, i32 6
+  %p3 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 0, i32 6
   ; CHECK-NOT: store i32
   store i32 %add, i32* %p3, align 4
   call i32 @foo(i32 5)				  ;not a barrier
diff --git a/test/Transforms/InstMerge/st_sink_no_barrier_load.ll b/test/Transforms/InstMerge/st_sink_no_barrier_load.ll
index 5be0c254ba6f..b7236e4c6a06 100644
--- a/test/Transforms/InstMerge/st_sink_no_barrier_load.ll
+++ b/test/Transforms/InstMerge/st_sink_no_barrier_load.ll
@@ -8,30 +8,30 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 ; Function Attrs: nounwind uwtable
 define void @sink_store(%struct.node* nocapture %r, i32 %index) {
 entry:
-  %node.0.in16 = getelementptr inbounds %struct.node* %r, i64 0, i32 2
-  %node.017 = load %struct.node** %node.0.in16, align 8
+  %node.0.in16 = getelementptr inbounds %struct.node, %struct.node* %r, i64 0, i32 2
+  %node.017 = load %struct.node*, %struct.node** %node.0.in16, align 8
   %index.addr = alloca i32, align 4
   store i32 %index, i32* %index.addr, align 4
-  %0 = load i32* %index.addr, align 4
+  %0 = load i32, i32* %index.addr, align 4
   %cmp = icmp slt i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
 ; CHECK: if.then
 if.then:                                          ; preds = %entry
-  %1 = load i32* %index.addr, align 4
-  %p1 = getelementptr inbounds %struct.node* %node.017, i32 0, i32 6
+  %1 = load i32, i32* %index.addr, align 4
+  %p1 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 0, i32 6
   ; CHECK-NOT: store i32
   store i32 %1, i32* %p1, align 4
-  %p2 = getelementptr inbounds %struct.node* %node.017, i32 5, i32 6
-  ; CHECK: load i32*
-  %not_barrier = load i32 * %p2, align 4
+  %p2 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 5, i32 6
+  ; CHECK: load i32, i32*
+  %not_barrier = load i32 , i32 * %p2, align 4
   br label %if.end
 
 ; CHECK: if.else
 if.else:                                          ; preds = %entry
-  %2 = load i32* %index.addr, align 4
+  %2 = load i32, i32* %index.addr, align 4
   %add = add nsw i32 %2, 1
-  %p3 = getelementptr inbounds %struct.node* %node.017, i32 0, i32 6
+  %p3 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 0, i32 6
   ; CHECK-NOT: store i32
   store i32 %add, i32* %p3, align 4
   br label %if.end
diff --git a/test/Transforms/InstMerge/st_sink_no_barrier_store.ll b/test/Transforms/InstMerge/st_sink_no_barrier_store.ll
index 06e2b63ca3ed..e13f28aa5e17 100644
--- a/test/Transforms/InstMerge/st_sink_no_barrier_store.ll
+++ b/test/Transforms/InstMerge/st_sink_no_barrier_store.ll
@@ -8,29 +8,29 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 ; Function Attrs: nounwind uwtable
 define void @sink_store(%struct.node* nocapture %r, i32 %index) {
 entry:
-  %node.0.in16 = getelementptr inbounds %struct.node* %r, i64 0, i32 2
-  %node.017 = load %struct.node** %node.0.in16, align 8
+  %node.0.in16 = getelementptr inbounds %struct.node, %struct.node* %r, i64 0, i32 2
+  %node.017 = load %struct.node*, %struct.node** %node.0.in16, align 8
   %index.addr = alloca i32, align 4
   store i32 %index, i32* %index.addr, align 4
-  %0 = load i32* %index.addr, align 4
+  %0 = load i32, i32* %index.addr, align 4
   %cmp = icmp slt i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
 ; CHECK: if.then
 if.then:                                          ; preds = %entry
-  %1 = load i32* %index.addr, align 4
-  %p1 = getelementptr inbounds %struct.node* %node.017, i32 0, i32 6
+  %1 = load i32, i32* %index.addr, align 4
+  %p1 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 0, i32 6
   ; CHECK-NOT: store i32
   store i32 %1, i32* %p1, align 4
   br label %if.end
 
 ; CHECK: if.else
 if.else:                                          ; preds = %entry
-  %2 = load i32* %index.addr, align 4
+  %2 = load i32, i32* %index.addr, align 4
   %add = add nsw i32 %2, 1
-  %p2 = getelementptr inbounds %struct.node* %node.017, i32 0, i32 6
+  %p2 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 0, i32 6
   store i32 %add, i32* %p2, align 4
-  %p3 = getelementptr inbounds %struct.node* %node.017, i32 5, i32 6
+  %p3 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 5, i32 6
   ; CHECK: store i32
   store i32 %add, i32* %p3, align 4  			  ; This is not a barrier
   br label %if.end
diff --git a/test/Transforms/InstMerge/st_sink_two_stores.ll b/test/Transforms/InstMerge/st_sink_two_stores.ll
index 1f7c6aa478ba..5b5582f438c8 100644
--- a/test/Transforms/InstMerge/st_sink_two_stores.ll
+++ b/test/Transforms/InstMerge/st_sink_two_stores.ll
@@ -8,33 +8,33 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 ; Function Attrs: nounwind uwtable
 define void @sink_store(%struct.node* nocapture %r, i32 %index) {
 entry:
-  %node.0.in16 = getelementptr inbounds %struct.node* %r, i64 0, i32 2
-  %node.017 = load %struct.node** %node.0.in16, align 8
+  %node.0.in16 = getelementptr inbounds %struct.node, %struct.node* %r, i64 0, i32 2
+  %node.017 = load %struct.node*, %struct.node** %node.0.in16, align 8
   %index.addr = alloca i32, align 4
   store i32 %index, i32* %index.addr, align 4
-  %0 = load i32* %index.addr, align 4
+  %0 = load i32, i32* %index.addr, align 4
   %cmp = icmp slt i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
 ; CHECK: if.then
 if.then:                                          ; preds = %entry
-  %1 = load i32* %index.addr, align 4
-  %p1 = getelementptr inbounds %struct.node* %node.017, i32 0, i32 6
+  %1 = load i32, i32* %index.addr, align 4
+  %p1 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 0, i32 6
   ; CHECK-NOT: store i32
   store i32 %1, i32* %p1, align 4
-  %p2 = getelementptr inbounds %struct.node* %node.017, i32 4, i32 6
+  %p2 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 4, i32 6
   ; CHECK-NOT: store i32
   store i32 %1, i32* %p2, align 4
   br label %if.end
 
 ; CHECK: if.else
 if.else:                                          ; preds = %entry
-  %2 = load i32* %index.addr, align 4
+  %2 = load i32, i32* %index.addr, align 4
   %add = add nsw i32 %2, 1
-  %p3 = getelementptr inbounds %struct.node* %node.017, i32 0, i32 6
+  %p3 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 0, i32 6
   ; CHECK-NOT: store i32
   store i32 %add, i32* %p3, align 4
-  %p4 = getelementptr inbounds %struct.node* %node.017, i32 4, i32 6
+  %p4 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 4, i32 6
   ; CHECK-NOT: store i32
   store i32 %2, i32* %p4, align 4  
   br label %if.end
diff --git a/test/Transforms/InstMerge/st_sink_with_barrier.ll b/test/Transforms/InstMerge/st_sink_with_barrier.ll
index d4efaa7efff7..a05ae88e3847 100644
--- a/test/Transforms/InstMerge/st_sink_with_barrier.ll
+++ b/test/Transforms/InstMerge/st_sink_with_barrier.ll
@@ -7,30 +7,30 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 ; Function Attrs: nounwind uwtable
 define void @sink_store(%struct.node* nocapture %r, i32 %index) {
 entry:
-  %node.0.in16 = getelementptr inbounds %struct.node* %r, i64 0, i32 2
-  %node.017 = load %struct.node** %node.0.in16, align 8
+  %node.0.in16 = getelementptr inbounds %struct.node, %struct.node* %r, i64 0, i32 2
+  %node.017 = load %struct.node*, %struct.node** %node.0.in16, align 8
   %index.addr = alloca i32, align 4
   store i32 %index, i32* %index.addr, align 4
-  %0 = load i32* %index.addr, align 4
+  %0 = load i32, i32* %index.addr, align 4
   %cmp = icmp slt i32 %0, 0
   br i1 %cmp, label %if.then, label %if.else
 
 ; CHECK: if.then
 if.then:                                          ; preds = %entry
-  %1 = load i32* %index.addr, align 4
-  %p1 = getelementptr inbounds %struct.node* %node.017, i32 0, i32 6
+  %1 = load i32, i32* %index.addr, align 4
+  %p1 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 0, i32 6
   ; CHECK: store i32
   store i32 %1, i32* %p1, align 4
-  %p2 = getelementptr inbounds %struct.node* %node.017, i32 0, i32 6
-  ; CHECK: load i32*
-  %barrier = load i32 * %p2, align 4
+  %p2 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 0, i32 6
+  ; CHECK: load i32, i32*
+  %barrier = load i32 , i32 * %p2, align 4
   br label %if.end
 
 ; CHECK: if.else
 if.else:                                          ; preds = %entry
-  %2 = load i32* %index.addr, align 4
+  %2 = load i32, i32* %index.addr, align 4
   %add = add nsw i32 %2, 1
-  %p3 = getelementptr inbounds %struct.node* %node.017, i32 0, i32 6
+  %p3 = getelementptr inbounds %struct.node, %struct.node* %node.017, i32 0, i32 6
   ; CHECK: store i32
   store i32 %add, i32* %p3, align 4
   br label %if.end
diff --git a/test/Transforms/InstSimplify/2011-10-27-BinOpCrash.ll b/test/Transforms/InstSimplify/2011-10-27-BinOpCrash.ll
index a10081a42dd5..5380a7bb6171 100644
--- a/test/Transforms/InstSimplify/2011-10-27-BinOpCrash.ll
+++ b/test/Transforms/InstSimplify/2011-10-27-BinOpCrash.ll
@@ -6,7 +6,7 @@
 @_ZN11xercesc_2_5L15gCombiningCharsE = external constant [163 x i16], align 2
 
 define i32 @_ZN11xercesc_2_515XMLRangeFactory11buildRangesEv(i32 %x) {
-  %a = add i32 %x, add (i32 add (i32 ashr (i32 add (i32 mul (i32 ptrtoint ([32 x i16]* @_ZN11xercesc_2_5L11gDigitCharsE to i32), i32 -1), i32 ptrtoint (i16* getelementptr inbounds ([32 x i16]* @_ZN11xercesc_2_5L11gDigitCharsE, i32 0, i32 30) to i32)), i32 1), i32 ashr (i32 add (i32 mul (i32 ptrtoint ([7 x i16]* @_ZN11xercesc_2_5L17gIdeographicCharsE to i32), i32 -1), i32 ptrtoint (i16* getelementptr inbounds ([7 x i16]* @_ZN11xercesc_2_5L17gIdeographicCharsE, i32 0, i32 4) to i32)), i32 1)), i32 8)
+  %a = add i32 %x, add (i32 add (i32 ashr (i32 add (i32 mul (i32 ptrtoint ([32 x i16]* @_ZN11xercesc_2_5L11gDigitCharsE to i32), i32 -1), i32 ptrtoint (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @_ZN11xercesc_2_5L11gDigitCharsE, i32 0, i32 30) to i32)), i32 1), i32 ashr (i32 add (i32 mul (i32 ptrtoint ([7 x i16]* @_ZN11xercesc_2_5L17gIdeographicCharsE to i32), i32 -1), i32 ptrtoint (i16* getelementptr inbounds ([7 x i16], [7 x i16]* @_ZN11xercesc_2_5L17gIdeographicCharsE, i32 0, i32 4) to i32)), i32 1)), i32 8)
   %b = add i32 %a, %x
   ret i32 %b
 }
diff --git a/test/Transforms/InstSimplify/call-callconv.ll b/test/Transforms/InstSimplify/call-callconv.ll
index e475be781db9..56a8e44328fe 100644
--- a/test/Transforms/InstSimplify/call-callconv.ll
+++ b/test/Transforms/InstSimplify/call-callconv.ll
@@ -29,7 +29,7 @@ declare arm_aapcscc i32 @labs(i32) nounwind readnone
 
 define arm_aapcscc i32 @_strlen1() {
 ; CHECK: _strlen1
-  %call = tail call arm_aapcscc i32 @strlen(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0))
+  %call = tail call arm_aapcscc i32 @strlen(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0))
   ret i32 %call
 ; CHECK: ret i32 3
 }
@@ -42,7 +42,7 @@ define arm_aapcscc zeroext i1 @_strlen2(i8* %str) {
   %cmp = icmp ne i32 %call, 0
   ret i1 %cmp
 
-; CHECK: %[[STRLENFIRST:.*]] = load i8* %str
+; CHECK: %[[STRLENFIRST:.*]] = load i8, i8* %str
 ; CHECK: %[[CMP:.*]] = icmp ne i8 %[[STRLENFIRST]], 0
 ; CHECK: ret i1 %[[CMP]]
 }
diff --git a/test/Transforms/InstSimplify/call.ll b/test/Transforms/InstSimplify/call.ll
index fd854c5b4662..465529aef66a 100644
--- a/test/Transforms/InstSimplify/call.ll
+++ b/test/Transforms/InstSimplify/call.ll
@@ -1,6 +1,9 @@
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 declare {i8, i1} @llvm.uadd.with.overflow.i8(i8 %a, i8 %b)
+declare {i8, i1} @llvm.usub.with.overflow.i8(i8 %a, i8 %b)
+declare {i8, i1} @llvm.ssub.with.overflow.i8(i8 %a, i8 %b)
+declare {i8, i1} @llvm.umul.with.overflow.i8(i8 %a, i8 %b)
 
 define i1 @test_uadd1() {
 ; CHECK-LABEL: @test_uadd1(
@@ -18,6 +21,27 @@ define i8 @test_uadd2() {
 ; CHECK-NEXT: ret i8 42
 }
 
+define {i8, i1} @test_usub1(i8 %V) {
+; CHECK-LABEL: @test_usub1(
+  %x = call {i8, i1} @llvm.usub.with.overflow.i8(i8 %V, i8 %V)
+  ret {i8, i1} %x
+; CHECK-NEXT: ret { i8, i1 } zeroinitializer
+}
+
+define {i8, i1} @test_ssub1(i8 %V) {
+; CHECK-LABEL: @test_ssub1(
+  %x = call {i8, i1} @llvm.ssub.with.overflow.i8(i8 %V, i8 %V)
+  ret {i8, i1} %x
+; CHECK-NEXT: ret { i8, i1 } zeroinitializer
+}
+
+define {i8, i1} @test_umul1(i8 %V) {
+; CHECK-LABEL: @test_umul1(
+  %x = call {i8, i1} @llvm.umul.with.overflow.i8(i8 %V, i8 0)
+  ret {i8, i1} %x
+; CHECK-NEXT: ret { i8, i1 } zeroinitializer
+}
+
 declare i256 @llvm.cttz.i256(i256 %src, i1 %is_zero_undef)
 
 define i256 @test_cttz() {
@@ -109,7 +133,7 @@ entry:
   br i1 %cmp, label %cast.end, label %cast.notnull
 
 cast.notnull:                                     ; preds = %entry
-  %add.ptr = getelementptr inbounds i8* %call, i64 4
+  %add.ptr = getelementptr inbounds i8, i8* %call, i64 4
   br label %cast.end
 
 cast.end:                                         ; preds = %cast.notnull, %entry
@@ -132,7 +156,7 @@ entry:
   br i1 %cmp, label %cast.end, label %cast.notnull
 
 cast.notnull:                                     ; preds = %entry
-  %add.ptr = getelementptr inbounds i8* %call, i64 4
+  %add.ptr = getelementptr inbounds i8, i8* %call, i64 4
   br label %cast.end
 
 cast.end:                                         ; preds = %cast.notnull, %entry
@@ -152,7 +176,7 @@ entry:
   br i1 %cmp, label %cast.end, label %cast.notnull
 
 cast.notnull:                                     ; preds = %entry
-  %add.ptr = getelementptr inbounds i8* %call, i64 4
+  %add.ptr = getelementptr inbounds i8, i8* %call, i64 4
   br label %cast.end
 
 cast.end:                                         ; preds = %cast.notnull, %entry
diff --git a/test/Transforms/InstSimplify/compare.ll b/test/Transforms/InstSimplify/compare.ll
index 10c7ca6754e3..07c90d8f1eb8 100644
--- a/test/Transforms/InstSimplify/compare.ll
+++ b/test/Transforms/InstSimplify/compare.ll
@@ -24,7 +24,7 @@ define i1 @bitcast() {
 define i1 @gep() {
 ; CHECK-LABEL: @gep(
   %a = alloca [3 x i8], align 8
-  %x = getelementptr inbounds [3 x i8]* %a, i32 0, i32 0
+  %x = getelementptr inbounds [3 x i8], [3 x i8]* %a, i32 0, i32 0
   %cmp = icmp eq i8* %x, null
   ret i1 %cmp
 ; CHECK-NEXT: ret i1 false
@@ -33,8 +33,8 @@ define i1 @gep() {
 define i1 @gep2() {
 ; CHECK-LABEL: @gep2(
   %a = alloca [3 x i8], align 8
-  %x = getelementptr inbounds [3 x i8]* %a, i32 0, i32 0
-  %y = getelementptr inbounds [3 x i8]* %a, i32 0, i32 0
+  %x = getelementptr inbounds [3 x i8], [3 x i8]* %a, i32 0, i32 0
+  %y = getelementptr inbounds [3 x i8], [3 x i8]* %a, i32 0, i32 0
   %cmp = icmp eq i8* %x, %y
   ret i1 %cmp
 ; CHECK-NEXT: ret i1 true
@@ -48,8 +48,8 @@ define i1 @gep2() {
 define i1 @gep3() {
 ; CHECK-LABEL: @gep3(
   %x = alloca %gept, align 8
-  %a = getelementptr %gept* %x, i64 0, i32 0
-  %b = getelementptr %gept* %x, i64 0, i32 1
+  %a = getelementptr %gept, %gept* %x, i64 0, i32 0
+  %b = getelementptr %gept, %gept* %x, i64 0, i32 1
   %equal = icmp eq i32* %a, %b
   ret i1 %equal
 ; CHECK-NEXT: ret i1 false
@@ -58,8 +58,8 @@ define i1 @gep3() {
 define i1 @gep4() {
 ; CHECK-LABEL: @gep4(
   %x = alloca %gept, align 8
-  %a = getelementptr %gept* @gepy, i64 0, i32 0
-  %b = getelementptr %gept* @gepy, i64 0, i32 1
+  %a = getelementptr %gept, %gept* @gepy, i64 0, i32 0
+  %b = getelementptr %gept, %gept* @gepy, i64 0, i32 1
   %equal = icmp eq i32* %a, %b
   ret i1 %equal
 ; CHECK-NEXT: ret i1 false
@@ -68,8 +68,8 @@ define i1 @gep4() {
 define i1 @gep5() {
 ; CHECK-LABEL: @gep5(
   %x = alloca %gept, align 8
-  %a = getelementptr inbounds %gept* %x, i64 0, i32 1
-  %b = getelementptr %gept* @gepy, i64 0, i32 0
+  %a = getelementptr inbounds %gept, %gept* %x, i64 0, i32 1
+  %b = getelementptr %gept, %gept* @gepy, i64 0, i32 0
   %equal = icmp eq i32* %a, %b
   ret i1 %equal
 ; CHECK-NEXT: ret i1 false
@@ -78,8 +78,8 @@ define i1 @gep5() {
 define i1 @gep6(%gept* %x) {
 ; Same as @gep3 but potentially null.
 ; CHECK-LABEL: @gep6(
-  %a = getelementptr %gept* %x, i64 0, i32 0
-  %b = getelementptr %gept* %x, i64 0, i32 1
+  %a = getelementptr %gept, %gept* %x, i64 0, i32 0
+  %b = getelementptr %gept, %gept* %x, i64 0, i32 1
   %equal = icmp eq i32* %a, %b
   ret i1 %equal
 ; CHECK-NEXT: ret i1 false
@@ -87,8 +87,8 @@ define i1 @gep6(%gept* %x) {
 
 define i1 @gep7(%gept* %x) {
 ; CHECK-LABEL: @gep7(
-  %a = getelementptr %gept* %x, i64 0, i32 0
-  %b = getelementptr %gept* @gepz, i64 0, i32 0
+  %a = getelementptr %gept, %gept* %x, i64 0, i32 0
+  %b = getelementptr %gept, %gept* @gepz, i64 0, i32 0
   %equal = icmp eq i32* %a, %b
   ret i1 %equal
 ; CHECK: ret i1 %equal
@@ -96,8 +96,8 @@ define i1 @gep7(%gept* %x) {
 
 define i1 @gep8(%gept* %x) {
 ; CHECK-LABEL: @gep8(
-  %a = getelementptr %gept* %x, i32 1
-  %b = getelementptr %gept* %x, i32 -1
+  %a = getelementptr %gept, %gept* %x, i32 1
+  %b = getelementptr %gept, %gept* %x, i32 -1
   %equal = icmp ugt %gept* %a, %b
   ret i1 %equal
 ; CHECK: ret i1 %equal
@@ -109,14 +109,14 @@ define i1 @gep9(i8* %ptr) {
 ; CHECK: ret i1 true
 
 entry:
-  %first1 = getelementptr inbounds i8* %ptr, i32 0
-  %first2 = getelementptr inbounds i8* %first1, i32 1
-  %first3 = getelementptr inbounds i8* %first2, i32 2
-  %first4 = getelementptr inbounds i8* %first3, i32 4
-  %last1 = getelementptr inbounds i8* %first2, i32 48
-  %last2 = getelementptr inbounds i8* %last1, i32 8
-  %last3 = getelementptr inbounds i8* %last2, i32 -4
-  %last4 = getelementptr inbounds i8* %last3, i32 -4
+  %first1 = getelementptr inbounds i8, i8* %ptr, i32 0
+  %first2 = getelementptr inbounds i8, i8* %first1, i32 1
+  %first3 = getelementptr inbounds i8, i8* %first2, i32 2
+  %first4 = getelementptr inbounds i8, i8* %first3, i32 4
+  %last1 = getelementptr inbounds i8, i8* %first2, i32 48
+  %last2 = getelementptr inbounds i8, i8* %last1, i32 8
+  %last3 = getelementptr inbounds i8, i8* %last2, i32 -4
+  %last4 = getelementptr inbounds i8, i8* %last3, i32 -4
   %first.int = ptrtoint i8* %first4 to i32
   %last.int = ptrtoint i8* %last4 to i32
   %cmp = icmp ne i32 %last.int, %first.int
@@ -129,10 +129,10 @@ define i1 @gep10(i8* %ptr) {
 ; CHECK: ret i1 true
 
 entry:
-  %first1 = getelementptr inbounds i8* %ptr, i32 -2
-  %first2 = getelementptr inbounds i8* %first1, i32 44
-  %last1 = getelementptr inbounds i8* %ptr, i32 48
-  %last2 = getelementptr inbounds i8* %last1, i32 -6
+  %first1 = getelementptr inbounds i8, i8* %ptr, i32 -2
+  %first2 = getelementptr inbounds i8, i8* %first1, i32 44
+  %last1 = getelementptr inbounds i8, i8* %ptr, i32 48
+  %last2 = getelementptr inbounds i8, i8* %last1, i32 -6
   %first.int = ptrtoint i8* %first2 to i32
   %last.int = ptrtoint i8* %last2 to i32
   %cmp = icmp eq i32 %last.int, %first.int
@@ -145,9 +145,9 @@ define i1 @gep11(i8* %ptr) {
 ; CHECK: ret i1 true
 
 entry:
-  %first1 = getelementptr inbounds i8* %ptr, i32 -2
-  %last1 = getelementptr inbounds i8* %ptr, i32 48
-  %last2 = getelementptr inbounds i8* %last1, i32 -6
+  %first1 = getelementptr inbounds i8, i8* %ptr, i32 -2
+  %last1 = getelementptr inbounds i8, i8* %ptr, i32 48
+  %last2 = getelementptr inbounds i8, i8* %last1, i32 -6
   %cmp = icmp ult i8* %first1, %last2
   ret i1 %cmp
 }
@@ -158,9 +158,9 @@ define i1 @gep12(i8* %ptr) {
 ; CHECK: ret i1 %cmp
 
 entry:
-  %first1 = getelementptr inbounds i8* %ptr, i32 -2
-  %last1 = getelementptr inbounds i8* %ptr, i32 48
-  %last2 = getelementptr inbounds i8* %last1, i32 -6
+  %first1 = getelementptr inbounds i8, i8* %ptr, i32 -2
+  %last1 = getelementptr inbounds i8, i8* %ptr, i32 48
+  %last2 = getelementptr inbounds i8, i8* %last1, i32 -6
   %cmp = icmp slt i8* %first1, %last2
   ret i1 %cmp
 }
@@ -168,7 +168,7 @@ entry:
 define i1 @gep13(i8* %ptr) {
 ; CHECK-LABEL: @gep13(
 ; We can prove this GEP is non-null because it is inbounds.
-  %x = getelementptr inbounds i8* %ptr, i32 1
+  %x = getelementptr inbounds i8, i8* %ptr, i32 1
   %cmp = icmp eq i8* %x, null
   ret i1 %cmp
 ; CHECK-NEXT: ret i1 false
@@ -178,7 +178,7 @@ define i1 @gep14({ {}, i8 }* %ptr) {
 ; CHECK-LABEL: @gep14(
 ; We can't simplify this because the offset of one in the GEP actually doesn't
 ; move the pointer.
-  %x = getelementptr inbounds { {}, i8 }* %ptr, i32 0, i32 1
+  %x = getelementptr inbounds { {}, i8 }, { {}, i8 }* %ptr, i32 0, i32 1
   %cmp = icmp eq i8* %x, null
   ret i1 %cmp
 ; CHECK-NOT: ret i1 false
@@ -188,7 +188,7 @@ define i1 @gep15({ {}, [4 x {i8, i8}]}* %ptr, i32 %y) {
 ; CHECK-LABEL: @gep15(
 ; We can prove this GEP is non-null even though there is a user value, as we
 ; would necessarily violate inbounds on one side or the other.
-  %x = getelementptr inbounds { {}, [4 x {i8, i8}]}* %ptr, i32 0, i32 1, i32 %y, i32 1
+  %x = getelementptr inbounds { {}, [4 x {i8, i8}]}, { {}, [4 x {i8, i8}]}* %ptr, i32 0, i32 1, i32 %y, i32 1
   %cmp = icmp eq i8* %x, null
   ret i1 %cmp
 ; CHECK-NEXT: ret i1 false
@@ -199,7 +199,7 @@ define i1 @gep16(i8* %ptr, i32 %a) {
 ; We can prove this GEP is non-null because it is inbounds and because we know
 ; %b is non-zero even though we don't know its value.
   %b = or i32 %a, 1
-  %x = getelementptr inbounds i8* %ptr, i32 %b
+  %x = getelementptr inbounds i8, i8* %ptr, i32 %b
   %cmp = icmp eq i8* %x, null
   ret i1 %cmp
 ; CHECK-NEXT: ret i1 false
@@ -687,7 +687,7 @@ define <2 x i1> @vectorselectcrash(i32 %arg1) {
 ; PR12013
 define i1 @alloca_compare(i64 %idx) {
   %sv = alloca { i32, i32, [124 x i32] }
-  %1 = getelementptr inbounds { i32, i32, [124 x i32] }* %sv, i32 0, i32 2, i64 %idx
+  %1 = getelementptr inbounds { i32, i32, [124 x i32] }, { i32, i32, [124 x i32] }* %sv, i32 0, i32 2, i64 %idx
   %2 = icmp eq i32* %1, null
   ret i1 %2
   ; CHECK: alloca_compare
@@ -699,7 +699,7 @@ define i1 @infinite_gep() {
   ret i1 1
 
 unreachableblock:
-  %X = getelementptr i32 *%X, i32 1
+  %X = getelementptr i32, i32 *%X, i32 1
   %Y = icmp eq i32* %X, null
   ret i1 %Y
 }
@@ -744,7 +744,7 @@ define i1 @alloca_gep(i64 %a, i64 %b) {
 ; We can prove this GEP is non-null because it is inbounds and the pointer
 ; is non-null.
   %strs = alloca [1000 x [1001 x i8]], align 16
-  %x = getelementptr inbounds [1000 x [1001 x i8]]* %strs, i64 0, i64 %a, i64 %b
+  %x = getelementptr inbounds [1000 x [1001 x i8]], [1000 x [1001 x i8]]* %strs, i64 0, i64 %a, i64 %b
   %cmp = icmp eq i8* %x, null
   ret i1 %cmp
 ; CHECK-NEXT: ret i1 false
@@ -753,10 +753,10 @@ define i1 @alloca_gep(i64 %a, i64 %b) {
 define i1 @non_inbounds_gep_compare(i64* %a) {
 ; CHECK-LABEL: @non_inbounds_gep_compare(
 ; Equality compares with non-inbounds GEPs can be folded.
-  %x = getelementptr i64* %a, i64 42
-  %y = getelementptr inbounds i64* %x, i64 -42
-  %z = getelementptr i64* %a, i64 -42
-  %w = getelementptr inbounds i64* %z, i64 42
+  %x = getelementptr i64, i64* %a, i64 42
+  %y = getelementptr inbounds i64, i64* %x, i64 -42
+  %z = getelementptr i64, i64* %a, i64 -42
+  %w = getelementptr inbounds i64, i64* %z, i64 42
   %cmp = icmp eq i64* %y, %w
   ret i1 %cmp
 ; CHECK-NEXT: ret i1 true
@@ -765,8 +765,8 @@ define i1 @non_inbounds_gep_compare(i64* %a) {
 define i1 @non_inbounds_gep_compare2(i64* %a) {
 ; CHECK-LABEL: @non_inbounds_gep_compare2(
 ; Equality compares with non-inbounds GEPs can be folded.
-  %x = getelementptr i64* %a, i64 4294967297
-  %y = getelementptr i64* %a, i64 1
+  %x = getelementptr i64, i64* %a, i64 4294967297
+  %y = getelementptr i64, i64* %a, i64 1
   %cmp = icmp eq i64* %y, %y
   ret i1 %cmp
 ; CHECK-NEXT: ret i1 true
@@ -918,7 +918,7 @@ define i1 @nonnull_deref_as_arg(i32 addrspace(1)* dereferenceable(4) %i) {
   ret i1 %cmp
 ; CHECK-LABEL: @nonnull_deref_as_arg
 ; CHECK: icmp
-; CHECK ret
+; CHECK: ret
 }
 
 declare nonnull i32* @returns_nonnull_helper()
@@ -950,7 +950,7 @@ define i1 @returns_nonnull_as_deref() {
 }
 
 define i1 @nonnull_load(i32** %addr) {
-  %ptr = load i32** %addr, !nonnull !{}
+  %ptr = load i32*, i32** %addr, !nonnull !{}
   %cmp = icmp eq i32* %ptr, null
   ret i1 %cmp
 ; CHECK-LABEL: @nonnull_load
@@ -958,14 +958,14 @@ define i1 @nonnull_load(i32** %addr) {
 }
 
 define i1 @nonnull_load_as_outer(i32* addrspace(1)* %addr) {
-  %ptr = load i32* addrspace(1)* %addr, !nonnull !{}
+  %ptr = load i32*, i32* addrspace(1)* %addr, !nonnull !{}
   %cmp = icmp eq i32* %ptr, null
   ret i1 %cmp
 ; CHECK-LABEL: @nonnull_load_as_outer
 ; CHECK: ret i1 false
 }
 define i1 @nonnull_load_as_inner(i32 addrspace(1)** %addr) {
-  %ptr = load i32 addrspace(1)** %addr, !nonnull !{}
+  %ptr = load i32 addrspace(1)*, i32 addrspace(1)** %addr, !nonnull !{}
   %cmp = icmp eq i32 addrspace(1)* %ptr, null
   ret i1 %cmp
 ; CHECK-LABEL: @nonnull_load_as_inner
diff --git a/test/Transforms/InstSimplify/fast-math.ll b/test/Transforms/InstSimplify/fast-math.ll
index 71d1ed838491..e7fb14d7e786 100644
--- a/test/Transforms/InstSimplify/fast-math.ll
+++ b/test/Transforms/InstSimplify/fast-math.ll
@@ -105,3 +105,12 @@ define float @nofold_fadd_x_0(float %a) {
 ; CHECK: ret float %no_zero
   ret float %no_zero
 }
+
+; fdiv nsz nnan 0, X ==> 0
+define double @fdiv_zero_by_x(double %X) {
+; CHECK-LABEL: @fdiv_zero_by_x(
+; 0 / X -> 0
+  %r = fdiv nnan nsz double 0.0, %X
+  ret double %r
+; CHECK: ret double 0
+}
diff --git a/test/Transforms/InstSimplify/floating-point-arithmetic.ll b/test/Transforms/InstSimplify/floating-point-arithmetic.ll
index 8177440472cb..b0957a817739 100644
--- a/test/Transforms/InstSimplify/floating-point-arithmetic.ll
+++ b/test/Transforms/InstSimplify/floating-point-arithmetic.ll
@@ -33,3 +33,29 @@ define double @fmul_X_1(double %a) {
   ; CHECK: ret double %a
   ret double %b
 }
+
+; We can't optimize away the fadd in this test because the input
+; value to the function and subsequently to the fadd may be -0.0. 
+; In that one special case, the result of the fadd should be +0.0
+; rather than the first parameter of the fadd.
+
+; Fragile test warning: We need 6 sqrt calls to trigger the bug 
+; because the internal logic has a magic recursion limit of 6. 
+; This is presented without any explanation or ability to customize.
+
+declare float @sqrtf(float)
+
+define float @PR22688(float %x) {
+  %1 = call float @sqrtf(float %x)
+  %2 = call float @sqrtf(float %1)
+  %3 = call float @sqrtf(float %2)
+  %4 = call float @sqrtf(float %3)
+  %5 = call float @sqrtf(float %4)
+  %6 = call float @sqrtf(float %5)
+  %7 = fadd float %6, 0.0
+  ret float %7
+
+; CHECK-LABEL: @PR22688(
+; CHECK: fadd float %6, 0.0
+}
+
diff --git a/test/Transforms/InstSimplify/floating-point-compare.ll b/test/Transforms/InstSimplify/floating-point-compare.ll
new file mode 100644
index 000000000000..af48d062b4f6
--- /dev/null
+++ b/test/Transforms/InstSimplify/floating-point-compare.ll
@@ -0,0 +1,60 @@
+; RUN: opt < %s -instsimplify -S | FileCheck %s
+
+; These tests choose arbitrarily between float and double,
+; and between uge and olt, to give reasonble coverage 
+; without combinatorial explosion.
+
+declare float @llvm.fabs.f32(float)
+declare float @llvm.sqrt.f32(float)
+declare double @llvm.powi.f64(double,i32)
+declare float @llvm.exp.f32(float)
+declare double @llvm.exp2.f64(double)
+declare float @llvm.fma.f32(float,float,float)
+
+declare void @expect_equal(i1,i1)
+
+; CHECK-LABEL: @orderedLessZeroTree(
+define i1 @orderedLessZeroTree(float,float,float,float) {
+  %square = fmul float %0, %0
+  %abs = call float @llvm.fabs.f32(float %1)
+  %sqrt = call float @llvm.sqrt.f32(float %2)
+  %fma = call float @llvm.fma.f32(float %3, float %3, float %sqrt)
+  %div = fdiv float %square, %abs
+  %rem = frem float %sqrt, %fma
+  %add = fadd float %div, %rem
+  %uge = fcmp uge float %add, 0.000000e+00
+; CHECK: ret i1 true
+  ret i1 %uge
+}
+
+; CHECK-LABEL: @orderedLessZeroExpExt(
+define i1 @orderedLessZeroExpExt(float) {
+  %a = call float @llvm.exp.f32(float %0)
+  %b = fpext float %a to double
+  %uge = fcmp uge double %b, 0.000000e+00
+; CHECK: ret i1 true
+  ret i1 %uge
+}
+
+; CHECK-LABEL: @orderedLessZeroExp2Trunc(
+define i1 @orderedLessZeroExp2Trunc(double) {
+  %a = call double @llvm.exp2.f64(double %0)
+  %b = fptrunc double %a to float
+  %olt = fcmp olt float %b, 0.000000e+00
+; CHECK: ret i1 false
+  ret i1 %olt
+}
+
+; CHECK-LABEL: @orderedLessZeroPowi(
+define i1 @orderedLessZeroPowi(double,double) {
+  ; Even constant exponent
+  %a = call double @llvm.powi.f64(double %0, i32 2)
+  %square = fmul double %1, %1
+  ; Odd constant exponent with provably non-negative base
+  %b = call double @llvm.powi.f64(double %square, i32 3)
+  %c = fadd double %a, %b
+  %olt = fcmp olt double %b, 0.000000e+00
+; CHECK: ret i1 false
+  ret i1 %olt
+}
+
diff --git a/test/Transforms/InstSimplify/gep.ll b/test/Transforms/InstSimplify/gep.ll
index 49a97f133cef..13640e7631d5 100644
--- a/test/Transforms/InstSimplify/gep.ll
+++ b/test/Transforms/InstSimplify/gep.ll
@@ -9,7 +9,7 @@ define %struct.A* @test1(%struct.A* %b, %struct.A* %e) {
   %b_ptr = ptrtoint %struct.A* %b to i64
   %sub = sub i64 %e_ptr, %b_ptr
   %sdiv = sdiv exact i64 %sub, 7
-  %gep = getelementptr inbounds %struct.A* %b, i64 %sdiv
+  %gep = getelementptr inbounds %struct.A, %struct.A* %b, i64 %sdiv
   ret %struct.A* %gep
 ; CHECK-LABEL: @test1
 ; CHECK-NEXT: ret %struct.A* %e
@@ -19,7 +19,7 @@ define i8* @test2(i8* %b, i8* %e) {
   %e_ptr = ptrtoint i8* %e to i64
   %b_ptr = ptrtoint i8* %b to i64
   %sub = sub i64 %e_ptr, %b_ptr
-  %gep = getelementptr inbounds i8* %b, i64 %sub
+  %gep = getelementptr inbounds i8, i8* %b, i64 %sub
   ret i8* %gep
 ; CHECK-LABEL: @test2
 ; CHECK-NEXT: ret i8* %e
@@ -30,7 +30,7 @@ define i64* @test3(i64* %b, i64* %e) {
   %b_ptr = ptrtoint i64* %b to i64
   %sub = sub i64 %e_ptr, %b_ptr
   %ashr = ashr exact i64 %sub, 3
-  %gep = getelementptr inbounds i64* %b, i64 %ashr
+  %gep = getelementptr inbounds i64, i64* %b, i64 %ashr
   ret i64* %gep
 ; CHECK-LABEL: @test3
 ; CHECK-NEXT: ret i64* %e
@@ -40,7 +40,7 @@ define %struct.A* @test4(%struct.A* %b) {
   %b_ptr = ptrtoint %struct.A* %b to i64
   %sub = sub i64 0, %b_ptr
   %sdiv = sdiv exact i64 %sub, 7
-  %gep = getelementptr inbounds %struct.A* %b, i64 %sdiv
+  %gep = getelementptr inbounds %struct.A, %struct.A* %b, i64 %sdiv
   ret %struct.A* %gep
 ; CHECK-LABEL: @test4
 ; CHECK-NEXT: ret %struct.A* null
@@ -49,7 +49,7 @@ define %struct.A* @test4(%struct.A* %b) {
 define i8* @test5(i8* %b) {
   %b_ptr = ptrtoint i8* %b to i64
   %sub = sub i64 0, %b_ptr
-  %gep = getelementptr inbounds i8* %b, i64 %sub
+  %gep = getelementptr inbounds i8, i8* %b, i64 %sub
   ret i8* %gep
 ; CHECK-LABEL: @test5
 ; CHECK-NEXT: ret i8* null
@@ -59,7 +59,7 @@ define i64* @test6(i64* %b) {
   %b_ptr = ptrtoint i64* %b to i64
   %sub = sub i64 0, %b_ptr
   %ashr = ashr exact i64 %sub, 3
-  %gep = getelementptr inbounds i64* %b, i64 %ashr
+  %gep = getelementptr inbounds i64, i64* %b, i64 %ashr
   ret i64* %gep
 ; CHECK-LABEL: @test6
 ; CHECK-NEXT: ret i64* null
@@ -69,7 +69,7 @@ define i8* @test7(i8* %b, i8** %e) {
   %e_ptr = ptrtoint i8** %e to i64
   %b_ptr = ptrtoint i8* %b to i64
   %sub = sub i64 %e_ptr, %b_ptr
-  %gep = getelementptr inbounds i8* %b, i64 %sub
+  %gep = getelementptr inbounds i8, i8* %b, i64 %sub
   ret i8* %gep
 ; CHECK-LABEL: @test7
 ; CHECK-NEXT: ptrtoint
diff --git a/test/Transforms/InstSimplify/load.ll b/test/Transforms/InstSimplify/load.ll
index 92953cd0ebfb..ab87d4b9c535 100644
--- a/test/Transforms/InstSimplify/load.ll
+++ b/test/Transforms/InstSimplify/load.ll
@@ -6,14 +6,14 @@
 define i32 @crash_on_zeroinit() {
 ; CHECK-LABEL: @crash_on_zeroinit
 ; CHECK: ret i32 0
-  %load = load i32* bitcast ({}* @zeroinit to i32*)
+  %load = load i32, i32* bitcast ({}* @zeroinit to i32*)
   ret i32 %load
 }
 
 define i32 @crash_on_undef() {
 ; CHECK-LABEL: @crash_on_undef
 ; CHECK: ret i32 undef
-  %load = load i32* bitcast ({}* @undef to i32*)
+  %load = load i32, i32* bitcast ({}* @undef to i32*)
   ret i32 %load
 }
 
diff --git a/test/Transforms/InstSimplify/noalias-ptr.ll b/test/Transforms/InstSimplify/noalias-ptr.ll
index 7693e5542355..59b1dfa8de34 100644
--- a/test/Transforms/InstSimplify/noalias-ptr.ll
+++ b/test/Transforms/InstSimplify/noalias-ptr.ll
@@ -26,7 +26,7 @@ define void @_Z2p1v() #0 {
   %1 = bitcast [10 x i32]* %mStackData to i8*
   %2 = tail call noalias i8* @_Znam(i64 48) #4
   %3 = bitcast i8* %2 to i32*
-  %4 = getelementptr inbounds [10 x i32]* %mStackData, i64 0, i64 0
+  %4 = getelementptr inbounds [10 x i32], [10 x i32]* %mStackData, i64 0, i64 0
   %5 = icmp eq i32* %3, %4
   br i1 %5, label %7, label %6
 
@@ -47,7 +47,7 @@ define void @_Z2p1v() #0 {
 define void @_Z2p2bb(i1 zeroext %b1, i1 zeroext %b2) #0 {
   %mStackData = alloca [10 x i32], align 16
   %1 = bitcast [10 x i32]* %mStackData to i8*
-  %2 = getelementptr inbounds [10 x i32]* %mStackData, i64 0, i64 0
+  %2 = getelementptr inbounds [10 x i32], [10 x i32]* %mStackData, i64 0, i64 0
   %3 = select i1 %b1, i32* %2, i32* @g2
   %4 = tail call noalias i8* @_Znam(i64 48) #4
   %5 = tail call noalias i8* @_Znam(i64 48) #4
@@ -72,7 +72,7 @@ define void @_Z2p2bb(i1 zeroext %b1, i1 zeroext %b2) #0 {
 define void @_Z2p4bb(i1 zeroext %b1, i1 zeroext %b2) #0 {
   %mStackData = alloca [10 x i32], align 16
   %1 = bitcast [10 x i32]* %mStackData to i8*
-  %2 = getelementptr inbounds [10 x i32]* %mStackData, i64 0, i64 0
+  %2 = getelementptr inbounds [10 x i32], [10 x i32]* %mStackData, i64 0, i64 0
   %3 = select i1 %b1, i32* %2, i32* @g3
   %4 = tail call noalias i8* @_Znam(i64 48) #4
   %5 = tail call noalias i8* @_Znam(i64 48) #4
@@ -97,7 +97,7 @@ define void @_Z2p4bb(i1 zeroext %b1, i1 zeroext %b2) #0 {
 define void @_Z2p5bb(i1 zeroext %b1, i1 zeroext %b2) #0 {
   %mStackData = alloca [10 x i32], align 16
   %1 = bitcast [10 x i32]* %mStackData to i8*
-  %2 = getelementptr inbounds [10 x i32]* %mStackData, i64 0, i64 0
+  %2 = getelementptr inbounds [10 x i32], [10 x i32]* %mStackData, i64 0, i64 0
   %3 = select i1 %b1, i32* %2, i32* @g4
   %4 = tail call noalias i8* @_Znam(i64 48) #4
   %5 = tail call noalias i8* @_Znam(i64 48) #4
@@ -122,7 +122,7 @@ define void @_Z2p5bb(i1 zeroext %b1, i1 zeroext %b2) #0 {
 define void @_Z2p6bb(i1 zeroext %b1, i1 zeroext %b2) #0 {
   %mStackData = alloca [10 x i32], align 16
   %1 = bitcast [10 x i32]* %mStackData to i8*
-  %2 = getelementptr inbounds [10 x i32]* %mStackData, i64 0, i64 0
+  %2 = getelementptr inbounds [10 x i32], [10 x i32]* %mStackData, i64 0, i64 0
   %3 = select i1 %b1, i32* %2, i32* @g5
   %4 = tail call noalias i8* @_Znam(i64 48) #4
   %5 = tail call noalias i8* @_Znam(i64 48) #4
@@ -151,7 +151,7 @@ define void @_Z2p6bb(i1 zeroext %b1, i1 zeroext %b2) #0 {
 define void @_Z4nopebbPi(i1 zeroext %b1, i1 zeroext %b2, i32* readnone %q) #0 {
   %mStackData = alloca [10 x i32], align 16
   %1 = bitcast [10 x i32]* %mStackData to i8*
-  %2 = getelementptr inbounds [10 x i32]* %mStackData, i64 0, i64 0
+  %2 = getelementptr inbounds [10 x i32], [10 x i32]* %mStackData, i64 0, i64 0
   %3 = select i1 %b1, i32* %2, i32* %q
   %4 = tail call noalias i8* @_Znam(i64 48) #4
   %5 = tail call noalias i8* @_Znam(i64 48) #4
@@ -176,7 +176,7 @@ define void @_Z4nopebbPi(i1 zeroext %b1, i1 zeroext %b2, i32* readnone %q) #0 {
 define void @_Z2p3bb(i1 zeroext %b1, i1 zeroext %b2) #0 {
   %mStackData = alloca [10 x i32], align 16
   %1 = bitcast [10 x i32]* %mStackData to i8*
-  %2 = getelementptr inbounds [10 x i32]* %mStackData, i64 0, i64 0
+  %2 = getelementptr inbounds [10 x i32], [10 x i32]* %mStackData, i64 0, i64 0
   %3 = select i1 %b1, i32* %2, i32* @g1
   %4 = tail call noalias i8* @_Znam(i64 48) #4
   %5 = tail call noalias i8* @_Znam(i64 48) #4
@@ -201,7 +201,7 @@ define void @_Z2p3bb(i1 zeroext %b1, i1 zeroext %b2) #0 {
 define void @_Z2p7bb(i1 zeroext %b1, i1 zeroext %b2) #0 {
   %mStackData = alloca [10 x i32], align 16
   %1 = bitcast [10 x i32]* %mStackData to i8*
-  %2 = getelementptr inbounds [10 x i32]* %mStackData, i64 0, i64 0
+  %2 = getelementptr inbounds [10 x i32], [10 x i32]* %mStackData, i64 0, i64 0
   %3 = select i1 %b1, i32* %2, i32* @g6
   %4 = tail call noalias i8* @_Znam(i64 48) #4
   %5 = tail call noalias i8* @_Znam(i64 48) #4
@@ -228,7 +228,7 @@ define void @_Z2p2v(i32 %c) #0 {
   %1 = bitcast [10 x i32]* %mStackData to i8*
   %2 = tail call noalias i8* @_Znam(i64 48) #4
   %3 = bitcast i8* %2 to i32*
-  %4 = getelementptr inbounds [10 x i32]* %mStackData, i64 0, i64 0
+  %4 = getelementptr inbounds [10 x i32], [10 x i32]* %mStackData, i64 0, i64 0
   %5 = icmp eq i32* %3, %4
   br i1 %5, label %7, label %6
 
diff --git a/test/Transforms/InstSimplify/past-the-end.ll b/test/Transforms/InstSimplify/past-the-end.ll
index 075da4a24be0..b676e9db2c77 100644
--- a/test/Transforms/InstSimplify/past-the-end.ll
+++ b/test/Transforms/InstSimplify/past-the-end.ll
@@ -18,8 +18,8 @@ define zeroext i1 @no_offsets() {
 ; Comparing past-the-end addresses of two distinct globals. Never equal.
 
 define zeroext i1 @both_past_the_end() {
-  %x = getelementptr i32* @opte_a, i32 1
-  %y = getelementptr i32* @opte_b, i32 1
+  %x = getelementptr i32, i32* @opte_a, i32 1
+  %y = getelementptr i32, i32* @opte_b, i32 1
   %t = icmp eq i32* %x, %y
   ret i1 %t
   ; CHECK: both_past_the_end(
@@ -31,11 +31,11 @@ define zeroext i1 @both_past_the_end() {
 ; of another. Can't fold this.
 
 define zeroext i1 @just_one_past_the_end() {
-  %x = getelementptr i32* @opte_a, i32 1
+  %x = getelementptr i32, i32* @opte_a, i32 1
   %t = icmp eq i32* %x, @opte_b
   ret i1 %t
   ; CHECK: just_one_past_the_end(
-  ; CHECK: ret i1 icmp eq (i32* getelementptr inbounds (i32* @opte_a, i32 1), i32* @opte_b)
+  ; CHECK: ret i1 icmp eq (i32* getelementptr inbounds (i32, i32* @opte_a, i32 1), i32* @opte_b)
 }
 
 ; Comparing base addresses of two distinct allocas. Never equal.
@@ -54,8 +54,8 @@ define zeroext i1 @no_alloca_offsets() {
 define zeroext i1 @both_past_the_end_alloca() {
   %m = alloca i32
   %n = alloca i32
-  %x = getelementptr i32* %m, i32 1
-  %y = getelementptr i32* %n, i32 1
+  %x = getelementptr i32, i32* %m, i32 1
+  %y = getelementptr i32, i32* %n, i32 1
   %t = icmp eq i32* %x, %y
   ret i1 %t
   ; CHECK: both_past_the_end_alloca(
@@ -69,7 +69,7 @@ define zeroext i1 @both_past_the_end_alloca() {
 define zeroext i1 @just_one_past_the_end_alloca() {
   %m = alloca i32
   %n = alloca i32
-  %x = getelementptr i32* %m, i32 1
+  %x = getelementptr i32, i32* %m, i32 1
   %t = icmp eq i32* %x, %n
   ret i1 %t
   ; CHECK: just_one_past_the_end_alloca(
diff --git a/test/Transforms/InstSimplify/ptr_diff.ll b/test/Transforms/InstSimplify/ptr_diff.ll
index 6a3f65237c5e..6c27e6f44678 100644
--- a/test/Transforms/InstSimplify/ptr_diff.ll
+++ b/test/Transforms/InstSimplify/ptr_diff.ll
@@ -6,8 +6,8 @@ define i64 @ptrdiff1(i8* %ptr) {
 ; CHECK-LABEL: @ptrdiff1(
 ; CHECK-NEXT: ret i64 42
 
-  %first = getelementptr inbounds i8* %ptr, i32 0
-  %last = getelementptr inbounds i8* %ptr, i32 42
+  %first = getelementptr inbounds i8, i8* %ptr, i32 0
+  %last = getelementptr inbounds i8, i8* %ptr, i32 42
   %first.int = ptrtoint i8* %first to i64
   %last.int = ptrtoint i8* %last to i64
   %diff = sub i64 %last.int, %first.int
@@ -18,14 +18,14 @@ define i64 @ptrdiff2(i8* %ptr) {
 ; CHECK-LABEL: @ptrdiff2(
 ; CHECK-NEXT: ret i64 42
 
-  %first1 = getelementptr inbounds i8* %ptr, i32 0
-  %first2 = getelementptr inbounds i8* %first1, i32 1
-  %first3 = getelementptr inbounds i8* %first2, i32 2
-  %first4 = getelementptr inbounds i8* %first3, i32 4
-  %last1 = getelementptr inbounds i8* %first2, i32 48
-  %last2 = getelementptr inbounds i8* %last1, i32 8
-  %last3 = getelementptr inbounds i8* %last2, i32 -4
-  %last4 = getelementptr inbounds i8* %last3, i32 -4
+  %first1 = getelementptr inbounds i8, i8* %ptr, i32 0
+  %first2 = getelementptr inbounds i8, i8* %first1, i32 1
+  %first3 = getelementptr inbounds i8, i8* %first2, i32 2
+  %first4 = getelementptr inbounds i8, i8* %first3, i32 4
+  %last1 = getelementptr inbounds i8, i8* %first2, i32 48
+  %last2 = getelementptr inbounds i8, i8* %last1, i32 8
+  %last3 = getelementptr inbounds i8, i8* %last2, i32 -4
+  %last4 = getelementptr inbounds i8, i8* %last3, i32 -4
   %first.int = ptrtoint i8* %first4 to i64
   %last.int = ptrtoint i8* %last4 to i64
   %diff = sub i64 %last.int, %first.int
@@ -39,8 +39,8 @@ define i64 @ptrdiff3(i8* %ptr) {
 ; CHECK: sub
 ; CHECK: ret
 
-  %first = getelementptr i8* %ptr, i32 0
-  %last = getelementptr i8* %ptr, i32 42
+  %first = getelementptr i8, i8* %ptr, i32 0
+  %last = getelementptr i8, i8* %ptr, i32 42
   %first.int = ptrtoint i8* %first to i64
   %last.int = ptrtoint i8* %last to i64
   %diff = sub i64 %last.int, %first.int
@@ -64,12 +64,12 @@ define <4 x i32> @ptrdiff4(<4 x i8*> %arg) nounwind {
 
 define i32 @ptrdiff5() nounwind {
 bb:
-  %tmp = getelementptr inbounds %struct.ham* @global, i32 0, i32 1
-  %tmp1 = getelementptr inbounds [2 x [2 x i32]]* %tmp, i32 0, i32 0
+  %tmp = getelementptr inbounds %struct.ham, %struct.ham* @global, i32 0, i32 1
+  %tmp1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %tmp, i32 0, i32 0
   %tmp2 = bitcast [2 x i32]* %tmp1 to i32*
   %tmp3 = ptrtoint i32* %tmp2 to i32
-  %tmp4 = getelementptr inbounds %struct.ham* @global, i32 0, i32 1
-  %tmp5 = getelementptr inbounds [2 x [2 x i32]]* %tmp4, i32 0, i32 0
+  %tmp4 = getelementptr inbounds %struct.ham, %struct.ham* @global, i32 0, i32 1
+  %tmp5 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %tmp4, i32 0, i32 0
   %tmp6 = ptrtoint [2 x i32]* %tmp5 to i32
   %tmp7 = sub i32 %tmp3, %tmp6
   ret i32 %tmp7
diff --git a/test/Transforms/InstSimplify/undef.ll b/test/Transforms/InstSimplify/undef.ll
index e8b49b6397db..f1f0b037fdbd 100644
--- a/test/Transforms/InstSimplify/undef.ll
+++ b/test/Transforms/InstSimplify/undef.ll
@@ -150,7 +150,7 @@ define i64 @test17(i64 %a) {
 ; @test18
 ; CHECK: ret i64 undef
 define i64 @test18(i64 %a) {
-  %r = call i64 (i64)* undef(i64 %a)
+  %r = call i64 (i64) undef(i64 %a)
   ret i64 %r
 }
 
diff --git a/test/Transforms/InstSimplify/vector_gep.ll b/test/Transforms/InstSimplify/vector_gep.ll
index 17814637b3dd..5c3062047c30 100644
--- a/test/Transforms/InstSimplify/vector_gep.ll
+++ b/test/Transforms/InstSimplify/vector_gep.ll
@@ -4,13 +4,13 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 
 declare void @helper(<2 x i8*>)
 define void @test(<2 x i8*> %a) {
-  %A = getelementptr <2 x i8*> %a, <2 x i32> <i32 0, i32 0>
+  %A = getelementptr i8, <2 x i8*> %a, <2 x i32> <i32 0, i32 0>
   call void @helper(<2 x i8*> %A)
   ret void
 }
 
 define <4 x i8*> @test1(<4 x i8*> %a) {
-  %gep = getelementptr <4 x i8*> %a, <4 x i32> zeroinitializer
+  %gep = getelementptr i8, <4 x i8*> %a, <4 x i32> zeroinitializer
   ret <4 x i8*> %gep
 
 ; CHECK-LABEL: @test1
@@ -18,7 +18,7 @@ define <4 x i8*> @test1(<4 x i8*> %a) {
 }
 
 define <4 x i8*> @test2(<4 x i8*> %a) {
-  %gep = getelementptr <4 x i8*> %a
+  %gep = getelementptr i8, <4 x i8*> %a
   ret <4 x i8*> %gep
 
 ; CHECK-LABEL: @test2
@@ -28,7 +28,7 @@ define <4 x i8*> @test2(<4 x i8*> %a) {
 %struct = type { double, float }
 
 define <4 x float*> @test3() {
-  %gep = getelementptr <4 x %struct*> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+  %gep = getelementptr %struct, <4 x %struct*> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   ret <4 x float*> %gep
 
 ; CHECK-LABEL: @test3
@@ -38,7 +38,7 @@ define <4 x float*> @test3() {
 %struct.empty = type { }
 
 define <4 x %struct.empty*> @test4(<4 x %struct.empty*> %a) {
-  %gep = getelementptr <4 x %struct.empty*> %a, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+  %gep = getelementptr %struct.empty, <4 x %struct.empty*> %a, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   ret <4 x %struct.empty*> %gep
 
 ; CHECK-LABEL: @test4
@@ -47,9 +47,9 @@ define <4 x %struct.empty*> @test4(<4 x %struct.empty*> %a) {
 
 define <4 x i8*> @test5() {
   %c = inttoptr <4 x i64> <i64 1, i64 2, i64 3, i64 4> to <4 x i8*>
-  %gep = getelementptr <4 x i8*> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+  %gep = getelementptr i8, <4 x i8*> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   ret <4 x i8*> %gep
 
 ; CHECK-LABEL: @test5
-; CHECK-NEXT: ret <4 x i8*> getelementptr (<4 x i8*> <i8* inttoptr (i64 1 to i8*), i8* inttoptr (i64 2 to i8*), i8* inttoptr (i64 3 to i8*), i8* inttoptr (i64 4 to i8*)>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
+; CHECK-NEXT: ret <4 x i8*> getelementptr (i8, <4 x i8*> <i8* inttoptr (i64 1 to i8*), i8* inttoptr (i64 2 to i8*), i8* inttoptr (i64 3 to i8*), i8* inttoptr (i64 4 to i8*)>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
 }
diff --git a/test/Transforms/InstSimplify/vector_ptr_bitcast.ll b/test/Transforms/InstSimplify/vector_ptr_bitcast.ll
index 607892ae74d2..97c8343bfb9b 100644
--- a/test/Transforms/InstSimplify/vector_ptr_bitcast.ll
+++ b/test/Transforms/InstSimplify/vector_ptr_bitcast.ll
@@ -14,7 +14,7 @@ target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
                                           align 8
 
 define i64 @fn() {
-  %x = load <2 x i8*>* bitcast (%mst* @a to <2 x i8*>*), align 8
+  %x = load <2 x i8*>, <2 x i8*>* bitcast (%mst* @a to <2 x i8*>*), align 8
   %b = extractelement <2 x i8*> %x, i32 0
   %c = ptrtoint i8* %b to i64
   ; CHECK-LABEL: @fn
@@ -23,7 +23,7 @@ define i64 @fn() {
 }
 
 define i64 @fn2() {
-  %x = load <4 x i32*>* bitcast (%mst2* @b to <4 x i32*>*), align 8
+  %x = load <4 x i32*>, <4 x i32*>* bitcast (%mst2* @b to <4 x i32*>*), align 8
   %b = extractelement <4 x i32*> %x, i32 0
   %c = extractelement <4 x i32*> %x, i32 3
   %d = ptrtoint i32* %b to i64
diff --git a/test/Transforms/Internalize/2009-01-05-InternalizeAliases.ll b/test/Transforms/Internalize/2009-01-05-InternalizeAliases.ll
index 16523886a068..c50b6fc61c8e 100644
--- a/test/Transforms/Internalize/2009-01-05-InternalizeAliases.ll
+++ b/test/Transforms/Internalize/2009-01-05-InternalizeAliases.ll
@@ -10,7 +10,7 @@
 ; CHECK: @C = internal alias i32* @A
 
 define i32 @main() {
-	%tmp = load i32* @C
+	%tmp = load i32, i32* @C
 	ret i32 %tmp
 }
 
diff --git a/test/Transforms/JumpThreading/2010-08-26-and.ll b/test/Transforms/JumpThreading/2010-08-26-and.ll
index 2d6caf752e09..cc56ac9cc84c 100644
--- a/test/Transforms/JumpThreading/2010-08-26-and.ll
+++ b/test/Transforms/JumpThreading/2010-08-26-and.ll
@@ -29,8 +29,8 @@ land.lhs.true.i:                                  ; preds = %_ZN12StringSwitchI5
   %retval.0.i.pre161 = phi i32 [ undef, %bb.nph ], [ %retval.0.i.pre, %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit134 ] ; <i32> [#uses=3]
   %indvar = phi i64 [ 0, %bb.nph ], [ %tmp146, %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit134 ] ; <i64> [#uses=1]
   %tmp146 = add i64 %indvar, 1                    ; <i64> [#uses=3]
-  %arrayidx = getelementptr i8** %argv, i64 %tmp146 ; <i8**> [#uses=1]
-  %tmp6 = load i8** %arrayidx, align 8            ; <i8*> [#uses=8]
+  %arrayidx = getelementptr i8*, i8** %argv, i64 %tmp146 ; <i8**> [#uses=1]
+  %tmp6 = load i8*, i8** %arrayidx, align 8            ; <i8*> [#uses=8]
   %call.i.i = call i64 @strlen(i8* %tmp6) nounwind ; <i64> [#uses=1]
   %conv.i.i = trunc i64 %call.i.i to i32          ; <i32> [#uses=6]\
 ; CHECK: switch i32 %conv.i.i
@@ -42,7 +42,7 @@ land.lhs.true.i:                                  ; preds = %_ZN12StringSwitchI5
   ]
 
 land.lhs.true5.i:                                 ; preds = %land.lhs.true.i
-  %call.i = call i32 @memcmp(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i8* %tmp6, i64 4) nounwind ; <i32> [#uses=1]
+  %call.i = call i32 @memcmp(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i8* %tmp6, i64 4) nounwind ; <i32> [#uses=1]
   %cmp9.i = icmp eq i32 %call.i, 0                ; <i1> [#uses=1]
   br i1 %cmp9.i, label %_ZN12StringSwitchI5ColorE4CaseILj4EEERS1_RAT__KcRKS0_.exit, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit
 
@@ -50,7 +50,7 @@ _ZN12StringSwitchI5ColorE4CaseILj4EEERS1_RAT__KcRKS0_.exit: ; preds = %land.lhs.
   br label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit
 
 land.lhs.true5.i37:                               ; preds = %land.lhs.true.i
-  %call.i35 = call i32 @memcmp(i8* getelementptr inbounds ([7 x i8]* @.str1, i64 0, i64 0), i8* %tmp6, i64 7) nounwind ; <i32> [#uses=1]
+  %call.i35 = call i32 @memcmp(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str1, i64 0, i64 0), i8* %tmp6, i64 7) nounwind ; <i32> [#uses=1]
   %cmp9.i36 = icmp eq i32 %call.i35, 0            ; <i1> [#uses=1]
   br i1 %cmp9.i36, label %if.then.i40, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit
 
@@ -66,7 +66,7 @@ _ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit: ; preds = %if.then.i
   br i1 %or.cond, label %land.lhs.true5.i55, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit60
 
 land.lhs.true5.i55:                               ; preds = %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit
-  %call.i53 = call i32 @memcmp(i8* getelementptr inbounds ([7 x i8]* @.str2, i64 0, i64 0), i8* %tmp6, i64 7) nounwind ; <i32> [#uses=1]
+  %call.i53 = call i32 @memcmp(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str2, i64 0, i64 0), i8* %tmp6, i64 7) nounwind ; <i32> [#uses=1]
   %cmp9.i54 = icmp eq i32 %call.i53, 0            ; <i1> [#uses=1]
   br i1 %cmp9.i54, label %if.then.i58, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit60
 
@@ -83,7 +83,7 @@ _ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit60: ; preds = %if.then
   br i1 %or.cond168, label %land.lhs.true5.i74, label %_ZN12StringSwitchI5ColorE4CaseILj6EEERS1_RAT__KcRKS0_.exit
 
 land.lhs.true5.i74:                               ; preds = %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit60
-  %call.i72 = call i32 @memcmp(i8* getelementptr inbounds ([6 x i8]* @.str3, i64 0, i64 0), i8* %tmp6, i64 6) nounwind ; <i32> [#uses=1]
+  %call.i72 = call i32 @memcmp(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str3, i64 0, i64 0), i8* %tmp6, i64 6) nounwind ; <i32> [#uses=1]
   %cmp9.i73 = icmp eq i32 %call.i72, 0            ; <i1> [#uses=1]
   br i1 %cmp9.i73, label %if.then.i77, label %_ZN12StringSwitchI5ColorE4CaseILj6EEERS1_RAT__KcRKS0_.exit
 
@@ -100,7 +100,7 @@ _ZN12StringSwitchI5ColorE4CaseILj6EEERS1_RAT__KcRKS0_.exit: ; preds = %if.then.i
   br i1 %or.cond169, label %land.lhs.true5.i92, label %_ZN12StringSwitchI5ColorE4CaseILj5EEERS1_RAT__KcRKS0_.exit
 
 land.lhs.true5.i92:                               ; preds = %_ZN12StringSwitchI5ColorE4CaseILj6EEERS1_RAT__KcRKS0_.exit
-  %call.i90 = call i32 @memcmp(i8* getelementptr inbounds ([5 x i8]* @.str4, i64 0, i64 0), i8* %tmp6, i64 5) nounwind ; <i32> [#uses=1]
+  %call.i90 = call i32 @memcmp(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str4, i64 0, i64 0), i8* %tmp6, i64 5) nounwind ; <i32> [#uses=1]
   %cmp9.i91 = icmp eq i32 %call.i90, 0            ; <i1> [#uses=1]
   br i1 %cmp9.i91, label %if.then.i95, label %_ZN12StringSwitchI5ColorE4CaseILj5EEERS1_RAT__KcRKS0_.exit
 
@@ -117,7 +117,7 @@ _ZN12StringSwitchI5ColorE4CaseILj5EEERS1_RAT__KcRKS0_.exit: ; preds = %if.then.i
   br i1 %or.cond170, label %land.lhs.true5.i110, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit115
 
 land.lhs.true5.i110:                              ; preds = %_ZN12StringSwitchI5ColorE4CaseILj5EEERS1_RAT__KcRKS0_.exit
-  %call.i108 = call i32 @memcmp(i8* getelementptr inbounds ([7 x i8]* @.str5, i64 0, i64 0), i8* %tmp6, i64 7) nounwind ; <i32> [#uses=1]
+  %call.i108 = call i32 @memcmp(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str5, i64 0, i64 0), i8* %tmp6, i64 7) nounwind ; <i32> [#uses=1]
   %cmp9.i109 = icmp eq i32 %call.i108, 0          ; <i1> [#uses=1]
   br i1 %cmp9.i109, label %if.then.i113, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit115
 
@@ -134,7 +134,7 @@ _ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit115: ; preds = %if.the
   br i1 %or.cond171, label %land.lhs.true5.i129, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit134
 
 land.lhs.true5.i129:                              ; preds = %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit115
-  %call.i127 = call i32 @memcmp(i8* getelementptr inbounds ([7 x i8]* @.str6, i64 0, i64 0), i8* %tmp6, i64 7) nounwind ; <i32> [#uses=1]
+  %call.i127 = call i32 @memcmp(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str6, i64 0, i64 0), i8* %tmp6, i64 7) nounwind ; <i32> [#uses=1]
   %cmp9.i128 = icmp eq i32 %call.i127, 0          ; <i1> [#uses=1]
   br i1 %cmp9.i128, label %if.then.i132, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit134
 
@@ -147,7 +147,7 @@ _ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit134: ; preds = %if.the
   %tmp7.i138 = and i8 %tmp2.i137, 1               ; <i8> [#uses=1]
   %tobool.i139 = icmp eq i8 %tmp7.i138, 0         ; <i1> [#uses=1]
   %retval.0.i = select i1 %tobool.i139, i32 0, i32 %retval.0.i.pre ; <i32> [#uses=1]
-  %call22 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str7, i64 0, i64 0), i32 %retval.0.i) ; <i32> [#uses=0]
+  %call22 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str7, i64 0, i64 0), i32 %retval.0.i) ; <i32> [#uses=0]
   %exitcond = icmp eq i64 %tmp146, %tmp145        ; <i1> [#uses=1]
   br i1 %exitcond, label %for.end, label %land.lhs.true.i
 
diff --git a/test/Transforms/JumpThreading/2011-04-14-InfLoop.ll b/test/Transforms/JumpThreading/2011-04-14-InfLoop.ll
index 86a1321c3543..0323723a3a85 100644
--- a/test/Transforms/JumpThreading/2011-04-14-InfLoop.ll
+++ b/test/Transforms/JumpThreading/2011-04-14-InfLoop.ll
@@ -15,7 +15,7 @@ for.cond1177:
   br i1 %cmp1179, label %for.cond1177, label %land.rhs1320
 
 land.rhs1320:
-  %tmp1324 = load volatile i64* getelementptr inbounds (%0* @g_338, i64 0, i32 2), align 1
+  %tmp1324 = load volatile i64, i64* getelementptr inbounds (%0, %0* @g_338, i64 0, i32 2), align 1
   br label %if.end.i
 
 if.end.i:
diff --git a/test/Transforms/JumpThreading/assume.ll b/test/Transforms/JumpThreading/assume.ll
index 89dd0a954c01..53010b71c728 100644
--- a/test/Transforms/JumpThreading/assume.ll
+++ b/test/Transforms/JumpThreading/assume.ll
@@ -21,11 +21,11 @@ if.then:                                          ; preds = %entry
   br i1 %cmp2, label %if.then3, label %return
 
 if.then3:                                         ; preds = %if.then
-  tail call void (...)* @bar() #1
+  tail call void (...) @bar() #1
   br label %return
 
 if.else:                                          ; preds = %entry
-  tail call void (...)* @car() #1
+  tail call void (...) @car() #1
   br label %return
 
 return:                                           ; preds = %if.else, %if.then, %if.then3
@@ -43,12 +43,12 @@ entry:
 ; CHECK-LABEL: @test2
 ; CHECK: icmp sgt i32 %a, 5
 ; CHECK: tail call void @llvm.assume
-; CHECK: tail call void (...)* @bar()
+; CHECK: tail call void (...) @bar()
 ; CHECK: ret i32 1
 
 
 if.then:                                          ; preds = %entry
-  tail call void (...)* @bar() #1
+  tail call void (...) @bar() #1
   br label %return
 
 return:                                           ; preds = %entry, %if.then
diff --git a/test/Transforms/JumpThreading/crash.ll b/test/Transforms/JumpThreading/crash.ll
index 2fe87464c117..900a7738d3bf 100644
--- a/test/Transforms/JumpThreading/crash.ll
+++ b/test/Transforms/JumpThreading/crash.ll
@@ -356,7 +356,7 @@ B2:
   br label %BrBlock
 
 BrBlock:
-  %L = load i32* %P
+  %L = load i32, i32* %P
   %C = icmp eq i32 %L, 42
   br i1 %C, label %T, label %F
   
diff --git a/test/Transforms/JumpThreading/indirectbr.ll b/test/Transforms/JumpThreading/indirectbr.ll
index b87fb6c22287..197ca30f58ae 100644
--- a/test/Transforms/JumpThreading/indirectbr.ll
+++ b/test/Transforms/JumpThreading/indirectbr.ll
@@ -79,15 +79,15 @@ entry:
   br label %__here
 
 __here:                                           ; preds = %entry
-  %call = call i32 (...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i64 ptrtoint (i8* blockaddress(@test3, %__here) to i64)) nounwind noredzone
+  %call = call i32 (...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i64 ptrtoint (i8* blockaddress(@test3, %__here) to i64)) nounwind noredzone
   br label %__here1
 
 __here1:                                          ; preds = %__here
-  %call2 = call i32 (...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i64 ptrtoint (i8* blockaddress(@test3, %__here1) to i64)) nounwind noredzone
+  %call2 = call i32 (...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i64 ptrtoint (i8* blockaddress(@test3, %__here1) to i64)) nounwind noredzone
   br label %__here3
 
 __here3:                                          ; preds = %__here1
-  %call4 = call i32 (...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i64 ptrtoint (i8* blockaddress(@test3, %__here3) to i64)) nounwind noredzone
+  %call4 = call i32 (...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i64 ptrtoint (i8* blockaddress(@test3, %__here3) to i64)) nounwind noredzone
   ret void
 }
 
diff --git a/test/Transforms/JumpThreading/landing-pad.ll b/test/Transforms/JumpThreading/landing-pad.ll
index 9ee0526d0446..4d49db04f6ab 100644
--- a/test/Transforms/JumpThreading/landing-pad.ll
+++ b/test/Transforms/JumpThreading/landing-pad.ll
@@ -13,8 +13,8 @@
 define void @_ZN15EditCommandImpl5applyEv(%class.E* %this) uwtable align 2 {
 entry:
   %0 = bitcast %class.E* %this to void (%class.E*)***
-  %vtable = load void (%class.E*)*** %0, align 8
-  %1 = load void (%class.E*)** %vtable, align 8
+  %vtable = load void (%class.E*)**, void (%class.E*)*** %0, align 8
+  %1 = load void (%class.E*)*, void (%class.E*)** %vtable, align 8
   call void %1(%class.E* %this)
   ret void
 }
@@ -22,16 +22,16 @@ entry:
 define void @_ZN1DC1Ev(%class.D* nocapture %this) unnamed_addr uwtable align 2 {
 entry:
   call void @_ZN24CompositeEditCommandImplC2Ev()
-  %0 = getelementptr inbounds %class.D* %this, i64 0, i32 0, i32 0, i32 0
-  store i32 (...)** bitcast (i8** getelementptr inbounds ([3 x i8*]* @_ZTV1D, i64 0, i64 2) to i32 (...)**), i32 (...)*** %0, align 8
+  %0 = getelementptr inbounds %class.D, %class.D* %this, i64 0, i32 0, i32 0, i32 0
+  store i32 (...)** bitcast (i8** getelementptr inbounds ([3 x i8*], [3 x i8*]* @_ZTV1D, i64 0, i64 2) to i32 (...)**), i32 (...)*** %0, align 8
   ret void
 }
 
 define void @_ZN1DC2Ev(%class.D* nocapture %this) unnamed_addr uwtable align 2 {
 entry:
   call void @_ZN24CompositeEditCommandImplC2Ev()
-  %0 = getelementptr inbounds %class.D* %this, i64 0, i32 0, i32 0, i32 0
-  store i32 (...)** bitcast (i8** getelementptr inbounds ([3 x i8*]* @_ZTV1D, i64 0, i64 2) to i32 (...)**), i32 (...)*** %0, align 8
+  %0 = getelementptr inbounds %class.D, %class.D* %this, i64 0, i32 0, i32 0, i32 0
+  store i32 (...)** bitcast (i8** getelementptr inbounds ([3 x i8*], [3 x i8*]* @_ZTV1D, i64 0, i64 2) to i32 (...)**), i32 (...)*** %0, align 8
   ret void
 }
 
@@ -50,10 +50,10 @@ entry:
 
 _ZN1DC1Ev.exit:                                   ; preds = %entry
   %0 = bitcast i8* %call to i32 (...)***
-  store i32 (...)** bitcast (i8** getelementptr inbounds ([3 x i8*]* @_ZTV1D, i64 0, i64 2) to i32 (...)**), i32 (...)*** %0, align 8
-  %_ref.i.i.i = getelementptr inbounds i8* %call, i64 8
+  store i32 (...)** bitcast (i8** getelementptr inbounds ([3 x i8*], [3 x i8*]* @_ZTV1D, i64 0, i64 2) to i32 (...)**), i32 (...)*** %0, align 8
+  %_ref.i.i.i = getelementptr inbounds i8, i8* %call, i64 8
   %1 = bitcast i8* %_ref.i.i.i to i32*
-  %2 = load i32* %1, align 4
+  %2 = load i32, i32* %1, align 4
   %inc.i.i.i = add nsw i32 %2, 1
   store i32 %inc.i.i.i, i32* %1, align 4
   %3 = bitcast i8* %call to %class.D*
@@ -76,7 +76,7 @@ lpad:                                             ; preds = %entry
 lpad1:                                            ; preds = %_ZN1DC1Ev.exit, %_ZN15EditCommandImpl5applyEv.exit
   %5 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
           cleanup
-  %6 = load i32* %1, align 4
+  %6 = load i32, i32* %1, align 4
   %tobool.i.i.i = icmp eq i32 %6, 0
   br i1 %tobool.i.i.i, label %_ZN1BI1DED1Ev.exit, label %if.then.i.i.i
 
@@ -98,10 +98,10 @@ terminate.lpad:                                   ; No predecessors!
 
 define void @_ZN1BI1DEC1EPS0_(%class.B* nocapture %this, %class.D* %p1) unnamed_addr uwtable align 2 {
 entry:
-  %m_ptr.i = getelementptr inbounds %class.B* %this, i64 0, i32 0
+  %m_ptr.i = getelementptr inbounds %class.B, %class.B* %this, i64 0, i32 0
   store %class.D* %p1, %class.D** %m_ptr.i, align 8
-  %_ref.i.i = getelementptr inbounds %class.D* %p1, i64 0, i32 0, i32 0, i32 1, i32 0, i32 0
-  %0 = load i32* %_ref.i.i, align 4
+  %_ref.i.i = getelementptr inbounds %class.D, %class.D* %p1, i64 0, i32 0, i32 0, i32 1, i32 0, i32 0
+  %0 = load i32, i32* %_ref.i.i, align 4
   %inc.i.i = add nsw i32 %0, 1
   store i32 %inc.i.i, i32* %_ref.i.i, align 4
   ret void
@@ -115,8 +115,8 @@ declare void @_ZdlPv()
 
 define %class.D* @_ZN1BI1DEptEv(%class.B* nocapture readonly %this) nounwind readonly uwtable align 2 {
 entry:
-  %m_ptr = getelementptr inbounds %class.B* %this, i64 0, i32 0
-  %0 = load %class.D** %m_ptr, align 8
+  %m_ptr = getelementptr inbounds %class.B, %class.B* %this, i64 0, i32 0
+  %0 = load %class.D*, %class.D** %m_ptr, align 8
   ret %class.D* %0
 }
 
@@ -124,10 +124,10 @@ declare void @_ZN1D16deleteKeyPressedEv()
 
 define void @_ZN1BI1DED1Ev(%class.B* nocapture readonly %this) unnamed_addr uwtable align 2 {
 entry:
-  %m_ptr.i = getelementptr inbounds %class.B* %this, i64 0, i32 0
-  %0 = load %class.D** %m_ptr.i, align 8
-  %_ref.i.i = getelementptr inbounds %class.D* %0, i64 0, i32 0, i32 0, i32 1, i32 0, i32 0
-  %1 = load i32* %_ref.i.i, align 4
+  %m_ptr.i = getelementptr inbounds %class.B, %class.B* %this, i64 0, i32 0
+  %0 = load %class.D*, %class.D** %m_ptr.i, align 8
+  %_ref.i.i = getelementptr inbounds %class.D, %class.D* %0, i64 0, i32 0, i32 0, i32 1, i32 0, i32 0
+  %1 = load i32, i32* %_ref.i.i, align 4
   %tobool.i.i = icmp eq i32 %1, 0
   br i1 %tobool.i.i, label %_ZN1BI1DED2Ev.exit, label %if.then.i.i
 
@@ -146,10 +146,10 @@ declare hidden void @__clang_call_terminate()
 
 define void @_ZN1BI1DED2Ev(%class.B* nocapture readonly %this) unnamed_addr uwtable align 2 {
 entry:
-  %m_ptr = getelementptr inbounds %class.B* %this, i64 0, i32 0
-  %0 = load %class.D** %m_ptr, align 8
-  %_ref.i = getelementptr inbounds %class.D* %0, i64 0, i32 0, i32 0, i32 1, i32 0, i32 0
-  %1 = load i32* %_ref.i, align 4
+  %m_ptr = getelementptr inbounds %class.B, %class.B* %this, i64 0, i32 0
+  %0 = load %class.D*, %class.D** %m_ptr, align 8
+  %_ref.i = getelementptr inbounds %class.D, %class.D* %0, i64 0, i32 0, i32 0, i32 1, i32 0, i32 0
+  %1 = load i32, i32* %_ref.i, align 4
   %tobool.i = icmp eq i32 %1, 0
   br i1 %tobool.i, label %_ZN1AI1CE5derefEv.exit, label %if.then.i
 
@@ -166,8 +166,8 @@ _ZN1AI1CE5derefEv.exit:                           ; preds = %entry, %if.then.i
 
 define void @_ZN1AI1CE5derefEv(%class.A* nocapture readonly %this) nounwind uwtable align 2 {
 entry:
-  %_ref = getelementptr inbounds %class.A* %this, i64 0, i32 0
-  %0 = load i32* %_ref, align 4
+  %_ref = getelementptr inbounds %class.A, %class.A* %this, i64 0, i32 0
+  %0 = load i32, i32* %_ref, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %if.end, label %if.then
 
@@ -184,10 +184,10 @@ if.end:                                           ; preds = %entry, %if.then
 
 define void @_ZN1BI1DEC2EPS0_(%class.B* nocapture %this, %class.D* %p1) unnamed_addr uwtable align 2 {
 entry:
-  %m_ptr = getelementptr inbounds %class.B* %this, i64 0, i32 0
+  %m_ptr = getelementptr inbounds %class.B, %class.B* %this, i64 0, i32 0
   store %class.D* %p1, %class.D** %m_ptr, align 8
-  %_ref.i = getelementptr inbounds %class.D* %p1, i64 0, i32 0, i32 0, i32 1, i32 0, i32 0
-  %0 = load i32* %_ref.i, align 4
+  %_ref.i = getelementptr inbounds %class.D, %class.D* %p1, i64 0, i32 0, i32 0, i32 1, i32 0, i32 0
+  %0 = load i32, i32* %_ref.i, align 4
   %inc.i = add nsw i32 %0, 1
   store i32 %inc.i, i32* %_ref.i, align 4
   ret void
@@ -195,8 +195,8 @@ entry:
 
 define void @_ZN1AI1CE3refEv(%class.A* nocapture %this) nounwind uwtable align 2 {
 entry:
-  %_ref = getelementptr inbounds %class.A* %this, i64 0, i32 0
-  %0 = load i32* %_ref, align 4
+  %_ref = getelementptr inbounds %class.A, %class.A* %this, i64 0, i32 0
+  %0 = load i32, i32* %_ref, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %_ref, align 4
   ret void
diff --git a/test/Transforms/JumpThreading/lvi-load.ll b/test/Transforms/JumpThreading/lvi-load.ll
index 2a4cf925102f..a36e263bf92c 100644
--- a/test/Transforms/JumpThreading/lvi-load.ll
+++ b/test/Transforms/JumpThreading/lvi-load.ll
@@ -16,8 +16,8 @@ target triple = "x86_64-apple-darwin10.4"
 ; CHECK: Z3fooPN4llvm5ValueE
 define zeroext i8 @_Z3fooPN4llvm5ValueE(%"struct.llvm::Value"* %V) ssp {
 entry:
-  %0 = getelementptr inbounds %"struct.llvm::Value"* %V, i64 0, i32 1 ; <i8*> [#uses=1]
-  %1 = load i8* %0, align 8                       ; <i8> [#uses=2]
+  %0 = getelementptr inbounds %"struct.llvm::Value", %"struct.llvm::Value"* %V, i64 0, i32 1 ; <i8*> [#uses=1]
+  %1 = load i8, i8* %0, align 8                       ; <i8> [#uses=2]
   %2 = icmp ugt i8 %1, 20                         ; <i1> [#uses=1]
   br i1 %2, label %bb.i, label %bb2
 
@@ -27,7 +27,7 @@ bb.i:                                             ; preds = %entry
 
 ; CHECK-NOT: assert
 bb6.i.i:                                          ; preds = %bb.i
-  tail call void @__assert_rtn(i8* getelementptr inbounds ([5 x i8]* @_ZZN4llvm4castINS_11InstructionEPNS_5ValueEEENS_10cast_rettyIT_T0_E8ret_typeERKS6_E8__func__, i64 0, i64 0), i8* getelementptr inbounds ([31 x i8]* @.str, i64 0, i64 0), i32 202, i8* getelementptr inbounds ([59 x i8]* @.str1, i64 0, i64 0)) noreturn
+  tail call void @__assert_rtn(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @_ZZN4llvm4castINS_11InstructionEPNS_5ValueEEENS_10cast_rettyIT_T0_E8ret_typeERKS6_E8__func__, i64 0, i64 0), i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str, i64 0, i64 0), i32 202, i8* getelementptr inbounds ([59 x i8], [59 x i8]* @.str1, i64 0, i64 0)) noreturn
   unreachable
 
 _ZN4llvm8dyn_castINS_11InstructionEPNS_5ValueEEENS_10cast_rettyIT_T0_E8ret_typeERKS6_.exit: ; preds = %bb.i
diff --git a/test/Transforms/JumpThreading/or-undef.ll b/test/Transforms/JumpThreading/or-undef.ll
index 6311b6df4373..b55bdddc196d 100644
--- a/test/Transforms/JumpThreading/or-undef.ll
+++ b/test/Transforms/JumpThreading/or-undef.ll
@@ -32,13 +32,13 @@ bb2:                                              ; preds = %bb1, %bb, %entry
   br i1 %tmp7, label %bb7, label %bb5
 
 bb5:                                              ; preds = %bb2
-  %tmp8 = load i8** %argv.0, align 8              ; <i8*> [#uses=1]
+  %tmp8 = load i8*, i8** %argv.0, align 8              ; <i8*> [#uses=1]
   %tmp9 = icmp eq i8* %tmp8, null                 ; <i1> [#uses=1]
   br i1 %tmp9, label %bb7, label %bb6
 
 bb6:                                              ; preds = %bb5
-  %tmp10 = load i8** %argv.0, align 8             ; <i8*> [#uses=1]
-  %tmp11 = load i8* %tmp10, align 1               ; <i8> [#uses=1]
+  %tmp10 = load i8*, i8** %argv.0, align 8             ; <i8*> [#uses=1]
+  %tmp11 = load i8, i8* %tmp10, align 1               ; <i8> [#uses=1]
   %tmp12 = icmp eq i8 %tmp11, 0                   ; <i1> [#uses=1]
   br i1 %tmp12, label %bb7, label %bb8
 
@@ -47,7 +47,7 @@ bb7:                                              ; preds = %bb6, %bb5, %bb2
   br label %bb9
 
 bb8:                                              ; preds = %bb6
-  %tmp13 = load i8** %argv.0, align 8             ; <i8*> [#uses=1]
+  %tmp13 = load i8*, i8** %argv.0, align 8             ; <i8*> [#uses=1]
   %tmp14 = call i64 @f5(i8* %tmp13) nounwind      ; <i64> [#uses=0]
   br label %bb9
 
diff --git a/test/Transforms/JumpThreading/phi-eq.ll b/test/Transforms/JumpThreading/phi-eq.ll
index e05d5ee7c974..75e8cc81fed8 100644
--- a/test/Transforms/JumpThreading/phi-eq.ll
+++ b/test/Transforms/JumpThreading/phi-eq.ll
@@ -39,7 +39,7 @@ if.then:                                          ; preds = %do.body
   br label %if.end
 
 if.else:                                          ; preds = %do.body
-  call void @g_assertion_message_expr(i8* null, i8* getelementptr inbounds ([10 x i8]* @.str2, i32 0, i32 0), i32 581, i8* getelementptr inbounds ([62 x i8]* @__PRETTY_FUNCTION__.copy_filter_list, i32 0, i32 0), i8* getelementptr inbounds ([22 x i8]* @.str12, i32 0, i32 0)) noreturn
+  call void @g_assertion_message_expr(i8* null, i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str2, i32 0, i32 0), i32 581, i8* getelementptr inbounds ([62 x i8], [62 x i8]* @__PRETTY_FUNCTION__.copy_filter_list, i32 0, i32 0), i8* getelementptr inbounds ([22 x i8], [22 x i8]* @.str12, i32 0, i32 0)) noreturn
   unreachable
 
 if.end:                                           ; preds = %if.then
@@ -66,7 +66,7 @@ sw.bb3.i:                                         ; preds = %do.end
   br label %get_filter_list.exit
 
 sw.default.i:                                     ; preds = %do.end
-  call void @g_assertion_message(i8* null, i8* getelementptr inbounds ([10 x i8]* @.str2, i32 0, i32 0), i32 408, i8* getelementptr inbounds ([44 x i8]* @__PRETTY_FUNCTION__.get_filter_list, i32 0, i32 0), i8* null) noreturn nounwind
+  call void @g_assertion_message(i8* null, i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str2, i32 0, i32 0), i32 408, i8* getelementptr inbounds ([44 x i8], [44 x i8]* @__PRETTY_FUNCTION__.get_filter_list, i32 0, i32 0), i8* null) noreturn nounwind
   unreachable
 
 get_filter_list.exit:                             ; preds = %sw.bb3.i, %sw.bb2.i, %sw.bb1.i, %sw.bb.i
@@ -91,40 +91,40 @@ sw.bb3.i4:                                        ; preds = %get_filter_list.exi
   br label %get_filter_list.exit6
 
 sw.default.i5:                                    ; preds = %get_filter_list.exit
-  call void @g_assertion_message(i8* null, i8* getelementptr inbounds ([10 x i8]* @.str2, i32 0, i32 0), i32 408, i8* getelementptr inbounds ([44 x i8]* @__PRETTY_FUNCTION__.get_filter_list, i32 0, i32 0), i8* null) noreturn nounwind
+  call void @g_assertion_message(i8* null, i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str2, i32 0, i32 0), i32 408, i8* getelementptr inbounds ([44 x i8], [44 x i8]* @__PRETTY_FUNCTION__.get_filter_list, i32 0, i32 0), i8* null) noreturn nounwind
   unreachable
 
 ; CHECK: get_filter_list.exit
 get_filter_list.exit6:                            ; preds = %sw.bb3.i4, %sw.bb2.i3, %sw.bb1.i2, %sw.bb.i1
   %1 = phi %struct._GList** [ @display_edited_filters, %sw.bb3.i4 ], [ @capture_edited_filters, %sw.bb2.i3 ], [ @display_filters, %sw.bb1.i2 ], [ @capture_filters, %sw.bb.i1 ]
 ; CHECK: %2 = load
-  %2 = load %struct._GList** %1, align 8
+  %2 = load %struct._GList*, %struct._GList** %1, align 8
 ; We should have jump-threading insert an additional load here for the value
 ; coming out of the first switch, which is picked up by a subsequent phi
-; CHECK: {{%\.pr = load %[^%]* %0}}
+; CHECK: %.pr = load %struct._GList*, %struct._GList** %0
 ; CHECK-NEXT:  br label %while.cond
   br label %while.cond
 
 ; CHECK: while.cond
 while.cond:                                       ; preds = %while.body, %get_filter_list.exit6
 ; CHECK: {{= phi .*%.pr}}
-  %3 = load %struct._GList** %0, align 8
+  %3 = load %struct._GList*, %struct._GList** %0, align 8
 ; CHECK: tobool
   %tobool = icmp ne %struct._GList* %3, null
   br i1 %tobool, label %while.body, label %while.end
 
 while.body:                                       ; preds = %while.cond
-  %4 = load %struct._GList** %0, align 8
-  %5 = load %struct._GList** %0, align 8
+  %4 = load %struct._GList*, %struct._GList** %0, align 8
+  %5 = load %struct._GList*, %struct._GList** %0, align 8
   %call2 = call %struct._GList* @g_list_first(%struct._GList* %5)
-  %data.i = getelementptr inbounds %struct._GList* %call2, i32 0, i32 0
-  %6 = load i8** %data.i, align 8
+  %data.i = getelementptr inbounds %struct._GList, %struct._GList* %call2, i32 0, i32 0
+  %6 = load i8*, i8** %data.i, align 8
   %7 = bitcast i8* %6 to %struct.filter_def*
-  %name.i = getelementptr inbounds %struct.filter_def* %7, i32 0, i32 0
-  %8 = load i8** %name.i, align 8
+  %name.i = getelementptr inbounds %struct.filter_def, %struct.filter_def* %7, i32 0, i32 0
+  %8 = load i8*, i8** %name.i, align 8
   call void @g_free(i8* %8) nounwind
-  %strval.i = getelementptr inbounds %struct.filter_def* %7, i32 0, i32 1
-  %9 = load i8** %strval.i, align 8
+  %strval.i = getelementptr inbounds %struct.filter_def, %struct.filter_def* %7, i32 0, i32 1
+  %9 = load i8*, i8** %strval.i, align 8
   call void @g_free(i8* %9) nounwind
   %10 = bitcast %struct.filter_def* %7 to i8*
   call void @g_free(i8* %10) nounwind
@@ -136,7 +136,7 @@ while.end:                                        ; preds = %while.cond
   br label %do.body4
 
 do.body4:                                         ; preds = %while.end
-  %11 = load %struct._GList** %0, align 8
+  %11 = load %struct._GList*, %struct._GList** %0, align 8
   %call5 = call i32 @g_list_length(%struct._GList* %11)
   %cmp6 = icmp eq i32 %call5, 0
   br i1 %cmp6, label %if.then7, label %if.else8
@@ -145,7 +145,7 @@ if.then7:                                         ; preds = %do.body4
   br label %if.end9
 
 if.else8:                                         ; preds = %do.body4
-  call void @g_assertion_message_expr(i8* null, i8* getelementptr inbounds ([10 x i8]* @.str2, i32 0, i32 0), i32 600, i8* getelementptr inbounds ([62 x i8]* @__PRETTY_FUNCTION__.copy_filter_list, i32 0, i32 0), i8* getelementptr inbounds ([31 x i8]* @.str13, i32 0, i32 0)) noreturn
+  call void @g_assertion_message_expr(i8* null, i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str2, i32 0, i32 0), i32 600, i8* getelementptr inbounds ([62 x i8], [62 x i8]* @__PRETTY_FUNCTION__.copy_filter_list, i32 0, i32 0), i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str13, i32 0, i32 0)) noreturn
   unreachable
 
 if.end9:                                          ; preds = %if.then7
@@ -160,21 +160,21 @@ while.cond11:                                     ; preds = %cond.end, %do.end10
   br i1 %tobool12, label %while.body13, label %while.end16
 
 while.body13:                                     ; preds = %while.cond11
-  %data = getelementptr inbounds %struct._GList* %cond10, i32 0, i32 0
-  %12 = load i8** %data, align 8
+  %data = getelementptr inbounds %struct._GList, %struct._GList* %cond10, i32 0, i32 0
+  %12 = load i8*, i8** %data, align 8
   %13 = bitcast i8* %12 to %struct.filter_def*
-  %14 = load %struct._GList** %0, align 8
-  %name = getelementptr inbounds %struct.filter_def* %13, i32 0, i32 0
-  %15 = load i8** %name, align 8
-  %strval = getelementptr inbounds %struct.filter_def* %13, i32 0, i32 1
-  %16 = load i8** %strval, align 8
+  %14 = load %struct._GList*, %struct._GList** %0, align 8
+  %name = getelementptr inbounds %struct.filter_def, %struct.filter_def* %13, i32 0, i32 0
+  %15 = load i8*, i8** %name, align 8
+  %strval = getelementptr inbounds %struct.filter_def, %struct.filter_def* %13, i32 0, i32 1
+  %16 = load i8*, i8** %strval, align 8
   %call.i7 = call noalias i8* @g_malloc(i64 16) nounwind
   %17 = bitcast i8* %call.i7 to %struct.filter_def*
   %call1.i = call noalias i8* @g_strdup(i8* %15) nounwind
-  %name.i8 = getelementptr inbounds %struct.filter_def* %17, i32 0, i32 0
+  %name.i8 = getelementptr inbounds %struct.filter_def, %struct.filter_def* %17, i32 0, i32 0
   store i8* %call1.i, i8** %name.i8, align 8
   %call2.i = call noalias i8* @g_strdup(i8* %16) nounwind
-  %strval.i9 = getelementptr inbounds %struct.filter_def* %17, i32 0, i32 1
+  %strval.i9 = getelementptr inbounds %struct.filter_def, %struct.filter_def* %17, i32 0, i32 1
   store i8* %call2.i, i8** %strval.i9, align 8
   %18 = bitcast %struct.filter_def* %17 to i8*
   %call3.i = call %struct._GList* @g_list_append(%struct._GList* %14, i8* %18) nounwind
@@ -183,8 +183,8 @@ while.body13:                                     ; preds = %while.cond11
   br i1 %tobool15, label %cond.true, label %cond.false
 
 cond.true:                                        ; preds = %while.body13
-  %next = getelementptr inbounds %struct._GList* %cond10, i32 0, i32 1
-  %19 = load %struct._GList** %next, align 8
+  %next = getelementptr inbounds %struct._GList, %struct._GList* %cond10, i32 0, i32 1
+  %19 = load %struct._GList*, %struct._GList** %next, align 8
   br label %cond.end
 
 cond.false:                                       ; preds = %while.body13
diff --git a/test/Transforms/JumpThreading/select.ll b/test/Transforms/JumpThreading/select.ll
index 545e86c082f4..d0df7725f722 100644
--- a/test/Transforms/JumpThreading/select.ll
+++ b/test/Transforms/JumpThreading/select.ll
@@ -135,7 +135,7 @@ L4:
 ; CHECK: icmp
 define void @test_switch_default(i32* nocapture %status) nounwind {
 entry:
-  %0 = load i32* %status, align 4
+  %0 = load i32, i32* %status, align 4
   switch i32 %0, label %L2 [
     i32 5061, label %L1
     i32 0, label %L2
@@ -146,7 +146,7 @@ L1:
   br label %L2
 
 L2:
-  %1 = load i32* %status, align 4
+  %1 = load i32, i32* %status, align 4
   %cmp57.i = icmp eq i32 %1, 0
   br i1 %cmp57.i, label %L3, label %L4
 
diff --git a/test/Transforms/JumpThreading/thread-cmp.ll b/test/Transforms/JumpThreading/thread-cmp.ll
new file mode 100644
index 000000000000..950896744762
--- /dev/null
+++ b/test/Transforms/JumpThreading/thread-cmp.ll
@@ -0,0 +1,69 @@
+; RUN: opt -S -jump-threading %s | FileCheck %s
+; When simplify a branch based on LVI predicates, we should replace the 
+; comparison itself with a constant (when possible) in case it's otherwise used.
+
+define i32 @test(i32* %p) {
+; CHECK-LABEL: @test
+; CHECK: icmp eq
+; CHECK-NEXT: br i1 %cmp, label %exit2, label %exit1
+; CHECK-NOT: icmp ne
+entry:
+  %cmp = icmp eq i32* %p, null
+  br i1 %cmp, label %is_null, label %not_null
+is_null:
+  %cmp2 = icmp ne i32* %p, null
+  br i1 %cmp2, label %exit1, label %exit2
+not_null:
+  %cmp3 = icmp ne i32* %p, null
+  br i1 %cmp3, label %exit1, label %exit2
+exit1:
+  ret i32 0
+exit2:
+  ret i32 1
+}
+
+declare void @use(i1)
+
+; It would not be legal to replace %cmp2 (well, in this case it actually is, 
+; but that's a CSE problem, not a LVI/jump threading problem)
+define i32 @test_negative(i32* %p) {
+; CHECK-LABEL: @test
+; CHECK: icmp ne
+; CHECK: icmp eq
+; CHECK-NEXT: br i1 %cmp, label %exit2, label %exit1
+; CHECK-NOT: icmp ne
+entry:
+  %cmp2 = icmp ne i32* %p, null
+  call void @use(i1 %cmp2)
+  %cmp = icmp eq i32* %p, null
+  br i1 %cmp, label %is_null, label %not_null
+is_null:
+  br i1 %cmp2, label %exit1, label %exit2
+not_null:
+  br i1 %cmp2, label %exit1, label %exit2
+exit1:
+  ret i32 0
+exit2:
+  ret i32 1
+}
+
+; In this case, we can remove cmp2 because it's otherwise unused
+define i32 @test2(i32* %p) {
+; CHECK-LABEL: @test
+; CHECK-LABEL: entry:
+; CHECK-NEXT: icmp eq
+; CHECK-NEXT: br i1 %cmp, label %exit2, label %exit1
+; CHECK-NOT: icmp ne
+entry:
+  %cmp2 = icmp ne i32* %p, null
+  %cmp = icmp eq i32* %p, null
+  br i1 %cmp, label %is_null, label %not_null
+is_null:
+  br i1 %cmp2, label %exit1, label %exit2
+not_null:
+  br i1 %cmp2, label %exit1, label %exit2
+exit1:
+  ret i32 0
+exit2:
+  ret i32 1
+}
diff --git a/test/Transforms/JumpThreading/thread-loads.ll b/test/Transforms/JumpThreading/thread-loads.ll
index 4351f9918109..f76c1ec51857 100644
--- a/test/Transforms/JumpThreading/thread-loads.ll
+++ b/test/Transforms/JumpThreading/thread-loads.ll
@@ -8,7 +8,7 @@ target triple = "i386-apple-darwin7"
 define i32 @test1(i32* %P) nounwind {
 ; CHECK-LABEL: @test1(
 entry:
-	%0 = tail call i32 (...)* @f1() nounwind		; <i32> [#uses=1]
+	%0 = tail call i32 (...) @f1() nounwind		; <i32> [#uses=1]
 	%1 = icmp eq i32 %0, 0		; <i1> [#uses=1]
 	br i1 %1, label %bb1, label %bb
 
@@ -21,12 +21,12 @@ bb:		; preds = %entry
 
 bb1:		; preds = %entry, %bb
 	%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]		; <i32> [#uses=2]
-	%2 = load i32* %P, align 4		; <i32> [#uses=1]
+	%2 = load i32, i32* %P, align 4		; <i32> [#uses=1]
 	%3 = icmp sgt i32 %2, 36		; <i1> [#uses=1]
 	br i1 %3, label %bb3, label %bb2
 
 bb2:		; preds = %bb1
-	%4 = tail call i32 (...)* @f2() nounwind		; <i32> [#uses=0]
+	%4 = tail call i32 (...) @f2() nounwind		; <i32> [#uses=0]
 	ret i32 %res.0
 
 bb3:		; preds = %bb1
@@ -47,7 +47,7 @@ declare i32 @f2(...)
 define i32 @test2(i32* %P) nounwind {
 ; CHECK-LABEL: @test2(
 entry:
-	%0 = tail call i32 (...)* @f1() nounwind		; <i32> [#uses=1]
+	%0 = tail call i32 (...) @f1() nounwind		; <i32> [#uses=1]
 	%1 = icmp eq i32 %0, 0		; <i1> [#uses=1]
 	br i1 %1, label %bb1, label %bb
 
@@ -60,12 +60,12 @@ bb:		; preds = %entry
 
 bb1:		; preds = %entry, %bb
 	%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
-	%2 = load i32* %P, align 4, !tbaa !0
+	%2 = load i32, i32* %P, align 4, !tbaa !0
 	%3 = icmp sgt i32 %2, 36
 	br i1 %3, label %bb3, label %bb2
 
 bb2:		; preds = %bb1
-	%4 = tail call i32 (...)* @f2() nounwind
+	%4 = tail call i32 (...) @f2() nounwind
 	ret i32 %res.0
 
 bb3:		; preds = %bb1
@@ -83,16 +83,16 @@ define i32 @test3(i8** %x, i1 %f) {
 ; CHECK-LABEL: @test3(
 entry:
   %0 = bitcast i8** %x to i32**
-  %1 = load i32** %0, align 8
+  %1 = load i32*, i32** %0, align 8
   br i1 %f, label %if.end57, label %if.then56
-; CHECK: %[[LOAD:.*]] = load i32**
+; CHECK: %[[LOAD:.*]] = load i32*, i32**
 ; CHECK: %[[CAST:.*]] = bitcast i32* %[[LOAD]] to i8*
 
 if.then56:
   br label %if.end57
 
 if.end57:
-  %2 = load i8** %x, align 8
+  %2 = load i8*, i8** %x, align 8
   %tobool59 = icmp eq i8* %2, null
   br i1 %tobool59, label %return, label %if.then60
 ; CHECK: %[[PHI:.*]] = phi i8* [ %[[CAST]], %[[PRED:[^ ]+]] ], [ %[[CAST]], %[[PRED]] ]
diff --git a/test/Transforms/LCSSA/2006-06-03-IncorrectIDFPhis.ll b/test/Transforms/LCSSA/2006-06-03-IncorrectIDFPhis.ll
index dd43c8837901..a6abfa5f3c4d 100644
--- a/test/Transforms/LCSSA/2006-06-03-IncorrectIDFPhis.ll
+++ b/test/Transforms/LCSSA/2006-06-03-IncorrectIDFPhis.ll
@@ -10,10 +10,10 @@ no_exit:                ; preds = %endif, %entry
         %SJE.0.0 = phi %struct.SetJmpMapEntry* [ %tmp.24, %endif ], [ null, %entry ]            ; <%struct.SetJmpMapEntry*> [#uses=1]
         br i1 false, label %then, label %endif
 then:           ; preds = %no_exit
-        %tmp.20 = getelementptr %struct.SetJmpMapEntry* %SJE.0.0, i32 0, i32 1          ; <i32*> [#uses=0]
+        %tmp.20 = getelementptr %struct.SetJmpMapEntry, %struct.SetJmpMapEntry* %SJE.0.0, i32 0, i32 1          ; <i32*> [#uses=0]
         ret void
 endif:          ; preds = %no_exit
-        %tmp.24 = load %struct.SetJmpMapEntry** null            ; <%struct.SetJmpMapEntry*> [#uses=1]
+        %tmp.24 = load %struct.SetJmpMapEntry*, %struct.SetJmpMapEntry** null            ; <%struct.SetJmpMapEntry*> [#uses=1]
         br i1 false, label %UnifiedReturnBlock, label %no_exit
 UnifiedReturnBlock:             ; preds = %endif, %entry
         ret void
diff --git a/test/Transforms/LCSSA/2006-07-09-NoDominator.ll b/test/Transforms/LCSSA/2006-07-09-NoDominator.ll
index b03f09ac20e5..bc3d150fbdfe 100644
--- a/test/Transforms/LCSSA/2006-07-09-NoDominator.ll
+++ b/test/Transforms/LCSSA/2006-07-09-NoDominator.ll
@@ -11,10 +11,10 @@ loopentry:		; preds = %endif, %entry
 no_exit:		; preds = %loopentry
 	br i1 false, label %then, label %endif
 then:		; preds = %no_exit
-	%tmp.21 = getelementptr %struct.SetJmpMapEntry* %SJE.0, i32 0, i32 1		; <i32*> [#uses=0]
+	%tmp.21 = getelementptr %struct.SetJmpMapEntry, %struct.SetJmpMapEntry* %SJE.0, i32 0, i32 1		; <i32*> [#uses=0]
 	br label %return
 endif:		; preds = %no_exit
-	%tmp.25 = load %struct.SetJmpMapEntry** null		; <%struct.SetJmpMapEntry*> [#uses=1]
+	%tmp.25 = load %struct.SetJmpMapEntry*, %struct.SetJmpMapEntry** null		; <%struct.SetJmpMapEntry*> [#uses=1]
 	br label %loopentry
 loopexit:		; preds = %loopentry
 	br label %return
diff --git a/test/Transforms/LCSSA/2007-07-12-LICM-2.ll b/test/Transforms/LCSSA/2007-07-12-LICM-2.ll
index 2c5815cef33a..f5d3f7e2b1c8 100644
--- a/test/Transforms/LCSSA/2007-07-12-LICM-2.ll
+++ b/test/Transforms/LCSSA/2007-07-12-LICM-2.ll
@@ -4,7 +4,7 @@ entry:
 	br label %bb7
 
 bb7:		; preds = %bb7, %entry
-	%tmp39 = load <4 x float>* null		; <<4 x float>> [#uses=1]
+	%tmp39 = load <4 x float>, <4 x float>* null		; <<4 x float>> [#uses=1]
 	%tmp40 = fadd <4 x float> %tmp39, < float 2.000000e+00, float 3.000000e+00, float 1.000000e+00, float 0.000000e+00 >		; <<4 x float>> [#uses=1]
 	%tmp43 = fadd <4 x float> %tmp40, < float 1.000000e+00, float 1.000000e+00, float 0.000000e+00, float 2.000000e+00 >		; <<4 x float>> [#uses=1]
 	%tmp46 = fadd <4 x float> %tmp43, < float 3.000000e+00, float 0.000000e+00, float 2.000000e+00, float 4.000000e+00 >		; <<4 x float>> [#uses=1]
diff --git a/test/Transforms/LCSSA/2007-07-12-LICM-3.ll b/test/Transforms/LCSSA/2007-07-12-LICM-3.ll
index 7e0d3c63b13c..689b6eaff8e0 100644
--- a/test/Transforms/LCSSA/2007-07-12-LICM-3.ll
+++ b/test/Transforms/LCSSA/2007-07-12-LICM-3.ll
@@ -8,7 +8,7 @@ bb:             ; preds = %bb56, %entry
         br label %bb7
 
 bb7:            ; preds = %bb7, %bb
-        %tmp39 = load <4 x float>* null         ; <<4 x float>> [#uses=1]
+        %tmp39 = load <4 x float>, <4 x float>* null         ; <<4 x float>> [#uses=1]
         %tmp40 = fadd <4 x float> %tmp39, < float 2.000000e+00, float 3.000000e+00, float 1.000000e+00, float 0.000000e+00 >             ; <<4 x float>> [#uses=1]
         %tmp43 = fadd <4 x float> %tmp40, < float 1.000000e+00, float 1.000000e+00, float 0.000000e+00, float 2.000000e+00 >             ; <<4 x float>> [#uses=1]
         %tmp46 = fadd <4 x float> %tmp43, < float 3.000000e+00, float 0.000000e+00, float 2.000000e+00, float 4.000000e+00 >             ; <<4 x float>> [#uses=1]
diff --git a/test/Transforms/LCSSA/2007-07-12-LICM.ll b/test/Transforms/LCSSA/2007-07-12-LICM.ll
index 8c07aa2ec352..f1785edc2af2 100644
--- a/test/Transforms/LCSSA/2007-07-12-LICM.ll
+++ b/test/Transforms/LCSSA/2007-07-12-LICM.ll
@@ -4,7 +4,7 @@ entry:
 	br label %bb7
 
 bb7:		; preds = %bb7, %entry
-	%tmp39 = load <4 x float>* null		; <<4 x float>> [#uses=1]
+	%tmp39 = load <4 x float>, <4 x float>* null		; <<4 x float>> [#uses=1]
 	%tmp40 = fadd <4 x float> %tmp39, < float 2.000000e+00, float 3.000000e+00, float 1.000000e+00, float 0.000000e+00 >		; <<4 x float>> [#uses=0]
 	store <4 x float> zeroinitializer, <4 x float>* null
 	br i1 false, label %bb7, label %bb56
diff --git a/test/Transforms/LCSSA/invoke-dest.ll b/test/Transforms/LCSSA/invoke-dest.ll
index 22b320296afd..1e3f178c7e6c 100644
--- a/test/Transforms/LCSSA/invoke-dest.ll
+++ b/test/Transforms/LCSSA/invoke-dest.ll
@@ -17,7 +17,7 @@ bb.i:		; preds = %entry
 	br label %_ZN7cObjectnwEj.exit
 
 _ZN7cObjectnwEj.exit:		; preds = %bb.i, %entry
-	invoke void @_ZN7cObjectC2EPKc(i8* undef, i8* getelementptr ([12 x i8]* @.str21179, i32 0, i32 0))
+	invoke void @_ZN7cObjectC2EPKc(i8* undef, i8* getelementptr ([12 x i8], [12 x i8]* @.str21179, i32 0, i32 0))
 			to label %bb1 unwind label %lpad
 
 bb1:		; preds = %_ZN7cObjectnwEj.exit
@@ -39,7 +39,7 @@ bb2:		; preds = %_ZNK5cGate4sizeEv.exit122
 	unreachable
 
 bb8:		; preds = %_ZNK5cGate4sizeEv.exit122
-	%tmp = invoke i8* @_ZN7cModule3parEPKc(i8* undef, i8* getelementptr ([10 x i8]* @.str25183, i32 0, i32 0))
+	%tmp = invoke i8* @_ZN7cModule3parEPKc(i8* undef, i8* getelementptr ([10 x i8], [10 x i8]* @.str25183, i32 0, i32 0))
 			to label %invcont9 unwind label %lpad119		; <i8*> [#uses=1]
 
 invcont9:		; preds = %bb8
@@ -54,7 +54,7 @@ invcont11:		; preds = %invcont10
 	br i1 undef, label %bb12, label %bb18
 
 bb12:		; preds = %invcont11
-	invoke void (i8*, i8*, ...)* @_ZN6cEnvir6printfEPKcz(i8* null, i8* getelementptr ([3 x i8]* @.str12, i32 0, i32 0), i32 undef)
+	invoke void (i8*, i8*, ...) @_ZN6cEnvir6printfEPKcz(i8* null, i8* getelementptr ([3 x i8], [3 x i8]* @.str12, i32 0, i32 0), i32 undef)
 			to label %bb.i.i159 unwind label %lpad119
 
 bb.i.i159:		; preds = %bb12
@@ -77,7 +77,7 @@ invcont35:		; preds = %bb34
 	br i1 undef, label %bb49, label %bb61
 
 bb49:		; preds = %invcont35
-	invoke void (i8*, i8*, ...)* @_ZNK13cSimpleModule5errorEPKcz(i8* undef, i8* getelementptr ([92 x i8]* @.str32190, i32 0, i32 0))
+	invoke void (i8*, i8*, ...) @_ZNK13cSimpleModule5errorEPKcz(i8* undef, i8* getelementptr ([92 x i8], [92 x i8]* @.str32190, i32 0, i32 0))
 			to label %bb51 unwind label %lpad119
 
 bb51:		; preds = %bb49
@@ -87,7 +87,7 @@ bb61:		; preds = %invcont35
 	br label %bb106
 
 .noexc:		; preds = %bb106
-	invoke void @_ZN7cObjectC2EPKc(i8* undef, i8* getelementptr ([25 x i8]* @.str41, i32 0, i32 0))
+	invoke void @_ZN7cObjectC2EPKc(i8* undef, i8* getelementptr ([25 x i8], [25 x i8]* @.str41, i32 0, i32 0))
 			to label %bb102 unwind label %lpad123
 
 bb102:		; preds = %.noexc
@@ -99,7 +99,7 @@ invcont103:		; preds = %bb102
 			to label %invcont104 unwind label %lpad119
 
 invcont104:		; preds = %invcont103
-	%tmp3 = invoke i32 @_ZN13cSimpleModule11sendDelayedEP8cMessagedPKci(i8* undef, i8* undef, double 0.000000e+00, i8* getelementptr ([4 x i8]* @.str17175, i32 0, i32 0), i32 undef)
+	%tmp3 = invoke i32 @_ZN13cSimpleModule11sendDelayedEP8cMessagedPKci(i8* undef, i8* undef, double 0.000000e+00, i8* getelementptr ([4 x i8], [4 x i8]* @.str17175, i32 0, i32 0), i32 undef)
 			to label %invcont105 unwind label %lpad119		; <i32> [#uses=0]
 
 invcont105:		; preds = %invcont104
diff --git a/test/Transforms/LCSSA/unreachable-use.ll b/test/Transforms/LCSSA/unreachable-use.ll
index 71ae134e314c..c9e456c17474 100644
--- a/test/Transforms/LCSSA/unreachable-use.ll
+++ b/test/Transforms/LCSSA/unreachable-use.ll
@@ -1,9 +1,11 @@
-; RUN: opt < %s -lcssa -S -verify-loop-info | grep "[%]tmp33 = load i1\*\* [%]tmp"
+; RUN: opt < %s -lcssa -S -verify-loop-info | FileCheck %s
 ; PR6546
 
 ; LCSSA doesn't need to transform uses in blocks not reachable
 ; from the entry block.
 
+; CHECK: %tmp33 = load i1*, i1** %tmp
+
 define fastcc void @dfs() nounwind {
 bb:
   br label %bb44
@@ -19,7 +21,7 @@ bb15:
   br label %bb44
 
 bb32:
-  %tmp33 = load i1** %tmp, align 8
+  %tmp33 = load i1*, i1** %tmp, align 8
   br label %bb45
 
 bb45:
diff --git a/test/Transforms/LICM/2003-02-26-LoopExitNotDominated.ll b/test/Transforms/LICM/2003-02-26-LoopExitNotDominated.ll
index ff20312ec372..1b50a6c87af7 100644
--- a/test/Transforms/LICM/2003-02-26-LoopExitNotDominated.ll
+++ b/test/Transforms/LICM/2003-02-26-LoopExitNotDominated.ll
@@ -7,7 +7,7 @@ bb3:
 	%X = alloca [2 x i64]		; <[2 x i64]*> [#uses=1]
 	br i1 false, label %bb13, label %bb4
 bb4:		; preds = %bb3
-	%reg3011 = getelementptr [2 x i64]* %X, i64 0, i64 0		; <i64*> [#uses=1]
+	%reg3011 = getelementptr [2 x i64], [2 x i64]* %X, i64 0, i64 0		; <i64*> [#uses=1]
 	br label %bb8
 bb8:		; preds = %bb8, %bb4
 	store i64 0, i64* %reg3011
diff --git a/test/Transforms/LICM/2003-05-02-LoadHoist.ll b/test/Transforms/LICM/2003-05-02-LoadHoist.ll
index 71d3e789aa08..2f94dff4efd7 100644
--- a/test/Transforms/LICM/2003-05-02-LoadHoist.ll
+++ b/test/Transforms/LICM/2003-05-02-LoadHoist.ll
@@ -10,12 +10,12 @@
 declare void @foo()
 
 define i32 @test(i1 %c) {
-	%A = load i32* @X		; <i32> [#uses=1]
+	%A = load i32, i32* @X		; <i32> [#uses=1]
 	br label %Loop
 Loop:		; preds = %Loop, %0
 	call void @foo( )
         ;; Should not hoist this load!
-	%B = load i32* @X		; <i32> [#uses=1]
+	%B = load i32, i32* @X		; <i32> [#uses=1]
 	br i1 %c, label %Loop, label %Out
 Out:		; preds = %Loop
 	%C = sub i32 %A, %B		; <i32> [#uses=1]
diff --git a/test/Transforms/LICM/2004-09-14-AliasAnalysisInvalidate.ll b/test/Transforms/LICM/2004-09-14-AliasAnalysisInvalidate.ll
index 16f4fed34ec3..73862db69819 100644
--- a/test/Transforms/LICM/2004-09-14-AliasAnalysisInvalidate.ll
+++ b/test/Transforms/LICM/2004-09-14-AliasAnalysisInvalidate.ll
@@ -7,8 +7,8 @@ define void @test() {
 Outer:		; preds = %Next, %0
 	br label %Inner
 Inner:		; preds = %Inner, %Outer
-	%tmp.114.i.i.i = load i8** @PL_regcomp_parse		; <i8*> [#uses=1]
-	%tmp.115.i.i.i = load i8* %tmp.114.i.i.i		; <i8> [#uses=0]
+	%tmp.114.i.i.i = load i8*, i8** @PL_regcomp_parse		; <i8*> [#uses=1]
+	%tmp.115.i.i.i = load i8, i8* %tmp.114.i.i.i		; <i8> [#uses=0]
 	store i8* null, i8** @PL_regcomp_parse
 	br i1 false, label %Inner, label %Next
 Next:		; preds = %Inner
diff --git a/test/Transforms/LICM/2004-11-17-UndefIndexCrash.ll b/test/Transforms/LICM/2004-11-17-UndefIndexCrash.ll
index a119865f0519..9416028ef2e7 100644
--- a/test/Transforms/LICM/2004-11-17-UndefIndexCrash.ll
+++ b/test/Transforms/LICM/2004-11-17-UndefIndexCrash.ll
@@ -11,10 +11,10 @@ define void @main() {
 __main.entry:
 	br label %invoke_cont.3
 invoke_cont.3:		; preds = %invoke_cont.3, %__main.entry
-	%tmp.34.i.i502.7 = getelementptr %struct.roadlet* null, i32 0, i32 3, i32 7		; <%struct.roadlet* (%struct.roadlet*, %struct.vehicle*, i32)**> [#uses=1]
+	%tmp.34.i.i502.7 = getelementptr %struct.roadlet, %struct.roadlet* null, i32 0, i32 3, i32 7		; <%struct.roadlet* (%struct.roadlet*, %struct.vehicle*, i32)**> [#uses=1]
 	store %struct.roadlet* (%struct.roadlet*, %struct.vehicle*, i32)* @_Z11return_nullP7roadletP7vehicle9direction, %struct.roadlet* (%struct.roadlet*, %struct.vehicle*, i32)** %tmp.34.i.i502.7
 	store %struct.roadlet* (%struct.roadlet*, %struct.vehicle*, i32)* @_Z14lane_switch_okP7roadletP7vehicle9direction, %struct.roadlet* (%struct.roadlet*, %struct.vehicle*, i32)** null
-	%tmp.4.i.i339 = getelementptr %struct.roadlet* null, i32 0, i32 3, i32 undef		; <%struct.roadlet* (%struct.roadlet*, %struct.vehicle*, i32)**> [#uses=1]
+	%tmp.4.i.i339 = getelementptr %struct.roadlet, %struct.roadlet* null, i32 0, i32 3, i32 undef		; <%struct.roadlet* (%struct.roadlet*, %struct.vehicle*, i32)**> [#uses=1]
 	store %struct.roadlet* (%struct.roadlet*, %struct.vehicle*, i32)* @_Z11return_nullP7roadletP7vehicle9direction, %struct.roadlet* (%struct.roadlet*, %struct.vehicle*, i32)** %tmp.4.i.i339
 	br label %invoke_cont.3
 }
diff --git a/test/Transforms/LICM/2007-05-22-VolatileSink.ll b/test/Transforms/LICM/2007-05-22-VolatileSink.ll
index 94511cc9c156..f5ce86b7245a 100644
--- a/test/Transforms/LICM/2007-05-22-VolatileSink.ll
+++ b/test/Transforms/LICM/2007-05-22-VolatileSink.ll
@@ -10,8 +10,8 @@ entry:
 	br label %bb6
 
 bb:		; preds = %bb6
-	%tmp2 = load volatile i32* %DataIn		; <i32> [#uses=1]
-	%tmp3 = getelementptr [64 x i32]* %buffer, i32 0, i32 %i.0		; <i32*> [#uses=1]
+	%tmp2 = load volatile i32, i32* %DataIn		; <i32> [#uses=1]
+	%tmp3 = getelementptr [64 x i32], [64 x i32]* %buffer, i32 0, i32 %i.0		; <i32*> [#uses=1]
 	store i32 %tmp2, i32* %tmp3
 	%tmp5 = add i32 %i.0, 1		; <i32> [#uses=1]
 	br label %bb6
@@ -26,8 +26,8 @@ bb6:		; preds = %bb, %entry
 bb12:		; preds = %bb22
 	%tmp14 = mul i32 %j.1, 8		; <i32> [#uses=1]
 	%tmp16 = add i32 %tmp14, %i.1		; <i32> [#uses=1]
-	%tmp17 = getelementptr [64 x i32]* %buffer, i32 0, i32 %tmp16		; <i32*> [#uses=1]
-	%tmp18 = load i32* %tmp17		; <i32> [#uses=1]
+	%tmp17 = getelementptr [64 x i32], [64 x i32]* %buffer, i32 0, i32 %tmp16		; <i32*> [#uses=1]
+	%tmp18 = load i32, i32* %tmp17		; <i32> [#uses=1]
 	store volatile i32 %tmp18, i32* %DataOut
 	%tmp21 = add i32 %j.1, 1		; <i32> [#uses=1]
 	br label %bb22
diff --git a/test/Transforms/LICM/2007-07-30-AliasSet.ll b/test/Transforms/LICM/2007-07-30-AliasSet.ll
index 8ecd1bcee486..3e4fbb0a06e0 100644
--- a/test/Transforms/LICM/2007-07-30-AliasSet.ll
+++ b/test/Transforms/LICM/2007-07-30-AliasSet.ll
@@ -17,12 +17,12 @@ bb63.outer:		; preds = %bb73, %bb28
 
 bb35:		; preds = %cond_next60, %bb63.outer
 	%window.34 = phi i32 [ %tmp62, %cond_next60 ], [ 0, %bb63.outer ]		; <i32> [#uses=1]
-	%tmp44 = getelementptr [4 x i32]* null, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp46 = load i32* %tmp44, align 4		; <i32> [#uses=0]
+	%tmp44 = getelementptr [4 x i32], [4 x i32]* null, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp46 = load i32, i32* %tmp44, align 4		; <i32> [#uses=0]
 	br i1 false, label %cond_true50, label %cond_next60
 
 cond_true50:		; preds = %bb35
-	%tmp59 = getelementptr [4 x i32]* null, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp59 = getelementptr [4 x i32], [4 x i32]* null, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp59, align 4
 	br label %cond_next60
 
diff --git a/test/Transforms/LICM/2007-09-17-PromoteValue.ll b/test/Transforms/LICM/2007-09-17-PromoteValue.ll
index 31abd8c180a5..1d25d17c2e64 100644
--- a/test/Transforms/LICM/2007-09-17-PromoteValue.ll
+++ b/test/Transforms/LICM/2007-09-17-PromoteValue.ll
@@ -14,7 +14,7 @@ blah.i:		; preds = %cond_true.i, %entry
 	br i1 %tmp3.i, label %clear_modes.exit, label %cond_true.i
 
 cond_true.i:		; preds = %blah.i
-	%tmp1.i = getelementptr %struct.decision* null, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp1.i = getelementptr %struct.decision, %struct.decision* null, i32 0, i32 0		; <i8*> [#uses=1]
 	store i8 0, i8* %tmp1.i
 	br label %blah.i
 
@@ -33,7 +33,7 @@ loop.head:              ; preds = %cond.true, %entry
         br i1 %tmp3.i, label %cond.true, label %exit
 
 cond.true:              ; preds = %loop.head
-        %ptr.i = getelementptr i8* %ptr, i32 0          ; <i8*> [#uses=2]
+        %ptr.i = getelementptr i8, i8* %ptr, i32 0          ; <i8*> [#uses=2]
         store i8 0, i8* %ptr.i
         br label %loop.head
 
@@ -50,7 +50,7 @@ loop.head:              ; preds = %cond.true, %entry
         br i1 %tmp3.i, label %exit, label %cond.true
 
 cond.true:              ; preds = %loop.head
-        %ptr.i = getelementptr i8* %p, i32 0          ; <i8*> [#uses=2]
+        %ptr.i = getelementptr i8, i8* %p, i32 0          ; <i8*> [#uses=2]
         store i8 0, i8* %ptr.i
         br label %loop.head
 
diff --git a/test/Transforms/LICM/2008-07-22-LoadGlobalConstant.ll b/test/Transforms/LICM/2008-07-22-LoadGlobalConstant.ll
index d4df26e67abc..a715af032a96 100644
--- a/test/Transforms/LICM/2008-07-22-LoadGlobalConstant.ll
+++ b/test/Transforms/LICM/2008-07-22-LoadGlobalConstant.ll
@@ -6,7 +6,7 @@ define void @test(i32 %count) {
 entry:
         br label %forcond
 
-; CHECK:  %tmp3 = load float** @a
+; CHECK:  %tmp3 = load float*, float** @a
 ; CHECK:  br label %forcond
 
 forcond:
@@ -19,14 +19,14 @@ forcond:
 ; CHECK:  br i1 %cmp, label %forbody, label %afterfor
 
 forbody:
-        %tmp3 = load float** @a
-        %arrayidx = getelementptr float* %tmp3, i32 %i.0
+        %tmp3 = load float*, float** @a
+        %arrayidx = getelementptr float, float* %tmp3, i32 %i.0
         %tmp7 = uitofp i32 %i.0 to float
         store float %tmp7, float* %arrayidx
         %inc = add i32 %i.0, 1
         br label %forcond
 
-; CHECK:  %arrayidx = getelementptr float* %tmp3, i32 %i.0
+; CHECK:  %arrayidx = getelementptr float, float* %tmp3, i32 %i.0
 ; CHECK:  %tmp7 = uitofp i32 %i.0 to float
 ; CHECK:  store float %tmp7, float* %arrayidx
 ; CHECK:  %inc = add i32 %i.0, 1
diff --git a/test/Transforms/LICM/2009-12-10-LICM-Indbr-Crash.ll b/test/Transforms/LICM/2009-12-10-LICM-Indbr-Crash.ll
index e3cdbb3d2a40..1b3ff5bbb318 100644
--- a/test/Transforms/LICM/2009-12-10-LICM-Indbr-Crash.ll
+++ b/test/Transforms/LICM/2009-12-10-LICM-Indbr-Crash.ll
@@ -12,7 +12,7 @@ define void @foo (i8* %v)
     indirectbr i8* undef, [label %preheader, label %stuff]
 
   stuff:
-    %0 = load i8* undef, align 1
+    %0 = load i8, i8* undef, align 1
     br label %loop
 
   return:
diff --git a/test/Transforms/LICM/2011-04-06-HoistMissedASTUpdate.ll b/test/Transforms/LICM/2011-04-06-HoistMissedASTUpdate.ll
index 2bbc6ab0414a..b462885e5fbc 100644
--- a/test/Transforms/LICM/2011-04-06-HoistMissedASTUpdate.ll
+++ b/test/Transforms/LICM/2011-04-06-HoistMissedASTUpdate.ll
@@ -15,11 +15,11 @@ for.body4.lr.ph:
   br label %for.body4
 
 ; CHECK: for.body4:
-; CHECK: load volatile i16* @g_39
+; CHECK: load volatile i16, i16* @g_39
 
 for.body4:
   %l_612.11 = phi i32* [ undef, %for.body4.lr.ph ], [ %call19, %for.body4 ]
-  %tmp7 = load volatile i16* @g_39, align 2
+  %tmp7 = load volatile i16, i16* @g_39, align 2
   %call = call i32** @func_108(i32*** undef)
   %call19 = call i32* @func_84(i32** %call)
   br i1 false, label %for.body4, label %for.cond.loopexit
diff --git a/test/Transforms/LICM/2011-04-06-PromoteResultOfPromotion.ll b/test/Transforms/LICM/2011-04-06-PromoteResultOfPromotion.ll
index 5587142dcf76..370491eab980 100644
--- a/test/Transforms/LICM/2011-04-06-PromoteResultOfPromotion.ll
+++ b/test/Transforms/LICM/2011-04-06-PromoteResultOfPromotion.ll
@@ -8,7 +8,7 @@ define void @f() nounwind {
 
 ; CHECK: entry:
 ; CHECK: alloca [9 x i16]
-; CHECK: load i32* @g_58
+; CHECK: load i32, i32* @g_58
 ; CHECK: br label %for.body
 
 entry:
@@ -18,8 +18,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.inc
   %inc12 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   store i32* @g_58, i32** @g_116, align 8, !tbaa !0
-  %tmp2 = load i32** @g_116, align 8, !tbaa !0
-  %tmp3 = load i32* %tmp2, !tbaa !4
+  %tmp2 = load i32*, i32** @g_116, align 8, !tbaa !0
+  %tmp3 = load i32, i32* %tmp2, !tbaa !4
   %or = or i32 %tmp3, 10
   store i32 %or, i32* %tmp2, !tbaa !4
   %inc = add nsw i32 %inc12, 1
diff --git a/test/Transforms/LICM/2011-04-09-RAUW-AST.ll b/test/Transforms/LICM/2011-04-09-RAUW-AST.ll
index 4285bd19e5f1..bf069c2a9917 100644
--- a/test/Transforms/LICM/2011-04-09-RAUW-AST.ll
+++ b/test/Transforms/LICM/2011-04-09-RAUW-AST.ll
@@ -6,7 +6,7 @@
 
 define i32 @main() nounwind {
 entry:
-  %tmp = load i32* @g_3, align 4
+  %tmp = load i32, i32* @g_3, align 4
   %tobool = icmp eq i32 %tmp, 0
   br i1 %tobool, label %for.cond, label %if.then
 
@@ -40,8 +40,8 @@ for.inc10:                                        ; preds = %for.cond4
   br label %for.cond
 
 for.end13:                                        ; preds = %for.cond
-  %tmp14 = load i32* @g_3, align 4
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32 %tmp14) nounwind
+  %tmp14 = load i32, i32* @g_3, align 4
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %tmp14) nounwind
   ret i32 0
 }
 
diff --git a/test/Transforms/LICM/2011-07-06-Alignment.ll b/test/Transforms/LICM/2011-07-06-Alignment.ll
index 569231489fec..c71dd802ea9b 100644
--- a/test/Transforms/LICM/2011-07-06-Alignment.ll
+++ b/test/Transforms/LICM/2011-07-06-Alignment.ll
@@ -8,7 +8,7 @@ entry:
 
 for.cond:
   %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr [1024 x float]* @A, i64 0, i64 3
+  %arrayidx = getelementptr [1024 x float], [1024 x float]* @A, i64 0, i64 3
   %vecidx = bitcast float* %arrayidx to <4 x float>*
   store <4 x float> zeroinitializer, <4 x float>* %vecidx, align 4
   %indvar.next = add i64 %indvar, 1
diff --git a/test/Transforms/LICM/PR21582.ll b/test/Transforms/LICM/PR21582.ll
index c068c2f8e32b..5664f2e2b6e0 100644
--- a/test/Transforms/LICM/PR21582.ll
+++ b/test/Transforms/LICM/PR21582.ll
@@ -19,8 +19,8 @@ for.body.preheader:                               ; preds = %for.cond
 
 for.body:                                         ; preds = %for.body, %for.body.preheader
   %g.15 = phi i32 [ undef, %for.body ], [ 0, %for.body.preheader ]
-  %arrayidx2 = getelementptr inbounds i32* @fn3.i, i64 0
-  %0 = load i32* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* @fn3.i, i64 0
+  %0 = load i32, i32* %arrayidx2, align 4
   %call = call i32 @g()
   br i1 false, label %for.body, label %for.end.loopexit
 
diff --git a/test/Transforms/LICM/atomics.ll b/test/Transforms/LICM/atomics.ll
index acf605d2dad8..4fe197abf5d3 100644
--- a/test/Transforms/LICM/atomics.ll
+++ b/test/Transforms/LICM/atomics.ll
@@ -7,7 +7,7 @@ entry:
 
 loop:
   %i = phi i32 [ %inc, %loop ], [ 0, %entry ]
-  %val = load atomic i32* %y unordered, align 4
+  %val = load atomic i32, i32* %y unordered, align 4
   %inc = add nsw i32 %i, 1
   %exitcond = icmp eq i32 %inc, %val
   br i1 %exitcond, label %end, label %loop
@@ -27,7 +27,7 @@ entry:
   br label %loop
 
 loop:
-  %val = load atomic i32* %y monotonic, align 4
+  %val = load atomic i32, i32* %y monotonic, align 4
   %exitcond = icmp ne i32 %val, 0
   br i1 %exitcond, label %end, label %loop
 
@@ -47,15 +47,15 @@ entry:
   br label %loop
 
 loop:
-  %vala = load atomic i32* %y monotonic, align 4
-  %valb = load atomic i32* %x unordered, align 4
+  %vala = load atomic i32, i32* %y monotonic, align 4
+  %valb = load atomic i32, i32* %x unordered, align 4
   %exitcond = icmp ne i32 %vala, %valb
   br i1 %exitcond, label %end, label %loop
 
 end:
   ret i32 %vala
 ; CHECK-LABEL: define i32 @test3(
-; CHECK: load atomic i32* %x unordered
+; CHECK: load atomic i32, i32* %x unordered
 ; CHECK-NEXT: br label %loop
 }
 
@@ -66,7 +66,7 @@ entry:
   br label %loop
 
 loop:
-  %vala = load atomic i32* %y monotonic, align 4
+  %vala = load atomic i32, i32* %y monotonic, align 4
   store atomic i32 %vala, i32* %x unordered, align 4
   %exitcond = icmp ne i32 %vala, 0
   br i1 %exitcond, label %end, label %loop
@@ -74,6 +74,6 @@ loop:
 end:
   ret i32 %vala
 ; CHECK-LABEL: define i32 @test4(
-; CHECK: load atomic i32* %y monotonic
+; CHECK: load atomic i32, i32* %y monotonic
 ; CHECK-NEXT: store atomic
 }
diff --git a/test/Transforms/LICM/constexpr.ll b/test/Transforms/LICM/constexpr.ll
new file mode 100644
index 000000000000..506721f25f8f
--- /dev/null
+++ b/test/Transforms/LICM/constexpr.ll
@@ -0,0 +1,46 @@
+; RUN: opt < %s -S -basicaa -licm | FileCheck %s
+; This fixes PR22460
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+@in = internal unnamed_addr global i32* null, align 8
+@out = internal unnamed_addr global i32* null, align 8
+
+; CHECK-LABEL: @bar
+; CHECK: entry:
+; CHECK: load i64, i64* bitcast (i32** @in to i64*)
+; CHECK: do.body:
+; CHECK-NOT: load
+
+define i64 @bar(i32 %N) {
+entry:
+  br label %do.body
+
+do.body:                                          ; preds = %l2, %entry
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %l2 ]
+  %total = phi i64 [ 0, %entry ], [ %next, %l2 ]
+  %c = icmp eq i32 %N, 6
+  br i1 %c, label %l1, label %do.body.l2_crit_edge
+
+do.body.l2_crit_edge:                             ; preds = %do.body
+  %inval.pre = load i32*, i32** @in, align 8
+  br label %l2
+
+l1:                                               ; preds = %do.body
+  %v1 = load i64, i64* bitcast (i32** @in to i64*), align 8
+  store i64 %v1, i64* bitcast (i32** @out to i64*), align 8
+  %0 = inttoptr i64 %v1 to i32*
+  br label %l2
+
+l2:                                               ; preds = %do.body.l2_crit_edge, %l1
+  %inval = phi i32* [ %inval.pre, %do.body.l2_crit_edge ], [ %0, %l1 ]
+  %int = ptrtoint i32* %inval to i64
+  %next = add i64 %total, %int
+  %inc = add nsw i32 %i.0, 1
+  %cmp = icmp slt i32 %inc, %N
+  br i1 %cmp, label %do.body, label %do.end
+
+do.end:                                           ; preds = %l2
+  ret i64 %total
+}
diff --git a/test/Transforms/LICM/crash.ll b/test/Transforms/LICM/crash.ll
index b43477a56df5..7fa41157338d 100644
--- a/test/Transforms/LICM/crash.ll
+++ b/test/Transforms/LICM/crash.ll
@@ -12,7 +12,7 @@ entry:
 
 for.body:                                         ; preds = %for.cond, %bb.nph
   store i8 0, i8* @g_12, align 1
-  %tmp6 = load i8* @g_12, align 1
+  %tmp6 = load i8, i8* @g_12, align 1
   br label %for.cond
 
 for.cond:                                         ; preds = %for.body
@@ -34,7 +34,7 @@ entry:
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
-  %tmp7 = load i32* @g_8, align 4
+  %tmp7 = load i32, i32* @g_8, align 4
   store i32* @g_8, i32** undef, align 16
   store i32 undef, i32* @g_8, align 4
   br label %for.body
@@ -47,10 +47,10 @@ entry:
   br i1 undef, label %for.cond, label %for.end
 
 for.cond:                                         ; preds = %for.cond, %entry
-  %tmp1 = getelementptr { i32*}* %__first, i32 0, i32 0
-  %tmp2 = load i32** %tmp1, align 4
+  %tmp1 = getelementptr { i32*}, { i32*}* %__first, i32 0, i32 0
+  %tmp2 = load i32*, i32** %tmp1, align 4
   %call = tail call i32* @test3helper(i32* %tmp2)
-  %tmp3 = getelementptr { i32*}* %__first, i32 0, i32 0
+  %tmp3 = getelementptr { i32*}, { i32*}* %__first, i32 0, i32 0
   store i32* %call, i32** %tmp3, align 4
   br i1 false, label %for.cond, label %for.end
 
diff --git a/test/Transforms/LICM/debug-value.ll b/test/Transforms/LICM/debug-value.ll
index b49c559672a6..62429fdc3216 100644
--- a/test/Transforms/LICM/debug-value.ll
+++ b/test/Transforms/LICM/debug-value.ll
@@ -15,7 +15,7 @@ if.then:                                          ; preds = %for.body
 
 if.then27:                                        ; preds = %if.then
 ; CHECK: tail call void @llvm.dbg.value
-  tail call void @llvm.dbg.value(metadata double undef, i64 0, metadata !19, metadata !{}), !dbg !21
+  tail call void @llvm.dbg.value(metadata double undef, i64 0, metadata !19, metadata !DIExpression()), !dbg !21
   br label %for.body61.us
 
 if.end.if.end.split_crit_edge.critedge:           ; preds = %if.then
@@ -36,30 +36,30 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.module.flags = !{!26}
 !llvm.dbg.sp = !{!0, !6, !9, !10}
 
-!0 = !{!"0x2e\00idamax\00idamax\00\00112\000\001\000\006\00256\000\000", !25, !1, !3, i32 0, null, null, null, null} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !25} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 2.9 (trunk 127169)\001\00\000\00\000", !25, !8, !8, !8, null, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !25, !1, null, !4, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = !DISubprogram(name: "idamax", line: 112, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !25, scope: !1, type: !3)
+!1 = !DIFile(filename: "/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/Benchmarks/CoyoteBench/lpbench.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 2.9 (trunk 127169)", isOptimized: true, emissionKind: 0, file: !25, enums: !8, retainedTypes: !8, subprograms: !8)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ]
-!6 = !{!"0x2e\00dscal\00dscal\00\00206\000\001\000\006\00256\000\000", !25, !1, !7, i32 0, null, null, null, null} ; [ DW_TAG_subprogram ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", !25, !1, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DISubprogram(name: "dscal", line: 206, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !25, scope: !1, type: !7)
+!7 = !DISubroutineType(types: !8)
 !8 = !{null}
-!9 = !{!"0x2e\00daxpy\00daxpy\00\00230\000\001\000\006\00256\000\000", !25, !1, !7, i32 0, null, null, null, null} ; [ DW_TAG_subprogram ]
-!10 = !{!"0x2e\00dgefa\00dgefa\00\00267\000\001\000\006\00256\000\000", !25, !1, !7, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 267] [def] [scope 0] [dgefa]
-!11 = !MDLocation(line: 281, column: 9, scope: !12)
-!12 = !{!"0xb\00272\005\0032", !25, !13} ; [ DW_TAG_lexical_block ]
-!13 = !{!"0xb\00271\005\0031", !25, !14} ; [ DW_TAG_lexical_block ]
-!14 = !{!"0xb\00267\001\0030", !25, !10} ; [ DW_TAG_lexical_block ]
-!15 = !MDLocation(line: 271, column: 5, scope: !14)
-!16 = !MDLocation(line: 284, column: 10, scope: !17)
-!17 = !{!"0xb\00282\009\0033", !25, !12} ; [ DW_TAG_lexical_block ]
+!9 = !DISubprogram(name: "daxpy", line: 230, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !25, scope: !1, type: !7)
+!10 = !DISubprogram(name: "dgefa", line: 267, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !25, scope: !1, type: !7)
+!11 = !DILocation(line: 281, column: 9, scope: !12)
+!12 = distinct !DILexicalBlock(line: 272, column: 5, file: !25, scope: !13)
+!13 = distinct !DILexicalBlock(line: 271, column: 5, file: !25, scope: !14)
+!14 = distinct !DILexicalBlock(line: 267, column: 1, file: !25, scope: !10)
+!15 = !DILocation(line: 271, column: 5, scope: !14)
+!16 = !DILocation(line: 284, column: 10, scope: !17)
+!17 = distinct !DILexicalBlock(line: 282, column: 9, file: !25, scope: !12)
 !18 = !{double undef}
-!19 = !{!"0x100\00temp\00268\000", !14, !1, !20} ; [ DW_TAG_auto_variable ]
-!20 = !{!"0x24\00double\000\0064\0064\000\000\004", null, !2} ; [ DW_TAG_base_type ]
-!21 = !MDLocation(line: 286, column: 14, scope: !22)
-!22 = !{!"0xb\00285\0013\0034", !25, !17} ; [ DW_TAG_lexical_block ]
-!23 = !MDLocation(line: 296, column: 13, scope: !17)
-!24 = !MDLocation(line: 313, column: 1, scope: !14)
-!25 = !{!"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/Benchmarks/CoyoteBench/lpbench.c", !"/private/tmp"}
-!26 = !{i32 1, !"Debug Info Version", i32 2}
+!19 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "temp", line: 268, scope: !14, file: !1, type: !20)
+!20 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 64, encoding: DW_ATE_float)
+!21 = !DILocation(line: 286, column: 14, scope: !22)
+!22 = distinct !DILexicalBlock(line: 285, column: 13, file: !25, scope: !17)
+!23 = !DILocation(line: 296, column: 13, scope: !17)
+!24 = !DILocation(line: 313, column: 1, scope: !14)
+!25 = !DIFile(filename: "/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/Benchmarks/CoyoteBench/lpbench.c", directory: "/private/tmp")
+!26 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/LICM/hoist-bitcast-load.ll b/test/Transforms/LICM/hoist-bitcast-load.ll
index fa61eaf5b46f..47c474c17dde 100644
--- a/test/Transforms/LICM/hoist-bitcast-load.ll
+++ b/test/Transforms/LICM/hoist-bitcast-load.ll
@@ -4,7 +4,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 ; Make sure the basic alloca pointer hoisting works:
 ; CHECK-LABEL: @test1
-; CHECK: load i32* %c, align 4
+; CHECK: load i32, i32* %c, align 4
 ; CHECK: for.body:
 
 ; Function Attrs: nounwind uwtable
@@ -16,15 +16,15 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.inc
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %0, 0
   br i1 %cmp1, label %if.then, label %for.inc
 
 if.then:                                          ; preds = %for.body
-  %1 = load i32* %c, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %2 = load i32* %arrayidx3, align 4
+  %1 = load i32, i32* %c, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
   %mul = mul nsw i32 %2, %1
   store i32 %mul, i32* %arrayidx, align 4
   br label %for.inc
@@ -42,7 +42,7 @@ for.end:                                          ; preds = %for.inc, %entry
 ; Make sure the basic alloca pointer hoisting works through a bitcast to a
 ; pointer to a smaller type:
 ; CHECK-LABEL: @test2
-; CHECK: load i32* %c, align 4
+; CHECK: load i32, i32* %c, align 4
 ; CHECK: for.body:
 
 ; Function Attrs: nounwind uwtable
@@ -55,15 +55,15 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.inc
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %0, 0
   br i1 %cmp1, label %if.then, label %for.inc
 
 if.then:                                          ; preds = %for.body
-  %1 = load i32* %c, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %2 = load i32* %arrayidx3, align 4
+  %1 = load i32, i32* %c, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
   %mul = mul nsw i32 %2, %1
   store i32 %mul, i32* %arrayidx, align 4
   br label %for.inc
@@ -80,7 +80,7 @@ for.end:                                          ; preds = %for.inc, %entry
 
 ; Make sure the basic alloca pointer hoisting works through an addrspacecast
 ; CHECK-LABEL: @test2_addrspacecast
-; CHECK: load i32 addrspace(1)* %c, align 4
+; CHECK: load i32, i32 addrspace(1)* %c, align 4
 ; CHECK: for.body:
 
 ; Function Attrs: nounwind uwtable
@@ -93,15 +93,15 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.inc
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32 addrspace(1)* %a, i64 %indvars.iv
-  %0 = load i32 addrspace(1)* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %indvars.iv
+  %0 = load i32, i32 addrspace(1)* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %0, 0
   br i1 %cmp1, label %if.then, label %for.inc
 
 if.then:                                          ; preds = %for.body
-  %1 = load i32 addrspace(1)* %c, align 4
-  %arrayidx3 = getelementptr inbounds i32 addrspace(1)* %b, i64 %indvars.iv
-  %2 = load i32 addrspace(1)* %arrayidx3, align 4
+  %1 = load i32, i32 addrspace(1)* %c, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32 addrspace(1)* %b, i64 %indvars.iv
+  %2 = load i32, i32 addrspace(1)* %arrayidx3, align 4
   %mul = mul nsw i32 %2, %1
   store i32 %mul, i32 addrspace(1)* %arrayidx, align 4
   br label %for.inc
@@ -119,7 +119,7 @@ for.end:                                          ; preds = %for.inc, %entry
 ; Make sure the basic alloca pointer hoisting works through a bitcast to a
 ; pointer to a smaller type (where the bitcast also needs to be hoisted):
 ; CHECK-LABEL: @test3
-; CHECK: load i32* %c, align 4
+; CHECK: load i32, i32* %c, align 4
 ; CHECK: for.body:
 
 ; Function Attrs: nounwind uwtable
@@ -131,16 +131,16 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.inc
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %0, 0
   br i1 %cmp1, label %if.then, label %for.inc
 
 if.then:                                          ; preds = %for.body
   %c = bitcast i64* %ca to i32*
-  %1 = load i32* %c, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %2 = load i32* %arrayidx3, align 4
+  %1 = load i32, i32* %c, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
   %mul = mul nsw i32 %2, %1
   store i32 %mul, i32* %arrayidx, align 4
   br label %for.inc
@@ -159,7 +159,7 @@ for.end:                                          ; preds = %for.inc, %entry
 ; to a pointer to a larger type:
 ; CHECK-LABEL: @test4
 ; CHECK: for.body:
-; CHECK: load i32* %c, align 4
+; CHECK: load i32, i32* %c, align 4
 
 ; Function Attrs: nounwind uwtable
 define void @test4(i32* nocapture %a, i32* nocapture readonly %b, i32 %n) #0 {
@@ -171,15 +171,15 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.inc
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %0, 0
   br i1 %cmp1, label %if.then, label %for.inc
 
 if.then:                                          ; preds = %for.body
-  %1 = load i32* %c, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %2 = load i32* %arrayidx3, align 4
+  %1 = load i32, i32* %c, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
   %mul = mul nsw i32 %2, %1
   store i32 %mul, i32* %arrayidx, align 4
   br label %for.inc
@@ -197,7 +197,7 @@ for.end:                                          ; preds = %for.inc, %entry
 ; Don't crash on bitcasts to unsized types.
 ; CHECK-LABEL: @test5
 ; CHECK: for.body:
-; CHECK: load i32* %c, align 4
+; CHECK: load i32, i32* %c, align 4
 
 %atype = type opaque
 
@@ -212,15 +212,15 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.inc
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %0, 0
   br i1 %cmp1, label %if.then, label %for.inc
 
 if.then:                                          ; preds = %for.body
-  %1 = load i32* %c, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %2 = load i32* %arrayidx3, align 4
+  %1 = load i32, i32* %c, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
   %mul = mul nsw i32 %2, %1
   store i32 %mul, i32* %arrayidx, align 4
   br label %for.inc
diff --git a/test/Transforms/LICM/hoist-deref-load.ll b/test/Transforms/LICM/hoist-deref-load.ll
index c230d1dcd43b..c384a858d1e6 100644
--- a/test/Transforms/LICM/hoist-deref-load.ll
+++ b/test/Transforms/LICM/hoist-deref-load.ll
@@ -12,7 +12,7 @@ target triple = "x86_64-unknown-linux-gnu"
 ; because the dereferenceable attribute is on %c.
 
 ; CHECK-LABEL: @test1
-; CHECK: load i32* %c, align 4
+; CHECK: load i32, i32* %c, align 4
 ; CHECK: for.body:
 
 define void @test1(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32* nocapture readonly nonnull dereferenceable(4) %c, i32 %n) #0 {
@@ -22,15 +22,15 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.inc
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %0, 0
   br i1 %cmp1, label %if.then, label %for.inc
 
 if.then:                                          ; preds = %for.body
-  %1 = load i32* %c, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %2 = load i32* %arrayidx3, align 4
+  %1 = load i32, i32* %c, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
   %mul = mul nsw i32 %2, %1
   store i32 %mul, i32* %arrayidx, align 4
   br label %for.inc
@@ -50,7 +50,7 @@ for.end:                                          ; preds = %for.inc, %entry
 
 ; CHECK-LABEL: @test2
 ; CHECK: if.then:
-; CHECK: load i32* %c, align 4
+; CHECK: load i32, i32* %c, align 4
 
 define void @test2(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32* nocapture readonly nonnull %c, i32 %n) #0 {
 entry:
@@ -59,15 +59,15 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.inc
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %0, 0
   br i1 %cmp1, label %if.then, label %for.inc
 
 if.then:                                          ; preds = %for.body
-  %1 = load i32* %c, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %2 = load i32* %arrayidx3, align 4
+  %1 = load i32, i32* %c, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
   %mul = mul nsw i32 %2, %1
   store i32 %mul, i32* %arrayidx, align 4
   br label %for.inc
@@ -92,7 +92,7 @@ for.end:                                          ; preds = %for.inc, %entry
 ; because the dereferenceable attribute is on %c.
 
 ; CHECK-LABEL: @test3
-; CHECK: load i32* %c2, align 4
+; CHECK: load i32, i32* %c2, align 4
 ; CHECK: for.body:
 
 define void @test3(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32* nocapture readonly dereferenceable(12) %c, i32 %n) #0 {
@@ -102,16 +102,16 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.inc
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %0, 0
   br i1 %cmp1, label %if.then, label %for.inc
 
 if.then:                                          ; preds = %for.body
-  %c2 = getelementptr inbounds i32* %c, i64 2
-  %1 = load i32* %c2, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %2 = load i32* %arrayidx3, align 4
+  %c2 = getelementptr inbounds i32, i32* %c, i64 2
+  %1 = load i32, i32* %c2, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
   %mul = mul nsw i32 %2, %1
   store i32 %mul, i32* %arrayidx, align 4
   br label %for.inc
@@ -131,7 +131,7 @@ for.end:                                          ; preds = %for.inc, %entry
 
 ; CHECK-LABEL: @test4
 ; CHECK: if.then:
-; CHECK: load i32* %c2, align 4
+; CHECK: load i32, i32* %c2, align 4
 
 define void @test4(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32* nocapture readonly dereferenceable(11) %c, i32 %n) #0 {
 entry:
@@ -140,16 +140,16 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.inc
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %0, 0
   br i1 %cmp1, label %if.then, label %for.inc
 
 if.then:                                          ; preds = %for.body
-  %c2 = getelementptr inbounds i32* %c, i64 2
-  %1 = load i32* %c2, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %2 = load i32* %arrayidx3, align 4
+  %c2 = getelementptr inbounds i32, i32* %c, i64 2
+  %1 = load i32, i32* %c2, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
   %mul = mul nsw i32 %2, %1
   store i32 %mul, i32* %arrayidx, align 4
   br label %for.inc
@@ -164,5 +164,229 @@ for.end:                                          ; preds = %for.inc, %entry
   ret void
 }
 
-attributes #0 = { nounwind uwtable }
+; This test represents the following function:
+; void test1(int * __restrict__ a, int *b, int &c, int n) {
+;   if (c != null)
+;     for (int i = 0; i < n; ++i)
+;       if (a[i] > 0)
+;         a[i] = c*b[i];
+; }
+; and we want to hoist the load of %c out of the loop. This can be done only
+; because the dereferenceable_or_null attribute is on %c and there is a null
+; check on %c.
+
+; CHECK-LABEL: @test5
+; CHECK: load i32, i32* %c, align 4
+; CHECK: for.body:
+
+define void @test5(i32* noalias %a, i32* %b, i32* dereferenceable_or_null(4) %c, i32 %n) #0 {
+entry:
+  %not_null = icmp ne i32* %c, null
+  br i1 %not_null, label %not.null, label %for.end
+
+not.null:
+  %cmp11 = icmp sgt i32 %n, 0
+  br i1 %cmp11, label %for.body, label %for.end
+
+for.body:                                         ; preds = %not.null, %for.inc
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %not.null ]
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %cmp1 = icmp sgt i32 %0, 0
+  br i1 %cmp1, label %if.then, label %for.inc
+
+if.then:                                          ; preds = %for.body
+  %1 = load i32, i32* %c, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
+  %mul = mul nsw i32 %2, %1
+  store i32 %mul, i32* %arrayidx, align 4
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body, %if.then
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.inc, %entry, %not.null
+  ret void
+}
+
+; This is the same as @test5, but without the null check on %c.
+; Without this check, we should not hoist the load of %c.
+
+; This test case has an icmp on c but the use of this comparison is
+; not a branch. 
+
+; CHECK-LABEL: @test6
+; CHECK: if.then:
+; CHECK: load i32, i32* %c, align 4
+
+define i1 @test6(i32* noalias %a, i32* %b, i32* dereferenceable_or_null(4) %c, i32 %n) #0 {
+entry:
+  %not_null = icmp ne i32* %c, null
+  %cmp11 = icmp sgt i32 %n, 0
+  br i1 %cmp11, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.inc
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %cmp1 = icmp sgt i32 %0, 0
+  br i1 %cmp1, label %if.then, label %for.inc
+
+if.then:                                          ; preds = %for.body
+  %1 = load i32, i32* %c, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
+  %mul = mul nsw i32 %2, %1
+  store i32 %mul, i32* %arrayidx, align 4
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body, %if.then
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.inc, %entry
+  ret i1 %not_null
+}
+
+; This test represents the following function:
+; void test1(int * __restrict__ a, int *b, int **cptr, int n) {
+;   c = *cptr;
+;   for (int i = 0; i < n; ++i)
+;     if (a[i] > 0)
+;       a[i] = (*c)*b[i];
+; }
+; and we want to hoist the load of %c out of the loop. This can be done only
+; because the dereferenceable meatdata on the c = *cptr load.
+
+; CHECK-LABEL: @test7
+; CHECK: load i32, i32* %c, align 4
+; CHECK: for.body:
+
+define void @test7(i32* noalias %a, i32* %b, i32** %cptr, i32 %n) #0 {
+entry:
+  %c = load i32*, i32** %cptr, !dereferenceable !0
+  %cmp11 = icmp sgt i32 %n, 0
+  br i1 %cmp11, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.inc
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %cmp1 = icmp sgt i32 %0, 0
+  br i1 %cmp1, label %if.then, label %for.inc
 
+if.then:                                          ; preds = %for.body
+  %1 = load i32, i32* %c, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
+  %mul = mul nsw i32 %2, %1
+  store i32 %mul, i32* %arrayidx, align 4
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body, %if.then
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.inc, %entry
+  ret void
+}
+
+; This test represents the following function:
+; void test1(int * __restrict__ a, int *b, int **cptr, int n) {
+;   c = *cptr;
+;   if (c != null)
+;     for (int i = 0; i < n; ++i)
+;       if (a[i] > 0)
+;         a[i] = (*c)*b[i];
+; }
+; and we want to hoist the load of %c out of the loop. This can be done only
+; because the dereferenceable_or_null meatdata on the c = *cptr load and there 
+; is a null check on %c.
+
+; CHECK-LABEL: @test8
+; CHECK: load i32, i32* %c, align 4
+; CHECK: for.body:
+
+define void @test8(i32* noalias %a, i32* %b, i32** %cptr, i32 %n) #0 {
+entry:
+  %c = load i32*, i32** %cptr, !dereferenceable_or_null !0
+  %not_null = icmp ne i32* %c, null
+  br i1 %not_null, label %not.null, label %for.end
+
+not.null:
+  %cmp11 = icmp sgt i32 %n, 0
+  br i1 %cmp11, label %for.body, label %for.end
+
+for.body:                                         ; preds = %not.null, %for.inc
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %not.null ]
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %cmp1 = icmp sgt i32 %0, 0
+  br i1 %cmp1, label %if.then, label %for.inc
+
+if.then:                                          ; preds = %for.body
+  %1 = load i32, i32* %c, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
+  %mul = mul nsw i32 %2, %1
+  store i32 %mul, i32* %arrayidx, align 4
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body, %if.then
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.inc, %entry, %not.null
+  ret void
+}
+
+; This is the same as @test8, but without the null check on %c.
+; Without this check, we should not hoist the load of %c.
+
+; CHECK-LABEL: @test9
+; CHECK: if.then:
+; CHECK: load i32, i32* %c, align 4
+
+define void @test9(i32* noalias %a, i32* %b, i32** %cptr, i32 %n) #0 {
+entry:
+  %c = load i32*, i32** %cptr, !dereferenceable_or_null !0
+  %cmp11 = icmp sgt i32 %n, 0
+  br i1 %cmp11, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.inc
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %cmp1 = icmp sgt i32 %0, 0
+  br i1 %cmp1, label %if.then, label %for.inc
+
+if.then:                                          ; preds = %for.body
+  %1 = load i32, i32* %c, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx3, align 4
+  %mul = mul nsw i32 %2, %1
+  store i32 %mul, i32* %arrayidx, align 4
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body, %if.then
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.inc, %entry
+  ret void
+}
+
+attributes #0 = { nounwind uwtable }
+!0 = !{i64 4}
diff --git a/test/Transforms/LICM/hoist-invariant-load.ll b/test/Transforms/LICM/hoist-invariant-load.ll
index 59904bad4ae6..aec155b5580a 100644
--- a/test/Transforms/LICM/hoist-invariant-load.ll
+++ b/test/Transforms/LICM/hoist-invariant-load.ll
@@ -2,9 +2,9 @@
 ; RUN: opt < %s -licm -stats -S 2>&1 | grep "1 licm"
 
 @"\01L_OBJC_METH_VAR_NAME_" = internal global [4 x i8] c"foo\00", section "__TEXT,__objc_methname,cstring_literals", align 1
-@"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
+@"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
 @"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] [i32 0, i32 16], section "__DATA, __objc_imageinfo, regular, no_dead_strip"
-@llvm.used = appending global [3 x i8*] [i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*)], section "llvm.metadata"
+@llvm.used = appending global [3 x i8*] [i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*)], section "llvm.metadata"
 
 define void @test(i8* %x) uwtable ssp {
 entry:
@@ -15,18 +15,18 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp ult i32 %0, 10000
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i8** %x.addr, align 8
-  %2 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", !invariant.load !0
+  %1 = load i8*, i8** %x.addr, align 8
+  %2 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", !invariant.load !0
   %call = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %1, i8* %2)
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %3 = load i32* %i, align 4
+  %3 = load i32, i32* %i, align 4
   %inc = add i32 %3, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
diff --git a/test/Transforms/LICM/hoisting.ll b/test/Transforms/LICM/hoisting.ll
index b4d297ac27bf..8609407cc599 100644
--- a/test/Transforms/LICM/hoisting.ll
+++ b/test/Transforms/LICM/hoisting.ll
@@ -8,7 +8,7 @@ declare void @foo()
 ; potentially trapping instructions when they are not guaranteed to execute.
 define i32 @test1(i1 %c) {
 ; CHECK-LABEL: @test1(
-	%A = load i32* @X		; <i32> [#uses=2]
+	%A = load i32, i32* @X		; <i32> [#uses=2]
 	br label %Loop
 Loop:		; preds = %LoopTail, %0
 	call void @foo( )
@@ -35,9 +35,9 @@ declare void @foo2(i32) nounwind
 ;; It is ok and desirable to hoist this potentially trapping instruction.
 define i32 @test2(i1 %c) {
 ; CHECK-LABEL: @test2(
-; CHECK-NEXT: load i32* @X
+; CHECK-NEXT: load i32, i32* @X
 ; CHECK-NEXT: %B = sdiv i32 4, %A
-	%A = load i32* @X		; <i32> [#uses=2]
+	%A = load i32, i32* @X		; <i32> [#uses=2]
 	br label %Loop
 Loop:
         ;; Should have hoisted this div!
@@ -54,7 +54,7 @@ Out:		; preds = %Loop
 define i32 @test3(i1 %c) {
 ; CHECK-LABEL: define i32 @test3(
 ; CHECK: call void @foo2(i32 6)
-	%A = load i32* @X		; <i32> [#uses=2]
+	%A = load i32, i32* @X		; <i32> [#uses=2]
 	br label %Loop
 Loop:
 	%B = add i32 4, 2		; <i32> [#uses=2]
diff --git a/test/Transforms/LICM/lcssa-ssa-promoter.ll b/test/Transforms/LICM/lcssa-ssa-promoter.ll
index 5df3ef12181b..b0cae8772f3e 100644
--- a/test/Transforms/LICM/lcssa-ssa-promoter.ll
+++ b/test/Transforms/LICM/lcssa-ssa-promoter.ll
@@ -44,7 +44,7 @@ inner.body.rhs:
 ; CHECK-NEXT: br label %inner.latch
 
 inner.latch:
-  %y_val = load i32* @y, align 4
+  %y_val = load i32, i32* @y, align 4
   %icmp = icmp eq i32 %y_val, 0
   br i1 %icmp, label %inner.exit, label %inner.header
 ; CHECK: inner.latch:
diff --git a/test/Transforms/LICM/pr23608.ll b/test/Transforms/LICM/pr23608.ll
new file mode 100644
index 000000000000..249bc6bf5f63
--- /dev/null
+++ b/test/Transforms/LICM/pr23608.ll
@@ -0,0 +1,50 @@
+; RUN: opt -S -licm %s | FileCheck %s
+; ModuleID = '../pr23608.ll'
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.PyFrameObject = type { i32 }
+
+@a = common global %struct.PyFrameObject* null, align 8
+@__msan_origin_tls = external thread_local(initialexec) global i32
+
+define void @fn1() {
+entry:
+  br label %indirectgoto
+
+while.cond:                                       ; preds = %indirectgoto, %bb15
+  %tmp = load %struct.PyFrameObject*, %struct.PyFrameObject** @a, align 8
+  %_msld = load i64, i64* inttoptr (i64 and (i64 ptrtoint (%struct.PyFrameObject** @a to i64), i64 -70368744177665) to i64*), align 8
+  %tmp1 = load i32, i32* inttoptr (i64 add (i64 and (i64 ptrtoint (%struct.PyFrameObject** @a to i64), i64 -70368744177665), i64 35184372088832) to i32*), align 8
+  %f_iblock = getelementptr inbounds %struct.PyFrameObject, %struct.PyFrameObject* %tmp, i64 0, i32 0
+  br label %bb2
+
+bb:                                               ; preds = %while.cond
+  call void @__msan_warning_noreturn()
+  unreachable
+
+bb2:                                              ; preds = %while.cond
+  %tmp3 = load i32, i32* %f_iblock, align 4
+  %tmp4 = ptrtoint i32* %f_iblock to i64
+  %tmp8 = inttoptr i64 %tmp4 to i32*
+  %tobool = icmp eq i64 %tmp4, 0
+  br i1 %tobool, label %bb13, label %bb15
+
+bb13:                                             ; preds = %bb2
+; CHECK-LABEL bb13:
+; CHECK: %tmp8.le = inttoptr
+  %.lcssa7 = phi i32* [ %tmp8, %bb2 ]
+  call void @__msan_warning_noreturn()
+  unreachable
+
+bb15:                                             ; preds = %bb2
+  br i1 %tobool, label %while.end, label %while.cond
+
+while.end:                                        ; preds = %bb15
+  ret void
+
+indirectgoto:                                     ; preds = %indirectgoto, %entry
+  indirectbr i8* null, [label %indirectgoto, label %while.cond]
+}
+
+declare void @__msan_warning_noreturn()
diff --git a/test/Transforms/LICM/scalar-promote-memmodel.ll b/test/Transforms/LICM/scalar-promote-memmodel.ll
index 23d70f51351a..3603c25ba23c 100644
--- a/test/Transforms/LICM/scalar-promote-memmodel.ll
+++ b/test/Transforms/LICM/scalar-promote-memmodel.ll
@@ -19,12 +19,12 @@ for.body:                                         ; preds = %for.cond
   br i1 %tobool, label %for.inc, label %if.then
 
 if.then:                                          ; preds = %for.body
-  %tmp3 = load i32* @g, align 4
+  %tmp3 = load i32, i32* @g, align 4
   %inc = add nsw i32 %tmp3, 1
   store i32 %inc, i32* @g, align 4
   br label %for.inc
 
-; CHECK: load i32*
+; CHECK: load i32, i32*
 ; CHECK-NEXT: add
 ; CHECK-NEXT: store i32
 
diff --git a/test/Transforms/LICM/scalar_promote.ll b/test/Transforms/LICM/scalar_promote.ll
index 80afb3c01e9a..6ef4bac39bbc 100644
--- a/test/Transforms/LICM/scalar_promote.ll
+++ b/test/Transforms/LICM/scalar_promote.ll
@@ -8,13 +8,13 @@ Entry:
   br label %Loop
 ; CHECK-LABEL: @test1(
 ; CHECK: Entry:
-; CHECK-NEXT:   load i32* @X
+; CHECK-NEXT:   load i32, i32* @X
 ; CHECK-NEXT:   br label %Loop
 
 
 Loop:   ; preds = %Loop, %0
   %j = phi i32 [ 0, %Entry ], [ %Next, %Loop ]    ; <i32> [#uses=1]
-  %x = load i32* @X   ; <i32> [#uses=1]
+  %x = load i32, i32* @X   ; <i32> [#uses=1]
   %x2 = add i32 %x, 1   ; <i32> [#uses=1]
   store i32 %x2, i32* @X
   %Next = add i32 %j, 1   ; <i32> [#uses=2]
@@ -35,14 +35,14 @@ Entry:
   br label %Loop
 ; CHECK-LABEL: @test2(
 ; CHECK: Entry:
-; CHECK-NEXT:    %.promoted = load i32* getelementptr inbounds (i32* @X, i64 1)
+; CHECK-NEXT:    %.promoted = load i32, i32* getelementptr inbounds (i32, i32* @X, i64 1)
 ; CHECK-NEXT:    br label %Loop
 
 Loop:   ; preds = %Loop, %0
-  %X1 = getelementptr i32* @X, i64 1    ; <i32*> [#uses=1]
-  %A = load i32* %X1    ; <i32> [#uses=1]
+  %X1 = getelementptr i32, i32* @X, i64 1    ; <i32*> [#uses=1]
+  %A = load i32, i32* %X1    ; <i32> [#uses=1]
   %V = add i32 %A, 1    ; <i32> [#uses=1]
-  %X2 = getelementptr i32* @X, i64 1    ; <i32*> [#uses=1]
+  %X2 = getelementptr i32, i32* @X, i64 1    ; <i32*> [#uses=1]
   store i32 %V, i32* %X2
   br i1 false, label %Loop, label %Exit
 
@@ -50,7 +50,7 @@ Exit:   ; preds = %Loop
   ret void
 ; CHECK: Exit:
 ; CHECK-NEXT:   %[[LCSSAPHI:.*]] = phi i32 [ %V
-; CHECK-NEXT:   store i32 %[[LCSSAPHI]], i32* getelementptr inbounds (i32* @X, i64 1)
+; CHECK-NEXT:   store i32 %[[LCSSAPHI]], i32* getelementptr inbounds (i32, i32* @X, i64 1)
 ; CHECK-NEXT:   ret void
 }
 
@@ -61,7 +61,7 @@ define void @test3(i32 %i) {
   br label %Loop
 Loop:
         ; Should not promote this to a register
-  %x = load volatile i32* @X
+  %x = load volatile i32, i32* @X
   %x2 = add i32 %x, 1
   store i32 %x2, i32* @X
   br i1 true, label %Out, label %Loop
@@ -82,15 +82,15 @@ define void @test4(i8* %x, i8 %n) {
   br label %loop
 
 loop:
-  %tmp = getelementptr i8* %x, i64 8
+  %tmp = getelementptr i8, i8* %x, i64 8
   store i8* %tmp, i8** %handle2
   br label %subloop
 
 subloop:
   %count = phi i8 [ 0, %loop ], [ %nextcount, %subloop ]
-  %offsetx2 = load i8** %handle2
+  %offsetx2 = load i8*, i8** %handle2
   store i8 %n, i8* %offsetx2
-  %newoffsetx2 = getelementptr i8* %offsetx2, i64 -1
+  %newoffsetx2 = getelementptr i8, i8* %offsetx2, i64 -1
   store i8* %newoffsetx2, i8** %handle2
   %nextcount = add i8 %count, 1
   %innerexitcond = icmp sge i8 %nextcount, 8
@@ -105,14 +105,14 @@ subloop:
 ; CHECK: br i1
 
 innerexit:
-  %offsetx1 = load i8** %handle1
-  %val = load i8* %offsetx1
+  %offsetx1 = load i8*, i8** %handle1
+  %val = load i8, i8* %offsetx1
   %cond = icmp eq i8 %val, %n
   br i1 %cond, label %exit, label %loop
 
 ; Should not have promoted offsetx1 loads.
 ; CHECK: innerexit:
-; CHECK: %val = load i8* %offsetx1
+; CHECK: %val = load i8, i8* %offsetx1
 ; CHECK: %cond = icmp eq i8 %val, %n
 ; CHECK: br i1 %cond, label %exit, label %loop
 
@@ -125,13 +125,13 @@ Entry:
   br label %Loop
 ; CHECK-LABEL: @test5(
 ; CHECK: Entry:
-; CHECK-NEXT:   load i32* @X
+; CHECK-NEXT:   load i32, i32* @X
 ; CHECK-NEXT:   br label %Loop
 
 
 Loop:   ; preds = %Loop, %0
   %j = phi i32 [ 0, %Entry ], [ %Next, %Loop ]    ; <i32> [#uses=1]
-  %x = load i32* @X   ; <i32> [#uses=1]
+  %x = load i32, i32* @X   ; <i32> [#uses=1]
   %x2 = add i32 %x, 1   ; <i32> [#uses=1]
   store i32 %x2, i32* @X
 
@@ -164,9 +164,9 @@ for.body.lr.ph:                                   ; preds = %entry
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %storemerge2 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %idxprom = sext i32 %storemerge2 to i64
-  %arrayidx = getelementptr inbounds float* %a, i64 %idxprom
+  %arrayidx = getelementptr inbounds float, float* %a, i64 %idxprom
   store float 0.000000e+00, float* %arrayidx, align 4, !tbaa !3
-  %0 = load i32* %gi, align 4, !tbaa !0
+  %0 = load i32, i32* %gi, align 4, !tbaa !0
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %gi, align 4, !tbaa !0
   %cmp = icmp slt i32 %inc, %n
@@ -179,7 +179,7 @@ for.end:                                          ; preds = %for.cond.for.end_cr
   ret void
 
 ; CHECK: for.body.lr.ph:
-; CHECK-NEXT:  %gi.promoted = load i32* %gi, align 4, !tbaa !0
+; CHECK-NEXT:  %gi.promoted = load i32, i32* %gi, align 4, !tbaa !0
 ; CHECK: for.cond.for.end_crit_edge:
 ; CHECK-NEXT:  %[[LCSSAPHI:.*]] = phi i32 [ %inc
 ; CHECK-NEXT:  store i32 %[[LCSSAPHI]], i32* %gi, align 4, !tbaa !0
diff --git a/test/Transforms/LICM/sinking.ll b/test/Transforms/LICM/sinking.ll
index d7a8fcdafcad..02bf5846a64c 100644
--- a/test/Transforms/LICM/sinking.ll
+++ b/test/Transforms/LICM/sinking.ll
@@ -93,7 +93,7 @@ Entry:
 	br label %Loop
 Loop:		; preds = %Loop, %Entry
 	%N_addr.0.pn = phi i32 [ %dec, %Loop ], [ %N, %Entry ]	
-	%tmp.6 = load i32* @X		; <i32> [#uses=1]
+	%tmp.6 = load i32, i32* @X		; <i32> [#uses=1]
 	%dec = add i32 %N_addr.0.pn, -1		; <i32> [#uses=1]
 	%tmp.1 = icmp ne i32 %N_addr.0.pn, 1		; <i1> [#uses=1]
 	br i1 %tmp.1, label %Loop, label %Out
@@ -101,7 +101,7 @@ Out:		; preds = %Loop
 	ret i32 %tmp.6
 ; CHECK-LABEL: @test5(
 ; CHECK:     Out:
-; CHECK-NEXT:  %tmp.6.le = load i32* @X
+; CHECK-NEXT:  %tmp.6.le = load i32, i32* @X
 ; CHECK-NEXT:  ret i32 %tmp.6.le
 }
 
@@ -118,15 +118,15 @@ Out:		; preds = %Loop
 define i32 @test6() {
 	br label %Loop
 Loop:
-	%dead = getelementptr %Ty* @X2, i64 0, i32 0
-	%sunk2 = load i32* %dead
+	%dead = getelementptr %Ty, %Ty* @X2, i64 0, i32 0
+	%sunk2 = load i32, i32* %dead
 	br i1 false, label %Loop, label %Out
 Out:		; preds = %Loop
 	ret i32 %sunk2
 ; CHECK-LABEL: @test6(
 ; CHECK:     Out:
-; CHECK-NEXT:  %dead.le = getelementptr %Ty* @X2, i64 0, i32 0
-; CHECK-NEXT:  %sunk2.le = load i32* %dead.le
+; CHECK-NEXT:  %dead.le = getelementptr %Ty, %Ty* @X2, i64 0, i32 0
+; CHECK-NEXT:  %sunk2.le = load i32, i32* %dead.le
 ; CHECK-NEXT:  ret i32 %sunk2.le
 }
 
@@ -174,7 +174,7 @@ Entry:
 Loop:		; preds = %Cont, %Entry
 	br i1 %C1, label %Cont, label %exit1
 Cont:		; preds = %Loop
-	%X = load i32* %P		; <i32> [#uses=2]
+	%X = load i32, i32* %P		; <i32> [#uses=2]
 	store i32 %X, i32* %Q
 	%V = add i32 %X, 1		; <i32> [#uses=1]
 	br i1 %C2, label %Loop, label %exit2
@@ -242,7 +242,7 @@ Out:		; preds = %Loop
 define void @test11() {
 	br label %Loop
 Loop:
-	%dead = getelementptr %Ty* @X2, i64 0, i32 0
+	%dead = getelementptr %Ty, %Ty* @X2, i64 0, i32 0
 	br i1 false, label %Loop, label %Out
 Out:
 	ret void
@@ -261,36 +261,36 @@ entry:
 
 l1.header:
   %iv = phi i64 [ %iv.next, %l1.latch ], [ 0, %entry ]
-  %arrayidx.i = getelementptr inbounds [1 x i32]* @c, i64 0, i64 %iv
+  %arrayidx.i = getelementptr inbounds [1 x i32], [1 x i32]* @c, i64 0, i64 %iv
   br label %l2.header
 
 l2.header:
-  %x0 = load i1* %c, align 4
+  %x0 = load i1, i1* %c, align 4
   br i1 %x0, label %l1.latch, label %l3.preheader
 
 l3.preheader:
   br label %l3.header
 
 l3.header:
-  %x1 = load i1* %d, align 4
+  %x1 = load i1, i1* %d, align 4
   br i1 %x1, label %l2.latch, label %l4.preheader
 
 l4.preheader:
   br label %l4.header
 
 l4.header:
-  %x2 = load i1* %a
+  %x2 = load i1, i1* %a
   br i1 %x2, label %l3.latch, label %l4.body
 
 l4.body:
   call void @f(i32* %arrayidx.i)
-  %x3 = load i1* %b
+  %x3 = load i1, i1* %b
   %l = trunc i64 %iv to i32
   br i1 %x3, label %l4.latch, label %exit
 
 l4.latch:
   call void @g()
-  %x4 = load i1* %b, align 4
+  %x4 = load i1, i1* %b, align 4
   br i1 %x4, label %l4.header, label %exit
 
 l3.latch:
diff --git a/test/Transforms/LICM/speculate.ll b/test/Transforms/LICM/speculate.ll
index 69266693c479..91b5a25ac0f5 100644
--- a/test/Transforms/LICM/speculate.ll
+++ b/test/Transforms/LICM/speculate.ll
@@ -12,14 +12,14 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.inc
   %i.02 = phi i64 [ %inc, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %p, i64 %i.02
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %p, i64 %i.02
+  %0 = load i32, i32* %arrayidx, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %for.inc, label %if.then
 
 if.then:                                          ; preds = %for.body
   %div = udiv i64 %x, 2
-  %arrayidx1 = getelementptr inbounds i64* %q, i64 %i.02
+  %arrayidx1 = getelementptr inbounds i64, i64* %q, i64 %i.02
   store i64 %div, i64* %arrayidx1, align 8
   br label %for.inc
 
@@ -44,14 +44,14 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.inc
   %i.02 = phi i64 [ %inc, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %p, i64 %i.02
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %p, i64 %i.02
+  %0 = load i32, i32* %arrayidx, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %for.inc, label %if.then
 
 if.then:                                          ; preds = %for.body
   %div = udiv i64 %x, %m
-  %arrayidx1 = getelementptr inbounds i64* %q, i64 %i.02
+  %arrayidx1 = getelementptr inbounds i64, i64* %q, i64 %i.02
   store i64 %div, i64* %arrayidx1, align 8
   br label %for.inc
 
@@ -78,14 +78,14 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.inc
   %i.02 = phi i64 [ %inc, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %p, i64 %i.02
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %p, i64 %i.02
+  %0 = load i32, i32* %arrayidx, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %for.inc, label %if.then
 
 if.then:                                          ; preds = %for.body
   %div = sdiv i64 %x, 2
-  %arrayidx1 = getelementptr inbounds i64* %q, i64 %i.02
+  %arrayidx1 = getelementptr inbounds i64, i64* %q, i64 %i.02
   store i64 %div, i64* %arrayidx1, align 8
   br label %for.inc
 
@@ -111,14 +111,14 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.inc
   %i.02 = phi i64 [ %inc, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %p, i64 %i.02
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %p, i64 %i.02
+  %0 = load i32, i32* %arrayidx, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %for.inc, label %if.then
 
 if.then:                                          ; preds = %for.body
   %div = sdiv i64 %x, %or
-  %arrayidx1 = getelementptr inbounds i64* %q, i64 %i.02
+  %arrayidx1 = getelementptr inbounds i64, i64* %q, i64 %i.02
   store i64 %div, i64* %arrayidx1, align 8
   br label %for.inc
 
@@ -144,14 +144,14 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.inc
   %i.02 = phi i64 [ %inc, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %p, i64 %i.02
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %p, i64 %i.02
+  %0 = load i32, i32* %arrayidx, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %for.inc, label %if.then
 
 if.then:                                          ; preds = %for.body
   %div = sdiv i64 %x, %and
-  %arrayidx1 = getelementptr inbounds i64* %q, i64 %i.02
+  %arrayidx1 = getelementptr inbounds i64, i64* %q, i64 %i.02
   store i64 %div, i64* %arrayidx1, align 8
   br label %for.inc
 
diff --git a/test/Transforms/LICM/volatile-alias.ll b/test/Transforms/LICM/volatile-alias.ll
index df7f0a931eb8..fda930df933b 100644
--- a/test/Transforms/LICM/volatile-alias.ll
+++ b/test/Transforms/LICM/volatile-alias.ll
@@ -2,9 +2,9 @@
 ; The objects *p and *q are aliased to each other, but even though *q is
 ; volatile, *p can be considered invariant in the loop. Check if it is moved
 ; out of the loop.
-; CHECK: load i32* %p
+; CHECK: load i32, i32* %p
 ; CHECK: for.body:
-; CHECK: load volatile i32* %q
+; CHECK: load volatile i32, i32* %q
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 
@@ -24,30 +24,30 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
-  %1 = load i32* %n.addr, align 4
+  %0 = load i32, i32* %i, align 4
+  %1 = load i32, i32* %n.addr, align 4
   %cmp = icmp slt i32 %0, %1
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %2 = load i32** %p.addr, align 8
-  %3 = load i32* %2, align 4
-  %4 = load i32** %q.addr, align 8
-  %5 = load volatile i32* %4, align 4
+  %2 = load i32*, i32** %p.addr, align 8
+  %3 = load i32, i32* %2, align 4
+  %4 = load i32*, i32** %q.addr, align 8
+  %5 = load volatile i32, i32* %4, align 4
   %add = add nsw i32 %3, %5
-  %6 = load i32* %s, align 4
+  %6 = load i32, i32* %s, align 4
   %add1 = add nsw i32 %6, %add
   store i32 %add1, i32* %s, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %7 = load i32* %i, align 4
+  %7 = load i32, i32* %i, align 4
   %inc = add nsw i32 %7, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %8 = load i32* %s, align 4
+  %8 = load i32, i32* %s, align 4
   ret i32 %8
 }
 
diff --git a/test/Transforms/LoadCombine/load-combine-aa.ll b/test/Transforms/LoadCombine/load-combine-aa.ll
index 3542dcebf5e4..fc639c0bc05d 100644
--- a/test/Transforms/LoadCombine/load-combine-aa.ll
+++ b/test/Transforms/LoadCombine/load-combine-aa.ll
@@ -5,14 +5,14 @@ target triple = "x86_64-unknown-linux-gnu"
 define i64 @test1(i32* nocapture readonly noalias %a, i32* nocapture readonly noalias %b) {
 ; CHECK-LABEL: @test1
 
-; CHECK: load i64*
+; CHECK: load i64, i64*
 ; CHECK: ret i64
 
-  %load1 = load i32* %a, align 4
+  %load1 = load i32, i32* %a, align 4
   %conv = zext i32 %load1 to i64
-  %arrayidx1 = getelementptr inbounds i32* %a, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %a, i64 1
   store i32 %load1, i32* %b, align 4
-  %load2 = load i32* %arrayidx1, align 4
+  %load2 = load i32, i32* %arrayidx1, align 4
   %conv2 = zext i32 %load2 to i64
   %shl = shl nuw i64 %conv2, 32
   %add = or i64 %shl, %conv
@@ -22,15 +22,15 @@ define i64 @test1(i32* nocapture readonly noalias %a, i32* nocapture readonly no
 define i64 @test2(i32* nocapture readonly %a, i32* nocapture readonly %b) {
 ; CHECK-LABEL: @test2
 
-; CHECK: load i32*
-; CHECK: load i32*
+; CHECK: load i32, i32*
+; CHECK: load i32, i32*
 ; CHECK: ret i64
 
-  %load1 = load i32* %a, align 4
+  %load1 = load i32, i32* %a, align 4
   %conv = zext i32 %load1 to i64
-  %arrayidx1 = getelementptr inbounds i32* %a, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %a, i64 1
   store i32 %load1, i32* %b, align 4
-  %load2 = load i32* %arrayidx1, align 4
+  %load2 = load i32, i32* %arrayidx1, align 4
   %conv2 = zext i32 %load2 to i64
   %shl = shl nuw i64 %conv2, 32
   %add = or i64 %shl, %conv
diff --git a/test/Transforms/LoadCombine/load-combine-assume.ll b/test/Transforms/LoadCombine/load-combine-assume.ll
index 94f630072add..2d6d160f12fe 100644
--- a/test/Transforms/LoadCombine/load-combine-assume.ll
+++ b/test/Transforms/LoadCombine/load-combine-assume.ll
@@ -8,14 +8,14 @@ declare void @llvm.assume(i1) nounwind
 define i64 @test1(i32* nocapture readonly %a, i1 %b) {
 ; CHECK-LABEL: @test1
 
-; CHECK-DAG: load i64* %1, align 4
+; CHECK-DAG: load i64, i64* %1, align 4
 ; CHECK-DAG: tail call void @llvm.assume(i1 %b)
 ; CHECK: ret i64
 
-  %load1 = load i32* %a, align 4
+  %load1 = load i32, i32* %a, align 4
   %conv = zext i32 %load1 to i64
-  %arrayidx1 = getelementptr inbounds i32* %a, i64 1
-  %load2 = load i32* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %a, i64 1
+  %load2 = load i32, i32* %arrayidx1, align 4
   tail call void @llvm.assume(i1 %b)
   %conv2 = zext i32 %load2 to i64
   %shl = shl nuw i64 %conv2, 32
@@ -27,15 +27,15 @@ define i64 @test1(i32* nocapture readonly %a, i1 %b) {
 define i64 @test2(i32* nocapture readonly %a, i1 %b) {
 ; CHECK-LABEL: @test2
 
-; CHECK-DAG: load i64* %1, align 4
+; CHECK-DAG: load i64, i64* %1, align 4
 ; CHECK-DAG: tail call void @llvm.assume(i1 %b)
 ; CHECK: ret i64
 
-  %load1 = load i32* %a, align 4
+  %load1 = load i32, i32* %a, align 4
   %conv = zext i32 %load1 to i64
-  %arrayidx1 = getelementptr inbounds i32* %a, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %a, i64 1
   tail call void @llvm.assume(i1 %b)
-  %load2 = load i32* %arrayidx1, align 4
+  %load2 = load i32, i32* %arrayidx1, align 4
   %conv2 = zext i32 %load2 to i64
   %shl = shl nuw i64 %conv2, 32
   %add = or i64 %shl, %conv
diff --git a/test/Transforms/LoadCombine/load-combine.ll b/test/Transforms/LoadCombine/load-combine.ll
index c4d9241764d9..d5068787639f 100644
--- a/test/Transforms/LoadCombine/load-combine.ll
+++ b/test/Transforms/LoadCombine/load-combine.ll
@@ -6,138 +6,138 @@ target triple = "x86_64-unknown-linux-gnu"
 ; Combine read from char* idiom.
 define i64 @LoadU64_x64_0(i64* %pData) {
   %1 = bitcast i64* %pData to i8*
-  %2 = load i8* %1, align 1
+  %2 = load i8, i8* %1, align 1
   %3 = zext i8 %2 to i64
   %4 = shl nuw i64 %3, 56
-  %5 = getelementptr inbounds i8* %1, i64 1
-  %6 = load i8* %5, align 1
+  %5 = getelementptr inbounds i8, i8* %1, i64 1
+  %6 = load i8, i8* %5, align 1
   %7 = zext i8 %6 to i64
   %8 = shl nuw nsw i64 %7, 48
   %9 = or i64 %8, %4
-  %10 = getelementptr inbounds i8* %1, i64 2
-  %11 = load i8* %10, align 1
+  %10 = getelementptr inbounds i8, i8* %1, i64 2
+  %11 = load i8, i8* %10, align 1
   %12 = zext i8 %11 to i64
   %13 = shl nuw nsw i64 %12, 40
   %14 = or i64 %9, %13
-  %15 = getelementptr inbounds i8* %1, i64 3
-  %16 = load i8* %15, align 1
+  %15 = getelementptr inbounds i8, i8* %1, i64 3
+  %16 = load i8, i8* %15, align 1
   %17 = zext i8 %16 to i64
   %18 = shl nuw nsw i64 %17, 32
   %19 = or i64 %14, %18
-  %20 = getelementptr inbounds i8* %1, i64 4
-  %21 = load i8* %20, align 1
+  %20 = getelementptr inbounds i8, i8* %1, i64 4
+  %21 = load i8, i8* %20, align 1
   %22 = zext i8 %21 to i64
   %23 = shl nuw nsw i64 %22, 24
   %24 = or i64 %19, %23
-  %25 = getelementptr inbounds i8* %1, i64 5
-  %26 = load i8* %25, align 1
+  %25 = getelementptr inbounds i8, i8* %1, i64 5
+  %26 = load i8, i8* %25, align 1
   %27 = zext i8 %26 to i64
   %28 = shl nuw nsw i64 %27, 16
   %29 = or i64 %24, %28
-  %30 = getelementptr inbounds i8* %1, i64 6
-  %31 = load i8* %30, align 1
+  %30 = getelementptr inbounds i8, i8* %1, i64 6
+  %31 = load i8, i8* %30, align 1
   %32 = zext i8 %31 to i64
   %33 = shl nuw nsw i64 %32, 8
   %34 = or i64 %29, %33
-  %35 = getelementptr inbounds i8* %1, i64 7
-  %36 = load i8* %35, align 1
+  %35 = getelementptr inbounds i8, i8* %1, i64 7
+  %36 = load i8, i8* %35, align 1
   %37 = zext i8 %36 to i64
   %38 = or i64 %34, %37
   ret i64 %38
 ; CHECK-LABEL: @LoadU64_x64_0(
-; CHECK: load i64* %{{.*}}, align 1
+; CHECK: load i64, i64* %{{.*}}, align 1
 ; CHECK-NOT: load
 }
 
 ; Combine simple adjacent loads.
 define i32 @"2xi16_i32"(i16* %x) {
-  %1 = load i16* %x, align 2
-  %2 = getelementptr inbounds i16* %x, i64 1
-  %3 = load i16* %2, align 2
+  %1 = load i16, i16* %x, align 2
+  %2 = getelementptr inbounds i16, i16* %x, i64 1
+  %3 = load i16, i16* %2, align 2
   %4 = zext i16 %3 to i32
   %5 = shl nuw i32 %4, 16
   %6 = zext i16 %1 to i32
   %7 = or i32 %5, %6
   ret i32 %7
 ; CHECK-LABEL: @"2xi16_i32"(
-; CHECK: load i32* %{{.*}}, align 2
+; CHECK: load i32, i32* %{{.*}}, align 2
 ; CHECK-NOT: load
 }
 
 ; Don't combine loads across stores.
 define i32 @"2xi16_i32_store"(i16* %x, i16* %y) {
-  %1 = load i16* %x, align 2
+  %1 = load i16, i16* %x, align 2
   store i16 0, i16* %y, align 2
-  %2 = getelementptr inbounds i16* %x, i64 1
-  %3 = load i16* %2, align 2
+  %2 = getelementptr inbounds i16, i16* %x, i64 1
+  %3 = load i16, i16* %2, align 2
   %4 = zext i16 %3 to i32
   %5 = shl nuw i32 %4, 16
   %6 = zext i16 %1 to i32
   %7 = or i32 %5, %6
   ret i32 %7
 ; CHECK-LABEL: @"2xi16_i32_store"(
-; CHECK: load i16* %{{.*}}, align 2
+; CHECK: load i16, i16* %{{.*}}, align 2
 ; CHECK: store
-; CHECK: load i16* %{{.*}}, align 2
+; CHECK: load i16, i16* %{{.*}}, align 2
 }
 
 ; Don't combine loads with a gap.
 define i32 @"2xi16_i32_gap"(i16* %x) {
-  %1 = load i16* %x, align 2
-  %2 = getelementptr inbounds i16* %x, i64 2
-  %3 = load i16* %2, align 2
+  %1 = load i16, i16* %x, align 2
+  %2 = getelementptr inbounds i16, i16* %x, i64 2
+  %3 = load i16, i16* %2, align 2
   %4 = zext i16 %3 to i32
   %5 = shl nuw i32 %4, 16
   %6 = zext i16 %1 to i32
   %7 = or i32 %5, %6
   ret i32 %7
 ; CHECK-LABEL: @"2xi16_i32_gap"(
-; CHECK: load i16* %{{.*}}, align 2
-; CHECK: load i16* %{{.*}}, align 2
+; CHECK: load i16, i16* %{{.*}}, align 2
+; CHECK: load i16, i16* %{{.*}}, align 2
 }
 
 ; Combine out of order loads.
 define i32 @"2xi16_i32_order"(i16* %x) {
-  %1 = getelementptr inbounds i16* %x, i64 1
-  %2 = load i16* %1, align 2
+  %1 = getelementptr inbounds i16, i16* %x, i64 1
+  %2 = load i16, i16* %1, align 2
   %3 = zext i16 %2 to i32
-  %4 = load i16* %x, align 2
+  %4 = load i16, i16* %x, align 2
   %5 = shl nuw i32 %3, 16
   %6 = zext i16 %4 to i32
   %7 = or i32 %5, %6
   ret i32 %7
 ; CHECK-LABEL: @"2xi16_i32_order"(
-; CHECK: load i32* %{{.*}}, align 2
+; CHECK: load i32, i32* %{{.*}}, align 2
 ; CHECK-NOT: load
 }
 
 ; Overlapping loads.
 define i32 @"2xi16_i32_overlap"(i8* %x) {
   %1 = bitcast i8* %x to i16*
-  %2 = load i16* %1, align 2
-  %3 = getelementptr inbounds i8* %x, i64 1
+  %2 = load i16, i16* %1, align 2
+  %3 = getelementptr inbounds i8, i8* %x, i64 1
   %4 = bitcast i8* %3 to i16*
-  %5 = load i16* %4, align 2
+  %5 = load i16, i16* %4, align 2
   %6 = zext i16 %5 to i32
   %7 = shl nuw i32 %6, 16
   %8 = zext i16 %2 to i32
   %9 = or i32 %7, %8
   ret i32 %9
 ; CHECK-LABEL: @"2xi16_i32_overlap"(
-; CHECK: load i16* %{{.*}}, align 2
-; CHECK: load i16* %{{.*}}, align 2
+; CHECK: load i16, i16* %{{.*}}, align 2
+; CHECK: load i16, i16* %{{.*}}, align 2
 }
 
 ; Combine valid alignments.
 define i64 @"2xi16_i64_align"(i8* %x) {
   %1 = bitcast i8* %x to i32*
-  %2 = load i32* %1, align 4
-  %3 = getelementptr inbounds i8* %x, i64 4
+  %2 = load i32, i32* %1, align 4
+  %3 = getelementptr inbounds i8, i8* %x, i64 4
   %4 = bitcast i8* %3 to i16*
-  %5 = load i16* %4, align 2
-  %6 = getelementptr inbounds i8* %x, i64 6
+  %5 = load i16, i16* %4, align 2
+  %6 = getelementptr inbounds i8, i8* %x, i64 6
   %7 = bitcast i8* %6 to i16*
-  %8 = load i16* %7, align 2
+  %8 = load i16, i16* %7, align 2
   %9 = zext i16 %8 to i64
   %10 = shl nuw i64 %9, 48
   %11 = zext i16 %5 to i64
@@ -147,44 +147,44 @@ define i64 @"2xi16_i64_align"(i8* %x) {
   %15 = or i64 %14, %10
   ret i64 %15
 ; CHECK-LABEL: @"2xi16_i64_align"(
-; CHECK: load i64* %{{.*}}, align 4
+; CHECK: load i64, i64* %{{.*}}, align 4
 }
 
 ; Non power of two.
 define i64 @"2xi16_i64_npo2"(i8* %x) {
-  %1 = load i8* %x, align 1
+  %1 = load i8, i8* %x, align 1
   %2 = zext i8 %1 to i64
-  %3 = getelementptr inbounds i8* %x, i64 1
-  %4 = load i8* %3, align 1
+  %3 = getelementptr inbounds i8, i8* %x, i64 1
+  %4 = load i8, i8* %3, align 1
   %5 = zext i8 %4 to i64
   %6 = shl nuw nsw i64 %5, 8
   %7 = or i64 %6, %2
-  %8 = getelementptr inbounds i8* %x, i64 2
-  %9 = load i8* %8, align 1
+  %8 = getelementptr inbounds i8, i8* %x, i64 2
+  %9 = load i8, i8* %8, align 1
   %10 = zext i8 %9 to i64
   %11 = shl nuw nsw i64 %10, 16
   %12 = or i64 %11, %7
-  %13 = getelementptr inbounds i8* %x, i64 3
-  %14 = load i8* %13, align 1
+  %13 = getelementptr inbounds i8, i8* %x, i64 3
+  %14 = load i8, i8* %13, align 1
   %15 = zext i8 %14 to i64
   %16 = shl nuw nsw i64 %15, 24
   %17 = or i64 %16, %12
-  %18 = getelementptr inbounds i8* %x, i64 4
-  %19 = load i8* %18, align 1
+  %18 = getelementptr inbounds i8, i8* %x, i64 4
+  %19 = load i8, i8* %18, align 1
   %20 = zext i8 %19 to i64
   %21 = shl nuw nsw i64 %20, 32
   %22 = or i64 %21, %17
-  %23 = getelementptr inbounds i8* %x, i64 5
-  %24 = load i8* %23, align 1
+  %23 = getelementptr inbounds i8, i8* %x, i64 5
+  %24 = load i8, i8* %23, align 1
   %25 = zext i8 %24 to i64
   %26 = shl nuw nsw i64 %25, 40
   %27 = or i64 %26, %22
-  %28 = getelementptr inbounds i8* %x, i64 6
-  %29 = load i8* %28, align 1
+  %28 = getelementptr inbounds i8, i8* %x, i64 6
+  %29 = load i8, i8* %28, align 1
   %30 = zext i8 %29 to i64
   %31 = shl nuw nsw i64 %30, 48
   %32 = or i64 %31, %27
   ret i64 %32
 ; CHECK-LABEL: @"2xi16_i64_npo2"(
-; CHECK: load i32* %{{.*}}, align 1
+; CHECK: load i32, i32* %{{.*}}, align 1
 }
diff --git a/test/Transforms/LoopDeletion/2008-05-06-Phi.ll b/test/Transforms/LoopDeletion/2008-05-06-Phi.ll
index ff6a30d3a342..fcf5ede76b71 100644
--- a/test/Transforms/LoopDeletion/2008-05-06-Phi.ll
+++ b/test/Transforms/LoopDeletion/2008-05-06-Phi.ll
@@ -23,7 +23,7 @@ declare %struct.BF_PartHolder* @BF_addElement(%struct.BF_PartHolder*, %struct.BF
 define %struct.BF_PartHolder* @BF_addEntry(%struct.BF_PartHolder* %thePH, i32 %value, i32 %length) nounwind  {
 entry:
 	%myElement = alloca %struct.BF_BitstreamElement		; <%struct.BF_BitstreamElement*> [#uses=2]
-	%tmp1 = getelementptr %struct.BF_BitstreamElement* %myElement, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp1 = getelementptr %struct.BF_BitstreamElement, %struct.BF_BitstreamElement* %myElement, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 %value, i32* %tmp1, align 8
 	%tmp7 = icmp eq i32 %length, 0		; <i1> [#uses=1]
 	br i1 %tmp7, label %bb13, label %bb
@@ -44,15 +44,15 @@ entry:
 
 define internal fastcc void @encodeMainData(%struct.lame_global_flags* %gfp, [2 x [576 x i32]]* %l3_enc, %struct.III_side_info_t* %si, [2 x %struct.III_scalefac_t]* %scalefac) nounwind  {
 entry:
-	%tmp69 = getelementptr %struct.lame_global_flags* %gfp, i32 0, i32 43		; <i32*> [#uses=1]
-	%tmp70 = load i32* %tmp69, align 4		; <i32> [#uses=1]
+	%tmp69 = getelementptr %struct.lame_global_flags, %struct.lame_global_flags* %gfp, i32 0, i32 43		; <i32*> [#uses=1]
+	%tmp70 = load i32, i32* %tmp69, align 4		; <i32> [#uses=1]
 	%tmp71 = icmp eq i32 %tmp70, 1		; <i1> [#uses=1]
 	br i1 %tmp71, label %bb352, label %bb498
 
 bb113:		; preds = %bb132
-	%tmp123 = getelementptr [2 x %struct.III_scalefac_t]* %scalefac, i32 0, i32 0, i32 1, i32 %sfb.0, i32 %window.0		; <i32*> [#uses=1]
-	%tmp124 = load i32* %tmp123, align 4		; <i32> [#uses=1]
-	%tmp126 = load %struct.BF_PartHolder** %tmp80, align 4		; <%struct.BF_PartHolder*> [#uses=1]
+	%tmp123 = getelementptr [2 x %struct.III_scalefac_t], [2 x %struct.III_scalefac_t]* %scalefac, i32 0, i32 0, i32 1, i32 %sfb.0, i32 %window.0		; <i32*> [#uses=1]
+	%tmp124 = load i32, i32* %tmp123, align 4		; <i32> [#uses=1]
+	%tmp126 = load %struct.BF_PartHolder*, %struct.BF_PartHolder** %tmp80, align 4		; <%struct.BF_PartHolder*> [#uses=1]
 	%tmp128 = call %struct.BF_PartHolder* @BF_addEntry( %struct.BF_PartHolder* %tmp126, i32 %tmp124, i32 %tmp93 ) nounwind 		; <%struct.BF_PartHolder*> [#uses=1]
 	store %struct.BF_PartHolder* %tmp128, %struct.BF_PartHolder** %tmp80, align 4
 	%tmp131 = add i32 %window.0, 1		; <i32> [#uses=1]
@@ -73,7 +73,7 @@ bb140:		; preds = %bb341, %bb137
 	br i1 %tmp142, label %bb132, label %bb174
 
 bb166:		; preds = %bb174
-	%tmp160 = load %struct.BF_PartHolder** %tmp80, align 4		; <%struct.BF_PartHolder*> [#uses=1]
+	%tmp160 = load %struct.BF_PartHolder*, %struct.BF_PartHolder** %tmp80, align 4		; <%struct.BF_PartHolder*> [#uses=1]
 	%tmp162 = call %struct.BF_PartHolder* @BF_addEntry( %struct.BF_PartHolder* %tmp160, i32 0, i32 0 ) nounwind 		; <%struct.BF_PartHolder*> [#uses=0]
 	unreachable
 
@@ -82,9 +82,9 @@ bb174:		; preds = %bb140
 	br i1 %tmp176, label %bb166, label %bb341
 
 bb341:		; preds = %bb352, %bb174
-	%tmp80 = getelementptr [2 x [2 x %struct.BF_PartHolder*]]* @scaleFactorsPH, i32 0, i32 0, i32 0		; <%struct.BF_PartHolder**> [#uses=3]
-	%tmp92 = getelementptr [16 x i32]* @slen1_tab, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp93 = load i32* %tmp92, align 4		; <i32> [#uses=1]
+	%tmp80 = getelementptr [2 x [2 x %struct.BF_PartHolder*]], [2 x [2 x %struct.BF_PartHolder*]]* @scaleFactorsPH, i32 0, i32 0, i32 0		; <%struct.BF_PartHolder**> [#uses=3]
+	%tmp92 = getelementptr [16 x i32], [16 x i32]* @slen1_tab, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp93 = load i32, i32* %tmp92, align 4		; <i32> [#uses=1]
 	br label %bb140
 
 bb352:		; preds = %entry
diff --git a/test/Transforms/LoopDistribute/basic-with-memchecks.ll b/test/Transforms/LoopDistribute/basic-with-memchecks.ll
new file mode 100644
index 000000000000..4c1c1b822964
--- /dev/null
+++ b/test/Transforms/LoopDistribute/basic-with-memchecks.ll
@@ -0,0 +1,112 @@
+; RUN: opt -basicaa -loop-distribute -verify-loop-info -verify-dom-info -S \
+; RUN:   < %s | FileCheck %s
+
+; RUN: opt -basicaa -loop-distribute -loop-vectorize -force-vector-width=4 \
+; RUN:   -verify-loop-info -verify-dom-info -S < %s | \
+; RUN:   FileCheck --check-prefix=VECTORIZE %s
+
+; The memcheck version of basic.ll.  We should distribute and vectorize the
+; second part of this loop with 5 memchecks (A+1 x {C, D, E} + C x {A, B})
+;
+;   for (i = 0; i < n; i++) {
+;     A[i + 1] = A[i] * B[i];
+; -------------------------------
+;     C[i] = D[i] * E[i];
+;   }
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+@B = common global i32* null, align 8
+@A = common global i32* null, align 8
+@C = common global i32* null, align 8
+@D = common global i32* null, align 8
+@E = common global i32* null, align 8
+
+define void @f() {
+entry:
+  %a = load i32*, i32** @A, align 8
+  %b = load i32*, i32** @B, align 8
+  %c = load i32*, i32** @C, align 8
+  %d = load i32*, i32** @D, align 8
+  %e = load i32*, i32** @E, align 8
+  br label %for.body
+
+; We have two compares for each array overlap check which is a total of 10
+; compares.
+;
+; CHECK: for.body.ldist.memcheck:
+; CHECK:     = icmp
+; CHECK:     = icmp
+
+; CHECK:     = icmp
+; CHECK:     = icmp
+
+; CHECK:     = icmp
+; CHECK:     = icmp
+
+; CHECK:     = icmp
+; CHECK:     = icmp
+
+; CHECK:     = icmp
+; CHECK:     = icmp
+
+; CHECK-NOT: = icmp
+; CHECK:     br i1 %memcheck.conflict, label %for.body.ph.ldist.nondist, label %for.body.ph.ldist1
+
+; The non-distributed loop that the memchecks fall back on.
+
+; CHECK: for.body.ph.ldist.nondist:
+; CHECK:     br label %for.body.ldist.nondist
+; CHECK: for.body.ldist.nondist:
+; CHECK:    br i1 %exitcond.ldist.nondist, label %for.end, label %for.body.ldist.nondist
+
+; Verify the two distributed loops.
+
+; CHECK: for.body.ph.ldist1:
+; CHECK:     br label %for.body.ldist1
+; CHECK: for.body.ldist1:
+; CHECK:    %mulA.ldist1 = mul i32 %loadB.ldist1, %loadA.ldist1
+; CHECK:    br i1 %exitcond.ldist1, label %for.body.ph, label %for.body.ldist1
+
+; CHECK: for.body.ph:
+; CHECK:    br label %for.body
+; CHECK: for.body:
+; CHECK:    %mulC = mul i32 %loadD, %loadE
+; CHECK: for.end:
+
+
+; VECTORIZE: mul <4 x i32>
+
+for.body:                                         ; preds = %for.body, %entry
+  %ind = phi i64 [ 0, %entry ], [ %add, %for.body ]
+
+  %arrayidxA = getelementptr inbounds i32, i32* %a, i64 %ind
+  %loadA = load i32, i32* %arrayidxA, align 4
+
+  %arrayidxB = getelementptr inbounds i32, i32* %b, i64 %ind
+  %loadB = load i32, i32* %arrayidxB, align 4
+
+  %mulA = mul i32 %loadB, %loadA
+
+  %add = add nuw nsw i64 %ind, 1
+  %arrayidxA_plus_4 = getelementptr inbounds i32, i32* %a, i64 %add
+  store i32 %mulA, i32* %arrayidxA_plus_4, align 4
+
+  %arrayidxD = getelementptr inbounds i32, i32* %d, i64 %ind
+  %loadD = load i32, i32* %arrayidxD, align 4
+
+  %arrayidxE = getelementptr inbounds i32, i32* %e, i64 %ind
+  %loadE = load i32, i32* %arrayidxE, align 4
+
+  %mulC = mul i32 %loadD, %loadE
+
+  %arrayidxC = getelementptr inbounds i32, i32* %c, i64 %ind
+  store i32 %mulC, i32* %arrayidxC, align 4
+
+  %exitcond = icmp eq i64 %add, 20
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
diff --git a/test/Transforms/LoopDistribute/basic.ll b/test/Transforms/LoopDistribute/basic.ll
new file mode 100644
index 000000000000..f19fa8bb1b14
--- /dev/null
+++ b/test/Transforms/LoopDistribute/basic.ll
@@ -0,0 +1,83 @@
+; RUN: opt -basicaa -loop-distribute -verify-loop-info -verify-dom-info -S \
+; RUN:   < %s | FileCheck %s
+
+; RUN: opt -basicaa -loop-distribute -verify-loop-info -verify-dom-info \
+; RUN:   -loop-accesses -analyze < %s | FileCheck %s --check-prefix=ANALYSIS
+
+; RUN: opt -basicaa -loop-distribute -loop-vectorize -force-vector-width=4 -S \
+; RUN:   < %s | FileCheck %s --check-prefix=VECTORIZE
+
+; We should distribute this loop into a safe (2nd statement) and unsafe loop
+; (1st statement):
+;   for (i = 0; i < n; i++) {
+;     A[i + 1] = A[i] * B[i];
+;     =======================
+;     C[i] = D[i] * E[i];
+;   }
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+define void @f(i32* noalias %a,
+               i32* noalias %b,
+               i32* noalias %c,
+               i32* noalias %d,
+               i32* noalias %e) {
+entry:
+  br label %for.body
+
+; Verify the two distributed loops.
+
+; CHECK: entry.split.ldist1:
+; CHECK:    br label %for.body.ldist1
+; CHECK: for.body.ldist1:
+; CHECK:    %mulA.ldist1 = mul i32 %loadB.ldist1, %loadA.ldist1
+; CHECK:    br i1 %exitcond.ldist1, label %entry.split, label %for.body.ldist1
+
+; CHECK: entry.split:
+; CHECK:    br label %for.body
+; CHECK: for.body:
+; CHECK:    %mulC = mul i32 %loadD, %loadE
+; CHECK: for.end:
+
+
+; ANALYSIS: for.body:
+; ANALYSIS-NEXT: Memory dependences are safe{{$}}
+; ANALYSIS: for.body.ldist1:
+; ANALYSIS-NEXT: Report: unsafe dependent memory operations in loop
+
+
+; VECTORIZE: mul <4 x i32>
+
+for.body:                                         ; preds = %for.body, %entry
+  %ind = phi i64 [ 0, %entry ], [ %add, %for.body ]
+
+  %arrayidxA = getelementptr inbounds i32, i32* %a, i64 %ind
+  %loadA = load i32, i32* %arrayidxA, align 4
+
+  %arrayidxB = getelementptr inbounds i32, i32* %b, i64 %ind
+  %loadB = load i32, i32* %arrayidxB, align 4
+
+  %mulA = mul i32 %loadB, %loadA
+
+  %add = add nuw nsw i64 %ind, 1
+  %arrayidxA_plus_4 = getelementptr inbounds i32, i32* %a, i64 %add
+  store i32 %mulA, i32* %arrayidxA_plus_4, align 4
+
+  %arrayidxD = getelementptr inbounds i32, i32* %d, i64 %ind
+  %loadD = load i32, i32* %arrayidxD, align 4
+
+  %arrayidxE = getelementptr inbounds i32, i32* %e, i64 %ind
+  %loadE = load i32, i32* %arrayidxE, align 4
+
+  %mulC = mul i32 %loadD, %loadE
+
+  %arrayidxC = getelementptr inbounds i32, i32* %c, i64 %ind
+  store i32 %mulC, i32* %arrayidxC, align 4
+
+  %exitcond = icmp eq i64 %add, 20
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
diff --git a/test/Transforms/LoopDistribute/crash-in-memcheck-generation.ll b/test/Transforms/LoopDistribute/crash-in-memcheck-generation.ll
new file mode 100644
index 000000000000..c81ddf59fa7c
--- /dev/null
+++ b/test/Transforms/LoopDistribute/crash-in-memcheck-generation.ll
@@ -0,0 +1,59 @@
+; RUN: opt -basicaa -loop-distribute -loop-vectorize -force-vector-width=4 \
+; RUN:   -verify-loop-info -verify-dom-info -S < %s | FileCheck %s
+
+; If only A and B can alias here, we don't need memchecks to distribute since
+; A and B are in the same partition.  This used to cause a crash in the
+; memcheck generation.
+;
+;   for (i = 0; i < n; i++) {
+;     A[i + 1] = A[i] * B[i];
+; ------------------------------
+;     C[i] = D[i] * E[i];
+;   }
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+define void @f(i32*  %a,
+               i32*  %b,
+               i32* noalias %c,
+               i32* noalias %d,
+               i32* noalias %e) {
+entry:
+  br label %for.body
+
+; CHECK-NOT: memcheck:
+; CHECK: mul <4 x i32>
+
+for.body:                                         ; preds = %for.body, %entry
+  %ind = phi i64 [ 0, %entry ], [ %add, %for.body ]
+
+  %arrayidxA = getelementptr inbounds i32, i32* %a, i64 %ind
+  %loadA = load i32, i32* %arrayidxA, align 4
+
+  %arrayidxB = getelementptr inbounds i32, i32* %b, i64 %ind
+  %loadB = load i32, i32* %arrayidxB, align 4
+
+  %mulA = mul i32 %loadB, %loadA
+
+  %add = add nuw nsw i64 %ind, 1
+  %arrayidxA_plus_4 = getelementptr inbounds i32, i32* %a, i64 %add
+  store i32 %mulA, i32* %arrayidxA_plus_4, align 4
+
+  %arrayidxD = getelementptr inbounds i32, i32* %d, i64 %ind
+  %loadD = load i32, i32* %arrayidxD, align 4
+
+  %arrayidxE = getelementptr inbounds i32, i32* %e, i64 %ind
+  %loadE = load i32, i32* %arrayidxE, align 4
+
+  %mulC = mul i32 %loadD, %loadE
+
+  %arrayidxC = getelementptr inbounds i32, i32* %c, i64 %ind
+  store i32 %mulC, i32* %arrayidxC, align 4
+
+  %exitcond = icmp eq i64 %add, 20
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
diff --git a/test/Transforms/LoopDistribute/no-if-convert.ll b/test/Transforms/LoopDistribute/no-if-convert.ll
new file mode 100644
index 000000000000..fcd8b65731cc
--- /dev/null
+++ b/test/Transforms/LoopDistribute/no-if-convert.ll
@@ -0,0 +1,95 @@
+; RUN: opt -basicaa -loop-distribute -verify-loop-info -verify-dom-info -S < %s \
+; RUN:   | FileCheck %s
+
+; We should distribute this loop along === but not along ---.  The last
+; partition won't be vectorized due to conditional stores so it's better to
+; keep it with the second partition which has a dependence cycle.
+
+; (1st statement):
+;   for (i = 0; i < n; i++) {
+;     C[i] = D[i] * E[i];
+;=============================
+;     A[i + 1] = A[i] * B[i];
+;-----------------------------
+;     if (F[i])
+;        G[i] = H[i] * J[i];
+;   }
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+define void @f(i32* noalias %a,
+               i32* noalias %b,
+               i32* noalias %c,
+               i32* noalias %d,
+               i32* noalias %e,
+               i32* noalias %g,
+               i32* noalias %h,
+               i32* noalias %j,
+               i64 %x) {
+entry:
+  br label %for.body
+
+; Ensure that we have only two partitions, the first with one multiplication
+; and the second with two.
+
+; CHECK: for.body.ldist1:
+; CHECK:    %mulC.ldist1 = mul i32 %loadD.ldist1, %loadE.ldist1
+; CHECK:    br i1 %exitcond.ldist1, label %entry.split, label %for.body.ldist1
+; CHECK: entry.split:
+; CHECK:    br label %for.body
+; CHECK: for.body:
+; CHECK:    %mulA = mul i32 %loadB, %loadA
+; CHECK:    %mulG = mul i32 %loadH, %loadJ
+; CHECK: for.end:
+
+for.body:                                         ; preds = %for.body, %entry
+  %ind = phi i64 [ 0, %entry ], [ %add, %if.end ]
+
+  %arrayidxD = getelementptr inbounds i32, i32* %d, i64 %ind
+  %loadD = load i32, i32* %arrayidxD, align 4
+
+  %arrayidxE = getelementptr inbounds i32, i32* %e, i64 %ind
+  %loadE = load i32, i32* %arrayidxE, align 4
+
+  %mulC = mul i32 %loadD, %loadE
+
+  %arrayidxC = getelementptr inbounds i32, i32* %c, i64 %ind
+  store i32 %mulC, i32* %arrayidxC, align 4
+
+
+  %arrayidxA = getelementptr inbounds i32, i32* %a, i64 %ind
+  %loadA = load i32, i32* %arrayidxA, align 4
+
+  %arrayidxB = getelementptr inbounds i32, i32* %b, i64 %ind
+  %loadB = load i32, i32* %arrayidxB, align 4
+
+  %mulA = mul i32 %loadB, %loadA
+
+  %add = add nuw nsw i64 %ind, 1
+  %arrayidxA_plus_4 = getelementptr inbounds i32, i32* %a, i64 %add
+  store i32 %mulA, i32* %arrayidxA_plus_4, align 4
+
+  %if.cond = icmp eq i64 %ind, %x
+  br i1 %if.cond, label %if.then, label %if.end
+
+if.then:
+  %arrayidxH = getelementptr inbounds i32, i32* %h, i64 %ind
+  %loadH = load i32, i32* %arrayidxH, align 4
+
+  %arrayidxJ = getelementptr inbounds i32, i32* %j, i64 %ind
+  %loadJ = load i32, i32* %arrayidxJ, align 4
+
+  %mulG = mul i32 %loadH, %loadJ
+
+  %arrayidxG = getelementptr inbounds i32, i32* %g, i64 %ind
+  store i32 %mulG, i32* %arrayidxG, align 4
+  br label %if.end
+
+if.end:
+  %exitcond = icmp eq i64 %add, 20
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
diff --git a/test/Transforms/LoopDistribute/outside-use.ll b/test/Transforms/LoopDistribute/outside-use.ll
new file mode 100644
index 000000000000..546050d5b046
--- /dev/null
+++ b/test/Transforms/LoopDistribute/outside-use.ll
@@ -0,0 +1,69 @@
+; RUN: opt -loop-distribute -verify-loop-info -verify-dom-info -S < %s \
+; RUN:   | FileCheck %s
+
+; Check that definitions used outside the loop are handled correctly: (1) they
+; are not dropped (2) when version the loop, a phi is added to merge the value
+; from the non-distributed loop and the distributed loop.
+;
+;   for (i = 0; i < n; i++) {
+;     A[i + 1] = A[i] * B[i];
+;   ==========================
+;     sum += C[i];
+;   }
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+@B = common global i32* null, align 8
+@A = common global i32* null, align 8
+@C = common global i32* null, align 8
+@D = common global i32* null, align 8
+@E = common global i32* null, align 8
+@SUM = common global i32 0, align 8
+
+define void @f() {
+entry:
+  %a = load i32*, i32** @A, align 8
+  %b = load i32*, i32** @B, align 8
+  %c = load i32*, i32** @C, align 8
+  %d = load i32*, i32** @D, align 8
+  %e = load i32*, i32** @E, align 8
+
+  br label %for.body
+
+; CHECK: for.body.ldist1:
+; CHECK:   %mulA.ldist1 = mul i32 %loadB.ldist1, %loadA.ldist1
+; CHECK: for.body.ph:
+; CHECK: for.body:
+; CHECK:   %sum_add = add nuw nsw i32 %sum, %loadC
+; CHECK: for.end:
+; CHECK:   %sum_add.ldist = phi i32 [ %sum_add, %for.body ], [ %sum_add.ldist.nondist, %for.body.ldist.nondist ]
+
+for.body:                                         ; preds = %for.body, %entry
+  %ind = phi i64 [ 0, %entry ], [ %add, %for.body ]
+  %sum = phi i32 [ 0, %entry ], [ %sum_add, %for.body ]
+
+  %arrayidxA = getelementptr inbounds i32, i32* %a, i64 %ind
+  %loadA = load i32, i32* %arrayidxA, align 4
+
+  %arrayidxB = getelementptr inbounds i32, i32* %b, i64 %ind
+  %loadB = load i32, i32* %arrayidxB, align 4
+
+  %mulA = mul i32 %loadB, %loadA
+
+  %add = add nuw nsw i64 %ind, 1
+  %arrayidxA_plus_4 = getelementptr inbounds i32, i32* %a, i64 %add
+  store i32 %mulA, i32* %arrayidxA_plus_4, align 4
+
+  %arrayidxC = getelementptr inbounds i32, i32* %c, i64 %ind
+  %loadC = load i32, i32* %arrayidxC, align 4
+
+  %sum_add = add nuw nsw i32 %sum, %loadC
+
+  %exitcond = icmp eq i64 %add, 20
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  store i32 %sum_add, i32* @SUM, align 4
+  ret void
+}
diff --git a/test/Transforms/LoopDistribute/program-order.ll b/test/Transforms/LoopDistribute/program-order.ll
new file mode 100644
index 000000000000..b534b79af71a
--- /dev/null
+++ b/test/Transforms/LoopDistribute/program-order.ll
@@ -0,0 +1,65 @@
+; RUN: opt -loop-distribute -S -verify-loop-info -verify-dom-info < %s \
+; RUN:   | FileCheck %s
+
+; Distributing this loop to avoid the dependence cycle would require to
+; reorder S1 and S2 to form the two partitions: {S2} | {S1, S3}.  The analysis
+; provided by LoopAccessAnalysis does not allow us to reorder memory
+; operations so make sure we bail on this loop.
+;
+;   for (i = 0; i < n; i++) {
+;     S1: d = D[i];
+;     S2: A[i + 1] = A[i] * B[i];
+;     S3: C[i] = d * E[i];
+;   }
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+define void @f(i32* noalias %a,
+               i32* noalias %b,
+               i32* noalias %c,
+               i32* noalias %d,
+               i32* noalias %e) {
+entry:
+  br label %for.body
+
+; CHECK: entry:
+; CHECK:    br label %for.body
+; CHECK: for.body:
+; CHECK:    br i1 %exitcond, label %for.end, label %for.body
+; CHECK: for.end:
+; CHECK:    ret void
+
+for.body:                                         ; preds = %for.body, %entry
+  %ind = phi i64 [ 0, %entry ], [ %add, %for.body ]
+
+  %arrayidxA = getelementptr inbounds i32, i32* %a, i64 %ind
+  %loadA = load i32, i32* %arrayidxA, align 4
+
+  %arrayidxB = getelementptr inbounds i32, i32* %b, i64 %ind
+  %loadB = load i32, i32* %arrayidxB, align 4
+
+  %mulA = mul i32 %loadB, %loadA
+
+  %arrayidxD = getelementptr inbounds i32, i32* %d, i64 %ind
+  %loadD = load i32, i32* %arrayidxD, align 4
+
+  %add = add nuw nsw i64 %ind, 1
+  %arrayidxA_plus_4 = getelementptr inbounds i32, i32* %a, i64 %add
+  store i32 %mulA, i32* %arrayidxA_plus_4, align 4
+
+  %arrayidxC = getelementptr inbounds i32, i32* %c, i64 %ind
+
+  %arrayidxE = getelementptr inbounds i32, i32* %e, i64 %ind
+  %loadE = load i32, i32* %arrayidxE, align 4
+
+  %mulC = mul i32 %loadD, %loadE
+
+  store i32 %mulC, i32* %arrayidxC, align 4
+
+  %exitcond = icmp eq i64 %add, 20
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
diff --git a/test/Transforms/LoopIdiom/basic-address-space.ll b/test/Transforms/LoopIdiom/basic-address-space.ll
index 697ab3726807..67cabf36eec7 100644
--- a/test/Transforms/LoopIdiom/basic-address-space.ll
+++ b/test/Transforms/LoopIdiom/basic-address-space.ll
@@ -22,7 +22,7 @@ for.body5:                                        ; preds = %for.body5, %bb.nph
   %j.02 = phi i16 [ 0, %bb.nph ], [ %inc, %for.body5 ]
   %mul = mul nsw i16 %i.04, 100
   %add = add nsw i16 %j.02, %mul
-  %arrayidx = getelementptr inbounds i8 addrspace(2)* %X, i16 %add
+  %arrayidx = getelementptr inbounds i8, i8 addrspace(2)* %X, i16 %add
   store i8 0, i8 addrspace(2)* %arrayidx, align 1
   %inc = add nsw i16 %j.02, 1
   %cmp4 = icmp eq i16 %inc, 100
@@ -45,7 +45,7 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %for.body ]
-  %arrayidx = getelementptr i32 addrspace(2)* %P, i64 %indvar
+  %arrayidx = getelementptr i32, i32 addrspace(2)* %P, i64 %indvar
   store i32 1, i32 addrspace(2)* %arrayidx, align 4
   %indvar.next = add i64 %indvar, 1
   %exitcond = icmp eq i64 %indvar.next, 10000
@@ -74,18 +74,18 @@ for.body:                                         ; preds = %for.inc, %for.body.
   %tmp5 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
   %add = add nsw i32 %tmp5, 4
   %idxprom = sext i32 %add to i64
-  %arrayidx = getelementptr inbounds [7 x i32] addrspace(2)* @g_50, i32 0, i64 %idxprom
-  %tmp2 = load i32 addrspace(2)* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [7 x i32], [7 x i32] addrspace(2)* @g_50, i32 0, i64 %idxprom
+  %tmp2 = load i32, i32 addrspace(2)* %arrayidx, align 4
   %add4 = add nsw i32 %tmp5, 5
   %idxprom5 = sext i32 %add4 to i64
-  %arrayidx6 = getelementptr inbounds [7 x i32] addrspace(2)* @g_50, i32 0, i64 %idxprom5
+  %arrayidx6 = getelementptr inbounds [7 x i32], [7 x i32] addrspace(2)* @g_50, i32 0, i64 %idxprom5
   store i32 %tmp2, i32 addrspace(2)* %arrayidx6, align 4
   %inc = add nsw i32 %tmp5, 1
   %cmp = icmp slt i32 %inc, 2
   br i1 %cmp, label %for.body, label %for.end
 
 for.end:                                          ; preds = %for.inc
-  %tmp8 = load i32 addrspace(2)* getelementptr inbounds ([7 x i32] addrspace(2)* @g_50, i32 0, i64 6), align 4
+  %tmp8 = load i32, i32 addrspace(2)* getelementptr inbounds ([7 x i32], [7 x i32] addrspace(2)* @g_50, i32 0, i64 6), align 4
   ret i32 %tmp8
 }
 
diff --git a/test/Transforms/LoopIdiom/basic.ll b/test/Transforms/LoopIdiom/basic.ll
index 835a9f695ca9..a8a2c8efa386 100644
--- a/test/Transforms/LoopIdiom/basic.ll
+++ b/test/Transforms/LoopIdiom/basic.ll
@@ -1,5 +1,12 @@
 ; RUN: opt -basicaa -loop-idiom < %s -S | FileCheck %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+
+; For @test11_pattern
+; CHECK: @.memset_pattern = private unnamed_addr constant [4 x i32] [i32 1, i32 1, i32 1, i32 1]
+
+; For @test13_pattern
+; CHECK: @.memset_pattern.1 = private unnamed_addr constant [2 x i32*] [i32* @G, i32* @G]
+
 target triple = "x86_64-apple-darwin10.0.0"
 
 define void @test1(i8* %Base, i64 %Size) nounwind ssp {
@@ -8,7 +15,7 @@ bb.nph:                                           ; preds = %entry
 
 for.body:                                         ; preds = %bb.nph, %for.body
   %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %for.body ]
-  %I.0.014 = getelementptr i8* %Base, i64 %indvar
+  %I.0.014 = getelementptr i8, i8* %Base, i64 %indvar
   store i8 0, i8* %I.0.014, align 1
   %indvar.next = add i64 %indvar, 1
   %exitcond = icmp eq i64 %indvar.next, %Size
@@ -29,7 +36,7 @@ bb.nph:                                           ; preds = %entry
 
 for.body:                                         ; preds = %bb.nph, %for.body
   %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %for.body.cont ]
-  %I.0.014 = getelementptr i8* %Base, i64 %indvar
+  %I.0.014 = getelementptr i8, i8* %Base, i64 %indvar
   store i8 0, i8* %I.0.014, align 1
   %indvar.next = add i64 %indvar, 1
   br label %for.body.cont
@@ -52,7 +59,7 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %i.011 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
-  %add.ptr.i = getelementptr i32* %Base, i64 %i.011
+  %add.ptr.i = getelementptr i32, i32* %Base, i64 %i.011
   store i32 16843009, i32* %add.ptr.i, align 4
   %inc = add nsw i64 %i.011, 1
   %exitcond = icmp eq i64 %inc, %Size
@@ -75,7 +82,7 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %i.011 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
-  %add.ptr.i = getelementptr i32* %Base, i64 %i.011
+  %add.ptr.i = getelementptr i32, i32* %Base, i64 %i.011
   store i32 16843009, i32* %add.ptr.i, align 4
   
   store i8 42, i8* %MayAlias
@@ -94,12 +101,12 @@ for.end:                                          ; preds = %entry
 ;; TODO: We should be able to promote this memset.  Not yet though.
 define void @test4(i8* %Base) nounwind ssp {
 bb.nph:                                           ; preds = %entry
-  %Base100 = getelementptr i8* %Base, i64 1000
+  %Base100 = getelementptr i8, i8* %Base, i64 1000
   br label %for.body
 
 for.body:                                         ; preds = %bb.nph, %for.body
   %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %for.body ]
-  %I.0.014 = getelementptr i8* %Base, i64 %indvar
+  %I.0.014 = getelementptr i8, i8* %Base, i64 %indvar
   store i8 0, i8* %I.0.014, align 1
   
   ;; Store beyond the range memset, should be safe to promote.
@@ -123,7 +130,7 @@ bb.nph:                                           ; preds = %entry
 
 for.body:                                         ; preds = %bb.nph, %for.body
   %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %for.body ]
-  %I.0.014 = getelementptr i8* %Base, i64 %indvar
+  %I.0.014 = getelementptr i8, i8* %Base, i64 %indvar
   
   %V = trunc i64 %indvar to i8
   store i8 %V, i8* %I.0.014, align 1
@@ -148,9 +155,9 @@ bb.nph:
 
 for.body:                                         ; preds = %bb.nph, %for.body
   %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %for.body ]
-  %I.0.014 = getelementptr i8* %Base, i64 %indvar
-  %DestI = getelementptr i8* %Dest, i64 %indvar
-  %V = load i8* %I.0.014, align 1
+  %I.0.014 = getelementptr i8, i8* %Base, i64 %indvar
+  %DestI = getelementptr i8, i8* %Dest, i64 %indvar
+  %V = load i8, i8* %I.0.014, align 1
   store i8 %V, i8* %DestI, align 1
   %indvar.next = add i64 %indvar, 1
   %exitcond = icmp eq i64 %indvar.next, %Size
@@ -175,7 +182,7 @@ for.body:                                         ; preds = %bb.nph, %for.body
   %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %for.body.cont ]
   br label %for.body.cont
 for.body.cont:
-  %I.0.014 = getelementptr i8* %Base, i64 %indvar
+  %I.0.014 = getelementptr i8, i8* %Base, i64 %indvar
   store i8 0, i8* %I.0.014, align 1
   %indvar.next = add i64 %indvar, 1
   %exitcond = icmp eq i64 %indvar.next, %Size
@@ -195,7 +202,7 @@ bb.nph:                                           ; preds = %entry
 
 for.body:                                         ; preds = %bb.nph, %for.body
   %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %for.body ]
-  %PI = getelementptr i64* %Ptr, i64 %indvar
+  %PI = getelementptr i64, i64* %Ptr, i64 %indvar
   store i64 0, i64 *%PI
   %indvar.next = add i64 %indvar, 1
   %exitcond = icmp eq i64 %indvar.next, 1
@@ -221,9 +228,9 @@ bb.nph:
 
 for.body:                                         ; preds = %bb.nph, %for.body
   %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %for.body ]
-  %I.0.014 = getelementptr i8* %Base, i64 %indvar
-  %DestI = getelementptr i8* %Dest, i64 %indvar
-  %V = load i8* %I.0.014, align 1
+  %I.0.014 = getelementptr i8, i8* %Base, i64 %indvar
+  %DestI = getelementptr i8, i8* %Dest, i64 %indvar
+  %V = load i8, i8* %I.0.014, align 1
   store i8 %V, i8* %DestI, align 1
 
   ;; This store can clobber the input.
@@ -254,7 +261,7 @@ for.body5:                                        ; preds = %for.body5, %bb.nph
   %mul = mul nsw i32 %i.04, 100
   %add = add nsw i32 %j.02, %mul
   %idxprom = sext i32 %add to i64
-  %arrayidx = getelementptr inbounds i8* %X, i64 %idxprom
+  %arrayidx = getelementptr inbounds i8, i8* %X, i64 %idxprom
   store i8 0, i8* %arrayidx, align 1
   %inc = add nsw i32 %j.02, 1
   %cmp4 = icmp eq i32 %inc, 100
@@ -283,7 +290,7 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %for.body ]
-  %arrayidx = getelementptr i32* %P, i64 %indvar
+  %arrayidx = getelementptr i32, i32* %P, i64 %indvar
   store i32 1, i32* %arrayidx, align 4
   %indvar.next = add i64 %indvar, 1
   %exitcond = icmp eq i64 %indvar.next, 10000
@@ -306,7 +313,7 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %for.body ]
-  %arrayidx = getelementptr i32** %P, i64 %indvar
+  %arrayidx = getelementptr i32*, i32** %P, i64 %indvar
   store i32* null, i32** %arrayidx, align 4
   %indvar.next = add i64 %indvar, 1
   %exitcond = icmp eq i64 %indvar.next, 10000
@@ -332,7 +339,7 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %for.body ]
-  %arrayidx = getelementptr i32** %P, i64 %indvar
+  %arrayidx = getelementptr i32*, i32** %P, i64 %indvar
   store i32* @G, i32** %arrayidx, align 4
   %indvar.next = add i64 %indvar, 1
   %exitcond = icmp eq i64 %indvar.next, 10000
@@ -362,18 +369,18 @@ for.body:                                         ; preds = %for.inc, %for.body.
   %tmp5 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
   %add = add nsw i32 %tmp5, 4
   %idxprom = sext i32 %add to i64
-  %arrayidx = getelementptr inbounds [7 x i32]* @g_50, i32 0, i64 %idxprom
-  %tmp2 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [7 x i32], [7 x i32]* @g_50, i32 0, i64 %idxprom
+  %tmp2 = load i32, i32* %arrayidx, align 4
   %add4 = add nsw i32 %tmp5, 5
   %idxprom5 = sext i32 %add4 to i64
-  %arrayidx6 = getelementptr inbounds [7 x i32]* @g_50, i32 0, i64 %idxprom5
+  %arrayidx6 = getelementptr inbounds [7 x i32], [7 x i32]* @g_50, i32 0, i64 %idxprom5
   store i32 %tmp2, i32* %arrayidx6, align 4
   %inc = add nsw i32 %tmp5, 1
   %cmp = icmp slt i32 %inc, 2
   br i1 %cmp, label %for.body, label %for.end
 
 for.end:                                          ; preds = %for.inc
-  %tmp8 = load i32* getelementptr inbounds ([7 x i32]* @g_50, i32 0, i64 6), align 4
+  %tmp8 = load i32, i32* getelementptr inbounds ([7 x i32], [7 x i32]* @g_50, i32 0, i64 6), align 4
   ret i32 %tmp8
 ; CHECK-LABEL: @test14(
 ; CHECK: for.body:
@@ -393,7 +400,7 @@ define void @PR14241(i32* %s, i64 %size) {
 
 entry:
   %end.idx = add i64 %size, -1
-  %end.ptr = getelementptr inbounds i32* %s, i64 %end.idx
+  %end.ptr = getelementptr inbounds i32, i32* %s, i64 %end.idx
   br label %while.body
 ; CHECK-NOT: memcpy
 ;
@@ -403,13 +410,13 @@ entry:
 
 while.body:
   %phi.ptr = phi i32* [ %s, %entry ], [ %next.ptr, %while.body ]
-  %src.ptr = getelementptr inbounds i32* %phi.ptr, i64 1
-  %val = load i32* %src.ptr, align 4
+  %src.ptr = getelementptr inbounds i32, i32* %phi.ptr, i64 1
+  %val = load i32, i32* %src.ptr, align 4
 ; CHECK: load
-  %dst.ptr = getelementptr inbounds i32* %phi.ptr, i64 0
+  %dst.ptr = getelementptr inbounds i32, i32* %phi.ptr, i64 0
   store i32 %val, i32* %dst.ptr, align 4
 ; CHECK: store
-  %next.ptr = getelementptr inbounds i32* %phi.ptr, i64 1
+  %next.ptr = getelementptr inbounds i32, i32* %phi.ptr, i64 1
   %cmp = icmp eq i32* %next.ptr, %end.ptr
   br i1 %cmp, label %exit, label %while.body
 
diff --git a/test/Transforms/LoopIdiom/crash.ll b/test/Transforms/LoopIdiom/crash.ll
index 969adbcd7635..c964aacd00c2 100644
--- a/test/Transforms/LoopIdiom/crash.ll
+++ b/test/Transforms/LoopIdiom/crash.ll
@@ -8,13 +8,13 @@ define void @test1(i64* %iwork, i64 %x)  {
 bb0:
   %mul116 = mul nsw i64 %x, %x
   %incdec.ptr6.sum175 = add i64 42, %x
-  %arrayidx135 = getelementptr inbounds i64* %iwork, i64 %incdec.ptr6.sum175
+  %arrayidx135 = getelementptr inbounds i64, i64* %iwork, i64 %incdec.ptr6.sum175
   br label %bb1
 bb1:
   %storemerge4226 = phi i64 [ 0, %bb0 ], [ %inc139, %bb1 ]
   store i64 1, i64* %arrayidx135, align 8
   %incdec.ptr6.sum176 = add i64 %mul116, %storemerge4226
-  %arrayidx137 = getelementptr inbounds i64* %iwork, i64 %incdec.ptr6.sum176
+  %arrayidx137 = getelementptr inbounds i64, i64* %iwork, i64 %incdec.ptr6.sum176
   store i64 1, i64* %arrayidx137, align 8
   %inc139 = add nsw i64 %storemerge4226, 1
   %cmp131 = icmp sgt i64 %storemerge4226, 42
diff --git a/test/Transforms/LoopIdiom/debug-line.ll b/test/Transforms/LoopIdiom/debug-line.ll
index 863df3c72d50..bcd862d7a729 100644
--- a/test/Transforms/LoopIdiom/debug-line.ll
+++ b/test/Transforms/LoopIdiom/debug-line.ll
@@ -5,13 +5,13 @@ target triple = "x86_64-apple-darwin10.0.0"
 
 define void @foo(double* nocapture %a) nounwind ssp {
 entry:
-  tail call void @llvm.dbg.value(metadata double* %a, i64 0, metadata !5, metadata !{}), !dbg !8
-  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !10, metadata !{}), !dbg !14
+  tail call void @llvm.dbg.value(metadata double* %a, i64 0, metadata !5, metadata !DIExpression()), !dbg !8
+  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !10, metadata !DIExpression()), !dbg !14
   br label %for.body
 
 for.body:                                         ; preds = %entry, %for.body
   %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %for.body ]
-  %arrayidx = getelementptr double* %a, i64 %indvar
+  %arrayidx = getelementptr double, double* %a, i64 %indvar
 ; CHECK: call void @llvm.memset{{.+}} !dbg 
   store double 0.000000e+00, double* %arrayidx, align 8, !dbg !15
   %indvar.next = add i64 %indvar, 1
@@ -19,7 +19,7 @@ for.body:                                         ; preds = %entry, %for.body
   br i1 %exitcond, label %for.body, label %for.end, !dbg !14
 
 for.end:                                          ; preds = %for.body
-  tail call void @llvm.dbg.value(metadata !{null}, i64 0, metadata !10, metadata !{}), !dbg !16
+  tail call void @llvm.dbg.value(metadata !{null}, i64 0, metadata !10, metadata !DIExpression()), !dbg !16
   ret void, !dbg !17
 }
 
@@ -30,23 +30,23 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.module.flags = !{!19}
 !llvm.dbg.sp = !{!0}
 
-!0 = !{!"0x2e\00foo\00foo\00\002\000\001\000\006\00256\000\000", !18, !1, !3, null, void (double*)* @foo, null, null, null} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 0] [foo]
-!1 = !{!"0x29", !18} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 2.9 (trunk 127165:127174)\001\00\000\00\000", !18, !9, !9, null, null, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !18, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "foo", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !18, scope: !1, type: !3, function: void (double*)* @foo)
+!1 = !DIFile(filename: "li.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 2.9 (trunk 127165:127174)", isOptimized: true, emissionKind: 0, file: !18, enums: !9, retainedTypes: !9)
+!3 = !DISubroutineType(types: !4)
 !4 = !{null}
-!5 = !{!"0x101\00a\0016777218\000", !0, !1, !6} ; [ DW_TAG_arg_variable ]
-!6 = !{!"0xf\00\000\0064\0064\000\000", null, !2, !7} ; [ DW_TAG_pointer_type ]
-!7 = !{!"0x24\00double\000\0064\0064\000\000\004", null, !2} ; [ DW_TAG_base_type ]
-!8 = !MDLocation(line: 2, column: 18, scope: !0)
-!9 = !{i32 0}
-!10 = !{!"0x100\00i\003\000", !11, !1, !13} ; [ DW_TAG_auto_variable ]
-!11 = !{!"0xb\003\003\001", !18, !12} ; [ DW_TAG_lexical_block ]
-!12 = !{!"0xb\002\0021\000", !18, !0} ; [ DW_TAG_lexical_block ]
-!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ]
-!14 = !MDLocation(line: 3, column: 3, scope: !12)
-!15 = !MDLocation(line: 4, column: 5, scope: !11)
-!16 = !MDLocation(line: 3, column: 29, scope: !11)
-!17 = !MDLocation(line: 5, column: 1, scope: !12)
-!18 = !{!"li.c", !"/private/tmp"}
-!19 = !{i32 1, !"Debug Info Version", i32 2}
+!5 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 2, arg: 1, scope: !0, file: !1, type: !6)
+!6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, scope: !2, baseType: !7)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 64, encoding: DW_ATE_float)
+!8 = !DILocation(line: 2, column: 18, scope: !0)
+!9 = !{}
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 3, scope: !11, file: !1, type: !13)
+!11 = distinct !DILexicalBlock(line: 3, column: 3, file: !18, scope: !12)
+!12 = distinct !DILexicalBlock(line: 2, column: 21, file: !18, scope: !0)
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!14 = !DILocation(line: 3, column: 3, scope: !12)
+!15 = !DILocation(line: 4, column: 5, scope: !11)
+!16 = !DILocation(line: 3, column: 29, scope: !11)
+!17 = !DILocation(line: 5, column: 1, scope: !12)
+!18 = !DIFile(filename: "li.c", directory: "/private/tmp")
+!19 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/LoopIdiom/memset_noidiom.ll b/test/Transforms/LoopIdiom/memset_noidiom.ll
index f2b55aed5467..f039d99ca49a 100644
--- a/test/Transforms/LoopIdiom/memset_noidiom.ll
+++ b/test/Transforms/LoopIdiom/memset_noidiom.ll
@@ -15,7 +15,7 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %indvar = phi i64 [ 0, %for.body.lr.ph ], [ %indvar.next, %for.body ]
-  %p.02 = getelementptr i8* %b, i64 %indvar
+  %p.02 = getelementptr i8, i8* %b, i64 %indvar
   store i8 %conv6, i8* %p.02, align 1
   %indvar.next = add i64 %indvar, 1
   %exitcond = icmp ne i64 %indvar.next, %len
diff --git a/test/Transforms/LoopIdiom/non-canonical-loop.ll b/test/Transforms/LoopIdiom/non-canonical-loop.ll
index a6a4f9227f9a..77c818f834ec 100644
--- a/test/Transforms/LoopIdiom/non-canonical-loop.ll
+++ b/test/Transforms/LoopIdiom/non-canonical-loop.ll
@@ -20,7 +20,7 @@ start.exit:                       ; preds = %entry
 
 for.bodyprime:                                    ; preds = %for.bodyprime, %start.exit
   %i.057375 = phi i32 [ 0, %start.exit ], [ %1, %for.bodyprime ]
-  %arrayidx8prime = getelementptr inbounds i32* %currMB, i32 %i.057375
+  %arrayidx8prime = getelementptr inbounds i32, i32* %currMB, i32 %i.057375
   store i32 0, i32* %arrayidx8prime, align 4
   %1 = add i32 %i.057375, 1
   %cmp5prime = icmp slt i32 %1, 4
diff --git a/test/Transforms/LoopIdiom/scev-invalidation.ll b/test/Transforms/LoopIdiom/scev-invalidation.ll
index a244d9a280b9..2fe8a3023c4c 100644
--- a/test/Transforms/LoopIdiom/scev-invalidation.ll
+++ b/test/Transforms/LoopIdiom/scev-invalidation.ll
@@ -11,7 +11,7 @@ for.cond:                                         ; preds = %for.inc, %entry
   %backslashes.0 = phi i32 [ undef, %entry ], [ %backslashes.2, %for.inc ]
   %p.0 = phi i8* [ undef, %entry ], [ %incdec.ptr3, %for.inc ]
   %q.0 = phi i8* [ undef, %entry ], [ %q.2, %for.inc ]
-  %0 = load i8* %p.0, align 1
+  %0 = load i8, i8* %p.0, align 1
   switch i8 %0, label %while.cond.preheader [
     i8 0, label %for.cond4.preheader
     i8 92, label %for.inc
@@ -36,7 +36,7 @@ for.body6.lr.ph:                                  ; preds = %for.cond4.preheader
 while.body:                                       ; preds = %while.body.lr.ph, %while.body
   %q.112 = phi i8* [ %q.0, %while.body.lr.ph ], [ %incdec.ptr, %while.body ]
   %backslashes.111 = phi i32 [ %backslashes.0, %while.body.lr.ph ], [ %dec, %while.body ]
-  %incdec.ptr = getelementptr inbounds i8* %q.112, i64 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %q.112, i64 1
   store i8 92, i8* %incdec.ptr, align 1
   %dec = add nsw i32 %backslashes.111, -1
   %tobool2 = icmp eq i32 %dec, 0
@@ -44,7 +44,7 @@ while.body:                                       ; preds = %while.body.lr.ph, %
 
 while.cond.for.inc.loopexit_crit_edge:            ; preds = %while.body
   %scevgep.sum = add i64 %2, 1
-  %scevgep13 = getelementptr i8* %q.0, i64 %scevgep.sum
+  %scevgep13 = getelementptr i8, i8* %q.0, i64 %scevgep.sum
   br label %for.inc.loopexit
 
 for.inc.loopexit:                                 ; preds = %while.cond.for.inc.loopexit_crit_edge, %while.cond.preheader
@@ -54,13 +54,13 @@ for.inc.loopexit:                                 ; preds = %while.cond.for.inc.
 for.inc:                                          ; preds = %for.inc.loopexit, %for.cond
   %backslashes.2 = phi i32 [ %backslashes.0, %for.cond ], [ 0, %for.inc.loopexit ]
   %q.2 = phi i8* [ %q.0, %for.cond ], [ %q.1.lcssa, %for.inc.loopexit ]
-  %incdec.ptr3 = getelementptr inbounds i8* %p.0, i64 1
+  %incdec.ptr3 = getelementptr inbounds i8, i8* %p.0, i64 1
   br label %for.cond
 
 for.body6:                                        ; preds = %for.body6.lr.ph, %for.body6
   %q.39 = phi i8* [ %q.0, %for.body6.lr.ph ], [ %incdec.ptr7, %for.body6 ]
   %backslashes.38 = phi i32 [ %backslashes.0, %for.body6.lr.ph ], [ %dec9, %for.body6 ]
-  %incdec.ptr7 = getelementptr inbounds i8* %q.39, i64 1
+  %incdec.ptr7 = getelementptr inbounds i8, i8* %q.39, i64 1
   store i8 92, i8* %incdec.ptr7, align 1
   %dec9 = add nsw i32 %backslashes.38, -1
   %tobool5 = icmp eq i32 %dec9, 0
diff --git a/test/Transforms/LoopInterchange/currentLimitation.ll b/test/Transforms/LoopInterchange/currentLimitation.ll
new file mode 100644
index 000000000000..8045dd87a75a
--- /dev/null
+++ b/test/Transforms/LoopInterchange/currentLimitation.ll
@@ -0,0 +1,58 @@
+; RUN: opt < %s -basicaa -loop-interchange -S | FileCheck %s
+;; These are test that fail to interchange due to current limitation. This will go off once we extend the loop interchange pass.
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+ 
+@A = common global [100 x [100 x i32]] zeroinitializer
+@B = common global [100 x [100 x [100 x i32]]] zeroinitializer
+ 
+;;--------------------------------------Test case 01------------------------------------
+;; [FIXME] This loop though valid is currently not interchanged due to the limitation that we cannot split the inner loop latch due to multiple use of inner induction
+;; variable.(used to increment the loop counter and to access A[j+1][i+1]
+;;  for(int i=0;i<N-1;i++)
+;;    for(int j=1;j<N-1;j++)
+;;      A[j+1][i+1] = A[j+1][i+1] + k;
+
+define void @interchange_01(i32 %k, i32 %N) {
+ entry:
+   %sub = add nsw i32 %N, -1
+   %cmp26 = icmp sgt i32 %N, 1
+   br i1 %cmp26, label %for.cond1.preheader.lr.ph, label %for.end17
+ 
+ for.cond1.preheader.lr.ph:
+   %cmp324 = icmp sgt i32 %sub, 1
+   %0 = add i32 %N, -2
+   %1 = sext i32 %sub to i64
+   br label %for.cond1.preheader
+ 
+ for.cond.loopexit:
+   %cmp = icmp slt i64 %indvars.iv.next29, %1
+   br i1 %cmp, label %for.cond1.preheader, label %for.end17
+ 
+ for.cond1.preheader:
+   %indvars.iv28 = phi i64 [ 0, %for.cond1.preheader.lr.ph ], [ %indvars.iv.next29, %for.cond.loopexit ]
+   %indvars.iv.next29 = add nuw nsw i64 %indvars.iv28, 1
+   br i1 %cmp324, label %for.body4, label %for.cond.loopexit
+ 
+ for.body4:
+   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body4 ], [ 1, %for.cond1.preheader ]
+   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+   %arrayidx7 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv.next, i64 %indvars.iv.next29
+   %2 = load i32, i32* %arrayidx7
+   %add8 = add nsw i32 %2, %k
+   store i32 %add8, i32* %arrayidx7
+   %lftr.wideiv = trunc i64 %indvars.iv to i32
+   %exitcond = icmp eq i32 %lftr.wideiv, %0
+   br i1 %exitcond, label %for.cond.loopexit, label %for.body4
+ 
+ for.end17: 
+   ret void
+}
+;; Inner loop not split so it is not interchanged.
+; CHECK-LABEL: @interchange_01
+; CHECK:      for.body4:
+; CHECK-NEXT:   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body4 ], [ 1, %for.body4.preheader ]
+; CHECK-NEXT:   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+; CHECK-NEXT:   %arrayidx7 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv.next, i64 %indvars.iv.next29
+ 
diff --git a/test/Transforms/LoopInterchange/interchange.ll b/test/Transforms/LoopInterchange/interchange.ll
new file mode 100644
index 000000000000..39941660e601
--- /dev/null
+++ b/test/Transforms/LoopInterchange/interchange.ll
@@ -0,0 +1,557 @@
+; RUN: opt < %s -basicaa -loop-interchange -S | FileCheck %s
+;; We test the complete .ll for adjustment in outer loop header/latch and inner loop header/latch.
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+@A = common global [100 x [100 x i32]] zeroinitializer
+@B = common global [100 x i32] zeroinitializer
+@C = common global [100 x [100 x i32]] zeroinitializer
+@D = common global [100 x [100 x [100 x i32]]] zeroinitializer
+
+declare void @foo(...)
+
+;;--------------------------------------Test case 01------------------------------------
+;;  for(int i=0;i<N;i++)
+;;    for(int j=1;j<N;j++)
+;;      A[j][i] = A[j][i]+k;
+
+define void @interchange_01(i32 %k, i32 %N) {
+entry:
+  %cmp21 = icmp sgt i32 %N, 0
+  br i1 %cmp21, label %for.cond1.preheader.lr.ph, label %for.end12
+
+for.cond1.preheader.lr.ph:
+  %cmp219 = icmp sgt i32 %N, 1
+  %0 = add i32 %N, -1
+  br label %for.cond1.preheader
+
+for.cond1.preheader: 
+  %indvars.iv23 = phi i64 [ 0, %for.cond1.preheader.lr.ph ], [ %indvars.iv.next24, %for.inc10 ]
+  br i1 %cmp219, label %for.body3, label %for.inc10
+
+for.body3:
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3 ], [ 1, %for.cond1.preheader ]
+  %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv, i64 %indvars.iv23
+  %1 = load i32, i32* %arrayidx5
+  %add = add nsw i32 %1, %k
+  store i32 %add, i32* %arrayidx5
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %0
+  br i1 %exitcond, label %for.inc10, label %for.body3
+
+for.inc10:
+  %indvars.iv.next24 = add nuw nsw i64 %indvars.iv23, 1
+  %lftr.wideiv25 = trunc i64 %indvars.iv23 to i32
+  %exitcond26 = icmp eq i32 %lftr.wideiv25, %0
+  br i1 %exitcond26, label %for.end12, label %for.cond1.preheader
+
+for.end12:
+  ret void
+}
+
+; CHECK-LABEL: @interchange_01
+; CHECK: entry:
+; CHECK:   %cmp21 = icmp sgt i32 %N, 0
+; CHECK:   br i1 %cmp21, label %for.body3.preheader, label %for.end12
+; CHECK: for.cond1.preheader.lr.ph:                        
+; CHECK:   br label %for.cond1.preheader
+; CHECK: for.cond1.preheader:                              
+; CHECK:   %indvars.iv23 = phi i64 [ 0, %for.cond1.preheader.lr.ph ], [ %indvars.iv.next24, %for.inc10 ]
+; CHECK:   br i1 %cmp219, label %for.body3.split1, label %for.end12.loopexit
+; CHECK: for.body3.preheader:                              
+; CHECK:   %cmp219 = icmp sgt i32 %N, 1
+; CHECK:   %0 = add i32 %N, -1
+; CHECK:   br label %for.body3
+; CHECK: for.body3:                                        
+; CHECK:   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3.split ], [ 1, %for.body3.preheader ]
+; CHECK:   br label %for.cond1.preheader.lr.ph
+; CHECK: for.body3.split1:                                 
+; CHECK:   %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv, i64 %indvars.iv23
+; CHECK:   %1 = load i32, i32* %arrayidx5
+; CHECK:   %add = add nsw i32 %1, %k
+; CHECK:   store i32 %add, i32* %arrayidx5
+; CHECK:   br label %for.inc10.loopexit
+; CHECK: for.body3.split:                                  
+; CHECK:   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+; CHECK:   %lftr.wideiv = trunc i64 %indvars.iv to i32
+; CHECK:   %exitcond = icmp eq i32 %lftr.wideiv, %0
+; CHECK:   br i1 %exitcond, label %for.end12.loopexit, label %for.body3
+; CHECK: for.inc10.loopexit:                               
+; CHECK:   br label %for.inc10
+; CHECK: for.inc10:                                        
+; CHECK:   %indvars.iv.next24 = add nuw nsw i64 %indvars.iv23, 1
+; CHECK:   %lftr.wideiv25 = trunc i64 %indvars.iv23 to i32
+; CHECK:   %exitcond26 = icmp eq i32 %lftr.wideiv25, %0
+; CHECK:   br i1 %exitcond26, label %for.body3.split, label %for.cond1.preheader
+; CHECK: for.end12.loopexit:                               
+; CHECK:   br label %for.end12
+; CHECK: for.end12:                                        
+; CHECK:   ret void
+
+;;--------------------------------------Test case 02-------------------------------------
+
+;; for(int i=0;i<100;i++)
+;;   for(int j=100;j>=0;j--)
+;;     A[j][i] = A[j][i]+k;
+
+define void @interchange_02(i32 %k) {
+entry:
+  br label %for.cond1.preheader
+
+for.cond1.preheader:
+  %indvars.iv19 = phi i64 [ 0, %entry ], [ %indvars.iv.next20, %for.inc10 ]
+  br label %for.body3
+
+for.body3:
+  %indvars.iv = phi i64 [ 100, %for.cond1.preheader ], [ %indvars.iv.next, %for.body3 ]
+  %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv, i64 %indvars.iv19
+  %0 = load i32, i32* %arrayidx5
+  %add = add nsw i32 %0, %k
+  store i32 %add, i32* %arrayidx5
+  %indvars.iv.next = add nsw i64 %indvars.iv, -1
+  %cmp2 = icmp sgt i64 %indvars.iv, 0
+  br i1 %cmp2, label %for.body3, label %for.inc10
+
+for.inc10:
+  %indvars.iv.next20 = add nuw nsw i64 %indvars.iv19, 1
+  %exitcond = icmp eq i64 %indvars.iv.next20, 100
+  br i1 %exitcond, label %for.end11, label %for.cond1.preheader
+
+for.end11:
+  ret void
+}
+
+; CHECK-LABEL: @interchange_02
+; CHECK: entry:
+; CHECK:   br label %for.body3.preheader
+; CHECK: for.cond1.preheader.preheader: 
+; CHECK:   br label %for.cond1.preheader
+; CHECK: for.cond1.preheader:  
+; CHECK:   %indvars.iv19 = phi i64 [ %indvars.iv.next20, %for.inc10 ], [ 0, %for.cond1.preheader.preheader ]
+; CHECK:   br label %for.body3.split1
+; CHECK: for.body3.preheader: 
+; CHECK:   br label %for.body3
+; CHECK: for.body3: 
+; CHECK:   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3.split ], [ 100, %for.body3.preheader ]
+; CHECK:   br label %for.cond1.preheader.preheader
+; CHECK: for.body3.split1:                                 ; preds = %for.cond1.preheader
+; CHECK:   %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv, i64 %indvars.iv19
+; CHECK:   %0 = load i32, i32* %arrayidx5
+; CHECK:   %add = add nsw i32 %0, %k
+; CHECK:   store i32 %add, i32* %arrayidx5
+; CHECK:   br label %for.inc10
+; CHECK: for.body3.split:
+; CHECK:   %indvars.iv.next = add nsw i64 %indvars.iv, -1
+; CHECK:   %cmp2 = icmp sgt i64 %indvars.iv, 0
+; CHECK:   br i1 %cmp2, label %for.body3, label %for.end11
+; CHECK: for.inc10:
+; CHECK:   %indvars.iv.next20 = add nuw nsw i64 %indvars.iv19, 1
+; CHECK:   %exitcond = icmp eq i64 %indvars.iv.next20, 100
+; CHECK:   br i1 %exitcond, label %for.body3.split, label %for.cond1.preheader
+; CHECK: for.end11: 
+; CHECK:   ret void
+
+;;--------------------------------------Test case 03-------------------------------------
+;; Loops should not be interchanged in this case as it is not profitable.
+;;  for(int i=0;i<100;i++)
+;;    for(int j=0;j<100;j++)
+;;      A[i][j] = A[i][j]+k;
+
+define void @interchange_03(i32 %k) {
+entry:
+  br label %for.cond1.preheader
+
+for.cond1.preheader:
+  %indvars.iv21 = phi i64 [ 0, %entry ], [ %indvars.iv.next22, %for.inc10 ]
+  br label %for.body3
+
+for.body3:
+  %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.body3 ]
+  %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv21, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx5
+  %add = add nsw i32 %0, %k
+  store i32 %add, i32* %arrayidx5
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond = icmp eq i64 %indvars.iv.next, 100
+  br i1 %exitcond, label %for.inc10, label %for.body3
+
+for.inc10:
+  %indvars.iv.next22 = add nuw nsw i64 %indvars.iv21, 1
+  %exitcond23 = icmp eq i64 %indvars.iv.next22, 100
+  br i1 %exitcond23, label %for.end12, label %for.cond1.preheader
+
+for.end12:
+  ret void
+}
+
+; CHECK-LABEL: @interchange_03
+; CHECK: entry:
+; CHECK:   br label %for.cond1.preheader.preheader
+; CHECK: for.cond1.preheader.preheader:                    ; preds = %entry
+; CHECK:   br label %for.cond1.preheader
+; CHECK: for.cond1.preheader:                              ; preds = %for.cond1.preheader.preheader, %for.inc10
+; CHECK:   %indvars.iv21 = phi i64 [ %indvars.iv.next22, %for.inc10 ], [ 0, %for.cond1.preheader.preheader ]
+; CHECK:  br label %for.body3.preheader
+; CHECK: for.body3.preheader:                              ; preds = %for.cond1.preheader
+; CHECK:   br label %for.body3
+; CHECK: for.body3:                                        ; preds = %for.body3.preheader, %for.body3
+; CHECK:   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3 ], [ 0, %for.body3.preheader ]
+; CHECK:   %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv21, i64 %indvars.iv
+; CHECK:   %0 = load i32, i32* %arrayidx5
+; CHECK:   %add = add nsw i32 %0, %k
+; CHECK:   store i32 %add, i32* %arrayidx5
+; CHECK:   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+; CHECK:   %exitcond = icmp eq i64 %indvars.iv.next, 100
+; CHECK:   br i1 %exitcond, label %for.inc10, label %for.body3
+; CHECK: for.inc10:                                        ; preds = %for.body3
+; CHECK:   %indvars.iv.next22 = add nuw nsw i64 %indvars.iv21, 1
+; CHECK:   %exitcond23 = icmp eq i64 %indvars.iv.next22, 100
+; CHECK:   br i1 %exitcond23, label %for.end12, label %for.cond1.preheader
+; CHECK: for.end12:                                        ; preds = %for.inc10
+; CHECK:   ret void
+
+
+;;--------------------------------------Test case 04-------------------------------------
+;; Loops should not be interchanged in this case as it is not legal due to dependency.
+;;  for(int j=0;j<99;j++)
+;;   for(int i=0;i<99;i++)
+;;       A[j][i+1] = A[j+1][i]+k;
+
+define void @interchange_04(i32 %k){
+entry:
+  br label %for.cond1.preheader
+
+for.cond1.preheader:
+  %indvars.iv23 = phi i64 [ 0, %entry ], [ %indvars.iv.next24, %for.inc12 ]
+  %indvars.iv.next24 = add nuw nsw i64 %indvars.iv23, 1
+  br label %for.body3
+
+for.body3:
+  %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.body3 ]
+  %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv.next24, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx5
+  %add6 = add nsw i32 %0, %k
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %arrayidx11 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv23, i64 %indvars.iv.next
+  store i32 %add6, i32* %arrayidx11
+  %exitcond = icmp eq i64 %indvars.iv.next, 99
+  br i1 %exitcond, label %for.inc12, label %for.body3
+
+for.inc12:
+  %exitcond25 = icmp eq i64 %indvars.iv.next24, 99
+  br i1 %exitcond25, label %for.end14, label %for.cond1.preheader
+
+for.end14:
+  ret void
+}
+
+; CHECK-LABEL: @interchange_04
+; CHECK: entry:
+; CHECK:   br label %for.cond1.preheader
+; CHECK: for.cond1.preheader:                              ; preds = %for.inc12, %entry
+; CHECK:   %indvars.iv23 = phi i64 [ 0, %entry ], [ %indvars.iv.next24, %for.inc12 ]
+; CHECK:   %indvars.iv.next24 = add nuw nsw i64 %indvars.iv23, 1
+; CHECK:   br label %for.body3
+; CHECK: for.body3:                                        ; preds = %for.body3, %for.cond1.preheader
+; CHECK:   %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.body3 ]
+; CHECK:   %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv.next24, i64 %indvars.iv
+; CHECK:   %0 = load i32, i32* %arrayidx5
+; CHECK:   %add6 = add nsw i32 %0, %k
+; CHECK:   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+; CHECK:   %arrayidx11 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv23, i64 %indvars.iv.next
+; CHECK:   store i32 %add6, i32* %arrayidx11
+; CHECK:   %exitcond = icmp eq i64 %indvars.iv.next, 99
+; CHECK:   br i1 %exitcond, label %for.inc12, label %for.body3
+; CHECK: for.inc12:                                        ; preds = %for.body3
+; CHECK:   %exitcond25 = icmp eq i64 %indvars.iv.next24, 99
+; CHECK:   br i1 %exitcond25, label %for.end14, label %for.cond1.preheader
+; CHECK: for.end14:                                        ; preds = %for.inc12
+; CHECK:   ret void
+
+
+
+;;--------------------------------------Test case 05-------------------------------------
+;; Loops not tightly nested are not interchanged
+;;  for(int j=0;j<N;j++) {
+;;    B[j] = j+k;
+;;    for(int i=0;i<N;i++)
+;;      A[j][i] = A[j][i]+B[j];
+;;  }
+
+define void @interchange_05(i32 %k, i32 %N){
+entry:
+  %cmp30 = icmp sgt i32 %N, 0
+  br i1 %cmp30, label %for.body.lr.ph, label %for.end17
+
+for.body.lr.ph:
+  %0 = add i32 %N, -1
+  %1 = zext i32 %k to i64
+  br label %for.body
+
+for.body:
+  %indvars.iv32 = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next33, %for.inc15 ]
+  %2 = add nsw i64 %indvars.iv32, %1
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* @B, i64 0, i64 %indvars.iv32
+  %3 = trunc i64 %2 to i32
+  store i32 %3, i32* %arrayidx
+  br label %for.body3
+
+for.body3:
+  %indvars.iv = phi i64 [ 0, %for.body ], [ %indvars.iv.next, %for.body3 ]
+  %arrayidx7 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv32, i64 %indvars.iv
+  %4 = load i32, i32* %arrayidx7
+  %add10 = add nsw i32 %3, %4
+  store i32 %add10, i32* %arrayidx7
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %0
+  br i1 %exitcond, label %for.inc15, label %for.body3
+
+for.inc15:
+  %indvars.iv.next33 = add nuw nsw i64 %indvars.iv32, 1
+  %lftr.wideiv35 = trunc i64 %indvars.iv32 to i32
+  %exitcond36 = icmp eq i32 %lftr.wideiv35, %0
+  br i1 %exitcond36, label %for.end17, label %for.body
+
+for.end17:
+  ret void
+}
+
+; CHECK-LABEL: @interchange_05
+; CHECK: entry:
+; CHECK: %cmp30 = icmp sgt i32 %N, 0
+; CHECK: br i1 %cmp30, label %for.body.lr.ph, label %for.end17
+; CHECK: for.body.lr.ph:
+; CHECK: %0 = add i32 %N, -1
+; CHECK: %1 = zext i32 %k to i64
+; CHECK: br label %for.body
+; CHECK: for.body:
+; CHECK: %indvars.iv32 = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next33, %for.inc15 ]
+; CHECK: %2 = add nsw i64 %indvars.iv32, %1
+; CHECK: %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* @B, i64 0, i64 %indvars.iv32
+; CHECK: %3 = trunc i64 %2 to i32
+; CHECK: store i32 %3, i32* %arrayidx
+; CHECK: br label %for.body3.preheader
+; CHECK: for.body3.preheader:
+; CHECK: br label %for.body3
+; CHECK: for.body3:
+; CHECK: %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3 ], [ 0, %for.body3.preheader ]
+; CHECK: %arrayidx7 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv32, i64 %indvars.iv
+; CHECK: %4 = load i32, i32* %arrayidx7
+; CHECK: %add10 = add nsw i32 %3, %4
+; CHECK: store i32 %add10, i32* %arrayidx7
+; CHECK: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+; CHECK: %lftr.wideiv = trunc i64 %indvars.iv to i32
+; CHECK: %exitcond = icmp eq i32 %lftr.wideiv, %0
+; CHECK: br i1 %exitcond, label %for.inc15, label %for.body3
+; CHECK: for.inc15:
+; CHECK: %indvars.iv.next33 = add nuw nsw i64 %indvars.iv32, 1
+; CHECK: %lftr.wideiv35 = trunc i64 %indvars.iv32 to i32
+; CHECK: %exitcond36 = icmp eq i32 %lftr.wideiv35, %0
+; CHECK: br i1 %exitcond36, label %for.end17.loopexit, label %for.body
+; CHECK: for.end17.loopexit:
+; CHECK: br label %for.end17
+; CHECK: for.end17:
+; CHECK: ret void
+
+
+;;--------------------------------------Test case 06-------------------------------------
+;; Loops not tightly nested are not interchanged
+;;  for(int j=0;j<N;j++) {
+;;    foo();
+;;    for(int i=2;i<N;i++)
+;;      A[j][i] = A[j][i]+k;
+;;  }
+
+define void @interchange_06(i32 %k, i32 %N) {
+entry:
+  %cmp22 = icmp sgt i32 %N, 0
+  br i1 %cmp22, label %for.body.lr.ph, label %for.end12
+
+for.body.lr.ph:
+  %0 = add i32 %N, -1
+  br label %for.body
+
+for.body:
+  %indvars.iv24 = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next25, %for.inc10 ]
+  tail call void (...) @foo()
+  br label %for.body3
+
+for.body3:
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3 ], [ 2, %for.body ]
+  %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv24, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx5
+  %add = add nsw i32 %1, %k
+  store i32 %add, i32* %arrayidx5
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %0
+  br i1 %exitcond, label %for.inc10, label %for.body3
+
+for.inc10:
+  %indvars.iv.next25 = add nuw nsw i64 %indvars.iv24, 1
+  %lftr.wideiv26 = trunc i64 %indvars.iv24 to i32
+  %exitcond27 = icmp eq i32 %lftr.wideiv26, %0
+  br i1 %exitcond27, label %for.end12, label %for.body
+
+for.end12:
+  ret void
+}
+;; Here we are checking if the inner phi is not split then we have not interchanged.
+; CHECK-LABEL: @interchange_06
+; CHECK:  phi i64 [ %indvars.iv.next, %for.body3 ], [ 2, %for.body3.preheader ]
+; CHECK-NEXT: getelementptr
+; CHECK-NEXT: %1 = load
+
+;;--------------------------------------Test case 07-------------------------------------
+;; FIXME:
+;; Test for interchange when we have an lcssa phi. This should ideally be interchanged but it is currently not supported.
+;;     for(gi=1;gi<N;gi++)
+;;       for(gj=1;gj<M;gj++)
+;;         A[gj][gi] = A[gj - 1][gi] + C[gj][gi];
+
+@gi = common global i32 0
+@gj = common global i32 0
+
+define void @interchange_07(i32 %N, i32 %M){
+entry:
+  store i32 1, i32* @gi
+  %cmp21 = icmp sgt i32 %N, 1
+  br i1 %cmp21, label %for.cond1.preheader.lr.ph, label %for.end16
+
+for.cond1.preheader.lr.ph: 
+  %cmp218 = icmp sgt i32 %M, 1
+  %gi.promoted = load i32, i32* @gi
+  %0 = add i32 %M, -1
+  %1 = sext i32 %gi.promoted to i64
+  %2 = sext i32 %N to i64
+  %3 = add i32 %gi.promoted, 1
+  %4 = icmp slt i32 %3, %N
+  %smax = select i1 %4, i32 %N, i32 %3
+  br label %for.cond1.preheader
+
+for.cond1.preheader: 
+  %indvars.iv25 = phi i64 [ %1, %for.cond1.preheader.lr.ph ], [ %indvars.iv.next26, %for.inc14 ]
+  br i1 %cmp218, label %for.body3, label %for.inc14
+
+for.body3: 
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3 ], [ 1, %for.cond1.preheader ]
+  %5 = add nsw i64 %indvars.iv, -1
+  %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %5, i64 %indvars.iv25
+  %6 = load i32, i32* %arrayidx5
+  %arrayidx9 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @C, i64 0, i64 %indvars.iv, i64 %indvars.iv25
+  %7 = load i32, i32* %arrayidx9
+  %add = add nsw i32 %7, %6
+  %arrayidx13 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv, i64 %indvars.iv25
+  store i32 %add, i32* %arrayidx13
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %0
+  br i1 %exitcond, label %for.inc14, label %for.body3
+
+for.inc14: 
+  %inc.lcssa23 = phi i32 [ 1, %for.cond1.preheader ], [ %M, %for.body3 ]
+  %indvars.iv.next26 = add nsw i64 %indvars.iv25, 1
+  %cmp = icmp slt i64 %indvars.iv.next26, %2
+  br i1 %cmp, label %for.cond1.preheader, label %for.cond.for.end16_crit_edge
+
+for.cond.for.end16_crit_edge: 
+  store i32 %inc.lcssa23, i32* @gj
+  store i32 %smax, i32* @gi
+  br label %for.end16
+
+for.end16:
+  ret void
+}
+
+; CHECK-LABEL: @interchange_07
+; CHECK: for.body3:                                        ; preds = %for.body3.preheader, %for.body3
+; CHECK:   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3 ], [ 1, %for.body3.preheader ]
+; CHECK:   %5 = add nsw i64 %indvars.iv, -1
+; CHECK:   %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %5, i64 %indvars.iv25
+; CHECK:   %6 = load i32, i32* %arrayidx5
+; CHECK:   %arrayidx9 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @C, i64 0, i64 %indvars.iv, i64 %indvars.iv25
+
+;;------------------------------------------------Test case 08-------------------------------
+;; Test for interchange in loop nest greater than 2.
+;;  for(int i=0;i<100;i++)
+;;    for(int j=0;j<100;j++)
+;;      for(int k=0;k<100;k++)
+;;        D[i][k][j] = D[i][k][j]+t;
+
+define void @interchange_08(i32 %t){
+entry:
+  br label %for.cond1.preheader
+
+for.cond1.preheader:                              ; preds = %for.inc15, %entry
+  %i.028 = phi i32 [ 0, %entry ], [ %inc16, %for.inc15 ]
+  br label %for.cond4.preheader
+
+for.cond4.preheader:                              ; preds = %for.inc12, %for.cond1.preheader
+  %j.027 = phi i32 [ 0, %for.cond1.preheader ], [ %inc13, %for.inc12 ]
+  br label %for.body6
+
+for.body6:                                        ; preds = %for.body6, %for.cond4.preheader
+  %k.026 = phi i32 [ 0, %for.cond4.preheader ], [ %inc, %for.body6 ]
+  %arrayidx8 = getelementptr inbounds [100 x [100 x [100 x i32]]], [100 x [100 x [100 x i32]]]* @D, i32 0, i32 %i.028, i32 %k.026, i32 %j.027
+  %0 = load i32, i32* %arrayidx8
+  %add = add nsw i32 %0, %t
+  store i32 %add, i32* %arrayidx8
+  %inc = add nuw nsw i32 %k.026, 1
+  %exitcond = icmp eq i32 %inc, 100
+  br i1 %exitcond, label %for.inc12, label %for.body6
+
+for.inc12:                                        ; preds = %for.body6
+  %inc13 = add nuw nsw i32 %j.027, 1
+  %exitcond29 = icmp eq i32 %inc13, 100
+  br i1 %exitcond29, label %for.inc15, label %for.cond4.preheader
+
+for.inc15:                                        ; preds = %for.inc12
+  %inc16 = add nuw nsw i32 %i.028, 1
+  %exitcond30 = icmp eq i32 %inc16, 100
+  br i1 %exitcond30, label %for.end17, label %for.cond1.preheader
+
+for.end17:                                        ; preds = %for.inc15
+  ret void
+}
+; CHECK-LABEL: @interchange_08
+; CHECK:   entry:
+; CHECK:     br label %for.cond1.preheader.preheader
+; CHECK:   for.cond1.preheader.preheader:                    ; preds = %entry
+; CHECK:     br label %for.cond1.preheader
+; CHECK:   for.cond1.preheader:                              ; preds = %for.cond1.preheader.preheader, %for.inc15
+; CHECK:     %i.028 = phi i32 [ %inc16, %for.inc15 ], [ 0, %for.cond1.preheader.preheader ]
+; CHECK:     br label %for.body6.preheader
+; CHECK:   for.cond4.preheader.preheader:                    ; preds = %for.body6
+; CHECK:     br label %for.cond4.preheader
+; CHECK:   for.cond4.preheader:                              ; preds = %for.cond4.preheader.preheader, %for.inc12
+; CHECK:     %j.027 = phi i32 [ %inc13, %for.inc12 ], [ 0, %for.cond4.preheader.preheader ]
+; CHECK:     br label %for.body6.split1
+; CHECK:   for.body6.preheader:                              ; preds = %for.cond1.preheader
+; CHECK:     br label %for.body6
+; CHECK:   for.body6:                                        ; preds = %for.body6.preheader, %for.body6.split
+; CHECK:     %k.026 = phi i32 [ %inc, %for.body6.split ], [ 0, %for.body6.preheader ]
+; CHECK:     br label %for.cond4.preheader.preheader
+; CHECK:   for.body6.split1:                                 ; preds = %for.cond4.preheader
+; CHECK:     %arrayidx8 = getelementptr inbounds [100 x [100 x [100 x i32]]], [100 x [100 x [100 x i32]]]* @D, i32 0, i32 %i.028, i32 %k.026, i32 %j.027
+; CHECK:     %0 = load i32, i32* %arrayidx8
+; CHECK:     %add = add nsw i32 %0, %t
+; CHECK:     store i32 %add, i32* %arrayidx8
+; CHECK:     br label %for.inc12
+; CHECK:   for.body6.split:                                  ; preds = %for.inc12
+; CHECK:     %inc = add nuw nsw i32 %k.026, 1
+; CHECK:     %exitcond = icmp eq i32 %inc, 100
+; CHECK:     br i1 %exitcond, label %for.inc15, label %for.body6
+; CHECK:   for.inc12:                                        ; preds = %for.body6.split1
+; CHECK:     %inc13 = add nuw nsw i32 %j.027, 1
+; CHECK:     %exitcond29 = icmp eq i32 %inc13, 100
+; CHECK:     br i1 %exitcond29, label %for.body6.split, label %for.cond4.preheader
+; CHECK:   for.inc15:                                        ; preds = %for.body6.split
+; CHECK:     %inc16 = add nuw nsw i32 %i.028, 1
+; CHECK:     %exitcond30 = icmp eq i32 %inc16, 100
+; CHECK:     br i1 %exitcond30, label %for.end17, label %for.cond1.preheader
+; CHECK:   for.end17:                                        ; preds = %for.inc15
+; CHECK:     ret void
+
diff --git a/test/Transforms/LoopInterchange/profitability.ll b/test/Transforms/LoopInterchange/profitability.ll
new file mode 100644
index 000000000000..ae1f79314486
--- /dev/null
+++ b/test/Transforms/LoopInterchange/profitability.ll
@@ -0,0 +1,205 @@
+; RUN: opt < %s -basicaa -loop-interchange -S | FileCheck %s
+;; We test profitability model in these test cases.
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+@A = common global [100 x [100 x i32]] zeroinitializer
+@B = common global [100 x [100 x i32]] zeroinitializer
+
+;;---------------------------------------Test case 01---------------------------------
+;; Loops interchange will result in code vectorization and hence profitable. Check for interchange.
+;;   for(int i=1;i<N;i++)
+;;     for(int j=1;j<N;j++)
+;;       A[j][i] = A[j - 1][i] + B[j][i];
+
+define void @interchange_01(i32 %N) {
+entry:
+  %cmp27 = icmp sgt i32 %N, 1
+  br i1 %cmp27, label %for.cond1.preheader.lr.ph, label %for.end16
+
+for.cond1.preheader.lr.ph:
+  %0 = add i32 %N, -1
+  br label %for.body3.preheader
+
+for.body3.preheader:
+  %indvars.iv30 = phi i64 [ 1, %for.cond1.preheader.lr.ph ], [ %indvars.iv.next31, %for.inc14 ]
+  br label %for.body3
+
+for.body3:
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3 ], [ 1, %for.body3.preheader ]
+  %1 = add nsw i64 %indvars.iv, -1
+  %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %1, i64 %indvars.iv30
+  %2 = load i32, i32* %arrayidx5
+  %arrayidx9 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @B, i64 0, i64 %indvars.iv, i64 %indvars.iv30
+  %3 = load i32, i32* %arrayidx9
+  %add = add nsw i32 %3, %2
+  %arrayidx13 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv, i64 %indvars.iv30
+  store i32 %add, i32* %arrayidx13
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %0
+  br i1 %exitcond, label %for.inc14, label %for.body3
+
+for.inc14:
+  %indvars.iv.next31 = add nuw nsw i64 %indvars.iv30, 1
+  %lftr.wideiv32 = trunc i64 %indvars.iv30 to i32
+  %exitcond33 = icmp eq i32 %lftr.wideiv32, %0
+  br i1 %exitcond33, label %for.end16, label %for.body3.preheader
+
+for.end16:
+  ret void
+}
+;; Here we are checking partial .ll to check if loop are interchanged.
+; CHECK-LABEL: @interchange_01
+; CHECK:  for.body3.preheader:                              ; preds = %for.inc14, %for.cond1.preheader.lr.ph
+; CHECK:    %indvars.iv30 = phi i64 [ 1, %for.cond1.preheader.lr.ph ], [ %indvars.iv.next31, %for.inc14 ]
+; CHECK:    br label %for.body3.split2
+
+; CHECK:  for.body3.preheader1:                             ; preds = %entry
+; CHECK:    br label %for.body3
+
+; CHECK:  for.body3:                                        ; preds = %for.body3.preheader1, %for.body3.split
+; CHECK:    %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3.split ], [ 1, %for.body3.preheader1 ]
+; CHECK:    br label %for.cond1.preheader.lr.ph
+
+; CHECK:  for.body3.split2:                                 ; preds = %for.body3.preheader
+; CHECK:    %1 = add nsw i64 %indvars.iv, -1
+; CHECK:    %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %1, i64 %indvars.iv30
+; CHECK:    %2 = load i32, i32* %arrayidx5
+; CHECK:    %arrayidx9 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @B, i64 0, i64 %indvars.iv, i64 %indvars.iv30
+; CHECK:    %3 = load i32, i32* %arrayidx9
+; CHECK:    %add = add nsw i32 %3, %2
+; CHECK:    %arrayidx13 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %indvars.iv, i64 %indvars.iv30
+; CHECK:    store i32 %add, i32* %arrayidx13
+; CHECK:    br label %for.inc14
+
+
+;; ---------------------------------------Test case 02---------------------------------
+;; Check loop interchange profitability model. 
+;; This tests profitability model when operands of getelementpointer and not exactly the induction variable but some 
+;; arithmetic operation on them.
+;;   for(int i=1;i<N;i++)
+;;    for(int j=1;j<N;j++)
+;;       A[j-1][i-1] = A[j - 1][i-1] + B[j-1][i-1];
+
+define void @interchange_02(i32 %N) {
+entry:
+  %cmp32 = icmp sgt i32 %N, 1
+  br i1 %cmp32, label %for.cond1.preheader.lr.ph, label %for.end21
+
+for.cond1.preheader.lr.ph:
+  %0 = add i32 %N, -1
+  br label %for.body3.lr.ph
+
+for.body3.lr.ph:
+  %indvars.iv35 = phi i64 [ 1, %for.cond1.preheader.lr.ph ], [ %indvars.iv.next36, %for.inc19 ]
+  %1 = add nsw i64 %indvars.iv35, -1
+  br label %for.body3
+
+for.body3: 
+  %indvars.iv = phi i64 [ 1, %for.body3.lr.ph ], [ %indvars.iv.next, %for.body3 ]
+  %2 = add nsw i64 %indvars.iv, -1
+  %arrayidx6 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %2, i64 %1
+  %3 = load i32, i32* %arrayidx6
+  %arrayidx12 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @B, i64 0, i64 %2, i64 %1
+  %4 = load i32, i32* %arrayidx12
+  %add = add nsw i32 %4, %3
+  store i32 %add, i32* %arrayidx6
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %0
+  br i1 %exitcond, label %for.inc19, label %for.body3
+
+for.inc19:
+  %indvars.iv.next36 = add nuw nsw i64 %indvars.iv35, 1
+  %lftr.wideiv38 = trunc i64 %indvars.iv35 to i32
+  %exitcond39 = icmp eq i32 %lftr.wideiv38, %0
+  br i1 %exitcond39, label %for.end21, label %for.body3.lr.ph
+
+for.end21:
+  ret void
+}
+; CHECK-LABEL: @interchange_02
+; CHECK:  for.body3.lr.ph:                                  ; preds = %for.inc19, %for.cond1.preheader.lr.ph
+; CHECK:    %indvars.iv35 = phi i64 [ 1, %for.cond1.preheader.lr.ph ], [ %indvars.iv.next36, %for.inc19 ]
+; CHECK:    %0 = add nsw i64 %indvars.iv35, -1
+; CHECK:    br label %for.body3.split1
+
+; CHECK:  for.body3.preheader:                              ; preds = %entry
+; CHECK:    %1 = add i32 %N, -1
+; CHECK:    br label %for.body3
+
+; CHECK:  for.body3:                                        ; preds = %for.body3.preheader, %for.body3.split
+; CHECK:    %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3.split ], [ 1, %for.body3.preheader ]
+; CHECK:    br label %for.cond1.preheader.lr.ph
+
+; CHECK:  for.body3.split1:                                 ; preds = %for.body3.lr.ph
+; CHECK:    %2 = add nsw i64 %indvars.iv, -1
+; CHECK:    %arrayidx6 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %2, i64 %0
+; CHECK:    %3 = load i32, i32* %arrayidx6
+; CHECK:    %arrayidx12 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @B, i64 0, i64 %2, i64 %0
+; CHECK:    %4 = load i32, i32* %arrayidx12
+; CHECK:    %add = add nsw i32 %4, %3
+; CHECK:    store i32 %add, i32* %arrayidx6
+; CHECK:    br label %for.inc19
+
+
+;;---------------------------------------Test case 03---------------------------------
+;; Loops interchange is not profitable.
+;;   for(int i=1;i<N;i++)
+;;     for(int j=1;j<N;j++)
+;;       A[i-1][j-1] = A[i - 1][j-1] + B[i][j];
+
+define void @interchange_03(i32 %N){
+entry:
+  %cmp31 = icmp sgt i32 %N, 1
+  br i1 %cmp31, label %for.cond1.preheader.lr.ph, label %for.end19
+
+for.cond1.preheader.lr.ph:
+  %0 = add i32 %N, -1
+  br label %for.body3.lr.ph
+
+for.body3.lr.ph:
+  %indvars.iv34 = phi i64 [ 1, %for.cond1.preheader.lr.ph ], [ %indvars.iv.next35, %for.inc17 ]
+  %1 = add nsw i64 %indvars.iv34, -1
+  br label %for.body3
+
+for.body3:
+  %indvars.iv = phi i64 [ 1, %for.body3.lr.ph ], [ %indvars.iv.next, %for.body3 ]
+  %2 = add nsw i64 %indvars.iv, -1
+  %arrayidx6 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %1, i64 %2
+  %3 = load i32, i32* %arrayidx6
+  %arrayidx10 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @B, i64 0, i64 %indvars.iv34, i64 %indvars.iv
+  %4 = load i32, i32* %arrayidx10
+  %add = add nsw i32 %4, %3
+  store i32 %add, i32* %arrayidx6
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %0
+  br i1 %exitcond, label %for.inc17, label %for.body3
+
+for.inc17:
+  %indvars.iv.next35 = add nuw nsw i64 %indvars.iv34, 1
+  %lftr.wideiv37 = trunc i64 %indvars.iv34 to i32
+  %exitcond38 = icmp eq i32 %lftr.wideiv37, %0
+  br i1 %exitcond38, label %for.end19, label %for.body3.lr.ph
+
+for.end19:
+  ret void
+}
+
+; CHECK-LABEL: @interchange_03
+; CHECK:  for.body3.lr.ph:
+; CHECK:    %indvars.iv34 = phi i64 [ 1, %for.cond1.preheader.lr.ph ], [ %indvars.iv.next35, %for.inc17 ]
+; CHECK:    %1 = add nsw i64 %indvars.iv34, -1
+; CHECK:    br label %for.body3.preheader
+; CHECK:  for.body3.preheader:
+; CHECK:    br label %for.body3
+; CHECK:  for.body3:
+; CHECK:    %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3 ], [ 1, %for.body3.preheader ]
+; CHECK:    %2 = add nsw i64 %indvars.iv, -1
+; CHECK:    %arrayidx6 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %1, i64 %2
+; CHECK:    %3 = load i32, i32* %arrayidx6
+; CHECK:    %arrayidx10 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @B, i64 0, i64 %indvars.iv34, i64 %indvars.iv
+; CHECK:    %4 = load i32, i32* %arrayidx10
diff --git a/test/Transforms/LoopInterchange/reductions.ll b/test/Transforms/LoopInterchange/reductions.ll
new file mode 100644
index 000000000000..86a44da7cf20
--- /dev/null
+++ b/test/Transforms/LoopInterchange/reductions.ll
@@ -0,0 +1,235 @@
+; RUN: opt < %s -basicaa -loop-interchange -S | FileCheck %s
+
+@A = common global [500 x [500 x i32]] zeroinitializer
+@X = common global i32 0
+@B = common global [500 x [500 x i32]] zeroinitializer
+@Y = common global i32 0
+
+;;  for( int i=1;i<N;i++)
+;;    for( int j=1;j<N;j++)
+;;      X+=A[j][i];
+
+define void @reduction_01(i32 %N) {
+entry:
+  %cmp16 = icmp sgt i32 %N, 1
+  br i1 %cmp16, label %for.body3.lr.ph, label %for.end8
+
+for.body3.lr.ph:                                  ; preds = %entry, %for.cond1.for.inc6_crit_edge
+  %indvars.iv18 = phi i64 [ %indvars.iv.next19, %for.cond1.for.inc6_crit_edge ], [ 1, %entry ]
+  %X.promoted = load i32, i32* @X
+  br label %for.body3
+
+for.body3:                                        ; preds = %for.body3, %for.body3.lr.ph
+  %indvars.iv = phi i64 [ 1, %for.body3.lr.ph ], [ %indvars.iv.next, %for.body3 ]
+  %add15 = phi i32 [ %X.promoted, %for.body3.lr.ph ], [ %add, %for.body3 ]
+  %arrayidx5 = getelementptr inbounds [500 x [500 x i32]], [500 x [500 x i32]]* @A, i64 0, i64 %indvars.iv, i64 %indvars.iv18
+  %0 = load i32, i32* %arrayidx5
+  %add = add nsw i32 %add15, %0
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %N
+  br i1 %exitcond, label %for.cond1.for.inc6_crit_edge, label %for.body3
+
+for.cond1.for.inc6_crit_edge:                     ; preds = %for.body3
+  store i32 %add, i32* @X
+  %indvars.iv.next19 = add nuw nsw i64 %indvars.iv18, 1
+  %lftr.wideiv20 = trunc i64 %indvars.iv.next19 to i32
+  %exitcond21 = icmp eq i32 %lftr.wideiv20, %N
+  br i1 %exitcond21, label %for.end8, label %for.body3.lr.ph
+
+for.end8:                                         ; preds = %for.cond1.for.inc6_crit_edge, %entry
+  ret void
+}
+
+;; Loop is interchanged check that the phi nodes are split and the promoted value is used instead of the reduction phi.
+; CHECK-LABEL: @reduction_01
+; CHECK:  for.body3:                                        ; preds = %for.body3.preheader, %for.body3.split
+; CHECK:    %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3.split ], [ 1, %for.body3.preheader ]
+; CHECK:    br label %for.body3.lr.ph.preheader
+; CHECK:    %add = add nsw i32 %X.promoted
+
+
+;; Test for more than 1 reductions inside a loop.
+;;  for( int i=1;i<N;i++)
+;;    for( int j=1;j<N;j++)
+;;      for( int k=1;k<N;k++) {
+;;        X+=A[k][j];
+;;        Y+=B[k][i];
+;;      }
+
+define void @reduction_02(i32 %N)  {
+entry:
+  %cmp34 = icmp sgt i32 %N, 1
+  br i1 %cmp34, label %for.cond4.preheader.preheader, label %for.end19
+
+for.cond4.preheader.preheader:                    ; preds = %entry, %for.inc17
+  %indvars.iv40 = phi i64 [ %indvars.iv.next41, %for.inc17 ], [ 1, %entry ]
+  br label %for.body6.lr.ph
+
+for.body6.lr.ph:                                  ; preds = %for.cond4.for.inc14_crit_edge, %for.cond4.preheader.preheader
+  %indvars.iv36 = phi i64 [ %indvars.iv.next37, %for.cond4.for.inc14_crit_edge ], [ 1, %for.cond4.preheader.preheader ]
+  %X.promoted = load i32, i32* @X
+  %Y.promoted = load i32, i32* @Y
+  br label %for.body6
+
+for.body6:                                        ; preds = %for.body6, %for.body6.lr.ph
+  %indvars.iv = phi i64 [ 1, %for.body6.lr.ph ], [ %indvars.iv.next, %for.body6 ]
+  %add1331 = phi i32 [ %Y.promoted, %for.body6.lr.ph ], [ %add13, %for.body6 ]
+  %add30 = phi i32 [ %X.promoted, %for.body6.lr.ph ], [ %add, %for.body6 ]
+  %arrayidx8 = getelementptr inbounds [500 x [500 x i32]], [500 x [500 x i32]]* @A, i64 0, i64 %indvars.iv, i64 %indvars.iv36
+  %0 = load i32, i32* %arrayidx8
+  %add = add nsw i32 %add30, %0
+  %arrayidx12 = getelementptr inbounds [500 x [500 x i32]], [500 x [500 x i32]]* @B, i64 0, i64 %indvars.iv, i64 %indvars.iv40
+  %1 = load i32, i32* %arrayidx12
+  %add13 = add nsw i32 %add1331, %1
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %N
+  br i1 %exitcond, label %for.cond4.for.inc14_crit_edge, label %for.body6
+
+for.cond4.for.inc14_crit_edge:                    ; preds = %for.body6
+  store i32 %add, i32* @X
+  store i32 %add13, i32* @Y
+  %indvars.iv.next37 = add nuw nsw i64 %indvars.iv36, 1
+  %lftr.wideiv38 = trunc i64 %indvars.iv.next37 to i32
+  %exitcond39 = icmp eq i32 %lftr.wideiv38, %N
+  br i1 %exitcond39, label %for.inc17, label %for.body6.lr.ph
+
+for.inc17:                                        ; preds = %for.cond4.for.inc14_crit_edge
+  %indvars.iv.next41 = add nuw nsw i64 %indvars.iv40, 1
+  %lftr.wideiv42 = trunc i64 %indvars.iv.next41 to i32
+  %exitcond43 = icmp eq i32 %lftr.wideiv42, %N
+  br i1 %exitcond43, label %for.end19, label %for.cond4.preheader.preheader
+
+for.end19:                                        ; preds = %for.inc17, %entry
+  ret void
+}
+
+;; Loop is interchanged check that the phi nodes are split and the promoted value is used instead of the reduction phi.
+; CHECK-LABEL: @reduction_02
+; CHECK:  for.body6:                                        ; preds = %for.body6.preheader, %for.body6.split
+; CHECK:    %indvars.iv = phi i64 [ %indvars.iv.next, %for.body6.split ], [ 1, %for.body6.preheader ]
+; CHECK:    br label %for.cond4.preheader.preheader.preheader
+; CHECK:    %add13 = add nsw i32 %Y.promoted
+
+
+;; Not tightly nested. Do not interchange.
+;;  for( int i=1;i<N;i++)
+;;    for( int j=1;j<N;j++) {
+;;      for( int k=1;k<N;k++) {
+;;        X+=A[k][j];
+;;      }
+;;      Y+=B[j][i];
+;;    }
+define void @reduction_03(i32 %N)  {
+entry:
+  %cmp35 = icmp sgt i32 %N, 1
+  br i1 %cmp35, label %for.cond4.preheader.lr.ph, label %for.end19
+
+for.cond4.preheader.lr.ph:                        ; preds = %entry, %for.cond1.for.inc17_crit_edge
+  %indvars.iv41 = phi i64 [ %indvars.iv.next42, %for.cond1.for.inc17_crit_edge ], [ 1, %entry ]
+  %Y.promoted = load i32, i32* @Y
+  br label %for.body6.lr.ph
+
+for.body6.lr.ph:                                  ; preds = %for.cond4.preheader.lr.ph, %for.cond4.for.end_crit_edge
+  %indvars.iv37 = phi i64 [ 1, %for.cond4.preheader.lr.ph ], [ %indvars.iv.next38, %for.cond4.for.end_crit_edge ]
+  %add1334 = phi i32 [ %Y.promoted, %for.cond4.preheader.lr.ph ], [ %add13, %for.cond4.for.end_crit_edge ]
+  %X.promoted = load i32, i32* @X
+  br label %for.body6
+
+for.body6:                                        ; preds = %for.body6, %for.body6.lr.ph
+  %indvars.iv = phi i64 [ 1, %for.body6.lr.ph ], [ %indvars.iv.next, %for.body6 ]
+  %add31 = phi i32 [ %X.promoted, %for.body6.lr.ph ], [ %add, %for.body6 ]
+  %arrayidx8 = getelementptr inbounds [500 x [500 x i32]], [500 x [500 x i32]]* @A, i64 0, i64 %indvars.iv, i64 %indvars.iv37
+  %0 = load i32, i32* %arrayidx8
+  %add = add nsw i32 %add31, %0
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %N
+  br i1 %exitcond, label %for.cond4.for.end_crit_edge, label %for.body6
+
+for.cond4.for.end_crit_edge:                      ; preds = %for.body6
+  store i32 %add, i32* @X
+  %arrayidx12 = getelementptr inbounds [500 x [500 x i32]], [500 x [500 x i32]]* @B, i64 0, i64 %indvars.iv37, i64 %indvars.iv41
+  %1 = load i32, i32* %arrayidx12
+  %add13 = add nsw i32 %add1334, %1
+  %indvars.iv.next38 = add nuw nsw i64 %indvars.iv37, 1
+  %lftr.wideiv39 = trunc i64 %indvars.iv.next38 to i32
+  %exitcond40 = icmp eq i32 %lftr.wideiv39, %N
+  br i1 %exitcond40, label %for.cond1.for.inc17_crit_edge, label %for.body6.lr.ph
+
+for.cond1.for.inc17_crit_edge:                    ; preds = %for.cond4.for.end_crit_edge
+  store i32 %add13, i32* @Y
+  %indvars.iv.next42 = add nuw nsw i64 %indvars.iv41, 1
+  %lftr.wideiv43 = trunc i64 %indvars.iv.next42 to i32
+  %exitcond44 = icmp eq i32 %lftr.wideiv43, %N
+  br i1 %exitcond44, label %for.end19, label %for.cond4.preheader.lr.ph
+
+for.end19:                                        ; preds = %for.cond1.for.inc17_crit_edge, %entry
+  ret void
+}
+;; Not tightly nested. Do not interchange.
+;; Not interchanged hence the phi's in the inner loop will not be split. Check for the same.
+; CHECK-LABEL: @reduction_03
+; CHECK:  for.body6:                                        ; preds = %for.body6.preheader, %for.body6
+; CHECK:    %indvars.iv = phi i64 [ %indvars.iv.next, %for.body6 ], [ 1, %for.body6.preheader ]
+; CHECK:    %add31 = phi i32 [ %add, %for.body6 ], [ %X.promoted, %for.body6.preheader ]
+
+
+
+;; Multiple use of reduction not safe. Do not interchange.
+;;  for( int i=1;i<N;i++)
+;;    for( int j=1;j<N;j++)
+;;      for( int k=1;k<N;k++) {
+;;        X+=A[k][j];
+;;        Y+=X;
+;;      }
+define void @reduction_04(i32 %N) {
+entry:
+  %cmp28 = icmp sgt i32 %N, 1
+  br i1 %cmp28, label %for.cond4.preheader.preheader, label %for.end15
+
+for.cond4.preheader.preheader:                    ; preds = %entry, %for.inc13
+  %i.029 = phi i32 [ %inc14, %for.inc13 ], [ 1, %entry ]
+  br label %for.body6.lr.ph
+
+for.body6.lr.ph:                                  ; preds = %for.cond4.for.inc10_crit_edge, %for.cond4.preheader.preheader
+  %indvars.iv30 = phi i64 [ %indvars.iv.next31, %for.cond4.for.inc10_crit_edge ], [ 1, %for.cond4.preheader.preheader ]
+  %X.promoted = load i32, i32* @X
+  %Y.promoted = load i32, i32* @Y
+  br label %for.body6
+
+for.body6:                                        ; preds = %for.body6, %for.body6.lr.ph
+  %indvars.iv = phi i64 [ 1, %for.body6.lr.ph ], [ %indvars.iv.next, %for.body6 ]
+  %add925 = phi i32 [ %Y.promoted, %for.body6.lr.ph ], [ %add9, %for.body6 ]
+  %add24 = phi i32 [ %X.promoted, %for.body6.lr.ph ], [ %add, %for.body6 ]
+  %arrayidx8 = getelementptr inbounds [500 x [500 x i32]], [500 x [500 x i32]]* @A, i64 0, i64 %indvars.iv, i64 %indvars.iv30
+  %0 = load i32, i32* %arrayidx8
+  %add = add nsw i32 %add24, %0
+  %add9 = add nsw i32 %add925, %add
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %N
+  br i1 %exitcond, label %for.cond4.for.inc10_crit_edge, label %for.body6
+
+for.cond4.for.inc10_crit_edge:                    ; preds = %for.body6
+  store i32 %add, i32* @X
+  store i32 %add9, i32* @Y
+  %indvars.iv.next31 = add nuw nsw i64 %indvars.iv30, 1
+  %lftr.wideiv32 = trunc i64 %indvars.iv.next31 to i32
+  %exitcond33 = icmp eq i32 %lftr.wideiv32, %N
+  br i1 %exitcond33, label %for.inc13, label %for.body6.lr.ph
+
+for.inc13:                                        ; preds = %for.cond4.for.inc10_crit_edge
+  %inc14 = add nuw nsw i32 %i.029, 1
+  %exitcond34 = icmp eq i32 %inc14, %N
+  br i1 %exitcond34, label %for.end15, label %for.cond4.preheader.preheader
+
+for.end15:                                        ; preds = %for.inc13, %entry
+  ret void
+}
+;; Not interchanged hence the phi's in the inner loop will not be split. Check for the same.
+; CHECK-LABEL: @reduction_04
+; CHECK:  for.body6:                                        ; preds = %for.body6.preheader, %for.body6
+; CHECK:    %indvars.iv = phi i64 [ %indvars.iv.next, %for.body6 ], [ 1, %for.body6.preheader ]
+; CHECK:    %add925 = phi i32 [ %add9, %for.body6 ], [ %Y.promoted, %for.body6.preheader ]
diff --git a/test/Transforms/LoopReroll/basic.ll b/test/Transforms/LoopReroll/basic.ll
index 3bd6d7ae02e1..16a6dc81af79 100644
--- a/test/Transforms/LoopReroll/basic.ll
+++ b/test/Transforms/LoopReroll/basic.ll
@@ -60,15 +60,15 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %call = tail call i32 @foo(i32 0) #1
-  %arrayidx = getelementptr inbounds i32* %x, i64 %indvars.iv
+  %arrayidx = getelementptr inbounds i32, i32* %x, i64 %indvars.iv
   store i32 %call, i32* %arrayidx, align 4
   %call1 = tail call i32 @foo(i32 0) #1
   %0 = add nsw i64 %indvars.iv, 1
-  %arrayidx3 = getelementptr inbounds i32* %x, i64 %0
+  %arrayidx3 = getelementptr inbounds i32, i32* %x, i64 %0
   store i32 %call1, i32* %arrayidx3, align 4
   %call4 = tail call i32 @foo(i32 0) #1
   %1 = add nsw i64 %indvars.iv, 2
-  %arrayidx7 = getelementptr inbounds i32* %x, i64 %1
+  %arrayidx7 = getelementptr inbounds i32, i32* %x, i64 %1
   store i32 %call4, i32* %arrayidx7, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 3
   %2 = trunc i64 %indvars.iv.next to i32
@@ -80,7 +80,7 @@ for.body:                                         ; preds = %entry, %for.body
 ; CHECK: for.body:
 ; CHECK: %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %entry ]
 ; CHECK: %call = tail call i32 @foo(i32 0) #1
-; CHECK: %arrayidx = getelementptr inbounds i32* %x, i64 %indvar
+; CHECK: %arrayidx = getelementptr inbounds i32, i32* %x, i64 %indvar
 ; CHECK: store i32 %call, i32* %arrayidx, align 4
 ; CHECK: %indvar.next = add i64 %indvar, 1
 ; CHECK: %exitcond = icmp eq i64 %indvar, 1499
@@ -109,15 +109,15 @@ for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %call = tail call i32 @foo(i32 0) #1
   %0 = mul nsw i64 %indvars.iv, 3
-  %arrayidx = getelementptr inbounds i32* %x, i64 %0
+  %arrayidx = getelementptr inbounds i32, i32* %x, i64 %0
   store i32 %call, i32* %arrayidx, align 4
   %call1 = tail call i32 @foo(i32 0) #1
   %1 = add nsw i64 %0, 1
-  %arrayidx4 = getelementptr inbounds i32* %x, i64 %1
+  %arrayidx4 = getelementptr inbounds i32, i32* %x, i64 %1
   store i32 %call1, i32* %arrayidx4, align 4
   %call5 = tail call i32 @foo(i32 0) #1
   %2 = add nsw i64 %0, 2
-  %arrayidx9 = getelementptr inbounds i32* %x, i64 %2
+  %arrayidx9 = getelementptr inbounds i32, i32* %x, i64 %2
   store i32 %call5, i32* %arrayidx9, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 500
@@ -128,7 +128,7 @@ for.body:                                         ; preds = %for.body, %entry
 ; CHECK: for.body:
 ; CHECK: %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
 ; CHECK: %call = tail call i32 @foo(i32 0) #1
-; CHECK: %arrayidx = getelementptr inbounds i32* %x, i64 %indvars.iv
+; CHECK: %arrayidx = getelementptr inbounds i32, i32* %x, i64 %indvars.iv
 ; CHECK: store i32 %call, i32* %arrayidx, align 4
 ; CHECK: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
 ; CHECK: %exitcond1 = icmp eq i64 %indvars.iv, 1499
@@ -157,43 +157,43 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %b, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %mul = fmul float %0, %alpha
-  %arrayidx2 = getelementptr inbounds float* %a, i64 %indvars.iv
-  %1 = load float* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %a, i64 %indvars.iv
+  %1 = load float, float* %arrayidx2, align 4
   %add = fadd float %1, %mul
   store float %add, float* %arrayidx2, align 4
   %2 = add nsw i64 %indvars.iv, 1
-  %arrayidx5 = getelementptr inbounds float* %b, i64 %2
-  %3 = load float* %arrayidx5, align 4
+  %arrayidx5 = getelementptr inbounds float, float* %b, i64 %2
+  %3 = load float, float* %arrayidx5, align 4
   %mul6 = fmul float %3, %alpha
-  %arrayidx9 = getelementptr inbounds float* %a, i64 %2
-  %4 = load float* %arrayidx9, align 4
+  %arrayidx9 = getelementptr inbounds float, float* %a, i64 %2
+  %4 = load float, float* %arrayidx9, align 4
   %add10 = fadd float %4, %mul6
   store float %add10, float* %arrayidx9, align 4
   %5 = add nsw i64 %indvars.iv, 2
-  %arrayidx13 = getelementptr inbounds float* %b, i64 %5
-  %6 = load float* %arrayidx13, align 4
+  %arrayidx13 = getelementptr inbounds float, float* %b, i64 %5
+  %6 = load float, float* %arrayidx13, align 4
   %mul14 = fmul float %6, %alpha
-  %arrayidx17 = getelementptr inbounds float* %a, i64 %5
-  %7 = load float* %arrayidx17, align 4
+  %arrayidx17 = getelementptr inbounds float, float* %a, i64 %5
+  %7 = load float, float* %arrayidx17, align 4
   %add18 = fadd float %7, %mul14
   store float %add18, float* %arrayidx17, align 4
   %8 = add nsw i64 %indvars.iv, 3
-  %arrayidx21 = getelementptr inbounds float* %b, i64 %8
-  %9 = load float* %arrayidx21, align 4
+  %arrayidx21 = getelementptr inbounds float, float* %b, i64 %8
+  %9 = load float, float* %arrayidx21, align 4
   %mul22 = fmul float %9, %alpha
-  %arrayidx25 = getelementptr inbounds float* %a, i64 %8
-  %10 = load float* %arrayidx25, align 4
+  %arrayidx25 = getelementptr inbounds float, float* %a, i64 %8
+  %10 = load float, float* %arrayidx25, align 4
   %add26 = fadd float %10, %mul22
   store float %add26, float* %arrayidx25, align 4
   %11 = add nsw i64 %indvars.iv, 4
-  %arrayidx29 = getelementptr inbounds float* %b, i64 %11
-  %12 = load float* %arrayidx29, align 4
+  %arrayidx29 = getelementptr inbounds float, float* %b, i64 %11
+  %12 = load float, float* %arrayidx29, align 4
   %mul30 = fmul float %12, %alpha
-  %arrayidx33 = getelementptr inbounds float* %a, i64 %11
-  %13 = load float* %arrayidx33, align 4
+  %arrayidx33 = getelementptr inbounds float, float* %a, i64 %11
+  %13 = load float, float* %arrayidx33, align 4
   %add34 = fadd float %13, %mul30
   store float %add34, float* %arrayidx33, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 5
@@ -205,11 +205,11 @@ for.body:                                         ; preds = %entry, %for.body
 
 ; CHECK: for.body:
 ; CHECK: %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %entry ]
-; CHECK: %arrayidx = getelementptr inbounds float* %b, i64 %indvar
-; CHECK: %0 = load float* %arrayidx, align 4
+; CHECK: %arrayidx = getelementptr inbounds float, float* %b, i64 %indvar
+; CHECK: %0 = load float, float* %arrayidx, align 4
 ; CHECK: %mul = fmul float %0, %alpha
-; CHECK: %arrayidx2 = getelementptr inbounds float* %a, i64 %indvar
-; CHECK: %1 = load float* %arrayidx2, align 4
+; CHECK: %arrayidx2 = getelementptr inbounds float, float* %a, i64 %indvar
+; CHECK: %1 = load float, float* %arrayidx2, align 4
 ; CHECK: %add = fadd float %1, %mul
 ; CHECK: store float %add, float* %arrayidx2, align 4
 ; CHECK: %indvar.next = add i64 %indvar, 1
@@ -239,58 +239,58 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %ip, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %ip, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %idxprom1 = sext i32 %0 to i64
-  %arrayidx2 = getelementptr inbounds float* %b, i64 %idxprom1
-  %1 = load float* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %b, i64 %idxprom1
+  %1 = load float, float* %arrayidx2, align 4
   %mul = fmul float %1, %alpha
-  %arrayidx4 = getelementptr inbounds float* %a, i64 %indvars.iv
-  %2 = load float* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds float, float* %a, i64 %indvars.iv
+  %2 = load float, float* %arrayidx4, align 4
   %add = fadd float %2, %mul
   store float %add, float* %arrayidx4, align 4
   %3 = add nsw i64 %indvars.iv, 1
-  %arrayidx7 = getelementptr inbounds i32* %ip, i64 %3
-  %4 = load i32* %arrayidx7, align 4
+  %arrayidx7 = getelementptr inbounds i32, i32* %ip, i64 %3
+  %4 = load i32, i32* %arrayidx7, align 4
   %idxprom8 = sext i32 %4 to i64
-  %arrayidx9 = getelementptr inbounds float* %b, i64 %idxprom8
-  %5 = load float* %arrayidx9, align 4
+  %arrayidx9 = getelementptr inbounds float, float* %b, i64 %idxprom8
+  %5 = load float, float* %arrayidx9, align 4
   %mul10 = fmul float %5, %alpha
-  %arrayidx13 = getelementptr inbounds float* %a, i64 %3
-  %6 = load float* %arrayidx13, align 4
+  %arrayidx13 = getelementptr inbounds float, float* %a, i64 %3
+  %6 = load float, float* %arrayidx13, align 4
   %add14 = fadd float %6, %mul10
   store float %add14, float* %arrayidx13, align 4
   %7 = add nsw i64 %indvars.iv, 2
-  %arrayidx17 = getelementptr inbounds i32* %ip, i64 %7
-  %8 = load i32* %arrayidx17, align 4
+  %arrayidx17 = getelementptr inbounds i32, i32* %ip, i64 %7
+  %8 = load i32, i32* %arrayidx17, align 4
   %idxprom18 = sext i32 %8 to i64
-  %arrayidx19 = getelementptr inbounds float* %b, i64 %idxprom18
-  %9 = load float* %arrayidx19, align 4
+  %arrayidx19 = getelementptr inbounds float, float* %b, i64 %idxprom18
+  %9 = load float, float* %arrayidx19, align 4
   %mul20 = fmul float %9, %alpha
-  %arrayidx23 = getelementptr inbounds float* %a, i64 %7
-  %10 = load float* %arrayidx23, align 4
+  %arrayidx23 = getelementptr inbounds float, float* %a, i64 %7
+  %10 = load float, float* %arrayidx23, align 4
   %add24 = fadd float %10, %mul20
   store float %add24, float* %arrayidx23, align 4
   %11 = add nsw i64 %indvars.iv, 3
-  %arrayidx27 = getelementptr inbounds i32* %ip, i64 %11
-  %12 = load i32* %arrayidx27, align 4
+  %arrayidx27 = getelementptr inbounds i32, i32* %ip, i64 %11
+  %12 = load i32, i32* %arrayidx27, align 4
   %idxprom28 = sext i32 %12 to i64
-  %arrayidx29 = getelementptr inbounds float* %b, i64 %idxprom28
-  %13 = load float* %arrayidx29, align 4
+  %arrayidx29 = getelementptr inbounds float, float* %b, i64 %idxprom28
+  %13 = load float, float* %arrayidx29, align 4
   %mul30 = fmul float %13, %alpha
-  %arrayidx33 = getelementptr inbounds float* %a, i64 %11
-  %14 = load float* %arrayidx33, align 4
+  %arrayidx33 = getelementptr inbounds float, float* %a, i64 %11
+  %14 = load float, float* %arrayidx33, align 4
   %add34 = fadd float %14, %mul30
   store float %add34, float* %arrayidx33, align 4
   %15 = add nsw i64 %indvars.iv, 4
-  %arrayidx37 = getelementptr inbounds i32* %ip, i64 %15
-  %16 = load i32* %arrayidx37, align 4
+  %arrayidx37 = getelementptr inbounds i32, i32* %ip, i64 %15
+  %16 = load i32, i32* %arrayidx37, align 4
   %idxprom38 = sext i32 %16 to i64
-  %arrayidx39 = getelementptr inbounds float* %b, i64 %idxprom38
-  %17 = load float* %arrayidx39, align 4
+  %arrayidx39 = getelementptr inbounds float, float* %b, i64 %idxprom38
+  %17 = load float, float* %arrayidx39, align 4
   %mul40 = fmul float %17, %alpha
-  %arrayidx43 = getelementptr inbounds float* %a, i64 %15
-  %18 = load float* %arrayidx43, align 4
+  %arrayidx43 = getelementptr inbounds float, float* %a, i64 %15
+  %18 = load float, float* %arrayidx43, align 4
   %add44 = fadd float %18, %mul40
   store float %add44, float* %arrayidx43, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 5
@@ -302,14 +302,14 @@ for.body:                                         ; preds = %entry, %for.body
 
 ; CHECK: for.body:
 ; CHECK: %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %entry ]
-; CHECK: %arrayidx = getelementptr inbounds i32* %ip, i64 %indvar
-; CHECK: %0 = load i32* %arrayidx, align 4
+; CHECK: %arrayidx = getelementptr inbounds i32, i32* %ip, i64 %indvar
+; CHECK: %0 = load i32, i32* %arrayidx, align 4
 ; CHECK: %idxprom1 = sext i32 %0 to i64
-; CHECK: %arrayidx2 = getelementptr inbounds float* %b, i64 %idxprom1
-; CHECK: %1 = load float* %arrayidx2, align 4
+; CHECK: %arrayidx2 = getelementptr inbounds float, float* %b, i64 %idxprom1
+; CHECK: %1 = load float, float* %arrayidx2, align 4
 ; CHECK: %mul = fmul float %1, %alpha
-; CHECK: %arrayidx4 = getelementptr inbounds float* %a, i64 %indvar
-; CHECK: %2 = load float* %arrayidx4, align 4
+; CHECK: %arrayidx4 = getelementptr inbounds float, float* %a, i64 %indvar
+; CHECK: %2 = load float, float* %arrayidx4, align 4
 ; CHECK: %add = fadd float %2, %mul
 ; CHECK: store float %add, float* %arrayidx4, align 4
 ; CHECK: %indvar.next = add i64 %indvar, 1
@@ -322,6 +322,260 @@ for.end:                                          ; preds = %for.body
   ret void
 }
 
+; void multi1(int *x) {
+;   y = foo(0)
+;   for (int i = 0; i < 500; ++i) {
+;     x[3*i] = y;
+;     x[3*i+1] = y;
+;     x[3*i+2] = y;
+;     x[3*i+6] = y;
+;     x[3*i+7] = y;
+;     x[3*i+8] = y;
+;   }
+; }
+
+; Function Attrs: nounwind uwtable
+define void @multi1(i32* nocapture %x) #0 {
+entry:
+  %call = tail call i32 @foo(i32 0) #1
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %0 = mul nsw i64 %indvars.iv, 3
+  %arrayidx = getelementptr inbounds i32, i32* %x, i64 %0
+  store i32 %call, i32* %arrayidx, align 4
+  %1 = add nsw i64 %0, 1
+  %arrayidx4 = getelementptr inbounds i32, i32* %x, i64 %1
+  store i32 %call, i32* %arrayidx4, align 4
+  %2 = add nsw i64 %0, 2
+  %arrayidx9 = getelementptr inbounds i32, i32* %x, i64 %2
+  store i32 %call, i32* %arrayidx9, align 4
+  %3 = add nsw i64 %0, 6
+  %arrayidx6 = getelementptr inbounds i32, i32* %x, i64 %3
+  store i32 %call, i32* %arrayidx6, align 4
+  %4 = add nsw i64 %0, 7
+  %arrayidx7 = getelementptr inbounds i32, i32* %x, i64 %4
+  store i32 %call, i32* %arrayidx7, align 4
+  %5 = add nsw i64 %0, 8
+  %arrayidx8 = getelementptr inbounds i32, i32* %x, i64 %5
+  store i32 %call, i32* %arrayidx8, align 4
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond = icmp eq i64 %indvars.iv.next, 500
+  br i1 %exitcond, label %for.end, label %for.body
+
+; CHECK-LABEL: @multi1
+
+; CHECK:for.body:
+; CHECK:  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+; CHECK:  %0 = add i64 %indvars.iv, 6
+; CHECK:  %arrayidx = getelementptr inbounds i32, i32* %x, i64 %indvars.iv
+; CHECK:  store i32 %call, i32* %arrayidx, align 4
+; CHECK:  %arrayidx6 = getelementptr inbounds i32, i32* %x, i64 %0
+; CHECK:  store i32 %call, i32* %arrayidx6, align 4
+; CHECK:  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+; CHECK:  %exitcond2 = icmp eq i64 %0, 1505
+; CHECK:  br i1 %exitcond2, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
+
+; void multi2(int *x) {
+;   y = foo(0)
+;   for (int i = 0; i < 500; ++i) {
+;     x[3*i] = y;
+;     x[3*i+1] = y;
+;     x[3*i+2] = y;
+;     x[3*(i+1)] = y;
+;     x[3*(i+1)+1] = y;
+;     x[3*(i+1)+2] = y;
+;   }
+; }
+
+; Function Attrs: nounwind uwtable
+define void @multi2(i32* nocapture %x) #0 {
+entry:
+  %call = tail call i32 @foo(i32 0) #1
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %0 = mul nsw i64 %indvars.iv, 3
+  %add = add nsw i64 %indvars.iv, 1
+  %newmul = mul nsw i64 %add, 3
+  %arrayidx = getelementptr inbounds i32, i32* %x, i64 %0
+  store i32 %call, i32* %arrayidx, align 4
+  %1 = add nsw i64 %0, 1
+  %arrayidx4 = getelementptr inbounds i32, i32* %x, i64 %1
+  store i32 %call, i32* %arrayidx4, align 4
+  %2 = add nsw i64 %0, 2
+  %arrayidx9 = getelementptr inbounds i32, i32* %x, i64 %2
+  store i32 %call, i32* %arrayidx9, align 4
+  %arrayidx6 = getelementptr inbounds i32, i32* %x, i64 %newmul
+  store i32 %call, i32* %arrayidx6, align 4
+  %3 = add nsw i64 %newmul, 1
+  %arrayidx7 = getelementptr inbounds i32, i32* %x, i64 %3
+  store i32 %call, i32* %arrayidx7, align 4
+  %4 = add nsw i64 %newmul, 2
+  %arrayidx8 = getelementptr inbounds i32, i32* %x, i64 %4
+  store i32 %call, i32* %arrayidx8, align 4
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond = icmp eq i64 %indvars.iv.next, 500
+  br i1 %exitcond, label %for.end, label %for.body
+
+; CHECK-LABEL: @multi2
+
+; CHECK:for.body:
+; CHECK:  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+; CHECK:  %0 = add i64 %indvars.iv, 3
+; CHECK:  %arrayidx = getelementptr inbounds i32, i32* %x, i64 %indvars.iv
+; CHECK:  store i32 %call, i32* %arrayidx, align 4
+; CHECK:  %arrayidx6 = getelementptr inbounds i32, i32* %x, i64 %0
+; CHECK:  store i32 %call, i32* %arrayidx6, align 4
+; CHECK:  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+; CHECK:  %exitcond2 = icmp eq i64 %indvars.iv, 1499
+; CHECK:  br i1 %exitcond2, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
+
+; void multi3(int *x) {
+;   y = foo(0)
+;   for (int i = 0; i < 500; ++i) {
+;     // Note: No zero index
+;     x[3*i+3] = y;
+;     x[3*i+4] = y;
+;     x[3*i+5] = y;
+;   }
+; }
+
+; Function Attrs: nounwind uwtable
+define void @multi3(i32* nocapture %x) #0 {
+entry:
+  %call = tail call i32 @foo(i32 0) #1
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %0 = mul nsw i64 %indvars.iv, 3
+  %x0 = add nsw i64 %0, 3
+  %add = add nsw i64 %indvars.iv, 1
+  %arrayidx = getelementptr inbounds i32, i32* %x, i64 %x0
+  store i32 %call, i32* %arrayidx, align 4
+  %1 = add nsw i64 %0, 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %x, i64 %1
+  store i32 %call, i32* %arrayidx4, align 4
+  %2 = add nsw i64 %0, 5
+  %arrayidx9 = getelementptr inbounds i32, i32* %x, i64 %2
+  store i32 %call, i32* %arrayidx9, align 4
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond = icmp eq i64 %indvars.iv.next, 500
+  br i1 %exitcond, label %for.end, label %for.body
+
+; CHECK-LABEL: @multi3
+; CHECK: for.body:
+; CHECK:   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+; CHECK:   %0 = add i64 %indvars.iv, 3
+; CHECK:   %arrayidx = getelementptr inbounds i32, i32* %x, i64 %0
+; CHECK:   store i32 %call, i32* %arrayidx, align 4
+; CHECK:   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+; CHECK:   %exitcond1 = icmp eq i64 %0, 1502
+; CHECK:   br i1 %exitcond1, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
+
+; int foo(int a);
+; void bar2(int *x, int y, int z) {
+;   for (int i = 0; i < 500; i += 3) {
+;     foo(i+y+i*z); // Slightly reordered instruction order
+;     foo(i+1+y+(i+1)*z);
+;     foo(i+2+y+(i+2)*z);
+;   }
+; }
+
+; Function Attrs: nounwind uwtable
+define void @bar2(i32* nocapture readnone %x, i32 %y, i32 %z) #0 {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.08 = phi i32 [ 0, %entry ], [ %add3, %for.body ]
+
+  %tmp1 = add i32 %i.08, %y
+  %tmp2 = mul i32 %i.08, %z
+  %tmp3 = add i32 %tmp2, %tmp1
+  %call = tail call i32 @foo(i32 %tmp3) #1
+
+  %add = add nsw i32 %i.08, 1
+  %tmp2a = mul i32 %add, %z
+  %tmp1a = add i32 %add, %y
+  %tmp3a = add i32 %tmp2a, %tmp1a
+  %calla = tail call i32 @foo(i32 %tmp3a) #1
+  
+  %add2 = add nsw i32 %i.08, 2
+  %tmp2b = mul i32 %add2, %z
+  %tmp1b = add i32 %add2, %y
+  %tmp3b = add i32 %tmp2b, %tmp1b
+  %callb = tail call i32 @foo(i32 %tmp3b) #1
+
+  %add3 = add nsw i32 %i.08, 3
+
+  %exitcond = icmp eq i32 %add3, 500
+  br i1 %exitcond, label %for.end, label %for.body
+
+; CHECK-LABEL: @bar2
+
+; CHECK: for.body:
+; CHECK: %indvar = phi i32 [ %indvar.next, %for.body ], [ 0, %entry ]
+; CHECK: %tmp1 = add i32 %indvar, %y
+; CHECK: %tmp2 = mul i32 %indvar, %z
+; CHECK: %tmp3 = add i32 %tmp2, %tmp1
+; CHECK: %call = tail call i32 @foo(i32 %tmp3) #1
+; CHECK: %indvar.next = add i32 %indvar, 1
+; CHECK: %exitcond1 = icmp eq i32 %indvar, 497
+; CHECK: br i1 %exitcond1, label %for.end, label %for.body
+
+; CHECK: ret
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
+
+%struct.s = type { i32, i32 }
+
+; Function Attrs: nounwind uwtable
+define void @gep1(%struct.s* nocapture %x) #0 {
+entry:
+  %call = tail call i32 @foo(i32 0) #1
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %0 = mul nsw i64 %indvars.iv, 3
+  %arrayidx = getelementptr inbounds %struct.s, %struct.s* %x, i64 %0, i32 0
+  store i32 %call, i32* %arrayidx, align 4
+  %1 = add nsw i64 %0, 1
+  %arrayidx4 = getelementptr inbounds %struct.s, %struct.s* %x, i64 %1, i32 0
+  store i32 %call, i32* %arrayidx4, align 4
+  %2 = add nsw i64 %0, 2
+  %arrayidx9 = getelementptr inbounds %struct.s, %struct.s* %x, i64 %2, i32 0
+  store i32 %call, i32* %arrayidx9, align 4
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond = icmp eq i64 %indvars.iv.next, 500
+  br i1 %exitcond, label %for.end, label %for.body
+
+; CHECK-LABEL: @gep1
+; This test is a crash test only.
+; CHECK: ret
+for.end:                                          ; preds = %for.body
+  ret void
+}
+
+
 attributes #0 = { nounwind uwtable }
 attributes #1 = { nounwind }
 
diff --git a/test/Transforms/LoopReroll/nonconst_lb.ll b/test/Transforms/LoopReroll/nonconst_lb.ll
index a45469bd2393..5effa42d07c4 100644
--- a/test/Transforms/LoopReroll/nonconst_lb.ll
+++ b/test/Transforms/LoopReroll/nonconst_lb.ll
@@ -17,28 +17,28 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %i.035 = phi i32 [ %add18, %for.body ], [ %m, %entry ]
-  %arrayidx = getelementptr inbounds i32* %B, i32 %i.035
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %B, i32 %i.035
+  %0 = load i32, i32* %arrayidx, align 4
   %mul = shl nsw i32 %0, 2
-  %arrayidx2 = getelementptr inbounds i32* %A, i32 %i.035
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i32 %i.035
   store i32 %mul, i32* %arrayidx2, align 4
   %add3 = add nsw i32 %i.035, 1
-  %arrayidx4 = getelementptr inbounds i32* %B, i32 %add3
-  %1 = load i32* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %B, i32 %add3
+  %1 = load i32, i32* %arrayidx4, align 4
   %mul5 = shl nsw i32 %1, 2
-  %arrayidx7 = getelementptr inbounds i32* %A, i32 %add3
+  %arrayidx7 = getelementptr inbounds i32, i32* %A, i32 %add3
   store i32 %mul5, i32* %arrayidx7, align 4
   %add8 = add nsw i32 %i.035, 2
-  %arrayidx9 = getelementptr inbounds i32* %B, i32 %add8
-  %2 = load i32* %arrayidx9, align 4
+  %arrayidx9 = getelementptr inbounds i32, i32* %B, i32 %add8
+  %2 = load i32, i32* %arrayidx9, align 4
   %mul10 = shl nsw i32 %2, 2
-  %arrayidx12 = getelementptr inbounds i32* %A, i32 %add8
+  %arrayidx12 = getelementptr inbounds i32, i32* %A, i32 %add8
   store i32 %mul10, i32* %arrayidx12, align 4
   %add13 = add nsw i32 %i.035, 3
-  %arrayidx14 = getelementptr inbounds i32* %B, i32 %add13
-  %3 = load i32* %arrayidx14, align 4
+  %arrayidx14 = getelementptr inbounds i32, i32* %B, i32 %add13
+  %3 = load i32, i32* %arrayidx14, align 4
   %mul15 = shl nsw i32 %3, 2
-  %arrayidx17 = getelementptr inbounds i32* %A, i32 %add13
+  %arrayidx17 = getelementptr inbounds i32, i32* %A, i32 %add13
   store i32 %mul15, i32* %arrayidx17, align 4
   %add18 = add nsw i32 %i.035, 4
   %cmp = icmp slt i32 %add18, %n
@@ -60,10 +60,10 @@ for.end:                                          ; preds = %for.body, %entry
 ; CHECK: for.body:                                         ; preds = %for.body, %for.body.preheader
 ; CHECK:   %indvar = phi i32 [ %indvar.next, %for.body ], [ 0, %for.body.preheader ]
 ; CHECK:   %6 = add i32 %m, %indvar
-; CHECK:   %arrayidx = getelementptr inbounds i32* %B, i32 %6
-; CHECK:   %7 = load i32* %arrayidx, align 4
+; CHECK:   %arrayidx = getelementptr inbounds i32, i32* %B, i32 %6
+; CHECK:   %7 = load i32, i32* %arrayidx, align 4
 ; CHECK:   %mul = shl nsw i32 %7, 2
-; CHECK:   %arrayidx2 = getelementptr inbounds i32* %A, i32 %6
+; CHECK:   %arrayidx2 = getelementptr inbounds i32, i32* %A, i32 %6
 ; CHECK:   store i32 %mul, i32* %arrayidx2, align 4
 ; CHECK:   %indvar.next = add i32 %indvar, 1
 ; CHECK:   %exitcond = icmp eq i32 %6, %5
@@ -88,34 +88,34 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %i.056 = phi i32 [ %add27, %for.body ], [ %rem, %entry ]
-  %arrayidx = getelementptr inbounds float* %dy, i32 %i.056
-  %0 = load float* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds float* %dx, i32 %i.056
-  %1 = load float* %arrayidx1, align 4
+  %arrayidx = getelementptr inbounds float, float* %dy, i32 %i.056
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx1 = getelementptr inbounds float, float* %dx, i32 %i.056
+  %1 = load float, float* %arrayidx1, align 4
   %mul = fmul float %1, %da
   %add = fadd float %0, %mul
   store float %add, float* %arrayidx, align 4
   %add3 = add nsw i32 %i.056, 1
-  %arrayidx4 = getelementptr inbounds float* %dy, i32 %add3
-  %2 = load float* %arrayidx4, align 4
-  %arrayidx6 = getelementptr inbounds float* %dx, i32 %add3
-  %3 = load float* %arrayidx6, align 4
+  %arrayidx4 = getelementptr inbounds float, float* %dy, i32 %add3
+  %2 = load float, float* %arrayidx4, align 4
+  %arrayidx6 = getelementptr inbounds float, float* %dx, i32 %add3
+  %3 = load float, float* %arrayidx6, align 4
   %mul7 = fmul float %3, %da
   %add8 = fadd float %2, %mul7
   store float %add8, float* %arrayidx4, align 4
   %add11 = add nsw i32 %i.056, 2
-  %arrayidx12 = getelementptr inbounds float* %dy, i32 %add11
-  %4 = load float* %arrayidx12, align 4
-  %arrayidx14 = getelementptr inbounds float* %dx, i32 %add11
-  %5 = load float* %arrayidx14, align 4
+  %arrayidx12 = getelementptr inbounds float, float* %dy, i32 %add11
+  %4 = load float, float* %arrayidx12, align 4
+  %arrayidx14 = getelementptr inbounds float, float* %dx, i32 %add11
+  %5 = load float, float* %arrayidx14, align 4
   %mul15 = fmul float %5, %da
   %add16 = fadd float %4, %mul15
   store float %add16, float* %arrayidx12, align 4
   %add19 = add nsw i32 %i.056, 3
-  %arrayidx20 = getelementptr inbounds float* %dy, i32 %add19
-  %6 = load float* %arrayidx20, align 4
-  %arrayidx22 = getelementptr inbounds float* %dx, i32 %add19
-  %7 = load float* %arrayidx22, align 4
+  %arrayidx20 = getelementptr inbounds float, float* %dy, i32 %add19
+  %6 = load float, float* %arrayidx20, align 4
+  %arrayidx22 = getelementptr inbounds float, float* %dx, i32 %add19
+  %7 = load float, float* %arrayidx22, align 4
   %mul23 = fmul float %7, %da
   %add24 = fadd float %6, %mul23
   store float %add24, float* %arrayidx20, align 4
@@ -140,10 +140,10 @@ for.end:                                          ; preds = %for.body, %entry
 ; CHECK: for.body:
 ; CHECK:   %indvar = phi i32 [ %indvar.next, %for.body ], [ 0, %for.body.preheader ]
 ; CHECK:   %6 = add i32 %rem, %indvar
-; CHECK:   %arrayidx = getelementptr inbounds float* %dy, i32 %6
-; CHECK:   %7 = load float* %arrayidx, align 4
-; CHECK:   %arrayidx1 = getelementptr inbounds float* %dx, i32 %6
-; CHECK:   %8 = load float* %arrayidx1, align 4
+; CHECK:   %arrayidx = getelementptr inbounds float, float* %dy, i32 %6
+; CHECK:   %7 = load float, float* %arrayidx, align 4
+; CHECK:   %arrayidx1 = getelementptr inbounds float, float* %dx, i32 %6
+; CHECK:   %8 = load float, float* %arrayidx1, align 4
 ; CHECK:   %mul = fmul float %8, %da
 ; CHECK:   %add = fadd float %7, %mul
 ; CHECK:   store float %add, float* %arrayidx, align 4
diff --git a/test/Transforms/LoopReroll/reduction.ll b/test/Transforms/LoopReroll/reduction.ll
index c9991c723ec6..191518514b8d 100644
--- a/test/Transforms/LoopReroll/reduction.ll
+++ b/test/Transforms/LoopReroll/reduction.ll
@@ -9,20 +9,20 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %r.029 = phi i32 [ 0, %entry ], [ %add12, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %x, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %x, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %r.029
   %1 = or i64 %indvars.iv, 1
-  %arrayidx3 = getelementptr inbounds i32* %x, i64 %1
-  %2 = load i32* %arrayidx3, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %x, i64 %1
+  %2 = load i32, i32* %arrayidx3, align 4
   %add4 = add nsw i32 %add, %2
   %3 = or i64 %indvars.iv, 2
-  %arrayidx7 = getelementptr inbounds i32* %x, i64 %3
-  %4 = load i32* %arrayidx7, align 4
+  %arrayidx7 = getelementptr inbounds i32, i32* %x, i64 %3
+  %4 = load i32, i32* %arrayidx7, align 4
   %add8 = add nsw i32 %add4, %4
   %5 = or i64 %indvars.iv, 3
-  %arrayidx11 = getelementptr inbounds i32* %x, i64 %5
-  %6 = load i32* %arrayidx11, align 4
+  %arrayidx11 = getelementptr inbounds i32, i32* %x, i64 %5
+  %6 = load i32, i32* %arrayidx11, align 4
   %add12 = add nsw i32 %add8, %6
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 4
   %7 = trunc i64 %indvars.iv.next to i32
@@ -34,8 +34,8 @@ for.body:                                         ; preds = %entry, %for.body
 ; CHECK: for.body:
 ; CHECK: %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %entry ]
 ; CHECK: %r.029 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-; CHECK: %arrayidx = getelementptr inbounds i32* %x, i64 %indvar
-; CHECK: %0 = load i32* %arrayidx, align 4
+; CHECK: %arrayidx = getelementptr inbounds i32, i32* %x, i64 %indvar
+; CHECK: %0 = load i32, i32* %arrayidx, align 4
 ; CHECK: %add = add nsw i32 %0, %r.029
 ; CHECK: %indvar.next = add i64 %indvar, 1
 ; CHECK: %exitcond = icmp eq i64 %indvar, 399
@@ -54,20 +54,20 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %r.029 = phi float [ 0.0, %entry ], [ %add12, %for.body ]
-  %arrayidx = getelementptr inbounds float* %x, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %add = fadd float %0, %r.029
   %1 = or i64 %indvars.iv, 1
-  %arrayidx3 = getelementptr inbounds float* %x, i64 %1
-  %2 = load float* %arrayidx3, align 4
+  %arrayidx3 = getelementptr inbounds float, float* %x, i64 %1
+  %2 = load float, float* %arrayidx3, align 4
   %add4 = fadd float %add, %2
   %3 = or i64 %indvars.iv, 2
-  %arrayidx7 = getelementptr inbounds float* %x, i64 %3
-  %4 = load float* %arrayidx7, align 4
+  %arrayidx7 = getelementptr inbounds float, float* %x, i64 %3
+  %4 = load float, float* %arrayidx7, align 4
   %add8 = fadd float %add4, %4
   %5 = or i64 %indvars.iv, 3
-  %arrayidx11 = getelementptr inbounds float* %x, i64 %5
-  %6 = load float* %arrayidx11, align 4
+  %arrayidx11 = getelementptr inbounds float, float* %x, i64 %5
+  %6 = load float, float* %arrayidx11, align 4
   %add12 = fadd float %add8, %6
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 4
   %7 = trunc i64 %indvars.iv.next to i32
@@ -79,8 +79,8 @@ for.body:                                         ; preds = %entry, %for.body
 ; CHECK: for.body:
 ; CHECK: %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %entry ]
 ; CHECK: %r.029 = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
-; CHECK: %arrayidx = getelementptr inbounds float* %x, i64 %indvar
-; CHECK: %0 = load float* %arrayidx, align 4
+; CHECK: %arrayidx = getelementptr inbounds float, float* %x, i64 %indvar
+; CHECK: %0 = load float, float* %arrayidx, align 4
 ; CHECK: %add = fadd float %0, %r.029
 ; CHECK: %indvar.next = add i64 %indvar, 1
 ; CHECK: %exitcond = icmp eq i64 %indvar, 399
@@ -92,5 +92,41 @@ for.end:                                          ; preds = %for.body
   ret float %add12
 }
 
+define i32 @foo_unusedphi(i32* nocapture readonly %x) #0 {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %r.029 = phi i32 [ 0, %entry ], [ %add12, %for.body ]
+  %arrayidx = getelementptr inbounds i32, i32* %x, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %add = add nsw i32 %0, %0
+  %1 = or i64 %indvars.iv, 1
+  %arrayidx3 = getelementptr inbounds i32, i32* %x, i64 %1
+  %2 = load i32, i32* %arrayidx3, align 4
+  %add4 = add nsw i32 %add, %2
+  %3 = or i64 %indvars.iv, 2
+  %arrayidx7 = getelementptr inbounds i32, i32* %x, i64 %3
+  %4 = load i32, i32* %arrayidx7, align 4
+  %add8 = add nsw i32 %add4, %4
+  %5 = or i64 %indvars.iv, 3
+  %arrayidx11 = getelementptr inbounds i32, i32* %x, i64 %5
+  %6 = load i32, i32* %arrayidx11, align 4
+  %add12 = add nsw i32 %add8, %6
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 4
+  %7 = trunc i64 %indvars.iv.next to i32
+  %cmp = icmp slt i32 %7, 400
+  br i1 %cmp, label %for.body, label %for.end
+
+; CHECK-LABEL: @foo_unusedphi
+; The above is just testing for a crash - no specific output expected.
+
+; CHECK: ret
+
+for.end:                                          ; preds = %for.body
+  ret i32 %add12
+}
+
 attributes #0 = { nounwind readonly uwtable }
 
diff --git a/test/Transforms/LoopRotate/PhiRename-1.ll b/test/Transforms/LoopRotate/PhiRename-1.ll
index a2247775ea78..6d75888d70db 100644
--- a/test/Transforms/LoopRotate/PhiRename-1.ll
+++ b/test/Transforms/LoopRotate/PhiRename-1.ll
@@ -36,59 +36,59 @@ entry:
 	%op = alloca %struct.operator*, align 4		; <%struct.operator**> [#uses=3]
 	store i32 %arity, i32* %arity_addr
 	store i32 0, i32* %c
-	%tmp1 = load %struct.list** @operators		; <%struct.list*> [#uses=1]
+	%tmp1 = load %struct.list*, %struct.list** @operators		; <%struct.list*> [#uses=1]
 	store %struct.list* %tmp1, %struct.list** %l
 	br label %bb21
 
 bb:		; preds = %bb21
-	%tmp3 = getelementptr %struct.list* %tmp22, i32 0, i32 0		; <i8**> [#uses=1]
-	%tmp4 = load i8** %tmp3		; <i8*> [#uses=1]
+	%tmp3 = getelementptr %struct.list, %struct.list* %tmp22, i32 0, i32 0		; <i8**> [#uses=1]
+	%tmp4 = load i8*, i8** %tmp3		; <i8*> [#uses=1]
 	%tmp45 = bitcast i8* %tmp4 to %struct.operator*		; <%struct.operator*> [#uses=1]
 	store %struct.operator* %tmp45, %struct.operator** %op
-	%tmp6 = load %struct.operator** %op		; <%struct.operator*> [#uses=1]
-	%tmp7 = getelementptr %struct.operator* %tmp6, i32 0, i32 5		; <i32*> [#uses=1]
-	%tmp8 = load i32* %tmp7		; <i32> [#uses=1]
-	%tmp9 = load i32* %arity_addr		; <i32> [#uses=1]
+	%tmp6 = load %struct.operator*, %struct.operator** %op		; <%struct.operator*> [#uses=1]
+	%tmp7 = getelementptr %struct.operator, %struct.operator* %tmp6, i32 0, i32 5		; <i32*> [#uses=1]
+	%tmp8 = load i32, i32* %tmp7		; <i32> [#uses=1]
+	%tmp9 = load i32, i32* %arity_addr		; <i32> [#uses=1]
 	icmp eq i32 %tmp8, %tmp9		; <i1>:0 [#uses=1]
 	zext i1 %0 to i8		; <i8>:1 [#uses=1]
 	icmp ne i8 %1, 0		; <i1>:2 [#uses=1]
 	br i1 %2, label %cond_true, label %cond_next
 
 cond_true:		; preds = %bb
-	%tmp10 = load %struct.operator** %op		; <%struct.operator*> [#uses=1]
-	%tmp11 = getelementptr %struct.operator* %tmp10, i32 0, i32 2		; <i32*> [#uses=1]
-	%tmp12 = load i32* %tmp11		; <i32> [#uses=1]
-	%tmp13 = load %struct.FILE** @outfile		; <%struct.FILE*> [#uses=1]
-	%tmp14 = getelementptr [11 x i8]* @str1, i32 0, i32 0		; <i8*> [#uses=1]
-	%tmp15 = call i32 (%struct.FILE*, i8*, ...)* @fprintf( %struct.FILE* %tmp13, i8* %tmp14, i32 %tmp12 )		; <i32> [#uses=0]
-	%tmp16 = load i32* %c		; <i32> [#uses=1]
+	%tmp10 = load %struct.operator*, %struct.operator** %op		; <%struct.operator*> [#uses=1]
+	%tmp11 = getelementptr %struct.operator, %struct.operator* %tmp10, i32 0, i32 2		; <i32*> [#uses=1]
+	%tmp12 = load i32, i32* %tmp11		; <i32> [#uses=1]
+	%tmp13 = load %struct.FILE*, %struct.FILE** @outfile		; <%struct.FILE*> [#uses=1]
+	%tmp14 = getelementptr [11 x i8], [11 x i8]* @str1, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp15 = call i32 (%struct.FILE*, i8*, ...) @fprintf( %struct.FILE* %tmp13, i8* %tmp14, i32 %tmp12 )		; <i32> [#uses=0]
+	%tmp16 = load i32, i32* %c		; <i32> [#uses=1]
 	%tmp17 = add i32 %tmp16, 1		; <i32> [#uses=1]
 	store i32 %tmp17, i32* %c
 	br label %cond_next
 
 cond_next:		; preds = %cond_true, %bb
-	%tmp19 = getelementptr %struct.list* %tmp22, i32 0, i32 1		; <%struct.list**> [#uses=1]
-	%tmp20 = load %struct.list** %tmp19		; <%struct.list*> [#uses=1]
+	%tmp19 = getelementptr %struct.list, %struct.list* %tmp22, i32 0, i32 1		; <%struct.list**> [#uses=1]
+	%tmp20 = load %struct.list*, %struct.list** %tmp19		; <%struct.list*> [#uses=1]
 	store %struct.list* %tmp20, %struct.list** %l
 	br label %bb21
 
 bb21:		; preds = %cond_next, %entry
         %l.in = phi %struct.list** [ @operators, %entry ], [ %tmp19, %cond_next ]
-	%tmp22 = load %struct.list** %l.in		; <%struct.list*> [#uses=1]
+	%tmp22 = load %struct.list*, %struct.list** %l.in		; <%struct.list*> [#uses=1]
 	icmp ne %struct.list* %tmp22, null		; <i1>:3 [#uses=1]
 	zext i1 %3 to i8		; <i8>:4 [#uses=1]
 	icmp ne i8 %4, 0		; <i1>:5 [#uses=1]
 	br i1 %5, label %bb, label %bb23
 
 bb23:		; preds = %bb21
-	%tmp24 = load i32* %c		; <i32> [#uses=1]
+	%tmp24 = load i32, i32* %c		; <i32> [#uses=1]
 	store i32 %tmp24, i32* %tmp
-	%tmp25 = load i32* %tmp		; <i32> [#uses=1]
+	%tmp25 = load i32, i32* %tmp		; <i32> [#uses=1]
 	store i32 %tmp25, i32* %retval
 	br label %return
 
 return:		; preds = %bb23
-	%retval26 = load i32* %retval		; <i32> [#uses=1]
+	%retval26 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval26
 }
 
diff --git a/test/Transforms/LoopRotate/PhiSelfReference-1.ll b/test/Transforms/LoopRotate/PhiSelfReference-1.ll
index aa1708e8475c..ed4944833913 100644
--- a/test/Transforms/LoopRotate/PhiSelfReference-1.ll
+++ b/test/Transforms/LoopRotate/PhiSelfReference-1.ll
@@ -28,7 +28,7 @@ bb243:		; preds = %bb307
 
 bb307:		; preds = %bb243, %bb52
 	%sx_addr.2.pn = phi float* [ %sx_addr.5, %bb243 ], [ null, %bb52 ]		; <float*> [#uses=1]
-	%sx_addr.5 = getelementptr float* %sx_addr.2.pn, i32 %incx		; <float*> [#uses=1]
+	%sx_addr.5 = getelementptr float, float* %sx_addr.2.pn, i32 %incx		; <float*> [#uses=1]
 	br i1 false, label %bb243, label %bb310
 
 bb310:		; preds = %bb307
diff --git a/test/Transforms/LoopRotate/alloca.ll b/test/Transforms/LoopRotate/alloca.ll
index fd217ea8dcf0..bbcfb39c3722 100644
--- a/test/Transforms/LoopRotate/alloca.ll
+++ b/test/Transforms/LoopRotate/alloca.ll
@@ -14,7 +14,7 @@ declare void @use(i8*)
 
 define void @test() {
 entry:
-  %end = load i16* @e
+  %end = load i16, i16* @e
   br label %loop
 
 loop:
diff --git a/test/Transforms/LoopRotate/basic.ll b/test/Transforms/LoopRotate/basic.ll
index 6b92a6ecac13..9c04fa28753e 100644
--- a/test/Transforms/LoopRotate/basic.ll
+++ b/test/Transforms/LoopRotate/basic.ll
@@ -13,7 +13,7 @@ entry:
 for.cond:                                         ; preds = %for.body, %entry
   %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %cmp = icmp slt i32 %i.0, 100
-  %arrayidx = getelementptr inbounds [20 x i32]* %array, i64 0, i64 0
+  %arrayidx = getelementptr inbounds [20 x i32], [20 x i32]* %array, i64 0, i64 0
   br i1 %cmp, label %for.body, label %for.end
 
 ; CHECK: for.body:
diff --git a/test/Transforms/LoopRotate/crash.ll b/test/Transforms/LoopRotate/crash.ll
index e95f9a1f350f..5e2b66d6803d 100644
--- a/test/Transforms/LoopRotate/crash.ll
+++ b/test/Transforms/LoopRotate/crash.ll
@@ -125,7 +125,7 @@ entry:
 	br label %bb15
 bb6:		; preds = %bb15
 	%gep.upgrd.1 = zext i32 %offset.1 to i64		; <i64> [#uses=1]
-	%tmp11 = getelementptr i8* %msg, i64 %gep.upgrd.1		; <i8*> [#uses=0]
+	%tmp11 = getelementptr i8, i8* %msg, i64 %gep.upgrd.1		; <i8*> [#uses=0]
 	br label %bb15
 bb15:		; preds = %bb6, %entry
 	%offset.1 = add i32 0, 1		; <i32> [#uses=2]
diff --git a/test/Transforms/LoopRotate/dbgvalue.ll b/test/Transforms/LoopRotate/dbgvalue.ll
index 846b366f2942..9bcca15ab551 100644
--- a/test/Transforms/LoopRotate/dbgvalue.ll
+++ b/test/Transforms/LoopRotate/dbgvalue.ll
@@ -15,9 +15,9 @@ tailrecurse:                                      ; preds = %if.then, %entry
   %x.tr = phi i32 [ %x, %entry ], [ %call, %if.then ]
   %y.tr = phi i32 [ %y, %entry ], [ %call9, %if.then ]
   %z.tr = phi i32 [ %z, %entry ], [ %call14, %if.then ]
-  tail call void @llvm.dbg.value(metadata i32 %x.tr, i64 0, metadata !6, metadata !{}), !dbg !7
-  tail call void @llvm.dbg.value(metadata i32 %y.tr, i64 0, metadata !8, metadata !{}), !dbg !9
-  tail call void @llvm.dbg.value(metadata i32 %z.tr, i64 0, metadata !10, metadata !{}), !dbg !11
+  tail call void @llvm.dbg.value(metadata i32 %x.tr, i64 0, metadata !6, metadata !DIExpression()), !dbg !7
+  tail call void @llvm.dbg.value(metadata i32 %y.tr, i64 0, metadata !8, metadata !DIExpression()), !dbg !9
+  tail call void @llvm.dbg.value(metadata i32 %z.tr, i64 0, metadata !10, metadata !DIExpression()), !dbg !11
   %cmp = icmp slt i32 %y.tr, %x.tr, !dbg !12
   br i1 %cmp, label %if.then, label %if.end, !dbg !12
 
@@ -61,18 +61,18 @@ for.cond:
   br i1 %cmp, label %for.end, label %for.body
 
 for.body:
-  %0 = load i64* @channelColumns, align 8
+  %0 = load i64, i64* @channelColumns, align 8
   %mul = mul i64 %0, %row
   %add = add i64 %mul, %i.0
-  %1 = load i8** @horzPlane, align 8
-  %arrayidx = getelementptr inbounds i8* %1, i64 %add
-  %2 = load i8* %arrayidx, align 1
+  %1 = load i8*, i8** @horzPlane, align 8
+  %arrayidx = getelementptr inbounds i8, i8* %1, i64 %add
+  %2 = load i8, i8* %arrayidx, align 1
   %tobool = icmp eq i8 %2, 0
   br i1 %tobool, label %for.inc, label %for.end
 
 for.inc:
   %dec = add i64 %i.0, -1
-  tail call void @llvm.dbg.value(metadata i64 %dec, i64 0, metadata !{!"undef"}, metadata !{})
+  tail call void @llvm.dbg.value(metadata i64 %dec, i64 0, metadata !DILocalVariable(tag: DW_TAG_auto_variable, scope: !0), metadata !DIExpression()), !dbg !DILocation(scope: !0)
   br label %for.cond
 
 for.end:
@@ -84,24 +84,24 @@ for.end:
 !llvm.module.flags = !{!20}
 !llvm.dbg.sp = !{!0}
 
-!0 = !{!"0x2e\00tak\00tak\00\0032\000\001\000\006\00256\000\000", !18, !1, !3, null, i32 (i32, i32, i32)* @tak, null, null, null} ; [ DW_TAG_subprogram ] [line 32] [def] [scope 0] [tak]
-!1 = !{!"0x29", !18} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 2.9 (trunk 125492)\001\00\000\00\000", !18, !19, !19, null, null, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !18, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "tak", line: 32, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !18, scope: !1, type: !3, function: i32 (i32, i32, i32)* @tak)
+!1 = !DIFile(filename: "/Volumes/Lalgate/cj/llvm/projects/llvm-test/SingleSource/Benchmarks/BenchmarkGame/recursive.c", directory: "/Volumes/Lalgate/cj/D/projects/llvm-test/SingleSource/Benchmarks/BenchmarkGame")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 2.9 (trunk 125492)", isOptimized: true, emissionKind: 0, file: !18, enums: !19, retainedTypes: !19)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ]
-!6 = !{!"0x101\00x\0032\000", !0, !1, !5} ; [ DW_TAG_arg_variable ]
-!7 = !MDLocation(line: 32, column: 13, scope: !0)
-!8 = !{!"0x101\00y\0032\000", !0, !1, !5} ; [ DW_TAG_arg_variable ]
-!9 = !MDLocation(line: 32, column: 20, scope: !0)
-!10 = !{!"0x101\00z\0032\000", !0, !1, !5} ; [ DW_TAG_arg_variable ]
-!11 = !MDLocation(line: 32, column: 27, scope: !0)
-!12 = !MDLocation(line: 33, column: 3, scope: !13)
-!13 = !{!"0xb\0032\0030\006", !18, !0} ; [ DW_TAG_lexical_block ]
-!14 = !MDLocation(line: 34, column: 5, scope: !15)
-!15 = !{!"0xb\0033\0014\007", !18, !13} ; [ DW_TAG_lexical_block ]
-!16 = !MDLocation(line: 36, column: 3, scope: !13)
-!17 = !MDLocation(line: 37, column: 1, scope: !13)
-!18 = !{!"/Volumes/Lalgate/cj/llvm/projects/llvm-test/SingleSource/Benchmarks/BenchmarkGame/recursive.c", !"/Volumes/Lalgate/cj/D/projects/llvm-test/SingleSource/Benchmarks/BenchmarkGame"}
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 32, arg: 0, scope: !0, file: !1, type: !5)
+!7 = !DILocation(line: 32, column: 13, scope: !0)
+!8 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "y", line: 32, arg: 0, scope: !0, file: !1, type: !5)
+!9 = !DILocation(line: 32, column: 20, scope: !0)
+!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "z", line: 32, arg: 0, scope: !0, file: !1, type: !5)
+!11 = !DILocation(line: 32, column: 27, scope: !0)
+!12 = !DILocation(line: 33, column: 3, scope: !13)
+!13 = distinct !DILexicalBlock(line: 32, column: 30, file: !18, scope: !0)
+!14 = !DILocation(line: 34, column: 5, scope: !15)
+!15 = distinct !DILexicalBlock(line: 33, column: 14, file: !18, scope: !13)
+!16 = !DILocation(line: 36, column: 3, scope: !13)
+!17 = !DILocation(line: 37, column: 1, scope: !13)
+!18 = !DIFile(filename: "/Volumes/Lalgate/cj/llvm/projects/llvm-test/SingleSource/Benchmarks/BenchmarkGame/recursive.c", directory: "/Volumes/Lalgate/cj/D/projects/llvm-test/SingleSource/Benchmarks/BenchmarkGame")
 !19 = !{i32 0}
-!20 = !{i32 1, !"Debug Info Version", i32 2}
+!20 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/LoopRotate/indirectbr.ll b/test/Transforms/LoopRotate/indirectbr.ll
index 9c82aa883463..2ccc54697aee 100644
--- a/test/Transforms/LoopRotate/indirectbr.ll
+++ b/test/Transforms/LoopRotate/indirectbr.ll
@@ -12,7 +12,7 @@ while.body:                                       ; preds = %while.cond
   br label %indirectgoto
 
 run_opcode:                                       ; preds = %indirectgoto
-  %tmp276 = load i8* undef                        ; <i8> [#uses=1]
+  %tmp276 = load i8, i8* undef                        ; <i8> [#uses=1]
   br label %indirectgoto
 
 if.else295:                                       ; preds = %divide_late
diff --git a/test/Transforms/LoopRotate/multiple-exits.ll b/test/Transforms/LoopRotate/multiple-exits.ll
index cc8738e479d4..f31ed7f1c5b5 100644
--- a/test/Transforms/LoopRotate/multiple-exits.ll
+++ b/test/Transforms/LoopRotate/multiple-exits.ll
@@ -21,8 +21,8 @@ for.cond1:                                        ; preds = %for.cond, %land.rhs
 
 land.rhs:                                         ; preds = %for.cond1
   %conv = zext i32 %i.1 to i64
-  %arrayidx = getelementptr inbounds [100 x i32]* %a, i64 0, i64 %conv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* %a, i64 0, i64 %conv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add i32 %0, %sum.1
   %cmp4 = icmp ugt i32 %add, 1000
   %inc = add i32 %i.1, 1
diff --git a/test/Transforms/LoopRotate/nosimplifylatch.ll b/test/Transforms/LoopRotate/nosimplifylatch.ll
index 8e858b4dfcc3..07ff6643c6d1 100644
--- a/test/Transforms/LoopRotate/nosimplifylatch.ll
+++ b/test/Transforms/LoopRotate/nosimplifylatch.ll
@@ -18,13 +18,13 @@ for.cond:                                         ; preds = %for.inc, %entry
   br i1 %lnot.i, label %for.end, label %for.body
 
 for.body:                                         ; preds = %for.cond
-  %0 = load i32* %coerce.val.ip9, align 4
-  %1 = load i32* %__value_, align 4
+  %0 = load i32, i32* %coerce.val.ip9, align 4
+  %1 = load i32, i32* %__value_, align 4
   %cmp = icmp eq i32 %0, %1
   br i1 %cmp, label %for.end, label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %incdec.ptr.i = getelementptr inbounds i32* %coerce.val.ip9, i64 1
+  %incdec.ptr.i = getelementptr inbounds i32, i32* %coerce.val.ip9, i64 1
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond, %for.body
diff --git a/test/Transforms/LoopRotate/phi-duplicate.ll b/test/Transforms/LoopRotate/phi-duplicate.ll
index 86a4f2a475fa..46ee5961ba54 100644
--- a/test/Transforms/LoopRotate/phi-duplicate.ll
+++ b/test/Transforms/LoopRotate/phi-duplicate.ll
@@ -13,13 +13,13 @@ for.cond:                                         ; preds = %for.body, %entry
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %arrayidx = getelementptr inbounds double* %G, i64 %j.0 ; <double*> [#uses=1]
-  %tmp3 = load double* %arrayidx                  ; <double> [#uses=1]
+  %arrayidx = getelementptr inbounds double, double* %G, i64 %j.0 ; <double*> [#uses=1]
+  %tmp3 = load double, double* %arrayidx                  ; <double> [#uses=1]
   %sub = sub i64 %j.0, 1                          ; <i64> [#uses=1]
-  %arrayidx6 = getelementptr inbounds double* %G, i64 %sub ; <double*> [#uses=1]
-  %tmp7 = load double* %arrayidx6                 ; <double> [#uses=1]
+  %arrayidx6 = getelementptr inbounds double, double* %G, i64 %sub ; <double*> [#uses=1]
+  %tmp7 = load double, double* %arrayidx6                 ; <double> [#uses=1]
   %add = fadd double %tmp3, %tmp7                 ; <double> [#uses=1]
-  %arrayidx10 = getelementptr inbounds double* %G, i64 %j.0 ; <double*> [#uses=1]
+  %arrayidx10 = getelementptr inbounds double, double* %G, i64 %j.0 ; <double*> [#uses=1]
   store double %add, double* %arrayidx10
   %inc = add nsw i64 %j.0, 1                      ; <i64> [#uses=1]
   br label %for.cond
diff --git a/test/Transforms/LoopRotate/pr22337.ll b/test/Transforms/LoopRotate/pr22337.ll
new file mode 100644
index 000000000000..03e804b775e4
--- /dev/null
+++ b/test/Transforms/LoopRotate/pr22337.ll
@@ -0,0 +1,24 @@
+; RUN: opt < %s -loop-rotate -S | FileCheck %s
+
+@a = external global i8, align 4
+@tmp = global i8* @a
+
+define void @f() {
+; CHECK-LABEL: define void @f(
+; CHECK: getelementptr i8, i8* @a, i32 0
+entry:
+  br label %for.preheader
+
+for.preheader:
+  br i1 undef, label %if.then8, label %for.body
+
+for.body:
+  br i1 undef, label %if.end, label %if.then8
+
+if.end:
+  %arrayidx = getelementptr i8, i8* @a, i32 0
+  br label %for.preheader
+
+if.then8:
+  unreachable
+}
diff --git a/test/Transforms/LoopRotate/simplifylatch.ll b/test/Transforms/LoopRotate/simplifylatch.ll
index 62e5b1ae11d5..215622fe3028 100644
--- a/test/Transforms/LoopRotate/simplifylatch.ll
+++ b/test/Transforms/LoopRotate/simplifylatch.ll
@@ -13,8 +13,8 @@ entry:
 bb:		; preds = %bb4, %entry
 	%mode.0 = phi i8 [ 0, %entry ], [ %indvar.next, %bb4 ]		; <i8> [#uses=4]
 	zext i8 %mode.0 to i32		; <i32>:1 [#uses=1]
-	getelementptr [4 x i32]* @mode_table, i32 0, i32 %1		; <i32*>:2 [#uses=1]
-	load i32* %2, align 4		; <i32>:3 [#uses=1]
+	getelementptr [4 x i32], [4 x i32]* @mode_table, i32 0, i32 %1		; <i32*>:2 [#uses=1]
+	load i32, i32* %2, align 4		; <i32>:3 [#uses=1]
 	icmp eq i32 %3, %0		; <i1>:4 [#uses=1]
 	br i1 %4, label %bb1, label %bb2
 
@@ -39,8 +39,8 @@ declare i32 @fegetround()
 declare void @raise_exception() noreturn
 
 ;CHECK: for.body.lr.ph:
-;CHECK-NEXT:  %arrayidx1 = getelementptr inbounds i8* %CurPtr, i64 0
-;CHECK-NEXT:  %0 = load i8* %arrayidx1, align 1
+;CHECK-NEXT:  %arrayidx1 = getelementptr inbounds i8, i8* %CurPtr, i64 0
+;CHECK-NEXT:  %0 = load i8, i8* %arrayidx1, align 1
 ;CHECK-NEXT:  %conv2 = sext i8 %0 to i32
 ;CHECK-NEXT:  br label %for.body
 
@@ -55,11 +55,11 @@ for.cond:					  ; preds = %for.inc, %entry
 
 for.body:					  ; preds = %for.cond
   %idxprom = zext i32 %i.0 to i64
-  %arrayidx = getelementptr inbounds i8* %CurPtr, i64 %idxprom
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %CurPtr, i64 %idxprom
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = sext i8 %0 to i32
-  %arrayidx1 = getelementptr inbounds i8* %CurPtr, i64 0
-  %1 = load i8* %arrayidx1, align 1
+  %arrayidx1 = getelementptr inbounds i8, i8* %CurPtr, i64 0
+  %1 = load i8, i8* %arrayidx1, align 1
   %conv2 = sext i8 %1 to i32
   %cmp3 = icmp ne i32 %conv, %conv2
   br i1 %cmp3, label %return, label %for.inc
diff --git a/test/Transforms/LoopSimplify/2003-08-15-PreheadersFail.ll b/test/Transforms/LoopSimplify/2003-08-15-PreheadersFail.ll
index 73f0813285ba..4a69067f5f18 100644
--- a/test/Transforms/LoopSimplify/2003-08-15-PreheadersFail.ll
+++ b/test/Transforms/LoopSimplify/2003-08-15-PreheadersFail.ll
@@ -8,29 +8,29 @@ target datalayout = "e-p:32:32"
 define i32 @_yylex() {
 	br label %loopentry.0
 loopentry.0:		; preds = %else.26, %0
-	store i32* getelementptr ([16386 x i32]* @yy_state_buf, i64 0, i64 0), i32** @yy_state_ptr
-	%tmp.35 = load i32** @yy_state_ptr		; <i32*> [#uses=2]
-	%inc.0 = getelementptr i32* %tmp.35, i64 1		; <i32*> [#uses=1]
+	store i32* getelementptr ([16386 x i32], [16386 x i32]* @yy_state_buf, i64 0, i64 0), i32** @yy_state_ptr
+	%tmp.35 = load i32*, i32** @yy_state_ptr		; <i32*> [#uses=2]
+	%inc.0 = getelementptr i32, i32* %tmp.35, i64 1		; <i32*> [#uses=1]
 	store i32* %inc.0, i32** @yy_state_ptr
-	%tmp.36 = load i32* null		; <i32> [#uses=1]
+	%tmp.36 = load i32, i32* null		; <i32> [#uses=1]
 	store i32 %tmp.36, i32* %tmp.35
 	br label %loopexit.2
 loopexit.2:		; preds = %else.26, %loopexit.2, %loopentry.0
 	store i8* null, i8** null
-	%tmp.91 = load i32* null		; <i32> [#uses=1]
+	%tmp.91 = load i32, i32* null		; <i32> [#uses=1]
 	%tmp.92 = sext i32 %tmp.91 to i64		; <i64> [#uses=1]
-	%tmp.93 = getelementptr [787 x i16]* @yy_base, i64 0, i64 %tmp.92		; <i16*> [#uses=1]
-	%tmp.94 = load i16* %tmp.93		; <i16> [#uses=1]
+	%tmp.93 = getelementptr [787 x i16], [787 x i16]* @yy_base, i64 0, i64 %tmp.92		; <i16*> [#uses=1]
+	%tmp.94 = load i16, i16* %tmp.93		; <i16> [#uses=1]
 	%tmp.95 = icmp ne i16 %tmp.94, 4394		; <i1> [#uses=1]
 	br i1 %tmp.95, label %loopexit.2, label %yy_find_action
 yy_find_action:		; preds = %else.26, %loopexit.2
 	br label %loopentry.3
 loopentry.3:		; preds = %then.9, %shortcirc_done.0, %yy_find_action
-	%tmp.105 = load i32* @yy_lp		; <i32> [#uses=1]
+	%tmp.105 = load i32, i32* @yy_lp		; <i32> [#uses=1]
 	%tmp.106 = icmp ne i32 %tmp.105, 0		; <i1> [#uses=1]
 	br i1 %tmp.106, label %shortcirc_next.0, label %shortcirc_done.0
 shortcirc_next.0:		; preds = %loopentry.3
-	%tmp.114 = load i16* null		; <i16> [#uses=1]
+	%tmp.114 = load i16, i16* null		; <i16> [#uses=1]
 	%tmp.115 = sext i16 %tmp.114 to i32		; <i32> [#uses=1]
 	%tmp.116 = icmp slt i32 0, %tmp.115		; <i1> [#uses=1]
 	br label %shortcirc_done.0
@@ -38,7 +38,7 @@ shortcirc_done.0:		; preds = %shortcirc_next.0, %loopentry.3
 	%shortcirc_val.0 = phi i1 [ false, %loopentry.3 ], [ %tmp.116, %shortcirc_next.0 ]		; <i1> [#uses=1]
 	br i1 %shortcirc_val.0, label %else.0, label %loopentry.3
 else.0:		; preds = %shortcirc_done.0
-	%tmp.144 = load i32* null		; <i32> [#uses=1]
+	%tmp.144 = load i32, i32* null		; <i32> [#uses=1]
 	%tmp.145 = and i32 %tmp.144, 8192		; <i32> [#uses=1]
 	%tmp.146 = icmp ne i32 %tmp.145, 0		; <i1> [#uses=1]
 	br i1 %tmp.146, label %then.9, label %else.26
diff --git a/test/Transforms/LoopSimplify/2003-12-10-ExitBlocksProblem.ll b/test/Transforms/LoopSimplify/2003-12-10-ExitBlocksProblem.ll
index fb39f05c6dbb..32b632220d3c 100644
--- a/test/Transforms/LoopSimplify/2003-12-10-ExitBlocksProblem.ll
+++ b/test/Transforms/LoopSimplify/2003-12-10-ExitBlocksProblem.ll
@@ -14,15 +14,15 @@ entry:
 	store i32 123, i32* @G
 	br label %loopentry.i
 loopentry.i:		; preds = %endif.1.i, %entry
-	%tmp.0.i = load i32* @G		; <i32> [#uses=1]
+	%tmp.0.i = load i32, i32* @G		; <i32> [#uses=1]
 	%tmp.1.i = icmp eq i32 %tmp.0.i, 123		; <i1> [#uses=1]
 	br i1 %tmp.1.i, label %Out.i, label %endif.0.i
 endif.0.i:		; preds = %loopentry.i
-	%tmp.3.i = load i32* @G		; <i32> [#uses=1]
+	%tmp.3.i = load i32, i32* @G		; <i32> [#uses=1]
 	%tmp.4.i = icmp eq i32 %tmp.3.i, 126		; <i1> [#uses=1]
 	br i1 %tmp.4.i, label %ExitBlock.i, label %endif.1.i
 endif.1.i:		; preds = %endif.0.i
-	%tmp.6.i = load i32* @G		; <i32> [#uses=1]
+	%tmp.6.i = load i32, i32* @G		; <i32> [#uses=1]
 	%inc.i = add i32 %tmp.6.i, 1		; <i32> [#uses=1]
 	store i32 %inc.i, i32* @G
 	br label %loopentry.i
@@ -30,7 +30,7 @@ Out.i:		; preds = %loopentry.i
 	store i32 0, i32* @G
 	br label %ExitBlock.i
 ExitBlock.i:		; preds = %Out.i, %endif.0.i
-	%tmp.7.i = load i32* @G		; <i32> [#uses=1]
+	%tmp.7.i = load i32, i32* @G		; <i32> [#uses=1]
 	ret i32 %tmp.7.i
 }
 
diff --git a/test/Transforms/LoopSimplify/2011-12-14-LandingpadHeader.ll b/test/Transforms/LoopSimplify/2011-12-14-LandingpadHeader.ll
index 173a5825767b..39471eb0d11a 100644
--- a/test/Transforms/LoopSimplify/2011-12-14-LandingpadHeader.ll
+++ b/test/Transforms/LoopSimplify/2011-12-14-LandingpadHeader.ll
@@ -12,7 +12,7 @@ entry:
 ; CHECK-NEXT: landingpad
 ; CHECK: br label %catch
 
-; CHECK: catch.split-lp:
+; CHECK: catch.preheader.split-lp:
 ; CHECK-NEXT: landingpad
 ; CHECK: br label %catch
 
diff --git a/test/Transforms/LoopSimplify/ashr-crash.ll b/test/Transforms/LoopSimplify/ashr-crash.ll
index c58903d49d55..b5cc1449cec2 100644
--- a/test/Transforms/LoopSimplify/ashr-crash.ll
+++ b/test/Transforms/LoopSimplify/ashr-crash.ll
@@ -51,10 +51,10 @@ for.cond1:                                        ; preds = %for.cond, %for.body
   br i1 %cmp2, label %for.body3, label %for.inc7
 
 for.body3:                                        ; preds = %for.cond1
-  %0 = load i32* @c, align 4
+  %0 = load i32, i32* @c, align 4
   %cmp4 = icmp sge i32 %storemerge1, %0
   %conv = zext i1 %cmp4 to i32
-  %1 = load i32* @d, align 4
+  %1 = load i32, i32* @d, align 4
   %add = add nsw i32 %conv, %1
   %sext = shl i32 %add, 16
   %conv6 = ashr exact i32 %sext, 16
@@ -63,7 +63,7 @@ for.body3:                                        ; preds = %for.cond1
   br label %for.cond1
 
 for.inc7:                                         ; preds = %for.cond1
-  %2 = load i32* @d, align 4
+  %2 = load i32, i32* @d, align 4
   %inc8 = add nsw i32 %2, 1
   br label %for.cond
 
diff --git a/test/Transforms/LoopSimplify/dup-preds.ll b/test/Transforms/LoopSimplify/dup-preds.ll
index 3d1f1499b11c..c9253fa51a65 100644
--- a/test/Transforms/LoopSimplify/dup-preds.ll
+++ b/test/Transforms/LoopSimplify/dup-preds.ll
@@ -28,7 +28,7 @@ for.body305:                                      ; preds = %for.body305, %if.th
   br label %for.body305
 
 for.body344:                                      ; preds = %for.body344, %for.body276.lr.ph, %for.body276.lr.ph
-  %indvar = phi i64 [ %indvar.next, %for.body344 ], [ 0, %for.body276.lr.ph ]
+  %indvar = phi i64 [ %indvar.next, %for.body344 ], [ 0, %for.body276.lr.ph ], [ 0, %for.body276.lr.ph ]
   %indvars.iv552 = phi i64 [ %indvars.iv.next553, %for.body344 ], [ 0, %for.body276.lr.ph ], [ 0, %for.body276.lr.ph ]
   %indvars.iv.next553 = add nuw nsw i64 %indvars.iv552, 1
   %indvar.next = add i64 %indvar, 1
diff --git a/test/Transforms/LoopSimplify/merge-exits.ll b/test/Transforms/LoopSimplify/merge-exits.ll
index 9678148c3570..5cdf81487784 100644
--- a/test/Transforms/LoopSimplify/merge-exits.ll
+++ b/test/Transforms/LoopSimplify/merge-exits.ll
@@ -15,18 +15,18 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 define float @test1(float* %pTmp1, float* %peakWeight, i32 %bandEdgeIndex) nounwind {
 entry:
-	%t0 = load float* %peakWeight, align 4
+	%t0 = load float, float* %peakWeight, align 4
 	br label %bb1
 
 bb:		; preds = %bb2
 	%t1 = sext i32 %hiPart.0 to i64
-	%t2 = getelementptr float* %pTmp1, i64 %t1
-	%t3 = load float* %t2, align 4
+	%t2 = getelementptr float, float* %pTmp1, i64 %t1
+	%t3 = load float, float* %t2, align 4
 	%t4 = fadd float %t3, %distERBhi.0
 	%t5 = add i32 %hiPart.0, 1
 	%t6 = sext i32 %t5 to i64
-	%t7 = getelementptr float* %peakWeight, i64 %t6
-	%t8 = load float* %t7, align 4
+	%t7 = getelementptr float, float* %peakWeight, i64 %t6
+	%t8 = load float, float* %t7, align 4
 	%t9 = fadd float %t8, %peakCount.0
 	br label %bb1
 
diff --git a/test/Transforms/LoopSimplify/notify-scev.ll b/test/Transforms/LoopSimplify/notify-scev.ll
index ee8e2eec9b3f..059b589abefa 100644
--- a/test/Transforms/LoopSimplify/notify-scev.ll
+++ b/test/Transforms/LoopSimplify/notify-scev.ll
@@ -60,7 +60,7 @@ for.inc172.us:
   br i1 undef, label %for.cond142.preheader.us, label %for.end174.us
 
 for.body145.us:
-  %arrayidx163.us = getelementptr inbounds %struct.Params* undef, i64 0, i32 0, i64 %idxprom130, i64 %idxprom146.us
+  %arrayidx163.us = getelementptr inbounds %struct.Params, %struct.Params* undef, i64 0, i32 0, i64 %idxprom130, i64 %idxprom146.us
   br i1 undef, label %for.body145.us, label %for.inc172.us
 
 for.cond142.preheader.us:
diff --git a/test/Transforms/LoopSimplify/phi-node-simplify.ll b/test/Transforms/LoopSimplify/phi-node-simplify.ll
index 8eb63d9111a7..6536acb7b038 100644
--- a/test/Transforms/LoopSimplify/phi-node-simplify.ll
+++ b/test/Transforms/LoopSimplify/phi-node-simplify.ll
@@ -12,29 +12,29 @@ entry:
 	br label %loopentry.1
 loopentry.1:		; preds = %loopexit.1, %entry
 	%indvar20 = phi i32 [ 0, %entry ], [ %indvar.next21, %loopexit.1 ]		; <i32> [#uses=1]
-	%a.1 = phi i32* [ getelementptr ([3000000 x i32]* @A, i32 0, i32 0), %entry ], [ %inc.0, %loopexit.1 ]		; <i32*> [#uses=1]
+	%a.1 = phi i32* [ getelementptr ([3000000 x i32], [3000000 x i32]* @A, i32 0, i32 0), %entry ], [ %inc.0, %loopexit.1 ]		; <i32*> [#uses=1]
 	br label %no_exit.2
 no_exit.2:		; preds = %loopexit.2, %no_exit.2, %loopentry.1
 	%a.0.4.ph = phi i32* [ %a.1, %loopentry.1 ], [ %inc.0, %loopexit.2 ], [ %a.0.4.ph, %no_exit.2 ]		; <i32*> [#uses=3]
-	%b.1.4.ph = phi i32* [ getelementptr ([20000 x i32]* @B, i32 0, i32 0), %loopentry.1 ], [ %inc.1, %loopexit.2 ], [ %b.1.4.ph, %no_exit.2 ]		; <i32*> [#uses=3]
+	%b.1.4.ph = phi i32* [ getelementptr ([20000 x i32], [20000 x i32]* @B, i32 0, i32 0), %loopentry.1 ], [ %inc.1, %loopexit.2 ], [ %b.1.4.ph, %no_exit.2 ]		; <i32*> [#uses=3]
 	%indvar17 = phi i32 [ 0, %loopentry.1 ], [ %indvar.next18, %loopexit.2 ], [ %indvar17, %no_exit.2 ]		; <i32> [#uses=2]
 	%indvar = phi i32 [ %indvar.next, %no_exit.2 ], [ 0, %loopexit.2 ], [ 0, %loopentry.1 ]		; <i32> [#uses=5]
 	%b.1.4.rec = bitcast i32 %indvar to i32		; <i32> [#uses=1]
 	%gep.upgrd.1 = zext i32 %indvar to i64		; <i64> [#uses=1]
-	%c.2.4 = getelementptr [100 x i32]* @C, i32 0, i64 %gep.upgrd.1		; <i32*> [#uses=1]
+	%c.2.4 = getelementptr [100 x i32], [100 x i32]* @C, i32 0, i64 %gep.upgrd.1		; <i32*> [#uses=1]
 	%gep.upgrd.2 = zext i32 %indvar to i64		; <i64> [#uses=1]
-	%a.0.4 = getelementptr i32* %a.0.4.ph, i64 %gep.upgrd.2		; <i32*> [#uses=1]
+	%a.0.4 = getelementptr i32, i32* %a.0.4.ph, i64 %gep.upgrd.2		; <i32*> [#uses=1]
 	%gep.upgrd.3 = zext i32 %indvar to i64		; <i64> [#uses=1]
-	%b.1.4 = getelementptr i32* %b.1.4.ph, i64 %gep.upgrd.3		; <i32*> [#uses=1]
+	%b.1.4 = getelementptr i32, i32* %b.1.4.ph, i64 %gep.upgrd.3		; <i32*> [#uses=1]
 	%inc.0.rec = add i32 %b.1.4.rec, 1		; <i32> [#uses=2]
-	%inc.0 = getelementptr i32* %a.0.4.ph, i32 %inc.0.rec		; <i32*> [#uses=2]
-	%tmp.13 = load i32* %a.0.4		; <i32> [#uses=1]
-	%inc.1 = getelementptr i32* %b.1.4.ph, i32 %inc.0.rec		; <i32*> [#uses=1]
-	%tmp.15 = load i32* %b.1.4		; <i32> [#uses=1]
-	%tmp.18 = load i32* %c.2.4		; <i32> [#uses=1]
+	%inc.0 = getelementptr i32, i32* %a.0.4.ph, i32 %inc.0.rec		; <i32*> [#uses=2]
+	%tmp.13 = load i32, i32* %a.0.4		; <i32> [#uses=1]
+	%inc.1 = getelementptr i32, i32* %b.1.4.ph, i32 %inc.0.rec		; <i32*> [#uses=1]
+	%tmp.15 = load i32, i32* %b.1.4		; <i32> [#uses=1]
+	%tmp.18 = load i32, i32* %c.2.4		; <i32> [#uses=1]
 	%tmp.16 = mul i32 %tmp.15, %tmp.13		; <i32> [#uses=1]
 	%tmp.19 = mul i32 %tmp.16, %tmp.18		; <i32> [#uses=1]
-	%tmp.20 = load i32* @Z		; <i32> [#uses=1]
+	%tmp.20 = load i32, i32* @Z		; <i32> [#uses=1]
 	%tmp.21 = add i32 %tmp.19, %tmp.20		; <i32> [#uses=1]
 	store i32 %tmp.21, i32* @Z
 	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=2]
diff --git a/test/Transforms/LoopSimplify/preserve-scev.ll b/test/Transforms/LoopSimplify/preserve-scev.ll
index 89626b2af518..f6fa8afc56b5 100644
--- a/test/Transforms/LoopSimplify/preserve-scev.ll
+++ b/test/Transforms/LoopSimplify/preserve-scev.ll
@@ -1,6 +1,9 @@
 ; RUN: opt -S < %s -indvars | opt -analyze -iv-users | grep "%cmp = icmp slt i32" | grep "= {%\.ph,+,1}<%for.cond>"
 ; PR8079
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
 ; LoopSimplify should invalidate indvars when splitting out the
 ; inner loop.
 
@@ -15,7 +18,7 @@ for.cond:                                         ; preds = %if.then5, %if.end,
   %0 = phi i32 [ 0, %entry ], [ %add, %if.end ], [ %add, %if.then5 ]
   %add = add i32 %0, 1
   %cmp = icmp slt i32 %0, 1
-  %tmp1 = load i32* @maxStat, align 4
+  %tmp1 = load i32, i32* @maxStat, align 4
   br i1 %cmp, label %for.body, label %for.cond14.preheader
 
 for.cond14.preheader:                             ; preds = %for.cond
@@ -39,7 +42,7 @@ for.body18:                                       ; preds = %for.body18, %for.co
   %i13.027 = phi i32 [ %1, %for.body18 ], [ 0, %for.cond14.preheader ]
   call void @foo() nounwind
   %1 = add nsw i32 %i13.027, 1
-  %tmp16 = load i32* @maxStat, align 4
+  %tmp16 = load i32, i32* @maxStat, align 4
   %cmp17 = icmp slt i32 %1, %tmp16
   br i1 %cmp17, label %for.body18, label %return
 
diff --git a/test/Transforms/LoopStrengthReduce/2005-08-15-AddRecIV.ll b/test/Transforms/LoopStrengthReduce/2005-08-15-AddRecIV.ll
index 1f08a4367bde..7ee1e63ced0f 100644
--- a/test/Transforms/LoopStrengthReduce/2005-08-15-AddRecIV.ll
+++ b/test/Transforms/LoopStrengthReduce/2005-08-15-AddRecIV.ll
@@ -48,9 +48,9 @@ loopexit.3:		; preds = %loopentry.3
 loopentry.4:		; preds = %loopentry.4, %loopexit.3
 	%indvar340 = phi i32 [ 0, %loopexit.3 ], [ %indvar.next341, %loopentry.4 ]		; <i32> [#uses=2]
 	%tmp. = add i32 %indvar340, %indvar342		; <i32> [#uses=1]
-	%tmp.526 = load i32** null		; <i32*> [#uses=1]
+	%tmp.526 = load i32*, i32** null		; <i32*> [#uses=1]
 	%gep.upgrd.1 = zext i32 %tmp. to i64		; <i64> [#uses=1]
-	%tmp.528 = getelementptr i32* %tmp.526, i64 %gep.upgrd.1		; <i32*> [#uses=1]
+	%tmp.528 = getelementptr i32, i32* %tmp.526, i64 %gep.upgrd.1		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp.528
 	%indvar.next341 = add i32 %indvar340, 1		; <i32> [#uses=1]
 	br label %loopentry.4
diff --git a/test/Transforms/LoopStrengthReduce/2005-08-17-OutOfLoopVariant.ll b/test/Transforms/LoopStrengthReduce/2005-08-17-OutOfLoopVariant.ll
index f1c523ae6c60..3e52dff2a876 100644
--- a/test/Transforms/LoopStrengthReduce/2005-08-17-OutOfLoopVariant.ll
+++ b/test/Transforms/LoopStrengthReduce/2005-08-17-OutOfLoopVariant.ll
@@ -6,7 +6,7 @@ loopentry.1.outer:
 	br label %loopentry.1
 loopentry.1:		; preds = %loopentry.1, %loopentry.1.outer
 	%i.3 = phi i32 [ 0, %loopentry.1.outer ], [ %i.3.be, %loopentry.1 ]		; <i32> [#uses=2]
-	%tmp.390 = load i32* null		; <i32> [#uses=1]
+	%tmp.390 = load i32, i32* null		; <i32> [#uses=1]
 	%tmp.392 = mul i32 %tmp.390, %j.2.1.ph		; <i32> [#uses=1]
 	%tmp.394 = add i32 %tmp.392, %i.3		; <i32> [#uses=1]
 	%i.3.be = add i32 %i.3, 1		; <i32> [#uses=1]
diff --git a/test/Transforms/LoopStrengthReduce/2007-04-23-UseIterator.ll b/test/Transforms/LoopStrengthReduce/2007-04-23-UseIterator.ll
index 8c2cfaf32107..44f98011b258 100644
--- a/test/Transforms/LoopStrengthReduce/2007-04-23-UseIterator.ll
+++ b/test/Transforms/LoopStrengthReduce/2007-04-23-UseIterator.ll
@@ -24,7 +24,7 @@ bb16:		; preds = %cond_next102, %bb16.preheader
 
 cond_next102:		; preds = %bb16
 	%tmp138145.rec = add i32 %ABC.2146.0.rec, 3		; <i32> [#uses=1]
-	%tmp138145 = getelementptr i8* %ABC, i32 %tmp138145.rec		; <i8*> [#uses=4]
+	%tmp138145 = getelementptr i8, i8* %ABC, i32 %tmp138145.rec		; <i8*> [#uses=4]
 	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=1]
 	switch i8 0, label %bb129.loopexit [
 		 i8 0, label %UnifiedReturnBlock.loopexit
diff --git a/test/Transforms/LoopStrengthReduce/2008-08-13-CmpStride.ll b/test/Transforms/LoopStrengthReduce/2008-08-13-CmpStride.ll
index ce56bd31018c..394969c9935a 100644
--- a/test/Transforms/LoopStrengthReduce/2008-08-13-CmpStride.ll
+++ b/test/Transforms/LoopStrengthReduce/2008-08-13-CmpStride.ll
@@ -1,5 +1,9 @@
 ; RUN: opt < %s -loop-reduce -S | grep add | count 2
 ; PR 2662
+
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
 @g_3 = common global i16 0		; <i16*> [#uses=2]
 @"\01LC" = internal constant [4 x i8] c"%d\0A\00"		; <[4 x i8]*> [#uses=1]
 
@@ -22,9 +26,9 @@ return:		; preds = %bb
 define i32 @main() nounwind {
 entry:
 	tail call void @func_1( ) nounwind
-	load volatile i16* @g_3, align 2		; <i16>:0 [#uses=1]
+	load volatile i16, i16* @g_3, align 2		; <i16>:0 [#uses=1]
 	zext i16 %0 to i32		; <i32>:1 [#uses=1]
-	tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), i32 %1 ) nounwind		; <i32>:2 [#uses=0]
+	tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), i32 %1 ) nounwind		; <i32>:2 [#uses=0]
 	ret i32 0
 }
 
diff --git a/test/Transforms/LoopStrengthReduce/2008-09-09-Overflow.ll b/test/Transforms/LoopStrengthReduce/2008-09-09-Overflow.ll
index 1ee6b5cdf18e..5904434e14ff 100644
--- a/test/Transforms/LoopStrengthReduce/2008-09-09-Overflow.ll
+++ b/test/Transforms/LoopStrengthReduce/2008-09-09-Overflow.ll
@@ -1,5 +1,9 @@
 ; RUN: opt < %s -loop-reduce -S | grep phi | count 2
 ; PR 2779
+
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
 @g_19 = common global i32 0		; <i32*> [#uses=3]
 @"\01LC" = internal constant [4 x i8] c"%d\0A\00"		; <[4 x i8]*> [#uses=1]
 
@@ -21,7 +25,7 @@ bb:		; preds = %bb, %entry
 	%indvar = phi i16 [ 0, %entry ], [ %indvar.next, %bb ]		; <i16> [#uses=2]
 	%tmp = sub i16 0, %indvar		; <i16> [#uses=1]
 	%tmp27 = trunc i16 %tmp to i8		; <i8> [#uses=1]
-	load i32* @g_19, align 4		; <i32>:0 [#uses=2]
+	load i32, i32* @g_19, align 4		; <i32>:0 [#uses=2]
 	add i32 %0, 1		; <i32>:1 [#uses=1]
 	store i32 %1, i32* @g_19, align 4
 	trunc i32 %0 to i8		; <i8>:2 [#uses=1]
@@ -40,8 +44,8 @@ return:		; preds = %bb
 define i32 @main() nounwind {
 entry:
 	tail call void @func_1( ) nounwind
-	load i32* @g_19, align 4		; <i32>:0 [#uses=1]
-	tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), i32 %0 ) nounwind		; <i32>:1 [#uses=0]
+	load i32, i32* @g_19, align 4		; <i32>:0 [#uses=1]
+	tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i32 0), i32 %0 ) nounwind		; <i32>:1 [#uses=0]
 	ret i32 0
 }
 
diff --git a/test/Transforms/LoopStrengthReduce/2009-01-13-nonconstant-stride-outside-loop.ll b/test/Transforms/LoopStrengthReduce/2009-01-13-nonconstant-stride-outside-loop.ll
index b2cf818dc45d..c287b10e6946 100644
--- a/test/Transforms/LoopStrengthReduce/2009-01-13-nonconstant-stride-outside-loop.ll
+++ b/test/Transforms/LoopStrengthReduce/2009-01-13-nonconstant-stride-outside-loop.ll
@@ -26,14 +26,14 @@ bb1.i:		; preds = %bb.i2, %entry
 	br i1 %0, label %bb2.i3, label %nactive_heaps.exit
 
 bb2.i3:		; preds = %bb1.i
-	%1 = load %struct.obj** null, align 4		; <%struct.obj*> [#uses=1]
+	%1 = load %struct.obj*, %struct.obj** null, align 4		; <%struct.obj*> [#uses=1]
 	%2 = icmp eq %struct.obj* %1, null		; <i1> [#uses=1]
 	br i1 %2, label %nactive_heaps.exit, label %bb.i2
 
 nactive_heaps.exit:		; preds = %bb2.i3, %bb1.i
-	%3 = load i32* @heap_size, align 4		; <i32> [#uses=1]
+	%3 = load i32, i32* @heap_size, align 4		; <i32> [#uses=1]
 	%4 = mul i32 %3, %m.0.i		; <i32> [#uses=1]
 	%5 = sub i32 %4, 0		; <i32> [#uses=1]
-	%6 = tail call i32 (i8*, i8*, ...)* @sprintf(i8* null, i8* getelementptr ([39 x i8]* @"\01LC85", i32 0, i32 0), i32 %m.0.i, i32 0, i32 %5, i32 0) nounwind		; <i32> [#uses=0]
+	%6 = tail call i32 (i8*, i8*, ...) @sprintf(i8* null, i8* getelementptr ([39 x i8], [39 x i8]* @"\01LC85", i32 0, i32 0), i32 %m.0.i, i32 0, i32 %5, i32 0) nounwind		; <i32> [#uses=0]
 	ret %struct.obj* null
 }
diff --git a/test/Transforms/LoopStrengthReduce/2009-04-28-no-reduce-mul.ll b/test/Transforms/LoopStrengthReduce/2009-04-28-no-reduce-mul.ll
index 002a878b7b24..8e890e84bccf 100644
--- a/test/Transforms/LoopStrengthReduce/2009-04-28-no-reduce-mul.ll
+++ b/test/Transforms/LoopStrengthReduce/2009-04-28-no-reduce-mul.ll
@@ -21,7 +21,7 @@ bb2:		; preds = %bb4, %bb2, %bb4.thread
 	%0 = trunc i32 %j.0.reg2mem.0 to i8		; <i8> [#uses=1]
 	%1 = sext i8 %0 to i32		; <i32> [#uses=1]
 	%2 = mul i32 %1, %i.0.reg2mem.0.ph		; <i32> [#uses=1]
-	%3 = getelementptr [32 x [256 x i32]]* @table, i32 0, i32 %i.0.reg2mem.0.ph, i32 %j.0.reg2mem.0		; <i32*> [#uses=1]
+	%3 = getelementptr [32 x [256 x i32]], [32 x [256 x i32]]* @table, i32 0, i32 %i.0.reg2mem.0.ph, i32 %j.0.reg2mem.0		; <i32*> [#uses=1]
 	store i32 %2, i32* %3, align 4
 	%indvar.next = add i32 %j.0.reg2mem.0, 1		; <i32> [#uses=2]
 	%exitcond = icmp eq i32 %indvar.next, 256		; <i1> [#uses=1]
@@ -33,7 +33,7 @@ bb4:		; preds = %bb2
 	br i1 %exitcond10, label %bb5, label %bb2
 
 bb5:		; preds = %bb4
-	%4 = load i32* getelementptr ([32 x [256 x i32]]* @table, i32 0, i32 9, i32 132), align 16		; <i32> [#uses=1]
+	%4 = load i32, i32* getelementptr ([32 x [256 x i32]], [32 x [256 x i32]]* @table, i32 0, i32 9, i32 132), align 16		; <i32> [#uses=1]
 	%5 = icmp eq i32 %4, -1116		; <i1> [#uses=1]
 	br i1 %5, label %bb7, label %bb6
 
diff --git a/test/Transforms/LoopStrengthReduce/2011-07-19-CritEdgeBreakCrash.ll b/test/Transforms/LoopStrengthReduce/2011-07-19-CritEdgeBreakCrash.ll
index b9bd7c9bf4a3..cf549fc38acd 100644
--- a/test/Transforms/LoopStrengthReduce/2011-07-19-CritEdgeBreakCrash.ll
+++ b/test/Transforms/LoopStrengthReduce/2011-07-19-CritEdgeBreakCrash.ll
@@ -24,12 +24,12 @@ H_MPZ_LBL:                                        ; preds = %indirectgoto
 while.cond.i:                                     ; preds = %while.body.i15795, %if.then.i15791
   %phi = phi i64 [ %tmp20916, %while.body.i15795 ], [ 0, %H_MPZ_LBL ]
   %tmp20916 = add i64 %phi, 1
-  %incdec.ptr.i15793 = getelementptr i64* %pc.0.lcssa.i1610719352, i64 %tmp20916
+  %incdec.ptr.i15793 = getelementptr i64, i64* %pc.0.lcssa.i1610719352, i64 %tmp20916
   %boo2 = call i1 @foo()
   br i1 %boo2, label %indirectgoto, label %while.body.i15795
 
 while.body.i15795:                                ; preds = %while.cond.i
-  %tmp20.i = load i64* %incdec.ptr.i15793, align 8
+  %tmp20.i = load i64, i64* %incdec.ptr.i15793, align 8
   %boo1 = call i1 @foo()
   br i1 %boo1, label %while.cond.i, label %body_failed
 
diff --git a/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll b/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll
index ccf8ebdd5d13..5588995a8ce8 100644
--- a/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll
+++ b/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll
@@ -4,6 +4,10 @@
 
 target triple = "x86-apple-darwin"
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+
 ; Verify that identical edges are merged. rdar://problem/6453893
 ; CHECK-LABEL: @test1(
 ; CHECK: bb89:
@@ -16,7 +20,7 @@ entry:
 loop:
   %rec = phi i32 [ %next, %loop ], [ 0, %entry ]
   %next = add i32 %rec, 1
-  %tmp75 = getelementptr i8* null, i32 %next
+  %tmp75 = getelementptr i8, i8* null, i32 %next
   br i1 false, label %loop, label %loopexit
 
 loopexit:
@@ -53,7 +57,7 @@ entry:
 loop:
   %rec = phi i32 [ %next, %loop ], [ 0, %entry ]
   %next = add i32 %rec, 1
-  %tmp75 = getelementptr i8* null, i32 %next
+  %tmp75 = getelementptr i8, i8* null, i32 %next
   br i1 false, label %loop, label %loopexit
 
 loopexit:
diff --git a/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll b/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll
index 83963e3126da..cc8226e12589 100644
--- a/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll
+++ b/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll
@@ -5,6 +5,10 @@
 
 target triple = "x86-apple-darwin"
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+
 ; CHECK-LABEL: @test(
 ; multiplies are hoisted out of the loop
 ; CHECK: while.body.lr.ph:
@@ -17,10 +21,10 @@ target triple = "x86-apple-darwin"
 ; CHECK: phi
 ; CHECK: phi
 ; CHECK-NOT: phi
-; CHECK: bitcast float* {{.*}} to i8*
-; CHECK: bitcast float* {{.*}} to i8*
-; CHECK: getelementptr i8*
-; CHECK: getelementptr i8*
+; CHECK: bitcast float* {{.*}} to i1*
+; CHECK: bitcast float* {{.*}} to i1*
+; CHECK: getelementptr i1, i1*
+; CHECK: getelementptr i1, i1*
 
 define float @test(float* nocapture %A, float* nocapture %B, i32 %N, i32 %IA, i32 %IB) nounwind uwtable readonly ssp {
 entry:
@@ -37,12 +41,12 @@ while.body:                                       ; preds = %while.body.lr.ph, %
   %B.addr.04 = phi float* [ %B, %while.body.lr.ph ], [ %add.ptr3, %while.body ]
   %N.addr.03 = phi i32 [ %N, %while.body.lr.ph ], [ %sub, %while.body ]
   %Sum0.02 = phi float [ 0.000000e+00, %while.body.lr.ph ], [ %add, %while.body ]
-  %0 = load float* %A.addr.05, align 4
-  %1 = load float* %B.addr.04, align 4
+  %0 = load float, float* %A.addr.05, align 4
+  %1 = load float, float* %B.addr.04, align 4
   %mul = fmul float %0, %1
   %add = fadd float %Sum0.02, %mul
-  %add.ptr = getelementptr inbounds float* %A.addr.05, i64 %idx.ext
-  %add.ptr3 = getelementptr inbounds float* %B.addr.04, i64 %idx.ext2
+  %add.ptr = getelementptr inbounds float, float* %A.addr.05, i64 %idx.ext
+  %add.ptr3 = getelementptr inbounds float, float* %B.addr.04, i64 %idx.ext2
   %sub = add nsw i32 %N.addr.03, -1
   %cmp = icmp sgt i32 %sub, 0
   br i1 %cmp, label %while.body, label %while.end
diff --git a/test/Transforms/LoopStrengthReduce/2011-10-13-SCEVChain.ll b/test/Transforms/LoopStrengthReduce/2011-10-13-SCEVChain.ll
index 484fefaad413..a61de24370f5 100644
--- a/test/Transforms/LoopStrengthReduce/2011-10-13-SCEVChain.ll
+++ b/test/Transforms/LoopStrengthReduce/2011-10-13-SCEVChain.ll
@@ -95,14 +95,14 @@ bb1:
   %t15 = icmp ugt i32 %n15, -4
   %m15 = select i1 %t15, i32 %n15, i32 -4
   %a16 = add i32 %m15, %a15
-  %gep = getelementptr i8* %base, i32 %a16
+  %gep = getelementptr i8, i8* %base, i32 %a16
   %ofs = add i32 %a16, 4
-  %limit = getelementptr i8* %base, i32 %ofs
+  %limit = getelementptr i8, i8* %base, i32 %ofs
   br label %loop
 
 loop:
   %iv = phi i8* [ %gep, %bb1 ], [ %inc, %loop ]
-  %inc = getelementptr inbounds i8* %iv, i64 1
+  %inc = getelementptr inbounds i8, i8* %iv, i64 1
   %exitcond = icmp eq i8* %inc, %limit
   br i1 %exitcond, label %loop, label %exit
 
diff --git a/test/Transforms/LoopStrengthReduce/2011-10-14-IntPtr.ll b/test/Transforms/LoopStrengthReduce/2011-10-14-IntPtr.ll
index 068b716651d8..fe9f8cb2de4c 100644
--- a/test/Transforms/LoopStrengthReduce/2011-10-14-IntPtr.ll
+++ b/test/Transforms/LoopStrengthReduce/2011-10-14-IntPtr.ll
@@ -22,6 +22,6 @@ for.end:                                          ; preds = %for.end.critedge, %
 for.body83:                                       ; preds = %for.body83, %for.end
   %ptr.0157 = phi i8* [ %add.ptr96, %for.body83 ], [ null, %for.end ]
   store i8 undef, i8* %ptr.0157, align 1
-  %add.ptr96 = getelementptr inbounds i8* %ptr.0157, i32 %cond
+  %add.ptr96 = getelementptr inbounds i8, i8* %ptr.0157, i32 %cond
   br label %for.body83
 }
diff --git a/test/Transforms/LoopStrengthReduce/2011-12-19-PostincQuadratic.ll b/test/Transforms/LoopStrengthReduce/2011-12-19-PostincQuadratic.ll
index 6c128feb541c..317b0b0b2939 100644
--- a/test/Transforms/LoopStrengthReduce/2011-12-19-PostincQuadratic.ll
+++ b/test/Transforms/LoopStrengthReduce/2011-12-19-PostincQuadratic.ll
@@ -15,7 +15,7 @@ target triple = "i386-unknown-freebsd10.0"
 ;   Inner recurrence:
 ; CHECK: %lsr.iv = phi i32
 ;   Outer step (relative to inner recurrence):
-; CHECK: %scevgep = getelementptr i1* %{{.*}}, i32 %lsr.iv
+; CHECK: %scevgep = getelementptr i1, i1* %{{.*}}, i32 %lsr.iv
 ;   Outer use:
 ; CHECK: %lsr.iv3 = phi [121 x i32]* [ %lsr.iv1, %for.body43.preheader ]
 define void @vb() nounwind {
@@ -32,8 +32,8 @@ for.body7:
 for.body43:
   %bf.459 = phi i32 [ %inc44, %for.body43 ], [ %t1, %for.body7 ]
   %inc44 = add nsw i32 %bf.459, 1
-  %arrayidx45 = getelementptr inbounds [121 x i32]* @b, i32 0, i32 %bf.459
-  %t2 = load i32* %arrayidx45, align 4
+  %arrayidx45 = getelementptr inbounds [121 x i32], [121 x i32]* @b, i32 0, i32 %bf.459
+  %t2 = load i32, i32* %arrayidx45, align 4
   br label %for.body43
 }
 
diff --git a/test/Transforms/LoopStrengthReduce/2012-01-02-nopreheader.ll b/test/Transforms/LoopStrengthReduce/2012-01-02-nopreheader.ll
index 87dd39730ec1..d8aa26402f72 100644
--- a/test/Transforms/LoopStrengthReduce/2012-01-02-nopreheader.ll
+++ b/test/Transforms/LoopStrengthReduce/2012-01-02-nopreheader.ll
@@ -35,7 +35,7 @@ bb7.lr.ph.us:                                     ; preds = %bb9.us, %bb8.prehea
 bb7.us:                                           ; preds = %bb7.lr.ph.us, %bb7.us
   %j.01.us = phi i32 [ 0, %bb7.lr.ph.us ], [ %1, %bb7.us ]
   %tmp31 = add i32 %tmp30, %j.01.us
-  %scevgep9 = getelementptr float* %a, i32 %tmp31
+  %scevgep9 = getelementptr float, float* %a, i32 %tmp31
   store float undef, float* %scevgep9, align 1
   %1 = add nsw i32 %j.01.us, 1
   indirectbr i8* undef, [label %bb9.us, label %bb7.us]
@@ -74,7 +74,7 @@ bb8.preheader:                                    ; preds = %bb9, %bb3
 
 bb7:                                              ; preds = %bb8.preheader, %bb7
   %indvar = phi i32 [ 0, %bb8.preheader ], [ %indvar.next, %bb7 ]
-  %scevgep = getelementptr [200 x i32]* %Array2, i32 %tmp26, i32 %indvar
+  %scevgep = getelementptr [200 x i32], [200 x i32]* %Array2, i32 %tmp26, i32 %indvar
   store i32 undef, i32* %scevgep, align 4
   %indvar.next = add i32 %indvar, 1
   indirectbr i8* undef, [label %bb9, label %bb7]
diff --git a/test/Transforms/LoopStrengthReduce/2012-01-16-nopreheader.ll b/test/Transforms/LoopStrengthReduce/2012-01-16-nopreheader.ll
index 94a037ec28eb..7f1eed03a713 100644
--- a/test/Transforms/LoopStrengthReduce/2012-01-16-nopreheader.ll
+++ b/test/Transforms/LoopStrengthReduce/2012-01-16-nopreheader.ll
@@ -48,7 +48,7 @@ while.cond238.preheader:                          ; preds = %lor.lhs.false227, %
 while.cond238:                                    ; preds = %land.rhs243, %while.cond238.preheader
   %1 = phi i64 [ %indvar.next15, %land.rhs243 ], [ 0, %while.cond238.preheader ]
   %tmp36 = add i64 %tmp16, %1
-  %s.3 = getelementptr i8* %s.1, i64 %tmp36
+  %s.3 = getelementptr i8, i8* %s.1, i64 %tmp36
   %cmp241 = icmp ult i8* %s.3, %end
   indirectbr i8* undef, [label %land.rhs243, label %while.end256]
 
@@ -75,7 +75,7 @@ if.end340:                                        ; preds = %while.end334
   indirectbr i8* undef, [label %PREMATURE, label %if.end348]
 
 if.end348:                                        ; preds = %if.end340
-  %incdec.ptr356 = getelementptr inbounds i8* undef, i64 2
+  %incdec.ptr356 = getelementptr inbounds i8, i8* undef, i64 2
   indirectbr i8* undef, [label %while.cond179]
 
 if.else386:                                       ; preds = %if.else
diff --git a/test/Transforms/LoopStrengthReduce/2012-03-15-nopreheader.ll b/test/Transforms/LoopStrengthReduce/2012-03-15-nopreheader.ll
index 5fa3838c8297..62064cb78813 100644
--- a/test/Transforms/LoopStrengthReduce/2012-03-15-nopreheader.ll
+++ b/test/Transforms/LoopStrengthReduce/2012-03-15-nopreheader.ll
@@ -34,8 +34,8 @@ lor.lhs.false184:                                 ; preds = %lor.lhs.false177
 for.cond:                                         ; preds = %for.inc, %lor.lhs.false184, %if.end152
   %indvar65 = phi i64 [ %indvar.next66, %for.inc ], [ 0, %lor.lhs.false184 ], [ 0, %if.end152 ]
   %tmp128 = add i64 %0, %indvar65
-  %s.4 = getelementptr i8* %cmd, i64 %tmp128
-  %tmp195 = load i8* %s.4, align 1
+  %s.4 = getelementptr i8, i8* %cmd, i64 %tmp128
+  %tmp195 = load i8, i8* %s.4, align 1
   indirectbr i8* undef, [label %return, label %land.rhs198]
 
 land.rhs198:                                      ; preds = %for.cond
diff --git a/test/Transforms/LoopStrengthReduce/2012-03-26-constexpr.ll b/test/Transforms/LoopStrengthReduce/2012-03-26-constexpr.ll
index c9b11a9feed0..ce6161cb1b45 100644
--- a/test/Transforms/LoopStrengthReduce/2012-03-26-constexpr.ll
+++ b/test/Transforms/LoopStrengthReduce/2012-03-26-constexpr.ll
@@ -10,11 +10,11 @@ target datalayout = "e-p:64:64:64-n32:64"
 
 define internal fastcc void @someFunction(%struct.this_structure_s.0.5* nocapture %scratch, i32 %stage, i32 %cbSize) nounwind {
 entry:
-  %0 = getelementptr inbounds %struct.this_structure_s.0.5* %scratch, i32 0, i32 4, i32 %stage
-  %1 = load i8** %0, align 4
-  %2 = getelementptr inbounds %struct.this_structure_s.0.5* %scratch, i32 0, i32 5, i32 %stage
-  %3 = load i8** %2, align 4
-  %4 = getelementptr inbounds %struct.this_structure_s.0.5* %scratch, i32 0, i32 2, i32 0, i32 0
+  %0 = getelementptr inbounds %struct.this_structure_s.0.5, %struct.this_structure_s.0.5* %scratch, i32 0, i32 4, i32 %stage
+  %1 = load i8*, i8** %0, align 4
+  %2 = getelementptr inbounds %struct.this_structure_s.0.5, %struct.this_structure_s.0.5* %scratch, i32 0, i32 5, i32 %stage
+  %3 = load i8*, i8** %2, align 4
+  %4 = getelementptr inbounds %struct.this_structure_s.0.5, %struct.this_structure_s.0.5* %scratch, i32 0, i32 2, i32 0, i32 0
   %tmp11 = shl i32 %stage, 1
   %tmp1325 = or i32 %tmp11, 1
   br label %__label_D_1608
@@ -22,18 +22,18 @@ entry:
 __label_D_1608:                                   ; preds = %__label_D_1608, %entry
   %i.12 = phi i32 [ 0, %entry ], [ %10, %__label_D_1608 ]
   %tmp = shl i32 %i.12, 2
-  %lvar_g.13 = getelementptr i32* %4, i32 %tmp
+  %lvar_g.13 = getelementptr i32, i32* %4, i32 %tmp
   %tmp626 = or i32 %tmp, 1
-  %scevgep = getelementptr i32* %4, i32 %tmp626
+  %scevgep = getelementptr i32, i32* %4, i32 %tmp626
   %tmp727 = or i32 %tmp, 2
-  %scevgep8 = getelementptr i32* %4, i32 %tmp727
+  %scevgep8 = getelementptr i32, i32* %4, i32 %tmp727
   %tmp928 = or i32 %tmp, 3
-  %scevgep10 = getelementptr i32* %4, i32 %tmp928
-  %scevgep12 = getelementptr %struct.this_structure_s.0.5* %scratch, i32 0, i32 9, i32 %tmp11, i32 %i.12
-  %scevgep14 = getelementptr %struct.this_structure_s.0.5* %scratch, i32 0, i32 9, i32 %tmp1325, i32 %i.12
-  %5 = load i8* %scevgep12, align 1
+  %scevgep10 = getelementptr i32, i32* %4, i32 %tmp928
+  %scevgep12 = getelementptr %struct.this_structure_s.0.5, %struct.this_structure_s.0.5* %scratch, i32 0, i32 9, i32 %tmp11, i32 %i.12
+  %scevgep14 = getelementptr %struct.this_structure_s.0.5, %struct.this_structure_s.0.5* %scratch, i32 0, i32 9, i32 %tmp1325, i32 %i.12
+  %5 = load i8, i8* %scevgep12, align 1
   %6 = sext i8 %5 to i32
-  %7 = load i8* %scevgep14, align 1
+  %7 = load i8, i8* %scevgep14, align 1
   %8 = sext i8 %7 to i32
   store i32 0, i32* %lvar_g.13, align 4
   store i32 %8, i32* %scevgep, align 4
diff --git a/test/Transforms/LoopStrengthReduce/2012-07-13-ExpandUDiv.ll b/test/Transforms/LoopStrengthReduce/2012-07-13-ExpandUDiv.ll
index ea1d65b1652e..80095c3ac154 100644
--- a/test/Transforms/LoopStrengthReduce/2012-07-13-ExpandUDiv.ll
+++ b/test/Transforms/LoopStrengthReduce/2012-07-13-ExpandUDiv.ll
@@ -17,12 +17,12 @@ target triple = "x86_64-apple-darwin"
 define i32 @main() nounwind uwtable ssp {
 entry:
   %l_2 = alloca [1 x i32], align 4
-  %arrayidx = getelementptr inbounds [1 x i32]* %l_2, i64 0, i64 0
+  %arrayidx = getelementptr inbounds [1 x i32], [1 x i32]* %l_2, i64 0, i64 0
   store i32 0, i32* %arrayidx, align 4
-  %tmp = load i32* @g_3, align 4
+  %tmp = load i32, i32* @g_3, align 4
   %idxprom = sext i32 %tmp to i64
-  %arrayidx1 = getelementptr inbounds [1 x i32]* %l_2, i64 0, i64 %idxprom
-  %tmp1 = load i32* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds [1 x i32], [1 x i32]* %l_2, i64 0, i64 %idxprom
+  %tmp1 = load i32, i32* %arrayidx1, align 4
   %conv.i.i = and i32 %tmp1, 65535
   %tobool.i.i.i = icmp ne i32 %tmp, 0
   br label %codeRepl
diff --git a/test/Transforms/LoopStrengthReduce/2012-07-18-LimitReassociate.ll b/test/Transforms/LoopStrengthReduce/2012-07-18-LimitReassociate.ll
index 9524be3ceee0..aaac868dfd28 100644
--- a/test/Transforms/LoopStrengthReduce/2012-07-18-LimitReassociate.ll
+++ b/test/Transforms/LoopStrengthReduce/2012-07-18-LimitReassociate.ll
@@ -1,5 +1,4 @@
-; RUN: opt -loop-reduce -disable-output -debug-only=loop-reduce < %s 2> %t
-; RUN: FileCheck %s < %t
+; RUN: opt -loop-reduce -disable-output -debug-only=loop-reduce < %s 2>&1 | FileCheck %s
 ; REQUIRES: asserts
 ;
 ; PR13361: LSR + SCEV "hangs" on reasonably sized test with sequence of loops
@@ -18,6 +17,10 @@
 ; CHECK-NOT:reg
 ; CHECK: Filtering for use
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+
 %struct.snork = type { %struct.fuga, i32, i32, i32, i32, i32, i32 }
 %struct.fuga = type { %struct.gork, i64 }
 %struct.gork = type { i8*, i32, i32, %struct.noot* }
@@ -44,18 +47,18 @@ bb:
   br i1 %tmp4, label %bb6, label %bb5
 
 bb5:                                              ; preds = %bb
-  tail call void (...)* @snork(i8* getelementptr inbounds ([52 x i8]* @global1, i64 0, i64 0), i32 2021) nounwind
-  tail call void (...)* @snork(i8* getelementptr inbounds (%struct.jim* @global3, i64 0, i32 3, i64 1), i32 -2146631418) nounwind
+  tail call void (...) @snork(i8* getelementptr inbounds ([52 x i8], [52 x i8]* @global1, i64 0, i64 0), i32 2021) nounwind
+  tail call void (...) @snork(i8* getelementptr inbounds (%struct.jim, %struct.jim* @global3, i64 0, i32 3, i64 1), i32 -2146631418) nounwind
   unreachable
 
 bb6:                                              ; preds = %bb
-  tail call void @zot(i8* getelementptr inbounds (%struct.jim* @global3, i64 0, i32 5, i64 0), i8* getelementptr inbounds (%struct.jim* @global3, i64 0, i32 3, i64 1), i64 undef, i32 1, i1 false) nounwind
-  %tmp7 = getelementptr inbounds %struct.jim* @global3, i64 0, i32 5, i64 undef
+  tail call void @zot(i8* getelementptr inbounds (%struct.jim, %struct.jim* @global3, i64 0, i32 5, i64 0), i8* getelementptr inbounds (%struct.jim, %struct.jim* @global3, i64 0, i32 3, i64 1), i64 undef, i32 1, i1 false) nounwind
+  %tmp7 = getelementptr inbounds %struct.jim, %struct.jim* @global3, i64 0, i32 5, i64 undef
   store i8 0, i8* %tmp7, align 1
   %tmp8 = add nsw i32 0, 1
   %tmp9 = sext i32 %tmp8 to i64
   %tmp10 = add i64 %tmp9, 1
-  %tmp11 = getelementptr inbounds %struct.jim* @global3, i64 0, i32 3, i64 %tmp10
+  %tmp11 = getelementptr inbounds %struct.jim, %struct.jim* @global3, i64 0, i32 3, i64 %tmp10
   %tmp12 = sub i64 2047, %tmp9
   %tmp13 = icmp eq i32 undef, 1
   br i1 %tmp13, label %bb14, label %bb15
@@ -76,8 +79,8 @@ bb17:                                             ; preds = %bb26, %bb15
   br i1 %tmp21, label %bb22, label %bb32
 
 bb22:                                             ; preds = %bb17
-  %tmp23 = getelementptr inbounds %struct.jim* @global3, i64 0, i32 3, i64 0
-  %tmp24 = load i8* %tmp23, align 1
+  %tmp23 = getelementptr inbounds %struct.jim, %struct.jim* @global3, i64 0, i32 3, i64 0
+  %tmp24 = load i8, i8* %tmp23, align 1
   %tmp25 = icmp eq i8 %tmp24, 58
   br i1 %tmp25, label %bb30, label %bb26
 
@@ -92,18 +95,18 @@ bb30:                                             ; preds = %bb22
   br i1 %tmp31, label %bb33, label %bb32
 
 bb32:                                             ; preds = %bb30, %bb26, %bb17
-  tail call void (...)* @snork(i8* getelementptr inbounds ([52 x i8]* @global1, i64 0, i64 0), i32 2038) nounwind
-  tail call void (...)* @snork(i8* %tmp11, i32 -2146631418) nounwind
+  tail call void (...) @snork(i8* getelementptr inbounds ([52 x i8], [52 x i8]* @global1, i64 0, i64 0), i32 2038) nounwind
+  tail call void (...) @snork(i8* %tmp11, i32 -2146631418) nounwind
   unreachable
 
 bb33:                                             ; preds = %bb30
-  tail call void @zot(i8* getelementptr inbounds (%struct.jim* @global3, i64 0, i32 5, i64 0), i8* %tmp11, i64 undef, i32 1, i1 false) nounwind
-  %tmp34 = getelementptr inbounds %struct.jim* @global3, i64 0, i32 5, i64 undef
+  tail call void @zot(i8* getelementptr inbounds (%struct.jim, %struct.jim* @global3, i64 0, i32 5, i64 0), i8* %tmp11, i64 undef, i32 1, i1 false) nounwind
+  %tmp34 = getelementptr inbounds %struct.jim, %struct.jim* @global3, i64 0, i32 5, i64 undef
   store i8 0, i8* %tmp34, align 1
   %tmp35 = add nsw i32 %tmp19, 1
   %tmp36 = sext i32 %tmp35 to i64
   %tmp37 = add i64 %tmp36, %tmp10
-  %tmp38 = getelementptr inbounds %struct.jim* @global3, i64 0, i32 3, i64 %tmp37
+  %tmp38 = getelementptr inbounds %struct.jim, %struct.jim* @global3, i64 0, i32 3, i64 %tmp37
   %tmp39 = sub i64 %tmp12, %tmp36
   br i1 false, label %bb40, label %bb41
 
@@ -123,7 +126,7 @@ bb43:                                             ; preds = %bb52, %bb41
 
 bb48:                                             ; preds = %bb43
   %tmp49 = add i64 %tmp44, %tmp37
-  %tmp50 = load i8* undef, align 1
+  %tmp50 = load i8, i8* undef, align 1
   %tmp51 = icmp eq i8 %tmp50, 58
   br i1 %tmp51, label %bb55, label %bb52
 
@@ -138,14 +141,14 @@ bb55:                                             ; preds = %bb48
   br i1 %tmp57, label %bb59, label %bb58
 
 bb58:                                             ; preds = %bb55, %bb52, %bb43
-  tail call void (...)* @snork(i8* getelementptr inbounds ([52 x i8]* @global1, i64 0, i64 0), i32 2055) nounwind
-  tail call void (...)* @snork(i8* %tmp38, i32 -2146631418) nounwind
+  tail call void (...) @snork(i8* getelementptr inbounds ([52 x i8], [52 x i8]* @global1, i64 0, i64 0), i32 2055) nounwind
+  tail call void (...) @snork(i8* %tmp38, i32 -2146631418) nounwind
   br label %bb247
 
 bb59:                                             ; preds = %bb55
   %tmp60 = sext i32 %tmp45 to i64
-  tail call void @zot(i8* getelementptr inbounds (%struct.jim* @global3, i64 0, i32 5, i64 0), i8* %tmp38, i64 %tmp60, i32 1, i1 false) nounwind
-  %tmp61 = getelementptr inbounds %struct.jim* @global3, i64 0, i32 5, i64 %tmp60
+  tail call void @zot(i8* getelementptr inbounds (%struct.jim, %struct.jim* @global3, i64 0, i32 5, i64 0), i8* %tmp38, i64 %tmp60, i32 1, i1 false) nounwind
+  %tmp61 = getelementptr inbounds %struct.jim, %struct.jim* @global3, i64 0, i32 5, i64 %tmp60
   store i8 0, i8* %tmp61, align 1
   %tmp62 = add nsw i32 %tmp45, 1
   %tmp63 = sext i32 %tmp62 to i64
@@ -165,12 +168,12 @@ bb68:                                             ; preds = %bb59
   ]
 
 bb69:                                             ; preds = %bb68
-  tail call void (...)* @snork(i8* getelementptr inbounds ([52 x i8]* @global1, i64 0, i64 0), i32 2071) nounwind
-  %tmp70 = load i32* getelementptr inbounds (%struct.snork* @global, i64 0, i32 2), align 4
+  tail call void (...) @snork(i8* getelementptr inbounds ([52 x i8], [52 x i8]* @global1, i64 0, i64 0), i32 2071) nounwind
+  %tmp70 = load i32, i32* getelementptr inbounds (%struct.snork, %struct.snork* @global, i64 0, i32 2), align 4
   unreachable
 
 bb71:                                             ; preds = %bb68
-  %tmp72 = load i32* getelementptr inbounds (%struct.snork* @global, i64 0, i32 4), align 4
+  %tmp72 = load i32, i32* getelementptr inbounds (%struct.snork, %struct.snork* @global, i64 0, i32 4), align 4
   %tmp73 = icmp eq i32 undef, 0
   br i1 %tmp73, label %bb247, label %bb74
 
@@ -461,8 +464,8 @@ bb221:                                            ; preds = %bb230, %bb219
 
 bb226:                                            ; preds = %bb221
   %tmp227 = add i64 %tmp222, %tmp216
-  %tmp228 = getelementptr inbounds %struct.jim* @global3, i64 0, i32 3, i64 %tmp227
-  %tmp229 = load i8* %tmp228, align 1
+  %tmp228 = getelementptr inbounds %struct.jim, %struct.jim* @global3, i64 0, i32 3, i64 %tmp227
+  %tmp229 = load i8, i8* %tmp228, align 1
   br i1 false, label %bb233, label %bb230
 
 bb230:                                            ; preds = %bb226
diff --git a/test/Transforms/LoopStrengthReduce/2013-01-14-ReuseCast.ll b/test/Transforms/LoopStrengthReduce/2013-01-14-ReuseCast.ll
index 79dbf0d53703..dcd068191e10 100644
--- a/test/Transforms/LoopStrengthReduce/2013-01-14-ReuseCast.ll
+++ b/test/Transforms/LoopStrengthReduce/2013-01-14-ReuseCast.ll
@@ -72,8 +72,8 @@ bb61:                                             ; preds = %bb63, %bb58
   br i1 %tmp62, label %_ZNK4llvm9StringRef4findEcm.exit._crit_edge, label %bb63
 
 bb63:                                             ; preds = %bb61
-  %tmp64 = getelementptr inbounds i8* %tmp3, i64 %i.0.i
-  %tmp65 = load i8* %tmp64, align 1
+  %tmp64 = getelementptr inbounds i8, i8* %tmp3, i64 %i.0.i
+  %tmp65 = load i8, i8* %tmp64, align 1
   %tmp67 = add i64 %i.0.i, 1
   br i1 undef, label %_ZNK4llvm9StringRef4findEcm.exit.loopexit, label %bb61
 
diff --git a/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll b/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll
index 9a175ad8d355..2120b2a3bfe7 100644
--- a/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll
+++ b/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll
@@ -19,9 +19,9 @@ while.body:                                       ; preds = %while.body, %entry
   %len.06 = phi i64 [ 1288, %entry ], [ %sub, %while.body ]
   %pDst.05 = phi i64* [ inttoptr (i64 6442450944 to i64*), %entry ], [ %incdec.ptr1, %while.body ]
   %pSrc.04 = phi i64* [ inttoptr (i64 4294967296 to i64*), %entry ], [ %incdec.ptr, %while.body ]
-  %incdec.ptr = getelementptr inbounds i64* %pSrc.04, i64 1
-  %tmp = load volatile i64* %pSrc.04, align 8
-  %incdec.ptr1 = getelementptr inbounds i64* %pDst.05, i64 1
+  %incdec.ptr = getelementptr inbounds i64, i64* %pSrc.04, i64 1
+  %tmp = load volatile i64, i64* %pSrc.04, align 8
+  %incdec.ptr1 = getelementptr inbounds i64, i64* %pDst.05, i64 1
   store volatile i64 %tmp, i64* %pDst.05, align 8
   %sub = add i64 %len.06, -8
   %cmp = icmp sgt i64 %sub, -1
diff --git a/test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll b/test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll
index 48b709429467..e84f675736d1 100644
--- a/test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll
+++ b/test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll
@@ -38,7 +38,7 @@ land.rhs:                                         ; preds = %while.cond
   br i1 %cmp5, label %if.end9, label %while.body
 
 while.body:                                       ; preds = %land.rhs
-  %incdec.ptr = getelementptr inbounds i8* %ptr.0, i64 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %ptr.0, i64 1
   store i8 %conv, i8* %ptr.0, align 1, !tbaa !0
   %dec = add i64 %len.addr.0, -1
   br label %while.cond
@@ -67,7 +67,7 @@ if.end9:                                          ; preds = %land.rhs
 while.body18:                                     ; preds = %if.end9, %while.body18
   %wideptr.038 = phi i64* [ %incdec.ptr19, %while.body18 ], [ %9, %if.end9 ]
   %len.addr.137 = phi i64 [ %sub, %while.body18 ], [ %len.addr.0, %if.end9 ]
-  %incdec.ptr19 = getelementptr inbounds i64* %wideptr.038, i64 1
+  %incdec.ptr19 = getelementptr inbounds i64, i64* %wideptr.038, i64 1
   store i64 %ins, i64* %wideptr.038, align 8, !tbaa !2
   %sub = add i64 %len.addr.137, -8
   %cmp16 = icmp ugt i64 %sub, 7
@@ -87,7 +87,7 @@ while.body29:                                     ; preds = %while.body29, %whil
   %len.addr.235 = phi i64 [ %len.addr.1.lcssa49, %while.body29.lr.ph ], [ %dec26, %while.body29 ]
   %ptr.134 = phi i8* [ %10, %while.body29.lr.ph ], [ %incdec.ptr31, %while.body29 ]
   %dec26 = add i64 %len.addr.235, -1
-  %incdec.ptr31 = getelementptr inbounds i8* %ptr.134, i64 1
+  %incdec.ptr31 = getelementptr inbounds i8, i8* %ptr.134, i64 1
   store i8 %conv, i8* %ptr.134, align 1, !tbaa !0
   %cmp27 = icmp eq i64 %dec26, 0
   br i1 %cmp27, label %done, label %while.body29
diff --git a/test/Transforms/LoopStrengthReduce/AArch64/req-regs.ll b/test/Transforms/LoopStrengthReduce/AArch64/req-regs.ll
index 217896e55c66..c877ace7abf3 100644
--- a/test/Transforms/LoopStrengthReduce/AArch64/req-regs.ll
+++ b/test/Transforms/LoopStrengthReduce/AArch64/req-regs.ll
@@ -11,7 +11,7 @@ target triple = "arm64-apple-ios"
 define void @do_integer_add(i64 %iterations, i8* nocapture readonly %cookie) {
 entry:
   %N = bitcast i8* %cookie to i32*
-  %0 = load i32* %N, align 4
+  %0 = load i32, i32* %N, align 4
   %add = add nsw i32 %0, 57
   %cmp56 = icmp eq i64 %iterations, 0
   br i1 %cmp56, label %while.end, label %for.cond.preheader.preheader
diff --git a/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll b/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll
index 1d56ddea2446..56ff69c977ee 100644
--- a/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll
+++ b/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll
@@ -50,7 +50,7 @@ declare %s* @getstruct() nounwind
 ; CHECK: ldr{{.*}}lsl #2
 define i32 @main() nounwind ssp {
 entry:
-  %v0 = load i32* @ncol, align 4
+  %v0 = load i32, i32* @ncol, align 4
   %v1 = tail call i32* @getptr() nounwind
   %cmp10.i = icmp eq i32 %v0, 0
   br label %while.cond.outer
@@ -64,12 +64,12 @@ while.cond:
   br label %while.body
 
 while.body:
-  %v3 = load i32* @ncol, align 4
+  %v3 = load i32, i32* @ncol, align 4
   br label %end_of_chain
 
 end_of_chain:
-  %state.i = getelementptr inbounds %s* %call18, i32 0, i32 0
-  %v4 = load i32** %state.i, align 4
+  %state.i = getelementptr inbounds %s, %s* %call18, i32 0, i32 0
+  %v4 = load i32*, i32** %state.i, align 4
   br label %while.cond.i.i
 
 while.cond.i.i:
@@ -79,10 +79,10 @@ while.cond.i.i:
   br i1 %tobool.i.i, label %where.exit, label %land.rhs.i.i
 
 land.rhs.i.i:
-  %arrayidx.i.i = getelementptr inbounds i32* %v4, i32 %dec.i.i
-  %v5 = load i32* %arrayidx.i.i, align 4
-  %arrayidx1.i.i = getelementptr inbounds i32* %v1, i32 %dec.i.i
-  %v6 = load i32* %arrayidx1.i.i, align 4
+  %arrayidx.i.i = getelementptr inbounds i32, i32* %v4, i32 %dec.i.i
+  %v5 = load i32, i32* %arrayidx.i.i, align 4
+  %arrayidx1.i.i = getelementptr inbounds i32, i32* %v1, i32 %dec.i.i
+  %v6 = load i32, i32* %arrayidx1.i.i, align 4
   %cmp.i.i = icmp eq i32 %v5, %v6
   br i1 %cmp.i.i, label %while.cond.i.i, label %equal_data.exit.i
 
diff --git a/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll b/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll
index f4edf092641f..2ad6c2ea52da 100644
--- a/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll
+++ b/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll
@@ -18,18 +18,18 @@ entry:
 loop:
   %iv = phi i32* [ %a, %entry ], [ %iv4, %loop ]
   %s = phi i32 [ 0, %entry ], [ %s4, %loop ]
-  %v = load i32* %iv
-  %iv1 = getelementptr inbounds i32* %iv, i32 %x
-  %v1 = load i32* %iv1
-  %iv2 = getelementptr inbounds i32* %iv1, i32 %x
-  %v2 = load i32* %iv2
-  %iv3 = getelementptr inbounds i32* %iv2, i32 %x
-  %v3 = load i32* %iv3
+  %v = load i32, i32* %iv
+  %iv1 = getelementptr inbounds i32, i32* %iv, i32 %x
+  %v1 = load i32, i32* %iv1
+  %iv2 = getelementptr inbounds i32, i32* %iv1, i32 %x
+  %v2 = load i32, i32* %iv2
+  %iv3 = getelementptr inbounds i32, i32* %iv2, i32 %x
+  %v3 = load i32, i32* %iv3
   %s1 = add i32 %s, %v
   %s2 = add i32 %s1, %v1
   %s3 = add i32 %s2, %v2
   %s4 = add i32 %s3, %v3
-  %iv4 = getelementptr inbounds i32* %iv3, i32 %x
+  %iv4 = getelementptr inbounds i32, i32* %iv3, i32 %x
   %cmp = icmp eq i32* %iv4, %b
   br i1 %cmp, label %exit, label %loop
 exit:
@@ -52,18 +52,18 @@ entry:
 loop:
   %iv = phi i32* [ %a, %entry ], [ %iv4, %loop ]
   %s = phi i32 [ 0, %entry ], [ %s4, %loop ]
-  %v = load i32* %iv
-  %iv1 = getelementptr inbounds i32* %iv, i32 %x
-  %v1 = load i32* %iv1
-  %iv2 = getelementptr inbounds i32* %iv1, i32 %x
-  %v2 = load i32* %iv2
-  %iv3 = getelementptr inbounds i32* %iv2, i32 %x
-  %v3 = load i32* %iv3
+  %v = load i32, i32* %iv
+  %iv1 = getelementptr inbounds i32, i32* %iv, i32 %x
+  %v1 = load i32, i32* %iv1
+  %iv2 = getelementptr inbounds i32, i32* %iv1, i32 %x
+  %v2 = load i32, i32* %iv2
+  %iv3 = getelementptr inbounds i32, i32* %iv2, i32 %x
+  %v3 = load i32, i32* %iv3
   %s1 = add i32 %s, %v
   %s2 = add i32 %s1, %v1
   %s3 = add i32 %s2, %v2
   %s4 = add i32 %s3, %v3
-  %iv4 = getelementptr inbounds i32* %iv3, i32 %x
+  %iv4 = getelementptr inbounds i32, i32* %iv3, i32 %x
   store i32 %s4, i32* %iv
   %cmp = icmp eq i32* %iv4, %b
   br i1 %cmp, label %exit, label %loop
@@ -103,26 +103,26 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %i.010 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %res.addr.09 = phi i32* [ %res, %for.body.lr.ph ], [ %add.ptr7, %for.body ]
   %0 = bitcast i8* %main.addr.011 to i32*
-  %1 = load i32* %0, align 4
-  %add.ptr = getelementptr inbounds i8* %main.addr.011, i32 %main_stride
+  %1 = load i32, i32* %0, align 4
+  %add.ptr = getelementptr inbounds i8, i8* %main.addr.011, i32 %main_stride
   %2 = bitcast i8* %add.ptr to i32*
-  %3 = load i32* %2, align 4
-  %add.ptr1 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr.sum
+  %3 = load i32, i32* %2, align 4
+  %add.ptr1 = getelementptr inbounds i8, i8* %main.addr.011, i32 %add.ptr.sum
   %4 = bitcast i8* %add.ptr1 to i32*
-  %5 = load i32* %4, align 4
-  %add.ptr2 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr1.sum
+  %5 = load i32, i32* %4, align 4
+  %add.ptr2 = getelementptr inbounds i8, i8* %main.addr.011, i32 %add.ptr1.sum
   %6 = bitcast i8* %add.ptr2 to i32*
-  %7 = load i32* %6, align 4
-  %add.ptr3 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr4.sum
+  %7 = load i32, i32* %6, align 4
+  %add.ptr3 = getelementptr inbounds i8, i8* %main.addr.011, i32 %add.ptr4.sum
   %8 = bitcast i8* %add.ptr3 to i32*
-  %9 = load i32* %8, align 4
+  %9 = load i32, i32* %8, align 4
   %add = add i32 %3, %1
   %add4 = add i32 %add, %5
   %add5 = add i32 %add4, %7
   %add6 = add i32 %add5, %9
   store i32 %add6, i32* %res.addr.09, align 4
-  %add.ptr6 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr3.sum
-  %add.ptr7 = getelementptr inbounds i32* %res.addr.09, i32 %y
+  %add.ptr6 = getelementptr inbounds i8, i8* %main.addr.011, i32 %add.ptr3.sum
+  %add.ptr7 = getelementptr inbounds i32, i32* %res.addr.09, i32 %y
   %inc = add i32 %i.010, 1
   %cmp = icmp eq i32 %inc, %z
   br i1 %cmp, label %for.end, label %for.body
@@ -146,48 +146,48 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %i.07 = phi i32 [ 0, %entry ], [ %inc.3, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %a, i32 %i.07
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %a, i32 %i.07
+  %0 = load i8, i8* %arrayidx, align 1
   %conv5 = zext i8 %0 to i32
-  %arrayidx1 = getelementptr inbounds i8* %b, i32 %i.07
-  %1 = load i8* %arrayidx1, align 1
+  %arrayidx1 = getelementptr inbounds i8, i8* %b, i32 %i.07
+  %1 = load i8, i8* %arrayidx1, align 1
   %conv26 = zext i8 %1 to i32
   %add = add nsw i32 %conv26, %conv5
   %conv3 = trunc i32 %add to i8
-  %arrayidx4 = getelementptr inbounds i8* %c, i32 %i.07
+  %arrayidx4 = getelementptr inbounds i8, i8* %c, i32 %i.07
   store i8 %conv3, i8* %arrayidx4, align 1
   %inc1 = or i32 %i.07, 1
-  %arrayidx.1 = getelementptr inbounds i8* %a, i32 %inc1
-  %2 = load i8* %arrayidx.1, align 1
+  %arrayidx.1 = getelementptr inbounds i8, i8* %a, i32 %inc1
+  %2 = load i8, i8* %arrayidx.1, align 1
   %conv5.1 = zext i8 %2 to i32
-  %arrayidx1.1 = getelementptr inbounds i8* %b, i32 %inc1
-  %3 = load i8* %arrayidx1.1, align 1
+  %arrayidx1.1 = getelementptr inbounds i8, i8* %b, i32 %inc1
+  %3 = load i8, i8* %arrayidx1.1, align 1
   %conv26.1 = zext i8 %3 to i32
   %add.1 = add nsw i32 %conv26.1, %conv5.1
   %conv3.1 = trunc i32 %add.1 to i8
-  %arrayidx4.1 = getelementptr inbounds i8* %c, i32 %inc1
+  %arrayidx4.1 = getelementptr inbounds i8, i8* %c, i32 %inc1
   store i8 %conv3.1, i8* %arrayidx4.1, align 1
   %inc.12 = or i32 %i.07, 2
-  %arrayidx.2 = getelementptr inbounds i8* %a, i32 %inc.12
-  %4 = load i8* %arrayidx.2, align 1
+  %arrayidx.2 = getelementptr inbounds i8, i8* %a, i32 %inc.12
+  %4 = load i8, i8* %arrayidx.2, align 1
   %conv5.2 = zext i8 %4 to i32
-  %arrayidx1.2 = getelementptr inbounds i8* %b, i32 %inc.12
-  %5 = load i8* %arrayidx1.2, align 1
+  %arrayidx1.2 = getelementptr inbounds i8, i8* %b, i32 %inc.12
+  %5 = load i8, i8* %arrayidx1.2, align 1
   %conv26.2 = zext i8 %5 to i32
   %add.2 = add nsw i32 %conv26.2, %conv5.2
   %conv3.2 = trunc i32 %add.2 to i8
-  %arrayidx4.2 = getelementptr inbounds i8* %c, i32 %inc.12
+  %arrayidx4.2 = getelementptr inbounds i8, i8* %c, i32 %inc.12
   store i8 %conv3.2, i8* %arrayidx4.2, align 1
   %inc.23 = or i32 %i.07, 3
-  %arrayidx.3 = getelementptr inbounds i8* %a, i32 %inc.23
-  %6 = load i8* %arrayidx.3, align 1
+  %arrayidx.3 = getelementptr inbounds i8, i8* %a, i32 %inc.23
+  %6 = load i8, i8* %arrayidx.3, align 1
   %conv5.3 = zext i8 %6 to i32
-  %arrayidx1.3 = getelementptr inbounds i8* %b, i32 %inc.23
-  %7 = load i8* %arrayidx1.3, align 1
+  %arrayidx1.3 = getelementptr inbounds i8, i8* %b, i32 %inc.23
+  %7 = load i8, i8* %arrayidx1.3, align 1
   %conv26.3 = zext i8 %7 to i32
   %add.3 = add nsw i32 %conv26.3, %conv5.3
   %conv3.3 = trunc i32 %add.3 to i8
-  %arrayidx4.3 = getelementptr inbounds i8* %c, i32 %inc.23
+  %arrayidx4.3 = getelementptr inbounds i8, i8* %c, i32 %inc.23
   store i8 %conv3.3, i8* %arrayidx4.3, align 1
   %inc.3 = add nsw i32 %i.07, 4
   %exitcond.3 = icmp eq i32 %inc.3, 400
@@ -201,7 +201,7 @@ for.end:                                          ; preds = %for.body
 ;
 ; Currently we have three extra add.w's that keep the store address
 ; live past the next increment because ISEL is unfortunately undoing
-; the store chain. ISEL also fails to convert the stores to
+; the store chain. ISEL also fails to convert all but one of the stores to
 ; post-increment addressing. However, the loads should use
 ; post-increment addressing, no add's or add.w's beyond the three
 ; mentioned. Most importantly, there should be no spills or reloads!
@@ -210,7 +210,7 @@ for.end:                                          ; preds = %for.body
 ; A9: %.lr.ph
 ; A9-NOT: lsl.w
 ; A9-NOT: {{ldr|str|adds|add r}}
-; A9: add.w r
+; A9: vst1.8 {{.*}} [r{{[0-9]+}}]!
 ; A9-NOT: {{ldr|str|adds|add r}}
 ; A9: add.w r
 ; A9-NOT: {{ldr|str|adds|add r}}
@@ -240,31 +240,31 @@ define hidden void @testNeon(i8* %ref_data, i32 %ref_stride, i32 %limit, <16 x i
   %result.03 = phi <16 x i8> [ zeroinitializer, %.lr.ph ], [ %41, %11 ]
   %.012 = phi <16 x i8>* [ %data, %.lr.ph ], [ %43, %11 ]
   %12 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %.05, i32 1) nounwind
-  %13 = getelementptr inbounds i8* %.05, i32 %ref_stride
+  %13 = getelementptr inbounds i8, i8* %.05, i32 %ref_stride
   %14 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %13, i32 1) nounwind
   %15 = shufflevector <1 x i64> %12, <1 x i64> %14, <2 x i32> <i32 0, i32 1>
   %16 = bitcast <2 x i64> %15 to <16 x i8>
-  %17 = getelementptr inbounds <16 x i8>* %.012, i32 1
+  %17 = getelementptr inbounds <16 x i8>, <16 x i8>* %.012, i32 1
   store <16 x i8> %16, <16 x i8>* %.012, align 4
-  %18 = getelementptr inbounds i8* %.05, i32 %2
+  %18 = getelementptr inbounds i8, i8* %.05, i32 %2
   %19 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %18, i32 1) nounwind
-  %20 = getelementptr inbounds i8* %.05, i32 %3
+  %20 = getelementptr inbounds i8, i8* %.05, i32 %3
   %21 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %20, i32 1) nounwind
   %22 = shufflevector <1 x i64> %19, <1 x i64> %21, <2 x i32> <i32 0, i32 1>
   %23 = bitcast <2 x i64> %22 to <16 x i8>
-  %24 = getelementptr inbounds <16 x i8>* %.012, i32 2
+  %24 = getelementptr inbounds <16 x i8>, <16 x i8>* %.012, i32 2
   store <16 x i8> %23, <16 x i8>* %17, align 4
-  %25 = getelementptr inbounds i8* %.05, i32 %4
+  %25 = getelementptr inbounds i8, i8* %.05, i32 %4
   %26 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %25, i32 1) nounwind
-  %27 = getelementptr inbounds i8* %.05, i32 %5
+  %27 = getelementptr inbounds i8, i8* %.05, i32 %5
   %28 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %27, i32 1) nounwind
   %29 = shufflevector <1 x i64> %26, <1 x i64> %28, <2 x i32> <i32 0, i32 1>
   %30 = bitcast <2 x i64> %29 to <16 x i8>
-  %31 = getelementptr inbounds <16 x i8>* %.012, i32 3
+  %31 = getelementptr inbounds <16 x i8>, <16 x i8>* %.012, i32 3
   store <16 x i8> %30, <16 x i8>* %24, align 4
-  %32 = getelementptr inbounds i8* %.05, i32 %6
+  %32 = getelementptr inbounds i8, i8* %.05, i32 %6
   %33 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %32, i32 1) nounwind
-  %34 = getelementptr inbounds i8* %.05, i32 %7
+  %34 = getelementptr inbounds i8, i8* %.05, i32 %7
   %35 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %34, i32 1) nounwind
   %36 = shufflevector <1 x i64> %33, <1 x i64> %35, <2 x i32> <i32 0, i32 1>
   %37 = bitcast <2 x i64> %36 to <16 x i8>
@@ -273,14 +273,14 @@ define hidden void @testNeon(i8* %ref_data, i32 %ref_stride, i32 %limit, <16 x i
   %39 = add <16 x i8> %38, %30
   %40 = add <16 x i8> %39, %37
   %41 = add <16 x i8> %result.03, %40
-  %42 = getelementptr i8* %.05, i32 %9
-  %43 = getelementptr inbounds <16 x i8>* %.012, i32 -64
+  %42 = getelementptr i8, i8* %.05, i32 %9
+  %43 = getelementptr inbounds <16 x i8>, <16 x i8>* %.012, i32 -64
   %44 = add nsw i32 %counter.04, 1
   %exitcond = icmp eq i32 %44, %limit
   br i1 %exitcond, label %._crit_edge, label %11
 
 ._crit_edge:                                      ; preds = %11
-  %scevgep = getelementptr <16 x i8>* %data, i32 %10
+  %scevgep = getelementptr <16 x i8>, <16 x i8>* %data, i32 %10
   br label %45
 
 ; <label>:45                                      ; preds = %._crit_edge, %0
@@ -327,20 +327,20 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %i.0110 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %src.addr = phi i8* [ %src, %entry ], [ %add.ptr45, %for.body ]
-  %add.ptr = getelementptr inbounds i8* %src.addr, i32 %idx.neg
+  %add.ptr = getelementptr inbounds i8, i8* %src.addr, i32 %idx.neg
   %vld1 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr, i32 1)
-  %add.ptr3 = getelementptr inbounds i8* %src.addr, i32 %idx.neg2
+  %add.ptr3 = getelementptr inbounds i8, i8* %src.addr, i32 %idx.neg2
   %vld2 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr3, i32 1)
-  %add.ptr7 = getelementptr inbounds i8* %src.addr, i32 %idx.neg6
+  %add.ptr7 = getelementptr inbounds i8, i8* %src.addr, i32 %idx.neg6
   %vld3 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr7, i32 1)
-  %add.ptr11 = getelementptr inbounds i8* %src.addr, i32 %idx.neg10
+  %add.ptr11 = getelementptr inbounds i8, i8* %src.addr, i32 %idx.neg10
   %vld4 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr11, i32 1)
   %vld5 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %src.addr, i32 1)
-  %add.ptr17 = getelementptr inbounds i8* %src.addr, i32 %stride
+  %add.ptr17 = getelementptr inbounds i8, i8* %src.addr, i32 %stride
   %vld6 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr17, i32 1)
-  %add.ptr20 = getelementptr inbounds i8* %src.addr, i32 %mul5
+  %add.ptr20 = getelementptr inbounds i8, i8* %src.addr, i32 %mul5
   %vld7 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr20, i32 1)
-  %add.ptr23 = getelementptr inbounds i8* %src.addr, i32 %mul1
+  %add.ptr23 = getelementptr inbounds i8, i8* %src.addr, i32 %mul1
   %vld8 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr23, i32 1)
   %vadd1 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld1, <8 x i8> %vld2) nounwind
   %vadd2 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld2, <8 x i8> %vld3) nounwind
@@ -355,7 +355,7 @@ for.body:                                         ; preds = %for.body, %entry
   tail call void @llvm.arm.neon.vst1.v8i8(i8* %add.ptr17, <8 x i8> %vadd5, i32 1)
   tail call void @llvm.arm.neon.vst1.v8i8(i8* %add.ptr20, <8 x i8> %vadd6, i32 1)
   %inc = add nsw i32 %i.0110, 1
-  %add.ptr45 = getelementptr inbounds i8* %src.addr, i32 8
+  %add.ptr45 = getelementptr inbounds i8, i8* %src.addr, i32 8
   %exitcond = icmp eq i32 %inc, 4
   br i1 %exitcond, label %for.end, label %for.body
 
diff --git a/test/Transforms/LoopStrengthReduce/X86/2008-08-14-ShadowIV.ll b/test/Transforms/LoopStrengthReduce/X86/2008-08-14-ShadowIV.ll
index 9a7f4865c591..f862c2635869 100644
--- a/test/Transforms/LoopStrengthReduce/X86/2008-08-14-ShadowIV.ll
+++ b/test/Transforms/LoopStrengthReduce/X86/2008-08-14-ShadowIV.ll
@@ -1,5 +1,9 @@
 ; RUN: opt < %s -loop-reduce -S -mtriple=x86_64-unknown-unknown | grep "phi double" | count 1
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+
 define void @foobar(i32 %n) nounwind {
 entry:
 	icmp eq i32 %n, 0		; <i1>:0 [#uses=2]
@@ -50,7 +54,7 @@ return:		; preds = %bb, %entry
 ; Unable to eliminate cast due to potentional overflow.
 define void @foobar3() nounwind {
 entry:
-	tail call i32 (...)* @nn( ) nounwind		; <i32>:0 [#uses=1]
+	tail call i32 (...) @nn( ) nounwind		; <i32>:0 [#uses=1]
 	icmp eq i32 %0, 0		; <i1>:1 [#uses=1]
 	br i1 %1, label %return, label %bb
 
@@ -60,7 +64,7 @@ bb:		; preds = %bb, %entry
 	uitofp i32 %i.03 to double		; <double>:2 [#uses=1]
 	tail call void @foo( double %2 ) nounwind
 	add i32 %i.03, 1		; <i32>:3 [#uses=2]
-	tail call i32 (...)* @nn( ) nounwind		; <i32>:4 [#uses=1]
+	tail call i32 (...) @nn( ) nounwind		; <i32>:4 [#uses=1]
 	icmp ugt i32 %4, %3		; <i1>:5 [#uses=1]
 	br i1 %5, label %bb, label %return
 
diff --git a/test/Transforms/LoopStrengthReduce/X86/2011-07-20-DoubleIV.ll b/test/Transforms/LoopStrengthReduce/X86/2011-07-20-DoubleIV.ll
index 2fe62e39fc93..0fc928ca9b28 100644
--- a/test/Transforms/LoopStrengthReduce/X86/2011-07-20-DoubleIV.ll
+++ b/test/Transforms/LoopStrengthReduce/X86/2011-07-20-DoubleIV.ll
@@ -4,6 +4,10 @@
 ; nonzero initial value.
 ; rdar://9786536
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+
 ; First, make sure LSR doesn't crash on an empty IVUsers list.
 ; CHECK-LABEL: @dummyIV(
 ; CHECK-NOT: phi
diff --git a/test/Transforms/LoopStrengthReduce/X86/2011-12-04-loserreg.ll b/test/Transforms/LoopStrengthReduce/X86/2011-12-04-loserreg.ll
index 001a1d695c99..862fff29cefb 100644
--- a/test/Transforms/LoopStrengthReduce/X86/2011-12-04-loserreg.ll
+++ b/test/Transforms/LoopStrengthReduce/X86/2011-12-04-loserreg.ll
@@ -29,34 +29,34 @@ for.body:                                         ; preds = %entry, %for.body
   %indvars.iv39 = phi i64 [ %indvars.iv.next40, %for.body ], [ 0, %entry ]
   %dp.036 = phi i32* [ %add.ptr, %for.body ], [ %destrow, %entry ]
   %p.035 = phi float* [ %incdec.ptr4, %for.body ], [ %srcrow, %entry ]
-  %incdec.ptr = getelementptr inbounds float* %p.035, i64 1
-  %0 = load float* %incdec.ptr, align 4
-  %incdec.ptr2 = getelementptr inbounds float* %p.035, i64 2
-  %1 = load float* %incdec.ptr2, align 4
-  %incdec.ptr3 = getelementptr inbounds float* %p.035, i64 3
-  %2 = load float* %incdec.ptr3, align 4
-  %incdec.ptr4 = getelementptr inbounds float* %p.035, i64 4
-  %3 = load float* %incdec.ptr4, align 4
-  %4 = load i32* %dp.036, align 4
+  %incdec.ptr = getelementptr inbounds float, float* %p.035, i64 1
+  %0 = load float, float* %incdec.ptr, align 4
+  %incdec.ptr2 = getelementptr inbounds float, float* %p.035, i64 2
+  %1 = load float, float* %incdec.ptr2, align 4
+  %incdec.ptr3 = getelementptr inbounds float, float* %p.035, i64 3
+  %2 = load float, float* %incdec.ptr3, align 4
+  %incdec.ptr4 = getelementptr inbounds float, float* %p.035, i64 4
+  %3 = load float, float* %incdec.ptr4, align 4
+  %4 = load i32, i32* %dp.036, align 4
   %conv5 = fptoui float %0 to i32
   %or = or i32 %4, %conv5
-  %arrayidx6 = getelementptr inbounds i32* %dp.036, i64 1
-  %5 = load i32* %arrayidx6, align 4
+  %arrayidx6 = getelementptr inbounds i32, i32* %dp.036, i64 1
+  %5 = load i32, i32* %arrayidx6, align 4
   %conv7 = fptoui float %1 to i32
   %or8 = or i32 %5, %conv7
-  %arrayidx9 = getelementptr inbounds i32* %dp.036, i64 2
-  %6 = load i32* %arrayidx9, align 4
+  %arrayidx9 = getelementptr inbounds i32, i32* %dp.036, i64 2
+  %6 = load i32, i32* %arrayidx9, align 4
   %conv10 = fptoui float %2 to i32
   %or11 = or i32 %6, %conv10
-  %arrayidx12 = getelementptr inbounds i32* %dp.036, i64 3
-  %7 = load i32* %arrayidx12, align 4
+  %arrayidx12 = getelementptr inbounds i32, i32* %dp.036, i64 3
+  %7 = load i32, i32* %arrayidx12, align 4
   %conv13 = fptoui float %3 to i32
   %or14 = or i32 %7, %conv13
   store i32 %or, i32* %dp.036, align 4
   store i32 %or8, i32* %arrayidx6, align 4
   store i32 %or11, i32* %arrayidx9, align 4
   store i32 %or14, i32* %arrayidx12, align 4
-  %add.ptr = getelementptr inbounds i32* %dp.036, i64 4
+  %add.ptr = getelementptr inbounds i32, i32* %dp.036, i64 4
   %indvars.iv.next40 = add i64 %indvars.iv39, 4
   %dummycnt = add i64 %dummyiv, 1
   %cmp = icmp ult i64 %indvars.iv.next40, %count
@@ -76,14 +76,14 @@ for.body23:                                       ; preds = %for.body23, %for.bo
   %indvars.iv = phi i64 [ 0, %for.body23.lr.ph ], [ %indvars.iv.next, %for.body23 ]
   %dp.132 = phi i32* [ %add.ptr, %for.body23.lr.ph ], [ %incdec.ptr28, %for.body23 ]
   %p.131 = phi float* [ %incdec.ptr4, %for.body23.lr.ph ], [ %incdec.ptr24, %for.body23 ]
-  %incdec.ptr24 = getelementptr inbounds float* %p.131, i64 1
-  %9 = load float* %incdec.ptr24, align 4
-  %10 = load i32* %dp.132, align 4
+  %incdec.ptr24 = getelementptr inbounds float, float* %p.131, i64 1
+  %9 = load float, float* %incdec.ptr24, align 4
+  %10 = load i32, i32* %dp.132, align 4
   %conv25 = fptoui float %9 to i32
   %or26 = or i32 %10, %conv25
   store i32 %or26, i32* %dp.132, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
-  %incdec.ptr28 = getelementptr inbounds i32* %dp.132, i64 1
+  %incdec.ptr28 = getelementptr inbounds i32, i32* %dp.132, i64 1
   %exitcond = icmp eq i64 %indvars.iv.next, %8
   br i1 %exitcond, label %for.end29, label %for.body23
 
diff --git a/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll b/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
index c3b8b8910d5c..184e300c7eb8 100644
--- a/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
+++ b/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
@@ -27,14 +27,14 @@ while.body.i:                                     ; preds = %cond.true29.i, %whi
 for.body.i:                                       ; preds = %for.body.i, %while.body.i
   %indvars.iv.i = phi i64 [ 0, %while.body.i ], [ %indvars.iv.next.i, %for.body.i ]
   %add.ptr.sum = add i64 %add.ptr.sum.i, %indvars.iv.i
-  %arrayidx22.i = getelementptr inbounds i8* %base, i64 %add.ptr.sum
-  %0 = load i8* %arrayidx22.i, align 1
+  %arrayidx22.i = getelementptr inbounds i8, i8* %base, i64 %add.ptr.sum
+  %0 = load i8, i8* %arrayidx22.i, align 1
   %indvars.iv.next.i = add i64 %indvars.iv.i, 1
   %cmp = call i1 @check() nounwind
   br i1 %cmp, label %for.end.i, label %for.body.i
 
 for.end.i:                                        ; preds = %for.body.i
-  %add.ptr.i144 = getelementptr inbounds i8* %base, i64 %add.ptr.sum.i
+  %add.ptr.i144 = getelementptr inbounds i8, i8* %base, i64 %add.ptr.sum.i
   %cmp2 = tail call i1 @foo(i8* %add.ptr.i144, i8* %add.ptr.i144, i8* undef) nounwind
   br i1 %cmp2, label %cond.true29.i, label %cond.false35.i
 
@@ -68,19 +68,19 @@ entry:
 
 for.cond468:                                      ; preds = %if.then477, %entry
   %indvars.iv1163 = phi i64 [ %indvars.iv.next1164, %if.then477 ], [ 1, %entry ]
-  %k.0.in = phi i32* [ %last, %if.then477 ], [ getelementptr inbounds ([5000 x %struct.anon.7.91.199.307.415.475.559.643.751.835.943.1003.1111.1219.1351.1375.1399.1435.1471.1483.1519.1531.1651.1771]* @tags, i64 0, i64 0, i32 2), %entry ]
-  %k.0 = load i32* %k.0.in, align 4
+  %k.0.in = phi i32* [ %last, %if.then477 ], [ getelementptr inbounds ([5000 x %struct.anon.7.91.199.307.415.475.559.643.751.835.943.1003.1111.1219.1351.1375.1399.1435.1471.1483.1519.1531.1651.1771], [5000 x %struct.anon.7.91.199.307.415.475.559.643.751.835.943.1003.1111.1219.1351.1375.1399.1435.1471.1483.1519.1531.1651.1771]* @tags, i64 0, i64 0, i32 2), %entry ]
+  %k.0 = load i32, i32* %k.0.in, align 4
   %0 = trunc i64 %indvars.iv1163 to i32
   %cmp469 = icmp slt i32 %0, %n
   br i1 %cmp469, label %for.body471, label %for.inc498
 
 for.body471:                                      ; preds = %for.cond468
-  %first = getelementptr inbounds [5000 x %struct.anon.7.91.199.307.415.475.559.643.751.835.943.1003.1111.1219.1351.1375.1399.1435.1471.1483.1519.1531.1651.1771]* @tags, i64 0, i64 %indvars.iv1163, i32 1
-  %1 = load i32* %first, align 4
+  %first = getelementptr inbounds [5000 x %struct.anon.7.91.199.307.415.475.559.643.751.835.943.1003.1111.1219.1351.1375.1399.1435.1471.1483.1519.1531.1651.1771], [5000 x %struct.anon.7.91.199.307.415.475.559.643.751.835.943.1003.1111.1219.1351.1375.1399.1435.1471.1483.1519.1531.1651.1771]* @tags, i64 0, i64 %indvars.iv1163, i32 1
+  %1 = load i32, i32* %first, align 4
   br i1 undef, label %if.then477, label %for.inc498
 
 if.then477:                                       ; preds = %for.body471
-  %last = getelementptr inbounds [5000 x %struct.anon.7.91.199.307.415.475.559.643.751.835.943.1003.1111.1219.1351.1375.1399.1435.1471.1483.1519.1531.1651.1771]* @tags, i64 0, i64 %indvars.iv1163, i32 2
+  %last = getelementptr inbounds [5000 x %struct.anon.7.91.199.307.415.475.559.643.751.835.943.1003.1111.1219.1351.1375.1399.1435.1471.1483.1519.1531.1651.1771], [5000 x %struct.anon.7.91.199.307.415.475.559.643.751.835.943.1003.1111.1219.1351.1375.1399.1435.1471.1483.1519.1531.1651.1771]* @tags, i64 0, i64 %indvars.iv1163, i32 2
   %indvars.iv.next1164 = add i64 %indvars.iv1163, 1
   br label %for.cond468
 
@@ -118,14 +118,14 @@ for.body3.us.i:                                   ; preds = %meshBB, %for.body3.
   %0 = add nsw i64 %indvars.iv.i.SV.phi, %indvars.iv8.i.SV.phi26
   %1 = trunc i64 %0 to i32
   %mul.i.us.i = mul nsw i32 0, %1
-  %arrayidx5.us.i = getelementptr inbounds double* %u, i64 %indvars.iv.i.SV.phi
-  %2 = load double* %arrayidx5.us.i, align 8
+  %arrayidx5.us.i = getelementptr inbounds double, double* %u, i64 %indvars.iv.i.SV.phi
+  %2 = load double, double* %arrayidx5.us.i, align 8
   %indvars.iv.next.i = add i64 %indvars.iv.i.SV.phi, 1
   br i1 undef, label %for.inc8.us.i, label %meshBB
 
 for.body3.lr.ph.us.i:                             ; preds = %meshBB1, %meshBB
   %indvars.iv8.i.SV.phi26 = phi i64 [ undef, %meshBB1 ], [ %indvars.iv8.i.SV.phi24, %meshBB ]
-  %arrayidx.us.i = getelementptr inbounds double* undef, i64 %indvars.iv8.i.SV.phi26
+  %arrayidx.us.i = getelementptr inbounds double, double* undef, i64 %indvars.iv8.i.SV.phi26
   %3 = add i64 %indvars.iv8.i.SV.phi26, 1
   br label %for.body3.us.i
 
diff --git a/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll b/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll
index 937791dca413..c1099b23dcfc 100644
--- a/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll
+++ b/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll
@@ -29,18 +29,18 @@ entry:
 loop:
   %iv = phi i32* [ %a, %entry ], [ %iv4, %loop ]
   %s = phi i32 [ 0, %entry ], [ %s4, %loop ]
-  %v = load i32* %iv
-  %iv1 = getelementptr inbounds i32* %iv, i32 %x
-  %v1 = load i32* %iv1
-  %iv2 = getelementptr inbounds i32* %iv1, i32 %x
-  %v2 = load i32* %iv2
-  %iv3 = getelementptr inbounds i32* %iv2, i32 %x
-  %v3 = load i32* %iv3
+  %v = load i32, i32* %iv
+  %iv1 = getelementptr inbounds i32, i32* %iv, i32 %x
+  %v1 = load i32, i32* %iv1
+  %iv2 = getelementptr inbounds i32, i32* %iv1, i32 %x
+  %v2 = load i32, i32* %iv2
+  %iv3 = getelementptr inbounds i32, i32* %iv2, i32 %x
+  %v3 = load i32, i32* %iv3
   %s1 = add i32 %s, %v
   %s2 = add i32 %s1, %v1
   %s3 = add i32 %s2, %v2
   %s4 = add i32 %s3, %v3
-  %iv4 = getelementptr inbounds i32* %iv3, i32 %x
+  %iv4 = getelementptr inbounds i32, i32* %iv3, i32 %x
   %cmp = icmp eq i32* %iv4, %b
   br i1 %cmp, label %exit, label %loop
 exit:
@@ -59,7 +59,9 @@ exit:
 ;
 ; X32: @user
 ; expensive address computation in the preheader
-; X32: imul
+; X32: shll $4
+; X32: lea
+; X32: lea
 ; X32: %loop
 ; complex address modes
 ; X32: (%{{[^)]+}},%{{[^)]+}},
@@ -69,18 +71,18 @@ entry:
 loop:
   %iv = phi i32* [ %a, %entry ], [ %iv4, %loop ]
   %s = phi i32 [ 0, %entry ], [ %s4, %loop ]
-  %v = load i32* %iv
-  %iv1 = getelementptr inbounds i32* %iv, i32 %x
-  %v1 = load i32* %iv1
-  %iv2 = getelementptr inbounds i32* %iv1, i32 %x
-  %v2 = load i32* %iv2
-  %iv3 = getelementptr inbounds i32* %iv2, i32 %x
-  %v3 = load i32* %iv3
+  %v = load i32, i32* %iv
+  %iv1 = getelementptr inbounds i32, i32* %iv, i32 %x
+  %v1 = load i32, i32* %iv1
+  %iv2 = getelementptr inbounds i32, i32* %iv1, i32 %x
+  %v2 = load i32, i32* %iv2
+  %iv3 = getelementptr inbounds i32, i32* %iv2, i32 %x
+  %v3 = load i32, i32* %iv3
   %s1 = add i32 %s, %v
   %s2 = add i32 %s1, %v1
   %s3 = add i32 %s2, %v2
   %s4 = add i32 %s3, %v3
-  %iv4 = getelementptr inbounds i32* %iv3, i32 %x
+  %iv4 = getelementptr inbounds i32, i32* %iv3, i32 %x
   store i32 %s4, i32* %iv
   %cmp = icmp eq i32* %iv4, %b
   br i1 %cmp, label %exit, label %loop
@@ -124,26 +126,26 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %i.010 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %res.addr.09 = phi i32* [ %res, %for.body.lr.ph ], [ %add.ptr7, %for.body ]
   %0 = bitcast i8* %main.addr.011 to i32*
-  %1 = load i32* %0, align 4
-  %add.ptr = getelementptr inbounds i8* %main.addr.011, i32 %main_stride
+  %1 = load i32, i32* %0, align 4
+  %add.ptr = getelementptr inbounds i8, i8* %main.addr.011, i32 %main_stride
   %2 = bitcast i8* %add.ptr to i32*
-  %3 = load i32* %2, align 4
-  %add.ptr1 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr.sum
+  %3 = load i32, i32* %2, align 4
+  %add.ptr1 = getelementptr inbounds i8, i8* %main.addr.011, i32 %add.ptr.sum
   %4 = bitcast i8* %add.ptr1 to i32*
-  %5 = load i32* %4, align 4
-  %add.ptr2 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr1.sum
+  %5 = load i32, i32* %4, align 4
+  %add.ptr2 = getelementptr inbounds i8, i8* %main.addr.011, i32 %add.ptr1.sum
   %6 = bitcast i8* %add.ptr2 to i32*
-  %7 = load i32* %6, align 4
-  %add.ptr3 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr4.sum
+  %7 = load i32, i32* %6, align 4
+  %add.ptr3 = getelementptr inbounds i8, i8* %main.addr.011, i32 %add.ptr4.sum
   %8 = bitcast i8* %add.ptr3 to i32*
-  %9 = load i32* %8, align 4
+  %9 = load i32, i32* %8, align 4
   %add = add i32 %3, %1
   %add4 = add i32 %add, %5
   %add5 = add i32 %add4, %7
   %add6 = add i32 %add5, %9
   store i32 %add6, i32* %res.addr.09, align 4
-  %add.ptr6 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr3.sum
-  %add.ptr7 = getelementptr inbounds i32* %res.addr.09, i32 %y
+  %add.ptr6 = getelementptr inbounds i8, i8* %main.addr.011, i32 %add.ptr3.sum
+  %add.ptr7 = getelementptr inbounds i32, i32* %res.addr.09, i32 %y
   %inc = add i32 %i.010, 1
   %cmp = icmp eq i32 %inc, %z
   br i1 %cmp, label %for.end, label %for.body
@@ -170,48 +172,48 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %i.07 = phi i32 [ 0, %entry ], [ %inc.3, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %a, i32 %i.07
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %a, i32 %i.07
+  %0 = load i8, i8* %arrayidx, align 1
   %conv5 = zext i8 %0 to i32
-  %arrayidx1 = getelementptr inbounds i8* %b, i32 %i.07
-  %1 = load i8* %arrayidx1, align 1
+  %arrayidx1 = getelementptr inbounds i8, i8* %b, i32 %i.07
+  %1 = load i8, i8* %arrayidx1, align 1
   %conv26 = zext i8 %1 to i32
   %add = add nsw i32 %conv26, %conv5
   %conv3 = trunc i32 %add to i8
-  %arrayidx4 = getelementptr inbounds i8* %c, i32 %i.07
+  %arrayidx4 = getelementptr inbounds i8, i8* %c, i32 %i.07
   store i8 %conv3, i8* %arrayidx4, align 1
   %inc1 = or i32 %i.07, 1
-  %arrayidx.1 = getelementptr inbounds i8* %a, i32 %inc1
-  %2 = load i8* %arrayidx.1, align 1
+  %arrayidx.1 = getelementptr inbounds i8, i8* %a, i32 %inc1
+  %2 = load i8, i8* %arrayidx.1, align 1
   %conv5.1 = zext i8 %2 to i32
-  %arrayidx1.1 = getelementptr inbounds i8* %b, i32 %inc1
-  %3 = load i8* %arrayidx1.1, align 1
+  %arrayidx1.1 = getelementptr inbounds i8, i8* %b, i32 %inc1
+  %3 = load i8, i8* %arrayidx1.1, align 1
   %conv26.1 = zext i8 %3 to i32
   %add.1 = add nsw i32 %conv26.1, %conv5.1
   %conv3.1 = trunc i32 %add.1 to i8
-  %arrayidx4.1 = getelementptr inbounds i8* %c, i32 %inc1
+  %arrayidx4.1 = getelementptr inbounds i8, i8* %c, i32 %inc1
   store i8 %conv3.1, i8* %arrayidx4.1, align 1
   %inc.12 = or i32 %i.07, 2
-  %arrayidx.2 = getelementptr inbounds i8* %a, i32 %inc.12
-  %4 = load i8* %arrayidx.2, align 1
+  %arrayidx.2 = getelementptr inbounds i8, i8* %a, i32 %inc.12
+  %4 = load i8, i8* %arrayidx.2, align 1
   %conv5.2 = zext i8 %4 to i32
-  %arrayidx1.2 = getelementptr inbounds i8* %b, i32 %inc.12
-  %5 = load i8* %arrayidx1.2, align 1
+  %arrayidx1.2 = getelementptr inbounds i8, i8* %b, i32 %inc.12
+  %5 = load i8, i8* %arrayidx1.2, align 1
   %conv26.2 = zext i8 %5 to i32
   %add.2 = add nsw i32 %conv26.2, %conv5.2
   %conv3.2 = trunc i32 %add.2 to i8
-  %arrayidx4.2 = getelementptr inbounds i8* %c, i32 %inc.12
+  %arrayidx4.2 = getelementptr inbounds i8, i8* %c, i32 %inc.12
   store i8 %conv3.2, i8* %arrayidx4.2, align 1
   %inc.23 = or i32 %i.07, 3
-  %arrayidx.3 = getelementptr inbounds i8* %a, i32 %inc.23
-  %6 = load i8* %arrayidx.3, align 1
+  %arrayidx.3 = getelementptr inbounds i8, i8* %a, i32 %inc.23
+  %6 = load i8, i8* %arrayidx.3, align 1
   %conv5.3 = zext i8 %6 to i32
-  %arrayidx1.3 = getelementptr inbounds i8* %b, i32 %inc.23
-  %7 = load i8* %arrayidx1.3, align 1
+  %arrayidx1.3 = getelementptr inbounds i8, i8* %b, i32 %inc.23
+  %7 = load i8, i8* %arrayidx1.3, align 1
   %conv26.3 = zext i8 %7 to i32
   %add.3 = add nsw i32 %conv26.3, %conv5.3
   %conv3.3 = trunc i32 %add.3 to i8
-  %arrayidx4.3 = getelementptr inbounds i8* %c, i32 %inc.23
+  %arrayidx4.3 = getelementptr inbounds i8, i8* %c, i32 %inc.23
   store i8 %conv3.3, i8* %arrayidx4.3, align 1
   %inc.3 = add nsw i32 %i.07, 4
   %exitcond.3 = icmp eq i32 %inc.3, 400
@@ -252,15 +254,15 @@ for.body:
   %i = phi i32 [ %inc4, %for.body ], [ 0, %entry ]
   store i32 %i, i32* %p, align 4
   %inc1 = or i32 %i, 1
-  %add.ptr.i1 = getelementptr inbounds i32* %p, i32 1
+  %add.ptr.i1 = getelementptr inbounds i32, i32* %p, i32 1
   store i32 %inc1, i32* %add.ptr.i1, align 4
   %inc2 = add nsw i32 %i, 2
-  %add.ptr.i2 = getelementptr inbounds i32* %p, i32 2
+  %add.ptr.i2 = getelementptr inbounds i32, i32* %p, i32 2
   store i32 %inc2, i32* %add.ptr.i2, align 4
   %inc3 = add nsw i32 %i, 3
-  %add.ptr.i3 = getelementptr inbounds i32* %p, i32 3
+  %add.ptr.i3 = getelementptr inbounds i32, i32* %p, i32 3
   store i32 %inc3, i32* %add.ptr.i3, align 4
-  %p.next = getelementptr inbounds i32* %p, i32 4
+  %p.next = getelementptr inbounds i32, i32* %p, i32 4
   %inc4 = add nsw i32 %i, 4
   %cmp = icmp slt i32 %inc4, %n
   br i1 %cmp, label %for.body, label %exit
@@ -279,20 +281,20 @@ exit:
 ; X32: jne
 define void @testCmpZero(i8* %src, i8* %dst, i32 %srcidx, i32 %dstidx, i32 %len) nounwind ssp {
 entry:
-  %dest0 = getelementptr inbounds i8* %src, i32 %srcidx
-  %source0 = getelementptr inbounds i8* %dst, i32 %dstidx
+  %dest0 = getelementptr inbounds i8, i8* %src, i32 %srcidx
+  %source0 = getelementptr inbounds i8, i8* %dst, i32 %dstidx
   %add.ptr79.us.sum = add i32 %srcidx, %len
-  %lftr.limit = getelementptr i8* %src, i32 %add.ptr79.us.sum
+  %lftr.limit = getelementptr i8, i8* %src, i32 %add.ptr79.us.sum
   br label %for.body82.us
 
 for.body82.us:
   %dest = phi i8* [ %dest0, %entry ], [ %incdec.ptr91.us, %for.body82.us ]
   %source = phi i8* [ %source0, %entry ], [ %add.ptr83.us, %for.body82.us ]
   %0 = bitcast i8* %source to i32*
-  %1 = load i32* %0, align 4
+  %1 = load i32, i32* %0, align 4
   %trunc = trunc i32 %1 to i8
-  %add.ptr83.us = getelementptr inbounds i8* %source, i32 4
-  %incdec.ptr91.us = getelementptr inbounds i8* %dest, i32 1
+  %add.ptr83.us = getelementptr inbounds i8, i8* %source, i32 4
+  %incdec.ptr91.us = getelementptr inbounds i8, i8* %dest, i32 1
   store i8 %trunc, i8* %dest, align 1
   %exitcond = icmp eq i8* %incdec.ptr91.us, %lftr.limit
   br i1 %exitcond, label %return, label %for.body82.us
diff --git a/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll b/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll
index d8e0aa9dc805..7925bf01020e 100644
--- a/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll
+++ b/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll
@@ -32,15 +32,15 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body.3
   %i.09 = phi i32 [ %add5.3, %for.body.3 ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i8* %a, i32 %i.09
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %a, i32 %i.09
+  %0 = load i8, i8* %arrayidx, align 1
   %conv6 = zext i8 %0 to i32
-  %arrayidx1 = getelementptr inbounds i8* %b, i32 %i.09
-  %1 = load i8* %arrayidx1, align 1
+  %arrayidx1 = getelementptr inbounds i8, i8* %b, i32 %i.09
+  %1 = load i8, i8* %arrayidx1, align 1
   %conv27 = zext i8 %1 to i32
   %add = add nsw i32 %conv27, %conv6
   %conv3 = trunc i32 %add to i8
-  %arrayidx4 = getelementptr inbounds i8* %c, i32 %i.09
+  %arrayidx4 = getelementptr inbounds i8, i8* %c, i32 %i.09
   store i8 %conv3, i8* %arrayidx4, align 1
   %add5 = add i32 %i.09, %s
   %cmp = icmp ult i32 %add5, %len
@@ -50,45 +50,45 @@ for.end:                                          ; preds = %for.body, %for.body
   ret void
 
 for.body.1:                                       ; preds = %for.body
-  %arrayidx.1 = getelementptr inbounds i8* %a, i32 %add5
-  %2 = load i8* %arrayidx.1, align 1
+  %arrayidx.1 = getelementptr inbounds i8, i8* %a, i32 %add5
+  %2 = load i8, i8* %arrayidx.1, align 1
   %conv6.1 = zext i8 %2 to i32
-  %arrayidx1.1 = getelementptr inbounds i8* %b, i32 %add5
-  %3 = load i8* %arrayidx1.1, align 1
+  %arrayidx1.1 = getelementptr inbounds i8, i8* %b, i32 %add5
+  %3 = load i8, i8* %arrayidx1.1, align 1
   %conv27.1 = zext i8 %3 to i32
   %add.1 = add nsw i32 %conv27.1, %conv6.1
   %conv3.1 = trunc i32 %add.1 to i8
-  %arrayidx4.1 = getelementptr inbounds i8* %c, i32 %add5
+  %arrayidx4.1 = getelementptr inbounds i8, i8* %c, i32 %add5
   store i8 %conv3.1, i8* %arrayidx4.1, align 1
   %add5.1 = add i32 %add5, %s
   %cmp.1 = icmp ult i32 %add5.1, %len
   br i1 %cmp.1, label %for.body.2, label %for.end
 
 for.body.2:                                       ; preds = %for.body.1
-  %arrayidx.2 = getelementptr inbounds i8* %a, i32 %add5.1
-  %4 = load i8* %arrayidx.2, align 1
+  %arrayidx.2 = getelementptr inbounds i8, i8* %a, i32 %add5.1
+  %4 = load i8, i8* %arrayidx.2, align 1
   %conv6.2 = zext i8 %4 to i32
-  %arrayidx1.2 = getelementptr inbounds i8* %b, i32 %add5.1
-  %5 = load i8* %arrayidx1.2, align 1
+  %arrayidx1.2 = getelementptr inbounds i8, i8* %b, i32 %add5.1
+  %5 = load i8, i8* %arrayidx1.2, align 1
   %conv27.2 = zext i8 %5 to i32
   %add.2 = add nsw i32 %conv27.2, %conv6.2
   %conv3.2 = trunc i32 %add.2 to i8
-  %arrayidx4.2 = getelementptr inbounds i8* %c, i32 %add5.1
+  %arrayidx4.2 = getelementptr inbounds i8, i8* %c, i32 %add5.1
   store i8 %conv3.2, i8* %arrayidx4.2, align 1
   %add5.2 = add i32 %add5.1, %s
   %cmp.2 = icmp ult i32 %add5.2, %len
   br i1 %cmp.2, label %for.body.3, label %for.end
 
 for.body.3:                                       ; preds = %for.body.2
-  %arrayidx.3 = getelementptr inbounds i8* %a, i32 %add5.2
-  %6 = load i8* %arrayidx.3, align 1
+  %arrayidx.3 = getelementptr inbounds i8, i8* %a, i32 %add5.2
+  %6 = load i8, i8* %arrayidx.3, align 1
   %conv6.3 = zext i8 %6 to i32
-  %arrayidx1.3 = getelementptr inbounds i8* %b, i32 %add5.2
-  %7 = load i8* %arrayidx1.3, align 1
+  %arrayidx1.3 = getelementptr inbounds i8, i8* %b, i32 %add5.2
+  %7 = load i8, i8* %arrayidx1.3, align 1
   %conv27.3 = zext i8 %7 to i32
   %add.3 = add nsw i32 %conv27.3, %conv6.3
   %conv3.3 = trunc i32 %add.3 to i8
-  %arrayidx4.3 = getelementptr inbounds i8* %c, i32 %add5.2
+  %arrayidx4.3 = getelementptr inbounds i8, i8* %c, i32 %add5.2
   store i8 %conv3.3, i8* %arrayidx4.3, align 1
   %add5.3 = add i32 %add5.2, %s
   %cmp.3 = icmp ult i32 %add5.3, %len
diff --git a/test/Transforms/LoopStrengthReduce/X86/no_superflous_induction_vars.ll b/test/Transforms/LoopStrengthReduce/X86/no_superflous_induction_vars.ll
index 55069947240d..a6613c53d786 100644
--- a/test/Transforms/LoopStrengthReduce/X86/no_superflous_induction_vars.ll
+++ b/test/Transforms/LoopStrengthReduce/X86/no_superflous_induction_vars.ll
@@ -38,9 +38,9 @@ for.body14.lr.ph:
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ %0, %for.body14.lr.ph ]
-  %4 = getelementptr inbounds i8* %rowsptr, i64 %index
+  %4 = getelementptr inbounds i8, i8* %rowsptr, i64 %index
   %5 = bitcast i8* %4 to <4 x i8>*
-  %wide.load = load <4 x i8>* %5, align 1
+  %wide.load = load <4 x i8>, <4 x i8>* %5, align 1
   %index.next = add i64 %index, 8
   %6 = icmp eq i64 %index.next, %end.idx.rnd.down
   br i1 %6, label %for.end24, label %vector.body
diff --git a/test/Transforms/LoopStrengthReduce/X86/pr17473.ll b/test/Transforms/LoopStrengthReduce/X86/pr17473.ll
index e7ebaa8ea61b..5b7bb8846044 100644
--- a/test/Transforms/LoopStrengthReduce/X86/pr17473.ll
+++ b/test/Transforms/LoopStrengthReduce/X86/pr17473.ll
@@ -25,9 +25,9 @@ target triple = "x86_64-apple-macosx10.9.0"
 define i32 @main() #0 {
 entry:
   store i8 0, i8* @h, align 1
-  %0 = load i32* @j, align 4
+  %0 = load i32, i32* @j, align 4
   %tobool.i = icmp eq i32 %0, 0
-  %1 = load i32* @d, align 4
+  %1 = load i32, i32* @d, align 4
   %cmp3 = icmp sgt i32 %1, -1
   %.lobit = lshr i32 %1, 31
   %.lobit.not = xor i32 %.lobit, 1
@@ -55,7 +55,7 @@ for.end:                                          ; preds = %fn3.exit
   %conv7 = sext i8 %inc to i32
   %add = add nsw i32 %conv7, %conv
   store i32 %add, i32* @e, align 4
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32 %add) #2
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %add) #2
   ret i32 0
 }
 
diff --git a/test/Transforms/LoopStrengthReduce/addrec-gep-address-space.ll b/test/Transforms/LoopStrengthReduce/addrec-gep-address-space.ll
index 6333291aa65d..5650f81a3087 100644
--- a/test/Transforms/LoopStrengthReduce/addrec-gep-address-space.ll
+++ b/test/Transforms/LoopStrengthReduce/addrec-gep-address-space.ll
@@ -1,15 +1,15 @@
 ; RUN: opt < %s -loop-reduce -S | FileCheck %s
 ; CHECK: bb1:
-; CHECK: load double addrspace(1)* [[IV:%[^,]+]]
+; CHECK: load double, double addrspace(1)* [[IV:%[^,]+]]
 ; CHECK: store double {{.*}}, double addrspace(1)* [[IV]]
 
 ; CHECK-NOT: cast
 ; Make sure the GEP has the right index type
-; CHECK: getelementptr double addrspace(1)* [[IV]], i16 1
+; CHECK: getelementptr double, double addrspace(1)* [[IV]], i16 1
 ; CHECK: br {{.*}} label %bb1
 
 ; Make sure the GEP has the right index type
-; CHECK: getelementptr double addrspace(1)* {{.*}}, i16
+; CHECK: getelementptr double, double addrspace(1)* {{.*}}, i16
 
 
 ; This test tests several things. The load and store should use the
@@ -36,11 +36,11 @@ bb1:		; preds = %bb2, %bb.nph
 	%tmp3 = add i64 %j.01, %tmp1		; <i64> [#uses=1]
 	%tmp4 = add i64 %j.01, %tmp2		; <i64> [#uses=1]
         %z0 = add i64 %tmp3, 5203
-	%tmp5 = getelementptr double addrspace(1)* %p, i64 %z0		; <double addrspace(1)*> [#uses=1]
-	%tmp6 = load double addrspace(1)* %tmp5, align 8		; <double> [#uses=1]
+	%tmp5 = getelementptr double, double addrspace(1)* %p, i64 %z0		; <double addrspace(1)*> [#uses=1]
+	%tmp6 = load double, double addrspace(1)* %tmp5, align 8		; <double> [#uses=1]
 	%tmp7 = fdiv double %tmp6, 2.100000e+00		; <double> [#uses=1]
         %z1 = add i64 %tmp4, 5203
-	%tmp8 = getelementptr double addrspace(1)* %p, i64 %z1		; <double addrspace(1)*> [#uses=1]
+	%tmp8 = getelementptr double, double addrspace(1)* %p, i64 %z1		; <double addrspace(1)*> [#uses=1]
 	store double %tmp7, double addrspace(1)* %tmp8, align 8
 	%tmp9 = add i64 %j.01, 1		; <i64> [#uses=2]
 	br label %bb2
diff --git a/test/Transforms/LoopStrengthReduce/addrec-gep.ll b/test/Transforms/LoopStrengthReduce/addrec-gep.ll
index 3e4e369657b0..6919a33d8a27 100644
--- a/test/Transforms/LoopStrengthReduce/addrec-gep.ll
+++ b/test/Transforms/LoopStrengthReduce/addrec-gep.ll
@@ -1,8 +1,8 @@
 ; RUN: opt < %s -loop-reduce -S | FileCheck %s
 ; CHECK: bb1:
-; CHECK: load double* [[IV:%[^,]+]]
+; CHECK: load double, double* [[IV:%[^,]+]]
 ; CHECK: store double {{.*}}, double* [[IV]]
-; CHECK: getelementptr double*
+; CHECK: getelementptr double, double*
 ; CHECK-NOT: cast
 ; CHECK: br {{.*}} label %bb1
 
@@ -30,11 +30,11 @@ bb1:		; preds = %bb2, %bb.nph
 	%tmp3 = add i64 %j.01, %tmp1		; <i64> [#uses=1]
 	%tmp4 = add i64 %j.01, %tmp2		; <i64> [#uses=1]
         %z0 = add i64 %tmp3, 5203
-	%tmp5 = getelementptr double* %p, i64 %z0		; <double*> [#uses=1]
-	%tmp6 = load double* %tmp5, align 8		; <double> [#uses=1]
+	%tmp5 = getelementptr double, double* %p, i64 %z0		; <double*> [#uses=1]
+	%tmp6 = load double, double* %tmp5, align 8		; <double> [#uses=1]
 	%tmp7 = fdiv double %tmp6, 2.100000e+00		; <double> [#uses=1]
         %z1 = add i64 %tmp4, 5203
-	%tmp8 = getelementptr double* %p, i64 %z1		; <double*> [#uses=1]
+	%tmp8 = getelementptr double, double* %p, i64 %z1		; <double*> [#uses=1]
 	store double %tmp7, double* %tmp8, align 8
 	%tmp9 = add i64 %j.01, 1		; <i64> [#uses=2]
 	br label %bb2
diff --git a/test/Transforms/LoopStrengthReduce/address-space-loop.ll b/test/Transforms/LoopStrengthReduce/address-space-loop.ll
index 9c1b213b5979..57ba665b5f45 100644
--- a/test/Transforms/LoopStrengthReduce/address-space-loop.ll
+++ b/test/Transforms/LoopStrengthReduce/address-space-loop.ll
@@ -27,7 +27,7 @@ bb3:                                              ; preds = %bb2, %bb
 ; CHECK: bb10:
 ; CHECK-NEXT: %t7 = icmp eq i16 %t4, 0
 ; Host %t2 computation outside the loop.
-; CHECK-NEXT: [[SCEVGEP:%[^ ]+]] = getelementptr i8 addrspace(1)* undef, i16 %t4
+; CHECK-NEXT: [[SCEVGEP:%[^ ]+]] = getelementptr i8, i8 addrspace(1)* undef, i16 %t4
 ; CHECK-NEXT: br label %bb14
 bb10:                                             ; preds = %bb9
   %t7 = icmp eq i16 %t4, 0                    ; <i1> [#uses=1]
@@ -36,20 +36,20 @@ bb10:                                             ; preds = %bb9
 
 ; CHECK: bb14:
 ; CHECK-NEXT: store i8 undef, i8 addrspace(1)* [[SCEVGEP]]
-; CHECK-NEXT: %t6 = load float addrspace(1)* addrspace(1)* undef
+; CHECK-NEXT: %t6 = load float addrspace(1)*, float addrspace(1)* addrspace(1)* undef
 ; Fold %t3's add within the address.
-; CHECK-NEXT: [[SCEVGEP1:%[^ ]+]] = getelementptr float addrspace(1)* %t6, i16 4
+; CHECK-NEXT: [[SCEVGEP1:%[^ ]+]] = getelementptr float, float addrspace(1)* %t6, i16 4
 ; CHECK-NEXT: [[SCEVGEP2:%[^ ]+]] = bitcast float addrspace(1)* [[SCEVGEP1]] to i8 addrspace(1)*
 ; Use the induction variable (%t4) to access the right element
-; CHECK-NEXT: [[ADDRESS:%[^ ]+]] = getelementptr i8 addrspace(1)* [[SCEVGEP2]], i16 %t4
+; CHECK-NEXT: [[ADDRESS:%[^ ]+]] = getelementptr i8, i8 addrspace(1)* [[SCEVGEP2]], i16 %t4
 ; CHECK-NEXT: store i8 undef, i8 addrspace(1)* [[ADDRESS]]
 ; CHECK-NEXT: br label %bb14
 bb14:                                             ; preds = %bb14, %bb10
-  %t2 = getelementptr inbounds i8 addrspace(1)* undef, i16 %t4 ; <i8*> [#uses=1]
+  %t2 = getelementptr inbounds i8, i8 addrspace(1)* undef, i16 %t4 ; <i8*> [#uses=1]
   store i8 undef, i8 addrspace(1)* %t2
-  %t6 = load float addrspace(1)* addrspace(1)* undef
+  %t6 = load float addrspace(1)*, float addrspace(1)* addrspace(1)* undef
   %t8 = bitcast float addrspace(1)* %t6 to i8 addrspace(1)*              ; <i8*> [#uses=1]
-  %t9 = getelementptr inbounds i8 addrspace(1)* %t8, i16 %t3 ; <i8*> [#uses=1]
+  %t9 = getelementptr inbounds i8, i8 addrspace(1)* %t8, i16 %t3 ; <i8*> [#uses=1]
   store i8 undef, i8 addrspace(1)* %t9
   br label %bb14
 }
diff --git a/test/Transforms/LoopStrengthReduce/count-to-zero.ll b/test/Transforms/LoopStrengthReduce/count-to-zero.ll
index feb79f8a0c71..ca93e38ab64f 100644
--- a/test/Transforms/LoopStrengthReduce/count-to-zero.ll
+++ b/test/Transforms/LoopStrengthReduce/count-to-zero.ll
@@ -1,6 +1,9 @@
 ; RUN: opt < %s -loop-reduce -S | FileCheck %s
 ; rdar://7382068
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
 define void @t(i32 %c) nounwind optsize {
 entry:
   br label %bb6
@@ -19,7 +22,7 @@ bb3:                                              ; preds = %bb1
   %tmp4 = add i32 %c_addr.1, -1                   ; <i32> [#uses=1]
   %c_addr.1.be = select i1 %tmp2, i32 %tmp3, i32 %tmp4 ; <i32> [#uses=1]
   %indvar.next = add i32 %indvar, 1               ; <i32> [#uses=1]
-; CHECK: add i32 %lsr.iv, -1
+; CHECK: add nsw i32 %lsr.iv, -1
   br label %bb6
 
 bb6:                                              ; preds = %bb3, %entry
diff --git a/test/Transforms/LoopStrengthReduce/different-type-ivs.ll b/test/Transforms/LoopStrengthReduce/different-type-ivs.ll
index 8cdd264591c8..c24f877a5502 100644
--- a/test/Transforms/LoopStrengthReduce/different-type-ivs.ll
+++ b/test/Transforms/LoopStrengthReduce/different-type-ivs.ll
@@ -11,7 +11,7 @@ no_exit:		; preds = %no_exit, %entry
 	%X.0.0 = mul i16 %indvar.upgrd.1, 1234		; <i16> [#uses=1]
 	%tmp. = mul i32 %indvar, 1234		; <i32> [#uses=1]
 	%tmp.5 = sext i16 %X.0.0 to i32		; <i32> [#uses=1]
-	%tmp.3 = call i32 (...)* @bar( i32 %tmp.5, i32 %tmp. )		; <i32> [#uses=0]
+	%tmp.3 = call i32 (...) @bar( i32 %tmp.5, i32 %tmp. )		; <i32> [#uses=0]
 	%tmp.0 = call i1 @pred( )		; <i1> [#uses=1]
 	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=1]
 	br i1 %tmp.0, label %return, label %no_exit
diff --git a/test/Transforms/LoopStrengthReduce/dominate-assert.ll b/test/Transforms/LoopStrengthReduce/dominate-assert.ll
index 3ba93ff74835..bca234c6f3c4 100644
--- a/test/Transforms/LoopStrengthReduce/dominate-assert.ll
+++ b/test/Transforms/LoopStrengthReduce/dominate-assert.ll
@@ -23,7 +23,7 @@ bb4:
   br label %bb9
 bb5:
   %v5 = bitcast i8* %v3 to i32**
-  %add.ptr.i = getelementptr inbounds i32** %v5, i64 %v0
+  %add.ptr.i = getelementptr inbounds i32*, i32** %v5, i64 %v0
   br label %bb6
 bb6:
   %v6 = phi i32** [ null, %bb2 ], [ %add.ptr.i, %bb5 ]
@@ -49,7 +49,7 @@ bb2:
   invoke void @g() optsize
           to label %bb3 unwind label %bb6
 bb3:
-  %arrayctor.next = getelementptr inbounds i8* %arrayctor.cur, i64 1
+  %arrayctor.next = getelementptr inbounds i8, i8* %arrayctor.cur, i64 1
   br label %bb2
 bb4:
   ret void
@@ -76,17 +76,17 @@ entry:
 
 while.cond:                                       ; preds = %while.cond, %entry
   %c.0 = phi i16* [ undef, %entry ], [ %incdec.ptr, %while.cond ]
-  %incdec.ptr = getelementptr inbounds i16* %c.0, i64 1
+  %incdec.ptr = getelementptr inbounds i16, i16* %c.0, i64 1
   br i1 undef, label %while.cond1, label %while.cond
 
 while.cond1:                                      ; preds = %while.cond1, %while.cond
   %c.1 = phi i16* [ %incdec.ptr5, %while.cond1 ], [ %c.0, %while.cond ]
-  %incdec.ptr5 = getelementptr inbounds i16* %c.1, i64 1
+  %incdec.ptr5 = getelementptr inbounds i16, i16* %c.1, i64 1
   br i1 undef, label %while.cond7, label %while.cond1
 
 while.cond7:                                      ; preds = %while.cond7, %while.cond1
   %0 = phi i16* [ %incdec.ptr10, %while.cond7 ], [ %c.1, %while.cond1 ]
-  %incdec.ptr10 = getelementptr inbounds i16* %0, i64 1
+  %incdec.ptr10 = getelementptr inbounds i16, i16* %0, i64 1
   br i1 undef, label %while.cond12.preheader, label %while.cond7
 
 while.cond12.preheader:                           ; preds = %while.cond7
@@ -104,7 +104,7 @@ while.body13.lr.ph:                               ; preds = %while.cond12.outer.
   br label %while.body13
 
 if.else:                                          ; preds = %while.body13
-  %incdec.ptr15 = getelementptr inbounds i16* %1, i64 1
+  %incdec.ptr15 = getelementptr inbounds i16, i16* %1, i64 1
   %cmp = icmp eq i16* %incdec.ptr15, %0
   br i1 %cmp, label %while.end16, label %while.body13
 
diff --git a/test/Transforms/LoopStrengthReduce/dont-hoist-simple-loop-constants.ll b/test/Transforms/LoopStrengthReduce/dont-hoist-simple-loop-constants.ll
index f7a82f6616d2..7b92acee5a91 100644
--- a/test/Transforms/LoopStrengthReduce/dont-hoist-simple-loop-constants.ll
+++ b/test/Transforms/LoopStrengthReduce/dont-hoist-simple-loop-constants.ll
@@ -10,7 +10,7 @@ then.0:
 no_exit.2:		; preds = %no_exit.2, %then.0
 	%indvar630 = phi i32 [ 0, %then.0 ], [ %indvar.next631, %no_exit.2 ]		; <i32> [#uses=4]
 	%gep.upgrd.1 = zext i32 %indvar630 to i64		; <i64> [#uses=1]
-	%tmp.38 = getelementptr [700 x i32]* %nbeaux_.0__558, i32 0, i64 %gep.upgrd.1		; <i32*> [#uses=1]
+	%tmp.38 = getelementptr [700 x i32], [700 x i32]* %nbeaux_.0__558, i32 0, i64 %gep.upgrd.1		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp.38
 	%inc.2 = add i32 %indvar630, 2		; <i32> [#uses=2]
 	%tmp.34 = icmp slt i32 %inc.2, 701		; <i1> [#uses=1]
diff --git a/test/Transforms/LoopStrengthReduce/dont_insert_redundant_ops.ll b/test/Transforms/LoopStrengthReduce/dont_insert_redundant_ops.ll
index 16bb508d2e27..4a6ec50ab97d 100644
--- a/test/Transforms/LoopStrengthReduce/dont_insert_redundant_ops.ll
+++ b/test/Transforms/LoopStrengthReduce/dont_insert_redundant_ops.ll
@@ -12,9 +12,9 @@ define void @test1({ i32, i32 }* %P) {
 	br label %Loop
 Loop:		; preds = %Loop, %0
 	%INDVAR = phi i32 [ 0, %0 ], [ %INDVAR2, %Loop ]		; <i32> [#uses=3]
-	%gep1 = getelementptr { i32, i32 }* %P, i32 %INDVAR, i32 0		; <i32*> [#uses=1]
+	%gep1 = getelementptr { i32, i32 }, { i32, i32 }* %P, i32 %INDVAR, i32 0		; <i32*> [#uses=1]
 	store i32 0, i32* %gep1
-	%gep2 = getelementptr { i32, i32 }* %P, i32 %INDVAR, i32 1		; <i32*> [#uses=1]
+	%gep2 = getelementptr { i32, i32 }, { i32, i32 }* %P, i32 %INDVAR, i32 1		; <i32*> [#uses=1]
 	store i32 0, i32* %gep2
 	%INDVAR2 = add i32 %INDVAR, 1		; <i32> [#uses=1]
 	%cond = call i1 @pred( )		; <i1> [#uses=1]
@@ -28,9 +28,9 @@ define void @test2([2 x i32]* %P) {
 	br label %Loop
 Loop:		; preds = %Loop, %0
 	%INDVAR = phi i32 [ 0, %0 ], [ %INDVAR2, %Loop ]		; <i32> [#uses=3]
-	%gep1 = getelementptr [2 x i32]* %P, i32 %INDVAR, i64 0		; <i32*> [#uses=1]
+	%gep1 = getelementptr [2 x i32], [2 x i32]* %P, i32 %INDVAR, i64 0		; <i32*> [#uses=1]
 	store i32 0, i32* %gep1
-	%gep2 = getelementptr [2 x i32]* %P, i32 %INDVAR, i64 1		; <i32*> [#uses=1]
+	%gep2 = getelementptr [2 x i32], [2 x i32]* %P, i32 %INDVAR, i64 1		; <i32*> [#uses=1]
 	store i32 0, i32* %gep2
 	%INDVAR2 = add i32 %INDVAR, 1		; <i32> [#uses=1]
 	%cond = call i1 @pred( )		; <i1> [#uses=1]
diff --git a/test/Transforms/LoopStrengthReduce/dont_reduce_bytes.ll b/test/Transforms/LoopStrengthReduce/dont_reduce_bytes.ll
index 20300002eb39..4974f485d1c1 100644
--- a/test/Transforms/LoopStrengthReduce/dont_reduce_bytes.ll
+++ b/test/Transforms/LoopStrengthReduce/dont_reduce_bytes.ll
@@ -11,7 +11,7 @@ define void @test(i8* %PTR) {
 	br label %Loop
 Loop:		; preds = %Loop, %0
 	%INDVAR = phi i32 [ 0, %0 ], [ %INDVAR2, %Loop ]		; <i32> [#uses=2]
-	%STRRED = getelementptr i8* %PTR, i32 %INDVAR		; <i8*> [#uses=1]
+	%STRRED = getelementptr i8, i8* %PTR, i32 %INDVAR		; <i8*> [#uses=1]
 	store i8 0, i8* %STRRED
 	%INDVAR2 = add i32 %INDVAR, 1		; <i32> [#uses=2]
         ;; cannot eliminate indvar
diff --git a/test/Transforms/LoopStrengthReduce/dont_reverse.ll b/test/Transforms/LoopStrengthReduce/dont_reverse.ll
index d65213d06af3..551bd03f0ae3 100644
--- a/test/Transforms/LoopStrengthReduce/dont_reverse.ll
+++ b/test/Transforms/LoopStrengthReduce/dont_reverse.ll
@@ -4,6 +4,10 @@
 ; Don't reverse the iteration if the rhs of the compare is defined
 ; inside the loop.
 
+; Provide legal integer types.
+; Declare i2 as legal so that IVUsers accepts to consider %indvar3451
+target datalayout = "n2:8:16:32:64"
+
 define void @Fill_Buffer(i2* %p) nounwind {
 entry:
 	br label %bb8
@@ -11,7 +15,7 @@ entry:
 bb8:
 	%indvar34 = phi i32 [ 0, %entry ], [ %indvar.next35, %bb8 ]
 	%indvar3451 = trunc i32 %indvar34 to i2
-	%xmp4344 = load i2* %p
+	%xmp4344 = load i2, i2* %p
 	%xmp104 = icmp eq i2 %indvar3451, %xmp4344
 	%indvar.next35 = add i32 %indvar34, 1
 	br i1 %xmp104, label %bb10, label %bb8
diff --git a/test/Transforms/LoopStrengthReduce/hoist-parent-preheader.ll b/test/Transforms/LoopStrengthReduce/hoist-parent-preheader.ll
index 7982fbc8c4a5..27371b56e611 100644
--- a/test/Transforms/LoopStrengthReduce/hoist-parent-preheader.ll
+++ b/test/Transforms/LoopStrengthReduce/hoist-parent-preheader.ll
@@ -15,7 +15,7 @@ loop2:                                            ; preds = %loop1, %loop2.backe
   %indvar414 = phi i64 [ %indvar.next415, %loop2.backedge ], [ 0, %loop1 ]
   %tmp473 = mul i64 %indvar414, -4
   %tmp485 = add i64 %tmp484, %tmp473
-  %storemerge4 = getelementptr i8* %a, i64 %tmp485
+  %storemerge4 = getelementptr i8, i8* %a, i64 %tmp485
   %0 = icmp ugt i8* %storemerge4, %a
   br i1 false, label %loop2.exit, label %loop2.backedge
 
diff --git a/test/Transforms/LoopStrengthReduce/invariant_value_first.ll b/test/Transforms/LoopStrengthReduce/invariant_value_first.ll
index 5c18809e59c2..4d59ca9869c2 100644
--- a/test/Transforms/LoopStrengthReduce/invariant_value_first.ll
+++ b/test/Transforms/LoopStrengthReduce/invariant_value_first.ll
@@ -13,7 +13,7 @@ define void @test([10000 x i32]* %P) {
 	br label %Loop
 Loop:		; preds = %Loop, %0
 	%INDVAR = phi i32 [ 0, %0 ], [ %INDVAR2, %Loop ]		; <i32> [#uses=2]
-	%STRRED = getelementptr [10000 x i32]* %P, i32 %outer, i32 %INDVAR		; <i32*> [#uses=1]
+	%STRRED = getelementptr [10000 x i32], [10000 x i32]* %P, i32 %outer, i32 %INDVAR		; <i32*> [#uses=1]
 	store i32 0, i32* %STRRED
 	%INDVAR2 = add i32 %INDVAR, 1		; <i32> [#uses=1]
 	%cond = call i1 @pred( )		; <i1> [#uses=1]
diff --git a/test/Transforms/LoopStrengthReduce/invariant_value_first_arg.ll b/test/Transforms/LoopStrengthReduce/invariant_value_first_arg.ll
index 8eb8f05a8a1f..57716408a298 100644
--- a/test/Transforms/LoopStrengthReduce/invariant_value_first_arg.ll
+++ b/test/Transforms/LoopStrengthReduce/invariant_value_first_arg.ll
@@ -10,7 +10,7 @@ define void @test([10000 x i32]* %P, i32 %outer) {
 	br label %Loop
 Loop:		; preds = %Loop, %0
 	%INDVAR = phi i32 [ 0, %0 ], [ %INDVAR2, %Loop ]		; <i32> [#uses=2]
-	%STRRED = getelementptr [10000 x i32]* %P, i32 %outer, i32 %INDVAR		; <i32*> [#uses=1]
+	%STRRED = getelementptr [10000 x i32], [10000 x i32]* %P, i32 %outer, i32 %INDVAR		; <i32*> [#uses=1]
 	store i32 0, i32* %STRRED
 	%INDVAR2 = add i32 %INDVAR, 1		; <i32> [#uses=1]
 	%cond = call i1 @pred( )		; <i1> [#uses=1]
diff --git a/test/Transforms/LoopStrengthReduce/ivchain.ll b/test/Transforms/LoopStrengthReduce/ivchain.ll
index 233800b71c64..d95220d238ac 100644
--- a/test/Transforms/LoopStrengthReduce/ivchain.ll
+++ b/test/Transforms/LoopStrengthReduce/ivchain.ll
@@ -4,6 +4,10 @@
 ; A sign extend feeds an IVUser and cannot be hoisted into the AddRec.
 ; CollectIVChains should bailout on this case.
 
+
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
 %struct = type { i8*, i8*, i16, i64, i16, i16, i16, i64, i64, i16, i8*, i64, i64, i64 }
 
 ; CHECK-LABEL: @test(
@@ -27,13 +31,13 @@ for.body:                                         ; preds = %sw.epilog, %land.en
   br label %if.end388
 
 if.end388:                                        ; preds = %if.then380, %if.else356
-  %ColLength = getelementptr inbounds %struct* %fbh.0, i64 0, i32 7
+  %ColLength = getelementptr inbounds %struct, %struct* %fbh.0, i64 0, i32 7
   %call405 = call signext i16 @SQLColAttribute(i8* undef, i16 zeroext %conv258, i16 zeroext 1003, i8* null, i16 signext 0, i16* null, i64* %ColLength) nounwind
   br label %sw.epilog
 
 sw.epilog:                                        ; preds = %sw.bb542, %sw.bb523, %if.end475
   %inc601 = add i16 %column_n.0, 1
-  %incdec.ptr = getelementptr inbounds %struct* %fbh.0, i64 1
+  %incdec.ptr = getelementptr inbounds %struct, %struct* %fbh.0, i64 1
   br label %for.body
 
 return:                                           ; preds = %entry
diff --git a/test/Transforms/LoopStrengthReduce/negative-scale.ll b/test/Transforms/LoopStrengthReduce/negative-scale.ll
new file mode 100644
index 000000000000..fdde1b6bf9dc
--- /dev/null
+++ b/test/Transforms/LoopStrengthReduce/negative-scale.ll
@@ -0,0 +1,28 @@
+; RUN: opt < %s -loop-reduce -S | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+
+declare void @foo(i8)
+
+define void @not_addressing_mode(i8* %input, i64 %n) {
+; CHECK-LABEL: @not_addressing_mode(
+entry:
+  br label %loop
+
+loop:
+; CHECK: loop:
+; CHECK: %lsr.iv = phi i8* [ {{%[^,]+}}, %loop ], [ %input, %entry ]
+  %i = phi i64 [ 0, %entry ], [ %i.next, %loop ]
+  %i.next = add i64 %i, 1
+  %j = mul i64 %i, -2
+  ; (%input - 2 * %j) is not foldable. Worth another indvar.
+  %p = getelementptr i8, i8* %input, i64 %j
+  %v = load i8, i8* %p
+; CHECK: %v = load i8, i8* %lsr.iv
+  call void @foo(i8 %v)
+  %exitcond = icmp slt i64 %i.next, %n
+  br i1 %exitcond, label %exit, label %loop
+
+exit:
+  ret void
+}
diff --git a/test/Transforms/LoopStrengthReduce/nested-reduce.ll b/test/Transforms/LoopStrengthReduce/nested-reduce.ll
index 58b8d3eecd03..c05b19d8fdd5 100644
--- a/test/Transforms/LoopStrengthReduce/nested-reduce.ll
+++ b/test/Transforms/LoopStrengthReduce/nested-reduce.ll
@@ -1,5 +1,8 @@
 ; RUN: opt < %s -loop-reduce -S | not grep mul
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
 ; Make sure we don't get a multiply by 6 in this loop.
 
 define i32 @foo(i32 %A, i32 %B, i32 %C, i32 %D) {
diff --git a/test/Transforms/LoopStrengthReduce/ops_after_indvar.ll b/test/Transforms/LoopStrengthReduce/ops_after_indvar.ll
index ec55179d6495..ad2caeb274f4 100644
--- a/test/Transforms/LoopStrengthReduce/ops_after_indvar.ll
+++ b/test/Transforms/LoopStrengthReduce/ops_after_indvar.ll
@@ -15,7 +15,7 @@ define void @test([10000 x i32]* %P) {
 Loop:		; preds = %Loop, %0
 	%INDVAR = phi i32 [ 0, %0 ], [ %INDVAR2, %Loop ]		; <i32> [#uses=2]
 	%idx = call i32 @getidx( )		; <i32> [#uses=1]
-	%STRRED = getelementptr [10000 x i32]* %P, i32 %INDVAR, i32 %idx		; <i32*> [#uses=1]
+	%STRRED = getelementptr [10000 x i32], [10000 x i32]* %P, i32 %INDVAR, i32 %idx		; <i32*> [#uses=1]
 	store i32 0, i32* %STRRED
 	%INDVAR2 = add i32 %INDVAR, 1		; <i32> [#uses=1]
 	%cond = call i1 @pred( )		; <i1> [#uses=1]
diff --git a/test/Transforms/LoopStrengthReduce/phi_node_update_multiple_preds.ll b/test/Transforms/LoopStrengthReduce/phi_node_update_multiple_preds.ll
index 7ef494debdda..6943ab9f29a9 100644
--- a/test/Transforms/LoopStrengthReduce/phi_node_update_multiple_preds.ll
+++ b/test/Transforms/LoopStrengthReduce/phi_node_update_multiple_preds.ll
@@ -10,12 +10,12 @@ entry:
 shortcirc_next:		; preds = %no_exit.2, %entry
 	%indvar37 = phi i32 [ 0, %entry ], [ %indvar.next38, %no_exit.2 ]		; <i32> [#uses=3]
 	%gep.upgrd.1 = zext i32 %indvar37 to i64		; <i64> [#uses=1]
-	%wp.2.4 = getelementptr i8* null, i64 %gep.upgrd.1		; <i8*> [#uses=1]
+	%wp.2.4 = getelementptr i8, i8* null, i64 %gep.upgrd.1		; <i8*> [#uses=1]
 	br i1 false, label %loopexit.2, label %no_exit.2
 no_exit.2:		; preds = %shortcirc_next
 	%wp.2.4.rec = bitcast i32 %indvar37 to i32		; <i32> [#uses=1]
 	%inc.1.rec = add i32 %wp.2.4.rec, 1		; <i32> [#uses=1]
-	%inc.1 = getelementptr i8* null, i32 %inc.1.rec		; <i8*> [#uses=2]
+	%inc.1 = getelementptr i8, i8* null, i32 %inc.1.rec		; <i8*> [#uses=2]
 	%indvar.next38 = add i32 %indvar37, 1		; <i32> [#uses=1]
 	switch i8 0, label %shortcirc_next [
 		 i8 32, label %loopexit.2
diff --git a/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll b/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll
index 45aeb4e691a0..092b274bfc03 100644
--- a/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll
+++ b/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll
@@ -23,19 +23,19 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 define void @_Z15IntegerToStringjjR7Vector2(i32 %i, i32 %radix, %struct.Vector2* nocapture %result) nounwind noinline {
 entry:
   %buffer = alloca [33 x i16], align 16
-  %add.ptr = getelementptr inbounds [33 x i16]* %buffer, i64 0, i64 33
+  %add.ptr = getelementptr inbounds [33 x i16], [33 x i16]* %buffer, i64 0, i64 33
   br label %do.body
 
 do.body:                                          ; preds = %do.body, %entry
   %0 = phi i64 [ %indvar.next44, %do.body ], [ 0, %entry ]
   %i.addr.0 = phi i32 [ %div, %do.body ], [ %i, %entry ]
   %tmp51 = sub i64 32, %0
-  %incdec.ptr = getelementptr [33 x i16]* %buffer, i64 0, i64 %tmp51
+  %incdec.ptr = getelementptr [33 x i16], [33 x i16]* %buffer, i64 0, i64 %tmp51
   %rem = urem i32 %i.addr.0, 10
   %div = udiv i32 %i.addr.0, 10
   %idxprom = zext i32 %rem to i64
-  %arrayidx = getelementptr inbounds [37 x i8]* @.str, i64 0, i64 %idxprom
-  %tmp5 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds [37 x i8], [37 x i8]* @.str, i64 0, i64 %idxprom
+  %tmp5 = load i8, i8* %arrayidx, align 1
   %conv = sext i8 %tmp5 to i16
   store i16 %conv, i16* %incdec.ptr, align 2
   %1 = icmp ugt i32 %i.addr.0, 9
@@ -50,30 +50,30 @@ do.end:                                           ; preds = %do.body
   %sub.ptr.sub = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast
   %sub.ptr.div39 = lshr exact i64 %sub.ptr.sub, 1
   %conv11 = trunc i64 %sub.ptr.div39 to i32
-  %mLength = getelementptr inbounds %struct.Vector2* %result, i64 0, i32 2
+  %mLength = getelementptr inbounds %struct.Vector2, %struct.Vector2* %result, i64 0, i32 2
   %idx.ext21 = bitcast i64 %sub.ptr.div39 to i64
   %incdec.ptr.sum = add i64 %idx.ext21, -1
   %cp.0.sum = sub i64 %incdec.ptr.sum, %0
-  %add.ptr22 = getelementptr [33 x i16]* %buffer, i64 1, i64 %cp.0.sum
+  %add.ptr22 = getelementptr [33 x i16], [33 x i16]* %buffer, i64 1, i64 %cp.0.sum
   %cmp2740 = icmp eq i64 %idx.ext21, 0
   br i1 %cmp2740, label %for.end, label %for.body.lr.ph
 
 for.body.lr.ph:                                   ; preds = %do.end
-  %tmp16 = load i32* %mLength, align 4
-  %mBegin = getelementptr inbounds %struct.Vector2* %result, i64 0, i32 0
-  %tmp14 = load i16** %mBegin, align 8
+  %tmp16 = load i32, i32* %mLength, align 4
+  %mBegin = getelementptr inbounds %struct.Vector2, %struct.Vector2* %result, i64 0, i32 0
+  %tmp14 = load i16*, i16** %mBegin, align 8
   %tmp48 = zext i32 %tmp16 to i64
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %for.body.lr.ph
   %indvar = phi i64 [ 0, %for.body.lr.ph ], [ %indvar.next, %for.body ]
   %tmp46 = add i64 %tmp51, %indvar
-  %p.042 = getelementptr [33 x i16]* %buffer, i64 0, i64 %tmp46
+  %p.042 = getelementptr [33 x i16], [33 x i16]* %buffer, i64 0, i64 %tmp46
   %tmp47 = sub i64 %indvar, %0
-  %incdec.ptr32 = getelementptr [33 x i16]* %buffer, i64 1, i64 %tmp47
+  %incdec.ptr32 = getelementptr [33 x i16], [33 x i16]* %buffer, i64 1, i64 %tmp47
   %tmp49 = add i64 %tmp48, %indvar
-  %dst.041 = getelementptr i16* %tmp14, i64 %tmp49
-  %tmp29 = load i16* %p.042, align 2
+  %dst.041 = getelementptr i16, i16* %tmp14, i64 %tmp49
+  %tmp29 = load i16, i16* %p.042, align 2
   store i16 %tmp29, i16* %dst.041, align 2
   %cmp27 = icmp eq i16* %incdec.ptr32, %add.ptr22
   %indvar.next = add i64 %indvar, 1
@@ -83,7 +83,7 @@ for.end.loopexit:                                 ; preds = %for.body
   br label %for.end
 
 for.end:                                          ; preds = %for.end.loopexit, %do.end
-  %tmp38 = load i32* %mLength, align 4
+  %tmp38 = load i32, i32* %mLength, align 4
   %add = add i32 %tmp38, %conv11
   store i32 %add, i32* %mLength, align 4
   ret void
diff --git a/test/Transforms/LoopStrengthReduce/pr12018.ll b/test/Transforms/LoopStrengthReduce/pr12018.ll
index e493cf85fdef..b15961a77904 100644
--- a/test/Transforms/LoopStrengthReduce/pr12018.ll
+++ b/test/Transforms/LoopStrengthReduce/pr12018.ll
@@ -12,15 +12,15 @@ entry:
 for.body:                                         ; preds = %_ZN8nsTArray9ElementAtEi.exit, %entry
   %i.06 = phi i32 [ %add, %_ZN8nsTArray9ElementAtEi.exit ], [ 0, %entry ]
   %call.i = call %struct.nsTArrayHeader* @_ZN8nsTArray4Hdr2Ev() nounwind
-  %add.ptr.i = getelementptr inbounds %struct.nsTArrayHeader* %call.i, i32 1
+  %add.ptr.i = getelementptr inbounds %struct.nsTArrayHeader, %struct.nsTArrayHeader* %call.i, i32 1
   %tmp = bitcast %struct.nsTArrayHeader* %add.ptr.i to %struct.nsTArray*
-  %arrayidx = getelementptr inbounds %struct.nsTArray* %tmp, i32 %i.06
+  %arrayidx = getelementptr inbounds %struct.nsTArray, %struct.nsTArray* %tmp, i32 %i.06
   %add = add nsw i32 %i.06, 1
-  call void @llvm.dbg.value(metadata %struct.nsTArray* %aValues, i64 0, metadata !0, metadata !{}) nounwind
+  call void @llvm.dbg.value(metadata %struct.nsTArray* %aValues, i64 0, metadata !0, metadata !DIExpression()) nounwind, !dbg !DILocation(scope: !DISubprogram())
   br label %_ZN8nsTArray9ElementAtEi.exit
 
 _ZN8nsTArray9ElementAtEi.exit:                    ; preds = %for.body
-  %arrayidx.i = getelementptr inbounds %struct.nsTArray* %tmp, i32 %add
+  %arrayidx.i = getelementptr inbounds %struct.nsTArray, %struct.nsTArray* %tmp, i32 %add
   call void @_ZN11nsTArray15ComputeDistanceERKS_Rd(%struct.nsTArray* %arrayidx, %struct.nsTArray* %arrayidx.i) nounwind
   %cmp = icmp slt i32 %add, %foo
   br i1 %cmp, label %for.body, label %for.end
@@ -35,4 +35,4 @@ declare %struct.nsTArrayHeader* @_ZN8nsTArray4Hdr2Ev()
 
 declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone
 
-!0 = !{!"0x101"}                       ; [ DW_TAG_arg_variable ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, scope: !DISubprogram())
diff --git a/test/Transforms/LoopStrengthReduce/pr12048.ll b/test/Transforms/LoopStrengthReduce/pr12048.ll
index 7e0f2ad7a3c7..212004b24f8d 100644
--- a/test/Transforms/LoopStrengthReduce/pr12048.ll
+++ b/test/Transforms/LoopStrengthReduce/pr12048.ll
@@ -13,8 +13,8 @@ while.cond40:
     i8 0, label %if.then59
   ]
 while.body51:                                     ; preds = %land.end50
-  %incdec.ptr = getelementptr inbounds i8* %tmp.1, i64 1
-  %scevgep = getelementptr i8* %indvars.iv194, i64 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %tmp.1, i64 1
+  %scevgep = getelementptr i8, i8* %indvars.iv194, i64 1
   br label %while.cond40
 if.then59:                                        ; preds = %while.end
   br i1 undef, label %if.then64, label %if.end113
@@ -29,7 +29,7 @@ while.cond132.preheader:                          ; preds = %if.end113
   %cmp133173 = icmp eq i8* %tmp.1, %tmp.4
   br i1 %cmp133173, label %while.cond40.preheader, label %while.body139.lr.ph
 while.body139.lr.ph:                              ; preds = %while.cond132.preheader
-  %scevgep198 = getelementptr i8* %indvars.iv194, i64 0
+  %scevgep198 = getelementptr i8, i8* %indvars.iv194, i64 0
   %scevgep198199 = ptrtoint i8* %scevgep198 to i64
   br label %while.body139
 while.body139:                                    ; preds = %while.body139, %while.body139.lr.ph
diff --git a/test/Transforms/LoopStrengthReduce/pr12691.ll b/test/Transforms/LoopStrengthReduce/pr12691.ll
index 8399434343eb..e33e40503a3e 100644
--- a/test/Transforms/LoopStrengthReduce/pr12691.ll
+++ b/test/Transforms/LoopStrengthReduce/pr12691.ll
@@ -1,5 +1,8 @@
 ; RUN: opt < %s -loop-reduce -S | FileCheck %s
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
 @d = common global i32 0, align 4
 
 define void @fn2(i32 %x) nounwind uwtable {
@@ -13,13 +16,13 @@ for.cond:
   br i1 %tobool, label %for.cond, label %for.end
 
 for.end:
-; CHECK:  %tmp1 = load i32* @d, align 4
-; CHECK-NEXT:  %tmp2 = load i32* @d, align 4
+; CHECK:  %tmp1 = load i32, i32* @d, align 4
+; CHECK-NEXT:  %tmp2 = load i32, i32* @d, align 4
 ; CHECK-NEXT:  %0 = sub i32 %tmp1, %tmp2
 
-  %tmp1 = load i32* @d, align 4
+  %tmp1 = load i32, i32* @d, align 4
   %add = add nsw i32 %tmp1, %g.0
-  %tmp2 = load i32* @d, align 4
+  %tmp2 = load i32, i32* @d, align 4
   %tobool26 = icmp eq i32 %x, 0
   br i1 %tobool26, label %for.end5, label %for.body.lr.ph
 
diff --git a/test/Transforms/LoopStrengthReduce/pr18165.ll b/test/Transforms/LoopStrengthReduce/pr18165.ll
index cc878c48c4b9..11c9c4ec403f 100644
--- a/test/Transforms/LoopStrengthReduce/pr18165.ll
+++ b/test/Transforms/LoopStrengthReduce/pr18165.ll
@@ -20,10 +20,10 @@ target triple = "x86_64-apple-macosx10.9.0"
 ; Function Attrs: nounwind optsize ssp uwtable
 define i32 @main() #0 {
 entry:
-  %0 = load i32* getelementptr inbounds (%struct.anon* @a, i64 0, i32 0), align 4, !tbaa !1
+  %0 = load i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @a, i64 0, i32 0), align 4, !tbaa !1
   %tobool7.i = icmp eq i32 %0, 0
-  %.promoted.i = load i32* getelementptr inbounds (%struct.anon* @a, i64 0, i32 2), align 4, !tbaa !6
-  %f.promoted.i = load i32* @f, align 4, !tbaa !7
+  %.promoted.i = load i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @a, i64 0, i32 2), align 4, !tbaa !6
+  %f.promoted.i = load i32, i32* @f, align 4, !tbaa !7
   br label %for.body6.i.outer
 
 for.body6.i.outer:                                ; preds = %entry, %lor.end.i
@@ -42,7 +42,7 @@ if.end9.i:                                        ; preds = %for.body6.i.outer
   br i1 %tobool12.i, label %lor.rhs.i, label %lor.end.i
 
 lor.rhs.i:                                        ; preds = %if.end9.i
-  %1 = load i32* @b, align 4, !tbaa !7
+  %1 = load i32, i32* @b, align 4, !tbaa !7
   %dec.i = add nsw i32 %1, -1
   store i32 %dec.i, i32* @b, align 4, !tbaa !7
   %tobool13.i = icmp ne i32 %1, 0
@@ -59,12 +59,12 @@ lor.end.i:                                        ; preds = %lor.rhs.i, %if.end9
 
 fn1.exit:                                         ; preds = %lor.end.i
   store i32 0, i32* @g, align 4, !tbaa !7
-  store i32 %or14.i, i32* getelementptr inbounds (%struct.anon* @a, i64 0, i32 2), align 4, !tbaa !6
+  store i32 %or14.i, i32* getelementptr inbounds (%struct.anon, %struct.anon* @a, i64 0, i32 2), align 4, !tbaa !6
   store i32 %or15.i, i32* @f, align 4, !tbaa !7
-  store i32 %add.i, i32* getelementptr inbounds (%struct.anon* @e, i64 0, i32 1), align 4, !tbaa !8
+  store i32 %add.i, i32* getelementptr inbounds (%struct.anon, %struct.anon* @e, i64 0, i32 1), align 4, !tbaa !8
   store i32 0, i32* @h, align 4, !tbaa !7
-  %3 = load i32* @b, align 4, !tbaa !7
-  %call1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32 %3) #2
+  %3 = load i32, i32* @b, align 4, !tbaa !7
+  %call1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %3) #2
   ret i32 0
 }
 
diff --git a/test/Transforms/LoopStrengthReduce/pr2570.ll b/test/Transforms/LoopStrengthReduce/pr2570.ll
index 7b569713a93d..671ffde671f7 100644
--- a/test/Transforms/LoopStrengthReduce/pr2570.ll
+++ b/test/Transforms/LoopStrengthReduce/pr2570.ll
@@ -23,7 +23,7 @@ define i32 @func_44(i32 %p_45, i32 %p_46, i16 zeroext  %p_48, i32 %p_49, i8 zero
 entry:
 	tail call i32 @func_116( i8 zeroext  2 ) nounwind 		; <i32>:0 [#uses=0]
 	tail call i32 @func_63( i16 signext  2 ) nounwind 		; <i32>:1 [#uses=1]
-	load i16* @g_39, align 2		; <i16>:2 [#uses=1]
+	load i16, i16* @g_39, align 2		; <i16>:2 [#uses=1]
 	tail call i32 @func_63( i16 signext  %2 ) nounwind 		; <i32>:3 [#uses=1]
 	trunc i32 %3 to i16		; <i16>:4 [#uses=1]
 	and i16 %4, 1		; <i16>:5 [#uses=1]
@@ -32,10 +32,10 @@ entry:
 	tail call i32 @func_74( i16 zeroext  %5, i8 zeroext  %6, i16 zeroext  %7, i16 zeroext  0 ) nounwind 		; <i32>:8 [#uses=0]
 	tail call i32 @func_124( i32 544824386 ) nounwind 		; <i32>:9 [#uses=0]
 	zext i8 %p_50 to i32		; <i32>:10 [#uses=1]
-	load i32* @g_43, align 4		; <i32>:11 [#uses=1]
+	load i32, i32* @g_43, align 4		; <i32>:11 [#uses=1]
 	icmp sle i32 %10, %11		; <i1>:12 [#uses=1]
 	zext i1 %12 to i32		; <i32>:13 [#uses=2]
-	load i8* @g_247, align 1		; <i8>:14 [#uses=1]
+	load i8, i8* @g_247, align 1		; <i8>:14 [#uses=1]
 	trunc i32 %p_45 to i16		; <i16>:15 [#uses=1]
 	zext i8 %14 to i16		; <i16>:16 [#uses=1]
 	tail call i32 @func_74( i16 zeroext  %15, i8 zeroext  0, i16 zeroext  %16, i16 zeroext  23618 ) nounwind 		; <i32>:17 [#uses=4]
@@ -72,7 +72,7 @@ bb172:		; preds = %bb168, %bb162
 	icmp eq i32 %.0343, 0		; <i1>:30 [#uses=1]
 	%.0341 = select i1 %30, i32 1, i32 %.0343		; <i32> [#uses=1]
 	urem i32 %23, %.0341		; <i32>:31 [#uses=1]
-	load i32* @g_137, align 4		; <i32>:32 [#uses=4]
+	load i32, i32* @g_137, align 4		; <i32>:32 [#uses=4]
 	icmp slt i32 %32, 0		; <i1>:33 [#uses=1]
 	br i1 %33, label %bb202, label %bb198
 
@@ -119,13 +119,13 @@ bb222:		; preds = %bb215, %bb205
 
 bb223:		; preds = %bb222, %bb215
 	%iftmp.437.0 = phi i32 [ 0, %bb222 ], [ 1, %bb215 ]		; <i32> [#uses=1]
-	load i32* @g_91, align 4		; <i32>:55 [#uses=3]
+	load i32, i32* @g_91, align 4		; <i32>:55 [#uses=3]
 	tail call i32 @func_103( i16 zeroext  4 ) nounwind 		; <i32>:56 [#uses=0]
 	tail call i32 @func_112( i32 0, i16 zeroext  -31374 ) nounwind 		; <i32>:57 [#uses=0]
-	load i32* @g_197, align 4		; <i32>:58 [#uses=1]
+	load i32, i32* @g_197, align 4		; <i32>:58 [#uses=1]
 	tail call i32 @func_124( i32 28156 ) nounwind 		; <i32>:59 [#uses=1]
-	load i32* @g_260, align 4		; <i32>:60 [#uses=1]
-	load i32* @g_43, align 4		; <i32>:61 [#uses=1]
+	load i32, i32* @g_260, align 4		; <i32>:60 [#uses=1]
+	load i32, i32* @g_43, align 4		; <i32>:61 [#uses=1]
 	xor i32 %61, %60		; <i32>:62 [#uses=1]
 	mul i32 %62, %59		; <i32>:63 [#uses=1]
 	trunc i32 %63 to i8		; <i8>:64 [#uses=1]
@@ -138,7 +138,7 @@ bb223:		; preds = %bb222, %bb215
 	%or.cond352 = or i1 %70, %67		; <i1> [#uses=1]
 	select i1 %or.cond352, i32 0, i32 %55		; <i32>:71 [#uses=1]
 	%.353 = ashr i32 %66, %71		; <i32> [#uses=2]
-	load i16* @g_221, align 2		; <i16>:72 [#uses=1]
+	load i16, i16* @g_221, align 2		; <i16>:72 [#uses=1]
 	zext i16 %72 to i32		; <i32>:73 [#uses=1]
 	icmp ugt i32 %.353, 31		; <i1>:74 [#uses=1]
 	select i1 %74, i32 0, i32 %.353		; <i32>:75 [#uses=1]
@@ -146,7 +146,7 @@ bb223:		; preds = %bb222, %bb215
 	add i32 %.0323, %iftmp.437.0		; <i32>:76 [#uses=1]
 	and i32 %48, 255		; <i32>:77 [#uses=2]
 	add i32 %77, 2042556439		; <i32>:78 [#uses=1]
-	load i32* @g_207, align 4		; <i32>:79 [#uses=2]
+	load i32, i32* @g_207, align 4		; <i32>:79 [#uses=2]
 	icmp ugt i32 %79, 31		; <i1>:80 [#uses=1]
 	select i1 %80, i32 0, i32 %79		; <i32>:81 [#uses=1]
 	%.0320 = lshr i32 %77, %81		; <i32> [#uses=1]
@@ -154,7 +154,7 @@ bb223:		; preds = %bb222, %bb215
 	zext i1 %82 to i8		; <i8>:83 [#uses=1]
 	tail call i32 @func_25( i8 zeroext  %83 ) nounwind 		; <i32>:84 [#uses=1]
 	xor i32 %84, 1		; <i32>:85 [#uses=1]
-	load i32* @g_197, align 4		; <i32>:86 [#uses=1]
+	load i32, i32* @g_197, align 4		; <i32>:86 [#uses=1]
 	add i32 %86, 1		; <i32>:87 [#uses=1]
 	add i32 %87, %85		; <i32>:88 [#uses=1]
 	icmp ugt i32 %76, %88		; <i1>:89 [#uses=1]
@@ -163,22 +163,22 @@ bb223:		; preds = %bb222, %bb215
 bb241:		; preds = %bb223
 	store i16 -9, i16* @g_221, align 2
 	udiv i32 %p_52, 1538244727		; <i32>:90 [#uses=1]
-	load i32* @g_207, align 4		; <i32>:91 [#uses=1]
+	load i32, i32* @g_207, align 4		; <i32>:91 [#uses=1]
 	sub i32 %91, %90		; <i32>:92 [#uses=1]
-	load i32* @g_14, align 4		; <i32>:93 [#uses=1]
+	load i32, i32* @g_14, align 4		; <i32>:93 [#uses=1]
 	trunc i32 %93 to i16		; <i16>:94 [#uses=1]
 	trunc i32 %p_46 to i16		; <i16>:95 [#uses=2]
 	sub i16 %94, %95		; <i16>:96 [#uses=1]
-	load i32* @g_197, align 4		; <i32>:97 [#uses=1]
+	load i32, i32* @g_197, align 4		; <i32>:97 [#uses=1]
 	trunc i32 %97 to i16		; <i16>:98 [#uses=1]
 	tail call i32 @func_55( i32 -346178830, i16 zeroext  %98, i16 zeroext  %95 ) nounwind 		; <i32>:99 [#uses=0]
 	zext i16 %p_48 to i32		; <i32>:100 [#uses=1]
-	load i8* @g_247, align 1		; <i8>:101 [#uses=1]
+	load i8, i8* @g_247, align 1		; <i8>:101 [#uses=1]
 	zext i8 %101 to i32		; <i32>:102 [#uses=1]
 	sub i32 %100, %102		; <i32>:103 [#uses=1]
 	tail call i32 @func_55( i32 %103, i16 zeroext  -2972, i16 zeroext  %96 ) nounwind 		; <i32>:104 [#uses=0]
 	xor i32 %92, 2968		; <i32>:105 [#uses=1]
-	load i32* @g_197, align 4		; <i32>:106 [#uses=1]
+	load i32, i32* @g_197, align 4		; <i32>:106 [#uses=1]
 	icmp ugt i32 %105, %106		; <i1>:107 [#uses=1]
 	zext i1 %107 to i32		; <i32>:108 [#uses=1]
 	store i32 %108, i32* @g_33, align 4
@@ -195,12 +195,12 @@ bb248:		; preds = %bb284, %bb241
 
 bb272.thread:		; preds = %bb248
 	store i32 1, i32* @g_82
-	load i16* @g_267, align 2		; <i16>:111 [#uses=1]
+	load i16, i16* @g_267, align 2		; <i16>:111 [#uses=1]
 	icmp eq i16 %111, 0		; <i1>:112 [#uses=1]
 	br i1 %112, label %bb311.loopexit.split, label %bb268
 
 bb255.thread:		; preds = %bb248
-	load i32* @g_260, align 4		; <i32>:113 [#uses=1]
+	load i32, i32* @g_260, align 4		; <i32>:113 [#uses=1]
 	sub i32 %113, %p_52		; <i32>:114 [#uses=1]
 	and i32 %114, -20753		; <i32>:115 [#uses=1]
 	icmp ne i32 %115, 0		; <i1>:116 [#uses=1]
@@ -237,7 +237,7 @@ bb284:		; preds = %bb279, %bb276, %bb255.thread
 	%p_49_addr.0 = phi i32 [ %p_49_addr.1.reg2mem.0, %bb279 ], [ %p_49_addr.1.reg2mem.0, %bb276 ], [ 0, %bb255.thread ]		; <i32> [#uses=1]
 	%p_48_addr.1 = phi i16 [ %124, %bb279 ], [ %118, %bb276 ], [ %p_48_addr.2.reg2mem.0, %bb255.thread ]		; <i16> [#uses=1]
 	%p_45_addr.0 = phi i32 [ %p_45_addr.1.reg2mem.0, %bb279 ], [ %p_45_addr.1.reg2mem.0, %bb276 ], [ 8, %bb255.thread ]		; <i32> [#uses=3]
-	load i32* @g_43, align 4		; <i32>:125 [#uses=1]
+	load i32, i32* @g_43, align 4		; <i32>:125 [#uses=1]
 	trunc i32 %125 to i8		; <i8>:126 [#uses=1]
 	tail call i32 @func_116( i8 zeroext  %126 ) nounwind 		; <i32>:127 [#uses=0]
 	lshr i32 65255, %p_45_addr.0		; <i32>:128 [#uses=1]
@@ -245,7 +245,7 @@ bb284:		; preds = %bb279, %bb276, %bb255.thread
 	%.op = lshr i32 %128, 31		; <i32> [#uses=1]
 	%.op.op = xor i32 %.op, 1		; <i32> [#uses=1]
 	%.354..lobit.not = select i1 %129, i32 1, i32 %.op.op		; <i32> [#uses=1]
-	load i16* @g_39, align 2		; <i16>:130 [#uses=1]
+	load i16, i16* @g_39, align 2		; <i16>:130 [#uses=1]
 	zext i16 %130 to i32		; <i32>:131 [#uses=1]
 	icmp slt i32 %.354..lobit.not, %131		; <i1>:132 [#uses=1]
 	zext i1 %132 to i32		; <i32>:133 [#uses=1]
diff --git a/test/Transforms/LoopStrengthReduce/pr3086.ll b/test/Transforms/LoopStrengthReduce/pr3086.ll
index 599633a11fee..187c14f900a5 100644
--- a/test/Transforms/LoopStrengthReduce/pr3086.ll
+++ b/test/Transforms/LoopStrengthReduce/pr3086.ll
@@ -10,18 +10,18 @@ entry:
 	br label %bb11
 
 bb5:		; preds = %bb9
-	%0 = load %struct.Lit** %storemerge, align 8		; <%struct.Lit*> [#uses=0]
+	%0 = load %struct.Lit*, %struct.Lit** %storemerge, align 8		; <%struct.Lit*> [#uses=0]
 	%indvar.next8 = add i64 %storemerge.rec, 1		; <i64> [#uses=1]
 	br label %bb9
 
 bb9:		; preds = %bb22, %bb5
 	%storemerge.rec = phi i64 [ %indvar.next8, %bb5 ], [ 0, %bb22 ]		; <i64> [#uses=2]
-	%storemerge = getelementptr %struct.Lit** null, i64 %storemerge.rec		; <%struct.Lit**> [#uses=2]
+	%storemerge = getelementptr %struct.Lit*, %struct.Lit** null, i64 %storemerge.rec		; <%struct.Lit**> [#uses=2]
 	%1 = icmp ugt %struct.Lit** null, %storemerge		; <i1> [#uses=1]
 	br i1 %1, label %bb5, label %bb22
 
 bb11:		; preds = %bb22, %entry
-	%2 = load %struct.Cls** null, align 8		; <%struct.Cls*> [#uses=0]
+	%2 = load %struct.Cls*, %struct.Cls** null, align 8		; <%struct.Cls*> [#uses=0]
 	br label %bb22
 
 bb22:		; preds = %bb11, %bb9
diff --git a/test/Transforms/LoopStrengthReduce/pr3399.ll b/test/Transforms/LoopStrengthReduce/pr3399.ll
index 26c5002fdecf..1037768f95c3 100644
--- a/test/Transforms/LoopStrengthReduce/pr3399.ll
+++ b/test/Transforms/LoopStrengthReduce/pr3399.ll
@@ -13,7 +13,7 @@ bb:		; preds = %bb5, %bb5.thread
 
 bb1:		; preds = %bb
 	%l_2.0.reg2mem.0 = sub i32 0, %indvar		; <i32> [#uses=1]
-	%0 = load volatile i32* @g_53, align 4		; <i32> [#uses=1]
+	%0 = load volatile i32, i32* @g_53, align 4		; <i32> [#uses=1]
 	%1 = trunc i32 %l_2.0.reg2mem.0 to i16		; <i16> [#uses=1]
 	%2 = trunc i32 %0 to i16		; <i16> [#uses=1]
 	%3 = mul i16 %2, %1		; <i16> [#uses=1]
diff --git a/test/Transforms/LoopStrengthReduce/pr3571.ll b/test/Transforms/LoopStrengthReduce/pr3571.ll
index a23e4db49705..1615a818771d 100644
--- a/test/Transforms/LoopStrengthReduce/pr3571.ll
+++ b/test/Transforms/LoopStrengthReduce/pr3571.ll
@@ -12,7 +12,7 @@ bb.i:		; preds = %_ZNK11QModelIndex7isValidEv.exit.i
 
 _ZNK11QModelIndex7isValidEv.exit.i:		; preds = %bb.i, %entry
 	%result.0.i = phi i32 [ 0, %entry ], [ %indvar.next, %bb.i ]		; <i32> [#uses=2]
-	%0 = load i32** null, align 4		; <%struct.QAbstractItemDelegate*> [#uses=0]
+	%0 = load i32*, i32** null, align 4		; <%struct.QAbstractItemDelegate*> [#uses=0]
 	br i1 false, label %_ZN18qdesigner_internalL5levelEP18QAbstractItemModelRK11QModelIndex.exit, label %bb.i
 
 _ZN18qdesigner_internalL5levelEP18QAbstractItemModelRK11QModelIndex.exit:		; preds = %_ZNK11QModelIndex7isValidEv.exit.i
diff --git a/test/Transforms/LoopStrengthReduce/preserve-gep-loop-variant.ll b/test/Transforms/LoopStrengthReduce/preserve-gep-loop-variant.ll
index f90d03080056..2b9920c566b2 100644
--- a/test/Transforms/LoopStrengthReduce/preserve-gep-loop-variant.ll
+++ b/test/Transforms/LoopStrengthReduce/preserve-gep-loop-variant.ll
@@ -28,7 +28,7 @@ for.body:
   %conv3 = sext i8 %conv to i64
   %add = add nsw i64 %call, %storemerge1
   %add4 = add nsw i64 %add, %conv3
-  %arrayidx = getelementptr inbounds i8* %p, i64 %add4
+  %arrayidx = getelementptr inbounds i8, i8* %p, i64 %add4
   store i8 0, i8* %arrayidx
   %inc = add nsw i64 %storemerge1, 1
   br label %for.cond
diff --git a/test/Transforms/LoopStrengthReduce/quadradic-exit-value.ll b/test/Transforms/LoopStrengthReduce/quadradic-exit-value.ll
index 65aa61fb937e..483becc0e7b8 100644
--- a/test/Transforms/LoopStrengthReduce/quadradic-exit-value.ll
+++ b/test/Transforms/LoopStrengthReduce/quadradic-exit-value.ll
@@ -1,5 +1,8 @@
 ; RUN: opt < %s -analyze -iv-users | FileCheck %s
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
 ; The value of %r is dependent on a polynomial iteration expression.
 ;
 ; CHECK-LABEL: IV Users for loop %foo.loop
diff --git a/test/Transforms/LoopStrengthReduce/related_indvars.ll b/test/Transforms/LoopStrengthReduce/related_indvars.ll
index 12942bf10a5a..fbe8ffde3547 100644
--- a/test/Transforms/LoopStrengthReduce/related_indvars.ll
+++ b/test/Transforms/LoopStrengthReduce/related_indvars.ll
@@ -14,9 +14,9 @@ entry:
 no_exit:		; preds = %no_exit, %entry
 	%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %no_exit ]		; <i32> [#uses=2]
 	%D_addr.0.0.rec = bitcast i32 %indvar to i32		; <i32> [#uses=2]
-	%D_addr.0.0 = getelementptr double* %D, i32 %D_addr.0.0.rec		; <double*> [#uses=1]
+	%D_addr.0.0 = getelementptr double, double* %D, i32 %D_addr.0.0.rec		; <double*> [#uses=1]
 	%inc.rec = add i32 %D_addr.0.0.rec, 1		; <i32> [#uses=1]
-	%inc = getelementptr double* %D, i32 %inc.rec		; <double*> [#uses=1]
+	%inc = getelementptr double, double* %D, i32 %inc.rec		; <double*> [#uses=1]
 	store double %F, double* %D_addr.0.0
 	%tmp.2 = icmp eq double* %inc, %E		; <i1> [#uses=1]
 	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=1]
diff --git a/test/Transforms/LoopStrengthReduce/remove_indvar.ll b/test/Transforms/LoopStrengthReduce/remove_indvar.ll
index bb395324d4e4..3b92c25389b0 100644
--- a/test/Transforms/LoopStrengthReduce/remove_indvar.ll
+++ b/test/Transforms/LoopStrengthReduce/remove_indvar.ll
@@ -1,6 +1,9 @@
 ; Check that this test makes INDVAR and related stuff dead.
 ; RUN: opt < %s -loop-reduce -S | not grep INDVAR
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
 declare i1 @pred()
 
 define void @test(i32* %P) {
@@ -9,7 +12,7 @@ define void @test(i32* %P) {
 Loop:		; preds = %Loop, %0
         %i = phi i32 [ 0, %0 ], [ %i.next, %Loop ]
 	%INDVAR = phi i32 [ 0, %0 ], [ %INDVAR2, %Loop ]		; <i32> [#uses=2]
-	%STRRED = getelementptr i32* %P, i32 %INDVAR		; <i32*> [#uses=1]
+	%STRRED = getelementptr i32, i32* %P, i32 %INDVAR		; <i32*> [#uses=1]
 	store i32 0, i32* %STRRED
 	%INDVAR2 = add i32 %INDVAR, 1		; <i32> [#uses=1]
         %i.next = add i32 %i, 1
diff --git a/test/Transforms/LoopStrengthReduce/scaling_factor_cost_crash.ll b/test/Transforms/LoopStrengthReduce/scaling_factor_cost_crash.ll
index a652a7661e23..27212d7b97b0 100644
--- a/test/Transforms/LoopStrengthReduce/scaling_factor_cost_crash.ll
+++ b/test/Transforms/LoopStrengthReduce/scaling_factor_cost_crash.ll
@@ -55,7 +55,7 @@ define void @scalingFactorCrash() {
 ; <label>:16                                      ; preds = %16, %15
   %17 = phi i32 [ %21, %16 ], [ undef, %15 ]
   %18 = sub i32 %17, 1623127498
-  %19 = getelementptr inbounds i32* undef, i32 %18
+  %19 = getelementptr inbounds i32, i32* undef, i32 %18
   store i32 undef, i32* %19, align 4
   %20 = add i32 %17, 1623127499
   %21 = add i32 %20, -1623127498
diff --git a/test/Transforms/LoopStrengthReduce/share_code_in_preheader.ll b/test/Transforms/LoopStrengthReduce/share_code_in_preheader.ll
index 412a716bc431..1035ce19ff10 100644
--- a/test/Transforms/LoopStrengthReduce/share_code_in_preheader.ll
+++ b/test/Transforms/LoopStrengthReduce/share_code_in_preheader.ll
@@ -12,10 +12,10 @@ no_exit:		; preds = %no_exit, %entry
 	%indvar = bitcast i32 %indvar.ui to i32		; <i32> [#uses=1]
 	%N_addr.0.0 = sub i32 %N.s, %indvar		; <i32> [#uses=1]
 	%tmp.8 = add i32 %N_addr.0.0, %tmp.6		; <i32> [#uses=2]
-	%tmp.9 = getelementptr i8* %A, i32 %tmp.8		; <i8*> [#uses=1]
-	%tmp.10 = load i8* %tmp.9		; <i8> [#uses=1]
-	%tmp.17 = getelementptr i8* %B, i32 %tmp.8		; <i8*> [#uses=1]
-	%tmp.18 = load i8* %tmp.17		; <i8> [#uses=1]
+	%tmp.9 = getelementptr i8, i8* %A, i32 %tmp.8		; <i8*> [#uses=1]
+	%tmp.10 = load i8, i8* %tmp.9		; <i8> [#uses=1]
+	%tmp.17 = getelementptr i8, i8* %B, i32 %tmp.8		; <i8*> [#uses=1]
+	%tmp.18 = load i8, i8* %tmp.17		; <i8> [#uses=1]
 	%tmp.19 = sub i8 %tmp.10, %tmp.18		; <i8> [#uses=1]
 	%tmp.21 = add i8 %tmp.19, %Sum.0.0		; <i8> [#uses=2]
 	%indvar.next = add i32 %indvar.ui, 1		; <i32> [#uses=2]
diff --git a/test/Transforms/LoopStrengthReduce/uglygep-address-space.ll b/test/Transforms/LoopStrengthReduce/uglygep-address-space.ll
index 2c65261f57f5..a81e314bad86 100644
--- a/test/Transforms/LoopStrengthReduce/uglygep-address-space.ll
+++ b/test/Transforms/LoopStrengthReduce/uglygep-address-space.ll
@@ -27,7 +27,7 @@ bb3:                                              ; preds = %bb2, %bb
 ; CHECK: bb10:
 ; CHECK-NEXT: %t7 = icmp eq i16 %t4, 0
 ; Host %t2 computation outside the loop.
-; CHECK-NEXT: [[SCEVGEP:%[^ ]+]] = getelementptr i8 addrspace(1)* undef, i16 %t4
+; CHECK-NEXT: [[SCEVGEP:%[^ ]+]] = getelementptr i8, i8 addrspace(1)* undef, i16 %t4
 ; CHECK-NEXT: br label %bb14
 bb10:                                             ; preds = %bb9
   %t7 = icmp eq i16 %t4, 0                    ; <i1> [#uses=1]
@@ -36,20 +36,20 @@ bb10:                                             ; preds = %bb9
 
 ; CHECK: bb14:
 ; CHECK-NEXT: store i8 undef, i8 addrspace(1)* [[SCEVGEP]]
-; CHECK-NEXT: %t6 = load float addrspace(1)* addrspace(1)* undef
+; CHECK-NEXT: %t6 = load float addrspace(1)*, float addrspace(1)* addrspace(1)* undef
 ; Fold %t3's add within the address.
-; CHECK-NEXT: [[SCEVGEP1:%[^ ]+]] = getelementptr float addrspace(1)* %t6, i16 4
+; CHECK-NEXT: [[SCEVGEP1:%[^ ]+]] = getelementptr float, float addrspace(1)* %t6, i16 4
 ; CHECK-NEXT: [[SCEVGEP2:%[^ ]+]] = bitcast float addrspace(1)* [[SCEVGEP1]] to i8 addrspace(1)*
 ; Use the induction variable (%t4) to access the right element
-; CHECK-NEXT: [[ADDRESS:%[^ ]+]] = getelementptr i8 addrspace(1)* [[SCEVGEP2]], i16 %t4
+; CHECK-NEXT: [[ADDRESS:%[^ ]+]] = getelementptr i8, i8 addrspace(1)* [[SCEVGEP2]], i16 %t4
 ; CHECK-NEXT: store i8 undef, i8 addrspace(1)* [[ADDRESS]]
 ; CHECK-NEXT: br label %bb14
 bb14:                                             ; preds = %bb14, %bb10
-  %t2 = getelementptr inbounds i8 addrspace(1)* undef, i16 %t4 ; <i8*> [#uses=1]
+  %t2 = getelementptr inbounds i8, i8 addrspace(1)* undef, i16 %t4 ; <i8*> [#uses=1]
   store i8 undef, i8 addrspace(1)* %t2
-  %t6 = load float addrspace(1)* addrspace(1)* undef
+  %t6 = load float addrspace(1)*, float addrspace(1)* addrspace(1)* undef
   %t8 = bitcast float addrspace(1)* %t6 to i8 addrspace(1)*              ; <i8*> [#uses=1]
-  %t9 = getelementptr inbounds i8 addrspace(1)* %t8, i16 %t3 ; <i8*> [#uses=1]
+  %t9 = getelementptr inbounds i8, i8 addrspace(1)* %t8, i16 %t3 ; <i8*> [#uses=1]
   store i8 undef, i8 addrspace(1)* %t9
   br label %bb14
 }
diff --git a/test/Transforms/LoopStrengthReduce/uglygep.ll b/test/Transforms/LoopStrengthReduce/uglygep.ll
index 4562d29a0a20..430127b3cd5d 100644
--- a/test/Transforms/LoopStrengthReduce/uglygep.ll
+++ b/test/Transforms/LoopStrengthReduce/uglygep.ll
@@ -24,7 +24,7 @@ bb3:                                              ; preds = %bb2, %bb
 ; CHECK: bb10:
 ; CHECK-NEXT: %t7 = icmp eq i64 %t4, 0
 ; Host %t2 computation outside the loop.
-; CHECK-NEXT: [[SCEVGEP:%[^ ]+]] = getelementptr i8* undef, i64 %t4
+; CHECK-NEXT: [[SCEVGEP:%[^ ]+]] = getelementptr i8, i8* undef, i64 %t4
 ; CHECK-NEXT: br label %bb14
 bb10:                                             ; preds = %bb9
   %t7 = icmp eq i64 %t4, 0                    ; <i1> [#uses=1]
@@ -33,20 +33,20 @@ bb10:                                             ; preds = %bb9
 
 ; CHECK: bb14:
 ; CHECK-NEXT: store i8 undef, i8* [[SCEVGEP]]
-; CHECK-NEXT: %t6 = load float** undef
+; CHECK-NEXT: %t6 = load float*, float** undef
 ; Fold %t3's add within the address.
-; CHECK-NEXT: [[SCEVGEP1:%[^ ]+]] = getelementptr float* %t6, i64 4
+; CHECK-NEXT: [[SCEVGEP1:%[^ ]+]] = getelementptr float, float* %t6, i64 4
 ; CHECK-NEXT: [[SCEVGEP2:%[^ ]+]] = bitcast float* [[SCEVGEP1]] to i8*
 ; Use the induction variable (%t4) to access the right element
-; CHECK-NEXT: [[ADDRESS:%[^ ]+]] = getelementptr i8* [[SCEVGEP2]], i64 %t4
+; CHECK-NEXT: [[ADDRESS:%[^ ]+]] = getelementptr i8, i8* [[SCEVGEP2]], i64 %t4
 ; CHECK-NEXT: store i8 undef, i8* [[ADDRESS]]
 ; CHECK-NEXT: br label %bb14
 bb14:                                             ; preds = %bb14, %bb10
-  %t2 = getelementptr inbounds i8* undef, i64 %t4 ; <i8*> [#uses=1]
+  %t2 = getelementptr inbounds i8, i8* undef, i64 %t4 ; <i8*> [#uses=1]
   store i8 undef, i8* %t2
-  %t6 = load float** undef
+  %t6 = load float*, float** undef
   %t8 = bitcast float* %t6 to i8*              ; <i8*> [#uses=1]
-  %t9 = getelementptr inbounds i8* %t8, i64 %t3 ; <i8*> [#uses=1]
+  %t9 = getelementptr inbounds i8, i8* %t8, i64 %t3 ; <i8*> [#uses=1]
   store i8 undef, i8* %t9
   br label %bb14
 }
@@ -59,7 +59,7 @@ bb:
 ; CHECK: loop0:
 ; Induction variable is initialized to -2.
 ; CHECK-NEXT: [[PHIIV:%[^ ]+]] = phi i32 [ [[IVNEXT:%[^ ]+]], %loop0 ], [ -2, %bb ]
-; CHECK-NEXT: [[IVNEXT]] = add i32 [[PHIIV]], 1
+; CHECK-NEXT: [[IVNEXT]] = add nuw nsw i32 [[PHIIV]], 1
 ; CHECK-NEXT: br i1 false, label %loop0, label %bb0
 loop0:                                            ; preds = %loop0, %bb
   %i0 = phi i32 [ %i0.next, %loop0 ], [ 0, %bb ]  ; <i32> [#uses=2]
diff --git a/test/Transforms/LoopStrengthReduce/use_postinc_value_outside_loop.ll b/test/Transforms/LoopStrengthReduce/use_postinc_value_outside_loop.ll
index 005e4c6b22c1..a673768d770e 100644
--- a/test/Transforms/LoopStrengthReduce/use_postinc_value_outside_loop.ll
+++ b/test/Transforms/LoopStrengthReduce/use_postinc_value_outside_loop.ll
@@ -16,7 +16,7 @@ no_exit.2:		; preds = %no_exit.2, %then.0
 	%indvar630.ui = phi i32 [ 0, %then.0 ], [ %indvar.next631, %no_exit.2 ]		; <i32> [#uses=3]
 	%indvar630 = bitcast i32 %indvar630.ui to i32		; <i32> [#uses=2]
 	%gep.upgrd.1 = zext i32 %indvar630.ui to i64		; <i64> [#uses=1]
-	%tmp.38 = getelementptr [700 x i32]* %nbeaux_.0__558, i32 0, i64 %gep.upgrd.1		; <i32*> [#uses=1]
+	%tmp.38 = getelementptr [700 x i32], [700 x i32]* %nbeaux_.0__558, i32 0, i64 %gep.upgrd.1		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp.38
 	%inc.2 = add i32 %indvar630, 2		; <i32> [#uses=1]
 	%tmp.34 = call i1 @pred( i32 %indvar630 )		; <i1> [#uses=1]
diff --git a/test/Transforms/LoopStrengthReduce/var_stride_used_by_compare.ll b/test/Transforms/LoopStrengthReduce/var_stride_used_by_compare.ll
index 3405b26f1f38..2dd14a0e5986 100644
--- a/test/Transforms/LoopStrengthReduce/var_stride_used_by_compare.ll
+++ b/test/Transforms/LoopStrengthReduce/var_stride_used_by_compare.ll
@@ -28,7 +28,7 @@ bb:		; preds = %bb, %bb.preheader
 	%tmp.16 = add i32 %tmp.15, %tmp.		; <i32> [#uses=2]
 	%k_addr.0.0 = bitcast i32 %tmp.16 to i32		; <i32> [#uses=1]
 	%gep.upgrd.1 = zext i32 %tmp.16 to i64		; <i64> [#uses=1]
-	%tmp = getelementptr [8193 x i8]* @flags2, i32 0, i64 %gep.upgrd.1		; <i8*> [#uses=1]
+	%tmp = getelementptr [8193 x i8], [8193 x i8]* @flags2, i32 0, i64 %gep.upgrd.1		; <i8*> [#uses=1]
 	store i8 0, i8* %tmp
 	%k_addr.0 = add i32 %k_addr.0.0, %i.s		; <i32> [#uses=1]
 	%tmp.upgrd.2 = icmp sgt i32 %k_addr.0, 8192		; <i1> [#uses=1]
diff --git a/test/Transforms/LoopStrengthReduce/variable_stride.ll b/test/Transforms/LoopStrengthReduce/variable_stride.ll
index 7c0f053e4c34..f82b2fc29ac5 100644
--- a/test/Transforms/LoopStrengthReduce/variable_stride.ll
+++ b/test/Transforms/LoopStrengthReduce/variable_stride.ll
@@ -1,6 +1,9 @@
 ; Check that variable strides are reduced to adds instead of multiplies.
 ; RUN: opt < %s -loop-reduce -S | not grep mul
 
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
 declare i1 @pred(i32)
 
 define void @test([10000 x i32]* %P, i32 %STRIDE) {
diff --git a/test/Transforms/LoopUnroll/2007-05-05-UnrollMiscomp.ll b/test/Transforms/LoopUnroll/2007-05-05-UnrollMiscomp.ll
index d4c8402bd2c6..95e9dde04e6f 100644
--- a/test/Transforms/LoopUnroll/2007-05-05-UnrollMiscomp.ll
+++ b/test/Transforms/LoopUnroll/2007-05-05-UnrollMiscomp.ll
@@ -9,11 +9,11 @@ target triple = "i686-apple-darwin8"
 define void @Foo(%struct.__mpz_struct* %base) {
 entry:
         %want = alloca [1 x %struct.__mpz_struct], align 16             ; <[1 x %struct.__mpz_struct]*> [#uses=4]
-        %want1 = getelementptr [1 x %struct.__mpz_struct]* %want, i32 0, i32 0          ; <%struct.__mpz_struct*> [#uses=1]
+        %want1 = getelementptr [1 x %struct.__mpz_struct], [1 x %struct.__mpz_struct]* %want, i32 0, i32 0          ; <%struct.__mpz_struct*> [#uses=1]
         call void @__gmpz_init( %struct.__mpz_struct* %want1 )
-        %want27 = getelementptr [1 x %struct.__mpz_struct]* %want, i32 0, i32 0         ; <%struct.__mpz_struct*> [#uses=1]
-        %want3 = getelementptr [1 x %struct.__mpz_struct]* %want, i32 0, i32 0          ; <%struct.__mpz_struct*> [#uses=1]
-        %want2 = getelementptr [1 x %struct.__mpz_struct]* %want, i32 0, i32 0          ; <%struct.__mpz_struct*> [#uses=2]
+        %want27 = getelementptr [1 x %struct.__mpz_struct], [1 x %struct.__mpz_struct]* %want, i32 0, i32 0         ; <%struct.__mpz_struct*> [#uses=1]
+        %want3 = getelementptr [1 x %struct.__mpz_struct], [1 x %struct.__mpz_struct]* %want, i32 0, i32 0          ; <%struct.__mpz_struct*> [#uses=1]
+        %want2 = getelementptr [1 x %struct.__mpz_struct], [1 x %struct.__mpz_struct]* %want, i32 0, i32 0          ; <%struct.__mpz_struct*> [#uses=2]
         br label %bb
 
 bb:             ; preds = %bb, %entry
diff --git a/test/Transforms/LoopUnroll/2011-08-08-PhiUpdate.ll b/test/Transforms/LoopUnroll/2011-08-08-PhiUpdate.ll
index bf6d6d5989c9..a87b16a28b7c 100644
--- a/test/Transforms/LoopUnroll/2011-08-08-PhiUpdate.ll
+++ b/test/Transforms/LoopUnroll/2011-08-08-PhiUpdate.ll
@@ -46,8 +46,8 @@ bb.nph:                                           ; preds = %entry
 bb:                                               ; preds = %bb.nph, %bb1
   %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb1 ] ; <i64> [#uses=2]
   %s.01 = phi i32 [ 0, %bb.nph ], [ %2, %bb1 ]    ; <i32> [#uses=1]
-  %scevgep = getelementptr i32* %p, i64 %indvar   ; <i32*> [#uses=1]
-  %1 = load i32* %scevgep, align 1                ; <i32> [#uses=1]
+  %scevgep = getelementptr i32, i32* %p, i64 %indvar   ; <i32*> [#uses=1]
+  %1 = load i32, i32* %scevgep, align 1                ; <i32> [#uses=1]
   %2 = add nsw i32 %1, %s.01                      ; <i32> [#uses=2]
   br label %bb1
 
@@ -84,7 +84,7 @@ do.body:                                          ; preds = %do.cond, %if.end
   br i1 %cond2, label %exit, label %do.cond
 
 exit:                  ; preds = %do.body
-  %tmp7.i = load i32* undef, align 8
+  %tmp7.i = load i32, i32* undef, align 8
   br i1 undef, label %do.cond, label %land.lhs.true
 
 land.lhs.true:                                    ; preds = %exit
diff --git a/test/Transforms/LoopUnroll/2011-08-09-IVSimplify.ll b/test/Transforms/LoopUnroll/2011-08-09-IVSimplify.ll
index a43a4ffc557c..0b4840956501 100644
--- a/test/Transforms/LoopUnroll/2011-08-09-IVSimplify.ll
+++ b/test/Transforms/LoopUnroll/2011-08-09-IVSimplify.ll
@@ -12,11 +12,11 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; CHECK: while.body:
 ; CHECK-NOT: while.body.1:
 ; CHECK: %shr.1 = lshr i32 %bit_addr.addr.01, 5
-; CHECK: %arrayidx.1 = getelementptr inbounds i32* %bitmap, i32 %shr.1
+; CHECK: %arrayidx.1 = getelementptr inbounds i32, i32* %bitmap, i32 %shr.1
 ; CHECK: %shr.2 = lshr i32 %bit_addr.addr.01, 5
-; CHECK: %arrayidx.2 = getelementptr inbounds i32* %bitmap, i32 %shr.2
+; CHECK: %arrayidx.2 = getelementptr inbounds i32, i32* %bitmap, i32 %shr.2
 ; CHECK: %shr.3 = lshr i32 %bit_addr.addr.01, 5
-; CHECK: %arrayidx.3 = getelementptr inbounds i32* %bitmap, i32 %shr.3
+; CHECK: %arrayidx.3 = getelementptr inbounds i32, i32* %bitmap, i32 %shr.3
 define void @FlipBit(i32* nocapture %bitmap, i32 %bit_addr, i32 %nbits) nounwind {
 entry:
   br label %while.body
@@ -28,8 +28,8 @@ while.body:
   %shr = lshr i32 %bit_addr.addr.01, 5
   %rem = and i32 %bit_addr.addr.01, 31
   %shl = shl i32 1, %rem
-  %arrayidx = getelementptr inbounds i32* %bitmap, i32 %shr
-  %tmp6 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %bitmap, i32 %shr
+  %tmp6 = load i32, i32* %arrayidx, align 4
   %xor = xor i32 %tmp6, %shl
   store i32 %xor, i32* %arrayidx, align 4
   %inc = add i32 %bit_addr.addr.01, 1
diff --git a/test/Transforms/LoopUnroll/2011-10-01-NoopTrunc.ll b/test/Transforms/LoopUnroll/2011-10-01-NoopTrunc.ll
index 617d4dbe8fdd..5f9eec72ba50 100644
--- a/test/Transforms/LoopUnroll/2011-10-01-NoopTrunc.ll
+++ b/test/Transforms/LoopUnroll/2011-10-01-NoopTrunc.ll
@@ -21,8 +21,8 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %sum.02 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds i8* %arr, i64 %indvars.iv
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %arr, i64 %indvars.iv
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = sext i8 %0 to i32
   %add = add nsw i32 %conv, %sum.02
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopUnroll/AArch64/lit.local.cfg b/test/Transforms/LoopUnroll/AArch64/lit.local.cfg
new file mode 100644
index 000000000000..cec29af5bbe4
--- /dev/null
+++ b/test/Transforms/LoopUnroll/AArch64/lit.local.cfg
@@ -0,0 +1,3 @@
+if not 'AArch64' in config.root.targets:
+    config.unsupported = True
+
diff --git a/test/Transforms/LoopUnroll/AArch64/partial.ll b/test/Transforms/LoopUnroll/AArch64/partial.ll
new file mode 100644
index 000000000000..8a1ea80c9d5b
--- /dev/null
+++ b/test/Transforms/LoopUnroll/AArch64/partial.ll
@@ -0,0 +1,76 @@
+; RUN: opt < %s -S -loop-unroll -mtriple aarch64 -mcpu=cortex-a57 | FileCheck %s
+
+; Partial unroll 8 times for this loop.
+define void @unroll1() nounwind {
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i32 [ 0, %entry ], [ %inc, %loop ]
+  %inc = add i32 %iv, 1
+  %exitcnd = icmp uge i32 %inc, 1024
+  br i1 %exitcnd, label %exit, label %loop
+
+exit:
+  ret void
+}
+
+; CHECK:      add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: icmp
+
+; Partial unroll 16 times for this loop.
+define void @unroll2() nounwind {
+entry:
+  br label %loop1
+
+loop1:
+  %iv1 = phi i32 [ 0, %entry ], [ %inc1, %loop1.latch ]
+  br label %loop2.header
+
+loop2.header:
+  br label %loop2
+
+loop2:
+  %iv2 = phi i32 [ 0, %loop2.header ], [ %inc2, %loop2 ]
+  %inc2 = add i32 %iv2, 1
+  %exitcnd2 = icmp uge i32 %inc2, 1024
+  br i1 %exitcnd2, label %exit2, label %loop2
+
+exit2:
+  br label %loop1.latch
+
+loop1.latch:
+  %inc1 = add i32 %iv1, 1
+  %exitcnd1 = icmp uge i32 %inc1, 1024
+  br i1 %exitcnd2, label %exit, label %loop1
+
+exit:
+  ret void
+}
+
+
+
+; CHECK:      add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: icmp
diff --git a/test/Transforms/LoopUnroll/AArch64/runtime-loop.ll b/test/Transforms/LoopUnroll/AArch64/runtime-loop.ll
new file mode 100644
index 000000000000..d3dc081fa6f8
--- /dev/null
+++ b/test/Transforms/LoopUnroll/AArch64/runtime-loop.ll
@@ -0,0 +1,33 @@
+; RUN: opt < %s -S -loop-unroll -mtriple aarch64 -mcpu=cortex-a57 | FileCheck %s
+
+; Tests for unrolling loops with run-time trip counts
+
+; CHECK:  %xtraiter = and i32 %n
+; CHECK:  %lcmp.mod = icmp ne i32 %xtraiter, 0
+; CHECK:  br i1 %lcmp.mod, label %for.body.prol, label %for.body.preheader.split
+
+; CHECK:  for.body.prol:
+; CHECK:  for.body:
+
+define i32 @test(i32* nocapture %a, i32 %n) nounwind uwtable readonly {
+entry:
+  %cmp1 = icmp eq i32 %n, 0
+  br i1 %cmp1, label %for.end, label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %sum.02 = phi i32 [ %add, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %add = add nsw i32 %0, %sum.02
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
+  ret i32 %sum.0.lcssa
+}
+
+
diff --git a/test/Transforms/LoopUnroll/PowerPC/a2-high-cost-trip-count-computation.ll b/test/Transforms/LoopUnroll/PowerPC/a2-high-cost-trip-count-computation.ll
new file mode 100644
index 000000000000..bd5f68f9f200
--- /dev/null
+++ b/test/Transforms/LoopUnroll/PowerPC/a2-high-cost-trip-count-computation.ll
@@ -0,0 +1,27 @@
+; RUN: opt < %s -S -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -loop-unroll | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+;; Check that we do emit expensive instructions to compute trip
+;; counts when unrolling loops on the a2 (because we unroll a lot).
+
+define i32 @test(i64 %v12, i8* %array, i64* %loc) {
+; CHECK-LABEL: @test(
+; CHECK: udiv
+entry:
+  %step = load i64, i64* %loc, !range !0
+  br label %loop
+
+loop:                                           ; preds = %entry, %loop
+  %k.015 = phi i64 [ %v15, %loop ], [ %v12, %entry ]
+  %v14 = getelementptr inbounds i8, i8* %array, i64 %k.015
+  store i8 0, i8* %v14
+  %v15 = add nuw nsw i64 %k.015, %step
+  %v16 = icmp slt i64 %v15, 8193
+  br i1 %v16, label %loop, label %loopexit
+
+loopexit:                             ; preds = %loop
+  ret i32 0
+}
+
+!0 = !{i64 1, i64 100}
diff --git a/test/Transforms/LoopUnroll/PowerPC/a2-unrolling.ll b/test/Transforms/LoopUnroll/PowerPC/a2-unrolling.ll
index aae79cbac789..e9aa1acd5fec 100644
--- a/test/Transforms/LoopUnroll/PowerPC/a2-unrolling.ll
+++ b/test/Transforms/LoopUnroll/PowerPC/a2-unrolling.ll
@@ -27,8 +27,8 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %sum.02 = phi i32 [ %add, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %sum.02
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopUnroll/X86/partial.ll b/test/Transforms/LoopUnroll/X86/partial.ll
index a2b04c7d85f8..4566f792deb4 100644
--- a/test/Transforms/LoopUnroll/X86/partial.ll
+++ b/test/Transforms/LoopUnroll/X86/partial.ll
@@ -9,20 +9,20 @@ entry:
 
 vector.body:                                      ; preds = %vector.body, %entry
   %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
-  %0 = getelementptr inbounds double* %b, i64 %index
+  %0 = getelementptr inbounds double, double* %b, i64 %index
   %1 = bitcast double* %0 to <2 x double>*
-  %wide.load = load <2 x double>* %1, align 8
+  %wide.load = load <2 x double>, <2 x double>* %1, align 8
   %.sum9 = or i64 %index, 2
-  %2 = getelementptr double* %b, i64 %.sum9
+  %2 = getelementptr double, double* %b, i64 %.sum9
   %3 = bitcast double* %2 to <2 x double>*
-  %wide.load8 = load <2 x double>* %3, align 8
+  %wide.load8 = load <2 x double>, <2 x double>* %3, align 8
   %4 = fadd <2 x double> %wide.load, <double 1.000000e+00, double 1.000000e+00>
   %5 = fadd <2 x double> %wide.load8, <double 1.000000e+00, double 1.000000e+00>
-  %6 = getelementptr inbounds double* %a, i64 %index
+  %6 = getelementptr inbounds double, double* %a, i64 %index
   %7 = bitcast double* %6 to <2 x double>*
   store <2 x double> %4, <2 x double>* %7, align 8
   %.sum10 = or i64 %index, 2
-  %8 = getelementptr double* %a, i64 %.sum10
+  %8 = getelementptr double, double* %a, i64 %.sum10
   %9 = bitcast double* %8 to <2 x double>*
   store <2 x double> %5, <2 x double>* %9, align 8
   %index.next = add i64 %index, 4
@@ -45,12 +45,12 @@ entry:
 
 vector.body:                                      ; preds = %vector.body, %entry
   %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
-  %v0 = getelementptr inbounds double* %b, i64 %index
+  %v0 = getelementptr inbounds double, double* %b, i64 %index
   %v1 = bitcast double* %v0 to <2 x double>*
-  %wide.load = load <2 x double>* %v1, align 8
+  %wide.load = load <2 x double>, <2 x double>* %v1, align 8
   %v4 = fadd <2 x double> %wide.load, <double 1.000000e+00, double 1.000000e+00>
   %v5 = fmul <2 x double> %v4, <double 8.000000e+00, double 8.000000e+00>
-  %v6 = getelementptr inbounds double* %a, i64 %index
+  %v6 = getelementptr inbounds double, double* %a, i64 %index
   %v7 = bitcast double* %v6 to <2 x double>*
   store <2 x double> %v5, <2 x double>* %v7, align 8
   %index.next = add i64 %index, 2
@@ -84,18 +84,18 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %reduction.026 = phi i16 [ %add14, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i16* %arr, i64 %indvars.iv
-  %0 = load i16* %arrayidx, align 2
+  %arrayidx = getelementptr inbounds i16, i16* %arr, i64 %indvars.iv
+  %0 = load i16, i16* %arrayidx, align 2
   %add = add i16 %0, %reduction.026
   %sext = mul i64 %indvars.iv, 12884901888
   %idxprom3 = ashr exact i64 %sext, 32
-  %arrayidx4 = getelementptr inbounds i16* %arr, i64 %idxprom3
-  %1 = load i16* %arrayidx4, align 2
+  %arrayidx4 = getelementptr inbounds i16, i16* %arr, i64 %idxprom3
+  %1 = load i16, i16* %arrayidx4, align 2
   %add7 = add i16 %add, %1
   %sext28 = mul i64 %indvars.iv, 21474836480
   %idxprom10 = ashr exact i64 %sext28, 32
-  %arrayidx11 = getelementptr inbounds i16* %arr, i64 %idxprom10
-  %2 = load i16* %arrayidx11, align 2
+  %arrayidx11 = getelementptr inbounds i16, i16* %arr, i64 %idxprom10
+  %2 = load i16, i16* %arrayidx11, align 2
   %add14 = add i16 %add7, %2
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopUnroll/ephemeral.ll b/test/Transforms/LoopUnroll/ephemeral.ll
index 9d4061390537..d16eba7a9644 100644
--- a/test/Transforms/LoopUnroll/ephemeral.ll
+++ b/test/Transforms/LoopUnroll/ephemeral.ll
@@ -12,8 +12,8 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %sum.01 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
 
   ; This loop will be completely unrolled, even with these extra instructions,
   ; but only because they're ephemeral (and, thus, free).
diff --git a/test/Transforms/LoopUnroll/full-unroll-bad-geps.ll b/test/Transforms/LoopUnroll/full-unroll-bad-geps.ll
new file mode 100644
index 000000000000..4c99bc73880b
--- /dev/null
+++ b/test/Transforms/LoopUnroll/full-unroll-bad-geps.ll
@@ -0,0 +1,34 @@
+; Check that we don't crash on corner cases.
+; RUN: opt < %s -S -loop-unroll -unroll-max-iteration-count-to-analyze=1000 -unroll-absolute-threshold=10  -unroll-threshold=10  -unroll-percent-of-optimized-for-complete-unroll=20 -o /dev/null
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+
+define void @foo1() {
+entry:
+  br label %for.body
+
+for.body:
+  %phi = phi i64 [ 0, %entry ], [ %inc, %for.body ]
+  %idx = zext i32 undef to i64
+  %add.ptr = getelementptr inbounds i64, i64* null, i64 %idx
+  %inc = add nuw nsw i64 %phi, 1
+  %cmp = icmp ult i64 %inc, 999
+  br i1 %cmp, label %for.body, label %for.exit
+
+for.exit:
+  ret void
+}
+
+define void @foo2() {
+entry:
+  br label %for.body
+
+for.body:
+  %phi = phi i64 [ 0, %entry ], [ %inc, %for.body ]
+  %x = getelementptr i32, <4 x i32*> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+  %inc = add nuw nsw i64 %phi, 1
+  %cmp = icmp ult i64 %inc, 999
+  br i1 %cmp, label %for.body, label %for.exit
+
+for.exit:
+  ret void
+}
diff --git a/test/Transforms/LoopUnroll/full-unroll-heuristics.ll b/test/Transforms/LoopUnroll/full-unroll-heuristics.ll
new file mode 100644
index 000000000000..2dab2fbf2e49
--- /dev/null
+++ b/test/Transforms/LoopUnroll/full-unroll-heuristics.ll
@@ -0,0 +1,62 @@
+; In this test we check how heuristics for complete unrolling work. We have
+; three knobs:
+;  1) -unroll-threshold
+;  2) -unroll-absolute-threshold and
+;  3) -unroll-percent-of-optimized-for-complete-unroll
+;
+; They control loop-unrolling according to the following rules:
+;  * If size of unrolled loop exceeds the absoulte threshold, we don't unroll
+;    this loop under any circumstances.
+;  * If size of unrolled loop is below the '-unroll-threshold', then we'll
+;    consider this loop as a very small one, and completely unroll it.
+;  * If a loop size is between these two tresholds, we only do complete unroll
+;    it if estimated number of potentially optimized instructions is high (we
+;    specify the minimal percent of such instructions).
+
+; In this particular test-case, complete unrolling will allow later
+; optimizations to remove ~55% of the instructions, the loop body size is 9,
+; and unrolled size is 65.
+
+; RUN: opt < %s -S -loop-unroll -unroll-max-iteration-count-to-analyze=1000 -unroll-absolute-threshold=10  -unroll-threshold=10  -unroll-percent-of-optimized-for-complete-unroll=20 | FileCheck %s -check-prefix=TEST1
+; RUN: opt < %s -S -loop-unroll -unroll-max-iteration-count-to-analyze=1000 -unroll-absolute-threshold=100 -unroll-threshold=10  -unroll-percent-of-optimized-for-complete-unroll=20 | FileCheck %s -check-prefix=TEST2
+; RUN: opt < %s -S -loop-unroll -unroll-max-iteration-count-to-analyze=1000 -unroll-absolute-threshold=100 -unroll-threshold=10  -unroll-percent-of-optimized-for-complete-unroll=80 | FileCheck %s -check-prefix=TEST3
+; RUN: opt < %s -S -loop-unroll -unroll-max-iteration-count-to-analyze=1000 -unroll-absolute-threshold=100 -unroll-threshold=100 -unroll-percent-of-optimized-for-complete-unroll=80 | FileCheck %s -check-prefix=TEST4
+
+; If the absolute threshold is too low, or if we can't optimize away requested
+; percent of instructions, we shouldn't unroll:
+; TEST1: %array_const_idx = getelementptr inbounds [9 x i32], [9 x i32]* @known_constant, i64 0, i64 %iv
+; TEST3: %array_const_idx = getelementptr inbounds [9 x i32], [9 x i32]* @known_constant, i64 0, i64 %iv
+
+; Otherwise, we should:
+; TEST2-NOT: %array_const_idx = getelementptr inbounds [9 x i32], [9 x i32]* @known_constant, i64 0, i64 %iv
+
+; Also, we should unroll if the 'unroll-threshold' is big enough:
+; TEST4-NOT: %array_const_idx = getelementptr inbounds [9 x i32], [9 x i32]* @known_constant, i64 0, i64 %iv
+
+; And check that we don't crash when we're not allowed to do any analysis.
+; RUN: opt < %s -loop-unroll -unroll-max-iteration-count-to-analyze=0 -disable-output
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+
+@known_constant = internal unnamed_addr constant [9 x i32] [i32 0, i32 -1, i32 0, i32 -1, i32 5, i32 -1, i32 0, i32 -1, i32 0], align 16
+
+define i32 @foo(i32* noalias nocapture readonly %src) {
+entry:
+  br label %loop
+
+loop:                                                ; preds = %loop, %entry
+  %iv = phi i64 [ 0, %entry ], [ %inc, %loop ]
+  %r  = phi i32 [ 0, %entry ], [ %add, %loop ]
+  %arrayidx = getelementptr inbounds i32, i32* %src, i64 %iv
+  %src_element = load i32, i32* %arrayidx, align 4
+  %array_const_idx = getelementptr inbounds [9 x i32], [9 x i32]* @known_constant, i64 0, i64 %iv
+  %const_array_element = load i32, i32* %array_const_idx, align 4
+  %mul = mul nsw i32 %src_element, %const_array_element
+  %add = add nsw i32 %mul, %r
+  %inc = add nuw nsw i64 %iv, 1
+  %exitcond86.i = icmp eq i64 %inc, 9
+  br i1 %exitcond86.i, label %loop.end, label %loop
+
+loop.end:                                            ; preds = %loop
+  %r.lcssa = phi i32 [ %r, %loop ]
+  ret i32 %r.lcssa
+}
diff --git a/test/Transforms/LoopUnroll/high-cost-trip-count-computation.ll b/test/Transforms/LoopUnroll/high-cost-trip-count-computation.ll
new file mode 100644
index 000000000000..6b1943f13bac
--- /dev/null
+++ b/test/Transforms/LoopUnroll/high-cost-trip-count-computation.ll
@@ -0,0 +1,27 @@
+; RUN: opt -S -unroll-runtime -loop-unroll < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+;; Check that we don't emit expensive instructions to compute trip
+;; counts when unrolling loops.
+
+define i32 @test(i64 %v12, i8* %array, i64* %loc) {
+; CHECK-LABEL: @test(
+; CHECK-NOT: udiv
+entry:
+  %step = load i64, i64* %loc, !range !0
+  br label %loop
+
+loop:                                           ; preds = %entry, %loop
+  %k.015 = phi i64 [ %v15, %loop ], [ %v12, %entry ]
+  %v14 = getelementptr inbounds i8, i8* %array, i64 %k.015
+  store i8 0, i8* %v14
+  %v15 = add nuw nsw i64 %k.015, %step
+  %v16 = icmp slt i64 %v15, 8193
+  br i1 %v16, label %loop, label %loopexit
+
+loopexit:                             ; preds = %loop
+  ret i32 0
+}
+
+!0 = !{i64 1, i64 100}
diff --git a/test/Transforms/LoopUnroll/ignore-annotation-intrinsic-cost.ll b/test/Transforms/LoopUnroll/ignore-annotation-intrinsic-cost.ll
index dcb5d1c28fb2..2101b63e026c 100644
--- a/test/Transforms/LoopUnroll/ignore-annotation-intrinsic-cost.ll
+++ b/test/Transforms/LoopUnroll/ignore-annotation-intrinsic-cost.ll
@@ -18,7 +18,7 @@ for.body:                                         ; preds = %entry, %for.body
   %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   ; The real loop.
   %mul = mul nsw i32 %B, %C
-  %arrayidx = getelementptr inbounds i32* %A, i32 %i.01
+  %arrayidx = getelementptr inbounds i32, i32* %A, i32 %i.01
   store i32 %mul, i32* %arrayidx, align 4
   %inc = add nsw i32 %i.01, 1
   %exitcond = icmp ne i32 %inc, 4
diff --git a/test/Transforms/LoopUnroll/runtime-loop.ll b/test/Transforms/LoopUnroll/runtime-loop.ll
index 80571ecbd882..fea15b65d5a5 100644
--- a/test/Transforms/LoopUnroll/runtime-loop.ll
+++ b/test/Transforms/LoopUnroll/runtime-loop.ll
@@ -1,5 +1,7 @@
 ; RUN: opt < %s -S -loop-unroll -unroll-runtime=true | FileCheck %s
 
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
 ; Tests for unrolling loops with run-time trip counts
 
 ; CHECK: %xtraiter = and i32 %n
@@ -20,8 +22,8 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %sum.02 = phi i32 [ %add, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %sum.02
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -47,8 +49,8 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %sum.01 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %sum.01
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -96,8 +98,8 @@ for.body:                                         ; preds = %for.body, %entry
   %p.addr.05 = phi i16* [ %incdec.ptr, %for.body ], [ %p, %entry ]
   %len.addr.04 = phi i32 [ %sub, %for.body ], [ %len, %entry ]
   %res.03 = phi i32 [ %add, %for.body ], [ 0, %entry ]
-  %incdec.ptr = getelementptr inbounds i16* %p.addr.05, i64 1
-  %0 = load i16* %p.addr.05, align 2
+  %incdec.ptr = getelementptr inbounds i16, i16* %p.addr.05, i64 1
+  %0 = load i16, i16* %p.addr.05, align 2
   %conv = zext i16 %0 to i32
   %add = add i32 %conv, %res.03
   %sub = add nsw i32 %len.addr.04, -2
@@ -113,6 +115,39 @@ for.end:                                          ; preds = %for.cond.for.end_cr
   ret i16 %res.0.lcssa
 }
 
+; Test run-time unrolling disable metadata.
+; CHECK: for.body:
+; CHECK-NOT: for.body.prol:
+
+define zeroext i16 @test2(i16* nocapture %p, i32 %len) nounwind uwtable readonly {
+entry:
+  %cmp2 = icmp eq i32 %len, 0
+  br i1 %cmp2, label %for.end, label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %p.addr.05 = phi i16* [ %incdec.ptr, %for.body ], [ %p, %entry ]
+  %len.addr.04 = phi i32 [ %sub, %for.body ], [ %len, %entry ]
+  %res.03 = phi i32 [ %add, %for.body ], [ 0, %entry ]
+  %incdec.ptr = getelementptr inbounds i16, i16* %p.addr.05, i64 1
+  %0 = load i16, i16* %p.addr.05, align 2
+  %conv = zext i16 %0 to i32
+  %add = add i32 %conv, %res.03
+  %sub = add nsw i32 %len.addr.04, -2
+  %cmp = icmp eq i32 %sub, 0
+  br i1 %cmp, label %for.cond.for.end_crit_edge, label %for.body, !llvm.loop !0
+
+for.cond.for.end_crit_edge:                       ; preds = %for.body
+  %phitmp = trunc i32 %add to i16
+  br label %for.end
+
+for.end:                                          ; preds = %for.cond.for.end_crit_edge, %entry
+  %res.0.lcssa = phi i16 [ %phitmp, %for.cond.for.end_crit_edge ], [ 0, %entry ]
+  ret i16 %res.0.lcssa
+}
+
+!0 = distinct !{!0, !1}
+!1 = !{!"llvm.loop.unroll.runtime.disable"}
+
 ; CHECK: !0 = distinct !{!0, !1}
 ; CHECK: !1 = !{!"llvm.loop.unroll.disable"}
 
diff --git a/test/Transforms/LoopUnroll/runtime-loop1.ll b/test/Transforms/LoopUnroll/runtime-loop1.ll
index 5ff75e33f7f8..7684e394290b 100644
--- a/test/Transforms/LoopUnroll/runtime-loop1.ll
+++ b/test/Transforms/LoopUnroll/runtime-loop1.ll
@@ -16,8 +16,8 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %sum.02 = phi i32 [ %add, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %sum.02
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopUnroll/runtime-loop2.ll b/test/Transforms/LoopUnroll/runtime-loop2.ll
index 176362a34456..7c6bb9690551 100644
--- a/test/Transforms/LoopUnroll/runtime-loop2.ll
+++ b/test/Transforms/LoopUnroll/runtime-loop2.ll
@@ -16,8 +16,8 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %sum.02 = phi i32 [ %add, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %sum.02
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopUnroll/runtime-loop3.ll b/test/Transforms/LoopUnroll/runtime-loop3.ll
index aa928ccc60c1..fd13ebfa0b84 100644
--- a/test/Transforms/LoopUnroll/runtime-loop3.ll
+++ b/test/Transforms/LoopUnroll/runtime-loop3.ll
@@ -23,8 +23,8 @@ for.body3:                                        ; preds = %for.cond1.preheader
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3 ], [ 0, %for.cond1.preheader ]
   %sum.19 = phi i32 [ %add4, %for.body3 ], [ %sum.012, %for.cond1.preheader ]
   %0 = add nsw i64 %indvars.iv, %indvars.iv16
-  %arrayidx = getelementptr inbounds i32* %a, i64 %0
-  %1 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %0
+  %1 = load i32, i32* %arrayidx, align 4
   %add4 = add nsw i32 %1, %sum.19
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopUnroll/runtime-loop4.ll b/test/Transforms/LoopUnroll/runtime-loop4.ll
new file mode 100644
index 000000000000..5014c739e4c9
--- /dev/null
+++ b/test/Transforms/LoopUnroll/runtime-loop4.ll
@@ -0,0 +1,44 @@
+; RUN: opt < %s -S -O2 -unroll-runtime=true | FileCheck %s
+
+; Check runtime unrolling prologue can be promoted by LICM pass.
+
+; CHECK: entry:
+; CHECK: %xtraiter
+; CHECK: %lcmp.mod
+; CHECK: loop1:
+; CHECK: br i1 %lcmp.mod
+; CHECK: loop2.prol:
+
+define void @unroll(i32 %iter, i32* %addr1, i32* %addr2) nounwind {
+entry:
+  br label %loop1
+
+loop1:
+  %iv1 = phi i32 [ 0, %entry ], [ %inc1, %loop1.latch ]
+  %offset1 = getelementptr i32, i32* %addr1, i32 %iv1
+  store i32 %iv1, i32* %offset1, align 4
+  br label %loop2.header
+
+loop2.header:
+  %e = icmp uge i32 %iter, 1
+  br i1 %e, label %loop2, label %exit2
+
+loop2:
+  %iv2 = phi i32 [ 0, %loop2.header ], [ %inc2, %loop2 ]
+  %offset2 = getelementptr i32, i32* %addr2, i32 %iv2
+  store i32 %iv2, i32* %offset2, align 4
+  %inc2 = add i32 %iv2, 1
+  %exitcnd2 = icmp uge i32 %inc2, %iter
+  br i1 %exitcnd2, label %exit2, label %loop2
+
+exit2:
+  br label %loop1.latch
+
+loop1.latch:
+  %inc1 = add i32 %iv1, 1
+  %exitcnd1 = icmp uge i32 %inc1, 1024
+  br i1 %exitcnd1, label %exit, label %loop1
+
+exit:
+  ret void
+}
diff --git a/test/Transforms/LoopUnroll/runtime-loop5.ll b/test/Transforms/LoopUnroll/runtime-loop5.ll
new file mode 100644
index 000000000000..e8d51775ce18
--- /dev/null
+++ b/test/Transforms/LoopUnroll/runtime-loop5.ll
@@ -0,0 +1,45 @@
+; RUN: opt < %s -S -loop-unroll -unroll-runtime=true -unroll-count=16 | FileCheck --check-prefix=UNROLL-16 %s
+; RUN: opt < %s -S -loop-unroll -unroll-runtime=true -unroll-count=4 | FileCheck --check-prefix=UNROLL-4 %s
+
+; Given that the trip-count of this loop is a 3-bit value, we cannot
+; safely unroll it with a count of anything more than 8.
+
+define i3 @test(i3* %a, i3 %n) {
+; UNROLL-16-LABEL: @test(
+; UNROLL-4-LABEL: @test(
+entry:
+  %cmp1 = icmp eq i3 %n, 0
+  br i1 %cmp1, label %for.end, label %for.body
+
+; UNROLL-16-NOT: for.body.prol:
+; UNROLL-4: for.body.prol:
+
+for.body:                                         ; preds = %for.body, %entry
+; UNROLL-16-LABEL: for.body:
+; UNROLL-4-LABEL: for.body:
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %sum.02 = phi i3 [ %add, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds i3, i3* %a, i64 %indvars.iv
+
+; UNROLL-16-LABEL: for.body
+; UNROLL-16-LABEL: getelementptr
+; UNROLL-16-LABEL-NOT: getelementptr
+
+; UNROLL-4-LABEL: getelementptr
+; UNROLL-4-LABEL: getelementptr
+; UNROLL-4-LABEL: getelementptr
+; UNROLL-4-LABEL: getelementptr
+
+  %0 = load i3, i3* %arrayidx
+  %add = add nsw i3 %0, %sum.02
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i3
+  %exitcond = icmp eq i3 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+; UNROLL-16-LABEL: for.end
+; UNROLL-4-LABEL: for.end
+for.end:                                          ; preds = %for.body, %entry
+  %sum.0.lcssa = phi i3 [ 0, %entry ], [ %add, %for.body ]
+  ret i3 %sum.0.lcssa
+}
diff --git a/test/Transforms/LoopUnroll/scevunroll.ll b/test/Transforms/LoopUnroll/scevunroll.ll
index 20161d798e9e..a5c9a6efacf3 100644
--- a/test/Transforms/LoopUnroll/scevunroll.ll
+++ b/test/Transforms/LoopUnroll/scevunroll.ll
@@ -19,8 +19,8 @@ while.body:
   %iv = phi i64 [ 10, %entry ], [ %iv.next, %while.body ]
   %sum = phi i32 [ 0, %entry ], [ %sum.next, %while.body ]
   %iv.next = add i64 %iv, -1
-  %adr = getelementptr inbounds i32* %base, i64 %iv.next
-  %tmp = load i32* %adr, align 8
+  %adr = getelementptr inbounds i32, i32* %base, i64 %iv.next
+  %tmp = load i32, i32* %adr, align 8
   %sum.next = add i32 %sum, %tmp
   %iv.narrow = trunc i64 %iv.next to i32
   %cmp.i65 = icmp sgt i32 %iv.narrow, 0
@@ -46,8 +46,8 @@ entry:
 loop:
   %iv = phi i64 [ 0, %entry ], [ %inc, %tail ]
   %s = phi i64 [ 0, %entry ], [ %s.next, %tail ]
-  %adr = getelementptr i64* %base, i64 %iv
-  %val = load i64* %adr
+  %adr = getelementptr i64, i64* %base, i64 %iv
+  %val = load i64, i64* %adr
   %s.next = add i64 %s, %val
   %inc = add i64 %iv, 1
   %cmp = icmp ne i64 %inc, 4
@@ -67,8 +67,8 @@ exit2:
 ; SCEV properly unrolls multi-exit loops.
 ;
 ; CHECK-LABEL: @multiExit(
-; CHECK: getelementptr i32* %base, i32 10
-; CHECK-NEXT: load i32*
+; CHECK: getelementptr i32, i32* %base, i32 10
+; CHECK-NEXT: load i32, i32*
 ; CHECK: br i1 false, label %l2.10, label %exit1
 ; CHECK: l2.10:
 ; CHECK-NOT: br
@@ -81,8 +81,8 @@ l1:
   %iv2 = phi i32 [ 0, %entry ], [ %inc2, %l2 ]
   %inc1 = add i32 %iv1, 1
   %inc2 = add i32 %iv2, 1
-  %adr = getelementptr i32* %base, i32 %iv1
-  %val = load i32* %adr
+  %adr = getelementptr i32, i32* %base, i32 %iv1
+  %val = load i32, i32* %adr
   %cmp1 = icmp slt i32 %iv1, 5
   br i1 %cmp1, label %l2, label %exit1
 l2:
@@ -112,8 +112,8 @@ l1:
   %iv2 = phi i32 [ 0, %entry ], [ %inc2, %l3 ]
   %inc1 = add i32 %iv1, 1
   %inc2 = add i32 %iv2, 1
-  %adr = getelementptr i32* %base, i32 %iv1
-  %val = load i32* %adr
+  %adr = getelementptr i32, i32* %base, i32 %iv1
+  %val = load i32, i32* %adr
   %cmp1 = icmp slt i32 %iv1, 5
   br i1 %cmp1, label %l2, label %exit1
 l2:
diff --git a/test/Transforms/LoopUnroll/shifted-tripcount.ll b/test/Transforms/LoopUnroll/shifted-tripcount.ll
index a118a463172e..4c216983af51 100644
--- a/test/Transforms/LoopUnroll/shifted-tripcount.ll
+++ b/test/Transforms/LoopUnroll/shifted-tripcount.ll
@@ -13,11 +13,11 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %i.013 = phi i64 [ %tmp16, %for.body ], [ 0, %entry ] ; <i64> [#uses=2]
-  %arrayidx7 = getelementptr double* %p, i64 %i.013 ; <double*> [#uses=2]
+  %arrayidx7 = getelementptr double, double* %p, i64 %i.013 ; <double*> [#uses=2]
   %tmp16 = add i64 %i.013, 1                      ; <i64> [#uses=3]
-  %arrayidx = getelementptr double* %p, i64 %tmp16 ; <double*> [#uses=1]
-  %tmp4 = load double* %arrayidx                  ; <double> [#uses=1]
-  %tmp8 = load double* %arrayidx7                 ; <double> [#uses=1]
+  %arrayidx = getelementptr double, double* %p, i64 %tmp16 ; <double*> [#uses=1]
+  %tmp4 = load double, double* %arrayidx                  ; <double> [#uses=1]
+  %tmp8 = load double, double* %arrayidx7                 ; <double> [#uses=1]
   %mul9 = fmul double %tmp8, %tmp4                ; <double> [#uses=1]
   store double %mul9, double* %arrayidx7
   %exitcond = icmp eq i64 %tmp16, %mul10          ; <i1> [#uses=1]
diff --git a/test/Transforms/LoopUnroll/unroll-cleanup.ll b/test/Transforms/LoopUnroll/unroll-cleanup.ll
new file mode 100644
index 000000000000..1e42203876ec
--- /dev/null
+++ b/test/Transforms/LoopUnroll/unroll-cleanup.ll
@@ -0,0 +1,85 @@
+; PR23524
+; The test is to check redundency produced by loop unroll pass
+; should be cleaned up by later pass.
+; RUN: opt < %s -O2 -S | FileCheck %s
+
+; After loop unroll:
+;       %dec18 = add nsw i32 %dec18.in, -1
+;       ...
+;       %dec18.1 = add nsw i32 %dec18, -1
+; should be merged to:
+;       %dec18.1 = add nsw i32 %dec18.in, -2
+;
+; CHECK-LABEL: @_Z3fn1v(
+; CHECK: %dec18.1 = add nsw i32 %dec18.in, -2
+
+; ModuleID = '<stdin>'
+target triple = "x86_64-unknown-linux-gnu"
+
+@b = global i32 0, align 4
+@c = global i32 0, align 4
+
+; Function Attrs: nounwind uwtable
+define void @_Z3fn1v() #0 {
+entry:
+  %tmp = load i32, i32* @b, align 4
+  %tobool20 = icmp eq i32 %tmp, 0
+  br i1 %tobool20, label %for.end6, label %for.body.lr.ph
+
+for.body.lr.ph:                                   ; preds = %entry
+  br label %for.body
+
+for.cond1.for.cond.loopexit_crit_edge:            ; preds = %for.inc
+  %add.ptr.lcssa = phi i16* [ %add.ptr, %for.inc ]
+  %incdec.ptr.lcssa = phi i8* [ %incdec.ptr, %for.inc ]
+  br label %for.cond.loopexit
+
+for.cond.loopexit:                                ; preds = %for.body, %for.cond1.for.cond.loopexit_crit_edge
+  %r.1.lcssa = phi i16* [ %add.ptr.lcssa, %for.cond1.for.cond.loopexit_crit_edge ], [ %r.022, %for.body ]
+  %a.1.lcssa = phi i8* [ %incdec.ptr.lcssa, %for.cond1.for.cond.loopexit_crit_edge ], [ %a.021, %for.body ]
+  %tmp1 = load i32, i32* @b, align 4
+  %tobool = icmp eq i32 %tmp1, 0
+  br i1 %tobool, label %for.cond.for.end6_crit_edge, label %for.body
+
+for.body:                                         ; preds = %for.cond.loopexit, %for.body.lr.ph
+  %r.022 = phi i16* [ undef, %for.body.lr.ph ], [ %r.1.lcssa, %for.cond.loopexit ]
+  %a.021 = phi i8* [ undef, %for.body.lr.ph ], [ %a.1.lcssa, %for.cond.loopexit ]
+  %tmp2 = load i32, i32* @c, align 4
+  %tobool215 = icmp eq i32 %tmp2, 0
+  br i1 %tobool215, label %for.cond.loopexit, label %for.body3.lr.ph
+
+for.body3.lr.ph:                                  ; preds = %for.body
+  br label %for.body3
+
+for.body3:                                        ; preds = %for.inc, %for.body3.lr.ph
+  %dec18.in = phi i32 [ %tmp2, %for.body3.lr.ph ], [ %dec18, %for.inc ]
+  %r.117 = phi i16* [ %r.022, %for.body3.lr.ph ], [ %add.ptr, %for.inc ]
+  %a.116 = phi i8* [ %a.021, %for.body3.lr.ph ], [ %incdec.ptr, %for.inc ]
+  %dec18 = add nsw i32 %dec18.in, -1
+  %tmp3 = load i8, i8* %a.116, align 1
+  %cmp = icmp eq i8 %tmp3, 0
+  br i1 %cmp, label %if.then, label %for.inc
+
+if.then:                                          ; preds = %for.body3
+  %arrayidx = getelementptr inbounds i16, i16* %r.117, i64 1
+  store i16 0, i16* %arrayidx, align 2
+  store i16 0, i16* %r.117, align 2
+  %arrayidx5 = getelementptr inbounds i16, i16* %r.117, i64 2
+  store i16 0, i16* %arrayidx5, align 2
+  br label %for.inc
+
+for.inc:                                          ; preds = %if.then, %for.body3
+  %incdec.ptr = getelementptr inbounds i8, i8* %a.116, i64 1
+  %add.ptr = getelementptr inbounds i16, i16* %r.117, i64 3
+  %tobool2 = icmp eq i32 %dec18, 0
+  br i1 %tobool2, label %for.cond1.for.cond.loopexit_crit_edge, label %for.body3, !llvm.loop !0
+
+for.cond.for.end6_crit_edge:                      ; preds = %for.cond.loopexit
+  br label %for.end6
+
+for.end6:                                         ; preds = %for.cond.for.end6_crit_edge, %entry
+  ret void
+}
+
+!0 = !{!0, !1}
+!1 = !{!"llvm.loop.unroll.count", i32 2}
diff --git a/test/Transforms/LoopUnroll/unroll-pragmas-disabled.ll b/test/Transforms/LoopUnroll/unroll-pragmas-disabled.ll
index 4f934a688be8..dc812fb4065f 100644
--- a/test/Transforms/LoopUnroll/unroll-pragmas-disabled.ll
+++ b/test/Transforms/LoopUnroll/unroll-pragmas-disabled.ll
@@ -19,8 +19,8 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
@@ -51,8 +51,8 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
@@ -78,8 +78,8 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
@@ -110,8 +110,8 @@ entry:
 
 for.body3:                                        ; preds = %for.body3, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body3 ]
-  %arrayidx = getelementptr inbounds i32* %List, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %List, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add4 = add nsw i32 %0, 10
   store i32 %add4, i32* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
@@ -124,8 +124,8 @@ for.body3.1.preheader:                            ; preds = %for.body3
 for.body3.1:                                      ; preds = %for.body3.1.preheader, %for.body3.1
   %indvars.iv.1 = phi i64 [ %1, %for.body3.1 ], [ 0, %for.body3.1.preheader ]
   %1 = add nsw i64 %indvars.iv.1, 1
-  %arrayidx.1 = getelementptr inbounds i32* %List, i64 %1
-  %2 = load i32* %arrayidx.1, align 4
+  %arrayidx.1 = getelementptr inbounds i32, i32* %List, i64 %1
+  %2 = load i32, i32* %arrayidx.1, align 4
   %add4.1 = add nsw i32 %2, 10
   store i32 %add4.1, i32* %arrayidx.1, align 4
   %exitcond.1 = icmp eq i64 %1, 4
diff --git a/test/Transforms/LoopUnroll/unroll-pragmas.ll b/test/Transforms/LoopUnroll/unroll-pragmas.ll
index d53fa49cc9f5..1354181becd0 100644
--- a/test/Transforms/LoopUnroll/unroll-pragmas.ll
+++ b/test/Transforms/LoopUnroll/unroll-pragmas.ll
@@ -1,5 +1,5 @@
-; RUN: opt < %s -loop-unroll -S | FileCheck %s
-; RUN: opt < %s -loop-unroll -loop-unroll -S | FileCheck %s
+; RUN: opt < %s -loop-unroll -pragma-unroll-threshold=1024 -S | FileCheck %s
+; RUN: opt < %s -loop-unroll -loop-unroll -pragma-unroll-threshold=1024 -S | FileCheck %s
 ;
 ; Run loop unrolling twice to verify that loop unrolling metadata is properly
 ; removed and further unrolling is disabled after the pass is run once.
@@ -19,8 +19,8 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
@@ -43,8 +43,8 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
@@ -71,8 +71,8 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
@@ -94,8 +94,8 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
@@ -124,8 +124,8 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
@@ -153,8 +153,8 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
@@ -190,8 +190,8 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
@@ -217,8 +217,8 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
@@ -245,8 +245,8 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopUnswitch/2007-07-12-ExitDomInfo.ll b/test/Transforms/LoopUnswitch/2007-07-12-ExitDomInfo.ll
index bf5a61b36300..9da8dc2f3e85 100644
--- a/test/Transforms/LoopUnswitch/2007-07-12-ExitDomInfo.ll
+++ b/test/Transforms/LoopUnswitch/2007-07-12-ExitDomInfo.ll
@@ -17,7 +17,7 @@ bb36.outer:		; preds = %bb41, %bb36.preheader
 bb.nph:		; preds = %bb36.outer
 	%ttmp8 = icmp eq i8* null, null		; <i1> [#uses=1]
 	%ttmp6 = icmp eq i8* null, null		; <i1> [#uses=1]
-	%tmp31 = call i32 @strcspn( i8* null, i8* getelementptr ([3 x i8]* @str3, i64 0, i64 0) )		; <i32> [#uses=1]
+	%tmp31 = call i32 @strcspn( i8* null, i8* getelementptr ([3 x i8], [3 x i8]* @str3, i64 0, i64 0) )		; <i32> [#uses=1]
 	br i1 %ttmp8, label %cond_next, label %cond_true
 
 cond_true:		; preds = %bb.nph
diff --git a/test/Transforms/LoopUnswitch/2007-07-18-DomInfo.ll b/test/Transforms/LoopUnswitch/2007-07-18-DomInfo.ll
index dfca15403bfa..c01bed142fc7 100644
--- a/test/Transforms/LoopUnswitch/2007-07-18-DomInfo.ll
+++ b/test/Transforms/LoopUnswitch/2007-07-18-DomInfo.ll
@@ -52,7 +52,7 @@ cond_next1929:          ; preds = %cond_next1915
         br i1 false, label %cond_next1961, label %cond_next2009
 
 cond_next1961:          ; preds = %cond_next1929
-        %tmp1992 = getelementptr i8* %b.10.ph, i32 0            ; <i8*> [#uses=0]
+        %tmp1992 = getelementptr i8, i8* %b.10.ph, i32 0            ; <i8*> [#uses=0]
         br label %cond_next1915
 
 cond_next2009:          ; preds = %cond_next1929
diff --git a/test/Transforms/LoopUnswitch/2007-08-01-LCSSA.ll b/test/Transforms/LoopUnswitch/2007-08-01-LCSSA.ll
index f83acaa6b0b5..49b30bda50fa 100644
--- a/test/Transforms/LoopUnswitch/2007-08-01-LCSSA.ll
+++ b/test/Transforms/LoopUnswitch/2007-08-01-LCSSA.ll
@@ -19,7 +19,7 @@ declare i32 @strcmp(i8*, i8*)
 
 define i32 @_ZN9Generator6strregEPKc(%struct.Generator* %this, i8* %s) {
 entry:
-	%s_addr.0 = select i1 false, i8* getelementptr ([1 x i8]* @.str9, i32 0, i32 0), i8* %s		; <i8*> [#uses=2]
+	%s_addr.0 = select i1 false, i8* getelementptr ([1 x i8], [1 x i8]* @.str9, i32 0, i32 0), i8* %s		; <i8*> [#uses=2]
 	%tmp122 = icmp eq i8* %s_addr.0, null		; <i1> [#uses=1]
 	br label %bb184
 
diff --git a/test/Transforms/LoopUnswitch/2008-06-02-DomInfo.ll b/test/Transforms/LoopUnswitch/2008-06-02-DomInfo.ll
index 906c2c581e1f..8ea4ed33fc5c 100644
--- a/test/Transforms/LoopUnswitch/2008-06-02-DomInfo.ll
+++ b/test/Transforms/LoopUnswitch/2008-06-02-DomInfo.ll
@@ -19,7 +19,7 @@ bb54:		; preds = %bb31, %bb5, %bb
 	br i1 false, label %bb64, label %bb
 bb64:		; preds = %bb54
 	%tmp6566 = sext i16 %p_6 to i32		; <i32> [#uses=1]
-	%tmp68 = tail call i32 (...)* @func_18( i32 1, i32 %tmp6566, i32 1 ) nounwind 		; <i32> [#uses=0]
+	%tmp68 = tail call i32 (...) @func_18( i32 1, i32 %tmp6566, i32 1 ) nounwind 		; <i32> [#uses=0]
 	ret i32 undef
 }
 
diff --git a/test/Transforms/LoopUnswitch/2008-06-17-DomFrontier.ll b/test/Transforms/LoopUnswitch/2008-06-17-DomFrontier.ll
index f74054a0589c..d606ea9c6d20 100644
--- a/test/Transforms/LoopUnswitch/2008-06-17-DomFrontier.ll
+++ b/test/Transforms/LoopUnswitch/2008-06-17-DomFrontier.ll
@@ -17,6 +17,6 @@ bb36:		; preds = %bb19
 	store i16 0, i16* @g_56, align 2
 	br i1 false, label %bb44, label %bb3
 bb44:		; preds = %bb44, %bb36
-	%tmp46 = load i16* @g_56, align 2		; <i16> [#uses=0]
+	%tmp46 = load i16, i16* @g_56, align 2		; <i16> [#uses=0]
 	br i1 false, label %bb, label %bb44
 }
diff --git a/test/Transforms/LoopUnswitch/2008-11-03-Invariant.ll b/test/Transforms/LoopUnswitch/2008-11-03-Invariant.ll
index 31dba79be1f8..90c0944e38d8 100644
--- a/test/Transforms/LoopUnswitch/2008-11-03-Invariant.ll
+++ b/test/Transforms/LoopUnswitch/2008-11-03-Invariant.ll
@@ -15,7 +15,7 @@ bb:		; preds = %bb.nph, %bb3
 	br i1 %1, label %bb2, label %bb1
 
 bb1:		; preds = %bb
-	%2 = tail call i32 (...)* @b() nounwind		; <i32> [#uses=0]
+	%2 = tail call i32 (...) @b() nounwind		; <i32> [#uses=0]
 	br label %bb2
 
 bb2:		; preds = %bb, %bb1
diff --git a/test/Transforms/LoopUnswitch/2010-11-18-LCSSA.ll b/test/Transforms/LoopUnswitch/2010-11-18-LCSSA.ll
index a976d18d4445..3b89fa915833 100644
--- a/test/Transforms/LoopUnswitch/2010-11-18-LCSSA.ll
+++ b/test/Transforms/LoopUnswitch/2010-11-18-LCSSA.ll
@@ -7,7 +7,7 @@ entry:
   br i1 true, label %for.end12, label %bb.nph
 
 bb.nph:                                           ; preds = %entry
-  %g_38.promoted = load i32* @g_38
+  %g_38.promoted = load i32, i32* @g_38
   br label %for.body
 
 for.body:                                         ; preds = %for.cond, %bb.nph
diff --git a/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll b/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll
index e8feef383b05..0b7f91fee150 100644
--- a/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll
+++ b/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll
@@ -22,9 +22,9 @@ for.body:                                         ; preds = %for.cond
 
 if.then:                                          ; preds = %for.body
   %idxprom = sext i32 %inc1 to i64
-  %array_ = getelementptr inbounds %class.MyContainer.1.3.19.29* %this, i32 0, i32 0
-  %arrayidx = getelementptr inbounds [6 x %class.MyMemVarClass.0.2.18.28*]* %array_, i32 0, i64 %idxprom
-  %tmp4 = load %class.MyMemVarClass.0.2.18.28** %arrayidx, align 8
+  %array_ = getelementptr inbounds %class.MyContainer.1.3.19.29, %class.MyContainer.1.3.19.29* %this, i32 0, i32 0
+  %arrayidx = getelementptr inbounds [6 x %class.MyMemVarClass.0.2.18.28*], [6 x %class.MyMemVarClass.0.2.18.28*]* %array_, i32 0, i64 %idxprom
+  %tmp4 = load %class.MyMemVarClass.0.2.18.28*, %class.MyMemVarClass.0.2.18.28** %arrayidx, align 8
   %isnull = icmp eq %class.MyMemVarClass.0.2.18.28* %tmp4, null
   br i1 %isnull, label %for.inc, label %delete.notnull
 
diff --git a/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll b/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll
index a8608b877205..abeea209f639 100644
--- a/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll
+++ b/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll
@@ -15,7 +15,7 @@
 ; CHECK-NEXT:   br label %loop_begin.us
 
 ; CHECK:      loop_begin.us:                                    ; preds = %loop_begin.backedge.us, %.split.us
-; CHECK-NEXT:   %var_val.us = load i32* %var
+; CHECK-NEXT:   %var_val.us = load i32, i32* %var
 ; CHECK-NEXT:   switch i32 1, label %default.us-lcssa.us [
 ; CHECK-NEXT:     i32 1, label %inc.us
 
@@ -34,7 +34,7 @@
 ; CHECK-NEXT:   br label %loop_begin.us1
 
 ; CHECK:      loop_begin.us1:                                   ; preds = %loop_begin.backedge.us5, %.split.split.us
-; CHECK-NEXT:   %var_val.us2 = load i32* %var
+; CHECK-NEXT:   %var_val.us.2 = load i32, i32* %var
 ; CHECK-NEXT:   switch i32 2, label %default.us-lcssa.us-lcssa.us [
 ; CHECK-NEXT:     i32 1, label %inc.us4
 ; CHECK-NEXT:     i32 2, label %dec.us3
@@ -48,7 +48,7 @@
 ; CHECK-NEXT:   br label %loop_begin
 
 ; CHECK:      loop_begin:                                       ; preds = %loop_begin.backedge, %.split.split
-; CHECK-NEXT:   %var_val = load i32* %var
+; CHECK-NEXT:   %var_val = load i32, i32* %var
 ; CHECK-NEXT:   switch i32 %c, label %default.us-lcssa.us-lcssa [
 ; CHECK-NEXT:     i32 1, label %inc
 ; CHECK-NEXT:     i32 2, label %dec
@@ -63,13 +63,13 @@
 define i32 @test(i32* %var) {
   %mem = alloca i32
   store i32 2, i32* %mem
-  %c = load i32* %mem
+  %c = load i32, i32* %mem
 
   br label %loop_begin
 
 loop_begin:
 
-  %var_val = load i32* %var
+  %var_val = load i32, i32* %var
 
   switch i32 %c, label %default [
       i32 1, label %inc
diff --git a/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll b/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll
index 686cedbbc51a..393dd5c313a4 100644
--- a/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll
+++ b/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll
@@ -52,14 +52,14 @@
 define i32 @test(i32* %var) {
   %mem = alloca i32
   store i32 2, i32* %mem
-  %c = load i32* %mem
-  %d = load i32* %mem
+  %c = load i32, i32* %mem
+  %d = load i32, i32* %mem
 
   br label %loop_begin
 
 loop_begin:
 
-  %var_val = load i32* %var
+  %var_val = load i32, i32* %var
 
   switch i32 %c, label %second_switch [
       i32 1, label %inc
diff --git a/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll b/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll
index 3ba9fc2f5cf1..02552ea5cc40 100644
--- a/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll
+++ b/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll
@@ -22,7 +22,7 @@
 ; CHECK-NEXT:   br label %loop_begin.us.us
 
 ; CHECK:      loop_begin.us.us:                                 ; preds = %loop_begin.backedge.us.us, %.split.us.split.us
-; CHECK-NEXT:   %var_val.us.us = load i32* %var
+; CHECK-NEXT:   %var_val.us.us = load i32, i32* %var
 ; CHECK-NEXT:   switch i32 1, label %second_switch.us.us [
 ; CHECK-NEXT:     i32 1, label %inc.us.us
 
@@ -38,7 +38,7 @@
 ; CHECK-NEXT:   br label %loop_begin.us
 
 ; CHECK:      loop_begin.us:                                    ; preds = %loop_begin.backedge.us, %.split.us.split
-; CHECK-NEXT:   %var_val.us = load i32* %var
+; CHECK-NEXT:   %var_val.us = load i32, i32* %var
 ; CHECK-NEXT:   switch i32 1, label %second_switch.us [
 ; CHECK-NEXT:     i32 1, label %inc.us
 
@@ -65,7 +65,7 @@
 ; CHECK-NEXT:   br label %loop_begin.us1
 
 ; CHECK:      loop_begin.us1:                                   ; preds = %loop_begin.backedge.us6, %.split.split.us
-; CHECK-NEXT:   %var_val.us2 = load i32* %var
+; CHECK-NEXT:   %var_val.us.2 = load i32, i32* %var
 ; CHECK-NEXT:   switch i32 %c, label %second_switch.us3 [
 ; CHECK-NEXT:     i32 1, label %loop_begin.inc_crit_edge.us
 ; CHECK-NEXT:   ]
@@ -86,7 +86,7 @@
 ; CHECK-NEXT:   br label %loop_begin
 
 ; CHECK:      loop_begin:                                       ; preds = %loop_begin.backedge, %.split.split
-; CHECK-NEXT:   %var_val = load i32* %var
+; CHECK-NEXT:   %var_val = load i32, i32* %var
 ; CHECK-NEXT:   switch i32 %c, label %second_switch [
 ; CHECK-NEXT:     i32 1, label %loop_begin.inc_crit_edge
 ; CHECK-NEXT:   ]
@@ -106,14 +106,14 @@
 define i32 @test(i32* %var) {
   %mem = alloca i32
   store i32 2, i32* %mem
-  %c = load i32* %mem
-  %d = load i32* %mem
+  %c = load i32, i32* %mem
+  %d = load i32, i32* %mem
 
   br label %loop_begin
 
 loop_begin:
 
-  %var_val = load i32* %var
+  %var_val = load i32, i32* %var
 
   switch i32 %c, label %second_switch [
       i32 1, label %inc
diff --git a/test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll b/test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll
index a6c0d83484b3..223fbf18bf53 100644
--- a/test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll
+++ b/test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll
@@ -46,9 +46,9 @@ define void @_ZN1DptEv(%class.D.22.42.66.102.138.158.178.198.238.242.246.250.262
 entry:
   %this.addr = alloca %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379*, align 8
   store %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %this, %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379** %this.addr, align 8
-  %this1 = load %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379** %this.addr
-  %px = getelementptr inbounds %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %this1, i32 0, i32 0
-  %0 = load %class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376** %px, align 8
+  %this1 = load %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379*, %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379** %this.addr
+  %px = getelementptr inbounds %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379, %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %this1, i32 0, i32 0
+  %0 = load %class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376*, %class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376** %px, align 8
   %tobool = icmp ne %class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376* %0, null
   br i1 %tobool, label %cond.end, label %cond.false
 
diff --git a/test/Transforms/LoopUnswitch/2012-05-20-Phi.ll b/test/Transforms/LoopUnswitch/2012-05-20-Phi.ll
index 4c63a56bfdc5..96bc28c9a358 100644
--- a/test/Transforms/LoopUnswitch/2012-05-20-Phi.ll
+++ b/test/Transforms/LoopUnswitch/2012-05-20-Phi.ll
@@ -9,9 +9,9 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define void @func() noreturn nounwind uwtable {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %tobool = icmp eq i32 %0, 0
-  %1 = load i32* @b, align 4
+  %1 = load i32, i32* @b, align 4
   br label %while.body
 
 while.body:                                       ; preds = %while.body, %entry
diff --git a/test/Transforms/LoopUnswitch/basictest.ll b/test/Transforms/LoopUnswitch/basictest.ll
index 85e44eca9b63..e990144d5ccc 100644
--- a/test/Transforms/LoopUnswitch/basictest.ll
+++ b/test/Transforms/LoopUnswitch/basictest.ll
@@ -6,13 +6,13 @@ entry:
 no_exit:		; preds = %no_exit.backedge, %entry
 	%i.0.0 = phi i32 [ 0, %entry ], [ %i.0.0.be, %no_exit.backedge ]		; <i32> [#uses=3]
 	%gep.upgrd.1 = zext i32 %i.0.0 to i64		; <i64> [#uses=1]
-	%tmp.7 = getelementptr i32* %A, i64 %gep.upgrd.1		; <i32*> [#uses=4]
-	%tmp.13 = load i32* %tmp.7		; <i32> [#uses=2]
+	%tmp.7 = getelementptr i32, i32* %A, i64 %gep.upgrd.1		; <i32*> [#uses=4]
+	%tmp.13 = load i32, i32* %tmp.7		; <i32> [#uses=2]
 	%tmp.14 = add i32 %tmp.13, 1		; <i32> [#uses=1]
 	store i32 %tmp.14, i32* %tmp.7
 	br i1 %C, label %then, label %endif
 then:		; preds = %no_exit
-	%tmp.29 = load i32* %tmp.7		; <i32> [#uses=1]
+	%tmp.29 = load i32, i32* %tmp.7		; <i32> [#uses=1]
 	%tmp.30 = add i32 %tmp.29, 2		; <i32> [#uses=1]
 	store i32 %tmp.30, i32* %tmp.7
 	%inc9 = add i32 %i.0.0, 1		; <i32> [#uses=2]
@@ -36,13 +36,13 @@ return:		; preds = %endif, %then
 define i32 @test2(i32* %var) {
   %mem = alloca i32
   store i32 2, i32* %mem
-  %c = load i32* %mem
+  %c = load i32, i32* %mem
 
   br label %loop_begin
 
 loop_begin:
 
-  %var_val = load i32* %var
+  %var_val = load i32, i32* %var
 
   switch i32 %c, label %default [
       i32 1, label %inc
diff --git a/test/Transforms/LoopUnswitch/preserve-analyses.ll b/test/Transforms/LoopUnswitch/preserve-analyses.ll
index f79612bef51e..e3774a1e907a 100644
--- a/test/Transforms/LoopUnswitch/preserve-analyses.ll
+++ b/test/Transforms/LoopUnswitch/preserve-analyses.ll
@@ -11,8 +11,8 @@ target triple = "armv6-apple-darwin9"
 
 define i32 @ineqn(i8* %s, i8* %p) nounwind readonly {
 entry:
-  %0 = load i32* @delim1, align 4                 ; <i32> [#uses=1]
-  %1 = load i32* @delim2, align 4                 ; <i32> [#uses=1]
+  %0 = load i32, i32* @delim1, align 4                 ; <i32> [#uses=1]
+  %1 = load i32, i32* @delim2, align 4                 ; <i32> [#uses=1]
   br label %bb8.outer
 
 bb:                                               ; preds = %bb8
@@ -20,7 +20,7 @@ bb:                                               ; preds = %bb8
   br i1 %2, label %bb10, label %bb2
 
 bb2:                                              ; preds = %bb
-  %3 = getelementptr inbounds i8* %p_addr.0, i32 1 ; <i8*> [#uses=3]
+  %3 = getelementptr inbounds i8, i8* %p_addr.0, i32 1 ; <i8*> [#uses=3]
   switch i32 %ineq.0.ph, label %bb8.backedge [
     i32 0, label %bb3
     i32 1, label %bb6
@@ -61,7 +61,7 @@ bb8.outer:                                        ; preds = %bb8.outer.backedge,
 
 bb8:                                              ; preds = %bb8.outer, %bb8.backedge
   %p_addr.0 = phi i8* [ %p_addr.0.ph, %bb8.outer ], [ %3, %bb8.backedge ] ; <i8*> [#uses=3]
-  %7 = load i8* %p_addr.0, align 1                ; <i8> [#uses=2]
+  %7 = load i8, i8* %p_addr.0, align 1                ; <i8> [#uses=2]
   %8 = sext i8 %7 to i32                          ; <i32> [#uses=2]
   %9 = icmp eq i8 %7, 0                           ; <i1> [#uses=1]
   br i1 %9, label %bb10, label %bb
diff --git a/test/Transforms/LoopVectorize/12-12-11-if-conv.ll b/test/Transforms/LoopVectorize/12-12-11-if-conv.ll
index a292afbd5882..d5e020c36e98 100644
--- a/test/Transforms/LoopVectorize/12-12-11-if-conv.ll
+++ b/test/Transforms/LoopVectorize/12-12-11-if-conv.ll
@@ -14,8 +14,8 @@ entry:
 
 for.body:                                         ; preds = %entry, %if.end
   %indvars.iv = phi i64 [ %indvars.iv.next, %if.end ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %if.end, label %if.then
 
diff --git a/test/Transforms/LoopVectorize/2012-10-22-isconsec.ll b/test/Transforms/LoopVectorize/2012-10-22-isconsec.ll
index 16d64eab25c3..9d848bdede2c 100644
--- a/test/Transforms/LoopVectorize/2012-10-22-isconsec.ll
+++ b/test/Transforms/LoopVectorize/2012-10-22-isconsec.ll
@@ -22,7 +22,7 @@ entry:
 "3":                                              ; preds = %"3.lr.ph", %"3"
   %indvars.iv = phi i64 [ 0, %"3.lr.ph" ], [ %indvars.iv.next, %"3" ]
   %3 = shl nsw i64 %indvars.iv, 2
-  %4 = getelementptr inbounds i8* %1, i64 %3
+  %4 = getelementptr inbounds i8, i8* %1, i64 %3
   %5 = bitcast i8* %4 to float*
   store float %value, float* %5, align 4
   %indvars.iv.next = add i64 %indvars.iv, %2
@@ -41,7 +41,7 @@ entry:
 "3":                                              ; preds = %"3", %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %"3" ]
   %0 = shl nsw i64 %indvars.iv, 2
-  %1 = getelementptr inbounds i8* bitcast (float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 16000) to i8*), i64 %0
+  %1 = getelementptr inbounds i8, i8* bitcast (float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 16000) to i8*), i64 %0
   %2 = bitcast i8* %1 to float*
   store float -1.000000e+00, float* %2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/AArch64/aarch64-unroll.ll b/test/Transforms/LoopVectorize/AArch64/aarch64-unroll.ll
index 9962c3d76a66..a689f44e912c 100644
--- a/test/Transforms/LoopVectorize/AArch64/aarch64-unroll.ll
+++ b/test/Transforms/LoopVectorize/AArch64/aarch64-unroll.ll
@@ -22,12 +22,12 @@ for.body.preheader:                               ; preds = %entry
 
 for.body:                                         ; preds = %for.body.preheader, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %1 = load i32* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx2, align 4
   %add = add nsw i32 %1, %0
-  %arrayidx4 = getelementptr inbounds i32* %c, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds i32, i32* %c, i64 %indvars.iv
   store i32 %add, i32* %arrayidx4, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/AArch64/arbitrary-induction-step.ll b/test/Transforms/LoopVectorize/AArch64/arbitrary-induction-step.ll
new file mode 100644
index 000000000000..4cd703f64582
--- /dev/null
+++ b/test/Transforms/LoopVectorize/AArch64/arbitrary-induction-step.ll
@@ -0,0 +1,150 @@
+; RUN: opt -S < %s -loop-vectorize 2>&1 | FileCheck %s
+; RUN: opt -S < %s -loop-vectorize -force-vector-interleave=1 -force-vector-width=2 | FileCheck %s --check-prefix=FORCE-VEC
+
+target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-gnueabi"
+
+; Test integer induction variable of step 2:
+;   for (int i = 0; i < 1024; i+=2) {
+;     int tmp = *A++;
+;     sum += i * tmp;
+;   }
+
+; CHECK-LABEL: @ind_plus2(
+; CHECK: load <4 x i32>, <4 x i32>*
+; CHECK: load <4 x i32>, <4 x i32>*
+; CHECK: mul nsw <4 x i32>
+; CHECK: mul nsw <4 x i32>
+; CHECK: add nsw <4 x i32>
+; CHECK: add nsw <4 x i32>
+; CHECK: %index.next = add i64 %index, 8
+; CHECK: icmp eq i64 %index.next, 512
+
+; FORCE-VEC-LABEL: @ind_plus2(
+; FORCE-VEC: %wide.load = load <2 x i32>, <2 x i32>*
+; FORCE-VEC: mul nsw <2 x i32>
+; FORCE-VEC: add nsw <2 x i32>
+; FORCE-VEC: %index.next = add i64 %index, 2
+; FORCE-VEC: icmp eq i64 %index.next, 512
+define i32 @ind_plus2(i32* %A) {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %A.addr = phi i32* [ %A, %entry ], [ %inc.ptr, %for.body ]
+  %i = phi i32 [ 0, %entry ], [ %add1, %for.body ]
+  %sum = phi i32 [ 0, %entry ], [ %add, %for.body ]
+  %inc.ptr = getelementptr inbounds i32, i32* %A.addr, i64 1
+  %0 = load i32, i32* %A.addr, align 4
+  %mul = mul nsw i32 %0, %i
+  %add = add nsw i32 %mul, %sum
+  %add1 = add nsw i32 %i, 2
+  %cmp = icmp slt i32 %add1, 1024
+  br i1 %cmp, label %for.body, label %for.end
+
+for.end:                                          ; preds = %for.body
+  %add.lcssa = phi i32 [ %add, %for.body ]
+  ret i32 %add.lcssa
+}
+
+
+; Test integer induction variable of step -2:
+;   for (int i = 1024; i > 0; i-=2) {
+;     int tmp = *A++;
+;     sum += i * tmp;
+;   }
+
+; CHECK-LABEL: @ind_minus2(
+; CHECK: load <4 x i32>, <4 x i32>*
+; CHECK: load <4 x i32>, <4 x i32>*
+; CHECK: mul nsw <4 x i32>
+; CHECK: mul nsw <4 x i32>
+; CHECK: add nsw <4 x i32>
+; CHECK: add nsw <4 x i32>
+; CHECK: %index.next = add i64 %index, 8
+; CHECK: icmp eq i64 %index.next, 512
+
+; FORCE-VEC-LABEL: @ind_minus2(
+; FORCE-VEC: %wide.load = load <2 x i32>, <2 x i32>*
+; FORCE-VEC: mul nsw <2 x i32>
+; FORCE-VEC: add nsw <2 x i32>
+; FORCE-VEC: %index.next = add i64 %index, 2
+; FORCE-VEC: icmp eq i64 %index.next, 512
+define i32 @ind_minus2(i32* %A) {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %A.addr = phi i32* [ %A, %entry ], [ %inc.ptr, %for.body ]
+  %i = phi i32 [ 1024, %entry ], [ %sub, %for.body ]
+  %sum = phi i32 [ 0, %entry ], [ %add, %for.body ]
+  %inc.ptr = getelementptr inbounds i32, i32* %A.addr, i64 1
+  %0 = load i32, i32* %A.addr, align 4
+  %mul = mul nsw i32 %0, %i
+  %add = add nsw i32 %mul, %sum
+  %sub = add nsw i32 %i, -2
+  %cmp = icmp sgt i32 %i, 2
+  br i1 %cmp, label %for.body, label %for.end
+
+for.end:                                          ; preds = %for.body
+  %add.lcssa = phi i32 [ %add, %for.body ]
+  ret i32 %add.lcssa
+}
+
+
+; Test pointer induction variable of step 2. As currently we don't support
+; masked load/store, vectorization is possible but not beneficial. If loop
+; vectorization is not enforced, LV will only do interleave.
+;   for (int i = 0; i < 1024; i++) {
+;     int tmp0 = *A++;
+;     int tmp1 = *A++;
+;     sum += tmp0 * tmp1;
+;   }
+
+; CHECK-LABEL: @ptr_ind_plus2(
+; CHECK: load i32, i32*
+; CHECK: load i32, i32*
+; CHECK: load i32, i32*
+; CHECK: load i32, i32*
+; CHECK: mul nsw i32
+; CHECK: mul nsw i32
+; CHECK: add nsw i32
+; CHECK: add nsw i32
+; CHECK: %index.next = add i64 %index, 2
+; CHECK: %21 = icmp eq i64 %index.next, 1024
+
+; FORCE-VEC-LABEL: @ptr_ind_plus2(
+; FORCE-VEC: load i32, i32*
+; FORCE-VEC: insertelement <2 x i32>
+; FORCE-VEC: load i32, i32*
+; FORCE-VEC: insertelement <2 x i32>
+; FORCE-VEC: load i32, i32*
+; FORCE-VEC: insertelement <2 x i32>
+; FORCE-VEC: load i32, i32*
+; FORCE-VEC: insertelement <2 x i32>
+; FORCE-VEC: mul nsw <2 x i32>
+; FORCE-VEC: add nsw <2 x i32>
+; FORCE-VEC: %index.next = add i64 %index, 2
+; FORCE-VEC: icmp eq i64 %index.next, 1024
+define i32 @ptr_ind_plus2(i32* %A) {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %A.addr = phi i32* [ %A, %entry ], [ %inc.ptr1, %for.body ]
+  %sum = phi i32 [ 0, %entry ], [ %add, %for.body ]
+  %i = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %inc.ptr = getelementptr inbounds i32, i32* %A.addr, i64 1
+  %0 = load i32, i32* %A.addr, align 4
+  %inc.ptr1 = getelementptr inbounds i32, i32* %A.addr, i64 2
+  %1 = load i32, i32* %inc.ptr, align 4
+  %mul = mul nsw i32 %1, %0
+  %add = add nsw i32 %mul, %sum
+  %inc = add nsw i32 %i, 1
+  %exitcond = icmp eq i32 %inc, 1024
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  %add.lcssa = phi i32 [ %add, %for.body ]
+  ret i32 %add.lcssa
+}
diff --git a/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll b/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll
index f8eb3ed1f35f..395b468c509c 100644
--- a/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll
+++ b/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll
@@ -22,12 +22,12 @@ for.body.preheader:                               ; preds = %entry
 
 for.body:                                         ; preds = %for.body.preheader, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %1 = load i32* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx2, align 4
   %add = add nsw i32 %1, %0
-  %arrayidx4 = getelementptr inbounds i32* %c, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds i32, i32* %c, i64 %indvars.iv
   store i32 %add, i32* %arrayidx4, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/AArch64/gather-cost.ll b/test/Transforms/LoopVectorize/AArch64/gather-cost.ll
index bb285382e53c..46b8ef1a09bf 100644
--- a/test/Transforms/LoopVectorize/AArch64/gather-cost.ll
+++ b/test/Transforms/LoopVectorize/AArch64/gather-cost.ll
@@ -30,32 +30,32 @@ for.body:
   %b.054 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add30, %for.body ]
   %add = add i64 %v.055, %offset
   %mul = mul i64 %add, 3
-  %arrayidx = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %mul
-  %0 = load float* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds [512 x float]* @kernel, i64 0, i64 %v.055
-  %1 = load float* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds [1536 x float], [1536 x float]* @src_data, i64 0, i64 %mul
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds [512 x float], [512 x float]* @kernel, i64 0, i64 %v.055
+  %1 = load float, float* %arrayidx2, align 4
   %mul3 = fmul fast float %0, %1
-  %arrayidx4 = getelementptr inbounds [512 x float]* @kernel2, i64 0, i64 %v.055
-  %2 = load float* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds [512 x float], [512 x float]* @kernel2, i64 0, i64 %v.055
+  %2 = load float, float* %arrayidx4, align 4
   %mul5 = fmul fast float %mul3, %2
-  %arrayidx6 = getelementptr inbounds [512 x float]* @kernel3, i64 0, i64 %v.055
-  %3 = load float* %arrayidx6, align 4
+  %arrayidx6 = getelementptr inbounds [512 x float], [512 x float]* @kernel3, i64 0, i64 %v.055
+  %3 = load float, float* %arrayidx6, align 4
   %mul7 = fmul fast float %mul5, %3
-  %arrayidx8 = getelementptr inbounds [512 x float]* @kernel4, i64 0, i64 %v.055
-  %4 = load float* %arrayidx8, align 4
+  %arrayidx8 = getelementptr inbounds [512 x float], [512 x float]* @kernel4, i64 0, i64 %v.055
+  %4 = load float, float* %arrayidx8, align 4
   %mul9 = fmul fast float %mul7, %4
   %add10 = fadd fast float %r.057, %mul9
   %arrayidx.sum = add i64 %mul, 1
-  %arrayidx11 = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum
-  %5 = load float* %arrayidx11, align 4
+  %arrayidx11 = getelementptr inbounds [1536 x float], [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum
+  %5 = load float, float* %arrayidx11, align 4
   %mul13 = fmul fast float %1, %5
   %mul15 = fmul fast float %2, %mul13
   %mul17 = fmul fast float %3, %mul15
   %mul19 = fmul fast float %4, %mul17
   %add20 = fadd fast float %g.056, %mul19
   %arrayidx.sum52 = add i64 %mul, 2
-  %arrayidx21 = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum52
-  %6 = load float* %arrayidx21, align 4
+  %arrayidx21 = getelementptr inbounds [1536 x float], [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum52
+  %6 = load float, float* %arrayidx21, align 4
   %mul23 = fmul fast float %1, %6
   %mul25 = fmul fast float %2, %mul23
   %mul27 = fmul fast float %3, %mul25
diff --git a/test/Transforms/LoopVectorize/AArch64/sdiv-pow2.ll b/test/Transforms/LoopVectorize/AArch64/sdiv-pow2.ll
index a01d54312a60..f3c6548c68ed 100644
--- a/test/Transforms/LoopVectorize/AArch64/sdiv-pow2.ll
+++ b/test/Transforms/LoopVectorize/AArch64/sdiv-pow2.ll
@@ -7,7 +7,7 @@ target triple = "aarch64--linux-gnu"
 @Foo = common global %struct.anon zeroinitializer, align 4
 
 ; CHECK-LABEL: @foo(
-; CHECK: load <4 x i32>*
+; CHECK: load <4 x i32>, <4 x i32>*
 ; CHECK: sdiv <4 x i32>
 ; CHECK: store <4 x i32>
 
@@ -17,10 +17,10 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds %struct.anon* @Foo, i64 0, i32 2, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds %struct.anon, %struct.anon* @Foo, i64 0, i32 2, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %div = sdiv i32 %0, 2
-  %arrayidx2 = getelementptr inbounds %struct.anon* @Foo, i64 0, i32 0, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds %struct.anon, %struct.anon* @Foo, i64 0, i32 0, i64 %indvars.iv
   store i32 %div, i32* %arrayidx2, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 100
diff --git a/test/Transforms/LoopVectorize/ARM/arm-unroll.ll b/test/Transforms/LoopVectorize/ARM/arm-unroll.ll
index 8843fc2d2b1a..7b09913636f7 100644
--- a/test/Transforms/LoopVectorize/ARM/arm-unroll.ll
+++ b/test/Transforms/LoopVectorize/ARM/arm-unroll.ll
@@ -20,8 +20,8 @@ define i32 @foo(i32* nocapture %A, i32 %n) nounwind readonly ssp {
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %i.02 = phi i32 [ %5, %.lr.ph ], [ 0, %0 ]
   %sum.01 = phi i32 [ %4, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds i32* %A, i32 %i.02
-  %3 = load i32* %2, align 4
+  %2 = getelementptr inbounds i32, i32* %A, i32 %i.02
+  %3 = load i32, i32* %2, align 4
   %4 = add nsw i32 %3, %sum.01
   %5 = add nsw i32 %i.02, 1
   %exitcond = icmp eq i32 %5, %n
@@ -48,8 +48,8 @@ define i32 @register_limit(i32* nocapture %A, i32 %n) {
   %sum.04 = phi i32 [ %8, %.lr.ph ], [ 0, %0 ]
   %sum.05 = phi i32 [ %9, %.lr.ph ], [ 0, %0 ]
   %sum.06 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds i32* %A, i32 %i.02
-  %3 = load i32* %2, align 4
+  %2 = getelementptr inbounds i32, i32* %A, i32 %i.02
+  %3 = load i32, i32* %2, align 4
   %4 = add nsw i32 %3, %sum.01
   %5 = add nsw i32 %i.02, 1
   %6 = add nsw i32 %3, %sum.02
diff --git a/test/Transforms/LoopVectorize/ARM/gather-cost.ll b/test/Transforms/LoopVectorize/ARM/gather-cost.ll
index 239a28fa6c7c..f14a8cc6ca2d 100644
--- a/test/Transforms/LoopVectorize/ARM/gather-cost.ll
+++ b/test/Transforms/LoopVectorize/ARM/gather-cost.ll
@@ -33,32 +33,32 @@ for.body:
   %b.054 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add30, %for.body ]
   %add = add i32 %v.055, %offset
   %mul = mul i32 %add, 3
-  %arrayidx = getelementptr inbounds [1536 x float]* @src_data, i32 0, i32 %mul
-  %0 = load float* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds [512 x float]* @kernel, i32 0, i32 %v.055
-  %1 = load float* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds [1536 x float], [1536 x float]* @src_data, i32 0, i32 %mul
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds [512 x float], [512 x float]* @kernel, i32 0, i32 %v.055
+  %1 = load float, float* %arrayidx2, align 4
   %mul3 = fmul fast float %0, %1
-  %arrayidx4 = getelementptr inbounds [512 x float]* @kernel2, i32 0, i32 %v.055
-  %2 = load float* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds [512 x float], [512 x float]* @kernel2, i32 0, i32 %v.055
+  %2 = load float, float* %arrayidx4, align 4
   %mul5 = fmul fast float %mul3, %2
-  %arrayidx6 = getelementptr inbounds [512 x float]* @kernel3, i32 0, i32 %v.055
-  %3 = load float* %arrayidx6, align 4
+  %arrayidx6 = getelementptr inbounds [512 x float], [512 x float]* @kernel3, i32 0, i32 %v.055
+  %3 = load float, float* %arrayidx6, align 4
   %mul7 = fmul fast float %mul5, %3
-  %arrayidx8 = getelementptr inbounds [512 x float]* @kernel4, i32 0, i32 %v.055
-  %4 = load float* %arrayidx8, align 4
+  %arrayidx8 = getelementptr inbounds [512 x float], [512 x float]* @kernel4, i32 0, i32 %v.055
+  %4 = load float, float* %arrayidx8, align 4
   %mul9 = fmul fast float %mul7, %4
   %add10 = fadd fast float %r.057, %mul9
   %arrayidx.sum = add i32 %mul, 1
-  %arrayidx11 = getelementptr inbounds [1536 x float]* @src_data, i32 0, i32 %arrayidx.sum
-  %5 = load float* %arrayidx11, align 4
+  %arrayidx11 = getelementptr inbounds [1536 x float], [1536 x float]* @src_data, i32 0, i32 %arrayidx.sum
+  %5 = load float, float* %arrayidx11, align 4
   %mul13 = fmul fast float %1, %5
   %mul15 = fmul fast float %2, %mul13
   %mul17 = fmul fast float %3, %mul15
   %mul19 = fmul fast float %4, %mul17
   %add20 = fadd fast float %g.056, %mul19
   %arrayidx.sum52 = add i32 %mul, 2
-  %arrayidx21 = getelementptr inbounds [1536 x float]* @src_data, i32 0, i32 %arrayidx.sum52
-  %6 = load float* %arrayidx21, align 4
+  %arrayidx21 = getelementptr inbounds [1536 x float], [1536 x float]* @src_data, i32 0, i32 %arrayidx.sum52
+  %6 = load float, float* %arrayidx21, align 4
   %mul23 = fmul fast float %1, %6
   %mul25 = fmul fast float %2, %mul23
   %mul27 = fmul fast float %3, %mul25
diff --git a/test/Transforms/LoopVectorize/ARM/gcc-examples.ll b/test/Transforms/LoopVectorize/ARM/gcc-examples.ll
index f2bd0ac200d4..783156d7399d 100644
--- a/test/Transforms/LoopVectorize/ARM/gcc-examples.ll
+++ b/test/Transforms/LoopVectorize/ARM/gcc-examples.ll
@@ -18,12 +18,12 @@ define void @example1() nounwind uwtable ssp {
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %indvars.iv
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds [2048 x i32]* @c, i64 0, i64 %indvars.iv
-  %5 = load i32* %4, align 4
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds [2048 x i32], [2048 x i32]* @c, i64 0, i64 %indvars.iv
+  %5 = load i32, i32* %4, align 4
   %6 = add nsw i32 %5, %3
-  %7 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %7 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
   store i32 %6, i32* %7, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -44,10 +44,10 @@ define void @example10b(i16* noalias nocapture %sa, i16* noalias nocapture %sb,
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds i16* %sb, i64 %indvars.iv
-  %3 = load i16* %2, align 2
+  %2 = getelementptr inbounds i16, i16* %sb, i64 %indvars.iv
+  %3 = load i16, i16* %2, align 2
   %4 = sext i16 %3 to i32
-  %5 = getelementptr inbounds i32* %ia, i64 %indvars.iv
+  %5 = getelementptr inbounds i32, i32* %ia, i64 %indvars.iv
   store i32 %4, i32* %5, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/ARM/mul-cast-vect.ll b/test/Transforms/LoopVectorize/ARM/mul-cast-vect.ll
index d2e3de279f7c..e88fcca1225c 100644
--- a/test/Transforms/LoopVectorize/ARM/mul-cast-vect.ll
+++ b/test/Transforms/LoopVectorize/ARM/mul-cast-vect.ll
@@ -16,9 +16,9 @@ target triple = "armv7--linux-gnueabihf"
 
 define void @direct(%T432* %loadaddr, %T432* %loadaddr2, %T432* %storeaddr) {
 ; COST: function 'direct':
-  %v0 = load %T432* %loadaddr
+  %v0 = load %T432, %T432* %loadaddr
 ; ASM: vld1.64
-  %v1 = load %T432* %loadaddr2
+  %v1 = load %T432, %T432* %loadaddr2
 ; ASM: vld1.64
   %r3 = mul %T432 %v0, %v1 
 ; COST: cost of 2 for instruction: {{.*}} mul <4 x i32>
@@ -30,9 +30,9 @@ define void @direct(%T432* %loadaddr, %T432* %loadaddr2, %T432* %storeaddr) {
 
 define void @ups1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
 ; COST: function 'ups1632':
-  %v0 = load %T416* %loadaddr
+  %v0 = load %T416, %T416* %loadaddr
 ; ASM: vldr
-  %v1 = load %T416* %loadaddr2
+  %v1 = load %T416, %T416* %loadaddr2
 ; ASM: vldr
   %r1 = sext %T416 %v0 to %T432
   %r2 = sext %T416 %v1 to %T432
@@ -47,9 +47,9 @@ define void @ups1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
 
 define void @upu1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
 ; COST: function 'upu1632':
-  %v0 = load %T416* %loadaddr
+  %v0 = load %T416, %T416* %loadaddr
 ; ASM: vldr
-  %v1 = load %T416* %loadaddr2
+  %v1 = load %T416, %T416* %loadaddr2
 ; ASM: vldr
   %r1 = zext %T416 %v0 to %T432
   %r2 = zext %T416 %v1 to %T432
@@ -64,9 +64,9 @@ define void @upu1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
 
 define void @ups3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) {
 ; COST: function 'ups3264':
-  %v0 = load %T232* %loadaddr
+  %v0 = load %T232, %T232* %loadaddr
 ; ASM: vldr
-  %v1 = load %T232* %loadaddr2
+  %v1 = load %T232, %T232* %loadaddr2
 ; ASM: vldr
   %r3 = mul %T232 %v0, %v1 
 ; ASM: vmul.i32
@@ -81,9 +81,9 @@ define void @ups3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) {
 
 define void @upu3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) {
 ; COST: function 'upu3264':
-  %v0 = load %T232* %loadaddr
+  %v0 = load %T232, %T232* %loadaddr
 ; ASM: vldr
-  %v1 = load %T232* %loadaddr2
+  %v1 = load %T232, %T232* %loadaddr2
 ; ASM: vldr
   %r3 = mul %T232 %v0, %v1 
 ; ASM: vmul.i32
@@ -98,9 +98,9 @@ define void @upu3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) {
 
 define void @dn3216(%T432* %loadaddr, %T432* %loadaddr2, %T416* %storeaddr) {
 ; COST: function 'dn3216':
-  %v0 = load %T432* %loadaddr
+  %v0 = load %T432, %T432* %loadaddr
 ; ASM: vld1.64
-  %v1 = load %T432* %loadaddr2
+  %v1 = load %T432, %T432* %loadaddr2
 ; ASM: vld1.64
   %r3 = mul %T432 %v0, %v1 
 ; ASM: vmul.i32
diff --git a/test/Transforms/LoopVectorize/ARM/width-detect.ll b/test/Transforms/LoopVectorize/ARM/width-detect.ll
index 99d7fa75ee33..66d2556dfb83 100644
--- a/test/Transforms/LoopVectorize/ARM/width-detect.ll
+++ b/test/Transforms/LoopVectorize/ARM/width-detect.ll
@@ -13,8 +13,8 @@ define float @foo_F32(float* nocapture %A, i32 %n) nounwind uwtable readonly ssp
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
   %prod.01 = phi float [ %4, %.lr.ph ], [ 0.000000e+00, %0 ]
-  %2 = getelementptr inbounds float* %A, i64 %indvars.iv
-  %3 = load float* %2, align 8
+  %2 = getelementptr inbounds float, float* %A, i64 %indvars.iv
+  %3 = load float, float* %2, align 8
   %4 = fmul fast float %prod.01, %3
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -36,8 +36,8 @@ define signext i8 @foo_I8(i8* nocapture %A, i32 %n) nounwind uwtable readonly ss
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
   %red.01 = phi i8 [ %4, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds i8* %A, i64 %indvars.iv
-  %3 = load i8* %2, align 1
+  %2 = getelementptr inbounds i8, i8* %A, i64 %indvars.iv
+  %3 = load i8, i8* %2, align 1
   %4 = xor i8 %3, %red.01
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/PowerPC/large-loop-rdx.ll b/test/Transforms/LoopVectorize/PowerPC/large-loop-rdx.ll
new file mode 100644
index 000000000000..de6595f64ed3
--- /dev/null
+++ b/test/Transforms/LoopVectorize/PowerPC/large-loop-rdx.ll
@@ -0,0 +1,73 @@
+; RUN: opt < %s -loop-vectorize -S | FileCheck %s
+
+; CHECK: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT-NOT: fadd
+
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-ibm-linux-gnu"
+
+define void @QLA_F3_r_veq_norm2_V(float* noalias nocapture %r, [3 x { float, float }]* noalias nocapture readonly %a, i32 signext %n) #0 {
+entry:
+  %cmp24 = icmp sgt i32 %n, 0
+  br i1 %cmp24, label %for.cond1.preheader.preheader, label %for.end13
+
+for.cond1.preheader.preheader:                    ; preds = %entry
+  br label %for.cond1.preheader
+
+for.cond1.preheader:                              ; preds = %for.cond1.preheader.preheader, %for.cond1.preheader
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.cond1.preheader ], [ 0, %for.cond1.preheader.preheader ]
+  %sum.026 = phi double [ %add10.2, %for.cond1.preheader ], [ 0.000000e+00, %for.cond1.preheader.preheader ]
+  %arrayidx5.realp = getelementptr inbounds [3 x { float, float }], [3 x { float, float }]* %a, i64 %indvars.iv, i64 0, i32 0
+  %arrayidx5.real = load float, float* %arrayidx5.realp, align 8
+  %arrayidx5.imagp = getelementptr inbounds [3 x { float, float }], [3 x { float, float }]* %a, i64 %indvars.iv, i64 0, i32 1
+  %arrayidx5.imag = load float, float* %arrayidx5.imagp, align 8
+  %mul = fmul fast float %arrayidx5.real, %arrayidx5.real
+  %mul9 = fmul fast float %arrayidx5.imag, %arrayidx5.imag
+  %add = fadd fast float %mul9, %mul
+  %conv = fpext float %add to double
+  %add10 = fadd fast double %conv, %sum.026
+  %arrayidx5.realp.1 = getelementptr inbounds [3 x { float, float }], [3 x { float, float }]* %a, i64 %indvars.iv, i64 1, i32 0
+  %arrayidx5.real.1 = load float, float* %arrayidx5.realp.1, align 8
+  %arrayidx5.imagp.1 = getelementptr inbounds [3 x { float, float }], [3 x { float, float }]* %a, i64 %indvars.iv, i64 1, i32 1
+  %arrayidx5.imag.1 = load float, float* %arrayidx5.imagp.1, align 8
+  %mul.1 = fmul fast float %arrayidx5.real.1, %arrayidx5.real.1
+  %mul9.1 = fmul fast float %arrayidx5.imag.1, %arrayidx5.imag.1
+  %add.1 = fadd fast float %mul9.1, %mul.1
+  %conv.1 = fpext float %add.1 to double
+  %add10.1 = fadd fast double %conv.1, %add10
+  %arrayidx5.realp.2 = getelementptr inbounds [3 x { float, float }], [3 x { float, float }]* %a, i64 %indvars.iv, i64 2, i32 0
+  %arrayidx5.real.2 = load float, float* %arrayidx5.realp.2, align 8
+  %arrayidx5.imagp.2 = getelementptr inbounds [3 x { float, float }], [3 x { float, float }]* %a, i64 %indvars.iv, i64 2, i32 1
+  %arrayidx5.imag.2 = load float, float* %arrayidx5.imagp.2, align 8
+  %mul.2 = fmul fast float %arrayidx5.real.2, %arrayidx5.real.2
+  %mul9.2 = fmul fast float %arrayidx5.imag.2, %arrayidx5.imag.2
+  %add.2 = fadd fast float %mul9.2, %mul.2
+  %conv.2 = fpext float %add.2 to double
+  %add10.2 = fadd fast double %conv.2, %add10.1
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.cond.for.end13_crit_edge, label %for.cond1.preheader
+
+for.cond.for.end13_crit_edge:                     ; preds = %for.cond1.preheader
+  %add10.2.lcssa = phi double [ %add10.2, %for.cond1.preheader ]
+  %phitmp = fptrunc double %add10.2.lcssa to float
+  br label %for.end13
+
+for.end13:                                        ; preds = %for.cond.for.end13_crit_edge, %entry
+  %sum.0.lcssa = phi float [ %phitmp, %for.cond.for.end13_crit_edge ], [ 0.000000e+00, %entry ]
+  store float %sum.0.lcssa, float* %r, align 4
+  ret void
+}
+
diff --git a/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll b/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll
new file mode 100644
index 000000000000..2898af2986d3
--- /dev/null
+++ b/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll
@@ -0,0 +1,47 @@
+; RUN: opt < %s -loop-vectorize -S | FileCheck %s
+
+; CHECK: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT: fadd
+; CHECK-NEXT-NOT: fadd
+
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-ibm-linux-gnu"
+
+define void @test(double* nocapture readonly %arr, i32 signext %len) #0 {
+entry:
+  %cmp4 = icmp sgt i32 %len, 0
+  br i1 %cmp4, label %for.body.lr.ph, label %for.end
+
+for.body.lr.ph:                                   ; preds = %entry
+  %0 = add i32 %len, -1
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %for.body.lr.ph
+  %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]
+  %redx.05 = phi double [ 0.000000e+00, %for.body.lr.ph ], [ %add, %for.body ]
+  %arrayidx = getelementptr inbounds double, double* %arr, i64 %indvars.iv
+  %1 = load double, double* %arrayidx, align 8
+  %add = fadd fast double %1, %redx.05
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %0
+  br i1 %exitcond, label %for.end.loopexit, label %for.body
+
+for.end.loopexit:                                 ; preds = %for.body
+  %add.lcssa = phi double [ %add, %for.body ]
+  br label %for.end
+
+for.end:                                          ; preds = %for.end.loopexit, %entry
+  %redx.0.lcssa = phi double [ 0.000000e+00, %entry ], [ %add.lcssa, %for.end.loopexit ]
+  ret void
+}
diff --git a/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll b/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll
index 6cd9c4d610b5..65b3919585e3 100644
--- a/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll
+++ b/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll
@@ -9,7 +9,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i32 @s173() #0 {
 entry:
-  %0 = load i32* @ntimes, align 4
+  %0 = load i32, i32* @ntimes, align 4
   %cmp21 = icmp sgt i32 %0, 0
   br i1 %cmp21, label %for.cond1.preheader, label %for.end12
 
@@ -19,13 +19,13 @@ for.cond1.preheader:                              ; preds = %for.end, %entry
 
 for.body3:                                        ; preds = %for.body3, %for.cond1.preheader
   %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.body3 ]
-  %arrayidx = getelementptr inbounds %struct.GlobalData* @global_data, i64 0, i32 0, i64 %indvars.iv
-  %1 = load float* %arrayidx, align 4
-  %arrayidx5 = getelementptr inbounds %struct.GlobalData* @global_data, i64 0, i32 3, i64 %indvars.iv
-  %2 = load float* %arrayidx5, align 4
+  %arrayidx = getelementptr inbounds %struct.GlobalData, %struct.GlobalData* @global_data, i64 0, i32 0, i64 %indvars.iv
+  %1 = load float, float* %arrayidx, align 4
+  %arrayidx5 = getelementptr inbounds %struct.GlobalData, %struct.GlobalData* @global_data, i64 0, i32 3, i64 %indvars.iv
+  %2 = load float, float* %arrayidx5, align 4
   %add = fadd float %1, %2
   %3 = add nsw i64 %indvars.iv, 16000
-  %arrayidx8 = getelementptr inbounds %struct.GlobalData* @global_data, i64 0, i32 0, i64 %3
+  %arrayidx8 = getelementptr inbounds %struct.GlobalData, %struct.GlobalData* @global_data, i64 0, i32 0, i64 %3
   store float %add, float* %arrayidx8, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 16000
@@ -33,7 +33,7 @@ for.body3:                                        ; preds = %for.body3, %for.con
 
 for.end:                                          ; preds = %for.body3
   %inc11 = add nsw i32 %nl.022, 1
-  %4 = load i32* @ntimes, align 4
+  %4 = load i32, i32* @ntimes, align 4
   %mul = mul nsw i32 %4, 10
   %cmp = icmp slt i32 %inc11, %mul
   br i1 %cmp, label %for.cond1.preheader, label %for.end12
@@ -42,7 +42,7 @@ for.end12:                                        ; preds = %for.end, %entry
   ret i32 0
 
 ; CHECK-LABEL: @s173
-; CHECK: load <4 x float>*
+; CHECK: load <4 x float>, <4 x float>*
 ; CHECK: add i64 %index, 16000
 ; CHECK: ret i32 0
 }
diff --git a/test/Transforms/LoopVectorize/X86/already-vectorized.ll b/test/Transforms/LoopVectorize/X86/already-vectorized.ll
index 29d74a0645e8..c400c76461bb 100644
--- a/test/Transforms/LoopVectorize/X86/already-vectorized.ll
+++ b/test/Transforms/LoopVectorize/X86/already-vectorized.ll
@@ -21,8 +21,8 @@ for.body:                                         ; preds = %for.body, %entry
 ; CHECK: LV: We can vectorize this loop!
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %red.05 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds [255 x i32]* @a, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [255 x i32], [255 x i32]* @a, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %red.05
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 255
@@ -42,5 +42,6 @@ for.end:                                          ; preds = %for.body
 ; CHECK: [[vect]] = distinct !{[[vect]], [[width:![0-9]+]], [[unroll:![0-9]+]]}
 ; CHECK: [[width]] = !{!"llvm.loop.vectorize.width", i32 1}
 ; CHECK: [[unroll]] = !{!"llvm.loop.interleave.count", i32 1}
-; CHECK: [[scalar]] = distinct !{[[scalar]], [[width]], [[unroll]]}
+; CHECK: [[scalar]] = distinct !{[[scalar]], [[runtime_unroll:![0-9]+]], [[width]], [[unroll]]}
+; CHECK: [[runtime_unroll]] = !{!"llvm.loop.unroll.runtime.disable"}
 
diff --git a/test/Transforms/LoopVectorize/X86/assume.ll b/test/Transforms/LoopVectorize/X86/assume.ll
index a94e24dd7e9c..4fd378d1a0a9 100644
--- a/test/Transforms/LoopVectorize/X86/assume.ll
+++ b/test/Transforms/LoopVectorize/X86/assume.ll
@@ -22,12 +22,12 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %b, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp1 = fcmp ogt float %0, 1.000000e+02
   tail call void @llvm.assume(i1 %cmp1)
   %add = fadd float %0, 1.000000e+00
-  %arrayidx5 = getelementptr inbounds float* %a, i64 %indvars.iv
+  %arrayidx5 = getelementptr inbounds float, float* %a, i64 %indvars.iv
   store float %add, float* %arrayidx5, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv, 1599
@@ -48,13 +48,13 @@ attributes #1 = { nounwind }
 ; Function Attrs: nounwind uwtable
 define void @test2(%struct.data* nocapture readonly %d) #0 {
 entry:
-  %b = getelementptr inbounds %struct.data* %d, i64 0, i32 1
-  %0 = load float** %b, align 8
+  %b = getelementptr inbounds %struct.data, %struct.data* %d, i64 0, i32 1
+  %0 = load float*, float** %b, align 8
   %ptrint = ptrtoint float* %0 to i64
   %maskedptr = and i64 %ptrint, 31
   %maskcond = icmp eq i64 %maskedptr, 0
-  %a = getelementptr inbounds %struct.data* %d, i64 0, i32 0
-  %1 = load float** %a, align 8
+  %a = getelementptr inbounds %struct.data, %struct.data* %d, i64 0, i32 0
+  %1 = load float*, float** %a, align 8
   %ptrint2 = ptrtoint float* %1 to i64
   %maskedptr3 = and i64 %ptrint2, 31
   %maskcond4 = icmp eq i64 %maskedptr3, 0
@@ -84,11 +84,11 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   tail call void @llvm.assume(i1 %maskcond)
-  %arrayidx = getelementptr inbounds float* %0, i64 %indvars.iv
-  %2 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %0, i64 %indvars.iv
+  %2 = load float, float* %arrayidx, align 4
   %add = fadd float %2, 1.000000e+00
   tail call void @llvm.assume(i1 %maskcond4)
-  %arrayidx5 = getelementptr inbounds float* %1, i64 %indvars.iv
+  %arrayidx5 = getelementptr inbounds float, float* %1, i64 %indvars.iv
   store float %add, float* %arrayidx5, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv, 1599
diff --git a/test/Transforms/LoopVectorize/X86/avx1.ll b/test/Transforms/LoopVectorize/X86/avx1.ll
index 01c912567b61..37977c43ac30 100644
--- a/test/Transforms/LoopVectorize/X86/avx1.ll
+++ b/test/Transforms/LoopVectorize/X86/avx1.ll
@@ -12,8 +12,8 @@ define i32 @read_mod_write_single_ptr(float* nocapture %a, i32 %n) nounwind uwta
 
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds float* %a, i64 %indvars.iv
-  %3 = load float* %2, align 4
+  %2 = getelementptr inbounds float, float* %a, i64 %indvars.iv
+  %3 = load float, float* %2, align 4
   %4 = fmul float %3, 3.000000e+00
   store float %4, float* %2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -35,8 +35,8 @@ define i32 @read_mod_i64(i64* nocapture %a, i32 %n) nounwind uwtable ssp {
 
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds i64* %a, i64 %indvars.iv
-  %3 = load i64* %2, align 4
+  %2 = getelementptr inbounds i64, i64* %a, i64 %indvars.iv
+  %3 = load i64, i64* %2, align 4
   %4 = add i64 %3, 3
   store i64 %4, i64* %2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/X86/avx512.ll b/test/Transforms/LoopVectorize/X86/avx512.ll
index a2208668177d..754e859cd8fe 100644
--- a/test/Transforms/LoopVectorize/X86/avx512.ll
+++ b/test/Transforms/LoopVectorize/X86/avx512.ll
@@ -20,7 +20,7 @@ for.body.preheader:                               ; preds = %entry
 
 for.body:                                         ; preds = %for.body.preheader, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
   store i32 %n, i32* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/X86/constant-vector-operand.ll b/test/Transforms/LoopVectorize/X86/constant-vector-operand.ll
index f4c07b4b24d9..d75b1d940ae2 100644
--- a/test/Transforms/LoopVectorize/X86/constant-vector-operand.ll
+++ b/test/Transforms/LoopVectorize/X86/constant-vector-operand.ll
@@ -15,10 +15,10 @@ entry:
 
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @B, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @B, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %shl = ashr i32 %0, 3
-  %arrayidx2 = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv
   store i32 %shl, i32* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/X86/conversion-cost.ll b/test/Transforms/LoopVectorize/X86/conversion-cost.ll
index 0af562db8479..eb2a2a56fae1 100644
--- a/test/Transforms/LoopVectorize/X86/conversion-cost.ll
+++ b/test/Transforms/LoopVectorize/X86/conversion-cost.ll
@@ -13,7 +13,7 @@ define i32 @conversion_cost1(i32 %n, i8* nocapture %A, float* nocapture %B) noun
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 3, %0 ]
   %2 = trunc i64 %indvars.iv to i8
-  %3 = getelementptr inbounds i8* %A, i64 %indvars.iv
+  %3 = getelementptr inbounds i8, i8* %A, i64 %indvars.iv
   store i8 %2, i8* %3, align 1
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -35,7 +35,7 @@ define i32 @conversion_cost2(i32 %n, i8* nocapture %A, float* nocapture %B) noun
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 9, %0 ]
   %add = add nsw i64 %indvars.iv, 3
   %tofp = sitofp i64 %add to float
-  %gep = getelementptr inbounds float* %B, i64 %indvars.iv
+  %gep = getelementptr inbounds float, float* %B, i64 %indvars.iv
   store float %tofp, float* %gep, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/X86/cost-model.ll b/test/Transforms/LoopVectorize/X86/cost-model.ll
index 98718e1e9708..013657102e6b 100644
--- a/test/Transforms/LoopVectorize/X86/cost-model.ll
+++ b/test/Transforms/LoopVectorize/X86/cost-model.ll
@@ -21,15 +21,15 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %0 = shl nsw i64 %indvars.iv, 1
-  %arrayidx = getelementptr inbounds [2048 x i32]* @c, i64 0, i64 %0
-  %1 = load i32* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds [2048 x i32], [2048 x i32]* @c, i64 0, i64 %0
+  %1 = load i32, i32* %arrayidx, align 8
   %idxprom1 = sext i32 %1 to i64
-  %arrayidx2 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %idxprom1
-  %2 = load i32* %arrayidx2, align 4
-  %arrayidx4 = getelementptr inbounds [2048 x i32]* @d, i64 0, i64 %indvars.iv
-  %3 = load i32* %arrayidx4, align 4
+  %arrayidx2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %idxprom1
+  %2 = load i32, i32* %arrayidx2, align 4
+  %arrayidx4 = getelementptr inbounds [2048 x i32], [2048 x i32]* @d, i64 0, i64 %indvars.iv
+  %3 = load i32, i32* %arrayidx4, align 4
   %idxprom5 = sext i32 %3 to i64
-  %arrayidx6 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %idxprom5
+  %arrayidx6 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %idxprom5
   store i32 %2, i32* %arrayidx6, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/X86/fp32_to_uint32-cost-model.ll b/test/Transforms/LoopVectorize/X86/fp32_to_uint32-cost-model.ll
index 529ed883c3b4..4a56d6b5ebf6 100644
--- a/test/Transforms/LoopVectorize/X86/fp32_to_uint32-cost-model.ll
+++ b/test/Transforms/LoopVectorize/X86/fp32_to_uint32-cost-model.ll
@@ -20,10 +20,10 @@ for.body.preheader:                               ; preds = %entry
 
 for.body:                                         ; preds = %for.body.preheader, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
-  %arrayidx = getelementptr inbounds [10000 x float]* @float_array, i64 0, i64 %indvars.iv
-  %1 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [10000 x float], [10000 x float]* @float_array, i64 0, i64 %indvars.iv
+  %1 = load float, float* %arrayidx, align 4
   %conv = fptoui float %1 to i32
-  %arrayidx2 = getelementptr inbounds [10000 x i32]* @unsigned_array, i64 0, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds [10000 x i32], [10000 x i32]* @unsigned_array, i64 0, i64 %indvars.iv
   store i32 %conv, i32* %arrayidx2, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/X86/fp64_to_uint32-cost-model.ll b/test/Transforms/LoopVectorize/X86/fp64_to_uint32-cost-model.ll
index ef3e3bec793a..c066afcfa63e 100644
--- a/test/Transforms/LoopVectorize/X86/fp64_to_uint32-cost-model.ll
+++ b/test/Transforms/LoopVectorize/X86/fp64_to_uint32-cost-model.ll
@@ -13,7 +13,7 @@ target triple = "x86_64-apple-macosx"
 
 define void @convert() {
 entry:
-  %0 = load i32* @n, align 4
+  %0 = load i32, i32* @n, align 4
   %cmp4 = icmp eq i32 %0, 0
   br i1 %cmp4, label %for.end, label %for.body.preheader
 
@@ -22,10 +22,10 @@ for.body.preheader:                               ; preds = %entry
 
 for.body:                                         ; preds = %for.body.preheader, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
-  %arrayidx = getelementptr inbounds [10000 x double]* @double_array, i64 0, i64 %indvars.iv
-  %1 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds [10000 x double], [10000 x double]* @double_array, i64 0, i64 %indvars.iv
+  %1 = load double, double* %arrayidx, align 8
   %conv = fptoui double %1 to i32
-  %arrayidx2 = getelementptr inbounds [10000 x i32]* @unsigned_array, i64 0, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds [10000 x i32], [10000 x i32]* @unsigned_array, i64 0, i64 %indvars.iv
   store i32 %conv, i32* %arrayidx2, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %2 = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/X86/fp_to_sint8-cost-model.ll b/test/Transforms/LoopVectorize/X86/fp_to_sint8-cost-model.ll
index 23e62275ce04..b3a0710545d7 100644
--- a/test/Transforms/LoopVectorize/X86/fp_to_sint8-cost-model.ll
+++ b/test/Transforms/LoopVectorize/X86/fp_to_sint8-cost-model.ll
@@ -11,10 +11,10 @@ entry:
   br label %for.body
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv
-  %tmp = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %b, i64 %indvars.iv
+  %tmp = load float, float* %arrayidx, align 4
   %conv = fptosi float %tmp to i8
-  %arrayidx2 = getelementptr inbounds i8* %a, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds i8, i8* %a, i64 %indvars.iv
   store i8 %conv, i8* %arrayidx2, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 256
diff --git a/test/Transforms/LoopVectorize/X86/gather-cost.ll b/test/Transforms/LoopVectorize/X86/gather-cost.ll
index 09363d65eefc..f0e6c8f205cf 100644
--- a/test/Transforms/LoopVectorize/X86/gather-cost.ll
+++ b/test/Transforms/LoopVectorize/X86/gather-cost.ll
@@ -31,32 +31,32 @@ for.body:
   %b.054 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add30, %for.body ]
   %add = add i64 %v.055, %offset
   %mul = mul i64 %add, 3
-  %arrayidx = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %mul
-  %0 = load float* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds [512 x float]* @kernel, i64 0, i64 %v.055
-  %1 = load float* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds [1536 x float], [1536 x float]* @src_data, i64 0, i64 %mul
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds [512 x float], [512 x float]* @kernel, i64 0, i64 %v.055
+  %1 = load float, float* %arrayidx2, align 4
   %mul3 = fmul fast float %0, %1
-  %arrayidx4 = getelementptr inbounds [512 x float]* @kernel2, i64 0, i64 %v.055
-  %2 = load float* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds [512 x float], [512 x float]* @kernel2, i64 0, i64 %v.055
+  %2 = load float, float* %arrayidx4, align 4
   %mul5 = fmul fast float %mul3, %2
-  %arrayidx6 = getelementptr inbounds [512 x float]* @kernel3, i64 0, i64 %v.055
-  %3 = load float* %arrayidx6, align 4
+  %arrayidx6 = getelementptr inbounds [512 x float], [512 x float]* @kernel3, i64 0, i64 %v.055
+  %3 = load float, float* %arrayidx6, align 4
   %mul7 = fmul fast float %mul5, %3
-  %arrayidx8 = getelementptr inbounds [512 x float]* @kernel4, i64 0, i64 %v.055
-  %4 = load float* %arrayidx8, align 4
+  %arrayidx8 = getelementptr inbounds [512 x float], [512 x float]* @kernel4, i64 0, i64 %v.055
+  %4 = load float, float* %arrayidx8, align 4
   %mul9 = fmul fast float %mul7, %4
   %add10 = fadd fast float %r.057, %mul9
   %arrayidx.sum = add i64 %mul, 1
-  %arrayidx11 = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum
-  %5 = load float* %arrayidx11, align 4
+  %arrayidx11 = getelementptr inbounds [1536 x float], [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum
+  %5 = load float, float* %arrayidx11, align 4
   %mul13 = fmul fast float %1, %5
   %mul15 = fmul fast float %2, %mul13
   %mul17 = fmul fast float %3, %mul15
   %mul19 = fmul fast float %4, %mul17
   %add20 = fadd fast float %g.056, %mul19
   %arrayidx.sum52 = add i64 %mul, 2
-  %arrayidx21 = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum52
-  %6 = load float* %arrayidx21, align 4
+  %arrayidx21 = getelementptr inbounds [1536 x float], [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum52
+  %6 = load float, float* %arrayidx21, align 4
   %mul23 = fmul fast float %1, %6
   %mul25 = fmul fast float %2, %mul23
   %mul27 = fmul fast float %3, %mul25
diff --git a/test/Transforms/LoopVectorize/X86/gcc-examples.ll b/test/Transforms/LoopVectorize/X86/gcc-examples.ll
index 05403cd5b61b..c581f4bf2a63 100644
--- a/test/Transforms/LoopVectorize/X86/gcc-examples.ll
+++ b/test/Transforms/LoopVectorize/X86/gcc-examples.ll
@@ -28,12 +28,12 @@ define void @example1() nounwind uwtable ssp {
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %indvars.iv
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds [2048 x i32]* @c, i64 0, i64 %indvars.iv
-  %5 = load i32* %4, align 4
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds [2048 x i32], [2048 x i32]* @c, i64 0, i64 %indvars.iv
+  %5 = load i32, i32* %4, align 4
   %6 = add nsw i32 %5, %3
-  %7 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %7 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
   store i32 %6, i32* %7, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -61,10 +61,10 @@ define void @example10b(i16* noalias nocapture %sa, i16* noalias nocapture %sb,
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds i16* %sb, i64 %indvars.iv
-  %3 = load i16* %2, align 2
+  %2 = getelementptr inbounds i16, i16* %sb, i64 %indvars.iv
+  %3 = load i16, i16* %2, align 2
   %4 = sext i16 %3 to i32
-  %5 = getelementptr inbounds i32* %ia, i64 %indvars.iv
+  %5 = getelementptr inbounds i32, i32* %ia, i64 %indvars.iv
   store i32 %4, i32* %5, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll b/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll
index 46efaf0e8531..cbba5300b9cb 100644
--- a/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll
+++ b/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll
@@ -14,8 +14,8 @@ entry:
   br i1 %cmp27, label %for.body3.lr.ph.us, label %for.end15
 
 for.end.us:                                       ; preds = %for.body3.us
-  %arrayidx9.us = getelementptr inbounds i32* %b, i64 %indvars.iv33
-  %0 = load i32* %arrayidx9.us, align 4, !llvm.mem.parallel_loop_access !3
+  %arrayidx9.us = getelementptr inbounds i32, i32* %b, i64 %indvars.iv33
+  %0 = load i32, i32* %arrayidx9.us, align 4, !llvm.mem.parallel_loop_access !3
   %add10.us = add nsw i32 %0, 3
   store i32 %add10.us, i32* %arrayidx9.us, align 4, !llvm.mem.parallel_loop_access !3
   %indvars.iv.next34 = add i64 %indvars.iv33, 1
@@ -28,8 +28,8 @@ for.body3.us:                                     ; preds = %for.body3.us, %for.
   %1 = trunc i64 %indvars.iv29 to i32
   %add4.us = add i32 %add.us, %1
   %idxprom.us = sext i32 %add4.us to i64
-  %arrayidx.us = getelementptr inbounds i32* %a, i64 %idxprom.us
-  %2 = load i32* %arrayidx.us, align 4, !llvm.mem.parallel_loop_access !3
+  %arrayidx.us = getelementptr inbounds i32, i32* %a, i64 %idxprom.us
+  %2 = load i32, i32* %arrayidx.us, align 4, !llvm.mem.parallel_loop_access !3
   %add5.us = add nsw i32 %2, 1
   store i32 %add5.us, i32* %arrayidx7.us, align 4, !llvm.mem.parallel_loop_access !3
   %indvars.iv.next30 = add i64 %indvars.iv29, 1
@@ -41,7 +41,7 @@ for.body3.lr.ph.us:                               ; preds = %for.end.us, %entry
   %indvars.iv33 = phi i64 [ %indvars.iv.next34, %for.end.us ], [ 0, %entry ]
   %3 = trunc i64 %indvars.iv33 to i32
   %add.us = add i32 %3, %k
-  %arrayidx7.us = getelementptr inbounds i32* %a, i64 %indvars.iv33
+  %arrayidx7.us = getelementptr inbounds i32, i32* %a, i64 %indvars.iv33
   br label %for.body3.us
 
 for.end15:                                        ; preds = %for.end.us, %entry
diff --git a/test/Transforms/LoopVectorize/X86/masked_load_store.ll b/test/Transforms/LoopVectorize/X86/masked_load_store.ll
index 9e2de8000587..8c375ccfd315 100644
--- a/test/Transforms/LoopVectorize/X86/masked_load_store.ll
+++ b/test/Transforms/LoopVectorize/X86/masked_load_store.ll
@@ -46,35 +46,35 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 10000
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %idxprom = sext i32 %1 to i64
-  %2 = load i32** %trigger.addr, align 8
-  %arrayidx = getelementptr inbounds i32* %2, i64 %idxprom
-  %3 = load i32* %arrayidx, align 4
+  %2 = load i32*, i32** %trigger.addr, align 8
+  %arrayidx = getelementptr inbounds i32, i32* %2, i64 %idxprom
+  %3 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp slt i32 %3, 100
   br i1 %cmp1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %for.body
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %idxprom2 = sext i32 %4 to i64
-  %5 = load i32** %B.addr, align 8
-  %arrayidx3 = getelementptr inbounds i32* %5, i64 %idxprom2
-  %6 = load i32* %arrayidx3, align 4
-  %7 = load i32* %i, align 4
+  %5 = load i32*, i32** %B.addr, align 8
+  %arrayidx3 = getelementptr inbounds i32, i32* %5, i64 %idxprom2
+  %6 = load i32, i32* %arrayidx3, align 4
+  %7 = load i32, i32* %i, align 4
   %idxprom4 = sext i32 %7 to i64
-  %8 = load i32** %trigger.addr, align 8
-  %arrayidx5 = getelementptr inbounds i32* %8, i64 %idxprom4
-  %9 = load i32* %arrayidx5, align 4
+  %8 = load i32*, i32** %trigger.addr, align 8
+  %arrayidx5 = getelementptr inbounds i32, i32* %8, i64 %idxprom4
+  %9 = load i32, i32* %arrayidx5, align 4
   %add = add nsw i32 %6, %9
-  %10 = load i32* %i, align 4
+  %10 = load i32, i32* %i, align 4
   %idxprom6 = sext i32 %10 to i64
-  %11 = load i32** %A.addr, align 8
-  %arrayidx7 = getelementptr inbounds i32* %11, i64 %idxprom6
+  %11 = load i32*, i32** %A.addr, align 8
+  %arrayidx7 = getelementptr inbounds i32, i32* %11, i64 %idxprom6
   store i32 %add, i32* %arrayidx7, align 4
   br label %if.end
 
@@ -82,7 +82,7 @@ if.end:                                           ; preds = %if.then, %for.body
   br label %for.inc
 
 for.inc:                                          ; preds = %if.end
-  %12 = load i32* %i, align 4
+  %12 = load i32, i32* %i, align 4
   %inc = add nsw i32 %12, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
@@ -130,36 +130,36 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 10000
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %idxprom = sext i32 %1 to i64
-  %2 = load i32** %trigger.addr, align 8
-  %arrayidx = getelementptr inbounds i32* %2, i64 %idxprom
-  %3 = load i32* %arrayidx, align 4
+  %2 = load i32*, i32** %trigger.addr, align 8
+  %arrayidx = getelementptr inbounds i32, i32* %2, i64 %idxprom
+  %3 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp slt i32 %3, 100
   br i1 %cmp1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %for.body
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %idxprom2 = sext i32 %4 to i64
-  %5 = load float** %B.addr, align 8
-  %arrayidx3 = getelementptr inbounds float* %5, i64 %idxprom2
-  %6 = load float* %arrayidx3, align 4
-  %7 = load i32* %i, align 4
+  %5 = load float*, float** %B.addr, align 8
+  %arrayidx3 = getelementptr inbounds float, float* %5, i64 %idxprom2
+  %6 = load float, float* %arrayidx3, align 4
+  %7 = load i32, i32* %i, align 4
   %idxprom4 = sext i32 %7 to i64
-  %8 = load i32** %trigger.addr, align 8
-  %arrayidx5 = getelementptr inbounds i32* %8, i64 %idxprom4
-  %9 = load i32* %arrayidx5, align 4
+  %8 = load i32*, i32** %trigger.addr, align 8
+  %arrayidx5 = getelementptr inbounds i32, i32* %8, i64 %idxprom4
+  %9 = load i32, i32* %arrayidx5, align 4
   %conv = sitofp i32 %9 to float
   %add = fadd float %6, %conv
-  %10 = load i32* %i, align 4
+  %10 = load i32, i32* %i, align 4
   %idxprom6 = sext i32 %10 to i64
-  %11 = load float** %A.addr, align 8
-  %arrayidx7 = getelementptr inbounds float* %11, i64 %idxprom6
+  %11 = load float*, float** %A.addr, align 8
+  %arrayidx7 = getelementptr inbounds float, float* %11, i64 %idxprom6
   store float %add, float* %arrayidx7, align 4
   br label %if.end
 
@@ -167,7 +167,7 @@ if.end:                                           ; preds = %if.then, %for.body
   br label %for.inc
 
 for.inc:                                          ; preds = %if.end
-  %12 = load i32* %i, align 4
+  %12 = load i32, i32* %i, align 4
   %inc = add nsw i32 %12, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
@@ -218,36 +218,36 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 10000
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %idxprom = sext i32 %1 to i64
-  %2 = load i32** %trigger.addr, align 8
-  %arrayidx = getelementptr inbounds i32* %2, i64 %idxprom
-  %3 = load i32* %arrayidx, align 4
+  %2 = load i32*, i32** %trigger.addr, align 8
+  %arrayidx = getelementptr inbounds i32, i32* %2, i64 %idxprom
+  %3 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp slt i32 %3, 100
   br i1 %cmp1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %for.body
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %idxprom2 = sext i32 %4 to i64
-  %5 = load double** %B.addr, align 8
-  %arrayidx3 = getelementptr inbounds double* %5, i64 %idxprom2
-  %6 = load double* %arrayidx3, align 8
-  %7 = load i32* %i, align 4
+  %5 = load double*, double** %B.addr, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %5, i64 %idxprom2
+  %6 = load double, double* %arrayidx3, align 8
+  %7 = load i32, i32* %i, align 4
   %idxprom4 = sext i32 %7 to i64
-  %8 = load i32** %trigger.addr, align 8
-  %arrayidx5 = getelementptr inbounds i32* %8, i64 %idxprom4
-  %9 = load i32* %arrayidx5, align 4
+  %8 = load i32*, i32** %trigger.addr, align 8
+  %arrayidx5 = getelementptr inbounds i32, i32* %8, i64 %idxprom4
+  %9 = load i32, i32* %arrayidx5, align 4
   %conv = sitofp i32 %9 to double
   %add = fadd double %6, %conv
-  %10 = load i32* %i, align 4
+  %10 = load i32, i32* %i, align 4
   %idxprom6 = sext i32 %10 to i64
-  %11 = load double** %A.addr, align 8
-  %arrayidx7 = getelementptr inbounds double* %11, i64 %idxprom6
+  %11 = load double*, double** %A.addr, align 8
+  %arrayidx7 = getelementptr inbounds double, double* %11, i64 %idxprom6
   store double %add, double* %arrayidx7, align 8
   br label %if.end
 
@@ -255,7 +255,7 @@ if.end:                                           ; preds = %if.then, %for.body
   br label %for.inc
 
 for.inc:                                          ; preds = %if.end
-  %12 = load i32* %i, align 4
+  %12 = load i32, i32* %i, align 4
   %inc = add nsw i32 %12, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
@@ -297,37 +297,37 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 10000
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %idxprom = sext i32 %1 to i64
-  %2 = load i32** %trigger.addr, align 8
-  %arrayidx = getelementptr inbounds i32* %2, i64 %idxprom
-  %3 = load i32* %arrayidx, align 4
+  %2 = load i32*, i32** %trigger.addr, align 8
+  %arrayidx = getelementptr inbounds i32, i32* %2, i64 %idxprom
+  %3 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp slt i32 %3, 100
   br i1 %cmp1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %for.body
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %mul = mul nsw i32 %4, 2
   %idxprom2 = sext i32 %mul to i64
-  %5 = load double** %B.addr, align 8
-  %arrayidx3 = getelementptr inbounds double* %5, i64 %idxprom2
-  %6 = load double* %arrayidx3, align 8
-  %7 = load i32* %i, align 4
+  %5 = load double*, double** %B.addr, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %5, i64 %idxprom2
+  %6 = load double, double* %arrayidx3, align 8
+  %7 = load i32, i32* %i, align 4
   %idxprom4 = sext i32 %7 to i64
-  %8 = load i32** %trigger.addr, align 8
-  %arrayidx5 = getelementptr inbounds i32* %8, i64 %idxprom4
-  %9 = load i32* %arrayidx5, align 4
+  %8 = load i32*, i32** %trigger.addr, align 8
+  %arrayidx5 = getelementptr inbounds i32, i32* %8, i64 %idxprom4
+  %9 = load i32, i32* %arrayidx5, align 4
   %conv = sitofp i32 %9 to double
   %add = fadd double %6, %conv
-  %10 = load i32* %i, align 4
+  %10 = load i32, i32* %i, align 4
   %idxprom6 = sext i32 %10 to i64
-  %11 = load double** %A.addr, align 8
-  %arrayidx7 = getelementptr inbounds double* %11, i64 %idxprom6
+  %11 = load double*, double** %A.addr, align 8
+  %arrayidx7 = getelementptr inbounds double, double* %11, i64 %idxprom6
   store double %add, double* %arrayidx7, align 8
   br label %if.end
 
@@ -335,7 +335,7 @@ if.end:                                           ; preds = %if.then, %for.body
   br label %for.inc
 
 for.inc:                                          ; preds = %if.end
-  %12 = load i32* %i, align 4
+  %12 = load i32, i32* %i, align 4
   %inc = add nsw i32 %12, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
@@ -373,43 +373,43 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 10000
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %idxprom = sext i32 %1 to i64
-  %2 = load i32** %trigger.addr, align 8
-  %arrayidx = getelementptr inbounds i32* %2, i64 %idxprom
-  %3 = load i32* %arrayidx, align 4
+  %2 = load i32*, i32** %trigger.addr, align 8
+  %arrayidx = getelementptr inbounds i32, i32* %2, i64 %idxprom
+  %3 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp slt i32 %3, 100
   br i1 %cmp1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %for.body
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %idxprom2 = sext i32 %4 to i64
-  %5 = load i32** %B.addr, align 8
-  %arrayidx3 = getelementptr inbounds i32* %5, i64 %idxprom2
-  %6 = load i32* %arrayidx3, align 4
-  %7 = load i32* %i, align 4
+  %5 = load i32*, i32** %B.addr, align 8
+  %arrayidx3 = getelementptr inbounds i32, i32* %5, i64 %idxprom2
+  %6 = load i32, i32* %arrayidx3, align 4
+  %7 = load i32, i32* %i, align 4
   %idxprom4 = sext i32 %7 to i64
-  %8 = load i32** %trigger.addr, align 8
-  %arrayidx5 = getelementptr inbounds i32* %8, i64 %idxprom4
-  %9 = load i32* %arrayidx5, align 4
+  %8 = load i32*, i32** %trigger.addr, align 8
+  %arrayidx5 = getelementptr inbounds i32, i32* %8, i64 %idxprom4
+  %9 = load i32, i32* %arrayidx5, align 4
   %add = add nsw i32 %6, %9
-  %10 = load i32* %i, align 4
+  %10 = load i32, i32* %i, align 4
   %idxprom6 = sext i32 %10 to i64
-  %11 = load i32** %A.addr, align 8
-  %arrayidx7 = getelementptr inbounds i32* %11, i64 %idxprom6
-  store i32 sdiv (i32 1, i32 zext (i1 icmp eq (i32** getelementptr inbounds ([1 x i32*]* @a, i64 0, i64 1), i32** @c) to i32)), i32* %arrayidx7, align 4
+  %11 = load i32*, i32** %A.addr, align 8
+  %arrayidx7 = getelementptr inbounds i32, i32* %11, i64 %idxprom6
+  store i32 sdiv (i32 1, i32 zext (i1 icmp eq (i32** getelementptr inbounds ([1 x i32*], [1 x i32*]* @a, i64 0, i64 1), i32** @c) to i32)), i32* %arrayidx7, align 4
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %for.body
   br label %for.inc
 
 for.inc:                                          ; preds = %if.end
-  %12 = load i32* %i, align 4
+  %12 = load i32, i32* %i, align 4
   %inc = add nsw i32 %12, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
@@ -459,30 +459,30 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp sge i32 %0, 0
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %idxprom = sext i32 %1 to i64
-  %2 = load i32** %trigger.addr, align 8
-  %arrayidx = getelementptr inbounds i32* %2, i64 %idxprom
-  %3 = load i32* %arrayidx, align 4
+  %2 = load i32*, i32** %trigger.addr, align 8
+  %arrayidx = getelementptr inbounds i32, i32* %2, i64 %idxprom
+  %3 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %3, 0
   br i1 %cmp1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %for.body
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %idxprom2 = sext i32 %4 to i64
-  %5 = load double** %in.addr, align 8
-  %arrayidx3 = getelementptr inbounds double* %5, i64 %idxprom2
-  %6 = load double* %arrayidx3, align 8
+  %5 = load double*, double** %in.addr, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %5, i64 %idxprom2
+  %6 = load double, double* %arrayidx3, align 8
   %add = fadd double %6, 5.000000e-01
-  %7 = load i32* %i, align 4
+  %7 = load i32, i32* %i, align 4
   %idxprom4 = sext i32 %7 to i64
-  %8 = load double** %out.addr, align 8
-  %arrayidx5 = getelementptr inbounds double* %8, i64 %idxprom4
+  %8 = load double*, double** %out.addr, align 8
+  %arrayidx5 = getelementptr inbounds double, double* %8, i64 %idxprom4
   store double %add, double* %arrayidx5, align 8
   br label %if.end
 
@@ -490,7 +490,7 @@ if.end:                                           ; preds = %if.then, %for.body
   br label %for.inc
 
 for.inc:                                          ; preds = %if.end
-  %9 = load i32* %i, align 4
+  %9 = load i32, i32* %i, align 4
   %dec = add nsw i32 %9, -1
   store i32 %dec, i32* %i, align 4
   br label %for.cond
diff --git a/test/Transforms/LoopVectorize/X86/metadata-enable.ll b/test/Transforms/LoopVectorize/X86/metadata-enable.ll
index 7feb66ce6a98..ba8e11e58749 100644
--- a/test/Transforms/LoopVectorize/X86/metadata-enable.ll
+++ b/test/Transforms/LoopVectorize/X86/metadata-enable.ll
@@ -54,17 +54,17 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %N
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
   store i32 %add, i32* %arrayidx2, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 32
   br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !0
 
 for.end:                                          ; preds = %for.body
-  %1 = load i32* %a, align 4
+  %1 = load i32, i32* %a, align 4
   ret i32 %1
 }
 
@@ -105,17 +105,17 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %N
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
   store i32 %add, i32* %arrayidx2, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 32
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:                                          ; preds = %for.body
-  %1 = load i32* %a, align 4
+  %1 = load i32, i32* %a, align 4
   ret i32 %1
 }
 
@@ -156,17 +156,17 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %N
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
   store i32 %add, i32* %arrayidx2, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 32
   br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !2
 
 for.end:                                          ; preds = %for.body
-  %1 = load i32* %a, align 4
+  %1 = load i32, i32* %a, align 4
   ret i32 %1
 }
 
diff --git a/test/Transforms/LoopVectorize/X86/min-trip-count-switch.ll b/test/Transforms/LoopVectorize/X86/min-trip-count-switch.ll
index fd69dc46070e..bb972c4488a4 100644
--- a/test/Transforms/LoopVectorize/X86/min-trip-count-switch.ll
+++ b/test/Transforms/LoopVectorize/X86/min-trip-count-switch.ll
@@ -10,8 +10,8 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds float* %a, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %add = fadd float %0, 1.000000e+00
   store float %add, float* %arrayidx, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/X86/no-vector.ll b/test/Transforms/LoopVectorize/X86/no-vector.ll
index 692eec989591..4b464b012675 100644
--- a/test/Transforms/LoopVectorize/X86/no-vector.ll
+++ b/test/Transforms/LoopVectorize/X86/no-vector.ll
@@ -8,8 +8,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %i.06 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
   %r.05 = phi i32 [ %xor, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i8* %s, i32 %i.06
-  %0 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %s, i32 %i.06
+  %0 = load i8, i8* %arrayidx, align 1
   %conv = sext i8 %0 to i32
   %xor = xor i32 %conv, %r.05
   %inc = add nsw i32 %i.06, 1
diff --git a/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll b/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll
index ad010443a5e0..631361c9d47d 100644
--- a/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll
+++ b/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll
@@ -17,28 +17,28 @@ entry:
   br label %for.body
 
 for.body:                                         ; preds = %for.body.for.body_crit_edge, %entry
-  %indvars.iv.reload = load i64* %indvars.iv.reg2mem
-  %arrayidx = getelementptr inbounds i32* %b, i64 %indvars.iv.reload
-  %0 = load i32* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv.reload
-  %1 = load i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3
+  %indvars.iv.reload = load i64, i64* %indvars.iv.reg2mem
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %indvars.iv.reload
+  %0 = load i32, i32* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv.reload
+  %1 = load i32, i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3
   %idxprom3 = sext i32 %1 to i64
-  %arrayidx4 = getelementptr inbounds i32* %a, i64 %idxprom3
+  %arrayidx4 = getelementptr inbounds i32, i32* %a, i64 %idxprom3
   store i32 %0, i32* %arrayidx4, align 4, !llvm.mem.parallel_loop_access !3
   %indvars.iv.next = add i64 %indvars.iv.reload, 1
   ; A new store without the parallel metadata here:
   store i64 %indvars.iv.next, i64* %indvars.iv.next.reg2mem
-  %indvars.iv.next.reload1 = load i64* %indvars.iv.next.reg2mem
-  %arrayidx6 = getelementptr inbounds i32* %b, i64 %indvars.iv.next.reload1
-  %2 = load i32* %arrayidx6, align 4, !llvm.mem.parallel_loop_access !3
+  %indvars.iv.next.reload1 = load i64, i64* %indvars.iv.next.reg2mem
+  %arrayidx6 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv.next.reload1
+  %2 = load i32, i32* %arrayidx6, align 4, !llvm.mem.parallel_loop_access !3
   store i32 %2, i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3
-  %indvars.iv.next.reload = load i64* %indvars.iv.next.reg2mem
+  %indvars.iv.next.reload = load i64, i64* %indvars.iv.next.reg2mem
   %lftr.wideiv = trunc i64 %indvars.iv.next.reload to i32
   %exitcond = icmp eq i32 %lftr.wideiv, 512
   br i1 %exitcond, label %for.end, label %for.body.for.body_crit_edge, !llvm.loop !3
 
 for.body.for.body_crit_edge:                      ; preds = %for.body
-  %indvars.iv.next.reload2 = load i64* %indvars.iv.next.reg2mem
+  %indvars.iv.next.reload2 = load i64, i64* %indvars.iv.next.reg2mem
   store i64 %indvars.iv.next.reload2, i64* %indvars.iv.reg2mem
   br label %for.body
 
diff --git a/test/Transforms/LoopVectorize/X86/parallel-loops.ll b/test/Transforms/LoopVectorize/X86/parallel-loops.ll
index 22ab52157498..53061edc35c5 100644
--- a/test/Transforms/LoopVectorize/X86/parallel-loops.ll
+++ b/test/Transforms/LoopVectorize/X86/parallel-loops.ll
@@ -20,16 +20,16 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %1 = load i32* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx2, align 4
   %idxprom3 = sext i32 %1 to i64
-  %arrayidx4 = getelementptr inbounds i32* %a, i64 %idxprom3
+  %arrayidx4 = getelementptr inbounds i32, i32* %a, i64 %idxprom3
   store i32 %0, i32* %arrayidx4, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
-  %arrayidx6 = getelementptr inbounds i32* %b, i64 %indvars.iv.next
-  %2 = load i32* %arrayidx6, align 4
+  %arrayidx6 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv.next
+  %2 = load i32, i32* %arrayidx6, align 4
   store i32 %2, i32* %arrayidx2, align 4
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
   %exitcond = icmp eq i32 %lftr.wideiv, 512
@@ -50,18 +50,18 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %1 = load i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3
   %idxprom3 = sext i32 %1 to i64
-  %arrayidx4 = getelementptr inbounds i32* %a, i64 %idxprom3
+  %arrayidx4 = getelementptr inbounds i32, i32* %a, i64 %idxprom3
   ; This store might have originated from inlining a function with a parallel
   ; loop. Refers to a list with the "original loop reference" (!4) also included.
   store i32 %0, i32* %arrayidx4, align 4, !llvm.mem.parallel_loop_access !5
   %indvars.iv.next = add i64 %indvars.iv, 1
-  %arrayidx6 = getelementptr inbounds i32* %b, i64 %indvars.iv.next
-  %2 = load i32* %arrayidx6, align 4, !llvm.mem.parallel_loop_access !3
+  %arrayidx6 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv.next
+  %2 = load i32, i32* %arrayidx6, align 4, !llvm.mem.parallel_loop_access !3
   store i32 %2, i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
   %exitcond = icmp eq i32 %lftr.wideiv, 512
@@ -83,18 +83,18 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4, !llvm.mem.parallel_loop_access !6
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %1 = load i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !6
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4, !llvm.mem.parallel_loop_access !6
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !6
   %idxprom3 = sext i32 %1 to i64
-  %arrayidx4 = getelementptr inbounds i32* %a, i64 %idxprom3
+  %arrayidx4 = getelementptr inbounds i32, i32* %a, i64 %idxprom3
   ; This refers to the loop marked with !7 which we are not in at the moment.
   ; It should prevent detecting as a parallel loop.
   store i32 %0, i32* %arrayidx4, align 4, !llvm.mem.parallel_loop_access !7
   %indvars.iv.next = add i64 %indvars.iv, 1
-  %arrayidx6 = getelementptr inbounds i32* %b, i64 %indvars.iv.next
-  %2 = load i32* %arrayidx6, align 4, !llvm.mem.parallel_loop_access !6
+  %arrayidx6 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv.next
+  %2 = load i32, i32* %arrayidx6, align 4, !llvm.mem.parallel_loop_access !6
   store i32 %2, i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !6
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
   %exitcond = icmp eq i32 %lftr.wideiv, 512
diff --git a/test/Transforms/LoopVectorize/X86/powof2div.ll b/test/Transforms/LoopVectorize/X86/powof2div.ll
index 054da8ed20ae..6bc738a7d143 100644
--- a/test/Transforms/LoopVectorize/X86/powof2div.ll
+++ b/test/Transforms/LoopVectorize/X86/powof2div.ll
@@ -7,7 +7,7 @@ target triple = "x86_64-unknown-linux-gnu"
 @Foo = common global %struct.anon zeroinitializer, align 4
 
 ;CHECK-LABEL: @foo(
-;CHECK: load <4 x i32>*
+;CHECK: load <4 x i32>, <4 x i32>*
 ;CHECK: sdiv <4 x i32>
 ;CHECK: store <4 x i32>
 
@@ -17,10 +17,10 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds %struct.anon* @Foo, i64 0, i32 2, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds %struct.anon, %struct.anon* @Foo, i64 0, i32 2, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %div = sdiv i32 %0, 2
-  %arrayidx2 = getelementptr inbounds %struct.anon* @Foo, i64 0, i32 0, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds %struct.anon, %struct.anon* @Foo, i64 0, i32 0, i64 %indvars.iv
   store i32 %div, i32* %arrayidx2, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 100
diff --git a/test/Transforms/LoopVectorize/X86/reduction-crash.ll b/test/Transforms/LoopVectorize/X86/reduction-crash.ll
index 3957a5541422..3741b95d9859 100644
--- a/test/Transforms/LoopVectorize/X86/reduction-crash.ll
+++ b/test/Transforms/LoopVectorize/X86/reduction-crash.ll
@@ -14,17 +14,17 @@ bb:
   br label %bb2
 
 bb2:                                              ; preds = %bb
-  %tmp = load double* null, align 8
+  %tmp = load double, double* null, align 8
   br i1 undef, label %bb3, label %bb12
 
 bb3:                                              ; preds = %bb3, %bb2
   %tmp4 = phi double [ %tmp9, %bb3 ], [ %tmp, %bb2 ]
   %tmp5 = phi i32 [ %tmp8, %bb3 ], [ 0, %bb2 ]
-  %tmp6 = getelementptr inbounds [16 x double]* undef, i32 0, i32 %tmp5
-  %tmp7 = load double* %tmp6, align 4
+  %tmp6 = getelementptr inbounds [16 x double], [16 x double]* undef, i32 0, i32 %tmp5
+  %tmp7 = load double, double* %tmp6, align 4
   %tmp8 = add nsw i32 %tmp5, 1
   %tmp9 = fadd fast double %tmp4, undef
-  %tmp10 = getelementptr inbounds float* %arg, i32 %tmp5
+  %tmp10 = getelementptr inbounds float, float* %arg, i32 %tmp5
   store float undef, float* %tmp10, align 4
   %tmp11 = icmp eq i32 %tmp8, %arg1
   br i1 %tmp11, label %bb12, label %bb3
diff --git a/test/Transforms/LoopVectorize/X86/small-size.ll b/test/Transforms/LoopVectorize/X86/small-size.ll
index 8c7a881be46f..47c262b11b46 100644
--- a/test/Transforms/LoopVectorize/X86/small-size.ll
+++ b/test/Transforms/LoopVectorize/X86/small-size.ll
@@ -30,12 +30,12 @@ define void @example1() optsize {
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %indvars.iv
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds [2048 x i32]* @c, i64 0, i64 %indvars.iv
-  %5 = load i32* %4, align 4
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds [2048 x i32], [2048 x i32]* @c, i64 0, i64 %indvars.iv
+  %5 = load i32, i32* %4, align 4
   %6 = add nsw i32 %5, %3
-  %7 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %7 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
   store i32 %6, i32* %7, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -65,7 +65,7 @@ define void @example2(i32 %n, i32 %x) optsize {
 
 .lr.ph5:                                          ; preds = %0, %.lr.ph5
   %indvars.iv6 = phi i64 [ %indvars.iv.next7, %.lr.ph5 ], [ 0, %0 ]
-  %3 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %indvars.iv6
+  %3 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %indvars.iv6
   store i32 %x, i32* %3, align 4
   %indvars.iv.next7 = add i64 %indvars.iv6, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next7 to i32
@@ -76,12 +76,12 @@ define void @example2(i32 %n, i32 %x) optsize {
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ %i.0.lcssa, %.preheader ]
   %.02 = phi i32 [ %4, %.lr.ph ], [ %n, %.preheader ]
   %4 = add nsw i32 %.02, -1
-  %5 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %indvars.iv
-  %6 = load i32* %5, align 4
-  %7 = getelementptr inbounds [2048 x i32]* @c, i64 0, i64 %indvars.iv
-  %8 = load i32* %7, align 4
+  %5 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %indvars.iv
+  %6 = load i32, i32* %5, align 4
+  %7 = getelementptr inbounds [2048 x i32], [2048 x i32]* @c, i64 0, i64 %indvars.iv
+  %8 = load i32, i32* %7, align 4
   %9 = and i32 %8, %6
-  %10 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %10 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
   store i32 %9, i32* %10, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %11 = icmp eq i32 %4, 0
@@ -104,9 +104,9 @@ define void @example3(i32 %n, i32* noalias nocapture %p, i32* noalias nocapture
   %.014 = phi i32* [ %5, %.lr.ph ], [ %p, %0 ]
   %.023 = phi i32* [ %3, %.lr.ph ], [ %q, %0 ]
   %2 = add nsw i32 %.05, -1
-  %3 = getelementptr inbounds i32* %.023, i64 1
-  %4 = load i32* %.023, align 16
-  %5 = getelementptr inbounds i32* %.014, i64 1
+  %3 = getelementptr inbounds i32, i32* %.023, i64 1
+  %4 = load i32, i32* %.023, align 16
+  %5 = getelementptr inbounds i32, i32* %.014, i64 1
   store i32 %4, i32* %.014, align 16
   %6 = icmp eq i32 %2, 0
   br i1 %6, label %._crit_edge, label %.lr.ph
@@ -128,9 +128,9 @@ define void @example4(i32 %n, i32* noalias nocapture %p, i32* noalias nocapture
   %.014 = phi i32* [ %5, %.lr.ph ], [ %p, %0 ]
   %.023 = phi i32* [ %3, %.lr.ph ], [ %q, %0 ]
   %2 = add nsw i32 %.05, -1
-  %3 = getelementptr inbounds i32* %.023, i64 1
-  %4 = load i32* %.023, align 16
-  %5 = getelementptr inbounds i32* %.014, i64 1
+  %3 = getelementptr inbounds i32, i32* %.023, i64 1
+  %4 = load i32, i32* %.023, align 16
+  %5 = getelementptr inbounds i32, i32* %.014, i64 1
   store i32 %4, i32* %.014, align 16
   %6 = icmp eq i32 %2, 0
   br i1 %6, label %._crit_edge, label %.lr.ph
@@ -152,11 +152,11 @@ define void @example23(i16* nocapture %src, i32* nocapture %dst) optsize {
   %.04 = phi i16* [ %src, %0 ], [ %2, %1 ]
   %.013 = phi i32* [ %dst, %0 ], [ %6, %1 ]
   %i.02 = phi i32 [ 0, %0 ], [ %7, %1 ]
-  %2 = getelementptr inbounds i16* %.04, i64 1
-  %3 = load i16* %.04, align 2
+  %2 = getelementptr inbounds i16, i16* %.04, i64 1
+  %3 = load i16, i16* %.04, align 2
   %4 = zext i16 %3 to i32
   %5 = shl nuw nsw i32 %4, 7
-  %6 = getelementptr inbounds i32* %.013, i64 1
+  %6 = getelementptr inbounds i32, i32* %.013, i64 1
   store i32 %5, i32* %.013, align 4
   %7 = add nsw i32 %i.02, 1
   %exitcond = icmp eq i32 %7, 256
@@ -178,11 +178,11 @@ define void @example23b(i16* noalias nocapture %src, i32* noalias nocapture %dst
   %.04 = phi i16* [ %src, %0 ], [ %2, %1 ]
   %.013 = phi i32* [ %dst, %0 ], [ %6, %1 ]
   %i.02 = phi i32 [ 0, %0 ], [ %7, %1 ]
-  %2 = getelementptr inbounds i16* %.04, i64 1
-  %3 = load i16* %.04, align 2
+  %2 = getelementptr inbounds i16, i16* %.04, i64 1
+  %3 = load i16, i16* %.04, align 2
   %4 = zext i16 %3 to i32
   %5 = shl nuw nsw i32 %4, 7
-  %6 = getelementptr inbounds i32* %.013, i64 1
+  %6 = getelementptr inbounds i32, i32* %.013, i64 1
   store i32 %5, i32* %.013, align 4
   %7 = add nsw i32 %i.02, 1
   %exitcond = icmp eq i32 %7, 256
diff --git a/test/Transforms/LoopVectorize/X86/struct-store.ll b/test/Transforms/LoopVectorize/X86/struct-store.ll
index a995e43a5ab1..4ff3b0e4c05d 100644
--- a/test/Transforms/LoopVectorize/X86/struct-store.ll
+++ b/test/Transforms/LoopVectorize/X86/struct-store.ll
@@ -15,7 +15,7 @@ entry:
 
 loop:
   %indvars.iv = phi i64 [ %indvars.iv.next, %loop ], [ 0, %entry ]
-  %tmp = getelementptr inbounds [16 x { i64, i64 }]* @glbl, i64 0, i64 %indvars.iv
+  %tmp = getelementptr inbounds [16 x { i64, i64 }], [16 x { i64, i64 }]* @glbl, i64 0, i64 %indvars.iv
   store { i64, i64 } { i64 ptrtoint (void ()* @fn to i64), i64 0 }, { i64, i64 }* %tmp, align 16
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/X86/tripcount.ll b/test/Transforms/LoopVectorize/X86/tripcount.ll
index a4ec6948a2f0..c0bbb92c2c53 100644
--- a/test/Transforms/LoopVectorize/X86/tripcount.ll
+++ b/test/Transforms/LoopVectorize/X86/tripcount.ll
@@ -22,8 +22,8 @@ for.body.preheader:
 
 for.body:
   %i.07 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
-  %arrayidx = getelementptr inbounds [0 x i32]* @big, i32 0, i32 %i.07
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @big, i32 0, i32 %i.07
+  %0 = load i32, i32* %arrayidx, align 4
   %neg = xor i32 %0, -1
   store i32 %neg, i32* %arrayidx, align 4
   %inc = add nsw i32 %i.07, 1
diff --git a/test/Transforms/LoopVectorize/X86/uint64_to_fp64-cost-model.ll b/test/Transforms/LoopVectorize/X86/uint64_to_fp64-cost-model.ll
index 86c32b2d2ee4..38af11c443d0 100644
--- a/test/Transforms/LoopVectorize/X86/uint64_to_fp64-cost-model.ll
+++ b/test/Transforms/LoopVectorize/X86/uint64_to_fp64-cost-model.ll
@@ -12,10 +12,10 @@ entry:
   br label %for.body
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i64* %a, i64 %indvars.iv
-  %tmp = load i64* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i64, i64* %a, i64 %indvars.iv
+  %tmp = load i64, i64* %arrayidx, align 4
   %conv = uitofp i64 %tmp to double
-  %arrayidx2 = getelementptr inbounds double* %b, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %b, i64 %indvars.iv
   store double %conv, double* %arrayidx2, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 256
diff --git a/test/Transforms/LoopVectorize/X86/unroll-pm.ll b/test/Transforms/LoopVectorize/X86/unroll-pm.ll
index 5064fec286ce..52914b6a7c67 100644
--- a/test/Transforms/LoopVectorize/X86/unroll-pm.ll
+++ b/test/Transforms/LoopVectorize/X86/unroll-pm.ll
@@ -17,8 +17,8 @@ define i32 @bar(i32* nocapture %A, i32 %n) nounwind uwtable ssp {
 
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %3 = load i32* %2, align 4
+  %2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
   %4 = add nsw i32 %3, 6
   store i32 %4, i32* %2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll b/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll
index 716dc08a55ac..69d2a319a8ca 100644
--- a/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll
+++ b/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll
@@ -16,8 +16,8 @@ target triple = "x86_64-apple-macosx10.8.0"
 ; CHECK-VECTOR: ret
 ;
 ; CHECK-SCALAR-LABEL: @foo(
-; CHECK-SCALAR: load i32*
-; CHECK-SCALAR-NOT: load i32*
+; CHECK-SCALAR: load i32, i32*
+; CHECK-SCALAR-NOT: load i32, i32*
 ; CHECK-SCALAR: store i32
 ; CHECK-SCALAR-NOT: store i32
 ; CHECK-SCALAR: ret
@@ -26,8 +26,8 @@ define i32 @foo(i32* nocapture %A) nounwind uwtable ssp {
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %3 = load i32* %2, align 4
+  %2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
   %4 = add nsw i32 %3, 6
   store i32 %4, i32* %2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -47,9 +47,11 @@ define i32 @foo(i32* nocapture %A) nounwind uwtable ssp {
 ; CHECK-VECTOR: store <4 x i32>
 ; CHECK-VECTOR: ret
 ;
+; For x86, loop unroll in loop vectorizer is disabled when VF==1.
+;
 ; CHECK-SCALAR-LABEL: @bar(
 ; CHECK-SCALAR: store i32
-; CHECK-SCALAR: store i32
+; CHECK-SCALAR-NOT: store i32
 ; CHECK-SCALAR: ret
 define i32 @bar(i32* nocapture %A, i32 %n) nounwind uwtable ssp {
   %1 = icmp sgt i32 %n, 0
@@ -57,8 +59,8 @@ define i32 @bar(i32* nocapture %A, i32 %n) nounwind uwtable ssp {
 
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %3 = load i32* %2, align 4
+  %2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
   %4 = add nsw i32 %3, 6
   store i32 %4, i32* %2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -86,10 +88,10 @@ entry:
 
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds float* %B, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %B, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %mul = fmul float %0, %N
-  %arrayidx2 = getelementptr inbounds float* %A, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %A, i64 %indvars.iv
   store float %mul, float* %arrayidx2, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 256
diff --git a/test/Transforms/LoopVectorize/X86/unroll_selection.ll b/test/Transforms/LoopVectorize/X86/unroll_selection.ll
index c684b4e79b14..71b829071e22 100644
--- a/test/Transforms/LoopVectorize/X86/unroll_selection.ll
+++ b/test/Transforms/LoopVectorize/X86/unroll_selection.ll
@@ -16,8 +16,8 @@ define void @reg_pressure(double* nocapture %A, i32 %n) nounwind uwtable ssp {
 
 ; <label>:2                                       ; preds = %2, %0
   %indvars.iv = phi i64 [ %indvars.iv.next, %2 ], [ %1, %0 ]
-  %3 = getelementptr inbounds double* %A, i64 %indvars.iv
-  %4 = load double* %3, align 8
+  %3 = getelementptr inbounds double, double* %A, i64 %indvars.iv
+  %4 = load double, double* %3, align 8
   %5 = fadd double %4, 3.000000e+00
   %6 = fmul double %4, 2.000000e+00
   %7 = fadd double %5, %6
@@ -58,8 +58,8 @@ define void @small_loop(i16* nocapture %A, i64 %n) nounwind uwtable ssp {
 
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %i.01 = phi i64 [ %5, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds i16* %A, i64 %i.01
-  %3 = load i16* %2, align 2
+  %2 = getelementptr inbounds i16, i16* %A, i64 %i.01
+  %3 = load i16, i16* %2, align 2
   %4 = xor i16 %3, 3
   store i16 %4, i16* %2, align 2
   %5 = add i64 %i.01, 1
diff --git a/test/Transforms/LoopVectorize/X86/veclib-calls.ll b/test/Transforms/LoopVectorize/X86/veclib-calls.ll
new file mode 100644
index 000000000000..6f8f5223ce45
--- /dev/null
+++ b/test/Transforms/LoopVectorize/X86/veclib-calls.ll
@@ -0,0 +1,632 @@
+; RUN: opt < %s -vector-library=Accelerate -loop-vectorize -S | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+;CHECK-LABEL: @sqrt_f32(
+;CHECK: vsqrtf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @sqrtf(float) nounwind readnone
+define void @sqrt_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @sqrtf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @exp_f32(
+;CHECK: vexpf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @expf(float) nounwind readnone
+define void @exp_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @expf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @log_f32(
+;CHECK: vlogf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @logf(float) nounwind readnone
+define void @log_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @logf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+; For abs instruction we'll generate vector intrinsic, as it's cheaper than a lib call.
+;CHECK-LABEL: @fabs_f32(
+;CHECK: fabs{{.*}}<4 x float>
+;CHECK: ret void
+declare float @fabsf(float) nounwind readnone
+define void @fabs_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @fabsf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+; Test that we can vectorize an intrinsic into a vector call.
+;CHECK-LABEL: @exp_f32_intrin(
+;CHECK: vexpf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @llvm.exp.f32(float) nounwind readnone
+define void @exp_f32_intrin(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @llvm.exp.f32(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+; Test that we don't vectorize arbitrary functions.
+;CHECK-LABEL: @foo_f32(
+;CHECK-NOT: foo{{.*}}<4 x float>
+;CHECK: ret void
+declare float @foo(float) nounwind readnone
+define void @foo_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @foo(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+; Test that we don't vectorize calls with nobuiltin attribute.
+;CHECK-LABEL: @sqrt_f32_nobuiltin(
+;CHECK-NOT: vsqrtf{{.*}}<4 x float>
+;CHECK: ret void
+define void @sqrt_f32_nobuiltin(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @sqrtf(float %0) nounwind readnone nobuiltin
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @ceil_f32(
+;CHECK: vceilf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @ceilf(float) nounwind readnone
+define void @ceil_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @ceilf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @floor_f32(
+;CHECK: vfloorf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @floorf(float) nounwind readnone
+define void @floor_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @floorf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @expm1_f32(
+;CHECK: vexpm1f{{.*}}<4 x float>
+;CHECK: ret void
+declare float @expm1f(float) nounwind readnone
+define void @expm1_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @expm1f(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @log1p_f32(
+;CHECK: vlog1pf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @log1pf(float) nounwind readnone
+define void @log1p_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @log1pf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @log10_f32(
+;CHECK: vlog10f{{.*}}<4 x float>
+;CHECK: ret void
+declare float @log10f(float) nounwind readnone
+define void @log10_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @log10f(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @logb_f32(
+;CHECK: vlogbf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @logbf(float) nounwind readnone
+define void @logb_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @logbf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @sin_f32(
+;CHECK: vsinf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @sinf(float) nounwind readnone
+define void @sin_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @sinf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @cos_f32(
+;CHECK: vcosf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @cosf(float) nounwind readnone
+define void @cos_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @cosf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @tan_f32(
+;CHECK: vtanf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @tanf(float) nounwind readnone
+define void @tan_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @tanf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @asin_f32(
+;CHECK: vasinf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @asinf(float) nounwind readnone
+define void @asin_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @asinf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @acos_f32(
+;CHECK: vacosf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @acosf(float) nounwind readnone
+define void @acos_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @acosf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @atan_f32(
+;CHECK: vatanf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @atanf(float) nounwind readnone
+define void @atan_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @atanf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @sinh_f32(
+;CHECK: vsinhf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @sinhf(float) nounwind readnone
+define void @sinh_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @sinhf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @cosh_f32(
+;CHECK: vcoshf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @coshf(float) nounwind readnone
+define void @cosh_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @coshf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @tanh_f32(
+;CHECK: vtanhf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @tanhf(float) nounwind readnone
+define void @tanh_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @tanhf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @asinh_f32(
+;CHECK: vasinhf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @asinhf(float) nounwind readnone
+define void @asinh_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @asinhf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @acosh_f32(
+;CHECK: vacoshf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @acoshf(float) nounwind readnone
+define void @acosh_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @acoshf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+;CHECK-LABEL: @atanh_f32(
+;CHECK: vatanhf{{.*}}<4 x float>
+;CHECK: ret void
+declare float @atanhf(float) nounwind readnone
+define void @atanh_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %call = tail call float @atanhf(float %0) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  store float %call, float* %arrayidx2, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
diff --git a/test/Transforms/LoopVectorize/X86/vect.omp.force.ll b/test/Transforms/LoopVectorize/X86/vect.omp.force.ll
index a781fbedb404..c2a0fed1fe6f 100644
--- a/test/Transforms/LoopVectorize/X86/vect.omp.force.ll
+++ b/test/Transforms/LoopVectorize/X86/vect.omp.force.ll
@@ -15,9 +15,9 @@ target triple = "x86_64-apple-macosx10.8.0"
 ; The source code for the test:
 ;
 ; #include <math.h>
-; void foo(float* restrict A, float * restrict B, int size)
+; void foo(float* restrict A, float * restrict B)
 ; {
-;   for (int i = 0; i < size; ++i) A[i] = sinf(B[i]);
+;   for (int i = 0; i < 1000; i+=2) A[i] = sinf(B[i]);
 ; }
 ;
 
@@ -25,24 +25,20 @@ target triple = "x86_64-apple-macosx10.8.0"
 ; This loop will be vectorized, although the scalar cost is lower than any of vector costs, but vectorization is explicitly forced in metadata.
 ;
 
-define void @vectorized(float* noalias nocapture %A, float* noalias nocapture %B, i32 %size) {
+define void @vectorized(float* noalias nocapture %A, float* noalias nocapture %B) {
 entry:
-  %cmp6 = icmp sgt i32 %size, 0
-  br i1 %cmp6, label %for.body.preheader, label %for.end
-
-for.body.preheader:
   br label %for.body
 
 for.body:
-  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
-  %arrayidx = getelementptr inbounds float* %B, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !1
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %B, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !1
   %call = tail call float @llvm.sin.f32(float %0)
-  %arrayidx2 = getelementptr inbounds float* %A, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %A, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !1
-  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 2
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
-  %exitcond = icmp eq i32 %lftr.wideiv, %size
+  %exitcond = icmp eq i32 %lftr.wideiv, 1000
   br i1 %exitcond, label %for.end.loopexit, label %for.body, !llvm.loop !1
 
 for.end.loopexit:
@@ -59,24 +55,20 @@ for.end:
 ; This method will not be vectorized, as scalar cost is lower than any of vector costs.
 ;
 
-define void @not_vectorized(float* noalias nocapture %A, float* noalias nocapture %B, i32 %size) {
+define void @not_vectorized(float* noalias nocapture %A, float* noalias nocapture %B) {
 entry:
-  %cmp6 = icmp sgt i32 %size, 0
-  br i1 %cmp6, label %for.body.preheader, label %for.end
-
-for.body.preheader:
   br label %for.body
 
 for.body:
-  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
-  %arrayidx = getelementptr inbounds float* %B, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %B, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3
   %call = tail call float @llvm.sin.f32(float %0)
-  %arrayidx2 = getelementptr inbounds float* %A, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %A, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3
-  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 2
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
-  %exitcond = icmp eq i32 %lftr.wideiv, %size
+  %exitcond = icmp eq i32 %lftr.wideiv, 1000
   br i1 %exitcond, label %for.end.loopexit, label %for.body, !llvm.loop !3
 
 for.end.loopexit:
diff --git a/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll b/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
index e39e6b57dd96..8d139ac7e5af 100644
--- a/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
+++ b/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
@@ -29,10 +29,10 @@ entry:
 
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds float* %B, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !1
-  %arrayidx2 = getelementptr inbounds float* %A, i64 %indvars.iv
-  %1 = load float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !1
+  %arrayidx = getelementptr inbounds float, float* %B, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !1
+  %arrayidx2 = getelementptr inbounds float, float* %A, i64 %indvars.iv
+  %1 = load float, float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !1
   %add = fadd fast float %0, %1
   store float %add, float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !1
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
@@ -55,10 +55,10 @@ entry:
 
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds float* %B, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3
-  %arrayidx2 = getelementptr inbounds float* %A, i64 %indvars.iv
-  %1 = load float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3
+  %arrayidx = getelementptr inbounds float, float* %B, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3
+  %arrayidx2 = getelementptr inbounds float, float* %A, i64 %indvars.iv
+  %1 = load float, float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3
   %add = fadd fast float %0, %1
   store float %add, float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/X86/vector-scalar-select-cost.ll b/test/Transforms/LoopVectorize/X86/vector-scalar-select-cost.ll
index 3b3a7875ab36..5efabe16d32b 100644
--- a/test/Transforms/LoopVectorize/X86/vector-scalar-select-cost.ll
+++ b/test/Transforms/LoopVectorize/X86/vector-scalar-select-cost.ll
@@ -15,12 +15,12 @@ define void @scalarselect(i1 %cond) {
 
 ; <label>:1
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %indvars.iv
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds [2048 x i32]* @c, i64 0, i64 %indvars.iv
-  %5 = load i32* %4, align 4
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds [2048 x i32], [2048 x i32]* @c, i64 0, i64 %indvars.iv
+  %5 = load i32, i32* %4, align 4
   %6 = add nsw i32 %5, %3
-  %7 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %7 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
 
 ; A scalar select has a cost of 1 on core2
 ; CHECK: cost of 1 for VF 2 {{.*}}  select i1 %cond, i32 %6, i32 0
@@ -42,16 +42,16 @@ define void @vectorselect(i1 %cond) {
 
 ; <label>:1
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %indvars.iv
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds [2048 x i32]* @c, i64 0, i64 %indvars.iv
-  %5 = load i32* %4, align 4
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds [2048 x i32], [2048 x i32]* @c, i64 0, i64 %indvars.iv
+  %5 = load i32, i32* %4, align 4
   %6 = add nsw i32 %5, %3
-  %7 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %7 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
   %8 = icmp ult i64 %indvars.iv, 8
 
-; A vector select has a cost of 4 on core2
-; CHECK: cost of 4 for VF 2 {{.*}}  select i1 %8, i32 %6, i32 0
+; A vector select has a cost of 1 on core2
+; CHECK: cost of 1 for VF 2 {{.*}}  select i1 %8, i32 %6, i32 0
 
   %sel = select i1 %8, i32 %6, i32 zeroinitializer
   store i32 %sel, i32* %7, align 4
diff --git a/test/Transforms/LoopVectorize/X86/vector_ptr_load_store.ll b/test/Transforms/LoopVectorize/X86/vector_ptr_load_store.ll
index e57cfefec07c..6cd3c9c3bc01 100644
--- a/test/Transforms/LoopVectorize/X86/vector_ptr_load_store.ll
+++ b/test/Transforms/LoopVectorize/X86/vector_ptr_load_store.ll
@@ -19,7 +19,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 ; CHECK: test_consecutive_store
 ; CHECK: The Widest type: 64 bits
 define void @test_consecutive_store(%0**, %0**, %0** nocapture) nounwind ssp uwtable align 2 {
-  %4 = load %0** %2, align 8
+  %4 = load %0*, %0** %2, align 8
   %5 = icmp eq %0** %0, %1
   br i1 %5, label %12, label %6
 
@@ -29,7 +29,7 @@ define void @test_consecutive_store(%0**, %0**, %0** nocapture) nounwind ssp uwt
 ; <label>:7                                       ; preds = %7, %6
   %8 = phi %0** [ %0, %6 ], [ %9, %7 ]
   store %0* %4, %0** %8, align 8
-  %9 = getelementptr inbounds %0** %8, i64 1
+  %9 = getelementptr inbounds %0*, %0** %8, i64 1
   %10 = icmp eq %0** %9, %1
   br i1 %10, label %11, label %7
 
@@ -61,12 +61,12 @@ define void @test_nonconsecutive_store() nounwind ssp uwtable {
 
 ; <label>:3                                       ; preds = %3, %1
   %4 = phi i64 [ 0, %1 ], [ %11, %3 ]
-  %5 = getelementptr inbounds [2048 x i16]* @q, i64 0, i64 %4
-  %6 = load i16* %5, align 2
+  %5 = getelementptr inbounds [2048 x i16], [2048 x i16]* @q, i64 0, i64 %4
+  %6 = load i16, i16* %5, align 2
   %7 = sext i16 %6 to i64
   %8 = add i64 %7, 1
   %9 = inttoptr i64 %8 to i32*
-  %10 = getelementptr inbounds [2048 x [8 x i32*]]* @p, i64 0, i64 %4, i64 %2
+  %10 = getelementptr inbounds [2048 x [8 x i32*]], [2048 x [8 x i32*]]* @p, i64 0, i64 %4, i64 %2
   store i32* %9, i32** %10, align 8
   %11 = add i64 %4, 1
   %12 = trunc i64 %11 to i32
@@ -100,8 +100,8 @@ define i8 @test_consecutive_ptr_load() nounwind readonly ssp uwtable {
 ; <label>:1                                       ; preds = %1, %0
   %2 = phi i64 [ 0, %0 ], [ %10, %1 ]
   %3 = phi i8 [ 0, %0 ], [ %9, %1 ]
-  %4 = getelementptr inbounds [1024 x i32*]* @ia, i32 0, i64 %2
-  %5 = load i32** %4, align 4
+  %4 = getelementptr inbounds [1024 x i32*], [1024 x i32*]* @ia, i32 0, i64 %2
+  %5 = load i32*, i32** %4, align 4
   %6 = ptrtoint i32* %5 to i64
   %7 = trunc i64 %6 to i8
   %8 = add i8 %3, 1
@@ -127,9 +127,9 @@ define void @test_nonconsecutive_ptr_load() nounwind ssp uwtable {
 
 ; <label>:3                                       ; preds = %3, %1
   %4 = phi i64 [ 0, %1 ], [ %10, %3 ]
-  %5 = getelementptr inbounds [2048 x [8 x i32*]]* @p2, i64 0, i64 %4, i64 %2
-  %6 = getelementptr inbounds [2048 x i16]* @q2, i64 0, i64 %4
-  %7 = load i32** %5, align 2
+  %5 = getelementptr inbounds [2048 x [8 x i32*]], [2048 x [8 x i32*]]* @p2, i64 0, i64 %4, i64 %2
+  %6 = getelementptr inbounds [2048 x i16], [2048 x i16]* @q2, i64 0, i64 %4
+  %7 = load i32*, i32** %5, align 2
   %8 = ptrtoint i32* %7 to i64
   %9 = trunc i64 %8 to i16
   store i16 %9, i16* %6, align 8
diff --git a/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll b/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
index 011ce8eac556..65cabb05f2fb 100644
--- a/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
+++ b/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
@@ -52,7 +52,7 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv, !dbg !16
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv, !dbg !16
   %0 = trunc i64 %indvars.iv to i32, !dbg !16
   store i32 %0, i32* %arrayidx, align 4, !dbg !16, !tbaa !18
   %cmp3 = icmp sle i32 %0, %Length, !dbg !22
@@ -74,7 +74,7 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv, !dbg !30
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv, !dbg !30
   %0 = trunc i64 %indvars.iv to i32, !dbg !30
   store i32 %0, i32* %arrayidx, align 4, !dbg !30, !tbaa !18
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1, !dbg !25
@@ -97,12 +97,12 @@ for.body.preheader:                               ; preds = %entry
 
 for.body:                                         ; preds = %for.body.preheader, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
-  %arrayidx = getelementptr inbounds i32* %B, i64 %indvars.iv, !dbg !35
-  %0 = load i32* %arrayidx, align 4, !dbg !35, !tbaa !18
+  %arrayidx = getelementptr inbounds i32, i32* %B, i64 %indvars.iv, !dbg !35
+  %0 = load i32, i32* %arrayidx, align 4, !dbg !35, !tbaa !18
   %idxprom1 = sext i32 %0 to i64, !dbg !35
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %idxprom1, !dbg !35
-  %1 = load i32* %arrayidx2, align 4, !dbg !35, !tbaa !18
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 %indvars.iv, !dbg !35
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %idxprom1, !dbg !35
+  %1 = load i32, i32* %arrayidx2, align 4, !dbg !35, !tbaa !18
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv, !dbg !35
   store i32 %1, i32* %arrayidx4, align 4, !dbg !35, !tbaa !18
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1, !dbg !32
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32, !dbg !32
@@ -122,40 +122,40 @@ attributes #0 = { nounwind }
 !llvm.module.flags = !{!9, !10}
 !llvm.ident = !{!11}
 
-!0 = !{!"0x11\004\00clang version 3.5.0\001\00\006\00\002", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [./source.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"source.cpp", !"."}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0", isOptimized: true, runtimeVersion: 6, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "source.cpp", directory: ".")
 !2 = !{}
 !3 = !{!4, !7, !8}
-!4 = !{!"0x2e\00test\00test\00\001\000\001\000\006\00256\001\001", !1, !5, !6, null, void (i32*, i32)* @_Z4testPii, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [test]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [./source.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!7 = !{!"0x2e\00test_disabled\00test_disabled\00\0010\000\001\000\006\00256\001\0010", !1, !5, !6, null, void (i32*, i32)* @_Z13test_disabledPii, null, null, !2} ; [ DW_TAG_subprogram ] [line 10] [def] [test_disabled]
-!8 = !{!"0x2e\00test_array_bounds\00test_array_bounds\00\0016\000\001\000\006\00256\001\0016", !1, !5, !6, null, void (i32*, i32*, i32)* @_Z17test_array_boundsPiS_i, null, null, !2} ; [ DW_TAG_subprogram ] [line 16] [def] [test_array_bounds]
+!4 = !DISubprogram(name: "test", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !1, scope: !5, type: !6, function: void (i32*, i32)* @_Z4testPii, variables: !2)
+!5 = !DIFile(filename: "source.cpp", directory: ".")
+!6 = !DISubroutineType(types: !2)
+!7 = !DISubprogram(name: "test_disabled", line: 10, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 10, file: !1, scope: !5, type: !6, function: void (i32*, i32)* @_Z13test_disabledPii, variables: !2)
+!8 = !DISubprogram(name: "test_array_bounds", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 16, file: !1, scope: !5, type: !6, function: void (i32*, i32*, i32)* @_Z17test_array_boundsPiS_i, variables: !2)
 !9 = !{i32 2, !"Dwarf Version", i32 2}
-!10 = !{i32 2, !"Debug Info Version", i32 2}
+!10 = !{i32 2, !"Debug Info Version", i32 3}
 !11 = !{!"clang version 3.5.0"}
-!12 = !MDLocation(line: 3, column: 8, scope: !13)
-!13 = !{!"0xb\003\003\000", !1, !4} ; [ DW_TAG_lexical_block ]
+!12 = !DILocation(line: 3, column: 8, scope: !13)
+!13 = distinct !DILexicalBlock(line: 3, column: 3, file: !1, scope: !4)
 !14 = !{!14, !15, !15}
 !15 = !{!"llvm.loop.vectorize.enable", i1 true}
-!16 = !MDLocation(line: 4, column: 5, scope: !17)
-!17 = !{!"0xb\003\0036\000", !1, !13} ; [ DW_TAG_lexical_block ]
+!16 = !DILocation(line: 4, column: 5, scope: !17)
+!17 = distinct !DILexicalBlock(line: 3, column: 36, file: !1, scope: !13)
 !18 = !{!19, !19, i64 0}
 !19 = !{!"int", !20, i64 0}
 !20 = !{!"omnipotent char", !21, i64 0}
 !21 = !{!"Simple C/C++ TBAA"}
-!22 = !MDLocation(line: 5, column: 9, scope: !23)
-!23 = !{!"0xb\005\009\000", !1, !17} ; [ DW_TAG_lexical_block ]
-!24 = !MDLocation(line: 8, column: 1, scope: !4)
-!25 = !MDLocation(line: 12, column: 8, scope: !26)
-!26 = !{!"0xb\0012\003\000", !1, !7} ; [ DW_TAG_lexical_block ]
+!22 = !DILocation(line: 5, column: 9, scope: !23)
+!23 = distinct !DILexicalBlock(line: 5, column: 9, file: !1, scope: !17)
+!24 = !DILocation(line: 8, column: 1, scope: !4)
+!25 = !DILocation(line: 12, column: 8, scope: !26)
+!26 = distinct !DILexicalBlock(line: 12, column: 3, file: !1, scope: !7)
 !27 = !{!27, !28, !29}
 !28 = !{!"llvm.loop.interleave.count", i32 1}
 !29 = !{!"llvm.loop.vectorize.width", i32 1}
-!30 = !MDLocation(line: 13, column: 5, scope: !26)
-!31 = !MDLocation(line: 14, column: 1, scope: !7)
-!32 = !MDLocation(line: 18, column: 8, scope: !33)
-!33 = !{!"0xb\0018\003\000", !1, !8} ; [ DW_TAG_lexical_block ]
+!30 = !DILocation(line: 13, column: 5, scope: !26)
+!31 = !DILocation(line: 14, column: 1, scope: !7)
+!32 = !DILocation(line: 18, column: 8, scope: !33)
+!33 = distinct !DILexicalBlock(line: 18, column: 3, file: !1, scope: !8)
 !34 = !{!34, !15}
-!35 = !MDLocation(line: 19, column: 5, scope: !33)
-!36 = !MDLocation(line: 20, column: 1, scope: !8)
+!35 = !DILocation(line: 19, column: 5, scope: !33)
+!36 = !DILocation(line: 20, column: 1, scope: !8)
diff --git a/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll b/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll
index 16fe370464b0..1c21748d8bdd 100644
--- a/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll
+++ b/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll
@@ -5,7 +5,7 @@
 ; This code has all the !dbg annotations needed to track source line information,
 ; but is missing the llvm.dbg.cu annotation. This prevents code generation from
 ; emitting debug info in the final output.
-; RUN: llc -mtriple x86_64-pc-linux-gnu %s -o - | FileCheck -check-prefix=DEBUG-OUTPUT %s
+; RUN: llc < %s -mtriple x86_64-pc-linux-gnu -o - | FileCheck -check-prefix=DEBUG-OUTPUT %s
 ; DEBUG-OUTPUT-NOT: .loc
 ; DEBUG-OUTPUT-NOT: {{.*}}.debug_info
 
@@ -26,11 +26,11 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %add8 = phi i32 [ 0, %entry ], [ %add, %for.body ], !dbg !19
-  %arrayidx = getelementptr inbounds [16 x i8]* %cb, i64 0, i64 %indvars.iv, !dbg !19
-  %0 = load i8* %arrayidx, align 1, !dbg !19, !tbaa !21
+  %arrayidx = getelementptr inbounds [16 x i8], [16 x i8]* %cb, i64 0, i64 %indvars.iv, !dbg !19
+  %0 = load i8, i8* %arrayidx, align 1, !dbg !19, !tbaa !21
   %conv = sext i8 %0 to i32, !dbg !19
-  %arrayidx2 = getelementptr inbounds [16 x i8]* %cc, i64 0, i64 %indvars.iv, !dbg !19
-  %1 = load i8* %arrayidx2, align 1, !dbg !19, !tbaa !21
+  %arrayidx2 = getelementptr inbounds [16 x i8], [16 x i8]* %cc, i64 0, i64 %indvars.iv, !dbg !19
+  %1 = load i8, i8* %arrayidx2, align 1, !dbg !19, !tbaa !21
   %conv3 = sext i8 %1 to i32, !dbg !19
   %sub = sub i32 %conv, %conv3, !dbg !19
   %add = add nsw i32 %sub, %add8, !dbg !19
@@ -49,26 +49,26 @@ declare void @ibar(i32*) #1
 !llvm.module.flags = !{!7, !8}
 !llvm.ident = !{!9}
 
-!1 = !{!"vectorization-remarks.c", !"."}
+!1 = !DIFile(filename: "vectorization-remarks.c", directory: ".")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\005\000\001\000\006\00256\001\006", !1, !5, !6, null, i32 (i32)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [scope 6] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [./vectorization-remarks.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 6, file: !1, scope: !5, type: !6, function: i32 (i32)* @foo, variables: !2)
+!5 = !DIFile(filename: "vectorization-remarks.c", directory: ".")
+!6 = !DISubroutineType(types: !2)
 !7 = !{i32 2, !"Dwarf Version", i32 4}
-!8 = !{i32 1, !"Debug Info Version", i32 2}
+!8 = !{i32 1, !"Debug Info Version", i32 3}
 !9 = !{!"clang version 3.5.0 "}
-!10 = !MDLocation(line: 8, column: 3, scope: !4)
+!10 = !DILocation(line: 8, column: 3, scope: !4)
 !11 = !{!12, !12, i64 0}
 !12 = !{!"int", !13, i64 0}
 !13 = !{!"omnipotent char", !14, i64 0}
 !14 = !{!"Simple C/C++ TBAA"}
-!15 = !MDLocation(line: 17, column: 8, scope: !16)
-!16 = !{!"0xb\0017\008\002", !1, !17} ; [ DW_TAG_lexical_block ] [./vectorization-remarks.c]
-!17 = !{!"0xb\0017\008\001", !1, !18} ; [ DW_TAG_lexical_block ] [./vectorization-remarks.c]
-!18 = !{!"0xb\0017\003\000", !1, !4} ; [ DW_TAG_lexical_block ] [./vectorization-remarks.c]
-!19 = !MDLocation(line: 18, column: 5, scope: !20)
-!20 = !{!"0xb\0017\0027\000", !1, !18} ; [ DW_TAG_lexical_block ] [./vectorization-remarks.c]
+!15 = !DILocation(line: 17, column: 8, scope: !16)
+!16 = distinct !DILexicalBlock(line: 17, column: 8, file: !1, scope: !17)
+!17 = distinct !DILexicalBlock(line: 17, column: 8, file: !1, scope: !18)
+!18 = distinct !DILexicalBlock(line: 17, column: 3, file: !1, scope: !4)
+!19 = !DILocation(line: 18, column: 5, scope: !20)
+!20 = distinct !DILexicalBlock(line: 17, column: 27, file: !1, scope: !18)
 !21 = !{!13, !13, i64 0}
-!22 = !MDLocation(line: 20, column: 3, scope: !4)
-!23 = !MDLocation(line: 21, column: 3, scope: !4)
+!22 = !DILocation(line: 20, column: 3, scope: !4)
+!23 = !DILocation(line: 21, column: 3, scope: !4)
diff --git a/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll b/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll
index d8e5403d2d4e..0debb338486c 100644
--- a/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll
+++ b/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll
@@ -17,7 +17,7 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %conv = sitofp i32 1 to x86_fp80
-  %arrayidx = getelementptr inbounds [1024 x x86_fp80]* @x, i64 0, i64 %indvars.iv
+  %arrayidx = getelementptr inbounds [1024 x x86_fp80], [1024 x x86_fp80]* @x, i64 0, i64 %indvars.iv
   store x86_fp80 %conv, x86_fp80* %arrayidx, align 16
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/XCore/no-vector-registers.ll b/test/Transforms/LoopVectorize/XCore/no-vector-registers.ll
index cab333d06406..afb3322dd67e 100644
--- a/test/Transforms/LoopVectorize/XCore/no-vector-registers.ll
+++ b/test/Transforms/LoopVectorize/XCore/no-vector-registers.ll
@@ -13,7 +13,7 @@ entry:
 do.body:
   %ptr.addr.0 = phi i8* [ %ptr, %entry ], [ %incdec.ptr, %do.body ]
   %len.addr.0 = phi i32 [ %len, %entry ], [ %dec, %do.body ]
-  %incdec.ptr = getelementptr inbounds i8* %ptr.addr.0, i32 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %ptr.addr.0, i32 1
   store i8 0, i8* %ptr.addr.0, align 1
   %dec = add nsw i32 %len.addr.0, -1
   %tobool = icmp eq i32 %len.addr.0, 0
diff --git a/test/Transforms/LoopVectorize/align.ll b/test/Transforms/LoopVectorize/align.ll
index f2fb8b91b46e..7ee401deef4e 100644
--- a/test/Transforms/LoopVectorize/align.ll
+++ b/test/Transforms/LoopVectorize/align.ll
@@ -6,8 +6,8 @@ target triple = "x86_64-apple-macosx10.8.0"
 ; Make sure we output the abi alignment if no alignment is specified.
 
 ;CHECK-LABEL: @align
-;CHECK: load <4 x i32>* {{.*}} align  4
-;CHECK: load <4 x i32>* {{.*}} align  4
+;CHECK: load <4 x i32>, <4 x i32>* {{.*}} align  4
+;CHECK: load <4 x i32>, <4 x i32>* {{.*}} align  4
 ;CHECK: store <4 x i32> {{.*}} align  4
 
 define void @align(i32* %a, i32* %b, i32* %c) nounwind uwtable ssp {
@@ -15,12 +15,12 @@ define void @align(i32* %a, i32* %b, i32* %c) nounwind uwtable ssp {
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %3 = load i32* %2
-  %4 = getelementptr inbounds i32* %c, i64 %indvars.iv
-  %5 = load i32* %4
+  %2 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %3 = load i32, i32* %2
+  %4 = getelementptr inbounds i32, i32* %c, i64 %indvars.iv
+  %5 = load i32, i32* %4
   %6 = add nsw i32 %5, %3
-  %7 = getelementptr inbounds i32* %a, i64 %indvars.iv
+  %7 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
   store i32 %6, i32* %7
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/bsd_regex.ll b/test/Transforms/LoopVectorize/bsd_regex.ll
index 7a3e79893da3..ddb00ba31e14 100644
--- a/test/Transforms/LoopVectorize/bsd_regex.ll
+++ b/test/Transforms/LoopVectorize/bsd_regex.ll
@@ -24,7 +24,7 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %0 = shl nsw i64 %indvars.iv, 2
-  %arrayidx = getelementptr inbounds i32* %A, i64 %0
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %0
   store i32 4, i32* %arrayidx, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/bzip_reverse_loops.ll b/test/Transforms/LoopVectorize/bzip_reverse_loops.ll
index d7cbad06ddf0..f1efb256391b 100644
--- a/test/Transforms/LoopVectorize/bzip_reverse_loops.ll
+++ b/test/Transforms/LoopVectorize/bzip_reverse_loops.ll
@@ -16,8 +16,8 @@ entry:
 do.body:                                          ; preds = %cond.end, %entry
   %n.addr.0 = phi i32 [ %n, %entry ], [ %dec, %cond.end ]
   %p.addr.0 = phi i16* [ %p, %entry ], [ %incdec.ptr, %cond.end ]
-  %incdec.ptr = getelementptr inbounds i16* %p.addr.0, i64 -1
-  %0 = load i16* %incdec.ptr, align 2
+  %incdec.ptr = getelementptr inbounds i16, i16* %p.addr.0, i64 -1
+  %0 = load i16, i16* %incdec.ptr, align 2
   %conv = zext i16 %0 to i32
   %cmp = icmp ult i32 %conv, %size
   br i1 %cmp, label %cond.end, label %cond.true
@@ -51,8 +51,8 @@ entry:
 do.body:                                          ; preds = %do.body, %entry
   %n.addr.0 = phi i32 [ %n, %entry ], [ %dec, %do.body ]
   %p.0 = phi i32* [ %a, %entry ], [ %incdec.ptr, %do.body ]
-  %incdec.ptr = getelementptr inbounds i32* %p.0, i64 -1
-  %0 = load i32* %incdec.ptr, align 4
+  %incdec.ptr = getelementptr inbounds i32, i32* %p.0, i64 -1
+  %0 = load i32, i32* %incdec.ptr, align 4
   %cmp = icmp slt i32 %0, %wsize
   %sub = sub nsw i32 %0, %wsize
   %cond = select i1 %cmp, i32 0, i32 %sub
diff --git a/test/Transforms/LoopVectorize/calloc.ll b/test/Transforms/LoopVectorize/calloc.ll
index 5f441f3e238f..a41e51787f32 100644
--- a/test/Transforms/LoopVectorize/calloc.ll
+++ b/test/Transforms/LoopVectorize/calloc.ll
@@ -22,8 +22,8 @@ for.body.lr.ph:                                   ; preds = %entry
 for.body:                                         ; preds = %for.body, %for.body.lr.ph
   %i.030 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %shr = lshr i64 %i.030, 1
-  %arrayidx = getelementptr inbounds i8* %bytes, i64 %shr
-  %1 = load i8* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %bytes, i64 %shr
+  %1 = load i8, i8* %arrayidx, align 1
   %conv = zext i8 %1 to i32
   %and = shl i64 %i.030, 2
   %neg = and i64 %and, 4
@@ -37,7 +37,7 @@ for.body:                                         ; preds = %for.body, %for.body
   %cond = select i1 %cmp15, i32 87, i32 48
   %add17 = add nsw i32 %cond, %shr11
   %conv18 = trunc i32 %add17 to i8
-  %arrayidx19 = getelementptr inbounds i8* %call, i64 %i.030
+  %arrayidx19 = getelementptr inbounds i8, i8* %call, i64 %i.030
   store i8 %conv18, i8* %arrayidx19, align 1
   %inc = add i64 %i.030, 1
   %exitcond = icmp eq i64 %inc, %0
diff --git a/test/Transforms/LoopVectorize/cast-induction.ll b/test/Transforms/LoopVectorize/cast-induction.ll
index 4f92d33ff528..fae89976a7bc 100644
--- a/test/Transforms/LoopVectorize/cast-induction.ll
+++ b/test/Transforms/LoopVectorize/cast-induction.ll
@@ -16,7 +16,7 @@ define void @example12() nounwind uwtable ssp {
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
   %3 = trunc i64 %indvars.iv to i32
   store i32 %3, i32* %2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/conditional-assignment.ll b/test/Transforms/LoopVectorize/conditional-assignment.ll
index 38e9c4f9a61c..f41f08df07a6 100644
--- a/test/Transforms/LoopVectorize/conditional-assignment.ll
+++ b/test/Transforms/LoopVectorize/conditional-assignment.ll
@@ -12,8 +12,8 @@ entry:
 
 for.body:                                         ; preds = %for.inc, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ]
-  %arrayidx = getelementptr inbounds i32* %indices, i64 %indvars.iv, !dbg !12
-  %0 = load i32* %arrayidx, align 4, !dbg !12, !tbaa !14
+  %arrayidx = getelementptr inbounds i32, i32* %indices, i64 %indvars.iv, !dbg !12
+  %0 = load i32, i32* %arrayidx, align 4, !dbg !12, !tbaa !14
   %cmp1 = icmp eq i32 %0, 1024, !dbg !12
   br i1 %cmp1, label %if.then, label %for.inc, !dbg !12
 
@@ -36,23 +36,23 @@ attributes #0 = { nounwind }
 !llvm.module.flags = !{!7, !8}
 !llvm.ident = !{!9}
 
-!0 = !{!"0x11\0012\00clang version 3.6.0\001\00\000\00\002", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ]
-!1 = !{!"source.c", !"."}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.6.0", isOptimized: true, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "source.c", directory: ".")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00conditional_store\00conditional_store\00\001\000\001\000\006\00256\001\001", !1, !5, !6, null, void (i32*)* @conditional_store, null, null, !2} ; [ DW_TAG_subprogram ]
-!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ]
+!4 = !DISubprogram(name: "conditional_store", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !1, scope: !5, type: !6, function: void (i32*)* @conditional_store, variables: !2)
+!5 = !DIFile(filename: "source.c", directory: ".")
+!6 = !DISubroutineType(types: !2)
 !7 = !{i32 2, !"Dwarf Version", i32 2}
-!8 = !{i32 2, !"Debug Info Version", i32 2}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
 !9 = !{!"clang version 3.6.0"}
-!10 = !MDLocation(line: 2, column: 8, scope: !11)
-!11 = !{!"0xb\002\003\000", !1, !4} ; [ DW_TAG_lexical_block ]
-!12 = !MDLocation(line: 3, column: 9, scope: !13)
-!13 = !{!"0xb\003\009\000", !1, !11} ; [ DW_TAG_lexical_block ]
+!10 = !DILocation(line: 2, column: 8, scope: !11)
+!11 = distinct !DILexicalBlock(line: 2, column: 3, file: !1, scope: !4)
+!12 = !DILocation(line: 3, column: 9, scope: !13)
+!13 = distinct !DILexicalBlock(line: 3, column: 9, file: !1, scope: !11)
 !14 = !{!15, !15, i64 0}
 !15 = !{!"int", !16, i64 0}
 !16 = !{!"omnipotent char", !17, i64 0}
 !17 = !{!"Simple C/C++ TBAA"}
-!18 = !MDLocation(line: 3, column: 29, scope: !13)
-!19 = !MDLocation(line: 4, column: 1, scope: !4)
+!18 = !DILocation(line: 3, column: 29, scope: !13)
+!19 = !DILocation(line: 4, column: 1, scope: !4)
diff --git a/test/Transforms/LoopVectorize/control-flow.ll b/test/Transforms/LoopVectorize/control-flow.ll
index 1882c3ff9a83..c56f9122e462 100644
--- a/test/Transforms/LoopVectorize/control-flow.ll
+++ b/test/Transforms/LoopVectorize/control-flow.ll
@@ -30,8 +30,8 @@ for.body.preheader:                               ; preds = %entry
 
 for.body:                                         ; preds = %for.body.preheader, %if.else
   %indvars.iv = phi i64 [ %indvars.iv.next, %if.else ], [ 0, %for.body.preheader ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv, !dbg !12
-  %0 = load i32* %arrayidx, align 4, !dbg !12, !tbaa !15
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv, !dbg !12
+  %0 = load i32, i32* %arrayidx, align 4, !dbg !12, !tbaa !15
   %cmp1 = icmp sgt i32 %0, 10, !dbg !12
   br i1 %cmp1, label %end.loopexit, label %if.else, !dbg !12
 
@@ -55,24 +55,24 @@ attributes #0 = { nounwind }
 !llvm.module.flags = !{!7, !8}
 !llvm.ident = !{!9}
 
-!0 = !{!"0x11\004\00clang version 3.5.0\001\00\006\00\002", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [./source.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"source.cpp", !"."}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0", isOptimized: true, runtimeVersion: 6, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "source.cpp", directory: ".")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00test\00test\00\001\000\001\000\006\00256\001\002", !1, !5, !6, null, i32 (i32*, i32)* @_Z4testPii, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [scope 2] [test]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [./source.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "test", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2, file: !1, scope: !5, type: !6, function: i32 (i32*, i32)* @_Z4testPii, variables: !2)
+!5 = !DIFile(filename: "source.cpp", directory: ".")
+!6 = !DISubroutineType(types: !2)
 !7 = !{i32 2, !"Dwarf Version", i32 2}
-!8 = !{i32 2, !"Debug Info Version", i32 2}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
 !9 = !{!"clang version 3.5.0"}
-!10 = !MDLocation(line: 3, column: 8, scope: !11)
-!11 = !{!"0xb\003\003\000", !1, !4} ; [ DW_TAG_lexical_block ]
-!12 = !MDLocation(line: 5, column: 9, scope: !13)
-!13 = !{!"0xb\005\009\000", !1, !14} ; [ DW_TAG_lexical_block ]
-!14 = !{!"0xb\004\003\000", !1, !11} ; [ DW_TAG_lexical_block ]
+!10 = !DILocation(line: 3, column: 8, scope: !11)
+!11 = distinct !DILexicalBlock(line: 3, column: 3, file: !1, scope: !4)
+!12 = !DILocation(line: 5, column: 9, scope: !13)
+!13 = distinct !DILexicalBlock(line: 5, column: 9, file: !1, scope: !14)
+!14 = distinct !DILexicalBlock(line: 4, column: 3, file: !1, scope: !11)
 !15 = !{!16, !16, i64 0}
 !16 = !{!"int", !17, i64 0}
 !17 = !{!"omnipotent char", !18, i64 0}
 !18 = !{!"Simple C/C++ TBAA"}
-!19 = !MDLocation(line: 8, column: 7, scope: !13)
-!20 = !MDLocation(line: 12, column: 3, scope: !4)
+!19 = !DILocation(line: 8, column: 7, scope: !13)
+!20 = !DILocation(line: 12, column: 3, scope: !4)
diff --git a/test/Transforms/LoopVectorize/cpp-new-array.ll b/test/Transforms/LoopVectorize/cpp-new-array.ll
index f32f610b1cd6..22896d33428a 100644
--- a/test/Transforms/LoopVectorize/cpp-new-array.ll
+++ b/test/Transforms/LoopVectorize/cpp-new-array.ll
@@ -24,21 +24,21 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %idxprom = sext i32 %i.01 to i64
-  %arrayidx = getelementptr inbounds float* %0, i64 %idxprom
-  %3 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %0, i64 %idxprom
+  %3 = load float, float* %arrayidx, align 4
   %idxprom5 = sext i32 %i.01 to i64
-  %arrayidx6 = getelementptr inbounds float* %1, i64 %idxprom5
-  %4 = load float* %arrayidx6, align 4
+  %arrayidx6 = getelementptr inbounds float, float* %1, i64 %idxprom5
+  %4 = load float, float* %arrayidx6, align 4
   %add = fadd float %3, %4
   %idxprom7 = sext i32 %i.01 to i64
-  %arrayidx8 = getelementptr inbounds float* %2, i64 %idxprom7
+  %arrayidx8 = getelementptr inbounds float, float* %2, i64 %idxprom7
   store float %add, float* %arrayidx8, align 4
   %inc = add nsw i32 %i.01, 1
   %cmp = icmp slt i32 %inc, 1000
   br i1 %cmp, label %for.body, label %for.end
 
 for.end:                                          ; preds = %for.body
-  %5 = load float* %2, align 4
+  %5 = load float, float* %2, align 4
   %conv10 = fptosi float %5 to i32
   ret i32 %conv10
 }
diff --git a/test/Transforms/LoopVectorize/dbg.value.ll b/test/Transforms/LoopVectorize/dbg.value.ll
index 92d315481266..c7440f84b2c9 100644
--- a/test/Transforms/LoopVectorize/dbg.value.ll
+++ b/test/Transforms/LoopVectorize/dbg.value.ll
@@ -11,21 +11,21 @@ target triple = "x86_64-apple-macosx10.8.0"
 ; CHECK-LABEL: @test(
 define i32 @test() #0 {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !9, metadata !{}), !dbg !18
+  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !9, metadata !DIExpression()), !dbg !18
   br label %for.body, !dbg !18
 
 for.body:
   ;CHECK: load <4 x i32>
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @B, i64 0, i64 %indvars.iv, !dbg !19
-  %0 = load i32* %arrayidx, align 4, !dbg !19
-  %arrayidx2 = getelementptr inbounds [1024 x i32]* @C, i64 0, i64 %indvars.iv, !dbg !19
-  %1 = load i32* %arrayidx2, align 4, !dbg !19
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @B, i64 0, i64 %indvars.iv, !dbg !19
+  %0 = load i32, i32* %arrayidx, align 4, !dbg !19
+  %arrayidx2 = getelementptr inbounds [1024 x i32], [1024 x i32]* @C, i64 0, i64 %indvars.iv, !dbg !19
+  %1 = load i32, i32* %arrayidx2, align 4, !dbg !19
   %add = add nsw i32 %1, %0, !dbg !19
-  %arrayidx4 = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv, !dbg !19
+  %arrayidx4 = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv, !dbg !19
   store i32 %add, i32* %arrayidx4, align 4, !dbg !19
   %indvars.iv.next = add i64 %indvars.iv, 1, !dbg !18
-  tail call void @llvm.dbg.value(metadata !{null}, i64 0, metadata !9, metadata !{}), !dbg !18
+  tail call void @llvm.dbg.value(metadata !{null}, i64 0, metadata !9, metadata !DIExpression()), !dbg !18
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32, !dbg !18
   %exitcond = icmp ne i32 %lftr.wideiv, 1024, !dbg !18
   br i1 %exitcond, label %for.body, label %for.end, !dbg !18
@@ -44,27 +44,27 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!26}
 
-!0 = !{!"0x11\004\00clang\001\00\000\00\000", !25, !1, !1, !2, !11, null} ; [ DW_TAG_compile_unit ]
-!1 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang", isOptimized: true, emissionKind: 0, file: !25, enums: !1, retainedTypes: !1, subprograms: !2, globals: !11)
+!1 = !{}
 !2 = !{!3}
-!3 = !{!"0x2e\00test\00test\00test\005\000\001\000\006\00256\001\005", !25, !4, !5, null, i32 ()* @test, null, null, !8} ; [ DW_TAG_subprogram ]
-!4 = !{!"0x29", !25} ; [ DW_TAG_file_type ]
-!5 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !6, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!3 = !DISubprogram(name: "test", linkageName: "test", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !25, scope: !4, type: !5, function: i32 ()* @test, variables: !8)
+!4 = !DIFile(filename: "test", directory: "/path/to/somewhere")
+!5 = !DISubroutineType(types: !6)
 !6 = !{!7}
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ]
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !8 = !{!9}
-!9 = !{!"0x100\00i\006\000", !10, !4, !7} ; [ DW_TAG_auto_variable ]
-!10 = !{!"0xb\006\000\000", !25, !3} ; [ DW_TAG_lexical_block ]
+!9 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 6, scope: !10, file: !4, type: !7)
+!10 = distinct !DILexicalBlock(line: 6, column: 0, file: !25, scope: !3)
 !11 = !{!12, !16, !17}
-!12 = !{!"0x34\00A\00A\00\001\000\001", null, !4, !13, [1024 x i32]* @A, null} ; [ DW_TAG_variable ]
-!13 = !{!"0x1\00\000\0032768\0032\000\000", null, null, !7, !14, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 32768, align 32, offset 0] [from int]
+!12 = !DIGlobalVariable(name: "A", line: 1, isLocal: false, isDefinition: true, scope: null, file: !4, type: !13, variable: [1024 x i32]* @A)
+!13 = !DICompositeType(tag: DW_TAG_array_type, size: 32768, align: 32, baseType: !7, elements: !14)
 !14 = !{!15}
 !15 = !{i32 786465, i64 0, i64 1024}
-!16 = !{!"0x34\00B\00B\00\002\000\001", null, !4, !13, [1024 x i32]* @B, null} ; [ DW_TAG_variable ]
-!17 = !{!"0x34\00C\00C\00\003\000\001", null, !4, !13, [1024 x i32]* @C, null} ; [ DW_TAG_variable ]
-!18 = !MDLocation(line: 6, scope: !10)
-!19 = !MDLocation(line: 7, scope: !20)
-!20 = !{!"0xb\006\000\001", !25, !10} ; [ DW_TAG_lexical_block ]
-!24 = !MDLocation(line: 9, scope: !3)
-!25 = !{!"test", !"/path/to/somewhere"}
-!26 = !{i32 1, !"Debug Info Version", i32 2}
+!16 = !DIGlobalVariable(name: "B", line: 2, isLocal: false, isDefinition: true, scope: null, file: !4, type: !13, variable: [1024 x i32]* @B)
+!17 = !DIGlobalVariable(name: "C", line: 3, isLocal: false, isDefinition: true, scope: null, file: !4, type: !13, variable: [1024 x i32]* @C)
+!18 = !DILocation(line: 6, scope: !10)
+!19 = !DILocation(line: 7, scope: !20)
+!20 = distinct !DILexicalBlock(line: 6, column: 0, file: !25, scope: !10)
+!24 = !DILocation(line: 9, scope: !3)
+!25 = !DIFile(filename: "test", directory: "/path/to/somewhere")
+!26 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/LoopVectorize/debugloc.ll b/test/Transforms/LoopVectorize/debugloc.ll
index 634bf79ddf0e..e691afdd6933 100644
--- a/test/Transforms/LoopVectorize/debugloc.ll
+++ b/test/Transforms/LoopVectorize/debugloc.ll
@@ -8,8 +8,8 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; CHECK:   cmp.zero = icmp eq i64 {{.*}}, 0, !dbg ![[LOC:[0-9]+]]
 ; CHECK: vector.body
 ; CHECK:   index {{.*}}, !dbg ![[LOC]]
-; CHECK:   getelementptr inbounds i32* %a, {{.*}}, !dbg ![[LOC2:[0-9]+]]
-; CHECK:   load <2 x i32>* {{.*}}, !dbg ![[LOC2]]
+; CHECK:   getelementptr inbounds i32, i32* %a, {{.*}}, !dbg ![[LOC2:[0-9]+]]
+; CHECK:   load <2 x i32>, <2 x i32>* {{.*}}, !dbg ![[LOC2]]
 ; CHECK:   add <2 x i32> {{.*}}, !dbg ![[LOC2]]
 ; CHECK:   add i64 %index, 2, !dbg ![[LOC]]
 ; CHECK:   icmp eq i64 %index.next, %end.idx.rnd.down, !dbg ![[LOC]]
@@ -19,10 +19,10 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 define i32 @f(i32* nocapture %a, i32 %size) #0 {
 entry:
-  tail call void @llvm.dbg.value(metadata i32* %a, i64 0, metadata !13, metadata !{}), !dbg !19
-  tail call void @llvm.dbg.value(metadata i32 %size, i64 0, metadata !14, metadata !{}), !dbg !19
-  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !15, metadata !{}), !dbg !20
-  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !16, metadata !{}), !dbg !21
+  tail call void @llvm.dbg.value(metadata i32* %a, i64 0, metadata !13, metadata !DIExpression()), !dbg !19
+  tail call void @llvm.dbg.value(metadata i32 %size, i64 0, metadata !14, metadata !DIExpression()), !dbg !19
+  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !15, metadata !DIExpression()), !dbg !20
+  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !16, metadata !DIExpression()), !dbg !21
   %cmp4 = icmp eq i32 %size, 0, !dbg !21
   br i1 %cmp4, label %for.end, label %for.body.lr.ph, !dbg !21
 
@@ -32,12 +32,12 @@ for.body.lr.ph:                                   ; preds = %entry
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]
   %sum.05 = phi i32 [ 0, %for.body.lr.ph ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv, !dbg !22
-  %0 = load i32* %arrayidx, align 4, !dbg !22
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv, !dbg !22
+  %0 = load i32, i32* %arrayidx, align 4, !dbg !22
   %add = add i32 %0, %sum.05, !dbg !22
-  tail call void @llvm.dbg.value(metadata i32 %add.lcssa, i64 0, metadata !15, metadata !{}), !dbg !22
+  tail call void @llvm.dbg.value(metadata i32 %add.lcssa, i64 0, metadata !15, metadata !DIExpression()), !dbg !22
   %indvars.iv.next = add i64 %indvars.iv, 1, !dbg !21
-  tail call void @llvm.dbg.value(metadata !{null}, i64 0, metadata !16, metadata !{}), !dbg !21
+  tail call void @llvm.dbg.value(metadata !{null}, i64 0, metadata !16, metadata !DIExpression()), !dbg !21
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32, !dbg !21
   %exitcond = icmp ne i32 %lftr.wideiv, %size, !dbg !21
   br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge, !dbg !21
@@ -63,28 +63,28 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!18, !27}
 
-!0 = !{!"0x11\0012\00clang version 3.4 (trunk 185038) (llvm/trunk 185097)\001\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/Volumes/Data/backedup/dev/os/llvm/debug/-] [DW_LANG_C99]
-!1 = !{!"-", !"/Volumes/Data/backedup/dev/os/llvm/debug"}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 185038) (llvm/trunk 185097)", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "-", directory: "/Volumes/Data/backedup/dev/os/llvm/debug")
+!2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00f\00f\00\003\000\001\000\006\00256\001\003", !5, !6, !7, null, i32 (i32*, i32)* @f, null, null, !12} ; [ DW_TAG_subprogram ] [line 3] [def] [f]
-!5 = !{!"<stdin>", !"/Volumes/Data/backedup/dev/os/llvm/debug"}
-!6 = !{!"0x29", !5}          ; [ DW_TAG_file_type ] [/Volumes/Data/backedup/dev/os/llvm/debug/<stdin>]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "f", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !5, scope: !6, type: !7, function: i32 (i32*, i32)* @f, variables: !12)
+!5 = !DIFile(filename: "<stdin>", directory: "/Volumes/Data/backedup/dev/os/llvm/debug")
+!6 = !DIFile(filename: "<stdin>", directory: "/Volumes/Data/backedup/dev/os/llvm/debug")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9, !10, !11}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"0xf\00\000\0064\0064\000\000", null, null, !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
-!11 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, null} ; [ DW_TAG_base_type ] [unsigned int] [line 0, size 32, align 32, offset 0, enc DW_ATE_unsigned]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !9)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
 !12 = !{!13, !14, !15, !16}
-!13 = !{!"0x101\00a\0016777219\000", !4, !6, !10} ; [ DW_TAG_arg_variable ] [a] [line 3]
-!14 = !{!"0x101\00size\0033554435\000", !4, !6, !11} ; [ DW_TAG_arg_variable ] [size] [line 3]
-!15 = !{!"0x100\00sum\004\000", !4, !6, !11} ; [ DW_TAG_auto_variable ] [sum] [line 4]
-!16 = !{!"0x100\00i\005\000", !17, !6, !11} ; [ DW_TAG_auto_variable ] [i] [line 5]
-!17 = !{!"0xb\005\000\000", !5, !4} ; [ DW_TAG_lexical_block ] [/Volumes/Data/backedup/dev/os/llvm/debug/<stdin>]
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 3, arg: 1, scope: !4, file: !6, type: !10)
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "size", line: 3, arg: 2, scope: !4, file: !6, type: !11)
+!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "sum", line: 4, scope: !4, file: !6, type: !11)
+!16 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 5, scope: !17, file: !6, type: !11)
+!17 = distinct !DILexicalBlock(line: 5, column: 0, file: !5, scope: !4)
 !18 = !{i32 2, !"Dwarf Version", i32 3}
-!19 = !MDLocation(line: 3, scope: !4)
-!20 = !MDLocation(line: 4, scope: !4)
-!21 = !MDLocation(line: 5, scope: !17)
-!22 = !MDLocation(line: 6, scope: !17)
-!26 = !MDLocation(line: 7, scope: !4)
-!27 = !{i32 1, !"Debug Info Version", i32 2}
+!19 = !DILocation(line: 3, scope: !4)
+!20 = !DILocation(line: 4, scope: !4)
+!21 = !DILocation(line: 5, scope: !17)
+!22 = !DILocation(line: 6, scope: !17)
+!26 = !DILocation(line: 7, scope: !4)
+!27 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/LoopVectorize/duplicated-metadata.ll b/test/Transforms/LoopVectorize/duplicated-metadata.ll
index bf2f899dff04..9f7cdef51fe3 100644
--- a/test/Transforms/LoopVectorize/duplicated-metadata.ll
+++ b/test/Transforms/LoopVectorize/duplicated-metadata.ll
@@ -12,8 +12,8 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds float* %a, i64 %indvars.iv
-  %p = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 %indvars.iv
+  %p = load float, float* %arrayidx, align 4
   %mul = fmul float %p, 2.000000e+00
   store float %mul, float* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/ee-crash.ll b/test/Transforms/LoopVectorize/ee-crash.ll
index a3c0bb89b128..0c387346f867 100644
--- a/test/Transforms/LoopVectorize/ee-crash.ll
+++ b/test/Transforms/LoopVectorize/ee-crash.ll
@@ -11,18 +11,18 @@ target triple = "x86_64-apple-macosx10.8.0"
 define i32 @_Z4foo1Pii(i32* %A, i32 %n, <2 x i32> %q) #0 {
 entry:
   %idx.ext = sext i32 %n to i64
-  %add.ptr = getelementptr inbounds i32* %A, i64 %idx.ext
+  %add.ptr = getelementptr inbounds i32, i32* %A, i64 %idx.ext
   %cmp3.i = icmp eq i32 %n, 0
   br i1 %cmp3.i, label %_ZSt10accumulateIPiiET0_T_S2_S1_.exit, label %for.body.i
 
 for.body.i:                                       ; preds = %entry, %for.body.i
   %__init.addr.05.i = phi i32 [ %add.i, %for.body.i ], [ 0, %entry ]
   %__first.addr.04.i = phi i32* [ %incdec.ptr.i, %for.body.i ], [ %A, %entry ]
-  %0 = load i32* %__first.addr.04.i, align 4
+  %0 = load i32, i32* %__first.addr.04.i, align 4
   %q1 = extractelement <2 x i32> %q, i32 %n
   %q2 = add nsw i32 %0, %q1
   %add.i = add nsw i32 %q2, %__init.addr.05.i
-  %incdec.ptr.i = getelementptr inbounds i32* %__first.addr.04.i, i64 1
+  %incdec.ptr.i = getelementptr inbounds i32, i32* %__first.addr.04.i, i64 1
   %cmp.i = icmp eq i32* %incdec.ptr.i, %add.ptr
   br i1 %cmp.i, label %_ZSt10accumulateIPiiET0_T_S2_S1_.exit, label %for.body.i
 
diff --git a/test/Transforms/LoopVectorize/exact.ll b/test/Transforms/LoopVectorize/exact.ll
index 0a8fbf337347..0a4e0dc17dfa 100644
--- a/test/Transforms/LoopVectorize/exact.ll
+++ b/test/Transforms/LoopVectorize/exact.ll
@@ -11,8 +11,8 @@ entry:
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %x, i64 %iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %x, i64 %iv
+  %0 = load i32, i32* %arrayidx, align 4
   %conv1 = lshr exact i32 %0, 1
   store i32 %conv1, i32* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
diff --git a/test/Transforms/LoopVectorize/flags.ll b/test/Transforms/LoopVectorize/flags.ll
index 0fc55c897310..fcbc8741741e 100644
--- a/test/Transforms/LoopVectorize/flags.ll
+++ b/test/Transforms/LoopVectorize/flags.ll
@@ -14,8 +14,8 @@ define i32 @flags1(i32 %n, i32* nocapture %A) nounwind uwtable ssp {
 
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 9, %0 ]
-  %2 = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %3 = load i32* %2, align 4
+  %2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
   %4 = mul nsw i32 %3, 3
   store i32 %4, i32* %2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -39,8 +39,8 @@ define i32 @flags2(i32 %n, i32* nocapture %A) nounwind uwtable ssp {
 
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 9, %0 ]
-  %2 = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %3 = load i32* %2, align 4
+  %2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
   %4 = mul i32 %3, 3
   store i32 %4, i32* %2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -66,8 +66,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %q.04 = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds float* %s, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %s, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %add = fadd fast float %q.04, %0
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 256
diff --git a/test/Transforms/LoopVectorize/float-reduction.ll b/test/Transforms/LoopVectorize/float-reduction.ll
index 0f064ee2dc85..1310b279f61e 100644
--- a/test/Transforms/LoopVectorize/float-reduction.ll
+++ b/test/Transforms/LoopVectorize/float-reduction.ll
@@ -12,8 +12,8 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %sum.04 = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds float* %A, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %A, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %add = fadd fast float %sum.04, %0
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -34,8 +34,8 @@ entry:
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %sum.04 = phi float [ 0.000000e+00, %entry ], [ %sub, %for.body ]
-  %arrayidx = getelementptr inbounds float* %A, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %A, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %sub = fsub fast float %sum.04, %0
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/funcall.ll b/test/Transforms/LoopVectorize/funcall.ll
index e03534fbac37..35c2dfca4b2f 100644
--- a/test/Transforms/LoopVectorize/funcall.ll
+++ b/test/Transforms/LoopVectorize/funcall.ll
@@ -16,8 +16,8 @@ entry:
 
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds double* %d, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %d, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %1 = tail call double @llvm.pow.f64(double %0, double %t)
   store double %1, double* %arrayidx, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/gcc-examples.ll b/test/Transforms/LoopVectorize/gcc-examples.ll
index 6c8af0bcd7c9..188090186158 100644
--- a/test/Transforms/LoopVectorize/gcc-examples.ll
+++ b/test/Transforms/LoopVectorize/gcc-examples.ll
@@ -44,12 +44,12 @@ define void @example1() nounwind uwtable ssp {
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %indvars.iv
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds [2048 x i32]* @c, i64 0, i64 %indvars.iv
-  %5 = load i32* %4, align 4
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds [2048 x i32], [2048 x i32]* @c, i64 0, i64 %indvars.iv
+  %5 = load i32, i32* %4, align 4
   %6 = add nsw i32 %5, %3
-  %7 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %7 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
   store i32 %6, i32* %7, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -84,7 +84,7 @@ define void @example2(i32 %n, i32 %x) nounwind uwtable ssp {
 
 .lr.ph5:                                          ; preds = %0, %.lr.ph5
   %indvars.iv6 = phi i64 [ %indvars.iv.next7, %.lr.ph5 ], [ 0, %0 ]
-  %3 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %indvars.iv6
+  %3 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %indvars.iv6
   store i32 %x, i32* %3, align 4
   %indvars.iv.next7 = add i64 %indvars.iv6, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next7 to i32
@@ -95,12 +95,12 @@ define void @example2(i32 %n, i32 %x) nounwind uwtable ssp {
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ %i.0.lcssa, %.preheader ]
   %.02 = phi i32 [ %4, %.lr.ph ], [ %n, %.preheader ]
   %4 = add nsw i32 %.02, -1
-  %5 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %indvars.iv
-  %6 = load i32* %5, align 4
-  %7 = getelementptr inbounds [2048 x i32]* @c, i64 0, i64 %indvars.iv
-  %8 = load i32* %7, align 4
+  %5 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %indvars.iv
+  %6 = load i32, i32* %5, align 4
+  %7 = getelementptr inbounds [2048 x i32], [2048 x i32]* @c, i64 0, i64 %indvars.iv
+  %8 = load i32, i32* %7, align 4
   %9 = and i32 %8, %6
-  %10 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %10 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
   store i32 %9, i32* %10, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %11 = icmp eq i32 %4, 0
@@ -128,9 +128,9 @@ define void @example3(i32 %n, i32* noalias nocapture %p, i32* noalias nocapture
   %.014 = phi i32* [ %5, %.lr.ph ], [ %p, %0 ]
   %.023 = phi i32* [ %3, %.lr.ph ], [ %q, %0 ]
   %2 = add nsw i32 %.05, -1
-  %3 = getelementptr inbounds i32* %.023, i64 1
-  %4 = load i32* %.023, align 16
-  %5 = getelementptr inbounds i32* %.014, i64 1
+  %3 = getelementptr inbounds i32, i32* %.023, i64 1
+  %4 = load i32, i32* %.023, align 16
+  %5 = getelementptr inbounds i32, i32* %.014, i64 1
   store i32 %4, i32* %.014, align 16
   %6 = icmp eq i32 %2, 0
   br i1 %6, label %._crit_edge, label %.lr.ph
@@ -161,10 +161,10 @@ define void @example4(i32 %n, i32* noalias nocapture %p, i32* noalias nocapture
   %4 = phi i32 [ %9, %.lr.ph10 ], [ %1, %0 ]
   %.018 = phi i32* [ %8, %.lr.ph10 ], [ %p, %0 ]
   %.027 = phi i32* [ %5, %.lr.ph10 ], [ %q, %0 ]
-  %5 = getelementptr inbounds i32* %.027, i64 1
-  %6 = load i32* %.027, align 16
+  %5 = getelementptr inbounds i32, i32* %.027, i64 1
+  %6 = load i32, i32* %.027, align 16
   %7 = add nsw i32 %6, 5
-  %8 = getelementptr inbounds i32* %.018, i64 1
+  %8 = getelementptr inbounds i32, i32* %.018, i64 1
   store i32 %7, i32* %.018, align 16
   %9 = add nsw i32 %4, -1
   %10 = icmp eq i32 %4, 0
@@ -176,13 +176,13 @@ define void @example4(i32 %n, i32* noalias nocapture %p, i32* noalias nocapture
 .lr.ph6:                                          ; preds = %.preheader4, %.lr.ph6
   %indvars.iv11 = phi i64 [ %indvars.iv.next12, %.lr.ph6 ], [ 0, %.preheader4 ]
   %indvars.iv.next12 = add i64 %indvars.iv11, 1
-  %11 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %indvars.iv.next12
-  %12 = load i32* %11, align 4
+  %11 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %indvars.iv.next12
+  %12 = load i32, i32* %11, align 4
   %13 = add nsw i64 %indvars.iv11, 3
-  %14 = getelementptr inbounds [2048 x i32]* @c, i64 0, i64 %13
-  %15 = load i32* %14, align 4
+  %14 = getelementptr inbounds [2048 x i32], [2048 x i32]* @c, i64 0, i64 %13
+  %15 = load i32, i32* %14, align 4
   %16 = add nsw i32 %15, %12
-  %17 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv11
+  %17 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv11
   store i32 %16, i32* %17, align 4
   %lftr.wideiv13 = trunc i64 %indvars.iv.next12 to i32
   %exitcond14 = icmp eq i32 %lftr.wideiv13, %1
@@ -190,11 +190,11 @@ define void @example4(i32 %n, i32* noalias nocapture %p, i32* noalias nocapture
 
 .lr.ph:                                           ; preds = %.preheader, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.preheader ]
-  %18 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
-  %19 = load i32* %18, align 4
+  %18 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %19 = load i32, i32* %18, align 4
   %20 = icmp sgt i32 %19, 4
   %21 = select i1 %20, i32 4, i32 0
-  %22 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %indvars.iv
+  %22 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %indvars.iv
   store i32 %21, i32* %22, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -223,7 +223,7 @@ define void @example8(i32 %x) nounwind uwtable ssp {
 
 ; <label>:1                                       ; preds = %1, %.preheader
   %indvars.iv = phi i64 [ 0, %.preheader ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds [32 x [1024 x i32]]* @G, i64 0, i64 %indvars.iv3, i64 %indvars.iv
+  %2 = getelementptr inbounds [32 x [1024 x i32]], [32 x [1024 x i32]]* @G, i64 0, i64 %indvars.iv3, i64 %indvars.iv
   store i32 %x, i32* %2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -249,10 +249,10 @@ define i32 @example9() nounwind uwtable readonly ssp {
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
   %diff.01 = phi i32 [ 0, %0 ], [ %7, %1 ]
-  %2 = getelementptr inbounds [1024 x i32]* @ub, i64 0, i64 %indvars.iv
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds [1024 x i32]* @uc, i64 0, i64 %indvars.iv
-  %5 = load i32* %4, align 4
+  %2 = getelementptr inbounds [1024 x i32], [1024 x i32]* @ub, i64 0, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds [1024 x i32], [1024 x i32]* @uc, i64 0, i64 %indvars.iv
+  %5 = load i32, i32* %4, align 4
   %6 = add i32 %3, %diff.01
   %7 = sub i32 %6, %5
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -276,19 +276,19 @@ define void @example10a(i16* noalias nocapture %sa, i16* noalias nocapture %sb,
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds i32* %ib, i64 %indvars.iv
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds i32* %ic, i64 %indvars.iv
-  %5 = load i32* %4, align 4
+  %2 = getelementptr inbounds i32, i32* %ib, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds i32, i32* %ic, i64 %indvars.iv
+  %5 = load i32, i32* %4, align 4
   %6 = add nsw i32 %5, %3
-  %7 = getelementptr inbounds i32* %ia, i64 %indvars.iv
+  %7 = getelementptr inbounds i32, i32* %ia, i64 %indvars.iv
   store i32 %6, i32* %7, align 4
-  %8 = getelementptr inbounds i16* %sb, i64 %indvars.iv
-  %9 = load i16* %8, align 2
-  %10 = getelementptr inbounds i16* %sc, i64 %indvars.iv
-  %11 = load i16* %10, align 2
+  %8 = getelementptr inbounds i16, i16* %sb, i64 %indvars.iv
+  %9 = load i16, i16* %8, align 2
+  %10 = getelementptr inbounds i16, i16* %sc, i64 %indvars.iv
+  %11 = load i16, i16* %10, align 2
   %12 = add i16 %11, %9
-  %13 = getelementptr inbounds i16* %sa, i64 %indvars.iv
+  %13 = getelementptr inbounds i16, i16* %sa, i64 %indvars.iv
   store i16 %12, i16* %13, align 2
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -309,10 +309,10 @@ define void @example10b(i16* noalias nocapture %sa, i16* noalias nocapture %sb,
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds i16* %sb, i64 %indvars.iv
-  %3 = load i16* %2, align 2
+  %2 = getelementptr inbounds i16, i16* %sb, i64 %indvars.iv
+  %3 = load i16, i16* %2, align 2
   %4 = sext i16 %3 to i32
-  %5 = getelementptr inbounds i32* %ia, i64 %indvars.iv
+  %5 = getelementptr inbounds i32, i32* %ia, i64 %indvars.iv
   store i32 %4, i32* %5, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -340,23 +340,23 @@ define void @example11() nounwind uwtable ssp {
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
   %2 = shl nsw i64 %indvars.iv, 1
   %3 = or i64 %2, 1
-  %4 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %3
-  %5 = load i32* %4, align 4
-  %6 = getelementptr inbounds [2048 x i32]* @c, i64 0, i64 %3
-  %7 = load i32* %6, align 4
+  %4 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %3
+  %5 = load i32, i32* %4, align 4
+  %6 = getelementptr inbounds [2048 x i32], [2048 x i32]* @c, i64 0, i64 %3
+  %7 = load i32, i32* %6, align 4
   %8 = mul nsw i32 %7, %5
-  %9 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %2
-  %10 = load i32* %9, align 8
-  %11 = getelementptr inbounds [2048 x i32]* @c, i64 0, i64 %2
-  %12 = load i32* %11, align 8
+  %9 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %2
+  %10 = load i32, i32* %9, align 8
+  %11 = getelementptr inbounds [2048 x i32], [2048 x i32]* @c, i64 0, i64 %2
+  %12 = load i32, i32* %11, align 8
   %13 = mul nsw i32 %12, %10
   %14 = sub nsw i32 %8, %13
-  %15 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %15 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
   store i32 %14, i32* %15, align 4
   %16 = mul nsw i32 %7, %10
   %17 = mul nsw i32 %12, %5
   %18 = add nsw i32 %17, %16
-  %19 = getelementptr inbounds [2048 x i32]* @d, i64 0, i64 %indvars.iv
+  %19 = getelementptr inbounds [2048 x i32], [2048 x i32]* @d, i64 0, i64 %indvars.iv
   store i32 %18, i32* %19, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -376,7 +376,7 @@ define void @example12() nounwind uwtable ssp {
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
   %3 = trunc i64 %indvars.iv to i32
   store i32 %3, i32* %2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -388,28 +388,27 @@ define void @example12() nounwind uwtable ssp {
   ret void
 }
 
-; Can't vectorize because of reductions.
 ;CHECK-LABEL: @example13(
-;CHECK-NOT: <4 x i32>
+;CHECK: <4 x i32>
 ;CHECK: ret void
 define void @example13(i32** nocapture %A, i32** nocapture %B, i32* nocapture %out) nounwind uwtable ssp {
   br label %.preheader
 
 .preheader:                                       ; preds = %14, %0
   %indvars.iv4 = phi i64 [ 0, %0 ], [ %indvars.iv.next5, %14 ]
-  %1 = getelementptr inbounds i32** %A, i64 %indvars.iv4
-  %2 = load i32** %1, align 8
-  %3 = getelementptr inbounds i32** %B, i64 %indvars.iv4
-  %4 = load i32** %3, align 8
+  %1 = getelementptr inbounds i32*, i32** %A, i64 %indvars.iv4
+  %2 = load i32*, i32** %1, align 8
+  %3 = getelementptr inbounds i32*, i32** %B, i64 %indvars.iv4
+  %4 = load i32*, i32** %3, align 8
   br label %5
 
 ; <label>:5                                       ; preds = %.preheader, %5
   %indvars.iv = phi i64 [ 0, %.preheader ], [ %indvars.iv.next, %5 ]
   %diff.02 = phi i32 [ 0, %.preheader ], [ %11, %5 ]
-  %6 = getelementptr inbounds i32* %2, i64 %indvars.iv
-  %7 = load i32* %6, align 4
-  %8 = getelementptr inbounds i32* %4, i64 %indvars.iv
-  %9 = load i32* %8, align 4
+  %6 = getelementptr inbounds i32, i32* %2, i64 %indvars.iv
+  %7 = load i32, i32* %6, align 4
+  %8 = getelementptr inbounds i32, i32* %4, i64 %indvars.iv
+  %9 = load i32, i32* %8, align 4
   %10 = add i32 %7, %diff.02
   %11 = sub i32 %10, %9
   %indvars.iv.next = add i64 %indvars.iv, 8
@@ -418,7 +417,7 @@ define void @example13(i32** nocapture %A, i32** nocapture %B, i32* nocapture %o
   br i1 %13, label %5, label %14
 
 ; <label>:14                                      ; preds = %5
-  %15 = getelementptr inbounds i32* %out, i64 %indvars.iv4
+  %15 = getelementptr inbounds i32, i32* %out, i64 %indvars.iv4
   store i32 %11, i32* %15, align 4
   %indvars.iv.next5 = add i64 %indvars.iv4, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next5 to i32
@@ -445,14 +444,14 @@ define void @example14(i32** nocapture %in, i32** nocapture %coeff, i32* nocaptu
 ; <label>:0                                       ; preds = %0, %.preheader
   %indvars.iv = phi i64 [ 0, %.preheader ], [ %indvars.iv.next, %0 ]
   %sum.12 = phi i32 [ %sum.05, %.preheader ], [ %10, %0 ]
-  %1 = getelementptr inbounds i32** %in, i64 %indvars.iv
-  %2 = load i32** %1, align 8
-  %3 = getelementptr inbounds i32* %2, i64 %indvars.iv7
-  %4 = load i32* %3, align 4
-  %5 = getelementptr inbounds i32** %coeff, i64 %indvars.iv
-  %6 = load i32** %5, align 8
-  %7 = getelementptr inbounds i32* %6, i64 %indvars.iv7
-  %8 = load i32* %7, align 4
+  %1 = getelementptr inbounds i32*, i32** %in, i64 %indvars.iv
+  %2 = load i32*, i32** %1, align 8
+  %3 = getelementptr inbounds i32, i32* %2, i64 %indvars.iv7
+  %4 = load i32, i32* %3, align 4
+  %5 = getelementptr inbounds i32*, i32** %coeff, i64 %indvars.iv
+  %6 = load i32*, i32** %5, align 8
+  %7 = getelementptr inbounds i32, i32* %6, i64 %indvars.iv7
+  %8 = load i32, i32* %7, align 4
   %9 = mul nsw i32 %8, %4
   %10 = add nsw i32 %9, %sum.12
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -479,14 +478,14 @@ define void @example14(i32** nocapture %in, i32** nocapture %coeff, i32* nocaptu
   %indvars.iv.1 = phi i64 [ 0, %.preheader.1 ], [ %13, %12 ]
   %sum.12.1 = phi i32 [ %sum.05.1, %.preheader.1 ], [ %23, %12 ]
   %13 = add nsw i64 %indvars.iv.1, 1
-  %14 = getelementptr inbounds i32** %in, i64 %13
-  %15 = load i32** %14, align 8
-  %16 = getelementptr inbounds i32* %15, i64 %indvars.iv7.1
-  %17 = load i32* %16, align 4
-  %18 = getelementptr inbounds i32** %coeff, i64 %indvars.iv.1
-  %19 = load i32** %18, align 8
-  %20 = getelementptr inbounds i32* %19, i64 %indvars.iv7.1
-  %21 = load i32* %20, align 4
+  %14 = getelementptr inbounds i32*, i32** %in, i64 %13
+  %15 = load i32*, i32** %14, align 8
+  %16 = getelementptr inbounds i32, i32* %15, i64 %indvars.iv7.1
+  %17 = load i32, i32* %16, align 4
+  %18 = getelementptr inbounds i32*, i32** %coeff, i64 %indvars.iv.1
+  %19 = load i32*, i32** %18, align 8
+  %20 = getelementptr inbounds i32, i32* %19, i64 %indvars.iv7.1
+  %21 = load i32, i32* %20, align 4
   %22 = mul nsw i32 %21, %17
   %23 = add nsw i32 %22, %sum.12.1
   %lftr.wideiv.1 = trunc i64 %13 to i32
@@ -500,7 +499,7 @@ define void @example14(i32** nocapture %in, i32** nocapture %coeff, i32* nocaptu
   br i1 %exitcond10.1, label %.preheader3.2, label %.preheader.1
 
 .preheader3.2:                                    ; preds = %24
-  %25 = getelementptr inbounds i32* %out, i64 1
+  %25 = getelementptr inbounds i32, i32* %out, i64 1
   store i32 %23, i32* %25, align 4
   br label %.preheader.2
 
@@ -513,14 +512,14 @@ define void @example14(i32** nocapture %in, i32** nocapture %coeff, i32* nocaptu
   %indvars.iv.2 = phi i64 [ 0, %.preheader.2 ], [ %indvars.iv.next.2, %26 ]
   %sum.12.2 = phi i32 [ %sum.05.2, %.preheader.2 ], [ %37, %26 ]
   %27 = add nsw i64 %indvars.iv.2, 2
-  %28 = getelementptr inbounds i32** %in, i64 %27
-  %29 = load i32** %28, align 8
-  %30 = getelementptr inbounds i32* %29, i64 %indvars.iv7.2
-  %31 = load i32* %30, align 4
-  %32 = getelementptr inbounds i32** %coeff, i64 %indvars.iv.2
-  %33 = load i32** %32, align 8
-  %34 = getelementptr inbounds i32* %33, i64 %indvars.iv7.2
-  %35 = load i32* %34, align 4
+  %28 = getelementptr inbounds i32*, i32** %in, i64 %27
+  %29 = load i32*, i32** %28, align 8
+  %30 = getelementptr inbounds i32, i32* %29, i64 %indvars.iv7.2
+  %31 = load i32, i32* %30, align 4
+  %32 = getelementptr inbounds i32*, i32** %coeff, i64 %indvars.iv.2
+  %33 = load i32*, i32** %32, align 8
+  %34 = getelementptr inbounds i32, i32* %33, i64 %indvars.iv7.2
+  %35 = load i32, i32* %34, align 4
   %36 = mul nsw i32 %35, %31
   %37 = add nsw i32 %36, %sum.12.2
   %indvars.iv.next.2 = add i64 %indvars.iv.2, 1
@@ -535,7 +534,7 @@ define void @example14(i32** nocapture %in, i32** nocapture %coeff, i32* nocaptu
   br i1 %exitcond10.2, label %.preheader3.3, label %.preheader.2
 
 .preheader3.3:                                    ; preds = %38
-  %39 = getelementptr inbounds i32* %out, i64 2
+  %39 = getelementptr inbounds i32, i32* %out, i64 2
   store i32 %37, i32* %39, align 4
   br label %.preheader.3
 
@@ -548,14 +547,14 @@ define void @example14(i32** nocapture %in, i32** nocapture %coeff, i32* nocaptu
   %indvars.iv.3 = phi i64 [ 0, %.preheader.3 ], [ %indvars.iv.next.3, %40 ]
   %sum.12.3 = phi i32 [ %sum.05.3, %.preheader.3 ], [ %51, %40 ]
   %41 = add nsw i64 %indvars.iv.3, 3
-  %42 = getelementptr inbounds i32** %in, i64 %41
-  %43 = load i32** %42, align 8
-  %44 = getelementptr inbounds i32* %43, i64 %indvars.iv7.3
-  %45 = load i32* %44, align 4
-  %46 = getelementptr inbounds i32** %coeff, i64 %indvars.iv.3
-  %47 = load i32** %46, align 8
-  %48 = getelementptr inbounds i32* %47, i64 %indvars.iv7.3
-  %49 = load i32* %48, align 4
+  %42 = getelementptr inbounds i32*, i32** %in, i64 %41
+  %43 = load i32*, i32** %42, align 8
+  %44 = getelementptr inbounds i32, i32* %43, i64 %indvars.iv7.3
+  %45 = load i32, i32* %44, align 4
+  %46 = getelementptr inbounds i32*, i32** %coeff, i64 %indvars.iv.3
+  %47 = load i32*, i32** %46, align 8
+  %48 = getelementptr inbounds i32, i32* %47, i64 %indvars.iv7.3
+  %49 = load i32, i32* %48, align 4
   %50 = mul nsw i32 %49, %45
   %51 = add nsw i32 %50, %sum.12.3
   %indvars.iv.next.3 = add i64 %indvars.iv.3, 1
@@ -570,7 +569,7 @@ define void @example14(i32** nocapture %in, i32** nocapture %coeff, i32* nocaptu
   br i1 %exitcond10.3, label %53, label %.preheader.3
 
 ; <label>:53                                      ; preds = %52
-  %54 = getelementptr inbounds i32* %out, i64 3
+  %54 = getelementptr inbounds i32, i32* %out, i64 3
   store i32 %51, i32* %54, align 4
   ret void
 }
@@ -591,8 +590,8 @@ define i32 @example21(i32* nocapture %b, i32 %n) nounwind uwtable readonly ssp {
   %indvars.iv = phi i64 [ %2, %.lr.ph ], [ %indvars.iv.next, %3 ]
   %a.02 = phi i32 [ 0, %.lr.ph ], [ %6, %3 ]
   %indvars.iv.next = add i64 %indvars.iv, -1
-  %4 = getelementptr inbounds i32* %b, i64 %indvars.iv.next
-  %5 = load i32* %4, align 4
+  %4 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv.next
+  %5 = load i32, i32* %4, align 4
   %6 = add nsw i32 %5, %a.02
   %7 = trunc i64 %indvars.iv.next to i32
   %8 = icmp sgt i32 %7, 0
@@ -613,11 +612,11 @@ define void @example23(i16* nocapture %src, i32* nocapture %dst) nounwind uwtabl
   %.04 = phi i16* [ %src, %0 ], [ %2, %1 ]
   %.013 = phi i32* [ %dst, %0 ], [ %6, %1 ]
   %i.02 = phi i32 [ 0, %0 ], [ %7, %1 ]
-  %2 = getelementptr inbounds i16* %.04, i64 1
-  %3 = load i16* %.04, align 2
+  %2 = getelementptr inbounds i16, i16* %.04, i64 1
+  %3 = load i16, i16* %.04, align 2
   %4 = zext i16 %3 to i32
   %5 = shl nuw nsw i32 %4, 7
-  %6 = getelementptr inbounds i32* %.013, i64 1
+  %6 = getelementptr inbounds i32, i32* %.013, i64 1
   store i32 %5, i32* %.013, align 4
   %7 = add nsw i32 %i.02, 1
   %exitcond = icmp eq i32 %7, 256
@@ -635,14 +634,14 @@ define void @example24(i16 signext %x, i16 signext %y) nounwind uwtable ssp {
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds [1024 x float]* @fa, i64 0, i64 %indvars.iv
-  %3 = load float* %2, align 4
-  %4 = getelementptr inbounds [1024 x float]* @fb, i64 0, i64 %indvars.iv
-  %5 = load float* %4, align 4
+  %2 = getelementptr inbounds [1024 x float], [1024 x float]* @fa, i64 0, i64 %indvars.iv
+  %3 = load float, float* %2, align 4
+  %4 = getelementptr inbounds [1024 x float], [1024 x float]* @fb, i64 0, i64 %indvars.iv
+  %5 = load float, float* %4, align 4
   %6 = fcmp olt float %3, %5
   %x.y = select i1 %6, i16 %x, i16 %y
   %7 = sext i16 %x.y to i32
-  %8 = getelementptr inbounds [1024 x i32]* @ic, i64 0, i64 %indvars.iv
+  %8 = getelementptr inbounds [1024 x i32], [1024 x i32]* @ic, i64 0, i64 %indvars.iv
   store i32 %7, i32* %8, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -662,19 +661,19 @@ define void @example25() nounwind uwtable ssp {
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds [1024 x float]* @da, i64 0, i64 %indvars.iv
-  %3 = load float* %2, align 4
-  %4 = getelementptr inbounds [1024 x float]* @db, i64 0, i64 %indvars.iv
-  %5 = load float* %4, align 4
+  %2 = getelementptr inbounds [1024 x float], [1024 x float]* @da, i64 0, i64 %indvars.iv
+  %3 = load float, float* %2, align 4
+  %4 = getelementptr inbounds [1024 x float], [1024 x float]* @db, i64 0, i64 %indvars.iv
+  %5 = load float, float* %4, align 4
   %6 = fcmp olt float %3, %5
-  %7 = getelementptr inbounds [1024 x float]* @dc, i64 0, i64 %indvars.iv
-  %8 = load float* %7, align 4
-  %9 = getelementptr inbounds [1024 x float]* @dd, i64 0, i64 %indvars.iv
-  %10 = load float* %9, align 4
+  %7 = getelementptr inbounds [1024 x float], [1024 x float]* @dc, i64 0, i64 %indvars.iv
+  %8 = load float, float* %7, align 4
+  %9 = getelementptr inbounds [1024 x float], [1024 x float]* @dd, i64 0, i64 %indvars.iv
+  %10 = load float, float* %9, align 4
   %11 = fcmp olt float %8, %10
   %12 = and i1 %6, %11
   %13 = zext i1 %12 to i32
-  %14 = getelementptr inbounds [1024 x i32]* @dj, i64 0, i64 %indvars.iv
+  %14 = getelementptr inbounds [1024 x i32], [1024 x i32]* @dj, i64 0, i64 %indvars.iv
   store i32 %13, i32* %14, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/global_alias.ll b/test/Transforms/LoopVectorize/global_alias.ll
index 3f11ce8bf213..84fa48cd5148 100644
--- a/test/Transforms/LoopVectorize/global_alias.ll
+++ b/test/Transforms/LoopVectorize/global_alias.ll
@@ -35,31 +35,31 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
-  %arrayidx = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %1
-  %2 = load i32* %arrayidx, align 4
-  %3 = load i32* %a.addr, align 4
+  %1 = load i32, i32* %i, align 4
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %1
+  %2 = load i32, i32* %arrayidx, align 4
+  %3 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %2, %3
-  %4 = load i32* %i, align 4
-  %arrayidx1 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %4
+  %4 = load i32, i32* %i, align 4
+  %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %4
   store i32 %add, i32* %arrayidx1, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %5 = load i32* %i, align 4
+  %5 = load i32, i32* %i, align 4
   %inc = add nsw i32 %5, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %6 = load i32* %a.addr, align 4
-  %arrayidx2 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
-  %7 = load i32* %arrayidx2, align 4
+  %6 = load i32, i32* %a.addr, align 4
+  %arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
+  %7 = load i32, i32* %arrayidx2, align 4
   ret i32 %7
 }
 
@@ -83,32 +83,32 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 90
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %add = add nsw i32 %1, 10
-  %arrayidx = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %add
-  %2 = load i32* %arrayidx, align 4
-  %3 = load i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %add
+  %2 = load i32, i32* %arrayidx, align 4
+  %3 = load i32, i32* %a.addr, align 4
   %add1 = add nsw i32 %2, %3
-  %4 = load i32* %i, align 4
-  %arrayidx2 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %4
+  %4 = load i32, i32* %i, align 4
+  %arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %4
   store i32 %add1, i32* %arrayidx2, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %5 = load i32* %i, align 4
+  %5 = load i32, i32* %i, align 4
   %inc = add nsw i32 %5, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %6 = load i32* %a.addr, align 4
-  %arrayidx3 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
-  %7 = load i32* %arrayidx3, align 4
+  %6 = load i32, i32* %a.addr, align 4
+  %arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
+  %7 = load i32, i32* %arrayidx3, align 4
   ret i32 %7
 }
 
@@ -132,32 +132,32 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
-  %arrayidx = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %1
-  %2 = load i32* %arrayidx, align 4
-  %3 = load i32* %a.addr, align 4
+  %1 = load i32, i32* %i, align 4
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %1
+  %2 = load i32, i32* %arrayidx, align 4
+  %3 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %2, %3
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %add1 = add nsw i32 %4, 10
-  %arrayidx2 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %add1
+  %arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %add1
   store i32 %add, i32* %arrayidx2, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %5 = load i32* %i, align 4
+  %5 = load i32, i32* %i, align 4
   %inc = add nsw i32 %5, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %6 = load i32* %a.addr, align 4
-  %arrayidx3 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
-  %7 = load i32* %arrayidx3, align 4
+  %6 = load i32, i32* %a.addr, align 4
+  %arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
+  %7 = load i32, i32* %arrayidx3, align 4
   ret i32 %7
 }
 
@@ -184,34 +184,34 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32** @PB, align 4
-  %2 = load i32* %i, align 4
-  %add.ptr = getelementptr inbounds i32* %1, i32 %2
-  %3 = load i32* %add.ptr, align 4
-  %4 = load i32* %a.addr, align 4
+  %1 = load i32*, i32** @PB, align 4
+  %2 = load i32, i32* %i, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %1, i32 %2
+  %3 = load i32, i32* %add.ptr, align 4
+  %4 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %3, %4
-  %5 = load i32** @PA, align 4
-  %6 = load i32* %i, align 4
-  %add.ptr1 = getelementptr inbounds i32* %5, i32 %6
+  %5 = load i32*, i32** @PA, align 4
+  %6 = load i32, i32* %i, align 4
+  %add.ptr1 = getelementptr inbounds i32, i32* %5, i32 %6
   store i32 %add, i32* %add.ptr1, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %7 = load i32* %i, align 4
+  %7 = load i32, i32* %i, align 4
   %inc = add nsw i32 %7, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %8 = load i32** @PA, align 4
-  %9 = load i32* %a.addr, align 4
-  %add.ptr2 = getelementptr inbounds i32* %8, i32 %9
-  %10 = load i32* %add.ptr2, align 4
+  %8 = load i32*, i32** @PA, align 4
+  %9 = load i32, i32* %a.addr, align 4
+  %add.ptr2 = getelementptr inbounds i32, i32* %8, i32 %9
+  %10 = load i32, i32* %add.ptr2, align 4
   ret i32 %10
 }
 
@@ -237,37 +237,37 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
-  %2 = load i32* %N, align 4
-  %arrayidx = getelementptr inbounds [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0* @Bar, i32 0, i32 2), i32 0, i32 %2
-  %arrayidx1 = getelementptr inbounds [100 x i32]* %arrayidx, i32 0, i32 %1
-  %3 = load i32* %arrayidx1, align 4
-  %4 = load i32* %a.addr, align 4
+  %1 = load i32, i32* %i, align 4
+  %2 = load i32, i32* %N, align 4
+  %arrayidx = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @Bar, i32 0, i32 2), i32 0, i32 %2
+  %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32]* %arrayidx, i32 0, i32 %1
+  %3 = load i32, i32* %arrayidx1, align 4
+  %4 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %3, %4
-  %5 = load i32* %i, align 4
-  %6 = load i32* %N, align 4
-  %arrayidx2 = getelementptr inbounds [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %6
-  %arrayidx3 = getelementptr inbounds [100 x i32]* %arrayidx2, i32 0, i32 %5
+  %5 = load i32, i32* %i, align 4
+  %6 = load i32, i32* %N, align 4
+  %arrayidx2 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %6
+  %arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* %arrayidx2, i32 0, i32 %5
   store i32 %add, i32* %arrayidx3, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %7 = load i32* %i, align 4
+  %7 = load i32, i32* %i, align 4
   %inc = add nsw i32 %7, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %8 = load i32* %a.addr, align 4
-  %9 = load i32* %N, align 4
-  %arrayidx4 = getelementptr inbounds [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %9
-  %arrayidx5 = getelementptr inbounds [100 x i32]* %arrayidx4, i32 0, i32 %8
-  %10 = load i32* %arrayidx5, align 4
+  %8 = load i32, i32* %a.addr, align 4
+  %9 = load i32, i32* %N, align 4
+  %arrayidx4 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %9
+  %arrayidx5 = getelementptr inbounds [100 x i32], [100 x i32]* %arrayidx4, i32 0, i32 %8
+  %10 = load i32, i32* %arrayidx5, align 4
   ret i32 %10
 }
 
@@ -293,38 +293,38 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
-  %2 = load i32* %N, align 4
+  %1 = load i32, i32* %i, align 4
+  %2 = load i32, i32* %N, align 4
   %add = add nsw i32 %2, 1
-  %arrayidx = getelementptr inbounds [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %add
-  %arrayidx1 = getelementptr inbounds [100 x i32]* %arrayidx, i32 0, i32 %1
-  %3 = load i32* %arrayidx1, align 4
-  %4 = load i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %add
+  %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32]* %arrayidx, i32 0, i32 %1
+  %3 = load i32, i32* %arrayidx1, align 4
+  %4 = load i32, i32* %a.addr, align 4
   %add2 = add nsw i32 %3, %4
-  %5 = load i32* %i, align 4
-  %6 = load i32* %N, align 4
-  %arrayidx3 = getelementptr inbounds [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %6
-  %arrayidx4 = getelementptr inbounds [100 x i32]* %arrayidx3, i32 0, i32 %5
+  %5 = load i32, i32* %i, align 4
+  %6 = load i32, i32* %N, align 4
+  %arrayidx3 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %6
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* %arrayidx3, i32 0, i32 %5
   store i32 %add2, i32* %arrayidx4, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %7 = load i32* %i, align 4
+  %7 = load i32, i32* %i, align 4
   %inc = add nsw i32 %7, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %8 = load i32* %a.addr, align 4
-  %9 = load i32* %N, align 4
-  %arrayidx5 = getelementptr inbounds [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %9
-  %arrayidx6 = getelementptr inbounds [100 x i32]* %arrayidx5, i32 0, i32 %8
-  %10 = load i32* %arrayidx6, align 4
+  %8 = load i32, i32* %a.addr, align 4
+  %9 = load i32, i32* %N, align 4
+  %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %9
+  %arrayidx6 = getelementptr inbounds [100 x i32], [100 x i32]* %arrayidx5, i32 0, i32 %8
+  %10 = load i32, i32* %arrayidx6, align 4
   ret i32 %10
 }
 
@@ -347,35 +347,35 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %sub = sub nsw i32 100, %1
   %sub1 = sub nsw i32 %sub, 1
-  %arrayidx = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %sub1
-  %2 = load i32* %arrayidx, align 4
-  %3 = load i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %sub1
+  %2 = load i32, i32* %arrayidx, align 4
+  %3 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %2, %3
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %sub2 = sub nsw i32 100, %4
   %sub3 = sub nsw i32 %sub2, 1
-  %arrayidx4 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %sub3
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %sub3
   store i32 %add, i32* %arrayidx4, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %5 = load i32* %i, align 4
+  %5 = load i32, i32* %i, align 4
   %inc = add nsw i32 %5, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %6 = load i32* %a.addr, align 4
-  %arrayidx5 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
-  %7 = load i32* %arrayidx5, align 4
+  %6 = load i32, i32* %a.addr, align 4
+  %arrayidx5 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
+  %7 = load i32, i32* %arrayidx5, align 4
   ret i32 %7
 }
 
@@ -399,35 +399,35 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 90
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %sub = sub nsw i32 100, %1
   %sub1 = sub nsw i32 %sub, 10
-  %arrayidx = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %sub1
-  %2 = load i32* %arrayidx, align 4
-  %3 = load i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %sub1
+  %2 = load i32, i32* %arrayidx, align 4
+  %3 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %2, %3
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %sub2 = sub nsw i32 100, %4
   %sub3 = sub nsw i32 %sub2, 1
-  %arrayidx4 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %sub3
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %sub3
   store i32 %add, i32* %arrayidx4, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %5 = load i32* %i, align 4
+  %5 = load i32, i32* %i, align 4
   %inc = add nsw i32 %5, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %6 = load i32* %a.addr, align 4
-  %arrayidx5 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
-  %7 = load i32* %arrayidx5, align 4
+  %6 = load i32, i32* %a.addr, align 4
+  %arrayidx5 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
+  %7 = load i32, i32* %arrayidx5, align 4
   ret i32 %7
 }
 
@@ -451,35 +451,35 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %sub = sub nsw i32 100, %1
   %sub1 = sub nsw i32 %sub, 1
-  %arrayidx = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %sub1
-  %2 = load i32* %arrayidx, align 4
-  %3 = load i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %sub1
+  %2 = load i32, i32* %arrayidx, align 4
+  %3 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %2, %3
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %sub2 = sub nsw i32 100, %4
   %sub3 = sub nsw i32 %sub2, 10
-  %arrayidx4 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %sub3
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %sub3
   store i32 %add, i32* %arrayidx4, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %5 = load i32* %i, align 4
+  %5 = load i32, i32* %i, align 4
   %inc = add nsw i32 %5, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %6 = load i32* %a.addr, align 4
-  %arrayidx5 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
-  %7 = load i32* %arrayidx5, align 4
+  %6 = load i32, i32* %a.addr, align 4
+  %arrayidx5 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
+  %7 = load i32, i32* %arrayidx5, align 4
   ret i32 %7
 }
 
@@ -506,40 +506,40 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32** @PB, align 4
-  %add.ptr = getelementptr inbounds i32* %1, i32 100
-  %2 = load i32* %i, align 4
+  %1 = load i32*, i32** @PB, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %1, i32 100
+  %2 = load i32, i32* %i, align 4
   %idx.neg = sub i32 0, %2
-  %add.ptr1 = getelementptr inbounds i32* %add.ptr, i32 %idx.neg
-  %add.ptr2 = getelementptr inbounds i32* %add.ptr1, i32 -1
-  %3 = load i32* %add.ptr2, align 4
-  %4 = load i32* %a.addr, align 4
+  %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 %idx.neg
+  %add.ptr2 = getelementptr inbounds i32, i32* %add.ptr1, i32 -1
+  %3 = load i32, i32* %add.ptr2, align 4
+  %4 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %3, %4
-  %5 = load i32** @PA, align 4
-  %add.ptr3 = getelementptr inbounds i32* %5, i32 100
-  %6 = load i32* %i, align 4
+  %5 = load i32*, i32** @PA, align 4
+  %add.ptr3 = getelementptr inbounds i32, i32* %5, i32 100
+  %6 = load i32, i32* %i, align 4
   %idx.neg4 = sub i32 0, %6
-  %add.ptr5 = getelementptr inbounds i32* %add.ptr3, i32 %idx.neg4
-  %add.ptr6 = getelementptr inbounds i32* %add.ptr5, i32 -1
+  %add.ptr5 = getelementptr inbounds i32, i32* %add.ptr3, i32 %idx.neg4
+  %add.ptr6 = getelementptr inbounds i32, i32* %add.ptr5, i32 -1
   store i32 %add, i32* %add.ptr6, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %7 = load i32* %i, align 4
+  %7 = load i32, i32* %i, align 4
   %inc = add nsw i32 %7, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %8 = load i32** @PA, align 4
-  %9 = load i32* %a.addr, align 4
-  %add.ptr7 = getelementptr inbounds i32* %8, i32 %9
-  %10 = load i32* %add.ptr7, align 4
+  %8 = load i32*, i32** @PA, align 4
+  %9 = load i32, i32* %a.addr, align 4
+  %add.ptr7 = getelementptr inbounds i32, i32* %8, i32 %9
+  %10 = load i32, i32* %add.ptr7, align 4
   ret i32 %10
 }
 
@@ -565,41 +565,41 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %sub = sub nsw i32 100, %1
   %sub1 = sub nsw i32 %sub, 1
-  %2 = load i32* %N, align 4
-  %arrayidx = getelementptr inbounds [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0* @Bar, i32 0, i32 2), i32 0, i32 %2
-  %arrayidx2 = getelementptr inbounds [100 x i32]* %arrayidx, i32 0, i32 %sub1
-  %3 = load i32* %arrayidx2, align 4
-  %4 = load i32* %a.addr, align 4
+  %2 = load i32, i32* %N, align 4
+  %arrayidx = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @Bar, i32 0, i32 2), i32 0, i32 %2
+  %arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32]* %arrayidx, i32 0, i32 %sub1
+  %3 = load i32, i32* %arrayidx2, align 4
+  %4 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %3, %4
-  %5 = load i32* %i, align 4
+  %5 = load i32, i32* %i, align 4
   %sub3 = sub nsw i32 100, %5
   %sub4 = sub nsw i32 %sub3, 1
-  %6 = load i32* %N, align 4
-  %arrayidx5 = getelementptr inbounds [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %6
-  %arrayidx6 = getelementptr inbounds [100 x i32]* %arrayidx5, i32 0, i32 %sub4
+  %6 = load i32, i32* %N, align 4
+  %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %6
+  %arrayidx6 = getelementptr inbounds [100 x i32], [100 x i32]* %arrayidx5, i32 0, i32 %sub4
   store i32 %add, i32* %arrayidx6, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %7 = load i32* %i, align 4
+  %7 = load i32, i32* %i, align 4
   %inc = add nsw i32 %7, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %8 = load i32* %a.addr, align 4
-  %9 = load i32* %N, align 4
-  %arrayidx7 = getelementptr inbounds [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %9
-  %arrayidx8 = getelementptr inbounds [100 x i32]* %arrayidx7, i32 0, i32 %8
-  %10 = load i32* %arrayidx8, align 4
+  %8 = load i32, i32* %a.addr, align 4
+  %9 = load i32, i32* %N, align 4
+  %arrayidx7 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %9
+  %arrayidx8 = getelementptr inbounds [100 x i32], [100 x i32]* %arrayidx7, i32 0, i32 %8
+  %10 = load i32, i32* %arrayidx8, align 4
   ret i32 %10
 }
 
@@ -625,42 +625,42 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %sub = sub nsw i32 100, %1
   %sub1 = sub nsw i32 %sub, 1
-  %2 = load i32* %N, align 4
+  %2 = load i32, i32* %N, align 4
   %add = add nsw i32 %2, 1
-  %arrayidx = getelementptr inbounds [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %add
-  %arrayidx2 = getelementptr inbounds [100 x i32]* %arrayidx, i32 0, i32 %sub1
-  %3 = load i32* %arrayidx2, align 4
-  %4 = load i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %add
+  %arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32]* %arrayidx, i32 0, i32 %sub1
+  %3 = load i32, i32* %arrayidx2, align 4
+  %4 = load i32, i32* %a.addr, align 4
   %add3 = add nsw i32 %3, %4
-  %5 = load i32* %i, align 4
+  %5 = load i32, i32* %i, align 4
   %sub4 = sub nsw i32 100, %5
   %sub5 = sub nsw i32 %sub4, 1
-  %6 = load i32* %N, align 4
-  %arrayidx6 = getelementptr inbounds [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %6
-  %arrayidx7 = getelementptr inbounds [100 x i32]* %arrayidx6, i32 0, i32 %sub5
+  %6 = load i32, i32* %N, align 4
+  %arrayidx6 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %6
+  %arrayidx7 = getelementptr inbounds [100 x i32], [100 x i32]* %arrayidx6, i32 0, i32 %sub5
   store i32 %add3, i32* %arrayidx7, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %7 = load i32* %i, align 4
+  %7 = load i32, i32* %i, align 4
   %inc = add nsw i32 %7, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %8 = load i32* %a.addr, align 4
-  %9 = load i32* %N, align 4
-  %arrayidx8 = getelementptr inbounds [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %9
-  %arrayidx9 = getelementptr inbounds [100 x i32]* %arrayidx8, i32 0, i32 %8
-  %10 = load i32* %arrayidx9, align 4
+  %8 = load i32, i32* %a.addr, align 4
+  %9 = load i32, i32* %N, align 4
+  %arrayidx8 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @Bar, i32 0, i32 0), i32 0, i32 %9
+  %arrayidx9 = getelementptr inbounds [100 x i32], [100 x i32]* %arrayidx8, i32 0, i32 %8
+  %10 = load i32, i32* %arrayidx9, align 4
   ret i32 %10
 }
 
@@ -684,32 +684,32 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %add = add nsw i32 %1, 4
-  %arrayidx = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %add
-  %2 = load i32* %arrayidx, align 4
-  %3 = load i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %add
+  %2 = load i32, i32* %arrayidx, align 4
+  %3 = load i32, i32* %a.addr, align 4
   %add1 = add nsw i32 %2, %3
-  %4 = load i32* %i, align 4
-  %arrayidx2 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %4
+  %4 = load i32, i32* %i, align 4
+  %arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %4
   store i32 %add1, i32* %arrayidx2, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %5 = load i32* %i, align 4
+  %5 = load i32, i32* %i, align 4
   %inc = add nsw i32 %5, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %6 = load i32* %a.addr, align 4
-  %arrayidx3 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
-  %7 = load i32* %arrayidx3, align 4
+  %6 = load i32, i32* %a.addr, align 4
+  %arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
+  %7 = load i32, i32* %arrayidx3, align 4
   ret i32 %7
 }
 
@@ -733,35 +733,35 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %sub = sub nsw i32 100, %1
   %sub1 = sub nsw i32 %sub, 5
-  %arrayidx = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %sub1
-  %2 = load i32* %arrayidx, align 4
-  %3 = load i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %sub1
+  %2 = load i32, i32* %arrayidx, align 4
+  %3 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %2, %3
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %sub2 = sub nsw i32 100, %4
   %sub3 = sub nsw i32 %sub2, 1
-  %arrayidx4 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %sub3
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %sub3
   store i32 %add, i32* %arrayidx4, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %5 = load i32* %i, align 4
+  %5 = load i32, i32* %i, align 4
   %inc = add nsw i32 %5, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %6 = load i32* %a.addr, align 4
-  %arrayidx5 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
-  %7 = load i32* %arrayidx5, align 4
+  %6 = load i32, i32* %a.addr, align 4
+  %arrayidx5 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
+  %7 = load i32, i32* %arrayidx5, align 4
   ret i32 %7
 }
 
@@ -789,33 +789,33 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %sub = sub nsw i32 100, %1
   %sub1 = sub nsw i32 %sub, 1
-  %arrayidx = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %sub1
-  %2 = load i32* %arrayidx, align 4
-  %3 = load i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %sub1
+  %2 = load i32, i32* %arrayidx, align 4
+  %3 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %2, %3
-  %4 = load i32* %i, align 4
-  %arrayidx2 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %4
+  %4 = load i32, i32* %i, align 4
+  %arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %4
   store i32 %add, i32* %arrayidx2, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %5 = load i32* %i, align 4
+  %5 = load i32, i32* %i, align 4
   %inc = add nsw i32 %5, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %6 = load i32* %a.addr, align 4
-  %arrayidx3 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
-  %7 = load i32* %arrayidx3, align 4
+  %6 = load i32, i32* %a.addr, align 4
+  %arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
+  %7 = load i32, i32* %arrayidx3, align 4
   ret i32 %7
 }
 
@@ -839,33 +839,33 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
-  %arrayidx = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %1
-  %2 = load i32* %arrayidx, align 4
-  %3 = load i32* %a.addr, align 4
+  %1 = load i32, i32* %i, align 4
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %1
+  %2 = load i32, i32* %arrayidx, align 4
+  %3 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %2, %3
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %sub = sub nsw i32 100, %4
   %sub1 = sub nsw i32 %sub, 1
-  %arrayidx2 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %sub1
+  %arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %sub1
   store i32 %add, i32* %arrayidx2, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %5 = load i32* %i, align 4
+  %5 = load i32, i32* %i, align 4
   %inc = add nsw i32 %5, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %6 = load i32* %a.addr, align 4
-  %arrayidx3 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
-  %7 = load i32* %arrayidx3, align 4
+  %6 = load i32, i32* %a.addr, align 4
+  %arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
+  %7 = load i32, i32* %arrayidx3, align 4
   ret i32 %7
 }
 
@@ -889,37 +889,37 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32** @PB, align 4
-  %add.ptr = getelementptr inbounds i32* %1, i32 100
-  %2 = load i32* %i, align 4
+  %1 = load i32*, i32** @PB, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %1, i32 100
+  %2 = load i32, i32* %i, align 4
   %idx.neg = sub i32 0, %2
-  %add.ptr1 = getelementptr inbounds i32* %add.ptr, i32 %idx.neg
-  %add.ptr2 = getelementptr inbounds i32* %add.ptr1, i32 -1
-  %3 = load i32* %add.ptr2, align 4
-  %4 = load i32* %a.addr, align 4
+  %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 %idx.neg
+  %add.ptr2 = getelementptr inbounds i32, i32* %add.ptr1, i32 -1
+  %3 = load i32, i32* %add.ptr2, align 4
+  %4 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %3, %4
-  %5 = load i32** @PA, align 4
-  %6 = load i32* %i, align 4
-  %add.ptr3 = getelementptr inbounds i32* %5, i32 %6
+  %5 = load i32*, i32** @PA, align 4
+  %6 = load i32, i32* %i, align 4
+  %add.ptr3 = getelementptr inbounds i32, i32* %5, i32 %6
   store i32 %add, i32* %add.ptr3, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %7 = load i32* %i, align 4
+  %7 = load i32, i32* %i, align 4
   %inc = add nsw i32 %7, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %8 = load i32** @PA, align 4
-  %9 = load i32* %a.addr, align 4
-  %add.ptr4 = getelementptr inbounds i32* %8, i32 %9
-  %10 = load i32* %add.ptr4, align 4
+  %8 = load i32*, i32** @PA, align 4
+  %9 = load i32, i32* %a.addr, align 4
+  %add.ptr4 = getelementptr inbounds i32, i32* %8, i32 %9
+  %10 = load i32, i32* %add.ptr4, align 4
   ret i32 %10
 }
 
@@ -946,34 +946,34 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %sub = sub nsw i32 100, %1
   %sub1 = sub nsw i32 %sub, 1
-  %arrayidx = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %sub1
-  %2 = load i32* %arrayidx, align 4
-  %3 = load i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %sub1
+  %2 = load i32, i32* %arrayidx, align 4
+  %3 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %2, %3
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %add2 = add nsw i32 %4, 10
-  %arrayidx3 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %add2
+  %arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %add2
   store i32 %add, i32* %arrayidx3, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %5 = load i32* %i, align 4
+  %5 = load i32, i32* %i, align 4
   %inc = add nsw i32 %5, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %6 = load i32* %a.addr, align 4
-  %arrayidx4 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
-  %7 = load i32* %arrayidx4, align 4
+  %6 = load i32, i32* %a.addr, align 4
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
+  %7 = load i32, i32* %arrayidx4, align 4
   ret i32 %7
 }
 
@@ -996,33 +996,33 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %sub = sub nsw i32 100, %1
   %sub1 = sub nsw i32 %sub, 10
-  %arrayidx = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %sub1
-  %2 = load i32* %arrayidx, align 4
-  %3 = load i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %sub1
+  %2 = load i32, i32* %arrayidx, align 4
+  %3 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %2, %3
-  %4 = load i32* %i, align 4
-  %arrayidx2 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %4
+  %4 = load i32, i32* %i, align 4
+  %arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %4
   store i32 %add, i32* %arrayidx2, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %5 = load i32* %i, align 4
+  %5 = load i32, i32* %i, align 4
   %inc = add nsw i32 %5, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %6 = load i32* %a.addr, align 4
-  %arrayidx3 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
-  %7 = load i32* %arrayidx3, align 4
+  %6 = load i32, i32* %a.addr, align 4
+  %arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
+  %7 = load i32, i32* %arrayidx3, align 4
   ret i32 %7
 }
 
@@ -1045,33 +1045,33 @@ entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc, %entry
-  %0 = load i32* %i, align 4
+  %0 = load i32, i32* %i, align 4
   %cmp = icmp slt i32 %0, 100
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-  %1 = load i32* %i, align 4
+  %1 = load i32, i32* %i, align 4
   %sub = sub nsw i32 100, %1
   %sub1 = sub nsw i32 %sub, 10
-  %arrayidx = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %sub1
-  %2 = load i32* %arrayidx, align 4
-  %3 = load i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 2), i32 0, i32 %sub1
+  %2 = load i32, i32* %arrayidx, align 4
+  %3 = load i32, i32* %a.addr, align 4
   %add = add nsw i32 %2, %3
-  %4 = load i32* %i, align 4
+  %4 = load i32, i32* %i, align 4
   %add2 = add nsw i32 %4, 10
-  %arrayidx3 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %add2
+  %arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %add2
   store i32 %add, i32* %arrayidx3, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
-  %5 = load i32* %i, align 4
+  %5 = load i32, i32* %i, align 4
   %inc = add nsw i32 %5, 1
   store i32 %inc, i32* %i, align 4
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %6 = load i32* %a.addr, align 4
-  %arrayidx4 = getelementptr inbounds [100 x i32]* getelementptr inbounds (%struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
-  %7 = load i32* %arrayidx4, align 4
+  %6 = load i32, i32* %a.addr, align 4
+  %arrayidx4 = getelementptr inbounds [100 x i32], [100 x i32]* getelementptr inbounds (%struct.anon, %struct.anon* @Foo, i32 0, i32 0), i32 0, i32 %6
+  %7 = load i32, i32* %arrayidx4, align 4
   ret i32 %7
 }
diff --git a/test/Transforms/LoopVectorize/hoist-loads.ll b/test/Transforms/LoopVectorize/hoist-loads.ll
index d0b27f1eae7c..a20b0f6cdf37 100644
--- a/test/Transforms/LoopVectorize/hoist-loads.ll
+++ b/test/Transforms/LoopVectorize/hoist-loads.ll
@@ -14,14 +14,14 @@ entry:
   br label %for.body
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end9 ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @A, i64 0, i64 %indvars.iv
-  %arrayidx2 = getelementptr inbounds [1024 x float]* @B, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @A, i64 0, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds [1024 x float], [1024 x float]* @B, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx2, align 4
   %cmp3 = fcmp oeq float %0, 0.000000e+00
   br i1 %cmp3, label %if.end9, label %if.else
 
 if.else:
-  %1 = load float* %arrayidx, align 4
+  %1 = load float, float* %arrayidx, align 4
   br label %if.end9
 
 if.end9:
@@ -46,14 +46,14 @@ entry:
   br label %for.body
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end9 ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @A, i64 0, i64 %indvars.iv
-  %arrayidx2 = getelementptr inbounds [1024 x float]* @B, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @A, i64 0, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds [1024 x float], [1024 x float]* @B, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx2, align 4
   %cmp3 = fcmp oeq float %0, 0.000000e+00
   br i1 %cmp3, label %if.end9, label %if.else
 
 if.else:
-  %1 = load float* %arrayidx, align 4
+  %1 = load float, float* %arrayidx, align 4
   br label %if.end9
 
 if.end9:
diff --git a/test/Transforms/LoopVectorize/i8-induction.ll b/test/Transforms/LoopVectorize/i8-induction.ll
index 90e3ec00cde2..d9e8a430be18 100644
--- a/test/Transforms/LoopVectorize/i8-induction.ll
+++ b/test/Transforms/LoopVectorize/i8-induction.ll
@@ -9,7 +9,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 define void @f() nounwind uwtable ssp {
 scalar.ph:
   store i8 0, i8* inttoptr (i64 1 to i8*), align 1
-  %0 = load i8* @a, align 1
+  %0 = load i8, i8* @a, align 1
   br label %for.body
 
 for.body:
diff --git a/test/Transforms/LoopVectorize/if-conversion-edgemasks.ll b/test/Transforms/LoopVectorize/if-conversion-edgemasks.ll
index 27c274d557eb..8d435f513537 100644
--- a/test/Transforms/LoopVectorize/if-conversion-edgemasks.ll
+++ b/test/Transforms/LoopVectorize/if-conversion-edgemasks.ll
@@ -20,12 +20,15 @@ entry:
   br i1 %cmp88, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:
-  %0 = load i32** @b, align 8  %1 = load i32** @a, align 8  %2 = load i32** @c, align 8  br label %for.body
+  %0 = load i32*, i32** @b, align 8
+  %1 = load i32*, i32** @a, align 8
+  %2 = load i32*, i32** @c, align 8
+  br label %for.body
 
 for.body:
   %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %_ZL3fn3ii.exit58 ]
-  %arrayidx = getelementptr inbounds i32* %0, i64 %indvars.iv
-  %3 = load i32* %arrayidx, align 4  %4 = trunc i64 %indvars.iv to i32
+  %arrayidx = getelementptr inbounds i32, i32* %0, i64 %indvars.iv
+  %3 = load i32, i32* %arrayidx, align 4  %4 = trunc i64 %indvars.iv to i32
   %and.i = and i32 %4, 1
   %tobool.i.i = icmp eq i32 %and.i, 0
   br i1 %tobool.i.i, label %if.end.i, label %if.then.i
@@ -131,9 +134,9 @@ if.then.i15.i:
 
 _ZL3fn3ii.exit:
   %p1.addr.0.i16.i = phi i32 [ %or.i14.i, %if.then.i15.i ], [ %p1.addr.3.i.i, %_Z3fn2iii.exit.i ]
-  %arrayidx2 = getelementptr inbounds i32* %1, i64 %indvars.iv
-  store i32 %p1.addr.0.i16.i, i32* %arrayidx2, align 4  %arrayidx4 = getelementptr inbounds i32* %0, i64 %indvars.iv
-  %10 = load i32* %arrayidx4, align 4  br i1 %tobool.i.i, label %_Z3fn1ii.exit.i26, label %if.then.i.i21
+  %arrayidx2 = getelementptr inbounds i32, i32* %1, i64 %indvars.iv
+  store i32 %p1.addr.0.i16.i, i32* %arrayidx2, align 4  %arrayidx4 = getelementptr inbounds i32, i32* %0, i64 %indvars.iv
+  %10 = load i32, i32* %arrayidx4, align 4  br i1 %tobool.i.i, label %_Z3fn1ii.exit.i26, label %if.then.i.i21
 
 if.then.i.i21:
   %and.i.i18 = lshr i32 %10, 2
@@ -229,7 +232,7 @@ if.then.i15.i56:
 
 _ZL3fn3ii.exit58:
   %p1.addr.0.i16.i57 = phi i32 [ %or.i14.i55, %if.then.i15.i56 ], [ %p1.addr.3.i.i50, %_Z3fn2iii.exit.i52 ]
-  %arrayidx7 = getelementptr inbounds i32* %2, i64 %indvars.iv
+  %arrayidx7 = getelementptr inbounds i32, i32* %2, i64 %indvars.iv
   store i32 %p1.addr.0.i16.i57, i32* %arrayidx7, align 4  %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
   %exitcond = icmp ne i32 %lftr.wideiv, %p1
diff --git a/test/Transforms/LoopVectorize/if-conversion-nest.ll b/test/Transforms/LoopVectorize/if-conversion-nest.ll
index b5ac8fca23b3..3a581ebf847e 100644
--- a/test/Transforms/LoopVectorize/if-conversion-nest.ll
+++ b/test/Transforms/LoopVectorize/if-conversion-nest.ll
@@ -19,10 +19,10 @@ entry:
 
 for.body:
   %indvars.iv = phi i64 [ %indvars.iv.next, %if.end14 ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds i32* %B, i64 %indvars.iv
-  %1 = load i32* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx2, align 4
   %cmp3 = icmp sgt i32 %0, %1
   br i1 %cmp3, label %if.then, label %if.end14
 
diff --git a/test/Transforms/LoopVectorize/if-conversion-reduction.ll b/test/Transforms/LoopVectorize/if-conversion-reduction.ll
index 455699c78030..20333b94345f 100644
--- a/test/Transforms/LoopVectorize/if-conversion-reduction.ll
+++ b/test/Transforms/LoopVectorize/if-conversion-reduction.ll
@@ -14,8 +14,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.inc
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
   %sum.011 = phi i32 [ %sum.1, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %0, 30
   br i1 %cmp1, label %if.then, label %for.inc
 
diff --git a/test/Transforms/LoopVectorize/if-conversion.ll b/test/Transforms/LoopVectorize/if-conversion.ll
index 9e185284919a..fb5416976525 100644
--- a/test/Transforms/LoopVectorize/if-conversion.ll
+++ b/test/Transforms/LoopVectorize/if-conversion.ll
@@ -19,9 +19,9 @@ target triple = "x86_64-apple-macosx10.9.0"
 
 ;CHECK-LABEL: @function0(
 ;CHECK: load <4 x i32>
-;CHECK: icmp sgt <4 x i32>
 ;CHECK: mul <4 x i32>
 ;CHECK: add <4 x i32>
+;CHECK: icmp sle <4 x i32>
 ;CHECK: select <4 x i1>
 ;CHECK: ret i32
 define i32 @function0(i32* nocapture %a, i32* nocapture %b, i32 %start, i32 %end) nounwind uwtable ssp {
@@ -35,10 +35,10 @@ for.body.lr.ph:
 
 for.body:
   %indvars.iv = phi i64 [ %0, %for.body.lr.ph ], [ %indvars.iv.next, %if.end ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %1 = load i32* %arrayidx, align 4
-  %arrayidx4 = getelementptr inbounds i32* %b, i64 %indvars.iv
-  %2 = load i32* %arrayidx4, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx4, align 4
   %cmp5 = icmp sgt i32 %1, %2
   br i1 %cmp5, label %if.then, label %if.end
 
@@ -72,8 +72,8 @@ for.end:
 
 ;CHECK-LABEL: @reduction_func(
 ;CHECK: load <4 x i32>
-;CHECK: icmp sgt <4 x i32>
 ;CHECK: add <4 x i32>
+;CHECK: icmp sle <4 x i32>
 ;CHECK: select <4 x i1>
 ;CHECK: ret i32
 define i32 @reduction_func(i32* nocapture %A, i32 %n) nounwind uwtable readonly ssp {
@@ -84,8 +84,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.inc
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
   %sum.011 = phi i32 [ %sum.1, %for.inc ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %0, 30
   br i1 %cmp1, label %if.then, label %for.inc
 
@@ -123,13 +123,13 @@ entry:
 for.body:
   %inc3 = phi i32 [ 0, %entry ], [ %inc, %cond.end ]
   %or2 = phi i32 [ 0, %entry ], [ %or, %cond.end ]
-  br i1 icmp eq (i32** getelementptr inbounds ([1 x i32*]* @a, i64 0, i64 0), i32** @c), label %cond.false, label %cond.end
+  br i1 icmp eq (i32** getelementptr inbounds ([1 x i32*], [1 x i32*]* @a, i64 0, i64 0), i32** @c), label %cond.false, label %cond.end
 
 cond.false:
   br label %cond.end
 
 cond.end:
-  %cond = phi i32 [ sdiv (i32 1, i32 zext (i1 icmp eq (i32** getelementptr inbounds ([1 x i32*]* @a, i64 0, i64 0), i32** @c) to i32)), %cond.false ], [ 0, %for.body ]
+  %cond = phi i32 [ sdiv (i32 1, i32 zext (i1 icmp eq (i32** getelementptr inbounds ([1 x i32*], [1 x i32*]* @a, i64 0, i64 0), i32** @c) to i32)), %cond.false ], [ 0, %for.body ]
   %or = or i32 %or2, %cond
   %inc = add nsw i32 %inc3, 1
   %cmp = icmp slt i32 %inc, 128
@@ -153,10 +153,10 @@ entry:
 for.body:
   %inc3 = phi i32 [ 0, %entry ], [ %inc, %cond.end ]
   %or2 = phi i32 [ 0, %entry ], [ %or, %cond.end ]
-  br i1 icmp eq (i32** getelementptr inbounds ([1 x i32*]* @a, i64 0, i64 0), i32** @c), label %cond.false, label %cond.end
+  br i1 icmp eq (i32** getelementptr inbounds ([1 x i32*], [1 x i32*]* @a, i64 0, i64 0), i32** @c), label %cond.false, label %cond.end
 
 cond.false:
-  %cond.1 = or i32 %inc3, sdiv (i32 1, i32 zext (i1 icmp eq (i32** getelementptr inbounds ([1 x i32*]* @a, i64 0, i64 1), i32** @c) to i32))
+  %cond.1 = or i32 %inc3, sdiv (i32 1, i32 zext (i1 icmp eq (i32** getelementptr inbounds ([1 x i32*], [1 x i32*]* @a, i64 0, i64 1), i32** @c) to i32))
   br label %cond.end
 
 cond.end:
diff --git a/test/Transforms/LoopVectorize/if-pred-stores.ll b/test/Transforms/LoopVectorize/if-pred-stores.ll
index c6067e01ee21..991d027ada5c 100644
--- a/test/Transforms/LoopVectorize/if-pred-stores.ll
+++ b/test/Transforms/LoopVectorize/if-pred-stores.ll
@@ -39,10 +39,10 @@ entry:
 ; UNROLL: vector.body:
 ; UNROLL:   %[[IND:[a-zA-Z0-9]+]] = add i64 %{{.*}}, 0
 ; UNROLL:   %[[IND1:[a-zA-Z0-9]+]] = add i64 %{{.*}}, 1
-; UNROLL:   %[[v0:[a-zA-Z0-9]+]] = getelementptr inbounds i32* %f, i64 %[[IND]]
-; UNROLL:   %[[v1:[a-zA-Z0-9]+]] = getelementptr inbounds i32* %f, i64 %[[IND1]]
-; UNROLL:   %[[v2:[a-zA-Z0-9]+]] = load i32* %[[v0]], align 4
-; UNROLL:   %[[v3:[a-zA-Z0-9]+]] = load i32* %[[v1]], align 4
+; UNROLL:   %[[v0:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND]]
+; UNROLL:   %[[v1:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND1]]
+; UNROLL:   %[[v2:[a-zA-Z0-9]+]] = load i32, i32* %[[v0]], align 4
+; UNROLL:   %[[v3:[a-zA-Z0-9]+]] = load i32, i32* %[[v1]], align 4
 ; UNROLL:   %[[v4:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v2]], 100
 ; UNROLL:   %[[v5:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v3]], 100
 ; UNROLL:   %[[v6:[a-zA-Z0-9]+]] = add nsw i32 %[[v2]], 20
@@ -66,8 +66,8 @@ entry:
 
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ]
-  %arrayidx = getelementptr inbounds i32* %f, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %f, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp1 = icmp sgt i32 %0, 100
   br i1 %cmp1, label %if.then, label %for.inc
 
@@ -104,8 +104,8 @@ for.body9:
 for.body14:
   %indvars.iv3 = phi i64 [ %indvars.iv.next4, %for.inc23 ], [ undef, %for.body9 ]
   %iNewChunks.120 = phi i32 [ %iNewChunks.2, %for.inc23 ], [ undef, %for.body9 ]
-  %arrayidx16 = getelementptr inbounds [768 x i32]* undef, i64 0, i64 %indvars.iv3
-  %tmp = load i32* %arrayidx16, align 4
+  %arrayidx16 = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 %indvars.iv3
+  %tmp = load i32, i32* %arrayidx16, align 4
   br i1 undef, label %if.then18, label %for.inc23
 
 if.then18:
diff --git a/test/Transforms/LoopVectorize/incorrect-dom-info.ll b/test/Transforms/LoopVectorize/incorrect-dom-info.ll
index b8624fd00774..798793a641bc 100644
--- a/test/Transforms/LoopVectorize/incorrect-dom-info.ll
+++ b/test/Transforms/LoopVectorize/incorrect-dom-info.ll
@@ -45,7 +45,7 @@ thread-pre-split.preheader:                       ; preds = %9
 
 .thread-pre-split.loopexit_crit_edge:             ; preds = %19
   %scevgep.sum = xor i64 %umax, -1
-  %scevgep45 = getelementptr i8* %d.020, i64 %scevgep.sum
+  %scevgep45 = getelementptr i8, i8* %d.020, i64 %scevgep.sum
   br label %thread-pre-split.loopexit
 
 thread-pre-split.loopexit:                        ; preds = %11, %.thread-pre-split.loopexit_crit_edge
@@ -58,8 +58,8 @@ thread-pre-split.loopexit:                        ; preds = %11, %.thread-pre-sp
   br i1 undef, label %11, label %22
 
 ; <label>:11                                      ; preds = %.lr.ph21
-  %12 = getelementptr inbounds [0 x i8]* @PL_utf8skip, i64 0, i64 undef
-  %13 = load i8* %12, align 1
+  %12 = getelementptr inbounds [0 x i8], [0 x i8]* @PL_utf8skip, i64 0, i64 undef
+  %13 = load i8, i8* %12, align 1
   %14 = zext i8 %13 to i64
   %15 = icmp ugt i64 %14, %10
   %. = select i1 %15, i64 %10, i64 %14
@@ -91,7 +91,7 @@ thread-pre-split.loopexit:                        ; preds = %11, %.thread-pre-sp
   br label %26
 
 ; <label>:26                                      ; preds = %25, %24, %23, %22
-  %27 = load i64* %len, align 8
+  %27 = load i64, i64* %len, align 8
   %28 = add i64 %27, -1
   br i1 undef, label %thread-pre-split._crit_edge, label %.lr.ph21
 
diff --git a/test/Transforms/LoopVectorize/increment.ll b/test/Transforms/LoopVectorize/increment.ll
index 067a76b51ad0..d0b25096e37a 100644
--- a/test/Transforms/LoopVectorize/increment.ll
+++ b/test/Transforms/LoopVectorize/increment.ll
@@ -20,8 +20,8 @@ define void @inc(i32 %n) nounwind uwtable noinline ssp {
 
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
-  %3 = load i32* %2, align 4
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
   %4 = trunc i64 %indvars.iv to i32
   %5 = add nsw i32 %3, %4
   store i32 %5, i32* %2, align 4
@@ -49,11 +49,11 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %B, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %idxprom1 = sext i32 %0 to i64
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %idxprom1
-  %1 = load i32* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %idxprom1
+  %1 = load i32, i32* %arrayidx2, align 4
   %inc = add nsw i32 %1, 1
   store i32 %inc, i32* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/induction.ll b/test/Transforms/LoopVectorize/induction.ll
index 3f3491835b54..2fbb2de797ae 100644
--- a/test/Transforms/LoopVectorize/induction.ll
+++ b/test/Transforms/LoopVectorize/induction.ll
@@ -16,7 +16,7 @@ for.body.lr.ph:
 for.body:
   %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]
   %count.09 = phi i32 [ 190, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
   store i32 %count.09, i32* %arrayidx2, align 4
   %inc = add nsw i32 %count.09, 1
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -51,11 +51,11 @@ entry:
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %ind.sum = add i64 %iv, %offset
-  %arr.idx = getelementptr inbounds float* %a, i64 %ind.sum
-  %l1 = load float* %arr.idx, align 4
+  %arr.idx = getelementptr inbounds float, float* %a, i64 %ind.sum
+  %l1 = load float, float* %arr.idx, align 4
   %ind.sum2 = add i64 %iv, %offset2
-  %arr.idx2 = getelementptr inbounds float* %a, i64 %ind.sum2
-  %l2 = load float* %arr.idx2, align 4
+  %arr.idx2 = getelementptr inbounds float, float* %a, i64 %ind.sum2
+  %l2 = load float, float* %arr.idx2, align 4
   %m = fmul fast float %b, %l2
   %ad = fadd fast float %l1, %m
   store float %ad, float* %arr.idx, align 4
@@ -153,9 +153,9 @@ define i32 @max_i32_backedgetaken() nounwind readnone ssp uwtable {
 @c = common global i32 0, align 4
 define i32 @testoverflowcheck() {
 entry:
-  %.pr.i = load i8* @e, align 1
-  %0 = load i32* @d, align 4
-  %c.promoted.i = load i32* @c, align 4
+  %.pr.i = load i8, i8* @e, align 1
+  %0 = load i32, i32* @d, align 4
+  %c.promoted.i = load i32, i32* @c, align 4
   br label %cond.end.i
 
 cond.end.i:
diff --git a/test/Transforms/LoopVectorize/induction_plus.ll b/test/Transforms/LoopVectorize/induction_plus.ll
index ce64c5b620d5..7c4c8f2edcbf 100644
--- a/test/Transforms/LoopVectorize/induction_plus.ll
+++ b/test/Transforms/LoopVectorize/induction_plus.ll
@@ -16,7 +16,7 @@ define i32 @array_at_plus_one(i32 %n) nounwind uwtable ssp {
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
   %2 = add nsw i64 %indvars.iv, 12
-  %3 = getelementptr inbounds [1024 x i32]* @array, i64 0, i64 %2
+  %3 = getelementptr inbounds [1024 x i32], [1024 x i32]* @array, i64 0, i64 %2
   %4 = trunc i64 %indvars.iv to i32
   store i32 %4, i32* %3, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/intrinsic.ll b/test/Transforms/LoopVectorize/intrinsic.ll
index d48731a07436..fae6a8cb714b 100644
--- a/test/Transforms/LoopVectorize/intrinsic.ll
+++ b/test/Transforms/LoopVectorize/intrinsic.ll
@@ -13,10 +13,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.sqrt.f32(float %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -39,10 +39,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.sqrt.f64(double %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -65,10 +65,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.sin.f32(float %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -91,10 +91,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.sin.f64(double %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -117,10 +117,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.cos.f32(float %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -143,10 +143,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.cos.f64(double %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -169,10 +169,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.exp.f32(float %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -195,10 +195,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.exp.f64(double %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -221,10 +221,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.exp2.f32(float %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -247,10 +247,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.exp2.f64(double %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -273,10 +273,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.log.f32(float %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -299,10 +299,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.log.f64(double %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -325,10 +325,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.log10.f32(float %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -351,10 +351,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.log10.f64(double %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -377,10 +377,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.log2.f32(float %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -403,10 +403,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.log2.f64(double %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -429,10 +429,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.fabs.f32(float %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -452,10 +452,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.fabs(double %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -478,12 +478,12 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds float* %z, i64 %indvars.iv
-  %1 = load float* %arrayidx1, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx1 = getelementptr inbounds float, float* %z, i64 %indvars.iv
+  %1 = load float, float* %arrayidx1, align 4
   %call = tail call float @llvm.copysign.f32(float %0, float %1) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -503,12 +503,12 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
-  %arrayidx1 = getelementptr inbounds double* %z, i64 %indvars.iv
-  %1 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
+  %arrayidx1 = getelementptr inbounds double, double* %z, i64 %indvars.iv
+  %1 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.copysign(double %0, double %1) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -531,10 +531,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.floor.f32(float %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -557,10 +557,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.floor.f64(double %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -583,10 +583,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.ceil.f32(float %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -609,10 +609,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.ceil.f64(double %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -635,10 +635,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.trunc.f32(float %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -661,10 +661,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.trunc.f64(double %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -687,10 +687,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.rint.f32(float %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -713,10 +713,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.rint.f64(double %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -739,10 +739,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.nearbyint.f32(float %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -765,10 +765,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.nearbyint.f64(double %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -791,10 +791,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.round.f32(float %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -817,10 +817,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.round.f64(double %0) nounwind readnone
-  %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx2, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -843,14 +843,14 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds float* %w, i64 %indvars.iv
-  %1 = load float* %arrayidx2, align 4
-  %arrayidx4 = getelementptr inbounds float* %z, i64 %indvars.iv
-  %2 = load float* %arrayidx4, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %w, i64 %indvars.iv
+  %1 = load float, float* %arrayidx2, align 4
+  %arrayidx4 = getelementptr inbounds float, float* %z, i64 %indvars.iv
+  %2 = load float, float* %arrayidx4, align 4
   %3 = tail call float @llvm.fma.f32(float %0, float %2, float %1)
-  %arrayidx6 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx6 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %3, float* %arrayidx6, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -873,14 +873,14 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
-  %arrayidx2 = getelementptr inbounds double* %w, i64 %indvars.iv
-  %1 = load double* %arrayidx2, align 8
-  %arrayidx4 = getelementptr inbounds double* %z, i64 %indvars.iv
-  %2 = load double* %arrayidx4, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %w, i64 %indvars.iv
+  %1 = load double, double* %arrayidx2, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %z, i64 %indvars.iv
+  %2 = load double, double* %arrayidx4, align 8
   %3 = tail call double @llvm.fma.f64(double %0, double %2, double %1)
-  %arrayidx6 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx6 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %3, double* %arrayidx6, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -903,14 +903,14 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds float* %w, i64 %indvars.iv
-  %1 = load float* %arrayidx2, align 4
-  %arrayidx4 = getelementptr inbounds float* %z, i64 %indvars.iv
-  %2 = load float* %arrayidx4, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %w, i64 %indvars.iv
+  %1 = load float, float* %arrayidx2, align 4
+  %arrayidx4 = getelementptr inbounds float, float* %z, i64 %indvars.iv
+  %2 = load float, float* %arrayidx4, align 4
   %3 = tail call float @llvm.fmuladd.f32(float %0, float %2, float %1)
-  %arrayidx6 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx6 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %3, float* %arrayidx6, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -933,14 +933,14 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
-  %arrayidx2 = getelementptr inbounds double* %w, i64 %indvars.iv
-  %1 = load double* %arrayidx2, align 8
-  %arrayidx4 = getelementptr inbounds double* %z, i64 %indvars.iv
-  %2 = load double* %arrayidx4, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %w, i64 %indvars.iv
+  %1 = load double, double* %arrayidx2, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %z, i64 %indvars.iv
+  %2 = load double, double* %arrayidx4, align 8
   %3 = tail call double @llvm.fmuladd.f64(double %0, double %2, double %1)
-  %arrayidx6 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx6 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %3, double* %arrayidx6, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -963,12 +963,12 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds float* %z, i64 %indvars.iv
-  %1 = load float* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %z, i64 %indvars.iv
+  %1 = load float, float* %arrayidx2, align 4
   %call = tail call float @llvm.pow.f32(float %0, float %1) nounwind readnone
-  %arrayidx4 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx4, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -991,12 +991,12 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
-  %arrayidx2 = getelementptr inbounds double* %z, i64 %indvars.iv
-  %1 = load double* %arrayidx2, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %z, i64 %indvars.iv
+  %1 = load double, double* %arrayidx2, align 8
   %call = tail call double @llvm.pow.f64(double %0, double %1) nounwind readnone
-  %arrayidx4 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx4, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -1016,8 +1016,8 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds float* %x, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @fabsf(float %0) nounwind readnone
   store float %call, float* %arrayidx, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -1050,8 +1050,8 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds float* %x, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %x, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %call = tail call float @roundf(float %0) nounwind readnone
   store float %call, float* %arrayidx, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -1077,8 +1077,8 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds double* %x, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds double, double* %x, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 4
   store double %0, double* %arrayidx, align 4
   tail call void @round(double %0) nounwind readnone
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -1102,10 +1102,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %call = tail call double @llvm.powi.f64(double %0, i32  %P) nounwind readnone
-  %arrayidx4 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx4, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -1126,11 +1126,11 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 8
   %1 = trunc i64 %indvars.iv to i32
   %call = tail call double @llvm.powi.f64(double %0, i32  %1) nounwind readnone
-  %arrayidx4 = getelementptr inbounds double* %x, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx4, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -1153,10 +1153,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i64* %y, i64 %indvars.iv
-  %0 = load i64* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds i64, i64* %y, i64 %indvars.iv
+  %0 = load i64, i64* %arrayidx, align 8
   %call = tail call i64 @llvm.cttz.i64(i64 %0, i1 true) nounwind readnone
-  %arrayidx4 = getelementptr inbounds i64* %x, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds i64, i64* %x, i64 %indvars.iv
   store i64 %call, i64* %arrayidx4, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -1179,10 +1179,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i64* %y, i64 %indvars.iv
-  %0 = load i64* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds i64, i64* %y, i64 %indvars.iv
+  %0 = load i64, i64* %arrayidx, align 8
   %call = tail call i64 @llvm.ctlz.i64(i64 %0, i1 true) nounwind readnone
-  %arrayidx4 = getelementptr inbounds i64* %x, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds i64, i64* %x, i64 %indvars.iv
   store i64 %call, i64* %arrayidx4, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -1205,12 +1205,12 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds float* %z, i64 %indvars.iv
-  %1 = load float* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %z, i64 %indvars.iv
+  %1 = load float, float* %arrayidx2, align 4
   %call = tail call float @llvm.minnum.f32(float %0, float %1) nounwind readnone
-  %arrayidx4 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx4, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -1233,12 +1233,12 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds float* %z, i64 %indvars.iv
-  %1 = load float* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %z, i64 %indvars.iv
+  %1 = load float, float* %arrayidx2, align 4
   %call = tail call float @llvm.maxnum.f32(float %0, float %1) nounwind readnone
-  %arrayidx4 = getelementptr inbounds float* %x, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds float, float* %x, i64 %indvars.iv
   store float %call, float* %arrayidx4, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/lifetime.ll b/test/Transforms/LoopVectorize/lifetime.ll
index ba36cc4f7aa4..6e525ca1d822 100644
--- a/test/Transforms/LoopVectorize/lifetime.ll
+++ b/test/Transforms/LoopVectorize/lifetime.ll
@@ -19,8 +19,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   call void @llvm.lifetime.end(i64 4096, i8* %0) #1
-  %arrayidx = getelementptr inbounds i32* %d, i64 %indvars.iv
-  %1 = load i32* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds i32, i32* %d, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx, align 8
   store i32 100, i32* %arrayidx, align 8
   call void @llvm.lifetime.start(i64 4096, i8* %0) #1
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -49,8 +49,8 @@ for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %1 = bitcast [1024 x i32]* %arr to i8*
   call void @llvm.lifetime.end(i64 4096, i8* %1) #1
-  %arrayidx = getelementptr inbounds i32* %d, i64 %indvars.iv
-  %2 = load i32* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds i32, i32* %d, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx, align 8
   store i32 100, i32* %arrayidx, align 8
   call void @llvm.lifetime.start(i64 4096, i8* %1) #1
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -75,11 +75,11 @@ entry:
 
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %0 = getelementptr [1024 x i32]* %arr, i32 0, i64 %indvars.iv
+  %0 = getelementptr [1024 x i32], [1024 x i32]* %arr, i32 0, i64 %indvars.iv
   %1 = bitcast [1024 x i32]* %arr to i8*
   call void @llvm.lifetime.end(i64 4096, i8* %1) #1
-  %arrayidx = getelementptr inbounds i32* %d, i64 %indvars.iv
-  %2 = load i32* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds i32, i32* %d, i64 %indvars.iv
+  %2 = load i32, i32* %arrayidx, align 8
   store i32 100, i32* %arrayidx, align 8
   call void @llvm.lifetime.start(i64 4096, i8* %1) #1
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/loop-form.ll b/test/Transforms/LoopVectorize/loop-form.ll
index 138df1d96138..3bbe8100e34e 100644
--- a/test/Transforms/LoopVectorize/loop-form.ll
+++ b/test/Transforms/LoopVectorize/loop-form.ll
@@ -21,7 +21,7 @@ for.cond:
 
 for.body:
   %iprom = sext i32 %i to i64
-  %b = getelementptr inbounds %struct.X* undef, i64 %iprom, i32 1
+  %b = getelementptr inbounds %struct.X, %struct.X* undef, i64 %iprom, i32 1
   store i16 0, i16* %b, align 4
   %inc = add nsw i32 %i, 1
   br label %for.cond
diff --git a/test/Transforms/LoopVectorize/loop-vect-memdep.ll b/test/Transforms/LoopVectorize/loop-vect-memdep.ll
index e2c7524238d1..d9efaa5c085f 100644
--- a/test/Transforms/LoopVectorize/loop-vect-memdep.ll
+++ b/test/Transforms/LoopVectorize/loop-vect-memdep.ll
@@ -6,16 +6,16 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 
 define void @test_loop_novect(double** %arr, i64 %n) {
 for.body.lr.ph:
-  %t = load double** %arr, align 8
+  %t = load double*, double** %arr, align 8
   br label %for.body
 
 for.body:                                      ; preds = %for.body, %for.body.lr.ph
   %i = phi i64 [ 0, %for.body.lr.ph ], [ %i.next, %for.body ]
-  %a = getelementptr inbounds double* %t, i64 %i
+  %a = getelementptr inbounds double, double* %t, i64 %i
   %i.next = add nuw nsw i64 %i, 1
-  %a.next = getelementptr inbounds double* %t, i64 %i.next
-  %t1 = load double* %a, align 8
-  %t2 = load double* %a.next, align 8
+  %a.next = getelementptr inbounds double, double* %t, i64 %i.next
+  %t1 = load double, double* %a, align 8
+  %t2 = load double, double* %a.next, align 8
   store double %t1, double* %a.next, align 8
   store double %t2, double* %a, align 8
   %c = icmp eq i64 %i, %n
diff --git a/test/Transforms/LoopVectorize/memdep.ll b/test/Transforms/LoopVectorize/memdep.ll
index f857e800bea7..fb608836dfef 100644
--- a/test/Transforms/LoopVectorize/memdep.ll
+++ b/test/Transforms/LoopVectorize/memdep.ll
@@ -19,10 +19,10 @@ entry:
 for.body:
   %indvars.iv = phi i32 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %indvars.iv.next = add i32 %indvars.iv, 1
-  %arrayidx = getelementptr inbounds i32* %A, i32 %indvars.iv.next
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i32 %indvars.iv.next
+  %0 = load i32, i32* %arrayidx, align 4
   %add1 = add nsw i32 %0, 1
-  %arrayidx3 = getelementptr inbounds i32* %A, i32 %indvars.iv
+  %arrayidx3 = getelementptr inbounds i32, i32* %A, i32 %indvars.iv
   store i32 %add1, i32* %arrayidx3, align 4
   %exitcond = icmp ne i32 %indvars.iv.next, 1024
   br i1 %exitcond, label %for.body, label %for.end
@@ -44,11 +44,11 @@ entry:
 
 for.body:
   %indvars.iv = phi i32 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %A, i32 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i32 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, 1
   %indvars.iv.next = add i32 %indvars.iv, 1
-  %arrayidx3 = getelementptr inbounds i32* %A, i32 %indvars.iv.next
+  %arrayidx3 = getelementptr inbounds i32, i32* %A, i32 %indvars.iv.next
   store i32 %add, i32* %arrayidx3, align 4
   %exitcond = icmp ne i32 %indvars.iv.next, 1024
   br i1 %exitcond, label %for.body, label %for.end
@@ -74,12 +74,12 @@ entry:
 for.body:
   %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %idxprom = sext i32 %i.01 to i64
-  %arrayidx = getelementptr inbounds i32* %A, i64 %idxprom
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %idxprom
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, 1
   %add1 = add nsw i32 %i.01, 2
   %idxprom2 = sext i32 %add1 to i64
-  %arrayidx3 = getelementptr inbounds i32* %A, i64 %idxprom2
+  %arrayidx3 = getelementptr inbounds i32, i32* %A, i64 %idxprom2
   store i32 %add, i32* %arrayidx3, align 4
   %inc = add nsw i32 %i.01, 1
   %cmp = icmp slt i32 %inc, 1024
@@ -105,13 +105,13 @@ entry:
 
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds i32* %B, i64 %indvars.iv
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
   store i32 %0, i32* %arrayidx2, align 4
   %indvars.iv.next = add nsw i64 %indvars.iv, 1
-  %arrayidx4 = getelementptr inbounds i32* %B, i64 %indvars.iv.next
-  %1 = load i32* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %B, i64 %indvars.iv.next
+  %1 = load i32, i32* %arrayidx4, align 4
   store i32 %1, i32* %arrayidx, align 4
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
   %exitcond = icmp ne i32 %lftr.wideiv, 1024
@@ -138,10 +138,10 @@ for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %tmp.addr.08 = phi i32 [ %tmp, %entry ], [ %0, %for.body ]
   %indvars.iv.next = add nsw i64 %indvars.iv, 1
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv.next
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv.next
   store i32 %tmp.addr.08, i32* %arrayidx, align 4
-  %arrayidx3 = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx3, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx3, align 4
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
   %exitcond = icmp ne i32 %lftr.wideiv, 1024
   br i1 %exitcond, label %for.body, label %for.end
@@ -169,13 +169,13 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 16, %entry ], [ %indvars.iv.next, %for.body ]
   %0 = add nsw i64 %indvars.iv, -3
-  %arrayidx = getelementptr inbounds i32* %A, i64 %0
-  %1 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %0
+  %1 = load i32, i32* %arrayidx, align 4
   %2 = add nsw i64 %indvars.iv, 4
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %2
-  %3 = load i32* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %2
+  %3 = load i32, i32* %arrayidx2, align 4
   %add3 = add nsw i32 %3, %1
-  %arrayidx5 = getelementptr inbounds i32* %A, i64 %indvars.iv
+  %arrayidx5 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
   store i32 %add3, i32* %arrayidx5, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -203,14 +203,14 @@ entry:
 
 for.body:
   %indvars.iv = phi i64 [ 16, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %B, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %indvars.iv
+  %arrayidx = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
   store i32 %0, i32* %arrayidx2, align 4
   %1 = add nsw i64 %indvars.iv, -3
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 %1
-  %2 = load i32* %arrayidx4, align 4
-  %arrayidx6 = getelementptr inbounds i32* %C, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 %1
+  %2 = load i32, i32* %arrayidx4, align 4
+  %arrayidx6 = getelementptr inbounds i32, i32* %C, i64 %indvars.iv
   store i32 %2, i32* %arrayidx6, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/metadata-unroll.ll b/test/Transforms/LoopVectorize/metadata-unroll.ll
index 36a231454f08..3c80ae0cb54f 100644
--- a/test/Transforms/LoopVectorize/metadata-unroll.ll
+++ b/test/Transforms/LoopVectorize/metadata-unroll.ll
@@ -23,8 +23,8 @@ define void @inc(i32 %n) nounwind uwtable noinline ssp {
 
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
-  %3 = load i32* %2, align 4
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
   %4 = trunc i64 %indvars.iv to i32
   %5 = add nsw i32 %3, %4
   store i32 %5, i32* %2, align 4
diff --git a/test/Transforms/LoopVectorize/metadata-width.ll b/test/Transforms/LoopVectorize/metadata-width.ll
index dee4feedd6b8..69d902fad640 100644
--- a/test/Transforms/LoopVectorize/metadata-width.ll
+++ b/test/Transforms/LoopVectorize/metadata-width.ll
@@ -13,7 +13,7 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
   %0 = trunc i64 %indvars.iv to i32
   store i32 %0, i32* %arrayidx, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/metadata.ll b/test/Transforms/LoopVectorize/metadata.ll
index a258f7c06c07..9a791aedbbe4 100644
--- a/test/Transforms/LoopVectorize/metadata.ll
+++ b/test/Transforms/LoopVectorize/metadata.ll
@@ -9,10 +9,10 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4, !tbaa !0
+  %arrayidx = getelementptr inbounds float, float* %b, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4, !tbaa !0
   %conv = fptosi float %0 to i32
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
   store i32 %conv, i32* %arrayidx2, align 4, !tbaa !4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 1600
@@ -23,7 +23,7 @@ for.end:                                          ; preds = %for.body
 }
 
 ; CHECK-LABEL: @test1
-; CHECK: load <4 x float>* %{{.*}}, align 4, !tbaa ![[TFLT:[0-9]+]]
+; CHECK: load <4 x float>, <4 x float>* %{{.*}}, align 4, !tbaa ![[TFLT:[0-9]+]]
 ; CHECK: store <4 x i32> %{{.*}}, <4 x i32>* %{{.*}}, align 4, !tbaa ![[TINT:[0-9]+]]
 ; CHECK: ret i32 0
 
diff --git a/test/Transforms/LoopVectorize/minmax_reduction.ll b/test/Transforms/LoopVectorize/minmax_reduction.ll
index 1984cdd892d1..5a0356fe11a2 100644
--- a/test/Transforms/LoopVectorize/minmax_reduction.ll
+++ b/test/Transforms/LoopVectorize/minmax_reduction.ll
@@ -26,8 +26,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp3 = icmp sgt i32 %0, %max.red.08
   %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -55,8 +55,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp3 = icmp slt i32 %max.red.08, %0
   %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -83,8 +83,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp3 = icmp slt i32 %0, %max.red.08
   %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -112,8 +112,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp3 = icmp sgt i32 %max.red.08, %0
   %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -142,8 +142,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp3 = icmp ugt i32 %0, %max.red.08
   %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -171,8 +171,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp3 = icmp ult i32 %max.red.08, %0
   %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -199,8 +199,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp3 = icmp ult i32 %0, %max.red.08
   %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -228,8 +228,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp3 = icmp ugt i32 %max.red.08, %0
   %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -257,8 +257,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp3 = icmp sge i32 %0, %max.red.08
   %max.red.0 = select i1 %cmp3, i32 %max.red.08, i32 %0
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -286,8 +286,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp3 = icmp sle i32 %0, %max.red.08
   %max.red.0 = select i1 %cmp3, i32 %max.red.08, i32 %0
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -315,8 +315,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp3 = icmp uge i32 %0, %max.red.08
   %max.red.0 = select i1 %cmp3, i32 %max.red.08, i32 %0
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -344,8 +344,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %cmp3 = icmp ule i32 %0, %max.red.08
   %max.red.0 = select i1 %cmp3, i32 %max.red.08, i32 %0
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -367,10 +367,10 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv
-  %arrayidx1 = getelementptr inbounds [1024 x i32]* @A, i64 1, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
-  %1 = load i32* %arrayidx1, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv
+  %arrayidx1 = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 1, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %1 = load i32, i32* %arrayidx1, align 4
   %cmp3 = icmp sgt i32 %0, %1
   %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -391,10 +391,10 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv
-  %arrayidx1 = getelementptr inbounds [1024 x i32]* @A, i64 1, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
-  %1 = load i32* %arrayidx1, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvars.iv
+  %arrayidx1 = getelementptr inbounds [1024 x i32], [1024 x i32]* @A, i64 1, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %1 = load i32, i32* %arrayidx1, align 4
   %cmp3 = icmp sgt i32 %0, %max.red.08
   %max.red.0 = select i1 %cmp3, i32 %0, i32 %1
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -425,8 +425,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp ogt float %0, %max.red.08
   %max.red.0 = select i1 %cmp3, float %0, float %max.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -451,8 +451,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp oge float %0, %max.red.08
   %max.red.0 = select i1 %cmp3, float %0, float %max.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -477,8 +477,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp olt float %0, %max.red.08
   %max.red.0 = select i1 %cmp3, float %max.red.08, float %0
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -503,8 +503,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp ole float %0, %max.red.08
   %max.red.0 = select i1 %cmp3, float %max.red.08, float %0
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -529,8 +529,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp ugt float %0, %max.red.08
   %max.red.0 = select i1 %cmp3, float %0, float %max.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -555,8 +555,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp uge float %0, %max.red.08
   %max.red.0 = select i1 %cmp3, float %0, float %max.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -581,8 +581,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp ult float %0, %max.red.08
   %max.red.0 = select i1 %cmp3, float %max.red.08, float %0
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -607,8 +607,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp ule float %0, %max.red.08
   %max.red.0 = select i1 %cmp3, float %max.red.08, float %0
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -636,8 +636,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp olt float %0, %min.red.08
   %min.red.0 = select i1 %cmp3, float %0, float %min.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -662,8 +662,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp ole float %0, %min.red.08
   %min.red.0 = select i1 %cmp3, float %0, float %min.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -688,8 +688,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp ogt float %0, %min.red.08
   %min.red.0 = select i1 %cmp3, float %min.red.08, float %0
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -714,8 +714,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp oge float %0, %min.red.08
   %min.red.0 = select i1 %cmp3, float %min.red.08, float %0
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -740,8 +740,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp ult float %0, %min.red.08
   %min.red.0 = select i1 %cmp3, float %0, float %min.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -766,8 +766,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp ule float %0, %min.red.08
   %min.red.0 = select i1 %cmp3, float %0, float %min.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -792,8 +792,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp ugt float %0, %min.red.08
   %min.red.0 = select i1 %cmp3, float %min.red.08, float %0
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -818,8 +818,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp uge float %0, %min.red.08
   %min.red.0 = select i1 %cmp3, float %min.red.08, float %0
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -845,8 +845,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %min.red.08 = phi double [ %min, %entry ], [ %min.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x double]* @dA, i64 0, i64 %indvars.iv
-  %0 = load double* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x double], [1024 x double]* @dA, i64 0, i64 %indvars.iv
+  %0 = load double, double* %arrayidx, align 4
   %cmp3 = fcmp olt double %0, %min.red.08
   %min.red.0 = select i1 %cmp3, double %0, double %min.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -869,8 +869,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ]
-  %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x float], [1024 x float]* @fA, i64 0, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %cmp3 = fcmp ogt float %0, %max.red.08
   %max.red.0 = select i1 %cmp3, float %0, float %max.red.08
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/multi-use-reduction-bug.ll b/test/Transforms/LoopVectorize/multi-use-reduction-bug.ll
index cd022adc9399..9f7fb39dc7ca 100644
--- a/test/Transforms/LoopVectorize/multi-use-reduction-bug.ll
+++ b/test/Transforms/LoopVectorize/multi-use-reduction-bug.ll
@@ -16,10 +16,10 @@ entry:
   %n = alloca i32, align 4
   %k7 = alloca i32, align 4
   %nf = alloca i32, align 4
-  %0 = load i32* %k7, align 4
+  %0 = load i32, i32* %k7, align 4
   %.neg1 = sub i32 0, %0
-  %n.promoted = load i32* %n, align 4
-  %nf.promoted = load i32* %nf, align 4
+  %n.promoted = load i32, i32* %n, align 4
+  %nf.promoted = load i32, i32* %nf, align 4
   br label %for.body
 
 for.body:
diff --git a/test/Transforms/LoopVectorize/multiple-address-spaces.ll b/test/Transforms/LoopVectorize/multiple-address-spaces.ll
index bb2af1e57ccc..e79c93146b19 100644
--- a/test/Transforms/LoopVectorize/multiple-address-spaces.ll
+++ b/test/Transforms/LoopVectorize/multiple-address-spaces.ll
@@ -27,10 +27,10 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds [40000 x i8] addrspace(1)* @Y, i64 0, i64 %indvars.iv
-  %0 = load i8 addrspace(1)* %arrayidx, align 1
+  %arrayidx = getelementptr inbounds [40000 x i8], [40000 x i8] addrspace(1)* @Y, i64 0, i64 %indvars.iv
+  %0 = load i8, i8 addrspace(1)* %arrayidx, align 1
   %add = add i8 %0, 1
-  %arrayidx3 = getelementptr inbounds [40000 x i8]* @X, i64 0, i64 %indvars.iv
+  %arrayidx3 = getelementptr inbounds [40000 x i8], [40000 x i8]* @X, i64 0, i64 %indvars.iv
   store i8 %add, i8* %arrayidx3, align 1
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/no_array_bounds.ll b/test/Transforms/LoopVectorize/no_array_bounds.ll
index d3bd755e6cf1..f7c7ff7732b9 100644
--- a/test/Transforms/LoopVectorize/no_array_bounds.ll
+++ b/test/Transforms/LoopVectorize/no_array_bounds.ll
@@ -33,11 +33,11 @@ for.body7.preheader:                              ; preds = %for.cond5.preheader
 
 for.body:                                         ; preds = %for.body.preheader, %for.body
   %indvars.iv27 = phi i64 [ %indvars.iv.next28, %for.body ], [ 0, %for.body.preheader ]
-  %arrayidx = getelementptr inbounds i32* %B, i64 %indvars.iv27, !dbg !14
-  %0 = load i32* %arrayidx, align 4, !dbg !14, !tbaa !22
+  %arrayidx = getelementptr inbounds i32, i32* %B, i64 %indvars.iv27, !dbg !14
+  %0 = load i32, i32* %arrayidx, align 4, !dbg !14, !tbaa !22
   %idxprom1 = sext i32 %0 to i64, !dbg !14
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 %idxprom1, !dbg !14
-  %1 = load i32* %arrayidx2, align 4, !dbg !14, !tbaa !22
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %idxprom1, !dbg !14
+  %1 = load i32, i32* %arrayidx2, align 4, !dbg !14, !tbaa !22
   %inc = add nsw i32 %1, 1, !dbg !14
   store i32 %inc, i32* %arrayidx2, align 4, !dbg !14, !tbaa !22
   %indvars.iv.next28 = add nuw nsw i64 %indvars.iv27, 1, !dbg !10
@@ -47,11 +47,11 @@ for.body:                                         ; preds = %for.body.preheader,
 
 for.body7:                                        ; preds = %for.body7.preheader, %for.body7
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body7 ], [ 0, %for.body7.preheader ]
-  %arrayidx9 = getelementptr inbounds i32* %A, i64 %indvars.iv, !dbg !20
-  %2 = load i32* %arrayidx9, align 4, !dbg !20, !tbaa !22
+  %arrayidx9 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv, !dbg !20
+  %2 = load i32, i32* %arrayidx9, align 4, !dbg !20, !tbaa !22
   %idxprom10 = sext i32 %2 to i64, !dbg !20
-  %arrayidx11 = getelementptr inbounds i32* %B, i64 %idxprom10, !dbg !20
-  %3 = load i32* %arrayidx11, align 4, !dbg !20, !tbaa !22
+  %arrayidx11 = getelementptr inbounds i32, i32* %B, i64 %idxprom10, !dbg !20
+  %3 = load i32, i32* %arrayidx11, align 4, !dbg !20, !tbaa !22
   %inc12 = add nsw i32 %3, 1, !dbg !20
   store i32 %inc12, i32* %arrayidx11, align 4, !dbg !20, !tbaa !22
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1, !dbg !16
@@ -72,30 +72,30 @@ attributes #0 = { nounwind }
 !llvm.module.flags = !{!7, !8}
 !llvm.ident = !{!9}
 
-!0 = !{!"0x11\004\00clang version 3.5.0\001\00\000\00\002", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ]
-!1 = !{!"no_array_bounds.cpp", !"."}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0", isOptimized: true, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "no_array_bounds.cpp", directory: ".")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00test\00test\00\001\000\001\000\006\00256\001\002", !1, !5, !6, null, void (i32*, i32*, i32)* @_Z4testPiS_i, null, null, !2} ; [ DW_TAG_subprogram ]
-!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ]
+!4 = !DISubprogram(name: "test", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2, file: !1, scope: !5, type: !6, function: void (i32*, i32*, i32)* @_Z4testPiS_i, variables: !2)
+!5 = !DIFile(filename: "no_array_bounds.cpp", directory: ".")
+!6 = !DISubroutineType(types: !2)
 !7 = !{i32 2, !"Dwarf Version", i32 2}
-!8 = !{i32 2, !"Debug Info Version", i32 2}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
 !9 = !{!"clang version 3.5.0"}
-!10 = !MDLocation(line: 4, column: 8, scope: !11)
-!11 = !{!"0xb\004\003\000", !1, !4} ; [ DW_TAG_lexical_block ]
+!10 = !DILocation(line: 4, column: 8, scope: !11)
+!11 = distinct !DILexicalBlock(line: 4, column: 3, file: !1, scope: !4)
 !12 = !{!12, !13}
 !13 = !{!"llvm.loop.vectorize.enable", i1 true}
-!14 = !MDLocation(line: 5, column: 5, scope: !15)
-!15 = !{!"0xb\004\0036\000", !1, !11} ; [ DW_TAG_lexical_block ]
-!16 = !MDLocation(line: 9, column: 8, scope: !17)
-!17 = !{!"0xb\009\003\000", !1, !4} ; [ DW_TAG_lexical_block ]
+!14 = !DILocation(line: 5, column: 5, scope: !15)
+!15 = distinct !DILexicalBlock(line: 4, column: 36, file: !1, scope: !11)
+!16 = !DILocation(line: 9, column: 8, scope: !17)
+!17 = distinct !DILexicalBlock(line: 9, column: 3, file: !1, scope: !4)
 !18 = !{!18, !13, !19}
 !19 = !{!"llvm.loop.vectorize.width", i32 1}
-!20 = !MDLocation(line: 10, column: 5, scope: !21)
-!21 = !{!"0xb\009\0036\000", !1, !17} ; [ DW_TAG_lexical_block ]
+!20 = !DILocation(line: 10, column: 5, scope: !21)
+!21 = distinct !DILexicalBlock(line: 9, column: 36, file: !1, scope: !17)
 !22 = !{!23, !23, i64 0}
 !23 = !{!"int", !24, i64 0}
 !24 = !{!"omnipotent char", !25, i64 0}
 !25 = !{!"Simple C/C++ TBAA"}
-!26 = !MDLocation(line: 12, column: 1, scope: !4)
+!26 = !DILocation(line: 12, column: 1, scope: !4)
diff --git a/test/Transforms/LoopVectorize/no_idiv_reduction.ll b/test/Transforms/LoopVectorize/no_idiv_reduction.ll
index 5c721a6806d9..bfa48a2529b9 100644
--- a/test/Transforms/LoopVectorize/no_idiv_reduction.ll
+++ b/test/Transforms/LoopVectorize/no_idiv_reduction.ll
@@ -11,8 +11,8 @@ for.body:
   ; CHECK-NOT: sdiv <2 x i32>
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %r.05 = phi i32 [ 80, %entry ], [ %div, %for.body ]
-  %arrayidx = getelementptr inbounds [128 x i32]* @a, i64 0, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [128 x i32], [128 x i32]* @a, i64 0, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %div = sdiv i32 %r.05, %0
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/no_int_induction.ll b/test/Transforms/LoopVectorize/no_int_induction.ll
index 1275915f5e36..7e6b26cd9006 100644
--- a/test/Transforms/LoopVectorize/no_int_induction.ll
+++ b/test/Transforms/LoopVectorize/no_int_induction.ll
@@ -14,16 +14,16 @@ target datalayout = "e-p:64:64:64-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-
 ;CHECK: ret i32
 define i32 @sum_array(i32* %A, i32 %n) nounwind uwtable readonly noinline ssp {
   %1 = sext i32 %n to i64
-  %2 = getelementptr inbounds i32* %A, i64 %1
+  %2 = getelementptr inbounds i32, i32* %A, i64 %1
   %3 = icmp eq i32 %n, 0
   br i1 %3, label %_ZSt10accumulateIPiiET0_T_S2_S1_.exit, label %.lr.ph.i
 
 .lr.ph.i:                                         ; preds = %0, %.lr.ph.i
   %.03.i = phi i32* [ %6, %.lr.ph.i ], [ %A, %0 ]
   %.012.i = phi i32 [ %5, %.lr.ph.i ], [ 0, %0 ]
-  %4 = load i32* %.03.i, align 4
+  %4 = load i32, i32* %.03.i, align 4
   %5 = add nsw i32 %4, %.012.i
-  %6 = getelementptr inbounds i32* %.03.i, i64 1
+  %6 = getelementptr inbounds i32, i32* %.03.i, i64 1
   %7 = icmp eq i32* %6, %2
   br i1 %7, label %_ZSt10accumulateIPiiET0_T_S2_S1_.exit, label %.lr.ph.i
 
@@ -41,16 +41,16 @@ _ZSt10accumulateIPiiET0_T_S2_S1_.exit:            ; preds = %.lr.ph.i, %0
 ;CHECK: ret i32
 define i32 @sum_array_as1(i32 addrspace(1)* %A, i32 %n) nounwind uwtable readonly noinline ssp {
   %1 = sext i32 %n to i64
-  %2 = getelementptr inbounds i32 addrspace(1)* %A, i64 %1
+  %2 = getelementptr inbounds i32, i32 addrspace(1)* %A, i64 %1
   %3 = icmp eq i32 %n, 0
   br i1 %3, label %_ZSt10accumulateIPiiET0_T_S2_S1_.exit, label %.lr.ph.i
 
 .lr.ph.i:                                         ; preds = %0, %.lr.ph.i
   %.03.i = phi i32 addrspace(1)* [ %6, %.lr.ph.i ], [ %A, %0 ]
   %.012.i = phi i32 [ %5, %.lr.ph.i ], [ 0, %0 ]
-  %4 = load i32 addrspace(1)* %.03.i, align 4
+  %4 = load i32, i32 addrspace(1)* %.03.i, align 4
   %5 = add nsw i32 %4, %.012.i
-  %6 = getelementptr inbounds i32 addrspace(1)* %.03.i, i64 1
+  %6 = getelementptr inbounds i32, i32 addrspace(1)* %.03.i, i64 1
   %7 = icmp eq i32 addrspace(1)* %6, %2
   br i1 %7, label %_ZSt10accumulateIPiiET0_T_S2_S1_.exit, label %.lr.ph.i
 
diff --git a/test/Transforms/LoopVectorize/no_outside_user.ll b/test/Transforms/LoopVectorize/no_outside_user.ll
index bcd29c1a439a..7030b6b4df2d 100644
--- a/test/Transforms/LoopVectorize/no_outside_user.ll
+++ b/test/Transforms/LoopVectorize/no_outside_user.ll
@@ -20,7 +20,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 
 define i32 @main()  {
 bb:
-  %b.promoted = load i32* @b, align 4
+  %b.promoted = load i32, i32* @b, align 4
   br label %.lr.ph.i
 
 .lr.ph.i:
@@ -56,7 +56,7 @@ f1.exit.loopexit:
 define i32 @test2()  {
 entry:
   store i32 0, i32* @x1, align 4
-  %0 = load i32* @x0, align 4
+  %0 = load i32, i32* @x0, align 4
   br label %for.cond1.preheader
 
 for.cond1.preheader:
diff --git a/test/Transforms/LoopVectorize/no_switch.ll b/test/Transforms/LoopVectorize/no_switch.ll
index 64aab37592f6..1f139c26d790 100644
--- a/test/Transforms/LoopVectorize/no_switch.ll
+++ b/test/Transforms/LoopVectorize/no_switch.ll
@@ -21,8 +21,8 @@ for.body.preheader:                               ; preds = %entry
 
 for.body:                                         ; preds = %for.body.preheader, %for.inc
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %for.body.preheader ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv, !dbg !14
-  %0 = load i32* %arrayidx, align 4, !dbg !14, !tbaa !16
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv, !dbg !14
+  %0 = load i32, i32* %arrayidx, align 4, !dbg !14, !tbaa !16
   switch i32 %0, label %for.inc [
     i32 0, label %sw.bb
     i32 1, label %sw.bb3
@@ -59,28 +59,28 @@ attributes #0 = { nounwind }
 !llvm.module.flags = !{!7, !8}
 !llvm.ident = !{!9}
 
-!0 = !{!"0x11\004\00clang version 3.5.0\001\00\006\00\002", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [./source.cpp] [DW_LANG_C_plus_plus]
-!1 = !{!"source.cpp", !"."}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0", isOptimized: true, runtimeVersion: 6, emissionKind: 2, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "source.cpp", directory: ".")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00test_switch\00test_switch\00\001\000\001\000\006\00256\001\001", !1, !5, !6, null, void (i32*, i32)* @_Z11test_switchPii, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [test_switch]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [./source.cpp]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "test_switch", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !1, scope: !5, type: !6, function: void (i32*, i32)* @_Z11test_switchPii, variables: !2)
+!5 = !DIFile(filename: "source.cpp", directory: ".")
+!6 = !DISubroutineType(types: !2)
 !7 = !{i32 2, !"Dwarf Version", i32 2}
-!8 = !{i32 2, !"Debug Info Version", i32 2}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
 !9 = !{!"clang version 3.5.0"}
-!10 = !MDLocation(line: 3, column: 8, scope: !11)
-!11 = !{!"0xb\003\003\000", !1, !4} ; [ DW_TAG_lexical_block ]
+!10 = !DILocation(line: 3, column: 8, scope: !11)
+!11 = distinct !DILexicalBlock(line: 3, column: 3, file: !1, scope: !4)
 !12 = !{!12, !13, !13}
 !13 = !{!"llvm.loop.vectorize.enable", i1 true}
-!14 = !MDLocation(line: 4, column: 5, scope: !15)
-!15 = !{!"0xb\003\0036\000", !1, !11} ; [ DW_TAG_lexical_block ]
+!14 = !DILocation(line: 4, column: 5, scope: !15)
+!15 = distinct !DILexicalBlock(line: 3, column: 36, file: !1, scope: !11)
 !16 = !{!17, !17, i64 0}
 !17 = !{!"int", !18, i64 0}
 !18 = !{!"omnipotent char", !19, i64 0}
 !19 = !{!"Simple C/C++ TBAA"}
-!20 = !MDLocation(line: 6, column: 7, scope: !21)
-!21 = !{!"0xb\004\0018\000", !1, !15} ; [ DW_TAG_lexical_block ]
-!22 = !MDLocation(line: 7, column: 5, scope: !21)
-!23 = !MDLocation(line: 9, column: 7, scope: !21)
-!24 = !MDLocation(line: 14, column: 1, scope: !4)
+!20 = !DILocation(line: 6, column: 7, scope: !21)
+!21 = distinct !DILexicalBlock(line: 4, column: 18, file: !1, scope: !15)
+!22 = !DILocation(line: 7, column: 5, scope: !21)
+!23 = !DILocation(line: 9, column: 7, scope: !21)
+!24 = !DILocation(line: 14, column: 1, scope: !4)
diff --git a/test/Transforms/LoopVectorize/nofloat.ll b/test/Transforms/LoopVectorize/nofloat.ll
index e9f4c5f23e08..6956bd9c0b45 100644
--- a/test/Transforms/LoopVectorize/nofloat.ll
+++ b/test/Transforms/LoopVectorize/nofloat.ll
@@ -15,7 +15,7 @@ define void @example12() noimplicitfloat { ;           <--------- "noimplicitflo
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
   %3 = trunc i64 %indvars.iv to i32
   store i32 %3, i32* %2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/non-const-n.ll b/test/Transforms/LoopVectorize/non-const-n.ll
index b03d4f05e16f..9007b1b00fd0 100644
--- a/test/Transforms/LoopVectorize/non-const-n.ll
+++ b/test/Transforms/LoopVectorize/non-const-n.ll
@@ -20,12 +20,12 @@ define void @example1(i32 %n) nounwind uwtable ssp {
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %indvars.iv
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds [2048 x i32]* @c, i64 0, i64 %indvars.iv
-  %5 = load i32* %4, align 4
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds [2048 x i32], [2048 x i32]* @c, i64 0, i64 %indvars.iv
+  %5 = load i32, i32* %4, align 4
   %6 = add nsw i32 %5, %3
-  %7 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %7 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
   store i32 %6, i32* %7, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/nsw-crash.ll b/test/Transforms/LoopVectorize/nsw-crash.ll
index 68d993340bdb..3631f0be6904 100644
--- a/test/Transforms/LoopVectorize/nsw-crash.ll
+++ b/test/Transforms/LoopVectorize/nsw-crash.ll
@@ -13,7 +13,7 @@ while.body.lr.ph:
 
 while.body:
   %it.sroa.0.091 = phi i32* [ undef, %while.body.lr.ph ], [ %incdec.ptr.i, %while.body ]
-  %incdec.ptr.i = getelementptr inbounds i32* %it.sroa.0.091, i64 1
+  %incdec.ptr.i = getelementptr inbounds i32, i32* %it.sroa.0.091, i64 1
   %inc32 = add i32 undef, 1                                        ; <------------- Make sure we don't set NSW flags to the undef.
   %cmp.i11 = icmp eq i32* %incdec.ptr.i, undef
   br i1 %cmp.i11, label %while.end, label %while.body
diff --git a/test/Transforms/LoopVectorize/opt.ll b/test/Transforms/LoopVectorize/opt.ll
index a9be80fbfee6..71b7e1f906b7 100644
--- a/test/Transforms/LoopVectorize/opt.ll
+++ b/test/Transforms/LoopVectorize/opt.ll
@@ -16,8 +16,8 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %red.05 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %red.05
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 255
diff --git a/test/Transforms/LoopVectorize/ptr_loops.ll b/test/Transforms/LoopVectorize/ptr_loops.ll
index 3fb38fe1ef13..bc804133e552 100644
--- a/test/Transforms/LoopVectorize/ptr_loops.ll
+++ b/test/Transforms/LoopVectorize/ptr_loops.ll
@@ -15,14 +15,14 @@ define i32 @_Z5test1v() nounwind uwtable ssp {
   br label %1
 
 ; <label>:1                                       ; preds = %0, %1
-  %p.02 = phi i32* [ getelementptr inbounds ([36 x i32]* @A, i64 0, i64 18), %0 ], [ %4, %1 ]
-  %b.01 = phi i32* [ getelementptr inbounds ([36 x i32]* @B, i64 0, i64 0), %0 ], [ %5, %1 ]
-  %2 = load i32* %b.01, align 4
+  %p.02 = phi i32* [ getelementptr inbounds ([36 x i32], [36 x i32]* @A, i64 0, i64 18), %0 ], [ %4, %1 ]
+  %b.01 = phi i32* [ getelementptr inbounds ([36 x i32], [36 x i32]* @B, i64 0, i64 0), %0 ], [ %5, %1 ]
+  %2 = load i32, i32* %b.01, align 4
   %3 = shl nsw i32 %2, 1
   store i32 %3, i32* %p.02, align 4
-  %4 = getelementptr inbounds i32* %p.02, i64 -1
-  %5 = getelementptr inbounds i32* %b.01, i64 1
-  %6 = icmp eq i32* %4, getelementptr ([36 x i32]* @A, i64 128102389400760775, i64 3)
+  %4 = getelementptr inbounds i32, i32* %p.02, i64 -1
+  %5 = getelementptr inbounds i32, i32* %b.01, i64 1
+  %6 = icmp eq i32* %4, getelementptr ([36 x i32], [36 x i32]* @A, i64 128102389400760775, i64 3)
   br i1 %6, label %7, label %1
 
 ; <label>:7                                       ; preds = %1
@@ -38,13 +38,13 @@ define i32 @_Z5test2v() nounwind uwtable ssp {
   br label %1
 
 ; <label>:1                                       ; preds = %0, %1
-  %p.02 = phi i32* [ getelementptr inbounds ([36 x i32]* @A, i64 0, i64 25), %0 ], [ %3, %1 ]
-  %b.01 = phi i32* [ getelementptr inbounds ([36 x i32]* @B, i64 0, i64 2), %0 ], [ %4, %1 ]
-  %2 = load i32* %b.01, align 4
+  %p.02 = phi i32* [ getelementptr inbounds ([36 x i32], [36 x i32]* @A, i64 0, i64 25), %0 ], [ %3, %1 ]
+  %b.01 = phi i32* [ getelementptr inbounds ([36 x i32], [36 x i32]* @B, i64 0, i64 2), %0 ], [ %4, %1 ]
+  %2 = load i32, i32* %b.01, align 4
   store i32 %2, i32* %p.02, align 4
-  %3 = getelementptr inbounds i32* %p.02, i64 -1
-  %4 = getelementptr inbounds i32* %b.01, i64 1
-  %5 = icmp eq i32* %4, getelementptr inbounds ([36 x i32]* @A, i64 0, i64 18)
+  %3 = getelementptr inbounds i32, i32* %p.02, i64 -1
+  %4 = getelementptr inbounds i32, i32* %b.01, i64 1
+  %5 = icmp eq i32* %4, getelementptr inbounds ([36 x i32], [36 x i32]* @A, i64 0, i64 18)
   br i1 %5, label %6, label %1
 
 ; <label>:6                                       ; preds = %1
@@ -60,13 +60,13 @@ define i32 @_Z5test3v() nounwind uwtable ssp {
   br label %1
 
 ; <label>:1                                       ; preds = %0, %1
-  %p.02 = phi i32* [ getelementptr inbounds ([36 x i32]* @A, i64 0, i64 29), %0 ], [ %3, %1 ]
-  %b.01 = phi i32* [ getelementptr inbounds ([36 x i32]* @B, i64 0, i64 5), %0 ], [ %4, %1 ]
-  %2 = load i32* %b.01, align 4
+  %p.02 = phi i32* [ getelementptr inbounds ([36 x i32], [36 x i32]* @A, i64 0, i64 29), %0 ], [ %3, %1 ]
+  %b.01 = phi i32* [ getelementptr inbounds ([36 x i32], [36 x i32]* @B, i64 0, i64 5), %0 ], [ %4, %1 ]
+  %2 = load i32, i32* %b.01, align 4
   store i32 %2, i32* %p.02, align 4
-  %3 = getelementptr inbounds i32* %p.02, i64 -1
-  %4 = getelementptr inbounds i32* %b.01, i64 1
-  %5 = icmp eq i32* %3, getelementptr ([36 x i32]* @A, i64 128102389400760775, i64 3)
+  %3 = getelementptr inbounds i32, i32* %p.02, i64 -1
+  %4 = getelementptr inbounds i32, i32* %b.01, i64 1
+  %5 = icmp eq i32* %3, getelementptr ([36 x i32], [36 x i32]* @A, i64 128102389400760775, i64 3)
   br i1 %5, label %6, label %1
 
 ; <label>:6                                       ; preds = %1
diff --git a/test/Transforms/LoopVectorize/read-only.ll b/test/Transforms/LoopVectorize/read-only.ll
index 2f7a96a09d22..f81afd6ad348 100644
--- a/test/Transforms/LoopVectorize/read-only.ll
+++ b/test/Transforms/LoopVectorize/read-only.ll
@@ -13,11 +13,11 @@ define i32 @read_only_func(i32* nocapture %A, i32* nocapture %B, i32 %n) nounwin
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
   %sum.02 = phi i32 [ %9, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %3 = load i32* %2, align 4
+  %2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
   %4 = add nsw i64 %indvars.iv, 13
-  %5 = getelementptr inbounds i32* %B, i64 %4
-  %6 = load i32* %5, align 4
+  %5 = getelementptr inbounds i32, i32* %B, i64 %4
+  %6 = load i32, i32* %5, align 4
   %7 = shl i32 %6, 1
   %8 = add i32 %3, %sum.02
   %9 = add i32 %8, %7
diff --git a/test/Transforms/LoopVectorize/reduction.ll b/test/Transforms/LoopVectorize/reduction.ll
index 5e6b7fa332b2..647e58a7e41f 100644
--- a/test/Transforms/LoopVectorize/reduction.ll
+++ b/test/Transforms/LoopVectorize/reduction.ll
@@ -20,10 +20,10 @@ define i32 @reduction_sum(i32 %n, i32* noalias nocapture %A, i32* noalias nocapt
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
   %sum.02 = phi i32 [ %9, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds i32* %B, i64 %indvars.iv
-  %5 = load i32* %4, align 4
+  %2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
+  %5 = load i32, i32* %4, align 4
   %6 = trunc i64 %indvars.iv to i32
   %7 = add i32 %sum.02, %6
   %8 = add i32 %7, %3
@@ -55,10 +55,10 @@ define i32 @reduction_prod(i32 %n, i32* noalias nocapture %A, i32* noalias nocap
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
   %prod.02 = phi i32 [ %9, %.lr.ph ], [ 1, %0 ]
-  %2 = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds i32* %B, i64 %indvars.iv
-  %5 = load i32* %4, align 4
+  %2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
+  %5 = load i32, i32* %4, align 4
   %6 = trunc i64 %indvars.iv to i32
   %7 = mul i32 %prod.02, %6
   %8 = mul i32 %7, %3
@@ -90,10 +90,10 @@ define i32 @reduction_mix(i32 %n, i32* noalias nocapture %A, i32* noalias nocapt
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
   %sum.02 = phi i32 [ %9, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds i32* %B, i64 %indvars.iv
-  %5 = load i32* %4, align 4
+  %2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
+  %5 = load i32, i32* %4, align 4
   %6 = mul nsw i32 %5, %3
   %7 = trunc i64 %indvars.iv to i32
   %8 = add i32 %sum.02, %7
@@ -123,10 +123,10 @@ define i32 @reduction_mul(i32 %n, i32* noalias nocapture %A, i32* noalias nocapt
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
   %sum.02 = phi i32 [ %9, %.lr.ph ], [ 19, %0 ]
-  %2 = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds i32* %B, i64 %indvars.iv
-  %5 = load i32* %4, align 4
+  %2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
+  %5 = load i32, i32* %4, align 4
   %6 = trunc i64 %indvars.iv to i32
   %7 = add i32 %3, %6
   %8 = add i32 %7, %5
@@ -158,10 +158,10 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %sum.09 = phi i32 [ %add, %for.body ], [ 120, %entry ]
-  %arrayidx = getelementptr inbounds i32* %in, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds i32* %coeff, i64 %indvars.iv
-  %1 = load i32* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %in, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %coeff, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx2, align 4
   %mul = mul nsw i32 %1, %0
   %add = add nsw i32 %mul, %sum.09
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -191,10 +191,10 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %result.08 = phi i32 [ %and, %for.body ], [ -1, %entry ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds i32* %B, i64 %indvars.iv
-  %1 = load i32* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx2, align 4
   %add = add nsw i32 %1, %0
   %and = and i32 %add, %result.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -223,10 +223,10 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %result.08 = phi i32 [ %or, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds i32* %B, i64 %indvars.iv
-  %1 = load i32* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx2, align 4
   %add = add nsw i32 %1, %0
   %or = or i32 %add, %result.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -255,10 +255,10 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %result.08 = phi i32 [ %xor, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds i32* %B, i64 %indvars.iv
-  %1 = load i32* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx2, align 4
   %add = add nsw i32 %1, %0
   %xor = xor i32 %add, %result.08
   %indvars.iv.next = add i64 %indvars.iv, 1
@@ -284,8 +284,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %x.05 = phi i32 [ %sub, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %sub = sub nsw i32 %0, %x.05
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -311,8 +311,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %x.05 = phi i32 [ %sub, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %sub = sub nsw i32 %x.05, %0
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -335,10 +335,10 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ]
   %sum.033 = phi float [ %S, %entry ], [ %sum.1, %for.inc ]
-  %arrayidx = getelementptr inbounds float* %A, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds float* %B, i64 %indvars.iv
-  %1 = load float* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds float, float* %A, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %B, i64 %indvars.iv
+  %1 = load float, float* %arrayidx2, align 4
   %cmp3 = fcmp ogt float %0, %1
   br i1 %cmp3, label %if.then, label %for.inc
 
@@ -380,10 +380,10 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ]
   %sum.033 = phi float [ %S, %entry ], [ %sum.1, %for.inc ]
-  %arrayidx = getelementptr inbounds float* %A, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds float* %B, i64 %indvars.iv
-  %1 = load float* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds float, float* %A, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %B, i64 %indvars.iv
+  %1 = load float, float* %arrayidx2, align 4
   %cmp3 = fcmp ogt float %0, %1
   br i1 %cmp3, label %if.then, label %for.inc
 
@@ -427,8 +427,8 @@ for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %sum2.09 = phi float [ 0.000000e+00, %entry ], [ %add1, %for.body ]
   %sum.08 = phi float [ %S, %entry ], [ %add, %for.body ]
-  %arrayidx = getelementptr inbounds float* %B, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %B, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %add = fadd fast float %sum.08, %0
   %add1 = fadd fast float %sum2.09, %add
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/reverse_induction.ll b/test/Transforms/LoopVectorize/reverse_induction.ll
index da02d01706ca..6b63a0d8db6c 100644
--- a/test/Transforms/LoopVectorize/reverse_induction.ll
+++ b/test/Transforms/LoopVectorize/reverse_induction.ll
@@ -18,8 +18,8 @@ for.body:
   %i.06 = phi i32 [ 0, %entry ], [ %inc4, %for.body ]
   %redux5 = phi i32 [ 0, %entry ], [ %inc.redux, %for.body ]
   %add.i = add i64 %add.i7, -1
-  %kind_.i = getelementptr inbounds i32* %ptr, i64 %add.i
-  %tmp.i1 = load i32* %kind_.i, align 4
+  %kind_.i = getelementptr inbounds i32, i32* %ptr, i64 %add.i
+  %tmp.i1 = load i32, i32* %kind_.i, align 4
   %inc.redux = add i32 %tmp.i1, %redux5
   %inc4 = add i32 %i.06, 1
   %exitcond = icmp ne i32 %inc4, 1024
@@ -41,8 +41,8 @@ for.body:
   %i.06 = phi i32 [ 0, %entry ], [ %inc4, %for.body ]
   %redux5 = phi i32 [ 0, %entry ], [ %inc.redux, %for.body ]
   %add.i = add i128 %add.i7, -1
-  %kind_.i = getelementptr inbounds i32* %ptr, i128 %add.i
-  %tmp.i1 = load i32* %kind_.i, align 4
+  %kind_.i = getelementptr inbounds i32, i32* %ptr, i128 %add.i
+  %tmp.i1 = load i32, i32* %kind_.i, align 4
   %inc.redux = add i32 %tmp.i1, %redux5
   %inc4 = add i32 %i.06, 1
   %exitcond = icmp ne i32 %inc4, 1024
@@ -65,8 +65,8 @@ for.body:
   %i.06 = phi i32 [ 0, %entry ], [ %inc4, %for.body ]
   %redux5 = phi i32 [ 0, %entry ], [ %inc.redux, %for.body ]
   %add.i = add i16 %add.i7, -1
-  %kind_.i = getelementptr inbounds i32* %ptr, i16 %add.i
-  %tmp.i1 = load i32* %kind_.i, align 4
+  %kind_.i = getelementptr inbounds i32, i32* %ptr, i16 %add.i
+  %tmp.i1 = load i32, i32* %kind_.i, align 4
   %inc.redux = add i32 %tmp.i1, %redux5
   %inc4 = add i32 %i.06, 1
   %exitcond = icmp ne i32 %inc4, 1024
@@ -97,7 +97,7 @@ loopend:
 ; CHECK: vector.body
 ; CHECK: %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
 ; CHECK: %normalized.idx = sub i64 %index, 0
-; CHECK: %reverse.idx = sub i64 1023, %normalized.idx
+; CHECK: %offset.idx = sub i64 1023, %normalized.idx
 ; CHECK: trunc i64 %index to i8
 
 define void @reverse_forward_induction_i64_i8() {
@@ -109,7 +109,7 @@ while.body:
   %forward_induction.05 = phi i8 [ 0, %entry ], [ %inc, %while.body ]
   %inc = add i8 %forward_induction.05, 1
   %conv = zext i8 %inc to i32
-  %arrayidx = getelementptr inbounds [1024 x i32]* @a, i64 0, i64 %indvars.iv
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @a, i64 0, i64 %indvars.iv
   store i32 %conv, i32* %arrayidx, align 4
   %indvars.iv.next = add i64 %indvars.iv, -1
   %0 = trunc i64 %indvars.iv to i32
@@ -124,7 +124,7 @@ while.end:
 ; CHECK: vector.body:
 ; CHECK:  %index = phi i64 [ 129, %vector.ph ], [ %index.next, %vector.body ]
 ; CHECK:  %normalized.idx = sub i64 %index, 129
-; CHECK:  %reverse.idx = sub i64 1023, %normalized.idx
+; CHECK:  %offset.idx = sub i64 1023, %normalized.idx
 ; CHECK:  trunc i64 %index to i8
 
 define void @reverse_forward_induction_i64_i8_signed() {
@@ -136,7 +136,7 @@ while.body:
   %forward_induction.05 = phi i8 [ -127, %entry ], [ %inc, %while.body ]
   %inc = add i8 %forward_induction.05, 1
   %conv = sext i8 %inc to i32
-  %arrayidx = getelementptr inbounds [1024 x i32]* @a, i64 0, i64 %indvars.iv
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @a, i64 0, i64 %indvars.iv
   store i32 %conv, i32* %arrayidx, align 4
   %indvars.iv.next = add i64 %indvars.iv, -1
   %0 = trunc i64 %indvars.iv to i32
diff --git a/test/Transforms/LoopVectorize/reverse_iter.ll b/test/Transforms/LoopVectorize/reverse_iter.ll
index 13172bb17aeb..5bbc769a20aa 100644
--- a/test/Transforms/LoopVectorize/reverse_iter.ll
+++ b/test/Transforms/LoopVectorize/reverse_iter.ll
@@ -30,8 +30,8 @@ define i32 @foo(i32 %n, i32* nocapture %A) {
   %4 = trunc i64 %indvars.iv to i32
   %5 = shl nsw i32 %4, 1
   %6 = sext i32 %5 to i64
-  %7 = getelementptr inbounds i32* %A, i64 %6
-  %8 = load i32* %7, align 4
+  %7 = getelementptr inbounds i32, i32* %A, i64 %6
+  %8 = load i32, i32* %7, align 4
   %9 = add nsw i32 %8, %sum.01
   %indvars.iv.next = add i64 %indvars.iv, -1
   %10 = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/runtime-check-address-space.ll b/test/Transforms/LoopVectorize/runtime-check-address-space.ll
index ec56f80144c4..8e7ac1f865a8 100644
--- a/test/Transforms/LoopVectorize/runtime-check-address-space.ll
+++ b/test/Transforms/LoopVectorize/runtime-check-address-space.ll
@@ -37,11 +37,11 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
   %idxprom = sext i32 %i.02 to i64
-  %arrayidx = getelementptr inbounds i32 addrspace(1)* %b, i64 %idxprom
-  %0 = load i32 addrspace(1)* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %b, i64 %idxprom
+  %0 = load i32, i32 addrspace(1)* %arrayidx, align 4
   %mul = mul nsw i32 %0, 3
   %idxprom1 = sext i32 %i.02 to i64
-  %arrayidx2 = getelementptr inbounds i32 addrspace(1)* %a, i64 %idxprom1
+  %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %idxprom1
   store i32 %mul, i32 addrspace(1)* %arrayidx2, align 4
   %inc = add nsw i32 %i.02, 1
   %cmp = icmp slt i32 %inc, %n
@@ -64,11 +64,11 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
   %idxprom = sext i32 %i.02 to i64
-  %arrayidx = getelementptr inbounds i32 addrspace(1)* %b, i64 %idxprom
-  %0 = load i32 addrspace(1)* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %b, i64 %idxprom
+  %0 = load i32, i32 addrspace(1)* %arrayidx, align 4
   %mul = mul nsw i32 %0, 3
   %idxprom1 = sext i32 %i.02 to i64
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %idxprom1
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %idxprom1
   store i32 %mul, i32* %arrayidx2, align 4
   %inc = add nsw i32 %i.02, 1
   %cmp = icmp slt i32 %inc, %n
@@ -91,11 +91,11 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
   %idxprom = sext i32 %i.02 to i64
-  %arrayidx = getelementptr inbounds i32* %b, i64 %idxprom
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %idxprom
+  %0 = load i32, i32* %arrayidx, align 4
   %mul = mul nsw i32 %0, 3
   %idxprom1 = sext i32 %i.02 to i64
-  %arrayidx2 = getelementptr inbounds i32 addrspace(1)* %a, i64 %idxprom1
+  %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %idxprom1
   store i32 %mul, i32 addrspace(1)* %arrayidx2, align 4
   %inc = add nsw i32 %i.02, 1
   %cmp = icmp slt i32 %inc, %n
@@ -119,11 +119,11 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
   %idxprom = sext i32 %i.02 to i64
-  %arrayidx = getelementptr inbounds i32 addrspace(1)* %b, i64 %idxprom
-  %0 = load i32 addrspace(1)* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %b, i64 %idxprom
+  %0 = load i32, i32 addrspace(1)* %arrayidx, align 4
   %mul = mul nsw i32 %0, 3
   %idxprom1 = sext i32 %i.02 to i64
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %idxprom1
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %idxprom1
   store i32 %mul, i32* %arrayidx2, align 4
   %inc = add nsw i32 %i.02, 1
   %cmp = icmp slt i32 %inc, %n
@@ -147,11 +147,11 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
   %idxprom = sext i32 %i.02 to i64
-  %arrayidx = getelementptr inbounds i32* %b, i64 %idxprom
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %idxprom
+  %0 = load i32, i32* %arrayidx, align 4
   %mul = mul nsw i32 %0, 3
   %idxprom1 = sext i32 %i.02 to i64
-  %arrayidx2 = getelementptr inbounds [1024 x i32] addrspace(1)* @g_as1, i64 0, i64 %idxprom1
+  %arrayidx2 = getelementptr inbounds [1024 x i32], [1024 x i32] addrspace(1)* @g_as1, i64 0, i64 %idxprom1
   store i32 %mul, i32 addrspace(1)* %arrayidx2, align 4
   %inc = add nsw i32 %i.02, 1
   %cmp = icmp slt i32 %inc, %n
@@ -176,11 +176,11 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
   %idxprom = sext i32 %i.02 to i64
-  %arrayidx = getelementptr inbounds [1024 x i32] addrspace(1)* @g_as1, i64 0, i64 %idxprom
-  %0 = load i32 addrspace(1)* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32] addrspace(1)* @g_as1, i64 0, i64 %idxprom
+  %0 = load i32, i32 addrspace(1)* %arrayidx, align 4
   %mul = mul nsw i32 %0, 3
   %idxprom1 = sext i32 %i.02 to i64
-  %arrayidx2 = getelementptr inbounds i32* %b, i64 %idxprom1
+  %arrayidx2 = getelementptr inbounds i32, i32* %b, i64 %idxprom1
   store i32 %mul, i32* %arrayidx2, align 4
   %inc = add nsw i32 %i.02, 1
   %cmp = icmp slt i32 %inc, %n
@@ -204,11 +204,11 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
   %idxprom = sext i32 %i.02 to i64
-  %arrayidx = getelementptr inbounds [1024 x i32] addrspace(2)* @q_as2, i64 0, i64 %idxprom
-  %0 = load i32 addrspace(2)* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32] addrspace(2)* @q_as2, i64 0, i64 %idxprom
+  %0 = load i32, i32 addrspace(2)* %arrayidx, align 4
   %mul = mul nsw i32 %0, 3
   %idxprom1 = sext i32 %i.02 to i64
-  %arrayidx2 = getelementptr inbounds [1024 x i32] addrspace(1)* @g_as1, i64 0, i64 %idxprom1
+  %arrayidx2 = getelementptr inbounds [1024 x i32], [1024 x i32] addrspace(1)* @g_as1, i64 0, i64 %idxprom1
   store i32 %mul, i32 addrspace(1)* %arrayidx2, align 4
   %inc = add nsw i32 %i.02, 1
   %cmp = icmp slt i32 %inc, %n
diff --git a/test/Transforms/LoopVectorize/runtime-check-readonly-address-space.ll b/test/Transforms/LoopVectorize/runtime-check-readonly-address-space.ll
index 12ba3ce6c667..6ee983d22c6d 100644
--- a/test/Transforms/LoopVectorize/runtime-check-readonly-address-space.ll
+++ b/test/Transforms/LoopVectorize/runtime-check-readonly-address-space.ll
@@ -14,12 +14,12 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %i.01 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i32 addrspace(1)* %b, i64 %i.01
-  %0 = load i32 addrspace(1)* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32 addrspace(1)* %c, i64 %i.01
-  %1 = load i32 addrspace(1)* %arrayidx1, align 4
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %b, i64 %i.01
+  %0 = load i32, i32 addrspace(1)* %arrayidx, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %c, i64 %i.01
+  %1 = load i32, i32 addrspace(1)* %arrayidx1, align 4
   %add = add nsw i32 %0, %1
-  %arrayidx2 = getelementptr inbounds i32 addrspace(1)* %a, i64 %i.01
+  %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %i.01
   store i32 %add, i32 addrspace(1)* %arrayidx2, align 4
   %inc = add i64 %i.01, 1
   %cmp = icmp ult i64 %inc, 200
@@ -39,12 +39,12 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %i.01 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %b, i64 %i.01
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %c, i64 %i.01
-  %1 = load i32* %arrayidx1, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %i.01
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %c, i64 %i.01
+  %1 = load i32, i32* %arrayidx1, align 4
   %add = add nsw i32 %0, %1
-  %arrayidx2 = getelementptr inbounds i32 addrspace(1)* %a, i64 %i.01
+  %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %i.01
   store i32 %add, i32 addrspace(1)* %arrayidx2, align 4
   %inc = add i64 %i.01, 1
   %cmp = icmp ult i64 %inc, 200
@@ -64,12 +64,12 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %i.01 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i32 addrspace(1)* %b, i64 %i.01
-  %0 = load i32 addrspace(1)* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %c, i64 %i.01
-  %1 = load i32* %arrayidx1, align 4
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %b, i64 %i.01
+  %0 = load i32, i32 addrspace(1)* %arrayidx, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %c, i64 %i.01
+  %1 = load i32, i32* %arrayidx1, align 4
   %add = add nsw i32 %0, %1
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %i.01
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %i.01
   store i32 %add, i32* %arrayidx2, align 4
   %inc = add i64 %i.01, 1
   %cmp = icmp ult i64 %inc, 200
@@ -89,12 +89,12 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %i.01 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i32 addrspace(1)* %b, i64 %i.01
-  %0 = load i32 addrspace(1)* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32 addrspace(1)* %c, i64 %i.01
-  %1 = load i32 addrspace(1)* %arrayidx1, align 4
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %b, i64 %i.01
+  %0 = load i32, i32 addrspace(1)* %arrayidx, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %c, i64 %i.01
+  %1 = load i32, i32 addrspace(1)* %arrayidx1, align 4
   %add = add nsw i32 %0, %1
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %i.01
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %i.01
   store i32 %add, i32* %arrayidx2, align 4
   %inc = add i64 %i.01, 1
   %cmp = icmp ult i64 %inc, 200
@@ -114,12 +114,12 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %i.01 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i32 addrspace(1)* %b, i64 %i.01
-  %0 = load i32 addrspace(1)* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32 addrspace(2)* %c, i64 %i.01
-  %1 = load i32 addrspace(2)* %arrayidx1, align 4
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %b, i64 %i.01
+  %0 = load i32, i32 addrspace(1)* %arrayidx, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32 addrspace(2)* %c, i64 %i.01
+  %1 = load i32, i32 addrspace(2)* %arrayidx1, align 4
   %add = add nsw i32 %0, %1
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %i.01
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %i.01
   store i32 %add, i32* %arrayidx2, align 4
   %inc = add i64 %i.01, 1
   %cmp = icmp ult i64 %inc, 200
diff --git a/test/Transforms/LoopVectorize/runtime-check-readonly.ll b/test/Transforms/LoopVectorize/runtime-check-readonly.ll
index 9d02a6accd67..a3b5a598d220 100644
--- a/test/Transforms/LoopVectorize/runtime-check-readonly.ll
+++ b/test/Transforms/LoopVectorize/runtime-check-readonly.ll
@@ -22,12 +22,12 @@ entry:
 
 for.body:
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %B, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx2 = getelementptr inbounds i32* %C, i64 %indvars.iv
-  %1 = load i32* %arrayidx2, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %C, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx2, align 4
   %add = add nsw i32 %1, %0
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
   store i32 %add, i32* %arrayidx4, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/runtime-check.ll b/test/Transforms/LoopVectorize/runtime-check.ll
index 1edafb4ed7a9..b1c5d402c458 100644
--- a/test/Transforms/LoopVectorize/runtime-check.ll
+++ b/test/Transforms/LoopVectorize/runtime-check.ll
@@ -21,10 +21,10 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %b, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
   %mul = fmul float %0, 3.000000e+00
-  %arrayidx2 = getelementptr inbounds float* %a, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds float, float* %a, i64 %indvars.iv
   store float %mul, float* %arrayidx2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -47,11 +47,11 @@ entry:
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %ind.sum = add i64 %iv, %offset
-  %arr.idx = getelementptr inbounds float* %a, i64 %ind.sum
-  %l1 = load float* %arr.idx, align 4
+  %arr.idx = getelementptr inbounds float, float* %a, i64 %ind.sum
+  %l1 = load float, float* %arr.idx, align 4
   %ind.sum2 = add i64 %iv, %offset2
-  %arr.idx2 = getelementptr inbounds float* %a, i64 %ind.sum2
-  %l2 = load float* %arr.idx2, align 4
+  %arr.idx2 = getelementptr inbounds float, float* %a, i64 %ind.sum2
+  %l2 = load float, float* %arr.idx2, align 4
   %m = fmul fast float %b, %l2
   %ad = fadd fast float %l1, %m
   store float %ad, float* %arr.idx, align 4
diff --git a/test/Transforms/LoopVectorize/runtime-limit.ll b/test/Transforms/LoopVectorize/runtime-limit.ll
index 324949dafd0a..6bc71e160ccd 100644
--- a/test/Transforms/LoopVectorize/runtime-limit.ll
+++ b/test/Transforms/LoopVectorize/runtime-limit.ll
@@ -13,21 +13,21 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %i.016 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %i.016
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %B, i64 %i.016
-  %1 = load i32* %arrayidx1, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %i.016
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %B, i64 %i.016
+  %1 = load i32, i32* %arrayidx1, align 4
   %add = add nsw i32 %1, %0
-  %arrayidx2 = getelementptr inbounds i32* %C, i64 %i.016
-  %2 = load i32* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %C, i64 %i.016
+  %2 = load i32, i32* %arrayidx2, align 4
   %add3 = add nsw i32 %add, %2
-  %arrayidx4 = getelementptr inbounds i32* %E, i64 %i.016
-  %3 = load i32* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %E, i64 %i.016
+  %3 = load i32, i32* %arrayidx4, align 4
   %add5 = add nsw i32 %add3, %3
-  %arrayidx6 = getelementptr inbounds i32* %F, i64 %i.016
-  %4 = load i32* %arrayidx6, align 4
+  %arrayidx6 = getelementptr inbounds i32, i32* %F, i64 %i.016
+  %4 = load i32, i32* %arrayidx6, align 4
   %add7 = add nsw i32 %add5, %4
-  %arrayidx8 = getelementptr inbounds i32* %out, i64 %i.016
+  %arrayidx8 = getelementptr inbounds i32, i32* %out, i64 %i.016
   store i32 %add7, i32* %arrayidx8, align 4
   %inc = add i64 %i.016, 1
   %exitcond = icmp eq i64 %inc, 256
@@ -47,32 +47,32 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %i.037 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %i.037
-  %0 = load i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds i32* %B, i64 %i.037
-  %1 = load i32* %arrayidx1, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %i.037
+  %0 = load i32, i32* %arrayidx, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %B, i64 %i.037
+  %1 = load i32, i32* %arrayidx1, align 4
   %add = add nsw i32 %1, %0
-  %arrayidx2 = getelementptr inbounds i32* %C, i64 %i.037
-  %2 = load i32* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %C, i64 %i.037
+  %2 = load i32, i32* %arrayidx2, align 4
   %add3 = add nsw i32 %add, %2
-  %arrayidx4 = getelementptr inbounds i32* %E, i64 %i.037
-  %3 = load i32* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %E, i64 %i.037
+  %3 = load i32, i32* %arrayidx4, align 4
   %add5 = add nsw i32 %add3, %3
-  %arrayidx6 = getelementptr inbounds i32* %F, i64 %i.037
-  %4 = load i32* %arrayidx6, align 4
+  %arrayidx6 = getelementptr inbounds i32, i32* %F, i64 %i.037
+  %4 = load i32, i32* %arrayidx6, align 4
   %add7 = add nsw i32 %add5, %4
-  %arrayidx8 = getelementptr inbounds i32* %out, i64 %i.037
+  %arrayidx8 = getelementptr inbounds i32, i32* %out, i64 %i.037
   store i32 %add7, i32* %arrayidx8, align 4
-  %5 = load i32* %arrayidx, align 4
-  %6 = load i32* %arrayidx1, align 4
+  %5 = load i32, i32* %arrayidx, align 4
+  %6 = load i32, i32* %arrayidx1, align 4
   %add11 = add nsw i32 %6, %5
-  %7 = load i32* %arrayidx2, align 4
+  %7 = load i32, i32* %arrayidx2, align 4
   %add13 = add nsw i32 %add11, %7
-  %8 = load i32* %arrayidx4, align 4
+  %8 = load i32, i32* %arrayidx4, align 4
   %add15 = add nsw i32 %add13, %8
-  %9 = load i32* %arrayidx6, align 4
+  %9 = load i32, i32* %arrayidx6, align 4
   %add17 = add nsw i32 %add15, %9
-  %arrayidx18 = getelementptr inbounds i32* %out2, i64 %i.037
+  %arrayidx18 = getelementptr inbounds i32, i32* %out2, i64 %i.037
   store i32 %add17, i32* %arrayidx18, align 4
   %inc = add i64 %i.037, 1
   %exitcond = icmp eq i64 %inc, 256
diff --git a/test/Transforms/LoopVectorize/safegep.ll b/test/Transforms/LoopVectorize/safegep.ll
index f853afd2bba6..ecef8138f0b2 100644
--- a/test/Transforms/LoopVectorize/safegep.ll
+++ b/test/Transforms/LoopVectorize/safegep.ll
@@ -17,10 +17,10 @@ entry:
 
 "<bb 3>":
   %i_15 = phi i32 [ 0, %entry ], [ %i_19, %"<bb 3>" ]
-  %pp3 = getelementptr float* %A, i32 %i_15
-  %D.1396_10 = load float* %pp3, align 4
-  %pp24 = getelementptr float* %B, i32 %i_15
-  %D.1398_15 = load float* %pp24, align 4
+  %pp3 = getelementptr float, float* %A, i32 %i_15
+  %D.1396_10 = load float, float* %pp3, align 4
+  %pp24 = getelementptr float, float* %B, i32 %i_15
+  %D.1398_15 = load float, float* %pp24, align 4
   %D.1399_17 = fadd float %D.1398_15, %K
   %D.1400_18 = fmul float %D.1396_10, %D.1399_17
   store float %D.1400_18, float* %pp3, align 4
@@ -43,10 +43,10 @@ entry:
 
 "<bb 3>":
   %i_15 = phi i32 [ 0, %entry ], [ %i_19, %"<bb 3>" ]
-  %pp3 = getelementptr float addrspace(5) * %A, i32 %i_15
-  %D.1396_10 = load float addrspace(5) * %pp3, align 4
-  %pp24 = getelementptr float* %B, i32 %i_15
-  %D.1398_15 = load float* %pp24, align 4
+  %pp3 = getelementptr float, float addrspace(5) * %A, i32 %i_15
+  %D.1396_10 = load float, float addrspace(5) * %pp3, align 4
+  %pp24 = getelementptr float, float* %B, i32 %i_15
+  %D.1398_15 = load float, float* %pp24, align 4
   %D.1399_17 = fadd float %D.1398_15, %K
   %D.1400_18 = fmul float %D.1396_10, %D.1399_17
   store float %D.1400_18, float addrspace(5) * %pp3, align 4
diff --git a/test/Transforms/LoopVectorize/same-base-access.ll b/test/Transforms/LoopVectorize/same-base-access.ll
index d19458f4aa92..31cff0ee653f 100644
--- a/test/Transforms/LoopVectorize/same-base-access.ll
+++ b/test/Transforms/LoopVectorize/same-base-access.ll
@@ -26,33 +26,33 @@ define i32 @kernel11(double* %x, double* %y, i32 %n) nounwind uwtable ssp {
   br label %4
 
 ; <label>:4                                       ; preds = %25, %0
-  %5 = load i32* %k, align 4
-  %6 = load i32* %3, align 4
+  %5 = load i32, i32* %k, align 4
+  %6 = load i32, i32* %3, align 4
   %7 = icmp slt i32 %5, %6
   br i1 %7, label %8, label %28
 
 ; <label>:8                                       ; preds = %4
-  %9 = load i32* %k, align 4
+  %9 = load i32, i32* %k, align 4
   %10 = sub nsw i32 %9, 1
   %11 = sext i32 %10 to i64
-  %12 = load double** %1, align 8
-  %13 = getelementptr inbounds double* %12, i64 %11
-  %14 = load double* %13, align 8
-  %15 = load i32* %k, align 4
+  %12 = load double*, double** %1, align 8
+  %13 = getelementptr inbounds double, double* %12, i64 %11
+  %14 = load double, double* %13, align 8
+  %15 = load i32, i32* %k, align 4
   %16 = sext i32 %15 to i64
-  %17 = load double** %2, align 8
-  %18 = getelementptr inbounds double* %17, i64 %16
-  %19 = load double* %18, align 8
+  %17 = load double*, double** %2, align 8
+  %18 = getelementptr inbounds double, double* %17, i64 %16
+  %19 = load double, double* %18, align 8
   %20 = fadd double %14, %19
-  %21 = load i32* %k, align 4
+  %21 = load i32, i32* %k, align 4
   %22 = sext i32 %21 to i64
-  %23 = load double** %1, align 8
-  %24 = getelementptr inbounds double* %23, i64 %22
+  %23 = load double*, double** %1, align 8
+  %24 = getelementptr inbounds double, double* %23, i64 %22
   store double %20, double* %24, align 8
   br label %25
 
 ; <label>:25                                      ; preds = %8
-  %26 = load i32* %k, align 4
+  %26 = load i32, i32* %k, align 4
   %27 = add nsw i32 %26, 1
   store i32 %27, i32* %k, align 4
   br label %4
@@ -86,8 +86,8 @@ define i32 @func2(i32* nocapture %a) nounwind uwtable ssp {
 ; <label>:1                                       ; preds = %7, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %7 ]
   %2 = mul nsw i64 %indvars.iv, 7
-  %3 = getelementptr inbounds i32* %a, i64 %2
-  %4 = load i32* %3, align 4
+  %3 = getelementptr inbounds i32, i32* %a, i64 %2
+  %4 = load i32, i32* %3, align 4
   %5 = icmp sgt i32 %4, 3
   br i1 %5, label %6, label %7
 
diff --git a/test/Transforms/LoopVectorize/scalar-select.ll b/test/Transforms/LoopVectorize/scalar-select.ll
index 6b37cc23ae31..b17b20288217 100644
--- a/test/Transforms/LoopVectorize/scalar-select.ll
+++ b/test/Transforms/LoopVectorize/scalar-select.ll
@@ -18,12 +18,12 @@ define void @example1(i1 %cond) nounwind uwtable ssp {
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %indvars.iv
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds [2048 x i32]* @c, i64 0, i64 %indvars.iv
-  %5 = load i32* %4, align 4
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds [2048 x i32], [2048 x i32]* @c, i64 0, i64 %indvars.iv
+  %5 = load i32, i32* %4, align 4
   %6 = add nsw i32 %5, %3
-  %7 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %7 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
   %sel = select i1 %cond, i32 %6, i32 zeroinitializer
   store i32 %sel, i32* %7, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/scev-exitlim-crash.ll b/test/Transforms/LoopVectorize/scev-exitlim-crash.ll
index 515477180772..cfc1d6d40a7e 100644
--- a/test/Transforms/LoopVectorize/scev-exitlim-crash.ll
+++ b/test/Transforms/LoopVectorize/scev-exitlim-crash.ll
@@ -29,14 +29,14 @@ for.cond4.preheader:                              ; preds = %for.cond
   br i1 %cmp514, label %for.cond7.preheader.lr.ph, label %for.end26
 
 for.cond7.preheader.lr.ph:                        ; preds = %for.cond4.preheader
-  %0 = load i32** @e, align 8, !tbaa !4
+  %0 = load i32*, i32** @e, align 8, !tbaa !4
   br label %for.cond7.preheader
 
 for.cond7.preheader:                              ; preds = %for.cond7.preheader.lr.ph, %for.inc23
   %y.017 = phi i32 [ 0, %for.cond7.preheader.lr.ph ], [ %inc24, %for.inc23 ]
   %i.116 = phi i32 [ 0, %for.cond7.preheader.lr.ph ], [ %i.2.lcssa, %for.inc23 ]
   %n.015 = phi i32 [ undef, %for.cond7.preheader.lr.ph ], [ %inc25, %for.inc23 ]
-  %1 = load i32* @b, align 4, !tbaa !5
+  %1 = load i32, i32* @b, align 4, !tbaa !5
   %tobool11 = icmp eq i32 %1, 0
   br i1 %tobool11, label %for.inc23, label %for.body8.lr.ph
 
@@ -51,7 +51,7 @@ for.body8:                                        ; preds = %for.body8.lr.ph, %f
   %add10 = add i32 %add9, %2
   store i32 %add10, i32* @f, align 4, !tbaa !5
   %idx.ext = sext i32 %add10 to i64
-  %add.ptr = getelementptr inbounds i32* @a, i64 %idx.ext
+  %add.ptr = getelementptr inbounds i32, i32* @a, i64 %idx.ext
   %tobool129 = icmp eq i32 %i.213, 0
   br i1 %tobool129, label %for.inc19, label %for.body13.lr.ph
 
@@ -62,9 +62,9 @@ for.body13.lr.ph:                                 ; preds = %for.body8
 for.body13:                                       ; preds = %for.body13.lr.ph, %for.body13
   %indvars.iv = phi i64 [ %3, %for.body13.lr.ph ], [ %indvars.iv.next, %for.body13 ]
   %add.ptr.sum = add i64 %idx.ext, %indvars.iv
-  %arrayidx = getelementptr inbounds i32* @a, i64 %add.ptr.sum
-  %4 = load i32* %arrayidx, align 4, !tbaa !5
-  %arrayidx15 = getelementptr inbounds i32* %0, i64 %indvars.iv
+  %arrayidx = getelementptr inbounds i32, i32* @a, i64 %add.ptr.sum
+  %4 = load i32, i32* %arrayidx, align 4, !tbaa !5
+  %arrayidx15 = getelementptr inbounds i32, i32* %0, i64 %indvars.iv
   store i32 %4, i32* %arrayidx15, align 4, !tbaa !5
   %indvars.iv.next = add i64 %indvars.iv, 1
   %5 = trunc i64 %indvars.iv.next to i32
@@ -75,11 +75,11 @@ for.cond11.for.inc19_crit_edge:                   ; preds = %for.body13
   br label %for.inc19
 
 for.inc19:                                        ; preds = %for.cond11.for.inc19_crit_edge, %for.body8
-  %6 = load i32* @c, align 4, !tbaa !5
+  %6 = load i32, i32* @c, align 4, !tbaa !5
   %inc20 = add nsw i32 %6, 1
   store i32 %inc20, i32* @c, align 4, !tbaa !5
   %indvars.iv.next20 = add i64 %indvars.iv19, 1
-  %7 = load i32* @b, align 4, !tbaa !5
+  %7 = load i32, i32* @b, align 4, !tbaa !5
   %tobool = icmp eq i32 %7, 0
   br i1 %tobool, label %for.cond7.for.inc23_crit_edge, label %for.body8
 
diff --git a/test/Transforms/LoopVectorize/simple-unroll.ll b/test/Transforms/LoopVectorize/simple-unroll.ll
index 8bf680ac7c5f..fc996ed3818d 100644
--- a/test/Transforms/LoopVectorize/simple-unroll.ll
+++ b/test/Transforms/LoopVectorize/simple-unroll.ll
@@ -23,8 +23,8 @@ define void @inc(i32 %n) nounwind uwtable noinline ssp {
 
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
-  %3 = load i32* %2, align 4
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
   %4 = trunc i64 %indvars.iv to i32
   %5 = add nsw i32 %3, %4
   store i32 %5, i32* %2, align 4
diff --git a/test/Transforms/LoopVectorize/small-loop.ll b/test/Transforms/LoopVectorize/small-loop.ll
index 1d30102c3f97..ce606d1b3606 100644
--- a/test/Transforms/LoopVectorize/small-loop.ll
+++ b/test/Transforms/LoopVectorize/small-loop.ll
@@ -15,12 +15,12 @@ define void @example1() nounwind uwtable ssp {
 
 ; <label>:1                                       ; preds = %1, %0
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
-  %2 = getelementptr inbounds [2048 x i32]* @b, i64 0, i64 %indvars.iv
-  %3 = load i32* %2, align 4
-  %4 = getelementptr inbounds [2048 x i32]* @c, i64 0, i64 %indvars.iv
-  %5 = load i32* %4, align 4
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @b, i64 0, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
+  %4 = getelementptr inbounds [2048 x i32], [2048 x i32]* @c, i64 0, i64 %indvars.iv
+  %5 = load i32, i32* %4, align 4
   %6 = add nsw i32 %5, %3
-  %7 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %7 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
   store i32 %6, i32* %7, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/start-non-zero.ll b/test/Transforms/LoopVectorize/start-non-zero.ll
index cc474945a9d0..b444a692319a 100644
--- a/test/Transforms/LoopVectorize/start-non-zero.ll
+++ b/test/Transforms/LoopVectorize/start-non-zero.ll
@@ -17,8 +17,8 @@ for.body.lr.ph:                                   ; preds = %entry
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
   %indvars.iv = phi i64 [ %0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %1 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx, align 4
   %mul = mul nuw i32 %1, 333
   store i32 %mul, i32* %arrayidx, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/store-shuffle-bug.ll b/test/Transforms/LoopVectorize/store-shuffle-bug.ll
index 6d3d11349b14..4d62df157175 100644
--- a/test/Transforms/LoopVectorize/store-shuffle-bug.ll
+++ b/test/Transforms/LoopVectorize/store-shuffle-bug.ll
@@ -30,14 +30,14 @@ entry:
 for.body:
   %indvars.iv = phi i64 [ 93, %entry ], [ %indvars.iv.next, %for.body ]
   %0 = add i64 %indvars.iv, 1
-  %arrayidx = getelementptr inbounds [100 x i32]* @uf, i64 0, i64 %0
-  %arrayidx3 = getelementptr inbounds [100 x i32]* @xi, i64 0, i64 %0
-  %1 = load i32* %arrayidx3, align 4
-  %2 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [100 x i32], [100 x i32]* @uf, i64 0, i64 %0
+  %arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* @xi, i64 0, i64 %0
+  %1 = load i32, i32* %arrayidx3, align 4
+  %2 = load i32, i32* %arrayidx, align 4
   %add4 = add nsw i32 %2, %1
   store i32 %add4, i32* %arrayidx, align 4
-  %arrayidx7 = getelementptr inbounds [100 x i32]* @q, i64 0, i64 %0
-  %3 = load i32* %arrayidx7, align 4
+  %arrayidx7 = getelementptr inbounds [100 x i32], [100 x i32]* @q, i64 0, i64 %0
+  %3 = load i32, i32* %arrayidx7, align 4
   %add8 = add nsw i32 %add4, %3
   store i32 %add8, i32* %arrayidx, align 4
   %indvars.iv.next = add i64 %indvars.iv, -1
diff --git a/test/Transforms/LoopVectorize/struct_access.ll b/test/Transforms/LoopVectorize/struct_access.ll
index cf6f325ae306..1e4019a7810a 100644
--- a/test/Transforms/LoopVectorize/struct_access.ll
+++ b/test/Transforms/LoopVectorize/struct_access.ll
@@ -32,8 +32,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %sum.05 = phi i32 [ %add, %for.body ], [ 0, %entry ]
-  %x = getelementptr inbounds %struct.coordinate* %A, i64 %indvars.iv, i32 0
-  %0 = load i32* %x, align 4
+  %x = getelementptr inbounds %struct.coordinate, %struct.coordinate* %A, i64 %indvars.iv, i32 0
+  %0 = load i32, i32* %x, align 4
   %add = add nsw i32 %0, %sum.05
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -74,8 +74,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %sum.05 = phi i32 [ %add, %for.body ], [ 0, %entry ]
-  %x = getelementptr inbounds %struct.lit* %A, i64 %indvars.iv, i32 0
-  %0 = load i32* %x, align 4
+  %x = getelementptr inbounds %struct.lit, %struct.lit* %A, i64 %indvars.iv, i32 0
+  %0 = load i32, i32* %x, align 4
   %add = add nsw i32 %0, %sum.05
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/tbaa-nodep.ll b/test/Transforms/LoopVectorize/tbaa-nodep.ll
index be3e74f5d68a..06d000230027 100644
--- a/test/Transforms/LoopVectorize/tbaa-nodep.ll
+++ b/test/Transforms/LoopVectorize/tbaa-nodep.ll
@@ -10,10 +10,10 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4, !tbaa !0
+  %arrayidx = getelementptr inbounds float, float* %b, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4, !tbaa !0
   %conv = fptosi float %0 to i32
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
   store i32 %conv, i32* %arrayidx2, align 4, !tbaa !4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 1600
@@ -30,7 +30,7 @@ for.end:                                          ; preds = %for.body
 ; CHECK-NEXT: br label %vector.body
 ; CHECK: vector.body:
 
-; CHECK: load <4 x float>* %{{.*}}, align 4, !tbaa
+; CHECK: load <4 x float>, <4 x float>* %{{.*}}, align 4, !tbaa
 ; CHECK: store <4 x i32> %{{.*}}, <4 x i32>* %{{.*}}, align 4, !tbaa
 
 ; CHECK: ret i32 0
@@ -38,7 +38,7 @@ for.end:                                          ; preds = %for.body
 ; CHECK-NOTBAA-LABEL: @test1
 ; CHECK-NOTBAA: icmp uge i32*
 
-; CHECK-NOTBAA: load <4 x float>* %{{.*}}, align 4, !tbaa
+; CHECK-NOTBAA: load <4 x float>, <4 x float>* %{{.*}}, align 4, !tbaa
 ; CHECK-NOTBAA: store <4 x i32> %{{.*}}, <4 x i32>* %{{.*}}, align 4, !tbaa
 
 ; CHECK-NOTBAA: ret i32 0
@@ -51,13 +51,13 @@ entry:
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
-  %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv
-  %0 = load float* %arrayidx, align 4, !tbaa !0
-  %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv
-  %1 = load i32* %arrayidx2, align 4, !tbaa !4
+  %arrayidx = getelementptr inbounds float, float* %b, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4, !tbaa !0
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  %1 = load i32, i32* %arrayidx2, align 4, !tbaa !4
   %conv = sitofp i32 %1 to float
   %mul = fmul float %0, %conv
-  %arrayidx4 = getelementptr inbounds float* %c, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds float, float* %c, i64 %indvars.iv
   store float %mul, float* %arrayidx4, align 4, !tbaa !0
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 1600
@@ -74,7 +74,7 @@ for.end:                                          ; preds = %for.body
 ; CHECK: icmp uge float*
 ; CHECK-NOT: icmp uge i32*
 
-; CHECK: load <4 x float>* %{{.*}}, align 4, !tbaa
+; CHECK: load <4 x float>, <4 x float>* %{{.*}}, align 4, !tbaa
 ; CHECK: store <4 x float> %{{.*}}, <4 x float>* %{{.*}}, align 4, !tbaa
 
 ; CHECK: ret i32 0
@@ -85,7 +85,7 @@ for.end:                                          ; preds = %for.body
 ; CHECK-NOTBAA-DAG: icmp uge float*
 ; CHECK-NOTBAA-DAG: icmp uge i32*
 
-; CHECK-NOTBAA: load <4 x float>* %{{.*}}, align 4, !tbaa
+; CHECK-NOTBAA: load <4 x float>, <4 x float>* %{{.*}}, align 4, !tbaa
 ; CHECK-NOTBAA: store <4 x float> %{{.*}}, <4 x float>* %{{.*}}, align 4, !tbaa
 
 ; CHECK-NOTBAA: ret i32 0
diff --git a/test/Transforms/LoopVectorize/undef-inst-bug.ll b/test/Transforms/LoopVectorize/undef-inst-bug.ll
index 0444fe894ed4..e9d053cf0bef 100644
--- a/test/Transforms/LoopVectorize/undef-inst-bug.ll
+++ b/test/Transforms/LoopVectorize/undef-inst-bug.ll
@@ -24,7 +24,7 @@ for.body:
   ; Loop invariant anchored in loop.
   %idxprom21 = zext i32 undef to i64
 
-  %arrayidx23 = getelementptr inbounds [100 x [100 x i32]]* undef, i64 0, i64 %idxprom21, i64 %indvars.iv17
+  %arrayidx23 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* undef, i64 0, i64 %idxprom21, i64 %indvars.iv17
   store i32 undef, i32* %arrayidx23, align 4
   %indvars.next= add i64 %indvars.iv17, -1
   %0 = trunc i64 %indvars.next to i32
diff --git a/test/Transforms/LoopVectorize/unroll.ll b/test/Transforms/LoopVectorize/unroll.ll
new file mode 100644
index 000000000000..74076f695104
--- /dev/null
+++ b/test/Transforms/LoopVectorize/unroll.ll
@@ -0,0 +1,37 @@
+; This test makes sure that loop will not be unrolled in vectorization if VF computed
+; equals to 1.
+; RUN: opt < %s -loop-vectorize -S | FileCheck %s
+
+; Make sure there are no geps being merged.
+; CHECK-LABEL: @foo(
+; CHECK: getelementptr
+; CHECK-NOT: getelementptr
+
+@N = common global i32 0, align 4
+@a = common global [1000 x i32] zeroinitializer, align 16
+
+define void @foo() #0 {
+entry:
+  %0 = load i32, i32* @N, align 4
+  %cmp5 = icmp sgt i32 %0, 0
+  br i1 %cmp5, label %for.body.lr.ph, label %for.end
+
+for.body.lr.ph:                                   ; preds = %entry
+  %conv = sext i32 %0 to i64
+  br label %for.body
+
+for.body:                                         ; preds = %for.body.lr.ph, %for.body
+  %i.06 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
+  %mul = mul nuw nsw i64 %i.06, 7
+  %arrayidx = getelementptr inbounds [1000 x i32], [1000 x i32]* @a, i64 0, i64 %mul
+  store i32 3, i32* %arrayidx, align 4
+  %inc = add nuw nsw i64 %i.06, 1
+  %cmp = icmp slt i64 %inc, %conv
+  br i1 %cmp, label %for.body, label %for.end.loopexit
+
+for.end.loopexit:                                 ; preds = %for.body
+  br label %for.end
+
+for.end:                                          ; preds = %for.end.loopexit, %entry
+  ret void
+}
diff --git a/test/Transforms/LoopVectorize/unroll_novec.ll b/test/Transforms/LoopVectorize/unroll_novec.ll
index 257b4e63a915..c23ad77a31f8 100644
--- a/test/Transforms/LoopVectorize/unroll_novec.ll
+++ b/test/Transforms/LoopVectorize/unroll_novec.ll
@@ -10,11 +10,11 @@ target triple = "x86_64-apple-macosx10.8.0"
 ;    a[i] += i;
 ;  }
 ;CHECK-LABEL: @inc(
-;CHECK: load i32*
-;CHECK: load i32*
-;CHECK: load i32*
-;CHECK: load i32*
-;CHECK-NOT: load i32*
+;CHECK: load i32, i32*
+;CHECK: load i32, i32*
+;CHECK: load i32, i32*
+;CHECK: load i32, i32*
+;CHECK-NOT: load i32, i32*
 ;CHECK: add nsw i32
 ;CHECK: add nsw i32
 ;CHECK: add nsw i32
@@ -33,8 +33,8 @@ define void @inc(i32 %n) nounwind uwtable noinline ssp {
 
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds [2048 x i32]* @a, i64 0, i64 %indvars.iv
-  %3 = load i32* %2, align 4
+  %2 = getelementptr inbounds [2048 x i32], [2048 x i32]* @a, i64 0, i64 %indvars.iv
+  %3 = load i32, i32* %2, align 4
   %4 = trunc i64 %indvars.iv to i32
   %5 = add nsw i32 %3, %4
   store i32 %5, i32* %2, align 4
diff --git a/test/Transforms/LoopVectorize/unsized-pointee-crash.ll b/test/Transforms/LoopVectorize/unsized-pointee-crash.ll
index 5cc98378b952..7763c9c68420 100644
--- a/test/Transforms/LoopVectorize/unsized-pointee-crash.ll
+++ b/test/Transforms/LoopVectorize/unsized-pointee-crash.ll
@@ -11,10 +11,10 @@ for.body:
   %b.05 = phi i32 (...)* [ undef, %entry ], [ %1, %for.body ]
   %a.04 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %0 = bitcast i32 (...)* %b.05 to i8*
-  %add.ptr = getelementptr i8* %0, i64 1
+  %add.ptr = getelementptr i8, i8* %0, i64 1
   %1 = bitcast i8* %add.ptr to i32 (...)*
 ; CHECK:      %[[cst:.*]] = bitcast i32 (...)* {{.*}} to i8*
-; CHECK-NEXT: %[[gep:.*]] = getelementptr i8* %[[cst]], i64 1
+; CHECK-NEXT: %[[gep:.*]] = getelementptr i8, i8* %[[cst]], i64 1
   %inc = add nsw i32 %a.04, 1
   %exitcond = icmp eq i32 %a.04, 63
   br i1 %exitcond, label %for.end, label %for.body
diff --git a/test/Transforms/LoopVectorize/value-ptr-bug.ll b/test/Transforms/LoopVectorize/value-ptr-bug.ll
index 7fb9095b7c10..ce4601f7b92d 100644
--- a/test/Transforms/LoopVectorize/value-ptr-bug.ll
+++ b/test/Transforms/LoopVectorize/value-ptr-bug.ll
@@ -19,8 +19,8 @@ entry:
 loop:
   %inc = phi i32 [ %sub267, %entry ], [ %add, %loop]
   %ext.inc = sext i32 %inc to i64
-  %add.ptr265 = getelementptr inbounds i32* %ptr265, i64 %ext.inc
-  %add.ptr266 = getelementptr inbounds i32* %ptr266, i64 %ext.inc
+  %add.ptr265 = getelementptr inbounds i32, i32* %ptr265, i64 %ext.inc
+  %add.ptr266 = getelementptr inbounds i32, i32* %ptr266, i64 %ext.inc
   %add = add i32 %inc, 9
   %cmp = icmp slt i32 %add, 140
   br i1 %cmp, label %block1, label %loop
@@ -37,9 +37,9 @@ do.body272:
   %row_width.5 = phi i32 [ %sub267.lcssa, %block1 ], [ %dec, %do.body272 ]
   %sp.4 = phi i8* [ %tmp30, %block1 ], [ %incdec.ptr273, %do.body272 ]
   %dp.addr.4 = phi i8* [ %tmp29, %block1 ], [ %incdec.ptr274, %do.body272 ]
-  %incdec.ptr273 = getelementptr inbounds i8* %sp.4, i64 1
-  %tmp31 = load i8* %sp.4, align 1
-  %incdec.ptr274 = getelementptr inbounds i8* %dp.addr.4, i64 1
+  %incdec.ptr273 = getelementptr inbounds i8, i8* %sp.4, i64 1
+  %tmp31 = load i8, i8* %sp.4, align 1
+  %incdec.ptr274 = getelementptr inbounds i8, i8* %dp.addr.4, i64 1
   store i8 %tmp31, i8* %dp.addr.4, align 1
   %dec = add i32 %row_width.5, -1
   %cmp276 = icmp eq i32 %dec, 0
diff --git a/test/Transforms/LoopVectorize/vect.omp.persistence.ll b/test/Transforms/LoopVectorize/vect.omp.persistence.ll
index ea7be9c106b3..0d7f8b9398f6 100644
--- a/test/Transforms/LoopVectorize/vect.omp.persistence.ll
+++ b/test/Transforms/LoopVectorize/vect.omp.persistence.ll
@@ -45,13 +45,13 @@ for.header:
 for.body:
 
   %0 = add nsw i64 %indvars.iv, -5
-  %arrayidx = getelementptr inbounds float* %a, i64 %0
-  %1 = load float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !1
+  %arrayidx = getelementptr inbounds float, float* %a, i64 %0
+  %1 = load float, float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !1
   %2 = add nsw i64 %indvars.iv, 2
-  %arrayidx2 = getelementptr inbounds float* %a, i64 %2
-  %3 = load float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !1
+  %arrayidx2 = getelementptr inbounds float, float* %a, i64 %2
+  %3 = load float, float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !1
   %mul = fmul float %1, %3
-  %arrayidx4 = getelementptr inbounds float* %a, i64 %indvars.iv
+  %arrayidx4 = getelementptr inbounds float, float* %a, i64 %indvars.iv
   store float %mul, float* %arrayidx4, align 4, !llvm.mem.parallel_loop_access !1
 
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
diff --git a/test/Transforms/LoopVectorize/vect.stats.ll b/test/Transforms/LoopVectorize/vect.stats.ll
index c5b6e64bc9fb..7bf5a6084847 100644
--- a/test/Transforms/LoopVectorize/vect.stats.ll
+++ b/test/Transforms/LoopVectorize/vect.stats.ll
@@ -20,8 +20,8 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv2 = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds float* %a, i64 %indvars.iv2
-  %0 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 %indvars.iv2
+  %0 = load float, float* %arrayidx, align 4
   %mul = fmul float %0, %0
   store float %mul, float* %arrayidx, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv2, 1
@@ -42,13 +42,13 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv2 = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %0 = add nsw i64 %indvars.iv2, -5
-  %arrayidx = getelementptr inbounds float* %a, i64 %0
-  %1 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %a, i64 %0
+  %1 = load float, float* %arrayidx, align 4
   %2 = add nsw i64 %indvars.iv2, 2
-  %arrayidx2 = getelementptr inbounds float* %a, i64 %2
-  %3 = load float* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %a, i64 %2
+  %3 = load float, float* %arrayidx2, align 4
   %mul = fmul float %1, %3
-  %arrayidx4 = getelementptr inbounds float* %a, i64 %indvars.iv2
+  %arrayidx4 = getelementptr inbounds float, float* %a, i64 %indvars.iv2
   store float %mul, float* %arrayidx4, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv2, 1
   %cmp2 = icmp sgt i64 %indvars.iv.next, %size
diff --git a/test/Transforms/LoopVectorize/vectorize-once.ll b/test/Transforms/LoopVectorize/vectorize-once.ll
index a9b2a53f74b3..9a9125039966 100644
--- a/test/Transforms/LoopVectorize/vectorize-once.ll
+++ b/test/Transforms/LoopVectorize/vectorize-once.ll
@@ -22,16 +22,16 @@ target triple = "x86_64-apple-macosx10.8.0"
 define i32 @_Z4foo1Pii(i32* %A, i32 %n) #0 {
 entry:
   %idx.ext = sext i32 %n to i64
-  %add.ptr = getelementptr inbounds i32* %A, i64 %idx.ext
+  %add.ptr = getelementptr inbounds i32, i32* %A, i64 %idx.ext
   %cmp3.i = icmp eq i32 %n, 0
   br i1 %cmp3.i, label %_ZSt10accumulateIPiiET0_T_S2_S1_.exit, label %for.body.i
 
 for.body.i:                                       ; preds = %entry, %for.body.i
   %__init.addr.05.i = phi i32 [ %add.i, %for.body.i ], [ 0, %entry ]
   %__first.addr.04.i = phi i32* [ %incdec.ptr.i, %for.body.i ], [ %A, %entry ]
-  %0 = load i32* %__first.addr.04.i, align 4
+  %0 = load i32, i32* %__first.addr.04.i, align 4
   %add.i = add nsw i32 %0, %__init.addr.05.i
-  %incdec.ptr.i = getelementptr inbounds i32* %__first.addr.04.i, i64 1
+  %incdec.ptr.i = getelementptr inbounds i32, i32* %__first.addr.04.i, i64 1
   %cmp.i = icmp eq i32* %incdec.ptr.i, %add.ptr
   br i1 %cmp.i, label %_ZSt10accumulateIPiiET0_T_S2_S1_.exit, label %for.body.i
 
@@ -48,16 +48,16 @@ _ZSt10accumulateIPiiET0_T_S2_S1_.exit:            ; preds = %for.body.i, %entry
 define i32 @_Z4foo2Pii(i32* %A, i32 %n) #0 {
 entry:
   %idx.ext = sext i32 %n to i64
-  %add.ptr = getelementptr inbounds i32* %A, i64 %idx.ext
+  %add.ptr = getelementptr inbounds i32, i32* %A, i64 %idx.ext
   %cmp3.i = icmp eq i32 %n, 0
   br i1 %cmp3.i, label %_ZSt10accumulateIPiiET0_T_S2_S1_.exit, label %for.body.i
 
 for.body.i:                                       ; preds = %entry, %for.body.i
   %__init.addr.05.i = phi i32 [ %add.i, %for.body.i ], [ 0, %entry ]
   %__first.addr.04.i = phi i32* [ %incdec.ptr.i, %for.body.i ], [ %A, %entry ]
-  %0 = load i32* %__first.addr.04.i, align 4
+  %0 = load i32, i32* %__first.addr.04.i, align 4
   %add.i = add nsw i32 %0, %__init.addr.05.i
-  %incdec.ptr.i = getelementptr inbounds i32* %__first.addr.04.i, i64 1
+  %incdec.ptr.i = getelementptr inbounds i32, i32* %__first.addr.04.i, i64 1
   %cmp.i = icmp eq i32* %incdec.ptr.i, %add.ptr
   br i1 %cmp.i, label %_ZSt10accumulateIPiiET0_T_S2_S1_.exit, label %for.body.i, !llvm.loop !0
 
@@ -71,7 +71,8 @@ attributes #0 = { nounwind readonly ssp uwtable "fp-contract-model"="standard" "
 ; CHECK: !0 = distinct !{!0, !1, !2}
 ; CHECK: !1 = !{!"llvm.loop.vectorize.width", i32 1}
 ; CHECK: !2 = !{!"llvm.loop.interleave.count", i32 1}
-; CHECK: !3 = distinct !{!3, !1, !2}
+; CHECK: !3 = distinct !{!3, !4, !1, !2}
+; CHECK: !4 = !{!"llvm.loop.unroll.runtime.disable"}
 
 !0 = !{!0, !1}
 !1 = !{!"llvm.loop.vectorize.width", i32 1}
diff --git a/test/Transforms/LoopVectorize/version-mem-access.ll b/test/Transforms/LoopVectorize/version-mem-access.ll
index 7ac2fca2533f..a9d319e5a2dd 100644
--- a/test/Transforms/LoopVectorize/version-mem-access.ll
+++ b/test/Transforms/LoopVectorize/version-mem-access.ll
@@ -2,10 +2,16 @@
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 
+; Check that we version this loop with speculating the value 1 for symbolic
+; strides.  This also checks that the symbolic stride information is correctly
+; propagated to the memcheck generation.  Without this the loop wouldn't
+; vectorize because we couldn't determine the array bounds for the required
+; memchecks.
+
 ; CHECK-LABEL: test
-define void @test(i32* noalias %A, i64 %AStride,
-                  i32* noalias %B, i32 %BStride,
-                  i32* noalias %C, i64 %CStride, i32 %N) {
+define void @test(i32*  %A, i64 %AStride,
+                  i32*  %B, i32 %BStride,
+                  i32*  %C, i64 %CStride, i32 %N) {
 entry:
   %cmp13 = icmp eq i32 %N, 0
   br i1 %cmp13, label %for.end, label %for.body.preheader
@@ -28,14 +34,14 @@ for.body:
   %iv.trunc = trunc i64 %indvars.iv to i32
   %mul = mul i32 %iv.trunc, %BStride
   %mul64 = zext i32 %mul to i64
-  %arrayidx = getelementptr inbounds i32* %B, i64 %mul64
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %B, i64 %mul64
+  %0 = load i32, i32* %arrayidx, align 4
   %mul2 = mul nsw i64 %indvars.iv, %CStride
-  %arrayidx3 = getelementptr inbounds i32* %C, i64 %mul2
-  %1 = load i32* %arrayidx3, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %C, i64 %mul2
+  %1 = load i32, i32* %arrayidx3, align 4
   %mul4 = mul nsw i32 %1, %0
   %mul3 = mul nsw i64 %indvars.iv, %AStride
-  %arrayidx7 = getelementptr inbounds i32* %A, i64 %mul3
+  %arrayidx7 = getelementptr inbounds i32, i32* %A, i64 %mul3
   store i32 %mul4, i32* %arrayidx7, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
@@ -70,9 +76,9 @@ for.body:
   %0 = trunc i64 %indvars.iv to i32
   %mul = mul nsw i32 %0, %conv
   %idxprom = sext i32 %mul to i64
-  %arrayidx = getelementptr inbounds double* %x, i64 %idxprom
-  %1 = load double* %arrayidx, align 8
-  %arrayidx3 = getelementptr inbounds double* %c, i64 %indvars.iv
+  %arrayidx = getelementptr inbounds double, double* %x, i64 %idxprom
+  %1 = load double, double* %arrayidx, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %c, i64 %indvars.iv
   store double %1, double* %arrayidx3, align 8
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
diff --git a/test/Transforms/LoopVectorize/write-only.ll b/test/Transforms/LoopVectorize/write-only.ll
index 2f100de82370..b2bc0458a23a 100644
--- a/test/Transforms/LoopVectorize/write-only.ll
+++ b/test/Transforms/LoopVectorize/write-only.ll
@@ -12,8 +12,8 @@ define i32 @read_mod_write_single_ptr(float* nocapture %a, i32 %n) nounwind uwta
 
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
-  %2 = getelementptr inbounds float* %a, i64 %indvars.iv
-  %3 = load float* %2, align 4
+  %2 = getelementptr inbounds float, float* %a, i64 %indvars.iv
+  %3 = load float, float* %2, align 4
   %4 = fmul float %3, 3.000000e+00
   store float %4, float* %2, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
diff --git a/test/Transforms/LowerAtomic/atomic-swap.ll b/test/Transforms/LowerAtomic/atomic-swap.ll
index cb1124136f86..77000527a11f 100644
--- a/test/Transforms/LowerAtomic/atomic-swap.ll
+++ b/test/Transforms/LowerAtomic/atomic-swap.ll
@@ -5,7 +5,7 @@ define i8 @cmpswap() {
   %i = alloca i8
   %pair = cmpxchg i8* %i, i8 0, i8 42 monotonic monotonic
   %j = extractvalue { i8, i1 } %pair, 0
-; CHECK: [[OLDVAL:%[a-z0-9]+]] = load i8* [[ADDR:%[a-z0-9]+]]
+; CHECK: [[OLDVAL:%[a-z0-9]+]] = load i8, i8* [[ADDR:%[a-z0-9]+]]
 ; CHECK-NEXT: [[SAME:%[a-z0-9]+]] = icmp eq i8 [[OLDVAL]], 0
 ; CHECK-NEXT: [[TO_STORE:%[a-z0-9]+]] = select i1 [[SAME]], i8 42, i8 [[OLDVAL]]
 ; CHECK-NEXT: store i8 [[TO_STORE]], i8* [[ADDR]]
diff --git a/test/Transforms/LowerBitSets/constant.ll b/test/Transforms/LowerBitSets/constant.ll
new file mode 100644
index 000000000000..99c925914f72
--- /dev/null
+++ b/test/Transforms/LowerBitSets/constant.ll
@@ -0,0 +1,34 @@
+; RUN: opt -S -lowerbitsets < %s | FileCheck %s
+
+target datalayout = "e-p:32:32"
+
+@a = constant i32 1
+@b = constant [2 x i32] [i32 2, i32 3]
+
+!0 = !{!"bitset1", i32* @a, i32 0}
+!1 = !{!"bitset1", [2 x i32]* @b, i32 4}
+
+!llvm.bitsets = !{ !0, !1 }
+
+declare i1 @llvm.bitset.test(i8* %ptr, metadata %bitset) nounwind readnone
+
+; CHECK: @foo(
+define i1 @foo() {
+  ; CHECK: ret i1 true
+  %x = call i1 @llvm.bitset.test(i8* bitcast (i32* @a to i8*), metadata !"bitset1")
+  ret i1 %x
+}
+
+; CHECK: @bar(
+define i1 @bar() {
+  ; CHECK: ret i1 true
+  %x = call i1 @llvm.bitset.test(i8* bitcast (i32* getelementptr ([2 x i32], [2 x i32]* @b, i32 0, i32 1) to i8*), metadata !"bitset1")
+  ret i1 %x
+}
+
+; CHECK: @baz(
+define i1 @baz() {
+  ; CHECK-NOT: ret i1 true
+  %x = call i1 @llvm.bitset.test(i8* bitcast (i32* getelementptr ([2 x i32], [2 x i32]* @b, i32 0, i32 0) to i8*), metadata !"bitset1")
+  ret i1 %x
+}
diff --git a/test/Transforms/LowerBitSets/layout.ll b/test/Transforms/LowerBitSets/layout.ll
new file mode 100644
index 000000000000..a0c6e77a57fe
--- /dev/null
+++ b/test/Transforms/LowerBitSets/layout.ll
@@ -0,0 +1,35 @@
+; RUN: opt -S -lowerbitsets < %s | FileCheck %s
+
+target datalayout = "e-p:32:32"
+
+; Tests that this set of globals is laid out according to our layout algorithm
+; (see GlobalLayoutBuilder in include/llvm/Transforms/IPO/LowerBitSets.h).
+; The chosen layout in this case is a, e, b, d, c.
+
+; CHECK: private constant { i32, [0 x i8], i32, [0 x i8], i32, [0 x i8], i32, [0 x i8], i32 } { i32 1, [0 x i8] zeroinitializer, i32 5, [0 x i8] zeroinitializer, i32 2, [0 x i8] zeroinitializer, i32 4, [0 x i8] zeroinitializer, i32 3 }
+@a = constant i32 1
+@b = constant i32 2
+@c = constant i32 3
+@d = constant i32 4
+@e = constant i32 5
+
+!0 = !{!"bitset1", i32* @a, i32 0}
+!1 = !{!"bitset1", i32* @b, i32 0}
+!2 = !{!"bitset1", i32* @c, i32 0}
+
+!3 = !{!"bitset2", i32* @b, i32 0}
+!4 = !{!"bitset2", i32* @d, i32 0}
+
+!5 = !{!"bitset3", i32* @a, i32 0}
+!6 = !{!"bitset3", i32* @e, i32 0}
+
+!llvm.bitsets = !{ !0, !1, !2, !3, !4, !5, !6 }
+
+declare i1 @llvm.bitset.test(i8* %ptr, metadata %bitset) nounwind readnone
+
+define void @foo() {
+  %x = call i1 @llvm.bitset.test(i8* undef, metadata !"bitset1")
+  %y = call i1 @llvm.bitset.test(i8* undef, metadata !"bitset2")
+  %z = call i1 @llvm.bitset.test(i8* undef, metadata !"bitset3")
+  ret void
+}
diff --git a/test/Transforms/LowerBitSets/simple.ll b/test/Transforms/LowerBitSets/simple.ll
new file mode 100644
index 000000000000..0fcdf0b36d63
--- /dev/null
+++ b/test/Transforms/LowerBitSets/simple.ll
@@ -0,0 +1,137 @@
+; RUN: opt -S -lowerbitsets < %s | FileCheck %s
+; RUN: opt -S -lowerbitsets -mtriple=x86_64-apple-macosx10.8.0 < %s | FileCheck -check-prefix=CHECK-DARWIN %s
+; RUN: opt -S -O3 < %s | FileCheck -check-prefix=CHECK-NODISCARD %s
+
+target datalayout = "e-p:32:32"
+
+; CHECK: [[G:@[^ ]*]] = private constant { i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] } { i32 1, [0 x i8] zeroinitializer, [63 x i32] zeroinitializer, [4 x i8] zeroinitializer, i32 3, [0 x i8] zeroinitializer, [2 x i32] [i32 4, i32 5] }
+@a = constant i32 1
+@b = constant [63 x i32] zeroinitializer
+@c = constant i32 3
+@d = constant [2 x i32] [i32 4, i32 5]
+
+; CHECK: [[BA:@[^ ]*]] = private constant [68 x i8] c"\03\01\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\02\00\01"
+
+; Offset 0, 4 byte alignment
+!0 = !{!"bitset1", i32* @a, i32 0}
+; CHECK-NODISCARD-DAG: !{!"bitset1", i32* @a, i32 0}
+!1 = !{!"bitset1", [63 x i32]* @b, i32 0}
+; CHECK-NODISCARD-DAG: !{!"bitset1", [63 x i32]* @b, i32 0}
+!2 = !{!"bitset1", [2 x i32]* @d, i32 4}
+; CHECK-NODISCARD-DAG: !{!"bitset1", [2 x i32]* @d, i32 4}
+
+; Offset 4, 256 byte alignment
+!3 = !{!"bitset2", [63 x i32]* @b, i32 0}
+; CHECK-NODISCARD-DAG: !{!"bitset2", [63 x i32]* @b, i32 0}
+!4 = !{!"bitset2", i32* @c, i32 0}
+; CHECK-NODISCARD-DAG: !{!"bitset2", i32* @c, i32 0}
+
+; Offset 0, 4 byte alignment
+!5 = !{!"bitset3", i32* @a, i32 0}
+; CHECK-NODISCARD-DAG: !{!"bitset3", i32* @a, i32 0}
+!6 = !{!"bitset3", i32* @c, i32 0}
+; CHECK-NODISCARD-DAG: !{!"bitset3", i32* @c, i32 0}
+
+; Entries whose second operand is null (the result of a global being DCE'd)
+; should be ignored.
+!7 = !{!"bitset2", null, i32 0}
+
+!llvm.bitsets = !{ !0, !1, !2, !3, !4, !5, !6, !7 }
+
+; CHECK: @bits_use{{[0-9]*}} = private alias i8* @bits{{[0-9]*}}
+; CHECK: @bits_use.{{[0-9]*}} = private alias i8* @bits{{[0-9]*}}
+; CHECK: @bits_use.{{[0-9]*}} = private alias i8* @bits{{[0-9]*}}
+
+; CHECK: @a = alias getelementptr inbounds ({ i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }, { i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }* [[G]], i32 0, i32 0)
+; CHECK: @b = alias getelementptr inbounds ({ i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }, { i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }* [[G]], i32 0, i32 2)
+; CHECK: @c = alias getelementptr inbounds ({ i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }, { i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }* [[G]], i32 0, i32 4)
+; CHECK: @d = alias getelementptr inbounds ({ i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }, { i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }* [[G]], i32 0, i32 6)
+
+; CHECK-DARWIN: @aptr = constant i32* getelementptr inbounds ({ i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }, { i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }* [[G:@[^ ]*]], i32 0, i32 0)
+@aptr = constant i32* @a
+
+; CHECK-DARWIN: @bptr = constant [63 x i32]* getelementptr inbounds ({ i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }, { i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }* [[G]], i32 0, i32 2)
+@bptr = constant [63 x i32]* @b
+
+; CHECK-DARWIN: @cptr = constant i32* getelementptr inbounds ({ i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }, { i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }* [[G]], i32 0, i32 4)
+@cptr = constant i32* @c
+
+; CHECK-DARWIN: @dptr = constant [2 x i32]* getelementptr inbounds ({ i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }, { i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }* [[G]], i32 0, i32 6)
+@dptr = constant [2 x i32]* @d
+
+; CHECK-DARWIN: [[G]] = private constant
+
+; CHECK: @bits{{[0-9]*}} = private alias getelementptr inbounds ([68 x i8], [68 x i8]* [[BA]], i32 0, i32 0)
+; CHECK: @bits.{{[0-9]*}} = private alias getelementptr inbounds ([68 x i8], [68 x i8]* [[BA]], i32 0, i32 0)
+
+declare i1 @llvm.bitset.test(i8* %ptr, metadata %bitset) nounwind readnone
+
+; CHECK: @foo(i32* [[A0:%[^ ]*]])
+define i1 @foo(i32* %p) {
+  ; CHECK-NOT: llvm.bitset.test
+
+  ; CHECK: [[R0:%[^ ]*]] = bitcast i32* [[A0]] to i8*
+  %pi8 = bitcast i32* %p to i8*
+  ; CHECK: [[R1:%[^ ]*]] = ptrtoint i8* [[R0]] to i32
+  ; CHECK: [[R2:%[^ ]*]] = sub i32 [[R1]], ptrtoint ({ i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }* [[G]] to i32)
+  ; CHECK: [[R3:%[^ ]*]] = lshr i32 [[R2]], 2
+  ; CHECK: [[R4:%[^ ]*]] = shl i32 [[R2]], 30
+  ; CHECK: [[R5:%[^ ]*]] = or i32 [[R3]], [[R4]]
+  ; CHECK: [[R6:%[^ ]*]] = icmp ult i32 [[R5]], 68
+  ; CHECK: br i1 [[R6]]
+
+  ; CHECK: [[R8:%[^ ]*]] = getelementptr i8, i8* @bits_use.{{[0-9]*}}, i32 [[R5]]
+  ; CHECK: [[R9:%[^ ]*]] = load i8, i8* [[R8]]
+  ; CHECK: [[R10:%[^ ]*]] = and i8 [[R9]], 1
+  ; CHECK: [[R11:%[^ ]*]] = icmp ne i8 [[R10]], 0
+
+  ; CHECK: [[R16:%[^ ]*]] = phi i1 [ false, {{%[^ ]*}} ], [ [[R11]], {{%[^ ]*}} ]
+  %x = call i1 @llvm.bitset.test(i8* %pi8, metadata !"bitset1")
+
+  ; CHECK-NOT: llvm.bitset.test
+  %y = call i1 @llvm.bitset.test(i8* %pi8, metadata !"bitset1")
+
+  ; CHECK: ret i1 [[R16]]
+  ret i1 %x
+}
+
+; CHECK: @bar(i32* [[B0:%[^ ]*]])
+define i1 @bar(i32* %p) {
+  ; CHECK: [[S0:%[^ ]*]] = bitcast i32* [[B0]] to i8*
+  %pi8 = bitcast i32* %p to i8*
+  ; CHECK: [[S1:%[^ ]*]] = ptrtoint i8* [[S0]] to i32
+  ; CHECK: [[S2:%[^ ]*]] = sub i32 [[S1]], add (i32 ptrtoint ({ i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }* [[G]] to i32), i32 4)
+  ; CHECK: [[S3:%[^ ]*]] = lshr i32 [[S2]], 8
+  ; CHECK: [[S4:%[^ ]*]] = shl i32 [[S2]], 24
+  ; CHECK: [[S5:%[^ ]*]] = or i32 [[S3]], [[S4]]
+  ; CHECK: [[S6:%[^ ]*]] = icmp ult i32 [[S5]], 2
+  %x = call i1 @llvm.bitset.test(i8* %pi8, metadata !"bitset2")
+
+  ; CHECK: ret i1 [[S6]]
+  ret i1 %x
+}
+
+; CHECK: @baz(i32* [[C0:%[^ ]*]])
+define i1 @baz(i32* %p) {
+  ; CHECK: [[T0:%[^ ]*]] = bitcast i32* [[C0]] to i8*
+  %pi8 = bitcast i32* %p to i8*
+  ; CHECK: [[T1:%[^ ]*]] = ptrtoint i8* [[T0]] to i32
+  ; CHECK: [[T2:%[^ ]*]] = sub i32 [[T1]], ptrtoint ({ i32, [0 x i8], [63 x i32], [4 x i8], i32, [0 x i8], [2 x i32] }* [[G]] to i32)
+  ; CHECK: [[T3:%[^ ]*]] = lshr i32 [[T2]], 2
+  ; CHECK: [[T4:%[^ ]*]] = shl i32 [[T2]], 30
+  ; CHECK: [[T5:%[^ ]*]] = or i32 [[T3]], [[T4]]
+  ; CHECK: [[T6:%[^ ]*]] = icmp ult i32 [[T5]], 66
+  ; CHECK: br i1 [[T6]]
+
+  ; CHECK: [[T8:%[^ ]*]] = getelementptr i8, i8* @bits_use.{{[0-9]*}}, i32 [[T5]]
+  ; CHECK: [[T9:%[^ ]*]] = load i8, i8* [[T8]]
+  ; CHECK: [[T10:%[^ ]*]] = and i8 [[T9]], 2
+  ; CHECK: [[T11:%[^ ]*]] = icmp ne i8 [[T10]], 0
+
+  ; CHECK: [[T16:%[^ ]*]] = phi i1 [ false, {{%[^ ]*}} ], [ [[T11]], {{%[^ ]*}} ]
+  %x = call i1 @llvm.bitset.test(i8* %pi8, metadata !"bitset3")
+  ; CHECK: ret i1 [[T16]]
+  ret i1 %x
+}
+
+; CHECK-NOT: !llvm.bitsets
diff --git a/test/Transforms/LowerBitSets/single-offset.ll b/test/Transforms/LowerBitSets/single-offset.ll
new file mode 100644
index 000000000000..57194f42e096
--- /dev/null
+++ b/test/Transforms/LowerBitSets/single-offset.ll
@@ -0,0 +1,40 @@
+; RUN: opt -S -lowerbitsets < %s | FileCheck %s
+
+target datalayout = "e-p:32:32"
+
+; CHECK: [[G:@[^ ]*]] = private constant { i32, [0 x i8], i32 }
+@a = constant i32 1
+@b = constant i32 2
+
+!0 = !{!"bitset1", i32* @a, i32 0}
+!1 = !{!"bitset1", i32* @b, i32 0}
+!2 = !{!"bitset2", i32* @a, i32 0}
+!3 = !{!"bitset3", i32* @b, i32 0}
+
+!llvm.bitsets = !{ !0, !1, !2, !3 }
+
+declare i1 @llvm.bitset.test(i8* %ptr, metadata %bitset) nounwind readnone
+
+; CHECK: @foo(i8* [[A0:%[^ ]*]])
+define i1 @foo(i8* %p) {
+  ; CHECK: [[R0:%[^ ]*]] = ptrtoint i8* [[A0]] to i32
+  ; CHECK: [[R1:%[^ ]*]] = icmp eq i32 [[R0]], ptrtoint ({ i32, [0 x i8], i32 }* [[G]] to i32)
+  %x = call i1 @llvm.bitset.test(i8* %p, metadata !"bitset2")
+  ; CHECK: ret i1 [[R1]]
+  ret i1 %x
+}
+
+; CHECK: @bar(i8* [[B0:%[^ ]*]])
+define i1 @bar(i8* %p) {
+  ; CHECK: [[S0:%[^ ]*]] = ptrtoint i8* [[B0]] to i32
+  ; CHECK: [[S1:%[^ ]*]] = icmp eq i32 [[S0]], add (i32 ptrtoint ({ i32, [0 x i8], i32 }* [[G]] to i32), i32 4)
+  %x = call i1 @llvm.bitset.test(i8* %p, metadata !"bitset3")
+  ; CHECK: ret i1 [[S1]]
+  ret i1 %x
+}
+
+; CHECK: @x(
+define i1 @x(i8* %p) {
+  %x = call i1 @llvm.bitset.test(i8* %p, metadata !"bitset1")
+  ret i1 %x
+}
diff --git a/test/Transforms/LowerExpectIntrinsic/basic.ll b/test/Transforms/LowerExpectIntrinsic/basic.ll
index b15edc715141..73d9f44ee7e5 100644
--- a/test/Transforms/LowerExpectIntrinsic/basic.ll
+++ b/test/Transforms/LowerExpectIntrinsic/basic.ll
@@ -1,4 +1,5 @@
 ; RUN: opt -lower-expect -strip-dead-prototypes -S -o - < %s | FileCheck %s
+; RUN: opt -S -passes=lower-expect < %s | opt -strip-dead-prototypes -S | FileCheck %s
 
 ; CHECK-LABEL: @test1(
 define i32 @test1(i32 %x) nounwind uwtable ssp {
@@ -6,7 +7,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %cmp = icmp sgt i32 %tmp, 1
   %conv = zext i1 %cmp to i32
   %conv1 = sext i32 %conv to i64
@@ -17,7 +18,7 @@ entry:
   br i1 %tobool, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %call = call i32 (...)* @f()
+  %call = call i32 (...) @f()
   store i32 %call, i32* %retval
   br label %return
 
@@ -26,7 +27,7 @@ if.end:                                           ; preds = %entry
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -40,7 +41,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %conv = sext i32 %tmp to i64
   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
   %tobool = icmp ne i64 %expval, 0
@@ -49,7 +50,7 @@ entry:
   br i1 %tobool, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %call = call i32 (...)* @f()
+  %call = call i32 (...) @f()
   store i32 %call, i32* %retval
   br label %return
 
@@ -58,7 +59,7 @@ if.end:                                           ; preds = %entry
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -68,7 +69,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %tobool = icmp ne i32 %tmp, 0
   %lnot = xor i1 %tobool, true
   %lnot.ext = zext i1 %lnot to i32
@@ -80,7 +81,7 @@ entry:
   br i1 %tobool1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %call = call i32 (...)* @f()
+  %call = call i32 (...) @f()
   store i32 %call, i32* %retval
   br label %return
 
@@ -89,7 +90,7 @@ if.end:                                           ; preds = %entry
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -99,7 +100,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %tobool = icmp ne i32 %tmp, 0
   %lnot = xor i1 %tobool, true
   %lnot1 = xor i1 %lnot, true
@@ -112,7 +113,7 @@ entry:
   br i1 %tobool2, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %call = call i32 (...)* @f()
+  %call = call i32 (...) @f()
   store i32 %call, i32* %retval
   br label %return
 
@@ -121,7 +122,7 @@ if.end:                                           ; preds = %entry
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -131,7 +132,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %cmp = icmp slt i32 %tmp, 0
   %conv = zext i1 %cmp to i32
   %conv1 = sext i32 %conv to i64
@@ -142,7 +143,7 @@ entry:
   br i1 %tobool, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %call = call i32 (...)* @f()
+  %call = call i32 (...) @f()
   store i32 %call, i32* %retval
   br label %return
 
@@ -151,7 +152,7 @@ if.end:                                           ; preds = %entry
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -161,7 +162,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %conv = sext i32 %tmp to i64
   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
 ; CHECK: !prof !2
@@ -180,7 +181,7 @@ sw.epilog:                                        ; preds = %entry
   br label %return
 
 return:                                           ; preds = %sw.epilog, %sw.bb
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -190,7 +191,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %conv = sext i32 %tmp to i64
   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
 ; CHECK: !prof !3
@@ -201,7 +202,7 @@ entry:
   ]
 
 sw.bb:                                            ; preds = %entry, %entry
-  %tmp1 = load i32* %x.addr, align 4
+  %tmp1 = load i32, i32* %x.addr, align 4
   store i32 %tmp1, i32* %retval
   br label %return
 
@@ -210,7 +211,7 @@ sw.epilog:                                        ; preds = %entry
   br label %return
 
 return:                                           ; preds = %sw.epilog, %sw.bb
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -220,7 +221,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %cmp = icmp sgt i32 %tmp, 1
   %conv = zext i1 %cmp to i32
   %expval = call i32 @llvm.expect.i32(i32 %conv, i32 1)
@@ -230,7 +231,7 @@ entry:
   br i1 %tobool, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %call = call i32 (...)* @f()
+  %call = call i32 (...) @f()
   store i32 %call, i32* %retval
   br label %return
 
@@ -239,7 +240,7 @@ if.end:                                           ; preds = %entry
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -251,7 +252,7 @@ entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
-  %tmp = load i32* %x.addr, align 4
+  %tmp = load i32, i32* %x.addr, align 4
   %cmp = icmp sgt i32 %tmp, 1
   %expval = call i1 @llvm.expect.i1(i1 %cmp, i1 1)
 ; CHECK: !prof !0
@@ -259,7 +260,7 @@ entry:
   br i1 %expval, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %call = call i32 (...)* @f()
+  %call = call i32 (...) @f()
   store i32 %call, i32* %retval
   br label %return
 
@@ -268,7 +269,7 @@ if.end:                                           ; preds = %entry
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
diff --git a/test/Transforms/LowerInvoke/2003-12-10-Crash.ll b/test/Transforms/LowerInvoke/2003-12-10-Crash.ll
index 31f3d42225ab..fca8e868018a 100644
--- a/test/Transforms/LowerInvoke/2003-12-10-Crash.ll
+++ b/test/Transforms/LowerInvoke/2003-12-10-Crash.ll
@@ -15,8 +15,11 @@ invoke_cont.0:		; preds = %then
 			to label %try_exit unwind label %try_catch
 try_catch:		; preds = %invoke_cont.0, %then
 	%__tmp.0 = phi i32* [ null, %invoke_cont.0 ], [ null, %then ]		; <i32*> [#uses=0]
+  %res = landingpad { i8* } personality i32 (...)* @__gxx_personality_v0
+          cleanup
 	ret void
 try_exit:		; preds = %invoke_cont.0
 	ret void
 }
 
+declare i32 @__gxx_personality_v0(...)
diff --git a/test/Transforms/LowerSwitch/2014-06-10-SwitchContiguousOpt.ll b/test/Transforms/LowerSwitch/2014-06-10-SwitchContiguousOpt.ll
index 3673c04a8b81..22173b492c4c 100644
--- a/test/Transforms/LowerSwitch/2014-06-10-SwitchContiguousOpt.ll
+++ b/test/Transforms/LowerSwitch/2014-06-10-SwitchContiguousOpt.ll
@@ -6,7 +6,7 @@ entry:
   %retval = alloca i32, align 4
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
-  %0 = load i32* %a.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4
   switch i32 %0, label %sw.default [
     i32 0, label %sw.bb
     i32 1, label %sw.bb1
diff --git a/test/Transforms/LowerSwitch/2014-06-11-SwitchDefaultUnreachableOpt.ll b/test/Transforms/LowerSwitch/2014-06-11-SwitchDefaultUnreachableOpt.ll
index 0f737211f598..2652a6cc5e09 100644
--- a/test/Transforms/LowerSwitch/2014-06-11-SwitchDefaultUnreachableOpt.ll
+++ b/test/Transforms/LowerSwitch/2014-06-11-SwitchDefaultUnreachableOpt.ll
@@ -1,5 +1,8 @@
 ; RUN: opt < %s -lowerswitch -S | FileCheck %s
-; CHECK-NOT: {{.*}}icmp eq{{.*}}
+;
+; The switch is lowered with a single icmp.
+; CHECK: icmp
+; CHECK-NOT: icmp
 ;
 ;int foo(int a) {
 ;
@@ -14,11 +17,11 @@
 ;
 ;}
 
-define i32 @foo(i32 %a) nounwind ssp uwtable {
+define i32 @foo(i32 %a) {
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   store i32 %a, i32* %2, align 4
-  %3 = load i32* %2, align 4
+  %3 = load i32, i32* %2, align 4
   switch i32 %3, label %6 [
     i32 0, label %4
     i32 1, label %5
@@ -36,6 +39,6 @@ define i32 @foo(i32 %a) nounwind ssp uwtable {
   unreachable
 
 ; <label>:7
-  %8 = load i32* %1
+  %8 = load i32, i32* %1
   ret i32 %8
 }
diff --git a/test/Transforms/LowerSwitch/feature.ll b/test/Transforms/LowerSwitch/feature.ll
index 09d25f0b06d4..b82d93455436 100644
--- a/test/Transforms/LowerSwitch/feature.ll
+++ b/test/Transforms/LowerSwitch/feature.ll
@@ -4,49 +4,49 @@
 ; On output we should got binary comparison tree. Check that all is fine.
 
 ;CHECK:     entry:
-;CHECK-NEXT:  br label %NodeBlock19
+;CHECK-NEXT:  br label %NodeBlock.19
 
-;CHECK:     NodeBlock19:                                      ; preds = %entry
-;CHECK-NEXT:  %Pivot20 = icmp slt i32 %tmp158, 10
-;CHECK-NEXT:  br i1 %Pivot20, label %NodeBlock5, label %NodeBlock17
+;CHECK:     NodeBlock.19:                                      ; preds = %entry
+;CHECK-NEXT:  %Pivot.20 = icmp slt i32 %tmp158, 10
+;CHECK-NEXT:  br i1 %Pivot.20, label %NodeBlock.5, label %NodeBlock.17
 
-;CHECK:     NodeBlock17:                                      ; preds = %NodeBlock19
-;CHECK-NEXT:  %Pivot18 = icmp slt i32 %tmp158, 13
-;CHECK-NEXT:  br i1 %Pivot18, label %NodeBlock9, label %NodeBlock15
+;CHECK:     NodeBlock.17:                                      ; preds = %NodeBlock.19
+;CHECK-NEXT:  %Pivot.18 = icmp slt i32 %tmp158, 13
+;CHECK-NEXT:  br i1 %Pivot.18, label %NodeBlock.9, label %NodeBlock.15
 
-;CHECK:     NodeBlock15:                                      ; preds = %NodeBlock17
-;CHECK-NEXT:  %Pivot16 = icmp slt i32 %tmp158, 14
-;CHECK-NEXT:  br i1 %Pivot16, label %bb330, label %NodeBlock13
+;CHECK:     NodeBlock.15:                                      ; preds = %NodeBlock.17
+;CHECK-NEXT:  %Pivot.16 = icmp slt i32 %tmp158, 14
+;CHECK-NEXT:  br i1 %Pivot.16, label %bb330, label %NodeBlock.13
 
-;CHECK:     NodeBlock13:                                      ; preds = %NodeBlock15
-;CHECK-NEXT:  %Pivot14 = icmp slt i32 %tmp158, 15
-;CHECK-NEXT:  br i1 %Pivot14, label %bb332, label %LeafBlock11
+;CHECK:     NodeBlock.13:                                      ; preds = %NodeBlock.15
+;CHECK-NEXT:  %Pivot.14 = icmp slt i32 %tmp158, 15
+;CHECK-NEXT:  br i1 %Pivot.14, label %bb332, label %LeafBlock.11
 
-;CHECK:     LeafBlock11:                                      ; preds = %NodeBlock13
+;CHECK:     LeafBlock.11:                                      ; preds = %NodeBlock.13
 ;CHECK-NEXT:  %SwitchLeaf12 = icmp eq i32 %tmp158, 15
 ;CHECK-NEXT:  br i1 %SwitchLeaf12, label %bb334, label %NewDefault
 
-;CHECK:     NodeBlock9:                                       ; preds = %NodeBlock17
-;CHECK-NEXT:  %Pivot10 = icmp slt i32 %tmp158, 11
-;CHECK-NEXT:  br i1 %Pivot10, label %bb324, label %NodeBlock7
+;CHECK:     NodeBlock.9:                                       ; preds = %NodeBlock.17
+;CHECK-NEXT:  %Pivot.10 = icmp slt i32 %tmp158, 11
+;CHECK-NEXT:  br i1 %Pivot.10, label %bb324, label %NodeBlock.7
 
-;CHECK:     NodeBlock7:                                       ; preds = %NodeBlock9
-;CHECK-NEXT:  %Pivot8 = icmp slt i32 %tmp158, 12
-;CHECK-NEXT:  br i1 %Pivot8, label %bb326, label %bb328
+;CHECK:     NodeBlock.7:                                       ; preds = %NodeBlock.9
+;CHECK-NEXT:  %Pivot.8 = icmp slt i32 %tmp158, 12
+;CHECK-NEXT:  br i1 %Pivot.8, label %bb326, label %bb328
 
-;CHECK:     NodeBlock5:                                       ; preds = %NodeBlock19
-;CHECK-NEXT:  %Pivot6 = icmp slt i32 %tmp158, 7
-;CHECK-NEXT:  br i1 %Pivot6, label %NodeBlock, label %NodeBlock3
+;CHECK:     NodeBlock.5:                                       ; preds = %NodeBlock.19
+;CHECK-NEXT:  %Pivot.6 = icmp slt i32 %tmp158, 7
+;CHECK-NEXT:  br i1 %Pivot.6, label %NodeBlock, label %NodeBlock.3
 
-;CHECK:     NodeBlock3:                                       ; preds = %NodeBlock5
-;CHECK-NEXT:  %Pivot4 = icmp slt i32 %tmp158, 8
-;CHECK-NEXT:  br i1 %Pivot4, label %bb, label %NodeBlock1
+;CHECK:     NodeBlock.3:                                       ; preds = %NodeBlock.5
+;CHECK-NEXT:  %Pivot.4 = icmp slt i32 %tmp158, 8
+;CHECK-NEXT:  br i1 %Pivot.4, label %bb, label %NodeBlock.1
 
-;CHECK:     NodeBlock1:                                       ; preds = %NodeBlock3
-;CHECK-NEXT:  %Pivot2 = icmp slt i32 %tmp158, 9
-;CHECK-NEXT:  br i1 %Pivot2, label %bb338, label %bb322
+;CHECK:     NodeBlock.1:                                       ; preds = %NodeBlock.3
+;CHECK-NEXT:  %Pivot.2 = icmp slt i32 %tmp158, 9
+;CHECK-NEXT:  br i1 %Pivot.2, label %bb338, label %bb322
 
-;CHECK:     NodeBlock:                                        ; preds = %NodeBlock5
+;CHECK:     NodeBlock:                                        ; preds = %NodeBlock.5
 ;CHECK-NEXT:  %Pivot = icmp slt i32 %tmp158, 0
 ;CHECK-NEXT:  br i1 %Pivot, label %LeafBlock, label %bb338
 
diff --git a/test/Transforms/LowerSwitch/fold-popular-case-to-unreachable-default.ll b/test/Transforms/LowerSwitch/fold-popular-case-to-unreachable-default.ll
new file mode 100644
index 000000000000..54929c5bfca3
--- /dev/null
+++ b/test/Transforms/LowerSwitch/fold-popular-case-to-unreachable-default.ll
@@ -0,0 +1,110 @@
+; RUN: opt %s -lowerswitch -S | FileCheck %s
+
+define void @foo(i32 %x, i32* %p) {
+; Cases 2 and 4 are removed and become the new default case.
+; It is now enough to use two icmps to lower the switch.
+;
+; CHECK-LABEL: @foo
+; CHECK:       icmp slt i32 %x, 5
+; CHECK:       icmp eq i32 %x, 1
+; CHECK-NOT:   icmp
+;
+entry:
+  switch i32 %x, label %default [
+    i32 1, label %bb0
+    i32 2, label %popular
+    i32 4, label %popular
+    i32 5, label %bb1
+  ]
+bb0:
+  store i32 0, i32* %p
+  br label %exit
+bb1:
+  store i32 1, i32* %p
+  br label %exit
+popular:
+  store i32 2, i32* %p
+  br label %exit
+exit:
+  ret void
+default:
+  unreachable
+}
+
+define void @unreachable_gap(i64 %x, i32* %p) {
+; Cases 6 and INT64_MAX become the new default, but we still exploit the fact
+; that 3-4 is unreachable, so four icmps is enough.
+
+; CHECK-LABEL: @unreachable_gap
+; CHECK:       icmp slt i64 %x, 2
+; CHECK:       icmp slt i64 %x, 5
+; CHECK:       icmp eq  i64 %x, 5
+; CHECK:       icmp slt i64 %x, 1
+; CHECK-NOT:   icmp
+
+entry:
+  switch i64 %x, label %default [
+    i64 -9223372036854775808, label %bb0
+    i64 1, label %bb1
+    i64 2, label %bb2
+    i64 5, label %bb3
+    i64 6, label %bb4
+    i64 9223372036854775807, label %bb4
+  ]
+bb0:
+  store i32 0, i32* %p
+  br label %exit
+bb1:
+  store i32 1, i32* %p
+  br label %exit
+bb2:
+  store i32 2, i32* %p
+  br label %exit
+bb3:
+  store i32 3, i32* %p
+  br label %exit
+bb4:
+  store i32 4, i32* %p
+  br label %exit
+exit:
+  ret void
+default:
+  unreachable
+}
+
+
+
+define void @nocases(i32 %x, i32* %p) {
+; Don't fall over when there are no cases.
+;
+; CHECK-LABEL: @nocases
+; CHECK-LABEL: entry
+; CHECK-NEXT:  br label %default
+;
+entry:
+  switch i32 %x, label %default [
+  ]
+default:
+  unreachable
+}
+
+define void @nocasesleft(i32 %x, i32* %p) {
+; Cases 2 and 4 are removed and we are left with no cases.
+;
+; CHECK-LABEL: @nocasesleft
+; CHECK-LABEL: entry
+; CHECK-NEXT:  br label %popular
+;
+entry:
+  switch i32 %x, label %default [
+    i32 2, label %popular
+    i32 4, label %popular
+  ]
+popular:
+  store i32 2, i32* %p
+  br label %exit
+exit:
+  ret void
+default:
+  unreachable
+}
diff --git a/test/Transforms/Mem2Reg/2002-03-28-UninitializedVal.ll b/test/Transforms/Mem2Reg/2002-03-28-UninitializedVal.ll
index 777f3757bb89..49b560551d4e 100644
--- a/test/Transforms/Mem2Reg/2002-03-28-UninitializedVal.ll
+++ b/test/Transforms/Mem2Reg/2002-03-28-UninitializedVal.ll
@@ -6,6 +6,6 @@
 define i32 @test() {
         ; To be promoted
 	%X = alloca i32		; <i32*> [#uses=1]
-	%Y = load i32* %X		; <i32> [#uses=1]
+	%Y = load i32, i32* %X		; <i32> [#uses=1]
 	ret i32 %Y
 }
diff --git a/test/Transforms/Mem2Reg/2003-04-24-MultipleIdenticalSuccessors.ll b/test/Transforms/Mem2Reg/2003-04-24-MultipleIdenticalSuccessors.ll
index f5f1ee34365d..a013ff401f6c 100644
--- a/test/Transforms/Mem2Reg/2003-04-24-MultipleIdenticalSuccessors.ll
+++ b/test/Transforms/Mem2Reg/2003-04-24-MultipleIdenticalSuccessors.ll
@@ -10,7 +10,7 @@ B2:		; preds = %0
 	store i32 2, i32* %X
 	br i1 %c2, label %Exit, label %Exit
 Exit:		; preds = %B2, %B2, %0
-	%Y = load i32* %X		; <i32> [#uses=1]
+	%Y = load i32, i32* %X		; <i32> [#uses=1]
 	ret i32 %Y
 }
 
diff --git a/test/Transforms/Mem2Reg/2003-06-26-IterativePromote.ll b/test/Transforms/Mem2Reg/2003-06-26-IterativePromote.ll
index e82caa9fe0f6..de7280e4d8e3 100644
--- a/test/Transforms/Mem2Reg/2003-06-26-IterativePromote.ll
+++ b/test/Transforms/Mem2Reg/2003-06-26-IterativePromote.ll
@@ -7,10 +7,10 @@ define i32 @test2() {
 	%p = alloca i32*		; <i32**> [#uses=2]
 	store i32 0, i32* %a
 	store i32* %a, i32** %p
-	%tmp.0 = load i32** %p		; <i32*> [#uses=1]
-	%tmp.1 = load i32* %tmp.0		; <i32> [#uses=1]
+	%tmp.0 = load i32*, i32** %p		; <i32*> [#uses=1]
+	%tmp.1 = load i32, i32* %tmp.0		; <i32> [#uses=1]
 	store i32 %tmp.1, i32* %result
-	%tmp.2 = load i32* %result		; <i32> [#uses=1]
+	%tmp.2 = load i32, i32* %result		; <i32> [#uses=1]
 	ret i32 %tmp.2
 }
 
diff --git a/test/Transforms/Mem2Reg/2003-10-05-DeadPHIInsertion.ll b/test/Transforms/Mem2Reg/2003-10-05-DeadPHIInsertion.ll
index 1d38efc74576..8d55a1d0fa10 100644
--- a/test/Transforms/Mem2Reg/2003-10-05-DeadPHIInsertion.ll
+++ b/test/Transforms/Mem2Reg/2003-10-05-DeadPHIInsertion.ll
@@ -9,11 +9,11 @@ define void @test(i32 %B, i1 %C) {
 	br i1 %C, label %L1, label %L2
 L1:		; preds = %0
 	store i32 %B, i32* %A
-	%D = load i32* %A		; <i32> [#uses=1]
+	%D = load i32, i32* %A		; <i32> [#uses=1]
 	call void @test( i32 %D, i1 false )
 	br label %L3
 L2:		; preds = %0
-	%E = load i32* %A		; <i32> [#uses=1]
+	%E = load i32, i32* %A		; <i32> [#uses=1]
 	call void @test( i32 %E, i1 true )
 	br label %L3
 L3:		; preds = %L2, %L1
diff --git a/test/Transforms/Mem2Reg/2005-06-30-ReadBeforeWrite.ll b/test/Transforms/Mem2Reg/2005-06-30-ReadBeforeWrite.ll
index 74355961fbf9..f0f1fdc7ee2b 100644
--- a/test/Transforms/Mem2Reg/2005-06-30-ReadBeforeWrite.ll
+++ b/test/Transforms/Mem2Reg/2005-06-30-ReadBeforeWrite.ll
@@ -14,31 +14,31 @@ entry:
 	store i32 0, i32* %i
 	br label %loopentry
 loopentry:		; preds = %endif, %entry
-	%tmp.0 = load i32* %n_addr		; <i32> [#uses=1]
+	%tmp.0 = load i32, i32* %n_addr		; <i32> [#uses=1]
 	%tmp.1 = add i32 %tmp.0, 1		; <i32> [#uses=1]
-	%tmp.2 = load i32* %i		; <i32> [#uses=1]
+	%tmp.2 = load i32, i32* %i		; <i32> [#uses=1]
 	%tmp.3 = icmp sgt i32 %tmp.1, %tmp.2		; <i1> [#uses=2]
 	%tmp.4 = zext i1 %tmp.3 to i32		; <i32> [#uses=0]
 	br i1 %tmp.3, label %no_exit, label %return
 no_exit:		; preds = %loopentry
-	%tmp.5 = load i32* %undef		; <i32> [#uses=1]
+	%tmp.5 = load i32, i32* %undef		; <i32> [#uses=1]
 	store i32 %tmp.5, i32* %out
 	store i32 0, i32* %undef
-	%tmp.6 = load i32* %i		; <i32> [#uses=1]
+	%tmp.6 = load i32, i32* %i		; <i32> [#uses=1]
 	%tmp.7 = icmp sgt i32 %tmp.6, 0		; <i1> [#uses=2]
 	%tmp.8 = zext i1 %tmp.7 to i32		; <i32> [#uses=0]
 	br i1 %tmp.7, label %then, label %endif
 then:		; preds = %no_exit
-	%tmp.9 = load i8** %p_addr		; <i8*> [#uses=1]
-	%tmp.10 = load i32* %i		; <i32> [#uses=1]
+	%tmp.9 = load i8*, i8** %p_addr		; <i8*> [#uses=1]
+	%tmp.10 = load i32, i32* %i		; <i32> [#uses=1]
 	%tmp.11 = sub i32 %tmp.10, 1		; <i32> [#uses=1]
-	%tmp.12 = getelementptr i8* %tmp.9, i32 %tmp.11		; <i8*> [#uses=1]
-	%tmp.13 = load i32* %out		; <i32> [#uses=1]
+	%tmp.12 = getelementptr i8, i8* %tmp.9, i32 %tmp.11		; <i8*> [#uses=1]
+	%tmp.13 = load i32, i32* %out		; <i32> [#uses=1]
 	%tmp.14 = trunc i32 %tmp.13 to i8		; <i8> [#uses=1]
 	store i8 %tmp.14, i8* %tmp.12
 	br label %endif
 endif:		; preds = %then, %no_exit
-	%tmp.15 = load i32* %i		; <i32> [#uses=1]
+	%tmp.15 = load i32, i32* %i		; <i32> [#uses=1]
 	%inc = add i32 %tmp.15, 1		; <i32> [#uses=1]
 	store i32 %inc, i32* %i
 	br label %loopentry
diff --git a/test/Transforms/Mem2Reg/2005-11-28-Crash.ll b/test/Transforms/Mem2Reg/2005-11-28-Crash.ll
index 8fd3351ba42d..4b1d7f6651f3 100644
--- a/test/Transforms/Mem2Reg/2005-11-28-Crash.ll
+++ b/test/Transforms/Mem2Reg/2005-11-28-Crash.ll
@@ -41,7 +41,7 @@ endif.3:		; preds = %then.3, %endif.1
 loopexit:		; preds = %loopentry
 	br label %endif.4
 then.4:		; No predecessors!
-	%tmp.61 = load i32* %flags		; <i32> [#uses=0]
+	%tmp.61 = load i32, i32* %flags		; <i32> [#uses=0]
 	br label %out
 dead_block_after_goto:		; No predecessors!
 	br label %endif.4
diff --git a/test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll b/test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll
index ea581d197e58..891af9843ed7 100644
--- a/test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll
+++ b/test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll
@@ -15,14 +15,14 @@ entry:
 	%tmp = alloca i32, align 4		; <i32*> [#uses=3]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store volatile i32 0, i32* %v, align 4
-	%tmp1 = call i32 @_setjmp( %struct.__jmp_buf_tag* getelementptr ([1 x %struct.__jmp_buf_tag]* @j, i32 0, i32 0) )		; <i32> [#uses=1]
+	%tmp1 = call i32 @_setjmp( %struct.__jmp_buf_tag* getelementptr ([1 x %struct.__jmp_buf_tag], [1 x %struct.__jmp_buf_tag]* @j, i32 0, i32 0) )		; <i32> [#uses=1]
 	%tmp2 = icmp ne i32 %tmp1, 0		; <i1> [#uses=1]
 	%tmp23 = zext i1 %tmp2 to i8		; <i8> [#uses=1]
 	%toBool = icmp ne i8 %tmp23, 0		; <i1> [#uses=1]
 	br i1 %toBool, label %bb, label %bb5
 
 bb:		; preds = %entry
-	%tmp4 = load volatile i32* %v, align 4		; <i32> [#uses=1]
+	%tmp4 = load volatile i32, i32* %v, align 4		; <i32> [#uses=1]
 	store i32 %tmp4, i32* %tmp, align 4
 	br label %bb6
 
@@ -33,12 +33,12 @@ bb5:		; preds = %entry
 	br label %bb6
 
 bb6:		; preds = %bb5, %bb
-	%tmp7 = load i32* %tmp, align 4		; <i32> [#uses=1]
+	%tmp7 = load i32, i32* %tmp, align 4		; <i32> [#uses=1]
 	store i32 %tmp7, i32* %retval, align 4
 	br label %return
 
 return:		; preds = %bb6
-	%retval8 = load i32* %retval		; <i32> [#uses=1]
+	%retval8 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval8
 }
 
diff --git a/test/Transforms/Mem2Reg/ConvertDebugInfo.ll b/test/Transforms/Mem2Reg/ConvertDebugInfo.ll
index a7369c0902b9..8a2eedd96baf 100644
--- a/test/Transforms/Mem2Reg/ConvertDebugInfo.ll
+++ b/test/Transforms/Mem2Reg/ConvertDebugInfo.ll
@@ -7,26 +7,26 @@ entry:
   %retval = alloca double                         ; <double*> [#uses=2]
   %0 = alloca double                              ; <double*> [#uses=2]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.declare(metadata i32* %i_addr, metadata !0, metadata !{}), !dbg !8
+  call void @llvm.dbg.declare(metadata i32* %i_addr, metadata !0, metadata !DIExpression()), !dbg !8
 ; CHECK: call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata ![[IVAR:[0-9]*]], metadata {{.*}})
 ; CHECK: call void @llvm.dbg.value(metadata double %j, i64 0, metadata ![[JVAR:[0-9]*]], metadata {{.*}})
-; CHECK: ![[IVAR]] = {{.*}} ; [ DW_TAG_arg_variable ] [i]
-; CHECK: ![[JVAR]] = {{.*}} ; [ DW_TAG_arg_variable ] [j]
+; CHECK: ![[IVAR]] = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i"
+; CHECK: ![[JVAR]] = !DILocalVariable(tag: DW_TAG_arg_variable, name: "j"
   store i32 %i, i32* %i_addr
-  call void @llvm.dbg.declare(metadata double* %j_addr, metadata !9, metadata !{}), !dbg !8
+  call void @llvm.dbg.declare(metadata double* %j_addr, metadata !9, metadata !DIExpression()), !dbg !8
   store double %j, double* %j_addr
-  %1 = load i32* %i_addr, align 4, !dbg !10       ; <i32> [#uses=1]
+  %1 = load i32, i32* %i_addr, align 4, !dbg !10       ; <i32> [#uses=1]
   %2 = add nsw i32 %1, 1, !dbg !10                ; <i32> [#uses=1]
   %3 = sitofp i32 %2 to double, !dbg !10          ; <double> [#uses=1]
-  %4 = load double* %j_addr, align 8, !dbg !10    ; <double> [#uses=1]
+  %4 = load double, double* %j_addr, align 8, !dbg !10    ; <double> [#uses=1]
   %5 = fadd double %3, %4, !dbg !10               ; <double> [#uses=1]
   store double %5, double* %0, align 8, !dbg !10
-  %6 = load double* %0, align 8, !dbg !10         ; <double> [#uses=1]
+  %6 = load double, double* %0, align 8, !dbg !10         ; <double> [#uses=1]
   store double %6, double* %retval, align 8, !dbg !10
   br label %return, !dbg !10
 
 return:                                           ; preds = %entry
-  %retval1 = load double* %retval, !dbg !10       ; <double> [#uses=1]
+  %retval1 = load double, double* %retval, !dbg !10       ; <double> [#uses=1]
   ret double %retval1, !dbg !10
 }
 
@@ -35,18 +35,18 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!3}
 !llvm.module.flags = !{!14}
 
-!0 = !{!"0x101\00i\002\000", !1, !2, !7} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00testfunc\00testfunc\00testfunc\002\000\001\000\006\000\000\002", !12, !2, !4, null, double (i32, double)* @testfunc, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !12} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\001\00\000\00\000", !12, !13, !13, null, null, null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !12, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 2, arg: 0, scope: !1, file: !2, type: !7)
+!1 = !DISubprogram(name: "testfunc", linkageName: "testfunc", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 2, file: !12, scope: !2, type: !4, function: double (i32, double)* @testfunc)
+!2 = !DIFile(filename: "testfunc.c", directory: "/tmp")
+!3 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 0, file: !12, enums: !13, retainedTypes: !13)
+!4 = !DISubroutineType(types: !5)
 !5 = !{!6, !7, !6}
-!6 = !{!"0x24\00double\000\0064\0064\000\000\004", !12, !2} ; [ DW_TAG_base_type ]
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", !12, !2} ; [ DW_TAG_base_type ]
-!8 = !MDLocation(line: 2, scope: !1)
-!9 = !{!"0x101\00j\002\000", !1, !2, !6} ; [ DW_TAG_arg_variable ]
-!10 = !MDLocation(line: 3, scope: !11)
-!11 = !{!"0xb\002\000\000", !12, !1} ; [ DW_TAG_lexical_block ]
-!12 = !{!"testfunc.c", !"/tmp"}
-!13 = !{i32 0}
-!14 = !{i32 1, !"Debug Info Version", i32 2}
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 64, encoding: DW_ATE_float)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DILocation(line: 2, scope: !1)
+!9 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "j", line: 2, arg: 0, scope: !1, file: !2, type: !6)
+!10 = !DILocation(line: 3, scope: !11)
+!11 = distinct !DILexicalBlock(line: 2, column: 0, file: !12, scope: !1)
+!12 = !DIFile(filename: "testfunc.c", directory: "/tmp")
+!13 = !{}
+!14 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll b/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll
index 76d2a1aa7d2b..831221b7f97f 100644
--- a/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll
+++ b/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll
@@ -11,18 +11,18 @@ entry:
   %z_addr.i = alloca i8*                          ; <i8**> [#uses=2]
   %a_addr = alloca i32                            ; <i32*> [#uses=2]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  call void @llvm.dbg.declare(metadata i32* %a_addr, metadata !0, metadata !{}), !dbg !7
+  call void @llvm.dbg.declare(metadata i32* %a_addr, metadata !0, metadata !DIExpression()), !dbg !7
   store i32 %a, i32* %a_addr
-  %0 = load i32* %a_addr, align 4, !dbg !8        ; <i32> [#uses=1]
-  call void @llvm.dbg.declare(metadata i32* %x_addr.i, metadata !9, metadata !{}) nounwind, !dbg !15
+  %0 = load i32, i32* %a_addr, align 4, !dbg !8        ; <i32> [#uses=1]
+  call void @llvm.dbg.declare(metadata i32* %x_addr.i, metadata !9, metadata !DIExpression()) nounwind, !dbg !15
   store i32 %0, i32* %x_addr.i
-  call void @llvm.dbg.declare(metadata i64* %y_addr.i, metadata !16, metadata !{}) nounwind, !dbg !15
+  call void @llvm.dbg.declare(metadata i64* %y_addr.i, metadata !16, metadata !DIExpression()) nounwind, !dbg !15
   store i64 55, i64* %y_addr.i
-  call void @llvm.dbg.declare(metadata i8** %z_addr.i, metadata !17, metadata !{}) nounwind, !dbg !15
+  call void @llvm.dbg.declare(metadata i8** %z_addr.i, metadata !17, metadata !DIExpression()) nounwind, !dbg !15
   store i8* bitcast (void (i32)* @baz to i8*), i8** %z_addr.i
-  %1 = load i32* %x_addr.i, align 4, !dbg !18     ; <i32> [#uses=1]
-  %2 = load i64* %y_addr.i, align 8, !dbg !18     ; <i64> [#uses=1]
-  %3 = load i8** %z_addr.i, align 8, !dbg !18     ; <i8*> [#uses=1]
+  %1 = load i32, i32* %x_addr.i, align 4, !dbg !18     ; <i32> [#uses=1]
+  %2 = load i64, i64* %y_addr.i, align 8, !dbg !18     ; <i64> [#uses=1]
+  %3 = load i8*, i8** %z_addr.i, align 8, !dbg !18     ; <i8*> [#uses=1]
   call void @foo(i32 %1, i64 %2, i8* %3) nounwind, !dbg !18
   br label %return, !dbg !19
 
@@ -32,26 +32,26 @@ return:                                           ; preds = %entry
 
 !llvm.dbg.cu = !{!3}
 !llvm.module.flags = !{!22}
-!0 = !{!"0x101\00a\008\000", !1, !2, !6} ; [ DW_TAG_arg_variable ]
-!1 = !{!"0x2e\00baz\00baz\00baz\008\000\001\000\006\000\000\008", !20, !2, !4, null, void (i32)* @baz, null, null, null} ; [ DW_TAG_subprogram ]
-!2 = !{!"0x29", !20} ; [ DW_TAG_file_type ]
-!3 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\001\00\000\00\000", !20, !21, !21, null, null, null} ; [ DW_TAG_compile_unit ]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !20, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 8, arg: 0, scope: !1, file: !2, type: !6)
+!1 = !DISubprogram(name: "baz", linkageName: "baz", line: 8, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 8, file: !20, scope: !2, type: !4, function: void (i32)* @baz)
+!2 = !DIFile(filename: "bar.c", directory: "/tmp/")
+!3 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 0, file: !20, enums: !21, retainedTypes: !21)
+!4 = !DISubroutineType(types: !5)
 !5 = !{null, !6}
-!6 = !{!"0x24\00int\000\0032\0032\000\000\005", !20, !2} ; [ DW_TAG_base_type ]
-!7 = !MDLocation(line: 8, scope: !1)
-!8 = !MDLocation(line: 9, scope: !1)
-!9 = !{!"0x101\00x\004\000", !10, !2, !6} ; [ DW_TAG_arg_variable ]
-!10 = !{!"0x2e\00bar\00bar\00bar\004\001\001\000\006\000\000\004", !20, !2, !11, null, null, null, null, null} ; [ DW_TAG_subprogram ]
-!11 = !{!"0x15\00\000\000\000\000\000\000", !20, !2, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!7 = !DILocation(line: 8, scope: !1)
+!8 = !DILocation(line: 9, scope: !1)
+!9 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 4, arg: 0, scope: !10, file: !2, type: !6)
+!10 = !DISubprogram(name: "bar", linkageName: "bar", line: 4, isLocal: true, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 4, file: !20, scope: !2, type: !11)
+!11 = !DISubroutineType(types: !12)
 !12 = !{null, !6, !13, !14}
-!13 = !{!"0x24\00long int\000\0064\0064\000\000\005", !20, !2} ; [ DW_TAG_base_type ]
-!14 = !{!"0xf\00\000\0064\0064\000\000", !20, !2, null} ; [ DW_TAG_pointer_type ]
-!15 = !MDLocation(line: 4, scope: !10, inlinedAt: !8)
-!16 = !{!"0x101\00y\004\000", !10, !2, !13} ; [ DW_TAG_arg_variable ]
-!17 = !{!"0x101\00z\004\000", !10, !2, !14} ; [ DW_TAG_arg_variable ]
-!18 = !MDLocation(line: 5, scope: !10, inlinedAt: !8)
-!19 = !MDLocation(line: 10, scope: !1)
-!20 = !{!"bar.c", !"/tmp/"}
-!21 = !{i32 0}
-!22 = !{i32 1, !"Debug Info Version", i32 2}
+!13 = !DIBasicType(tag: DW_TAG_base_type, name: "long int", size: 64, align: 64, encoding: DW_ATE_signed)
+!14 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !20, scope: !2, baseType: null)
+!15 = !DILocation(line: 4, scope: !10, inlinedAt: !8)
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "y", line: 4, arg: 0, scope: !10, file: !2, type: !13)
+!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "z", line: 4, arg: 0, scope: !10, file: !2, type: !14)
+!18 = !DILocation(line: 5, scope: !10, inlinedAt: !8)
+!19 = !DILocation(line: 10, scope: !1)
+!20 = !DIFile(filename: "bar.c", directory: "/tmp/")
+!21 = !{}
+!22 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/Mem2Reg/PromoteMemToRegister.ll b/test/Transforms/Mem2Reg/PromoteMemToRegister.ll
index 1be6b03beec6..b7f39947afb4 100644
--- a/test/Transforms/Mem2Reg/PromoteMemToRegister.ll
+++ b/test/Transforms/Mem2Reg/PromoteMemToRegister.ll
@@ -6,12 +6,12 @@ define double @testfunc(i32 %i, double %j) {
 	%J = alloca double		; <double*> [#uses=2]
 	store i32 %i, i32* %I
 	store double %j, double* %J
-	%t1 = load i32* %I		; <i32> [#uses=1]
+	%t1 = load i32, i32* %I		; <i32> [#uses=1]
 	%t2 = add i32 %t1, 1		; <i32> [#uses=1]
 	store i32 %t2, i32* %I
-	%t3 = load i32* %I		; <i32> [#uses=1]
+	%t3 = load i32, i32* %I		; <i32> [#uses=1]
 	%t4 = sitofp i32 %t3 to double		; <double> [#uses=1]
-	%t5 = load double* %J		; <double> [#uses=1]
+	%t5 = load double, double* %J		; <double> [#uses=1]
 	%t6 = fmul double %t4, %t5		; <double> [#uses=1]
 	ret double %t6
 }
diff --git a/test/Transforms/Mem2Reg/UndefValuesMerge.ll b/test/Transforms/Mem2Reg/UndefValuesMerge.ll
index 5013229b77f9..eeeb72f8e5a4 100644
--- a/test/Transforms/Mem2Reg/UndefValuesMerge.ll
+++ b/test/Transforms/Mem2Reg/UndefValuesMerge.ll
@@ -7,7 +7,7 @@ T:		; preds = %0
 	store i32 %i, i32* %I
 	br label %Cont
 Cont:		; preds = %T, %0
-	%Y = load i32* %I		; <i32> [#uses=1]
+	%Y = load i32, i32* %I		; <i32> [#uses=1]
 	ret i32 %Y
 }
 
diff --git a/test/Transforms/Mem2Reg/atomic.ll b/test/Transforms/Mem2Reg/atomic.ll
index 5bc9e9281b27..f20043d9716a 100644
--- a/test/Transforms/Mem2Reg/atomic.ll
+++ b/test/Transforms/Mem2Reg/atomic.ll
@@ -7,6 +7,6 @@ define i32 @test1(i32 %x) {
 ; CHECK: ret i32 %x
   %a = alloca i32
   store atomic i32 %x, i32* %a seq_cst, align 4
-  %r = load atomic i32* %a seq_cst, align 4
+  %r = load atomic i32, i32* %a seq_cst, align 4
   ret i32 %r
 }
diff --git a/test/Transforms/Mem2Reg/crash.ll b/test/Transforms/Mem2Reg/crash.ll
index 59e2c0b3108d..a4a31b112ee8 100644
--- a/test/Transforms/Mem2Reg/crash.ll
+++ b/test/Transforms/Mem2Reg/crash.ll
@@ -14,7 +14,7 @@ invcont2:
   br label %bb15
 
 bb15:
-  %B = load i32* %whichFlag
+  %B = load i32, i32* %whichFlag
   ret i32 %B
 
 lpad86:
@@ -33,11 +33,11 @@ entry:
   br label %bb15
 
 bb15:
-  %B = load i32* %whichFlag
+  %B = load i32, i32* %whichFlag
   ret i32 %B
 
 invcont2:
-  %C = load i32* %whichFlag
+  %C = load i32, i32* %whichFlag
   store i32 %C, i32* %whichFlag
   br label %bb15
 }
diff --git a/test/Transforms/Mem2Reg/ignore-lifetime.ll b/test/Transforms/Mem2Reg/ignore-lifetime.ll
index 5e4f9bfd8c5b..12adaffc7714 100644
--- a/test/Transforms/Mem2Reg/ignore-lifetime.ll
+++ b/test/Transforms/Mem2Reg/ignore-lifetime.ll
@@ -18,7 +18,7 @@ define void @test2() {
 ; CHECK: test2
 ; CHECK-NOT: alloca
   %A = alloca {i8, i16}
-  %B = getelementptr {i8, i16}* %A, i32 0, i32 0
+  %B = getelementptr {i8, i16}, {i8, i16}* %A, i32 0, i32 0
   call void @llvm.lifetime.start(i64 2, i8* %B)
   store {i8, i16} zeroinitializer, {i8, i16}* %A
   call void @llvm.lifetime.end(i64 2, i8* %B)
diff --git a/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll b/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll
index 00ac34d93e79..f73addd62687 100644
--- a/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll
+++ b/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll
@@ -8,9 +8,9 @@ target triple = "i386-pc-linux-gnu"
 
 define internal fastcc void @initialize(%0* noalias nocapture sret %agg.result) nounwind {
 entry:
-  %agg.result.03 = getelementptr %0* %agg.result, i32 0, i32 0
+  %agg.result.03 = getelementptr %0, %0* %agg.result, i32 0, i32 0
   store x86_fp80 0xK00000000000000000000, x86_fp80* %agg.result.03
-  %agg.result.15 = getelementptr %0* %agg.result, i32 0, i32 1
+  %agg.result.15 = getelementptr %0, %0* %agg.result, i32 0, i32 1
   store x86_fp80 0xK00000000000000000000, x86_fp80* %agg.result.15
   ret void
 }
diff --git a/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll b/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll
index 6982c8bf2f85..ffbb2992557a 100644
--- a/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll
+++ b/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll
@@ -14,8 +14,8 @@ entry:
   %a_i8 = bitcast %a* %a_var to i8*
   %b_i8 = bitcast %b* %b_var to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %b_i8, i8* %a_i8, i32 4, i32 1, i1 false)
-  %tmp1 = getelementptr %b* %b_var, i32 0, i32 0
-  %tmp2 = load float* %tmp1
+  %tmp1 = getelementptr %b, %b* %b_var, i32 0, i32 0
+  %tmp2 = load float, float* %tmp1
   ret float %tmp2
 }
 
diff --git a/test/Transforms/MemCpyOpt/2011-06-02-CallSlotOverwritten.ll b/test/Transforms/MemCpyOpt/2011-06-02-CallSlotOverwritten.ll
index 132966ef6b98..8e4a0230d7fd 100644
--- a/test/Transforms/MemCpyOpt/2011-06-02-CallSlotOverwritten.ll
+++ b/test/Transforms/MemCpyOpt/2011-06-02-CallSlotOverwritten.ll
@@ -17,20 +17,20 @@ define i32 @foo() nounwind {
   call void @bar(%struct1* sret %x) nounwind
 ; CHECK: call void @bar(%struct1* sret %x)
 
-  %gepn1 = getelementptr inbounds %struct2* %y, i32 0, i32 0, i32 0
+  %gepn1 = getelementptr inbounds %struct2, %struct2* %y, i32 0, i32 0, i32 0
   store i32 0, i32* %gepn1, align 8
-  %gepn2 = getelementptr inbounds %struct2* %y, i32 0, i32 0, i32 1
+  %gepn2 = getelementptr inbounds %struct2, %struct2* %y, i32 0, i32 0, i32 1
   store i32 0, i32* %gepn2, align 4
 
   %bit1 = bitcast %struct1* %x to i64*
   %bit2 = bitcast %struct2* %y to i64*
-  %load = load i64* %bit1, align 8
+  %load = load i64, i64* %bit1, align 8
   store i64 %load, i64* %bit2, align 8
 
-; CHECK: %load = load i64* %bit1, align 8
+; CHECK: %load = load i64, i64* %bit1, align 8
 ; CHECK: store i64 %load, i64* %bit2, align 8
 
-  %gep1 = getelementptr %struct2* %y, i32 0, i32 0, i32 0
-  %ret = load i32* %gep1
+  %gep1 = getelementptr %struct2, %struct2* %y, i32 0, i32 0, i32 0
+  %ret = load i32, i32* %gep1
   ret i32 %ret
 }
diff --git a/test/Transforms/MemCpyOpt/align.ll b/test/Transforms/MemCpyOpt/align.ll
index 5d5bfbdafc5b..9074684f6c76 100644
--- a/test/Transforms/MemCpyOpt/align.ll
+++ b/test/Transforms/MemCpyOpt/align.ll
@@ -10,13 +10,13 @@ declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
 define void @foo(i32* %p) {
 ; CHECK-LABEL: @foo(
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* {{.*}}, i8 0, i64 16, i32 4, i1 false)
-  %a0 = getelementptr i32* %p, i64 0
+  %a0 = getelementptr i32, i32* %p, i64 0
   store i32 0, i32* %a0, align 4
-  %a1 = getelementptr i32* %p, i64 1
+  %a1 = getelementptr i32, i32* %p, i64 1
   store i32 0, i32* %a1, align 16
-  %a2 = getelementptr i32* %p, i64 2
+  %a2 = getelementptr i32, i32* %p, i64 2
   store i32 0, i32* %a2, align 4
-  %a3 = getelementptr i32* %p, i64 3
+  %a3 = getelementptr i32, i32* %p, i64 3
   store i32 0, i32* %a3, align 4
   ret void
 }
diff --git a/test/Transforms/MemCpyOpt/atomic.ll b/test/Transforms/MemCpyOpt/atomic.ll
index f351e6792e22..5be6b1555b56 100644
--- a/test/Transforms/MemCpyOpt/atomic.ll
+++ b/test/Transforms/MemCpyOpt/atomic.ll
@@ -16,9 +16,9 @@ define void @test1() nounwind uwtable ssp {
   %x = alloca [101 x i32], align 16
   %bc = bitcast [101 x i32]* %x to i8*
   call void @llvm.memset.p0i8.i64(i8* %bc, i8 0, i64 400, i32 16, i1 false)
-  %gep1 = getelementptr inbounds [101 x i32]* %x, i32 0, i32 100
+  %gep1 = getelementptr inbounds [101 x i32], [101 x i32]* %x, i32 0, i32 100
   store atomic i32 0, i32* %gep1 unordered, align 4
-  %gep2 = getelementptr inbounds [101 x i32]* %x, i32 0, i32 0
+  %gep2 = getelementptr inbounds [101 x i32], [101 x i32]* %x, i32 0, i32 0
   call void @otherf(i32* %gep2)
   ret void
 }
@@ -33,7 +33,7 @@ define void @test2() nounwind uwtable ssp {
   %new = alloca i32
   call void @otherf(i32* nocapture %old)
   store atomic i32 0, i32* @x unordered, align 4
-  %v = load i32* %old
+  %v = load i32, i32* %old
   store i32 %v, i32* %new
   call void @otherf(i32* nocapture %new)  
   ret void
diff --git a/test/Transforms/MemCpyOpt/callslot_deref.ll b/test/Transforms/MemCpyOpt/callslot_deref.ll
index 4d51552d0151..4c3e3e86bf38 100644
--- a/test/Transforms/MemCpyOpt/callslot_deref.ll
+++ b/test/Transforms/MemCpyOpt/callslot_deref.ll
@@ -10,19 +10,20 @@ define void @must_remove_memcpy(i8* noalias nocapture dereferenceable(4096) %dst
 ; CHECK: call void @llvm.memset.p0i8.i64
 ; CHECK-NOT: call void @llvm.memcpy.p0i8.p0i8.i64
   %src = alloca [4096 x i8], align 1
-  %p = getelementptr inbounds [4096 x i8]* %src, i64 0, i64 0
+  %p = getelementptr inbounds [4096 x i8], [4096 x i8]* %src, i64 0, i64 0
   call void @llvm.memset.p0i8.i64(i8* %p, i8 0, i64 4096, i32 1, i1 false)
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %p, i64 4096, i32 1, i1 false) #2
   ret void
 }
 
 ; memset touch more bytes than those guaranteed to be dereferenceable
+; We can't remove the memcpy, but we can turn it into an independent memset.
 define void @must_not_remove_memcpy(i8* noalias nocapture dereferenceable(1024) %dst) {
 ; CHECK-LABEL: @must_not_remove_memcpy(
 ; CHECK: call void @llvm.memset.p0i8.i64
-; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64
+; CHECK: call void @llvm.memset.p0i8.i64
   %src = alloca [4096 x i8], align 1
-  %p = getelementptr inbounds [4096 x i8]* %src, i64 0, i64 0
+  %p = getelementptr inbounds [4096 x i8], [4096 x i8]* %src, i64 0, i64 0
   call void @llvm.memset.p0i8.i64(i8* %p, i8 0, i64 4096, i32 1, i1 false)
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %p, i64 4096, i32 1, i1 false) #2
   ret void
diff --git a/test/Transforms/MemCpyOpt/crash.ll b/test/Transforms/MemCpyOpt/crash.ll
index cc3a6b05278a..56757a6d1f8b 100644
--- a/test/Transforms/MemCpyOpt/crash.ll
+++ b/test/Transforms/MemCpyOpt/crash.ll
@@ -9,37 +9,37 @@ target triple = "armv7-eabi"
 ; PR4882
 define void @test1(%struct.bar* %this) {
 entry:
-  %0 = getelementptr inbounds %struct.bar* %this, i32 0, i32 0, i32 0, i32 0
+  %0 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 0, i32 0, i32 0
   store float 0.000000e+00, float* %0, align 4
-  %1 = getelementptr inbounds %struct.bar* %this, i32 0, i32 0, i32 0, i32 1
+  %1 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 0, i32 0, i32 1
   store float 0.000000e+00, float* %1, align 4
-  %2 = getelementptr inbounds %struct.bar* %this, i32 0, i32 0, i32 0, i32 2
+  %2 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 0, i32 0, i32 2
   store float 0.000000e+00, float* %2, align 4
-  %3 = getelementptr inbounds %struct.bar* %this, i32 0, i32 0, i32 0, i32 3
+  %3 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 0, i32 0, i32 3
   store float 0.000000e+00, float* %3, align 4
-  %4 = getelementptr inbounds %struct.bar* %this, i32 0, i32 1, i32 0, i32 0
+  %4 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 1, i32 0, i32 0
   store float 0.000000e+00, float* %4, align 4
-  %5 = getelementptr inbounds %struct.bar* %this, i32 0, i32 1, i32 0, i32 1
+  %5 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 1, i32 0, i32 1
   store float 0.000000e+00, float* %5, align 4
-  %6 = getelementptr inbounds %struct.bar* %this, i32 0, i32 1, i32 0, i32 2
+  %6 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 1, i32 0, i32 2
   store float 0.000000e+00, float* %6, align 4
-  %7 = getelementptr inbounds %struct.bar* %this, i32 0, i32 1, i32 0, i32 3
+  %7 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 1, i32 0, i32 3
   store float 0.000000e+00, float* %7, align 4
-  %8 = getelementptr inbounds %struct.bar* %this, i32 0, i32 3, i32 0, i32 1
+  %8 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 3, i32 0, i32 1
   store float 0.000000e+00, float* %8, align 4
-  %9 = getelementptr inbounds %struct.bar* %this, i32 0, i32 3, i32 0, i32 2
+  %9 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 3, i32 0, i32 2
   store float 0.000000e+00, float* %9, align 4
-  %10 = getelementptr inbounds %struct.bar* %this, i32 0, i32 3, i32 0, i32 3
+  %10 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 3, i32 0, i32 3
   store float 0.000000e+00, float* %10, align 4
-  %11 = getelementptr inbounds %struct.bar* %this, i32 0, i32 4, i32 0, i32 0
+  %11 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 4, i32 0, i32 0
   store float 0.000000e+00, float* %11, align 4
-  %12 = getelementptr inbounds %struct.bar* %this, i32 0, i32 4, i32 0, i32 1
+  %12 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 4, i32 0, i32 1
   store float 0.000000e+00, float* %12, align 4
-  %13 = getelementptr inbounds %struct.bar* %this, i32 0, i32 4, i32 0, i32 2
+  %13 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 4, i32 0, i32 2
   store float 0.000000e+00, float* %13, align 4
-  %14 = getelementptr inbounds %struct.bar* %this, i32 0, i32 4, i32 0, i32 3
+  %14 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 4, i32 0, i32 3
   store float 0.000000e+00, float* %14, align 4
-  %15 = getelementptr inbounds %struct.bar* %this, i32 0, i32 5
+  %15 = getelementptr inbounds %struct.bar, %struct.bar* %this, i32 0, i32 5
   store float 0.000000e+00, float* %15, align 4
   unreachable
 }
diff --git a/test/Transforms/MemCpyOpt/form-memset.ll b/test/Transforms/MemCpyOpt/form-memset.ll
index d980b7fdbd69..7d7f3a6dac3c 100644
--- a/test/Transforms/MemCpyOpt/form-memset.ll
+++ b/test/Transforms/MemCpyOpt/form-memset.ll
@@ -8,45 +8,45 @@ target triple = "i386-apple-darwin8"
 define void @test1(i8 signext  %c) nounwind  {
 entry:
 	%x = alloca [19 x i8]		; <[19 x i8]*> [#uses=20]
-	%tmp = getelementptr [19 x i8]* %x, i32 0, i32 0		; <i8*> [#uses=1]
+	%tmp = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 0		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp, align 1
-	%tmp5 = getelementptr [19 x i8]* %x, i32 0, i32 1		; <i8*> [#uses=1]
+	%tmp5 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 1		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp5, align 1
-	%tmp9 = getelementptr [19 x i8]* %x, i32 0, i32 2		; <i8*> [#uses=1]
+	%tmp9 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 2		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp9, align 1
-	%tmp13 = getelementptr [19 x i8]* %x, i32 0, i32 3		; <i8*> [#uses=1]
+	%tmp13 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 3		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp13, align 1
-	%tmp17 = getelementptr [19 x i8]* %x, i32 0, i32 4		; <i8*> [#uses=1]
+	%tmp17 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 4		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp17, align 1
-	%tmp21 = getelementptr [19 x i8]* %x, i32 0, i32 5		; <i8*> [#uses=1]
+	%tmp21 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 5		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp21, align 1
-	%tmp25 = getelementptr [19 x i8]* %x, i32 0, i32 6		; <i8*> [#uses=1]
+	%tmp25 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 6		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp25, align 1
-	%tmp29 = getelementptr [19 x i8]* %x, i32 0, i32 7		; <i8*> [#uses=1]
+	%tmp29 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 7		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp29, align 1
-	%tmp33 = getelementptr [19 x i8]* %x, i32 0, i32 8		; <i8*> [#uses=1]
+	%tmp33 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 8		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp33, align 1
-	%tmp37 = getelementptr [19 x i8]* %x, i32 0, i32 9		; <i8*> [#uses=1]
+	%tmp37 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 9		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp37, align 1
-	%tmp41 = getelementptr [19 x i8]* %x, i32 0, i32 10		; <i8*> [#uses=1]
+	%tmp41 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 10		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp41, align 1
-	%tmp45 = getelementptr [19 x i8]* %x, i32 0, i32 11		; <i8*> [#uses=1]
+	%tmp45 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 11		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp45, align 1
-	%tmp49 = getelementptr [19 x i8]* %x, i32 0, i32 12		; <i8*> [#uses=1]
+	%tmp49 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 12		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp49, align 1
-	%tmp53 = getelementptr [19 x i8]* %x, i32 0, i32 13		; <i8*> [#uses=1]
+	%tmp53 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 13		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp53, align 1
-	%tmp57 = getelementptr [19 x i8]* %x, i32 0, i32 14		; <i8*> [#uses=1]
+	%tmp57 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 14		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp57, align 1
-	%tmp61 = getelementptr [19 x i8]* %x, i32 0, i32 15		; <i8*> [#uses=1]
+	%tmp61 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 15		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp61, align 1
-	%tmp65 = getelementptr [19 x i8]* %x, i32 0, i32 16		; <i8*> [#uses=1]
+	%tmp65 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 16		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp65, align 1
-	%tmp69 = getelementptr [19 x i8]* %x, i32 0, i32 17		; <i8*> [#uses=1]
+	%tmp69 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 17		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp69, align 1
-	%tmp73 = getelementptr [19 x i8]* %x, i32 0, i32 18		; <i8*> [#uses=1]
+	%tmp73 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 18		; <i8*> [#uses=1]
 	store i8 %c, i8* %tmp73, align 1
-	%tmp76 = call i32 (...)* @bar( [19 x i8]* %x ) nounwind
+	%tmp76 = call i32 (...) @bar( [19 x i8]* %x ) nounwind
 	ret void
 ; CHECK-LABEL: @test1(
 ; CHECK-NOT: store
@@ -65,88 +65,88 @@ entry:
 	%ref_idx = alloca [8 x i8]		; <[8 x i8]*> [#uses=8]
 	%left_mvd = alloca [8 x %struct.MV]		; <[8 x %struct.MV]*> [#uses=17]
 	%up_mvd = alloca [8 x %struct.MV]		; <[8 x %struct.MV]*> [#uses=17]
-	%tmp20 = getelementptr [8 x i8]* %ref_idx, i32 0, i32 7		; <i8*> [#uses=1]
+	%tmp20 = getelementptr [8 x i8], [8 x i8]* %ref_idx, i32 0, i32 7		; <i8*> [#uses=1]
 	store i8 -1, i8* %tmp20, align 1
-	%tmp23 = getelementptr [8 x i8]* %ref_idx, i32 0, i32 6		; <i8*> [#uses=1]
+	%tmp23 = getelementptr [8 x i8], [8 x i8]* %ref_idx, i32 0, i32 6		; <i8*> [#uses=1]
 	store i8 -1, i8* %tmp23, align 1
-	%tmp26 = getelementptr [8 x i8]* %ref_idx, i32 0, i32 5		; <i8*> [#uses=1]
+	%tmp26 = getelementptr [8 x i8], [8 x i8]* %ref_idx, i32 0, i32 5		; <i8*> [#uses=1]
 	store i8 -1, i8* %tmp26, align 1
-	%tmp29 = getelementptr [8 x i8]* %ref_idx, i32 0, i32 4		; <i8*> [#uses=1]
+	%tmp29 = getelementptr [8 x i8], [8 x i8]* %ref_idx, i32 0, i32 4		; <i8*> [#uses=1]
 	store i8 -1, i8* %tmp29, align 1
-	%tmp32 = getelementptr [8 x i8]* %ref_idx, i32 0, i32 3		; <i8*> [#uses=1]
+	%tmp32 = getelementptr [8 x i8], [8 x i8]* %ref_idx, i32 0, i32 3		; <i8*> [#uses=1]
 	store i8 -1, i8* %tmp32, align 1
-	%tmp35 = getelementptr [8 x i8]* %ref_idx, i32 0, i32 2		; <i8*> [#uses=1]
+	%tmp35 = getelementptr [8 x i8], [8 x i8]* %ref_idx, i32 0, i32 2		; <i8*> [#uses=1]
 	store i8 -1, i8* %tmp35, align 1
-	%tmp38 = getelementptr [8 x i8]* %ref_idx, i32 0, i32 1		; <i8*> [#uses=1]
+	%tmp38 = getelementptr [8 x i8], [8 x i8]* %ref_idx, i32 0, i32 1		; <i8*> [#uses=1]
 	store i8 -1, i8* %tmp38, align 1
-	%tmp41 = getelementptr [8 x i8]* %ref_idx, i32 0, i32 0		; <i8*> [#uses=2]
+	%tmp41 = getelementptr [8 x i8], [8 x i8]* %ref_idx, i32 0, i32 0		; <i8*> [#uses=2]
 	store i8 -1, i8* %tmp41, align 1
-	%tmp43 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 7, i32 0		; <i16*> [#uses=1]
+	%tmp43 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 7, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp43, align 2
-	%tmp46 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 7, i32 1		; <i16*> [#uses=1]
+	%tmp46 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 7, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp46, align 2
-	%tmp57 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 6, i32 0		; <i16*> [#uses=1]
+	%tmp57 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 6, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp57, align 2
-	%tmp60 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 6, i32 1		; <i16*> [#uses=1]
+	%tmp60 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 6, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp60, align 2
-	%tmp71 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 5, i32 0		; <i16*> [#uses=1]
+	%tmp71 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 5, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp71, align 2
-	%tmp74 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 5, i32 1		; <i16*> [#uses=1]
+	%tmp74 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 5, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp74, align 2
-	%tmp85 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 4, i32 0		; <i16*> [#uses=1]
+	%tmp85 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 4, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp85, align 2
-	%tmp88 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 4, i32 1		; <i16*> [#uses=1]
+	%tmp88 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 4, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp88, align 2
-	%tmp99 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 3, i32 0		; <i16*> [#uses=1]
+	%tmp99 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 3, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp99, align 2
-	%tmp102 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 3, i32 1		; <i16*> [#uses=1]
+	%tmp102 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 3, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp102, align 2
-	%tmp113 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 2, i32 0		; <i16*> [#uses=1]
+	%tmp113 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 2, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp113, align 2
-	%tmp116 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 2, i32 1		; <i16*> [#uses=1]
+	%tmp116 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 2, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp116, align 2
-	%tmp127 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 1, i32 0		; <i16*> [#uses=1]
+	%tmp127 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 1, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp127, align 2
-	%tmp130 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 1, i32 1		; <i16*> [#uses=1]
+	%tmp130 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 1, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp130, align 2
-	%tmp141 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 0, i32 0		; <i16*> [#uses=1]
+	%tmp141 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 0, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp141, align 8
-	%tmp144 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 0, i32 1		; <i16*> [#uses=1]
+	%tmp144 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 0, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp144, align 2
-	%tmp148 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 7, i32 0		; <i16*> [#uses=1]
+	%tmp148 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 7, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp148, align 2
-	%tmp151 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 7, i32 1		; <i16*> [#uses=1]
+	%tmp151 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 7, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp151, align 2
-	%tmp162 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 6, i32 0		; <i16*> [#uses=1]
+	%tmp162 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 6, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp162, align 2
-	%tmp165 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 6, i32 1		; <i16*> [#uses=1]
+	%tmp165 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 6, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp165, align 2
-	%tmp176 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 5, i32 0		; <i16*> [#uses=1]
+	%tmp176 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 5, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp176, align 2
-	%tmp179 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 5, i32 1		; <i16*> [#uses=1]
+	%tmp179 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 5, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp179, align 2
-	%tmp190 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 4, i32 0		; <i16*> [#uses=1]
+	%tmp190 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 4, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp190, align 2
-	%tmp193 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 4, i32 1		; <i16*> [#uses=1]
+	%tmp193 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 4, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp193, align 2
-	%tmp204 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 3, i32 0		; <i16*> [#uses=1]
+	%tmp204 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 3, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp204, align 2
-	%tmp207 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 3, i32 1		; <i16*> [#uses=1]
+	%tmp207 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 3, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp207, align 2
-	%tmp218 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 2, i32 0		; <i16*> [#uses=1]
+	%tmp218 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 2, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp218, align 2
-	%tmp221 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 2, i32 1		; <i16*> [#uses=1]
+	%tmp221 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 2, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp221, align 2
-	%tmp232 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 1, i32 0		; <i16*> [#uses=1]
+	%tmp232 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 1, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp232, align 2
-	%tmp235 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 1, i32 1		; <i16*> [#uses=1]
+	%tmp235 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 1, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp235, align 2
-	%tmp246 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 0, i32 0		; <i16*> [#uses=1]
+	%tmp246 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 0, i32 0		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp246, align 8
-	%tmp249 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 0, i32 1		; <i16*> [#uses=1]
+	%tmp249 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 0, i32 1		; <i16*> [#uses=1]
 	store i16 0, i16* %tmp249, align 2
-	%up_mvd252 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 0		; <%struct.MV*> [#uses=1]
-	%left_mvd253 = getelementptr [8 x %struct.MV]* %left_mvd, i32 0, i32 0		; <%struct.MV*> [#uses=1]
+	%up_mvd252 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 0		; <%struct.MV*> [#uses=1]
+	%left_mvd253 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 0		; <%struct.MV*> [#uses=1]
 	call void @foo( %struct.MV* %up_mvd252, %struct.MV* %left_mvd253, i8* %tmp41 ) nounwind 
 	ret void
         
@@ -167,9 +167,9 @@ declare void @foo(%struct.MV*, %struct.MV*, i8*)
 ; Store followed by memset.
 define void @test3(i32* nocapture %P) nounwind ssp {
 entry:
-  %arrayidx = getelementptr inbounds i32* %P, i64 1
+  %arrayidx = getelementptr inbounds i32, i32* %P, i64 1
   store i32 0, i32* %arrayidx, align 4
-  %add.ptr = getelementptr inbounds i32* %P, i64 2
+  %add.ptr = getelementptr inbounds i32, i32* %P, i64 2
   %0 = bitcast i32* %add.ptr to i8*
   tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 11, i32 1, i1 false)
   ret void
@@ -182,7 +182,7 @@ entry:
 define void @test4(i32* nocapture %P) nounwind ssp {
 entry:
   store i32 0, i32* %P, align 4
-  %add.ptr = getelementptr inbounds i32* %P, i64 1
+  %add.ptr = getelementptr inbounds i32, i32* %P, i64 1
   %0 = bitcast i32* %add.ptr to i8*
   tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 11, i32 1, i1 false)
   ret void
@@ -196,10 +196,10 @@ declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
 ; Memset followed by store.
 define void @test5(i32* nocapture %P) nounwind ssp {
 entry:
-  %add.ptr = getelementptr inbounds i32* %P, i64 2
+  %add.ptr = getelementptr inbounds i32, i32* %P, i64 2
   %0 = bitcast i32* %add.ptr to i8*
   tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 11, i32 1, i1 false)
-  %arrayidx = getelementptr inbounds i32* %P, i64 1
+  %arrayidx = getelementptr inbounds i32, i32* %P, i64 1
   store i32 0, i32* %arrayidx, align 4
   ret void
 ; CHECK-LABEL: @test5(
@@ -212,7 +212,7 @@ define void @test6(i32* nocapture %P) nounwind ssp {
 entry:
   %0 = bitcast i32* %P to i8*
   tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 12, i32 1, i1 false)
-  %add.ptr = getelementptr inbounds i32* %P, i64 3
+  %add.ptr = getelementptr inbounds i32, i32* %P, i64 3
   %1 = bitcast i32* %add.ptr to i8*
   tail call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 12, i32 1, i1 false)
   ret void
@@ -224,13 +224,13 @@ entry:
 ; rdar://9892684
 define void @test7(i32* nocapture %c) nounwind optsize {
   store i32 -1, i32* %c, align 4
-  %1 = getelementptr inbounds i32* %c, i32 1
+  %1 = getelementptr inbounds i32, i32* %c, i32 1
   store i32 -1, i32* %1, align 4
-  %2 = getelementptr inbounds i32* %c, i32 2
+  %2 = getelementptr inbounds i32, i32* %c, i32 2
   store i32 -1, i32* %2, align 4
-  %3 = getelementptr inbounds i32* %c, i32 3
+  %3 = getelementptr inbounds i32, i32* %c, i32 3
   store i32 -1, i32* %3, align 4
-  %4 = getelementptr inbounds i32* %c, i32 4
+  %4 = getelementptr inbounds i32, i32* %c, i32 4
   store i32 -1, i32* %4, align 4
 ; CHECK-LABEL: @test7(
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %5, i8 -1, i64 20, i32 4, i1 false)
@@ -253,21 +253,21 @@ entry:
 
 define void @test9() nounwind {
   store i8 -1, i8* bitcast ([16 x i64]* @test9buf to i8*), align 16
-  store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 1), align 1
-  store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 2), align 2
-  store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 3), align 1
-  store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 4), align 4
-  store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 5), align 1
-  store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 6), align 2
-  store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 7), align 1
-  store i8 -1, i8* bitcast (i64* getelementptr inbounds ([16 x i64]* @test9buf, i64 0, i64 1) to i8*), align 8
-  store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 9), align 1
-  store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 10), align 2
-  store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 11), align 1
-  store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 12), align 4
-  store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 13), align 1
-  store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 14), align 2
-  store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 15), align 1
+  store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 1), align 1
+  store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 2), align 2
+  store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 3), align 1
+  store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 4), align 4
+  store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 5), align 1
+  store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 6), align 2
+  store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 7), align 1
+  store i8 -1, i8* bitcast (i64* getelementptr inbounds ([16 x i64], [16 x i64]* @test9buf, i64 0, i64 1) to i8*), align 8
+  store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 9), align 1
+  store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 10), align 2
+  store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 11), align 1
+  store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 12), align 4
+  store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 13), align 1
+  store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 14), align 2
+  store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 15), align 1
   ret void
 ; CHECK-LABEL: @test9(
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* bitcast ([16 x i64]* @test9buf to i8*), i8 -1, i64 16, i32 16, i1 false)
@@ -284,3 +284,18 @@ define void @test10(i8* nocapture %P) nounwind {
 ; CHECK-NOT: memset
 ; CHECK: ret void
 }
+
+; Memset followed by odd store.
+define void @test11(i32* nocapture %P) nounwind ssp {
+entry:
+  %add.ptr = getelementptr inbounds i32, i32* %P, i64 3
+  %0 = bitcast i32* %add.ptr to i8*
+  tail call void @llvm.memset.p0i8.i64(i8* %0, i8 1, i64 11, i32 1, i1 false)
+  %arrayidx = getelementptr inbounds i32, i32* %P, i64 0
+  %arrayidx.cast = bitcast i32* %arrayidx to i96*
+  store i96 310698676526526814092329217, i96* %arrayidx.cast, align 4
+  ret void
+; CHECK-LABEL: @test11(
+; CHECK-NOT: store
+; CHECK: call void @llvm.memset.p0i8.i64(i8* %1, i8 1, i64 23, i32 4, i1 false)
+}
diff --git a/test/Transforms/MemCpyOpt/loadstore-sret.ll b/test/Transforms/MemCpyOpt/loadstore-sret.ll
index d4a700d03115..55cbe59651f4 100644
--- a/test/Transforms/MemCpyOpt/loadstore-sret.ll
+++ b/test/Transforms/MemCpyOpt/loadstore-sret.ll
@@ -12,10 +12,10 @@ _ZNSt8auto_ptrIiED1Ev.exit:
   %temp.lvalue = alloca %"class.std::auto_ptr", align 8
 ; CHECK: call void @_Z3barv(%"class.std::auto_ptr"* sret %agg.result)
   call void @_Z3barv(%"class.std::auto_ptr"* sret %temp.lvalue)
-  %tmp.i.i = getelementptr inbounds %"class.std::auto_ptr"* %temp.lvalue, i64 0, i32 0
+  %tmp.i.i = getelementptr inbounds %"class.std::auto_ptr", %"class.std::auto_ptr"* %temp.lvalue, i64 0, i32 0
 ; CHECK-NOT: load
-  %tmp2.i.i = load i32** %tmp.i.i, align 8
-  %tmp.i.i4 = getelementptr inbounds %"class.std::auto_ptr"* %agg.result, i64 0, i32 0
+  %tmp2.i.i = load i32*, i32** %tmp.i.i, align 8
+  %tmp.i.i4 = getelementptr inbounds %"class.std::auto_ptr", %"class.std::auto_ptr"* %agg.result, i64 0, i32 0
 ; CHECK-NOT: store
   store i32* %tmp2.i.i, i32** %tmp.i.i4, align 8
 ; CHECK: ret void
diff --git a/test/Transforms/MemCpyOpt/memcpy-to-memset-with-lifetimes.ll b/test/Transforms/MemCpyOpt/memcpy-to-memset-with-lifetimes.ll
index 626317614c94..e3e57f09d88f 100644
--- a/test/Transforms/MemCpyOpt/memcpy-to-memset-with-lifetimes.ll
+++ b/test/Transforms/MemCpyOpt/memcpy-to-memset-with-lifetimes.ll
@@ -40,7 +40,7 @@ entry-block:
 ; CHECK:         %[[a_cast:[^=]+]] = bitcast [8 x i64]* %[[a]] to i8*
 ; CHECK:         call void @llvm.memset.p0i8.i64(i8* %[[a_cast]], i8 0, i64 64
 ; CHECK:         %[[sret_cast:[^=]+]] = bitcast [8 x i64]* %sret to i8*
-; CHECK:         call void @llvm.memcpy.p0i8.p0i8.i64(i8* %[[sret_cast]], i8* %[[a_cast]], i64 64
+; CHECK:         call void @llvm.memset.p0i8.i64(i8* %[[sret_cast]], i8 0, i64 64
 ; CHECK:         call void @llvm.memset.p0i8.i64(i8* %[[a_cast]], i8 42, i64 32
 ; CHECK:         %[[out_cast:[^=]+]] = bitcast [8 x i64]* %out to i8*
 ; CHECK:         call void @llvm.memcpy.p0i8.p0i8.i64(i8* %[[out_cast]], i8* %[[a_cast]], i64 64
diff --git a/test/Transforms/MemCpyOpt/memcpy-to-memset.ll b/test/Transforms/MemCpyOpt/memcpy-to-memset.ll
index 8409de7ad206..fd8b93c19b1d 100644
--- a/test/Transforms/MemCpyOpt/memcpy-to-memset.ll
+++ b/test/Transforms/MemCpyOpt/memcpy-to-memset.ll
@@ -9,7 +9,7 @@ define void @test1() nounwind {
   %arr = alloca [3 x i32], align 4
   %arr_i8 = bitcast [3 x i32]* %arr to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %arr_i8, i8* bitcast ([3 x i32]* @cst to i8*), i64 12, i32 4, i1 false)
-  %arraydecay = getelementptr inbounds [3 x i32]* %arr, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [3 x i32], [3 x i32]* %arr, i64 0, i64 0
   call void @foo(i32* %arraydecay) nounwind
   ret void
 ; CHECK-LABEL: @test1(
diff --git a/test/Transforms/MemCpyOpt/memcpy-undef.ll b/test/Transforms/MemCpyOpt/memcpy-undef.ll
index 663b8dcfd3df..c75d020c0786 100644
--- a/test/Transforms/MemCpyOpt/memcpy-undef.ll
+++ b/test/Transforms/MemCpyOpt/memcpy-undef.ll
@@ -7,12 +7,12 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 define i32 @test1(%struct.foo* nocapture %foobie) nounwind noinline ssp uwtable {
   %bletch.sroa.1 = alloca [7 x i8], align 1
-  %1 = getelementptr inbounds %struct.foo* %foobie, i64 0, i32 0
+  %1 = getelementptr inbounds %struct.foo, %struct.foo* %foobie, i64 0, i32 0
   store i8 98, i8* %1, align 4
-  %2 = getelementptr inbounds %struct.foo* %foobie, i64 0, i32 1, i64 0
-  %3 = getelementptr inbounds [7 x i8]* %bletch.sroa.1, i64 0, i64 0
+  %2 = getelementptr inbounds %struct.foo, %struct.foo* %foobie, i64 0, i32 1, i64 0
+  %3 = getelementptr inbounds [7 x i8], [7 x i8]* %bletch.sroa.1, i64 0, i64 0
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 7, i32 1, i1 false)
-  %4 = getelementptr inbounds %struct.foo* %foobie, i64 0, i32 2
+  %4 = getelementptr inbounds %struct.foo, %struct.foo* %foobie, i64 0, i32 2
   store i32 20, i32* %4, align 4
   ret i32 undef
 
diff --git a/test/Transforms/MemCpyOpt/memcpy.ll b/test/Transforms/MemCpyOpt/memcpy.ll
index ee04f1951164..731847440d76 100644
--- a/test/Transforms/MemCpyOpt/memcpy.ll
+++ b/test/Transforms/MemCpyOpt/memcpy.ll
@@ -93,7 +93,7 @@ entry:
   %y = alloca %struct.S, align 16
   %tmp = bitcast %struct.S* %y to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp, i8* bitcast (%struct.S* @sS to i8*), i64 32, i32 16, i1 false)
-  %a = getelementptr %struct.S* %y, i64 0, i32 1, i64 0
+  %a = getelementptr %struct.S, %struct.S* %y, i64 0, i32 1, i64 0
   store i8 4, i8* %a
   call void @test5a(%struct.S* align 16 byval %y)
   ret i32 0
@@ -139,10 +139,10 @@ define void @test8() {
 ; CHECK: test8
 ; CHECK-NOT: memcpy
   %A = tail call i8* @malloc(i32 10)
-  %B = getelementptr inbounds i8* %A, i64 2
-  tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %B, i8* getelementptr inbounds ([7 x i8]* @test8.str, i64 0, i64 0), i32 7, i32 1, i1 false)
+  %B = getelementptr inbounds i8, i8* %A, i64 2
+  tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %B, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @test8.str, i64 0, i64 0), i32 7, i32 1, i1 false)
   %C = tail call i8* @malloc(i32 10)
-  %D = getelementptr inbounds i8* %C, i64 2
+  %D = getelementptr inbounds i8, i8* %C, i64 2
   tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %D, i8* %B, i32 7, i32 1, i1 false)
   ret void
 ; CHECK: ret void
@@ -196,7 +196,7 @@ define void @test10(%opaque* noalias nocapture sret %x, i32 %y) {
   %a = alloca i32, align 4
   store i32 %y, i32* %a
   call void @foo(i32* noalias nocapture %a)
-  %c = load i32* %a
+  %c = load i32, i32* %a
   %d = bitcast %opaque* %x to i32*
   store i32 %c, i32* %d
   ret void
diff --git a/test/Transforms/MemCpyOpt/memmove.ll b/test/Transforms/MemCpyOpt/memmove.ll
index 2057760efa01..1af85a1edc56 100644
--- a/test/Transforms/MemCpyOpt/memmove.ll
+++ b/test/Transforms/MemCpyOpt/memmove.ll
@@ -11,9 +11,9 @@ entry:
 ; CHECK-LABEL: @test1(
 ; CHECK: call void @llvm.memcpy
 
-  %malloccall = tail call i8* @malloc(i32 trunc (i64 mul nuw (i64 ptrtoint (i8* getelementptr (i8* null, i32 1) to i64), i64 13) to i32))
+  %malloccall = tail call i8* @malloc(i32 trunc (i64 mul nuw (i64 ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64), i64 13) to i32))
   %call3 = bitcast i8* %malloccall to [13 x i8]*
-  %call3.sub = getelementptr inbounds [13 x i8]* %call3, i64 0, i64 0
+  %call3.sub = getelementptr inbounds [13 x i8], [13 x i8]* %call3, i64 0, i64 0
   tail call void @llvm.memmove.p0i8.p0i8.i64(i8* %call3.sub, i8* %src, i64 13, i32 1, i1 false)
   ret i8* %call3.sub
 }
@@ -24,7 +24,7 @@ define void @test2(i8* %P) nounwind {
 entry:
 ; CHECK-LABEL: @test2(
 ; CHECK: call void @llvm.memcpy
-  %add.ptr = getelementptr i8* %P, i64 16
+  %add.ptr = getelementptr i8, i8* %P, i64 16
   tail call void @llvm.memmove.p0i8.p0i8.i64(i8* %P, i8* %add.ptr, i64 16, i32 1, i1 false)
   ret void
 }
@@ -34,7 +34,7 @@ define void @test3(i8* %P) nounwind {
 entry:
 ; CHECK-LABEL: @test3(
 ; CHECK: call void @llvm.memmove
-  %add.ptr = getelementptr i8* %P, i64 16
+  %add.ptr = getelementptr i8, i8* %P, i64 16
   tail call void @llvm.memmove.p0i8.p0i8.i64(i8* %P, i8* %add.ptr, i64 17, i32 1, i1 false)
   ret void
 }
diff --git a/test/Transforms/MemCpyOpt/memset-memcpy-redundant-memset.ll b/test/Transforms/MemCpyOpt/memset-memcpy-redundant-memset.ll
new file mode 100644
index 000000000000..993c8a1bb2d0
--- /dev/null
+++ b/test/Transforms/MemCpyOpt/memset-memcpy-redundant-memset.ll
@@ -0,0 +1,168 @@
+; RUN: opt -basicaa -memcpyopt -S %s | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+
+; CHECK-LABEL: define void @test
+; CHECK-DAG: [[DST:%[0-9]+]] = getelementptr i8, i8* %dst, i64 %src_size
+; CHECK-DAG: [[ULE:%[0-9]+]] = icmp ule i64 %dst_size, %src_size
+; CHECK-DAG: [[SIZEDIFF:%[0-9]+]] = sub i64 %dst_size, %src_size
+; CHECK-DAG: [[SIZE:%[0-9]+]] = select i1 [[ULE]], i64 0, i64 [[SIZEDIFF]]
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* [[DST]], i8 %c, i64 [[SIZE]], i32 1, i1 false)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %src_size, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test(i8* %src, i64 %src_size, i8* %dst, i64 %dst_size, i8 %c) {
+  call void @llvm.memset.p0i8.i64(i8* %dst, i8 %c, i64 %dst_size, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %src_size, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_different_types_i32_i64
+; CHECK-DAG: [[DSTSIZE:%[0-9]+]] = zext i32 %dst_size to i64
+; CHECK-DAG: [[DST:%[0-9]+]] = getelementptr i8, i8* %dst, i64 %src_size
+; CHECK-DAG: [[ULE:%[0-9]+]] = icmp ule i64 [[DSTSIZE]], %src_size
+; CHECK-DAG: [[SIZEDIFF:%[0-9]+]] = sub i64 [[DSTSIZE]], %src_size
+; CHECK-DAG: [[SIZE:%[0-9]+]] = select i1 [[ULE]], i64 0, i64 [[SIZEDIFF]]
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* [[DST]], i8 %c, i64 [[SIZE]], i32 1, i1 false)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %src_size, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test_different_types_i32_i64(i8* %dst, i8* %src, i32 %dst_size, i64 %src_size, i8 %c) {
+  call void @llvm.memset.p0i8.i32(i8* %dst, i8 %c, i32 %dst_size, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %src_size, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_different_types_i128_i32
+; CHECK-DAG: [[SRCSIZE:%[0-9]+]] = zext i32 %src_size to i128
+; CHECK-DAG: [[DST:%[0-9]+]] = getelementptr i8, i8* %dst, i128 [[SRCSIZE]]
+; CHECK-DAG: [[ULE:%[0-9]+]] = icmp ule i128 %dst_size, [[SRCSIZE]]
+; CHECK-DAG: [[SIZEDIFF:%[0-9]+]] = sub i128 %dst_size, [[SRCSIZE]]
+; CHECK-DAG: [[SIZE:%[0-9]+]] = select i1 [[ULE]], i128 0, i128 [[SIZEDIFF]]
+; CHECK-NEXT: call void @llvm.memset.p0i8.i128(i8* [[DST]], i8 %c, i128 [[SIZE]], i32 1, i1 false)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src, i32 %src_size, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test_different_types_i128_i32(i8* %dst, i8* %src, i128 %dst_size, i32 %src_size, i8 %c) {
+  call void @llvm.memset.p0i8.i128(i8* %dst, i8 %c, i128 %dst_size, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src, i32 %src_size, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_different_types_i32_i128
+; CHECK-DAG: [[DSTSIZE:%[0-9]+]] = zext i32 %dst_size to i128
+; CHECK-DAG: [[DST:%[0-9]+]] = getelementptr i8, i8* %dst, i128 %src_size
+; CHECK-DAG: [[ULE:%[0-9]+]] = icmp ule i128 [[DSTSIZE]], %src_size
+; CHECK-DAG: [[SIZEDIFF:%[0-9]+]] = sub i128 [[DSTSIZE]], %src_size
+; CHECK-DAG: [[SIZE:%[0-9]+]] = select i1 [[ULE]], i128 0, i128 [[SIZEDIFF]]
+; CHECK-NEXT: call void @llvm.memset.p0i8.i128(i8* [[DST]], i8 %c, i128 [[SIZE]], i32 1, i1 false)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i128(i8* %dst, i8* %src, i128 %src_size, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test_different_types_i32_i128(i8* %dst, i8* %src, i32 %dst_size, i128 %src_size, i8 %c) {
+  call void @llvm.memset.p0i8.i32(i8* %dst, i8 %c, i32 %dst_size, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i128(i8* %dst, i8* %src, i128 %src_size, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_different_types_i64_i32
+; CHECK-DAG: [[SRCSIZE:%[0-9]+]] = zext i32 %src_size to i64
+; CHECK-DAG: [[DST:%[0-9]+]] = getelementptr i8, i8* %dst, i64 [[SRCSIZE]]
+; CHECK-DAG: [[ULE:%[0-9]+]] = icmp ule i64 %dst_size, [[SRCSIZE]]
+; CHECK-DAG: [[SIZEDIFF:%[0-9]+]] = sub i64 %dst_size, [[SRCSIZE]]
+; CHECK-DAG: [[SIZE:%[0-9]+]] = select i1 [[ULE]], i64 0, i64 [[SIZEDIFF]]
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* [[DST]], i8 %c, i64 [[SIZE]], i32 1, i1 false)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src, i32 %src_size, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test_different_types_i64_i32(i8* %dst, i8* %src, i64 %dst_size, i32 %src_size, i8 %c) {
+  call void @llvm.memset.p0i8.i64(i8* %dst, i8 %c, i64 %dst_size, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src, i32 %src_size, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_align_same
+; CHECK: call void @llvm.memset.p0i8.i64(i8* {{.*}}, i8 0, i64 {{.*}}, i32 8, i1 false)
+define void @test_align_same(i8* %src, i8* %dst, i64 %dst_size) {
+  call void @llvm.memset.p0i8.i64(i8* %dst, i8 0, i64 %dst_size, i32 8, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 80, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_align_min
+; CHECK: call void @llvm.memset.p0i8.i64(i8* {{.*}}, i8 0, i64 {{.*}}, i32 4, i1 false)
+define void @test_align_min(i8* %src, i8* %dst, i64 %dst_size) {
+  call void @llvm.memset.p0i8.i64(i8* %dst, i8 0, i64 %dst_size, i32 8, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 36, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_align_memcpy
+; CHECK: call void @llvm.memset.p0i8.i64(i8* {{.*}}, i8 0, i64 {{.*}}, i32 8, i1 false)
+define void @test_align_memcpy(i8* %src, i8* %dst, i64 %dst_size) {
+  call void @llvm.memset.p0i8.i64(i8* %dst, i8 0, i64 %dst_size, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 80, i32 8, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_non_i8_dst_type
+; CHECK-NEXT: %dst = bitcast i64* %dst_pi64 to i8*
+; CHECK-DAG: [[DST:%[0-9]+]] = getelementptr i8, i8* %dst, i64 %src_size
+; CHECK-DAG: [[ULE:%[0-9]+]] = icmp ule i64 %dst_size, %src_size
+; CHECK-DAG: [[SIZEDIFF:%[0-9]+]] = sub i64 %dst_size, %src_size
+; CHECK-DAG: [[SIZE:%[0-9]+]] = select i1 [[ULE]], i64 0, i64 [[SIZEDIFF]]
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* [[DST]], i8 %c, i64 [[SIZE]], i32 1, i1 false)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %src_size, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test_non_i8_dst_type(i8* %src, i64 %src_size, i64* %dst_pi64, i64 %dst_size, i8 %c) {
+  %dst = bitcast i64* %dst_pi64 to i8*
+  call void @llvm.memset.p0i8.i64(i8* %dst, i8 %c, i64 %dst_size, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %src_size, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_different_dst
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %dst, i8 0, i64 %dst_size, i32 1, i1 false)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %src, i64 %src_size, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test_different_dst(i8* %dst2, i8* %src, i64 %src_size, i8* %dst, i64 %dst_size) {
+  call void @llvm.memset.p0i8.i64(i8* %dst, i8 0, i64 %dst_size, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %src, i64 %src_size, i32 1, i1 false)
+  ret void
+}
+
+; Make sure we also take into account dependencies on the destination.
+
+; CHECK-LABEL: define i8 @test_intermediate_read
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %a, i8 0, i64 64, i32 1, i1 false)
+; CHECK-NEXT: %r = load i8, i8* %a
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 24, i32 1, i1 false)
+; CHECK-NEXT: ret i8 %r
+define i8 @test_intermediate_read(i8* %a, i8* %b) #0 {
+  call void @llvm.memset.p0i8.i64(i8* %a, i8 0, i64 64, i32 1, i1 false)
+  %r = load i8, i8* %a
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 24, i32 1, i1 false)
+  ret i8 %r
+}
+
+%struct = type { [8 x i8], [8 x i8] }
+
+; CHECK-LABEL: define void @test_intermediate_write
+; CHECK-NEXT: %a = alloca %struct
+; CHECK-NEXT: %a0 = getelementptr %struct, %struct* %a, i32 0, i32 0, i32 0
+; CHECK-NEXT: %a1 = getelementptr %struct, %struct* %a, i32 0, i32 1, i32 0
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %a0, i8 0, i64 16, i32 1, i1 false)
+; CHECK-NEXT: store i8 1, i8* %a1
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a0, i8* %b, i64 8, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test_intermediate_write(i8* %b) #0 {
+  %a = alloca %struct
+  %a0 = getelementptr %struct, %struct* %a, i32 0, i32 0, i32 0
+  %a1 = getelementptr %struct, %struct* %a, i32 0, i32 1, i32 0
+  call void @llvm.memset.p0i8.i64(i8* %a0, i8 0, i64 16, i32 1, i1 false)
+  store i8 1, i8* %a1
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a0, i8* %b, i64 8, i32 1, i1 false)
+  ret void
+}
+
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1)
+declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1)
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1)
+declare void @llvm.memset.p0i8.i128(i8* nocapture, i8, i128, i32, i1)
+declare void @llvm.memcpy.p0i8.p0i8.i128(i8* nocapture, i8* nocapture readonly, i128, i32, i1)
diff --git a/test/Transforms/MemCpyOpt/memset-memcpy-to-2x-memset.ll b/test/Transforms/MemCpyOpt/memset-memcpy-to-2x-memset.ll
new file mode 100644
index 000000000000..1c567042ce79
--- /dev/null
+++ b/test/Transforms/MemCpyOpt/memset-memcpy-to-2x-memset.ll
@@ -0,0 +1,101 @@
+; RUN: opt -memcpyopt -S %s | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+
+; CHECK-LABEL: define void @test(
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 128, i32 1, i1 false)
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %dst2, i8 %c, i64 128, i32 8, i1 false)
+; CHECK-NEXT: ret void
+define void @test(i8* %dst1, i8* %dst2, i8 %c) {
+  call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 128, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %dst1, i64 128, i32 8, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_smaller_memcpy(
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 128, i32 1, i1 false)
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %dst2, i8 %c, i64 100, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test_smaller_memcpy(i8* %dst1, i8* %dst2, i8 %c) {
+  call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 128, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %dst1, i64 100, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_smaller_memset(
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 100, i32 1, i1 false)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %dst1, i64 128, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test_smaller_memset(i8* %dst1, i8* %dst2, i8 %c) {
+  call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 100, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %dst1, i64 128, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_align_memset(
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 128, i32 8, i1 false)
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %dst2, i8 %c, i64 128, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test_align_memset(i8* %dst1, i8* %dst2, i8 %c) {
+  call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 128, i32 8, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %dst1, i64 128, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_different_types(
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 128, i32 8, i1 false)
+; CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* %dst2, i8 %c, i32 100, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test_different_types(i8* %dst1, i8* %dst2, i8 %c) {
+  call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 128, i32 8, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst2, i8* %dst1, i32 100, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_different_types_2(
+; CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* %dst1, i8 %c, i32 128, i32 8, i1 false)
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %dst2, i8 %c, i64 100, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test_different_types_2(i8* %dst1, i8* %dst2, i8 %c) {
+  call void @llvm.memset.p0i8.i32(i8* %dst1, i8 %c, i32 128, i32 8, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %dst1, i64 100, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_different_source_gep(
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 128, i32 1, i1 false)
+; CHECK-NEXT: %p = getelementptr i8, i8* %dst1, i64 64
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %p, i64 64, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test_different_source_gep(i8* %dst1, i8* %dst2, i8 %c) {
+  call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 128, i32 1, i1 false)
+  ; FIXME: We could optimize this as well.
+  %p = getelementptr i8, i8* %dst1, i64 64
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %p, i64 64, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_variable_size_1(
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 %dst1_size, i32 1, i1 false)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %dst1, i64 128, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test_variable_size_1(i8* %dst1, i64 %dst1_size, i8* %dst2, i8 %c) {
+  call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 %dst1_size, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %dst1, i64 128, i32 1, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: define void @test_variable_size_2(
+; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 128, i32 1, i1 false)
+; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %dst1, i64 %dst2_size, i32 1, i1 false)
+; CHECK-NEXT: ret void
+define void @test_variable_size_2(i8* %dst1, i8* %dst2, i64 %dst2_size, i8 %c) {
+  call void @llvm.memset.p0i8.i64(i8* %dst1, i8 %c, i64 128, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %dst1, i64 %dst2_size, i32 1, i1 false)
+  ret void
+}
+
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1)
+declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1)
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1)
diff --git a/test/Transforms/MemCpyOpt/smaller.ll b/test/Transforms/MemCpyOpt/smaller.ll
index 1d35582d993e..8f6cafa6c012 100644
--- a/test/Transforms/MemCpyOpt/smaller.ll
+++ b/test/Transforms/MemCpyOpt/smaller.ll
@@ -4,7 +4,7 @@
 ; Memcpyopt shouldn't optimize the second memcpy using the first
 ; because the first has a smaller size.
 
-; CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp, i8* getelementptr inbounds (%struct.s* @cell, i32 0, i32 0, i32 0), i32 16, i32 4, i1 false)
+; CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp, i8* getelementptr inbounds (%struct.s, %struct.s* @cell, i32 0, i32 0, i32 0), i32 16, i32 4, i1 false)
 
 target datalayout = "e-p:32:32:32"
 
@@ -19,10 +19,10 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32,
 define void @foo() nounwind {
 entry:
   %agg.tmp = alloca %struct.s, align 4
-  store i32 99, i32* getelementptr inbounds (%struct.s* @cell, i32 0, i32 1), align 4
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.s* @cell, i32 0, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i32 11, i32 1, i1 false)
-  %tmp = getelementptr inbounds %struct.s* %agg.tmp, i32 0, i32 0, i32 0
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp, i8* getelementptr inbounds (%struct.s* @cell, i32 0, i32 0, i32 0), i32 16, i32 4, i1 false)
+  store i32 99, i32* getelementptr inbounds (%struct.s, %struct.s* @cell, i32 0, i32 1), align 4
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.s, %struct.s* @cell, i32 0, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i32 11, i32 1, i1 false)
+  %tmp = getelementptr inbounds %struct.s, %struct.s* %agg.tmp, i32 0, i32 0, i32 0
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp, i8* getelementptr inbounds (%struct.s, %struct.s* @cell, i32 0, i32 0, i32 0), i32 16, i32 4, i1 false)
   call void @check(%struct.s* byval %agg.tmp)
   ret void
 }
diff --git a/test/Transforms/MemCpyOpt/sret.ll b/test/Transforms/MemCpyOpt/sret.ll
index bfe5e0fbb993..34ba4c4d8bb7 100644
--- a/test/Transforms/MemCpyOpt/sret.ll
+++ b/test/Transforms/MemCpyOpt/sret.ll
@@ -9,13 +9,13 @@ define void @ccosl(%0* noalias sret %agg.result, %0* byval align 8 %z) nounwind
 entry:
   %iz = alloca %0
   %memtmp = alloca %0, align 16
-  %tmp1 = getelementptr %0* %z, i32 0, i32 1
-  %tmp2 = load x86_fp80* %tmp1, align 16
+  %tmp1 = getelementptr %0, %0* %z, i32 0, i32 1
+  %tmp2 = load x86_fp80, x86_fp80* %tmp1, align 16
   %tmp3 = fsub x86_fp80 0xK80000000000000000000, %tmp2
-  %tmp4 = getelementptr %0* %iz, i32 0, i32 1
-  %real = getelementptr %0* %iz, i32 0, i32 0
-  %tmp7 = getelementptr %0* %z, i32 0, i32 0
-  %tmp8 = load x86_fp80* %tmp7, align 16
+  %tmp4 = getelementptr %0, %0* %iz, i32 0, i32 1
+  %real = getelementptr %0, %0* %iz, i32 0, i32 0
+  %tmp7 = getelementptr %0, %0* %z, i32 0, i32 0
+  %tmp8 = load x86_fp80, x86_fp80* %tmp7, align 16
   store x86_fp80 %tmp3, x86_fp80* %real, align 16
   store x86_fp80 %tmp8, x86_fp80* %tmp4, align 16
   call void @ccoshl(%0* noalias sret %memtmp, %0* byval align 8 %iz) nounwind
diff --git a/test/Transforms/MergeFunc/2011-02-08-RemoveEqual.ll b/test/Transforms/MergeFunc/2011-02-08-RemoveEqual.ll
index 19cd6a5171da..4735ea5e61d2 100644
--- a/test/Transforms/MergeFunc/2011-02-08-RemoveEqual.ll
+++ b/test/Transforms/MergeFunc/2011-02-08-RemoveEqual.ll
@@ -36,15 +36,15 @@ entry:
   store %"struct.kc::impl_fileline_FileLine"* %this, %"struct.kc::impl_fileline_FileLine"** %this_addr
   store %"struct.kc::impl_casestring__Str"* %_file, %"struct.kc::impl_casestring__Str"** %_file_addr
   store i32 %_line, i32* %_line_addr
-  %0 = load %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
-  %1 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine"* %0, i32 0, i32 0
+  %0 = load %"struct.kc::impl_fileline_FileLine"*, %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
+  %1 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine", %"struct.kc::impl_fileline_FileLine"* %0, i32 0, i32 0
   call void @_ZN2kc13impl_filelineC2Ev() nounwind
-  %2 = load %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
-  %3 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine"* %2, i32 0, i32 0
-  %4 = getelementptr inbounds %"struct.kc::impl_fileline"* %3, i32 0, i32 0
-  %5 = getelementptr inbounds %"struct.kc::impl_abstract_phylum"* %4, i32 0, i32 0
-  store i32 (...)** getelementptr inbounds ([13 x i32 (...)*]* @_ZTVN2kc22impl_fileline_FileLineE, i32 0, i32 2), i32 (...)*** %5, align 4
-  %6 = load %"struct.kc::impl_casestring__Str"** %_file_addr, align 4
+  %2 = load %"struct.kc::impl_fileline_FileLine"*, %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
+  %3 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine", %"struct.kc::impl_fileline_FileLine"* %2, i32 0, i32 0
+  %4 = getelementptr inbounds %"struct.kc::impl_fileline", %"struct.kc::impl_fileline"* %3, i32 0, i32 0
+  %5 = getelementptr inbounds %"struct.kc::impl_abstract_phylum", %"struct.kc::impl_abstract_phylum"* %4, i32 0, i32 0
+  store i32 (...)** getelementptr inbounds ([13 x i32 (...)*], [13 x i32 (...)*]* @_ZTVN2kc22impl_fileline_FileLineE, i32 0, i32 2), i32 (...)*** %5, align 4
+  %6 = load %"struct.kc::impl_casestring__Str"*, %"struct.kc::impl_casestring__Str"** %_file_addr, align 4
   %7 = icmp eq %"struct.kc::impl_casestring__Str"* %6, null
   br i1 %7, label %bb, label %bb1
 
@@ -57,20 +57,20 @@ invcont:                                          ; preds = %bb
   br label %bb2
 
 bb1:                                              ; preds = %entry
-  %9 = load %"struct.kc::impl_casestring__Str"** %_file_addr, align 4
+  %9 = load %"struct.kc::impl_casestring__Str"*, %"struct.kc::impl_casestring__Str"** %_file_addr, align 4
   store %"struct.kc::impl_casestring__Str"* %9, %"struct.kc::impl_casestring__Str"** %iftmp.99, align 4
   br label %bb2
 
 bb2:                                              ; preds = %bb1, %invcont
-  %10 = load %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
-  %11 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine"* %10, i32 0, i32 0
-  %12 = getelementptr inbounds %"struct.kc::impl_fileline"* %11, i32 0, i32 1
-  %13 = load %"struct.kc::impl_casestring__Str"** %iftmp.99, align 4
+  %10 = load %"struct.kc::impl_fileline_FileLine"*, %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
+  %11 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine", %"struct.kc::impl_fileline_FileLine"* %10, i32 0, i32 0
+  %12 = getelementptr inbounds %"struct.kc::impl_fileline", %"struct.kc::impl_fileline"* %11, i32 0, i32 1
+  %13 = load %"struct.kc::impl_casestring__Str"*, %"struct.kc::impl_casestring__Str"** %iftmp.99, align 4
   store %"struct.kc::impl_casestring__Str"* %13, %"struct.kc::impl_casestring__Str"** %12, align 4
-  %14 = load %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
-  %15 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine"* %14, i32 0, i32 0
-  %16 = getelementptr inbounds %"struct.kc::impl_fileline"* %15, i32 0, i32 2
-  %17 = load i32* %_line_addr, align 4
+  %14 = load %"struct.kc::impl_fileline_FileLine"*, %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
+  %15 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine", %"struct.kc::impl_fileline_FileLine"* %14, i32 0, i32 0
+  %16 = getelementptr inbounds %"struct.kc::impl_fileline", %"struct.kc::impl_fileline"* %15, i32 0, i32 2
+  %17 = load i32, i32* %_line_addr, align 4
   store i32 %17, i32* %16, align 4
   ret void
 
@@ -79,21 +79,21 @@ lpad:                                             ; preds = %bb
               cleanup
   %exn = extractvalue { i8*, i32 } %eh_ptr, 0
   store i8* %exn, i8** %eh_exception
-  %eh_ptr4 = load i8** %eh_exception
+  %eh_ptr4 = load i8*, i8** %eh_exception
   %eh_select5 = extractvalue { i8*, i32 } %eh_ptr, 1
   store i32 %eh_select5, i32* %eh_selector
-  %eh_select = load i32* %eh_selector
+  %eh_select = load i32, i32* %eh_selector
   store i32 %eh_select, i32* %save_filt.150, align 4
-  %eh_value = load i8** %eh_exception
+  %eh_value = load i8*, i8** %eh_exception
   store i8* %eh_value, i8** %save_eptr.149, align 4
-  %18 = load %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
+  %18 = load %"struct.kc::impl_fileline_FileLine"*, %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
   %19 = bitcast %"struct.kc::impl_fileline_FileLine"* %18 to %"struct.kc::impl_fileline"*
   call void @_ZN2kc13impl_filelineD2Ev(%"struct.kc::impl_fileline"* %19) nounwind
-  %20 = load i8** %save_eptr.149, align 4
+  %20 = load i8*, i8** %save_eptr.149, align 4
   store i8* %20, i8** %eh_exception, align 4
-  %21 = load i32* %save_filt.150, align 4
+  %21 = load i32, i32* %save_filt.150, align 4
   store i32 %21, i32* %eh_selector, align 4
-  %eh_ptr6 = load i8** %eh_exception
+  %eh_ptr6 = load i8*, i8** %eh_exception
   call void @_Unwind_Resume_or_Rethrow()
   unreachable
 }
@@ -105,16 +105,16 @@ entry:
   %this_addr = alloca %"struct.kc::impl_fileline"*, align 4
   %"alloca point" = bitcast i32 0 to i32
   store %"struct.kc::impl_fileline"* %this, %"struct.kc::impl_fileline"** %this_addr
-  %0 = load %"struct.kc::impl_fileline"** %this_addr, align 4
-  %1 = getelementptr inbounds %"struct.kc::impl_fileline"* %0, i32 0, i32 0
-  %2 = getelementptr inbounds %"struct.kc::impl_abstract_phylum"* %1, i32 0, i32 0
-  store i32 (...)** getelementptr inbounds ([13 x i32 (...)*]* @_ZTVN2kc13impl_filelineE, i32 0, i32 2), i32 (...)*** %2, align 4
+  %0 = load %"struct.kc::impl_fileline"*, %"struct.kc::impl_fileline"** %this_addr, align 4
+  %1 = getelementptr inbounds %"struct.kc::impl_fileline", %"struct.kc::impl_fileline"* %0, i32 0, i32 0
+  %2 = getelementptr inbounds %"struct.kc::impl_abstract_phylum", %"struct.kc::impl_abstract_phylum"* %1, i32 0, i32 0
+  store i32 (...)** getelementptr inbounds ([13 x i32 (...)*], [13 x i32 (...)*]* @_ZTVN2kc13impl_filelineE, i32 0, i32 2), i32 (...)*** %2, align 4
   %3 = trunc i32 0 to i8
   %toBool = icmp ne i8 %3, 0
   br i1 %toBool, label %bb1, label %return
 
 bb1:                                              ; preds = %entry
-  %4 = load %"struct.kc::impl_fileline"** %this_addr, align 4
+  %4 = load %"struct.kc::impl_fileline"*, %"struct.kc::impl_fileline"** %this_addr, align 4
   %5 = bitcast %"struct.kc::impl_fileline"* %4 to i8*
   call void @_ZdlPv() nounwind
   br label %return
@@ -130,16 +130,16 @@ entry:
   %this_addr = alloca %"struct.kc::impl_fileline"*, align 4
   %"alloca point" = bitcast i32 0 to i32
   store %"struct.kc::impl_fileline"* %this, %"struct.kc::impl_fileline"** %this_addr
-  %0 = load %"struct.kc::impl_fileline"** %this_addr, align 4
-  %1 = getelementptr inbounds %"struct.kc::impl_fileline"* %0, i32 0, i32 0
-  %2 = getelementptr inbounds %"struct.kc::impl_abstract_phylum"* %1, i32 0, i32 0
-  store i32 (...)** getelementptr inbounds ([13 x i32 (...)*]* @_ZTVN2kc13impl_filelineE, i32 0, i32 2), i32 (...)*** %2, align 4
+  %0 = load %"struct.kc::impl_fileline"*, %"struct.kc::impl_fileline"** %this_addr, align 4
+  %1 = getelementptr inbounds %"struct.kc::impl_fileline", %"struct.kc::impl_fileline"* %0, i32 0, i32 0
+  %2 = getelementptr inbounds %"struct.kc::impl_abstract_phylum", %"struct.kc::impl_abstract_phylum"* %1, i32 0, i32 0
+  store i32 (...)** getelementptr inbounds ([13 x i32 (...)*], [13 x i32 (...)*]* @_ZTVN2kc13impl_filelineE, i32 0, i32 2), i32 (...)*** %2, align 4
   %3 = trunc i32 0 to i8
   %toBool = icmp ne i8 %3, 0
   br i1 %toBool, label %bb1, label %return
 
 bb1:                                              ; preds = %entry
-  %4 = load %"struct.kc::impl_fileline"** %this_addr, align 4
+  %4 = load %"struct.kc::impl_fileline"*, %"struct.kc::impl_fileline"** %this_addr, align 4
   %5 = bitcast %"struct.kc::impl_fileline"* %4 to i8*
   call void @_ZdlPv() nounwind
   br label %return
@@ -162,15 +162,15 @@ entry:
   store %"struct.kc::impl_fileline_FileLine"* %this, %"struct.kc::impl_fileline_FileLine"** %this_addr
   store %"struct.kc::impl_casestring__Str"* %_file, %"struct.kc::impl_casestring__Str"** %_file_addr
   store i32 %_line, i32* %_line_addr
-  %0 = load %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
-  %1 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine"* %0, i32 0, i32 0
+  %0 = load %"struct.kc::impl_fileline_FileLine"*, %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
+  %1 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine", %"struct.kc::impl_fileline_FileLine"* %0, i32 0, i32 0
   call void @_ZN2kc13impl_filelineC2Ev() nounwind
-  %2 = load %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
-  %3 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine"* %2, i32 0, i32 0
-  %4 = getelementptr inbounds %"struct.kc::impl_fileline"* %3, i32 0, i32 0
-  %5 = getelementptr inbounds %"struct.kc::impl_abstract_phylum"* %4, i32 0, i32 0
-  store i32 (...)** getelementptr inbounds ([13 x i32 (...)*]* @_ZTVN2kc22impl_fileline_FileLineE, i32 0, i32 2), i32 (...)*** %5, align 4
-  %6 = load %"struct.kc::impl_casestring__Str"** %_file_addr, align 4
+  %2 = load %"struct.kc::impl_fileline_FileLine"*, %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
+  %3 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine", %"struct.kc::impl_fileline_FileLine"* %2, i32 0, i32 0
+  %4 = getelementptr inbounds %"struct.kc::impl_fileline", %"struct.kc::impl_fileline"* %3, i32 0, i32 0
+  %5 = getelementptr inbounds %"struct.kc::impl_abstract_phylum", %"struct.kc::impl_abstract_phylum"* %4, i32 0, i32 0
+  store i32 (...)** getelementptr inbounds ([13 x i32 (...)*], [13 x i32 (...)*]* @_ZTVN2kc22impl_fileline_FileLineE, i32 0, i32 2), i32 (...)*** %5, align 4
+  %6 = load %"struct.kc::impl_casestring__Str"*, %"struct.kc::impl_casestring__Str"** %_file_addr, align 4
   %7 = icmp eq %"struct.kc::impl_casestring__Str"* %6, null
   br i1 %7, label %bb, label %bb1
 
@@ -183,20 +183,20 @@ invcont:                                          ; preds = %bb
   br label %bb2
 
 bb1:                                              ; preds = %entry
-  %9 = load %"struct.kc::impl_casestring__Str"** %_file_addr, align 4
+  %9 = load %"struct.kc::impl_casestring__Str"*, %"struct.kc::impl_casestring__Str"** %_file_addr, align 4
   store %"struct.kc::impl_casestring__Str"* %9, %"struct.kc::impl_casestring__Str"** %iftmp.99, align 4
   br label %bb2
 
 bb2:                                              ; preds = %bb1, %invcont
-  %10 = load %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
-  %11 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine"* %10, i32 0, i32 0
-  %12 = getelementptr inbounds %"struct.kc::impl_fileline"* %11, i32 0, i32 1
-  %13 = load %"struct.kc::impl_casestring__Str"** %iftmp.99, align 4
+  %10 = load %"struct.kc::impl_fileline_FileLine"*, %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
+  %11 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine", %"struct.kc::impl_fileline_FileLine"* %10, i32 0, i32 0
+  %12 = getelementptr inbounds %"struct.kc::impl_fileline", %"struct.kc::impl_fileline"* %11, i32 0, i32 1
+  %13 = load %"struct.kc::impl_casestring__Str"*, %"struct.kc::impl_casestring__Str"** %iftmp.99, align 4
   store %"struct.kc::impl_casestring__Str"* %13, %"struct.kc::impl_casestring__Str"** %12, align 4
-  %14 = load %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
-  %15 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine"* %14, i32 0, i32 0
-  %16 = getelementptr inbounds %"struct.kc::impl_fileline"* %15, i32 0, i32 2
-  %17 = load i32* %_line_addr, align 4
+  %14 = load %"struct.kc::impl_fileline_FileLine"*, %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
+  %15 = getelementptr inbounds %"struct.kc::impl_fileline_FileLine", %"struct.kc::impl_fileline_FileLine"* %14, i32 0, i32 0
+  %16 = getelementptr inbounds %"struct.kc::impl_fileline", %"struct.kc::impl_fileline"* %15, i32 0, i32 2
+  %17 = load i32, i32* %_line_addr, align 4
   store i32 %17, i32* %16, align 4
   ret void
 
@@ -205,21 +205,21 @@ lpad:                                             ; preds = %bb
               cleanup
   %exn = extractvalue { i8*, i32 } %eh_ptr, 0
   store i8* %exn, i8** %eh_exception
-  %eh_ptr4 = load i8** %eh_exception
+  %eh_ptr4 = load i8*, i8** %eh_exception
   %eh_select5 = extractvalue { i8*, i32 } %eh_ptr, 1
   store i32 %eh_select5, i32* %eh_selector
-  %eh_select = load i32* %eh_selector
+  %eh_select = load i32, i32* %eh_selector
   store i32 %eh_select, i32* %save_filt.148, align 4
-  %eh_value = load i8** %eh_exception
+  %eh_value = load i8*, i8** %eh_exception
   store i8* %eh_value, i8** %save_eptr.147, align 4
-  %18 = load %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
+  %18 = load %"struct.kc::impl_fileline_FileLine"*, %"struct.kc::impl_fileline_FileLine"** %this_addr, align 4
   %19 = bitcast %"struct.kc::impl_fileline_FileLine"* %18 to %"struct.kc::impl_fileline"*
   call void @_ZN2kc13impl_filelineD2Ev(%"struct.kc::impl_fileline"* %19) nounwind
-  %20 = load i8** %save_eptr.147, align 4
+  %20 = load i8*, i8** %save_eptr.147, align 4
   store i8* %20, i8** %eh_exception, align 4
-  %21 = load i32* %save_filt.148, align 4
+  %21 = load i32, i32* %save_filt.148, align 4
   store i32 %21, i32* %eh_selector, align 4
-  %eh_ptr6 = load i8** %eh_exception
+  %eh_ptr6 = load i8*, i8** %eh_exception
   call void @_Unwind_Resume_or_Rethrow()
   unreachable
 }
diff --git a/test/Transforms/MergeFunc/address-spaces.ll b/test/Transforms/MergeFunc/address-spaces.ll
index 0d66b8281fb2..1cfecae979d2 100644
--- a/test/Transforms/MergeFunc/address-spaces.ll
+++ b/test/Transforms/MergeFunc/address-spaces.ll
@@ -9,8 +9,8 @@ declare void @foo(i32) nounwind
 define i32 @store_as0(i32* %x) {
 ; CHECK-LABEL: @store_as0(
 ; CHECK: call void @foo(
-  %gep = getelementptr i32* %x, i32 4
-  %y = load i32* %gep
+  %gep = getelementptr i32, i32* %x, i32 4
+  %y = load i32, i32* %gep
   call void @foo(i32 %y) nounwind
   ret i32 %y
 }
@@ -18,8 +18,8 @@ define i32 @store_as0(i32* %x) {
 define i32 @store_as1(i32 addrspace(1)* %x) {
 ; CHECK-LABEL: @store_as1(
 ; CHECK: call void @foo(
-  %gep = getelementptr i32 addrspace(1)* %x, i32 4
-  %y = load i32 addrspace(1)* %gep
+  %gep = getelementptr i32, i32 addrspace(1)* %x, i32 4
+  %y = load i32, i32 addrspace(1)* %gep
   call void @foo(i32 %y) nounwind
   ret i32 %y
 }
@@ -27,8 +27,8 @@ define i32 @store_as1(i32 addrspace(1)* %x) {
 define i32 @store_as2(i32 addrspace(2)* %x) {
 ; CHECK-LABEL: @store_as2(
 ; CHECK: call void @foo(
-  %gep = getelementptr i32 addrspace(2)* %x, i32 4
-  %y = load i32 addrspace(2)* %gep
+  %gep = getelementptr i32, i32 addrspace(2)* %x, i32 4
+  %y = load i32, i32 addrspace(2)* %gep
   call void @foo(i32 %y) nounwind
   ret i32 %y
 }
diff --git a/test/Transforms/MergeFunc/alloca.ll b/test/Transforms/MergeFunc/alloca.ll
new file mode 100644
index 000000000000..d9f66d0911da
--- /dev/null
+++ b/test/Transforms/MergeFunc/alloca.ll
@@ -0,0 +1,33 @@
+; RUN: opt -mergefunc -S < %s | FileCheck %s
+
+;; Make sure that two different sized allocas are not treated as equal.
+
+target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"
+
+%kv1 = type { i32, i32 }
+%kv2 = type { i8 }
+
+
+define void @a(i8 *%f) {
+  %v = alloca %kv1, align 8
+  %f_2 = bitcast i8* %f to void (%kv1 *)*
+  call void %f_2(%kv1 * %v)
+  call void %f_2(%kv1 * %v)
+  call void %f_2(%kv1 * %v)
+  call void %f_2(%kv1 * %v)
+  ret void
+}
+
+; CHECK-LABEL: define void @b
+; CHECK-NOT: call @a
+; CHECK: ret
+
+define void @b(i8 *%f) {
+  %v = alloca %kv2, align 8
+  %f_2 = bitcast i8* %f to void (%kv2 *)*
+  call void %f_2(%kv2 * %v)
+  call void %f_2(%kv2 * %v)
+  call void %f_2(%kv2 * %v)
+  call void %f_2(%kv2 * %v)
+  ret void
+}
diff --git a/test/Transforms/MergeFunc/crash.ll b/test/Transforms/MergeFunc/crash.ll
index 3475e28a6565..73802203dc51 100644
--- a/test/Transforms/MergeFunc/crash.ll
+++ b/test/Transforms/MergeFunc/crash.ll
@@ -21,13 +21,13 @@ define internal i32 @func1(i32* %ptr, { i32, i32 }* nocapture %method) align 2 {
 }
 
 define internal i32 @func10(%.qux.2496* nocapture %this) align 2 {
-  %1 = getelementptr inbounds %.qux.2496* %this, i32 0, i32 1, i32 1
-  %2 = load i32* %1, align 4
+  %1 = getelementptr inbounds %.qux.2496, %.qux.2496* %this, i32 0, i32 1, i32 1
+  %2 = load i32, i32* %1, align 4
   ret i32 %2
 }
 
 define internal i8* @func29(i32* nocapture %this) align 2 {
-  ret i8* getelementptr inbounds ([9 x i8]* @g2, i32 0, i32 0)
+  ret i8* getelementptr inbounds ([9 x i8], [9 x i8]* @g2, i32 0, i32 0)
 }
 
 define internal i32* @func33(%.qux.2585* nocapture %this) align 2 {
@@ -35,12 +35,12 @@ define internal i32* @func33(%.qux.2585* nocapture %this) align 2 {
 }
 
 define internal i32* @func34(%.qux.2585* nocapture %this) align 2 {
-  %1 = getelementptr inbounds %.qux.2585* %this, i32 0
+  %1 = getelementptr inbounds %.qux.2585, %.qux.2585* %this, i32 0
   ret i32* undef
 }
 
 define internal i8* @func35(%.qux.2585* nocapture %this) align 2 {
-  %1 = getelementptr inbounds %.qux.2585* %this, i32 0, i32 2
-  %2 = load i8** %1, align 4
+  %1 = getelementptr inbounds %.qux.2585, %.qux.2585* %this, i32 0, i32 2
+  %2 = load i8*, i8** %1, align 4
   ret i8* %2
 }
diff --git a/test/Transforms/MergeFunc/inttoptr-address-space.ll b/test/Transforms/MergeFunc/inttoptr-address-space.ll
index 2e5e2fcc4865..5f672debd919 100644
--- a/test/Transforms/MergeFunc/inttoptr-address-space.ll
+++ b/test/Transforms/MergeFunc/inttoptr-address-space.ll
@@ -11,8 +11,8 @@ target datalayout = "e-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-
 
 define internal i32 @func10(%.qux.2496 addrspace(1)* nocapture %this) align 2 {
 bb:
-  %tmp = getelementptr inbounds %.qux.2496 addrspace(1)* %this, i32 0, i32 1, i32 1
-  %tmp1 = load i32 addrspace(1)* %tmp, align 4
+  %tmp = getelementptr inbounds %.qux.2496, %.qux.2496 addrspace(1)* %this, i32 0, i32 1, i32 1
+  %tmp1 = load i32, i32 addrspace(1)* %tmp, align 4
   ret i32 %tmp1
 }
 
@@ -23,7 +23,7 @@ bb:
 ; CHECK: %[[V2:.+]] = bitcast %.qux.2585 addrspace(1)* %{{.*}} to %.qux.2496 addrspace(1)*
 ; CHECK: %[[V3:.+]] = tail call i32 @func10(%.qux.2496 addrspace(1)* %[[V2]])
 ; CHECK: %{{.*}} = inttoptr i32 %[[V3]] to i8*
-  %tmp = getelementptr inbounds %.qux.2585 addrspace(1)* %this, i32 0, i32 2
-  %tmp1 = load i8* addrspace(1)* %tmp, align 4
+  %tmp = getelementptr inbounds %.qux.2585, %.qux.2585 addrspace(1)* %this, i32 0, i32 2
+  %tmp1 = load i8*, i8* addrspace(1)* %tmp, align 4
   ret i8* %tmp1
 }
diff --git a/test/Transforms/MergeFunc/inttoptr.ll b/test/Transforms/MergeFunc/inttoptr.ll
index 86c18a0c122b..0abbf6239a34 100644
--- a/test/Transforms/MergeFunc/inttoptr.ll
+++ b/test/Transforms/MergeFunc/inttoptr.ll
@@ -23,14 +23,14 @@ bb2:                                              ; preds = %bb1
 
 define internal i32 @func10(%.qux.2496* nocapture %this) align 2 {
 bb:
-  %tmp = getelementptr inbounds %.qux.2496* %this, i32 0, i32 1, i32 1
-  %tmp1 = load i32* %tmp, align 4
+  %tmp = getelementptr inbounds %.qux.2496, %.qux.2496* %this, i32 0, i32 1, i32 1
+  %tmp1 = load i32, i32* %tmp, align 4
   ret i32 %tmp1
 }
 
 define internal i8* @func29(i32* nocapture %this) align 2 {
 bb:
-  ret i8* getelementptr inbounds ([9 x i8]* @g2, i32 0, i32 0)
+  ret i8* getelementptr inbounds ([9 x i8], [9 x i8]* @g2, i32 0, i32 0)
 }
 
 define internal i32* @func33(%.qux.2585* nocapture %this) align 2 {
@@ -40,7 +40,7 @@ bb:
 
 define internal i32* @func34(%.qux.2585* nocapture %this) align 2 {
 bb:
-  %tmp = getelementptr inbounds %.qux.2585* %this, i32 0
+  %tmp = getelementptr inbounds %.qux.2585, %.qux.2585* %this, i32 0
   ret i32* undef
 }
 
@@ -50,7 +50,7 @@ bb:
 ; CHECK: %[[V2:.+]] = bitcast %.qux.2585* %{{.*}} to %.qux.2496*
 ; CHECK: %[[V3:.+]] = tail call i32 @func10(%.qux.2496* %[[V2]])
 ; CHECK: %{{.*}} = inttoptr i32 %[[V3]] to i8*
-  %tmp = getelementptr inbounds %.qux.2585* %this, i32 0, i32 2
-  %tmp1 = load i8** %tmp, align 4
+  %tmp = getelementptr inbounds %.qux.2585, %.qux.2585* %this, i32 0, i32 2
+  %tmp1 = load i8*, i8** %tmp, align 4
   ret i8* %tmp1
 }
diff --git a/test/Transforms/MergeFunc/mergefunc-struct-return.ll b/test/Transforms/MergeFunc/mergefunc-struct-return.ll
index d2cbe43da0c4..14db39995e72 100644
--- a/test/Transforms/MergeFunc/mergefunc-struct-return.ll
+++ b/test/Transforms/MergeFunc/mergefunc-struct-return.ll
@@ -13,12 +13,12 @@ declare void @noop()
 define %kv1 @fn1() {
 ; CHECK-LABEL: @fn1(
   %tmp = alloca %kv1
-  %v1 = getelementptr %kv1* %tmp, i32 0, i32 0
+  %v1 = getelementptr %kv1, %kv1* %tmp, i32 0, i32 0
   store i32* null, i32** %v1
-  %v2 = getelementptr %kv1* %tmp, i32 0, i32 0
+  %v2 = getelementptr %kv1, %kv1* %tmp, i32 0, i32 0
   store i32* null, i32** %v2
   call void @noop()
-  %v3 = load %kv1* %tmp
+  %v3 = load %kv1, %kv1* %tmp
   ret %kv1 %v3
 }
 
@@ -29,12 +29,12 @@ define %kv2 @fn2() {
 ; CHECK: %3 = bitcast i32* %2 to i8*
 ; CHECK: %4 = insertvalue %kv2 undef, i8* %3, 0
   %tmp = alloca %kv2
-  %v1 = getelementptr %kv2* %tmp, i32 0, i32 0
+  %v1 = getelementptr %kv2, %kv2* %tmp, i32 0, i32 0
   store i8* null, i8** %v1
-  %v2 = getelementptr %kv2* %tmp, i32 0, i32 0
+  %v2 = getelementptr %kv2, %kv2* %tmp, i32 0, i32 0
   store i8* null, i8** %v2
   call void @noop()
 
-  %v3 = load %kv2* %tmp
+  %v3 = load %kv2, %kv2* %tmp
   ret %kv2 %v3
 }
diff --git a/test/Transforms/MergeFunc/ranges.ll b/test/Transforms/MergeFunc/ranges.ll
index d3e4d942a9d5..46a0c76cc7d1 100644
--- a/test/Transforms/MergeFunc/ranges.ll
+++ b/test/Transforms/MergeFunc/ranges.ll
@@ -1,31 +1,31 @@
 ; RUN: opt -mergefunc -S < %s | FileCheck %s
 define i1 @cmp_with_range(i8*, i8*) {
-  %v1 = load i8* %0, !range !0
-  %v2 = load i8* %1, !range !0
+  %v1 = load i8, i8* %0, !range !0
+  %v2 = load i8, i8* %1, !range !0
   %out = icmp eq i8 %v1, %v2
   ret i1 %out
 }
 
 define i1 @cmp_no_range(i8*, i8*) {
 ; CHECK-LABEL: @cmp_no_range
-; CHECK-NEXT  %v1 = load i8* %0
-; CHECK-NEXT  %v2 = load i8* %1
+; CHECK-NEXT  %v1 = load i8, i8* %0
+; CHECK-NEXT  %v2 = load i8, i8* %1
 ; CHECK-NEXT  %out = icmp eq i8 %v1, %v2
 ; CHECK-NEXT  ret i1 %out
-  %v1 = load i8* %0
-  %v2 = load i8* %1
+  %v1 = load i8, i8* %0
+  %v2 = load i8, i8* %1
   %out = icmp eq i8 %v1, %v2
   ret i1 %out
 }
 
 define i1 @cmp_different_range(i8*, i8*) {
 ; CHECK-LABEL: @cmp_different_range
-; CHECK-NEXT:  %v1 = load i8* %0, !range !1
-; CHECK-NEXT:  %v2 = load i8* %1, !range !1
+; CHECK-NEXT:  %v1 = load i8, i8* %0, !range !1
+; CHECK-NEXT:  %v2 = load i8, i8* %1, !range !1
 ; CHECK-NEXT:  %out = icmp eq i8 %v1, %v2
 ; CHECK-NEXT:  ret i1 %out
-  %v1 = load i8* %0, !range !1
-  %v2 = load i8* %1, !range !1
+  %v1 = load i8, i8* %0, !range !1
+  %v2 = load i8, i8* %1, !range !1
   %out = icmp eq i8 %v1, %v2
   ret i1 %out
 }
@@ -33,8 +33,8 @@ define i1 @cmp_different_range(i8*, i8*) {
 define i1 @cmp_with_same_range(i8*, i8*) {
 ; CHECK-LABEL: @cmp_with_same_range
 ; CHECK: tail call i1 @cmp_with_range
-  %v1 = load i8* %0, !range !0
-  %v2 = load i8* %1, !range !0
+  %v1 = load i8, i8* %0, !range !0
+  %v2 = load i8, i8* %1, !range !0
   %out = icmp eq i8 %v1, %v2
   ret i1 %out
 }
diff --git a/test/Transforms/MergeFunc/vector-GEP-crash.ll b/test/Transforms/MergeFunc/vector-GEP-crash.ll
index a1eefa0bc983..d0e86ebf54b9 100644
--- a/test/Transforms/MergeFunc/vector-GEP-crash.ll
+++ b/test/Transforms/MergeFunc/vector-GEP-crash.ll
@@ -2,11 +2,11 @@
 ; This used to cause a crash when compairing the GEPs
 
 define void @foo(<2 x i64*>) {
-  %tmp = getelementptr <2 x i64*> %0, <2 x i64> <i64 0, i64 0>
+  %tmp = getelementptr i64, <2 x i64*> %0, <2 x i64> <i64 0, i64 0>
   ret void
 }
 
 define void @bar(<2 x i64*>) {
-  %tmp = getelementptr <2 x i64*> %0, <2 x i64> <i64 0, i64 0>
+  %tmp = getelementptr i64, <2 x i64*> %0, <2 x i64> <i64 0, i64 0>
   ret void
 }
diff --git a/test/Transforms/MergeFunc/vector.ll b/test/Transforms/MergeFunc/vector.ll
index 56f74e65c60d..ef1375311e60 100644
--- a/test/Transforms/MergeFunc/vector.ll
+++ b/test/Transforms/MergeFunc/vector.ll
@@ -22,7 +22,7 @@ target triple = "x86_64-unknown-linux-gnu"
 define linkonce_odr void @_ZNSt6vectorIlSaIlEED1Ev(%"class.std::vector"* nocapture %this) unnamed_addr align 2 {
 entry:
   %tmp2.i.i = bitcast %"class.std::vector"* %this to i64**
-  %tmp3.i.i = load i64** %tmp2.i.i, align 8
+  %tmp3.i.i = load i64*, i64** %tmp2.i.i, align 8
   %tobool.i.i.i = icmp eq i64* %tmp3.i.i, null
   br i1 %tobool.i.i.i, label %_ZNSt6vectorIlSaIlEED2Ev.exit, label %if.then.i.i.i
 
@@ -40,7 +40,7 @@ declare i32 @__cxa_atexit(void (i8*)*, i8*, i8*)
 define linkonce_odr void @_ZNSt6vectorIPvSaIS0_EED1Ev(%"class.std::vector"* nocapture %this) unnamed_addr align 2 {
 entry:
   %tmp2.i.i = bitcast %"class.std::vector"* %this to i8***
-  %tmp3.i.i = load i8*** %tmp2.i.i, align 8
+  %tmp3.i.i = load i8**, i8*** %tmp2.i.i, align 8
   %tobool.i.i.i = icmp eq i8** %tmp3.i.i, null
   br i1 %tobool.i.i.i, label %_ZNSt6vectorIPvSaIS0_EED2Ev.exit, label %if.then.i.i.i
 
diff --git a/test/Transforms/MetaRenamer/metarenamer.ll b/test/Transforms/MetaRenamer/metarenamer.ll
index 4010f31ff772..e126bed9b232 100644
--- a/test/Transforms/MetaRenamer/metarenamer.ll
+++ b/test/Transforms/MetaRenamer/metarenamer.ll
@@ -24,14 +24,14 @@ define i32 @func_3_xxx() nounwind uwtable ssp {
 
 define void @func_4_xxx(%struct.foo_xxx* sret %agg.result) nounwind uwtable ssp {
   %1 = alloca %struct.foo_xxx, align 8
-  %2 = getelementptr inbounds %struct.foo_xxx* %1, i32 0, i32 0
+  %2 = getelementptr inbounds %struct.foo_xxx, %struct.foo_xxx* %1, i32 0, i32 0
   store i32 1, i32* %2, align 4
-  %3 = getelementptr inbounds %struct.foo_xxx* %1, i32 0, i32 1
+  %3 = getelementptr inbounds %struct.foo_xxx, %struct.foo_xxx* %1, i32 0, i32 1
   store float 2.000000e+00, float* %3, align 4
-  %4 = getelementptr inbounds %struct.foo_xxx* %1, i32 0, i32 2
-  %5 = getelementptr inbounds %struct.bar_xxx* %4, i32 0, i32 0
+  %4 = getelementptr inbounds %struct.foo_xxx, %struct.foo_xxx* %1, i32 0, i32 2
+  %5 = getelementptr inbounds %struct.bar_xxx, %struct.bar_xxx* %4, i32 0, i32 0
   store i32 3, i32* %5, align 4
-  %6 = getelementptr inbounds %struct.bar_xxx* %4, i32 0, i32 1
+  %6 = getelementptr inbounds %struct.bar_xxx, %struct.bar_xxx* %4, i32 0, i32 1
   store double 4.000000e+00, double* %6, align 8
   %7 = bitcast %struct.foo_xxx* %agg.result to i8*
   %8 = bitcast %struct.foo_xxx* %1 to i8*
@@ -59,7 +59,7 @@ define i32 @func_5_xxx(i32 %arg_1_xxx, i32 %arg_2_xxx, i32 %arg_3_xxx, i32 %arg_
   br label %5
 
 ; <label>:5                                       ; preds = %9, %0
-  %6 = load i32* %i, align 4
+  %6 = load i32, i32* %i, align 4
   %7 = icmp slt i32 %6, 10
   br i1 %7, label %8, label %12
 
@@ -67,24 +67,24 @@ define i32 @func_5_xxx(i32 %arg_1_xxx, i32 %arg_2_xxx, i32 %arg_3_xxx, i32 %arg_
   br label %9
 
 ; <label>:9                                       ; preds = %8
-  %10 = load i32* %i, align 4
+  %10 = load i32, i32* %i, align 4
   %11 = add nsw i32 %10, 1
   store i32 %11, i32* %i, align 4
   br label %5
 
 ; <label>:12                                      ; preds = %5
-  %13 = load i32* %local_1_xxx, align 4
-  %14 = load i32* %1, align 4
+  %13 = load i32, i32* %local_1_xxx, align 4
+  %14 = load i32, i32* %1, align 4
   %15 = add nsw i32 %13, %14
-  %16 = load i32* %local_2_xxx, align 4
+  %16 = load i32, i32* %local_2_xxx, align 4
   %17 = add nsw i32 %15, %16
-  %18 = load i32* %2, align 4
+  %18 = load i32, i32* %2, align 4
   %19 = add nsw i32 %17, %18
-  %20 = load i32* @func_5_xxx.static_local_3_xxx, align 4
+  %20 = load i32, i32* @func_5_xxx.static_local_3_xxx, align 4
   %21 = add nsw i32 %19, %20
-  %22 = load i32* %3, align 4
+  %22 = load i32, i32* %3, align 4
   %23 = add nsw i32 %21, %22
-  %24 = load i32* %4, align 4
+  %24 = load i32, i32* %4, align 4
   %25 = add nsw i32 %23, %24
   ret i32 %25
 }
diff --git a/test/Transforms/NaryReassociate/NVPTX/lit.local.cfg b/test/Transforms/NaryReassociate/NVPTX/lit.local.cfg
new file mode 100644
index 000000000000..2cb98eb371b2
--- /dev/null
+++ b/test/Transforms/NaryReassociate/NVPTX/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'NVPTX' in config.root.targets:
+    config.unsupported = True
diff --git a/test/Transforms/NaryReassociate/NVPTX/nary-gep.ll b/test/Transforms/NaryReassociate/NVPTX/nary-gep.ll
new file mode 100644
index 000000000000..a620c98ec18f
--- /dev/null
+++ b/test/Transforms/NaryReassociate/NVPTX/nary-gep.ll
@@ -0,0 +1,77 @@
+; RUN: opt < %s -nary-reassociate -S | FileCheck %s
+
+target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
+target triple = "nvptx64-unknown-unknown"
+
+declare void @foo(float*)
+
+; foo(&a[i]);
+; foo(&a[i + j]);
+;   =>
+; t = &a[i];
+; foo(t);
+; foo(t + j);
+define void @reassociate_gep(float* %a, i64 %i, i64 %j) {
+; CHECK-LABEL: @reassociate_gep(
+  %1 = add i64 %i, %j
+  %2 = getelementptr float, float* %a, i64 %i
+; CHECK: [[t1:[^ ]+]] = getelementptr float, float* %a, i64 %i
+  call void @foo(float* %2)
+; CHECK: call void @foo(float* [[t1]])
+  %3 = getelementptr float, float* %a, i64 %1
+; CHECK: [[t2:[^ ]+]] = getelementptr float, float* [[t1]], i64 %j
+  call void @foo(float* %3)
+; CHECK: call void @foo(float* [[t2]])
+  ret void
+}
+
+; foo(&a[sext(j)]);
+; foo(&a[sext(i +nsw j)]);
+;   =>
+; t = &a[sext(j)];
+; foo(t);
+; foo(t + sext(i));
+define void @reassociate_gep_nsw(float* %a, i32 %i, i32 %j) {
+; CHECK-LABEL: @reassociate_gep_nsw(
+  %1 = add nsw i32 %i, %j
+  %idxprom.1 = sext i32 %1 to i64
+  %idxprom.j = sext i32 %j to i64
+  %2 = getelementptr float, float* %a, i64 %idxprom.j
+; CHECK: [[t1:[^ ]+]] = getelementptr float, float* %a, i64 %idxprom.j
+  call void @foo(float* %2)
+; CHECK: call void @foo(float* [[t1]])
+  %3 = getelementptr float, float* %a, i64 %idxprom.1
+; CHECK: [[sexti:[^ ]+]] = sext i32 %i to i64
+; CHECK: [[t2:[^ ]+]] = getelementptr float, float* [[t1]], i64 [[sexti]]
+  call void @foo(float* %3)
+; CHECK: call void @foo(float* [[t2]])
+  ret void
+}
+
+; Do not split the second GEP because sext(i + j) != sext(i) + sext(j).
+define void @reassociate_gep_no_nsw(float* %a, i32 %i, i32 %j) {
+; CHECK-LABEL: @reassociate_gep_no_nsw(
+  %1 = add i32 %i, %j
+  %2 = getelementptr float, float* %a, i32 %j
+; CHECK: getelementptr float, float* %a, i32 %j
+  call void @foo(float* %2)
+  %3 = getelementptr float, float* %a, i32 %1
+; CHECK: getelementptr float, float* %a, i32 %1
+  call void @foo(float* %3)
+  ret void
+}
+
+define void @reassociate_gep_128(float* %a, i128 %i, i128 %j) {
+; CHECK-LABEL: @reassociate_gep_128(
+  %1 = add i128 %i, %j
+  %2 = getelementptr float, float* %a, i128 %i
+; CHECK: [[t1:[^ ]+]] = getelementptr float, float* %a, i128 %i
+  call void @foo(float* %2)
+; CHECK: call void @foo(float* [[t1]])
+  %3 = getelementptr float, float* %a, i128 %1
+; CHECK: [[truncj:[^ ]+]] = trunc i128 %j to i64
+; CHECK: [[t2:[^ ]+]] = getelementptr float, float* [[t1]], i64 [[truncj]]
+  call void @foo(float* %3)
+; CHECK: call void @foo(float* [[t2]])
+  ret void
+}
diff --git a/test/Transforms/NaryReassociate/NVPTX/nary-slsr.ll b/test/Transforms/NaryReassociate/NVPTX/nary-slsr.ll
new file mode 100644
index 000000000000..2360fe7f1b78
--- /dev/null
+++ b/test/Transforms/NaryReassociate/NVPTX/nary-slsr.ll
@@ -0,0 +1,47 @@
+; RUN: opt < %s -slsr -nary-reassociate -S | FileCheck %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX
+
+target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
+
+; foo((a + b) + c);
+; foo((a + b * 2) + c);
+; foo((a + b * 3) + c);
+;   =>
+; abc = (a + b) + c;
+; foo(abc);
+; ab2c = abc + b;
+; foo(ab2c);
+; ab3c = ab2c + b;
+; foo(ab3c);
+define void @nary_reassociate_after_slsr(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @nary_reassociate_after_slsr(
+; PTX-LABEL: .visible .func nary_reassociate_after_slsr(
+; PTX: ld.param.u32 [[b:%r[0-9]+]], [nary_reassociate_after_slsr_param_1];
+  %ab = add i32 %a, %b
+  %abc = add i32 %ab, %c
+  call void @foo(i32 %abc)
+; CHECK: call void @foo(i32 %abc)
+; PTX: st.param.b32 [param0+0], [[abc:%r[0-9]+]];
+
+  %b2 = shl i32 %b, 1
+  %ab2 = add i32 %a, %b2
+  %ab2c = add i32 %ab2, %c
+; CHECK-NEXT: %ab2c = add i32 %abc, %b
+; PTX: add.s32 [[ab2c:%r[0-9]+]], [[abc]], [[b]]
+  call void @foo(i32 %ab2c)
+; CHECK-NEXT: call void @foo(i32 %ab2c)
+; PTX: st.param.b32 [param0+0], [[ab2c]];
+
+  %b3 = mul i32 %b, 3
+  %ab3 = add i32 %a, %b3
+  %ab3c = add i32 %ab3, %c
+; CHECK-NEXT: %ab3c = add i32 %ab2c, %b
+; PTX: add.s32 [[ab3c:%r[0-9]+]], [[ab2c]], [[b]]
+  call void @foo(i32 %ab3c)
+; CHECK-NEXT: call void @foo(i32 %ab3c)
+; PTX: st.param.b32 [param0+0], [[ab3c]];
+
+  ret void
+}
+
+declare void @foo(i32)
diff --git a/test/Transforms/NaryReassociate/nary-add.ll b/test/Transforms/NaryReassociate/nary-add.ll
new file mode 100644
index 000000000000..b3093ff6ecd6
--- /dev/null
+++ b/test/Transforms/NaryReassociate/nary-add.ll
@@ -0,0 +1,209 @@
+; RUN: opt < %s -nary-reassociate -S | FileCheck %s
+
+target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
+
+declare void @foo(i32)
+
+; foo(a + c);
+; foo((a + (b + c));
+;   =>
+; t = a + c;
+; foo(t);
+; foo(t + b);
+define void @left_reassociate(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @left_reassociate(
+  %1 = add i32 %a, %c
+; CHECK: [[BASE:%[a-zA-Z0-9]+]] = add i32 %a, %c
+  call void @foo(i32 %1)
+  %2 = add i32 %b, %c
+  %3 = add i32 %a, %2
+; CHECK: add i32 [[BASE]], %b
+  call void @foo(i32 %3)
+  ret void
+}
+
+; foo(a + c);
+; foo((a + b) + c);
+;   =>
+; t = a + c;
+; foo(t);
+; foo(t + b);
+define void @right_reassociate(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @right_reassociate(
+  %1 = add i32 %a, %c
+; CHECK: [[BASE:%[a-zA-Z0-9]+]] = add i32 %a, %c
+  call void @foo(i32 %1)
+  %2 = add i32 %a, %b
+  %3 = add i32 %2, %c
+; CHECK: add i32 [[BASE]], %b
+  call void @foo(i32 %3)
+  ret void
+}
+
+; t1 = a + c;
+; foo(t1);
+; t2 = a + b;
+; foo(t2);
+; t3 = t2 + c;
+; foo(t3);
+;
+; Do not rewrite t3 into t1 + b because t2 is used elsewhere and is likely free.
+define void @no_reassociate(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @no_reassociate(
+  %1 = add i32 %a, %c
+; CHECK: add i32 %a, %c
+  call void @foo(i32 %1)
+  %2 = add i32 %a, %b
+; CHECK: add i32 %a, %b
+  call void @foo(i32 %2)
+  %3 = add i32 %2, %c
+; CHECK: add i32 %2, %c
+  call void @foo(i32 %3)
+  ret void
+}
+
+; if (p1)
+;   foo(a + c);
+; if (p2)
+;   foo(a + c);
+; if (p3)
+;   foo((a + b) + c);
+;
+; No action because (a + c) does not dominate ((a + b) + c).
+define void @conditional(i1 %p1, i1 %p2, i1 %p3, i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @conditional(
+entry:
+  br i1 %p1, label %then1, label %branch1
+
+then1:
+  %0 = add i32 %a, %c
+; CHECK: add i32 %a, %c
+  call void @foo(i32 %0)
+  br label %branch1
+
+branch1:
+  br i1 %p2, label %then2, label %branch2
+
+then2:
+  %1 = add i32 %a, %c
+; CHECK: add i32 %a, %c
+  call void @foo(i32 %1)
+  br label %branch2
+
+branch2:
+  br i1 %p3, label %then3, label %return
+
+then3:
+  %2 = add i32 %a, %b
+; CHECK: %2 = add i32 %a, %b
+  %3 = add i32 %2, %c
+; CHECK: add i32 %2, %c
+  call void @foo(i32 %3)
+  br label %return
+
+return:
+  ret void
+}
+
+; This test involves more conditional reassociation candidates. It exercises
+; the stack optimization in tryReassociatedAdd that pops the candidates that
+; do not dominate the current instruction.
+;
+;       def1
+;      cond1
+;      /  \
+;     /    \
+;   cond2  use2
+;   /  \
+;  /    \
+; def2  def3
+;      cond3
+;       /  \
+;      /    \
+;    def4   use1
+;
+; NaryReassociate should match use1 with def3, and use2 with def1.
+define void @conditional2(i32 %a, i32 %b, i32 %c, i1 %cond1, i1 %cond2, i1 %cond3) {
+entry:
+  %def1 = add i32 %a, %b
+  br i1 %cond1, label %bb1, label %bb6
+bb1:
+  br i1 %cond2, label %bb2, label %bb3
+bb2:
+  %def2 = add i32 %a, %b
+  call void @foo(i32 %def2)
+  ret void
+bb3:
+  %def3 = add i32 %a, %b
+  br i1 %cond3, label %bb4, label %bb5
+bb4:
+  %def4 = add i32 %a, %b
+  call void @foo(i32 %def4)
+  ret void
+bb5:
+  %0 = add i32 %a, %c
+  %1 = add i32 %0, %b
+; CHECK: [[t1:%[0-9]+]] = add i32 %def3, %c
+  call void @foo(i32 %1) ; foo((a + c) + b);
+; CHECK-NEXT: call void @foo(i32 [[t1]])
+  ret void
+bb6:
+  %2 = add i32 %a, %c
+  %3 = add i32 %2, %b
+; CHECK: [[t2:%[0-9]+]] = add i32 %def1, %c
+  call void @foo(i32 %3) ; foo((a + c) + b);
+; CHECK-NEXT: call void @foo(i32 [[t2]])
+  ret void
+}
+
+; foo((a + b) + c)
+; foo(((a + d) + b) + c)
+;   =>
+; t = (a + b) + c;
+; foo(t);
+; foo(t + d);
+define void @quaternary(i32 %a, i32 %b, i32 %c, i32 %d) {
+; CHECK-LABEL: @quaternary(
+  %1 = add i32 %a, %b
+  %2 = add i32 %1, %c
+  call void @foo(i32 %2)
+; CHECK: call void @foo(i32 [[TMP1:%[a-zA-Z0-9]]])
+  %3 = add i32 %a, %d
+  %4 = add i32 %3, %b
+  %5 = add i32 %4, %c
+; CHECK: [[TMP2:%[a-zA-Z0-9]]] = add i32 [[TMP1]], %d
+  call void @foo(i32 %5)
+; CHECK: call void @foo(i32 [[TMP2]]
+  ret void
+}
+
+define void @iterative(i32 %a, i32 %b, i32 %c) {
+  %ab = add i32 %a, %b
+  %abc = add i32 %ab, %c
+  call void @foo(i32 %abc)
+
+  %ab2 = add i32 %ab, %b
+  %ab2c = add i32 %ab2, %c
+; CHECK: %ab2c = add i32 %abc, %b
+  call void @foo(i32 %ab2c)
+; CHECK-NEXT: call void @foo(i32 %ab2c)
+
+  %ab3 = add i32 %ab2, %b
+  %ab3c = add i32 %ab3, %c
+; CHECK-NEXT: %ab3c = add i32 %ab2c, %b
+  call void @foo(i32 %ab3c)
+; CHECK-NEXT: call void @foo(i32 %ab3c)
+
+  ret void
+}
+
+define void @avoid_infinite_loop(i32 %a, i32 %b) {
+; CHECK-LABEL: @avoid_infinite_loop
+  %ab = add i32 %a, %b
+; CHECK-NEXT: %ab
+  %ab2 = add i32 %ab, %b
+; CHECK-NEXT: %ab2
+  call void @foo(i32 %ab2)
+; CHECK-NEXT: @foo(i32 %ab2)
+  ret void
+}
diff --git a/test/Transforms/ObjCARC/allocas.ll b/test/Transforms/ObjCARC/allocas.ll
index 7b671df70649..ac26a097d49d 100644
--- a/test/Transforms/ObjCARC/allocas.ll
+++ b/test/Transforms/ObjCARC/allocas.ll
@@ -56,7 +56,7 @@ entry:
   tail call i8* @objc_retain(i8* %x)
   tail call i8* @objc_retain(i8* %x)
   store i8* %x, i8** %A, align 8
-  %y = load i8** %A
+  %y = load i8*, i8** %A
   call void @use_alloca(i8** %A)
   call void @objc_release(i8* %y), !clang.imprecise_release !0
   call void @use_pointer(i8* %x)
@@ -74,11 +74,11 @@ entry:
 define void @test1b(i8* %x) {
 entry:
   %A = alloca i8*
-  %gep = getelementptr i8** %A, i32 0
+  %gep = getelementptr i8*, i8** %A, i32 0
   tail call i8* @objc_retain(i8* %x)
   tail call i8* @objc_retain(i8* %x)
   store i8* %x, i8** %gep, align 8
-  %y = load i8** %A
+  %y = load i8*, i8** %A
   call void @use_alloca(i8** %A)
   call void @objc_release(i8* %y), !clang.imprecise_release !0
   call void @use_pointer(i8* %x)
@@ -97,11 +97,11 @@ entry:
 define void @test1c(i8* %x) {
 entry:
   %A = alloca i8*, i32 3
-  %gep = getelementptr i8** %A, i32 2
+  %gep = getelementptr i8*, i8** %A, i32 2
   tail call i8* @objc_retain(i8* %x)
   tail call i8* @objc_retain(i8* %x)
   store i8* %x, i8** %gep, align 8
-  %y = load i8** %gep
+  %y = load i8*, i8** %gep
   call void @use_alloca(i8** %A)
   call void @objc_release(i8* %y), !clang.imprecise_release !0
   call void @use_pointer(i8* %x)
@@ -131,11 +131,11 @@ use_allocaB:
 
 exit:
   %A = phi i8** [ %allocaA, %use_allocaA ], [ %allocaB, %use_allocaB ]
-  %gep = getelementptr i8** %A, i32 0
+  %gep = getelementptr i8*, i8** %A, i32 0
   tail call i8* @objc_retain(i8* %x)
   tail call i8* @objc_retain(i8* %x)
   store i8* %x, i8** %gep, align 8
-  %y = load i8** %gep
+  %y = load i8*, i8** %gep
   call void @use_alloca(i8** %A)
   call void @objc_release(i8* %y), !clang.imprecise_release !0
   call void @use_pointer(i8* %x)
@@ -164,11 +164,11 @@ use_allocaB:
 
 exit:
   %A = phi i8** [ %allocaA, %use_allocaA ], [ %allocaB, %use_allocaB ]
-  %gep = getelementptr i8** %A, i32 2
+  %gep = getelementptr i8*, i8** %A, i32 2
   tail call i8* @objc_retain(i8* %x)
   tail call i8* @objc_retain(i8* %x)
   store i8* %x, i8** %gep, align 8
-  %y = load i8** %gep
+  %y = load i8*, i8** %gep
   call void @use_alloca(i8** %A)
   call void @objc_release(i8* %y), !clang.imprecise_release !0
   call void @use_pointer(i8* %x)
@@ -191,7 +191,7 @@ entry:
   tail call i8* @objc_retain(i8* %x)
   tail call i8* @objc_retain(i8* %x)
   store i8* %x, i8** %A, align 8
-  %y = load i8** %A
+  %y = load i8*, i8** %A
   call void @use_alloca(i8** %A)
   call void @objc_release(i8* %y), !clang.imprecise_release !0
   call void @use_pointer(i8* %x)
@@ -214,7 +214,7 @@ define void @test2a(i8* %x) {
 entry:
   %A = alloca i8*
   store i8* %x, i8** %A, align 8
-  %y = load i8** %A
+  %y = load i8*, i8** %A
   br label %bb1
 
 bb1:
@@ -243,10 +243,10 @@ bb3:
 define void @test2b(i8* %x) {
 entry:
   %A = alloca i8*
-  %gep1 = getelementptr i8** %A, i32 0
+  %gep1 = getelementptr i8*, i8** %A, i32 0
   store i8* %x, i8** %gep1, align 8
-  %gep2 = getelementptr i8** %A, i32 0
-  %y = load i8** %gep2
+  %gep2 = getelementptr i8*, i8** %A, i32 0
+  %y = load i8*, i8** %gep2
   br label %bb1
 
 bb1:
@@ -275,10 +275,10 @@ bb3:
 define void @test2c(i8* %x) {
 entry:
   %A = alloca i8*, i32 3
-  %gep1 = getelementptr i8** %A, i32 2
+  %gep1 = getelementptr i8*, i8** %A, i32 2
   store i8* %x, i8** %gep1, align 8
-  %gep2 = getelementptr i8** %A, i32 2
-  %y = load i8** %gep2
+  %gep2 = getelementptr i8*, i8** %A, i32 2
+  %y = load i8*, i8** %gep2
   tail call i8* @objc_retain(i8* %x)
   br label %bb1
 
@@ -311,18 +311,18 @@ entry:
 
 bb1:
   %Abb1 = alloca i8*, i32 3
-  %gepbb11 = getelementptr i8** %Abb1, i32 2
+  %gepbb11 = getelementptr i8*, i8** %Abb1, i32 2
   store i8* %x, i8** %gepbb11, align 8
-  %gepbb12 = getelementptr i8** %Abb1, i32 2
-  %ybb1 = load i8** %gepbb12
+  %gepbb12 = getelementptr i8*, i8** %Abb1, i32 2
+  %ybb1 = load i8*, i8** %gepbb12
   br label %bb3
 
 bb2:
   %Abb2 = alloca i8*, i32 4
-  %gepbb21 = getelementptr i8** %Abb2, i32 2
+  %gepbb21 = getelementptr i8*, i8** %Abb2, i32 2
   store i8* %x, i8** %gepbb21, align 8
-  %gepbb22 = getelementptr i8** %Abb2, i32 2
-  %ybb2 = load i8** %gepbb22
+  %gepbb22 = getelementptr i8*, i8** %Abb2, i32 2
+  %ybb2 = load i8*, i8** %gepbb22
   br label %bb3
 
 bb3:
@@ -369,44 +369,44 @@ entry:
   %call1 = call i8* @returner()
   %tmp0 = tail call i8* @objc_retainAutoreleasedReturnValue(i8* %call1)
 
-  %objs.begin = getelementptr inbounds [2 x i8*]* %objs, i64 0, i64 0
+  %objs.begin = getelementptr inbounds [2 x i8*], [2 x i8*]* %objs, i64 0, i64 0
   tail call i8* @objc_retain(i8* %call1)
   store i8* %call1, i8** %objs.begin, align 8
-  %objs.elt = getelementptr inbounds [2 x i8*]* %objs, i64 0, i64 1
+  %objs.elt = getelementptr inbounds [2 x i8*], [2 x i8*]* %objs, i64 0, i64 1
   tail call i8* @objc_retain(i8* %call1)
   store i8* %call1, i8** %objs.elt
 
   %call2 = call i8* @returner1()
   %call3 = call i8* @returner2()
-  %keys.begin = getelementptr inbounds [2 x i8*]* %keys, i64 0, i64 0
+  %keys.begin = getelementptr inbounds [2 x i8*], [2 x i8*]* %keys, i64 0, i64 0
   tail call i8* @objc_retain(i8* %call2)
   store i8* %call2, i8** %keys.begin, align 8
-  %keys.elt = getelementptr inbounds [2 x i8*]* %keys, i64 0, i64 1
+  %keys.elt = getelementptr inbounds [2 x i8*], [2 x i8*]* %keys, i64 0, i64 1
   tail call i8* @objc_retain(i8* %call3)
   store i8* %call3, i8** %keys.elt  
   
-  %gep = getelementptr inbounds [2 x i8*]* %objs, i64 0, i64 2
+  %gep = getelementptr inbounds [2 x i8*], [2 x i8*]* %objs, i64 0, i64 2
   br label %arraydestroy.body
 
 arraydestroy.body:
   %arraydestroy.elementPast = phi i8** [ %gep, %entry ], [ %arraydestroy.element, %arraydestroy.body ]
-  %arraydestroy.element = getelementptr inbounds i8** %arraydestroy.elementPast, i64 -1
-  %destroy_tmp = load i8** %arraydestroy.element, align 8
+  %arraydestroy.element = getelementptr inbounds i8*, i8** %arraydestroy.elementPast, i64 -1
+  %destroy_tmp = load i8*, i8** %arraydestroy.element, align 8
   call void @objc_release(i8* %destroy_tmp), !clang.imprecise_release !0
-  %objs_ptr = getelementptr inbounds [2 x i8*]* %objs, i64 0, i64 0
+  %objs_ptr = getelementptr inbounds [2 x i8*], [2 x i8*]* %objs, i64 0, i64 0
   %arraydestroy.cmp = icmp eq i8** %arraydestroy.element, %objs_ptr
   br i1 %arraydestroy.cmp, label %arraydestroy.done, label %arraydestroy.body
 
 arraydestroy.done:
-  %gep1 = getelementptr inbounds [2 x i8*]* %keys, i64 0, i64 2
+  %gep1 = getelementptr inbounds [2 x i8*], [2 x i8*]* %keys, i64 0, i64 2
   br label %arraydestroy.body1
 
 arraydestroy.body1:
   %arraydestroy.elementPast1 = phi i8** [ %gep1, %arraydestroy.done ], [ %arraydestroy.element1, %arraydestroy.body1 ]
-  %arraydestroy.element1 = getelementptr inbounds i8** %arraydestroy.elementPast1, i64 -1
-  %destroy_tmp1 = load i8** %arraydestroy.element1, align 8
+  %arraydestroy.element1 = getelementptr inbounds i8*, i8** %arraydestroy.elementPast1, i64 -1
+  %destroy_tmp1 = load i8*, i8** %arraydestroy.element1, align 8
   call void @objc_release(i8* %destroy_tmp1), !clang.imprecise_release !0
-  %keys_ptr = getelementptr inbounds [2 x i8*]* %keys, i64 0, i64 0
+  %keys_ptr = getelementptr inbounds [2 x i8*], [2 x i8*]* %keys, i64 0, i64 0
   %arraydestroy.cmp1 = icmp eq i8** %arraydestroy.element1, %keys_ptr
   br i1 %arraydestroy.cmp1, label %arraydestroy.done1, label %arraydestroy.body1
 
@@ -448,44 +448,44 @@ entry:
   %tmp0 = tail call i8* @objc_retainAutoreleasedReturnValue(i8* %call1)
   %tmp1 = tail call i8* @objc_retain(i8* %call1)
 
-  %objs.begin = getelementptr inbounds [2 x i8*]* %objs, i64 0, i64 0
+  %objs.begin = getelementptr inbounds [2 x i8*], [2 x i8*]* %objs, i64 0, i64 0
   tail call i8* @objc_retain(i8* %call1)
   store i8* %call1, i8** %objs.begin, align 8
-  %objs.elt = getelementptr inbounds [2 x i8*]* %objs, i64 0, i64 1
+  %objs.elt = getelementptr inbounds [2 x i8*], [2 x i8*]* %objs, i64 0, i64 1
   tail call i8* @objc_retain(i8* %call1)
   store i8* %call1, i8** %objs.elt
 
   %call2 = call i8* @returner1()
   %call3 = call i8* @returner2()
-  %keys.begin = getelementptr inbounds [2 x i8*]* %keys, i64 0, i64 0
+  %keys.begin = getelementptr inbounds [2 x i8*], [2 x i8*]* %keys, i64 0, i64 0
   tail call i8* @objc_retain(i8* %call2)
   store i8* %call2, i8** %keys.begin, align 8
-  %keys.elt = getelementptr inbounds [2 x i8*]* %keys, i64 0, i64 1
+  %keys.elt = getelementptr inbounds [2 x i8*], [2 x i8*]* %keys, i64 0, i64 1
   tail call i8* @objc_retain(i8* %call3)
   store i8* %call3, i8** %keys.elt  
   
-  %gep = getelementptr inbounds [2 x i8*]* %objs, i64 0, i64 2
+  %gep = getelementptr inbounds [2 x i8*], [2 x i8*]* %objs, i64 0, i64 2
   br label %arraydestroy.body
 
 arraydestroy.body:
   %arraydestroy.elementPast = phi i8** [ %gep, %entry ], [ %arraydestroy.element, %arraydestroy.body ]
-  %arraydestroy.element = getelementptr inbounds i8** %arraydestroy.elementPast, i64 -1
-  %destroy_tmp = load i8** %arraydestroy.element, align 8
+  %arraydestroy.element = getelementptr inbounds i8*, i8** %arraydestroy.elementPast, i64 -1
+  %destroy_tmp = load i8*, i8** %arraydestroy.element, align 8
   call void @objc_release(i8* %destroy_tmp), !clang.imprecise_release !0
-  %objs_ptr = getelementptr inbounds [2 x i8*]* %objs, i64 0, i64 0
+  %objs_ptr = getelementptr inbounds [2 x i8*], [2 x i8*]* %objs, i64 0, i64 0
   %arraydestroy.cmp = icmp eq i8** %arraydestroy.element, %objs_ptr
   br i1 %arraydestroy.cmp, label %arraydestroy.done, label %arraydestroy.body
 
 arraydestroy.done:
-  %gep1 = getelementptr inbounds [2 x i8*]* %keys, i64 0, i64 2
+  %gep1 = getelementptr inbounds [2 x i8*], [2 x i8*]* %keys, i64 0, i64 2
   br label %arraydestroy.body1
 
 arraydestroy.body1:
   %arraydestroy.elementPast1 = phi i8** [ %gep1, %arraydestroy.done ], [ %arraydestroy.element1, %arraydestroy.body1 ]
-  %arraydestroy.element1 = getelementptr inbounds i8** %arraydestroy.elementPast1, i64 -1
-  %destroy_tmp1 = load i8** %arraydestroy.element1, align 8
+  %arraydestroy.element1 = getelementptr inbounds i8*, i8** %arraydestroy.elementPast1, i64 -1
+  %destroy_tmp1 = load i8*, i8** %arraydestroy.element1, align 8
   call void @objc_release(i8* %destroy_tmp1), !clang.imprecise_release !0
-  %keys_ptr = getelementptr inbounds [2 x i8*]* %keys, i64 0, i64 0
+  %keys_ptr = getelementptr inbounds [2 x i8*], [2 x i8*]* %keys, i64 0, i64 0
   %arraydestroy.cmp1 = icmp eq i8** %arraydestroy.element1, %keys_ptr
   br i1 %arraydestroy.cmp1, label %arraydestroy.done1, label %arraydestroy.body1
 
diff --git a/test/Transforms/ObjCARC/arc-annotations.ll b/test/Transforms/ObjCARC/arc-annotations.ll
deleted file mode 100644
index c0ce44f284ca..000000000000
--- a/test/Transforms/ObjCARC/arc-annotations.ll
+++ /dev/null
@@ -1,83 +0,0 @@
-; This file consists of various tests which ensure that the objc-arc-annotations
-; are working correctly. In the future, I will use this in other lit tests to
-; check the data flow analysis of ARC.
-
-; REQUIRES: asserts
-; RUN: opt -S -objc-arc -enable-objc-arc-annotations < %s | FileCheck %s
-
-declare i8* @objc_retain(i8*)
-declare i8* @objc_retainAutoreleasedReturnValue(i8*)
-declare void @objc_release(i8*)
-declare i8* @objc_autorelease(i8*)
-declare i8* @objc_autoreleaseReturnValue(i8*)
-declare void @objc_autoreleasePoolPop(i8*)
-declare i8* @objc_autoreleasePoolPush()
-declare i8* @objc_retainBlock(i8*)
-
-declare i8* @objc_retainedObject(i8*)
-declare i8* @objc_unretainedObject(i8*)
-declare i8* @objc_unretainedPointer(i8*)
-
-declare void @use_pointer(i8*)
-declare void @callee()
-declare void @callee_fnptr(void ()*)
-declare void @invokee()
-declare i8* @returner()
-
-; Simple retain+release pair deletion, with some intervening control
-; flow and harmless instructions.
-
-; CHECK-LABEL: define void @test0(
-; CHECK: entry:
-; CHECK:   call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_None)
-; CHECK:   %0 = tail call i8* @objc_retain(i8* %a) #0, !llvm.arc.annotation.bottomup ![[ANN0:[0-9]+]], !llvm.arc.annotation.topdown ![[ANN1:[0-9]+]]
-; CHECK:   call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_Use)
-; CHECK:   call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_Retain)
-; CHECK: t:
-; CHECK:   call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_Retain)
-; CHECK:   call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_Use)
-; CHECK:   store float 2.000000e+00, float* %b, !llvm.arc.annotation.bottomup ![[ANN2:[0-9]+]]
-; CHECK:   call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_Release)
-; CHECK:   call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_Retain)
-; CHECK: f:
-; CHECK:   call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_Retain)
-; CHECK:   call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_Use)
-; CHECK:   store i32 7, i32* %x, !llvm.arc.annotation.bottomup ![[ANN2]]
-; CHECK:   call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_Release)
-; CHECK:   call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_Retain)
-; CHECK: return:
-; CHECK:   call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_Retain)
-; CHECK:   call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_Release)
-; CHECK:   call void @objc_release(i8* %c) #0, !llvm.arc.annotation.bottomup ![[ANN3:[0-9]+]], !llvm.arc.annotation.topdown ![[ANN4:[0-9]+]]
-; CHECK:   call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_None)
-; CHECK: }
-define void @test0(i32* %x, i1 %p) nounwind {
-entry:
-  %a = bitcast i32* %x to i8*
-  %0 = call i8* @objc_retain(i8* %a) nounwind
-  br i1 %p, label %t, label %f
-
-t:
-  store i8 3, i8* %a
-  %b = bitcast i32* %x to float*
-  store float 2.0, float* %b
-  br label %return
-
-f:
-  store i32 7, i32* %x
-  br label %return
-
-return:
-  %c = bitcast i32* %x to i8*
-  call void @objc_release(i8* %c) nounwind
-  ret void
-}
-
-!0 = !{}
-
-; CHECK: ![[ANN0]] = !{!"(test0,%x)", !"S_Use", !"S_None"}
-; CHECK: ![[ANN1]] = !{!"(test0,%x)", !"S_None", !"S_Retain"}
-; CHECK: ![[ANN2]] = !{!"(test0,%x)", !"S_Release", !"S_Use"}
-; CHECK: ![[ANN3]] = !{!"(test0,%x)", !"S_None", !"S_Release"}
-; CHECK: ![[ANN4]] = !{!"(test0,%x)", !"S_Retain", !"S_None"}
-
diff --git a/test/Transforms/ObjCARC/basic.ll b/test/Transforms/ObjCARC/basic.ll
index 7bc58c42d532..ff6c69cd9ed0 100644
--- a/test/Transforms/ObjCARC/basic.ll
+++ b/test/Transforms/ObjCARC/basic.ll
@@ -286,7 +286,7 @@ entry:
 loop:
   %c = bitcast i32* %x to i8*
   call void @objc_release(i8* %c) nounwind
-  %j = load volatile i1* %q
+  %j = load volatile i1, i1* %q
   br i1 %j, label %loop, label %return
 
 return:
@@ -306,7 +306,7 @@ entry:
 loop:
   %c = bitcast i32* %x to i8*
   call void @objc_release(i8* %c) nounwind, !clang.imprecise_release !0
-  %j = load volatile i1* %q
+  %j = load volatile i1, i1* %q
   br i1 %j, label %loop, label %return
 
 return:
@@ -330,7 +330,7 @@ entry:
 loop:
   %a = bitcast i32* %x to i8*
   %0 = call i8* @objc_retain(i8* %a) nounwind
-  %j = load volatile i1* %q
+  %j = load volatile i1, i1* %q
   br i1 %j, label %loop, label %return
 
 return:
@@ -350,7 +350,7 @@ entry:
 loop:
   %a = bitcast i32* %x to i8*
   %0 = call i8* @objc_retain(i8* %a) nounwind
-  %j = load volatile i1* %q
+  %j = load volatile i1, i1* %q
   br i1 %j, label %loop, label %return
 
 return:
@@ -900,13 +900,14 @@ entry:
   ret i8* %x
 }
 
-; Trivial retain,release pair with intervening call, but it's dominated
-; by another retain - delete!
+; We can not delete this retain, release since we do not have a post-dominating
+; use of the release.
 
 ; CHECK-LABEL: define void @test12(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: @objc_retain(i8* %x)
-; CHECK-NOT: @objc_
+; CHECK-NEXT: @objc_retain
+; CHECK: @objc_release
 ; CHECK: }
 define void @test12(i8* %x, i64 %n) {
 entry:
@@ -942,6 +943,8 @@ entry:
 ; CHECK-NEXT: @objc_retain(i8* %x)
 ; CHECK-NEXT: @use_pointer
 ; CHECK-NEXT: @use_pointer
+; CHECK-NEXT: @use_pointer
+; CHECK-NEXT: @objc_release
 ; CHECK-NEXT: ret void
 ; CHECK-NEXT: }
 define void @test13b(i8* %x, i64 %n) {
@@ -951,6 +954,8 @@ entry:
   call void @use_pointer(i8* %x)
   call void @use_pointer(i8* %x)
   call void @objc_release(i8* %x) nounwind
+  call void @use_pointer(i8* %x)
+  call void @objc_release(i8* %x) nounwind
   ret void
 }
 
@@ -984,6 +989,8 @@ entry:
 ; CHECK-NEXT: @objc_autoreleasePoolPush
 ; CHECK-NEXT: @use_pointer
 ; CHECK-NEXT: @use_pointer
+; CHECK-NEXT: @use_pointer
+; CHECK-NEXT: @objc_release
 ; CHECK-NEXT: ret void
 ; CHECK-NEXT: }
 define void @test13d(i8* %x, i64 %n) {
@@ -994,17 +1001,22 @@ entry:
   call void @use_pointer(i8* %x)
   call void @use_pointer(i8* %x)
   call void @objc_release(i8* %x) nounwind
+  call void @use_pointer(i8* %x)
+  call void @objc_release(i8* %x) nounwind
   ret void
 }
 
-; Trivial retain,release pair with intervening call, but it's post-dominated
-; by another release - delete!
+; Trivial retain,release pair with intervening call, and it's post-dominated by
+; another release. But it is not known safe in the top down direction. We can
+; not eliminate it.
 
 ; CHECK-LABEL: define void @test14(
 ; CHECK-NEXT: entry:
+; CHECK-NEXT: @objc_retain
 ; CHECK-NEXT: @use_pointer
 ; CHECK-NEXT: @use_pointer
 ; CHECK-NEXT: @objc_release
+; CHECK-NEXT: @objc_release
 ; CHECK-NEXT: ret void
 ; CHECK-NEXT: }
 define void @test14(i8* %x, i64 %n) {
@@ -1073,6 +1085,9 @@ entry:
 ; CHECK-LABEL: define void @test16a(
 ; CHECK: @objc_retain(i8* %x)
 ; CHECK-NOT: @objc
+; CHECK: purple:
+; CHECK: @use_pointer
+; CHECK: @objc_release
 ; CHECK: }
 define void @test16a(i1 %a, i1 %b, i8* %x) {
 entry:
@@ -1101,12 +1116,18 @@ blue:
   br label %purple
 
 purple:
+  call void @use_pointer(i8* %x)
+  call void @objc_release(i8* %x) nounwind
   ret void
 }
 
 ; CHECK-LABEL: define void @test16b(
 ; CHECK: @objc_retain(i8* %x)
 ; CHECK-NOT: @objc
+; CHECK: purple:
+; CHECK-NEXT: @use_pointer
+; CHECK-NEXT: @use_pointer
+; CHECK-NEXT: @objc_release
 ; CHECK: }
 define void @test16b(i1 %a, i1 %b, i8* %x) {
 entry:
@@ -1135,12 +1156,18 @@ blue:
   br label %purple
 
 purple:
+  call void @use_pointer(i8* %x)
+  call void @use_pointer(i8* %x)
+  call void @objc_release(i8* %x) nounwind
   ret void
 }
 
 ; CHECK-LABEL: define void @test16c(
 ; CHECK: @objc_retain(i8* %x)
 ; CHECK-NOT: @objc
+; CHECK: purple:
+; CHECK: @use_pointer
+; CHECK: @objc_release
 ; CHECK: }
 define void @test16c(i1 %a, i1 %b, i8* %x) {
 entry:
@@ -1169,12 +1196,14 @@ blue:
   br label %purple
 
 purple:
+  call void @use_pointer(i8* %x)
+  call void @objc_release(i8* %x) nounwind, !clang.imprecise_release !0
   ret void
 }
 
 ; CHECK-LABEL: define void @test16d(
 ; CHECK: @objc_retain(i8* %x)
-; CHECK-NOT: @objc
+; CHECK: @objc
 ; CHECK: }
 define void @test16d(i1 %a, i1 %b, i8* %x) {
 entry:
@@ -1206,44 +1235,6 @@ purple:
   ret void
 }
 
-
-; Retain+release pairs in diamonds, all post-dominated by a release.
-
-; CHECK-LABEL: define void @test17(
-; CHECK-NOT: @objc_
-; CHECK: purple:
-; CHECK: @objc_release
-; CHECK: }
-define void @test17(i1 %a, i1 %b, i8* %x) {
-entry:
-  br i1 %a, label %red, label %orange
-
-red:
-  call i8* @objc_retain(i8* %x) nounwind
-  br label %yellow
-
-orange:
-  call i8* @objc_retain(i8* %x) nounwind
-  br label %yellow
-
-yellow:
-  call void @use_pointer(i8* %x)
-  call void @use_pointer(i8* %x)
-  br i1 %b, label %green, label %blue
-
-green:
-  call void @objc_release(i8* %x) nounwind
-  br label %purple
-
-blue:
-  call void @objc_release(i8* %x) nounwind
-  br label %purple
-
-purple:
-  call void @objc_release(i8* %x) nounwind
-  ret void
-}
-
 ; Delete no-ops.
 
 ; CHECK-LABEL: define void @test18(
@@ -1366,7 +1357,7 @@ C:
 define void @test24(i8* %r, i8* %a) {
   call i8* @objc_retain(i8* %a)
   call void @use_pointer(i8* %r)
-  %q = load i8* %a
+  %q = load i8, i8* %a
   call void @objc_release(i8* %a)
   ret void
 }
@@ -1659,7 +1650,7 @@ true:
 
 done:
   %g = bitcast i8* %p to i8*
-  %h = getelementptr i8* %g, i64 0
+  %h = getelementptr i8, i8* %g, i64 0
   call void @objc_release(i8* %g)
   ret void
 }
@@ -1688,7 +1679,7 @@ true:
 
 done:
   %g = bitcast i8* %p to i8*
-  %h = getelementptr i8* %g, i64 0
+  %h = getelementptr i8, i8* %g, i64 0
   call void @objc_release(i8* %g)
   ret void
 }
@@ -1713,7 +1704,7 @@ true:
 
 done:
   %g = bitcast i8* %p to i8*
-  %h = getelementptr i8* %g, i64 0
+  %h = getelementptr i8, i8* %g, i64 0
   call void @objc_release(i8* %g)
   ret void
 }
@@ -1732,7 +1723,7 @@ true:
 
 done:
   %g = bitcast i8* %p to i8*
-  %h = getelementptr i8* %g, i64 0
+  %h = getelementptr i8, i8* %g, i64 0
   call void @objc_release(i8* %g), !clang.imprecise_release !0
   ret void
 }
@@ -1760,7 +1751,7 @@ true:
 
 done:
   %g = bitcast i8* %p to i8*
-  %h = getelementptr i8* %g, i64 0
+  %h = getelementptr i8, i8* %g, i64 0
   call void @objc_release(i8* %g)
   ret void
 }
@@ -1780,7 +1771,7 @@ true:
 
 done:
   %g = bitcast i8* %p to i8*
-  %h = getelementptr i8* %g, i64 0
+  %h = getelementptr i8, i8* %g, i64 0
   call void @objc_release(i8* %g), !clang.imprecise_release !0
   ret void
 }
@@ -1936,6 +1927,9 @@ exit:                                             ; preds = %loop
 ; CHECK-NEXT: call i8* @objc_autorelease(i8* %p)
 ; CHECK-NEXT: call void @use_pointer(i8* %p)
 ; CHECK-NEXT: call void @use_pointer(i8* %p)
+; CHECK-NEXT: call void @use_pointer(i8* %p)
+; CHECK-NEXT: call void @use_pointer(i8* %p)
+; CHECK-NEXT: call void @objc_release(i8* %p)
 ; CHECK-NEXT: ret void
 ; CHECK-NEXT: }
 define void @test42(i8* %p) {
@@ -1946,6 +1940,9 @@ entry:
   call void @use_pointer(i8* %p)
   call void @use_pointer(i8* %p)
   call void @objc_release(i8* %p)
+  call void @use_pointer(i8* %p)
+  call void @use_pointer(i8* %p)
+  call void @objc_release(i8* %p)
   ret void
 }
 
@@ -1985,6 +1982,8 @@ entry:
 ; CHECK-NEXT: call void @use_pointer(i8* %p)
 ; CHECK-NEXT: call void @use_pointer(i8* %p)
 ; CHECK-NEXT: call i8* @objc_autoreleasePoolPush()
+; CHECK-NEXT: call void @use_pointer(i8* %p)
+; CHECK-NEXT: call void @objc_release
 ; CHECK-NEXT: ret void
 ; CHECK-NEXT: }
 define void @test43b(i8* %p) {
@@ -1996,6 +1995,8 @@ entry:
   call void @use_pointer(i8* %p)
   call i8* @objc_autoreleasePoolPush()
   call void @objc_release(i8* %p)
+  call void @use_pointer(i8* %p)
+  call void @objc_release(i8* %p)
   ret void
 }
 
@@ -2005,7 +2006,7 @@ entry:
 ; CHECK-NOT: objc_
 ; CHECK: }
 define void @test44(i8** %pp) {
-  %p = load i8** %pp
+  %p = load i8*, i8** %pp
   %q = call i8* @objc_retain(i8* %p)
   call void @objc_release(i8* %q)
   ret void
@@ -2021,8 +2022,8 @@ define void @test44(i8** %pp) {
 ; CHECK: call void @objc_release(i8* %p)
 ; CHECK: }
 define void @test45(i8** %pp, i8** %qq) {
-  %p = load i8** %pp
-  %q = load i8** %qq
+  %p = load i8*, i8** %pp
+  %q = load i8*, i8** %qq
   call i8* @objc_retain(i8* %p)
   call void @objc_release(i8* %q)
   call void @use_pointer(i8* %p)
@@ -2154,10 +2155,10 @@ define void @test51b(i8* %p) {
 ; CHECK: ret void
 ; CHECK: }
 define void @test52a(i8** %zz, i8** %pp) {
-  %p = load i8** %pp
+  %p = load i8*, i8** %pp
   %1 = call i8* @objc_retain(i8* %p)
   call void @callee()
-  %z = load i8** %zz
+  %z = load i8*, i8** %zz
   call void @use_pointer(i8* %z)
   call void @objc_release(i8* %p)
   ret void
@@ -2171,10 +2172,10 @@ define void @test52a(i8** %zz, i8** %pp) {
 ; CHECK: ret void
 ; CHECK: }
 define void @test52b(i8** %zz, i8** %pp) {
-  %p = load i8** %pp
+  %p = load i8*, i8** %pp
   %1 = call i8* @objc_retain(i8* %p)
   call void @callee()
-  %z = load i8** %zz
+  %z = load i8*, i8** %zz
   call void @use_pointer(i8* %z)
   call void @objc_release(i8* %p), !clang.imprecise_release !0
   ret void
@@ -2189,10 +2190,10 @@ define void @test52b(i8** %zz, i8** %pp) {
 ; CHECK: @objc_
 ; CHECK: }
 define void @test53(void ()** %zz, i8** %pp) {
-  %p = load i8** %pp
+  %p = load i8*, i8** %pp
   %1 = call i8* @objc_retain(i8* %p)
   call void @callee()
-  %z = load void ()** %zz
+  %z = load void ()*, void ()** %zz
   call void @callee_fnptr(void ()* %z)
   call void @objc_release(i8* %p)
   ret void
@@ -2260,15 +2261,16 @@ if.end:                                           ; preds = %entry, %if.then
   ret void
 }
 
-; When there are adjacent retain+release pairs, the first one is
-; known unnecessary because the presence of the second one means that
-; the first one won't be deleting the object.
+; When there are adjacent retain+release pairs, the first one is known
+; unnecessary because the presence of the second one means that the first one
+; won't be deleting the object.
 
 ; CHECK-LABEL:      define void @test57(
 ; CHECK-NEXT: entry:
+; CHECK-NEXT:   tail call i8* @objc_retain(i8* %x) [[NUW]]
 ; CHECK-NEXT:   call void @use_pointer(i8* %x)
 ; CHECK-NEXT:   call void @use_pointer(i8* %x)
-; CHECK-NEXT:   %0 = tail call i8* @objc_retain(i8* %x) [[NUW]]
+; CHECK-NEXT:   tail call i8* @objc_retain(i8* %x) [[NUW]]
 ; CHECK-NEXT:   call void @use_pointer(i8* %x)
 ; CHECK-NEXT:   call void @use_pointer(i8* %x)
 ; CHECK-NEXT:   call void @objc_release(i8* %x) [[NUW]]
@@ -2277,6 +2279,7 @@ if.end:                                           ; preds = %entry, %if.then
 define void @test57(i8* %x) nounwind {
 entry:
   call i8* @objc_retain(i8* %x) nounwind
+  call i8* @objc_retain(i8* %x) nounwind
   call void @use_pointer(i8* %x)
   call void @use_pointer(i8* %x)
   call void @objc_release(i8* %x) nounwind
@@ -2292,6 +2295,7 @@ entry:
 
 ; CHECK-LABEL:      define void @test58(
 ; CHECK-NEXT: entry:
+; CHECK-NEXT:   @objc_retain
 ; CHECK-NEXT:   call void @use_pointer(i8* %x)
 ; CHECK-NEXT:   call void @use_pointer(i8* %x)
 ; CHECK-NEXT:   ret void
@@ -2299,6 +2303,7 @@ entry:
 define void @test58(i8* %x) nounwind {
 entry:
   call i8* @objc_retain(i8* %x) nounwind
+  call i8* @objc_retain(i8* %x) nounwind
   call void @use_pointer(i8* %x)
   call void @use_pointer(i8* %x)
   call void @objc_release(i8* %x) nounwind
@@ -2341,8 +2346,8 @@ entry:
 ; CHECK: call void @objc_release
 ; CHECK: }
 define void @test60a() {
-  %t = load i8** @constptr
-  %s = load i8** @something
+  %t = load i8*, i8** @constptr
+  %s = load i8*, i8** @something
   call i8* @objc_retain(i8* %s)
   call void @callee()
   call void @use_pointer(i8* %t)
@@ -2353,16 +2358,16 @@ define void @test60a() {
 ; CHECK-LABEL: define void @test60b(
 ; CHECK: call i8* @objc_retain
 ; CHECK-NOT: call i8* @objc_retain
-; CHECK-NOT: call i8* @objc_rrelease
+; CHECK-NOT: call i8* @objc_release
 ; CHECK: }
 define void @test60b() {
-  %t = load i8** @constptr
-  %s = load i8** @something
-  call i8* @objc_retain(i8* %s)
-  call i8* @objc_retain(i8* %s)
+  %t = load i8*, i8** @constptr
+  %s = load i8*, i8** @something
+  call i8* @objc_retain(i8* %t)
+  call i8* @objc_retain(i8* %t)
   call void @callee()
-  call void @use_pointer(i8* %t)
-  call void @objc_release(i8* %s)
+  call void @use_pointer(i8* %s)
+  call void @objc_release(i8* %t)
   ret void
 }
 
@@ -2370,12 +2375,12 @@ define void @test60b() {
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test60c() {
-  %t = load i8** @constptr
-  %s = load i8** @something
-  call i8* @objc_retain(i8* %s)
+  %t = load i8*, i8** @constptr
+  %s = load i8*, i8** @something
+  call i8* @objc_retain(i8* %t)
   call void @callee()
-  call void @use_pointer(i8* %t)
-  call void @objc_release(i8* %s), !clang.imprecise_release !0
+  call void @use_pointer(i8* %s)
+  call void @objc_release(i8* %t), !clang.imprecise_release !0
   ret void
 }
 
@@ -2383,8 +2388,8 @@ define void @test60c() {
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test60d() {
-  %t = load i8** @constptr
-  %s = load i8** @something
+  %t = load i8*, i8** @constptr
+  %s = load i8*, i8** @something
   call i8* @objc_retain(i8* %t)
   call void @callee()
   call void @use_pointer(i8* %s)
@@ -2396,8 +2401,8 @@ define void @test60d() {
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test60e() {
-  %t = load i8** @constptr
-  %s = load i8** @something
+  %t = load i8*, i8** @constptr
+  %s = load i8*, i8** @something
   call i8* @objc_retain(i8* %t)
   call void @callee()
   call void @use_pointer(i8* %s)
@@ -2412,7 +2417,7 @@ define void @test60e() {
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test61() {
-  %t = load i8** @constptr
+  %t = load i8*, i8** @constptr
   call i8* @objc_retain(i8* %t)
   call void @callee()
   call void @use_pointer(i8* %t)
@@ -2432,7 +2437,7 @@ entry:
 
 loop:
   call i8* @objc_retain(i8* %x)
-  %q = load i1* %p
+  %q = load i1, i1* %p
   br i1 %q, label %loop.more, label %exit
 
 loop.more:
@@ -2459,7 +2464,7 @@ entry:
 
 loop:
   call i8* @objc_retain(i8* %x)
-  %q = load i1* %p
+  %q = load i1, i1* %p
   br i1 %q, label %loop.more, label %exit
 
 loop.more:
@@ -2485,7 +2490,7 @@ entry:
 
 loop:
   call i8* @objc_retain(i8* %x)
-  %q = load i1* %p
+  %q = load i1, i1* %p
   br i1 %q, label %loop.more, label %exit
 
 loop.more:
@@ -2679,33 +2684,33 @@ define {<2 x float>, <2 x float>} @"\01-[A z]"({}* %self, i8* nocapture %_cmd) n
 invoke.cont:
   %0 = bitcast {}* %self to i8*
   %1 = tail call i8* @objc_retain(i8* %0) nounwind
-  tail call void @llvm.dbg.value(metadata {}* %self, i64 0, metadata !0, metadata !{})
-  tail call void @llvm.dbg.value(metadata {}* %self, i64 0, metadata !0, metadata !{})
-  %ivar = load i64* @"OBJC_IVAR_$_A.myZ", align 8
-  %add.ptr = getelementptr i8* %0, i64 %ivar
+  tail call void @llvm.dbg.value(metadata {}* %self, i64 0, metadata !DILocalVariable(tag: DW_TAG_auto_variable, scope: !2), metadata !DIExpression()), !dbg !DILocation(scope: !2)
+  tail call void @llvm.dbg.value(metadata {}* %self, i64 0, metadata !DILocalVariable(tag: DW_TAG_auto_variable, scope: !2), metadata !DIExpression()), !dbg !DILocation(scope: !2)
+  %ivar = load i64, i64* @"OBJC_IVAR_$_A.myZ", align 8
+  %add.ptr = getelementptr i8, i8* %0, i64 %ivar
   %tmp1 = bitcast i8* %add.ptr to float*
-  %tmp2 = load float* %tmp1, align 4
+  %tmp2 = load float, float* %tmp1, align 4
   %conv = fpext float %tmp2 to double
   %add.ptr.sum = add i64 %ivar, 4
-  %tmp6 = getelementptr inbounds i8* %0, i64 %add.ptr.sum
+  %tmp6 = getelementptr inbounds i8, i8* %0, i64 %add.ptr.sum
   %2 = bitcast i8* %tmp6 to float*
-  %tmp7 = load float* %2, align 4
+  %tmp7 = load float, float* %2, align 4
   %conv8 = fpext float %tmp7 to double
   %add.ptr.sum36 = add i64 %ivar, 8
-  %tmp12 = getelementptr inbounds i8* %0, i64 %add.ptr.sum36
+  %tmp12 = getelementptr inbounds i8, i8* %0, i64 %add.ptr.sum36
   %arrayidx = bitcast i8* %tmp12 to float*
-  %tmp13 = load float* %arrayidx, align 4
+  %tmp13 = load float, float* %arrayidx, align 4
   %conv14 = fpext float %tmp13 to double
   %tmp12.sum = add i64 %ivar, 12
-  %arrayidx19 = getelementptr inbounds i8* %0, i64 %tmp12.sum
+  %arrayidx19 = getelementptr inbounds i8, i8* %0, i64 %tmp12.sum
   %3 = bitcast i8* %arrayidx19 to float*
-  %tmp20 = load float* %3, align 4
+  %tmp20 = load float, float* %3, align 4
   %conv21 = fpext float %tmp20 to double
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([33 x i8]* @.str4, i64 0, i64 0), double %conv, double %conv8, double %conv14, double %conv21)
-  %ivar23 = load i64* @"OBJC_IVAR_$_A.myZ", align 8
-  %add.ptr24 = getelementptr i8* %0, i64 %ivar23
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([33 x i8], [33 x i8]* @.str4, i64 0, i64 0), double %conv, double %conv8, double %conv14, double %conv21)
+  %ivar23 = load i64, i64* @"OBJC_IVAR_$_A.myZ", align 8
+  %add.ptr24 = getelementptr i8, i8* %0, i64 %ivar23
   %4 = bitcast i8* %add.ptr24 to i128*
-  %srcval = load i128* %4, align 4
+  %srcval = load i128, i128* %4, align 4
   tail call void @objc_release(i8* %0) nounwind
   %tmp29 = trunc i128 %srcval to i64
   %tmp30 = bitcast i64 %tmp29 to <2 x float>
@@ -2725,14 +2730,14 @@ define i32 @"\01-[Top0 _getX]"({}* %self, i8* nocapture %_cmd) nounwind {
 invoke.cont:
   %0 = bitcast {}* %self to i8*
   %1 = tail call i8* @objc_retain(i8* %0) nounwind
-  %puts = tail call i32 @puts(i8* getelementptr inbounds ([16 x i8]* @str, i64 0, i64 0))
+  %puts = tail call i32 @puts(i8* getelementptr inbounds ([16 x i8], [16 x i8]* @str, i64 0, i64 0))
   tail call void @objc_release(i8* %0) nounwind
   ret i32 0
 }
 
-@"\01L_OBJC_METH_VAR_NAME_" = internal global [5 x i8] c"frob\00", section "__TEXT,__cstring,cstring_literals", align 1@"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([5 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i64 0, i64 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
+@"\01L_OBJC_METH_VAR_NAME_" = internal global [5 x i8] c"frob\00", section "__TEXT,__cstring,cstring_literals", align 1@"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([5 x i8], [5 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i64 0, i64 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
 @"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] [i32 0, i32 16], section "__DATA, __objc_imageinfo, regular, no_dead_strip"
-@llvm.used = appending global [3 x i8*] [i8* getelementptr inbounds ([5 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*)], section "llvm.metadata"
+@llvm.used = appending global [3 x i8*] [i8* getelementptr inbounds ([5 x i8], [5 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*)], section "llvm.metadata"
 
 ; A simple loop. Eliminate the retain and release inside of it!
 
@@ -2752,8 +2757,8 @@ entry:
 for.body:                                         ; preds = %entry, %for.body
   %i.010 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
   %1 = tail call i8* @objc_retain(i8* %x) nounwind
-  %tmp5 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
-  %call = tail call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %1, i8* %tmp5)
+  %tmp5 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %call = tail call i8* (i8*, i8*, ...) @objc_msgSend(i8* %1, i8* %tmp5)
   tail call void @objc_release(i8* %1) nounwind, !clang.imprecise_release !0
   %inc = add nsw i64 %i.010, 1
   %exitcond = icmp eq i64 %inc, %n
@@ -2828,21 +2833,21 @@ entry:
   %tmp7 = bitcast %2* %self to i8*
   %tmp8 = call i8* @objc_retain(i8* %tmp7) nounwind
   store %4* null, %4** %err, align 8
-  %tmp1 = load %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_17", align 8
-  %tmp2 = load %struct.__CFString** @kUTTypePlainText, align 8
-  %tmp3 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_19", align 8
+  %tmp1 = load %struct._class_t*, %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_17", align 8
+  %tmp2 = load %struct.__CFString*, %struct.__CFString** @kUTTypePlainText, align 8
+  %tmp3 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_19", align 8
   %tmp4 = bitcast %struct._class_t* %tmp1 to i8*
-  %call5 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %tmp4, i8* %tmp3, %struct.__CFString* %tmp2)
-  %tmp5 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_21", align 8
+  %call5 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %tmp4, i8* %tmp3, %struct.__CFString* %tmp2)
+  %tmp5 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_21", align 8
   %tmp6 = bitcast %3* %pboard to i8*
-  %call76 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %tmp6, i8* %tmp5, i8* %call5)
+  %call76 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %tmp6, i8* %tmp5, i8* %call5)
   %tmp9 = call i8* @objc_retain(i8* %call76) nounwind
   %tobool = icmp eq i8* %tmp9, null
   br i1 %tobool, label %end, label %land.lhs.true
 
 land.lhs.true:                                    ; preds = %entry
-  %tmp11 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_23", align 8
-  %call137 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %tmp6, i8* %tmp11, i8* %tmp9)
+  %tmp11 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_23", align 8
+  %call137 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %tmp6, i8* %tmp11, i8* %tmp9)
   %tmp = bitcast i8* %call137 to %1*
   %tmp10 = call i8* @objc_retain(i8* %call137) nounwind
   call void @objc_release(i8* null) nounwind
@@ -2852,16 +2857,16 @@ land.lhs.true:                                    ; preds = %entry
   br i1 %tobool16, label %end, label %if.then
 
 if.then:                                          ; preds = %land.lhs.true
-  %tmp19 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_25", align 8
+  %tmp19 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_25", align 8
   %call21 = call signext i8 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8 (i8*, i8*)*)(i8* %call137, i8* %tmp19)
   %tobool22 = icmp eq i8 %call21, 0
   br i1 %tobool22, label %if.then44, label %land.lhs.true23
 
 land.lhs.true23:                                  ; preds = %if.then
-  %tmp24 = load %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_26", align 8
-  %tmp26 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_28", align 8
+  %tmp24 = load %struct._class_t*, %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_26", align 8
+  %tmp26 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_28", align 8
   %tmp27 = bitcast %struct._class_t* %tmp24 to i8*
-  %call2822 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %tmp27, i8* %tmp26, i8* %call137)
+  %call2822 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %tmp27, i8* %tmp26, i8* %call137)
   %tmp13 = bitcast i8* %call2822 to %5*
   %tmp14 = call i8* @objc_retain(i8* %call2822) nounwind
   call void @objc_release(i8* null) nounwind
@@ -2869,39 +2874,39 @@ land.lhs.true23:                                  ; preds = %if.then
   br i1 %tobool30, label %if.then44, label %if.end
 
 if.end:                                           ; preds = %land.lhs.true23
-  %tmp32 = load %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_29", align 8
-  %tmp33 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_31", align 8
+  %tmp32 = load %struct._class_t*, %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_29", align 8
+  %tmp33 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_31", align 8
   %tmp34 = bitcast %struct._class_t* %tmp32 to i8*
-  %call35 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %tmp34, i8* %tmp33)
-  %tmp37 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_33", align 8
-  %call3923 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %call35, i8* %tmp37, i8* %call2822, i32 signext 1, %4** %err)
+  %call35 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %tmp34, i8* %tmp33)
+  %tmp37 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_33", align 8
+  %call3923 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %call35, i8* %tmp37, i8* %call2822, i32 signext 1, %4** %err)
   %cmp = icmp eq i8* %call3923, null
   br i1 %cmp, label %if.then44, label %end
 
 if.then44:                                        ; preds = %if.end, %land.lhs.true23, %if.then
   %url.025 = phi %5* [ %tmp13, %if.end ], [ %tmp13, %land.lhs.true23 ], [ null, %if.then ]
-  %tmp49 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_35", align 8
+  %tmp49 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_35", align 8
   %call51 = call %struct._NSRange bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %struct._NSRange (i8*, i8*, i64, i64)*)(i8* %call137, i8* %tmp49, i64 0, i64 0)
   %call513 = extractvalue %struct._NSRange %call51, 0
   %call514 = extractvalue %struct._NSRange %call51, 1
-  %tmp52 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_37", align 8
-  %call548 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %call137, i8* %tmp52, i64 %call513, i64 %call514)
-  %tmp55 = load %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_38", align 8
-  %tmp56 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_40", align 8
+  %tmp52 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_37", align 8
+  %call548 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %call137, i8* %tmp52, i64 %call513, i64 %call514)
+  %tmp55 = load %struct._class_t*, %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_38", align 8
+  %tmp56 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_40", align 8
   %tmp57 = bitcast %struct._class_t* %tmp55 to i8*
-  %call58 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %tmp57, i8* %tmp56)
-  %tmp59 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_42", align 8
-  %call6110 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %call548, i8* %tmp59, i8* %call58)
+  %call58 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %tmp57, i8* %tmp56)
+  %tmp59 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_42", align 8
+  %call6110 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %call548, i8* %tmp59, i8* %call58)
   %tmp15 = call i8* @objc_retain(i8* %call6110) nounwind
   call void @objc_release(i8* %call137) nounwind
-  %tmp64 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_46", align 8
+  %tmp64 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_46", align 8
   %call66 = call signext i8 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8 (i8*, i8*, %1*)*)(i8* %call6110, i8* %tmp64, %1* bitcast (%struct.NSConstantString* @_unnamed_cfstring_44 to %1*))
   %tobool67 = icmp eq i8 %call66, 0
   br i1 %tobool67, label %if.end74, label %if.then68
 
 if.then68:                                        ; preds = %if.then44
-  %tmp70 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_48", align 8
-  %call7220 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %call6110, i8* %tmp70)
+  %tmp70 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_48", align 8
+  %call7220 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %call6110, i8* %tmp70)
   %tmp16 = call i8* @objc_retain(i8* %call7220) nounwind
   call void @objc_release(i8* %call6110) nounwind
   br label %if.end74
@@ -2909,54 +2914,54 @@ if.then68:                                        ; preds = %if.then44
 if.end74:                                         ; preds = %if.then68, %if.then44
   %filename.0.in = phi i8* [ %call7220, %if.then68 ], [ %call6110, %if.then44 ]
   %filename.0 = bitcast i8* %filename.0.in to %1*
-  %tmp17 = load i8** bitcast (%0* @"\01l_objc_msgSend_fixup_isEqual_" to i8**), align 16
+  %tmp17 = load i8*, i8** bitcast (%0* @"\01l_objc_msgSend_fixup_isEqual_" to i8**), align 16
   %tmp18 = bitcast i8* %tmp17 to i8 (i8*, %struct._message_ref_t*, i8*, ...)*
-  %call78 = call signext i8 (i8*, %struct._message_ref_t*, i8*, ...)* %tmp18(i8* %call137, %struct._message_ref_t* bitcast (%0* @"\01l_objc_msgSend_fixup_isEqual_" to %struct._message_ref_t*), i8* %filename.0.in)
+  %call78 = call signext i8 (i8*, %struct._message_ref_t*, i8*, ...) %tmp18(i8* %call137, %struct._message_ref_t* bitcast (%0* @"\01l_objc_msgSend_fixup_isEqual_" to %struct._message_ref_t*), i8* %filename.0.in)
   %tobool79 = icmp eq i8 %call78, 0
   br i1 %tobool79, label %land.lhs.true80, label %if.then109
 
 land.lhs.true80:                                  ; preds = %if.end74
-  %tmp82 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_25", align 8
+  %tmp82 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_25", align 8
   %call84 = call signext i8 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8 (i8*, i8*)*)(i8* %filename.0.in, i8* %tmp82)
   %tobool86 = icmp eq i8 %call84, 0
   br i1 %tobool86, label %if.then109, label %if.end106
 
 if.end106:                                        ; preds = %land.lhs.true80
-  %tmp88 = load %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_26", align 8
-  %tmp90 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_28", align 8
+  %tmp88 = load %struct._class_t*, %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_26", align 8
+  %tmp90 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_28", align 8
   %tmp91 = bitcast %struct._class_t* %tmp88 to i8*
-  %call9218 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %tmp91, i8* %tmp90, i8* %filename.0.in)
+  %call9218 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %tmp91, i8* %tmp90, i8* %filename.0.in)
   %tmp20 = bitcast i8* %call9218 to %5*
   %tmp21 = call i8* @objc_retain(i8* %call9218) nounwind
   %tmp22 = bitcast %5* %url.025 to i8*
   call void @objc_release(i8* %tmp22) nounwind
-  %tmp94 = load %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_29", align 8
-  %tmp95 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_31", align 8
+  %tmp94 = load %struct._class_t*, %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_29", align 8
+  %tmp95 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_31", align 8
   %tmp96 = bitcast %struct._class_t* %tmp94 to i8*
-  %call97 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %tmp96, i8* %tmp95)
-  %tmp99 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_33", align 8
-  %call10119 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %call97, i8* %tmp99, i8* %call9218, i32 signext 1, %4** %err)
+  %call97 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %tmp96, i8* %tmp95)
+  %tmp99 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_33", align 8
+  %call10119 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %call97, i8* %tmp99, i8* %call9218, i32 signext 1, %4** %err)
   %phitmp = icmp eq i8* %call10119, null
   br i1 %phitmp, label %if.then109, label %end
 
 if.then109:                                       ; preds = %if.end106, %land.lhs.true80, %if.end74
   %url.129 = phi %5* [ %tmp20, %if.end106 ], [ %url.025, %if.end74 ], [ %url.025, %land.lhs.true80 ]
-  %tmp110 = load %4** %err, align 8
+  %tmp110 = load %4*, %4** %err, align 8
   %tobool111 = icmp eq %4* %tmp110, null
   br i1 %tobool111, label %if.then112, label %if.end125
 
 if.then112:                                       ; preds = %if.then109
-  %tmp113 = load %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_50", align 8
-  %tmp114 = load %1** @NSCocoaErrorDomain, align 8
-  %tmp115 = load %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_51", align 8
+  %tmp113 = load %struct._class_t*, %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_50", align 8
+  %tmp114 = load %1*, %1** @NSCocoaErrorDomain, align 8
+  %tmp115 = load %struct._class_t*, %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_51", align 8
   %call117 = call %1* @truncatedString(%1* %filename.0, i64 1034)
-  %tmp118 = load %1** @NSFilePathErrorKey, align 8
-  %tmp119 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_53", align 8
+  %tmp118 = load %1*, %1** @NSFilePathErrorKey, align 8
+  %tmp119 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_53", align 8
   %tmp120 = bitcast %struct._class_t* %tmp115 to i8*
-  %call12113 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %tmp120, i8* %tmp119, %1* %call117, %1* %tmp118, i8* null)
-  %tmp122 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_55", align 8
+  %call12113 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %tmp120, i8* %tmp119, %1* %call117, %1* %tmp118, i8* null)
+  %tmp122 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_55", align 8
   %tmp123 = bitcast %struct._class_t* %tmp113 to i8*
-  %call12414 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %tmp123, i8* %tmp122, %1* %tmp114, i64 258, i8* %call12113)
+  %call12414 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %tmp123, i8* %tmp122, %1* %tmp114, i64 258, i8* %call12113)
   %tmp23 = call i8* @objc_retain(i8* %call12414) nounwind
   %tmp25 = call i8* @objc_autorelease(i8* %tmp23) nounwind
   %tmp28 = bitcast i8* %tmp25 to %4*
@@ -2965,12 +2970,12 @@ if.then112:                                       ; preds = %if.then109
 
 if.end125:                                        ; preds = %if.then112, %if.then109
   %tmp127 = phi %4* [ %tmp110, %if.then109 ], [ %tmp28, %if.then112 ]
-  %tmp126 = load %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_56", align 8
-  %tmp128 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_58", align 8
+  %tmp126 = load %struct._class_t*, %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_56", align 8
+  %tmp128 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_58", align 8
   %tmp129 = bitcast %struct._class_t* %tmp126 to i8*
-  %call13015 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %tmp129, i8* %tmp128, %4* %tmp127)
-  %tmp131 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_60", align 8
-  %call13317 = call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %call13015, i8* %tmp131)
+  %call13015 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %tmp129, i8* %tmp128, %4* %tmp127)
+  %tmp131 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_60", align 8
+  %call13317 = call i8* (i8*, i8*, ...) @objc_msgSend(i8* %call13015, i8* %tmp131)
   br label %end
 
 end:                                              ; preds = %if.end125, %if.end106, %if.end, %land.lhs.true, %entry
@@ -3012,7 +3017,8 @@ define void @test67(i8* %x) {
 !llvm.module.flags = !{!1}
 
 !0 = !{}
-!1 = !{i32 1, !"Debug Info Version", i32 2}
+!1 = !{i32 1, !"Debug Info Version", i32 3}
+!2 = !DISubprogram()
 
 ; CHECK: attributes #0 = { nounwind readnone }
 ; CHECK: attributes [[NUW]] = { nounwind }
diff --git a/test/Transforms/ObjCARC/cfg-hazards.ll b/test/Transforms/ObjCARC/cfg-hazards.ll
index 746d56df8fad..8407e446b4f3 100644
--- a/test/Transforms/ObjCARC/cfg-hazards.ll
+++ b/test/Transforms/ObjCARC/cfg-hazards.ll
@@ -421,7 +421,7 @@ loop:
   store i8* %a, i8** %block, align 8
   %casted_block = bitcast i8** %block to void ()*
   call void @block_callee(void ()* %casted_block)
-  %reloaded_a = load i8** %block, align 8
+  %reloaded_a = load i8*, i8** %block, align 8
   call void @objc_release(i8* %reloaded_a) nounwind, !clang.imprecise_release !0
   br i1 undef, label %loop, label %exit
   
diff --git a/test/Transforms/ObjCARC/contract-storestrong-ivar.ll b/test/Transforms/ObjCARC/contract-storestrong-ivar.ll
index 4a9b3140f101..8b1a02f3feb9 100644
--- a/test/Transforms/ObjCARC/contract-storestrong-ivar.ll
+++ b/test/Transforms/ObjCARC/contract-storestrong-ivar.ll
@@ -16,11 +16,11 @@ declare void @objc_release(i8*)
 
 define hidden void @y(%0* nocapture %self, %1* %preferencesController) nounwind {
 entry:
-  %ivar = load i64* @"OBJC_IVAR_$_Controller.preferencesController", align 8
+  %ivar = load i64, i64* @"OBJC_IVAR_$_Controller.preferencesController", align 8
   %tmp = bitcast %0* %self to i8*
-  %add.ptr = getelementptr inbounds i8* %tmp, i64 %ivar
+  %add.ptr = getelementptr inbounds i8, i8* %tmp, i64 %ivar
   %tmp1 = bitcast i8* %add.ptr to %1**
-  %tmp2 = load %1** %tmp1, align 8
+  %tmp2 = load %1*, %1** %tmp1, align 8
   %tmp3 = bitcast %1* %preferencesController to i8*
   %tmp4 = tail call i8* @objc_retain(i8* %tmp3) nounwind
   %tmp5 = bitcast %1* %tmp2 to i8*
diff --git a/test/Transforms/ObjCARC/contract-storestrong.ll b/test/Transforms/ObjCARC/contract-storestrong.ll
index f9308c8fdee2..aadc3a26539a 100644
--- a/test/Transforms/ObjCARC/contract-storestrong.ll
+++ b/test/Transforms/ObjCARC/contract-storestrong.ll
@@ -16,7 +16,7 @@ declare void @use_pointer(i8*)
 define void @test0(i8* %p) {
 entry:
   %0 = tail call i8* @objc_retain(i8* %p) nounwind
-  %tmp = load i8** @x, align 8
+  %tmp = load i8*, i8** @x, align 8
   store i8* %0, i8** @x, align 8
   tail call void @objc_release(i8* %tmp) nounwind
   ret void
@@ -24,10 +24,10 @@ entry:
 
 ; Don't do this if the load is volatile.
 
-;      CHECK: define void @test1(i8* %p) {
+; CHECK-LABEL: define void @test1(i8* %p) {
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   %0 = tail call i8* @objc_retain(i8* %p) [[NUW]]
-; CHECK-NEXT:   %tmp = load volatile i8** @x, align 8
+; CHECK-NEXT:   %tmp = load volatile i8*, i8** @x, align 8
 ; CHECK-NEXT:   store i8* %0, i8** @x, align 8
 ; CHECK-NEXT:   tail call void @objc_release(i8* %tmp) [[NUW]]
 ; CHECK-NEXT:   ret void
@@ -35,7 +35,7 @@ entry:
 define void @test1(i8* %p) {
 entry:
   %0 = tail call i8* @objc_retain(i8* %p) nounwind
-  %tmp = load volatile i8** @x, align 8
+  %tmp = load volatile i8*, i8** @x, align 8
   store i8* %0, i8** @x, align 8
   tail call void @objc_release(i8* %tmp) nounwind
   ret void
@@ -43,10 +43,10 @@ entry:
 
 ; Don't do this if the store is volatile.
 
-;      CHECK: define void @test2(i8* %p) {
+; CHECK-LABEL: define void @test2(i8* %p) {
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   %0 = tail call i8* @objc_retain(i8* %p) [[NUW]]
-; CHECK-NEXT:   %tmp = load i8** @x, align 8
+; CHECK-NEXT:   %tmp = load i8*, i8** @x, align 8
 ; CHECK-NEXT:   store volatile i8* %0, i8** @x, align 8
 ; CHECK-NEXT:   tail call void @objc_release(i8* %tmp) [[NUW]]
 ; CHECK-NEXT:   ret void
@@ -54,7 +54,7 @@ entry:
 define void @test2(i8* %p) {
 entry:
   %0 = tail call i8* @objc_retain(i8* %p) nounwind
-  %tmp = load i8** @x, align 8
+  %tmp = load i8*, i8** @x, align 8
   store volatile i8* %0, i8** @x, align 8
   tail call void @objc_release(i8* %tmp) nounwind
   ret void
@@ -63,19 +63,19 @@ entry:
 ; Don't do this if there's a use of the old pointer value between the store
 ; and the release.
 
-; CHECK:      define void @test3(i8* %newValue) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT:   %x0 = tail call i8* @objc_retain(i8* %newValue) [[NUW]]
-; CHECK-NEXT:   %x1 = load i8** @x, align 8
-; CHECK-NEXT:   store i8* %x0, i8** @x, align 8
-; CHECK-NEXT:   tail call void @use_pointer(i8* %x1), !clang.arc.no_objc_arc_exceptions !0
-; CHECK-NEXT:   tail call void @objc_release(i8* %x1) [[NUW]], !clang.imprecise_release !0
-; CHECK-NEXT:   ret void
-; CHECK-NEXT: }
+; CHECK-LABEL: define void @test3(i8* %newValue) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    %x0 = tail call i8* @objc_retain(i8* %newValue) [[NUW]]
+; CHECK-NEXT:    %x1 = load i8*, i8** @x, align 8
+; CHECK-NEXT:    store i8* %x0, i8** @x, align 8
+; CHECK-NEXT:    tail call void @use_pointer(i8* %x1), !clang.arc.no_objc_arc_exceptions !0
+; CHECK-NEXT:    tail call void @objc_release(i8* %x1) [[NUW]], !clang.imprecise_release !0
+; CHECK-NEXT:    ret void
+; CHECK-NEXT:  }
 define void @test3(i8* %newValue) {
 entry:
   %x0 = tail call i8* @objc_retain(i8* %newValue) nounwind
-  %x1 = load i8** @x, align 8
+  %x1 = load i8*, i8** @x, align 8
   store i8* %newValue, i8** @x, align 8
   tail call void @use_pointer(i8* %x1), !clang.arc.no_objc_arc_exceptions !0
   tail call void @objc_release(i8* %x1) nounwind, !clang.imprecise_release !0
@@ -84,19 +84,19 @@ entry:
 
 ; Like test3, but with an icmp use instead of a call, for good measure.
 
-; CHECK:      define i1 @test4(i8* %newValue, i8* %foo) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT:   %x0 = tail call i8* @objc_retain(i8* %newValue) [[NUW]]
-; CHECK-NEXT:   %x1 = load i8** @x, align 8
-; CHECK-NEXT:   store i8* %x0, i8** @x, align 8
-; CHECK-NEXT:   %t = icmp eq i8* %x1, %foo
-; CHECK-NEXT:   tail call void @objc_release(i8* %x1) [[NUW]], !clang.imprecise_release !0
-; CHECK-NEXT:   ret i1 %t
-; CHECK-NEXT: }
+; CHECK-LABEL:  define i1 @test4(i8* %newValue, i8* %foo) {
+; CHECK-NEXT:   entry:
+; CHECK-NEXT:     %x0 = tail call i8* @objc_retain(i8* %newValue) [[NUW]]
+; CHECK-NEXT:     %x1 = load i8*, i8** @x, align 8
+; CHECK-NEXT:     store i8* %x0, i8** @x, align 8
+; CHECK-NEXT:     %t = icmp eq i8* %x1, %foo
+; CHECK-NEXT:     tail call void @objc_release(i8* %x1) [[NUW]], !clang.imprecise_release !0
+; CHECK-NEXT:     ret i1 %t
+; CHECK-NEXT:   }
 define i1 @test4(i8* %newValue, i8* %foo) {
 entry:
   %x0 = tail call i8* @objc_retain(i8* %newValue) nounwind
-  %x1 = load i8** @x, align 8
+  %x1 = load i8*, i8** @x, align 8
   store i8* %newValue, i8** @x, align 8
   %t = icmp eq i8* %x1, %foo
   tail call void @objc_release(i8* %x1) nounwind, !clang.imprecise_release !0
@@ -105,14 +105,14 @@ entry:
 
 ; Do form an objc_storeStrong here, because the use is before the store.
 
-; CHECK: define i1 @test5(i8* %newValue, i8* %foo) {
+; CHECK-LABEL: define i1 @test5(i8* %newValue, i8* %foo) {
 ; CHECK: %t = icmp eq i8* %x1, %foo
 ; CHECK: tail call void @objc_storeStrong(i8** @x, i8* %newValue) [[NUW]]
 ; CHECK: }
 define i1 @test5(i8* %newValue, i8* %foo) {
 entry:
   %x0 = tail call i8* @objc_retain(i8* %newValue) nounwind
-  %x1 = load i8** @x, align 8
+  %x1 = load i8*, i8** @x, align 8
   %t = icmp eq i8* %x1, %foo
   store i8* %newValue, i8** @x, align 8
   tail call void @objc_release(i8* %x1) nounwind, !clang.imprecise_release !0
@@ -121,14 +121,14 @@ entry:
 
 ; Like test5, but the release is before the store.
 
-; CHECK: define i1 @test6(i8* %newValue, i8* %foo) {
+; CHECK-LABEL: define i1 @test6(i8* %newValue, i8* %foo) {
 ; CHECK: %t = icmp eq i8* %x1, %foo
 ; CHECK: tail call void @objc_storeStrong(i8** @x, i8* %newValue) [[NUW]]
 ; CHECK: }
 define i1 @test6(i8* %newValue, i8* %foo) {
 entry:
   %x0 = tail call i8* @objc_retain(i8* %newValue) nounwind
-  %x1 = load i8** @x, align 8
+  %x1 = load i8*, i8** @x, align 8
   tail call void @objc_release(i8* %x1) nounwind, !clang.imprecise_release !0
   %t = icmp eq i8* %x1, %foo
   store i8* %newValue, i8** @x, align 8
@@ -137,38 +137,86 @@ entry:
 
 ; Like test0, but there's no store, so don't form an objc_storeStrong.
 
-;      CHECK-LABEL: define void @test7(
+; CHECK-LABEL: define void @test7(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   %0 = tail call i8* @objc_retain(i8* %p) [[NUW]]
-; CHECK-NEXT:   %tmp = load i8** @x, align 8
+; CHECK-NEXT:   %tmp = load i8*, i8** @x, align 8
 ; CHECK-NEXT:   tail call void @objc_release(i8* %tmp) [[NUW]]
 ; CHECK-NEXT:   ret void
 ; CHECK-NEXT: }
 define void @test7(i8* %p) {
 entry:
   %0 = tail call i8* @objc_retain(i8* %p) nounwind
-  %tmp = load i8** @x, align 8
+  %tmp = load i8*, i8** @x, align 8
   tail call void @objc_release(i8* %tmp) nounwind
   ret void
 }
 
 ; Like test0, but there's no retain, so don't form an objc_storeStrong.
 
-;      CHECK-LABEL: define void @test8(
+; CHECK-LABEL: define void @test8(
 ; CHECK-NEXT: entry:
-; CHECK-NEXT:   %tmp = load i8** @x, align 8
+; CHECK-NEXT:   %tmp = load i8*, i8** @x, align 8
 ; CHECK-NEXT:   store i8* %p, i8** @x, align 8
 ; CHECK-NEXT:   tail call void @objc_release(i8* %tmp) [[NUW]]
 ; CHECK-NEXT:   ret void
 ; CHECK-NEXT: }
 define void @test8(i8* %p) {
 entry:
-  %tmp = load i8** @x, align 8
+  %tmp = load i8*, i8** @x, align 8
   store i8* %p, i8** @x, align 8
   tail call void @objc_release(i8* %tmp) nounwind
   ret void
 }
 
+; Make sure that we properly handle release that *may* release our new
+; value in between the retain and the store. We need to be sure that
+; this we can safely move the retain to the store. This specific test
+; makes sure that we properly handled a release of an unrelated
+; pointer.
+;
+; CHECK-LABEL: define i1 @test9(i8* %newValue, i8* %foo, i8* %unrelated_ptr) {
+; CHECK-NOT: objc_storeStrong
+define i1 @test9(i8* %newValue, i8* %foo, i8* %unrelated_ptr) {
+entry:
+  %x0 = tail call i8* @objc_retain(i8* %newValue) nounwind
+  tail call void @objc_release(i8* %unrelated_ptr) nounwind, !clang.imprecise_release !0
+  %x1 = load i8*, i8** @x, align 8
+  tail call void @objc_release(i8* %x1) nounwind, !clang.imprecise_release !0
+  %t = icmp eq i8* %x1, %foo
+  store i8* %newValue, i8** @x, align 8
+  ret i1 %t  
+}
+
+; Make sure that we don't perform the optimization when we just have a call.
+;
+; CHECK-LABEL: define i1 @test10(i8* %newValue, i8* %foo, i8* %unrelated_ptr) {
+; CHECK-NOT: objc_storeStrong
+define i1 @test10(i8* %newValue, i8* %foo, i8* %unrelated_ptr) {
+entry:
+  %x0 = tail call i8* @objc_retain(i8* %newValue) nounwind
+  call void @use_pointer(i8* %unrelated_ptr)
+  %x1 = load i8*, i8** @x, align 8
+  tail call void @objc_release(i8* %x1) nounwind, !clang.imprecise_release !0
+  %t = icmp eq i8* %x1, %foo
+  store i8* %newValue, i8** @x, align 8
+  ret i1 %t
+}
+
+; Make sure we form the store strong if the use in between the retain
+; and the store does not touch reference counts.
+; CHECK-LABEL: define i1 @test11(i8* %newValue, i8* %foo, i8* %unrelated_ptr) {
+; CHECK: objc_storeStrong
+define i1 @test11(i8* %newValue, i8* %foo, i8* %unrelated_ptr) {
+entry:
+  %x0 = tail call i8* @objc_retain(i8* %newValue) nounwind
+  %t = icmp eq i8* %newValue, %foo
+  %x1 = load i8*, i8** @x, align 8
+  tail call void @objc_release(i8* %x1) nounwind, !clang.imprecise_release !0
+  store i8* %newValue, i8** @x, align 8
+  ret i1 %t
+}
+
 !0 = !{}
 
 ; CHECK: attributes [[NUW]] = { nounwind }
diff --git a/test/Transforms/ObjCARC/contract.ll b/test/Transforms/ObjCARC/contract.ll
index 2259e17ec58c..6ad46f2c85c5 100644
--- a/test/Transforms/ObjCARC/contract.ll
+++ b/test/Transforms/ObjCARC/contract.ll
@@ -169,7 +169,7 @@ return:                                           ; preds = %if.then, %entry
 ; CHECK-NOT: clang.arc.use
 ; CHECK: }
 define void @test9(i8* %a, i8* %b) {
-  call void (...)* @clang.arc.use(i8* %a, i8* %b) nounwind
+  call void (...) @clang.arc.use(i8* %a, i8* %b) nounwind
   ret void
 }
 
diff --git a/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll b/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll
index c72566cd2065..b875c3f039e6 100644
--- a/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll
+++ b/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll
@@ -22,29 +22,29 @@ target triple = "x86_64-apple-macosx10.9.0"
 @"OBJC_CLASS_$_NSObject" = external global %struct._class_t
 @"\01L_OBJC_CLASSLIST_REFERENCES_$_" = internal global %struct._class_t* @"OBJC_CLASS_$_NSObject", section "__DATA, __objc_classrefs, regular, no_dead_strip", align 8
 @"\01L_OBJC_METH_VAR_NAME_" = internal global [4 x i8] c"new\00", section "__TEXT,__objc_methname,cstring_literals", align 1
-@"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i64 0, i64 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
+@"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i64 0, i64 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
 @__CFConstantStringClassReference = external global [0 x i32]
 @.str = private unnamed_addr constant [11 x i8] c"Failed: %@\00", align 1
-@_unnamed_cfstring_ = private constant %struct.NSConstantString { i32* getelementptr inbounds ([0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i64 10 }, section "__DATA,__cfstring"
+@_unnamed_cfstring_ = private constant %struct.NSConstantString { i32* getelementptr inbounds ([0 x i32], [0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i64 10 }, section "__DATA,__cfstring"
 @"OBJC_CLASS_$_NSException" = external global %struct._class_t
 @"\01L_OBJC_CLASSLIST_REFERENCES_$_1" = internal global %struct._class_t* @"OBJC_CLASS_$_NSException", section "__DATA, __objc_classrefs, regular, no_dead_strip", align 8
 @.str2 = private unnamed_addr constant [4 x i8] c"Foo\00", align 1
-@_unnamed_cfstring_3 = private constant %struct.NSConstantString { i32* getelementptr inbounds ([0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr inbounds ([4 x i8]* @.str2, i32 0, i32 0), i64 3 }, section "__DATA,__cfstring"
+@_unnamed_cfstring_3 = private constant %struct.NSConstantString { i32* getelementptr inbounds ([0 x i32], [0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str2, i32 0, i32 0), i64 3 }, section "__DATA,__cfstring"
 @"\01L_OBJC_METH_VAR_NAME_4" = internal global [14 x i8] c"raise:format:\00", section "__TEXT,__objc_methname,cstring_literals", align 1
-@"\01L_OBJC_SELECTOR_REFERENCES_5" = internal global i8* getelementptr inbounds ([14 x i8]* @"\01L_OBJC_METH_VAR_NAME_4", i64 0, i64 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
-@llvm.used = appending global [6 x i8*] [i8* bitcast (%struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_" to i8*), i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* bitcast (%struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_1" to i8*), i8* getelementptr inbounds ([14 x i8]* @"\01L_OBJC_METH_VAR_NAME_4", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_5" to i8*)], section "llvm.metadata"
+@"\01L_OBJC_SELECTOR_REFERENCES_5" = internal global i8* getelementptr inbounds ([14 x i8], [14 x i8]* @"\01L_OBJC_METH_VAR_NAME_4", i64 0, i64 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
+@llvm.used = appending global [6 x i8*] [i8* bitcast (%struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_" to i8*), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* bitcast (%struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_1" to i8*), i8* getelementptr inbounds ([14 x i8], [14 x i8]* @"\01L_OBJC_METH_VAR_NAME_4", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_5" to i8*)], section "llvm.metadata"
 
 define i32 @main() uwtable ssp {
 entry:
-  %tmp = load %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_", align 8, !dbg !37
-  %tmp1 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8, !dbg !37, !invariant.load !38
+  %tmp = load %struct._class_t*, %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_", align 8, !dbg !37
+  %tmp1 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8, !dbg !37, !invariant.load !38
   %tmp2 = bitcast %struct._class_t* %tmp to i8*, !dbg !37
 ; CHECK: call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %tmp2, i8* %tmp1)
   %call = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %tmp2, i8* %tmp1), !dbg !37, !clang.arc.no_objc_arc_exceptions !38
-  call void @llvm.dbg.value(metadata i8* %call, i64 0, metadata i32 02, metadata !{}), !dbg !37
+  call void @llvm.dbg.value(metadata i8* %call, i64 0, metadata !25, metadata !DIExpression()), !dbg !37
 ; CHECK: call i8* @objc_retain(i8* %call) [[NUW:#[0-9]+]]
   %tmp3 = call i8* @objc_retain(i8* %call) nounwind, !dbg !39
-  call void @llvm.dbg.value(metadata i8* %call, i64 0, metadata !25, metadata !{}), !dbg !39
+  call void @llvm.dbg.value(metadata i8* %call, i64 0, metadata !25, metadata !DIExpression()), !dbg !39
   invoke fastcc void @ThrowFunc(i8* %call)
           to label %eh.cont unwind label %lpad, !dbg !40, !clang.arc.no_objc_arc_exceptions !38
 
@@ -58,15 +58,15 @@ lpad:                                             ; preds = %entry
           catch i8* null, !dbg !40
   %tmp5 = extractvalue { i8*, i32 } %tmp4, 0, !dbg !40
   %exn.adjusted = call i8* @objc_begin_catch(i8* %tmp5) nounwind, !dbg !44
-  call void @llvm.dbg.value(metadata i8 0, i64 0, metadata !21, metadata !{}), !dbg !46
+  call void @llvm.dbg.value(metadata i8 0, i64 0, metadata !21, metadata !DIExpression()), !dbg !46
   call void @objc_end_catch(), !dbg !49, !clang.arc.no_objc_arc_exceptions !38
 ; CHECK: call void @objc_release(i8* %call)
   call void @objc_release(i8* %call) nounwind, !dbg !42, !clang.imprecise_release !38
-  call void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring_ to i8*), i8* %call), !dbg !50, !clang.arc.no_objc_arc_exceptions !38
+  call void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring_ to i8*), i8* %call), !dbg !50, !clang.arc.no_objc_arc_exceptions !38
   br label %if.end, !dbg !52
 
 if.end:                                           ; preds = %lpad, %eh.cont
-  call void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring_ to i8*), i8* %call), !dbg !53, !clang.arc.no_objc_arc_exceptions !38
+  call void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring_ to i8*), i8* %call), !dbg !53, !clang.arc.no_objc_arc_exceptions !38
 ; CHECK: call void @objc_release(i8* %call)
   call void @objc_release(i8* %call) nounwind, !dbg !54, !clang.imprecise_release !38
   ret i32 0, !dbg !54
@@ -87,11 +87,11 @@ declare void @objc_exception_rethrow()
 define internal fastcc void @ThrowFunc(i8* %obj) uwtable noinline ssp {
 entry:
   %tmp = call i8* @objc_retain(i8* %obj) nounwind
-  call void @llvm.dbg.value(metadata i8* %obj, i64 0, metadata !32, metadata !{}), !dbg !55
-  %tmp1 = load %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_1", align 8, !dbg !56
-  %tmp2 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_5", align 8, !dbg !56, !invariant.load !38
+  call void @llvm.dbg.value(metadata i8* %obj, i64 0, metadata !32, metadata !DIExpression()), !dbg !55
+  %tmp1 = load %struct._class_t*, %struct._class_t** @"\01L_OBJC_CLASSLIST_REFERENCES_$_1", align 8, !dbg !56
+  %tmp2 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_5", align 8, !dbg !56, !invariant.load !38
   %tmp3 = bitcast %struct._class_t* %tmp1 to i8*, !dbg !56
-  call void (i8*, i8*, %0*, %0*, ...)* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %0*, %0*, ...)*)(i8* %tmp3, i8* %tmp2, %0* bitcast (%struct.NSConstantString* @_unnamed_cfstring_3 to %0*), %0* bitcast (%struct.NSConstantString* @_unnamed_cfstring_3 to %0*)), !dbg !56, !clang.arc.no_objc_arc_exceptions !38
+  call void (i8*, i8*, %0*, %0*, ...) bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %0*, %0*, ...)*)(i8* %tmp3, i8* %tmp2, %0* bitcast (%struct.NSConstantString* @_unnamed_cfstring_3 to %0*), %0* bitcast (%struct.NSConstantString* @_unnamed_cfstring_3 to %0*)), !dbg !56, !clang.arc.no_objc_arc_exceptions !38
   call void @objc_release(i8* %obj) nounwind, !dbg !58, !clang.imprecise_release !38
   ret void, !dbg !58
 }
@@ -113,62 +113,60 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!33, !34, !35, !36, !61}
 
-!0 = !{!"0x11\0016\00clang version 3.3 \001\00\002\00\000", !60, !1, !1, !3, !1, null} ; [ DW_TAG_compile_unit ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m] [DW_LANG_ObjC]
-!1 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_ObjC, producer: "clang version 3.3 ", isOptimized: true, runtimeVersion: 2, emissionKind: 0, file: !60, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1)
+!1 = !{}
 !3 = !{!5, !27}
-!5 = !{!"0x2e\00main\00main\00\009\000\001\000\006\000\001\0010", !60, !6, !7, null, i32 ()* @main, null, null, !10} ; [ DW_TAG_subprogram ] [line 9] [def] [scope 10] [main]
-!6 = !{!"0x29", !60} ; [ DW_TAG_file_type ]
-!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = !DISubprogram(name: "main", line: 9, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 10, file: !60, scope: !6, type: !7, function: i32 ()* @main, variables: !11)
+!6 = !DIFile(filename: "test.m", directory: "/Volumes/Files/gottesmmcab/Radar/12906997")
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!11}
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !11 = !{!12, !21, !25}
-!12 = !{!"0x100\00obj\0011\000", !13, !6, !14} ; [ DW_TAG_auto_variable ] [obj] [line 11]
-!13 = !{!"0xb\0010\000\000", !60, !5} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
-!14 = !{!"0x16\00id\0011\000\000\000\000", !60, null, !15} ; [ DW_TAG_typedef ] [id] [line 11, size 0, align 0, offset 0] [from ]
-!15 = !{!"0xf\00\000\0064\0064\000\000", !60, null, !16} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from objc_object]
-!16 = !{!"0x13\00objc_object\000\000\000\000\000\000", !60, null, null, !17, null, i32 0, null} ; [ DW_TAG_structure_type ] [objc_object] [line 0, size 0, align 0, offset 0] [def] [from ]
+!12 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "obj", line: 11, scope: !13, file: !6, type: !14)
+!13 = distinct !DILexicalBlock(line: 10, column: 0, file: !60, scope: !5)
+!14 = !DIDerivedType(tag: DW_TAG_typedef, name: "id", line: 11, file: !60, baseType: !15)
+!15 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !60, baseType: !16)
+!16 = !DICompositeType(tag: DW_TAG_structure_type, name: "objc_object", file: !60, elements: !17)
 !17 = !{!18}
-!18 = !{!"0xd\00isa\000\0064\000\000\000", !60, !16, !19} ; [ DW_TAG_member ] [isa] [line 0, size 64, align 0, offset 0] [from ]
-!19 = !{!"0xf\00\000\0064\000\000\000", null, null, !20} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from objc_class]
-!20 = !{!"0x13\00objc_class\000\000\000\000\004\000", !60, null, null, null, null, null, null} ; [ DW_TAG_structure_type ] [objc_class] [line 0, size 0, align 0, offset 0] [decl] [from ]
-!21 = !{!"0x100\00ok\0013\000", !22, !6, !23} ; [ DW_TAG_auto_variable ] [ok] [line 13]
-!22 = !{!"0xb\0012\000\001", !60, !13} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
-!23 = !{!"0x16\00BOOL\0062\000\000\000\000", !60, null, !24} ; [ DW_TAG_typedef ] [BOOL] [line 62, size 0, align 0, offset 0] [from signed char]
-!24 = !{!"0x24\00signed char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ] [signed char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
-!25 = !{!"0x100\00obj2\0015\000", !26, !6, !14} ; [ DW_TAG_auto_variable ] [obj2] [line 15]
-!26 = !{!"0xb\0014\000\002", !60, !22} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
-!27 = !{!"0x2e\00ThrowFunc\00ThrowFunc\00\004\001\001\000\006\00256\001\005", !60, !6, !28, null, void (i8*)* @ThrowFunc, null, null, !30} ; [ DW_TAG_subprogram ] [line 4] [local] [def] [scope 5] [ThrowFunc]
-!28 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !29, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!18 = !DIDerivedType(tag: DW_TAG_member, name: "isa", size: 64, file: !60, scope: !16, baseType: !19)
+!19 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, baseType: !20)
+!20 = !DICompositeType(tag: DW_TAG_structure_type, name: "objc_class", flags: DIFlagFwdDecl, file: !60)
+!21 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "ok", line: 13, scope: !22, file: !6, type: !23)
+!22 = distinct !DILexicalBlock(line: 12, column: 0, file: !60, scope: !13)
+!23 = !DIDerivedType(tag: DW_TAG_typedef, name: "BOOL", line: 62, file: !60, baseType: !24)
+!24 = !DIBasicType(tag: DW_TAG_base_type, name: "signed char", size: 8, align: 8, encoding: DW_ATE_signed_char)
+!25 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "obj2", line: 15, scope: !26, file: !6, type: !14)
+!26 = distinct !DILexicalBlock(line: 14, column: 0, file: !60, scope: !22)
+!27 = !DISubprogram(name: "ThrowFunc", line: 4, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !60, scope: !6, type: !28, function: void (i8*)* @ThrowFunc, variables: !31)
+!28 = !DISubroutineType(types: !29)
 !29 = !{null, !14}
-!30 = !{!31}
 !31 = !{!32}
-!32 = !{!"0x101\00obj\0016777220\000", !27, !6, !14} ; [ DW_TAG_arg_variable ] [obj] [line 4]
+!32 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "obj", line: 4, arg: 1, scope: !27, file: !6, type: !14)
 !33 = !{i32 1, !"Objective-C Version", i32 2}
 !34 = !{i32 1, !"Objective-C Image Info Version", i32 0}
 !35 = !{i32 1, !"Objective-C Image Info Section", !"__DATA, __objc_imageinfo, regular, no_dead_strip"}
 !36 = !{i32 4, !"Objective-C Garbage Collection", i32 0}
-!37 = !MDLocation(line: 11, scope: !13)
+!37 = !DILocation(line: 11, scope: !13)
 !38 = !{}
-!39 = !MDLocation(line: 15, scope: !26)
-!40 = !MDLocation(line: 17, scope: !41)
-!41 = !{!"0xb\0016\000\003", !60, !26} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
-!42 = !MDLocation(line: 22, scope: !26)
-!43 = !MDLocation(line: 23, scope: !22)
-!44 = !MDLocation(line: 19, scope: !41)
+!39 = !DILocation(line: 15, scope: !26)
+!40 = !DILocation(line: 17, scope: !41)
+!41 = distinct !DILexicalBlock(line: 16, column: 0, file: !60, scope: !26)
+!42 = !DILocation(line: 22, scope: !26)
+!43 = !DILocation(line: 23, scope: !22)
+!44 = !DILocation(line: 19, scope: !41)
 !45 = !{i8 0}
-!46 = !MDLocation(line: 20, scope: !47)
-!47 = !{!"0xb\0019\000\005", !60, !48} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
-!48 = !{!"0xb\0019\000\004", !60, !26} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
-!49 = !MDLocation(line: 21, scope: !47)
-!50 = !MDLocation(line: 24, scope: !51)
-!51 = !{!"0xb\0023\000\006", !60, !22} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
-!52 = !MDLocation(line: 25, scope: !51)
-!53 = !MDLocation(line: 27, scope: !13)
-!54 = !MDLocation(line: 28, scope: !13)
-!55 = !MDLocation(line: 4, scope: !27)
-!56 = !MDLocation(line: 6, scope: !57)
-!57 = !{!"0xb\005\000\007", !60, !27} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
-!58 = !MDLocation(line: 7, scope: !57)
-!60 = !{!"test.m", !"/Volumes/Files/gottesmmcab/Radar/12906997"}
-!61 = !{i32 1, !"Debug Info Version", i32 2}
+!46 = !DILocation(line: 20, scope: !47)
+!47 = distinct !DILexicalBlock(line: 19, column: 0, file: !60, scope: !48)
+!48 = distinct !DILexicalBlock(line: 19, column: 0, file: !60, scope: !26)
+!49 = !DILocation(line: 21, scope: !47)
+!50 = !DILocation(line: 24, scope: !51)
+!51 = distinct !DILexicalBlock(line: 23, column: 0, file: !60, scope: !22)
+!52 = !DILocation(line: 25, scope: !51)
+!53 = !DILocation(line: 27, scope: !13)
+!54 = !DILocation(line: 28, scope: !13)
+!55 = !DILocation(line: 4, scope: !27)
+!56 = !DILocation(line: 6, scope: !57)
+!57 = distinct !DILexicalBlock(line: 5, column: 0, file: !60, scope: !27)
+!58 = !DILocation(line: 7, scope: !57)
+!60 = !DIFile(filename: "test.m", directory: "/Volumes/Files/gottesmmcab/Radar/12906997")
+!61 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/ObjCARC/escape.ll b/test/Transforms/ObjCARC/escape.ll
index 357f7592d83c..c7a1b03c16fc 100644
--- a/test/Transforms/ObjCARC/escape.ll
+++ b/test/Transforms/ObjCARC/escape.ll
@@ -17,43 +17,43 @@ define void @test0() nounwind {
 entry:
   %weakLogNTimes = alloca %struct.__block_byref_weakLogNTimes, align 8
   %block = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, align 8
-  %byref.isa = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 0
+  %byref.isa = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 0
   store i8* null, i8** %byref.isa, align 8
-  %byref.forwarding = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 1
+  %byref.forwarding = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 1
   store %struct.__block_byref_weakLogNTimes* %weakLogNTimes, %struct.__block_byref_weakLogNTimes** %byref.forwarding, align 8
-  %byref.flags = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 2
+  %byref.flags = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 2
   store i32 33554432, i32* %byref.flags, align 8
-  %byref.size = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 3
+  %byref.size = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 3
   store i32 48, i32* %byref.size, align 4
-  %tmp1 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 4
+  %tmp1 = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 4
   store i8* bitcast (void (i8*, i8*)* @__Block_byref_object_copy_ to i8*), i8** %tmp1, align 8
-  %tmp2 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 5
+  %tmp2 = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 5
   store i8* bitcast (void (i8*)* @__Block_byref_object_dispose_ to i8*), i8** %tmp2, align 8
-  %weakLogNTimes1 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 6
+  %weakLogNTimes1 = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 6
   %tmp3 = bitcast void (...)** %weakLogNTimes1 to i8**
   %tmp4 = call i8* @objc_initWeak(i8** %tmp3, i8* null) nounwind
-  %block.isa = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 0
+  %block.isa = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 0
   store i8* null, i8** %block.isa, align 8
-  %block.flags = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 1
+  %block.flags = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 1
   store i32 1107296256, i32* %block.flags, align 8
-  %block.reserved = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 2
+  %block.reserved = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 2
   store i32 0, i32* %block.reserved, align 4
-  %block.invoke = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 3
+  %block.invoke = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 3
   store i8* bitcast (void (i8*, i32)* @__main_block_invoke_0 to i8*), i8** %block.invoke, align 8
-  %block.descriptor = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 4
+  %block.descriptor = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 4
   store %struct.__block_descriptor* null, %struct.__block_descriptor** %block.descriptor, align 8
-  %block.captured = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 5
+  %block.captured = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 5
   %tmp5 = bitcast %struct.__block_byref_weakLogNTimes* %weakLogNTimes to i8*
   store i8* %tmp5, i8** %block.captured, align 8
   %tmp6 = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block to i8*
   %tmp7 = call i8* @objc_retainBlock(i8* %tmp6) nounwind, !clang.arc.copy_on_escape !0
-  %tmp8 = load %struct.__block_byref_weakLogNTimes** %byref.forwarding, align 8
-  %weakLogNTimes3 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %tmp8, i64 0, i32 6
+  %tmp8 = load %struct.__block_byref_weakLogNTimes*, %struct.__block_byref_weakLogNTimes** %byref.forwarding, align 8
+  %weakLogNTimes3 = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %tmp8, i64 0, i32 6
   %tmp9 = bitcast void (...)** %weakLogNTimes3 to i8**
   %tmp10 = call i8* @objc_storeWeak(i8** %tmp9, i8* %tmp7) nounwind
-  %tmp11 = getelementptr inbounds i8* %tmp7, i64 16
+  %tmp11 = getelementptr inbounds i8, i8* %tmp7, i64 16
   %tmp12 = bitcast i8* %tmp11 to i8**
-  %tmp13 = load i8** %tmp12, align 8
+  %tmp13 = load i8*, i8** %tmp12, align 8
   %tmp14 = bitcast i8* %tmp13 to void (i8*, i32)*
   call void %tmp14(i8* %tmp7, i32 10) nounwind, !clang.arc.no_objc_arc_exceptions !0
   call void @objc_release(i8* %tmp7) nounwind, !clang.imprecise_release !0
@@ -72,43 +72,43 @@ define void @test1() nounwind {
 entry:
   %weakLogNTimes = alloca %struct.__block_byref_weakLogNTimes, align 8
   %block = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, align 8
-  %byref.isa = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 0
+  %byref.isa = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 0
   store i8* null, i8** %byref.isa, align 8
-  %byref.forwarding = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 1
+  %byref.forwarding = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 1
   store %struct.__block_byref_weakLogNTimes* %weakLogNTimes, %struct.__block_byref_weakLogNTimes** %byref.forwarding, align 8
-  %byref.flags = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 2
+  %byref.flags = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 2
   store i32 33554432, i32* %byref.flags, align 8
-  %byref.size = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 3
+  %byref.size = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 3
   store i32 48, i32* %byref.size, align 4
-  %tmp1 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 4
+  %tmp1 = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 4
   store i8* bitcast (void (i8*, i8*)* @__Block_byref_object_copy_ to i8*), i8** %tmp1, align 8
-  %tmp2 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 5
+  %tmp2 = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 5
   store i8* bitcast (void (i8*)* @__Block_byref_object_dispose_ to i8*), i8** %tmp2, align 8
-  %weakLogNTimes1 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 6
+  %weakLogNTimes1 = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 6
   %tmp3 = bitcast void (...)** %weakLogNTimes1 to i8**
   %tmp4 = call i8* @objc_initWeak(i8** %tmp3, i8* null) nounwind
-  %block.isa = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 0
+  %block.isa = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 0
   store i8* null, i8** %block.isa, align 8
-  %block.flags = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 1
+  %block.flags = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 1
   store i32 1107296256, i32* %block.flags, align 8
-  %block.reserved = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 2
+  %block.reserved = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 2
   store i32 0, i32* %block.reserved, align 4
-  %block.invoke = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 3
+  %block.invoke = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 3
   store i8* bitcast (void (i8*, i32)* @__main_block_invoke_0 to i8*), i8** %block.invoke, align 8
-  %block.descriptor = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 4
+  %block.descriptor = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 4
   store %struct.__block_descriptor* null, %struct.__block_descriptor** %block.descriptor, align 8
-  %block.captured = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 5
+  %block.captured = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 5
   %tmp5 = bitcast %struct.__block_byref_weakLogNTimes* %weakLogNTimes to i8*
   store i8* %tmp5, i8** %block.captured, align 8
   %tmp6 = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block to i8*
   %tmp7 = call i8* @objc_retainBlock(i8* %tmp6) nounwind, !clang.arc.copy_on_escape !0
-  %tmp8 = load %struct.__block_byref_weakLogNTimes** %byref.forwarding, align 8
-  %weakLogNTimes3 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %tmp8, i64 0, i32 6
+  %tmp8 = load %struct.__block_byref_weakLogNTimes*, %struct.__block_byref_weakLogNTimes** %byref.forwarding, align 8
+  %weakLogNTimes3 = getelementptr inbounds %struct.__block_byref_weakLogNTimes, %struct.__block_byref_weakLogNTimes* %tmp8, i64 0, i32 6
   %tmp9 = bitcast void (...)** %weakLogNTimes3 to i8**
   %tmp10 = call i8* @not_really_objc_storeWeak(i8** %tmp9, i8* %tmp7) nounwind
-  %tmp11 = getelementptr inbounds i8* %tmp7, i64 16
+  %tmp11 = getelementptr inbounds i8, i8* %tmp7, i64 16
   %tmp12 = bitcast i8* %tmp11 to i8**
-  %tmp13 = load i8** %tmp12, align 8
+  %tmp13 = load i8*, i8** %tmp12, align 8
   %tmp14 = bitcast i8* %tmp13 to void (i8*, i32)*
   call void %tmp14(i8* %tmp7, i32 10) nounwind, !clang.arc.no_objc_arc_exceptions !0
   call void @objc_release(i8* %tmp7) nounwind, !clang.imprecise_release !0
diff --git a/test/Transforms/ObjCARC/gvn.ll b/test/Transforms/ObjCARC/gvn.ll
index 2d120e7345a5..6f828545bc6f 100644
--- a/test/Transforms/ObjCARC/gvn.ll
+++ b/test/Transforms/ObjCARC/gvn.ll
@@ -11,15 +11,15 @@ declare i32 @objc_sync_exit(i8*)
 
 ; CHECK: define i8* @test0(i32 %n)
 ; CHECK-NEXT: entry:
-; CHECK-NEXT: %s = load i8** @x
+; CHECK-NEXT: %s = load i8*, i8** @x
 ; CHECK-NOT: load
 ; CHECK: ret i8* %s
 ; CHECK-NEXT: }
 define i8* @test0(i32 %n) nounwind {
 entry:
-  %s = load i8** @x
+  %s = load i8*, i8** @x
   %0 = tail call i8* @objc_retain(i8* %s) nounwind
-  %t = load i8** @x
+  %t = load i8*, i8** @x
   ret i8* %t
 }
 
@@ -33,9 +33,9 @@ entry:
 ; CHECK: }
 define i8* @test1(i32 %n) nounwind {
 entry:
-  %s = load i8** @x
+  %s = load i8*, i8** @x
   %0 = call i32 @objc_sync_enter(i8* %s)
-  %t = load i8** @x
+  %t = load i8*, i8** @x
   %1 = call i32 @objc_sync_exit(i8* %s)
   ret i8* %t
 }
diff --git a/test/Transforms/ObjCARC/intrinsic-use-isolated.ll b/test/Transforms/ObjCARC/intrinsic-use-isolated.ll
index f5c31fd82ecb..03d7520dde91 100644
--- a/test/Transforms/ObjCARC/intrinsic-use-isolated.ll
+++ b/test/Transforms/ObjCARC/intrinsic-use-isolated.ll
@@ -10,7 +10,7 @@ declare void @clang.arc.use(...) nounwind
 ; CHECK-NOT: clang.arc.use
 ; CHECK: }
 define void @test0(i8* %a, i8* %b) {
-  call void (...)* @clang.arc.use(i8* %a, i8* %b) nounwind
+  call void (...) @clang.arc.use(i8* %a, i8* %b) nounwind
   ret void
 }
 
diff --git a/test/Transforms/ObjCARC/intrinsic-use.ll b/test/Transforms/ObjCARC/intrinsic-use.ll
index b1e56c8e9de1..f75b1872b172 100644
--- a/test/Transforms/ObjCARC/intrinsic-use.ll
+++ b/test/Transforms/ObjCARC/intrinsic-use.ll
@@ -22,14 +22,14 @@ declare void @test0_helper(i8*, i8**)
 ; CHECK-NEXT:   store i8* %y, i8** %temp0
 ; CHECK-NEXT:   @objc_retain(i8* %y)
 ; CHECK-NEXT:   call void @test0_helper
-; CHECK-NEXT:   [[VAL1:%.*]] = load i8** %temp0
-; CHECK-NEXT:   call void (...)* @clang.arc.use(i8* %y)
+; CHECK-NEXT:   [[VAL1:%.*]] = load i8*, i8** %temp0
+; CHECK-NEXT:   call void (...) @clang.arc.use(i8* %y)
 ; CHECK-NEXT:   @objc_retain(i8* [[VAL1]])
 ; CHECK-NEXT:   @objc_release(i8* %y)
 ; CHECK-NEXT:   store i8* [[VAL1]], i8** %temp1
 ; CHECK-NEXT:   call void @test0_helper
-; CHECK-NEXT:   [[VAL2:%.*]] = load i8** %temp1
-; CHECK-NEXT:   call void (...)* @clang.arc.use(i8* [[VAL1]])
+; CHECK-NEXT:   [[VAL2:%.*]] = load i8*, i8** %temp1
+; CHECK-NEXT:   call void (...) @clang.arc.use(i8* [[VAL1]])
 ; CHECK-NEXT:   @objc_retain(i8* [[VAL2]])
 ; CHECK-NEXT:   @objc_release(i8* [[VAL1]])
 ; CHECK-NEXT:   @objc_autorelease(i8* %x)
@@ -47,15 +47,15 @@ entry:
   %1 = call i8* @objc_retain(i8* %y) nounwind
   store i8* %y, i8** %temp0
   call void @test0_helper(i8* %x, i8** %temp0)
-  %val1 = load i8** %temp0
+  %val1 = load i8*, i8** %temp0
   %2 = call i8* @objc_retain(i8* %val1) nounwind
-  call void (...)* @clang.arc.use(i8* %y) nounwind
+  call void (...) @clang.arc.use(i8* %y) nounwind
   call void @objc_release(i8* %y) nounwind
   store i8* %val1, i8** %temp1
   call void @test0_helper(i8* %x, i8** %temp1)
-  %val2 = load i8** %temp1
+  %val2 = load i8*, i8** %temp1
   %3 = call i8* @objc_retain(i8* %val2) nounwind
-  call void (...)* @clang.arc.use(i8* %val1) nounwind
+  call void (...) @clang.arc.use(i8* %val1) nounwind
   call void @objc_release(i8* %val1) nounwind
   %4 = call i8* @objc_retain(i8* %x) nounwind
   %5 = call i8* @objc_autorelease(i8* %x) nounwind
@@ -70,14 +70,14 @@ entry:
 ; CHECK-NEXT:   store i8* %y, i8** %temp0
 ; CHECK-NEXT:   @objc_retain(i8* %y)
 ; CHECK-NEXT:   call void @test0_helper
-; CHECK-NEXT:   [[VAL1:%.*]] = load i8** %temp0
-; CHECK-NEXT:   call void (...)* @clang.arc.use(i8* %y)
+; CHECK-NEXT:   [[VAL1:%.*]] = load i8*, i8** %temp0
+; CHECK-NEXT:   call void (...) @clang.arc.use(i8* %y)
 ; CHECK-NEXT:   @objc_retain(i8* [[VAL1]])
 ; CHECK-NEXT:   @objc_release(i8* %y)
 ; CHECK-NEXT:   store i8* [[VAL1]], i8** %temp1
 ; CHECK-NEXT:   call void @test0_helper
-; CHECK-NEXT:   [[VAL2:%.*]] = load i8** %temp1
-; CHECK-NEXT:   call void (...)* @clang.arc.use(i8* [[VAL1]])
+; CHECK-NEXT:   [[VAL2:%.*]] = load i8*, i8** %temp1
+; CHECK-NEXT:   call void (...) @clang.arc.use(i8* [[VAL1]])
 ; CHECK-NEXT:   @objc_retain(i8* [[VAL2]])
 ; CHECK-NEXT:   @objc_release(i8* [[VAL1]])
 ; CHECK-NEXT:   @objc_autorelease(i8* %x)
@@ -93,15 +93,15 @@ entry:
   %1 = call i8* @objc_retain(i8* %y) nounwind
   store i8* %y, i8** %temp0
   call void @test0_helper(i8* %x, i8** %temp0)
-  %val1 = load i8** %temp0
+  %val1 = load i8*, i8** %temp0
   %2 = call i8* @objc_retain(i8* %val1) nounwind
-  call void (...)* @clang.arc.use(i8* %y) nounwind
+  call void (...) @clang.arc.use(i8* %y) nounwind
   call void @objc_release(i8* %y) nounwind, !clang.imprecise_release !0
   store i8* %val1, i8** %temp1
   call void @test0_helper(i8* %x, i8** %temp1)
-  %val2 = load i8** %temp1
+  %val2 = load i8*, i8** %temp1
   %3 = call i8* @objc_retain(i8* %val2) nounwind
-  call void (...)* @clang.arc.use(i8* %val1) nounwind
+  call void (...) @clang.arc.use(i8* %val1) nounwind
   call void @objc_release(i8* %val1) nounwind, !clang.imprecise_release !0
   %4 = call i8* @objc_retain(i8* %x) nounwind
   %5 = call i8* @objc_autorelease(i8* %x) nounwind
diff --git a/test/Transforms/ObjCARC/move-and-form-retain-autorelease.ll b/test/Transforms/ObjCARC/move-and-form-retain-autorelease.ll
index 5d058257c6ed..9894eb4f5345 100644
--- a/test/Transforms/ObjCARC/move-and-form-retain-autorelease.ll
+++ b/test/Transforms/ObjCARC/move-and-form-retain-autorelease.ll
@@ -80,20 +80,20 @@ declare i8* @objc_explicit_autorelease(i8*)
 
 define hidden %14* @foo(%15* %arg, %16* %arg2) {
 bb:
-  %tmp = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_3725", align 8
+  %tmp = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_3725", align 8
   %tmp4 = bitcast %15* %arg to i8*
   %tmp5 = tail call %18* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %18* (i8*, i8*)*)(i8* %tmp4, i8* %tmp)
   %tmp6 = bitcast %18* %tmp5 to i8*
   %tmp7 = tail call i8* @objc_retain(i8* %tmp6) nounwind
-  %tmp8 = load %2** @"\01L_OBJC_CLASSLIST_REFERENCES_$_40", align 8
-  %tmp9 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_4227", align 8
+  %tmp8 = load %2*, %2** @"\01L_OBJC_CLASSLIST_REFERENCES_$_40", align 8
+  %tmp9 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_4227", align 8
   %tmp10 = bitcast %2* %tmp8 to i8*
   %tmp11 = tail call %19* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %19* (i8*, i8*)*)(i8* %tmp10, i8* %tmp9)
-  %tmp12 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_4631", align 8
+  %tmp12 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_4631", align 8
   %tmp13 = bitcast %19* %tmp11 to i8*
   %tmp14 = tail call signext i8 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8 (i8*, i8*, %13*)*)(i8* %tmp13, i8* %tmp12, %13* bitcast (%12* @_unnamed_cfstring_386 to %13*))
   %tmp15 = bitcast %16* %arg2 to i8*
-  %tmp16 = load i8** bitcast (%0* @"\01l_objc_msgSend_fixup_count" to i8**), align 16
+  %tmp16 = load i8*, i8** bitcast (%0* @"\01l_objc_msgSend_fixup_count" to i8**), align 16
   %tmp17 = bitcast i8* %tmp16 to i64 (i8*, %1*)*
   %tmp18 = tail call i64 %tmp17(i8* %tmp15, %1* bitcast (%0* @"\01l_objc_msgSend_fixup_count" to %1*))
   %tmp19 = icmp eq i64 %tmp18, 0
@@ -110,104 +110,104 @@ bb22:                                             ; preds = %bb
 
 bb25:                                             ; preds = %bb22, %bb20
   %tmp26 = phi i1 [ %tmp21, %bb20 ], [ false, %bb22 ]
-  %tmp27 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_188", align 8
+  %tmp27 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_188", align 8
   %tmp28 = tail call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %tmp7, i8* %tmp27)
   %tmp29 = tail call i8* @objc_explicit_autorelease(i8* %tmp28) nounwind
   %tmp30 = bitcast i8* %tmp29 to %18*
   tail call void @objc_release(i8* %tmp7) nounwind
-  %tmp31 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_389", align 8
+  %tmp31 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_389", align 8
   %tmp32 = tail call %20* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %20* (i8*, i8*)*)(i8* %tmp29, i8* %tmp31)
-  %tmp33 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_391", align 8
+  %tmp33 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_391", align 8
   %tmp34 = bitcast %20* %tmp32 to i8*
   tail call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %16*)*)(i8* %tmp34, i8* %tmp33, %16* %arg2)
   br i1 %tmp26, label %bb46, label %bb35
 
 bb35:                                             ; preds = %bb25
-  %tmp36 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_389", align 8
+  %tmp36 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_389", align 8
   %tmp37 = tail call %20* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %20* (i8*, i8*)*)(i8* %tmp29, i8* %tmp36)
-  %tmp38 = load %2** @"\01L_OBJC_CLASSLIST_REFERENCES_$_70", align 8
-  %tmp39 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_393", align 8
+  %tmp38 = load %2*, %2** @"\01L_OBJC_CLASSLIST_REFERENCES_$_70", align 8
+  %tmp39 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_393", align 8
   %tmp40 = bitcast %2* %tmp38 to i8*
   %tmp41 = tail call %21* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %21* (i8*, i8*, i8)*)(i8* %tmp40, i8* %tmp39, i8 signext 1)
   %tmp42 = bitcast %21* %tmp41 to i8*
-  %tmp43 = load %13** @NSPrintHeaderAndFooter, align 8
-  %tmp44 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_159", align 8
+  %tmp43 = load %13*, %13** @NSPrintHeaderAndFooter, align 8
+  %tmp44 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_159", align 8
   %tmp45 = bitcast %20* %tmp37 to i8*
   tail call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i8*, %13*)*)(i8* %tmp45, i8* %tmp44, i8* %tmp42, %13* %tmp43)
   br label %bb46
 
 bb46:                                             ; preds = %bb35, %bb25, %bb22
   %tmp47 = phi %18* [ %tmp30, %bb35 ], [ %tmp30, %bb25 ], [ %tmp23, %bb22 ]
-  %tmp48 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_328", align 8
+  %tmp48 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_328", align 8
   %tmp49 = tail call %22* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %22* (i8*, i8*)*)(i8* %tmp4, i8* %tmp48)
   %tmp50 = bitcast %22* %tmp49 to i8*
-  %tmp51 = load i8** bitcast (%0* @"\01l_objc_msgSend_fixup_count" to i8**), align 16
+  %tmp51 = load i8*, i8** bitcast (%0* @"\01l_objc_msgSend_fixup_count" to i8**), align 16
   %tmp52 = bitcast i8* %tmp51 to i64 (i8*, %1*)*
   %tmp53 = tail call i64 %tmp52(i8* %tmp50, %1* bitcast (%0* @"\01l_objc_msgSend_fixup_count" to %1*))
   %tmp54 = icmp eq i64 %tmp53, 0
   br i1 %tmp54, label %bb55, label %bb57
 
 bb55:                                             ; preds = %bb46
-  %tmp56 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_395", align 8
+  %tmp56 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_395", align 8
   tail call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*)*)(i8* %tmp4, i8* %tmp56)
   br label %bb57
 
 bb57:                                             ; preds = %bb55, %bb46
-  %tmp58 = load %2** @"\01L_OBJC_CLASSLIST_REFERENCES_$_396", align 8
-  %tmp59 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_328", align 8
+  %tmp58 = load %2*, %2** @"\01L_OBJC_CLASSLIST_REFERENCES_$_396", align 8
+  %tmp59 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_328", align 8
   %tmp60 = tail call %22* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %22* (i8*, i8*)*)(i8* %tmp4, i8* %tmp59)
   %tmp61 = bitcast %22* %tmp60 to i8*
-  %tmp62 = load i8** bitcast (%0* @"\01l_objc_msgSend_fixup_objectAtIndex_" to i8**), align 16
+  %tmp62 = load i8*, i8** bitcast (%0* @"\01l_objc_msgSend_fixup_objectAtIndex_" to i8**), align 16
   %tmp63 = bitcast i8* %tmp62 to i8* (i8*, %1*, i64)*
   %tmp64 = tail call i8* %tmp63(i8* %tmp61, %1* bitcast (%0* @"\01l_objc_msgSend_fixup_objectAtIndex_" to %1*), i64 0)
-  %tmp65 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_398", align 8
+  %tmp65 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_398", align 8
   %tmp66 = tail call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %tmp64, i8* %tmp65)
   %tmp67 = bitcast i8* %tmp66 to %23*
-  %tmp68 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_400", align 8
+  %tmp68 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_400", align 8
   %tmp69 = bitcast %2* %tmp58 to i8*
   %tmp70 = tail call %14* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %14* (i8*, i8*, %23*, %18*)*)(i8* %tmp69, i8* %tmp68, %23* %tmp67, %18* %tmp47)
   %tmp71 = bitcast %14* %tmp70 to i8*
   ; hack to prevent the optimize from using objc_retainAutoreleasedReturnValue.
-  %tmp71x = getelementptr i8* %tmp71, i64 1
+  %tmp71x = getelementptr i8, i8* %tmp71, i64 1
   %tmp72 = tail call i8* @objc_retain(i8* %tmp71x) nounwind
-  %tmp73 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_402", align 8
+  %tmp73 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_402", align 8
   tail call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i8)*)(i8* %tmp72, i8* %tmp73, i8 signext 1)
-  %tmp74 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_404", align 8
+  %tmp74 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_404", align 8
   tail call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i8)*)(i8* %tmp72, i8* %tmp74, i8 signext 1)
-  %tmp75 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_328", align 8
+  %tmp75 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_328", align 8
   %tmp76 = tail call %22* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %22* (i8*, i8*)*)(i8* %tmp4, i8* %tmp75)
   %tmp77 = bitcast %22* %tmp76 to i8*
-  %tmp78 = load i8** bitcast (%0* @"\01l_objc_msgSend_fixup_objectAtIndex_" to i8**), align 16
+  %tmp78 = load i8*, i8** bitcast (%0* @"\01l_objc_msgSend_fixup_objectAtIndex_" to i8**), align 16
   %tmp79 = bitcast i8* %tmp78 to i8* (i8*, %1*, i64)*
   %tmp80 = tail call i8* %tmp79(i8* %tmp77, %1* bitcast (%0* @"\01l_objc_msgSend_fixup_objectAtIndex_" to %1*), i64 0)
-  %tmp81 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_406", align 8
+  %tmp81 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_406", align 8
   tail call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i64)*)(i8* %tmp80, i8* %tmp81, i64 9223372036854775807)
-  %tmp82 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_408", align 8
+  %tmp82 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_408", align 8
   %tmp83 = tail call %24* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %24* (i8*, i8*)*)(i8* %tmp72, i8* %tmp82)
   %tmp84 = bitcast %24* %tmp83 to i8*
   %tmp85 = tail call i8* @objc_retain(i8* %tmp84) nounwind
-  %tmp86 = load %2** @"\01L_OBJC_CLASSLIST_REFERENCES_$_409", align 8
+  %tmp86 = load %2*, %2** @"\01L_OBJC_CLASSLIST_REFERENCES_$_409", align 8
   %tmp87 = bitcast %2* %tmp86 to i8*
-  %tmp88 = load i8** bitcast (%0* @"\01l_objc_msgSend_fixup_alloc" to i8**), align 16
+  %tmp88 = load i8*, i8** bitcast (%0* @"\01l_objc_msgSend_fixup_alloc" to i8**), align 16
   %tmp89 = bitcast i8* %tmp88 to i8* (i8*, %1*)*
   %tmp90 = tail call i8* %tmp89(i8* %tmp87, %1* bitcast (%0* @"\01l_objc_msgSend_fixup_alloc" to %1*))
-  %tmp91 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_8", align 8
+  %tmp91 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_8", align 8
   %tmp92 = tail call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %tmp90, i8* %tmp91)
   %tmp93 = tail call i8* @objc_explicit_autorelease(i8* %tmp92) nounwind
   %tmp94 = bitcast i8* %tmp93 to %25*
-  %tmp95 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_411", align 8
+  %tmp95 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_411", align 8
   tail call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %25*)*)(i8* %tmp85, i8* %tmp95, %25* %tmp94)
   tail call void @objc_release(i8* %tmp93) nounwind
-  %tmp96 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_148", align 8
+  %tmp96 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_148", align 8
   %tmp97 = tail call signext i8 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8 (i8*, i8*)*)(i8* %tmp4, i8* %tmp96)
   %tmp98 = icmp eq i8 %tmp97, 0
   br i1 %tmp98, label %bb99, label %bb104
 
 bb99:                                             ; preds = %bb57
-  %tmp100 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_413", align 8
+  %tmp100 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_413", align 8
   %tmp101 = tail call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*)*)(i8* %tmp85, i8* %tmp100)
   %tmp102 = or i64 %tmp101, 12
-  %tmp103 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_415", align 8
+  %tmp103 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_415", align 8
   tail call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i64)*)(i8* %tmp85, i8* %tmp103, i64 %tmp102)
   br label %bb104
 
diff --git a/test/Transforms/ObjCARC/move-and-merge-autorelease.ll b/test/Transforms/ObjCARC/move-and-merge-autorelease.ll
index e5d2f07e45a2..0a68541d9350 100644
--- a/test/Transforms/ObjCARC/move-and-merge-autorelease.ll
+++ b/test/Transforms/ObjCARC/move-and-merge-autorelease.ll
@@ -35,10 +35,10 @@ declare i8* @objc_autorelease(i8*)
 
 define hidden %0* @foo(%1* %arg, %3* %arg3) {
 bb:
-  %tmp16 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_620", align 8
+  %tmp16 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_620", align 8
   %tmp17 = bitcast %3* %arg3 to i8*
   %tmp18 = call %4* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %4* (i8*, i8*)*)(i8* %tmp17, i8* %tmp16)
-  %tmp19 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_622", align 8
+  %tmp19 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_622", align 8
   %tmp20 = bitcast %4* %tmp18 to i8*
   %tmp21 = call %5* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %5* (i8*, i8*)*)(i8* %tmp20, i8* %tmp19)
   %tmp22 = bitcast %5* %tmp21 to i8*
@@ -48,11 +48,11 @@ bb:
   br i1 %tmp26, label %bb81, label %bb27
 
 bb27:                                             ; preds = %bb
-  %tmp29 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_11", align 8
+  %tmp29 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_11", align 8
   %tmp30 = bitcast %1* %arg to i8*
   %tmp31 = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %tmp30, i8* %tmp29)
   %tmp34 = call i8* @objc_retain(i8* %tmp31) nounwind
-  %tmp37 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_421455", align 8
+  %tmp37 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_421455", align 8
   %tmp39 = call %0* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %0* (i8*, i8*)*)(i8* %tmp34, i8* %tmp37)
   %tmp40 = bitcast %0* %tmp39 to i8*
   %tmp41 = call i8* @objc_retain(i8* %tmp40) nounwind
@@ -61,7 +61,7 @@ bb27:                                             ; preds = %bb
   br i1 %tmp44, label %bb45, label %bb55
 
 bb45:                                             ; preds = %bb27
-  %tmp47 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_624", align 8
+  %tmp47 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_624", align 8
   %tmp49 = call %0* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %0* (i8*, i8*)*)(i8* %tmp34, i8* %tmp47)
   %tmp51 = bitcast %0* %tmp49 to i8*
   %tmp52 = call i8* @objc_retain(i8* %tmp51) nounwind
@@ -74,14 +74,14 @@ bb55:                                             ; preds = %bb27, %bb45
   br i1 %tmp57, label %bb76, label %bb58
 
 bb58:                                             ; preds = %bb55
-  %tmp60 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_598", align 8
+  %tmp60 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_598", align 8
   %tmp61 = bitcast %0* %tmp13.0 to i8*
   %tmp62 = call signext i8 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8 (i8*, i8*)*)(i8* %tmp61, i8* %tmp60)
   %tmp64 = icmp eq i8 %tmp62, 0
   br i1 %tmp64, label %bb76, label %bb65
 
 bb65:                                             ; preds = %bb58
-  %tmp68 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_626", align 8
+  %tmp68 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_626", align 8
   %tmp69 = bitcast %0* %tmp13.0 to i8*
   %tmp70 = call %0* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %0* (i8*, i8*, %5*)*)(i8* %tmp69, i8* %tmp68, %5* %tmp24)
   %tmp72 = bitcast %0* %tmp70 to i8*
@@ -99,9 +99,9 @@ bb81:                                             ; preds = %bb, %bb76
   %tmp10.1 = phi %0* [ %tmp10.0, %bb76 ], [ null, %bb ]
   %tmp83 = bitcast %0* %tmp10.1 to i8*
   %tmp84 = call i8* @objc_retain(i8* %tmp83) nounwind
-  %tmp88 = bitcast i8* %tmp87 to %0*
   call void @objc_release(i8* %tmp23) nounwind
   %tmp87 = call i8* @objc_autorelease(i8* %tmp84) nounwind
+  %tmp88 = bitcast i8* %tmp87 to %0*
   %tmp92 = bitcast %0* %tmp10.1 to i8*
   call void @objc_release(i8* %tmp92) nounwind
   ret %0* %tmp88
diff --git a/test/Transforms/ObjCARC/nested.ll b/test/Transforms/ObjCARC/nested.ll
index 7d72e37f8034..464426abfb06 100644
--- a/test/Transforms/ObjCARC/nested.ll
+++ b/test/Transforms/ObjCARC/nested.ll
@@ -3,7 +3,7 @@
 %struct.__objcFastEnumerationState = type { i64, i8**, i64*, [5 x i64] }
 
 @"\01L_OBJC_METH_VAR_NAME_" = internal global [43 x i8] c"countByEnumeratingWithState:objects:count:\00", section "__TEXT,__objc_methname,cstring_literals", align 1
-@"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([43 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i64 0, i64 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
+@"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([43 x i8], [43 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i64 0, i64 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
 @g = common global i8* null, align 8
 @"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] [i32 0, i32 16], section "__DATA, __objc_imageinfo, regular, no_dead_strip"
 
@@ -37,16 +37,16 @@ entry:
   %tmp = bitcast %struct.__objcFastEnumerationState* %state.ptr to i8*
   call void @llvm.memset.p0i8.i64(i8* %tmp, i8 0, i64 64, i32 8, i1 false)
   %1 = call i8* @objc_retain(i8* %0) nounwind
-  %tmp2 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp2 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %1, i8* %tmp2, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %iszero = icmp eq i64 %call, 0
   br i1 %iszero, label %forcoll.empty, label %forcoll.loopinit
 
 forcoll.loopinit:
-  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
-  %mutationsptr = load i64** %mutationsptr.ptr, align 8
-  %forcoll.initial-mutations = load i64* %mutationsptr, align 8
-  %stateitems.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 1
+  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
+  %mutationsptr = load i64*, i64** %mutationsptr.ptr, align 8
+  %forcoll.initial-mutations = load i64, i64* %mutationsptr, align 8
+  %stateitems.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 1
   br label %forcoll.loopbody.outer
 
 forcoll.loopbody.outer:
@@ -57,8 +57,8 @@ forcoll.loopbody.outer:
 
 forcoll.loopbody:
   %forcoll.index = phi i64 [ 0, %forcoll.loopbody.outer ], [ %4, %forcoll.notmutated ]
-  %mutationsptr3 = load i64** %mutationsptr.ptr, align 8
-  %statemutations = load i64* %mutationsptr3, align 8
+  %mutationsptr3 = load i64*, i64** %mutationsptr.ptr, align 8
+  %statemutations = load i64, i64* %mutationsptr3, align 8
   %2 = icmp eq i64 %statemutations, %forcoll.initial-mutations
   br i1 %2, label %forcoll.notmutated, label %forcoll.mutated
 
@@ -67,16 +67,16 @@ forcoll.mutated:
   br label %forcoll.notmutated
 
 forcoll.notmutated:
-  %stateitems = load i8*** %stateitems.ptr, align 8
-  %currentitem.ptr = getelementptr i8** %stateitems, i64 %forcoll.index
-  %3 = load i8** %currentitem.ptr, align 8
+  %stateitems = load i8**, i8*** %stateitems.ptr, align 8
+  %currentitem.ptr = getelementptr i8*, i8** %stateitems, i64 %forcoll.index
+  %3 = load i8*, i8** %currentitem.ptr, align 8
   call void @use(i8* %3)
   %4 = add i64 %forcoll.index, 1
   %exitcond = icmp eq i64 %4, %umax
   br i1 %exitcond, label %forcoll.refetch, label %forcoll.loopbody
 
 forcoll.refetch:
-  %tmp5 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp5 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call6 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %1, i8* %tmp5, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %5 = icmp eq i64 %call6, 0
   br i1 %5, label %forcoll.empty, label %forcoll.loopbody.outer
@@ -102,16 +102,16 @@ entry:
   %tmp = bitcast %struct.__objcFastEnumerationState* %state.ptr to i8*
   call void @llvm.memset.p0i8.i64(i8* %tmp, i8 0, i64 64, i32 8, i1 false)
   %1 = call i8* @objc_retain(i8* %0) nounwind
-  %tmp2 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp2 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call3 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %1, i8* %tmp2, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %iszero = icmp eq i64 %call3, 0
   br i1 %iszero, label %forcoll.empty, label %forcoll.loopinit
 
 forcoll.loopinit:
-  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
-  %mutationsptr = load i64** %mutationsptr.ptr, align 8
-  %forcoll.initial-mutations = load i64* %mutationsptr, align 8
-  %stateitems.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 1
+  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
+  %mutationsptr = load i64*, i64** %mutationsptr.ptr, align 8
+  %forcoll.initial-mutations = load i64, i64* %mutationsptr, align 8
+  %stateitems.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 1
   br label %forcoll.loopbody.outer
 
 forcoll.loopbody.outer:
@@ -122,8 +122,8 @@ forcoll.loopbody.outer:
 
 forcoll.loopbody:
   %forcoll.index = phi i64 [ 0, %forcoll.loopbody.outer ], [ %4, %forcoll.notmutated ]
-  %mutationsptr4 = load i64** %mutationsptr.ptr, align 8
-  %statemutations = load i64* %mutationsptr4, align 8
+  %mutationsptr4 = load i64*, i64** %mutationsptr.ptr, align 8
+  %statemutations = load i64, i64* %mutationsptr4, align 8
   %2 = icmp eq i64 %statemutations, %forcoll.initial-mutations
   br i1 %2, label %forcoll.notmutated, label %forcoll.mutated
 
@@ -132,16 +132,16 @@ forcoll.mutated:
   br label %forcoll.notmutated
 
 forcoll.notmutated:
-  %stateitems = load i8*** %stateitems.ptr, align 8
-  %currentitem.ptr = getelementptr i8** %stateitems, i64 %forcoll.index
-  %3 = load i8** %currentitem.ptr, align 8
+  %stateitems = load i8**, i8*** %stateitems.ptr, align 8
+  %currentitem.ptr = getelementptr i8*, i8** %stateitems, i64 %forcoll.index
+  %3 = load i8*, i8** %currentitem.ptr, align 8
   call void @use(i8* %3)
   %4 = add i64 %forcoll.index, 1
   %exitcond = icmp eq i64 %4, %umax
   br i1 %exitcond, label %forcoll.refetch, label %forcoll.loopbody
 
 forcoll.refetch:
-  %tmp6 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp6 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call7 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %1, i8* %tmp6, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %5 = icmp eq i64 %call7, 0
   br i1 %5, label %forcoll.empty, label %forcoll.loopbody.outer
@@ -162,21 +162,21 @@ define void @test4() nounwind {
 entry:
   %state.ptr = alloca %struct.__objcFastEnumerationState, align 8
   %items.ptr = alloca [16 x i8*], align 8
-  %tmp = load i8** @g, align 8
+  %tmp = load i8*, i8** @g, align 8
   %0 = call i8* @objc_retain(i8* %tmp) nounwind
   %tmp2 = bitcast %struct.__objcFastEnumerationState* %state.ptr to i8*
   call void @llvm.memset.p0i8.i64(i8* %tmp2, i8 0, i64 64, i32 8, i1 false)
   %1 = call i8* @objc_retain(i8* %0) nounwind
-  %tmp4 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp4 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %1, i8* %tmp4, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %iszero = icmp eq i64 %call, 0
   br i1 %iszero, label %forcoll.empty, label %forcoll.loopinit
 
 forcoll.loopinit:
-  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
-  %mutationsptr = load i64** %mutationsptr.ptr, align 8
-  %forcoll.initial-mutations = load i64* %mutationsptr, align 8
-  %stateitems.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 1
+  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
+  %mutationsptr = load i64*, i64** %mutationsptr.ptr, align 8
+  %forcoll.initial-mutations = load i64, i64* %mutationsptr, align 8
+  %stateitems.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 1
   br label %forcoll.loopbody.outer
 
 forcoll.loopbody.outer:
@@ -187,8 +187,8 @@ forcoll.loopbody.outer:
 
 forcoll.loopbody:
   %forcoll.index = phi i64 [ 0, %forcoll.loopbody.outer ], [ %4, %forcoll.notmutated ]
-  %mutationsptr5 = load i64** %mutationsptr.ptr, align 8
-  %statemutations = load i64* %mutationsptr5, align 8
+  %mutationsptr5 = load i64*, i64** %mutationsptr.ptr, align 8
+  %statemutations = load i64, i64* %mutationsptr5, align 8
   %2 = icmp eq i64 %statemutations, %forcoll.initial-mutations
   br i1 %2, label %forcoll.notmutated, label %forcoll.mutated
 
@@ -197,16 +197,16 @@ forcoll.mutated:
   br label %forcoll.notmutated
 
 forcoll.notmutated:
-  %stateitems = load i8*** %stateitems.ptr, align 8
-  %currentitem.ptr = getelementptr i8** %stateitems, i64 %forcoll.index
-  %3 = load i8** %currentitem.ptr, align 8
+  %stateitems = load i8**, i8*** %stateitems.ptr, align 8
+  %currentitem.ptr = getelementptr i8*, i8** %stateitems, i64 %forcoll.index
+  %3 = load i8*, i8** %currentitem.ptr, align 8
   call void @use(i8* %3)
   %4 = add i64 %forcoll.index, 1
   %exitcond = icmp eq i64 %4, %umax
   br i1 %exitcond, label %forcoll.refetch, label %forcoll.loopbody
 
 forcoll.refetch:
-  %tmp7 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp7 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call8 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %1, i8* %tmp7, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %5 = icmp eq i64 %call8, 0
   br i1 %5, label %forcoll.empty, label %forcoll.loopbody.outer
@@ -229,20 +229,19 @@ entry:
   %items.ptr = alloca [16 x i8*], align 8
   %call = call i8* @returner()
   %0 = call i8* @objc_retainAutoreleasedReturnValue(i8* %call) nounwind
-  call void @callee()
   %tmp = bitcast %struct.__objcFastEnumerationState* %state.ptr to i8*
   call void @llvm.memset.p0i8.i64(i8* %tmp, i8 0, i64 64, i32 8, i1 false)
   %1 = call i8* @objc_retain(i8* %0) nounwind
-  %tmp2 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp2 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call3 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %1, i8* %tmp2, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %iszero = icmp eq i64 %call3, 0
   br i1 %iszero, label %forcoll.empty, label %forcoll.loopinit
 
 forcoll.loopinit:
-  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
-  %mutationsptr = load i64** %mutationsptr.ptr, align 8
-  %forcoll.initial-mutations = load i64* %mutationsptr, align 8
-  %stateitems.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 1
+  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
+  %mutationsptr = load i64*, i64** %mutationsptr.ptr, align 8
+  %forcoll.initial-mutations = load i64, i64* %mutationsptr, align 8
+  %stateitems.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 1
   br label %forcoll.loopbody.outer
 
 forcoll.loopbody.outer:
@@ -253,8 +252,8 @@ forcoll.loopbody.outer:
 
 forcoll.loopbody:
   %forcoll.index = phi i64 [ 0, %forcoll.loopbody.outer ], [ %4, %forcoll.notmutated ]
-  %mutationsptr4 = load i64** %mutationsptr.ptr, align 8
-  %statemutations = load i64* %mutationsptr4, align 8
+  %mutationsptr4 = load i64*, i64** %mutationsptr.ptr, align 8
+  %statemutations = load i64, i64* %mutationsptr4, align 8
   %2 = icmp eq i64 %statemutations, %forcoll.initial-mutations
   br i1 %2, label %forcoll.notmutated, label %forcoll.mutated
 
@@ -263,16 +262,16 @@ forcoll.mutated:
   br label %forcoll.notmutated
 
 forcoll.notmutated:
-  %stateitems = load i8*** %stateitems.ptr, align 8
-  %currentitem.ptr = getelementptr i8** %stateitems, i64 %forcoll.index
-  %3 = load i8** %currentitem.ptr, align 8
+  %stateitems = load i8**, i8*** %stateitems.ptr, align 8
+  %currentitem.ptr = getelementptr i8*, i8** %stateitems, i64 %forcoll.index
+  %3 = load i8*, i8** %currentitem.ptr, align 8
   call void @use(i8* %3)
   %4 = add i64 %forcoll.index, 1
   %exitcond = icmp eq i64 %4, %umax
   br i1 %exitcond, label %forcoll.refetch, label %forcoll.loopbody
 
 forcoll.refetch:
-  %tmp6 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp6 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call7 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %1, i8* %tmp6, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %5 = icmp eq i64 %call7, 0
   br i1 %5, label %forcoll.empty, label %forcoll.loopbody.outer
@@ -283,13 +282,12 @@ forcoll.empty:
   ret void
 }
 
-; TODO: Delete a nested retain+release pair.
-; The optimizer currently can't do this, because isn't isn't sophisticated enough in
-; reasnoning about nesting.
-
+; We handle this now due to the fact that a release just needs a post dominating
+; use.
+;
 ; CHECK-LABEL: define void @test6(
 ; CHECK: call i8* @objc_retain
-; CHECK: @objc_retain
+; CHECK-NOT: @objc_retain
 ; CHECK: }
 define void @test6() nounwind {
 entry:
@@ -300,16 +298,16 @@ entry:
   %tmp = bitcast %struct.__objcFastEnumerationState* %state.ptr to i8*
   call void @llvm.memset.p0i8.i64(i8* %tmp, i8 0, i64 64, i32 8, i1 false)
   %1 = call i8* @objc_retain(i8* %0) nounwind
-  %tmp2 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp2 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call3 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %1, i8* %tmp2, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %iszero = icmp eq i64 %call3, 0
   br i1 %iszero, label %forcoll.empty, label %forcoll.loopinit
 
 forcoll.loopinit:
-  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
-  %mutationsptr = load i64** %mutationsptr.ptr, align 8
-  %forcoll.initial-mutations = load i64* %mutationsptr, align 8
-  %stateitems.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 1
+  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
+  %mutationsptr = load i64*, i64** %mutationsptr.ptr, align 8
+  %forcoll.initial-mutations = load i64, i64* %mutationsptr, align 8
+  %stateitems.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 1
   br label %forcoll.loopbody.outer
 
 forcoll.loopbody.outer:
@@ -320,8 +318,8 @@ forcoll.loopbody.outer:
 
 forcoll.loopbody:
   %forcoll.index = phi i64 [ 0, %forcoll.loopbody.outer ], [ %4, %forcoll.notmutated ]
-  %mutationsptr4 = load i64** %mutationsptr.ptr, align 8
-  %statemutations = load i64* %mutationsptr4, align 8
+  %mutationsptr4 = load i64*, i64** %mutationsptr.ptr, align 8
+  %statemutations = load i64, i64* %mutationsptr4, align 8
   %2 = icmp eq i64 %statemutations, %forcoll.initial-mutations
   br i1 %2, label %forcoll.notmutated, label %forcoll.mutated
 
@@ -330,16 +328,16 @@ forcoll.mutated:
   br label %forcoll.notmutated
 
 forcoll.notmutated:
-  %stateitems = load i8*** %stateitems.ptr, align 8
-  %currentitem.ptr = getelementptr i8** %stateitems, i64 %forcoll.index
-  %3 = load i8** %currentitem.ptr, align 8
+  %stateitems = load i8**, i8*** %stateitems.ptr, align 8
+  %currentitem.ptr = getelementptr i8*, i8** %stateitems, i64 %forcoll.index
+  %3 = load i8*, i8** %currentitem.ptr, align 8
   call void @use(i8* %3)
   %4 = add i64 %forcoll.index, 1
   %exitcond = icmp eq i64 %4, %umax
   br i1 %exitcond, label %forcoll.refetch, label %forcoll.loopbody
 
 forcoll.refetch:
-  %tmp6 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp6 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call7 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %1, i8* %tmp6, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %5 = icmp eq i64 %call7, 0
   br i1 %5, label %forcoll.empty, label %forcoll.loopbody.outer
@@ -369,16 +367,16 @@ entry:
   %tmp = bitcast %struct.__objcFastEnumerationState* %state.ptr to i8*
   call void @llvm.memset.p0i8.i64(i8* %tmp, i8 0, i64 64, i32 8, i1 false)
   %1 = call i8* @objc_retain(i8* %0) nounwind
-  %tmp2 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp2 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call3 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %1, i8* %tmp2, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %iszero = icmp eq i64 %call3, 0
   br i1 %iszero, label %forcoll.empty, label %forcoll.loopinit
 
 forcoll.loopinit:
-  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
-  %mutationsptr = load i64** %mutationsptr.ptr, align 8
-  %forcoll.initial-mutations = load i64* %mutationsptr, align 8
-  %stateitems.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 1
+  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
+  %mutationsptr = load i64*, i64** %mutationsptr.ptr, align 8
+  %forcoll.initial-mutations = load i64, i64* %mutationsptr, align 8
+  %stateitems.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 1
   br label %forcoll.loopbody.outer
 
 forcoll.loopbody.outer:
@@ -389,8 +387,8 @@ forcoll.loopbody.outer:
 
 forcoll.loopbody:
   %forcoll.index = phi i64 [ 0, %forcoll.loopbody.outer ], [ %4, %forcoll.notmutated ]
-  %mutationsptr4 = load i64** %mutationsptr.ptr, align 8
-  %statemutations = load i64* %mutationsptr4, align 8
+  %mutationsptr4 = load i64*, i64** %mutationsptr.ptr, align 8
+  %statemutations = load i64, i64* %mutationsptr4, align 8
   %2 = icmp eq i64 %statemutations, %forcoll.initial-mutations
   br i1 %2, label %forcoll.notmutated, label %forcoll.mutated
 
@@ -399,16 +397,16 @@ forcoll.mutated:
   br label %forcoll.notmutated
 
 forcoll.notmutated:
-  %stateitems = load i8*** %stateitems.ptr, align 8
-  %currentitem.ptr = getelementptr i8** %stateitems, i64 %forcoll.index
-  %3 = load i8** %currentitem.ptr, align 8
+  %stateitems = load i8**, i8*** %stateitems.ptr, align 8
+  %currentitem.ptr = getelementptr i8*, i8** %stateitems, i64 %forcoll.index
+  %3 = load i8*, i8** %currentitem.ptr, align 8
   call void @use(i8* %3)
   %4 = add i64 %forcoll.index, 1
   %exitcond = icmp eq i64 %4, %umax
   br i1 %exitcond, label %forcoll.refetch, label %forcoll.loopbody
 
 forcoll.refetch:
-  %tmp6 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp6 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call7 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %1, i8* %tmp6, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %5 = icmp eq i64 %call7, 0
   br i1 %5, label %forcoll.empty, label %forcoll.loopbody.outer
@@ -435,16 +433,16 @@ entry:
   %tmp = bitcast %struct.__objcFastEnumerationState* %state.ptr to i8*
   call void @llvm.memset.p0i8.i64(i8* %tmp, i8 0, i64 64, i32 8, i1 false)
   %1 = call i8* @objc_retain(i8* %0) nounwind
-  %tmp2 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp2 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call3 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %1, i8* %tmp2, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %iszero = icmp eq i64 %call3, 0
   br i1 %iszero, label %forcoll.empty, label %forcoll.loopinit
 
 forcoll.loopinit:
-  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
-  %mutationsptr = load i64** %mutationsptr.ptr, align 8
-  %forcoll.initial-mutations = load i64* %mutationsptr, align 8
-  %stateitems.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 1
+  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
+  %mutationsptr = load i64*, i64** %mutationsptr.ptr, align 8
+  %forcoll.initial-mutations = load i64, i64* %mutationsptr, align 8
+  %stateitems.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 1
   br label %forcoll.loopbody.outer
 
 forcoll.loopbody.outer:
@@ -455,8 +453,8 @@ forcoll.loopbody.outer:
 
 forcoll.loopbody:
   %forcoll.index = phi i64 [ 0, %forcoll.loopbody.outer ], [ %4, %forcoll.next ]
-  %mutationsptr4 = load i64** %mutationsptr.ptr, align 8
-  %statemutations = load i64* %mutationsptr4, align 8
+  %mutationsptr4 = load i64*, i64** %mutationsptr.ptr, align 8
+  %statemutations = load i64, i64* %mutationsptr4, align 8
   %2 = icmp eq i64 %statemutations, %forcoll.initial-mutations
   br i1 %2, label %forcoll.notmutated, label %forcoll.mutated
 
@@ -465,9 +463,9 @@ forcoll.mutated:
   br label %forcoll.notmutated
 
 forcoll.notmutated:
-  %stateitems = load i8*** %stateitems.ptr, align 8
-  %currentitem.ptr = getelementptr i8** %stateitems, i64 %forcoll.index
-  %3 = load i8** %currentitem.ptr, align 8
+  %stateitems = load i8**, i8*** %stateitems.ptr, align 8
+  %currentitem.ptr = getelementptr i8*, i8** %stateitems, i64 %forcoll.index
+  %3 = load i8*, i8** %currentitem.ptr, align 8
   %tobool = icmp eq i8* %3, null
   br i1 %tobool, label %forcoll.next, label %if.then
 
@@ -481,7 +479,7 @@ forcoll.next:
   br i1 %exitcond, label %forcoll.refetch, label %forcoll.loopbody
 
 forcoll.refetch:
-  %tmp6 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp6 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call7 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %1, i8* %tmp6, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %5 = icmp eq i64 %call7, 0
   br i1 %5, label %forcoll.empty, label %forcoll.loopbody.outer
@@ -512,15 +510,15 @@ entry:
   %tmp = bitcast %struct.__objcFastEnumerationState* %state.ptr to i8*
   call void @llvm.memset.p0i8.i64(i8* %tmp, i8 0, i64 64, i32 8, i1 false)
   %2 = call i8* @objc_retain(i8* %0) nounwind
-  %tmp3 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp3 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call4 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %2, i8* %tmp3, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %iszero = icmp eq i64 %call4, 0
   br i1 %iszero, label %forcoll.empty, label %forcoll.loopinit
 
 forcoll.loopinit:
-  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
-  %mutationsptr = load i64** %mutationsptr.ptr, align 8
-  %forcoll.initial-mutations = load i64* %mutationsptr, align 8
+  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
+  %mutationsptr = load i64*, i64** %mutationsptr.ptr, align 8
+  %forcoll.initial-mutations = load i64, i64* %mutationsptr, align 8
   br label %forcoll.loopbody.outer
 
 forcoll.loopbody.outer:
@@ -531,8 +529,8 @@ forcoll.loopbody.outer:
 
 forcoll.loopbody:
   %forcoll.index = phi i64 [ %phitmp, %forcoll.notmutated.forcoll.loopbody_crit_edge ], [ 1, %forcoll.loopbody.outer ]
-  %mutationsptr5 = load i64** %mutationsptr.ptr, align 8
-  %statemutations = load i64* %mutationsptr5, align 8
+  %mutationsptr5 = load i64*, i64** %mutationsptr.ptr, align 8
+  %statemutations = load i64, i64* %mutationsptr5, align 8
   %3 = icmp eq i64 %statemutations, %forcoll.initial-mutations
   br i1 %3, label %forcoll.notmutated, label %forcoll.mutated
 
@@ -549,7 +547,7 @@ forcoll.notmutated.forcoll.loopbody_crit_edge:
   br label %forcoll.loopbody
 
 forcoll.refetch:
-  %tmp6 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp6 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call7 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %2, i8* %tmp6, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %4 = icmp eq i64 %call7, 0
   br i1 %4, label %forcoll.empty, label %forcoll.loopbody.outer
@@ -579,15 +577,15 @@ entry:
   %tmp = bitcast %struct.__objcFastEnumerationState* %state.ptr to i8*
   call void @llvm.memset.p0i8.i64(i8* %tmp, i8 0, i64 64, i32 8, i1 false)
   %2 = call i8* @objc_retain(i8* %0) nounwind
-  %tmp3 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp3 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call4 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %2, i8* %tmp3, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %iszero = icmp eq i64 %call4, 0
   br i1 %iszero, label %forcoll.empty, label %forcoll.loopinit
 
 forcoll.loopinit:
-  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
-  %mutationsptr = load i64** %mutationsptr.ptr, align 8
-  %forcoll.initial-mutations = load i64* %mutationsptr, align 8
+  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
+  %mutationsptr = load i64*, i64** %mutationsptr.ptr, align 8
+  %forcoll.initial-mutations = load i64, i64* %mutationsptr, align 8
   br label %forcoll.loopbody.outer
 
 forcoll.loopbody.outer:
@@ -598,8 +596,8 @@ forcoll.loopbody.outer:
 
 forcoll.loopbody:
   %forcoll.index = phi i64 [ %phitmp, %forcoll.notmutated ], [ 0, %forcoll.loopbody.outer ]
-  %mutationsptr5 = load i64** %mutationsptr.ptr, align 8
-  %statemutations = load i64* %mutationsptr5, align 8
+  %mutationsptr5 = load i64*, i64** %mutationsptr.ptr, align 8
+  %statemutations = load i64, i64* %mutationsptr5, align 8
   %3 = icmp eq i64 %statemutations, %forcoll.initial-mutations
   br i1 %3, label %forcoll.notmutated, label %forcoll.mutated
 
@@ -613,7 +611,7 @@ forcoll.notmutated:
   br i1 %exitcond, label %forcoll.refetch, label %forcoll.loopbody
 
 forcoll.refetch:
-  %tmp6 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp6 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call7 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %2, i8* %tmp6, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %4 = icmp eq i64 %call7, 0
   br i1 %4, label %forcoll.empty, label %forcoll.loopbody.outer
@@ -646,15 +644,15 @@ entry:
   %tmp = bitcast %struct.__objcFastEnumerationState* %state.ptr to i8*
   call void @llvm.memset.p0i8.i64(i8* %tmp, i8 0, i64 64, i32 8, i1 false)
   %2 = call i8* @objc_retain(i8* %0) nounwind
-  %tmp3 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp3 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call4 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %2, i8* %tmp3, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %iszero = icmp eq i64 %call4, 0
   br i1 %iszero, label %forcoll.empty, label %forcoll.loopinit
 
 forcoll.loopinit:
-  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
-  %mutationsptr = load i64** %mutationsptr.ptr, align 8
-  %forcoll.initial-mutations = load i64* %mutationsptr, align 8
+  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
+  %mutationsptr = load i64*, i64** %mutationsptr.ptr, align 8
+  %forcoll.initial-mutations = load i64, i64* %mutationsptr, align 8
   br label %forcoll.loopbody.outer
 
 forcoll.loopbody.outer:
@@ -665,8 +663,8 @@ forcoll.loopbody.outer:
 
 forcoll.loopbody:
   %forcoll.index = phi i64 [ %phitmp, %forcoll.notmutated.forcoll.loopbody_crit_edge ], [ 1, %forcoll.loopbody.outer ]
-  %mutationsptr5 = load i64** %mutationsptr.ptr, align 8
-  %statemutations = load i64* %mutationsptr5, align 8
+  %mutationsptr5 = load i64*, i64** %mutationsptr.ptr, align 8
+  %statemutations = load i64, i64* %mutationsptr5, align 8
   %3 = icmp eq i64 %statemutations, %forcoll.initial-mutations
   br i1 %3, label %forcoll.notmutated, label %forcoll.mutated
 
@@ -683,7 +681,7 @@ forcoll.notmutated.forcoll.loopbody_crit_edge:
   br label %forcoll.loopbody
 
 forcoll.refetch:
-  %tmp6 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp6 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call7 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %2, i8* %tmp6, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %4 = icmp eq i64 %call7, 0
   br i1 %4, label %forcoll.empty, label %forcoll.loopbody.outer
@@ -714,15 +712,15 @@ entry:
   %tmp = bitcast %struct.__objcFastEnumerationState* %state.ptr to i8*
   call void @llvm.memset.p0i8.i64(i8* %tmp, i8 0, i64 64, i32 8, i1 false)
   %2 = call i8* @objc_retain(i8* %0) nounwind
-  %tmp3 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp3 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call4 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %2, i8* %tmp3, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %iszero = icmp eq i64 %call4, 0
   br i1 %iszero, label %forcoll.empty, label %forcoll.loopinit
 
 forcoll.loopinit:
-  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
-  %mutationsptr = load i64** %mutationsptr.ptr, align 8
-  %forcoll.initial-mutations = load i64* %mutationsptr, align 8
+  %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState, %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2
+  %mutationsptr = load i64*, i64** %mutationsptr.ptr, align 8
+  %forcoll.initial-mutations = load i64, i64* %mutationsptr, align 8
   br label %forcoll.loopbody.outer
 
 forcoll.loopbody.outer:
@@ -733,8 +731,8 @@ forcoll.loopbody.outer:
 
 forcoll.loopbody:
   %forcoll.index = phi i64 [ %phitmp, %forcoll.notmutated ], [ 0, %forcoll.loopbody.outer ]
-  %mutationsptr5 = load i64** %mutationsptr.ptr, align 8
-  %statemutations = load i64* %mutationsptr5, align 8
+  %mutationsptr5 = load i64*, i64** %mutationsptr.ptr, align 8
+  %statemutations = load i64, i64* %mutationsptr5, align 8
   %3 = icmp eq i64 %statemutations, %forcoll.initial-mutations
   br i1 %3, label %forcoll.notmutated, label %forcoll.mutated
 
@@ -748,7 +746,7 @@ forcoll.notmutated:
   br i1 %exitcond, label %forcoll.refetch, label %forcoll.loopbody
 
 forcoll.refetch:
-  %tmp6 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
+  %tmp6 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8
   %call7 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %2, i8* %tmp6, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16)
   %4 = icmp eq i64 %call7, 0
   br i1 %4, label %forcoll.empty, label %forcoll.loopbody.outer
@@ -779,16 +777,16 @@ entry:
   %block = alloca <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>, align 8
   %block9 = alloca <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>, align 8
   %call = call i8* @def(), !clang.arc.no_objc_arc_exceptions !0
-  %foo = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block, i64 0, i32 5
-  %block.isa = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block, i64 0, i32 0
+  %foo = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block, i64 0, i32 5
+  %block.isa = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block, i64 0, i32 0
   store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** %block.isa, align 8
-  %block.flags = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block, i64 0, i32 1
+  %block.flags = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block, i64 0, i32 1
   store i32 1107296256, i32* %block.flags, align 8
-  %block.reserved = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block, i64 0, i32 2
+  %block.reserved = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block, i64 0, i32 2
   store i32 0, i32* %block.reserved, align 4
-  %block.invoke = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block, i64 0, i32 3
+  %block.invoke = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block, i64 0, i32 3
   store i8* bitcast (void (i8*)* @__crasher_block_invoke to i8*), i8** %block.invoke, align 8
-  %block.d = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block, i64 0, i32 4
+  %block.d = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block, i64 0, i32 4
   store %struct.__block_d* bitcast ({ i64, i64, i8*, i8*, i8*, i8* }* @__block_d_tmp to %struct.__block_d*), %struct.__block_d** %block.d, align 8
   %foo2 = tail call i8* @objc_retain(i8* %call) nounwind
   store i8* %foo2, i8** %foo, align 8
@@ -796,18 +794,18 @@ entry:
   %foo5 = call i8* @objc_retainBlock(i8* %foo4) nounwind
   call void @use(i8* %foo5), !clang.arc.no_objc_arc_exceptions !0
   call void @objc_release(i8* %foo5) nounwind
-  %strongdestroy = load i8** %foo, align 8
+  %strongdestroy = load i8*, i8** %foo, align 8
   call void @objc_release(i8* %strongdestroy) nounwind, !clang.imprecise_release !0
-  %foo10 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block9, i64 0, i32 5
-  %block.isa11 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block9, i64 0, i32 0
+  %foo10 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block9, i64 0, i32 5
+  %block.isa11 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block9, i64 0, i32 0
   store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** %block.isa11, align 8
-  %block.flags12 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block9, i64 0, i32 1
+  %block.flags12 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block9, i64 0, i32 1
   store i32 1107296256, i32* %block.flags12, align 8
-  %block.reserved13 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block9, i64 0, i32 2
+  %block.reserved13 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block9, i64 0, i32 2
   store i32 0, i32* %block.reserved13, align 4
-  %block.invoke14 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block9, i64 0, i32 3
+  %block.invoke14 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block9, i64 0, i32 3
   store i8* bitcast (void (i8*)* @__crasher_block_invoke1 to i8*), i8** %block.invoke14, align 8
-  %block.d15 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block9, i64 0, i32 4
+  %block.d15 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_d*, i8* }>* %block9, i64 0, i32 4
   store %struct.__block_d* bitcast ({ i64, i64, i8*, i8*, i8*, i8* }* @__block_d_tmp5 to %struct.__block_d*), %struct.__block_d** %block.d15, align 8
   %foo18 = call i8* @objc_retain(i8* %call) nounwind
   store i8* %call, i8** %foo10, align 8
@@ -815,7 +813,7 @@ entry:
   %foo21 = call i8* @objc_retainBlock(i8* %foo20) nounwind
   call void @use(i8* %foo21), !clang.arc.no_objc_arc_exceptions !0
   call void @objc_release(i8* %foo21) nounwind
-  %strongdestroy25 = load i8** %foo10, align 8
+  %strongdestroy25 = load i8*, i8** %foo10, align 8
   call void @objc_release(i8* %strongdestroy25) nounwind, !clang.imprecise_release !0
   call void @objc_release(i8* %call) nounwind, !clang.imprecise_release !0
   ret void
diff --git a/test/Transforms/ObjCARC/path-overflow.ll b/test/Transforms/ObjCARC/path-overflow.ll
index d23965310127..31f0e3b034b5 100644
--- a/test/Transforms/ObjCARC/path-overflow.ll
+++ b/test/Transforms/ObjCARC/path-overflow.ll
@@ -881,7 +881,7 @@ land.rhs:                                         ; preds = %invoke.cont4
           to label %land.end unwind label %lpad3
 
 land.end:                                         ; preds = %land.rhs, %invoke.cont4
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i unwind label %lpad.i
 
 invoke.cont.i:                                    ; preds = %land.end
@@ -896,7 +896,7 @@ lpad.i:                                           ; preds = %land.end
   unreachable
 
 invoke.cont8:                                     ; preds = %if.then.i, %invoke.cont.i
-  %call18 = invoke i8* (i8*, i8*, i8*, ...)* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*, i8*, ...)*)(i8* undef, i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef)
+  %call18 = invoke i8* (i8*, i8*, i8*, ...) bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*, i8*, ...)*)(i8* undef, i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef)
           to label %invoke.cont17 unwind label %lpad16
 
 invoke.cont17:                                    ; preds = %invoke.cont8
@@ -904,7 +904,7 @@ invoke.cont17:                                    ; preds = %invoke.cont8
           to label %invoke.cont21 unwind label %lpad20
 
 invoke.cont21:                                    ; preds = %invoke.cont17
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i1980 unwind label %lpad.i1982
 
 invoke.cont.i1980:                                ; preds = %invoke.cont21
@@ -930,7 +930,7 @@ land.rhs39:                                       ; preds = %invoke.cont36
           to label %land.end43 unwind label %lpad35
 
 land.end43:                                       ; preds = %land.rhs39, %invoke.cont36
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i1986 unwind label %lpad.i1988
 
 invoke.cont.i1986:                                ; preds = %land.end43
@@ -960,7 +960,7 @@ invoke.cont62:                                    ; preds = %land.rhs58
           to label %land.end70 unwind label %lpad66.body.thread
 
 land.end70:                                       ; preds = %invoke.cont62, %invoke.cont52
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i1992 unwind label %lpad66.body
 
 invoke.cont.i1992:                                ; preds = %land.end70
@@ -970,7 +970,7 @@ if.then.i1993:                                    ; preds = %invoke.cont.i1992
   br label %invoke.cont71
 
 invoke.cont71:                                    ; preds = %if.then.i1993, %invoke.cont.i1992
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i1998 unwind label %lpad.i2000
 
 invoke.cont.i1998:                                ; preds = %invoke.cont71
@@ -993,7 +993,7 @@ invoke.cont95:                                    ; preds = %invoke.cont91
           to label %invoke.cont97 unwind label %lpad94
 
 invoke.cont97:                                    ; preds = %invoke.cont95
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2004 unwind label %lpad.i2006
 
 invoke.cont.i2004:                                ; preds = %invoke.cont97
@@ -1012,7 +1012,7 @@ invoke.cont100:                                   ; preds = %if.then.i2005, %inv
           to label %invoke.cont110 unwind label %lpad109
 
 invoke.cont110:                                   ; preds = %invoke.cont100
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2010 unwind label %lpad.i2012
 
 invoke.cont.i2010:                                ; preds = %invoke.cont110
@@ -1027,7 +1027,7 @@ lpad.i2012:                                       ; preds = %invoke.cont110
   unreachable
 
 invoke.cont117:                                   ; preds = %if.then.i2011, %invoke.cont.i2010
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2022 unwind label %lpad156.body
 
 lpad:                                             ; preds = %entry
@@ -1101,7 +1101,7 @@ if.then.i2023:                                    ; preds = %invoke.cont.i2022
   br label %invoke.cont157
 
 invoke.cont157:                                   ; preds = %if.then.i2023, %invoke.cont.i2022
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2028 unwind label %lpad164.body
 
 invoke.cont.i2028:                                ; preds = %invoke.cont157
@@ -1119,7 +1119,7 @@ invoke.cont184:                                   ; preds = %invoke.cont165
           to label %invoke.cont185 unwind label %lpad183
 
 invoke.cont185:                                   ; preds = %invoke.cont184
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2034 unwind label %lpad.i2036
 
 invoke.cont.i2034:                                ; preds = %invoke.cont185
@@ -1146,7 +1146,7 @@ invoke.cont201:                                   ; preds = %invoke.cont197
           to label %invoke.cont204 unwind label %lpad203
 
 invoke.cont204:                                   ; preds = %invoke.cont201
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2040 unwind label %lpad.i2042
 
 invoke.cont.i2040:                                ; preds = %invoke.cont204
@@ -1165,7 +1165,7 @@ invoke.cont207:                                   ; preds = %if.then.i2041, %inv
           to label %invoke.cont208 unwind label %lpad203
 
 invoke.cont208:                                   ; preds = %invoke.cont207
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2046 unwind label %lpad212.body
 
 invoke.cont.i2046:                                ; preds = %invoke.cont208
@@ -1183,7 +1183,7 @@ invoke.cont221:                                   ; preds = %invoke.cont213
           to label %invoke.cont228 unwind label %lpad227
 
 invoke.cont228:                                   ; preds = %invoke.cont221
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2052 unwind label %lpad.i2054
 
 invoke.cont.i2052:                                ; preds = %invoke.cont228
@@ -1202,7 +1202,7 @@ invoke.cont231:                                   ; preds = %if.then.i2053, %inv
           to label %invoke.cont232 unwind label %lpad227
 
 invoke.cont232:                                   ; preds = %invoke.cont231
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2058 unwind label %lpad236.body
 
 invoke.cont.i2058:                                ; preds = %invoke.cont232
@@ -1248,7 +1248,7 @@ invoke.cont274:                                   ; preds = %invoke.cont266
           to label %invoke.cont278 unwind label %lpad277
 
 invoke.cont278:                                   ; preds = %invoke.cont274
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2064 unwind label %lpad.i2066
 
 invoke.cont.i2064:                                ; preds = %invoke.cont278
@@ -1294,7 +1294,7 @@ land.rhs335:                                      ; preds = %invoke.cont321
           to label %land.end344 unwind label %lpad340.body.thread
 
 land.end344:                                      ; preds = %land.rhs335, %invoke.cont321
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2070 unwind label %lpad340.body
 
 invoke.cont.i2070:                                ; preds = %land.end344
@@ -1316,7 +1316,7 @@ invoke.cont364:                                   ; preds = %invoke.cont361
           to label %invoke.cont370 unwind label %lpad369
 
 invoke.cont370:                                   ; preds = %invoke.cont364
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2076 unwind label %lpad.i2078
 
 invoke.cont.i2076:                                ; preds = %invoke.cont370
@@ -1343,7 +1343,7 @@ invoke.cont382:                                   ; preds = %invoke.cont376
           to label %invoke.cont383 unwind label %lpad381
 
 invoke.cont383:                                   ; preds = %invoke.cont382
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2082 unwind label %lpad.i2084
 
 invoke.cont.i2082:                                ; preds = %invoke.cont383
@@ -1374,7 +1374,7 @@ invoke.cont399:                                   ; preds = %invoke.cont396
           to label %invoke.cont402 unwind label %lpad401
 
 invoke.cont402:                                   ; preds = %invoke.cont399
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2088 unwind label %lpad.i2090
 
 invoke.cont.i2088:                                ; preds = %invoke.cont402
@@ -1401,7 +1401,7 @@ invoke.cont409:                                   ; preds = %invoke.cont408
           to label %invoke.cont412 unwind label %lpad411
 
 invoke.cont412:                                   ; preds = %invoke.cont409
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2094 unwind label %lpad.i2096
 
 invoke.cont.i2094:                                ; preds = %invoke.cont412
@@ -1432,7 +1432,7 @@ invoke.cont426:                                   ; preds = %invoke.cont423
           to label %invoke.cont429 unwind label %lpad428
 
 invoke.cont429:                                   ; preds = %invoke.cont426
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2100 unwind label %lpad.i2102
 
 invoke.cont.i2100:                                ; preds = %invoke.cont429
@@ -1451,7 +1451,7 @@ invoke.cont432:                                   ; preds = %if.then.i2101, %inv
           to label %invoke.cont435 unwind label %lpad381
 
 invoke.cont435:                                   ; preds = %invoke.cont432
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2106 unwind label %lpad.i2108
 
 invoke.cont.i2106:                                ; preds = %invoke.cont435
@@ -1464,7 +1464,7 @@ lpad.i2108:                                       ; preds = %invoke.cont435
   unreachable
 
 invoke.cont443:                                   ; preds = %invoke.cont.i2106
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2112 unwind label %lpad.i2114
 
 invoke.cont.i2112:                                ; preds = %invoke.cont443
@@ -1487,7 +1487,7 @@ invoke.cont452:                                   ; preds = %invoke.cont449
           to label %invoke.cont455 unwind label %lpad454
 
 invoke.cont455:                                   ; preds = %invoke.cont452
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2118 unwind label %lpad.i2120
 
 invoke.cont.i2118:                                ; preds = %invoke.cont455
@@ -1506,7 +1506,7 @@ invoke.cont458:                                   ; preds = %if.then.i2119, %inv
           to label %invoke.cont460 unwind label %lpad381
 
 invoke.cont460:                                   ; preds = %invoke.cont458
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2124 unwind label %lpad.i2126
 
 invoke.cont.i2124:                                ; preds = %invoke.cont460
@@ -1525,7 +1525,7 @@ invoke.cont466:                                   ; preds = %if.then.i2125, %inv
           to label %invoke.cont469 unwind label %lpad381
 
 invoke.cont469:                                   ; preds = %invoke.cont466
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2130 unwind label %lpad.i2132
 
 invoke.cont.i2130:                                ; preds = %invoke.cont469
@@ -1574,7 +1574,7 @@ msgSend.null-receiver:                            ; preds = %invoke.cont512
   br label %msgSend.cont
 
 msgSend.cont:                                     ; preds = %msgSend.null-receiver, %msgSend.call
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2136 unwind label %lpad.i2138
 
 invoke.cont.i2136:                                ; preds = %msgSend.cont
@@ -1601,7 +1601,7 @@ invoke.cont531:                                   ; preds = %invoke.cont528
           to label %invoke.cont534 unwind label %lpad533
 
 invoke.cont534:                                   ; preds = %invoke.cont531
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* undef, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2142 unwind label %lpad.i2144
 
 invoke.cont.i2142:                                ; preds = %invoke.cont534
@@ -1633,7 +1633,7 @@ invoke.cont548:                                   ; preds = %invoke.cont546
 
 invoke.cont554:                                   ; preds = %invoke.cont548
   %tmp499 = call i8* @objc_retain(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*)) #3
-  invoke void (i8*, ...)* @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* %tmp499, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
+  invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*), i8* %tmp499, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring to i8*))
           to label %invoke.cont.i2148 unwind label %lpad.i2150
 
 invoke.cont.i2148:                                ; preds = %invoke.cont554
diff --git a/test/Transforms/ObjCARC/provenance.ll b/test/Transforms/ObjCARC/provenance.ll
index 937c68924357..aa5a932a86e9 100644
--- a/test/Transforms/ObjCARC/provenance.ll
+++ b/test/Transforms/ObjCARC/provenance.ll
@@ -10,28 +10,28 @@
 declare void @g(i8)
 
 define void @f(i8* %a, i8** %b, i8** %c) {
-  %y1 = load i8* %a
+  %y1 = load i8, i8* %a
   call void @g(i8 %y1)
 
-  %y2 = load i8** %b
-  %y3 = load i8** %c
+  %y2 = load i8*, i8** %b
+  %y3 = load i8*, i8** %c
 
-  %x0 = load i8* @"\01l_objc_msgSend_fixup_"
+  %x0 = load i8, i8* @"\01l_objc_msgSend_fixup_"
   call void @g(i8 %x0)
 
-  %x1 = load i8* @g1
+  %x1 = load i8, i8* @g1
   call void @g(i8 %x1)
 
-  %x2 = load i8* @g2
+  %x2 = load i8, i8* @g2
   call void @g(i8 %x2)
 
-  %x3 = load i8* @g3
+  %x3 = load i8, i8* @g3
   call void @g(i8 %x3)
 
-  %x4 = load i8* @g4
+  %x4 = load i8, i8* @g4
   call void @g(i8 %x4)
 
-  %x5 = load i8* @g5
+  %x5 = load i8, i8* @g5
   call void @g(i8 %x5)
   ret void
 }
diff --git a/test/Transforms/ObjCARC/retain-block-side-effects.ll b/test/Transforms/ObjCARC/retain-block-side-effects.ll
index 7fa73cbfef15..5f5def9ff036 100644
--- a/test/Transforms/ObjCARC/retain-block-side-effects.ll
+++ b/test/Transforms/ObjCARC/retain-block-side-effects.ll
@@ -6,8 +6,8 @@
 
 ; CHECK: %tmp16 = call i8* @objc_retainBlock(i8* %tmp15) [[NUW:#[0-9]+]]
 ; CHECK: %tmp17 = bitcast i8* %tmp16 to void ()*
-; CHECK: %tmp18 = load %struct.__block_byref_repeater** %byref.forwarding, align 8
-; CHECK: %repeater12 = getelementptr inbounds %struct.__block_byref_repeater* %tmp18, i64 0, i32 6
+; CHECK: %tmp18 = load %struct.__block_byref_repeater*, %struct.__block_byref_repeater** %byref.forwarding, align 8
+; CHECK: %repeater12 = getelementptr inbounds %struct.__block_byref_repeater, %struct.__block_byref_repeater* %tmp18, i64 0, i32 6
 ; CHECK: store void ()* %tmp17, void ()** %repeater12, align 8
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
@@ -20,18 +20,18 @@ define void @foo() noreturn {
 entry:
   %repeater = alloca %struct.__block_byref_repeater, align 8
   %block = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0*, i8* }>, align 8
-  %byref.forwarding = getelementptr inbounds %struct.__block_byref_repeater* %repeater, i64 0, i32 1
-  %tmp10 = getelementptr inbounds %struct.__block_byref_repeater* %repeater, i64 0, i32 6
+  %byref.forwarding = getelementptr inbounds %struct.__block_byref_repeater, %struct.__block_byref_repeater* %repeater, i64 0, i32 1
+  %tmp10 = getelementptr inbounds %struct.__block_byref_repeater, %struct.__block_byref_repeater* %repeater, i64 0, i32 6
   store void ()* null, void ()** %tmp10, align 8
-  %block.captured11 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0*, i8* }>* %block, i64 0, i32 6
+  %block.captured11 = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0*, i8* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0*, i8* }>* %block, i64 0, i32 6
   %tmp14 = bitcast %struct.__block_byref_repeater* %repeater to i8*
   store i8* %tmp14, i8** %block.captured11, align 8
   %tmp15 = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0*, i8* }>* %block to i8*
   %tmp16 = call i8* @objc_retainBlock(i8* %tmp15) nounwind
   %tmp17 = bitcast i8* %tmp16 to void ()*
-  %tmp18 = load %struct.__block_byref_repeater** %byref.forwarding, align 8
-  %repeater12 = getelementptr inbounds %struct.__block_byref_repeater* %tmp18, i64 0, i32 6
-  %tmp13 = load void ()** %repeater12, align 8
+  %tmp18 = load %struct.__block_byref_repeater*, %struct.__block_byref_repeater** %byref.forwarding, align 8
+  %repeater12 = getelementptr inbounds %struct.__block_byref_repeater, %struct.__block_byref_repeater* %tmp18, i64 0, i32 6
+  %tmp13 = load void ()*, void ()** %repeater12, align 8
   store void ()* %tmp17, void ()** %repeater12, align 8
   ret void
 }
diff --git a/test/Transforms/ObjCARC/weak-copies.ll b/test/Transforms/ObjCARC/weak-copies.ll
index 13d0b0a0c6b7..d3177bb727fc 100644
--- a/test/Transforms/ObjCARC/weak-copies.ll
+++ b/test/Transforms/ObjCARC/weak-copies.ll
@@ -10,9 +10,9 @@ target triple = "x86_64-apple-darwin11.0.0"
 @_NSConcreteStackBlock = external global i8*
 @.str = private unnamed_addr constant [6 x i8] c"v8@?0\00"
 @"\01L_OBJC_CLASS_NAME_" = internal global [3 x i8] c"\01@\00", section "__TEXT,__objc_classname,cstring_literals", align 1
-@__block_descriptor_tmp = internal constant %0 { i64 0, i64 40, i8* bitcast (void (i8*, i8*)* @__copy_helper_block_ to i8*), i8* bitcast (void (i8*)* @__destroy_helper_block_ to i8*), i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([3 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0) }
+@__block_descriptor_tmp = internal constant %0 { i64 0, i64 40, i8* bitcast (void (i8*, i8*)* @__copy_helper_block_ to i8*), i8* bitcast (void (i8*)* @__destroy_helper_block_ to i8*), i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0) }
 @"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] [i32 0, i32 16], section "__DATA, __objc_imageinfo, regular, no_dead_strip"
-@llvm.used = appending global [2 x i8*] [i8* getelementptr inbounds ([3 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*)], section "llvm.metadata"
+@llvm.used = appending global [2 x i8*] [i8* getelementptr inbounds ([3 x i8], [3 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*)], section "llvm.metadata"
 
 ; Eliminate unnecessary weak pointer copies.
 
@@ -50,17 +50,17 @@ entry:
   %block = alloca %1, align 8
   %0 = call i8* @objc_retain(i8* %me) nounwind
   %1 = call i8* @objc_initWeak(i8** %w, i8* %0) nounwind
-  %block.isa = getelementptr inbounds %1* %block, i64 0, i32 0
+  %block.isa = getelementptr inbounds %1, %1* %block, i64 0, i32 0
   store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** %block.isa, align 8
-  %block.flags = getelementptr inbounds %1* %block, i64 0, i32 1
+  %block.flags = getelementptr inbounds %1, %1* %block, i64 0, i32 1
   store i32 1107296256, i32* %block.flags, align 8
-  %block.reserved = getelementptr inbounds %1* %block, i64 0, i32 2
+  %block.reserved = getelementptr inbounds %1, %1* %block, i64 0, i32 2
   store i32 0, i32* %block.reserved, align 4
-  %block.invoke = getelementptr inbounds %1* %block, i64 0, i32 3
+  %block.invoke = getelementptr inbounds %1, %1* %block, i64 0, i32 3
   store i8* bitcast (void (i8*)* @__qux_block_invoke_0 to i8*), i8** %block.invoke, align 8
-  %block.descriptor = getelementptr inbounds %1* %block, i64 0, i32 4
+  %block.descriptor = getelementptr inbounds %1, %1* %block, i64 0, i32 4
   store %struct.__block_descriptor* bitcast (%0* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** %block.descriptor, align 8
-  %block.captured = getelementptr inbounds %1* %block, i64 0, i32 5
+  %block.captured = getelementptr inbounds %1, %1* %block, i64 0, i32 5
   %2 = call i8* @objc_loadWeak(i8** %w) nounwind
   %3 = call i8* @objc_initWeak(i8** %block.captured, i8* %2) nounwind
   %4 = bitcast %1* %block to void ()*
diff --git a/test/Transforms/PhaseOrdering/2010-03-22-empty-baseclass.ll b/test/Transforms/PhaseOrdering/2010-03-22-empty-baseclass.ll
index 53d98e02ec88..13404a8b6a71 100644
--- a/test/Transforms/PhaseOrdering/2010-03-22-empty-baseclass.ll
+++ b/test/Transforms/PhaseOrdering/2010-03-22-empty-baseclass.ll
@@ -29,29 +29,29 @@ entry:
   store %struct.empty_base_t* %4, %struct.empty_base_t** %2, align 8
   call void @_ZN7empty_tC1Ev(%struct.empty_base_t* %1) nounwind
   %5 = call i32* @_ZN5boost15compressed_pairI7empty_tiE6secondEv(%"struct.boost::compressed_pair<empty_t,int>"* %x) ssp ; <i32*> [#uses=1]
-  %6 = load i32* %5, align 4                      ; <i32> [#uses=1]
+  %6 = load i32, i32* %5, align 4                      ; <i32> [#uses=1]
   %7 = icmp ne i32 %6, -3                         ; <i1> [#uses=1]
   %8 = zext i1 %7 to i8                           ; <i8> [#uses=1]
   store i8 %8, i8* %retval.1, align 1
-  %9 = load i8* %retval.1, align 1                ; <i8> [#uses=1]
+  %9 = load i8, i8* %retval.1, align 1                ; <i8> [#uses=1]
   %toBool = icmp ne i8 %9, 0                      ; <i1> [#uses=1]
   br i1 %toBool, label %bb, label %bb1
 
 bb:                                               ; preds = %entry
-  %10 = call i32 @puts(i8* getelementptr inbounds ([25 x i8]* @.str, i64 0, i64 0)) ; <i32> [#uses=0]
+  %10 = call i32 @puts(i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i64 0, i64 0)) ; <i32> [#uses=0]
   call void @abort() noreturn
   unreachable
 
 bb1:                                              ; preds = %entry
   store i32 0, i32* %0, align 4
-  %11 = load i32* %0, align 4                     ; <i32> [#uses=1]
+  %11 = load i32, i32* %0, align 4                     ; <i32> [#uses=1]
   store i32 %11, i32* %retval, align 4
   br label %return
 
 ; CHECK-NOT: x.second() was clobbered
 ; CHECK: ret i32
 return:                                           ; preds = %bb1
-  %retval2 = load i32* %retval                    ; <i32> [#uses=1]
+  %retval2 = load i32, i32* %retval                    ; <i32> [#uses=1]
   ret i32 %retval2
 }
 
@@ -71,7 +71,7 @@ entry:
   %this_addr = alloca %struct.empty_base_t*, align 8 ; <%struct.empty_base_t**> [#uses=2]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   store %struct.empty_base_t* %this, %struct.empty_base_t** %this_addr
-  %0 = load %struct.empty_base_t** %this_addr, align 8 ; <%struct.empty_base_t*> [#uses=1]
+  %0 = load %struct.empty_base_t*, %struct.empty_base_t** %this_addr, align 8 ; <%struct.empty_base_t*> [#uses=1]
   call void @_ZN12empty_base_tC2Ev(%struct.empty_base_t* %0) nounwind
   br label %return
 
@@ -86,15 +86,15 @@ entry:
   %0 = alloca i32*                                ; <i32**> [#uses=2]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   store %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %this, %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"** %this_addr
-  %1 = load %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"** %this_addr, align 8 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
-  %2 = getelementptr inbounds %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %1, i32 0, i32 0 ; <i32*> [#uses=1]
+  %1 = load %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*, %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"** %this_addr, align 8 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
+  %2 = getelementptr inbounds %"struct.boost::details::compressed_pair_imp<empty_t,int,1>", %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %1, i32 0, i32 0 ; <i32*> [#uses=1]
   store i32* %2, i32** %0, align 8
-  %3 = load i32** %0, align 8                     ; <i32*> [#uses=1]
+  %3 = load i32*, i32** %0, align 8                     ; <i32*> [#uses=1]
   store i32* %3, i32** %retval, align 8
   br label %return
 
 return:                                           ; preds = %entry
-  %retval1 = load i32** %retval                   ; <i32*> [#uses=1]
+  %retval1 = load i32*, i32** %retval                   ; <i32*> [#uses=1]
   ret i32* %retval1
 }
 
@@ -105,16 +105,16 @@ entry:
   %0 = alloca i32*                                ; <i32**> [#uses=2]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   store %"struct.boost::compressed_pair<empty_t,int>"* %this, %"struct.boost::compressed_pair<empty_t,int>"** %this_addr
-  %1 = load %"struct.boost::compressed_pair<empty_t,int>"** %this_addr, align 8 ; <%"struct.boost::compressed_pair<empty_t,int>"*> [#uses=1]
-  %2 = getelementptr inbounds %"struct.boost::compressed_pair<empty_t,int>"* %1, i32 0, i32 0 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
+  %1 = load %"struct.boost::compressed_pair<empty_t,int>"*, %"struct.boost::compressed_pair<empty_t,int>"** %this_addr, align 8 ; <%"struct.boost::compressed_pair<empty_t,int>"*> [#uses=1]
+  %2 = getelementptr inbounds %"struct.boost::compressed_pair<empty_t,int>", %"struct.boost::compressed_pair<empty_t,int>"* %1, i32 0, i32 0 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
   %3 = call i32* @_ZN5boost7details19compressed_pair_impI7empty_tiLi1EE6secondEv(%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %2) nounwind ; <i32*> [#uses=1]
   store i32* %3, i32** %0, align 8
-  %4 = load i32** %0, align 8                     ; <i32*> [#uses=1]
+  %4 = load i32*, i32** %0, align 8                     ; <i32*> [#uses=1]
   store i32* %4, i32** %retval, align 8
   br label %return
 
 return:                                           ; preds = %entry
-  %retval1 = load i32** %retval                   ; <i32*> [#uses=1]
+  %retval1 = load i32*, i32** %retval                   ; <i32*> [#uses=1]
   ret i32* %retval1
 }
 
@@ -125,15 +125,15 @@ entry:
   %0 = alloca %struct.empty_base_t*               ; <%struct.empty_base_t**> [#uses=2]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   store %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %this, %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"** %this_addr
-  %1 = load %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"** %this_addr, align 8 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
+  %1 = load %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*, %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"** %this_addr, align 8 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
   %2 = bitcast %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %1 to %struct.empty_base_t* ; <%struct.empty_base_t*> [#uses=1]
   store %struct.empty_base_t* %2, %struct.empty_base_t** %0, align 8
-  %3 = load %struct.empty_base_t** %0, align 8    ; <%struct.empty_base_t*> [#uses=1]
+  %3 = load %struct.empty_base_t*, %struct.empty_base_t** %0, align 8    ; <%struct.empty_base_t*> [#uses=1]
   store %struct.empty_base_t* %3, %struct.empty_base_t** %retval, align 8
   br label %return
 
 return:                                           ; preds = %entry
-  %retval1 = load %struct.empty_base_t** %retval  ; <%struct.empty_base_t*> [#uses=1]
+  %retval1 = load %struct.empty_base_t*, %struct.empty_base_t** %retval  ; <%struct.empty_base_t*> [#uses=1]
   ret %struct.empty_base_t* %retval1
 }
 
@@ -144,16 +144,16 @@ entry:
   %0 = alloca %struct.empty_base_t*               ; <%struct.empty_base_t**> [#uses=2]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   store %"struct.boost::compressed_pair<empty_t,int>"* %this, %"struct.boost::compressed_pair<empty_t,int>"** %this_addr
-  %1 = load %"struct.boost::compressed_pair<empty_t,int>"** %this_addr, align 8 ; <%"struct.boost::compressed_pair<empty_t,int>"*> [#uses=1]
-  %2 = getelementptr inbounds %"struct.boost::compressed_pair<empty_t,int>"* %1, i32 0, i32 0 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
+  %1 = load %"struct.boost::compressed_pair<empty_t,int>"*, %"struct.boost::compressed_pair<empty_t,int>"** %this_addr, align 8 ; <%"struct.boost::compressed_pair<empty_t,int>"*> [#uses=1]
+  %2 = getelementptr inbounds %"struct.boost::compressed_pair<empty_t,int>", %"struct.boost::compressed_pair<empty_t,int>"* %1, i32 0, i32 0 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
   %3 = call %struct.empty_base_t* @_ZN5boost7details19compressed_pair_impI7empty_tiLi1EE5firstEv(%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %2) nounwind ; <%struct.empty_base_t*> [#uses=1]
   store %struct.empty_base_t* %3, %struct.empty_base_t** %0, align 8
-  %4 = load %struct.empty_base_t** %0, align 8    ; <%struct.empty_base_t*> [#uses=1]
+  %4 = load %struct.empty_base_t*, %struct.empty_base_t** %0, align 8    ; <%struct.empty_base_t*> [#uses=1]
   store %struct.empty_base_t* %4, %struct.empty_base_t** %retval, align 8
   br label %return
 
 return:                                           ; preds = %entry
-  %retval1 = load %struct.empty_base_t** %retval  ; <%struct.empty_base_t*> [#uses=1]
+  %retval1 = load %struct.empty_base_t*, %struct.empty_base_t** %retval  ; <%struct.empty_base_t*> [#uses=1]
   ret %struct.empty_base_t* %retval1
 }
 
diff --git a/test/Transforms/PhaseOrdering/PR6627.ll b/test/Transforms/PhaseOrdering/PR6627.ll
index cf95363e655a..2774d208352c 100644
--- a/test/Transforms/PhaseOrdering/PR6627.ll
+++ b/test/Transforms/PhaseOrdering/PR6627.ll
@@ -8,42 +8,42 @@ declare i32 @doo(...)
 define void @test2(i8* %arrayidx) nounwind ssp {
 entry:
   %xx = bitcast i8* %arrayidx to i32*
-  %x1 = load i32* %xx, align 4
+  %x1 = load i32, i32* %xx, align 4
   %tmp = trunc i32 %x1 to i8
   %conv = zext i8 %tmp to i32
   %cmp = icmp eq i32 %conv, 127
   br i1 %cmp, label %land.lhs.true, label %if.end
 
 land.lhs.true:                                    ; preds = %entry
-  %arrayidx4 = getelementptr inbounds i8* %arrayidx, i64 1
-  %tmp5 = load i8* %arrayidx4, align 1
+  %arrayidx4 = getelementptr inbounds i8, i8* %arrayidx, i64 1
+  %tmp5 = load i8, i8* %arrayidx4, align 1
   %conv6 = zext i8 %tmp5 to i32
   %cmp7 = icmp eq i32 %conv6, 69
   br i1 %cmp7, label %land.lhs.true9, label %if.end
 
 land.lhs.true9:                                   ; preds = %land.lhs.true
-  %arrayidx12 = getelementptr inbounds i8* %arrayidx, i64 2
-  %tmp13 = load i8* %arrayidx12, align 1
+  %arrayidx12 = getelementptr inbounds i8, i8* %arrayidx, i64 2
+  %tmp13 = load i8, i8* %arrayidx12, align 1
   %conv14 = zext i8 %tmp13 to i32
   %cmp15 = icmp eq i32 %conv14, 76
   br i1 %cmp15, label %land.lhs.true17, label %if.end
 
 land.lhs.true17:                                  ; preds = %land.lhs.true9
-  %arrayidx20 = getelementptr inbounds i8* %arrayidx, i64 3
-  %tmp21 = load i8* %arrayidx20, align 1
+  %arrayidx20 = getelementptr inbounds i8, i8* %arrayidx, i64 3
+  %tmp21 = load i8, i8* %arrayidx20, align 1
   %conv22 = zext i8 %tmp21 to i32
   %cmp23 = icmp eq i32 %conv22, 70
   br i1 %cmp23, label %if.then, label %if.end
 
 if.then:                                          ; preds = %land.lhs.true17
-  %call25 = call i32 (...)* @doo()
+  %call25 = call i32 (...) @doo()
   br label %if.end
 
 if.end:
   ret void
 
 ; CHECK-LABEL: @test2(
-; CHECK: %x1 = load i32* %xx, align 4
+; CHECK: %x1 = load i32, i32* %xx, align 4
 ; CHECK-NEXT: icmp eq i32 %x1, 1179403647
 ; CHECK-NEXT: br i1 {{.*}}, label %if.then, label %if.end 
 }
@@ -53,41 +53,41 @@ if.end:
 ; requiring widening.
 define void @test2a(i8* %arrayidx) nounwind ssp {
 entry:
-  %x1 = load i8* %arrayidx, align 4
+  %x1 = load i8, i8* %arrayidx, align 4
   %conv = zext i8 %x1 to i32
   %cmp = icmp eq i32 %conv, 127
   br i1 %cmp, label %land.lhs.true, label %if.end
 
 land.lhs.true:                                    ; preds = %entry
-  %arrayidx4 = getelementptr inbounds i8* %arrayidx, i64 1
-  %tmp5 = load i8* %arrayidx4, align 1
+  %arrayidx4 = getelementptr inbounds i8, i8* %arrayidx, i64 1
+  %tmp5 = load i8, i8* %arrayidx4, align 1
   %conv6 = zext i8 %tmp5 to i32
   %cmp7 = icmp eq i32 %conv6, 69
   br i1 %cmp7, label %land.lhs.true9, label %if.end
 
 land.lhs.true9:                                   ; preds = %land.lhs.true
-  %arrayidx12 = getelementptr inbounds i8* %arrayidx, i64 2
-  %tmp13 = load i8* %arrayidx12, align 1
+  %arrayidx12 = getelementptr inbounds i8, i8* %arrayidx, i64 2
+  %tmp13 = load i8, i8* %arrayidx12, align 1
   %conv14 = zext i8 %tmp13 to i32
   %cmp15 = icmp eq i32 %conv14, 76
   br i1 %cmp15, label %land.lhs.true17, label %if.end
 
 land.lhs.true17:                                  ; preds = %land.lhs.true9
-  %arrayidx20 = getelementptr inbounds i8* %arrayidx, i64 3
-  %tmp21 = load i8* %arrayidx20, align 1
+  %arrayidx20 = getelementptr inbounds i8, i8* %arrayidx, i64 3
+  %tmp21 = load i8, i8* %arrayidx20, align 1
   %conv22 = zext i8 %tmp21 to i32
   %cmp23 = icmp eq i32 %conv22, 70
   br i1 %cmp23, label %if.then, label %if.end
 
 if.then:                                          ; preds = %land.lhs.true17
-  %call25 = call i32 (...)* @doo()
+  %call25 = call i32 (...) @doo()
   br label %if.end
 
 if.end:
   ret void
 
 ; CHECK-LABEL: @test2a(
-; CHECK: %x1 = load i32* {{.*}}, align 4
+; CHECK: %x1 = load i32, i32* {{.*}}, align 4
 ; CHECK-NEXT: icmp eq i32 %x1, 1179403647
 ; CHECK-NEXT: br i1 {{.*}}, label %if.then, label %if.end 
 }
diff --git a/test/Transforms/PhaseOrdering/basic.ll b/test/Transforms/PhaseOrdering/basic.ll
index 2deefa618109..ef57e55e15e3 100644
--- a/test/Transforms/PhaseOrdering/basic.ll
+++ b/test/Transforms/PhaseOrdering/basic.ll
@@ -13,9 +13,9 @@ define void @test1() nounwind ssp {
   %i = alloca i8*, align 8
   %call = call i8* @malloc(i64 1)
   store i8* %call, i8** %i, align 8
-  %tmp = load i8** %i, align 8
+  %tmp = load i8*, i8** %i, align 8
   store i8 1, i8* %tmp
-  %tmp1 = load i8** %i, align 8
+  %tmp1 = load i8*, i8** %i, align 8
   call void @free(i8* %tmp1)
   ret void
 
@@ -31,15 +31,15 @@ define void @test1() nounwind ssp {
 define i32 @test2(i32 %a, i32* %p) nounwind uwtable ssp {
 entry:
   %div = udiv i32 %a, 4
-  %arrayidx = getelementptr inbounds i32* %p, i64 0
+  %arrayidx = getelementptr inbounds i32, i32* %p, i64 0
   store i32 %div, i32* %arrayidx, align 4
   %add = add i32 %div, %div
-  %arrayidx1 = getelementptr inbounds i32* %p, i64 1
+  %arrayidx1 = getelementptr inbounds i32, i32* %p, i64 1
   store i32 %add, i32* %arrayidx1, align 4
-  %arrayidx2 = getelementptr inbounds i32* %p, i64 1
-  %0 = load i32* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds i32* %p, i64 0
-  %1 = load i32* %arrayidx3, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %p, i64 1
+  %0 = load i32, i32* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %p, i64 0
+  %1 = load i32, i32* %arrayidx3, align 4
   %mul = mul i32 2, %1
   %sub = sub i32 %0, %mul
   ret i32 %sub
diff --git a/test/Transforms/PhaseOrdering/gdce.ll b/test/Transforms/PhaseOrdering/gdce.ll
index 95f06757a788..6f79eb815832 100644
--- a/test/Transforms/PhaseOrdering/gdce.ll
+++ b/test/Transforms/PhaseOrdering/gdce.ll
@@ -15,7 +15,7 @@
 @_ZTV4Base = linkonce_odr unnamed_addr constant [4 x i8*] [i8* null, i8* bitcast ({ i8*, i8* }* @_ZTI4Base to i8*), i8* bitcast (void (%class.Base*)* @_ZN4BaseD1Ev to i8*), i8* bitcast (void (%class.Base*)* @_ZN4BaseD0Ev to i8*)]
 @_ZTVN10__cxxabiv117__class_type_infoE = external global i8*
 @_ZTS4Base = linkonce_odr constant [6 x i8] c"4Base\00"
-@_ZTI4Base = linkonce_odr unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([6 x i8]* @_ZTS4Base, i32 0, i32 0) }
+@_ZTI4Base = linkonce_odr unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([6 x i8], [6 x i8]* @_ZTS4Base, i32 0, i32 0) }
 
 define i32 @main() uwtable ssp {
 entry:
@@ -27,7 +27,7 @@ entry:
   store i32 0, i32* %retval
   store i32 1, i32* %cleanup.dest.slot
   call void @_ZN4BaseD1Ev(%class.Base* %b)
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -35,7 +35,7 @@ define linkonce_odr void @_ZN4BaseC1Ev(%class.Base* %this) unnamed_addr uwtable
 entry:
   %this.addr = alloca %class.Base*, align 8
   store %class.Base* %this, %class.Base** %this.addr, align 8
-  %this1 = load %class.Base** %this.addr
+  %this1 = load %class.Base*, %class.Base** %this.addr
   call void @_ZN4BaseC2Ev(%class.Base* %this1)
   ret void
 }
@@ -44,7 +44,7 @@ define linkonce_odr void @_ZN4BaseD1Ev(%class.Base* %this) unnamed_addr uwtable
 entry:
   %this.addr = alloca %class.Base*, align 8
   store %class.Base* %this, %class.Base** %this.addr, align 8
-  %this1 = load %class.Base** %this.addr
+  %this1 = load %class.Base*, %class.Base** %this.addr
   call void @_ZN4BaseD2Ev(%class.Base* %this1)
   ret void
 }
@@ -53,7 +53,7 @@ define linkonce_odr void @_ZN4BaseD2Ev(%class.Base* %this) unnamed_addr nounwind
 entry:
   %this.addr = alloca %class.Base*, align 8
   store %class.Base* %this, %class.Base** %this.addr, align 8
-  %this1 = load %class.Base** %this.addr
+  %this1 = load %class.Base*, %class.Base** %this.addr
   ret void
 }
 
@@ -61,9 +61,9 @@ define linkonce_odr void @_ZN4BaseC2Ev(%class.Base* %this) unnamed_addr nounwind
 entry:
   %this.addr = alloca %class.Base*, align 8
   store %class.Base* %this, %class.Base** %this.addr, align 8
-  %this1 = load %class.Base** %this.addr
+  %this1 = load %class.Base*, %class.Base** %this.addr
   %0 = bitcast %class.Base* %this1 to i8***
-  store i8** getelementptr inbounds ([4 x i8*]* @_ZTV4Base, i64 0, i64 2), i8*** %0
+  store i8** getelementptr inbounds ([4 x i8*], [4 x i8*]* @_ZTV4Base, i64 0, i64 2), i8*** %0
   ret void
 }
 
@@ -73,7 +73,7 @@ entry:
   %exn.slot = alloca i8*
   %ehselector.slot = alloca i32
   store %class.Base* %this, %class.Base** %this.addr, align 8
-  %this1 = load %class.Base** %this.addr
+  %this1 = load %class.Base*, %class.Base** %this.addr
   invoke void @_ZN4BaseD1Ev(%class.Base* %this1)
           to label %invoke.cont unwind label %lpad
 
@@ -94,8 +94,8 @@ lpad:                                             ; preds = %entry
   br label %eh.resume
 
 eh.resume:                                        ; preds = %lpad
-  %exn = load i8** %exn.slot
-  %sel = load i32* %ehselector.slot
+  %exn = load i8*, i8** %exn.slot
+  %sel = load i32, i32* %ehselector.slot
   %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn, 0
   %lpad.val2 = insertvalue { i8*, i32 } %lpad.val, i32 %sel, 1
   resume { i8*, i32 } %lpad.val2
diff --git a/test/Transforms/PhaseOrdering/scev.ll b/test/Transforms/PhaseOrdering/scev.ll
index 39adb6b73d3a..c616ca2d7684 100644
--- a/test/Transforms/PhaseOrdering/scev.ll
+++ b/test/Transforms/PhaseOrdering/scev.ll
@@ -7,7 +7,7 @@
 ; CHECK: test1
 ; The loop body contains two increments by %div.
 ; Make sure that 2*%div is recognizable, and not expressed as a bit mask of %d.
-; CHECK: -->  {%p,+,(2 * (%d /u 4) * sizeof(i32))}
+; CHECK: -->  {%p,+,(8 * (%d /u 4))}
 define void @test1(i64 %d, i32* %p) nounwind uwtable ssp {
 entry:
   %div = udiv i64 %d, 4
@@ -21,9 +21,9 @@ for.cond:                                         ; preds = %for.inc, %entry
 
 for.body:                                         ; preds = %for.cond
   store i32 0, i32* %p.addr.0, align 4
-  %add.ptr = getelementptr inbounds i32* %p.addr.0, i64 %div
+  %add.ptr = getelementptr inbounds i32, i32* %p.addr.0, i64 %div
   store i32 1, i32* %add.ptr, align 4
-  %add.ptr1 = getelementptr inbounds i32* %add.ptr, i64 %div
+  %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i64 %div
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
@@ -36,7 +36,7 @@ for.end:                                          ; preds = %for.cond
 
 ; CHECK: test1a
 ; Same thing as test1, but it is even more tempting to fold 2 * (%d /u 2)
-; CHECK: -->  {%p,+,(2 * (%d /u 2) * sizeof(i32))}
+; CHECK: -->  {%p,+,(8 * (%d /u 2))}
 define void @test1a(i64 %d, i32* %p) nounwind uwtable ssp {
 entry:
   %div = udiv i64 %d, 2
@@ -50,9 +50,9 @@ for.cond:                                         ; preds = %for.inc, %entry
 
 for.body:                                         ; preds = %for.cond
   store i32 0, i32* %p.addr.0, align 4
-  %add.ptr = getelementptr inbounds i32* %p.addr.0, i64 %div
+  %add.ptr = getelementptr inbounds i32, i32* %p.addr.0, i64 %div
   store i32 1, i32* %add.ptr, align 4
-  %add.ptr1 = getelementptr inbounds i32* %add.ptr, i64 %div
+  %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i64 %div
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
diff --git a/test/Transforms/PlaceSafepoints/basic.ll b/test/Transforms/PlaceSafepoints/basic.ll
new file mode 100644
index 000000000000..32aa4da68f21
--- /dev/null
+++ b/test/Transforms/PlaceSafepoints/basic.ll
@@ -0,0 +1,94 @@
+; RUN: opt %s -S -place-safepoints | FileCheck %s
+
+
+; Do we insert a simple entry safepoint?
+define void @test_entry() gc "statepoint-example" {
+; CHECK-LABEL: @test_entry
+entry:
+; CHECK-LABEL: entry
+; CHECK: statepoint
+  ret void
+}
+
+; On a non-gc function, we should NOT get an entry safepoint
+define void @test_negative() {
+; CHECK-LABEL: @test_negative
+entry:
+; CHECK-NOT: statepoint
+  ret void
+}
+
+; Do we insert a backedge safepoint in a statically
+; infinite loop?
+define void @test_backedge() gc "statepoint-example" {
+; CHECK-LABEL: test_backedge
+entry:
+; CHECK-LABEL: entry
+; This statepoint is technically not required, but we don't exploit that yet.
+; CHECK: statepoint
+  br label %other
+
+; CHECK-LABEL: other
+; CHECK: statepoint
+other:
+  call void undef()
+  br label %other
+}
+
+; Check that we remove an unreachable block rather than trying
+; to insert a backedge safepoint
+define void @test_unreachable() gc "statepoint-example" {
+; CHECK-LABEL: test_unreachable
+entry:
+; CHECK-LABEL: entry
+; CHECK: statepoint
+  ret void
+
+; CHECK-NOT: other
+; CHECK-NOT: statepoint
+other:
+  br label %other
+}
+
+declare void @foo()
+
+; Do we turn a call into it's own statepoint
+define void @test_simple_call() gc "statepoint-example" {
+; CHECK-LABEL: test_simple_call
+entry:
+  br label %other
+other:
+; CHECK-LABEL: other
+; CHECK: statepoint
+; CHECK-NOT: gc.result
+  call void @foo()
+  ret void
+}
+
+declare zeroext i1 @i1_return_i1(i1)
+
+define i1 @test_call_with_result() gc "statepoint-example" {
+; CHECK-LABEL: test_call_with_result
+; This is checking that a statepoint_poll + statepoint + result is
+; inserted for a function that takes 1 argument.
+; CHECK: gc.statepoint.p0f_isVoidf
+; CHECK: gc.statepoint.p0f_i1i1f
+; CHECK: (i64 2882400000, i32 0, i1 (i1)* @i1_return_i1, i32 1, i32 0, i1 false, i32 0, i32 0)
+; CHECK: %call1.2 = call i1 @llvm.experimental.gc.result.i1
+entry:
+  %call1 = tail call i1 (i1) @i1_return_i1(i1 false)
+  ret i1 %call1
+}
+
+; This function is inlined when inserting a poll.  To avoid recursive 
+; issues, make sure we don't place safepoints in it.
+declare void @do_safepoint()
+define void @gc.safepoint_poll() {
+; CHECK-LABEL: gc.safepoint_poll
+; CHECK-LABEL: entry
+; CHECK-NEXT: do_safepoint
+; CHECK-NEXT: ret void 
+entry:
+  call void @do_safepoint()
+  ret void
+}
diff --git a/test/Transforms/PlaceSafepoints/call-in-loop.ll b/test/Transforms/PlaceSafepoints/call-in-loop.ll
new file mode 100644
index 000000000000..9edfeb75e0c4
--- /dev/null
+++ b/test/Transforms/PlaceSafepoints/call-in-loop.ll
@@ -0,0 +1,31 @@
+; If there's a call in the loop which dominates the backedge, we 
+; don't need a safepoint poll (since the callee must contain a 
+; poll test).
+;; RUN: opt %s -place-safepoints -S | FileCheck %s
+
+declare void @foo()
+
+define void @test1() gc "statepoint-example" {
+; CHECK-LABEL: test1
+
+entry:
+; CHECK-LABEL: entry
+; CHECK: statepoint
+  br label %loop
+
+loop:
+; CHECK-LABEL: loop
+; CHECK: @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @foo
+; CHECK-NOT: statepoint
+  call void @foo()
+  br label %loop
+}
+
+; This function is inlined when inserting a poll.
+declare void @do_safepoint()
+define void @gc.safepoint_poll() {
+; CHECK-LABEL: gc.safepoint_poll
+entry:
+  call void @do_safepoint()
+  ret void
+}
diff --git a/test/Transforms/PlaceSafepoints/call_gc_result.ll b/test/Transforms/PlaceSafepoints/call_gc_result.ll
new file mode 100644
index 000000000000..d78a0989c3b1
--- /dev/null
+++ b/test/Transforms/PlaceSafepoints/call_gc_result.ll
@@ -0,0 +1,38 @@
+;; RUN: opt %s -place-safepoints -S | FileCheck %s
+
+;; This test is to verify that gc_result from a call statepoint
+;; can have preceding phis in its parent basic block. Unlike
+;; invoke statepoint, call statepoint does not terminate the
+;; block, and thus its gc_result is in the same block with the
+;; call statepoint.
+
+declare i32 @foo()
+
+define i32 @test1(i1 %cond, i32 %a) gc "statepoint-example" {
+entry:
+  br i1 %cond, label %branch1, label %branch2
+  
+branch1:
+  %b = add i32 %a, 1
+  br label %merge
+ 
+branch2:
+  br label %merge
+
+merge:
+;; CHECK: 		%phi = phi i32 [ %a, %branch2 ], [ %b, %branch1 ]
+;; CHECK-NEXT:  %safepoint_token.1 = call i32 (i64, i32, i32 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i32f(i64 2882400000, i32 0, i32 ()* @foo, i32 0, i32 0, i32 0, i32 0)
+;; CHECK-NEXT:  %ret.2 = call i32 @llvm.experimental.gc.result.i32(i32 %safepoint_token.1)
+  %phi = phi i32 [ %a, %branch2 ], [ %b, %branch1 ]
+  %ret = call i32 @foo()
+  ret i32 %ret
+}
+
+; This function is inlined when inserting a poll.
+declare void @do_safepoint()
+define void @gc.safepoint_poll() {
+; CHECK-LABEL: gc.safepoint_poll
+entry:
+  call void @do_safepoint()
+  ret void
+}
diff --git a/test/Transforms/PlaceSafepoints/finite-loops.ll b/test/Transforms/PlaceSafepoints/finite-loops.ll
new file mode 100644
index 000000000000..3cc7158afcfe
--- /dev/null
+++ b/test/Transforms/PlaceSafepoints/finite-loops.ll
@@ -0,0 +1,80 @@
+; Tests to ensure that we are not placing backedge safepoints in
+; loops which are clearly finite.
+;; RUN: opt %s -place-safepoints -S | FileCheck %s
+
+
+; A simple counted loop with trivially known range
+define void @test1(i32) gc "statepoint-example" {
+; CHECK-LABEL: test1
+; CHECK-LABEL: entry
+; CHECK: statepoint
+; CHECK-LABEL: loop
+; CHECK-NOT: statepoint
+
+entry:
+  br label %loop
+
+loop:
+  %counter = phi i32 [ 0 , %entry ], [ %counter.inc , %loop ]
+  %counter.inc = add i32 %counter, 1
+  %counter.cmp = icmp slt i32 %counter.inc, 16
+  br i1 %counter.cmp, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+; The same counted loop, but with an unknown early exit
+define void @test2(i32) gc "statepoint-example" {
+; CHECK-LABEL: test2
+; CHECK-LABEL: entry
+; CHECK: statepoint
+; CHECK-LABEL: loop
+; CHECK-NOT: statepoint
+
+entry:
+  br label %loop
+
+loop:
+  %counter = phi i32 [ 0 , %entry ], [ %counter.inc , %continue ]
+  %counter.inc = add i32 %counter, 1
+  %counter.cmp = icmp slt i32 %counter.inc, 16
+  br i1 undef, label %continue, label %exit
+
+continue:
+  br i1 %counter.cmp, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+; The range is a 8 bit value and we can't overflow
+define void @test3(i8 %upper) gc "statepoint-example" {
+; CHECK-LABEL: test3
+; CHECK-LABEL: entry
+; CHECK: statepoint
+; CHECK-LABEL: loop
+; CHECK-NOT: statepoint
+
+entry:
+  br label %loop
+
+loop:
+  %counter = phi i8 [ 0 , %entry ], [ %counter.inc , %loop ]
+  %counter.inc = add nsw i8 %counter, 1
+  %counter.cmp = icmp slt i8 %counter.inc, %upper
+  br i1 %counter.cmp, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+
+; This function is inlined when inserting a poll.
+declare void @do_safepoint()
+define void @gc.safepoint_poll() {
+; CHECK-LABEL: gc.safepoint_poll
+entry:
+  call void @do_safepoint()
+  ret void
+}
\ No newline at end of file
diff --git a/test/Transforms/PlaceSafepoints/invokes.ll b/test/Transforms/PlaceSafepoints/invokes.ll
new file mode 100644
index 000000000000..913e148d9bcc
--- /dev/null
+++ b/test/Transforms/PlaceSafepoints/invokes.ll
@@ -0,0 +1,111 @@
+; RUN: opt %s -S -place-safepoints | FileCheck %s
+
+declare i64 addrspace(1)* @"some_call"(i64 addrspace(1)*)
+declare i32 @"personality_function"()
+
+define i64 addrspace(1)* @test_basic(i64 addrspace(1)* %obj, i64 addrspace(1)* %obj1) gc "statepoint-example" {
+; CHECK-LABEL: entry:
+entry:
+  ; CHECK: invoke
+  ; CHECK: statepoint
+  ; CHECK: some_call
+  %ret_val = invoke i64 addrspace(1)* @"some_call"(i64 addrspace(1)* %obj)
+               to label %normal_return unwind label %exceptional_return
+
+; CHECK-LABEL: normal_return:
+; CHECK: gc.result
+; CHECK: ret i64
+
+normal_return:
+  ret i64 addrspace(1)* %ret_val
+
+; CHECK-LABEL: exceptional_return:
+; CHECK: landingpad
+; CHECK: ret i64
+
+exceptional_return:
+  %landing_pad4 = landingpad {i8*, i32} personality i32 ()* @"personality_function"
+          cleanup
+  ret i64 addrspace(1)* %obj1
+}
+
+define i64 addrspace(1)* @test_two_invokes(i64 addrspace(1)* %obj, i64 addrspace(1)* %obj1) gc "statepoint-example" {
+; CHECK-LABEL: entry:
+entry:
+  ; CHECK: invoke 
+  ; CHECK: statepoint
+  ; CHECK: some_call
+  %ret_val1 = invoke i64 addrspace(1)* @"some_call"(i64 addrspace(1)* %obj)
+               to label %second_invoke unwind label %exceptional_return
+
+; CHECK-LABEL: second_invoke:
+second_invoke:
+  ; CHECK: invoke
+  ; CHECK: statepoint
+  ; CHECK: some_call
+  %ret_val2 = invoke i64 addrspace(1)* @"some_call"(i64 addrspace(1)* %ret_val1)
+                to label %normal_return unwind label %exceptional_return
+
+; CHECK-LABEL: normal_return:
+normal_return:
+  ; CHECK: gc.result
+  ; CHECK: ret i64
+  ret i64 addrspace(1)* %ret_val2
+
+; CHECK: exceptional_return:
+; CHECK: ret i64
+
+exceptional_return:
+  %landing_pad4 = landingpad {i8*, i32} personality i32 ()* @"personality_function"
+          cleanup
+  ret i64 addrspace(1)* %obj1
+}
+
+define i64 addrspace(1)* @test_phi_node(i1 %cond, i64 addrspace(1)* %obj) gc "statepoint-example" {
+; CHECK-LABEL: @test_phi_node
+; CHECK-LABEL: entry:
+entry:
+  br i1 %cond, label %left, label %right
+
+left:
+  %ret_val_left = invoke i64 addrspace(1)* @"some_call"(i64 addrspace(1)* %obj)
+                    to label %merge unwind label %exceptional_return
+
+right:
+  %ret_val_right = invoke i64 addrspace(1)* @"some_call"(i64 addrspace(1)* %obj)
+                     to label %merge unwind label %exceptional_return
+
+; CHECK: merge[[A:[0-9]]]:
+; CHECK: gc.result
+; CHECK: br label %[[with_phi:merge[0-9]*]]
+
+; CHECK: merge[[B:[0-9]]]:
+; CHECK: gc.result
+; CHECK: br label %[[with_phi]]
+
+; CHECK: [[with_phi]]:
+; CHECK: phi
+; CHECK: ret i64 addrspace(1)* %ret_val
+merge:
+  %ret_val = phi i64 addrspace(1)* [%ret_val_left, %left], [%ret_val_right, %right]
+  ret i64 addrspace(1)* %ret_val
+
+; CHECK-LABEL: exceptional_return:
+; CHECK: ret i64 addrspace(1)*
+
+exceptional_return:
+  %landing_pad4 = landingpad {i8*, i32} personality i32 ()* @"personality_function"
+          cleanup
+  ret i64 addrspace(1)* %obj
+}
+
+declare void @do_safepoint()
+define void @gc.safepoint_poll() {
+; CHECK-LABEL: gc.safepoint_poll
+; CHECK-LABEL: entry
+; CHECK-NEXT: do_safepoint
+; CHECK-NEXT: ret void 
+entry:
+  call void @do_safepoint()
+  ret void
+}
\ No newline at end of file
diff --git a/test/Transforms/PlaceSafepoints/memset.ll b/test/Transforms/PlaceSafepoints/memset.ll
new file mode 100644
index 000000000000..534b2f120581
--- /dev/null
+++ b/test/Transforms/PlaceSafepoints/memset.ll
@@ -0,0 +1,20 @@
+; RUN: opt -S -place-safepoints %s | FileCheck %s
+
+define void @test(i32, i8 addrspace(1)* %ptr) gc "statepoint-example" {
+; CHECK-LABEL: @test
+; CHECK-NEXT: llvm.memset
+; CHECK: do_safepoint
+; CHECK: @foo
+  call void @llvm.memset.p1i8.i64(i8 addrspace(1)* %ptr, i8 0, i64 24, i32 8, i1 false)
+  call void @foo()
+  ret void
+}
+
+declare void @foo()
+declare void @llvm.memset.p1i8.i64(i8 addrspace(1)*, i8, i64, i32, i1)
+
+declare void @do_safepoint()
+define void @gc.safepoint_poll() {
+  call void @do_safepoint()
+  ret void
+}
diff --git a/test/Transforms/PlaceSafepoints/patchable-statepoints.ll b/test/Transforms/PlaceSafepoints/patchable-statepoints.ll
new file mode 100644
index 000000000000..ac0aa29e5049
--- /dev/null
+++ b/test/Transforms/PlaceSafepoints/patchable-statepoints.ll
@@ -0,0 +1,44 @@
+; RUN: opt -place-safepoints -S < %s | FileCheck %s
+
+declare void @f()
+declare i32 @personality_function()
+
+define void @test_id() gc "statepoint-example" {
+; CHECK-LABEL: @test_id(
+entry:
+; CHECK-LABEL: entry:
+; CHECK: invoke i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 100, i32 0, void ()* @f
+  invoke void @f()  "statepoint-id"="100" to label %normal_return unwind label %exceptional_return
+
+normal_return:
+  ret void
+
+exceptional_return:
+  %landing_pad4 = landingpad {i8*, i32} personality i32 ()* @personality_function cleanup
+  ret void
+}
+
+define void @test_num_patch_bytes() gc "statepoint-example" {
+; CHECK-LABEL: @test_num_patch_bytes(
+entry:
+; CHECK-LABEL: entry:
+; CHECK: invoke i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 99, void ()* null,
+  invoke void @f()  "statepoint-num-patch-bytes"="99" to label %normal_return unwind label %exceptional_return
+
+normal_return:
+  ret void
+
+exceptional_return:
+  %landing_pad4 = landingpad {i8*, i32} personality i32 ()* @personality_function cleanup
+  ret void
+}
+
+declare void @do_safepoint()
+define void @gc.safepoint_poll() {
+entry:
+  call void @do_safepoint()
+  ret void
+}
+
+; CHECK-NOT: statepoint-id
+; CHECK-NOT: statepoint-num-patch_bytes
diff --git a/test/Transforms/PlaceSafepoints/split-backedge.ll b/test/Transforms/PlaceSafepoints/split-backedge.ll
new file mode 100644
index 000000000000..b9fad45709d0
--- /dev/null
+++ b/test/Transforms/PlaceSafepoints/split-backedge.ll
@@ -0,0 +1,46 @@
+;; A very basic test to make sure that splitting the backedge keeps working
+;; RUN: opt -place-safepoints -spp-split-backedge=1 -S %s | FileCheck %s
+
+define void @test(i32, i1 %cond) gc "statepoint-example" {
+; CHECK-LABEL: @test
+; CHECK-LABEL: loop.loop_crit_edge
+; CHECK: gc.statepoint
+; CHECK-NEXT: br label %loop
+entry:
+  br label %loop
+
+loop:
+  br i1 %cond, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+; Test for the case where a single conditional branch jumps to two
+; different loop header blocks.  Since we're currently using LoopSimplfy
+; this doesn't hit the interesting case, but once we remove that, we need
+; to be sure this keeps working.
+define void @test2(i32, i1 %cond) gc "statepoint-example" {
+; CHECK-LABEL: @test2
+; CHECK-LABEL: loop2.loop2_crit_edge:
+; CHECK: gc.statepoint
+; CHECK-NEXT: br label %loop2
+; CHECK-LABEL: loop2.loop_crit_edge:
+; CHECK: gc.statepoint
+; CHECK-NEXT: br label %loop
+entry:
+  br label %loop
+
+loop:
+  br label %loop2
+
+loop2:
+  br i1 %cond, label %loop, label %loop2
+}
+
+declare void @do_safepoint()
+define void @gc.safepoint_poll() {
+entry:
+  call void @do_safepoint()
+  ret void
+}
\ No newline at end of file
diff --git a/test/Transforms/PlaceSafepoints/statepoint-calling-conventions.ll b/test/Transforms/PlaceSafepoints/statepoint-calling-conventions.ll
new file mode 100644
index 000000000000..e31c2aa5166a
--- /dev/null
+++ b/test/Transforms/PlaceSafepoints/statepoint-calling-conventions.ll
@@ -0,0 +1,42 @@
+; RUN: opt -place-safepoints -S < %s | FileCheck %s
+
+; Ensure that the gc.statepoint calls / invokes we generate carry over
+; the right calling conventions.
+
+define i64 addrspace(1)* @test_invoke_format(i64 addrspace(1)* %obj, i64 addrspace(1)* %obj1) gc "statepoint-example" {
+; CHECK-LABEL: @test_invoke_format(
+; CHECK-LABEL: entry:
+; CHECK: invoke coldcc i32 (i64, i32, i64 addrspace(1)* (i64 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_p1i64p1i64f(i64 2882400000, i32 0, i64 addrspace(1)* (i64 addrspace(1)*)* @callee, i32 1, i32 0, i64 addrspace(1)* %obj, i32 0, i32 0)
+entry:
+  %ret_val = invoke coldcc i64 addrspace(1)* @callee(i64 addrspace(1)* %obj)
+               to label %normal_return unwind label %exceptional_return
+
+normal_return:
+  ret i64 addrspace(1)* %ret_val
+
+exceptional_return:
+  %landing_pad4 = landingpad {i8*, i32} personality i32 ()* @personality
+          cleanup
+  ret i64 addrspace(1)* %obj1
+}
+
+define i64 addrspace(1)* @test_call_format(i64 addrspace(1)* %obj, i64 addrspace(1)* %obj1) gc "statepoint-example" {
+; CHECK-LABEL: @test_call_format(
+; CHECK-LABEL: entry:
+; CHECK: call coldcc i32 (i64, i32, i64 addrspace(1)* (i64 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_p1i64p1i64f(i64 2882400000, i32 0, i64 addrspace(1)* (i64 addrspace(1)*)* @callee, i32 1, i32 0, i64 addrspace(1)* %obj, i32 0, i32 0)
+entry:
+  %ret_val = call coldcc i64 addrspace(1)* @callee(i64 addrspace(1)* %obj)
+  ret i64 addrspace(1)* %ret_val
+}
+
+; This function is inlined when inserting a poll.
+declare void @do_safepoint()
+define void @gc.safepoint_poll() {
+; CHECK-LABEL: gc.safepoint_poll
+entry:
+  call void @do_safepoint()
+  ret void
+}
+
+declare coldcc i64 addrspace(1)* @callee(i64 addrspace(1)*)
+declare i32 @personality()
diff --git a/test/Transforms/PlaceSafepoints/statepoint-coreclr.ll b/test/Transforms/PlaceSafepoints/statepoint-coreclr.ll
new file mode 100644
index 000000000000..dc468966877f
--- /dev/null
+++ b/test/Transforms/PlaceSafepoints/statepoint-coreclr.ll
@@ -0,0 +1,31 @@
+; RUN: opt %s -S -place-safepoints | FileCheck %s

+

+; Basic test to make sure that safepoints are placed

+; for CoreCLR GC

+

+declare void @foo()

+

+define void @test_simple_call() gc "coreclr" {

+; CHECK-LABEL: test_simple_call

+entry:

+  br label %other

+other:

+; CHECK-LABEL: other

+; CHECK: statepoint

+; CHECK-NOT: gc.result

+  call void @foo()

+  ret void

+}

+

+; This function is inlined when inserting a poll.  To avoid recursive

+; issues, make sure we don't place safepoints in it.

+declare void @do_safepoint()

+define void @gc.safepoint_poll() {

+; CHECK-LABEL: gc.safepoint_poll

+; CHECK-LABEL: entry

+; CHECK-NEXT: do_safepoint

+; CHECK-NEXT: ret void

+entry:

+  call void @do_safepoint()

+  ret void

+}

diff --git a/test/Transforms/PlaceSafepoints/statepoint-format.ll b/test/Transforms/PlaceSafepoints/statepoint-format.ll
new file mode 100644
index 000000000000..328b670873eb
--- /dev/null
+++ b/test/Transforms/PlaceSafepoints/statepoint-format.ll
@@ -0,0 +1,42 @@
+; RUN: opt -place-safepoints -S < %s | FileCheck %s
+
+; Ensure that the gc.statepoint calls / invokes we generate have the
+; set of arguments we expect it to have.
+
+define i64 addrspace(1)* @test_invoke_format(i64 addrspace(1)* %obj, i64 addrspace(1)* %obj1) gc "statepoint-example" {
+; CHECK-LABEL: @test_invoke_format(
+; CHECK-LABEL: entry:
+; CHECK: invoke i32 (i64, i32, i64 addrspace(1)* (i64 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_p1i64p1i64f(i64 2882400000, i32 0, i64 addrspace(1)* (i64 addrspace(1)*)* @callee, i32 1, i32 0, i64 addrspace(1)* %obj, i32 0, i32 0)
+entry:
+  %ret_val = invoke i64 addrspace(1)* @callee(i64 addrspace(1)* %obj)
+               to label %normal_return unwind label %exceptional_return
+
+normal_return:
+  ret i64 addrspace(1)* %ret_val
+
+exceptional_return:
+  %landing_pad4 = landingpad {i8*, i32} personality i32 ()* @personality
+          cleanup
+  ret i64 addrspace(1)* %obj1
+}
+
+define i64 addrspace(1)* @test_call_format(i64 addrspace(1)* %obj, i64 addrspace(1)* %obj1) gc "statepoint-example" {
+; CHECK-LABEL: @test_call_format(
+; CHECK-LABEL: entry:
+; CHECK: call i32 (i64, i32, i64 addrspace(1)* (i64 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_p1i64p1i64f(i64 2882400000, i32 0, i64 addrspace(1)* (i64 addrspace(1)*)* @callee, i32 1, i32 0, i64 addrspace(1)* %obj, i32 0, i32 0)
+entry:
+  %ret_val = call i64 addrspace(1)* @callee(i64 addrspace(1)* %obj)
+  ret i64 addrspace(1)* %ret_val
+}
+
+; This function is inlined when inserting a poll.
+declare void @do_safepoint()
+define void @gc.safepoint_poll() {
+; CHECK-LABEL: gc.safepoint_poll
+entry:
+  call void @do_safepoint()
+  ret void
+}
+
+declare i64 addrspace(1)* @callee(i64 addrspace(1)*)
+declare i32 @personality()
diff --git a/test/Transforms/PlaceSafepoints/statepoint-frameescape.ll b/test/Transforms/PlaceSafepoints/statepoint-frameescape.ll
new file mode 100644
index 000000000000..a6ee5ee078fb
--- /dev/null
+++ b/test/Transforms/PlaceSafepoints/statepoint-frameescape.ll
@@ -0,0 +1,29 @@
+; RUN: opt %s -S -place-safepoints | FileCheck %s
+
+declare void @llvm.frameescape(...)
+
+; Do we insert the entry safepoint after the frameescape intrinsic?
+define void @parent() gc "statepoint-example" {
+; CHECK-LABEL: @parent
+entry:
+; CHECK-LABEL: entry
+; CHECK-NEXT: alloca
+; CHECK-NEXT: frameescape
+; CHECK-NEXT: statepoint
+  %ptr = alloca i32
+  call void (...) @llvm.frameescape(i32* %ptr)
+  ret void
+}
+
+; This function is inlined when inserting a poll.  To avoid recursive 
+; issues, make sure we don't place safepoints in it.
+declare void @do_safepoint()
+define void @gc.safepoint_poll() {
+; CHECK-LABEL: gc.safepoint_poll
+; CHECK-LABEL: entry
+; CHECK-NEXT: do_safepoint
+; CHECK-NEXT: ret void 
+entry:
+  call void @do_safepoint()
+  ret void
+}
\ No newline at end of file
diff --git a/test/Transforms/PruneEH/2003-11-21-PHIUpdate.ll b/test/Transforms/PruneEH/2003-11-21-PHIUpdate.ll
deleted file mode 100644
index a01070308bed..000000000000
--- a/test/Transforms/PruneEH/2003-11-21-PHIUpdate.ll
+++ /dev/null
@@ -1,15 +0,0 @@
-; RUN: opt < %s -prune-eh -disable-output
-
-define internal void @callee() {
-	ret void
-}
-
-define i32 @caller() {
-; <label>:0
-	invoke void @callee( )
-			to label %E unwind label %E
-E:		; preds = %0, %0
-	%X = phi i32 [ 0, %0 ], [ 0, %0 ]		; <i32> [#uses=1]
-	ret i32 %X
-}
-
diff --git a/test/Transforms/PruneEH/recursivetest.ll b/test/Transforms/PruneEH/recursivetest.ll
index 724c7cf224c1..bc002ae70d3b 100644
--- a/test/Transforms/PruneEH/recursivetest.ll
+++ b/test/Transforms/PruneEH/recursivetest.ll
@@ -6,6 +6,8 @@ define internal i32 @foo() {
 Normal:		; preds = %0
 	ret i32 12
 Except:		; preds = %0
+        landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
+                catch i8* null
 	ret i32 123
 }
 
@@ -15,6 +17,9 @@ define i32 @caller() {
 Normal:		; preds = %0
 	ret i32 0
 Except:		; preds = %0
+        landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
+                catch i8* null
 	ret i32 1
 }
 
+declare i32 @__gxx_personality_v0(...)
diff --git a/test/Transforms/PruneEH/seh-nounwind.ll b/test/Transforms/PruneEH/seh-nounwind.ll
new file mode 100644
index 000000000000..4b69ae4b28dd
--- /dev/null
+++ b/test/Transforms/PruneEH/seh-nounwind.ll
@@ -0,0 +1,31 @@
+; RUN: opt -S -prune-eh < %s | FileCheck %s
+
+; Don't remove invokes of nounwind functions if the personality handles async
+; exceptions. The @div function in this test can fault, even though it can't
+; throw a synchronous exception.
+
+define i32 @div(i32 %n, i32 %d) nounwind {
+entry:
+  %div = sdiv i32 %n, %d
+  ret i32 %div
+}
+
+define i32 @main() nounwind {
+entry:
+  %call = invoke i32 @div(i32 10, i32 0)
+          to label %__try.cont unwind label %lpad
+
+lpad:
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+          catch i8* null
+  br label %__try.cont
+
+__try.cont:
+  %retval.0 = phi i32 [ %call, %entry ], [ 0, %lpad ]
+  ret i32 %retval.0
+}
+
+; CHECK-LABEL: define i32 @main()
+; CHECK: invoke i32 @div(i32 10, i32 0)
+
+declare i32 @__C_specific_handler(...)
diff --git a/test/Transforms/PruneEH/simpletest.ll b/test/Transforms/PruneEH/simpletest.ll
index 77c429dae6d6..6154a80b68a3 100644
--- a/test/Transforms/PruneEH/simpletest.ll
+++ b/test/Transforms/PruneEH/simpletest.ll
@@ -15,5 +15,9 @@ Normal:		; preds = %0
 	ret i32 0
 
 Except:		; preds = %0
+        landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
+                catch i8* null
 	ret i32 1
 }
+
+declare i32 @__gxx_personality_v0(...)
diff --git a/test/Transforms/Reassociate/2011-01-26-UseAfterFree.ll b/test/Transforms/Reassociate/2011-01-26-UseAfterFree.ll
index 003fbb1b3bb3..1c8f0d2ea219 100644
--- a/test/Transforms/Reassociate/2011-01-26-UseAfterFree.ll
+++ b/test/Transforms/Reassociate/2011-01-26-UseAfterFree.ll
@@ -5,7 +5,7 @@ target triple = "i386-gnu-linux"
 
 define void @exp_averages_intraday__deviation() {
 entry:
-  %0 = load i32* undef, align 4
+  %0 = load i32, i32* undef, align 4
   %1 = shl i32 %0, 2
   %2 = add nsw i32 undef, %1
   %3 = add nsw i32 %2, undef
@@ -22,7 +22,7 @@ entry:
   unreachable
 
 "8":                                              ; preds = %"4"
-  %8 = getelementptr inbounds i8* undef, i32 %6
+  %8 = getelementptr inbounds i8, i8* undef, i32 %6
   br i1 undef, label %"13", label %"12"
 
 "12":                                             ; preds = %"8", %entry
diff --git a/test/Transforms/Reassociate/basictest.ll b/test/Transforms/Reassociate/basictest.ll
index 0194ce2e302c..015d3b0bee9f 100644
--- a/test/Transforms/Reassociate/basictest.ll
+++ b/test/Transforms/Reassociate/basictest.ll
@@ -28,9 +28,9 @@ define i32 @test2(i32 %reg109, i32 %reg1111) {
 @f = external global i32
 
 define void @test3() {
-  %A = load i32* @a
-  %B = load i32* @b
-  %C = load i32* @c
+  %A = load i32, i32* @a
+  %B = load i32, i32* @b
+  %C = load i32, i32* @c
   %t1 = add i32 %A, %B
   %t2 = add i32 %t1, %C
   %t3 = add i32 %C, %A
@@ -49,9 +49,9 @@ define void @test3() {
 }
 
 define void @test4() {
-  %A = load i32* @a
-  %B = load i32* @b
-  %C = load i32* @c
+  %A = load i32, i32* @a
+  %B = load i32, i32* @b
+  %C = load i32, i32* @c
   %t1 = add i32 %A, %B
   %t2 = add i32 %t1, %C
   %t3 = add i32 %C, %A
@@ -70,9 +70,9 @@ define void @test4() {
 }
 
 define void @test5() {
-  %A = load i32* @a
-  %B = load i32* @b
-  %C = load i32* @c
+  %A = load i32, i32* @a
+  %B = load i32, i32* @b
+  %C = load i32, i32* @c
   %t1 = add i32 %B, %A
   %t2 = add i32 %t1, %C
   %t3 = add i32 %C, %A
@@ -91,11 +91,11 @@ define void @test5() {
 }
 
 define i32 @test6() {
-  %tmp.0 = load i32* @a
-  %tmp.1 = load i32* @b
+  %tmp.0 = load i32, i32* @a
+  %tmp.1 = load i32, i32* @b
   ; (a+b)
   %tmp.2 = add i32 %tmp.0, %tmp.1
-  %tmp.4 = load i32* @c
+  %tmp.4 = load i32, i32* @c
   ; (a+b)+c
   %tmp.5 = add i32 %tmp.2, %tmp.4
   ; (a+c)
diff --git a/test/Transforms/Reassociate/crash.ll b/test/Transforms/Reassociate/crash.ll
index 770f97371d7e..f8774ea509a4 100644
--- a/test/Transforms/Reassociate/crash.ll
+++ b/test/Transforms/Reassociate/crash.ll
@@ -17,7 +17,7 @@ for.cond:                                         ; preds = %for.body, %entry
 ; PR5981
 define i32 @test2() nounwind ssp {
 entry:
-  %0 = load i32* undef, align 4
+  %0 = load i32, i32* undef, align 4
   %1 = mul nsw i32 undef, %0
   %2 = mul nsw i32 undef, %0
   %3 = add nsw i32 undef, %1
@@ -50,7 +50,7 @@ _:
   br label %_33
 
 _33:                                              ; preds = %_33, %_
-  %tmp348 = load i8* %arg, align 1
+  %tmp348 = load i8, i8* %arg, align 1
   %tmp349 = lshr i8 %tmp348, 7
   %tmp350 = or i8 %tmp349, 42
   %tmp351 = add i8 %tmp350, -42
@@ -123,7 +123,7 @@ for.cond:                                         ; preds = %for.cond, %entry
 ; PR12963
 @a = external global i8
 define i8 @f0(i8 %x) {
-  %t0 = load i8* @a
+  %t0 = load i8, i8* @a
   %t1 = mul i8 %x, %x
   %t2 = mul i8 %t1, %t1
   %t3 = mul i8 %t2, %t2
diff --git a/test/Transforms/Reassociate/crash2.ll b/test/Transforms/Reassociate/crash2.ll
new file mode 100644
index 000000000000..b51a88ca674d
--- /dev/null
+++ b/test/Transforms/Reassociate/crash2.ll
@@ -0,0 +1,25 @@
+; RUN: opt -reassociate %s -S -o - | FileCheck %s
+
+; Reassociate pass used to crash on these example
+
+
+define float @undef1() {
+wrapper_entry:
+; CHECK-LABEL: @undef1
+; CHECK: ret float fadd (float undef, float fadd (float undef, float fadd (float fsub (float -0.000000e+00, float undef), float fsub (float -0.000000e+00, float undef))))
+  %0 = fadd fast float undef, undef
+  %1 = fsub fast float undef, %0
+  %2 = fadd fast float undef, %1
+  ret float %2
+}
+
+define void @undef2() {
+wrapper_entry:
+; CHECK-LABEL: @undef2
+; CHECK: unreachable
+  %0 = fadd fast float undef, undef
+  %1 = fadd fast float %0, 1.000000e+00
+  %2 = fsub fast float %0, %1
+  %3 = fmul fast float %2, 2.000000e+00
+  unreachable
+}
diff --git a/test/Transforms/Reassociate/fast-ReassociateVector.ll b/test/Transforms/Reassociate/fast-ReassociateVector.ll
index eeae096bf944..9fbb5ccfe9a2 100644
--- a/test/Transforms/Reassociate/fast-ReassociateVector.ll
+++ b/test/Transforms/Reassociate/fast-ReassociateVector.ll
@@ -1,46 +1,192 @@
 ; RUN: opt < %s -reassociate -S | FileCheck %s
 
-; Canonicalize operands, but don't optimize floating point vector operations.
-define <4 x float> @test1() {
-; CHECK-LABEL: test1
-; CHECK-NEXT: %tmp1 = fsub fast <4 x float> zeroinitializer, zeroinitializer
-; CHECK-NEXT: %tmp2 = fmul fast <4 x float> %tmp1, zeroinitializer
-
-  %tmp1 = fsub fast <4 x float> zeroinitializer, zeroinitializer
-  %tmp2 = fmul fast <4 x float> zeroinitializer, %tmp1
-  ret <4 x float> %tmp2
-}
-
-; Commute integer vector operations.
-define <2 x i32> @test2(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: test2
-; CHECK-NEXT: %tmp1 = add <2 x i32> %x, %y
-; CHECK-NEXT: %tmp2 = add <2 x i32> %x, %y
-; CHECK-NEXT: %tmp3 = add <2 x i32> %tmp1, %tmp2
-
-  %tmp1 = add <2 x i32> %x, %y
-  %tmp2 = add <2 x i32> %y, %x
-  %tmp3 = add <2 x i32> %tmp1, %tmp2
-  ret <2 x i32> %tmp3
+; Check that a*c+b*c is turned into (a+b)*c
+define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
+; CHECK-LABEL: @test1
+; CHECK-NEXT: %tmp = fadd fast <4 x float> %b, %a
+; CHECK-NEXT: %tmp1 = fmul fast <4 x float> %tmp, %c
+; CHECK-NEXT: ret <4 x float> %tmp1
+
+  %mul = fmul fast <4 x float> %a, %c
+  %mul1 = fmul fast <4 x float> %b, %c
+  %add = fadd fast <4 x float> %mul, %mul1
+  ret <4 x float> %add
 }
 
-define <2 x i32> @test3(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: test3
-; CHECK-NEXT: %tmp1 = mul <2 x i32> %x, %y
-; CHECK-NEXT: %tmp2 = mul <2 x i32> %x, %y
-; CHECK-NEXT: %tmp3 = mul <2 x i32> %tmp1, %tmp2
+; Check that a*a*b+a*a*c is turned into a*(a*(b+c)).
+define <2 x float> @test2(<2 x float> %a, <2 x float> %b, <2 x float> %c) {
+; CHECK-LABEL: @test2
+; CHECK-NEXT: fadd fast <2 x float> %c, %b
+; CHECK-NEXT: fmul fast <2 x float> %a, %tmp2
+; CHECK-NEXT: fmul fast <2 x float> %tmp3, %a
+; CHECK-NEXT: ret <2 x float>
 
-  %tmp1 = mul <2 x i32> %x, %y
-  %tmp2 = mul <2 x i32> %y, %x
-  %tmp3 = mul <2 x i32> %tmp1, %tmp2
-  ret <2 x i32> %tmp3
+  %t0 = fmul fast <2 x float> %a, %b
+  %t1 = fmul fast <2 x float> %a, %t0
+  %t2 = fmul fast <2 x float> %a, %c
+  %t3 = fmul fast <2 x float> %a, %t2
+  %t4 = fadd fast <2 x float> %t1, %t3
+  ret <2 x float> %t4
+}
+
+; Check that a*b+a*c+d is turned into a*(b+c)+d.
+define <2 x double> @test3(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
+; CHECK-LABEL: @test3
+; CHECK-NEXT: fadd fast <2 x double> %c, %b
+; CHECK-NEXT: fmul fast <2 x double> %tmp, %a
+; CHECK-NEXT: fadd fast <2 x double> %tmp1, %d
+; CHECK-NEXT: ret <2 x double>
+
+  %t0 = fmul fast <2 x double> %a, %b
+  %t1 = fmul fast <2 x double> %a, %c
+  %t2 = fadd fast <2 x double> %t1, %d
+  %t3 = fadd fast <2 x double> %t0, %t2
+  ret <2 x double> %t3
+}
+
+; No fast-math.
+define <2 x float> @test4(<2 x float> %A) {
+; CHECK-LABEL: @test4
+; CHECK-NEXT: %X = fadd <2 x float> %A, <float 1.000000e+00, float 1.000000e+00>
+; CHECK-NEXT: %Y = fadd <2 x float> %A, <float 1.000000e+00, float 1.000000e+00>
+; CHECK-NEXT: %R = fsub <2 x float> %X, %Y
+; CHECK-NEXT: ret <2 x float> %R
+
+  %X = fadd <2 x float> %A, < float 1.000000e+00, float 1.000000e+00 >
+  %Y = fadd <2 x float> %A, < float 1.000000e+00, float 1.000000e+00 >
+  %R = fsub <2 x float> %X, %Y
+  ret <2 x float> %R
+}
+
+; Check 47*X + 47*X -> 94*X.
+define <2 x float> @test5(<2 x float> %X) {
+; CHECK-LABEL: @test5
+; CHECK-NEXT: fmul fast <2 x float> %X, <float 9.400000e+01, float 9.400000e+01>
+; CHECK-NEXT: ret <2 x float>
+
+  %Y = fmul fast <2 x float> %X, <float 4.700000e+01, float 4.700000e+01>
+  %Z = fadd fast <2 x float> %Y, %Y
+  ret <2 x float> %Z
+}
+
+; Check X+X+X -> 3*X.
+define <2 x float> @test6(<2 x float> %X) {
+; CHECK-LABEL: @test6
+; CHECK-NEXT: fmul fast <2 x float> %X, <float 3.000000e+00, float 3.000000e+00>
+; CHECK-NEXT: ret <2 x float>
+
+  %Y = fadd fast <2 x float> %X ,%X
+  %Z = fadd fast <2 x float> %Y, %X
+  ret <2 x float> %Z
+}
+
+; Check 127*W+50*W -> 177*W.
+define <2 x double> @test7(<2 x double> %W) {
+; CHECK-LABEL: @test7
+; CHECK-NEXT: fmul fast <2 x double> %W, <double 1.770000e+02, double 1.770000e+02>
+; CHECK-NEXT: ret <2 x double>
+
+  %X = fmul fast <2 x double> %W, <double 127.0, double 127.0>
+  %Y = fmul fast <2 x double> %W, <double 50.0, double 50.0>
+  %Z = fadd fast <2 x double> %Y, %X
+  ret <2 x double> %Z
+}
+
+; Check X*12*12 -> X*144.
+define <2 x float> @test8(<2 x float> %arg) {
+; CHECK-LABEL: @test8
+; CHECK: fmul fast <2 x float> %arg, <float 1.440000e+02, float 1.440000e+02>
+; CHECK-NEXT: ret <2 x float> %tmp2
+
+  %tmp1 = fmul fast <2 x float> <float 1.200000e+01, float 1.200000e+01>, %arg
+  %tmp2 = fmul fast <2 x float> %tmp1, <float 1.200000e+01, float 1.200000e+01>
+  ret <2 x float> %tmp2
+}
+
+; Check (b+(a+1234))+-a -> b+1234.
+define <2 x double> @test9(<2 x double> %b, <2 x double> %a) {
+; CHECK-LABEL: @test9
+; CHECK: fadd fast <2 x double> %b, <double 1.234000e+03, double 1.234000e+03>
+; CHECK-NEXT: ret <2 x double>
+
+  %1 = fadd fast <2 x double> %a, <double 1.234000e+03, double 1.234000e+03>
+  %2 = fadd fast <2 x double> %b, %1
+  %3 = fsub fast <2 x double> <double 0.000000e+00, double 0.000000e+00>, %a
+  %4 = fadd fast <2 x double> %2, %3
+  ret <2 x double> %4
+}
+
+; Check -(-(z*40)*a) -> a*40*z.
+define <2 x float> @test10(<2 x float> %a, <2 x float> %b, <2 x float> %z) {
+; CHECK-LABEL: @test10
+; CHECK: fmul fast <2 x float> %a, <float 4.000000e+01, float 4.000000e+01>
+; CHECK-NEXT: fmul fast <2 x float> %e, %z
+; CHECK-NEXT: ret <2 x float>
+
+  %d = fmul fast <2 x float> %z, <float 4.000000e+01, float 4.000000e+01>
+  %c = fsub fast <2 x float> <float 0.000000e+00, float 0.000000e+00>, %d
+  %e = fmul fast <2 x float> %a, %c
+  %f = fsub fast <2 x float> <float 0.000000e+00, float 0.000000e+00>, %e
+  ret <2 x float> %f
+}
+
+; Check x*y+y*x -> x*y*2.
+define <2 x double> @test11(<2 x double> %x, <2 x double> %y) {
+; CHECK-LABEL: @test11
+; CHECK-NEXT: %factor = fmul fast <2 x double> %y, <double 2.000000e+00, double 2.000000e+00>
+; CHECK-NEXT: %tmp1 = fmul fast <2 x double> %factor, %x
+; CHECK-NEXT: ret <2 x double> %tmp1
+
+  %1 = fmul fast <2 x double> %x, %y
+  %2 = fmul fast <2 x double> %y, %x
+  %3 = fadd fast <2 x double> %1, %2
+  ret <2 x double> %3
+}
+
+; FIXME: shifts should be converted to mul to assist further reassociation.
+define <2 x i64> @test12(<2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: @test12
+; CHECK-NEXT:  %mul = mul <2 x i64> %c, %b
+; CHECK-NEXT:  %shl = shl <2 x i64> %mul, <i64 5, i64 5>
+; CHECK-NEXT:  ret <2 x i64> %shl
+
+  %mul = mul <2 x i64> %c, %b
+  %shl = shl <2 x i64> %mul, <i64 5, i64 5>
+  ret <2 x i64> %shl
+}
+
+; FIXME: expressions with a negative const should be canonicalized to assist
+; further reassociation.
+; We would expect (-5*b)+a -> a-(5*b) but only the constant operand is commuted.
+define <4 x float> @test13(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test13
+; CHECK-NEXT:  %mul = fmul fast <4 x float> %b, <float -5.000000e+00, float -5.000000e+00, float -5.000000e+00, float -5.000000e+00>
+; CHECK-NEXT:  %add = fadd fast <4 x float> %mul, %a
+; CHECK-NEXT:  ret <4 x float> %add
+
+  %mul = fmul fast <4 x float> <float -5.000000e+00, float -5.000000e+00, float -5.000000e+00, float -5.000000e+00>, %b
+  %add = fadd fast <4 x float> %mul, %a
+  ret <4 x float> %add
+}
+
+; Break up subtract to assist further reassociation.
+; Check a+b-c -> a+b+-c.
+define <2 x i64> @test14(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: @test14
+; CHECK-NEXT: %add = add <2 x i64> %b, %a
+; CHECK-NEXT: %c.neg = sub <2 x i64> zeroinitializer, %c
+; CHECK-NEXT: %sub = add <2 x i64> %add, %c.neg
+; CHECK-NEXT: ret <2 x i64> %sub
+
+  %add = add <2 x i64> %b, %a
+  %sub = sub <2 x i64> %add, %c
+  ret <2 x i64> %sub
 }
 
-define <2 x i32> @test4(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: test4
-; CHECK-NEXT: %tmp1 = and <2 x i32> %x, %y
-; CHECK-NEXT: %tmp2 = and <2 x i32> %x, %y
-; CHECK-NEXT: %tmp3 = and <2 x i32> %tmp1, %tmp2
+define <2 x i32> @test15(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: test15
+; CHECK-NEXT: %tmp3 = and <2 x i32> %y, %x
+; CHECK-NEXT: ret <2 x i32> %tmp3
 
   %tmp1 = and <2 x i32> %x, %y
   %tmp2 = and <2 x i32> %y, %x
@@ -48,11 +194,10 @@ define <2 x i32> @test4(<2 x i32> %x, <2 x i32> %y) {
   ret <2 x i32> %tmp3
 }
 
-define <2 x i32> @test5(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: test5
-; CHECK-NEXT: %tmp1 = or <2 x i32> %x, %y
-; CHECK-NEXT: %tmp2 = or <2 x i32> %x, %y
-; CHECK-NEXT: %tmp3 = or <2 x i32> %tmp1, %tmp2
+define <2 x i32> @test16(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: test16
+; CHECK-NEXT: %tmp3 = or <2 x i32> %y, %x
+; CHECK-NEXT: ret <2 x i32> %tmp3
 
   %tmp1 = or <2 x i32> %x, %y
   %tmp2 = or <2 x i32> %y, %x
@@ -60,8 +205,9 @@ define <2 x i32> @test5(<2 x i32> %x, <2 x i32> %y) {
   ret <2 x i32> %tmp3
 }
 
-define <2 x i32> @test6(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: test6
+; FIXME: Optimize vector xor.  Currently only commute operands.
+define <2 x i32> @test17(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: test17
 ; CHECK-NEXT: %tmp1 = xor <2 x i32> %x, %y
 ; CHECK-NEXT: %tmp2 = xor <2 x i32> %x, %y
 ; CHECK-NEXT: %tmp3 = xor <2 x i32> %tmp1, %tmp2
diff --git a/test/Transforms/Reassociate/fast-basictest.ll b/test/Transforms/Reassociate/fast-basictest.ll
index 67b07f4d2699..64b74e3e8c16 100644
--- a/test/Transforms/Reassociate/fast-basictest.ll
+++ b/test/Transforms/Reassociate/fast-basictest.ll
@@ -48,9 +48,9 @@ define void @test4() {
 ; CHECK-NOT: fadd fast float
 ; CHECK: ret void
 
-  %A = load float* @fa
-  %B = load float* @fb
-  %C = load float* @fc
+  %A = load float, float* @fa
+  %B = load float, float* @fb
+  %C = load float, float* @fc
   %t1 = fadd fast float %A, %B
   %t2 = fadd fast float %t1, %C
   %t3 = fadd fast float %C, %A
@@ -69,9 +69,9 @@ define void @test5() {
 ; CHECK-NOT: fadd
 ; CHECK: ret void
 
-  %A = load float* @fa
-  %B = load float* @fb
-  %C = load float* @fc
+  %A = load float, float* @fa
+  %B = load float, float* @fb
+  %C = load float, float* @fc
   %t1 = fadd fast float %A, %B
   %t2 = fadd fast float %t1, %C
   %t3 = fadd fast float %C, %A
@@ -90,9 +90,9 @@ define void @test6() {
 ; CHECK-NOT: fadd
 ; CHECK: ret void
 
-  %A = load float* @fa
-  %B = load float* @fb
-  %C = load float* @fc
+  %A = load float, float* @fa
+  %B = load float, float* @fb
+  %C = load float, float* @fc
   %t1 = fadd fast float %B, %A
   %t2 = fadd fast float %t1, %C
   %t3 = fadd fast float %C, %A
diff --git a/test/Transforms/Reassociate/looptest.ll b/test/Transforms/Reassociate/looptest.ll
index aad3b206f69f..5563070d5245 100644
--- a/test/Transforms/Reassociate/looptest.ll
+++ b/test/Transforms/Reassociate/looptest.ll
@@ -33,8 +33,8 @@ bb4:		; preds = %bb4, %bb3
 	%reg117 = phi i32 [ %reg118, %bb4 ], [ 0, %bb3 ]		; <i32> [#uses=2]
 	%reg113 = add i32 %reg115, %reg117		; <i32> [#uses=1]
 	%reg114 = add i32 %reg113, %reg116		; <i32> [#uses=1]
-	%cast227 = getelementptr [4 x i8]* @.LC0, i64 0, i64 0		; <i8*> [#uses=1]
-	call i32 (i8*, ...)* @printf( i8* %cast227, i32 %reg114 )		; <i32>:0 [#uses=0]
+	%cast227 = getelementptr [4 x i8], [4 x i8]* @.LC0, i64 0, i64 0		; <i8*> [#uses=1]
+	call i32 (i8*, ...) @printf( i8* %cast227, i32 %reg114 )		; <i32>:0 [#uses=0]
 	%reg118 = add i32 %reg117, 1		; <i32> [#uses=2]
 	%cond224 = icmp ne i32 %reg118, %Num		; <i1> [#uses=1]
 	br i1 %cond224, label %bb4, label %bb5
diff --git a/test/Transforms/Reassociate/min_int.ll b/test/Transforms/Reassociate/min_int.ll
new file mode 100644
index 000000000000..52dab3a531f7
--- /dev/null
+++ b/test/Transforms/Reassociate/min_int.ll
@@ -0,0 +1,13 @@
+; RUN: opt < %s -reassociate -dce -S | FileCheck %s
+
+; MIN_INT cannot be negated during reassociation
+
+define i32 @minint(i32 %i) {
+; CHECK:  %mul = mul i32 %i, -2147483648
+; CHECK-NEXT:  %add = add i32 %mul, 1
+; CHECK-NEXT:  ret i32 %add
+  %mul = mul i32 %i, -2147483648
+  %add = add i32 %mul, 1
+  ret i32 %add
+}
+
diff --git a/test/Transforms/Reassociate/pr12245.ll b/test/Transforms/Reassociate/pr12245.ll
index e9b5355cceb1..0e7152e2a177 100644
--- a/test/Transforms/Reassociate/pr12245.ll
+++ b/test/Transforms/Reassociate/pr12245.ll
@@ -6,34 +6,34 @@
 
 define i32 @fn2() nounwind uwtable ssp {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %dec = add nsw i32 %0, -1
   store i32 %dec, i32* @a, align 4
-  %1 = load i32* @d, align 4
+  %1 = load i32, i32* @d, align 4
   %sub = sub nsw i32 %dec, %1
   store i32 %sub, i32* @d, align 4
-  %2 = load i32* @a, align 4
+  %2 = load i32, i32* @a, align 4
   %dec1 = add nsw i32 %2, -1
   store i32 %dec1, i32* @a, align 4
-  %3 = load i32* @d, align 4
+  %3 = load i32, i32* @d, align 4
   %sub2 = sub nsw i32 %dec1, %3
   store i32 %sub2, i32* @d, align 4
-  %4 = load i32* @a, align 4
+  %4 = load i32, i32* @a, align 4
   %dec3 = add nsw i32 %4, -1
   store i32 %dec3, i32* @a, align 4
-  %5 = load i32* @d, align 4
+  %5 = load i32, i32* @d, align 4
   %sub4 = sub nsw i32 %dec3, %5
   store i32 %sub4, i32* @d, align 4
-  %6 = load i32* @a, align 4
+  %6 = load i32, i32* @a, align 4
   %dec5 = add nsw i32 %6, -1
   store i32 %dec5, i32* @a, align 4
-  %7 = load i32* @d, align 4
+  %7 = load i32, i32* @d, align 4
   %sub6 = sub nsw i32 %dec5, %7
   store i32 %sub6, i32* @d, align 4
-  %8 = load i32* @a, align 4
+  %8 = load i32, i32* @a, align 4
   %dec7 = add nsw i32 %8, -1
   store i32 %dec7, i32* @a, align 4
-  %9 = load i32* @d, align 4
+  %9 = load i32, i32* @d, align 4
   %sub8 = sub nsw i32 %dec7, %9
   store i32 %sub8, i32* @d, align 4
   ret i32 0
diff --git a/test/Transforms/Reassociate/pr21205.ll b/test/Transforms/Reassociate/pr21205.ll
index fcc7150478eb..0c6fd3ab5693 100644
--- a/test/Transforms/Reassociate/pr21205.ll
+++ b/test/Transforms/Reassociate/pr21205.ll
@@ -11,7 +11,7 @@
 
 define i32 @test1() {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %conv = sitofp i32 %0 to float
   %sub = fsub fast float %conv, undef
   %sub1 = fadd fast float %sub, -1.000000e+00
diff --git a/test/Transforms/RewriteStatepointsForGC/base-pointers-1.ll b/test/Transforms/RewriteStatepointsForGC/base-pointers-1.ll
new file mode 100644
index 000000000000..1ff1abedd31c
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/base-pointers-1.ll
@@ -0,0 +1,28 @@
+; RUN: opt %s -rewrite-statepoints-for-gc -spp-print-base-pointers -S 2>&1 | FileCheck %s
+
+; CHECK: derived %merged_value base %base_phi
+
+declare void @site_for_call_safpeoint()
+
+define i64 addrspace(1)* @test(i64 addrspace(1)* %base_obj_x, i64 addrspace(1)* %base_obj_y, i1 %runtime_condition) gc "statepoint-example" {
+entry:
+  br i1 %runtime_condition, label %here, label %there
+
+here:
+  %x = getelementptr i64, i64 addrspace(1)* %base_obj_x, i32 1
+  br label %merge
+
+there:
+  %y = getelementptr i64, i64 addrspace(1)* %base_obj_y, i32 1
+  br label %merge
+
+merge:
+; CHECK-LABEL: merge:
+; CHECK:   %base_phi = phi i64 addrspace(1)* [ %base_obj_x, %here ], [ %base_obj_y, %there ]
+  %merged_value = phi i64 addrspace(1)* [ %x, %here ], [ %y, %there ]
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @site_for_call_safpeoint, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  ret i64 addrspace(1)* %merged_value
+}
+
+declare void @foo()
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
\ No newline at end of file
diff --git a/test/Transforms/RewriteStatepointsForGC/base-pointers-10.ll b/test/Transforms/RewriteStatepointsForGC/base-pointers-10.ll
new file mode 100644
index 000000000000..f4292a998485
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/base-pointers-10.ll
@@ -0,0 +1,37 @@
+; RUN: opt %s -rewrite-statepoints-for-gc -spp-print-base-pointers -S 2>&1 | FileCheck %s
+
+; CHECK: derived %next_x base %base_obj_x
+; CHECK: derived %next_y base %base_obj_y
+; CHECK: derived %next base %base_phi
+
+declare i1 @runtime_value()
+declare void @do_safepoint()
+
+define void @select_of_phi(i64 addrspace(1)* %base_obj_x, i64 addrspace(1)* %base_obj_y) gc "statepoint-example" {
+entry:
+  br label %loop
+
+loop:
+  %current_x = phi i64 addrspace(1)* [ %base_obj_x , %entry ], [ %next_x, %merge ]
+  %current_y = phi i64 addrspace(1)* [ %base_obj_y , %entry ], [ %next_y, %merge ]
+  %current = phi i64 addrspace(1)* [ null , %entry ], [ %next , %merge ]
+
+  %condition = call i1 @runtime_value()
+  %next_x = getelementptr i64, i64 addrspace(1)* %current_x, i32 1
+  %next_y = getelementptr i64, i64 addrspace(1)* %current_y, i32 1
+
+  br i1 %condition, label %true, label %false
+
+true:
+  br label %merge
+
+false:
+  br label %merge
+
+merge:
+  %next = phi i64 addrspace(1)* [ %next_x, %true ], [ %next_y, %false ]
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  br label %loop
+}
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
\ No newline at end of file
diff --git a/test/Transforms/RewriteStatepointsForGC/base-pointers-11.ll b/test/Transforms/RewriteStatepointsForGC/base-pointers-11.ll
new file mode 100644
index 000000000000..2a7a7444adec
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/base-pointers-11.ll
@@ -0,0 +1,26 @@
+; RUN: opt %s -rewrite-statepoints-for-gc -spp-print-base-pointers  -S 2>&1 | FileCheck %s
+
+; CHECK: derived %next base %base_obj
+
+declare void @do_safepoint()
+
+define void @test(i64 addrspace(1)* %base_obj) gc "statepoint-example" {
+entry:
+  %obj = getelementptr i64, i64 addrspace(1)* %base_obj, i32 1
+  br label %loop
+
+loop:                                             ; preds = %loop, %entry
+; CHECK-LABEL: loop:
+; CHECK: phi i64 addrspace(1)*
+; CHECK-DAG:  [ %base_obj.relocated.casted, %loop ] 
+; CHECK-DAG:  [ %base_obj, %entry ]
+; CHECK:  %current = phi i64 addrspace(1)* 
+; CHECK-DAG:  [ %obj, %entry ]
+; CHECK-DAG:  [ %next.relocated.casted, %loop ]
+  %current = phi i64 addrspace(1)* [ %obj, %entry ], [ %next, %loop ]
+  %next = getelementptr i64, i64 addrspace(1)* %current, i32 1
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  br label %loop
+}
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
\ No newline at end of file
diff --git a/test/Transforms/RewriteStatepointsForGC/base-pointers-2.ll b/test/Transforms/RewriteStatepointsForGC/base-pointers-2.ll
new file mode 100644
index 000000000000..c2877d8b5393
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/base-pointers-2.ll
@@ -0,0 +1,21 @@
+; RUN: opt %s -rewrite-statepoints-for-gc -spp-print-base-pointers -S 2>&1 | FileCheck %s
+
+; CHECK: derived %merged_value base %base_obj
+
+
+define i64 addrspace(1)* @test(i64 addrspace(1)* %base_obj, i1 %runtime_condition) gc "statepoint-example" {
+entry:
+  br i1 %runtime_condition, label %merge, label %there
+
+there:
+  %derived_obj = getelementptr i64, i64 addrspace(1)* %base_obj, i32 1
+  br label %merge
+
+merge:
+  %merged_value = phi i64 addrspace(1)* [ %base_obj, %entry ], [ %derived_obj, %there ]
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  ret i64 addrspace(1)* %merged_value
+}
+
+declare void @foo()
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
\ No newline at end of file
diff --git a/test/Transforms/RewriteStatepointsForGC/base-pointers-3.ll b/test/Transforms/RewriteStatepointsForGC/base-pointers-3.ll
new file mode 100644
index 000000000000..f72201b5138e
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/base-pointers-3.ll
@@ -0,0 +1,20 @@
+; RUN: opt %s -rewrite-statepoints-for-gc -spp-print-base-pointers -S 2>&1 | FileCheck %s
+
+; CHECK: derived %next.i64 base %base_obj
+
+define void @test(i64 addrspace(1)* %base_obj) gc "statepoint-example" {
+entry:
+  %obj = getelementptr i64, i64 addrspace(1)* %base_obj, i32 1
+  br label %loop
+
+loop:
+  %current = phi i64 addrspace(1)* [ %obj, %entry ], [ %next.i64, %loop ]
+  %current.i32 = bitcast i64 addrspace(1)* %current to i32 addrspace(1)*
+  %next.i32 = getelementptr i32, i32 addrspace(1)* %current.i32, i32 1
+  %next.i64 = bitcast i32 addrspace(1)* %next.i32 to i64 addrspace(1)*
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  br label %loop
+}
+
+declare void @do_safepoint()
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
\ No newline at end of file
diff --git a/test/Transforms/RewriteStatepointsForGC/base-pointers-4.ll b/test/Transforms/RewriteStatepointsForGC/base-pointers-4.ll
new file mode 100644
index 000000000000..90d91d21d7b4
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/base-pointers-4.ll
@@ -0,0 +1,53 @@
+; RUN: opt %s -rewrite-statepoints-for-gc -spp-print-base-pointers -S 2>&1 | FileCheck %s
+
+
+; CHECK: derived %obj_to_consume base %base_phi
+
+declare void @foo()
+declare i64 addrspace(1)* @generate_obj()
+declare void @consume_obj(i64 addrspace(1)*)
+
+define void @test(i32 %condition) gc "statepoint-example" {
+entry:
+  br label %loop
+
+loop:
+; CHECK: loop:
+; CHECK:  %safepoint_token1 = call i32 (i64, i32, i64 addrspace(1)* ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_p1i64f(i64 0, i32 0, i64 addrspace(1)* ()* @generate_obj, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i3
+; CHECK-NEXT:  %obj2 = call i64 addrspace(1)* @llvm.experimental.gc.result
+  %safepoint_token1 = call i32 (i64, i32, i64 addrspace(1)* ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_p1i64f(i64 0, i32 0, i64 addrspace(1)* ()* @generate_obj, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  %obj2 = call i64 addrspace(1)* @llvm.experimental.gc.result.p1i64(i32 %safepoint_token1)
+  switch i32 %condition, label %dest_a [
+    i32 0, label %dest_b
+    i32 1, label %dest_c
+  ]
+
+dest_a:
+  br label %merge
+
+dest_b:
+  br label %merge
+
+dest_c:
+  br label %merge
+
+merge:
+; CHECK: merge:
+; CHECK:  %base_phi = phi i64 addrspace(1)* [ %obj2, %dest_a ], [ null, %dest_b ], [ null, %dest_c ]
+; CHECK:  %obj_to_consume = phi i64 addrspace(1)* [ %obj2, %dest_a ], [ null, %dest_b ], [ null, %dest_c ]
+
+  %obj_to_consume = phi i64 addrspace(1)* [ %obj2, %dest_a ], [ null, %dest_b ], [ null, %dest_c ]
+  %safepoint_token3 = call i32 (i64, i32, void (i64 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidp1i64f(i64 0, i32 0, void (i64 addrspace(1)*)* @consume_obj, i32 1, i32 0, i64 addrspace(1)* %obj_to_consume, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  br label %merge.split
+
+merge.split:                                      ; preds = %merge
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  br label %loop
+}
+
+
+; Function Attrs: nounwind
+declare i64 addrspace(1)* @llvm.experimental.gc.result.p1i64(i32) #0
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
+declare i32 @llvm.experimental.gc.statepoint.p0f_p1i64f(i64, i32, i64 addrspace(1)* ()*, i32, i32, ...)
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidp1i64f(i64, i32, void (i64 addrspace(1)*)*, i32, i32, ...)
\ No newline at end of file
diff --git a/test/Transforms/RewriteStatepointsForGC/base-pointers-5.ll b/test/Transforms/RewriteStatepointsForGC/base-pointers-5.ll
new file mode 100644
index 000000000000..9b73377e31cb
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/base-pointers-5.ll
@@ -0,0 +1,30 @@
+; RUN: opt %s -rewrite-statepoints-for-gc -spp-print-base-pointers -S 2>&1 | FileCheck %s
+
+; CHECK: derived %merged_value base %base_phi
+
+declare void @foo()
+
+define i64 addrspace(1)* @test(i64 addrspace(1)* %base_obj_x, i64 addrspace(1)* %base_obj_y, i1 %runtime_condition) gc "statepoint-example" {
+entry:
+  br i1 %runtime_condition, label %here, label %there
+
+here:
+  br label %bump
+
+bump:
+  br label %merge
+
+there:
+  %y = getelementptr i64, i64 addrspace(1)* %base_obj_y, i32 1
+  br label %merge
+
+merge:
+; CHECK: merge:
+; CHECK:  %base_phi = phi i64 addrspace(1)* [ %base_obj_x, %bump ], [ %base_obj_y, %there ]
+; CHECK-NEXT:  %merged_value = phi i64 addrspace(1)* [ %base_obj_x, %bump ], [ %y, %there ]  
+  %merged_value = phi i64 addrspace(1)* [ %base_obj_x, %bump ], [ %y, %there ]
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  ret i64 addrspace(1)* %merged_value
+}
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
diff --git a/test/Transforms/RewriteStatepointsForGC/base-pointers-6.ll b/test/Transforms/RewriteStatepointsForGC/base-pointers-6.ll
new file mode 100644
index 000000000000..0b785d72d63c
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/base-pointers-6.ll
@@ -0,0 +1,41 @@
+; RUN: opt %s -rewrite-statepoints-for-gc -spp-print-base-pointers -S 2>&1 | FileCheck %s
+
+; CHECK: derived %merged_value base %base_phi
+
+declare void @site_for_call_safpeoint()
+
+define i64 addrspace(1)* @test(i64 addrspace(1)* %base_obj_x, i64 addrspace(1)* %base_obj_y, i1 %runtime_condition_x, i1 %runtime_condition_y) gc "statepoint-example" {
+entry:
+  br i1 %runtime_condition_x, label %here, label %there
+
+here:
+ br i1 %runtime_condition_y, label %bump_here_a, label %bump_here_b
+
+bump_here_a:
+  %x_a = getelementptr i64, i64 addrspace(1)* %base_obj_x, i32 1
+  br label %merge_here
+
+bump_here_b:
+  %x_b = getelementptr i64, i64 addrspace(1)* %base_obj_x, i32 2
+  br label %merge_here
+  
+
+merge_here:
+  %x = phi i64 addrspace(1)* [ %x_a , %bump_here_a ], [ %x_b , %bump_here_b ]
+  br label %merge
+
+there:
+  %y = getelementptr i64, i64 addrspace(1)* %base_obj_y, i32 1
+  br label %merge
+
+merge:
+; CHECK: merge:
+; CHECK:  %base_phi = phi i64 addrspace(1)* [ %base_obj_x, %merge_here ], [ %base_obj_y, %there ]
+; CHECK-NEXT:  %merged_value = phi i64 addrspace(1)* [ %x, %merge_here ], [ %y, %there ]  
+  %merged_value = phi i64 addrspace(1)* [ %x, %merge_here ], [ %y, %there ]
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @site_for_call_safpeoint, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  ret i64 addrspace(1)* %merged_value
+}
+
+declare void @do_safepoint()
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
\ No newline at end of file
diff --git a/test/Transforms/RewriteStatepointsForGC/base-pointers-7.ll b/test/Transforms/RewriteStatepointsForGC/base-pointers-7.ll
new file mode 100644
index 000000000000..467429b4d27d
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/base-pointers-7.ll
@@ -0,0 +1,52 @@
+; RUN: opt %s -rewrite-statepoints-for-gc -spp-print-base-pointers -S 2>&1 | FileCheck %s
+
+; CHECK: derived %merged_value base %base_phi
+
+declare void @site_for_call_safpeoint()
+
+define i64 addrspace(1)* @test(i64 addrspace(1)* %base_obj_x, 
+   i64 addrspace(1)* %base_obj_y, i1 %runtime_condition_x, 
+   i1 %runtime_condition_y) gc "statepoint-example" {
+entry:
+  br i1 %runtime_condition_x, label %here, label %there
+
+here:
+ br i1 %runtime_condition_y, label %bump_here_a, label %bump_here_b
+
+bump_here_a:
+  %x_a = getelementptr i64, i64 addrspace(1)* %base_obj_x, i32 1
+  br label %merge_here
+
+bump_here_b:
+  %x_b = getelementptr i64, i64 addrspace(1)* %base_obj_y, i32 2
+  br label %merge_here
+  
+
+merge_here:
+; CHECK: merge_here:
+; CHECK-DAG: %base_phi
+; CHECK-DAG: phi i64 addrspace(1)*
+; CHECK-DAG: [ %base_obj_x, %bump_here_a ]
+; CHECK-DAG: [ %base_obj_y, %bump_here_b ]
+  %x = phi i64 addrspace(1)* [ %x_a , %bump_here_a ], [ %x_b , %bump_here_b ]
+  br label %merge
+
+there:
+  %y = getelementptr i64, i64 addrspace(1)* %base_obj_y, i32 1
+  br label %merge
+
+merge:
+; CHECK: merge:
+; CHECK-DAG:  %base_phi1
+; CHECK-DAG: phi i64 addrspace(1)*
+; CHECK-DAG: %merge_here
+; CHECK-DAG: [ %base_obj_y, %there ]
+; CHECK:  %merged_value = phi i64 addrspace(1)* [ %x, %merge_here ], [ %y, %there ]  
+  %merged_value = phi i64 addrspace(1)* [ %x, %merge_here ], [ %y, %there ]
+
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @site_for_call_safpeoint, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  ret i64 addrspace(1)* %merged_value
+}
+
+declare void @do_safepoint()
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
diff --git a/test/Transforms/RewriteStatepointsForGC/base-pointers-8.ll b/test/Transforms/RewriteStatepointsForGC/base-pointers-8.ll
new file mode 100644
index 000000000000..b89be7daa67b
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/base-pointers-8.ll
@@ -0,0 +1,38 @@
+; RUN: opt %s -rewrite-statepoints-for-gc -spp-print-base-pointers -S 2>&1 | FileCheck %s
+
+; CHECK: derived %next_element_ptr base %array_obj
+
+define i32 @null_in_array(i64 addrspace(1)* %array_obj) gc "statepoint-example" {
+entry:
+  %array_len_pointer.i64 = getelementptr i64, i64 addrspace(1)* %array_obj, i32 1
+  %array_len_pointer.i32 = bitcast i64 addrspace(1)* %array_len_pointer.i64 to i32 addrspace(1)*
+  %array_len = load i32, i32 addrspace(1)* %array_len_pointer.i32
+  %array_elems = bitcast i32 addrspace(1)* %array_len_pointer.i32 to i64 addrspace(1)* addrspace(1)*
+  br label %loop_check
+
+loop_check:
+  %index = phi i32 [ 0, %entry ], [ %next_index, %loop_back ]
+  %current_element_ptr = phi i64 addrspace(1)* addrspace(1)* [ %array_elems, %entry ], [ %next_element_ptr, %loop_back ]
+  %index_lt = icmp ult i32 %index, %array_len
+  br i1 %index_lt, label %check_for_null, label %not_found
+
+check_for_null:
+  %current_element = load i64 addrspace(1)*, i64 addrspace(1)* addrspace(1)* %current_element_ptr
+  %is_null = icmp eq i64 addrspace(1)* %current_element, null
+  br i1 %is_null, label %found, label %loop_back
+
+loop_back:
+  %next_element_ptr = getelementptr i64 addrspace(1)*, i64 addrspace(1)* addrspace(1)* %current_element_ptr, i32 1
+  %next_index = add i32 %index, 1
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  br label %loop_check
+
+not_found:
+  ret i32 -1
+
+found:
+  ret i32 %index
+}
+
+declare void @do_safepoint()
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
\ No newline at end of file
diff --git a/test/Transforms/RewriteStatepointsForGC/base-pointers-9.ll b/test/Transforms/RewriteStatepointsForGC/base-pointers-9.ll
new file mode 100644
index 000000000000..848633b2a275
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/base-pointers-9.ll
@@ -0,0 +1,21 @@
+; RUN: opt %s -rewrite-statepoints-for-gc -spp-print-base-pointers -S  2>&1 | FileCheck %s
+
+; CHECK: derived %next base %base_obj
+
+declare i1 @runtime_value()
+
+define void @maybe_GEP(i64 addrspace(1)* %base_obj) gc "statepoint-example" {
+entry:
+  br label %loop
+
+loop:
+  %current = phi i64 addrspace(1)* [ %base_obj, %entry ], [ %next, %loop ]
+  %condition = call i1 @runtime_value()
+  %maybe_next = getelementptr i64, i64 addrspace(1)* %current, i32 1
+  %next = select i1 %condition, i64 addrspace(1)* %maybe_next, i64 addrspace(1)* %current
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  br label %loop
+}
+
+declare void @do_safepoint()
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
\ No newline at end of file
diff --git a/test/Transforms/RewriteStatepointsForGC/base-pointers.ll b/test/Transforms/RewriteStatepointsForGC/base-pointers.ll
new file mode 100644
index 000000000000..879f3f9e24da
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/base-pointers.ll
@@ -0,0 +1,100 @@
+; RUN: opt %s -rewrite-statepoints-for-gc -S 2>&1 | FileCheck %s
+
+declare i64 addrspace(1)* @generate_obj()
+declare void @use_obj(i64 addrspace(1)*)
+
+; The rewriting needs to make %obj loop variant by inserting a phi 
+; of the original value and it's relocation.
+define void @def_use_safepoint() gc "statepoint-example" {
+; CHECK-LABEL: def_use_safepoint
+entry:
+  %obj = call i64 addrspace(1)* @generate_obj()
+  br label %loop
+
+loop:
+; CHECK: phi i64 addrspace(1)* 
+; CHECK-DAG: [ %obj.relocated.casted, %loop ]
+; CHECK-DAG: [ %obj, %entry ]
+  call void @use_obj(i64 addrspace(1)* %obj)
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  br label %loop
+}
+
+declare void @do_safepoint()
+
+declare void @parse_point(i64 addrspace(1)*)
+
+define i64 addrspace(1)* @test1(i32 %caller, i8 addrspace(1)* %a, i8 addrspace(1)* %b, i32 %unknown) gc "statepoint-example" {
+; CHECK-LABEL: test1
+ entry:
+  br i1 undef, label %left, label %right
+
+ left:
+  %a.cast = bitcast i8 addrspace(1)* %a to i64 addrspace(1)*
+; CHECK: left:
+; CHECK-NEXT: %a.cast = bitcast i8 addrspace(1)* %a to i64 addrspace(1)*
+; CHECK-NEXT: [[CAST_L:%.*]] = bitcast i8 addrspace(1)* %a to i64 addrspace(1)*
+
+; Our safepoint placement pass calls removeUnreachableBlocks, which does a bunch
+; of simplifications to branch instructions.  This bug is visible only when
+; there are multiple branches into the same block from the same predecessor, and
+; the following ceremony is to make that artefact survive a call to 
+; removeUnreachableBlocks.  As an example, "br i1 undef, label %merge, label %merge"
+; will get simplified to "br label %merge" by removeUnreachableBlocks.
+  switch i32 %unknown, label %right [ i32 0, label %merge
+                                      i32 1, label %merge
+                                      i32 5, label %merge
+                                      i32 3, label %right ]
+
+ right:
+  %b.cast = bitcast i8 addrspace(1)* %b to i64 addrspace(1)*
+  br label %merge
+; CHECK: right:
+; CHECK-NEXT: %b.cast = bitcast i8 addrspace(1)* %b to i64 addrspace(1)*
+; CHECK-NEXT: [[CAST_R:%.*]] = bitcast i8 addrspace(1)* %b to i64 addrspace(1)*
+
+ merge:
+; CHECK: merge:
+; CHECK-NEXT: %base_phi = phi i64 addrspace(1)* [ [[CAST_L]], %left ], [ [[CAST_L]], %left ], [ [[CAST_L]], %left ], [ [[CAST_R]], %right ], !is_base_value !0
+  %value = phi i64 addrspace(1)* [ %a.cast, %left], [ %a.cast, %left], [ %a.cast, %left], [ %b.cast, %right]
+  %safepoint_token = call i32 (i64, i32, void (i64 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidp1i64f(i64 0, i32 0, void (i64 addrspace(1)*)* @parse_point, i32 1, i32 0, i64 addrspace(1)* %value, i32 0, i32 5, i32 0, i32 0, i32 0, i32 0, i32 0)
+
+  ret i64 addrspace(1)* %value
+}
+
+;; The purpose of this test is to ensure that when two live values share a
+;;  base defining value with inherent conflicts, we end up with a *single*
+;;  base phi/select per such node.  This is testing an optimization, not a
+;;  fundemental correctness criteria
+define void @test2(i1 %cnd, i64 addrspace(1)* %base_obj, i64 addrspace(1)* %base_arg2)  gc "statepoint-example" {
+; CHECK-LABEL: @test2
+entry:
+  %obj = getelementptr i64, i64 addrspace(1)* %base_obj, i32 1
+  br label %loop
+
+loop:                                             ; preds = %loop, %entry
+; CHECK-LABEL: loop
+; CHECK:   %base_phi = phi i64 addrspace(1)*
+; CHECK-DAG: [ %base_obj, %entry ]
+; Given the two selects are equivelent, so are their base phis - ideally,
+; we'd have commoned these, but that's a missed optimization, not correctness.
+; CHECK-DAG: [ [[DISCARD:%base_select.*.relocated.casted]], %loop ]
+; CHECK-NOT: base_phi2
+; CHECK: next = select
+; CHECK: base_select
+; CHECK: extra2 = select
+; CHECK: base_select
+; CHECK: statepoint
+;; Both 'next' and 'extra2' are live across the backedge safepoint...
+  %current = phi i64 addrspace(1)* [ %obj, %entry ], [ %next, %loop ]
+  %extra = phi i64 addrspace(1)* [ %obj, %entry ], [ %extra2, %loop ]
+  %nexta = getelementptr i64, i64 addrspace(1)* %current, i32 1
+  %next = select i1 %cnd, i64 addrspace(1)* %nexta, i64 addrspace(1)* %base_arg2
+  %extra2 = select i1 %cnd, i64 addrspace(1)* %nexta, i64 addrspace(1)* %base_arg2
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  br label %loop
+}
+
+declare void @foo()
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidp1i64f(i64, i32, void (i64 addrspace(1)*)*, i32, i32, ...)
\ No newline at end of file
diff --git a/test/Transforms/RewriteStatepointsForGC/basics.ll b/test/Transforms/RewriteStatepointsForGC/basics.ll
new file mode 100644
index 000000000000..2a61924a5927
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/basics.ll
@@ -0,0 +1,88 @@
+; This is a collection of really basic tests for gc.statepoint rewriting.
+; RUN:  opt %s -rewrite-statepoints-for-gc -spp-rematerialization-threshold=0 -S | FileCheck %s
+
+declare void @foo()
+
+; Trivial relocation over a single call
+define i8 addrspace(1)* @test1(i8 addrspace(1)* %obj) gc "statepoint-example" {
+; CHECK-LABEL: @test1
+; CHECK-LABEL: entry:
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: %obj.relocated = call coldcc i8 addrspace(1)*
+entry:
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  ret i8 addrspace(1)* %obj
+}
+
+; Two safepoints in a row (i.e. consistent liveness)
+define i8 addrspace(1)* @test2(i8 addrspace(1)* %obj) gc "statepoint-example" {
+; CHECK-LABEL: @test2
+; CHECK-LABEL: entry:
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: %obj.relocated = call coldcc i8 addrspace(1)*
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: %obj.relocated1 = call coldcc i8 addrspace(1)*
+entry:
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  ret i8 addrspace(1)* %obj
+}
+
+; A simple derived pointer
+define i8 @test3(i8 addrspace(1)* %obj) gc "statepoint-example" {
+; CHECK-LABEL: entry:
+; CHECK-NEXT: getelementptr
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: %derived.relocated = call coldcc i8 addrspace(1)*
+; CHECK-NEXT: %obj.relocated = call coldcc i8 addrspace(1)*
+; CHECK-NEXT: load i8, i8 addrspace(1)* %derived.relocated
+; CHECK-NEXT: load i8, i8 addrspace(1)* %obj.relocated
+entry:
+  %derived = getelementptr i8, i8 addrspace(1)* %obj, i64 10
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+
+  %a = load i8, i8 addrspace(1)* %derived
+  %b = load i8, i8 addrspace(1)* %obj
+  %c = sub i8 %a, %b
+  ret i8 %c
+}
+
+; Tests to make sure we visit both the taken and untaken predeccessor 
+; of merge.  This was a bug in the dataflow liveness at one point.
+define i8 addrspace(1)* @test4(i1 %cmp, i8 addrspace(1)* %obj) gc "statepoint-example" {
+entry:
+  br i1 %cmp, label %taken, label %untaken
+
+taken:
+; CHECK-LABEL: taken:
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: %obj.relocated = call coldcc i8 addrspace(1)*
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  br label %merge
+
+untaken:
+; CHECK-LABEL: untaken:
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: %obj.relocated1 = call coldcc i8 addrspace(1)*
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  br label %merge
+
+merge:
+; CHECK-LABEL: merge:
+; CHECK-NEXT: %.0 = phi i8 addrspace(1)* [ %obj.relocated, %taken ], [ %obj.relocated1, %untaken ]
+; CHECK-NEXT: ret i8 addrspace(1)* %.0
+  ret i8 addrspace(1)* %obj
+}
+
+; When run over a function which doesn't opt in, should do nothing!
+define i8 addrspace(1)* @test5(i8 addrspace(1)* %obj) gc "ocaml" {
+; CHECK-LABEL: @test5
+; CHECK-LABEL: entry:
+; CHECK-NEXT: gc.statepoint
+; CHECK-NOT: %obj.relocated = call coldcc i8 addrspace(1)*
+entry:
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  ret i8 addrspace(1)* %obj
+}
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
\ No newline at end of file
diff --git a/test/Transforms/RewriteStatepointsForGC/constants.ll b/test/Transforms/RewriteStatepointsForGC/constants.ll
new file mode 100644
index 000000000000..a30fdd7034a4
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/constants.ll
@@ -0,0 +1,60 @@
+; RUN: opt -S -rewrite-statepoints-for-gc %s | FileCheck %s
+
+declare void @foo()
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
+
+; constants don't get relocated.
+define i8 @test() gc "statepoint-example" {
+; CHECK-LABEL: @test
+; CHECK: gc.statepoint
+; CHECK-NEXT: load i8, i8 addrspace(1)* inttoptr (i64 15 to i8 addrspace(1)*)
+entry:
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  %res = load i8, i8 addrspace(1)* inttoptr (i64 15 to i8 addrspace(1)*)
+  ret i8 %res
+}
+
+
+; Mostly just here to show reasonable code test can come from.  
+define i8 @test2(i8 addrspace(1)* %p) gc "statepoint-example" {
+; CHECK-LABEL: @test2
+; CHECK: gc.statepoint
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: icmp
+entry:
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  %cmp = icmp eq i8 addrspace(1)* %p, null
+  br i1 %cmp, label %taken, label %not_taken
+
+taken:
+  ret i8 0
+
+not_taken:
+  %cmp2 = icmp ne i8 addrspace(1)* %p, null
+  br i1 %cmp2, label %taken, label %dead
+
+dead:
+  ; We see that dead can't be reached, but the optimizer might not.  It's 
+  ; completely legal for it to exploit the fact that if dead executed, %p 
+  ; would have to equal null.  This can produce intermediate states which 
+  ; look like that of test above, even if arbitrary constant addresses aren't
+  ; legal in the source language
+  %addr = getelementptr i8, i8 addrspace(1)* %p, i32 15
+  %res = load i8, i8addrspace(1)* %addr
+  ret i8 %res
+}
+
+@G = addrspace(1) global i8 5
+
+; Globals don't move and thus don't get relocated
+define i8 @test3(i1 %always_true) gc "statepoint-example" {
+; CHECK-LABEL: @test3
+; CHECK: gc.statepoint
+; CHECK-NEXT: load i8, i8 addrspace(1)* @G
+entry:
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  %res = load i8, i8 addrspace(1)* @G, align 1
+  ret i8 %res
+}
+
+
diff --git a/test/Transforms/RewriteStatepointsForGC/gc_relocate_creation.ll b/test/Transforms/RewriteStatepointsForGC/gc_relocate_creation.ll
new file mode 100644
index 000000000000..355ffa634f3c
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/gc_relocate_creation.ll
@@ -0,0 +1,20 @@
+; RUN: opt %s -rewrite-statepoints-for-gc -S 2>&1 | FileCheck %s
+; This test is to verify gc.relocate can handle pointer to vector of
+; pointers (<2 x i32 addrspace(1)*> addrspace(1)* in this case).
+; The old scheme to create a gc.relocate of <2 x i32 addrspace(1)*> addrspace(1)*
+; type will fail because llvm does not support mangling vector of pointers.
+; The new scheme will create all gc.relocate to i8 addrspace(1)* type and
+; then bitcast to the correct type.
+
+declare void @foo()
+declare void @use(...)
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
+
+define void @test1(<2 x i32 addrspace(1)*> addrspace(1)* %obj) gc "statepoint-example" {
+entry:
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+; CHECK: %obj.relocated = call coldcc i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(i32 %safepoint_token, i32 7, i32 7)
+; CHECK-NEXT:  %obj.relocated.casted = bitcast i8 addrspace(1)* %obj.relocated to <2 x i32 addrspace(1)*> addrspace(1)*
+  call void (...) @use(<2 x i32 addrspace(1)*> addrspace(1)* %obj)
+  ret void
+}
diff --git a/test/Transforms/RewriteStatepointsForGC/live-vector.ll b/test/Transforms/RewriteStatepointsForGC/live-vector.ll
new file mode 100644
index 000000000000..c49e101abe14
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/live-vector.ll
@@ -0,0 +1,121 @@
+; Test that we can correctly handle vectors of pointers in statepoint 
+; rewriting.  Currently, we scalarize, but that's an implementation detail.
+; RUN: opt %s -rewrite-statepoints-for-gc -S | FileCheck  %s
+
+; A non-vector relocation for comparison
+define i64 addrspace(1)* @test(i64 addrspace(1)* %obj) gc "statepoint-example" {
+; CHECK-LABEL: test
+; CHECK: gc.statepoint
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: ret i64 addrspace(1)* %obj.relocated.casted
+entry:
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+  ret i64 addrspace(1)* %obj
+}
+
+; A base vector from a argument
+define <2 x i64 addrspace(1)*> @test2(<2 x i64 addrspace(1)*> %obj) gc "statepoint-example" {
+; CHECK-LABEL: test2
+; CHECK: extractelement
+; CHECK-NEXT: extractelement
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: insertelement
+; CHECK-NEXT: insertelement
+; CHECK-NEXT: ret <2 x i64 addrspace(1)*> %7
+entry:
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+  ret <2 x i64 addrspace(1)*> %obj
+}
+
+; A base vector from a load
+define <2 x i64 addrspace(1)*> @test3(<2 x i64 addrspace(1)*>* %ptr) gc "statepoint-example" {
+; CHECK-LABEL: test3
+; CHECK: load
+; CHECK-NEXT: extractelement
+; CHECK-NEXT: extractelement
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: insertelement
+; CHECK-NEXT: insertelement
+; CHECK-NEXT: ret <2 x i64 addrspace(1)*> %7
+entry:
+  %obj = load <2 x i64 addrspace(1)*>, <2 x i64 addrspace(1)*>* %ptr
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+  ret <2 x i64 addrspace(1)*> %obj
+}
+
+declare i32 @fake_personality_function()
+
+; When a statepoint is an invoke rather than a call
+define <2 x i64 addrspace(1)*> @test4(<2 x i64 addrspace(1)*>* %ptr) gc "statepoint-example" {
+; CHECK-LABEL: test4
+; CHECK: load
+; CHECK-NEXT: extractelement
+; CHECK-NEXT: extractelement
+; CHECK-NEXT: gc.statepoint
+entry:
+  %obj = load <2 x i64 addrspace(1)*>, <2 x i64 addrspace(1)*>* %ptr
+  invoke i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+          to label %normal_return unwind label %exceptional_return
+
+; CHECK-LABEL: normal_return:
+; CHECK: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: insertelement
+; CHECK-NEXT: insertelement
+; CHECK-NEXT: ret <2 x i64 addrspace(1)*> %8
+normal_return:                                    ; preds = %entry
+  ret <2 x i64 addrspace(1)*> %obj
+
+; CHECK-LABEL: exceptional_return:
+; CHECK: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: insertelement
+; CHECK-NEXT: insertelement
+; CHECK-NEXT: ret <2 x i64 addrspace(1)*> %14
+exceptional_return:                               ; preds = %entry
+  %landing_pad4 = landingpad { i8*, i32 } personality i32 ()* @fake_personality_function
+          cleanup
+  ret <2 x i64 addrspace(1)*> %obj
+}
+
+; Can we handle an insert element with a constant offset?  This effectively
+; tests both the equal and inequal case since we have to relocate both indices
+; in the vector.
+define <2 x i64 addrspace(1)*> @test5(i64 addrspace(1)* %p) 
+     gc "statepoint-example" {
+; CHECK-LABEL: test5
+; CHECK: insertelement
+; CHECK-NEXT: extractelement
+; CHECK-NEXT: extractelement
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: insertelement
+; CHECK-NEXT: insertelement
+; CHECK-NEXT: ret <2 x i64 addrspace(1)*> %7
+entry:
+  %vec = insertelement <2 x i64 addrspace(1)*> undef, i64 addrspace(1)* %p, i32 0
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+  ret <2 x i64 addrspace(1)*> %vec
+}
+
+declare void @do_safepoint()
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
diff --git a/test/Transforms/RewriteStatepointsForGC/liveness-basics.ll b/test/Transforms/RewriteStatepointsForGC/liveness-basics.ll
new file mode 100644
index 000000000000..6bc4d5324494
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/liveness-basics.ll
@@ -0,0 +1,166 @@
+; A collection of liveness test cases to ensure we're reporting the
+; correct live values at statepoints
+; RUN: opt -rewrite-statepoints-for-gc -spp-rematerialization-threshold=0 -S < %s | FileCheck %s
+
+
+; Tests to make sure we consider %obj live in both the taken and untaken 
+; predeccessor of merge.
+define i64 addrspace(1)* @test1(i1 %cmp, i64 addrspace(1)* %obj) gc "statepoint-example" {
+; CHECK-LABEL: @test1
+entry:
+  br i1 %cmp, label %taken, label %untaken
+
+taken:
+; CHECK-LABEL: taken:
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: %obj.relocated = call coldcc i8 addrspace(1)*
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: br label %merge
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  br label %merge
+
+untaken:
+; CHECK-LABEL: untaken:
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: %obj.relocated1 = call coldcc i8 addrspace(1)*
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: br label %merge
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  br label %merge
+
+merge:
+; CHECK-LABEL: merge:
+; CHECK-NEXT: %.0 = phi i64 addrspace(1)* [ %obj.relocated.casted, %taken ], [ %obj.relocated1.casted, %untaken ]
+; CHECK-NEXT: ret i64 addrspace(1)* %.0
+  ret i64 addrspace(1)* %obj
+}
+
+; A local kill should not effect liveness in predecessor block
+define i64 addrspace(1)* @test2(i1 %cmp, i64 addrspace(1)** %loc) gc "statepoint-example" {
+; CHECK-LABEL: @test2
+entry:
+; CHECK-LABEL: entry:
+; CHECK-NEXT:  gc.statepoint
+; CHECK-NEXT:  br
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  br i1 %cmp, label %taken, label %untaken
+
+taken:
+; CHECK-LABEL: taken:
+; CHECK-NEXT:  %obj = load
+; CHECK-NEXT:  gc.statepoint
+; CHECK-NEXT:  gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT:  ret i64 addrspace(1)* %obj.relocated.casted
+
+  %obj = load i64 addrspace(1)*, i64 addrspace(1)** %loc
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  ret i64 addrspace(1)* %obj
+
+untaken:
+  ret i64 addrspace(1)* null
+}
+
+; A local kill should effect values live from a successor phi.  Also, we
+; should only propagate liveness from a phi to the appropriate predecessors.
+define i64 addrspace(1)* @test3(i1 %cmp, i64 addrspace(1)** %loc) gc "statepoint-example" {
+; CHECK-LABEL: @test3
+entry:
+  br i1 %cmp, label %taken, label %untaken
+
+taken:
+; CHECK-LABEL: taken:
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: %obj = load
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: %obj.relocated = call coldcc i8 addrspace(1)*
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: br label %merge
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  %obj = load i64 addrspace(1)*, i64 addrspace(1)** %loc
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  br label %merge
+
+untaken:
+; CHECK-LABEL: taken:
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: br label %merge
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  br label %merge
+
+merge:
+  %phi = phi i64 addrspace(1)* [ %obj, %taken ], [ null, %untaken ]
+  ret i64 addrspace(1)* %phi
+}
+
+; A base pointer must be live if it is needed at a later statepoint,
+; even if the base pointer is otherwise unused.
+define i64 addrspace(1)* @test4(i1 %cmp, i64 addrspace(1)* %obj) gc "statepoint-example" {
+; CHECK-LABEL: @test4
+entry:
+; CHECK-LABEL: entry:
+; CHECK-NEXT:  %derived = getelementptr
+; CHECK-NEXT:  gc.statepoint
+; CHECK-NEXT:  %derived.relocated =
+; CHECK-NEXT:  bitcast 
+; CHECK-NEXT:  %obj.relocated =
+; CHECK-NEXT:  bitcast
+; CHECK-NEXT:  gc.statepoint
+; CHECK-NEXT:  %derived.relocated1 =
+; CHECK-NEXT:  bitcast 
+; Note: It's legal to relocate obj again, but not strictly needed
+; CHECK-NEXT:  %obj.relocated2 =
+; CHECK-NEXT:  bitcast
+; CHECK-NEXT:  ret i64 addrspace(1)* %derived.relocated1.casted
+; 
+  %derived = getelementptr i64, i64 addrspace(1)* %obj, i64 8
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  ret i64 addrspace(1)* %derived
+}
+
+declare void @consume(...) readonly
+
+; Make sure that a phi def visited during iteration is considered a kill.
+; Also, liveness after base pointer analysis can change based on new uses,
+; not just new defs.
+define i64 addrspace(1)* @test5(i1 %cmp, i64 addrspace(1)* %obj) gc "statepoint-example" {
+; CHECK-LABEL: @test5
+entry:
+  br i1 %cmp, label %taken, label %untaken
+
+taken:
+; CHECK-LABEL: taken:
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: %obj.relocated = call coldcc i8 addrspace(1)*
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: br label %merge
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  br label %merge
+
+untaken:
+; CHECK-LABEL: untaken:
+; CHECK-NEXT: br label %merge
+  br label %merge
+
+merge:
+; CHECK-LABEL: merge:
+; CHECK-NEXT: %.0 = phi i64 addrspace(1)*
+; CHECK-NEXT: %obj2a = phi
+; CHECK-NEXT: @consume
+; CHECK-NEXT: br label %final
+  %obj2a = phi i64 addrspace(1)* [ %obj, %taken ], [null, %untaken]
+  call void (...) @consume(i64 addrspace(1)* %obj2a)
+  br label %final
+final:
+; CHECK-LABEL: final:
+; CHECK-NEXT: @consume
+; CHECK-NEXT: ret i64 addrspace(1)* %.0
+  call void (...) @consume(i64 addrspace(1)* %obj2a)
+  ret i64 addrspace(1)* %obj
+}
+
+declare void @foo()
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
diff --git a/test/Transforms/RewriteStatepointsForGC/preprocess.ll b/test/Transforms/RewriteStatepointsForGC/preprocess.ll
new file mode 100644
index 000000000000..60215310af02
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/preprocess.ll
@@ -0,0 +1,65 @@
+; RUN: opt -rewrite-statepoints-for-gc -S < %s | FileCheck %s
+
+declare void @consume(...)
+
+; Test to make sure we destroy LCSSA's single entry phi nodes before
+; running liveness
+define void @test6(i64 addrspace(1)* %obj) gc "statepoint-example" {
+; CHECK-LABEL: @test6
+entry:
+  br label %next
+
+next:
+; CHECK-LABEL: next:
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: @consume(i64 addrspace(1)* %obj.relocated.casted)
+; CHECK-NEXT: @consume(i64 addrspace(1)* %obj.relocated.casted)
+  %obj2 = phi i64 addrspace(1)* [ %obj, %entry ]
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  call void (...) @consume(i64 addrspace(1)* %obj2)
+  call void (...) @consume(i64 addrspace(1)* %obj)
+  ret void
+}
+
+declare void @some_call(i64 addrspace(1)*)
+
+; Need to delete unreachable gc.statepoint call
+define void @test7() gc "statepoint-example" {
+; CHECK-LABEL: test7
+; CHECK-NOT: gc.statepoint
+  ret void
+
+unreached:
+  %obj = phi i64 addrspace(1)* [null, %unreached]
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  call void (...) @consume(i64 addrspace(1)* %obj)
+  br label %unreached
+}
+
+; Need to delete unreachable gc.statepoint invoke - tested seperately given
+; a correct implementation could only remove the instructions, not the block
+define void @test8() gc "statepoint-example" {
+; CHECK-LABEL: test8
+; CHECK-NOT: gc.statepoint
+  ret void
+
+unreached:
+  invoke i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+          to label %normal_return unwind label %exceptional_return
+
+normal_return:                                    ; preds = %entry
+  ret void
+
+exceptional_return:                               ; preds = %entry
+  %landing_pad4 = landingpad { i8*, i32 } personality i32 ()* undef
+          cleanup
+  ret void
+}
+
+declare void @foo()
+; Bound the last check-not
+; CHECK-LABEL: @foo
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
diff --git a/test/Transforms/RewriteStatepointsForGC/relocate_invoke_result.ll b/test/Transforms/RewriteStatepointsForGC/relocate_invoke_result.ll
new file mode 100644
index 000000000000..9c00b53dfbb5
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/relocate_invoke_result.ll
@@ -0,0 +1,33 @@
+;; RUN: opt -rewrite-statepoints-for-gc -verify -S < %s | FileCheck %s
+
+;; This test is to verify that RewriteStatepointsForGC correctly relocates values
+;; defined by invoke instruction results. 
+
+declare i64* addrspace(1)* @non_gc_call()
+
+declare void @gc_call()
+
+declare i32* @fake_personality_function()
+
+; Function Attrs: nounwind
+define i64* addrspace(1)* @test() gc "statepoint-example" {
+entry:
+  %obj = invoke i64* addrspace(1)* @non_gc_call()
+          to label %normal_dest unwind label %unwind_dest
+
+unwind_dest: 
+  %lpad = landingpad { i8*, i32 } personality i32* ()* @fake_personality_function
+          cleanup
+  resume { i8*, i32 } undef
+
+normal_dest:
+;; CHECK-LABEL: normal_dest:
+;; CHECK-NEXT: gc.statepoint
+;; CHECK-NEXT: %obj.relocated = call coldcc i8 addrspace(1)*
+;; CHECK-NEXT: bitcast
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @gc_call, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  ret i64* addrspace(1)* %obj
+}
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
+
diff --git a/test/Transforms/RewriteStatepointsForGC/relocation.ll b/test/Transforms/RewriteStatepointsForGC/relocation.ll
new file mode 100644
index 000000000000..d7a84e5820c8
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/relocation.ll
@@ -0,0 +1,295 @@
+; RUN: opt %s -rewrite-statepoints-for-gc -spp-rematerialization-threshold=0 -S 2>&1 | FileCheck %s
+
+
+declare void @foo()
+declare void @use(...)
+
+define i64 addrspace(1)* @test1(i64 addrspace(1)* %obj, i64 addrspace(1)* %obj2, i1 %condition) gc "statepoint-example" {
+entry:
+; CHECK-LABEL: @test1
+; CHECK-DAG: %obj.relocated
+; CHECK-DAG: %obj2.relocated
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  br label %joint
+
+joint:
+; CHECK-LABEL: joint:
+; CHECK: %phi1 = phi i64 addrspace(1)* [ %obj.relocated.casted, %entry ], [ %obj3, %joint2 ]
+  %phi1 = phi i64 addrspace(1)* [ %obj, %entry ], [ %obj3, %joint2 ]
+  br i1 %condition, label %use, label %joint2
+
+use:
+  br label %joint2
+
+joint2:
+; CHECK-LABEL: joint2:
+; CHECK: %phi2 = phi i64 addrspace(1)* [ %obj.relocated.casted, %use ], [ %obj2.relocated.casted, %joint ]
+; CHECK: %obj3 = getelementptr i64, i64 addrspace(1)* %obj2.relocated.casted, i32 1
+  %phi2 = phi i64 addrspace(1)* [ %obj, %use ], [ %obj2, %joint ]
+  %obj3 = getelementptr i64, i64 addrspace(1)* %obj2, i32 1
+  br label %joint
+}
+
+declare i64 addrspace(1)* @generate_obj()
+
+declare void @consume_obj(i64 addrspace(1)*)
+
+declare i1 @rt()
+
+define void @test2() gc "statepoint-example" {
+; CHECK-LABEL: @test2
+entry:
+  %obj_init = call i64 addrspace(1)* @generate_obj()
+  %obj = getelementptr i64, i64 addrspace(1)* %obj_init, i32 42
+  br label %loop
+
+loop:
+; CHECK: loop:
+; CHECK-DAG: [ %obj_init.relocated.casted, %loop.backedge ]
+; CHECK-DAG: [ %obj_init, %entry ]
+; CHECK-DAG: [ %obj.relocated.casted, %loop.backedge ]
+; CHECK-DAG: [ %obj, %entry ]
+  %index = phi i32 [ 0, %entry ], [ %index.inc, %loop.backedge ]
+; CHECK-NOT: %location = getelementptr i64, i64 addrspace(1)* %obj, i32 %index
+  %location = getelementptr i64, i64 addrspace(1)* %obj, i32 %index
+  call void @consume_obj(i64 addrspace(1)* %location)
+  %index.inc = add i32 %index, 1
+  %condition = call i1 @rt()
+  br i1 %condition, label %loop_x, label %loop_y
+
+loop_x:
+  br label %loop.backedge
+
+loop.backedge:
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+  br label %loop
+
+loop_y:
+  br label %loop.backedge
+}
+
+declare void @some_call(i8 addrspace(1)*)
+
+define void @relocate_merge(i1 %cnd, i8 addrspace(1)* %arg) gc "statepoint-example" {
+; CHECK-LABEL: @relocate_merge
+bci_0:
+  br i1 %cnd, label %if_branch, label %else_branch
+
+if_branch:
+; CHECK-LABEL: if_branch:
+; CHECK: gc.statepoint
+; CHECK: gc.relocate
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  br label %join
+
+else_branch:
+; CHECK-LABEL: else_branch:
+; CHECK: gc.statepoint
+; CHECK: gc.relocate
+  %safepoint_token1 = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0)
+  br label %join
+
+join:
+; We need to end up with a single relocation phi updated from both paths 
+; CHECK-LABEL: join:
+; CHECK: phi i8 addrspace(1)*
+; CHECK-DAG: [ %arg.relocated, %if_branch ]
+; CHECK-DAG: [ %arg.relocated4, %else_branch ]
+; CHECK-NOT: phi
+  call void (i8 addrspace(1)*) @some_call(i8 addrspace(1)* %arg)
+  ret void
+}
+
+; Make sure a use in a statepoint gets properly relocated at a previous one.  
+; This is basically just making sure that statepoints aren't accidentally 
+; treated specially.
+define void @test3(i64 addrspace(1)* %obj) gc "statepoint-example" {
+entry:
+; CHECK-LABEL: @test3
+; CHECK: gc.statepoint
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: gc.statepoint
+  %safepoint_token = call i32 (i64, i32, void (i64)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi64f(i64 0, i32 0, void (i64)* undef, i32 1, i32 0, i64 undef, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  %safepoint_token1 = call i32 (i64, i32, i32 (i64 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i32p1i64f(i64 0, i32 0, i32 (i64 addrspace(1)*)* undef, i32 1, i32 0, i64 addrspace(1)* %obj, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  ret void
+}
+
+; Check specifically for the case where the result of a statepoint needs to 
+; be relocated itself
+define void @test4() gc "statepoint-example" {
+; CHECK-LABEL: @test4
+; CHECK: gc.statepoint
+; CHECK: gc.result
+; CHECK: gc.statepoint
+; CHECK: gc.relocate
+; CHECK: @use(i8 addrspace(1)* %res.relocated)
+  %safepoint_token2 = tail call i32 (i64, i32, i8 addrspace(1)* ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_p1i8f(i64 0, i32 0, i8 addrspace(1)* ()* undef, i32 0, i32 0, i32 0, i32 0)
+  %res = call i8 addrspace(1)* @llvm.experimental.gc.result.ptr.p1i8(i32 %safepoint_token2)
+  call i32 (i64, i32, i8 addrspace(1)* ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_p1i8f(i64 0, i32 0, i8 addrspace(1)* ()* undef, i32 0, i32 0, i32 0, i32 0)
+  call void (...) @use(i8 addrspace(1)* %res)
+  unreachable
+}
+
+
+; Test updating a phi where not all inputs are live to begin with
+define void @test5(i8 addrspace(1)* %arg) gc "statepoint-example" {
+; CHECK-LABEL: test5
+entry:
+  call i32 (i64, i32, i8 addrspace(1)* ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_p1i8f(i64 0, i32 0, i8 addrspace(1)* ()* undef, i32 0, i32 0, i32 0, i32 0)
+  switch i32 undef, label %kill [
+    i32 10, label %merge
+    i32 13, label %merge
+  ]
+
+kill:
+  br label %merge
+
+merge:
+; CHECK: merge:
+; CHECK: %test = phi i8 addrspace(1)
+; CHECK-DAG: [ null, %kill ]
+; CHECK-DAG: [ %arg.relocated, %entry ]
+; CHECK-DAG: [ %arg.relocated, %entry ]
+  %test = phi i8 addrspace(1)* [ null, %kill ], [ %arg, %entry ], [ %arg, %entry ]
+  call void (...) @use(i8 addrspace(1)* %test)
+  unreachable
+}
+
+
+; Check to make sure we handle values live over an entry statepoint
+define void @test6(i8 addrspace(1)* %arg1, i8 addrspace(1)* %arg2, 
+                  i8 addrspace(1)* %arg3) gc "statepoint-example" {
+; CHECK-LABEL: @test6
+entry:
+  br i1 undef, label %gc.safepoint_poll.exit2, label %do_safepoint
+
+do_safepoint:
+; CHECK-LABEL: do_safepoint:
+; CHECK: gc.statepoint
+; CHECK: arg1.relocated = 
+; CHECK: arg2.relocated = 
+; CHECK: arg3.relocated = 
+  call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 3, i8 addrspace(1)* %arg1, i8 addrspace(1)* %arg2, i8 addrspace(1)* %arg3)
+  br label %gc.safepoint_poll.exit2
+
+gc.safepoint_poll.exit2:
+; CHECK-LABEL: gc.safepoint_poll.exit2:
+; CHECK: phi i8 addrspace(1)*
+; CHECK-DAG: [ %arg3, %entry ]
+; CHECK-DAG: [ %arg3.relocated, %do_safepoint ]
+; CHECK: phi i8 addrspace(1)*
+; CHECK-DAG: [ %arg2, %entry ]
+; CHECK-DAG: [ %arg2.relocated, %do_safepoint ]
+; CHECK: phi i8 addrspace(1)*
+; CHECK-DAG: [ %arg1, %entry ]
+; CHECK-DAG:  [ %arg1.relocated, %do_safepoint ]
+  call void (...) @use(i8 addrspace(1)* %arg1, i8 addrspace(1)* %arg2, i8 addrspace(1)* %arg3)
+  ret void
+}
+
+; Check relocation in a loop nest where a relocation happens in the outer
+; but not the inner loop
+define void @test_outer_loop(i8 addrspace(1)* %arg1, i8 addrspace(1)* %arg2, 
+                  i1 %cmp) gc "statepoint-example" {
+; CHECK-LABEL: @test_outer_loop
+bci_0:
+  br label %outer-loop
+
+outer-loop:
+; CHECK-LABEL: outer-loop:
+; CHECK: phi i8 addrspace(1)* [ %arg2, %bci_0 ], [ %arg2.relocated, %outer-inc ]
+; CHECK: phi i8 addrspace(1)* [ %arg1, %bci_0 ], [ %arg1.relocated, %outer-inc ]
+  br label %inner-loop
+
+inner-loop:
+  br i1 %cmp, label %inner-loop, label %outer-inc
+
+outer-inc:
+; CHECK-LABEL: outer-inc:
+; CHECK: %arg1.relocated
+; CHECK: %arg2.relocated
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 2, i8 addrspace(1)* %arg1, i8 addrspace(1)* %arg2)
+  br label %outer-loop
+}
+
+; Check that both inner and outer loops get phis when relocation is in
+;  inner loop
+define void @test_inner_loop(i8 addrspace(1)* %arg1, i8 addrspace(1)* %arg2, 
+                  i1 %cmp) gc "statepoint-example" {
+; CHECK-LABEL: @test_inner_loop
+bci_0:
+  br label %outer-loop
+
+outer-loop:
+; CHECK-LABEL: outer-loop:
+; CHECK: phi i8 addrspace(1)* [ %arg2, %bci_0 ], [ %arg2.relocated, %outer-inc ]
+; CHECK: phi i8 addrspace(1)* [ %arg1, %bci_0 ], [ %arg1.relocated, %outer-inc ]
+  br label %inner-loop
+
+inner-loop:
+; CHECK-LABEL: inner-loop
+; CHECK: phi i8 addrspace(1)* 
+; CHECK-DAG: %outer-loop ]
+; CHECK-DAG: [ %arg2.relocated, %inner-loop ]
+; CHECKL phi i8 addrspace(1)* 
+; CHECK-DAG: %outer-loop ]
+; CHECK-DAG: [ %arg1.relocated, %inner-loop ]
+; CHECK: gc.statepoint
+; CHECK: %arg1.relocated
+; CHECK: %arg2.relocated
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 2, i8 addrspace(1)* %arg1, i8 addrspace(1)* %arg2)
+  br i1 %cmp, label %inner-loop, label %outer-inc
+
+outer-inc:
+; CHECK-LABEL: outer-inc:
+  br label %outer-loop
+}
+
+
+; This test shows why updating just those uses of the original value being
+; relocated dominated by the inserted relocation is not always sufficient.
+define i64 addrspace(1)* @test7(i64 addrspace(1)* %obj, i64 addrspace(1)* %obj2, i1 %condition) gc "statepoint-example" {
+; CHECK-LABEL: @test7
+entry:
+  br i1 %condition, label %branch2, label %join
+
+branch2:
+  br i1 %condition, label %callbb, label %join2
+
+callbb:
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0)
+  br label %join
+
+join:
+; CHECK-LABEL: join:
+; CHECK: phi i64 addrspace(1)* [ %obj.relocated.casted, %callbb ], [ %obj, %entry ]
+; CHECK: phi i64 addrspace(1)* 
+; CHECK-DAG: [ %obj, %entry ]
+; CHECK-DAG: [ %obj2.relocated.casted, %callbb ]
+  ; This is a phi outside the dominator region of the new defs inserted by
+  ; the safepoint, BUT we can't stop the search here or we miss the second
+  ; phi below.
+  %phi1 = phi i64 addrspace(1)* [ %obj, %entry ], [ %obj2, %callbb ]
+  br label %join2
+
+join2:
+; CHECK-LABEL: join2:
+; CHECK: phi2 = phi i64 addrspace(1)* 
+; CHECK-DAG: %join ] 
+; CHECK-DAG:  [ %obj2, %branch2 ]
+  %phi2 = phi i64 addrspace(1)* [ %obj, %join ], [ %obj2, %branch2 ]
+  ret i64 addrspace(1)* %phi2
+}
+
+
+declare void @do_safepoint()
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
+declare i32 @llvm.experimental.gc.statepoint.p0f_p1i8f(i64, i32, i8 addrspace(1)* ()*, i32, i32, ...)
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidi64f(i64, i32, void (i64)*, i32, i32, ...)
+declare i32 @llvm.experimental.gc.statepoint.p0f_i32p1i64f(i64, i32, i32 (i64 addrspace(1)*)*, i32, i32, ...)
+declare i8 addrspace(1)* @llvm.experimental.gc.result.ptr.p1i8(i32) #3
+
+
+
diff --git a/test/Transforms/RewriteStatepointsForGC/rematerialize-derived-pointers.ll b/test/Transforms/RewriteStatepointsForGC/rematerialize-derived-pointers.ll
new file mode 100644
index 000000000000..dc52bd88776b
--- /dev/null
+++ b/test/Transforms/RewriteStatepointsForGC/rematerialize-derived-pointers.ll
@@ -0,0 +1,222 @@
+; RUN: opt %s -rewrite-statepoints-for-gc -S 2>&1 | FileCheck %s
+
+declare void @use_obj16(i16 addrspace(1)*)
+declare void @use_obj32(i32 addrspace(1)*)
+declare void @use_obj64(i64 addrspace(1)*)
+declare void @do_safepoint()
+
+define void @"test_gep_const"(i32 addrspace(1)* %base) gc "statepoint-example" {
+; CHECK-LABEL: test_gep_const
+entry:
+  %ptr = getelementptr i32, i32 addrspace(1)* %base, i32 15
+  ; CHECK: getelementptr i32, i32 addrspace(1)* %base, i32 15
+  %sp = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+  ; CHECK: %base.relocated = call coldcc i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(i32 %sp, i32 7, i32 7)
+  ; CHECK: bitcast i8 addrspace(1)* %base.relocated to i32 addrspace(1)*
+  ; CHECK: getelementptr i32, i32 addrspace(1)* %base.relocated.casted, i32 15
+  call void @use_obj32(i32 addrspace(1)* %base)
+  call void @use_obj32(i32 addrspace(1)* %ptr)
+  ret void
+}
+
+define void @"test_gep_idx"(i32 addrspace(1)* %base, i32 %idx) gc "statepoint-example" {
+; CHECK-LABEL: test_gep_idx
+entry:
+  %ptr = getelementptr i32, i32 addrspace(1)* %base, i32 %idx
+  ; CHECK: getelementptr
+  %sp = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+  ; CHECK: %base.relocated = call coldcc i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(i32 %sp, i32 7, i32 7)
+  ; CHECK: %base.relocated.casted = bitcast i8 addrspace(1)* %base.relocated to i32 addrspace(1)*
+  ; CHECK: getelementptr i32, i32 addrspace(1)* %base.relocated.casted, i32 %idx
+  call void @use_obj32(i32 addrspace(1)* %base)
+  call void @use_obj32(i32 addrspace(1)* %ptr)
+  ret void
+}
+
+define void @"test_bitcast"(i32 addrspace(1)* %base) gc "statepoint-example" {
+; CHECK-LABEL: test_bitcast
+entry:
+  %ptr = bitcast i32 addrspace(1)* %base to i64 addrspace(1)*
+  ; CHECK: bitcast i32 addrspace(1)* %base to i64 addrspace(1)*
+  %sp = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+  ; CHECK: %base.relocated = call coldcc i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(i32 %sp, i32 7, i32 7)
+  ; CHECK: %base.relocated.casted = bitcast i8 addrspace(1)* %base.relocated to i32 addrspace(1)*
+  ; CHECK: bitcast i32 addrspace(1)* %base.relocated.casted to i64 addrspace(1)*
+  call void @use_obj32(i32 addrspace(1)* %base)
+  call void @use_obj64(i64 addrspace(1)* %ptr)
+  ret void
+}
+
+define void @"test_bitcast_gep"(i32 addrspace(1)* %base) gc "statepoint-example" {
+; CHECK-LABEL: test_bitcast_gep
+entry:
+  %ptr.gep = getelementptr i32, i32 addrspace(1)* %base, i32 15
+  ; CHECK: getelementptr
+  %ptr.cast = bitcast i32 addrspace(1)* %ptr.gep to i64 addrspace(1)*
+  ; CHECK: bitcast
+  %sp = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+  ; CHECK: gc.relocate
+  ; CHECK: bitcast
+  ; CHECK: getelementptr
+  ; CHECK: bitcast
+  call void @use_obj32(i32 addrspace(1)* %base)
+  call void @use_obj64(i64 addrspace(1)* %ptr.cast)
+  ret void
+}
+
+define void @"test_intersecting_chains"(i32 addrspace(1)* %base, i32 %idx) gc "statepoint-example" {
+; CHECK-LABEL: test_intersecting_chains
+entry:
+  %ptr.gep = getelementptr i32, i32 addrspace(1)* %base, i32 15
+  ; CHECK: getelementptr
+  %ptr.cast = bitcast i32 addrspace(1)* %ptr.gep to i64 addrspace(1)*
+  ; CHECK: bitcast
+  %ptr.cast2 = bitcast i32 addrspace(1)* %ptr.gep to i16 addrspace(1)*
+  ; CHECK: bitcast
+  %sp = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+  ; CHECK: getelementptr
+  ; CHECK: bitcast
+  ; CHECK: getelementptr
+  ; CHECK: bitcast
+  call void @use_obj64(i64 addrspace(1)* %ptr.cast)
+  call void @use_obj16(i16 addrspace(1)* %ptr.cast2)
+  ret void
+}
+
+define void @"test_cost_threshold"(i32 addrspace(1)* %base, i32 %idx1, i32 %idx2, i32 %idx3) gc "statepoint-example" {
+; CHECK-LABEL: test_cost_threshold
+entry:
+  %ptr.gep = getelementptr i32, i32 addrspace(1)* %base, i32 15
+  ; CHECK: getelementptr
+  %ptr.gep2 = getelementptr i32, i32 addrspace(1)* %ptr.gep, i32 %idx1
+  ; CHECK: getelementptr
+  %ptr.gep3 = getelementptr i32, i32 addrspace(1)* %ptr.gep2, i32 %idx2
+  ; CHECK: getelementptr
+  %ptr.gep4 = getelementptr i32, i32 addrspace(1)* %ptr.gep3, i32 %idx3
+  ; CHECK: getelementptr
+  %ptr.cast = bitcast i32 addrspace(1)* %ptr.gep4 to i64 addrspace(1)*
+  ; CHECK: bitcast
+  %sp = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+  ; CHECK: gc.relocate
+  ; CHECK: bitcast
+  ; CHECK: gc.relocate
+  ; CHECK: bitcast
+  call void @use_obj64(i64 addrspace(1)* %ptr.cast)
+  ret void
+}
+
+define void @"test_two_derived"(i32 addrspace(1)* %base) gc "statepoint-example" {
+; CHECK-LABEL: test_two_derived
+entry:
+  %ptr = getelementptr i32, i32 addrspace(1)* %base, i32 15
+  %ptr2 = getelementptr i32, i32 addrspace(1)* %base, i32 12
+  ; CHECK: getelementptr
+  ; CHECK: getelementptr
+  %sp = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+  ; CHECK: gc.relocate
+  ; CHECK: bitcast
+  ; CHECK: getelementptr
+  ; CHECK: getelementptr
+  call void @use_obj32(i32 addrspace(1)* %ptr)
+  call void @use_obj32(i32 addrspace(1)* %ptr2)
+  ret void
+}
+
+define void @"test_gep_smallint_array"([3 x i32] addrspace(1)* %base) gc "statepoint-example" {
+; CHECK-LABEL: test_gep_smallint_array
+entry:
+  %ptr = getelementptr [3 x i32], [3 x i32] addrspace(1)* %base, i32 0, i32 2
+  ; CHECK: getelementptr
+  %sp = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+  ; CHECK: gc.relocate
+  ; CHECK: bitcast
+  ; CHECK: getelementptr
+  call void @use_obj32(i32 addrspace(1)* %ptr)
+  ret void
+}
+
+declare i32 @fake_personality_function()
+
+define void @"test_invoke"(i32 addrspace(1)* %base) gc "statepoint-example" {
+; CHECK-LABEL: test_invoke
+entry:
+  %ptr.gep = getelementptr i32, i32 addrspace(1)* %base, i32 15
+  ; CHECK: getelementptr
+  %ptr.cast = bitcast i32 addrspace(1)* %ptr.gep to i64 addrspace(1)*
+  ; CHECK: bitcast
+  %ptr.cast2 = bitcast i32 addrspace(1)* %ptr.gep to i16 addrspace(1)*
+  ; CHECK: bitcast
+  %sp = invoke i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+                to label %normal unwind label %exception
+
+normal:
+  ; CHECK-LABEL: normal:
+  ; CHECK: gc.relocate
+  ; CHECK: bitcast
+  ; CHECK: getelementptr
+  ; CHECK: bitcast
+  ; CHECK: getelementptr
+  ; CHECK: bitcast
+  call void @use_obj64(i64 addrspace(1)* %ptr.cast)
+  call void @use_obj16(i16 addrspace(1)* %ptr.cast2)
+  ret void
+
+exception:
+  ; CHECK-LABEL: exception:
+  %landing_pad4 = landingpad { i8*, i32 } personality i32 ()* @fake_personality_function
+          cleanup
+  ; CHECK: gc.relocate
+  ; CHECK: bitcast
+  ; CHECK: getelementptr
+  ; CHECK: bitcast
+  ; CHECK: getelementptr
+  ; CHECK: bitcast
+  call void @use_obj64(i64 addrspace(1)* %ptr.cast)
+  call void @use_obj16(i16 addrspace(1)* %ptr.cast2)
+  ret void
+}
+
+define void @"test_loop"(i32 addrspace(1)* %base) gc "statepoint-example" {
+; CHECK-LABEL: test_loop
+entry:
+  %ptr.gep = getelementptr i32, i32 addrspace(1)* %base, i32 15
+  ; CHECK: getelementptr
+  br label %loop
+
+loop:
+  ; CHECK: phi i32 addrspace(1)* [ %ptr.gep, %entry ], [ %ptr.gep.remat, %loop ]
+  ; CHECK: phi i32 addrspace(1)* [ %base, %entry ], [ %base.relocated.casted, %loop ]
+  call void @use_obj32(i32 addrspace(1)* %ptr.gep)
+  %sp = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+  ; CHECK: gc.relocate
+  ; CHECK: bitcast
+  ; CHECK: getelementptr
+  br label %loop
+}
+
+define void @"test_too_long"(i32 addrspace(1)* %base) gc "statepoint-example" {
+; CHECK-LABEL: test_too_long
+entry:
+  %ptr.gep   = getelementptr i32, i32 addrspace(1)* %base, i32 15
+  %ptr.gep1  = getelementptr i32, i32 addrspace(1)* %ptr.gep, i32 15
+  %ptr.gep2  = getelementptr i32, i32 addrspace(1)* %ptr.gep1, i32 15
+  %ptr.gep3  = getelementptr i32, i32 addrspace(1)* %ptr.gep2, i32 15
+  %ptr.gep4  = getelementptr i32, i32 addrspace(1)* %ptr.gep3, i32 15
+  %ptr.gep5  = getelementptr i32, i32 addrspace(1)* %ptr.gep4, i32 15
+  %ptr.gep6  = getelementptr i32, i32 addrspace(1)* %ptr.gep5, i32 15
+  %ptr.gep7  = getelementptr i32, i32 addrspace(1)* %ptr.gep6, i32 15
+  %ptr.gep8  = getelementptr i32, i32 addrspace(1)* %ptr.gep7, i32 15
+  %ptr.gep9  = getelementptr i32, i32 addrspace(1)* %ptr.gep8, i32 15
+  %ptr.gep10 = getelementptr i32, i32 addrspace(1)* %ptr.gep9, i32 15
+  %ptr.gep11 = getelementptr i32, i32 addrspace(1)* %ptr.gep10, i32 15
+  %sp = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0)
+  ; CHECK: gc.relocate
+  ; CHECK: bitcast
+  ; CHECK: gc.relocate
+  ; CHECK: bitcast
+  call void @use_obj32(i32 addrspace(1)* %ptr.gep11)
+  ret void
+}
+
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
diff --git a/test/Transforms/SCCP/2002-08-30-GetElementPtrTest.ll b/test/Transforms/SCCP/2002-08-30-GetElementPtrTest.ll
index 6aaf33ec206c..7b88a669ffba 100644
--- a/test/Transforms/SCCP/2002-08-30-GetElementPtrTest.ll
+++ b/test/Transforms/SCCP/2002-08-30-GetElementPtrTest.ll
@@ -3,7 +3,7 @@
 @G = external global [40 x i32]		; <[40 x i32]*> [#uses=1]
 
 define i32* @test() {
-	%X = getelementptr [40 x i32]* @G, i64 0, i64 0		; <i32*> [#uses=1]
+	%X = getelementptr [40 x i32], [40 x i32]* @G, i64 0, i64 0		; <i32*> [#uses=1]
 	ret i32* %X
 }
 
diff --git a/test/Transforms/SCCP/2003-06-24-OverdefinedPHIValue.ll b/test/Transforms/SCCP/2003-06-24-OverdefinedPHIValue.ll
index 576f5d6504d1..e5a1d679fc29 100644
--- a/test/Transforms/SCCP/2003-06-24-OverdefinedPHIValue.ll
+++ b/test/Transforms/SCCP/2003-06-24-OverdefinedPHIValue.ll
@@ -3,7 +3,7 @@
 
 define void @cprop_test11(i32* %data.1) {
 entry:
-	%tmp.1 = load i32* %data.1		; <i32> [#uses=3]
+	%tmp.1 = load i32, i32* %data.1		; <i32> [#uses=3]
 	%tmp.41 = icmp sgt i32 %tmp.1, 1		; <i1> [#uses=1]
 	br i1 %tmp.41, label %no_exit, label %loopexit
 no_exit:		; preds = %endif, %then, %entry
@@ -22,9 +22,9 @@ endif:		; preds = %no_exit
 loopexit:		; preds = %endif, %then, %entry
 	%j.1 = phi i32 [ 1, %entry ], [ %j.0, %endif ], [ %i.0, %then ]		; <i32> [#uses=1]
 	%i.1 = phi i32 [ 1, %entry ], [ %inc, %endif ], [ %inc1, %then ]		; <i32> [#uses=1]
-	%tmp.17 = getelementptr i32* %data.1, i64 1		; <i32*> [#uses=1]
+	%tmp.17 = getelementptr i32, i32* %data.1, i64 1		; <i32*> [#uses=1]
 	store i32 %j.1, i32* %tmp.17
-	%tmp.23 = getelementptr i32* %data.1, i64 2		; <i32*> [#uses=1]
+	%tmp.23 = getelementptr i32, i32* %data.1, i64 2		; <i32*> [#uses=1]
 	store i32 %i.1, i32* %tmp.23
 	ret void
 }
diff --git a/test/Transforms/SCCP/2006-10-23-IPSCCP-Crash.ll b/test/Transforms/SCCP/2006-10-23-IPSCCP-Crash.ll
index 47f9cb45cc67..9724e6ebc24e 100644
--- a/test/Transforms/SCCP/2006-10-23-IPSCCP-Crash.ll
+++ b/test/Transforms/SCCP/2006-10-23-IPSCCP-Crash.ll
@@ -37,7 +37,7 @@ cond_next50:		; preds = %entry
 	%tmp52 = icmp sgt i32 %D, 0		; <i1> [#uses=1]
 	br i1 %tmp52, label %cond_true53, label %cond_next71
 cond_true53:		; preds = %cond_next50
-	%tmp54 = load i32* @JUMP		; <i32> [#uses=1]
+	%tmp54 = load i32, i32* @JUMP		; <i32> [#uses=1]
 	%tmp55 = icmp eq i32 %tmp54, 1		; <i1> [#uses=1]
 	br i1 %tmp55, label %cond_true56, label %cond_next63
 cond_true56:		; preds = %cond_true53
@@ -67,9 +67,9 @@ bb217:		; preds = %cond_true260
 	ret void
 cond_next252:		; preds = %cond_next208, %entry
 	%D.0.0 = phi i32 [ 0, %entry ], [ %tmp229, %cond_next208 ]		; <i32> [#uses=1]
-	%tmp254 = getelementptr i8** null, i32 1		; <i8**> [#uses=1]
-	%tmp256 = load i8** %tmp254		; <i8*> [#uses=1]
-	%tmp258 = load i8* %tmp256		; <i8> [#uses=1]
+	%tmp254 = getelementptr i8*, i8** null, i32 1		; <i8**> [#uses=1]
+	%tmp256 = load i8*, i8** %tmp254		; <i8*> [#uses=1]
+	%tmp258 = load i8, i8* %tmp256		; <i8> [#uses=1]
 	%tmp259 = icmp eq i8 %tmp258, 45		; <i1> [#uses=1]
 	br i1 %tmp259, label %cond_true260, label %bb263
 cond_true260:		; preds = %cond_next252
diff --git a/test/Transforms/SCCP/2006-12-04-PackedType.ll b/test/Transforms/SCCP/2006-12-04-PackedType.ll
index cee334987218..05cf5fffd2b6 100644
--- a/test/Transforms/SCCP/2006-12-04-PackedType.ll
+++ b/test/Transforms/SCCP/2006-12-04-PackedType.ll
@@ -103,14 +103,14 @@ target triple = "powerpc-apple-darwin8"
 
 define void @gldLLVMVecPointRender(%struct.GLDContextRec* %ctx) {
 entry:
-	%tmp.uip = getelementptr %struct.GLDContextRec* %ctx, i32 0, i32 22		; <i32*> [#uses=1]
-	%tmp = load i32* %tmp.uip		; <i32> [#uses=3]
+	%tmp.uip = getelementptr %struct.GLDContextRec, %struct.GLDContextRec* %ctx, i32 0, i32 22		; <i32*> [#uses=1]
+	%tmp = load i32, i32* %tmp.uip		; <i32> [#uses=3]
 	%tmp91 = lshr i32 %tmp, 5		; <i32> [#uses=1]
 	%tmp92 = trunc i32 %tmp91 to i1		; <i1> [#uses=1]
 	br i1 %tmp92, label %cond_true93, label %cond_next116
 cond_true93:		; preds = %entry
-	%tmp.upgrd.1 = getelementptr %struct.GLDContextRec* %ctx, i32 0, i32 31, i32 14		; <i32*> [#uses=1]
-	%tmp95 = load i32* %tmp.upgrd.1		; <i32> [#uses=1]
+	%tmp.upgrd.1 = getelementptr %struct.GLDContextRec, %struct.GLDContextRec* %ctx, i32 0, i32 31, i32 14		; <i32*> [#uses=1]
+	%tmp95 = load i32, i32* %tmp.upgrd.1		; <i32> [#uses=1]
 	%tmp95.upgrd.2 = sitofp i32 %tmp95 to float		; <float> [#uses=1]
 	%tmp108 = fmul float undef, %tmp95.upgrd.2		; <float> [#uses=1]
 	br label %cond_next116
diff --git a/test/Transforms/SCCP/2009-05-27-VectorOperandZero.ll b/test/Transforms/SCCP/2009-05-27-VectorOperandZero.ll
index 7aced6635272..1ac6bcd8b4ec 100644
--- a/test/Transforms/SCCP/2009-05-27-VectorOperandZero.ll
+++ b/test/Transforms/SCCP/2009-05-27-VectorOperandZero.ll
@@ -3,7 +3,7 @@
 
 define i32 @main() nounwind {
 entry:
-	%0 = tail call signext i8 (...)* @sin() nounwind
+	%0 = tail call signext i8 (...) @sin() nounwind
 	ret i32 0
 }
 
diff --git a/test/Transforms/SCCP/apint-array.ll b/test/Transforms/SCCP/apint-array.ll
index 888b9e1d22d5..eff6cc997e35 100644
--- a/test/Transforms/SCCP/apint-array.ll
+++ b/test/Transforms/SCCP/apint-array.ll
@@ -6,16 +6,16 @@
 define i101 @array()
 {
 Head:
-   %A = getelementptr [6 x i101]* @Y, i32 0, i32 1
+   %A = getelementptr [6 x i101], [6 x i101]* @Y, i32 0, i32 1
 
-   %B = load i101* %A
+   %B = load i101, i101* %A
    %C = icmp sge i101 %B, 1
    br i1 %C, label %True, label %False
 True:
    %D = and i101 %B, 1
    %E = trunc i101 %D to i32
-   %F = getelementptr [6 x i101]* @Y, i32 0, i32 %E
-   %G = load i101* %F
+   %F = getelementptr [6 x i101], [6 x i101]* @Y, i32 0, i32 %E
+   %G = load i101, i101* %F
    br label %False
 False:
    %H = phi i101 [%G, %True], [-1, %Head]
diff --git a/test/Transforms/SCCP/apint-bigarray.ll b/test/Transforms/SCCP/apint-bigarray.ll
index 0dd9ad331a07..e0231997f1bf 100644
--- a/test/Transforms/SCCP/apint-bigarray.ll
+++ b/test/Transforms/SCCP/apint-bigarray.ll
@@ -3,7 +3,7 @@
 @G =  global [1000000 x i10000] zeroinitializer
 
 define internal i10000* @test(i10000 %Arg) {
-	%X = getelementptr [1000000 x i10000]* @G, i32 0, i32 999
+	%X = getelementptr [1000000 x i10000], [1000000 x i10000]* @G, i32 0, i32 999
         store i10000 %Arg, i10000* %X
 	ret i10000* %X
 }
@@ -11,13 +11,13 @@ define internal i10000* @test(i10000 %Arg) {
 define i10000 @caller()
 {
         %Y = call i10000* @test(i10000 -1)
-        %Z = load i10000* %Y
+        %Z = load i10000, i10000* %Y
         ret i10000 %Z 
 }
 
 define i10000 @caller2()
 {
         %Y = call i10000* @test(i10000 1)
-        %Z = load i10000* %Y
+        %Z = load i10000, i10000* %Y
         ret i10000 %Z 
 }
diff --git a/test/Transforms/SCCP/apint-bigint2.ll b/test/Transforms/SCCP/apint-bigint2.ll
index 660eaad7bc12..f28b966aceba 100644
--- a/test/Transforms/SCCP/apint-bigint2.ll
+++ b/test/Transforms/SCCP/apint-bigint2.ll
@@ -6,13 +6,13 @@
 define i101 @array()
 {
 Head:
-   %A = getelementptr [6 x i101]* @Y, i32 0, i32 1
-   %B = load i101* %A
+   %A = getelementptr [6 x i101], [6 x i101]* @Y, i32 0, i32 1
+   %B = load i101, i101* %A
    %D = and i101 %B, 1
    %DD = or i101 %D, 1
    %E = trunc i101 %DD to i32
-   %F = getelementptr [6 x i101]* @Y, i32 0, i32 %E
-   %G = load i101* %F
+   %F = getelementptr [6 x i101], [6 x i101]* @Y, i32 0, i32 %E
+   %G = load i101, i101* %F
  
    ret i101 %G
 }
diff --git a/test/Transforms/SCCP/apint-ipsccp3.ll b/test/Transforms/SCCP/apint-ipsccp3.ll
index 68987aee249a..c99ae5820b2d 100644
--- a/test/Transforms/SCCP/apint-ipsccp3.ll
+++ b/test/Transforms/SCCP/apint-ipsccp3.ll
@@ -5,13 +5,13 @@
 
 
 define void @foo() {
-	%X = load i66* @G
+	%X = load i66, i66* @G
 	store i66 %X, i66* @G
 	ret void
 }
 
 define i66 @bar() {
-	%V = load i66* @G
+	%V = load i66, i66* @G
 	%C = icmp eq i66 %V, 17
 	br i1 %C, label %T, label %F
 T:
diff --git a/test/Transforms/SCCP/apint-ipsccp4.ll b/test/Transforms/SCCP/apint-ipsccp4.ll
index 75875ff642d2..be06d03f3914 100644
--- a/test/Transforms/SCCP/apint-ipsccp4.ll
+++ b/test/Transforms/SCCP/apint-ipsccp4.ll
@@ -9,14 +9,14 @@
                                      { i212, float } { i212 37, float 2.0 } ]
 
 define internal float @test2() {
-	%A = getelementptr [2 x { i212, float}]* @Y, i32 0, i32 1, i32 1
-	%B = load float* %A
+	%A = getelementptr [2 x { i212, float}], [2 x { i212, float}]* @Y, i32 0, i32 1, i32 1
+	%B = load float, float* %A
 	ret float %B
 }
 
 define internal float  @test3() {
-	%A = getelementptr [2 x { i212, float}]* @Y, i32 0, i32 0, i32 1
-	%B = load float* %A
+	%A = getelementptr [2 x { i212, float}], [2 x { i212, float}]* @Y, i32 0, i32 0, i32 1
+	%B = load float, float* %A
 	ret float %B
 }
 
diff --git a/test/Transforms/SCCP/apint-load.ll b/test/Transforms/SCCP/apint-load.ll
index 56fdb3513f15..17506fc043cc 100644
--- a/test/Transforms/SCCP/apint-load.ll
+++ b/test/Transforms/SCCP/apint-load.ll
@@ -7,19 +7,19 @@
 @Y = constant [2 x { i212, float }] [ { i212, float } { i212 12, float 1.0 }, 
                                      { i212, float } { i212 37, float 0x3FF3B2FEC0000000 } ]
 define i212 @test1() {
-	%B = load i212* @X
+	%B = load i212, i212* @X
 	ret i212 %B
 }
 
 define internal float @test2() {
-	%A = getelementptr [2 x { i212, float}]* @Y, i32 0, i32 1, i32 1
-	%B = load float* %A
+	%A = getelementptr [2 x { i212, float}], [2 x { i212, float}]* @Y, i32 0, i32 1, i32 1
+	%B = load float, float* %A
 	ret float %B
 }
 
 define internal i212 @test3() {
-	%A = getelementptr [2 x { i212, float}]* @Y, i32 0, i32 0, i32 0
-	%B = load i212* %A
+	%A = getelementptr [2 x { i212, float}], [2 x { i212, float}]* @Y, i32 0, i32 0, i32 0
+	%B = load i212, i212* %A
 	ret i212 %B
 }
 
diff --git a/test/Transforms/SCCP/apint-select.ll b/test/Transforms/SCCP/apint-select.ll
index c79751910fcb..893331ea9867 100644
--- a/test/Transforms/SCCP/apint-select.ll
+++ b/test/Transforms/SCCP/apint-select.ll
@@ -3,7 +3,7 @@
 @A = constant i32 10
 
 define i712 @test1() {
-        %P = getelementptr i32* @A, i32 0
+        %P = getelementptr i32, i32* @A, i32 0
         %B = ptrtoint i32* %P to i64
         %BB = and i64 %B, undef
         %C = icmp sge i64 %BB, 0
diff --git a/test/Transforms/SCCP/atomic-load-store.ll b/test/Transforms/SCCP/atomic-load-store.ll
index 53e4c10a720a..45b5d7c80feb 100644
--- a/test/Transforms/SCCP/atomic-load-store.ll
+++ b/test/Transforms/SCCP/atomic-load-store.ll
@@ -6,7 +6,7 @@
 @C = internal constant i32 222
 
 define i32 @test1() {
-	%V = load atomic i32* @G seq_cst, align 4
+	%V = load atomic i32, i32* @G seq_cst, align 4
 	%C = icmp eq i32 %V, 17
 	br i1 %C, label %T, label %F
 T:
@@ -21,7 +21,7 @@ F:
 ; CHECK: ret i32 17
 
 define i32 @test2() {
-	%V = load atomic i32* @C seq_cst, align 4
+	%V = load atomic i32, i32* @C seq_cst, align 4
 	ret i32 %V
 }
 
diff --git a/test/Transforms/SCCP/ipsccp-basic.ll b/test/Transforms/SCCP/ipsccp-basic.ll
index 107b7af2c1dc..c74063f33009 100644
--- a/test/Transforms/SCCP/ipsccp-basic.ll
+++ b/test/Transforms/SCCP/ipsccp-basic.ll
@@ -50,7 +50,7 @@ define i32 @test2b() {
 @G = internal global i32 undef
 
 define void @test3a() {
-	%X = load i32* @G
+	%X = load i32, i32* @G
 	store i32 %X, i32* @G
 	ret void
 }
@@ -59,7 +59,7 @@ define void @test3a() {
 
 
 define i32 @test3b() {
-	%V = load i32* @G
+	%V = load i32, i32* @G
 	%C = icmp eq i32 %V, 17
 	br i1 %C, label %T, label %F
 T:
@@ -203,7 +203,7 @@ define void @test8b(i32* %P) {
 define void @test9() {
 entry:
         %local_foo = alloca {  }
-        load {  }* @test9g
+        load {  }, {  }* @test9g
         store {  } %0, {  }* %local_foo
         ret void
 }
diff --git a/test/Transforms/SCCP/loadtest.ll b/test/Transforms/SCCP/loadtest.ll
index dd1dba69143c..b88b44b76040 100644
--- a/test/Transforms/SCCP/loadtest.ll
+++ b/test/Transforms/SCCP/loadtest.ll
@@ -10,25 +10,25 @@
 @Y = constant [2 x { i32, float }] [ { i32, float } { i32 12, float 1.000000e+00 }, { i32, float } { i32 37, float 0x3FF3B2FEC0000000 } ]		; <[2 x { i32, float }]*> [#uses=2]
 
 define i32 @test1() {
-	%B = load i32* @X		; <i32> [#uses=1]
+	%B = load i32, i32* @X		; <i32> [#uses=1]
 	ret i32 %B
 }
 
 define float @test2() {
-	%A = getelementptr [2 x { i32, float }]* @Y, i64 0, i64 1, i32 1		; <float*> [#uses=1]
-	%B = load float* %A		; <float> [#uses=1]
+	%A = getelementptr [2 x { i32, float }], [2 x { i32, float }]* @Y, i64 0, i64 1, i32 1		; <float*> [#uses=1]
+	%B = load float, float* %A		; <float> [#uses=1]
 	ret float %B
 }
 
 define i32 @test3() {
-	%A = getelementptr [2 x { i32, float }]* @Y, i64 0, i64 0, i32 0		; <i32*> [#uses=1]
-	%B = load i32* %A
+	%A = getelementptr [2 x { i32, float }], [2 x { i32, float }]* @Y, i64 0, i64 0, i32 0		; <i32*> [#uses=1]
+	%B = load i32, i32* %A
 	ret i32 %B
 }
 
 define i8 @test4() {
 	%A = bitcast i32* @X to i8*
-	%B = load i8* %A
+	%B = load i8, i8* %A
 	ret i8 %B
 }
 
diff --git a/test/Transforms/SCCP/retvalue-undef.ll b/test/Transforms/SCCP/retvalue-undef.ll
index 5a4ba113b7c0..f0e9e676cc04 100644
--- a/test/Transforms/SCCP/retvalue-undef.ll
+++ b/test/Transforms/SCCP/retvalue-undef.ll
@@ -15,7 +15,7 @@ define internal i32 @g() {
 ; CHECK-NEXT: ret i32 8
 
 define internal void @outer_mod() {
-  %1 = call i32 ()* ()* @f()                      ; <i32 ()*> [#uses=1]
+  %1 = call i32 ()* () @f()                      ; <i32 ()*> [#uses=1]
   %2 = call i32 %1()                              ; <i32> [#uses=0]
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/AArch64/commute.ll b/test/Transforms/SLPVectorizer/AArch64/commute.ll
index 4ee91a5ed4c0..1cff73d9f695 100644
--- a/test/Transforms/SLPVectorizer/AArch64/commute.ll
+++ b/test/Transforms/SLPVectorizer/AArch64/commute.ll
@@ -6,10 +6,10 @@ target triple = "aarch64--linux-gnu"
 
 define void @test1(%structA* nocapture readonly %J, i32 %xmin, i32 %ymin) {
 ; CHECK-LABEL: test1
-; CHECK: %arrayidx4 = getelementptr inbounds %structA* %J, i64 0, i32 0, i64 0
-; CHECK: %arrayidx9 = getelementptr inbounds %structA* %J, i64 0, i32 0, i64 1
+; CHECK: %arrayidx4 = getelementptr inbounds %structA, %structA* %J, i64 0, i32 0, i64 0
+; CHECK: %arrayidx9 = getelementptr inbounds %structA, %structA* %J, i64 0, i32 0, i64 1
 ; CHECK: %3 = bitcast float* %arrayidx4 to <2 x float>*
-; CHECK: %4 = load <2 x float>* %3, align 4
+; CHECK: %4 = load <2 x float>, <2 x float>* %3, align 4
 ; CHECK: %5 = fsub fast <2 x float> %2, %4
 ; CHECK: %6 = fmul fast <2 x float> %5, %5
 ; CHECK: %7 = extractelement <2 x float> %6, i32 0
@@ -23,11 +23,11 @@ entry:
 for.body3.lr.ph:
   %conv5 = sitofp i32 %ymin to float
   %conv = sitofp i32 %xmin to float
-  %arrayidx4 = getelementptr inbounds %structA* %J, i64 0, i32 0, i64 0
-  %0 = load float* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds %structA, %structA* %J, i64 0, i32 0, i64 0
+  %0 = load float, float* %arrayidx4, align 4
   %sub = fsub fast float %conv, %0
-  %arrayidx9 = getelementptr inbounds %structA* %J, i64 0, i32 0, i64 1
-  %1 = load float* %arrayidx9, align 4
+  %arrayidx9 = getelementptr inbounds %structA, %structA* %J, i64 0, i32 0, i64 1
+  %1 = load float, float* %arrayidx9, align 4
   %sub10 = fsub fast float %conv5, %1
   %mul11 = fmul fast float %sub, %sub
   %mul12 = fmul fast float %sub10, %sub10
@@ -41,10 +41,10 @@ for.end27:
 
 define void @test2(%structA* nocapture readonly %J, i32 %xmin, i32 %ymin) {
 ; CHECK-LABEL: test2
-; CHECK: %arrayidx4 = getelementptr inbounds %structA* %J, i64 0, i32 0, i64 0
-; CHECK: %arrayidx9 = getelementptr inbounds %structA* %J, i64 0, i32 0, i64 1
+; CHECK: %arrayidx4 = getelementptr inbounds %structA, %structA* %J, i64 0, i32 0, i64 0
+; CHECK: %arrayidx9 = getelementptr inbounds %structA, %structA* %J, i64 0, i32 0, i64 1
 ; CHECK: %3 = bitcast float* %arrayidx4 to <2 x float>*
-; CHECK: %4 = load <2 x float>* %3, align 4
+; CHECK: %4 = load <2 x float>, <2 x float>* %3, align 4
 ; CHECK: %5 = fsub fast <2 x float> %2, %4
 ; CHECK: %6 = fmul fast <2 x float> %5, %5
 ; CHECK: %7 = extractelement <2 x float> %6, i32 0
@@ -58,11 +58,11 @@ entry:
 for.body3.lr.ph:
   %conv5 = sitofp i32 %ymin to float
   %conv = sitofp i32 %xmin to float
-  %arrayidx4 = getelementptr inbounds %structA* %J, i64 0, i32 0, i64 0
-  %0 = load float* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds %structA, %structA* %J, i64 0, i32 0, i64 0
+  %0 = load float, float* %arrayidx4, align 4
   %sub = fsub fast float %conv, %0
-  %arrayidx9 = getelementptr inbounds %structA* %J, i64 0, i32 0, i64 1
-  %1 = load float* %arrayidx9, align 4
+  %arrayidx9 = getelementptr inbounds %structA, %structA* %J, i64 0, i32 0, i64 1
+  %1 = load float, float* %arrayidx9, align 4
   %sub10 = fsub fast float %conv5, %1
   %mul11 = fmul fast float %sub, %sub
   %mul12 = fmul fast float %sub10, %sub10
diff --git a/test/Transforms/SLPVectorizer/AArch64/load-store-q.ll b/test/Transforms/SLPVectorizer/AArch64/load-store-q.ll
index 45fa2f917f3a..6ff1118d3cc6 100644
--- a/test/Transforms/SLPVectorizer/AArch64/load-store-q.ll
+++ b/test/Transforms/SLPVectorizer/AArch64/load-store-q.ll
@@ -13,10 +13,10 @@ target triple = "arm64-apple-ios5.0.0"
 ; CHECK: store double
 ; CHECK: store double
 define void @f(double* %p, double* %q) {
-  %addr2 = getelementptr double* %q, i32 1
-  %addr = getelementptr double* %p, i32 1
-  %x = load double* %p
-  %y = load double* %addr
+  %addr2 = getelementptr double, double* %q, i32 1
+  %addr = getelementptr double, double* %p, i32 1
+  %x = load double, double* %p
+  %y = load double, double* %addr
   call void @g()
   store double %x, double* %q
   store double %y, double* %addr2
@@ -35,12 +35,12 @@ entry:
 loop:
   %p1 = phi double [0.0, %entry], [%x, %loop]
   %p2 = phi double [0.0, %entry], [%y, %loop]
-  %addr2 = getelementptr double* %q, i32 1
-  %addr = getelementptr double* %p, i32 1
+  %addr2 = getelementptr double, double* %q, i32 1
+  %addr = getelementptr double, double* %p, i32 1
   store double %p1, double* %q
   store double %p2, double* %addr2
 
-  %x = load double* %p
-  %y = load double* %addr
+  %x = load double, double* %p
+  %y = load double, double* %addr
   br label %loop
 }
diff --git a/test/Transforms/SLPVectorizer/AArch64/sdiv-pow2.ll b/test/Transforms/SLPVectorizer/AArch64/sdiv-pow2.ll
index e49c7adda400..72c70823e698 100644
--- a/test/Transforms/SLPVectorizer/AArch64/sdiv-pow2.ll
+++ b/test/Transforms/SLPVectorizer/AArch64/sdiv-pow2.ll
@@ -9,34 +9,34 @@ target triple = "aarch64--linux-gnu"
 
 define void @test1(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32* noalias nocapture readonly %c) {
 entry:
-  %0 = load i32* %b, align 4
-  %1 = load i32* %c, align 4
+  %0 = load i32, i32* %b, align 4
+  %1 = load i32, i32* %c, align 4
   %add = add nsw i32 %1, %0
   %div = sdiv i32 %add, 2
   store i32 %div, i32* %a, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i64 1
-  %2 = load i32* %arrayidx3, align 4
-  %arrayidx4 = getelementptr inbounds i32* %c, i64 1
-  %3 = load i32* %arrayidx4, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 1
+  %2 = load i32, i32* %arrayidx3, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %c, i64 1
+  %3 = load i32, i32* %arrayidx4, align 4
   %add5 = add nsw i32 %3, %2
   %div6 = sdiv i32 %add5, 2
-  %arrayidx7 = getelementptr inbounds i32* %a, i64 1
+  %arrayidx7 = getelementptr inbounds i32, i32* %a, i64 1
   store i32 %div6, i32* %arrayidx7, align 4
-  %arrayidx8 = getelementptr inbounds i32* %b, i64 2
-  %4 = load i32* %arrayidx8, align 4
-  %arrayidx9 = getelementptr inbounds i32* %c, i64 2
-  %5 = load i32* %arrayidx9, align 4
+  %arrayidx8 = getelementptr inbounds i32, i32* %b, i64 2
+  %4 = load i32, i32* %arrayidx8, align 4
+  %arrayidx9 = getelementptr inbounds i32, i32* %c, i64 2
+  %5 = load i32, i32* %arrayidx9, align 4
   %add10 = add nsw i32 %5, %4
   %div11 = sdiv i32 %add10, 2
-  %arrayidx12 = getelementptr inbounds i32* %a, i64 2
+  %arrayidx12 = getelementptr inbounds i32, i32* %a, i64 2
   store i32 %div11, i32* %arrayidx12, align 4
-  %arrayidx13 = getelementptr inbounds i32* %b, i64 3
-  %6 = load i32* %arrayidx13, align 4
-  %arrayidx14 = getelementptr inbounds i32* %c, i64 3
-  %7 = load i32* %arrayidx14, align 4
+  %arrayidx13 = getelementptr inbounds i32, i32* %b, i64 3
+  %6 = load i32, i32* %arrayidx13, align 4
+  %arrayidx14 = getelementptr inbounds i32, i32* %c, i64 3
+  %7 = load i32, i32* %arrayidx14, align 4
   %add15 = add nsw i32 %7, %6
   %div16 = sdiv i32 %add15, 2
-  %arrayidx17 = getelementptr inbounds i32* %a, i64 3
+  %arrayidx17 = getelementptr inbounds i32, i32* %a, i64 3
   store i32 %div16, i32* %arrayidx17, align 4
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/ARM/memory.ll b/test/Transforms/SLPVectorizer/ARM/memory.ll
index 383c808d21cf..57d7cceac6b9 100644
--- a/test/Transforms/SLPVectorizer/ARM/memory.ll
+++ b/test/Transforms/SLPVectorizer/ARM/memory.ll
@@ -10,11 +10,11 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-
 ; CHECK-NOT: store <2 x double>
 define void @expensive_double_store(double* noalias %dst, double* noalias %src, i64 %count) {
 entry:
-  %0 = load double* %src, align 8
+  %0 = load double, double* %src, align 8
   store double %0, double* %dst, align 8
-  %arrayidx2 = getelementptr inbounds double* %src, i64 1
-  %1 = load double* %arrayidx2, align 8
-  %arrayidx3 = getelementptr inbounds double* %dst, i64 1
+  %arrayidx2 = getelementptr inbounds double, double* %src, i64 1
+  %1 = load double, double* %arrayidx2, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %dst, i64 1
   store double %1, double* %arrayidx3, align 8
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/ARM/sroa.ll b/test/Transforms/SLPVectorizer/ARM/sroa.ll
index 899cfb1f82cf..65e02608b290 100644
--- a/test/Transforms/SLPVectorizer/ARM/sroa.ll
+++ b/test/Transforms/SLPVectorizer/ARM/sroa.ll
@@ -44,9 +44,9 @@ entry:
   %3 = bitcast i64 %b.sroa.3.12.insert.insert to double
   %add = fadd double %0, %2
   %add3 = fadd double %1, %3
-  %re.i.i = getelementptr inbounds %class.Complex* %agg.result, i32 0, i32 0
+  %re.i.i = getelementptr inbounds %class.Complex, %class.Complex* %agg.result, i32 0, i32 0
   store double %add, double* %re.i.i, align 4
-  %im.i.i = getelementptr inbounds %class.Complex* %agg.result, i32 0, i32 1
+  %im.i.i = getelementptr inbounds %class.Complex, %class.Complex* %agg.result, i32 0, i32 1
   store double %add3, double* %im.i.i, align 4
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/R600/simplebb.ll b/test/Transforms/SLPVectorizer/R600/simplebb.ll
index b6d794b994d4..9ed86f881473 100644
--- a/test/Transforms/SLPVectorizer/R600/simplebb.ll
+++ b/test/Transforms/SLPVectorizer/R600/simplebb.ll
@@ -6,60 +6,60 @@ target datalayout = "e-p:32:32:32-p3:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-
 ; Simple 3-pair chain with loads and stores
 define void @test1_as_3_3_3(double addrspace(3)* %a, double addrspace(3)* %b, double addrspace(3)* %c) {
 ; CHECK-LABEL: @test1_as_3_3_3(
-; CHECK: load <2 x double> addrspace(3)*
-; CHECK: load <2 x double> addrspace(3)*
+; CHECK: load <2 x double>, <2 x double> addrspace(3)*
+; CHECK: load <2 x double>, <2 x double> addrspace(3)*
 ; CHECK: store <2 x double> %{{.*}}, <2 x double> addrspace(3)* %
 ; CHECK: ret
-  %i0 = load double addrspace(3)* %a, align 8
-  %i1 = load double addrspace(3)* %b, align 8
+  %i0 = load double, double addrspace(3)* %a, align 8
+  %i1 = load double, double addrspace(3)* %b, align 8
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds double addrspace(3)* %a, i64 1
-  %i3 = load double addrspace(3)* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double addrspace(3)* %b, i64 1
-  %i4 = load double addrspace(3)* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double addrspace(3)* %a, i64 1
+  %i3 = load double, double addrspace(3)* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double addrspace(3)* %b, i64 1
+  %i4 = load double, double addrspace(3)* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   store double %mul, double addrspace(3)* %c, align 8
-  %arrayidx5 = getelementptr inbounds double addrspace(3)* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double addrspace(3)* %c, i64 1
   store double %mul5, double addrspace(3)* %arrayidx5, align 8
   ret void
 }
 
 define void @test1_as_3_0_0(double addrspace(3)* %a, double* %b, double* %c) {
 ; CHECK-LABEL: @test1_as_3_0_0(
-; CHECK: load <2 x double> addrspace(3)*
-; CHECK: load <2 x double>*
+; CHECK: load <2 x double>, <2 x double> addrspace(3)*
+; CHECK: load <2 x double>, <2 x double>*
 ; CHECK: store <2 x double> %{{.*}}, <2 x double>* %
 ; CHECK: ret
-  %i0 = load double addrspace(3)* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double addrspace(3)* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds double addrspace(3)* %a, i64 1
-  %i3 = load double addrspace(3)* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double addrspace(3)* %a, i64 1
+  %i3 = load double, double addrspace(3)* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   store double %mul, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   ret void
 }
 
 define void @test1_as_0_0_3(double* %a, double* %b, double addrspace(3)* %c) {
 ; CHECK-LABEL: @test1_as_0_0_3(
-; CHECK: load <2 x double>*
-; CHECK: load <2 x double>*
+; CHECK: load <2 x double>, <2 x double>*
+; CHECK: load <2 x double>, <2 x double>*
 ; CHECK: store <2 x double> %{{.*}}, <2 x double> addrspace(3)* %
 ; CHECK: ret
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   store double %mul, double addrspace(3)* %c, align 8
-  %arrayidx5 = getelementptr inbounds double addrspace(3)* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double addrspace(3)* %c, i64 1
   store double %mul5, double addrspace(3)* %arrayidx5, align 8
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/X86/addsub.ll b/test/Transforms/SLPVectorizer/X86/addsub.ll
index 174d40046849..7056a14c1c4f 100644
--- a/test/Transforms/SLPVectorizer/X86/addsub.ll
+++ b/test/Transforms/SLPVectorizer/X86/addsub.ll
@@ -10,6 +10,7 @@ target triple = "x86_64-unknown-linux-gnu"
 @fb = common global [4 x float] zeroinitializer, align 16
 @fc = common global [4 x float] zeroinitializer, align 16
 @fa = common global [4 x float] zeroinitializer, align 16
+@fd = common global [4 x float] zeroinitializer, align 16
 
 ; CHECK-LABEL: @addsub
 ; CHECK: %5 = add nsw <4 x i32> %3, %4
@@ -20,38 +21,38 @@ target triple = "x86_64-unknown-linux-gnu"
 ; Function Attrs: nounwind uwtable
 define void @addsub() #0 {
 entry:
-  %0 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 0), align 4
-  %1 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 0), align 4
+  %0 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @b, i32 0, i64 0), align 4
+  %1 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @c, i32 0, i64 0), align 4
   %add = add nsw i32 %0, %1
-  %2 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 0), align 4
-  %3 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 0), align 4
+  %2 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @d, i32 0, i64 0), align 4
+  %3 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i64 0), align 4
   %add1 = add nsw i32 %2, %3
   %add2 = add nsw i32 %add, %add1
-  store i32 %add2, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 0), align 4
-  %4 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 1), align 4
-  %5 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 1), align 4
+  store i32 %add2, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i32 0, i64 0), align 4
+  %4 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @b, i32 0, i64 1), align 4
+  %5 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @c, i32 0, i64 1), align 4
   %add3 = add nsw i32 %4, %5
-  %6 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 1), align 4
-  %7 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 1), align 4
+  %6 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @d, i32 0, i64 1), align 4
+  %7 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i64 1), align 4
   %add4 = add nsw i32 %6, %7
   %sub = sub nsw i32 %add3, %add4
-  store i32 %sub, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 1), align 4
-  %8 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 2), align 4
-  %9 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 2), align 4
+  store i32 %sub, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i32 0, i64 1), align 4
+  %8 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @b, i32 0, i64 2), align 4
+  %9 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @c, i32 0, i64 2), align 4
   %add5 = add nsw i32 %8, %9
-  %10 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 2), align 4
-  %11 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 2), align 4
+  %10 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @d, i32 0, i64 2), align 4
+  %11 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i64 2), align 4
   %add6 = add nsw i32 %10, %11
   %add7 = add nsw i32 %add5, %add6
-  store i32 %add7, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 2), align 4
-  %12 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 3), align 4
-  %13 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 3), align 4
+  store i32 %add7, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i32 0, i64 2), align 4
+  %12 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @b, i32 0, i64 3), align 4
+  %13 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @c, i32 0, i64 3), align 4
   %add8 = add nsw i32 %12, %13
-  %14 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 3), align 4
-  %15 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 3), align 4
+  %14 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @d, i32 0, i64 3), align 4
+  %15 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i64 3), align 4
   %add9 = add nsw i32 %14, %15
   %sub10 = sub nsw i32 %add8, %add9
-  store i32 %sub10, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 3), align 4
+  store i32 %sub10, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i32 0, i64 3), align 4
   ret void
 }
 
@@ -64,38 +65,38 @@ entry:
 ; Function Attrs: nounwind uwtable
 define void @subadd() #0 {
 entry:
-  %0 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 0), align 4
-  %1 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 0), align 4
+  %0 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @b, i32 0, i64 0), align 4
+  %1 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @c, i32 0, i64 0), align 4
   %add = add nsw i32 %0, %1
-  %2 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 0), align 4
-  %3 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 0), align 4
+  %2 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @d, i32 0, i64 0), align 4
+  %3 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i64 0), align 4
   %add1 = add nsw i32 %2, %3
   %sub = sub nsw i32 %add, %add1
-  store i32 %sub, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 0), align 4
-  %4 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 1), align 4
-  %5 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 1), align 4
+  store i32 %sub, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i32 0, i64 0), align 4
+  %4 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @b, i32 0, i64 1), align 4
+  %5 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @c, i32 0, i64 1), align 4
   %add2 = add nsw i32 %4, %5
-  %6 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 1), align 4
-  %7 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 1), align 4
+  %6 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @d, i32 0, i64 1), align 4
+  %7 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i64 1), align 4
   %add3 = add nsw i32 %6, %7
   %add4 = add nsw i32 %add2, %add3
-  store i32 %add4, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 1), align 4
-  %8 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 2), align 4
-  %9 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 2), align 4
+  store i32 %add4, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i32 0, i64 1), align 4
+  %8 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @b, i32 0, i64 2), align 4
+  %9 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @c, i32 0, i64 2), align 4
   %add5 = add nsw i32 %8, %9
-  %10 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 2), align 4
-  %11 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 2), align 4
+  %10 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @d, i32 0, i64 2), align 4
+  %11 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i64 2), align 4
   %add6 = add nsw i32 %10, %11
   %sub7 = sub nsw i32 %add5, %add6
-  store i32 %sub7, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 2), align 4
-  %12 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 3), align 4
-  %13 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 3), align 4
+  store i32 %sub7, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i32 0, i64 2), align 4
+  %12 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @b, i32 0, i64 3), align 4
+  %13 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @c, i32 0, i64 3), align 4
   %add8 = add nsw i32 %12, %13
-  %14 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 3), align 4
-  %15 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 3), align 4
+  %14 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @d, i32 0, i64 3), align 4
+  %15 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i64 3), align 4
   %add9 = add nsw i32 %14, %15
   %add10 = add nsw i32 %add8, %add9
-  store i32 %add10, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 3), align 4
+  store i32 %add10, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i32 0, i64 3), align 4
   ret void
 }
 
@@ -106,22 +107,22 @@ entry:
 ; Function Attrs: nounwind uwtable
 define void @faddfsub() #0 {
 entry:
-  %0 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 0), align 4
-  %1 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 0), align 4
+  %0 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 0), align 4
+  %1 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 0), align 4
   %add = fadd float %0, %1
-  store float %add, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 0), align 4
-  %2 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 1), align 4
-  %3 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 1), align 4
+  store float %add, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 0), align 4
+  %2 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 1), align 4
+  %3 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 1), align 4
   %sub = fsub float %2, %3
-  store float %sub, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 1), align 4
-  %4 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 2), align 4
-  %5 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 2), align 4
+  store float %sub, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 1), align 4
+  %4 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 2), align 4
+  %5 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 2), align 4
   %add1 = fadd float %4, %5
-  store float %add1, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 2), align 4
-  %6 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 3), align 4
-  %7 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 3), align 4
+  store float %add1, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 2), align 4
+  %6 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 3), align 4
+  %7 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 3), align 4
   %sub2 = fsub float %6, %7
-  store float %sub2, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 3), align 4
+  store float %sub2, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 3), align 4
   ret void
 }
 
@@ -132,22 +133,22 @@ entry:
 ; Function Attrs: nounwind uwtable
 define void @fsubfadd() #0 {
 entry:
-  %0 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 0), align 4
-  %1 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 0), align 4
+  %0 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 0), align 4
+  %1 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 0), align 4
   %sub = fsub float %0, %1
-  store float %sub, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 0), align 4
-  %2 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 1), align 4
-  %3 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 1), align 4
+  store float %sub, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 0), align 4
+  %2 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 1), align 4
+  %3 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 1), align 4
   %add = fadd float %2, %3
-  store float %add, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 1), align 4
-  %4 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 2), align 4
-  %5 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 2), align 4
+  store float %add, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 1), align 4
+  %4 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 2), align 4
+  %5 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 2), align 4
   %sub1 = fsub float %4, %5
-  store float %sub1, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 2), align 4
-  %6 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 3), align 4
-  %7 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 3), align 4
+  store float %sub1, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 2), align 4
+  %6 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 3), align 4
+  %7 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 3), align 4
   %add2 = fadd float %6, %7
-  store float %add2, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 3), align 4
+  store float %add2, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 3), align 4
   ret void
 }
 
@@ -158,24 +159,156 @@ entry:
 ; Function Attrs: nounwind uwtable
 define void @No_faddfsub() #0 {
 entry:
-  %0 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 0), align 4
-  %1 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 0), align 4
+  %0 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 0), align 4
+  %1 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 0), align 4
   %add = fadd float %0, %1
-  store float %add, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 0), align 4
-  %2 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 1), align 4
-  %3 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 1), align 4
+  store float %add, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 0), align 4
+  %2 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 1), align 4
+  %3 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 1), align 4
   %add1 = fadd float %2, %3
-  store float %add1, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 1), align 4
-  %4 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 2), align 4
-  %5 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 2), align 4
+  store float %add1, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 1), align 4
+  %4 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 2), align 4
+  %5 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 2), align 4
   %add2 = fadd float %4, %5
-  store float %add2, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 2), align 4
-  %6 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 3), align 4
-  %7 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 3), align 4
+  store float %add2, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 2), align 4
+  %6 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 3), align 4
+  %7 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 3), align 4
   %sub = fsub float %6, %7
-  store float %sub, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 3), align 4
+  store float %sub, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 3), align 4
   ret void
 }
 
+; Check vectorization of following code for float data type-
+;  fc[0] = fb[0]+fa[0]; //swapped fb and fa
+;  fc[1] = fa[1]-fb[1];
+;  fc[2] = fa[2]+fb[2];
+;  fc[3] = fa[3]-fb[3];
+
+; CHECK-LABEL: @reorder_alt
+; CHECK: %3 = fadd <4 x float> %1, %2
+; CHECK: %4 = fsub <4 x float> %1, %2
+; CHECK: %5 = shufflevector <4 x float> %3, <4 x float> %4, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+define void @reorder_alt() #0 {
+  %1 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 0), align 4
+  %2 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 0), align 4
+  %3 = fadd float %1, %2
+  store float %3, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 0), align 4
+  %4 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 1), align 4
+  %5 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 1), align 4
+  %6 = fsub float %4, %5
+  store float %6, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 1), align 4
+  %7 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 2), align 4
+  %8 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 2), align 4
+  %9 = fadd float %7, %8
+  store float %9, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 2), align 4
+  %10 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 3), align 4
+  %11 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 3), align 4
+  %12 = fsub float %10, %11
+  store float %12, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 3), align 4
+  ret void
+}
+
+; Check vectorization of following code for float data type-
+;  fc[0] = fa[0]+(fb[0]-fd[0]);
+;  fc[1] = fa[1]-(fb[1]+fd[1]);
+;  fc[2] = fa[2]+(fb[2]-fd[2]);
+;  fc[3] = fa[3]-(fd[3]+fb[3]); //swapped fd and fb 
+
+; CHECK-LABEL: @reorder_alt_subTree
+; CHECK: %4 = fsub <4 x float> %3, %2
+; CHECK: %5 = fadd <4 x float> %3, %2
+; CHECK: %6 = shufflevector <4 x float> %4, <4 x float> %5, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; CHECK: %7 = fadd <4 x float> %1, %6
+; CHECK: %8 = fsub <4 x float> %1, %6
+; CHECK: %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+define void @reorder_alt_subTree() #0 {
+  %1 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 0), align 4
+  %2 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 0), align 4
+  %3 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fd, i32 0, i64 0), align 4
+  %4 = fsub float %2, %3
+  %5 = fadd float %1, %4
+  store float %5, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 0), align 4
+  %6 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 1), align 4
+  %7 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 1), align 4
+  %8 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fd, i32 0, i64 1), align 4
+  %9 = fadd float %7, %8
+  %10 = fsub float %6, %9
+  store float %10, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 1), align 4
+  %11 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 2), align 4
+  %12 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 2), align 4
+  %13 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fd, i32 0, i64 2), align 4
+  %14 = fsub float %12, %13
+  %15 = fadd float %11, %14
+  store float %15, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 2), align 4
+  %16 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 3), align 4
+  %17 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fd, i32 0, i64 3), align 4
+  %18 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 3), align 4
+  %19 = fadd float %17, %18
+  %20 = fsub float %16, %19
+  store float %20, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 3), align 4
+  ret void
+}
+
+; Check vectorization of following code for double data type-
+;  c[0] = (a[0]+b[0])-d[0];
+;  c[1] = d[1]+(a[1]+b[1]); //swapped d[1] and (a[1]+b[1]) 
+
+; CHECK-LABEL: @reorder_alt_rightsubTree
+; CHECK: fadd <2 x double>
+; CHECK: fsub <2 x double>
+; CHECK: shufflevector <2 x double> 
+define void @reorder_alt_rightsubTree(double* nocapture %c, double* noalias nocapture readonly %a, double* noalias nocapture readonly %b, double* noalias nocapture readonly %d) {
+  %1 = load double, double* %a
+  %2 = load double, double* %b
+  %3 = fadd double %1, %2
+  %4 = load double, double* %d
+  %5 = fsub double %3, %4
+  store double %5, double* %c
+  %6 = getelementptr inbounds double, double* %d, i64 1
+  %7 = load double, double* %6
+  %8 = getelementptr inbounds double, double* %a, i64 1
+  %9 = load double, double* %8
+  %10 = getelementptr inbounds double, double* %b, i64 1
+  %11 = load double, double* %10
+  %12 = fadd double %9, %11
+  %13 = fadd double %7, %12
+  %14 = getelementptr inbounds double, double* %c, i64 1
+  store double %13, double* %14
+  ret void
+}
+
+; Dont vectorization of following code for float data type as sub is not commutative-
+;  fc[0] = fb[0]+fa[0];
+;  fc[1] = fa[1]-fb[1];
+;  fc[2] = fa[2]+fb[2];
+;  fc[3] = fb[3]-fa[3];
+;  In the above code we can swap the 1st and 2nd operation as fadd is commutative
+;  but not 2nd or 4th as fsub is not commutative. 
+
+; CHECK-LABEL: @no_vec_shuff_reorder
+; CHECK-NOT: fadd <4 x float>
+; CHECK-NOT: fsub <4 x float>
+; CHECK-NOT: shufflevector
+define void @no_vec_shuff_reorder() #0 {
+  %1 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 0), align 4
+  %2 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 0), align 4
+  %3 = fadd float %1, %2
+  store float %3, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 0), align 4
+  %4 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 1), align 4
+  %5 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 1), align 4
+  %6 = fsub float %4, %5
+  store float %6, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 1), align 4
+  %7 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 2), align 4
+  %8 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 2), align 4
+  %9 = fadd float %7, %8
+  store float %9, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 2), align 4
+  %10 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fb, i32 0, i64 3), align 4
+  %11 = load float, float* getelementptr inbounds ([4 x float], [4 x float]* @fa, i32 0, i64 3), align 4
+  %12 = fsub float %10, %11
+  store float %12, float* getelementptr inbounds ([4 x float], [4 x float]* @fc, i32 0, i64 3), align 4
+  ret void
+}
+
+
 attributes #0 = { nounwind }
 
diff --git a/test/Transforms/SLPVectorizer/X86/align.ll b/test/Transforms/SLPVectorizer/X86/align.ll
index ce8062025064..b74b70900ee9 100644
--- a/test/Transforms/SLPVectorizer/X86/align.ll
+++ b/test/Transforms/SLPVectorizer/X86/align.ll
@@ -8,16 +8,16 @@ target triple = "x86_64-apple-macosx10.8.0"
 define void @test1(double* %a, double* %b, double* %c) {
 entry:
   %agg.tmp.i.i.sroa.0 = alloca [3 x double], align 16
-; CHECK: %[[V0:[0-9]+]] = load <2 x double>* %[[V2:[0-9]+]], align 8
-  %i0 = load double* %a 
-  %i1 = load double* %b 
+; CHECK: %[[V0:[0-9]+]] = load <2 x double>, <2 x double>* %[[V2:[0-9]+]], align 8
+  %i0 = load double, double* %a 
+  %i1 = load double, double* %b 
   %mul = fmul double %i0, %i1
-  %store1 = getelementptr inbounds [3 x double]* %agg.tmp.i.i.sroa.0, i64 0, i64 1
-  %store2 = getelementptr inbounds [3 x double]* %agg.tmp.i.i.sroa.0, i64 0, i64 2
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %store1 = getelementptr inbounds [3 x double], [3 x double]* %agg.tmp.i.i.sroa.0, i64 0, i64 1
+  %store2 = getelementptr inbounds [3 x double], [3 x double]* %agg.tmp.i.i.sroa.0, i64 0, i64 2
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
 ; CHECK: store <2 x double> %[[V1:[0-9]+]], <2 x double>* %[[V2:[0-9]+]], align 8
   store double %mul, double* %store1
@@ -37,19 +37,19 @@ entry:
 
 define void @test2(float * %a, float * %b) {
 entry:
-  %l0 = load float* %a
-  %a1 = getelementptr inbounds float* %a, i64 1
-  %l1 = load float* %a1
-  %a2 = getelementptr inbounds float* %a, i64 2
-  %l2 = load float* %a2
-  %a3 = getelementptr inbounds float* %a, i64 3
-  %l3 = load float* %a3
+  %l0 = load float, float* %a
+  %a1 = getelementptr inbounds float, float* %a, i64 1
+  %l1 = load float, float* %a1
+  %a2 = getelementptr inbounds float, float* %a, i64 2
+  %l2 = load float, float* %a2
+  %a3 = getelementptr inbounds float, float* %a, i64 3
+  %l3 = load float, float* %a3
   store float %l0, float* %b
-  %b1 = getelementptr inbounds float* %b, i64 1
+  %b1 = getelementptr inbounds float, float* %b, i64 1
   store float %l1, float* %b1
-  %b2 = getelementptr inbounds float* %b, i64 2
+  %b2 = getelementptr inbounds float, float* %b, i64 2
   store float %l2, float* %b2
-  %b3 = getelementptr inbounds float* %b, i64 3
+  %b3 = getelementptr inbounds float, float* %b, i64 3
   store float %l3, float* %b3
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/X86/atomics.ll b/test/Transforms/SLPVectorizer/X86/atomics.ll
new file mode 100644
index 000000000000..a48b793922f4
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/atomics.ll
@@ -0,0 +1,31 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -S |FileCheck %s
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+
+@x = global [4 x i32] zeroinitializer, align 16
+@a = global [4 x i32] zeroinitializer, align 16
+
+; The SLPVectorizer should not vectorize atomic stores and it should not
+; schedule regular stores around atomic stores.
+
+; CHECK-LABEL: test
+; CHECK: store i32
+; CHECK: store atomic i32
+; CHECK: store i32
+; CHECK: store atomic i32
+; CHECK: store i32
+; CHECK: store atomic i32
+; CHECK: store i32
+; CHECK: store atomic i32
+define void @test() {
+entry:
+  store i32 0, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i64 0, i64 0), align 16
+  store atomic i32 0, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @x, i64 0, i64 0) release, align 16
+  store i32 0, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i64 0, i64 1), align 4
+  store atomic i32 1, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @x, i64 0, i64 1) release, align 4
+  store i32 0, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i64 0, i64 2), align 8
+  store atomic i32 2, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @x, i64 0, i64 2) release, align 8
+  store i32 0, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i64 0, i64 3), align 4
+  store atomic i32 3, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @x, i64 0, i64 3) release, align 4
+  ret void
+}
+
diff --git a/test/Transforms/SLPVectorizer/X86/bad_types.ll b/test/Transforms/SLPVectorizer/X86/bad_types.ll
index 38ed18dad2ac..2d8f3832ee29 100644
--- a/test/Transforms/SLPVectorizer/X86/bad_types.ll
+++ b/test/Transforms/SLPVectorizer/X86/bad_types.ll
@@ -16,7 +16,7 @@ entry:
   %b.cast = bitcast x86_mmx %b to i64
   %a.and = and i64 %a.cast, 42
   %b.and = and i64 %b.cast, 42
-  %gep = getelementptr i64* %ptr, i32 1
+  %gep = getelementptr i64, i64* %ptr, i32 1
   store i64 %a.and, i64* %ptr
   store i64 %b.and, i64* %gep
   ret void
diff --git a/test/Transforms/SLPVectorizer/X86/barriercall.ll b/test/Transforms/SLPVectorizer/X86/barriercall.ll
index bba285526a4b..382a43fddf58 100644
--- a/test/Transforms/SLPVectorizer/X86/barriercall.ll
+++ b/test/Transforms/SLPVectorizer/X86/barriercall.ll
@@ -8,21 +8,21 @@ target triple = "x86_64-apple-macosx10.8.0"
 ;CHECK: ret
 define i32 @foo(i32* nocapture %A, i32 %n) {
 entry:
-  %call = tail call i32 (...)* @bar() #2
+  %call = tail call i32 (...) @bar() #2
   %mul = mul nsw i32 %n, 5
   %add = add nsw i32 %mul, 9
   store i32 %add, i32* %A, align 4
   %mul1 = mul nsw i32 %n, 9
   %add2 = add nsw i32 %mul1, 9
-  %arrayidx3 = getelementptr inbounds i32* %A, i64 1
+  %arrayidx3 = getelementptr inbounds i32, i32* %A, i64 1
   store i32 %add2, i32* %arrayidx3, align 4
   %mul4 = shl i32 %n, 3
   %add5 = add nsw i32 %mul4, 9
-  %arrayidx6 = getelementptr inbounds i32* %A, i64 2
+  %arrayidx6 = getelementptr inbounds i32, i32* %A, i64 2
   store i32 %add5, i32* %arrayidx6, align 4
   %mul7 = mul nsw i32 %n, 10
   %add8 = add nsw i32 %mul7, 9
-  %arrayidx9 = getelementptr inbounds i32* %A, i64 3
+  %arrayidx9 = getelementptr inbounds i32, i32* %A, i64 3
   store i32 %add8, i32* %arrayidx9, align 4
   ret i32 undef
 }
diff --git a/test/Transforms/SLPVectorizer/X86/call.ll b/test/Transforms/SLPVectorizer/X86/call.ll
index 83d45c0a9d72..a55cc1bf793f 100644
--- a/test/Transforms/SLPVectorizer/X86/call.ll
+++ b/test/Transforms/SLPVectorizer/X86/call.ll
@@ -15,18 +15,18 @@ declare i64 @round(i64)
 ; CHECK: ret void
 define void @sin_libm(double* %a, double* %b, double* %c) {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
   %call = tail call double @sin(double %mul) nounwind readnone
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   %call5 = tail call double @sin(double %mul5) nounwind readnone
   store double %call, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %call5, double* %arrayidx5, align 8
   ret void
 }
@@ -36,18 +36,18 @@ entry:
 ; CHECK: ret void
 define void @cos_libm(double* %a, double* %b, double* %c) {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
   %call = tail call double @cos(double %mul) nounwind readnone
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   %call5 = tail call double @cos(double %mul5) nounwind readnone
   store double %call, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %call5, double* %arrayidx5, align 8
   ret void
 }
@@ -57,18 +57,18 @@ entry:
 ; CHECK: ret void
 define void @pow_libm(double* %a, double* %b, double* %c) {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
   %call = tail call double @pow(double %mul,double %mul) nounwind readnone
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   %call5 = tail call double @pow(double %mul5,double %mul5) nounwind readnone
   store double %call, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %call5, double* %arrayidx5, align 8
   ret void
 }
@@ -79,18 +79,18 @@ entry:
 ; CHECK: ret void
 define void @exp2_libm(double* %a, double* %b, double* %c) {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
   %call = tail call double @exp2(double %mul) nounwind readnone
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   %call5 = tail call double @exp2(double %mul5) nounwind readnone
   store double %call, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %call5, double* %arrayidx5, align 8
   ret void
 }
@@ -102,27 +102,27 @@ entry:
 ; CHECK: ret void
 define void @round_custom(i64* %a, i64* %b, i64* %c) {
 entry:
-  %i0 = load i64* %a, align 8
-  %i1 = load i64* %b, align 8
+  %i0 = load i64, i64* %a, align 8
+  %i1 = load i64, i64* %b, align 8
   %mul = mul i64 %i0, %i1
   %call = tail call i64 @round(i64 %mul) nounwind readnone
-  %arrayidx3 = getelementptr inbounds i64* %a, i64 1
-  %i3 = load i64* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds i64* %b, i64 1
-  %i4 = load i64* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds i64, i64* %a, i64 1
+  %i3 = load i64, i64* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds i64, i64* %b, i64 1
+  %i4 = load i64, i64* %arrayidx4, align 8
   %mul5 = mul i64 %i3, %i4
   %call5 = tail call i64 @round(i64 %mul5) nounwind readnone
   store i64 %call, i64* %c, align 8
-  %arrayidx5 = getelementptr inbounds i64* %c, i64 1
+  %arrayidx5 = getelementptr inbounds i64, i64* %c, i64 1
   store i64 %call5, i64* %arrayidx5, align 8
   ret void
 }
 
 
-; CHECK: declare <2 x double> @llvm.sin.v2f64(<2 x double>) #0
-; CHECK: declare <2 x double> @llvm.cos.v2f64(<2 x double>) #0
-; CHECK: declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) #0
-; CHECK: declare <2 x double> @llvm.exp2.v2f64(<2 x double>) #0
+; CHECK: declare <2 x double> @llvm.sin.v2f64(<2 x double>) [[ATTR0:#[0-9]+]]
+; CHECK: declare <2 x double> @llvm.cos.v2f64(<2 x double>) [[ATTR0]]
+; CHECK: declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) [[ATTR0]]
+; CHECK: declare <2 x double> @llvm.exp2.v2f64(<2 x double>) [[ATTR0]]
 
-; CHECK: attributes #0 = { nounwind readnone }
+; CHECK: attributes [[ATTR0]] = { nounwind readnone }
 
diff --git a/test/Transforms/SLPVectorizer/X86/cast.ll b/test/Transforms/SLPVectorizer/X86/cast.ll
index e340fba351a3..044db5d694b6 100644
--- a/test/Transforms/SLPVectorizer/X86/cast.ll
+++ b/test/Transforms/SLPVectorizer/X86/cast.ll
@@ -15,23 +15,23 @@ target triple = "x86_64-apple-macosx10.9.0"
 ;CHECK: store <4 x i32>
 define i32 @foo(i32* noalias nocapture %A, i8* noalias nocapture %B) {
 entry:
-  %0 = load i8* %B, align 1
+  %0 = load i8, i8* %B, align 1
   %conv = sext i8 %0 to i32
   store i32 %conv, i32* %A, align 4
-  %arrayidx2 = getelementptr inbounds i8* %B, i64 1
-  %1 = load i8* %arrayidx2, align 1
+  %arrayidx2 = getelementptr inbounds i8, i8* %B, i64 1
+  %1 = load i8, i8* %arrayidx2, align 1
   %conv3 = sext i8 %1 to i32
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 1
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 1
   store i32 %conv3, i32* %arrayidx4, align 4
-  %arrayidx5 = getelementptr inbounds i8* %B, i64 2
-  %2 = load i8* %arrayidx5, align 1
+  %arrayidx5 = getelementptr inbounds i8, i8* %B, i64 2
+  %2 = load i8, i8* %arrayidx5, align 1
   %conv6 = sext i8 %2 to i32
-  %arrayidx7 = getelementptr inbounds i32* %A, i64 2
+  %arrayidx7 = getelementptr inbounds i32, i32* %A, i64 2
   store i32 %conv6, i32* %arrayidx7, align 4
-  %arrayidx8 = getelementptr inbounds i8* %B, i64 3
-  %3 = load i8* %arrayidx8, align 1
+  %arrayidx8 = getelementptr inbounds i8, i8* %B, i64 3
+  %3 = load i8, i8* %arrayidx8, align 1
   %conv9 = sext i8 %3 to i32
-  %arrayidx10 = getelementptr inbounds i32* %A, i64 3
+  %arrayidx10 = getelementptr inbounds i32, i32* %A, i64 3
   store i32 %conv9, i32* %arrayidx10, align 4
   ret i32 undef
 }
diff --git a/test/Transforms/SLPVectorizer/X86/cmp_sel.ll b/test/Transforms/SLPVectorizer/X86/cmp_sel.ll
index 0c124a75d417..a3e2b21ea6e0 100644
--- a/test/Transforms/SLPVectorizer/X86/cmp_sel.ll
+++ b/test/Transforms/SLPVectorizer/X86/cmp_sel.ll
@@ -16,16 +16,16 @@ target triple = "x86_64-apple-macosx10.8.0"
 ;CHECK: ret i32 undef
 define i32 @foo(double* noalias nocapture %A, double* noalias nocapture %B, double %G) {
 entry:
-  %arrayidx = getelementptr inbounds double* %B, i64 10
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %B, i64 10
+  %0 = load double, double* %arrayidx, align 8
   %tobool = fcmp une double %0, 0.000000e+00
   %cond = select i1 %tobool, double %G, double 1.000000e+00
   store double %cond, double* %A, align 8
-  %arrayidx2 = getelementptr inbounds double* %B, i64 11
-  %1 = load double* %arrayidx2, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %B, i64 11
+  %1 = load double, double* %arrayidx2, align 8
   %tobool3 = fcmp une double %1, 0.000000e+00
   %cond7 = select i1 %tobool3, double %G, double 1.000000e+00
-  %arrayidx8 = getelementptr inbounds double* %A, i64 1
+  %arrayidx8 = getelementptr inbounds double, double* %A, i64 1
   store double %cond7, double* %arrayidx8, align 8
   ret i32 undef
 }
diff --git a/test/Transforms/SLPVectorizer/X86/compare-reduce.ll b/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
index 9653d18db566..be17c5db2e86 100644
--- a/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
+++ b/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
@@ -21,14 +21,14 @@ entry:
 for.body:                                         ; preds = %for.inc, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ]
   %0 = shl nsw i64 %indvars.iv, 1
-  %arrayidx = getelementptr inbounds double* %A, i64 %0
-  %1 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %A, i64 %0
+  %1 = load double, double* %arrayidx, align 8
   %mul1 = fmul double %conv, %1
   %mul2 = fmul double %mul1, 7.000000e+00
   %add = fadd double %mul2, 5.000000e+00
   %2 = or i64 %0, 1
-  %arrayidx6 = getelementptr inbounds double* %A, i64 %2
-  %3 = load double* %arrayidx6, align 8
+  %arrayidx6 = getelementptr inbounds double, double* %A, i64 %2
+  %3 = load double, double* %arrayidx6, align 8
   %mul8 = fmul double %conv, %3
   %mul9 = fmul double %mul8, 4.000000e+00
   %add10 = fadd double %mul9, 9.000000e+00
@@ -36,7 +36,7 @@ for.body:                                         ; preds = %for.inc, %entry
   br i1 %cmp11, label %if.then, label %for.inc
 
 if.then:                                          ; preds = %for.body
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([6 x i8]* @.str, i64 0, i64 0))
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0))
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body, %if.then
diff --git a/test/Transforms/SLPVectorizer/X86/consecutive-access.ll b/test/Transforms/SLPVectorizer/X86/consecutive-access.ll
index aa59429a77d1..1ad4d694d34a 100644
--- a/test/Transforms/SLPVectorizer/X86/consecutive-access.ll
+++ b/test/Transforms/SLPVectorizer/X86/consecutive-access.ll
@@ -20,26 +20,26 @@ entry:
   store i32 %u, i32* %u.addr, align 4
   %mul = mul nsw i32 %u, 3
   %idxprom = sext i32 %mul to i64
-  %arrayidx = getelementptr inbounds [2000 x double]* @A, i32 0, i64 %idxprom
-  %0 = load double* %arrayidx, align 8
-  %arrayidx4 = getelementptr inbounds [2000 x double]* @B, i32 0, i64 %idxprom
-  %1 = load double* %arrayidx4, align 8
+  %arrayidx = getelementptr inbounds [2000 x double], [2000 x double]* @A, i32 0, i64 %idxprom
+  %0 = load double, double* %arrayidx, align 8
+  %arrayidx4 = getelementptr inbounds [2000 x double], [2000 x double]* @B, i32 0, i64 %idxprom
+  %1 = load double, double* %arrayidx4, align 8
   %add5 = fadd double %0, %1
   store double %add5, double* %arrayidx, align 8
   %add11 = add nsw i32 %mul, 1
   %idxprom12 = sext i32 %add11 to i64
-  %arrayidx13 = getelementptr inbounds [2000 x double]* @A, i32 0, i64 %idxprom12
-  %2 = load double* %arrayidx13, align 8
-  %arrayidx17 = getelementptr inbounds [2000 x double]* @B, i32 0, i64 %idxprom12
-  %3 = load double* %arrayidx17, align 8
+  %arrayidx13 = getelementptr inbounds [2000 x double], [2000 x double]* @A, i32 0, i64 %idxprom12
+  %2 = load double, double* %arrayidx13, align 8
+  %arrayidx17 = getelementptr inbounds [2000 x double], [2000 x double]* @B, i32 0, i64 %idxprom12
+  %3 = load double, double* %arrayidx17, align 8
   %add18 = fadd double %2, %3
   store double %add18, double* %arrayidx13, align 8
   %add24 = add nsw i32 %mul, 2
   %idxprom25 = sext i32 %add24 to i64
-  %arrayidx26 = getelementptr inbounds [2000 x double]* @A, i32 0, i64 %idxprom25
-  %4 = load double* %arrayidx26, align 8
-  %arrayidx30 = getelementptr inbounds [2000 x double]* @B, i32 0, i64 %idxprom25
-  %5 = load double* %arrayidx30, align 8
+  %arrayidx26 = getelementptr inbounds [2000 x double], [2000 x double]* @A, i32 0, i64 %idxprom25
+  %4 = load double, double* %arrayidx26, align 8
+  %arrayidx30 = getelementptr inbounds [2000 x double], [2000 x double]* @B, i32 0, i64 %idxprom25
+  %5 = load double, double* %arrayidx30, align 8
   %add31 = fadd double %4, %5
   store double %add31, double* %arrayidx26, align 8
   ret void
@@ -57,18 +57,18 @@ entry:
   store i32 %u, i32* %u.addr, align 4
   %mul = mul nsw i32 %u, 2
   %idxprom = sext i32 %mul to i64
-  %arrayidx = getelementptr inbounds [2000 x double]* @A, i32 0, i64 %idxprom
-  %0 = load double* %arrayidx, align 8
-  %arrayidx4 = getelementptr inbounds [2000 x double]* @B, i32 0, i64 %idxprom
-  %1 = load double* %arrayidx4, align 8
+  %arrayidx = getelementptr inbounds [2000 x double], [2000 x double]* @A, i32 0, i64 %idxprom
+  %0 = load double, double* %arrayidx, align 8
+  %arrayidx4 = getelementptr inbounds [2000 x double], [2000 x double]* @B, i32 0, i64 %idxprom
+  %1 = load double, double* %arrayidx4, align 8
   %add5 = fadd double %0, %1
   store double %add5, double* %arrayidx, align 8
   %add11 = add nsw i32 %mul, 1
   %idxprom12 = sext i32 %add11 to i64
-  %arrayidx13 = getelementptr inbounds [2000 x double]* @A, i32 0, i64 %idxprom12
-  %2 = load double* %arrayidx13, align 8
-  %arrayidx17 = getelementptr inbounds [2000 x double]* @B, i32 0, i64 %idxprom12
-  %3 = load double* %arrayidx17, align 8
+  %arrayidx13 = getelementptr inbounds [2000 x double], [2000 x double]* @A, i32 0, i64 %idxprom12
+  %2 = load double, double* %arrayidx13, align 8
+  %arrayidx17 = getelementptr inbounds [2000 x double], [2000 x double]* @B, i32 0, i64 %idxprom12
+  %3 = load double, double* %arrayidx17, align 8
   %add18 = fadd double %2, %3
   store double %add18, double* %arrayidx13, align 8
   ret void
@@ -84,34 +84,34 @@ entry:
   store i32 %u, i32* %u.addr, align 4
   %mul = mul nsw i32 %u, 4
   %idxprom = sext i32 %mul to i64
-  %arrayidx = getelementptr inbounds [2000 x float]* @C, i32 0, i64 %idxprom
-  %0 = load float* %arrayidx, align 4
-  %arrayidx4 = getelementptr inbounds [2000 x float]* @D, i32 0, i64 %idxprom
-  %1 = load float* %arrayidx4, align 4
+  %arrayidx = getelementptr inbounds [2000 x float], [2000 x float]* @C, i32 0, i64 %idxprom
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx4 = getelementptr inbounds [2000 x float], [2000 x float]* @D, i32 0, i64 %idxprom
+  %1 = load float, float* %arrayidx4, align 4
   %add5 = fadd float %0, %1
   store float %add5, float* %arrayidx, align 4
   %add11 = add nsw i32 %mul, 1
   %idxprom12 = sext i32 %add11 to i64
-  %arrayidx13 = getelementptr inbounds [2000 x float]* @C, i32 0, i64 %idxprom12
-  %2 = load float* %arrayidx13, align 4
-  %arrayidx17 = getelementptr inbounds [2000 x float]* @D, i32 0, i64 %idxprom12
-  %3 = load float* %arrayidx17, align 4
+  %arrayidx13 = getelementptr inbounds [2000 x float], [2000 x float]* @C, i32 0, i64 %idxprom12
+  %2 = load float, float* %arrayidx13, align 4
+  %arrayidx17 = getelementptr inbounds [2000 x float], [2000 x float]* @D, i32 0, i64 %idxprom12
+  %3 = load float, float* %arrayidx17, align 4
   %add18 = fadd float %2, %3
   store float %add18, float* %arrayidx13, align 4
   %add24 = add nsw i32 %mul, 2
   %idxprom25 = sext i32 %add24 to i64
-  %arrayidx26 = getelementptr inbounds [2000 x float]* @C, i32 0, i64 %idxprom25
-  %4 = load float* %arrayidx26, align 4
-  %arrayidx30 = getelementptr inbounds [2000 x float]* @D, i32 0, i64 %idxprom25
-  %5 = load float* %arrayidx30, align 4
+  %arrayidx26 = getelementptr inbounds [2000 x float], [2000 x float]* @C, i32 0, i64 %idxprom25
+  %4 = load float, float* %arrayidx26, align 4
+  %arrayidx30 = getelementptr inbounds [2000 x float], [2000 x float]* @D, i32 0, i64 %idxprom25
+  %5 = load float, float* %arrayidx30, align 4
   %add31 = fadd float %4, %5
   store float %add31, float* %arrayidx26, align 4
   %add37 = add nsw i32 %mul, 3
   %idxprom38 = sext i32 %add37 to i64
-  %arrayidx39 = getelementptr inbounds [2000 x float]* @C, i32 0, i64 %idxprom38
-  %6 = load float* %arrayidx39, align 4
-  %arrayidx43 = getelementptr inbounds [2000 x float]* @D, i32 0, i64 %idxprom38
-  %7 = load float* %arrayidx43, align 4
+  %arrayidx39 = getelementptr inbounds [2000 x float], [2000 x float]* @C, i32 0, i64 %idxprom38
+  %6 = load float, float* %arrayidx39, align 4
+  %arrayidx43 = getelementptr inbounds [2000 x float], [2000 x float]* @D, i32 0, i64 %idxprom38
+  %7 = load float, float* %arrayidx43, align 4
   %add44 = fadd float %6, %7
   store float %add44, float* %arrayidx39, align 4
   ret void
@@ -142,13 +142,13 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %1 = phi double [ 0.000000e+00, %for.body.lr.ph ], [ %add7, %for.body ]
   %mul = mul nsw i32 %0, 2
   %idxprom = sext i32 %mul to i64
-  %arrayidx = getelementptr inbounds double* %A, i64 %idxprom
-  %2 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %A, i64 %idxprom
+  %2 = load double, double* %arrayidx, align 8
   %mul1 = fmul double 7.000000e+00, %2
   %add = add nsw i32 %mul, 1
   %idxprom3 = sext i32 %add to i64
-  %arrayidx4 = getelementptr inbounds double* %A, i64 %idxprom3
-  %3 = load double* %arrayidx4, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %A, i64 %idxprom3
+  %3 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double 7.000000e+00, %3
   %add6 = fadd double %mul1, %mul5
   %add7 = fadd double %1, %add6
diff --git a/test/Transforms/SLPVectorizer/X86/continue_vectorizing.ll b/test/Transforms/SLPVectorizer/X86/continue_vectorizing.ll
index ed225743a6e2..ecae70ecc918 100644
--- a/test/Transforms/SLPVectorizer/X86/continue_vectorizing.ll
+++ b/test/Transforms/SLPVectorizer/X86/continue_vectorizing.ll
@@ -9,21 +9,21 @@ target triple = "x86_64-apple-macosx10.8.0"
 ; CHECK: ret
 define void @test1(double* %a, double* %b, double* %c, double* %d) {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   store double %mul, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   %0 = bitcast double* %a to <4 x i32>*
-  %1 = load <4 x i32>* %0, align 8
+  %1 = load <4 x i32>, <4 x i32>* %0, align 8
   %2 = bitcast double* %b to <4 x i32>*
-  %3 = load <4 x i32>* %2, align 8
+  %3 = load <4 x i32>, <4 x i32>* %2, align 8
   %4 = mul <4 x i32> %1, %3
   %5 = bitcast double* %d to <4 x i32>*
   store <4 x i32> %4, <4 x i32>* %5, align 8
diff --git a/test/Transforms/SLPVectorizer/X86/crash_7zip.ll b/test/Transforms/SLPVectorizer/X86/crash_7zip.ll
index 51b1c08fb36f..54e5d5a53080 100644
--- a/test/Transforms/SLPVectorizer/X86/crash_7zip.ll
+++ b/test/Transforms/SLPVectorizer/X86/crash_7zip.ll
@@ -8,8 +8,8 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 define fastcc void @LzmaDec_DecodeReal2(%struct.CLzmaDec.1.28.55.82.103.124.145.166.181.196.229.259.334* %p) {
 entry:
-  %range20.i = getelementptr inbounds %struct.CLzmaDec.1.28.55.82.103.124.145.166.181.196.229.259.334* %p, i64 0, i32 4
-  %code21.i = getelementptr inbounds %struct.CLzmaDec.1.28.55.82.103.124.145.166.181.196.229.259.334* %p, i64 0, i32 5
+  %range20.i = getelementptr inbounds %struct.CLzmaDec.1.28.55.82.103.124.145.166.181.196.229.259.334, %struct.CLzmaDec.1.28.55.82.103.124.145.166.181.196.229.259.334* %p, i64 0, i32 4
+  %code21.i = getelementptr inbounds %struct.CLzmaDec.1.28.55.82.103.124.145.166.181.196.229.259.334, %struct.CLzmaDec.1.28.55.82.103.124.145.166.181.196.229.259.334* %p, i64 0, i32 5
   br label %do.body66.i
 
 do.body66.i:                                      ; preds = %do.cond.i, %entry
diff --git a/test/Transforms/SLPVectorizer/X86/crash_binaryop.ll b/test/Transforms/SLPVectorizer/X86/crash_binaryop.ll
index dc99366e1da7..9046c3562821 100644
--- a/test/Transforms/SLPVectorizer/X86/crash_binaryop.ll
+++ b/test/Transforms/SLPVectorizer/X86/crash_binaryop.ll
@@ -7,7 +7,7 @@ target triple = "x86_64-apple-darwin13.3.0"
 
 define i32 @fn1() {
 entry:
-  %init = load double* @a, align 8
+  %init = load double, double* @a, align 8
   br label %loop
 
 loop:
diff --git a/test/Transforms/SLPVectorizer/X86/crash_bullet.ll b/test/Transforms/SLPVectorizer/X86/crash_bullet.ll
index 389892115ced..1bad671fd824 100644
--- a/test/Transforms/SLPVectorizer/X86/crash_bullet.ll
+++ b/test/Transforms/SLPVectorizer/X86/crash_bullet.ll
@@ -13,8 +13,8 @@ if.then:                                          ; preds = %entry
   ret void
 
 if.else:                                          ; preds = %entry
-  %m_numConstraintRows4 = getelementptr inbounds %"struct.btTypedConstraint::btConstraintInfo1.17.157.357.417.477.960"* %info, i64 0, i32 0
-  %nub5 = getelementptr inbounds %"struct.btTypedConstraint::btConstraintInfo1.17.157.357.417.477.960"* %info, i64 0, i32 1
+  %m_numConstraintRows4 = getelementptr inbounds %"struct.btTypedConstraint::btConstraintInfo1.17.157.357.417.477.960", %"struct.btTypedConstraint::btConstraintInfo1.17.157.357.417.477.960"* %info, i64 0, i32 0
+  %nub5 = getelementptr inbounds %"struct.btTypedConstraint::btConstraintInfo1.17.157.357.417.477.960", %"struct.btTypedConstraint::btConstraintInfo1.17.157.357.417.477.960"* %info, i64 0, i32 1
   br i1 undef, label %land.lhs.true.i.1, label %if.then7.1
 
 land.lhs.true.i.1:                                ; preds = %if.else
@@ -43,9 +43,9 @@ for.inc.1:                                        ; preds = %if.then7.1, %land.l
 
 define void @_ZN30GIM_TRIANGLE_CALCULATION_CACHE18triangle_collisionERK9btVector3S2_S2_fS2_S2_S2_fR25GIM_TRIANGLE_CONTACT_DATA(%class.GIM_TRIANGLE_CALCULATION_CACHE.9.34.69.94.119.144.179.189.264.284.332* %this) {
 entry:
-  %arrayidx26 = getelementptr inbounds %class.GIM_TRIANGLE_CALCULATION_CACHE.9.34.69.94.119.144.179.189.264.284.332* %this, i64 0, i32 2, i64 0, i32 0, i64 1
-  %arrayidx36 = getelementptr inbounds %class.GIM_TRIANGLE_CALCULATION_CACHE.9.34.69.94.119.144.179.189.264.284.332* %this, i64 0, i32 2, i64 0, i32 0, i64 2
-  %0 = load float* %arrayidx36, align 4
+  %arrayidx26 = getelementptr inbounds %class.GIM_TRIANGLE_CALCULATION_CACHE.9.34.69.94.119.144.179.189.264.284.332, %class.GIM_TRIANGLE_CALCULATION_CACHE.9.34.69.94.119.144.179.189.264.284.332* %this, i64 0, i32 2, i64 0, i32 0, i64 1
+  %arrayidx36 = getelementptr inbounds %class.GIM_TRIANGLE_CALCULATION_CACHE.9.34.69.94.119.144.179.189.264.284.332, %class.GIM_TRIANGLE_CALCULATION_CACHE.9.34.69.94.119.144.179.189.264.284.332* %this, i64 0, i32 2, i64 0, i32 0, i64 2
+  %0 = load float, float* %arrayidx36, align 4
   %add587 = fadd float undef, undef
   %sub600 = fsub float %add587, undef
   store float %sub600, float* undef, align 4
diff --git a/test/Transforms/SLPVectorizer/X86/crash_bullet3.ll b/test/Transforms/SLPVectorizer/X86/crash_bullet3.ll
index 25c65457946b..810276929530 100644
--- a/test/Transforms/SLPVectorizer/X86/crash_bullet3.ll
+++ b/test/Transforms/SLPVectorizer/X86/crash_bullet3.ll
@@ -59,9 +59,9 @@ if.end332:                                        ; preds = %if.then329, %if.end
   %dy276.1 = phi float [ undef, %if.then329 ], [ undef, %if.end327 ], [ 0x3F847AE140000000, %if.then291 ]
   %sub334 = fsub float %add294, %dx272.1
   %sub338 = fsub float %add297, %dy276.1
-  %arrayidx.i.i606 = getelementptr inbounds %class.btVector3.23.221.463.485.507.573.595.683.727.749.815.837.991.1585.1607.1629.1651.1849.2047.2069.2091.2113* %vertices, i64 0, i32 0, i64 0
+  %arrayidx.i.i606 = getelementptr inbounds %class.btVector3.23.221.463.485.507.573.595.683.727.749.815.837.991.1585.1607.1629.1651.1849.2047.2069.2091.2113, %class.btVector3.23.221.463.485.507.573.595.683.727.749.815.837.991.1585.1607.1629.1651.1849.2047.2069.2091.2113* %vertices, i64 0, i32 0, i64 0
   store float %sub334, float* %arrayidx.i.i606, align 4
-  %arrayidx3.i607 = getelementptr inbounds %class.btVector3.23.221.463.485.507.573.595.683.727.749.815.837.991.1585.1607.1629.1651.1849.2047.2069.2091.2113* %vertices, i64 0, i32 0, i64 1
+  %arrayidx3.i607 = getelementptr inbounds %class.btVector3.23.221.463.485.507.573.595.683.727.749.815.837.991.1585.1607.1629.1651.1849.2047.2069.2091.2113, %class.btVector3.23.221.463.485.507.573.595.683.727.749.815.837.991.1585.1607.1629.1651.1849.2047.2069.2091.2113* %vertices, i64 0, i32 0, i64 1
   store float %sub338, float* %arrayidx3.i607, align 4
   br label %return
 
diff --git a/test/Transforms/SLPVectorizer/X86/crash_cmpop.ll b/test/Transforms/SLPVectorizer/X86/crash_cmpop.ll
new file mode 100644
index 000000000000..f10c8626d417
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/crash_cmpop.ll
@@ -0,0 +1,56 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -S
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+define void @testfunc(float* nocapture %dest, float* nocapture readonly %src) {
+entry:
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %acc1.056 = phi float [ 0.000000e+00, %entry ], [ %add13, %for.body ]
+  %s1.055 = phi float [ 0.000000e+00, %entry ], [ %cond.i40, %for.body ]
+  %s0.054 = phi float [ 0.000000e+00, %entry ], [ %cond.i44, %for.body ]
+  %arrayidx = getelementptr inbounds float, float* %src, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %arrayidx2 = getelementptr inbounds float, float* %dest, i64 %indvars.iv
+  store float %acc1.056, float* %arrayidx2, align 4
+  %add = fadd float %s0.054, %0
+  %add3 = fadd float %s1.055, %0
+  %mul = fmul float %s0.054, 0.000000e+00
+  %add4 = fadd float %mul, %add3
+  %mul5 = fmul float %s1.055, 0.000000e+00
+  %add6 = fadd float %mul5, %add
+  %cmp.i = fcmp olt float %add6, 1.000000e+00
+  %cond.i = select i1 %cmp.i, float %add6, float 1.000000e+00
+  %cmp.i51 = fcmp olt float %cond.i, -1.000000e+00
+  %cmp.i49 = fcmp olt float %add4, 1.000000e+00
+  %cond.i50 = select i1 %cmp.i49, float %add4, float 1.000000e+00
+  %cmp.i47 = fcmp olt float %cond.i50, -1.000000e+00
+  %cond.i.op = fmul float %cond.i, 0.000000e+00
+  %mul10 = select i1 %cmp.i51, float -0.000000e+00, float %cond.i.op
+  %cond.i50.op = fmul float %cond.i50, 0.000000e+00
+  %mul11 = select i1 %cmp.i47, float -0.000000e+00, float %cond.i50.op
+  %add13 = fadd float %mul10, %mul11
+
+  ; The SLPVectorizer crashed in vectorizeChainsInBlock() because it tried
+  ; to access the second operand of the following cmp after the cmp itself
+  ; was already vectorized and deleted.
+  %cmp.i45 = fcmp olt float %add13, 1.000000e+00
+
+  %cond.i46 = select i1 %cmp.i45, float %add13, float 1.000000e+00
+  %cmp.i43 = fcmp olt float %cond.i46, -1.000000e+00
+  %cond.i44 = select i1 %cmp.i43, float -1.000000e+00, float %cond.i46
+  %cmp.i41 = fcmp olt float %mul11, 1.000000e+00
+  %cond.i42 = select i1 %cmp.i41, float %mul11, float 1.000000e+00
+  %cmp.i39 = fcmp olt float %cond.i42, -1.000000e+00
+  %cond.i40 = select i1 %cmp.i39, float -1.000000e+00, float %cond.i42
+  %exitcond = icmp eq i64 %indvars.iv.next, 32
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
diff --git a/test/Transforms/SLPVectorizer/X86/crash_dequeue.ll b/test/Transforms/SLPVectorizer/X86/crash_dequeue.ll
index ce0159071c60..28b7aa3c4de3 100644
--- a/test/Transforms/SLPVectorizer/X86/crash_dequeue.ll
+++ b/test/Transforms/SLPVectorizer/X86/crash_dequeue.ll
@@ -7,13 +7,13 @@ target triple = "x86_64-apple-macosx10.8.0"
 ; Function Attrs: nounwind ssp uwtable
 define void @_ZSt6uniqueISt15_Deque_iteratorIdRdPdEET_S4_S4_(%"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* %__first, %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* nocapture %__last) {
 entry:
-  %_M_cur2.i.i = getelementptr inbounds %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* %__first, i64 0, i32 0
-  %0 = load double** %_M_cur2.i.i, align 8
-  %_M_first3.i.i = getelementptr inbounds %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* %__first, i64 0, i32 1
-  %_M_cur2.i.i81 = getelementptr inbounds %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* %__last, i64 0, i32 0
-  %1 = load double** %_M_cur2.i.i81, align 8
-  %_M_first3.i.i83 = getelementptr inbounds %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* %__last, i64 0, i32 1
-  %2 = load double** %_M_first3.i.i83, align 8
+  %_M_cur2.i.i = getelementptr inbounds %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731", %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* %__first, i64 0, i32 0
+  %0 = load double*, double** %_M_cur2.i.i, align 8
+  %_M_first3.i.i = getelementptr inbounds %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731", %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* %__first, i64 0, i32 1
+  %_M_cur2.i.i81 = getelementptr inbounds %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731", %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* %__last, i64 0, i32 0
+  %1 = load double*, double** %_M_cur2.i.i81, align 8
+  %_M_first3.i.i83 = getelementptr inbounds %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731", %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* %__last, i64 0, i32 1
+  %2 = load double*, double** %_M_first3.i.i83, align 8
   br i1 undef, label %_ZSt13adjacent_findISt15_Deque_iteratorIdRdPdEET_S4_S4_.exit, label %while.cond.i.preheader
 
 while.cond.i.preheader:                           ; preds = %entry
diff --git a/test/Transforms/SLPVectorizer/X86/crash_gep.ll b/test/Transforms/SLPVectorizer/X86/crash_gep.ll
index dd4034c116e4..bd1e8f7cc19d 100644
--- a/test/Transforms/SLPVectorizer/X86/crash_gep.ll
+++ b/test/Transforms/SLPVectorizer/X86/crash_gep.ll
@@ -8,10 +8,10 @@ target triple = "x86_64-unknown-linux-gnu"
 ; Function Attrs: nounwind uwtable
 define i32 @fn1() {
 entry:
-  %0 = load i64** @a, align 8
-  %add.ptr = getelementptr inbounds i64* %0, i64 1
+  %0 = load i64*, i64** @a, align 8
+  %add.ptr = getelementptr inbounds i64, i64* %0, i64 1
   %1 = ptrtoint i64* %add.ptr to i64
-  %arrayidx = getelementptr inbounds i64* %0, i64 2
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 2
   store i64 %1, i64* %arrayidx, align 8
   %2 = ptrtoint i64* %arrayidx to i64
   store i64 %2, i64* %add.ptr, align 8
diff --git a/test/Transforms/SLPVectorizer/X86/crash_lencod.ll b/test/Transforms/SLPVectorizer/X86/crash_lencod.ll
index c02e1fa607d5..70b13fd75f14 100644
--- a/test/Transforms/SLPVectorizer/X86/crash_lencod.ll
+++ b/test/Transforms/SLPVectorizer/X86/crash_lencod.ll
@@ -68,23 +68,23 @@ if.end103:                                        ; preds = %if.else, %if.then88
 define void @intrapred_luma() {
 entry:
   %conv153 = trunc i32 undef to i16
-  %arrayidx154 = getelementptr inbounds [13 x i16]* undef, i64 0, i64 12
+  %arrayidx154 = getelementptr inbounds [13 x i16], [13 x i16]* undef, i64 0, i64 12
   store i16 %conv153, i16* %arrayidx154, align 8
-  %arrayidx155 = getelementptr inbounds [13 x i16]* undef, i64 0, i64 11
+  %arrayidx155 = getelementptr inbounds [13 x i16], [13 x i16]* undef, i64 0, i64 11
   store i16 %conv153, i16* %arrayidx155, align 2
-  %arrayidx156 = getelementptr inbounds [13 x i16]* undef, i64 0, i64 10
+  %arrayidx156 = getelementptr inbounds [13 x i16], [13 x i16]* undef, i64 0, i64 10
   store i16 %conv153, i16* %arrayidx156, align 4
   ret void
 }
 
 define fastcc void @dct36(double* %inbuf) {
 entry:
-  %arrayidx41 = getelementptr inbounds double* %inbuf, i64 2
-  %arrayidx44 = getelementptr inbounds double* %inbuf, i64 1
-  %0 = load double* %arrayidx44, align 8
+  %arrayidx41 = getelementptr inbounds double, double* %inbuf, i64 2
+  %arrayidx44 = getelementptr inbounds double, double* %inbuf, i64 1
+  %0 = load double, double* %arrayidx44, align 8
   %add46 = fadd double %0, undef
   store double %add46, double* %arrayidx41, align 8
-  %1 = load double* %inbuf, align 8
+  %1 = load double, double* %inbuf, align 8
   %add49 = fadd double %1, %0
   store double %add49, double* %arrayidx44, align 8
   ret void
diff --git a/test/Transforms/SLPVectorizer/X86/crash_mandeltext.ll b/test/Transforms/SLPVectorizer/X86/crash_mandeltext.ll
index d6915e2dc5d6..f82343fb433f 100644
--- a/test/Transforms/SLPVectorizer/X86/crash_mandeltext.ll
+++ b/test/Transforms/SLPVectorizer/X86/crash_mandeltext.ll
@@ -55,18 +55,18 @@ for.end48:                                        ; preds = %for.end44
 
 define void @zot(%struct.hoge* %arg) {
 bb:
-  %tmp = load double* undef, align 8
+  %tmp = load double, double* undef, align 8
   %tmp1 = fsub double %tmp, undef
-  %tmp2 = load double* undef, align 8
+  %tmp2 = load double, double* undef, align 8
   %tmp3 = fsub double %tmp2, undef
   %tmp4 = fmul double %tmp3, undef
   %tmp5 = fmul double %tmp3, undef
   %tmp6 = fsub double %tmp5, undef
-  %tmp7 = getelementptr inbounds %struct.hoge* %arg, i64 0, i32 1
+  %tmp7 = getelementptr inbounds %struct.hoge, %struct.hoge* %arg, i64 0, i32 1
   store double %tmp6, double* %tmp7, align 8
   %tmp8 = fmul double %tmp1, undef
   %tmp9 = fsub double %tmp8, undef
-  %tmp10 = getelementptr inbounds %struct.hoge* %arg, i64 0, i32 2
+  %tmp10 = getelementptr inbounds %struct.hoge, %struct.hoge* %arg, i64 0, i32 2
   store double %tmp9, double* %tmp10, align 8
   br i1 undef, label %bb11, label %bb12
 
@@ -86,8 +86,8 @@ bb14:                                             ; preds = %bb12, %bb11
 
 define void @rc4_crypt(%struct.rc4_state.0.24* nocapture %s) {
 entry:
-  %x1 = getelementptr inbounds %struct.rc4_state.0.24* %s, i64 0, i32 0
-  %y2 = getelementptr inbounds %struct.rc4_state.0.24* %s, i64 0, i32 1
+  %x1 = getelementptr inbounds %struct.rc4_state.0.24, %struct.rc4_state.0.24* %s, i64 0, i32 0
+  %y2 = getelementptr inbounds %struct.rc4_state.0.24, %struct.rc4_state.0.24* %s, i64 0, i32 1
   br i1 undef, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.body, %entry
diff --git a/test/Transforms/SLPVectorizer/X86/crash_netbsd_decompress.ll b/test/Transforms/SLPVectorizer/X86/crash_netbsd_decompress.ll
index 8da3c34a0279..e1df98d83bdb 100644
--- a/test/Transforms/SLPVectorizer/X86/crash_netbsd_decompress.ll
+++ b/test/Transforms/SLPVectorizer/X86/crash_netbsd_decompress.ll
@@ -13,14 +13,14 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 define i32 @fn1() {
 entry:
-  %0 = load i32* getelementptr inbounds (%struct.DState* @b, i32 0, i32 0), align 4
-  %1 = load i32* getelementptr inbounds (%struct.DState* @b, i32 0, i32 1), align 4
-  %2 = load i32* @d, align 4
+  %0 = load i32, i32* getelementptr inbounds (%struct.DState, %struct.DState* @b, i32 0, i32 0), align 4
+  %1 = load i32, i32* getelementptr inbounds (%struct.DState, %struct.DState* @b, i32 0, i32 1), align 4
+  %2 = load i32, i32* @d, align 4
   %cond = icmp eq i32 %2, 0
   br i1 %cond, label %sw.bb, label %save_state_and_return
 
 sw.bb:                                            ; preds = %entry
-  %3 = load i32* @c, align 4
+  %3 = load i32, i32* @c, align 4
   %and = and i32 %3, 7
   store i32 %and, i32* @a, align 4
   switch i32 %and, label %if.end [
@@ -34,8 +34,8 @@ if.end:                                           ; preds = %sw.bb
 save_state_and_return:                            ; preds = %sw.bb, %sw.bb, %if.end, %entry
   %t.0 = phi i32 [ 0, %if.end ], [ %0, %entry ], [ %0, %sw.bb ], [ %0, %sw.bb ]
   %f.0 = phi i32 [ 0, %if.end ], [ %1, %entry ], [ 0, %sw.bb ], [ 0, %sw.bb ]
-  store i32 %t.0, i32* getelementptr inbounds (%struct.DState* @b, i32 0, i32 0), align 4
-  store i32 %f.0, i32* getelementptr inbounds (%struct.DState* @b, i32 0, i32 1), align 4
+  store i32 %t.0, i32* getelementptr inbounds (%struct.DState, %struct.DState* @b, i32 0, i32 0), align 4
+  store i32 %f.0, i32* getelementptr inbounds (%struct.DState, %struct.DState* @b, i32 0, i32 1), align 4
   ret i32 undef
 }
 
diff --git a/test/Transforms/SLPVectorizer/X86/crash_scheduling.ll b/test/Transforms/SLPVectorizer/X86/crash_scheduling.ll
index e6cc0f783d79..14a8b35f550a 100644
--- a/test/Transforms/SLPVectorizer/X86/crash_scheduling.ll
+++ b/test/Transforms/SLPVectorizer/X86/crash_scheduling.ll
@@ -25,11 +25,11 @@ for.body:
   %p3.addr.0258 = phi double [ %add, %bb1 ], [ %add28, %for.body ]
   %vecinit.i.i237 = insertelement <2 x double> undef, double %t.0259, i32 0
   %x13 = tail call i32 @_xfn(<2 x double> %vecinit.i.i237) #2
-  %arrayidx = getelementptr inbounds [256 x i32]* %tab1, i64 0, i64 %indvars.iv266
+  %arrayidx = getelementptr inbounds [256 x i32], [256 x i32]* %tab1, i64 0, i64 %indvars.iv266
   store i32 %x13, i32* %arrayidx, align 4, !tbaa !4
   %vecinit.i.i = insertelement <2 x double> undef, double %p3.addr.0258, i32 0
   %x14 = tail call i32 @_xfn(<2 x double> %vecinit.i.i) #2
-  %arrayidx26 = getelementptr inbounds [256 x i32]* %tab2, i64 0, i64 %indvars.iv266
+  %arrayidx26 = getelementptr inbounds [256 x i32], [256 x i32]* %tab2, i64 0, i64 %indvars.iv266
   store i32 %x14, i32* %arrayidx26, align 4, !tbaa !4
   %add27 = fadd double %mul19, %t.0259
   %add28 = fadd double %mul21, %p3.addr.0258
diff --git a/test/Transforms/SLPVectorizer/X86/crash_sim4b1.ll b/test/Transforms/SLPVectorizer/X86/crash_sim4b1.ll
index 05415456cf0f..5a576c2a7222 100644
--- a/test/Transforms/SLPVectorizer/X86/crash_sim4b1.ll
+++ b/test/Transforms/SLPVectorizer/X86/crash_sim4b1.ll
@@ -34,13 +34,13 @@ land.rhs.lr.ph:                                   ; preds = %if.then17
   unreachable
 
 if.end98:                                         ; preds = %if.then17
-  %from299 = getelementptr inbounds %struct._exon_t.12.103.220.363.480.649.740.857.1039.1065.1078.1091.1117.1130.1156.1169.1195.1221.1234.1286.1299.1312.1338.1429.1455.1468.1494.1520.1884.1897.1975.2066.2105.2170.2171* undef, i64 0, i32 1
+  %from299 = getelementptr inbounds %struct._exon_t.12.103.220.363.480.649.740.857.1039.1065.1078.1091.1117.1130.1156.1169.1195.1221.1234.1286.1299.1312.1338.1429.1455.1468.1494.1520.1884.1897.1975.2066.2105.2170.2171, %struct._exon_t.12.103.220.363.480.649.740.857.1039.1065.1078.1091.1117.1130.1156.1169.1195.1221.1234.1286.1299.1312.1338.1429.1455.1468.1494.1520.1884.1897.1975.2066.2105.2170.2171* undef, i64 0, i32 1
   br i1 undef, label %land.lhs.true167, label %if.then103
 
 if.then103:                                       ; preds = %if.end98
   %.sub100 = select i1 undef, i32 250, i32 undef
   %mul114 = shl nsw i32 %.sub100, 2
-  %from1115 = getelementptr inbounds %struct._exon_t.12.103.220.363.480.649.740.857.1039.1065.1078.1091.1117.1130.1156.1169.1195.1221.1234.1286.1299.1312.1338.1429.1455.1468.1494.1520.1884.1897.1975.2066.2105.2170.2171* undef, i64 0, i32 0
+  %from1115 = getelementptr inbounds %struct._exon_t.12.103.220.363.480.649.740.857.1039.1065.1078.1091.1117.1130.1156.1169.1195.1221.1234.1286.1299.1312.1338.1429.1455.1468.1494.1520.1884.1897.1975.2066.2105.2170.2171, %struct._exon_t.12.103.220.363.480.649.740.857.1039.1065.1078.1091.1117.1130.1156.1169.1195.1221.1234.1286.1299.1312.1338.1429.1455.1468.1494.1520.1884.1897.1975.2066.2105.2170.2171* undef, i64 0, i32 0
   %cond125 = select i1 undef, i32 undef, i32 %mul114
   br label %for.cond.i
 
diff --git a/test/Transforms/SLPVectorizer/X86/crash_smallpt.ll b/test/Transforms/SLPVectorizer/X86/crash_smallpt.ll
index 915c41bb9c59..273584c11a9c 100644
--- a/test/Transforms/SLPVectorizer/X86/crash_smallpt.ll
+++ b/test/Transforms/SLPVectorizer/X86/crash_smallpt.ll
@@ -21,10 +21,10 @@ invoke.cont:                                      ; preds = %invoke.cont, %cond.
   br i1 undef, label %arrayctor.cont, label %invoke.cont
 
 arrayctor.cont:                                   ; preds = %invoke.cont
-  %agg.tmp99208.sroa.0.0.idx = getelementptr inbounds %struct.Ray.5.11.53.113.119.137.149.185.329.389.416* undef, i64 0, i32 0, i32 0
-  %agg.tmp99208.sroa.1.8.idx388 = getelementptr inbounds %struct.Ray.5.11.53.113.119.137.149.185.329.389.416* undef, i64 0, i32 0, i32 1
-  %agg.tmp101211.sroa.0.0.idx = getelementptr inbounds %struct.Ray.5.11.53.113.119.137.149.185.329.389.416* undef, i64 0, i32 1, i32 0
-  %agg.tmp101211.sroa.1.8.idx390 = getelementptr inbounds %struct.Ray.5.11.53.113.119.137.149.185.329.389.416* undef, i64 0, i32 1, i32 1
+  %agg.tmp99208.sroa.0.0.idx = getelementptr inbounds %struct.Ray.5.11.53.113.119.137.149.185.329.389.416, %struct.Ray.5.11.53.113.119.137.149.185.329.389.416* undef, i64 0, i32 0, i32 0
+  %agg.tmp99208.sroa.1.8.idx388 = getelementptr inbounds %struct.Ray.5.11.53.113.119.137.149.185.329.389.416, %struct.Ray.5.11.53.113.119.137.149.185.329.389.416* undef, i64 0, i32 0, i32 1
+  %agg.tmp101211.sroa.0.0.idx = getelementptr inbounds %struct.Ray.5.11.53.113.119.137.149.185.329.389.416, %struct.Ray.5.11.53.113.119.137.149.185.329.389.416* undef, i64 0, i32 1, i32 0
+  %agg.tmp101211.sroa.1.8.idx390 = getelementptr inbounds %struct.Ray.5.11.53.113.119.137.149.185.329.389.416, %struct.Ray.5.11.53.113.119.137.149.185.329.389.416* undef, i64 0, i32 1, i32 1
   br label %for.cond36.preheader
 
 for.cond36.preheader:                             ; preds = %_Z5clampd.exit.1, %arrayctor.cont
@@ -89,9 +89,9 @@ if.then38:                                        ; preds = %entry
   %add4.i698 = fadd double undef, %add4.i719
   %mul.i.i679 = fmul double undef, %add.i695
   %mul2.i.i680 = fmul double undef, %add4.i698
-  %agg.tmp74663.sroa.0.0.idx = getelementptr inbounds %struct.Ray.5.11.53.95.137.191.197.203.239.257.263.269.275.281.287.293.383.437.443.455.461.599.601* undef, i64 0, i32 1, i32 0
+  %agg.tmp74663.sroa.0.0.idx = getelementptr inbounds %struct.Ray.5.11.53.95.137.191.197.203.239.257.263.269.275.281.287.293.383.437.443.455.461.599.601, %struct.Ray.5.11.53.95.137.191.197.203.239.257.263.269.275.281.287.293.383.437.443.455.461.599.601* undef, i64 0, i32 1, i32 0
   store double %mul.i.i679, double* %agg.tmp74663.sroa.0.0.idx, align 8
-  %agg.tmp74663.sroa.1.8.idx943 = getelementptr inbounds %struct.Ray.5.11.53.95.137.191.197.203.239.257.263.269.275.281.287.293.383.437.443.455.461.599.601* undef, i64 0, i32 1, i32 1
+  %agg.tmp74663.sroa.1.8.idx943 = getelementptr inbounds %struct.Ray.5.11.53.95.137.191.197.203.239.257.263.269.275.281.287.293.383.437.443.455.461.599.601, %struct.Ray.5.11.53.95.137.191.197.203.239.257.263.269.275.281.287.293.383.437.443.455.461.599.601* undef, i64 0, i32 1, i32 1
   store double %mul2.i.i680, double* %agg.tmp74663.sroa.1.8.idx943, align 8
   br label %return
 
diff --git a/test/Transforms/SLPVectorizer/X86/crash_vectorizeTree.ll b/test/Transforms/SLPVectorizer/X86/crash_vectorizeTree.ll
index 9f1fb71e096f..45ca99a3ea16 100644
--- a/test/Transforms/SLPVectorizer/X86/crash_vectorizeTree.ll
+++ b/test/Transforms/SLPVectorizer/X86/crash_vectorizeTree.ll
@@ -17,12 +17,12 @@ target triple = "x86_64-apple-macosx10.9.0"
 
 ;define fastcc void @bar() {
 define void @bar() {
-  %1 = getelementptr inbounds %0* undef, i64 0, i32 1, i32 0
-  %2 = getelementptr inbounds %0* undef, i64 0, i32 1, i32 1
-  %3 = getelementptr inbounds %0* undef, i64 0, i32 1, i32 0
-  %4 = getelementptr inbounds %0* undef, i64 0, i32 1, i32 1
-  %5 = getelementptr inbounds %0* undef, i64 0, i32 1, i32 0
-  %6 = getelementptr inbounds %0* undef, i64 0, i32 1, i32 1
+  %1 = getelementptr inbounds %0, %0* undef, i64 0, i32 1, i32 0
+  %2 = getelementptr inbounds %0, %0* undef, i64 0, i32 1, i32 1
+  %3 = getelementptr inbounds %0, %0* undef, i64 0, i32 1, i32 0
+  %4 = getelementptr inbounds %0, %0* undef, i64 0, i32 1, i32 1
+  %5 = getelementptr inbounds %0, %0* undef, i64 0, i32 1, i32 0
+  %6 = getelementptr inbounds %0, %0* undef, i64 0, i32 1, i32 1
   br label %7
 
 ; <label>:7                                       ; preds = %18, %17, %17, %0
@@ -30,8 +30,8 @@ define void @bar() {
   %9 = phi double [ 1.800000e+01, %0 ], [ %10, %18 ], [ %10, %17 ], [ %10, %17 ]
   store double %9, double* %1, align 8
   store double %8, double* %2, align 8
-  %10 = load double* %3, align 8
-  %11 = load double* %4, align 8
+  %10 = load double, double* %3, align 8
+  %11 = load double, double* %4, align 8
   br i1 undef, label %12, label %13
 
 ; <label>:12                                      ; preds = %7
diff --git a/test/Transforms/SLPVectorizer/X86/cross_block_slp.ll b/test/Transforms/SLPVectorizer/X86/cross_block_slp.ll
index 06c4b524ee95..eac20a006450 100644
--- a/test/Transforms/SLPVectorizer/X86/cross_block_slp.ll
+++ b/test/Transforms/SLPVectorizer/X86/cross_block_slp.ll
@@ -26,26 +26,26 @@ target triple = "x86_64-apple-macosx10.8.0"
 ;CHECK: ret
 define i32 @foo(double* nocapture %A, float* nocapture %B, i32 %g) {
 entry:
-  %0 = load float* %B, align 4
-  %arrayidx1 = getelementptr inbounds float* %B, i64 1
-  %1 = load float* %arrayidx1, align 4
+  %0 = load float, float* %B, align 4
+  %arrayidx1 = getelementptr inbounds float, float* %B, i64 1
+  %1 = load float, float* %arrayidx1, align 4
   %add = fadd float %0, 5.000000e+00
   %add2 = fadd float %1, 8.000000e+00
   %tobool = icmp eq i32 %g, 0
   br i1 %tobool, label %if.end, label %if.then
 
 if.then:
-  %call = tail call i32 (...)* @bar()
+  %call = tail call i32 (...) @bar()
   br label %if.end
 
 if.end:
   %conv = fpext float %add to double
-  %2 = load double* %A, align 8
+  %2 = load double, double* %A, align 8
   %add4 = fadd double %conv, %2
   store double %add4, double* %A, align 8
   %conv5 = fpext float %add2 to double
-  %arrayidx6 = getelementptr inbounds double* %A, i64 1
-  %3 = load double* %arrayidx6, align 8
+  %arrayidx6 = getelementptr inbounds double, double* %A, i64 1
+  %3 = load double, double* %arrayidx6, align 8
   %add7 = fadd double %conv5, %3
   store double %add7, double* %arrayidx6, align 8
   ret i32 undef
diff --git a/test/Transforms/SLPVectorizer/X86/cse.ll b/test/Transforms/SLPVectorizer/X86/cse.ll
index d2ad7eb1a82a..9f56e2195991 100644
--- a/test/Transforms/SLPVectorizer/X86/cse.ll
+++ b/test/Transforms/SLPVectorizer/X86/cse.ll
@@ -21,23 +21,23 @@ target triple = "i386-apple-macosx10.8.0"
 
 define i32 @test(double* nocapture %G) {
 entry:
-  %arrayidx = getelementptr inbounds double* %G, i64 5
-  %0 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %G, i64 5
+  %0 = load double, double* %arrayidx, align 8
   %mul = fmul double %0, 4.000000e+00
   %add = fadd double %mul, 1.000000e+00
   store double %add, double* %G, align 8
-  %arrayidx2 = getelementptr inbounds double* %G, i64 6
-  %1 = load double* %arrayidx2, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %G, i64 6
+  %1 = load double, double* %arrayidx2, align 8
   %mul3 = fmul double %1, 3.000000e+00
   %add4 = fadd double %mul3, 6.000000e+00
-  %arrayidx5 = getelementptr inbounds double* %G, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %G, i64 1
   store double %add4, double* %arrayidx5, align 8
   %add8 = fadd double %mul, 7.000000e+00
-  %arrayidx9 = getelementptr inbounds double* %G, i64 2
+  %arrayidx9 = getelementptr inbounds double, double* %G, i64 2
   store double %add8, double* %arrayidx9, align 8
   %mul11 = fmul double %1, 4.000000e+00
   %add12 = fadd double %mul11, 8.000000e+00
-  %arrayidx13 = getelementptr inbounds double* %G, i64 3
+  %arrayidx13 = getelementptr inbounds double, double* %G, i64 3
   store double %add12, double* %arrayidx13, align 8
   ret i32 undef
 }
@@ -55,26 +55,26 @@ entry:
 ;CHECK: ret
 define i32 @foo(double* nocapture %A, i32 %n) {
 entry:
-  %0 = load double* %A, align 8
+  %0 = load double, double* %A, align 8
   %mul = fmul double %0, 7.900000e+00
   %conv = sitofp i32 %n to double
   %mul1 = fmul double %conv, %mul
   %add = fadd double %mul1, 6.000000e+00
   store double %add, double* %A, align 8
-  %arrayidx3 = getelementptr inbounds double* %A, i64 1
-  %1 = load double* %arrayidx3, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %A, i64 1
+  %1 = load double, double* %arrayidx3, align 8
   %mul4 = fmul double %1, 7.700000e+00
   %mul6 = fmul double %conv, %mul4
   %add7 = fadd double %mul6, 2.000000e+00
   store double %add7, double* %arrayidx3, align 8
-  %arrayidx9 = getelementptr inbounds double* %A, i64 2
-  %2 = load double* %arrayidx9, align 8
+  %arrayidx9 = getelementptr inbounds double, double* %A, i64 2
+  %2 = load double, double* %arrayidx9, align 8
   %mul10 = fmul double %2, 7.600000e+00
   %mul12 = fmul double %conv, %mul10
   %add13 = fadd double %mul12, 3.000000e+00
   store double %add13, double* %arrayidx9, align 8
-  %arrayidx15 = getelementptr inbounds double* %A, i64 3
-  %3 = load double* %arrayidx15, align 8
+  %arrayidx15 = getelementptr inbounds double, double* %A, i64 3
+  %3 = load double, double* %arrayidx15, align 8
   %mul16 = fmul double %3, 7.400000e+00
   %mul18 = fmul double %conv, %mul16
   %add19 = fadd double %mul18, 4.000000e+00
@@ -101,31 +101,31 @@ entry:
 ; CHECK: ret
 define i32 @test2(double* nocapture %G, i32 %k) {
   %1 = icmp eq i32 %k, 0
-  %2 = getelementptr inbounds double* %G, i64 5
-  %3 = load double* %2, align 8
+  %2 = getelementptr inbounds double, double* %G, i64 5
+  %3 = load double, double* %2, align 8
   %4 = fmul double %3, 4.000000e+00
   br i1 %1, label %12, label %5
 
 ; <label>:5                                       ; preds = %0
   %6 = fadd double %4, 1.000000e+00
   store double %6, double* %G, align 8
-  %7 = getelementptr inbounds double* %G, i64 6
-  %8 = load double* %7, align 8
+  %7 = getelementptr inbounds double, double* %G, i64 6
+  %8 = load double, double* %7, align 8
   %9 = fmul double %8, 3.000000e+00
   %10 = fadd double %9, 6.000000e+00
-  %11 = getelementptr inbounds double* %G, i64 1
+  %11 = getelementptr inbounds double, double* %G, i64 1
   store double %10, double* %11, align 8
   br label %20
 
 ; <label>:12                                      ; preds = %0
   %13 = fadd double %4, 7.000000e+00
-  %14 = getelementptr inbounds double* %G, i64 2
+  %14 = getelementptr inbounds double, double* %G, i64 2
   store double %13, double* %14, align 8
-  %15 = getelementptr inbounds double* %G, i64 6
-  %16 = load double* %15, align 8
+  %15 = getelementptr inbounds double, double* %G, i64 6
+  %16 = load double, double* %15, align 8
   %17 = fmul double %16, 3.000000e+00
   %18 = fadd double %17, 8.000000e+00
-  %19 = getelementptr inbounds double* %G, i64 3
+  %19 = getelementptr inbounds double, double* %G, i64 3
   store double %18, double* %19, align 8
   br label %20
 
@@ -147,26 +147,26 @@ define i32 @test2(double* nocapture %G, i32 %k) {
 ;CHECK: ret
 define i32 @foo4(double* nocapture %A, i32 %n) {
 entry:
-  %0 = load double* %A, align 8
+  %0 = load double, double* %A, align 8
   %mul = fmul double %0, 7.900000e+00
   %conv = sitofp i32 %n to double
   %mul1 = fmul double %conv, %mul
   %add = fadd double %mul1, 6.000000e+00
   store double %add, double* %A, align 8
-  %arrayidx3 = getelementptr inbounds double* %A, i64 1
-  %1 = load double* %arrayidx3, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %A, i64 1
+  %1 = load double, double* %arrayidx3, align 8
   %mul4 = fmul double %1, 7.900000e+00
   %mul6 = fmul double %conv, %mul4
   %add7 = fadd double %mul6, 6.000000e+00
   store double %add7, double* %arrayidx3, align 8
-  %arrayidx9 = getelementptr inbounds double* %A, i64 2
-  %2 = load double* %arrayidx9, align 8
+  %arrayidx9 = getelementptr inbounds double, double* %A, i64 2
+  %2 = load double, double* %arrayidx9, align 8
   %mul10 = fmul double %2, 7.900000e+00
   %mul12 = fmul double %conv, %mul10
   %add13 = fadd double %mul12, 6.000000e+00
   store double %add13, double* %arrayidx9, align 8
-  %arrayidx15 = getelementptr inbounds double* %A, i64 3
-  %3 = load double* %arrayidx15, align 8
+  %arrayidx15 = getelementptr inbounds double, double* %A, i64 3
+  %3 = load double, double* %arrayidx15, align 8
   %mul16 = fmul double %3, 7.900000e+00
   %mul18 = fmul double %conv, %mul16
   %add19 = fadd double %mul18, 6.000000e+00
@@ -189,24 +189,24 @@ entry:
 ;CHECK: ret
 define i32 @partial_mrg(double* nocapture %A, i32 %n) {
 entry:
-  %0 = load double* %A, align 8
+  %0 = load double, double* %A, align 8
   %conv = sitofp i32 %n to double
   %mul = fmul double %conv, %0
   store double %mul, double* %A, align 8
-  %arrayidx2 = getelementptr inbounds double* %A, i64 1
-  %1 = load double* %arrayidx2, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %A, i64 1
+  %1 = load double, double* %arrayidx2, align 8
   %mul4 = fmul double %conv, %1
   store double %mul4, double* %arrayidx2, align 8
   %cmp = icmp slt i32 %n, 4
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
-  %arrayidx7 = getelementptr inbounds double* %A, i64 2
-  %2 = load double* %arrayidx7, align 8
+  %arrayidx7 = getelementptr inbounds double, double* %A, i64 2
+  %2 = load double, double* %arrayidx7, align 8
   %mul9 = fmul double %conv, %2
   store double %mul9, double* %arrayidx7, align 8
-  %arrayidx11 = getelementptr inbounds double* %A, i64 3
-  %3 = load double* %arrayidx11, align 8
+  %arrayidx11 = getelementptr inbounds double, double* %A, i64 3
+  %3 = load double, double* %arrayidx11, align 8
   %add = add nsw i32 %n, 4
   %conv12 = sitofp i32 %add to double
   %mul13 = fmul double %conv12, %3
@@ -227,19 +227,19 @@ entry:
   br i1 undef, label %if.end13, label %if.end13
 
 sw.epilog7:                                       ; No predecessors!
-  %.in = getelementptr inbounds %class.B.53.55* %this, i64 0, i32 0, i32 1
-  %0 = load double* %.in, align 8
+  %.in = getelementptr inbounds %class.B.53.55, %class.B.53.55* %this, i64 0, i32 0, i32 1
+  %0 = load double, double* %.in, align 8
   %add = fadd double undef, 0.000000e+00
   %add6 = fadd double %add, %0
-  %1 = load double* @a, align 8
+  %1 = load double, double* @a, align 8
   %add8 = fadd double %1, 0.000000e+00
-  %_dy = getelementptr inbounds %class.B.53.55* %this, i64 0, i32 0, i32 2
-  %2 = load double* %_dy, align 8
+  %_dy = getelementptr inbounds %class.B.53.55, %class.B.53.55* %this, i64 0, i32 0, i32 2
+  %2 = load double, double* %_dy, align 8
   %add10 = fadd double %add8, %2
   br i1 undef, label %if.then12, label %if.end13
 
 if.then12:                                        ; preds = %sw.epilog7
-  %3 = load double* undef, align 8
+  %3 = load double, double* undef, align 8
   br label %if.end13
 
 if.end13:                                         ; preds = %if.then12, %sw.epilog7, %entry
diff --git a/test/Transforms/SLPVectorizer/X86/cycle_dup.ll b/test/Transforms/SLPVectorizer/X86/cycle_dup.ll
index bac2c3c0df34..0a4e961c2e88 100644
--- a/test/Transforms/SLPVectorizer/X86/cycle_dup.ll
+++ b/test/Transforms/SLPVectorizer/X86/cycle_dup.ll
@@ -23,15 +23,15 @@ target triple = "x86_64-apple-macosx10.9.0"
 ;CHECK-NEXT:ret i32 undef
 define i32 @foo(i32* nocapture %A) #0 {
 entry:
-  %0 = load i32* %A, align 4
-  %arrayidx1 = getelementptr inbounds i32* %A, i64 1
-  %1 = load i32* %arrayidx1, align 4
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 2
-  %2 = load i32* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds i32* %A, i64 3
-  %3 = load i32* %arrayidx3, align 4
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 13
-  %4 = load i32* %arrayidx4, align 4
+  %0 = load i32, i32* %A, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %A, i64 1
+  %1 = load i32, i32* %arrayidx1, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 2
+  %2 = load i32, i32* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %A, i64 3
+  %3 = load i32, i32* %arrayidx3, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 13
+  %4 = load i32, i32* %arrayidx4, align 4
   %cmp24 = icmp sgt i32 %4, 0
   br i1 %cmp24, label %for.body, label %for.end
 
diff --git a/test/Transforms/SLPVectorizer/X86/debug_info.ll b/test/Transforms/SLPVectorizer/X86/debug_info.ll
index 21f51d7c6125..1d349fbc98b5 100644
--- a/test/Transforms/SLPVectorizer/X86/debug_info.ll
+++ b/test/Transforms/SLPVectorizer/X86/debug_info.ll
@@ -15,35 +15,35 @@ target triple = "x86_64-apple-macosx10.7.0"
 ;CHECK: @depth
 ;CHECK: getelementptr inbounds {{.*}}, !dbg ![[LOC:[0-9]+]]
 ;CHECK: bitcast double* {{.*}}, !dbg ![[LOC]]
-;CHECK: load <2 x double>* {{.*}}, !dbg ![[LOC]]
+;CHECK: load <2 x double>, <2 x double>* {{.*}}, !dbg ![[LOC]]
 ;CHECK: store <2 x double> {{.*}}, !dbg ![[LOC2:[0-9]+]]
 ;CHECK: ret
-;CHECK: ![[LOC]] = !MDLocation(line: 4, scope:
-;CHECK: ![[LOC2]] = !MDLocation(line: 7, scope:
+;CHECK: ![[LOC]] = !DILocation(line: 4, scope:
+;CHECK: ![[LOC2]] = !DILocation(line: 7, scope:
 
 define i32 @depth(double* nocapture %A, i32 %m) #0 {
 entry:
-  tail call void @llvm.dbg.value(metadata double* %A, i64 0, metadata !12, metadata !{}), !dbg !19
-  tail call void @llvm.dbg.value(metadata i32 %m, i64 0, metadata !13, metadata !{}), !dbg !19
-  tail call void @llvm.dbg.value(metadata i32 00, i64 0, metadata !14, metadata !{}), !dbg !21
-  tail call void @llvm.dbg.value(metadata i32 02, i64 0, metadata !15, metadata !{}), !dbg !21
-  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !16, metadata !{}), !dbg !23
+  tail call void @llvm.dbg.value(metadata double* %A, i64 0, metadata !12, metadata !DIExpression()), !dbg !19
+  tail call void @llvm.dbg.value(metadata i32 %m, i64 0, metadata !13, metadata !DIExpression()), !dbg !19
+  tail call void @llvm.dbg.value(metadata i32 00, i64 0, metadata !14, metadata !DIExpression()), !dbg !21
+  tail call void @llvm.dbg.value(metadata i32 02, i64 0, metadata !15, metadata !DIExpression()), !dbg !21
+  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !16, metadata !DIExpression()), !dbg !23
   %cmp8 = icmp sgt i32 %m, 0, !dbg !23
   br i1 %cmp8, label %for.body.lr.ph, label %for.end, !dbg !23
 
 for.body.lr.ph:                                   ; preds = %entry
-  %arrayidx = getelementptr inbounds double* %A, i64 4, !dbg !24
-  %0 = load double* %arrayidx, align 8, !dbg !24
-  %arrayidx1 = getelementptr inbounds double* %A, i64 5, !dbg !29
-  %1 = load double* %arrayidx1, align 8, !dbg !29
+  %arrayidx = getelementptr inbounds double, double* %A, i64 4, !dbg !24
+  %0 = load double, double* %arrayidx, align 8, !dbg !24
+  %arrayidx1 = getelementptr inbounds double, double* %A, i64 5, !dbg !29
+  %1 = load double, double* %arrayidx1, align 8, !dbg !29
   br label %for.end, !dbg !23
 
 for.end:                                          ; preds = %for.body.lr.ph, %entry
   %y1.0.lcssa = phi double [ %1, %for.body.lr.ph ], [ 1.000000e+00, %entry ]
   %y0.0.lcssa = phi double [ %0, %for.body.lr.ph ], [ 0.000000e+00, %entry ]
-  %arrayidx2 = getelementptr inbounds double* %A, i64 8, !dbg !30
+  %arrayidx2 = getelementptr inbounds double, double* %A, i64 8, !dbg !30
   store double %y0.0.lcssa, double* %arrayidx2, align 8, !dbg !30
-  %arrayidx3 = getelementptr inbounds double* %A, i64 9, !dbg !30
+  %arrayidx3 = getelementptr inbounds double, double* %A, i64 9, !dbg !30
   store double %y1.0.lcssa, double* %arrayidx3, align 8, !dbg !30
   ret i32 undef, !dbg !31
 }
@@ -57,33 +57,33 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!18, !32}
 
-!0 = !{!"0x11\0012\00clang version 3.4 (trunk 187335) (llvm/trunk 187335:187340M)\001\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/Users/nadav/file.c] [DW_LANG_C99]
-!1 = !{!"file.c", !"/Users/nadav"}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 187335) (llvm/trunk 187335:187340M)", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "file.c", directory: "/Users/nadav")
+!2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00depth\00depth\00\001\000\001\000\006\00256\001\001", !1, !5, !6, null, i32 (double*, i32)* @depth, null, null, !11} ; [ DW_TAG_subprogram ] [line 1] [def] [depth]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/Users/nadav/file.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "depth", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 (double*, i32)* @depth, variables: !11)
+!5 = !DIFile(filename: "file.c", directory: "/Users/nadav")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !9, !8}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0xf\00\000\0064\0064\000\000", null, null, !10} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from double]
-!10 = !{!"0x24\00double\000\0064\0064\000\000\004", null, null} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !10)
+!10 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 64, encoding: DW_ATE_float)
 !11 = !{!12, !13, !14, !15, !16}
-!12 = !{!"0x101\00A\0016777217\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [A] [line 1]
-!13 = !{!"0x101\00m\0033554433\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [m] [line 1]
-!14 = !{!"0x100\00y0\002\000", !4, !5, !10} ; [ DW_TAG_auto_variable ] [y0] [line 2]
-!15 = !{!"0x100\00y1\002\000", !4, !5, !10} ; [ DW_TAG_auto_variable ] [y1] [line 2]
-!16 = !{!"0x100\00i\003\000", !17, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 3]
-!17 = !{!"0xb\003\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/Users/nadav/file.c]
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "A", line: 1, arg: 1, scope: !4, file: !5, type: !9)
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "m", line: 1, arg: 2, scope: !4, file: !5, type: !8)
+!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y0", line: 2, scope: !4, file: !5, type: !10)
+!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y1", line: 2, scope: !4, file: !5, type: !10)
+!16 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 3, scope: !17, file: !5, type: !8)
+!17 = distinct !DILexicalBlock(line: 3, column: 0, file: !1, scope: !4)
 !18 = !{i32 2, !"Dwarf Version", i32 2}
-!19 = !MDLocation(line: 1, scope: !4)
+!19 = !DILocation(line: 1, scope: !4)
 !20 = !{double 0.000000e+00}
-!21 = !MDLocation(line: 2, scope: !4)
+!21 = !DILocation(line: 2, scope: !4)
 !22 = !{double 1.000000e+00}
-!23 = !MDLocation(line: 3, scope: !17)
-!24 = !MDLocation(line: 4, scope: !25)
-!25 = !{!"0xb\003\000\001", !1, !17} ; [ DW_TAG_lexical_block ] [/Users/nadav/file.c]
-!29 = !MDLocation(line: 5, scope: !25)
-!30 = !MDLocation(line: 7, scope: !4)
-!31 = !MDLocation(line: 8, scope: !4)
-!32 = !{i32 1, !"Debug Info Version", i32 2}
+!23 = !DILocation(line: 3, scope: !17)
+!24 = !DILocation(line: 4, scope: !25)
+!25 = distinct !DILexicalBlock(line: 3, column: 0, file: !1, scope: !17)
+!29 = !DILocation(line: 5, scope: !25)
+!30 = !DILocation(line: 7, scope: !4)
+!31 = !DILocation(line: 8, scope: !4)
+!32 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/SLPVectorizer/X86/diamond.ll b/test/Transforms/SLPVectorizer/X86/diamond.ll
index 5135a92a7bdb..4e2c02f6965a 100644
--- a/test/Transforms/SLPVectorizer/X86/diamond.ll
+++ b/test/Transforms/SLPVectorizer/X86/diamond.ll
@@ -18,24 +18,24 @@ target triple = "x86_64-apple-macosx10.8.0"
 ; CHECK: ret
 define i32 @foo(i32* noalias nocapture %B, i32* noalias nocapture %A, i32 %n, i32 %m) #0 {
 entry:
-  %0 = load i32* %A, align 4
+  %0 = load i32, i32* %A, align 4
   %mul238 = add i32 %m, %n
   %add = mul i32 %0, %mul238
   store i32 %add, i32* %B, align 4
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 1
-  %1 = load i32* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 1
+  %1 = load i32, i32* %arrayidx4, align 4
   %add8 = mul i32 %1, %mul238
-  %arrayidx9 = getelementptr inbounds i32* %B, i64 1
+  %arrayidx9 = getelementptr inbounds i32, i32* %B, i64 1
   store i32 %add8, i32* %arrayidx9, align 4
-  %arrayidx10 = getelementptr inbounds i32* %A, i64 2
-  %2 = load i32* %arrayidx10, align 4
+  %arrayidx10 = getelementptr inbounds i32, i32* %A, i64 2
+  %2 = load i32, i32* %arrayidx10, align 4
   %add14 = mul i32 %2, %mul238
-  %arrayidx15 = getelementptr inbounds i32* %B, i64 2
+  %arrayidx15 = getelementptr inbounds i32, i32* %B, i64 2
   store i32 %add14, i32* %arrayidx15, align 4
-  %arrayidx16 = getelementptr inbounds i32* %A, i64 3
-  %3 = load i32* %arrayidx16, align 4
+  %arrayidx16 = getelementptr inbounds i32, i32* %A, i64 3
+  %3 = load i32, i32* %arrayidx16, align 4
   %add20 = mul i32 %3, %mul238
-  %arrayidx21 = getelementptr inbounds i32* %B, i64 3
+  %arrayidx21 = getelementptr inbounds i32, i32* %B, i64 3
   store i32 %add20, i32* %arrayidx21, align 4
   ret i32 0
 }
@@ -56,24 +56,24 @@ entry:
 ; CHECK-NEXT: ret
 define i32 @extr_user(i32* noalias nocapture %B, i32* noalias nocapture %A, i32 %n, i32 %m) {
 entry:
-  %0 = load i32* %A, align 4
+  %0 = load i32, i32* %A, align 4
   %mul238 = add i32 %m, %n
   %add = mul i32 %0, %mul238
   store i32 %add, i32* %B, align 4
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 1
-  %1 = load i32* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 1
+  %1 = load i32, i32* %arrayidx4, align 4
   %add8 = mul i32 %1, %mul238
-  %arrayidx9 = getelementptr inbounds i32* %B, i64 1
+  %arrayidx9 = getelementptr inbounds i32, i32* %B, i64 1
   store i32 %add8, i32* %arrayidx9, align 4
-  %arrayidx10 = getelementptr inbounds i32* %A, i64 2
-  %2 = load i32* %arrayidx10, align 4
+  %arrayidx10 = getelementptr inbounds i32, i32* %A, i64 2
+  %2 = load i32, i32* %arrayidx10, align 4
   %add14 = mul i32 %2, %mul238
-  %arrayidx15 = getelementptr inbounds i32* %B, i64 2
+  %arrayidx15 = getelementptr inbounds i32, i32* %B, i64 2
   store i32 %add14, i32* %arrayidx15, align 4
-  %arrayidx16 = getelementptr inbounds i32* %A, i64 3
-  %3 = load i32* %arrayidx16, align 4
+  %arrayidx16 = getelementptr inbounds i32, i32* %A, i64 3
+  %3 = load i32, i32* %arrayidx16, align 4
   %add20 = mul i32 %3, %mul238
-  %arrayidx21 = getelementptr inbounds i32* %B, i64 3
+  %arrayidx21 = getelementptr inbounds i32, i32* %B, i64 3
   store i32 %add20, i32* %arrayidx21, align 4
   ret i32 %0  ;<--------- This value has multiple users
 }
@@ -86,24 +86,24 @@ entry:
 ; CHECK-NEXT: ret
 define i32 @extr_user1(i32* noalias nocapture %B, i32* noalias nocapture %A, i32 %n, i32 %m) {
 entry:
-  %0 = load i32* %A, align 4
+  %0 = load i32, i32* %A, align 4
   %mul238 = add i32 %m, %n
   %add = mul i32 %0, %mul238
   store i32 %add, i32* %B, align 4
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 1
-  %1 = load i32* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 1
+  %1 = load i32, i32* %arrayidx4, align 4
   %add8 = mul i32 %1, %mul238
-  %arrayidx9 = getelementptr inbounds i32* %B, i64 1
+  %arrayidx9 = getelementptr inbounds i32, i32* %B, i64 1
   store i32 %add8, i32* %arrayidx9, align 4
-  %arrayidx10 = getelementptr inbounds i32* %A, i64 2
-  %2 = load i32* %arrayidx10, align 4
+  %arrayidx10 = getelementptr inbounds i32, i32* %A, i64 2
+  %2 = load i32, i32* %arrayidx10, align 4
   %add14 = mul i32 %2, %mul238
-  %arrayidx15 = getelementptr inbounds i32* %B, i64 2
+  %arrayidx15 = getelementptr inbounds i32, i32* %B, i64 2
   store i32 %add14, i32* %arrayidx15, align 4
-  %arrayidx16 = getelementptr inbounds i32* %A, i64 3
-  %3 = load i32* %arrayidx16, align 4
+  %arrayidx16 = getelementptr inbounds i32, i32* %A, i64 3
+  %3 = load i32, i32* %arrayidx16, align 4
   %add20 = mul i32 %3, %mul238
-  %arrayidx21 = getelementptr inbounds i32* %B, i64 3
+  %arrayidx21 = getelementptr inbounds i32, i32* %B, i64 3
   store i32 %add20, i32* %arrayidx21, align 4
   ret i32 %1  ;<--------- This value has multiple users
 }
diff --git a/test/Transforms/SLPVectorizer/X86/external_user.ll b/test/Transforms/SLPVectorizer/X86/external_user.ll
index 6d09aa61bf35..bf2febda86b4 100644
--- a/test/Transforms/SLPVectorizer/X86/external_user.ll
+++ b/test/Transforms/SLPVectorizer/X86/external_user.ll
@@ -33,9 +33,9 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 define double @ext_user(double* noalias nocapture %B, double* noalias nocapture %A, i32 %n, i32 %m) {
 entry:
-  %arrayidx = getelementptr inbounds double* %A, i64 1
-  %0 = load double* %arrayidx, align 8
-  %1 = load double* %A, align 8
+  %arrayidx = getelementptr inbounds double, double* %A, i64 1
+  %0 = load double, double* %arrayidx, align 8
+  %1 = load double, double* %A, align 8
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
@@ -54,7 +54,7 @@ for.body:                                         ; preds = %for.body, %entry
 
 for.end:                                          ; preds = %for.body
   store double %add5, double* %B, align 8
-  %arrayidx7 = getelementptr inbounds double* %B, i64 1
+  %arrayidx7 = getelementptr inbounds double, double* %B, i64 1
   store double %add4, double* %arrayidx7, align 8
   ret double %mul3
 }
@@ -69,9 +69,9 @@ for.end:                                          ; preds = %for.body
 define i32 @needtogather(double *noalias %a, i32 *noalias %b,  float * noalias %c,
                 i32 * noalias %d) {
 entry:
-  %0 = load i32* %d, align 4
+  %0 = load i32, i32* %d, align 4
   %conv = sitofp i32 %0 to float
-  %1 = load float* %c
+  %1 = load float, float* %c
   %sub = fsub float 0.000000e+00, %1
   %mul = fmul float %sub, 0.000000e+00
   %add = fadd float %conv, %mul
diff --git a/test/Transforms/SLPVectorizer/X86/extract.ll b/test/Transforms/SLPVectorizer/X86/extract.ll
index f611fd4ec24f..9a6ee2afc8eb 100644
--- a/test/Transforms/SLPVectorizer/X86/extract.ll
+++ b/test/Transforms/SLPVectorizer/X86/extract.ll
@@ -9,11 +9,11 @@ target triple = "x86_64-apple-macosx10.8.0"
 ;CHECK: ret void
 define void @fextr(double* %ptr) {
 entry:
-  %LD = load <2 x double>* undef
+  %LD = load <2 x double>, <2 x double>* undef
   %V0 = extractelement <2 x double> %LD, i32 0
   %V1 = extractelement <2 x double> %LD, i32 1
-  %P0 = getelementptr inbounds double* %ptr, i64 0
-  %P1 = getelementptr inbounds double* %ptr, i64 1
+  %P0 = getelementptr inbounds double, double* %ptr, i64 0
+  %P1 = getelementptr inbounds double, double* %ptr, i64 1
   %A0 = fadd double %V0, 0.0
   %A1 = fadd double %V1, 1.1
   store double %A0, double* %P0, align 4
@@ -27,11 +27,11 @@ entry:
 ;CHECK: ret void
 define void @fextr1(double* %ptr) {
 entry:
-  %LD = load <2 x double>* undef
+  %LD = load <2 x double>, <2 x double>* undef
   %V0 = extractelement <2 x double> %LD, i32 0
   %V1 = extractelement <2 x double> %LD, i32 1
-  %P0 = getelementptr inbounds double* %ptr, i64 1  ; <--- incorrect order
-  %P1 = getelementptr inbounds double* %ptr, i64 0
+  %P0 = getelementptr inbounds double, double* %ptr, i64 1  ; <--- incorrect order
+  %P1 = getelementptr inbounds double, double* %ptr, i64 0
   %A0 = fadd double %V0, 1.2
   %A1 = fadd double %V1, 3.4
   store double %A0, double* %P0, align 4
@@ -45,11 +45,11 @@ entry:
 ;CHECK: ret void
 define void @fextr2(double* %ptr) {
 entry:
-  %LD = load <4 x double>* undef
+  %LD = load <4 x double>, <4 x double>* undef
   %V0 = extractelement <4 x double> %LD, i32 0  ; <--- invalid size.
   %V1 = extractelement <4 x double> %LD, i32 1
-  %P0 = getelementptr inbounds double* %ptr, i64 0
-  %P1 = getelementptr inbounds double* %ptr, i64 1
+  %P0 = getelementptr inbounds double, double* %ptr, i64 0
+  %P1 = getelementptr inbounds double, double* %ptr, i64 1
   %A0 = fadd double %V0, 5.5
   %A1 = fadd double %V1, 6.6
   store double %A0, double* %P0, align 4
diff --git a/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll b/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll
index 3628042cdb4d..6e5415b3c701 100644
--- a/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll
+++ b/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll
@@ -7,13 +7,13 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 ; Function Attrs: nounwind ssp uwtable
 define i32 @fn1() {
 entry:
-  %0 = load i64** @a, align 8
-  %add.ptr = getelementptr inbounds i64* %0, i64 11
+  %0 = load i64*, i64** @a, align 8
+  %add.ptr = getelementptr inbounds i64, i64* %0, i64 11
   %1 = ptrtoint i64* %add.ptr to i64
   store i64 %1, i64* %add.ptr, align 8
-  %add.ptr1 = getelementptr inbounds i64* %0, i64 56
+  %add.ptr1 = getelementptr inbounds i64, i64* %0, i64 56
   %2 = ptrtoint i64* %add.ptr1 to i64
-  %arrayidx2 = getelementptr inbounds i64* %0, i64 12
+  %arrayidx2 = getelementptr inbounds i64, i64* %0, i64 12
   store i64 %2, i64* %arrayidx2, align 8
   ret i32 undef
 ; CHECK-LABEL: @fn1(
@@ -25,42 +25,42 @@ entry:
 declare float @llvm.powi.f32(float, i32)
 define void @fn2(i32* %a, i32* %b, float* %c) {
 entry:
-  %i0 = load i32* %a, align 4
-  %i1 = load i32* %b, align 4
+  %i0 = load i32, i32* %a, align 4
+  %i1 = load i32, i32* %b, align 4
   %add1 = add i32 %i0, %i1
   %fp1 = sitofp i32 %add1 to float
   %call1 = tail call float @llvm.powi.f32(float %fp1,i32 %add1) nounwind readnone
 
-  %arrayidx2 = getelementptr inbounds i32* %a, i32 1
-  %i2 = load i32* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i32 1
-  %i3 = load i32* %arrayidx3, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 1
+  %i2 = load i32, i32* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i32 1
+  %i3 = load i32, i32* %arrayidx3, align 4
   %add2 = add i32 %i2, %i3
   %fp2 = sitofp i32 %add2 to float
   %call2 = tail call float @llvm.powi.f32(float %fp2,i32 %add1) nounwind readnone
 
-  %arrayidx4 = getelementptr inbounds i32* %a, i32 2
-  %i4 = load i32* %arrayidx4, align 4
-  %arrayidx5 = getelementptr inbounds i32* %b, i32 2
-  %i5 = load i32* %arrayidx5, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %a, i32 2
+  %i4 = load i32, i32* %arrayidx4, align 4
+  %arrayidx5 = getelementptr inbounds i32, i32* %b, i32 2
+  %i5 = load i32, i32* %arrayidx5, align 4
   %add3 = add i32 %i4, %i5
   %fp3 = sitofp i32 %add3 to float
   %call3 = tail call float @llvm.powi.f32(float %fp3,i32 %add1) nounwind readnone
 
-  %arrayidx6 = getelementptr inbounds i32* %a, i32 3
-  %i6 = load i32* %arrayidx6, align 4
-  %arrayidx7 = getelementptr inbounds i32* %b, i32 3
-  %i7 = load i32* %arrayidx7, align 4
+  %arrayidx6 = getelementptr inbounds i32, i32* %a, i32 3
+  %i6 = load i32, i32* %arrayidx6, align 4
+  %arrayidx7 = getelementptr inbounds i32, i32* %b, i32 3
+  %i7 = load i32, i32* %arrayidx7, align 4
   %add4 = add i32 %i6, %i7
   %fp4 = sitofp i32 %add4 to float
   %call4 = tail call float @llvm.powi.f32(float %fp4,i32 %add1) nounwind readnone
 
   store float %call1, float* %c, align 4
-  %arrayidx8 = getelementptr inbounds float* %c, i32 1
+  %arrayidx8 = getelementptr inbounds float, float* %c, i32 1
   store float %call2, float* %arrayidx8, align 4
-  %arrayidx9 = getelementptr inbounds float* %c, i32 2
+  %arrayidx9 = getelementptr inbounds float, float* %c, i32 2
   store float %call3, float* %arrayidx9, align 4
-  %arrayidx10 = getelementptr inbounds float* %c, i32 3
+  %arrayidx10 = getelementptr inbounds float, float* %c, i32 3
   store float %call4, float* %arrayidx10, align 4
   ret void
 
diff --git a/test/Transforms/SLPVectorizer/X86/extractcost.ll b/test/Transforms/SLPVectorizer/X86/extractcost.ll
index 01baf66e2f95..164ddf38c192 100644
--- a/test/Transforms/SLPVectorizer/X86/extractcost.ll
+++ b/test/Transforms/SLPVectorizer/X86/extractcost.ll
@@ -13,15 +13,15 @@ entry:
   store i32 %add, i32* %A, align 4
   %mul1 = mul nsw i32 %n, 9
   %add2 = add nsw i32 %mul1, 9
-  %arrayidx3 = getelementptr inbounds i32* %A, i64 1
+  %arrayidx3 = getelementptr inbounds i32, i32* %A, i64 1
   store i32 %add2, i32* %arrayidx3, align 4
   %mul4 = shl i32 %n, 3
   %add5 = add nsw i32 %mul4, 9
-  %arrayidx6 = getelementptr inbounds i32* %A, i64 2
+  %arrayidx6 = getelementptr inbounds i32, i32* %A, i64 2
   store i32 %add5, i32* %arrayidx6, align 4
   %mul7 = mul nsw i32 %n, 10
   %add8 = add nsw i32 %mul7, 9
-  %arrayidx9 = getelementptr inbounds i32* %A, i64 3
+  %arrayidx9 = getelementptr inbounds i32, i32* %A, i64 3
   store i32 %add8, i32* %arrayidx9, align 4
   %externaluse1 = add nsw i32 %add, %m  
   %externaluse2 = mul nsw i32 %add, %m  ; we should add the extract cost only once and the store will be vectorized
diff --git a/test/Transforms/SLPVectorizer/X86/flag.ll b/test/Transforms/SLPVectorizer/X86/flag.ll
index 3ca540706744..7db8d75c20a7 100644
--- a/test/Transforms/SLPVectorizer/X86/flag.ll
+++ b/test/Transforms/SLPVectorizer/X86/flag.ll
@@ -15,17 +15,17 @@ define i32 @rollable(i32* noalias nocapture %in, i32* noalias nocapture %out, i6
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %i.019 = phi i64 [ %26, %.lr.ph ], [ 0, %0 ]
   %2 = shl i64 %i.019, 2
-  %3 = getelementptr inbounds i32* %in, i64 %2
-  %4 = load i32* %3, align 4
+  %3 = getelementptr inbounds i32, i32* %in, i64 %2
+  %4 = load i32, i32* %3, align 4
   %5 = or i64 %2, 1
-  %6 = getelementptr inbounds i32* %in, i64 %5
-  %7 = load i32* %6, align 4
+  %6 = getelementptr inbounds i32, i32* %in, i64 %5
+  %7 = load i32, i32* %6, align 4
   %8 = or i64 %2, 2
-  %9 = getelementptr inbounds i32* %in, i64 %8
-  %10 = load i32* %9, align 4
+  %9 = getelementptr inbounds i32, i32* %in, i64 %8
+  %10 = load i32, i32* %9, align 4
   %11 = or i64 %2, 3
-  %12 = getelementptr inbounds i32* %in, i64 %11
-  %13 = load i32* %12, align 4
+  %12 = getelementptr inbounds i32, i32* %in, i64 %11
+  %13 = load i32, i32* %12, align 4
   %14 = mul i32 %4, 7
   %15 = add i32 %14, 7
   %16 = mul i32 %7, 7
@@ -34,13 +34,13 @@ define i32 @rollable(i32* noalias nocapture %in, i32* noalias nocapture %out, i6
   %19 = add i32 %18, 21
   %20 = mul i32 %13, 7
   %21 = add i32 %20, 28
-  %22 = getelementptr inbounds i32* %out, i64 %2
+  %22 = getelementptr inbounds i32, i32* %out, i64 %2
   store i32 %15, i32* %22, align 4
-  %23 = getelementptr inbounds i32* %out, i64 %5
+  %23 = getelementptr inbounds i32, i32* %out, i64 %5
   store i32 %17, i32* %23, align 4
-  %24 = getelementptr inbounds i32* %out, i64 %8
+  %24 = getelementptr inbounds i32, i32* %out, i64 %8
   store i32 %19, i32* %24, align 4
-  %25 = getelementptr inbounds i32* %out, i64 %11
+  %25 = getelementptr inbounds i32, i32* %out, i64 %11
   store i32 %21, i32* %25, align 4
   %26 = add i64 %i.019, 1
   %exitcond = icmp eq i64 %26, %n
diff --git a/test/Transforms/SLPVectorizer/X86/gep.ll b/test/Transforms/SLPVectorizer/X86/gep.ll
index 9e105ec98489..3f952d7b242b 100644
--- a/test/Transforms/SLPVectorizer/X86/gep.ll
+++ b/test/Transforms/SLPVectorizer/X86/gep.ll
@@ -9,15 +9,15 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 ; CHECK-LABEL: foo1
 ; CHECK: <2 x i32*>
 define void @foo1 ({ i32*, i32* }* noalias %x, { i32*, i32* }* noalias %y) {
-  %1 = getelementptr inbounds { i32*, i32* }* %y, i64 0, i32 0
-  %2 = load i32** %1, align 8
-  %3 = getelementptr inbounds i32* %2, i64 16
-  %4 = getelementptr inbounds { i32*, i32* }* %x, i64 0, i32 0
+  %1 = getelementptr inbounds { i32*, i32* }, { i32*, i32* }* %y, i64 0, i32 0
+  %2 = load i32*, i32** %1, align 8
+  %3 = getelementptr inbounds i32, i32* %2, i64 16
+  %4 = getelementptr inbounds { i32*, i32* }, { i32*, i32* }* %x, i64 0, i32 0
   store i32* %3, i32** %4, align 8
-  %5 = getelementptr inbounds { i32*, i32* }* %y, i64 0, i32 1
-  %6 = load i32** %5, align 8
-  %7 = getelementptr inbounds i32* %6, i64 16
-  %8 = getelementptr inbounds { i32*, i32* }* %x, i64 0, i32 1
+  %5 = getelementptr inbounds { i32*, i32* }, { i32*, i32* }* %y, i64 0, i32 1
+  %6 = load i32*, i32** %5, align 8
+  %7 = getelementptr inbounds i32, i32* %6, i64 16
+  %8 = getelementptr inbounds { i32*, i32* }, { i32*, i32* }* %x, i64 0, i32 1
   store i32* %7, i32** %8, align 8
   ret void
 }
@@ -27,15 +27,15 @@ define void @foo1 ({ i32*, i32* }* noalias %x, { i32*, i32* }* noalias %y) {
 ; CHECK-LABEL: foo2
 ; CHECK-NOT: <2 x i32*>
 define void @foo2 ({ i32*, i32* }* noalias %x, { i32*, i32* }* noalias %y, i32 %i) {
-  %1 = getelementptr inbounds { i32*, i32* }* %y, i64 0, i32 0
-  %2 = load i32** %1, align 8
-  %3 = getelementptr inbounds i32* %2, i32 %i
-  %4 = getelementptr inbounds { i32*, i32* }* %x, i64 0, i32 0
+  %1 = getelementptr inbounds { i32*, i32* }, { i32*, i32* }* %y, i64 0, i32 0
+  %2 = load i32*, i32** %1, align 8
+  %3 = getelementptr inbounds i32, i32* %2, i32 %i
+  %4 = getelementptr inbounds { i32*, i32* }, { i32*, i32* }* %x, i64 0, i32 0
   store i32* %3, i32** %4, align 8
-  %5 = getelementptr inbounds { i32*, i32* }* %y, i64 0, i32 1
-  %6 = load i32** %5, align 8
-  %7 = getelementptr inbounds i32* %6, i32 %i
-  %8 = getelementptr inbounds { i32*, i32* }* %x, i64 0, i32 1
+  %5 = getelementptr inbounds { i32*, i32* }, { i32*, i32* }* %y, i64 0, i32 1
+  %6 = load i32*, i32** %5, align 8
+  %7 = getelementptr inbounds i32, i32* %6, i32 %i
+  %8 = getelementptr inbounds { i32*, i32* }, { i32*, i32* }* %x, i64 0, i32 1
   store i32* %7, i32** %8, align 8
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/X86/hoist.ll b/test/Transforms/SLPVectorizer/X86/hoist.ll
index 78c58f1d84e9..36c939b597e0 100644
--- a/test/Transforms/SLPVectorizer/X86/hoist.ll
+++ b/test/Transforms/SLPVectorizer/X86/hoist.ll
@@ -30,23 +30,23 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %i.024 = phi i32 [ 0, %entry ], [ %add10, %for.body ]
-  %arrayidx = getelementptr inbounds i32* %A, i32 %i.024
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i32 %i.024
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %n
   store i32 %add, i32* %arrayidx, align 4
   %add121 = or i32 %i.024, 1
-  %arrayidx2 = getelementptr inbounds i32* %A, i32 %add121
-  %1 = load i32* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i32 %add121
+  %1 = load i32, i32* %arrayidx2, align 4
   %add3 = add nsw i32 %1, %k
   store i32 %add3, i32* %arrayidx2, align 4
   %add422 = or i32 %i.024, 2
-  %arrayidx5 = getelementptr inbounds i32* %A, i32 %add422
-  %2 = load i32* %arrayidx5, align 4
+  %arrayidx5 = getelementptr inbounds i32, i32* %A, i32 %add422
+  %2 = load i32, i32* %arrayidx5, align 4
   %add6 = add nsw i32 %2, %n
   store i32 %add6, i32* %arrayidx5, align 4
   %add723 = or i32 %i.024, 3
-  %arrayidx8 = getelementptr inbounds i32* %A, i32 %add723
-  %3 = load i32* %arrayidx8, align 4
+  %arrayidx8 = getelementptr inbounds i32, i32* %A, i32 %add723
+  %3 = load i32, i32* %arrayidx8, align 4
   %add9 = add nsw i32 %3, %k
   store i32 %add9, i32* %arrayidx8, align 4
   %add10 = add nsw i32 %i.024, 4
diff --git a/test/Transforms/SLPVectorizer/X86/horizontal.ll b/test/Transforms/SLPVectorizer/X86/horizontal.ll
index 18360471c190..83b2e01f04e0 100644
--- a/test/Transforms/SLPVectorizer/X86/horizontal.ll
+++ b/test/Transforms/SLPVectorizer/X86/horizontal.ll
@@ -32,22 +32,22 @@ for.body:
   %i.033 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %sum.032 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add17, %for.body ]
   %mul = shl nsw i64 %i.033, 2
-  %arrayidx = getelementptr inbounds float* %A, i64 %mul
-  %1 = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds float, float* %A, i64 %mul
+  %1 = load float, float* %arrayidx, align 4
   %mul2 = fmul float %1, 7.000000e+00
   %add28 = or i64 %mul, 1
-  %arrayidx4 = getelementptr inbounds float* %A, i64 %add28
-  %2 = load float* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds float, float* %A, i64 %add28
+  %2 = load float, float* %arrayidx4, align 4
   %mul5 = fmul float %2, 7.000000e+00
   %add6 = fadd fast float %mul2, %mul5
   %add829 = or i64 %mul, 2
-  %arrayidx9 = getelementptr inbounds float* %A, i64 %add829
-  %3 = load float* %arrayidx9, align 4
+  %arrayidx9 = getelementptr inbounds float, float* %A, i64 %add829
+  %3 = load float, float* %arrayidx9, align 4
   %mul10 = fmul float %3, 7.000000e+00
   %add11 = fadd fast float %add6, %mul10
   %add1330 = or i64 %mul, 3
-  %arrayidx14 = getelementptr inbounds float* %A, i64 %add1330
-  %4 = load float* %arrayidx14, align 4
+  %arrayidx14 = getelementptr inbounds float, float* %A, i64 %add1330
+  %4 = load float, float* %arrayidx14, align 4
   %mul15 = fmul float %4, 7.000000e+00
   %add16 = fadd fast float %add11, %mul15
   %add17 = fadd fast float %sum.032, %add16
@@ -85,13 +85,13 @@ entry:
   br i1 %cmp38, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:
-  %0 = load float* %B, align 4
-  %arrayidx4 = getelementptr inbounds float* %B, i64 1
-  %1 = load float* %arrayidx4, align 4
-  %arrayidx9 = getelementptr inbounds float* %B, i64 2
-  %2 = load float* %arrayidx9, align 4
-  %arrayidx15 = getelementptr inbounds float* %B, i64 3
-  %3 = load float* %arrayidx15, align 4
+  %0 = load float, float* %B, align 4
+  %arrayidx4 = getelementptr inbounds float, float* %B, i64 1
+  %1 = load float, float* %arrayidx4, align 4
+  %arrayidx9 = getelementptr inbounds float, float* %B, i64 2
+  %2 = load float, float* %arrayidx9, align 4
+  %arrayidx15 = getelementptr inbounds float, float* %B, i64 3
+  %3 = load float, float* %arrayidx15, align 4
   %4 = sext i32 %n to i64
   br label %for.body
 
@@ -99,22 +99,22 @@ for.body:
   %i.040 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %sum.039 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %mul21, %for.body ]
   %mul = shl nsw i64 %i.040, 2
-  %arrayidx2 = getelementptr inbounds float* %A, i64 %mul
-  %5 = load float* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %A, i64 %mul
+  %5 = load float, float* %arrayidx2, align 4
   %mul3 = fmul float %0, %5
   %add35 = or i64 %mul, 1
-  %arrayidx6 = getelementptr inbounds float* %A, i64 %add35
-  %6 = load float* %arrayidx6, align 4
+  %arrayidx6 = getelementptr inbounds float, float* %A, i64 %add35
+  %6 = load float, float* %arrayidx6, align 4
   %mul7 = fmul float %1, %6
   %add8 = fadd fast float %mul3, %mul7
   %add1136 = or i64 %mul, 2
-  %arrayidx12 = getelementptr inbounds float* %A, i64 %add1136
-  %7 = load float* %arrayidx12, align 4
+  %arrayidx12 = getelementptr inbounds float, float* %A, i64 %add1136
+  %7 = load float, float* %arrayidx12, align 4
   %mul13 = fmul float %2, %7
   %add14 = fadd fast float %add8, %mul13
   %add1737 = or i64 %mul, 3
-  %arrayidx18 = getelementptr inbounds float* %A, i64 %add1737
-  %8 = load float* %arrayidx18, align 4
+  %arrayidx18 = getelementptr inbounds float, float* %A, i64 %add1737
+  %8 = load float, float* %arrayidx18, align 4
   %mul19 = fmul float %3, %8
   %add20 = fadd fast float %add14, %mul19
   %mul21 = fmul float %sum.039, %add20
@@ -157,23 +157,23 @@ entry:
   br i1 %cmp81, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:
-  %0 = load float* %B, align 4
-  %arrayidx4 = getelementptr inbounds float* %B, i64 1
-  %1 = load float* %arrayidx4, align 4
-  %arrayidx9 = getelementptr inbounds float* %B, i64 2
-  %2 = load float* %arrayidx9, align 4
-  %arrayidx15 = getelementptr inbounds float* %B, i64 3
-  %3 = load float* %arrayidx15, align 4
-  %arrayidx21 = getelementptr inbounds float* %B, i64 4
-  %4 = load float* %arrayidx21, align 4
-  %arrayidx27 = getelementptr inbounds float* %B, i64 5
-  %5 = load float* %arrayidx27, align 4
-  %arrayidx33 = getelementptr inbounds float* %B, i64 6
-  %6 = load float* %arrayidx33, align 4
-  %arrayidx39 = getelementptr inbounds float* %B, i64 7
-  %7 = load float* %arrayidx39, align 4
-  %arrayidx45 = getelementptr inbounds float* %B, i64 8
-  %8 = load float* %arrayidx45, align 4
+  %0 = load float, float* %B, align 4
+  %arrayidx4 = getelementptr inbounds float, float* %B, i64 1
+  %1 = load float, float* %arrayidx4, align 4
+  %arrayidx9 = getelementptr inbounds float, float* %B, i64 2
+  %2 = load float, float* %arrayidx9, align 4
+  %arrayidx15 = getelementptr inbounds float, float* %B, i64 3
+  %3 = load float, float* %arrayidx15, align 4
+  %arrayidx21 = getelementptr inbounds float, float* %B, i64 4
+  %4 = load float, float* %arrayidx21, align 4
+  %arrayidx27 = getelementptr inbounds float, float* %B, i64 5
+  %5 = load float, float* %arrayidx27, align 4
+  %arrayidx33 = getelementptr inbounds float, float* %B, i64 6
+  %6 = load float, float* %arrayidx33, align 4
+  %arrayidx39 = getelementptr inbounds float, float* %B, i64 7
+  %7 = load float, float* %arrayidx39, align 4
+  %arrayidx45 = getelementptr inbounds float, float* %B, i64 8
+  %8 = load float, float* %arrayidx45, align 4
   %9 = sext i32 %n to i64
   br label %for.body
 
@@ -181,47 +181,47 @@ for.body:
   %i.083 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %sum.082 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add51, %for.body ]
   %mul = mul nsw i64 %i.083, 6
-  %arrayidx2 = getelementptr inbounds float* %A, i64 %mul
-  %10 = load float* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %A, i64 %mul
+  %10 = load float, float* %arrayidx2, align 4
   %mul3 = fmul fast float %0, %10
   %add80 = or i64 %mul, 1
-  %arrayidx6 = getelementptr inbounds float* %A, i64 %add80
-  %11 = load float* %arrayidx6, align 4
+  %arrayidx6 = getelementptr inbounds float, float* %A, i64 %add80
+  %11 = load float, float* %arrayidx6, align 4
   %mul7 = fmul fast float %1, %11
   %add8 = fadd fast float %mul3, %mul7
   %add11 = add nsw i64 %mul, 2
-  %arrayidx12 = getelementptr inbounds float* %A, i64 %add11
-  %12 = load float* %arrayidx12, align 4
+  %arrayidx12 = getelementptr inbounds float, float* %A, i64 %add11
+  %12 = load float, float* %arrayidx12, align 4
   %mul13 = fmul fast float %2, %12
   %add14 = fadd fast float %add8, %mul13
   %add17 = add nsw i64 %mul, 3
-  %arrayidx18 = getelementptr inbounds float* %A, i64 %add17
-  %13 = load float* %arrayidx18, align 4
+  %arrayidx18 = getelementptr inbounds float, float* %A, i64 %add17
+  %13 = load float, float* %arrayidx18, align 4
   %mul19 = fmul fast float %3, %13
   %add20 = fadd fast float %add14, %mul19
   %add23 = add nsw i64 %mul, 4
-  %arrayidx24 = getelementptr inbounds float* %A, i64 %add23
-  %14 = load float* %arrayidx24, align 4
+  %arrayidx24 = getelementptr inbounds float, float* %A, i64 %add23
+  %14 = load float, float* %arrayidx24, align 4
   %mul25 = fmul fast float %4, %14
   %add26 = fadd fast float %add20, %mul25
   %add29 = add nsw i64 %mul, 5
-  %arrayidx30 = getelementptr inbounds float* %A, i64 %add29
-  %15 = load float* %arrayidx30, align 4
+  %arrayidx30 = getelementptr inbounds float, float* %A, i64 %add29
+  %15 = load float, float* %arrayidx30, align 4
   %mul31 = fmul fast float %5, %15
   %add32 = fadd fast float %add26, %mul31
   %add35 = add nsw i64 %mul, 6
-  %arrayidx36 = getelementptr inbounds float* %A, i64 %add35
-  %16 = load float* %arrayidx36, align 4
+  %arrayidx36 = getelementptr inbounds float, float* %A, i64 %add35
+  %16 = load float, float* %arrayidx36, align 4
   %mul37 = fmul fast float %6, %16
   %add38 = fadd fast float %add32, %mul37
   %add41 = add nsw i64 %mul, 7
-  %arrayidx42 = getelementptr inbounds float* %A, i64 %add41
-  %17 = load float* %arrayidx42, align 4
+  %arrayidx42 = getelementptr inbounds float, float* %A, i64 %add41
+  %17 = load float, float* %arrayidx42, align 4
   %mul43 = fmul fast float %7, %17
   %add44 = fadd fast float %add38, %mul43
   %add47 = add nsw i64 %mul, 8
-  %arrayidx48 = getelementptr inbounds float* %A, i64 %add47
-  %18 = load float* %arrayidx48, align 4
+  %arrayidx48 = getelementptr inbounds float, float* %A, i64 %add47
+  %18 = load float, float* %arrayidx48, align 4
   %mul49 = fmul fast float %8, %18
   %add50 = fadd fast float %add44, %mul49
   %add51 = fadd fast float %sum.082, %add50
@@ -259,13 +259,13 @@ entry:
   br i1 %cmp41, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:
-  %0 = load float* %B, align 4
-  %arrayidx4 = getelementptr inbounds float* %B, i64 1
-  %1 = load float* %arrayidx4, align 4
-  %arrayidx10 = getelementptr inbounds float* %B, i64 2
-  %2 = load float* %arrayidx10, align 4
-  %arrayidx16 = getelementptr inbounds float* %B, i64 3
-  %3 = load float* %arrayidx16, align 4
+  %0 = load float, float* %B, align 4
+  %arrayidx4 = getelementptr inbounds float, float* %B, i64 1
+  %1 = load float, float* %arrayidx4, align 4
+  %arrayidx10 = getelementptr inbounds float, float* %B, i64 2
+  %2 = load float, float* %arrayidx10, align 4
+  %arrayidx16 = getelementptr inbounds float, float* %B, i64 3
+  %3 = load float, float* %arrayidx16, align 4
   %4 = sext i32 %n to i64
   br label %for.body
 
@@ -273,23 +273,23 @@ for.body:
   %i.043 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %sum.042 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add21, %for.body ]
   %mul = shl nsw i64 %i.043, 2
-  %arrayidx2 = getelementptr inbounds float* %A, i64 %mul
-  %5 = load float* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %A, i64 %mul
+  %5 = load float, float* %arrayidx2, align 4
   %mul3 = fmul fast float %0, %5
   %add = fadd fast float %sum.042, %mul3
   %add638 = or i64 %mul, 1
-  %arrayidx7 = getelementptr inbounds float* %A, i64 %add638
-  %6 = load float* %arrayidx7, align 4
+  %arrayidx7 = getelementptr inbounds float, float* %A, i64 %add638
+  %6 = load float, float* %arrayidx7, align 4
   %mul8 = fmul fast float %1, %6
   %add9 = fadd fast float %add, %mul8
   %add1239 = or i64 %mul, 2
-  %arrayidx13 = getelementptr inbounds float* %A, i64 %add1239
-  %7 = load float* %arrayidx13, align 4
+  %arrayidx13 = getelementptr inbounds float, float* %A, i64 %add1239
+  %7 = load float, float* %arrayidx13, align 4
   %mul14 = fmul fast float %2, %7
   %add15 = fadd fast float %add9, %mul14
   %add1840 = or i64 %mul, 3
-  %arrayidx19 = getelementptr inbounds float* %A, i64 %add1840
-  %8 = load float* %arrayidx19, align 4
+  %arrayidx19 = getelementptr inbounds float, float* %A, i64 %add1840
+  %8 = load float, float* %arrayidx19, align 4
   %mul20 = fmul fast float %3, %8
   %add21 = fadd fast float %add15, %mul20
   %inc = add nsw i64 %i.043, 1
@@ -326,40 +326,40 @@ entry:
   br i1 %cmp37, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:
-  %arrayidx4 = getelementptr inbounds float* %B, i64 1
-  %arrayidx9 = getelementptr inbounds float* %B, i64 2
-  %arrayidx15 = getelementptr inbounds float* %B, i64 3
+  %arrayidx4 = getelementptr inbounds float, float* %B, i64 1
+  %arrayidx9 = getelementptr inbounds float, float* %B, i64 2
+  %arrayidx15 = getelementptr inbounds float, float* %B, i64 3
   %0 = sext i32 %n to i64
   br label %for.body
 
 for.body:
   %i.039 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %C.addr.038 = phi float* [ %C, %for.body.lr.ph ], [ %incdec.ptr, %for.body ]
-  %1 = load float* %B, align 4
+  %1 = load float, float* %B, align 4
   %mul = shl nsw i64 %i.039, 2
-  %arrayidx2 = getelementptr inbounds float* %A, i64 %mul
-  %2 = load float* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %A, i64 %mul
+  %2 = load float, float* %arrayidx2, align 4
   %mul3 = fmul fast float %1, %2
-  %3 = load float* %arrayidx4, align 4
+  %3 = load float, float* %arrayidx4, align 4
   %add34 = or i64 %mul, 1
-  %arrayidx6 = getelementptr inbounds float* %A, i64 %add34
-  %4 = load float* %arrayidx6, align 4
+  %arrayidx6 = getelementptr inbounds float, float* %A, i64 %add34
+  %4 = load float, float* %arrayidx6, align 4
   %mul7 = fmul fast float %3, %4
   %add8 = fadd fast float %mul3, %mul7
-  %5 = load float* %arrayidx9, align 4
+  %5 = load float, float* %arrayidx9, align 4
   %add1135 = or i64 %mul, 2
-  %arrayidx12 = getelementptr inbounds float* %A, i64 %add1135
-  %6 = load float* %arrayidx12, align 4
+  %arrayidx12 = getelementptr inbounds float, float* %A, i64 %add1135
+  %6 = load float, float* %arrayidx12, align 4
   %mul13 = fmul fast float %5, %6
   %add14 = fadd fast float %add8, %mul13
-  %7 = load float* %arrayidx15, align 4
+  %7 = load float, float* %arrayidx15, align 4
   %add1736 = or i64 %mul, 3
-  %arrayidx18 = getelementptr inbounds float* %A, i64 %add1736
-  %8 = load float* %arrayidx18, align 4
+  %arrayidx18 = getelementptr inbounds float, float* %A, i64 %add1736
+  %8 = load float, float* %arrayidx18, align 4
   %mul19 = fmul fast float %7, %8
   %add20 = fadd fast float %add14, %mul19
   store float %add20, float* %C.addr.038, align 4
-  %incdec.ptr = getelementptr inbounds float* %C.addr.038, i64 1
+  %incdec.ptr = getelementptr inbounds float, float* %C.addr.038, i64 1
   %inc = add nsw i64 %i.039, 1
   %exitcond = icmp eq i64 %inc, %0
   br i1 %exitcond, label %for.end, label %for.body
@@ -389,24 +389,24 @@ entry:
   br i1 %cmp17, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:
-  %0 = load double* %B, align 8
-  %arrayidx4 = getelementptr inbounds double* %B, i64 1
-  %1 = load double* %arrayidx4, align 8
+  %0 = load double, double* %B, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %B, i64 1
+  %1 = load double, double* %arrayidx4, align 8
   %2 = sext i32 %n to i64
   br label %for.body
 
 for.body:
   %i.018 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %mul = shl nsw i64 %i.018, 2
-  %arrayidx2 = getelementptr inbounds double* %A, i64 %mul
-  %3 = load double* %arrayidx2, align 8
+  %arrayidx2 = getelementptr inbounds double, double* %A, i64 %mul
+  %3 = load double, double* %arrayidx2, align 8
   %mul3 = fmul fast double %0, %3
   %add16 = or i64 %mul, 1
-  %arrayidx6 = getelementptr inbounds double* %A, i64 %add16
-  %4 = load double* %arrayidx6, align 8
+  %arrayidx6 = getelementptr inbounds double, double* %A, i64 %add16
+  %4 = load double, double* %arrayidx6, align 8
   %mul7 = fmul fast double %1, %4
   %add8 = fadd fast double %mul3, %mul7
-  %arrayidx9 = getelementptr inbounds double* %C, i64 %i.018
+  %arrayidx9 = getelementptr inbounds double, double* %C, i64 %i.018
   store double %add8, double* %arrayidx9, align 8
   %inc = add nsw i64 %i.018, 1
   %exitcond = icmp eq i64 %inc, %2
diff --git a/test/Transforms/SLPVectorizer/X86/implicitfloat.ll b/test/Transforms/SLPVectorizer/X86/implicitfloat.ll
index f63f2683b10e..f7283f0d0271 100644
--- a/test/Transforms/SLPVectorizer/X86/implicitfloat.ll
+++ b/test/Transforms/SLPVectorizer/X86/implicitfloat.ll
@@ -9,16 +9,16 @@ target triple = "x86_64-apple-macosx10.8.0"
 ; CHECK: ret
 define void @test1(double* %a, double* %b, double* %c) noimplicitfloat { ; <------ noimplicitfloat attribute here!
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   store double %mul, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/X86/in-tree-user.ll b/test/Transforms/SLPVectorizer/X86/in-tree-user.ll
index 194a0fbd5ed0..b0ce07421b57 100644
--- a/test/Transforms/SLPVectorizer/X86/in-tree-user.ll
+++ b/test/Transforms/SLPVectorizer/X86/in-tree-user.ll
@@ -19,15 +19,15 @@ entry:
 for.body:                                         ; preds = %for.inc, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ]
   %0 = shl nsw i64 %indvars.iv, 1
-  %arrayidx = getelementptr inbounds double* %A, i64 %0
-  %1 = load double* %arrayidx, align 8
+  %arrayidx = getelementptr inbounds double, double* %A, i64 %0
+  %1 = load double, double* %arrayidx, align 8
   %mul1 = fmul double %conv, %1
   %mul2 = fmul double %mul1, 7.000000e+00
   %add = fadd double %mul2, 5.000000e+00
   %InTreeUser = fadd double %add, %add    ; <------------------ In tree user.
   %2 = or i64 %0, 1
-  %arrayidx6 = getelementptr inbounds double* %A, i64 %2
-  %3 = load double* %arrayidx6, align 8
+  %arrayidx6 = getelementptr inbounds double, double* %A, i64 %2
+  %3 = load double, double* %arrayidx6, align 8
   %mul8 = fmul double %conv, %3
   %mul9 = fmul double %mul8, 4.000000e+00
   %add10 = fadd double %mul9, 9.000000e+00
@@ -35,7 +35,7 @@ for.body:                                         ; preds = %for.inc, %entry
   br i1 %cmp11, label %if.then, label %for.inc
 
 if.then:                                          ; preds = %for.body
-  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([6 x i8]* @.str, i64 0, i64 0))
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0))
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body, %if.then
diff --git a/test/Transforms/SLPVectorizer/X86/intrinsic.ll b/test/Transforms/SLPVectorizer/X86/intrinsic.ll
index 937252f4146b..cc5a4afe43d9 100644
--- a/test/Transforms/SLPVectorizer/X86/intrinsic.ll
+++ b/test/Transforms/SLPVectorizer/X86/intrinsic.ll
@@ -13,18 +13,18 @@ declare double @llvm.fabs.f64(double) nounwind readnone
 ;CHECK: ret
 define void @vec_fabs_f64(double* %a, double* %b, double* %c) {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
   %call = tail call double @llvm.fabs.f64(double %mul) nounwind readnone
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   %call5 = tail call double @llvm.fabs.f64(double %mul5) nounwind readnone
   store double %call, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %call5, double* %arrayidx5, align 8
   ret void
 }
@@ -39,33 +39,33 @@ declare float @llvm.copysign.f32(float, float) nounwind readnone
 ;CHECK: ret
 define void @vec_copysign_f32(float* %a, float* %b, float* noalias %c) {
 entry:
-  %0 = load float* %a, align 4
-  %1 = load float* %b, align 4
+  %0 = load float, float* %a, align 4
+  %1 = load float, float* %b, align 4
   %call0 = tail call float @llvm.copysign.f32(float %0, float %1) nounwind readnone
   store float %call0, float* %c, align 4
 
-  %ix2 = getelementptr inbounds float* %a, i64 1
-  %2 = load float* %ix2, align 4
-  %ix3 = getelementptr inbounds float* %b, i64 1
-  %3 = load float* %ix3, align 4
+  %ix2 = getelementptr inbounds float, float* %a, i64 1
+  %2 = load float, float* %ix2, align 4
+  %ix3 = getelementptr inbounds float, float* %b, i64 1
+  %3 = load float, float* %ix3, align 4
   %call1 = tail call float @llvm.copysign.f32(float %2, float %3) nounwind readnone
-  %c1 = getelementptr inbounds float* %c, i64 1
+  %c1 = getelementptr inbounds float, float* %c, i64 1
   store float %call1, float* %c1, align 4
 
-  %ix4 = getelementptr inbounds float* %a, i64 2
-  %4 = load float* %ix4, align 4
-  %ix5 = getelementptr inbounds float* %b, i64 2
-  %5 = load float* %ix5, align 4
+  %ix4 = getelementptr inbounds float, float* %a, i64 2
+  %4 = load float, float* %ix4, align 4
+  %ix5 = getelementptr inbounds float, float* %b, i64 2
+  %5 = load float, float* %ix5, align 4
   %call2 = tail call float @llvm.copysign.f32(float %4, float %5) nounwind readnone
-  %c2 = getelementptr inbounds float* %c, i64 2
+  %c2 = getelementptr inbounds float, float* %c, i64 2
   store float %call2, float* %c2, align 4
 
-  %ix6 = getelementptr inbounds float* %a, i64 3
-  %6 = load float* %ix6, align 4
-  %ix7 = getelementptr inbounds float* %b, i64 3
-  %7 = load float* %ix7, align 4
+  %ix6 = getelementptr inbounds float, float* %a, i64 3
+  %6 = load float, float* %ix6, align 4
+  %ix7 = getelementptr inbounds float, float* %b, i64 3
+  %7 = load float, float* %ix7, align 4
   %call3 = tail call float @llvm.copysign.f32(float %6, float %7) nounwind readnone
-  %c3 = getelementptr inbounds float* %c, i64 3
+  %c3 = getelementptr inbounds float, float* %c, i64 3
   store float %call3, float* %c3, align 4
 
   ret void
@@ -75,38 +75,38 @@ declare i32 @llvm.bswap.i32(i32) nounwind readnone
 
 define void @vec_bswap_i32(i32* %a, i32* %b, i32* %c) {
 entry:
-  %i0 = load i32* %a, align 4
-  %i1 = load i32* %b, align 4
+  %i0 = load i32, i32* %a, align 4
+  %i1 = load i32, i32* %b, align 4
   %add1 = add i32 %i0, %i1
   %call1 = tail call i32 @llvm.bswap.i32(i32 %add1) nounwind readnone
 
-  %arrayidx2 = getelementptr inbounds i32* %a, i32 1
-  %i2 = load i32* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i32 1
-  %i3 = load i32* %arrayidx3, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 1
+  %i2 = load i32, i32* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i32 1
+  %i3 = load i32, i32* %arrayidx3, align 4
   %add2 = add i32 %i2, %i3
   %call2 = tail call i32 @llvm.bswap.i32(i32 %add2) nounwind readnone
 
-  %arrayidx4 = getelementptr inbounds i32* %a, i32 2
-  %i4 = load i32* %arrayidx4, align 4
-  %arrayidx5 = getelementptr inbounds i32* %b, i32 2
-  %i5 = load i32* %arrayidx5, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %a, i32 2
+  %i4 = load i32, i32* %arrayidx4, align 4
+  %arrayidx5 = getelementptr inbounds i32, i32* %b, i32 2
+  %i5 = load i32, i32* %arrayidx5, align 4
   %add3 = add i32 %i4, %i5
   %call3 = tail call i32 @llvm.bswap.i32(i32 %add3) nounwind readnone
 
-  %arrayidx6 = getelementptr inbounds i32* %a, i32 3
-  %i6 = load i32* %arrayidx6, align 4
-  %arrayidx7 = getelementptr inbounds i32* %b, i32 3
-  %i7 = load i32* %arrayidx7, align 4
+  %arrayidx6 = getelementptr inbounds i32, i32* %a, i32 3
+  %i6 = load i32, i32* %arrayidx6, align 4
+  %arrayidx7 = getelementptr inbounds i32, i32* %b, i32 3
+  %i7 = load i32, i32* %arrayidx7, align 4
   %add4 = add i32 %i6, %i7
   %call4 = tail call i32 @llvm.bswap.i32(i32 %add4) nounwind readnone
 
   store i32 %call1, i32* %c, align 4
-  %arrayidx8 = getelementptr inbounds i32* %c, i32 1
+  %arrayidx8 = getelementptr inbounds i32, i32* %c, i32 1
   store i32 %call2, i32* %arrayidx8, align 4
-  %arrayidx9 = getelementptr inbounds i32* %c, i32 2
+  %arrayidx9 = getelementptr inbounds i32, i32* %c, i32 2
   store i32 %call3, i32* %arrayidx9, align 4
-  %arrayidx10 = getelementptr inbounds i32* %c, i32 3
+  %arrayidx10 = getelementptr inbounds i32, i32* %c, i32 3
   store i32 %call4, i32* %arrayidx10, align 4
   ret void
 
@@ -122,38 +122,38 @@ declare i32 @llvm.ctlz.i32(i32,i1) nounwind readnone
 
 define void @vec_ctlz_i32(i32* %a, i32* %b, i32* %c, i1) {
 entry:
-  %i0 = load i32* %a, align 4
-  %i1 = load i32* %b, align 4
+  %i0 = load i32, i32* %a, align 4
+  %i1 = load i32, i32* %b, align 4
   %add1 = add i32 %i0, %i1
   %call1 = tail call i32 @llvm.ctlz.i32(i32 %add1,i1 true) nounwind readnone
 
-  %arrayidx2 = getelementptr inbounds i32* %a, i32 1
-  %i2 = load i32* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i32 1
-  %i3 = load i32* %arrayidx3, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 1
+  %i2 = load i32, i32* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i32 1
+  %i3 = load i32, i32* %arrayidx3, align 4
   %add2 = add i32 %i2, %i3
   %call2 = tail call i32 @llvm.ctlz.i32(i32 %add2,i1 true) nounwind readnone
 
-  %arrayidx4 = getelementptr inbounds i32* %a, i32 2
-  %i4 = load i32* %arrayidx4, align 4
-  %arrayidx5 = getelementptr inbounds i32* %b, i32 2
-  %i5 = load i32* %arrayidx5, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %a, i32 2
+  %i4 = load i32, i32* %arrayidx4, align 4
+  %arrayidx5 = getelementptr inbounds i32, i32* %b, i32 2
+  %i5 = load i32, i32* %arrayidx5, align 4
   %add3 = add i32 %i4, %i5
   %call3 = tail call i32 @llvm.ctlz.i32(i32 %add3,i1 true) nounwind readnone
 
-  %arrayidx6 = getelementptr inbounds i32* %a, i32 3
-  %i6 = load i32* %arrayidx6, align 4
-  %arrayidx7 = getelementptr inbounds i32* %b, i32 3
-  %i7 = load i32* %arrayidx7, align 4
+  %arrayidx6 = getelementptr inbounds i32, i32* %a, i32 3
+  %i6 = load i32, i32* %arrayidx6, align 4
+  %arrayidx7 = getelementptr inbounds i32, i32* %b, i32 3
+  %i7 = load i32, i32* %arrayidx7, align 4
   %add4 = add i32 %i6, %i7
   %call4 = tail call i32 @llvm.ctlz.i32(i32 %add4,i1 true) nounwind readnone
 
   store i32 %call1, i32* %c, align 4
-  %arrayidx8 = getelementptr inbounds i32* %c, i32 1
+  %arrayidx8 = getelementptr inbounds i32, i32* %c, i32 1
   store i32 %call2, i32* %arrayidx8, align 4
-  %arrayidx9 = getelementptr inbounds i32* %c, i32 2
+  %arrayidx9 = getelementptr inbounds i32, i32* %c, i32 2
   store i32 %call3, i32* %arrayidx9, align 4
-  %arrayidx10 = getelementptr inbounds i32* %c, i32 3
+  %arrayidx10 = getelementptr inbounds i32, i32* %c, i32 3
   store i32 %call4, i32* %arrayidx10, align 4
   ret void
 
@@ -167,38 +167,38 @@ entry:
 
 define void @vec_ctlz_i32_neg(i32* %a, i32* %b, i32* %c, i1) {
 entry:
-  %i0 = load i32* %a, align 4
-  %i1 = load i32* %b, align 4
+  %i0 = load i32, i32* %a, align 4
+  %i1 = load i32, i32* %b, align 4
   %add1 = add i32 %i0, %i1
   %call1 = tail call i32 @llvm.ctlz.i32(i32 %add1,i1 true) nounwind readnone
 
-  %arrayidx2 = getelementptr inbounds i32* %a, i32 1
-  %i2 = load i32* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i32 1
-  %i3 = load i32* %arrayidx3, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 1
+  %i2 = load i32, i32* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i32 1
+  %i3 = load i32, i32* %arrayidx3, align 4
   %add2 = add i32 %i2, %i3
   %call2 = tail call i32 @llvm.ctlz.i32(i32 %add2,i1 false) nounwind readnone
 
-  %arrayidx4 = getelementptr inbounds i32* %a, i32 2
-  %i4 = load i32* %arrayidx4, align 4
-  %arrayidx5 = getelementptr inbounds i32* %b, i32 2
-  %i5 = load i32* %arrayidx5, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %a, i32 2
+  %i4 = load i32, i32* %arrayidx4, align 4
+  %arrayidx5 = getelementptr inbounds i32, i32* %b, i32 2
+  %i5 = load i32, i32* %arrayidx5, align 4
   %add3 = add i32 %i4, %i5
   %call3 = tail call i32 @llvm.ctlz.i32(i32 %add3,i1 true) nounwind readnone
 
-  %arrayidx6 = getelementptr inbounds i32* %a, i32 3
-  %i6 = load i32* %arrayidx6, align 4
-  %arrayidx7 = getelementptr inbounds i32* %b, i32 3
-  %i7 = load i32* %arrayidx7, align 4
+  %arrayidx6 = getelementptr inbounds i32, i32* %a, i32 3
+  %i6 = load i32, i32* %arrayidx6, align 4
+  %arrayidx7 = getelementptr inbounds i32, i32* %b, i32 3
+  %i7 = load i32, i32* %arrayidx7, align 4
   %add4 = add i32 %i6, %i7
   %call4 = tail call i32 @llvm.ctlz.i32(i32 %add4,i1 false) nounwind readnone
 
   store i32 %call1, i32* %c, align 4
-  %arrayidx8 = getelementptr inbounds i32* %c, i32 1
+  %arrayidx8 = getelementptr inbounds i32, i32* %c, i32 1
   store i32 %call2, i32* %arrayidx8, align 4
-  %arrayidx9 = getelementptr inbounds i32* %c, i32 2
+  %arrayidx9 = getelementptr inbounds i32, i32* %c, i32 2
   store i32 %call3, i32* %arrayidx9, align 4
-  %arrayidx10 = getelementptr inbounds i32* %c, i32 3
+  %arrayidx10 = getelementptr inbounds i32, i32* %c, i32 3
   store i32 %call4, i32* %arrayidx10, align 4
   ret void
 
@@ -212,38 +212,38 @@ declare i32 @llvm.cttz.i32(i32,i1) nounwind readnone
 
 define void @vec_cttz_i32(i32* %a, i32* %b, i32* %c, i1) {
 entry:
-  %i0 = load i32* %a, align 4
-  %i1 = load i32* %b, align 4
+  %i0 = load i32, i32* %a, align 4
+  %i1 = load i32, i32* %b, align 4
   %add1 = add i32 %i0, %i1
   %call1 = tail call i32 @llvm.cttz.i32(i32 %add1,i1 true) nounwind readnone
 
-  %arrayidx2 = getelementptr inbounds i32* %a, i32 1
-  %i2 = load i32* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i32 1
-  %i3 = load i32* %arrayidx3, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 1
+  %i2 = load i32, i32* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i32 1
+  %i3 = load i32, i32* %arrayidx3, align 4
   %add2 = add i32 %i2, %i3
   %call2 = tail call i32 @llvm.cttz.i32(i32 %add2,i1 true) nounwind readnone
 
-  %arrayidx4 = getelementptr inbounds i32* %a, i32 2
-  %i4 = load i32* %arrayidx4, align 4
-  %arrayidx5 = getelementptr inbounds i32* %b, i32 2
-  %i5 = load i32* %arrayidx5, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %a, i32 2
+  %i4 = load i32, i32* %arrayidx4, align 4
+  %arrayidx5 = getelementptr inbounds i32, i32* %b, i32 2
+  %i5 = load i32, i32* %arrayidx5, align 4
   %add3 = add i32 %i4, %i5
   %call3 = tail call i32 @llvm.cttz.i32(i32 %add3,i1 true) nounwind readnone
 
-  %arrayidx6 = getelementptr inbounds i32* %a, i32 3
-  %i6 = load i32* %arrayidx6, align 4
-  %arrayidx7 = getelementptr inbounds i32* %b, i32 3
-  %i7 = load i32* %arrayidx7, align 4
+  %arrayidx6 = getelementptr inbounds i32, i32* %a, i32 3
+  %i6 = load i32, i32* %arrayidx6, align 4
+  %arrayidx7 = getelementptr inbounds i32, i32* %b, i32 3
+  %i7 = load i32, i32* %arrayidx7, align 4
   %add4 = add i32 %i6, %i7
   %call4 = tail call i32 @llvm.cttz.i32(i32 %add4,i1 true) nounwind readnone
 
   store i32 %call1, i32* %c, align 4
-  %arrayidx8 = getelementptr inbounds i32* %c, i32 1
+  %arrayidx8 = getelementptr inbounds i32, i32* %c, i32 1
   store i32 %call2, i32* %arrayidx8, align 4
-  %arrayidx9 = getelementptr inbounds i32* %c, i32 2
+  %arrayidx9 = getelementptr inbounds i32, i32* %c, i32 2
   store i32 %call3, i32* %arrayidx9, align 4
-  %arrayidx10 = getelementptr inbounds i32* %c, i32 3
+  %arrayidx10 = getelementptr inbounds i32, i32* %c, i32 3
   store i32 %call4, i32* %arrayidx10, align 4
   ret void
 
@@ -257,38 +257,38 @@ entry:
 
 define void @vec_cttz_i32_neg(i32* %a, i32* %b, i32* %c, i1) {
 entry:
-  %i0 = load i32* %a, align 4
-  %i1 = load i32* %b, align 4
+  %i0 = load i32, i32* %a, align 4
+  %i1 = load i32, i32* %b, align 4
   %add1 = add i32 %i0, %i1
   %call1 = tail call i32 @llvm.cttz.i32(i32 %add1,i1 true) nounwind readnone
 
-  %arrayidx2 = getelementptr inbounds i32* %a, i32 1
-  %i2 = load i32* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i32 1
-  %i3 = load i32* %arrayidx3, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 1
+  %i2 = load i32, i32* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i32 1
+  %i3 = load i32, i32* %arrayidx3, align 4
   %add2 = add i32 %i2, %i3
   %call2 = tail call i32 @llvm.cttz.i32(i32 %add2,i1 false) nounwind readnone
 
-  %arrayidx4 = getelementptr inbounds i32* %a, i32 2
-  %i4 = load i32* %arrayidx4, align 4
-  %arrayidx5 = getelementptr inbounds i32* %b, i32 2
-  %i5 = load i32* %arrayidx5, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %a, i32 2
+  %i4 = load i32, i32* %arrayidx4, align 4
+  %arrayidx5 = getelementptr inbounds i32, i32* %b, i32 2
+  %i5 = load i32, i32* %arrayidx5, align 4
   %add3 = add i32 %i4, %i5
   %call3 = tail call i32 @llvm.cttz.i32(i32 %add3,i1 true) nounwind readnone
 
-  %arrayidx6 = getelementptr inbounds i32* %a, i32 3
-  %i6 = load i32* %arrayidx6, align 4
-  %arrayidx7 = getelementptr inbounds i32* %b, i32 3
-  %i7 = load i32* %arrayidx7, align 4
+  %arrayidx6 = getelementptr inbounds i32, i32* %a, i32 3
+  %i6 = load i32, i32* %arrayidx6, align 4
+  %arrayidx7 = getelementptr inbounds i32, i32* %b, i32 3
+  %i7 = load i32, i32* %arrayidx7, align 4
   %add4 = add i32 %i6, %i7
   %call4 = tail call i32 @llvm.cttz.i32(i32 %add4,i1 false) nounwind readnone
 
   store i32 %call1, i32* %c, align 4
-  %arrayidx8 = getelementptr inbounds i32* %c, i32 1
+  %arrayidx8 = getelementptr inbounds i32, i32* %c, i32 1
   store i32 %call2, i32* %arrayidx8, align 4
-  %arrayidx9 = getelementptr inbounds i32* %c, i32 2
+  %arrayidx9 = getelementptr inbounds i32, i32* %c, i32 2
   store i32 %call3, i32* %arrayidx9, align 4
-  %arrayidx10 = getelementptr inbounds i32* %c, i32 3
+  %arrayidx10 = getelementptr inbounds i32, i32* %c, i32 3
   store i32 %call4, i32* %arrayidx10, align 4
   ret void
 
@@ -300,38 +300,38 @@ entry:
 declare float @llvm.powi.f32(float, i32)
 define void @vec_powi_f32(float* %a, float* %b, float* %c, i32 %P) {
 entry:
-  %i0 = load float* %a, align 4
-  %i1 = load float* %b, align 4
+  %i0 = load float, float* %a, align 4
+  %i1 = load float, float* %b, align 4
   %add1 = fadd float %i0, %i1
   %call1 = tail call float @llvm.powi.f32(float %add1,i32 %P) nounwind readnone
 
-  %arrayidx2 = getelementptr inbounds float* %a, i32 1
-  %i2 = load float* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds float* %b, i32 1
-  %i3 = load float* %arrayidx3, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %a, i32 1
+  %i2 = load float, float* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds float, float* %b, i32 1
+  %i3 = load float, float* %arrayidx3, align 4
   %add2 = fadd float %i2, %i3
   %call2 = tail call float @llvm.powi.f32(float %add2,i32 %P) nounwind readnone
 
-  %arrayidx4 = getelementptr inbounds float* %a, i32 2
-  %i4 = load float* %arrayidx4, align 4
-  %arrayidx5 = getelementptr inbounds float* %b, i32 2
-  %i5 = load float* %arrayidx5, align 4
+  %arrayidx4 = getelementptr inbounds float, float* %a, i32 2
+  %i4 = load float, float* %arrayidx4, align 4
+  %arrayidx5 = getelementptr inbounds float, float* %b, i32 2
+  %i5 = load float, float* %arrayidx5, align 4
   %add3 = fadd float %i4, %i5
   %call3 = tail call float @llvm.powi.f32(float %add3,i32 %P) nounwind readnone
 
-  %arrayidx6 = getelementptr inbounds float* %a, i32 3
-  %i6 = load float* %arrayidx6, align 4
-  %arrayidx7 = getelementptr inbounds float* %b, i32 3
-  %i7 = load float* %arrayidx7, align 4
+  %arrayidx6 = getelementptr inbounds float, float* %a, i32 3
+  %i6 = load float, float* %arrayidx6, align 4
+  %arrayidx7 = getelementptr inbounds float, float* %b, i32 3
+  %i7 = load float, float* %arrayidx7, align 4
   %add4 = fadd float %i6, %i7
   %call4 = tail call float @llvm.powi.f32(float %add4,i32 %P) nounwind readnone
 
   store float %call1, float* %c, align 4
-  %arrayidx8 = getelementptr inbounds float* %c, i32 1
+  %arrayidx8 = getelementptr inbounds float, float* %c, i32 1
   store float %call2, float* %arrayidx8, align 4
-  %arrayidx9 = getelementptr inbounds float* %c, i32 2
+  %arrayidx9 = getelementptr inbounds float, float* %c, i32 2
   store float %call3, float* %arrayidx9, align 4
-  %arrayidx10 = getelementptr inbounds float* %c, i32 3
+  %arrayidx10 = getelementptr inbounds float, float* %c, i32 3
   store float %call4, float* %arrayidx10, align 4
   ret void
 
@@ -346,38 +346,38 @@ entry:
 
 define void @vec_powi_f32_neg(float* %a, float* %b, float* %c, i32 %P, i32 %Q) {
 entry:
-  %i0 = load float* %a, align 4
-  %i1 = load float* %b, align 4
+  %i0 = load float, float* %a, align 4
+  %i1 = load float, float* %b, align 4
   %add1 = fadd float %i0, %i1
   %call1 = tail call float @llvm.powi.f32(float %add1,i32 %P) nounwind readnone
 
-  %arrayidx2 = getelementptr inbounds float* %a, i32 1
-  %i2 = load float* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds float* %b, i32 1
-  %i3 = load float* %arrayidx3, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %a, i32 1
+  %i2 = load float, float* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds float, float* %b, i32 1
+  %i3 = load float, float* %arrayidx3, align 4
   %add2 = fadd float %i2, %i3
   %call2 = tail call float @llvm.powi.f32(float %add2,i32 %Q) nounwind readnone
 
-  %arrayidx4 = getelementptr inbounds float* %a, i32 2
-  %i4 = load float* %arrayidx4, align 4
-  %arrayidx5 = getelementptr inbounds float* %b, i32 2
-  %i5 = load float* %arrayidx5, align 4
+  %arrayidx4 = getelementptr inbounds float, float* %a, i32 2
+  %i4 = load float, float* %arrayidx4, align 4
+  %arrayidx5 = getelementptr inbounds float, float* %b, i32 2
+  %i5 = load float, float* %arrayidx5, align 4
   %add3 = fadd float %i4, %i5
   %call3 = tail call float @llvm.powi.f32(float %add3,i32 %P) nounwind readnone
 
-  %arrayidx6 = getelementptr inbounds float* %a, i32 3
-  %i6 = load float* %arrayidx6, align 4
-  %arrayidx7 = getelementptr inbounds float* %b, i32 3
-  %i7 = load float* %arrayidx7, align 4
+  %arrayidx6 = getelementptr inbounds float, float* %a, i32 3
+  %i6 = load float, float* %arrayidx6, align 4
+  %arrayidx7 = getelementptr inbounds float, float* %b, i32 3
+  %i7 = load float, float* %arrayidx7, align 4
   %add4 = fadd float %i6, %i7
   %call4 = tail call float @llvm.powi.f32(float %add4,i32 %Q) nounwind readnone
 
   store float %call1, float* %c, align 4
-  %arrayidx8 = getelementptr inbounds float* %c, i32 1
+  %arrayidx8 = getelementptr inbounds float, float* %c, i32 1
   store float %call2, float* %arrayidx8, align 4
-  %arrayidx9 = getelementptr inbounds float* %c, i32 2
+  %arrayidx9 = getelementptr inbounds float, float* %c, i32 2
   store float %call3, float* %arrayidx9, align 4
-  %arrayidx10 = getelementptr inbounds float* %c, i32 3
+  %arrayidx10 = getelementptr inbounds float, float* %c, i32 3
   store float %call4, float* %arrayidx10, align 4
   ret void
 
diff --git a/test/Transforms/SLPVectorizer/X86/long_chains.ll b/test/Transforms/SLPVectorizer/X86/long_chains.ll
index 5af3e6d6e903..f87dabf4c9fe 100644
--- a/test/Transforms/SLPVectorizer/X86/long_chains.ll
+++ b/test/Transforms/SLPVectorizer/X86/long_chains.ll
@@ -13,9 +13,9 @@ target triple = "x86_64-apple-macosx10.8.0"
 ; CHECK: ret
 define i32 @test(double* nocapture %A, i8* nocapture %B) {
 entry:
-  %0 = load i8* %B, align 1
-  %arrayidx1 = getelementptr inbounds i8* %B, i64 1
-  %1 = load i8* %arrayidx1, align 1
+  %0 = load i8, i8* %B, align 1
+  %arrayidx1 = getelementptr inbounds i8, i8* %B, i64 1
+  %1 = load i8, i8* %arrayidx1, align 1
   %add = add i8 %0, 3
   %add4 = add i8 %1, 3
   %conv6 = sitofp i8 %add to double
@@ -41,7 +41,7 @@ entry:
   %mul25 = fmul double %add22, %add22
   %add26 = fadd double %mul25, 1.000000e+00
   store double %add24, double* %A, align 8
-  %arrayidx28 = getelementptr inbounds double* %A, i64 1
+  %arrayidx28 = getelementptr inbounds double, double* %A, i64 1
   store double %add26, double* %arrayidx28, align 8
   ret i32 undef
 }
diff --git a/test/Transforms/SLPVectorizer/X86/loopinvariant.ll b/test/Transforms/SLPVectorizer/X86/loopinvariant.ll
index bc12926e3fe6..0c16c34a1888 100644
--- a/test/Transforms/SLPVectorizer/X86/loopinvariant.ll
+++ b/test/Transforms/SLPVectorizer/X86/loopinvariant.ll
@@ -18,43 +18,43 @@ entry:
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
-  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
   %add1 = add nsw i32 %0, %n
   store i32 %add1, i32* %arrayidx, align 4
   %1 = or i64 %indvars.iv, 1
-  %arrayidx4 = getelementptr inbounds i32* %A, i64 %1
-  %2 = load i32* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %A, i64 %1
+  %2 = load i32, i32* %arrayidx4, align 4
   %add5 = add nsw i32 %2, %n
   store i32 %add5, i32* %arrayidx4, align 4
   %3 = or i64 %indvars.iv, 2
-  %arrayidx8 = getelementptr inbounds i32* %A, i64 %3
-  %4 = load i32* %arrayidx8, align 4
+  %arrayidx8 = getelementptr inbounds i32, i32* %A, i64 %3
+  %4 = load i32, i32* %arrayidx8, align 4
   %add9 = add nsw i32 %4, %n
   store i32 %add9, i32* %arrayidx8, align 4
   %5 = or i64 %indvars.iv, 3
-  %arrayidx12 = getelementptr inbounds i32* %A, i64 %5
-  %6 = load i32* %arrayidx12, align 4
+  %arrayidx12 = getelementptr inbounds i32, i32* %A, i64 %5
+  %6 = load i32, i32* %arrayidx12, align 4
   %add13 = add nsw i32 %6, %n
   store i32 %add13, i32* %arrayidx12, align 4
   %7 = or i64 %indvars.iv, 4
-  %arrayidx16 = getelementptr inbounds i32* %A, i64 %7
-  %8 = load i32* %arrayidx16, align 4
+  %arrayidx16 = getelementptr inbounds i32, i32* %A, i64 %7
+  %8 = load i32, i32* %arrayidx16, align 4
   %add17 = add nsw i32 %8, %n
   store i32 %add17, i32* %arrayidx16, align 4
   %9 = or i64 %indvars.iv, 5
-  %arrayidx20 = getelementptr inbounds i32* %A, i64 %9
-  %10 = load i32* %arrayidx20, align 4
+  %arrayidx20 = getelementptr inbounds i32, i32* %A, i64 %9
+  %10 = load i32, i32* %arrayidx20, align 4
   %add21 = add nsw i32 %10, %n
   store i32 %add21, i32* %arrayidx20, align 4
   %11 = or i64 %indvars.iv, 6
-  %arrayidx24 = getelementptr inbounds i32* %A, i64 %11
-  %12 = load i32* %arrayidx24, align 4
+  %arrayidx24 = getelementptr inbounds i32, i32* %A, i64 %11
+  %12 = load i32, i32* %arrayidx24, align 4
   %add25 = add nsw i32 %12, %n
   store i32 %add25, i32* %arrayidx24, align 4
   %13 = or i64 %indvars.iv, 7
-  %arrayidx28 = getelementptr inbounds i32* %A, i64 %13
-  %14 = load i32* %arrayidx28, align 4
+  %arrayidx28 = getelementptr inbounds i32, i32* %A, i64 %13
+  %14 = load i32, i32* %arrayidx28, align 4
   %add29 = add nsw i32 %14, %n
   store i32 %add29, i32* %arrayidx28, align 4
   %indvars.iv.next = add i64 %indvars.iv, 8
diff --git a/test/Transforms/SLPVectorizer/X86/metadata.ll b/test/Transforms/SLPVectorizer/X86/metadata.ll
index e021cca23e34..ebef6b53c6a4 100644
--- a/test/Transforms/SLPVectorizer/X86/metadata.ll
+++ b/test/Transforms/SLPVectorizer/X86/metadata.ll
@@ -12,16 +12,16 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 define void @test1(double* %a, double* %b, double* %c) {
 entry:
-  %i0 = load double* %a, align 8, !tbaa !4
-  %i1 = load double* %b, align 8, !tbaa !4
+  %i0 = load double, double* %a, align 8, !tbaa !4
+  %i1 = load double, double* %b, align 8, !tbaa !4
   %mul = fmul double %i0, %i1, !fpmath !0
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8, !tbaa !4
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8, !tbaa !4
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8, !tbaa !4
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8, !tbaa !4
   %mul5 = fmul double %i3, %i4, !fpmath !0
   store double %mul, double* %c, align 8, !tbaa !4
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8, !tbaa !4
   ret void
 }
@@ -35,17 +35,17 @@ entry:
 
 define void @test2(double* %a, double* %b, i8* %e) {
 entry:
-  %i0 = load double* %a, align 8, !tbaa !4
-  %i1 = load double* %b, align 8, !tbaa !4
+  %i0 = load double, double* %a, align 8, !tbaa !4
+  %i1 = load double, double* %b, align 8, !tbaa !4
   %mul = fmul double %i0, %i1, !fpmath !1
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8, !tbaa !4
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8, !tbaa !4
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8, !tbaa !4
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8, !tbaa !4
   %mul5 = fmul double %i3, %i4, !fpmath !1
   %c = bitcast i8* %e to double*
   store double %mul, double* %c, align 8, !tbaa !4
-  %carrayidx5 = getelementptr inbounds i8* %e, i64 8
+  %carrayidx5 = getelementptr inbounds i8, i8* %e, i64 8
   %arrayidx5 = bitcast i8* %carrayidx5 to double*
   store double %mul5, double* %arrayidx5, align 8, !tbaa !4
   ret void
diff --git a/test/Transforms/SLPVectorizer/X86/multi_block.ll b/test/Transforms/SLPVectorizer/X86/multi_block.ll
index 2f1cc74d05ff..b381d06688bd 100644
--- a/test/Transforms/SLPVectorizer/X86/multi_block.ll
+++ b/test/Transforms/SLPVectorizer/X86/multi_block.ll
@@ -25,16 +25,16 @@ target triple = "x86_64-apple-macosx10.7.0"
 ;CHECK: store <2 x double>
 ;CHECK: ret
 define i32 @bar(double* nocapture %A, i32 %d) {
-  %1 = load double* %A, align 8
-  %2 = getelementptr inbounds double* %A, i64 1
-  %3 = load double* %2, align 8
+  %1 = load double, double* %A, align 8
+  %2 = getelementptr inbounds double, double* %A, i64 1
+  %3 = load double, double* %2, align 8
   %4 = fptrunc double %1 to float
   %5 = fptrunc double %3 to float
   %6 = icmp eq i32 %d, 0
   br i1 %6, label %9, label %7
 
 ; <label>:7                                       ; preds = %0
-  %8 = tail call i32 (...)* @foo()
+  %8 = tail call i32 (...) @foo()
   br label %9
 
 ; <label>:9                                       ; preds = %0, %7
@@ -42,11 +42,11 @@ define i32 @bar(double* nocapture %A, i32 %d) {
   %11 = fadd float %5, 5.000000e+00
   %12 = fpext float %10 to double
   %13 = fadd double %12, 9.000000e+00
-  %14 = getelementptr inbounds double* %A, i64 8
+  %14 = getelementptr inbounds double, double* %A, i64 8
   store double %13, double* %14, align 8
   %15 = fpext float %11 to double
   %16 = fadd double %15, 5.000000e+00
-  %17 = getelementptr inbounds double* %A, i64 9
+  %17 = getelementptr inbounds double, double* %A, i64 9
   store double %16, double* %17, align 8
   ret i32 undef
 }
diff --git a/test/Transforms/SLPVectorizer/X86/multi_user.ll b/test/Transforms/SLPVectorizer/X86/multi_user.ll
index 63a77e4b6733..3197f6db266f 100644
--- a/test/Transforms/SLPVectorizer/X86/multi_user.ll
+++ b/test/Transforms/SLPVectorizer/X86/multi_user.ll
@@ -20,27 +20,27 @@ target triple = "x86_64-apple-macosx10.7.0"
 define i32 @foo(i32* nocapture %A, i32 %n) {
   %1 = mul nsw i32 %n, 5
   %2 = add nsw i32 %1, 7
-  %3 = load i32* %A, align 4
+  %3 = load i32, i32* %A, align 4
   %4 = add nsw i32 %2, %3
   store i32 %4, i32* %A, align 4
   %5 = add nsw i32 %1, 8
-  %6 = getelementptr inbounds i32* %A, i64 1
-  %7 = load i32* %6, align 4
+  %6 = getelementptr inbounds i32, i32* %A, i64 1
+  %7 = load i32, i32* %6, align 4
   %8 = add nsw i32 %5, %7
   store i32 %8, i32* %6, align 4
   %9 = add nsw i32 %1, 9
-  %10 = getelementptr inbounds i32* %A, i64 2
-  %11 = load i32* %10, align 4
+  %10 = getelementptr inbounds i32, i32* %A, i64 2
+  %11 = load i32, i32* %10, align 4
   %12 = add nsw i32 %9, %11
   store i32 %12, i32* %10, align 4
   %13 = add nsw i32 %1, 10
-  %14 = getelementptr inbounds i32* %A, i64 3
-  %15 = load i32* %14, align 4
+  %14 = getelementptr inbounds i32, i32* %A, i64 3
+  %15 = load i32, i32* %14, align 4
   %16 = add nsw i32 %13, %15
   store i32 %16, i32* %14, align 4
   %17 = add nsw i32 %1, 11
-  %18 = getelementptr inbounds i32* %A, i64 4
-  %19 = load i32* %18, align 4
+  %18 = getelementptr inbounds i32, i32* %A, i64 4
+  %19 = load i32, i32* %18, align 4
   %20 = add nsw i32 %17, %19
   store i32 %20, i32* %18, align 4
   ret i32 undef
diff --git a/test/Transforms/SLPVectorizer/X86/odd_store.ll b/test/Transforms/SLPVectorizer/X86/odd_store.ll
index 027f6016e2b9..25f049adf479 100644
--- a/test/Transforms/SLPVectorizer/X86/odd_store.ll
+++ b/test/Transforms/SLPVectorizer/X86/odd_store.ll
@@ -18,28 +18,28 @@ target triple = "x86_64-apple-macosx10.8.0"
 ;CHECK-NOT: store <3 x i8>
 ;CHECK: ret
 define i32 @foo(i8* noalias nocapture %A, float* noalias nocapture %B, float %T) {
-  %1 = getelementptr inbounds float* %B, i64 10
-  %2 = load float* %1, align 4
+  %1 = getelementptr inbounds float, float* %B, i64 10
+  %2 = load float, float* %1, align 4
   %3 = fmul float %2, %T
   %4 = fpext float %3 to double
   %5 = fadd double %4, 4.000000e+00
   %6 = fptosi double %5 to i8
   store i8 %6, i8* %A, align 1
-  %7 = getelementptr inbounds float* %B, i64 11
-  %8 = load float* %7, align 4
+  %7 = getelementptr inbounds float, float* %B, i64 11
+  %8 = load float, float* %7, align 4
   %9 = fmul float %8, %T
   %10 = fpext float %9 to double
   %11 = fadd double %10, 5.000000e+00
   %12 = fptosi double %11 to i8
-  %13 = getelementptr inbounds i8* %A, i64 1
+  %13 = getelementptr inbounds i8, i8* %A, i64 1
   store i8 %12, i8* %13, align 1
-  %14 = getelementptr inbounds float* %B, i64 12
-  %15 = load float* %14, align 4
+  %14 = getelementptr inbounds float, float* %B, i64 12
+  %15 = load float, float* %14, align 4
   %16 = fmul float %15, %T
   %17 = fpext float %16 to double
   %18 = fadd double %17, 6.000000e+00
   %19 = fptosi double %18 to i8
-  %20 = getelementptr inbounds i8* %A, i64 2
+  %20 = getelementptr inbounds i8, i8* %A, i64 2
   store i8 %19, i8* %20, align 1
   ret i32 undef
 }
diff --git a/test/Transforms/SLPVectorizer/X86/operandorder.ll b/test/Transforms/SLPVectorizer/X86/operandorder.ll
index c5322a839ed1..109540bc769d 100644
--- a/test/Transforms/SLPVectorizer/X86/operandorder.ll
+++ b/test/Transforms/SLPVectorizer/X86/operandorder.ll
@@ -13,12 +13,12 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 
 define void @shuffle_operands1(double * noalias %from, double * noalias %to,
                                double %v1, double %v2) {
-  %from_1 = getelementptr double *%from, i64 1
-  %v0_1 = load double * %from
-  %v0_2 = load double * %from_1
+  %from_1 = getelementptr double, double *%from, i64 1
+  %v0_1 = load double , double * %from
+  %v0_2 = load double , double * %from_1
   %v1_1 = fadd double %v0_1, %v1
   %v1_2 = fadd double %v2, %v0_2
-  %to_2 = getelementptr double * %to, i64 1
+  %to_2 = getelementptr double, double * %to, i64 1
   store double %v1_1, double *%to
   store double %v1_2, double *%to_2
   ret void
@@ -35,12 +35,12 @@ br label %lp
 
 lp:
   %p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ]
-  %from_1 = getelementptr double *%from, i64 1
-  %v0_1 = load double * %from
-  %v0_2 = load double * %from_1
+  %from_1 = getelementptr double, double *%from, i64 1
+  %v0_1 = load double , double * %from
+  %v0_2 = load double , double * %from_1
   %v1_1 = fadd double %v0_1, %p
   %v1_2 = fadd double %v0_1, %v0_2
-  %to_2 = getelementptr double * %to, i64 1
+  %to_2 = getelementptr double, double * %to, i64 1
   store double %v1_1, double *%to
   store double %v1_2, double *%to_2
 br i1 undef, label %lp, label %ext
@@ -60,12 +60,12 @@ br label %lp
 
 lp:
   %p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ]
-  %from_1 = getelementptr double *%from, i64 1
-  %v0_1 = load double * %from
-  %v0_2 = load double * %from_1
+  %from_1 = getelementptr double, double *%from, i64 1
+  %v0_1 = load double , double * %from
+  %v0_2 = load double , double * %from_1
   %v1_1 = fadd double %p, %v0_1
   %v1_2 = fadd double %v0_2, %v0_1
-  %to_2 = getelementptr double * %to, i64 1
+  %to_2 = getelementptr double, double * %to, i64 1
   store double %v1_1, double *%to
   store double %v1_2, double *%to_2
 br i1 undef, label %lp, label %ext
@@ -85,12 +85,12 @@ br label %lp
 
 lp:
   %p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ]
-  %from_1 = getelementptr double *%from, i64 1
-  %v0_1 = load double * %from
-  %v0_2 = load double * %from_1
+  %from_1 = getelementptr double, double *%from, i64 1
+  %v0_1 = load double , double * %from
+  %v0_2 = load double , double * %from_1
   %v1_1 = fadd double %p, %v0_1
   %v1_2 = fadd double %v0_1, %v0_2
-  %to_2 = getelementptr double * %to, i64 1
+  %to_2 = getelementptr double, double * %to, i64 1
   store double %v1_1, double *%to
   store double %v1_2, double *%to_2
 br i1 undef, label %lp, label %ext
@@ -111,12 +111,12 @@ br label %lp
 
 lp:
   %p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ]
-  %from_1 = getelementptr double *%from, i64 1
-  %v0_1 = load double * %from
-  %v0_2 = load double * %from_1
+  %from_1 = getelementptr double, double *%from, i64 1
+  %v0_1 = load double , double * %from
+  %v0_2 = load double , double * %from_1
   %v1_1 = fadd double %v0_2, %v0_1
   %v1_2 = fadd double %p, %v0_1
-  %to_2 = getelementptr double * %to, i64 1
+  %to_2 = getelementptr double, double * %to, i64 1
   store double %v1_1, double *%to
   store double %v1_2, double *%to_2
 br i1 undef, label %lp, label %ext
@@ -136,12 +136,12 @@ br label %lp
 
 lp:
   %p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ]
-  %from_1 = getelementptr double *%from, i64 1
-  %v0_1 = load double * %from
-  %v0_2 = load double * %from_1
+  %from_1 = getelementptr double, double *%from, i64 1
+  %v0_1 = load double , double * %from
+  %v0_2 = load double , double * %from_1
   %v1_1 = fadd double %v0_1, %v0_2
   %v1_2 = fadd double %p, %v0_1
-  %to_2 = getelementptr double * %to, i64 1
+  %to_2 = getelementptr double, double * %to, i64 1
   store double %v1_1, double *%to
   store double %v1_2, double *%to_2
 br i1 undef, label %lp, label %ext
@@ -162,12 +162,12 @@ br label %lp
 
 lp:
   %p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ]
-  %from_1 = getelementptr double *%from, i64 1
-  %v0_1 = load double * %from
-  %v0_2 = load double * %from_1
+  %from_1 = getelementptr double, double *%from, i64 1
+  %v0_1 = load double , double * %from
+  %v0_2 = load double , double * %from_1
   %v1_1 = fadd double %v0_1, %v0_2
   %v1_2 = fadd double %v0_1, %p
-  %to_2 = getelementptr double * %to, i64 1
+  %to_2 = getelementptr double, double * %to, i64 1
   store double %v1_1, double *%to
   store double %v1_2, double *%to_2
 br i1 undef, label %lp, label %ext
@@ -181,7 +181,7 @@ ext:
 
 ; CHECK-LABEL: good_load_order
 
-; CHECK: %[[V1:[0-9]+]] = load <4 x float>*
+; CHECK: %[[V1:[0-9]+]] = load <4 x float>, <4 x float>*
 ; CHECK: %[[V2:[0-9]+]] = insertelement <4 x float> undef, float %1, i32 0
 ; CHECK: %[[V3:[0-9]+]] = shufflevector <4 x float> %[[V2]], <4 x float> %[[V1]], <4 x i32> <i32 0, i32 4, i32 5, i32 6>
 ; CHECK:                = fmul <4 x float> %[[V1]], %[[V3]]
@@ -193,36 +193,36 @@ entry:
   br label %for.cond1.preheader
 
 for.cond1.preheader:
-  %0 = load float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), align 16
+  %0 = load float, float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), align 16
   br label %for.body3
 
 for.body3:
   %1 = phi float [ %0, %for.cond1.preheader ], [ %10, %for.body3 ]
   %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.body3 ]
   %2 = add nsw i64 %indvars.iv, 1
-  %arrayidx = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %2
-  %3 = load float* %arrayidx, align 4
-  %arrayidx5 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv
+  %arrayidx = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %2
+  %3 = load float, float* %arrayidx, align 4
+  %arrayidx5 = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %indvars.iv
   %mul6 = fmul float %3, %1
   store float %mul6, float* %arrayidx5, align 4
   %4 = add nsw i64 %indvars.iv, 2
-  %arrayidx11 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %4
-  %5 = load float* %arrayidx11, align 4
+  %arrayidx11 = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %4
+  %5 = load float, float* %arrayidx11, align 4
   %mul15 = fmul float %5, %3
   store float %mul15, float* %arrayidx, align 4
   %6 = add nsw i64 %indvars.iv, 3
-  %arrayidx21 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %6
-  %7 = load float* %arrayidx21, align 4
+  %arrayidx21 = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %6
+  %7 = load float, float* %arrayidx21, align 4
   %mul25 = fmul float %7, %5
   store float %mul25, float* %arrayidx11, align 4
   %8 = add nsw i64 %indvars.iv, 4
-  %arrayidx31 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %8
-  %9 = load float* %arrayidx31, align 4
+  %arrayidx31 = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %8
+  %9 = load float, float* %arrayidx31, align 4
   %mul35 = fmul float %9, %7
   store float %mul35, float* %arrayidx21, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 5
-  %arrayidx41 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv.next
-  %10 = load float* %arrayidx41, align 4
+  %arrayidx41 = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %indvars.iv.next
+  %10 = load float, float* %arrayidx41, align 4
   %mul45 = fmul float %10, %9
   store float %mul45, float* %arrayidx31, align 4
   %11 = trunc i64 %indvars.iv.next to i32
@@ -232,3 +232,113 @@ for.body3:
 for.end:
   ret void
 }
+
+; Check vectorization of following code for double data type-
+;  c[0] = a[0]+b[0];
+;  c[1] = b[1]+a[1]; // swapped b[1] and a[1]
+
+; CHECK-LABEL: load_reorder_double
+; CHECK: load <2 x double>, <2 x double>*
+; CHECK: fadd <2 x double>
+define void @load_reorder_double(double* nocapture %c, double* noalias nocapture readonly %a, double* noalias nocapture readonly %b){
+  %1 = load double, double* %a
+  %2 = load double, double* %b
+  %3 = fadd double %1, %2
+  store double %3, double* %c
+  %4 = getelementptr inbounds double, double* %b, i64 1
+  %5 = load double, double* %4
+  %6 = getelementptr inbounds double, double* %a, i64 1
+  %7 = load double, double* %6
+  %8 = fadd double %5, %7
+  %9 = getelementptr inbounds double, double* %c, i64 1
+  store double %8, double* %9
+  ret void
+}
+
+; Check vectorization of following code for float data type-
+;  c[0] = a[0]+b[0];
+;  c[1] = b[1]+a[1]; // swapped b[1] and a[1]
+;  c[2] = a[2]+b[2];
+;  c[3] = a[3]+b[3];
+
+; CHECK-LABEL: load_reorder_float
+; CHECK: load <4 x float>, <4 x float>*
+; CHECK: fadd <4 x float>
+define void @load_reorder_float(float* nocapture %c, float* noalias nocapture readonly %a, float* noalias nocapture readonly %b){
+  %1 = load float, float* %a
+  %2 = load float, float* %b
+  %3 = fadd float %1, %2
+  store float %3, float* %c
+  %4 = getelementptr inbounds float, float* %b, i64 1
+  %5 = load float, float* %4
+  %6 = getelementptr inbounds float, float* %a, i64 1
+  %7 = load float, float* %6
+  %8 = fadd float %5, %7
+  %9 = getelementptr inbounds float, float* %c, i64 1
+  store float %8, float* %9
+  %10 = getelementptr inbounds float, float* %a, i64 2
+  %11 = load float, float* %10
+  %12 = getelementptr inbounds float, float* %b, i64 2
+  %13 = load float, float* %12
+  %14 = fadd float %11, %13
+  %15 = getelementptr inbounds float, float* %c, i64 2
+  store float %14, float* %15
+  %16 = getelementptr inbounds float, float* %a, i64 3
+  %17 = load float, float* %16
+  %18 = getelementptr inbounds float, float* %b, i64 3
+  %19 = load float, float* %18
+  %20 = fadd float %17, %19
+  %21 = getelementptr inbounds float, float* %c, i64 3
+  store float %20, float* %21
+  ret void
+}
+
+; Check we properly reorder the below code so that it gets vectorized optimally-
+; a[0] = (b[0]+c[0])+d[0];
+; a[1] = d[1]+(b[1]+c[1]);
+; a[2] = (b[2]+c[2])+d[2];
+; a[3] = (b[3]+c[3])+d[3];
+
+; CHECK-LABEL: opcode_reorder
+; CHECK: load <4 x float>, <4 x float>*
+; CHECK: fadd <4 x float>
+define void @opcode_reorder(float* noalias nocapture %a, float* noalias nocapture readonly %b, 
+                            float* noalias nocapture readonly %c,float* noalias nocapture readonly %d){
+  %1 = load float, float* %b
+  %2 = load float, float* %c
+  %3 = fadd float %1, %2
+  %4 = load float, float* %d
+  %5 = fadd float %3, %4
+  store float %5, float* %a
+  %6 = getelementptr inbounds float, float* %d, i64 1
+  %7 = load float, float* %6
+  %8 = getelementptr inbounds float, float* %b, i64 1
+  %9 = load float, float* %8
+  %10 = getelementptr inbounds float, float* %c, i64 1
+  %11 = load float, float* %10
+  %12 = fadd float %9, %11
+  %13 = fadd float %7, %12
+  %14 = getelementptr inbounds float, float* %a, i64 1
+  store float %13, float* %14
+  %15 = getelementptr inbounds float, float* %b, i64 2
+  %16 = load float, float* %15
+  %17 = getelementptr inbounds float, float* %c, i64 2
+  %18 = load float, float* %17
+  %19 = fadd float %16, %18
+  %20 = getelementptr inbounds float, float* %d, i64 2
+  %21 = load float, float* %20
+  %22 = fadd float %19, %21
+  %23 = getelementptr inbounds float, float* %a, i64 2
+  store float %22, float* %23
+  %24 = getelementptr inbounds float, float* %b, i64 3
+  %25 = load float, float* %24
+  %26 = getelementptr inbounds float, float* %c, i64 3
+  %27 = load float, float* %26
+  %28 = fadd float %25, %27
+  %29 = getelementptr inbounds float, float* %d, i64 3
+  %30 = load float, float* %29
+  %31 = fadd float %28, %30
+  %32 = getelementptr inbounds float, float* %a, i64 3
+  store float %31, float* %32
+  ret void
+}
diff --git a/test/Transforms/SLPVectorizer/X86/opt.ll b/test/Transforms/SLPVectorizer/X86/opt.ll
index 14137c11ee41..824e9992af03 100644
--- a/test/Transforms/SLPVectorizer/X86/opt.ll
+++ b/test/Transforms/SLPVectorizer/X86/opt.ll
@@ -15,16 +15,16 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 define void @test1(double* %a, double* %b, double* %c) {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   store double %mul, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/X86/ordering.ll b/test/Transforms/SLPVectorizer/X86/ordering.ll
index d2ecd4546ddb..0fa72c94c272 100644
--- a/test/Transforms/SLPVectorizer/X86/ordering.ll
+++ b/test/Transforms/SLPVectorizer/X86/ordering.ll
@@ -5,7 +5,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 define void @updateModelQPFrame(i32 %m_Bits) {
 entry:
-  %0 = load double* undef, align 8
+  %0 = load double, double* undef, align 8
   %mul = fmul double undef, %0
   %mul2 = fmul double undef, %mul
   %mul4 = fmul double %0, %mul2
diff --git a/test/Transforms/SLPVectorizer/X86/phi.ll b/test/Transforms/SLPVectorizer/X86/phi.ll
index 0c53b60f3df1..ef94467f509a 100644
--- a/test/Transforms/SLPVectorizer/X86/phi.ll
+++ b/test/Transforms/SLPVectorizer/X86/phi.ll
@@ -29,17 +29,17 @@ entry:
   br i1 %tobool, label %if.else, label %if.end
 
 if.else:                                          ; preds = %entry
-  %arrayidx = getelementptr inbounds double* %A, i64 10
-  %0 = load double* %arrayidx, align 8
-  %arrayidx1 = getelementptr inbounds double* %A, i64 11
-  %1 = load double* %arrayidx1, align 8
+  %arrayidx = getelementptr inbounds double, double* %A, i64 10
+  %0 = load double, double* %arrayidx, align 8
+  %arrayidx1 = getelementptr inbounds double, double* %A, i64 11
+  %1 = load double, double* %arrayidx1, align 8
   br label %if.end
 
 if.end:                                           ; preds = %entry, %if.else
   %A0.0 = phi double [ %0, %if.else ], [ 3.000000e+00, %entry ]
   %A1.0 = phi double [ %1, %if.else ], [ 5.000000e+00, %entry ]
   store double %A0.0, double* %A, align 8
-  %arrayidx3 = getelementptr inbounds double* %A, i64 1
+  %arrayidx3 = getelementptr inbounds double, double* %A, i64 1
   store double %A1.0, double* %arrayidx3, align 8
   ret i32 undef
 }
@@ -69,9 +69,9 @@ if.end:                                           ; preds = %entry, %if.else
 ;CHECK: ret
 define i32 @foo2(double* noalias nocapture %B, double* noalias nocapture %A, i32 %n, i32 %m) #0 {
 entry:
-  %arrayidx = getelementptr inbounds double* %A, i64 1
-  %0 = load double* %arrayidx, align 8
-  %1 = load double* %A, align 8
+  %arrayidx = getelementptr inbounds double, double* %A, i64 1
+  %0 = load double, double* %arrayidx, align 8
+  %1 = load double, double* %A, align 8
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
@@ -90,7 +90,7 @@ for.body:                                         ; preds = %for.body, %entry
 
 for.end:                                          ; preds = %for.body
   store double %add5, double* %B, align 8
-  %arrayidx7 = getelementptr inbounds double* %B, i64 1
+  %arrayidx7 = getelementptr inbounds double, double* %B, i64 1
   store double %add4, double* %arrayidx7, align 8
   ret i32 0
 }
@@ -123,15 +123,15 @@ for.end:                                          ; preds = %for.body
 
 define float @foo3(float* nocapture readonly %A) #0 {
 entry:
-  %0 = load float* %A, align 4
-  %arrayidx1 = getelementptr inbounds float* %A, i64 1
-  %1 = load float* %arrayidx1, align 4
-  %arrayidx2 = getelementptr inbounds float* %A, i64 2
-  %2 = load float* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds float* %A, i64 3
-  %3 = load float* %arrayidx3, align 4
-  %arrayidx4 = getelementptr inbounds float* %A, i64 4
-  %4 = load float* %arrayidx4, align 4
+  %0 = load float, float* %A, align 4
+  %arrayidx1 = getelementptr inbounds float, float* %A, i64 1
+  %1 = load float, float* %arrayidx1, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %A, i64 2
+  %2 = load float, float* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds float, float* %A, i64 3
+  %3 = load float, float* %arrayidx3, align 4
+  %arrayidx4 = getelementptr inbounds float, float* %A, i64 4
+  %4 = load float, float* %arrayidx4, align 4
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
@@ -148,18 +148,18 @@ for.body:                                         ; preds = %for.body, %entry
   %mul10 = fmul float %5, 8.000000e+00
   %add11 = fadd float %G.053, %mul10
   %7 = add nsw i64 %indvars.iv, 2
-  %arrayidx14 = getelementptr inbounds float* %A, i64 %7
-  %8 = load float* %arrayidx14, align 4
+  %arrayidx14 = getelementptr inbounds float, float* %A, i64 %7
+  %8 = load float, float* %arrayidx14, align 4
   %mul15 = fmul float %8, 9.000000e+00
   %add16 = fadd float %B.054, %mul15
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 3
-  %arrayidx19 = getelementptr inbounds float* %A, i64 %indvars.iv.next
-  %9 = load float* %arrayidx19, align 4
+  %arrayidx19 = getelementptr inbounds float, float* %A, i64 %indvars.iv.next
+  %9 = load float, float* %arrayidx19, align 4
   %mul20 = fmul float %9, 1.000000e+01
   %add21 = fadd float %Y.055, %mul20
   %10 = add nsw i64 %indvars.iv, 4
-  %arrayidx24 = getelementptr inbounds float* %A, i64 %10
-  %11 = load float* %arrayidx24, align 4
+  %arrayidx24 = getelementptr inbounds float, float* %A, i64 %10
+  %11 = load float, float* %arrayidx24, align 4
   %mul25 = fmul float %11, 1.100000e+01
   %add26 = fadd float %P.056, %mul25
   %12 = trunc i64 %indvars.iv.next to i32
@@ -215,22 +215,22 @@ define void @test(x86_fp80* %i1, x86_fp80* %i2, x86_fp80* %o) {
 ; We disable the vectorization of x86_fp80 for now. 
 
 entry:
-  %i1.0 = load x86_fp80* %i1, align 16
-  %i1.gep1 = getelementptr x86_fp80* %i1, i64 1
-  %i1.1 = load x86_fp80* %i1.gep1, align 16
-; CHECK: load x86_fp80*
-; CHECK: load x86_fp80*
+  %i1.0 = load x86_fp80, x86_fp80* %i1, align 16
+  %i1.gep1 = getelementptr x86_fp80, x86_fp80* %i1, i64 1
+  %i1.1 = load x86_fp80, x86_fp80* %i1.gep1, align 16
+; CHECK: load x86_fp80, x86_fp80*
+; CHECK: load x86_fp80, x86_fp80*
 ; CHECK-NOT: insertelement <2 x x86_fp80>
 ; CHECK-NOT: insertelement <2 x x86_fp80>
   br i1 undef, label %then, label %end
 
 then:
-  %i2.gep0 = getelementptr inbounds x86_fp80* %i2, i64 0
-  %i2.0 = load x86_fp80* %i2.gep0, align 16
-  %i2.gep1 = getelementptr inbounds x86_fp80* %i2, i64 1
-  %i2.1 = load x86_fp80* %i2.gep1, align 16
-; CHECK: load x86_fp80*
-; CHECK: load x86_fp80*
+  %i2.gep0 = getelementptr inbounds x86_fp80, x86_fp80* %i2, i64 0
+  %i2.0 = load x86_fp80, x86_fp80* %i2.gep0, align 16
+  %i2.gep1 = getelementptr inbounds x86_fp80, x86_fp80* %i2, i64 1
+  %i2.1 = load x86_fp80, x86_fp80* %i2.gep1, align 16
+; CHECK: load x86_fp80, x86_fp80*
+; CHECK: load x86_fp80, x86_fp80*
 ; CHECK-NOT: insertelement <2 x x86_fp80>
 ; CHECK-NOT: insertelement <2 x x86_fp80>
   br label %end
@@ -242,7 +242,7 @@ end:
 ; CHECK-NOT: extractelement <2 x x86_fp80>
 ; CHECK-NOT: extractelement <2 x x86_fp80>
   store x86_fp80 %phi0, x86_fp80* %o, align 16
-  %o.gep1 = getelementptr inbounds x86_fp80* %o, i64 1
+  %o.gep1 = getelementptr inbounds x86_fp80, x86_fp80* %o, i64 1
   store x86_fp80 %phi1, x86_fp80* %o.gep1, align 16
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/X86/phi3.ll b/test/Transforms/SLPVectorizer/X86/phi3.ll
index fd8d36137201..61628301aec7 100644
--- a/test/Transforms/SLPVectorizer/X86/phi3.ll
+++ b/test/Transforms/SLPVectorizer/X86/phi3.ll
@@ -12,7 +12,7 @@ declare %struct.GPar.0.16.26* @Rf_gpptr(...)
 define void @Rf_GReset() {
 entry:
   %sub = fsub double -0.000000e+00, undef
-  %0 = load double* @d, align 8
+  %0 = load double, double* @d, align 8
   %sub1 = fsub double -0.000000e+00, %0
   br i1 icmp eq (%struct.GPar.0.16.26* (...)* inttoptr (i64 115 to %struct.GPar.0.16.26* (...)*), %struct.GPar.0.16.26* (...)* @Rf_gpptr), label %if.then, label %if.end7
 
diff --git a/test/Transforms/SLPVectorizer/X86/phi_overalignedtype.ll b/test/Transforms/SLPVectorizer/X86/phi_overalignedtype.ll
index 520e6729de0c..fa08effcd648 100644
--- a/test/Transforms/SLPVectorizer/X86/phi_overalignedtype.ll
+++ b/test/Transforms/SLPVectorizer/X86/phi_overalignedtype.ll
@@ -12,22 +12,22 @@ define void @test(double* %i1, double* %i2, double* %o) {
 ; size is less than the alignment, and through various different GEP formations.
 
 entry:
-  %i1.0 = load double* %i1, align 16
-  %i1.gep1 = getelementptr double* %i1, i64 1
-  %i1.1 = load double* %i1.gep1, align 16
-; CHECK: load double*
-; CHECK: load double*
+  %i1.0 = load double, double* %i1, align 16
+  %i1.gep1 = getelementptr double, double* %i1, i64 1
+  %i1.1 = load double, double* %i1.gep1, align 16
+; CHECK: load double, double*
+; CHECK: load double, double*
 ; CHECK: insertelement <2 x double>
 ; CHECK: insertelement <2 x double>
   br i1 undef, label %then, label %end
 
 then:
-  %i2.gep0 = getelementptr inbounds double* %i2, i64 0
-  %i2.0 = load double* %i2.gep0, align 16
-  %i2.gep1 = getelementptr inbounds double* %i2, i64 1
-  %i2.1 = load double* %i2.gep1, align 16
-; CHECK: load double*
-; CHECK: load double*
+  %i2.gep0 = getelementptr inbounds double, double* %i2, i64 0
+  %i2.0 = load double, double* %i2.gep0, align 16
+  %i2.gep1 = getelementptr inbounds double, double* %i2, i64 1
+  %i2.1 = load double, double* %i2.gep1, align 16
+; CHECK: load double, double*
+; CHECK: load double, double*
 ; CHECK: insertelement <2 x double>
 ; CHECK: insertelement <2 x double>
   br label %end
@@ -39,7 +39,7 @@ end:
 ; CHECK: extractelement <2 x double>
 ; CHECK: extractelement <2 x double>
   store double %phi0, double* %o, align 16
-  %o.gep1 = getelementptr inbounds double* %o, i64 1
+  %o.gep1 = getelementptr inbounds double, double* %o, i64 1
   store double %phi1, double* %o.gep1, align 16
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/X86/powof2div.ll b/test/Transforms/SLPVectorizer/X86/powof2div.ll
index 7aa1efde6f06..a97b870f3f44 100644
--- a/test/Transforms/SLPVectorizer/X86/powof2div.ll
+++ b/test/Transforms/SLPVectorizer/X86/powof2div.ll
@@ -4,39 +4,39 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 ;CHECK-LABEL: @powof2div(
-;CHECK: load <4 x i32>*
+;CHECK: load <4 x i32>, <4 x i32>*
 ;CHECK: add nsw <4 x i32>
 ;CHECK: sdiv <4 x i32>
 define void @powof2div(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32* noalias nocapture readonly %c){
 entry:
-  %0 = load i32* %b, align 4
-  %1 = load i32* %c, align 4
+  %0 = load i32, i32* %b, align 4
+  %1 = load i32, i32* %c, align 4
   %add = add nsw i32 %1, %0
   %div = sdiv i32 %add, 2
   store i32 %div, i32* %a, align 4
-  %arrayidx3 = getelementptr inbounds i32* %b, i64 1
-  %2 = load i32* %arrayidx3, align 4
-  %arrayidx4 = getelementptr inbounds i32* %c, i64 1
-  %3 = load i32* %arrayidx4, align 4
+  %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 1
+  %2 = load i32, i32* %arrayidx3, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %c, i64 1
+  %3 = load i32, i32* %arrayidx4, align 4
   %add5 = add nsw i32 %3, %2
   %div6 = sdiv i32 %add5, 2
-  %arrayidx7 = getelementptr inbounds i32* %a, i64 1
+  %arrayidx7 = getelementptr inbounds i32, i32* %a, i64 1
   store i32 %div6, i32* %arrayidx7, align 4
-  %arrayidx8 = getelementptr inbounds i32* %b, i64 2
-  %4 = load i32* %arrayidx8, align 4
-  %arrayidx9 = getelementptr inbounds i32* %c, i64 2
-  %5 = load i32* %arrayidx9, align 4
+  %arrayidx8 = getelementptr inbounds i32, i32* %b, i64 2
+  %4 = load i32, i32* %arrayidx8, align 4
+  %arrayidx9 = getelementptr inbounds i32, i32* %c, i64 2
+  %5 = load i32, i32* %arrayidx9, align 4
   %add10 = add nsw i32 %5, %4
   %div11 = sdiv i32 %add10, 2
-  %arrayidx12 = getelementptr inbounds i32* %a, i64 2
+  %arrayidx12 = getelementptr inbounds i32, i32* %a, i64 2
   store i32 %div11, i32* %arrayidx12, align 4
-  %arrayidx13 = getelementptr inbounds i32* %b, i64 3
-  %6 = load i32* %arrayidx13, align 4
-  %arrayidx14 = getelementptr inbounds i32* %c, i64 3
-  %7 = load i32* %arrayidx14, align 4
+  %arrayidx13 = getelementptr inbounds i32, i32* %b, i64 3
+  %6 = load i32, i32* %arrayidx13, align 4
+  %arrayidx14 = getelementptr inbounds i32, i32* %c, i64 3
+  %7 = load i32, i32* %arrayidx14, align 4
   %add15 = add nsw i32 %7, %6
   %div16 = sdiv i32 %add15, 2
-  %arrayidx17 = getelementptr inbounds i32* %a, i64 3
+  %arrayidx17 = getelementptr inbounds i32, i32* %a, i64 3
   store i32 %div16, i32* %arrayidx17, align 4
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/X86/pr16628.ll b/test/Transforms/SLPVectorizer/X86/pr16628.ll
index 3f9d775eeeb6..06abe9127e6f 100644
--- a/test/Transforms/SLPVectorizer/X86/pr16628.ll
+++ b/test/Transforms/SLPVectorizer/X86/pr16628.ll
@@ -10,11 +10,11 @@ target triple = "x86_64-apple-macosx10.9.0"
 ; Function Attrs: nounwind ssp uwtable
 define void @f() {
 entry:
-  %call = tail call i32 (...)* @g()
-  %0 = load i32* @c, align 4
+  %call = tail call i32 (...) @g()
+  %0 = load i32, i32* @c, align 4
   %lnot = icmp eq i32 %0, 0
   %lnot.ext = zext i1 %lnot to i32
-  %1 = load i16* @a, align 2
+  %1 = load i16, i16* @a, align 2
   %lnot2 = icmp eq i16 %1, 0
   %lnot.ext3 = zext i1 %lnot2 to i32
   %or = or i32 %lnot.ext3, %lnot.ext
diff --git a/test/Transforms/SLPVectorizer/X86/pr16899.ll b/test/Transforms/SLPVectorizer/X86/pr16899.ll
index c642f3cfe1d4..0de14ec35856 100644
--- a/test/Transforms/SLPVectorizer/X86/pr16899.ll
+++ b/test/Transforms/SLPVectorizer/X86/pr16899.ll
@@ -7,10 +7,10 @@ target triple = "i386--netbsd"
 ; Function Attrs: noreturn nounwind readonly
 define i32 @fn1() #0 {
 entry:
-  %0 = load i32** @a, align 4, !tbaa !4
-  %1 = load i32* %0, align 4, !tbaa !5
-  %arrayidx1 = getelementptr inbounds i32* %0, i32 1
-  %2 = load i32* %arrayidx1, align 4, !tbaa !5
+  %0 = load i32*, i32** @a, align 4, !tbaa !4
+  %1 = load i32, i32* %0, align 4, !tbaa !5
+  %arrayidx1 = getelementptr inbounds i32, i32* %0, i32 1
+  %2 = load i32, i32* %arrayidx1, align 4, !tbaa !5
   br label %do.body
 
 do.body:                                          ; preds = %do.body, %entry
diff --git a/test/Transforms/SLPVectorizer/X86/pr19657.ll b/test/Transforms/SLPVectorizer/X86/pr19657.ll
index 93523089c28b..a687aec76103 100644
--- a/test/Transforms/SLPVectorizer/X86/pr19657.ll
+++ b/test/Transforms/SLPVectorizer/X86/pr19657.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
-;CHECK: load <2 x double>*
+;CHECK: load <2 x double>, <2 x double>*
 ;CHECK: fadd <2 x double>
 ;CHECK: store <2 x double>
 
@@ -11,61 +11,61 @@ target triple = "x86_64-unknown-linux-gnu"
 define void @foo(double* %x) #0 {
   %1 = alloca double*, align 8
   store double* %x, double** %1, align 8
-  %2 = load double** %1, align 8
-  %3 = getelementptr inbounds double* %2, i64 0
-  %4 = load double* %3, align 8
-  %5 = load double** %1, align 8
-  %6 = getelementptr inbounds double* %5, i64 0
-  %7 = load double* %6, align 8
+  %2 = load double*, double** %1, align 8
+  %3 = getelementptr inbounds double, double* %2, i64 0
+  %4 = load double, double* %3, align 8
+  %5 = load double*, double** %1, align 8
+  %6 = getelementptr inbounds double, double* %5, i64 0
+  %7 = load double, double* %6, align 8
   %8 = fadd double %4, %7
-  %9 = load double** %1, align 8
-  %10 = getelementptr inbounds double* %9, i64 0
-  %11 = load double* %10, align 8
+  %9 = load double*, double** %1, align 8
+  %10 = getelementptr inbounds double, double* %9, i64 0
+  %11 = load double, double* %10, align 8
   %12 = fadd double %8, %11
-  %13 = load double** %1, align 8
-  %14 = getelementptr inbounds double* %13, i64 0
+  %13 = load double*, double** %1, align 8
+  %14 = getelementptr inbounds double, double* %13, i64 0
   store double %12, double* %14, align 8
-  %15 = load double** %1, align 8
-  %16 = getelementptr inbounds double* %15, i64 1
-  %17 = load double* %16, align 8
-  %18 = load double** %1, align 8
-  %19 = getelementptr inbounds double* %18, i64 1
-  %20 = load double* %19, align 8
+  %15 = load double*, double** %1, align 8
+  %16 = getelementptr inbounds double, double* %15, i64 1
+  %17 = load double, double* %16, align 8
+  %18 = load double*, double** %1, align 8
+  %19 = getelementptr inbounds double, double* %18, i64 1
+  %20 = load double, double* %19, align 8
   %21 = fadd double %17, %20
-  %22 = load double** %1, align 8
-  %23 = getelementptr inbounds double* %22, i64 1
-  %24 = load double* %23, align 8
+  %22 = load double*, double** %1, align 8
+  %23 = getelementptr inbounds double, double* %22, i64 1
+  %24 = load double, double* %23, align 8
   %25 = fadd double %21, %24
-  %26 = load double** %1, align 8
-  %27 = getelementptr inbounds double* %26, i64 1
+  %26 = load double*, double** %1, align 8
+  %27 = getelementptr inbounds double, double* %26, i64 1
   store double %25, double* %27, align 8
-  %28 = load double** %1, align 8
-  %29 = getelementptr inbounds double* %28, i64 2
-  %30 = load double* %29, align 8
-  %31 = load double** %1, align 8
-  %32 = getelementptr inbounds double* %31, i64 2
-  %33 = load double* %32, align 8
+  %28 = load double*, double** %1, align 8
+  %29 = getelementptr inbounds double, double* %28, i64 2
+  %30 = load double, double* %29, align 8
+  %31 = load double*, double** %1, align 8
+  %32 = getelementptr inbounds double, double* %31, i64 2
+  %33 = load double, double* %32, align 8
   %34 = fadd double %30, %33
-  %35 = load double** %1, align 8
-  %36 = getelementptr inbounds double* %35, i64 2
-  %37 = load double* %36, align 8
+  %35 = load double*, double** %1, align 8
+  %36 = getelementptr inbounds double, double* %35, i64 2
+  %37 = load double, double* %36, align 8
   %38 = fadd double %34, %37
-  %39 = load double** %1, align 8
-  %40 = getelementptr inbounds double* %39, i64 2
+  %39 = load double*, double** %1, align 8
+  %40 = getelementptr inbounds double, double* %39, i64 2
   store double %38, double* %40, align 8
-  %41 = load double** %1, align 8
-  %42 = getelementptr inbounds double* %41, i64 3
-  %43 = load double* %42, align 8
-  %44 = load double** %1, align 8
-  %45 = getelementptr inbounds double* %44, i64 3
-  %46 = load double* %45, align 8
+  %41 = load double*, double** %1, align 8
+  %42 = getelementptr inbounds double, double* %41, i64 3
+  %43 = load double, double* %42, align 8
+  %44 = load double*, double** %1, align 8
+  %45 = getelementptr inbounds double, double* %44, i64 3
+  %46 = load double, double* %45, align 8
   %47 = fadd double %43, %46
-  %48 = load double** %1, align 8
-  %49 = getelementptr inbounds double* %48, i64 3
-  %50 = load double* %49, align 8
+  %48 = load double*, double** %1, align 8
+  %49 = getelementptr inbounds double, double* %48, i64 3
+  %50 = load double, double* %49, align 8
   %51 = fadd double %47, %50
-  %52 = load double** %1, align 8
-  %53 = getelementptr inbounds double* %52, i64 3
+  %52 = load double*, double** %1, align 8
+  %53 = getelementptr inbounds double, double* %52, i64 3
   store double %51, double* %53, align 8
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/X86/propagate_ir_flags.ll b/test/Transforms/SLPVectorizer/X86/propagate_ir_flags.ll
index 3843ef7f62c7..a3b0c8ff0279 100644
--- a/test/Transforms/SLPVectorizer/X86/propagate_ir_flags.ll
+++ b/test/Transforms/SLPVectorizer/X86/propagate_ir_flags.ll
@@ -10,15 +10,15 @@ target triple = "x86_64-unknown-unknown"
 ; CHECK-LABEL: @exact(
 ; CHECK: lshr exact <4 x i32>
 define void @exact(i32* %x) {
-  %idx1 = getelementptr inbounds i32* %x, i64 0
-  %idx2 = getelementptr inbounds i32* %x, i64 1
-  %idx3 = getelementptr inbounds i32* %x, i64 2
-  %idx4 = getelementptr inbounds i32* %x, i64 3
+  %idx1 = getelementptr inbounds i32, i32* %x, i64 0
+  %idx2 = getelementptr inbounds i32, i32* %x, i64 1
+  %idx3 = getelementptr inbounds i32, i32* %x, i64 2
+  %idx4 = getelementptr inbounds i32, i32* %x, i64 3
 
-  %load1 = load i32* %idx1, align 4
-  %load2 = load i32* %idx2, align 4
-  %load3 = load i32* %idx3, align 4
-  %load4 = load i32* %idx4, align 4
+  %load1 = load i32, i32* %idx1, align 4
+  %load2 = load i32, i32* %idx2, align 4
+  %load3 = load i32, i32* %idx3, align 4
+  %load4 = load i32, i32* %idx4, align 4
 
   %op1 = lshr exact i32 %load1, 1
   %op2 = lshr exact i32 %load2, 1
@@ -36,15 +36,15 @@ define void @exact(i32* %x) {
 ; CHECK-LABEL: @not_exact(
 ; CHECK: lshr <4 x i32>
 define void @not_exact(i32* %x) {
-  %idx1 = getelementptr inbounds i32* %x, i64 0
-  %idx2 = getelementptr inbounds i32* %x, i64 1
-  %idx3 = getelementptr inbounds i32* %x, i64 2
-  %idx4 = getelementptr inbounds i32* %x, i64 3
+  %idx1 = getelementptr inbounds i32, i32* %x, i64 0
+  %idx2 = getelementptr inbounds i32, i32* %x, i64 1
+  %idx3 = getelementptr inbounds i32, i32* %x, i64 2
+  %idx4 = getelementptr inbounds i32, i32* %x, i64 3
 
-  %load1 = load i32* %idx1, align 4
-  %load2 = load i32* %idx2, align 4
-  %load3 = load i32* %idx3, align 4
-  %load4 = load i32* %idx4, align 4
+  %load1 = load i32, i32* %idx1, align 4
+  %load2 = load i32, i32* %idx2, align 4
+  %load3 = load i32, i32* %idx3, align 4
+  %load4 = load i32, i32* %idx4, align 4
 
   %op1 = lshr exact i32 %load1, 1
   %op2 = lshr i32 %load2, 1
@@ -62,15 +62,15 @@ define void @not_exact(i32* %x) {
 ; CHECK-LABEL: @nsw(
 ; CHECK: add nsw <4 x i32>
 define void @nsw(i32* %x) {
-  %idx1 = getelementptr inbounds i32* %x, i64 0
-  %idx2 = getelementptr inbounds i32* %x, i64 1
-  %idx3 = getelementptr inbounds i32* %x, i64 2
-  %idx4 = getelementptr inbounds i32* %x, i64 3
+  %idx1 = getelementptr inbounds i32, i32* %x, i64 0
+  %idx2 = getelementptr inbounds i32, i32* %x, i64 1
+  %idx3 = getelementptr inbounds i32, i32* %x, i64 2
+  %idx4 = getelementptr inbounds i32, i32* %x, i64 3
 
-  %load1 = load i32* %idx1, align 4
-  %load2 = load i32* %idx2, align 4
-  %load3 = load i32* %idx3, align 4
-  %load4 = load i32* %idx4, align 4
+  %load1 = load i32, i32* %idx1, align 4
+  %load2 = load i32, i32* %idx2, align 4
+  %load3 = load i32, i32* %idx3, align 4
+  %load4 = load i32, i32* %idx4, align 4
 
   %op1 = add nsw i32 %load1, 1
   %op2 = add nsw i32 %load2, 1
@@ -88,15 +88,15 @@ define void @nsw(i32* %x) {
 ; CHECK-LABEL: @not_nsw(
 ; CHECK: add <4 x i32>
 define void @not_nsw(i32* %x) {
-  %idx1 = getelementptr inbounds i32* %x, i64 0
-  %idx2 = getelementptr inbounds i32* %x, i64 1
-  %idx3 = getelementptr inbounds i32* %x, i64 2
-  %idx4 = getelementptr inbounds i32* %x, i64 3
+  %idx1 = getelementptr inbounds i32, i32* %x, i64 0
+  %idx2 = getelementptr inbounds i32, i32* %x, i64 1
+  %idx3 = getelementptr inbounds i32, i32* %x, i64 2
+  %idx4 = getelementptr inbounds i32, i32* %x, i64 3
 
-  %load1 = load i32* %idx1, align 4
-  %load2 = load i32* %idx2, align 4
-  %load3 = load i32* %idx3, align 4
-  %load4 = load i32* %idx4, align 4
+  %load1 = load i32, i32* %idx1, align 4
+  %load2 = load i32, i32* %idx2, align 4
+  %load3 = load i32, i32* %idx3, align 4
+  %load4 = load i32, i32* %idx4, align 4
 
   %op1 = add nsw i32 %load1, 1
   %op2 = add nsw i32 %load2, 1
@@ -114,15 +114,15 @@ define void @not_nsw(i32* %x) {
 ; CHECK-LABEL: @nuw(
 ; CHECK: add nuw <4 x i32>
 define void @nuw(i32* %x) {
-  %idx1 = getelementptr inbounds i32* %x, i64 0
-  %idx2 = getelementptr inbounds i32* %x, i64 1
-  %idx3 = getelementptr inbounds i32* %x, i64 2
-  %idx4 = getelementptr inbounds i32* %x, i64 3
+  %idx1 = getelementptr inbounds i32, i32* %x, i64 0
+  %idx2 = getelementptr inbounds i32, i32* %x, i64 1
+  %idx3 = getelementptr inbounds i32, i32* %x, i64 2
+  %idx4 = getelementptr inbounds i32, i32* %x, i64 3
 
-  %load1 = load i32* %idx1, align 4
-  %load2 = load i32* %idx2, align 4
-  %load3 = load i32* %idx3, align 4
-  %load4 = load i32* %idx4, align 4
+  %load1 = load i32, i32* %idx1, align 4
+  %load2 = load i32, i32* %idx2, align 4
+  %load3 = load i32, i32* %idx3, align 4
+  %load4 = load i32, i32* %idx4, align 4
 
   %op1 = add nuw i32 %load1, 1
   %op2 = add nuw i32 %load2, 1
@@ -140,15 +140,15 @@ define void @nuw(i32* %x) {
 ; CHECK-LABEL: @not_nuw(
 ; CHECK: add <4 x i32>
 define void @not_nuw(i32* %x) {
-  %idx1 = getelementptr inbounds i32* %x, i64 0
-  %idx2 = getelementptr inbounds i32* %x, i64 1
-  %idx3 = getelementptr inbounds i32* %x, i64 2
-  %idx4 = getelementptr inbounds i32* %x, i64 3
+  %idx1 = getelementptr inbounds i32, i32* %x, i64 0
+  %idx2 = getelementptr inbounds i32, i32* %x, i64 1
+  %idx3 = getelementptr inbounds i32, i32* %x, i64 2
+  %idx4 = getelementptr inbounds i32, i32* %x, i64 3
 
-  %load1 = load i32* %idx1, align 4
-  %load2 = load i32* %idx2, align 4
-  %load3 = load i32* %idx3, align 4
-  %load4 = load i32* %idx4, align 4
+  %load1 = load i32, i32* %idx1, align 4
+  %load2 = load i32, i32* %idx2, align 4
+  %load3 = load i32, i32* %idx3, align 4
+  %load4 = load i32, i32* %idx4, align 4
 
   %op1 = add nuw i32 %load1, 1
   %op2 = add i32 %load2, 1
@@ -166,15 +166,15 @@ define void @not_nuw(i32* %x) {
 ; CHECK-LABEL: @nnan(
 ; CHECK: fadd nnan <4 x float>
 define void @nnan(float* %x) {
-  %idx1 = getelementptr inbounds float* %x, i64 0
-  %idx2 = getelementptr inbounds float* %x, i64 1
-  %idx3 = getelementptr inbounds float* %x, i64 2
-  %idx4 = getelementptr inbounds float* %x, i64 3
+  %idx1 = getelementptr inbounds float, float* %x, i64 0
+  %idx2 = getelementptr inbounds float, float* %x, i64 1
+  %idx3 = getelementptr inbounds float, float* %x, i64 2
+  %idx4 = getelementptr inbounds float, float* %x, i64 3
 
-  %load1 = load float* %idx1, align 4
-  %load2 = load float* %idx2, align 4
-  %load3 = load float* %idx3, align 4
-  %load4 = load float* %idx4, align 4
+  %load1 = load float, float* %idx1, align 4
+  %load2 = load float, float* %idx2, align 4
+  %load3 = load float, float* %idx3, align 4
+  %load4 = load float, float* %idx4, align 4
 
   %op1 = fadd fast nnan float %load1, 1.0
   %op2 = fadd nnan ninf float %load2, 1.0
@@ -192,15 +192,15 @@ define void @nnan(float* %x) {
 ; CHECK-LABEL: @not_nnan(
 ; CHECK: fadd <4 x float>
 define void @not_nnan(float* %x) {
-  %idx1 = getelementptr inbounds float* %x, i64 0
-  %idx2 = getelementptr inbounds float* %x, i64 1
-  %idx3 = getelementptr inbounds float* %x, i64 2
-  %idx4 = getelementptr inbounds float* %x, i64 3
+  %idx1 = getelementptr inbounds float, float* %x, i64 0
+  %idx2 = getelementptr inbounds float, float* %x, i64 1
+  %idx3 = getelementptr inbounds float, float* %x, i64 2
+  %idx4 = getelementptr inbounds float, float* %x, i64 3
 
-  %load1 = load float* %idx1, align 4
-  %load2 = load float* %idx2, align 4
-  %load3 = load float* %idx3, align 4
-  %load4 = load float* %idx4, align 4
+  %load1 = load float, float* %idx1, align 4
+  %load2 = load float, float* %idx2, align 4
+  %load3 = load float, float* %idx3, align 4
+  %load4 = load float, float* %idx4, align 4
 
   %op1 = fadd nnan float %load1, 1.0
   %op2 = fadd ninf float %load2, 1.0
@@ -218,15 +218,15 @@ define void @not_nnan(float* %x) {
 ; CHECK-LABEL: @only_fast(
 ; CHECK: fadd fast <4 x float>
 define void @only_fast(float* %x) {
-  %idx1 = getelementptr inbounds float* %x, i64 0
-  %idx2 = getelementptr inbounds float* %x, i64 1
-  %idx3 = getelementptr inbounds float* %x, i64 2
-  %idx4 = getelementptr inbounds float* %x, i64 3
+  %idx1 = getelementptr inbounds float, float* %x, i64 0
+  %idx2 = getelementptr inbounds float, float* %x, i64 1
+  %idx3 = getelementptr inbounds float, float* %x, i64 2
+  %idx4 = getelementptr inbounds float, float* %x, i64 3
 
-  %load1 = load float* %idx1, align 4
-  %load2 = load float* %idx2, align 4
-  %load3 = load float* %idx3, align 4
-  %load4 = load float* %idx4, align 4
+  %load1 = load float, float* %idx1, align 4
+  %load2 = load float, float* %idx2, align 4
+  %load3 = load float, float* %idx3, align 4
+  %load4 = load float, float* %idx4, align 4
 
   %op1 = fadd fast nnan float %load1, 1.0
   %op2 = fadd fast nnan ninf float %load2, 1.0
@@ -244,15 +244,15 @@ define void @only_fast(float* %x) {
 ; CHECK-LABEL: @only_arcp(
 ; CHECK: fadd arcp <4 x float>
 define void @only_arcp(float* %x) {
-  %idx1 = getelementptr inbounds float* %x, i64 0
-  %idx2 = getelementptr inbounds float* %x, i64 1
-  %idx3 = getelementptr inbounds float* %x, i64 2
-  %idx4 = getelementptr inbounds float* %x, i64 3
+  %idx1 = getelementptr inbounds float, float* %x, i64 0
+  %idx2 = getelementptr inbounds float, float* %x, i64 1
+  %idx3 = getelementptr inbounds float, float* %x, i64 2
+  %idx4 = getelementptr inbounds float, float* %x, i64 3
 
-  %load1 = load float* %idx1, align 4
-  %load2 = load float* %idx2, align 4
-  %load3 = load float* %idx3, align 4
-  %load4 = load float* %idx4, align 4
+  %load1 = load float, float* %idx1, align 4
+  %load2 = load float, float* %idx2, align 4
+  %load3 = load float, float* %idx3, align 4
+  %load4 = load float, float* %idx4, align 4
 
   %op1 = fadd fast float %load1, 1.0
   %op2 = fadd fast float %load2, 1.0
@@ -271,15 +271,15 @@ define void @only_arcp(float* %x) {
 ; CHECK: add nsw <4 x i32>
 ; CHECK: sub nsw <4 x i32>
 define void @addsub_all_nsw(i32* %x) {
-  %idx1 = getelementptr inbounds i32* %x, i64 0
-  %idx2 = getelementptr inbounds i32* %x, i64 1
-  %idx3 = getelementptr inbounds i32* %x, i64 2
-  %idx4 = getelementptr inbounds i32* %x, i64 3
+  %idx1 = getelementptr inbounds i32, i32* %x, i64 0
+  %idx2 = getelementptr inbounds i32, i32* %x, i64 1
+  %idx3 = getelementptr inbounds i32, i32* %x, i64 2
+  %idx4 = getelementptr inbounds i32, i32* %x, i64 3
 
-  %load1 = load i32* %idx1, align 4
-  %load2 = load i32* %idx2, align 4
-  %load3 = load i32* %idx3, align 4
-  %load4 = load i32* %idx4, align 4
+  %load1 = load i32, i32* %idx1, align 4
+  %load2 = load i32, i32* %idx2, align 4
+  %load3 = load i32, i32* %idx3, align 4
+  %load4 = load i32, i32* %idx4, align 4
 
   %op1 = add nsw i32 %load1, 1
   %op2 = sub nsw i32 %load2, 1
@@ -298,15 +298,15 @@ define void @addsub_all_nsw(i32* %x) {
 ; CHECK: add nsw <4 x i32>
 ; CHECK: sub <4 x i32>
 define void @addsub_some_nsw(i32* %x) {
-  %idx1 = getelementptr inbounds i32* %x, i64 0
-  %idx2 = getelementptr inbounds i32* %x, i64 1
-  %idx3 = getelementptr inbounds i32* %x, i64 2
-  %idx4 = getelementptr inbounds i32* %x, i64 3
+  %idx1 = getelementptr inbounds i32, i32* %x, i64 0
+  %idx2 = getelementptr inbounds i32, i32* %x, i64 1
+  %idx3 = getelementptr inbounds i32, i32* %x, i64 2
+  %idx4 = getelementptr inbounds i32, i32* %x, i64 3
 
-  %load1 = load i32* %idx1, align 4
-  %load2 = load i32* %idx2, align 4
-  %load3 = load i32* %idx3, align 4
-  %load4 = load i32* %idx4, align 4
+  %load1 = load i32, i32* %idx1, align 4
+  %load2 = load i32, i32* %idx2, align 4
+  %load3 = load i32, i32* %idx3, align 4
+  %load4 = load i32, i32* %idx4, align 4
 
   %op1 = add nsw i32 %load1, 1
   %op2 = sub nsw i32 %load2, 1
@@ -325,15 +325,15 @@ define void @addsub_some_nsw(i32* %x) {
 ; CHECK: add <4 x i32>
 ; CHECK: sub <4 x i32>
 define void @addsub_no_nsw(i32* %x) {
-  %idx1 = getelementptr inbounds i32* %x, i64 0
-  %idx2 = getelementptr inbounds i32* %x, i64 1
-  %idx3 = getelementptr inbounds i32* %x, i64 2
-  %idx4 = getelementptr inbounds i32* %x, i64 3
-
-  %load1 = load i32* %idx1, align 4
-  %load2 = load i32* %idx2, align 4
-  %load3 = load i32* %idx3, align 4
-  %load4 = load i32* %idx4, align 4
+  %idx1 = getelementptr inbounds i32, i32* %x, i64 0
+  %idx2 = getelementptr inbounds i32, i32* %x, i64 1
+  %idx3 = getelementptr inbounds i32, i32* %x, i64 2
+  %idx4 = getelementptr inbounds i32, i32* %x, i64 3
+
+  %load1 = load i32, i32* %idx1, align 4
+  %load2 = load i32, i32* %idx2, align 4
+  %load3 = load i32, i32* %idx3, align 4
+  %load4 = load i32, i32* %idx4, align 4
 
   %op1 = add i32 %load1, 1
   %op2 = sub nsw i32 %load2, 1
diff --git a/test/Transforms/SLPVectorizer/X86/reduction.ll b/test/Transforms/SLPVectorizer/X86/reduction.ll
index 70b7c3a0b998..4c5f1266336b 100644
--- a/test/Transforms/SLPVectorizer/X86/reduction.ll
+++ b/test/Transforms/SLPVectorizer/X86/reduction.ll
@@ -23,12 +23,12 @@ for.body:                                         ; preds = %entry, %for.body
   %i.015 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
   %sum.014 = phi double [ %add6, %for.body ], [ 0.000000e+00, %entry ]
   %mul = shl nsw i32 %i.015, 1
-  %arrayidx = getelementptr inbounds double* %A, i32 %mul
-  %0 = load double* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds double, double* %A, i32 %mul
+  %0 = load double, double* %arrayidx, align 4
   %mul1 = fmul double %0, 7.000000e+00
   %add12 = or i32 %mul, 1
-  %arrayidx3 = getelementptr inbounds double* %A, i32 %add12
-  %1 = load double* %arrayidx3, align 4
+  %arrayidx3 = getelementptr inbounds double, double* %A, i32 %add12
+  %1 = load double, double* %arrayidx3, align 4
   %mul4 = fmul double %1, 7.000000e+00
   %add5 = fadd double %mul1, %mul4
   %add6 = fadd double %sum.014, %add5
diff --git a/test/Transforms/SLPVectorizer/X86/reduction2.ll b/test/Transforms/SLPVectorizer/X86/reduction2.ll
index f21e86c5646c..507a61aa16f4 100644
--- a/test/Transforms/SLPVectorizer/X86/reduction2.ll
+++ b/test/Transforms/SLPVectorizer/X86/reduction2.ll
@@ -13,13 +13,13 @@ define double @foo(double* nocapture %D) {
   %i.02 = phi i32 [ 0, %0 ], [ %10, %1 ]
   %sum.01 = phi double [ 0.000000e+00, %0 ], [ %9, %1 ]
   %2 = shl nsw i32 %i.02, 1
-  %3 = getelementptr inbounds double* %D, i32 %2
-  %4 = load double* %3, align 4
+  %3 = getelementptr inbounds double, double* %D, i32 %2
+  %4 = load double, double* %3, align 4
   %A4 = fmul double %4, %4
   %A42 = fmul double %A4, %A4
   %5 = or i32 %2, 1
-  %6 = getelementptr inbounds double* %D, i32 %5
-  %7 = load double* %6, align 4
+  %6 = getelementptr inbounds double, double* %D, i32 %5
+  %7 = load double, double* %6, align 4
   %A7 = fmul double %7, %7
   %A72 = fmul double %A7, %A7
   %8 = fadd double %A42, %A72
diff --git a/test/Transforms/SLPVectorizer/X86/return.ll b/test/Transforms/SLPVectorizer/X86/return.ll
index 1a81c235bdfb..e2b263718e02 100644
--- a/test/Transforms/SLPVectorizer/X86/return.ll
+++ b/test/Transforms/SLPVectorizer/X86/return.ll
@@ -13,17 +13,17 @@ target triple = "x86_64--linux-gnu"
 ; }
 
 ; CHECK-LABEL: @return1
-; CHECK: %0 = load <2 x double>*
-; CHECK: %1 = load <2 x double>*
+; CHECK: %0 = load <2 x double>, <2 x double>*
+; CHECK: %1 = load <2 x double>, <2 x double>*
 ; CHECK: %2 = fadd <2 x double>
 
 define double @return1() {
 entry:
-  %a0 = load double* getelementptr inbounds ([4 x double]* @a, i32 0, i32 0), align 8
-  %b0 = load double* getelementptr inbounds ([4 x double]* @b, i32 0, i32 0), align 8
+  %a0 = load double, double* getelementptr inbounds ([4 x double], [4 x double]* @a, i32 0, i32 0), align 8
+  %b0 = load double, double* getelementptr inbounds ([4 x double], [4 x double]* @b, i32 0, i32 0), align 8
   %add0 = fadd double %a0, %b0
-  %a1 = load double* getelementptr inbounds ([4 x double]* @a, i32 0, i32 1), align 8
-  %b1 = load double* getelementptr inbounds ([4 x double]* @b, i32 0, i32 1), align 8
+  %a1 = load double, double* getelementptr inbounds ([4 x double], [4 x double]* @a, i32 0, i32 1), align 8
+  %b1 = load double, double* getelementptr inbounds ([4 x double], [4 x double]* @b, i32 0, i32 1), align 8
   %add1 = fadd double %a1, %b1
   %add2 = fadd double %add0, %add1
   ret double %add2
@@ -34,20 +34,20 @@ entry:
 ; }
 
 ; CHECK-LABEL: @return2
-; CHECK: %1 = load <2 x double>*
-; CHECK: %3 = load <2 x double>* %2
+; CHECK: %1 = load <2 x double>, <2 x double>*
+; CHECK: %3 = load <2 x double>, <2 x double>* %2
 ; CHECK: %4 = fadd <2 x double> %1, %3
 
 define double @return2(double* nocapture readonly %x) {
 entry:
-  %x0 = load double* %x, align 4
-  %arrayidx1 = getelementptr inbounds double* %x, i32 2
-  %x2 = load double* %arrayidx1, align 4
+  %x0 = load double, double* %x, align 4
+  %arrayidx1 = getelementptr inbounds double, double* %x, i32 2
+  %x2 = load double, double* %arrayidx1, align 4
   %add3 = fadd double %x0, %x2
-  %arrayidx2 = getelementptr inbounds double* %x, i32 1
-  %x1 = load double* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds double* %x, i32 3
-  %x3 = load double* %arrayidx3, align 4
+  %arrayidx2 = getelementptr inbounds double, double* %x, i32 1
+  %x1 = load double, double* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds double, double* %x, i32 3
+  %x3 = load double, double* %arrayidx3, align 4
   %add4 = fadd double %x1, %x3
   %add5 = fadd double %add3, %add4
   ret double %add5
diff --git a/test/Transforms/SLPVectorizer/X86/rgb_phi.ll b/test/Transforms/SLPVectorizer/X86/rgb_phi.ll
index 6aea5d3c6f6b..0bdb7dab1726 100644
--- a/test/Transforms/SLPVectorizer/X86/rgb_phi.ll
+++ b/test/Transforms/SLPVectorizer/X86/rgb_phi.ll
@@ -33,11 +33,11 @@ target triple = "i386-apple-macosx10.9.0"
 
 define float @foo(float* nocapture readonly %A) {
 entry:
-  %0 = load float* %A, align 4
-  %arrayidx1 = getelementptr inbounds float* %A, i64 1
-  %1 = load float* %arrayidx1, align 4
-  %arrayidx2 = getelementptr inbounds float* %A, i64 2
-  %2 = load float* %arrayidx2, align 4
+  %0 = load float, float* %A, align 4
+  %arrayidx1 = getelementptr inbounds float, float* %A, i64 1
+  %1 = load float, float* %arrayidx1, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %A, i64 2
+  %2 = load float, float* %arrayidx2, align 4
   br label %for.body
 
 for.body:                                         ; preds = %for.body.for.body_crit_edge, %entry
@@ -49,13 +49,13 @@ for.body:                                         ; preds = %for.body.for.body_c
   %mul = fmul float %3, 7.000000e+00
   %add4 = fadd float %R.030, %mul
   %4 = add nsw i64 %indvars.iv, 1
-  %arrayidx7 = getelementptr inbounds float* %A, i64 %4
-  %5 = load float* %arrayidx7, align 4
+  %arrayidx7 = getelementptr inbounds float, float* %A, i64 %4
+  %5 = load float, float* %arrayidx7, align 4
   %mul8 = fmul float %5, 8.000000e+00
   %add9 = fadd float %G.031, %mul8
   %6 = add nsw i64 %indvars.iv, 2
-  %arrayidx12 = getelementptr inbounds float* %A, i64 %6
-  %7 = load float* %arrayidx12, align 4
+  %arrayidx12 = getelementptr inbounds float, float* %A, i64 %6
+  %7 = load float, float* %arrayidx12, align 4
   %mul13 = fmul float %7, 9.000000e+00
   %add14 = fadd float %B.032, %mul13
   %indvars.iv.next = add i64 %indvars.iv, 3
@@ -64,8 +64,8 @@ for.body:                                         ; preds = %for.body.for.body_c
   br i1 %cmp, label %for.body.for.body_crit_edge, label %for.end
 
 for.body.for.body_crit_edge:                      ; preds = %for.body
-  %arrayidx3.phi.trans.insert = getelementptr inbounds float* %A, i64 %indvars.iv.next
-  %.pre = load float* %arrayidx3.phi.trans.insert, align 4
+  %arrayidx3.phi.trans.insert = getelementptr inbounds float, float* %A, i64 %indvars.iv.next
+  %.pre = load float, float* %arrayidx3.phi.trans.insert, align 4
   br label %for.body
 
 for.end:                                          ; preds = %for.body
diff --git a/test/Transforms/SLPVectorizer/X86/saxpy.ll b/test/Transforms/SLPVectorizer/X86/saxpy.ll
index 4b39d46f89db..a9ca093c0cdf 100644
--- a/test/Transforms/SLPVectorizer/X86/saxpy.ll
+++ b/test/Transforms/SLPVectorizer/X86/saxpy.ll
@@ -9,35 +9,35 @@ target triple = "x86_64-apple-macosx10.8.0"
 ;CHECK: ret
 
 define void @SAXPY(i32* noalias nocapture %x, i32* noalias nocapture %y, i32 %a, i64 %i) {
-  %1 = getelementptr inbounds i32* %x, i64 %i
-  %2 = load i32* %1, align 4
+  %1 = getelementptr inbounds i32, i32* %x, i64 %i
+  %2 = load i32, i32* %1, align 4
   %3 = mul nsw i32 %2, %a
-  %4 = getelementptr inbounds i32* %y, i64 %i
-  %5 = load i32* %4, align 4
+  %4 = getelementptr inbounds i32, i32* %y, i64 %i
+  %5 = load i32, i32* %4, align 4
   %6 = add nsw i32 %3, %5
   store i32 %6, i32* %1, align 4
   %7 = add i64 %i, 1
-  %8 = getelementptr inbounds i32* %x, i64 %7
-  %9 = load i32* %8, align 4
+  %8 = getelementptr inbounds i32, i32* %x, i64 %7
+  %9 = load i32, i32* %8, align 4
   %10 = mul nsw i32 %9, %a
-  %11 = getelementptr inbounds i32* %y, i64 %7
-  %12 = load i32* %11, align 4
+  %11 = getelementptr inbounds i32, i32* %y, i64 %7
+  %12 = load i32, i32* %11, align 4
   %13 = add nsw i32 %10, %12
   store i32 %13, i32* %8, align 4
   %14 = add i64 %i, 2
-  %15 = getelementptr inbounds i32* %x, i64 %14
-  %16 = load i32* %15, align 4
+  %15 = getelementptr inbounds i32, i32* %x, i64 %14
+  %16 = load i32, i32* %15, align 4
   %17 = mul nsw i32 %16, %a
-  %18 = getelementptr inbounds i32* %y, i64 %14
-  %19 = load i32* %18, align 4
+  %18 = getelementptr inbounds i32, i32* %y, i64 %14
+  %19 = load i32, i32* %18, align 4
   %20 = add nsw i32 %17, %19
   store i32 %20, i32* %15, align 4
   %21 = add i64 %i, 3
-  %22 = getelementptr inbounds i32* %x, i64 %21
-  %23 = load i32* %22, align 4
+  %22 = getelementptr inbounds i32, i32* %x, i64 %21
+  %23 = load i32, i32* %22, align 4
   %24 = mul nsw i32 %23, %a
-  %25 = getelementptr inbounds i32* %y, i64 %21
-  %26 = load i32* %25, align 4
+  %25 = getelementptr inbounds i32, i32* %y, i64 %21
+  %26 = load i32, i32* %25, align 4
   %27 = add nsw i32 %24, %26
   store i32 %27, i32* %22, align 4
   ret void
@@ -46,15 +46,15 @@ define void @SAXPY(i32* noalias nocapture %x, i32* noalias nocapture %y, i32 %a,
 ; Make sure we don't crash on this one.
 define void @SAXPY_crash(i32* noalias nocapture %x, i32* noalias nocapture %y, i64 %i) {
   %1 = add i64 %i, 1
-  %2 = getelementptr inbounds i32* %x, i64 %1
-  %3 = getelementptr inbounds i32* %y, i64 %1
-  %4 = load i32* %3, align 4
+  %2 = getelementptr inbounds i32, i32* %x, i64 %1
+  %3 = getelementptr inbounds i32, i32* %y, i64 %1
+  %4 = load i32, i32* %3, align 4
   %5 = add nsw i32 undef, %4
   store i32 %5, i32* %2, align 4
   %6 = add i64 %i, 2
-  %7 = getelementptr inbounds i32* %x, i64 %6
-  %8 = getelementptr inbounds i32* %y, i64 %6
-  %9 = load i32* %8, align 4
+  %7 = getelementptr inbounds i32, i32* %x, i64 %6
+  %8 = getelementptr inbounds i32, i32* %y, i64 %6
+  %9 = load i32, i32* %8, align 4
   %10 = add nsw i32 undef, %9
   store i32 %10, i32* %7, align 4
   ret void
diff --git a/test/Transforms/SLPVectorizer/X86/scheduling.ll b/test/Transforms/SLPVectorizer/X86/scheduling.ll
index 3b3bd804e057..33bdc6a6b04a 100644
--- a/test/Transforms/SLPVectorizer/X86/scheduling.ll
+++ b/test/Transforms/SLPVectorizer/X86/scheduling.ll
@@ -24,43 +24,43 @@ for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %a.088 = phi i32 [ 0, %entry ], [ %add52, %for.body ]
   %1 = shl i64 %indvars.iv, 3
-  %arrayidx = getelementptr inbounds i32* %diff, i64 %1
-  %2 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %diff, i64 %1
+  %2 = load i32, i32* %arrayidx, align 4
   %3 = or i64 %1, 4
-  %arrayidx2 = getelementptr inbounds i32* %diff, i64 %3
-  %4 = load i32* %arrayidx2, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %diff, i64 %3
+  %4 = load i32, i32* %arrayidx2, align 4
   %add3 = add nsw i32 %4, %2
-  %arrayidx6 = getelementptr inbounds [8 x [8 x i32]]* %m2, i64 0, i64 %indvars.iv, i64 0
+  %arrayidx6 = getelementptr inbounds [8 x [8 x i32]], [8 x [8 x i32]]* %m2, i64 0, i64 %indvars.iv, i64 0
   store i32 %add3, i32* %arrayidx6, align 16
   %add10 = add nsw i32 %add3, %a.088
   %5 = or i64 %1, 1
-  %arrayidx13 = getelementptr inbounds i32* %diff, i64 %5
-  %6 = load i32* %arrayidx13, align 4
+  %arrayidx13 = getelementptr inbounds i32, i32* %diff, i64 %5
+  %6 = load i32, i32* %arrayidx13, align 4
   %7 = or i64 %1, 5
-  %arrayidx16 = getelementptr inbounds i32* %diff, i64 %7
-  %8 = load i32* %arrayidx16, align 4
+  %arrayidx16 = getelementptr inbounds i32, i32* %diff, i64 %7
+  %8 = load i32, i32* %arrayidx16, align 4
   %add17 = add nsw i32 %8, %6
-  %arrayidx20 = getelementptr inbounds [8 x [8 x i32]]* %m2, i64 0, i64 %indvars.iv, i64 1
+  %arrayidx20 = getelementptr inbounds [8 x [8 x i32]], [8 x [8 x i32]]* %m2, i64 0, i64 %indvars.iv, i64 1
   store i32 %add17, i32* %arrayidx20, align 4
   %add24 = add nsw i32 %add10, %add17
   %9 = or i64 %1, 2
-  %arrayidx27 = getelementptr inbounds i32* %diff, i64 %9
-  %10 = load i32* %arrayidx27, align 4
+  %arrayidx27 = getelementptr inbounds i32, i32* %diff, i64 %9
+  %10 = load i32, i32* %arrayidx27, align 4
   %11 = or i64 %1, 6
-  %arrayidx30 = getelementptr inbounds i32* %diff, i64 %11
-  %12 = load i32* %arrayidx30, align 4
+  %arrayidx30 = getelementptr inbounds i32, i32* %diff, i64 %11
+  %12 = load i32, i32* %arrayidx30, align 4
   %add31 = add nsw i32 %12, %10
-  %arrayidx34 = getelementptr inbounds [8 x [8 x i32]]* %m2, i64 0, i64 %indvars.iv, i64 2
+  %arrayidx34 = getelementptr inbounds [8 x [8 x i32]], [8 x [8 x i32]]* %m2, i64 0, i64 %indvars.iv, i64 2
   store i32 %add31, i32* %arrayidx34, align 8
   %add38 = add nsw i32 %add24, %add31
   %13 = or i64 %1, 3
-  %arrayidx41 = getelementptr inbounds i32* %diff, i64 %13
-  %14 = load i32* %arrayidx41, align 4
+  %arrayidx41 = getelementptr inbounds i32, i32* %diff, i64 %13
+  %14 = load i32, i32* %arrayidx41, align 4
   %15 = or i64 %1, 7
-  %arrayidx44 = getelementptr inbounds i32* %diff, i64 %15
-  %16 = load i32* %arrayidx44, align 4
+  %arrayidx44 = getelementptr inbounds i32, i32* %diff, i64 %15
+  %16 = load i32, i32* %arrayidx44, align 4
   %add45 = add nsw i32 %16, %14
-  %arrayidx48 = getelementptr inbounds [8 x [8 x i32]]* %m2, i64 0, i64 %indvars.iv, i64 3
+  %arrayidx48 = getelementptr inbounds [8 x [8 x i32]], [8 x [8 x i32]]* %m2, i64 0, i64 %indvars.iv, i64 3
   store i32 %add45, i32* %arrayidx48, align 4
   %add52 = add nsw i32 %add38, %add45
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
@@ -68,7 +68,7 @@ for.body:                                         ; preds = %for.body, %entry
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:                                          ; preds = %for.body
-  %arraydecay = getelementptr inbounds [8 x [8 x i32]]* %m2, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [8 x [8 x i32]], [8 x [8 x i32]]* %m2, i64 0, i64 0
   call void @ff([8 x i32]* %arraydecay) #1
   ret i32 %add52
 }
diff --git a/test/Transforms/SLPVectorizer/X86/simple-loop.ll b/test/Transforms/SLPVectorizer/X86/simple-loop.ll
index 0111b946d496..c9bb88497ac1 100644
--- a/test/Transforms/SLPVectorizer/X86/simple-loop.ll
+++ b/test/Transforms/SLPVectorizer/X86/simple-loop.ll
@@ -11,18 +11,18 @@ define i32 @rollable(i32* noalias nocapture %in, i32* noalias nocapture %out, i6
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %i.019 = phi i64 [ %26, %.lr.ph ], [ 0, %0 ]
   %2 = shl i64 %i.019, 2
-  %3 = getelementptr inbounds i32* %in, i64 %2
+  %3 = getelementptr inbounds i32, i32* %in, i64 %2
 ;CHECK:load <4 x i32>
-  %4 = load i32* %3, align 4
+  %4 = load i32, i32* %3, align 4
   %5 = or i64 %2, 1
-  %6 = getelementptr inbounds i32* %in, i64 %5
-  %7 = load i32* %6, align 4
+  %6 = getelementptr inbounds i32, i32* %in, i64 %5
+  %7 = load i32, i32* %6, align 4
   %8 = or i64 %2, 2
-  %9 = getelementptr inbounds i32* %in, i64 %8
-  %10 = load i32* %9, align 4
+  %9 = getelementptr inbounds i32, i32* %in, i64 %8
+  %10 = load i32, i32* %9, align 4
   %11 = or i64 %2, 3
-  %12 = getelementptr inbounds i32* %in, i64 %11
-  %13 = load i32* %12, align 4
+  %12 = getelementptr inbounds i32, i32* %in, i64 %11
+  %13 = load i32, i32* %12, align 4
 ;CHECK:mul <4 x i32>
   %14 = mul i32 %4, 7
 ;CHECK:add <4 x i32>
@@ -33,14 +33,14 @@ define i32 @rollable(i32* noalias nocapture %in, i32* noalias nocapture %out, i6
   %19 = add i32 %18, 21
   %20 = mul i32 %13, 7
   %21 = add i32 %20, 28
-  %22 = getelementptr inbounds i32* %out, i64 %2
+  %22 = getelementptr inbounds i32, i32* %out, i64 %2
 ;CHECK:store <4 x i32>
   store i32 %15, i32* %22, align 4
-  %23 = getelementptr inbounds i32* %out, i64 %5
+  %23 = getelementptr inbounds i32, i32* %out, i64 %5
   store i32 %17, i32* %23, align 4
-  %24 = getelementptr inbounds i32* %out, i64 %8
+  %24 = getelementptr inbounds i32, i32* %out, i64 %8
   store i32 %19, i32* %24, align 4
-  %25 = getelementptr inbounds i32* %out, i64 %11
+  %25 = getelementptr inbounds i32, i32* %out, i64 %11
   store i32 %21, i32* %25, align 4
   %26 = add i64 %i.019, 1
   %exitcond = icmp eq i64 %26, %n
@@ -61,17 +61,17 @@ define i32 @unrollable(i32* %in, i32* %out, i64 %n) nounwind ssp uwtable {
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %i.019 = phi i64 [ %26, %.lr.ph ], [ 0, %0 ]
   %2 = shl i64 %i.019, 2
-  %3 = getelementptr inbounds i32* %in, i64 %2
-  %4 = load i32* %3, align 4
+  %3 = getelementptr inbounds i32, i32* %in, i64 %2
+  %4 = load i32, i32* %3, align 4
   %5 = or i64 %2, 1
-  %6 = getelementptr inbounds i32* %in, i64 %5
-  %7 = load i32* %6, align 4
+  %6 = getelementptr inbounds i32, i32* %in, i64 %5
+  %7 = load i32, i32* %6, align 4
   %8 = or i64 %2, 2
-  %9 = getelementptr inbounds i32* %in, i64 %8
-  %10 = load i32* %9, align 4
+  %9 = getelementptr inbounds i32, i32* %in, i64 %8
+  %10 = load i32, i32* %9, align 4
   %11 = or i64 %2, 3
-  %12 = getelementptr inbounds i32* %in, i64 %11
-  %13 = load i32* %12, align 4
+  %12 = getelementptr inbounds i32, i32* %in, i64 %11
+  %13 = load i32, i32* %12, align 4
   %14 = mul i32 %4, 7
   %15 = add i32 %14, 7
   %16 = mul i32 %7, 7
@@ -80,14 +80,14 @@ define i32 @unrollable(i32* %in, i32* %out, i64 %n) nounwind ssp uwtable {
   %19 = add i32 %18, 21
   %20 = mul i32 %13, 7
   %21 = add i32 %20, 28
-  %22 = getelementptr inbounds i32* %out, i64 %2
+  %22 = getelementptr inbounds i32, i32* %out, i64 %2
   store i32 %15, i32* %22, align 4
-  %23 = getelementptr inbounds i32* %out, i64 %5
+  %23 = getelementptr inbounds i32, i32* %out, i64 %5
   store i32 %17, i32* %23, align 4
   %barrier = call i32 @goo(i32 0)                      ; <---------------- memory barrier.
-  %24 = getelementptr inbounds i32* %out, i64 %8
+  %24 = getelementptr inbounds i32, i32* %out, i64 %8
   store i32 %19, i32* %24, align 4
-  %25 = getelementptr inbounds i32* %out, i64 %11
+  %25 = getelementptr inbounds i32, i32* %out, i64 %11
   store i32 %21, i32* %25, align 4
   %26 = add i64 %i.019, 1
   %exitcond = icmp eq i64 %26, %n
diff --git a/test/Transforms/SLPVectorizer/X86/simplebb.ll b/test/Transforms/SLPVectorizer/X86/simplebb.ll
index 7d682e5e4676..a5d9ad9685c0 100644
--- a/test/Transforms/SLPVectorizer/X86/simplebb.ll
+++ b/test/Transforms/SLPVectorizer/X86/simplebb.ll
@@ -9,16 +9,16 @@ target triple = "x86_64-apple-macosx10.8.0"
 ; CHECK: ret
 define void @test1(double* %a, double* %b, double* %c) {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   store double %mul, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   ret void
 }
@@ -29,17 +29,17 @@ entry:
 ; CHECK: ret
 define void @test2(double* %a, double* %b, i8* %e) {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   %c = bitcast i8* %e to double*
   store double %mul, double* %c, align 8
-  %carrayidx5 = getelementptr inbounds i8* %e, i64 8
+  %carrayidx5 = getelementptr inbounds i8, i8* %e, i64 8
   %arrayidx5 = bitcast i8* %carrayidx5 to double*
   store double %mul5, double* %arrayidx5, align 8
   ret void
@@ -52,16 +52,16 @@ entry:
 ; CHECK: ret
 define void @test_volatile_load(double* %a, double* %b, double* %c) {
 entry:
-  %i0 = load volatile double* %a, align 8
-  %i1 = load volatile double* %b, align 8
+  %i0 = load volatile double, double* %a, align 8
+  %i1 = load volatile double, double* %b, align 8
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   store double %mul, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   ret void
 }
@@ -72,16 +72,16 @@ entry:
 ; CHECK: ret
 define void @test_volatile_store(double* %a, double* %b, double* %c) {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   store volatile double %mul, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store volatile double %mul5, double* %arrayidx5, align 8
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/X86/tiny-tree.ll b/test/Transforms/SLPVectorizer/X86/tiny-tree.ll
index 10c3130b424c..6c93222ef93a 100644
--- a/test/Transforms/SLPVectorizer/X86/tiny-tree.ll
+++ b/test/Transforms/SLPVectorizer/X86/tiny-tree.ll
@@ -17,14 +17,14 @@ for.body:                                         ; preds = %entry, %for.body
   %i.015 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
   %dst.addr.014 = phi double* [ %add.ptr4, %for.body ], [ %dst, %entry ]
   %src.addr.013 = phi double* [ %add.ptr, %for.body ], [ %src, %entry ]
-  %0 = load double* %src.addr.013, align 8
+  %0 = load double, double* %src.addr.013, align 8
   store double %0, double* %dst.addr.014, align 8
-  %arrayidx2 = getelementptr inbounds double* %src.addr.013, i64 1
-  %1 = load double* %arrayidx2, align 8
-  %arrayidx3 = getelementptr inbounds double* %dst.addr.014, i64 1
+  %arrayidx2 = getelementptr inbounds double, double* %src.addr.013, i64 1
+  %1 = load double, double* %arrayidx2, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %dst.addr.014, i64 1
   store double %1, double* %arrayidx3, align 8
-  %add.ptr = getelementptr inbounds double* %src.addr.013, i64 %i.015
-  %add.ptr4 = getelementptr inbounds double* %dst.addr.014, i64 %i.015
+  %add.ptr = getelementptr inbounds double, double* %src.addr.013, i64 %i.015
+  %add.ptr4 = getelementptr inbounds double, double* %dst.addr.014, i64 %i.015
   %inc = add i64 %i.015, 1
   %exitcond = icmp eq i64 %inc, %count
   br i1 %exitcond, label %for.end, label %for.body
@@ -47,22 +47,22 @@ for.body:                                         ; preds = %entry, %for.body
   %i.023 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
   %dst.addr.022 = phi float* [ %add.ptr8, %for.body ], [ %dst, %entry ]
   %src.addr.021 = phi float* [ %add.ptr, %for.body ], [ %src, %entry ]
-  %0 = load float* %src.addr.021, align 4
+  %0 = load float, float* %src.addr.021, align 4
   store float %0, float* %dst.addr.022, align 4
-  %arrayidx2 = getelementptr inbounds float* %src.addr.021, i64 1
-  %1 = load float* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds float* %dst.addr.022, i64 1
+  %arrayidx2 = getelementptr inbounds float, float* %src.addr.021, i64 1
+  %1 = load float, float* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds float, float* %dst.addr.022, i64 1
   store float %1, float* %arrayidx3, align 4
-  %arrayidx4 = getelementptr inbounds float* %src.addr.021, i64 2
-  %2 = load float* %arrayidx4, align 4
-  %arrayidx5 = getelementptr inbounds float* %dst.addr.022, i64 2
+  %arrayidx4 = getelementptr inbounds float, float* %src.addr.021, i64 2
+  %2 = load float, float* %arrayidx4, align 4
+  %arrayidx5 = getelementptr inbounds float, float* %dst.addr.022, i64 2
   store float %2, float* %arrayidx5, align 4
-  %arrayidx6 = getelementptr inbounds float* %src.addr.021, i64 3
-  %3 = load float* %arrayidx6, align 4
-  %arrayidx7 = getelementptr inbounds float* %dst.addr.022, i64 3
+  %arrayidx6 = getelementptr inbounds float, float* %src.addr.021, i64 3
+  %3 = load float, float* %arrayidx6, align 4
+  %arrayidx7 = getelementptr inbounds float, float* %dst.addr.022, i64 3
   store float %3, float* %arrayidx7, align 4
-  %add.ptr = getelementptr inbounds float* %src.addr.021, i64 %i.023
-  %add.ptr8 = getelementptr inbounds float* %dst.addr.022, i64 %i.023
+  %add.ptr = getelementptr inbounds float, float* %src.addr.021, i64 %i.023
+  %add.ptr8 = getelementptr inbounds float, float* %dst.addr.022, i64 %i.023
   %inc = add i64 %i.023, 1
   %exitcond = icmp eq i64 %inc, %count
   br i1 %exitcond, label %for.end, label %for.body
@@ -85,14 +85,14 @@ for.body:                                         ; preds = %entry, %for.body
   %i.015 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
   %dst.addr.014 = phi double* [ %add.ptr4, %for.body ], [ %dst, %entry ]
   %src.addr.013 = phi double* [ %add.ptr, %for.body ], [ %src, %entry ]
-  %0 = load double* %src.addr.013, align 8
+  %0 = load double, double* %src.addr.013, align 8
   store double %0, double* %dst.addr.014, align 8
-  %arrayidx2 = getelementptr inbounds double* %src.addr.013, i64 2
-  %1 = load double* %arrayidx2, align 8
-  %arrayidx3 = getelementptr inbounds double* %dst.addr.014, i64 1 
+  %arrayidx2 = getelementptr inbounds double, double* %src.addr.013, i64 2
+  %1 = load double, double* %arrayidx2, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %dst.addr.014, i64 1 
   store double %1, double* %arrayidx3, align 8
-  %add.ptr = getelementptr inbounds double* %src.addr.013, i64 %i.015
-  %add.ptr4 = getelementptr inbounds double* %dst.addr.014, i64 %i.015
+  %add.ptr = getelementptr inbounds double, double* %src.addr.013, i64 %i.015
+  %add.ptr4 = getelementptr inbounds double, double* %dst.addr.014, i64 %i.015
   %inc = add i64 %i.015, 1
   %exitcond = icmp eq i64 %inc, %count
   br i1 %exitcond, label %for.end, label %for.body
@@ -115,22 +115,22 @@ for.body:                                         ; preds = %entry, %for.body
   %i.023 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
   %dst.addr.022 = phi float* [ %add.ptr8, %for.body ], [ %dst, %entry ]
   %src.addr.021 = phi float* [ %add.ptr, %for.body ], [ %src, %entry ]
-  %0 = load float* %src.addr.021, align 4
+  %0 = load float, float* %src.addr.021, align 4
   store float %0, float* %dst.addr.022, align 4
-  %arrayidx2 = getelementptr inbounds float* %src.addr.021, i64 4 
-  %1 = load float* %arrayidx2, align 4
-  %arrayidx3 = getelementptr inbounds float* %dst.addr.022, i64 1
+  %arrayidx2 = getelementptr inbounds float, float* %src.addr.021, i64 4 
+  %1 = load float, float* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds float, float* %dst.addr.022, i64 1
   store float %1, float* %arrayidx3, align 4
-  %arrayidx4 = getelementptr inbounds float* %src.addr.021, i64 2
-  %2 = load float* %arrayidx4, align 4
-  %arrayidx5 = getelementptr inbounds float* %dst.addr.022, i64 2
+  %arrayidx4 = getelementptr inbounds float, float* %src.addr.021, i64 2
+  %2 = load float, float* %arrayidx4, align 4
+  %arrayidx5 = getelementptr inbounds float, float* %dst.addr.022, i64 2
   store float %2, float* %arrayidx5, align 4
-  %arrayidx6 = getelementptr inbounds float* %src.addr.021, i64 3
-  %3 = load float* %arrayidx6, align 4
-  %arrayidx7 = getelementptr inbounds float* %dst.addr.022, i64 3
+  %arrayidx6 = getelementptr inbounds float, float* %src.addr.021, i64 3
+  %3 = load float, float* %arrayidx6, align 4
+  %arrayidx7 = getelementptr inbounds float, float* %dst.addr.022, i64 3
   store float %3, float* %arrayidx7, align 4
-  %add.ptr = getelementptr inbounds float* %src.addr.021, i64 %i.023
-  %add.ptr8 = getelementptr inbounds float* %dst.addr.022, i64 %i.023
+  %add.ptr = getelementptr inbounds float, float* %src.addr.021, i64 %i.023
+  %add.ptr8 = getelementptr inbounds float, float* %dst.addr.022, i64 %i.023
   %inc = add i64 %i.023, 1
   %exitcond = icmp eq i64 %inc, %count
   br i1 %exitcond, label %for.end, label %for.body
@@ -143,13 +143,13 @@ for.end:                                          ; preds = %for.body, %entry
 ; CHECK-LABEL: store_splat
 ; CHECK: store <4 x float>
 define void @store_splat(float*, float) {
-  %3 = getelementptr inbounds float* %0, i64 0
+  %3 = getelementptr inbounds float, float* %0, i64 0
   store float %1, float* %3, align 4
-  %4 = getelementptr inbounds float* %0, i64 1
+  %4 = getelementptr inbounds float, float* %0, i64 1
   store float %1, float* %4, align 4
-  %5 = getelementptr inbounds float* %0, i64 2
+  %5 = getelementptr inbounds float, float* %0, i64 2
   store float %1, float* %5, align 4
-  %6 = getelementptr inbounds float* %0, i64 3
+  %6 = getelementptr inbounds float, float* %0, i64 3
   store float %1, float* %6, align 4
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/X86/unreachable.ll b/test/Transforms/SLPVectorizer/X86/unreachable.ll
index 8d609571be17..f29f69d7e82f 100644
--- a/test/Transforms/SLPVectorizer/X86/unreachable.ll
+++ b/test/Transforms/SLPVectorizer/X86/unreachable.ll
@@ -11,16 +11,16 @@ entry:
   br label %bb2
 
 bb1:                                    ; an unreachable block
-  %t3 = getelementptr inbounds i32* %x, i64 4
-  %t4 = load i32* %t3, align 4
-  %t5 = getelementptr inbounds i32* %x, i64 5
-  %t6 = load i32* %t5, align 4
+  %t3 = getelementptr inbounds i32, i32* %x, i64 4
+  %t4 = load i32, i32* %t3, align 4
+  %t5 = getelementptr inbounds i32, i32* %x, i64 5
+  %t6 = load i32, i32* %t5, align 4
   %bad = fadd float %bad, 0.000000e+00  ; <- an instruction with self dependency,
                                         ;    but legal in unreachable code
-  %t7 = getelementptr inbounds i32* %x, i64 6
-  %t8 = load i32* %t7, align 4
-  %t9 = getelementptr inbounds i32* %x, i64 7
-  %t10 = load i32* %t9, align 4
+  %t7 = getelementptr inbounds i32, i32* %x, i64 6
+  %t8 = load i32, i32* %t7, align 4
+  %t9 = getelementptr inbounds i32, i32* %x, i64 7
+  %t10 = load i32, i32* %t9, align 4
   br label %bb2
 
 bb2:
@@ -29,11 +29,11 @@ bb2:
   %t3.0 = phi i32 [ %t8, %bb1 ], [ 2, %entry ]
   %t4.0 = phi i32 [ %t10, %bb1 ], [ 2, %entry ]
   store i32 %t1.0, i32* %x, align 4
-  %t12 = getelementptr inbounds i32* %x, i64 1
+  %t12 = getelementptr inbounds i32, i32* %x, i64 1
   store i32 %t2.0, i32* %t12, align 4
-  %t13 = getelementptr inbounds i32* %x, i64 2
+  %t13 = getelementptr inbounds i32, i32* %x, i64 2
   store i32 %t3.0, i32* %t13, align 4
-  %t14 = getelementptr inbounds i32* %x, i64 3
+  %t14 = getelementptr inbounds i32, i32* %x, i64 3
   store i32 %t4.0, i32* %t14, align 4
   ret void
 }
diff --git a/test/Transforms/SLPVectorizer/XCore/no-vector-registers.ll b/test/Transforms/SLPVectorizer/XCore/no-vector-registers.ll
index 66392e74cb31..efd5386f520e 100644
--- a/test/Transforms/SLPVectorizer/XCore/no-vector-registers.ll
+++ b/test/Transforms/SLPVectorizer/XCore/no-vector-registers.ll
@@ -8,16 +8,16 @@ target triple = "xcore"
 ; CHECK-NOT: <2 x double>
 define void @test1(double* %a, double* %b, double* %c) {
 entry:
-  %i0 = load double* %a, align 8
-  %i1 = load double* %b, align 8
+  %i0 = load double, double* %a, align 8
+  %i1 = load double, double* %b, align 8
   %mul = fmul double %i0, %i1
-  %arrayidx3 = getelementptr inbounds double* %a, i64 1
-  %i3 = load double* %arrayidx3, align 8
-  %arrayidx4 = getelementptr inbounds double* %b, i64 1
-  %i4 = load double* %arrayidx4, align 8
+  %arrayidx3 = getelementptr inbounds double, double* %a, i64 1
+  %i3 = load double, double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
+  %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   store double %mul, double* %c, align 8
-  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  %arrayidx5 = getelementptr inbounds double, double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   ret void
 }
diff --git a/test/Transforms/SROA/address-spaces.ll b/test/Transforms/SROA/address-spaces.ll
index 847f2851bbbf..004695dceddc 100644
--- a/test/Transforms/SROA/address-spaces.ll
+++ b/test/Transforms/SROA/address-spaces.ll
@@ -10,7 +10,7 @@ declare void @llvm.memcpy.p1i8.p1i8.i32(i8 addrspace(1)* nocapture, i8 addrspace
 ; Make sure an illegal bitcast isn't introduced
 define void @test_address_space_1_1(<2 x i64> addrspace(1)* %a, i16 addrspace(1)* %b) {
 ; CHECK-LABEL: @test_address_space_1_1(
-; CHECK: load <2 x i64> addrspace(1)* %a, align 2
+; CHECK: load <2 x i64>, <2 x i64> addrspace(1)* %a, align 2
 ; CHECK: store <2 x i64> {{.*}}, <2 x i64> addrspace(1)* {{.*}}, align 2
 ; CHECK: ret void
   %aa = alloca <2 x i64>, align 16
@@ -24,7 +24,7 @@ define void @test_address_space_1_1(<2 x i64> addrspace(1)* %a, i16 addrspace(1)
 
 define void @test_address_space_1_0(<2 x i64> addrspace(1)* %a, i16* %b) {
 ; CHECK-LABEL: @test_address_space_1_0(
-; CHECK: load <2 x i64> addrspace(1)* %a, align 2
+; CHECK: load <2 x i64>, <2 x i64> addrspace(1)* %a, align 2
 ; CHECK: store <2 x i64> {{.*}}, <2 x i64>* {{.*}}, align 2
 ; CHECK: ret void
   %aa = alloca <2 x i64>, align 16
@@ -38,7 +38,7 @@ define void @test_address_space_1_0(<2 x i64> addrspace(1)* %a, i16* %b) {
 
 define void @test_address_space_0_1(<2 x i64>* %a, i16 addrspace(1)* %b) {
 ; CHECK-LABEL: @test_address_space_0_1(
-; CHECK: load <2 x i64>* %a, align 2
+; CHECK: load <2 x i64>, <2 x i64>* %a, align 2
 ; CHECK: store <2 x i64> {{.*}}, <2 x i64> addrspace(1)* {{.*}}, align 2
 ; CHECK: ret void
   %aa = alloca <2 x i64>, align 16
@@ -60,7 +60,7 @@ for.end:
   %in = alloca %struct.struct_test_27.0.13, align 8
   %0 = bitcast %struct.struct_test_27.0.13* %in to [5 x i64]*
   store [5 x i64] %in.coerce, [5 x i64]* %0, align 8
-  %scevgep9 = getelementptr %struct.struct_test_27.0.13* %in, i32 0, i32 4, i32 0
+  %scevgep9 = getelementptr %struct.struct_test_27.0.13, %struct.struct_test_27.0.13* %in, i32 0, i32 4, i32 0
   %scevgep910 = bitcast i32* %scevgep9 to i8*
   call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* undef, i8* %scevgep910, i32 16, i32 4, i1 false)
   ret void
diff --git a/test/Transforms/SROA/alignment.ll b/test/Transforms/SROA/alignment.ll
index 4f4e40cf76a7..455d14246e57 100644
--- a/test/Transforms/SROA/alignment.ll
+++ b/test/Transforms/SROA/alignment.ll
@@ -5,21 +5,21 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
 
 define void @test1({ i8, i8 }* %a, { i8, i8 }* %b) {
 ; CHECK-LABEL: @test1(
-; CHECK: %[[gep_a0:.*]] = getelementptr inbounds { i8, i8 }* %a, i64 0, i32 0
-; CHECK: %[[a0:.*]] = load i8* %[[gep_a0]], align 16
-; CHECK: %[[gep_a1:.*]] = getelementptr inbounds { i8, i8 }* %a, i64 0, i32 1
-; CHECK: %[[a1:.*]] = load i8* %[[gep_a1]], align 1
-; CHECK: %[[gep_b0:.*]] = getelementptr inbounds { i8, i8 }* %b, i64 0, i32 0
+; CHECK: %[[gep_a0:.*]] = getelementptr inbounds { i8, i8 }, { i8, i8 }* %a, i64 0, i32 0
+; CHECK: %[[a0:.*]] = load i8, i8* %[[gep_a0]], align 16
+; CHECK: %[[gep_a1:.*]] = getelementptr inbounds { i8, i8 }, { i8, i8 }* %a, i64 0, i32 1
+; CHECK: %[[a1:.*]] = load i8, i8* %[[gep_a1]], align 1
+; CHECK: %[[gep_b0:.*]] = getelementptr inbounds { i8, i8 }, { i8, i8 }* %b, i64 0, i32 0
 ; CHECK: store i8 %[[a0]], i8* %[[gep_b0]], align 16
-; CHECK: %[[gep_b1:.*]] = getelementptr inbounds { i8, i8 }* %b, i64 0, i32 1
+; CHECK: %[[gep_b1:.*]] = getelementptr inbounds { i8, i8 }, { i8, i8 }* %b, i64 0, i32 1
 ; CHECK: store i8 %[[a1]], i8* %[[gep_b1]], align 1
 ; CHECK: ret void
 
 entry:
   %alloca = alloca { i8, i8 }, align 16
-  %gep_a = getelementptr { i8, i8 }* %a, i32 0, i32 0
-  %gep_alloca = getelementptr { i8, i8 }* %alloca, i32 0, i32 0
-  %gep_b = getelementptr { i8, i8 }* %b, i32 0, i32 0
+  %gep_a = getelementptr { i8, i8 }, { i8, i8 }* %a, i32 0, i32 0
+  %gep_alloca = getelementptr { i8, i8 }, { i8, i8 }* %alloca, i32 0, i32 0
+  %gep_b = getelementptr { i8, i8 }, { i8, i8 }* %b, i32 0, i32 0
 
   store i8 420, i8* %gep_alloca, align 16
 
@@ -31,17 +31,17 @@ entry:
 define void @test2() {
 ; CHECK-LABEL: @test2(
 ; CHECK: alloca i16
-; CHECK: load i8* %{{.*}}
+; CHECK: load i8, i8* %{{.*}}
 ; CHECK: store i8 42, i8* %{{.*}}
 ; CHECK: ret void
 
 entry:
   %a = alloca { i8, i8, i8, i8 }, align 2
-  %gep1 = getelementptr { i8, i8, i8, i8 }* %a, i32 0, i32 1
+  %gep1 = getelementptr { i8, i8, i8, i8 }, { i8, i8, i8, i8 }* %a, i32 0, i32 1
   %cast1 = bitcast i8* %gep1 to i16*
   store volatile i16 0, i16* %cast1
-  %gep2 = getelementptr { i8, i8, i8, i8 }* %a, i32 0, i32 2
-  %result = load i8* %gep2
+  %gep2 = getelementptr { i8, i8, i8, i8 }, { i8, i8, i8, i8 }* %a, i32 0, i32 2
+  %result = load i8, i8* %gep2
   store i8 42, i8* %gep2
   ret void
 }
@@ -49,7 +49,7 @@ entry:
 define void @PR13920(<2 x i64>* %a, i16* %b) {
 ; Test that alignments on memcpy intrinsics get propagated to loads and stores.
 ; CHECK-LABEL: @PR13920(
-; CHECK: load <2 x i64>* %a, align 2
+; CHECK: load <2 x i64>, <2 x i64>* %a, align 2
 ; CHECK: store <2 x i64> {{.*}}, <2 x i64>* {{.*}}, align 2
 ; CHECK: ret void
 
@@ -79,7 +79,7 @@ entry:
   %a_raw = bitcast { i8*, i8*, i8* }* %a to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a_raw, i8* %x, i32 22, i32 8, i1 false)
   %b_raw = bitcast { i8*, i8*, i8* }* %b to i8*
-  %b_gep = getelementptr i8* %b_raw, i32 6
+  %b_gep = getelementptr i8, i8* %b_raw, i32 6
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %b_gep, i8* %x, i32 18, i32 2, i1 false)
   ret void
 }
@@ -93,28 +93,28 @@ define void @test5() {
 ; CHECK: alloca [9 x i8]
 ; CHECK: alloca [9 x i8]
 ; CHECK: store volatile double 0.0{{.*}}, double* %{{.*}}, align 1
-; CHECK: load volatile i16* %{{.*}}, align 1
-; CHECK: load double* %{{.*}}, align 1
+; CHECK: load volatile i16, i16* %{{.*}}, align 1
+; CHECK: load double, double* %{{.*}}, align 1
 ; CHECK: store volatile double %{{.*}}, double* %{{.*}}, align 1
-; CHECK: load volatile i16* %{{.*}}, align 1
+; CHECK: load volatile i16, i16* %{{.*}}, align 1
 ; CHECK: ret void
 
 entry:
   %a = alloca [18 x i8]
-  %raw1 = getelementptr inbounds [18 x i8]* %a, i32 0, i32 0
+  %raw1 = getelementptr inbounds [18 x i8], [18 x i8]* %a, i32 0, i32 0
   %ptr1 = bitcast i8* %raw1 to double*
   store volatile double 0.0, double* %ptr1, align 1
-  %weird_gep1 = getelementptr inbounds [18 x i8]* %a, i32 0, i32 7
+  %weird_gep1 = getelementptr inbounds [18 x i8], [18 x i8]* %a, i32 0, i32 7
   %weird_cast1 = bitcast i8* %weird_gep1 to i16*
-  %weird_load1 = load volatile i16* %weird_cast1, align 1
+  %weird_load1 = load volatile i16, i16* %weird_cast1, align 1
 
-  %raw2 = getelementptr inbounds [18 x i8]* %a, i32 0, i32 9
+  %raw2 = getelementptr inbounds [18 x i8], [18 x i8]* %a, i32 0, i32 9
   %ptr2 = bitcast i8* %raw2 to double*
-  %d1 = load double* %ptr1, align 1
+  %d1 = load double, double* %ptr1, align 1
   store volatile double %d1, double* %ptr2, align 1
-  %weird_gep2 = getelementptr inbounds [18 x i8]* %a, i32 0, i32 16
+  %weird_gep2 = getelementptr inbounds [18 x i8], [18 x i8]* %a, i32 0, i32 16
   %weird_cast2 = bitcast i8* %weird_gep2 to i16*
-  %weird_load2 = load volatile i16* %weird_cast2, align 1
+  %weird_load2 = load volatile i16, i16* %weird_cast2, align 1
 
   ret void
 }
@@ -130,13 +130,13 @@ define void @test6() {
 
 entry:
   %a = alloca [16 x i8]
-  %raw1 = getelementptr inbounds [16 x i8]* %a, i32 0, i32 0
+  %raw1 = getelementptr inbounds [16 x i8], [16 x i8]* %a, i32 0, i32 0
   %ptr1 = bitcast i8* %raw1 to double*
   store volatile double 0.0, double* %ptr1, align 1
 
-  %raw2 = getelementptr inbounds [16 x i8]* %a, i32 0, i32 8
+  %raw2 = getelementptr inbounds [16 x i8], [16 x i8]* %a, i32 0, i32 8
   %ptr2 = bitcast i8* %raw2 to double*
-  %val = load double* %ptr1, align 1
+  %val = load double, double* %ptr1, align 1
   store volatile double %val, double* %ptr2, align 1
 
   ret void
@@ -150,17 +150,17 @@ define void @test7(i8* %out) {
 
 entry:
   %a = alloca [16 x i8]
-  %raw1 = getelementptr inbounds [16 x i8]* %a, i32 0, i32 0
+  %raw1 = getelementptr inbounds [16 x i8], [16 x i8]* %a, i32 0, i32 0
   %ptr1 = bitcast i8* %raw1 to double*
-  %raw2 = getelementptr inbounds [16 x i8]* %a, i32 0, i32 8
+  %raw2 = getelementptr inbounds [16 x i8], [16 x i8]* %a, i32 0, i32 8
   %ptr2 = bitcast i8* %raw2 to double*
 
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %raw1, i8* %out, i32 16, i32 0, i1 false)
-; CHECK: %[[val2:.*]] = load double* %{{.*}}, align 1
-; CHECK: %[[val1:.*]] = load double* %{{.*}}, align 1
+; CHECK: %[[val2:.*]] = load double, double* %{{.*}}, align 1
+; CHECK: %[[val1:.*]] = load double, double* %{{.*}}, align 1
 
-  %val1 = load double* %ptr2, align 1
-  %val2 = load double* %ptr1, align 1
+  %val1 = load double, double* %ptr2, align 1
+  %val2 = load double, double* %ptr1, align 1
 
   store double %val1, double* %ptr1, align 1
   store double %val2, double* %ptr2, align 1
diff --git a/test/Transforms/SROA/basictest.ll b/test/Transforms/SROA/basictest.ll
index e3f762abfa39..a59192d718cf 100644
--- a/test/Transforms/SROA/basictest.ll
+++ b/test/Transforms/SROA/basictest.ll
@@ -19,7 +19,7 @@ entry:
   call void @llvm.lifetime.start(i64 4, i8* %a1.i8)
 
   store i32 0, i32* %a1
-  %v1 = load i32* %a1
+  %v1 = load i32, i32* %a1
 
   call void @llvm.lifetime.end(i64 4, i8* %a1.i8)
 
@@ -27,7 +27,7 @@ entry:
   call void @llvm.lifetime.start(i64 4, i8* %a2.i8)
 
   store float 0.0, float* %a2
-  %v2 = load float * %a2
+  %v2 = load float , float * %a2
   %v2.int = bitcast float %v2 to i32
   %sum1 = add i32 %v1, %v2.int
 
@@ -43,9 +43,9 @@ define i32 @test1() {
 
 entry:
   %X = alloca { i32, float }
-  %Y = getelementptr { i32, float }* %X, i64 0, i32 0
+  %Y = getelementptr { i32, float }, { i32, float }* %X, i64 0, i32 0
   store i32 0, i32* %Y
-  %Z = load i32* %Y
+  %Z = load i32, i32* %Y
   ret i32 %Z
 }
 
@@ -61,7 +61,7 @@ entry:
   br label %L2
 
 L2:
-  %Z = load i64* %B
+  %Z = load i64, i64* %B
   ret i64 %Z
 }
 
@@ -79,48 +79,48 @@ entry:
 ; CHECK-NEXT: %[[test3_a6:.*]] = alloca [7 x i8]
 ; CHECK-NEXT: %[[test3_a7:.*]] = alloca [85 x i8]
 
-  %b = getelementptr [300 x i8]* %a, i64 0, i64 0
+  %b = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 0
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %b, i8* %src, i32 300, i32 1, i1 false)
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [42 x i8]* %[[test3_a1]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [42 x i8], [42 x i8]* %[[test3_a1]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %src, i32 42
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %src, i64 42
-; CHECK-NEXT: %[[test3_r1:.*]] = load i8* %[[gep]]
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8* %src, i64 43
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [99 x i8]* %[[test3_a2]], i64 0, i64 0
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %src, i64 42
+; CHECK-NEXT: %[[test3_r1:.*]] = load i8, i8* %[[gep]]
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8, i8* %src, i64 43
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [99 x i8], [99 x i8]* %[[test3_a2]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 99
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8* %src, i64 142
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [16 x i8]* %[[test3_a3]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8, i8* %src, i64 142
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [16 x i8], [16 x i8]* %[[test3_a3]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 16
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8* %src, i64 158
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [42 x i8]* %[[test3_a4]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8, i8* %src, i64 158
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [42 x i8], [42 x i8]* %[[test3_a4]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 42
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8* %src, i64 200
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a5]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8, i8* %src, i64 200
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a5]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 7
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %src, i64 207
-; CHECK-NEXT: %[[test3_r2:.*]] = load i8* %[[gep]]
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8* %src, i64 208
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a6]], i64 0, i64 0
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %src, i64 207
+; CHECK-NEXT: %[[test3_r2:.*]] = load i8, i8* %[[gep]]
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8, i8* %src, i64 208
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a6]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 7
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8* %src, i64 215
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [85 x i8]* %[[test3_a7]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8, i8* %src, i64 215
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [85 x i8], [85 x i8]* %[[test3_a7]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 85
 
   ; Clobber a single element of the array, this should be promotable.
-  %c = getelementptr [300 x i8]* %a, i64 0, i64 42
+  %c = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 42
   store i8 0, i8* %c
 
   ; Make a sequence of overlapping stores to the array. These overlap both in
   ; forward strides and in shrinking accesses.
-  %overlap.1.i8 = getelementptr [300 x i8]* %a, i64 0, i64 142
-  %overlap.2.i8 = getelementptr [300 x i8]* %a, i64 0, i64 143
-  %overlap.3.i8 = getelementptr [300 x i8]* %a, i64 0, i64 144
-  %overlap.4.i8 = getelementptr [300 x i8]* %a, i64 0, i64 145
-  %overlap.5.i8 = getelementptr [300 x i8]* %a, i64 0, i64 146
-  %overlap.6.i8 = getelementptr [300 x i8]* %a, i64 0, i64 147
-  %overlap.7.i8 = getelementptr [300 x i8]* %a, i64 0, i64 148
-  %overlap.8.i8 = getelementptr [300 x i8]* %a, i64 0, i64 149
-  %overlap.9.i8 = getelementptr [300 x i8]* %a, i64 0, i64 150
+  %overlap.1.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 142
+  %overlap.2.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 143
+  %overlap.3.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 144
+  %overlap.4.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 145
+  %overlap.5.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 146
+  %overlap.6.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 147
+  %overlap.7.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 148
+  %overlap.8.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 149
+  %overlap.9.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 150
   %overlap.1.i16 = bitcast i8* %overlap.1.i8 to i16*
   %overlap.1.i32 = bitcast i8* %overlap.1.i8 to i32*
   %overlap.1.i64 = bitcast i8* %overlap.1.i8 to i64*
@@ -133,7 +133,7 @@ entry:
   %overlap.8.i64 = bitcast i8* %overlap.8.i8 to i64*
   %overlap.9.i64 = bitcast i8* %overlap.9.i8 to i64*
   store i8 1, i8* %overlap.1.i8
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8]* %[[test3_a3]], i64 0, i64 0
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8], [16 x i8]* %[[test3_a3]], i64 0, i64 0
 ; CHECK-NEXT: store i8 1, i8* %[[gep]]
   store i16 1, i16* %overlap.1.i16
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast [16 x i8]* %[[test3_a3]] to i16*
@@ -145,48 +145,48 @@ entry:
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast [16 x i8]* %[[test3_a3]] to i64*
 ; CHECK-NEXT: store i64 1, i64* %[[bitcast]]
   store i64 2, i64* %overlap.2.i64
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8]* %[[test3_a3]], i64 0, i64 1
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8], [16 x i8]* %[[test3_a3]], i64 0, i64 1
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i64*
 ; CHECK-NEXT: store i64 2, i64* %[[bitcast]]
   store i64 3, i64* %overlap.3.i64
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8]* %[[test3_a3]], i64 0, i64 2
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8], [16 x i8]* %[[test3_a3]], i64 0, i64 2
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i64*
 ; CHECK-NEXT: store i64 3, i64* %[[bitcast]]
   store i64 4, i64* %overlap.4.i64
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8]* %[[test3_a3]], i64 0, i64 3
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8], [16 x i8]* %[[test3_a3]], i64 0, i64 3
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i64*
 ; CHECK-NEXT: store i64 4, i64* %[[bitcast]]
   store i64 5, i64* %overlap.5.i64
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8]* %[[test3_a3]], i64 0, i64 4
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8], [16 x i8]* %[[test3_a3]], i64 0, i64 4
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i64*
 ; CHECK-NEXT: store i64 5, i64* %[[bitcast]]
   store i64 6, i64* %overlap.6.i64
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8]* %[[test3_a3]], i64 0, i64 5
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8], [16 x i8]* %[[test3_a3]], i64 0, i64 5
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i64*
 ; CHECK-NEXT: store i64 6, i64* %[[bitcast]]
   store i64 7, i64* %overlap.7.i64
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8]* %[[test3_a3]], i64 0, i64 6
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8], [16 x i8]* %[[test3_a3]], i64 0, i64 6
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i64*
 ; CHECK-NEXT: store i64 7, i64* %[[bitcast]]
   store i64 8, i64* %overlap.8.i64
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8]* %[[test3_a3]], i64 0, i64 7
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8], [16 x i8]* %[[test3_a3]], i64 0, i64 7
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i64*
 ; CHECK-NEXT: store i64 8, i64* %[[bitcast]]
   store i64 9, i64* %overlap.9.i64
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8]* %[[test3_a3]], i64 0, i64 8
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [16 x i8], [16 x i8]* %[[test3_a3]], i64 0, i64 8
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i64*
 ; CHECK-NEXT: store i64 9, i64* %[[bitcast]]
 
   ; Make two sequences of overlapping stores with more gaps and irregularities.
-  %overlap2.1.0.i8 = getelementptr [300 x i8]* %a, i64 0, i64 200
-  %overlap2.1.1.i8 = getelementptr [300 x i8]* %a, i64 0, i64 201
-  %overlap2.1.2.i8 = getelementptr [300 x i8]* %a, i64 0, i64 202
-  %overlap2.1.3.i8 = getelementptr [300 x i8]* %a, i64 0, i64 203
+  %overlap2.1.0.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 200
+  %overlap2.1.1.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 201
+  %overlap2.1.2.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 202
+  %overlap2.1.3.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 203
 
-  %overlap2.2.0.i8 = getelementptr [300 x i8]* %a, i64 0, i64 208
-  %overlap2.2.1.i8 = getelementptr [300 x i8]* %a, i64 0, i64 209
-  %overlap2.2.2.i8 = getelementptr [300 x i8]* %a, i64 0, i64 210
-  %overlap2.2.3.i8 = getelementptr [300 x i8]* %a, i64 0, i64 211
+  %overlap2.2.0.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 208
+  %overlap2.2.1.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 209
+  %overlap2.2.2.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 210
+  %overlap2.2.3.i8 = getelementptr [300 x i8], [300 x i8]* %a, i64 0, i64 211
 
   %overlap2.1.0.i16 = bitcast i8* %overlap2.1.0.i8 to i16*
   %overlap2.1.0.i32 = bitcast i8* %overlap2.1.0.i8 to i32*
@@ -194,7 +194,7 @@ entry:
   %overlap2.1.2.i32 = bitcast i8* %overlap2.1.2.i8 to i32*
   %overlap2.1.3.i32 = bitcast i8* %overlap2.1.3.i8 to i32*
   store i8 1,  i8*  %overlap2.1.0.i8
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a5]], i64 0, i64 0
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a5]], i64 0, i64 0
 ; CHECK-NEXT: store i8 1, i8* %[[gep]]
   store i16 1, i16* %overlap2.1.0.i16
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast [7 x i8]* %[[test3_a5]] to i16*
@@ -203,15 +203,15 @@ entry:
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast [7 x i8]* %[[test3_a5]] to i32*
 ; CHECK-NEXT: store i32 1, i32* %[[bitcast]]
   store i32 2, i32* %overlap2.1.1.i32
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a5]], i64 0, i64 1
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a5]], i64 0, i64 1
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i32*
 ; CHECK-NEXT: store i32 2, i32* %[[bitcast]]
   store i32 3, i32* %overlap2.1.2.i32
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a5]], i64 0, i64 2
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a5]], i64 0, i64 2
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i32*
 ; CHECK-NEXT: store i32 3, i32* %[[bitcast]]
   store i32 4, i32* %overlap2.1.3.i32
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a5]], i64 0, i64 3
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a5]], i64 0, i64 3
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i32*
 ; CHECK-NEXT: store i32 4, i32* %[[bitcast]]
 
@@ -224,78 +224,78 @@ entry:
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast [7 x i8]* %[[test3_a6]] to i32*
 ; CHECK-NEXT: store i32 1, i32* %[[bitcast]]
   store i8 1,  i8*  %overlap2.2.1.i8
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a6]], i64 0, i64 1
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a6]], i64 0, i64 1
 ; CHECK-NEXT: store i8 1, i8* %[[gep]]
   store i16 1, i16* %overlap2.2.1.i16
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a6]], i64 0, i64 1
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a6]], i64 0, i64 1
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i16*
 ; CHECK-NEXT: store i16 1, i16* %[[bitcast]]
   store i32 1, i32* %overlap2.2.1.i32
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a6]], i64 0, i64 1
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a6]], i64 0, i64 1
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i32*
 ; CHECK-NEXT: store i32 1, i32* %[[bitcast]]
   store i32 3, i32* %overlap2.2.2.i32
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a6]], i64 0, i64 2
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a6]], i64 0, i64 2
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i32*
 ; CHECK-NEXT: store i32 3, i32* %[[bitcast]]
   store i32 4, i32* %overlap2.2.3.i32
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a6]], i64 0, i64 3
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a6]], i64 0, i64 3
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i32*
 ; CHECK-NEXT: store i32 4, i32* %[[bitcast]]
 
-  %overlap2.prefix = getelementptr i8* %overlap2.1.1.i8, i64 -4
+  %overlap2.prefix = getelementptr i8, i8* %overlap2.1.1.i8, i64 -4
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %overlap2.prefix, i8* %src, i32 8, i32 1, i1 false)
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [42 x i8]* %[[test3_a4]], i64 0, i64 39
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [42 x i8], [42 x i8]* %[[test3_a4]], i64 0, i64 39
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %src, i32 3
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8* %src, i64 3
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a5]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8, i8* %src, i64 3
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a5]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 5
 
   ; Bridge between the overlapping areas
   call void @llvm.memset.p0i8.i32(i8* %overlap2.1.2.i8, i8 42, i32 8, i32 1, i1 false)
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a5]], i64 0, i64 2
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a5]], i64 0, i64 2
 ; CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* %[[gep]], i8 42, i32 5
 ; ...promoted i8 store...
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a6]], i64 0, i64 0
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a6]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* %[[gep]], i8 42, i32 2
 
   ; Entirely within the second overlap.
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %overlap2.2.1.i8, i8* %src, i32 5, i32 1, i1 false)
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a6]], i64 0, i64 1
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a6]], i64 0, i64 1
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep]], i8* %src, i32 5
 
   ; Trailing past the second overlap.
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %overlap2.2.2.i8, i8* %src, i32 8, i32 1, i1 false)
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a6]], i64 0, i64 2
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a6]], i64 0, i64 2
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep]], i8* %src, i32 5
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8* %src, i64 5
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [85 x i8]* %[[test3_a7]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8, i8* %src, i64 5
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [85 x i8], [85 x i8]* %[[test3_a7]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 3
 
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %b, i32 300, i32 1, i1 false)
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [42 x i8]* %[[test3_a1]], i64 0, i64 0
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [42 x i8], [42 x i8]* %[[test3_a1]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %[[gep]], i32 42
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %dst, i64 42
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %dst, i64 42
 ; CHECK-NEXT: store i8 0, i8* %[[gep]]
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8* %dst, i64 43
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [99 x i8]* %[[test3_a2]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8, i8* %dst, i64 43
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [99 x i8], [99 x i8]* %[[test3_a2]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 99
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8* %dst, i64 142
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [16 x i8]* %[[test3_a3]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8, i8* %dst, i64 142
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [16 x i8], [16 x i8]* %[[test3_a3]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 16
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8* %dst, i64 158
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [42 x i8]* %[[test3_a4]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8, i8* %dst, i64 158
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [42 x i8], [42 x i8]* %[[test3_a4]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 42
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8* %dst, i64 200
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a5]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8, i8* %dst, i64 200
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a5]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 7
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %dst, i64 207
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %dst, i64 207
 ; CHECK-NEXT: store i8 42, i8* %[[gep]]
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8* %dst, i64 208
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [7 x i8]* %[[test3_a6]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8, i8* %dst, i64 208
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test3_a6]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 7
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8* %dst, i64 215
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [85 x i8]* %[[test3_a7]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8, i8* %dst, i64 215
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [85 x i8], [85 x i8]* %[[test3_a7]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 85
 
   ret void
@@ -314,90 +314,90 @@ entry:
 ; CHECK-NEXT: %[[test4_a5:.*]] = alloca [7 x i8]
 ; CHECK-NEXT: %[[test4_a6:.*]] = alloca [40 x i8]
 
-  %b = getelementptr [100 x i8]* %a, i64 0, i64 0
+  %b = getelementptr [100 x i8], [100 x i8]* %a, i64 0, i64 0
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %b, i8* %src, i32 100, i32 1, i1 false)
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [20 x i8]* %[[test4_a1]], i64 0, i64 0
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [20 x i8], [20 x i8]* %[[test4_a1]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep]], i8* %src, i32 20
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %src, i64 20
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %src, i64 20
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i16*
-; CHECK-NEXT: %[[test4_r1:.*]] = load i16* %[[bitcast]]
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %src, i64 22
-; CHECK-NEXT: %[[test4_r2:.*]] = load i8* %[[gep]]
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8* %src, i64 23
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8]* %[[test4_a2]], i64 0, i64 0
+; CHECK-NEXT: %[[test4_r1:.*]] = load i16, i16* %[[bitcast]]
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %src, i64 22
+; CHECK-NEXT: %[[test4_r2:.*]] = load i8, i8* %[[gep]]
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8, i8* %src, i64 23
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test4_a2]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 7
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8* %src, i64 30
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [10 x i8]* %[[test4_a3]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8, i8* %src, i64 30
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [10 x i8], [10 x i8]* %[[test4_a3]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 10
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %src, i64 40
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %src, i64 40
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i16*
-; CHECK-NEXT: %[[test4_r3:.*]] = load i16* %[[bitcast]]
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %src, i64 42
-; CHECK-NEXT: %[[test4_r4:.*]] = load i8* %[[gep]]
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8* %src, i64 43
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8]* %[[test4_a4]], i64 0, i64 0
+; CHECK-NEXT: %[[test4_r3:.*]] = load i16, i16* %[[bitcast]]
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %src, i64 42
+; CHECK-NEXT: %[[test4_r4:.*]] = load i8, i8* %[[gep]]
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8, i8* %src, i64 43
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test4_a4]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 7
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %src, i64 50
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %src, i64 50
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i16*
-; CHECK-NEXT: %[[test4_r5:.*]] = load i16* %[[bitcast]]
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %src, i64 52
-; CHECK-NEXT: %[[test4_r6:.*]] = load i8* %[[gep]]
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8* %src, i64 53
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8]* %[[test4_a5]], i64 0, i64 0
+; CHECK-NEXT: %[[test4_r5:.*]] = load i16, i16* %[[bitcast]]
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %src, i64 52
+; CHECK-NEXT: %[[test4_r6:.*]] = load i8, i8* %[[gep]]
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8, i8* %src, i64 53
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test4_a5]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 7
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8* %src, i64 60
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [40 x i8]* %[[test4_a6]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds i8, i8* %src, i64 60
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [40 x i8], [40 x i8]* %[[test4_a6]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 40
 
-  %a.src.1 = getelementptr [100 x i8]* %a, i64 0, i64 20
-  %a.dst.1 = getelementptr [100 x i8]* %a, i64 0, i64 40
+  %a.src.1 = getelementptr [100 x i8], [100 x i8]* %a, i64 0, i64 20
+  %a.dst.1 = getelementptr [100 x i8], [100 x i8]* %a, i64 0, i64 40
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a.dst.1, i8* %a.src.1, i32 10, i32 1, i1 false)
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8]* %[[test4_a4]], i64 0, i64 0
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [7 x i8]* %[[test4_a2]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test4_a4]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test4_a2]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 7
 
   ; Clobber a single element of the array, this should be promotable, and be deleted.
-  %c = getelementptr [100 x i8]* %a, i64 0, i64 42
+  %c = getelementptr [100 x i8], [100 x i8]* %a, i64 0, i64 42
   store i8 0, i8* %c
 
-  %a.src.2 = getelementptr [100 x i8]* %a, i64 0, i64 50
+  %a.src.2 = getelementptr [100 x i8], [100 x i8]* %a, i64 0, i64 50
   call void @llvm.memmove.p0i8.p0i8.i32(i8* %a.dst.1, i8* %a.src.2, i32 10, i32 1, i1 false)
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8]* %[[test4_a4]], i64 0, i64 0
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [7 x i8]* %[[test4_a5]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test4_a4]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test4_a5]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 7
 
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %b, i32 100, i32 1, i1 false)
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [20 x i8]* %[[test4_a1]], i64 0, i64 0
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds [20 x i8], [20 x i8]* %[[test4_a1]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %[[gep]], i32 20
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %dst, i64 20
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %dst, i64 20
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i16*
 ; CHECK-NEXT: store i16 %[[test4_r1]], i16* %[[bitcast]]
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %dst, i64 22
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %dst, i64 22
 ; CHECK-NEXT: store i8 %[[test4_r2]], i8* %[[gep]]
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8* %dst, i64 23
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [7 x i8]* %[[test4_a2]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8, i8* %dst, i64 23
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test4_a2]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 7
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8* %dst, i64 30
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [10 x i8]* %[[test4_a3]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8, i8* %dst, i64 30
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [10 x i8], [10 x i8]* %[[test4_a3]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 10
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %dst, i64 40
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %dst, i64 40
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i16*
 ; CHECK-NEXT: store i16 %[[test4_r5]], i16* %[[bitcast]]
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %dst, i64 42
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %dst, i64 42
 ; CHECK-NEXT: store i8 %[[test4_r6]], i8* %[[gep]]
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8* %dst, i64 43
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [7 x i8]* %[[test4_a4]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8, i8* %dst, i64 43
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test4_a4]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 7
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %dst, i64 50
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %dst, i64 50
 ; CHECK-NEXT: %[[bitcast:.*]] = bitcast i8* %[[gep]] to i16*
 ; CHECK-NEXT: store i16 %[[test4_r5]], i16* %[[bitcast]]
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8* %dst, i64 52
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds i8, i8* %dst, i64 52
 ; CHECK-NEXT: store i8 %[[test4_r6]], i8* %[[gep]]
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8* %dst, i64 53
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [7 x i8]* %[[test4_a5]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8, i8* %dst, i64 53
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [7 x i8], [7 x i8]* %[[test4_a5]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 7
-; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8* %dst, i64 60
-; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [40 x i8]* %[[test4_a6]], i64 0, i64 0
+; CHECK-NEXT: %[[gep_dst:.*]] = getelementptr inbounds i8, i8* %dst, i64 60
+; CHECK-NEXT: %[[gep_src:.*]] = getelementptr inbounds [40 x i8], [40 x i8]* %[[test4_a6]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[gep_dst]], i8* %[[gep_src]], i32 40
 
   ret void
@@ -420,9 +420,9 @@ entry:
   %a = alloca [4 x i8]
   %fptr = bitcast [4 x i8]* %a to float*
   store float 0.0, float* %fptr
-  %ptr = getelementptr [4 x i8]* %a, i32 0, i32 2
+  %ptr = getelementptr [4 x i8], [4 x i8]* %a, i32 0, i32 2
   %iptr = bitcast i8* %ptr to i16*
-  %val = load i16* %iptr
+  %val = load i16, i16* %iptr
   ret i16 %val
 }
 
@@ -430,15 +430,15 @@ define i32 @test6() {
 ; CHECK-LABEL: @test6(
 ; CHECK: alloca i32
 ; CHECK-NEXT: store volatile i32
-; CHECK-NEXT: load i32*
+; CHECK-NEXT: load i32, i32*
 ; CHECK-NEXT: ret i32
 
 entry:
   %a = alloca [4 x i8]
-  %ptr = getelementptr [4 x i8]* %a, i32 0, i32 0
+  %ptr = getelementptr [4 x i8], [4 x i8]* %a, i32 0, i32 0
   call void @llvm.memset.p0i8.i32(i8* %ptr, i8 42, i32 4, i32 1, i1 true)
   %iptr = bitcast i8* %ptr to i32*
-  %val = load i32* %iptr
+  %val = load i32, i32* %iptr
   ret i32 %val
 }
 
@@ -446,16 +446,16 @@ define void @test7(i8* %src, i8* %dst) {
 ; CHECK-LABEL: @test7(
 ; CHECK: alloca i32
 ; CHECK-NEXT: bitcast i8* %src to i32*
-; CHECK-NEXT: load volatile i32*
+; CHECK-NEXT: load volatile i32, i32*
 ; CHECK-NEXT: store volatile i32
 ; CHECK-NEXT: bitcast i8* %dst to i32*
-; CHECK-NEXT: load volatile i32*
+; CHECK-NEXT: load volatile i32, i32*
 ; CHECK-NEXT: store volatile i32
 ; CHECK-NEXT: ret
 
 entry:
   %a = alloca [4 x i8]
-  %ptr = getelementptr [4 x i8]* %a, i32 0, i32 0
+  %ptr = getelementptr [4 x i8], [4 x i8]* %a, i32 0, i32 0
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %ptr, i8* %src, i32 4, i32 1, i1 true)
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %ptr, i32 4, i32 1, i1 true)
   ret void
@@ -471,28 +471,28 @@ entry:
   %new = alloca %S2
 ; CHECK-NOT: alloca
 
-  %s2.next.ptr = getelementptr %S2* %s2, i64 0, i32 1
-  %s2.next = load %S2** %s2.next.ptr
-; CHECK:      %[[gep:.*]] = getelementptr %S2* %s2, i64 0, i32 1
-; CHECK-NEXT: %[[next:.*]] = load %S2** %[[gep]]
+  %s2.next.ptr = getelementptr %S2, %S2* %s2, i64 0, i32 1
+  %s2.next = load %S2*, %S2** %s2.next.ptr
+; CHECK:      %[[gep:.*]] = getelementptr %S2, %S2* %s2, i64 0, i32 1
+; CHECK-NEXT: %[[next:.*]] = load %S2*, %S2** %[[gep]]
 
-  %s2.next.s1.ptr = getelementptr %S2* %s2.next, i64 0, i32 0
-  %s2.next.s1 = load %S1** %s2.next.s1.ptr
-  %new.s1.ptr = getelementptr %S2* %new, i64 0, i32 0
+  %s2.next.s1.ptr = getelementptr %S2, %S2* %s2.next, i64 0, i32 0
+  %s2.next.s1 = load %S1*, %S1** %s2.next.s1.ptr
+  %new.s1.ptr = getelementptr %S2, %S2* %new, i64 0, i32 0
   store %S1* %s2.next.s1, %S1** %new.s1.ptr
-  %s2.next.next.ptr = getelementptr %S2* %s2.next, i64 0, i32 1
-  %s2.next.next = load %S2** %s2.next.next.ptr
-  %new.next.ptr = getelementptr %S2* %new, i64 0, i32 1
+  %s2.next.next.ptr = getelementptr %S2, %S2* %s2.next, i64 0, i32 1
+  %s2.next.next = load %S2*, %S2** %s2.next.next.ptr
+  %new.next.ptr = getelementptr %S2, %S2* %new, i64 0, i32 1
   store %S2* %s2.next.next, %S2** %new.next.ptr
-; CHECK-NEXT: %[[gep:.*]] = getelementptr %S2* %[[next]], i64 0, i32 0
-; CHECK-NEXT: %[[next_s1:.*]] = load %S1** %[[gep]]
-; CHECK-NEXT: %[[gep:.*]] = getelementptr %S2* %[[next]], i64 0, i32 1
-; CHECK-NEXT: %[[next_next:.*]] = load %S2** %[[gep]]
+; CHECK-NEXT: %[[gep:.*]] = getelementptr %S2, %S2* %[[next]], i64 0, i32 0
+; CHECK-NEXT: %[[next_s1:.*]] = load %S1*, %S1** %[[gep]]
+; CHECK-NEXT: %[[gep:.*]] = getelementptr %S2, %S2* %[[next]], i64 0, i32 1
+; CHECK-NEXT: %[[next_next:.*]] = load %S2*, %S2** %[[gep]]
 
-  %new.s1 = load %S1** %new.s1.ptr
+  %new.s1 = load %S1*, %S1** %new.s1.ptr
   %result1 = insertvalue %S2 undef, %S1* %new.s1, 0
 ; CHECK-NEXT: %[[result1:.*]] = insertvalue %S2 undef, %S1* %[[next_s1]], 0
-  %new.next = load %S2** %new.next.ptr
+  %new.next = load %S2*, %S2** %new.next.ptr
   %result2 = insertvalue %S2 %result1, %S2* %new.next, 1
 ; CHECK-NEXT: %[[result2:.*]] = insertvalue %S2 %[[result1]], %S2* %[[next_next]], 1
   ret %S2 %result2
@@ -522,15 +522,15 @@ define i64 @test9() {
 
 entry:
   %a = alloca { [3 x i8] }, align 8
-  %gep1 = getelementptr inbounds { [3 x i8] }* %a, i32 0, i32 0, i32 0
+  %gep1 = getelementptr inbounds { [3 x i8] }, { [3 x i8] }* %a, i32 0, i32 0, i32 0
   store i8 0, i8* %gep1, align 1
-  %gep2 = getelementptr inbounds { [3 x i8] }* %a, i32 0, i32 0, i32 1
+  %gep2 = getelementptr inbounds { [3 x i8] }, { [3 x i8] }* %a, i32 0, i32 0, i32 1
   store i8 0, i8* %gep2, align 1
-  %gep3 = getelementptr inbounds { [3 x i8] }* %a, i32 0, i32 0, i32 2
+  %gep3 = getelementptr inbounds { [3 x i8] }, { [3 x i8] }* %a, i32 0, i32 0, i32 2
   store i8 26, i8* %gep3, align 1
   %cast = bitcast { [3 x i8] }* %a to { i64 }*
-  %elt = getelementptr inbounds { i64 }* %cast, i32 0, i32 0
-  %load = load i64* %elt
+  %elt = getelementptr inbounds { i64 }, { i64 }* %cast, i32 0, i32 0
+  %load = load i64, i64* %elt
   %result = and i64 %load, 16777215
   ret i64 %result
 }
@@ -542,10 +542,10 @@ define %S2* @test10() {
 
 entry:
   %a = alloca [8 x i8]
-  %ptr = getelementptr [8 x i8]* %a, i32 0, i32 0
+  %ptr = getelementptr [8 x i8], [8 x i8]* %a, i32 0, i32 0
   call void @llvm.memset.p0i8.i32(i8* %ptr, i8 0, i32 8, i32 1, i1 false)
   %s2ptrptr = bitcast i8* %ptr to %S2**
-  %s2ptr = load %S2** %s2ptrptr
+  %s2ptr = load %S2*, %S2** %s2ptrptr
   ret %S2* %s2ptr
 }
 
@@ -559,15 +559,15 @@ entry:
   br i1 undef, label %good, label %bad
 
 good:
-  %Y = getelementptr i32* %X, i64 0
+  %Y = getelementptr i32, i32* %X, i64 0
   store i32 0, i32* %Y
-  %Z = load i32* %Y
+  %Z = load i32, i32* %Y
   ret i32 %Z
 
 bad:
-  %Y2 = getelementptr i32* %X, i64 1
+  %Y2 = getelementptr i32, i32* %X, i64 1
   store i32 0, i32* %Y2
-  %Z2 = load i32* %Y2
+  %Z2 = load i32, i32* %Y2
   ret i32 %Z2
 }
 
@@ -582,14 +582,14 @@ entry:
   %b = alloca [3 x i8]
 ; CHECK-NOT: alloca
 
-  %a0ptr = getelementptr [3 x i8]* %a, i64 0, i32 0
+  %a0ptr = getelementptr [3 x i8], [3 x i8]* %a, i64 0, i32 0
   store i8 0, i8* %a0ptr
-  %a1ptr = getelementptr [3 x i8]* %a, i64 0, i32 1
+  %a1ptr = getelementptr [3 x i8], [3 x i8]* %a, i64 0, i32 1
   store i8 0, i8* %a1ptr
-  %a2ptr = getelementptr [3 x i8]* %a, i64 0, i32 2
+  %a2ptr = getelementptr [3 x i8], [3 x i8]* %a, i64 0, i32 2
   store i8 0, i8* %a2ptr
   %aiptr = bitcast [3 x i8]* %a to i24*
-  %ai = load i24* %aiptr
+  %ai = load i24, i24* %aiptr
 ; CHECK-NOT: store
 ; CHECK-NOT: load
 ; CHECK:      %[[ext2:.*]] = zext i8 0 to i24
@@ -606,12 +606,12 @@ entry:
 
   %biptr = bitcast [3 x i8]* %b to i24*
   store i24 %ai, i24* %biptr
-  %b0ptr = getelementptr [3 x i8]* %b, i64 0, i32 0
-  %b0 = load i8* %b0ptr
-  %b1ptr = getelementptr [3 x i8]* %b, i64 0, i32 1
-  %b1 = load i8* %b1ptr
-  %b2ptr = getelementptr [3 x i8]* %b, i64 0, i32 2
-  %b2 = load i8* %b2ptr
+  %b0ptr = getelementptr [3 x i8], [3 x i8]* %b, i64 0, i32 0
+  %b0 = load i8, i8* %b0ptr
+  %b1ptr = getelementptr [3 x i8], [3 x i8]* %b, i64 0, i32 1
+  %b1 = load i8, i8* %b1ptr
+  %b2ptr = getelementptr [3 x i8], [3 x i8]* %b, i64 0, i32 2
+  %b2 = load i8, i8* %b2ptr
 ; CHECK-NOT: store
 ; CHECK-NOT: load
 ; CHECK:      %[[trunc0:.*]] = trunc i24 %[[insert0]] to i8
@@ -638,15 +638,15 @@ define i32 @test13() {
 
 entry:
   %a = alloca [3 x i8], align 2
-  %b0ptr = getelementptr [3 x i8]* %a, i64 0, i32 0
+  %b0ptr = getelementptr [3 x i8], [3 x i8]* %a, i64 0, i32 0
   store i8 0, i8* %b0ptr
-  %b1ptr = getelementptr [3 x i8]* %a, i64 0, i32 1
+  %b1ptr = getelementptr [3 x i8], [3 x i8]* %a, i64 0, i32 1
   store i8 0, i8* %b1ptr
-  %b2ptr = getelementptr [3 x i8]* %a, i64 0, i32 2
+  %b2ptr = getelementptr [3 x i8], [3 x i8]* %a, i64 0, i32 2
   store i8 0, i8* %b2ptr
   %iptrcast = bitcast [3 x i8]* %a to i16*
-  %iptrgep = getelementptr i16* %iptrcast, i64 1
-  %i = load i16* %iptrgep
+  %iptrgep = getelementptr i16, i16* %iptrcast, i64 1
+  %i = load i16, i16* %iptrgep
   %ret = zext i16 %i to i32
   ret i32 %ret
 }
@@ -666,21 +666,21 @@ entry:
   %a = alloca %test14.struct
   %p = alloca %test14.struct*
   %0 = bitcast %test14.struct* %a to i8*
-  %1 = getelementptr i8* %0, i64 12
+  %1 = getelementptr i8, i8* %0, i64 12
   %2 = bitcast i8* %1 to %test14.struct*
-  %3 = getelementptr inbounds %test14.struct* %2, i32 0, i32 0
-  %4 = getelementptr inbounds %test14.struct* %a, i32 0, i32 0
+  %3 = getelementptr inbounds %test14.struct, %test14.struct* %2, i32 0, i32 0
+  %4 = getelementptr inbounds %test14.struct, %test14.struct* %a, i32 0, i32 0
   %5 = bitcast [3 x i32]* %3 to i32*
   %6 = bitcast [3 x i32]* %4 to i32*
-  %7 = load i32* %6, align 4
+  %7 = load i32, i32* %6, align 4
   store i32 %7, i32* %5, align 4
-  %8 = getelementptr inbounds i32* %5, i32 1
-  %9 = getelementptr inbounds i32* %6, i32 1
-  %10 = load i32* %9, align 4
+  %8 = getelementptr inbounds i32, i32* %5, i32 1
+  %9 = getelementptr inbounds i32, i32* %6, i32 1
+  %10 = load i32, i32* %9, align 4
   store i32 %10, i32* %8, align 4
-  %11 = getelementptr inbounds i32* %5, i32 2
-  %12 = getelementptr inbounds i32* %6, i32 2
-  %13 = load i32* %12, align 4
+  %11 = getelementptr inbounds i32, i32* %5, i32 2
+  %12 = getelementptr inbounds i32, i32* %6, i32 2
+  %13 = load i32, i32* %12, align 4
   store i32 %13, i32* %11, align 4
   ret void
 }
@@ -707,25 +707,25 @@ loop:
 
   store i64 1879048192, i64* %l0, align 8
   %bc0 = bitcast i64* %l0 to i8*
-  %gep0 = getelementptr i8* %bc0, i64 3
+  %gep0 = getelementptr i8, i8* %bc0, i64 3
   %dead0 = bitcast i8* %gep0 to i64*
 
   store i64 1879048192, i64* %l1, align 8
   %bc1 = bitcast i64* %l1 to i8*
-  %gep1 = getelementptr i8* %bc1, i64 3
-  %dead1 = getelementptr i8* %gep1, i64 1
+  %gep1 = getelementptr i8, i8* %bc1, i64 3
+  %dead1 = getelementptr i8, i8* %gep1, i64 1
 
   store i64 1879048192, i64* %l2, align 8
   %bc2 = bitcast i64* %l2 to i8*
-  %gep2.1 = getelementptr i8* %bc2, i64 1
-  %gep2.2 = getelementptr i8* %bc2, i64 3
+  %gep2.1 = getelementptr i8, i8* %bc2, i64 1
+  %gep2.2 = getelementptr i8, i8* %bc2, i64 3
   ; Note that this select should get visited multiple times due to using two
   ; different GEPs off the same alloca. We should only delete it once.
   %dead2 = select i1 %flag, i8* %gep2.1, i8* %gep2.2
 
   store i64 1879048192, i64* %l3, align 8
   %bc3 = bitcast i64* %l3 to i8*
-  %gep3 = getelementptr i8* %bc3, i64 3
+  %gep3 = getelementptr i8, i8* %bc3, i64 3
 
   br label %loop
 }
@@ -735,14 +735,14 @@ define void @test16(i8* %src, i8* %dst) {
 ; CHECK-LABEL: @test16(
 ; CHECK-NOT: alloca
 ; CHECK:      %[[srccast:.*]] = bitcast i8* %src to i24*
-; CHECK-NEXT: load i24* %[[srccast]]
+; CHECK-NEXT: load i24, i24* %[[srccast]]
 ; CHECK-NEXT: %[[dstcast:.*]] = bitcast i8* %dst to i24*
 ; CHECK-NEXT: store i24 0, i24* %[[dstcast]]
 ; CHECK-NEXT: ret void
 
 entry:
   %a = alloca [3 x i8]
-  %ptr = getelementptr [3 x i8]* %a, i32 0, i32 0
+  %ptr = getelementptr [3 x i8], [3 x i8]* %a, i32 0, i32 0
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %ptr, i8* %src, i32 4, i32 1, i1 false)
   %cast = bitcast i8* %ptr to i24*
   store i24 0, i24* %cast
@@ -755,14 +755,14 @@ define void @test17(i8* %src, i8* %dst) {
 ; the alloca.
 ; CHECK-LABEL: @test17(
 ; CHECK:      %[[a:.*]] = alloca [3 x i8]
-; CHECK-NEXT: %[[ptr:.*]] = getelementptr [3 x i8]* %[[a]], i32 0, i32 0
+; CHECK-NEXT: %[[ptr:.*]] = getelementptr [3 x i8], [3 x i8]* %[[a]], i32 0, i32 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[ptr]], i8* %src,
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %[[ptr]],
 ; CHECK-NEXT: ret void
 
 entry:
   %a = alloca [3 x i8]
-  %ptr = getelementptr [3 x i8]* %a, i32 0, i32 0
+  %ptr = getelementptr [3 x i8], [3 x i8]* %a, i32 0, i32 0
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %ptr, i8* %src, i32 4, i32 1, i1 true)
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %ptr, i32 4, i32 1, i1 true)
   ret void
@@ -774,27 +774,27 @@ define void @test18(i8* %src, i8* %dst, i32 %size) {
 ; the variable sized intrinsic.
 ; CHECK-LABEL: @test18(
 ; CHECK:      %[[a:.*]] = alloca [34 x i8]
-; CHECK:      %[[srcgep1:.*]] = getelementptr inbounds i8* %src, i64 4
+; CHECK:      %[[srcgep1:.*]] = getelementptr inbounds i8, i8* %src, i64 4
 ; CHECK-NEXT: %[[srccast1:.*]] = bitcast i8* %[[srcgep1]] to i32*
-; CHECK-NEXT: %[[srcload:.*]] = load i32* %[[srccast1]]
-; CHECK-NEXT: %[[agep1:.*]] = getelementptr inbounds [34 x i8]* %[[a]], i64 0, i64 0
+; CHECK-NEXT: %[[srcload:.*]] = load i32, i32* %[[srccast1]]
+; CHECK-NEXT: %[[agep1:.*]] = getelementptr inbounds [34 x i8], [34 x i8]* %[[a]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[agep1]], i8* %src, i32 %size,
-; CHECK-NEXT: %[[agep2:.*]] = getelementptr inbounds [34 x i8]* %[[a]], i64 0, i64 0
+; CHECK-NEXT: %[[agep2:.*]] = getelementptr inbounds [34 x i8], [34 x i8]* %[[a]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* %[[agep2]], i8 42, i32 %size,
 ; CHECK-NEXT: %[[dstcast1:.*]] = bitcast i8* %dst to i32*
 ; CHECK-NEXT: store i32 42, i32* %[[dstcast1]]
-; CHECK-NEXT: %[[dstgep1:.*]] = getelementptr inbounds i8* %dst, i64 4
+; CHECK-NEXT: %[[dstgep1:.*]] = getelementptr inbounds i8, i8* %dst, i64 4
 ; CHECK-NEXT: %[[dstcast2:.*]] = bitcast i8* %[[dstgep1]] to i32*
 ; CHECK-NEXT: store i32 %[[srcload]], i32* %[[dstcast2]]
-; CHECK-NEXT: %[[agep3:.*]] = getelementptr inbounds [34 x i8]* %[[a]], i64 0, i64 0
+; CHECK-NEXT: %[[agep3:.*]] = getelementptr inbounds [34 x i8], [34 x i8]* %[[a]], i64 0, i64 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %[[agep3]], i32 %size,
 ; CHECK-NEXT: ret void
 
 entry:
   %a = alloca [42 x i8]
-  %ptr = getelementptr [42 x i8]* %a, i32 0, i32 0
+  %ptr = getelementptr [42 x i8], [42 x i8]* %a, i32 0, i32 0
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %ptr, i8* %src, i32 8, i32 1, i1 false)
-  %ptr2 = getelementptr [42 x i8]* %a, i32 0, i32 8
+  %ptr2 = getelementptr [42 x i8], [42 x i8]* %a, i32 0, i32 8
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %ptr2, i8* %src, i32 %size, i32 1, i1 false)
   call void @llvm.memset.p0i8.i32(i8* %ptr2, i8 42, i32 %size, i32 1, i1 false)
   %cast = bitcast i8* %ptr to i32*
@@ -820,8 +820,8 @@ entry:
   %cast1 = bitcast %opaque* %x to i8*
   %cast2 = bitcast { i64, i8* }* %a to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %cast2, i8* %cast1, i32 16, i32 1, i1 false)
-  %gep = getelementptr inbounds { i64, i8* }* %a, i32 0, i32 0
-  %val = load i64* %gep
+  %gep = getelementptr inbounds { i64, i8* }, { i64, i8* }* %a, i32 0, i32 0
+  %val = load i64, i64* %gep
   ret i32 undef
 }
 
@@ -836,18 +836,18 @@ define i32 @test20() {
 
 entry:
   %a = alloca [3 x i32]
-  %gep1 = getelementptr [3 x i32]* %a, i32 0, i32 0
+  %gep1 = getelementptr [3 x i32], [3 x i32]* %a, i32 0, i32 0
   store i32 1, i32* %gep1
-  %gep2.1 = getelementptr [3 x i32]* %a, i32 0, i32 -2
-  %gep2.2 = getelementptr i32* %gep2.1, i32 3
+  %gep2.1 = getelementptr [3 x i32], [3 x i32]* %a, i32 0, i32 -2
+  %gep2.2 = getelementptr i32, i32* %gep2.1, i32 3
   store i32 2, i32* %gep2.2
-  %gep3.1 = getelementptr [3 x i32]* %a, i32 0, i32 14
-  %gep3.2 = getelementptr i32* %gep3.1, i32 -12
+  %gep3.1 = getelementptr [3 x i32], [3 x i32]* %a, i32 0, i32 14
+  %gep3.2 = getelementptr i32, i32* %gep3.1, i32 -12
   store i32 3, i32* %gep3.2
 
-  %load1 = load i32* %gep1
-  %load2 = load i32* %gep2.2
-  %load3 = load i32* %gep3.2
+  %load1 = load i32, i32* %gep1
+  %load2 = load i32, i32* %gep2.2
+  %load3 = load i32, i32* %gep3.2
   %sum1 = add i32 %load1, %load2
   %sum2 = add i32 %sum1, %load3
   ret i32 %sum2
@@ -865,20 +865,20 @@ define i8 @test21() {
 
 entry:
   %a = alloca [2305843009213693951 x i8]
-  %gep0 = getelementptr [2305843009213693951 x i8]* %a, i64 0, i64 2305843009213693949
+  %gep0 = getelementptr [2305843009213693951 x i8], [2305843009213693951 x i8]* %a, i64 0, i64 2305843009213693949
   store i8 255, i8* %gep0
-  %gep1 = getelementptr [2305843009213693951 x i8]* %a, i64 0, i64 -9223372036854775807
-  %gep2 = getelementptr i8* %gep1, i64 -1
+  %gep1 = getelementptr [2305843009213693951 x i8], [2305843009213693951 x i8]* %a, i64 0, i64 -9223372036854775807
+  %gep2 = getelementptr i8, i8* %gep1, i64 -1
   call void @llvm.memset.p0i8.i64(i8* %gep2, i8 0, i64 18446744073709551615, i32 1, i1 false)
-  %gep3 = getelementptr i8* %gep1, i64 9223372036854775807
-  %gep4 = getelementptr i8* %gep3, i64 9223372036854775807
-  %gep5 = getelementptr i8* %gep4, i64 -6917529027641081857
+  %gep3 = getelementptr i8, i8* %gep1, i64 9223372036854775807
+  %gep4 = getelementptr i8, i8* %gep3, i64 9223372036854775807
+  %gep5 = getelementptr i8, i8* %gep4, i64 -6917529027641081857
   store i8 255, i8* %gep5
   %cast1 = bitcast i8* %gep4 to i32*
   store i32 0, i32* %cast1
-  %load = load i8* %gep0
-  %gep6 = getelementptr i8* %gep0, i32 1
-  %load2 = load i8* %gep6
+  %load = load i8, i8* %gep0
+  %gep6 = getelementptr i8, i8* %gep0, i32 1
+  %load2 = load i8, i8* %gep6
   %result = or i8 %load, %load2
   ret i8 %result
 }
@@ -895,7 +895,7 @@ define void @PR13916.1() {
 entry:
   %a = alloca i8
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a, i8* %a, i32 1, i32 1, i1 false)
-  %tmp2 = load i8* %a
+  %tmp2 = load i8, i8* %a
   ret void
 }
 
@@ -918,8 +918,8 @@ if.then:
   br label %if.end
 
 if.end:
-  %gep = getelementptr %PR13916.struct* %a, i32 0, i32 0
-  %tmp2 = load i8* %gep
+  %gep = getelementptr %PR13916.struct, %PR13916.struct* %a, i32 0, i32 0
+  %tmp2 = load i8, i8* %gep
   ret void
 }
 
@@ -968,7 +968,7 @@ entry:
   store double* %c, double** %b
   store double* %a, double** %b
   store double %x, double* %c
-  %ret = load double* %a
+  %ret = load double, double* %a
 ; CHECK-NOT: store
 ; CHECK-NOT: load
 
@@ -987,8 +987,8 @@ define void @PR14034() {
 
 entry:
   %a = alloca %PR14034.struct
-  %list = getelementptr %PR14034.struct* %a, i32 0, i32 2
-  %prev = getelementptr %PR14034.list* %list, i32 0, i32 1
+  %list = getelementptr %PR14034.struct, %PR14034.struct* %a, i32 0, i32 2
+  %prev = getelementptr %PR14034.list, %PR14034.list* %list, i32 0, i32 1
   store %PR14034.list* undef, %PR14034.list** %prev
   %cast0 = bitcast %PR14034.struct* undef to i8*
   %cast1 = bitcast %PR14034.struct* %a to i8*
@@ -1008,31 +1008,31 @@ entry:
 ; CHECK-NOT: alloca
 
   %wrap1 = insertvalue [1 x { i32 }] undef, i32 %x, 0, 0
-  %gep1 = getelementptr { { [1 x { i32 }] } }* %a1, i32 0, i32 0, i32 0
+  %gep1 = getelementptr { { [1 x { i32 }] } }, { { [1 x { i32 }] } }* %a1, i32 0, i32 0, i32 0
   store [1 x { i32 }] %wrap1, [1 x { i32 }]* %gep1
 
-  %gep2 = getelementptr { { [1 x { i32 }] } }* %a1, i32 0, i32 0
+  %gep2 = getelementptr { { [1 x { i32 }] } }, { { [1 x { i32 }] } }* %a1, i32 0, i32 0
   %ptrcast1 = bitcast { [1 x { i32 }] }* %gep2 to { [1 x { float }] }*
-  %load1 = load { [1 x { float }] }* %ptrcast1
+  %load1 = load { [1 x { float }] }, { [1 x { float }] }* %ptrcast1
   %unwrap1 = extractvalue { [1 x { float }] } %load1, 0, 0
 
   %wrap2 = insertvalue { {}, { float }, [0 x i8] } undef, { float } %unwrap1, 1
   store { {}, { float }, [0 x i8] } %wrap2, { {}, { float }, [0 x i8] }* %a2
 
-  %gep3 = getelementptr { {}, { float }, [0 x i8] }* %a2, i32 0, i32 1, i32 0
+  %gep3 = getelementptr { {}, { float }, [0 x i8] }, { {}, { float }, [0 x i8] }* %a2, i32 0, i32 1, i32 0
   %ptrcast2 = bitcast float* %gep3 to <4 x i8>*
-  %load3 = load <4 x i8>* %ptrcast2
+  %load3 = load <4 x i8>, <4 x i8>* %ptrcast2
   %valcast1 = bitcast <4 x i8> %load3 to i32
 
   %wrap3 = insertvalue [1 x [1 x i32]] undef, i32 %valcast1, 0, 0
   %wrap4 = insertvalue { [1 x [1 x i32]], {} } undef, [1 x [1 x i32]] %wrap3, 0
-  %gep4 = getelementptr { [0 x i8], { [0 x double], [1 x [1 x <4 x i8>]], {} }, { { {} } } }* %a3, i32 0, i32 1
+  %gep4 = getelementptr { [0 x i8], { [0 x double], [1 x [1 x <4 x i8>]], {} }, { { {} } } }, { [0 x i8], { [0 x double], [1 x [1 x <4 x i8>]], {} }, { { {} } } }* %a3, i32 0, i32 1
   %ptrcast3 = bitcast { [0 x double], [1 x [1 x <4 x i8>]], {} }* %gep4 to { [1 x [1 x i32]], {} }*
   store { [1 x [1 x i32]], {} } %wrap4, { [1 x [1 x i32]], {} }* %ptrcast3
 
-  %gep5 = getelementptr { [0 x i8], { [0 x double], [1 x [1 x <4 x i8>]], {} }, { { {} } } }* %a3, i32 0, i32 1, i32 1, i32 0
+  %gep5 = getelementptr { [0 x i8], { [0 x double], [1 x [1 x <4 x i8>]], {} }, { { {} } } }, { [0 x i8], { [0 x double], [1 x [1 x <4 x i8>]], {} }, { { {} } } }* %a3, i32 0, i32 1, i32 1, i32 0
   %ptrcast4 = bitcast [1 x <4 x i8>]* %gep5 to { {}, float, {} }*
-  %load4 = load { {}, float, {} }* %ptrcast4
+  %load4 = load { {}, float, {} }, { {}, float, {} }* %ptrcast4
   %unwrap2 = extractvalue { {}, float, {} } %load4, 1
   %valcast2 = bitcast float %unwrap2 to i32
 
@@ -1064,14 +1064,14 @@ entry:
   store i32 0, i32* %X.sroa.0.0.cast2.i, align 8
 
   ; Also use a memset to the middle 32-bits for fun.
-  %X.sroa.0.2.raw_idx2.i = getelementptr inbounds i8* %0, i32 2
+  %X.sroa.0.2.raw_idx2.i = getelementptr inbounds i8, i8* %0, i32 2
   call void @llvm.memset.p0i8.i64(i8* %X.sroa.0.2.raw_idx2.i, i8 0, i64 4, i32 1, i1 false)
 
   ; Or a memset of the whole thing.
   call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 8, i32 1, i1 false)
 
   ; Write to the high 32-bits with a memcpy.
-  %X.sroa.0.4.raw_idx4.i = getelementptr inbounds i8* %0, i32 4
+  %X.sroa.0.4.raw_idx4.i = getelementptr inbounds i8, i8* %0, i32 4
   %d.raw = bitcast double* %d to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %X.sroa.0.4.raw_idx4.i, i8* %d.raw, i32 4, i32 1, i1 false)
 
@@ -1080,8 +1080,8 @@ entry:
   store i32 1072693248, i32* %X.sroa.0.4.cast5.i, align 4
 
   ; Do the actual math...
-  %X.sroa.0.0.load1.i = load double* %X.sroa.0.i, align 8
-  %accum.real.i = load double* %d, align 8
+  %X.sroa.0.0.load1.i = load double, double* %X.sroa.0.i, align 8
+  %accum.real.i = load double, double* %d, align 8
   %add.r.i = fadd double %accum.real.i, %X.sroa.0.0.load1.i
   store double %add.r.i, double* %d, align 8
   call void @llvm.lifetime.end(i64 -1, i8* %0)
@@ -1103,17 +1103,17 @@ entry:
   store i64 0, i64* %0
   ; CHECK-NOT: store
 
-  %phi.realp = getelementptr inbounds { float, float }* %phi, i32 0, i32 0
-  %phi.real = load float* %phi.realp
-  %phi.imagp = getelementptr inbounds { float, float }* %phi, i32 0, i32 1
-  %phi.imag = load float* %phi.imagp
-  ; CHECK:      %[[realp:.*]] = getelementptr inbounds { float, float }* %phi, i32 0, i32 0
-  ; CHECK-NEXT: %[[real:.*]] = load float* %[[realp]]
-  ; CHECK-NEXT: %[[imagp:.*]] = getelementptr inbounds { float, float }* %phi, i32 0, i32 1
-  ; CHECK-NEXT: %[[imag:.*]] = load float* %[[imagp]]
-
-  %real = getelementptr inbounds { float, float }* %retval, i32 0, i32 0
-  %imag = getelementptr inbounds { float, float }* %retval, i32 0, i32 1
+  %phi.realp = getelementptr inbounds { float, float }, { float, float }* %phi, i32 0, i32 0
+  %phi.real = load float, float* %phi.realp
+  %phi.imagp = getelementptr inbounds { float, float }, { float, float }* %phi, i32 0, i32 1
+  %phi.imag = load float, float* %phi.imagp
+  ; CHECK:      %[[realp:.*]] = getelementptr inbounds { float, float }, { float, float }* %phi, i32 0, i32 0
+  ; CHECK-NEXT: %[[real:.*]] = load float, float* %[[realp]]
+  ; CHECK-NEXT: %[[imagp:.*]] = getelementptr inbounds { float, float }, { float, float }* %phi, i32 0, i32 1
+  ; CHECK-NEXT: %[[imag:.*]] = load float, float* %[[imagp]]
+
+  %real = getelementptr inbounds { float, float }, { float, float }* %retval, i32 0, i32 0
+  %imag = getelementptr inbounds { float, float }, { float, float }* %retval, i32 0, i32 1
   store float %phi.real, float* %real
   store float %phi.imag, float* %imag
   ; CHECK-NEXT: %[[real_convert:.*]] = bitcast float %[[real]] to i32
@@ -1126,7 +1126,7 @@ entry:
   ; CHECK-NEXT: %[[real_mask:.*]] = and i64 %[[imag_insert]], -4294967296
   ; CHECK-NEXT: %[[real_insert:.*]] = or i64 %[[real_mask]], %[[real_ext]]
 
-  %1 = load i64* %0, align 1
+  %1 = load i64, i64* %0, align 1
   ret i64 %1
   ; CHECK-NEXT: ret i64 %[[real_insert]]
 }
@@ -1141,8 +1141,8 @@ entry:
   %a = alloca { [16 x i8] }, align 8
 ; CHECK: alloca [16 x i8], align 8
 
-  %gep = getelementptr inbounds { [16 x i8] }* %ptr, i64 -1
-; CHECK-NEXT: getelementptr inbounds { [16 x i8] }* %ptr, i64 -1, i32 0, i64 0
+  %gep = getelementptr inbounds { [16 x i8] }, { [16 x i8] }* %ptr, i64 -1
+; CHECK-NEXT: getelementptr inbounds { [16 x i8] }, { [16 x i8] }* %ptr, i64 -1, i32 0, i64 0
 
   %cast1 = bitcast { [16 x i8 ] }* %gep to i8*
   %cast2 = bitcast { [16 x i8 ] }* %a to i8*
@@ -1159,8 +1159,8 @@ entry:
   %a = alloca { [16 x i8] }, align 8
 ; CHECK: alloca [16 x i8], align 8
 
-  %gep = getelementptr inbounds { [16 x i8] } addrspace(1)* %ptr, i64 -1
-; CHECK-NEXT: getelementptr inbounds { [16 x i8] } addrspace(1)* %ptr, i16 -1, i32 0, i16 0
+  %gep = getelementptr inbounds { [16 x i8] }, { [16 x i8] } addrspace(1)* %ptr, i64 -1
+; CHECK-NEXT: getelementptr inbounds { [16 x i8] }, { [16 x i8] } addrspace(1)* %ptr, i16 -1, i32 0, i16 0
 
   %cast1 = bitcast { [16 x i8 ] } addrspace(1)* %gep to i8 addrspace(1)*
   %cast2 = bitcast { [16 x i8 ] }* %a to i8*
@@ -1199,18 +1199,18 @@ entry:
   %b.i1 = bitcast <{ i1 }>* %b to i1*
   store i1 %x, i1* %b.i1, align 8
   %b.i8 = bitcast <{ i1 }>* %b to i8*
-  %foo = load i8* %b.i8, align 1
+  %foo = load i8, i8* %b.i8, align 1
 ; CHECK-NEXT: %[[ext:.*]] = zext i1 %x to i8
 ; CHECK-NEXT: store i8 %[[ext]], i8* %[[a]], align 8
-; CHECK-NEXT: {{.*}} = load i8* %[[a]], align 8
+; CHECK-NEXT: {{.*}} = load i8, i8* %[[a]], align 8
 
   %a.i8 = bitcast <{ i1 }>* %a to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a.i8, i8* %b.i8, i32 1, i32 1, i1 false) nounwind
-  %bar = load i8* %a.i8, align 1
-  %a.i1 = getelementptr inbounds <{ i1 }>* %a, i32 0, i32 0
-  %baz = load i1* %a.i1, align 1
+  %bar = load i8, i8* %a.i8, align 1
+  %a.i1 = getelementptr inbounds <{ i1 }>, <{ i1 }>* %a, i32 0, i32 0
+  %baz = load i1, i1* %a.i1, align 1
 ; CHECK-NEXT: %[[a_cast:.*]] = bitcast i8* %[[a]] to i1*
-; CHECK-NEXT: {{.*}} = load i1* %[[a_cast]], align 8
+; CHECK-NEXT: {{.*}} = load i1, i1* %[[a_cast]], align 8
 
   ret void
 }
@@ -1226,7 +1226,7 @@ entry:
 
   %cast = bitcast <3 x i8>* %a to i32*
   store i32 %x, i32* %cast, align 1
-  %y = load <3 x i8>* %a, align 4
+  %y = load <3 x i8>, <3 x i8>* %a, align 4
   ret <3 x i8> %y
 ; CHECK: ret <3 x i8>
 }
@@ -1242,7 +1242,7 @@ entry:
 
   store <3 x i8> %x, <3 x i8>* %a, align 1
   %cast = bitcast <3 x i8>* %a to i32*
-  %y = load i32* %cast, align 4
+  %y = load i32, i32* %cast, align 4
   ret i32 %y
 ; CHECK: ret i32
 }
@@ -1258,7 +1258,7 @@ entry:
 
   %a.i8 = bitcast i32* %a to i8*
   call void @llvm.memset.p0i8.i32(i8* %a.i8, i8 0, i32 %x, i32 1, i1 false)
-  %v = load i32* %a
+  %v = load i32, i32* %a
   ret i32 %v
 }
 
@@ -1282,36 +1282,36 @@ entry:
   ]
 
 bb4:
-  %src.gep3 = getelementptr inbounds i8* %src, i32 3
-  %src.3 = load i8* %src.gep3
-  %tmp.gep3 = getelementptr inbounds [4 x i8]* %tmp, i32 0, i32 3
+  %src.gep3 = getelementptr inbounds i8, i8* %src, i32 3
+  %src.3 = load i8, i8* %src.gep3
+  %tmp.gep3 = getelementptr inbounds [4 x i8], [4 x i8]* %tmp, i32 0, i32 3
   store i8 %src.3, i8* %tmp.gep3
 ; CHECK: store i8
 
   br label %bb3
 
 bb3:
-  %src.gep2 = getelementptr inbounds i8* %src, i32 2
-  %src.2 = load i8* %src.gep2
-  %tmp.gep2 = getelementptr inbounds [4 x i8]* %tmp, i32 0, i32 2
+  %src.gep2 = getelementptr inbounds i8, i8* %src, i32 2
+  %src.2 = load i8, i8* %src.gep2
+  %tmp.gep2 = getelementptr inbounds [4 x i8], [4 x i8]* %tmp, i32 0, i32 2
   store i8 %src.2, i8* %tmp.gep2
 ; CHECK: store i8
 
   br label %bb2
 
 bb2:
-  %src.gep1 = getelementptr inbounds i8* %src, i32 1
-  %src.1 = load i8* %src.gep1
-  %tmp.gep1 = getelementptr inbounds [4 x i8]* %tmp, i32 0, i32 1
+  %src.gep1 = getelementptr inbounds i8, i8* %src, i32 1
+  %src.1 = load i8, i8* %src.gep1
+  %tmp.gep1 = getelementptr inbounds [4 x i8], [4 x i8]* %tmp, i32 0, i32 1
   store i8 %src.1, i8* %tmp.gep1
 ; CHECK: store i8
 
   br label %bb1
 
 bb1:
-  %src.gep0 = getelementptr inbounds i8* %src, i32 0
-  %src.0 = load i8* %src.gep0
-  %tmp.gep0 = getelementptr inbounds [4 x i8]* %tmp, i32 0, i32 0
+  %src.gep0 = getelementptr inbounds i8, i8* %src, i32 0
+  %src.0 = load i8, i8* %src.gep0
+  %tmp.gep0 = getelementptr inbounds [4 x i8], [4 x i8]* %tmp, i32 0, i32 0
   store i8 %src.0, i8* %tmp.gep0
 ; CHECK: store i8
 
@@ -1332,7 +1332,7 @@ define void @PR15805(i1 %a, i1 %b) {
   %c = alloca i64, align 8
   %p.0.c = select i1 undef, i64* %c, i64* %c
   %cond.in = select i1 undef, i64* %p.0.c, i64* %c
-  %cond = load i64* %cond.in, align 8
+  %cond = load i64, i64* %cond.in, align 8
   ret void
 }
 
@@ -1351,7 +1351,7 @@ define void @PR15805.1(i1 %a, i1 %b) {
 loop:
   %cond.in = select i1 undef, i64* %c, i64* %p.0.c
   %p.0.c = select i1 undef, i64* %c, i64* %c
-  %cond = load i64* %cond.in, align 8
+  %cond = load i64, i64* %cond.in, align 8
   br i1 undef, label %loop, label %exit
 
 exit:
@@ -1373,8 +1373,8 @@ entry:
   %b = alloca i32, align 4
   %b.cast = bitcast i32* %b to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %b.cast, i8* %a, i32 4, i32 4, i1 true)
-  %b.gep = getelementptr inbounds i8* %b.cast, i32 2
-  load i8* %b.gep, align 2
+  %b.gep = getelementptr inbounds i8, i8* %b.cast, i32 2
+  load i8, i8* %b.gep, align 2
   unreachable
 }
 
@@ -1390,11 +1390,11 @@ define void @PR16651.2() {
 
 entry:
   %tv1 = alloca { <2 x float>, <2 x float> }, align 8
-  %0 = getelementptr { <2 x float>, <2 x float> }* %tv1, i64 0, i32 1
+  %0 = getelementptr { <2 x float>, <2 x float> }, { <2 x float>, <2 x float> }* %tv1, i64 0, i32 1
   store <2 x float> undef, <2 x float>* %0, align 8
-  %1 = getelementptr inbounds { <2 x float>, <2 x float> }* %tv1, i64 0, i32 1, i64 0
+  %1 = getelementptr inbounds { <2 x float>, <2 x float> }, { <2 x float>, <2 x float> }* %tv1, i64 0, i32 1, i64 0
   %cond105.in.i.i = select i1 undef, float* null, float* %1
-  %cond105.i.i = load float* %cond105.in.i.i, align 8
+  %cond105.i.i = load float, float* %cond105.in.i.i, align 8
   ret void
 }
 
@@ -1405,8 +1405,8 @@ define void @test23(i32 %x) {
 entry:
   %a = alloca i32, align 4
   store i32 %x, i32* %a, align 4
-  %gep1 = getelementptr inbounds i32* %a, i32 1
-  %gep0 = getelementptr inbounds i32* %a, i32 0
+  %gep1 = getelementptr inbounds i32, i32* %a, i32 1
+  %gep0 = getelementptr inbounds i32, i32* %a, i32 0
   %cast1 = bitcast i32* %gep1 to i8*
   %cast0 = bitcast i32* %gep0 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %cast1, i8* %cast0, i32 4, i32 1, i1 false)
@@ -1419,7 +1419,7 @@ define void @PR18615() {
 ; CHECK: ret void
 entry:
   %f = alloca i8
-  %gep = getelementptr i8* %f, i64 -1
+  %gep = getelementptr i8, i8* %f, i64 -1
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* %gep, i32 1, i32 1, i1 false)
   ret void
 }
@@ -1427,9 +1427,9 @@ entry:
 define void @test24(i8* %src, i8* %dst) {
 ; CHECK-LABEL: @test24(
 ; CHECK: alloca i64, align 16
-; CHECK: load volatile i64* %{{[^,]*}}, align 1
+; CHECK: load volatile i64, i64* %{{[^,]*}}, align 1
 ; CHECK: store volatile i64 %{{[^,]*}}, i64* %{{[^,]*}}, align 16
-; CHECK: load volatile i64* %{{[^,]*}}, align 16
+; CHECK: load volatile i64, i64* %{{[^,]*}}, align 16
 ; CHECK: store volatile i64 %{{[^,]*}}, i64* %{{[^,]*}}, align 1
 
 entry:
@@ -1459,17 +1459,17 @@ entry:
   %a = alloca i64
   %b = alloca i64
   %a.cast = bitcast i64* %a to [2 x float]*
-  %a.gep1 = getelementptr [2 x float]* %a.cast, i32 0, i32 0
-  %a.gep2 = getelementptr [2 x float]* %a.cast, i32 0, i32 1
+  %a.gep1 = getelementptr [2 x float], [2 x float]* %a.cast, i32 0, i32 0
+  %a.gep2 = getelementptr [2 x float], [2 x float]* %a.cast, i32 0, i32 1
   %b.cast = bitcast i64* %b to [2 x float]*
-  %b.gep1 = getelementptr [2 x float]* %b.cast, i32 0, i32 0
-  %b.gep2 = getelementptr [2 x float]* %b.cast, i32 0, i32 1
+  %b.gep1 = getelementptr [2 x float], [2 x float]* %b.cast, i32 0, i32 0
+  %b.gep2 = getelementptr [2 x float], [2 x float]* %b.cast, i32 0, i32 1
   store float 0.0, float* %a.gep1
   store float 1.0, float* %a.gep2
-  %v = load i64* %a
+  %v = load i64, i64* %a
   store i64 %v, i64* %b
-  %f1 = load float* %b.gep1
-  %f2 = load float* %b.gep2
+  %f1 = load float, float* %b.gep1
+  %f2 = load float, float* %b.gep2
   %ret = fadd float %f1, %f2
   ret float %ret
 }
@@ -1482,8 +1482,8 @@ define void @test26() {
 ;
 ; CHECK-LABEL: @test26(
 ; CHECK-NOT: alloca
-; CHECK: %[[L1:.*]] = load i32* bitcast
-; CHECK: %[[L2:.*]] = load i32* bitcast
+; CHECK: %[[L1:.*]] = load i32, i32* bitcast
+; CHECK: %[[L2:.*]] = load i32, i32* bitcast
 ; CHECK: %[[F1:.*]] = bitcast i32 %[[L1]] to float
 ; CHECK: %[[F2:.*]] = bitcast i32 %[[L2]] to float
 ; CHECK: %[[SUM:.*]] = fadd float %[[F1]], %[[F2]]
@@ -1496,16 +1496,16 @@ define void @test26() {
 entry:
   %a = alloca i64
   %a.cast = bitcast i64* %a to [2 x float]*
-  %a.gep1 = getelementptr [2 x float]* %a.cast, i32 0, i32 0
-  %a.gep2 = getelementptr [2 x float]* %a.cast, i32 0, i32 1
-  %v1 = load i64* bitcast ([2 x float]* @complex1 to i64*)
+  %a.gep1 = getelementptr [2 x float], [2 x float]* %a.cast, i32 0, i32 0
+  %a.gep2 = getelementptr [2 x float], [2 x float]* %a.cast, i32 0, i32 1
+  %v1 = load i64, i64* bitcast ([2 x float]* @complex1 to i64*)
   store i64 %v1, i64* %a
-  %f1 = load float* %a.gep1
-  %f2 = load float* %a.gep2
+  %f1 = load float, float* %a.gep1
+  %f2 = load float, float* %a.gep2
   %sum = fadd float %f1, %f2
   store float %sum, float* %a.gep1
   store float %sum, float* %a.gep2
-  %v2 = load i64* %a
+  %v2 = load i64, i64* %a
   store i64 %v2, i64* bitcast ([2 x float]* @complex2 to i64*)
   ret void
 }
@@ -1524,9 +1524,9 @@ define float @test27() {
 
 entry:
   %a = alloca [12 x i8]
-  %gep1 = getelementptr [12 x i8]* %a, i32 0, i32 0
-  %gep2 = getelementptr [12 x i8]* %a, i32 0, i32 4
-  %gep3 = getelementptr [12 x i8]* %a, i32 0, i32 8
+  %gep1 = getelementptr [12 x i8], [12 x i8]* %a, i32 0, i32 0
+  %gep2 = getelementptr [12 x i8], [12 x i8]* %a, i32 0, i32 4
+  %gep3 = getelementptr [12 x i8], [12 x i8]* %a, i32 0, i32 8
   %iptr1 = bitcast i8* %gep1 to i64*
   %iptr2 = bitcast i8* %gep2 to i64*
   %fptr1 = bitcast i8* %gep1 to float*
@@ -1534,10 +1534,10 @@ entry:
   %fptr3 = bitcast i8* %gep3 to float*
   store float 0.0, float* %fptr1
   store float 1.0, float* %fptr2
-  %v = load i64* %iptr1
+  %v = load i64, i64* %iptr1
   store i64 %v, i64* %iptr2
-  %f1 = load float* %fptr2
-  %f2 = load float* %fptr3
+  %f1 = load float, float* %fptr2
+  %f2 = load float, float* %fptr3
   %ret = fadd float %f1, %f2
   ret float %ret
 }
@@ -1560,7 +1560,7 @@ entry:
   %a = alloca i32
   %a.cast = bitcast i32* %a to i16*
   store volatile i16 42, i16* %a.cast
-  %load = load i32* %a
+  %load = load i32, i32* %a
   store i32 %load, i32* %a
   ret i32 %load
 }
@@ -1587,9 +1587,9 @@ entry:
   %a.cast1 = bitcast i64* %a to i32*
   %a.cast2 = bitcast i64* %a to i16*
   store volatile i16 42, i16* %a.cast2
-  %load = load i32* %a.cast1
+  %load = load i32, i32* %a.cast1
   store i32 %load, i32* %a.cast1
-  %a.gep1 = getelementptr i32* %a.cast1, i32 1
+  %a.gep1 = getelementptr i32, i32* %a.cast1, i32 1
   %a.cast3 = bitcast i32* %a.gep1 to i8*
   store volatile i8 13, i8* %a.cast3
   store i32 %load, i32* %a.gep1
diff --git a/test/Transforms/SROA/big-endian.ll b/test/Transforms/SROA/big-endian.ll
index 9e87a9f073c5..b5a04ca8e64a 100644
--- a/test/Transforms/SROA/big-endian.ll
+++ b/test/Transforms/SROA/big-endian.ll
@@ -16,14 +16,14 @@ entry:
   %b = alloca [3 x i8]
 ; CHECK-NOT: alloca
 
-  %a0ptr = getelementptr [3 x i8]* %a, i64 0, i32 0
+  %a0ptr = getelementptr [3 x i8], [3 x i8]* %a, i64 0, i32 0
   store i8 0, i8* %a0ptr
-  %a1ptr = getelementptr [3 x i8]* %a, i64 0, i32 1
+  %a1ptr = getelementptr [3 x i8], [3 x i8]* %a, i64 0, i32 1
   store i8 0, i8* %a1ptr
-  %a2ptr = getelementptr [3 x i8]* %a, i64 0, i32 2
+  %a2ptr = getelementptr [3 x i8], [3 x i8]* %a, i64 0, i32 2
   store i8 0, i8* %a2ptr
   %aiptr = bitcast [3 x i8]* %a to i24*
-  %ai = load i24* %aiptr
+  %ai = load i24, i24* %aiptr
 ; CHECK-NOT: store
 ; CHECK-NOT: load
 ; CHECK:      %[[ext2:.*]] = zext i8 0 to i24
@@ -40,12 +40,12 @@ entry:
 
   %biptr = bitcast [3 x i8]* %b to i24*
   store i24 %ai, i24* %biptr
-  %b0ptr = getelementptr [3 x i8]* %b, i64 0, i32 0
-  %b0 = load i8* %b0ptr
-  %b1ptr = getelementptr [3 x i8]* %b, i64 0, i32 1
-  %b1 = load i8* %b1ptr
-  %b2ptr = getelementptr [3 x i8]* %b, i64 0, i32 2
-  %b2 = load i8* %b2ptr
+  %b0ptr = getelementptr [3 x i8], [3 x i8]* %b, i64 0, i32 0
+  %b0 = load i8, i8* %b0ptr
+  %b1ptr = getelementptr [3 x i8], [3 x i8]* %b, i64 0, i32 1
+  %b1 = load i8, i8* %b1ptr
+  %b2ptr = getelementptr [3 x i8], [3 x i8]* %b, i64 0, i32 2
+  %b2 = load i8, i8* %b2ptr
 ; CHECK-NOT: store
 ; CHECK-NOT: load
 ; CHECK:      %[[shift0:.*]] = lshr i24 %[[insert0]], 16
@@ -72,10 +72,10 @@ entry:
   %a = alloca [7 x i8]
 ; CHECK-NOT: alloca
 
-  %a0ptr = getelementptr [7 x i8]* %a, i64 0, i32 0
-  %a1ptr = getelementptr [7 x i8]* %a, i64 0, i32 1
-  %a2ptr = getelementptr [7 x i8]* %a, i64 0, i32 2
-  %a3ptr = getelementptr [7 x i8]* %a, i64 0, i32 3
+  %a0ptr = getelementptr [7 x i8], [7 x i8]* %a, i64 0, i32 0
+  %a1ptr = getelementptr [7 x i8], [7 x i8]* %a, i64 0, i32 1
+  %a2ptr = getelementptr [7 x i8], [7 x i8]* %a, i64 0, i32 2
+  %a3ptr = getelementptr [7 x i8], [7 x i8]* %a, i64 0, i32 3
 
 ; CHECK-NOT: store
 ; CHECK-NOT: load
@@ -102,7 +102,7 @@ entry:
 ; CHECK-NOT: load
 
   %aiptr = bitcast [7 x i8]* %a to i56*
-  %ai = load i56* %aiptr
+  %ai = load i56, i56* %aiptr
   %ret = zext i56 %ai to i64
   ret i64 %ret
 ; CHECK-NEXT: %[[ext4:.*]] = zext i16 1 to i56
diff --git a/test/Transforms/SROA/fca.ll b/test/Transforms/SROA/fca.ll
index e8b4c6c13c88..6eaa73f53189 100644
--- a/test/Transforms/SROA/fca.ll
+++ b/test/Transforms/SROA/fca.ll
@@ -14,12 +14,12 @@ entry:
 
   store { i32, i32 } undef, { i32, i32 }* %a
 
-  %gep1 = getelementptr inbounds { i32, i32 }* %a, i32 0, i32 0
+  %gep1 = getelementptr inbounds { i32, i32 }, { i32, i32 }* %a, i32 0, i32 0
   store i32 %x, i32* %gep1
-  %gep2 = getelementptr inbounds { i32, i32 }* %a, i32 0, i32 1
+  %gep2 = getelementptr inbounds { i32, i32 }, { i32, i32 }* %a, i32 0, i32 1
   store i32 %y, i32* %gep2
 
-  %result = load { i32, i32 }* %a
+  %result = load { i32, i32 }, { i32, i32 }* %a
   ret { i32, i32 } %result
 }
 
@@ -30,7 +30,7 @@ define { i32, i32 } @test1(i32 %x, i32 %y) {
 ; CHECK-LABEL: @test1(
 ; CHECK: alloca
 ; CHECK: alloca
-; CHECK: load volatile { i32, i32 }*
+; CHECK: load volatile { i32, i32 }, { i32, i32 }*
 ; CHECK: store volatile { i32, i32 }
 ; CHECK: ret { i32, i32 }
 
@@ -38,12 +38,12 @@ entry:
   %a = alloca { i32, i32 }
   %b = alloca { i32, i32 }
 
-  %gep1 = getelementptr inbounds { i32, i32 }* %a, i32 0, i32 0
+  %gep1 = getelementptr inbounds { i32, i32 }, { i32, i32 }* %a, i32 0, i32 0
   store i32 %x, i32* %gep1
-  %gep2 = getelementptr inbounds { i32, i32 }* %a, i32 0, i32 1
+  %gep2 = getelementptr inbounds { i32, i32 }, { i32, i32 }* %a, i32 0, i32 1
   store i32 %y, i32* %gep2
 
-  %result = load volatile { i32, i32 }* %a
+  %result = load volatile { i32, i32 }, { i32, i32 }* %a
   store volatile { i32, i32 } %result, { i32, i32 }* %b
   ret { i32, i32 } %result
 }
diff --git a/test/Transforms/SROA/phi-and-select.ll b/test/Transforms/SROA/phi-and-select.ll
index f2870127352c..e97bd66d052a 100644
--- a/test/Transforms/SROA/phi-and-select.ll
+++ b/test/Transforms/SROA/phi-and-select.ll
@@ -7,12 +7,12 @@ entry:
 	%a = alloca [2 x i32]
 ; CHECK-NOT: alloca
 
-  %a0 = getelementptr [2 x i32]* %a, i64 0, i32 0
-  %a1 = getelementptr [2 x i32]* %a, i64 0, i32 1
+  %a0 = getelementptr [2 x i32], [2 x i32]* %a, i64 0, i32 0
+  %a1 = getelementptr [2 x i32], [2 x i32]* %a, i64 0, i32 1
 	store i32 0, i32* %a0
 	store i32 1, i32* %a1
-	%v0 = load i32* %a0
-	%v1 = load i32* %a1
+	%v0 = load i32, i32* %a0
+	%v1 = load i32, i32* %a1
 ; CHECK-NOT: store
 ; CHECK-NOT: load
 
@@ -26,7 +26,7 @@ exit:
 	%phi = phi i32* [ %a1, %then ], [ %a0, %entry ]
 ; CHECK: phi i32 [ 1, %{{.*}} ], [ 0, %{{.*}} ]
 
-	%result = load i32* %phi
+	%result = load i32, i32* %phi
 	ret i32 %result
 }
 
@@ -36,12 +36,12 @@ entry:
 	%a = alloca [2 x i32]
 ; CHECK-NOT: alloca
 
-  %a0 = getelementptr [2 x i32]* %a, i64 0, i32 0
-  %a1 = getelementptr [2 x i32]* %a, i64 0, i32 1
+  %a0 = getelementptr [2 x i32], [2 x i32]* %a, i64 0, i32 0
+  %a1 = getelementptr [2 x i32], [2 x i32]* %a, i64 0, i32 1
 	store i32 0, i32* %a0
 	store i32 1, i32* %a1
-	%v0 = load i32* %a0
-	%v1 = load i32* %a1
+	%v0 = load i32, i32* %a0
+	%v1 = load i32, i32* %a1
 ; CHECK-NOT: store
 ; CHECK-NOT: load
 
@@ -49,7 +49,7 @@ entry:
 	%select = select i1 %cond, i32* %a1, i32* %a0
 ; CHECK: select i1 %{{.*}}, i32 1, i32 0
 
-	%result = load i32* %select
+	%result = load i32, i32* %select
 	ret i32 %result
 }
 
@@ -62,10 +62,10 @@ entry:
   ; Note that we build redundant GEPs here to ensure that having different GEPs
   ; into the same alloca partation continues to work with PHI speculation. This
   ; was the underlying cause of PR13926.
-  %a0 = getelementptr [2 x i32]* %a, i64 0, i32 0
-  %a0b = getelementptr [2 x i32]* %a, i64 0, i32 0
-  %a1 = getelementptr [2 x i32]* %a, i64 0, i32 1
-  %a1b = getelementptr [2 x i32]* %a, i64 0, i32 1
+  %a0 = getelementptr [2 x i32], [2 x i32]* %a, i64 0, i32 0
+  %a0b = getelementptr [2 x i32], [2 x i32]* %a, i64 0, i32 0
+  %a1 = getelementptr [2 x i32], [2 x i32]* %a, i64 0, i32 1
+  %a1b = getelementptr [2 x i32], [2 x i32]* %a, i64 0, i32 1
 	store i32 0, i32* %a0
 	store i32 1, i32* %a1
 ; CHECK-NOT: store
@@ -100,7 +100,7 @@ exit:
                   [ %a1b, %bb4 ], [ %a0b, %bb5 ], [ %a0b, %bb6 ], [ %a1b, %bb7 ]
 ; CHECK: phi i32 [ 1, %{{.*}} ], [ 0, %{{.*}} ], [ 0, %{{.*}} ], [ 1, %{{.*}} ], [ 1, %{{.*}} ], [ 0, %{{.*}} ], [ 0, %{{.*}} ], [ 1, %{{.*}} ]
 
-	%result = load i32* %phi
+	%result = load i32, i32* %phi
 	ret i32 %result
 }
 
@@ -110,12 +110,12 @@ entry:
 	%a = alloca [2 x i32]
 ; CHECK-NOT: alloca
 
-  %a0 = getelementptr [2 x i32]* %a, i64 0, i32 0
-  %a1 = getelementptr [2 x i32]* %a, i64 0, i32 1
+  %a0 = getelementptr [2 x i32], [2 x i32]* %a, i64 0, i32 0
+  %a1 = getelementptr [2 x i32], [2 x i32]* %a, i64 0, i32 1
 	store i32 0, i32* %a0
 	store i32 1, i32* %a1
-	%v0 = load i32* %a0
-	%v1 = load i32* %a1
+	%v0 = load i32, i32* %a0
+	%v1 = load i32, i32* %a1
 ; CHECK-NOT: store
 ; CHECK-NOT: load
 
@@ -123,7 +123,7 @@ entry:
 	%select = select i1 %cond, i32* %a0, i32* %a0
 ; CHECK-NOT: select
 
-	%result = load i32* %select
+	%result = load i32, i32* %select
 	ret i32 %result
 ; CHECK: ret i32 0
 }
@@ -134,14 +134,14 @@ entry:
 	%a = alloca [2 x i32]
 ; CHECK-NOT: alloca
 
-  %a1 = getelementptr [2 x i32]* %a, i64 0, i32 1
+  %a1 = getelementptr [2 x i32], [2 x i32]* %a, i64 0, i32 1
 	store i32 1, i32* %a1
 ; CHECK-NOT: store
 
 	%select = select i1 true, i32* %a1, i32* %b
 ; CHECK-NOT: select
 
-	%result = load i32* %select
+	%result = load i32, i32* %select
 ; CHECK-NOT: load
 
 	ret i32 %result
@@ -157,7 +157,7 @@ entry:
   %c = alloca i32
 ; CHECK-NOT: alloca
 
-  %a1 = getelementptr [2 x i32]* %a, i64 0, i32 1
+  %a1 = getelementptr [2 x i32], [2 x i32]* %a, i64 0, i32 1
 	store i32 1, i32* %a1
 
 	%select = select i1 true, i32* %a1, i32* %b
@@ -172,10 +172,10 @@ entry:
 ; CHECK: call void @f(i32* %[[select2]], i32* %[[select3]])
 
 
-	%result = load i32* %select
+	%result = load i32, i32* %select
 ; CHECK-NOT: load
 
-  %dead = load i32* %c
+  %dead = load i32, i32* %c
 
 	ret i32 %result
 ; CHECK: ret i32 1
@@ -190,19 +190,19 @@ entry:
   br i1 undef, label %good, label %bad
 
 good:
-  %Y1 = getelementptr i32* %X, i64 0
+  %Y1 = getelementptr i32, i32* %X, i64 0
   store i32 0, i32* %Y1
   br label %exit
 
 bad:
-  %Y2 = getelementptr i32* %X, i64 1
+  %Y2 = getelementptr i32, i32* %X, i64 1
   store i32 0, i32* %Y2
   br label %exit
 
 exit:
 	%P = phi i32* [ %Y1, %good ], [ %Y2, %bad ]
 ; CHECK: %[[phi:.*]] = phi i32 [ 0, %good ],
-  %Z2 = load i32* %P
+  %Z2 = load i32, i32* %P
   ret i32 %Z2
 ; CHECK: ret i32 %[[phi]]
 }
@@ -213,7 +213,7 @@ define i32 @test8(i32 %b, i32* %ptr) {
 ; CHECK-LABEL: @test8(
 ; CHECK-NOT: alloca
 ; CHECK-NOT: load
-; CHECK: %[[value:.*]] = load i32* %ptr
+; CHECK: %[[value:.*]] = load i32, i32* %ptr
 ; CHECK-NOT: load
 ; CHECK: %[[result:.*]] = phi i32 [ undef, %else ], [ %[[value]], %then ]
 ; CHECK-NEXT: ret i32 %[[result]]
@@ -232,7 +232,7 @@ else:
 
 exit:
   %phi = phi i32* [ %bitcast, %else ], [ %ptr, %then ]
-  %loaded = load i32* %phi, align 4
+  %loaded = load i32, i32* %phi, align 4
   ret i32 %loaded
 }
 
@@ -241,7 +241,7 @@ define i32 @test9(i32 %b, i32* %ptr) {
 ; CHECK-LABEL: @test9(
 ; CHECK-NOT: alloca
 ; CHECK-NOT: load
-; CHECK: %[[value:.*]] = load i32* %ptr
+; CHECK: %[[value:.*]] = load i32, i32* %ptr
 ; CHECK-NOT: load
 ; CHECK: %[[result:.*]] = select i1 %{{.*}}, i32 undef, i32 %[[value]]
 ; CHECK-NEXT: ret i32 %[[result]]
@@ -252,7 +252,7 @@ entry:
   %test = icmp ne i32 %b, 0
   %bitcast = bitcast float* %f to i32*
   %select = select i1 %test, i32* %bitcast, i32* %ptr
-  %loaded = load i32* %select, align 4
+  %loaded = load i32, i32* %select, align 4
   ret i32 %loaded
 }
 
@@ -262,9 +262,9 @@ define float @test10(i32 %b, float* %ptr) {
 ; node.
 ; CHECK-LABEL: @test10(
 ; CHECK: %[[alloca:.*]] = alloca
-; CHECK: %[[argvalue:.*]] = load float* %ptr
+; CHECK: %[[argvalue:.*]] = load float, float* %ptr
 ; CHECK: %[[cast:.*]] = bitcast double* %[[alloca]] to float*
-; CHECK: %[[allocavalue:.*]] = load float* %[[cast]]
+; CHECK: %[[allocavalue:.*]] = load float, float* %[[cast]]
 ; CHECK: %[[result:.*]] = phi float [ %[[allocavalue]], %else ], [ %[[argvalue]], %then ]
 ; CHECK-NEXT: ret float %[[result]]
 
@@ -283,7 +283,7 @@ else:
 
 exit:
   %phi = phi float* [ %bitcast, %else ], [ %ptr, %then ]
-  %loaded = load float* %phi, align 4
+  %loaded = load float, float* %phi, align 4
   ret float %loaded
 }
 
@@ -292,8 +292,8 @@ define float @test11(i32 %b, float* %ptr) {
 ; CHECK-LABEL: @test11(
 ; CHECK: %[[alloca:.*]] = alloca
 ; CHECK: %[[cast:.*]] = bitcast double* %[[alloca]] to float*
-; CHECK: %[[allocavalue:.*]] = load float* %[[cast]]
-; CHECK: %[[argvalue:.*]] = load float* %ptr
+; CHECK: %[[allocavalue:.*]] = load float, float* %[[cast]]
+; CHECK: %[[argvalue:.*]] = load float, float* %ptr
 ; CHECK: %[[result:.*]] = select i1 %{{.*}}, float %[[allocavalue]], float %[[argvalue]]
 ; CHECK-NEXT: ret float %[[result]]
 
@@ -304,7 +304,7 @@ entry:
   %test = icmp ne i32 %b, 0
   %bitcast = bitcast double* %f to float*
   %select = select i1 %test, float* %bitcast, float* %ptr
-  %loaded = load float* %select, align 4
+  %loaded = load float, float* %select, align 4
   ret float %loaded
 }
 
@@ -320,7 +320,7 @@ entry:
   %a = alloca i32
   store i32 %x, i32* %a
   %dead = select i1 undef, i32* %a, i32* %p
-  %load = load i32* %a
+  %load = load i32, i32* %a
   ret i32 %load
 }
 
@@ -342,7 +342,7 @@ loop:
   br i1 undef, label %loop, label %exit
 
 exit:
-  %load = load i32* %a
+  %load = load i32, i32* %a
   ret i32 %load
 }
 
@@ -376,9 +376,9 @@ else:
 exit:
   %f.phi = phi i32* [ %f, %then ], [ %f.select, %else ]
   %g.phi = phi i32* [ %g, %then ], [ %ptr, %else ]
-  %f.loaded = load i32* %f.phi
+  %f.loaded = load i32, i32* %f.phi
   %g.select = select i1 %b1, i32* %g, i32* %g.phi
-  %g.loaded = load i32* %g.select
+  %g.loaded = load i32, i32* %g.select
   %result = add i32 %f.loaded, %g.loaded
   ret i32 %result
 }
@@ -456,8 +456,8 @@ if.then:
 ; CHECK: %[[ext:.*]] = zext i8 1 to i64
 
 if.end:
-  %tmp = load i64** %ptr
-  %result = load i64* %tmp
+  %tmp = load i64*, i64** %ptr
+  %result = load i64, i64* %tmp
 ; CHECK-NOT: load
 ; CHECK: %[[result:.*]] = phi i64 [ %[[ext]], %if.then ], [ 0, %entry ]
 
@@ -488,14 +488,14 @@ then:
 
 else:
   %a.raw = bitcast i64* %a to i8*
-  %a.raw.4 = getelementptr i8* %a.raw, i64 4
+  %a.raw.4 = getelementptr i8, i8* %a.raw, i64 4
   %a.raw.4.f = bitcast i8* %a.raw.4 to float*
   br label %end
 ; CHECK: %[[hi_cast:.*]] = bitcast i32 %[[hi]] to float
 
 end:
   %a.phi.f = phi float* [ %a.f, %then ], [ %a.raw.4.f, %else ]
-  %f = load float* %a.phi.f
+  %f = load float, float* %a.phi.f
   ret float %f
 ; CHECK: %[[phi:.*]] = phi float [ %[[lo_cast]], %then ], [ %[[hi_cast]], %else ]
 ; CHECK-NOT: load
@@ -516,19 +516,19 @@ entry:
   br i1 %cond, label %then, label %else
 
 then:
-  %0 = getelementptr inbounds [4 x float]* %arr, i64 0, i64 3
+  %0 = getelementptr inbounds [4 x float], [4 x float]* %arr, i64 0, i64 3
   store float 1.000000e+00, float* %0, align 4
   br label %merge
 
 else:
-  %1 = getelementptr inbounds [4 x float]* %arr, i64 0, i64 3
+  %1 = getelementptr inbounds [4 x float], [4 x float]* %arr, i64 0, i64 3
   store float 2.000000e+00, float* %1, align 4
   br label %merge
 
 merge:
   %2 = phi float* [ %0, %then ], [ %1, %else ]
   store float 0.000000e+00, float* %temp, align 4
-  %3 = load float* %2, align 4
+  %3 = load float, float* %2, align 4
   ret float %3
 }
 
@@ -546,7 +546,7 @@ entry:
   br i1 %cond, label %then, label %else
 
 then:
-  %0 = getelementptr inbounds [4 x float]* %arr, i64 0, i64 3
+  %0 = getelementptr inbounds [4 x float], [4 x float]* %arr, i64 0, i64 3
   store float 1.000000e+00, float* %0, align 4
   br label %then2
 
@@ -556,14 +556,14 @@ then2:
   br label %merge
 
 else:
-  %2 = getelementptr inbounds [4 x float]* %arr, i64 0, i64 3
+  %2 = getelementptr inbounds [4 x float], [4 x float]* %arr, i64 0, i64 3
   store float 3.000000e+00, float* %2, align 4
   br label %merge
 
 merge:
   %3 = phi float* [ %1, %then2 ], [ %2, %else ]
   store float 0.000000e+00, float* %temp, align 4
-  %4 = load float* %3, align 4
+  %4 = load float, float* %3, align 4
   ret float %4
 }
 
diff --git a/test/Transforms/SROA/ppcf128-no-fold.ll b/test/Transforms/SROA/ppcf128-no-fold.ll
new file mode 100644
index 000000000000..3f2934cbe166
--- /dev/null
+++ b/test/Transforms/SROA/ppcf128-no-fold.ll
@@ -0,0 +1,36 @@
+; RUN: opt < %s -sroa -S | FileCheck %s 
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.ld2 = type { [2 x ppc_fp128] }
+declare void @bar(i8*, [2 x i128])
+
+define void @foo(i8* %v) #0 {
+entry:
+  %v.addr = alloca i8*, align 8
+  %z = alloca %struct.ld2, align 16
+  store i8* %v, i8** %v.addr, align 8
+  %dat = getelementptr inbounds %struct.ld2, %struct.ld2* %z, i32 0, i32 0
+  %arrayidx = getelementptr inbounds [2 x ppc_fp128], [2 x ppc_fp128]* %dat, i32 0, i64 0
+  store ppc_fp128 0xM403B0000000000000000000000000000, ppc_fp128* %arrayidx, align 16
+  %dat1 = getelementptr inbounds %struct.ld2, %struct.ld2* %z, i32 0, i32 0
+  %arrayidx2 = getelementptr inbounds [2 x ppc_fp128], [2 x ppc_fp128]* %dat1, i32 0, i64 1
+  store ppc_fp128 0xM4093B400000000000000000000000000, ppc_fp128* %arrayidx2, align 16
+  %0 = load i8*, i8** %v.addr, align 8
+  %coerce.dive = getelementptr %struct.ld2, %struct.ld2* %z, i32 0, i32 0
+  %1 = bitcast [2 x ppc_fp128]* %coerce.dive to [2 x i128]*
+  %2 = load [2 x i128], [2 x i128]* %1, align 1
+  call void @bar(i8* %0, [2 x i128] %2)
+  ret void
+}
+
+; CHECK-LABEL: @foo
+; CHECK-NOT: i128 4628293042053316608
+; CHECK-NOT: i128 4653260752096854016
+; CHECK-DAG: i128 bitcast (ppc_fp128 0xM403B0000000000000000000000000000 to i128)
+; CHECK-DAG: i128 bitcast (ppc_fp128 0xM4093B400000000000000000000000000 to i128)
+; CHECK: call void @bar(i8* %v, [2 x i128]
+; CHECK: ret void
+
+attributes #0 = { nounwind }
+
diff --git a/test/Transforms/SROA/slice-order-independence.ll b/test/Transforms/SROA/slice-order-independence.ll
index 364ef85f1d14..7d57be6d81cc 100644
--- a/test/Transforms/SROA/slice-order-independence.ll
+++ b/test/Transforms/SROA/slice-order-independence.ll
@@ -13,11 +13,11 @@ define void @skipped_inttype_first({ i16*, i32 }*) {
   %2 = bitcast { i16*, i32 }* %0 to i8*
   %3 = bitcast { i16*, i32 }* %arg to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %3, i8* %2, i32 16, i32 8, i1 false)
-  %b = getelementptr inbounds { i16*, i32 }* %arg, i64 0, i32 0
+  %b = getelementptr inbounds { i16*, i32 }, { i16*, i32 }* %arg, i64 0, i32 0
   %pb0 = bitcast i16** %b to i63*
-  %b0 = load i63* %pb0
+  %b0 = load i63, i63* %pb0
   %pb1 = bitcast i16** %b to i8**
-  %b1 = load i8** %pb1
+  %b1 = load i8*, i8** %pb1
   ret void
 }
 
@@ -28,10 +28,10 @@ define void @skipped_inttype_last({ i16*, i32 }*) {
   %2 = bitcast { i16*, i32 }* %0 to i8*
   %3 = bitcast { i16*, i32 }* %arg to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %3, i8* %2, i32 16, i32 8, i1 false)
-  %b = getelementptr inbounds { i16*, i32 }* %arg, i64 0, i32 0
+  %b = getelementptr inbounds { i16*, i32 }, { i16*, i32 }* %arg, i64 0, i32 0
   %pb1 = bitcast i16** %b to i8**
-  %b1 = load i8** %pb1
+  %b1 = load i8*, i8** %pb1
   %pb0 = bitcast i16** %b to i63*
-  %b0 = load i63* %pb0
+  %b0 = load i63, i63* %pb0
   ret void
 }
diff --git a/test/Transforms/SROA/slice-width.ll b/test/Transforms/SROA/slice-width.ll
index ff66dcccee4b..6b6ab93dd0d2 100644
--- a/test/Transforms/SROA/slice-width.ll
+++ b/test/Transforms/SROA/slice-width.ll
@@ -14,14 +14,14 @@ load_i32:
 ; CHECK-LABEL: load_i32:
 ; CHECK-NOT: bitcast {{.*}} to i1
 ; CHECK-NOT: zext i1
-  %r0 = load i32* %arg
+  %r0 = load i32, i32* %arg
   br label %load_i1
 
 load_i1:
 ; CHECK-LABEL: load_i1:
 ; CHECK: bitcast {{.*}} to i1
   %p1 = bitcast i32* %arg to i1*
-  %t1 = load i1* %p1
+  %t1 = load i1, i1* %p1
   ret void
 }
 
@@ -42,16 +42,16 @@ define void @memcpy_fp80_padding() {
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %x_i8, i8* bitcast (%union.Foo* @foo_copy_source to i8*), i32 32, i32 16, i1 false)
 
   ; Access a slice of the alloca to trigger SROA.
-  %mid_p = getelementptr %union.Foo* %x, i32 0, i32 1
-  %elt = load i64* %mid_p
+  %mid_p = getelementptr %union.Foo, %union.Foo* %x, i32 0, i32 1
+  %elt = load i64, i64* %mid_p
   store i64 %elt, i64* @i64_sink
   ret void
 }
 ; CHECK-LABEL: define void @memcpy_fp80_padding
 ; CHECK: alloca x86_fp80
 ; CHECK: call void @llvm.memcpy.p0i8.p0i8.i32
-; CHECK: load i64* getelementptr inbounds (%union.Foo* @foo_copy_source, i64 0, i32 1)
-; CHECK: load i64* getelementptr inbounds (%union.Foo* @foo_copy_source, i64 0, i32 2)
+; CHECK: load i64, i64* getelementptr inbounds (%union.Foo, %union.Foo* @foo_copy_source, i64 0, i32 1)
+; CHECK: load i64, i64* getelementptr inbounds (%union.Foo, %union.Foo* @foo_copy_source, i64 0, i32 2)
 
 define void @memset_fp80_padding() {
   %x = alloca %union.Foo
@@ -61,8 +61,8 @@ define void @memset_fp80_padding() {
   call void @llvm.memset.p0i8.i32(i8* %x_i8, i8 -1, i32 32, i32 16, i1 false)
 
   ; Access a slice of the alloca to trigger SROA.
-  %mid_p = getelementptr %union.Foo* %x, i32 0, i32 1
-  %elt = load i64* %mid_p
+  %mid_p = getelementptr %union.Foo, %union.Foo* %x, i32 0, i32 1
+  %elt = load i64, i64* %mid_p
   store i64 %elt, i64* @i64_sink
   ret void
 }
@@ -89,8 +89,8 @@ entry:
 
   ; The following block does nothing; but appears to confuse SROA
   %unused1 = bitcast %S.vec3float* %tmp1 to %U.vec3float*
-  %unused2 = getelementptr inbounds %U.vec3float* %unused1, i32 0, i32 0
-  %unused3 = load <4 x float>* %unused2, align 1
+  %unused2 = getelementptr inbounds %U.vec3float, %U.vec3float* %unused1, i32 0, i32 0
+  %unused3 = load <4 x float>, <4 x float>* %unused2, align 1
 
   ; Create a second temporary and copy %tmp1 into it
   %tmp2 = alloca %S.vec3float, align 4
diff --git a/test/Transforms/SROA/vector-conversion.ll b/test/Transforms/SROA/vector-conversion.ll
index 08d796087317..91ae5be6c3d2 100644
--- a/test/Transforms/SROA/vector-conversion.ll
+++ b/test/Transforms/SROA/vector-conversion.ll
@@ -10,7 +10,7 @@ define <4 x i64> @vector_ptrtoint({<2 x i32*>, <2 x i32*>} %x) {
 ; CHECK-NOT: store
 
   %cast = bitcast {<2 x i32*>, <2 x i32*>}* %a to <4 x i64>*
-  %vec = load <4 x i64>* %cast
+  %vec = load <4 x i64>, <4 x i64>* %cast
 ; CHECK-NOT: load
 ; CHECK: ptrtoint
 
@@ -26,7 +26,7 @@ define <4 x i32*> @vector_inttoptr({<2 x i64>, <2 x i64>} %x) {
 ; CHECK-NOT: store
 
   %cast = bitcast {<2 x i64>, <2 x i64>}* %a to <4 x i32*>*
-  %vec = load <4 x i32*>* %cast
+  %vec = load <4 x i32*>, <4 x i32*>* %cast
 ; CHECK-NOT: load
 ; CHECK: inttoptr
 
@@ -42,7 +42,7 @@ define <2 x i64> @vector_ptrtointbitcast({<1 x i32*>, <1 x i32*>} %x) {
 ; CHECK-NOT: store
 
   %cast = bitcast {<1 x i32*>, <1 x i32*>}* %a to <2 x i64>*
-  %vec = load <2 x i64>* %cast
+  %vec = load <2 x i64>, <2 x i64>* %cast
 ; CHECK-NOT: load
 ; CHECK: ptrtoint
 ; CHECK: bitcast
diff --git a/test/Transforms/SROA/vector-lifetime-intrinsic.ll b/test/Transforms/SROA/vector-lifetime-intrinsic.ll
index 30c93b054ecc..37cf394382ac 100644
--- a/test/Transforms/SROA/vector-lifetime-intrinsic.ll
+++ b/test/Transforms/SROA/vector-lifetime-intrinsic.ll
@@ -18,7 +18,7 @@ bb:
   call void @llvm.lifetime.start(i64 16, i8* %tmp8)
   store <4 x float> %arg1, <4 x float>* %tmp, align 16
   %tmp17 = bitcast <4 x float>* %tmp to <3 x float>*
-  %tmp18 = load <3 x float>* %tmp17
+  %tmp18 = load <3 x float>, <3 x float>* %tmp17
   %tmp20 = bitcast <4 x float>* %tmp to i8*
   call void @llvm.lifetime.end(i64 16, i8* %tmp20)
   call void @wombat3(<3 x float> %tmp18)
diff --git a/test/Transforms/SROA/vector-promotion.ll b/test/Transforms/SROA/vector-promotion.ll
index c20c6352e099..2d9b26b5309c 100644
--- a/test/Transforms/SROA/vector-promotion.ll
+++ b/test/Transforms/SROA/vector-promotion.ll
@@ -9,18 +9,18 @@ entry:
 	%a = alloca [2 x <4 x i32>]
 ; CHECK-NOT: alloca
 
-  %a.x = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 0
+  %a.x = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 0
   store <4 x i32> %x, <4 x i32>* %a.x
-  %a.y = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1
+  %a.y = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1
   store <4 x i32> %y, <4 x i32>* %a.y
 ; CHECK-NOT: store
 
-  %a.tmp1 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 0, i64 2
-  %tmp1 = load i32* %a.tmp1
-  %a.tmp2 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1, i64 3
-  %tmp2 = load i32* %a.tmp2
-  %a.tmp3 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1, i64 0
-  %tmp3 = load i32* %a.tmp3
+  %a.tmp1 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 0, i64 2
+  %tmp1 = load i32, i32* %a.tmp1
+  %a.tmp2 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1, i64 3
+  %tmp2 = load i32, i32* %a.tmp2
+  %a.tmp3 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1, i64 0
+  %tmp3 = load i32, i32* %a.tmp3
 ; CHECK-NOT: load
 ; CHECK:      extractelement <4 x i32> %x, i32 2
 ; CHECK-NEXT: extractelement <4 x i32> %y, i32 3
@@ -40,19 +40,19 @@ entry:
 	%a = alloca [2 x <4 x i32>]
 ; CHECK-NOT: alloca
 
-  %a.x = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 0
+  %a.x = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 0
   store <4 x i32> %x, <4 x i32>* %a.x
-  %a.y = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1
+  %a.y = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1
   store <4 x i32> %y, <4 x i32>* %a.y
 ; CHECK-NOT: store
 
-  %a.tmp1 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 0, i64 2
-  %tmp1 = load i32* %a.tmp1
-  %a.tmp2 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1, i64 3
-  %tmp2 = load i32* %a.tmp2
-  %a.tmp3 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1, i64 0
+  %a.tmp1 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 0, i64 2
+  %tmp1 = load i32, i32* %a.tmp1
+  %a.tmp2 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1, i64 3
+  %tmp2 = load i32, i32* %a.tmp2
+  %a.tmp3 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1, i64 0
   %a.tmp3.cast = bitcast i32* %a.tmp3 to <2 x i32>*
-  %tmp3.vec = load <2 x i32>* %a.tmp3.cast
+  %tmp3.vec = load <2 x i32>, <2 x i32>* %a.tmp3.cast
   %tmp3 = extractelement <2 x i32> %tmp3.vec, i32 0
 ; CHECK-NOT: load
 ; CHECK:      %[[extract1:.*]] = extractelement <4 x i32> %x, i32 2
@@ -74,9 +74,9 @@ entry:
 	%a = alloca [2 x <4 x i32>]
 ; CHECK-NOT: alloca
 
-  %a.x = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 0
+  %a.x = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 0
   store <4 x i32> %x, <4 x i32>* %a.x
-  %a.y = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1
+  %a.y = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1
   store <4 x i32> %y, <4 x i32>* %a.y
 ; CHECK-NOT: store
 
@@ -84,14 +84,14 @@ entry:
   call void @llvm.memset.p0i8.i32(i8* %a.y.cast, i8 0, i32 16, i32 1, i1 false)
 ; CHECK-NOT: memset
 
-  %a.tmp1 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 0, i64 2
+  %a.tmp1 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 0, i64 2
   %a.tmp1.cast = bitcast i32* %a.tmp1 to i8*
   call void @llvm.memset.p0i8.i32(i8* %a.tmp1.cast, i8 -1, i32 4, i32 1, i1 false)
-  %tmp1 = load i32* %a.tmp1
-  %a.tmp2 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1, i64 3
-  %tmp2 = load i32* %a.tmp2
-  %a.tmp3 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1, i64 0
-  %tmp3 = load i32* %a.tmp3
+  %tmp1 = load i32, i32* %a.tmp1
+  %a.tmp2 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1, i64 3
+  %tmp2 = load i32, i32* %a.tmp2
+  %a.tmp3 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1, i64 0
+  %tmp3 = load i32, i32* %a.tmp3
 ; CHECK-NOT: load
 ; CHECK:      %[[insert:.*]] = insertelement <4 x i32> %x, i32 -1, i32 2
 ; CHECK-NEXT: extractelement <4 x i32> %[[insert]], i32 2
@@ -112,9 +112,9 @@ entry:
 	%a = alloca [2 x <4 x i32>]
 ; CHECK-NOT: alloca
 
-  %a.x = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 0
+  %a.x = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 0
   store <4 x i32> %x, <4 x i32>* %a.x
-  %a.y = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1
+  %a.y = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1
   store <4 x i32> %y, <4 x i32>* %a.y
 ; CHECK-NOT: store
 
@@ -123,20 +123,20 @@ entry:
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a.y.cast, i8* %z.cast, i32 16, i32 1, i1 false)
 ; CHECK-NOT: memcpy
 
-  %a.tmp1 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 0, i64 2
+  %a.tmp1 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 0, i64 2
   %a.tmp1.cast = bitcast i32* %a.tmp1 to i8*
-  %z.tmp1 = getelementptr inbounds <4 x i32>* %z, i64 0, i64 2
+  %z.tmp1 = getelementptr inbounds <4 x i32>, <4 x i32>* %z, i64 0, i64 2
   %z.tmp1.cast = bitcast i32* %z.tmp1 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a.tmp1.cast, i8* %z.tmp1.cast, i32 4, i32 1, i1 false)
-  %tmp1 = load i32* %a.tmp1
-  %a.tmp2 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1, i64 3
-  %tmp2 = load i32* %a.tmp2
-  %a.tmp3 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1, i64 0
-  %tmp3 = load i32* %a.tmp3
+  %tmp1 = load i32, i32* %a.tmp1
+  %a.tmp2 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1, i64 3
+  %tmp2 = load i32, i32* %a.tmp2
+  %a.tmp3 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1, i64 0
+  %tmp3 = load i32, i32* %a.tmp3
 ; CHECK-NOT: memcpy
-; CHECK:      %[[load:.*]] = load <4 x i32>* %z
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds <4 x i32>* %z, i64 0, i64 2
-; CHECK-NEXT: %[[element_load:.*]] = load i32* %[[gep]]
+; CHECK:      %[[load:.*]] = load <4 x i32>, <4 x i32>* %z
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds <4 x i32>, <4 x i32>* %z, i64 0, i64 2
+; CHECK-NEXT: %[[element_load:.*]] = load i32, i32* %[[gep]]
 ; CHECK-NEXT: %[[insert:.*]] = insertelement <4 x i32> %x, i32 %[[element_load]], i32 2
 ; CHECK-NEXT: extractelement <4 x i32> %[[insert]], i32 2
 ; CHECK-NEXT: extractelement <4 x i32> %[[load]], i32 3
@@ -159,9 +159,9 @@ entry:
 	%a = alloca [2 x <4 x i32>]
 ; CHECK-NOT: alloca
 
-  %a.x = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 0
+  %a.x = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 0
   store <4 x i32> %x, <4 x i32>* %a.x
-  %a.y = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1
+  %a.y = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1
   store <4 x i32> %y, <4 x i32>* %a.y
 ; CHECK-NOT: store
 
@@ -170,20 +170,20 @@ entry:
   call void @llvm.memcpy.p0i8.p1i8.i32(i8* %a.y.cast, i8 addrspace(1)* %z.cast, i32 16, i32 1, i1 false)
 ; CHECK-NOT: memcpy
 
-  %a.tmp1 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 0, i64 2
+  %a.tmp1 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 0, i64 2
   %a.tmp1.cast = bitcast i32* %a.tmp1 to i8*
-  %z.tmp1 = getelementptr inbounds <4 x i32> addrspace(1)* %z, i16 0, i16 2
+  %z.tmp1 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %z, i16 0, i16 2
   %z.tmp1.cast = bitcast i32 addrspace(1)* %z.tmp1 to i8 addrspace(1)*
   call void @llvm.memcpy.p0i8.p1i8.i32(i8* %a.tmp1.cast, i8 addrspace(1)* %z.tmp1.cast, i32 4, i32 1, i1 false)
-  %tmp1 = load i32* %a.tmp1
-  %a.tmp2 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1, i64 3
-  %tmp2 = load i32* %a.tmp2
-  %a.tmp3 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1, i64 0
-  %tmp3 = load i32* %a.tmp3
+  %tmp1 = load i32, i32* %a.tmp1
+  %a.tmp2 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1, i64 3
+  %tmp2 = load i32, i32* %a.tmp2
+  %a.tmp3 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1, i64 0
+  %tmp3 = load i32, i32* %a.tmp3
 ; CHECK-NOT: memcpy
-; CHECK:      %[[load:.*]] = load <4 x i32> addrspace(1)* %z
-; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds <4 x i32> addrspace(1)* %z, i64 0, i64 2
-; CHECK-NEXT: %[[element_load:.*]] = load i32 addrspace(1)* %[[gep]]
+; CHECK:      %[[load:.*]] = load <4 x i32>, <4 x i32> addrspace(1)* %z
+; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %z, i64 0, i64 2
+; CHECK-NEXT: %[[element_load:.*]] = load i32, i32 addrspace(1)* %[[gep]]
 ; CHECK-NEXT: %[[insert:.*]] = insertelement <4 x i32> %x, i32 %[[element_load]], i32 2
 ; CHECK-NEXT: extractelement <4 x i32> %[[insert]], i32 2
 ; CHECK-NEXT: extractelement <4 x i32> %[[load]], i32 3
@@ -205,9 +205,9 @@ entry:
 	%a = alloca [2 x <4 x i32>]
 ; CHECK-NOT: alloca
 
-  %a.x = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 0
+  %a.x = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 0
   store <4 x i32> %x, <4 x i32>* %a.x
-  %a.y = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1
+  %a.y = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1
   store <4 x i32> %y, <4 x i32>* %a.y
 ; CHECK-NOT: store
 
@@ -216,18 +216,18 @@ entry:
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a.x.cast, i8* %a.y.cast, i32 16, i32 1, i1 false)
 ; CHECK-NOT: memcpy
 
-  %a.tmp1 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 0, i64 2
+  %a.tmp1 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 0, i64 2
   %a.tmp1.cast = bitcast i32* %a.tmp1 to i8*
-  %z.tmp1 = getelementptr inbounds <4 x i32>* %z, i64 0, i64 2
+  %z.tmp1 = getelementptr inbounds <4 x i32>, <4 x i32>* %z, i64 0, i64 2
   %z.tmp1.cast = bitcast i32* %z.tmp1 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %z.tmp1.cast, i8* %a.tmp1.cast, i32 4, i32 1, i1 false)
-  %tmp1 = load i32* %a.tmp1
-  %a.tmp2 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1, i64 3
-  %tmp2 = load i32* %a.tmp2
-  %a.tmp3 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1, i64 0
-  %tmp3 = load i32* %a.tmp3
+  %tmp1 = load i32, i32* %a.tmp1
+  %a.tmp2 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1, i64 3
+  %tmp2 = load i32, i32* %a.tmp2
+  %a.tmp3 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %a, i64 0, i64 1, i64 0
+  %tmp3 = load i32, i32* %a.tmp3
 ; CHECK-NOT: memcpy
-; CHECK:      %[[gep:.*]] = getelementptr inbounds <4 x i32>* %z, i64 0, i64 2
+; CHECK:      %[[gep:.*]] = getelementptr inbounds <4 x i32>, <4 x i32>* %z, i64 0, i64 2
 ; CHECK-NEXT: %[[extract:.*]] = extractelement <4 x i32> %y, i32 2
 ; CHECK-NEXT: store i32 %[[extract]], i32* %[[gep]]
 ; CHECK-NEXT: extractelement <4 x i32> %y, i32 2
@@ -250,14 +250,14 @@ define i64 @test6(<4 x i64> %x, <4 x i64> %y, i64 %n) {
 ; The old scalarrepl pass would wrongly drop the store to the second alloca.
 ; PR13254
   %tmp = alloca { <4 x i64>, <4 x i64> }
-  %p0 = getelementptr inbounds { <4 x i64>, <4 x i64> }* %tmp, i32 0, i32 0
+  %p0 = getelementptr inbounds { <4 x i64>, <4 x i64> }, { <4 x i64>, <4 x i64> }* %tmp, i32 0, i32 0
   store <4 x i64> %x, <4 x i64>* %p0
 ; CHECK: store <4 x i64> %x,
-  %p1 = getelementptr inbounds { <4 x i64>, <4 x i64> }* %tmp, i32 0, i32 1
+  %p1 = getelementptr inbounds { <4 x i64>, <4 x i64> }, { <4 x i64>, <4 x i64> }* %tmp, i32 0, i32 1
   store <4 x i64> %y, <4 x i64>* %p1
 ; CHECK: store <4 x i64> %y,
-  %addr = getelementptr inbounds { <4 x i64>, <4 x i64> }* %tmp, i32 0, i32 0, i64 %n
-  %res = load i64* %addr, align 4
+  %addr = getelementptr inbounds { <4 x i64>, <4 x i64> }, { <4 x i64>, <4 x i64> }* %tmp, i32 0, i32 0, i64 %n
+  %res = load i64, i64* %addr, align 4
   ret i64 %res
 }
 
@@ -267,27 +267,27 @@ entry:
   %a = alloca <4 x i32>
 ; CHECK-NOT: alloca
 
-  %a.gep0 = getelementptr <4 x i32>* %a, i32 0, i32 0
+  %a.gep0 = getelementptr <4 x i32>, <4 x i32>* %a, i32 0, i32 0
   %a.cast0 = bitcast i32* %a.gep0 to <2 x i32>*
   store <2 x i32> <i32 0, i32 0>, <2 x i32>* %a.cast0
 ; CHECK-NOT: store
 ; CHECK:     select <4 x i1> <i1 true, i1 true, i1 false, i1 false> 
 
-  %a.gep1 = getelementptr <4 x i32>* %a, i32 0, i32 1
+  %a.gep1 = getelementptr <4 x i32>, <4 x i32>* %a, i32 0, i32 1
   %a.cast1 = bitcast i32* %a.gep1 to <2 x i32>*
   store <2 x i32> <i32 1, i32 1>, <2 x i32>* %a.cast1
 ; CHECK-NEXT: select <4 x i1> <i1 false, i1 true, i1 true, i1 false>
 
-  %a.gep2 = getelementptr <4 x i32>* %a, i32 0, i32 2
+  %a.gep2 = getelementptr <4 x i32>, <4 x i32>* %a, i32 0, i32 2
   %a.cast2 = bitcast i32* %a.gep2 to <2 x i32>*
   store <2 x i32> <i32 2, i32 2>, <2 x i32>* %a.cast2
 ; CHECK-NEXT: select <4 x i1> <i1 false, i1 false, i1 true, i1 true>
 
-  %a.gep3 = getelementptr <4 x i32>* %a, i32 0, i32 3
+  %a.gep3 = getelementptr <4 x i32>, <4 x i32>* %a, i32 0, i32 3
   store i32 3, i32* %a.gep3
 ; CHECK-NEXT: insertelement <4 x i32>
 
-  %ret = load <4 x i32>* %a
+  %ret = load <4 x i32>, <4 x i32>* %a
 
   ret <4 x i32> %ret
 ; CHECK-NEXT: ret <4 x i32> 
@@ -301,20 +301,20 @@ entry:
   store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a
 ; CHECK-NOT: store
 
-  %a.gep0 = getelementptr <4 x i32>* %a, i32 0, i32 0
+  %a.gep0 = getelementptr <4 x i32>, <4 x i32>* %a, i32 0, i32 0
   %a.cast0 = bitcast i32* %a.gep0 to <2 x i32>*
-  %first = load <2 x i32>* %a.cast0
+  %first = load <2 x i32>, <2 x i32>* %a.cast0
 ; CHECK-NOT: load
 ; CHECK:      %[[extract1:.*]] = shufflevector <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
 
-  %a.gep1 = getelementptr <4 x i32>* %a, i32 0, i32 1
+  %a.gep1 = getelementptr <4 x i32>, <4 x i32>* %a, i32 0, i32 1
   %a.cast1 = bitcast i32* %a.gep1 to <2 x i32>*
-  %second = load <2 x i32>* %a.cast1
+  %second = load <2 x i32>, <2 x i32>* %a.cast1
 ; CHECK-NEXT: %[[extract2:.*]] = shufflevector <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> undef, <2 x i32> <i32 1, i32 2>
 
-  %a.gep2 = getelementptr <4 x i32>* %a, i32 0, i32 2
+  %a.gep2 = getelementptr <4 x i32>, <4 x i32>* %a, i32 0, i32 2
   %a.cast2 = bitcast i32* %a.gep2 to <2 x i32>*
-  %third = load <2 x i32>* %a.cast2
+  %third = load <2 x i32>, <2 x i32>* %a.cast2
 ; CHECK-NEXT: %[[extract3:.*]] = shufflevector <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
 
   %tmp = shufflevector <2 x i32> %first, <2 x i32> %second, <2 x i32> <i32 0, i32 2>
@@ -334,28 +334,28 @@ entry:
   %a = alloca <4 x float>
 ; CHECK-NOT: alloca
 
-  %a.gep0 = getelementptr <4 x float>* %a, i32 0, i32 0
+  %a.gep0 = getelementptr <4 x float>, <4 x float>* %a, i32 0, i32 0
   %a.cast0 = bitcast float* %a.gep0 to i8*
   call void @llvm.memset.p0i8.i32(i8* %a.cast0, i8 0, i32 8, i32 0, i1 false)
 ; CHECK-NOT: store
 ; CHECK: select <4 x i1> <i1 true, i1 true, i1 false, i1 false>
 
-  %a.gep1 = getelementptr <4 x float>* %a, i32 0, i32 1
+  %a.gep1 = getelementptr <4 x float>, <4 x float>* %a, i32 0, i32 1
   %a.cast1 = bitcast float* %a.gep1 to i8*
   call void @llvm.memset.p0i8.i32(i8* %a.cast1, i8 1, i32 8, i32 0, i1 false)
 ; CHECK-NEXT: select <4 x i1> <i1 false, i1 true, i1 true, i1 false>
 
-  %a.gep2 = getelementptr <4 x float>* %a, i32 0, i32 2
+  %a.gep2 = getelementptr <4 x float>, <4 x float>* %a, i32 0, i32 2
   %a.cast2 = bitcast float* %a.gep2 to i8*
   call void @llvm.memset.p0i8.i32(i8* %a.cast2, i8 3, i32 8, i32 0, i1 false)
 ; CHECK-NEXT: select <4 x i1> <i1 false, i1 false, i1 true, i1 true>
 
-  %a.gep3 = getelementptr <4 x float>* %a, i32 0, i32 3
+  %a.gep3 = getelementptr <4 x float>, <4 x float>* %a, i32 0, i32 3
   %a.cast3 = bitcast float* %a.gep3 to i8*
   call void @llvm.memset.p0i8.i32(i8* %a.cast3, i8 7, i32 4, i32 0, i1 false)
 ; CHECK-NEXT: insertelement <4 x float> 
 
-  %ret = load <4 x float>* %a
+  %ret = load <4 x float>, <4 x float>* %a
 
   ret <4 x float> %ret
 ; CHECK-NEXT: ret <4 x float> 
@@ -367,35 +367,35 @@ entry:
   %a = alloca <4 x float>
 ; CHECK-NOT: alloca
 
-  %a.gep0 = getelementptr <4 x float>* %a, i32 0, i32 0
+  %a.gep0 = getelementptr <4 x float>, <4 x float>* %a, i32 0, i32 0
   %a.cast0 = bitcast float* %a.gep0 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a.cast0, i8* %x, i32 8, i32 0, i1 false)
 ; CHECK:      %[[xptr:.*]] = bitcast i8* %x to <2 x float>*
-; CHECK-NEXT: %[[x:.*]] = load <2 x float>* %[[xptr]]
+; CHECK-NEXT: %[[x:.*]] = load <2 x float>, <2 x float>* %[[xptr]]
 ; CHECK-NEXT: %[[expand_x:.*]] = shufflevector <2 x float> %[[x]], <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT: select <4 x i1> <i1 true, i1 true, i1 false, i1 false>  
 
-  %a.gep1 = getelementptr <4 x float>* %a, i32 0, i32 1
+  %a.gep1 = getelementptr <4 x float>, <4 x float>* %a, i32 0, i32 1
   %a.cast1 = bitcast float* %a.gep1 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a.cast1, i8* %y, i32 8, i32 0, i1 false)
 ; CHECK-NEXT: %[[yptr:.*]] = bitcast i8* %y to <2 x float>*
-; CHECK-NEXT: %[[y:.*]] = load <2 x float>* %[[yptr]]
+; CHECK-NEXT: %[[y:.*]] = load <2 x float>, <2 x float>* %[[yptr]]
 ; CHECK-NEXT: %[[expand_y:.*]] = shufflevector <2 x float> %[[y]], <2 x float> undef, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>
 ; CHECK-NEXT: select <4 x i1> <i1 false, i1 true, i1 true, i1 false>
 
-  %a.gep2 = getelementptr <4 x float>* %a, i32 0, i32 2
+  %a.gep2 = getelementptr <4 x float>, <4 x float>* %a, i32 0, i32 2
   %a.cast2 = bitcast float* %a.gep2 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a.cast2, i8* %z, i32 8, i32 0, i1 false)
 ; CHECK-NEXT: %[[zptr:.*]] = bitcast i8* %z to <2 x float>*
-; CHECK-NEXT: %[[z:.*]] = load <2 x float>* %[[zptr]]
+; CHECK-NEXT: %[[z:.*]] = load <2 x float>, <2 x float>* %[[zptr]]
 ; CHECK-NEXT: %[[expand_z:.*]] = shufflevector <2 x float> %[[z]], <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
 ; CHECK-NEXT: select <4 x i1> <i1 false, i1 false, i1 true, i1 true>
 
-  %a.gep3 = getelementptr <4 x float>* %a, i32 0, i32 3
+  %a.gep3 = getelementptr <4 x float>, <4 x float>* %a, i32 0, i32 3
   %a.cast3 = bitcast float* %a.gep3 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a.cast3, i8* %f, i32 4, i32 0, i1 false)
 ; CHECK-NEXT: %[[fptr:.*]] = bitcast i8* %f to float*
-; CHECK-NEXT: %[[f:.*]] = load float* %[[fptr]]
+; CHECK-NEXT: %[[f:.*]] = load float, float* %[[fptr]]
 ; CHECK-NEXT: %[[insert_f:.*]] = insertelement <4 x float> 
 
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %out, i8* %a.cast2, i32 8, i32 0, i1 false)
@@ -403,7 +403,7 @@ entry:
 ; CHECK-NEXT: %[[extract_out:.*]] = shufflevector <4 x float> %[[insert_f]], <4 x float> undef, <2 x i32> <i32 2, i32 3>
 ; CHECK-NEXT: store <2 x float> %[[extract_out]], <2 x float>* %[[outptr]]
 
-  %ret = load <4 x float>* %a
+  %ret = load <4 x float>, <4 x float>* %a
 
   ret <4 x float> %ret
 ; CHECK-NEXT: ret <4 x float> %[[insert_f]]
@@ -419,7 +419,7 @@ entry:
 
   store <3 x i8> undef, <3 x i8>* %retval, align 4
   %cast = bitcast <3 x i8>* %retval to i32*
-  %load = load i32* %cast, align 4
+  %load = load i32, i32* %cast, align 4
   ret i32 %load
 ; CHECK: ret i32
 }
@@ -437,7 +437,7 @@ entry:
 ; CHECK-NOT: store
 
   %cast = bitcast i32* %a to <2 x i8>*
-  %vec = load <2 x i8>* %cast
+  %vec = load <2 x i8>, <2 x i8>* %cast
 ; CHECK-NOT: load
 
   ret <2 x i8> %vec
@@ -459,7 +459,7 @@ entry:
   store <2 x i8> %x, <2 x i8>* %cast
 ; CHECK-NOT: store
 
-  %int = load i32* %a
+  %int = load i32, i32* %a
 ; CHECK-NOT: load
 
   ret i32 %int
@@ -477,18 +477,18 @@ entry:
   %a.cast = bitcast [2 x i64]* %a to [2 x <2 x i32>]*
 ; CHECK-NOT: alloca
 
-  %a.x = getelementptr inbounds [2 x <2 x i32>]* %a.cast, i64 0, i64 0
+  %a.x = getelementptr inbounds [2 x <2 x i32>], [2 x <2 x i32>]* %a.cast, i64 0, i64 0
   store <2 x i32> %x, <2 x i32>* %a.x
-  %a.y = getelementptr inbounds [2 x <2 x i32>]* %a.cast, i64 0, i64 1
+  %a.y = getelementptr inbounds [2 x <2 x i32>], [2 x <2 x i32>]* %a.cast, i64 0, i64 1
   store <2 x i32> %y, <2 x i32>* %a.y
 ; CHECK-NOT: store
 
-  %a.tmp1 = getelementptr inbounds [2 x <2 x i32>]* %a.cast, i64 0, i64 0, i64 1
-  %tmp1 = load i32* %a.tmp1
-  %a.tmp2 = getelementptr inbounds [2 x <2 x i32>]* %a.cast, i64 0, i64 1, i64 1
-  %tmp2 = load i32* %a.tmp2
-  %a.tmp3 = getelementptr inbounds [2 x <2 x i32>]* %a.cast, i64 0, i64 1, i64 0
-  %tmp3 = load i32* %a.tmp3
+  %a.tmp1 = getelementptr inbounds [2 x <2 x i32>], [2 x <2 x i32>]* %a.cast, i64 0, i64 0, i64 1
+  %tmp1 = load i32, i32* %a.tmp1
+  %a.tmp2 = getelementptr inbounds [2 x <2 x i32>], [2 x <2 x i32>]* %a.cast, i64 0, i64 1, i64 1
+  %tmp2 = load i32, i32* %a.tmp2
+  %a.tmp3 = getelementptr inbounds [2 x <2 x i32>], [2 x <2 x i32>]* %a.cast, i64 0, i64 1, i64 0
+  %tmp3 = load i32, i32* %a.tmp3
 ; CHECK-NOT: load
 ; CHECK:      extractelement <2 x i32> %x, i32 1
 ; CHECK-NEXT: extractelement <2 x i32> %y, i32 1
@@ -515,9 +515,9 @@ entry:
   store <2 x i32> %x, <2 x i32>* %a.vec
 ; CHECK-NOT: store
 
-  %tmp1 = load i32* %a.i32
-  %a.tmp2 = getelementptr inbounds i32* %a.i32, i64 1
-  %tmp2 = load i32* %a.tmp2
+  %tmp1 = load i32, i32* %a.i32
+  %a.tmp2 = getelementptr inbounds i32, i32* %a.i32, i64 1
+  %tmp2 = load i32, i32* %a.tmp2
 ; CHECK-NOT: load
 ; CHECK:      extractelement <2 x i32> %x, i32 0
 ; CHECK-NEXT: extractelement <2 x i32> %x, i32 1
@@ -539,13 +539,13 @@ entry:
 ; CHECK-NOT: alloca
 
   store i32 %x, i32* %a.i32
-  %a.tmp2 = getelementptr inbounds i32* %a.i32, i64 1
+  %a.tmp2 = getelementptr inbounds i32, i32* %a.i32, i64 1
   store i32 %y, i32* %a.tmp2
 ; CHECK-NOT: store
 ; CHECK:      %[[V1:.*]] = insertelement <2 x i32> undef, i32 %x, i32 0
 ; CHECK-NEXT: %[[V2:.*]] = insertelement <2 x i32> %[[V1]], i32 %y, i32 1
 
-  %result = load <2 x i32>* %a.vec
+  %result = load <2 x i32>, <2 x i32>* %a.vec
 ; CHECK-NOT:  load
 
   ret <2 x i32> %result
@@ -564,13 +564,13 @@ entry:
 ; CHECK-NOT: alloca
 
   store <4 x i16> %x, <4 x i16>* %a.vec2
-  %a.tmp2 = getelementptr inbounds i32* %a.i32, i64 1
+  %a.tmp2 = getelementptr inbounds i32, i32* %a.i32, i64 1
   store i32 %y, i32* %a.tmp2
 ; CHECK-NOT: store
 ; CHECK:      %[[V1:.*]] = bitcast <4 x i16> %x to <2 x i32>
 ; CHECK-NEXT: %[[V2:.*]] = insertelement <2 x i32> %[[V1]], i32 %y, i32 1
 
-  %result = load <2 x i32>* %a.vec1
+  %result = load <2 x i32>, <2 x i32>* %a.vec1
 ; CHECK-NOT:  load
 
   ret <2 x i32> %result
@@ -590,7 +590,7 @@ entry:
 ; CHECK-NOT: alloca
 
   store <4 x i16> %x, <4 x i16>* %a.vec2
-  %a.tmp2 = getelementptr inbounds i32* %a.i32, i64 1
+  %a.tmp2 = getelementptr inbounds i32, i32* %a.i32, i64 1
   store i32 %y, i32* %a.tmp2
 ; CHECK-NOT: store
 ; CHECK:      %[[V1:.*]] = bitcast i32 %y to <2 x i16>
@@ -598,7 +598,7 @@ entry:
 ; CHECK-NEXT: %[[V3:.*]] = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x i16> %[[V2]], <4 x i16> %x
 ; CHECK-NEXT: %[[V4:.*]] = bitcast <4 x i16> %[[V3]] to <2 x float>
 
-  %result = load <2 x float>* %a.vec1
+  %result = load <2 x float>, <2 x float>* %a.vec1
 ; CHECK-NOT:  load
 
   ret <2 x float> %result
@@ -616,7 +616,7 @@ define <4 x float> @test12() {
 
   %cast2 = bitcast <3 x i32>* %a to <3 x float>*
   %cast3 = bitcast <3 x float>* %cast2 to <4 x float>*
-  %vec = load <4 x float>* %cast3
+  %vec = load <4 x float>, <4 x float>* %cast3
 ; CHECK-NOT: load
 
 ; CHECK:      %[[ret:.*]] = bitcast <4 x i32> undef to <4 x float>
diff --git a/test/Transforms/SROA/vectors-of-pointers.ll b/test/Transforms/SROA/vectors-of-pointers.ll
index 7e995b9e4476..ff09e9598965 100644
--- a/test/Transforms/SROA/vectors-of-pointers.ll
+++ b/test/Transforms/SROA/vectors-of-pointers.ll
@@ -20,6 +20,6 @@ if.then.i.i.i.i.i237:
   unreachable
 
 bb0.exit257:
-  %0 = load <2 x i32*>* %Args.i, align 16
+  %0 = load <2 x i32*>, <2 x i32*>* %Args.i, align 16
   unreachable
 }
diff --git a/test/Transforms/SampleProfile/Inputs/entry_counts.prof b/test/Transforms/SampleProfile/Inputs/entry_counts.prof
new file mode 100644
index 000000000000..5c2172b5a4d3
--- /dev/null
+++ b/test/Transforms/SampleProfile/Inputs/entry_counts.prof
@@ -0,0 +1,3 @@
+empty:100:13293
+0: 0
+1: 100
diff --git a/test/Transforms/SampleProfile/branch.ll b/test/Transforms/SampleProfile/branch.ll
index 6391fc5158cf..25bd455a044c 100644
--- a/test/Transforms/SampleProfile/branch.ll
+++ b/test/Transforms/SampleProfile/branch.ll
@@ -32,22 +32,22 @@ define i32 @main(i32 %argc, i8** nocapture readonly %argv) #0 {
 ; CHECK: Printing analysis 'Branch Probability Analysis' for function 'main':
 
 entry:
-  tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !13, metadata !{}), !dbg !27
-  tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !14, metadata !{}), !dbg !27
+  tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !13, metadata !DIExpression()), !dbg !27
+  tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !14, metadata !DIExpression()), !dbg !27
   %cmp = icmp slt i32 %argc, 2, !dbg !28
   br i1 %cmp, label %return, label %if.end, !dbg !28
-; CHECK: edge entry -> return probability is 1 / 2 = 50%
-; CHECK: edge entry -> if.end probability is 1 / 2 = 50%
+; CHECK: edge entry -> return probability is 0 / 1 = 0%
+; CHECK: edge entry -> if.end probability is 1 / 1 = 100%
 
 if.end:                                           ; preds = %entry
-  %arrayidx = getelementptr inbounds i8** %argv, i64 1, !dbg !30
-  %0 = load i8** %arrayidx, align 8, !dbg !30, !tbaa !31
+  %arrayidx = getelementptr inbounds i8*, i8** %argv, i64 1, !dbg !30
+  %0 = load i8*, i8** %arrayidx, align 8, !dbg !30, !tbaa !31
   %call = tail call i32 @atoi(i8* %0) #4, !dbg !30
-  tail call void @llvm.dbg.value(metadata i32 %call, i64 0, metadata !17, metadata !{}), !dbg !30
+  tail call void @llvm.dbg.value(metadata i32 %call, i64 0, metadata !17, metadata !DIExpression()), !dbg !30
   %cmp1 = icmp sgt i32 %call, 100, !dbg !35
   br i1 %cmp1, label %for.body, label %if.end6, !dbg !35
-; CHECK: edge if.end -> for.body probability is 1 / 2 = 50%
-; CHECK: edge if.end -> if.end6 probability is 1 / 2 = 50%
+; CHECK: edge if.end -> for.body probability is 0 / 1 = 0%
+; CHECK: edge if.end -> if.end6 probability is 1 / 1 = 100%
 
 for.body:                                         ; preds = %if.end, %for.body
   %u.016 = phi i32 [ %inc, %for.body ], [ 0, %if.end ]
@@ -55,22 +55,22 @@ for.body:                                         ; preds = %if.end, %for.body
   %add = fadd double %s.015, 3.049000e+00, !dbg !36
   %conv = sitofp i32 %u.016 to double, !dbg !36
   %add4 = fadd double %add, %conv, !dbg !36
-  tail call void @llvm.dbg.value(metadata double %add4, i64 0, metadata !18, metadata !{}), !dbg !36
+  tail call void @llvm.dbg.value(metadata double %add4, i64 0, metadata !18, metadata !DIExpression()), !dbg !36
   %div = fdiv double 3.940000e+00, %s.015, !dbg !37
   %mul = fmul double %div, 3.200000e-01, !dbg !37
   %add5 = fadd double %add4, %mul, !dbg !37
   %sub = fsub double %add4, %add5, !dbg !37
-  tail call void @llvm.dbg.value(metadata double %sub, i64 0, metadata !18, metadata !{}), !dbg !37
+  tail call void @llvm.dbg.value(metadata double %sub, i64 0, metadata !18, metadata !DIExpression()), !dbg !37
   %inc = add nsw i32 %u.016, 1, !dbg !38
-  tail call void @llvm.dbg.value(metadata i32 %inc, i64 0, metadata !21, metadata !{}), !dbg !38
+  tail call void @llvm.dbg.value(metadata i32 %inc, i64 0, metadata !21, metadata !DIExpression()), !dbg !38
   %exitcond = icmp eq i32 %inc, %call, !dbg !38
   br i1 %exitcond, label %if.end6, label %for.body, !dbg !38
-; CHECK: edge for.body -> if.end6 probability is 1 / 10227 = 0.00977804
-; CHECK: edge for.body -> for.body probability is 10226 / 10227 = 99.9902% [HOT edge]
+; CHECK: edge for.body -> if.end6 probability is 0 / 10226 = 0%
+; CHECK: edge for.body -> for.body probability is 10226 / 10226 = 100% [HOT edge]
 
 if.end6:                                          ; preds = %for.body, %if.end
   %result.0 = phi double [ 0.000000e+00, %if.end ], [ %sub, %for.body ]
-  %call7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([15 x i8]* @.str, i64 0, i64 0), double %result.0), !dbg !39
+  %call7 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @.str, i64 0, i64 0), double %result.0), !dbg !39
   br label %return, !dbg !40
 ; CHECK: edge if.end6 -> return probability is 16 / 16 = 100% [HOT edge]
 
@@ -98,46 +98,46 @@ attributes #4 = { nounwind readonly }
 !llvm.module.flags = !{!25, !42}
 !llvm.ident = !{!26}
 
-!0 = !{!"0x11\004\00clang version 3.4 (trunk 192896) (llvm/trunk 192895)\001\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [./branch.cc] [DW_LANG_C_plus_plus]
-!1 = !{!"branch.cc", !"."}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.4 (trunk 192896) (llvm/trunk 192895)", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "branch.cc", directory: ".")
+!2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00main\00main\00\004\000\001\000\006\00256\001\004", !1, !5, !6, null, i32 (i32, i8**)* @main, null, null, !12} ; [ DW_TAG_subprogram ] [line 4] [def] [main]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [./branch.cc]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "main", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 4, file: !1, scope: !5, type: !6, function: i32 (i32, i8**)* @main, variables: !12)
+!5 = !DIFile(filename: "branch.cc", directory: ".")
+!6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8, !9}
-!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = !{!"0xf\00\000\0064\0064\000\000", null, null, !10} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
-!10 = !{!"0xf\00\000\0064\0064\000\000", null, null, !11} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char]
-!11 = !{!"0x24\00char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
+!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !10)
+!10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !11)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
 !12 = !{!13, !14, !15, !17, !18, !21, !23}
-!13 = !{!"0x101\00argc\0016777220\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [argc] [line 4]
-!14 = !{!"0x101\00argv\0033554436\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [argv] [line 4]
-!15 = !{!"0x100\00result\007\000", !4, !5, !16} ; [ DW_TAG_auto_variable ] [result] [line 7]
-!16 = !{!"0x24\00double\000\0064\0064\000\000\004", null, null} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float]
-!17 = !{!"0x100\00limit\008\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [limit] [line 8]
-!18 = !{!"0x100\00s\0010\000", !19, !5, !16} ; [ DW_TAG_auto_variable ] [s] [line 10]
-!19 = !{!"0xb\009\000\000", !1, !20} ; [ DW_TAG_lexical_block ] [./branch.cc]
-!20 = !{!"0xb\009\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [./branch.cc]
-!21 = !{!"0x100\00u\0011\000", !22, !5, !8} ; [ DW_TAG_auto_variable ] [u] [line 11]
-!22 = !{!"0xb\0011\000\000", !1, !19} ; [ DW_TAG_lexical_block ] [./branch.cc]
-!23 = !{!"0x100\00x\0012\000", !24, !5, !16} ; [ DW_TAG_auto_variable ] [x] [line 12]
-!24 = !{!"0xb\0011\000\000", !1, !22} ; [ DW_TAG_lexical_block ] [./branch.cc]
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 4, arg: 1, scope: !4, file: !5, type: !8)
+!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 4, arg: 2, scope: !4, file: !5, type: !9)
+!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "result", line: 7, scope: !4, file: !5, type: !16)
+!16 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 64, encoding: DW_ATE_float)
+!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "limit", line: 8, scope: !4, file: !5, type: !8)
+!18 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "s", line: 10, scope: !19, file: !5, type: !16)
+!19 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !20)
+!20 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !4)
+!21 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "u", line: 11, scope: !22, file: !5, type: !8)
+!22 = distinct !DILexicalBlock(line: 11, column: 0, file: !1, scope: !19)
+!23 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 12, scope: !24, file: !5, type: !16)
+!24 = distinct !DILexicalBlock(line: 11, column: 0, file: !1, scope: !22)
 !25 = !{i32 2, !"Dwarf Version", i32 4}
 !26 = !{!"clang version 3.4 (trunk 192896) (llvm/trunk 192895)"}
-!27 = !MDLocation(line: 4, scope: !4)
-!28 = !MDLocation(line: 5, scope: !29)
-!29 = !{!"0xb\005\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [./branch.cc]
-!30 = !MDLocation(line: 8, scope: !4)
+!27 = !DILocation(line: 4, scope: !4)
+!28 = !DILocation(line: 5, scope: !29)
+!29 = distinct !DILexicalBlock(line: 5, column: 0, file: !1, scope: !4)
+!30 = !DILocation(line: 8, scope: !4)
 !31 = !{!32, !32, i64 0}
 !32 = !{!"any pointer", !33, i64 0}
 !33 = !{!"omnipotent char", !34, i64 0}
 !34 = !{!"Simple C/C++ TBAA"}
-!35 = !MDLocation(line: 9, scope: !20)
-!36 = !MDLocation(line: 13, scope: !24)
-!37 = !MDLocation(line: 14, scope: !24)
-!38 = !MDLocation(line: 11, scope: !22)
-!39 = !MDLocation(line: 20, scope: !4)
-!40 = !MDLocation(line: 21, scope: !4)
-!41 = !MDLocation(line: 22, scope: !4)
-!42 = !{i32 1, !"Debug Info Version", i32 2}
+!35 = !DILocation(line: 9, scope: !20)
+!36 = !DILocation(line: 13, scope: !24)
+!37 = !DILocation(line: 14, scope: !24)
+!38 = !DILocation(line: 11, scope: !22)
+!39 = !DILocation(line: 20, scope: !4)
+!40 = !DILocation(line: 21, scope: !4)
+!41 = !DILocation(line: 22, scope: !4)
+!42 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/SampleProfile/calls.ll b/test/Transforms/SampleProfile/calls.ll
index d56660937bc0..10f43a1a6126 100644
--- a/test/Transforms/SampleProfile/calls.ll
+++ b/test/Transforms/SampleProfile/calls.ll
@@ -30,8 +30,8 @@ entry:
   %y.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
   store i32 %y, i32* %y.addr, align 4
-  %0 = load i32* %x.addr, align 4, !dbg !11
-  %1 = load i32* %y.addr, align 4, !dbg !11
+  %0 = load i32, i32* %x.addr, align 4, !dbg !11
+  %1 = load i32, i32* %y.addr, align 4, !dbg !11
   %add = add nsw i32 %0, %1, !dbg !11
   ret i32 %add, !dbg !11
 }
@@ -47,29 +47,29 @@ entry:
   br label %while.cond, !dbg !13
 
 while.cond:                                       ; preds = %if.end, %entry
-  %0 = load i32* %i, align 4, !dbg !14
+  %0 = load i32, i32* %i, align 4, !dbg !14
   %inc = add nsw i32 %0, 1, !dbg !14
   store i32 %inc, i32* %i, align 4, !dbg !14
   %cmp = icmp slt i32 %0, 400000000, !dbg !14
   br i1 %cmp, label %while.body, label %while.end, !dbg !14
-; CHECK: edge while.cond -> while.body probability is 5391 / 5392 = 99.9815% [HOT edge]
-; CHECK: edge while.cond -> while.end probability is 1 / 5392 = 0.018546%
+; CHECK: edge while.cond -> while.body probability is 5391 / 5391 = 100% [HOT edge]
+; CHECK: edge while.cond -> while.end probability is 0 / 5391 = 0%
 
 while.body:                                       ; preds = %while.cond
-  %1 = load i32* %i, align 4, !dbg !16
+  %1 = load i32, i32* %i, align 4, !dbg !16
   %cmp1 = icmp ne i32 %1, 100, !dbg !16
   br i1 %cmp1, label %if.then, label %if.else, !dbg !16
 ; Without discriminator information, the profiler used to think that
 ; both branches out of while.body had the same weight. In reality,
 ; the edge while.body->if.then is taken most of the time.
 ;
-; CHECK: edge while.body -> if.then probability is 5752 / 5753 = 99.9826% [HOT edge]
-; CHECK: edge while.body -> if.else probability is 1 / 5753 = 0.0173822%
+; CHECK: edge while.body -> if.then probability is 5752 / 5752 = 100% [HOT edge]
+; CHECK: edge while.body -> if.else probability is 0 / 5752 = 0%
 
 
 if.then:                                          ; preds = %while.body
-  %2 = load i32* %i, align 4, !dbg !18
-  %3 = load i32* %s, align 4, !dbg !18
+  %2 = load i32, i32* %i, align 4, !dbg !18
+  %3 = load i32, i32* %s, align 4, !dbg !18
   %call = call i32 @_Z3sumii(i32 %2, i32 %3), !dbg !18
   store i32 %call, i32* %s, align 4, !dbg !18
   br label %if.end, !dbg !18
@@ -82,8 +82,8 @@ if.end:                                           ; preds = %if.else, %if.then
   br label %while.cond, !dbg !22
 
 while.end:                                        ; preds = %while.cond
-  %4 = load i32* %s, align 4, !dbg !24
-  %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i32 %4), !dbg !24
+  %4 = load i32, i32* %s, align 4, !dbg !24
+  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i32 %4), !dbg !24
   ret i32 0, !dbg !25
 }
 
@@ -92,29 +92,29 @@ declare i32 @printf(i8*, ...) #2
 !llvm.module.flags = !{!8, !9}
 !llvm.ident = !{!10}
 
-!0 = !{!"0x11\004\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [./calls.cc] [DW_LANG_C_plus_plus]
-!1 = !{!"calls.cc", !"."}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "calls.cc", directory: ".")
 !2 = !{}
 !3 = !{!4, !7}
-!4 = !{!"0x2e\00sum\00sum\00\003\000\001\000\006\00256\000\003", !1, !5, !6, null, i32 (i32, i32)* @_Z3sumii, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [sum]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [./calls.cc]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!7 = !{!"0x2e\00main\00main\00\007\000\001\000\006\00256\000\007", !1, !5, !6, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 7] [def] [main]
+!4 = !DISubprogram(name: "sum", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !5, type: !6, function: i32 (i32, i32)* @_Z3sumii, variables: !2)
+!5 = !DIFile(filename: "calls.cc", directory: ".")
+!6 = !DISubroutineType(types: !2)
+!7 = !DISubprogram(name: "main", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 7, file: !1, scope: !5, type: !6, function: i32 ()* @main, variables: !2)
 !8 = !{i32 2, !"Dwarf Version", i32 4}
-!9 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !{i32 1, !"Debug Info Version", i32 3}
 !10 = !{!"clang version 3.5 "}
-!11 = !MDLocation(line: 4, scope: !4)
-!12 = !MDLocation(line: 8, scope: !7)
-!13 = !MDLocation(line: 9, scope: !7)
-!14 = !MDLocation(line: 9, scope: !15)
-!15 = !{!"0xb\001", !1, !7} ; [ DW_TAG_lexical_block ] [./calls.cc]
-!16 = !MDLocation(line: 10, scope: !17)
-!17 = !{!"0xb\0010\000\000", !1, !7} ; [ DW_TAG_lexical_block ] [./calls.cc]
-!18 = !MDLocation(line: 10, scope: !19)
-!19 = !{!"0xb\001", !1, !17} ; [ DW_TAG_lexical_block ] [./calls.cc]
-!20 = !MDLocation(line: 10, scope: !21)
-!21 = !{!"0xb\002", !1, !17} ; [ DW_TAG_lexical_block ] [./calls.cc]
-!22 = !MDLocation(line: 10, scope: !23)
-!23 = !{!"0xb\003", !1, !17} ; [ DW_TAG_lexical_block ] [./calls.cc]
-!24 = !MDLocation(line: 11, scope: !7)
-!25 = !MDLocation(line: 12, scope: !7)
+!11 = !DILocation(line: 4, scope: !4)
+!12 = !DILocation(line: 8, scope: !7)
+!13 = !DILocation(line: 9, scope: !7)
+!14 = !DILocation(line: 9, scope: !15)
+!15 = !DILexicalBlockFile(discriminator: 1, file: !1, scope: !7)
+!16 = !DILocation(line: 10, scope: !17)
+!17 = distinct !DILexicalBlock(line: 10, column: 0, file: !1, scope: !7)
+!18 = !DILocation(line: 10, scope: !19)
+!19 = !DILexicalBlockFile(discriminator: 1, file: !1, scope: !17)
+!20 = !DILocation(line: 10, scope: !21)
+!21 = !DILexicalBlockFile(discriminator: 2, file: !1, scope: !17)
+!22 = !DILocation(line: 10, scope: !23)
+!23 = !DILexicalBlockFile(discriminator: 3, file: !1, scope: !17)
+!24 = !DILocation(line: 11, scope: !7)
+!25 = !DILocation(line: 12, scope: !7)
diff --git a/test/Transforms/SampleProfile/discriminator.ll b/test/Transforms/SampleProfile/discriminator.ll
index cafc69d14923..2445c5c5d609 100644
--- a/test/Transforms/SampleProfile/discriminator.ll
+++ b/test/Transforms/SampleProfile/discriminator.ll
@@ -31,33 +31,33 @@ entry:
   br label %while.cond, !dbg !11
 
 while.cond:                                       ; preds = %if.end, %entry
-  %0 = load i32* %i.addr, align 4, !dbg !12
+  %0 = load i32, i32* %i.addr, align 4, !dbg !12
   %cmp = icmp slt i32 %0, 100, !dbg !12
   br i1 %cmp, label %while.body, label %while.end, !dbg !12
 ; CHECK: edge while.cond -> while.body probability is 100 / 101 = 99.0099% [HOT edge]
 ; CHECK: edge while.cond -> while.end probability is 1 / 101 = 0.990099%
 
 while.body:                                       ; preds = %while.cond
-  %1 = load i32* %i.addr, align 4, !dbg !14
+  %1 = load i32, i32* %i.addr, align 4, !dbg !14
   %cmp1 = icmp slt i32 %1, 50, !dbg !14
   br i1 %cmp1, label %if.then, label %if.end, !dbg !14
 ; CHECK: edge while.body -> if.then probability is 5 / 100 = 5%
 ; CHECK: edge while.body -> if.end probability is 95 / 100 = 95% [HOT edge]
 
 if.then:                                          ; preds = %while.body
-  %2 = load i32* %x, align 4, !dbg !17
+  %2 = load i32, i32* %x, align 4, !dbg !17
   %dec = add nsw i32 %2, -1, !dbg !17
   store i32 %dec, i32* %x, align 4, !dbg !17
   br label %if.end, !dbg !17
 
 if.end:                                           ; preds = %if.then, %while.body
-  %3 = load i32* %i.addr, align 4, !dbg !19
+  %3 = load i32, i32* %i.addr, align 4, !dbg !19
   %inc = add nsw i32 %3, 1, !dbg !19
   store i32 %inc, i32* %i.addr, align 4, !dbg !19
   br label %while.cond, !dbg !20
 
 while.end:                                        ; preds = %while.cond
-  %4 = load i32* %x, align 4, !dbg !21
+  %4 = load i32, i32* %x, align 4, !dbg !21
   ret i32 %4, !dbg !21
 }
 
@@ -66,25 +66,25 @@ while.end:                                        ; preds = %while.cond
 !llvm.module.flags = !{!7, !8}
 !llvm.ident = !{!9}
 
-!0 = !{!"0x11\0012\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [discriminator.c] [DW_LANG_C99]
-!1 = !{!"discriminator.c", !"."}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "discriminator.c", directory: ".")
 !2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\000\001", !1, !5, !6, null, i32 (i32)* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [discriminator.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: i32 (i32)* @foo, variables: !2)
+!5 = !DIFile(filename: "discriminator.c", directory: ".")
+!6 = !DISubroutineType(types: !2)
 !7 = !{i32 2, !"Dwarf Version", i32 4}
-!8 = !{i32 1, !"Debug Info Version", i32 2}
+!8 = !{i32 1, !"Debug Info Version", i32 3}
 !9 = !{!"clang version 3.5 "}
-!10 = !MDLocation(line: 2, scope: !4)
-!11 = !MDLocation(line: 3, scope: !4)
-!12 = !MDLocation(line: 3, scope: !13)
-!13 = !{!"0xb\001", !1, !4} ; [ DW_TAG_lexical_block ] [discriminator.c]
-!14 = !MDLocation(line: 4, scope: !15)
-!15 = !{!"0xb\004\000\001", !1, !16} ; [ DW_TAG_lexical_block ] [discriminator.c]
-!16 = !{!"0xb\003\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [discriminator.c]
-!17 = !MDLocation(line: 4, scope: !18)
-!18 = !{!"0xb\001", !1, !15} ; [ DW_TAG_lexical_block ] [discriminator.c]
-!19 = !MDLocation(line: 5, scope: !16)
-!20 = !MDLocation(line: 6, scope: !16)
-!21 = !MDLocation(line: 7, scope: !4)
+!10 = !DILocation(line: 2, scope: !4)
+!11 = !DILocation(line: 3, scope: !4)
+!12 = !DILocation(line: 3, scope: !13)
+!13 = !DILexicalBlockFile(discriminator: 1, file: !1, scope: !4)
+!14 = !DILocation(line: 4, scope: !15)
+!15 = distinct !DILexicalBlock(line: 4, column: 0, file: !1, scope: !16)
+!16 = distinct !DILexicalBlock(line: 3, column: 0, file: !1, scope: !4)
+!17 = !DILocation(line: 4, scope: !18)
+!18 = !DILexicalBlockFile(discriminator: 1, file: !1, scope: !15)
+!19 = !DILocation(line: 5, scope: !16)
+!20 = !DILocation(line: 6, scope: !16)
+!21 = !DILocation(line: 7, scope: !4)
diff --git a/test/Transforms/SampleProfile/entry_counts.ll b/test/Transforms/SampleProfile/entry_counts.ll
new file mode 100644
index 000000000000..bf66e693a9d1
--- /dev/null
+++ b/test/Transforms/SampleProfile/entry_counts.ll
@@ -0,0 +1,24 @@
+; RUN: opt < %s -sample-profile -sample-profile-file=%S/Inputs/entry_counts.prof -S | FileCheck %s
+
+; According to the profile, function empty() was called 13,293 times.
+; CHECK: {{.*}} = !{!"function_entry_count", i64 13293}
+
+define void @empty() {
+entry:
+  ret void, !dbg !9
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!6, !7}
+!llvm.ident = !{!8}
+
+!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 237249) (llvm/trunk 237261)", isOptimized: false, runtimeVersion: 0, emissionKind: 2, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "entry_counts.c", directory: "/usr/local/google/home/dnovillo/llvm/test/pgo")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "empty", scope: !1, file: !1, line: 1, type: !5, isLocal: false, isDefinition: true, scopeLine: 1, isOptimized: false, function: void ()* @empty, variables: !2)
+!5 = !DISubroutineType(types: !2)
+!6 = !{i32 2, !"Dwarf Version", i32 4}
+!7 = !{i32 2, !"Debug Info Version", i32 3}
+!8 = !{!"clang version 3.7.0 (trunk 237249) (llvm/trunk 237261)"}
+!9 = !DILocation(line: 1, column: 15, scope: !4)
diff --git a/test/Transforms/SampleProfile/fnptr.ll b/test/Transforms/SampleProfile/fnptr.ll
index 096033bd35fc..368da42fc8a1 100644
--- a/test/Transforms/SampleProfile/fnptr.ll
+++ b/test/Transforms/SampleProfile/fnptr.ll
@@ -114,7 +114,7 @@ for.inc12:                                        ; preds = %for.inc
 
 for.end14:                                        ; preds = %for.inc12
   %S.2.lcssa.lcssa = phi double [ %S.2.lcssa, %for.inc12 ]
-  %call15 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i64 0, i64 0), double %S.2.lcssa.lcssa), !dbg !24
+  %call15 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i64 0, i64 0), double %S.2.lcssa.lcssa), !dbg !24
   ret i32 0, !dbg !25
 }
 
@@ -127,29 +127,29 @@ declare i32 @printf(i8* nocapture readonly, ...) #1
 !llvm.module.flags = !{!0}
 !llvm.ident = !{!1}
 
-!0 = !{i32 2, !"Debug Info Version", i32 2}
+!0 = !{i32 2, !"Debug Info Version", i32 3}
 !1 = !{!"clang version 3.6.0 "}
-!2 = !MDLocation(line: 9, column: 3, scope: !3)
-!3 = !{!"0x2e\00foo\00foo\00\008\000\001\000\000\00256\001\008", !4, !5, !6, null, double (i32)* @_Z3fooi, null, null, !7} ; [ DW_TAG_subprogram ] [line 8] [def] [foo]
-!4 = !{!"fnptr.cc", !"."}
-!5 = !{!"0x29", !4}    ; [ DW_TAG_file_type ] [./fnptr.cc]
-!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!2 = !DILocation(line: 9, column: 3, scope: !3)
+!3 = !DISubprogram(name: "foo", line: 8, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 8, file: !4, scope: !5, type: !6, function: double (i32)* @_Z3fooi, variables: !7)
+!4 = !DIFile(filename: "fnptr.cc", directory: ".")
+!5 = !DIFile(filename: "fnptr.cc", directory: ".")
+!6 = !DISubroutineType(types: !7)
 !7 = !{}
-!8 = !MDLocation(line: 9, column: 14, scope: !3)
-!9 = !MDLocation(line: 13, column: 3, scope: !10)
-!10 = !{!"0x2e\00bar\00bar\00\0012\000\001\000\000\00256\001\0012", !4, !5, !6, null, double (i32)* @_Z3bari, null, null, !7} ; [ DW_TAG_subprogram ] [line 12] [def] [bar]
-!11 = !MDLocation(line: 13, column: 14, scope: !10)
-!12 = !MDLocation(line: 19, column: 3, scope: !13)
-!13 = !{!"0x2e\00main\00main\00\0016\000\001\000\000\00256\001\0016", !4, !5, !6, null, i32 ()* @main, null, null, !7} ; [ DW_TAG_subprogram ] [line 16] [def] [main]
-!14 = !MDLocation(line: 20, column: 5, scope: !13)
-!15 = !MDLocation(line: 21, column: 15, scope: !13)
-!16 = !MDLocation(line: 22, column: 11, scope: !13)
+!8 = !DILocation(line: 9, column: 14, scope: !3)
+!9 = !DILocation(line: 13, column: 3, scope: !10)
+!10 = !DISubprogram(name: "bar", line: 12, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 12, file: !4, scope: !5, type: !6, function: double (i32)* @_Z3bari, variables: !7)
+!11 = !DILocation(line: 13, column: 14, scope: !10)
+!12 = !DILocation(line: 19, column: 3, scope: !13)
+!13 = !DISubprogram(name: "main", line: 16, isLocal: false, isDefinition: true, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 16, file: !4, scope: !5, type: !6, function: i32 ()* @main, variables: !7)
+!14 = !DILocation(line: 20, column: 5, scope: !13)
+!15 = !DILocation(line: 21, column: 15, scope: !13)
+!16 = !DILocation(line: 22, column: 11, scope: !13)
 !17 = !{!"branch_weights", i32 534, i32 2064}
-!18 = !MDLocation(line: 23, column: 14, scope: !13)
-!19 = !MDLocation(line: 25, column: 14, scope: !13)
-!20 = !MDLocation(line: 20, column: 28, scope: !13)
+!18 = !DILocation(line: 23, column: 14, scope: !13)
+!19 = !DILocation(line: 25, column: 14, scope: !13)
+!20 = !DILocation(line: 20, column: 28, scope: !13)
 !21 = !{!"branch_weights", i32 0, i32 1075}
-!22 = !MDLocation(line: 19, column: 26, scope: !13)
+!22 = !DILocation(line: 19, column: 26, scope: !13)
 !23 = !{!"branch_weights", i32 0, i32 534}
-!24 = !MDLocation(line: 27, column: 3, scope: !13)
-!25 = !MDLocation(line: 28, column: 3, scope: !13)
+!24 = !DILocation(line: 27, column: 3, scope: !13)
+!25 = !DILocation(line: 28, column: 3, scope: !13)
diff --git a/test/Transforms/SampleProfile/propagate.ll b/test/Transforms/SampleProfile/propagate.ll
index 594645f7f2be..620d125875f7 100644
--- a/test/Transforms/SampleProfile/propagate.ll
+++ b/test/Transforms/SampleProfile/propagate.ll
@@ -51,14 +51,14 @@ entry:
   store i32 %x, i32* %x.addr, align 4
   store i32 %y, i32* %y.addr, align 4
   store i64 %N, i64* %N.addr, align 8
-  %0 = load i32* %x.addr, align 4, !dbg !11
-  %1 = load i32* %y.addr, align 4, !dbg !11
+  %0 = load i32, i32* %x.addr, align 4, !dbg !11
+  %1 = load i32, i32* %y.addr, align 4, !dbg !11
   %cmp = icmp slt i32 %0, %1, !dbg !11
   br i1 %cmp, label %if.then, label %if.else, !dbg !11
 
 if.then:                                          ; preds = %entry
-  %2 = load i32* %y.addr, align 4, !dbg !13
-  %3 = load i32* %x.addr, align 4, !dbg !13
+  %2 = load i32, i32* %y.addr, align 4, !dbg !13
+  %3 = load i32, i32* %x.addr, align 4, !dbg !13
   %sub = sub nsw i32 %2, %3, !dbg !13
   %conv = sext i32 %sub to i64, !dbg !13
   store i64 %conv, i64* %retval, !dbg !13
@@ -69,16 +69,16 @@ if.else:                                          ; preds = %entry
   br label %for.cond, !dbg !15
 
 for.cond:                                         ; preds = %for.inc16, %if.else
-  %4 = load i64* %i, align 8, !dbg !15
-  %5 = load i64* %N.addr, align 8, !dbg !15
+  %4 = load i64, i64* %i, align 8, !dbg !15
+  %5 = load i64, i64* %N.addr, align 8, !dbg !15
   %cmp1 = icmp slt i64 %4, %5, !dbg !15
   br i1 %cmp1, label %for.body, label %for.end18, !dbg !15
-; CHECK: edge for.cond -> for.body probability is 10 / 11 = 90.9091% [HOT edge]
-; CHECK: edge for.cond -> for.end18 probability is 1 / 11 = 9.09091%
+; CHECK: edge for.cond -> for.body probability is 10 / 10 = 100% [HOT edge]
+; CHECK: edge for.cond -> for.end18 probability is 0 / 10 = 0%
 
 for.body:                                         ; preds = %for.cond
-  %6 = load i64* %i, align 8, !dbg !18
-  %7 = load i64* %N.addr, align 8, !dbg !18
+  %6 = load i64, i64* %i, align 8, !dbg !18
+  %7 = load i64, i64* %N.addr, align 8, !dbg !18
   %div = sdiv i64 %7, 3, !dbg !18
   %cmp2 = icmp sgt i64 %6, %div, !dbg !18
   br i1 %cmp2, label %if.then3, label %if.end, !dbg !18
@@ -86,14 +86,14 @@ for.body:                                         ; preds = %for.cond
 ; CHECK: edge for.body -> if.end probability is 4 / 5 = 80%
 
 if.then3:                                         ; preds = %for.body
-  %8 = load i32* %x.addr, align 4, !dbg !21
+  %8 = load i32, i32* %x.addr, align 4, !dbg !21
   %dec = add nsw i32 %8, -1, !dbg !21
   store i32 %dec, i32* %x.addr, align 4, !dbg !21
   br label %if.end, !dbg !21
 
 if.end:                                           ; preds = %if.then3, %for.body
-  %9 = load i64* %i, align 8, !dbg !22
-  %10 = load i64* %N.addr, align 8, !dbg !22
+  %9 = load i64, i64* %i, align 8, !dbg !22
+  %10 = load i64, i64* %N.addr, align 8, !dbg !22
   %div4 = sdiv i64 %10, 4, !dbg !22
   %cmp5 = icmp sgt i64 %9, %div4, !dbg !22
   br i1 %cmp5, label %if.then6, label %if.else7, !dbg !22
@@ -101,10 +101,10 @@ if.end:                                           ; preds = %if.then3, %for.body
 ; CHECK: edge if.end -> if.else7 probability is 6339 / 6342 = 99.9527% [HOT edge]
 
 if.then6:                                         ; preds = %if.end
-  %11 = load i32* %y.addr, align 4, !dbg !24
+  %11 = load i32, i32* %y.addr, align 4, !dbg !24
   %inc = add nsw i32 %11, 1, !dbg !24
   store i32 %inc, i32* %y.addr, align 4, !dbg !24
-  %12 = load i32* %x.addr, align 4, !dbg !26
+  %12 = load i32, i32* %x.addr, align 4, !dbg !26
   %add = add nsw i32 %12, 3, !dbg !26
   store i32 %add, i32* %x.addr, align 4, !dbg !26
   br label %if.end15, !dbg !27
@@ -114,26 +114,26 @@ if.else7:                                         ; preds = %if.end
   br label %for.cond8, !dbg !28
 
 for.cond8:                                        ; preds = %for.inc, %if.else7
-  %13 = load i32* %j, align 4, !dbg !28
+  %13 = load i32, i32* %j, align 4, !dbg !28
   %conv9 = zext i32 %13 to i64, !dbg !28
-  %14 = load i64* %i, align 8, !dbg !28
+  %14 = load i64, i64* %i, align 8, !dbg !28
   %cmp10 = icmp slt i64 %conv9, %14, !dbg !28
   br i1 %cmp10, label %for.body11, label %for.end, !dbg !28
-; CHECK: edge for.cond8 -> for.body11 probability is 16191 / 16192 = 99.9938% [HOT edge]
-; CHECK: edge for.cond8 -> for.end probability is 1 / 16192 = 0.00617589%
+; CHECK: edge for.cond8 -> for.body11 probability is 16191 / 16191 = 100% [HOT edge]
+; CHECK: edge for.cond8 -> for.end probability is 0 / 16191 = 0%
 
 for.body11:                                       ; preds = %for.cond8
-  %15 = load i32* %j, align 4, !dbg !31
-  %16 = load i32* %x.addr, align 4, !dbg !31
+  %15 = load i32, i32* %j, align 4, !dbg !31
+  %16 = load i32, i32* %x.addr, align 4, !dbg !31
   %add12 = add i32 %16, %15, !dbg !31
   store i32 %add12, i32* %x.addr, align 4, !dbg !31
-  %17 = load i32* %y.addr, align 4, !dbg !33
+  %17 = load i32, i32* %y.addr, align 4, !dbg !33
   %sub13 = sub nsw i32 %17, 3, !dbg !33
   store i32 %sub13, i32* %y.addr, align 4, !dbg !33
   br label %for.inc, !dbg !34
 
 for.inc:                                          ; preds = %for.body11
-  %18 = load i32* %j, align 4, !dbg !28
+  %18 = load i32, i32* %j, align 4, !dbg !28
   %inc14 = add i32 %18, 1, !dbg !28
   store i32 %inc14, i32* %j, align 4, !dbg !28
   br label %for.cond8, !dbg !28
@@ -145,7 +145,7 @@ if.end15:                                         ; preds = %for.end, %if.then6
   br label %for.inc16, !dbg !35
 
 for.inc16:                                        ; preds = %if.end15
-  %19 = load i64* %i, align 8, !dbg !15
+  %19 = load i64, i64* %i, align 8, !dbg !15
   %inc17 = add nsw i64 %19, 1, !dbg !15
   store i64 %inc17, i64* %i, align 8, !dbg !15
   br label %for.cond, !dbg !15
@@ -154,15 +154,15 @@ for.end18:                                        ; preds = %for.cond
   br label %if.end19
 
 if.end19:                                         ; preds = %for.end18
-  %20 = load i32* %y.addr, align 4, !dbg !36
-  %21 = load i32* %x.addr, align 4, !dbg !36
+  %20 = load i32, i32* %y.addr, align 4, !dbg !36
+  %21 = load i32, i32* %x.addr, align 4, !dbg !36
   %mul = mul nsw i32 %20, %21, !dbg !36
   %conv20 = sext i32 %mul to i64, !dbg !36
   store i64 %conv20, i64* %retval, !dbg !36
   br label %return, !dbg !36
 
 return:                                           ; preds = %if.end19, %if.then
-  %22 = load i64* %retval, !dbg !37
+  %22 = load i64, i64* %retval, !dbg !37
   ret i64 %22, !dbg !37
 }
 
@@ -177,14 +177,14 @@ entry:
   store i32 5678, i32* %x, align 4, !dbg !38
   store i32 1234, i32* %y, align 4, !dbg !39
   store i64 999999, i64* %N, align 8, !dbg !40
-  %0 = load i32* %x, align 4, !dbg !41
-  %1 = load i32* %y, align 4, !dbg !41
-  %2 = load i64* %N, align 8, !dbg !41
-  %3 = load i32* %x, align 4, !dbg !41
-  %4 = load i32* %y, align 4, !dbg !41
-  %5 = load i64* %N, align 8, !dbg !41
+  %0 = load i32, i32* %x, align 4, !dbg !41
+  %1 = load i32, i32* %y, align 4, !dbg !41
+  %2 = load i64, i64* %N, align 8, !dbg !41
+  %3 = load i32, i32* %x, align 4, !dbg !41
+  %4 = load i32, i32* %y, align 4, !dbg !41
+  %5 = load i64, i64* %N, align 8, !dbg !41
   %call = call i64 @_Z3fooiil(i32 %3, i32 %4, i64 %5), !dbg !41
-  %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([24 x i8]* @.str, i32 0, i32 0), i32 %0, i32 %1, i64 %2, i64 %call), !dbg !41
+  %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str, i32 0, i32 0), i32 %0, i32 %1, i64 %2, i64 %call), !dbg !41
   ret i32 0, !dbg !42
 }
 
@@ -198,46 +198,46 @@ attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n
 !llvm.module.flags = !{!8, !9}
 !llvm.ident = !{!10}
 
-!0 = !{!"0x11\004\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [propagate.cc] [DW_LANG_C_plus_plus]
-!1 = !{!"propagate.cc", !"."}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "propagate.cc", directory: ".")
+!2 = !{}
 !3 = !{!4, !7}
-!4 = !{!"0x2e\00foo\00foo\00\003\000\001\000\006\00256\000\003", !1, !5, !6, null, i64 (i32, i32, i64)* @_Z3fooiil, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [foo]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [propagate.cc]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!7 = !{!"0x2e\00main\00main\00\0024\000\001\000\006\00256\000\0024", !1, !5, !6, null, i32 ()* @main, null, null, !2} ; [ DW_TAG_subprogram ] [line 24] [def] [main]
+!4 = !DISubprogram(name: "foo", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 3, file: !1, scope: !5, type: !6, function: i64 (i32, i32, i64)* @_Z3fooiil, variables: !2)
+!5 = !DIFile(filename: "propagate.cc", directory: ".")
+!6 = !DISubroutineType(types: !{null})
+!7 = !DISubprogram(name: "main", line: 24, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 24, file: !1, scope: !5, type: !6, function: i32 ()* @main, variables: !2)
 !8 = !{i32 2, !"Dwarf Version", i32 4}
-!9 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !{i32 1, !"Debug Info Version", i32 3}
 !10 = !{!"clang version 3.5 "}
-!11 = !MDLocation(line: 4, scope: !12)
-!12 = !{!"0xb\004\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [propagate.cc]
-!13 = !MDLocation(line: 5, scope: !14)
-!14 = !{!"0xb\004\000\000", !1, !12} ; [ DW_TAG_lexical_block ] [propagate.cc]
-!15 = !MDLocation(line: 7, scope: !16)
-!16 = !{!"0xb\007\000\000", !1, !17} ; [ DW_TAG_lexical_block ] [propagate.cc]
-!17 = !{!"0xb\006\000\000", !1, !12} ; [ DW_TAG_lexical_block ] [propagate.cc]
-!18 = !MDLocation(line: 8, scope: !19)
-!19 = !{!"0xb\008\000\000", !1, !20} ; [ DW_TAG_lexical_block ] [propagate.cc]
-!20 = !{!"0xb\007\000\000", !1, !16} ; [ DW_TAG_lexical_block ] [propagate.cc]
-!21 = !MDLocation(line: 9, scope: !19)
-!22 = !MDLocation(line: 10, scope: !23)
-!23 = !{!"0xb\0010\000\000", !1, !20} ; [ DW_TAG_lexical_block ] [propagate.cc]
-!24 = !MDLocation(line: 11, scope: !25)
-!25 = !{!"0xb\0010\000\000", !1, !23} ; [ DW_TAG_lexical_block ] [propagate.cc]
-!26 = !MDLocation(line: 12, scope: !25)
-!27 = !MDLocation(line: 13, scope: !25)
-!28 = !MDLocation(line: 14, scope: !29)
-!29 = !{!"0xb\0014\000\000", !1, !30} ; [ DW_TAG_lexical_block ] [propagate.cc]
-!30 = !{!"0xb\0013\000\000", !1, !23} ; [ DW_TAG_lexical_block ] [propagate.cc]
-!31 = !MDLocation(line: 15, scope: !32)
-!32 = !{!"0xb\0014\000\000", !1, !29} ; [ DW_TAG_lexical_block ] [propagate.cc]
-!33 = !MDLocation(line: 16, scope: !32)
-!34 = !MDLocation(line: 17, scope: !32)
-!35 = !MDLocation(line: 19, scope: !20)
-!36 = !MDLocation(line: 21, scope: !4)
-!37 = !MDLocation(line: 22, scope: !4)
-!38 = !MDLocation(line: 25, scope: !7)
-!39 = !MDLocation(line: 26, scope: !7)
-!40 = !MDLocation(line: 27, scope: !7)
-!41 = !MDLocation(line: 28, scope: !7)
-!42 = !MDLocation(line: 29, scope: !7)
+!11 = !DILocation(line: 4, scope: !12)
+!12 = distinct !DILexicalBlock(line: 4, column: 0, file: !1, scope: !4)
+!13 = !DILocation(line: 5, scope: !14)
+!14 = distinct !DILexicalBlock(line: 4, column: 0, file: !1, scope: !12)
+!15 = !DILocation(line: 7, scope: !16)
+!16 = distinct !DILexicalBlock(line: 7, column: 0, file: !1, scope: !17)
+!17 = distinct !DILexicalBlock(line: 6, column: 0, file: !1, scope: !12)
+!18 = !DILocation(line: 8, scope: !19)
+!19 = distinct !DILexicalBlock(line: 8, column: 0, file: !1, scope: !20)
+!20 = distinct !DILexicalBlock(line: 7, column: 0, file: !1, scope: !16)
+!21 = !DILocation(line: 9, scope: !19)
+!22 = !DILocation(line: 10, scope: !23)
+!23 = distinct !DILexicalBlock(line: 10, column: 0, file: !1, scope: !20)
+!24 = !DILocation(line: 11, scope: !25)
+!25 = distinct !DILexicalBlock(line: 10, column: 0, file: !1, scope: !23)
+!26 = !DILocation(line: 12, scope: !25)
+!27 = !DILocation(line: 13, scope: !25)
+!28 = !DILocation(line: 14, scope: !29)
+!29 = distinct !DILexicalBlock(line: 14, column: 0, file: !1, scope: !30)
+!30 = distinct !DILexicalBlock(line: 13, column: 0, file: !1, scope: !23)
+!31 = !DILocation(line: 15, scope: !32)
+!32 = distinct !DILexicalBlock(line: 14, column: 0, file: !1, scope: !29)
+!33 = !DILocation(line: 16, scope: !32)
+!34 = !DILocation(line: 17, scope: !32)
+!35 = !DILocation(line: 19, scope: !20)
+!36 = !DILocation(line: 21, scope: !4)
+!37 = !DILocation(line: 22, scope: !4)
+!38 = !DILocation(line: 25, scope: !7)
+!39 = !DILocation(line: 26, scope: !7)
+!40 = !DILocation(line: 27, scope: !7)
+!41 = !DILocation(line: 28, scope: !7)
+!42 = !DILocation(line: 29, scope: !7)
diff --git a/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll b/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll
index 7116199d021f..336c0a9dfa6b 100644
--- a/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll
+++ b/test/Transforms/ScalarRepl/2003-05-29-ArrayFail.ll
@@ -5,9 +5,9 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 
 define i32 @test() nounwind {
 	%X = alloca [4 x i32]		; <[4 x i32]*> [#uses=1]
-	%Y = getelementptr [4 x i32]* %X, i64 0, i64 0		; <i32*> [#uses=1]
+	%Y = getelementptr [4 x i32], [4 x i32]* %X, i64 0, i64 0		; <i32*> [#uses=1]
         ; Must preserve arrayness!
-	%Z = getelementptr i32* %Y, i64 1		; <i32*> [#uses=1]
-	%A = load i32* %Z		; <i32> [#uses=1]
+	%Z = getelementptr i32, i32* %Y, i64 1		; <i32*> [#uses=1]
+	%A = load i32, i32* %Z		; <i32> [#uses=1]
 	ret i32 %A
 }
diff --git a/test/Transforms/ScalarRepl/2003-09-12-IncorrectPromote.ll b/test/Transforms/ScalarRepl/2003-09-12-IncorrectPromote.ll
index 3f28cb187f86..c5ca428be4bc 100644
--- a/test/Transforms/ScalarRepl/2003-09-12-IncorrectPromote.ll
+++ b/test/Transforms/ScalarRepl/2003-09-12-IncorrectPromote.ll
@@ -4,8 +4,8 @@
 
 define i8* @test() {
 	%A = alloca [30 x i8]		; <[30 x i8]*> [#uses=1]
-	%B = getelementptr [30 x i8]* %A, i64 0, i64 0		; <i8*> [#uses=2]
-	%C = getelementptr i8* %B, i64 1		; <i8*> [#uses=1]
+	%B = getelementptr [30 x i8], [30 x i8]* %A, i64 0, i64 0		; <i8*> [#uses=2]
+	%C = getelementptr i8, i8* %B, i64 1		; <i8*> [#uses=1]
 	store i8 0, i8* %B
 	ret i8* %C
 }
diff --git a/test/Transforms/ScalarRepl/2003-10-29-ArrayProblem.ll b/test/Transforms/ScalarRepl/2003-10-29-ArrayProblem.ll
index 77c7b54b63ff..ce652737bc1e 100644
--- a/test/Transforms/ScalarRepl/2003-10-29-ArrayProblem.ll
+++ b/test/Transforms/ScalarRepl/2003-10-29-ArrayProblem.ll
@@ -7,9 +7,9 @@ declare void @.iter_2(i32 (i8*)*, i8*)
 
 define i32 @main() {
 	%d = alloca %T		; <{ [80 x i8], i32, i32 }*> [#uses=2]
-	%tmp.0 = getelementptr %T* %d, i64 0, i32 2		; <i32*> [#uses=1]
+	%tmp.0 = getelementptr %T, %T* %d, i64 0, i32 2		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp.0
-	%tmp.1 = getelementptr %T* %d, i64 0, i32 0, i64 0		; <i8*> [#uses=1]
+	%tmp.1 = getelementptr %T, %T* %d, i64 0, i32 0, i64 0		; <i8*> [#uses=1]
 	call void @.iter_2( i32 (i8*)* @.callback_1, i8* %tmp.1 )
 	ret i32 0
 }
diff --git a/test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll b/test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll
index 99c9fb9ef326..2701fdaea516 100644
--- a/test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll
+++ b/test/Transforms/ScalarRepl/2006-11-07-InvalidArrayPromote.ll
@@ -5,14 +5,14 @@ define i32 @func(<4 x float> %v0, <4 x float> %v1) nounwind {
 	%vsiidx = alloca [2 x <4 x i32>], align 16		; <[2 x <4 x i32>]*> [#uses=3]
 	%tmp = call <4 x i32> @llvm.x86.sse2.cvttps2dq( <4 x float> %v0 )		; <<4 x i32>> [#uses=2]
 	%tmp.upgrd.1 = bitcast <4 x i32> %tmp to <2 x i64>		; <<2 x i64>> [#uses=0]
-	%tmp.upgrd.2 = getelementptr [2 x <4 x i32>]* %vsiidx, i32 0, i32 0		; <<4 x i32>*> [#uses=1]
+	%tmp.upgrd.2 = getelementptr [2 x <4 x i32>], [2 x <4 x i32>]* %vsiidx, i32 0, i32 0		; <<4 x i32>*> [#uses=1]
 	store <4 x i32> %tmp, <4 x i32>* %tmp.upgrd.2
 	%tmp10 = call <4 x i32> @llvm.x86.sse2.cvttps2dq( <4 x float> %v1 )		; <<4 x i32>> [#uses=2]
 	%tmp10.upgrd.3 = bitcast <4 x i32> %tmp10 to <2 x i64>		; <<2 x i64>> [#uses=0]
-	%tmp14 = getelementptr [2 x <4 x i32>]* %vsiidx, i32 0, i32 1		; <<4 x i32>*> [#uses=1]
+	%tmp14 = getelementptr [2 x <4 x i32>], [2 x <4 x i32>]* %vsiidx, i32 0, i32 1		; <<4 x i32>*> [#uses=1]
 	store <4 x i32> %tmp10, <4 x i32>* %tmp14
-	%tmp15 = getelementptr [2 x <4 x i32>]* %vsiidx, i32 0, i32 0, i32 4		; <i32*> [#uses=1]
-	%tmp.upgrd.4 = load i32* %tmp15		; <i32> [#uses=1]
+	%tmp15 = getelementptr [2 x <4 x i32>], [2 x <4 x i32>]* %vsiidx, i32 0, i32 0, i32 4		; <i32*> [#uses=1]
+	%tmp.upgrd.4 = load i32, i32* %tmp15		; <i32> [#uses=1]
 	ret i32 %tmp.upgrd.4
 }
 
diff --git a/test/Transforms/ScalarRepl/2007-05-29-MemcpyPreserve.ll b/test/Transforms/ScalarRepl/2007-05-29-MemcpyPreserve.ll
index cf96c4cc205c..966b17939fec 100644
--- a/test/Transforms/ScalarRepl/2007-05-29-MemcpyPreserve.ll
+++ b/test/Transforms/ScalarRepl/2007-05-29-MemcpyPreserve.ll
@@ -11,12 +11,12 @@ target triple = "i686-apple-darwin8"
 define void @_Z4testP9UnionTypePS0_(%struct.UnionType* %p, %struct.UnionType** %pointerToUnion) {
 entry:
   %tmp = alloca %struct.UnionType, align 8
-  %tmp2 = getelementptr %struct.UnionType* %tmp, i32 0, i32 0, i32 0
-  %tmp13 = getelementptr %struct.UnionType* %p, i32 0, i32 0, i32 0
+  %tmp2 = getelementptr %struct.UnionType, %struct.UnionType* %tmp, i32 0, i32 0, i32 0
+  %tmp13 = getelementptr %struct.UnionType, %struct.UnionType* %p, i32 0, i32 0, i32 0
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp2, i8* %tmp13, i32 8, i32 0, i1 false)
-  %tmp5 = load %struct.UnionType** %pointerToUnion
-  %tmp56 = getelementptr %struct.UnionType* %tmp5, i32 0, i32 0, i32 0
-  %tmp7 = getelementptr %struct.UnionType* %tmp, i32 0, i32 0, i32 0
+  %tmp5 = load %struct.UnionType*, %struct.UnionType** %pointerToUnion
+  %tmp56 = getelementptr %struct.UnionType, %struct.UnionType* %tmp5, i32 0, i32 0, i32 0
+  %tmp7 = getelementptr %struct.UnionType, %struct.UnionType* %tmp, i32 0, i32 0, i32 0
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp56, i8* %tmp7, i32 8, i32 0, i1 false)
   ret void
 }
diff --git a/test/Transforms/ScalarRepl/2007-11-03-bigendian_apint.ll b/test/Transforms/ScalarRepl/2007-11-03-bigendian_apint.ll
index 48abffe5f571..28f503a210ca 100644
--- a/test/Transforms/ScalarRepl/2007-11-03-bigendian_apint.ll
+++ b/test/Transforms/ScalarRepl/2007-11-03-bigendian_apint.ll
@@ -1,5 +1,11 @@
 ; RUN: opt < %s -scalarrepl -S | not grep shr
 
+; FIXME: I think this test is no longer valid.
+; It was working because SROA was aborting when
+; no datalayout was supplied
+; XFAIL: *
+
+
 %struct.S = type { i16 }
 
 define zeroext i1 @f(i16 signext  %b)   {
@@ -10,21 +16,21 @@ entry:
 	%tmp = alloca i32		; <i32*> [#uses=2]
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	store i16 %b, i16* %b_addr
-	%tmp1 = getelementptr %struct.S* %s, i32 0, i32 0		; <i16*> [#uses=1]
-	%tmp2 = load i16* %b_addr, align 2		; <i16> [#uses=1]
+	%tmp1 = getelementptr %struct.S, %struct.S* %s, i32 0, i32 0		; <i16*> [#uses=1]
+	%tmp2 = load i16, i16* %b_addr, align 2		; <i16> [#uses=1]
 	store i16 %tmp2, i16* %tmp1, align 2
-	%tmp3 = getelementptr %struct.S* %s, i32 0, i32 0		; <i16*> [#uses=1]
+	%tmp3 = getelementptr %struct.S, %struct.S* %s, i32 0, i32 0		; <i16*> [#uses=1]
 	%tmp34 = bitcast i16* %tmp3 to [2 x i1]*		; <[2 x i1]*> [#uses=1]
-	%tmp5 = getelementptr [2 x i1]* %tmp34, i32 0, i32 1		; <i1*> [#uses=1]
-	%tmp6 = load i1* %tmp5, align 1		; <i1> [#uses=1]
+	%tmp5 = getelementptr [2 x i1], [2 x i1]* %tmp34, i32 0, i32 1		; <i1*> [#uses=1]
+	%tmp6 = load i1, i1* %tmp5, align 1		; <i1> [#uses=1]
 	%tmp67 = zext i1 %tmp6 to i32		; <i32> [#uses=1]
 	store i32 %tmp67, i32* %tmp, align 4
-	%tmp8 = load i32* %tmp, align 4		; <i32> [#uses=1]
+	%tmp8 = load i32, i32* %tmp, align 4		; <i32> [#uses=1]
 	store i32 %tmp8, i32* %retval, align 4
 	br label %return
 
 return:		; preds = %entry
-	%retval9 = load i32* %retval		; <i32> [#uses=1]
+	%retval9 = load i32, i32* %retval		; <i32> [#uses=1]
 	%retval910 = trunc i32 %retval9 to i1		; <i1> [#uses=1]
 	ret i1 %retval910
 }
diff --git a/test/Transforms/ScalarRepl/2008-01-29-PromoteBug.ll b/test/Transforms/ScalarRepl/2008-01-29-PromoteBug.ll
index a53f3deadc72..99366b36442b 100644
--- a/test/Transforms/ScalarRepl/2008-01-29-PromoteBug.ll
+++ b/test/Transforms/ScalarRepl/2008-01-29-PromoteBug.ll
@@ -10,10 +10,10 @@ entry:
 	%T3 = bitcast [1 x %struct.T]* %s to i32*
 	store i32 -61184, i32* %T3
 
-	%tmp16 = getelementptr [1 x %struct.T]* %s, i32 0, i32 0		; <%struct.T*> [#uses=1]
-	%tmp17 = getelementptr %struct.T* %tmp16, i32 0, i32 1		; <[3 x i8]*> [#uses=1]
+	%tmp16 = getelementptr [1 x %struct.T], [1 x %struct.T]* %s, i32 0, i32 0		; <%struct.T*> [#uses=1]
+	%tmp17 = getelementptr %struct.T, %struct.T* %tmp16, i32 0, i32 1		; <[3 x i8]*> [#uses=1]
 	%tmp1718 = bitcast [3 x i8]* %tmp17 to i32*		; <i32*> [#uses=1]
-	%tmp19 = load i32* %tmp1718, align 4		; <i32> [#uses=1]
+	%tmp19 = load i32, i32* %tmp1718, align 4		; <i32> [#uses=1]
 	%mask = and i32 %tmp19, 16777215		; <i32> [#uses=2]
 	%mask2324 = trunc i32 %mask to i8		; <i8> [#uses=1]
 	ret i8 %mask2324
diff --git a/test/Transforms/ScalarRepl/2008-02-28-SubElementExtractCrash.ll b/test/Transforms/ScalarRepl/2008-02-28-SubElementExtractCrash.ll
index 7f8ef8310522..f37b6529a546 100644
--- a/test/Transforms/ScalarRepl/2008-02-28-SubElementExtractCrash.ll
+++ b/test/Transforms/ScalarRepl/2008-02-28-SubElementExtractCrash.ll
@@ -6,11 +6,11 @@ target triple = "i686-apple-darwin8"
 define i32 @main(i32 %argc, i8** %argv) {
 entry:
 	%c = alloca %struct..0anon		; <%struct..0anon*> [#uses=2]
-	%tmp2 = getelementptr %struct..0anon* %c, i32 0, i32 0		; <<1 x i64>*> [#uses=1]
+	%tmp2 = getelementptr %struct..0anon, %struct..0anon* %c, i32 0, i32 0		; <<1 x i64>*> [#uses=1]
 	store <1 x i64> zeroinitializer, <1 x i64>* %tmp2, align 8
-	%tmp7 = getelementptr %struct..0anon* %c, i32 0, i32 0		; <<1 x i64>*> [#uses=1]
+	%tmp7 = getelementptr %struct..0anon, %struct..0anon* %c, i32 0, i32 0		; <<1 x i64>*> [#uses=1]
 	%tmp78 = bitcast <1 x i64>* %tmp7 to [2 x i32]*		; <[2 x i32]*> [#uses=1]
-	%tmp9 = getelementptr [2 x i32]* %tmp78, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp10 = load i32* %tmp9, align 4		; <i32> [#uses=0]
+	%tmp9 = getelementptr [2 x i32], [2 x i32]* %tmp78, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp10 = load i32, i32* %tmp9, align 4		; <i32> [#uses=0]
 	unreachable
 }
diff --git a/test/Transforms/ScalarRepl/2008-06-05-loadstore-agg.ll b/test/Transforms/ScalarRepl/2008-06-05-loadstore-agg.ll
index ce70a1b13b81..d1f331211745 100644
--- a/test/Transforms/ScalarRepl/2008-06-05-loadstore-agg.ll
+++ b/test/Transforms/ScalarRepl/2008-06-05-loadstore-agg.ll
@@ -14,8 +14,8 @@ define i32 @foo() {
         ; And store it
 	store { i32, i32 } %res2, { i32, i32 }* %target
         ; Actually use %target, so it doesn't get removed altogether
-        %ptr = getelementptr { i32, i32 }* %target, i32 0, i32 0
-        %val = load i32* %ptr
+        %ptr = getelementptr { i32, i32 }, { i32, i32 }* %target, i32 0, i32 0
+        %val = load i32, i32* %ptr
 	ret i32 %val
 }
 
@@ -27,7 +27,7 @@ define i32 @bar() {
         ; And store it
 	store [ 2 x i32 ] %res2, [ 2 x i32 ]* %target
         ; Actually use %target, so it doesn't get removed altogether
-        %ptr = getelementptr [ 2 x i32 ]* %target, i32 0, i32 0
-        %val = load i32* %ptr
+        %ptr = getelementptr [ 2 x i32 ], [ 2 x i32 ]* %target, i32 0, i32 0
+        %val = load i32, i32* %ptr
 	ret i32 %val
 }
diff --git a/test/Transforms/ScalarRepl/2008-08-22-out-of-range-array-promote.ll b/test/Transforms/ScalarRepl/2008-08-22-out-of-range-array-promote.ll
index b2a9d43b2277..c0ff25f3541c 100644
--- a/test/Transforms/ScalarRepl/2008-08-22-out-of-range-array-promote.ll
+++ b/test/Transforms/ScalarRepl/2008-08-22-out-of-range-array-promote.ll
@@ -13,8 +13,8 @@ entry:
   %r1 = bitcast %struct.x* %r to i8*
   %s2 = bitcast %struct.x* %s to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %r1, i8* %s2, i32 12, i32 8, i1 false)
-  %1 = getelementptr %struct.x* %r, i32 0, i32 0, i32 1
-  %2 = load i32* %1, align 4
+  %1 = getelementptr %struct.x, %struct.x* %r, i32 0, i32 0, i32 1
+  %2 = load i32, i32* %1, align 4
   ret i32 %2
 }
 
diff --git a/test/Transforms/ScalarRepl/2008-09-22-vector-gep.ll b/test/Transforms/ScalarRepl/2008-09-22-vector-gep.ll
index 7554b7f2b0b8..16d9108bb24c 100644
--- a/test/Transforms/ScalarRepl/2008-09-22-vector-gep.ll
+++ b/test/Transforms/ScalarRepl/2008-09-22-vector-gep.ll
@@ -12,11 +12,11 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 define void @main(%struct.two* %D, i16 %V) {
 entry:
 	%S = alloca %struct.two
-        %S.2 = getelementptr %struct.two* %S, i32 0, i32 1
+        %S.2 = getelementptr %struct.two, %struct.two* %S, i32 0, i32 1
         store i16 %V, i16* %S.2
         ; This gep is effectively a bitcast to i8*, but is sometimes generated
         ; because the type of the first element in %struct.two is i8.
-	%tmpS = getelementptr %struct.two* %S, i32 0, i32 0, i32 0 
+	%tmpS = getelementptr %struct.two, %struct.two* %S, i32 0, i32 0, i32 0 
 	%tmpD = bitcast %struct.two* %D to i8*
         call void @llvm.memmove.p0i8.p0i8.i32(i8* %tmpD, i8* %tmpS, i32 4, i32 1, i1 false)
         ret void
diff --git a/test/Transforms/ScalarRepl/2009-02-02-ScalarPromoteOutOfRange.ll b/test/Transforms/ScalarRepl/2009-02-02-ScalarPromoteOutOfRange.ll
index 3c8a364edcdc..f0af1caa4610 100644
--- a/test/Transforms/ScalarRepl/2009-02-02-ScalarPromoteOutOfRange.ll
+++ b/test/Transforms/ScalarRepl/2009-02-02-ScalarPromoteOutOfRange.ll
@@ -6,11 +6,11 @@ target triple = "i386-pc-linux-gnu"
 
 define i32 @f(i32 %x, i32 %y) {
        %instance = alloca %pair
-       %first = getelementptr %pair* %instance, i32 0, i32 0
+       %first = getelementptr %pair, %pair* %instance, i32 0, i32 0
        %cast = bitcast [1 x i32]* %first to i32*
        store i32 %x, i32* %cast
-       %second = getelementptr %pair* %instance, i32 0, i32 1
+       %second = getelementptr %pair, %pair* %instance, i32 0, i32 1
        store i32 %y, i32* %second
-       %v = load i32* %cast
+       %v = load i32, i32* %cast
        ret i32 %v
 }
diff --git a/test/Transforms/ScalarRepl/2009-02-05-LoadFCA.ll b/test/Transforms/ScalarRepl/2009-02-05-LoadFCA.ll
index 67228a7a3cec..56375ffe7933 100644
--- a/test/Transforms/ScalarRepl/2009-02-05-LoadFCA.ll
+++ b/test/Transforms/ScalarRepl/2009-02-05-LoadFCA.ll
@@ -9,7 +9,7 @@ entry:
 	%tmp = alloca { i64, i64 }, align 8		; <{ i64, i64 }*> [#uses=2]
 	store { i64, i64 } %0, { i64, i64 }* %tmp
 	%1 = bitcast { i64, i64 }* %tmp to %struct.anon*		; <%struct.anon*> [#uses=1]
-	%2 = load %struct.anon* %1, align 8		; <%struct.anon> [#uses=1]
+	%2 = load %struct.anon, %struct.anon* %1, align 8		; <%struct.anon> [#uses=1]
         %tmp3 = extractvalue %struct.anon %2, 0
 	ret i32 %tmp3
 }
diff --git a/test/Transforms/ScalarRepl/2009-03-04-MemCpyAlign.ll b/test/Transforms/ScalarRepl/2009-03-04-MemCpyAlign.ll
index a4182d4c1d7c..025578c7f44d 100644
--- a/test/Transforms/ScalarRepl/2009-03-04-MemCpyAlign.ll
+++ b/test/Transforms/ScalarRepl/2009-03-04-MemCpyAlign.ll
@@ -9,7 +9,7 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 define void @f(i8* %p) nounwind {
 entry:
         %s = alloca %struct.st, align 4  ; <%struct.st*> [#uses=2]
-        %0 = getelementptr %struct.st* %s, i32 0, i32 0  ; <i16*> [#uses=1]
+        %0 = getelementptr %struct.st, %struct.st* %s, i32 0, i32 0  ; <i16*> [#uses=1]
         store i16 1, i16* %0, align 4
         %s1 = bitcast %struct.st* %s to i8*  ; <i8*> [#uses=1]
         call void @llvm.memcpy.p0i8.p0i8.i32(i8* %p, i8* %s1, i32 2, i32 1, i1 false)
diff --git a/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll b/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll
index 1f921914fcb0..d1cc4244ccfc 100644
--- a/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll
+++ b/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll
@@ -25,37 +25,37 @@ entry:
   %tmp2 = alloca %struct.int16x8x2_t
   %0 = alloca %struct.int16x8x2_t
   %"alloca point" = bitcast i32 0 to i32
-  %1 = getelementptr inbounds %struct.int16x8_t* %tmp_addr, i32 0, i32 0
+  %1 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %tmp_addr, i32 0, i32 0
   store <8 x i16> %tmp.0, <8 x i16>* %1
   store %struct.int16x8x2_t* %dst, %struct.int16x8x2_t** %dst_addr
-  %2 = getelementptr inbounds %struct.int16x8_t* %__ax, i32 0, i32 0
-  %3 = getelementptr inbounds %struct.int16x8_t* %tmp_addr, i32 0, i32 0
-  %4 = load <8 x i16>* %3, align 16
+  %2 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %__ax, i32 0, i32 0
+  %3 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %tmp_addr, i32 0, i32 0
+  %4 = load <8 x i16>, <8 x i16>* %3, align 16
   store <8 x i16> %4, <8 x i16>* %2, align 16
-  %5 = getelementptr inbounds %struct.int16x8_t* %__bx, i32 0, i32 0
-  %6 = getelementptr inbounds %struct.int16x8_t* %tmp_addr, i32 0, i32 0
-  %7 = load <8 x i16>* %6, align 16
+  %5 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %__bx, i32 0, i32 0
+  %6 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %tmp_addr, i32 0, i32 0
+  %7 = load <8 x i16>, <8 x i16>* %6, align 16
   store <8 x i16> %7, <8 x i16>* %5, align 16
-  %8 = getelementptr inbounds %struct.int16x8_t* %__ax, i32 0, i32 0
-  %9 = load <8 x i16>* %8, align 16
-  %10 = getelementptr inbounds %struct.int16x8_t* %__bx, i32 0, i32 0
-  %11 = load <8 x i16>* %10, align 16
-  %12 = getelementptr inbounds %union..0anon* %__rv, i32 0, i32 0
+  %8 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %__ax, i32 0, i32 0
+  %9 = load <8 x i16>, <8 x i16>* %8, align 16
+  %10 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %__bx, i32 0, i32 0
+  %11 = load <8 x i16>, <8 x i16>* %10, align 16
+  %12 = getelementptr inbounds %union..0anon, %union..0anon* %__rv, i32 0, i32 0
   %13 = bitcast %struct.int16x8x2_t* %12 to %struct.__neon_int16x8x2_t*
   %14 = shufflevector <8 x i16> %9, <8 x i16> %11, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
-  %15 = getelementptr inbounds %struct.__neon_int16x8x2_t* %13, i32 0, i32 0
+  %15 = getelementptr inbounds %struct.__neon_int16x8x2_t, %struct.__neon_int16x8x2_t* %13, i32 0, i32 0
   store <8 x i16> %14, <8 x i16>* %15
   %16 = shufflevector <8 x i16> %9, <8 x i16> %11, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
-  %17 = getelementptr inbounds %struct.__neon_int16x8x2_t* %13, i32 0, i32 1
+  %17 = getelementptr inbounds %struct.__neon_int16x8x2_t, %struct.__neon_int16x8x2_t* %13, i32 0, i32 1
   store <8 x i16> %16, <8 x i16>* %17
-  %18 = getelementptr inbounds %union..0anon* %__rv, i32 0, i32 0
+  %18 = getelementptr inbounds %union..0anon, %union..0anon* %__rv, i32 0, i32 0
   %19 = bitcast %struct.int16x8x2_t* %0 to i8*
   %20 = bitcast %struct.int16x8x2_t* %18 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %19, i8* %20, i32 32, i32 16, i1 false)
   %tmp21 = bitcast %struct.int16x8x2_t* %tmp2 to i8*
   %21 = bitcast %struct.int16x8x2_t* %0 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp21, i8* %21, i32 32, i32 16, i1 false)
-  %22 = load %struct.int16x8x2_t** %dst_addr, align 4
+  %22 = load %struct.int16x8x2_t*, %struct.int16x8x2_t** %dst_addr, align 4
   %23 = bitcast %struct.int16x8x2_t* %22 to i8*
   %tmp22 = bitcast %struct.int16x8x2_t* %tmp2 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %23, i8* %tmp22, i32 32, i32 16, i1 false)
diff --git a/test/Transforms/ScalarRepl/2011-05-06-CapturedAlloca.ll b/test/Transforms/ScalarRepl/2011-05-06-CapturedAlloca.ll
index 816cb60e82a4..997d03b059e9 100644
--- a/test/Transforms/ScalarRepl/2011-05-06-CapturedAlloca.ll
+++ b/test/Transforms/ScalarRepl/2011-05-06-CapturedAlloca.ll
@@ -17,7 +17,7 @@ entry:
   %tmp = bitcast [4 x i32]* %l_10 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp, i8* bitcast ([4 x i32]* @func_1.l_10 to i8*), i64 16, i32 16, i1 false)
 ; CHECK: call void @llvm.memcpy
-  %arrayidx = getelementptr inbounds [4 x i32]* %l_10, i64 0, i64 0
+  %arrayidx = getelementptr inbounds [4 x i32], [4 x i32]* %l_10, i64 0, i64 0
   %call = call i32* @noop(i32* %arrayidx)
   store i32 0, i32* %call
   ret i32 0
diff --git a/test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll b/test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll
index 459688547fb4..dee27f8e3068 100644
--- a/test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll
+++ b/test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll
@@ -16,12 +16,12 @@ define void @main() uwtable ssp {
 entry:
   %ref.tmp2 = alloca %0, align 16
   %tmpcast = bitcast %0* %ref.tmp2 to %struct.Point_3*
-  %0 = getelementptr %0* %ref.tmp2, i64 0, i32 0
+  %0 = getelementptr %0, %0* %ref.tmp2, i64 0, i32 0
   store <2 x float> zeroinitializer, <2 x float>* %0, align 16
-  %1 = getelementptr inbounds %struct.Point_3* %tmpcast, i64 0, i32 0
-  %base.i.i.i = getelementptr inbounds %struct.PointC3* %1, i64 0, i32 0
-  %arrayidx.i.i.i.i = getelementptr inbounds %struct.array* %base.i.i.i, i64 0, i32 0, i64 0
-  %tmp5.i.i = load float* %arrayidx.i.i.i.i, align 4
+  %1 = getelementptr inbounds %struct.Point_3, %struct.Point_3* %tmpcast, i64 0, i32 0
+  %base.i.i.i = getelementptr inbounds %struct.PointC3, %struct.PointC3* %1, i64 0, i32 0
+  %arrayidx.i.i.i.i = getelementptr inbounds %struct.array, %struct.array* %base.i.i.i, i64 0, i32 0, i64 0
+  %tmp5.i.i = load float, float* %arrayidx.i.i.i.i, align 4
   ret void
 }
 
@@ -33,9 +33,9 @@ define void @test1() uwtable ssp {
 entry:
   %ref.tmp2 = alloca {<2 x float>, float}, align 16
   %tmpcast = bitcast {<2 x float>, float}* %ref.tmp2 to float*
-  %0 = getelementptr {<2 x float>, float}* %ref.tmp2, i64 0, i32 0
+  %0 = getelementptr {<2 x float>, float}, {<2 x float>, float}* %ref.tmp2, i64 0, i32 0
   store <2 x float> zeroinitializer, <2 x float>* %0, align 16
-  %tmp5.i.i = load float* %tmpcast, align 4
+  %tmp5.i.i = load float, float* %tmpcast, align 4
   ret void
 }
 
@@ -50,12 +50,12 @@ define float @test2() uwtable ssp {
 entry:
   %ref.tmp2 = alloca {<2 x float>, float}, align 16
   %tmpcast = bitcast {<2 x float>, float}* %ref.tmp2 to float*
-  %tmpcast2 = getelementptr {<2 x float>, float}* %ref.tmp2, i64 0, i32 1
-  %0 = getelementptr {<2 x float>, float}* %ref.tmp2, i64 0, i32 0
+  %tmpcast2 = getelementptr {<2 x float>, float}, {<2 x float>, float}* %ref.tmp2, i64 0, i32 1
+  %0 = getelementptr {<2 x float>, float}, {<2 x float>, float}* %ref.tmp2, i64 0, i32 0
   store <2 x float> zeroinitializer, <2 x float>* %0, align 16
   store float 1.0, float* %tmpcast2, align 4
-  %r1 = load float* %tmpcast, align 4
-  %r2 = load float* %tmpcast2, align 4
+  %r1 = load float, float* %tmpcast, align 4
+  %r2 = load float, float* %tmpcast2, align 4
   %r = fadd float %r1, %r2
   ret float %r
 }
@@ -69,7 +69,7 @@ entry:
   %ai = alloca { <2 x float>, <2 x float> }, align 8
   store { <2 x float>, <2 x float> } {<2 x float> <float 0.0, float 1.0>, <2 x float> <float 2.0, float 3.0>}, { <2 x float>, <2 x float> }* %ai, align 8
   %tmpcast = bitcast { <2 x float>, <2 x float> }* %ai to [4 x float]*
-  %arrayidx = getelementptr inbounds [4 x float]* %tmpcast, i64 0, i64 3
-  %f = load float* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds [4 x float], [4 x float]* %tmpcast, i64 0, i64 3
+  %f = load float, float* %arrayidx, align 4
   ret float %f
 }
diff --git a/test/Transforms/ScalarRepl/2011-06-17-VectorPartialMemset.ll b/test/Transforms/ScalarRepl/2011-06-17-VectorPartialMemset.ll
index f8530d68a8fb..af6d1f36faea 100644
--- a/test/Transforms/ScalarRepl/2011-06-17-VectorPartialMemset.ll
+++ b/test/Transforms/ScalarRepl/2011-06-17-VectorPartialMemset.ll
@@ -14,7 +14,7 @@ entry:
   %a = alloca <4 x float>, align 16
   %p = bitcast <4 x float>* %a to i8*
   call void @llvm.memset.p0i8.i32(i8* %p, i8 0, i32 3, i32 16, i1 false)
-  %vec = load <4 x float>* %a, align 8
+  %vec = load <4 x float>, <4 x float>* %a, align 8
   %val = extractelement <4 x float> %vec, i32 0
   ret float %val
 }
@@ -29,7 +29,7 @@ entry:
   %p = bitcast { <4 x float> }* %a to i8*
   call void @llvm.memset.p0i8.i32(i8* %p, i8 0, i32 16, i32 16, i1 false)
   %q = bitcast { <4 x float> }* %a to [2 x <2 x float>]*
-  %arrayidx = getelementptr inbounds [2 x <2 x float>]* %q, i32 0, i32 0
+  %arrayidx = getelementptr inbounds [2 x <2 x float>], [2 x <2 x float>]* %q, i32 0, i32 0
   store <2 x float> undef, <2 x float>* %arrayidx, align 8
   ret void
 }
diff --git a/test/Transforms/ScalarRepl/2011-09-22-PHISpeculateInvoke.ll b/test/Transforms/ScalarRepl/2011-09-22-PHISpeculateInvoke.ll
index 5f4d0fc7e1c8..9a24662f4114 100644
--- a/test/Transforms/ScalarRepl/2011-09-22-PHISpeculateInvoke.ll
+++ b/test/Transforms/ScalarRepl/2011-09-22-PHISpeculateInvoke.ll
@@ -25,7 +25,7 @@ else:                                             ; preds = %2
 
 join:                                             ; preds = %then, %else
   %storemerge.in = phi i32* [ %retptr2, %else ], [ %retptr1, %then ]
-  %storemerge = load i32* %storemerge.in
+  %storemerge = load i32, i32* %storemerge.in
   %x3 = call i32 @extern_fn2(i32 %storemerge)
   ret void
 
diff --git a/test/Transforms/ScalarRepl/2011-10-22-VectorCrash.ll b/test/Transforms/ScalarRepl/2011-10-22-VectorCrash.ll
index e4456361a66d..c9c1a148a484 100644
--- a/test/Transforms/ScalarRepl/2011-10-22-VectorCrash.ll
+++ b/test/Transforms/ScalarRepl/2011-10-22-VectorCrash.ll
@@ -11,7 +11,7 @@ define void @test() nounwind {
 entry:
   %u = alloca %union.anon, align 16
   %u164 = bitcast %union.anon* %u to [4 x i32]*
-  %arrayidx165 = getelementptr inbounds [4 x i32]* %u164, i32 0, i32 0
+  %arrayidx165 = getelementptr inbounds [4 x i32], [4 x i32]* %u164, i32 0, i32 0
   store i32 undef, i32* %arrayidx165, align 4
   %v186 = bitcast %union.anon* %u to <4 x float>*
   store <4 x float> undef, <4 x float>* %v186, align 16
diff --git a/test/Transforms/ScalarRepl/2011-11-11-EmptyStruct.ll b/test/Transforms/ScalarRepl/2011-11-11-EmptyStruct.ll
index da707b706d6d..51d1d146a90b 100644
--- a/test/Transforms/ScalarRepl/2011-11-11-EmptyStruct.ll
+++ b/test/Transforms/ScalarRepl/2011-11-11-EmptyStruct.ll
@@ -13,13 +13,13 @@ define double @test() nounwind uwtable ssp {
 entry:
   %retval = alloca %struct.S, align 8
   %ret = alloca %struct.S, align 8
-  %b = getelementptr inbounds %struct.S* %ret, i32 0, i32 1
+  %b = getelementptr inbounds %struct.S, %struct.S* %ret, i32 0, i32 1
   store double 1.000000e+00, double* %b, align 8
   %0 = bitcast %struct.S* %retval to i8*
   %1 = bitcast %struct.S* %ret to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 8, i32 8, i1 false)
   %2 = bitcast %struct.S* %retval to double*
-  %3 = load double* %2, align 1
+  %3 = load double, double* %2, align 1
   ret double %3
 }
 
diff --git a/test/Transforms/ScalarRepl/AggregatePromote.ll b/test/Transforms/ScalarRepl/AggregatePromote.ll
index 16b327356bbd..f6dfdf55346a 100644
--- a/test/Transforms/ScalarRepl/AggregatePromote.ll
+++ b/test/Transforms/ScalarRepl/AggregatePromote.ll
@@ -10,7 +10,7 @@ define i64 @test1(i64 %X) {
 	%B = bitcast i64* %A to i32*		; <i32*> [#uses=1]
 	%C = bitcast i32* %B to i8*		; <i8*> [#uses=1]
 	store i8 0, i8* %C
-	%Y = load i64* %A		; <i64> [#uses=1]
+	%Y = load i64, i64* %A		; <i64> [#uses=1]
 	ret i64 %Y
 }
 
@@ -18,22 +18,22 @@ define i8 @test2(i64 %X) {
 	%X_addr = alloca i64		; <i64*> [#uses=2]
 	store i64 %X, i64* %X_addr
 	%tmp.0 = bitcast i64* %X_addr to i32*		; <i32*> [#uses=1]
-	%tmp.1 = getelementptr i32* %tmp.0, i32 1		; <i32*> [#uses=1]
+	%tmp.1 = getelementptr i32, i32* %tmp.0, i32 1		; <i32*> [#uses=1]
 	%tmp.2 = bitcast i32* %tmp.1 to i8*		; <i8*> [#uses=1]
-	%tmp.3 = getelementptr i8* %tmp.2, i32 3		; <i8*> [#uses=1]
-	%tmp.2.upgrd.1 = load i8* %tmp.3		; <i8> [#uses=1]
+	%tmp.3 = getelementptr i8, i8* %tmp.2, i32 3		; <i8*> [#uses=1]
+	%tmp.2.upgrd.1 = load i8, i8* %tmp.3		; <i8> [#uses=1]
 	ret i8 %tmp.2.upgrd.1
 }
 
 define i16 @crafty(i64 %X) {
 	%a = alloca { i64 }		; <{ i64 }*> [#uses=2]
-	%tmp.0 = getelementptr { i64 }* %a, i32 0, i32 0		; <i64*> [#uses=1]
+	%tmp.0 = getelementptr { i64 }, { i64 }* %a, i32 0, i32 0		; <i64*> [#uses=1]
 	store i64 %X, i64* %tmp.0
 	%tmp.3 = bitcast { i64 }* %a to [4 x i16]*		; <[4 x i16]*> [#uses=2]
-	%tmp.4 = getelementptr [4 x i16]* %tmp.3, i32 0, i32 3		; <i16*> [#uses=1]
-	%tmp.5 = load i16* %tmp.4		; <i16> [#uses=1]
-	%tmp.8 = getelementptr [4 x i16]* %tmp.3, i32 0, i32 2		; <i16*> [#uses=1]
-	%tmp.9 = load i16* %tmp.8		; <i16> [#uses=1]
+	%tmp.4 = getelementptr [4 x i16], [4 x i16]* %tmp.3, i32 0, i32 3		; <i16*> [#uses=1]
+	%tmp.5 = load i16, i16* %tmp.4		; <i16> [#uses=1]
+	%tmp.8 = getelementptr [4 x i16], [4 x i16]* %tmp.3, i32 0, i32 2		; <i16*> [#uses=1]
+	%tmp.9 = load i16, i16* %tmp.8		; <i16> [#uses=1]
 	%tmp.10 = or i16 %tmp.9, %tmp.5		; <i16> [#uses=1]
 	ret i16 %tmp.10
 }
@@ -42,10 +42,10 @@ define i16 @crafty2(i64 %X) {
 	%a = alloca i64		; <i64*> [#uses=2]
 	store i64 %X, i64* %a
 	%tmp.3 = bitcast i64* %a to [4 x i16]*		; <[4 x i16]*> [#uses=2]
-	%tmp.4 = getelementptr [4 x i16]* %tmp.3, i32 0, i32 3		; <i16*> [#uses=1]
-	%tmp.5 = load i16* %tmp.4		; <i16> [#uses=1]
-	%tmp.8 = getelementptr [4 x i16]* %tmp.3, i32 0, i32 2		; <i16*> [#uses=1]
-	%tmp.9 = load i16* %tmp.8		; <i16> [#uses=1]
+	%tmp.4 = getelementptr [4 x i16], [4 x i16]* %tmp.3, i32 0, i32 3		; <i16*> [#uses=1]
+	%tmp.5 = load i16, i16* %tmp.4		; <i16> [#uses=1]
+	%tmp.8 = getelementptr [4 x i16], [4 x i16]* %tmp.3, i32 0, i32 2		; <i16*> [#uses=1]
+	%tmp.9 = load i16, i16* %tmp.8		; <i16> [#uses=1]
 	%tmp.10 = or i16 %tmp.9, %tmp.5		; <i16> [#uses=1]
 	ret i16 %tmp.10
 }
diff --git a/test/Transforms/ScalarRepl/DifferingTypes.ll b/test/Transforms/ScalarRepl/DifferingTypes.ll
index 933c47f79874..3860f6cd757f 100644
--- a/test/Transforms/ScalarRepl/DifferingTypes.ll
+++ b/test/Transforms/ScalarRepl/DifferingTypes.ll
@@ -10,7 +10,7 @@ define i32 @testfunc(i32 %i, i8 %j) {
 	store i32 %i, i32* %I
 	%P = bitcast i32* %I to i8*		; <i8*> [#uses=1]
 	store i8 %j, i8* %P
-	%t = load i32* %I		; <i32> [#uses=1]
+	%t = load i32, i32* %I		; <i32> [#uses=1]
 	ret i32 %t
 }
 
diff --git a/test/Transforms/ScalarRepl/address-space.ll b/test/Transforms/ScalarRepl/address-space.ll
index d8efc1774b7e..b8b90efefc3b 100644
--- a/test/Transforms/ScalarRepl/address-space.ll
+++ b/test/Transforms/ScalarRepl/address-space.ll
@@ -7,22 +7,22 @@ target triple = "x86_64-apple-darwin10"
 %struct.anon = type { [1 x float] }
 
 ; CHECK-LABEL: define void @Test(
-; CHECK: load float addrspace(2)*
+; CHECK: load float, float addrspace(2)*
 ; CHECK-NEXT: fsub float
 ; CHECK: store float {{.*}}, float addrspace(2)* 
 define void @Test(%struct.anon addrspace(2)* %pPtr) nounwind {
 entry:
   %s = alloca %struct.anon, align 4               ; <%struct.anon*> [#uses=3]
-  %arrayidx = getelementptr inbounds %struct.anon addrspace(2)* %pPtr, i64 0 ; <%struct.anon addrspace(2)*> [#uses=1]
+  %arrayidx = getelementptr inbounds %struct.anon, %struct.anon addrspace(2)* %pPtr, i64 0 ; <%struct.anon addrspace(2)*> [#uses=1]
   %tmp1 = bitcast %struct.anon* %s to i8*         ; <i8*> [#uses=1]
   %tmp2 = bitcast %struct.anon addrspace(2)* %arrayidx to i8 addrspace(2)* ; <i8 addrspace(2)*> [#uses=1]
   call void @llvm.memcpy.p0i8.p2i8.i64(i8* %tmp1, i8 addrspace(2)* %tmp2, i64 4, i32 4, i1 false)
-  %tmp3 = getelementptr inbounds %struct.anon* %s, i32 0, i32 0 ; <[1 x float]*> [#uses=1]
-  %arrayidx4 = getelementptr inbounds [1 x float]* %tmp3, i32 0, i64 0 ; <float*> [#uses=2]
-  %tmp5 = load float* %arrayidx4                  ; <float> [#uses=1]
+  %tmp3 = getelementptr inbounds %struct.anon, %struct.anon* %s, i32 0, i32 0 ; <[1 x float]*> [#uses=1]
+  %arrayidx4 = getelementptr inbounds [1 x float], [1 x float]* %tmp3, i32 0, i64 0 ; <float*> [#uses=2]
+  %tmp5 = load float, float* %arrayidx4                  ; <float> [#uses=1]
   %sub = fsub float %tmp5, 5.000000e+00           ; <float> [#uses=1]
   store float %sub, float* %arrayidx4
-  %arrayidx7 = getelementptr inbounds %struct.anon addrspace(2)* %pPtr, i64 0 ; <%struct.anon addrspace(2)*> [#uses=1]
+  %arrayidx7 = getelementptr inbounds %struct.anon, %struct.anon addrspace(2)* %pPtr, i64 0 ; <%struct.anon addrspace(2)*> [#uses=1]
   %tmp8 = bitcast %struct.anon addrspace(2)* %arrayidx7 to i8 addrspace(2)* ; <i8 addrspace(2)*> [#uses=1]
   %tmp9 = bitcast %struct.anon* %s to i8*         ; <i8*> [#uses=1]
   call void @llvm.memcpy.p2i8.p0i8.i64(i8 addrspace(2)* %tmp8, i8* %tmp9, i64 4, i32 4, i1 false)
diff --git a/test/Transforms/ScalarRepl/arraytest.ll b/test/Transforms/ScalarRepl/arraytest.ll
index 06a928c6d821..486e725fa6a5 100644
--- a/test/Transforms/ScalarRepl/arraytest.ll
+++ b/test/Transforms/ScalarRepl/arraytest.ll
@@ -3,9 +3,9 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 
 define i32 @test() {
 	%X = alloca [4 x i32]		; <[4 x i32]*> [#uses=1]
-	%Y = getelementptr [4 x i32]* %X, i64 0, i64 0		; <i32*> [#uses=2]
+	%Y = getelementptr [4 x i32], [4 x i32]* %X, i64 0, i64 0		; <i32*> [#uses=2]
 	store i32 0, i32* %Y
-	%Z = load i32* %Y		; <i32> [#uses=1]
+	%Z = load i32, i32* %Y		; <i32> [#uses=1]
 	ret i32 %Z
 }
 
diff --git a/test/Transforms/ScalarRepl/badarray.ll b/test/Transforms/ScalarRepl/badarray.ll
index 480e12b8d445..6f5bc95b43ba 100644
--- a/test/Transforms/ScalarRepl/badarray.ll
+++ b/test/Transforms/ScalarRepl/badarray.ll
@@ -10,9 +10,9 @@ define i32 @test1() {
 ; CHECK-LABEL: @test1(
 ; CHECK-NOT: = alloca
 	%X = alloca [4 x i32]
-	%Y = getelementptr [4 x i32]* %X, i64 0, i64 6		; <i32*> [#uses=2]
+	%Y = getelementptr [4 x i32], [4 x i32]* %X, i64 0, i64 6		; <i32*> [#uses=2]
 	store i32 0, i32* %Y
-	%Z = load i32* %Y		; <i32> [#uses=1]
+	%Z = load i32, i32* %Y		; <i32> [#uses=1]
 	ret i32 %Z
 }
 
@@ -24,7 +24,7 @@ entry:
 ; CHECK-NOT: = alloca
         %yx2.i = alloca float, align 4          ; <float*> [#uses=1]            
         %yx26.i = bitcast float* %yx2.i to i64*         ; <i64*> [#uses=1]      
-        %0 = load i64* %yx26.i, align 8         ; <i64> [#uses=0]               
+        %0 = load i64, i64* %yx26.i, align 8         ; <i64> [#uses=0]               
         unreachable
 }
 
@@ -38,9 +38,9 @@ entry:
 ; CHECK-NOT: = alloca
 ; CHECK: store i64
   %var_1 = alloca %padded, align 8                ; <%padded*> [#uses=3]
-  %0 = getelementptr inbounds %padded* %var_1, i32 0, i32 0 ; <%base*> [#uses=2]
+  %0 = getelementptr inbounds %padded, %padded* %var_1, i32 0, i32 0 ; <%base*> [#uses=2]
   
-  %p2 = getelementptr inbounds %base* %0, i32 0, i32 1, i32 0 ; <i8*> [#uses=1]
+  %p2 = getelementptr inbounds %base, %base* %0, i32 0, i32 1, i32 0 ; <i8*> [#uses=1]
   store i8 72, i8* %p2, align 1
   
   ; 72 -> a[0].
diff --git a/test/Transforms/ScalarRepl/basictest.ll b/test/Transforms/ScalarRepl/basictest.ll
index af3c237d4914..35d4d3ba86fe 100644
--- a/test/Transforms/ScalarRepl/basictest.ll
+++ b/test/Transforms/ScalarRepl/basictest.ll
@@ -3,9 +3,9 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 
 define i32 @test1() {
 	%X = alloca { i32, float }		; <{ i32, float }*> [#uses=1]
-	%Y = getelementptr { i32, float }* %X, i64 0, i32 0		; <i32*> [#uses=2]
+	%Y = getelementptr { i32, float }, { i32, float }* %X, i64 0, i32 0		; <i32*> [#uses=2]
 	store i32 0, i32* %Y
-	%Z = load i32* %Y		; <i32> [#uses=1]
+	%Z = load i32, i32* %Y		; <i32> [#uses=1]
 	ret i32 %Z
 ; CHECK-LABEL: @test1(
 ; CHECK-NOT: alloca
@@ -21,7 +21,7 @@ define i64 @test2(i64 %X) {
         br label %L2
         
 L2:
-	%Z = load i64* %B		; <i32> [#uses=1]
+	%Z = load i64, i64* %B		; <i32> [#uses=1]
 	ret i64 %Z
 ; CHECK-LABEL: @test2(
 ; CHECK-NOT: alloca
diff --git a/test/Transforms/ScalarRepl/bitfield-sroa.ll b/test/Transforms/ScalarRepl/bitfield-sroa.ll
index 3728658caaee..52986b0a49d7 100644
--- a/test/Transforms/ScalarRepl/bitfield-sroa.ll
+++ b/test/Transforms/ScalarRepl/bitfield-sroa.ll
@@ -7,11 +7,11 @@ define i8 @foo(i64 %A) {
         %ALL = alloca %t, align 8 
         %tmp59172 = bitcast %t* %ALL to i64*
         store i64 %A, i64* %tmp59172, align 8
-        %C = getelementptr %t* %ALL, i32 0, i32 0, i32 1             
+        %C = getelementptr %t, %t* %ALL, i32 0, i32 0, i32 1             
         %D = bitcast i16* %C to i32*    
-        %E = load i32* %D, align 4     
+        %E = load i32, i32* %D, align 4     
         %F = bitcast %t* %ALL to i8* 
-        %G = load i8* %F, align 8 
+        %G = load i8, i8* %F, align 8 
 	ret i8 %G
 }
 
diff --git a/test/Transforms/ScalarRepl/copy-aggregate.ll b/test/Transforms/ScalarRepl/copy-aggregate.ll
index 51ba8109b39b..97977dbf11f1 100644
--- a/test/Transforms/ScalarRepl/copy-aggregate.ll
+++ b/test/Transforms/ScalarRepl/copy-aggregate.ll
@@ -10,10 +10,10 @@ define i32 @test1(i64 %V) nounwind {
 	%Y = bitcast {{i32,i32}}* %X to i64*
 	store i64 %V, i64* %Y
 
-	%A = getelementptr {{i32,i32}}* %X, i32 0, i32 0, i32 0
-	%B = getelementptr {{i32,i32}}* %X, i32 0, i32 0, i32 1
-	%a = load i32* %A
-	%b = load i32* %B
+	%A = getelementptr {{i32,i32}}, {{i32,i32}}* %X, i32 0, i32 0, i32 0
+	%B = getelementptr {{i32,i32}}, {{i32,i32}}* %X, i32 0, i32 0, i32 1
+	%a = load i32, i32* %A
+	%b = load i32, i32* %B
 	%c = add i32 %a, %b
 	ret i32 %c
 }
@@ -26,10 +26,10 @@ define float @test2(i128 %V) nounwind {
 	%Y = bitcast {[4 x float]}* %X to i128*
 	store i128 %V, i128* %Y
 
-	%A = getelementptr {[4 x float]}* %X, i32 0, i32 0, i32 0
-	%B = getelementptr {[4 x float]}* %X, i32 0, i32 0, i32 3
-	%a = load float* %A
-	%b = load float* %B
+	%A = getelementptr {[4 x float]}, {[4 x float]}* %X, i32 0, i32 0, i32 0
+	%B = getelementptr {[4 x float]}, {[4 x float]}* %X, i32 0, i32 0, i32 3
+	%a = load float, float* %A
+	%b = load float, float* %B
 	%c = fadd float %a, %b
 	ret float %c
 }
@@ -40,13 +40,13 @@ define i64 @test3(i32 %a, i32 %b) nounwind {
 ; CHECK-NOT: alloca
 	%X = alloca {{i32, i32}}
 
-	%A = getelementptr {{i32,i32}}* %X, i32 0, i32 0, i32 0
-	%B = getelementptr {{i32,i32}}* %X, i32 0, i32 0, i32 1
+	%A = getelementptr {{i32,i32}}, {{i32,i32}}* %X, i32 0, i32 0, i32 0
+	%B = getelementptr {{i32,i32}}, {{i32,i32}}* %X, i32 0, i32 0, i32 1
         store i32 %a, i32* %A
         store i32 %b, i32* %B
 
 	%Y = bitcast {{i32,i32}}* %X to i64*
-        %Z = load i64* %Y
+        %Z = load i64, i64* %Y
 	ret i64 %Z
 }
 
@@ -55,13 +55,13 @@ define i128 @test4(float %a, float %b) nounwind {
 ; CHECK: test4
 ; CHECK-NOT: alloca
 	%X = alloca {[4 x float]}
-	%A = getelementptr {[4 x float]}* %X, i32 0, i32 0, i32 0
-	%B = getelementptr {[4 x float]}* %X, i32 0, i32 0, i32 3
+	%A = getelementptr {[4 x float]}, {[4 x float]}* %X, i32 0, i32 0, i32 0
+	%B = getelementptr {[4 x float]}, {[4 x float]}* %X, i32 0, i32 0, i32 3
 	store float %a, float* %A
 	store float %b, float* %B
         
       	%Y = bitcast {[4 x float]}* %X to i128*
-	%V = load i128* %Y
+	%V = load i128, i128* %Y
 	ret i128 %V
 }
 
diff --git a/test/Transforms/ScalarRepl/crash.ll b/test/Transforms/ScalarRepl/crash.ll
index 8c60dceb8b07..72e9f090fb68 100644
--- a/test/Transforms/ScalarRepl/crash.ll
+++ b/test/Transforms/ScalarRepl/crash.ll
@@ -11,7 +11,7 @@ entry:
   unreachable
 
 for.cond:                                         ; preds = %for.cond
-  %tmp1.i = load i32** %l_72, align 8
+  %tmp1.i = load i32*, i32** %l_72, align 8
   store i32* %tmp1.i, i32** %l_72, align 8
   br label %for.cond
 
@@ -22,15 +22,15 @@ if.end:                                           ; No predecessors!
 
 define void @test2() {
   %E = alloca { { i32, float, double, i64 }, { i32, float, double, i64 } }        ; <{ { i32, float, double, i64 }, { i32, float, double, i64 } }*> [#uses=1]
-  %tmp.151 = getelementptr { { i32, float, double, i64 }, { i32, float, double, i64 } }* %E, i64 0, i32 1, i32 3          ; <i64*> [#uses=0]
+  %tmp.151 = getelementptr { { i32, float, double, i64 }, { i32, float, double, i64 } }, { { i32, float, double, i64 }, { i32, float, double, i64 } }* %E, i64 0, i32 1, i32 3          ; <i64*> [#uses=0]
   ret void
 }
 
 define i32 @test3() {
         %X = alloca { [4 x i32] }               ; <{ [4 x i32] }*> [#uses=1]
-        %Y = getelementptr { [4 x i32] }* %X, i64 0, i32 0, i64 2               ; <i32*> [#uses=2]
+        %Y = getelementptr { [4 x i32] }, { [4 x i32] }* %X, i64 0, i32 0, i64 2               ; <i32*> [#uses=2]
         store i32 4, i32* %Y
-        %Z = load i32* %Y               ; <i32> [#uses=1]
+        %Z = load i32, i32* %Y               ; <i32> [#uses=1]
         ret i32 %Z
 }
 
@@ -102,11 +102,11 @@ bb9131:         ; preds = %bb1365
         ret void
 bb9875:         ; preds = %bb1365
         %source_ptr9884 = bitcast i8** %source_ptr to i8**              ; <i8**> [#uses=1]
-        %tmp9885 = load i8** %source_ptr9884            ; <i8*> [#uses=0]
+        %tmp9885 = load i8*, i8** %source_ptr9884            ; <i8*> [#uses=0]
         ret void
 bb10249:                ; preds = %bb1365
         %source_ptr10257 = bitcast i8** %source_ptr to i16**            ; <i16**> [#uses=1]
-        %tmp10258 = load i16** %source_ptr10257         ; <i16*> [#uses=0]
+        %tmp10258 = load i16*, i16** %source_ptr10257         ; <i16*> [#uses=0]
         ret void
 cond_next10377:         ; preds = %bb1365
         ret void
@@ -125,10 +125,10 @@ entry:
         %this_addr.i = alloca %"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"*                ; <%"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"**> [#uses=3]
         %tmp = alloca %"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>", align 4                ; <%"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"*> [#uses=1]
         store %"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"* %tmp, %"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"** %this_addr.i
-        %tmp.i = load %"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"** %this_addr.i          ; <%"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"*> [#uses=1]
+        %tmp.i = load %"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"*, %"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"** %this_addr.i          ; <%"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"*> [#uses=1]
         %tmp.i.upgrd.1 = bitcast %"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"* %tmp.i to %"struct.__gnu_cxx::bitmap_allocator<char>"*              ; <%"struct.__gnu_cxx::bitmap_allocator<char>"*> [#uses=0]
-        %tmp1.i = load %"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"** %this_addr.i         ; <%"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"*> [#uses=1]
-        %tmp.i.upgrd.2 = getelementptr %"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"* %tmp1.i, i32 0, i32 0         ; <%"struct.__gnu_cxx::bitmap_allocator<char>::_Alloc_block"**> [#uses=0]
+        %tmp1.i = load %"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"*, %"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"** %this_addr.i         ; <%"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"*> [#uses=1]
+        %tmp.i.upgrd.2 = getelementptr %"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>", %"struct.__gnu_cxx::balloc::_Inclusive_between<__gnu_cxx::bitmap_allocator<char>::_Alloc_block*>"* %tmp1.i, i32 0, i32 0         ; <%"struct.__gnu_cxx::bitmap_allocator<char>::_Alloc_block"**> [#uses=0]
         unreachable
 }
 
@@ -161,8 +161,8 @@ cond_next:              ; preds = %cond_true
         br i1 false, label %cond_next34, label %cond_next79
 
 cond_next34:            ; preds = %cond_next
-        %i.2.reload22 = load i32* null          ; <i32> [#uses=1]
-        %tmp51 = getelementptr %struct.aal_spanbucket_t* %SB, i32 0, i32 2, i32 0, i32 0, i32 %i.2.reload22, i32 1      
+        %i.2.reload22 = load i32, i32* null          ; <i32> [#uses=1]
+        %tmp51 = getelementptr %struct.aal_spanbucket_t, %struct.aal_spanbucket_t* %SB, i32 0, i32 2, i32 0, i32 0, i32 %i.2.reload22, i32 1      
         ; <i16*> [#uses=0]
         ret void
 
@@ -180,7 +180,7 @@ cond_next79:            ; preds = %cond_next, %entry
 define void @test8() {
 entry:
         %v = alloca %struct.c37304a__vrec
-        %0 = getelementptr %struct.c37304a__vrec* %v, i32 0, i32 0             
+        %0 = getelementptr %struct.c37304a__vrec, %struct.c37304a__vrec* %v, i32 0, i32 0             
         store i8 8, i8* %0, align 1
         unreachable
 }
@@ -193,7 +193,7 @@ entry:
 define i32 @test9() {
 entry:
         %.compoundliteral = alloca %0           
-        %tmp228 = getelementptr %0* %.compoundliteral, i32 0, i32 7
+        %tmp228 = getelementptr %0, %0* %.compoundliteral, i32 0, i32 7
         %tmp229 = bitcast [0 x i16]* %tmp228 to i8*             
         call void @llvm.memset.p0i8.i64(i8* %tmp229, i8 0, i64 0, i32 2, i1 false)
         unreachable
@@ -207,7 +207,7 @@ declare void @llvm.memset.i64(i8* nocapture, i8, i64, i32) nounwind
 define void @test10() {
 entry:
         %w = alloca %wrapper, align 8           ; <%wrapper*> [#uses=1]
-        %0 = getelementptr %wrapper* %w, i64 0, i32 0           ; <i1*>
+        %0 = getelementptr %wrapper, %wrapper* %w, i64 0, i32 0           ; <i1*>
         store i1 true, i1* %0
         ret void
 }
@@ -220,8 +220,8 @@ entry:
         %a = alloca %struct.singlebool, align 1         ; <%struct.singlebool*> [#uses=2]
         %storetmp.i = bitcast %struct.singlebool* %a to i1*             ; <i1*> [#uses=1]
         store i1 true, i1* %storetmp.i
-        %tmp = getelementptr %struct.singlebool* %a, i64 0, i32 0               ; <i8*> [#uses=1]
-        %tmp1 = load i8* %tmp           ; <i8> [#uses=1]
+        %tmp = getelementptr %struct.singlebool, %struct.singlebool* %a, i64 0, i32 0               ; <i8*> [#uses=1]
+        %tmp1 = load i8, i8* %tmp           ; <i8> [#uses=1]
         ret i8 %tmp1
 }
 
@@ -246,7 +246,7 @@ define void @test12() {
 bb4.i:
         %malloccall = tail call i8* @malloc(i32 0)
         %0 = bitcast i8* %malloccall to [0 x %struct.Item]*
-        %.sub.i.c.i = getelementptr [0 x %struct.Item]* %0, i32 0, i32 0                ; <%struct.Item*> [#uses=0]
+        %.sub.i.c.i = getelementptr [0 x %struct.Item], [0 x %struct.Item]* %0, i32 0, i32 0                ; <%struct.Item*> [#uses=0]
         unreachable
 }
 declare noalias i8* @malloc(i32)
@@ -268,13 +268,13 @@ define fastcc void @test() optsize inlinehint ssp align 2 {
 entry:
   %alloc.0.0 = alloca <4 x float>, align 16
   %bitcast = bitcast <4 x float>* %alloc.0.0 to [4 x float]*
-  %idx3 = getelementptr inbounds [4 x float]* %bitcast, i32 0, i32 3
+  %idx3 = getelementptr inbounds [4 x float], [4 x float]* %bitcast, i32 0, i32 3
   store float 0.000000e+00, float* %idx3, align 4
   br label %for.body10
 
 for.body10:                                       ; preds = %for.body10, %entry
   %loopidx = phi i32 [ 0, %entry ], [ undef, %for.body10 ]
-  %unusedidx = getelementptr inbounds <4 x float>* %alloc.0.0, i32 0, i32 %loopidx
+  %unusedidx = getelementptr inbounds <4 x float>, <4 x float>* %alloc.0.0, i32 0, i32 %loopidx
   br i1 undef, label %for.end, label %for.body10
 
 for.end:                                          ; preds = %for.body10
diff --git a/test/Transforms/ScalarRepl/debuginfo-preserved.ll b/test/Transforms/ScalarRepl/debuginfo-preserved.ll
index b0c459e21b10..8e5d4ff773dd 100644
--- a/test/Transforms/ScalarRepl/debuginfo-preserved.ll
+++ b/test/Transforms/ScalarRepl/debuginfo-preserved.ll
@@ -17,22 +17,22 @@ entry:
   %b.addr = alloca i32, align 4
   %c = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !6, metadata !{}), !dbg !7
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !6, metadata !DIExpression()), !dbg !7
   store i32 %b, i32* %b.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %b.addr, metadata !8, metadata !{}), !dbg !9
-  call void @llvm.dbg.declare(metadata i32* %c, metadata !10, metadata !{}), !dbg !12
-  %tmp = load i32* %a.addr, align 4, !dbg !13
+  call void @llvm.dbg.declare(metadata i32* %b.addr, metadata !8, metadata !DIExpression()), !dbg !9
+  call void @llvm.dbg.declare(metadata i32* %c, metadata !10, metadata !DIExpression()), !dbg !12
+  %tmp = load i32, i32* %a.addr, align 4, !dbg !13
   store i32 %tmp, i32* %c, align 4, !dbg !13
-  %tmp1 = load i32* %a.addr, align 4, !dbg !14
-  %tmp2 = load i32* %b.addr, align 4, !dbg !14
+  %tmp1 = load i32, i32* %a.addr, align 4, !dbg !14
+  %tmp2 = load i32, i32* %b.addr, align 4, !dbg !14
   %add = add nsw i32 %tmp1, %tmp2, !dbg !14
   store i32 %add, i32* %a.addr, align 4, !dbg !14
-  %tmp3 = load i32* %c, align 4, !dbg !15
-  %tmp4 = load i32* %b.addr, align 4, !dbg !15
+  %tmp3 = load i32, i32* %c, align 4, !dbg !15
+  %tmp4 = load i32, i32* %b.addr, align 4, !dbg !15
   %sub = sub nsw i32 %tmp3, %tmp4, !dbg !15
   store i32 %sub, i32* %b.addr, align 4, !dbg !15
-  %tmp5 = load i32* %a.addr, align 4, !dbg !16
-  %tmp6 = load i32* %b.addr, align 4, !dbg !16
+  %tmp5 = load i32, i32* %a.addr, align 4, !dbg !16
+  %tmp6 = load i32, i32* %b.addr, align 4, !dbg !16
   %add7 = add nsw i32 %tmp5, %tmp6, !dbg !16
   ret i32 %add7, !dbg !16
 }
@@ -42,24 +42,24 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!20}
 
-!0 = !{!"0x11\0012\00clang version 3.0 (trunk 131941)\000\00\000\00\000", !18, !19, !19, !17, null, null} ; [ DW_TAG_compile_unit ]
-!1 = !{!"0x2e\00f\00f\00\001\000\001\000\006\00256\000\001", !18, !2, !3, null, i32 (i32, i32)* @f, null, null, null} ; [ DW_TAG_subprogram ] [line 1] [def] [f]
-!2 = !{!"0x29", !18} ; [ DW_TAG_file_type ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !18, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 131941)", isOptimized: false, emissionKind: 0, file: !18, enums: !19, retainedTypes: !19, subprograms: !17)
+!1 = !DISubprogram(name: "f", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 1, file: !18, scope: !2, type: !3, function: i32 (i32, i32)* @f)
+!2 = !DIFile(filename: "/d/j/debug-test.c", directory: "/Volumes/Data/b")
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ]
-!6 = !{!"0x101\00a\0016777217\000", !1, !2, !5} ; [ DW_TAG_arg_variable ]
-!7 = !MDLocation(line: 1, column: 11, scope: !1)
-!8 = !{!"0x101\00b\0033554433\000", !1, !2, !5} ; [ DW_TAG_arg_variable ]
-!9 = !MDLocation(line: 1, column: 18, scope: !1)
-!10 = !{!"0x100\00c\002\000", !11, !2, !5} ; [ DW_TAG_auto_variable ]
-!11 = !{!"0xb\001\0021\000", !18, !1} ; [ DW_TAG_lexical_block ]
-!12 = !MDLocation(line: 2, column: 9, scope: !11)
-!13 = !MDLocation(line: 2, column: 14, scope: !11)
-!14 = !MDLocation(line: 3, column: 5, scope: !11)
-!15 = !MDLocation(line: 4, column: 5, scope: !11)
-!16 = !MDLocation(line: 5, column: 5, scope: !11)
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 1, arg: 1, scope: !1, file: !2, type: !5)
+!7 = !DILocation(line: 1, column: 11, scope: !1)
+!8 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 1, arg: 2, scope: !1, file: !2, type: !5)
+!9 = !DILocation(line: 1, column: 18, scope: !1)
+!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "c", line: 2, scope: !11, file: !2, type: !5)
+!11 = distinct !DILexicalBlock(line: 1, column: 21, file: !18, scope: !1)
+!12 = !DILocation(line: 2, column: 9, scope: !11)
+!13 = !DILocation(line: 2, column: 14, scope: !11)
+!14 = !DILocation(line: 3, column: 5, scope: !11)
+!15 = !DILocation(line: 4, column: 5, scope: !11)
+!16 = !DILocation(line: 5, column: 5, scope: !11)
 !17 = !{!1}
-!18 = !{!"/d/j/debug-test.c", !"/Volumes/Data/b"}
-!19 = !{i32 0}
-!20 = !{i32 1, !"Debug Info Version", i32 2}
+!18 = !DIFile(filename: "/d/j/debug-test.c", directory: "/Volumes/Data/b")
+!19 = !{}
+!20 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/ScalarRepl/inline-vector.ll b/test/Transforms/ScalarRepl/inline-vector.ll
index f7c70dcd5575..85f37414e656 100644
--- a/test/Transforms/ScalarRepl/inline-vector.ll
+++ b/test/Transforms/ScalarRepl/inline-vector.ll
@@ -30,22 +30,22 @@ for.body:                                         ; preds = %for.cond
   %tmp3 = bitcast %struct.Vector4* %vector to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp2, i8* %tmp3, i32 16, i32 16, i1 false)
   %0 = bitcast %struct.Vector4* %agg.tmp to [2 x i64]*
-  %1 = load [2 x i64]* %0, align 16
+  %1 = load [2 x i64], [2 x i64]* %0, align 16
   %tmp2.i = extractvalue [2 x i64] %1, 0
   %tmp3.i = zext i64 %tmp2.i to i128
   %tmp10.i = bitcast i128 %tmp3.i to <4 x float>
   %sub.i.i = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %tmp10.i
   %2 = bitcast %struct.Vector4* %vector to <4 x float>*
   store <4 x float> %sub.i.i, <4 x float>* %2, align 16
-  %tmp4 = load i32* %i, align 4
+  %tmp4 = load i32, i32* %i, align 4
   %inc = add nsw i32 %tmp4, 1
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
-  %x = getelementptr inbounds %struct.Vector4* %vector, i32 0, i32 0
-  %tmp5 = load float* %x, align 16
+  %x = getelementptr inbounds %struct.Vector4, %struct.Vector4* %vector, i32 0, i32 0
+  %tmp5 = load float, float* %x, align 16
   %conv = fpext float %tmp5 to double
-  %call = call i32 (...)* @printf(double %conv) nounwind
+  %call = call i32 (...) @printf(double %conv) nounwind
   ret void
 }
 
diff --git a/test/Transforms/ScalarRepl/lifetime.ll b/test/Transforms/ScalarRepl/lifetime.ll
index 47cb8549822b..c0ddfb58bbdf 100644
--- a/test/Transforms/ScalarRepl/lifetime.ll
+++ b/test/Transforms/ScalarRepl/lifetime.ll
@@ -11,9 +11,9 @@ declare void @llvm.lifetime.end(i64, i8*)
 define void @test1() {
 ; CHECK-LABEL: @test1(
   %A = alloca %t1
-  %A1 = getelementptr %t1* %A, i32 0, i32 0
-  %A2 = getelementptr %t1* %A, i32 0, i32 1
-  %A3 = getelementptr %t1* %A, i32 0, i32 2
+  %A1 = getelementptr %t1, %t1* %A, i32 0, i32 0
+  %A2 = getelementptr %t1, %t1* %A, i32 0, i32 1
+  %A3 = getelementptr %t1, %t1* %A, i32 0, i32 2
   %B = bitcast i32* %A1 to i8*
   store i32 0, i32* %A1
   call void @llvm.lifetime.start(i64 -1, i8* %B)
@@ -24,13 +24,13 @@ define void @test1() {
 define void @test2() {
 ; CHECK-LABEL: @test2(
   %A = alloca %t1
-  %A1 = getelementptr %t1* %A, i32 0, i32 0
-  %A2 = getelementptr %t1* %A, i32 0, i32 1
-  %A3 = getelementptr %t1* %A, i32 0, i32 2
+  %A1 = getelementptr %t1, %t1* %A, i32 0, i32 0
+  %A2 = getelementptr %t1, %t1* %A, i32 0, i32 1
+  %A3 = getelementptr %t1, %t1* %A, i32 0, i32 2
   %B = bitcast i32* %A2 to i8*
   store i32 0, i32* %A2
   call void @llvm.lifetime.start(i64 -1, i8* %B)
-  %C = load i32* %A2
+  %C = load i32, i32* %A2
   ret void
 ; CHECK: ret void
 }
@@ -38,13 +38,13 @@ define void @test2() {
 define void @test3() {
 ; CHECK-LABEL: @test3(
   %A = alloca %t1
-  %A1 = getelementptr %t1* %A, i32 0, i32 0
-  %A2 = getelementptr %t1* %A, i32 0, i32 1
-  %A3 = getelementptr %t1* %A, i32 0, i32 2
+  %A1 = getelementptr %t1, %t1* %A, i32 0, i32 0
+  %A2 = getelementptr %t1, %t1* %A, i32 0, i32 1
+  %A3 = getelementptr %t1, %t1* %A, i32 0, i32 2
   %B = bitcast i32* %A2 to i8*
   store i32 0, i32* %A2
   call void @llvm.lifetime.start(i64 6, i8* %B)
-  %C = load i32* %A2
+  %C = load i32, i32* %A2
   ret void
 ; CHECK-NEXT: ret void
 }
@@ -52,13 +52,13 @@ define void @test3() {
 define void @test4() {
 ; CHECK-LABEL: @test4(
   %A = alloca %t1
-  %A1 = getelementptr %t1* %A, i32 0, i32 0
-  %A2 = getelementptr %t1* %A, i32 0, i32 1
-  %A3 = getelementptr %t1* %A, i32 0, i32 2
+  %A1 = getelementptr %t1, %t1* %A, i32 0, i32 0
+  %A2 = getelementptr %t1, %t1* %A, i32 0, i32 1
+  %A3 = getelementptr %t1, %t1* %A, i32 0, i32 2
   %B = bitcast i32* %A2 to i8*
   store i32 0, i32* %A2
   call void @llvm.lifetime.start(i64 1, i8* %B)
-  %C = load i32* %A2
+  %C = load i32, i32* %A2
   ret void
 ; CHECK-NEXT: ret void
 }
@@ -72,25 +72,25 @@ define void @test5() {
 ; CHECK: alloca{{.*}}i8
 ; CHECK: alloca{{.*}}i8
 
-  %A21 = getelementptr %t2* %A, i32 0, i32 1, i32 0
-  %A22 = getelementptr %t2* %A, i32 0, i32 1, i32 1
-  %A23 = getelementptr %t2* %A, i32 0, i32 1, i32 2
-  %A24 = getelementptr %t2* %A, i32 0, i32 1, i32 3
+  %A21 = getelementptr %t2, %t2* %A, i32 0, i32 1, i32 0
+  %A22 = getelementptr %t2, %t2* %A, i32 0, i32 1, i32 1
+  %A23 = getelementptr %t2, %t2* %A, i32 0, i32 1, i32 2
+  %A24 = getelementptr %t2, %t2* %A, i32 0, i32 1, i32 3
 ; CHECK-NOT: store i8 1
   store i8 1, i8* %A21
   store i8 2, i8* %A22
   store i8 3, i8* %A23
   store i8 4, i8* %A24
 
-  %A1 = getelementptr %t2* %A, i32 0, i32 0
-  %A2 = getelementptr %t2* %A, i32 0, i32 1, i32 1
-  %A3 = getelementptr %t2* %A, i32 0, i32 2
+  %A1 = getelementptr %t2, %t2* %A, i32 0, i32 0
+  %A2 = getelementptr %t2, %t2* %A, i32 0, i32 1, i32 1
+  %A3 = getelementptr %t2, %t2* %A, i32 0, i32 2
   store i8 0, i8* %A2
   call void @llvm.lifetime.start(i64 5, i8* %A2)
 ; CHECK: llvm.lifetime{{.*}}i64 1
 ; CHECK: llvm.lifetime{{.*}}i64 1
 ; CHECK: llvm.lifetime{{.*}}i64 1
-  %C = load i8* %A2
+  %C = load i8, i8* %A2
   ret void
 }
 
@@ -103,10 +103,10 @@ define void @test6() {
 ; CHECK: alloca i8
 ; CHECK: alloca i8
 
-  %A11 = getelementptr %t3* %A, i32 0, i32 0, i32 0
-  %A12 = getelementptr %t3* %A, i32 0, i32 0, i32 1
-  %A13 = getelementptr %t3* %A, i32 0, i32 0, i32 2
-  %A14 = getelementptr %t3* %A, i32 0, i32 0, i32 3
+  %A11 = getelementptr %t3, %t3* %A, i32 0, i32 0, i32 0
+  %A12 = getelementptr %t3, %t3* %A, i32 0, i32 0, i32 1
+  %A13 = getelementptr %t3, %t3* %A, i32 0, i32 0, i32 2
+  %A14 = getelementptr %t3, %t3* %A, i32 0, i32 0, i32 3
   store i16 11, i16* %A11
   store i16 12, i16* %A12
   store i16 13, i16* %A13
@@ -116,10 +116,10 @@ define void @test6() {
 ; CHECK-NOT: store i16 13
 ; CHECK-NOT: store i16 14
 
-  %A21 = getelementptr %t3* %A, i32 0, i32 1, i32 0
-  %A22 = getelementptr %t3* %A, i32 0, i32 1, i32 1
-  %A23 = getelementptr %t3* %A, i32 0, i32 1, i32 2
-  %A24 = getelementptr %t3* %A, i32 0, i32 1, i32 3
+  %A21 = getelementptr %t3, %t3* %A, i32 0, i32 1, i32 0
+  %A22 = getelementptr %t3, %t3* %A, i32 0, i32 1, i32 1
+  %A23 = getelementptr %t3, %t3* %A, i32 0, i32 1, i32 2
+  %A24 = getelementptr %t3, %t3* %A, i32 0, i32 1, i32 3
   store i8 21, i8* %A21
   store i8 22, i8* %A22
   store i8 23, i8* %A23
diff --git a/test/Transforms/ScalarRepl/load-store-aggregate.ll b/test/Transforms/ScalarRepl/load-store-aggregate.ll
index c5008ac1312f..88299f3679c2 100644
--- a/test/Transforms/ScalarRepl/load-store-aggregate.ll
+++ b/test/Transforms/ScalarRepl/load-store-aggregate.ll
@@ -11,21 +11,21 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 define i32 @test(%struct.foo* %P) {
 entry:
 	%L = alloca %struct.foo, align 8		; <%struct.foo*> [#uses=2]
-        %V = load %struct.foo* %P
+        %V = load %struct.foo, %struct.foo* %P
         store %struct.foo %V, %struct.foo* %L
 
-	%tmp4 = getelementptr %struct.foo* %L, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp5 = load i32* %tmp4		; <i32> [#uses=1]
+	%tmp4 = getelementptr %struct.foo, %struct.foo* %L, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp5 = load i32, i32* %tmp4		; <i32> [#uses=1]
 	ret i32 %tmp5
 }
 
 define %struct.foo @test2(i32 %A, i32 %B) {
 entry:
 	%L = alloca %struct.foo, align 8		; <%struct.foo*> [#uses=2]
-        %L.0 = getelementptr %struct.foo* %L, i32 0, i32 0
+        %L.0 = getelementptr %struct.foo, %struct.foo* %L, i32 0, i32 0
         store i32 %A, i32* %L.0
-        %L.1 = getelementptr %struct.foo* %L, i32 0, i32 1
+        %L.1 = getelementptr %struct.foo, %struct.foo* %L, i32 0, i32 1
         store i32 %B, i32* %L.1
-        %V = load %struct.foo* %L
+        %V = load %struct.foo, %struct.foo* %L
         ret %struct.foo %V
 }
diff --git a/test/Transforms/ScalarRepl/memcpy-align.ll b/test/Transforms/ScalarRepl/memcpy-align.ll
index 6046e1295d9e..29a1bb8a4b5a 100644
--- a/test/Transforms/ScalarRepl/memcpy-align.ll
+++ b/test/Transforms/ScalarRepl/memcpy-align.ll
@@ -15,7 +15,7 @@ entry:
   %tmp = bitcast %struct.anon* %x0 to i8*         ; <i8*> [#uses=1]
   call void @llvm.memset.p0i8.i32(i8* %tmp, i8 0, i32 4, i32 4, i1 false)
   %tmp1 = bitcast %struct.anon* %x0 to i8*        ; <i8*> [#uses=1]
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%0* @c, i32
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%0, %0* @c, i32
 0, i32 0, i32 0, i32 0), i8* %tmp1, i32 4, i32 4, i1 false)
   ret void
   
diff --git a/test/Transforms/ScalarRepl/memset-aggregate-byte-leader.ll b/test/Transforms/ScalarRepl/memset-aggregate-byte-leader.ll
index 8ac1d2570a1c..e8088c121fbc 100644
--- a/test/Transforms/ScalarRepl/memset-aggregate-byte-leader.ll
+++ b/test/Transforms/ScalarRepl/memset-aggregate-byte-leader.ll
@@ -12,10 +12,10 @@ target triple = "powerpc-apple-darwin8.8.0"
 define i32 @test1(%struct.foo* %P) {
 entry:
 	%L = alloca %struct.foo, align 2		; <%struct.foo*> [#uses=1]
-	%L2 = getelementptr %struct.foo* %L, i32 0, i32 0		; <i8*> [#uses=2]
-	%tmp13 = getelementptr %struct.foo* %P, i32 0, i32 0		; <i8*> [#uses=1]
+	%L2 = getelementptr %struct.foo, %struct.foo* %L, i32 0, i32 0		; <i8*> [#uses=2]
+	%tmp13 = getelementptr %struct.foo, %struct.foo* %P, i32 0, i32 0		; <i8*> [#uses=1]
 	call void @llvm.memcpy.p0i8.p0i8.i32( i8* %L2, i8* %tmp13, i32 2, i32 1, i1 false)
-	%tmp5 = load i8* %L2		; <i8> [#uses=1]
+	%tmp5 = load i8, i8* %L2		; <i8> [#uses=1]
 	%tmp56 = sext i8 %tmp5 to i32		; <i32> [#uses=1]
 	ret i32 %tmp56
 }
diff --git a/test/Transforms/ScalarRepl/memset-aggregate.ll b/test/Transforms/ScalarRepl/memset-aggregate.ll
index 3a5c37c04673..98e2dddefe7f 100644
--- a/test/Transforms/ScalarRepl/memset-aggregate.ll
+++ b/test/Transforms/ScalarRepl/memset-aggregate.ll
@@ -15,8 +15,8 @@ entry:
 	%L2 = bitcast %struct.foo* %L to i8*		; <i8*> [#uses=1]
 	%tmp13 = bitcast %struct.foo* %P to i8*		; <i8*> [#uses=1]
         call void @llvm.memcpy.p0i8.p0i8.i32(i8* %L2, i8* %tmp13, i32 8, i32 4, i1 false)
-	%tmp4 = getelementptr %struct.foo* %L, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp5 = load i32* %tmp4		; <i32> [#uses=1]
+	%tmp4 = getelementptr %struct.foo, %struct.foo* %L, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp5 = load i32, i32* %tmp4		; <i32> [#uses=1]
 	ret i32 %tmp5
 }
 
@@ -26,8 +26,8 @@ entry:
 	%L = alloca [4 x %struct.foo], align 16		; <[4 x %struct.foo]*> [#uses=2]
 	%L12 = bitcast [4 x %struct.foo]* %L to i8*		; <i8*> [#uses=1]
         call void @llvm.memset.p0i8.i32(i8* %L12, i8 0, i32 32, i32 16, i1 false)
-	%tmp4 = getelementptr [4 x %struct.foo]* %L, i32 0, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp5 = load i32* %tmp4		; <i32> [#uses=1]
+	%tmp4 = getelementptr [4 x %struct.foo], [4 x %struct.foo]* %L, i32 0, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp5 = load i32, i32* %tmp4		; <i32> [#uses=1]
 	ret i32 %tmp5
 }
 
@@ -37,12 +37,12 @@ entry:
 	%B = alloca %struct.bar, align 16		; <%struct.bar*> [#uses=4]
 	%B1 = bitcast %struct.bar* %B to i8*		; <i8*> [#uses=1]
 	call void @llvm.memset.p0i8.i32(i8* %B1, i8 1, i32 24, i32 16, i1 false)
-	%tmp3 = getelementptr %struct.bar* %B, i32 0, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp3 = getelementptr %struct.bar, %struct.bar* %B, i32 0, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 1, i32* %tmp3
-	%tmp4 = getelementptr %struct.bar* %B, i32 0, i32 2		; <double*> [#uses=1]
+	%tmp4 = getelementptr %struct.bar, %struct.bar* %B, i32 0, i32 2		; <double*> [#uses=1]
 	store double 1.000000e+01, double* %tmp4
-	%tmp6 = getelementptr %struct.bar* %B, i32 0, i32 0, i32 1		; <i32*> [#uses=1]
-	%tmp7 = load i32* %tmp6		; <i32> [#uses=1]
+	%tmp6 = getelementptr %struct.bar, %struct.bar* %B, i32 0, i32 0, i32 1		; <i32*> [#uses=1]
+	%tmp7 = load i32, i32* %tmp6		; <i32> [#uses=1]
 	ret i32 %tmp7
 }
 
@@ -52,13 +52,13 @@ entry:
 define i16 @test4() nounwind {
 entry:
 	%A = alloca %struct.f, align 8		; <%struct.f*> [#uses=3]
-	%0 = getelementptr %struct.f* %A, i32 0, i32 0		; <i32*> [#uses=1]
+	%0 = getelementptr %struct.f, %struct.f* %A, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 1, i32* %0, align 8
-	%1 = getelementptr %struct.f* %A, i32 0, i32 1		; <i32*> [#uses=1]
+	%1 = getelementptr %struct.f, %struct.f* %A, i32 0, i32 1		; <i32*> [#uses=1]
 	%2 = bitcast i32* %1 to i8*		; <i8*> [#uses=1]
 	call void @llvm.memset.p0i8.i32(i8* %2, i8 2, i32 12, i32 4, i1 false)
-	%3 = getelementptr %struct.f* %A, i32 0, i32 2		; <i32*> [#uses=1]
-	%4 = load i32* %3, align 8		; <i32> [#uses=1]
+	%3 = getelementptr %struct.f, %struct.f* %A, i32 0, i32 2		; <i32*> [#uses=1]
+	%4 = load i32, i32* %3, align 8		; <i32> [#uses=1]
 	%retval12 = trunc i32 %4 to i16		; <i16> [#uses=1]
 	ret i16 %retval12
 }
diff --git a/test/Transforms/ScalarRepl/negative-memset.ll b/test/Transforms/ScalarRepl/negative-memset.ll
index e52ab468fd2c..458d9610cd73 100644
--- a/test/Transforms/ScalarRepl/negative-memset.ll
+++ b/test/Transforms/ScalarRepl/negative-memset.ll
@@ -12,7 +12,7 @@ entry:
   store i32 0, i32* %retval
   %0 = bitcast [1 x i8]* %buff to i8*
   call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 1, i32 1, i1 false)
-  %arraydecay = getelementptr inbounds [1 x i8]* %buff, i32 0, i32 0
+  %arraydecay = getelementptr inbounds [1 x i8], [1 x i8]* %buff, i32 0, i32 0
   call void @llvm.memset.p0i8.i32(i8* %arraydecay, i8 -1, i32 -8, i32 1, i1 false)	; Negative 8!
   ret i32 0
 }
diff --git a/test/Transforms/ScalarRepl/nonzero-first-index.ll b/test/Transforms/ScalarRepl/nonzero-first-index.ll
index b2e93feb6cc2..da757b08d454 100644
--- a/test/Transforms/ScalarRepl/nonzero-first-index.ll
+++ b/test/Transforms/ScalarRepl/nonzero-first-index.ll
@@ -12,9 +12,9 @@ define i32 @test1() {
 ; CHECK-NOT: = i160
 ; CHECK: ret i32 undef
 	%A = alloca %nested
-	%B = getelementptr %nested* %A, i32 0, i32 1, i32 0
-	%C = getelementptr i32* %B, i32 2
-	%D = load i32* %C
+	%B = getelementptr %nested, %nested* %A, i32 0, i32 1, i32 0
+	%C = getelementptr i32, i32* %B, i32 2
+	%D = load i32, i32* %C
 	ret i32 %D
 }
 
@@ -23,9 +23,9 @@ define i32 @test2() {
 ; CHECK-LABEL: @test2(
 ; CHECK: i160
 	%A = alloca %nested
-	%B = getelementptr %nested* %A, i32 0, i32 1, i32 0
-	%C = getelementptr i32* %B, i32 4
-	%D = load i32* %C
+	%B = getelementptr %nested, %nested* %A, i32 0, i32 1, i32 0
+	%C = getelementptr i32, i32* %B, i32 4
+	%D = load i32, i32* %C
 	ret i32 %D
 }
 
@@ -36,8 +36,8 @@ define i32 @test3() {
 ; CHECK: ret i32 undef
 	%A = alloca %nested
 	%B = bitcast %nested* %A to i32*
-	%C = getelementptr i32* %B, i32 2
-	%D = load i32* %C
+	%C = getelementptr i32, i32* %B, i32 2
+	%D = load i32, i32* %C
 	ret i32 %D
 }
 
@@ -47,7 +47,7 @@ define i32 @test4() {
 ; CHECK: i160
 	%A = alloca %nested
 	%B = bitcast %nested* %A to i32*
-	%C = getelementptr i32* %B, i32 -1
-	%D = load i32* %C
+	%C = getelementptr i32, i32* %B, i32 -1
+	%D = load i32, i32* %C
 	ret i32 %D
 }
diff --git a/test/Transforms/ScalarRepl/not-a-vector.ll b/test/Transforms/ScalarRepl/not-a-vector.ll
index 67fefb4841b3..04c1f93617b9 100644
--- a/test/Transforms/ScalarRepl/not-a-vector.ll
+++ b/test/Transforms/ScalarRepl/not-a-vector.ll
@@ -8,12 +8,12 @@ define double @test(double %A, double %B) {
 	%C = bitcast [7 x i64]* %ARR to double*
 	store double %A, double* %C
 
-	%D = getelementptr [7 x i64]* %ARR, i32 0, i32 4
+	%D = getelementptr [7 x i64], [7 x i64]* %ARR, i32 0, i32 4
 	%E = bitcast i64* %D to double*
 	store double %B, double* %E
 
-	%F = getelementptr double* %C, i32 4
-	%G = load double* %F
+	%F = getelementptr double, double* %C, i32 4
+	%G = load double, double* %F
 	ret double %G
 }
 
diff --git a/test/Transforms/ScalarRepl/only-memcpy-uses.ll b/test/Transforms/ScalarRepl/only-memcpy-uses.ll
index 935c2895520c..d0ed20b26bca 100644
--- a/test/Transforms/ScalarRepl/only-memcpy-uses.ll
+++ b/test/Transforms/ScalarRepl/only-memcpy-uses.ll
@@ -18,7 +18,7 @@ entry:
   %tmp2 = bitcast %struct.S* %agg.tmp to i8*
   %tmp3 = bitcast %struct.S* %t to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp2, i8* %tmp3, i64 48, i32 4, i1 false)
-  %call = call i32 (...)* @bazz(%struct.S* byval %agg.tmp)
+  %call = call i32 (...) @bazz(%struct.S* byval %agg.tmp)
   ret void
 }
 
diff --git a/test/Transforms/ScalarRepl/phi-cycle.ll b/test/Transforms/ScalarRepl/phi-cycle.ll
index 05d9382cec40..a44f08180643 100644
--- a/test/Transforms/ScalarRepl/phi-cycle.ll
+++ b/test/Transforms/ScalarRepl/phi-cycle.ll
@@ -11,9 +11,9 @@ target triple = "x86_64-unknown-linux-gnu"
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind uwtable {
 entry:
   %f = alloca %struct.foo, align 4
-  %x.i = getelementptr inbounds %struct.foo* %f, i64 0, i32 0
+  %x.i = getelementptr inbounds %struct.foo, %struct.foo* %f, i64 0, i32 0
   store i32 1, i32* %x.i, align 4
-  %y.i = getelementptr inbounds %struct.foo* %f, i64 0, i32 1
+  %y.i = getelementptr inbounds %struct.foo, %struct.foo* %f, i64 0, i32 1
   br label %while.cond.i
 
 ; CHECK: while.cond.i:
@@ -67,10 +67,10 @@ while.cond.backedge.i:                            ; preds = %if.end.i, %while.bo
 
 ; CHECK: func.exit:
 ; CHECK-NOT: load
-; CHECK: %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([6 x i8]* @.str, i64 0, i64 0), i32 %tmp) [[NUW:#[0-9]+]]
+; CHECK: %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0), i32 %tmp) [[NUW:#[0-9]+]]
 func.exit:                                        ; preds = %while.body.i.func.exit_crit_edge, %while.cond.i.func.exit_crit_edge
-  %tmp3 = load i32* %x.i, align 4
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([6 x i8]* @.str, i64 0, i64 0), i32 %tmp3) nounwind
+  %tmp3 = load i32, i32* %x.i, align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0), i32 %tmp3) nounwind
   ret i32 0
 }
 
diff --git a/test/Transforms/ScalarRepl/phi-select.ll b/test/Transforms/ScalarRepl/phi-select.ll
index a5da2dcf49d1..a6c7135a4925 100644
--- a/test/Transforms/ScalarRepl/phi-select.ll
+++ b/test/Transforms/ScalarRepl/phi-select.ll
@@ -13,14 +13,14 @@ define i32 @test1(i32 %x) nounwind readnone ssp {
 entry:
   %a = alloca %struct.X, align 8                  ; <%struct.X*> [#uses=2]
   %b = alloca %struct.X, align 8                  ; <%struct.X*> [#uses=2]
-  %0 = getelementptr inbounds %struct.X* %a, i64 0, i32 0 ; <i32*> [#uses=1]
+  %0 = getelementptr inbounds %struct.X, %struct.X* %a, i64 0, i32 0 ; <i32*> [#uses=1]
   store i32 1, i32* %0, align 8
-  %1 = getelementptr inbounds %struct.X* %b, i64 0, i32 0 ; <i32*> [#uses=1]
+  %1 = getelementptr inbounds %struct.X, %struct.X* %b, i64 0, i32 0 ; <i32*> [#uses=1]
   store i32 2, i32* %1, align 8
   %2 = icmp eq i32 %x, 0                          ; <i1> [#uses=1]
   %p.0 = select i1 %2, %struct.X* %b, %struct.X* %a ; <%struct.X*> [#uses=1]
-  %3 = getelementptr inbounds %struct.X* %p.0, i64 0, i32 0 ; <i32*> [#uses=1]
-  %4 = load i32* %3, align 8                      ; <i32> [#uses=1]
+  %3 = getelementptr inbounds %struct.X, %struct.X* %p.0, i64 0, i32 0 ; <i32*> [#uses=1]
+  %4 = load i32, i32* %3, align 8                      ; <i32> [#uses=1]
   ret i32 %4
 }
 
@@ -30,16 +30,16 @@ entry:
 define i32 @test2(i1 %c) {
 entry:
   %A = alloca {i32, i32}
-  %B = getelementptr {i32, i32}* %A, i32 0, i32 0
+  %B = getelementptr {i32, i32}, {i32, i32}* %A, i32 0, i32 0
   store i32 1, i32* %B
   br i1 %c, label %T, label %F
 T:
-  %C = getelementptr {i32, i32}* %A, i32 0, i32 1
+  %C = getelementptr {i32, i32}, {i32, i32}* %A, i32 0, i32 1
   store i32 2, i32* %C
   br label %F
 F:
   %X = phi i32* [%B, %entry], [%C, %T]
-  %Q = load i32* %X
+  %Q = load i32, i32* %X
   ret i32 %Q
 }
 
@@ -49,13 +49,13 @@ F:
 ; rdar://8904039
 define i32 @test3(i1 %c) {
   %A = alloca {i32, i32}
-  %B = getelementptr {i32, i32}* %A, i32 0, i32 0
+  %B = getelementptr {i32, i32}, {i32, i32}* %A, i32 0, i32 0
   store i32 1, i32* %B
-  %C = getelementptr {i32, i32}* %A, i32 0, i32 1
+  %C = getelementptr {i32, i32}, {i32, i32}* %A, i32 0, i32 1
   store i32 2, i32* %C
   
   %X = select i1 %c, i32* %B, i32* %C
-  %Q = load i32* %X
+  %Q = load i32, i32* %X
   ret i32 %Q
 }
 
@@ -65,14 +65,14 @@ entry:
   %A = alloca %PairTy
   ; CHECK-LABEL: @test4(
   ; CHECK: %A = alloca %PairTy
-  %B = getelementptr %PairTy* %A, i32 0, i32 0
+  %B = getelementptr %PairTy, %PairTy* %A, i32 0, i32 0
   store i32 1, i32* %B
-  %C = getelementptr %PairTy* %A, i32 0, i32 1
+  %C = getelementptr %PairTy, %PairTy* %A, i32 0, i32 1
   store i32 2, i32* %B
   
   %X = select i1 %c, i32* %B, i32* %C
   %Y = bitcast i32* %X to i64*
-  %Q = load i64* %Y
+  %Q = load i64, i64* %Y
   ret i64 %Q
 }
 
@@ -91,7 +91,7 @@ entry:
   %p.0 = select i1 false, i32* %b, i32* %P
   store i32 123, i32* %p.0
   
-  %r = load i32* %b, align 8
+  %r = load i32, i32* %b, align 8
   ret i32 %r
   
 ; CHECK-LABEL: @test5(
@@ -105,7 +105,7 @@ define i32 @test6(i32 %x, i1 %c) nounwind readnone ssp {
   store i32 1, i32* %a, align 8
   store i32 2, i32* %b, align 8
   %p.0 = select i1 %c, i32* %b, i32* %a
-  %r = load i32* %p.0, align 8
+  %r = load i32, i32* %p.0, align 8
   ret i32 %r
 ; CHECK-LABEL: @test6(
 ; CHECK-NEXT: %r = select i1 %c, i32 2, i32 1
@@ -122,7 +122,7 @@ define i32 @test7(i32 %x, i1 %c) nounwind readnone ssp {
   
   store i32 0, i32* %a
   
-  %r = load i32* %p.0, align 8
+  %r = load i32, i32* %p.0, align 8
   ret i32 %r
 ; CHECK-LABEL: @test7(
 ; CHECK-NOT: alloca i32
@@ -148,6 +148,6 @@ T:
   br label %Cont
 Cont:
   %p.0 = phi i32* [%b, %entry],[%a, %T]
-  %r = load i32* %p.0, align 8
+  %r = load i32, i32* %p.0, align 8
   ret i32 %r
 }
diff --git a/test/Transforms/ScalarRepl/phinodepromote.ll b/test/Transforms/ScalarRepl/phinodepromote.ll
index 9c6e8b92f3e5..c3af62485db1 100644
--- a/test/Transforms/ScalarRepl/phinodepromote.ll
+++ b/test/Transforms/ScalarRepl/phinodepromote.ll
@@ -21,14 +21,14 @@ entry:
 	%mem_tmp.1 = alloca i32		; <i32*> [#uses=3]
 	store i32 0, i32* %mem_tmp.0
 	store i32 1, i32* %mem_tmp.1
-	%tmp.1.i = load i32* %mem_tmp.1		; <i32> [#uses=1]
-	%tmp.3.i = load i32* %mem_tmp.0		; <i32> [#uses=1]
+	%tmp.1.i = load i32, i32* %mem_tmp.1		; <i32> [#uses=1]
+	%tmp.3.i = load i32, i32* %mem_tmp.0		; <i32> [#uses=1]
 	%tmp.4.i = icmp sle i32 %tmp.1.i, %tmp.3.i		; <i1> [#uses=1]
 	br i1 %tmp.4.i, label %cond_true.i, label %cond_continue.i
 cond_true.i:		; preds = %entry
 	br label %cond_continue.i
 cond_continue.i:		; preds = %cond_true.i, %entry
 	%mem_tmp.i.0 = phi i32* [ %mem_tmp.1, %cond_true.i ], [ %mem_tmp.0, %entry ]		; <i32*> [#uses=1]
-	%tmp.3 = load i32* %mem_tmp.i.0		; <i32> [#uses=1]
+	%tmp.3 = load i32, i32* %mem_tmp.i.0		; <i32> [#uses=1]
 	ret i32 %tmp.3
 }
diff --git a/test/Transforms/ScalarRepl/select_promote.ll b/test/Transforms/ScalarRepl/select_promote.ll
index d6b2b75327c5..b4ef8c46fa09 100644
--- a/test/Transforms/ScalarRepl/select_promote.ll
+++ b/test/Transforms/ScalarRepl/select_promote.ll
@@ -8,11 +8,11 @@ define i32 @main() {
 	%mem_tmp.1 = alloca i32		; <i32*> [#uses=3]
 	store i32 0, i32* %mem_tmp.0
 	store i32 1, i32* %mem_tmp.1
-	%tmp.1.i = load i32* %mem_tmp.1		; <i32> [#uses=1]
-	%tmp.3.i = load i32* %mem_tmp.0		; <i32> [#uses=1]
+	%tmp.1.i = load i32, i32* %mem_tmp.1		; <i32> [#uses=1]
+	%tmp.3.i = load i32, i32* %mem_tmp.0		; <i32> [#uses=1]
 	%tmp.4.i = icmp sle i32 %tmp.1.i, %tmp.3.i		; <i1> [#uses=1]
 	%mem_tmp.i.0 = select i1 %tmp.4.i, i32* %mem_tmp.1, i32* %mem_tmp.0		; <i32*> [#uses=1]
-	%tmp.3 = load i32* %mem_tmp.i.0		; <i32> [#uses=1]
+	%tmp.3 = load i32, i32* %mem_tmp.i.0		; <i32> [#uses=1]
 	ret i32 %tmp.3
 }
 
diff --git a/test/Transforms/ScalarRepl/sroa-fca.ll b/test/Transforms/ScalarRepl/sroa-fca.ll
index 2df3b9be1e48..c6e7c23ab066 100644
--- a/test/Transforms/ScalarRepl/sroa-fca.ll
+++ b/test/Transforms/ScalarRepl/sroa-fca.ll
@@ -6,7 +6,7 @@ define i64 @test({i32, i32} %A) {
 	%Y = bitcast i64* %X to {i32,i32}*
 	store {i32,i32} %A, {i32,i32}* %Y
 	
-	%Q = load i64* %X
+	%Q = load i64, i64* %X
 	ret i64 %Q
 }
 
@@ -15,7 +15,7 @@ define {i32,i32} @test2(i64 %A) {
 	%Y = bitcast i64* %X to {i32,i32}*
 	store i64 %A, i64* %X
 	
-	%Q = load {i32,i32}* %Y
+	%Q = load {i32,i32}, {i32,i32}* %Y
 	ret {i32,i32} %Q
 }
 
diff --git a/test/Transforms/ScalarRepl/sroa_two.ll b/test/Transforms/ScalarRepl/sroa_two.ll
index d8aa26dce637..f2285ef21a49 100644
--- a/test/Transforms/ScalarRepl/sroa_two.ll
+++ b/test/Transforms/ScalarRepl/sroa_two.ll
@@ -2,12 +2,12 @@
 
 define i32 @test(i32 %X) {
 	%Arr = alloca [2 x i32]		; <[2 x i32]*> [#uses=3]
-	%tmp.0 = getelementptr [2 x i32]* %Arr, i32 0, i32 0		; <i32*> [#uses=1]
+	%tmp.0 = getelementptr [2 x i32], [2 x i32]* %Arr, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 1, i32* %tmp.0
-	%tmp.1 = getelementptr [2 x i32]* %Arr, i32 0, i32 1		; <i32*> [#uses=1]
+	%tmp.1 = getelementptr [2 x i32], [2 x i32]* %Arr, i32 0, i32 1		; <i32*> [#uses=1]
 	store i32 2, i32* %tmp.1
-	%tmp.3 = getelementptr [2 x i32]* %Arr, i32 0, i32 %X		; <i32*> [#uses=1]
-	%tmp.4 = load i32* %tmp.3		; <i32> [#uses=1]
+	%tmp.3 = getelementptr [2 x i32], [2 x i32]* %Arr, i32 0, i32 %X		; <i32*> [#uses=1]
+	%tmp.4 = load i32, i32* %tmp.3		; <i32> [#uses=1]
 	ret i32 %tmp.4
 }
 
diff --git a/test/Transforms/ScalarRepl/union-fp-int.ll b/test/Transforms/ScalarRepl/union-fp-int.ll
index 6a4991887186..fa64b60685f4 100644
--- a/test/Transforms/ScalarRepl/union-fp-int.ll
+++ b/test/Transforms/ScalarRepl/union-fp-int.ll
@@ -8,7 +8,7 @@ define i32 @test(float %X) {
 	%X_addr = alloca float		; <float*> [#uses=2]
 	store float %X, float* %X_addr
 	%X_addr.upgrd.1 = bitcast float* %X_addr to i32*		; <i32*> [#uses=1]
-	%tmp = load i32* %X_addr.upgrd.1		; <i32> [#uses=1]
+	%tmp = load i32, i32* %X_addr.upgrd.1		; <i32> [#uses=1]
 	ret i32 %tmp
 }
 
diff --git a/test/Transforms/ScalarRepl/union-packed.ll b/test/Transforms/ScalarRepl/union-packed.ll
index b272abfc3d5b..741de76d581b 100644
--- a/test/Transforms/ScalarRepl/union-packed.ll
+++ b/test/Transforms/ScalarRepl/union-packed.ll
@@ -8,7 +8,7 @@ define <4 x i32> @test(<4 x float> %X) {
 	%X_addr = alloca <4 x float>		; <<4 x float>*> [#uses=2]
 	store <4 x float> %X, <4 x float>* %X_addr
 	%X_addr.upgrd.1 = bitcast <4 x float>* %X_addr to <4 x i32>*		; <<4 x i32>*> [#uses=1]
-	%tmp = load <4 x i32>* %X_addr.upgrd.1		; <<4 x i32>> [#uses=1]
+	%tmp = load <4 x i32>, <4 x i32>* %X_addr.upgrd.1		; <<4 x i32>> [#uses=1]
 	ret <4 x i32> %tmp
 }
 
diff --git a/test/Transforms/ScalarRepl/union-pointer.ll b/test/Transforms/ScalarRepl/union-pointer.ll
index f0dc141aca8d..6a5db1c4d6bd 100644
--- a/test/Transforms/ScalarRepl/union-pointer.ll
+++ b/test/Transforms/ScalarRepl/union-pointer.ll
@@ -14,7 +14,7 @@ define i8* @test(i16* %X) {
 	%X_addr = alloca i16*		; <i16**> [#uses=2]
 	store i16* %X, i16** %X_addr
 	%X_addr.upgrd.1 = bitcast i16** %X_addr to i8**		; <i8**> [#uses=1]
-	%tmp = load i8** %X_addr.upgrd.1		; <i8*> [#uses=1]
+	%tmp = load i8*, i8** %X_addr.upgrd.1		; <i8*> [#uses=1]
 	ret i8* %tmp
 }
 
@@ -26,7 +26,7 @@ define i8 addrspace(1)* @test_as1(i16 addrspace(1)* %x) {
     %x_addr = alloca i16 addrspace(1)*
 	store i16 addrspace(1)* %x, i16 addrspace(1)** %x_addr
 	%x_addr.upgrd.1 = bitcast i16 addrspace(1)** %x_addr to i8 addrspace(1)**
-	%tmp = load i8 addrspace(1)** %x_addr.upgrd.1
+	%tmp = load i8 addrspace(1)*, i8 addrspace(1)** %x_addr.upgrd.1
 	ret i8 addrspace(1)* %tmp
 }
 
@@ -36,10 +36,10 @@ define i8 addrspace(1)* @test_as1_array(i16 addrspace(1)* %x) {
 ; CHECK-NEXT: %2 = inttoptr i16 %1 to i8 addrspace(1)*
 ; CHECK-NEXT: ret i8 addrspace(1)* %2
   %as_ptr_array = alloca [4 x i16 addrspace(1)*]
-  %elem1 = getelementptr [4 x i16 addrspace(1)*]* %as_ptr_array, i32 0, i32 1
+  %elem1 = getelementptr [4 x i16 addrspace(1)*], [4 x i16 addrspace(1)*]* %as_ptr_array, i32 0, i32 1
   store i16 addrspace(1)* %x, i16 addrspace(1)** %elem1
   %elem1.cast = bitcast i16 addrspace(1)** %elem1 to i8 addrspace(1)**
-  %tmp = load i8 addrspace(1)** %elem1.cast
+  %tmp = load i8 addrspace(1)*, i8 addrspace(1)** %elem1.cast
   ret i8 addrspace(1)* %tmp
 }
 
@@ -54,17 +54,17 @@ define void @test2(i64 %Op.0) {
 	%tmp.upgrd.2 = call i64 @_Z3foov( )		; <i64> [#uses=1]
 	%tmp1.upgrd.3 = bitcast %struct.Val* %tmp1 to i64*		; <i64*> [#uses=1]
 	store i64 %tmp.upgrd.2, i64* %tmp1.upgrd.3
-	%tmp.upgrd.4 = getelementptr %struct.Val* %tmp, i32 0, i32 0		; <i32**> [#uses=1]
-	%tmp2 = getelementptr %struct.Val* %tmp1, i32 0, i32 0		; <i32**> [#uses=1]
-	%tmp.upgrd.5 = load i32** %tmp2		; <i32*> [#uses=1]
+	%tmp.upgrd.4 = getelementptr %struct.Val, %struct.Val* %tmp, i32 0, i32 0		; <i32**> [#uses=1]
+	%tmp2 = getelementptr %struct.Val, %struct.Val* %tmp1, i32 0, i32 0		; <i32**> [#uses=1]
+	%tmp.upgrd.5 = load i32*, i32** %tmp2		; <i32*> [#uses=1]
 	store i32* %tmp.upgrd.5, i32** %tmp.upgrd.4
-	%tmp3 = getelementptr %struct.Val* %tmp, i32 0, i32 1		; <i32*> [#uses=1]
-	%tmp4 = getelementptr %struct.Val* %tmp1, i32 0, i32 1		; <i32*> [#uses=1]
-	%tmp.upgrd.6 = load i32* %tmp4		; <i32> [#uses=1]
+	%tmp3 = getelementptr %struct.Val, %struct.Val* %tmp, i32 0, i32 1		; <i32*> [#uses=1]
+	%tmp4 = getelementptr %struct.Val, %struct.Val* %tmp1, i32 0, i32 1		; <i32*> [#uses=1]
+	%tmp.upgrd.6 = load i32, i32* %tmp4		; <i32> [#uses=1]
 	store i32 %tmp.upgrd.6, i32* %tmp3
 	%tmp7 = bitcast %struct.Val* %tmp to { i64 }*		; <{ i64 }*> [#uses=1]
-	%tmp8 = getelementptr { i64 }* %tmp7, i32 0, i32 0		; <i64*> [#uses=1]
-	%tmp9 = load i64* %tmp8		; <i64> [#uses=1]
+	%tmp8 = getelementptr { i64 }, { i64 }* %tmp7, i32 0, i32 0		; <i64*> [#uses=1]
+	%tmp9 = load i64, i64* %tmp8		; <i64> [#uses=1]
 	call void @_Z3bar3ValS_( i64 %Op.0, i64 %tmp9 )
 	ret void
 }
diff --git a/test/Transforms/ScalarRepl/vector_memcpy.ll b/test/Transforms/ScalarRepl/vector_memcpy.ll
index dfba9e2c8074..031ad5e38ca7 100644
--- a/test/Transforms/ScalarRepl/vector_memcpy.ll
+++ b/test/Transforms/ScalarRepl/vector_memcpy.ll
@@ -10,7 +10,7 @@ define <16 x float> @foo(<16 x float> %A) nounwind {
 	%s = bitcast <16 x float>* %tmp to i8*
 	%s2 = bitcast <16 x float>* %tmp2 to i8*
 	call void @llvm.memcpy.p0i8.p0i8.i64(i8* %s2, i8* %s, i64 64, i32 16, i1 false)
-	%R = load <16 x float>* %tmp2
+	%R = load <16 x float>, <16 x float>* %tmp2
 	ret <16 x float> %R
 }
 
@@ -20,7 +20,7 @@ define <16 x float> @foo2(<16 x float> %A) nounwind {
 	%s2 = bitcast <16 x float>* %tmp2 to i8*
 	call void @llvm.memset.p0i8.i64(i8* %s2, i8 0, i64 64, i32 16, i1 false)
 	
-	%R = load <16 x float>* %tmp2
+	%R = load <16 x float>, <16 x float>* %tmp2
 	ret <16 x float> %R
 }
 
diff --git a/test/Transforms/ScalarRepl/vector_promote.ll b/test/Transforms/ScalarRepl/vector_promote.ll
index 8ca1ed5005b3..3c2377fc0f28 100644
--- a/test/Transforms/ScalarRepl/vector_promote.ll
+++ b/test/Transforms/ScalarRepl/vector_promote.ll
@@ -5,18 +5,18 @@ target triple = "x86_64-apple-darwin10.0.0"
 define void @test1(<4 x float>* %F, float %f) {
 entry:
 	%G = alloca <4 x float>, align 16		; <<4 x float>*> [#uses=3]
-	%tmp = load <4 x float>* %F		; <<4 x float>> [#uses=2]
+	%tmp = load <4 x float>, <4 x float>* %F		; <<4 x float>> [#uses=2]
 	%tmp3 = fadd <4 x float> %tmp, %tmp		; <<4 x float>> [#uses=1]
 	store <4 x float> %tmp3, <4 x float>* %G
-	%G.upgrd.1 = getelementptr <4 x float>* %G, i32 0, i32 0		; <float*> [#uses=1]
+	%G.upgrd.1 = getelementptr <4 x float>, <4 x float>* %G, i32 0, i32 0		; <float*> [#uses=1]
 	store float %f, float* %G.upgrd.1
-	%tmp4 = load <4 x float>* %G		; <<4 x float>> [#uses=2]
+	%tmp4 = load <4 x float>, <4 x float>* %G		; <<4 x float>> [#uses=2]
 	%tmp6 = fadd <4 x float> %tmp4, %tmp4		; <<4 x float>> [#uses=1]
 	store <4 x float> %tmp6, <4 x float>* %F
 	ret void
 ; CHECK-LABEL: @test1(
 ; CHECK-NOT: alloca
-; CHECK: %tmp = load <4 x float>* %F
+; CHECK: %tmp = load <4 x float>, <4 x float>* %F
 ; CHECK: fadd <4 x float> %tmp, %tmp
 ; CHECK-NEXT: insertelement <4 x float> %tmp3, float %f, i32 0
 }
@@ -24,18 +24,18 @@ entry:
 define void @test2(<4 x float>* %F, float %f) {
 entry:
 	%G = alloca <4 x float>, align 16		; <<4 x float>*> [#uses=3]
-	%tmp = load <4 x float>* %F		; <<4 x float>> [#uses=2]
+	%tmp = load <4 x float>, <4 x float>* %F		; <<4 x float>> [#uses=2]
 	%tmp3 = fadd <4 x float> %tmp, %tmp		; <<4 x float>> [#uses=1]
 	store <4 x float> %tmp3, <4 x float>* %G
-	%tmp.upgrd.2 = getelementptr <4 x float>* %G, i32 0, i32 2		; <float*> [#uses=1]
+	%tmp.upgrd.2 = getelementptr <4 x float>, <4 x float>* %G, i32 0, i32 2		; <float*> [#uses=1]
 	store float %f, float* %tmp.upgrd.2
-	%tmp4 = load <4 x float>* %G		; <<4 x float>> [#uses=2]
+	%tmp4 = load <4 x float>, <4 x float>* %G		; <<4 x float>> [#uses=2]
 	%tmp6 = fadd <4 x float> %tmp4, %tmp4		; <<4 x float>> [#uses=1]
 	store <4 x float> %tmp6, <4 x float>* %F
 	ret void
 ; CHECK-LABEL: @test2(
 ; CHECK-NOT: alloca
-; CHECK: %tmp = load <4 x float>* %F
+; CHECK: %tmp = load <4 x float>, <4 x float>* %F
 ; CHECK: fadd <4 x float> %tmp, %tmp
 ; CHECK-NEXT: insertelement <4 x float> %tmp3, float %f, i32 2
 }
@@ -43,16 +43,16 @@ entry:
 define void @test3(<4 x float>* %F, float* %f) {
 entry:
 	%G = alloca <4 x float>, align 16		; <<4 x float>*> [#uses=2]
-	%tmp = load <4 x float>* %F		; <<4 x float>> [#uses=2]
+	%tmp = load <4 x float>, <4 x float>* %F		; <<4 x float>> [#uses=2]
 	%tmp3 = fadd <4 x float> %tmp, %tmp		; <<4 x float>> [#uses=1]
 	store <4 x float> %tmp3, <4 x float>* %G
-	%tmp.upgrd.3 = getelementptr <4 x float>* %G, i32 0, i32 2		; <float*> [#uses=1]
-	%tmp.upgrd.4 = load float* %tmp.upgrd.3		; <float> [#uses=1]
+	%tmp.upgrd.3 = getelementptr <4 x float>, <4 x float>* %G, i32 0, i32 2		; <float*> [#uses=1]
+	%tmp.upgrd.4 = load float, float* %tmp.upgrd.3		; <float> [#uses=1]
 	store float %tmp.upgrd.4, float* %f
 	ret void
 ; CHECK-LABEL: @test3(
 ; CHECK-NOT: alloca
-; CHECK: %tmp = load <4 x float>* %F
+; CHECK: %tmp = load <4 x float>, <4 x float>* %F
 ; CHECK: fadd <4 x float> %tmp, %tmp
 ; CHECK-NEXT: extractelement <4 x float> %tmp3, i32 2
 }
@@ -60,26 +60,26 @@ entry:
 define void @test4(<4 x float>* %F, float* %f) {
 entry:
 	%G = alloca <4 x float>, align 16		; <<4 x float>*> [#uses=2]
-	%tmp = load <4 x float>* %F		; <<4 x float>> [#uses=2]
+	%tmp = load <4 x float>, <4 x float>* %F		; <<4 x float>> [#uses=2]
 	%tmp3 = fadd <4 x float> %tmp, %tmp		; <<4 x float>> [#uses=1]
 	store <4 x float> %tmp3, <4 x float>* %G
-	%G.upgrd.5 = getelementptr <4 x float>* %G, i32 0, i32 0		; <float*> [#uses=1]
-	%tmp.upgrd.6 = load float* %G.upgrd.5		; <float> [#uses=1]
+	%G.upgrd.5 = getelementptr <4 x float>, <4 x float>* %G, i32 0, i32 0		; <float*> [#uses=1]
+	%tmp.upgrd.6 = load float, float* %G.upgrd.5		; <float> [#uses=1]
 	store float %tmp.upgrd.6, float* %f
 	ret void
 ; CHECK-LABEL: @test4(
 ; CHECK-NOT: alloca
-; CHECK: %tmp = load <4 x float>* %F
+; CHECK: %tmp = load <4 x float>, <4 x float>* %F
 ; CHECK: fadd <4 x float> %tmp, %tmp
 ; CHECK-NEXT: extractelement <4 x float> %tmp3, i32 0
 }
 
 define i32 @test5(float %X) {  ;; should turn into bitcast.
 	%X_addr = alloca [4 x float]
-        %X1 = getelementptr [4 x float]* %X_addr, i32 0, i32 2
+        %X1 = getelementptr [4 x float], [4 x float]* %X_addr, i32 0, i32 2
 	store float %X, float* %X1
 	%a = bitcast float* %X1 to i32*
-	%tmp = load i32* %a
+	%tmp = load i32, i32* %a
 	ret i32 %tmp
 ; CHECK-LABEL: @test5(
 ; CHECK-NEXT: bitcast float %X to i32
@@ -90,7 +90,7 @@ define i64 @test6(<2 x float> %X) {
 	%X_addr = alloca <2 x float>
         store <2 x float> %X, <2 x float>* %X_addr
 	%P = bitcast <2 x float>* %X_addr to i64*
-	%tmp = load i64* %P
+	%tmp = load i64, i64* %P
 	ret i64 %tmp
 ; CHECK-LABEL: @test6(
 ; CHECK: bitcast <2 x float> %X to i64
@@ -104,7 +104,7 @@ entry:
   %memtmp = alloca %struct.test7, align 16
   %0 = bitcast %struct.test7* %memtmp to <4 x i32>*
   store <4 x i32> zeroinitializer, <4 x i32>* %0, align 16
-  %1 = getelementptr inbounds %struct.test7* %memtmp, i64 0, i32 0, i64 5
+  %1 = getelementptr inbounds %struct.test7, %struct.test7* %memtmp, i64 0, i32 0, i64 5
   store i32 0, i32* %1, align 4
   ret void
 ; CHECK-LABEL: @test7(
@@ -121,14 +121,14 @@ entry:
   %__a = alloca <1 x i64>, align 8
   %tmp = alloca <1 x i64>, align 8
   store <1 x i64> %a, <1 x i64>* %a.addr, align 8
-  %0 = load <1 x i64>* %a.addr, align 8
+  %0 = load <1 x i64>, <1 x i64>* %a.addr, align 8
   store <1 x i64> %0, <1 x i64>* %__a, align 8
-  %1 = load <1 x i64>* %__a, align 8
+  %1 = load <1 x i64>, <1 x i64>* %__a, align 8
   %2 = bitcast <1 x i64> %1 to <8 x i8>
   %3 = bitcast <8 x i8> %2 to <1 x i64>
   %vshl_n = shl <1 x i64> %3, <i64 4>
   store <1 x i64> %vshl_n, <1 x i64>* %tmp
-  %4 = load <1 x i64>* %tmp
+  %4 = load <1 x i64>, <1 x i64>* %tmp
   ret <1 x i64> %4
 ; CHECK-LABEL: @test8(
 ; CHECK-NOT: alloca
diff --git a/test/Transforms/ScalarRepl/vectors-with-mismatched-elements.ll b/test/Transforms/ScalarRepl/vectors-with-mismatched-elements.ll
index c3fbdf5f8632..154883122df6 100644
--- a/test/Transforms/ScalarRepl/vectors-with-mismatched-elements.ll
+++ b/test/Transforms/ScalarRepl/vectors-with-mismatched-elements.ll
@@ -18,10 +18,10 @@ define <2 x i64> @foo() nounwind {
 entry:
   %retval = alloca <3 x i32>, align 16
   %z = alloca <4 x i32>, align 16
-  %tmp = load <4 x i32>* %z
+  %tmp = load <4 x i32>, <4 x i32>* %z
   %tmp1 = shufflevector <4 x i32> %tmp, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
   store <3 x i32> %tmp1, <3 x i32>* %retval
   %0 = bitcast <3 x i32>* %retval to <2 x i64>*
-  %1 = load <2 x i64>* %0, align 1
+  %1 = load <2 x i64>, <2 x i64>* %0, align 1
   ret <2 x i64> %1
 }
diff --git a/test/Transforms/ScalarRepl/volatile.ll b/test/Transforms/ScalarRepl/volatile.ll
index d506cdfbd87a..2a600b3b2797 100644
--- a/test/Transforms/ScalarRepl/volatile.ll
+++ b/test/Transforms/ScalarRepl/volatile.ll
@@ -2,12 +2,12 @@
 
 define i32 @voltest(i32 %T) {
 	%A = alloca {i32, i32}
-	%B = getelementptr {i32,i32}* %A, i32 0, i32 0
+	%B = getelementptr {i32,i32}, {i32,i32}* %A, i32 0, i32 0
 	store volatile i32 %T, i32* %B
 ; CHECK: store volatile
 
-	%C = getelementptr {i32,i32}* %A, i32 0, i32 1
-	%X = load volatile i32* %C
+	%C = getelementptr {i32,i32}, {i32,i32}* %A, i32 0, i32 1
+	%X = load volatile i32, i32* %C
 ; CHECK: load volatile
 	ret i32 %X
 }
diff --git a/test/Transforms/Scalarizer/basic.ll b/test/Transforms/Scalarizer/basic.ll
index a94cf9f61142..150eb7d43c46 100644
--- a/test/Transforms/Scalarizer/basic.ll
+++ b/test/Transforms/Scalarizer/basic.ll
@@ -19,15 +19,15 @@ define void @f1(<4 x float> %init, <4 x float> *%base, i32 %count) {
 ; CHECK:   %acc.i2 = phi float [ %init.i2, %entry ], [ %sel.i2, %loop ]
 ; CHECK:   %acc.i3 = phi float [ %init.i3, %entry ], [ %sel.i3, %loop ]
 ; CHECK:   %nexti = sub i32 %i, 1
-; CHECK:   %ptr = getelementptr <4 x float>* %base, i32 %i
+; CHECK:   %ptr = getelementptr <4 x float>, <4 x float>* %base, i32 %i
 ; CHECK:   %ptr.i0 = bitcast <4 x float>* %ptr to float*
-; CHECK:   %val.i0 = load float* %ptr.i0, align 16
-; CHECK:   %ptr.i1 = getelementptr float* %ptr.i0, i32 1
-; CHECK:   %val.i1 = load float* %ptr.i1, align 4
-; CHECK:   %ptr.i2 = getelementptr float* %ptr.i0, i32 2
-; CHECK:   %val.i2 = load float* %ptr.i2, align 8
-; CHECK:   %ptr.i3 = getelementptr float* %ptr.i0, i32 3
-; CHECK:   %val.i3 = load float* %ptr.i3, align 4
+; CHECK:   %val.i0 = load float, float* %ptr.i0, align 16
+; CHECK:   %ptr.i1 = getelementptr float, float* %ptr.i0, i32 1
+; CHECK:   %val.i1 = load float, float* %ptr.i1, align 4
+; CHECK:   %ptr.i2 = getelementptr float, float* %ptr.i0, i32 2
+; CHECK:   %val.i2 = load float, float* %ptr.i2, align 8
+; CHECK:   %ptr.i3 = getelementptr float, float* %ptr.i0, i32 3
+; CHECK:   %val.i3 = load float, float* %ptr.i3, align 4
 ; CHECK:   %add.i0 = fadd float %val.i0, %val.i2
 ; CHECK:   %add.i1 = fadd float %val.i1, %val.i3
 ; CHECK:   %add.i2 = fadd float %acc.i0, %acc.i2
@@ -65,8 +65,8 @@ loop:
   %acc = phi <4 x float> [ %init, %entry ], [ %sel, %loop ]
   %nexti = sub i32 %i, 1
 
-  %ptr = getelementptr <4 x float> *%base, i32 %i
-  %val = load <4 x float> *%ptr
+  %ptr = getelementptr <4 x float>, <4 x float> *%base, i32 %i
+  %val = load <4 x float> , <4 x float> *%ptr
   %dval = bitcast <4 x float> %val to <2 x double>
   %dacc = bitcast <4 x float> %acc to <2 x double>
   %shuffle1 = shufflevector <2 x double> %dval, <2 x double> %dacc,
@@ -105,15 +105,15 @@ define void @f2(<4 x i32> %init, <4 x i8> *%base, i32 %count) {
 ; CHECK:   %acc.i2 = phi i32 [ %init.i2, %entry ], [ %sel.i2, %loop ]
 ; CHECK:   %acc.i3 = phi i32 [ %init.i3, %entry ], [ %sel.i3, %loop ]
 ; CHECK:   %nexti = sub i32 %i, 1
-; CHECK:   %ptr = getelementptr <4 x i8>* %base, i32 %i
+; CHECK:   %ptr = getelementptr <4 x i8>, <4 x i8>* %base, i32 %i
 ; CHECK:   %ptr.i0 = bitcast <4 x i8>* %ptr to i8*
-; CHECK:   %val.i0 = load i8* %ptr.i0, align 4
-; CHECK:   %ptr.i1 = getelementptr i8* %ptr.i0, i32 1
-; CHECK:   %val.i1 = load i8* %ptr.i1, align 1
-; CHECK:   %ptr.i2 = getelementptr i8* %ptr.i0, i32 2
-; CHECK:   %val.i2 = load i8* %ptr.i2, align 2
-; CHECK:   %ptr.i3 = getelementptr i8* %ptr.i0, i32 3
-; CHECK:   %val.i3 = load i8* %ptr.i3, align 1
+; CHECK:   %val.i0 = load i8, i8* %ptr.i0, align 4
+; CHECK:   %ptr.i1 = getelementptr i8, i8* %ptr.i0, i32 1
+; CHECK:   %val.i1 = load i8, i8* %ptr.i1, align 1
+; CHECK:   %ptr.i2 = getelementptr i8, i8* %ptr.i0, i32 2
+; CHECK:   %val.i2 = load i8, i8* %ptr.i2, align 2
+; CHECK:   %ptr.i3 = getelementptr i8, i8* %ptr.i0, i32 3
+; CHECK:   %val.i3 = load i8, i8* %ptr.i3, align 1
 ; CHECK:   %ext.i0 = sext i8 %val.i0 to i32
 ; CHECK:   %ext.i1 = sext i8 %val.i1 to i32
 ; CHECK:   %ext.i2 = sext i8 %val.i2 to i32
@@ -150,8 +150,8 @@ loop:
   %acc = phi <4 x i32> [ %init, %entry ], [ %sel, %loop ]
   %nexti = sub i32 %i, 1
 
-  %ptr = getelementptr <4 x i8> *%base, i32 %i
-  %val = load <4 x i8> *%ptr
+  %ptr = getelementptr <4 x i8>, <4 x i8> *%base, i32 %i
+  %val = load <4 x i8> , <4 x i8> *%ptr
   %ext = sext <4 x i8> %val to <4 x i32>
   %add = add <4 x i32> %ext, %acc
   %cmp = icmp slt <4 x i32> %add, <i32 -10, i32 -11, i32 -12, i32 -13>
@@ -172,16 +172,16 @@ exit:
 ; Check that !tbaa information is preserved.
 define void @f3(<4 x i32> *%src, <4 x i32> *%dst) {
 ; CHECK-LABEL: @f3(
-; CHECK: %val.i0 = load i32* %src.i0, align 16, !tbaa ![[TAG:[0-9]*]]
-; CHECK: %val.i1 = load i32* %src.i1, align 4, !tbaa ![[TAG]]
-; CHECK: %val.i2 = load i32* %src.i2, align 8, !tbaa ![[TAG]]
-; CHECK: %val.i3 = load i32* %src.i3, align 4, !tbaa ![[TAG]]
+; CHECK: %val.i0 = load i32, i32* %src.i0, align 16, !tbaa ![[TAG:[0-9]*]]
+; CHECK: %val.i1 = load i32, i32* %src.i1, align 4, !tbaa ![[TAG]]
+; CHECK: %val.i2 = load i32, i32* %src.i2, align 8, !tbaa ![[TAG]]
+; CHECK: %val.i3 = load i32, i32* %src.i3, align 4, !tbaa ![[TAG]]
 ; CHECK: store i32 %add.i0, i32* %dst.i0, align 16, !tbaa ![[TAG:[0-9]*]]
 ; CHECK: store i32 %add.i1, i32* %dst.i1, align 4, !tbaa ![[TAG]]
 ; CHECK: store i32 %add.i2, i32* %dst.i2, align 8, !tbaa ![[TAG]]
 ; CHECK: store i32 %add.i3, i32* %dst.i3, align 4, !tbaa ![[TAG]]
 ; CHECK: ret void
-  %val = load <4 x i32> *%src, !tbaa !1
+  %val = load <4 x i32> , <4 x i32> *%src, !tbaa !1
   %add = add <4 x i32> %val, %val
   store <4 x i32> %add, <4 x i32> *%dst, !tbaa !2
   ret void
@@ -190,16 +190,16 @@ define void @f3(<4 x i32> *%src, <4 x i32> *%dst) {
 ; Check that !tbaa.struct information is preserved.
 define void @f4(<4 x i32> *%src, <4 x i32> *%dst) {
 ; CHECK-LABEL: @f4(
-; CHECK: %val.i0 = load i32* %src.i0, align 16, !tbaa.struct ![[TAG:[0-9]*]]
-; CHECK: %val.i1 = load i32* %src.i1, align 4, !tbaa.struct ![[TAG]]
-; CHECK: %val.i2 = load i32* %src.i2, align 8, !tbaa.struct ![[TAG]]
-; CHECK: %val.i3 = load i32* %src.i3, align 4, !tbaa.struct ![[TAG]]
+; CHECK: %val.i0 = load i32, i32* %src.i0, align 16, !tbaa.struct ![[TAG:[0-9]*]]
+; CHECK: %val.i1 = load i32, i32* %src.i1, align 4, !tbaa.struct ![[TAG]]
+; CHECK: %val.i2 = load i32, i32* %src.i2, align 8, !tbaa.struct ![[TAG]]
+; CHECK: %val.i3 = load i32, i32* %src.i3, align 4, !tbaa.struct ![[TAG]]
 ; CHECK: store i32 %add.i0, i32* %dst.i0, align 16, !tbaa.struct ![[TAG]]
 ; CHECK: store i32 %add.i1, i32* %dst.i1, align 4, !tbaa.struct ![[TAG]]
 ; CHECK: store i32 %add.i2, i32* %dst.i2, align 8, !tbaa.struct ![[TAG]]
 ; CHECK: store i32 %add.i3, i32* %dst.i3, align 4, !tbaa.struct ![[TAG]]
 ; CHECK: ret void
-  %val = load <4 x i32> *%src, !tbaa.struct !5
+  %val = load <4 x i32> , <4 x i32> *%src, !tbaa.struct !5
   %add = add <4 x i32> %val, %val
   store <4 x i32> %add, <4 x i32> *%dst, !tbaa.struct !5
   ret void
@@ -208,10 +208,10 @@ define void @f4(<4 x i32> *%src, <4 x i32> *%dst) {
 ; Check that llvm.mem.parallel_loop_access information is preserved.
 define void @f5(i32 %count, <4 x i32> *%src, <4 x i32> *%dst) {
 ; CHECK-LABEL: @f5(
-; CHECK: %val.i0 = load i32* %this_src.i0, align 16, !llvm.mem.parallel_loop_access ![[TAG:[0-9]*]]
-; CHECK: %val.i1 = load i32* %this_src.i1, align 4, !llvm.mem.parallel_loop_access ![[TAG]]
-; CHECK: %val.i2 = load i32* %this_src.i2, align 8, !llvm.mem.parallel_loop_access ![[TAG]]
-; CHECK: %val.i3 = load i32* %this_src.i3, align 4, !llvm.mem.parallel_loop_access ![[TAG]]
+; CHECK: %val.i0 = load i32, i32* %this_src.i0, align 16, !llvm.mem.parallel_loop_access ![[TAG:[0-9]*]]
+; CHECK: %val.i1 = load i32, i32* %this_src.i1, align 4, !llvm.mem.parallel_loop_access ![[TAG]]
+; CHECK: %val.i2 = load i32, i32* %this_src.i2, align 8, !llvm.mem.parallel_loop_access ![[TAG]]
+; CHECK: %val.i3 = load i32, i32* %this_src.i3, align 4, !llvm.mem.parallel_loop_access ![[TAG]]
 ; CHECK: store i32 %add.i0, i32* %this_dst.i0, align 16, !llvm.mem.parallel_loop_access ![[TAG]]
 ; CHECK: store i32 %add.i1, i32* %this_dst.i1, align 4, !llvm.mem.parallel_loop_access ![[TAG]]
 ; CHECK: store i32 %add.i2, i32* %this_dst.i2, align 8, !llvm.mem.parallel_loop_access ![[TAG]]
@@ -222,9 +222,9 @@ entry:
 
 loop:
   %index = phi i32 [ 0, %entry ], [ %next_index, %loop ]
-  %this_src = getelementptr <4 x i32> *%src, i32 %index
-  %this_dst = getelementptr <4 x i32> *%dst, i32 %index
-  %val = load <4 x i32> *%this_src, !llvm.mem.parallel_loop_access !3
+  %this_src = getelementptr <4 x i32>, <4 x i32> *%src, i32 %index
+  %this_dst = getelementptr <4 x i32>, <4 x i32> *%dst, i32 %index
+  %val = load <4 x i32> , <4 x i32> *%this_src, !llvm.mem.parallel_loop_access !3
   %add = add <4 x i32> %val, %val
   store <4 x i32> %add, <4 x i32> *%this_dst, !llvm.mem.parallel_loop_access !3
   %next_index = add i32 %index, -1
@@ -261,7 +261,7 @@ define void @f7(<4 x i32> *%src, <4 x i32> *%dst) {
 ; CHECK-LABEL: @f7(
 ; CHECK-NOT: !foo
 ; CHECK: ret void
-  %val = load <4 x i32> *%src, !foo !5
+  %val = load <4 x i32> , <4 x i32> *%src, !foo !5
   %add = add <4 x i32> %val, %val
   store <4 x i32> %add, <4 x i32> *%dst, !foo !5
   ret void
@@ -272,18 +272,18 @@ define void @f8(<4 x float *> *%dest, <4 x float *> %ptr0, <4 x i32> %i0,
                 float *%other) {
 ; CHECK-LABEL: @f8(
 ; CHECK: %dest.i0 = bitcast <4 x float*>* %dest to float**
-; CHECK: %dest.i1 = getelementptr float** %dest.i0, i32 1
-; CHECK: %dest.i2 = getelementptr float** %dest.i0, i32 2
-; CHECK: %dest.i3 = getelementptr float** %dest.i0, i32 3
+; CHECK: %dest.i1 = getelementptr float*, float** %dest.i0, i32 1
+; CHECK: %dest.i2 = getelementptr float*, float** %dest.i0, i32 2
+; CHECK: %dest.i3 = getelementptr float*, float** %dest.i0, i32 3
 ; CHECK: %i0.i1 = extractelement <4 x i32> %i0, i32 1
 ; CHECK: %i0.i3 = extractelement <4 x i32> %i0, i32 3
 ; CHECK: %ptr0.i0 = extractelement <4 x float*> %ptr0, i32 0
-; CHECK: %val.i0 = getelementptr float* %ptr0.i0, i32 100
-; CHECK: %val.i1 = getelementptr float* %other, i32 %i0.i1
+; CHECK: %val.i0 = getelementptr float, float* %ptr0.i0, i32 100
+; CHECK: %val.i1 = getelementptr float, float* %other, i32 %i0.i1
 ; CHECK: %ptr0.i2 = extractelement <4 x float*> %ptr0, i32 2
-; CHECK: %val.i2 = getelementptr float* %ptr0.i2, i32 100
+; CHECK: %val.i2 = getelementptr float, float* %ptr0.i2, i32 100
 ; CHECK: %ptr0.i3 = extractelement <4 x float*> %ptr0, i32 3
-; CHECK: %val.i3 = getelementptr float* %ptr0.i3, i32 %i0.i3
+; CHECK: %val.i3 = getelementptr float, float* %ptr0.i3, i32 %i0.i3
 ; CHECK: store float* %val.i0, float** %dest.i0, align 32
 ; CHECK: store float* %val.i1, float** %dest.i1, align 8
 ; CHECK: store float* %val.i2, float** %dest.i2, align 16
@@ -292,7 +292,7 @@ define void @f8(<4 x float *> *%dest, <4 x float *> %ptr0, <4 x i32> %i0,
   %i1 = insertelement <4 x i32> %i0, i32 100, i32 0
   %i2 = insertelement <4 x i32> %i1, i32 100, i32 2
   %ptr1 = insertelement <4 x float *> %ptr0, float *%other, i32 1
-  %val = getelementptr <4 x float *> %ptr1, <4 x i32> %i2
+  %val = getelementptr float, <4 x float *> %ptr1, <4 x i32> %i2
   store <4 x float *> %val, <4 x float *> *%dest
   ret void
 }
@@ -301,23 +301,23 @@ define void @f8(<4 x float *> *%dest, <4 x float *> %ptr0, <4 x i32> %i0,
 define void @f9(<4 x float> *%dest, <4 x float> *%src) {
 ; CHECK: @f9(
 ; CHECK: %dest.i0 = bitcast <4 x float>* %dest to float*
-; CHECK: %dest.i1 = getelementptr float* %dest.i0, i32 1
-; CHECK: %dest.i2 = getelementptr float* %dest.i0, i32 2
-; CHECK: %dest.i3 = getelementptr float* %dest.i0, i32 3
+; CHECK: %dest.i1 = getelementptr float, float* %dest.i0, i32 1
+; CHECK: %dest.i2 = getelementptr float, float* %dest.i0, i32 2
+; CHECK: %dest.i3 = getelementptr float, float* %dest.i0, i32 3
 ; CHECK: %src.i0 = bitcast <4 x float>* %src to float*
-; CHECK: %val.i0 = load float* %src.i0, align 4
-; CHECK: %src.i1 = getelementptr float* %src.i0, i32 1
-; CHECK: %val.i1 = load float* %src.i1, align 4
-; CHECK: %src.i2 = getelementptr float* %src.i0, i32 2
-; CHECK: %val.i2 = load float* %src.i2, align 4
-; CHECK: %src.i3 = getelementptr float* %src.i0, i32 3
-; CHECK: %val.i3 = load float* %src.i3, align 4
+; CHECK: %val.i0 = load float, float* %src.i0, align 4
+; CHECK: %src.i1 = getelementptr float, float* %src.i0, i32 1
+; CHECK: %val.i1 = load float, float* %src.i1, align 4
+; CHECK: %src.i2 = getelementptr float, float* %src.i0, i32 2
+; CHECK: %val.i2 = load float, float* %src.i2, align 4
+; CHECK: %src.i3 = getelementptr float, float* %src.i0, i32 3
+; CHECK: %val.i3 = load float, float* %src.i3, align 4
 ; CHECK: store float %val.i0, float* %dest.i0, align 8
 ; CHECK: store float %val.i1, float* %dest.i1, align 4
 ; CHECK: store float %val.i2, float* %dest.i2, align 8
 ; CHECK: store float %val.i3, float* %dest.i3, align 4
 ; CHECK: ret void
-  %val = load <4 x float> *%src, align 4
+  %val = load <4 x float> , <4 x float> *%src, align 4
   store <4 x float> %val, <4 x float> *%dest, align 8
   ret void
 }
@@ -326,23 +326,23 @@ define void @f9(<4 x float> *%dest, <4 x float> *%src) {
 define void @f10(<4 x float> *%dest, <4 x float> *%src) {
 ; CHECK: @f10(
 ; CHECK: %dest.i0 = bitcast <4 x float>* %dest to float*
-; CHECK: %dest.i1 = getelementptr float* %dest.i0, i32 1
-; CHECK: %dest.i2 = getelementptr float* %dest.i0, i32 2
-; CHECK: %dest.i3 = getelementptr float* %dest.i0, i32 3
+; CHECK: %dest.i1 = getelementptr float, float* %dest.i0, i32 1
+; CHECK: %dest.i2 = getelementptr float, float* %dest.i0, i32 2
+; CHECK: %dest.i3 = getelementptr float, float* %dest.i0, i32 3
 ; CHECK: %src.i0 = bitcast <4 x float>* %src to float*
-; CHECK: %val.i0 = load float* %src.i0, align 1
-; CHECK: %src.i1 = getelementptr float* %src.i0, i32 1
-; CHECK: %val.i1 = load float* %src.i1, align 1
-; CHECK: %src.i2 = getelementptr float* %src.i0, i32 2
-; CHECK: %val.i2 = load float* %src.i2, align 1
-; CHECK: %src.i3 = getelementptr float* %src.i0, i32 3
-; CHECK: %val.i3 = load float* %src.i3, align 1
+; CHECK: %val.i0 = load float, float* %src.i0, align 1
+; CHECK: %src.i1 = getelementptr float, float* %src.i0, i32 1
+; CHECK: %val.i1 = load float, float* %src.i1, align 1
+; CHECK: %src.i2 = getelementptr float, float* %src.i0, i32 2
+; CHECK: %val.i2 = load float, float* %src.i2, align 1
+; CHECK: %src.i3 = getelementptr float, float* %src.i0, i32 3
+; CHECK: %val.i3 = load float, float* %src.i3, align 1
 ; CHECK: store float %val.i0, float* %dest.i0, align 2
 ; CHECK: store float %val.i1, float* %dest.i1, align 2
 ; CHECK: store float %val.i2, float* %dest.i2, align 2
 ; CHECK: store float %val.i3, float* %dest.i3, align 2
 ; CHECK: ret void
-  %val = load <4 x float> *%src, align 1
+  %val = load <4 x float> , <4 x float> *%src, align 1
   store <4 x float> %val, <4 x float> *%dest, align 2
   ret void
 }
@@ -350,13 +350,13 @@ define void @f10(<4 x float> *%dest, <4 x float> *%src) {
 ; Test that sub-byte loads aren't scalarized.
 define void @f11(<32 x i1> *%dest, <32 x i1> *%src0) {
 ; CHECK: @f11(
-; CHECK: %val0 = load <32 x i1>* %src0
-; CHECK: %val1 = load <32 x i1>* %src1
+; CHECK: %val0 = load <32 x i1>, <32 x i1>* %src0
+; CHECK: %val1 = load <32 x i1>, <32 x i1>* %src1
 ; CHECK: store <32 x i1> %and, <32 x i1>* %dest
 ; CHECK: ret void
-  %src1 = getelementptr <32 x i1> *%src0, i32 1
-  %val0 = load <32 x i1> *%src0
-  %val1 = load <32 x i1> *%src1
+  %src1 = getelementptr <32 x i1>, <32 x i1> *%src0, i32 1
+  %val0 = load <32 x i1> , <32 x i1> *%src0
+  %val1 = load <32 x i1> , <32 x i1> *%src1
   %and = and <32 x i1> %val0, %val1
   store <32 x i1> %and, <32 x i1> *%dest
   ret void
@@ -375,7 +375,7 @@ define void @f12(<4 x i32> *%dest, <4 x i32> *%src, i32 %index) {
 ; CHECK-DAG: %val2.i2 = shl i32 3, %val1.i2
 ; CHECK-DAG: %val2.i3 = shl i32 4, %val1.i3
 ; CHECK: ret void
-  %val0 = load <4 x i32> *%src
+  %val0 = load <4 x i32> , <4 x i32> *%src
   %val1 = insertelement <4 x i32> %val0, i32 1, i32 %index
   %val2 = shl <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %val1
   store <4 x i32> %val2, <4 x i32> *%dest
@@ -387,27 +387,27 @@ define void @f13(<4 x float *> *%dest, <4 x [4 x float] *> %ptr, <4 x i32> %i,
                  float *%other) {
 ; CHECK-LABEL: @f13(
 ; CHECK: %dest.i0 = bitcast <4 x float*>* %dest to float**
-; CHECK: %dest.i1 = getelementptr float** %dest.i0, i32 1
-; CHECK: %dest.i2 = getelementptr float** %dest.i0, i32 2
-; CHECK: %dest.i3 = getelementptr float** %dest.i0, i32 3
+; CHECK: %dest.i1 = getelementptr float*, float** %dest.i0, i32 1
+; CHECK: %dest.i2 = getelementptr float*, float** %dest.i0, i32 2
+; CHECK: %dest.i3 = getelementptr float*, float** %dest.i0, i32 3
 ; CHECK: %i.i0 = extractelement <4 x i32> %i, i32 0
 ; CHECK: %ptr.i0 = extractelement <4 x [4 x float]*> %ptr, i32 0
-; CHECK: %val.i0 = getelementptr inbounds [4 x float]* %ptr.i0, i32 0, i32 %i.i0
+; CHECK: %val.i0 = getelementptr inbounds [4 x float], [4 x float]* %ptr.i0, i32 0, i32 %i.i0
 ; CHECK: %i.i1 = extractelement <4 x i32> %i, i32 1
 ; CHECK: %ptr.i1 = extractelement <4 x [4 x float]*> %ptr, i32 1
-; CHECK: %val.i1 = getelementptr inbounds [4 x float]* %ptr.i1, i32 1, i32 %i.i1
+; CHECK: %val.i1 = getelementptr inbounds [4 x float], [4 x float]* %ptr.i1, i32 1, i32 %i.i1
 ; CHECK: %i.i2 = extractelement <4 x i32> %i, i32 2
 ; CHECK: %ptr.i2 = extractelement <4 x [4 x float]*> %ptr, i32 2
-; CHECK: %val.i2 = getelementptr inbounds [4 x float]* %ptr.i2, i32 2, i32 %i.i2
+; CHECK: %val.i2 = getelementptr inbounds [4 x float], [4 x float]* %ptr.i2, i32 2, i32 %i.i2
 ; CHECK: %i.i3 = extractelement <4 x i32> %i, i32 3
 ; CHECK: %ptr.i3 = extractelement <4 x [4 x float]*> %ptr, i32 3
-; CHECK: %val.i3 = getelementptr inbounds [4 x float]* %ptr.i3, i32 3, i32 %i.i3
+; CHECK: %val.i3 = getelementptr inbounds [4 x float], [4 x float]* %ptr.i3, i32 3, i32 %i.i3
 ; CHECK: store float* %val.i0, float** %dest.i0, align 32
 ; CHECK: store float* %val.i1, float** %dest.i1, align 8
 ; CHECK: store float* %val.i2, float** %dest.i2, align 16
 ; CHECK: store float* %val.i3, float** %dest.i3, align 8
 ; CHECK: ret void
-  %val = getelementptr inbounds <4 x [4 x float] *> %ptr,
+  %val = getelementptr inbounds [4 x float], <4 x [4 x float] *> %ptr,
                                 <4 x i32> <i32 0, i32 1, i32 2, i32 3>,
                                 <4 x i32> %i
   store <4 x float *> %val, <4 x float *> *%dest
diff --git a/test/Transforms/Scalarizer/dbginfo.ll b/test/Transforms/Scalarizer/dbginfo.ll
index ed65aaace2c4..3770a3e8c642 100644
--- a/test/Transforms/Scalarizer/dbginfo.ll
+++ b/test/Transforms/Scalarizer/dbginfo.ll
@@ -5,28 +5,28 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 define void @f1(<4 x i32>* nocapture %a, <4 x i32>* nocapture readonly %b, <4 x i32>* nocapture readonly %c) #0 {
 ; CHECK: @f1(
 ; CHECK: %a.i0 = bitcast <4 x i32>* %a to i32*
-; CHECK: %a.i1 = getelementptr i32* %a.i0, i32 1
-; CHECK: %a.i2 = getelementptr i32* %a.i0, i32 2
-; CHECK: %a.i3 = getelementptr i32* %a.i0, i32 3
+; CHECK: %a.i1 = getelementptr i32, i32* %a.i0, i32 1
+; CHECK: %a.i2 = getelementptr i32, i32* %a.i0, i32 2
+; CHECK: %a.i3 = getelementptr i32, i32* %a.i0, i32 3
 ; CHECK: %c.i0 = bitcast <4 x i32>* %c to i32*
-; CHECK: %c.i1 = getelementptr i32* %c.i0, i32 1
-; CHECK: %c.i2 = getelementptr i32* %c.i0, i32 2
-; CHECK: %c.i3 = getelementptr i32* %c.i0, i32 3
+; CHECK: %c.i1 = getelementptr i32, i32* %c.i0, i32 1
+; CHECK: %c.i2 = getelementptr i32, i32* %c.i0, i32 2
+; CHECK: %c.i3 = getelementptr i32, i32* %c.i0, i32 3
 ; CHECK: %b.i0 = bitcast <4 x i32>* %b to i32*
-; CHECK: %b.i1 = getelementptr i32* %b.i0, i32 1
-; CHECK: %b.i2 = getelementptr i32* %b.i0, i32 2
-; CHECK: %b.i3 = getelementptr i32* %b.i0, i32 3
+; CHECK: %b.i1 = getelementptr i32, i32* %b.i0, i32 1
+; CHECK: %b.i2 = getelementptr i32, i32* %b.i0, i32 2
+; CHECK: %b.i3 = getelementptr i32, i32* %b.i0, i32 3
 ; CHECK: tail call void @llvm.dbg.value(metadata <4 x i32>* %a, i64 0, metadata !{{[0-9]+}}, metadata {{.*}}), !dbg !{{[0-9]+}}
 ; CHECK: tail call void @llvm.dbg.value(metadata <4 x i32>* %b, i64 0, metadata !{{[0-9]+}}, metadata {{.*}}), !dbg !{{[0-9]+}}
 ; CHECK: tail call void @llvm.dbg.value(metadata <4 x i32>* %c, i64 0, metadata !{{[0-9]+}}, metadata {{.*}}), !dbg !{{[0-9]+}}
-; CHECK: %bval.i0 = load i32* %b.i0, align 16, !dbg ![[TAG1:[0-9]+]], !tbaa ![[TAG2:[0-9]+]]
-; CHECK: %bval.i1 = load i32* %b.i1, align 4, !dbg ![[TAG1]], !tbaa ![[TAG2]]
-; CHECK: %bval.i2 = load i32* %b.i2, align 8, !dbg ![[TAG1]], !tbaa ![[TAG2]]
-; CHECK: %bval.i3 = load i32* %b.i3, align 4, !dbg ![[TAG1]], !tbaa ![[TAG2]]
-; CHECK: %cval.i0 = load i32* %c.i0, align 16, !dbg ![[TAG1]], !tbaa ![[TAG2]]
-; CHECK: %cval.i1 = load i32* %c.i1, align 4, !dbg ![[TAG1]], !tbaa ![[TAG2]]
-; CHECK: %cval.i2 = load i32* %c.i2, align 8, !dbg ![[TAG1]], !tbaa ![[TAG2]]
-; CHECK: %cval.i3 = load i32* %c.i3, align 4, !dbg ![[TAG1]], !tbaa ![[TAG2]]
+; CHECK: %bval.i0 = load i32, i32* %b.i0, align 16, !dbg ![[TAG1:[0-9]+]], !tbaa ![[TAG2:[0-9]+]]
+; CHECK: %bval.i1 = load i32, i32* %b.i1, align 4, !dbg ![[TAG1]], !tbaa ![[TAG2]]
+; CHECK: %bval.i2 = load i32, i32* %b.i2, align 8, !dbg ![[TAG1]], !tbaa ![[TAG2]]
+; CHECK: %bval.i3 = load i32, i32* %b.i3, align 4, !dbg ![[TAG1]], !tbaa ![[TAG2]]
+; CHECK: %cval.i0 = load i32, i32* %c.i0, align 16, !dbg ![[TAG1]], !tbaa ![[TAG2]]
+; CHECK: %cval.i1 = load i32, i32* %c.i1, align 4, !dbg ![[TAG1]], !tbaa ![[TAG2]]
+; CHECK: %cval.i2 = load i32, i32* %c.i2, align 8, !dbg ![[TAG1]], !tbaa ![[TAG2]]
+; CHECK: %cval.i3 = load i32, i32* %c.i3, align 4, !dbg ![[TAG1]], !tbaa ![[TAG2]]
 ; CHECK: %add.i0 = add i32 %bval.i0, %cval.i0, !dbg ![[TAG1]]
 ; CHECK: %add.i1 = add i32 %bval.i1, %cval.i1, !dbg ![[TAG1]]
 ; CHECK: %add.i2 = add i32 %bval.i2, %cval.i2, !dbg ![[TAG1]]
@@ -37,11 +37,11 @@ define void @f1(<4 x i32>* nocapture %a, <4 x i32>* nocapture readonly %b, <4 x
 ; CHECK: store i32 %add.i3, i32* %a.i3, align 4, !dbg ![[TAG1]], !tbaa ![[TAG2]]
 ; CHECK: ret void
 entry:
-  tail call void @llvm.dbg.value(metadata <4 x i32>* %a, i64 0, metadata !15, metadata !{}), !dbg !20
-  tail call void @llvm.dbg.value(metadata <4 x i32>* %b, i64 0, metadata !16, metadata !{}), !dbg !20
-  tail call void @llvm.dbg.value(metadata <4 x i32>* %c, i64 0, metadata !17, metadata !{}), !dbg !20
-  %bval = load <4 x i32>* %b, align 16, !dbg !21, !tbaa !22
-  %cval = load <4 x i32>* %c, align 16, !dbg !21, !tbaa !22
+  tail call void @llvm.dbg.value(metadata <4 x i32>* %a, i64 0, metadata !15, metadata !DIExpression()), !dbg !20
+  tail call void @llvm.dbg.value(metadata <4 x i32>* %b, i64 0, metadata !16, metadata !DIExpression()), !dbg !20
+  tail call void @llvm.dbg.value(metadata <4 x i32>* %c, i64 0, metadata !17, metadata !DIExpression()), !dbg !20
+  %bval = load <4 x i32>, <4 x i32>* %b, align 16, !dbg !21, !tbaa !22
+  %cval = load <4 x i32>, <4 x i32>* %c, align 16, !dbg !21, !tbaa !22
   %add = add <4 x i32> %bval, %cval, !dbg !21
   store <4 x i32> %add, <4 x i32>* %a, align 16, !dbg !21, !tbaa !22
   ret void, !dbg !25
@@ -57,30 +57,30 @@ attributes #1 = { nounwind readnone }
 !llvm.module.flags = !{!18, !26}
 !llvm.ident = !{!19}
 
-!0 = !{!"0x11\0012\00clang version 3.4 (trunk 194134) (llvm/trunk 194126)\001\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/home/richards/llvm/build//tmp/add.c] [DW_LANG_C99]
-!1 = !{!"/tmp/add.c", !"/home/richards/llvm/build"}
-!2 = !{i32 0}
+!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 194134) (llvm/trunk 194126)", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!1 = !DIFile(filename: "/tmp/add.c", directory: "/home/richards/llvm/build")
+!2 = !{}
 !3 = !{!4}
-!4 = !{!"0x2e\00f1\00f1\00\003\000\001\000\006\00256\001\004", !1, !5, !6, null, void (<4 x i32>*, <4 x i32>*, <4 x i32>*)* @f1, null, null, !14} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 4] [f]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/home/richards/llvm/build//tmp/add.c]
-!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!4 = !DISubprogram(name: "f1", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 4, file: !1, scope: !5, type: !6, function: void (<4 x i32>*, <4 x i32>*, <4 x i32>*)* @f1, variables: !14)
+!5 = !DIFile(filename: "/tmp/add.c", directory: "/home/richards/llvm/build")
+!6 = !DISubroutineType(types: !7)
 !7 = !{null, !8, !8, !8}
-!8 = !{!"0xf\00\000\0064\0064\000\000", null, null, !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from V4SI]
-!9 = !{!"0x16\00V4SI\001\000\000\000\000", !1, null, !10} ; [ DW_TAG_typedef ] [V4SI] [line 1, size 0, align 0, offset 0] [from ]
-!10 = !{!"0x1\00\000\00128\00128\000\002048", null, null, !11, !12, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 128, offset 0] [vector] [from int]
-!11 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!8 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !9)
+!9 = !DIDerivedType(tag: DW_TAG_typedef, name: "V4SI", line: 1, file: !1, baseType: !10)
+!10 = !DICompositeType(tag: DW_TAG_array_type, size: 128, align: 128, flags: DIFlagVector, baseType: !11, elements: !12)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
 !12 = !{!13}
-!13 = !{!"0x21\000\004"}        ; [ DW_TAG_subrange_type ] [0, 3]
+!13 = !DISubrange(count: 4)
 !14 = !{!15, !16, !17}
-!15 = !{!"0x101\00a\0016777219\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [a] [line 3]
-!16 = !{!"0x101\00b\0033554435\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [b] [line 3]
-!17 = !{!"0x101\00c\0050331651\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [c] [line 3]
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 3, arg: 1, scope: !4, file: !5, type: !8)
+!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 3, arg: 2, scope: !4, file: !5, type: !8)
+!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 3, arg: 3, scope: !4, file: !5, type: !8)
 !18 = !{i32 2, !"Dwarf Version", i32 4}
 !19 = !{!"clang version 3.4 (trunk 194134) (llvm/trunk 194126)"}
-!20 = !MDLocation(line: 3, scope: !4)
-!21 = !MDLocation(line: 5, scope: !4)
+!20 = !DILocation(line: 3, scope: !4)
+!21 = !DILocation(line: 5, scope: !4)
 !22 = !{!23, !23, i64 0}
 !23 = !{!"omnipotent char", !24, i64 0}
 !24 = !{!"Simple C/C++ TBAA"}
-!25 = !MDLocation(line: 6, scope: !4)
-!26 = !{i32 1, !"Debug Info Version", i32 2}
+!25 = !DILocation(line: 6, scope: !4)
+!26 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/Scalarizer/no-data-layout.ll b/test/Transforms/Scalarizer/no-data-layout.ll
deleted file mode 100644
index 3eaf669ef9dd..000000000000
--- a/test/Transforms/Scalarizer/no-data-layout.ll
+++ /dev/null
@@ -1,25 +0,0 @@
-; RUN: opt %s -scalarizer -scalarize-load-store -S | FileCheck %s
-
-; Test the handling of loads and stores when no data layout is available.
-define void @f1(<4 x float> *%dest, <4 x float> *%src) {
-; CHECK: @f1(
-; CHECK: %val = load <4 x float>* %src, align 4
-; CHECK: %val.i0 = extractelement <4 x float> %val, i32 0
-; CHECK: %add.i0 = fadd float %val.i0, %val.i0
-; CHECK: %val.i1 = extractelement <4 x float> %val, i32 1
-; CHECK: %add.i1 = fadd float %val.i1, %val.i1
-; CHECK: %val.i2 = extractelement <4 x float> %val, i32 2
-; CHECK: %add.i2 = fadd float %val.i2, %val.i2
-; CHECK: %val.i3 = extractelement <4 x float> %val, i32 3
-; CHECK: %add.i3 = fadd float %val.i3, %val.i3
-; CHECK: %add.upto0 = insertelement <4 x float> undef, float %add.i0, i32 0
-; CHECK: %add.upto1 = insertelement <4 x float> %add.upto0, float %add.i1, i32 1
-; CHECK: %add.upto2 = insertelement <4 x float> %add.upto1, float %add.i2, i32 2
-; CHECK: %add = insertelement <4 x float> %add.upto2, float %add.i3, i32 3
-; CHECK: store <4 x float> %add, <4 x float>* %dest, align 8
-; CHECK: ret void
-  %val = load <4 x float> *%src, align 4
-  %add = fadd <4 x float> %val, %val
-  store <4 x float> %add, <4 x float> *%dest, align 8
-  ret void
-}
diff --git a/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll b/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
index d054a3b1b9f2..073313d40e77 100644
--- a/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
+++ b/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX
-; RUN: opt < %s -S -separate-const-offset-from-gep -gvn -dce | FileCheck %s --check-prefix=IR
+; RUN: opt < %s -S -separate-const-offset-from-gep -reassociate-geps-verify-no-dead-code -gvn | FileCheck %s --check-prefix=IR
 
 ; Verifies the SeparateConstOffsetFromGEP pass.
 ; The following code computes
@@ -21,25 +21,25 @@ define void @sum_of_array(i32 %x, i32 %y, float* nocapture %output) {
 .preheader:
   %0 = sext i32 %y to i64
   %1 = sext i32 %x to i64
-  %2 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0
+  %2 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0
   %3 = addrspacecast float addrspace(3)* %2 to float*
-  %4 = load float* %3, align 4
+  %4 = load float, float* %3, align 4
   %5 = fadd float %4, 0.000000e+00
   %6 = add i32 %y, 1
   %7 = sext i32 %6 to i64
-  %8 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %7
+  %8 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %7
   %9 = addrspacecast float addrspace(3)* %8 to float*
-  %10 = load float* %9, align 4
+  %10 = load float, float* %9, align 4
   %11 = fadd float %5, %10
   %12 = add i32 %x, 1
   %13 = sext i32 %12 to i64
-  %14 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %0
+  %14 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %0
   %15 = addrspacecast float addrspace(3)* %14 to float*
-  %16 = load float* %15, align 4
+  %16 = load float, float* %15, align 4
   %17 = fadd float %11, %16
-  %18 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %7
+  %18 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %7
   %19 = addrspacecast float addrspace(3)* %18 to float*
-  %20 = load float* %19, align 4
+  %20 = load float, float* %19, align 4
   %21 = fadd float %17, %20
   store float %21, float* %output, align 4
   ret void
@@ -51,10 +51,10 @@ define void @sum_of_array(i32 %x, i32 %y, float* nocapture %output) {
 ; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}}
 
 ; IR-LABEL: @sum_of_array(
-; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
-; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 1
-; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 32
-; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 33
+; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
+; IR: getelementptr float, float addrspace(3)* [[BASE_PTR]], i64 1
+; IR: getelementptr float, float addrspace(3)* [[BASE_PTR]], i64 32
+; IR: getelementptr float, float addrspace(3)* [[BASE_PTR]], i64 33
 
 ; @sum_of_array2 is very similar to @sum_of_array. The only difference is in
 ; the order of "sext" and "add" when computing the array indices. @sum_of_array
@@ -66,23 +66,23 @@ define void @sum_of_array2(i32 %x, i32 %y, float* nocapture %output) {
 .preheader:
   %0 = sext i32 %y to i64
   %1 = sext i32 %x to i64
-  %2 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0
+  %2 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0
   %3 = addrspacecast float addrspace(3)* %2 to float*
-  %4 = load float* %3, align 4
+  %4 = load float, float* %3, align 4
   %5 = fadd float %4, 0.000000e+00
   %6 = add i64 %0, 1
-  %7 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %6
+  %7 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %6
   %8 = addrspacecast float addrspace(3)* %7 to float*
-  %9 = load float* %8, align 4
+  %9 = load float, float* %8, align 4
   %10 = fadd float %5, %9
   %11 = add i64 %1, 1
-  %12 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %0
+  %12 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %0
   %13 = addrspacecast float addrspace(3)* %12 to float*
-  %14 = load float* %13, align 4
+  %14 = load float, float* %13, align 4
   %15 = fadd float %10, %14
-  %16 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %6
+  %16 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %6
   %17 = addrspacecast float addrspace(3)* %16 to float*
-  %18 = load float* %17, align 4
+  %18 = load float, float* %17, align 4
   %19 = fadd float %15, %18
   store float %19, float* %output, align 4
   ret void
@@ -94,10 +94,10 @@ define void @sum_of_array2(i32 %x, i32 %y, float* nocapture %output) {
 ; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}}
 
 ; IR-LABEL: @sum_of_array2(
-; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
-; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 1
-; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 32
-; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 33
+; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
+; IR: getelementptr float, float addrspace(3)* [[BASE_PTR]], i64 1
+; IR: getelementptr float, float addrspace(3)* [[BASE_PTR]], i64 32
+; IR: getelementptr float, float addrspace(3)* [[BASE_PTR]], i64 33
 
 
 ; This function loads
@@ -114,25 +114,25 @@ define void @sum_of_array3(i32 %x, i32 %y, float* nocapture %output) {
 .preheader:
   %0 = zext i32 %y to i64
   %1 = zext i32 %x to i64
-  %2 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0
+  %2 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0
   %3 = addrspacecast float addrspace(3)* %2 to float*
-  %4 = load float* %3, align 4
+  %4 = load float, float* %3, align 4
   %5 = fadd float %4, 0.000000e+00
   %6 = add nuw i32 %y, 1
   %7 = zext i32 %6 to i64
-  %8 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %7
+  %8 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %7
   %9 = addrspacecast float addrspace(3)* %8 to float*
-  %10 = load float* %9, align 4
+  %10 = load float, float* %9, align 4
   %11 = fadd float %5, %10
   %12 = add nuw i32 %x, 1
   %13 = zext i32 %12 to i64
-  %14 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %0
+  %14 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %0
   %15 = addrspacecast float addrspace(3)* %14 to float*
-  %16 = load float* %15, align 4
+  %16 = load float, float* %15, align 4
   %17 = fadd float %11, %16
-  %18 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %7
+  %18 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %7
   %19 = addrspacecast float addrspace(3)* %18 to float*
-  %20 = load float* %19, align 4
+  %20 = load float, float* %19, align 4
   %21 = fadd float %17, %20
   store float %21, float* %output, align 4
   ret void
@@ -144,10 +144,10 @@ define void @sum_of_array3(i32 %x, i32 %y, float* nocapture %output) {
 ; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}}
 
 ; IR-LABEL: @sum_of_array3(
-; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
-; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 1
-; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 32
-; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 33
+; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
+; IR: getelementptr float, float addrspace(3)* [[BASE_PTR]], i64 1
+; IR: getelementptr float, float addrspace(3)* [[BASE_PTR]], i64 32
+; IR: getelementptr float, float addrspace(3)* [[BASE_PTR]], i64 33
 
 
 ; This function loads
@@ -162,23 +162,23 @@ define void @sum_of_array4(i32 %x, i32 %y, float* nocapture %output) {
 .preheader:
   %0 = zext i32 %y to i64
   %1 = zext i32 %x to i64
-  %2 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0
+  %2 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0
   %3 = addrspacecast float addrspace(3)* %2 to float*
-  %4 = load float* %3, align 4
+  %4 = load float, float* %3, align 4
   %5 = fadd float %4, 0.000000e+00
   %6 = add i64 %0, 1
-  %7 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %6
+  %7 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %6
   %8 = addrspacecast float addrspace(3)* %7 to float*
-  %9 = load float* %8, align 4
+  %9 = load float, float* %8, align 4
   %10 = fadd float %5, %9
   %11 = add i64 %1, 1
-  %12 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %0
+  %12 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %0
   %13 = addrspacecast float addrspace(3)* %12 to float*
-  %14 = load float* %13, align 4
+  %14 = load float, float* %13, align 4
   %15 = fadd float %10, %14
-  %16 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %6
+  %16 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %6
   %17 = addrspacecast float addrspace(3)* %16 to float*
-  %18 = load float* %17, align 4
+  %18 = load float, float* %17, align 4
   %19 = fadd float %15, %18
   store float %19, float* %output, align 4
   ret void
@@ -190,7 +190,7 @@ define void @sum_of_array4(i32 %x, i32 %y, float* nocapture %output) {
 ; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}}
 
 ; IR-LABEL: @sum_of_array4(
-; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
-; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 1
-; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 32
-; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 33
+; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
+; IR: getelementptr float, float addrspace(3)* [[BASE_PTR]], i64 1
+; IR: getelementptr float, float addrspace(3)* [[BASE_PTR]], i64 32
+; IR: getelementptr float, float addrspace(3)* [[BASE_PTR]], i64 33
diff --git a/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll b/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
index ea0d3f5673a5..2fdd158a35ed 100644
--- a/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
+++ b/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
@@ -1,4 +1,4 @@
-; RUN: opt < %s -separate-const-offset-from-gep -dce -S | FileCheck %s
+; RUN: opt < %s -separate-const-offset-from-gep -reassociate-geps-verify-no-dead-code -S | FileCheck %s
 
 ; Several unit tests for -separate-const-offset-from-gep. The transformation
 ; heavily relies on TargetTransformInfo, so we put these tests under
@@ -20,11 +20,11 @@ define double* @struct(i32 %i) {
 entry:
   %add = add nsw i32 %i, 5
   %idxprom = sext i32 %add to i64
-  %p = getelementptr inbounds [1024 x %struct.S]* @struct_array, i64 0, i64 %idxprom, i32 1
+  %p = getelementptr inbounds [1024 x %struct.S], [1024 x %struct.S]* @struct_array, i64 0, i64 %idxprom, i32 1
   ret double* %p
 }
 ; CHECK-LABEL: @struct(
-; CHECK: getelementptr [1024 x %struct.S]* @struct_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i32 1
+; CHECK: getelementptr [1024 x %struct.S], [1024 x %struct.S]* @struct_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i32 1
 
 ; We should be able to trace into sext(a + b) if a + b is non-negative
 ; (e.g., used as an index of an inbounds GEP) and one of a and b is
@@ -36,15 +36,15 @@ entry:
   %2 = add i32 %j, -2
   ; However, inbound sext(j + -2) != sext(j) + -2, e.g., j = INT_MIN
   %3 = sext i32 %2 to i64
-  %p = getelementptr inbounds [32 x [32 x float]]* @float_2d_array, i64 0, i64 %1, i64 %3
+  %p = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %1, i64 %3
   ret float* %p
 }
 ; CHECK-LABEL: @sext_add(
 ; CHECK-NOT: = add
 ; CHECK: add i32 %j, -2
 ; CHECK: sext
-; CHECK: getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
-; CHECK: getelementptr float* %{{[a-zA-Z0-9]+}}, i64 32
+; CHECK: getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
+; CHECK: getelementptr float, float* %{{[a-zA-Z0-9]+}}, i64 32
 
 ; We should be able to trace into sext/zext if it can be distributed to both
 ; operands, e.g., sext (add nsw a, b) == add nsw (sext a), (sext b)
@@ -60,12 +60,12 @@ define float* @ext_add_no_overflow(i64 %a, i32 %b, i64 %c, i32 %d) {
   %d1 = add nuw i32 %d, 1
   %d2 = zext i32 %d1 to i64
   %j = add i64 %c, %d2       ; j = c + zext(d +nuw 1)
-  %p = getelementptr inbounds [32 x [32 x float]]* @float_2d_array, i64 0, i64 %i, i64 %j
+  %p = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %i, i64 %j
   ret float* %p
 }
 ; CHECK-LABEL: @ext_add_no_overflow(
-; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
-; CHECK: getelementptr float* [[BASE_PTR]], i64 33
+; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
+; CHECK: getelementptr float, float* [[BASE_PTR]], i64 33
 
 ; Verifies we handle nested sext/zext correctly.
 define void @sext_zext(i32 %a, i32 %b, float** %out1, float** %out2) {
@@ -76,7 +76,7 @@ entry:
   %3 = add nsw i32 %b, 2
   %4 = sext i32 %3 to i48
   %5 = zext i48 %4 to i64    ; zext(sext(b +nsw 2)) != zext(sext(b)) + 2
-  %p1 = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %2, i64 %5
+  %p1 = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %2, i64 %5
   store float* %p1, float** %out1
   %6 = add nuw i32 %a, 3
   %7 = zext i32 %6 to i48
@@ -84,15 +84,15 @@ entry:
   %9 = add nsw i32 %b, 4
   %10 = zext i32 %9 to i48
   %11 = sext i48 %10 to i64  ; sext(zext(b +nsw 4)) != zext(b) + 4
-  %p2 = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %8, i64 %11
+  %p2 = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %8, i64 %11
   store float* %p2, float** %out2
   ret void
 }
 ; CHECK-LABEL: @sext_zext(
-; CHECK: [[BASE_PTR_1:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
-; CHECK: getelementptr float* [[BASE_PTR_1]], i64 32
-; CHECK: [[BASE_PTR_2:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
-; CHECK: getelementptr float* [[BASE_PTR_2]], i64 96
+; CHECK: [[BASE_PTR_1:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
+; CHECK: getelementptr float, float* [[BASE_PTR_1]], i64 32
+; CHECK: [[BASE_PTR_2:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
+; CHECK: getelementptr float, float* [[BASE_PTR_2]], i64 96
 
 ; Similar to @ext_add_no_overflow, we should be able to trace into s/zext if
 ; its operand is an OR and the two operands of the OR have no common bits.
@@ -105,12 +105,12 @@ entry:
   %b3.ext = sext i32 %b3 to i64
   %i = add i64 %a, %b2.ext
   %j = add i64 %a, %b3.ext
-  %p = getelementptr inbounds [32 x [32 x float]]* @float_2d_array, i64 0, i64 %i, i64 %j
+  %p = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %i, i64 %j
   ret float* %p
 }
 ; CHECK-LABEL: @sext_or(
-; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
-; CHECK: getelementptr float* [[BASE_PTR]], i64 32
+; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
+; CHECK: getelementptr float, float* [[BASE_PTR]], i64 32
 
 ; The subexpression (b + 5) is used in both "i = a + (b + 5)" and "*out = b +
 ; 5". When extracting the constant offset 5, make sure "*out = b + 5" isn't
@@ -119,13 +119,13 @@ define float* @expr(i64 %a, i64 %b, i64* %out) {
 entry:
   %b5 = add i64 %b, 5
   %i = add i64 %b5, %a
-  %p = getelementptr inbounds [32 x [32 x float]]* @float_2d_array, i64 0, i64 %i, i64 0
+  %p = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %i, i64 0
   store i64 %b5, i64* %out
   ret float* %p
 }
 ; CHECK-LABEL: @expr(
-; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 0
-; CHECK: getelementptr float* [[BASE_PTR]], i64 160
+; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 0
+; CHECK: getelementptr float, float* [[BASE_PTR]], i64 160
 ; CHECK: store i64 %b5, i64* %out
 
 ; d + sext(a +nsw (b +nsw (c +nsw 8))) => (d + sext(a) + sext(b) + sext(c)) + 8
@@ -136,26 +136,26 @@ entry:
   %2 = add nsw i32 %a, %1
   %3 = sext i32 %2 to i64
   %i = add i64 %d, %3
-  %p = getelementptr inbounds [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %i
+  %p = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %i
   ret float* %p
 }
 ; CHECK-LABEL: @sext_expr(
 ; CHECK: sext i32
 ; CHECK: sext i32
 ; CHECK: sext i32
-; CHECK: getelementptr float* %{{[a-zA-Z0-9]+}}, i64 8
+; CHECK: getelementptr float, float* %{{[a-zA-Z0-9]+}}, i64 8
 
 ; Verifies we handle "sub" correctly.
 define float* @sub(i64 %i, i64 %j) {
   %i2 = sub i64 %i, 5 ; i - 5
   %j2 = sub i64 5, %j ; 5 - i
-  %p = getelementptr inbounds [32 x [32 x float]]* @float_2d_array, i64 0, i64 %i2, i64 %j2
+  %p = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %i2, i64 %j2
   ret float* %p
 }
 ; CHECK-LABEL: @sub(
 ; CHECK: %[[j2:[a-zA-Z0-9]+]] = sub i64 0, %j
-; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %i, i64 %[[j2]]
-; CHECK: getelementptr float* [[BASE_PTR]], i64 -155
+; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %i, i64 %[[j2]]
+; CHECK: getelementptr float, float* [[BASE_PTR]], i64 -155
 
 %struct.Packed = type <{ [3 x i32], [8 x i64] }> ; <> means packed
 
@@ -167,13 +167,13 @@ entry:
   %idxprom = sext i32 %add to i64
   %add1 = add nsw i32 %i, 1
   %idxprom2 = sext i32 %add1 to i64
-  %arrayidx3 = getelementptr inbounds [1024 x %struct.Packed]* %s, i64 0, i64 %idxprom2, i32 1, i64 %idxprom
+  %arrayidx3 = getelementptr inbounds [1024 x %struct.Packed], [1024 x %struct.Packed]* %s, i64 0, i64 %idxprom2, i32 1, i64 %idxprom
   ret i64* %arrayidx3
 }
 ; CHECK-LABEL: @packed_struct(
-; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [1024 x %struct.Packed]* %s, i64 0, i64 %{{[a-zA-Z0-9]+}}, i32 1, i64 %{{[a-zA-Z0-9]+}}
+; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [1024 x %struct.Packed], [1024 x %struct.Packed]* %s, i64 0, i64 %{{[a-zA-Z0-9]+}}, i32 1, i64 %{{[a-zA-Z0-9]+}}
 ; CHECK: [[CASTED_PTR:%[a-zA-Z0-9]+]] = bitcast i64* [[BASE_PTR]] to i8*
-; CHECK: %uglygep = getelementptr i8* [[CASTED_PTR]], i64 100
+; CHECK: %uglygep = getelementptr i8, i8* [[CASTED_PTR]], i64 100
 ; CHECK: bitcast i8* %uglygep to i64*
 
 ; We shouldn't be able to extract the 8 from "zext(a +nuw (b + 8))",
@@ -183,11 +183,11 @@ entry:
   %0 = add i32 %b, 8
   %1 = add nuw i32 %a, %0
   %i = zext i32 %1 to i64
-  %p = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %i
+  %p = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %i
   ret float* %p
 }
 ; CHECK-LABEL: zext_expr(
-; CHECK: getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %i
+; CHECK: getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %i
 
 ; Per http://llvm.org/docs/LangRef.html#id181, the indices of a off-bound gep
 ; should be considered sign-extended to the pointer size. Therefore,
@@ -200,11 +200,11 @@ entry:
 define float* @i32_add(i32 %a) {
 entry:
   %i = add i32 %a, 8
-  %p = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i32 %i
+  %p = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i32 %i
   ret float* %p
 }
 ; CHECK-LABEL: @i32_add(
-; CHECK: getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %{{[a-zA-Z0-9]+}}
+; CHECK: getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %{{[a-zA-Z0-9]+}}
 ; CHECK-NOT: getelementptr
 
 ; Verifies that we compute the correct constant offset when the index is
@@ -216,23 +216,23 @@ entry:
   %0 = add nsw nuw i1 %a, 1
   %1 = sext i1 %0 to i4
   %2 = zext i4 %1 to i64         ; zext (sext i1 1 to i4) to i64 = 15
-  %p = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %2
+  %p = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %2
   ret float* %p
 }
 ; CHECK-LABEL: @apint(
-; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %{{[a-zA-Z0-9]+}}
-; CHECK: getelementptr float* [[BASE_PTR]], i64 15
+; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %{{[a-zA-Z0-9]+}}
+; CHECK: getelementptr float, float* [[BASE_PTR]], i64 15
 
 ; Do not trace into binary operators other than ADD, SUB, and OR.
 define float* @and(i64 %a) {
 entry:
   %0 = shl i64 %a, 2
   %1 = and i64 %0, 1
-  %p = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %1
+  %p = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %1
   ret float* %p
 }
 ; CHECK-LABEL: @and(
-; CHECK: getelementptr [32 x [32 x float]]* @float_2d_array
+; CHECK: getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array
 ; CHECK-NOT: getelementptr
 
 ; The code that rebuilds an OR expression used to be buggy, and failed on this
@@ -247,9 +247,9 @@ entry:
   ; ((a << 2) + 12) and 1 have no common bits. Therefore,
   ; SeparateConstOffsetFromGEP is able to extract the 12.
   ; TODO(jingyue): We could reassociate the expression to combine 12 and 1.
-  %p = getelementptr float* %ptr, i64 %or
-; CHECK: [[PTR:%[a-zA-Z0-9]+]] = getelementptr float* %ptr, i64 [[OR]]
-; CHECK: getelementptr float* [[PTR]], i64 12
+  %p = getelementptr float, float* %ptr, i64 %or
+; CHECK: [[PTR:%[a-zA-Z0-9]+]] = getelementptr float, float* %ptr, i64 [[OR]]
+; CHECK: getelementptr float, float* [[PTR]], i64 12
   ret float* %p
 ; CHECK-NEXT: ret
 }
@@ -269,10 +269,10 @@ define %struct2* @sign_mod_unsign(%struct0* %ptr, i64 %idx) {
 entry:
   %arrayidx = add nsw i64 %idx, -2
 ; CHECK-NOT: add
-  %ptr2 = getelementptr inbounds %struct0* %ptr, i64 0, i32 3, i64 %arrayidx, i32 1
-; CHECK: [[PTR:%[a-zA-Z0-9]+]] = getelementptr %struct0* %ptr, i64 0, i32 3, i64 %idx, i32 1
+  %ptr2 = getelementptr inbounds %struct0, %struct0* %ptr, i64 0, i32 3, i64 %arrayidx, i32 1
+; CHECK: [[PTR:%[a-zA-Z0-9]+]] = getelementptr %struct0, %struct0* %ptr, i64 0, i32 3, i64 %idx, i32 1
 ; CHECK: [[PTR1:%[a-zA-Z0-9]+]] = bitcast %struct2* [[PTR]] to i8*
-; CHECK: getelementptr i8* [[PTR1]], i64 -64
+; CHECK: getelementptr i8, i8* [[PTR1]], i64 -64
 ; CHECK: bitcast
   ret %struct2* %ptr2
 ; CHECK-NEXT: ret
diff --git a/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/value-tracking-domtree.ll b/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/value-tracking-domtree.ll
new file mode 100644
index 000000000000..d1a0f33d5a21
--- /dev/null
+++ b/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/value-tracking-domtree.ll
@@ -0,0 +1,33 @@
+; RUN: opt < %s -separate-const-offset-from-gep -value-tracking-dom-conditions -reassociate-geps-verify-no-dead-code -S | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "nvptx64-unknown-unknown"
+
+; if (i == 4)
+;   p = &input[i | 3];
+;
+; =>
+;
+; if (i == 4) {
+;   base = &input[i];
+;   p = &base[3];
+; }
+;
+; We should treat (i | 3) as (i + 3) because i is guaranteed to be 4, which
+; does not share any set bits with 3.
+define float* @guarded_or(float* %input, i64 %i) {
+; CHECK-LABEL: @guarded_or(
+entry:
+  %is4 = icmp eq i64 %i, 4
+  br i1 %is4, label %then, label %exit
+
+then:
+  %or = or i64 %i, 3
+  %p = getelementptr inbounds float, float* %input, i64 %or
+; CHECK: [[base:[^ ]+]] = getelementptr float, float* %input, i64 %i
+; CHECK: getelementptr float, float* [[base]], i64 3
+  ret float* %p
+
+exit:
+  ret float* null
+}
diff --git a/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch-dbg.ll b/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch-dbg.ll
index fbfb100274f6..0626ea178e5c 100644
--- a/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch-dbg.ll
+++ b/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch-dbg.ll
@@ -9,7 +9,7 @@
 @.str = internal constant [4 x i8] c"a.c\00", section "llvm.metadata"		; <[4 x i8]*> [#uses=1]
 @.str1 = internal constant [6 x i8] c"/tmp/\00", section "llvm.metadata"	; <[6 x i8]*> [#uses=1]
 @.str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build 00)\00", section "llvm.metadata"		; <[55 x i8]*> [#uses=1]
-@llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([6 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata"		; <%llvm.dbg.compile_unit.type*> [#uses=1]
+@llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8], [55 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata"		; <%llvm.dbg.compile_unit.type*> [#uses=1]
 
 declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind
 
diff --git a/test/Transforms/SimplifyCFG/2005-06-16-PHICrash.ll b/test/Transforms/SimplifyCFG/2005-06-16-PHICrash.ll
index 90be6803a5c3..8fd1fae34503 100644
--- a/test/Transforms/SimplifyCFG/2005-06-16-PHICrash.ll
+++ b/test/Transforms/SimplifyCFG/2005-06-16-PHICrash.ll
@@ -30,7 +30,7 @@ endif.0:		; preds = %loopentry.0
 	%tmp.14 = sext i8 %tmp.1 to i32		; <i32> [#uses=1]
 	%tmp.16 = zext i8 %l_88173906 to i32		; <i32> [#uses=1]
 	%tmp.17 = icmp sgt i32 %tmp.14, %tmp.16		; <i1> [#uses=1]
-	%tmp.19 = load i32* @g_59182229		; <i32> [#uses=2]
+	%tmp.19 = load i32, i32* @g_59182229		; <i32> [#uses=2]
 	br i1 %tmp.17, label %cond_true, label %cond_false
 cond_true:		; preds = %endif.0
 	%tmp.20 = icmp ne i32 %tmp.19, 1		; <i1> [#uses=1]
@@ -53,7 +53,7 @@ loopentry.1:		; preds = %endif.3, %else.2
 	%tmp.29 = icmp sgt i32 %i.1.1, 99		; <i1> [#uses=1]
 	br i1 %tmp.29, label %endif.2, label %no_exit.1
 no_exit.1:		; preds = %loopentry.1
-	%tmp.30 = load i32* @g_38098584		; <i32> [#uses=1]
+	%tmp.30 = load i32, i32* @g_38098584		; <i32> [#uses=1]
 	%tmp.31 = icmp eq i32 %tmp.30, 0		; <i1> [#uses=1]
 	br i1 %tmp.31, label %else.3, label %then.3
 then.3:		; preds = %no_exit.1
diff --git a/test/Transforms/SimplifyCFG/2005-08-01-PHIUpdateFail.ll b/test/Transforms/SimplifyCFG/2005-08-01-PHIUpdateFail.ll
index c30bfa1379c7..c45986749ab0 100644
--- a/test/Transforms/SimplifyCFG/2005-08-01-PHIUpdateFail.ll
+++ b/test/Transforms/SimplifyCFG/2005-08-01-PHIUpdateFail.ll
@@ -58,7 +58,7 @@ then.2.i:		; preds = %endif.1.i, %then.1.i
 getfree.exit:		; preds = %endif.1.i, %then.1.i
 	ret void
 endif.1:		; preds = %read_min.exit
-	%tmp.27.i = getelementptr i32* null, i32 0		; <i32*> [#uses=0]
+	%tmp.27.i = getelementptr i32, i32* null, i32 0		; <i32*> [#uses=0]
 	br i1 false, label %loopexit.0.i15, label %no_exit.0.i14
 no_exit.0.i14:		; preds = %endif.1
 	ret void
diff --git a/test/Transforms/SimplifyCFG/2005-12-03-IncorrectPHIFold.ll b/test/Transforms/SimplifyCFG/2005-12-03-IncorrectPHIFold.ll
index 907261bd438a..2606e08da9a2 100644
--- a/test/Transforms/SimplifyCFG/2005-12-03-IncorrectPHIFold.ll
+++ b/test/Transforms/SimplifyCFG/2005-12-03-IncorrectPHIFold.ll
@@ -36,8 +36,8 @@ entry:
 	%guess = alloca %struct.anon*		; <%struct.anon**> [#uses=7]
 	%guess1 = alloca %struct.anon*		; <%struct.anon**> [#uses=7]
 	%point5 = alloca %struct.anon*		; <%struct.anon**> [#uses=3]
-	%tmp = load %struct.anon** %num		; <%struct.anon*> [#uses=1]
-	%tmp1 = load %struct.anon** @_zero_		; <%struct.anon*> [#uses=1]
+	%tmp = load %struct.anon*, %struct.anon** %num		; <%struct.anon*> [#uses=1]
+	%tmp1 = load %struct.anon*, %struct.anon** @_zero_		; <%struct.anon*> [#uses=1]
 	%tmp.upgrd.1 = call i32 @bc_compare( %struct.anon* %tmp, %struct.anon* %tmp1 )		; <i32> [#uses=2]
 	%tmp.upgrd.2 = icmp slt i32 %tmp.upgrd.1, 0		; <i1> [#uses=1]
 	br i1 %tmp.upgrd.2, label %cond_true, label %cond_false
@@ -48,26 +48,26 @@ cond_false:		; preds = %entry
 	br i1 %tmp5, label %cond_true6, label %cond_next13
 cond_true6:		; preds = %cond_false
 	call void @free_num( %struct.anon** %num )
-	%tmp8 = load %struct.anon** @_zero_		; <%struct.anon*> [#uses=1]
+	%tmp8 = load %struct.anon*, %struct.anon** @_zero_		; <%struct.anon*> [#uses=1]
 	%tmp9 = call %struct.anon* @copy_num( %struct.anon* %tmp8 )		; <%struct.anon*> [#uses=1]
 	store %struct.anon* %tmp9, %struct.anon** %num
 	ret i32 1
 cond_next13:		; preds = %cond_false
-	%tmp15 = load %struct.anon** %num		; <%struct.anon*> [#uses=1]
-	%tmp16 = load %struct.anon** @_one_		; <%struct.anon*> [#uses=1]
+	%tmp15 = load %struct.anon*, %struct.anon** %num		; <%struct.anon*> [#uses=1]
+	%tmp16 = load %struct.anon*, %struct.anon** @_one_		; <%struct.anon*> [#uses=1]
 	%tmp17 = call i32 @bc_compare( %struct.anon* %tmp15, %struct.anon* %tmp16 )		; <i32> [#uses=2]
 	%tmp19 = icmp eq i32 %tmp17, 0		; <i1> [#uses=1]
 	br i1 %tmp19, label %cond_true20, label %cond_next27
 cond_true20:		; preds = %cond_next13
 	call void @free_num( %struct.anon** %num )
-	%tmp22 = load %struct.anon** @_one_		; <%struct.anon*> [#uses=1]
+	%tmp22 = load %struct.anon*, %struct.anon** @_one_		; <%struct.anon*> [#uses=1]
 	%tmp23 = call %struct.anon* @copy_num( %struct.anon* %tmp22 )		; <%struct.anon*> [#uses=1]
 	store %struct.anon* %tmp23, %struct.anon** %num
 	ret i32 1
 cond_next27:		; preds = %cond_next13
-	%tmp29 = load %struct.anon** %num		; <%struct.anon*> [#uses=1]
-	%tmp30 = getelementptr %struct.anon* %tmp29, i32 0, i32 2		; <i32*> [#uses=1]
-	%tmp31 = load i32* %tmp30		; <i32> [#uses=2]
+	%tmp29 = load %struct.anon*, %struct.anon** %num		; <%struct.anon*> [#uses=1]
+	%tmp30 = getelementptr %struct.anon, %struct.anon* %tmp29, i32 0, i32 2		; <i32*> [#uses=1]
+	%tmp31 = load i32, i32* %tmp30		; <i32> [#uses=2]
 	%tmp33 = icmp sge i32 %tmp31, %scale		; <i1> [#uses=1]
 	%max = select i1 %tmp33, i32 %tmp31, i32 %scale		; <i32> [#uses=4]
 	%tmp35 = add i32 %max, 2		; <i32> [#uses=0]
@@ -75,29 +75,29 @@ cond_next27:		; preds = %cond_next13
 	call void @init_num( %struct.anon** %guess1 )
 	%tmp36 = call %struct.anon* @new_num( i32 1, i32 1 )		; <%struct.anon*> [#uses=2]
 	store %struct.anon* %tmp36, %struct.anon** %point5
-	%tmp.upgrd.3 = getelementptr %struct.anon* %tmp36, i32 0, i32 4, i32 1		; <i8*> [#uses=1]
+	%tmp.upgrd.3 = getelementptr %struct.anon, %struct.anon* %tmp36, i32 0, i32 4, i32 1		; <i8*> [#uses=1]
 	store i8 5, i8* %tmp.upgrd.3
 	%tmp39 = icmp slt i32 %tmp17, 0		; <i1> [#uses=1]
 	br i1 %tmp39, label %cond_true40, label %cond_false43
 cond_true40:		; preds = %cond_next27
-	%tmp41 = load %struct.anon** @_one_		; <%struct.anon*> [#uses=1]
+	%tmp41 = load %struct.anon*, %struct.anon** @_one_		; <%struct.anon*> [#uses=1]
 	%tmp42 = call %struct.anon* @copy_num( %struct.anon* %tmp41 )		; <%struct.anon*> [#uses=1]
 	store %struct.anon* %tmp42, %struct.anon** %guess
 	br label %bb80.outer
 cond_false43:		; preds = %cond_next27
 	call void @int2num( %struct.anon** %guess, i32 10 )
-	%tmp45 = load %struct.anon** %num		; <%struct.anon*> [#uses=1]
-	%tmp46 = getelementptr %struct.anon* %tmp45, i32 0, i32 1		; <i32*> [#uses=1]
-	%tmp47 = load i32* %tmp46		; <i32> [#uses=1]
+	%tmp45 = load %struct.anon*, %struct.anon** %num		; <%struct.anon*> [#uses=1]
+	%tmp46 = getelementptr %struct.anon, %struct.anon* %tmp45, i32 0, i32 1		; <i32*> [#uses=1]
+	%tmp47 = load i32, i32* %tmp46		; <i32> [#uses=1]
 	call void @int2num( %struct.anon** %guess1, i32 %tmp47 )
-	%tmp48 = load %struct.anon** %guess1		; <%struct.anon*> [#uses=1]
-	%tmp49 = load %struct.anon** %point5		; <%struct.anon*> [#uses=1]
+	%tmp48 = load %struct.anon*, %struct.anon** %guess1		; <%struct.anon*> [#uses=1]
+	%tmp49 = load %struct.anon*, %struct.anon** %point5		; <%struct.anon*> [#uses=1]
 	call void @bc_multiply( %struct.anon* %tmp48, %struct.anon* %tmp49, %struct.anon** %guess1, i32 %max )
-	%tmp51 = load %struct.anon** %guess1		; <%struct.anon*> [#uses=1]
-	%tmp52 = getelementptr %struct.anon* %tmp51, i32 0, i32 2		; <i32*> [#uses=1]
+	%tmp51 = load %struct.anon*, %struct.anon** %guess1		; <%struct.anon*> [#uses=1]
+	%tmp52 = getelementptr %struct.anon, %struct.anon* %tmp51, i32 0, i32 2		; <i32*> [#uses=1]
 	store i32 0, i32* %tmp52
-	%tmp53 = load %struct.anon** %guess		; <%struct.anon*> [#uses=1]
-	%tmp54 = load %struct.anon** %guess1		; <%struct.anon*> [#uses=1]
+	%tmp53 = load %struct.anon*, %struct.anon** %guess		; <%struct.anon*> [#uses=1]
+	%tmp54 = load %struct.anon*, %struct.anon** %guess1		; <%struct.anon*> [#uses=1]
 	call void @bc_raise( %struct.anon* %tmp53, %struct.anon* %tmp54, %struct.anon** %guess, i32 %max )
 	br label %bb80.outer
 bb80.outer:		; preds = %cond_true83, %cond_false43, %cond_true40
@@ -113,8 +113,8 @@ cond_true83:		; preds = %bb80
 ; CHECK: bb86
 bb86:		; preds = %bb80
 	call void @free_num( %struct.anon** %num )
-	%tmp88 = load %struct.anon** %guess		; <%struct.anon*> [#uses=1]
-	%tmp89 = load %struct.anon** @_one_		; <%struct.anon*> [#uses=1]
+	%tmp88 = load %struct.anon*, %struct.anon** %guess		; <%struct.anon*> [#uses=1]
+	%tmp89 = load %struct.anon*, %struct.anon** @_one_		; <%struct.anon*> [#uses=1]
 	%tmp92 = call i32 @bc_divide( %struct.anon* %tmp88, %struct.anon* %tmp89, %struct.anon** %num, i32 %max )		; <i32> [#uses=0]
 	call void @free_num( %struct.anon** %guess )
 	call void @free_num( %struct.anon** %guess1 )
diff --git a/test/Transforms/SimplifyCFG/2006-08-03-Crash.ll b/test/Transforms/SimplifyCFG/2006-08-03-Crash.ll
index 70fbddfe33b4..0820e9c9825f 100644
--- a/test/Transforms/SimplifyCFG/2006-08-03-Crash.ll
+++ b/test/Transforms/SimplifyCFG/2006-08-03-Crash.ll
@@ -34,7 +34,7 @@ target triple = "powerpc-apple-darwin8"
 
 define void @fold_builtin_classify() {
 entry:
-	%tmp63 = load i32* null		; <i32> [#uses=1]
+	%tmp63 = load i32, i32* null		; <i32> [#uses=1]
 	switch i32 %tmp63, label %bb276 [
 		 i32 414, label %bb145
 		 i32 417, label %bb
@@ -42,54 +42,54 @@ entry:
 bb:		; preds = %entry
 	ret void
 bb145:		; preds = %entry
-	%tmp146 = load %struct.tree_node** null		; <%struct.tree_node*> [#uses=1]
-	%tmp148 = getelementptr %struct.tree_node* %tmp146, i32 0, i32 0, i32 0, i32 1		; <%struct.tree_node**> [#uses=1]
-	%tmp149 = load %struct.tree_node** %tmp148		; <%struct.tree_node*> [#uses=1]
+	%tmp146 = load %struct.tree_node*, %struct.tree_node** null		; <%struct.tree_node*> [#uses=1]
+	%tmp148 = getelementptr %struct.tree_node, %struct.tree_node* %tmp146, i32 0, i32 0, i32 0, i32 1		; <%struct.tree_node**> [#uses=1]
+	%tmp149 = load %struct.tree_node*, %struct.tree_node** %tmp148		; <%struct.tree_node*> [#uses=1]
 	%tmp150 = bitcast %struct.tree_node* %tmp149 to %struct.tree_type*		; <%struct.tree_type*> [#uses=1]
-	%tmp151 = getelementptr %struct.tree_type* %tmp150, i32 0, i32 6		; <i16*> [#uses=1]
+	%tmp151 = getelementptr %struct.tree_type, %struct.tree_type* %tmp150, i32 0, i32 6		; <i16*> [#uses=1]
 	%tmp151.upgrd.1 = bitcast i16* %tmp151 to i32*		; <i32*> [#uses=1]
-	%tmp152 = load i32* %tmp151.upgrd.1		; <i32> [#uses=1]
+	%tmp152 = load i32, i32* %tmp151.upgrd.1		; <i32> [#uses=1]
 	%tmp154 = lshr i32 %tmp152, 16		; <i32> [#uses=1]
 	%tmp154.mask = and i32 %tmp154, 127		; <i32> [#uses=1]
 	%gep.upgrd.2 = zext i32 %tmp154.mask to i64		; <i64> [#uses=1]
-	%tmp155 = getelementptr [35 x i8]* @mode_class, i32 0, i64 %gep.upgrd.2		; <i8*> [#uses=1]
-	%tmp156 = load i8* %tmp155		; <i8> [#uses=1]
+	%tmp155 = getelementptr [35 x i8], [35 x i8]* @mode_class, i32 0, i64 %gep.upgrd.2		; <i8*> [#uses=1]
+	%tmp156 = load i8, i8* %tmp155		; <i8> [#uses=1]
 	%tmp157 = icmp eq i8 %tmp156, 4		; <i1> [#uses=1]
 	br i1 %tmp157, label %cond_next241, label %cond_true158
 cond_true158:		; preds = %bb145
-	%tmp172 = load %struct.tree_node** null		; <%struct.tree_node*> [#uses=1]
-	%tmp174 = getelementptr %struct.tree_node* %tmp172, i32 0, i32 0, i32 0, i32 1		; <%struct.tree_node**> [#uses=1]
-	%tmp175 = load %struct.tree_node** %tmp174		; <%struct.tree_node*> [#uses=1]
+	%tmp172 = load %struct.tree_node*, %struct.tree_node** null		; <%struct.tree_node*> [#uses=1]
+	%tmp174 = getelementptr %struct.tree_node, %struct.tree_node* %tmp172, i32 0, i32 0, i32 0, i32 1		; <%struct.tree_node**> [#uses=1]
+	%tmp175 = load %struct.tree_node*, %struct.tree_node** %tmp174		; <%struct.tree_node*> [#uses=1]
 	%tmp176 = bitcast %struct.tree_node* %tmp175 to %struct.tree_type*		; <%struct.tree_type*> [#uses=1]
-	%tmp177 = getelementptr %struct.tree_type* %tmp176, i32 0, i32 6		; <i16*> [#uses=1]
+	%tmp177 = getelementptr %struct.tree_type, %struct.tree_type* %tmp176, i32 0, i32 6		; <i16*> [#uses=1]
 	%tmp177.upgrd.3 = bitcast i16* %tmp177 to i32*		; <i32*> [#uses=1]
-	%tmp178 = load i32* %tmp177.upgrd.3		; <i32> [#uses=1]
+	%tmp178 = load i32, i32* %tmp177.upgrd.3		; <i32> [#uses=1]
 	%tmp180 = lshr i32 %tmp178, 16		; <i32> [#uses=1]
 	%tmp180.mask = and i32 %tmp180, 127		; <i32> [#uses=1]
 	%gep.upgrd.4 = zext i32 %tmp180.mask to i64		; <i64> [#uses=1]
-	%tmp181 = getelementptr [35 x i8]* @mode_class, i32 0, i64 %gep.upgrd.4		; <i8*> [#uses=1]
-	%tmp182 = load i8* %tmp181		; <i8> [#uses=1]
+	%tmp181 = getelementptr [35 x i8], [35 x i8]* @mode_class, i32 0, i64 %gep.upgrd.4		; <i8*> [#uses=1]
+	%tmp182 = load i8, i8* %tmp181		; <i8> [#uses=1]
 	%tmp183 = icmp eq i8 %tmp182, 8		; <i1> [#uses=1]
 	br i1 %tmp183, label %cond_next241, label %cond_true184
 cond_true184:		; preds = %cond_true158
-	%tmp185 = load %struct.tree_node** null		; <%struct.tree_node*> [#uses=1]
-	%tmp187 = getelementptr %struct.tree_node* %tmp185, i32 0, i32 0, i32 0, i32 1		; <%struct.tree_node**> [#uses=1]
-	%tmp188 = load %struct.tree_node** %tmp187		; <%struct.tree_node*> [#uses=1]
+	%tmp185 = load %struct.tree_node*, %struct.tree_node** null		; <%struct.tree_node*> [#uses=1]
+	%tmp187 = getelementptr %struct.tree_node, %struct.tree_node* %tmp185, i32 0, i32 0, i32 0, i32 1		; <%struct.tree_node**> [#uses=1]
+	%tmp188 = load %struct.tree_node*, %struct.tree_node** %tmp187		; <%struct.tree_node*> [#uses=1]
 	%tmp189 = bitcast %struct.tree_node* %tmp188 to %struct.tree_type*		; <%struct.tree_type*> [#uses=1]
-	%tmp190 = getelementptr %struct.tree_type* %tmp189, i32 0, i32 6		; <i16*> [#uses=1]
+	%tmp190 = getelementptr %struct.tree_type, %struct.tree_type* %tmp189, i32 0, i32 6		; <i16*> [#uses=1]
 	%tmp190.upgrd.5 = bitcast i16* %tmp190 to i32*		; <i32*> [#uses=1]
-	%tmp191 = load i32* %tmp190.upgrd.5		; <i32> [#uses=1]
+	%tmp191 = load i32, i32* %tmp190.upgrd.5		; <i32> [#uses=1]
 	%tmp193 = lshr i32 %tmp191, 16		; <i32> [#uses=1]
 	%tmp193.mask = and i32 %tmp193, 127		; <i32> [#uses=1]
 	%gep.upgrd.6 = zext i32 %tmp193.mask to i64		; <i64> [#uses=1]
-	%tmp194 = getelementptr [35 x i8]* @mode_class, i32 0, i64 %gep.upgrd.6		; <i8*> [#uses=1]
-	%tmp195 = load i8* %tmp194		; <i8> [#uses=1]
+	%tmp194 = getelementptr [35 x i8], [35 x i8]* @mode_class, i32 0, i64 %gep.upgrd.6		; <i8*> [#uses=1]
+	%tmp195 = load i8, i8* %tmp194		; <i8> [#uses=1]
 	%tmp196 = icmp eq i8 %tmp195, 4		; <i1> [#uses=1]
 	br i1 %tmp196, label %cond_next241, label %cond_true197
 cond_true197:		; preds = %cond_true184
 	ret void
 cond_next241:		; preds = %cond_true184, %cond_true158, %bb145
-	%tmp245 = load i32* null		; <i32> [#uses=0]
+	%tmp245 = load i32, i32* null		; <i32> [#uses=0]
 	ret void
 bb276:		; preds = %entry
 	ret void
diff --git a/test/Transforms/SimplifyCFG/2006-12-08-Ptr-ICmp-Branch.ll b/test/Transforms/SimplifyCFG/2006-12-08-Ptr-ICmp-Branch.ll
index af865ce7fac0..dcf241255d85 100644
--- a/test/Transforms/SimplifyCFG/2006-12-08-Ptr-ICmp-Branch.ll
+++ b/test/Transforms/SimplifyCFG/2006-12-08-Ptr-ICmp-Branch.ll
@@ -45,42 +45,42 @@ entry:
 	store %struct.trie_s* %t, %struct.trie_s** %t_addr
 	store %struct.FILE* %f, %struct.FILE** %f_addr
 	store i32 0, i32* %wstate
-	%tmp = getelementptr %struct.charsequence* %cs, i64 0, i32 0		; <i8**> [#uses=1]
-	%tmp1 = getelementptr %struct.charsequence* @C.0.2294, i64 0, i32 0		; <i8**> [#uses=1]
-	%tmp.upgrd.5 = load i8** %tmp1		; <i8*> [#uses=1]
+	%tmp = getelementptr %struct.charsequence, %struct.charsequence* %cs, i64 0, i32 0		; <i8**> [#uses=1]
+	%tmp1 = getelementptr %struct.charsequence, %struct.charsequence* @C.0.2294, i64 0, i32 0		; <i8**> [#uses=1]
+	%tmp.upgrd.5 = load i8*, i8** %tmp1		; <i8*> [#uses=1]
 	store i8* %tmp.upgrd.5, i8** %tmp
-	%tmp.upgrd.6 = getelementptr %struct.charsequence* %cs, i64 0, i32 1		; <i32*> [#uses=1]
-	%tmp2 = getelementptr %struct.charsequence* @C.0.2294, i64 0, i32 1		; <i32*> [#uses=1]
-	%tmp.upgrd.7 = load i32* %tmp2		; <i32> [#uses=1]
+	%tmp.upgrd.6 = getelementptr %struct.charsequence, %struct.charsequence* %cs, i64 0, i32 1		; <i32*> [#uses=1]
+	%tmp2 = getelementptr %struct.charsequence, %struct.charsequence* @C.0.2294, i64 0, i32 1		; <i32*> [#uses=1]
+	%tmp.upgrd.7 = load i32, i32* %tmp2		; <i32> [#uses=1]
 	store i32 %tmp.upgrd.7, i32* %tmp.upgrd.6
-	%tmp3 = getelementptr %struct.charsequence* %cs, i64 0, i32 2		; <i32*> [#uses=1]
-	%tmp4 = getelementptr %struct.charsequence* @C.0.2294, i64 0, i32 2		; <i32*> [#uses=1]
-	%tmp5 = load i32* %tmp4		; <i32> [#uses=1]
+	%tmp3 = getelementptr %struct.charsequence, %struct.charsequence* %cs, i64 0, i32 2		; <i32*> [#uses=1]
+	%tmp4 = getelementptr %struct.charsequence, %struct.charsequence* @C.0.2294, i64 0, i32 2		; <i32*> [#uses=1]
+	%tmp5 = load i32, i32* %tmp4		; <i32> [#uses=1]
 	store i32 %tmp5, i32* %tmp3
 	br label %bb33
 bb:		; preds = %bb33
-	%tmp.upgrd.8 = load %struct.FILE** %f_addr		; <%struct.FILE*> [#uses=1]
+	%tmp.upgrd.8 = load %struct.FILE*, %struct.FILE** %f_addr		; <%struct.FILE*> [#uses=1]
 	%tmp.upgrd.9 = call i32 @_IO_getc( %struct.FILE* %tmp.upgrd.8 )		; <i32> [#uses=1]
 	%tmp6 = call i32 @tolower( i32 %tmp.upgrd.9 )		; <i32> [#uses=1]
 	%tmp6.upgrd.10 = trunc i32 %tmp6 to i8		; <i8> [#uses=1]
 	store i8 %tmp6.upgrd.10, i8* %c
-	%tmp7 = load i32* %wstate		; <i32> [#uses=1]
+	%tmp7 = load i32, i32* %wstate		; <i32> [#uses=1]
 	%tmp.upgrd.11 = icmp ne i32 %tmp7, 0		; <i1> [#uses=1]
 	br i1 %tmp.upgrd.11, label %cond_true, label %cond_false
 cond_true:		; preds = %bb
-	%tmp.upgrd.12 = load i8* %c		; <i8> [#uses=1]
+	%tmp.upgrd.12 = load i8, i8* %c		; <i8> [#uses=1]
 	%tmp8 = icmp sle i8 %tmp.upgrd.12, 96		; <i1> [#uses=1]
 	br i1 %tmp8, label %cond_true9, label %cond_next
 cond_true9:		; preds = %cond_true
 	br label %bb16
 cond_next:		; preds = %cond_true
-	%tmp10 = load i8* %c		; <i8> [#uses=1]
+	%tmp10 = load i8, i8* %c		; <i8> [#uses=1]
 	%tmp11 = icmp sgt i8 %tmp10, 122		; <i1> [#uses=1]
 	br i1 %tmp11, label %cond_true12, label %cond_next13
 cond_true12:		; preds = %cond_next
 	br label %bb16
 cond_next13:		; preds = %cond_next
-	%tmp14 = load i8* %c		; <i8> [#uses=1]
+	%tmp14 = load i8, i8* %c		; <i8> [#uses=1]
 	%tmp14.upgrd.13 = sext i8 %tmp14 to i32		; <i32> [#uses=1]
 	%tmp1415 = trunc i32 %tmp14.upgrd.13 to i8		; <i8> [#uses=1]
 	call void @charsequence_push( %struct.charsequence* %cs, i8 %tmp1415 )
@@ -88,26 +88,26 @@ cond_next13:		; preds = %cond_next
 bb16:		; preds = %cond_true12, %cond_true9
 	%tmp17 = call i8* @charsequence_val( %struct.charsequence* %cs )		; <i8*> [#uses=1]
 	store i8* %tmp17, i8** %str
-	%tmp.upgrd.14 = load %struct.trie_s** %t_addr		; <%struct.trie_s*> [#uses=1]
-	%tmp18 = load i8** %str		; <i8*> [#uses=1]
+	%tmp.upgrd.14 = load %struct.trie_s*, %struct.trie_s** %t_addr		; <%struct.trie_s*> [#uses=1]
+	%tmp18 = load i8*, i8** %str		; <i8*> [#uses=1]
 	%tmp19 = call %struct.trie_s* @trie_insert( %struct.trie_s* %tmp.upgrd.14, i8* %tmp18 )		; <%struct.trie_s*> [#uses=0]
-	%tmp20 = load i8** %str		; <i8*> [#uses=1]
+	%tmp20 = load i8*, i8** %str		; <i8*> [#uses=1]
 	call void @free( i8* %tmp20 )
 	store i32 0, i32* %wstate
 	br label %bb21
 bb21:		; preds = %bb16, %cond_next13
 	br label %cond_next32
 cond_false:		; preds = %bb
-	%tmp22 = load i8* %c		; <i8> [#uses=1]
+	%tmp22 = load i8, i8* %c		; <i8> [#uses=1]
 	%tmp23 = icmp sgt i8 %tmp22, 96		; <i1> [#uses=1]
 	br i1 %tmp23, label %cond_true24, label %cond_next31
 cond_true24:		; preds = %cond_false
-	%tmp25 = load i8* %c		; <i8> [#uses=1]
+	%tmp25 = load i8, i8* %c		; <i8> [#uses=1]
 	%tmp26 = icmp sle i8 %tmp25, 122		; <i1> [#uses=1]
 	br i1 %tmp26, label %cond_true27, label %cond_next30
 cond_true27:		; preds = %cond_true24
 	call void @charsequence_reset( %struct.charsequence* %cs )
-	%tmp28 = load i8* %c		; <i8> [#uses=1]
+	%tmp28 = load i8, i8* %c		; <i8> [#uses=1]
 	%tmp28.upgrd.15 = sext i8 %tmp28 to i32		; <i32> [#uses=1]
 	%tmp2829 = trunc i32 %tmp28.upgrd.15 to i8		; <i8> [#uses=1]
 	call void @charsequence_push( %struct.charsequence* %cs, i8 %tmp2829 )
@@ -120,7 +120,7 @@ cond_next31:		; preds = %cond_next30, %cond_false
 cond_next32:		; preds = %cond_next31, %bb21
 	br label %bb33
 bb33:		; preds = %cond_next32, %entry
-	%tmp34 = load %struct.FILE** %f_addr		; <%struct.FILE*> [#uses=1]
+	%tmp34 = load %struct.FILE*, %struct.FILE** %f_addr		; <%struct.FILE*> [#uses=1]
 	%tmp35 = call i32 @feof( %struct.FILE* %tmp34 )		; <i32> [#uses=1]
 	%tmp36 = icmp eq i32 %tmp35, 0		; <i1> [#uses=1]
 	br i1 %tmp36, label %bb, label %bb37
diff --git a/test/Transforms/SimplifyCFG/2007-11-22-InvokeNoUnwind.ll b/test/Transforms/SimplifyCFG/2007-11-22-InvokeNoUnwind.ll
index a90e07276253..76f41e8fc218 100644
--- a/test/Transforms/SimplifyCFG/2007-11-22-InvokeNoUnwind.ll
+++ b/test/Transforms/SimplifyCFG/2007-11-22-InvokeNoUnwind.ll
@@ -12,5 +12,9 @@ Cont:		; preds = %0
 	ret i32 0
 
 Other:		; preds = %0
+	landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
+		catch i8* null
 	ret i32 1
 }
+
+declare i32 @__gxx_personality_v0(...)
diff --git a/test/Transforms/SimplifyCFG/2007-12-21-Crash.ll b/test/Transforms/SimplifyCFG/2007-12-21-Crash.ll
index 46df0f0ed071..99041ede5d98 100644
--- a/test/Transforms/SimplifyCFG/2007-12-21-Crash.ll
+++ b/test/Transforms/SimplifyCFG/2007-12-21-Crash.ll
@@ -13,7 +13,7 @@ bb5.outer:		; preds = %bb5.outer.loopexit, %entry
 	br label %bb5
 
 bb5:		; preds = %bb5, %bb5.outer
-	%tmp6 = tail call i32 (...)* @foo( ) nounwind 		; <i32> [#uses=1]
+	%tmp6 = tail call i32 (...) @foo( ) nounwind 		; <i32> [#uses=1]
 	switch i32 %tmp6, label %bb13 [
 		 i32 -1, label %bb10
 		 i32 102, label %bb5
@@ -21,7 +21,7 @@ bb5:		; preds = %bb5, %bb5.outer
 	]
 
 bb10:		; preds = %bb5
-	%tmp12 = tail call i32 (...)* @bar( i32 %undo.0.ph ) nounwind 		; <i32> [#uses=0]
+	%tmp12 = tail call i32 (...) @bar( i32 %undo.0.ph ) nounwind 		; <i32> [#uses=0]
 	br label %UnifiedReturnBlock
 
 bb13:		; preds = %bb5
diff --git a/test/Transforms/SimplifyCFG/2008-01-02-hoist-fp-add.ll b/test/Transforms/SimplifyCFG/2008-01-02-hoist-fp-add.ll
index cf29b7159793..7625d935ab3d 100644
--- a/test/Transforms/SimplifyCFG/2008-01-02-hoist-fp-add.ll
+++ b/test/Transforms/SimplifyCFG/2008-01-02-hoist-fp-add.ll
@@ -1,27 +1,27 @@
-; The phi should not be eliminated in this case, because the fp op could trap.
+; The phi should not be eliminated in this case, because the divide op could trap.
 ; RUN: opt < %s -simplifycfg -S | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i686-apple-darwin8"
-@G = weak global double 0.000000e+00, align 8		; <double*> [#uses=2]
+@G = weak global i32 0, align 8		; <i32*> [#uses=2]
 
-define void @test(i32 %X, i32 %Y, double %Z) {
+define void @test(i32 %X, i32 %Y, i32 %Z) {
 entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
-	%tmp = load double* @G, align 8		; <double> [#uses=2]
+	%tmp = load i32, i32* @G, align 8		; <i32> [#uses=2]
 	%tmp3 = icmp eq i32 %X, %Y		; <i1> [#uses=1]
 	%tmp34 = zext i1 %tmp3 to i8		; <i8> [#uses=1]
 	%toBool = icmp ne i8 %tmp34, 0		; <i1> [#uses=1]
 	br i1 %toBool, label %cond_true, label %cond_next
 
 cond_true:		; preds = %entry
-	%tmp7 = fadd double %tmp, %Z		; <double> [#uses=1]
+	%tmp7 = udiv i32 %tmp, %Z		; <i32> [#uses=1]
 	br label %cond_next
 
 cond_next:		; preds = %cond_true, %entry
-; CHECK: = phi double
-	%F.0 = phi double [ %tmp, %entry ], [ %tmp7, %cond_true ]		; <double> [#uses=1]
-	store double %F.0, double* @G, align 8
+; CHECK: = phi i32
+	%F.0 = phi i32 [ %tmp, %entry ], [ %tmp7, %cond_true ]		; <i32> [#uses=1]
+	store i32 %F.0, i32* @G, align 8
 	ret void
 }
 
diff --git a/test/Transforms/SimplifyCFG/2008-07-13-InfLoopMiscompile.ll b/test/Transforms/SimplifyCFG/2008-07-13-InfLoopMiscompile.ll
index 9b6084f0e1af..154677b0747f 100644
--- a/test/Transforms/SimplifyCFG/2008-07-13-InfLoopMiscompile.ll
+++ b/test/Transforms/SimplifyCFG/2008-07-13-InfLoopMiscompile.ll
@@ -9,7 +9,7 @@ target triple = "i386-pc-linux-gnu"
 
 define i32 @main() nounwind  {
 entry:
-	%l = load i32* @g_37, align 4		; <i32> [#uses=1]
+	%l = load i32, i32* @g_37, align 4		; <i32> [#uses=1]
 	%cmpa = icmp ne i32 %l, 0		; <i1> [#uses=3]
 	br i1 %cmpa, label %func_1.exit, label %mooseblock
 
@@ -29,7 +29,7 @@ cowblock:		; preds = %beeblock, %monkeyblock
 
 func_1.exit:		; preds = %cowblock, %entry
 	%outval = phi i32 [ %cowval, %cowblock ], [ 1, %entry ]		; <i32> [#uses=1]
-	%pout = tail call i32 (i8*, ...)* @printf( i8* noalias  getelementptr ([4 x i8]* @.str, i32 0, i32 0), i32 %outval ) nounwind 		; <i32> [#uses=0]
+	%pout = tail call i32 (i8*, ...) @printf( i8* noalias  getelementptr ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %outval ) nounwind 		; <i32> [#uses=0]
 	ret i32 0
 }
 
diff --git a/test/Transforms/SimplifyCFG/2008-09-08-MultiplePred.ll b/test/Transforms/SimplifyCFG/2008-09-08-MultiplePred.ll
index ac9622d43c31..6b216f598efb 100644
--- a/test/Transforms/SimplifyCFG/2008-09-08-MultiplePred.ll
+++ b/test/Transforms/SimplifyCFG/2008-09-08-MultiplePred.ll
@@ -4,7 +4,7 @@
 
 define i32 @func_127(i32 %p_129) nounwind {
 entry:
-	load i32* @g_103, align 4		; <i32>:0 [#uses=1]
+	load i32, i32* @g_103, align 4		; <i32>:0 [#uses=1]
 	icmp eq i32 %0, 0		; <i1>:1 [#uses=2]
 	br i1 %1, label %bb6.preheader, label %entry.return_crit_edge
 
diff --git a/test/Transforms/SimplifyCFG/2008-12-16-DCECond.ll b/test/Transforms/SimplifyCFG/2008-12-16-DCECond.ll
index 727102435fc7..4fc21d942237 100644
--- a/test/Transforms/SimplifyCFG/2008-12-16-DCECond.ll
+++ b/test/Transforms/SimplifyCFG/2008-12-16-DCECond.ll
@@ -9,7 +9,7 @@ entry:
 	br i1 %cmp, label %ifthen, label %ifend
 
 ifthen:		; preds = %entry
-	%call = call i32 (...)* @foo()		; <i32> [#uses=0]
+	%call = call i32 (...) @foo()		; <i32> [#uses=0]
 	br label %ifend
 
 ifend:		; preds = %ifthen, %entry
@@ -17,7 +17,7 @@ ifend:		; preds = %ifthen, %entry
 	br i1 %cmp2, label %ifthen3, label %ifend5
 
 ifthen3:		; preds = %ifend
-	%call4 = call i32 (...)* @foo()		; <i32> [#uses=0]
+	%call4 = call i32 (...) @foo()		; <i32> [#uses=0]
 	br label %ifend5
 
 ifend5:		; preds = %ifthen3, %ifend
@@ -25,7 +25,7 @@ ifend5:		; preds = %ifthen3, %ifend
 	br i1 %cmp7, label %ifthen8, label %ifend10
 
 ifthen8:		; preds = %ifend5
-	%call9 = call i32 (...)* @bar()		; <i32> [#uses=0]
+	%call9 = call i32 (...) @bar()		; <i32> [#uses=0]
 	br label %ifend10
 
 ifend10:		; preds = %ifthen8, %ifend5
@@ -33,7 +33,7 @@ ifend10:		; preds = %ifthen8, %ifend5
 	br i1 %cmp12, label %ifthen13, label %ifend15
 
 ifthen13:		; preds = %ifend10
-	%call14 = call i32 (...)* @bar()		; <i32> [#uses=0]
+	%call14 = call i32 (...) @bar()		; <i32> [#uses=0]
 	br label %ifend15
 
 ifend15:		; preds = %ifthen13, %ifend10
diff --git a/test/Transforms/SimplifyCFG/2009-05-12-externweak.ll b/test/Transforms/SimplifyCFG/2009-05-12-externweak.ll
index 419feb6b56a1..faf3f5f8b2a7 100644
--- a/test/Transforms/SimplifyCFG/2009-05-12-externweak.ll
+++ b/test/Transforms/SimplifyCFG/2009-05-12-externweak.ll
@@ -18,7 +18,7 @@ bb:		; preds = %bb4
 	br i1 icmp ne (i32* @i, i32* null), label %bb1, label %bb2
 
 bb1:		; preds = %bb
-	%0 = load i32* @i, align 4		; <i32> [#uses=1]
+	%0 = load i32, i32* @i, align 4		; <i32> [#uses=1]
 	br label %bb3
 
 bb2:		; preds = %bb
diff --git a/test/Transforms/SimplifyCFG/AArch64/lit.local.cfg b/test/Transforms/SimplifyCFG/AArch64/lit.local.cfg
new file mode 100644
index 000000000000..6642d2870680
--- /dev/null
+++ b/test/Transforms/SimplifyCFG/AArch64/lit.local.cfg
@@ -0,0 +1,5 @@
+config.suffixes = ['.ll']
+
+targets = set(config.root.targets_to_build.split())
+if not 'AArch64' in targets:
+    config.unsupported = True
diff --git a/test/Transforms/SimplifyCFG/AArch64/prefer-fma.ll b/test/Transforms/SimplifyCFG/AArch64/prefer-fma.ll
new file mode 100644
index 000000000000..cfbe219c4c2d
--- /dev/null
+++ b/test/Transforms/SimplifyCFG/AArch64/prefer-fma.ll
@@ -0,0 +1,72 @@
+; RUN: opt < %s -mtriple=aarch64-linux-gnu -simplifycfg -enable-unsafe-fp-math -S >%t
+; RUN: FileCheck %s < %t
+; ModuleID = 't.cc'
+
+; Function Attrs: nounwind
+define double @_Z3fooRdS_S_S_(double* dereferenceable(8) %x, double* dereferenceable(8) %y, double* dereferenceable(8) %a) #0 {
+entry:
+  %0 = load double, double* %y, align 8
+  %cmp = fcmp oeq double %0, 0.000000e+00
+  %1 = load double, double* %x, align 8
+  br i1 %cmp, label %if.then, label %if.else
+
+; fadd (const, (fmul x, y))
+if.then:                                          ; preds = %entry
+; CHECK-LABEL: if.then:
+; CHECK:   %3 = fmul fast double %1, %2
+; CHECK-NEXT:   %mul = fadd fast double 1.000000e+00, %3
+  %2 = load double, double* %a, align 8
+  %3 = fmul fast double %1, %2
+  %mul = fadd fast double 1.000000e+00, %3
+  store double %mul, double* %y, align 8
+  br label %if.end
+
+; fsub ((fmul x, y), z)
+if.else:                                          ; preds = %entry
+; CHECK-LABEL: if.else:
+; CHECK:   %mul1 = fmul fast double %1, %2
+; CHECK-NEXT:   %sub1 = fsub fast double %mul1, %0
+  %4 = load double, double* %a, align 8
+  %mul1 = fmul fast double %1, %4
+  %sub1 = fsub fast double %mul1, %0
+  store double %sub1, double* %y, align 8
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  %5 = load double, double* %y, align 8
+  %cmp2 = fcmp oeq double %5, 2.000000e+00
+  %6 = load double, double* %x, align 8
+  br i1 %cmp2, label %if.then2, label %if.else2
+
+; fsub (x, (fmul y, z))
+if.then2:                                         ; preds = %entry
+; CHECK-LABEL: if.then2:
+; CHECK:   %7 = fmul fast double %5, 3.000000e+00
+; CHECK-NEXT:   %mul2 = fsub fast double %6, %7
+  %7 = load double, double* %a, align 8
+  %8 = fmul fast double %6, 3.0000000e+00
+  %mul2 = fsub fast double %7, %8
+  store double %mul2, double* %y, align 8
+  br label %if.end2
+
+; fsub (fneg((fmul x, y)), const)
+if.else2:                                         ; preds = %entry
+; CHECK-LABEL: if.else2:
+; CHECK:   %mul3 = fmul fast double %5, 3.000000e+00
+; CHECK-NEXT:   %neg = fsub fast double 0.000000e+00, %mul3
+; CHECK-NEXT:   %sub2 = fsub fast double %neg, 3.000000e+00
+  %mul3 = fmul fast double %6, 3.0000000e+00
+  %neg = fsub fast double 0.0000000e+00, %mul3
+  %sub2 = fsub fast double %neg, 3.0000000e+00
+  store double %sub2, double* %y, align 8
+  br label %if.end2
+
+if.end2:                                           ; preds = %if.else, %if.then
+  %9 = load double, double* %x, align 8
+  %10 = load double, double* %y, align 8
+  %add = fadd fast double %9, %10
+  %11 = load double, double* %a, align 8
+  %add2 = fadd fast double %add, %11
+  ret double %add2
+}
+
diff --git a/test/Transforms/SimplifyCFG/EmptyBlockMerge.ll b/test/Transforms/SimplifyCFG/EmptyBlockMerge.ll
index aba08dc073a8..32a0202364d9 100644
--- a/test/Transforms/SimplifyCFG/EmptyBlockMerge.ll
+++ b/test/Transforms/SimplifyCFG/EmptyBlockMerge.ll
@@ -6,7 +6,7 @@ declare void @foo()
 
 define void @cprop_test12(i32* %data) {
 bb0:
-	%reg108 = load i32* %data		; <i32> [#uses=2]
+	%reg108 = load i32, i32* %data		; <i32> [#uses=2]
 	%cond218 = icmp ne i32 %reg108, 5		; <i1> [#uses=1]
 	br i1 %cond218, label %bb3, label %bb2
 bb2:		; preds = %bb0
diff --git a/test/Transforms/SimplifyCFG/MagicPointer.ll b/test/Transforms/SimplifyCFG/MagicPointer.ll
index b8b8cbd9dc63..7789600f3f0c 100644
--- a/test/Transforms/SimplifyCFG/MagicPointer.ll
+++ b/test/Transforms/SimplifyCFG/MagicPointer.ll
@@ -33,7 +33,7 @@ entry:
   br i1 %tobool, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  %call = call i32 @puts(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+  %call = call i32 @puts(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
   br label %if.end21
 
 if.else:                                          ; preds = %entry
@@ -41,7 +41,7 @@ if.else:                                          ; preds = %entry
   br i1 %cmp, label %if.then2, label %if.else4
 
 if.then2:                                         ; preds = %if.else
-  %call3 = call i32 @puts(i8* getelementptr inbounds ([4 x i8]* @.str1, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+  %call3 = call i32 @puts(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str1, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
   br label %if.end20
 
 if.else4:                                         ; preds = %if.else
@@ -53,7 +53,7 @@ lor.lhs.false:                                    ; preds = %if.else4
   br i1 %cmp8, label %if.then9, label %if.else11
 
 if.then9:                                         ; preds = %lor.lhs.false, %if.else4
-  %call10 = call i32 @puts(i8* getelementptr inbounds ([4 x i8]* @.str2, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+  %call10 = call i32 @puts(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str2, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
   br label %if.end19
 
 if.else11:                                        ; preds = %lor.lhs.false
@@ -61,7 +61,7 @@ if.else11:                                        ; preds = %lor.lhs.false
   br i1 %cmp13, label %if.then14, label %if.else16
 
 if.then14:                                        ; preds = %if.else11
-  %call15 = call i32 @puts(i8* getelementptr inbounds ([5 x i8]* @.str3, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+  %call15 = call i32 @puts(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str3, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
   br label %if.end
 
 if.else16:                                        ; preds = %if.else11
@@ -99,7 +99,7 @@ entry:
   br i1 %tobool, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
-  %call = call i32 @puts_as1(i8 addrspace(1)* getelementptr inbounds ([5 x i8] addrspace(1)* @.str_as1, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+  %call = call i32 @puts_as1(i8 addrspace(1)* getelementptr inbounds ([5 x i8], [5 x i8] addrspace(1)* @.str_as1, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
   br label %if.end21
 
 if.else:                                          ; preds = %entry
@@ -107,7 +107,7 @@ if.else:                                          ; preds = %entry
   br i1 %cmp, label %if.then2, label %if.else4
 
 if.then2:                                         ; preds = %if.else
-  %call3 = call i32 @puts_as1(i8 addrspace(1)* getelementptr inbounds ([4 x i8] addrspace(1)* @.str1_as1, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+  %call3 = call i32 @puts_as1(i8 addrspace(1)* getelementptr inbounds ([4 x i8], [4 x i8] addrspace(1)* @.str1_as1, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
   br label %if.end20
 
 if.else4:                                         ; preds = %if.else
@@ -119,7 +119,7 @@ lor.lhs.false:                                    ; preds = %if.else4
   br i1 %cmp8, label %if.then9, label %if.else11
 
 if.then9:                                         ; preds = %lor.lhs.false, %if.else4
-  %call10 = call i32 @puts_as1(i8 addrspace(1)* getelementptr inbounds ([4 x i8] addrspace(1)* @.str2_as1, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+  %call10 = call i32 @puts_as1(i8 addrspace(1)* getelementptr inbounds ([4 x i8], [4 x i8] addrspace(1)* @.str2_as1, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
   br label %if.end19
 
 if.else11:                                        ; preds = %lor.lhs.false
@@ -127,7 +127,7 @@ if.else11:                                        ; preds = %lor.lhs.false
   br i1 %cmp13, label %if.then14, label %if.else16
 
 if.then14:                                        ; preds = %if.else11
-  %call15 = call i32 @puts_as1(i8 addrspace(1)* getelementptr inbounds ([5 x i8] addrspace(1)* @.str3_as1, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+  %call15 = call i32 @puts_as1(i8 addrspace(1)* getelementptr inbounds ([5 x i8], [5 x i8] addrspace(1)* @.str3_as1, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
   br label %if.end
 
 if.else16:                                        ; preds = %if.else11
diff --git a/test/Transforms/SimplifyCFG/PR17073.ll b/test/Transforms/SimplifyCFG/PR17073.ll
index 8dc9fb28d617..e6e98b266879 100644
--- a/test/Transforms/SimplifyCFG/PR17073.ll
+++ b/test/Transforms/SimplifyCFG/PR17073.ll
@@ -18,7 +18,7 @@ target triple = "i386-apple-macosx10.9.0"
 ; CHECK-NOT: select i1 %tobool, i32* null, i32* select (i1 icmp eq (i64 urem (i64 2, i64 zext (i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) to i64)), i64 0), i32* null, i32* @a) 
 define i32* @can_trap1() {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %exit, label %block1
 
@@ -38,7 +38,7 @@ exit:
 ; CHECK-NOT: select i1 %tobool, i32* select (i1 icmp eq (i64 urem (i64 2, i64 zext (i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) to i64)), i64 0), i32* null, i32* @a), i32* null
 define i32* @can_trap2() {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %exit, label %block1
 
@@ -57,7 +57,7 @@ exit:
 ; CHECK: select i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a), i32* select (i1 icmp eq (i64 add (i64 zext (i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) to i64), i64 2), i64 0), i32* null, i32* @a), i32* null
 define i32* @cannot_trap() {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %exit, label %block1
 
diff --git a/test/Transforms/SimplifyCFG/PhiBlockMerge.ll b/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
index 36b52f52d490..555082921b96 100644
--- a/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
+++ b/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
@@ -4,9 +4,7 @@
 ;
 
 define i32 @test(i1 %a, i1 %b) {
-; CHECK: br i1 %a
         br i1 %a, label %M, label %O
-; CHECK: O:
 O:              ; preds = %0
 ; CHECK: select i1 %b, i32 0, i32 1
 ; CHECK-NOT: phi
@@ -18,9 +16,9 @@ N:              ; preds = %Q, %O
         %Wp = phi i32 [ 0, %O ], [ 1, %Q ]              ; <i32> [#uses=1]
         br label %M
 M:              ; preds = %N, %0
-; CHECK: %W = phi i32
         %W = phi i32 [ %Wp, %N ], [ 2, %0 ]             ; <i32> [#uses=1]
         %R = add i32 %W, 1              ; <i32> [#uses=1]
         ret i32 %R
+; CHECK: ret
 }
 
diff --git a/test/Transforms/SimplifyCFG/PowerPC/cttz-ctlz-spec.ll b/test/Transforms/SimplifyCFG/PowerPC/cttz-ctlz-spec.ll
new file mode 100644
index 000000000000..fa74549710f4
--- /dev/null
+++ b/test/Transforms/SimplifyCFG/PowerPC/cttz-ctlz-spec.ll
@@ -0,0 +1,45 @@
+; RUN: opt -S -simplifycfg < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define i64 @test1(i64 %A) {
+; CHECK-LABEL: @test1(
+; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
+; CHECK-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
+; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
+; CHECK-NEXT: ret i64 [[SEL]]
+entry:
+  %tobool = icmp eq i64 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i64 [ %0, %cond.true ], [ 64, %entry ]
+  ret i64 %cond
+}
+
+define i64 @test1b(i64 %A) {
+; CHECK-LABEL: @test1b(
+; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
+; CHECK-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
+; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
+; CHECK-NEXT: ret i64 [[SEL]]
+entry:
+  %tobool = icmp eq i64 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i64 [ %0, %cond.true ], [ 64, %entry ]
+  ret i64 %cond
+}
+
+declare i64 @llvm.ctlz.i64(i64, i1)
+declare i64 @llvm.cttz.i64(i64, i1)
+
diff --git a/test/Transforms/SimplifyCFG/PowerPC/lit.local.cfg b/test/Transforms/SimplifyCFG/PowerPC/lit.local.cfg
new file mode 100644
index 000000000000..091332439b18
--- /dev/null
+++ b/test/Transforms/SimplifyCFG/PowerPC/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'PowerPC' in config.root.targets:
+    config.unsupported = True
diff --git a/test/Transforms/SimplifyCFG/R600/cttz-ctlz.ll b/test/Transforms/SimplifyCFG/R600/cttz-ctlz.ll
new file mode 100644
index 000000000000..5b2799494647
--- /dev/null
+++ b/test/Transforms/SimplifyCFG/R600/cttz-ctlz.ll
@@ -0,0 +1,249 @@
+; RUN: opt -S -simplifycfg -mtriple=r600-unknown-unknown -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=ALL %s
+; RUN: opt -S -simplifycfg -mtriple=r600-unknown-unknown -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=ALL %s
+
+
+define i64 @test1(i64 %A) {
+; ALL-LABEL: @test1(
+; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
+; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
+; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
+; SI-NEXT: ret i64 [[SEL]]
+entry:
+  %tobool = icmp eq i64 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i64 [ %0, %cond.true ], [ 64, %entry ]
+  ret i64 %cond
+}
+
+
+define i32 @test2(i32 %A) {
+; ALL-LABEL: @test2(
+; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
+; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
+; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTLZ]]
+; SI-NEXT: ret i32 [[SEL]]
+entry:
+  %tobool = icmp eq i32 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i32 [ %0, %cond.true ], [ 32, %entry ]
+  ret i32 %cond
+}
+
+
+define signext i16 @test3(i16 signext %A) {
+; ALL-LABEL: @test3(
+; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i16 %A, 0
+; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
+; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTLZ]]
+; SI-NEXT: ret i16 [[SEL]]
+entry:
+  %tobool = icmp eq i16 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i16 [ %0, %cond.true ], [ 16, %entry ]
+  ret i16 %cond
+}
+
+
+define i64 @test1b(i64 %A) {
+; ALL-LABEL: @test1b(
+; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
+; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
+; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTTZ]]
+; SI-NEXT: ret i64 [[SEL]]
+entry:
+  %tobool = icmp eq i64 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i64 [ %0, %cond.true ], [ 64, %entry ]
+  ret i64 %cond
+}
+
+
+define i32 @test2b(i32 %A) {
+; ALL-LABEL: @test2b(
+; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
+; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
+; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTTZ]]
+; SI-NEXT: ret i32 [[SEL]]
+entry:
+  %tobool = icmp eq i32 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i32 [ %0, %cond.true ], [ 32, %entry ]
+  ret i32 %cond
+}
+
+
+define signext i16 @test3b(i16 signext %A) {
+; ALL-LABEL: @test3b(
+; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i16 %A, 0
+; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
+; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTTZ]]
+; SI-NEXT: ret i16 [[SEL]]
+entry:
+  %tobool = icmp eq i16 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i16 [ %0, %cond.true ], [ 16, %entry ]
+  ret i16 %cond
+}
+
+
+define i64 @test1c(i64 %A) {
+; ALL-LABEL: @test1c(
+; ALL: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
+; ALL-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
+; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 63, i64 [[CTLZ]]
+; ALL-NEXT: ret i64 [[SEL]]
+entry:
+  %tobool = icmp eq i64 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i64 [ %0, %cond.true ], [ 63, %entry ]
+  ret i64 %cond
+}
+
+define i32 @test2c(i32 %A) {
+; ALL-LABEL: @test2c(
+; ALL: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
+; ALL-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
+; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 31, i32 [[CTLZ]]
+; ALL-NEXT: ret i32 [[SEL]]
+entry:
+  %tobool = icmp eq i32 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i32 [ %0, %cond.true ], [ 31, %entry ]
+  ret i32 %cond
+}
+
+
+define signext i16 @test3c(i16 signext %A) {
+; ALL-LABEL: @test3c(
+; ALL: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i16 %A, 0
+; ALL-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
+; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 15, i16 [[CTLZ]]
+; ALL-NEXT: ret i16 [[SEL]]
+entry:
+  %tobool = icmp eq i16 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i16 [ %0, %cond.true ], [ 15, %entry ]
+  ret i16 %cond
+}
+
+
+define i64 @test1d(i64 %A) {
+; ALL-LABEL: @test1d(
+; ALL: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
+; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
+; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 63, i64 [[CTTZ]]
+; ALL-NEXT: ret i64 [[SEL]]
+entry:
+  %tobool = icmp eq i64 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i64 [ %0, %cond.true ], [ 63, %entry ]
+  ret i64 %cond
+}
+
+
+define i32 @test2d(i32 %A) {
+; ALL-LABEL: @test2d(
+; ALL: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
+; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
+; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 31, i32 [[CTTZ]]
+; ALL-NEXT: ret i32 [[SEL]]
+entry:
+  %tobool = icmp eq i32 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i32 [ %0, %cond.true ], [ 31, %entry ]
+  ret i32 %cond
+}
+
+
+define signext i16 @test3d(i16 signext %A) {
+; ALL-LABEL: @test3d(
+; ALL: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i16 %A, 0
+; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
+; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 15, i16 [[CTTZ]]
+; ALL-NEXT: ret i16 [[SEL]]
+entry:
+  %tobool = icmp eq i16 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i16 [ %0, %cond.true ], [ 15, %entry ]
+  ret i16 %cond
+}
+
+
+declare i64 @llvm.ctlz.i64(i64, i1)
+declare i32 @llvm.ctlz.i32(i32, i1)
+declare i16 @llvm.ctlz.i16(i16, i1)
+declare i64 @llvm.cttz.i64(i64, i1)
+declare i32 @llvm.cttz.i32(i32, i1)
+declare i16 @llvm.cttz.i16(i16, i1)
diff --git a/test/Transforms/SimplifyCFG/R600/lit.local.cfg b/test/Transforms/SimplifyCFG/R600/lit.local.cfg
new file mode 100644
index 000000000000..ad9ce2541ef7
--- /dev/null
+++ b/test/Transforms/SimplifyCFG/R600/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'R600' in config.root.targets:
+    config.unsupported = True
diff --git a/test/Transforms/SimplifyCFG/SpeculativeExec.ll b/test/Transforms/SimplifyCFG/SpeculativeExec.ll
index 83fa41900035..c23a96df52ee 100644
--- a/test/Transforms/SimplifyCFG/SpeculativeExec.ll
+++ b/test/Transforms/SimplifyCFG/SpeculativeExec.ll
@@ -28,33 +28,17 @@ bb3:		; preds = %bb2, %entry
 	ret i32 %tmp5
 }
 
-declare i8 @llvm.cttz.i8(i8, i1)
-
-define i8 @test2(i8 %a) {
-; CHECK-LABEL: @test2(
-  br i1 undef, label %bb_true, label %bb_false
-bb_true:
-  %b = tail call i8 @llvm.cttz.i8(i8 %a, i1 false)
-  br label %join
-bb_false:
-  br label %join
-join:
-  %c = phi i8 [%b, %bb_true], [%a, %bb_false]
-; CHECK: select
-  ret i8 %c
-}
-
 define i8* @test4(i1* %dummy, i8* %a, i8* %b) {
 ; Test that we don't speculate an arbitrarily large number of unfolded constant
 ; expressions.
 ; CHECK-LABEL: @test4(
 
 entry:
-  %cond1 = load volatile i1* %dummy
+  %cond1 = load volatile i1, i1* %dummy
   br i1 %cond1, label %if, label %end
 
 if:
-  %cond2 = load volatile i1* %dummy
+  %cond2 = load volatile i1, i1* %dummy
   br i1 %cond2, label %then, label %end
 
 then:
diff --git a/test/Transforms/SimplifyCFG/UnreachableEliminate.ll b/test/Transforms/SimplifyCFG/UnreachableEliminate.ll
index 21428c62f531..8718c552c693 100644
--- a/test/Transforms/SimplifyCFG/UnreachableEliminate.ll
+++ b/test/Transforms/SimplifyCFG/UnreachableEliminate.ll
@@ -22,11 +22,15 @@ entry:
         invoke void @test2( )
                         to label %N unwind label %U
 U:
+  %res = landingpad { i8* } personality i32 (...)* @__gxx_personality_v0
+          cleanup
         unreachable
 N:
         ret void
 }
 
+declare i32 @__gxx_personality_v0(...)
+
 define i32 @test3(i32 %v) {
 ; CHECK-LABEL: @test3(
 ; CHECK: entry:
@@ -46,32 +50,6 @@ T:
         ret i32 2
 }
 
-; PR9450
-define i32 @test4(i32 %v, i32 %w) {
-; CHECK: entry:
-; CHECK-NEXT:  switch i32 %v, label %T [
-; CHECK-NEXT:    i32 3, label %V
-; CHECK-NEXT:    i32 2, label %U
-; CHECK-NEXT:  ]
-
-entry:
-        br label %SWITCH
-V:
-        ret i32 7
-SWITCH:
-        switch i32 %v, label %default [
-                 i32 1, label %T
-                 i32 2, label %U
-                 i32 3, label %V
-        ]
-default:
-        unreachable
-U:
-        ret i32 %w
-T:
-        ret i32 2
-}
-
 
 ;; We can either convert the following control-flow to a select or remove the
 ;; unreachable control flow because of the undef store of null. Make sure we do
diff --git a/test/Transforms/SimplifyCFG/X86/speculate-cttz-ctlz.ll b/test/Transforms/SimplifyCFG/X86/speculate-cttz-ctlz.ll
new file mode 100644
index 000000000000..69f6c69059d4
--- /dev/null
+++ b/test/Transforms/SimplifyCFG/X86/speculate-cttz-ctlz.ll
@@ -0,0 +1,330 @@
+; RUN: opt -S -simplifycfg -mtriple=x86_64-unknown-unknown -mattr=+bmi < %s | FileCheck %s --check-prefix=ALL --check-prefix=BMI
+; RUN: opt -S -simplifycfg -mtriple=x86_64-unknown-unknown -mattr=+lzcnt < %s | FileCheck %s --check-prefix=ALL --check-prefix=LZCNT
+; RUN: opt -S -simplifycfg -mtriple=x86_64-unknown-unknown < %s | FileCheck %s --check-prefix=ALL --check-prefix=GENERIC
+
+
+define i64 @test1(i64 %A) {
+; ALL-LABEL: @test1(
+; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
+; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
+; LZCNT-NEXT: select i1 [[COND]], i64 64, i64 [[CTLZ]]
+; BMI-NOT: select
+; GENERIC-NOT: select
+; ALL: ret
+entry:
+  %tobool = icmp eq i64 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i64 [ %0, %cond.true ], [ 64, %entry ]
+  ret i64 %cond
+}
+
+define i32 @test2(i32 %A) {
+; ALL-LABEL: @test2(
+; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
+; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
+; LZCNT-NEXT: select i1 [[COND]], i32 32, i32 [[CTLZ]]
+; BMI-NOT: select
+; GENERIC-NOT: select
+; ALL: ret
+entry:
+  %tobool = icmp eq i32 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i32 [ %0, %cond.true ], [ 32, %entry ]
+  ret i32 %cond
+}
+
+
+define signext i16 @test3(i16 signext %A) {
+; ALL-LABEL: @test3(
+; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i16 %A, 0
+; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
+; LZCNT-NEXT: select i1 [[COND]], i16 16, i16 [[CTLZ]]
+; BMI-NOT: select
+; GENERIC-NOT: select
+; ALL: ret
+entry:
+  %tobool = icmp eq i16 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i16 [ %0, %cond.true ], [ 16, %entry ]
+  ret i16 %cond
+}
+
+
+define i64 @test1b(i64 %A) {
+; ALL-LABEL: @test1b(
+; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
+; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
+; BMI-NEXT: select i1 [[COND]], i64 64, i64 [[CTTZ]]
+; LZCNT-NOT: select
+; GENERIC-NOT: select
+; ALL: ret
+entry:
+  %tobool = icmp eq i64 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i64 [ %0, %cond.true ], [ 64, %entry ]
+  ret i64 %cond
+}
+
+
+define i32 @test2b(i32 %A) {
+; ALL-LABEL: @test2b(
+; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
+; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
+; BMI-NEXT: select i1 [[COND]], i32 32, i32 [[CTTZ]]
+; LZCNT-NOT: select
+; GENERIC-NOT: select
+; ALL: ret
+entry:
+  %tobool = icmp eq i32 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i32 [ %0, %cond.true ], [ 32, %entry ]
+  ret i32 %cond
+}
+
+
+define signext i16 @test3b(i16 signext %A) {
+; ALL-LABEL: @test3b(
+; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i16 %A, 0
+; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
+; BMI-NEXT: select i1 [[COND]], i16 16, i16 [[CTTZ]]
+; LZCNT-NOT: select
+; GENERIC-NOT: select
+; ALL: ret
+entry:
+  %tobool = icmp eq i16 %A, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i16 [ %0, %cond.true ], [ 16, %entry ]
+  ret i16 %cond
+}
+
+; The following tests verify that calls to cttz/ctlz are speculated even if
+; basic block %cond.true has an extra zero extend/truncate which is "free"
+; for the target.
+
+define i64 @test1e(i32 %x) {
+; ALL-LABEL: @test1e(
+; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %x, 0
+; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
+; ALL: [[ZEXT:%[A-Za-z0-9]+]] = zext i32 [[CTTZ]] to i64
+; BMI-NEXT: select i1 [[COND]], i64 32, i64 [[ZEXT]]
+; LZCNT-NOT: select
+; GENERIC-NOT: select
+; ALL: ret
+entry:
+  %tobool = icmp eq i32 %x, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
+  %phitmp2 = zext i32 %0 to i64
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i64 [ %phitmp2, %cond.true ], [ 32, %entry ]
+  ret i64 %cond
+}
+
+define i32 @test2e(i64 %x) {
+; ALL-LABEL: @test2e(
+; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %x, 0
+; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
+; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTTZ]] to i32
+; BMI-NEXT: select i1 [[COND]], i32 64, i32 [[TRUNC]]
+; LZCNT-NOT: select
+; GENERIC-NOT: select
+; ALL: ret
+entry:
+  %tobool = icmp eq i64 %x, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
+  %cast = trunc i64 %0 to i32
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i32 [ %cast, %cond.true ], [ 64, %entry ]
+  ret i32 %cond
+}
+
+define i64 @test3e(i32 %x) {
+; ALL-LABEL: @test3e(
+; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %x, 0
+; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+; ALL: [[ZEXT:%[A-Za-z0-9]+]] = zext i32 [[CTLZ]] to i64
+; LZCNT-NEXT: select i1 [[COND]], i64 32, i64 [[ZEXT]]
+; BMI-NOT: select
+; GENERIC-NOT: select
+; ALL: ret
+entry:
+  %tobool = icmp eq i32 %x, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+  %phitmp2 = zext i32 %0 to i64
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i64 [ %phitmp2, %cond.true ], [ 32, %entry ]
+  ret i64 %cond
+}
+
+define i32 @test4e(i64 %x) {
+; ALL-LABEL: @test4e(
+; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %x, 0
+; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
+; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTLZ]] to i32
+; LZCNT-NEXT: select i1 [[COND]], i32 64, i32 [[TRUNC]]
+; BMI-NOT: select
+; GENERIC-NOT: select
+; ALL: ret
+entry:
+  %tobool = icmp eq i64 %x, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
+  %cast = trunc i64 %0 to i32
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i32 [ %cast, %cond.true ], [ 64, %entry ]
+  ret i32 %cond
+}
+
+define i16 @test5e(i64 %x) {
+; ALL-LABEL: @test5e(
+; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %x, 0
+; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
+; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTLZ]] to i16
+; LZCNT-NEXT: select i1 [[COND]], i16 64, i16 [[TRUNC]]
+; BMI-NOT: select
+; GENERIC-NOT: select
+; ALL: ret
+entry:
+  %tobool = icmp eq i64 %x, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
+  %cast = trunc i64 %0 to i16
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i16 [ %cast, %cond.true ], [ 64, %entry ]
+  ret i16 %cond
+}
+
+define i16 @test6e(i32 %x) {
+; ALL-LABEL: @test6e(
+; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %x, 0
+; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i32 [[CTLZ]] to i16
+; LZCNT-NEXT: select i1 [[COND]], i16 32, i16 [[TRUNC]]
+; BMI-NOT: select
+; GENERIC-NOT: select
+; ALL: ret
+entry:
+  %tobool = icmp eq i32 %x, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+  %cast = trunc i32 %0 to i16
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i16 [ %cast, %cond.true ], [ 32, %entry ]
+  ret i16 %cond
+}
+
+define i16 @test7e(i64 %x) {
+; ALL-LABEL: @test7e(
+; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %x, 0
+; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
+; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTTZ]] to i16
+; BMI-NEXT: select i1 [[COND]], i16 64, i16 [[TRUNC]]
+; LZCNT-NOT: select
+; GENERIC-NOT: select
+; ALL: ret
+entry:
+  %tobool = icmp eq i64 %x, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
+  %cast = trunc i64 %0 to i16
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i16 [ %cast, %cond.true ], [ 64, %entry ]
+  ret i16 %cond
+}
+
+define i16 @test8e(i32 %x) {
+; ALL-LABEL: @test8e(
+; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %x, 0
+; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
+; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i32 [[CTTZ]] to i16
+; BMI-NEXT: select i1 [[COND]], i16 32, i16 [[TRUNC]]
+; LZCNT-NOT: select
+; GENERIC-NOT: select
+; ALL: ret
+entry:
+  %tobool = icmp eq i32 %x, 0
+  br i1 %tobool, label %cond.end, label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %0 = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
+  %cast = trunc i32 %0 to i16
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i16 [ %cast, %cond.true ], [ 32, %entry ]
+  ret i16 %cond
+}
+
+
+declare i64 @llvm.ctlz.i64(i64, i1)
+declare i32 @llvm.ctlz.i32(i32, i1)
+declare i16 @llvm.ctlz.i16(i16, i1)
+declare i64 @llvm.cttz.i64(i64, i1)
+declare i32 @llvm.cttz.i32(i32, i1)
+declare i16 @llvm.cttz.i16(i16, i1)
diff --git a/test/Transforms/SimplifyCFG/X86/switch-covered-bug.ll b/test/Transforms/SimplifyCFG/X86/switch-covered-bug.ll
index 22599b397ed4..f3e5506ad933 100644
--- a/test/Transforms/SimplifyCFG/X86/switch-covered-bug.ll
+++ b/test/Transforms/SimplifyCFG/X86/switch-covered-bug.ll
@@ -9,8 +9,8 @@ target triple = "x86_64-apple-darwin12.0.0"
 ; CHECK: entry:
 ; CHECK-NEXT: sub i3 %arg, -4
 ; CHECK-NEXT: zext i3 %switch.tableidx to i4
-; CHECK-NEXT: getelementptr inbounds [8 x i64]* @switch.table, i32 0, i4 %switch.tableidx.zext
-; CHECK-NEXT: load i64* %switch.gep
+; CHECK-NEXT: getelementptr inbounds [8 x i64], [8 x i64]* @switch.table, i32 0, i4 %switch.tableidx.zext
+; CHECK-NEXT: load i64, i64* %switch.gep
 ; CHECK-NEXT: add i64
 ; CHECK-NEXT: ret i64
 define i64 @test(i3 %arg) {
diff --git a/test/Transforms/SimplifyCFG/X86/switch-table-bug.ll b/test/Transforms/SimplifyCFG/X86/switch-table-bug.ll
index d0b8ab29d26b..26008700f5be 100644
--- a/test/Transforms/SimplifyCFG/X86/switch-table-bug.ll
+++ b/test/Transforms/SimplifyCFG/X86/switch-table-bug.ll
@@ -8,8 +8,8 @@ target triple = "x86_64-apple-darwin12.0.0"
 ; CHECK: entry:
 ; CHECK-NEXT: sub i2 %0, -2
 ; CHECK-NEXT: zext i2 %switch.tableidx to i3
-; CHECK-NEXT: getelementptr inbounds [4 x i64]* @switch.table, i32 0, i3 %switch.tableidx.zext
-; CHECK-NEXT: load i64* %switch.gep
+; CHECK-NEXT: getelementptr inbounds [4 x i64], [4 x i64]* @switch.table, i32 0, i3 %switch.tableidx.zext
+; CHECK-NEXT: load i64, i64* %switch.gep
 ; CHECK-NEXT: ret i64 %switch.load
 define i64 @_TFO6reduce1E5toRawfS0_FT_Si(i2) {
 entry:
diff --git a/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll b/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
index 22f18cd4d432..cae1a91bd43d 100644
--- a/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
+++ b/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
@@ -7,22 +7,22 @@ target triple = "x86_64-unknown-linux-gnu"
 ; CHECK: @switch.table = private unnamed_addr constant [7 x i32] [i32 55, i32 123, i32 0, i32 -1, i32 27, i32 62, i32 1]
 
 ; The float table for @h
-; CHECK: @switch.table1 = private unnamed_addr constant [4 x float] [float 0x40091EB860000000, float 0x3FF3BE76C0000000, float 0x4012449BA0000000, float 0x4001AE1480000000]
+; CHECK: @switch.table.1 = private unnamed_addr constant [4 x float] [float 0x40091EB860000000, float 0x3FF3BE76C0000000, float 0x4012449BA0000000, float 0x4001AE1480000000]
 
 ; The table for @foostring
-; CHECK: @switch.table2 = private unnamed_addr constant [4 x i8*] [i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8]* @.str1, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8]* @.str2, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8]* @.str3, i64 0, i64 0)]
+; CHECK: @switch.table.2 = private unnamed_addr constant [4 x i8*] [i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str1, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str2, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str3, i64 0, i64 0)]
 
 ; The table for @earlyreturncrash
-; CHECK: @switch.table3 = private unnamed_addr constant [4 x i32] [i32 42, i32 9, i32 88, i32 5]
+; CHECK: @switch.table.3 = private unnamed_addr constant [4 x i32] [i32 42, i32 9, i32 88, i32 5]
 
 ; The table for @large.
-; CHECK: @switch.table4 = private unnamed_addr constant [199 x i32] [i32 1, i32 4, i32 9,
+; CHECK: @switch.table.4 = private unnamed_addr constant [199 x i32] [i32 1, i32 4, i32 9,
 
 ; The table for @cprop
-; CHECK: @switch.table5 = private unnamed_addr constant [7 x i32] [i32 5, i32 42, i32 126, i32 -452, i32 128, i32 6, i32 7]
+; CHECK: @switch.table.5 = private unnamed_addr constant [7 x i32] [i32 5, i32 42, i32 126, i32 -452, i32 128, i32 6, i32 7]
 
-; The table for @unreachable
-; CHECK: @switch.table6 = private unnamed_addr constant [5 x i32] [i32 0, i32 0, i32 0, i32 1, i32 -1]
+; The table for @unreachable_case
+; CHECK: @switch.table.6 = private unnamed_addr constant [9 x i32] [i32 0, i32 0, i32 0, i32 2, i32 -1, i32 1, i32 1, i32 1, i32 1]
 
 ; A simple int-to-int selection switch.
 ; It is dense enough to be replaced by table lookup.
@@ -58,8 +58,8 @@ return:
 ; CHECK-NEXT: %0 = icmp ult i32 %switch.tableidx, 7
 ; CHECK-NEXT: br i1 %0, label %switch.lookup, label %return
 ; CHECK: switch.lookup:
-; CHECK-NEXT: %switch.gep = getelementptr inbounds [7 x i32]* @switch.table, i32 0, i32 %switch.tableidx
-; CHECK-NEXT: %switch.load = load i32* %switch.gep
+; CHECK-NEXT: %switch.gep = getelementptr inbounds [7 x i32], [7 x i32]* @switch.table, i32 0, i32 %switch.tableidx
+; CHECK-NEXT: %switch.load = load i32, i32* %switch.gep
 ; CHECK-NEXT: ret i32 %switch.load
 ; CHECK: return:
 ; CHECK-NEXT: ret i32 15
@@ -97,8 +97,8 @@ sw.epilog:
 ; CHECK-NEXT: %switch.shiftamt = mul i32 %switch.tableidx, 8
 ; CHECK-NEXT: %switch.downshift = lshr i32 89655594, %switch.shiftamt
 ; CHECK-NEXT: %switch.masked = trunc i32 %switch.downshift to i8
-; CHECK-NEXT: %switch.gep = getelementptr inbounds [4 x float]* @switch.table1, i32 0, i32 %switch.tableidx
-; CHECK-NEXT: %switch.load = load float* %switch.gep
+; CHECK-NEXT: %switch.gep = getelementptr inbounds [4 x float], [4 x float]* @switch.table.1, i32 0, i32 %switch.tableidx
+; CHECK-NEXT: %switch.load = load float, float* %switch.gep
 ; CHECK-NEXT: br label %sw.epilog
 ; CHECK: sw.epilog:
 ; CHECK-NEXT: %a.0 = phi i8 [ %switch.masked, %switch.lookup ], [ 7, %entry ]
@@ -131,11 +131,11 @@ sw.bb3: br label %return
 sw.default: br label %return
 
 return:
-  %retval.0 = phi i8* [ getelementptr inbounds ([6 x i8]* @.str4, i64 0, i64 0), %sw.default ],
-                      [ getelementptr inbounds ([4 x i8]* @.str3, i64 0, i64 0), %sw.bb3 ],
-                      [ getelementptr inbounds ([4 x i8]* @.str2, i64 0, i64 0), %sw.bb2 ],
-                      [ getelementptr inbounds ([4 x i8]* @.str1, i64 0, i64 0), %sw.bb1 ],
-                      [ getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), %entry ]
+  %retval.0 = phi i8* [ getelementptr inbounds ([6 x i8], [6 x i8]* @.str4, i64 0, i64 0), %sw.default ],
+                      [ getelementptr inbounds ([4 x i8], [4 x i8]* @.str3, i64 0, i64 0), %sw.bb3 ],
+                      [ getelementptr inbounds ([4 x i8], [4 x i8]* @.str2, i64 0, i64 0), %sw.bb2 ],
+                      [ getelementptr inbounds ([4 x i8], [4 x i8]* @.str1, i64 0, i64 0), %sw.bb1 ],
+                      [ getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), %entry ]
   ret i8* %retval.0
 
 ; CHECK-LABEL: @foostring(
@@ -144,8 +144,8 @@ return:
 ; CHECK-NEXT: %0 = icmp ult i32 %switch.tableidx, 4
 ; CHECK-NEXT: br i1 %0, label %switch.lookup, label %return
 ; CHECK: switch.lookup:
-; CHECK-NEXT: %switch.gep = getelementptr inbounds [4 x i8*]* @switch.table2, i32 0, i32 %switch.tableidx
-; CHECK-NEXT: %switch.load = load i8** %switch.gep
+; CHECK-NEXT: %switch.gep = getelementptr inbounds [4 x i8*], [4 x i8*]* @switch.table.2, i32 0, i32 %switch.tableidx
+; CHECK-NEXT: %switch.load = load i8*, i8** %switch.gep
 ; CHECK-NEXT: ret i8* %switch.load
 }
 
@@ -173,8 +173,8 @@ sw.epilog:
 
 ; CHECK-LABEL: @earlyreturncrash(
 ; CHECK: switch.lookup:
-; CHECK-NEXT: %switch.gep = getelementptr inbounds [4 x i32]* @switch.table3, i32 0, i32 %switch.tableidx
-; CHECK-NEXT: %switch.load = load i32* %switch.gep
+; CHECK-NEXT: %switch.gep = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.3, i32 0, i32 %switch.tableidx
+; CHECK-NEXT: %switch.load = load i32, i32* %switch.gep
 ; CHECK-NEXT: ret i32 %switch.load
 ; CHECK: sw.epilog:
 ; CHECK-NEXT: ret i32 7
@@ -749,10 +749,10 @@ return:
 
 ; CHECK-LABEL: @cprop(
 ; CHECK: switch.lookup:
-; CHECK: %switch.gep = getelementptr inbounds [7 x i32]* @switch.table5, i32 0, i32 %switch.tableidx
+; CHECK: %switch.gep = getelementptr inbounds [7 x i32], [7 x i32]* @switch.table.5, i32 0, i32 %switch.tableidx
 }
 
-define i32 @unreachable(i32 %x)  {
+define i32 @unreachable_case(i32 %x)  {
 entry:
   switch i32 %x, label %sw.default [
     i32 0, label %sw.bb
@@ -770,15 +770,44 @@ sw.bb: br label %return
 sw.bb1: unreachable
 sw.bb2: br label %return
 sw.bb3: br label %return
-sw.default: unreachable
+sw.default: br label %return
 
 return:
-  %retval.0 = phi i32 [ 1, %sw.bb3 ], [ -1, %sw.bb2 ], [ 0, %sw.bb ]
+  %retval.0 = phi i32 [ 1, %sw.bb3 ], [ -1, %sw.bb2 ], [ 0, %sw.bb ], [ 2, %sw.default ]
   ret i32 %retval.0
 
-; CHECK-LABEL: @unreachable(
+; CHECK-LABEL: @unreachable_case(
 ; CHECK: switch.lookup:
-; CHECK: getelementptr inbounds [5 x i32]* @switch.table6, i32 0, i32 %switch.tableidx
+; CHECK: getelementptr inbounds [9 x i32], [9 x i32]* @switch.table.6, i32 0, i32 %switch.tableidx
+}
+
+define i32 @unreachable_default(i32 %x)  {
+entry:
+  switch i32 %x, label %default [
+    i32 0, label %bb0
+    i32 1, label %bb1
+    i32 2, label %bb2
+    i32 3, label %bb3
+  ]
+
+bb0: br label %return
+bb1: br label %return
+bb2: br label %return
+bb3: br label %return
+default: unreachable
+
+return:
+  %retval = phi i32 [ 42, %bb0 ], [ 52, %bb1 ], [ 1, %bb2 ], [ 2, %bb3 ]
+  ret i32 %retval
+
+; CHECK-LABEL: @unreachable_default(
+; CHECK: entry:
+; CHECK-NEXT: %switch.tableidx = sub i32 %x, 0
+; CHECK-NOT: icmp
+; CHECK-NOT: br 1i
+; CHECK-NEXT: %switch.gep = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.7, i32 0, i32 %switch.tableidx
+; CHECK-NEXT: %switch.load = load i32, i32* %switch.gep
+; CHECK-NEXT: ret i32 %switch.load
 }
 
 ; Don't create a table with illegal type
@@ -967,10 +996,10 @@ sw.bb2:
 sw.default:
   br label %return
 return:
-  %retval.0 = phi i32* [ getelementptr inbounds ([3 x i32]* @dllimport_d, i32 0, i32 0), %sw.default ],
-                       [ getelementptr inbounds ([3 x i32]* @dllimport_c, i32 0, i32 0), %sw.bb2 ],
-                       [ getelementptr inbounds ([3 x i32]* @dllimport_b, i32 0, i32 0), %sw.bb1 ],
-                       [ getelementptr inbounds ([3 x i32]* @dllimport_a, i32 0, i32 0), %entry ]
+  %retval.0 = phi i32* [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_d, i32 0, i32 0), %sw.default ],
+                       [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_c, i32 0, i32 0), %sw.bb2 ],
+                       [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_b, i32 0, i32 0), %sw.bb1 ],
+                       [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_a, i32 0, i32 0), %entry ]
   ret i32* %retval.0
 ; CHECK-LABEL: @dllimport(
 ; CHECK: switch i32
@@ -1244,3 +1273,32 @@ end:
 ; CHECK-LABEL: @pr20210
 ; CHECK: switch i8 %x
 }
+
+; Make sure we do not crash due to trying to generate an unguarded
+; lookup (since i3 can only hold values in the range of explicit
+; values) and simultaneously trying to generate a branch to deal with
+; the fact that we have holes in the range.
+define i32 @covered_switch_with_bit_tests(i3) {
+entry:
+  switch i3 %0, label %l6 [
+    i3 -3, label %l5
+    i3 -4, label %l5
+    i3 3, label %l1
+    i3 2, label %l1
+  ]
+
+l1: br label %l2
+
+l2:
+  %x = phi i32 [ 1, %l1 ], [ 2, %l5 ]
+  br label %l6
+
+l5: br label %l2
+
+l6:
+  %r = phi i32 [ %x, %l2 ], [ 0, %entry ]
+  ret i32 %r
+; CHECK-LABEL: @covered_switch_with_bit_tests
+; CHECK: entry
+; CHECK-NEXT: switch
+}
diff --git a/test/Transforms/SimplifyCFG/attr-noduplicate.ll b/test/Transforms/SimplifyCFG/attr-noduplicate.ll
index 523aa51bb84e..5f8456ba4054 100644
--- a/test/Transforms/SimplifyCFG/attr-noduplicate.ll
+++ b/test/Transforms/SimplifyCFG/attr-noduplicate.ll
@@ -8,8 +8,8 @@
 ; CHECK-NOT: call void @barrier
 define void @noduplicate(i32 %cond, i32* %out) {
 entry:
-  %out1 = getelementptr i32* %out, i32 1
-  %out2 = getelementptr i32* %out, i32 2
+  %out1 = getelementptr i32, i32* %out, i32 1
+  %out2 = getelementptr i32, i32* %out, i32 2
   %cmp = icmp eq i32 %cond, 0
   br i1 %cmp, label %if.then, label %if.end
 
diff --git a/test/Transforms/SimplifyCFG/basictest.ll b/test/Transforms/SimplifyCFG/basictest.ll
index 5de7cc5e31d5..d228499b2ec5 100644
--- a/test/Transforms/SimplifyCFG/basictest.ll
+++ b/test/Transforms/SimplifyCFG/basictest.ll
@@ -1,6 +1,7 @@
 ; Test CFG simplify removal of branch instructions.
 ;
 ; RUN: opt < %s -simplifycfg -S | FileCheck %s
+; RUN: opt < %s -passes=simplify-cfg -S | FileCheck %s
 
 define void @test1() {
         br label %1
@@ -49,7 +50,7 @@ define i8 @test6f() {
 ; CHECK: alloca i8, align 1
 ; CHECK-NEXT: call i8 @test6g
 ; CHECK-NEXT: icmp eq i8 %tmp, 0
-; CHECK-NEXT: load i8* %r, align 1{{$}}
+; CHECK-NEXT: load i8, i8* %r, align 1{{$}}
 
 bb0:
   %r = alloca i8, align 1
@@ -57,7 +58,7 @@ bb0:
   %tmp1 = icmp eq i8 %tmp, 0
   br i1 %tmp1, label %bb2, label %bb1
 bb1:
-  %tmp3 = load i8* %r, align 1, !range !2, !tbaa !1
+  %tmp3 = load i8, i8* %r, align 1, !range !2, !tbaa !1
   %tmp4 = icmp eq i8 %tmp3, 1
   br i1 %tmp4, label %bb2, label %bb3
 bb2:
diff --git a/test/Transforms/SimplifyCFG/branch-fold-dbg.ll b/test/Transforms/SimplifyCFG/branch-fold-dbg.ll
index f715a0cda93c..fac5b186e89d 100644
--- a/test/Transforms/SimplifyCFG/branch-fold-dbg.ll
+++ b/test/Transforms/SimplifyCFG/branch-fold-dbg.ll
@@ -24,7 +24,7 @@ BB2:                                              ; preds = %BB1
 ;CHECK-NEXT: icmp eq
 
 BB3:                                              ; preds = %BB2
-  %6 = getelementptr inbounds [5 x %0]* @0, i32 0, i32 %0, !dbg !6
+  %6 = getelementptr inbounds [5 x %0], [5 x %0]* @0, i32 0, i32 %0, !dbg !6
   call void @llvm.dbg.value(metadata %0* %6, i64 0, metadata !7, metadata !{}), !dbg !12
   %7 = icmp eq %0* %6, null, !dbg !13
   br i1 %7, label %BB5, label %BB4, !dbg !13
@@ -41,19 +41,19 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 
 !llvm.dbg.sp = !{!0}
 
-!0 = !{!"0x2e\00foo\00foo\00\00231\000\001\000\006\00256\000\000", !15, !1, !3, null, void (i32)* @foo, null, null, null} ; [ DW_TAG_subprogram ] [line 231] [def] [scope 0] [foo]
-!1 = !{!"0x29", !15} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang (trunk 129006)\001\00\000\00\000", !15, !4, !4, null, null, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !15, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "foo", line: 231, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !15, scope: !1, type: !3, function: void (i32)* @foo)
+!1 = !DIFile(filename: "a.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang (trunk 129006)", isOptimized: true, emissionKind: 0, file: !15, enums: !4, retainedTypes: !4)
+!3 = !DISubroutineType(types: !4)
 !4 = !{null}
-!5 = !MDLocation(line: 131, column: 2, scope: !0)
-!6 = !MDLocation(line: 134, column: 2, scope: !0)
-!7 = !{!"0x100\00bar\00232\000", !8, !1, !9} ; [ DW_TAG_auto_variable ]
-!8 = !{!"0xb\00231\001\003", !15, !0} ; [ DW_TAG_lexical_block ]
-!9 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !10} ; [ DW_TAG_pointer_type ]
-!10 = !{!"0x26\00\000\000\000\000\000", null, !2, !11} ; [ DW_TAG_const_type ]
-!11 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, !2} ; [ DW_TAG_base_type ]
-!12 = !MDLocation(line: 232, column: 40, scope: !8)
-!13 = !MDLocation(line: 234, column: 2, scope: !8)
-!14 = !MDLocation(line: 274, column: 1, scope: !8)
-!15 = !{!"a.c", !"/private/tmp"}
+!5 = !DILocation(line: 131, column: 2, scope: !0)
+!6 = !DILocation(line: 134, column: 2, scope: !0)
+!7 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "bar", line: 232, scope: !8, file: !1, type: !9)
+!8 = distinct !DILexicalBlock(line: 231, column: 1, file: !15, scope: !0)
+!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !10)
+!10 = !DIDerivedType(tag: DW_TAG_const_type, scope: !2, baseType: !11)
+!11 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
+!12 = !DILocation(line: 232, column: 40, scope: !8)
+!13 = !DILocation(line: 234, column: 2, scope: !8)
+!14 = !DILocation(line: 274, column: 1, scope: !8)
+!15 = !DIFile(filename: "a.c", directory: "/private/tmp")
diff --git a/test/Transforms/SimplifyCFG/branch-fold-threshold.ll b/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
index 878c0a4837ae..fad5fce1d4b0 100644
--- a/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
+++ b/test/Transforms/SimplifyCFG/branch-fold-threshold.ll
@@ -19,7 +19,7 @@ lor.lhs.false:
 ; AGGRESSIVE-NOT: br i1
 
 cond.false:
-  %0 = load i32* %input, align 4
+  %0 = load i32, i32* %input, align 4
   br label %cond.end
 
 cond.end:
diff --git a/test/Transforms/SimplifyCFG/branch-phi-thread.ll b/test/Transforms/SimplifyCFG/branch-phi-thread.ll
index c19ba69866b4..4c1b7e68e25f 100644
--- a/test/Transforms/SimplifyCFG/branch-phi-thread.ll
+++ b/test/Transforms/SimplifyCFG/branch-phi-thread.ll
@@ -51,7 +51,7 @@ E:
 	br i1 %C, label %T, label %F
 T:		; preds = %A, %E
 	call void @f3( )
-	%XX = load i32* %AP		; <i32> [#uses=1]
+	%XX = load i32, i32* %AP		; <i32> [#uses=1]
 	store i32 %XX, i32* %BP
 	br i1 %C, label %B, label %A
 A:		; preds = %T
diff --git a/test/Transforms/SimplifyCFG/clamp.ll b/test/Transforms/SimplifyCFG/clamp.ll
new file mode 100644
index 000000000000..d21894a12699
--- /dev/null
+++ b/test/Transforms/SimplifyCFG/clamp.ll
@@ -0,0 +1,22 @@
+; RUN: opt < %s -simplifycfg -S | FileCheck %s
+
+define float @clamp(float %a, float %b, float %c) {
+; CHECK-LABEL: @clamp
+; CHECK:  %cmp = fcmp ogt float %a, %c
+; CHECK:  %cmp1 = fcmp olt float %a, %b
+; CHECK:  %cond = select i1 %cmp1, float %b, float %a
+; CHECK:  %cond5 = select i1 %cmp, float %c, float %cond
+; CHECK:  ret float %cond5
+entry:
+  %cmp = fcmp ogt float %a, %c
+  br i1 %cmp, label %cond.end4, label %cond.false
+
+cond.false:                                       ; preds = %entry
+  %cmp1 = fcmp olt float %a, %b
+  %cond = select i1 %cmp1, float %b, float %a
+  br label %cond.end4
+
+cond.end4:                                        ; preds = %entry, %cond.false
+  %cond5 = phi float [ %cond, %cond.false ], [ %c, %entry ]
+  ret float %cond5
+}
diff --git a/test/Transforms/SimplifyCFG/common-dest-folding.ll b/test/Transforms/SimplifyCFG/common-dest-folding.ll
index 0aa3b2c560a5..e3e27c706d1d 100644
--- a/test/Transforms/SimplifyCFG/common-dest-folding.ll
+++ b/test/Transforms/SimplifyCFG/common-dest-folding.ll
@@ -18,7 +18,7 @@ define i32 @foo(i32 %k, i32 %c1, i32 %c2) {
   br i1 %5, label %8, label %6
 
 ; <label>:6                                       ; preds = %3
-  %7 = tail call i32 (...)* @bar() nounwind
+  %7 = tail call i32 (...) @bar() nounwind
   br label %8
 
 ; <label>:8                                       ; preds = %3, %0, %6
@@ -47,7 +47,7 @@ bb3:                                              ; preds = %bb
   br i1 %tmp6, label %bb9, label %bb7
 
 bb7:                                              ; preds = %bb3
-  %tmp8 = tail call i32 (...)* @bar() #1
+  %tmp8 = tail call i32 (...) @bar() #1
   br label %bb9
 
 bb9:                                              ; preds = %bb7, %bb3, %bb
diff --git a/test/Transforms/SimplifyCFG/dbginfo.ll b/test/Transforms/SimplifyCFG/dbginfo.ll
index 1a9f20ac871e..12aec91c6c55 100644
--- a/test/Transforms/SimplifyCFG/dbginfo.ll
+++ b/test/Transforms/SimplifyCFG/dbginfo.ll
@@ -58,7 +58,7 @@ entry:
 	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
 	call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram947 to { }*))
 	store %struct.__false_type* %this, %struct.__false_type** %this_addr
-	%0 = load %struct.__false_type** %this_addr, align 4		; <%struct.__false_type*> [#uses=1]
+	%0 = load %struct.__false_type*, %struct.__false_type** %this_addr, align 4		; <%struct.__false_type*> [#uses=1]
 	call void @_ZN9__gnu_cxx13new_allocatorIP5SceneED2Ev(%struct.__false_type* %0) nounwind
 	br label %bb
 
diff --git a/test/Transforms/SimplifyCFG/duplicate-landingpad.ll b/test/Transforms/SimplifyCFG/duplicate-landingpad.ll
new file mode 100644
index 000000000000..54028774d20e
--- /dev/null
+++ b/test/Transforms/SimplifyCFG/duplicate-landingpad.ll
@@ -0,0 +1,110 @@
+; RUN: opt < %s -simplifycfg -S | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+declare i32 @__gxx_personality_v0(...)
+declare void @fn()
+
+
+; CHECK-LABEL: @test1
+define void @test1() {
+entry:
+; CHECK-LABEL: entry:
+; CHECK: to label %invoke2 unwind label %lpad2
+  invoke void @fn()
+    to label %invoke2 unwind label %lpad1
+
+invoke2:
+; CHECK-LABEL: invoke2:
+; CHECK: to label %invoke.cont unwind label %lpad2
+  invoke void @fn()
+    to label %invoke.cont unwind label %lpad2
+
+invoke.cont:
+  ret void
+
+lpad1:
+  %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
+         cleanup
+  br label %shared_resume
+
+lpad2:
+; CHECK-LABEL: lpad2:
+; CHECK: landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
+; CHECK-NEXT: cleanup
+; CHECK-NEXT: call void @fn()
+; CHECK-NEXT: ret void
+  %exn2 = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
+          cleanup
+  br label %shared_resume
+
+shared_resume:
+  call void @fn()
+  ret void
+}
+
+; Don't trigger if blocks aren't the same/empty
+define void @neg1() {
+; CHECK-LABEL: @neg1
+entry:
+; CHECK-LABEL: entry:
+; CHECK: to label %invoke2 unwind label %lpad1
+  invoke void @fn()
+    to label %invoke2 unwind label %lpad1
+
+invoke2:
+; CHECK-LABEL: invoke2:
+; CHECK: to label %invoke.cont unwind label %lpad2
+  invoke void @fn()
+    to label %invoke.cont unwind label %lpad2
+
+invoke.cont:
+  ret void
+
+lpad1:
+  %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
+         filter [0 x i8*] zeroinitializer
+  call void @fn()
+  br label %shared_resume
+
+lpad2:
+  %exn2 = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
+          cleanup
+  br label %shared_resume
+
+shared_resume:
+  call void @fn()
+  ret void
+}
+
+; Should not trigger when the landing pads are not the exact same
+define void @neg2() {
+; CHECK-LABEL: @neg2
+entry:
+; CHECK-LABEL: entry:
+; CHECK: to label %invoke2 unwind label %lpad1
+  invoke void @fn()
+    to label %invoke2 unwind label %lpad1
+
+invoke2:
+; CHECK-LABEL: invoke2:
+; CHECK: to label %invoke.cont unwind label %lpad2
+  invoke void @fn()
+    to label %invoke.cont unwind label %lpad2
+
+invoke.cont:
+  ret void
+
+lpad1:
+  %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
+         filter [0 x i8*] zeroinitializer
+  br label %shared_resume
+
+lpad2:
+  %exn2 = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
+          cleanup
+  br label %shared_resume
+
+shared_resume:
+  call void @fn()
+  ret void
+}
diff --git a/test/Transforms/SimplifyCFG/hoist-common-code.ll b/test/Transforms/SimplifyCFG/hoist-common-code.ll
index 5c83e2a3aa49..c1ca605cc206 100644
--- a/test/Transforms/SimplifyCFG/hoist-common-code.ll
+++ b/test/Transforms/SimplifyCFG/hoist-common-code.ll
@@ -6,12 +6,12 @@ define void @test(i1 %P, i32* %Q) {
         br i1 %P, label %T, label %F
 T:              ; preds = %0
         store i32 1, i32* %Q
-        %A = load i32* %Q               ; <i32> [#uses=1]
+        %A = load i32, i32* %Q               ; <i32> [#uses=1]
         call void @bar( i32 %A )
         ret void
 F:              ; preds = %0
         store i32 1, i32* %Q
-        %B = load i32* %Q               ; <i32> [#uses=1]
+        %B = load i32, i32* %Q               ; <i32> [#uses=1]
         call void @bar( i32 %B )
         ret void
 }
diff --git a/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll b/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll
index 869ce099d075..345cf6282e3c 100644
--- a/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll
+++ b/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll
@@ -1,21 +1,21 @@
 ; RUN: opt -simplifycfg -S < %s | FileCheck %s
 
 define i32 @foo(i32 %i) nounwind ssp {
-  call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !6, metadata !{}), !dbg !7
-  call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !9, metadata !{}), !dbg !11
+  call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !6, metadata !DIExpression()), !dbg !7
+  call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !9, metadata !DIExpression()), !dbg !11
   %1 = icmp ne i32 %i, 0, !dbg !12
-;CHECK: call i32 (...)* @bar()
+;CHECK: call i32 (...) @bar()
 ;CHECK-NEXT: llvm.dbg.value
   br i1 %1, label %2, label %4, !dbg !12
 
 ; <label>:2                                       ; preds = %0
-  %3 = call i32 (...)* @bar(), !dbg !13
-  call void @llvm.dbg.value(metadata i32 %3, i64 0, metadata !9, metadata !{}), !dbg !13
+  %3 = call i32 (...) @bar(), !dbg !13
+  call void @llvm.dbg.value(metadata i32 %3, i64 0, metadata !9, metadata !DIExpression()), !dbg !13
   br label %6, !dbg !15
 
 ; <label>:4                                       ; preds = %0
-  %5 = call i32 (...)* @bar(), !dbg !16
-  call void @llvm.dbg.value(metadata i32 %5, i64 0, metadata !9, metadata !{}), !dbg !16
+  %5 = call i32 (...) @bar(), !dbg !16
+  call void @llvm.dbg.value(metadata i32 %5, i64 0, metadata !9, metadata !DIExpression()), !dbg !16
   br label %6, !dbg !18
 
 ; <label>:6                                       ; preds = %4, %2
@@ -32,25 +32,25 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.module.flags = !{!21}
 !llvm.dbg.sp = !{!0}
 
-!0 = !{!"0x2e\00foo\00foo\00\002\000\001\000\006\00256\000\000", !20, !1, !3, null, i32 (i32)* @foo, null, null, null} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 0] [foo]
-!1 = !{!"0x29", !20} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang\001\00\000\00\000", !20, !8, !8, null, null, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !20, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "foo", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !1, type: !3, function: i32 (i32)* @foo)
+!1 = !DIFile(filename: "b.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang", isOptimized: true, emissionKind: 0, file: !20, enums: !8, retainedTypes: !8)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ]
-!6 = !{!"0x101\00i\0016777218\000", !0, !1, !5} ; [ DW_TAG_arg_variable ]
-!7 = !MDLocation(line: 2, column: 13, scope: !0)
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 2, arg: 1, scope: !0, file: !1, type: !5)
+!7 = !DILocation(line: 2, column: 13, scope: !0)
 !8 = !{i32 0}
-!9 = !{!"0x100\00k\003\000", !10, !1, !5} ; [ DW_TAG_auto_variable ]
-!10 = !{!"0xb\002\0016\000", !20, !0} ; [ DW_TAG_lexical_block ]
-!11 = !MDLocation(line: 3, column: 12, scope: !10)
-!12 = !MDLocation(line: 4, column: 3, scope: !10)
-!13 = !MDLocation(line: 5, column: 5, scope: !14)
-!14 = !{!"0xb\004\0010\001", !20, !10} ; [ DW_TAG_lexical_block ]
-!15 = !MDLocation(line: 6, column: 3, scope: !14)
-!16 = !MDLocation(line: 7, column: 5, scope: !17)
-!17 = !{!"0xb\006\0010\002", !20, !10} ; [ DW_TAG_lexical_block ]
-!18 = !MDLocation(line: 8, column: 3, scope: !17)
-!19 = !MDLocation(line: 9, column: 3, scope: !10)
-!20 = !{!"b.c", !"/private/tmp"}
-!21 = !{i32 1, !"Debug Info Version", i32 2}
+!9 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 3, scope: !10, file: !1, type: !5)
+!10 = distinct !DILexicalBlock(line: 2, column: 16, file: !20, scope: !0)
+!11 = !DILocation(line: 3, column: 12, scope: !10)
+!12 = !DILocation(line: 4, column: 3, scope: !10)
+!13 = !DILocation(line: 5, column: 5, scope: !14)
+!14 = distinct !DILexicalBlock(line: 4, column: 10, file: !20, scope: !10)
+!15 = !DILocation(line: 6, column: 3, scope: !14)
+!16 = !DILocation(line: 7, column: 5, scope: !17)
+!17 = distinct !DILexicalBlock(line: 6, column: 10, file: !20, scope: !10)
+!18 = !DILocation(line: 8, column: 3, scope: !17)
+!19 = !DILocation(line: 9, column: 3, scope: !10)
+!20 = !DIFile(filename: "b.c", directory: "/private/tmp")
+!21 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/SimplifyCFG/hoist-with-range.ll b/test/Transforms/SimplifyCFG/hoist-with-range.ll
index 7ca3ff247dc8..0a2b28267ef1 100644
--- a/test/Transforms/SimplifyCFG/hoist-with-range.ll
+++ b/test/Transforms/SimplifyCFG/hoist-with-range.ll
@@ -2,15 +2,15 @@
 
 define void @foo(i1 %c, i8* %p) {
 ; CHECK: if:
-; CHECK-NEXT: load i8* %p, !range !0
+; CHECK-NEXT: load i8, i8* %p, !range !0
 ; CHECK: !0 = !{i8 0, i8 1, i8 3, i8 5}
 if:
   br i1 %c, label %then, label %else
 then:
-  %t = load i8* %p, !range !0
+  %t = load i8, i8* %p, !range !0
   br label %out
 else:
-  %e = load i8* %p, !range !1
+  %e = load i8, i8* %p, !range !1
   br label %out
 out:
   ret void
diff --git a/test/Transforms/SimplifyCFG/indirectbr.ll b/test/Transforms/SimplifyCFG/indirectbr.ll
index d0020d001b03..67e23d2fe935 100644
--- a/test/Transforms/SimplifyCFG/indirectbr.ll
+++ b/test/Transforms/SimplifyCFG/indirectbr.ll
@@ -17,7 +17,7 @@ entry:
   store i8* blockaddress(@indbrtest0, %BB1), i8** %P
   store i8* blockaddress(@indbrtest0, %BB2), i8** %P
   call void @foo()
-  %t = load i8** %Q
+  %t = load i8*, i8** %Q
   indirectbr i8* %t, [label %BB0, label %BB1, label %BB2, label %BB0, label %BB1, label %BB2]
 BB0:
   call void @A()
@@ -42,7 +42,7 @@ define void @indbrtest1(i8** %P, i8** %Q) {
 entry:
   store i8* blockaddress(@indbrtest1, %BB0), i8** %P
   call void @foo()
-  %t = load i8** %Q
+  %t = load i8*, i8** %Q
   indirectbr i8* %t, [label %BB0, label %BB0]
 BB0:
   call void @A()
@@ -192,8 +192,8 @@ escape-string.top:
 
 xlab8x:                                           ; preds = %xlab5x
   %xvaluex = call i32 @xselectorx()
-  %xblkx.x = getelementptr [9 x i8*]* @xblkx.bbs, i32 0, i32 %xvaluex
-  %xblkx.load = load i8** %xblkx.x
+  %xblkx.x = getelementptr [9 x i8*], [9 x i8*]* @xblkx.bbs, i32 0, i32 %xvaluex
+  %xblkx.load = load i8*, i8** %xblkx.x
   indirectbr i8* %xblkx.load, [label %xblkx.begin, label %xblkx.begin3, label %xblkx.begin4, label %xblkx.begin5, label %xblkx.begin6, label %xblkx.begin7, label %xblkx.begin8, label %xblkx.begin9, label %xblkx.end]
 
 xblkx.begin:
diff --git a/test/Transforms/SimplifyCFG/iterative-simplify.ll b/test/Transforms/SimplifyCFG/iterative-simplify.ll
index a39741105764..60728b9a9578 100644
--- a/test/Transforms/SimplifyCFG/iterative-simplify.ll
+++ b/test/Transforms/SimplifyCFG/iterative-simplify.ll
@@ -17,13 +17,13 @@ cond_true:		; preds = %entry
 	br label %bb
 
 bb:		; preds = %cond_next, %cond_true
-	%tmp = load i32* %z		; <i32> [#uses=1]
+	%tmp = load i32, i32* %z		; <i32> [#uses=1]
 	%tmp1 = sub i32 %tmp, 16384		; <i32> [#uses=1]
 	store i32 %tmp1, i32* %z
-	%tmp2 = load i32* %i		; <i32> [#uses=1]
+	%tmp2 = load i32, i32* %i		; <i32> [#uses=1]
 	%tmp3 = add i32 %tmp2, 1		; <i32> [#uses=1]
 	store i32 %tmp3, i32* %i
-	%tmp4 = load i32* %i		; <i32> [#uses=1]
+	%tmp4 = load i32, i32* %i		; <i32> [#uses=1]
 	%tmp5 = icmp sgt i32 %tmp4, 262144		; <i1> [#uses=1]
 	%tmp56 = zext i1 %tmp5 to i8		; <i8> [#uses=1]
 	%toBool7 = icmp ne i8 %tmp56, 0		; <i1> [#uses=1]
@@ -34,7 +34,7 @@ cond_true8:		; preds = %bb
 	unreachable
 
 cond_next:		; preds = %bb
-	%tmp9 = load i32* %z		; <i32> [#uses=1]
+	%tmp9 = load i32, i32* %z		; <i32> [#uses=1]
 	%tmp10 = icmp ne i32 %tmp9, 0		; <i1> [#uses=1]
 	%tmp1011 = zext i1 %tmp10 to i8		; <i8> [#uses=1]
 	%toBool12 = icmp ne i8 %tmp1011, 0		; <i1> [#uses=1]
@@ -53,13 +53,13 @@ cond_true15:		; preds = %cond_false
 	br label %bb17
 
 bb17:		; preds = %cond_next27, %cond_true15
-	%tmp18 = load i32* %z16		; <i32> [#uses=1]
+	%tmp18 = load i32, i32* %z16		; <i32> [#uses=1]
 	%tmp19 = sub i32 %tmp18, 16384		; <i32> [#uses=1]
 	store i32 %tmp19, i32* %z16
-	%tmp20 = load i32* %i		; <i32> [#uses=1]
+	%tmp20 = load i32, i32* %i		; <i32> [#uses=1]
 	%tmp21 = add i32 %tmp20, 1		; <i32> [#uses=1]
 	store i32 %tmp21, i32* %i
-	%tmp22 = load i32* %i		; <i32> [#uses=1]
+	%tmp22 = load i32, i32* %i		; <i32> [#uses=1]
 	%tmp23 = icmp sgt i32 %tmp22, 262144		; <i1> [#uses=1]
 	%tmp2324 = zext i1 %tmp23 to i8		; <i8> [#uses=1]
 	%toBool25 = icmp ne i8 %tmp2324, 0		; <i1> [#uses=1]
@@ -70,7 +70,7 @@ cond_true26:		; preds = %bb17
 	unreachable
 
 cond_next27:		; preds = %bb17
-	%tmp28 = load i32* %z16		; <i32> [#uses=1]
+	%tmp28 = load i32, i32* %z16		; <i32> [#uses=1]
 	%tmp29 = icmp ne i32 %tmp28, 0		; <i1> [#uses=1]
 	%tmp2930 = zext i1 %tmp29 to i8		; <i8> [#uses=1]
 	%toBool31 = icmp ne i8 %tmp2930, 0		; <i1> [#uses=1]
@@ -91,7 +91,7 @@ cond_next35:		; preds = %cond_next34
 	br label %return
 
 return:		; preds = %cond_next35
-	%retval36 = load i32* %retval		; <i32> [#uses=1]
+	%retval36 = load i32, i32* %retval		; <i32> [#uses=1]
 	ret i32 %retval36
 }
 
diff --git a/test/Transforms/SimplifyCFG/multiple-phis.ll b/test/Transforms/SimplifyCFG/multiple-phis.ll
index 78454232461a..a6eef09ae646 100644
--- a/test/Transforms/SimplifyCFG/multiple-phis.ll
+++ b/test/Transforms/SimplifyCFG/multiple-phis.ll
@@ -22,8 +22,8 @@ while.body:                                       ; preds = %while.cond
   %add = add i32 %low.0, %high.addr.0
   %div = udiv i32 %add, 2
   %idxprom = zext i32 %div to i64
-  %arrayidx = getelementptr inbounds i32* %r, i64 %idxprom
-  %0 = load i32* %arrayidx
+  %arrayidx = getelementptr inbounds i32, i32* %r, i64 %idxprom
+  %0 = load i32, i32* %arrayidx
   %cmp1 = icmp ult i32 %k, %0
   br i1 %cmp1, label %if.then, label %if.else
 
diff --git a/test/Transforms/SimplifyCFG/no_speculative_loads_with_tsan.ll b/test/Transforms/SimplifyCFG/no_speculative_loads_with_tsan.ll
index b388cc5830f4..4792e9565b2d 100644
--- a/test/Transforms/SimplifyCFG/no_speculative_loads_with_tsan.ll
+++ b/test/Transforms/SimplifyCFG/no_speculative_loads_with_tsan.ll
@@ -8,7 +8,7 @@ entry:
   br i1 %tobool, label %return, label %if.then
 
 if.then:                                          ; preds = %entry
-  %0 = load i32* @g, align 4
+  %0 = load i32, i32* @g, align 4
   br label %return
 
 return:                                           ; preds = %entry, %if.then
@@ -26,7 +26,7 @@ entry:
   br i1 %tobool, label %return, label %if.then
 
 if.then:                                          ; preds = %entry
-  %0 = load i32* @g, align 4
+  %0 = load i32, i32* @g, align 4
   br label %return
 
 return:                                           ; preds = %entry, %if.then
@@ -34,7 +34,7 @@ return:                                           ; preds = %entry, %if.then
   ret i32 %retval
 ; CHECK-LABEL: @TestTsan
 ; CHECK: br i1
-; CHECK: load i32* @g
+; CHECK: load i32, i32* @g
 ; CHECK: br label
 ; CHECK: ret i32
 }
diff --git a/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll b/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll
index f34aec525df8..c0f0046a1d2c 100644
--- a/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll
+++ b/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll
@@ -21,7 +21,7 @@ if.then4:                                         ; preds = %if.else
 
 if.end7:                                          ; preds = %if.else, %if.then4, %if.then
   %x.0 = phi i32* [ %a, %if.then ], [ %c, %if.then4 ], [ null, %if.else ]
-  %tmp9 = load i32* %x.0
+  %tmp9 = load i32, i32* %x.0
   ret i32 %tmp9
 
 ; CHECK-LABEL: @test1(
@@ -50,7 +50,7 @@ if.then4:                                         ; preds = %if.else
 
 if.end7:                                          ; preds = %if.else, %if.then4, %if.then
   %x.0 = phi i32* [ %a, %if.then ], [ null, %if.then4 ], [ null, %if.else ]
-  %tmp9 = load i32* %x.0
+  %tmp9 = load i32, i32* %x.0
   ret i32 %tmp9
 ; CHECK-LABEL: @test2(
 ; CHECK: if.else:
@@ -79,7 +79,7 @@ if.then4:                                         ; preds = %if.else
 if.end7:                                          ; preds = %if.else, %if.then4, %if.then
   %x.0 = phi i32* [ %a, %if.then ], [ null, %if.then4 ], [ null, %if.else ]
   tail call void @bar() nounwind
-  %tmp9 = load i32* %x.0
+  %tmp9 = load i32, i32* %x.0
   ret i32 %tmp9
 ; CHECK-LABEL: @test3(
 ; CHECK: if.end7:
@@ -105,8 +105,8 @@ if.then4:                                         ; preds = %if.else
 
 if.end7:                                          ; preds = %if.else, %if.then4, %if.then
   %x.0 = phi i32* [ %a, %if.then ], [ null, %if.then4 ], [ null, %if.else ]
-  %gep = getelementptr i32* %x.0, i32 10
-  %tmp9 = load i32* %gep
+  %gep = getelementptr i32, i32* %x.0, i32 10
+  %tmp9 = load i32, i32* %gep
   %tmp10 = or i32 %tmp9, 1
   store i32 %tmp10, i32* %gep
   ret i32 %tmp9
diff --git a/test/Transforms/SimplifyCFG/preserve-branchweights.ll b/test/Transforms/SimplifyCFG/preserve-branchweights.ll
index 7802a0593574..ae1794b1c61a 100644
--- a/test/Transforms/SimplifyCFG/preserve-branchweights.ll
+++ b/test/Transforms/SimplifyCFG/preserve-branchweights.ll
@@ -353,7 +353,7 @@ for.cond2:
   %tobool = icmp eq i32 %bit.0, 0
   br i1 %tobool, label %for.exit, label %for.body3, !prof !10
 for.body3:
-  %v3 = load i32* @max_regno, align 4
+  %v3 = load i32, i32* @max_regno, align 4
   %cmp4 = icmp eq i32 %i.1, %v3
   br i1 %cmp4, label %for.exit, label %for.inc, !prof !11
 for.inc:
diff --git a/test/Transforms/SimplifyCFG/seh-nounwind.ll b/test/Transforms/SimplifyCFG/seh-nounwind.ll
new file mode 100644
index 000000000000..3845e3198909
--- /dev/null
+++ b/test/Transforms/SimplifyCFG/seh-nounwind.ll
@@ -0,0 +1,31 @@
+; RUN: opt -S -simplifycfg < %s | FileCheck %s
+
+; Don't remove invokes of nounwind functions if the personality handles async
+; exceptions. The @div function in this test can fault, even though it can't
+; throw a synchronous exception.
+
+define i32 @div(i32 %n, i32 %d) nounwind {
+entry:
+  %div = sdiv i32 %n, %d
+  ret i32 %div
+}
+
+define i32 @main() nounwind {
+entry:
+  %call = invoke i32 @div(i32 10, i32 0)
+          to label %__try.cont unwind label %lpad
+
+lpad:
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+          catch i8* null
+  br label %__try.cont
+
+__try.cont:
+  %retval.0 = phi i32 [ %call, %entry ], [ 0, %lpad ]
+  ret i32 %retval.0
+}
+
+; CHECK-LABEL: define i32 @main()
+; CHECK: invoke i32 @div(i32 10, i32 0)
+
+declare i32 @__C_specific_handler(...)
diff --git a/test/Transforms/SimplifyCFG/select-gep.ll b/test/Transforms/SimplifyCFG/select-gep.ll
index 96c214cbc81e..f2bc5abbf738 100644
--- a/test/Transforms/SimplifyCFG/select-gep.ll
+++ b/test/Transforms/SimplifyCFG/select-gep.ll
@@ -1,40 +1,21 @@
 ; RUN: opt -S -simplifycfg < %s | FileCheck %s
 
-define i8* @test1(i8* %x, i64 %y) nounwind {
-entry:
-  %tmp1 = load i8* %x, align 1
-  %cmp = icmp eq i8 %tmp1, 47
-  br i1 %cmp, label %if.then, label %if.end
-
-if.then:
-  %incdec.ptr = getelementptr inbounds i8* %x, i64 %y
-  br label %if.end
-
-if.end:
-  %x.addr = phi i8* [ %incdec.ptr, %if.then ], [ %x, %entry ]
-  ret i8* %x.addr
-
-; CHECK-LABEL: @test1(
-; CHECK-NOT: select
-; CHECK: ret i8* %x.addr
-}
-
 %ST = type { i8, i8 }
 
-define i8* @test2(%ST* %x, i8* %y) nounwind {
+define i8* @test1(%ST* %x, i8* %y) nounwind {
 entry:
   %cmp = icmp eq %ST* %x, null
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
-  %incdec.ptr = getelementptr %ST* %x, i32 0, i32 1
+  %incdec.ptr = getelementptr %ST, %ST* %x, i32 0, i32 1
   br label %if.end
 
 if.end:
   %x.addr = phi i8* [ %incdec.ptr, %if.then ], [ %y, %entry ]
   ret i8* %x.addr
 
-; CHECK-LABEL: @test2(
+; CHECK-LABEL: @test1(
 ; CHECK: %incdec.ptr.y = select i1 %cmp, i8* %incdec.ptr, i8* %y
 ; CHECK: ret i8* %incdec.ptr.y
 }
diff --git a/test/Transforms/SimplifyCFG/speculate-store.ll b/test/Transforms/SimplifyCFG/speculate-store.ll
index e241901a8789..c1ac7bcea249 100644
--- a/test/Transforms/SimplifyCFG/speculate-store.ll
+++ b/test/Transforms/SimplifyCFG/speculate-store.ll
@@ -2,15 +2,15 @@
 
 define void @ifconvertstore(i32 %m, i32* %A, i32* %B, i32 %C, i32 %D) {
 entry:
-  %arrayidx = getelementptr inbounds i32* %B, i64 0
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %B, i64 0
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %C
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 0
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 0
 
 ; First store to the location.
   store i32 %add, i32* %arrayidx2, align 4
-  %arrayidx4 = getelementptr inbounds i32* %B, i64 1
-  %1 = load i32* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %B, i64 1
+  %1 = load i32, i32* %arrayidx4, align 4
   %add5 = add nsw i32 %1, %D
   %cmp6 = icmp sgt i32 %add5, %C
   br i1 %cmp6, label %if.then, label %ret.end
@@ -30,15 +30,15 @@ ret.end:
 
 define void @noifconvertstore1(i32 %m, i32* %A, i32* %B, i32 %C, i32 %D) {
 entry:
-  %arrayidx = getelementptr inbounds i32* %B, i64 0
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %B, i64 0
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %C
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 0
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 0
 
 ; Store to a different location.
   store i32 %add, i32* %arrayidx, align 4
-  %arrayidx4 = getelementptr inbounds i32* %B, i64 1
-  %1 = load i32* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %B, i64 1
+  %1 = load i32, i32* %arrayidx4, align 4
   %add5 = add nsw i32 %1, %D
   %cmp6 = icmp sgt i32 %add5, %C
   br i1 %cmp6, label %if.then, label %ret.end
@@ -57,16 +57,16 @@ declare void @unknown_fun()
 
 define void @noifconvertstore2(i32 %m, i32* %A, i32* %B, i32 %C, i32 %D) {
 entry:
-  %arrayidx = getelementptr inbounds i32* %B, i64 0
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %B, i64 0
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %C
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 0
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 0
 
 ; First store to the location.
   store i32 %add, i32* %arrayidx2, align 4
   call void @unknown_fun()
-  %arrayidx4 = getelementptr inbounds i32* %B, i64 1
-  %1 = load i32* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %B, i64 1
+  %1 = load i32, i32* %arrayidx4, align 4
   %add5 = add nsw i32 %1, %D
   %cmp6 = icmp sgt i32 %add5, %C
   br i1 %cmp6, label %if.then, label %ret.end
@@ -83,15 +83,15 @@ ret.end:
 
 define void @noifconvertstore_volatile(i32 %m, i32* %A, i32* %B, i32 %C, i32 %D) {
 entry:
-  %arrayidx = getelementptr inbounds i32* %B, i64 0
-  %0 = load i32* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, i32* %B, i64 0
+  %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %C
-  %arrayidx2 = getelementptr inbounds i32* %A, i64 0
+  %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 0
 
 ; First store to the location.
   store i32 %add, i32* %arrayidx2, align 4
-  %arrayidx4 = getelementptr inbounds i32* %B, i64 1
-  %1 = load i32* %arrayidx4, align 4
+  %arrayidx4 = getelementptr inbounds i32, i32* %B, i64 1
+  %1 = load i32, i32* %arrayidx4, align 4
   %add5 = add nsw i32 %1, %D
   %cmp6 = icmp sgt i32 %add5, %C
   br i1 %cmp6, label %if.then, label %ret.end
diff --git a/test/Transforms/SimplifyCFG/speculate-with-offset.ll b/test/Transforms/SimplifyCFG/speculate-with-offset.ll
index 64fed85c795c..65ebb5c2c3f6 100644
--- a/test/Transforms/SimplifyCFG/speculate-with-offset.ll
+++ b/test/Transforms/SimplifyCFG/speculate-with-offset.ll
@@ -9,7 +9,7 @@
 define void @yes(i1 %c) nounwind {
 entry:
   %a = alloca [4 x i64*], align 8
-  %__a.addr = getelementptr [4 x i64*]* %a, i64 0, i64 3
+  %__a.addr = getelementptr [4 x i64*], [4 x i64*]* %a, i64 0, i64 3
   call void @frob(i64** %__a.addr)
   br i1 %c, label %if.then, label %if.end
 
@@ -17,7 +17,7 @@ if.then:                                          ; preds = %entry
   br label %return
 
 if.end:                                           ; preds = %entry
-  %tmp5 = load i64** %__a.addr, align 8
+  %tmp5 = load i64*, i64** %__a.addr, align 8
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
@@ -31,7 +31,7 @@ return:                                           ; preds = %if.end, %if.then
 define void @no0(i1 %c) nounwind {
 entry:
   %a = alloca [4 x i64*], align 8
-  %__a.addr = getelementptr [4 x i64*]* %a, i64 0, i64 4
+  %__a.addr = getelementptr [4 x i64*], [4 x i64*]* %a, i64 0, i64 4
   call void @frob(i64** %__a.addr)
   br i1 %c, label %if.then, label %if.end
 
@@ -39,7 +39,7 @@ if.then:                                          ; preds = %entry
   br label %return
 
 if.end:                                           ; preds = %entry
-  %tmp5 = load i64** %__a.addr, align 8
+  %tmp5 = load i64*, i64** %__a.addr, align 8
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
@@ -53,7 +53,7 @@ return:                                           ; preds = %if.end, %if.then
 define void @no1(i1 %c, i64 %n) nounwind {
 entry:
   %a = alloca [4 x i64*], align 8
-  %__a.addr = getelementptr [4 x i64*]* %a, i64 0, i64 %n
+  %__a.addr = getelementptr [4 x i64*], [4 x i64*]* %a, i64 0, i64 %n
   call void @frob(i64** %__a.addr)
   br i1 %c, label %if.then, label %if.end
 
@@ -61,7 +61,7 @@ if.then:                                          ; preds = %entry
   br label %return
 
 if.end:                                           ; preds = %entry
-  %tmp5 = load i64** %__a.addr, align 8
+  %tmp5 = load i64*, i64** %__a.addr, align 8
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
@@ -75,7 +75,7 @@ return:                                           ; preds = %if.end, %if.then
 define void @no2(i1 %c, i64 %n) nounwind {
 entry:
   %a = alloca [4 x i64*], align 8
-  %__a.addr = getelementptr [4 x i64*]* %a, i64 1, i64 0
+  %__a.addr = getelementptr [4 x i64*], [4 x i64*]* %a, i64 1, i64 0
   call void @frob(i64** %__a.addr)
   br i1 %c, label %if.then, label %if.end
 
@@ -83,7 +83,7 @@ if.then:                                          ; preds = %entry
   br label %return
 
 if.end:                                           ; preds = %entry
-  %tmp5 = load i64** %__a.addr, align 8
+  %tmp5 = load i64*, i64** %__a.addr, align 8
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
diff --git a/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll b/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll
index 8bf2b04520b9..a109b317c732 100644
--- a/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll
+++ b/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll
@@ -48,3 +48,30 @@ b:
   %1 = call i32 @f(i32 1)
   ret i32 %1
 }
+
+
+define i32 @unreachable2(i32 %x) {
+; CHECK-LABEL: @unreachable2
+; CHECK: x.off = add i32 %x, -5
+; CHECK: %switch = icmp ult i32 %x.off, 3
+; CHECK: br i1 %switch, label %a, label %b
+
+entry:
+  ; Note: folding the most popular case destination into the default
+  ; would prevent switch-to-icmp here.
+  switch i32 %x, label %unreachable [
+    i32 5, label %a
+    i32 6, label %a
+    i32 7, label %a
+    i32 10, label %b
+    i32 20, label %b
+  ]
+unreachable:
+  unreachable
+a:
+  %0 = call i32 @f(i32 0)
+  ret i32 %0
+b:
+  %1 = call i32 @f(i32 1)
+  ret i32 %1
+}
diff --git a/test/Transforms/SimplifyCFG/switch-to-select-multiple-edge-per-block-phi.ll b/test/Transforms/SimplifyCFG/switch-to-select-multiple-edge-per-block-phi.ll
index ddf5d1f06ce7..f5359b5b2b32 100644
--- a/test/Transforms/SimplifyCFG/switch-to-select-multiple-edge-per-block-phi.ll
+++ b/test/Transforms/SimplifyCFG/switch-to-select-multiple-edge-per-block-phi.ll
@@ -20,12 +20,12 @@ define i32 @fn1() {
 ; CHECK: %switch.selectcmp1 = icmp eq i32 %1, 5
 ; CHECK: %switch.select2 = select i1 %switch.selectcmp1, i32 5, i32 %switch.select
 entry:
-  %0 = load i32* @b, align 4
+  %0 = load i32, i32* @b, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %if.end3, label %if.then
 
 if.then:
-  %1 = load i32* @a, align 4
+  %1 = load i32, i32* @a, align 4
   switch i32 %1, label %if.end3 [
     i32 5, label %return
     i32 0, label %return
diff --git a/test/Transforms/SimplifyCFG/switch-to-select-two-case.ll b/test/Transforms/SimplifyCFG/switch-to-select-two-case.ll
index 69f97e5f9f9f..f4d171ad2b18 100644
--- a/test/Transforms/SimplifyCFG/switch-to-select-two-case.ll
+++ b/test/Transforms/SimplifyCFG/switch-to-select-two-case.ll
@@ -35,38 +35,3 @@ return:
   %retval.0 = phi i32 [ 4, %sw.epilog ], [ 2, %sw.bb1 ], [ 10, %sw.bb ]
   ret i32 %retval.0
 }
-
-; int foo1_without_default(int a) {
-;   switch(a) {
-;     case 10:
-;       return 10;
-;     case 20:
-;       return 2;
-;   }
-;   __builtin_unreachable();
-; }
-
-define i32 @foo1_without_default(i32 %a) {
-; CHECK-LABEL: @foo1_without_default
-; CHECK: %switch.selectcmp = icmp eq i32 %a, 10
-; CHECK-NEXT: %switch.select = select i1 %switch.selectcmp, i32 10, i32 2
-; CHECK-NOT: %switch.selectcmp1
-entry:
-  switch i32 %a, label %sw.epilog [
-    i32 10, label %sw.bb
-    i32 20, label %sw.bb1
-  ]
-
-sw.bb:
-  br label %return
-
-sw.bb1:
-  br label %return
-
-sw.epilog:
-  unreachable
-
-return:
-  %retval.0 = phi i32 [ 2, %sw.bb1 ], [ 10, %sw.bb ]
-  ret i32 %retval.0
-}
diff --git a/test/Transforms/SimplifyCFG/switch_create.ll b/test/Transforms/SimplifyCFG/switch_create.ll
index e1e91570300c..490b7513a944 100644
--- a/test/Transforms/SimplifyCFG/switch_create.ll
+++ b/test/Transforms/SimplifyCFG/switch_create.ll
@@ -154,8 +154,8 @@ lor.end:                                          ; preds = %entry, %entry, %ent
 
 define i1 @test6({ i32, i32 }* %I) {
 entry:
-        %tmp.1.i = getelementptr { i32, i32 }* %I, i64 0, i32 1         ; <i32*> [#uses=1]
-        %tmp.2.i = load i32* %tmp.1.i           ; <i32> [#uses=6]
+        %tmp.1.i = getelementptr { i32, i32 }, { i32, i32 }* %I, i64 0, i32 1         ; <i32*> [#uses=1]
+        %tmp.2.i = load i32, i32* %tmp.1.i           ; <i32> [#uses=6]
         %tmp.2 = icmp eq i32 %tmp.2.i, 14               ; <i1> [#uses=1]
         br i1 %tmp.2, label %shortcirc_done.4, label %shortcirc_next.0
 shortcirc_next.0:               ; preds = %entry
diff --git a/test/Transforms/SimplifyCFG/trap-debugloc.ll b/test/Transforms/SimplifyCFG/trap-debugloc.ll
index 24a286fd9735..fedf6b172d75 100644
--- a/test/Transforms/SimplifyCFG/trap-debugloc.ll
+++ b/test/Transforms/SimplifyCFG/trap-debugloc.ll
@@ -11,14 +11,14 @@ define void @foo() nounwind ssp {
 !llvm.module.flags = !{!10}
 !llvm.dbg.sp = !{!0}
 
-!0 = !{!"0x2e\00foo\00foo\00\003\000\001\000\006\000\000\000", !8, !1, !3, null, void ()* @foo, null, null, null} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 0] [foo]
-!1 = !{!"0x29", !8} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00Apple clang version 3.0 (tags/Apple/clang-206.1) (based on LLVM 3.0svn)\001\00\000\00\000", !8, !4, !4, !9, null, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !8, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "foo", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !8, scope: !1, type: !3, function: void ()* @foo)
+!1 = !DIFile(filename: "foo.c", directory: "/private/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "Apple clang version 3.0 (tags/Apple/clang-206.1) (based on LLVM 3.0svn)", isOptimized: true, emissionKind: 0, file: !8, enums: !{}, retainedTypes: !{}, subprograms: !9)
+!3 = !DISubroutineType(types: !4)
 !4 = !{null}
-!5 = !MDLocation(line: 4, column: 2, scope: !6)
-!6 = !{!"0xb\003\0012\000", !8, !0} ; [ DW_TAG_lexical_block ]
-!7 = !MDLocation(line: 5, column: 1, scope: !6)
-!8 = !{!"foo.c", !"/private/tmp"}
+!5 = !DILocation(line: 4, column: 2, scope: !6)
+!6 = distinct !DILexicalBlock(line: 3, column: 12, file: !8, scope: !0)
+!7 = !DILocation(line: 5, column: 1, scope: !6)
+!8 = !DIFile(filename: "foo.c", directory: "/private/tmp")
 !9 = !{!0}
-!10 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll b/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
index 5ae62af54581..5881367d9610 100644
--- a/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
+++ b/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
@@ -11,7 +11,7 @@ entry:
         br i1 %0, label %bb, label %return
 
 bb:             ; preds = %entry
-        %1 = load volatile i32* null
+        %1 = load volatile i32, i32* null
         unreachable
         
         br label %return
diff --git a/test/Transforms/SimplifyCFG/trivial-throw.ll b/test/Transforms/SimplifyCFG/trivial-throw.ll
deleted file mode 100644
index ca2b5693e600..000000000000
--- a/test/Transforms/SimplifyCFG/trivial-throw.ll
+++ /dev/null
@@ -1,77 +0,0 @@
-; RUN: opt -simplifycfg -S < %s | FileCheck %s
-; <rdar://problem/13360379>
-
-@_ZTVN10__cxxabiv117__class_type_infoE = external global i8*
-@_ZTS13TestException = linkonce_odr constant [16 x i8] c"13TestException\00"
-@_ZTI13TestException = linkonce_odr unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([16 x i8]* @_ZTS13TestException, i32 0, i32 0) }
-
-define void @throw(i32 %n) #0 {
-entry:
-  %exception = call i8* @__cxa_allocate_exception(i64 1) #4
-  call void @__cxa_throw(i8* %exception, i8* bitcast ({ i8*, i8* }* @_ZTI13TestException to i8*), i8* null) #2
-  unreachable
-}
-
-define void @func() #0 {
-entry:
-; CHECK: func()
-; CHECK: invoke void @throw
-; CHECK-NOT: call void @throw
-  invoke void @throw(i32 42) #0
-          to label %exit unwind label %lpad
-
-lpad:
-  %tmp0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
-          cleanup
-  resume { i8*, i32 } %tmp0
-
-exit:
-  invoke void @abort() #2
-          to label %invoke.cont unwind label %lpad1
-
-invoke.cont:
-  unreachable
-
-lpad1:
-  %tmp1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
-          catch i8* bitcast ({ i8*, i8* }* @_ZTI13TestException to i8*)
-  %tmp2 = extractvalue { i8*, i32 } %tmp1, 1
-  %tmp3 = call i32 @llvm.eh.typeid.for(i8* bitcast ({ i8*, i8* }* @_ZTI13TestException to i8*)) #4
-  %matches = icmp eq i32 %tmp2, %tmp3
-  br i1 %matches, label %catch, label %eh.resume
-
-catch:
-  ret void
-
-eh.resume:
-  resume { i8*, i32 } %tmp1
-}
-
-define linkonce_odr hidden void @__clang_call_terminate(i8*) #1 {
-  %2 = call i8* @__cxa_begin_catch(i8* %0) #4
-  call void @_ZSt9terminatev() #5
-  unreachable
-}
-
-declare void @abort() #2
-
-declare i32 @llvm.eh.typeid.for(i8*) #3
-
-declare void @__cxa_end_catch()
-
-declare i8* @__cxa_allocate_exception(i64)
-
-declare i32 @__gxx_personality_v0(...)
-
-declare void @__cxa_throw(i8*, i8*, i8*)
-
-declare i8* @__cxa_begin_catch(i8*)
-
-declare void @_ZSt9terminatev()
-
-attributes #0 = { ssp uwtable }
-attributes #1 = { noinline noreturn nounwind }
-attributes #2 = { noreturn }
-attributes #3 = { nounwind readnone }
-attributes #4 = { nounwind }
-attributes #5 = { noreturn nounwind }
diff --git a/test/Transforms/SimplifyCFG/unreachable-blocks.ll b/test/Transforms/SimplifyCFG/unreachable-blocks.ll
index 1df0eab6259f..87a64ad47c62 100644
--- a/test/Transforms/SimplifyCFG/unreachable-blocks.ll
+++ b/test/Transforms/SimplifyCFG/unreachable-blocks.ll
@@ -10,12 +10,12 @@ entry:
 
 while_block:                                      ; preds = %and_if_cont2, %and_if_cont
   %newlen = sub i32 %newlen, 1
-  %newptr = getelementptr i8* %newptr, i64 1
+  %newptr = getelementptr i8, i8* %newptr, i64 1
   %test = icmp sgt i32 %newlen, 0
   br i1 %test, label %and_if1, label %and_if_cont2
 
 and_if1:                                          ; preds = %while_block
-  %char = load i8* %newptr
+  %char = load i8, i8* %newptr
   %test2 = icmp ule i8 %char, 32
   br label %and_if_cont2
 
diff --git a/test/Transforms/SimplifyCFG/volatile-phioper.ll b/test/Transforms/SimplifyCFG/volatile-phioper.ll
index 6367451433c1..c366d059d334 100644
--- a/test/Transforms/SimplifyCFG/volatile-phioper.ll
+++ b/test/Transforms/SimplifyCFG/volatile-phioper.ll
@@ -17,19 +17,19 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 define void @test(i8** nocapture %PeiServices) #0 {
 entry:
-  %call = tail call i32 (...)* @Trace() #2
+  %call = tail call i32 (...) @Trace() #2
   %tobool = icmp eq i32 %call, 0
   br i1 %tobool, label %while.body, label %if.then
 
 if.then:                                          ; preds = %entry
-  %call1 = tail call i32 (...)* @Trace() #2
+  %call1 = tail call i32 (...) @Trace() #2
   br label %while.body
 
 while.body:                                       ; preds = %entry, %if.then, %while.body
   %Addr.017 = phi i8* [ %incdec.ptr, %while.body ], [ null, %if.then ], [ null, %entry ]
   %x.016 = phi i8 [ %inc, %while.body ], [ 0, %if.then ], [ 0, %entry ]
   %inc = add i8 %x.016, 1
-  %incdec.ptr = getelementptr inbounds i8* %Addr.017, i64 1
+  %incdec.ptr = getelementptr inbounds i8, i8* %Addr.017, i64 1
   store volatile i8 %x.016, i8* %Addr.017, align 1
   %0 = ptrtoint i8* %incdec.ptr to i64
   %1 = trunc i64 %0 to i32
diff --git a/test/Transforms/Sink/basic.ll b/test/Transforms/Sink/basic.ll
index 4aac6d613a8c..1bbf161921d1 100644
--- a/test/Transforms/Sink/basic.ll
+++ b/test/Transforms/Sink/basic.ll
@@ -8,11 +8,11 @@
 
 ;      CHECK-LABEL: @foo(
 ;      CHECK: true:
-; CHECK-NEXT: %l = load i32* @A
+; CHECK-NEXT: %l = load i32, i32* @A
 ; CHECK-NEXT: ret i32 %l
 
 define i32 @foo(i1 %z) {
-  %l = load i32* @A
+  %l = load i32, i32* @A
   store i32 0, i32* @B
   br i1 %z, label %true, label %false
 true:
@@ -28,7 +28,7 @@ false:
 ; CHECK-NEXT: store i32
 
 define i32 @foo2(i1 %z) {
-  %l = load volatile i32* @A
+  %l = load volatile i32, i32* @A
   store i32 0, i32* @B
   br i1 %z, label %true, label %false
 true:
@@ -75,11 +75,11 @@ entry:
   br i1 %1, label %if, label %endif
 
 if:
-  %2 = getelementptr i32* %0, i32 1
+  %2 = getelementptr i32, i32* %0, i32 1
   store i32 0, i32* %0
   store i32 1, i32* %2
-  %3 = getelementptr i32* %0, i32 %b
-  %4 = load i32* %3
+  %3 = getelementptr i32, i32* %0, i32 %b
+  %4 = load i32, i32* %3
   ret i32 %4
 
 endif:
@@ -100,11 +100,11 @@ entry:
   br i1 %1, label %if, label %endif
 
 if:
-  %2 = getelementptr i32* %0, i32 1
+  %2 = getelementptr i32, i32* %0, i32 1
   store i32 0, i32* %0
   store i32 1, i32* %2
-  %3 = getelementptr i32* %0, i32 %b
-  %4 = load i32* %3
+  %3 = getelementptr i32, i32* %0, i32 %b
+  %4 = load i32, i32* %3
   ret i32 %4
 
 endif:
@@ -131,11 +131,11 @@ if0:
   br i1 %1, label %if, label %endif
 
 if:
-  %2 = getelementptr i32* %0, i32 1
+  %2 = getelementptr i32, i32* %0, i32 1
   store i32 0, i32* %0
   store i32 1, i32* %2
-  %3 = getelementptr i32* %0, i32 %b
-  %4 = load i32* %3
+  %3 = getelementptr i32, i32* %0, i32 %b
+  %4 = load i32, i32* %3
   ret i32 %4
 
 endif:
diff --git a/test/Transforms/SpeculativeExecution/spec.ll b/test/Transforms/SpeculativeExecution/spec.ll
new file mode 100644
index 000000000000..b0953c85dd40
--- /dev/null
+++ b/test/Transforms/SpeculativeExecution/spec.ll
@@ -0,0 +1,195 @@
+; RUN: opt < %s -S -speculative-execution \
+; RUN:   -spec-exec-max-speculation-cost 4 -spec-exec-max-not-hoisted 3 \
+; RUN:   | FileCheck %s
+
+target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
+
+; Hoist in if-then pattern.
+define void @ifThen() {
+; CHECK-LABEL: @ifThen(
+; CHECK: %x = add i32 2, 3
+; CHECK: br i1 true
+  br i1 true, label %a, label %b
+; CHECK: a:
+a:
+  %x = add i32 2, 3
+; CHECK: br label
+  br label %b
+; CHECK: b:
+b:
+; CHECK: ret void
+  ret void
+}
+
+; Hoist in if-else pattern.
+define void @ifElse() {
+; CHECK-LABEL: @ifElse(
+; CHECK: %x = add i32 2, 3
+; CHECK: br i1 true
+  br i1 true, label %b, label %a
+; CHECK: a:
+a:
+  %x = add i32 2, 3
+; CHECK: br label
+  br label %b
+; CHECK: b:
+b:
+; CHECK: ret void
+  ret void
+}
+
+; Hoist in if-then-else pattern if it is equivalent to if-then.
+define void @ifElseThenAsIfThen() {
+; CHECK-LABEL: @ifElseThenAsIfThen(
+; CHECK: %x = add i32 2, 3
+; CHECK: br
+  br i1 true, label %a, label %b
+; CHECK: a:
+a:
+  %x = add i32 2, 3
+; CHECK: br label
+  br label %c
+; CHECK: b:
+b:
+  br label %c
+; CHECK: c
+c:
+  ret void
+}
+
+; Hoist in if-then-else pattern if it is equivalent to if-else.
+define void @ifElseThenAsIfElse() {
+; CHECK-LABEL: @ifElseThenAsIfElse(
+; CHECK: %x = add i32 2, 3
+; CHECK: br
+  br i1 true, label %b, label %a
+; CHECK: a:
+a:
+  %x = add i32 2, 3
+; CHECK: br label
+  br label %c
+; CHECK: b:
+b:
+  br label %c
+; CHECK: c
+c:
+  ret void
+}
+
+; Do not hoist if-then-else pattern if it is not equivalent to if-then
+; or if-else.
+define void @ifElseThen() {
+; CHECK-LABEL: @ifElseThen(
+; CHECK: br
+  br i1 true, label %a, label %b
+; CHECK: a:
+a:
+; CHECK: %x = add
+  %x = add i32 2, 3
+; CHECK: br label
+  br label %c
+; CHECK: b:
+b:
+; CHECK: %y = add
+  %y = add i32 2, 3
+  br label %c
+; CHECK: c
+c:
+  ret void
+}
+
+; Do not hoist loads and do not hoist an instruction past a definition of
+; an operand.
+define void @doNotHoistPastDef() {
+; CHECK-LABEL: @doNotHoistPastDef(
+  br i1 true, label %b, label %a
+; CHECK-NOT: load
+; CHECK-NOT: add
+; CHECK: a:
+a:
+; CHECK: %def = load
+  %def = load i32, i32* null
+; CHECK: %use = add
+  %use = add i32 %def, 0
+  br label %b
+; CHECK: b:
+b:
+  ret void
+}
+
+; Case with nothing to speculate.
+define void @nothingToSpeculate() {
+; CHECK-LABEL: @nothingToSpeculate(
+  br i1 true, label %b, label %a
+; CHECK: a:
+a:
+; CHECK: %def = load
+  %def = load i32, i32* null
+  br label %b
+; CHECK: b:
+b:
+  ret void
+}
+
+; Still hoist if an operand is defined before the block or is itself hoisted.
+define void @hoistIfNotPastDef() {
+; CHECK-LABEL: @hoistIfNotPastDef(
+; CHECK: %x = load
+  %x = load i32, i32* null
+; CHECK: %y = add i32 %x, 1
+; CHECK: %z = add i32 %y, 1
+; CHECK: br
+  br i1 true, label %b, label %a
+; CHECK: a:
+a:
+  %y = add i32 %x, 1
+  %z = add i32 %y, 1
+  br label %b
+; CHECK: b:
+b:
+  ret void
+}
+
+; Do not hoist if the speculation cost is too high.
+define void @costTooHigh() {
+; CHECK-LABEL: @costTooHigh(
+; CHECK: br
+  br i1 true, label %b, label %a
+; CHECK: a:
+a:
+; CHECK: %r1 = add
+  %r1 = add i32 1, 1
+; CHECK: %r2 = add
+  %r2 = add i32 1, 1
+; CHECK: %r3 = add
+  %r3 = add i32 1, 1
+; CHECK: %r4 = add
+  %r4 = add i32 1, 1
+; CHECK: %r5 = add
+  %r5 = add i32 1, 1
+  br label %b
+; CHECK: b:
+b:
+  ret void
+}
+
+; Do not hoist if too many instructions are left behind.
+define void @tooMuchLeftBehind() {
+; CHECK-LABEL: @tooMuchLeftBehind(
+; CHECK: br
+  br i1 true, label %b, label %a
+; CHECK: a:
+a:
+; CHECK: %x = load
+  %x = load i32, i32* null
+; CHECK: %r1 = add
+  %r1 = add i32 %x, 1
+; CHECK: %r2 = add
+  %r2 = add i32 %x, 1
+; CHECK: %r3 = add
+  %r3 = add i32 %x, 1
+  br label %b
+; CHECK: b:
+b:
+  ret void
+}
diff --git a/test/Transforms/StraightLineStrengthReduce/NVPTX/lit.local.cfg b/test/Transforms/StraightLineStrengthReduce/NVPTX/lit.local.cfg
new file mode 100644
index 000000000000..2cb98eb371b2
--- /dev/null
+++ b/test/Transforms/StraightLineStrengthReduce/NVPTX/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'NVPTX' in config.root.targets:
+    config.unsupported = True
diff --git a/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll b/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll
new file mode 100644
index 000000000000..03c0356eb5b4
--- /dev/null
+++ b/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll
@@ -0,0 +1,74 @@
+; RUN: opt < %s -separate-const-offset-from-gep -slsr -gvn -S | FileCheck %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s --check-prefix=PTX
+
+target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
+target triple = "nvptx64-unknown-unknown"
+
+; arr[i + 5]
+; arr[i * 2 + 5]
+; arr[i * 3 + 5]
+; arr[i * 4 + 5]
+;
+;   => reassociate-geps
+;
+; *(&arr[i] + 5)
+; *(&arr[i * 2] + 5)
+; *(&arr[i * 3] + 5)
+; *(&arr[i * 4] + 5)
+;
+;   => slsr
+;
+; p1 = &arr[i]
+; *(p1 + 5)
+; p2 = p1 + i
+; *(p2 + 5)
+; p3 = p2 + i
+; *(p3 + 5)
+; p4 = p3 + i
+; *(p4 + 5)
+define void @slsr_after_reassociate_geps(float* %arr, i32 %i) {
+; CHECK-LABEL: @slsr_after_reassociate_geps(
+; PTX-LABEL: .visible .func slsr_after_reassociate_geps(
+; PTX: ld.param.u64 [[arr:%rd[0-9]+]], [slsr_after_reassociate_geps_param_0];
+; PTX: ld.param.u32 [[i:%r[0-9]+]], [slsr_after_reassociate_geps_param_1];
+  %i2 = shl nsw i32 %i, 1
+  %i3 = mul nsw i32 %i, 3
+  %i4 = shl nsw i32 %i, 2
+
+  %j1 = add nsw i32 %i, 5
+  %p1 = getelementptr inbounds float, float* %arr, i32 %j1
+; CHECK: [[b1:%[0-9]+]] = getelementptr float, float* %arr, i64 [[bump:%[0-9]+]]
+; PTX: mul.wide.s32 [[i4:%rd[0-9]+]], [[i]], 4;
+; PTX: add.s64 [[base1:%rd[0-9]+]], [[arr]], [[i4]];
+  %v1 = load float, float* %p1, align 4
+; PTX: ld.f32 {{%f[0-9]+}}, {{\[}}[[base1]]+20];
+  call void @foo(float %v1)
+
+  %j2 = add nsw i32 %i2, 5
+  %p2 = getelementptr inbounds float, float* %arr, i32 %j2
+; CHECK: [[b2:%[0-9]+]] = getelementptr float, float* [[b1]], i64 [[bump]]
+; PTX: add.s64 [[base2:%rd[0-9]+]], [[base1]], [[i4]];
+  %v2 = load float, float* %p2, align 4
+; PTX: ld.f32 {{%f[0-9]+}}, {{\[}}[[base2]]+20];
+  call void @foo(float %v2)
+
+  %j3 = add nsw i32 %i3, 5
+  %p3 = getelementptr inbounds float, float* %arr, i32 %j3
+; CHECK: [[b3:%[0-9]+]] = getelementptr float, float* [[b2]], i64 [[bump]]
+; PTX: add.s64 [[base3:%rd[0-9]+]], [[base2]], [[i4]];
+  %v3 = load float, float* %p3, align 4
+; PTX: ld.f32 {{%f[0-9]+}}, {{\[}}[[base3]]+20];
+  call void @foo(float %v3)
+
+  %j4 = add nsw i32 %i4, 5
+  %p4 = getelementptr inbounds float, float* %arr, i32 %j4
+; CHECK: [[b4:%[0-9]+]] = getelementptr float, float* [[b3]], i64 [[bump]]
+; PTX: add.s64 [[base4:%rd[0-9]+]], [[base3]], [[i4]];
+  %v4 = load float, float* %p4, align 4
+; PTX: ld.f32 {{%f[0-9]+}}, {{\[}}[[base4]]+20];
+  call void @foo(float %v4)
+
+  ret void
+}
+
+declare void @foo(float)
diff --git a/test/Transforms/StraightLineStrengthReduce/X86/lit.local.cfg b/test/Transforms/StraightLineStrengthReduce/X86/lit.local.cfg
new file mode 100644
index 000000000000..c8625f4d9d24
--- /dev/null
+++ b/test/Transforms/StraightLineStrengthReduce/X86/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'X86' in config.root.targets:
+    config.unsupported = True
diff --git a/test/Transforms/StraightLineStrengthReduce/X86/no-slsr.ll b/test/Transforms/StraightLineStrengthReduce/X86/no-slsr.ll
new file mode 100644
index 000000000000..f11cbc5897a6
--- /dev/null
+++ b/test/Transforms/StraightLineStrengthReduce/X86/no-slsr.ll
@@ -0,0 +1,44 @@
+; RUN: opt < %s -slsr -gvn -S | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; Do not perform SLSR on &input[s] and &input[s * 2] which fit into addressing
+; modes of X86.
+define i32 @no_slsr_gep(i32* %input, i64 %s) {
+; CHECK-LABEL: @no_slsr_gep(
+  ; v0 = input[0];
+  %p0 = getelementptr inbounds i32, i32* %input, i64 0
+  %v0 = load i32, i32* %p0
+
+  ; v1 = input[s];
+  %p1 = getelementptr inbounds i32, i32* %input, i64 %s
+; CHECK: %p1 = getelementptr inbounds i32, i32* %input, i64 %s
+  %v1 = load i32, i32* %p1
+
+  ; v2 = input[s * 2];
+  %s2 = mul nsw i64 %s, 2
+  %p2 = getelementptr inbounds i32, i32* %input, i64 %s2
+; CHECK: %p2 = getelementptr inbounds i32, i32* %input, i64 %s2
+  %v2 = load i32, i32* %p2
+
+  ; return v0 + v1 + v2;
+  %1 = add i32 %v0, %v1
+  %2 = add i32 %1, %v2
+  ret i32 %2
+}
+
+define void @no_slsr_add(i32 %b, i32 %s) {
+; CHECK-LABEL: @no_slsr_add(
+  %1 = add i32 %b, %s
+; CHECK: add i32 %b, %s
+  call void @foo(i32 %1)
+  %s2 = mul i32 %s, 2
+; CHECK: %s2 = mul i32 %s, 2
+  %2 = add i32 %b, %s2
+; CHECK: add i32 %b, %s2
+  call void @foo(i32 %2)
+  ret void
+}
+
+declare void @foo(i32 %a)
diff --git a/test/Transforms/StraightLineStrengthReduce/slsr-add.ll b/test/Transforms/StraightLineStrengthReduce/slsr-add.ll
new file mode 100644
index 000000000000..e25ddc2888a3
--- /dev/null
+++ b/test/Transforms/StraightLineStrengthReduce/slsr-add.ll
@@ -0,0 +1,101 @@
+; RUN: opt < %s -slsr -gvn -S | FileCheck %s
+
+target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
+
+define void @shl(i32 %b, i32 %s) {
+; CHECK-LABEL: @shl(
+  %1 = add i32 %b, %s
+; [[BASIS:%[a-zA-Z0-9]+]] = add i32 %b, %s
+  call void @foo(i32 %1)
+  %s2 = shl i32 %s, 1
+  %2 = add i32 %b, %s2
+; add i32 [[BASIS]], %s
+  call void @foo(i32 %2)
+  ret void
+}
+
+define void @stride_is_2s(i32 %b, i32 %s) {
+; CHECK-LABEL: @stride_is_2s(
+  %s2 = shl i32 %s, 1
+; CHECK: %s2 = shl i32 %s, 1
+  %1 = add i32 %b, %s2
+; CHECK: [[t1:%[a-zA-Z0-9]+]] = add i32 %b, %s2
+  call void @foo(i32 %1)
+  %s4 = shl i32 %s, 2
+  %2 = add i32 %b, %s4
+; CHECK: [[t2:%[a-zA-Z0-9]+]] = add i32 [[t1]], %s2
+  call void @foo(i32 %2)
+  %s6 = mul i32 %s, 6
+  %3 = add i32 %b, %s6
+; CHECK: add i32 [[t2]], %s2
+  call void @foo(i32 %3)
+  ret void
+}
+
+define void @stride_is_3s(i32 %b, i32 %s) {
+; CHECK-LABEL: @stride_is_3s(
+  %1 = add i32 %s, %b
+; CHECK: [[t1:%[a-zA-Z0-9]+]] = add i32 %s, %b
+  call void @foo(i32 %1)
+  %s4 = shl i32 %s, 2
+  %2 = add i32 %s4, %b
+; CHECK: [[bump:%[a-zA-Z0-9]+]] = mul i32 %s, 3
+; CHECK: [[t2:%[a-zA-Z0-9]+]] = add i32 [[t1]], [[bump]]
+  call void @foo(i32 %2)
+  %s7 = mul i32 %s, 7
+  %3 = add i32 %s7, %b
+; CHECK: add i32 [[t2]], [[bump]]
+  call void @foo(i32 %3)
+  ret void
+}
+
+; foo(b + 6 * s);
+; foo(b + 4 * s);
+; foo(b + 2 * s);
+;   =>
+; t1 = b + 6 * s;
+; foo(t1);
+; s2 = 2 * s;
+; t2 = t1 - s2;
+; foo(t2);
+; t3 = t2 - s2;
+; foo(t3);
+define void @stride_is_minus_2s(i32 %b, i32 %s) {
+; CHECK-LABEL: @stride_is_minus_2s(
+  %s6 = mul i32 %s, 6
+  %1 = add i32 %b, %s6
+; CHECK: [[t1:%[a-zA-Z0-9]+]] = add i32 %b, %s6
+; CHECK: call void @foo(i32 [[t1]])
+  call void @foo(i32 %1)
+  %s4 = shl i32 %s, 2
+  %2 = add i32 %b, %s4
+; CHECK: [[bump:%[a-zA-Z0-9]+]] = shl i32 %s, 1
+; CHECK: [[t2:%[a-zA-Z0-9]+]] = sub i32 [[t1]], [[bump]]
+  call void @foo(i32 %2)
+; CHECK: call void @foo(i32 [[t2]])
+  %s2 = shl i32 %s, 1
+  %3 = add i32 %b, %s2
+; CHECK: [[t3:%[a-zA-Z0-9]+]] = sub i32 [[t2]], [[bump]]
+  call void @foo(i32 %3)
+; CHECK: call void @foo(i32 [[t3]])
+  ret void
+}
+
+; t = b + (s << 3);
+; foo(t);
+; foo(b + s);
+;
+; do not rewrite b + s to t - 7 * s because the latter is more complicated.
+define void @simple_enough(i32 %b, i32 %s) {
+; CHECK-LABEL: @simple_enough(
+  %s8 = shl i32 %s, 3
+  %1 = add i32 %b, %s8
+  call void @foo(i32 %1)
+  %2 = add i32 %b, %s
+; CHECK: [[t:%[a-zA-Z0-9]+]] = add i32 %b, %s{{$}}
+  call void @foo(i32 %2)
+; CHECK: call void @foo(i32 [[t]])
+  ret void
+}
+
+declare void @foo(i32)
diff --git a/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll b/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll
new file mode 100644
index 000000000000..bd92780a036c
--- /dev/null
+++ b/test/Transforms/StraightLineStrengthReduce/slsr-gep.ll
@@ -0,0 +1,168 @@
+; RUN: opt < %s -slsr -gvn -S | FileCheck %s
+
+target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
+
+; foo(input[0]);
+; foo(input[s]);
+; foo(input[s * 2]);
+;   =>
+; p0 = &input[0];
+; foo(*p);
+; p1 = p0 + s;
+; foo(*p1);
+; p2 = p1 + s;
+; foo(*p2);
+define void @slsr_gep(i32* %input, i64 %s) {
+; CHECK-LABEL: @slsr_gep(
+  ; v0 = input[0];
+  %p0 = getelementptr inbounds i32, i32* %input, i64 0
+  %v0 = load i32, i32* %p0
+  call void @foo(i32 %v0)
+
+  ; v1 = input[s];
+  %p1 = getelementptr inbounds i32, i32* %input, i64 %s
+; CHECK: %p1 = getelementptr inbounds i32, i32* %input, i64 %s
+  %v1 = load i32, i32* %p1
+  call void @foo(i32 %v1)
+
+  ; v2 = input[s * 2];
+  %s2 = shl nsw i64 %s, 1
+  %p2 = getelementptr inbounds i32, i32* %input, i64 %s2
+; CHECK: %p2 = getelementptr inbounds i32, i32* %p1, i64 %s
+  %v2 = load i32, i32* %p2
+  call void @foo(i32 %v2)
+
+  ret void
+}
+
+; foo(input[0]);
+; foo(input[(long)s]);
+; foo(input[(long)(s * 2)]);
+;   =>
+; p0 = &input[0];
+; foo(*p);
+; p1 = p0 + (long)s;
+; foo(*p1);
+; p2 = p1 + (long)s;
+; foo(*p2);
+define void @slsr_gep_sext(i32* %input, i32 %s) {
+; CHECK-LABEL: @slsr_gep_sext(
+  ; v0 = input[0];
+  %p0 = getelementptr inbounds i32, i32* %input, i64 0
+  %v0 = load i32, i32* %p0
+  call void @foo(i32 %v0)
+
+  ; v1 = input[s];
+  %t = sext i32 %s to i64
+  %p1 = getelementptr inbounds i32, i32* %input, i64 %t
+; CHECK: %p1 = getelementptr inbounds i32, i32* %input, i64 %t
+  %v1 = load i32, i32* %p1
+  call void @foo(i32 %v1)
+
+  ; v2 = input[s * 2];
+  %s2 = shl nsw i32 %s, 1
+  %t2 = sext i32 %s2 to i64
+  %p2 = getelementptr inbounds i32, i32* %input, i64 %t2
+; CHECK: %p2 = getelementptr inbounds i32, i32* %p1, i64 %t
+  %v2 = load i32, i32* %p2
+  call void @foo(i32 %v2)
+
+  ret void
+}
+
+; int input[10][5];
+; foo(input[s][t]);
+; foo(input[s * 2][t]);
+; foo(input[s * 3][t]);
+;   =>
+; p0 = &input[s][t];
+; foo(*p0);
+; p1 = p0 + 5s;
+; foo(*p1);
+; p2 = p1 + 5s;
+; foo(*p2);
+define void @slsr_gep_2d([10 x [5 x i32]]* %input, i64 %s, i64 %t) {
+; CHECK-LABEL: @slsr_gep_2d(
+  ; v0 = input[s][t];
+  %p0 = getelementptr inbounds [10 x [5 x i32]], [10 x [5 x i32]]* %input, i64 0, i64 %s, i64 %t
+  %v0 = load i32, i32* %p0
+  call void @foo(i32 %v0)
+
+  ; v1 = input[s * 2][t];
+  %s2 = shl nsw i64 %s, 1
+; CHECK: [[BUMP:%[a-zA-Z0-9]+]] = mul i64 %s, 5
+  %p1 = getelementptr inbounds [10 x [5 x i32]], [10 x [5 x i32]]* %input, i64 0, i64 %s2, i64 %t
+; CHECK: %p1 = getelementptr inbounds i32, i32* %p0, i64 [[BUMP]]
+  %v1 = load i32, i32* %p1
+  call void @foo(i32 %v1)
+
+  ; v3 = input[s * 3][t];
+  %s3 = mul nsw i64 %s, 3
+  %p2 = getelementptr inbounds [10 x [5 x i32]], [10 x [5 x i32]]* %input, i64 0, i64 %s3, i64 %t
+; CHECK: %p2 = getelementptr inbounds i32, i32* %p1, i64 [[BUMP]]
+  %v2 = load i32, i32* %p2
+  call void @foo(i32 %v2)
+
+  ret void
+}
+
+%struct.S = type <{ i64, i32 }>
+
+; In this case, the bump
+;     = (char *)&input[s * 2][t].f1 - (char *)&input[s][t].f1
+;     = 60 * s
+; which may not be divisible by typeof(input[s][t].f1) = 8. Therefore, we
+; rewrite the candidates using byte offset instead of index offset as in
+; @slsr_gep_2d.
+define void @slsr_gep_uglygep([10 x [5 x %struct.S]]* %input, i64 %s, i64 %t) {
+; CHECK-LABEL: @slsr_gep_uglygep(
+  ; v0 = input[s][t].f1;
+  %p0 = getelementptr inbounds [10 x [5 x %struct.S]], [10 x [5 x %struct.S]]* %input, i64 0, i64 %s, i64 %t, i32 0
+  %v0 = load i64, i64* %p0
+  call void @bar(i64 %v0)
+
+  ; v1 = input[s * 2][t].f1;
+  %s2 = shl nsw i64 %s, 1
+; CHECK: [[BUMP:%[a-zA-Z0-9]+]] = mul i64 %s, 60
+  %p1 = getelementptr inbounds [10 x [5 x %struct.S]], [10 x [5 x %struct.S]]* %input, i64 0, i64 %s2, i64 %t, i32 0
+; CHECK: getelementptr inbounds i8, i8* %{{[0-9]+}}, i64 [[BUMP]]
+  %v1 = load i64, i64* %p1
+  call void @bar(i64 %v1)
+
+  ; v2 = input[s * 3][t].f1;
+  %s3 = mul nsw i64 %s, 3
+  %p2 = getelementptr inbounds [10 x [5 x %struct.S]], [10 x [5 x %struct.S]]* %input, i64 0, i64 %s3, i64 %t, i32 0
+; CHECK: getelementptr inbounds i8, i8* %{{[0-9]+}}, i64 [[BUMP]]
+  %v2 = load i64, i64* %p2
+  call void @bar(i64 %v2)
+
+  ret void
+}
+
+define void @slsr_out_of_bounds_gep(i32* %input, i32 %s) {
+; CHECK-LABEL: @slsr_out_of_bounds_gep(
+  ; v0 = input[0];
+  %p0 = getelementptr i32, i32* %input, i64 0
+  %v0 = load i32, i32* %p0
+  call void @foo(i32 %v0)
+
+  ; v1 = input[(long)s];
+  %t = sext i32 %s to i64
+  %p1 = getelementptr i32, i32* %input, i64 %t
+; CHECK: %p1 = getelementptr i32, i32* %input, i64 %t
+  %v1 = load i32, i32* %p1
+  call void @foo(i32 %v1)
+
+  ; v2 = input[(long)(s * 2)];
+  %s2 = shl nsw i32 %s, 1
+  %t2 = sext i32 %s2 to i64
+  %p2 = getelementptr i32, i32* %input, i64 %t2
+; CHECK: %p2 = getelementptr i32, i32* %p1, i64 %t
+  %v2 = load i32, i32* %p2
+  call void @foo(i32 %v2)
+
+  ret void
+}
+
+declare void @foo(i32)
+declare void @bar(i64)
diff --git a/test/Transforms/StraightLineStrengthReduce/slsr-mul.ll b/test/Transforms/StraightLineStrengthReduce/slsr-mul.ll
new file mode 100644
index 000000000000..56b1d1fc5cdd
--- /dev/null
+++ b/test/Transforms/StraightLineStrengthReduce/slsr-mul.ll
@@ -0,0 +1,147 @@
+; RUN: opt < %s -slsr -gvn -S | FileCheck %s
+
+target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
+
+define void @slsr1(i32 %b, i32 %s) {
+; CHECK-LABEL: @slsr1(
+  ; foo(b * s);
+  %mul0 = mul i32 %b, %s
+; CHECK: mul i32
+; CHECK-NOT: mul i32
+  call void @foo(i32 %mul0)
+
+  ; foo((b + 1) * s);
+  %b1 = add i32 %b, 1
+  %mul1 = mul i32 %b1, %s
+  call void @foo(i32 %mul1)
+
+  ; foo((b + 2) * s);
+  %b2 = add i32 %b, 2
+  %mul2 = mul i32 %b2, %s
+  call void @foo(i32 %mul2)
+
+  ret void
+}
+
+define void @non_canonicalized(i32 %b, i32 %s) {
+; CHECK-LABEL: @non_canonicalized(
+  ; foo(b * s);
+  %mul0 = mul i32 %b, %s
+; CHECK: mul i32
+; CHECK-NOT: mul i32
+  call void @foo(i32 %mul0)
+
+  ; foo((1 + b) * s);
+  %b1 = add i32 1, %b
+  %mul1 = mul i32 %b1, %s
+  call void @foo(i32 %mul1)
+
+  ; foo((2 + b) * s);
+  %b2 = add i32 2, %b
+  %mul2 = mul i32 %b2, %s
+  call void @foo(i32 %mul2)
+
+  ret void
+}
+
+define void @or(i32 %a, i32 %s) {
+  %b = shl i32 %a, 1
+; CHECK-LABEL: @or(
+  ; foo(b * s);
+  %mul0 = mul i32 %b, %s
+; CHECK: [[base:[^ ]+]] = mul i32
+  call void @foo(i32 %mul0)
+
+  ; foo((b | 1) * s);
+  %b1 = or i32 %b, 1
+  %mul1 = mul i32 %b1, %s
+; CHECK: add i32 [[base]], %s
+  call void @foo(i32 %mul1)
+
+  ; foo((b | 2) * s);
+  %b2 = or i32 %b, 2
+  %mul2 = mul i32 %b2, %s
+; CHECK: mul i32 %b2, %s
+  call void @foo(i32 %mul2)
+
+  ret void
+}
+
+; foo(a * b)
+; foo((a + 1) * b)
+; foo(a * (b + 1))
+; foo((a + 1) * (b + 1))
+define void @slsr2(i32 %a, i32 %b) {
+; CHECK-LABEL: @slsr2(
+  %a1 = add i32 %a, 1
+  %b1 = add i32 %b, 1
+  %mul0 = mul i32 %a, %b
+; CHECK: mul i32
+; CHECK-NOT: mul i32
+  %mul1 = mul i32 %a1, %b
+  %mul2 = mul i32 %a, %b1
+  %mul3 = mul i32 %a1, %b1
+
+  call void @foo(i32 %mul0)
+  call void @foo(i32 %mul1)
+  call void @foo(i32 %mul2)
+  call void @foo(i32 %mul3)
+
+  ret void
+}
+
+; The bump is a multiple of the stride.
+;
+; foo(b * s);
+; foo((b + 2) * s);
+; foo((b + 4) * s);
+;   =>
+; mul0 = b * s;
+; bump = s * 2;
+; mul1 = mul0 + bump; // GVN ensures mul1 and mul2 use the same bump.
+; mul2 = mul1 + bump;
+define void @slsr3(i32 %b, i32 %s) {
+; CHECK-LABEL: @slsr3(
+  %mul0 = mul i32 %b, %s
+; CHECK: mul i32
+  call void @foo(i32 %mul0)
+
+  %b1 = add i32 %b, 2
+  %mul1 = mul i32 %b1, %s
+; CHECK: [[BUMP:%[a-zA-Z0-9]+]] = shl i32 %s, 1
+; CHECK: %mul1 = add i32 %mul0, [[BUMP]]
+  call void @foo(i32 %mul1)
+
+  %b2 = add i32 %b, 4
+  %mul2 = mul i32 %b2, %s
+; CHECK: %mul2 = add i32 %mul1, [[BUMP]]
+  call void @foo(i32 %mul2)
+
+  ret void
+}
+
+; Do not rewrite a candidate if its potential basis does not dominate it.
+;
+; if (cond)
+;   foo(a * b);
+; foo((a + 1) * b);
+define void @not_dominate(i1 %cond, i32 %a, i32 %b) {
+; CHECK-LABEL: @not_dominate(
+entry:
+  %a1 = add i32 %a, 1
+  br i1 %cond, label %then, label %merge
+
+then:
+  %mul0 = mul i32 %a, %b
+; CHECK: %mul0 = mul i32 %a, %b
+  call void @foo(i32 %mul0)
+  br label %merge
+
+merge:
+  %mul1 = mul i32 %a1, %b
+; CHECK: %mul1 = mul i32 %a1, %b
+  call void @foo(i32 %mul1)
+  ret void
+}
+
+declare void @foo(i32)
diff --git a/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll b/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll
index f2c705a317af..3b1fd74b9813 100644
--- a/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll
+++ b/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll
@@ -18,17 +18,17 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.lv.foo = !{!5}
 !llvm.dbg.gv = !{!8}
 
-!0 = !{!"0x2e\00foo\00foo\00foo\002\000\001\000\006\000\001\000", !12, !1, !3, null, void ()* @foo, null, null, null} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !12} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\001\00\000\00\000", !12, !4, !4, null, null, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !12, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "foo", linkageName: "foo", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, file: !12, scope: !1, type: !3, function: void ()* @foo)
+!1 = !DIFile(filename: "b.c", directory: "/tmp")
+!2 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 0, file: !12, enums: !4, retainedTypes: !4)
+!3 = !DISubroutineType(types: !4)
 !4 = !{null}
-!5 = !{!"0x100\00y\003\000", !6, !1, !7} ; [ DW_TAG_auto_variable ]
-!6 = !{!"0xb\002\000\000", !12, !0} ; [ DW_TAG_lexical_block ]
-!7 = !{!"0x24\00int\000\0032\0032\000\000\005", !12, !1} ; [ DW_TAG_base_type ]
-!8 = !{!"0x34\00x\00x\00\001\000\001", !1, !1, !7, i32* @x} ; [ DW_TAG_variable ]
+!5 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y", line: 3, scope: !6, file: !1, type: !7)
+!6 = distinct !DILexicalBlock(line: 2, column: 0, file: !12, scope: !0)
+!7 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = !DIGlobalVariable(name: "x", line: 1, isLocal: false, isDefinition: true, scope: !1, file: !1, type: !7, variable: i32* @x)
 !9 = !{i32 0}
-!10 = !MDLocation(line: 3, scope: !6)
-!11 = !MDLocation(line: 4, scope: !6)
-!12 = !{!"b.c", !"/tmp"}
-!13 = !{i32 1, !"Debug Info Version", i32 2}
+!10 = !DILocation(line: 3, scope: !6)
+!11 = !DILocation(line: 4, scope: !6)
+!12 = !DIFile(filename: "b.c", directory: "/tmp")
+!13 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/StripSymbols/2010-08-25-crash.ll b/test/Transforms/StripSymbols/2010-08-25-crash.ll
index 1534647c2a71..f77ed11d912c 100644
--- a/test/Transforms/StripSymbols/2010-08-25-crash.ll
+++ b/test/Transforms/StripSymbols/2010-08-25-crash.ll
@@ -7,18 +7,18 @@ entry:
 !llvm.dbg.cu = !{!2}
 !llvm.module.flags = !{!14}
 
-!0 = !{!"0x2e\00foo\00foo\00foo\003\000\001\000\006\000\000\000", !10, !1, !3, null, i32 ()* @foo, null, null, null} ; [ DW_TAG_subprogram ]
-!1 = !{!"0x29", !10} ; [ DW_TAG_file_type ]
-!2 = !{!"0x11\0012\00clang version 2.8 (trunk 112062)\001\00\000\00\001", !10, !11, !11, !12, !13, null} ; [ DW_TAG_compile_unit ]
-!3 = !{!"0x15\00\000\000\000\000\000\000", !10, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!0 = !DISubprogram(name: "foo", linkageName: "foo", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !10, scope: !1, type: !3, function: i32 ()* @foo)
+!1 = !DIFile(filename: "/tmp/a.c", directory: "/Volumes/Lalgate/clean/D.CW")
+!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 2.8 (trunk 112062)", isOptimized: true, emissionKind: 1, file: !10, enums: !11, retainedTypes: !11, subprograms: !12, globals: !13)
+!3 = !DISubroutineType(types: !4)
 !4 = !{!5}
-!5 = !{!"0x24\00int\000\0032\0032\000\000\005", !10, !1} ; [ DW_TAG_base_type ]
-!6 = !{!"0x34\00i\00i\00i\002\001\001", !1, !1, !7, i32 0, null} ; [ DW_TAG_variable ]
-!7 = !{!"0x26\00\000\000\000\000\000", !10, !1, !5} ; [ DW_TAG_const_type ]
-!8 = !MDLocation(line: 3, column: 13, scope: !9)
-!9 = !{!"0xb\003\0011\000", !10, !0} ; [ DW_TAG_lexical_block ]
-!10 = !{!"/tmp/a.c", !"/Volumes/Lalgate/clean/D.CW"}
-!11 = !{i32 0}
+!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!6 = !DIGlobalVariable(name: "i", linkageName: "i", line: 2, isLocal: true, isDefinition: true, scope: !1, file: !1, type: !7)
+!7 = !DIDerivedType(tag: DW_TAG_const_type, file: !10, scope: !1, baseType: !5)
+!8 = !DILocation(line: 3, column: 13, scope: !9)
+!9 = distinct !DILexicalBlock(line: 3, column: 11, file: !10, scope: !0)
+!10 = !DIFile(filename: "/tmp/a.c", directory: "/Volumes/Lalgate/clean/D.CW")
+!11 = !{}
 !12 = !{!0}
 !13 = !{!6}
-!14 = !{i32 1, !"Debug Info Version", i32 2}
+!14 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/StripSymbols/strip-dead-debug-info.ll b/test/Transforms/StripSymbols/strip-dead-debug-info.ll
index aca7cd608470..08eff003dfca 100644
--- a/test/Transforms/StripSymbols/strip-dead-debug-info.ll
+++ b/test/Transforms/StripSymbols/strip-dead-debug-info.ll
@@ -18,8 +18,8 @@ entry:
 ; Function Attrs: nounwind readonly ssp
 define i32 @foo(i32 %i) #2 {
 entry:
-  tail call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !15, metadata !{}), !dbg !20
-  %.0 = load i32* @xyz, align 4
+  tail call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !15, metadata !DIExpression()), !dbg !20
+  %.0 = load i32, i32* @xyz, align 4
   ret i32 %.0, !dbg !21
 }
 
@@ -30,29 +30,29 @@ attributes #2 = { nounwind readonly ssp }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!25}
 
-!0 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\001\00\000\00\001", !1, !2, !2, !23, !24, null} ; [ DW_TAG_compile_unit ] [/tmp//g.c] [DW_LANG_C89]
-!1 = !{!"g.c", !"/tmp/"}
+!0 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: true, emissionKind: 1, file: !1, enums: !{}, retainedTypes: !{}, subprograms: !23, globals: !24)
+!1 = !DIFile(filename: "g.c", directory: "/tmp/")
 !2 = !{null}
-!3 = !{!"0x2e\00bar\00bar\00\005\001\001\000\006\000\001\000", !1, null, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 5] [local] [def] [scope 0] [bar]
-!4 = !{!"0x15\00\000\000\000\000\000\000", !1, !5, null, !2, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!5 = !{!"0x29", !1}          ; [ DW_TAG_file_type ] [/tmp//g.c]
-!6 = !{!"0x2e\00fn\00fn\00fn\006\000\001\000\006\000\001\000", !1, null, !7, null, i32 ()* @fn, null, null, null} ; [ DW_TAG_subprogram ] [line 6] [def] [scope 0] [fn]
-!7 = !{!"0x15\00\000\000\000\000\000\000", !1, !5, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!3 = !DISubprogram(name: "bar", line: 5, isLocal: true, isDefinition: true, virtualIndex: 6, isOptimized: true, file: !1, scope: null, type: !4)
+!4 = !DISubroutineType(types: !2)
+!5 = !DIFile(filename: "g.c", directory: "/tmp/")
+!6 = !DISubprogram(name: "fn", linkageName: "fn", line: 6, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, file: !1, scope: null, type: !7, function: i32 ()* @fn)
+!7 = !DISubroutineType(types: !8)
 !8 = !{!9}
-!9 = !{!"0x24\00int\000\0032\0032\000\000\005", !1, !5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = !{!"0x2e\00foo\00foo\00foo\007\000\001\000\006\000\001\000", !1, null, !11, null, i32 (i32)* @foo, null, null, null} ; [ DW_TAG_subprogram ] [line 7] [def] [scope 0] [foo]
-!11 = !{!"0x15\00\000\000\000\000\000\000", !1, !5, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!9 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !DISubprogram(name: "foo", linkageName: "foo", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, file: !1, scope: null, type: !11, function: i32 (i32)* @foo)
+!11 = !DISubroutineType(types: !12)
 !12 = !{!9, !9}
-!13 = !{!"0x100\00bb\005\000", !14, !5, !9} ; [ DW_TAG_auto_variable ]
-!14 = !{!"0xb\005\000\000", !1, !3} ; [ DW_TAG_lexical_block ] [/tmp//g.c]
-!15 = !{!"0x101\00i\007\000", !10, !5, !9} ; [ DW_TAG_arg_variable ]
-!16 = !{!"0x34\00abcd\00abcd\00\002\001\001", !5, !5, !9, null, null} ; [ DW_TAG_variable ]
-!17 = !{!"0x34\00xyz\00xyz\00\003\000\001", !5, !5, !9, i32* @xyz, null} ; [ DW_TAG_variable ]
-!18 = !MDLocation(line: 6, scope: !19)
-!19 = !{!"0xb\006\000\000", !1, !6} ; [ DW_TAG_lexical_block ] [/tmp//g.c]
-!20 = !MDLocation(line: 7, scope: !10)
-!21 = !MDLocation(line: 10, scope: !22)
-!22 = !{!"0xb\007\000\000", !1, !10} ; [ DW_TAG_lexical_block ] [/tmp//g.c]
+!13 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "bb", line: 5, scope: !14, file: !5, type: !9)
+!14 = distinct !DILexicalBlock(line: 5, column: 0, file: !1, scope: !3)
+!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 7, arg: 0, scope: !10, file: !5, type: !9)
+!16 = !DIGlobalVariable(name: "abcd", line: 2, isLocal: true, isDefinition: true, scope: !5, file: !5, type: !9)
+!17 = !DIGlobalVariable(name: "xyz", line: 3, isLocal: false, isDefinition: true, scope: !5, file: !5, type: !9, variable: i32* @xyz)
+!18 = !DILocation(line: 6, scope: !19)
+!19 = distinct !DILexicalBlock(line: 6, column: 0, file: !1, scope: !6)
+!20 = !DILocation(line: 7, scope: !10)
+!21 = !DILocation(line: 10, scope: !22)
+!22 = distinct !DILexicalBlock(line: 7, column: 0, file: !1, scope: !10)
 !23 = !{!3, !6, !10}
 !24 = !{!16, !17}
-!25 = !{i32 1, !"Debug Info Version", i32 2}
+!25 = !{i32 1, !"Debug Info Version", i32 3}
diff --git a/test/Transforms/StructurizeCFG/branch-on-argument.ll b/test/Transforms/StructurizeCFG/branch-on-argument.ll
index 4eba0cd8fe15..386994f1fd90 100644
--- a/test/Transforms/StructurizeCFG/branch-on-argument.ll
+++ b/test/Transforms/StructurizeCFG/branch-on-argument.ll
@@ -28,7 +28,7 @@ entry:
 
 for.body:
   %i = phi i32 [0, %entry], [%i.inc, %end.loop]
-  %ptr = getelementptr i32 addrspace(1)* %out, i32 %i
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i32 %i
   store i32 %i, i32 addrspace(1)* %ptr, align 4
   br i1 %arg, label %mid.loop, label %end.loop
 
diff --git a/test/Transforms/StructurizeCFG/loop-multiple-exits.ll b/test/Transforms/StructurizeCFG/loop-multiple-exits.ll
index 45f3165671e1..40f6be9670a3 100644
--- a/test/Transforms/StructurizeCFG/loop-multiple-exits.ll
+++ b/test/Transforms/StructurizeCFG/loop-multiple-exits.ll
@@ -23,7 +23,7 @@ for.cond:                                         ; preds = %for.inc, %entry
 
 ; CHECK: for.body:
 for.body:                                         ; preds = %for.cond
-  %arrayidx = getelementptr inbounds i32 addrspace(1)* %out, i32 %i.0
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %i.0
   store i32 %i.0, i32 addrspace(1)* %arrayidx, align 4
   %cmp1 = icmp ugt i32 %i.0, %cond_b
 ; CHECK: br i1 %{{[0-9a-zA-Z_]+}}, label %for.inc, label %[[FLOW1:[0-9a-zA-Z_]+]]
@@ -37,7 +37,7 @@ for.body:                                         ; preds = %for.cond
 
 for.inc:                                          ; preds = %for.body
   %0 = add i32 %cond_a, %i.0
-  %arrayidx3 = getelementptr inbounds i32 addrspace(1)* %out, i32 %0
+  %arrayidx3 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %0
   store i32 %i.0, i32 addrspace(1)* %arrayidx3, align 4
   %inc = add i32 %i.0, 1
   br label %for.cond
diff --git a/test/Transforms/StructurizeCFG/nested-loop-order.ll b/test/Transforms/StructurizeCFG/nested-loop-order.ll
new file mode 100644
index 000000000000..fee1ff0433b5
--- /dev/null
+++ b/test/Transforms/StructurizeCFG/nested-loop-order.ll
@@ -0,0 +1,79 @@
+; RUN: opt -S -structurizecfg %s -o - | FileCheck %s
+
+define void @main(float addrspace(1)* %out) {
+
+; CHECK: main_body:
+; CHECK: br label %LOOP.outer
+main_body:
+  br label %LOOP.outer
+
+; CHECK: LOOP.outer:
+; CHECK: br label %LOOP
+LOOP.outer:                                       ; preds = %ENDIF28, %main_body
+  %temp8.0.ph = phi float [ 0.000000e+00, %main_body ], [ %tmp35, %ENDIF28 ]
+  %temp4.0.ph = phi i32 [ 0, %main_body ], [ %tmp20, %ENDIF28 ]
+  br label %LOOP
+
+; CHECK: LOOP:
+; br i1 %{{[0-9]+}}, label %ENDIF, label %Flow
+LOOP:                                             ; preds = %IF29, %LOOP.outer
+  %temp4.0 = phi i32 [ %temp4.0.ph, %LOOP.outer ], [ %tmp20, %IF29 ]
+  %tmp20 = add i32 %temp4.0, 1
+  %tmp22 = icmp sgt i32 %tmp20, 3
+  br i1 %tmp22, label %ENDLOOP, label %ENDIF
+
+; CHECK: Flow3
+; CHECK: br i1 %{{[0-9]+}}, label %ENDLOOP, label %LOOP.outer
+
+; CHECK: ENDLOOP:
+; CHECK: ret void
+ENDLOOP:                                          ; preds = %ENDIF28, %IF29, %LOOP
+  %temp8.1 = phi float [ %temp8.0.ph, %LOOP ], [ %temp8.0.ph, %IF29 ], [ %tmp35, %ENDIF28 ]
+  %tmp23 = icmp eq i32 %tmp20, 3
+  %.45 = select i1 %tmp23, float 0.000000e+00, float 1.000000e+00
+  store float %.45, float addrspace(1)* %out
+  ret void
+
+; CHECK: ENDIF:
+; CHECK: br i1 %tmp31, label %IF29, label %Flow1
+ENDIF:                                            ; preds = %LOOP
+  %tmp31 = icmp sgt i32 %tmp20, 1
+  br i1 %tmp31, label %IF29, label %ENDIF28
+
+; CHECK: Flow:
+; CHECK br i1 %{{[0-9]+}}, label %Flow, label %LOOP
+
+; CHECK: IF29:
+; CHECK: br label %Flow1
+IF29:                                             ; preds = %ENDIF
+  %tmp32 = icmp sgt i32 %tmp20, 2
+  br i1 %tmp32, label %ENDLOOP, label %LOOP
+
+; CHECK: Flow1:
+; CHECK: br label %Flow
+
+; CHECK: Flow2:
+; CHECK: br i1 %{{[0-9]+}}, label %ENDIF28, label %Flow3
+
+; CHECK: ENDIF28:
+; CHECK: br label %Flow3
+ENDIF28:                                          ; preds = %ENDIF
+  %tmp35 = fadd float %temp8.0.ph, 1.0
+  %tmp36 = icmp sgt i32 %tmp20, 2
+  br i1 %tmp36, label %ENDLOOP, label %LOOP.outer
+}
+
+; Function Attrs: nounwind readnone
+declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
+
+; Function Attrs: readnone
+declare float @llvm.AMDIL.clamp.(float, float, float) #2
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
+
+attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" }
+attributes #1 = { nounwind readnone }
+attributes #2 = { readnone }
+
+!0 = !{!1, !1, i64 0, i32 1}
+!1 = !{!"const", null}
diff --git a/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll b/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll
index 8ebd47aefd15..668a1e99d814 100644
--- a/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll
+++ b/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll
@@ -11,28 +11,29 @@ bb:
 bb3:                                              ; preds = %bb7, %bb
   %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb7 ]
   %tmp4 = fcmp ult float %arg1, 3.500000e+00
-; CHECK: br i1 %tmp4, label %bb7, label %Flow
+; CHECK: %0 = xor i1 %tmp4, true
+; CHECK: br i1 %0, label %bb5, label %Flow
   br i1 %tmp4, label %bb7, label %bb5
 
-; CHECK: Flow:
-; CHECK: br i1 %2, label %Flow1, label %bb3
-
-; CHECK: Flow1:
-; CHECK: br i1 %3, label %bb5, label %bb10
-
 ; CHECK: bb5:
 bb5:                                              ; preds = %bb3
   %tmp6 = fcmp olt float 0.000000e+00, %arg2
-; CHECK: br label %bb10
+; CHECK: br label %Flow
   br i1 %tmp6, label %bb10, label %bb7
 
+; CHECK: Flow:
+; CHECK: br i1 %3, label %bb7, label %Flow1
+
 ; CHECK: bb7
 bb7:                                              ; preds = %bb5, %bb3
   %tmp8 = add nuw nsw i64 %tmp, 1
   %tmp9 = icmp slt i64 %tmp8, 5
-; CHECK: br label %Flow
+; CHECK: br label %Flow1
   br i1 %tmp9, label %bb3, label %bb10
 
+; CHECK: Flow1:
+; CHECK: br i1 %7, label %bb10, label %bb3
+
 ; CHECK: bb10
 bb10:                                             ; preds = %bb7, %bb5
   %tmp11 = phi i32 [ 15, %bb5 ], [ 255, %bb7 ]
diff --git a/test/Transforms/StructurizeCFG/post-order-traversal-bug.ll b/test/Transforms/StructurizeCFG/post-order-traversal-bug.ll
new file mode 100644
index 000000000000..ba9aa2913061
--- /dev/null
+++ b/test/Transforms/StructurizeCFG/post-order-traversal-bug.ll
@@ -0,0 +1,100 @@
+; RUN: opt -S -structurizecfg %s -o - | FileCheck %s
+
+; The structurize cfg pass used to do a post-order traversal to generate a list
+; of ; basic blocks and then operate on the list in reverse.  This led to bugs,
+; because sometimes successors would be visited before their predecessors.
+; The fix for this was to do a reverse post-order traversal which is what the
+; algorithm requires.
+
+; Function Attrs: nounwind
+define void @test(float* nocapture %out, i32 %K1, float* nocapture readonly %nr) {
+
+; CHECK: entry:
+; CHECK: br label %for.body
+entry:
+  br label %for.body
+
+; CHECK: for.body:
+; CHECK: br i1 %{{[0-9]+}}, label %lor.lhs.false, label %Flow
+for.body:                                         ; preds = %for.body.backedge, %entry
+  %indvars.iv = phi i64 [ %indvars.iv.be, %for.body.backedge ], [ 1, %entry ]
+  %best_val.027 = phi float [ %best_val.027.be, %for.body.backedge ], [ 5.000000e+01, %entry ]
+  %prev_start.026 = phi i32 [ %tmp26, %for.body.backedge ], [ 0, %entry ]
+  %best_count.025 = phi i32 [ %best_count.025.be, %for.body.backedge ], [ 0, %entry ]
+  %tmp0 = trunc i64 %indvars.iv to i32
+  %cmp1 = icmp eq i32 %tmp0, %K1
+  br i1 %cmp1, label %if.then, label %lor.lhs.false
+
+; CHECK: lor.lhs.false:
+; CHECK: br label %Flow
+lor.lhs.false:                                    ; preds = %for.body
+  %arrayidx = getelementptr inbounds float, float* %nr, i64 %indvars.iv
+  %tmp1 = load float, float* %arrayidx, align 4
+  %tmp2 = add nsw i64 %indvars.iv, -1
+  %arrayidx2 = getelementptr inbounds float, float* %nr, i64 %tmp2
+  %tmp3 = load float, float* %arrayidx2, align 4
+  %cmp3 = fcmp une float %tmp1, %tmp3
+  br i1 %cmp3, label %if.then, label %for.body.1
+
+; CHECK: Flow:
+; CHECK: br i1 %{{[0-9]+}}, label %if.then, label %Flow1
+
+; CHECK: if.then:
+; CHECK: br label %Flow1
+if.then:                                          ; preds = %lor.lhs.false, %for.body
+  %sub4 = sub nsw i32 %tmp0, %prev_start.026
+  %tmp4 = add nsw i64 %indvars.iv, -1
+  %arrayidx8 = getelementptr inbounds float, float* %nr, i64 %tmp4
+  %tmp5 = load float, float* %arrayidx8, align 4
+  br i1 %cmp1, label %for.end, label %for.body.1
+
+; CHECK: for.end:
+; CHECK: ret void
+for.end:                                          ; preds = %for.body.1, %if.then
+  %best_val.0.lcssa = phi float [ %best_val.233, %for.body.1 ], [ %tmp5, %if.then ]
+  store float %best_val.0.lcssa, float* %out, align 4
+  ret void
+
+; CHECK: Flow1
+; CHECK: br i1 %{{[0-9]}}, label %for.body.1, label %Flow2
+
+; CHECK: for.body.1:
+; CHECK: br i1 %{{[0-9]+}}, label %for.body.6, label %Flow3
+for.body.1:                                       ; preds = %if.then, %lor.lhs.false
+  %best_val.233 = phi float [ %tmp5, %if.then ], [ %best_val.027, %lor.lhs.false ]
+  %best_count.231 = phi i32 [ %sub4, %if.then ], [ %best_count.025, %lor.lhs.false ]
+  %indvars.iv.next.454 = add nsw i64 %indvars.iv, 5
+  %tmp22 = trunc i64 %indvars.iv.next.454 to i32
+  %cmp1.5 = icmp eq i32 %tmp22, %K1
+  br i1 %cmp1.5, label %for.end, label %for.body.6
+
+; CHECK: Flow2:
+; CHECK: br i1 %{{[0-9]+}}, label %for.end, label %for.body
+
+; CHECK: for.body.6:
+; CHECK: br i1 %cmp5.6, label %if.then6.6, label %for.body.backedge
+for.body.6:                                       ; preds = %for.body.1
+  %indvars.iv.next.559 = add nsw i64 %indvars.iv, 6
+  %tmp26 = trunc i64 %indvars.iv.next.559 to i32
+  %sub4.6 = sub nsw i32 %tmp26, %tmp22
+  %cmp5.6 = icmp slt i32 %best_count.231, %sub4.6
+  br i1 %cmp5.6, label %if.then6.6, label %for.body.backedge
+
+; CHECK: if.then6.6
+; CHECK: br label %for.body.backedge
+if.then6.6:                                       ; preds = %for.body.6
+  %arrayidx8.6 = getelementptr inbounds float, float* %nr, i64 %indvars.iv.next.454
+  %tmp29 = load float, float* %arrayidx8.6, align 4
+  br label %for.body.backedge
+
+; CHECK: Flow3:
+; CHECK: br label %Flow2
+
+; CHECK: for.body.backedge:
+; CHECK: br label %Flow3
+for.body.backedge:                                ; preds = %if.then6.6, %for.body.6
+  %best_val.027.be = phi float [ %tmp29, %if.then6.6 ], [ %best_val.233, %for.body.6 ]
+  %best_count.025.be = phi i32 [ %sub4.6, %if.then6.6 ], [ %best_count.231, %for.body.6 ]
+  %indvars.iv.be = add nsw i64 %indvars.iv, 7
+  br label %for.body
+}
diff --git a/test/Transforms/TailCallElim/basic.ll b/test/Transforms/TailCallElim/basic.ll
index 8e9814b52bbc..2488b552d8f3 100644
--- a/test/Transforms/TailCallElim/basic.ll
+++ b/test/Transforms/TailCallElim/basic.ll
@@ -183,7 +183,7 @@ define void @test11() {
   %a = alloca i8*
   %b = alloca i8
   call void @test11_helper1(i8** %a, i8* %b)  ; a = &b
-  %c = load i8** %a
+  %c = load i8*, i8** %a
   call void @test11_helper2(i8* %c)
 ; CHECK: call void @test11_helper2
   ret void
diff --git a/test/Transforms/TailCallElim/dont_reorder_load.ll b/test/Transforms/TailCallElim/dont_reorder_load.ll
index a29b72e94239..ac399a1bf5a9 100644
--- a/test/Transforms/TailCallElim/dont_reorder_load.ll
+++ b/test/Transforms/TailCallElim/dont_reorder_load.ll
@@ -21,7 +21,7 @@ if:		; preds = %entry
 else:		; preds = %entry
 	%tmp7 = add i32 %start_arg, 1		; <i32> [#uses=1]
 	%tmp8 = call fastcc i32 @no_tailrecelim_1(i32* %a_arg, i32 %a_len_arg, i32 %tmp7)		; <i32> [#uses=1]
-	%tmp9 = load i32* @extern_weak_global		; <i32> [#uses=1]
+	%tmp9 = load i32, i32* @extern_weak_global		; <i32> [#uses=1]
 	%tmp10 = add i32 %tmp9, %tmp8		; <i32> [#uses=1]
 	ret i32 %tmp10
 }
@@ -40,7 +40,7 @@ if:		; preds = %entry
 else:		; preds = %entry
 	%tmp7 = add i32 %start_arg, 1		; <i32> [#uses=1]
 	%tmp8 = call fastcc i32 @no_tailrecelim_2(i32* %a_arg, i32 %a_len_arg, i32 %tmp7)		; <i32> [#uses=1]
-	%tmp9 = load i32* %a_arg		; <i32> [#uses=1]
+	%tmp9 = load i32, i32* %a_arg		; <i32> [#uses=1]
 	%tmp10 = add i32 %tmp9, %tmp8		; <i32> [#uses=1]
 	ret i32 %tmp10
 }
@@ -58,7 +58,7 @@ if:		; preds = %entry
 else:		; preds = %entry
 	%tmp7 = add i32 %start_arg, 1		; <i32> [#uses=1]
 	%tmp8 = call fastcc i32 @no_tailrecelim_3(i32* %a_arg, i32 %a_len_arg, i32 %tmp7)		; <i32> [#uses=1]
-	%tmp9 = load volatile i32* %a_arg		; <i32> [#uses=1]
+	%tmp9 = load volatile i32, i32* %a_arg		; <i32> [#uses=1]
 	%tmp10 = add i32 %tmp9, %tmp8		; <i32> [#uses=1]
 	ret i32 %tmp10
 }
diff --git a/test/Transforms/TailCallElim/inf-recursion.ll b/test/Transforms/TailCallElim/inf-recursion.ll
index 157226f93d3f..c121c25aee98 100644
--- a/test/Transforms/TailCallElim/inf-recursion.ll
+++ b/test/Transforms/TailCallElim/inf-recursion.ll
@@ -31,3 +31,24 @@ define float @fabsf(float %f) {
 }
 
 declare x86_fp80 @fabsl(x86_fp80 %f)
+
+; Don't crash while transforming a function with infinite recursion.
+define i32 @PR22704(i1 %bool) {
+entry:
+  br i1 %bool, label %t, label %f
+
+t:
+  %call1 = call i32 @PR22704(i1 1)
+  br label %return
+
+f:
+  %call = call i32 @PR22704(i1 1)
+  br label %return
+
+return:
+  ret i32 0
+
+; CHECK-LABEL: @PR22704(
+; CHECK:       %bool.tr = phi i1 [ %bool, %entry ], [ true, %t ], [ true, %f ]
+; CHECK:       br i1 %bool.tr, label %t, label %f
+}
diff --git a/test/Transforms/TailCallElim/reorder_load.ll b/test/Transforms/TailCallElim/reorder_load.ll
index 2e350d662a39..b989bbf9547a 100644
--- a/test/Transforms/TailCallElim/reorder_load.ll
+++ b/test/Transforms/TailCallElim/reorder_load.ll
@@ -16,7 +16,7 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 define fastcc i32 @raise_load_1(i32* %a_arg, i32 %a_len_arg, i32 %start_arg) nounwind readonly {
 ; CHECK-LABEL: @raise_load_1(
 ; CHECK-NOT: call
-; CHECK: load i32*
+; CHECK: load i32, i32*
 ; CHECK-NOT: call
 ; CHECK: }
 entry:
@@ -29,7 +29,7 @@ if:		; preds = %entry
 else:		; preds = %entry
 	%tmp7 = add i32 %start_arg, 1		; <i32> [#uses=1]
 	%tmp8 = call fastcc i32 @raise_load_1(i32* %a_arg, i32 %a_len_arg, i32 %tmp7)		; <i32> [#uses=1]
-	%tmp9 = load i32* %a_arg		; <i32> [#uses=1]
+	%tmp9 = load i32, i32* %a_arg		; <i32> [#uses=1]
 	%tmp10 = add i32 %tmp9, %tmp8		; <i32> [#uses=1]
 	ret i32 %tmp10
 }
@@ -40,7 +40,7 @@ else:		; preds = %entry
 define fastcc i32 @raise_load_2(i32* %a_arg, i32 %a_len_arg, i32 %start_arg) readonly {
 ; CHECK-LABEL: @raise_load_2(
 ; CHECK-NOT: call
-; CHECK: load i32*
+; CHECK: load i32, i32*
 ; CHECK-NOT: call
 ; CHECK: }
 entry:
@@ -60,7 +60,7 @@ unwind:		; preds = %else
 recurse:		; preds = %else
 	%tmp7 = add i32 %start_arg, 1		; <i32> [#uses=1]
 	%tmp8 = call fastcc i32 @raise_load_2(i32* %a_arg, i32 %a_len_arg, i32 %tmp7)		; <i32> [#uses=1]
-	%tmp9 = load i32* @global		; <i32> [#uses=1]
+	%tmp9 = load i32, i32* @global		; <i32> [#uses=1]
 	%tmp10 = add i32 %tmp9, %tmp8		; <i32> [#uses=1]
 	ret i32 %tmp10
 }
@@ -71,7 +71,7 @@ recurse:		; preds = %else
 define fastcc i32 @raise_load_3(i32* %a_arg, i32 %a_len_arg, i32 %start_arg) nounwind readonly {
 ; CHECK-LABEL: @raise_load_3(
 ; CHECK-NOT: call
-; CHECK: load i32*
+; CHECK: load i32, i32*
 ; CHECK-NOT: call
 ; CHECK: }
 entry:
@@ -84,7 +84,7 @@ if:		; preds = %entry
 else:		; preds = %entry
 	%tmp7 = add i32 %start_arg, 1		; <i32> [#uses=1]
 	%tmp8 = call fastcc i32 @raise_load_3(i32* %a_arg, i32 %a_len_arg, i32 %tmp7)		; <i32> [#uses=1]
-	%tmp9 = load i32* @extern_weak_global		; <i32> [#uses=1]
+	%tmp9 = load i32, i32* @extern_weak_global		; <i32> [#uses=1]
 	%tmp10 = add i32 %tmp9, %tmp8		; <i32> [#uses=1]
 	ret i32 %tmp10
 }
@@ -96,8 +96,8 @@ else:		; preds = %entry
 define fastcc i32 @raise_load_4(i32* %a_arg, i32 %a_len_arg, i32 %start_arg) readonly {
 ; CHECK-LABEL: @raise_load_4(
 ; CHECK-NOT: call
-; CHECK: load i32*
-; CHECK-NEXT: load i32*
+; CHECK: load i32, i32*
+; CHECK-NEXT: load i32, i32*
 ; CHECK-NOT: call
 ; CHECK: }
 entry:
@@ -116,9 +116,9 @@ unwind:		; preds = %else
 
 recurse:		; preds = %else
 	%tmp7 = add i32 %start_arg, 1		; <i32> [#uses=1]
-	%first = load i32* %a_arg		; <i32> [#uses=1]
+	%first = load i32, i32* %a_arg		; <i32> [#uses=1]
 	%tmp8 = call fastcc i32 @raise_load_4(i32* %a_arg, i32 %first, i32 %tmp7)		; <i32> [#uses=1]
-	%second = load i32* %a_arg		; <i32> [#uses=1]
+	%second = load i32, i32* %a_arg		; <i32> [#uses=1]
 	%tmp10 = add i32 %second, %tmp8		; <i32> [#uses=1]
 	ret i32 %tmp10
 }
diff --git a/test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll b/test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll
index 292186020f4f..4f7a3ca8ce6a 100644
--- a/test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll
+++ b/test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll
@@ -11,7 +11,7 @@ bb:		; preds = %entry
 	br label %bb9
 
 bb5:		; preds = %bb9
-	%tmp7 = call i32 (...)* @bar( i32 %x.0 ) nounwind 		; <i32> [#uses=1]
+	%tmp7 = call i32 (...) @bar( i32 %x.0 ) nounwind 		; <i32> [#uses=1]
 	br label %bb9
 
 bb9:		; preds = %bb5, %bb, %entry
diff --git a/test/Transforms/Util/lowerswitch.ll b/test/Transforms/Util/lowerswitch.ll
index 17c12028705f..6e21f916c038 100644
--- a/test/Transforms/Util/lowerswitch.ll
+++ b/test/Transforms/Util/lowerswitch.ll
@@ -3,7 +3,7 @@
 ; Test that we don't crash and have a different basic block for each incoming edge.
 define void @test0() {
 ; CHECK-LABEL: @test0
-; CHECK: %merge = phi i64 [ 1, %BB3 ], [ 0, %NewDefault ], [ 0, %NodeBlock5 ], [ 0, %LeafBlock1 ]
+; CHECK: %merge = phi i64 [ 1, %BB3 ], [ 0, %NewDefault ], [ 0, %NodeBlock.5 ], [ 0, %LeafBlock.1 ]
 BB1:
   switch i32 undef, label %BB2 [
     i32 3, label %BB2
@@ -43,12 +43,146 @@ bb2:
 
 bb3:
 ; CHECK-LABEL: bb3
-; CHECK: %tmp = phi i32 [ 1, %NodeBlock ], [ 0, %bb2 ], [ 1, %LeafBlock3 ]
+; CHECK: %tmp = phi i32 [ 1, %NodeBlock ], [ 0, %bb2 ], [ 1, %LeafBlock.3 ]
   %tmp = phi i32 [ 1, %bb1 ], [ 0, %bb2 ], [ 1, %bb1 ], [ 1, %bb1 ]
-; CHECK-NEXT: %tmp2 = phi i32 [ 2, %NodeBlock ], [ 5, %bb2 ], [ 2, %LeafBlock3 ]
+; CHECK-NEXT: %tmp2 = phi i32 [ 2, %NodeBlock ], [ 5, %bb2 ], [ 2, %LeafBlock.3 ]
   %tmp2 = phi i32 [ 2, %bb1 ], [ 2, %bb1 ], [ 5, %bb2 ], [ 2, %bb1 ]
   br label %exit
 
 exit:
   ret void
 }
+
+; Test that we don't crash.
+define void @test2(i32 %mode) {
+; CHECK-LABEL: @test2
+  br i1 undef, label %1, label %._crit_edge
+
+; <label>:1                                       ; preds = %0
+  switch i32 %mode, label %33 [
+    i32 2, label %2
+    i32 3, label %3
+    i32 4, label %4
+    i32 5, label %5
+    i32 6, label %6
+    i32 7, label %7
+    i32 8, label %8
+    i32 9, label %9
+    i32 10, label %10
+    i32 11, label %14
+    i32 12, label %18
+    i32 13, label %22
+    i32 14, label %26
+    i32 15, label %27
+    i32 16, label %34
+    i32 17, label %34
+    i32 18, label %34
+    i32 19, label %34
+    i32 22, label %34
+    i32 20, label %31
+    i32 21, label %32
+  ]
+
+; <label>:2                                       ; preds = %1
+  br label %34
+
+; <label>:3                                       ; preds = %1
+  br label %34
+
+; <label>:4                                       ; preds = %1
+  br label %34
+
+; <label>:5                                       ; preds = %1
+  br label %34
+
+; <label>:6                                       ; preds = %1
+  br label %34
+
+; <label>:7                                       ; preds = %1
+  br label %34
+
+; <label>:8                                       ; preds = %1
+  br label %34
+
+; <label>:9                                       ; preds = %1
+  br label %34
+
+; <label>:10                                      ; preds = %1
+  br i1 undef, label %11, label %12
+
+; <label>:11                                      ; preds = %10
+  br label %13
+
+; <label>:12                                      ; preds = %10
+  br label %13
+
+; <label>:13                                      ; preds = %12, %11
+  br label %34
+
+; <label>:14                                      ; preds = %1
+  br i1 undef, label %15, label %16
+
+; <label>:15                                      ; preds = %14
+  br label %17
+
+; <label>:16                                      ; preds = %14
+  br label %17
+
+; <label>:17                                      ; preds = %16, %15
+  br label %34
+
+; <label>:18                                      ; preds = %1
+  br i1 undef, label %19, label %20
+
+; <label>:19                                      ; preds = %18
+  br label %21
+
+; <label>:20                                      ; preds = %18
+  br label %21
+
+; <label>:21                                      ; preds = %20, %19
+  br label %34
+
+; <label>:22                                      ; preds = %1
+  br i1 undef, label %23, label %24
+
+; <label>:23                                      ; preds = %22
+  br label %25
+
+; <label>:24                                      ; preds = %22
+  br label %25
+
+; <label>:25                                      ; preds = %24, %23
+  br label %34
+
+; <label>:26                                      ; preds = %1
+  br label %34
+
+; <label>:27                                      ; preds = %1
+  br i1 undef, label %28, label %29
+
+; <label>:28                                      ; preds = %27
+  br label %30
+
+; <label>:29                                      ; preds = %27
+  br label %30
+
+; <label>:30                                      ; preds = %29, %28
+  br label %34
+
+; <label>:31                                      ; preds = %1
+  br label %34
+
+; <label>:32                                      ; preds = %1
+  br label %34
+
+; <label>:33                                      ; preds = %1
+  br label %34
+
+; <label>:34                                      ; preds = %33, %32, %31, %30, %26, %25, %21, %17, %13, %9, %8, %7, %6, %5, %4, %3, %2, %1, %1, %1, %1, %1
+  %o.0 = phi float [ undef, %33 ], [ undef, %32 ], [ undef, %31 ], [ undef, %30 ], [ undef, %26 ], [ undef, %25 ], [ undef, %21 ], [ undef, %17 ], [ undef, %13 ], [ undef, %9 ], [ undef, %8 ], [ undef, %7 ], [ undef, %6 ], [ undef, %5 ], [ undef, %4 ], [ undef, %3 ], [ undef, %2 ], [ undef, %1 ], [ undef, %1 ], [ undef, %1 ], [ undef, %1 ], [ undef, %1 ]
+  br label %._crit_edge
+
+._crit_edge:                                      ; preds = %34, %0
+  ret void
+}
diff --git a/test/Verifier/2002-11-05-GetelementptrPointers.ll b/test/Verifier/2002-11-05-GetelementptrPointers.ll
index 66b233ec63ae..2dccedacc314 100644
--- a/test/Verifier/2002-11-05-GetelementptrPointers.ll
+++ b/test/Verifier/2002-11-05-GetelementptrPointers.ll
@@ -5,6 +5,6 @@
 ; contained WITHIN a structure.
 
 define void @test({i32, i32*} * %X) {
-	getelementptr {i32, i32*} * %X, i32 0, i32 1, i32 0
+	getelementptr {i32, i32*}, {i32, i32*} * %X, i32 0, i32 1, i32 0
 	ret void
 }
diff --git a/test/Verifier/2006-10-15-AddrLabel.ll b/test/Verifier/2006-10-15-AddrLabel.ll
index decbf5ba42bb..bd2c40da14f5 100644
--- a/test/Verifier/2006-10-15-AddrLabel.ll
+++ b/test/Verifier/2006-10-15-AddrLabel.ll
@@ -5,6 +5,6 @@
 define i32 @main() {
          %foo  = call i8* %llvm.stacksave()
          %foop = bitcast i8* %foo to label*
-         %nret = load label* %foop
+         %nret = load label, label* %foop
          br label %nret
 }
diff --git a/test/Verifier/2008-01-11-VarargAttrs.ll b/test/Verifier/2008-01-11-VarargAttrs.ll
index b6ce6251cfc6..af97ce647449 100644
--- a/test/Verifier/2008-01-11-VarargAttrs.ll
+++ b/test/Verifier/2008-01-11-VarargAttrs.ll
@@ -5,6 +5,6 @@
 declare void @foo(...)
 
 define void @bar() {
-	call void (...)* @foo(%struct* sret null )
+	call void (...) @foo(%struct* sret null )
 	ret void
 }
diff --git a/test/Verifier/2008-03-01-AllocaSized.ll b/test/Verifier/2008-03-01-AllocaSized.ll
index fc12a96e4f9f..7478334959fe 100644
--- a/test/Verifier/2008-03-01-AllocaSized.ll
+++ b/test/Verifier/2008-03-01-AllocaSized.ll
@@ -1,5 +1,5 @@
 ; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s
-; CHECK: Cannot allocate unsized type
+; CHECK: invalid type for alloca
 ; PR2113
 
 define void @test() {
diff --git a/test/Verifier/2010-08-07-PointerIntrinsic.ll b/test/Verifier/2010-08-07-PointerIntrinsic.ll
index 427eb66aa7b6..0c0121ddbc81 100644
--- a/test/Verifier/2010-08-07-PointerIntrinsic.ll
+++ b/test/Verifier/2010-08-07-PointerIntrinsic.ll
@@ -8,10 +8,10 @@ target triple = "x86-unknown-unknown"
 @bb = global [16 x i8] zeroinitializer, align 1
 define void @x() nounwind {
 L.0:
-	%0 = getelementptr [32 x i8]* @aa, i32 0, i32 4
+	%0 = getelementptr [32 x i8], [32 x i8]* @aa, i32 0, i32 4
 	%1 = bitcast i8* %0 to [16 x i8]*
 	%2 = bitcast [16 x i8]* %1 to [0 x i8]*
-	%3 = getelementptr [16 x i8]* @bb
+	%3 = getelementptr [16 x i8], [16 x i8]* @bb
 	%4 = bitcast [16 x i8]* %3 to [0 x i8]*
 	call void @llvm.memcpy.i32([0 x i8]* %2, [0 x i8]* %4, i32 16, i32 1)
 	br label %return
diff --git a/test/Verifier/bitcast-address-space-through-constant-inttoptr-inside-gep-instruction.ll b/test/Verifier/bitcast-address-space-through-constant-inttoptr-inside-gep-instruction.ll
index ef38d37068ba..6e91164e0438 100644
--- a/test/Verifier/bitcast-address-space-through-constant-inttoptr-inside-gep-instruction.ll
+++ b/test/Verifier/bitcast-address-space-through-constant-inttoptr-inside-gep-instruction.ll
@@ -7,7 +7,7 @@ target datalayout = "e-p:32:32:32-p1:16:16:16-p2:8:8:8-i1:8:32-i8:8:32-i16:16:32
 ; Check that we can find inttoptr -> illegal bitcasts when hidden
 ; inside constantexpr pointer operands
 define i32 addrspace(2)* @illegal_bitcast_inttoptr_as_1_to_2_inside_gep() {
-  %cast = getelementptr i32 addrspace(2)* bitcast (i32 addrspace(1)* inttoptr (i32 1234 to i32 addrspace(1)*) to i32 addrspace(2)*), i32 3
+  %cast = getelementptr i32, i32 addrspace(2)* bitcast (i32 addrspace(1)* inttoptr (i32 1234 to i32 addrspace(1)*) to i32 addrspace(2)*), i32 3
   ret i32 addrspace(2)* %cast
 }
 
diff --git a/test/Verifier/bitcast-address-space-through-gep-2.ll b/test/Verifier/bitcast-address-space-through-gep-2.ll
index 2ee394206aef..026df524456a 100644
--- a/test/Verifier/bitcast-address-space-through-gep-2.ll
+++ b/test/Verifier/bitcast-address-space-through-gep-2.ll
@@ -13,7 +13,7 @@ target datalayout = "e-p:32:32:32-p1:16:16:16-p2:8:8:8-p3:8:8:8-i1:8:32-i8:8:32-
 @bitcast_after_gep_bitcast_gep =
          global %struct.Foo1 { i32 addrspace(1)* bitcast
                                     (i32 addrspace(3)* getelementptr
-                                         (i32 addrspace(3)* bitcast
+                                         (i32, i32 addrspace(3)* bitcast
                                               (i32 addrspace(2)* getelementptr
-                                                   ([32 x i32] addrspace(2)* @as2_array, i32 0, i32 8) to i32 addrspace(3)*), i32 3) to i32 addrspace(1)*) }
+                                                   ([32 x i32], [32 x i32] addrspace(2)* @as2_array, i32 0, i32 8) to i32 addrspace(3)*), i32 3) to i32 addrspace(1)*) }
 
diff --git a/test/Verifier/bitcast-address-space-through-gep.ll b/test/Verifier/bitcast-address-space-through-gep.ll
index 9494420841dc..3d3fb9f20001 100644
--- a/test/Verifier/bitcast-address-space-through-gep.ll
+++ b/test/Verifier/bitcast-address-space-through-gep.ll
@@ -10,6 +10,6 @@ target datalayout = "e-p:32:32:32-p1:16:16:16-p2:8:8:8-i1:8:32-i8:8:32-i16:16:32
 ; CHECK: error: invalid cast opcode for cast from 'i32 addrspace(2)*' to 'i32 addrspace(1)*'
 
 ; Make sure we still reject the bitcast after the value is accessed through a GEP
-@bitcast_after_gep = global %struct.Foo { i32 addrspace(1)* bitcast (i32 addrspace(2)* getelementptr ([32 x i32] addrspace(2)* @as2_array, i32 0, i32 8) to i32 addrspace(1)*) }
+@bitcast_after_gep = global %struct.Foo { i32 addrspace(1)* bitcast (i32 addrspace(2)* getelementptr ([32 x i32], [32 x i32] addrspace(2)* @as2_array, i32 0, i32 8) to i32 addrspace(1)*) }
 
 
diff --git a/test/Verifier/comdat3.ll b/test/Verifier/comdat3.ll
new file mode 100644
index 000000000000..28df930d9ddd
--- /dev/null
+++ b/test/Verifier/comdat3.ll
@@ -0,0 +1,5 @@
+; This used to be invalid, but now it's valid.  Ensure the verifier
+; doesn't reject it.
+; RUN: llvm-as %s -o /dev/null
+
+$v = comdat largest
diff --git a/test/Verifier/dbg-typerefs.ll b/test/Verifier/dbg-typerefs.ll
new file mode 100644
index 000000000000..dc50fce0715c
--- /dev/null
+++ b/test/Verifier/dbg-typerefs.ll
@@ -0,0 +1,32 @@
+; RUN: not llvm-as -disable-output <%s 2>&1 | FileCheck %s
+; Check that the debug info verifier gives nice errors for bad type refs
+; (rather than crashing).
+!llvm.module.flags = !{!0}
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+
+; Make a bunch of type references.  Note that !4 references !"0.bad" (instead
+; of !"4.bad") to test error ordering.
+!typerefs = !{!1, !2, !3, !4}
+!1 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !"1.good")
+!2 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !"2.bad")
+!3 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !"3.good")
+!4 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !"0.bad")
+
+; Add a minimal compile unit to resolve some of the type references.
+!llvm.dbg.cu = !{!5}
+!5 = !DICompileUnit(file: !6, language: DW_LANG_C99, retainedTypes: !7)
+!6 = !DIFile(filename: "file.c", directory: "/path/to/dir")
+!7 = !{!8, !9}
+!8 = !DICompositeType(tag: DW_TAG_structure_type, identifier: "1.good")
+!9 = !DICompositeType(tag: DW_TAG_structure_type, identifier: "3.good")
+
+; CHECK:      assembly parsed, but does not verify
+; CHECK-NEXT: unresolved type ref
+; CHECK-NEXT: !"0.bad"
+; CHECK-NEXT: !DIDerivedType(tag: DW_TAG_pointer_type
+; CHECK-SAME:                baseType: !"0.bad"
+; CHECK-NEXT: unresolved type ref
+; CHECK-NEXT: !"2.bad"
+; CHECK-NEXT: !DIDerivedType(tag: DW_TAG_pointer_type
+; CHECK-SAME:                baseType: !"2.bad"
+; CHECK-NOT:  unresolved
diff --git a/test/Verifier/dbg.ll b/test/Verifier/dbg.ll
new file mode 100644
index 000000000000..395806b1299a
--- /dev/null
+++ b/test/Verifier/dbg.ll
@@ -0,0 +1,18 @@
+; RUN: not llvm-as -disable-output <%s 2>&1 | FileCheck %s
+
+define void @foo() {
+entry:
+  br label %exit, !dbg !DILocation(scope: !DISubprogram(), inlinedAt: !{})
+; CHECK: inlined-at should be a location
+; CHECK-NEXT: !{{[0-9]+}} = !DILocation(line: 0, scope: !{{[0-9]+}}, inlinedAt: ![[IA:[0-9]+]])
+; CHECK-NEXT: ![[IA]] = !{}
+
+exit:
+  ret void, !dbg !{}
+; CHECK: invalid !dbg metadata attachment
+; CHECK-NEXT: ret void, !dbg ![[LOC:[0-9]+]]
+; CHECK-NEXT: ![[LOC]] = !{}
+}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 2, !"Debug Info Version", i32 3}
diff --git a/test/Verifier/frameallocate.ll b/test/Verifier/frameallocate.ll
deleted file mode 100644
index e3018db15275..000000000000
--- a/test/Verifier/frameallocate.ll
+++ /dev/null
@@ -1,48 +0,0 @@
-; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s
-
-declare i8* @llvm.frameallocate(i32)
-declare i8* @llvm.framerecover(i8*, i8*)
-
-define internal void @f() {
-  call i8* @llvm.frameallocate(i32 4)
-  call i8* @llvm.frameallocate(i32 4)
-  ret void
-}
-; CHECK: multiple calls to llvm.frameallocate in one function
-
-define internal void @f_a(i32 %n) {
-  call i8* @llvm.frameallocate(i32 %n)
-  ret void
-}
-; CHECK: llvm.frameallocate argument must be constant integer size
-
-define internal void @g() {
-entry:
-  br label %not_entry
-not_entry:
-  call i8* @llvm.frameallocate(i32 4)
-  ret void
-}
-; CHECK: llvm.frameallocate used outside of entry block
-
-define internal void @h() {
-  call i8* @llvm.framerecover(i8* null, i8* null)
-  ret void
-}
-; CHECK: llvm.framerecover first argument must be function defined in this module
-
-@global = constant i8 0
-
-declare void @declaration()
-
-define internal void @i() {
-  call i8* @llvm.framerecover(i8* @global, i8* null)
-  ret void
-}
-; CHECK: llvm.framerecover first argument must be function defined in this module
-
-define internal void @j() {
-  call i8* @llvm.framerecover(i8* bitcast(void()* @declaration to i8*), i8* null)
-  ret void
-}
-; CHECK: llvm.framerecover first argument must be function defined in this module
diff --git a/test/Verifier/frameescape.ll b/test/Verifier/frameescape.ll
new file mode 100644
index 000000000000..1fb9387eb2ff
--- /dev/null
+++ b/test/Verifier/frameescape.ll
@@ -0,0 +1,69 @@
+; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s
+
+declare void @llvm.frameescape(...)
+declare i8* @llvm.framerecover(i8*, i8*, i32)
+
+define internal void @f() {
+  %a = alloca i8
+  call void (...) @llvm.frameescape(i8* %a)
+  call void (...) @llvm.frameescape(i8* %a)
+  ret void
+}
+; CHECK: multiple calls to llvm.frameescape in one function
+
+define internal void @g() {
+entry:
+  %a = alloca i8
+  br label %not_entry
+not_entry:
+  call void (...) @llvm.frameescape(i8* %a)
+  ret void
+}
+; CHECK: llvm.frameescape used outside of entry block
+
+define internal void @h() {
+  call i8* @llvm.framerecover(i8* null, i8* null, i32 0)
+  ret void
+}
+; CHECK: llvm.framerecover first argument must be function defined in this module
+
+@global = constant i8 0
+
+declare void @declaration()
+
+define internal void @i() {
+  call i8* @llvm.framerecover(i8* @global, i8* null, i32 0)
+  ret void
+}
+; CHECK: llvm.framerecover first argument must be function defined in this module
+
+define internal void @j() {
+  call i8* @llvm.framerecover(i8* bitcast(void()* @declaration to i8*), i8* null, i32 0)
+  ret void
+}
+; CHECK: llvm.framerecover first argument must be function defined in this module
+
+define internal void @k(i32 %n) {
+  call i8* @llvm.framerecover(i8* bitcast(void()* @f to i8*), i8* null, i32 %n)
+  ret void
+}
+; CHECK: idx argument of llvm.framerecover must be a constant int
+
+define internal void @l(i8* %b) {
+  %a = alloca i8
+  call void (...) @llvm.frameescape(i8* %a, i8* %b)
+  ret void
+}
+; CHECK: llvm.frameescape only accepts static allocas
+
+define internal void @m() {
+  %a = alloca i8
+  call void (...) @llvm.frameescape(i8* %a)
+  ret void
+}
+
+define internal void @n(i8* %fp) {
+  call i8* @llvm.framerecover(i8* bitcast(void ()* @m to i8*), i8* %fp, i32 1)
+  ret void
+}
+; CHECK: all indices passed to llvm.framerecover must be less than the number of arguments passed ot llvm.frameescape in the parent function
diff --git a/test/Verifier/function-metadata-bad.ll b/test/Verifier/function-metadata-bad.ll
new file mode 100644
index 000000000000..9e7ba225408e
--- /dev/null
+++ b/test/Verifier/function-metadata-bad.ll
@@ -0,0 +1,35 @@
+; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s
+
+define i32 @bad1() !prof !0 {
+  ret i32 0
+}
+
+!0 = !{i32 123, i32 3}
+; CHECK: assembly parsed, but does not verify as correct!
+; CHECK-NEXT: expected string with name of the !prof annotation
+; CHECK-NEXT: !0 = !{i32 123, i32 3}
+
+define i32 @bad2() !prof !1 {
+  ret i32 0
+}
+
+!1 = !{!"function_entry_count"}
+; CHECK-NEXT: !prof annotations should have exactly 2 operands
+; CHECK-NEXT: !1 = !{!"function_entry_count"}
+
+
+define i32 @bad3() !prof !2 {
+  ret i32 0
+}
+
+!2 = !{!"some_other_count", i64 200}
+; CHECK-NEXT: first operand should be 'function_entry_count'
+; CHECK-NEXT: !2 = !{!"some_other_count", i64 200}
+
+define i32 @bad4() !prof !3 {
+  ret i32 0
+}
+
+!3 = !{!"function_entry_count", !"string"}
+; CHECK-NEXT: expected integer argument to function_entry_count
+; CHECK-NEXT: !3 = !{!"function_entry_count", !"string"}
diff --git a/test/Verifier/function-metadata-good.ll b/test/Verifier/function-metadata-good.ll
new file mode 100644
index 000000000000..3d73a1c06945
--- /dev/null
+++ b/test/Verifier/function-metadata-good.ll
@@ -0,0 +1,8 @@
+; RUN: llvm-as < %s -o /dev/null 2>&1
+
+; Function foo() is called 2,304 times at runtime.
+define i32 @foo() !prof !0 {
+  ret i32 0
+}
+
+!0 = !{!"function_entry_count", i32 2304}
diff --git a/test/Verifier/gc_relocate_addrspace.ll b/test/Verifier/gc_relocate_addrspace.ll
new file mode 100644
index 000000000000..ddc1b230a8c2
--- /dev/null
+++ b/test/Verifier/gc_relocate_addrspace.ll
@@ -0,0 +1,23 @@
+; RUN: not llvm-as -disable-output <%s 2>&1 | FileCheck %s
+; This is to verify that gc_relocate must return a pointer with the same
+; address space with the relocated value.
+
+; CHECK:       gc.relocate: relocating a pointer shouldn't change its address space
+; CHECK-NEXT:  %obj.relocated = call coldcc i8* @llvm.experimental.gc.relocate.p0i8(i32 %safepoint_token, i32 7, i32 7) ;
+
+declare void @foo()
+
+; Function Attrs: nounwind
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...) #0
+
+define void @test1(i64 addrspace(1)* %obj) gc "statepoint-example" {
+entry:
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0, i64 addrspace(1)* %obj)
+  %obj.relocated = call coldcc i8* @llvm.experimental.gc.relocate.p0i8(i32 %safepoint_token, i32 7, i32 7) ; (%obj, %obj)
+  ret void
+}
+
+; Function Attrs: nounwind
+declare i8* @llvm.experimental.gc.relocate.p0i8(i32, i32, i32) #0
+
+attributes #0 = { nounwind }
diff --git a/test/Verifier/gc_relocate_operand.ll b/test/Verifier/gc_relocate_operand.ll
new file mode 100644
index 000000000000..c28b8d870365
--- /dev/null
+++ b/test/Verifier/gc_relocate_operand.ll
@@ -0,0 +1,21 @@
+; RUN: not llvm-as -disable-output <%s 2>&1 | FileCheck %s
+; This is to verify that the relocated value by gc_relocate must be a pointer type.
+
+; CHECK: gc.relocate: relocated value must be a gc pointer
+
+declare void @foo()
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
+
+define void @test1(i64 %obj) gc "statepoint-example" {
+entry:
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0, i64 %obj)
+  %obj.relocated = call coldcc i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(i32 %safepoint_token, i32 7, i32 7) ; (%obj, %obj)
+  ret void
+}
+
+; Function Attrs: nounwind
+declare i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(i32, i32, i32) #0
+
+attributes #0 = { nounwind }
+
diff --git a/test/Verifier/gc_relocate_return.ll b/test/Verifier/gc_relocate_return.ll
new file mode 100644
index 000000000000..3957d4c0cec8
--- /dev/null
+++ b/test/Verifier/gc_relocate_return.ll
@@ -0,0 +1,22 @@
+; RUN: not llvm-as -disable-output <%s 2>&1 | FileCheck %s
+; This is to verify that gc_relocate must return a pointer type, which is defined
+; in intrinsics.td.
+
+; CHECK: Intrinsic has incorrect return type!
+
+declare void @foo()
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
+
+define void @test1(<2 x i32 addrspace(1)*> addrspace(1)* %obj) gc "statepoint-example" {
+entry:
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @foo, i32 0, i32 0, i32 0, i32 0, <2 x i32 addrspace(1)*> addrspace(1)* %obj)
+  %obj.relocated = call coldcc i8 @llvm.experimental.gc.relocate.i8(i32 %safepoint_token, i32 7, i32 7) ; (%obj, %obj)
+  ret void
+}
+
+; Function Attrs: nounwind
+declare i8 @llvm.experimental.gc.relocate.i8(i32, i32, i32) #0
+
+attributes #0 = { nounwind }
+
diff --git a/test/Verifier/ident-meta4.ll b/test/Verifier/ident-meta4.ll
new file mode 100644
index 000000000000..f44dbd540a1c
--- /dev/null
+++ b/test/Verifier/ident-meta4.ll
@@ -0,0 +1,9 @@
+; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s
+; Verify that llvm.ident is properly structured.
+; llvm.ident takes a list of metadata entries.
+; Each metadata entry can contain one string only.
+
+!llvm.ident = !{!0}
+!0 = !{null}
+; CHECK: assembly parsed, but does not verify as correct!
+; CHECK-NEXT: invalid value for llvm.ident metadata entry operand(the operand should be a string)
diff --git a/test/Verifier/inalloca-vararg.ll b/test/Verifier/inalloca-vararg.ll
index 5099fd19927e..428f89ec88f1 100755
--- a/test/Verifier/inalloca-vararg.ll
+++ b/test/Verifier/inalloca-vararg.ll
@@ -3,7 +3,7 @@
 declare void @h(i32, ...)
 define void @i() {
   %args = alloca inalloca i32
-  call void (i32, ...)* @h(i32 1, i32* inalloca %args, i32 3)
+  call void (i32, ...) @h(i32 1, i32* inalloca %args, i32 3)
 ; CHECK: inalloca isn't on the last argument!
   ret void
 }
diff --git a/test/Verifier/invalid-patchable-statepoint.ll b/test/Verifier/invalid-patchable-statepoint.ll
new file mode 100644
index 000000000000..4783fa57f8fa
--- /dev/null
+++ b/test/Verifier/invalid-patchable-statepoint.ll
@@ -0,0 +1,14 @@
+; RUN: not opt -verify 2>&1 < %s | FileCheck %s
+
+; CHECK: gc.statepoint must have null as call target if number of patchable bytes is non zero
+
+define i1 @invalid_patchable_statepoint() gc "statepoint-example" {
+entry:
+  %safepoint_token = tail call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 3, i1 ()* @func, i32 0, i32 0, i32 0, i32 0)
+  %call1 = call i1 @llvm.experimental.gc.result.i1(i32 %safepoint_token)
+  ret i1 %call1
+}
+
+declare i32 @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i32, ...)
+declare i1 @llvm.experimental.gc.result.i1(i32)
+declare i1 @func()
diff --git a/test/Verifier/invalid-statepoint.ll b/test/Verifier/invalid-statepoint.ll
new file mode 100644
index 000000000000..6c3525a16df5
--- /dev/null
+++ b/test/Verifier/invalid-statepoint.ll
@@ -0,0 +1,20 @@
+; RUN: not opt -verify 2>&1 < %s | FileCheck %s
+
+; CHECK: gc.statepoint: mismatch in number of call arguments 
+
+declare zeroext i1 @return0i1()
+
+; Function Attrs: nounwind
+declare i32 @llvm.experimental.gc.statepoint.p0f0i1f(i64, i32, i1 ()*, i32, i32, ...) #0
+
+; Function Attrs: nounwind
+declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32, i32, i32) #0
+
+define i32 addrspace(1)* @0(i32 addrspace(1)* %dparam) {
+  %a00 = load i32, i32 addrspace(1)* %dparam
+  %to0 = call i32 (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f0i1f(i64 0, i32 0, i1 ()* @return0i1, i32 9, i32 0, i2 0, i32 addrspace(1)* %dparam)
+  %relocate = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %to0, i32 2, i32 6)
+  ret i32 addrspace(1)* %relocate
+}
+
+attributes #0 = { nounwind }
\ No newline at end of file
diff --git a/test/Verifier/invalid-statepoint2.ll b/test/Verifier/invalid-statepoint2.ll
new file mode 100644
index 000000000000..c8b453c31e69
--- /dev/null
+++ b/test/Verifier/invalid-statepoint2.ll
@@ -0,0 +1,18 @@
+; RUN: not opt -S < %s -verify 2>&1 | FileCheck %s
+
+; CHECK: gc.statepoint: number of deoptimization arguments must be a constant integer
+
+declare void @use(...)
+declare i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(i32, i32, i32)
+declare i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32, i32, i32)
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
+declare i32 @"personality_function"()
+
+;; Basic usage
+define i64 addrspace(1)* @test1(i8 addrspace(1)* %arg, i32 %val) gc "statepoint-example" {
+entry:
+  %cast = bitcast i8 addrspace(1)* %arg to i64 addrspace(1)*
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* undef, i32 0, i32 0, i32 0, i32 %val, i32 0, i32 0, i32 0, i32 10, i32 0, i8 addrspace(1)* %arg, i64 addrspace(1)* %cast, i8 addrspace(1)* %arg, i8 addrspace(1)* %arg)
+  %reloc = call i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %safepoint_token, i32 12, i32 13)
+  ret i64 addrspace(1)* %reloc
+}
diff --git a/test/Verifier/llvm.dbg.declare-address.ll b/test/Verifier/llvm.dbg.declare-address.ll
new file mode 100644
index 000000000000..ba132ad53465
--- /dev/null
+++ b/test/Verifier/llvm.dbg.declare-address.ll
@@ -0,0 +1,17 @@
+; RUN: not llvm-as -disable-output <%s 2>&1 | FileCheck %s
+; CHECK: invalid llvm.dbg.declare intrinsic address/value
+; CHECK-NEXT: call void @llvm.dbg.declare({{.*}})
+; CHECK-NEXT: !""
+
+define void @foo(i32 %a) {
+entry:
+  %s = alloca i32
+  call void @llvm.dbg.declare(metadata !"", metadata !DILocalVariable(tag: DW_TAG_arg_variable, scope: !1), metadata !DIExpression()), !dbg !DILocation(scope: !1)
+  ret void
+}
+
+declare void @llvm.dbg.declare(metadata, metadata, metadata)
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !DISubprogram()
diff --git a/test/Verifier/llvm.dbg.declare-expression.ll b/test/Verifier/llvm.dbg.declare-expression.ll
new file mode 100644
index 000000000000..4c1bd65230a9
--- /dev/null
+++ b/test/Verifier/llvm.dbg.declare-expression.ll
@@ -0,0 +1,17 @@
+; RUN: not llvm-as -disable-output <%s 2>&1 | FileCheck %s
+; CHECK: invalid llvm.dbg.declare intrinsic expression
+; CHECK-NEXT: call void @llvm.dbg.declare({{.*}})
+; CHECK-NEXT: !""
+
+define void @foo(i32 %a) {
+entry:
+  %s = alloca i32
+  call void @llvm.dbg.declare(metadata i32* %s, metadata !DILocalVariable(tag: DW_TAG_arg_variable, scope: !1), metadata !"")
+  ret void
+}
+
+declare void @llvm.dbg.declare(metadata, metadata, metadata)
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !DISubprogram()
diff --git a/test/Verifier/llvm.dbg.declare-variable.ll b/test/Verifier/llvm.dbg.declare-variable.ll
new file mode 100644
index 000000000000..deef50fd717d
--- /dev/null
+++ b/test/Verifier/llvm.dbg.declare-variable.ll
@@ -0,0 +1,17 @@
+; RUN: not llvm-as -disable-output <%s 2>&1 | FileCheck %s
+; CHECK: invalid llvm.dbg.declare intrinsic variable
+; CHECK-NEXT: call void @llvm.dbg.declare({{.*}})
+; CHECK-NEXT: !""
+
+define void @foo(i32 %a) {
+entry:
+  %s = alloca i32
+  call void @llvm.dbg.declare(metadata i32* %s, metadata !"", metadata !DIExpression()), !dbg !DILocation(scope: !1)
+  ret void
+}
+
+declare void @llvm.dbg.declare(metadata, metadata, metadata)
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !DISubprogram()
diff --git a/test/Verifier/llvm.dbg.intrinsic-dbg-attachment.ll b/test/Verifier/llvm.dbg.intrinsic-dbg-attachment.ll
new file mode 100644
index 000000000000..717794b4274b
--- /dev/null
+++ b/test/Verifier/llvm.dbg.intrinsic-dbg-attachment.ll
@@ -0,0 +1,61 @@
+; RUN: not llvm-as -disable-output <%s 2>&1 | FileCheck %s
+define void @foo() {
+entry:
+  call void @llvm.dbg.value(
+      metadata i8* undef,
+      i64 0,
+      metadata !DILocalVariable(tag: DW_TAG_arg_variable, scope: !1),
+      metadata !DIExpression())
+; CHECK-LABEL: llvm.dbg.value intrinsic requires a !dbg attachment
+; CHECK-NEXT: call void @llvm.dbg.value({{.*}})
+; CHECK-NEXT: label %entry
+; CHECK-NEXT: void ()* @foo
+
+  call void @llvm.dbg.declare(
+      metadata i8* undef,
+      metadata !DILocalVariable(tag: DW_TAG_arg_variable, scope: !1),
+      metadata !DIExpression())
+; CHECK-LABEL: llvm.dbg.declare intrinsic requires a !dbg attachment
+; CHECK-NEXT: call void @llvm.dbg.declare({{.*}})
+; CHECK-NEXT: label %entry
+; CHECK-NEXT: void ()* @foo
+
+  call void @llvm.dbg.value(
+      metadata i8* undef,
+      i64 0,
+      metadata !DILocalVariable(tag: DW_TAG_arg_variable, scope: !1),
+      metadata !DIExpression()),
+    !dbg !DILocation(scope: !2)
+; CHECK-LABEL: mismatched subprogram between llvm.dbg.value variable and !dbg attachment
+; CHECK-NEXT: call void @llvm.dbg.value({{[^,]+, [^,]+}}, metadata ![[VAR:[0-9]+]], {{[^,]+}}), !dbg ![[LOC:[0-9]+]]
+; CHECK-NEXT: label %entry
+; CHECK-NEXT: void ()* @foo
+; CHECK-NEXT: ![[VAR]] = !DILocalVariable({{.*}}scope: ![[VARSP:[0-9]+]]
+; CHECK-NEXT: ![[VARSP]] = !DISubprogram(
+; CHECK-NEXT: ![[LOC]] = !DILocation({{.*}}scope: ![[LOCSP:[0-9]+]]
+; CHECK-NEXT: ![[LOCSP]] = !DISubprogram(
+
+  call void @llvm.dbg.declare(
+      metadata i8* undef,
+      metadata !DILocalVariable(tag: DW_TAG_arg_variable, scope: !1),
+      metadata !DIExpression()),
+    !dbg !DILocation(scope: !2)
+; CHECK-LABEL: mismatched subprogram between llvm.dbg.declare variable and !dbg attachment
+; CHECK-NEXT: call void @llvm.dbg.declare({{[^,]+}}, metadata ![[VAR:[0-9]+]], {{.*[^,]+}}), !dbg ![[LOC:[0-9]+]]
+; CHECK-NEXT: label %entry
+; CHECK-NEXT: void ()* @foo
+; CHECK-NEXT: ![[VAR]] = !DILocalVariable({{.*}}scope: ![[VARSP:[0-9]+]]
+; CHECK-NEXT: ![[VARSP]] = !DISubprogram(
+; CHECK-NEXT: ![[LOC]] = !DILocation({{.*}}scope: ![[LOCSP:[0-9]+]]
+; CHECK-NEXT: ![[LOCSP]] = !DISubprogram(
+
+  ret void
+}
+
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
+declare void @llvm.dbg.declare(metadata, metadata, metadata)
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !DISubprogram(name: "foo")
+!2 = !DISubprogram(name: "bar")
diff --git a/test/Verifier/llvm.dbg.value-expression.ll b/test/Verifier/llvm.dbg.value-expression.ll
new file mode 100644
index 000000000000..78a7c50f233d
--- /dev/null
+++ b/test/Verifier/llvm.dbg.value-expression.ll
@@ -0,0 +1,17 @@
+; RUN: not llvm-as -disable-output <%s 2>&1 | FileCheck %s
+; CHECK: invalid llvm.dbg.value intrinsic expression
+; CHECK-NEXT: call void @llvm.dbg.value({{.*}})
+; CHECK-NEXT: !""
+
+define void @foo(i32 %a) {
+entry:
+  %s = alloca i32
+  call void @llvm.dbg.value(metadata i32* %s, i64 0, metadata !DILocalVariable(tag: DW_TAG_arg_variable, scope: !1), metadata !""), !dbg !DILocation(scope: !1)
+  ret void
+}
+
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !DISubprogram()
diff --git a/test/Verifier/llvm.dbg.value-value.ll b/test/Verifier/llvm.dbg.value-value.ll
new file mode 100644
index 000000000000..1acb5f8132fa
--- /dev/null
+++ b/test/Verifier/llvm.dbg.value-value.ll
@@ -0,0 +1,17 @@
+; RUN: not llvm-as -disable-output <%s 2>&1 | FileCheck %s
+; CHECK: invalid llvm.dbg.value intrinsic address/value
+; CHECK-NEXT: call void @llvm.dbg.value({{.*}})
+; CHECK-NEXT: !""
+
+define void @foo(i32 %a) {
+entry:
+  %s = alloca i32
+  call void @llvm.dbg.value(metadata !"", i64 0, metadata !DILocalVariable(tag: DW_TAG_arg_variable, scope: !1), metadata !DIExpression()), !dbg !DILocation(scope: !1)
+  ret void
+}
+
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !DISubprogram()
diff --git a/test/Verifier/llvm.dbg.value-variable.ll b/test/Verifier/llvm.dbg.value-variable.ll
new file mode 100644
index 000000000000..66329f9fdaa7
--- /dev/null
+++ b/test/Verifier/llvm.dbg.value-variable.ll
@@ -0,0 +1,17 @@
+; RUN: not llvm-as -disable-output <%s 2>&1 | FileCheck %s
+; CHECK: invalid llvm.dbg.value intrinsic variable
+; CHECK-NEXT: call void @llvm.dbg.value({{.*}})
+; CHECK-NEXT: !""
+
+define void @foo(i32 %a) {
+entry:
+  %s = alloca i32
+  call void @llvm.dbg.value(metadata i32* %s, i64 0, metadata !"", metadata !DIExpression()), !dbg !DILocation(scope: !1)
+  ret void
+}
+
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !DISubprogram()
diff --git a/test/Verifier/mdcompositetype-templateparams-tuple.ll b/test/Verifier/mdcompositetype-templateparams-tuple.ll
new file mode 100644
index 000000000000..8de6fac50eae
--- /dev/null
+++ b/test/Verifier/mdcompositetype-templateparams-tuple.ll
@@ -0,0 +1,11 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK:      invalid template params
+; CHECK-NEXT: !2 = !DICompositeType(
+; CHECK-SAME:                       templateParams: !1
+; CHECK-NEXT: !1 = !DITemplateTypeParameter(
+
+!named = !{!0, !1, !2}
+!0 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!1 = !DITemplateTypeParameter(name: "T", type: !0)
+!2 = !DICompositeType(tag: DW_TAG_structure_type, name: "IntTy", size: 32, align: 32, templateParams: !1)
diff --git a/test/Verifier/mdcompositetype-templateparams.ll b/test/Verifier/mdcompositetype-templateparams.ll
new file mode 100644
index 000000000000..5d4bef2232fc
--- /dev/null
+++ b/test/Verifier/mdcompositetype-templateparams.ll
@@ -0,0 +1,12 @@
+; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s
+
+; CHECK:      invalid template parameter
+; CHECK-NEXT: !2 = !DICompositeType(
+; CHECK-SAME:                       templateParams: !1
+; CHECK-NEXT: !1 = !{!0}
+; CHECK-NEXT: !0 = !DIBasicType(
+
+!named = !{!0, !1, !2}
+!0 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!1 = !{!0}
+!2 = !DICompositeType(tag: DW_TAG_structure_type, name: "IntTy", size: 32, align: 32, templateParams: !1)
diff --git a/test/Verifier/memcpy.ll b/test/Verifier/memcpy.ll
new file mode 100644
index 000000000000..bd168cc953cc
--- /dev/null
+++ b/test/Verifier/memcpy.ll
@@ -0,0 +1,9 @@
+; RUN: not opt -verify < %s 2>&1 | FileCheck %s
+
+; CHECK: alignment argument of memory intrinsics must be a power of 2 
+
+define void @foo(i8* %P, i8* %Q) {
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %P, i8* %Q, i32 4, i32 3, i1 false)
+  ret void
+}
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
diff --git a/test/Verifier/module-flags-2.ll b/test/Verifier/module-flags-2.ll
new file mode 100644
index 000000000000..8582162eaf8b
--- /dev/null
+++ b/test/Verifier/module-flags-2.ll
@@ -0,0 +1,6 @@
+; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s
+
+!llvm.module.flags = !{!0}
+!0 = !{null, null, null}
+
+; CHECK: invalid behavior operand in module flag (expected constant integer)
diff --git a/test/Verifier/module-flags-3.ll b/test/Verifier/module-flags-3.ll
new file mode 100644
index 000000000000..64ab57ed786f
--- /dev/null
+++ b/test/Verifier/module-flags-3.ll
@@ -0,0 +1,6 @@
+; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, null, null}
+
+; CHECK: invalid ID operand in module flag (expected metadata string)
diff --git a/test/Verifier/musttail-invalid.ll b/test/Verifier/musttail-invalid.ll
index e5f9a404b9e3..78017db6e667 100644
--- a/test/Verifier/musttail-invalid.ll
+++ b/test/Verifier/musttail-invalid.ll
@@ -26,7 +26,7 @@ define void @mismatched_intty(i32) {
 declare void @mismatched_vararg_callee(i8*, ...)
 define void @mismatched_vararg(i8*) {
 ; CHECK: mismatched varargs
-  musttail call void (i8*, ...)* @mismatched_vararg_callee(i8* null)
+  musttail call void (i8*, ...) @mismatched_vararg_callee(i8* null)
   ret void
 }
 
diff --git a/test/Verifier/musttail-valid.ll b/test/Verifier/musttail-valid.ll
index bdc0c8cf7fd6..150e9491b750 100644
--- a/test/Verifier/musttail-valid.ll
+++ b/test/Verifier/musttail-valid.ll
@@ -17,13 +17,13 @@ define i32* @similar_ret_ptrty() {
 
 declare x86_thiscallcc void @varargs_thiscall(i8*, ...)
 define x86_thiscallcc void @varargs_thiscall_thunk(i8* %this, ...) {
-  musttail call x86_thiscallcc void (i8*, ...)* @varargs_thiscall(i8* %this, ...)
+  musttail call x86_thiscallcc void (i8*, ...) @varargs_thiscall(i8* %this, ...)
   ret void
 }
 
 declare x86_fastcallcc void @varargs_fastcall(i8*, ...)
 define x86_fastcallcc void @varargs_fastcall_thunk(i8* %this, ...) {
-  musttail call x86_fastcallcc void (i8*, ...)* @varargs_fastcall(i8* %this, ...)
+  musttail call x86_fastcallcc void (i8*, ...) @varargs_fastcall(i8* %this, ...)
   ret void
 }
 
@@ -32,7 +32,7 @@ define x86_thiscallcc void @varargs_thiscall_unreachable(i8* %this, ...) {
 }
 
 define x86_thiscallcc void @varargs_thiscall_ret_unreachable(i8* %this, ...) {
-  musttail call x86_thiscallcc void (i8*, ...)* @varargs_thiscall(i8* %this, ...)
+  musttail call x86_thiscallcc void (i8*, ...) @varargs_thiscall(i8* %this, ...)
   ret void
 bb1:
   ret void
diff --git a/test/Verifier/range-1.ll b/test/Verifier/range-1.ll
index fda65cbbbb89..170badc751a1 100644
--- a/test/Verifier/range-1.ll
+++ b/test/Verifier/range-1.ll
@@ -11,7 +11,7 @@ entry:
 
 define i8 @f2(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !1
+  %y = load i8, i8* %x, align 1, !range !1
   ret i8 %y
 }
 !1 = !{}
@@ -19,7 +19,7 @@ entry:
 
 define i8 @f3(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !2
+  %y = load i8, i8* %x, align 1, !range !2
   ret i8 %y
 }
 !2 = !{i8 0}
@@ -27,7 +27,7 @@ entry:
 
 define i8 @f4(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !3
+  %y = load i8, i8* %x, align 1, !range !3
   ret i8 %y
 }
 !3 = !{double 0.0, i8 0}
@@ -35,7 +35,7 @@ entry:
 
 define i8 @f5(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !4
+  %y = load i8, i8* %x, align 1, !range !4
   ret i8 %y
 }
 !4 = !{i8 0, double 0.0}
@@ -43,7 +43,7 @@ entry:
 
 define i8 @f6(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !5
+  %y = load i8, i8* %x, align 1, !range !5
   ret i8 %y
 }
 !5 = !{i32 0, i8 0}
@@ -52,7 +52,7 @@ entry:
 
 define i8 @f7(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !6
+  %y = load i8, i8* %x, align 1, !range !6
   ret i8 %y
 }
 !6 = !{i8 0, i32 0}
@@ -61,7 +61,7 @@ entry:
 
 define i8 @f8(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !7
+  %y = load i8, i8* %x, align 1, !range !7
   ret i8 %y
 }
 !7 = !{i32 0, i32 0}
@@ -70,7 +70,7 @@ entry:
 
 define i8 @f9(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !8
+  %y = load i8, i8* %x, align 1, !range !8
   ret i8 %y
 }
 !8 = !{i8 0, i8 0}
@@ -78,7 +78,7 @@ entry:
 
 define i8 @f10(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !9
+  %y = load i8, i8* %x, align 1, !range !9
   ret i8 %y
 }
 !9 = !{i8 0, i8 2, i8 1, i8 3}
@@ -86,7 +86,7 @@ entry:
 
 define i8 @f11(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !10
+  %y = load i8, i8* %x, align 1, !range !10
   ret i8 %y
 }
 !10 = !{i8 0, i8 2, i8 2, i8 3}
@@ -94,7 +94,7 @@ entry:
 
 define i8 @f12(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !11
+  %y = load i8, i8* %x, align 1, !range !11
   ret i8 %y
 }
 !11 = !{i8 1, i8 2, i8 -1, i8 0}
@@ -102,7 +102,7 @@ entry:
 
 define i8 @f13(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !12
+  %y = load i8, i8* %x, align 1, !range !12
   ret i8 %y
 }
 !12 = !{i8 1, i8 3, i8 5, i8 1}
@@ -110,7 +110,7 @@ entry:
 
 define i8 @f14(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !13
+  %y = load i8, i8* %x, align 1, !range !13
   ret i8 %y
 }
 !13 = !{i8 1, i8 3, i8 5, i8 2}
@@ -118,7 +118,7 @@ entry:
 
 define i8 @f15(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !14
+  %y = load i8, i8* %x, align 1, !range !14
   ret i8 %y
 }
 !14 = !{i8 10, i8 1, i8 12, i8 13}
@@ -126,7 +126,7 @@ entry:
 
 define i8 @f16(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !16
+  %y = load i8, i8* %x, align 1, !range !16
   ret i8 %y
 }
 !16 = !{i8 1, i8 3, i8 4, i8 5, i8 6, i8 2}
@@ -134,7 +134,7 @@ entry:
 
 define i8 @f17(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !17
+  %y = load i8, i8* %x, align 1, !range !17
   ret i8 %y
 }
 !17 = !{i8 1, i8 3, i8 4, i8 5, i8 6, i8 1}
diff --git a/test/Verifier/range-2.ll b/test/Verifier/range-2.ll
index f8891c83225e..b7c9a6e65e67 100644
--- a/test/Verifier/range-2.ll
+++ b/test/Verifier/range-2.ll
@@ -2,35 +2,35 @@
 
 define i8 @f1(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !0
+  %y = load i8, i8* %x, align 1, !range !0
   ret i8 %y
 }
 !0 = !{i8 0, i8 1}
 
 define i8 @f2(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !1
+  %y = load i8, i8* %x, align 1, !range !1
   ret i8 %y
 }
 !1 = !{i8 255, i8 1}
 
 define i8 @f3(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !2
+  %y = load i8, i8* %x, align 1, !range !2
   ret i8 %y
 }
 !2 = !{i8 1, i8 3, i8 5, i8 42}
 
 define i8 @f4(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !3
+  %y = load i8, i8* %x, align 1, !range !3
   ret i8 %y
 }
 !3 = !{i8 -1, i8 0, i8 1, i8 2}
 
 define i8 @f5(i8* %x) {
 entry:
-  %y = load i8* %x, align 1, !range !4
+  %y = load i8, i8* %x, align 1, !range !4
   ret i8 %y
 }
 !4 = !{i8 -1, i8 0, i8 1, i8 -2}
diff --git a/test/Verifier/recursive-struct-param.ll b/test/Verifier/recursive-struct-param.ll
new file mode 100644
index 000000000000..4b280a010f03
--- /dev/null
+++ b/test/Verifier/recursive-struct-param.ll
@@ -0,0 +1,15 @@
+; RUN: opt -verify < %s
+
+%struct.__sFILE = type { %struct.__sFILE }
+
+@.str = private unnamed_addr constant [13 x i8] c"Hello world\0A\00", align 1
+
+; Function Attrs: nounwind ssp
+define void @test(%struct.__sFILE* %stream, i8* %str) {
+  %fputs = call i32 @fputs(i8* %str, %struct.__sFILE* %stream)
+  ret void
+}
+
+; Function Attrs: nounwind
+declare i32 @fputs(i8* nocapture, %struct.__sFILE* nocapture)
+
diff --git a/test/Verifier/statepoint.ll b/test/Verifier/statepoint.ll
index 3fbaeb53f918..05a3eddcc3a0 100644
--- a/test/Verifier/statepoint.ll
+++ b/test/Verifier/statepoint.ll
@@ -1,25 +1,27 @@
 ; RUN: opt -S %s -verify | FileCheck %s
 
 declare void @use(...)
-declare i8 addrspace(1)* @llvm.gc.relocate.p1i8(i32, i32, i32)
-declare i32 @llvm.statepoint.p0f_isVoidf(void ()*, i32, i32, ...)
+declare i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(i32, i32, i32)
+declare i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32, i32, i32)
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
+declare i32 @"personality_function"()
 
 ;; Basic usage
-define i8 addrspace(1)* @test1(i8 addrspace(1)* %arg) {
+define i64 addrspace(1)* @test1(i8 addrspace(1)* %arg) gc "statepoint-example" {
 entry:
   %cast = bitcast i8 addrspace(1)* %arg to i64 addrspace(1)*
-  %safepoint_token = call i32 (void ()*, i32, i32, ...)* @llvm.statepoint.p0f_isVoidf(void ()* undef, i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 10, i32 0, i8 addrspace(1)* %arg, i64 addrspace(1)* %cast, i8 addrspace(1)* %arg, i8 addrspace(1)* %arg)
-  %reloc = call i8 addrspace(1)* @llvm.gc.relocate.p1i8(i32 %safepoint_token, i32 9, i32 10)
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* undef, i32 0, i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 10, i32 0, i8 addrspace(1)* %arg, i64 addrspace(1)* %cast, i8 addrspace(1)* %arg, i8 addrspace(1)* %arg)
+  %reloc = call i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %safepoint_token, i32 12, i32 13)
   ;; It is perfectly legal to relocate the same value multiple times...
-  %reloc2 = call i8 addrspace(1)* @llvm.gc.relocate.p1i8(i32 %safepoint_token, i32 9, i32 10)
-  %reloc3 = call i8 addrspace(1)* @llvm.gc.relocate.p1i8(i32 %safepoint_token, i32 10, i32 9)
-  ret i8 addrspace(1)* %reloc
+  %reloc2 = call i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %safepoint_token, i32 12, i32 13)
+  %reloc3 = call i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(i32 %safepoint_token, i32 13, i32 12)
+  ret i64 addrspace(1)* %reloc
 ; CHECK-LABEL: test1
 ; CHECK: statepoint
 ; CHECK: gc.relocate
 ; CHECK: gc.relocate
 ; CHECK: gc.relocate
-; CHECK: ret i8 addrspace(1)* %reloc
+; CHECK: ret i64 addrspace(1)* %reloc
 }
 
 ; This test catches two cases where the verifier was too strict:
@@ -27,7 +29,7 @@ entry:
 ; 2) A value can be replaced by one which is known equal.  This
 ; means a potentially derived pointer can be known base and that
 ; we can't check that derived pointer are never bases.
-define void @test2(i8 addrspace(1)* %arg, i64 addrspace(1)* %arg2) {
+define void @test2(i8 addrspace(1)* %arg, i64 addrspace(1)* %arg2) gc "statepoint-example" {
 entry:
   %cast = bitcast i8 addrspace(1)* %arg to i64 addrspace(1)*
   %c = icmp eq i64 addrspace(1)* %cast,  %arg2
@@ -37,9 +39,9 @@ notequal:
   ret void
 
 equal:
-%safepoint_token = call i32 (void ()*, i32, i32, ...)* @llvm.statepoint.p0f_isVoidf(void ()* undef, i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 10, i32 0, i8 addrspace(1)* %arg, i64 addrspace(1)* %cast, i8 addrspace(1)* %arg, i8 addrspace(1)* %arg)
-  %reloc = call i8 addrspace(1)* @llvm.gc.relocate.p1i8(i32 %safepoint_token, i32 9, i32 10)
-  call void undef(i8 addrspace(1)* %reloc)
+  %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* undef, i32 0, i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 10, i32 0, i8 addrspace(1)* %arg, i64 addrspace(1)* %cast, i8 addrspace(1)* %arg, i8 addrspace(1)* %arg)
+  %reloc = call i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(i32 %safepoint_token, i32 12, i32 13)
+  call void undef(i64 addrspace(1)* %reloc)
   ret void
 ; CHECK-LABEL: test2
 ; CHECK-LABEL: equal
@@ -48,3 +50,33 @@ equal:
 ; CHECK-NEXT: call
 ; CHECK-NEXT: ret voi
 }
+
+; Basic test for invoke statepoints
+define i8 addrspace(1)* @test3(i8 addrspace(1)* %obj, i8 addrspace(1)* %obj1) gc "statepoint-example" {
+; CHECK-LABEL: test3
+entry:
+  ; CHECK-LABEL: entry
+  ; CHECK: statepoint
+  %0 = invoke i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* undef, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i8 addrspace(1)* %obj, i8 addrspace(1)* %obj1)
+          to label %normal_dest unwind label %exceptional_return
+
+normal_dest:
+  ; CHECK-LABEL: normal_dest:
+  ; CHECK: gc.relocate
+  ; CHECK: gc.relocate
+  ; CHECK: ret
+  %obj.relocated = call coldcc i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(i32 %0, i32 12, i32 12)
+  %obj1.relocated = call coldcc i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(i32 %0, i32 12, i32 12)
+  ret i8 addrspace(1)* %obj.relocated
+
+exceptional_return:
+  ; CHECK-LABEL: exceptional_return
+  ; CHECK: gc.relocate
+  ; CHECK: gc.relocate
+  %landing_pad = landingpad { i8*, i32 } personality i32 ()* @"personality_function"
+          cleanup
+  %relocate_token = extractvalue { i8*, i32 } %landing_pad, 1
+  %obj.relocated1 = call coldcc i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(i32 %relocate_token, i32 12, i32 12)
+  %obj1.relocated1 = call coldcc i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(i32 %relocate_token, i32 12, i32 12)
+  ret i8 addrspace(1)* %obj1.relocated1
+}
diff --git a/test/Verifier/varargs-intrinsic.ll b/test/Verifier/varargs-intrinsic.ll
index 2fff1db7d0ce..26fe61fb058d 100644
--- a/test/Verifier/varargs-intrinsic.ll
+++ b/test/Verifier/varargs-intrinsic.ll
@@ -10,7 +10,7 @@ define void @foo1() {
 }
 
 define void @foo2() {
-  call void (...)* @llvm.donothing(i64 0, i64 1)
+  call void (...) @llvm.donothing(i64 0, i64 1)
 ; CHECK: Intrinsic was not defined with variable arguments!
   ret void
 }
diff --git a/test/YAMLParser/bool.data b/test/YAMLParser/bool.test
index e987a0ec1e32..e987a0ec1e32 100644
--- a/test/YAMLParser/bool.data
+++ b/test/YAMLParser/bool.test
diff --git a/test/YAMLParser/construct-bool.data b/test/YAMLParser/construct-bool.test
index 035ec0c85805..035ec0c85805 100644
--- a/test/YAMLParser/construct-bool.data
+++ b/test/YAMLParser/construct-bool.test
diff --git a/test/YAMLParser/construct-custom.data b/test/YAMLParser/construct-custom.test
index cac95e0a5fb7..cac95e0a5fb7 100644
--- a/test/YAMLParser/construct-custom.data
+++ b/test/YAMLParser/construct-custom.test
diff --git a/test/YAMLParser/construct-float.data b/test/YAMLParser/construct-float.test
index 07c51bdd833b..07c51bdd833b 100644
--- a/test/YAMLParser/construct-float.data
+++ b/test/YAMLParser/construct-float.test
diff --git a/test/YAMLParser/construct-int.data b/test/YAMLParser/construct-int.test
index b14c37f7880e..b14c37f7880e 100644
--- a/test/YAMLParser/construct-int.data
+++ b/test/YAMLParser/construct-int.test
diff --git a/test/YAMLParser/construct-map.data b/test/YAMLParser/construct-map.test
index 1b681206d177..1b681206d177 100644
--- a/test/YAMLParser/construct-map.data
+++ b/test/YAMLParser/construct-map.test
diff --git a/test/YAMLParser/construct-merge.data b/test/YAMLParser/construct-merge.test
index 0ebc9f612d5d..0ebc9f612d5d 100644
--- a/test/YAMLParser/construct-merge.data
+++ b/test/YAMLParser/construct-merge.test
diff --git a/test/YAMLParser/construct-null.data b/test/YAMLParser/construct-null.test
index 51f8b61e24ef..51f8b61e24ef 100644
--- a/test/YAMLParser/construct-null.data
+++ b/test/YAMLParser/construct-null.test
diff --git a/test/YAMLParser/construct-omap.data b/test/YAMLParser/construct-omap.test
index b96d6799c7d4..b96d6799c7d4 100644
--- a/test/YAMLParser/construct-omap.data
+++ b/test/YAMLParser/construct-omap.test
diff --git a/test/YAMLParser/construct-pairs.data b/test/YAMLParser/construct-pairs.test
index 40f288d1d741..40f288d1d741 100644
--- a/test/YAMLParser/construct-pairs.data
+++ b/test/YAMLParser/construct-pairs.test
diff --git a/test/YAMLParser/construct-seq.data b/test/YAMLParser/construct-seq.test
index f43fd39f8ed2..f43fd39f8ed2 100644
--- a/test/YAMLParser/construct-seq.data
+++ b/test/YAMLParser/construct-seq.test
diff --git a/test/YAMLParser/construct-set.data b/test/YAMLParser/construct-set.test
index 3e9d095e714e..3e9d095e714e 100644
--- a/test/YAMLParser/construct-set.data
+++ b/test/YAMLParser/construct-set.test
diff --git a/test/YAMLParser/construct-str-ascii.data b/test/YAMLParser/construct-str-ascii.test
index 24290ae8a99c..24290ae8a99c 100644
--- a/test/YAMLParser/construct-str-ascii.data
+++ b/test/YAMLParser/construct-str-ascii.test
diff --git a/test/YAMLParser/construct-str.data b/test/YAMLParser/construct-str.test
index dc1ce825cdc8..dc1ce825cdc8 100644
--- a/test/YAMLParser/construct-str.data
+++ b/test/YAMLParser/construct-str.test
diff --git a/test/YAMLParser/construct-timestamp.data b/test/YAMLParser/construct-timestamp.test
index f262c2d02c0d..f262c2d02c0d 100644
--- a/test/YAMLParser/construct-timestamp.data
+++ b/test/YAMLParser/construct-timestamp.test
diff --git a/test/YAMLParser/construct-value.data b/test/YAMLParser/construct-value.test
index fe01a0dc9049..fe01a0dc9049 100644
--- a/test/YAMLParser/construct-value.data
+++ b/test/YAMLParser/construct-value.test
diff --git a/test/YAMLParser/duplicate-key.former-loader-error.data b/test/YAMLParser/duplicate-key.former-loader-error.test
index 9272103fe657..9272103fe657 100644
--- a/test/YAMLParser/duplicate-key.former-loader-error.data
+++ b/test/YAMLParser/duplicate-key.former-loader-error.test
diff --git a/test/YAMLParser/duplicate-mapping-key.former-loader-error.data b/test/YAMLParser/duplicate-mapping-key.former-loader-error.test
index 96d175d2ac1a..96d175d2ac1a 100644
--- a/test/YAMLParser/duplicate-mapping-key.former-loader-error.data
+++ b/test/YAMLParser/duplicate-mapping-key.former-loader-error.test
diff --git a/test/YAMLParser/duplicate-merge-key.former-loader-error.data b/test/YAMLParser/duplicate-merge-key.former-loader-error.test
index 6b1276436ab1..6b1276436ab1 100644
--- a/test/YAMLParser/duplicate-merge-key.former-loader-error.data
+++ b/test/YAMLParser/duplicate-merge-key.former-loader-error.test
diff --git a/test/YAMLParser/duplicate-value-key.former-loader-error.data b/test/YAMLParser/duplicate-value-key.former-loader-error.test
index dc20e0b275c6..dc20e0b275c6 100644
--- a/test/YAMLParser/duplicate-value-key.former-loader-error.data
+++ b/test/YAMLParser/duplicate-value-key.former-loader-error.test
diff --git a/test/YAMLParser/emit-block-scalar-in-simple-key-context-bug.data b/test/YAMLParser/emit-block-scalar-in-simple-key-context-bug.test
index f5adedb1350f..f5adedb1350f 100644
--- a/test/YAMLParser/emit-block-scalar-in-simple-key-context-bug.data
+++ b/test/YAMLParser/emit-block-scalar-in-simple-key-context-bug.test
diff --git a/test/YAMLParser/empty-document-bug.data b/test/YAMLParser/empty-document-bug.test
index fa131fe78efe..fa131fe78efe 100644
--- a/test/YAMLParser/empty-document-bug.data
+++ b/test/YAMLParser/empty-document-bug.test
diff --git a/test/YAMLParser/float.data b/test/YAMLParser/float.test
index c4de97037c83..c4de97037c83 100644
--- a/test/YAMLParser/float.data
+++ b/test/YAMLParser/float.test
diff --git a/test/YAMLParser/int.data b/test/YAMLParser/int.test
index 2651d096ff60..2651d096ff60 100644
--- a/test/YAMLParser/int.data
+++ b/test/YAMLParser/int.test
diff --git a/test/YAMLParser/invalid-single-quote-bug.data b/test/YAMLParser/invalid-single-quote-bug.test
index 3722a003dfff..3722a003dfff 100644
--- a/test/YAMLParser/invalid-single-quote-bug.data
+++ b/test/YAMLParser/invalid-single-quote-bug.test
diff --git a/test/YAMLParser/merge.data b/test/YAMLParser/merge.test
index 86313596e198..86313596e198 100644
--- a/test/YAMLParser/merge.data
+++ b/test/YAMLParser/merge.test
diff --git a/test/YAMLParser/more-floats.data b/test/YAMLParser/more-floats.test
index 668b31cd13ae..668b31cd13ae 100644
--- a/test/YAMLParser/more-floats.data
+++ b/test/YAMLParser/more-floats.test
diff --git a/test/YAMLParser/negative-float-bug.data b/test/YAMLParser/negative-float-bug.test
index 0ba0ffee3010..0ba0ffee3010 100644
--- a/test/YAMLParser/negative-float-bug.data
+++ b/test/YAMLParser/negative-float-bug.test
diff --git a/test/YAMLParser/null.data b/test/YAMLParser/null.test
index a38d7fa6c522..a38d7fa6c522 100644
--- a/test/YAMLParser/null.data
+++ b/test/YAMLParser/null.test
diff --git a/test/YAMLParser/resolver.data b/test/YAMLParser/resolver.test
index 8cbba6328b68..8cbba6328b68 100644
--- a/test/YAMLParser/resolver.data
+++ b/test/YAMLParser/resolver.test
diff --git a/test/YAMLParser/run-parser-crash-bug.data b/test/YAMLParser/run-parser-crash-bug.test
index 3ec910ce0477..3ec910ce0477 100644
--- a/test/YAMLParser/run-parser-crash-bug.data
+++ b/test/YAMLParser/run-parser-crash-bug.test
diff --git a/test/YAMLParser/scan-document-end-bug.data b/test/YAMLParser/scan-document-end-bug.test
index 7354caf8cd8b..7354caf8cd8b 100644
--- a/test/YAMLParser/scan-document-end-bug.data
+++ b/test/YAMLParser/scan-document-end-bug.test
diff --git a/test/YAMLParser/scan-line-break-bug.data b/test/YAMLParser/scan-line-break-bug.test
index 792973d3f56c..792973d3f56c 100644
--- a/test/YAMLParser/scan-line-break-bug.data
+++ b/test/YAMLParser/scan-line-break-bug.test
diff --git a/test/YAMLParser/single-dot-is-not-float-bug.data b/test/YAMLParser/single-dot-is-not-float-bug.test
index 810a5936a894..810a5936a894 100644
--- a/test/YAMLParser/single-dot-is-not-float-bug.data
+++ b/test/YAMLParser/single-dot-is-not-float-bug.test
diff --git a/test/YAMLParser/sloppy-indentation.data b/test/YAMLParser/sloppy-indentation.test
index 2b2b62b14afa..2b2b62b14afa 100644
--- a/test/YAMLParser/sloppy-indentation.data
+++ b/test/YAMLParser/sloppy-indentation.test
diff --git a/test/YAMLParser/spec-02-01.data b/test/YAMLParser/spec-02-01.test
index dd15b2bc26a1..dd15b2bc26a1 100644
--- a/test/YAMLParser/spec-02-01.data
+++ b/test/YAMLParser/spec-02-01.test
diff --git a/test/YAMLParser/spec-02-02.data b/test/YAMLParser/spec-02-02.test
index a5695d5c27a5..a5695d5c27a5 100644
--- a/test/YAMLParser/spec-02-02.data
+++ b/test/YAMLParser/spec-02-02.test
diff --git a/test/YAMLParser/spec-02-03.data b/test/YAMLParser/spec-02-03.test
index 81f8d991f746..81f8d991f746 100644
--- a/test/YAMLParser/spec-02-03.data
+++ b/test/YAMLParser/spec-02-03.test
diff --git a/test/YAMLParser/spec-02-04.data b/test/YAMLParser/spec-02-04.test
index 44a218d5926b..44a218d5926b 100644
--- a/test/YAMLParser/spec-02-04.data
+++ b/test/YAMLParser/spec-02-04.test
diff --git a/test/YAMLParser/spec-02-05.data b/test/YAMLParser/spec-02-05.test
index c9a4a7572f7a..c9a4a7572f7a 100644
--- a/test/YAMLParser/spec-02-05.data
+++ b/test/YAMLParser/spec-02-05.test
diff --git a/test/YAMLParser/spec-02-06.data b/test/YAMLParser/spec-02-06.test
index 85c1e2bab8c4..85c1e2bab8c4 100644
--- a/test/YAMLParser/spec-02-06.data
+++ b/test/YAMLParser/spec-02-06.test
diff --git a/test/YAMLParser/spec-02-07.data b/test/YAMLParser/spec-02-07.test
index c349662a98ac..c349662a98ac 100644
--- a/test/YAMLParser/spec-02-07.data
+++ b/test/YAMLParser/spec-02-07.test
diff --git a/test/YAMLParser/spec-02-08.data b/test/YAMLParser/spec-02-08.test
index 9746a43788a5..9746a43788a5 100644
--- a/test/YAMLParser/spec-02-08.data
+++ b/test/YAMLParser/spec-02-08.test
diff --git a/test/YAMLParser/spec-02-09.data b/test/YAMLParser/spec-02-09.test
index 6aef9333799a..6aef9333799a 100644
--- a/test/YAMLParser/spec-02-09.data
+++ b/test/YAMLParser/spec-02-09.test
diff --git a/test/YAMLParser/spec-02-10.data b/test/YAMLParser/spec-02-10.test
index 0302fa750099..0302fa750099 100644
--- a/test/YAMLParser/spec-02-10.data
+++ b/test/YAMLParser/spec-02-10.test
diff --git a/test/YAMLParser/spec-02-11.data b/test/YAMLParser/spec-02-11.test
index d8cf863b2c1e..d8cf863b2c1e 100644
--- a/test/YAMLParser/spec-02-11.data
+++ b/test/YAMLParser/spec-02-11.test
diff --git a/test/YAMLParser/spec-02-12.data b/test/YAMLParser/spec-02-12.test
index 3b4d5370a939..3b4d5370a939 100644
--- a/test/YAMLParser/spec-02-12.data
+++ b/test/YAMLParser/spec-02-12.test
diff --git a/test/YAMLParser/spec-02-13.data b/test/YAMLParser/spec-02-13.test
index 2bbccbf5d7de..2bbccbf5d7de 100644
--- a/test/YAMLParser/spec-02-13.data
+++ b/test/YAMLParser/spec-02-13.test
diff --git a/test/YAMLParser/spec-02-14.data b/test/YAMLParser/spec-02-14.test
index 5a18ea213e6c..5a18ea213e6c 100644
--- a/test/YAMLParser/spec-02-14.data
+++ b/test/YAMLParser/spec-02-14.test
diff --git a/test/YAMLParser/spec-02-15.data b/test/YAMLParser/spec-02-15.test
index 2a7fbe96ad40..2a7fbe96ad40 100644
--- a/test/YAMLParser/spec-02-15.data
+++ b/test/YAMLParser/spec-02-15.test
diff --git a/test/YAMLParser/spec-02-16.data b/test/YAMLParser/spec-02-16.test
index 3a5792c76320..3a5792c76320 100644
--- a/test/YAMLParser/spec-02-16.data
+++ b/test/YAMLParser/spec-02-16.test
diff --git a/test/YAMLParser/spec-02-17.data b/test/YAMLParser/spec-02-17.test
index 2bcb60c8d933..2bcb60c8d933 100644
--- a/test/YAMLParser/spec-02-17.data
+++ b/test/YAMLParser/spec-02-17.test
diff --git a/test/YAMLParser/spec-02-18.data b/test/YAMLParser/spec-02-18.test
index 625a4962e997..625a4962e997 100644
--- a/test/YAMLParser/spec-02-18.data
+++ b/test/YAMLParser/spec-02-18.test
diff --git a/test/YAMLParser/spec-02-19.data b/test/YAMLParser/spec-02-19.test
index cb9df6dd1f43..cb9df6dd1f43 100644
--- a/test/YAMLParser/spec-02-19.data
+++ b/test/YAMLParser/spec-02-19.test
diff --git a/test/YAMLParser/spec-02-20.data b/test/YAMLParser/spec-02-20.test
index ed147986119d..ed147986119d 100644
--- a/test/YAMLParser/spec-02-20.data
+++ b/test/YAMLParser/spec-02-20.test
diff --git a/test/YAMLParser/spec-02-21.data b/test/YAMLParser/spec-02-21.test
index ea979db065b1..ea979db065b1 100644
--- a/test/YAMLParser/spec-02-21.data
+++ b/test/YAMLParser/spec-02-21.test
diff --git a/test/YAMLParser/spec-02-22.data b/test/YAMLParser/spec-02-22.test
index 77724f71066e..77724f71066e 100644
--- a/test/YAMLParser/spec-02-22.data
+++ b/test/YAMLParser/spec-02-22.test
diff --git a/test/YAMLParser/spec-02-23.data b/test/YAMLParser/spec-02-23.test
index d08dfa755c6b..d08dfa755c6b 100644
--- a/test/YAMLParser/spec-02-23.data
+++ b/test/YAMLParser/spec-02-23.test
diff --git a/test/YAMLParser/spec-02-24.data b/test/YAMLParser/spec-02-24.test
index 56b25cbbd80d..56b25cbbd80d 100644
--- a/test/YAMLParser/spec-02-24.data
+++ b/test/YAMLParser/spec-02-24.test
diff --git a/test/YAMLParser/spec-02-25.data b/test/YAMLParser/spec-02-25.test
index fbadfda97e36..fbadfda97e36 100644
--- a/test/YAMLParser/spec-02-25.data
+++ b/test/YAMLParser/spec-02-25.test
diff --git a/test/YAMLParser/spec-02-26.data b/test/YAMLParser/spec-02-26.test
index 257108e7e043..257108e7e043 100644
--- a/test/YAMLParser/spec-02-26.data
+++ b/test/YAMLParser/spec-02-26.test
diff --git a/test/YAMLParser/spec-02-27.data b/test/YAMLParser/spec-02-27.test
index a190ff19db0b..a190ff19db0b 100644
--- a/test/YAMLParser/spec-02-27.data
+++ b/test/YAMLParser/spec-02-27.test
diff --git a/test/YAMLParser/spec-02-28.data b/test/YAMLParser/spec-02-28.test
index 695c27f5d55a..695c27f5d55a 100644
--- a/test/YAMLParser/spec-02-28.data
+++ b/test/YAMLParser/spec-02-28.test
diff --git a/test/YAMLParser/spec-05-01-utf8.data b/test/YAMLParser/spec-05-01-utf8.test
index 349da06fab26..349da06fab26 100644
--- a/test/YAMLParser/spec-05-01-utf8.data
+++ b/test/YAMLParser/spec-05-01-utf8.test
diff --git a/test/YAMLParser/spec-05-02-utf8.data b/test/YAMLParser/spec-05-02-utf8.data
deleted file mode 100644
index 028f41bb557c..000000000000
--- a/test/YAMLParser/spec-05-02-utf8.data
+++ /dev/null
@@ -1,7 +0,0 @@
-# RUN: yaml-bench -canonical %s 2>&1 | FileCheck %s
-
-# Invalid use of BOM
-# inside a
-# document.
-
-# CHECK: error
diff --git a/test/YAMLParser/spec-05-02-utf8.test b/test/YAMLParser/spec-05-02-utf8.test
new file mode 100644
index 000000000000..3666f990e47f
--- /dev/null
+++ b/test/YAMLParser/spec-05-02-utf8.test
@@ -0,0 +1,7 @@
+# RUN: not yaml-bench -canonical %s 2>&1 | FileCheck %s
+
+# Invalid use of BOM
+# inside a
+# document.
+
+# CHECK: error
diff --git a/test/YAMLParser/spec-05-03.data b/test/YAMLParser/spec-05-03.test
index 461e98d2c2b8..461e98d2c2b8 100644
--- a/test/YAMLParser/spec-05-03.data
+++ b/test/YAMLParser/spec-05-03.test
diff --git a/test/YAMLParser/spec-05-04.data b/test/YAMLParser/spec-05-04.test
index 52850f435bf5..52850f435bf5 100644
--- a/test/YAMLParser/spec-05-04.data
+++ b/test/YAMLParser/spec-05-04.test
diff --git a/test/YAMLParser/spec-05-05.data b/test/YAMLParser/spec-05-05.test
index 499ee8ffb8ff..499ee8ffb8ff 100644
--- a/test/YAMLParser/spec-05-05.data
+++ b/test/YAMLParser/spec-05-05.test
diff --git a/test/YAMLParser/spec-05-06.data b/test/YAMLParser/spec-05-06.test
index 729141acf4b3..729141acf4b3 100644
--- a/test/YAMLParser/spec-05-06.data
+++ b/test/YAMLParser/spec-05-06.test
diff --git a/test/YAMLParser/spec-05-07.data b/test/YAMLParser/spec-05-07.test
index fc80a0d4152e..fc80a0d4152e 100644
--- a/test/YAMLParser/spec-05-07.data
+++ b/test/YAMLParser/spec-05-07.test
diff --git a/test/YAMLParser/spec-05-08.data b/test/YAMLParser/spec-05-08.test
index 9f2b7ece53fc..9f2b7ece53fc 100644
--- a/test/YAMLParser/spec-05-08.data
+++ b/test/YAMLParser/spec-05-08.test
diff --git a/test/YAMLParser/spec-05-09.data b/test/YAMLParser/spec-05-09.test
index fc061fb2982e..fc061fb2982e 100644
--- a/test/YAMLParser/spec-05-09.data
+++ b/test/YAMLParser/spec-05-09.test
diff --git a/test/YAMLParser/spec-05-10.data b/test/YAMLParser/spec-05-10.data
deleted file mode 100644
index bab2c1b89ca3..000000000000
--- a/test/YAMLParser/spec-05-10.data
+++ /dev/null
@@ -1,6 +0,0 @@
-# RUN: yaml-bench -canonical %s 2>&1 | FileCheck %s
-
-commercial-at: @text
-grave-accent: `text
-
-# CHECK: error
diff --git a/test/YAMLParser/spec-05-10.test b/test/YAMLParser/spec-05-10.test
new file mode 100644
index 000000000000..14112c1eed50
--- /dev/null
+++ b/test/YAMLParser/spec-05-10.test
@@ -0,0 +1,6 @@
+# RUN: not yaml-bench -canonical %s 2>&1 | FileCheck %s
+
+commercial-at: @text
+grave-accent: `text
+
+# CHECK: error
diff --git a/test/YAMLParser/spec-05-11.data b/test/YAMLParser/spec-05-11.test
index 7cba5562d5fb..7cba5562d5fb 100644
--- a/test/YAMLParser/spec-05-11.data
+++ b/test/YAMLParser/spec-05-11.test
diff --git a/test/YAMLParser/spec-05-12.data b/test/YAMLParser/spec-05-12.data
deleted file mode 100644
index eedfc08cf38a..000000000000
--- a/test/YAMLParser/spec-05-12.data
+++ /dev/null
@@ -1,16 +0,0 @@
-# RUN: yaml-bench -canonical %s 2>&1 | FileCheck %s
-#
-# We don't currently reject tabs as indentation.
-# XFAIL: *
-
-# Tabs do's and don'ts:
-# comment:
-quoted: "Quoted		"
-block: |
-  void main() {
-  	printf("Hello, world!\n");
-  }
-elsewhere:	# separation
-	indentation, in	plain scalar
-
-# CHECK: error
diff --git a/test/YAMLParser/spec-05-12.test b/test/YAMLParser/spec-05-12.test
new file mode 100644
index 000000000000..7ecc36dee8bf
--- /dev/null
+++ b/test/YAMLParser/spec-05-12.test
@@ -0,0 +1,18 @@
+# RUN: yaml-bench -canonical %s 2>&1 | FileCheck %s
+#
+# FIXME: This test should actually fail. Yaml-bench should report an error
+# that a tab is being used to indent a plain scalar at line 15.
+# We don't currently reject tabs as indentation.
+
+# Tabs do's and don'ts:
+# comment:
+quoted: "Quoted		"
+block: |
+  void main() {
+  	printf("Hello, world!\n");
+  }
+elsewhere:	# separation
+	indentation, in	plain scalar
+
+
+# CHECK: !!str "Quoted\t\t"
diff --git a/test/YAMLParser/spec-05-13.data b/test/YAMLParser/spec-05-13.test
index db62e866a755..db62e866a755 100644
--- a/test/YAMLParser/spec-05-13.data
+++ b/test/YAMLParser/spec-05-13.test
diff --git a/test/YAMLParser/spec-05-14.data b/test/YAMLParser/spec-05-14.test
index 65451651b69e..65451651b69e 100644
--- a/test/YAMLParser/spec-05-14.data
+++ b/test/YAMLParser/spec-05-14.test
diff --git a/test/YAMLParser/spec-05-15.data b/test/YAMLParser/spec-05-15.data
deleted file mode 100644
index 27dbd8396eaa..000000000000
--- a/test/YAMLParser/spec-05-15.data
+++ /dev/null
@@ -1,7 +0,0 @@
-# RUN: yaml-bench -canonical %s 2>&1 | FileCheck %s
-
-Bad escapes:
-  "\c
-  \xq-"
-
-# CHECK: error
diff --git a/test/YAMLParser/spec-05-15.test b/test/YAMLParser/spec-05-15.test
new file mode 100644
index 000000000000..46228bae215e
--- /dev/null
+++ b/test/YAMLParser/spec-05-15.test
@@ -0,0 +1,7 @@
+# RUN: not yaml-bench -canonical %s 2>&1 | FileCheck %s
+
+Bad escapes:
+  "\c
+  \xq-"
+
+# CHECK: error
diff --git a/test/YAMLParser/spec-06-01.data b/test/YAMLParser/spec-06-01.test
index 95b26bdb3856..95b26bdb3856 100644
--- a/test/YAMLParser/spec-06-01.data
+++ b/test/YAMLParser/spec-06-01.test
diff --git a/test/YAMLParser/spec-06-02.data b/test/YAMLParser/spec-06-02.test
index 40a15c9f3ea2..40a15c9f3ea2 100644
--- a/test/YAMLParser/spec-06-02.data
+++ b/test/YAMLParser/spec-06-02.test
diff --git a/test/YAMLParser/spec-06-03.data b/test/YAMLParser/spec-06-03.test
index c1893ef08324..c1893ef08324 100644
--- a/test/YAMLParser/spec-06-03.data
+++ b/test/YAMLParser/spec-06-03.test
diff --git a/test/YAMLParser/spec-06-04.data b/test/YAMLParser/spec-06-04.test
index b61bcc6b9551..b61bcc6b9551 100644
--- a/test/YAMLParser/spec-06-04.data
+++ b/test/YAMLParser/spec-06-04.test
diff --git a/test/YAMLParser/spec-06-05.data b/test/YAMLParser/spec-06-05.test
index 4bcaa5a81893..4bcaa5a81893 100644
--- a/test/YAMLParser/spec-06-05.data
+++ b/test/YAMLParser/spec-06-05.test
diff --git a/test/YAMLParser/spec-06-06.data b/test/YAMLParser/spec-06-06.test
index 67e39ddf8996..67e39ddf8996 100644
--- a/test/YAMLParser/spec-06-06.data
+++ b/test/YAMLParser/spec-06-06.test
diff --git a/test/YAMLParser/spec-06-07.data b/test/YAMLParser/spec-06-07.test
index 451bd349e3ef..451bd349e3ef 100644
--- a/test/YAMLParser/spec-06-07.data
+++ b/test/YAMLParser/spec-06-07.test
diff --git a/test/YAMLParser/spec-06-08.data b/test/YAMLParser/spec-06-08.test
index aa06f847ea36..aa06f847ea36 100644
--- a/test/YAMLParser/spec-06-08.data
+++ b/test/YAMLParser/spec-06-08.test
diff --git a/test/YAMLParser/spec-07-01.data b/test/YAMLParser/spec-07-01.test
index 21bc5e59d59c..21bc5e59d59c 100644
--- a/test/YAMLParser/spec-07-01.data
+++ b/test/YAMLParser/spec-07-01.test
diff --git a/test/YAMLParser/spec-07-02.data b/test/YAMLParser/spec-07-02.test
index bf0e758c880c..bf0e758c880c 100644
--- a/test/YAMLParser/spec-07-02.data
+++ b/test/YAMLParser/spec-07-02.test
diff --git a/test/YAMLParser/spec-07-03.data b/test/YAMLParser/spec-07-03.data
deleted file mode 100644
index c4a5299562a4..000000000000
--- a/test/YAMLParser/spec-07-03.data
+++ /dev/null
@@ -1,7 +0,0 @@
-# RUN: yaml-bench -canonical %s 2>&1 | FileCheck %s
-
-%YAML 1.1
-%YAML 1.1
-foo
-
-# CHECK: error
diff --git a/test/YAMLParser/spec-07-03.test b/test/YAMLParser/spec-07-03.test
new file mode 100644
index 000000000000..76266b896d7a
--- /dev/null
+++ b/test/YAMLParser/spec-07-03.test
@@ -0,0 +1,7 @@
+# RUN: not yaml-bench -canonical %s 2>&1 | FileCheck %s
+
+%YAML 1.1
+%YAML 1.1
+foo
+
+# CHECK: error
diff --git a/test/YAMLParser/spec-07-04.data b/test/YAMLParser/spec-07-04.test
index 2c8b2ec6959c..2c8b2ec6959c 100644
--- a/test/YAMLParser/spec-07-04.data
+++ b/test/YAMLParser/spec-07-04.test
diff --git a/test/YAMLParser/spec-07-05.data b/test/YAMLParser/spec-07-05.data
deleted file mode 100644
index f7cff3a8390c..000000000000
--- a/test/YAMLParser/spec-07-05.data
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: yaml-bench -canonical %s 2>&1 | FileCheck %s
-#
-# We don't currently parse TAG directives.
-# XFAIL: *
-
-%TAG ! !foo
-%TAG ! !foo
-bar
-
-# CHECK: error
diff --git a/test/YAMLParser/spec-07-05.test b/test/YAMLParser/spec-07-05.test
new file mode 100644
index 000000000000..447cba81902c
--- /dev/null
+++ b/test/YAMLParser/spec-07-05.test
@@ -0,0 +1,8 @@
+# RUN: not yaml-bench -canonical %s 2>&1 | FileCheck %s
+#
+# We don't currently parse TAG directives.
+# CHECK: error: Unexpected token
+
+%TAG ! !foo
+%TAG ! !foo
+bar
diff --git a/test/YAMLParser/spec-07-06.data b/test/YAMLParser/spec-07-06.test
index 9f27f91f3111..9f27f91f3111 100644
--- a/test/YAMLParser/spec-07-06.data
+++ b/test/YAMLParser/spec-07-06.test
diff --git a/test/YAMLParser/spec-07-07a.data b/test/YAMLParser/spec-07-07a.test
index e51f8f7d6947..e51f8f7d6947 100644
--- a/test/YAMLParser/spec-07-07a.data
+++ b/test/YAMLParser/spec-07-07a.test
diff --git a/test/YAMLParser/spec-07-07b.data b/test/YAMLParser/spec-07-07b.test
index 003d5755726b..003d5755726b 100644
--- a/test/YAMLParser/spec-07-07b.data
+++ b/test/YAMLParser/spec-07-07b.test
diff --git a/test/YAMLParser/spec-07-08.data b/test/YAMLParser/spec-07-08.test
index 7197404b3849..7197404b3849 100644
--- a/test/YAMLParser/spec-07-08.data
+++ b/test/YAMLParser/spec-07-08.test
diff --git a/test/YAMLParser/spec-07-09.data b/test/YAMLParser/spec-07-09.test
index 1f98ba041468..1f98ba041468 100644
--- a/test/YAMLParser/spec-07-09.data
+++ b/test/YAMLParser/spec-07-09.test
diff --git a/test/YAMLParser/spec-07-10.data b/test/YAMLParser/spec-07-10.test
index a1766834781a..a1766834781a 100644
--- a/test/YAMLParser/spec-07-10.data
+++ b/test/YAMLParser/spec-07-10.test
diff --git a/test/YAMLParser/spec-07-11.data b/test/YAMLParser/spec-07-11.test
index ce14b7ebe4dc..ce14b7ebe4dc 100644
--- a/test/YAMLParser/spec-07-11.data
+++ b/test/YAMLParser/spec-07-11.test
diff --git a/test/YAMLParser/spec-07-12a.data b/test/YAMLParser/spec-07-12a.test
index 7327f8188e0b..7327f8188e0b 100644
--- a/test/YAMLParser/spec-07-12a.data
+++ b/test/YAMLParser/spec-07-12a.test
diff --git a/test/YAMLParser/spec-07-12b.data b/test/YAMLParser/spec-07-12b.test
index d759abea7d44..d759abea7d44 100644
--- a/test/YAMLParser/spec-07-12b.data
+++ b/test/YAMLParser/spec-07-12b.test
diff --git a/test/YAMLParser/spec-07-13.data b/test/YAMLParser/spec-07-13.test
index ab74df101872..ab74df101872 100644
--- a/test/YAMLParser/spec-07-13.data
+++ b/test/YAMLParser/spec-07-13.test
diff --git a/test/YAMLParser/spec-08-01.data b/test/YAMLParser/spec-08-01.test
index 5abbfa809491..5abbfa809491 100644
--- a/test/YAMLParser/spec-08-01.data
+++ b/test/YAMLParser/spec-08-01.test
diff --git a/test/YAMLParser/spec-08-02.data b/test/YAMLParser/spec-08-02.test
index 8a75783a7095..8a75783a7095 100644
--- a/test/YAMLParser/spec-08-02.data
+++ b/test/YAMLParser/spec-08-02.test
diff --git a/test/YAMLParser/spec-08-03.data b/test/YAMLParser/spec-08-03.test
index 8c715305a810..8c715305a810 100644
--- a/test/YAMLParser/spec-08-03.data
+++ b/test/YAMLParser/spec-08-03.test
diff --git a/test/YAMLParser/spec-08-04.data b/test/YAMLParser/spec-08-04.data
deleted file mode 100644
index 73c493d76379..000000000000
--- a/test/YAMLParser/spec-08-04.data
+++ /dev/null
@@ -1,9 +0,0 @@
-# RUN: yaml-bench -canonical %s 2>&1 | FileCheck %s
-#
-# We don't currently look at the content of literal tags.
-# XFAIL: *
-
-- !<!> foo
-- !<$:?> bar
-
-# CHECK: error
diff --git a/test/YAMLParser/spec-08-04.test b/test/YAMLParser/spec-08-04.test
new file mode 100644
index 000000000000..5b502ae3a17f
--- /dev/null
+++ b/test/YAMLParser/spec-08-04.test
@@ -0,0 +1,7 @@
+# RUN: not yaml-bench -canonical %s 2>&1 | FileCheck %s
+#
+# We don't currently look at the content of literal tags.
+# CHECK: error: Unknown tag handle
+
+- !<!> foo
+- !<$:?> bar
diff --git a/test/YAMLParser/spec-08-05.data b/test/YAMLParser/spec-08-05.test
index 0613446c8974..0613446c8974 100644
--- a/test/YAMLParser/spec-08-05.data
+++ b/test/YAMLParser/spec-08-05.test
diff --git a/test/YAMLParser/spec-08-06.data b/test/YAMLParser/spec-08-06.data
deleted file mode 100644
index 9844f53a4ef3..000000000000
--- a/test/YAMLParser/spec-08-06.data
+++ /dev/null
@@ -1,12 +0,0 @@
-# RUN: yaml-bench -canonical %s 2>&1 | FileCheck %s
-#
-# We don't currently validate tags.
-# XFAIL: *
-
-%TAG !o! tag:ben-kiki.org,2000:
----
-- !$a!b foo
-- !o! bar
-- !h!type baz
-
-# CHECK: error
diff --git a/test/YAMLParser/spec-08-06.test b/test/YAMLParser/spec-08-06.test
new file mode 100644
index 000000000000..b457d59b569e
--- /dev/null
+++ b/test/YAMLParser/spec-08-06.test
@@ -0,0 +1,11 @@
+# RUN: not yaml-bench -canonical %s 2>&1 | FileCheck %s
+#
+# We don't currently validate tags.
+# CHECK: error: Unknown tag handle
+
+%TAG !o! tag:ben-kiki.org,2000:
+---
+- !$a!b foo
+- !o! bar
+- !h!type baz
+
diff --git a/test/YAMLParser/spec-08-07.data b/test/YAMLParser/spec-08-07.test
index fc3f2df7f058..fc3f2df7f058 100644
--- a/test/YAMLParser/spec-08-07.data
+++ b/test/YAMLParser/spec-08-07.test
diff --git a/test/YAMLParser/spec-08-08.data b/test/YAMLParser/spec-08-08.test
index 460029f6ace0..460029f6ace0 100644
--- a/test/YAMLParser/spec-08-08.data
+++ b/test/YAMLParser/spec-08-08.test
diff --git a/test/YAMLParser/spec-08-09.data b/test/YAMLParser/spec-08-09.test
index 1c8258594310..1c8258594310 100644
--- a/test/YAMLParser/spec-08-09.data
+++ b/test/YAMLParser/spec-08-09.test
diff --git a/test/YAMLParser/spec-08-10.data b/test/YAMLParser/spec-08-10.test
index 74054eb08832..74054eb08832 100644
--- a/test/YAMLParser/spec-08-10.data
+++ b/test/YAMLParser/spec-08-10.test
diff --git a/test/YAMLParser/spec-08-11.data b/test/YAMLParser/spec-08-11.test
index 8a75783a7095..8a75783a7095 100644
--- a/test/YAMLParser/spec-08-11.data
+++ b/test/YAMLParser/spec-08-11.test
diff --git a/test/YAMLParser/spec-08-12.data b/test/YAMLParser/spec-08-12.test
index 69e78b42d276..69e78b42d276 100644
--- a/test/YAMLParser/spec-08-12.data
+++ b/test/YAMLParser/spec-08-12.test
diff --git a/test/YAMLParser/spec-08-13.data b/test/YAMLParser/spec-08-13.test
index 931d56a0cfe7..931d56a0cfe7 100644
--- a/test/YAMLParser/spec-08-13.data
+++ b/test/YAMLParser/spec-08-13.test
diff --git a/test/YAMLParser/spec-08-14.data b/test/YAMLParser/spec-08-14.test
index 61c448351ae5..61c448351ae5 100644
--- a/test/YAMLParser/spec-08-14.data
+++ b/test/YAMLParser/spec-08-14.test
diff --git a/test/YAMLParser/spec-08-15.data b/test/YAMLParser/spec-08-15.test
index f21e84a43141..f21e84a43141 100644
--- a/test/YAMLParser/spec-08-15.data
+++ b/test/YAMLParser/spec-08-15.test
diff --git a/test/YAMLParser/spec-09-01.data b/test/YAMLParser/spec-09-01.test
index 8999b4961626..8999b4961626 100644
--- a/test/YAMLParser/spec-09-01.data
+++ b/test/YAMLParser/spec-09-01.test
diff --git a/test/YAMLParser/spec-09-02.data b/test/YAMLParser/spec-09-02.data
deleted file mode 100644
index 9d8a58ca33ae..000000000000
--- a/test/YAMLParser/spec-09-02.data
+++ /dev/null
@@ -1,14 +0,0 @@
-# RUN: yaml-bench -canonical %s 2>&1 | FileCheck %s
-#
-# Indent trimming is not yet implemented.
-# XFAIL: *
-
- "as space
- trimmed
-
- specific
-
- escaped	\
- none"
-
-# CHECK: !!str "as space trimmed\nspecific\nescaped\tnone"
diff --git a/test/YAMLParser/spec-09-02.test b/test/YAMLParser/spec-09-02.test
new file mode 100644
index 000000000000..3f8e49a8bd31
--- /dev/null
+++ b/test/YAMLParser/spec-09-02.test
@@ -0,0 +1,14 @@
+# RUN: yaml-bench -canonical %s 2>&1 | FileCheck %s
+
+ "as space
+ trimmed
+
+ specific
+
+ escaped	\
+ none"
+
+# FIXME: The string below should actually be
+#   "as space trimmed\nspecific\nescaped\tnone", but the parser currently has
+#   a bug when parsing multiline quoted strings.
+# CHECK: !!str "as space\n trimmed\n specific\n escaped\t none"
diff --git a/test/YAMLParser/spec-09-03.data b/test/YAMLParser/spec-09-03.test
index 3fb0d8b184ab..3fb0d8b184ab 100644
--- a/test/YAMLParser/spec-09-03.data
+++ b/test/YAMLParser/spec-09-03.test
diff --git a/test/YAMLParser/spec-09-04.data b/test/YAMLParser/spec-09-04.test
index 4178ec6befbd..4178ec6befbd 100644
--- a/test/YAMLParser/spec-09-04.data
+++ b/test/YAMLParser/spec-09-04.test
diff --git a/test/YAMLParser/spec-09-05.data b/test/YAMLParser/spec-09-05.test
index e482d5366235..e482d5366235 100644
--- a/test/YAMLParser/spec-09-05.data
+++ b/test/YAMLParser/spec-09-05.test
diff --git a/test/YAMLParser/spec-09-06.data b/test/YAMLParser/spec-09-06.test
index edc0cbba9004..edc0cbba9004 100644
--- a/test/YAMLParser/spec-09-06.data
+++ b/test/YAMLParser/spec-09-06.test
diff --git a/test/YAMLParser/spec-09-07.data b/test/YAMLParser/spec-09-07.test
index 3c010ca5b93b..3c010ca5b93b 100644
--- a/test/YAMLParser/spec-09-07.data
+++ b/test/YAMLParser/spec-09-07.test
diff --git a/test/YAMLParser/spec-09-08.data b/test/YAMLParser/spec-09-08.test
index d114e58fcac1..d114e58fcac1 100644
--- a/test/YAMLParser/spec-09-08.data
+++ b/test/YAMLParser/spec-09-08.test
diff --git a/test/YAMLParser/spec-09-09.data b/test/YAMLParser/spec-09-09.test
index 2fec1b536ef1..2fec1b536ef1 100644
--- a/test/YAMLParser/spec-09-09.data
+++ b/test/YAMLParser/spec-09-09.test
diff --git a/test/YAMLParser/spec-09-10.data b/test/YAMLParser/spec-09-10.test
index faabfb06b5ec..faabfb06b5ec 100644
--- a/test/YAMLParser/spec-09-10.data
+++ b/test/YAMLParser/spec-09-10.test
diff --git a/test/YAMLParser/spec-09-11.data b/test/YAMLParser/spec-09-11.test
index 3f487ad6b043..3f487ad6b043 100644
--- a/test/YAMLParser/spec-09-11.data
+++ b/test/YAMLParser/spec-09-11.test
diff --git a/test/YAMLParser/spec-09-12.data b/test/YAMLParser/spec-09-12.test
index d992c589cd69..d992c589cd69 100644
--- a/test/YAMLParser/spec-09-12.data
+++ b/test/YAMLParser/spec-09-12.test
diff --git a/test/YAMLParser/spec-09-13.data b/test/YAMLParser/spec-09-13.test
index d48f2d2c47ee..d48f2d2c47ee 100644
--- a/test/YAMLParser/spec-09-13.data
+++ b/test/YAMLParser/spec-09-13.test
diff --git a/test/YAMLParser/spec-09-14.data b/test/YAMLParser/spec-09-14.data
deleted file mode 100644
index a83fcd45e2c0..000000000000
--- a/test/YAMLParser/spec-09-14.data
+++ /dev/null
@@ -1,21 +0,0 @@
-# RUN: yaml-bench -canonical %s 2>&1 | FileCheck %s
-#
-# Not quite sure why this doesn't fail.
-# XFAIL: *
-
----
---- ||| : foo
-... >>>: bar
----
-[
----
-,
-... ,
-{
---- :
-... # Nested
-}
-]
-...
-
-# CHECK: error
diff --git a/test/YAMLParser/spec-09-14.test b/test/YAMLParser/spec-09-14.test
new file mode 100644
index 000000000000..5f028f920fcd
--- /dev/null
+++ b/test/YAMLParser/spec-09-14.test
@@ -0,0 +1,18 @@
+# RUN: not yaml-bench -canonical %s 2>&1 | FileCheck %s
+#
+# CHECK: error: Expected a line break after block scalar header
+
+---
+--- ||| : foo
+... >>>: bar
+---
+[
+---
+,
+... ,
+{
+--- :
+... # Nested
+}
+]
+...
diff --git a/test/YAMLParser/spec-09-15.data b/test/YAMLParser/spec-09-15.test
index 4111d1ba2cb1..4111d1ba2cb1 100644
--- a/test/YAMLParser/spec-09-15.data
+++ b/test/YAMLParser/spec-09-15.test
diff --git a/test/YAMLParser/spec-09-16.data b/test/YAMLParser/spec-09-16.test
index e595f47bece9..e595f47bece9 100644
--- a/test/YAMLParser/spec-09-16.data
+++ b/test/YAMLParser/spec-09-16.test
diff --git a/test/YAMLParser/spec-09-17.data b/test/YAMLParser/spec-09-17.test
index 1bacf4d68b1f..1bacf4d68b1f 100644
--- a/test/YAMLParser/spec-09-17.data
+++ b/test/YAMLParser/spec-09-17.test
diff --git a/test/YAMLParser/spec-09-18.data b/test/YAMLParser/spec-09-18.data
deleted file mode 100644
index ac623f9973f7..000000000000
--- a/test/YAMLParser/spec-09-18.data
+++ /dev/null
@@ -1,11 +0,0 @@
-# RUN: yaml-bench -canonical %s
-
-- | # Just the style
- literal
-- >1 # Indentation indicator
-  folded
-- |+ # Chomping indicator
- keep
-
-- >-1 # Both indicators
-  strip
diff --git a/test/YAMLParser/spec-09-18.test b/test/YAMLParser/spec-09-18.test
new file mode 100644
index 000000000000..cb05bb3774c5
--- /dev/null
+++ b/test/YAMLParser/spec-09-18.test
@@ -0,0 +1,15 @@
+# RUN: yaml-bench -canonical %s | FileCheck %s
+# CHECK: !!str "literal\n"
+# CHECK: !!str " folded\n"
+# CHECK: !!str "keep\n\n"
+# CHECK: !!str " strip"
+
+- | # Just the style
+ literal
+- >1 # Indentation indicator
+  folded
+- |+ # Chomping indicator
+ keep
+
+- >-1 # Both indicators
+  strip
diff --git a/test/YAMLParser/spec-09-19.data b/test/YAMLParser/spec-09-19.data
deleted file mode 100644
index 52aa157137b2..000000000000
--- a/test/YAMLParser/spec-09-19.data
+++ /dev/null
@@ -1,6 +0,0 @@
-# RUN: yaml-bench -canonical %s
-
-- |
- literal
-- >
- folded
diff --git a/test/YAMLParser/spec-09-19.test b/test/YAMLParser/spec-09-19.test
new file mode 100644
index 000000000000..f385717b0359
--- /dev/null
+++ b/test/YAMLParser/spec-09-19.test
@@ -0,0 +1,8 @@
+# RUN: yaml-bench -canonical %s | FileCheck %s
+# CHECK: !!str "literal\n"
+# CHECK: !!str "folded\n"
+
+- |
+ literal
+- >
+ folded
diff --git a/test/YAMLParser/spec-09-20.data b/test/YAMLParser/spec-09-20.data
deleted file mode 100644
index 86fc7ab9a2ed..000000000000
--- a/test/YAMLParser/spec-09-20.data
+++ /dev/null
@@ -1,13 +0,0 @@
-# RUN: yaml-bench -canonical %s
-
-- |
- detected
-- >
- 
-  
-  # detected
-- |1
-  explicit
-- >
- 	
- detected
diff --git a/test/YAMLParser/spec-09-20.test b/test/YAMLParser/spec-09-20.test
new file mode 100644
index 000000000000..47c255b85739
--- /dev/null
+++ b/test/YAMLParser/spec-09-20.test
@@ -0,0 +1,17 @@
+# RUN: yaml-bench -canonical %s | FileCheck %s
+# CHECK: !!str "detected\n"
+# CHECK: !!str "\n\n# detected\n"
+# CHECK: !!str " explicit\n"
+# CHECK: !!str "\t\ndetected\n"
+
+- |
+ detected
+- >
+ 
+  
+  # detected
+- |1
+  explicit
+- >
+ 	
+ detected
diff --git a/test/YAMLParser/spec-09-21.data b/test/YAMLParser/spec-09-21.data
deleted file mode 100644
index 6eb7917a97e3..000000000000
--- a/test/YAMLParser/spec-09-21.data
+++ /dev/null
@@ -1,12 +0,0 @@
-# RUN: yaml-bench -canonical %s 2>&1 | FileCheck %s
-
-- |
-
- text
-- >
-  text
- text
-- |1
- text
-
-# CHECK: error
diff --git a/test/YAMLParser/spec-09-21.test b/test/YAMLParser/spec-09-21.test
new file mode 100644
index 000000000000..661f986917af
--- /dev/null
+++ b/test/YAMLParser/spec-09-21.test
@@ -0,0 +1,12 @@
+# RUN: not yaml-bench -canonical %s 2>&1 | FileCheck %s
+
+- |
+
+ text
+- >
+  text
+ text
+- |1
+ text
+
+# CHECK: 8:2: error: A text line is less indented than the block scalar
diff --git a/test/YAMLParser/spec-09-22.data b/test/YAMLParser/spec-09-22.data
deleted file mode 100644
index b95faa50b5d0..000000000000
--- a/test/YAMLParser/spec-09-22.data
+++ /dev/null
@@ -1,6 +0,0 @@
-# RUN: yaml-bench -canonical %s
-
-strip: |-
-  text
clip: |
-  textÂ…keep: |+
-  text

diff --git a/test/YAMLParser/spec-09-22.test b/test/YAMLParser/spec-09-22.test
new file mode 100644
index 000000000000..726358dd5ba8
--- /dev/null
+++ b/test/YAMLParser/spec-09-22.test
@@ -0,0 +1,12 @@
+# RUN: yaml-bench -canonical %s | FileCheck %s
+# CHECK: !!str "text"
+# CHECK: !!str "text\n"
+# CHECK: !!str "text\n\n"
+
+strip: |-
+  text
+clip: |
+  text
+keep: |+
+  text
+
diff --git a/test/YAMLParser/spec-09-23.data b/test/YAMLParser/spec-09-23.test
index 94f839818b6c..94f839818b6c 100644
--- a/test/YAMLParser/spec-09-23.data
+++ b/test/YAMLParser/spec-09-23.test
diff --git a/test/YAMLParser/spec-09-24.data b/test/YAMLParser/spec-09-24.data
deleted file mode 100644
index f08eae6a80ea..000000000000
--- a/test/YAMLParser/spec-09-24.data
+++ /dev/null
@@ -1,8 +0,0 @@
-# RUN: yaml-bench -canonical %s
-
-strip: >-
-
-clip: >
-
-keep: |+
-
diff --git a/test/YAMLParser/spec-09-24.test b/test/YAMLParser/spec-09-24.test
new file mode 100644
index 000000000000..9cf514138550
--- /dev/null
+++ b/test/YAMLParser/spec-09-24.test
@@ -0,0 +1,13 @@
+# RUN: yaml-bench -canonical %s | FileCheck %s
+# CHECK: ? !!str "strip"
+# CHECK: : !!str ""
+# CHECK: ? !!str "clip"
+# CHECK: : !!str ""
+# CHECK: ? !!str "keep"
+# CHECK: : !!str "\n"
+
+strip: >-
+
+clip: >
+
+keep: |+
diff --git a/test/YAMLParser/spec-09-25.data b/test/YAMLParser/spec-09-25.data
deleted file mode 100644
index b15edb523d2f..000000000000
--- a/test/YAMLParser/spec-09-25.data
+++ /dev/null
@@ -1,5 +0,0 @@
-# RUN: yaml-bench -canonical %s
-
-| # Simple block scalar
- literal
- 	text
diff --git a/test/YAMLParser/spec-09-25.test b/test/YAMLParser/spec-09-25.test
new file mode 100644
index 000000000000..697b47e9ac7c
--- /dev/null
+++ b/test/YAMLParser/spec-09-25.test
@@ -0,0 +1,6 @@
+# RUN: yaml-bench -canonical %s | FileCheck %s
+# CHECK: !!str "literal\n\ttext\n"
+
+| # Simple block scalar
+ literal
+ 	text
diff --git a/test/YAMLParser/spec-09-26.data b/test/YAMLParser/spec-09-26.data
deleted file mode 100644
index 286740ed39cc..000000000000
--- a/test/YAMLParser/spec-09-26.data
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: yaml-bench -canonical %s
-
-|
- 
-  
-  literal
- 
-  text
-
- # Comment
diff --git a/test/YAMLParser/spec-09-26.test b/test/YAMLParser/spec-09-26.test
new file mode 100644
index 000000000000..c8f31aea2b3e
--- /dev/null
+++ b/test/YAMLParser/spec-09-26.test
@@ -0,0 +1,11 @@
+# RUN: yaml-bench -canonical %s | FileCheck %s
+# CHECK: !!str "\n\nliteral\n\ntext\n"
+
+|
+ 
+  
+  literal
+ 
+  text
+
+ # Comment
diff --git a/test/YAMLParser/spec-09-27.data b/test/YAMLParser/spec-09-27.data
deleted file mode 100644
index 286740ed39cc..000000000000
--- a/test/YAMLParser/spec-09-27.data
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: yaml-bench -canonical %s
-
-|
- 
-  
-  literal
- 
-  text
-
- # Comment
diff --git a/test/YAMLParser/spec-09-28.data b/test/YAMLParser/spec-09-28.data
deleted file mode 100644
index 286740ed39cc..000000000000
--- a/test/YAMLParser/spec-09-28.data
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: yaml-bench -canonical %s
-
-|
- 
-  
-  literal
- 
-  text
-
- # Comment
diff --git a/test/YAMLParser/spec-09-29.data b/test/YAMLParser/spec-09-29.test
index e8906ff64a15..e8906ff64a15 100644
--- a/test/YAMLParser/spec-09-29.data
+++ b/test/YAMLParser/spec-09-29.test
diff --git a/test/YAMLParser/spec-09-30.data b/test/YAMLParser/spec-09-30.test
index a2d8bf495043..a2d8bf495043 100644
--- a/test/YAMLParser/spec-09-30.data
+++ b/test/YAMLParser/spec-09-30.test
diff --git a/test/YAMLParser/spec-09-31.data b/test/YAMLParser/spec-09-31.test
index a2d8bf495043..a2d8bf495043 100644
--- a/test/YAMLParser/spec-09-31.data
+++ b/test/YAMLParser/spec-09-31.test
diff --git a/test/YAMLParser/spec-09-32.data b/test/YAMLParser/spec-09-32.test
index a2d8bf495043..a2d8bf495043 100644
--- a/test/YAMLParser/spec-09-32.data
+++ b/test/YAMLParser/spec-09-32.test
diff --git a/test/YAMLParser/spec-09-33.data b/test/YAMLParser/spec-09-33.test
index a2d8bf495043..a2d8bf495043 100644
--- a/test/YAMLParser/spec-09-33.data
+++ b/test/YAMLParser/spec-09-33.test
diff --git a/test/YAMLParser/spec-10-01.data b/test/YAMLParser/spec-10-01.test
index 549a54db42fd..549a54db42fd 100644
--- a/test/YAMLParser/spec-10-01.data
+++ b/test/YAMLParser/spec-10-01.test
diff --git a/test/YAMLParser/spec-10-02.data b/test/YAMLParser/spec-10-02.test
index 662427a0c066..662427a0c066 100644
--- a/test/YAMLParser/spec-10-02.data
+++ b/test/YAMLParser/spec-10-02.test
diff --git a/test/YAMLParser/spec-10-03.data b/test/YAMLParser/spec-10-03.test
index 43f300e40c35..43f300e40c35 100644
--- a/test/YAMLParser/spec-10-03.data
+++ b/test/YAMLParser/spec-10-03.test
diff --git a/test/YAMLParser/spec-10-04.data b/test/YAMLParser/spec-10-04.test
index 733a570efe8a..733a570efe8a 100644
--- a/test/YAMLParser/spec-10-04.data
+++ b/test/YAMLParser/spec-10-04.test
diff --git a/test/YAMLParser/spec-10-05.data b/test/YAMLParser/spec-10-05.test
index 3848b2a20060..3848b2a20060 100644
--- a/test/YAMLParser/spec-10-05.data
+++ b/test/YAMLParser/spec-10-05.test
diff --git a/test/YAMLParser/spec-10-06.data b/test/YAMLParser/spec-10-06.test
index 40efb2b916ca..40efb2b916ca 100644
--- a/test/YAMLParser/spec-10-06.data
+++ b/test/YAMLParser/spec-10-06.test
diff --git a/test/YAMLParser/spec-10-07.data b/test/YAMLParser/spec-10-07.test
index 7aa350e40bb5..7aa350e40bb5 100644
--- a/test/YAMLParser/spec-10-07.data
+++ b/test/YAMLParser/spec-10-07.test
diff --git a/test/YAMLParser/spec-10-08.data b/test/YAMLParser/spec-10-08.data
deleted file mode 100644
index 53faeb9e001b..000000000000
--- a/test/YAMLParser/spec-10-08.data
+++ /dev/null
@@ -1,13 +0,0 @@
-# RUN: yaml-bench -canonical %s 2>&1 | FileCheck %s
-#
-# This fails because even without a key token, some contexts (in this case flow
-# maps) allow implicit null keys, which mix with this in weird ways.
-# XFAIL: *
-
-{
-multi-line
- simple key : value,
-very long ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................(>1KB)................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... key: value
-}
-
-# CHECK: error
diff --git a/test/YAMLParser/spec-10-08.test b/test/YAMLParser/spec-10-08.test
new file mode 100644
index 000000000000..c4cb8e65ef29
--- /dev/null
+++ b/test/YAMLParser/spec-10-08.test
@@ -0,0 +1,13 @@
+# RUN: yaml-bench -canonical %s 2>&1 | FileCheck %s
+#
+# FIXME: This test should fail. Yaml bench should report an error that a simple
+# key spans across multiple lines and that another simple key is longer than
+# 1024 characters.
+
+{
+multi-line
+ simple key : value,
+very long ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................(>1KB)................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... key: value
+}
+
+# CHECK: ? !!str "very long
diff --git a/test/YAMLParser/spec-10-09.data b/test/YAMLParser/spec-10-09.test
index a6b1fd00dde3..a6b1fd00dde3 100644
--- a/test/YAMLParser/spec-10-09.data
+++ b/test/YAMLParser/spec-10-09.test
diff --git a/test/YAMLParser/spec-10-10.data b/test/YAMLParser/spec-10-10.test
index c97901ddfbe0..c97901ddfbe0 100644
--- a/test/YAMLParser/spec-10-10.data
+++ b/test/YAMLParser/spec-10-10.test
diff --git a/test/YAMLParser/spec-10-11.data b/test/YAMLParser/spec-10-11.test
index 51bd06f02025..51bd06f02025 100644
--- a/test/YAMLParser/spec-10-11.data
+++ b/test/YAMLParser/spec-10-11.test
diff --git a/test/YAMLParser/spec-10-12.data b/test/YAMLParser/spec-10-12.test
index 65a90b3f2c5a..65a90b3f2c5a 100644
--- a/test/YAMLParser/spec-10-12.data
+++ b/test/YAMLParser/spec-10-12.test
diff --git a/test/YAMLParser/spec-10-13.data b/test/YAMLParser/spec-10-13.test
index ccadeb1e7d5f..ccadeb1e7d5f 100644
--- a/test/YAMLParser/spec-10-13.data
+++ b/test/YAMLParser/spec-10-13.test
diff --git a/test/YAMLParser/spec-10-14.data b/test/YAMLParser/spec-10-14.test
index 866ec1f7b2c3..866ec1f7b2c3 100644
--- a/test/YAMLParser/spec-10-14.data
+++ b/test/YAMLParser/spec-10-14.test
diff --git a/test/YAMLParser/spec-10-15.data b/test/YAMLParser/spec-10-15.test
index 7d061bddd193..7d061bddd193 100644
--- a/test/YAMLParser/spec-10-15.data
+++ b/test/YAMLParser/spec-10-15.test
diff --git a/test/YAMLParser/str.data b/test/YAMLParser/str.test
index bf013b6f52c5..bf013b6f52c5 100644
--- a/test/YAMLParser/str.data
+++ b/test/YAMLParser/str.test
diff --git a/test/YAMLParser/timestamp-bugs.data b/test/YAMLParser/timestamp-bugs.test
index bf41a21b22d9..bf41a21b22d9 100644
--- a/test/YAMLParser/timestamp-bugs.data
+++ b/test/YAMLParser/timestamp-bugs.test
diff --git a/test/YAMLParser/timestamp.data b/test/YAMLParser/timestamp.test
index 79945451b54e..79945451b54e 100644
--- a/test/YAMLParser/timestamp.data
+++ b/test/YAMLParser/timestamp.test
diff --git a/test/YAMLParser/utf8-implicit.data b/test/YAMLParser/utf8-implicit.test
index ee2791fb062e..ee2791fb062e 100644
--- a/test/YAMLParser/utf8-implicit.data
+++ b/test/YAMLParser/utf8-implicit.test
diff --git a/test/YAMLParser/utf8.data b/test/YAMLParser/utf8.test
index 3935e9d12179..3935e9d12179 100644
--- a/test/YAMLParser/utf8.data
+++ b/test/YAMLParser/utf8.test
diff --git a/test/YAMLParser/value.data b/test/YAMLParser/value.test
index 311ccd4f22e9..311ccd4f22e9 100644
--- a/test/YAMLParser/value.data
+++ b/test/YAMLParser/value.test
diff --git a/test/YAMLParser/yaml.data b/test/YAMLParser/yaml.test
index 4f9b294f456b..4f9b294f456b 100644
--- a/test/YAMLParser/yaml.data
+++ b/test/YAMLParser/yaml.test
diff --git a/test/lit.cfg b/test/lit.cfg
index cd615b3c5736..c9b1320f9d71 100644
--- a/test/lit.cfg
+++ b/test/lit.cfg
@@ -41,7 +41,7 @@ config.test_format = lit.formats.ShTest(execute_external)
 
 # suffixes: A list of file extensions to treat as test files. This is overriden
 # by individual lit.local.cfg files in the test subdirectories.
-config.suffixes = ['.ll', '.c', '.cpp', '.test', '.txt', '.s']
+config.suffixes = ['.ll', '.c', '.cxx', '.test', '.txt', '.s']
 
 # excludes: A list of directories to exclude from the testsuite. The 'Inputs'
 # subdirectories contain auxiliary inputs for various tests in their parent
@@ -176,7 +176,7 @@ lli = 'lli'
 # we don't support COFF in MCJIT well enough for the tests, force ELF format on
 # Windows.  FIXME: the process target triple should be used here, but this is
 # difficult to obtain on Windows.
-if re.search(r'cygwin|mingw32|windows-gnu|win32', config.host_triple):
+if re.search(r'cygwin|mingw32|windows-gnu|windows-msvc|win32', config.host_triple):
   lli += ' -mtriple='+config.host_triple+'-elf'
 config.substitutions.append( ('%lli', lli ) )
 
@@ -187,6 +187,8 @@ if re.search(r'win32', config.target_triple):
 config.substitutions.append( ('%llc_dwarf', llc_dwarf) )
 
 # Add site-specific substitutions.
+config.substitutions.append( ('%gold', config.gold_executable) )
+config.substitutions.append( ('%ld64', config.ld64_executable) )
 config.substitutions.append( ('%go', config.go_executable) )
 config.substitutions.append( ('%llvmshlibdir', config.llvm_shlib_dir) )
 config.substitutions.append( ('%shlibext', config.llvm_shlib_ext) )
@@ -227,6 +229,7 @@ for pattern in [r"\bbugpoint\b(?!-)",
                 r"\bllvm-bcanalyzer\b",
                 r"\bllvm-config\b",
                 r"\bllvm-cov\b",
+                r"\bllvm-cxxdump\b",
                 r"\bllvm-diff\b",
                 r"\bllvm-dis\b",
                 r"\bllvm-dsymutil\b",
@@ -245,13 +248,13 @@ for pattern in [r"\bbugpoint\b(?!-)",
                 r"\bllvm-rtdyld\b",
                 r"\bllvm-size\b",
                 r"\bllvm-tblgen\b",
-                r"\bllvm-vtabledump\b",
                 r"\bllvm-c-test\b",
                 r"\bmacho-dump\b",
                 NOJUNK + r"\bopt\b",
                 r"\bFileCheck\b",
                 r"\bobj2yaml\b",
                 r"\byaml2obj\b",
+                r"\byaml-bench\b",
                 r"\bverify-uselistorder\b",
                 # Handle these specially as they are strings searched
                 # for during testing.
@@ -265,11 +268,19 @@ for pattern in [r"\bbugpoint\b(?!-)",
                           pattern)
     tool_pipe = tool_match.group(2)
     tool_name = tool_match.group(4)
-    tool_path = lit.util.which(tool_name, llvm_tools_dir)
-    if not tool_path:
+    # Did the user specify the tool path + arguments? This allows things like
+    # llvm-lit "-Dllc=llc -enable-misched -verify-machineinstrs"
+    tool_path = lit_config.params.get(tool_name)
+    if tool_path is None:
+        tool_path = lit.util.which(tool_name, llvm_tools_dir)
+    if tool_path is None:
         # Warn, but still provide a substitution.
         lit_config.note('Did not find ' + tool_name + ' in ' + llvm_tools_dir)
         tool_path = llvm_tools_dir + '/' + tool_name
+    if (tool_name == "llc" and
+       'LLVM_ENABLE_MACHINE_VERIFIER' in os.environ and
+       os.environ['LLVM_ENABLE_MACHINE_VERIFIER'] == "1"):
+        tool_path += " -verify-machineinstrs"
     config.substitutions.append((pattern, tool_pipe + tool_path))
 
 ### Targets
@@ -307,6 +318,10 @@ if config.llvm_use_sanitizer == "Undefined":
 else:
     config.available_features.add("not_ubsan")
 
+# Check if we should run long running tests.
+if lit_config.params.get("run_long_tests", None) == "true":
+    config.available_features.add("long_tests")
+
 # Direct object generation
 # Suppress x86_64-mingw32 while investigating since r219108.
 if not 'hexagon' in config.target_triple and not re.match(r'^x86_64.*-(mingw32|windows-gnu|win32)', config.target_triple):
@@ -329,7 +344,7 @@ def have_ld_plugin_support():
     if not os.path.exists(os.path.join(config.llvm_shlib_dir, 'LLVMgold.so')):
         return False
 
-    ld_cmd = subprocess.Popen(['ld', '--help'], stdout = subprocess.PIPE)
+    ld_cmd = subprocess.Popen([config.gold_executable, '--help'], stdout = subprocess.PIPE)
     ld_out = ld_cmd.stdout.read().decode()
     ld_cmd.wait()
 
@@ -345,11 +360,13 @@ def have_ld_plugin_support():
     if len(fields) != 3:
         return False
     emulations = fields[2].split()
-    if 'elf32ppc' not in emulations or 'elf_x86_64' not in emulations:
+    if 'elf_x86_64' not in emulations:
         return False
+    if 'elf32ppc' in emulations:
+        config.available_features.add('ld_emu_elf32ppc')
 
-    ld_version = subprocess.Popen(['ld', '--version'], stdout = subprocess.PIPE)
-    if not 'GNU gold' in ld_version.stdout.read():
+    ld_version = subprocess.Popen([config.gold_executable, '--version'], stdout = subprocess.PIPE)
+    if not 'GNU gold' in ld_version.stdout.read().decode():
         return False
     ld_version.wait()
 
@@ -358,6 +375,22 @@ def have_ld_plugin_support():
 if have_ld_plugin_support():
     config.available_features.add('ld_plugin')
 
+def have_ld64_plugin_support():
+    if config.ld64_executable == '':
+        return False
+
+    ld_cmd = subprocess.Popen([config.ld64_executable, '-v'], stderr = subprocess.PIPE)
+    ld_out = ld_cmd.stderr.read().decode()
+    ld_cmd.wait()
+
+    if 'ld64' not in ld_out or 'LTO' not in ld_out:
+        return False
+
+    return True
+
+if have_ld64_plugin_support():
+    config.available_features.add('ld64_plugin')
+
 # Ask llvm-config about assertion mode.
 try:
     llvm_config_cmd = subprocess.Popen(
diff --git a/test/lit.site.cfg.in b/test/lit.site.cfg.in
index 64ad0c398420..0f5d223a3abf 100644
--- a/test/lit.site.cfg.in
+++ b/test/lit.site.cfg.in
@@ -13,6 +13,8 @@ config.llvm_shlib_ext = "@SHLIBEXT@"
 config.llvm_exe_ext = "@EXEEXT@"
 config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"
 config.python_executable = "@PYTHON_EXECUTABLE@"
+config.gold_executable = "@GOLD_EXECUTABLE@"
+config.ld64_executable = "@LD64_EXECUTABLE@"
 config.ocamlfind_executable = "@OCAMLFIND@"
 config.have_ocamlopt = "@HAVE_OCAMLOPT@"
 config.have_ocaml_ounit = "@HAVE_OCAML_OUNIT@"
@@ -30,6 +32,7 @@ config.host_ldflags = "@HOST_LDFLAGS@"
 config.llvm_use_intel_jitevents = "@LLVM_USE_INTEL_JITEVENTS@"
 config.llvm_use_sanitizer = "@LLVM_USE_SANITIZER@"
 config.have_zlib = "@HAVE_LIBZ@"
+config.have_dia_sdk = @HAVE_DIA_SDK@
 config.enable_ffi = "@LLVM_ENABLE_FFI@"
 
 # Support substitution of the tools_dir with user parameters. This is
diff --git a/test/tools/dsymutil/Inputs/basic-lto-dw4.macho.x86_64 b/test/tools/dsymutil/Inputs/basic-lto-dw4.macho.x86_64
new file mode 100755
index 000000000000..7e7ba2f48f86
--- /dev/null
+++ b/test/tools/dsymutil/Inputs/basic-lto-dw4.macho.x86_64
diff --git a/test/tools/dsymutil/Inputs/basic-lto-dw4.macho.x86_64.o b/test/tools/dsymutil/Inputs/basic-lto-dw4.macho.x86_64.o
new file mode 100644
index 000000000000..307a68130920
--- /dev/null
+++ b/test/tools/dsymutil/Inputs/basic-lto-dw4.macho.x86_64.o
diff --git a/test/tools/dsymutil/X86/basic-linking-x86.test b/test/tools/dsymutil/X86/basic-linking-x86.test
new file mode 100644
index 000000000000..1059e233f94b
--- /dev/null
+++ b/test/tools/dsymutil/X86/basic-linking-x86.test
@@ -0,0 +1,218 @@
+REQUIRES: shell
+RUN: cat %p/../Inputs/basic.macho.x86_64 > %t1
+RUN: llvm-dsymutil -oso-prepend-path=%p/.. %t1
+RUN: llvm-dwarfdump %t1.dwarf | FileCheck %s
+RUN: llvm-dsymutil -o %t2 -oso-prepend-path=%p/.. %p/../Inputs/basic.macho.x86_64
+RUN: llvm-dwarfdump %t2 | FileCheck %s
+RUN: llvm-dsymutil -o - -oso-prepend-path=%p/.. %p/../Inputs/basic.macho.x86_64 | llvm-dwarfdump - | FileCheck %s --check-prefix=CHECK --check-prefix=BASIC
+RUN: llvm-dsymutil -o - -oso-prepend-path=%p/.. %p/../Inputs/basic-archive.macho.x86_64 | llvm-dwarfdump - | FileCheck %s --check-prefix=CHECK --check-prefix=ARCHIVE
+
+CHECK: file format Mach-O 64-bit x86-64
+
+CHECK: debug_info contents
+
+CHECK:  Compile Unit:
+
+CHECK:  DW_TAG_compile_unit [1] *
+CHECK:    DW_AT_producer [DW_FORM_strp]     ( .debug_str[0x00000001] = "Apple LLVM version 6.0 (clang-600.0.39) (based on LLVM 3.5svn)")
+CHECK:    DW_AT_language [DW_FORM_data2]	(DW_LANG_C99)
+CHECK:    DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000040] = "basic1.c")
+CHECK:    DW_AT_stmt_list [DW_FORM_data4]   (0x00000000)
+CHECK:    DW_AT_comp_dir [DW_FORM_strp]     ( .debug_str[0x00000049] = "/Inputs")
+CHECK:    DW_AT_low_pc [DW_FORM_addr]       (0x0000000100000ea0)
+CHECK:    DW_TAG_subprogram [2] *
+CHECK:    DW_AT_name [DW_FORM_strp]       ( .debug_str[0x00000051] = "main")
+CHECK:      DW_AT_decl_file [DW_FORM_data1] ("/Inputs{{[/\\]}}basic1.c")
+CHECK:      DW_AT_decl_line [DW_FORM_data1]	(23)
+CHECK:      DW_AT_prototyped [DW_FORM_flag]	(0x01)
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x0063 => {0x00000063})
+CHECK:      DW_AT_external [DW_FORM_flag]	(0x01)
+CHECK:      DW_AT_accessibility [DW_FORM_data1]	(DW_ACCESS_public)
+CHECK:      DW_AT_low_pc [DW_FORM_addr]     (0x0000000100000ea0)
+CHECK:      DW_AT_high_pc [DW_FORM_addr]    (0x0000000100000ec4)
+CHECK:      DW_AT_frame_base [DW_FORM_block1]	(<0x01> 56 )
+CHECK:      DW_TAG_formal_parameter [3]
+CHECK:        DW_AT_name [DW_FORM_strp]     ( .debug_str[0x00000056] = "argc")
+CHECK:        DW_AT_decl_file [DW_FORM_data1]       ("/Inputs{{[/\\]}}basic1.c")
+CHECK:        DW_AT_decl_line [DW_FORM_data1]	(23)
+CHECK:        DW_AT_type [DW_FORM_ref4]     (cu + 0x0063 => {0x00000063})
+CHECK:        DW_AT_location [DW_FORM_block1]	(<0x02> 91 78 )
+CHECK:      DW_TAG_formal_parameter [3]
+CHECK:        DW_AT_name [DW_FORM_strp]     ( .debug_str[0x0000005b] = "argv")
+CHECK:        DW_AT_decl_file [DW_FORM_data1]	("/Inputs{{[/\\]}}basic1.c")
+CHECK:        DW_AT_decl_line [DW_FORM_data1]	(23)
+CHECK:        DW_AT_type [DW_FORM_ref4]     (cu + 0x006a => {0x0000006a})
+CHECK:        DW_AT_location [DW_FORM_block1]	(<0x02> 91 70 )
+CHECK:      NULL
+CHECK:    DW_TAG_base_type [4]
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x00000060] = "int")
+CHECK:      DW_AT_encoding [DW_FORM_data1]	(DW_ATE_signed)
+CHECK:      DW_AT_byte_size [DW_FORM_data1]	(0x04)
+CHECK:    DW_TAG_pointer_type [5]
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x006f => {0x0000006f})
+CHECK:    DW_TAG_pointer_type [5]
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x0074 => {0x00000074})
+CHECK:    DW_TAG_const_type [6]
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x0079 => {0x00000079})
+CHECK:    DW_TAG_base_type [4]
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x00000064] = "char")
+CHECK:      DW_AT_encoding [DW_FORM_data1]	(DW_ATE_signed_char)
+CHECK:      DW_AT_byte_size [DW_FORM_data1]	(0x01)
+CHECK:    NULL
+
+CHECK:  Compile Unit:
+
+CHECK:  DW_TAG_compile_unit [1] *
+CHECK:   DW_AT_producer [DW_FORM_strp]     ( .debug_str[0x00000001] = "Apple LLVM version 6.0 (clang-600.0.39) (based on LLVM 3.5svn)")
+CHECK:   DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000069] = "basic2.c")
+CHECK:   DW_AT_stmt_list [DW_FORM_data4]   (0x0000003f)
+CHECK:   DW_AT_comp_dir [DW_FORM_strp]     ( .debug_str[0x00000049] = "/Inputs")
+CHECK:   DW_AT_low_pc [DW_FORM_addr]       (0x0000000100000ed0)
+CHECK:    DW_TAG_base_type [4]
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x00000060] = "int")
+CHECK:    DW_TAG_variable [7]
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x00000072] = "private_int")
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x0026 => {0x000000a7})
+CHECK:      DW_AT_decl_file [DW_FORM_data1] ("/Inputs{{[/\\]}}basic2.c")
+BASIC:      DW_AT_location [DW_FORM_block1] (<0x09> 03 08 10 00 00 01 00 00 00 )
+ARCHIVE:    DW_AT_location [DW_FORM_block1] (<0x09> 03 04 10 00 00 01 00 00 00 )
+CHECK:    DW_TAG_variable [7]
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x0000007e] = "baz")
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x0026 => {0x000000a7})
+CHECK:      DW_AT_decl_file [DW_FORM_data1] ("/Inputs{{[/\\]}}basic2.c")
+CHECK:      DW_AT_location [DW_FORM_block1] (<0x09> 03 00 10 00 00 01 00 00 00 )
+CHECK:    DW_TAG_subprogram [2] *
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x00000082] = "foo")
+CHECK:      DW_AT_decl_file [DW_FORM_data1] ("/Inputs{{[/\\]}}basic2.c")
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x0026 => {0x000000a7})
+CHECK:      DW_AT_low_pc [DW_FORM_addr]     (0x0000000100000ed0)
+CHECK:      DW_AT_high_pc [DW_FORM_addr]    (0x0000000100000f19)
+CHECK:      DW_AT_frame_base [DW_FORM_block1]	(<0x01> 56 )
+CHECK:      DW_TAG_formal_parameter [3]
+CHECK:        DW_AT_name [DW_FORM_strp]     ( .debug_str[0x00000086] = "arg")
+CHECK:        DW_AT_type [DW_FORM_ref4]     (cu + 0x0026 => {0x000000a7})
+CHECK:        DW_AT_location [DW_FORM_block1]	(<0x02> 91 7c )
+CHECK:      NULL
+CHECK:    DW_TAG_subprogram [8]
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x0000008a] = "inc")
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x0026 => {0x000000a7})
+CHECK:      DW_AT_low_pc [DW_FORM_addr]     (0x0000000100000f20)
+CHECK:      DW_AT_high_pc [DW_FORM_addr]    (0x0000000100000f37)
+CHECK:      DW_AT_frame_base [DW_FORM_block1]	(<0x01> 56 )
+CHECK:    NULL
+
+CHECK:  Compile Unit:
+
+CHECK:  DW_TAG_compile_unit [1] *
+CHECK:    DW_AT_producer [DW_FORM_strp]     ( .debug_str[0x00000001] = "Apple LLVM version 6.0 (clang-600.0.39) (based on LLVM 3.5svn)")
+CHECK:    DW_AT_name [DW_FORM_strp] ( .debug_str[0x0000008e] = "basic3.c")
+CHECK:    DW_AT_stmt_list [DW_FORM_data4]   (0x00000093)
+CHECK:    DW_AT_comp_dir [DW_FORM_strp]     ( .debug_str[0x00000049] = "/Inputs")
+CHECK:    DW_AT_low_pc [DW_FORM_addr]       (0x0000000100000f40)
+CHECK:    DW_TAG_variable [9]
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x00000097] = "val")
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x003c => {0x00000162})
+CHECK:      DW_AT_decl_file [DW_FORM_data1] ("/Inputs{{[/\\]}}basic3.c")
+BASIC:      DW_AT_location [DW_FORM_block1] (<0x09> 03 04 10 00 00 01 00 00 00 )
+ARCHIVE:    DW_AT_location [DW_FORM_block1] (<0x09> 03 08 10 00 00 01 00 00 00 )
+CHECK:    DW_TAG_volatile_type [10]
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x0041 => {0x00000167})
+CHECK:    DW_TAG_base_type [4]
+CHACK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x00000060] = "int")
+CHECK:    DW_TAG_subprogram [2] *
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x0000009b] = "bar")
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x0041 => {0x00000167})
+CHECK:      DW_AT_low_pc [DW_FORM_addr]     (0x0000000100000f40)
+CHECK:      DW_AT_high_pc [DW_FORM_addr]    (0x0000000100000f84)
+CHECK:      DW_AT_frame_base [DW_FORM_block1]	(<0x01> 56 )
+CHECK:      DW_TAG_formal_parameter [3]
+CHECK:        DW_AT_name [DW_FORM_strp]     ( .debug_str[0x00000086] = "arg")
+CHECK:        DW_AT_type [DW_FORM_ref4]     (cu + 0x0041 => {0x00000167})
+CHECK:        DW_AT_location [DW_FORM_block1]	(<0x02> 91 78 )
+CHECK:      NULL
+CHECK:    DW_TAG_subprogram [8]
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x0000008a] = "inc")
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x0041 => {0x00000167})
+CHECK:      DW_AT_low_pc [DW_FORM_addr]     (0x0000000100000f90)
+CHECK:      DW_AT_high_pc [DW_FORM_addr]    (0x0000000100000fa9)
+CHECK:      DW_AT_frame_base [DW_FORM_block1]	(<0x01> 56 )
+
+CHECK:    NULL
+
+CHECK: .debug_loc contents
+CHECK-NOT: Location
+
+CHECK:.debug_aranges contents:
+CHECK-NEXT:Address Range Header: length = 0x0000002c, version = 0x0002, cu_offset = 0x00000000, addr_size = 0x08, seg_size = 0x00
+CHECK-NEXT:[0x0000000100000ea0 - 0x0000000100000ec4)
+CHECK-NEXT:Address Range Header: length = 0x0000003c, version = 0x0002, cu_offset = 0x00000081, addr_size = 0x08, seg_size = 0x00
+CHECK-NEXT:[0x0000000100000ed0 - 0x0000000100000f19)
+CHECK-NEXT:[0x0000000100000f20 - 0x0000000100000f37)
+CHECK-NEXT:Address Range Header: length = 0x0000003c, version = 0x0002, cu_offset = 0x00000126, addr_size = 0x08, seg_size = 0x00
+CHECK-NEXT:[0x0000000100000f40 - 0x0000000100000f84)
+CHECK-NEXT:[0x0000000100000f90 - 0x0000000100000fa9)
+
+CHECK: .debug_line contents:
+CHECK:                Dir  Mod Time   File Len   File Name
+CHECK-NEXT:                 ---- ---------- ---------- ---------------------------
+CHECK-NEXT: file_names[  1]    0 0x00000000 0x00000000 basic1.c
+CHECK: Address            Line   Column File   ISA Discriminator Flags
+CHECK-NEXT: ------------------ ------ ------ ------ --- ------------- -------------
+CHECK-NEXT: 0x0000000100000ea0     23      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000eb6     24      0      1   0             0  is_stmt prologue_end
+CHECK-NEXT: 0x0000000100000ec4     24      0      1   0             0  is_stmt end_sequence
+
+CHECK:                 Dir  Mod Time   File Len   File Name
+CHECK-NEXT:                 ---- ---------- ---------- ---------------------------
+CHECK-NEXT: file_names[  1]    0 0x00000000 0x00000000 basic2.c
+CHECK: Address            Line   Column File   ISA Discriminator Flags
+CHECK-NEXT: ------------------ ------ ------ ------ --- ------------- -------------
+CHECK-NEXT: 0x0000000100000ed0     19      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000ee2     20      0      1   0             0  is_stmt prologue_end
+CHECK-NEXT: 0x0000000100000f19     20      0      1   0             0  is_stmt end_sequence
+CHECK-NEXT: 0x0000000100000f20     14      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f24     15      0      1   0             0  is_stmt prologue_end
+CHECK-NEXT: 0x0000000100000f37     15      0      1   0             0  is_stmt end_sequence
+
+CHECK:                 Dir  Mod Time   File Len   File Name
+CHECK-NEXT:                 ---- ---------- ---------- ---------------------------
+CHECK-NEXT: file_names[  1]    0 0x00000000 0x00000000 basic3.c
+CHECK: Address            Line   Column File   ISA Discriminator Flags
+CHECK-NEXT: ------------------ ------ ------ ------ --- ------------- -------------
+CHECK-NEXT: 0x0000000100000f40     16      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f4b     17      0      1   0             0  is_stmt prologue_end
+CHECK-NEXT: 0x0000000100000f58     18      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f6c     19      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f7b     20      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f84     20      0      1   0             0  is_stmt end_sequence
+CHECK-NEXT: 0x0000000100000f90     11      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f9b     12      0      1   0             0  is_stmt prologue_end
+CHECK-NEXT: 0x0000000100000fa9     12      0      1   0             0  is_stmt end_sequence
+
+CHECK: .debug_pubnames contents:
+CHECK-NEXT: length = 0x00000017 version = 0x0002 unit_offset = 0x00000000 unit_size = 0x00000081
+CHECK-NEXT: Offset     Name
+CHECK-NEXT: 0x00000026 "main"
+CHECK-NEXT: length = 0x00000036 version = 0x0002 unit_offset = 0x00000081 unit_size = 0x000000a5
+CHECK-NEXT: Offset     Name
+CHECK-NEXT: 0x0000002d "private_int"
+CHECK-NEXT: 0x00000042 "baz"
+CHECK-NEXT: 0x00000057 "foo"
+CHECK-NEXT: 0x00000086 "inc"
+CHECK-NEXT: length = 0x00000026 version = 0x0002 unit_offset = 0x00000126 unit_size = 0x00000096
+CHECK-NEXT: Offset     Name
+CHECK-NEXT: 0x00000026 "val"
+CHECK-NEXT: 0x00000048 "bar"
+CHECK-NEXT: 0x00000077 "inc"
+
+CHECK: .debug_pubtypes contents:
+CHECK-NEXT: length = 0x0000001f version = 0x0002 unit_offset = 0x00000000 unit_size = 0x00000081
+CHECK-NEXT: Offset     Name
+CHECK-NEXT: 0x00000063 "int"
+CHECK-NEXT: 0x00000079 "char"
+CHECK-NEXT: length = 0x00000016 version = 0x0002 unit_offset = 0x00000081 unit_size = 0x000000a5
+CHECK-NEXT: Offset     Name
+CHECK-NEXT: 0x00000026 "int"
+CHECK-NEXT: length = 0x00000016 version = 0x0002 unit_offset = 0x00000126 unit_size = 0x00000096
+CHECK-NEXT: Offset     Name
+CHECK-NEXT: 0x00000041 "int"
diff --git a/test/tools/dsymutil/X86/basic-lto-dw4-linking-x86.test b/test/tools/dsymutil/X86/basic-lto-dw4-linking-x86.test
new file mode 100644
index 000000000000..ad3ba5a15b6b
--- /dev/null
+++ b/test/tools/dsymutil/X86/basic-lto-dw4-linking-x86.test
@@ -0,0 +1,204 @@
+REQUIRES: shell
+RUN: llvm-dsymutil -o - -oso-prepend-path=%p/.. %p/../Inputs/basic-lto-dw4.macho.x86_64 | llvm-dwarfdump - | FileCheck %s
+
+CHECK: file format Mach-O 64-bit x86-64
+
+CHECK: debug_info contents
+
+CHECK:  Compile Unit: {{.*}} version = 0x0004
+CHECK:  DW_TAG_compile_unit [1] *
+CHECK:    DW_AT_producer [DW_FORM_strp]	( .debug_str[0x00000001] = "clang version 3.7.0 ")
+CHECK:    DW_AT_language [DW_FORM_data2]	(DW_LANG_C99)
+CHECK:    DW_AT_name [DW_FORM_strp]	( .debug_str[0x00000016] = "basic1.c")
+CHECK:    DW_AT_stmt_list [DW_FORM_sec_offset]      (0x00000000)
+CHECK:    DW_AT_comp_dir [DW_FORM_strp]	( .debug_str[0x0000001f] = "/Inputs")
+CHECK:    DW_AT_low_pc [DW_FORM_addr]       (0x0000000100000f40)
+CHECK:    DW_AT_high_pc [DW_FORM_data4]     (0x0000000b)
+CHECK:    DW_TAG_subprogram [2] *
+CHECK:      DW_AT_low_pc [DW_FORM_addr]	(0x0000000100000f40)
+CHECK:      DW_AT_high_pc [DW_FORM_data4]	(0x0000000b)
+CHECK:      DW_AT_frame_base [DW_FORM_exprloc]	(<0x1> 56 )
+CHECK:      DW_AT_name [DW_FORM_strp]	( .debug_str[0x00000027] = "main")
+CHECK:      DW_AT_decl_file [DW_FORM_data1] ("/Inputs{{[/\\]}}basic1.c")
+CHECK:      DW_AT_prototyped [DW_FORM_flag_present]	(true)
+CHECK:      DW_AT_type [DW_FORM_ref_addr]   (0x00000000000000a1)
+CHECK:      DW_AT_external [DW_FORM_flag_present]	(true)
+CHECK:      DW_TAG_formal_parameter [3]  
+CHECK:        DW_AT_location [DW_FORM_exprloc]	(<0x3> 55 93 04 )
+CHECK:        DW_AT_name [DW_FORM_strp]	( .debug_str[0x0000002c] = "argc")
+CHECK:        DW_AT_decl_file [DW_FORM_data1]       ("/Inputs{{[/\\]}}basic1.c")
+CHECK:        DW_AT_type [DW_FORM_ref_addr] (0x00000000000000a1)
+CHECK:      DW_TAG_formal_parameter [4]  
+CHECK:        DW_AT_location [DW_FORM_exprloc]	(<0x1> 54 )
+CHECK:        DW_AT_name [DW_FORM_strp]	( .debug_str[0x00000031] = "argv")
+CHECK:        DW_AT_type [DW_FORM_ref4]     (cu + 0x0060 => {0x00000060})
+CHECK:      NULL
+CHECK:    DW_TAG_pointer_type [5]
+CHECK:       DW_AT_type [DW_FORM_ref4]       (cu + 0x0065 => {0x00000065})
+CHECK:    DW_TAG_pointer_type [5]  
+CHECK:    DW_TAG_const_type [6]  
+CHECK:    DW_TAG_base_type [7]  
+CHECK:      DW_AT_name [DW_FORM_strp]	( .debug_str[0x00000036] = "char")
+CHECK:      DW_AT_encoding [DW_FORM_data1]	(DW_ATE_signed_char)
+CHECK:      DW_AT_byte_size [DW_FORM_data1]	(0x01)
+CHECK:    NULL
+
+CHECK:  Compile Unit:{{.*}} version = 0x0004
+
+CHECK:  DW_TAG_compile_unit [1] *
+CHECK:    DW_AT_producer [DW_FORM_strp]	( .debug_str[0x00000001] = "clang version 3.7.0 ")
+CHECK:    DW_AT_language [DW_FORM_data2]	(DW_LANG_C99)
+CHECK:    DW_AT_name [DW_FORM_strp]	( .debug_str[0x0000003b] = "basic2.c")
+CHECK:    DW_AT_stmt_list [DW_FORM_sec_offset]      (0x00000044)
+CHECK:    DW_AT_low_pc [DW_FORM_addr]       (0x0000000100000f50)
+CHECK:    DW_AT_high_pc [DW_FORM_data4]     (0x00000037)
+CHECK:    DW_TAG_base_type [7]  
+CHECK:      DW_AT_name [DW_FORM_strp]	( .debug_str[0x00000044] = "int")
+CHECK:    DW_TAG_variable [8]  
+CHECK:      DW_AT_name [DW_FORM_strp]	( .debug_str[0x00000048] = "baz")
+CHECK:      DW_AT_location [DW_FORM_exprloc]	(<0x9> 03 00 10 00 00 01 00 00 00 )
+CHECK:    DW_TAG_variable [8]  
+CHECK:      DW_AT_name [DW_FORM_strp]	( .debug_str[0x0000004c] = "private_int")
+CHECK:      DW_AT_decl_file [DW_FORM_data1] ("/Inputs{{[/\\]}}basic2.c")
+CHECK:      DW_AT_location [DW_FORM_exprloc]	(<0x9> 03 08 10 00 00 01 00 00 00 )
+CHECK:    DW_TAG_subprogram [9]  
+CHECK:      DW_AT_name [DW_FORM_strp]	( .debug_str[0x00000058] = "inc")
+CHECK:      DW_AT_type [DW_FORM_ref4]	(cu + 0x002a => {0x000000a1})
+CHECK:      DW_AT_inline [DW_FORM_data1]	(DW_INL_inlined)
+CHECK:    DW_TAG_subprogram [10] *
+CHECK:      DW_AT_low_pc [DW_FORM_addr]	(0x0000000100000f50)
+CHECK:      DW_AT_high_pc [DW_FORM_data4]	(0x00000037)
+CHECK:      DW_AT_frame_base [DW_FORM_exprloc]	(<0x1> 56 )
+CHECK:      DW_AT_name [DW_FORM_strp]	( .debug_str[0x0000005c] = "foo")
+CHECK:      DW_AT_decl_file [DW_FORM_data1] ("/Inputs{{[/\\]}}basic2.c")
+CHECK:      DW_AT_prototyped [DW_FORM_flag_present]	(true)
+CHECK:      DW_AT_type [DW_FORM_ref4]	(cu + 0x002a => {0x000000a1})
+CHECK:      DW_TAG_formal_parameter [11]
+CHECK:        DW_AT_location [DW_FORM_sec_offset]   (0x00000000)
+CHECK:        DW_AT_name [DW_FORM_strp]	( .debug_str[0x00000060] = "arg")
+CHECK:        DW_AT_type [DW_FORM_ref4]	(cu + 0x002a => {0x000000a1})
+CHECK:      DW_TAG_inlined_subroutine [12]  
+CHECK:        DW_AT_abstract_origin [DW_FORM_ref4]	(cu + 0x005b => {0x000000d2} "inc")
+CHECK:        DW_AT_low_pc [DW_FORM_addr]	(0x0000000100000f61)
+CHECK:        DW_AT_high_pc [DW_FORM_data4]	(0x0000000f)
+CHECK:      NULL
+CHECK:    NULL
+
+CHECK:  Compile Unit: {{.*}} version = 0x0004
+
+CHECK:  DW_TAG_compile_unit [1] *
+CHECK:    DW_AT_producer [DW_FORM_strp]	( .debug_str[0x00000001] = "clang version 3.7.0 ")
+CHECK:    DW_AT_name [DW_FORM_strp]	( .debug_str[0x00000064] = "basic3.c")
+CHECK:    DW_AT_stmt_list [DW_FORM_sec_offset]      (0x0000009a)
+CHECK:    DW_AT_low_pc [DW_FORM_addr]       (0x0000000100000f90)
+CHECK:    DW_AT_high_pc [DW_FORM_data4]     (0x00000024)
+CHECK:    DW_TAG_variable [13]  
+CHECK:      DW_AT_name [DW_FORM_strp]	( .debug_str[0x0000006d] = "val")
+CHECK:      DW_AT_decl_file [DW_FORM_data1] ("/Inputs{{[/\\]}}basic3.c")
+CHECK:      DW_AT_location [DW_FORM_exprloc]	(<0x9> 03 04 10 00 00 01 00 00 00 )
+CHECK:    DW_TAG_volatile_type [14]  
+CHECK:    DW_TAG_subprogram [15]  
+CHECK:      DW_AT_name [DW_FORM_strp]	( .debug_str[0x00000058] = "inc")
+CHECK:      DW_AT_inline [DW_FORM_data1]	(DW_INL_inlined)
+CHECK:    DW_TAG_subprogram [2] *
+CHECK:      DW_AT_low_pc [DW_FORM_addr]	(0x0000000100000f90)
+CHECK:      DW_AT_high_pc [DW_FORM_data4]	(0x00000024)
+CHECK:      DW_AT_frame_base [DW_FORM_exprloc]	(<0x1> 56 )
+CHECK:      DW_AT_name [DW_FORM_strp]	( .debug_str[0x00000071] = "bar")
+CHECK:      DW_TAG_formal_parameter [16]
+CHECK:        DW_AT_location [DW_FORM_sec_offset]   (0x00000025)
+CHECK:        DW_AT_name [DW_FORM_strp]	( .debug_str[0x00000060] = "arg")
+CHECK:      DW_TAG_inlined_subroutine [17]  
+CHECK:        DW_AT_abstract_origin [DW_FORM_ref4]	(cu + 0x0044 => {0x0000015f} "inc")
+CHECK:        DW_AT_ranges [DW_FORM_sec_offset]     (0x00000000
+CHECK:           [0x0000000100000f94 - 0x0000000100000f9a)
+CHECK:           [0x0000000100000f9f - 0x0000000100000fa7))
+
+CHECK:      NULL
+CHECK:    NULL
+
+
+CHECK: .debug_loc contents:
+CHECK-NEXT: 0x00000000: Beginning address offset: 0x0000000000000000
+CHECK-NEXT:                Ending address offset: 0x000000000000000c
+CHECK-NEXT:                 Location description: 55 93 04
+CHECK-NEXT: {{^$}}
+CHECK-NEXT: 0x00000025: Beginning address offset: 0x0000000000000000
+CHECK-NEXT:                Ending address offset: 0x000000000000000f
+CHECK-NEXT:                 Location description: 55 93 04 
+CHECK-NEXT: {{^$}}
+CHECK-NEXT:             Beginning address offset: 0x0000000000000019
+CHECK-NEXT:                Ending address offset: 0x000000000000001d
+CHECK-NEXT:                 Location description: 55 93 04 
+
+CHECK: .debug_aranges contents:
+CHECK-NEXT: Address Range Header: length = 0x0000002c, version = 0x0002, cu_offset = 0x00000000, addr_size = 0x08, seg_size = 0x00
+CHECK-NEXT: [0x0000000100000f40 - 0x0000000100000f4b)
+CHECK-NEXT: Address Range Header: length = 0x0000002c, version = 0x0002, cu_offset = 0x00000077, addr_size = 0x08, seg_size = 0x00
+CHECK-NEXT: [0x0000000100000f50 - 0x0000000100000f87)
+CHECK-NEXT: Address Range Header: length = 0x0000002c, version = 0x0002, cu_offset = 0x0000011b, addr_size = 0x08, seg_size = 0x00
+CHECK-NEXT: [0x0000000100000f90 - 0x0000000100000fb4)
+
+CHECK: .debug_line contents:
+CHECK:                 Dir  Mod Time   File Len   File Name
+CHECK-NEXT:                 ---- ---------- ---------- ---------------------------
+CHECK-NEXT: file_names[  1]    0 0x00000000 0x00000000 basic1.c
+CHECK: Address            Line   Column File   ISA Discriminator Flags
+CHECK-NEXT: ------------------ ------ ------ ------ --- ------------- -------------
+CHECK-NEXT: 0x0000000100000f40     26      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f44     27     10      1   0             0  is_stmt prologue_end
+CHECK-NEXT: 0x0000000100000f49     27      3      1   0             0 
+CHECK-NEXT: 0x0000000100000f4b     27      3      1   0             0  end_sequence
+
+CHECK:                 Dir  Mod Time   File Len   File Name
+CHECK-NEXT:                 ---- ---------- ---------- ---------------------------
+CHECK-NEXT: file_names[  1]    0 0x00000000 0x00000000 basic2.c
+CHECK: Address            Line   Column File   ISA Discriminator Flags
+CHECK-NEXT: ------------------ ------ ------ ------ --- ------------- -------------
+CHECK-NEXT: 0x0000000100000f50     19      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f54     20     18      1   0             0  is_stmt prologue_end
+CHECK-NEXT: 0x0000000100000f5a     20     17      1   0             0 
+CHECK-NEXT: 0x0000000100000f5c     20     10      1   0             0 
+CHECK-NEXT: 0x0000000100000f61     15     10      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f70     20     23      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f74     20     36      1   0             0 
+CHECK-NEXT: 0x0000000100000f83     20     31      1   0             0 
+CHECK-NEXT: 0x0000000100000f85     20      3      1   0             0 
+CHECK-NEXT: 0x0000000100000f87     20      3      1   0             0  end_sequence
+
+CHECK:                 Dir  Mod Time   File Len   File Name
+CHECK-NEXT:                 ---- ---------- ---------- ---------------------------
+CHECK-NEXT: file_names[  1]    0 0x00000000 0x00000000 basic3.c
+CHECK: Address            Line   Column File   ISA Discriminator Flags
+CHECK-NEXT: ------------------ ------ ------ ------ --- ------------- -------------
+CHECK-NEXT: 0x0000000100000f90     16      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f94     12     10      1   0             0  is_stmt prologue_end
+CHECK-NEXT: 0x0000000100000f9a     17      7      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f9f     12     10      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000fa7     20      1      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000fa9     19     18      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000fab     19     10      1   0             0 
+CHECK-NEXT: 0x0000000100000fb2     20      1      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000fb4     20      1      1   0             0  is_stmt end_sequence
+
+CHECK: .debug_pubnames contents:
+CHECK-NEXT: length = 0x00000017 version = 0x0002 unit_offset = 0x00000000 unit_size = 0x00000077
+CHECK-NEXT: Offset     Name
+CHECK-NEXT: 0x0000002a "main"
+CHECK-NEXT: length = 0x0000002e version = 0x0002 unit_offset = 0x00000077 unit_size = 0x000000a4
+CHECK-NEXT: Offset     Name
+CHECK-NEXT: 0x00000031 "baz"
+CHECK-NEXT: 0x00000046 "private_int"
+CHECK-NEXT: 0x00000067 "foo"
+CHECK-NEXT: length = 0x0000001e version = 0x0002 unit_offset = 0x0000011b unit_size = 0x00000085
+CHECK-NEXT: Offset     Name
+CHECK-NEXT: 0x0000002a "val"
+CHECK-NEXT: 0x00000050 "bar"
+
+CHECK: .debug_pubtypes contents:
+CHECK-NEXT: length = 0x00000017 version = 0x0002 unit_offset = 0x00000000 unit_size = 0x00000077
+CHECK-NEXT: Offset     Name
+CHECK-NEXT: 0x0000006f "char"
+CHECK-NEXT: length = 0x00000016 version = 0x0002 unit_offset = 0x00000077 unit_size = 0x000000a4
+CHECK-NEXT: Offset     Name
+CHECK-NEXT: 0x0000002a "int"
diff --git a/test/tools/dsymutil/X86/basic-lto-linking-x86.test b/test/tools/dsymutil/X86/basic-lto-linking-x86.test
new file mode 100644
index 000000000000..22b6e0808d8a
--- /dev/null
+++ b/test/tools/dsymutil/X86/basic-lto-linking-x86.test
@@ -0,0 +1,207 @@
+REQUIRES: shell
+RUN: llvm-dsymutil -o - -oso-prepend-path=%p/.. %p/../Inputs/basic-lto.macho.x86_64 | llvm-dwarfdump - | FileCheck %s
+
+CHECK: file format Mach-O 64-bit x86-64
+
+CHECK: debug_info contents
+
+CHECK:  Compile Unit:
+
+CHECK:  DW_TAG_compile_unit [1] *
+CHECK:    DW_AT_producer [DW_FORM_strp]     ( .debug_str[0x00000001] = "Apple LLVM version 6.0 (clang-600.0.39) (based on LLVM 3.5svn)")
+CHECK:    DW_AT_language [DW_FORM_data2]	(DW_LANG_C99)
+CHECK:    DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000040] = "basic1.c")
+CHECK:    DW_AT_stmt_list [DW_FORM_data4]   (0x00000000)
+CHECK:    DW_AT_comp_dir [DW_FORM_strp]     ( .debug_str[0x00000049] = "/Inputs")
+CHECK:    DW_AT_low_pc [DW_FORM_addr]       (0x0000000100000f40)
+CHECK:    DW_TAG_subprogram [2] *
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x00000051] = "main")
+CHECK:      DW_AT_decl_file [DW_FORM_data1] ("/Inputs{{[/\\]}}basic1.c")
+CHECK:      DW_AT_decl_line [DW_FORM_data1]	(23)
+CHECK:      DW_AT_prototyped [DW_FORM_flag]	(0x01)
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x0063 => {0x00000063})
+CHECK:      DW_AT_external [DW_FORM_flag]	(0x01)
+CHECK:      DW_AT_accessibility [DW_FORM_data1]	(DW_ACCESS_public)
+CHECK:      DW_AT_low_pc [DW_FORM_addr]     (0x0000000100000f40)
+CHECK:      DW_AT_high_pc [DW_FORM_addr]     (0x0000000100000f4b)
+CHECK:      DW_AT_frame_base [DW_FORM_block1]	(<0x01> 56 )
+CHECK:      DW_TAG_formal_parameter [3]
+CHECK:        DW_AT_name [DW_FORM_strp]     ( .debug_str[0x00000056] = "argc")
+CHECK:        DW_AT_type [DW_FORM_ref4]     (cu + 0x0063 => {0x00000063})
+CHECK:        DW_AT_location [DW_FORM_block1]	(<0x03> 55 93 04 )
+CHECK:      DW_TAG_formal_parameter [3]
+CHECK:        DW_AT_name [DW_FORM_strp]     ( .debug_str[0x0000005b] = "argv")
+CHECK:        DW_AT_type [DW_FORM_ref4]     (cu + 0x006a => {0x0000006a})
+CHECK:        DW_AT_location [DW_FORM_block1]	(<0x01> 54 )
+CHECK:      NULL
+CHECK:    DW_TAG_base_type [4]
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x00000060] = "int")
+CHECK:      DW_AT_encoding [DW_FORM_data1]	(DW_ATE_signed)
+CHECK:      DW_AT_byte_size [DW_FORM_data1]	(0x04)
+CHECK:    DW_TAG_pointer_type [5]
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x006f => {0x0000006f})
+CHECK:    DW_TAG_pointer_type [5]
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x0074 => {0x00000074})
+CHECK:    DW_TAG_const_type [6]
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x0079 => {0x00000079})
+CHECK:    DW_TAG_base_type [4]
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x00000064] = "char")
+CHECK:      DW_AT_encoding [DW_FORM_data1]	(DW_ATE_signed_char)
+CHECK:      DW_AT_byte_size [DW_FORM_data1]	(0x01)
+CHECK:    NULL
+
+CHECK:  Compile Unit:
+
+CHECK:  DW_TAG_compile_unit [1] *
+CHECK:    DW_AT_producer [DW_FORM_strp]     ( .debug_str[0x00000001] = "Apple LLVM version 6.0 (clang-600.0.39) (based on LLVM 3.5svn)")
+CHECK:    DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000069] = "basic2.c")
+CHECK:    DW_AT_stmt_list [DW_FORM_data4]   (0x0000003e)
+CHECK:    DW_AT_comp_dir [DW_FORM_strp]     ( .debug_str[0x00000049] = "/Inputs")
+CHECK:   DW_AT_low_pc [DW_FORM_addr]       (0x0000000100000f50)
+CHECK:    DW_TAG_variable [7]
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x00000072] = "private_int")
+CHECK:      DW_AT_type [DW_FORM_ref_addr]   (0x0000000000000063)
+CHECK:      DW_AT_decl_file [DW_FORM_data1] ("/Inputs{{[/\\]}}basic2.c")
+CHECK:      DW_AT_location [DW_FORM_block1] (<0x09> 03 08 10 00 00 01 00 00 00 )
+CHECK:    DW_TAG_variable [7]
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x0000007e] = "baz")
+CHECK:      DW_AT_type [DW_FORM_ref_addr]   (0x0000000000000063)
+CHECK:      DW_AT_location [DW_FORM_block1] (<0x09> 03 00 10 00 00 01 00 00 00 )
+CHECK:    DW_TAG_subprogram [8] *
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x00000082] = "foo")
+CHECK:      DW_AT_type [DW_FORM_ref_addr]   (0x0000000000000063)
+CHECK:      DW_AT_low_pc [DW_FORM_addr]     (0x0000000100000f50)
+CHECK:      DW_AT_high_pc [DW_FORM_addr]    (0x0000000100000f89)
+CHECK:      DW_AT_frame_base [DW_FORM_block1]	(<0x01> 56 )
+CHECK:      DW_TAG_formal_parameter [9]
+CHECK:        DW_AT_name [DW_FORM_strp]     ( .debug_str[0x00000086] = "arg")
+CHECK:        DW_AT_type [DW_FORM_ref_addr] (0x0000000000000063)
+CHECK:        DW_AT_location [DW_FORM_data4]        (0x00000000)
+CHECK:      DW_TAG_inlined_subroutine [10]
+CHECK:        DW_AT_abstract_origin [DW_FORM_ref4]  (cu + 0x00a7 => {0x00000128} "inc")
+CHECK:        DW_AT_low_pc [DW_FORM_addr]   (0x0000000100000f63)
+CHECK:        DW_AT_high_pc [DW_FORM_addr]  (0x0000000100000f72)
+CHECK:        DW_AT_call_line [DW_FORM_data1]	(20)
+CHECK:      NULL
+CHECK:    DW_TAG_subprogram [11]
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x0000008a] = "inc")
+CHECK:      DW_AT_type [DW_FORM_ref_addr]   (0x0000000000000063)
+CHECK:      DW_AT_inline [DW_FORM_data1]	(DW_INL_inlined)
+CHECK:    NULL
+
+CHECK:  Compile Unit:
+
+CHECK:  DW_TAG_compile_unit [1] *
+CHECK:    DW_AT_producer [DW_FORM_strp]     ( .debug_str[0x00000001] = "Apple LLVM version 6.0 (clang-600.0.39) (based on LLVM 3.5svn)")
+CHECK:    DW_AT_name [DW_FORM_strp] ( .debug_str[0x0000008e] = "basic3.c")
+CHECK:    DW_AT_stmt_list [DW_FORM_data4]   (0x0000007e)
+CHECK:    DW_AT_comp_dir [DW_FORM_strp]     ( .debug_str[0x00000049] = "/Inputs")
+CHECK:    DW_AT_low_pc [DW_FORM_addr]       (0x0000000100000f90)
+CHECK:    DW_TAG_variable [12]
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x00000097] = "val")
+CHECK:      DW_AT_type [DW_FORM_ref4]       (cu + 0x003c => {0x00000176})
+CHECK:      DW_AT_decl_file [DW_FORM_data1] ("/Inputs{{[/\\]}}basic3.c")
+CHECK:      DW_AT_location [DW_FORM_block1] (<0x09> 03 04 10 00 00 01 00 00 00 )
+CHECK:    DW_TAG_volatile_type [13]
+CHECK:      DW_AT_type [DW_FORM_ref_addr]   (0x0000000000000063)
+CHECK:    DW_TAG_subprogram [8] *
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x0000009b] = "bar")
+CHECK:      DW_AT_type [DW_FORM_ref_addr]   (0x0000000000000063)
+CHECK:      DW_AT_low_pc [DW_FORM_addr]     (0x0000000100000f90)
+CHECK:      DW_AT_high_pc [DW_FORM_addr]    (0x0000000100000fb4)
+CHECK:      DW_AT_frame_base [DW_FORM_block1]	(<0x01> 56 )
+CHECK:      DW_TAG_formal_parameter [9]
+CHECK:        DW_AT_name [DW_FORM_strp]     ( .debug_str[0x00000086] = "arg")
+CHECK:        DW_AT_type [DW_FORM_ref_addr] (0x0000000000000063)
+CHECK:        DW_AT_location [DW_FORM_data4]        (0x00000025)
+CHECK:      DW_TAG_lexical_block [14] *
+CHECK:        DW_AT_low_pc [DW_FORM_addr]   (0x0000000100000f94)
+CHECK         DW_AT_high_pc [DW_FORM_addr]  (0x0000000100000fa7)
+CHECK:        DW_TAG_inlined_subroutine [15]
+CHECK:          DW_AT_abstract_origin [DW_FORM_ref4]        (cu + 0x009a => {0x000001d4} "inc")
+CHECK:          DW_AT_ranges [DW_FORM_data4]        (0x00000000
+CHECK:             [0x0000000100000f94 - 0x0000000100000f9a)
+CHECK:             [0x0000000100000f9f - 0x0000000100000fa7))
+CHECK:        NULL
+CHECK:      NULL
+CHECK:    DW_TAG_subprogram [11]
+CHECK:      DW_AT_name [DW_FORM_strp]       ( .debug_str[0x0000008a] = "inc")
+CHECK:      DW_AT_type [DW_FORM_ref_addr]   (0x0000000000000063)
+CHECK:    NULL
+
+CHECK:.debug_loc contents:
+CHECK-NEXT: 0x00000000: Beginning address offset: 0x0000000000000000
+CHECK-NEXT:                Ending address offset: 0x000000000000000e
+CHECK-NEXT:                 Location description: 55 93 04 
+CHECK-NEXT: {{^$}}
+CHECK-NEXT: 0x00000025: Beginning address offset: 0x0000000000000000
+CHECK-NEXT:                Ending address offset: 0x000000000000000f
+CHECK-NEXT:                 Location description: 55 93 04 
+CHECK-NEXT: {{^$}}
+CHECK-NEXT:             Beginning address offset: 0x0000000000000019
+CHECK-NEXT:                Ending address offset: 0x000000000000001d
+CHECK-NEXT:                 Location description: 55 93 04 
+
+CHECK: .debug_aranges contents:
+CHECK-NEXT: Address Range Header: length = 0x0000002c, version = 0x0002, cu_offset = 0x00000000, addr_size = 0x08, seg_size = 0x00
+CHECK-NEXT: [0x0000000100000f40 - 0x0000000100000f4b)
+CHECK-NEXT: Address Range Header: length = 0x0000002c, version = 0x0002, cu_offset = 0x00000081, addr_size = 0x08, seg_size = 0x00
+CHECK-NEXT: [0x0000000100000f50 - 0x0000000100000f89)
+CHECK-NEXT: Address Range Header: length = 0x0000002c, version = 0x0002, cu_offset = 0x0000013a, addr_size = 0x08, seg_size = 0x00
+CHECK-NEXT: [0x0000000100000f90 - 0x0000000100000fb4)
+
+
+CHECK: .debug_line contents
+CHECK:                 Dir  Mod Time   File Len   File Name
+CHECK-NEXT:                 ---- ---------- ---------- ---------------------------
+CHECK-NEXT: file_names[  1]    0 0x00000000 0x00000000 basic1.c
+CHECK: Address            Line   Column File   ISA Discriminator Flags
+CHECK-NEXT: ------------------ ------ ------ ------ --- ------------- -------------
+CHECK-NEXT: 0x0000000100000f40     23      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f44     24      0      1   0             0  is_stmt prologue_end
+CHECK-NEXT: 0x0000000100000f4b     24      0      1   0             0  is_stmt end_sequence
+
+CHECK:                 Dir  Mod Time   File Len   File Name
+CHECK-NEXT:                 ---- ---------- ---------- ---------------------------
+CHECK-NEXT: file_names[  1]    0 0x00000000 0x00000000 basic2.c
+CHECK: Address            Line   Column File   ISA Discriminator Flags
+CHECK-NEXT: ------------------ ------ ------ ------ --- ------------- -------------
+CHECK-NEXT: 0x0000000100000f50     19      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f54     20      0      1   0             0  is_stmt prologue_end
+CHECK-NEXT: 0x0000000100000f63     15      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f72     20      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f89     20      0      1   0             0  is_stmt end_sequence
+
+CHECK:                 Dir  Mod Time   File Len   File Name
+CHECK-NEXT:                 ---- ---------- ---------- ---------------------------
+CHECK-NEXT: file_names[  1]    0 0x00000000 0x00000000 basic3.c
+CHECK: Address            Line   Column File   ISA Discriminator Flags
+CHECK-NEXT: ------------------ ------ ------ ------ --- ------------- -------------
+CHECK-NEXT: 0x0000000100000f90     16      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f94     12      0      1   0             0  is_stmt prologue_end
+CHECK-NEXT: 0x0000000100000f9a     17      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000f9f     12      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000fa7     20      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000fa9     19      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000fb2     20      0      1   0             0  is_stmt
+CHECK-NEXT: 0x0000000100000fb4     20      0      1   0             0  is_stmt end_sequence
+
+CHECK: .debug_pubnames contents:
+CHECK-NEXT: length = 0x00000017 version = 0x0002 unit_offset = 0x00000000 unit_size = 0x00000081
+CHECK-NEXT: Offset     Name
+CHECK-NEXT: 0x00000026 "main"
+CHECK-NEXT: length = 0x0000002e version = 0x0002 unit_offset = 0x00000081 unit_size = 0x000000b9
+CHECK-NEXT: Offset     Name
+CHECK-NEXT: 0x00000026 "private_int"
+CHECK-NEXT: 0x0000003f "baz"
+CHECK-NEXT: 0x00000058 "foo"
+CHECK-NEXT: length = 0x0000001e version = 0x0002 unit_offset = 0x0000013a unit_size = 0x000000ac
+CHECK-NEXT: Offset     Name
+CHECK-NEXT: 0x00000026 "val"
+CHECK-NEXT: 0x00000045 "bar"
+
+CHECK: .debug_pubtypes contents:
+CHECK-NEXT: length = 0x0000001f version = 0x0002 unit_offset = 0x00000000 unit_size = 0x00000081
+CHECK-NEXT: Offset     Name
+CHECK-NEXT: 0x00000063 "int"
+CHECK-NEXT: 0x00000079 "char"
diff --git a/test/tools/dsymutil/X86/lit.local.cfg b/test/tools/dsymutil/X86/lit.local.cfg
new file mode 100644
index 000000000000..c8625f4d9d24
--- /dev/null
+++ b/test/tools/dsymutil/X86/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'X86' in config.root.targets:
+    config.unsupported = True
diff --git a/test/tools/dsymutil/basic-linking.test b/test/tools/dsymutil/basic-linking.test
new file mode 100644
index 000000000000..ec6a5b771461
--- /dev/null
+++ b/test/tools/dsymutil/basic-linking.test
@@ -0,0 +1,149 @@
+RUN: llvm-dsymutil -no-output -v -oso-prepend-path=%p %p/Inputs/basic.macho.x86_64 | FileCheck %s
+RUN: llvm-dsymutil -no-output -v -oso-prepend-path=%p %p/Inputs/basic-lto.macho.x86_64 | FileCheck %s --check-prefix=CHECK-LTO
+RUN: llvm-dsymutil -no-output -v -oso-prepend-path=%p %p/Inputs/basic-archive.macho.x86_64 | FileCheck %s --check-prefix=CHECK-ARCHIVE
+
+This test check the basic Dwarf linking process through the debug dumps.
+
+================================= Simple link ================================
+CHECK: DEBUG MAP OBJECT: {{.*}}basic1.macho.x86_64.o
+CHECK: Input compilation unit:
+CHECK-NEXT: TAG_compile_unit
+CHECK-NOT: TAG
+CHECK: AT_name {{.*}}basic1.c
+CHECK-NOT: Found valid debug map entry
+CHECK: Found valid debug map entry: _main 	0000000000000000 => 0000000100000ea0
+CHECK-NEXT: DW_TAG_subprogram
+CHECK-NEXT:   DW_AT_name{{.*}}"main"
+
+CHECK: DEBUG MAP OBJECT: {{.*}}basic2.macho.x86_64.o
+CHECK: Input compilation unit:
+CHECK-NEXT: TAG_compile_unit
+CHECK-NOT: TAG
+CHECK: AT_name {{.*}}basic2.c
+CHECK-NOT: Found valid debug map entry
+CHECK: Found valid debug map entry: _private_int 	0000000000000560 => 0000000100001008
+CHECK-NEXT: DW_TAG_variable
+CHECK-NEXT:   DW_AT_name {{.*}}"private_int"
+CHECK-NOT: Found valid debug map entry
+CHECK: Found valid debug map entry: _baz 	0000000000000310 => 0000000100001000
+CHECK-NEXT: DW_TAG_variable
+CHECK-NEXT:   DW_AT_name {{.*}}"baz"
+CHECK-NOT: Found valid debug map entry
+CHECK: Found valid debug map entry: _foo 	0000000000000020 => 0000000100000ed0
+CHECK-NEXT: DW_TAG_subprogram
+CHECK-NEXT:   DW_AT_name {{.*}}"foo"
+CHECK-NOT: Found valid debug map entry
+CHECK: Found valid debug map entry: _inc 	0000000000000070 => 0000000100000f20
+CHECK-NEXT: DW_TAG_subprogram
+CHECK-NEXT:   DW_AT_name {{.*}}"inc"
+
+CHECK: DEBUG MAP OBJECT: {{.*}}basic3.macho.x86_64.o
+CHECK: Input compilation unit:
+CHECK-NEXT: TAG_compile_unit
+CHECK-NOT: TAG
+CHECK: AT_name {{.*}}basic3.c
+CHECK-NOT: Found valid debug map entry
+CHECK: Found valid debug map entry: _val 	0000000000000004 => 0000000100001004
+CHECK-NEXT: DW_TAG_variable
+CHECK-NEXT:   DW_AT_name {{.*}}"val"
+CHECK-NOT: Found valid debug map entry
+CHECK: Found valid debug map entry: _bar 	0000000000000020 => 0000000100000f40
+CHECK-NEXT: DW_TAG_subprogram
+CHECK-NEXT:   DW_AT_name {{.*}}"bar"
+CHECK-NOT: Found valid debug map entry
+CHECK: Found valid debug map entry: _inc 	0000000000000070 => 0000000100000f90
+CHECK-NEXT: DW_TAG_subprogram
+CHECK-NEXT:   DW_AT_name {{.*}}"inc")
+
+
+================================= LTO link ================================
+CHECK-LTO: DEBUG MAP OBJECT: {{.*}}basic-lto.macho.x86_64.o
+CHECK-LTO: Input compilation unit:
+CHECK-LTO-NEXT: TAG_compile_unit
+CHECK-LTO-NOT: TAG
+CHECK-LTO: AT_name {{.*}}basic1.c
+CHECK-LTO: Input compilation unit:
+CHECK-LTO-NEXT: TAG_compile_unit
+CHECK-LTO-NOT: TAG
+CHECK-LTO: AT_name {{.*}}basic2.c
+CHECK-LTO: Input compilation unit:
+CHECK-LTO-NEXT: TAG_compile_unit
+CHECK-LTO-NOT: TAG
+CHECK-LTO: AT_name {{.*}}basic3.c
+
+CHECK-LTO-NOT: Found valid debug map entry
+CHECK-LTO: Found valid debug map entry: _main 	0000000000000000 => 0000000100000f40
+CHECK-LTO-NEXT: DW_TAG_subprogram
+CHECK-LTO-NEXT:   DW_AT_name {{.*}}"main"
+CHECK-LTO-NOT: Found valid debug map entry
+CHECK-LTO: Found valid debug map entry: _private_int 	00000000000008e8 => 0000000100001008
+CHECK-LTO-NEXT: DW_TAG_variable
+CHECK-LTO-NEXT:   DW_AT_name {{.*}}"private_int"
+CHECK-LTO-NOT: Found valid debug map entry
+CHECK-LTO: Found valid debug map entry: _baz 	0000000000000658 => 0000000100001000
+CHECK-LTO-NEXT: DW_TAG_variable
+CHECK-LTO-NEXT:   DW_AT_name {{.*}} "baz"
+CHECK-LTO-NOT: Found valid debug map entry
+CHECK-LTO: Found valid debug map entry: _foo 	0000000000000010 => 0000000100000f50
+CHECK-LTO-NEXT: DW_TAG_subprogram
+CHECK-LTO-NEXT:   DW_AT_name {{.*}}"foo"
+CHECK-LTO-NOT: Found valid debug map entry
+CHECK-LTO: Found valid debug map entry: _val 	00000000000008ec => 0000000100001004
+CHECK-LTO-NEXT: DW_TAG_variable
+CHECK-LTO-NEXT:   DW_AT_name {{.*}}"val"
+CHECK-LTO-NOT: Found valid debug map entry
+CHECK-LTO: Found valid debug map entry: _bar 	0000000000000050 => 0000000100000f90
+CHECK-LTO-NEXT: DW_TAG_subprogram
+CHECK-LTO-NEXT:   DW_AT_name {{.*}}"bar"
+
+
+================================= Archive link ================================
+CHECK-ARCHIVE: DEBUG MAP OBJECT: {{.*}}basic1.macho.x86_64.o
+CHECK-ARCHIVE: Input compilation unit:
+CHECK-ARCHIVE-NEXT: TAG_compile_unit
+CHECK-ARCHIVE-NOT: TAG
+CHECK-ARCHIVE: AT_name {{.*}}basic1.c
+CHECK-ARCHIVE-NOT: Found valid debug map entry
+CHECK-ARCHIVE: Found valid debug map entry: _main 	0000000000000000 => 0000000100000ea0
+CHECK-ARCHIVE-NEXT: DW_TAG_subprogram
+CHECK-ARCHIVE-NEXT:   DW_AT_name{{.*}}"main"
+
+CHECK-ARCHIVE: DEBUG MAP OBJECT: {{.*}}libbasic.a(basic2.macho.x86_64.o)
+CHECK-ARCHIVE: Input compilation unit:
+CHECK-ARCHIVE-NEXT: TAG_compile_unit
+CHECK-ARCHIVE-NOT: TAG
+CHECK-ARCHIVE: AT_name {{.*}}basic2.c
+CHECK-ARCHIVE-NOT: Found valid debug map entry
+CHECK-ARCHIVE: Found valid debug map entry: _private_int 	0000000000000560 => 0000000100001004
+CHECK-ARCHIVE-NEXT: DW_TAG_variable
+CHECK-ARCHIVE-NEXT:   DW_AT_name {{.*}}"private_int"
+CHECK-ARCHIVE-NOT: Found valid debug map entry
+CHECK-ARCHIVE: Found valid debug map entry: _baz 	0000000000000310 => 0000000100001000
+CHECK-ARCHIVE-NEXT: DW_TAG_variable
+CHECK-ARCHIVE-NEXT:   DW_AT_name {{.*}}"baz"
+CHECK-ARCHIVE-NOT: Found valid debug map entry
+CHECK-ARCHIVE: Found valid debug map entry: _foo 	0000000000000020 => 0000000100000ed0
+CHECK-ARCHIVE-NEXT: DW_TAG_subprogram
+CHECK-ARCHIVE-NEXT:   DW_AT_name {{.*}}"foo"
+CHECK-ARCHIVE-NOT: Found valid debug map entry
+CHECK-ARCHIVE: Found valid debug map entry: _inc 	0000000000000070 => 0000000100000f20
+CHECK-ARCHIVE-NEXT: DW_TAG_subprogram
+CHECK-ARCHIVE-NEXT:   DW_AT_name {{.*}}"inc"
+
+CHECK-ARCHIVE: DEBUG MAP OBJECT: {{.*}}libbasic.a(basic3.macho.x86_64.o)
+CHECK-ARCHIVE: Input compilation unit:
+CHECK-ARCHIVE-NEXT: TAG_compile_unit
+CHECK-ARCHIVE-NOT: TAG
+CHECK-ARCHIVE: AT_name {{.*}}basic3.c
+CHECK-ARCHIVE-NOT: Found valid debug map entry
+CHECK-ARCHIVE: Found valid debug map entry: _val 	0000000000000004 => 0000000100001008
+CHECK-ARCHIVE-NEXT: DW_TAG_variable
+CHECK-ARCHIVE-NEXT:   DW_AT_name {{.*}}"val"
+CHECK-ARCHIVE-NOT: Found valid debug map entry
+CHECK-ARCHIVE: Found valid debug map entry: _bar 	0000000000000020 => 0000000100000f40
+CHECK-ARCHIVE-NEXT: DW_TAG_subprogram
+CHECK-ARCHIVE-NEXT:   DW_AT_name {{.*}}"bar"
+CHECK-ARCHIVE-NOT: Found valid debug map entry
+CHECK-ARCHIVE: Found valid debug map entry: _inc 	0000000000000070 => 0000000100000f90
+CHECK-ARCHIVE-NEXT: DW_TAG_subprogram
+CHECK-ARCHIVE-NEXT:   DW_AT_name {{.*}}"inc")
diff --git a/test/tools/dsymutil/debug-map-parsing.test b/test/tools/dsymutil/debug-map-parsing.test
index f1b310f9b714..3422316191fe 100644
--- a/test/tools/dsymutil/debug-map-parsing.test
+++ b/test/tools/dsymutil/debug-map-parsing.test
@@ -8,32 +8,32 @@ RUN: not llvm-dsymutil -v -parse-only %p/Inputs/inexistant 2>&1 | FileCheck %s -
 Check that We can parse the debug map of the basic executable.
 
 CHECK-NOT: error
-CHECK: DEBUG MAP:
+CHECK: DEBUG MAP: x86_64-unknown-unknown-macho
 CHECK: /Inputs/basic1.macho.x86_64.o:
-CHECK: 	0000000000000000 => 0000000100000ea0	_main
+CHECK: 	0000000000000000 => 0000000100000ea0+0x24	_main
 CHECK: /Inputs/basic2.macho.x86_64.o:
-CHECK: 	0000000000000310 => 0000000100001000	_baz
-CHECK: 	0000000000000020 => 0000000100000ed0	_foo
-CHECK: 	0000000000000070 => 0000000100000f20	_inc
-CHECK: 	0000000000000560 => 0000000100001008	_private_int
+CHECK: 	0000000000000310 => 0000000100001000+0x0	_baz
+CHECK: 	0000000000000020 => 0000000100000ed0+0x50	_foo
+CHECK: 	0000000000000070 => 0000000100000f20+0x17	_inc
+CHECK: 	0000000000000560 => 0000000100001008+0x0	_private_int
 CHECK: /Inputs/basic3.macho.x86_64.o:
-CHECK: 	0000000000000020 => 0000000100000f40	_bar
-CHECK: 	0000000000000070 => 0000000100000f90	_inc
-CHECK: 	0000000000000004 => 0000000100001004	_val
+CHECK: 	0000000000000020 => 0000000100000f40+0x50	_bar
+CHECK: 	0000000000000070 => 0000000100000f90+0x19	_inc
+CHECK: 	0000000000000004 => 0000000100001004+0x0	_val
 CHECK: END DEBUG MAP
 
 
 Check that we can parse the debug-map of the basic-lto executable
 
 CHECK-LTO-NOT: error
-CHECK-LTO: DEBUG MAP:
+CHECK-LTO: DEBUG MAP: x86_64-unknown-unknown-macho
 CHECK-LTO: /Inputs/basic-lto.macho.x86_64.o:
-CHECK-LTO: 	0000000000000050 => 0000000100000f90	_bar
-CHECK-LTO: 	0000000000000658 => 0000000100001000	_baz
-CHECK-LTO: 	0000000000000010 => 0000000100000f50	_foo
-CHECK-LTO: 	0000000000000000 => 0000000100000f40	_main
-CHECK-LTO: 	00000000000008e8 => 0000000100001008	_private_int
-CHECK-LTO: 	00000000000008ec => 0000000100001004	_val
+CHECK-LTO: 	0000000000000050 => 0000000100000f90+0x24	_bar
+CHECK-LTO: 	0000000000000658 => 0000000100001000+0x0	_baz
+CHECK-LTO: 	0000000000000010 => 0000000100000f50+0x40	_foo
+CHECK-LTO: 	0000000000000000 => 0000000100000f40+0x10	_main
+CHECK-LTO: 	00000000000008e8 => 0000000100001008+0x0	_private_int
+CHECK-LTO: 	00000000000008ec => 0000000100001004+0x0	_val
 CHECK-LTO: END DEBUG MAP
 
 Check thet we correctly handle debug maps with archive members (including only
@@ -48,18 +48,19 @@ CHECK-ARCHIVE-NEXT: 	opened new archive {{.*}}/libbasic.a'
 CHECK-ARCHIVE-NEXT: 	found member in current archive.
 CHECK-ARCHIVE-NEXT: trying to open {{.*}}/libbasic.a(basic3.macho.x86_64.o)'
 CHECK-ARCHIVE-NEXT: 	found member in current archive.
-CHECK-ARCHIVE: DEBUG MAP:   object addr =>  executable addr	symbol name
+CHECK-ARCHIVE: DEBUG MAP: x86_64-unknown-unknown-macho
+CHECK-ARCHIVE:       object addr =>  executable addr	symbol name
 CHECK-ARCHIVE: /Inputs/basic1.macho.x86_64.o:
-CHECK-ARCHIVE: 	0000000000000000 => 0000000100000ea0	_main
+CHECK-ARCHIVE: 	0000000000000000 => 0000000100000ea0+0x24	_main
 CHECK-ARCHIVE: /Inputs/./libbasic.a(basic2.macho.x86_64.o):
-CHECK-ARCHIVE: 	0000000000000310 => 0000000100001000	_baz
-CHECK-ARCHIVE: 	0000000000000020 => 0000000100000ed0	_foo
-CHECK-ARCHIVE: 	0000000000000070 => 0000000100000f20	_inc
-CHECK-ARCHIVE: 	0000000000000560 => 0000000100001004	_private_int
+CHECK-ARCHIVE: 	0000000000000310 => 0000000100001000+0x0	_baz
+CHECK-ARCHIVE: 	0000000000000020 => 0000000100000ed0+0x50	_foo
+CHECK-ARCHIVE: 	0000000000000070 => 0000000100000f20+0x17	_inc
+CHECK-ARCHIVE: 	0000000000000560 => 0000000100001004+0x0	_private_int
 CHECK-ARCHIVE: /Inputs/./libbasic.a(basic3.macho.x86_64.o):
-CHECK-ARCHIVE: 	0000000000000020 => 0000000100000f40	_bar
-CHECK-ARCHIVE: 	0000000000000070 => 0000000100000f90	_inc
-CHECK-ARCHIVE: 	0000000000000004 => 0000000100001008	_val
+CHECK-ARCHIVE: 	0000000000000020 => 0000000100000f40+0x50	_bar
+CHECK-ARCHIVE: 	0000000000000070 => 0000000100000f90+0x19	_inc
+CHECK-ARCHIVE: 	0000000000000004 => 0000000100001008+0x0	_val
 CHECK-ARCHIVE: END DEBUG MAP
 
 Check that we warn about missing object files (this presumes that the files aren't
@@ -69,6 +70,7 @@ NOT-FOUND: cannot open{{.*}}"/Inputs/basic1.macho.x86_64.o": {{[Nn]o}} such file
 NOT-FOUND: cannot open{{.*}}"/Inputs/basic2.macho.x86_64.o": {{[Nn]o}} such file
 NOT-FOUND: cannot open{{.*}}"/Inputs/basic3.macho.x86_64.o": {{[Nn]o}} such file
 NOT-FOUND: DEBUG MAP:
+NOT-FOUND-NEXT:  object addr =>  executable addr	symbol name
 NOT-FOUND-NEXT: END DEBUG MAP
 
 Check that we correctly error out on invalid executatble.
diff --git a/test/tools/gold/Inputs/drop-debug.bc b/test/tools/gold/Inputs/drop-debug.bc
new file mode 100644
index 000000000000..f9c471f8e0d1
--- /dev/null
+++ b/test/tools/gold/Inputs/drop-debug.bc
diff --git a/test/tools/gold/alias.ll b/test/tools/gold/alias.ll
index dbf3af57a7b4..b4edb05a4e46 100644
--- a/test/tools/gold/alias.ll
+++ b/test/tools/gold/alias.ll
@@ -1,6 +1,6 @@
 ; RUN: llvm-as %s -o %t.o
 ; RUN: llvm-as %p/Inputs/alias-1.ll -o %t2.o
-; RUN: ld -shared -o %t3.o -plugin %llvmshlibdir/LLVMgold.so %t2.o %t.o \
+; RUN: %gold -shared -o %t3.o -plugin %llvmshlibdir/LLVMgold.so %t2.o %t.o \
 ; RUN:  -plugin-opt=emit-llvm
 ; RUN: llvm-dis < %t3.o -o - | FileCheck %s
 
diff --git a/test/tools/gold/bad-alias.ll b/test/tools/gold/bad-alias.ll
index e0fc788a6123..a98bf710b454 100644
--- a/test/tools/gold/bad-alias.ll
+++ b/test/tools/gold/bad-alias.ll
@@ -1,6 +1,6 @@
 ; RUN: llvm-as %s -o %t.o
 
-; RUN: not ld -plugin %llvmshlibdir/LLVMgold.so \
+; RUN: not %gold -plugin %llvmshlibdir/LLVMgold.so \
 ; RUN:    --plugin-opt=emit-llvm \
 ; RUN:    -shared %t.o -o %t2.o 2>&1 | FileCheck %s
 
diff --git a/test/tools/gold/bcsection.ll b/test/tools/gold/bcsection.ll
index 8565d9ddc4c1..37d2994cc780 100644
--- a/test/tools/gold/bcsection.ll
+++ b/test/tools/gold/bcsection.ll
@@ -2,7 +2,7 @@
 
 ; RUN: llvm-mc -I=%T -filetype=obj -o %T/bcsection.bco %p/Inputs/bcsection.s
 ; RUN: llvm-nm -no-llvm-bc %T/bcsection.bco | count 0
-; RUN: ld -r -o %T/bcsection.o -plugin %llvmshlibdir/LLVMgold.so %T/bcsection.bco
+; RUN: %gold -r -o %T/bcsection.o -plugin %llvmshlibdir/LLVMgold.so %T/bcsection.bco
 ; RUN: llvm-nm -no-llvm-bc %T/bcsection.o | FileCheck %s
 
 ; CHECK: main
diff --git a/test/tools/gold/coff.ll b/test/tools/gold/coff.ll
index b66f028a14d8..5d8a1c9da5fc 100644
--- a/test/tools/gold/coff.ll
+++ b/test/tools/gold/coff.ll
@@ -1,5 +1,5 @@
 ; RUN: llvm-as %s -o %t.o
-; RUN: ld      -plugin %llvmshlibdir/LLVMgold.so -plugin-opt=emit-llvm \
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so -plugin-opt=emit-llvm \
 ; RUN:    -shared %t.o -o %t2.o
 ; RUN: llvm-dis %t2.o -o - | FileCheck %s
 
diff --git a/test/tools/gold/comdat.ll b/test/tools/gold/comdat.ll
index 2edd7822c91a..370bf5641f31 100644
--- a/test/tools/gold/comdat.ll
+++ b/test/tools/gold/comdat.ll
@@ -1,6 +1,6 @@
 ; RUN: llvm-as %s -o %t.o
 ; RUN: llvm-as %p/Inputs/comdat.ll -o %t2.o
-; RUN: ld -shared -o %t3.o -plugin %llvmshlibdir/LLVMgold.so %t.o %t2.o \
+; RUN: %gold -shared -o %t3.o -plugin %llvmshlibdir/LLVMgold.so %t.o %t2.o \
 ; RUN:  -plugin-opt=emit-llvm
 ; RUN: llvm-dis %t3.o -o - | FileCheck %s
 
diff --git a/test/tools/gold/common.ll b/test/tools/gold/common.ll
index f3092310a1da..ef18e6831045 100644
--- a/test/tools/gold/common.ll
+++ b/test/tools/gold/common.ll
@@ -1,7 +1,7 @@
 ; RUN: llvm-as %s -o %t1.o
 ; RUN: llvm-as %p/Inputs/common.ll -o %t2.o
 
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so \
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so \
 ; RUN:    --plugin-opt=emit-llvm \
 ; RUN:    -shared %t1.o %t2.o -o %t3.o
 ; RUN: llvm-dis %t3.o -o - | FileCheck %s
@@ -11,7 +11,7 @@
 ; Shared library case, we merge @a as common and keep it for the symbol table.
 ; CHECK: @a = common global i16 0, align 8
 
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so \
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so \
 ; RUN:    --plugin-opt=emit-llvm \
 ; RUN:    %t1.o %t2.o -o %t3.o
 ; RUN: llvm-dis %t3.o -o - | FileCheck --check-prefix=EXEC %s
@@ -20,7 +20,7 @@
 ; EXEC: @a = internal global i16 0, align 8
 
 ; RUN: llc %p/Inputs/common.ll -o %t2.o -filetype=obj
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so \
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so \
 ; RUN:    --plugin-opt=emit-llvm \
 ; RUN:    %t1.o %t2.o -o %t3.o
 ; RUN: llvm-dis %t3.o -o - | FileCheck --check-prefix=MIXED %s
diff --git a/test/tools/gold/drop-debug.ll b/test/tools/gold/drop-debug.ll
new file mode 100644
index 000000000000..b8c4d8c62a9b
--- /dev/null
+++ b/test/tools/gold/drop-debug.ll
@@ -0,0 +1,8 @@
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so \
+; RUN:    --plugin-opt=emit-llvm -shared %p/Inputs/drop-debug.bc \
+; RUN:    -o t2.bc 2>&1 | FileCheck %s
+
+; drop-debug.bc was created from "void f(void) {}" with clang 3.5 and
+; -gline-tables-only, so it contains old debug info.
+
+; CHECK: warning: LLVM gold plugin: ignoring debug info with an invalid version (1) in {{.*}}/Inputs/drop-debug.bc
diff --git a/test/tools/gold/emit-llvm.ll b/test/tools/gold/emit-llvm.ll
index 2c43147a2eab..f851fbfb5e02 100644
--- a/test/tools/gold/emit-llvm.ll
+++ b/test/tools/gold/emit-llvm.ll
@@ -1,20 +1,20 @@
 ; RUN: llvm-as %s -o %t.o
 
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so \
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so \
 ; RUN:    --plugin-opt=emit-llvm \
 ; RUN:    --plugin-opt=generate-api-file \
 ; RUN:    -shared %t.o -o %t2.o
 ; RUN: llvm-dis %t2.o -o - | FileCheck %s
 ; RUN: FileCheck --check-prefix=API %s < %T/../apifile.txt
 
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so \
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so \
 ; RUN:     -m elf_x86_64 --plugin-opt=save-temps \
 ; RUN:    -shared %t.o -o %t3.o
 ; RUN: llvm-dis %t3.o.bc -o - | FileCheck %s
 ; RUN: llvm-dis %t3.o.opt.bc -o - | FileCheck --check-prefix=OPT %s
 
 ; RUN: rm -f %t4.o
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so \
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so \
 ; RUN:     -m elf_x86_64 --plugin-opt=disable-output \
 ; RUN:    -shared %t.o -o %t4.o
 ; RUN: not test -a %t4.o
diff --git a/test/tools/gold/invalid.ll b/test/tools/gold/invalid.ll
index 8db76446a3d7..858cd47adbed 100644
--- a/test/tools/gold/invalid.ll
+++ b/test/tools/gold/invalid.ll
@@ -1,4 +1,4 @@
-; RUN: not ld -plugin %llvmshlibdir/LLVMgold.so \
+; RUN: not %gold -plugin %llvmshlibdir/LLVMgold.so \
 ; RUN:    %p/Inputs/invalid.bc -o %t2 2>&1 | FileCheck %s
 
 ; test that only one error gets printed
diff --git a/test/tools/gold/linker-script.ll b/test/tools/gold/linker-script.ll
index 35a769453e57..7c88b0ffd5fb 100644
--- a/test/tools/gold/linker-script.ll
+++ b/test/tools/gold/linker-script.ll
@@ -1,6 +1,6 @@
 ; RUN: llvm-as %s -o %t.o
 
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so \
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so \
 ; RUN:    --plugin-opt=emit-llvm \
 ; RUN:    -shared %t.o -o %t2.o \
 ; RUN:    -version-script=%p/Inputs/linker-script.export
diff --git a/test/tools/gold/linkonce-weak.ll b/test/tools/gold/linkonce-weak.ll
index 765275b09d50..a0cccea56cfe 100644
--- a/test/tools/gold/linkonce-weak.ll
+++ b/test/tools/gold/linkonce-weak.ll
@@ -1,12 +1,12 @@
 ; RUN: llvm-as %s -o %t.o
 ; RUN: llvm-as %p/Inputs/linkonce-weak.ll -o %t2.o
 
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so \
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so \
 ; RUN:    --plugin-opt=emit-llvm \
 ; RUN:    -shared %t.o %t2.o -o %t3.o
 ; RUN: llvm-dis %t3.o -o - | FileCheck %s
 
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so \
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so \
 ; RUN:    --plugin-opt=emit-llvm \
 ; RUN:    -shared %t2.o %t.o -o %t3.o
 ; RUN: llvm-dis %t3.o -o - | FileCheck %s
diff --git a/test/tools/gold/mtriple.ll b/test/tools/gold/mtriple.ll
index 6395af6f1ab9..87b226014cab 100644
--- a/test/tools/gold/mtriple.ll
+++ b/test/tools/gold/mtriple.ll
@@ -1,5 +1,7 @@
+; REQUIRES: ld_emu_elf32ppc
+
 ; RUN: llvm-as %s -o %t.o
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so -m elf32ppc \
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so -m elf32ppc \
 ; RUN:    -plugin-opt=mtriple=powerpc-linux-gnu \
 ; RUN:    -plugin-opt=obj-path=%t3.o \
 ; RUN:    -shared %t.o -o %t2
diff --git a/test/tools/gold/no-map-whole-file.ll b/test/tools/gold/no-map-whole-file.ll
index 21a0c46d28b0..4c261d70a249 100644
--- a/test/tools/gold/no-map-whole-file.ll
+++ b/test/tools/gold/no-map-whole-file.ll
@@ -1,5 +1,5 @@
 ; RUN: llvm-as -o %t.bc %s
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so -plugin-opt=emit-llvm \
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so -plugin-opt=emit-llvm \
 ; RUN:    --no-map-whole-files -r -o %t2.bc %t.bc
 ; RUN: llvm-dis < %t2.bc -o - | FileCheck %s
 
diff --git a/test/tools/gold/opt-level.ll b/test/tools/gold/opt-level.ll
new file mode 100644
index 000000000000..3deb0af37a74
--- /dev/null
+++ b/test/tools/gold/opt-level.ll
@@ -0,0 +1,50 @@
+; RUN: llvm-as -o %t.bc %s
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so -plugin-opt=save-temps \
+; RUN:    -plugin-opt=O0 -r -o %t.o %t.bc
+; RUN: llvm-dis < %t.o.opt.bc -o - | FileCheck --check-prefix=CHECK-O0 %s
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so -plugin-opt=save-temps \
+; RUN:    -plugin-opt=O1 -r -o %t.o %t.bc
+; RUN: llvm-dis < %t.o.opt.bc -o - | FileCheck --check-prefix=CHECK-O1 %s
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so -plugin-opt=save-temps \
+; RUN:    -plugin-opt=O2 -r -o %t.o %t.bc
+; RUN: llvm-dis < %t.o.opt.bc -o - | FileCheck --check-prefix=CHECK-O2 %s
+
+; CHECK-O0: define internal void @foo(
+; CHECK-O1: define internal void @foo(
+; CHECK-O2-NOT: define internal void @foo(
+define internal void @foo() {
+  ret void
+}
+
+; CHECK-O0: define internal i32 @bar(
+; CHECK-O1: define internal i32 @bar(
+define internal i32 @bar(i1 %p) {
+  br i1 %p, label %t, label %f
+
+t:
+  br label %end
+
+f:
+  br label %end
+
+end:
+  ; CHECK-O0: phi
+  ; CHECK-O1: select
+  %r = phi i32 [ 1, %t ], [ 2, %f ]
+  ret i32 %r
+}
+
+define void @baz() {
+  call void @foo()
+  %c = call i32 @bar(i1 true)
+  ret void
+}
+
+@a = constant i32 1
+
+!0 = !{!"bitset1", i32* @a, i32 0}
+
+; CHECK-O0-NOT: llvm.bitsets
+; CHECK-O1-NOT: llvm.bitsets
+; CHECK-O2-NOT: llvm.bitsets
+!llvm.bitsets = !{ !0 }
diff --git a/test/tools/gold/option.ll b/test/tools/gold/option.ll
deleted file mode 100644
index 8154e435b4ed..000000000000
--- a/test/tools/gold/option.ll
+++ /dev/null
@@ -1,39 +0,0 @@
-; RUN: llvm-as %s -o %t.o
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so -m elf_x86_64 \
-; RUN:    --plugin-opt=-jump-table-type=arity \
-; RUN:    --plugin-opt=-mattr=+aes \
-; RUN:    --plugin-opt=mcpu=core-avx2 \
-; RUN:    -shared %t.o -o %t2.o
-; RUN: llvm-nm %t2.o | FileCheck %s
-
-; CHECK: t __llvm_jump_instr_table_0_1
-; CHECK: t __llvm_jump_instr_table_1_1
-
-target triple = "x86_64-unknown-linux-gnu"
-define i32 @g(i32 %a) unnamed_addr jumptable {
-  ret i32 %a
-}
-
-define i32 (i32)* @get_g() {
-  ret i32 (i32)* @g
-}
-
-define i32 @f() unnamed_addr jumptable {
-  ret i32 0
-}
-
-define i32 ()* @get_f() {
-  ret i32 ()* @f
-}
-
-define <2 x i64> @test_aes(<2 x i64> %a0, <2 x i64> %a1) {
-  %res = call <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64> %a0, <2 x i64> %a1)
-  ret <2 x i64> %res
-}
-declare <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64>, <2 x i64>) nounwind readnone
-
-define <32 x i8> @test_avx2(<16 x i16> %a0, <16 x i16> %a1) {
-  %res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %a0, <16 x i16> %a1)
-  ret <32 x i8> %res
-}
-declare <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16>, <16 x i16>) nounwind readnone
diff --git a/test/tools/gold/pr19901.ll b/test/tools/gold/pr19901.ll
index 304246bca47a..71bb134ead7b 100644
--- a/test/tools/gold/pr19901.ll
+++ b/test/tools/gold/pr19901.ll
@@ -1,6 +1,7 @@
 ; RUN: llc %s -o %t.o -filetype=obj -relocation-model=pic
 ; RUN: llvm-as %p/Inputs/pr19901-1.ll -o %t2.o
-; RUN: ld -shared -o %t.so -plugin %llvmshlibdir/LLVMgold.so %t2.o %t.o
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so \
+; RUN:     -shared -m elf_x86_64 -o %t.so %t2.o %t.o
 ; RUN: llvm-readobj -t %t.so | FileCheck %s
 
 ; CHECK:       Symbol {
@@ -9,7 +10,7 @@
 ; CHECK-NEXT:    Size:
 ; CHECK-NEXT:    Binding: Local
 ; CHECK-NEXT:    Type: Function
-; CHECK-NEXT:    Other: 2
+; CHECK-NEXT:    Other: {{2|0}}
 ; CHECK-NEXT:    Section: .text
 ; CHECK-NEXT:  }
 
diff --git a/test/tools/gold/remarks.ll b/test/tools/gold/remarks.ll
new file mode 100644
index 000000000000..c4fa7f787f26
--- /dev/null
+++ b/test/tools/gold/remarks.ll
@@ -0,0 +1,22 @@
+; RUN: llvm-as %s -o %t.o
+
+; RUN: %gold -m elf_x86_64 -plugin %llvmshlibdir/LLVMgold.so \
+; RUN:    -plugin-opt=-pass-remarks=inline %t.o -o %t2.o 2>&1 | FileCheck %s
+
+; RUN: %gold -m elf_x86_64 -plugin %llvmshlibdir/LLVMgold.so \
+; RUN:   %t.o -o %t2.o 2>&1 | FileCheck -allow-empty --check-prefix=NO-REMARK %s
+
+
+; CHECK: f inlined into _start
+; NO-REMARK-NOT: inlined
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define i32 @f() {
+  ret i32 0
+}
+
+define i32 @_start() {
+  %call = call i32 @f()
+  ret i32 %call
+}
diff --git a/test/tools/gold/slp-vectorize.ll b/test/tools/gold/slp-vectorize.ll
index d378902e32f6..a75f0b38cc1f 100644
--- a/test/tools/gold/slp-vectorize.ll
+++ b/test/tools/gold/slp-vectorize.ll
@@ -1,6 +1,6 @@
 ; RUN: llvm-as %s -o %t.o
 
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so \
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so \
 ; RUN:    --plugin-opt=save-temps \
 ; RUN:    -shared %t.o -o %t2.o
 ; RUN: llvm-dis %t2.o.opt.bc -o - | FileCheck %s
@@ -11,19 +11,19 @@
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 
 define void @f(float* nocapture %x) {
-  %tmp = load float* %x, align 4
+  %tmp = load float, float* %x, align 4
   %add = fadd float %tmp, 1.000000e+00
   store float %add, float* %x, align 4
-  %arrayidx1 = getelementptr inbounds float* %x, i64 1
-  %tmp1 = load float* %arrayidx1, align 4
+  %arrayidx1 = getelementptr inbounds float, float* %x, i64 1
+  %tmp1 = load float, float* %arrayidx1, align 4
   %add2 = fadd float %tmp1, 1.000000e+00
   store float %add2, float* %arrayidx1, align 4
-  %arrayidx3 = getelementptr inbounds float* %x, i64 2
-  %tmp2 = load float* %arrayidx3, align 4
+  %arrayidx3 = getelementptr inbounds float, float* %x, i64 2
+  %tmp2 = load float, float* %arrayidx3, align 4
   %add4 = fadd float %tmp2, 1.000000e+00
   store float %add4, float* %arrayidx3, align 4
-  %arrayidx5 = getelementptr inbounds float* %x, i64 3
-  %tmp3 = load float* %arrayidx5, align 4
+  %arrayidx5 = getelementptr inbounds float, float* %x, i64 3
+  %tmp3 = load float, float* %arrayidx5, align 4
   %add6 = fadd float %tmp3, 1.000000e+00
   store float %add6, float* %arrayidx5, align 4
   ret void
diff --git a/test/tools/gold/stats.ll b/test/tools/gold/stats.ll
index 7c353e6ab2a6..b3c829798df2 100644
--- a/test/tools/gold/stats.ll
+++ b/test/tools/gold/stats.ll
@@ -1,7 +1,7 @@
 ; REQUIRES: asserts
 
 ; RUN: llvm-as %s -o %t.o
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so  -shared \
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so  -shared \
 ; RUN:    -plugin-opt=-stats %t.o -o %t2 2>&1 | FileCheck %s
 
 ; CHECK: Statistics Collected
diff --git a/test/tools/gold/vectorize.ll b/test/tools/gold/vectorize.ll
index 3d305db1e31b..5f003dd02e21 100644
--- a/test/tools/gold/vectorize.ll
+++ b/test/tools/gold/vectorize.ll
@@ -1,6 +1,6 @@
 ; RUN: llvm-as %s -o %t.o
 
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so \
+; RUN: %gold -m elf_x86_64 -plugin %llvmshlibdir/LLVMgold.so \
 ; RUN:    --plugin-opt=save-temps \
 ; RUN:    -shared %t.o -o %t2.o
 ; RUN: llvm-dis %t2.o.opt.bc -o - | FileCheck %s
@@ -17,8 +17,8 @@ bb:
 
 bb1:
   %i.0 = phi i64 [ 0, %bb ], [ %tmp4, %bb1 ]
-  %tmp = getelementptr inbounds float* %x, i64 %i.0
-  %tmp2 = load float* %tmp, align 4
+  %tmp = getelementptr inbounds float, float* %x, i64 %i.0
+  %tmp2 = load float, float* %tmp, align 4
   %tmp3 = fadd float %tmp2, 1.000000e+00
   store float %tmp3, float* %tmp, align 4
   %tmp4 = add nsw i64 %i.0, 1
diff --git a/test/tools/gold/weak.ll b/test/tools/gold/weak.ll
index e05e905cc140..6d8d7a871f1b 100644
--- a/test/tools/gold/weak.ll
+++ b/test/tools/gold/weak.ll
@@ -1,7 +1,7 @@
 ; RUN: llvm-as %s -o %t.o
 ; RUN: llvm-as %p/Inputs/weak.ll -o %t2.o
 
-; RUN: ld -plugin %llvmshlibdir/LLVMgold.so \
+; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so \
 ; RUN:    --plugin-opt=emit-llvm \
 ; RUN:    -shared %t.o %t2.o -o %t3.o
 ; RUN: llvm-dis %t3.o -o - | FileCheck %s
diff --git a/test/tools/llvm-cov/Inputs/binary-formats.macho32b b/test/tools/llvm-cov/Inputs/binary-formats.macho32b
new file mode 100755
index 000000000000..bb9f356c9dc4
--- /dev/null
+++ b/test/tools/llvm-cov/Inputs/binary-formats.macho32b
diff --git a/test/tools/llvm-cov/Inputs/binary-formats.macho32l b/test/tools/llvm-cov/Inputs/binary-formats.macho32l
new file mode 100755
index 000000000000..2dd4c44866b0
--- /dev/null
+++ b/test/tools/llvm-cov/Inputs/binary-formats.macho32l
diff --git a/test/tools/llvm-cov/Inputs/binary-formats.macho64l b/test/tools/llvm-cov/Inputs/binary-formats.macho64l
new file mode 100755
index 000000000000..0045c4355750
--- /dev/null
+++ b/test/tools/llvm-cov/Inputs/binary-formats.macho64l
diff --git a/test/tools/llvm-cov/Inputs/binary-formats.proftext b/test/tools/llvm-cov/Inputs/binary-formats.proftext
new file mode 100644
index 000000000000..97816c29f360
--- /dev/null
+++ b/test/tools/llvm-cov/Inputs/binary-formats.proftext
@@ -0,0 +1,4 @@
+main
+0x0
+1
+100
diff --git a/test/tools/llvm-cov/Inputs/highlightedRanges.covmapping b/test/tools/llvm-cov/Inputs/highlightedRanges.covmapping
index 20eb0d7e8df5..e97320b7855d 100644
--- a/test/tools/llvm-cov/Inputs/highlightedRanges.covmapping
+++ b/test/tools/llvm-cov/Inputs/highlightedRanges.covmapping
diff --git a/test/tools/llvm-cov/Inputs/lineExecutionCounts.profdata b/test/tools/llvm-cov/Inputs/lineExecutionCounts.profdata
deleted file mode 100644
index 871222723967..000000000000
--- a/test/tools/llvm-cov/Inputs/lineExecutionCounts.profdata
+++ /dev/null
diff --git a/test/tools/llvm-cov/Inputs/lineExecutionCounts.proftext b/test/tools/llvm-cov/Inputs/lineExecutionCounts.proftext
new file mode 100644
index 000000000000..38387a6237ab
--- /dev/null
+++ b/test/tools/llvm-cov/Inputs/lineExecutionCounts.proftext
@@ -0,0 +1,8 @@
+main
+0x000000000028434d
+5
+161
+0
+16100
+161
+0
diff --git a/test/tools/llvm-cov/Inputs/regionMarkers.covmapping b/test/tools/llvm-cov/Inputs/regionMarkers.covmapping
index 3ebcb0777af3..501cba2b734a 100644
--- a/test/tools/llvm-cov/Inputs/regionMarkers.covmapping
+++ b/test/tools/llvm-cov/Inputs/regionMarkers.covmapping
diff --git a/test/tools/llvm-cov/Inputs/regionMarkers.profdata b/test/tools/llvm-cov/Inputs/regionMarkers.profdata
deleted file mode 100644
index 871222723967..000000000000
--- a/test/tools/llvm-cov/Inputs/regionMarkers.profdata
+++ /dev/null
diff --git a/test/tools/llvm-cov/Inputs/regionMarkers.proftext b/test/tools/llvm-cov/Inputs/regionMarkers.proftext
new file mode 100644
index 000000000000..5199edc53948
--- /dev/null
+++ b/test/tools/llvm-cov/Inputs/regionMarkers.proftext
@@ -0,0 +1,8 @@
+main
+0x000000000028434d
+5
+1111000
+0
+111100000
+1111000
+0
diff --git a/test/tools/llvm-cov/Inputs/report.covmapping b/test/tools/llvm-cov/Inputs/report.covmapping
index 32d84bc7273a..5d0bfc116816 100644
--- a/test/tools/llvm-cov/Inputs/report.covmapping
+++ b/test/tools/llvm-cov/Inputs/report.covmapping
diff --git a/test/tools/llvm-cov/Inputs/showExpansions.covmapping b/test/tools/llvm-cov/Inputs/showExpansions.covmapping
index b8c7d9711afe..e02a7281b000 100644
--- a/test/tools/llvm-cov/Inputs/showExpansions.covmapping
+++ b/test/tools/llvm-cov/Inputs/showExpansions.covmapping
diff --git a/test/tools/llvm-cov/Inputs/universal-binary b/test/tools/llvm-cov/Inputs/universal-binary
new file mode 100755
index 000000000000..aad5758332f6
--- /dev/null
+++ b/test/tools/llvm-cov/Inputs/universal-binary
diff --git a/test/tools/llvm-cov/Inputs/universal-binary.proftext b/test/tools/llvm-cov/Inputs/universal-binary.proftext
new file mode 100644
index 000000000000..97816c29f360
--- /dev/null
+++ b/test/tools/llvm-cov/Inputs/universal-binary.proftext
@@ -0,0 +1,4 @@
+main
+0x0
+1
+100
diff --git a/test/tools/llvm-cov/binary-formats.c b/test/tools/llvm-cov/binary-formats.c
new file mode 100644
index 000000000000..31c6c4c3bf4d
--- /dev/null
+++ b/test/tools/llvm-cov/binary-formats.c
@@ -0,0 +1,9 @@
+// Checks for reading various formats.
+
+// CHECK: 100| [[@LINE+1]]|int main
+int main(int argc, const char *argv[]) {}
+
+// RUN: llvm-profdata merge %S/Inputs/binary-formats.proftext -o %t.profdata
+// RUN: llvm-cov show %S/Inputs/binary-formats.macho32l -instr-profile %t.profdata -filename-equivalence %s | FileCheck %s
+// RUN: llvm-cov show %S/Inputs/binary-formats.macho64l -instr-profile %t.profdata -filename-equivalence %s | FileCheck %s
+// RUN: llvm-cov show %S/Inputs/binary-formats.macho32b -instr-profile %t.profdata -filename-equivalence %s | FileCheck %s
diff --git a/test/tools/llvm-cov/copy_block_helper.m b/test/tools/llvm-cov/copy_block_helper.m
index 64973f11009a..d8202d085b20 100644
--- a/test/tools/llvm-cov/copy_block_helper.m
+++ b/test/tools/llvm-cov/copy_block_helper.m
@@ -9,7 +9,7 @@
 // RUN: cd %t
 // RUN: cp %s %p/Inputs/copy_block_helper.gc* .
 
-// RUN: llvm-cov copy_block_helper.m | FileCheck %s --check-prefix=STDOUT
+// RUN: llvm-cov gcov copy_block_helper.m | FileCheck %s --check-prefix=STDOUT
 // STDOUT: File 'copy_block_helper.m'
 // STDOUT: Lines executed:100.00% of 5
 // STDOUT: copy_block_helper.m:creating 'copy_block_helper.m.gcov'
diff --git a/test/tools/llvm-cov/lit.local.cfg b/test/tools/llvm-cov/lit.local.cfg
index 650bc02747b5..05aef8645e4d 100644
--- a/test/tools/llvm-cov/lit.local.cfg
+++ b/test/tools/llvm-cov/lit.local.cfg
@@ -1,5 +1 @@
-config.suffixes = ['.test', '.m', '.cpp']
-
-# http://llvm.org/bugs/show_bug.cgi?id=20979
-if 'ubsan' in config.available_features:
-  config.unsupported = True
+config.suffixes = ['.test', '.m', '.cpp', '.c']
diff --git a/test/tools/llvm-cov/llvm-cov.test b/test/tools/llvm-cov/llvm-cov.test
index bce80d2e2778..ba5e18a91061 100644
--- a/test/tools/llvm-cov/llvm-cov.test
+++ b/test/tools/llvm-cov/llvm-cov.test
@@ -1,7 +1,8 @@
 # Tests for compatibility between llvm-cov and gcov. These work by
 # comparing llvm-cov against reference outputs generated by gcov 4.2.
 
-# "cd" and globbing are unsupported in lit internal runner.
+# Test fails on Windows where internal shell is used due to path separator
+# mismatches.
 REQUIRES: shell
 
 RUN: rm -rf %t
@@ -10,70 +11,70 @@ RUN: cd %t
 RUN: cp %p/Inputs/test* .
 
 # Basic behaviour with no flags
-RUN: llvm-cov test.c | diff -u test_no_options.output -
+RUN: llvm-cov gcov test.c | diff -u test_no_options.output -
 RUN: diff -aub test_no_options.cpp.gcov test.cpp.gcov
 RUN: diff -aub test_no_options.h.gcov test.h.gcov
 
 # Same, but specifying the object directory
 RUN: mkdir -p %t/objdir
 RUN: cp test.gcno test.gcda %t/objdir
-RUN: llvm-cov -o objdir test.c | diff -u test_no_options.output -
+RUN: llvm-cov gcov -o objdir test.c | diff -u test_no_options.output -
 RUN: diff -aub test_objdir.cpp.gcov test.cpp.gcov
 RUN: diff -aub test_objdir.h.gcov test.h.gcov
 
 # Specifying an object file
-RUN: llvm-cov -o objdir/test.o test.c | diff -u test_no_options.output -
+RUN: llvm-cov gcov -o objdir/test.o test.c | diff -u test_no_options.output -
 RUN: diff -aub test_objdir.cpp.gcov test.cpp.gcov
 RUN: diff -aub test_objdir.h.gcov test.h.gcov
 
 # Specifying an object file that could be ambiguous with a directory
-RUN: llvm-cov -o objdir/test test.c | diff -u test_no_options.output -
+RUN: llvm-cov gcov -o objdir/test test.c | diff -u test_no_options.output -
 RUN: diff -aub test_objdir.cpp.gcov test.cpp.gcov
 RUN: diff -aub test_objdir.h.gcov test.h.gcov
 
 # With gcov output disabled
-RUN: llvm-cov -n test.c | diff -u test_no_output.output -
+RUN: llvm-cov gcov -n test.c | diff -u test_no_output.output -
 
 # Missing source files. This test is fragile, as it depends on being
 # run before we copy some sources into place in the next test.
-RUN: llvm-cov test_paths.cpp 2>/dev/null | diff -u test_missing.output -
+RUN: llvm-cov gcov test_paths.cpp 2>/dev/null | diff -u test_missing.output -
 RUN: diff -aub test_missing.cpp.gcov test.cpp.gcov
 RUN: diff -aub test_missing.h.gcov test.h.gcov
 
 # Preserve paths. This mangles the output filenames.
 RUN: mkdir -p %t/srcdir/nested_dir
 RUN: cp test.cpp test.h %t/srcdir
-RUN: llvm-cov -p test_paths.cpp | diff -u test_preserve_paths.output -
+RUN: llvm-cov gcov -p test_paths.cpp | diff -u test_preserve_paths.output -
 RUN: diff -aub test_paths.cpp.gcov srcdir#nested_dir#^#test.cpp.gcov
 RUN: diff -aub test_paths.h.gcov srcdir#nested_dir#^#test.h.gcov
 
 # Don't preserve paths. Same results as preserve paths, but no mangling.
-RUN: llvm-cov test_paths.cpp | diff -u test_no_preserve_paths.output -
+RUN: llvm-cov gcov test_paths.cpp | diff -u test_no_preserve_paths.output -
 RUN: diff -aub test_paths.cpp.gcov test.cpp.gcov
 RUN: diff -aub test_paths.h.gcov test.h.gcov
 
 # Long file names.
-RUN: llvm-cov -l test_paths.cpp | diff -u test_long_file_names.output -
+RUN: llvm-cov gcov -l test_paths.cpp | diff -u test_long_file_names.output -
 RUN: diff -aub test_paths.cpp.gcov test_paths.cpp##test.cpp.gcov
 RUN: diff -aub test_paths.h.gcov test_paths.cpp##test.h.gcov
 
 # Long file names and preserve paths.
-RUN: llvm-cov -lp -gcno test_paths.gcno -gcda test_paths.gcda srcdir/../test_paths.cpp | diff -u test_long_paths.output -
+RUN: llvm-cov gcov -lp -gcno test_paths.gcno -gcda test_paths.gcda srcdir/../test_paths.cpp | diff -u test_long_paths.output -
 RUN: diff -aub test_paths.cpp.gcov srcdir#^#test_paths.cpp##srcdir#nested_dir#^#test.cpp.gcov
 RUN: diff -aub test_paths.h.gcov srcdir#^#test_paths.cpp##srcdir#nested_dir#^#test.h.gcov
 
 # Function summaries. This changes stdout, but not the gcov files.
-RUN: llvm-cov test.c -f | diff -u test_-f.output -
+RUN: llvm-cov gcov test.c -f | diff -u test_-f.output -
 RUN: diff -aub test_no_options.cpp.gcov test.cpp.gcov
 RUN: diff -aub test_no_options.h.gcov test.h.gcov
 
 # All blocks. This doesn't affect stdout, only the gcov files.
-RUN: llvm-cov test.c -a | diff -u test_no_options.output -
+RUN: llvm-cov gcov test.c -a | diff -u test_no_options.output -
 RUN: diff -aub test_-a.cpp.gcov test.cpp.gcov
 RUN: diff -aub test_-a.h.gcov test.h.gcov
 
 # Branch probabilities.
-RUN: llvm-cov test.c -a -b | diff -u test_-b.output -
+RUN: llvm-cov gcov test.c -a -b | diff -u test_-b.output -
 RUN: diff -aub test_-a_-b.cpp.gcov test.cpp.gcov
 RUN: diff -aub test_-a_-b.h.gcov test.h.gcov
 
@@ -82,36 +83,36 @@ RUN: diff -aub test_-a_-b.h.gcov test.h.gcov
 # FIXME: We don't correctly handle calls when -b and -f are used
 # together, so our output differs from gcov. Remove the 'not' from
 # this test once this is fixed.
-RUN: llvm-cov test.c -a -b -f | not diff -u test_-b_-f.output - >/dev/null
+RUN: llvm-cov gcov test.c -a -b -f | not diff -u test_-b_-f.output - >/dev/null
 RUN: diff -aub test_-a_-b.cpp.gcov test.cpp.gcov
 RUN: diff -aub test_-a_-b.h.gcov test.h.gcov
 
 # Summarize unconditional branches too.
-RUN: llvm-cov test.c -a -b -u | diff -u test_-b.output -
+RUN: llvm-cov gcov test.c -a -b -u | diff -u test_-b.output -
 RUN: diff -aub test_-a_-b_-u.cpp.gcov test.cpp.gcov
 RUN: diff -aub test_-a_-b_-u.h.gcov test.h.gcov
 
 # Absolute counts for branches.
-RUN: llvm-cov test.c -a -b -c -u | diff -u test_-b.output -
+RUN: llvm-cov gcov test.c -a -b -c -u | diff -u test_-b.output -
 RUN: diff -aub test_-a_-b_-c_-u.cpp.gcov test.cpp.gcov
 RUN: diff -aub test_-a_-b_-c_-u.h.gcov test.h.gcov
 
 # Missing gcda file just gives 0 counts.
-RUN: llvm-cov test.c -gcda=no_such_gcda_file | diff -u test_no_gcda.output -
+RUN: llvm-cov gcov test.c -gcda=no_such_gcda_file | diff -u test_no_gcda.output -
 RUN: diff -aub test_no_gcda.cpp.gcov test.cpp.gcov
 RUN: diff -aub test_no_gcda.h.gcov test.h.gcov
 
 # Invalid gcno file.
-RUN: llvm-cov test.c -gcno=test_read_fail.gcno
+RUN: llvm-cov gcov test.c -gcno=test_read_fail.gcno
 
 # Bad file checksum on gcda.
-RUN: llvm-cov test.c -gcda=test_file_checksum_fail.gcda
+RUN: llvm-cov gcov test.c -gcda=test_file_checksum_fail.gcda
 
 # Bad function checksum on gcda
-RUN: llvm-cov test.c -gcda=test_func_checksum_fail.gcda
+RUN: llvm-cov gcov test.c -gcda=test_func_checksum_fail.gcda
 
 # Has arcs from exit blocks
-RUN: llvm-cov test_exit_block_arcs.c 2>&1 | FileCheck %s -check-prefix=EXIT_BLOCK_ARCS
+RUN: llvm-cov gcov test_exit_block_arcs.c 2>&1 | FileCheck %s -check-prefix=EXIT_BLOCK_ARCS
 EXIT_BLOCK_ARCS: (main) has arcs from exit block.
 
 XFAIL: powerpc64-, s390x, mips-, mips64-, sparc
diff --git a/test/tools/llvm-cov/range_based_for.cpp b/test/tools/llvm-cov/range_based_for.cpp
index 3fdb2441399c..6f7a11ad6341 100644
--- a/test/tools/llvm-cov/range_based_for.cpp
+++ b/test/tools/llvm-cov/range_based_for.cpp
@@ -9,7 +9,7 @@
 // RUN: cd %t
 // RUN: cp %s %p/Inputs/range_based_for.gc* .
 
-// RUN: llvm-cov range_based_for.cpp | FileCheck %s --check-prefix=STDOUT
+// RUN: llvm-cov gcov range_based_for.cpp | FileCheck %s --check-prefix=STDOUT
 // STDOUT: File 'range_based_for.cpp'
 // STDOUT: Lines executed:100.00% of 5
 // STDOUT: range_based_for.cpp:creating 'range_based_for.cpp.gcov'
diff --git a/test/tools/llvm-cov/report.cpp b/test/tools/llvm-cov/report.cpp
index 297322a775d7..3322e1a2c063 100644
--- a/test/tools/llvm-cov/report.cpp
+++ b/test/tools/llvm-cov/report.cpp
@@ -1,7 +1,21 @@
-// RUN: llvm-cov report %S/Inputs/report.covmapping -instr-profile %S/Inputs/report.profdata -no-colors 2>&1 | FileCheck %s
+// RUN: llvm-cov report %S/Inputs/report.covmapping -instr-profile %S/Inputs/report.profdata -filename-equivalence 2>&1 | FileCheck %s
+// RUN: llvm-cov report %S/Inputs/report.covmapping -instr-profile %S/Inputs/report.profdata -filename-equivalence report.cpp 2>&1 | FileCheck -check-prefix=FILT-NEXT %s
 
-// CHECK: Filename                    Regions    Miss   Cover Functions  Executed
-// CHECK: TOTAL                             5       2  60.00%         4    75.00%
+// CHECK:      Filename   Regions  Miss   Cover  Functions  Executed
+// CHECK-NEXT: ---
+// CHECK-NEXT: report.cpp       5     2  60.00%          4    75.00%
+// CHECK-NEXT: ---
+// CHECK-NEXT: TOTAL            5     2  60.00%          4    75.00%
+
+// FILT: File 'report.cpp':
+// FILT-NEXT: Name        Regions  Miss   Cover  Lines  Miss   Cover
+// FILT-NEXT: ---
+// FILT-NEXT: _Z3foob           2     1  50.00%      4     2  50.00%
+// FILT-NEXT: _Z3barv           1     0 100.00%      2     0 100.00%
+// FILT-NEXT: _Z4funcv          1     1   0.00%      2     2   0.00%
+// FILT-NEXT: main              1     0 100.00%      5     0 100.00%
+// FILT-NEXT: ---
+// FILT-NEXT: TOTAL             5     2  60.00%     13     4  69.23%
 
 void foo(bool cond) {
   if (cond) {
@@ -19,6 +33,3 @@ int main() {
   bar();
   return 0;
 }
-
-// llvm-cov doesn't work on big endian yet
-// XFAIL: powerpc64-, s390x, mips-, mips64-, sparc
diff --git a/test/tools/llvm-cov/showExpansions.cpp b/test/tools/llvm-cov/showExpansions.cpp
index 30edd90584f8..de3898fc897a 100644
--- a/test/tools/llvm-cov/showExpansions.cpp
+++ b/test/tools/llvm-cov/showExpansions.cpp
@@ -24,6 +24,3 @@ int main(int argc, const char *argv[]) {
     DO_SOMETHING(i); // CHECK-DAG: Expansion at line [[@LINE]], 5 -> 17
   return 0;
 }
-
-// llvm-cov doesn't work on big endian yet
-// XFAIL: powerpc64-, s390x, mips-, mips64-, sparc
diff --git a/test/tools/llvm-cov/showHighlightedRanges.cpp b/test/tools/llvm-cov/showHighlightedRanges.cpp
index cec730829e0c..b5209d40d22b 100644
--- a/test/tools/llvm-cov/showHighlightedRanges.cpp
+++ b/test/tools/llvm-cov/showHighlightedRanges.cpp
@@ -2,17 +2,17 @@
 
 void func() {
   return;
-  int i = 0;                     // CHECK: Highlighted line [[@LINE]], 3 -> 12
-}
+  int i = 0;                     // CHECK: Highlighted line [[@LINE]], 3 -> ?
+}                                // CHECK: Highlighted line [[@LINE]], 1 -> 2
 
 void func2(int x) {
   if(x > 5) {
     while(x >= 9) {
       return;
-      --x;                       // CHECK: Highlighted line [[@LINE]], 7 -> 10
-    }
-    int i = 0;                   // CHECK: Highlighted line [[@LINE]], 5 -> 14
-  }
+      --x;                       // CHECK: Highlighted line [[@LINE]], 7 -> ?
+    }                            // CHECK: Highlighted line [[@LINE]], 1 -> 6
+    int i = 0;                   // CHECK: Highlighted line [[@LINE]], 5 -> ?
+  }                              // CHECK: Highlighted line [[@LINE]], 1 -> 4
 }
 
 void test() {
@@ -43,6 +43,3 @@ int main() {
   func2(9);
   return 0;
 }
-
-// llvm-cov doesn't work on big endian yet
-// XFAIL: powerpc64-, s390x, mips-, mips64-, sparc
diff --git a/test/tools/llvm-cov/showLineExecutionCounts.cpp b/test/tools/llvm-cov/showLineExecutionCounts.cpp
index 34baa574dab2..83fee977e6d8 100644
--- a/test/tools/llvm-cov/showLineExecutionCounts.cpp
+++ b/test/tools/llvm-cov/showLineExecutionCounts.cpp
@@ -1,30 +1,30 @@
-// RUN: llvm-cov show %S/Inputs/lineExecutionCounts.covmapping -instr-profile %S/Inputs/lineExecutionCounts.profdata -no-colors -filename-equivalence %s | FileCheck -check-prefix=CHECK -check-prefix=WHOLE-FILE %s
-// RUN: llvm-cov show %S/Inputs/lineExecutionCounts.covmapping -instr-profile %S/Inputs/lineExecutionCounts.profdata -no-colors -filename-equivalence -name=main %s | FileCheck -check-prefix=CHECK -check-prefix=FILTER %s
+// Basic handling of line counts.
+// RUN: llvm-profdata merge %S/Inputs/lineExecutionCounts.proftext -o %t.profdata
 
-// before any coverage              // WHOLE-FILE:    | [[@LINE]]|// before
-                                    // FILTER-NOT:    | [[@LINE-1]]|// before
-int main() {                             // CHECK:   1| [[@LINE]]|int main(
-  int x = 0;                             // CHECK:   1| [[@LINE]]|  int x
-                                         // CHECK:   1| [[@LINE]]|
-  if (x) {                               // CHECK:   0| [[@LINE]]|  if (x)
-    x = 0;                               // CHECK:   0| [[@LINE]]|    x = 0
-  } else {                               // CHECK:   1| [[@LINE]]|  } else
-    x = 1;                               // CHECK:   1| [[@LINE]]|    x = 1
-  }                                      // CHECK:   1| [[@LINE]]|  }
-                                         // CHECK:   1| [[@LINE]]|
-  for (int i = 0; i < 100; ++i) {        // CHECK: 100| [[@LINE]]|  for (
-    x = 1;                               // CHECK: 100| [[@LINE]]|    x = 1
-  }                                      // CHECK: 100| [[@LINE]]|  }
-                                         // CHECK:   1| [[@LINE]]|
-  x = x < 10 ? x + 1 : x - 1;            // CHECK:   0| [[@LINE]]|  x =
-  x = x > 10 ?                           // CHECK:   1| [[@LINE]]|  x =
-        x - 1:                           // CHECK:   0| [[@LINE]]|        x
-        x + 1;                           // CHECK:   1| [[@LINE]]|        x
-                                         // CHECK:   1| [[@LINE]]|
-  return 0;                              // CHECK:   1| [[@LINE]]|  return
-}                                        // CHECK:   1| [[@LINE]]|}
-// after coverage                   // WHOLE-FILE:    | [[@LINE]]|// after
-                                    // FILTER-NOT:    | [[@LINE-1]]|// after
+// before any coverage              // WHOLE-FILE:      | [[@LINE]]|// before
+                                    // FILTER-NOT:      | [[@LINE-1]]|// before
+int main() {                             // CHECK:   161| [[@LINE]]|int main(
+  int x = 0;                             // CHECK:   161| [[@LINE]]|  int x
+                                         // CHECK:   161| [[@LINE]]|
+  if (x) {                               // CHECK:     0| [[@LINE]]|  if (x)
+    x = 0;                               // CHECK:     0| [[@LINE]]|    x = 0
+  } else {                               // CHECK:   161| [[@LINE]]|  } else
+    x = 1;                               // CHECK:   161| [[@LINE]]|    x = 1
+  }                                      // CHECK:   161| [[@LINE]]|  }
+                                         // CHECK:   161| [[@LINE]]|
+  for (int i = 0; i < 100; ++i) {        // CHECK: 16.2k| [[@LINE]]|  for (
+    x = 1;                               // CHECK: 16.1k| [[@LINE]]|    x = 1
+  }                                      // CHECK: 16.1k| [[@LINE]]|  }
+                                         // CHECK:   161| [[@LINE]]|
+  x = x < 10 ? x + 1 : x - 1;            // CHECK:   161| [[@LINE]]|  x =
+  x = x > 10 ?                           // CHECK:   161| [[@LINE]]|  x =
+        x - 1:                           // CHECK:     0| [[@LINE]]|        x
+        x + 1;                           // CHECK:   161| [[@LINE]]|        x
+                                         // CHECK:   161| [[@LINE]]|
+  return 0;                              // CHECK:   161| [[@LINE]]|  return
+}                                        // CHECK:   161| [[@LINE]]|}
+// after coverage                   // WHOLE-FILE:      | [[@LINE]]|// after
+                                    // FILTER-NOT:      | [[@LINE-1]]|// after
 
-// llvm-cov doesn't work on big endian yet
-// XFAIL: powerpc64-, s390x, mips-, mips64-, sparc
+// RUN: llvm-cov show %S/Inputs/lineExecutionCounts.covmapping -instr-profile %t.profdata -filename-equivalence %s | FileCheck -check-prefix=CHECK -check-prefix=WHOLE-FILE %s
+// RUN: llvm-cov show %S/Inputs/lineExecutionCounts.covmapping -instr-profile %t.profdata -filename-equivalence -name=main %s | FileCheck -check-prefix=CHECK -check-prefix=FILTER %s
diff --git a/test/tools/llvm-cov/showRegionMarkers.cpp b/test/tools/llvm-cov/showRegionMarkers.cpp
index 136c3bf7cac3..5507367c0ed1 100644
--- a/test/tools/llvm-cov/showRegionMarkers.cpp
+++ b/test/tools/llvm-cov/showRegionMarkers.cpp
@@ -1,26 +1,25 @@
-// RUN: llvm-cov show %S/Inputs/regionMarkers.covmapping -instr-profile %S/Inputs/regionMarkers.profdata -show-regions -dump -filename-equivalence %s 2>&1 | FileCheck %s
+// RUN: llvm-profdata merge %S/Inputs/regionMarkers.proftext -o %t.profdata
 
-int main() {                      // CHECK: Marker at [[@LINE]]:12 = 1
+int main() {                      // CHECK: Marker at [[@LINE]]:12 = 1.11M
   int x = 0;
 
   if (x) {                        // CHECK: Marker at [[@LINE]]:10 = 0
     x = 0;
-  } else {                        // CHECK: Marker at [[@LINE]]:10 = 1
+  } else {                        // CHECK: Marker at [[@LINE]]:10 = 1.11M
     x = 1;
   }
-                                  // CHECK: Marker at [[@LINE+2]]:19 = 101
-                                  // CHECK: Marker at [[@LINE+1]]:28 = 100
-  for (int i = 0; i < 100; ++i) { // CHECK: Marker at [[@LINE]]:33 = 100
+                                  // CHECK: Marker at [[@LINE+2]]:19 = 112M
+                                  // CHECK: Marker at [[@LINE+1]]:28 = 111M
+  for (int i = 0; i < 100; ++i) { // CHECK: Marker at [[@LINE]]:33 = 111M
     x = 1;
   }
-                                  // CHECK: Marker at [[@LINE+1]]:16 = 1
+                                  // CHECK: Marker at [[@LINE+1]]:16 = 1.11M
   x = x < 10 ? x + 1 : x - 1;     // CHECK: Marker at [[@LINE]]:24 = 0
   x = x > 10 ?
         x - 1:                    // CHECK: Marker at [[@LINE]]:9 = 0
-        x + 1;                    // CHECK: Marker at [[@LINE]]:9 = 1
+        x + 1;                    // CHECK: Marker at [[@LINE]]:9 = 1.11M
 
   return 0;
 }
 
-// llvm-cov doesn't work on big endian yet
-// XFAIL: powerpc64-, s390x, mips-, mips64-, sparc
+// RUN: llvm-cov show %S/Inputs/regionMarkers.covmapping -instr-profile %t.profdata -show-regions -dump -filename-equivalence %s 2>&1 | FileCheck %s
diff --git a/test/tools/llvm-cov/showTemplateInstantiations.cpp b/test/tools/llvm-cov/showTemplateInstantiations.cpp
index 2b72d83c013d..a9be473dc915 100644
--- a/test/tools/llvm-cov/showTemplateInstantiations.cpp
+++ b/test/tools/llvm-cov/showTemplateInstantiations.cpp
@@ -1,5 +1,5 @@
-// RUN: llvm-cov show %S/Inputs/templateInstantiations.covmapping -instr-profile %S/Inputs/templateInstantiations.profdata -no-colors -filename-equivalence %s | FileCheck -check-prefix=CHECK -check-prefix=ALL %s
-// RUN: llvm-cov show %S/Inputs/templateInstantiations.covmapping -instr-profile %S/Inputs/templateInstantiations.profdata -no-colors -filename-equivalence -name=_Z4funcIbEiT_ %s | FileCheck -check-prefix=CHECK -check-prefix=FILTER %s
+// RUN: llvm-cov show %S/Inputs/templateInstantiations.covmapping -instr-profile %S/Inputs/templateInstantiations.profdata -filename-equivalence %s | FileCheck -check-prefix=CHECK -check-prefix=ALL %s
+// RUN: llvm-cov show %S/Inputs/templateInstantiations.covmapping -instr-profile %S/Inputs/templateInstantiations.profdata -filename-equivalence -name=_Z4funcIbEiT_ %s | FileCheck -check-prefix=CHECK -check-prefix=FILTER %s
 
 // before coverage   // WHOLE-FILE:   | [[@LINE]]|// before
                      // FILTER-NOT:   | [[@LINE-1]]|// before
@@ -38,6 +38,3 @@ int main() {         // ALL:         1| [[@LINE]]|int main() {
 }                    // ALL-NEXT:    1| [[@LINE]]|}
 // after coverage    // ALL-NEXT:     | [[@LINE]]|// after
                      // FILTER-NOT:   | [[@LINE-1]]|// after
-
-// llvm-cov doesn't work on big endian yet
-// XFAIL: powerpc64-, s390x, mips-, mips64-, sparc
diff --git a/test/tools/llvm-cov/universal-binary.c b/test/tools/llvm-cov/universal-binary.c
new file mode 100644
index 000000000000..8ff94d4e3ad3
--- /dev/null
+++ b/test/tools/llvm-cov/universal-binary.c
@@ -0,0 +1,10 @@
+// The coverage reader should be able to handle universal binaries
+
+// CHECK: 100| [[@LINE+1]]|int main
+int main(int argc, const char *argv[]) {}
+
+// RUN: llvm-profdata merge %S/Inputs/universal-binary.proftext -o %t.profdata
+// RUN: llvm-cov show %S/Inputs/universal-binary -instr-profile %t.profdata -filename-equivalence %s -arch x86_64 | FileCheck %s
+
+// RUN: not llvm-cov show %S/Inputs/universal-binary -instr-profile %t.profdata -filename-equivalence %s -arch i386 2>&1 | FileCheck --check-prefix=WRONG-ARCH %s
+// WRONG-ARCH: Failed to load coverage
diff --git a/test/tools/llvm-cxxdump/Inputs/eh.obj.coff-i386 b/test/tools/llvm-cxxdump/Inputs/eh.obj.coff-i386
new file mode 100644
index 000000000000..f34a079bdb88
--- /dev/null
+++ b/test/tools/llvm-cxxdump/Inputs/eh.obj.coff-i386
diff --git a/test/tools/llvm-vtabledump/Inputs/trivial.obj.coff-i386 b/test/tools/llvm-cxxdump/Inputs/trivial.obj.coff-i386
index 3b9395583eb5..3b9395583eb5 100644
--- a/test/tools/llvm-vtabledump/Inputs/trivial.obj.coff-i386
+++ b/test/tools/llvm-cxxdump/Inputs/trivial.obj.coff-i386
diff --git a/test/tools/llvm-vtabledump/Inputs/trivial.obj.elf-i386 b/test/tools/llvm-cxxdump/Inputs/trivial.obj.elf-i386
index 1a5c929b0829..1a5c929b0829 100644
--- a/test/tools/llvm-vtabledump/Inputs/trivial.obj.elf-i386
+++ b/test/tools/llvm-cxxdump/Inputs/trivial.obj.elf-i386
diff --git a/test/tools/llvm-cxxdump/eh.test b/test/tools/llvm-cxxdump/eh.test
new file mode 100644
index 000000000000..b323b05defe4
--- /dev/null
+++ b/test/tools/llvm-cxxdump/eh.test
@@ -0,0 +1,258 @@
+RUN: llvm-cxxdump %p/Inputs/eh.obj.coff-i386 \
+RUN:   | FileCheck %s --check-prefix=COFF-I386
+
+
+COFF-I386: ??_R0?AUA@@@8[VFPtr]: ??_7type_info@@6B@
+COFF-I386: ??_R0?AUA@@@8[AlwaysZero]: 0
+COFF-I386: ??_R0?AUA@@@8[MangledName]: .?AUA@@
+COFF-I386: ??_R0?AUB@@@8[VFPtr]: ??_7type_info@@6B@
+COFF-I386: ??_R0?AUB@@@8[AlwaysZero]: 0
+COFF-I386: ??_R0?AUB@@@8[MangledName]: .?AUB@@
+COFF-I386: ??_R0?AUC@@@8[VFPtr]: ??_7type_info@@6B@
+COFF-I386: ??_R0?AUC@@@8[AlwaysZero]: 0
+COFF-I386: ??_R0?AUC@@@8[MangledName]: .?AUC@@
+COFF-I386: ??_R0?AUM@@@8[VFPtr]: ??_7type_info@@6B@
+COFF-I386: ??_R0?AUM@@@8[AlwaysZero]: 0
+COFF-I386: ??_R0?AUM@@@8[MangledName]: .?AUM@@
+COFF-I386: ??_R0?AUS@@@8[VFPtr]: ??_7type_info@@6B@
+COFF-I386: ??_R0?AUS@@@8[AlwaysZero]: 0
+COFF-I386: ??_R0?AUS@@@8[MangledName]: .?AUS@@
+COFF-I386: ??_R0?AW4E@@@8[VFPtr]: ??_7type_info@@6B@
+COFF-I386: ??_R0?AW4E@@@8[AlwaysZero]: 0
+COFF-I386: ??_R0?AW4E@@@8[MangledName]: .?AW4E@@
+COFF-I386: ??_R0PAUA@@@8[VFPtr]: ??_7type_info@@6B@
+COFF-I386: ??_R0PAUA@@@8[AlwaysZero]: 0
+COFF-I386: ??_R0PAUA@@@8[MangledName]: .PAUA@@
+COFF-I386: ??_R0PAUC@@@8[VFPtr]: ??_7type_info@@6B@
+COFF-I386: ??_R0PAUC@@@8[AlwaysZero]: 0
+COFF-I386: ??_R0PAUC@@@8[MangledName]: .PAUC@@
+COFF-I386: ??_R0PAUS@@@8[VFPtr]: ??_7type_info@@6B@
+COFF-I386: ??_R0PAUS@@@8[AlwaysZero]: 0
+COFF-I386: ??_R0PAUS@@@8[MangledName]: .PAUS@@
+COFF-I386: ??_R0PAW4E@@@8[VFPtr]: ??_7type_info@@6B@
+COFF-I386: ??_R0PAW4E@@@8[AlwaysZero]: 0
+COFF-I386: ??_R0PAW4E@@@8[MangledName]: .PAW4E@@
+COFF-I386: ??_R0PAX@8[VFPtr]: ??_7type_info@@6B@
+COFF-I386: ??_R0PAX@8[AlwaysZero]: 0
+COFF-I386: ??_R0PAX@8[MangledName]: .PAX
+COFF-I386: ??_R0PQS@@H@8[VFPtr]: ??_7type_info@@6B@
+COFF-I386: ??_R0PQS@@H@8[AlwaysZero]: 0
+COFF-I386: ??_R0PQS@@H@8[MangledName]: .PQS@@H
+COFF-I386: __TI1?AW4E@@[Flags]: 0
+COFF-I386: __TI1?AW4E@@[Flags.Const]: false
+COFF-I386: __TI1?AW4E@@[Flags.Volatile]: false
+COFF-I386: __TI1?AW4E@@[CleanupFn]: null
+COFF-I386: __TI1?AW4E@@[ForwardCompat]: null
+COFF-I386: __TI1?AW4E@@[CatchableTypeArray]: __CTA1?AW4E@@
+COFF-I386: __TI1PQS@@H[Flags]: 0
+COFF-I386: __TI1PQS@@H[Flags.Const]: false
+COFF-I386: __TI1PQS@@H[Flags.Volatile]: false
+COFF-I386: __TI1PQS@@H[CleanupFn]: null
+COFF-I386: __TI1PQS@@H[ForwardCompat]: null
+COFF-I386: __TI1PQS@@H[CatchableTypeArray]: __CTA1PQS@@H
+COFF-I386: __TI2CPAW4E@@[Flags]: 1
+COFF-I386: __TI2CPAW4E@@[Flags.Const]: true
+COFF-I386: __TI2CPAW4E@@[Flags.Volatile]: false
+COFF-I386: __TI2CPAW4E@@[CleanupFn]: null
+COFF-I386: __TI2CPAW4E@@[ForwardCompat]: null
+COFF-I386: __TI2CPAW4E@@[CatchableTypeArray]: __CTA2PAW4E@@
+COFF-I386: __TI2CVPAW4E@@[Flags]: 3
+COFF-I386: __TI2CVPAW4E@@[Flags.Const]: true
+COFF-I386: __TI2CVPAW4E@@[Flags.Volatile]: true
+COFF-I386: __TI2CVPAW4E@@[CleanupFn]: null
+COFF-I386: __TI2CVPAW4E@@[ForwardCompat]: null
+COFF-I386: __TI2CVPAW4E@@[CatchableTypeArray]: __CTA2PAW4E@@
+COFF-I386: __TI2PAW4E@@[Flags]: 0
+COFF-I386: __TI2PAW4E@@[Flags.Const]: false
+COFF-I386: __TI2PAW4E@@[Flags.Volatile]: false
+COFF-I386: __TI2PAW4E@@[CleanupFn]: null
+COFF-I386: __TI2PAW4E@@[ForwardCompat]: null
+COFF-I386: __TI2PAW4E@@[CatchableTypeArray]: __CTA2PAW4E@@
+COFF-I386: __TI2PAX[Flags]: 0
+COFF-I386: __TI2PAX[Flags.Const]: false
+COFF-I386: __TI2PAX[Flags.Volatile]: false
+COFF-I386: __TI2PAX[CleanupFn]: null
+COFF-I386: __TI2PAX[ForwardCompat]: null
+COFF-I386: __TI2PAX[CatchableTypeArray]: __CTA2PAX
+COFF-I386: __TI2VPAW4E@@[Flags]: 2
+COFF-I386: __TI2VPAW4E@@[Flags.Const]: false
+COFF-I386: __TI2VPAW4E@@[Flags.Volatile]: true
+COFF-I386: __TI2VPAW4E@@[CleanupFn]: null
+COFF-I386: __TI2VPAW4E@@[ForwardCompat]: null
+COFF-I386: __TI2VPAW4E@@[CatchableTypeArray]: __CTA2PAW4E@@
+COFF-I386: __TI3?AUM@@[Flags]: 0
+COFF-I386: __TI3?AUM@@[Flags.Const]: false
+COFF-I386: __TI3?AUM@@[Flags.Volatile]: false
+COFF-I386: __TI3?AUM@@[CleanupFn]: null
+COFF-I386: __TI3?AUM@@[ForwardCompat]: null
+COFF-I386: __TI3?AUM@@[CatchableTypeArray]: __CTA3?AUM@@
+COFF-I386: __TI3?AUS@@[Flags]: 0
+COFF-I386: __TI3?AUS@@[Flags.Const]: false
+COFF-I386: __TI3?AUS@@[Flags.Volatile]: false
+COFF-I386: __TI3?AUS@@[CleanupFn]: ??1S@@UAE@XZ
+COFF-I386: __TI3?AUS@@[ForwardCompat]: null
+COFF-I386: __TI3?AUS@@[CatchableTypeArray]: __CTA3?AUS@@
+COFF-I386: __TI4CPAUS@@[Flags]: 1
+COFF-I386: __TI4CPAUS@@[Flags.Const]: true
+COFF-I386: __TI4CPAUS@@[Flags.Volatile]: false
+COFF-I386: __TI4CPAUS@@[CleanupFn]: null
+COFF-I386: __TI4CPAUS@@[ForwardCompat]: null
+COFF-I386: __TI4CPAUS@@[CatchableTypeArray]: __CTA4PAUS@@
+COFF-I386: __TI4CVPAUS@@[Flags]: 3
+COFF-I386: __TI4CVPAUS@@[Flags.Const]: true
+COFF-I386: __TI4CVPAUS@@[Flags.Volatile]: true
+COFF-I386: __TI4CVPAUS@@[CleanupFn]: null
+COFF-I386: __TI4CVPAUS@@[ForwardCompat]: null
+COFF-I386: __TI4CVPAUS@@[CatchableTypeArray]: __CTA4PAUS@@
+COFF-I386: __TI4PAUS@@[Flags]: 0
+COFF-I386: __TI4PAUS@@[Flags.Const]: false
+COFF-I386: __TI4PAUS@@[Flags.Volatile]: false
+COFF-I386: __TI4PAUS@@[CleanupFn]: null
+COFF-I386: __TI4PAUS@@[ForwardCompat]: null
+COFF-I386: __TI4PAUS@@[CatchableTypeArray]: __CTA4PAUS@@
+COFF-I386: __TI4VPAUS@@[Flags]: 2
+COFF-I386: __TI4VPAUS@@[Flags.Const]: false
+COFF-I386: __TI4VPAUS@@[Flags.Volatile]: true
+COFF-I386: __TI4VPAUS@@[CleanupFn]: null
+COFF-I386: __TI4VPAUS@@[ForwardCompat]: null
+COFF-I386: __TI4VPAUS@@[CatchableTypeArray]: __CTA4PAUS@@
+COFF-I386: __CTA1?AW4E@@[NumEntries]: 1
+COFF-I386: __CTA1?AW4E@@[0]: __CT??_R0?AW4E@@@84
+COFF-I386: __CTA1PQS@@H[NumEntries]: 1
+COFF-I386: __CTA1PQS@@H[0]: __CT??_R0PQS@@H@88
+COFF-I386: __CTA2PAW4E@@[NumEntries]: 2
+COFF-I386: __CTA2PAW4E@@[0]: __CT??_R0PAW4E@@@84
+COFF-I386: __CTA2PAW4E@@[1]: __CT??_R0PAX@84
+COFF-I386: __CTA2PAX[NumEntries]: 2
+COFF-I386: __CTA2PAX[0]: __CT??_R0PAX@84
+COFF-I386: __CTA2PAX[1]: __CT??_R0PAX@84
+COFF-I386: __CTA3?AUM@@[NumEntries]: 3
+COFF-I386: __CTA3?AUM@@[0]: __CT??_R0?AUM@@@88
+COFF-I386: __CTA3?AUM@@[1]: __CT??_R0?AUA@@@84
+COFF-I386: __CTA3?AUM@@[2]: __CT??_R0?AUB@@@844
+COFF-I386: __CTA3?AUS@@[NumEntries]: 3
+COFF-I386: __CTA3?AUS@@[0]: __CT??_R0?AUS@@@8??0S@@QAE@ABU0@@Z16
+COFF-I386: __CTA3?AUS@@[1]: __CT??_R0?AUA@@@84044
+COFF-I386: __CTA3?AUS@@[2]: __CT??_R0?AUC@@@84048
+COFF-I386: __CTA4PAUS@@[NumEntries]: 4
+COFF-I386: __CTA4PAUS@@[0]: __CT??_R0PAUS@@@84
+COFF-I386: __CTA4PAUS@@[1]: __CT??_R0PAUA@@@84044
+COFF-I386: __CTA4PAUS@@[2]: __CT??_R0PAUC@@@84048
+COFF-I386: __CTA4PAUS@@[3]: __CT??_R0PAX@84
+COFF-I386: __CT??_R0?AUA@@@84[Flags]: 0
+COFF-I386: __CT??_R0?AUA@@@84[Flags.ScalarType]: false
+COFF-I386: __CT??_R0?AUA@@@84[Flags.VirtualInheritance]: false
+COFF-I386: __CT??_R0?AUA@@@84[TypeDescriptor]: ??_R0?AUA@@@8
+COFF-I386: __CT??_R0?AUA@@@84[NonVirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0?AUA@@@84[VirtualBasePointerOffset]: -1
+COFF-I386: __CT??_R0?AUA@@@84[VirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0?AUA@@@84[Size]: 4
+COFF-I386: __CT??_R0?AUA@@@84[CopyCtor]: null
+COFF-I386: __CT??_R0?AUA@@@84044[Flags]: 0
+COFF-I386: __CT??_R0?AUA@@@84044[Flags.ScalarType]: false
+COFF-I386: __CT??_R0?AUA@@@84044[Flags.VirtualInheritance]: false
+COFF-I386: __CT??_R0?AUA@@@84044[TypeDescriptor]: ??_R0?AUA@@@8
+COFF-I386: __CT??_R0?AUA@@@84044[NonVirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0?AUA@@@84044[VirtualBasePointerOffset]: 4
+COFF-I386: __CT??_R0?AUA@@@84044[VirtualBaseAdjustmentOffset]: 4
+COFF-I386: __CT??_R0?AUA@@@84044[Size]: 4
+COFF-I386: __CT??_R0?AUA@@@84044[CopyCtor]: null
+COFF-I386: __CT??_R0?AUB@@@844[Flags]: 0
+COFF-I386: __CT??_R0?AUB@@@844[Flags.ScalarType]: false
+COFF-I386: __CT??_R0?AUB@@@844[Flags.VirtualInheritance]: false
+COFF-I386: __CT??_R0?AUB@@@844[TypeDescriptor]: ??_R0?AUB@@@8
+COFF-I386: __CT??_R0?AUB@@@844[NonVirtualBaseAdjustmentOffset]: 4
+COFF-I386: __CT??_R0?AUB@@@844[VirtualBasePointerOffset]: -1
+COFF-I386: __CT??_R0?AUB@@@844[VirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0?AUB@@@844[Size]: 4
+COFF-I386: __CT??_R0?AUB@@@844[CopyCtor]: null
+COFF-I386: __CT??_R0?AUC@@@84048[Flags]: 0
+COFF-I386: __CT??_R0?AUC@@@84048[Flags.ScalarType]: false
+COFF-I386: __CT??_R0?AUC@@@84048[Flags.VirtualInheritance]: false
+COFF-I386: __CT??_R0?AUC@@@84048[TypeDescriptor]: ??_R0?AUC@@@8
+COFF-I386: __CT??_R0?AUC@@@84048[NonVirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0?AUC@@@84048[VirtualBasePointerOffset]: 4
+COFF-I386: __CT??_R0?AUC@@@84048[VirtualBaseAdjustmentOffset]: 8
+COFF-I386: __CT??_R0?AUC@@@84048[Size]: 4
+COFF-I386: __CT??_R0?AUC@@@84048[CopyCtor]: null
+COFF-I386: __CT??_R0?AUM@@@88[Flags]: 0
+COFF-I386: __CT??_R0?AUM@@@88[Flags.ScalarType]: false
+COFF-I386: __CT??_R0?AUM@@@88[Flags.VirtualInheritance]: false
+COFF-I386: __CT??_R0?AUM@@@88[TypeDescriptor]: ??_R0?AUM@@@8
+COFF-I386: __CT??_R0?AUM@@@88[NonVirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0?AUM@@@88[VirtualBasePointerOffset]: -1
+COFF-I386: __CT??_R0?AUM@@@88[VirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0?AUM@@@88[Size]: 8
+COFF-I386: __CT??_R0?AUM@@@88[CopyCtor]: null
+COFF-I386: __CT??_R0?AUS@@@8??0S@@QAE@ABU0@@Z16[Flags]: 4
+COFF-I386: __CT??_R0?AUS@@@8??0S@@QAE@ABU0@@Z16[Flags.ScalarType]: false
+COFF-I386: __CT??_R0?AUS@@@8??0S@@QAE@ABU0@@Z16[Flags.VirtualInheritance]: true
+COFF-I386: __CT??_R0?AUS@@@8??0S@@QAE@ABU0@@Z16[TypeDescriptor]: ??_R0?AUS@@@8
+COFF-I386: __CT??_R0?AUS@@@8??0S@@QAE@ABU0@@Z16[NonVirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0?AUS@@@8??0S@@QAE@ABU0@@Z16[VirtualBasePointerOffset]: -1
+COFF-I386: __CT??_R0?AUS@@@8??0S@@QAE@ABU0@@Z16[VirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0?AUS@@@8??0S@@QAE@ABU0@@Z16[Size]: 16
+COFF-I386: __CT??_R0?AUS@@@8??0S@@QAE@ABU0@@Z16[CopyCtor]: ??0S@@QAE@ABU0@@Z
+COFF-I386: __CT??_R0?AW4E@@@84[Flags]: 1
+COFF-I386: __CT??_R0?AW4E@@@84[Flags.ScalarType]: true
+COFF-I386: __CT??_R0?AW4E@@@84[Flags.VirtualInheritance]: false
+COFF-I386: __CT??_R0?AW4E@@@84[TypeDescriptor]: ??_R0?AW4E@@@8
+COFF-I386: __CT??_R0?AW4E@@@84[NonVirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0?AW4E@@@84[VirtualBasePointerOffset]: -1
+COFF-I386: __CT??_R0?AW4E@@@84[VirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0?AW4E@@@84[Size]: 4
+COFF-I386: __CT??_R0?AW4E@@@84[CopyCtor]: null
+COFF-I386: __CT??_R0PAUA@@@84044[Flags]: 1
+COFF-I386: __CT??_R0PAUA@@@84044[Flags.ScalarType]: true
+COFF-I386: __CT??_R0PAUA@@@84044[Flags.VirtualInheritance]: false
+COFF-I386: __CT??_R0PAUA@@@84044[TypeDescriptor]: ??_R0PAUA@@@8
+COFF-I386: __CT??_R0PAUA@@@84044[NonVirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0PAUA@@@84044[VirtualBasePointerOffset]: 4
+COFF-I386: __CT??_R0PAUA@@@84044[VirtualBaseAdjustmentOffset]: 4
+COFF-I386: __CT??_R0PAUA@@@84044[Size]: 4
+COFF-I386: __CT??_R0PAUA@@@84044[CopyCtor]: null
+COFF-I386: __CT??_R0PAUC@@@84048[Flags]: 1
+COFF-I386: __CT??_R0PAUC@@@84048[Flags.ScalarType]: true
+COFF-I386: __CT??_R0PAUC@@@84048[Flags.VirtualInheritance]: false
+COFF-I386: __CT??_R0PAUC@@@84048[TypeDescriptor]: ??_R0PAUC@@@8
+COFF-I386: __CT??_R0PAUC@@@84048[NonVirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0PAUC@@@84048[VirtualBasePointerOffset]: 4
+COFF-I386: __CT??_R0PAUC@@@84048[VirtualBaseAdjustmentOffset]: 8
+COFF-I386: __CT??_R0PAUC@@@84048[Size]: 4
+COFF-I386: __CT??_R0PAUC@@@84048[CopyCtor]: null
+COFF-I386: __CT??_R0PAUS@@@84[Flags]: 5
+COFF-I386: __CT??_R0PAUS@@@84[Flags.ScalarType]: true
+COFF-I386: __CT??_R0PAUS@@@84[Flags.VirtualInheritance]: true
+COFF-I386: __CT??_R0PAUS@@@84[TypeDescriptor]: ??_R0PAUS@@@8
+COFF-I386: __CT??_R0PAUS@@@84[NonVirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0PAUS@@@84[VirtualBasePointerOffset]: -1
+COFF-I386: __CT??_R0PAUS@@@84[VirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0PAUS@@@84[Size]: 4
+COFF-I386: __CT??_R0PAUS@@@84[CopyCtor]: null
+COFF-I386: __CT??_R0PAW4E@@@84[Flags]: 1
+COFF-I386: __CT??_R0PAW4E@@@84[Flags.ScalarType]: true
+COFF-I386: __CT??_R0PAW4E@@@84[Flags.VirtualInheritance]: false
+COFF-I386: __CT??_R0PAW4E@@@84[TypeDescriptor]: ??_R0PAW4E@@@8
+COFF-I386: __CT??_R0PAW4E@@@84[NonVirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0PAW4E@@@84[VirtualBasePointerOffset]: -1
+COFF-I386: __CT??_R0PAW4E@@@84[VirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0PAW4E@@@84[Size]: 4
+COFF-I386: __CT??_R0PAW4E@@@84[CopyCtor]: null
+COFF-I386: __CT??_R0PAX@84[Flags]: 1
+COFF-I386: __CT??_R0PAX@84[Flags.ScalarType]: true
+COFF-I386: __CT??_R0PAX@84[Flags.VirtualInheritance]: false
+COFF-I386: __CT??_R0PAX@84[TypeDescriptor]: ??_R0PAX@8
+COFF-I386: __CT??_R0PAX@84[NonVirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0PAX@84[VirtualBasePointerOffset]: -1
+COFF-I386: __CT??_R0PAX@84[VirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0PAX@84[Size]: 4
+COFF-I386: __CT??_R0PAX@84[CopyCtor]: null
+COFF-I386: __CT??_R0PQS@@H@88[Flags]: 1
+COFF-I386: __CT??_R0PQS@@H@88[Flags.ScalarType]: true
+COFF-I386: __CT??_R0PQS@@H@88[Flags.VirtualInheritance]: false
+COFF-I386: __CT??_R0PQS@@H@88[TypeDescriptor]: ??_R0PQS@@H@8
+COFF-I386: __CT??_R0PQS@@H@88[NonVirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0PQS@@H@88[VirtualBasePointerOffset]: -1
+COFF-I386: __CT??_R0PQS@@H@88[VirtualBaseAdjustmentOffset]: 0
+COFF-I386: __CT??_R0PQS@@H@88[Size]: 8
+COFF-I386: __CT??_R0PQS@@H@88[CopyCtor]: null
diff --git a/test/tools/llvm-cxxdump/trivial.test b/test/tools/llvm-cxxdump/trivial.test
new file mode 100644
index 000000000000..450ed3b3780d
--- /dev/null
+++ b/test/tools/llvm-cxxdump/trivial.test
@@ -0,0 +1,58 @@
+RUN: llvm-cxxdump %p/Inputs/trivial.obj.coff-i386 \
+RUN:   | FileCheck %s --check-prefix=COFF-I386
+
+RUN: llvm-cxxdump %p/Inputs/trivial.obj.elf-i386 \
+RUN:   | FileCheck %s --check-prefix=ELF-I386
+
+COFF-I386:      ??_7S@@6B@[0]: ??_R4S@@6B@
+COFF-I386-NEXT: ??_7S@@6B@[4]: ??_GS@@UAEPAXI@Z
+COFF-I386-NEXT: ??_8S@@7B@[0]: -4
+COFF-I386-NEXT: ??_8S@@7B@[4]: 4
+COFF-I386-NEXT: ??_R4S@@6B@[IsImageRelative]: 0
+COFF-I386-NEXT: ??_R4S@@6B@[OffsetToTop]: 0
+COFF-I386-NEXT: ??_R4S@@6B@[VFPtrOffset]: 0
+COFF-I386-NEXT: ??_R4S@@6B@[TypeDescriptor]: ??_R0?AUS@@@8
+COFF-I386-NEXT: ??_R4S@@6B@[ClassHierarchyDescriptor]: ??_R3S@@8
+COFF-I386-NEXT: ??_R3A@@8[AlwaysZero]: 0
+COFF-I386-NEXT: ??_R3A@@8[Flags]: 0
+COFF-I386-NEXT: ??_R3A@@8[NumClasses]: 1
+COFF-I386-NEXT: ??_R3A@@8[BaseClassArray]: ??_R2A@@8
+COFF-I386-NEXT: ??_R3S@@8[AlwaysZero]: 0
+COFF-I386-NEXT: ??_R3S@@8[Flags]: 0
+COFF-I386-NEXT: ??_R3S@@8[NumClasses]: 2
+COFF-I386-NEXT: ??_R3S@@8[BaseClassArray]: ??_R2S@@8
+COFF-I386-NEXT: ??_R2A@@8[0]: ??_R1A@?0A@EA@A@@8
+COFF-I386-NEXT: ??_R2S@@8[0]: ??_R1A@?0A@EA@S@@8
+COFF-I386-NEXT: ??_R2S@@8[4]: ??_R1A@33FA@A@@8
+COFF-I386-NEXT: ??_R1A@33FA@A@@8[TypeDescriptor]: ??_R0?AUA@@@8
+COFF-I386-NEXT: ??_R1A@33FA@A@@8[NumBases]: 0
+COFF-I386-NEXT: ??_R1A@33FA@A@@8[OffsetInVBase]: 0
+COFF-I386-NEXT: ??_R1A@33FA@A@@8[VBPtrOffset]: 4
+COFF-I386-NEXT: ??_R1A@33FA@A@@8[OffsetInVBTable]: 4
+COFF-I386-NEXT: ??_R1A@33FA@A@@8[Flags]: 80
+COFF-I386-NEXT: ??_R1A@33FA@A@@8[ClassHierarchyDescriptor]: ??_R3A@@8
+COFF-I386-NEXT: ??_R1A@?0A@EA@A@@8[TypeDescriptor]: ??_R0?AUA@@@8
+COFF-I386-NEXT: ??_R1A@?0A@EA@A@@8[NumBases]: 0
+COFF-I386-NEXT: ??_R1A@?0A@EA@A@@8[OffsetInVBase]: 0
+COFF-I386-NEXT: ??_R1A@?0A@EA@A@@8[VBPtrOffset]: -1
+COFF-I386-NEXT: ??_R1A@?0A@EA@A@@8[OffsetInVBTable]: 0
+COFF-I386-NEXT: ??_R1A@?0A@EA@A@@8[Flags]: 64
+COFF-I386-NEXT: ??_R1A@?0A@EA@A@@8[ClassHierarchyDescriptor]: ??_R3A@@8
+COFF-I386-NEXT: ??_R1A@?0A@EA@S@@8[TypeDescriptor]: ??_R0?AUS@@@8
+COFF-I386-NEXT: ??_R1A@?0A@EA@S@@8[NumBases]: 1
+COFF-I386-NEXT: ??_R1A@?0A@EA@S@@8[OffsetInVBase]: 0
+COFF-I386-NEXT: ??_R1A@?0A@EA@S@@8[VBPtrOffset]: -1
+COFF-I386-NEXT: ??_R1A@?0A@EA@S@@8[OffsetInVBTable]: 0
+COFF-I386-NEXT: ??_R1A@?0A@EA@S@@8[Flags]: 64
+COFF-I386-NEXT: ??_R1A@?0A@EA@S@@8[ClassHierarchyDescriptor]: ??_R3S@@8
+COFF-I386-NEXT: ??_R0?AUA@@@8[VFPtr]: ??_7type_info@@6B@
+COFF-I386-NEXT: ??_R0?AUA@@@8[AlwaysZero]: 0
+COFF-I386-NEXT: ??_R0?AUA@@@8[MangledName]: .?AUA@@
+COFF-I386-NEXT: ??_R0?AUS@@@8[VFPtr]: ??_7type_info@@6B@
+COFF-I386-NEXT: ??_R0?AUS@@@8[AlwaysZero]: 0
+COFF-I386-NEXT: ??_R0?AUS@@@8[MangledName]: .?AUS@@
+
+ELF-I386:      _ZTS1A: 1A
+ELF-I386-NEXT: _ZTV1A[0]: 0
+ELF-I386-NEXT: _ZTV1A[4]: _ZTI1A
+ELF-I386-NEXT: _ZTV1A[8]: _ZN1A1fEv
diff --git a/test/tools/llvm-objdump/AArch64/Inputs/link-opt-hints.macho-aarch64 b/test/tools/llvm-objdump/AArch64/Inputs/link-opt-hints.macho-aarch64
new file mode 100644
index 000000000000..12d33fcdf751
--- /dev/null
+++ b/test/tools/llvm-objdump/AArch64/Inputs/link-opt-hints.macho-aarch64
diff --git a/test/tools/llvm-objdump/AArch64/Inputs/print-mrs.obj.macho-aarch64 b/test/tools/llvm-objdump/AArch64/Inputs/print-mrs.obj.macho-aarch64
new file mode 100644
index 000000000000..06cb13d07daf
--- /dev/null
+++ b/test/tools/llvm-objdump/AArch64/Inputs/print-mrs.obj.macho-aarch64
diff --git a/test/tools/llvm-objdump/AArch64/macho-link-opt-hints.test b/test/tools/llvm-objdump/AArch64/macho-link-opt-hints.test
new file mode 100644
index 000000000000..932bc4fa8380
--- /dev/null
+++ b/test/tools/llvm-objdump/AArch64/macho-link-opt-hints.test
@@ -0,0 +1,11 @@
+RUN: llvm-objdump -m -link-opt-hints %p/Inputs/link-opt-hints.macho-aarch64 | FileCheck %s
+
+CHECK: Linker optimiztion hints (8 total bytes)
+CHECK:     identifier 8 AdrpLdrGot
+CHECK:     narguments 2
+CHECK: 	value 0x18
+CHECK: 	value 0x1c
+CHECK:     identifier 7 AdrpAdd
+CHECK:     narguments 2
+CHECK: 	value 0x6c
+CHECK: 	value 0x70
diff --git a/test/tools/llvm-objdump/AArch64/macho-print-mrs.test b/test/tools/llvm-objdump/AArch64/macho-print-mrs.test
new file mode 100644
index 000000000000..cc1d14faf8d3
--- /dev/null
+++ b/test/tools/llvm-objdump/AArch64/macho-print-mrs.test
@@ -0,0 +1,3 @@
+RUN: llvm-objdump -d -m -no-show-raw-insn %p/Inputs/print-mrs.obj.macho-aarch64 | FileCheck %s
+
+CHECK: 0:  mrs x0, S3_7_C15_C2_0
diff --git a/test/tools/llvm-objdump/ARM/Inputs/data-in-code.macho-arm b/test/tools/llvm-objdump/ARM/Inputs/data-in-code.macho-arm
new file mode 100644
index 000000000000..e826f29a233a
--- /dev/null
+++ b/test/tools/llvm-objdump/ARM/Inputs/data-in-code.macho-arm
diff --git a/test/tools/llvm-objdump/ARM/macho-data-in-code.test b/test/tools/llvm-objdump/ARM/macho-data-in-code.test
new file mode 100644
index 000000000000..c7a6da1d9504
--- /dev/null
+++ b/test/tools/llvm-objdump/ARM/macho-data-in-code.test
@@ -0,0 +1,16 @@
+RUN: llvm-objdump -m -data-in-code %p/Inputs/data-in-code.macho-arm | FileCheck %s
+RUN: llvm-objdump -m -data-in-code -non-verbose %p/Inputs/data-in-code.macho-arm | FileCheck %s -check-prefix=NON_VERBOSE
+
+CHECK: Data in code table (4 entries)
+CHECK: offset     length kind
+CHECK: 0x00000000      4 DATA
+CHECK: 0x00000004      4 JUMP_TABLE32
+CHECK: 0x00000008      2 JUMP_TABLE16
+CHECK: 0x0000000a      1 JUMP_TABLE8
+
+NON_VERBOSE: Data in code table (4 entries)
+NON_VERBOSE: offset     length kind
+NON_VERBOSE: 0x00000000      4 0x0001
+NON_VERBOSE: 0x00000004      4 0x0004
+NON_VERBOSE: 0x00000008      2 0x0003
+NON_VERBOSE: 0x0000000a      1 0x0002
diff --git a/test/tools/llvm-objdump/Inputs/common-symbol-elf b/test/tools/llvm-objdump/Inputs/common-symbol-elf
new file mode 100644
index 000000000000..9609edb041fe
--- /dev/null
+++ b/test/tools/llvm-objdump/Inputs/common-symbol-elf
diff --git a/test/tools/llvm-objdump/Inputs/proc-specific-section-elf b/test/tools/llvm-objdump/Inputs/proc-specific-section-elf
new file mode 100644
index 000000000000..7c3d613cb87a
--- /dev/null
+++ b/test/tools/llvm-objdump/Inputs/proc-specific-section-elf
diff --git a/test/tools/llvm-objdump/X86/Inputs/Objc1.32bit.exe.macho-i386 b/test/tools/llvm-objdump/X86/Inputs/Objc1.32bit.exe.macho-i386
new file mode 100755
index 000000000000..72b7ea83011a
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/Inputs/Objc1.32bit.exe.macho-i386
diff --git a/test/tools/llvm-objdump/X86/Inputs/Objc1.32bit.obj.macho-i386 b/test/tools/llvm-objdump/X86/Inputs/Objc1.32bit.obj.macho-i386
new file mode 100644
index 000000000000..7f62ad1daeab
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/Inputs/Objc1.32bit.obj.macho-i386
diff --git a/test/tools/llvm-objdump/X86/Inputs/Objc2.32bit.exe.macho-i386 b/test/tools/llvm-objdump/X86/Inputs/Objc2.32bit.exe.macho-i386
new file mode 100755
index 000000000000..b44c7dc58731
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/Inputs/Objc2.32bit.exe.macho-i386
diff --git a/test/tools/llvm-objdump/X86/Inputs/Objc2.32bit.obj.macho-i386 b/test/tools/llvm-objdump/X86/Inputs/Objc2.32bit.obj.macho-i386
new file mode 100644
index 000000000000..51449643fcdd
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/Inputs/Objc2.32bit.obj.macho-i386
diff --git a/test/tools/llvm-objdump/X86/Inputs/Objc2.64bit.exe.macho-x86_64 b/test/tools/llvm-objdump/X86/Inputs/Objc2.64bit.exe.macho-x86_64
new file mode 100755
index 000000000000..5cee0773604a
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/Inputs/Objc2.64bit.exe.macho-x86_64
diff --git a/test/tools/llvm-objdump/X86/Inputs/Objc2.64bit.obj.macho-x86_64 b/test/tools/llvm-objdump/X86/Inputs/Objc2.64bit.obj.macho-x86_64
new file mode 100644
index 000000000000..5734780a1643
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/Inputs/Objc2.64bit.obj.macho-x86_64
diff --git a/test/tools/llvm-objdump/X86/Inputs/dylibModInit.macho-x86_64 b/test/tools/llvm-objdump/X86/Inputs/dylibModInit.macho-x86_64
new file mode 100755
index 000000000000..a39424aab312
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/Inputs/dylibModInit.macho-x86_64
diff --git a/test/tools/llvm-objdump/X86/macho-archive-headers.test b/test/tools/llvm-objdump/X86/macho-archive-headers.test
new file mode 100644
index 000000000000..1253b46529b9
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-archive-headers.test
@@ -0,0 +1,28 @@
+RUN: llvm-objdump %p/Inputs/macho-universal-archive.x86_64.i386 -macho -archive-headers -arch all \
+RUN: | FileCheck %s
+RUN: llvm-objdump %p/Inputs/macho-universal-archive.x86_64.i386 -macho -archive-headers -arch all -archive-member-offsets \
+RUN: | FileCheck %s -check-prefix=OFFSETS
+RUN: llvm-objdump %p/Inputs/macho-universal-archive.x86_64.i386 -macho -archive-headers -arch all -non-verbose \
+RUN: | FileCheck %s -check-prefix=NON-VERBOSE
+
+# Note the date as printed by ctime(3) is time zone dependent and not checked.
+CHECK: Archive : {{.*}}/macho-universal-archive.x86_64.i386 (architecture x86_64)
+CHECK: -rw-r--r--124/11     44 {{.*}} __.SYMDEF SORTED
+CHECK: -rw-r--r--124/0     860 {{.*}} hello.o
+CHECK: Archive : {{.*}}/macho-universal-archive.x86_64.i386 (architecture i386)
+CHECK: -rw-r--r--124/11     60 {{.*}} __.SYMDEF SORTED
+CHECK: -rw-r--r--124/0     388 {{.*}} foo.o
+
+OFFSETS: Archive : {{.*}}/macho-universal-archive.x86_64.i386 (architecture x86_64)
+OFFSETS: 8	-rw-r--r--124/11     44 {{.*}} __.SYMDEF SORTED
+OFFSETS: 112	-rw-r--r--124/0     860 {{.*}} hello.o
+OFFSETS: Archive : {{.*}}/macho-universal-archive.x86_64.i386 (architecture i386)
+OFFSETS: 8	-rw-r--r--124/11     60 {{.*}} __.SYMDEF SORTED
+OFFSETS: 128	-rw-r--r--124/0     388 {{.*}} foo.o
+
+NON-VERBOSE: Archive : {{.*}}/macho-universal-archive.x86_64.i386 (architecture x86_64)
+NON-VERBOSE: 0100644 124/11     44 1399572709 #1/20
+NON-VERBOSE: 0100644 124/0     860 1399501499 #1/12
+NON-VERBOSE: Archive : {{.*}}/macho-universal-archive.x86_64.i386 (architecture i386)
+NON-VERBOSE: 0100644 124/11     60 1399572709 #1/20
+NON-VERBOSE: 0100644 124/0     388 1399572697 #1/12
diff --git a/test/tools/llvm-objdump/X86/macho-cstring-dump.test b/test/tools/llvm-objdump/X86/macho-cstring-dump.test
new file mode 100644
index 000000000000..0e19f51d6a63
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-cstring-dump.test
@@ -0,0 +1,13 @@
+RUN: llvm-objdump -m -section __TEXT,__cstring %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
+RUN: llvm-objdump -m -section __TEXT,__cstring -no-leading-addr %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s -check-prefix=NO_ADDR
+RUN: llvm-objdump -m -section __TEXT,__cstring -non-verbose %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s -check-prefix=NON_VERBOSE
+
+CHECK: Contents of (__TEXT,__cstring) section
+CHECK: 000000000000003b  Hello world\n
+
+NO_ADDR: Contents of (__TEXT,__cstring) section
+NO_ADDR: Hello world\n
+NO_ADDR-NOT: 000000000000003b
+
+NON_VERBOSE: Contents of (__TEXT,__cstring) section
+NON_VERBOSE: 000000000000003b	48 65 6c 6c 6f 20 77 6f 72 6c 64 0a 00 
diff --git a/test/tools/llvm-objdump/X86/macho-dis-no-leading-addr.test b/test/tools/llvm-objdump/X86/macho-dis-no-leading-addr.test
new file mode 100644
index 000000000000..df4618dc4681
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-dis-no-leading-addr.test
@@ -0,0 +1,24 @@
+# RUN: llvm-objdump -m -d %p/Inputs/hello.obj.macho-x86_64 -no-show-raw-insn -print-imm-hex -no-leading-addr | FileCheck %s
+
+# CHECK: (__TEXT,__text) section
+# CHECK: _main:
+# CHECK: 	pushq	%rbp
+# CHECK: 	movq	%rsp, %rbp
+# CHECK: 	subq	$0x20, %rsp
+# CHECK: 	leaq	L_.str(%rip), %rax ## literal pool for: "Hello world\n"
+# CHECK: 	movl	$_main, -0x4(%rbp)
+# CHECK: 	movl	%edi, -0x8(%rbp)
+# CHECK: 	movq	%rsi, -0x10(%rbp)
+# CHECK: 	movq	%rdx, -0x18(%rbp)
+# CHECK: 	movq	%rax, %rdi
+# CHECK: 	movb	$0x0, %al
+# CHECK: 	callq	_printf
+# CHECK: 	movl	$_main, %ecx
+# CHECK: 	movl	%eax, -0x1c(%rbp)
+# CHECK: 	movl	%ecx, %eax
+# CHECK: 	addq	$0x20, %rsp
+# CHECK: 	popq	%rbp
+# CHECK: 	retq
+
+# CHECK-NOT: 0:
+# CHECK-NOT: 0000000000000000
diff --git a/test/tools/llvm-objdump/X86/macho-dis-symname.test b/test/tools/llvm-objdump/X86/macho-dis-symname.test
new file mode 100644
index 000000000000..39d16ecba6f8
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-dis-symname.test
@@ -0,0 +1,19 @@
+# RUN: llvm-objdump -m -d %p/Inputs/exeThread.macho-x86_64 -dis-symname start -no-show-raw-insn -full-leading-addr -print-imm-hex | FileCheck %s
+
+# CHECK: (__TEXT,__text) section
+# CHECK: start:
+# CHECK: 0000000100000d00	pushq	$0x0
+# CHECK: 0000000100000d02	movq	%rsp, %rbp
+# CHECK: 0000000100000d05	andq	$-0x10, %rsp
+# CHECK: 0000000100000d09	movq	0x8(%rbp), %rdi
+# CHECK: 0000000100000d0d	leaq	0x10(%rbp), %rsi
+# CHECK: 0000000100000d11	movl	%edi, %edx
+# CHECK: 0000000100000d13	addl	$0x1, %edx
+# CHECK: 0000000100000d16	shll	$0x3, %edx
+# CHECK: 0000000100000d19	addq	%rsi, %rdx
+# CHECK: 0000000100000d1c	callq	__start
+# CHECK: 0000000100000d21	hlt
+
+# CHECK-NOT: __start:
+# CHECK-NOT: 0000000100000d22
+# CHECK-NOT: _main:
diff --git a/test/tools/llvm-objdump/X86/macho-dylib.test b/test/tools/llvm-objdump/X86/macho-dylib.test
new file mode 100644
index 000000000000..0e31b8b930e6
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-dylib.test
@@ -0,0 +1,6 @@
+RUN: llvm-objdump -m -dylibs-used %p/Inputs/hello.exe.macho-x86_64 | FileCheck %s -check-prefix=USED
+RUN: llvm-objdump -m -dylib-id %p/Inputs/dylibLoadKinds.macho-x86_64 | FileCheck %s -check-prefix=ID
+
+USED: /usr/lib/libSystem.B.dylib (compatibility version 1.0.0, current version 1197.1.1)
+
+ID: /usr/lib/foo.dylib
diff --git a/test/tools/llvm-objdump/X86/macho-indirect-symbols.test b/test/tools/llvm-objdump/X86/macho-indirect-symbols.test
new file mode 100644
index 000000000000..fdc465ad5425
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-indirect-symbols.test
@@ -0,0 +1,24 @@
+RUN: llvm-objdump -macho -indirect-symbols %p/Inputs/hello.exe.macho-x86_64 | FileCheck %s
+RUN: llvm-objdump -macho -indirect-symbols -non-verbose %p/Inputs/hello.exe.macho-x86_64 | FileCheck %s -check-prefix=NON_VERBOSE
+
+CHECK: Indirect symbols for (__TEXT,__stubs) 1 entries
+CHECK: address            index name
+CHECK: 0x0000000100000f6c     2 _printf
+CHECK: Indirect symbols for (__DATA,__nl_symbol_ptr) 2 entries
+CHECK: address            index name
+CHECK: 0x0000000100001000     3 dyld_stub_binder
+CHECK: 0x0000000100001008 ABSOLUTE
+CHECK: Indirect symbols for (__DATA,__la_symbol_ptr) 1 entries
+CHECK: address            index name
+CHECK: 0x0000000100001010     2 _printf
+
+NON_VERBOSE: Indirect symbols for (__TEXT,__stubs) 1 entries
+NON_VERBOSE: address            index
+NON_VERBOSE: 0x0000000100000f6c     2 
+NON_VERBOSE: Indirect symbols for (__DATA,__nl_symbol_ptr) 2 entries
+NON_VERBOSE: address            index
+NON_VERBOSE: 0x0000000100001000     3 
+NON_VERBOSE: 0x0000000100001008 ABSOLUTE
+NON_VERBOSE: Indirect symbols for (__DATA,__la_symbol_ptr) 1 entries
+NON_VERBOSE: address            index
+NON_VERBOSE: 0x0000000100001010     2 
diff --git a/test/tools/llvm-objdump/X86/macho-info-plist.test b/test/tools/llvm-objdump/X86/macho-info-plist.test
new file mode 100644
index 000000000000..bee1952ce9b8
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-info-plist.test
@@ -0,0 +1,7 @@
+# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -info-plist - | FileCheck %s
+
+.section __TEXT, __info_plist
+.asciz "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n"
+
+# CHECK: Contents of (__TEXT,__info_plist) section
+# CHECK: <?xml version="1.0" encoding="UTF-8"?>
diff --git a/test/tools/llvm-objdump/X86/macho-literal-pointers-i386.test b/test/tools/llvm-objdump/X86/macho-literal-pointers-i386.test
new file mode 100644
index 000000000000..62ed607c8ee5
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-literal-pointers-i386.test
@@ -0,0 +1,39 @@
+# RUN: llvm-mc < %s -triple i386-apple-darwin -filetype=obj | llvm-objdump -m -section __DATA,__litp - | FileCheck %s
+# RUN: llvm-mc < %s -triple i386-apple-darwin -filetype=obj | llvm-objdump -m -section __DATA,__litp -non-verbose - | FileCheck %s -check-prefix=NON-VERBOSE
+
+.cstring
+L1: .asciz "Hello world\n"
+
+.literal4
+.align 2
+L2: .float 4.0
+
+.literal8
+.align 3
+L3: .double 8.0
+
+.literal16
+.align 4
+L4: .long 0x10000016, 0x20000016, 0x30000016, 0x40000016
+
+.const
+L5: .asciz "const non-literal string"
+
+.section __DATA,__litp, literal_pointers
+.align 2
+.long L1
+.long L2
+.long L3
+.long L4
+.long L5
+
+# CHECK: Contents of (__DATA,__litp) section
+# CHECK: 0000004c  __TEXT:__cstring:Hello world\n
+# CHECK: 00000050  __TEXT:__literal4:0x40800000
+# CHECK: 00000054  __TEXT:__literal8:0x00000000 0x40200000
+# CHECK: 00000058  __TEXT:__literal16:0x10000016 0x20000016 0x30000016 0x40000016
+# CHECK: 0000005c  0x30 (not in a literal section)
+
+# NON-VERBOSE: Contents of (__DATA,__litp) section
+# NON-VERBOSE: 0000004c	00 00 00 00 10 00 00 00 18 00 00 00 20 00 00 00 
+# NON-VERBOSE: 0000005c	30 00 00 00 
diff --git a/test/tools/llvm-objdump/X86/macho-literal-pointers-x86_64.test b/test/tools/llvm-objdump/X86/macho-literal-pointers-x86_64.test
new file mode 100644
index 000000000000..f1912e8861cb
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-literal-pointers-x86_64.test
@@ -0,0 +1,40 @@
+# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __DATA,__litp - | FileCheck %s
+# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __DATA,__litp -non-verbose - | FileCheck %s -check-prefix=NON-VERBOSE
+
+.cstring
+L1: .asciz "Hello world\n"
+
+.literal4
+.align 2
+L2: .float 4.0
+
+.literal8
+.align 3
+L3: .double 8.0
+
+.literal16
+.align 4
+L4: .long 0x10000016, 0x20000016, 0x30000016, 0x40000016
+
+.const
+L5: .asciz "const non-literal string"
+
+.section __DATA,__litp, literal_pointers
+.align 3
+.quad L1
+.quad L2
+.quad L3
+.quad L4
+.quad L5
+
+# CHECK: Contents of (__DATA,__litp) section
+# CHECK: 0000000000000050  __TEXT:__cstring:Hello world\n
+# CHECK: 0000000000000058  __TEXT:__literal4:0x40800000
+# CHECK: 0000000000000060  __TEXT:__literal8:0x00000000 0x40200000
+# CHECK: 0000000000000068  __TEXT:__literal16:0x10000016 0x20000016 0x30000016 0x40000016
+# CHECK: 0000000000000070  0x30 (not in a literal section)
+
+# NON-VERBOSE: Contents of (__DATA,__litp) section
+# NON-VERBOSE: 0000000000000050	00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 
+# NON-VERBOSE: 0000000000000060	18 00 00 00 00 00 00 00 20 00 00 00 00 00 00 00 
+# NON-VERBOSE: 0000000000000070	30 00 00 00 00 00 00 00 
diff --git a/test/tools/llvm-objdump/X86/macho-literals.test b/test/tools/llvm-objdump/X86/macho-literals.test
new file mode 100644
index 000000000000..d93ae679f348
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-literals.test
@@ -0,0 +1,63 @@
+# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __TEXT,__literal4 - | FileCheck %s -check-prefix=CHECK-LIT4
+# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __TEXT,__literal4 -non-verbose - | FileCheck %s -check-prefix=NON-VERBOSE-LIT4
+# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __TEXT,__literal8 - | FileCheck %s -check-prefix=CHECK-LIT8
+# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __TEXT,__literal8 -non-verbose - | FileCheck %s -check-prefix=NON-VERBOSE-LIT8
+# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __TEXT,__literal16 - | FileCheck %s -check-prefix=CHECK-LIT16
+# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __TEXT,__literal16 -non-verbose - | FileCheck %s -check-prefix=NON-VERBOSE-LIT16
+
+.literal4
+.float 2.5
+.float 8.25
+.long 0x7f800000
+.long 0xff800000
+.long 0x7fc00000
+.long 0x7f800001
+
+# CHECK-LIT4: Contents of (__TEXT,__literal4) section
+# CHECK-LIT4: 0000000000000000  0x40200000
+# CHECK-LIT4: 0000000000000004  0x41040000
+# CHECK-LIT4: 0000000000000008  0x7f800000
+# CHECK-LIT4: 000000000000000c  0xff800000
+# CHECK-LIT4: 0000000000000010  0x7fc00000
+# CHECK-LIT4: 0000000000000014  0x7f800001
+
+# NON-VERBOSE-LIT4: Contents of (__TEXT,__literal4) section
+# NON-VERBOSE-LIT4: 0000000000000000	00 00 20 40 00 00 04 41 00 00 80 7f 00 00 80 ff 
+# NON-VERBOSE-LIT4: 0000000000000010	00 00 c0 7f 01 00 80 7f 
+
+.literal8
+.double 2.5
+.double 8.25
+.long 0
+.long 0x7ff00000
+.long 0
+.long 0xfff00000
+.long 0
+.long 0x7ff80000
+.long 1
+.long 0x7ff00000
+
+# CHECK-LIT8: Contents of (__TEXT,__literal8) section
+# CHECK-LIT8: 0000000000000018  0x00000000 0x40040000
+# CHECK-LIT8: 0000000000000020  0x00000000 0x40208000
+# CHECK-LIT8: 0000000000000028  0x00000000 0x7ff00000
+# CHECK-LIT8: 0000000000000030  0x00000000 0xfff00000
+# CHECK-LIT8: 0000000000000038  0x00000000 0x7ff80000
+# CHECK-LIT8: 0000000000000040  0x00000001 0x7ff00000
+
+# NON-VERBOSE-LIT8: Contents of (__TEXT,__literal8) section
+# NON-VERBOSE-LIT8: 0000000000000018	00 00 00 00 00 00 04 40 00 00 00 00 00 80 20 40 
+# NON-VERBOSE-LIT8: 0000000000000028	00 00 00 00 00 00 f0 7f 00 00 00 00 00 00 f0 ff 
+# NON-VERBOSE-LIT8: 0000000000000038	00 00 00 00 00 00 f8 7f 01 00 00 00 00 00 f0 7f 
+
+.literal16
+.long 1
+.long 2
+.long 3
+.long 4
+
+# CHECK-LIT16: Contents of (__TEXT,__literal16) section
+# CHECK-LIT16: 0000000000000050  0x00000001 0x00000002 0x00000003 0x00000004
+
+# NON-VERBOSE-LIT16: Contents of (__TEXT,__literal16) section
+# NON-VERBOSE-LIT16: 0000000000000050	01 00 00 00 02 00 00 00 03 00 00 00 04 00 00 00 
diff --git a/test/tools/llvm-objdump/X86/macho-nontext-disasm.test b/test/tools/llvm-objdump/X86/macho-nontext-disasm.test
new file mode 100644
index 000000000000..27b7bb441520
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-nontext-disasm.test
@@ -0,0 +1,9 @@
+# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __FOO,__bar -full-leading-addr -print-imm-hex -no-show-raw-insn - | FileCheck %s
+
+.section __FOO, __bar
+_foo:
+	nop
+
+# CHECK: Contents of (__FOO,__bar) section
+# CHECK: _foo:
+# CHECK: 0000000000000000	nop
diff --git a/test/tools/llvm-objdump/X86/macho-objc-meta-data.test b/test/tools/llvm-objdump/X86/macho-objc-meta-data.test
new file mode 100644
index 000000000000..f4abf6cdb49e
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-objc-meta-data.test
@@ -0,0 +1,1039 @@
+# RUN: llvm-objdump -m -objc-meta-data %p/Inputs/Objc2.64bit.exe.macho-x86_64 | FileCheck %s -check-prefix=OBJC2_64BIT_EXE
+# RUN: llvm-objdump -m -objc-meta-data %p/Inputs/Objc2.64bit.obj.macho-x86_64 | FileCheck %s -check-prefix=OBJC2_64BIT_OBJ
+# RUN: llvm-objdump -m -objc-meta-data %p/Inputs/Objc2.32bit.exe.macho-i386 | FileCheck %s -check-prefix=OBJC2_32BIT_EXE
+# RUN: llvm-objdump -m -objc-meta-data %p/Inputs/Objc2.32bit.obj.macho-i386 | FileCheck %s -check-prefix=OBJC2_32BIT_OBJ
+# RUN: llvm-objdump -m -objc-meta-data %p/Inputs/Objc1.32bit.exe.macho-i386 | FileCheck %s -check-prefix=OBJC1_32BIT_EXE
+# RUN: llvm-objdump -m -objc-meta-data %p/Inputs/Objc1.32bit.obj.macho-i386 | FileCheck %s -check-prefix=OBJC1_32BIT_OBJ
+# RUN: llvm-objdump -m -section __OBJC,__protocol %p/Inputs/Objc1.32bit.exe.macho-i386 | FileCheck %s -check-prefix=PROTOCOL
+
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+OBJC2_64BIT_EXE: 0000000100002028 0x1000029f0
+OBJC2_64BIT_EXE:            isa 0x100002a18
+OBJC2_64BIT_EXE:     superclass 0x0
+OBJC2_64BIT_EXE:          cache 0x0
+OBJC2_64BIT_EXE:         vtable 0x0
+OBJC2_64BIT_EXE:           data 0x1000020d0 (struct class_ro_t *)
+OBJC2_64BIT_EXE:                     flags 0x80
+OBJC2_64BIT_EXE:             instanceStart 100
+OBJC2_64BIT_EXE:              instanceSize 100
+OBJC2_64BIT_EXE:                  reserved 0x0
+OBJC2_64BIT_EXE:                ivarLayout 0x0
+OBJC2_64BIT_EXE:                      name 0x100001b0e ViewController
+OBJC2_64BIT_EXE:               baseMethods 0x100002098 (struct method_list_t *)
+OBJC2_64BIT_EXE: 		   entsize 24
+OBJC2_64BIT_EXE: 		     count 2
+OBJC2_64BIT_EXE: 		      name 0x1000014ee viewDidLoad
+OBJC2_64BIT_EXE: 		     types 0x100001b48 v16@0:8
+OBJC2_64BIT_EXE: 		       imp 0x100001350 
+OBJC2_64BIT_EXE: 		      name 0x1000014fa setRepresentedObject:
+OBJC2_64BIT_EXE: 		     types 0x100001b50 v24@0:8@16
+OBJC2_64BIT_EXE: 		       imp 0x100001390 
+OBJC2_64BIT_EXE:             baseProtocols 0x0
+OBJC2_64BIT_EXE:                     ivars 0x0
+OBJC2_64BIT_EXE:            weakIvarLayout 0x0
+OBJC2_64BIT_EXE:            baseProperties 0x0
+OBJC2_64BIT_EXE: Meta Class
+OBJC2_64BIT_EXE:            isa 0x0
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+OBJC2_64BIT_EXE:          cache 0x0
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+OBJC2_64BIT_EXE:                     flags 0x81 RO_META
+OBJC2_64BIT_EXE:             instanceStart 40
+OBJC2_64BIT_EXE:              instanceSize 40
+OBJC2_64BIT_EXE:                  reserved 0x0
+OBJC2_64BIT_EXE:                ivarLayout 0x0
+OBJC2_64BIT_EXE:                      name 0x100001b0e ViewController
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+OBJC2_64BIT_EXE:            baseProperties 0x0
+OBJC2_64BIT_EXE: 0000000100002030 0x100002a68
+OBJC2_64BIT_EXE:            isa 0x100002a40
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+OBJC2_64BIT_EXE:               baseMethods 0x100002910 (struct method_list_t *)
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+OBJC2_64BIT_EXE: 		     count 2
+OBJC2_64BIT_EXE: 		      name 0x100001885 applicationDidFinishLaunching:
+OBJC2_64BIT_EXE: 		     types 0x100001b50 v24@0:8@16
+OBJC2_64BIT_EXE: 		       imp 0x100001430 
+OBJC2_64BIT_EXE: 		      name 0x100001999 applicationWillTerminate:
+OBJC2_64BIT_EXE: 		     types 0x100001b50 v24@0:8@16
+OBJC2_64BIT_EXE: 		       imp 0x100001470 
+OBJC2_64BIT_EXE:             baseProtocols 0x1000028b0
+OBJC2_64BIT_EXE:                       count 1
+OBJC2_64BIT_EXE: 		      list[0] 0x100002ae0 (struct protocol_t *)
+OBJC2_64BIT_EXE: 			      isa 0x0
+OBJC2_64BIT_EXE: 			     name 0x100001b29 NSApplicationDelegate
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+OBJC2_64BIT_EXE:                     entsize 16
+OBJC2_64BIT_EXE:                       count 4
+OBJC2_64BIT_EXE: 			     name 0x100001f25 hash
+OBJC2_64BIT_EXE: 			attributes 0x100001f2a TQ,R
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+OBJC2_64BIT_EXE: 			attributes 0x100001f3a T#,R
+OBJC2_64BIT_EXE: 			     name 0x100001f3f description
+OBJC2_64BIT_EXE: 			attributes 0x100001f4b T@"NSString",R,C
+OBJC2_64BIT_EXE: 			     name 0x100001f5c debugDescription
+OBJC2_64BIT_EXE: 			attributes 0x100001f4b T@"NSString",R,C
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+OBJC2_64BIT_EXE:                  reserved 0x0
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+OBJC2_64BIT_EXE: Contents of (__DATA,__objc_superrefs) section
+OBJC2_64BIT_EXE: 00000001000029e8 0x1000029f0
+OBJC2_64BIT_EXE: Contents of (__DATA,__objc_protolist) section
+OBJC2_64BIT_EXE: 0000000100002038 0x100002a90
+OBJC2_64BIT_EXE: 0000000100002040 0x100002ae0
+OBJC2_64BIT_EXE: Contents of (__DATA,__objc_imageinfo) section
+OBJC2_64BIT_EXE:   version 0
+OBJC2_64BIT_EXE:     flags 0x0
+
+OBJC2_64BIT_OBJ: Contents of (__DATA,__objc_classlist) section
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+OBJC2_64BIT_OBJ: 		       imp -[AppDelegate applicationDidFinishLaunching:]
+OBJC2_64BIT_OBJ: 		      name 0xbac applicationWillTerminate:
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+OBJC2_64BIT_OBJ: 		       imp -[AppDelegate applicationWillTerminate:]
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+OBJC2_64BIT_OBJ: 			attributes 0x19de T@"NSString",R,C
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+OBJC1_32BIT_OBJ: 		  version 0x00000000
+OBJC1_32BIT_OBJ: 		     info 0x00000002 CLS_META
+OBJC1_32BIT_OBJ: 	    instance_size 0x00000030
+OBJC1_32BIT_OBJ: 		    ivars 0x00000000 (not in an __OBJC section)
+OBJC1_32BIT_OBJ: 		  methods 0x00000000 (not in an __OBJC section)
+OBJC1_32BIT_OBJ: 		    cache 0x00000000
+OBJC1_32BIT_OBJ: 		protocols 0x00000000 (not in an __OBJC section)
+OBJC1_32BIT_OBJ: Contents of (__OBJC,__image_info) section
+OBJC1_32BIT_OBJ:   version 0
+OBJC1_32BIT_OBJ:     flags 0x0 RR
+
+PROTOCOL: Contents of (__OBJC,__protocol) section
+PROTOCOL: Protocol 0x437c
+PROTOCOL:               isa 0x00003120
+PROTOCOL:     protocol_name 0x000025af NSObject
+PROTOCOL:     protocol_list 0x00000000 (not in an __OBJC section)
+PROTOCOL:  instance_methods 0x00004290
+PROTOCOL:         count 19
+PROTOCOL:         list[0]
+PROTOCOL:              name 0x00002de9 isEqual:
+PROTOCOL:             types 0x000026e7 c12@0:4@8
+PROTOCOL:         list[1]
+PROTOCOL:              name 0x00002df2 class
+PROTOCOL:             types 0x00002df8 #8@0:4
+PROTOCOL:         list[2]
+PROTOCOL:              name 0x00002dff self
+PROTOCOL:             types 0x00002e04 @8@0:4
+PROTOCOL:         list[3]
+PROTOCOL:              name 0x00002e0b performSelector:
+PROTOCOL:             types 0x00002e1c @12@0:4:8
+PROTOCOL:         list[4]
+PROTOCOL:              name 0x00002e26 performSelector:withObject:
+PROTOCOL:             types 0x00002e42 @16@0:4:8@12
+PROTOCOL:         list[5]
+PROTOCOL:              name 0x00002e4f performSelector:withObject:withObject:
+PROTOCOL:             types 0x00002e76 @20@0:4:8@12@16
+PROTOCOL:         list[6]
+PROTOCOL:              name 0x00002e86 isProxy
+PROTOCOL:             types 0x00002e8e c8@0:4
+PROTOCOL:         list[7]
+PROTOCOL:              name 0x00002e95 isKindOfClass:
+PROTOCOL:             types 0x00002ea4 c12@0:4#8
+PROTOCOL:         list[8]
+PROTOCOL:              name 0x00002eae isMemberOfClass:
+PROTOCOL:             types 0x00002ea4 c12@0:4#8
+PROTOCOL:         list[9]
+PROTOCOL:              name 0x00002ebf conformsToProtocol:
+PROTOCOL:             types 0x000026e7 c12@0:4@8
+PROTOCOL:         list[10]
+PROTOCOL:              name 0x00002ee7 respondsToSelector:
+PROTOCOL:             types 0x00002efb c12@0:4:8
+PROTOCOL:         list[11]
+PROTOCOL:              name 0x00002f05 retain
+PROTOCOL:             types 0x00002e04 @8@0:4
+PROTOCOL:         list[12]
+PROTOCOL:              name 0x00002f0c release
+PROTOCOL:             types 0x00002f14 Vv8@0:4
+PROTOCOL:         list[13]
+PROTOCOL:              name 0x00002f1c autorelease
+PROTOCOL:             types 0x00002e04 @8@0:4
+PROTOCOL:         list[14]
+PROTOCOL:              name 0x00002f28 retainCount
+PROTOCOL:             types 0x00002f34 I8@0:4
+PROTOCOL:         list[15]
+PROTOCOL:              name 0x00002f3b zone
+PROTOCOL:             types 0x00002f40 ^{_NSZone=}8@0:4
+PROTOCOL:         list[16]
+PROTOCOL:              name 0x00002f51 hash
+PROTOCOL:             types 0x00002f34 I8@0:4
+PROTOCOL:         list[17]
+PROTOCOL:              name 0x00002f56 superclass
+PROTOCOL:             types 0x00002df8 #8@0:4
+PROTOCOL:         list[18]
+PROTOCOL:              name 0x00002f61 description
+PROTOCOL:             types 0x00002e04 @8@0:4
+PROTOCOL:     class_methods 0x00000000 (not in an __OBJC section)
+PROTOCOL: Protocol 0x4390
+PROTOCOL:               isa 0x000030b0
+PROTOCOL:     protocol_name 0x00002dd3 NSApplicationDelegate
+PROTOCOL:     protocol_list 0x000043a4
+PROTOCOL:              next 0x00000000
+PROTOCOL:             count 1
+PROTOCOL:           list[0] 0x0000437c
+PROTOCOL:                   isa 0x00003120
+PROTOCOL:         protocol_name 0x000025af NSObject
+PROTOCOL:         protocol_list 0x00000000 (not in an __OBJC section)
+PROTOCOL:      instance_methods 0x00004290
+PROTOCOL:             count 19
+PROTOCOL:             list[0]
+PROTOCOL:                  name 0x00002de9 isEqual:
+PROTOCOL:                 types 0x000026e7 c12@0:4@8
+PROTOCOL:             list[1]
+PROTOCOL:                  name 0x00002df2 class
+PROTOCOL:                 types 0x00002df8 #8@0:4
+PROTOCOL:             list[2]
+PROTOCOL:                  name 0x00002dff self
+PROTOCOL:                 types 0x00002e04 @8@0:4
+PROTOCOL:             list[3]
+PROTOCOL:                  name 0x00002e0b performSelector:
+PROTOCOL:                 types 0x00002e1c @12@0:4:8
+PROTOCOL:             list[4]
+PROTOCOL:                  name 0x00002e26 performSelector:withObject:
+PROTOCOL:                 types 0x00002e42 @16@0:4:8@12
+PROTOCOL:             list[5]
+PROTOCOL:                  name 0x00002e4f performSelector:withObject:withObject:
+PROTOCOL:                 types 0x00002e76 @20@0:4:8@12@16
+PROTOCOL:             list[6]
+PROTOCOL:                  name 0x00002e86 isProxy
+PROTOCOL:                 types 0x00002e8e c8@0:4
+PROTOCOL:             list[7]
+PROTOCOL:                  name 0x00002e95 isKindOfClass:
+PROTOCOL:                 types 0x00002ea4 c12@0:4#8
+PROTOCOL:             list[8]
+PROTOCOL:                  name 0x00002eae isMemberOfClass:
+PROTOCOL:                 types 0x00002ea4 c12@0:4#8
+PROTOCOL:             list[9]
+PROTOCOL:                  name 0x00002ebf conformsToProtocol:
+PROTOCOL:                 types 0x000026e7 c12@0:4@8
+PROTOCOL:             list[10]
+PROTOCOL:                  name 0x00002ee7 respondsToSelector:
+PROTOCOL:                 types 0x00002efb c12@0:4:8
+PROTOCOL:             list[11]
+PROTOCOL:                  name 0x00002f05 retain
+PROTOCOL:                 types 0x00002e04 @8@0:4
+PROTOCOL:             list[12]
+PROTOCOL:                  name 0x00002f0c release
+PROTOCOL:                 types 0x00002f14 Vv8@0:4
+PROTOCOL:             list[13]
+PROTOCOL:                  name 0x00002f1c autorelease
+PROTOCOL:                 types 0x00002e04 @8@0:4
+PROTOCOL:             list[14]
+PROTOCOL:                  name 0x00002f28 retainCount
+PROTOCOL:                 types 0x00002f34 I8@0:4
+PROTOCOL:             list[15]
+PROTOCOL:                  name 0x00002f3b zone
+PROTOCOL:                 types 0x00002f40 ^{_NSZone=}8@0:4
+PROTOCOL:             list[16]
+PROTOCOL:                  name 0x00002f51 hash
+PROTOCOL:                 types 0x00002f34 I8@0:4
+PROTOCOL:             list[17]
+PROTOCOL:                  name 0x00002f56 superclass
+PROTOCOL:                 types 0x00002df8 #8@0:4
+PROTOCOL:             list[18]
+PROTOCOL:                  name 0x00002f61 description
+PROTOCOL:                 types 0x00002e04 @8@0:4
+PROTOCOL:         class_methods 0x00000000 (not in an __OBJC section)
+PROTOCOL:  instance_methods 0x00000000 (not in an __OBJC section)
+PROTOCOL:     class_methods 0x00000000 (not in an __OBJC section)
diff --git a/test/tools/llvm-objdump/X86/macho-private-headers.test b/test/tools/llvm-objdump/X86/macho-private-headers.test
index c80bb083af37..ff45b1823fff 100644
--- a/test/tools/llvm-objdump/X86/macho-private-headers.test
+++ b/test/tools/llvm-objdump/X86/macho-private-headers.test
@@ -19,6 +19,8 @@
 // RUN:     | FileCheck %s -check-prefix=THREAD
 // RUN: llvm-objdump -macho -p -arch i386 %p/Inputs/macho-universal.x86_64.i386 \
 // RUN:     | FileCheck %s -check-prefix=FATi386
+// RUN: llvm-objdump -p -non-verbose %p/Inputs/hello.obj.macho-x86_64 \
+// RUN:     | FileCheck %s -check-prefix=NON_VERBOSE
 
 CHECK: Mach header
 CHECK:       magic cputype cpusubtype  caps    filetype ncmds sizeofcmds      flags
@@ -443,3 +445,95 @@ THREAD:     gs  0x0000000000000000
 FATi386: Mach header
 FATi386:       magic cputype cpusubtype  caps    filetype ncmds sizeofcmds      flags
 FATi386:    MH_MAGIC    I386        ALL  0x00     EXECUTE    16        716   NOUNDEFS DYLDLINK TWOLEVEL PIE MH_NO_HEAP_EXECUTION
+
+NON_VERBOSE: Mach header
+NON_VERBOSE:       magic cputype cpusubtype  caps    filetype ncmds sizeofcmds      flags
+NON_VERBOSE:  0xfeedfacf 16777223          3  0x00           1     3        496 0x00002000
+NON_VERBOSE: Load command 0
+NON_VERBOSE:       cmd LC_SEGMENT_64
+NON_VERBOSE:   cmdsize 392
+NON_VERBOSE:   segname 
+NON_VERBOSE:    vmaddr 0x0000000000000000
+NON_VERBOSE:    vmsize 0x00000000000000a8
+NON_VERBOSE:   fileoff 528
+NON_VERBOSE:  filesize 168
+NON_VERBOSE:   maxprot 0x00000007
+NON_VERBOSE:  initprot 0x00000007
+NON_VERBOSE:    nsects 4
+NON_VERBOSE:     flags 0x0
+NON_VERBOSE: Section
+NON_VERBOSE:   sectname __text
+NON_VERBOSE:    segname __TEXT
+NON_VERBOSE:       addr 0x0000000000000000
+NON_VERBOSE:       size 0x000000000000003b
+NON_VERBOSE:     offset 528
+NON_VERBOSE:      align 2^4 (16)
+NON_VERBOSE:     reloff 696
+NON_VERBOSE:     nreloc 2
+NON_VERBOSE:      flags 0x80000400
+NON_VERBOSE:  reserved1 0
+NON_VERBOSE:  reserved2 0
+NON_VERBOSE: Section
+NON_VERBOSE:   sectname __cstring
+NON_VERBOSE:    segname __TEXT
+NON_VERBOSE:       addr 0x000000000000003b
+NON_VERBOSE:       size 0x000000000000000d
+NON_VERBOSE:     offset 587
+NON_VERBOSE:      align 2^0 (1)
+NON_VERBOSE:     reloff 0
+NON_VERBOSE:     nreloc 0
+NON_VERBOSE:      flags 0x00000002
+NON_VERBOSE:  reserved1 0
+NON_VERBOSE:  reserved2 0
+NON_VERBOSE: Section
+NON_VERBOSE:   sectname __compact_unwind
+NON_VERBOSE:    segname __LD
+NON_VERBOSE:       addr 0x0000000000000048
+NON_VERBOSE:       size 0x0000000000000020
+NON_VERBOSE:     offset 600
+NON_VERBOSE:      align 2^3 (8)
+NON_VERBOSE:     reloff 712
+NON_VERBOSE:     nreloc 1
+NON_VERBOSE:      flags 0x02000000
+NON_VERBOSE:  reserved1 0
+NON_VERBOSE:  reserved2 0
+NON_VERBOSE: Section
+NON_VERBOSE:   sectname __eh_frame
+NON_VERBOSE:    segname __TEXT
+NON_VERBOSE:       addr 0x0000000000000068
+NON_VERBOSE:       size 0x0000000000000040
+NON_VERBOSE:     offset 632
+NON_VERBOSE:      align 2^3 (8)
+NON_VERBOSE:     reloff 0
+NON_VERBOSE:     nreloc 0
+NON_VERBOSE:      flags 0x6800000b
+NON_VERBOSE:  reserved1 0
+NON_VERBOSE:  reserved2 0
+NON_VERBOSE: Load command 1
+NON_VERBOSE:      cmd LC_SYMTAB
+NON_VERBOSE:  cmdsize 24
+NON_VERBOSE:   symoff 720
+NON_VERBOSE:    nsyms 5
+NON_VERBOSE:   stroff 800
+NON_VERBOSE:  strsize 44
+NON_VERBOSE: Load command 2
+NON_VERBOSE:             cmd LC_DYSYMTAB
+NON_VERBOSE:         cmdsize 80
+NON_VERBOSE:       ilocalsym 0
+NON_VERBOSE:       nlocalsym 2
+NON_VERBOSE:      iextdefsym 2
+NON_VERBOSE:      nextdefsym 2
+NON_VERBOSE:       iundefsym 4
+NON_VERBOSE:       nundefsym 1
+NON_VERBOSE:          tocoff 0
+NON_VERBOSE:            ntoc 0
+NON_VERBOSE:       modtaboff 0
+NON_VERBOSE:         nmodtab 0
+NON_VERBOSE:    extrefsymoff 0
+NON_VERBOSE:     nextrefsyms 0
+NON_VERBOSE:  indirectsymoff 0
+NON_VERBOSE:   nindirectsyms 0
+NON_VERBOSE:       extreloff 0
+NON_VERBOSE:         nextrel 0
+NON_VERBOSE:       locreloff 0
+NON_VERBOSE:         nlocrel 0
diff --git a/test/tools/llvm-objdump/X86/macho-relocations.test b/test/tools/llvm-objdump/X86/macho-relocations.test
new file mode 100644
index 000000000000..536aec8b1bcc
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-relocations.test
@@ -0,0 +1,7 @@
+RUN: llvm-objdump -macho -r %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
+
+CHECK: RELOCATION RECORDS FOR [__text]:
+CHECK: 0000000000000027 X86_64_RELOC_BRANCH _printf
+CHECK: 000000000000000b X86_64_RELOC_SIGNED L_.str
+CHECK: RELOCATION RECORDS FOR [__compact_unwind]:
+CHECK: 0000000000000000 X86_64_RELOC_UNSIGNED __text
diff --git a/test/tools/llvm-objdump/X86/macho-section-contents.test b/test/tools/llvm-objdump/X86/macho-section-contents.test
new file mode 100644
index 000000000000..f62b5a7b52db
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-section-contents.test
@@ -0,0 +1,17 @@
+RUN: llvm-objdump -macho -s %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
+
+CHECK: Contents of section __text:
+CHECK:  0000 554889e5 4883ec20 488d0500 000000c7  UH..H.. H.......
+CHECK:  0010 45fc0000 0000897d f8488975 f0488955  E......}.H.u.H.U
+CHECK:  0020 e84889c7 b000e800 000000b9 00000000  .H..............
+CHECK:  0030 8945e489 c84883c4 205dc3             .E...H.. ].
+CHECK: Contents of section __cstring:
+CHECK:  003b 48656c6c 6f20776f 726c640a 00        Hello world..
+CHECK: Contents of section __compact_unwind:
+CHECK:  0048 00000000 00000000 3b000000 00000001  ........;.......
+CHECK:  0058 00000000 00000000 00000000 00000000  ................
+CHECK: Contents of section __eh_frame:
+CHECK:  0068 14000000 00000000 017a5200 01781001  .........zR..x..
+CHECK:  0078 100c0708 90010000 24000000 1c000000  ........$.......
+CHECK:  0088 78ffffff ffffffff 3b000000 00000000  x.......;.......
+CHECK:  0098 00410e10 8602430d 06000000 00000000  .A....C.........
diff --git a/test/tools/llvm-objdump/X86/macho-section-headers.test b/test/tools/llvm-objdump/X86/macho-section-headers.test
new file mode 100644
index 000000000000..5159d1808228
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-section-headers.test
@@ -0,0 +1,8 @@
+RUN: llvm-objdump -macho -h %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
+
+CHECK: Sections:
+CHECK: Idx Name          Size      Address          Type
+CHECK:   0 __text        0000003b 0000000000000000 TEXT 
+CHECK:   1 __cstring     0000000d 000000000000003b DATA 
+CHECK:   2 __compact_unwind 00000020 0000000000000048 DATA 
+CHECK:   3 __eh_frame    00000040 0000000000000068 DATA 
diff --git a/test/tools/llvm-objdump/X86/macho-section.test b/test/tools/llvm-objdump/X86/macho-section.test
new file mode 100644
index 000000000000..e4d7857f1414
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-section.test
@@ -0,0 +1,8 @@
+// RUN: llvm-objdump -m -section __DATA,__mod_init_func %p/Inputs/dylibModInit.macho-x86_64 | FileCheck %s -check-prefix=MODINIT
+// RUN: llvm-objdump -m -section __DATA,__mod_init_func -non-verbose %p/Inputs/dylibModInit.macho-x86_64 | FileCheck %s -check-prefix=NON_VERBOSE
+
+MODINIT: Contents of (__DATA,__mod_init_func) section
+MODINIT: 0x0000000000001000 0x0000000000000f30 _libinit
+
+NON_VERBOSE: Contents of (__DATA,__mod_init_func) section
+NON_VERBOSE: 0000000000001000	30 0f 00 00 00 00 00 00 
diff --git a/test/tools/llvm-objdump/X86/macho-symbol-table.test b/test/tools/llvm-objdump/X86/macho-symbol-table.test
new file mode 100644
index 000000000000..3fe5aea6c377
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-symbol-table.test
@@ -0,0 +1,8 @@
+RUN: llvm-objdump -macho -t %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
+
+CHECK: SYMBOL TABLE:
+CHECK: 000000000000003b l     F __TEXT,__cstring	00000000 L_.str
+CHECK: 0000000000000068 l     F __TEXT,__eh_frame	00000000 EH_frame0
+CHECK: 0000000000000000 g     F __TEXT,__text	00000000 _main
+CHECK: 0000000000000080 g     F __TEXT,__eh_frame	00000000 _main.eh
+CHECK: 0000000000000000         *UND*	00000000 _printf
diff --git a/test/tools/llvm-objdump/X86/macho-symbolized-disassembly.test b/test/tools/llvm-objdump/X86/macho-symbolized-disassembly.test
index 1e1080a30f06..6f49b456227e 100644
--- a/test/tools/llvm-objdump/X86/macho-symbolized-disassembly.test
+++ b/test/tools/llvm-objdump/X86/macho-symbolized-disassembly.test
@@ -7,6 +7,9 @@
 // RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/hello.obj.macho-i386 | FileCheck %s -check-prefix=i386-OBJ
 // RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/hello.exe.macho-i386 | FileCheck %s -check-prefix=i386-EXE
 
+// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex -no-symbolic-operands %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s -check-prefix=NO-SYM-OPS-OBJ
+// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex -no-symbolic-operands %p/Inputs/hello.exe.macho-x86_64 | FileCheck %s -check-prefix=NO-SYM-OPS-EXE
+
 OBJ: 0000000000000008	leaq	L_.str(%rip), %rax      ## literal pool for: "Hello world\n"
 OBJ: 0000000000000026	callq	_printf
 
@@ -36,3 +39,9 @@ CXX-EXE: 00000001000014cb	callq	__ZNSt3__116__pad_and_outputIcNS_11char_traitsIc
 i386-OBJ: 0000002f	calll	_printf
 
 i386-EXE: 00001f6f	calll	0x1f84                  ## symbol stub for: _printf
+
+NO-SYM-OPS-OBJ: 0000000000000008	leaq	(%rip), %rax
+NO-SYM-OPS-OBJ: 0000000000000026	callq	0x2b
+
+NO-SYM-OPS-EXE: 0000000100000f38	leaq	0x4f(%rip), %rax
+NO-SYM-OPS-EXE: 0000000100000f56	callq	0x100000f6c
diff --git a/test/tools/llvm-objdump/X86/macho-universal-x86_64.i386.test b/test/tools/llvm-objdump/X86/macho-universal-x86_64.i386.test
index e4fd37a902c4..260e9aa341e8 100644
--- a/test/tools/llvm-objdump/X86/macho-universal-x86_64.i386.test
+++ b/test/tools/llvm-objdump/X86/macho-universal-x86_64.i386.test
@@ -4,6 +4,8 @@ RUN: llvm-objdump %p/Inputs/macho-universal-archive.x86_64.i386 -d -m -no-show-r
 RUN: | FileCheck %s -check-prefix UArchive-i386
 RUN: llvm-objdump %p/Inputs/macho-universal.x86_64.i386 -universal-headers -m \
 RUN: | FileCheck %s -check-prefix FAT
+RUN: llvm-objdump %p/Inputs/macho-universal.x86_64.i386 -universal-headers -m \
+RUN: -non-verbose | FileCheck %s -check-prefix NON-VERBOSE
 
 UEXE-all: macho-universal.x86_64.i386 (architecture x86_64):
 UEXE-all: (__TEXT,__text) section
@@ -42,3 +44,21 @@ FAT:     capabilities 0x0
 FAT:     offset 12288
 FAT:     size 4336
 FAT:     align 2^12 (4096)
+
+NON-VERBOSE: Fat headers
+NON-VERBOSE: fat_magic 0xcafebabe
+NON-VERBOSE: nfat_arch 2
+NON-VERBOSE: architecture 0
+NON-VERBOSE:     cputype 16777223
+NON-VERBOSE:     cpusubtype 3
+NON-VERBOSE:     capabilities 0x80
+NON-VERBOSE:     offset 4096
+NON-VERBOSE:     size 4360
+NON-VERBOSE:     align 2^12 (4096)
+NON-VERBOSE: architecture 1
+NON-VERBOSE:     cputype 7
+NON-VERBOSE:     cpusubtype 3
+NON-VERBOSE:     capabilities 0x0
+NON-VERBOSE:     offset 12288
+NON-VERBOSE:     size 4336
+NON-VERBOSE:     align 2^12 (4096)
diff --git a/test/tools/llvm-objdump/X86/macho-unwind-info.test b/test/tools/llvm-objdump/X86/macho-unwind-info.test
new file mode 100644
index 000000000000..33db84fc07d1
--- /dev/null
+++ b/test/tools/llvm-objdump/X86/macho-unwind-info.test
@@ -0,0 +1,7 @@
+RUN: llvm-objdump -macho -u %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
+
+CHECK: Contents of __compact_unwind section:
+CHECK:   Entry at offset 0x0:
+CHECK:     start:                0x0 _main
+CHECK:     length:               0x3b
+CHECK:     compact encoding:     0x01000000
diff --git a/test/tools/llvm-objdump/common-symbol-elf.test b/test/tools/llvm-objdump/common-symbol-elf.test
new file mode 100644
index 000000000000..32df05ac051b
--- /dev/null
+++ b/test/tools/llvm-objdump/common-symbol-elf.test
@@ -0,0 +1,3 @@
+// RUN: llvm-objdump -t %p/Inputs/common-symbol-elf | FileCheck %s
+
+CHECK: 00000400 g       *COM*  00000008 common_symbol
diff --git a/test/tools/llvm-objdump/macho-sections.test b/test/tools/llvm-objdump/macho-sections.test
new file mode 100644
index 000000000000..31efd110a5c8
--- /dev/null
+++ b/test/tools/llvm-objdump/macho-sections.test
@@ -0,0 +1,5 @@
+# RUN: llvm-objdump -macho -section=__data %p/Inputs/bind2.macho-x86_64 | FileCheck %s
+# RUN: llvm-objdump -macho -section=__data -raw %p/Inputs/bind2.macho-x86_64 | FileCheck --check-prefix=RAW %s
+
+# CHECK: bind2.macho-x86_64:
+# RAW-NOT: bind2.macho-x86_64:
diff --git a/test/tools/llvm-objdump/proc-specific-section-elf.test b/test/tools/llvm-objdump/proc-specific-section-elf.test
new file mode 100644
index 000000000000..b3067d49af8e
--- /dev/null
+++ b/test/tools/llvm-objdump/proc-specific-section-elf.test
@@ -0,0 +1,3 @@
+// RUN: llvm-objdump -t %p/Inputs/proc-specific-section-elf | FileCheck %s
+
+CHECK: 00000000         *UND*  00000000 print
diff --git a/test/tools/llvm-pdbdump/Inputs/ClassLayoutTest.cpp b/test/tools/llvm-pdbdump/Inputs/ClassLayoutTest.cpp
new file mode 100644
index 000000000000..00565970cac0
--- /dev/null
+++ b/test/tools/llvm-pdbdump/Inputs/ClassLayoutTest.cpp
@@ -0,0 +1,64 @@
+// Compile with "cl /c /Zi /GR- ClassLayoutTest.cpp"
+// Link with "link ClassLayoutTest.obj /debug /nodefaultlib /entry:main"
+
+namespace MembersTest {
+  class A {
+  public:
+    typedef int NestedTypedef;
+    enum NestedEnum {
+      NestedEnumValue1
+    };
+
+    void MemberFunc() {}
+
+  private:
+    int IntMemberVar;
+    double DoubleMemberVar;
+  };
+}
+
+namespace GlobalsTest {
+  int IntVar;
+  double DoubleVar;
+  
+  typedef int Typedef;
+  enum Enum {
+    Val1
+  } EnumVar;
+  Typedef TypedefVar;
+}
+
+namespace BaseClassTest {
+  class A {};
+  class B : public virtual A {};
+  class C : public virtual A {};
+  class D : protected B, private C {};
+}
+
+namespace UdtKindTest {
+  struct A {};
+  class B {};
+  union C {};
+}
+
+namespace BitFieldTest {
+  struct A {
+    int Bits1 : 1;
+    int Bits2 : 2;
+    int Bits3 : 3;
+    int Bits4 : 4;
+    int Bits22 : 22;
+    int Offset0x04;
+  };
+};
+
+int main(int argc, char **argv) {
+  MembersTest::A v1;
+  v1.MemberFunc();
+  BaseClassTest::D v2;
+  UdtKindTest::A v3;
+  UdtKindTest::B v4;
+  UdtKindTest::C v5;
+  BitFieldTest::A v7;
+  return 0;
+}
diff --git a/test/tools/llvm-pdbdump/Inputs/ClassLayoutTest.pdb b/test/tools/llvm-pdbdump/Inputs/ClassLayoutTest.pdb
new file mode 100644
index 000000000000..5f5190df4b76
--- /dev/null
+++ b/test/tools/llvm-pdbdump/Inputs/ClassLayoutTest.pdb
diff --git a/test/tools/llvm-pdbdump/Inputs/FilterTest.cpp b/test/tools/llvm-pdbdump/Inputs/FilterTest.cpp
new file mode 100644
index 000000000000..bcf9360d4a9b
--- /dev/null
+++ b/test/tools/llvm-pdbdump/Inputs/FilterTest.cpp
@@ -0,0 +1,29 @@
+// Compile with "cl /c /Zi /GR- FilterTest.cpp"
+// Link with "link FilterTest.obj /debug /nodefaultlib /entry:main"
+
+class FilterTestClass {
+public:
+  typedef int NestedTypedef;
+  enum NestedEnum {
+    NestedEnumValue1
+  };
+
+  void MemberFunc() {}
+
+private:
+  int IntMemberVar;
+  double DoubleMemberVar;
+};
+
+int IntGlobalVar;
+double DoubleGlobalVar;
+typedef int GlobalTypedef;
+enum GlobalEnum {
+  GlobalEnumVal1
+} GlobalEnumVar;
+
+int main(int argc, char **argv) {
+  FilterTestClass TestClass;
+  GlobalTypedef v1;
+  return 0;
+}
diff --git a/test/tools/llvm-pdbdump/Inputs/FilterTest.pdb b/test/tools/llvm-pdbdump/Inputs/FilterTest.pdb
new file mode 100644
index 000000000000..5f01ec701b81
--- /dev/null
+++ b/test/tools/llvm-pdbdump/Inputs/FilterTest.pdb
diff --git a/test/tools/llvm-pdbdump/Inputs/LoadAddressTest.cpp b/test/tools/llvm-pdbdump/Inputs/LoadAddressTest.cpp
new file mode 100644
index 000000000000..10abcab8b717
--- /dev/null
+++ b/test/tools/llvm-pdbdump/Inputs/LoadAddressTest.cpp
@@ -0,0 +1,6 @@
+// Compile with "cl /c /Zi /GR- LoadAddressTest.cpp"
+// Link with "link LoadAddressTest.obj /debug /nodefaultlib /entry:main"
+
+int main(int argc, char **argv) {
+  return 0;
+}
diff --git a/test/tools/llvm-pdbdump/Inputs/LoadAddressTest.pdb b/test/tools/llvm-pdbdump/Inputs/LoadAddressTest.pdb
new file mode 100644
index 000000000000..e302e9bf3b61
--- /dev/null
+++ b/test/tools/llvm-pdbdump/Inputs/LoadAddressTest.pdb
diff --git a/test/tools/llvm-pdbdump/class-layout.test b/test/tools/llvm-pdbdump/class-layout.test
new file mode 100644
index 000000000000..c46e62b21961
--- /dev/null
+++ b/test/tools/llvm-pdbdump/class-layout.test
@@ -0,0 +1,57 @@
+; RUN: llvm-pdbdump -all %p/Inputs/ClassLayoutTest.pdb > %t

+; RUN: FileCheck -input-file=%t %s -check-prefix=GLOBALS_TEST

+; RUN: FileCheck -input-file=%t %s -check-prefix=MEMBERS_TEST

+; RUN: FileCheck -input-file=%t %s -check-prefix=BASE_CLASS_A

+; RUN: FileCheck -input-file=%t %s -check-prefix=BASE_CLASS_B

+; RUN: FileCheck -input-file=%t %s -check-prefix=BASE_CLASS_C

+; RUN: FileCheck -input-file=%t %s -check-prefix=BASE_CLASS_D

+; RUN: FileCheck -input-file=%t %s -check-prefix=UDT_KIND_TEST

+; RUN: FileCheck -input-file=%t %s -check-prefix=BITFIELD_TEST

+

+; GLOBALS_TEST: ---GLOBALS---

+; GLOBALS_TEST-DAG: int GlobalsTest::IntVar

+; GLOBALS_TEST-DAG: double GlobalsTest::DoubleVar

+; GLOBALS_TEST-DAG: GlobalsTest::Enum GlobalsTest::EnumVar

+

+; MEMBERS_TEST: ---TYPES---

+; MEMBERS_TEST: class MembersTest::A {

+; MEMBERS_TEST-DAG: typedef int NestedTypedef

+; MEMBERS_TEST-DAG: enum NestedEnum

+; MEMBERS_TEST: public:

+; MEMBERS_TEST-NEXT: void MemberFunc()

+; MEMBERS_TEST-NEXT: private:

+; MEMBERS_TEST-DAG: int IntMemberVar

+; MEMBERS_TEST-DAG: double DoubleMemberVar

+; MEMBERS_TEST: }

+

+; BASE_CLASS_A: ---TYPES---

+; BASE_CLASS_A: class BaseClassTest::A {}

+

+; BASE_CLASS_B: ---TYPES---

+; BASE_CLASS_B: class BaseClassTest::B

+; BASE_CLASS_B-NEXT: : public virtual BaseClassTest::A {

+

+; BASE_CLASS_C: ---TYPES---

+; BASE_CLASS_C: class BaseClassTest::C

+; BASE_CLASS_C-NEXT: : public virtual BaseClassTest::A {

+

+; BASE_CLASS_D: ---TYPES---

+; BASE_CLASS_D: class BaseClassTest::D

+; BASE_CLASS_D-DAG: protected BaseClassTest::B

+; BASE_CLASS_D-DAG: private BaseClassTest::C

+; BASE_CLASS_D-DAG: protected virtual BaseClassTest::A

+

+; UDT_KIND_TEST: ---TYPES---

+; UDT_KIND_TEST-DAG: union UdtKindTest::C {}

+; UDT_KIND_TEST-DAG: class UdtKindTest::B {}

+; UDT_KIND_TEST-DAG: struct UdtKindTest::A {}

+

+; BITFIELD_TEST: ---TYPES---

+; BITFIELD_TEST: struct BitFieldTest::A {

+; BITFIELD_TEST-NEXT: public:

+; BITFIELD_TEST-NEXT: +0x00 int Bits1 : 1

+; BITFIELD_TEST-NEXT: +0x00 int Bits2 : 2

+; BITFIELD_TEST-NEXT: +0x00 int Bits3 : 3

+; BITFIELD_TEST-NEXT: +0x00 int Bits4 : 4

+; BITFIELD_TEST-NEXT: +0x00 int Bits22 : 22

+; BITFIELD_TEST-NEXT: +0x04 int Offset0x04

diff --git a/test/tools/llvm-pdbdump/enum-layout.test b/test/tools/llvm-pdbdump/enum-layout.test
new file mode 100644
index 000000000000..c6145533899f
--- /dev/null
+++ b/test/tools/llvm-pdbdump/enum-layout.test
@@ -0,0 +1,20 @@
+; RUN: llvm-pdbdump -types %p/Inputs/ClassLayoutTest.pdb > %t

+; RUN: FileCheck -input-file=%t %s -check-prefix=GLOBAL_ENUM

+; RUN: FileCheck -input-file=%t %s -check-prefix=MEMBER_ENUM

+

+; GLOBAL_ENUM: ---TYPES---

+; GLOBAL_ENUM: Enums:

+; GLOBAL_ENUM: enum GlobalsTest::Enum {

+; GLOBAL_ENUM-NEXT: Val1 = 0

+; GLOBAL_ENUM-NEXT: }

+

+; MEMBER_ENUM: ---TYPES---

+; MEMBER_ENUM: Classes:

+; MEMBER_ENUM: struct __vc_attributes::threadingAttribute {

+; MEMBER_ENUM-NEXT: enum threading_e {

+; MEMBER_ENUM-NEXT: apartment = 1

+; MEMBER_ENUM-NEXT: single = 2

+; MEMBER_ENUM-NEXT: free = 3

+; MEMBER_ENUM-NEXT: neutral = 4

+; MEMBER_ENUM-NEXT: both = 5

+; MEMBER_ENUM-NEXT: }

diff --git a/test/tools/llvm-pdbdump/lit.local.cfg b/test/tools/llvm-pdbdump/lit.local.cfg
new file mode 100644
index 000000000000..28a895f51148
--- /dev/null
+++ b/test/tools/llvm-pdbdump/lit.local.cfg
@@ -0,0 +1 @@
+config.unsupported = not config.have_dia_sdk
diff --git a/test/tools/llvm-pdbdump/load-address.test b/test/tools/llvm-pdbdump/load-address.test
new file mode 100644
index 000000000000..7a5a4dbff673
--- /dev/null
+++ b/test/tools/llvm-pdbdump/load-address.test
@@ -0,0 +1,10 @@
+; RUN: llvm-pdbdump -externals %p/Inputs/LoadAddressTest.pdb \

+; RUN:    | FileCheck --check-prefix=RVA %s

+; RUN: llvm-pdbdump -externals -load-address=0x40000000 \

+; RUN: %p/Inputs/LoadAddressTest.pdb | FileCheck --check-prefix=VA %s

+

+; RVA: ---EXTERNALS---

+; RVA: [0x00001010] _main

+

+; VA: ---EXTERNALS---

+; VA: [0x40001010] _main

diff --git a/test/tools/llvm-pdbdump/regex-filter.test b/test/tools/llvm-pdbdump/regex-filter.test
new file mode 100644
index 000000000000..8b9eca63f585
--- /dev/null
+++ b/test/tools/llvm-pdbdump/regex-filter.test
@@ -0,0 +1,75 @@
+; RUN: llvm-pdbdump -symbols -globals -types %p/Inputs/FilterTest.pdb \
+; RUN:    | FileCheck --check-prefix=NO_FILTER %s
+; RUN: llvm-pdbdump -types -exclude-types="GlobalTypedef|NestedTypedef" \
+; RUN:    %p/Inputs/FilterTest.pdb | FileCheck --check-prefix=EXCLUDE_TYPEDEFS %s
+; RUN: llvm-pdbdump -types -exclude-types="GlobalEnum|NestedEnum" \
+; RUN:    %p/Inputs/FilterTest.pdb | FileCheck --check-prefix=EXCLUDE_ENUMS %s
+; RUN: llvm-pdbdump -types -symbols -globals -exclude-symbols="MemberVar|GlobalVar" \
+; RUN:    %p/Inputs/FilterTest.pdb | FileCheck --check-prefix=EXCLUDE_VARS %s
+; RUN: llvm-pdbdump -types -exclude-types="FilterTestClass" \
+; RUN:    %p/Inputs/FilterTest.pdb | FileCheck  --check-prefix=EXCLUDE_WHOLE_CLASS %s
+; RUN: llvm-pdbdump -symbols -globals -exclude-compilands="FilterTest.obj"  \
+; RUN:    %p/Inputs/FilterTest.pdb | FileCheck  --check-prefix=EXCLUDE_COMPILAND %s
+
+; NO_FILTER: ---TYPES---
+; NO_FILTER: Enums:
+; NO_FILTER: enum GlobalEnum
+; NO_FILTER: Typedefs
+; NO_FILTER: typedef int GlobalTypedef
+; NO_FILTER: Classes:
+; NO_FILTER: struct __vc_attributes
+; NO_FILTER: class FilterTestClass
+; NO_FILTER-DAG: typedef int NestedTypedef
+; NO_FILTER-DAG: enum NestedEnum
+; NO_FILTER-DAG: int IntMemberVar
+; NO_FILTER-DAG: double DoubleMemberVar
+; NO_FILTER: ---SYMBOLS---
+; NO_FILTER: Inputs\FilterTest.obj
+; NO_FILTER: int __cdecl main(int argc, char** argv)
+; NO_FILTER: ---GLOBALS---
+; NO_FILTER-DAG: double DoubleGlobalVar
+; NO_FILTER-DAG: int IntGlobalVar
+; NO_FILTER-DAG: GlobalEnum GlobalEnumVar
+
+; EXCLUDE_TYPEDEFS: ---TYPES---
+; EXCLUDE_TYPEDEFS: Enums:
+; EXCLUDE_TYPEDEFS: GlobalEnum
+; EXCLUDE_TYPEDEFS: Typedefs
+; EXCLUDE_TYPEDEFS-NOT: GlobalTypedef
+; EXCLUDE_TYPEDEFS: Classes
+; EXCLUDE_TYPEDEFS: class FilterTestClass
+; EXCLUDE_TYPEDEFS-NOT: NestedTypedef
+; EXCLUDE_TYPEDEFS: private:
+
+; EXCLUDE_ENUMS: ---TYPES---
+; EXCLUDE_ENUMS: Enums:
+; EXCLUDE_ENUMS-NOT: GlobalEnum
+; EXCLUDE_ENUMS: Typedefs
+; EXCLUDE_ENUMS: GlobalTypedef
+; EXCLUDE_ENUMS: Classes
+; EXCLUDE_ENUMS: class FilterTestClass
+; EXCLUDE_ENUMS-NOT: NestedEnum
+; EXCLUDE_ENUMS: private:
+
+; EXCLUDE_VARS: ---TYPES---
+; EXCLUDE_VARS: Classes:
+; EXCLUDE_VARS: class FilterTestClass
+; EXCLUDE_VARS: private:
+; EXCLUDE_VARS-NOT: IntMemberVar
+; EXCLUDE_VARS-NOT: DoubleMemberVar
+; EXCLUDE_VARS: ---GLOBALS---
+; EXCLUDE_VARS-NOT: DoubleGlobalVar
+; EXCLUDE_VARS-NOT: IntGlobalVar
+
+; EXCLUDE_WHOLE_CLASS: ---TYPES---
+; EXCLUDE_WHOLE_CLASS-NOT: class FilterTestClass
+; EXCLUDE_WHOLE_CLASS-NOT: typedef int NestedTypedef
+; EXCLUDE_WHOLE_CLASS-NOT: enum NestedEnum
+; EXCLUDE_WHOLE_CLASS-NOT: int IntMemberVar
+; EXCLUDE_WHOLE_CLASS-NOT: double DoubleMemberVar
+
+; EXCLUDE_COMPILAND: ---SYMBOLS---
+; EXCLUDE_COMPILAND-NOT: FilterTest.obj
+; EXCLUDE_COMPILAND-NOT: __cdecl main
+; EXCLUDE_COMPILAND: * Linker *
+; EXCLUDE_COMPILAND: ---GLOBALS---
diff --git a/test/tools/llvm-profdata/general.proftext b/test/tools/llvm-profdata/general.proftext
index 591d2628d776..5302fce015e8 100644
--- a/test/tools/llvm-profdata/general.proftext
+++ b/test/tools/llvm-profdata/general.proftext
@@ -38,6 +38,14 @@ large_numbers
 # LARGENUM-NEXT: Function count: 2305843009213693952
 # LARGENUM-NEXT: Block counts: [1152921504606846976, 576460752303423488, 288230376151711744, 144115188075855872, 72057594037927936]
 
+# RUN: llvm-profdata show %t.profdata --function hex_hash | FileCheck %s -check-prefix=HEX-HASH
+hex_hash
+0x1234
+1
+0
+# HEX-HASH: Hash: 0x0000000000001234
+# HEX-HASH-NEXT: Counters: 1
+
 # RUN: llvm-profdata show %t.profdata --function NOSUCHFUNC | FileCheck %s -check-prefix=NOSUCHFUNC
 # NOSUCHFUNC-NOT: Counters:
 # NOSUCHFUNC: Functions shown: 0
@@ -46,11 +54,11 @@ large_numbers
 # SOMEFUNCS: Counters:
 # SOMEFUNCS: function_count_only:
 # SOMEFUNCS: large_numbers:
-# SOMEFUNCS: Functions shown: 2
+# SOMEFUNCS: Functions shown: 3
 
 # RUN: llvm-profdata show %t.profdata | FileCheck %s -check-prefix=SUMMARY
 # SUMMARY-NOT: Counters:
 # SUMMARY-NOT: Functions shown:
-# SUMMARY: Total functions: 3
+# SUMMARY: Total functions: 4
 # SUMMARY: Maximum function count: 2305843009213693952
 # SUMMARY: Maximum internal block count: 1152921504606846976
diff --git a/test/tools/llvm-profdata/raw-magic-but-no-header.test b/test/tools/llvm-profdata/raw-magic-but-no-header.test
index 6db723c3e253..b2a697042b0a 100644
--- a/test/tools/llvm-profdata/raw-magic-but-no-header.test
+++ b/test/tools/llvm-profdata/raw-magic-but-no-header.test
@@ -3,4 +3,4 @@ RUN: not llvm-profdata show %t 2>&1 | FileCheck %s
 RUN: printf '\377lprofr\201' > %t
 RUN: not llvm-profdata show %t 2>&1 | FileCheck %s
 
-CHECK: error: {{.+}}: Invalid header
+CHECK: error: {{.+}}: Invalid profile data (file header is corrupt)
diff --git a/test/tools/llvm-readobj/Inputs/abiflags.obj.elf-mips b/test/tools/llvm-readobj/Inputs/abiflags.obj.elf-mips
new file mode 100644
index 000000000000..edcd50becec4
--- /dev/null
+++ b/test/tools/llvm-readobj/Inputs/abiflags.obj.elf-mips
diff --git a/test/tools/llvm-readobj/Inputs/abiflags.obj.elf-mipsel b/test/tools/llvm-readobj/Inputs/abiflags.obj.elf-mipsel
new file mode 100644
index 000000000000..bb5f43d28623
--- /dev/null
+++ b/test/tools/llvm-readobj/Inputs/abiflags.obj.elf-mipsel
diff --git a/test/tools/llvm-readobj/Inputs/dtflags.elf-x86-64 b/test/tools/llvm-readobj/Inputs/dtflags.elf-x86-64
new file mode 100755
index 000000000000..c6e8501d9e73
--- /dev/null
+++ b/test/tools/llvm-readobj/Inputs/dtflags.elf-x86-64
diff --git a/test/tools/llvm-readobj/Inputs/macho-universal-archive.x86_64.i386 b/test/tools/llvm-readobj/Inputs/macho-universal-archive.x86_64.i386
new file mode 100644
index 000000000000..1660714c68ea
--- /dev/null
+++ b/test/tools/llvm-readobj/Inputs/macho-universal-archive.x86_64.i386
diff --git a/test/tools/llvm-readobj/Inputs/macho-universal.x86_64.i386 b/test/tools/llvm-readobj/Inputs/macho-universal.x86_64.i386
new file mode 100644
index 000000000000..36d5fc29d681
--- /dev/null
+++ b/test/tools/llvm-readobj/Inputs/macho-universal.x86_64.i386
diff --git a/test/tools/llvm-readobj/Inputs/mips-options.elf-mips64el b/test/tools/llvm-readobj/Inputs/mips-options.elf-mips64el
new file mode 100755
index 000000000000..4b6525731dd7
--- /dev/null
+++ b/test/tools/llvm-readobj/Inputs/mips-options.elf-mips64el
diff --git a/test/tools/llvm-readobj/Inputs/trivial.exe.coff-arm b/test/tools/llvm-readobj/Inputs/trivial.exe.coff-arm
new file mode 100755
index 000000000000..121d820b6b0f
--- /dev/null
+++ b/test/tools/llvm-readobj/Inputs/trivial.exe.coff-arm
diff --git a/test/tools/llvm-readobj/Inputs/trivial.ll b/test/tools/llvm-readobj/Inputs/trivial.ll
index 2cd7ec89e246..f79b8b897691 100644
--- a/test/tools/llvm-readobj/Inputs/trivial.ll
+++ b/test/tools/llvm-readobj/Inputs/trivial.ll
@@ -9,7 +9,7 @@
 
 define i32 @main() nounwind {
 entry:
-  %call = tail call i32 @puts(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0)) nounwind
+  %call = tail call i32 @puts(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0)) nounwind
   tail call void bitcast (void (...)* @SomeOtherFunction to void ()*)() nounwind
   ret i32 0
 }
diff --git a/test/tools/llvm-readobj/codeview-linetables.test b/test/tools/llvm-readobj/codeview-linetables.test
index e5e344bf10ff..b2acee1200b9 100644
--- a/test/tools/llvm-readobj/codeview-linetables.test
+++ b/test/tools/llvm-readobj/codeview-linetables.test
@@ -18,16 +18,16 @@
 ;     z();
 ;   }
 ; using 32-/64-bit versions of CL v17.00.61030 and v18.00.21005.1 respectively.
-RUN: llvm-readobj -s -codeview-linetables %p/Inputs/multifunction-linetables.obj.coff-2012-i368 \
+RUN: llvm-readobj -s -codeview -section-symbols %p/Inputs/multifunction-linetables.obj.coff-2012-i368 \
 RUN:   | FileCheck %s -check-prefix MFUN32
-RUN: llvm-readobj -s -codeview-linetables %p/Inputs/multifunction-linetables.obj.coff-2013-i368 \
+RUN: llvm-readobj -s -codeview -section-symbols %p/Inputs/multifunction-linetables.obj.coff-2013-i368 \
 RUN:   | FileCheck %s -check-prefix MFUN32
-RUN: llvm-readobj -s -codeview-linetables %p/Inputs/multifunction-linetables.obj.coff-2012-x86_64 \
+RUN: llvm-readobj -s -codeview -section-symbols %p/Inputs/multifunction-linetables.obj.coff-2012-x86_64 \
 RUN:   | FileCheck %s -check-prefix MFUN64
-RUN: llvm-readobj -s -codeview-linetables %p/Inputs/multifunction-linetables.obj.coff-2013-x86_64 \
+RUN: llvm-readobj -s -codeview -section-symbols %p/Inputs/multifunction-linetables.obj.coff-2013-x86_64 \
 RUN:   | FileCheck %s -check-prefix MFUN64
 
-MFUN32:      CodeViewLineTables [
+MFUN32:      CodeViewDebugInfo [
 MFUN32-NEXT:   Magic: 0x4
 MFUN32-NEXT:   Subsection [
 MFUN32-NEXT:     Type: 0xF1
@@ -136,7 +136,7 @@ MFUN32-NEXT:     ]
 MFUN32-NEXT:   ]
 MFUN32-NEXT: ]
 
-MFUN64:      CodeViewLineTables [
+MFUN64:      CodeViewDebugInfo [
 MFUN64-NEXT:   Magic: 0x4
 MFUN64-NEXT:   Subsection [
 MFUN64-NEXT:     Type: 0xF1
@@ -248,16 +248,16 @@ MFUN64-NEXT: ]
 ;     g();
 ;   }
 ; using 32-/64-bit versions of CL v17.00.61030 and v18.00.21005.1 respectively.
-RUN: llvm-readobj -s -codeview-linetables %p/Inputs/multifile-linetables.obj.coff-2012-i368 \
+RUN: llvm-readobj -s -codeview -section-symbols %p/Inputs/multifile-linetables.obj.coff-2012-i368 \
 RUN:   | FileCheck %s -check-prefix MFILE32
-RUN: llvm-readobj -s -codeview-linetables %p/Inputs/multifile-linetables.obj.coff-2013-i368 \
+RUN: llvm-readobj -s -codeview -section-symbols %p/Inputs/multifile-linetables.obj.coff-2013-i368 \
 RUN:   | FileCheck %s -check-prefix MFILE32
-RUN: llvm-readobj -s -codeview-linetables %p/Inputs/multifile-linetables.obj.coff-2012-x86_64 \
+RUN: llvm-readobj -s -codeview -section-symbols %p/Inputs/multifile-linetables.obj.coff-2012-x86_64 \
 RUN:   | FileCheck %s -check-prefix MFILE64
-RUN: llvm-readobj -s -codeview-linetables %p/Inputs/multifile-linetables.obj.coff-2013-x86_64 \
+RUN: llvm-readobj -s -codeview -section-symbols %p/Inputs/multifile-linetables.obj.coff-2013-x86_64 \
 RUN:   | FileCheck %s -check-prefix MFILE64
 
-MFILE32:      CodeViewLineTables [
+MFILE32:      CodeViewDebugInfo [
 MFILE32-NEXT:   Magic: 0x4
 MFILE32-NEXT:   Subsection [
 MFILE32-NEXT:     Type: 0xF1
@@ -317,7 +317,7 @@ MFILE32-NEXT:     ]
 MFILE32-NEXT:   ]
 MFILE32-NEXT: ]
 
-MFILE64:      CodeViewLineTables [
+MFILE64:      CodeViewDebugInfo [
 MFILE64-NEXT:   Magic: 0x4
 MFILE64-NEXT:   Subsection [
 MFILE64-NEXT:     Type: 0xF1
@@ -387,9 +387,9 @@ MFILE64-NEXT: ]
 ;     return 0;
 ;   }
 ; using 32-version of CL v17.00.61030 and v18.00.21005.1 respectively.
-RUN: llvm-readobj -s -codeview-linetables %p/Inputs/comdat-function-linetables.obj.coff-2012-i386 \
+RUN: llvm-readobj -s -codeview -section-symbols %p/Inputs/comdat-function-linetables.obj.coff-2012-i386 \
 RUN:   | FileCheck %s -check-prefix MCOMDAT
-RUN: llvm-readobj -s -codeview-linetables %p/Inputs/comdat-function-linetables.obj.coff-2013-i386 \
+RUN: llvm-readobj -s -codeview -section-symbols %p/Inputs/comdat-function-linetables.obj.coff-2013-i386 \
 RUN:   | FileCheck %s -check-prefix MCOMDAT
 
 MCOMDAT:      ProcStart {
diff --git a/test/tools/llvm-readobj/coff-arm-baserelocs.test b/test/tools/llvm-readobj/coff-arm-baserelocs.test
new file mode 100644
index 000000000000..c0febd74aef4
--- /dev/null
+++ b/test/tools/llvm-readobj/coff-arm-baserelocs.test
@@ -0,0 +1,7 @@
+# RUN: llvm-readobj -coff-basereloc %p/Inputs/trivial.exe.coff-arm | FileCheck %s
+
+# CHECK: Entry {
+# CHECK:  Type: ARM_MOV32(T)
+# CHECK:  Address: 0x9390
+# CHECK: }
+
diff --git a/test/tools/llvm-readobj/elf-dtflags.test b/test/tools/llvm-readobj/elf-dtflags.test
new file mode 100644
index 000000000000..0ed1c7adf91d
--- /dev/null
+++ b/test/tools/llvm-readobj/elf-dtflags.test
@@ -0,0 +1,6 @@
+// Test that llvm-readobj dumps DF_XXX and DF_1_XXX flags correctly.
+
+RUN: llvm-readobj -dynamic-table %p/Inputs/dtflags.elf-x86-64 | FileCheck %s
+
+CHECK: 0x000000000000001E FLAGS                ORIGIN BIND_NOW
+CHECK: 0x000000006FFFFFFB FLAGS_1              NOW ORIGIN
diff --git a/test/tools/llvm-readobj/macho-universal-x86_64.i386.test b/test/tools/llvm-readobj/macho-universal-x86_64.i386.test
new file mode 100644
index 000000000000..2138bb70ad3c
--- /dev/null
+++ b/test/tools/llvm-readobj/macho-universal-x86_64.i386.test
@@ -0,0 +1,297 @@
+RUN: llvm-readobj -h %p/Inputs/macho-universal.x86_64.i386 \
+RUN: | FileCheck %s -check-prefix MULTIHEADER
+
+RUN: llvm-readobj -sections %p/Inputs/macho-universal.x86_64.i386 \
+RUN: | FileCheck %s -check-prefix MULTISECTIONS
+
+RUN: llvm-readobj -h %p/Inputs/macho-universal-archive.x86_64.i386 \
+RUN: | FileCheck %s -check-prefix MULTIHEADER-ARCHIVE
+
+RUN: llvm-readobj -sections %p/Inputs/macho-universal-archive.x86_64.i386 \
+RUN: | FileCheck %s -check-prefix MULTISECTIONS-ARCHIVE
+
+MULTIHEADER: Format: Mach-O 64-bit x86-64
+MULTIHEADER: Arch: x86_64
+MULTIHEADER: AddressSize: 64bit
+MULTIHEADER: MachHeader {
+MULTIHEADER:   Magic: Magic64 (0xFEEDFACF)
+MULTIHEADER:   CpuType: X86-64 (0x1000007)
+MULTIHEADER:   CpuSubType: CPU_SUBTYPE_X86_64_ALL (0x3)
+MULTIHEADER:   FileType: Executable (0x2)
+MULTIHEADER:   NumOfLoadCommands: 16
+MULTIHEADER:   SizeOfLoadCommands: 880
+MULTIHEADER:   Flags [ (0x200085)
+MULTIHEADER:     MH_DYLDLINK (0x4)
+MULTIHEADER:     MH_NOUNDEFS (0x1)
+MULTIHEADER:     MH_PIE (0x200000)
+MULTIHEADER:     MH_TWOLEVEL (0x80)
+MULTIHEADER:   ]
+MULTIHEADER:   Reserved: 0x0
+MULTIHEADER: }
+
+MULTIHEADER: Format: Mach-O 32-bit i386
+MULTIHEADER: Arch: i386
+MULTIHEADER: AddressSize: 32bit
+MULTIHEADER: MachHeader {
+MULTIHEADER:   Magic: Magic (0xFEEDFACE)
+MULTIHEADER:   CpuType: X86 (0x7)
+MULTIHEADER:   CpuSubType: CPU_SUBTYPE_I386_ALL (0x3)
+MULTIHEADER:   FileType: Executable (0x2)
+MULTIHEADER:   NumOfLoadCommands: 16
+MULTIHEADER:   SizeOfLoadCommands: 716
+MULTIHEADER:   Flags [ (0x1200085)
+MULTIHEADER:     MH_DYLDLINK (0x4)
+MULTIHEADER:     MH_NOUNDEFS (0x1)
+MULTIHEADER:     MH_NO_HEAP_EXECUTION (0x1000000)
+MULTIHEADER:     MH_PIE (0x200000)
+MULTIHEADER:     MH_TWOLEVEL (0x80)
+MULTIHEADER:   ]
+MULTIHEADER: }
+
+
+
+MULTISECTIONS: Format: Mach-O 64-bit x86-64
+MULTISECTIONS: Arch: x86_64
+MULTISECTIONS: AddressSize: 64bit
+MULTISECTIONS: Sections [
+MULTISECTIONS:   Section {
+MULTISECTIONS:     Index: 0
+MULTISECTIONS:     Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS:     Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS:     Address: 0x100000F60
+MULTISECTIONS:     Size: 0x12
+MULTISECTIONS:     Offset: 3936
+MULTISECTIONS:     Alignment: 4
+MULTISECTIONS:     RelocationOffset: 0x0
+MULTISECTIONS:     RelocationCount: 0
+MULTISECTIONS:     Type: 0x0
+MULTISECTIONS:     Attributes [ (0x800004)
+MULTISECTIONS:       PureInstructions (0x800000)
+MULTISECTIONS:       SomeInstructions (0x4)
+MULTISECTIONS:     ]
+MULTISECTIONS:     Reserved1: 0x0
+MULTISECTIONS:     Reserved2: 0x0
+MULTISECTIONS:   }
+MULTISECTIONS:   Section {
+MULTISECTIONS:     Index: 1
+MULTISECTIONS:     Name: __unwind_info (5F 5F 75 6E 77 69 6E 64 5F 69 6E 66 6F 00 00 00)
+MULTISECTIONS:     Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS:     Address: 0x100000F72
+MULTISECTIONS:     Size: 0x48
+MULTISECTIONS:     Offset: 3954
+MULTISECTIONS:     Alignment: 0
+MULTISECTIONS:     RelocationOffset: 0x0
+MULTISECTIONS:     RelocationCount: 0
+MULTISECTIONS:     Type: 0x0
+MULTISECTIONS:     Attributes [ (0x0)
+MULTISECTIONS:     ]
+MULTISECTIONS:     Reserved1: 0x0
+MULTISECTIONS:     Reserved2: 0x0
+MULTISECTIONS:   }
+MULTISECTIONS:   Section {
+MULTISECTIONS:     Index: 2
+MULTISECTIONS:     Name: __eh_frame (5F 5F 65 68 5F 66 72 61 6D 65 00 00 00 00 00 00)
+MULTISECTIONS:     Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS:     Address: 0x100000FC0
+MULTISECTIONS:     Size: 0x40
+MULTISECTIONS:     Offset: 4032
+MULTISECTIONS:     Alignment: 3
+MULTISECTIONS:     RelocationOffset: 0x0
+MULTISECTIONS:     RelocationCount: 0
+MULTISECTIONS:     Type: 0x0
+MULTISECTIONS:     Attributes [ (0x0)
+MULTISECTIONS:     ]
+MULTISECTIONS:     Reserved1: 0x0
+MULTISECTIONS:     Reserved2: 0x0
+MULTISECTIONS:   }
+MULTISECTIONS: ]
+
+MULTISECTIONS: Format: Mach-O 32-bit i386
+MULTISECTIONS: Arch: i386
+MULTISECTIONS: AddressSize: 32bit
+MULTISECTIONS: Sections [
+MULTISECTIONS:   Section {
+MULTISECTIONS:     Index: 0
+MULTISECTIONS:     Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS:     Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS:     Address: 0x1FA0
+MULTISECTIONS:     Size: 0x15
+MULTISECTIONS:     Offset: 4000
+MULTISECTIONS:     Alignment: 4
+MULTISECTIONS:     RelocationOffset: 0x0
+MULTISECTIONS:     RelocationCount: 0
+MULTISECTIONS:     Type: 0x0
+MULTISECTIONS:     Attributes [ (0x800004)
+MULTISECTIONS:       PureInstructions (0x800000)
+MULTISECTIONS:       SomeInstructions (0x4)
+MULTISECTIONS:     ]
+MULTISECTIONS:     Reserved1: 0x0
+MULTISECTIONS:     Reserved2: 0x0
+MULTISECTIONS:   }
+MULTISECTIONS:   Section {
+MULTISECTIONS:     Index: 1
+MULTISECTIONS:     Name: __unwind_info (5F 5F 75 6E 77 69 6E 64 5F 69 6E 66 6F 00 00 00)
+MULTISECTIONS:     Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS:     Address: 0x1FB5
+MULTISECTIONS:     Size: 0x48
+MULTISECTIONS:     Offset: 4021
+MULTISECTIONS:     Alignment: 0
+MULTISECTIONS:     RelocationOffset: 0x0
+MULTISECTIONS:     RelocationCount: 0
+MULTISECTIONS:     Type: 0x0
+MULTISECTIONS:     Attributes [ (0x0)
+MULTISECTIONS:     ]
+MULTISECTIONS:     Reserved1: 0x0
+MULTISECTIONS:     Reserved2: 0x0
+MULTISECTIONS:   }
+MULTISECTIONS: ]
+
+MULTIHEADER-ARCHIVE: File: hello.o
+MULTIHEADER-ARCHIVE: Format: Mach-O 64-bit x86-64
+MULTIHEADER-ARCHIVE: Arch: x86_64
+MULTIHEADER-ARCHIVE: AddressSize: 64bit
+MULTIHEADER-ARCHIVE: MachHeader {
+MULTIHEADER-ARCHIVE:   Magic: Magic64 (0xFEEDFACF)
+MULTIHEADER-ARCHIVE:   CpuType: X86-64 (0x1000007)
+MULTIHEADER-ARCHIVE:   CpuSubType: CPU_SUBTYPE_X86_64_ALL (0x3)
+MULTIHEADER-ARCHIVE:   FileType: Relocatable (0x1)
+MULTIHEADER-ARCHIVE:   NumOfLoadCommands: 3
+MULTIHEADER-ARCHIVE:   SizeOfLoadCommands: 496
+MULTIHEADER-ARCHIVE:   Flags [ (0x2000)
+MULTIHEADER-ARCHIVE:     MH_SUBSECTIONS_VIA_SYMBOLS (0x2000)
+MULTIHEADER-ARCHIVE:   ]
+MULTIHEADER-ARCHIVE:   Reserved: 0x0
+MULTIHEADER-ARCHIVE: }
+MULTIHEADER-ARCHIVE: File: foo.o
+MULTIHEADER-ARCHIVE: Format: Mach-O 32-bit i386
+MULTIHEADER-ARCHIVE: Arch: i386
+MULTIHEADER-ARCHIVE: AddressSize: 32bit
+MULTIHEADER-ARCHIVE: MachHeader {
+MULTIHEADER-ARCHIVE:   Magic: Magic (0xFEEDFACE)
+MULTIHEADER-ARCHIVE:   CpuType: X86 (0x7)
+MULTIHEADER-ARCHIVE:   CpuSubType: CPU_SUBTYPE_I386_ALL (0x3)
+MULTIHEADER-ARCHIVE:   FileType: Relocatable (0x1)
+MULTIHEADER-ARCHIVE:   NumOfLoadCommands: 3
+MULTIHEADER-ARCHIVE:   SizeOfLoadCommands: 296
+MULTIHEADER-ARCHIVE:   Flags [ (0x2000)
+MULTIHEADER-ARCHIVE:     MH_SUBSECTIONS_VIA_SYMBOLS (0x2000)
+MULTIHEADER-ARCHIVE:   ]
+MULTIHEADER-ARCHIVE: }
+
+MULTISECTIONS-ARCHIVE: File: hello.o
+MULTISECTIONS-ARCHIVE: Format: Mach-O 64-bit x86-64
+MULTISECTIONS-ARCHIVE: Arch: x86_64
+MULTISECTIONS-ARCHIVE: AddressSize: 64bit
+MULTISECTIONS-ARCHIVE: Sections [
+MULTISECTIONS-ARCHIVE:   Section {
+MULTISECTIONS-ARCHIVE:     Index: 0
+MULTISECTIONS-ARCHIVE:     Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS-ARCHIVE:     Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS-ARCHIVE:     Address: 0x0
+MULTISECTIONS-ARCHIVE:     Size: 0x3B
+MULTISECTIONS-ARCHIVE:     Offset: 528
+MULTISECTIONS-ARCHIVE:     Alignment: 4
+MULTISECTIONS-ARCHIVE:     RelocationOffset: 0x2B8
+MULTISECTIONS-ARCHIVE:     RelocationCount: 2
+MULTISECTIONS-ARCHIVE:     Type: 0x0
+MULTISECTIONS-ARCHIVE:     Attributes [ (0x800004)
+MULTISECTIONS-ARCHIVE:       PureInstructions (0x800000)
+MULTISECTIONS-ARCHIVE:       SomeInstructions (0x4)
+MULTISECTIONS-ARCHIVE:     ]
+MULTISECTIONS-ARCHIVE:     Reserved1: 0x0
+MULTISECTIONS-ARCHIVE:     Reserved2: 0x0
+MULTISECTIONS-ARCHIVE:   }
+MULTISECTIONS-ARCHIVE:   Section {
+MULTISECTIONS-ARCHIVE:     Index: 1
+MULTISECTIONS-ARCHIVE:     Name: __cstring (5F 5F 63 73 74 72 69 6E 67 00 00 00 00 00 00 00)
+MULTISECTIONS-ARCHIVE:     Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS-ARCHIVE:     Address: 0x3B
+MULTISECTIONS-ARCHIVE:     Size: 0xD
+MULTISECTIONS-ARCHIVE:     Offset: 587
+MULTISECTIONS-ARCHIVE:     Alignment: 0
+MULTISECTIONS-ARCHIVE:     RelocationOffset: 0x0
+MULTISECTIONS-ARCHIVE:     RelocationCount: 0
+MULTISECTIONS-ARCHIVE:     Type: ExtReloc (0x2)
+MULTISECTIONS-ARCHIVE:     Attributes [ (0x0)
+MULTISECTIONS-ARCHIVE:     ]
+MULTISECTIONS-ARCHIVE:     Reserved1: 0x0
+MULTISECTIONS-ARCHIVE:     Reserved2: 0x0
+MULTISECTIONS-ARCHIVE:   }
+MULTISECTIONS-ARCHIVE:   Section {
+MULTISECTIONS-ARCHIVE:     Index: 2
+MULTISECTIONS-ARCHIVE:     Name: __compact_unwind (5F 5F 63 6F 6D 70 61 63 74 5F 75 6E 77 69 6E 64)
+MULTISECTIONS-ARCHIVE:     Segment: __LD (5F 5F 4C 44 00 00 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS-ARCHIVE:     Address: 0x48
+MULTISECTIONS-ARCHIVE:     Size: 0x20
+MULTISECTIONS-ARCHIVE:     Offset: 600
+MULTISECTIONS-ARCHIVE:     Alignment: 3
+MULTISECTIONS-ARCHIVE:     RelocationOffset: 0x2C8
+MULTISECTIONS-ARCHIVE:     RelocationCount: 1
+MULTISECTIONS-ARCHIVE:     Type: 0x0
+MULTISECTIONS-ARCHIVE:     Attributes [ (0x20000)
+MULTISECTIONS-ARCHIVE:       Debug (0x20000)
+MULTISECTIONS-ARCHIVE:     ]
+MULTISECTIONS-ARCHIVE:     Reserved1: 0x0
+MULTISECTIONS-ARCHIVE:     Reserved2: 0x0
+MULTISECTIONS-ARCHIVE:   }
+MULTISECTIONS-ARCHIVE:   Section {
+MULTISECTIONS-ARCHIVE:     Index: 3
+MULTISECTIONS-ARCHIVE:     Name: __eh_frame (5F 5F 65 68 5F 66 72 61 6D 65 00 00 00 00 00 00)
+MULTISECTIONS-ARCHIVE:     Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS-ARCHIVE:     Address: 0x68
+MULTISECTIONS-ARCHIVE:     Size: 0x40
+MULTISECTIONS-ARCHIVE:     Offset: 632
+MULTISECTIONS-ARCHIVE:     Alignment: 3
+MULTISECTIONS-ARCHIVE:     RelocationOffset: 0x0
+MULTISECTIONS-ARCHIVE:     RelocationCount: 0
+MULTISECTIONS-ARCHIVE:     Type: 0xB
+MULTISECTIONS-ARCHIVE:     Attributes [ (0x680000)
+MULTISECTIONS-ARCHIVE:       LiveSupport (0x80000)
+MULTISECTIONS-ARCHIVE:       NoTOC (0x400000)
+MULTISECTIONS-ARCHIVE:       StripStaticSyms (0x200000)
+MULTISECTIONS-ARCHIVE:     ]
+MULTISECTIONS-ARCHIVE:     Reserved1: 0x0
+MULTISECTIONS-ARCHIVE:     Reserved2: 0x0
+MULTISECTIONS-ARCHIVE:   }
+MULTISECTIONS-ARCHIVE: ]
+MULTISECTIONS-ARCHIVE: File: foo.o
+MULTISECTIONS-ARCHIVE: Format: Mach-O 32-bit i386
+MULTISECTIONS-ARCHIVE: Arch: i386
+MULTISECTIONS-ARCHIVE: AddressSize: 32bit
+MULTISECTIONS-ARCHIVE: Sections [
+MULTISECTIONS-ARCHIVE:   Section {
+MULTISECTIONS-ARCHIVE:     Index: 0
+MULTISECTIONS-ARCHIVE:     Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS-ARCHIVE:     Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS-ARCHIVE:     Address: 0x0
+MULTISECTIONS-ARCHIVE:     Size: 0x5
+MULTISECTIONS-ARCHIVE:     Offset: 324
+MULTISECTIONS-ARCHIVE:     Alignment: 4
+MULTISECTIONS-ARCHIVE:     RelocationOffset: 0x0
+MULTISECTIONS-ARCHIVE:     RelocationCount: 0
+MULTISECTIONS-ARCHIVE:     Type: 0x0
+MULTISECTIONS-ARCHIVE:     Attributes [ (0x800004)
+MULTISECTIONS-ARCHIVE:       PureInstructions (0x800000)
+MULTISECTIONS-ARCHIVE:       SomeInstructions (0x4)
+MULTISECTIONS-ARCHIVE:     ]
+MULTISECTIONS-ARCHIVE:     Reserved1: 0x0
+MULTISECTIONS-ARCHIVE:     Reserved2: 0x0
+MULTISECTIONS-ARCHIVE:   }
+MULTISECTIONS-ARCHIVE:   Section {
+MULTISECTIONS-ARCHIVE:     Index: 1
+MULTISECTIONS-ARCHIVE:     Name: __data (5F 5F 64 61 74 61 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS-ARCHIVE:     Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00)
+MULTISECTIONS-ARCHIVE:     Address: 0x8
+MULTISECTIONS-ARCHIVE:     Size: 0x4
+MULTISECTIONS-ARCHIVE:     Offset: 332
+MULTISECTIONS-ARCHIVE:     Alignment: 2
+MULTISECTIONS-ARCHIVE:     RelocationOffset: 0x0
+MULTISECTIONS-ARCHIVE:     RelocationCount: 0
+MULTISECTIONS-ARCHIVE:     Type: 0x0
+MULTISECTIONS-ARCHIVE:     Attributes [ (0x0)
+MULTISECTIONS-ARCHIVE:     ]
+MULTISECTIONS-ARCHIVE:     Reserved1: 0x0
+MULTISECTIONS-ARCHIVE:     Reserved2: 0x0
+MULTISECTIONS-ARCHIVE:   }
+MULTISECTIONS-ARCHIVE: ]
+
diff --git a/test/tools/llvm-readobj/mips-abiflags.test b/test/tools/llvm-readobj/mips-abiflags.test
new file mode 100644
index 000000000000..b4c769be2073
--- /dev/null
+++ b/test/tools/llvm-readobj/mips-abiflags.test
@@ -0,0 +1,42 @@
+RUN: llvm-readobj -mips-abi-flags %p/Inputs/abiflags.obj.elf-mipsel | \
+RUN:   FileCheck -check-prefix=EL64 %s
+RUN: llvm-readobj -mips-abi-flags %p/Inputs/abiflags.obj.elf-mips | \
+RUN:   FileCheck -check-prefix=BE32 %s
+
+EL64:      MIPS ABI Flags {
+EL64-NEXT:   Version: 0
+EL64-NEXT:   ISA: MIPS64r5
+EL64-NEXT:   ISA Extension: Cavium Networks Octeon3 (0x13)
+EL64-NEXT:   ASEs [ (0x103)
+EL64-NEXT:     DSP (0x1)
+EL64-NEXT:     DSPR2 (0x2)
+EL64-NEXT:     VZ (0x100)
+EL64-NEXT:   ]
+EL64-NEXT:   FP ABI: Hard float (double precision) (0x1)
+EL64-NEXT:   GPR size: 64
+EL64-NEXT:   CPR1 size: 64
+EL64-NEXT:   CPR2 size: 0
+EL64-NEXT:   Flags 1 [ (0x1)
+EL64-NEXT:     ODDSPREG (0x1)
+EL64-NEXT:   ]
+EL64-NEXT:   Flags 2: 0x0
+EL64-NEXT: }
+
+BE32:      MIPS ABI Flags {
+BE32-NEXT:   Version: 0
+BE32-NEXT:   ISA: MIPS32r2
+BE32-NEXT:   ISA Extension: None (0x0)
+BE32-NEXT:   ASEs [ (0x803)
+BE32-NEXT:     DSP (0x1)
+BE32-NEXT:     DSPR2 (0x2)
+BE32-NEXT:     microMIPS (0x800)
+BE32-NEXT:   ]
+BE32-NEXT:   FP ABI: Soft float (0x3)
+BE32-NEXT:   GPR size: 32
+BE32-NEXT:   CPR1 size: 0
+BE32-NEXT:   CPR2 size: 0
+BE32-NEXT:   Flags 1 [ (0x1)
+BE32-NEXT:     ODDSPREG (0x1)
+BE32-NEXT:   ]
+BE32-NEXT:   Flags 2: 0x0
+BE32-NEXT: }
diff --git a/test/tools/llvm-readobj/mips-options.test b/test/tools/llvm-readobj/mips-options.test
new file mode 100644
index 000000000000..7a2959dd0325
--- /dev/null
+++ b/test/tools/llvm-readobj/mips-options.test
@@ -0,0 +1,22 @@
+# Check DT_MIPS_OPTIONS .dynamic section tag reading
+
+RUN: llvm-readobj -dynamic-table %p/Inputs/mips-options.elf-mips64el | \
+RUN:   FileCheck %s
+
+CHECK:      DynamicSection [ (14 entries)
+CHECK-NEXT:   Tag                Type                 Name/Value
+CHECK-NEXT:   0x0000000000000004 HASH                 0x158
+CHECK-NEXT:   0x0000000000000005 STRTAB               0x1C0
+CHECK-NEXT:   0x0000000000000006 SYMTAB               0x178
+CHECK-NEXT:   0x000000000000000A STRSZ                7 (bytes)
+CHECK-NEXT:   0x000000000000000B SYMENT               24 (bytes)
+CHECK-NEXT:   0x0000000070000001 MIPS_RLD_VERSION     1
+CHECK-NEXT:   0x0000000070000005 MIPS_FLAGS           NOTPOT 
+CHECK-NEXT:   0x0000000070000006 MIPS_BASE_ADDRESS    0x0
+CHECK-NEXT:   0x000000007000000A MIPS_LOCAL_GOTNO     2
+CHECK-NEXT:   0x0000000070000011 MIPS_SYMTABNO        3
+CHECK-NEXT:   0x0000000070000013 MIPS_GOTSYM          0x3
+CHECK-NEXT:   0x0000000000000003 PLTGOT               0x2000
+CHECK-NEXT:   0x0000000070000029 MIPS_OPTIONS         0x1000
+CHECK-NEXT:   0x0000000000000000 NULL                 0x0
+CHECK-NEXT: ]
diff --git a/test/tools/llvm-readobj/program-headers.test b/test/tools/llvm-readobj/program-headers.test
index f014c0390420..8e8855d8b8e8 100644
--- a/test/tools/llvm-readobj/program-headers.test
+++ b/test/tools/llvm-readobj/program-headers.test
@@ -83,10 +83,22 @@ ELF-MIPS-NEXT: AddressSize: 32bit
 ELF-MIPS-NEXT: LoadName:
 ELF-MIPS-NEXT: ProgramHeaders [
 ELF-MIPS-NEXT:   ProgramHeader {
+ELF-MIPS-NEXT:     Type: PT_MIPS_ABIFLAGS (0x70000003)
+ELF-MIPS-NEXT:     Offset: 0x98
+ELF-MIPS-NEXT:     VirtualAddress: 0x400098
+ELF-MIPS-NEXT:     PhysicalAddress: 0x400098
+ELF-MIPS-NEXT:     FileSize: 24
+ELF-MIPS-NEXT:     MemSize: 24
+ELF-MIPS-NEXT:     Flags [ (0x4)
+ELF-MIPS-NEXT:       PF_R (0x4)
+ELF-MIPS-NEXT:     ]
+ELF-MIPS-NEXT:     Alignment: 8
+ELF-MIPS-NEXT:   }
+ELF-MIPS-NEXT:   ProgramHeader {
 ELF-MIPS-NEXT:     Type: PT_MIPS_REGINFO (0x70000000)
-ELF-MIPS-NEXT:     Offset: 0x74
-ELF-MIPS-NEXT:     VirtualAddress: 0x400074
-ELF-MIPS-NEXT:     PhysicalAddress: 0x400074
+ELF-MIPS-NEXT:     Offset: 0xB0
+ELF-MIPS-NEXT:     VirtualAddress: 0x4000B0
+ELF-MIPS-NEXT:     PhysicalAddress: 0x4000B0
 ELF-MIPS-NEXT:     FileSize: 24
 ELF-MIPS-NEXT:     MemSize: 24
 ELF-MIPS-NEXT:     Flags [ (0x4)
@@ -99,8 +111,8 @@ ELF-MIPS-NEXT:     Type: PT_LOAD (0x1)
 ELF-MIPS-NEXT:     Offset: 0x0
 ELF-MIPS-NEXT:     VirtualAddress: 0x400000
 ELF-MIPS-NEXT:     PhysicalAddress: 0x400000
-ELF-MIPS-NEXT:     FileSize: 160
-ELF-MIPS-NEXT:     MemSize: 160
+ELF-MIPS-NEXT:     FileSize: 224
+ELF-MIPS-NEXT:     MemSize: 224
 ELF-MIPS-NEXT:     Flags [ (0x5)
 ELF-MIPS-NEXT:       PF_R (0x4)
 ELF-MIPS-NEXT:       PF_X (0x1)
diff --git a/test/tools/llvm-symbolizer/pdb/Inputs/test.cpp b/test/tools/llvm-symbolizer/pdb/Inputs/test.cpp
new file mode 100644
index 000000000000..f1f98af41907
--- /dev/null
+++ b/test/tools/llvm-symbolizer/pdb/Inputs/test.cpp
@@ -0,0 +1,18 @@
+// To generate the corresponding EXE/PDB, run:
+// cl /Zi test.cpp
+
+namespace NS {
+struct Foo {
+  void bar() {}
+};
+}
+
+void foo() {
+}
+
+int main() {
+  foo();
+  
+  NS::Foo f;
+  f.bar();
+}
diff --git a/test/tools/llvm-symbolizer/pdb/Inputs/test.exe b/test/tools/llvm-symbolizer/pdb/Inputs/test.exe
new file mode 100644
index 000000000000..80fb34bb6dcb
--- /dev/null
+++ b/test/tools/llvm-symbolizer/pdb/Inputs/test.exe
diff --git a/test/tools/llvm-symbolizer/pdb/Inputs/test.exe.input b/test/tools/llvm-symbolizer/pdb/Inputs/test.exe.input
new file mode 100644
index 000000000000..affda60449b2
--- /dev/null
+++ b/test/tools/llvm-symbolizer/pdb/Inputs/test.exe.input
@@ -0,0 +1,4 @@
+0x401030
+0x401040
+0x401060
+0x500000
diff --git a/test/tools/llvm-symbolizer/pdb/Inputs/test.pdb b/test/tools/llvm-symbolizer/pdb/Inputs/test.pdb
new file mode 100644
index 000000000000..974e565e87f4
--- /dev/null
+++ b/test/tools/llvm-symbolizer/pdb/Inputs/test.pdb
diff --git a/test/tools/llvm-symbolizer/pdb/lit.local.cfg b/test/tools/llvm-symbolizer/pdb/lit.local.cfg
new file mode 100644
index 000000000000..8c58f1666400
--- /dev/null
+++ b/test/tools/llvm-symbolizer/pdb/lit.local.cfg
@@ -0,0 +1 @@
+config.unsupported = not config.have_dia_sdk

diff --git a/test/tools/llvm-symbolizer/pdb/pdb.test b/test/tools/llvm-symbolizer/pdb/pdb.test
new file mode 100644
index 000000000000..b5d0f15fbcb8
--- /dev/null
+++ b/test/tools/llvm-symbolizer/pdb/pdb.test
@@ -0,0 +1,18 @@
+RUN: llvm-symbolizer -obj="%p/Inputs/test.exe" < "%p/Inputs/test.exe.input" | \

+RUN:    FileCheck %s --check-prefix=CHECK

+RUN: llvm-symbolizer -obj="%p/Inputs/test.exe" -demangle=false < \

+RUN:    "%p/Inputs/test.exe.input" | FileCheck %s --check-prefix=CHECK-NO-DEMANGLE

+

+CHECK: foo(void)

+CHECK-NEXT: test.cpp:10

+CHECK: _main

+CHECK-NEXT: test.cpp:13:0

+CHECK: NS::Foo::bar(void)

+CHECK-NEXT: test.cpp:6:0

+

+CHECK-NO-DEMANGLE: foo

+CHECK-NO-DEMANGLE-NEXT: test.cpp:10

+CHECK-NO-DEMANGLE: _main

+CHECK-LINKAGE-NAME-NEXT: test.cpp:13:0

+CHECK-NO-DEMANGLE: bar

+CHECK-LINKAGE-NAME-NEXT: test.cpp:6:0

diff --git a/test/tools/llvm-vtabledump/trivial.test b/test/tools/llvm-vtabledump/trivial.test
deleted file mode 100644
index 92bd058cfb18..000000000000
--- a/test/tools/llvm-vtabledump/trivial.test
+++ /dev/null
@@ -1,58 +0,0 @@
-RUN: llvm-vtabledump %p/Inputs/trivial.obj.coff-i386 \
-RUN:   | FileCheck %s --check-prefix=COFF-I386
-
-RUN: llvm-vtabledump %p/Inputs/trivial.obj.elf-i386 \
-RUN:   | FileCheck %s --check-prefix=ELF-I386
-
-COFF-I386:      ??_7S@@6B@[0]: ??_R4S@@6B@
-COFF-I386-NEXT: ??_7S@@6B@[4]: ??_GS@@UAEPAXI@Z
-COFF-I386-NEXT: ??_8S@@7B@[0]: -4
-COFF-I386-NEXT: ??_8S@@7B@[4]: 4
-COFF-I386-NEXT: ??_R4S@@6B@[IsImageRelative]: 0
-COFF-I386-NEXT: ??_R4S@@6B@[OffsetToTop]: 0
-COFF-I386-NEXT: ??_R4S@@6B@[VFPtrOffset]: 0
-COFF-I386-NEXT: ??_R4S@@6B@[TypeDescriptor]: ??_R0?AUS@@@8
-COFF-I386-NEXT: ??_R4S@@6B@[ClassHierarchyDescriptor]: ??_R3S@@8
-COFF-I386-NEXT: ??_R3A@@8[AlwaysZero]: 0
-COFF-I386-NEXT: ??_R3A@@8[Flags]: 0
-COFF-I386-NEXT: ??_R3A@@8[NumClasses]: 1
-COFF-I386-NEXT: ??_R3A@@8[BaseClassArray]: ??_R2A@@8
-COFF-I386-NEXT: ??_R3S@@8[AlwaysZero]: 0
-COFF-I386-NEXT: ??_R3S@@8[Flags]: 0
-COFF-I386-NEXT: ??_R3S@@8[NumClasses]: 2
-COFF-I386-NEXT: ??_R3S@@8[BaseClassArray]: ??_R2S@@8
-COFF-I386-NEXT: ??_R2A@@8[0]: ??_R1A@?0A@EA@A@@8
-COFF-I386-NEXT: ??_R2S@@8[0]: ??_R1A@?0A@EA@S@@8
-COFF-I386-NEXT: ??_R2S@@8[4]: ??_R1A@33FA@A@@8
-COFF-I386-NEXT: ??_R1A@33FA@A@@8[TypeDescriptor]: ??_R0?AUA@@@8
-COFF-I386-NEXT: ??_R1A@33FA@A@@8[NumBases]: 0
-COFF-I386-NEXT: ??_R1A@33FA@A@@8[OffsetInVBase]: 0
-COFF-I386-NEXT: ??_R1A@33FA@A@@8[VBPtrOffset]: 4
-COFF-I386-NEXT: ??_R1A@33FA@A@@8[OffsetInVBTable]: 4
-COFF-I386-NEXT: ??_R1A@33FA@A@@8[Flags]: 80
-COFF-I386-NEXT: ??_R1A@33FA@A@@8[ClassHierarchyDescriptor]: ??_R3A@@8
-COFF-I386-NEXT: ??_R1A@?0A@EA@A@@8[TypeDescriptor]: ??_R0?AUA@@@8
-COFF-I386-NEXT: ??_R1A@?0A@EA@A@@8[NumBases]: 0
-COFF-I386-NEXT: ??_R1A@?0A@EA@A@@8[OffsetInVBase]: 0
-COFF-I386-NEXT: ??_R1A@?0A@EA@A@@8[VBPtrOffset]: -1
-COFF-I386-NEXT: ??_R1A@?0A@EA@A@@8[OffsetInVBTable]: 0
-COFF-I386-NEXT: ??_R1A@?0A@EA@A@@8[Flags]: 64
-COFF-I386-NEXT: ??_R1A@?0A@EA@A@@8[ClassHierarchyDescriptor]: ??_R3A@@8
-COFF-I386-NEXT: ??_R1A@?0A@EA@S@@8[TypeDescriptor]: ??_R0?AUS@@@8
-COFF-I386-NEXT: ??_R1A@?0A@EA@S@@8[NumBases]: 1
-COFF-I386-NEXT: ??_R1A@?0A@EA@S@@8[OffsetInVBase]: 0
-COFF-I386-NEXT: ??_R1A@?0A@EA@S@@8[VBPtrOffset]: -1
-COFF-I386-NEXT: ??_R1A@?0A@EA@S@@8[OffsetInVBTable]: 0
-COFF-I386-NEXT: ??_R1A@?0A@EA@S@@8[Flags]: 64
-COFF-I386-NEXT: ??_R1A@?0A@EA@S@@8[ClassHierarchyDescriptor]: ??_R3S@@8
-COFF-I386-NEXT: ??_R0?AUA@@@8[VFPtr]: ??_7type_info@@6B@
-COFF-I386-NEXT: ??_R0?AUA@@@8[AlwaysZero]: 0
-COFF-I386-NEXT: ??_R0?AUA@@@8[MangledName]: .?AUA@@
-COFF-I386-NEXT: ??_R0?AUS@@@8[VFPtr]: ??_7type_info@@6B@
-COFF-I386-NEXT: ??_R0?AUS@@@8[AlwaysZero]: 0
-COFF-I386-NEXT: ??_R0?AUS@@@8[MangledName]: .?AUS@@
-
-ELF-I386:      _ZTS1A: 1A
-ELF-I386-NEXT: _ZTV1A[0]: 0
-ELF-I386-NEXT: _ZTV1A[4]: _ZTI1A
-ELF-I386-NEXT: _ZTV1A[8]: _ZN1A1fEv
diff --git a/test/tools/lto/lit.local.cfg b/test/tools/lto/lit.local.cfg
new file mode 100644
index 000000000000..b91f8f4de9a6
--- /dev/null
+++ b/test/tools/lto/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'ld64_plugin' in config.available_features:
+   config.unsupported = True
diff --git a/test/tools/lto/opt-level.ll b/test/tools/lto/opt-level.ll
new file mode 100644
index 000000000000..013a1f408821
--- /dev/null
+++ b/test/tools/lto/opt-level.ll
@@ -0,0 +1,20 @@
+; RUN: llvm-as %s -o %t.o
+; RUN: env DYLD_LIBRARY_PATH=%llvmshlibdir %ld64 -arch x86_64 -dylib -mllvm -O0 -o %t.dylib %t.o
+; RUN: llvm-nm -no-llvm-bc %t.dylib | FileCheck --check-prefix=CHECK-O0 %s
+; RUN: env DYLD_LIBRARY_PATH=%llvmshlibdir %ld64 -arch x86_64 -dylib -mllvm -O2 -o %t.dylib %t.o
+; RUN: llvm-nm -no-llvm-bc %t.dylib | FileCheck --check-prefix=CHECK-O2 %s
+
+target triple = "x86_64-apple-macosx10.8.0"
+
+; CHECK-O0: t _f1
+; CHECK-O2-NOT: _f1
+define internal void @f1() {
+  ret void
+}
+
+; CHECK-O0: T _f2
+; CHECK-O2: T _f2
+define void @f2() {
+  call void @f1()
+  ret void
+}